diff --git a/CMakeLists.txt b/CMakeLists.txt index e1be6eb..0fcce61 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -5,7 +5,7 @@ cmake_minimum_required(VERSION 2.6) set(MCU "atmega328p" ) set(CPU_SPEED "16000000" ) -set(PORT "/dev/ttyUSB1") +set(PORT "/dev/ttyUSB0") set(PORT_SPEED "57600") set(PIN_VARIANT "standard") set(ARDUINO_PATH "arduino") diff --git a/arduino/hardware/tools/avr/avr/bin/ar b/arduino/hardware/tools/avr/avr/bin/ar deleted file mode 100755 index 1184a71..0000000 Binary files a/arduino/hardware/tools/avr/avr/bin/ar and /dev/null differ diff --git a/arduino/hardware/tools/avr/avr/bin/as b/arduino/hardware/tools/avr/avr/bin/as deleted file mode 100755 index 51f2cfc..0000000 Binary files a/arduino/hardware/tools/avr/avr/bin/as and /dev/null differ diff --git a/arduino/hardware/tools/avr/avr/bin/ld b/arduino/hardware/tools/avr/avr/bin/ld deleted file mode 100755 index 147bbe1..0000000 Binary files a/arduino/hardware/tools/avr/avr/bin/ld and /dev/null differ diff --git a/arduino/hardware/tools/avr/avr/bin/ld.bfd b/arduino/hardware/tools/avr/avr/bin/ld.bfd deleted file mode 100755 index 147bbe1..0000000 Binary files a/arduino/hardware/tools/avr/avr/bin/ld.bfd and /dev/null differ diff --git a/arduino/hardware/tools/avr/avr/bin/nm b/arduino/hardware/tools/avr/avr/bin/nm deleted file mode 100755 index 3b428f3..0000000 Binary files a/arduino/hardware/tools/avr/avr/bin/nm and /dev/null differ diff --git a/arduino/hardware/tools/avr/avr/bin/objcopy b/arduino/hardware/tools/avr/avr/bin/objcopy deleted file mode 100755 index 214835b..0000000 Binary files a/arduino/hardware/tools/avr/avr/bin/objcopy and /dev/null differ diff --git a/arduino/hardware/tools/avr/avr/bin/objdump b/arduino/hardware/tools/avr/avr/bin/objdump deleted file mode 100755 index 421786b..0000000 Binary files a/arduino/hardware/tools/avr/avr/bin/objdump and /dev/null differ diff --git a/arduino/hardware/tools/avr/avr/bin/ranlib b/arduino/hardware/tools/avr/avr/bin/ranlib deleted file mode 100755 index ac629f3..0000000 Binary files a/arduino/hardware/tools/avr/avr/bin/ranlib and /dev/null differ diff --git a/arduino/hardware/tools/avr/avr/bin/readelf b/arduino/hardware/tools/avr/avr/bin/readelf deleted file mode 100755 index af419b1..0000000 Binary files a/arduino/hardware/tools/avr/avr/bin/readelf and /dev/null differ diff --git a/arduino/hardware/tools/avr/avr/bin/strip b/arduino/hardware/tools/avr/avr/bin/strip deleted file mode 100755 index e40c50f..0000000 Binary files a/arduino/hardware/tools/avr/avr/bin/strip and /dev/null differ diff --git a/arduino/hardware/tools/avr/avr/include/alloca.h b/arduino/hardware/tools/avr/avr/include/alloca.h deleted file mode 100644 index a213c0c..0000000 --- a/arduino/hardware/tools/avr/avr/include/alloca.h +++ /dev/null @@ -1,59 +0,0 @@ -/* Copyright (c) 2007, Dmitry Xmelkov - All rights reserved. - - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - * Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - * Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in - the documentation and/or other materials provided with the - distribution. - * Neither the name of the copyright holders nor the names of - contributors may be used to endorse or promote products derived - from this software without specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. */ - -/* $Id$ */ - -#ifndef _ALLOCA_H -#define _ALLOCA_H 1 - -#include - -/** \defgroup alloca : Allocate space in the stack */ - -/** \ingroup alloca - \brief Allocate \a __size bytes of space in the stack frame of the caller. - - This temporary space is automatically freed when the function that - called alloca() returns to its caller. Avr-libc defines the alloca() as - a macro, which is translated into the inlined \c __builtin_alloca() - function. The fact that the code is inlined, means that it is impossible - to take the address of this function, or to change its behaviour by - linking with a different library. - - \return alloca() returns a pointer to the beginning of the allocated - space. If the allocation causes stack overflow, program behaviour is - undefined. - - \warning Avoid use alloca() inside the list of arguments of a function - call. - */ -extern void *alloca (size_t __size); - -#define alloca(size) __builtin_alloca (size) - -#endif /* alloca.h */ diff --git a/arduino/hardware/tools/avr/avr/include/assert.h b/arduino/hardware/tools/avr/avr/include/assert.h deleted file mode 100644 index 9ae1cc6..0000000 --- a/arduino/hardware/tools/avr/avr/include/assert.h +++ /dev/null @@ -1,120 +0,0 @@ -/* Copyright (c) 2005,2007 Joerg Wunsch - All rights reserved. - - Portions of documentation Copyright (c) 1991, 1993 - The Regents of the University of California. - - All rights reserved. - - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - * Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - * Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in - the documentation and/or other materials provided with the - distribution. - - * Neither the name of the copyright holders nor the names of - contributors may be used to endorse or promote products derived - from this software without specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - - $Id$ -*/ - -/** \file */ -/** \defgroup avr_assert : Diagnostics - \code #include \endcode - - This header file defines a debugging aid. - - As there is no standard error output stream available for many - applications using this library, the generation of a printable - error message is not enabled by default. These messages will - only be generated if the application defines the macro - - \code __ASSERT_USE_STDERR \endcode - - before including the \c header file. By default, - only abort() will be called to halt the application. -*/ - -/*@{*/ - -/* - * The ability to include this file (with or without NDEBUG) is a - * feature. - */ - -#undef assert - -#include - -#if defined(__DOXYGEN__) -/** - * \def assert - * \param expression Expression to test for. - * - * The assert() macro tests the given expression and if it is false, - * the calling process is terminated. A diagnostic message is written - * to stderr and the function abort() is called, effectively - * terminating the program. - * - * If expression is true, the assert() macro does nothing. - * - * The assert() macro may be removed at compile time by defining - * NDEBUG as a macro (e.g., by using the compiler option -DNDEBUG). - */ -# define assert(expression) - -#else /* !DOXYGEN */ - -# if defined(NDEBUG) -# define assert(e) ((void)0) -# else /* !NDEBUG */ -# if defined(__ASSERT_USE_STDERR) -# define assert(e) ((e) ? (void)0 : \ - __assert(__func__, __FILE__, __LINE__, #e)) -# else /* !__ASSERT_USE_STDERR */ -# define assert(e) ((e) ? (void)0 : abort()) -# endif /* __ASSERT_USE_STDERR */ -# endif /* NDEBUG */ -#endif /* DOXYGEN */ - -#if (defined __STDC_VERSION__ && __STDC_VERSION__ >= 201112L) || \ - ((_GNUC_ > 4 || (_GNUC_ == 4 && _GNUC_MINOR_ >= 6)) && !defined __cplusplus) -# undef static_assert -# define static_assert _Static_assert -#endif - -#ifdef __cplusplus -extern "C" { -#endif - -#if !defined(__DOXYGEN__) - -extern void __assert(const char *__func, const char *__file, - int __lineno, const char *__sexp); - -#endif /* not __DOXYGEN__ */ - -#ifdef __cplusplus -} -#endif - -/*@}*/ -/* EOF */ diff --git a/arduino/hardware/tools/avr/avr/include/avr/boot.h b/arduino/hardware/tools/avr/avr/include/avr/boot.h deleted file mode 100644 index eed5729..0000000 --- a/arduino/hardware/tools/avr/avr/include/avr/boot.h +++ /dev/null @@ -1,684 +0,0 @@ -/* Copyright (c) 2002,2003,2004,2005,2006,2007,2008,2009 Eric B. Weddington - All rights reserved. - - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - * Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - * Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in - the documentation and/or other materials provided with the - distribution. - * Neither the name of the copyright holders nor the names of - contributors may be used to endorse or promote products derived - from this software without specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. */ - -/* $Id$ */ - -#ifndef _AVR_BOOT_H_ -#define _AVR_BOOT_H_ 1 - -/** \file */ -/** \defgroup avr_boot : Bootloader Support Utilities - \code - #include - #include - \endcode - - The macros in this module provide a C language interface to the - bootloader support functionality of certain AVR processors. These - macros are designed to work with all sizes of flash memory. - - Global interrupts are not automatically disabled for these macros. It - is left up to the programmer to do this. See the code example below. - Also see the processor datasheet for caveats on having global interrupts - enabled during writing of the Flash. - - \note Not all AVR processors provide bootloader support. See your - processor datasheet to see if it provides bootloader support. - - \todo From email with Marek: On smaller devices (all except ATmega64/128), - __SPM_REG is in the I/O space, accessible with the shorter "in" and "out" - instructions - since the boot loader has a limited size, this could be an - important optimization. - - \par API Usage Example - The following code shows typical usage of the boot API. - - \code - #include - #include - #include - - void boot_program_page (uint32_t page, uint8_t *buf) - { - uint16_t i; - uint8_t sreg; - - // Disable interrupts. - - sreg = SREG; - cli(); - - eeprom_busy_wait (); - - boot_page_erase (page); - boot_spm_busy_wait (); // Wait until the memory is erased. - - for (i=0; i -#include -#include -#include - -/* Check for SPM Control Register in processor. */ -#if defined (SPMCSR) -# define __SPM_REG SPMCSR -#else -# if defined (SPMCR) -# define __SPM_REG SPMCR -# else -# error AVR processor does not provide bootloader support! -# endif -#endif - - -/* Check for SPM Enable bit. */ -#if defined(SPMEN) -# define __SPM_ENABLE SPMEN -#elif defined(SELFPRGEN) -# define __SPM_ENABLE SELFPRGEN -#else -# error Cannot find SPM Enable bit definition! -#endif - -/** \ingroup avr_boot - \def BOOTLOADER_SECTION - - Used to declare a function or variable to be placed into a - new section called .bootloader. This section and its contents - can then be relocated to any address (such as the bootloader - NRWW area) at link-time. */ - -#define BOOTLOADER_SECTION __attribute__ ((section (".bootloader"))) - -#ifndef __DOXYGEN__ -/* Create common bit definitions. */ -#ifdef ASB -#define __COMMON_ASB ASB -#else -#define __COMMON_ASB RWWSB -#endif - -#ifdef ASRE -#define __COMMON_ASRE ASRE -#else -#define __COMMON_ASRE RWWSRE -#endif - -/* Define the bit positions of the Boot Lock Bits. */ - -#define BLB12 5 -#define BLB11 4 -#define BLB02 3 -#define BLB01 2 -#endif /* __DOXYGEN__ */ - -/** \ingroup avr_boot - \def boot_spm_interrupt_enable() - Enable the SPM interrupt. */ - -#define boot_spm_interrupt_enable() (__SPM_REG |= (uint8_t)_BV(SPMIE)) - -/** \ingroup avr_boot - \def boot_spm_interrupt_disable() - Disable the SPM interrupt. */ - -#define boot_spm_interrupt_disable() (__SPM_REG &= (uint8_t)~_BV(SPMIE)) - -/** \ingroup avr_boot - \def boot_is_spm_interrupt() - Check if the SPM interrupt is enabled. */ - -#define boot_is_spm_interrupt() (__SPM_REG & (uint8_t)_BV(SPMIE)) - -/** \ingroup avr_boot - \def boot_rww_busy() - Check if the RWW section is busy. */ - -#define boot_rww_busy() (__SPM_REG & (uint8_t)_BV(__COMMON_ASB)) - -/** \ingroup avr_boot - \def boot_spm_busy() - Check if the SPM instruction is busy. */ - -#define boot_spm_busy() (__SPM_REG & (uint8_t)_BV(__SPM_ENABLE)) - -/** \ingroup avr_boot - \def boot_spm_busy_wait() - Wait while the SPM instruction is busy. */ - -#define boot_spm_busy_wait() do{}while(boot_spm_busy()) - -#ifndef __DOXYGEN__ -#define __BOOT_PAGE_ERASE (_BV(__SPM_ENABLE) | _BV(PGERS)) -#define __BOOT_PAGE_WRITE (_BV(__SPM_ENABLE) | _BV(PGWRT)) -#define __BOOT_PAGE_FILL _BV(__SPM_ENABLE) -#define __BOOT_RWW_ENABLE (_BV(__SPM_ENABLE) | _BV(__COMMON_ASRE)) -#if defined(BLBSET) -#define __BOOT_LOCK_BITS_SET (_BV(__SPM_ENABLE) | _BV(BLBSET)) -#elif defined(RFLB) /* Some devices have RFLB defined instead of BLBSET. */ -#define __BOOT_LOCK_BITS_SET (_BV(__SPM_ENABLE) | _BV(RFLB)) -#endif - -#define __boot_page_fill_normal(address, data) \ -(__extension__({ \ - __asm__ __volatile__ \ - ( \ - "movw r0, %3\n\t" \ - "sts %0, %1\n\t" \ - "spm\n\t" \ - "clr r1\n\t" \ - : \ - : "i" (_SFR_MEM_ADDR(__SPM_REG)), \ - "r" ((uint8_t)(__BOOT_PAGE_FILL)), \ - "z" ((uint16_t)(address)), \ - "r" ((uint16_t)(data)) \ - : "r0" \ - ); \ -})) - -#define __boot_page_fill_alternate(address, data)\ -(__extension__({ \ - __asm__ __volatile__ \ - ( \ - "movw r0, %3\n\t" \ - "sts %0, %1\n\t" \ - "spm\n\t" \ - ".word 0xffff\n\t" \ - "nop\n\t" \ - "clr r1\n\t" \ - : \ - : "i" (_SFR_MEM_ADDR(__SPM_REG)), \ - "r" ((uint8_t)(__BOOT_PAGE_FILL)), \ - "z" ((uint16_t)(address)), \ - "r" ((uint16_t)(data)) \ - : "r0" \ - ); \ -})) - -#define __boot_page_fill_extended(address, data) \ -(__extension__({ \ - __asm__ __volatile__ \ - ( \ - "movw r0, %4\n\t" \ - "movw r30, %A3\n\t" \ - "sts %1, %C3\n\t" \ - "sts %0, %2\n\t" \ - "spm\n\t" \ - "clr r1\n\t" \ - : \ - : "i" (_SFR_MEM_ADDR(__SPM_REG)), \ - "i" (_SFR_MEM_ADDR(RAMPZ)), \ - "r" ((uint8_t)(__BOOT_PAGE_FILL)), \ - "r" ((uint32_t)(address)), \ - "r" ((uint16_t)(data)) \ - : "r0", "r30", "r31" \ - ); \ -})) - -#define __boot_page_erase_normal(address) \ -(__extension__({ \ - __asm__ __volatile__ \ - ( \ - "sts %0, %1\n\t" \ - "spm\n\t" \ - : \ - : "i" (_SFR_MEM_ADDR(__SPM_REG)), \ - "r" ((uint8_t)(__BOOT_PAGE_ERASE)), \ - "z" ((uint16_t)(address)) \ - ); \ -})) - -#define __boot_page_erase_alternate(address) \ -(__extension__({ \ - __asm__ __volatile__ \ - ( \ - "sts %0, %1\n\t" \ - "spm\n\t" \ - ".word 0xffff\n\t" \ - "nop\n\t" \ - : \ - : "i" (_SFR_MEM_ADDR(__SPM_REG)), \ - "r" ((uint8_t)(__BOOT_PAGE_ERASE)), \ - "z" ((uint16_t)(address)) \ - ); \ -})) - -#define __boot_page_erase_extended(address) \ -(__extension__({ \ - __asm__ __volatile__ \ - ( \ - "movw r30, %A3\n\t" \ - "sts %1, %C3\n\t" \ - "sts %0, %2\n\t" \ - "spm\n\t" \ - : \ - : "i" (_SFR_MEM_ADDR(__SPM_REG)), \ - "i" (_SFR_MEM_ADDR(RAMPZ)), \ - "r" ((uint8_t)(__BOOT_PAGE_ERASE)), \ - "r" ((uint32_t)(address)) \ - : "r30", "r31" \ - ); \ -})) - -#define __boot_page_write_normal(address) \ -(__extension__({ \ - __asm__ __volatile__ \ - ( \ - "sts %0, %1\n\t" \ - "spm\n\t" \ - : \ - : "i" (_SFR_MEM_ADDR(__SPM_REG)), \ - "r" ((uint8_t)(__BOOT_PAGE_WRITE)), \ - "z" ((uint16_t)(address)) \ - ); \ -})) - -#define __boot_page_write_alternate(address) \ -(__extension__({ \ - __asm__ __volatile__ \ - ( \ - "sts %0, %1\n\t" \ - "spm\n\t" \ - ".word 0xffff\n\t" \ - "nop\n\t" \ - : \ - : "i" (_SFR_MEM_ADDR(__SPM_REG)), \ - "r" ((uint8_t)(__BOOT_PAGE_WRITE)), \ - "z" ((uint16_t)(address)) \ - ); \ -})) - -#define __boot_page_write_extended(address) \ -(__extension__({ \ - __asm__ __volatile__ \ - ( \ - "movw r30, %A3\n\t" \ - "sts %1, %C3\n\t" \ - "sts %0, %2\n\t" \ - "spm\n\t" \ - : \ - : "i" (_SFR_MEM_ADDR(__SPM_REG)), \ - "i" (_SFR_MEM_ADDR(RAMPZ)), \ - "r" ((uint8_t)(__BOOT_PAGE_WRITE)), \ - "r" ((uint32_t)(address)) \ - : "r30", "r31" \ - ); \ -})) - -#define __boot_rww_enable() \ -(__extension__({ \ - __asm__ __volatile__ \ - ( \ - "sts %0, %1\n\t" \ - "spm\n\t" \ - : \ - : "i" (_SFR_MEM_ADDR(__SPM_REG)), \ - "r" ((uint8_t)(__BOOT_RWW_ENABLE)) \ - ); \ -})) - -#define __boot_rww_enable_alternate() \ -(__extension__({ \ - __asm__ __volatile__ \ - ( \ - "sts %0, %1\n\t" \ - "spm\n\t" \ - ".word 0xffff\n\t" \ - "nop\n\t" \ - : \ - : "i" (_SFR_MEM_ADDR(__SPM_REG)), \ - "r" ((uint8_t)(__BOOT_RWW_ENABLE)) \ - ); \ -})) - -/* From the mega16/mega128 data sheets (maybe others): - - Bits by SPM To set the Boot Loader Lock bits, write the desired data to - R0, write "X0001001" to SPMCR and execute SPM within four clock cycles - after writing SPMCR. The only accessible Lock bits are the Boot Lock bits - that may prevent the Application and Boot Loader section from any - software update by the MCU. - - If bits 5..2 in R0 are cleared (zero), the corresponding Boot Lock bit - will be programmed if an SPM instruction is executed within four cycles - after BLBSET and SPMEN (or SELFPRGEN) are set in SPMCR. The Z-pointer is - don't care during this operation, but for future compatibility it is - recommended to load the Z-pointer with $0001 (same as used for reading the - Lock bits). For future compatibility It is also recommended to set bits 7, - 6, 1, and 0 in R0 to 1 when writing the Lock bits. When programming the - Lock bits the entire Flash can be read during the operation. */ - -#define __boot_lock_bits_set(lock_bits) \ -(__extension__({ \ - uint8_t value = (uint8_t)(~(lock_bits)); \ - __asm__ __volatile__ \ - ( \ - "ldi r30, 1\n\t" \ - "ldi r31, 0\n\t" \ - "mov r0, %2\n\t" \ - "sts %0, %1\n\t" \ - "spm\n\t" \ - : \ - : "i" (_SFR_MEM_ADDR(__SPM_REG)), \ - "r" ((uint8_t)(__BOOT_LOCK_BITS_SET)), \ - "r" (value) \ - : "r0", "r30", "r31" \ - ); \ -})) - -#define __boot_lock_bits_set_alternate(lock_bits) \ -(__extension__({ \ - uint8_t value = (uint8_t)(~(lock_bits)); \ - __asm__ __volatile__ \ - ( \ - "ldi r30, 1\n\t" \ - "ldi r31, 0\n\t" \ - "mov r0, %2\n\t" \ - "sts %0, %1\n\t" \ - "spm\n\t" \ - ".word 0xffff\n\t" \ - "nop\n\t" \ - : \ - : "i" (_SFR_MEM_ADDR(__SPM_REG)), \ - "r" ((uint8_t)(__BOOT_LOCK_BITS_SET)), \ - "r" (value) \ - : "r0", "r30", "r31" \ - ); \ -})) -#endif /* __DOXYGEN__ */ - -/* - Reading lock and fuse bits: - - Similarly to writing the lock bits above, set BLBSET and SPMEN (or - SELFPRGEN) bits in __SPMREG, and then (within four clock cycles) issue an - LPM instruction. - - Z address: contents: - 0x0000 low fuse bits - 0x0001 lock bits - 0x0002 extended fuse bits - 0x0003 high fuse bits - - Sounds confusing, doesn't it? - - Unlike the macros in pgmspace.h, no need to care for non-enhanced - cores here as these old cores do not provide SPM support anyway. - */ - -/** \ingroup avr_boot - \def GET_LOW_FUSE_BITS - address to read the low fuse bits, using boot_lock_fuse_bits_get - */ -#define GET_LOW_FUSE_BITS (0x0000) -/** \ingroup avr_boot - \def GET_LOCK_BITS - address to read the lock bits, using boot_lock_fuse_bits_get - */ -#define GET_LOCK_BITS (0x0001) -/** \ingroup avr_boot - \def GET_EXTENDED_FUSE_BITS - address to read the extended fuse bits, using boot_lock_fuse_bits_get - */ -#define GET_EXTENDED_FUSE_BITS (0x0002) -/** \ingroup avr_boot - \def GET_HIGH_FUSE_BITS - address to read the high fuse bits, using boot_lock_fuse_bits_get - */ -#define GET_HIGH_FUSE_BITS (0x0003) - -/** \ingroup avr_boot - \def boot_lock_fuse_bits_get(address) - - Read the lock or fuse bits at \c address. - - Parameter \c address can be any of GET_LOW_FUSE_BITS, - GET_LOCK_BITS, GET_EXTENDED_FUSE_BITS, or GET_HIGH_FUSE_BITS. - - \note The lock and fuse bits returned are the physical values, - i.e. a bit returned as 0 means the corresponding fuse or lock bit - is programmed. - */ -#define boot_lock_fuse_bits_get(address) \ -(__extension__({ \ - uint8_t __result; \ - __asm__ __volatile__ \ - ( \ - "sts %1, %2\n\t" \ - "lpm %0, Z\n\t" \ - : "=r" (__result) \ - : "i" (_SFR_MEM_ADDR(__SPM_REG)), \ - "r" ((uint8_t)(__BOOT_LOCK_BITS_SET)), \ - "z" ((uint16_t)(address)) \ - ); \ - __result; \ -})) - -#ifndef __DOXYGEN__ -#define __BOOT_SIGROW_READ (_BV(__SPM_ENABLE) | _BV(SIGRD)) -#endif -/** \ingroup avr_boot - \def boot_signature_byte_get(address) - - Read the Signature Row byte at \c address. For some MCU types, - this function can also retrieve the factory-stored oscillator - calibration bytes. - - Parameter \c address can be 0-0x1f as documented by the datasheet. - \note The values are MCU type dependent. -*/ - -#define boot_signature_byte_get(addr) \ -(__extension__({ \ - uint8_t __result; \ - __asm__ __volatile__ \ - ( \ - "sts %1, %2\n\t" \ - "lpm %0, Z" "\n\t" \ - : "=r" (__result) \ - : "i" (_SFR_MEM_ADDR(__SPM_REG)), \ - "r" ((uint8_t)(__BOOT_SIGROW_READ)), \ - "z" ((uint16_t)(addr)) \ - ); \ - __result; \ -})) - -/** \ingroup avr_boot - \def boot_page_fill(address, data) - - Fill the bootloader temporary page buffer for flash - address with data word. - - \note The address is a byte address. The data is a word. The AVR - writes data to the buffer a word at a time, but addresses the buffer - per byte! So, increment your address by 2 between calls, and send 2 - data bytes in a word format! The LSB of the data is written to the lower - address; the MSB of the data is written to the higher address.*/ - -/** \ingroup avr_boot - \def boot_page_erase(address) - - Erase the flash page that contains address. - - \note address is a byte address in flash, not a word address. */ - -/** \ingroup avr_boot - \def boot_page_write(address) - - Write the bootloader temporary page buffer - to flash page that contains address. - - \note address is a byte address in flash, not a word address. */ - -/** \ingroup avr_boot - \def boot_rww_enable() - - Enable the Read-While-Write memory section. */ - -/** \ingroup avr_boot - \def boot_lock_bits_set(lock_bits) - - Set the bootloader lock bits. - - \param lock_bits A mask of which Boot Loader Lock Bits to set. - - \note In this context, a 'set bit' will be written to a zero value. - Note also that only BLBxx bits can be programmed by this command. - - For example, to disallow the SPM instruction from writing to the Boot - Loader memory section of flash, you would use this macro as such: - - \code - boot_lock_bits_set (_BV (BLB11)); - \endcode - - \note Like any lock bits, the Boot Loader Lock Bits, once set, - cannot be cleared again except by a chip erase which will in turn - also erase the boot loader itself. */ - -/* Normal versions of the macros use 16-bit addresses. - Extended versions of the macros use 32-bit addresses. - Alternate versions of the macros use 16-bit addresses and require special - instruction sequences after LPM. - - FLASHEND is defined in the ioXXXX.h file. - USHRT_MAX is defined in . */ - -#if defined(__AVR_ATmega161__) || defined(__AVR_ATmega163__) \ - || defined(__AVR_ATmega323__) - -/* Alternate: ATmega161/163/323 and 16 bit address */ -#define boot_page_fill(address, data) __boot_page_fill_alternate(address, data) -#define boot_page_erase(address) __boot_page_erase_alternate(address) -#define boot_page_write(address) __boot_page_write_alternate(address) -#define boot_rww_enable() __boot_rww_enable_alternate() -#define boot_lock_bits_set(lock_bits) __boot_lock_bits_set_alternate(lock_bits) - -#elif (FLASHEND > USHRT_MAX) - -/* Extended: >16 bit address */ -#define boot_page_fill(address, data) __boot_page_fill_extended(address, data) -#define boot_page_erase(address) __boot_page_erase_extended(address) -#define boot_page_write(address) __boot_page_write_extended(address) -#define boot_rww_enable() __boot_rww_enable() -#define boot_lock_bits_set(lock_bits) __boot_lock_bits_set(lock_bits) - -#else - -/* Normal: 16 bit address */ -#define boot_page_fill(address, data) __boot_page_fill_normal(address, data) -#define boot_page_erase(address) __boot_page_erase_normal(address) -#define boot_page_write(address) __boot_page_write_normal(address) -#define boot_rww_enable() __boot_rww_enable() -#define boot_lock_bits_set(lock_bits) __boot_lock_bits_set(lock_bits) - -#endif - -/** \ingroup avr_boot - - Same as boot_page_fill() except it waits for eeprom and spm operations to - complete before filling the page. */ - -#define boot_page_fill_safe(address, data) \ -do { \ - boot_spm_busy_wait(); \ - eeprom_busy_wait(); \ - boot_page_fill(address, data); \ -} while (0) - -/** \ingroup avr_boot - - Same as boot_page_erase() except it waits for eeprom and spm operations to - complete before erasing the page. */ - -#define boot_page_erase_safe(address) \ -do { \ - boot_spm_busy_wait(); \ - eeprom_busy_wait(); \ - boot_page_erase (address); \ -} while (0) - -/** \ingroup avr_boot - - Same as boot_page_write() except it waits for eeprom and spm operations to - complete before writing the page. */ - -#define boot_page_write_safe(address) \ -do { \ - boot_spm_busy_wait(); \ - eeprom_busy_wait(); \ - boot_page_write (address); \ -} while (0) - -/** \ingroup avr_boot - - Same as boot_rww_enable() except waits for eeprom and spm operations to - complete before enabling the RWW mameory. */ - -#define boot_rww_enable_safe() \ -do { \ - boot_spm_busy_wait(); \ - eeprom_busy_wait(); \ - boot_rww_enable(); \ -} while (0) - -/** \ingroup avr_boot - - Same as boot_lock_bits_set() except waits for eeprom and spm operations to - complete before setting the lock bits. */ - -#define boot_lock_bits_set_safe(lock_bits) \ -do { \ - boot_spm_busy_wait(); \ - eeprom_busy_wait(); \ - boot_lock_bits_set (lock_bits); \ -} while (0) - -#endif /* _AVR_BOOT_H_ */ diff --git a/arduino/hardware/tools/avr/avr/include/avr/builtins.h b/arduino/hardware/tools/avr/avr/include/avr/builtins.h deleted file mode 100644 index f0f554f..0000000 --- a/arduino/hardware/tools/avr/avr/include/avr/builtins.h +++ /dev/null @@ -1,113 +0,0 @@ -/* Copyright (c) 2008 Anatoly Sokolov - Copyright (c) 2010 Joerg Wunsch - All rights reserved. - - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - * Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - * Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in - the documentation and/or other materials provided with the - distribution. - - * Neither the name of the copyright holders nor the names of - contributors may be used to endorse or promote products derived - from this software without specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. */ - -/* $Id$ */ - -/* - avr/builtins.h - Intrinsic functions built into the compiler - */ - -#ifndef _AVR_BUILTINS_H_ -#define _AVR_BUILTINS_H_ - -#ifndef __HAS_DELAY_CYCLES -#define __HAS_DELAY_CYCLES 1 -#endif - -/** \file */ -/** \defgroup avr_builtins : GCC builtins - \code #include \endcode - - This header file declares AVR builtins. - All the functions documented here are built into the - compiler, and cause it to emit the corresponding assembly - code instructions. -*/ - -/** - \ingroup avr_builtins - - Enables interrupts by setting the global interrupt mask. */ -extern void __builtin_avr_sei(void); - -/** - \ingroup avr_builtins - - Disables all interrupts by clearing the global interrupt mask. */ -extern void __builtin_avr_cli(void); - -/** - \ingroup avr_builtins - - Emits a \c SLEEP instruction. */ - -extern void __builtin_avr_sleep(void); - -/** - \ingroup avr_builtins - - Emits a WDR (watchdog reset) instruction. */ -extern void __builtin_avr_wdr(void); - -/** - \ingroup avr_builtins - - Emits a SWAP (nibble swap) instruction on __b. */ -extern unsigned char __builtin_avr_swap(unsigned char __b); - -/** - \ingroup avr_builtins - - Emits an FMUL (fractional multiply unsigned) instruction. */ -extern unsigned int __builtin_avr_fmul(unsigned char __a, unsigned char __b); - -/** - \ingroup avr_builtins - - Emits an FMUL (fractional multiply signed) instruction. */ -extern int __builtin_avr_fmuls(char __a, char __b); - -/** - \ingroup avr_builtins - - Emits an FMUL (fractional multiply signed with unsigned) instruction. */ -extern int __builtin_avr_fmulsu(char __a, unsigned char __b); - -#if __HAS_DELAY_CYCLES || defined(__DOXYGEN__) -/** - \ingroup avr_builtins - - Emits a sequence of instructions causing the CPU to spend - \c __n cycles on it. */ -extern void __builtin_avr_delay_cycles(unsigned long __n); -#endif - -#endif /* _AVR_BUILTINS_H_ */ diff --git a/arduino/hardware/tools/avr/avr/include/avr/common.h b/arduino/hardware/tools/avr/avr/include/avr/common.h deleted file mode 100644 index 358b328..0000000 --- a/arduino/hardware/tools/avr/avr/include/avr/common.h +++ /dev/null @@ -1,335 +0,0 @@ -/* Copyright (c) 2007 Eric B. Weddington - All rights reserved. - - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - * Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - * Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in - the documentation and/or other materials provided with the - distribution. - - * Neither the name of the copyright holders nor the names of - contributors may be used to endorse or promote products derived - from this software without specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. */ - -/* $Id$ */ - - -#ifndef _AVR_COMMON_H -#define _AVR_COMMON_H - -#include - -/* -This purpose of this header is to define registers that have not been -previously defined in the individual device IO header files, and to define -other symbols that are common across AVR device families. - -This file is designed to be included in after the individual -device IO header files, and after - -*/ - -/*------------ Registers Not Previously Defined ------------*/ - -/* -These are registers that are not previously defined in the individual -IO header files, OR they are defined here because they are used in parts of -avr-libc even if a device is not selected but a general architecture has -been selected. -*/ - - -/* -Stack pointer register. - -AVR architecture 1 has no RAM, thus no stack pointer. - -All other architectures do have a stack pointer. Some devices have only -less than 256 bytes of possible RAM locations (128 Bytes of SRAM -and no option for external RAM), thus SPH is officially "reserved" -for them. -*/ -#if __AVR_ARCH__ >= 100 -# ifndef SPL -# define SPL _SFR_MEM8(0x3D) -# endif -# ifndef SPH -# define SPH _SFR_MEM8(0x3E) -# endif -# ifndef SP -# define SP _SFR_MEM16(0x3D) -# endif -#elif __AVR_ARCH__ != 1 -# ifndef SPL -# define SPL _SFR_IO8(0x3D) -# endif -# if XRAMEND < 0x100 && !defined(__COMPILING_AVR_LIBC__) -# ifndef SP -# define SP _SFR_IO8(0x3D) -# endif -# else -# ifndef SP -# define SP _SFR_IO16(0x3D) -# endif -# ifndef SPH -# define SPH _SFR_IO8(0x3E) -# endif -# endif /* XRAMEND < 0x100 && !defined(__COMPILING_AVR_LIBC__) */ -#endif /* __AVR_ARCH__ != 1 */ - - -/* Status Register */ -#ifndef SREG -# if __AVR_ARCH__ >= 100 -# define SREG _SFR_MEM8(0x3F) -# else -# define SREG _SFR_IO8(0x3F) -# endif -#endif - - -/* SREG bit definitions */ -#ifndef SREG_C -# define SREG_C (0) -#endif -#ifndef SREG_Z -# define SREG_Z (1) -#endif -#ifndef SREG_N -# define SREG_N (2) -#endif -#ifndef SREG_V -# define SREG_V (3) -#endif -#ifndef SREG_S -# define SREG_S (4) -#endif -#ifndef SREG_H -# define SREG_H (5) -#endif -#ifndef SREG_T -# define SREG_T (6) -#endif -#ifndef SREG_I -# define SREG_I (7) -#endif - - -#if defined(__COMPILING_AVR_LIBC__) - -/* AVR 6 Architecture */ -# if __AVR_ARCH__ == 6 -# ifndef EIND -# define EIND _SFR_IO8(0X3C) -# endif -/* XMEGA Architectures */ -# elif __AVR_ARCH__ >= 100 -# ifndef EIND -# define EIND _SFR_MEM8(0x3C) -# endif -# endif - -/* -Only few devices come without EEPROM. In order to assemble the -EEPROM library components without defining a specific device, we -keep the EEPROM-related definitions here. -*/ - -/* EEPROM Control Register */ -# ifndef EECR -# define EECR _SFR_IO8(0x1C) -# endif - -/* EEPROM Data Register */ -# ifndef EEDR -# define EEDR _SFR_IO8(0x1D) -# endif - -/* EEPROM Address Register */ -# ifndef EEAR -# define EEAR _SFR_IO16(0x1E) -# endif -# ifndef EEARL -# define EEARL _SFR_IO8(0x1E) -# endif -# ifndef EEARH -# define EEARH _SFR_IO8(0x1F) -# endif - -/* EEPROM Control Register bits */ -# ifndef EERE -# define EERE (0) -# endif -# ifndef EEWE -# define EEWE (1) -# endif -# ifndef EEMWE -# define EEMWE (2) -# endif -# ifndef EERIE -# define EERIE (3) -# endif - - -/* RAM Page Z Select Register */ -#ifndef RAMPZ -# if defined(__AVR_HAVE_RAMPZ__) && __AVR_HAVE_RAMPZ__ -# if __AVR_ARCH__ >= 100 -# define RAMPZ _SFR_MEM8(0x3B) -# else -# define RAMPZ _SFR_IO8(0x3B) -# endif -# endif -#endif - -#endif /* __COMPILING_AVR_LIBC__ */ - - - -/*------------ Common Symbols ------------*/ - -/* -Generic definitions for registers that are common across multiple AVR devices -and families. -*/ - -/* Pointer registers definitions */ -#if __AVR_ARCH__ != 1 /* avr1 does not have X and Y pointers */ -# define XL r26 -# define XH r27 -# define YL r28 -# define YH r29 -#endif /* #if __AVR_ARCH__ != 1 */ -#define ZL r30 -#define ZH r31 - - -/* Status Register */ -#if defined(SREG) -# define AVR_STATUS_REG SREG -# if __AVR_ARCH__ >= 100 -# define AVR_STATUS_ADDR _SFR_MEM_ADDR(SREG) -# else -# define AVR_STATUS_ADDR _SFR_IO_ADDR(SREG) -# endif -#endif - -/* Stack Pointer (combined) Register */ -#if defined(SP) -# define AVR_STACK_POINTER_REG SP -# if __AVR_ARCH__ >= 100 -# define AVR_STACK_POINTER_ADDR _SFR_MEM_ADDR(SP) -# else -# define AVR_STACK_POINTER_ADDR _SFR_IO_ADDR(SP) -# endif -#endif - -/* Stack Pointer High Register */ -#if defined(SPH) -# define _HAVE_AVR_STACK_POINTER_HI 1 -# define AVR_STACK_POINTER_HI_REG SPH -# if __AVR_ARCH__ >= 100 -# define AVR_STACK_POINTER_HI_ADDR _SFR_MEM_ADDR(SPH) -# else -# define AVR_STACK_POINTER_HI_ADDR _SFR_IO_ADDR(SPH) -# endif -#endif - -/* Stack Pointer Low Register */ -#if defined(SPL) -# define AVR_STACK_POINTER_LO_REG SPL -# if __AVR_ARCH__ >= 100 -# define AVR_STACK_POINTER_LO_ADDR _SFR_MEM_ADDR(SPL) -# else -# define AVR_STACK_POINTER_LO_ADDR _SFR_IO_ADDR(SPL) -# endif -#endif - -/* RAMPD Register */ -#if defined(RAMPD) -# define AVR_RAMPD_REG RAMPD -# if __AVR_ARCH__ >= 100 -# define AVR_RAMPD_ADDR _SFR_MEM_ADDR(RAMPD) -# else -# define AVR_RAMPD_ADDR _SFR_IO_ADDR(RAMPD) -# endif -#endif - -/* RAMPX Register */ -#if defined(RAMPX) -# define AVR_RAMPX_REG RAMPX -# if __AVR_ARCH__ >= 100 -# define AVR_RAMPX_ADDR _SFR_MEM_ADDR(RAMPX) -# else -# define AVR_RAMPX_ADDR _SFR_IO_ADDR(RAMPX) -# endif -#endif - -/* RAMPY Register */ -#if defined(RAMPY) -# define AVR_RAMPY_REG RAMPY -# if __AVR_ARCH__ >= 100 -# define AVR_RAMPY_ADDR _SFR_MEM_ADDR(RAMPY) -# else -# define AVR_RAMPY_ADDR _SFR_IO_ADDR(RAMPY) -# endif -#endif - -/* RAMPZ Register */ -#if defined(RAMPZ) -# define AVR_RAMPZ_REG RAMPZ -# if __AVR_ARCH__ >= 100 -# define AVR_RAMPZ_ADDR _SFR_MEM_ADDR(RAMPZ) -# else -# define AVR_RAMPZ_ADDR _SFR_IO_ADDR(RAMPZ) -# endif -#endif - -/* Extended Indirect Register */ -#if defined(EIND) -# define AVR_EXTENDED_INDIRECT_REG EIND -# if __AVR_ARCH__ >= 100 -# define AVR_EXTENDED_INDIRECT_ADDR _SFR_MEM_ADDR(EIND) -# else -# define AVR_EXTENDED_INDIRECT_ADDR _SFR_IO_ADDR(EIND) -# endif -#endif - -/*------------ Workaround to old compilers (4.1.2 and earlier) ------------*/ - -#ifndef __AVR_HAVE_MOVW__ -# if defined(__AVR_ENHANCED__) && __AVR_ENHANCED__ -# define __AVR_HAVE_MOVW__ 1 -# endif -#endif - -#ifndef __AVR_HAVE_LPMX__ -# if defined(__AVR_ENHANCED__) && __AVR_ENHANCED__ -# define __AVR_HAVE_LPMX__ 1 -# endif -#endif - -#ifndef __AVR_HAVE_MUL__ -# if defined(__AVR_ENHANCED__) && __AVR_ENHANCED__ -# define __AVR_HAVE_MUL__ 1 -# endif -#endif - -#endif /* _AVR_COMMON_H */ diff --git a/arduino/hardware/tools/avr/avr/include/avr/cpufunc.h b/arduino/hardware/tools/avr/avr/include/avr/cpufunc.h deleted file mode 100644 index 3e255aa..0000000 --- a/arduino/hardware/tools/avr/avr/include/avr/cpufunc.h +++ /dev/null @@ -1,93 +0,0 @@ -/* Copyright (c) 2010, Joerg Wunsch - All rights reserved. - - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - * Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - * Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in - the documentation and/or other materials provided with the - distribution. - - * Neither the name of the copyright holders nor the names of - contributors may be used to endorse or promote products derived - from this software without specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. */ - -/* $Id$ */ - -/* avr/cpufunc.h - Special CPU functions */ - -#ifndef _AVR_CPUFUNC_H_ -#define _AVR_CPUFUNC_H_ 1 - -#include - -/** \file */ -/** \defgroup avr_cpufunc : Special AVR CPU functions - \code #include \endcode - - This header file contains macros that access special functions of - the AVR CPU which do not fit into any of the other header files. - -*/ - -#if defined(__DOXYGEN__) -/** - \ingroup avr_cpufunc - \def _NOP - - Execute a no operation (NOP) CPU instruction. This - should not be used to implement delays, better use the functions - from or for this. For - debugging purposes, a NOP can be useful to have an instruction that - is guaranteed to be not optimized away by the compiler, so it can - always become a breakpoint in the debugger. -*/ -#define _NOP() -#else /* real code */ -#define _NOP() __asm__ __volatile__("nop") -#endif /* __DOXYGEN__ */ - -#if defined(__DOXYGEN__) -/** - \ingroup avr_cpufunc - \def _MemoryBarrier - - Implement a read/write memory barrier. A memory - barrier instructs the compiler to not cache any memory data in - registers beyond the barrier. This can sometimes be more effective - than blocking certain optimizations by declaring some object with a - \c volatile qualifier. - - See \ref optim_code_reorder for things to be taken into account - with respect to compiler optimizations. -*/ -#define _MemoryBarrier() -#else /* real code */ -#define _MemoryBarrier() __asm__ __volatile__("":::"memory") -#endif /* __DOXYGEN__ */ - -/** - \ingroup avr_cpufunc - - Write \a __value to Configuration Change Protected (CCP) IO register - at \a __ioaddr. - */ -void ccp_write_io (uint8_t *__ioaddr, uint8_t __value); - -#endif /* _AVR_CPUFUNC_H_ */ diff --git a/arduino/hardware/tools/avr/avr/include/avr/crc16.h b/arduino/hardware/tools/avr/avr/include/avr/crc16.h deleted file mode 100644 index 6c8de25..0000000 --- a/arduino/hardware/tools/avr/avr/include/avr/crc16.h +++ /dev/null @@ -1,39 +0,0 @@ -/* Copyright (c) 2005 Joerg Wunsch - All rights reserved. - - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - * Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - * Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in - the documentation and/or other materials provided with the - distribution. - - * Neither the name of the copyright holders nor the names of - contributors may be used to endorse or promote products derived - from this software without specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. */ - -/* $Id$ */ - -#ifndef _AVR_CRC16_H_ -#define _AVR_CRC16_H_ - -#warning "This file has been moved to ." -#include - -#endif /* _AVR_CRC16_H_ */ diff --git a/arduino/hardware/tools/avr/avr/include/avr/delay.h b/arduino/hardware/tools/avr/avr/include/avr/delay.h deleted file mode 100644 index 2847ceb..0000000 --- a/arduino/hardware/tools/avr/avr/include/avr/delay.h +++ /dev/null @@ -1,39 +0,0 @@ -/* Copyright (c) 2005 Joerg Wunsch - All rights reserved. - - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - * Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - * Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in - the documentation and/or other materials provided with the - distribution. - - * Neither the name of the copyright holders nor the names of - contributors may be used to endorse or promote products derived - from this software without specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. */ - -/* $Id$ */ - -#ifndef _AVR_DELAY_H_ -#define _AVR_DELAY_H_ - -#warning "This file has been moved to ." -#include - -#endif /* _AVR_DELAY_H_ */ diff --git a/arduino/hardware/tools/avr/avr/include/avr/eeprom.h b/arduino/hardware/tools/avr/avr/include/avr/eeprom.h deleted file mode 100644 index 1c3385b..0000000 --- a/arduino/hardware/tools/avr/avr/include/avr/eeprom.h +++ /dev/null @@ -1,246 +0,0 @@ -/* Copyright (c) 2002, 2003, 2004, 2007 Marek Michalkiewicz - Copyright (c) 2005, 2006 Bjoern Haase - Copyright (c) 2008 Atmel Corporation - Copyright (c) 2008 Wouter van Gulik - Copyright (c) 2009 Dmitry Xmelkov - All rights reserved. - - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - * Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - * Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in - the documentation and/or other materials provided with the - distribution. - * Neither the name of the copyright holders nor the names of - contributors may be used to endorse or promote products derived - from this software without specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. */ - -/* $Id$ */ - -#ifndef _AVR_EEPROM_H_ -#define _AVR_EEPROM_H_ 1 - -#include - -#if !E2END && !defined(__DOXYGEN__) && !defined(__COMPILING_AVR_LIBC__) -# warning "Device does not have EEPROM available." -#else - -#if defined (EEAR) && !defined (EEARL) && !defined (EEARH) -#define EEARL EEAR -#endif - -#ifndef __ASSEMBLER__ - -#include /* size_t */ -#include - -/** \defgroup avr_eeprom : EEPROM handling - \code #include \endcode - - This header file declares the interface to some simple library - routines suitable for handling the data EEPROM contained in the - AVR microcontrollers. The implementation uses a simple polled - mode interface. Applications that require interrupt-controlled - EEPROM access to ensure that no time will be wasted in spinloops - will have to deploy their own implementation. - - \par Notes: - - - In addition to the write functions there is a set of update ones. - This functions read each byte first and skip the burning if the - old value is the same with new. The scaning direction is from - high address to low, to obtain quick return in common cases. - - - All of the read/write functions first make sure the EEPROM is - ready to be accessed. Since this may cause long delays if a - write operation is still pending, time-critical applications - should first poll the EEPROM e. g. using eeprom_is_ready() before - attempting any actual I/O. But this functions are not wait until - SELFPRGEN in SPMCSR becomes zero. Do this manually, if your - softwate contains the Flash burning. - - - As these functions modify IO registers, they are known to be - non-reentrant. If any of these functions are used from both, - standard and interrupt context, the applications must ensure - proper protection (e.g. by disabling interrupts before accessing - them). - - - All write functions force erase_and_write programming mode. - - - For Xmega the EEPROM start address is 0, like other architectures. - The reading functions add the 0x2000 value to use EEPROM mapping into - data space. - */ - -#ifdef __cplusplus -extern "C" { -#endif - -#ifndef __ATTR_PURE__ -# ifdef __DOXYGEN__ -# define __ATTR_PURE__ -# else -# define __ATTR_PURE__ __attribute__((__pure__)) -# endif -#endif - -/** \def EEMEM - \ingroup avr_eeprom - Attribute expression causing a variable to be allocated within the - .eeprom section. */ -#define EEMEM __attribute__((section(".eeprom"))) - -/** \def eeprom_is_ready - \ingroup avr_eeprom - \returns 1 if EEPROM is ready for a new read/write operation, 0 if not. - */ -#if defined (__DOXYGEN__) -# define eeprom_is_ready() -#elif defined (__AVR_XMEGA__) && __AVR_XMEGA__ -# define eeprom_is_ready() bit_is_clear (NVM_STATUS, NVM_NVMBUSY_bp) -#elif defined (DEECR) -# define eeprom_is_ready() bit_is_clear (DEECR, BSY) -#elif defined (EEPE) -# define eeprom_is_ready() bit_is_clear (EECR, EEPE) -#else -# define eeprom_is_ready() bit_is_clear (EECR, EEWE) -#endif - - -/** \def eeprom_busy_wait - \ingroup avr_eeprom - Loops until the eeprom is no longer busy. - \returns Nothing. - */ -#define eeprom_busy_wait() do {} while (!eeprom_is_ready()) - - -/** \ingroup avr_eeprom - Read one byte from EEPROM address \a __p. - */ -uint8_t eeprom_read_byte (const uint8_t *__p) __ATTR_PURE__; - -/** \ingroup avr_eeprom - Read one 16-bit word (little endian) from EEPROM address \a __p. - */ -uint16_t eeprom_read_word (const uint16_t *__p) __ATTR_PURE__; - -/** \ingroup avr_eeprom - Read one 32-bit double word (little endian) from EEPROM address \a __p. - */ -uint32_t eeprom_read_dword (const uint32_t *__p) __ATTR_PURE__; - -/** \ingroup avr_eeprom - Read one float value (little endian) from EEPROM address \a __p. - */ -float eeprom_read_float (const float *__p) __ATTR_PURE__; - -/** \ingroup avr_eeprom - Read a block of \a __n bytes from EEPROM address \a __src to SRAM - \a __dst. - */ -void eeprom_read_block (void *__dst, const void *__src, size_t __n); - - -/** \ingroup avr_eeprom - Write a byte \a __value to EEPROM address \a __p. - */ -void eeprom_write_byte (uint8_t *__p, uint8_t __value); - -/** \ingroup avr_eeprom - Write a word \a __value to EEPROM address \a __p. - */ -void eeprom_write_word (uint16_t *__p, uint16_t __value); - -/** \ingroup avr_eeprom - Write a 32-bit double word \a __value to EEPROM address \a __p. - */ -void eeprom_write_dword (uint32_t *__p, uint32_t __value); - -/** \ingroup avr_eeprom - Write a float \a __value to EEPROM address \a __p. - */ -void eeprom_write_float (float *__p, float __value); - -/** \ingroup avr_eeprom - Write a block of \a __n bytes to EEPROM address \a __dst from \a __src. - \note The argument order is mismatch with common functions like strcpy(). - */ -void eeprom_write_block (const void *__src, void *__dst, size_t __n); - - -/** \ingroup avr_eeprom - Update a byte \a __value to EEPROM address \a __p. - */ -void eeprom_update_byte (uint8_t *__p, uint8_t __value); - -/** \ingroup avr_eeprom - Update a word \a __value to EEPROM address \a __p. - */ -void eeprom_update_word (uint16_t *__p, uint16_t __value); - -/** \ingroup avr_eeprom - Update a 32-bit double word \a __value to EEPROM address \a __p. - */ -void eeprom_update_dword (uint32_t *__p, uint32_t __value); - -/** \ingroup avr_eeprom - Update a float \a __value to EEPROM address \a __p. - */ -void eeprom_update_float (float *__p, float __value); - -/** \ingroup avr_eeprom - Update a block of \a __n bytes to EEPROM address \a __dst from \a __src. - \note The argument order is mismatch with common functions like strcpy(). - */ -void eeprom_update_block (const void *__src, void *__dst, size_t __n); - - -/** \name IAR C compatibility defines */ -/*@{*/ - -/** \def _EEPUT - \ingroup avr_eeprom - Write a byte to EEPROM. Compatibility define for IAR C. */ -#define _EEPUT(addr, val) eeprom_write_byte ((uint8_t *)(addr), (uint8_t)(val)) - -/** \def __EEPUT - \ingroup avr_eeprom - Write a byte to EEPROM. Compatibility define for IAR C. */ -#define __EEPUT(addr, val) eeprom_write_byte ((uint8_t *)(addr), (uint8_t)(val)) - -/** \def _EEGET - \ingroup avr_eeprom - Read a byte from EEPROM. Compatibility define for IAR C. */ -#define _EEGET(var, addr) (var) = eeprom_read_byte ((const uint8_t *)(addr)) - -/** \def __EEGET - \ingroup avr_eeprom - Read a byte from EEPROM. Compatibility define for IAR C. */ -#define __EEGET(var, addr) (var) = eeprom_read_byte ((const uint8_t *)(addr)) - -/*@}*/ - -#ifdef __cplusplus -} -#endif - -#endif /* !__ASSEMBLER__ */ -#endif /* E2END || defined(__DOXYGEN__) || defined(__COMPILING_AVR_LIBC__) */ -#endif /* !_AVR_EEPROM_H_ */ diff --git a/arduino/hardware/tools/avr/avr/include/avr/fuse.h b/arduino/hardware/tools/avr/avr/include/avr/fuse.h deleted file mode 100644 index 22888a0..0000000 --- a/arduino/hardware/tools/avr/avr/include/avr/fuse.h +++ /dev/null @@ -1,274 +0,0 @@ -/* Copyright (c) 2007, Atmel Corporation - All rights reserved. - - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - * Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - * Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in - the documentation and/or other materials provided with the - distribution. - - * Neither the name of the copyright holders nor the names of - contributors may be used to endorse or promote products derived - from this software without specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. */ - -/* $Id$ */ - -/* avr/fuse.h - Fuse API */ - -#ifndef _AVR_FUSE_H_ -#define _AVR_FUSE_H_ 1 - -/* This file must be explicitly included by . */ -#if !defined(_AVR_IO_H_) -#error "You must #include and not by itself." -#endif - - -/** \file */ -/** \defgroup avr_fuse : Fuse Support - - \par Introduction - - The Fuse API allows a user to specify the fuse settings for the specific - AVR device they are compiling for. These fuse settings will be placed - in a special section in the ELF output file, after linking. - - Programming tools can take advantage of the fuse information embedded in - the ELF file, by extracting this information and determining if the fuses - need to be programmed before programming the Flash and EEPROM memories. - This also allows a single ELF file to contain all the - information needed to program an AVR. - - To use the Fuse API, include the header file, which in turn - automatically includes the individual I/O header file and the - file. These other two files provides everything necessary to set the AVR - fuses. - - \par Fuse API - - Each I/O header file must define the FUSE_MEMORY_SIZE macro which is - defined to the number of fuse bytes that exist in the AVR device. - - A new type, __fuse_t, is defined as a structure. The number of fields in - this structure are determined by the number of fuse bytes in the - FUSE_MEMORY_SIZE macro. - - If FUSE_MEMORY_SIZE == 1, there is only a single field: byte, of type - unsigned char. - - If FUSE_MEMORY_SIZE == 2, there are two fields: low, and high, of type - unsigned char. - - If FUSE_MEMORY_SIZE == 3, there are three fields: low, high, and extended, - of type unsigned char. - - If FUSE_MEMORY_SIZE > 3, there is a single field: byte, which is an array - of unsigned char with the size of the array being FUSE_MEMORY_SIZE. - - A convenience macro, FUSEMEM, is defined as a GCC attribute for a - custom-named section of ".fuse". - - A convenience macro, FUSES, is defined that declares a variable, __fuse, of - type __fuse_t with the attribute defined by FUSEMEM. This variable - allows the end user to easily set the fuse data. - - \note If a device-specific I/O header file has previously defined FUSEMEM, - then FUSEMEM is not redefined. If a device-specific I/O header file has - previously defined FUSES, then FUSES is not redefined. - - Each AVR device I/O header file has a set of defined macros which specify the - actual fuse bits available on that device. The AVR fuses have inverted - values, logical 1 for an unprogrammed (disabled) bit and logical 0 for a - programmed (enabled) bit. The defined macros for each individual fuse - bit represent this in their definition by a bit-wise inversion of a mask. - For example, the FUSE_EESAVE fuse in the ATmega128 is defined as: - \code - #define FUSE_EESAVE ~_BV(3) - \endcode - \note The _BV macro creates a bit mask from a bit number. It is then - inverted to represent logical values for a fuse memory byte. - - To combine the fuse bits macros together to represent a whole fuse byte, - use the bitwise AND operator, like so: - \code - (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_EESAVE & FUSE_SPIEN & FUSE_JTAGEN) - \endcode - - Each device I/O header file also defines macros that provide default values - for each fuse byte that is available. LFUSE_DEFAULT is defined for a Low - Fuse byte. HFUSE_DEFAULT is defined for a High Fuse byte. EFUSE_DEFAULT - is defined for an Extended Fuse byte. - - If FUSE_MEMORY_SIZE > 3, then the I/O header file defines macros that - provide default values for each fuse byte like so: - FUSE0_DEFAULT - FUSE1_DEFAULT - FUSE2_DEFAULT - FUSE3_DEFAULT - FUSE4_DEFAULT - .... - - \par API Usage Example - - Putting all of this together is easy. Using C99's designated initializers: - - \code - #include - - FUSES = - { - .low = LFUSE_DEFAULT, - .high = (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_EESAVE & FUSE_SPIEN & FUSE_JTAGEN), - .extended = EFUSE_DEFAULT, - }; - - int main(void) - { - return 0; - } - \endcode - - Or, using the variable directly instead of the FUSES macro, - - \code - #include - - __fuse_t __fuse __attribute__((section (".fuse"))) = - { - .low = LFUSE_DEFAULT, - .high = (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_EESAVE & FUSE_SPIEN & FUSE_JTAGEN), - .extended = EFUSE_DEFAULT, - }; - - int main(void) - { - return 0; - } - \endcode - - If you are compiling in C++, you cannot use the designated intializers so - you must do: - - \code - #include - - FUSES = - { - LFUSE_DEFAULT, // .low - (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_EESAVE & FUSE_SPIEN & FUSE_JTAGEN), // .high - EFUSE_DEFAULT, // .extended - }; - - int main(void) - { - return 0; - } - \endcode - - - However there are a number of caveats that you need to be aware of to - use this API properly. - - Be sure to include to get all of the definitions for the API. - The FUSES macro defines a global variable to store the fuse data. This - variable is assigned to its own linker section. Assign the desired fuse - values immediately in the variable initialization. - - The .fuse section in the ELF file will get its values from the initial - variable assignment ONLY. This means that you can NOT assign values to - this variable in functions and the new values will not be put into the - ELF .fuse section. - - The global variable is declared in the FUSES macro has two leading - underscores, which means that it is reserved for the "implementation", - meaning the library, so it will not conflict with a user-named variable. - - You must initialize ALL fields in the __fuse_t structure. This is because - the fuse bits in all bytes default to a logical 1, meaning unprogrammed. - Normal uninitialized data defaults to all locgial zeros. So it is vital that - all fuse bytes are initialized, even with default data. If they are not, - then the fuse bits may not programmed to the desired settings. - - Be sure to have the -mmcu=device flag in your compile command line and - your linker command line to have the correct device selected and to have - the correct I/O header file included when you include . - - You can print out the contents of the .fuse section in the ELF file by - using this command line: - \code - avr-objdump -s -j .fuse - \endcode - The section contents shows the address on the left, then the data going from - lower address to a higher address, left to right. - -*/ - -#if !(defined(__ASSEMBLER__) || defined(__DOXYGEN__)) - -#ifndef FUSEMEM -#define FUSEMEM __attribute__((__used__, __section__ (".fuse"))) -#endif - -#if FUSE_MEMORY_SIZE > 3 - -typedef struct -{ - unsigned char byte[FUSE_MEMORY_SIZE]; -} __fuse_t; - - -#elif FUSE_MEMORY_SIZE == 3 - -typedef struct -{ - unsigned char low; - unsigned char high; - unsigned char extended; -} __fuse_t; - -#elif FUSE_MEMORY_SIZE == 2 - -typedef struct -{ - unsigned char low; - unsigned char high; -} __fuse_t; - -#elif FUSE_MEMORY_SIZE == 1 - -typedef struct -{ - unsigned char byte; -} __fuse_t; - -#endif - -#if !defined(FUSES) - #if defined(__AVR_XMEGA__) - #define FUSES NVM_FUSES_t __fuse FUSEMEM - #else - #define FUSES __fuse_t __fuse FUSEMEM - #endif -#endif - - -#endif /* !(__ASSEMBLER__ || __DOXYGEN__) */ - -#endif /* _AVR_FUSE_H_ */ diff --git a/arduino/hardware/tools/avr/avr/include/avr/interrupt.h b/arduino/hardware/tools/avr/avr/include/avr/interrupt.h deleted file mode 100644 index ce9a4bd..0000000 --- a/arduino/hardware/tools/avr/avr/include/avr/interrupt.h +++ /dev/null @@ -1,344 +0,0 @@ -/* Copyright (c) 2002,2005,2007 Marek Michalkiewicz - Copyright (c) 2007, Dean Camera - - All rights reserved. - - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - * Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - * Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in - the documentation and/or other materials provided with the - distribution. - - * Neither the name of the copyright holders nor the names of - contributors may be used to endorse or promote products derived - from this software without specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. */ - -/* $Id$ */ - -#ifndef _AVR_INTERRUPT_H_ -#define _AVR_INTERRUPT_H_ - -#include - -#if !defined(__DOXYGEN__) && !defined(__STRINGIFY) -/* Auxiliary macro for ISR_ALIAS(). */ -#define __STRINGIFY(x) #x -#endif /* !defined(__DOXYGEN__) */ - -/** -\file -\@{ -*/ - - -/** \name Global manipulation of the interrupt flag - - The global interrupt flag is maintained in the I bit of the status - register (SREG). - - Handling interrupts frequently requires attention regarding atomic - access to objects that could be altered by code running within an - interrupt context, see . - - Frequently, interrupts are being disabled for periods of time in - order to perform certain operations without being disturbed; see - \ref optim_code_reorder for things to be taken into account with - respect to compiler optimizations. -*/ - -#if defined(__DOXYGEN__) -/** \def sei() - \ingroup avr_interrupts - - Enables interrupts by setting the global interrupt mask. This function - actually compiles into a single line of assembly, so there is no function - call overhead. However, the macro also implies a memory barrier - which can cause additional loss of optimization. - - In order to implement atomic access to multi-byte objects, - consider using the macros from , rather than - implementing them manually with cli() and sei(). -*/ -#define sei() -#else /* !DOXYGEN */ -# define sei() __asm__ __volatile__ ("sei" ::: "memory") -#endif /* DOXYGEN */ - -#if defined(__DOXYGEN__) -/** \def cli() - \ingroup avr_interrupts - - Disables all interrupts by clearing the global interrupt mask. This function - actually compiles into a single line of assembly, so there is no function - call overhead. However, the macro also implies a memory barrier - which can cause additional loss of optimization. - - In order to implement atomic access to multi-byte objects, - consider using the macros from , rather than - implementing them manually with cli() and sei(). -*/ -#define cli() -#else /* !DOXYGEN */ -# define cli() __asm__ __volatile__ ("cli" ::: "memory") -#endif /* DOXYGEN */ - - -/** \name Macros for writing interrupt handler functions */ - - -#if defined(__DOXYGEN__) -/** \def ISR(vector [, attributes]) - \ingroup avr_interrupts - - Introduces an interrupt handler function (interrupt service - routine) that runs with global interrupts initially disabled - by default with no attributes specified. - - The attributes are optional and alter the behaviour and resultant - generated code of the interrupt routine. Multiple attributes may - be used for a single function, with a space seperating each - attribute. - - Valid attributes are ISR_BLOCK, ISR_NOBLOCK, ISR_NAKED and - ISR_ALIASOF(vect). - - \c vector must be one of the interrupt vector names that are - valid for the particular MCU type. -*/ -# define ISR(vector, [attributes]) -#else /* real code */ - -#if (__GNUC__ == 4 && __GNUC_MINOR__ >= 1) || (__GNUC__ > 4) -# define __INTR_ATTRS used, externally_visible -#else /* GCC < 4.1 */ -# define __INTR_ATTRS used -#endif - -#ifdef __cplusplus -# define ISR(vector, ...) \ - extern "C" void vector (void) __attribute__ ((signal,__INTR_ATTRS)) __VA_ARGS__; \ - void vector (void) -#else -# define ISR(vector, ...) \ - void vector (void) __attribute__ ((signal,__INTR_ATTRS)) __VA_ARGS__; \ - void vector (void) -#endif - -#endif /* DOXYGEN */ - -#if defined(__DOXYGEN__) -/** \def SIGNAL(vector) - \ingroup avr_interrupts - - Introduces an interrupt handler function that runs with global interrupts - initially disabled. - - This is the same as the ISR macro without optional attributes. - \deprecated Do not use SIGNAL() in new code. Use ISR() instead. -*/ -# define SIGNAL(vector) -#else /* real code */ - -#ifdef __cplusplus -# define SIGNAL(vector) \ - extern "C" void vector(void) __attribute__ ((signal, __INTR_ATTRS)); \ - void vector (void) -#else -# define SIGNAL(vector) \ - void vector (void) __attribute__ ((signal, __INTR_ATTRS)); \ - void vector (void) -#endif - -#endif /* DOXYGEN */ - -#if defined(__DOXYGEN__) -/** \def EMPTY_INTERRUPT(vector) - \ingroup avr_interrupts - - Defines an empty interrupt handler function. This will not generate - any prolog or epilog code and will only return from the ISR. Do not - define a function body as this will define it for you. - Example: - \code EMPTY_INTERRUPT(ADC_vect);\endcode */ -# define EMPTY_INTERRUPT(vector) -#else /* real code */ - -#ifdef __cplusplus -# define EMPTY_INTERRUPT(vector) \ - extern "C" void vector(void) __attribute__ ((signal,naked,__INTR_ATTRS)); \ - void vector (void) { __asm__ __volatile__ ("reti" ::); } -#else -# define EMPTY_INTERRUPT(vector) \ - void vector (void) __attribute__ ((signal,naked,__INTR_ATTRS)); \ - void vector (void) { __asm__ __volatile__ ("reti" ::); } -#endif - -#endif /* DOXYGEN */ - -#if defined(__DOXYGEN__) -/** \def ISR_ALIAS(vector, target_vector) - \ingroup avr_interrupts - - Aliases a given vector to another one in the same manner as the - ISR_ALIASOF attribute for the ISR() macro. Unlike the ISR_ALIASOF - attribute macro however, this is compatible for all versions of - GCC rather than just GCC version 4.2 onwards. - - \note This macro creates a trampoline function for the aliased - macro. This will result in a two cycle penalty for the aliased - vector compared to the ISR the vector is aliased to, due to the - JMP/RJMP opcode used. - - \deprecated - For new code, the use of ISR(..., ISR_ALIASOF(...)) is - recommended. - - Example: - \code - ISR(INT0_vect) - { - PORTB = 42; - } - - ISR_ALIAS(INT1_vect, INT0_vect); - \endcode - -*/ -# define ISR_ALIAS(vector, target_vector) -#else /* real code */ - -#ifdef __cplusplus -# if defined(__AVR_MEGA__) && __AVR_MEGA__ -# define ISR_ALIAS(vector, tgt) extern "C" void vector (void) \ - __attribute__((signal, naked, __INTR_ATTRS)); \ - void vector (void) { asm volatile ("jmp " __STRINGIFY(tgt) ::); } -# else /* !__AVR_MEGA */ -# define ISR_ALIAS(vector, tgt) extern "C" void vector (void) \ - __attribute__((signal, naked, __INTR_ATTRS)); \ - void vector (void) { asm volatile ("rjmp " __STRINGIFY(tgt) ::); } -# endif /* __AVR_MEGA__ */ -#else /* !__cplusplus */ -# if defined(__AVR_MEGA__) && __AVR_MEGA__ -# define ISR_ALIAS(vector, tgt) void vector (void) \ - __attribute__((signal, naked, __INTR_ATTRS)); \ - void vector (void) { asm volatile ("jmp " __STRINGIFY(tgt) ::); } -# else /* !__AVR_MEGA */ -# define ISR_ALIAS(vector, tgt) void vector (void) \ - __attribute__((signal, naked, __INTR_ATTRS)); \ - void vector (void) { asm volatile ("rjmp " __STRINGIFY(tgt) ::); } -# endif /* __AVR_MEGA__ */ -#endif /* __cplusplus */ - -#endif /* DOXYGEN */ - -#if defined(__DOXYGEN__) -/** \def reti() - \ingroup avr_interrupts - - Returns from an interrupt routine, enabling global interrupts. This should - be the last command executed before leaving an ISR defined with the ISR_NAKED - attribute. - - This macro actually compiles into a single line of assembly, so there is - no function call overhead. -*/ -# define reti() -#else /* !DOXYGEN */ -# define reti() __asm__ __volatile__ ("reti" ::) -#endif /* DOXYGEN */ - -#if defined(__DOXYGEN__) -/** \def BADISR_vect - \ingroup avr_interrupts - - \code #include \endcode - - This is a vector which is aliased to __vector_default, the vector - executed when an ISR fires with no accompanying ISR handler. This - may be used along with the ISR() macro to create a catch-all for - undefined but used ISRs for debugging purposes. -*/ -# define BADISR_vect -#else /* !DOXYGEN */ -# define BADISR_vect __vector_default -#endif /* DOXYGEN */ - -/** \name ISR attributes */ - -#if defined(__DOXYGEN__) -/** \def ISR_BLOCK - \ingroup avr_interrupts - - Identical to an ISR with no attributes specified. Global - interrupts are initially disabled by the AVR hardware when - entering the ISR, without the compiler modifying this state. - - Use this attribute in the attributes parameter of the ISR macro. -*/ -# define ISR_BLOCK - -/** \def ISR_NOBLOCK - \ingroup avr_interrupts - - ISR runs with global interrupts initially enabled. The interrupt - enable flag is activated by the compiler as early as possible - within the ISR to ensure minimal processing delay for nested - interrupts. - - This may be used to create nested ISRs, however care should be - taken to avoid stack overflows, or to avoid infinitely entering - the ISR for those cases where the AVR hardware does not clear the - respective interrupt flag before entering the ISR. - - Use this attribute in the attributes parameter of the ISR macro. -*/ -# define ISR_NOBLOCK - -/** \def ISR_NAKED - \ingroup avr_interrupts - - ISR is created with no prologue or epilogue code. The user code is - responsible for preservation of the machine state including the - SREG register, as well as placing a reti() at the end of the - interrupt routine. - - Use this attribute in the attributes parameter of the ISR macro. -*/ -# define ISR_NAKED - -/** \def ISR_ALIASOF(target_vector) - \ingroup avr_interrupts - - The ISR is linked to another ISR, specified by the vect parameter. - This is compatible with GCC 4.2 and greater only. - - Use this attribute in the attributes parameter of the ISR macro. -*/ -# define ISR_ALIASOF(target_vector) -#else /* !DOXYGEN */ -# define ISR_BLOCK -# define ISR_NOBLOCK __attribute__((interrupt)) -# define ISR_NAKED __attribute__((naked)) -# define ISR_ALIASOF(v) __attribute__((alias(__STRINGIFY(v)))) -#endif /* DOXYGEN */ - -/* \@} */ - -#endif diff --git a/arduino/hardware/tools/avr/avr/include/avr/io.h b/arduino/hardware/tools/avr/avr/include/avr/io.h deleted file mode 100644 index 4643948..0000000 --- a/arduino/hardware/tools/avr/avr/include/avr/io.h +++ /dev/null @@ -1,655 +0,0 @@ -/* Copyright (c) 2002,2003,2005,2006,2007 Marek Michalkiewicz, Joerg Wunsch - Copyright (c) 2007 Eric B. Weddington - All rights reserved. - - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - * Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - * Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in - the documentation and/or other materials provided with the - distribution. - - * Neither the name of the copyright holders nor the names of - contributors may be used to endorse or promote products derived - from this software without specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. */ - -/* $Id$ */ - -/** \file */ -/** \defgroup avr_io : AVR device-specific IO definitions - \code #include \endcode - - This header file includes the apropriate IO definitions for the - device that has been specified by the -mmcu= compiler - command-line switch. This is done by diverting to the appropriate - file <avr/ioXXXX.h> which should - never be included directly. Some register names common to all - AVR devices are defined directly within <avr/common.h>, - which is included in <avr/io.h>, - but most of the details come from the respective include file. - - Note that this file always includes the following files: - \code - #include - #include - #include - #include - \endcode - See \ref avr_sfr for more details about that header file. - - Included are definitions of the IO register set and their - respective bit values as specified in the Atmel documentation. - Note that inconsistencies in naming conventions, - so even identical functions sometimes get different names on - different devices. - - Also included are the specific names useable for interrupt - function definitions as documented - \ref avr_signames "here". - - Finally, the following macros are defined: - - - \b RAMEND -
- The last on-chip RAM address. -
- - \b XRAMEND -
- The last possible RAM location that is addressable. This is equal to - RAMEND for devices that do not allow for external RAM. For devices - that allow external RAM, this will be larger than RAMEND. -
- - \b E2END -
- The last EEPROM address. -
- - \b FLASHEND -
- The last byte address in the Flash program space. -
- - \b SPM_PAGESIZE -
- For devices with bootloader support, the flash pagesize - (in bytes) to be used for the \c SPM instruction. - - \b E2PAGESIZE -
- The size of the EEPROM page. - -*/ - -#ifndef _AVR_IO_H_ -#define _AVR_IO_H_ - -#include - -#if defined (__AVR_AT94K__) -# include -#elif defined (__AVR_AT43USB320__) -# include -#elif defined (__AVR_AT43USB355__) -# include -#elif defined (__AVR_AT76C711__) -# include -#elif defined (__AVR_AT86RF401__) -# include -#elif defined (__AVR_AT90PWM1__) -# include -#elif defined (__AVR_AT90PWM2__) -# include -#elif defined (__AVR_AT90PWM2B__) -# include -#elif defined (__AVR_AT90PWM3__) -# include -#elif defined (__AVR_AT90PWM3B__) -# include -#elif defined (__AVR_AT90PWM216__) -# include -#elif defined (__AVR_AT90PWM316__) -# include -#elif defined (__AVR_AT90PWM161__) -# include -#elif defined (__AVR_AT90PWM81__) -# include -#elif defined (__AVR_ATmega8U2__) -# include -#elif defined (__AVR_ATmega16M1__) -# include -#elif defined (__AVR_ATmega16U2__) -# include -#elif defined (__AVR_ATmega16U4__) -# include -#elif defined (__AVR_ATmega32C1__) -# include -#elif defined (__AVR_ATmega32M1__) -# include -#elif defined (__AVR_ATmega32U2__) -# include -#elif defined (__AVR_ATmega32U4__) -# include -#elif defined (__AVR_ATmega32U6__) -# include -#elif defined (__AVR_ATmega64C1__) -# include -#elif defined (__AVR_ATmega64M1__) -# include -#elif defined (__AVR_ATmega128__) -# include -#elif defined (__AVR_ATmega128A__) -# include -#elif defined (__AVR_ATmega1280__) -# include -#elif defined (__AVR_ATmega1281__) -# include -#elif defined (__AVR_ATmega1284__) -# include -#elif defined (__AVR_ATmega1284P__) -# include -#elif defined (__AVR_ATmega128RFA1__) -# include -#elif defined (__AVR_ATmega1284RFR2__) -# include -#elif defined (__AVR_ATmega128RFR2__) -# include -#elif defined (__AVR_ATmega2564RFR2__) -# include -#elif defined (__AVR_ATmega256RFR2__) -# include -#elif defined (__AVR_ATmega2560__) -# include -#elif defined (__AVR_ATmega2561__) -# include -#elif defined (__AVR_AT90CAN32__) -# include -#elif defined (__AVR_AT90CAN64__) -# include -#elif defined (__AVR_AT90CAN128__) -# include -#elif defined (__AVR_AT90USB82__) -# include -#elif defined (__AVR_AT90USB162__) -# include -#elif defined (__AVR_AT90USB646__) -# include -#elif defined (__AVR_AT90USB647__) -# include -#elif defined (__AVR_AT90USB1286__) -# include -#elif defined (__AVR_AT90USB1287__) -# include -#elif defined (__AVR_ATmega644RFR2__) -# include -#elif defined (__AVR_ATmega64RFR2__) -# include -#elif defined (__AVR_ATmega64__) -# include -#elif defined (__AVR_ATmega64A__) -# include -#elif defined (__AVR_ATmega640__) -# include -#elif defined (__AVR_ATmega644__) -# include -#elif defined (__AVR_ATmega644A__) -# include -#elif defined (__AVR_ATmega644P__) -# include -#elif defined (__AVR_ATmega644PA__) -# include -#elif defined (__AVR_ATmega645__) -# include -#elif (defined __AVR_ATmega645A__) -#include -#elif (defined __AVR_ATmega645P__) -#include -#elif defined (__AVR_ATmega6450__) -# include -#elif (defined __AVR_ATmega6450A__) -#include -#elif (defined __AVR_ATmega6450P__) -#include -#elif defined (__AVR_ATmega649__) -# include -#elif (defined __AVR_ATmega649A__) -#include -#elif defined (__AVR_ATmega6490__) -# include -#elif (defined __AVR_ATmega6490A__) -#include -#elif (defined __AVR_ATmega6490P__) -#include -#elif defined (__AVR_ATmega649P__) -# include -#elif defined (__AVR_ATmega64HVE__) -# include -#elif defined (__AVR_ATmega64HVE2__) -# include -#elif defined (__AVR_ATmega103__) -# include -#elif defined (__AVR_ATmega32__) -# include -#elif defined (__AVR_ATmega32A__) -# include -#elif defined (__AVR_ATmega323__) -# include -#elif defined (__AVR_ATmega324P__) -# include -#elif (defined __AVR_ATmega324A__) -#include -#elif defined (__AVR_ATmega324PA__) -# include -#elif defined (__AVR_ATmega325__) -# include -#elif (defined __AVR_ATmega325A__) -#include -#elif defined (__AVR_ATmega325P__) -# include -#elif defined (__AVR_ATmega325PA__) -# include -#elif defined (__AVR_ATmega3250__) -# include -#elif (defined __AVR_ATmega3250A__) -#include -#elif defined (__AVR_ATmega3250P__) -# include -#elif defined (__AVR_ATmega3250PA__) -# include -#elif defined (__AVR_ATmega328P__) -# include -#elif (defined __AVR_ATmega328__) -#include -#elif defined (__AVR_ATmega329__) -# include -#elif (defined __AVR_ATmega329A__) -#include -#elif defined (__AVR_ATmega329P__) -# include -#elif (defined __AVR_ATmega329PA__) -#include -#elif (defined __AVR_ATmega3290PA__) -#include -#elif defined (__AVR_ATmega3290__) -# include -#elif (defined __AVR_ATmega3290A__) -#include -#elif defined (__AVR_ATmega3290P__) -# include -#elif defined (__AVR_ATmega32HVB__) -# include -#elif defined (__AVR_ATmega32HVBREVB__) -# include -#elif defined (__AVR_ATmega406__) -# include -#elif defined (__AVR_ATmega16__) -# include -#elif defined (__AVR_ATmega16A__) -# include -#elif defined (__AVR_ATmega161__) -# include -#elif defined (__AVR_ATmega162__) -# include -#elif defined (__AVR_ATmega163__) -# include -#elif defined (__AVR_ATmega164P__) -# include -#elif (defined __AVR_ATmega164A__) -#include -#elif defined (__AVR_ATmega164PA__) -# include -#elif defined (__AVR_ATmega165__) -# include -#elif defined (__AVR_ATmega165A__) -# include -#elif defined (__AVR_ATmega165P__) -# include -#elif defined (__AVR_ATmega165PA__) -# include -#elif defined (__AVR_ATmega168__) -# include -#elif defined (__AVR_ATmega168A__) -# include -#elif defined (__AVR_ATmega168P__) -# include -#elif defined (__AVR_ATmega168PA__) -# include -#elif defined (__AVR_ATmega168PB__) -# include -#elif defined (__AVR_ATmega169__) -# include -#elif (defined __AVR_ATmega169A__) -#include -#elif defined (__AVR_ATmega169P__) -# include -#elif defined (__AVR_ATmega169PA__) -# include -#elif defined (__AVR_ATmega8HVA__) -# include -#elif defined (__AVR_ATmega16HVA__) -# include -#elif defined (__AVR_ATmega16HVA2__) -# include -#elif defined (__AVR_ATmega16HVB__) -# include -#elif defined (__AVR_ATmega16HVBREVB__) -# include -#elif defined (__AVR_ATmega8__) -# include -#elif defined (__AVR_ATmega8A__) -# include -#elif defined (__AVR_ATmega48__) -# include -#elif defined (__AVR_ATmega48A__) -# include -#elif defined (__AVR_ATmega48PA__) -# include -#elif defined (__AVR_ATmega48PB__) -# include -#elif defined (__AVR_ATmega48P__) -# include -#elif defined (__AVR_ATmega88__) -# include -#elif defined (__AVR_ATmega88A__) -# include -#elif defined (__AVR_ATmega88P__) -# include -#elif defined (__AVR_ATmega88PA__) -# include -#elif defined (__AVR_ATmega88PB__) -# include -#elif defined (__AVR_ATmega8515__) -# include -#elif defined (__AVR_ATmega8535__) -# include -#elif defined (__AVR_AT90S8535__) -# include -#elif defined (__AVR_AT90C8534__) -# include -#elif defined (__AVR_AT90S8515__) -# include -#elif defined (__AVR_AT90S4434__) -# include -#elif defined (__AVR_AT90S4433__) -# include -#elif defined (__AVR_AT90S4414__) -# include -#elif defined (__AVR_ATtiny22__) -# include -#elif defined (__AVR_ATtiny26__) -# include -#elif defined (__AVR_AT90S2343__) -# include -#elif defined (__AVR_AT90S2333__) -# include -#elif defined (__AVR_AT90S2323__) -# include -#elif defined (__AVR_AT90S2313__) -# include -#elif defined (__AVR_ATtiny4__) -# include -#elif defined (__AVR_ATtiny5__) -# include -#elif defined (__AVR_ATtiny9__) -# include -#elif defined (__AVR_ATtiny10__) -# include -#elif defined (__AVR_ATtiny20__) -# include -#elif defined (__AVR_ATtiny40__) -# include -#elif defined (__AVR_ATtiny2313__) -# include -#elif defined (__AVR_ATtiny2313A__) -# include -#elif defined (__AVR_ATtiny13__) -# include -#elif defined (__AVR_ATtiny13A__) -# include -#elif defined (__AVR_ATtiny25__) -# include -#elif defined (__AVR_ATtiny4313__) -# include -#elif defined (__AVR_ATtiny45__) -# include -#elif defined (__AVR_ATtiny85__) -# include -#elif defined (__AVR_ATtiny24__) -# include -#elif defined (__AVR_ATtiny24A__) -# include -#elif defined (__AVR_ATtiny44__) -# include -#elif defined (__AVR_ATtiny44A__) -# include -#elif defined (__AVR_ATtiny441__) -# include -#elif defined (__AVR_ATtiny84__) -# include -#elif defined (__AVR_ATtiny84A__) -# include -#elif defined (__AVR_ATtiny841__) -# include -#elif defined (__AVR_ATtiny261__) -# include -#elif defined (__AVR_ATtiny261A__) -# include -#elif defined (__AVR_ATtiny461__) -# include -#elif defined (__AVR_ATtiny461A__) -# include -#elif defined (__AVR_ATtiny861__) -# include -#elif defined (__AVR_ATtiny861A__) -# include -#elif defined (__AVR_ATtiny43U__) -# include -#elif defined (__AVR_ATtiny48__) -# include -#elif defined (__AVR_ATtiny88__) -# include -#elif defined (__AVR_ATtiny828__) -# include -#elif defined (__AVR_ATtiny87__) -# include -#elif defined (__AVR_ATtiny167__) -# include -#elif defined (__AVR_ATtiny1634__) -# include -#elif defined (__AVR_AT90SCR100__) -# include -#elif defined (__AVR_ATxmega8E5__) -# include -#elif defined (__AVR_ATxmega16A4__) -# include -#elif defined (__AVR_ATxmega16A4U__) -# include -#elif defined (__AVR_ATxmega16C4__) -# include -#elif defined (__AVR_ATxmega16D4__) -# include -#elif defined (__AVR_ATxmega16E5__) -# include -#elif defined (__AVR_ATxmega32A4__) -# include -#elif defined (__AVR_ATxmega32A4U__) -# include -#elif defined (__AVR_ATxmega32C3__) -# include -#elif defined (__AVR_ATxmega32C4__) -# include -#elif defined (__AVR_ATxmega32D3__) -# include -#elif defined (__AVR_ATxmega32D4__) -# include -#elif defined (__AVR_ATxmega32E5__) -# include -#elif defined (__AVR_ATxmega64A1__) -# include -#elif defined (__AVR_ATxmega64A1U__) -# include -#elif defined (__AVR_ATxmega64A3__) -# include -#elif defined (__AVR_ATxmega64A3U__) -# include -#elif defined (__AVR_ATxmega64A4U__) -# include -#elif defined (__AVR_ATxmega64B1__) -# include -#elif defined (__AVR_ATxmega64B3__) -# include -#elif defined (__AVR_ATxmega64C3__) -# include -#elif defined (__AVR_ATxmega64D3__) -# include -#elif defined (__AVR_ATxmega64D4__) -# include -#elif defined (__AVR_ATxmega128A1__) -# include -#elif defined (__AVR_ATxmega128A1U__) -# include -#elif defined (__AVR_ATxmega128A4U__) -# include -#elif defined (__AVR_ATxmega128A3__) -# include -#elif defined (__AVR_ATxmega128A3U__) -# include -#elif defined (__AVR_ATxmega128B1__) -# include -#elif defined (__AVR_ATxmega128B3__) -# include -#elif defined (__AVR_ATxmega128C3__) -# include -#elif defined (__AVR_ATxmega128D3__) -# include -#elif defined (__AVR_ATxmega128D4__) -# include -#elif defined (__AVR_ATxmega192A3__) -# include -#elif defined (__AVR_ATxmega192A3U__) -# include -#elif defined (__AVR_ATxmega192C3__) -# include -#elif defined (__AVR_ATxmega192D3__) -# include -#elif defined (__AVR_ATxmega256A3__) -# include -#elif defined (__AVR_ATxmega256A3U__) -# include -#elif defined (__AVR_ATxmega256A3B__) -# include -#elif defined (__AVR_ATxmega256A3BU__) -# include -#elif defined (__AVR_ATxmega256C3__) -# include -#elif defined (__AVR_ATxmega256D3__) -# include -#elif defined (__AVR_ATxmega384C3__) -# include -#elif defined (__AVR_ATxmega384D3__) -# include -#elif defined (__AVR_ATA5702M322__) -# include -#elif defined (__AVR_ATA5782__) -# include -#elif defined (__AVR_ATA5790__) -# include -#elif defined (__AVR_ATA5790N__) -# include -#elif defined (__AVR_ATA5791__) -# include -#elif defined (__AVR_ATA5831__) -# include -#elif defined (__AVR_ATA5272__) -# include -#elif defined (__AVR_ATA5505__) -# include -#elif defined (__AVR_ATA5795__) -# include -#elif defined (__AVR_ATA6285__) -# include -#elif defined (__AVR_ATA6286__) -# include -#elif defined (__AVR_ATA6289__) -# include -#elif defined (__AVR_ATA6612C__) -# include -#elif defined (__AVR_ATA6613C__) -# include -#elif defined (__AVR_ATA6614Q__) -# include -#elif defined (__AVR_ATA6616C__) -# include -#elif defined (__AVR_ATA6617C__) -# include -#elif defined (__AVR_ATA664251__) -# include -#elif defined (__AVR_ATA8210__) -# include -#elif defined (__AVR_ATA8510__) -# include -/* avr1: the following only supported for assembler programs */ -#elif defined (__AVR_ATtiny28__) -# include -#elif defined (__AVR_AT90S1200__) -# include -#elif defined (__AVR_ATtiny15__) -# include -#elif defined (__AVR_ATtiny12__) -# include -#elif defined (__AVR_ATtiny11__) -# include -#elif defined (__AVR_M3000__) -# include -#elif defined (__AVR_ATmega4809__) -# include -#elif defined (__AVR_ATmega4808__) -# include -#elif defined (__AVR_ATmega328PB__) -# include -#elif defined (__AVR_ATmega324PB__) -# include -#elif defined (__AVR_ATmega3209__) -# include -#elif defined (__AVR_ATmega3208__) -# include -#elif defined (__AVR_DEV_LIB_NAME__) -# define __concat__(a,b) a##b -# define __header1__(a,b) __concat__(a,b) -# define __AVR_DEVICE_HEADER__ -# include __AVR_DEVICE_HEADER__ -#else -# if !defined(__COMPILING_AVR_LIBC__) -# warning "device type not defined" -# endif -#endif - -#include - -#include - -#include - -#if __AVR_ARCH__ >= 100 -# include -#endif - -/* Include fuse.h after individual IO header files. */ -#include - -/* Include lock.h after individual IO header files. */ -#include - -#endif /* _AVR_IO_H_ */ diff --git a/arduino/hardware/tools/avr/avr/include/avr/io1200.h b/arduino/hardware/tools/avr/avr/include/avr/io1200.h deleted file mode 100644 index aeaf7d6..0000000 --- a/arduino/hardware/tools/avr/avr/include/avr/io1200.h +++ /dev/null @@ -1,274 +0,0 @@ -/* Copyright (c) 2002, Marek Michalkiewicz - All rights reserved. - - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - * Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - * Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in - the documentation and/or other materials provided with the - distribution. - - * Neither the name of the copyright holders nor the names of - contributors may be used to endorse or promote products derived - from this software without specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. */ - -/* $Id: io1200.h 2225 2011-03-02 16:27:26Z arcanum $ */ - -/* avr/io1200.h - definitions for AT90S1200 */ - -#ifndef _AVR_IO1200_H_ -#define _AVR_IO1200_H_ 1 - -/* This file should only be included from , never directly. */ - -#ifndef _AVR_IO_H_ -# error "Include instead of this file." -#endif - -#ifndef _AVR_IOXXX_H_ -# define _AVR_IOXXX_H_ "io1200.h" -#else -# error "Attempt to include more than one file." -#endif - -#ifndef __ASSEMBLER__ -# warning "MCU not supported by the C compiler" -#endif - -/* I/O registers */ - -/* 0x00..0x07 reserved */ - -/* Analog Comparator Control and Status Register */ -#define ACSR _SFR_IO8(0x08) - -/* 0x09..0x0F reserved */ - -#define PIND _SFR_IO8(0x10) -#define DDRD _SFR_IO8(0x11) -#define PORTD _SFR_IO8(0x12) - -/* 0x13..0x15 reserved */ - -#define PINB _SFR_IO8(0x16) -#define DDRB _SFR_IO8(0x17) -#define PORTB _SFR_IO8(0x18) - -/* 0x19..0x1B reserved */ - -/* EEPROM Control Register */ -#define EECR _SFR_IO8(0x1C) - -/* EEPROM Data Register */ -#define EEDR _SFR_IO8(0x1D) - -/* EEPROM Address Register */ -#define EEAR _SFR_IO8(0x1E) -#define EEARL _SFR_IO8(0x1E) - -/* 0x1F..0x20 reserved */ - -/* Watchdog Timer Control Register */ -#define WDTCR _SFR_IO8(0x21) - -/* 0x22..0x31 reserved */ - -#define TCNT0 _SFR_IO8(0x32) -#define TCCR0 _SFR_IO8(0x33) - -/* 0x34 reserved */ - -#define MCUCR _SFR_IO8(0x35) - -/* 0x36..0x37 reserved */ - -/* Timer/Counter Interrupt Flag Register */ -#define TIFR _SFR_IO8(0x38) - -/* Timer/Counter Interrupt MaSK Register */ -#define TIMSK _SFR_IO8(0x39) - -/* 0x3A reserved */ - -#define GIMSK _SFR_IO8(0x3B) - -/* 0x3C..0x3E reserved */ - -/* 0x3F SREG */ - -/* Interrupt vectors */ - -/* External Interrupt 0 */ -#define INT0_vect_num 1 -#define INT0_vect _VECTOR(1) -#define SIG_INTERRUPT0 _VECTOR(1) - -/* Timer/Counter0 Overflow */ -#define TIMER0_OVF_vect_num 2 -#define TIMER0_OVF_vect _VECTOR(2) -#define SIG_OVERFLOW0 _VECTOR(2) - -/* Analog Comparator */ -#define ANA_COMP_vect_num 3 -#define ANA_COMP_vect _VECTOR(3) -#define SIG_COMPARATOR _VECTOR(3) - -#define _VECTORS_SIZE 8 - -/* Bit numbers */ - -/* GIMSK */ -#define INT0 6 - -/* TIMSK */ -#define TOIE0 1 - -/* TIFR */ -#define TOV0 1 - -/* MCUCR */ -#define SE 5 -#define SM 4 -#define ISC01 1 -#define ISC00 0 - -/* TCCR0 */ -#define CS02 2 -#define CS01 1 -#define CS00 0 - -/* WDTCR */ -#define WDE 3 -#define WDP2 2 -#define WDP1 1 -#define WDP0 0 - -/* EECR */ -#undef EEMWE - -/* - PB7 = SCK - PB6 = MISO - PB5 = MOSI - PB1 = AIN1 - PB0 = AIN0 - */ - -/* PORTB */ -#define PB7 7 -#define PB6 6 -#define PB5 5 -#define PB4 4 -#define PB3 3 -#define PB2 2 -#define PB1 1 -#define PB0 0 - -/* DDRB */ -#define DDB7 7 -#define DDB6 6 -#define DDB5 5 -#define DDB4 4 -#define DDB3 3 -#define DDB2 2 -#define DDB1 1 -#define DDB0 0 - -/* PINB */ -#define PINB7 7 -#define PINB6 6 -#define PINB5 5 -#define PINB4 4 -#define PINB3 3 -#define PINB2 2 -#define PINB1 1 -#define PINB0 0 - -/* PORTD */ -#define PD6 6 -#define PD5 5 -#define PD4 4 -#define PD3 3 -#define PD2 2 -#define PD1 1 -#define PD0 0 - -/* DDRD */ -#define DDD6 6 -#define DDD5 5 -#define DDD4 4 -#define DDD3 3 -#define DDD2 2 -#define DDD1 1 -#define DDD0 0 - -/* PIND */ -#define PIND6 6 -#define PIND5 5 -#define PIND4 4 -#define PIND3 3 -#define PIND2 2 -#define PIND1 1 -#define PIND0 0 - -/* ACSR */ -#define ACD 7 -#define ACO 5 -#define ACI 4 -#define ACIE 3 -#define ACIS1 1 -#define ACIS0 0 - -/* EEPROM Control Register */ -#define EERIE 3 -#define EEMWE 2 -#define EEWE 1 -#define EERE 0 - -#undef ZH - -#define RAMSTART 0x60 -/* Last memory addresses */ -#define RAMEND 0x1F -#define XRAMEND 0x0 -#define E2END 0x3F -#define E2PAGESIZE 0 -#define FLASHEND 0x3FF - - -/* Fuses */ -#define FUSE_MEMORY_SIZE 1 - -/* Low Fuse Byte */ -#define FUSE_RCEN (unsigned char)~_BV(0) -#define FUSE_SPIEN (unsigned char)~_BV(5) -#define LFUSE_DEFAULT (0xFF) - - -/* Lock Bits */ -#define __LOCK_BITS_EXIST - - -/* Signature */ -#define SIGNATURE_0 0x1E -#define SIGNATURE_1 0x90 -#define SIGNATURE_2 0x01 - - -#endif /* _AVR_IO1200_H_ */ diff --git a/arduino/hardware/tools/avr/avr/include/avr/io2313.h b/arduino/hardware/tools/avr/avr/include/avr/io2313.h deleted file mode 100644 index a469f20..0000000 --- a/arduino/hardware/tools/avr/avr/include/avr/io2313.h +++ /dev/null @@ -1,385 +0,0 @@ -/* Copyright (c) 2002, Marek Michalkiewicz - All rights reserved. - - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - * Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - * Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in - the documentation and/or other materials provided with the - distribution. - - * Neither the name of the copyright holders nor the names of - contributors may be used to endorse or promote products derived - from this software without specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. */ - -/* $Id: io2313.h 2225 2011-03-02 16:27:26Z arcanum $ */ - -/* avr/io2313.h - definitions for AT90S2313 */ - -#ifndef _AVR_IO2313_H_ -#define _AVR_IO2313_H_ 1 - -/* This file should only be included from , never directly. */ - -#ifndef _AVR_IO_H_ -# error "Include instead of this file." -#endif - -#ifndef _AVR_IOXXX_H_ -# define _AVR_IOXXX_H_ "io2313.h" -#else -# error "Attempt to include more than one file." -#endif - -/* I/O registers */ - -/* Analog Comparator Control and Status Register */ -#define ACSR _SFR_IO8(0x08) - -/* UART Baud Rate Register */ -#define UBRR _SFR_IO8(0x09) - -/* UART Control Register */ -#define UCR _SFR_IO8(0x0A) - -/* UART Status Register */ -#define USR _SFR_IO8(0x0B) - -/* UART I/O Data Register */ -#define UDR _SFR_IO8(0x0C) - -/* Input Pins, Port D */ -#define PIND _SFR_IO8(0x10) - -/* Data Direction Register, Port D */ -#define DDRD _SFR_IO8(0x11) - -/* Data Register, Port D */ -#define PORTD _SFR_IO8(0x12) - -/* Input Pins, Port B */ -#define PINB _SFR_IO8(0x16) - -/* Data Direction Register, Port B */ -#define DDRB _SFR_IO8(0x17) - -/* Data Register, Port B */ -#define PORTB _SFR_IO8(0x18) - -/* EEPROM Control Register */ -#define EECR _SFR_IO8(0x1C) - -/* EEPROM Data Register */ -#define EEDR _SFR_IO8(0x1D) - -/* EEPROM Address Register */ -#define EEAR _SFR_IO8(0x1E) -#define EEARL _SFR_IO8(0x1E) - -/* Watchdog Timer Control Register */ -#define WDTCR _SFR_IO8(0x21) - -/* T/C 1 Input Capture Register */ -#define ICR1 _SFR_IO16(0x24) -#define ICR1L _SFR_IO8(0x24) -#define ICR1H _SFR_IO8(0x25) - -/* Output Compare Register 1 */ -#define OCR1 _SFR_IO16(0x2A) -#define OCR1L _SFR_IO8(0x2A) -#define OCR1H _SFR_IO8(0x2B) -#define OCR1A _SFR_IO16(0x2A) -#define OCR1AL _SFR_IO8(0x2A) -#define OCR1AH _SFR_IO8(0x2B) - -/* Timer/Counter 1 */ -#define TCNT1 _SFR_IO16(0x2C) -#define TCNT1L _SFR_IO8(0x2C) -#define TCNT1H _SFR_IO8(0x2D) - -/* Timer/Counter 1 Control and Status Register */ -#define TCCR1B _SFR_IO8(0x2E) - -/* Timer/Counter 1 Control Register */ -#define TCCR1A _SFR_IO8(0x2F) - -/* Timer/Counter 0 */ -#define TCNT0 _SFR_IO8(0x32) - -/* Timer/Counter 0 Control Register */ -#define TCCR0 _SFR_IO8(0x33) - -/* MCU general Control Register */ -#define MCUCR _SFR_IO8(0x35) - -/* Timer/Counter Interrupt Flag register */ -#define TIFR _SFR_IO8(0x38) - -/* Timer/Counter Interrupt MaSK register */ -#define TIMSK _SFR_IO8(0x39) - -/* General Interrupt Flag Register */ -#define GIFR _SFR_IO8(0x3A) - -/* General Interrupt MaSK register */ -#define GIMSK _SFR_IO8(0x3B) - -/* 0x3C..0x3D SP */ - -/* 0x3F SREG */ - -/* Interrupt vectors */ - -/* External Interrupt Request 0 */ -#define INT0_vect_num 1 -#define INT0_vect _VECTOR(1) -#define SIG_INTERRUPT0 _VECTOR(1) - -/* External Interrupt Request 1 */ -#define INT1_vect_num 2 -#define INT1_vect _VECTOR(2) -#define SIG_INTERRUPT1 _VECTOR(2) - -/* Timer/Counter1 Capture Event */ -#define TIMER1_CAPT1_vect_num 3 -#define TIMER1_CAPT1_vect _VECTOR(3) -#define SIG_INPUT_CAPTURE1 _VECTOR(3) - -/* Timer/Counter1 Compare Match */ -#define TIMER1_COMP1_vect_num 4 -#define TIMER1_COMP1_vect _VECTOR(4) -#define SIG_OUTPUT_COMPARE1A _VECTOR(4) - -/* Timer/Counter1 Overflow */ -#define TIMER1_OVF1_vect_num 5 -#define TIMER1_OVF1_vect _VECTOR(5) -#define SIG_OVERFLOW1 _VECTOR(5) - -/* Timer/Counter0 Overflow */ -#define TIMER0_OVF0_vect_num 6 -#define TIMER0_OVF0_vect _VECTOR(6) -#define SIG_OVERFLOW0 _VECTOR(6) - -/* UART, Rx Complete */ -#define UART_RX_vect_num 7 -#define UART_RX_vect _VECTOR(7) -#define SIG_UART_RECV _VECTOR(7) - -/* UART Data Register Empty */ -#define UART_UDRE_vect_num 8 -#define UART_UDRE_vect _VECTOR(8) -#define SIG_UART_DATA _VECTOR(8) - -/* UART, Tx Complete */ -#define UART_TX_vect_num 9 -#define UART_TX_vect _VECTOR(9) -#define SIG_UART_TRANS _VECTOR(9) - -/* Analog Comparator */ -#define ANA_COMP_vect_num 10 -#define ANA_COMP_vect _VECTOR(10) -#define SIG_COMPARATOR _VECTOR(10) - -#define _VECTORS_SIZE 22 - -/* - * The Register Bit names are represented by their bit number (0-7). - */ - -/* General Interrupt MaSK register */ -#define INT1 7 -#define INT0 6 - -/* General Interrupt Flag Register */ -#define INTF1 7 -#define INTF0 6 - -/* Timer/Counter Interrupt MaSK register */ -#define TOIE1 7 -#define OCIE1A 6 -#define TICIE 3 /* old name */ -#define TICIE1 3 -#define TOIE0 1 - -/* Timer/Counter Interrupt Flag register */ -#define TOV1 7 -#define OCF1A 6 -#define ICF1 3 -#define TOV0 1 - -/* MCU general Control Register */ -#define SE 5 -#define SM 4 -#define ISC11 3 -#define ISC10 2 -#define ISC01 1 -#define ISC00 0 - -/* Timer/Counter 0 Control Register */ -#define CS02 2 -#define CS01 1 -#define CS00 0 - -/* Timer/Counter 1 Control Register */ -#define COM1A1 7 -#define COM1A0 6 -#define PWM11 1 -#define PWM10 0 - -/* Timer/Counter 1 Control and Status Register */ -#define ICNC1 7 -#define ICES1 6 -#define CTC1 3 -#define CS12 2 -#define CS11 1 -#define CS10 0 - -/* Watchdog Timer Control Register */ -#define WDTOE 4 -#define WDE 3 -#define WDP2 2 -#define WDP1 1 -#define WDP0 0 - -/* EEPROM Control Register */ -#define EEMWE 2 -#define EEWE 1 -#define EERE 0 - -/* Data Register, Port B */ -#define PB7 7 -#define PB6 6 -#define PB5 5 -#define PB4 4 -#define PB3 3 -#define PB2 2 -#define PB1 1 -#define PB0 0 - -/* Data Direction Register, Port B */ -#define DDB7 7 -#define DDB6 6 -#define DDB5 5 -#define DDB4 4 -#define DDB3 3 -#define DDB2 2 -#define DDB1 1 -#define DDB0 0 - -/* Input Pins, Port B */ -#define PINB7 7 -#define PINB6 6 -#define PINB5 5 -#define PINB4 4 -#define PINB3 3 -#define PINB2 2 -#define PINB1 1 -#define PINB0 0 - -/* Data Register, Port D */ -#define PD6 6 -#define PD5 5 -#define PD4 4 -#define PD3 3 -#define PD2 2 -#define PD1 1 -#define PD0 0 - -/* Data Direction Register, Port D */ -#define DDD6 6 -#define DDD5 5 -#define DDD4 4 -#define DDD3 3 -#define DDD2 2 -#define DDD1 1 -#define DDD0 0 - -/* Input Pins, Port D */ -#define PIND6 6 -#define PIND5 5 -#define PIND4 4 -#define PIND3 3 -#define PIND2 2 -#define PIND1 1 -#define PIND0 0 - -/* UART Status Register */ -#define RXC 7 -#define TXC 6 -#define UDRE 5 -#define FE 4 -#define DOR 3 - -/* UART Control Register */ -#define RXCIE 7 -#define TXCIE 6 -#define UDRIE 5 -#define RXEN 4 -#define TXEN 3 -#define CHR9 2 -#define RXB8 1 -#define TXB8 0 - -/* Analog Comparator Control and Status Register */ -#define ACD 7 -#define ACO 5 -#define ACI 4 -#define ACIE 3 -#define ACIC 2 -#define ACIS1 1 -#define ACIS0 0 - -/* EEPROM Control Register */ -#define EERIE 3 -#define EEMWE 2 -#define EEWE 1 -#define EERE 0 - -/* Constants */ -#define RAMSTART 0x60 -#define RAMEND 0xDF -#define XRAMEND RAMEND -#define E2END 0x7F -#define E2PAGESIZE 0 -#define FLASHEND 0x07FF - - -/* Fuses */ -#define FUSE_MEMORY_SIZE 1 - -/* Low Fuse Byte */ -#define FUSE_FSTRT (unsigned char)~_BV(0) -#define FUSE_SPIEN (unsigned char)~_BV(5) -#define LFUSE_DEFAULT (0xFF) - - -/* Lock Bits */ -#define __LOCK_BITS_EXIST - - -/* Signature */ -#define SIGNATURE_0 0x1E -#define SIGNATURE_1 0x91 -#define SIGNATURE_2 0x01 - -#define SLEEP_MODE_IDLE 0 -#define SLEEP_MODE_PWR_DOWN _BV(SM) - - -#endif /* _AVR_IO2313_H_ */ diff --git a/arduino/hardware/tools/avr/avr/include/avr/io2323.h b/arduino/hardware/tools/avr/avr/include/avr/io2323.h deleted file mode 100644 index cd1311f..0000000 --- a/arduino/hardware/tools/avr/avr/include/avr/io2323.h +++ /dev/null @@ -1,210 +0,0 @@ -/* Copyright (c) 2002, Marek Michalkiewicz - All rights reserved. - - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - * Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - * Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in - the documentation and/or other materials provided with the - distribution. - - * Neither the name of the copyright holders nor the names of - contributors may be used to endorse or promote products derived - from this software without specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. */ - -/* $Id: io2323.h 2225 2011-03-02 16:27:26Z arcanum $ */ - -/* avr/io2323.h - definitions for AT90S2323 */ - -#ifndef _AVR_IO2323_H_ -#define _AVR_IO2323_H_ 1 - -/* This file should only be included from , never directly. */ - -#ifndef _AVR_IO_H_ -# error "Include instead of this file." -#endif - -#ifndef _AVR_IOXXX_H_ -# define _AVR_IOXXX_H_ "io2323.h" -#else -# error "Attempt to include more than one file." -#endif - -/* I/O registers */ - -/* Input Pins, Port B */ -#define PINB _SFR_IO8(0x16) - -/* Data Direction Register, Port B */ -#define DDRB _SFR_IO8(0x17) - -/* Data Register, Port B */ -#define PORTB _SFR_IO8(0x18) - -/* EEPROM Control Register */ -#define EECR _SFR_IO8(0x1C) - -/* EEPROM Data Register */ -#define EEDR _SFR_IO8(0x1D) - -/* EEPROM Address Register */ -#define EEAR _SFR_IO8(0x1E) -#define EEARL _SFR_IO8(0x1E) - -/* Watchdog Timer Control Register */ -#define WDTCR _SFR_IO8(0x21) - -/* Timer/Counter 0 */ -#define TCNT0 _SFR_IO8(0x32) - -/* Timer/Counter 0 Control Register */ -#define TCCR0 _SFR_IO8(0x33) - -/* MCU Status Register */ -#define MCUSR _SFR_IO8(0x34) - -/* MCU general Control Register */ -#define MCUCR _SFR_IO8(0x35) - -/* Timer/Counter Interrupt Flag register */ -#define TIFR _SFR_IO8(0x38) - -/* Timer/Counter Interrupt MaSK register */ -#define TIMSK _SFR_IO8(0x39) - -/* General Interrupt Flag register */ -#define GIFR _SFR_IO8(0x3A) - -/* General Interrupt MaSK register */ -#define GIMSK _SFR_IO8(0x3B) - -/* 0x3D..0x3E SP */ - -/* 0x3F SREG */ - -/* Interrupt vectors */ - -/* External Interrupt 0 */ -#define INT0_vect_num 1 -#define INT0_vect _VECTOR(1) -#define SIG_INTERRUPT0 _VECTOR(1) - -/* Timer/Counter0 Overflow */ -#define TIMER0_OVF0_vect_num 2 -#define TIMER0_OVF0_vect _VECTOR(2) -#define SIG_OVERFLOW0 _VECTOR(2) - -#define _VECTORS_SIZE 6 - -/* - The Register Bit names are represented by their bit number (0-7). - */ - -/* General Interrupt MaSK register */ -#define INT0 6 -#define INTF0 6 - -/* General Interrupt Flag Register */ -#define TOIE0 1 -#define TOV0 1 - -/* MCU general Control Register */ -#define SE 5 -#define SM 4 -#define ISC01 1 -#define ISC00 0 - -/* Timer/Counter 0 Control Register */ -#define CS02 2 -#define CS01 1 -#define CS00 0 - -/* Watchdog Timer Control Register */ -#define WDTOE 4 -#define WDE 3 -#define WDP2 2 -#define WDP1 1 -#define WDP0 0 - -/* - PB2 = SCK/T0 - PB1 = MISO/INT0 - PB0 = MOSI - */ - -/* Data Register, Port B */ -#define PB2 2 -#define PB1 1 -#define PB0 0 - -/* Data Direction Register, Port B */ -#define DDB2 2 -#define DDB1 1 -#define DDB0 0 - -/* Input Pins, Port B */ -#define PINB2 2 -#define PINB1 1 -#define PINB0 0 - -/* EEPROM Control Register */ -#define EERIE 3 -#define EEMWE 2 -#define EEWE 1 -#define EERE 0 - -/* Constants */ -#define RAMSTART 0x60 -#define RAMEND 0xDF -#define XRAMEND RAMEND -#define E2END 0x7F -#define E2PAGESIZE 0 -#define FLASHEND 0x07FF - - -/* Fuses */ -#define FUSE_MEMORY_SIZE 1 - -/* Low Fuse Byte */ -#define FUSE_FSTRT (unsigned char)~_BV(0) -#define FUSE_SPIEN (unsigned char)~_BV(5) -#define LFUSE_DEFAULT (0xFF) - - -/* Lock Bits */ -#define __LOCK_BITS_EXIST - - -/* Signature */ -#define SIGNATURE_0 0x1E -#define SIGNATURE_1 0x91 -#define SIGNATURE_2 0x02 - -#define SLEEP_MODE_IDLE 0 -#define SLEEP_MODE_PWR_DOWN _BV(SM) - - -#endif /* _AVR_IO2323_H_ */ - -/* Signature */ -#define SIGNATURE_0 0x1E -#define SIGNATURE_1 0x91 -#define SIGNATURE_2 0x02 - diff --git a/arduino/hardware/tools/avr/avr/include/avr/io2333.h b/arduino/hardware/tools/avr/avr/include/avr/io2333.h deleted file mode 100644 index 7dccf42..0000000 --- a/arduino/hardware/tools/avr/avr/include/avr/io2333.h +++ /dev/null @@ -1,461 +0,0 @@ -/* Copyright (c) 2002, Marek Michalkiewicz - All rights reserved. - - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - * Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - * Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in - the documentation and/or other materials provided with the - distribution. - - * Neither the name of the copyright holders nor the names of - contributors may be used to endorse or promote products derived - from this software without specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. */ - -/* $Id: io2333.h 2225 2011-03-02 16:27:26Z arcanum $ */ - -/* avr/io2333.h - definitions for AT90S2333 */ - -#ifndef _AVR_IO2333_H_ -#define _AVR_IO2333_H_ 1 - -/* This file should only be included from , never directly. */ - -#ifndef _AVR_IO_H_ -# error "Include instead of this file." -#endif - -#ifndef _AVR_IOXXX_H_ -# define _AVR_IOXXX_H_ "io2333.h" -#else -# error "Attempt to include more than one file." -#endif - -/* I/O registers */ - -/* UART Baud Rate Register high */ -#define UBRRH _SFR_IO8(0x03) - -/* ADC Data register */ -#ifndef __ASSEMBLER__ -#define ADC _SFR_IO16(0x04) -#endif -#define ADCW _SFR_IO16(0x04) -#define ADCL _SFR_IO8(0x04) -#define ADCH _SFR_IO8(0x05) - -/* ADC Control and Status Register */ -#define ADCSR _SFR_IO8(0x06) - -/* ADC MUX */ -#define ADMUX _SFR_IO8(0x07) - -/* Analog Comparator Control and Status Register */ -#define ACSR _SFR_IO8(0x08) - -/* UART Baud Rate Register */ -#define UBRR _SFR_IO8(0x09) - -/* UART Control/Status Registers */ -#define UCSRB _SFR_IO8(0x0A) -#define UCSRA _SFR_IO8(0x0B) - -/* UART I/O Data Register */ -#define UDR _SFR_IO8(0x0C) - -/* SPI Control Register */ -#define SPCR _SFR_IO8(0x0D) - -/* SPI Status Register */ -#define SPSR _SFR_IO8(0x0E) - -/* SPI I/O Data Register */ -#define SPDR _SFR_IO8(0x0F) - -/* Input Pins, Port D */ -#define PIND _SFR_IO8(0x10) - -/* Data Direction Register, Port D */ -#define DDRD _SFR_IO8(0x11) - -/* Data Register, Port D */ -#define PORTD _SFR_IO8(0x12) - -/* Input Pins, Port C */ -#define PINC _SFR_IO8(0x13) - -/* Data Direction Register, Port C */ -#define DDRC _SFR_IO8(0x14) - -/* Data Register, Port C */ -#define PORTC _SFR_IO8(0x15) - -/* Input Pins, Port B */ -#define PINB _SFR_IO8(0x16) - -/* Data Direction Register, Port B */ -#define DDRB _SFR_IO8(0x17) - -/* Data Register, Port B */ -#define PORTB _SFR_IO8(0x18) - -/* EEPROM Control Register */ -#define EECR _SFR_IO8(0x1C) - -/* EEPROM Data Register */ -#define EEDR _SFR_IO8(0x1D) - -/* EEPROM Address Register */ -#define EEAR _SFR_IO8(0x1E) -#define EEARL _SFR_IO8(0x1E) - -/* Watchdog Timer Control Register */ -#define WDTCR _SFR_IO8(0x21) - -/* T/C 1 Input Capture Register */ -#define ICR1 _SFR_IO16(0x26) -#define ICR1L _SFR_IO8(0x26) -#define ICR1H _SFR_IO8(0x27) - -/* Timer/Counter1 Output Compare Register A */ -#define OCR1 _SFR_IO16(0x2A) -#define OCR1L _SFR_IO8(0x2A) -#define OCR1H _SFR_IO8(0x2B) - -/* Timer/Counter 1 */ -#define TCNT1 _SFR_IO16(0x2C) -#define TCNT1L _SFR_IO8(0x2C) -#define TCNT1H _SFR_IO8(0x2D) - -/* Timer/Counter 1 Control and Status Register */ -#define TCCR1B _SFR_IO8(0x2E) - -/* Timer/Counter 1 Control Register */ -#define TCCR1A _SFR_IO8(0x2F) - -/* Timer/Counter 0 */ -#define TCNT0 _SFR_IO8(0x32) - -/* Timer/Counter 0 Control Register */ -#define TCCR0 _SFR_IO8(0x33) - -/* MCU general Status Register */ -#define MCUSR _SFR_IO8(0x34) - -/* MCU general Control Register */ -#define MCUCR _SFR_IO8(0x35) - -/* Timer/Counter Interrupt Flag register */ -#define TIFR _SFR_IO8(0x38) - -/* Timer/Counter Interrupt MaSK register */ -#define TIMSK _SFR_IO8(0x39) - -/* General Interrupt Flag Register */ -#define GIFR _SFR_IO8(0x3A) - -/* General Interrupt MaSK register */ -#define GIMSK _SFR_IO8(0x3B) - -/* Interrupt vectors */ - -/* External Interrupt 0 */ -#define INT0_vect_num 1 -#define INT0_vect _VECTOR(1) -#define SIG_INTERRUPT0 _VECTOR(1) - -/* External Interrupt 1 */ -#define INT1_vect_num 2 -#define INT1_vect _VECTOR(2) -#define SIG_INTERRUPT1 _VECTOR(2) - -/* Timer/Counter Capture Event */ -#define TIMER1_CAPT_vect_num 3 -#define TIMER1_CAPT_vect _VECTOR(3) -#define SIG_INPUT_CAPTURE1 _VECTOR(3) - -/* Timer/Counter1 Compare Match */ -#define TIMER1_COMP_vect_num 4 -#define TIMER1_COMP_vect _VECTOR(4) -#define SIG_OUTPUT_COMPARE1A _VECTOR(4) - -/* Timer/Counter1 Overflow */ -#define TIMER1_OVF_vect_num 5 -#define TIMER1_OVF_vect _VECTOR(5) -#define SIG_OVERFLOW1 _VECTOR(5) - -/* Timer/Counter0 Overflow */ -#define TIMER0_OVF_vect_num 6 -#define TIMER0_OVF_vect _VECTOR(6) -#define SIG_OVERFLOW0 _VECTOR(6) - -/* Serial Transfer Complete */ -#define SPI_STC_vect_num 7 -#define SPI_STC_vect _VECTOR(7) -#define SIG_SPI _VECTOR(7) - -/* UART, Rx Complete */ -#define UART_RX_vect_num 8 -#define UART_RX_vect _VECTOR(8) -#define SIG_UART_RECV _VECTOR(8) - -/* UART Data Register Empty */ -#define UART_UDRE_vect_num 9 -#define UART_UDRE_vect _VECTOR(9) -#define SIG_UART_DATA _VECTOR(9) - -/* UART, Tx Complete */ -#define UART_TX_vect_num 10 -#define UART_TX_vect _VECTOR(10) -#define SIG_UART_TRANS _VECTOR(10) - -/* ADC Conversion Complete */ -#define ADC_vect_num 11 -#define ADC_vect _VECTOR(11) -#define SIG_ADC _VECTOR(11) - -/* EEPROM Ready */ -#define EE_RDY_vect_num 12 -#define EE_RDY_vect _VECTOR(12) -#define SIG_EEPROM_READY _VECTOR(12) - -/* Analog Comparator */ -#define ANA_COMP_vect_num 13 -#define ANA_COMP_vect _VECTOR(13) -#define SIG_COMPARATOR _VECTOR(13) - -#define _VECTORS_SIZE 28 - -/* - The Register Bit names are represented by their bit number (0-7). -*/ - -/* MCU general Status Register */ -#define WDRF 3 -#define BORF 2 -#define EXTRF 1 -#define PORF 0 - -/* General Interrupt MaSK register */ -#define INT1 7 -#define INT0 6 - -/* General Interrupt Flag Register */ -#define INTF1 7 -#define INTF0 6 - -/* Timer/Counter Interrupt MaSK register */ -#define TOIE1 7 -#define OCIE1 6 -#define TICIE1 3 -#define TOIE0 1 - -/* Timer/Counter Interrupt Flag register */ -#define TOV1 7 -#define OCF1 6 -#define ICF1 3 -#define TOV0 1 - -/* MCU general Control Register */ -#define SE 5 -#define SM 4 -#define ISC11 3 -#define ISC10 2 -#define ISC01 1 -#define ISC00 0 - -/* Timer/Counter 0 Control Register */ -#define CS02 2 -#define CS01 1 -#define CS00 0 - -/* Timer/Counter 1 Control Register */ -#define COM11 7 -#define COM10 6 -#define PWM11 1 -#define PWM10 0 - -/* Timer/Counter 1 Control and Status Register */ -#define ICNC1 7 -#define ICES1 6 -#define CTC1 3 -#define CS12 2 -#define CS11 1 -#define CS10 0 - -/* Watchdog Timer Control Register */ -#define WDTOE 4 -#define WDE 3 -#define WDP2 2 -#define WDP1 1 -#define WDP0 0 - -/* SPI Control Register */ -#define SPIE 7 -#define SPE 6 -#define DORD 5 -#define MSTR 4 -#define CPOL 3 -#define CPHA 2 -#define SPR1 1 -#define SPR0 0 - -/* SPI Status Register */ -#define SPIF 7 -#define WCOL 6 - -/* UART Status Register */ -#define RXC 7 -#define TXC 6 -#define UDRE 5 -#define FE 4 -#define DOR 3 -#define MPCM 0 - -/* UART Control Register */ -#define RXCIE 7 -#define TXCIE 6 -#define UDRIE 5 -#define RXEN 4 -#define TXEN 3 -#define CHR9 2 -#define RXB8 1 -#define TXB8 0 - -/* Analog Comparator Control and Status Register */ -#define ACD 7 -#define AINBG 6 -#define ACO 5 -#define ACI 4 -#define ACIE 3 -#define ACIC 2 -#define ACIS1 1 -#define ACIS0 0 - -/* ADC MUX */ -#define ACDBG 6 -#define MUX2 2 -#define MUX1 1 -#define MUX0 0 - -/* ADC Control and Status Register */ -#define ADEN 7 -#define ADSC 6 -#define ADFR 5 -#define ADIF 4 -#define ADIE 3 -#define ADPS2 2 -#define ADPS1 1 -#define ADPS0 0 - -/* Data Register, Port B */ -#define PB5 5 -#define PB4 4 -#define PB3 3 -#define PB2 2 -#define PB1 1 -#define PB0 0 - -/* Data Direction Register, Port B */ -#define DDB5 5 -#define DDB4 4 -#define DDB3 3 -#define DDB2 2 -#define DDB1 1 -#define DDB0 0 - -/* Input Pins, Port B */ -#define PINB5 5 -#define PINB4 4 -#define PINB3 3 -#define PINB2 2 -#define PINB1 1 -#define PINB0 0 - -/* Data Register, Port C */ -#define PC5 5 -#define PC4 4 -#define PC3 3 -#define PC2 2 -#define PC1 1 -#define PC0 0 - -/* Data Direction Register, Port C */ -#define DDC5 5 -#define DDC4 4 -#define DDC3 3 -#define DDC2 2 -#define DDC1 1 -#define DDC0 0 - -/* Input Pins, Port C */ -#define PINC5 5 -#define PINC4 4 -#define PINC3 3 -#define PINC2 2 -#define PINC1 1 -#define PINC0 0 - -/* Data Register, Port D */ -#define PD7 7 -#define PD6 6 -#define PD5 5 -#define PD4 4 -#define PD3 3 -#define PD2 2 -#define PD1 1 -#define PD0 0 - -/* Data Direction Register, Port D */ -#define DDD7 7 -#define DDD6 6 -#define DDD5 5 -#define DDD4 4 -#define DDD3 3 -#define DDD2 2 -#define DDD1 1 -#define DDD0 0 - -/* Input Pins, Port D */ -#define PIND7 7 -#define PIND6 6 -#define PIND5 5 -#define PIND4 4 -#define PIND3 3 -#define PIND2 2 -#define PIND1 1 -#define PIND0 0 - -/* EEPROM Control Register */ -#define EERIE 3 -#define EEMWE 2 -#define EEWE 1 -#define EERE 0 - -/* Constants */ -#define RAMSTART 0x60 -#define RAMEND 0xDF /*Last On-Chip SRAM location*/ -#define XRAMEND RAMEND -#define E2END 0x7F -#define FLASHEND 0x7FF - -#define SLEEP_MODE_IDLE 0 -#define SLEEP_MODE_PWR_DOWN _BV(SM) - -#endif /* _AVR_IO2333_H_ */ diff --git a/arduino/hardware/tools/avr/avr/include/avr/io2343.h b/arduino/hardware/tools/avr/avr/include/avr/io2343.h deleted file mode 100644 index da40c62..0000000 --- a/arduino/hardware/tools/avr/avr/include/avr/io2343.h +++ /dev/null @@ -1,214 +0,0 @@ -/* Copyright (c) 2002, Marek Michalkiewicz - All rights reserved. - - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - * Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - * Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in - the documentation and/or other materials provided with the - distribution. - - * Neither the name of the copyright holders nor the names of - contributors may be used to endorse or promote products derived - from this software without specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. */ - -/* $Id: io2343.h 2225 2011-03-02 16:27:26Z arcanum $ */ - -/* avr/io2343.h - definitions for AT90S2343 */ - -#ifndef _AVR_IO2343_H_ -#define _AVR_IO2343_H_ 1 - -/* This file should only be included from , never directly. */ - -#ifndef _AVR_IO_H_ -# error "Include instead of this file." -#endif - -#ifndef _AVR_IOXXX_H_ -# define _AVR_IOXXX_H_ "io2343.h" -#else -# error "Attempt to include more than one file." -#endif - -/* I/O registers */ - -/* Input Pins, Port B */ -#define PINB _SFR_IO8(0x16) - -/* Data Direction Register, Port B */ -#define DDRB _SFR_IO8(0x17) - -/* Data Register, Port B */ -#define PORTB _SFR_IO8(0x18) - -/* EEPROM Control Register */ -#define EECR _SFR_IO8(0x1C) - -/* EEPROM Data Register */ -#define EEDR _SFR_IO8(0x1D) - -/* EEPROM Address Register */ -#define EEAR _SFR_IO8(0x1E) -#define EEARL _SFR_IO8(0x1E) - -/* Watchdog Timer Control Register */ -#define WDTCR _SFR_IO8(0x21) - -/* Timer/Counter 0 */ -#define TCNT0 _SFR_IO8(0x32) - -/* Timer/Counter 0 Control Register */ -#define TCCR0 _SFR_IO8(0x33) - -/* MCU Status Register */ -#define MCUSR _SFR_IO8(0x34) - -/* MCU general Control Register */ -#define MCUCR _SFR_IO8(0x35) - -/* Timer/Counter Interrupt Flag register */ -#define TIFR _SFR_IO8(0x38) - -/* Timer/Counter Interrupt MaSK register */ -#define TIMSK _SFR_IO8(0x39) - -/* General Interrupt Flag register */ -#define GIFR _SFR_IO8(0x3A) - -/* General Interrupt MaSK register */ -#define GIMSK _SFR_IO8(0x3B) - -/* 0x3D..0x3E SP */ - -/* 0x3F SREG */ - -/* Interrupt vectors */ - -/* External Interrupt 0 */ -#define INT0_vect_num 1 -#define INT0_vect _VECTOR(1) -#define SIG_INTERRUPT0 _VECTOR(1) - -/* Timer/Counter0 Overflow */ -#define TIMER0_OVF0_vect_num 2 -#define TIMER0_OVF0_vect _VECTOR(2) -#define SIG_OVERFLOW0 _VECTOR(2) - -#define _VECTORS_SIZE 6 - -/* - The Register Bit names are represented by their bit number (0-7). - */ - -/* General Interrupt MaSK register */ -#define INT0 6 -#define INTF0 6 - -/* General Interrupt Flag Register */ -#define TOIE0 1 -#define TOV0 1 - -/* MCU general Control Register */ -#define SE 5 -#define SM 4 -#define ISC01 1 -#define ISC00 0 - -/* MCU Status Register */ -#define PORF 0 -#define EXTRF 1 - -/* Timer/Counter 0 Control Register */ -#define CS02 2 -#define CS01 1 -#define CS00 0 - -/* Watchdog Timer Control Register */ -#define WDTOE 4 -#define WDE 3 -#define WDP2 2 -#define WDP1 1 -#define WDP0 0 - -/* - PB3 = CLOCK - PB2 = SCK/T0 - PB1 = MISO/INT0 - PB0 = MOSI - */ - -/* Data Register, Port B */ -#define PB4 4 -#define PB3 3 -#define PB2 2 -#define PB1 1 -#define PB0 0 - -/* Data Direction Register, Port B */ -#define DDB4 4 -#define DDB3 3 -#define DDB2 2 -#define DDB1 1 -#define DDB0 0 - -/* Input Pins, Port B */ -#define PINB4 4 -#define PINB3 3 -#define PINB2 2 -#define PINB1 1 -#define PINB0 0 - -/* EEPROM Control Register */ -#define EERIE 3 -#define EEMWE 2 -#define EEWE 1 -#define EERE 0 - -/* Constants */ -#define RAMSTART 0x60 -#define RAMEND 0xDF -#define XRAMEND RAMEND -#define E2END 0x7F -#define E2PAGESIZE 0 -#define FLASHEND 0x07FF - - -/* Fuses */ -#define FUSE_MEMORY_SIZE 1 - -/* Low Fuse Byte */ -#define FUSE_RCEN (unsigned char)~_BV(0) -#define FUSE_SPIEN (unsigned char)~_BV(5) -#define LFUSE_DEFAULT (0xFF) - - -/* Lock Bits */ -#define __LOCK_BITS_EXIST - - -/* Signature */ -#define SIGNATURE_0 0x1E -#define SIGNATURE_1 0x91 -#define SIGNATURE_2 0x03 - -#define SLEEP_MODE_IDLE 0 -#define SLEEP_MODE_PWR_DOWN _BV(SM) - -#endif /* _AVR_IO2343_H_ */ diff --git a/arduino/hardware/tools/avr/avr/include/avr/io43u32x.h b/arduino/hardware/tools/avr/avr/include/avr/io43u32x.h deleted file mode 100644 index 96d2308..0000000 --- a/arduino/hardware/tools/avr/avr/include/avr/io43u32x.h +++ /dev/null @@ -1,440 +0,0 @@ -/* Copyright (c) 2003,2005 Keith Gudger - All rights reserved. - - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - * Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - * Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in - the documentation and/or other materials provided with the - distribution. - - * Neither the name of the copyright holders nor the names of - contributors may be used to endorse or promote products derived - from this software without specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. */ - -/* $Id: io43u32x.h 1873 2009-02-11 17:53:39Z arcanum $ */ - -/* avr/io43u32x.h - definitions for AT43USB32x */ - -#ifndef _AVR_IO43U32X_H_ -#define _AVR_IO43U32X_H_ 1 - -/* This file should only be included from , never directly. */ - -#ifndef _AVR_IO_H_ -# error "Include instead of this file." -#endif - -#ifndef _AVR_IOXXX_H_ -# define _AVR_IOXXX_H_ "io43u32x.h" -#else -# error "Attempt to include more than one file." -#endif - -/* I/O registers */ - -/* Analog Comparator Control and Status Register */ -#define ACSR _SFR_IO8(0x08) - -/* UART Baud Rate Register */ -#define UBRR _SFR_IO8(0x09) - -/* UART Control Register */ -#define UCR _SFR_IO8(0x0A) - -/* UART Status Register */ -#define USR _SFR_IO8(0x0B) - -/* UART I/O Data Register */ -#define UDR _SFR_IO8(0x0C) - -/* Input Pins, Port E */ // new port for 43324/6 -#define PINE _SFR_IO8(0x01) - -/* Data Direction Register, Port E */ -#define DDRE _SFR_IO8(0x02) - -/* Data Register, Port E */ -#define PORTE _SFR_IO8(0x03) - -/* SPI Control Register */ -#define SPCR _SFR_IO8(0x0D) - -/* SPI Status Register */ -#define SPSR _SFR_IO8(0x0E) - -/* SPI I/O Data Register */ -#define SPDR _SFR_IO8(0x0F) - -/* Input Pins, Port D */ -#define PIND _SFR_IO8(0x10) - -/* Data Direction Register, Port D */ -#define DDRD _SFR_IO8(0x11) - -/* Data Register, Port D */ -#define PORTD _SFR_IO8(0x12) - -/* Input Pins, Port C */ -#define PINC _SFR_IO8(0x13) - -/* Data Direction Register, Port C */ -#define DDRC _SFR_IO8(0x14) - -/* Data Register, Port C */ -#define PORTC _SFR_IO8(0x15) - -/* Input Pins, Port B */ -#define PINB _SFR_IO8(0x16) - -/* Data Direction Register, Port B */ -#define DDRB _SFR_IO8(0x17) - -/* Data Register, Port B */ -#define PORTB _SFR_IO8(0x18) - -/* Input Pins, Port A */ -#define PINA _SFR_IO8(0x19) - -/* Data Direction Register, Port A */ -#define DDRA _SFR_IO8(0x1A) - -/* Data Register, Port A */ -#define PORTA _SFR_IO8(0x1B) - -/* 0x1C..0x1F reserved */ - -/* Watchdog Timer Control Register */ -#define WDTCR _SFR_IO8(0x21) - -/* T/C 1 Input Capture Register */ -#define ICR1 _SFR_IO16(0x24) -#define ICR1L _SFR_IO8(0x24) -#define ICR1H _SFR_IO8(0x25) - -/* Timer/Counter1 Output Compare Register B */ -#define OCR1B _SFR_IO16(0x28) -#define OCR1BL _SFR_IO8(0x28) -#define OCR1BH _SFR_IO8(0x29) - -/* Timer/Counter1 Output Compare Register A */ -#define OCR1A _SFR_IO16(0x2A) -#define OCR1AL _SFR_IO8(0x2A) -#define OCR1AH _SFR_IO8(0x2B) - -/* Timer/Counter 1 */ -#define TCNT1 _SFR_IO16(0x2C) -#define TCNT1L _SFR_IO8(0x2C) -#define TCNT1H _SFR_IO8(0x2D) - -/* Timer/Counter 1 Control and Status Register */ -#define TCCR1B _SFR_IO8(0x2E) - -/* Timer/Counter 1 Control Register */ -#define TCCR1A _SFR_IO8(0x2F) - -/* Timer/Counter 0 */ -#define TCNT0 _SFR_IO8(0x32) - -/* Timer/Counter 0 Control Register */ -#define TCCR0 _SFR_IO8(0x33) - -/* MCU general Control Register */ -#define MCUCR _SFR_IO8(0x35) - -/* Timer/Counter Interrupt Flag Register */ -#define TIFR _SFR_IO8(0x38) - -/* Timer/Counter Interrupt MaSK register */ -#define TIMSK _SFR_IO8(0x39) - -/* General Interrupt Control Register */ -#define GIFR _SFR_IO8(0x3A) - -/* General Interrupt Mask register */ -#define GIMSK _SFR_IO8(0x3B) - -/* Interrupt vectors */ - -#define SIG_INTERRUPT0 _VECTOR(1) -#define SIG_INTERRUPT1 _VECTOR(2) -#define SIG_TIMER1_CAPT1 _VECTOR(3) -#define SIG_INPUT_CAPTURE1 _VECTOR(3) -#define SIG_OUTPUT_COMPARE1A _VECTOR(4) -#define SIG_OUTPUT_COMPARE1B _VECTOR(5) -#define SIG_OVERFLOW1 _VECTOR(6) -#define SIG_OVERFLOW0 _VECTOR(7) -#define SIG_SPI _VECTOR(8) -#define SIG_UART_RECV _VECTOR(9) -#define SIG_UART_DATA _VECTOR(10) -#define SIG_UART_TRANS _VECTOR(11) -#define SIG_USB_INT _VECTOR(12) - -#define _VECTORS_SIZE 52 - -/* - The Register Bit names are represented by their bit number (0-7). -*/ - -/* Timer/Counter Interrupt MaSK register */ -#define TICIE1 3 -#define OCIE1A 6 -#define OCIE1B 5 -#define TOIE1 7 -#define TOIE0 1 - -/* Timer/Counter Interrupt Flag Register */ -#define ICF1 3 -#define OCF1A 6 -#define OCF1B 5 -#define TOV1 7 -#define TOV0 1 - -/* MCU general Control Register */ -#define SE 5 -#define SM 4 -#define ISC11 3 -#define ISC10 2 -#define ISC01 1 -#define ISC00 0 - -/* Timer/Counter 0 Control Register */ -#define CS02 2 -#define CS01 1 -#define CS00 0 - - -/* Timer/Counter 1 Control Register */ -#define COM1A1 7 -#define COM1A0 6 -#define COM1B1 5 -#define COM1B0 4 -#define PWM11 1 -#define PWM10 0 - -/* Timer/Counter 1 Control and Status Register */ -#define ICNC1 7 -#define ICES1 6 -#define CTC1 3 -#define CS12 2 -#define CS11 1 -#define CS10 0 - -/* Watchdog Timer Control Register */ -#define WDTOE 4 -#define WDE 3 -#define WDP2 2 -#define WDP1 1 -#define WDP0 0 - -/* Data Register, Port A */ -#define PA7 7 -#define PA6 6 -#define PA5 5 -#define PA4 4 -#define PA3 3 -#define PA2 2 -#define PA1 1 -#define PA0 0 - -/* Data Direction Register, Port A */ -#define DDA7 7 -#define DDA6 6 -#define DDA5 5 -#define DDA4 4 -#define DDA3 3 -#define DDA2 2 -#define DDA1 1 -#define DDA0 0 - -/* Input Pins, Port A */ -#define PINA7 7 -#define PINA6 6 -#define PINA5 5 -#define PINA4 4 -#define PINA3 3 -#define PINA2 2 -#define PINA1 1 -#define PINA0 0 - -/* Data Register, Port B */ -#define PB7 7 -#define PB6 6 -#define PB5 5 -#define PB4 4 -#define PB3 3 -#define PB2 2 -#define PB1 1 -#define PB0 0 - -/* Data Direction Register, Port B */ -#define DDB7 7 -#define DDB6 6 -#define DDB5 5 -#define DDB4 4 -#define DDB3 3 -#define DDB2 2 -#define DDB1 1 -#define DDB0 0 - -/* Input Pins, Port B */ -#define PINB7 7 -#define PINB6 6 -#define PINB5 5 -#define PINB4 4 -#define PINB3 3 -#define PINB2 2 -#define PINB1 1 -#define PINB0 0 - -/* Data Direction Register, Port C */ -#define DDC7 7 -#define DDC6 6 -#define DDC5 5 -#define DDC4 4 -#define DDC3 3 -#define DDC2 2 -#define DDC1 1 -#define DDC0 0 - -/* Input Pins, Port C */ -#define PINC7 7 -#define PINC6 6 -#define PINC5 5 -#define PINC4 4 -#define PINC3 3 -#define PINC2 2 -#define PINC1 1 -#define PINC0 0 - -/* Data Register, Port C */ -#define PC7 7 -#define PC6 6 -#define PC5 5 -#define PC4 4 -#define PC3 3 -#define PC2 2 -#define PC1 1 -#define PC0 0 - -/* Data Register, Port D */ -#define PD7 7 -#define PD6 6 -#define PD5 5 -#define PD4 4 -#define PD3 3 -#define PD2 2 -#define PD1 1 -#define PD0 0 - -/* Data Direction Register, Port D */ -#define DDD7 7 -#define DDD6 6 -#define DDD5 5 -#define DDD4 4 -#define DDD3 3 -#define DDD2 2 -#define DDD1 1 -#define DDD0 0 - -/* Input Pins, Port D */ -#define PIND7 7 -#define PIND6 6 -#define PIND5 5 -#define PIND4 4 -#define PIND3 3 -#define PIND2 2 -#define PIND1 1 -#define PIND0 0 - -/* Data Register, Port E */ -#define PE7 7 -#define PE6 6 -#define PE5 5 -#define PE4 4 -#define PE3 3 -#define PE2 2 -#define PE1 1 -#define PE0 0 - -/* Data Direction Register, Port E */ -#define DDE7 7 -#define DDE6 6 -#define DDE5 5 -#define DDE4 4 -#define DDE3 3 -#define DDE2 2 -#define DDE1 1 -#define DDE0 0 - -/* Input Pins, Port E */ -#define PINE7 7 -#define PINE6 6 -#define PINE5 5 -#define PINE4 4 -#define PINE3 3 -#define PINE2 2 -#define PINE1 1 -#define PINE0 0 - -/* SPI Status Register */ -#define SPIF 7 -#define WCOL 6 - -/* SPI Control Register */ -#define SPIE 7 -#define SPE 6 -#define DORD 5 -#define MSTR 4 -#define CPOL 3 -#define CPHA 2 -#define SPR1 1 -#define SPR0 0 - -/* UART Status Register */ -#define RXC 7 -#define TXC 6 -#define UDRE 5 -#define FE 4 -#define DOR 3 - -/* UART Control Register */ -#define RXCIE 7 -#define TXCIE 6 -#define UDRIE 5 -#define RXEN 4 -#define TXEN 3 -#define CHR9 2 -#define RXB8 1 -#define TXB8 0 - -/* Constants */ -#define RAMSTART 0x60 -#define RAMEND 0x025F /*Last On-Chip SRAM Location*/ -#define XRAMEND RAMEND -#define E2END 0x0000 - -/* FIXME: should be 0x1FFFF for max 128K (64K*16) external program memory, - but no RAMPZ causes gcrt1.S build to fail, so assume 64K for now... */ -#define FLASHEND 0x0FFFF - -#define SLEEP_MODE_IDLE 0 -#define SLEEP_MODE_PWR_DOWN _BV(SM) - -#endif /* _AVR_43USB32X_H_ */ diff --git a/arduino/hardware/tools/avr/avr/include/avr/io43u35x.h b/arduino/hardware/tools/avr/avr/include/avr/io43u35x.h deleted file mode 100644 index 231d08c..0000000 --- a/arduino/hardware/tools/avr/avr/include/avr/io43u35x.h +++ /dev/null @@ -1,432 +0,0 @@ -/* Copyright (c) 2003,2005 Keith Gudger - All rights reserved. - - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - * Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - * Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in - the documentation and/or other materials provided with the - distribution. - - * Neither the name of the copyright holders nor the names of - contributors may be used to endorse or promote products derived - from this software without specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. */ - -/* $Id: io43u35x.h 1873 2009-02-11 17:53:39Z arcanum $ */ - -/* avr/io43u35x.h - definitions for AT43USB35x */ - -#ifndef _AVR_IO43U35X_H_ -#define _AVR_IO43U35X_H_ 1 - -/* This file should only be included from , never directly. */ - -#ifndef _AVR_IO_H_ -# error "Include instead of this file." -#endif - -#ifndef _AVR_IOXXX_H_ -# define _AVR_IOXXX_H_ "io43u35x.h" -#else -# error "Attempt to include more than one file." -#endif - -/* I/O registers */ - -/* ADC Data Register */ -#ifndef __ASSEMBLER__ -#define ADC _SFR_IO16(0x02) -#endif -#define ADCW _SFR_IO16(0x02) -#define ADCL _SFR_IO8(0x02) -#define ADCH _SFR_IO8(0x03) - -/* ADC Control and status register */ -#define ADCSR _SFR_IO8(0x07) - -/* ADC Multiplexer select */ -#define ADMUX _SFR_IO8(0x08) - -/* Analog Comparator Control and Status Register */ -#define ACSR _SFR_IO8(0x08) - -/* Input Pins, Port F */ -#define PINF _SFR_IO8(0x04) - -/* Data Direction Register, Port F */ -#define DDRF _SFR_IO8(0x05) - -/* Data Register, Port F */ -#define PORTF _SFR_IO8(0x06) - -/* Input Pins, Port E */ -#define PINE _SFR_IO8(0x01) - -/* Data Direction Register, Port E */ -#define DDRE _SFR_IO8(0x02) - -/* Data Register, Port E */ -#define PORTE _SFR_IO8(0x03) - -/* SPI Control Register */ -#define SPCR _SFR_IO8(0x0D) - -/* SPI Status Register */ -#define SPSR _SFR_IO8(0x0E) - -/* SPI I/O Data Register */ -#define SPDR _SFR_IO8(0x0F) - -/* Input Pins, Port D */ -#define PIND _SFR_IO8(0x10) - -/* Data Direction Register, Port D */ -#define DDRD _SFR_IO8(0x11) - -/* Data Register, Port D */ -#define PORTD _SFR_IO8(0x12) - -/* Input Pins, Port C */ -#define PINC _SFR_IO8(0x13) - -/* Data Direction Register, Port C */ -#define DDRC _SFR_IO8(0x14) - -/* Data Register, Port C */ -#define PORTC _SFR_IO8(0x15) - -/* Input Pins, Port B */ -#define PINB _SFR_IO8(0x16) - -/* Data Direction Register, Port B */ -#define DDRB _SFR_IO8(0x17) - -/* Data Register, Port B */ -#define PORTB _SFR_IO8(0x18) - -/* Input Pins, Port A */ -#define PINA _SFR_IO8(0x19) - -/* Data Direction Register, Port A */ -#define DDRA _SFR_IO8(0x1A) - -/* Data Register, Port A */ -#define PORTA _SFR_IO8(0x1B) - -/* 0x1C..0x1F reserved */ - -/* Watchdog Timer Control Register */ -#define WDTCR _SFR_IO8(0x21) - -/* T/C 1 Input Capture Register */ -#define ICR1 _SFR_IO16(0x24) -#define ICR1L _SFR_IO8(0x24) -#define ICR1H _SFR_IO8(0x25) - -/* Timer/Counter1 Output Compare Register B */ -#define OCR1B _SFR_IO16(0x28) -#define OCR1BL _SFR_IO8(0x28) -#define OCR1BH _SFR_IO8(0x29) - -/* Timer/Counter1 Output Compare Register A */ -#define OCR1A _SFR_IO16(0x2A) -#define OCR1AL _SFR_IO8(0x2A) -#define OCR1AH _SFR_IO8(0x2B) - -/* Timer/Counter 1 */ -#define TCNT1 _SFR_IO16(0x2C) -#define TCNT1L _SFR_IO8(0x2C) -#define TCNT1H _SFR_IO8(0x2D) - -/* Timer/Counter 1 Control and Status Register */ -#define TCCR1B _SFR_IO8(0x2E) - -/* Timer/Counter 1 Control Register */ -#define TCCR1A _SFR_IO8(0x2F) - -/* Timer/Counter 0 */ -#define TCNT0 _SFR_IO8(0x32) - -/* Timer/Counter 0 Control Register */ -#define TCCR0 _SFR_IO8(0x33) - -/* MCU general Control Register */ -#define MCUCR _SFR_IO8(0x35) - -/* Timer/Counter Interrupt Flag Register */ -#define TIFR _SFR_IO8(0x38) - -/* Timer/Counter Interrupt MaSK register */ -#define TIMSK _SFR_IO8(0x39) - -/* General Interrupt Control Register */ -#define GIFR _SFR_IO8(0x3A) - -/* General Interrupt Mask register */ -#define GIMSK _SFR_IO8(0x3B) - -/* Interrupt vectors */ - -#define SIG_INTERRUPT0 _VECTOR(1) /* suspend/resume */ -#define SIG_INTERRUPT1 _VECTOR(2) -#define SIG_TIMER1_CAPT1 _VECTOR(3) -#define SIG_INPUT_CAPTURE1 _VECTOR(3) -#define SIG_OUTPUT_COMPARE1A _VECTOR(4) -#define SIG_OUTPUT_COMPARE1B _VECTOR(5) -#define SIG_OVERFLOW1 _VECTOR(6) -#define SIG_OVERFLOW0 _VECTOR(7) -#define SIG_SPI _VECTOR(8) -/* 9, 10: reserved */ -#define SIG_ADC _VECTOR(11) -#define SIG_USB_INT _VECTOR(12) - -#define _VECTORS_SIZE 52 - -/* - The Register Bit names are represented by their bit number (0-7). -*/ - -/* Timer/Counter Interrupt MaSK register */ -#define TICIE1 3 -#define OCIE1A 6 -#define OCIE1B 5 -#define TOIE1 7 -#define TOIE0 1 - -/* Timer/Counter Interrupt Flag Register */ -#define ICF1 3 -#define OCF1A 6 -#define OCF1B 5 -#define TOV1 7 -#define TOV0 1 - -/* MCU general Control Register */ -#define SE 5 -#define SM 4 -#define ISC11 3 -#define ISC10 2 -#define ISC01 1 -#define ISC00 0 - -/* Timer/Counter 0 Control Register */ -#define CS02 2 -#define CS01 1 -#define CS00 0 - - -/* Timer/Counter 1 Control Register */ -#define COM1A1 7 -#define COM1A0 6 -#define COM1B1 5 -#define COM1B0 4 -#define PWM11 1 -#define PWM10 0 - -/* Timer/Counter 1 Control and Status Register */ -#define ICNC1 7 -#define ICES1 6 -#define CTC1 3 -#define CS12 2 -#define CS11 1 -#define CS10 0 - -/* Watchdog Timer Control Register */ -#define WDTOE 4 -#define WDE 3 -#define WDP2 2 -#define WDP1 1 -#define WDP0 0 - -/* Data Register, Port A */ -#define PA7 7 -#define PA6 6 -#define PA5 5 -#define PA4 4 -#define PA3 3 -#define PA2 2 -#define PA1 1 -#define PA0 0 - -/* Data Direction Register, Port A */ -#define DDA7 7 -#define DDA6 6 -#define DDA5 5 -#define DDA4 4 -#define DDA3 3 -#define DDA2 2 -#define DDA1 1 -#define DDA0 0 - -/* Input Pins, Port A */ -#define PINA7 7 -#define PINA6 6 -#define PINA5 5 -#define PINA4 4 -#define PINA3 3 -#define PINA2 2 -#define PINA1 1 -#define PINA0 0 - -/* Data Register, Port B */ -#define PB7 7 -#define PB6 6 -#define PB5 5 -#define PB4 4 -#define PB3 3 -#define PB2 2 -#define PB1 1 -#define PB0 0 - -/* Data Direction Register, Port B */ -#define DDB7 7 -#define DDB6 6 -#define DDB5 5 -#define DDB4 4 -#define DDB3 3 -#define DDB2 2 -#define DDB1 1 -#define DDB0 0 - -/* Input Pins, Port B */ -#define PINB7 7 -#define PINB6 6 -#define PINB5 5 -#define PINB4 4 -#define PINB3 3 -#define PINB2 2 -#define PINB1 1 -#define PINB0 0 - -/* Data Direction Register, Port C */ -#define DDC7 7 -#define DDC6 6 -#define DDC5 5 -#define DDC4 4 -#define DDC3 3 -#define DDC2 2 -#define DDC1 1 -#define DDC0 0 - -/* Input Pins, Port C */ -#define PINC7 7 -#define PINC6 6 -#define PINC5 5 -#define PINC4 4 -#define PINC3 3 -#define PINC2 2 -#define PINC1 1 -#define PINC0 0 - -/* Data Register, Port C */ -#define PC7 7 -#define PC6 6 -#define PC5 5 -#define PC4 4 -#define PC3 3 -#define PC2 2 -#define PC1 1 -#define PC0 0 - -/* Data Register, Port D */ -#define PD7 7 -#define PD6 6 -#define PD5 5 -#define PD4 4 -#define PD3 3 -#define PD2 2 -#define PD1 1 -#define PD0 0 - -/* Data Direction Register, Port D */ -#define DDD7 7 -#define DDD6 6 -#define DDD5 5 -#define DDD4 4 -#define DDD3 3 -#define DDD2 2 -#define DDD1 1 -#define DDD0 0 - -/* Input Pins, Port D */ -#define PIND7 7 -#define PIND6 6 -#define PIND5 5 -#define PIND4 4 -#define PIND3 3 -#define PIND2 2 -#define PIND1 1 -#define PIND0 0 - -/* Data Register, Port F */ -#define PF3 3 -#define PF2 2 -#define PF1 1 -#define PF0 0 - -/* Data Direction Register, Port F */ -#define DDF3 3 -#define DDF2 2 -#define DDF1 1 - -/* Input Pins, Port F */ -#define PINF3 3 -#define PINF2 2 -#define PINF1 1 -#define PINF0 0 - -/* SPI Status Register */ -#define SPIF 7 -#define WCOL 6 - -/* SPI Control Register */ -#define SPIE 7 -#define SPE 6 -#define DORD 5 -#define MSTR 4 -#define CPOL 3 -#define CPHA 2 -#define SPR1 1 -#define SPR0 0 - -/* ADC Multiplexer select */ -#define MUX2 2 -#define MUX1 1 -#define MUX0 0 - -/* ADC Control and Status Register */ -#define ADEN 7 -#define ADSC 6 -#define ADFR 5 -#define ADIF 4 -#define ADIE 3 -#define ADPS2 2 -#define ADPS1 1 -#define ADPS0 0 - -/* Constants */ -#define RAMSTART 0x60 -#define RAMEND 0x045F /*Last On-Chip SRAM Location*/ -#define XRAMEND RAMEND -#define E2END 0x0000 -#define FLASHEND 0x5FFF - -#define SLEEP_MODE_IDLE 0 -#define SLEEP_MODE_PWR_DOWN _BV(SM) - -#endif /* _AVR_43USB355_H_ */ diff --git a/arduino/hardware/tools/avr/avr/include/avr/io4414.h b/arduino/hardware/tools/avr/avr/include/avr/io4414.h deleted file mode 100644 index 98e0c3b..0000000 --- a/arduino/hardware/tools/avr/avr/include/avr/io4414.h +++ /dev/null @@ -1,500 +0,0 @@ -/* Copyright (c) 2002, Marek Michalkiewicz - All rights reserved. - - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - * Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - * Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in - the documentation and/or other materials provided with the - distribution. - - * Neither the name of the copyright holders nor the names of - contributors may be used to endorse or promote products derived - from this software without specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. */ - -/* $Id: io4414.h 2225 2011-03-02 16:27:26Z arcanum $ */ - -/* avr/io4414.h - definitions for AT90S4414 */ - -#ifndef _AVR_IO4414_H_ -#define _AVR_IO4414_H_ 1 - -/* This file should only be included from , never directly. */ - -#ifndef _AVR_IO_H_ -# error "Include instead of this file." -#endif - -#ifndef _AVR_IOXXX_H_ -# define _AVR_IOXXX_H_ "io4414.h" -#else -# error "Attempt to include more than one file." -#endif - -/* I/O registers */ - -/* Analog Comparator Control and Status Register */ -#define ACSR _SFR_IO8(0x08) - -/* UART Baud Rate Register */ -#define UBRR _SFR_IO8(0x09) - -/* UART Control Register */ -#define UCR _SFR_IO8(0x0A) - -/* UART Status Register */ -#define USR _SFR_IO8(0x0B) - -/* UART I/O Data Register */ -#define UDR _SFR_IO8(0x0C) - -/* SPI Control Register */ -#define SPCR _SFR_IO8(0x0D) - -/* SPI Status Register */ -#define SPSR _SFR_IO8(0x0E) - -/* SPI I/O Data Register */ -#define SPDR _SFR_IO8(0x0F) - -/* Input Pins, Port D */ -#define PIND _SFR_IO8(0x10) - -/* Data Direction Register, Port D */ -#define DDRD _SFR_IO8(0x11) - -/* Data Register, Port D */ -#define PORTD _SFR_IO8(0x12) - -/* Input Pins, Port C */ -#define PINC _SFR_IO8(0x13) - -/* Data Direction Register, Port C */ -#define DDRC _SFR_IO8(0x14) - -/* Data Register, Port C */ -#define PORTC _SFR_IO8(0x15) - -/* Input Pins, Port B */ -#define PINB _SFR_IO8(0x16) - -/* Data Direction Register, Port B */ -#define DDRB _SFR_IO8(0x17) - -/* Data Register, Port B */ -#define PORTB _SFR_IO8(0x18) - -/* Input Pins, Port A */ -#define PINA _SFR_IO8(0x19) - -/* Data Direction Register, Port A */ -#define DDRA _SFR_IO8(0x1A) - -/* Data Register, Port A */ -#define PORTA _SFR_IO8(0x1B) - -/* EEPROM Control Register */ -#define EECR _SFR_IO8(0x1C) - -/* EEPROM Data Register */ -#define EEDR _SFR_IO8(0x1D) - -/* EEPROM Address Register */ -#define EEAR _SFR_IO8(0x1E) -#define EEARL _SFR_IO8(0x1E) - -/* Watchdog Timer Control Register */ -#define WDTCR _SFR_IO8(0x21) - -/* T/C 1 Input Capture Register */ -#define ICR1 _SFR_IO16(0x24) -#define ICR1L _SFR_IO8(0x24) -#define ICR1H _SFR_IO8(0x25) - -/* Timer/Counter1 Output Compare Register B */ -#define OCR1B _SFR_IO16(0x28) -#define OCR1BL _SFR_IO8(0x28) -#define OCR1BH _SFR_IO8(0x29) - -/* Timer/Counter1 Output Compare Register A */ -#define OCR1A _SFR_IO16(0x2A) -#define OCR1AL _SFR_IO8(0x2A) -#define OCR1AH _SFR_IO8(0x2B) - -/* Timer/Counter 1 */ -#define TCNT1 _SFR_IO16(0x2C) -#define TCNT1L _SFR_IO8(0x2C) -#define TCNT1H _SFR_IO8(0x2D) - -/* Timer/Counter 1 Control and Status Register */ -#define TCCR1B _SFR_IO8(0x2E) - -/* Timer/Counter 1 Control Register */ -#define TCCR1A _SFR_IO8(0x2F) - -/* Timer/Counter 0 */ -#define TCNT0 _SFR_IO8(0x32) - -/* Timer/Counter 0 Control Register */ -#define TCCR0 _SFR_IO8(0x33) - -/* MCU general Control Register */ -#define MCUCR _SFR_IO8(0x35) - -/* Timer/Counter Interrupt Flag register */ -#define TIFR _SFR_IO8(0x38) - -/* Timer/Counter Interrupt MaSK register */ -#define TIMSK _SFR_IO8(0x39) - -/* General Interrupt Flag Register */ -#define GIFR _SFR_IO8(0x3A) - -/* General Interrupt MaSK register */ -#define GIMSK _SFR_IO8(0x3B) - -/* 0x3C..0x3D SP */ - -/* 0x3F SREG */ - -/* Interrupt vectors */ - -/* External Interrupt Request 0 */ -#define INT0_vect_num 1 -#define INT0_vect _VECTOR(1) -#define SIG_INTERRUPT0 _VECTOR(1) - -/* External Interrupt Request 1 */ -#define INT1_vect_num 2 -#define INT1_vect _VECTOR(2) -#define SIG_INTERRUPT1 _VECTOR(2) - -/* Timer/Counter Capture Event */ -#define TIMER1_CAPT_vect_num 3 -#define TIMER1_CAPT_vect _VECTOR(3) -#define SIG_INPUT_CAPTURE1 _VECTOR(3) - -/* Timer/Counter1 Compare Match A */ -#define TIMER1_COMPA_vect_num 4 -#define TIMER1_COMPA_vect _VECTOR(4) -#define SIG_OUTPUT_COMPARE1A _VECTOR(4) - -/* Timer/Counter1 Compare MatchB */ -#define TIMER1_COMPB_vect_num 5 -#define TIMER1_COMPB_vect _VECTOR(5) -#define SIG_OUTPUT_COMPARE1B _VECTOR(5) - -/* Timer/Counter1 Overflow */ -#define TIMER1_OVF_vect_num 6 -#define TIMER1_OVF_vect _VECTOR(6) -#define SIG_OVERFLOW1 _VECTOR(6) - -/* Timer/Counter0 Overflow */ -#define TIMER0_OVF_vect_num 7 -#define TIMER0_OVF_vect _VECTOR(7) -#define SIG_OVERFLOW0 _VECTOR(7) - -/* Serial Transfer Complete */ -#define SPI_STC_vect_num 8 -#define SPI_STC_vect _VECTOR(8) -#define SIG_SPI _VECTOR(8) - -/* UART, Rx Complete */ -#define UART_RX_vect_num 9 -#define UART_RX_vect _VECTOR(9) -#define SIG_UART_RECV _VECTOR(9) - -/* UART Data Register Empty */ -#define UART_UDRE_vect_num 10 -#define UART_UDRE_vect _VECTOR(10) -#define SIG_UART_DATA _VECTOR(10) - -/* UART, Tx Complete */ -#define UART_TX_vect_num 11 -#define UART_TX_vect _VECTOR(11) -#define SIG_UART_TRANS _VECTOR(11) - -/* Analog Comparator */ -#define ANA_COMP_vect_num 12 -#define ANA_COMP_vect _VECTOR(12) -#define SIG_COMPARATOR _VECTOR(12) - -#define _VECTORS_SIZE 26 - -/* - The Register Bit names are represented by their bit number (0-7). -*/ - -/* General Interrupt MaSK register */ -#define INT1 7 -#define INT0 6 - -/* General Interrupt Flag Register */ -#define INTF1 7 -#define INTF0 6 - -/* Timer/Counter Interrupt MaSK register */ -#define TOIE1 7 -#define OCIE1A 6 -#define OCIE1B 5 -#define TICIE1 3 -#define TOIE0 1 - -/* Timer/Counter Interrupt Flag register */ -#define TOV1 7 -#define OCF1A 6 -#define OCF1B 5 -#define ICF1 3 -#define TOV0 1 - -/* MCU general Control Register */ -#define SRE 7 -#define SRW 6 -#define SE 5 -#define SM 4 -#define ISC11 3 -#define ISC10 2 -#define ISC01 1 -#define ISC00 0 - -/* Timer/Counter 0 Control Register */ -#define CS02 2 -#define CS01 1 -#define CS00 0 - -/* Timer/Counter 1 Control Register */ -#define COM1A1 7 -#define COM1A0 6 -#define COM1B1 5 -#define COM1B0 4 -#define PWM11 1 -#define PWM10 0 - -/* Timer/Counter 1 Control and Status Register */ -#define ICNC1 7 -#define ICES1 6 -#define CTC1 3 -#define CS12 2 -#define CS11 1 -#define CS10 0 - -/* Watchdog Timer Control Register */ -#define WDTOE 4 -#define WDE 3 -#define WDP2 2 -#define WDP1 1 -#define WDP0 0 - -/* Data Register, Port A */ -#define PA7 7 -#define PA6 6 -#define PA5 5 -#define PA4 4 -#define PA3 3 -#define PA2 2 -#define PA1 1 -#define PA0 0 - -/* Data Direction Register, Port A */ -#define DDA7 7 -#define DDA6 6 -#define DDA5 5 -#define DDA4 4 -#define DDA3 3 -#define DDA2 2 -#define DDA1 1 -#define DDA0 0 - -/* Input Pins, Port A */ -#define PINA7 7 -#define PINA6 6 -#define PINA5 5 -#define PINA4 4 -#define PINA3 3 -#define PINA2 2 -#define PINA1 1 -#define PINA0 0 - -/* Data Register, Port B */ -#define PB7 7 -#define PB6 6 -#define PB5 5 -#define PB4 4 -#define PB3 3 -#define PB2 2 -#define PB1 1 -#define PB0 0 - -/* Data Direction Register, Port B */ -#define DDB7 7 -#define DDB6 6 -#define DDB5 5 -#define DDB4 4 -#define DDB3 3 -#define DDB2 2 -#define DDB1 1 -#define DDB0 0 - -/* Input Pins, Port B */ -#define PINB7 7 -#define PINB6 6 -#define PINB5 5 -#define PINB4 4 -#define PINB3 3 -#define PINB2 2 -#define PINB1 1 -#define PINB0 0 - -/* Data Register, Port C */ -#define PC7 7 -#define PC6 6 -#define PC5 5 -#define PC4 4 -#define PC3 3 -#define PC2 2 -#define PC1 1 -#define PC0 0 - -/* Data Direction Register, Port C */ -#define DDC7 7 -#define DDC6 6 -#define DDC5 5 -#define DDC4 4 -#define DDC3 3 -#define DDC2 2 -#define DDC1 1 -#define DDC0 0 - -/* Input Pins, Port C */ -#define PINC7 7 -#define PINC6 6 -#define PINC5 5 -#define PINC4 4 -#define PINC3 3 -#define PINC2 2 -#define PINC1 1 -#define PINC0 0 - -/* Data Register, Port D */ -#define PD7 7 -#define PD6 6 -#define PD5 5 -#define PD4 4 -#define PD3 3 -#define PD2 2 -#define PD1 1 -#define PD0 0 - -/* Data Direction Register, Port D */ -#define DDD7 7 -#define DDD6 6 -#define DDD5 5 -#define DDD4 4 -#define DDD3 3 -#define DDD2 2 -#define DDD1 1 -#define DDD0 0 - -/* Input Pins, Port D */ -#define PIND7 7 -#define PIND6 6 -#define PIND5 5 -#define PIND4 4 -#define PIND3 3 -#define PIND2 2 -#define PIND1 1 -#define PIND0 0 - -/* SPI Status Register */ -#define SPIF 7 -#define WCOL 6 - -/* SPI Control Register */ -#define SPIE 7 -#define SPE 6 -#define DORD 5 -#define MSTR 4 -#define CPOL 3 -#define CPHA 2 -#define SPR1 1 -#define SPR0 0 - -/* UART Status Register */ -#define RXC 7 -#define TXC 6 -#define UDRE 5 -#define FE 4 -#define DOR 3 - -/* UART Control Register */ -#define RXCIE 7 -#define TXCIE 6 -#define UDRIE 5 -#define RXEN 4 -#define TXEN 3 -#define CHR9 2 -#define RXB8 1 -#define TXB8 0 - -/* Analog Comparator Control and Status Register */ -#define ACD 7 -#define ACO 5 -#define ACI 4 -#define ACIE 3 -#define ACIC 2 -#define ACIS1 1 -#define ACIS0 0 - -/* EEPROM Control Register */ -#define EERIE 3 -#define EEMWE 2 -#define EEWE 1 -#define EERE 0 - -/* Constants */ -#define RAMSTART 0x60 -#define RAMEND 0x15F /* Last On-Chip SRAM Location */ -#define XRAMEND 0xFFFF -#define E2END 0xFF -#define E2PAGESIZE 0 -#define FLASHEND 0xFFF - - -/* Fuses */ -#define FUSE_MEMORY_SIZE 1 - -/* Low Fuse Byte */ -#define FUSE_SPIEN (unsigned char)~_BV(1) /* Serial Program Downloading Enabled */ -#define FUSE_FSTRT (unsigned char)~_BV(2) /* Short Start-up time selected */ -#define LFUSE_DEFAULT (0xFF) - - -/* Lock Bits */ -#define __LOCK_BITS_EXIST - - -/* Signature */ -#define SIGNATURE_0 0x1E -#define SIGNATURE_1 0x92 -#define SIGNATURE_2 0x01 - -#define SLEEP_MODE_IDLE 0 -#define SLEEP_MODE_PWR_DOWN _BV(SM) - -#endif /* _AVR_IO4414_H_ */ diff --git a/arduino/hardware/tools/avr/avr/include/avr/io4433.h b/arduino/hardware/tools/avr/avr/include/avr/io4433.h deleted file mode 100644 index 805cd46..0000000 --- a/arduino/hardware/tools/avr/avr/include/avr/io4433.h +++ /dev/null @@ -1,489 +0,0 @@ -/* Copyright (c) 2002, Marek Michalkiewicz - All rights reserved. - - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - * Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - * Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in - the documentation and/or other materials provided with the - distribution. - - * Neither the name of the copyright holders nor the names of - contributors may be used to endorse or promote products derived - from this software without specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. */ - -/* $Id: io4433.h 2225 2011-03-02 16:27:26Z arcanum $ */ - -/* avr/io4433.h - definitions for AT90S4433 */ - -#ifndef _AVR_IO4433_H_ -#define _AVR_IO4433_H_ 1 - -/* This file should only be included from , never directly. */ - -#ifndef _AVR_IO_H_ -# error "Include instead of this file." -#endif - -#ifndef _AVR_IOXXX_H_ -# define _AVR_IOXXX_H_ "io4433.h" -#else -# error "Attempt to include more than one file." -#endif - -/* I/O registers */ - -/* UART Baud Rate Register high */ -#define UBRRH _SFR_IO8(0x03) - -/* ADC Data register */ -#ifndef __ASSEMBLER__ -#define ADC _SFR_IO16(0x04) -#endif -#define ADCW _SFR_IO16(0x04) -#define ADCL _SFR_IO8(0x04) -#define ADCH _SFR_IO8(0x05) - -/* ADC Control and Status Register */ -#define ADCSR _SFR_IO8(0x06) - -/* ADC MUX */ -#define ADMUX _SFR_IO8(0x07) - -/* Analog Comparator Control and Status Register */ -#define ACSR _SFR_IO8(0x08) - -/* UART Baud Rate Register */ -#define UBRR _SFR_IO8(0x09) - -/* UART Control/Status Registers */ -#define UCSRB _SFR_IO8(0x0A) -#define UCSRA _SFR_IO8(0x0B) - -/* UART I/O Data Register */ -#define UDR _SFR_IO8(0x0C) - -/* SPI Control Register */ -#define SPCR _SFR_IO8(0x0D) - -/* SPI Status Register */ -#define SPSR _SFR_IO8(0x0E) - -/* SPI I/O Data Register */ -#define SPDR _SFR_IO8(0x0F) - -/* Input Pins, Port D */ -#define PIND _SFR_IO8(0x10) - -/* Data Direction Register, Port D */ -#define DDRD _SFR_IO8(0x11) - -/* Data Register, Port D */ -#define PORTD _SFR_IO8(0x12) - -/* Input Pins, Port C */ -#define PINC _SFR_IO8(0x13) - -/* Data Direction Register, Port C */ -#define DDRC _SFR_IO8(0x14) - -/* Data Register, Port C */ -#define PORTC _SFR_IO8(0x15) - -/* Input Pins, Port B */ -#define PINB _SFR_IO8(0x16) - -/* Data Direction Register, Port B */ -#define DDRB _SFR_IO8(0x17) - -/* Data Register, Port B */ -#define PORTB _SFR_IO8(0x18) - -/* EEPROM Control Register */ -#define EECR _SFR_IO8(0x1C) - -/* EEPROM Data Register */ -#define EEDR _SFR_IO8(0x1D) - -/* EEPROM Address Register */ -#define EEAR _SFR_IO8(0x1E) -#define EEARL _SFR_IO8(0x1E) - -/* Watchdog Timer Control Register */ -#define WDTCR _SFR_IO8(0x21) - -/* T/C 1 Input Capture Register */ -#define ICR1 _SFR_IO16(0x26) -#define ICR1L _SFR_IO8(0x26) -#define ICR1H _SFR_IO8(0x27) - -/* Timer/Counter1 Output Compare Register A */ -#define OCR1 _SFR_IO16(0x2A) -#define OCR1L _SFR_IO8(0x2A) -#define OCR1H _SFR_IO8(0x2B) - -/* Timer/Counter 1 */ -#define TCNT1 _SFR_IO16(0x2C) -#define TCNT1L _SFR_IO8(0x2C) -#define TCNT1H _SFR_IO8(0x2D) - -/* Timer/Counter 1 Control and Status Register */ -#define TCCR1B _SFR_IO8(0x2E) - -/* Timer/Counter 1 Control Register */ -#define TCCR1A _SFR_IO8(0x2F) - -/* Timer/Counter 0 */ -#define TCNT0 _SFR_IO8(0x32) - -/* Timer/Counter 0 Control Register */ -#define TCCR0 _SFR_IO8(0x33) - -/* MCU general Status Register */ -#define MCUSR _SFR_IO8(0x34) - -/* MCU general Control Register */ -#define MCUCR _SFR_IO8(0x35) - -/* Timer/Counter Interrupt Flag register */ -#define TIFR _SFR_IO8(0x38) - -/* Timer/Counter Interrupt MaSK register */ -#define TIMSK _SFR_IO8(0x39) - -/* General Interrupt Flag Register */ -#define GIFR _SFR_IO8(0x3A) - -/* General Interrupt MaSK register */ -#define GIMSK _SFR_IO8(0x3B) - -/* 0x3D..0x3E SP */ - -/* 0x3F SREG */ - -/* Interrupt vectors */ - -/* External Interrupt 0 */ -#define INT0_vect_num 1 -#define INT0_vect _VECTOR(1) -#define SIG_INTERRUPT0 _VECTOR(1) - -/* External Interrupt 1 */ -#define INT1_vect_num 2 -#define INT1_vect _VECTOR(2) -#define SIG_INTERRUPT1 _VECTOR(2) - -/* Timer/Counter Capture Event */ -#define TIMER1_CAPT_vect_num 3 -#define TIMER1_CAPT_vect _VECTOR(3) -#define SIG_INPUT_CAPTURE1 _VECTOR(3) - -/* Timer/Counter1 Compare Match */ -#define TIMER1_COMP_vect_num 4 -#define TIMER1_COMP_vect _VECTOR(4) -#define SIG_OUTPUT_COMPARE1A _VECTOR(4) - -/* Timer/Counter1 Overflow */ -#define TIMER1_OVF_vect_num 5 -#define TIMER1_OVF_vect _VECTOR(5) -#define SIG_OVERFLOW1 _VECTOR(5) - -/* Timer/Counter0 Overflow */ -#define TIMER0_OVF_vect_num 6 -#define TIMER0_OVF_vect _VECTOR(6) -#define SIG_OVERFLOW0 _VECTOR(6) - -/* Serial Transfer Complete */ -#define SPI_STC_vect_num 7 -#define SPI_STC_vect _VECTOR(7) -#define SIG_SPI _VECTOR(7) - -/* UART, Rx Complete */ -#define UART_RX_vect_num 8 -#define UART_RX_vect _VECTOR(8) -#define SIG_UART_RECV _VECTOR(8) - -/* UART Data Register Empty */ -#define UART_UDRE_vect_num 9 -#define UART_UDRE_vect _VECTOR(9) -#define SIG_UART_DATA _VECTOR(9) - -/* UART, Tx Complete */ -#define UART_TX_vect_num 10 -#define UART_TX_vect _VECTOR(10) -#define SIG_UART_TRANS _VECTOR(10) - -/* ADC Conversion Complete */ -#define ADC_vect_num 11 -#define ADC_vect _VECTOR(11) -#define SIG_ADC _VECTOR(11) - -/* EEPROM Ready */ -#define EE_RDY_vect_num 12 -#define EE_RDY_vect _VECTOR(12) -#define SIG_EEPROM_READY _VECTOR(12) - -/* Analog Comparator */ -#define ANA_COMP_vect_num 13 -#define ANA_COMP_vect _VECTOR(13) -#define SIG_COMPARATOR _VECTOR(13) - -#define _VECTORS_SIZE 28 - -/* - The Register Bit names are represented by their bit number (0-7). -*/ - -/* MCU general Status Register */ -#define WDRF 3 -#define BORF 2 -#define EXTRF 1 -#define PORF 0 - -/* General Interrupt MaSK register */ -#define INT1 7 -#define INT0 6 - -/* General Interrupt Flag Register */ -#define INTF1 7 -#define INTF0 6 - -/* Timer/Counter Interrupt MaSK register */ -#define TOIE1 7 -#define OCIE1 6 -#define TICIE1 3 -#define TOIE0 1 - -/* Timer/Counter Interrupt Flag register */ -#define TOV1 7 -#define OCF1 6 -#define ICF1 3 -#define TOV0 1 - -/* MCU general Control Register */ -#define SE 5 -#define SM 4 -#define ISC11 3 -#define ISC10 2 -#define ISC01 1 -#define ISC00 0 - -/* Timer/Counter 0 Control Register */ -#define CS02 2 -#define CS01 1 -#define CS00 0 - -/* Timer/Counter 1 Control Register */ -#define COM11 7 -#define COM10 6 -#define PWM11 1 -#define PWM10 0 - -/* Timer/Counter 1 Control and Status Register */ -#define ICNC1 7 -#define ICES1 6 -#define CTC1 3 -#define CS12 2 -#define CS11 1 -#define CS10 0 - -/* Watchdog Timer Control Register */ -#define WDTOE 4 -#define WDE 3 -#define WDP2 2 -#define WDP1 1 -#define WDP0 0 - -/* SPI Control Register */ -#define SPIE 7 -#define SPE 6 -#define DORD 5 -#define MSTR 4 -#define CPOL 3 -#define CPHA 2 -#define SPR1 1 -#define SPR0 0 - -/* SPI Status Register */ -#define SPIF 7 -#define WCOL 6 - -/* UART Status Register */ -#define RXC 7 -#define TXC 6 -#define UDRE 5 -#define FE 4 -#define DOR 3 -#define MPCM 0 - -/* UART Control Register */ -#define RXCIE 7 -#define TXCIE 6 -#define UDRIE 5 -#define RXEN 4 -#define TXEN 3 -#define CHR9 2 -#define RXB8 1 -#define TXB8 0 - -/* Analog Comparator Control and Status Register */ -#define ACD 7 -#define AINBG 6 -#define ACO 5 -#define ACI 4 -#define ACIE 3 -#define ACIC 2 -#define ACIS1 1 -#define ACIS0 0 - -/* ADC MUX */ -#define ACDBG 6 -#define MUX2 2 -#define MUX1 1 -#define MUX0 0 - -/* ADC Control and Status Register */ -#define ADEN 7 -#define ADSC 6 -#define ADFR 5 -#define ADIF 4 -#define ADIE 3 -#define ADPS2 2 -#define ADPS1 1 -#define ADPS0 0 - -/* Data Register, Port B */ -#define PB5 5 -#define PB4 4 -#define PB3 3 -#define PB2 2 -#define PB1 1 -#define PB0 0 - -/* Data Direction Register, Port B */ -#define DDB5 5 -#define DDB4 4 -#define DDB3 3 -#define DDB2 2 -#define DDB1 1 -#define DDB0 0 - -/* Input Pins, Port B */ -#define PINB5 5 -#define PINB4 4 -#define PINB3 3 -#define PINB2 2 -#define PINB1 1 -#define PINB0 0 - -/* Data Register, Port C */ -#define PC5 5 -#define PC4 4 -#define PC3 3 -#define PC2 2 -#define PC1 1 -#define PC0 0 - -/* Data Direction Register, Port C */ -#define DDC5 5 -#define DDC4 4 -#define DDC3 3 -#define DDC2 2 -#define DDC1 1 -#define DDC0 0 - -/* Input Pins, Port C */ -#define PINC5 5 -#define PINC4 4 -#define PINC3 3 -#define PINC2 2 -#define PINC1 1 -#define PINC0 0 - -/* Data Register, Port D */ -#define PD7 7 -#define PD6 6 -#define PD5 5 -#define PD4 4 -#define PD3 3 -#define PD2 2 -#define PD1 1 -#define PD0 0 - -/* Data Direction Register, Port D */ -#define DDD7 7 -#define DDD6 6 -#define DDD5 5 -#define DDD4 4 -#define DDD3 3 -#define DDD2 2 -#define DDD1 1 -#define DDD0 0 - -/* Input Pins, Port D */ -#define PIND7 7 -#define PIND6 6 -#define PIND5 5 -#define PIND4 4 -#define PIND3 3 -#define PIND2 2 -#define PIND1 1 -#define PIND0 0 - -/* EEPROM Control Register */ -#define EERIE 3 -#define EEMWE 2 -#define EEWE 1 -#define EERE 0 - -/* Constants */ -#define RAMSTART 0x60 -#define RAMEND 0xDF /*Last On-Chip SRAM location*/ -#define XRAMEND RAMEND -#define E2END 0xFF -#define E2PAGESIZE 0 -#define FLASHEND 0xFFF - - -/* Fuses */ -#define FUSE_MEMORY_SIZE 1 - -/* Low Fuse Byte */ -#define FUSE_CKSEL0 (unsigned char)~_BV(0) -#define FUSE_CKSEL1 (unsigned char)~_BV(1) -#define FUSE_CKSEL2 (unsigned char)~_BV(2) -#define FUSE_BODEN (unsigned char)~_BV(3) -#define FUSE_BODLEVEL (unsigned char)~_BV(4) -#define FUSE_SPIEN (unsigned char)~_BV(5) -#define LFUSE_DEFAULT (0xFF) - - -/* Lock Bits */ -#define __LOCK_BITS_EXIST - - -/* Signature */ -#define SIGNATURE_0 0x1E -#define SIGNATURE_1 0x92 -#define SIGNATURE_2 0x03 - -#define SLEEP_MODE_IDLE 0 -#define SLEEP_MODE_PWR_DOWN _BV(SM) - -#endif /* _AVR_IO4433_H_ */ diff --git a/arduino/hardware/tools/avr/avr/include/avr/io4434.h b/arduino/hardware/tools/avr/avr/include/avr/io4434.h deleted file mode 100644 index db1005d..0000000 --- a/arduino/hardware/tools/avr/avr/include/avr/io4434.h +++ /dev/null @@ -1,588 +0,0 @@ -/* Copyright (c) 2002, Marek Michalkiewicz - All rights reserved. - - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - * Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - * Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in - the documentation and/or other materials provided with the - distribution. - - * Neither the name of the copyright holders nor the names of - contributors may be used to endorse or promote products derived - from this software without specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. */ - -/* $Id: io4434.h 2225 2011-03-02 16:27:26Z arcanum $ */ - -/* avr/io4434.h - definitions for AT90S4434 */ - -#ifndef _AVR_IO4434_H_ -#define _AVR_IO4434_H_ 1 - -/* This file should only be included from , never directly. */ - -#ifndef _AVR_IO_H_ -# error "Include instead of this file." -#endif - -#ifndef _AVR_IOXXX_H_ -# define _AVR_IOXXX_H_ "io4434.h" -#else -# error "Attempt to include more than one file." -#endif - -/* I/O registers */ - -/* ADC Data register */ -#ifndef __ASSEMBLER__ -#define ADC _SFR_IO16(0x04) -#endif -#define ADCW _SFR_IO16(0x04) -#define ADCL _SFR_IO8(0x04) -#define ADCH _SFR_IO8(0x05) - -/* ADC Control and Status Register */ -#define ADCSR _SFR_IO8(0x06) - -/* ADC MUX */ -#define ADMUX _SFR_IO8(0x07) - -/* Analog Comparator Control and Status Register */ -#define ACSR _SFR_IO8(0x08) - -/* UART Baud Rate Register */ -#define UBRR _SFR_IO8(0x09) - -/* UART Control Register */ -#define UCR _SFR_IO8(0x0A) - -/* UART Status Register */ -#define USR _SFR_IO8(0x0B) - -/* UART I/O Data Register */ -#define UDR _SFR_IO8(0x0C) - -/* SPI Control Register */ -#define SPCR _SFR_IO8(0x0D) - -/* SPI Status Register */ -#define SPSR _SFR_IO8(0x0E) - -/* SPI I/O Data Register */ -#define SPDR _SFR_IO8(0x0F) - -/* Input Pins, Port D */ -#define PIND _SFR_IO8(0x10) - -/* Data Direction Register, Port D */ -#define DDRD _SFR_IO8(0x11) - -/* Data Register, Port D */ -#define PORTD _SFR_IO8(0x12) - -/* Input Pins, Port C */ -#define PINC _SFR_IO8(0x13) - -/* Data Direction Register, Port C */ -#define DDRC _SFR_IO8(0x14) - -/* Data Register, Port C */ -#define PORTC _SFR_IO8(0x15) - -/* Input Pins, Port B */ -#define PINB _SFR_IO8(0x16) - -/* Data Direction Register, Port B */ -#define DDRB _SFR_IO8(0x17) - -/* Data Register, Port B */ -#define PORTB _SFR_IO8(0x18) - -/* Input Pins, Port A */ -#define PINA _SFR_IO8(0x19) - -/* Data Direction Register, Port A */ -#define DDRA _SFR_IO8(0x1A) - -/* Data Register, Port A */ -#define PORTA _SFR_IO8(0x1B) - -/* EEPROM Control Register */ -#define EECR _SFR_IO8(0x1C) - -/* EEPROM Data Register */ -#define EEDR _SFR_IO8(0x1D) - -/* EEPROM Address Register */ -#define EEAR _SFR_IO8(0x1E) -#define EEARL _SFR_IO8(0x1E) - -/* Watchdog Timer Control Register */ -#define WDTCR _SFR_IO8(0x21) - -/* Asynchronous mode Status Register */ -#define ASSR _SFR_IO8(0x22) - -/* Timer/Counter2 Output Compare Register */ -#define OCR2 _SFR_IO8(0x23) - -/* Timer/Counter 2 */ -#define TCNT2 _SFR_IO8(0x24) - -/* Timer/Counter 2 Control Register */ -#define TCCR2 _SFR_IO8(0x25) - -/* T/C 1 Input Capture Register */ -#define ICR1 _SFR_IO16(0x26) -#define ICR1L _SFR_IO8(0x26) -#define ICR1H _SFR_IO8(0x27) - -/* Timer/Counter1 Output Compare Register B */ -#define OCR1B _SFR_IO16(0x28) -#define OCR1BL _SFR_IO8(0x28) -#define OCR1BH _SFR_IO8(0x29) - -/* Timer/Counter1 Output Compare Register A */ -#define OCR1A _SFR_IO16(0x2A) -#define OCR1AL _SFR_IO8(0x2A) -#define OCR1AH _SFR_IO8(0x2B) - -/* Timer/Counter 1 */ -#define TCNT1 _SFR_IO16(0x2C) -#define TCNT1L _SFR_IO8(0x2C) -#define TCNT1H _SFR_IO8(0x2D) - -/* Timer/Counter 1 Control and Status Register */ -#define TCCR1B _SFR_IO8(0x2E) - -/* Timer/Counter 1 Control Register */ -#define TCCR1A _SFR_IO8(0x2F) - -/* Timer/Counter 0 */ -#define TCNT0 _SFR_IO8(0x32) - -/* Timer/Counter 0 Control Register */ -#define TCCR0 _SFR_IO8(0x33) - -/* MCU general Status Register */ -#define MCUSR _SFR_IO8(0x34) - -/* MCU general Control Register */ -#define MCUCR _SFR_IO8(0x35) - -/* Timer/Counter Interrupt Flag register */ -#define TIFR _SFR_IO8(0x38) - -/* Timer/Counter Interrupt MaSK register */ -#define TIMSK _SFR_IO8(0x39) - -/* General Interrupt Flag Register */ -#define GIFR _SFR_IO8(0x3A) - -/* General Interrupt MaSK register */ -#define GIMSK _SFR_IO8(0x3B) - -/* 0x3D..0x3E SP */ - -/* 0x3F SREG */ - -/* Interrupt vectors */ - -/* External Interrupt 0 */ -#define INT0_vect_num 1 -#define INT0_vect _VECTOR(1) -#define SIG_INTERRUPT0 _VECTOR(1) - -/* External Interrupt 1 */ -#define INT1_vect_num 2 -#define INT1_vect _VECTOR(2) -#define SIG_INTERRUPT1 _VECTOR(2) - -/* Timer/Counter2 Compare Match */ -#define TIMER2_COMP_vect_num 3 -#define TIMER2_COMP_vect _VECTOR(3) -#define SIG_OUTPUT_COMPARE2 _VECTOR(3) - -/* Timer/Counter2 Overflow */ -#define TIMER2_OVF_vect_num 4 -#define TIMER2_OVF_vect _VECTOR(4) -#define SIG_OVERFLOW2 _VECTOR(4) - -/* Timer/Counter1 Capture Event */ -#define TIMER1_CAPT_vect_num 5 -#define TIMER1_CAPT_vect _VECTOR(5) -#define SIG_INPUT_CAPTURE1 _VECTOR(5) - -/* Timer/Counter1 Compare Match A */ -#define TIMER1_COMPA_vect_num 6 -#define TIMER1_COMPA_vect _VECTOR(6) -#define SIG_OUTPUT_COMPARE1A _VECTOR(6) - -/* Timer/Counter1 Compare Match B */ -#define TIMER1_COMPB_vect_num 7 -#define TIMER1_COMPB_vect _VECTOR(7) -#define SIG_OUTPUT_COMPARE1B _VECTOR(7) - -/* Timer/Counter1 Overflow */ -#define TIMER1_OVF_vect_num 8 -#define TIMER1_OVF_vect _VECTOR(8) -#define SIG_OVERFLOW1 _VECTOR(8) - -/* Timer/Counter0 Overflow */ -#define TIMER0_OVF_vect_num 9 -#define TIMER0_OVF_vect _VECTOR(9) -#define SIG_OVERFLOW0 _VECTOR(9) - -/* SPI Serial Transfer Complete */ -#define SPI_STC_vect_num 10 -#define SPI_STC_vect _VECTOR(10) -#define SIG_SPI _VECTOR(10) - -/* UART, RX Complete */ -#define UART_RX_vect_num 11 -#define UART_RX_vect _VECTOR(11) -#define SIG_UART_RECV _VECTOR(11) - -/* UART Data Register Empty */ -#define UART_UDRE_vect_num 12 -#define UART_UDRE_vect _VECTOR(12) -#define SIG_UART_DATA _VECTOR(12) - -/* UART, TX Complete */ -#define UART_TX_vect_num 13 -#define UART_TX_vect _VECTOR(13) -#define SIG_UART_TRANS _VECTOR(13) - -/* ADC Conversion Complete */ -#define ADC_vect_num 14 -#define ADC_vect _VECTOR(14) -#define SIG_ADC _VECTOR(14) - -/* EEPROM Ready */ -#define EE_RDY_vect_num 15 -#define EE_RDY_vect _VECTOR(15) -#define SIG_EEPROM_READY _VECTOR(15) - -/* Analog Comparator */ -#define ANA_COMP_vect_num 16 -#define ANA_COMP_vect _VECTOR(16) -#define SIG_COMPARATOR _VECTOR(16) - -#define _VECTORS_SIZE 34 - -/* - The Register Bit names are represented by their bit number (0-7). -*/ - -/* MCU general Status Register */ -#define EXTRF 1 -#define PORF 0 - -/* General Interrupt MaSK register */ -#define INT1 7 -#define INT0 6 - -/* General Interrupt Flag Register */ -#define INTF1 7 -#define INTF0 6 - -/* Timer/Counter Interrupt MaSK register */ -#define OCIE2 7 -#define TOIE2 6 -#define TICIE1 5 -#define OCIE1A 4 -#define OCIE1B 3 -#define TOIE1 2 -#define TOIE0 0 - -/* Timer/Counter Interrupt Flag register */ -#define OCF2 7 -#define TOV2 6 -#define ICF1 5 -#define OCF1A 4 -#define OCF1B 3 -#define TOV1 2 -#define TOV0 0 - -/* MCU general Control Register */ -#define SE 6 -#define SM1 5 -#define SM0 4 -#define ISC11 3 -#define ISC10 2 -#define ISC01 1 -#define ISC00 0 - -/* Timer/Counter 0 Control Register */ -#define CS02 2 -#define CS01 1 -#define CS00 0 - -/* Timer/Counter 1 Control Register */ -#define COM1A1 7 -#define COM1A0 6 -#define COM1B1 5 -#define COM1B0 4 -#define PWM11 1 -#define PWM10 0 - -/* Timer/Counter 1 Control and Status Register */ -#define ICNC1 7 -#define ICES1 6 -#define CTC1 3 -#define CS12 2 -#define CS11 1 -#define CS10 0 - -/* Timer/Counter 2 Control Register */ -#define PWM2 6 -#define COM21 5 -#define COM20 4 -#define CTC2 3 -#define CS22 2 -#define CS21 1 -#define CS20 0 - -/* Asynchronous mode Status Register */ -#define AS2 3 -#define TCN2UB 2 -#define OCR2UB 1 -#define TCR2UB 0 - -/* Watchdog Timer Control Register */ -#define WDTOE 4 -#define WDE 3 -#define WDP2 2 -#define WDP1 1 -#define WDP0 0 - -/* Data Register, Port A */ -#define PA7 7 -#define PA6 6 -#define PA5 5 -#define PA4 4 -#define PA3 3 -#define PA2 2 -#define PA1 1 -#define PA0 0 - -/* Data Direction Register, Port A */ -#define DDA7 7 -#define DDA6 6 -#define DDA5 5 -#define DDA4 4 -#define DDA3 3 -#define DDA2 2 -#define DDA1 1 -#define DDA0 0 - -/* Input Pins, Port A */ -#define PINA7 7 -#define PINA6 6 -#define PINA5 5 -#define PINA4 4 -#define PINA3 3 -#define PINA2 2 -#define PINA1 1 -#define PINA0 0 - -/* Data Register, Port B */ -#define PB7 7 -#define PB6 6 -#define PB5 5 -#define PB4 4 -#define PB3 3 -#define PB2 2 -#define PB1 1 -#define PB0 0 - -/* Data Direction Register, Port B */ -#define DDB7 7 -#define DDB6 6 -#define DDB5 5 -#define DDB4 4 -#define DDB3 3 -#define DDB2 2 -#define DDB1 1 -#define DDB0 0 - -/* Input Pins, Port B */ -#define PINB7 7 -#define PINB6 6 -#define PINB5 5 -#define PINB4 4 -#define PINB3 3 -#define PINB2 2 -#define PINB1 1 -#define PINB0 0 - -/* Data Register, Port C */ -#define PC7 7 -#define PC6 6 -#define PC5 5 -#define PC4 4 -#define PC3 3 -#define PC2 2 -#define PC1 1 -#define PC0 0 - -/* Data Direction Register, Port C */ -#define DDC7 7 -#define DDC6 6 -#define DDC5 5 -#define DDC4 4 -#define DDC3 3 -#define DDC2 2 -#define DDC1 1 -#define DDC0 0 - -/* Input Pins, Port C */ -#define PINC7 7 -#define PINC6 6 -#define PINC5 5 -#define PINC4 4 -#define PINC3 3 -#define PINC2 2 -#define PINC1 1 -#define PINC0 0 - -/* Data Register, Port D */ -#define PD7 7 -#define PD6 6 -#define PD5 5 -#define PD4 4 -#define PD3 3 -#define PD2 2 -#define PD1 1 -#define PD0 0 - -/* Data Direction Register, Port D */ -#define DDD7 7 -#define DDD6 6 -#define DDD5 5 -#define DDD4 4 -#define DDD3 3 -#define DDD2 2 -#define DDD1 1 -#define DDD0 0 - -/* Input Pins, Port D */ -#define PIND7 7 -#define PIND6 6 -#define PIND5 5 -#define PIND4 4 -#define PIND3 3 -#define PIND2 2 -#define PIND1 1 -#define PIND0 0 - -/* SPI Control Register */ -#define SPIE 7 -#define SPE 6 -#define DORD 5 -#define MSTR 4 -#define CPOL 3 -#define CPHA 2 -#define SPR1 1 -#define SPR0 0 - -/* SPI Status Register */ -#define SPIF 7 -#define WCOL 6 - -/* UART Status Register */ -#define RXC 7 -#define TXC 6 -#define UDRE 5 -#define FE 4 -#define DOR 3 - -/* UART Control Register */ -#define RXCIE 7 -#define TXCIE 6 -#define UDRIE 5 -#define RXEN 4 -#define TXEN 3 -#define CHR9 2 -#define RXB8 1 -#define TXB8 0 - -/* Analog Comparator Control and Status Register */ -#define ACD 7 -#define ACO 5 -#define ACI 4 -#define ACIE 3 -#define ACIC 2 -#define ACIS1 1 -#define ACIS0 0 - -/* ADC MUX */ -#define MUX2 2 -#define MUX1 1 -#define MUX0 0 - -/* ADC Control and Status Register */ -#define ADEN 7 -#define ADSC 6 -#define ADFR 5 -#define ADIF 4 -#define ADIE 3 -#define ADPS2 2 -#define ADPS1 1 -#define ADPS0 0 - -/* EEPROM Control Register */ -#define EERIE 3 -#define EEMWE 2 -#define EEWE 1 -#define EERE 0 - -/* Constants */ -#define RAMSTART 0x60 -#define RAMEND 0x15F /*Last On-Chip SRAM location*/ -#define XRAMEND RAMEND -#define E2END 0xFF -#define E2PAGESIZE 0 -#define FLASHEND 0xFFF - - -/* Fuses */ -#define FUSE_MEMORY_SIZE 1 - -/* Low Fuse Byte */ -#define FUSE_SPIEN ~_BV(1) /* Serial Program Downloading Enabled */ -#define FUSE_FSTRT ~_BV(2) /* Short Start-up time selected */ -#define LFUSE_DEFAULT (0xFF) - - -/* Lock Bits */ -#define __LOCK_BITS_EXIST - - -/* Signature */ -#define SIGNATURE_0 0x1E -#define SIGNATURE_1 0x93 -#define SIGNATURE_2 0x03 - -#define SLEEP_MODE_IDLE 0 -#define SLEEP_MODE_ADC _BV(SM0) -#define SLEEP_MODE_PWR_DOWN _BV(SM1) -#define SLEEP_MODE_PWR_SAVE (_BV(SM0) | _BV(SM1)) - -#endif /* _AVR_IO4434_H_ */ diff --git a/arduino/hardware/tools/avr/avr/include/avr/io76c711.h b/arduino/hardware/tools/avr/avr/include/avr/io76c711.h deleted file mode 100644 index 1c2edf2..0000000 --- a/arduino/hardware/tools/avr/avr/include/avr/io76c711.h +++ /dev/null @@ -1,499 +0,0 @@ -/* Copyright (c) 2002, Marek Michalkiewicz - All rights reserved. - - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - * Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - * Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in - the documentation and/or other materials provided with the - distribution. - - * Neither the name of the copyright holders nor the names of - contributors may be used to endorse or promote products derived - from this software without specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. */ - -/* $Id: io76c711.h 1873 2009-02-11 17:53:39Z arcanum $ */ - -/* avr/io76c711.h - definitions for AT76C711 */ - -#ifndef _AVR_IO76C711_H_ -#define _AVR_IO76C711_H_ 1 - -/* This file should only be included from , never directly. */ - -#ifndef _AVR_IO_H_ -# error "Include instead of this file." -#endif - -#ifndef _AVR_IOXXX_H_ -# define _AVR_IOXXX_H_ "io76c711.h" -#else -# error "Attempt to include more than one file." -#endif - -/* I/O registers */ - -/* 0x00-0x0C reserved */ - -/* SPI */ -#define SPCR _SFR_IO8(0x0D) -#define SPSR _SFR_IO8(0x0E) -#define SPDR _SFR_IO8(0x0F) - -/* Port D */ -#define PIND _SFR_IO8(0x10) -#define DDRD _SFR_IO8(0x11) -#define PORTD _SFR_IO8(0x12) - -/* Peripheral Enable Register */ -#define PERIPHEN _SFR_IO8(0x13) - -/* Clock Control Register */ -#define CLK_CNTR _SFR_IO8(0x14) - -/* Data Register, Port C */ -#define PORTC _SFR_IO8(0x15) - -/* Port B */ -#define PINB _SFR_IO8(0x16) -#define DDRB _SFR_IO8(0x17) -#define PORTB _SFR_IO8(0x18) - -/* Port A */ -#define PINA _SFR_IO8(0x19) -#define DDRA _SFR_IO8(0x1A) -#define PORTA _SFR_IO8(0x1B) - -/* 0x1C-0x1F reserved */ - -#define IRDAMOD _SFR_IO8(0x20) - -#define WDTCR _SFR_IO8(0x21) - -/* 0x22-0x25 reserved */ -/* Timer 1 */ -#define ICR1 _SFR_IO16(0x26) -#define ICR1L _SFR_IO8(0x26) -#define ICR1H _SFR_IO8(0x27) -#define OCR1B _SFR_IO16(0x28) -#define OCR1BL _SFR_IO8(0x28) -#define OCR1BH _SFR_IO8(0x29) -#define OCR1A _SFR_IO16(0x2A) -#define OCR1AL _SFR_IO8(0x2A) -#define OCR1AH _SFR_IO8(0x2B) -#define TCNT1 _SFR_IO16(0x2C) -#define TCNT1L _SFR_IO8(0x2C) -#define TCNT1H _SFR_IO8(0x2D) -#define TCCR1B _SFR_IO8(0x2E) -#define TCCR1A _SFR_IO8(0x2F) - -/* 0x30 reserved */ - -/* Timer 0 */ -#define PRELD _SFR_IO8(0x31) -#define TCNT0 _SFR_IO8(0x32) -#define TCCR0 _SFR_IO8(0x33) - -#define MCUSR _SFR_IO8(0x34) -#define MCUCR _SFR_IO8(0x35) - -#define TIFR _SFR_IO8(0x36) -#define TIMSK _SFR_IO8(0x37) - -/* 0x38 reserved */ - -#define EIMSK _SFR_IO8(0x39) - -/* 0x3A-0x3C reserved */ - -/* 0x3D..0x3E SP */ - -/* 0x3F SREG */ - -/* Interrupt vectors */ - -#define SIG_SUSPEND_RESUME _VECTOR(1) -#define SIG_INTERRUPT0 _VECTOR(2) -#define SIG_INPUT_CAPTURE1 _VECTOR(3) -#define SIG_OUTPUT_COMPARE1A _VECTOR(4) -#define SIG_OUTPUT_COMPARE1B _VECTOR(5) -#define SIG_OVERFLOW1 _VECTOR(6) -#define SIG_OVERFLOW0 _VECTOR(7) -#define SIG_SPI _VECTOR(8) -#define SIG_TDMAC _VECTOR(9) -#define SIG_UART0 _VECTOR(10) -#define SIG_RDMAC _VECTOR(11) -#define SIG_USB_HW _VECTOR(12) -#define SIG_UART1 _VECTOR(13) -#define SIG_INTERRUPT1 _VECTOR(14) - -#define _VECTORS_SIZE 60 - -/* Bit numbers */ - -/* EIMSK */ -/* bits 7-4 reserved */ -#define POL1 3 -#define POL0 2 -#define INT1 1 -#define INT0 0 - -/* TIMSK */ -#define TOIE1 7 -#define OCIE1A 6 -#define OCIE1B 5 -/* bit 4 reserved */ -#define TICIE1 3 -/* bit 2 reserved */ -#define TOIE0 1 -/* bit 0 reserved */ - -/* TIFR */ -#define TOV1 7 -#define OCF1A 6 -#define OCF1B 5 -/* bit 4 reserved */ -#define ICF1 3 -/* bit 2 reserved */ -#define TOV0 1 -/* bit 0 reserved */ - -/* MCUCR */ -/* bits 7-6 reserved */ -#define SE 5 -#define SM1 4 -#define SM0 3 -/* bits 2-0 reserved */ - -/* MCUSR */ -/* bits 7-2 reserved */ -#define EXTRF 1 -#define PORF 0 - -/* TCCR0 */ -/* bits 7-6 reserved */ -#define COM01 5 -#define COM00 4 -#define CTC0 3 -#define CS02 2 -#define CS01 1 -#define CS00 0 - -/* TCCR1A */ -#define COM1A1 7 -#define COM1A0 6 -#define COM1B1 5 -#define COM1B0 4 -/* bits 3-0 reserved */ - -/* TCCR1B */ -#define ICNC1 7 -#define ICES1 6 -/* bits 5-4 reserved */ -#define CTC1 3 -#define CS12 2 -#define CS11 1 -#define CS10 0 - -/* WDTCR */ -/* bits 7-5 reserved */ -#define WDTOE 4 -#define WDE 3 -#define WDP2 2 -#define WDP1 1 -#define WDP0 0 - -/* IRDAMOD */ -/* bits 7-3 reserved */ -#define POL 2 -#define MODE 1 -#define EN 0 - -/* PORTA */ -#define PA7 7 -#define PA6 6 -#define PA5 5 -#define PA4 4 -#define PA3 3 -#define PA2 2 -#define PA1 1 -#define PA0 0 - -/* DDRA */ -#define DDA7 7 -#define DDA6 6 -#define DDA5 5 -#define DDA4 4 -#define DDA3 3 -#define DDA2 2 -#define DDA1 1 -#define DDA0 0 - -/* PINA */ -#define PINA7 7 -#define PINA6 6 -#define PINA5 5 -#define PINA4 4 -#define PINA3 3 -#define PINA2 2 -#define PINA1 1 -#define PINA0 0 - -/* - PB7 = SCK - PB6 = MISO - PB5 = MOSI - PB4 = SS# - PB2 = ICP - PB1 = T1 - PB0 = T0 - */ - -/* PORTB */ -#define PB7 7 -#define PB6 6 -#define PB5 5 -#define PB4 4 -#define PB3 3 -#define PB2 2 -#define PB1 1 -#define PB0 0 - -/* DDRB */ -#define DDB7 7 -#define DDB6 6 -#define DDB5 5 -#define DDB4 4 -#define DDB3 3 -#define DDB2 2 -#define DDB1 1 -#define DDB0 0 - -/* PINB */ -#define PINB7 7 -#define PINB6 6 -#define PINB5 5 -#define PINB4 4 -#define PINB3 3 -#define PINB2 2 -#define PINB1 1 -#define PINB0 0 - -/* PORTC */ -/* bits 7-4 reserved */ -#define PC3 3 -#define PC2 2 -#define PC1 1 -#define PC0 0 - -/* - PD7 = INT1 / OC1B - PD6 = INT0 / OC1A - PD1 = TXD - PD0 = RXD - */ - -/* PORTD */ -#define PD7 7 -#define PD6 6 -#define PD5 5 -#define PD4 4 -#define PD3 3 -#define PD2 2 -#define PD1 1 -#define PD0 0 - -/* DDRD */ -#define DDD7 7 -#define DDD6 6 -#define DDD5 5 -#define DDD4 4 -#define DDD3 3 -#define DDD2 2 -#define DDD1 1 -#define DDD0 0 - -/* PIND */ -#define PIND7 7 -#define PIND6 6 -#define PIND5 5 -#define PIND4 4 -#define PIND3 3 -#define PIND2 2 -#define PIND1 1 -#define PIND0 0 - -/* CLK_CNTR */ -/* bits 7-5 reserved */ -#define UOSC 4 -#define UCK 3 -#define IRCK 2 -/* bits 1-0 reserved */ - -/* PERIPHEN */ -/* bits 7-3 reserved */ -#define IRDA 2 -#define UART 1 -#define USB 0 - -/* SPSR */ -#define SPIF 7 -#define WCOL 6 -/* bits 5-0 reserved */ - -/* SPCR */ -#define SPIE 7 -#define SPE 6 -#define DORD 5 -#define MSTR 4 -#define CPOL 3 -#define CPHA 2 -#define SPR1 1 -#define SPR0 0 - -/* Memory mapped registers (XXX - not yet changed to use _SFR_MEM8() macros) */ - -/* UART */ -#define UART0_BASE 0x2020 -#define UART1_BASE 0x2030 -/* offsets from the base address */ -#define US_RHR 0x00 -#define US_THR 0x00 -#define US_IER 0x01 -#define US_FCR 0x02 -#define US_PMR 0x03 -#define US_MR 0x04 -#define US_CSR 0x05 -#define US_CR 0x06 -#define US_BL 0x07 -#define US_BM 0x08 -#define US_RTO 0x09 -#define US_TTG 0x0A - -/* DMA */ -#define DMA_BASE 0x2000 -/* offsets from the base address */ -#define TXTADL 0x01 -#define TXPLL 0x03 -#define TXPLM 0x04 -#define TXTPLL 0x05 -#define TXTPLM 0x06 -#define RXTADL 0x07 -#define RXTADMEN 0x08 -#define RSPLL 0x09 -#define RXPLM 0x0A -#define RXTPLL 0x0B -#define RXTPLM 0x0C -#define INTCST 0x0D -/* XXX DPORG register mentioned on page 20, but undocumented */ - -/* XXX Program Memory Control Bit mentioned on page 20, but undocumented */ -#define PROGRAM_MEMORY_CONTROL_BIT 0x2040 - -/* USB */ -#define USB_BASE 0x1000 -/* offsets from the base address */ -#define FRM_NUM_H 0x0FD -#define FRM_NUM_L 0x0FC -#define GLB_STATE 0x0FB -#define SPRSR 0x0FA -#define SPRSIE 0x0F9 -#define UISR 0x0F7 -#define UIAR 0x0F5 -#define FADDR 0x0F2 -#define ENDPPGPG 0x0F1 -#define ECR0 0x0EF -#define ECR1 0x0EE -#define ECR2 0x0ED -#define ECR3 0x0EC -#define ECR4 0x0EB -#define ECR5 0x0EA -#define ECR6 0x0E9 -#define ECR7 0x0E8 -#define CSR0 0x0DF -#define CSR1 0x0DE -#define CSR2 0x0DD -#define CSR3 0x0DC -#define CSR4 0x0DB -#define CSR5 0x0DA -#define CSR6 0x0D9 -#define CSR7 0x0D8 -#define FDR0 0x0CF -#define FDR1 0x0CE -#define FDR2 0x0CD -#define FDR3 0x0CC -#define FDR4 0x0CB -#define FDR5 0x0CA -#define FDR6 0x0C9 -#define FDR7 0x0C8 -#define FBYTE_CNT0_L 0x0BF -#define FBYTE_CNT1_L 0x0BE -#define FBYTE_CNT2_L 0x0BD -#define FBYTE_CNT3_L 0x0BC -#define FBYTE_CNT4_L 0x0BB -#define FBYTE_CNT5_L 0x0BA -#define FBYTE_CNT6_L 0x0B9 -#define FBYTE_CNT7_L 0x0B8 -#define FBYTE_CNT0_H 0x0AF -#define FBYTE_CNT1_H 0x0AE -#define FBYTE_CNT2_H 0x0AD -#define FBYTE_CNT3_H 0x0AC -#define FBYTE_CNT4_H 0x0AB -#define FBYTE_CNT5_H 0x0AA -#define FBYTE_CNT6_H 0x0A9 -#define FBYTE_CNT7_H 0x0A8 -#define SLP_MD_EN 0x100 -#define IRQ_EN 0x101 -#define IRQ_STAT 0x102 -#define SUSP_WUP 0x103 -#define PA_EN 0x104 -#define USB_DMA_ADL 0x105 -#define USB_DMA_ADH 0x106 -#define USB_DMA_PLR 0x107 -#define USB_DMA_EAD 0x108 -#define USB_DMA_PLT 0x109 -#define USB_DMA_EN 0x10A - -/* Last memory addresses */ -#define RAMSTART 0x60 -#define RAMEND 0x07FF -#define XRAMEND RAMEND -#define E2END 0 -#define FLASHEND 0x3FFF - -#define SLEEP_MODE_IDLE 0 -#define SLEEP_MODE_ADC _BV(SM0) -#define SLEEP_MODE_PWR_DOWN _BV(SM1) -#define SLEEP_MODE_PWR_SAVE (_BV(SM0) | _BV(SM1)) - -/* - AT76C711 data space memory map (ranges not listed are reserved): - 0x0000 - 0x001F - AVR registers - 0x0020 - 0x005F - AVR I/O space - 0x0060 - 0x07FF - AVR data SRAM - 0x1000 - 0x1FFF - USB (not all locations used) - 0x2000 - 0x201F - DMA controller - 0x2020 - 0x202F - UART0 - 0x2030 - 0x203F - UART1 (IRDA) - 0x2040 - the mysterious Program Memory Control bit (???) - 0x3000 - 0x37FF - DPRAM - 0x8000 - 0xBFFF - program SRAM (read/write), would be nice if other - AVR devices did that as well (no need to use LPM!) - */ -#endif /* _AVR_IO76C711_H_ */ diff --git a/arduino/hardware/tools/avr/avr/include/avr/io8515.h b/arduino/hardware/tools/avr/avr/include/avr/io8515.h deleted file mode 100644 index 8aa1d9d..0000000 --- a/arduino/hardware/tools/avr/avr/include/avr/io8515.h +++ /dev/null @@ -1,501 +0,0 @@ -/* Copyright (c) 2002, Marek Michalkiewicz - All rights reserved. - - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - * Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - * Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in - the documentation and/or other materials provided with the - distribution. - - * Neither the name of the copyright holders nor the names of - contributors may be used to endorse or promote products derived - from this software without specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. */ - -/* $Id: io8515.h 2225 2011-03-02 16:27:26Z arcanum $ */ - -/* avr/io8515.h - definitions for AT90S8515 */ - -#ifndef _AVR_IO8515_H_ -#define _AVR_IO8515_H_ 1 - -/* This file should only be included from , never directly. */ - -#ifndef _AVR_IO_H_ -# error "Include instead of this file." -#endif - -#ifndef _AVR_IOXXX_H_ -# define _AVR_IOXXX_H_ "io8515.h" -#else -# error "Attempt to include more than one file." -#endif - -/* I/O registers */ - -/* Analog Comparator Control and Status Register */ -#define ACSR _SFR_IO8(0x08) - -/* UART Baud Rate Register */ -#define UBRR _SFR_IO8(0x09) - -/* UART Control Register */ -#define UCR _SFR_IO8(0x0A) - -/* UART Status Register */ -#define USR _SFR_IO8(0x0B) - -/* UART I/O Data Register */ -#define UDR _SFR_IO8(0x0C) - -/* SPI Control Register */ -#define SPCR _SFR_IO8(0x0D) - -/* SPI Status Register */ -#define SPSR _SFR_IO8(0x0E) - -/* SPI I/O Data Register */ -#define SPDR _SFR_IO8(0x0F) - -/* Input Pins, Port D */ -#define PIND _SFR_IO8(0x10) - -/* Data Direction Register, Port D */ -#define DDRD _SFR_IO8(0x11) - -/* Data Register, Port D */ -#define PORTD _SFR_IO8(0x12) - -/* Input Pins, Port C */ -#define PINC _SFR_IO8(0x13) - -/* Data Direction Register, Port C */ -#define DDRC _SFR_IO8(0x14) - -/* Data Register, Port C */ -#define PORTC _SFR_IO8(0x15) - -/* Input Pins, Port B */ -#define PINB _SFR_IO8(0x16) - -/* Data Direction Register, Port B */ -#define DDRB _SFR_IO8(0x17) - -/* Data Register, Port B */ -#define PORTB _SFR_IO8(0x18) - -/* Input Pins, Port A */ -#define PINA _SFR_IO8(0x19) - -/* Data Direction Register, Port A */ -#define DDRA _SFR_IO8(0x1A) - -/* Data Register, Port A */ -#define PORTA _SFR_IO8(0x1B) - -/* EEPROM Control Register */ -#define EECR _SFR_IO8(0x1C) - -/* EEPROM Data Register */ -#define EEDR _SFR_IO8(0x1D) - -/* EEPROM Address Register */ -#define EEAR _SFR_IO16(0x1E) -#define EEARL _SFR_IO8(0x1E) -#define EEARH _SFR_IO8(0x1F) - -/* Watchdog Timer Control Register */ -#define WDTCR _SFR_IO8(0x21) - -/* T/C 1 Input Capture Register */ -#define ICR1 _SFR_IO16(0x24) -#define ICR1L _SFR_IO8(0x24) -#define ICR1H _SFR_IO8(0x25) - -/* Timer/Counter1 Output Compare Register B */ -#define OCR1B _SFR_IO16(0x28) -#define OCR1BL _SFR_IO8(0x28) -#define OCR1BH _SFR_IO8(0x29) - -/* Timer/Counter1 Output Compare Register A */ -#define OCR1A _SFR_IO16(0x2A) -#define OCR1AL _SFR_IO8(0x2A) -#define OCR1AH _SFR_IO8(0x2B) - -/* Timer/Counter 1 */ -#define TCNT1 _SFR_IO16(0x2C) -#define TCNT1L _SFR_IO8(0x2C) -#define TCNT1H _SFR_IO8(0x2D) - -/* Timer/Counter 1 Control and Status Register */ -#define TCCR1B _SFR_IO8(0x2E) - -/* Timer/Counter 1 Control Register */ -#define TCCR1A _SFR_IO8(0x2F) - -/* Timer/Counter 0 */ -#define TCNT0 _SFR_IO8(0x32) - -/* Timer/Counter 0 Control Register */ -#define TCCR0 _SFR_IO8(0x33) - -/* MCU general Control Register */ -#define MCUCR _SFR_IO8(0x35) - -/* Timer/Counter Interrupt Flag register */ -#define TIFR _SFR_IO8(0x38) - -/* Timer/Counter Interrupt MaSK register */ -#define TIMSK _SFR_IO8(0x39) - -/* General Interrupt Flag Register */ -#define GIFR _SFR_IO8(0x3A) - -/* General Interrupt MaSK register */ -#define GIMSK _SFR_IO8(0x3B) - -/* 0x3D..0x3E SP */ - -/* 0x3F SREG */ - -/* Interrupt vectors */ - -/* External Interrupt Request 0 */ -#define INT0_vect_num 1 -#define INT0_vect _VECTOR(1) -#define SIG_INTERRUPT0 _VECTOR(1) - -/* External Interrupt Request 1 */ -#define INT1_vect_num 2 -#define INT1_vect _VECTOR(2) -#define SIG_INTERRUPT1 _VECTOR(2) - -/* Timer/Counter Capture Event */ -#define TIMER1_CAPT_vect_num 3 -#define TIMER1_CAPT_vect _VECTOR(3) -#define SIG_INPUT_CAPTURE1 _VECTOR(3) - -/* Timer/Counter1 Compare Match A */ -#define TIMER1_COMPA_vect_num 4 -#define TIMER1_COMPA_vect _VECTOR(4) -#define SIG_OUTPUT_COMPARE1A _VECTOR(4) - -/* Timer/Counter1 Compare MatchB */ -#define TIMER1_COMPB_vect_num 5 -#define TIMER1_COMPB_vect _VECTOR(5) -#define SIG_OUTPUT_COMPARE1B _VECTOR(5) - -/* Timer/Counter1 Overflow */ -#define TIMER1_OVF_vect_num 6 -#define TIMER1_OVF_vect _VECTOR(6) -#define SIG_OVERFLOW1 _VECTOR(6) - -/* Timer/Counter0 Overflow */ -#define TIMER0_OVF_vect_num 7 -#define TIMER0_OVF_vect _VECTOR(7) -#define SIG_OVERFLOW0 _VECTOR(7) - -/* Serial Transfer Complete */ -#define SPI_STC_vect_num 8 -#define SPI_STC_vect _VECTOR(8) -#define SIG_SPI _VECTOR(8) - -/* UART, Rx Complete */ -#define UART_RX_vect_num 9 -#define UART_RX_vect _VECTOR(9) -#define SIG_UART_RECV _VECTOR(9) - -/* UART Data Register Empty */ -#define UART_UDRE_vect_num 10 -#define UART_UDRE_vect _VECTOR(10) -#define SIG_UART_DATA _VECTOR(10) - -/* UART, Tx Complete */ -#define UART_TX_vect_num 11 -#define UART_TX_vect _VECTOR(11) -#define SIG_UART_TRANS _VECTOR(11) - -/* Analog Comparator */ -#define ANA_COMP_vect_num 12 -#define ANA_COMP_vect _VECTOR(12) -#define SIG_COMPARATOR _VECTOR(12) - -#define _VECTORS_SIZE 26 - -/* - The Register Bit names are represented by their bit number (0-7). -*/ - -/* General Interrupt MaSK register */ -#define INT1 7 -#define INT0 6 - -/* General Interrupt Flag Register */ -#define INTF1 7 -#define INTF0 6 - -/* Timer/Counter Interrupt MaSK register */ -#define TOIE1 7 -#define OCIE1A 6 -#define OCIE1B 5 -#define TICIE1 3 -#define TOIE0 1 - -/* Timer/Counter Interrupt Flag register */ -#define TOV1 7 -#define OCF1A 6 -#define OCF1B 5 -#define ICF1 3 -#define TOV0 1 - -/* MCU general Control Register */ -#define SRE 7 -#define SRW 6 -#define SE 5 -#define SM 4 -#define ISC11 3 -#define ISC10 2 -#define ISC01 1 -#define ISC00 0 - -/* Timer/Counter 0 Control Register */ -#define CS02 2 -#define CS01 1 -#define CS00 0 - -/* Timer/Counter 1 Control Register */ -#define COM1A1 7 -#define COM1A0 6 -#define COM1B1 5 -#define COM1B0 4 -#define PWM11 1 -#define PWM10 0 - -/* Timer/Counter 1 Control and Status Register */ -#define ICNC1 7 -#define ICES1 6 -#define CTC1 3 -#define CS12 2 -#define CS11 1 -#define CS10 0 - -/* Watchdog Timer Control Register */ -#define WDTOE 4 -#define WDE 3 -#define WDP2 2 -#define WDP1 1 -#define WDP0 0 - -/* Data Register, Port A */ -#define PA7 7 -#define PA6 6 -#define PA5 5 -#define PA4 4 -#define PA3 3 -#define PA2 2 -#define PA1 1 -#define PA0 0 - -/* Data Direction Register, Port A */ -#define DDA7 7 -#define DDA6 6 -#define DDA5 5 -#define DDA4 4 -#define DDA3 3 -#define DDA2 2 -#define DDA1 1 -#define DDA0 0 - -/* Input Pins, Port A */ -#define PINA7 7 -#define PINA6 6 -#define PINA5 5 -#define PINA4 4 -#define PINA3 3 -#define PINA2 2 -#define PINA1 1 -#define PINA0 0 - -/* Data Register, Port B */ -#define PB7 7 -#define PB6 6 -#define PB5 5 -#define PB4 4 -#define PB3 3 -#define PB2 2 -#define PB1 1 -#define PB0 0 - -/* Data Direction Register, Port B */ -#define DDB7 7 -#define DDB6 6 -#define DDB5 5 -#define DDB4 4 -#define DDB3 3 -#define DDB2 2 -#define DDB1 1 -#define DDB0 0 - -/* Input Pins, Port B */ -#define PINB7 7 -#define PINB6 6 -#define PINB5 5 -#define PINB4 4 -#define PINB3 3 -#define PINB2 2 -#define PINB1 1 -#define PINB0 0 - -/* Data Register, Port C */ -#define PC7 7 -#define PC6 6 -#define PC5 5 -#define PC4 4 -#define PC3 3 -#define PC2 2 -#define PC1 1 -#define PC0 0 - -/* Data Direction Register, Port C */ -#define DDC7 7 -#define DDC6 6 -#define DDC5 5 -#define DDC4 4 -#define DDC3 3 -#define DDC2 2 -#define DDC1 1 -#define DDC0 0 - -/* Input Pins, Port C */ -#define PINC7 7 -#define PINC6 6 -#define PINC5 5 -#define PINC4 4 -#define PINC3 3 -#define PINC2 2 -#define PINC1 1 -#define PINC0 0 - -/* Data Register, Port D */ -#define PD7 7 -#define PD6 6 -#define PD5 5 -#define PD4 4 -#define PD3 3 -#define PD2 2 -#define PD1 1 -#define PD0 0 - -/* Data Direction Register, Port D */ -#define DDD7 7 -#define DDD6 6 -#define DDD5 5 -#define DDD4 4 -#define DDD3 3 -#define DDD2 2 -#define DDD1 1 -#define DDD0 0 - -/* Input Pins, Port D */ -#define PIND7 7 -#define PIND6 6 -#define PIND5 5 -#define PIND4 4 -#define PIND3 3 -#define PIND2 2 -#define PIND1 1 -#define PIND0 0 - -/* SPI Status Register */ -#define SPIF 7 -#define WCOL 6 - -/* SPI Control Register */ -#define SPIE 7 -#define SPE 6 -#define DORD 5 -#define MSTR 4 -#define CPOL 3 -#define CPHA 2 -#define SPR1 1 -#define SPR0 0 - -/* UART Status Register */ -#define RXC 7 -#define TXC 6 -#define UDRE 5 -#define FE 4 -#define DOR 3 - -/* UART Control Register */ -#define RXCIE 7 -#define TXCIE 6 -#define UDRIE 5 -#define RXEN 4 -#define TXEN 3 -#define CHR9 2 -#define RXB8 1 -#define TXB8 0 - -/* Analog Comparator Control and Status Register */ -#define ACD 7 -#define ACO 5 -#define ACI 4 -#define ACIE 3 -#define ACIC 2 -#define ACIS1 1 -#define ACIS0 0 - -/* EEPROM Control Register */ -#define EERIE 3 -#define EEMWE 2 -#define EEWE 1 -#define EERE 0 - -/* Constants */ -#define RAMSTART 0x60 -#define RAMEND 0x25F /* Last On-Chip SRAM Location */ -#define XRAMEND 0xFFFF -#define E2END 0x1FF -#define E2PAGESIZE 0 -#define FLASHEND 0x1FFF - - -/* Fuses */ -#define FUSE_MEMORY_SIZE 1 - -/* Low Fuse Byte */ -#define FUSE_SPIEN ~_BV(1) /* Serial Program Downloading Enabled */ -#define FUSE_FSTRT ~_BV(2) /* Short Start-up time selected */ -#define LFUSE_DEFAULT (0xFF) - - -/* Lock Bits */ -#define __LOCK_BITS_EXIST - - -/* Signature */ -#define SIGNATURE_0 0x1E -#define SIGNATURE_1 0x93 -#define SIGNATURE_2 0x01 - -#define SLEEP_MODE_IDLE 0 -#define SLEEP_MODE_PWR_DOWN _BV(SM) - -#endif /* _AVR_IO8515_H_ */ diff --git a/arduino/hardware/tools/avr/avr/include/avr/io8534.h b/arduino/hardware/tools/avr/avr/include/avr/io8534.h deleted file mode 100644 index 63d4ad0..0000000 --- a/arduino/hardware/tools/avr/avr/include/avr/io8534.h +++ /dev/null @@ -1,217 +0,0 @@ -/* Copyright (c) 2002, Marek Michalkiewicz - All rights reserved. - - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - * Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - * Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in - the documentation and/or other materials provided with the - distribution. - - * Neither the name of the copyright holders nor the names of - contributors may be used to endorse or promote products derived - from this software without specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. */ - -/* $Id: io8534.h 1873 2009-02-11 17:53:39Z arcanum $ */ - -/* avr/io8534.h - definitions for AT90C8534 */ - -#ifndef _AVR_IO8534_ -#define _AVR_IO8534_ 1 - -/* This file should only be included from , never directly. */ - -#ifndef _AVR_IO_H_ -# error "Include instead of this file." -#endif - -#ifndef _AVR_IOXXX_H_ -# define _AVR_IOXXX_H_ "io8534.h" -#else -# error "Attempt to include more than one file." -#endif - -/* I/O registers */ - -/* 0x00..0x03 reserved */ - -/* ADC Data Register */ -#ifndef __ASSEMBLER__ -#define ADC _SFR_IO16(0x04) -#endif -#define ADCW _SFR_IO16(0x04) -#define ADCL _SFR_IO8(0x04) -#define ADCH _SFR_IO8(0x05) - -/* ADC Control and Status Register */ -#define ADCSR _SFR_IO8(0x06) - -/* ADC Multiplexer Select Register */ -#define ADMUX _SFR_IO8(0x07) - -/* 0x08..0x0F reserved */ - -/* General Interrupt Pin Register */ -#define GIPR _SFR_IO8(0x10) - -/* 0x11..0x19 reserved */ - -/* Data Direction Register, Port A */ -#define DDRA _SFR_IO8(0x1A) - -/* Data Register, Port A */ -#define PORTA _SFR_IO8(0x1B) - -/* EEPROM Control Register */ -#define EECR _SFR_IO8(0x1C) - -/* EEPROM Data Register */ -#define EEDR _SFR_IO8(0x1D) - -/* EEPROM Address Register */ -#define EEAR _SFR_IO16(0x1E) -#define EEARL _SFR_IO8(0x1E) -#define EEARH _SFR_IO8(0x1F) - -/* 0x20..0x2B reserved */ - -/* Timer/Counter1 */ -#define TCNT1 _SFR_IO16(0x2C) -#define TCNT1L _SFR_IO8(0x2C) -#define TCNT1H _SFR_IO8(0x2D) - -/* Timer/Counter1 Control Register */ -#define TCCR1 _SFR_IO8(0x2E) - -/* 0x2F..0x31 reserved */ - -/* Timer/Counter0 (8-bit) */ -#define TCNT0 _SFR_IO8(0x32) - -/* Timer/Counter0 Control Register */ -#define TCCR0 _SFR_IO8(0x33) - -/* 0x34 reserved */ - -/* MCU general Control Register */ -#define MCUCR _SFR_IO8(0x35) - -/* 0x36..0x37 reserved */ - -/* Timer/Counter Interrupt Flag Register */ -#define TIFR _SFR_IO8(0x38) - -/* Timer/Counter Interrupt MaSK Register */ -#define TIMSK _SFR_IO8(0x39) - -/* General Interrupt Flag Register */ -#define GIFR _SFR_IO8(0x3A) - -/* General Interrupt MaSK register */ -#define GIMSK _SFR_IO8(0x3B) - -/* 0x3C reserved */ - -/* 0x3D..0x3E SP */ - -/* 0x3F SREG */ - -/* Interrupt vectors */ - -#define SIG_INTERRUPT0 _VECTOR(1) -#define SIG_INTERRUPT1 _VECTOR(2) -#define SIG_OVERFLOW1 _VECTOR(3) -#define SIG_OVERFLOW0 _VECTOR(4) -#define SIG_ADC _VECTOR(5) -#define SIG_EEPROM_READY _VECTOR(6) - -#define _VECTORS_SIZE 14 - -/* Bit numbers */ - -/* GIMSK */ -#define INT1 7 -#define INT0 6 - -/* GIFR */ -#define INTF1 7 -#define INTF0 6 - -/* GIPR */ -#define IPIN1 3 -#define IPIN0 2 - -/* TIMSK */ -#define TOIE1 2 -#define TOIE0 0 - -/* TIFR */ -#define TOV1 2 -#define TOV0 0 - -/* MCUCR */ -#define SE 6 -#define SM 5 -#define ISC1 2 -#define ISC0 0 - -/* TCCR0 */ -#define CS02 2 -#define CS01 1 -#define CS00 0 - -/* TCCR1 */ -#define CS12 2 -#define CS11 1 -#define CS10 0 - -/* PORTA */ -#define PA7 7 -#define PA6 6 -#define PA5 5 -#define PA4 4 -#define PA3 3 -#define PA2 2 -#define PA1 1 -#define PA0 0 - -/* DDRA */ -#define DDA7 7 -#define DDA6 6 -#define DDA5 5 -#define DDA4 4 -#define DDA3 3 -#define DDA2 2 -#define DDA1 1 -#define DDA0 0 - -/* EEPROM Control Register */ -#define EERIE 3 -#define EEMWE 2 -#define EEWE 1 -#define EERE 0 - -/* Last memory addresses */ -#define RAMSTART 0x60 -#define RAMEND 0x15F -#define XRAMEND RAMEND -#define E2END 0x1FF -#define FLASHEND 0x1FFF - -#endif /* _AVR_IO8534_H_ */ diff --git a/arduino/hardware/tools/avr/avr/include/avr/io8535.h b/arduino/hardware/tools/avr/avr/include/avr/io8535.h deleted file mode 100644 index df7784c..0000000 --- a/arduino/hardware/tools/avr/avr/include/avr/io8535.h +++ /dev/null @@ -1,589 +0,0 @@ -/* Copyright (c) 2002, Marek Michalkiewicz - All rights reserved. - - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - * Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - * Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in - the documentation and/or other materials provided with the - distribution. - - * Neither the name of the copyright holders nor the names of - contributors may be used to endorse or promote products derived - from this software without specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. */ - -/* $Id: io8535.h 2225 2011-03-02 16:27:26Z arcanum $ */ - -/* avr/io8535.h - definitions for AT90S8535 */ - -#ifndef _AVR_IO8535_H_ -#define _AVR_IO8535_H_ 1 - -/* This file should only be included from , never directly. */ - -#ifndef _AVR_IO_H_ -# error "Include instead of this file." -#endif - -#ifndef _AVR_IOXXX_H_ -# define _AVR_IOXXX_H_ "io8535.h" -#else -# error "Attempt to include more than one file." -#endif - -/* I/O registers */ - -/* ADC Data register */ -#ifndef __ASSEMBLER__ -#define ADC _SFR_IO16(0x04) -#endif -#define ADCW _SFR_IO16(0x04) -#define ADCL _SFR_IO8(0x04) -#define ADCH _SFR_IO8(0x05) - -/* ADC Control and Status Register */ -#define ADCSR _SFR_IO8(0x06) - -/* ADC MUX */ -#define ADMUX _SFR_IO8(0x07) - -/* Analog Comparator Control and Status Register */ -#define ACSR _SFR_IO8(0x08) - -/* UART Baud Rate Register */ -#define UBRR _SFR_IO8(0x09) - -/* UART Control Register */ -#define UCR _SFR_IO8(0x0A) - -/* UART Status Register */ -#define USR _SFR_IO8(0x0B) - -/* UART I/O Data Register */ -#define UDR _SFR_IO8(0x0C) - -/* SPI Control Register */ -#define SPCR _SFR_IO8(0x0D) - -/* SPI Status Register */ -#define SPSR _SFR_IO8(0x0E) - -/* SPI I/O Data Register */ -#define SPDR _SFR_IO8(0x0F) - -/* Input Pins, Port D */ -#define PIND _SFR_IO8(0x10) - -/* Data Direction Register, Port D */ -#define DDRD _SFR_IO8(0x11) - -/* Data Register, Port D */ -#define PORTD _SFR_IO8(0x12) - -/* Input Pins, Port C */ -#define PINC _SFR_IO8(0x13) - -/* Data Direction Register, Port C */ -#define DDRC _SFR_IO8(0x14) - -/* Data Register, Port C */ -#define PORTC _SFR_IO8(0x15) - -/* Input Pins, Port B */ -#define PINB _SFR_IO8(0x16) - -/* Data Direction Register, Port B */ -#define DDRB _SFR_IO8(0x17) - -/* Data Register, Port B */ -#define PORTB _SFR_IO8(0x18) - -/* Input Pins, Port A */ -#define PINA _SFR_IO8(0x19) - -/* Data Direction Register, Port A */ -#define DDRA _SFR_IO8(0x1A) - -/* Data Register, Port A */ -#define PORTA _SFR_IO8(0x1B) - -/* EEPROM Control Register */ -#define EECR _SFR_IO8(0x1C) - -/* EEPROM Data Register */ -#define EEDR _SFR_IO8(0x1D) - -/* EEPROM Address Register */ -#define EEAR _SFR_IO16(0x1E) -#define EEARL _SFR_IO8(0x1E) -#define EEARH _SFR_IO8(0x1F) - -/* Watchdog Timer Control Register */ -#define WDTCR _SFR_IO8(0x21) - -/* Asynchronous mode Status Register */ -#define ASSR _SFR_IO8(0x22) - -/* Timer/Counter2 Output Compare Register */ -#define OCR2 _SFR_IO8(0x23) - -/* Timer/Counter 2 */ -#define TCNT2 _SFR_IO8(0x24) - -/* Timer/Counter 2 Control Register */ -#define TCCR2 _SFR_IO8(0x25) - -/* T/C 1 Input Capture Register */ -#define ICR1 _SFR_IO16(0x26) -#define ICR1L _SFR_IO8(0x26) -#define ICR1H _SFR_IO8(0x27) - -/* Timer/Counter1 Output Compare Register B */ -#define OCR1B _SFR_IO16(0x28) -#define OCR1BL _SFR_IO8(0x28) -#define OCR1BH _SFR_IO8(0x29) - -/* Timer/Counter1 Output Compare Register A */ -#define OCR1A _SFR_IO16(0x2A) -#define OCR1AL _SFR_IO8(0x2A) -#define OCR1AH _SFR_IO8(0x2B) - -/* Timer/Counter 1 */ -#define TCNT1 _SFR_IO16(0x2C) -#define TCNT1L _SFR_IO8(0x2C) -#define TCNT1H _SFR_IO8(0x2D) - -/* Timer/Counter 1 Control and Status Register */ -#define TCCR1B _SFR_IO8(0x2E) - -/* Timer/Counter 1 Control Register */ -#define TCCR1A _SFR_IO8(0x2F) - -/* Timer/Counter 0 */ -#define TCNT0 _SFR_IO8(0x32) - -/* Timer/Counter 0 Control Register */ -#define TCCR0 _SFR_IO8(0x33) - -/* MCU general Status Register */ -#define MCUSR _SFR_IO8(0x34) - -/* MCU general Control Register */ -#define MCUCR _SFR_IO8(0x35) - -/* Timer/Counter Interrupt Flag register */ -#define TIFR _SFR_IO8(0x38) - -/* Timer/Counter Interrupt MaSK register */ -#define TIMSK _SFR_IO8(0x39) - -/* General Interrupt Flag Register */ -#define GIFR _SFR_IO8(0x3A) - -/* General Interrupt MaSK register */ -#define GIMSK _SFR_IO8(0x3B) - -/* 0x3D..0x3E SP */ - -/* 0x3F SREG */ - -/* Interrupt vectors */ - -/* External Interrupt 0 */ -#define INT0_vect_num 1 -#define INT0_vect _VECTOR(1) -#define SIG_INTERRUPT0 _VECTOR(1) - -/* External Interrupt 1 */ -#define INT1_vect_num 2 -#define INT1_vect _VECTOR(2) -#define SIG_INTERRUPT1 _VECTOR(2) - -/* Timer/Counter2 Compare Match */ -#define TIMER2_COMP_vect_num 3 -#define TIMER2_COMP_vect _VECTOR(3) -#define SIG_OUTPUT_COMPARE2 _VECTOR(3) - -/* Timer/Counter2 Overflow */ -#define TIMER2_OVF_vect_num 4 -#define TIMER2_OVF_vect _VECTOR(4) -#define SIG_OVERFLOW2 _VECTOR(4) - -/* Timer/Counter1 Capture Event */ -#define TIMER1_CAPT_vect_num 5 -#define TIMER1_CAPT_vect _VECTOR(5) -#define SIG_INPUT_CAPTURE1 _VECTOR(5) - -/* Timer/Counter1 Compare Match A */ -#define TIMER1_COMPA_vect_num 6 -#define TIMER1_COMPA_vect _VECTOR(6) -#define SIG_OUTPUT_COMPARE1A _VECTOR(6) - -/* Timer/Counter1 Compare Match B */ -#define TIMER1_COMPB_vect_num 7 -#define TIMER1_COMPB_vect _VECTOR(7) -#define SIG_OUTPUT_COMPARE1B _VECTOR(7) - -/* Timer/Counter1 Overflow */ -#define TIMER1_OVF_vect_num 8 -#define TIMER1_OVF_vect _VECTOR(8) -#define SIG_OVERFLOW1 _VECTOR(8) - -/* Timer/Counter0 Overflow */ -#define TIMER0_OVF_vect_num 9 -#define TIMER0_OVF_vect _VECTOR(9) -#define SIG_OVERFLOW0 _VECTOR(9) - -/* SPI Serial Transfer Complete */ -#define SPI_STC_vect_num 10 -#define SPI_STC_vect _VECTOR(10) -#define SIG_SPI _VECTOR(10) - -/* UART, RX Complete */ -#define UART_RX_vect_num 11 -#define UART_RX_vect _VECTOR(11) -#define SIG_UART_RECV _VECTOR(11) - -/* UART Data Register Empty */ -#define UART_UDRE_vect_num 12 -#define UART_UDRE_vect _VECTOR(12) -#define SIG_UART_DATA _VECTOR(12) - -/* UART, TX Complete */ -#define UART_TX_vect_num 13 -#define UART_TX_vect _VECTOR(13) -#define SIG_UART_TRANS _VECTOR(13) - -/* ADC Conversion Complete */ -#define ADC_vect_num 14 -#define ADC_vect _VECTOR(14) -#define SIG_ADC _VECTOR(14) - -/* EEPROM Ready */ -#define EE_RDY_vect_num 15 -#define EE_RDY_vect _VECTOR(15) -#define SIG_EEPROM_READY _VECTOR(15) - -/* Analog Comparator */ -#define ANA_COMP_vect_num 16 -#define ANA_COMP_vect _VECTOR(16) -#define SIG_COMPARATOR _VECTOR(16) - -#define _VECTORS_SIZE 34 - -/* - The Register Bit names are represented by their bit number (0-7). -*/ - -/* MCU general Status Register */ -#define EXTRF 1 -#define PORF 0 - -/* General Interrupt MaSK register */ -#define INT1 7 -#define INT0 6 - -/* General Interrupt Flag Register */ -#define INTF1 7 -#define INTF0 6 - -/* Timer/Counter Interrupt MaSK register */ -#define OCIE2 7 -#define TOIE2 6 -#define TICIE1 5 -#define OCIE1A 4 -#define OCIE1B 3 -#define TOIE1 2 -#define TOIE0 0 - -/* Timer/Counter Interrupt Flag register */ -#define OCF2 7 -#define TOV2 6 -#define ICF1 5 -#define OCF1A 4 -#define OCF1B 3 -#define TOV1 2 -#define TOV0 0 - -/* MCU general Control Register */ -#define SE 6 -#define SM1 5 -#define SM0 4 -#define ISC11 3 -#define ISC10 2 -#define ISC01 1 -#define ISC00 0 - -/* Timer/Counter 0 Control Register */ -#define CS02 2 -#define CS01 1 -#define CS00 0 - -/* Timer/Counter 1 Control Register */ -#define COM1A1 7 -#define COM1A0 6 -#define COM1B1 5 -#define COM1B0 4 -#define PWM11 1 -#define PWM10 0 - -/* Timer/Counter 1 Control and Status Register */ -#define ICNC1 7 -#define ICES1 6 -#define CTC1 3 -#define CS12 2 -#define CS11 1 -#define CS10 0 - -/* Timer/Counter 2 Control Register */ -#define PWM2 6 -#define COM21 5 -#define COM20 4 -#define CTC2 3 -#define CS22 2 -#define CS21 1 -#define CS20 0 - -/* Asynchronous mode Status Register */ -#define AS2 3 -#define TCN2UB 2 -#define OCR2UB 1 -#define TCR2UB 0 - -/* Watchdog Timer Control Register */ -#define WDTOE 4 -#define WDE 3 -#define WDP2 2 -#define WDP1 1 -#define WDP0 0 - -/* Data Register, Port A */ -#define PA7 7 -#define PA6 6 -#define PA5 5 -#define PA4 4 -#define PA3 3 -#define PA2 2 -#define PA1 1 -#define PA0 0 - -/* Data Direction Register, Port A */ -#define DDA7 7 -#define DDA6 6 -#define DDA5 5 -#define DDA4 4 -#define DDA3 3 -#define DDA2 2 -#define DDA1 1 -#define DDA0 0 - -/* Input Pins, Port A */ -#define PINA7 7 -#define PINA6 6 -#define PINA5 5 -#define PINA4 4 -#define PINA3 3 -#define PINA2 2 -#define PINA1 1 -#define PINA0 0 - -/* Data Register, Port B */ -#define PB7 7 -#define PB6 6 -#define PB5 5 -#define PB4 4 -#define PB3 3 -#define PB2 2 -#define PB1 1 -#define PB0 0 - -/* Data Direction Register, Port B */ -#define DDB7 7 -#define DDB6 6 -#define DDB5 5 -#define DDB4 4 -#define DDB3 3 -#define DDB2 2 -#define DDB1 1 -#define DDB0 0 - -/* Input Pins, Port B */ -#define PINB7 7 -#define PINB6 6 -#define PINB5 5 -#define PINB4 4 -#define PINB3 3 -#define PINB2 2 -#define PINB1 1 -#define PINB0 0 - -/* Data Register, Port C */ -#define PC7 7 -#define PC6 6 -#define PC5 5 -#define PC4 4 -#define PC3 3 -#define PC2 2 -#define PC1 1 -#define PC0 0 - -/* Data Direction Register, Port C */ -#define DDC7 7 -#define DDC6 6 -#define DDC5 5 -#define DDC4 4 -#define DDC3 3 -#define DDC2 2 -#define DDC1 1 -#define DDC0 0 - -/* Input Pins, Port C */ -#define PINC7 7 -#define PINC6 6 -#define PINC5 5 -#define PINC4 4 -#define PINC3 3 -#define PINC2 2 -#define PINC1 1 -#define PINC0 0 - -/* Data Register, Port D */ -#define PD7 7 -#define PD6 6 -#define PD5 5 -#define PD4 4 -#define PD3 3 -#define PD2 2 -#define PD1 1 -#define PD0 0 - -/* Data Direction Register, Port D */ -#define DDD7 7 -#define DDD6 6 -#define DDD5 5 -#define DDD4 4 -#define DDD3 3 -#define DDD2 2 -#define DDD1 1 -#define DDD0 0 - -/* Input Pins, Port D */ -#define PIND7 7 -#define PIND6 6 -#define PIND5 5 -#define PIND4 4 -#define PIND3 3 -#define PIND2 2 -#define PIND1 1 -#define PIND0 0 - -/* SPI Control Register */ -#define SPIE 7 -#define SPE 6 -#define DORD 5 -#define MSTR 4 -#define CPOL 3 -#define CPHA 2 -#define SPR1 1 -#define SPR0 0 - -/* SPI Status Register */ -#define SPIF 7 -#define WCOL 6 - -/* UART Status Register */ -#define RXC 7 -#define TXC 6 -#define UDRE 5 -#define FE 4 -#define DOR 3 - -/* UART Control Register */ -#define RXCIE 7 -#define TXCIE 6 -#define UDRIE 5 -#define RXEN 4 -#define TXEN 3 -#define CHR9 2 -#define RXB8 1 -#define TXB8 0 - -/* Analog Comparator Control and Status Register */ -#define ACD 7 -#define ACO 5 -#define ACI 4 -#define ACIE 3 -#define ACIC 2 -#define ACIS1 1 -#define ACIS0 0 - -/* ADC MUX */ -#define MUX2 2 -#define MUX1 1 -#define MUX0 0 - -/* ADC Control and Status Register */ -#define ADEN 7 -#define ADSC 6 -#define ADFR 5 -#define ADIF 4 -#define ADIE 3 -#define ADPS2 2 -#define ADPS1 1 -#define ADPS0 0 - -/* EEPROM Control Register */ -#define EERIE 3 -#define EEMWE 2 -#define EEWE 1 -#define EERE 0 - -/* Constants */ -#define RAMSTART 0x60 -#define RAMEND 0x25F /*Last On-Chip SRAM location*/ -#define XRAMEND RAMEND -#define E2END 0x1FF -#define E2PAGESIZE 0 -#define FLASHEND 0x1FFF - - -/* Fuses */ -#define FUSE_MEMORY_SIZE 1 - -/* Low Fuse Byte */ -#define FUSE_SPIEN (unsigned char)~_BV(1) /* Serial Program Downloading Enabled */ -#define FUSE_FSTRT (unsigned char)~_BV(2) /* Short Start-up time selected */ -#define LFUSE_DEFAULT (0xFF) - - -/* Lock Bits */ -#define __LOCK_BITS_EXIST - - -/* Signature */ -#define SIGNATURE_0 0x1E -#define SIGNATURE_1 0x93 -#define SIGNATURE_2 0x03 - -#define SLEEP_MODE_IDLE 0 -#define SLEEP_MODE_ADC _BV(SM0) -#define SLEEP_MODE_PWR_DOWN _BV(SM1) -#define SLEEP_MODE_PWR_SAVE (_BV(SM0) | _BV(SM1)) - -#endif /* _AVR_IO8535_H_ */ diff --git a/arduino/hardware/tools/avr/avr/include/avr/io86r401.h b/arduino/hardware/tools/avr/avr/include/avr/io86r401.h deleted file mode 100644 index f1c58eb..0000000 --- a/arduino/hardware/tools/avr/avr/include/avr/io86r401.h +++ /dev/null @@ -1,311 +0,0 @@ -/* Copyright (c) 2002, Colin O'Flynn - All rights reserved. - - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - * Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - * Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in - the documentation and/or other materials provided with the - distribution. - - * Neither the name of the copyright holders nor the names of - contributors may be used to endorse or promote products derived - from this software without specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. */ - -/* avr/io86r401.h - definitions for AT86RF401 */ - -#ifndef _AVR_IO86RF401_H_ -#define _AVR_IO86RF401_H_ 1 - -/* This file should only be included from , never directly. */ - -#ifndef _AVR_IO_H_ -# error "Include instead of this file." -#endif - -#ifndef _AVR_IOXXX_H_ -# define _AVR_IOXXX_H_ "io86r401.h" -#else -# error "Attempt to include more than one file." -#endif - -#include - -/* Status REGister */ -#define SREG _SFR_IO8(0x3F) - -/* Stack Pointer */ -#define SP _SFR_IO16(0x3D) -#define SPH _SFR_IO8(0x3E) -#define SPL _SFR_IO8(0x3D) - -/*Battery low configeration register */ -#define BL_CONFIG _SFR_IO8(0x35) - -/*Button detect register*/ -#define B_DET _SFR_IO8(0x34) - -/*AVR Configeration register*/ -#define AVR_CONFIG _SFR_IO8(0x33) - -/* I/O registers */ - -/*Data in register */ -#define IO_DATIN _SFR_IO8(0x32) - -/*Data out register */ -#define IO_DATOUT _SFR_IO8(0x31) - -/*IO Enable register */ -#define IO_ENAB _SFR_IO8(0x30) - -/* Watchdog Timer Control Register */ -#define WDTCR _SFR_IO8(0x22) - -/* Bit Timer Control Register */ -#define BTCR _SFR_IO8(0x21) - -#define BTCNT _SFR_IO8(0x20) - -/* -NOTE: EEPROM name's changed to have D in front on them, per datasheet, but -you may want to remove the leading D. -*/ -/* EEPROM Control Register */ - -/* EEPROM Address Register */ -#define DEEAR _SFR_IO8(0x1E) -#define DEEARL _SFR_IO8(0x1E) - -/* EEPROM Data Register */ -#define DEEDR _SFR_IO8(0x1D) -/* EEPROM Control Register */ -#define DEECR _SFR_IO8(0x1C) - -/* Lock Detector Configuration Register 2 */ -#define LOCKDET2 _SFR_IO8(0x17) - -/* VCO Tuning Register*/ -#define VCOTUNE _SFR_IO8(0x16) - -/* Power Attenuation Control Register */ -#define PWR_ATTEN _SFR_IO8(0x14) - -/* Transmitter Control Register */ -#define TX_CNTL _SFR_IO8(0x12) - -/* Lock Detector Configuration Register 1 */ -#define LOCKDET1 _SFR_IO8(0x10) - - -/* Interrupt vectors */ - -/* Transmission Done, Bit Timer Flag 2 Interrupt */ -#define TXDONE_vect_num 1 -#define TXDONE_vect _VECTOR(1) -#define SIG_TXDONE _VECTOR(1) - -/* Transmit Buffer Empty, Bit Itmer Flag 0 Interrupt */ -#define TXEMPTY_vect_num 2 -#define TXEMPTY_vect _VECTOR(2) -#define SIG_TXBE _VECTOR(2) - -#define _VECTORS_SIZE 12 - -/* - * The Register Bit names are represented by their bit number (0-7). - */ - -/* Lock Detector Configuration Register 1 - LOCKDET1 */ -#define UPOK 4 -#define ENKO 3 -#define BOD 2 -#define CS1 1 -#define CS0 0 - -/* Transmit Control Register - TX_CNTL */ -#define TXE 5 -#define TXK 4 -#define LOC 2 - -/* Power Attenuation Control Register - PWR_ATTEN */ -#define PCC2 5 -#define PCC1 4 -#define PCC0 3 -#define PCF2 2 -#define PCF1 1 -#define PCF0 0 - -/* VCO Tuning Register 6 - VCOTUNE --NOTE: [] removed from names*/ -#define VCOVDET1 7 -#define VCOVDET0 6 -#define VCOTUNE4 4 -#define VCOTUNE3 3 -#define VCOTUNE2 2 -#define VCOTUNE1 1 -#define VCOTUNE0 0 - -/* Lock Detector Configuration Register 2 - LOCKDET2 --NOTE: [] removed from names*/ -#define EUD 7 -#define LAT 6 -#define ULC2 5 -#define ULC1 4 -#define ULC0 3 -#define LC2 2 -#define LC1 1 -#define LC0 0 - -/* Data EEPROM Control Register - DEECR */ -#define BSY 3 -#define EEU 2 -#define EEL 1 -#define EER 0 - -/* Data EEPROM Data Register - DEEDR */ -#define ED7 7 -#define ED6 6 -#define ED5 5 -#define ED4 4 -#define ED3 3 -#define ED2 2 -#define ED1 1 -#define ED0 0 - -/* Data EEPROM Address Register - DEEAR */ -#define PA6 6 -#define PA5 5 -#define PA4 4 -#define PA3 3 -#define BA2 2 /* B is not a typo! */ -#define BA1 1 -#define BA0 0 - -/* Bit Timer Count Register - BTCNT */ -#define C7 7 -#define C6 6 -#define C5 5 -#define C4 4 -#define C3 3 -#define C2 2 -#define C1 1 -#define C0 0 - -/* Bit Timer Control Register - BTCR */ -#define C9 7 -#define C8 6 -#define M1 5 -#define M0 4 -#define IE 3 -#define F2 2 -#define DATA 1 -#define F0 0 - -/* Watchdog Timer Control Register - WDTCR */ -#define WDTOE 4 -#define WDE 3 -#define WDP2 2 -#define WDP1 1 -#define WDP0 0 - -/* I/O Enable Register - IO_ENAB */ -#define BOHYST 6 -#define IOE5 5 -#define IOE4 4 -#define IOE3 3 -#define IOE2 2 -#define IOE1 1 -#define IOE0 0 - -/* Note: No PORTB or whatever, this is the equivalent. */ -/* I/O Data Out Register - IO_DATOUT */ -#define IOO5 5 -#define IOO4 4 -#define IOO3 3 -#define IOO2 2 -#define IOO1 1 -#define IOO0 0 - -/* Note: No PINB or whatever, this is the equivalent. */ -/* I/O Data In Register - IO_DATIN */ -#define IOI5 5 -#define IOI4 4 -#define IOI3 3 -#define IOI2 2 -#define IOI1 1 -#define IOI0 0 - -/* AVR Configuration Register - AVR_CONFIG */ -#define ACS1 6 -#define ACS0 5 -#define TM 4 -#define BD 3 -#define BLI 2 -#define SLEEP 1 -#define BBM 0 - -/* Button Detect Register - B_DET */ -#define BD5 5 -#define BD4 4 -#define BD3 3 -#define BD2 2 -#define BD1 1 -#define BD0 0 - -/* Battery Low Configuration Register - BL_CONFIG */ -#define BL 7 -#define BLV 6 -#define BL5 5 -#define BL4 4 -#define BL3 3 -#define BL2 2 -#define BL1 1 -#define BL0 0 - -/* Pointer definition */ -#define XL r26 -#define XH r27 -#define YL r28 -#define YH r29 -#define ZL r30 -#define ZH r31 - -/* Constants */ -#define RAMSTART 0x60 -#define RAMEND 0xDF -#define XRAMEND RAMEND -#define E2END 0x7F -#define E2PAGESIZE 0 -#define FLASHEND 0x07FF - - -/* Fuses */ -#define FUSE_MEMORY_SIZE 0 - - -/* Lock Bits */ -#define __LOCK_BITS_EXIST - - -/* Signature */ -#define SIGNATURE_0 0x1E -#define SIGNATURE_1 0x91 -#define SIGNATURE_2 0x81 - - -#endif /* _AVR_IO86RF401_H_ */ diff --git a/arduino/hardware/tools/avr/avr/include/avr/io90pwm1.h b/arduino/hardware/tools/avr/avr/include/avr/io90pwm1.h deleted file mode 100644 index bdb64c2..0000000 --- a/arduino/hardware/tools/avr/avr/include/avr/io90pwm1.h +++ /dev/null @@ -1,1157 +0,0 @@ -/* Copyright (c) 2005, Andrey Pashchenko - Copyright (c) 2007, Anatoly Sokolov - All rights reserved. - - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - * Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - * Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in - the documentation and/or other materials provided with the - distribution. - - * Neither the name of the copyright holders nor the names of - contributors may be used to endorse or promote products derived - from this software without specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. */ - -/* $Id: io90pwm1.h 2225 2011-03-02 16:27:26Z arcanum $ */ - -/* avr/iopwm1.h - definitions for AT90PWM1 device */ - -#ifndef _AVR_IOPWM1_H_ -#define _AVR_IOPWM1_H_ 1 - -/* This file should only be included from , never directly. */ - -#ifndef _AVR_IO_H_ -# error "Include instead of this file." -#endif - -#ifndef _AVR_IOXXX_H_ -# define _AVR_IOXXX_H_ "iopwm1.h" -#else -# error "Attempt to include more than one file." -#endif - -/* I/O registers */ - -/* Reserved [0x00..0x02] */ - -/* Port B Input Pins Address */ -#define PINB _SFR_IO8(0x03) -/* PINB */ -#define PINB7 7 -#define PINB6 6 -#define PINB5 5 -#define PINB4 4 -#define PINB3 3 -#define PINB2 2 -#define PINB1 1 -#define PINB0 0 - -/* Port B Data Direction Register */ -#define DDRB _SFR_IO8(0x04) -/* DDRB */ -#define DDB7 7 -#define DDB6 6 -#define DDB5 5 -#define DDB4 4 -#define DDB3 3 -#define DDB2 2 -#define DDB1 1 -#define DDB0 0 - -/* Port B Data Register */ -#define PORTB _SFR_IO8(0x05) -/* PORTB */ -#define PB7 7 -#define PB6 6 -#define PB5 5 -#define PB4 4 -#define PB3 3 -#define PB2 2 -#define PB1 1 -#define PB0 0 - -/* Reserved [0x06..0x08] */ - -/* Port D Input Pins Address */ -#define PIND _SFR_IO8(0x09) -/* PIND */ -#define PIND7 7 -#define PIND6 6 -#define PIND5 5 -#define PIND4 4 -#define PIND3 3 -#define PIND2 2 -#define PIND1 1 -#define PIND0 0 - -/* Port D Data Direction Register */ -#define DDRD _SFR_IO8(0x0A) -/* DDRD */ -#define DDD7 7 -#define DDD6 6 -#define DDD5 5 -#define DDD4 4 -#define DDD3 3 -#define DDD2 2 -#define DDD1 1 -#define DDD0 0 - -/* Port D Data Register */ -#define PORTD _SFR_IO8(0x0B) -/* PORTD */ -#define PD7 7 -#define PD6 6 -#define PD5 5 -#define PD4 4 -#define PD3 3 -#define PD2 2 -#define PD1 1 -#define PD0 0 - -/* Port E Input Pins Address */ -#define PINE _SFR_IO8(0x0C) -/* PINE */ -#define PINE2 2 -#define PINE1 1 -#define PINE0 0 - -/* Port E Data Direction Register */ -#define DDRE _SFR_IO8(0x0D) -/* DDRE */ -#define DDE2 2 -#define DDE1 1 -#define DDE0 0 - -/* Port E Data Register */ -#define PORTE _SFR_IO8(0x0E) -/* PORTE */ -#define PE2 2 -#define PE1 1 -#define PE0 0 - -/* Reserved [0x0F..0x14] */ - -/* Timer/Counter 0 Interrupt Flag Register */ -#define TIFR0 _SFR_IO8(0x15) -/* TIFR0 */ -#define OCF0B 2 /* Output Compare Flag 0B */ -#define OCF0A 1 /* Output Compare Flag 0A */ -#define TOV0 0 /* Overflow Flag */ - -/* Timer/Counter1 Interrupt Flag Register */ -#define TIFR1 _SFR_IO8(0x16) -/* TIFR1 */ -#define ICF1 5 /* Input Capture Flag 1 */ -#define OCF1B 2 /* Output Compare Flag 1B*/ -#define OCF1A 1 /* Output Compare Flag 1A*/ -#define TOV1 0 /* Overflow Flag */ - -/* Reserved [0x17..0x18] */ - -/* General Purpose I/O Register 1 */ -#define GPIOR1 _SFR_IO8(0x19) -/* GPIOR1 */ -#define GPIOR17 7 -#define GPIOR16 6 -#define GPIOR15 5 -#define GPIOR14 4 -#define GPIOR13 3 -#define GPIOR12 2 -#define GPIOR11 1 -#define GPIOR10 0 - -/* General Purpose I/O Register 2 */ -#define GPIOR2 _SFR_IO8(0x1A) -/* GPIOR2 */ -#define GPIOR27 7 -#define GPIOR26 6 -#define GPIOR25 5 -#define GPIOR24 4 -#define GPIOR23 3 -#define GPIOR22 2 -#define GPIOR21 1 -#define GPIOR20 0 - -/* General Purpose I/O Register 3 */ -#define GPIOR3 _SFR_IO8(0x1B) -/* GPIOR3 */ -#define GPIOR37 7 -#define GPIOR36 6 -#define GPIOR35 5 -#define GPIOR34 4 -#define GPIOR33 3 -#define GPIOR32 2 -#define GPIOR31 1 -#define GPIOR30 0 - -/* External Interrupt Flag Register */ -#define EIFR _SFR_IO8(0x1C) -/* EIFR */ -#define INTF3 3 -#define INTF2 2 -#define INTF1 1 -#define INTF0 0 - -/* External Interrupt Mask Register */ -#define EIMSK _SFR_IO8(0x1D) -/* EIMSK */ -#define INT3 3 /* External Interrupt Request 3 Enable */ -#define INT2 2 /* External Interrupt Request 2 Enable */ -#define INT1 1 /* External Interrupt Request 1 Enable */ -#define INT0 0 /* External Interrupt Request 0 Enable */ - -/* General Purpose I/O Register 0 */ -#define GPIOR0 _SFR_IO8(0x1E) -/* GPIOR0 */ -#define GPIOR07 7 -#define GPIOR06 6 -#define GPIOR05 5 -#define GPIOR04 4 -#define GPIOR03 3 -#define GPIOR02 2 -#define GPIOR01 1 -#define GPIOR00 0 - -/* EEPROM Control Register */ -#define EECR _SFR_IO8(0x1F) -/* EECR */ -#define EERIE 3 /* EEPROM Ready Interrupt Enable */ -#define EEMWE 2 /* EEPROM Master Write Enable */ -#define EEWE 1 /* EEPROM Write Enable */ -#define EERE 0 /* EEPROM Read Enable */ - -/* EEPROM Data Register */ -#define EEDR _SFR_IO8(0x20) -/* EEDR */ -#define EEDR7 7 -#define EEDR6 6 -#define EEDR5 5 -#define EEDR4 4 -#define EEDR3 3 -#define EEDR2 2 -#define EEDR1 1 -#define EEDR0 0 - -/* The EEPROM Address Registers */ -#define EEAR _SFR_IO16(0x21) -#define EEARL _SFR_IO8(0x21) -#define EEARH _SFR_IO8(0x22) -/* EEARH */ -#define EEAR11 3 -#define EEAR10 2 -#define EEAR9 1 -#define EEAR8 0 -/* EEARL */ -#define EEAR7 7 -#define EEAR6 6 -#define EEAR5 5 -#define EEAR4 4 -#define EEAR3 3 -#define EEAR2 2 -#define EEAR1 1 -#define EEAR0 0 - -/* 6-char sequence denoting where to find the EEPROM registers in memory space. - Adresses denoted in hex syntax with uppercase letters. Used by the EEPROM - subroutines. - First two letters: EECR address. - Second two letters: EEDR address. - Last two letters: EEAR address. */ -#define __EEPROM_REG_LOCATIONS__ 1F2021 - -/* General Timer/Counter Control Register */ -#define GTCCR _SFR_IO8(0x23) -/* GTCCR */ -#define TSM 7 /* Timer/Counter Synchronization Mode */ -#define ICPSEL1 6 /* Timer1 Input Capture Selection Bit */ -#define PSRSYNC 0 - -/* Timer/Counter Control Register A */ -#define TCCR0A _SFR_IO8(0x24) -/* TCCR0A */ -#define COM0A1 7 /* Compare Output Mode, Phase Correct PWM Mode */ -#define COM0A0 6 /* Compare Output Mode, Phase Correct PWM Mode */ -#define COM0B1 5 /* Compare Output Mode, Fast PWm */ -#define COM0B0 4 /* Compare Output Mode, Fast PWm */ -#define WGM01 1 /* Waveform Generation Mode */ -#define WGM00 0 /* Waveform Generation Mode */ - -/* Timer/Counter Control Register B */ -#define TCCR0B _SFR_IO8(0x25) -/* TCCR0B */ -#define FOC0A 7 /* Force Output Compare A */ -#define FOC0B 6 /* Force Output Compare B */ -#define WGM02 3 /* Waveform Generation Mode */ -#define CS02 2 /* Clock Select */ -#define CS01 1 /* Clock Select */ -#define CS00 0 /* Clock Select */ - -/* Timer/Counter0 Register */ -#define TCNT0 _SFR_IO8(0x26) -/* TCNT0 */ -#define TCNT07 7 -#define TCNT06 6 -#define TCNT05 5 -#define TCNT04 4 -#define TCNT03 3 -#define TCNT02 2 -#define TCNT01 1 -#define TCNT00 0 - -/* Timer/Counter0 Output Compare Register A */ -#define OCR0A _SFR_IO8(0x27) -/* OCR0A */ -#define OCR0A7 7 -#define OCR0A6 6 -#define OCR0A5 5 -#define OCR0A4 4 -#define OCR0A3 3 -#define OCR0A2 2 -#define OCR0A1 1 -#define OCR0A0 0 - -/* Timer/Counter0 Output Compare Register B */ -#define OCR0B _SFR_IO8(0x28) -/* OCR0B */ -#define OCR0B7 7 -#define OCR0B6 6 -#define OCR0B5 5 -#define OCR0B4 4 -#define OCR0B3 3 -#define OCR0B2 2 -#define OCR0B1 1 -#define OCR0B0 0 - -/* PLL Control and Status Register */ -#define PLLCSR _SFR_IO8(0x29) -/* PLLCSR */ -#define PLLF 2 -#define PLLE 1 /* PLL Enable */ -#define PLOCK 0 /* PLL Lock Detector */ - -/* Reserved [0x2A..0x2B] */ - -/* SPI Control Register */ -#define SPCR _SFR_IO8(0x2C) -/* SPCR */ -#define SPIE 7 /* SPI Interrupt Enable */ -#define SPE 6 /* SPI Enable */ -#define DORD 5 /* Data Order */ -#define MSTR 4 /* Master/Slave Select */ -#define CPOL 3 /* Clock polarity */ -#define CPHA 2 /* Clock Phase */ -#define SPR1 1 /* SPI Clock Rate Select 1 */ -#define SPR0 0 /* SPI Clock Rate Select 0 */ - -/* SPI Status Register */ -#define SPSR _SFR_IO8(0x2D) -/* SPSR */ -#define SPIF 7 /* SPI Interrupt Flag */ -#define WCOL 6 /* Write Collision Flag */ -#define SPI2X 0 /* Double SPI Speed Bit */ - -/* SPI Data Register */ -#define SPDR _SFR_IO8(0x2E) -/* SPDR */ -#define SPD7 7 -#define SPD6 6 -#define SPD5 5 -#define SPD4 4 -#define SPD3 3 -#define SPD2 2 -#define SPD1 1 -#define SPD0 0 - -/* Reserved [0x2F] */ - -/* Analog Comparator Status Register */ -#define ACSR _SFR_IO8(0x30) -/* ACSR */ -#define ACCKDIV 7 /* Analog Comparator Clock Divider */ -#define AC2IF 6 /* Analog Comparator 2 Interrupt Flag Bit */ -#define AC0IF 4 /* Analog Comparator 0 Interrupt Flag Bit */ -#define AC2O 2 /* Analog Comparator 2 Output Bit */ -#define AC0O 0 /* Analog Comparator 0 Output Bit */ - -/* Monitor Data Register */ -#define MONDR _SFR_IO8(0x31) - -/* Monitor Stop Mode Control Register */ -#define MSMCR _SFR_IO8(0x32) - -/* Sleep Mode Control Register */ -#define SMCR _SFR_IO8(0x33) -/* SMCR */ -#define SM2 3 /* Sleep Mode Select bit2 */ -#define SM1 2 /* Sleep Mode Select bit1 */ -#define SM0 1 /* Sleep Mode Select bit0 */ -#define SE 0 /* Sleep Enable */ - -/* MCU Status Register */ -#define MCUSR _SFR_IO8(0x34) -/* MCUSR */ -#define WDRF 3 /* Watchdog Reset Flag */ -#define BORF 2 /* Brown-out Reset Flag */ -#define EXTRF 1 /* External Reset Flag */ -#define PORF 0 /* Power-on reset flag */ - -/* MCU Control Register */ -#define MCUCR _SFR_IO8(0x35) -/* MCUCR */ -#define SPIPS 7 /* SPI Pin Select */ -#define PUD 4 /* Pull-up disable */ -#define IVSEL 1 /* Interrupt Vector Select */ -#define IVCE 0 /* Interrupt Vector Change Enable */ - -/* Reserved [0x36] */ - -/* Store Program Memory Control Register */ -#define SPMCSR _SFR_IO8(0x37) -/* SPMCSR */ -#define SPMIE 7 /* SPM Interrupt Enable */ -#define RWWSB 6 /* Read While Write Section Busy */ -#define RWWSRE 4 /* Read While Write section read enable */ -#define BLBSET 3 /* Boot Lock Bit Set */ -#define PGWRT 2 /* Page Write */ -#define PGERS 1 /* Page Erase */ -#define SPMEN 0 /* Store Program Memory Enable */ - -/* Reserved [0x38..0x3C] */ - -/* 0x3D..0x3E SP [defined in ] */ -/* 0x3F SREG [defined in ] */ - -/* Watchdog Timer Control Register */ -#define WDTCSR _SFR_MEM8(0x60) -/* WDTCSR */ -#define WDIF 7 /* Watchdog Timeout Interrupt Flag */ -#define WDIE 6 /* Watchdog Timeout Interrupt Enable */ -#define WDP3 5 /* Watchdog Timer Prescaler bit3 */ -#define WDCE 4 /* Watchdog Change Enable */ -#define WDE 3 /* Watchdog Enable */ -#define WDP2 2 /* Watchdog Timer Prescaler bit2 */ -#define WDP1 1 /* Watchdog Timer Prescaler bit1 */ -#define WDP0 0 /* Watchdog Timer Prescaler bit0 */ - -/* Clock Prescaler Register */ -#define CLKPR _SFR_MEM8(0x61) -/* CLKPR */ -#define CLKPCE 7 /* Clock Prescaler Change Enable */ -#define CLKPS3 3 /* Clock Prescaler Select bit3 */ -#define CLKPS2 2 /* Clock Prescaler Select bit2 */ -#define CLKPS1 1 /* Clock Prescaler Select bit1 */ -#define CLKPS0 0 /* Clock Prescaler Select bit0 */ - -/* Reserved [0x62..0x63] */ - -/* Power Reduction Register */ -#define PRR _SFR_MEM8(0x64) -/* PRR */ -#define PRPSC2 7 /* Power Reduction PSC2 */ -#define PRPSC1 6 /* Power Reduction PSC1 */ -#define PRPSC0 5 /* Power Reduction PSC0 */ -#define PRTIM1 4 /* Power Reduction Timer/Counter1 */ -#define PRTIM0 3 /* Power Reduction Timer/Counter0 */ -#define PRSPI 2 /* Power Reduction Serial Peripheral Interface */ -#define PRADC 0 /* Power Reduction ADC */ - -#define __AVR_HAVE_PRR ((1< instead of this file." -#endif - -#ifndef _AVR_IOXXX_H_ -# define _AVR_IOXXX_H_ "io90pwm161.h" -#else -# error "Attempt to include more than one file." -#endif - -/* Registers and associated bit numbers */ - -#define ACSR _SFR_IO8(0x00) -#define AC1O 1 -#define AC2O 2 -#define AC3O 3 -#define AC1IF 5 -#define AC2IF 6 -#define AC3IF 7 - -#define TIMSK1 _SFR_IO8(0x01) -#define TOIE1 0 -#define ICIE1 5 - -#define TIFR1 _SFR_IO8(0x02) -#define TOV1 0 -#define ICF1 5 - -#define PINB _SFR_IO8(0x03) -#define PINB7 7 -#define PINB6 6 -#define PINB5 5 -#define PINB4 4 -#define PINB3 3 -#define PINB2 2 -#define PINB1 1 -#define PINB0 0 - -#define DDRB _SFR_IO8(0x04) -#define DDRB7 7 -// Inserted "DDB7" from "DDRB7" due to compatibility -#define DDB7 7 -#define DDRB6 6 -// Inserted "DDB6" from "DDRB6" due to compatibility -#define DDB6 6 -#define DDRB5 5 -// Inserted "DDB5" from "DDRB5" due to compatibility -#define DDB5 5 -#define DDRB4 4 -// Inserted "DDB4" from "DDRB4" due to compatibility -#define DDB4 4 -#define DDRB3 3 -// Inserted "DDB3" from "DDRB3" due to compatibility -#define DDB3 3 -#define DDRB2 2 -// Inserted "DDB2" from "DDRB2" due to compatibility -#define DDB2 2 -#define DDRB1 1 -// Inserted "DDB1" from "DDRB1" due to compatibility -#define DDB1 1 -#define DDRB0 0 -// Inserted "DDB0" from "DDRB0" due to compatibility -#define DDB0 0 - -#define PORTB _SFR_IO8(0x05) -#define PORTB7 7 -#define PORTB6 6 -#define PORTB5 5 -#define PORTB4 4 -#define PORTB3 3 -#define PORTB2 2 -#define PORTB1 1 -#define PORTB0 0 - -#define ADCSRA _SFR_IO8(0x06) -#define ADPS0 0 -#define ADPS1 1 -#define ADPS2 2 -#define ADIE 3 -#define ADIF 4 -#define ADATE 5 -#define ADSC 6 -#define ADEN 7 - -#define ADCSRB _SFR_IO8(0x07) -#define ADTS0 0 -#define ADTS1 1 -#define ADTS2 2 -#define ADTS3 3 -#define ADSSEN 4 -#define ADNCDIS 6 -#define ADHSM 7 - -#define ADMUX _SFR_IO8(0x08) -#define MUX0 0 -#define MUX1 1 -#define MUX2 2 -#define MUX3 3 -#define ADLAR 5 -#define REFS0 6 -#define REFS1 7 - -#define PIND _SFR_IO8(0x09) -#define PIND7 7 -#define PIND6 6 -#define PIND5 5 -#define PIND4 4 -#define PIND3 3 -#define PIND2 2 -#define PIND1 1 -#define PIND0 0 - -#define DDRD _SFR_IO8(0x0A) -#define DDRD7 7 -// Inserted "DDD7" from "DDRD7" due to compatibility -#define DDD7 7 -#define DDRD6 6 -// Inserted "DDD6" from "DDRD6" due to compatibility -#define DDD6 6 -#define DDRD5 5 -// Inserted "DDD5" from "DDRD5" due to compatibility -#define DDD5 5 -#define DDRD4 4 -// Inserted "DDD4" from "DDRD4" due to compatibility -#define DDD4 4 -#define DDRD3 3 -// Inserted "DDD3" from "DDRD3" due to compatibility -#define DDD3 3 -#define DDRD2 2 -// Inserted "DDD2" from "DDRD2" due to compatibility -#define DDD2 2 -#define DDRD1 1 -// Inserted "DDD1" from "DDRD1" due to compatibility -#define DDD1 1 -#define DDRD0 0 -// Inserted "DDD0" from "DDRD0" due to compatibility -#define DDD0 0 - -#define PORTD _SFR_IO8(0x0B) -#define PORTD7 7 -#define PORTD6 6 -#define PORTD5 5 -#define PORTD4 4 -#define PORTD3 3 -#define PORTD2 2 -#define PORTD1 1 -#define PORTD0 0 - -#define PINE _SFR_IO8(0x0C) -#define PINE2 2 -#define PINE1 1 -#define PINE0 0 - -#define DDRE _SFR_IO8(0x0D) -#define DDRE2 2 -// Inserted "DDE2" from "DDRE2" due to compatibility -#define DDE2 2 -#define DDRE1 1 -// Inserted "DDE1" from "DDRE1" due to compatibility -#define DDE1 1 -#define DDRE0 0 -// Inserted "DDE0" from "DDRE0" due to compatibility -#define DDE0 0 - -#define PORTE _SFR_IO8(0x0E) -#define PORTE2 2 -#define PORTE1 1 -#define PORTE0 0 - -#define PIM0 _SFR_IO8(0x0F) -#define PEOPE0 0 -#define PEOEPE0 1 -#define PEVE0A 3 -#define PEVE0B 4 - -#define PIFR0 _SFR_IO8(0x10) -#define PEOP0 0 -#define PRN00 1 -#define PRN01 2 -#define PEV0A 3 -#define PEV0B 4 -#define POAC0A 6 -#define POAC0B 7 - -#define PCNF0 _SFR_IO8(0x11) -#define PCLKSEL0 1 -#define POP0 2 -#define PMODE00 3 -#define PMODE01 4 -#define PLOCK0 5 -#define PALOCK0 6 -#define PFIFTY0 7 - -#define PCTL0 _SFR_IO8(0x12) -#define PRUN0 0 -#define PCCYC0 1 -#define PAOC0A 3 -#define PAOC0B 4 -#define PBFM00 2 -#define PBFM01 5 -#define PPRE00 6 -#define PPRE01 7 - -#define PIM2 _SFR_IO8(0x13) -#define PEOPE2 0 -#define PEOEPE2 1 -#define PEVE2A 3 -#define PEVE2B 4 -#define PSEIE2 5 - -#define PIFR2 _SFR_IO8(0x14) -#define PEOP2 0 -#define PRN20 1 -#define PRN21 2 -#define PEV2A 3 -#define PEV2B 4 -#define PSEI2 5 -#define POAC2A 6 -#define POAC2B 7 - -#define PCNF2 _SFR_IO8(0x15) -#define POME2 0 -#define PCLKSEL2 1 -#define POP2 2 -#define PMODE20 3 -#define PMODE21 4 -#define PLOCK2 5 -#define PALOCK2 6 -#define PFIFTY2 7 - -#define PCTL2 _SFR_IO8(0x16) -#define PRUN2 0 -#define PCCYC2 1 -#define PARUN2 2 -#define PAOC2A 3 -#define PAOC2B 4 -#define PBFM2 5 -#define PPRE20 6 -#define PPRE21 7 - -#define SPCR _SFR_IO8(0x17) -#define SPR0 0 -#define SPR1 1 -#define CPHA 2 -#define CPOL 3 -#define MSTR 4 -#define DORD 5 -#define SPE 6 -#define SPIE 7 - -#define SPSR _SFR_IO8(0x18) -#define SPI2X 0 -#define WCOL 6 -#define SPIF 7 - -#define GPIOR0 _SFR_IO8(0x19) -#define GPIOR00 0 -#define GPIOR01 1 -#define GPIOR02 2 -#define GPIOR03 3 -#define GPIOR04 4 -#define GPIOR05 5 -#define GPIOR06 6 -#define GPIOR07 7 - -#define GPIOR1 _SFR_IO8(0x1A) -#define GPIOR10 0 -#define GPIOR11 1 -#define GPIOR12 2 -#define GPIOR13 3 -#define GPIOR14 4 -#define GPIOR15 5 -#define GPIOR16 6 -#define GPIOR17 7 - -#define GPIOR2 _SFR_IO8(0x1B) -#define GPIOR20 0 -#define GPIOR21 1 -#define GPIOR22 2 -#define GPIOR23 3 -#define GPIOR24 4 -#define GPIOR25 5 -#define GPIOR26 6 -#define GPIOR27 7 - -#define EECR _SFR_IO8(0x1C) -#define EERE 0 -#define EEWE 1 -#define EEMWE 2 -#define EERIE 3 -#define EEPM0 4 -#define EEPM1 5 -#define EEPAGE 6 -#define NVMBSY 7 - -#define EEDR _SFR_IO8(0x1D) - -/* Combine EEARL and EEARH */ -#define EEAR _SFR_IO16(0x1E) - -#define EEARL _SFR_IO8(0x1E) -#define EEARH _SFR_IO8(0x1F) - -#define EIFR _SFR_IO8(0x20) -#define INTF0 0 -#define INTF1 1 -#define INTF2 2 - -#define EIMSK _SFR_IO8(0x21) -#define INT0 0 -#define INT1 1 -#define INT2 2 - -/* Combine OCR0SBL and OCR0SBH */ -#define OCR0SB _SFR_IO16(0x22) - -#define OCR0SBL _SFR_IO8(0x22) -#define OCR0SBH _SFR_IO8(0x23) - -/* Combine OCR0RBL and OCR0RBH */ -#define OCR0RB _SFR_IO16(0x24) - -#define OCR0RBL _SFR_IO8(0x24) -#define OCR0RBH _SFR_IO8(0x25) - -/* Combine OCR2SBL and OCR2SBH */ -#define OCR2SB _SFR_IO16(0x26) - -#define OCR2SBL _SFR_IO8(0x26) -#define OCR2SBH _SFR_IO8(0x27) - -/* Combine OCR2RBL and OCR2RBH */ -#define OCR2RB _SFR_IO16(0x28) - -#define OCR2RBL _SFR_IO8(0x28) -#define OCR2RBH _SFR_IO8(0x29) - -/* Combine OCR0RAL and OCR0RAH */ -#define OCR0RA _SFR_IO16(0x2A) - -#define OCR0RAL _SFR_IO8(0x2A) -#define OCR0RAH _SFR_IO8(0x2B) - -/* Combine ADCL and ADCH */ -#ifndef __ASSEMBLER__ -#define ADC _SFR_IO16(0x2C) -#endif -#define ADCW _SFR_IO16(0x2C) - -#define ADCL _SFR_IO8(0x2C) -#define ADCH _SFR_IO8(0x2D) - -/* Combine OCR2RAL and OCR2RAH */ -#define OCR2RA _SFR_IO16(0x2E) - -#define OCR2RAL _SFR_IO8(0x2E) -#define OCR2RAH _SFR_IO8(0x2F) - -/* Reserved [0x30..0x32] */ - -#define SMCR _SFR_IO8(0x33) -#define SE 0 -#define SM0 1 -#define SM1 2 -#define SM2 3 - -#define MCUSR _SFR_IO8(0x34) -#define PORF 0 -#define EXTRF 1 -#define BORF 2 -#define WDRF 3 - -#define MCUCR _SFR_IO8(0x35) -#define IVCE 0 -#define IVSEL 1 -#define CKRC81 2 -#define RSTDIS 3 -#define PUD 4 - -#define SPDR _SFR_IO8(0x36) - -#define SPMCSR _SFR_IO8(0x37) -#define SPMEN 0 -#define PGERS 1 -#define PGWRT 2 -#define BLBSET 3 -#define RWWSRE 4 -#define SIGRD 5 -#define RWWSB 6 -#define SPMIE 7 - -#define DACL _SFR_IO8(0x38) -#define DACL0 0 -#define DACL1 1 -#define DACL2 2 -#define DACL3 3 -#define DACL4 4 -#define DACL5 5 -#define DACL6 6 -#define DACL7 7 - -#define DACH _SFR_IO8(0x39) -#define DACH0 0 -#define DACH1 1 -#define DACH2 2 -#define DACH3 3 -#define DACH4 4 -#define DACH5 5 -#define DACH6 6 -#define DACH7 7 - -/* Combine TCNT1L and TCNT1H */ -#define TCNT1 _SFR_IO16(0x3A) - -#define TCNT1L _SFR_IO8(0x3A) -#define TCNT1H _SFR_IO8(0x3B) - -/* Reserved [0x3C] */ - -/* SP [0x3D..0x3E] */ - -/* SREG [0x3F] */ - -/* Combine OCR0SAL and OCR0SAH */ -#define OCR0SA _SFR_MEM16(0x60) - -#define OCR0SAL _SFR_MEM8(0x60) -#define OCR0SAH _SFR_MEM8(0x61) - -#define PFRC0A _SFR_MEM8(0x62) -#define PRFM0A0 0 -#define PRFM0A1 1 -#define PRFM0A2 2 -#define PRFM0A3 3 -#define PFLTE0A 4 -#define PELEV0A 5 -#define PISEL0A 6 -#define PCAE0A 7 - -#define PFRC0B _SFR_MEM8(0x63) -#define PRFM0B0 0 -#define PRFM0B1 1 -#define PRFM0B2 2 -#define PRFM0B3 3 -#define PFLTE0B 4 -#define PELEV0B 5 -#define PISEL0B 6 -#define PCAE0B 7 - -/* Combine OCR2SAL and OCR2SAH */ -#define OCR2SA _SFR_MEM16(0x64) - -#define OCR2SAL _SFR_MEM8(0x64) -#define OCR2SAH _SFR_MEM8(0x65) - -#define PFRC2A _SFR_MEM8(0x66) -#define PRFM2A0 0 -#define PRFM2A1 1 -#define PRFM2A2 2 -#define PRFM2A3 3 -#define PFLTE2A 4 -#define PELEV2A 5 -#define PISEL2A 6 -#define PCAE2A 7 - -#define PFRC2B _SFR_MEM8(0x67) -#define PRFM2B0 0 -#define PRFM2B1 1 -#define PRFM2B2 2 -#define PRFM2B3 3 -#define PFLTE2B 4 -#define PELEV2B 5 -#define PISEL2B 6 -#define PCAE2B 7 - -/* Combine PICR0L and PICR0H */ -#define PICR0 _SFR_MEM16(0x68) - -#define PICR0L _SFR_MEM8(0x68) -#define PICR0H _SFR_MEM8(0x69) - -#define PSOC0 _SFR_MEM8(0x6A) -#define POEN0A 0 -#define POEN0B 2 -#define PSYNC00 4 -#define PSYNC01 5 -#define PISEL0B1 6 -#define PISEL0A1 7 - -/* Reserved [0x6B] */ - -#define PICR2L _SFR_MEM8(0x6C) - -#define PICR2H _SFR_MEM8(0x6D) -#define PICR28 0 -#define PICR29 1 -#define PICR210 2 -#define PICR211 3 -#define PCST2 7 - -#define PSOC2 _SFR_MEM8(0x6E) -#define POEN2A 0 -#define POEN2C 1 -#define POEN2B 2 -#define POEN2D 3 -#define PSYNC20 4 -#define PSYNC21 5 -#define POS22 6 -#define POS23 7 - -#define POM2 _SFR_MEM8(0x6F) -#define POMV2A0 0 -#define POMV2A1 1 -#define POMV2A2 2 -#define POMV2A3 3 -#define POMV2B0 4 -#define POMV2B1 5 -#define POMV2B2 6 -#define POMV2B3 7 - -#define PCNFE2 _SFR_MEM8(0x70) -#define PISEL2B1 0 -#define PISEL2A1 1 -#define PELEV2B1 2 -#define PELEV2A1 3 -#define PBFM21 4 -#define PASDLK20 5 -#define PASDLK21 6 -#define PASDLK22 7 - -#define PASDLY2 _SFR_MEM8(0x71) - -/* Reserved [0x72..0x75] */ - -#define DACON _SFR_MEM8(0x76) -#define DAEN 0 -#define DALA 2 -#define DATS0 4 -#define DATS1 5 -#define DATS2 6 -#define DAATE 7 - -#define DIDR0 _SFR_MEM8(0x77) -#define ADC0D 0 -#define ADC1D 1 -#define ADC2D 2 -#define ADC3D 3 -#define ADC4D 4 -#define ADC5D 5 -#define ADC6D 6 -#define ADC7D 7 - -#define DIDR1 _SFR_MEM8(0x78) -#define ADC9D 0 -#define ADC10D 1 -#define AMP0POSD 2 -#define ACMP1MD 3 - -#define AMP0CSR _SFR_MEM8(0x79) -#define AMP0TS0 0 -#define AMP0TS1 1 -#define AMP0GS 3 -#define AMP0G0 4 -#define AMP0G1 5 -#define AMP0IS 6 -#define AMP0EN 7 - -#define AC1ECON _SFR_MEM8(0x7A) -#define AC1H0 0 -#define AC1H1 1 -#define AC1H2 2 -#define AC1ICE 3 -#define AC1OE 4 -#define AC1OI 5 - -#define AC2ECON _SFR_MEM8(0x7B) -#define AC2H0 0 -#define AC2H1 1 -#define AC2H2 2 -#define AC2OE 4 -#define AC2OI 5 - -#define AC3ECON _SFR_MEM8(0x7C) -#define AC3H0 0 -#define AC3H1 1 -#define AC3H2 2 -#define AC3OE 4 -#define AC3OI 5 - -#define AC1CON _SFR_MEM8(0x7D) -#define AC1M0 0 -#define AC1M1 1 -#define AC1M2 2 -#define AC1IS0 4 -#define AC1IS1 5 -#define AC1IE 6 -#define AC1EN 7 - -#define AC2CON _SFR_MEM8(0x7E) -#define AC2M0 0 -#define AC2M1 1 -#define AC2M2 2 -#define AC2IS0 4 -#define AC2IS1 5 -#define AC2IE 6 -#define AC2EN 7 - -#define AC3CON _SFR_MEM8(0x7F) -#define AC3M0 0 -#define AC3M1 1 -#define AC3M2 2 -#define AC3OEA 3 -#define AC3IS0 4 -#define AC3IS1 5 -#define AC3IE 6 -#define AC3EN 7 - -#define BGCRR _SFR_MEM8(0x80) -#define BGCR0 0 -#define BGCR1 1 -#define BGCR2 2 -#define BGCR3 3 - -#define BGCCR _SFR_MEM8(0x81) -#define BGCC0 0 -#define BGCC1 1 -#define BGCC2 2 -#define BGCC3 3 - -#define WDTCSR _SFR_MEM8(0x82) -#define WDE 3 -#define WDCE 4 -#define WDP0 0 -#define WDP1 1 -#define WDP2 2 -#define WDP3 5 -#define WDIE 6 -#define WDIF 7 - -#define CLKPR _SFR_MEM8(0x83) -#define CLKPS0 0 -#define CLKPS1 1 -#define CLKPS2 2 -#define CLKPS3 3 -#define CLKPCE 7 - -#define CLKCSR _SFR_MEM8(0x84) -#define CLKC0 0 -#define CLKC1 1 -#define CLKC2 2 -#define CLKC3 3 -#define CLKRDY 4 -#define CLKCCE 7 - -#define CLKSELR _SFR_MEM8(0x85) -#define CKSEL0 0 -#define CKSEL1 1 -#define CKSEL2 2 -#define CKSEL3 3 -#define CSUT0 4 -#define CSUT1 5 -#define COUT 6 - -#define PRR _SFR_MEM8(0x86) -#define PRADC 0 -#define PRSPI 2 -#define PRTIM1 4 -#define PRPSCR 5 -#define PRPSC2 7 - -#define __AVR_HAVE_PRR ((1<, never directly. */ - -#ifndef _AVR_IO_H_ -# error "Include instead of this file." -#endif - -#ifndef _AVR_IOXXX_H_ -# define _AVR_IOXXX_H_ "io90pwm216.h" -#else -# error "Attempt to include more than one file." -#endif - -/* I/O registers */ - -/* Port B Input Pins Address */ -#define PINB _SFR_IO8(0x03) -#define PINB0 0 -#define PINB1 1 -#define PINB2 2 -#define PINB3 3 -#define PINB4 4 -#define PINB5 5 -#define PINB6 6 -#define PINB7 7 - -/* Port B Data Direction Register */ -#define DDRB _SFR_IO8(0x04) -#define DDB0 0 -#define DDB1 1 -#define DDB2 2 -#define DDB3 3 -#define DDB4 4 -#define DDB5 5 -#define DDB6 6 -#define DDB7 7 - -/* Port B Data Register */ -#define PORTB _SFR_IO8(0x05) -#define PB0 0 -#define PB1 1 -#define PB2 2 -#define PB3 3 -#define PB4 4 -#define PB5 5 -#define PB6 6 -#define PB7 7 - -/* Port C Input Pins Address */ -#define PINC _SFR_IO8(0x06) -#define PINC0 0 -#define PINC1 1 -#define PINC2 2 -#define PINC3 3 -#define PINC4 4 -#define PINC5 5 -#define PINC6 6 -#define PINC7 7 - -/* Port C Data Direction Register */ -#define DDRC _SFR_IO8(0x07) -#define DDC0 0 -#define DDC1 1 -#define DDC2 2 -#define DDC3 3 -#define DDC4 4 -#define DDC5 5 -#define DDC6 6 -#define DDC7 7 - -/* Port C Data Register */ -#define PORTC _SFR_IO8(0x08) -#define PC0 0 -#define PC1 1 -#define PC2 2 -#define PC3 3 -#define PC4 4 -#define PC5 5 -#define PC6 6 -#define PC7 7 - -/* Port D Input Pins Address */ -#define PIND _SFR_IO8(0x09) -#define PIND0 0 -#define PIND1 1 -#define PIND2 2 -#define PIND3 3 -#define PIND4 4 -#define PIND5 5 -#define PIND6 6 -#define PIND7 7 - -/* Port D Data Direction Register */ -#define DDRD _SFR_IO8(0x0A) -#define DDD0 0 -#define DDD1 1 -#define DDD2 2 -#define DDD3 3 -#define DDD4 4 -#define DDD5 5 -#define DDD6 6 -#define DDD7 7 - -/* Port D Data Register */ -#define PORTD _SFR_IO8(0x0B) -#define PD0 0 -#define PD1 1 -#define PD2 2 -#define PD3 3 -#define PD4 4 -#define PD5 5 -#define PD6 6 -#define PD7 7 - -/* Port E Input Pins Address */ -#define PINE _SFR_IO8(0x0C) -#define PINE0 0 -#define PINE1 1 -#define PINE2 2 - -/* Port E Data Direction Register */ -#define DDRE _SFR_IO8(0x0D) -#define DDE0 0 -#define DDE1 1 -#define DDE2 2 - -/* Port E Data Register */ -#define PORTE _SFR_IO8(0x0E) -#define PE0 0 -#define PE1 1 -#define PE2 2 - -/* Timer/Counter 0 Interrupt Flag Register */ -#define TIFR0 _SFR_IO8(0x15) -#define TOV0 0 /* Overflow Flag */ -#define OCF0A 1 /* Output Compare Flag 0A */ -#define OCF0B 2 /* Output Compare Flag 0B */ - -/* Timer/Counter1 Interrupt Flag Register */ -#define TIFR1 _SFR_IO8(0x16) -#define TOV1 0 /* Overflow Flag */ -#define OCF1A 1 /* Output Compare Flag 1A*/ -#define OCF1B 2 /* Output Compare Flag 1B*/ -#define ICF1 5 /* Input Capture Flag 1 */ - -/* General Purpose I/O Register 1 */ -#define GPIOR1 _SFR_IO8(0x19) -#define GPIOR10 0 -#define GPIOR11 1 -#define GPIOR12 2 -#define GPIOR13 3 -#define GPIOR14 4 -#define GPIOR15 5 -#define GPIOR16 6 -#define GPIOR17 7 - -/* General Purpose I/O Register 2 */ -#define GPIOR2 _SFR_IO8(0x1A) -#define GPIOR20 0 -#define GPIOR21 1 -#define GPIOR22 2 -#define GPIOR23 3 -#define GPIOR24 4 -#define GPIOR25 5 -#define GPIOR26 6 -#define GPIOR27 7 - -/* General Purpose I/O Register 3 */ -#define GPIOR3 _SFR_IO8(0x1B) -#define GPIOR30 0 -#define GPIOR31 1 -#define GPIOR32 2 -#define GPIOR33 3 -#define GPIOR34 4 -#define GPIOR35 5 -#define GPIOR36 6 -#define GPIOR37 7 - -/* External Interrupt Flag Register */ -#define EIFR _SFR_IO8(0x1C) -#define INTF0 0 -#define INTF1 1 -#define INTF2 2 -#define INTF3 3 - -/* External Interrupt Mask Register */ -#define EIMSK _SFR_IO8(0x1D) -#define INT0 0 /* External Interrupt Request 0 Enable */ -#define INT1 1 /* External Interrupt Request 1 Enable */ -#define INT2 2 /* External Interrupt Request 2 Enable */ -#define INT3 3 /* External Interrupt Request 3 Enable */ - -/* General Purpose I/O Register 0 */ -#define GPIOR0 _SFR_IO8(0x1E) -#define GPIOR00 0 -#define GPIOR01 1 -#define GPIOR02 2 -#define GPIOR03 3 -#define GPIOR04 4 -#define GPIOR05 5 -#define GPIOR06 6 -#define GPIOR07 7 - -/* EEPROM Control Register */ -#define EECR _SFR_IO8(0x1F) -#define EERE 0 /* EEPROM Read Enable */ -#define EEWE 1 /* EEPROM Write Enable */ -#define EEMWE 2 /* EEPROM Master Write Enable */ -#define EERIE 3 /* EEPROM Ready Interrupt Enable */ - -/* EEPROM Data Register */ -#define EEDR _SFR_IO8(0x20) -#define EEDR0 0 -#define EEDR1 1 -#define EEDR2 2 -#define EEDR3 3 -#define EEDR4 4 -#define EEDR5 5 -#define EEDR6 6 -#define EEDR7 7 - -/* The EEPROM Address Registers */ -#define EEAR _SFR_IO16(0x21) -#define EEARL _SFR_IO8(0x21) -#define EEAR0 0 -#define EEAR1 1 -#define EEAR2 2 -#define EEAR3 3 -#define EEAR4 4 -#define EEAR5 5 -#define EEAR6 6 -#define EEAR7 7 -#define EEARH _SFR_IO8(0x22) -#define EEAR8 0 -#define EEAR9 1 -#define EEAR10 2 -#define EEAR11 3 - -/* 6-char sequence denoting where to find the EEPROM registers in memory space. - Adresses denoted in hex syntax with uppercase letters. Used by the EEPROM - subroutines. - First two letters: EECR address. - Second two letters: EEDR address. - Last two letters: EEAR address. */ -#define __EEPROM_REG_LOCATIONS__ 1F2021 - -/* General Timer/Counter Control Register */ -#define GTCCR _SFR_IO8(0x23) -#define PSR10 0 /* Prescaler Reset Timer/Counter1 and Timer/Counter0 */ -#define ICPSEL1 6 /* Timer1 Input Capture Selection Bit */ -#define TSM 7 /* Timer/Counter Synchronization Mode */ - -/* Timer/Counter Control Register A */ -#define TCCR0A _SFR_IO8(0x24) -#define WGM00 0 /* Waveform Generation Mode */ -#define WGM01 1 /* Waveform Generation Mode */ -#define COM0B0 4 /* Compare Output Mode, Fast PWm */ -#define COM0B1 5 /* Compare Output Mode, Fast PWm */ -#define COM0A0 6 /* Compare Output Mode, Phase Correct PWM Mode */ -#define COM0A1 7 /* Compare Output Mode, Phase Correct PWM Mode */ - -/* Timer/Counter Control Register B */ -#define TCCR0B _SFR_IO8(0x25) -#define CS00 0 /* Clock Select */ -#define CS01 1 /* Clock Select */ -#define CS02 2 /* Clock Select */ -#define WGM02 3 /* Waveform Generation Mode */ -#define FOC0B 6 /* Force Output Compare B */ -#define FOC0A 7 /* Force Output Compare A */ - -/* Timer/Counter0 Register */ -#define TCNT0 _SFR_IO8(0x26) -#define TCNT00 0 -#define TCNT01 1 -#define TCNT02 2 -#define TCNT03 3 -#define TCNT04 4 -#define TCNT05 5 -#define TCNT06 6 -#define TCNT07 7 - -/* Timer/Counter0 Output Compare Register A */ -#define OCR0A _SFR_IO8(0x27) -#define OCR0A0 0 -#define OCR0A1 1 -#define OCR0A2 2 -#define OCR0A3 3 -#define OCR0A4 4 -#define OCR0A5 5 -#define OCR0A6 6 -#define OCR0A7 7 - -/* Timer/Counter0 Output Compare Register B */ -#define OCR0B _SFR_IO8(0x28) -#define OCR0B0 0 -#define OCR0B1 1 -#define OCR0B2 2 -#define OCR0B3 3 -#define OCR0B4 4 -#define OCR0B5 5 -#define OCR0B6 6 -#define OCR0B7 7 - -/* PLL Control and Status Register */ -#define PLLCSR _SFR_IO8(0x29) -#define PLOCK 0 /* PLL Lock Detector */ -#define PLLE 1 /* PLL Enable */ -#define PLLF 2 /* PLL Factor */ - -/* SPI Control Register */ -#define SPCR _SFR_IO8(0x2C) -#define SPR0 0 /* SPI Clock Rate Select 0 */ -#define SPR1 1 /* SPI Clock Rate Select 1 */ -#define CPHA 2 /* Clock Phase */ -#define CPOL 3 /* Clock polarity */ -#define MSTR 4 /* Master/Slave Select */ -#define DORD 5 /* Data Order */ -#define SPE 6 /* SPI Enable */ -#define SPIE 7 /* SPI Interrupt Enable */ - -/* SPI Status Register */ -#define SPSR _SFR_IO8(0x2D) -#define SPI2X 0 /* Double SPI Speed Bit */ -#define WCOL 6 /* Write Collision Flag */ -#define SPIF 7 /* SPI Interrupt Flag */ - -/* SPI Data Register */ -#define SPDR _SFR_IO8(0x2E) -#define SPD0 0 -#define SPD1 1 -#define SPD2 2 -#define SPD3 3 -#define SPD4 4 -#define SPD5 5 -#define SPD6 6 -#define SPD7 7 - -/* Analog Comparator Status Register */ -#define ACSR _SFR_IO8(0x30) -#define AC0O 0 /* Analog Comparator 0 Output Bit */ -#define AC1O 1 /* Analog Comparator 1 Output Bit */ -#define AC2O 2 /* Analog Comparator 2 Output Bit */ -#define AC0IF 4 /* Analog Comparator 0 Interrupt Flag Bit */ -#define AC1IF 5 /* Analog Comparator 1 Interrupt Flag Bit */ -#define AC2IF 6 /* Analog Comparator 2 Interrupt Flag Bit */ -#define ACCKDIV 7 /* Analog Comparator Clock Divider */ - -/* Sleep Mode Control Register */ -#define SMCR _SFR_IO8(0x33) -#define SE 0 /* Sleep Enable */ -#define SM0 1 /* Sleep Mode Select bit0 */ -#define SM1 2 /* Sleep Mode Select bit1 */ -#define SM2 3 /* Sleep Mode Select bit2 */ - -/* MCU Status Register */ -#define MCUSR _SFR_IO8(0x34) -#define PORF 0 /* Power-on reset flag */ -#define EXTRF 1 /* External Reset Flag */ -#define BORF 2 /* Brown-out Reset Flag */ -#define WDRF 3 /* Watchdog Reset Flag */ - -/* MCU Control Register */ -#define MCUCR _SFR_IO8(0x35) -#define IVCE 0 /* Interrupt Vector Change Enable */ -#define IVSEL 1 /* Interrupt Vector Select */ -#define PUD 4 /* Pull-up disable */ -#define SPIPS 7 /* SPI Pin Select */ - -/* Store Program Memory Control Register */ -#define SPMCSR _SFR_IO8(0x37) -#define SPMEN 0 /* Store Program Memory Enable */ -#define PGERS 1 /* Page Erase */ -#define PGWRT 2 /* Page Write */ -#define BLBSET 3 /* Boot Lock Bit Set */ -#define RWWSRE 4 /* Read While Write section read enable */ -#define RWWSB 6 /* Read While Write Section Busy */ -#define SPMIE 7 /* SPM Interrupt Enable */ - -/* Watchdog Timer Control Register */ -#define WDTCSR _SFR_MEM8(0x60) -#define WDP0 0 /* Watchdog Timer Prescaler bit0 */ -#define WDP1 1 /* Watchdog Timer Prescaler bit1 */ -#define WDP2 2 /* Watchdog Timer Prescaler bit2 */ -#define WDE 3 /* Watchdog Enable */ -#define WDCE 4 /* Watchdog Change Enable */ -#define WDP3 5 /* Watchdog Timer Prescaler bit3 */ -#define WDIE 6 /* Watchdog Timeout Interrupt Enable */ -#define WDIF 7 /* Watchdog Timeout Interrupt Flag */ - -/* Clock Prescaler Register */ -#define CLKPR _SFR_MEM8(0x61) -#define CLKPS0 0 /* Clock Prescaler Select bit0 */ -#define CLKPS1 1 /* Clock Prescaler Select bit1 */ -#define CLKPS2 2 /* Clock Prescaler Select bit2 */ -#define CLKPS3 3 /* Clock Prescaler Select bit3 */ -#define CLKPCE 7 /* Clock Prescaler Change Enable */ - -/* Power Reduction Register */ -#define PRR _SFR_MEM8(0x64) -#define PRADC 0 /* Power Reduction ADC */ -#define PRUSART0 1 /* Power Reduction USART0 */ -#define PRUSART PRUSART0 /* Define to maintain backward-compatibility */ -#define PRSPI 2 /* Power Reduction Serial Peripheral Interface */ -#define PRTIM0 3 /* Power Reduction Timer/Counter0 */ -#define PRTIM1 4 /* Power Reduction Timer/Counter1 */ -#define PRPSC0 5 /* Power Reduction PSC0 */ -#define PRPSC1 6 /* Power Reduction PSC1 */ -#define PRPSC2 7 /* Power Reduction PSC2 */ - -#define __AVR_HAVE_PRR ((1<, never directly. */ - -#ifndef _AVR_IO_H_ -# error "Include instead of this file." -#endif - -#ifndef _AVR_IOXXX_H_ -# define _AVR_IOXXX_H_ "io90pwm2b.h" -#else -# error "Attempt to include more than one file." -#endif - - -#ifndef _AVR_IO90PWM2B_H_ -#define _AVR_IO90PWM2B_H_ 1 - -/* Registers and associated bit numbers */ - -#define PINB _SFR_IO8(0x03) -#define PINB0 0 -#define PINB1 1 -#define PINB2 2 -#define PINB3 3 -#define PINB4 4 -#define PINB5 5 -#define PINB6 6 -#define PINB7 7 - -#define DDRB _SFR_IO8(0x04) -#define DDB0 0 -#define DDB1 1 -#define DDB2 2 -#define DDB3 3 -#define DDB4 4 -#define DDB5 5 -#define DDB6 6 -#define DDB7 7 - -#define PORTB _SFR_IO8(0x05) -#define PORTB0 0 -#define PORTB1 1 -#define PORTB2 2 -#define PORTB3 3 -#define PORTB4 4 -#define PORTB5 5 -#define PORTB6 6 -#define PORTB7 7 - -#define PINC _SFR_IO8(0x06) -#define PINC0 0 -#define PINC1 1 -#define PINC2 2 -#define PINC3 3 -#define PINC4 4 -#define PINC5 5 -#define PINC6 6 -#define PINC7 7 - -#define DDRC _SFR_IO8(0x07) -#define DDC0 0 -#define DDC1 1 -#define DDC2 2 -#define DDC3 3 -#define DDC4 4 -#define DDC5 5 -#define DDC6 6 -#define DDC7 7 - -#define PORTC _SFR_IO8(0x08) -#define PORTC0 0 -#define PORTC1 1 -#define PORTC2 2 -#define PORTC3 3 -#define PORTC4 4 -#define PORTC5 5 -#define PORTC6 6 -#define PORTC7 7 - -#define PIND _SFR_IO8(0x09) -#define PIND0 0 -#define PIND1 1 -#define PIND2 2 -#define PIND3 3 -#define PIND4 4 -#define PIND5 5 -#define PIND6 6 -#define PIND7 7 - -#define DDRD _SFR_IO8(0x0A) -#define DDD0 0 -#define DDD1 1 -#define DDD2 2 -#define DDD3 3 -#define DDD4 4 -#define DDD5 5 -#define DDD6 6 -#define DDD7 7 - -#define PORTD _SFR_IO8(0x0B) -#define PORTD0 0 -#define PORTD1 1 -#define PORTD2 2 -#define PORTD3 3 -#define PORTD4 4 -#define PORTD5 5 -#define PORTD6 6 -#define PORTD7 7 - -#define PINE _SFR_IO8(0x0C) -#define PINE0 0 -#define PINE1 1 -#define PINE2 2 - -#define DDRE _SFR_IO8(0x0D) -#define DDE0 0 -#define DDE1 1 -#define DDE2 2 - -#define PORTE _SFR_IO8(0x0E) -#define PORTE0 0 -#define PORTE1 1 -#define PORTE2 2 - -#define TIFR0 _SFR_IO8(0x15) -#define TOV0 0 -#define OCF0A 1 -#define OCF0B 2 - -#define TIFR1 _SFR_IO8(0x16) -#define TOV1 0 -#define OCF1A 1 -#define OCF1B 2 -#define ICF1 5 - -#define GPIOR1 _SFR_IO8(0x19) -#define GPIOR10 0 -#define GPIOR11 1 -#define GPIOR12 2 -#define GPIOR13 3 -#define GPIOR14 4 -#define GPIOR15 5 -#define GPIOR16 6 -#define GPIOR17 7 - -#define GPIOR2 _SFR_IO8(0x1A) -#define GPIOR20 0 -#define GPIOR21 1 -#define GPIOR22 2 -#define GPIOR23 3 -#define GPIOR24 4 -#define GPIOR25 5 -#define GPIOR26 6 -#define GPIOR27 7 - -#define GPIOR3 _SFR_IO8(0x1B) -#define GPIOR30 0 -#define GPIOR31 1 -#define GPIOR32 2 -#define GPIOR33 3 -#define GPIOR34 4 -#define GPIOR35 5 -#define GPIOR36 6 -#define GPIOR37 7 - -#define EIFR _SFR_IO8(0x1C) -#define INTF0 0 -#define INTF1 1 -#define INTF2 2 -#define INTF3 3 - -#define EIMSK _SFR_IO8(0x1D) -#define INT0 0 -#define INT1 1 -#define INT2 2 -#define INT3 3 - -#define GPIOR0 _SFR_IO8(0x1E) -#define GPIOR00 0 -#define GPIOR01 1 -#define GPIOR02 2 -#define GPIOR03 3 -#define GPIOR04 4 -#define GPIOR05 5 -#define GPIOR06 6 -#define GPIOR07 7 - -#define EECR _SFR_IO8(0x1F) -#define EERE 0 -#define EEWE 1 -#define EEMWE 2 -#define EERIE 3 -#define EEPM0 4 -#define EEPM1 5 - -#define EEDR _SFR_IO8(0x20) -#define EEDR0 0 -#define EEDR1 1 -#define EEDR2 2 -#define EEDR3 3 -#define EEDR4 4 -#define EEDR5 5 -#define EEDR6 6 -#define EEDR7 7 - -#define EEAR _SFR_IO16(0x21) - -#define EEARL _SFR_IO8(0x21) -#define EEARL0 0 -#define EEARL1 1 -#define EEARL2 2 -#define EEARL3 3 -#define EEARL4 4 -#define EEARL5 5 -#define EEARL6 6 -#define EEARL7 7 - -#define EEARH _SFR_IO8(0x22) -#define EEAR8 0 -#define EEAR9 1 -#define EEAR10 2 -#define EEAR11 3 - -#define GTCCR _SFR_IO8(0x23) -#define PSR10 0 -#define PSRSYNC 0 -#define ICPSEL1 2 -#define TSM 3 - -#define TCCR0A _SFR_IO8(0x24) -#define WGM00 0 -#define WGM01 1 -#define COM0B0 4 -#define COM0B1 5 -#define COM0A0 6 -#define COM0A1 7 - -#define TCCR0B _SFR_IO8(0x25) -#define CS00 0 -#define CS01 1 -#define CS02 2 -#define WGM02 3 -#define FOC0B 6 -#define FOC0A 7 - -#define TCNT0 _SFR_IO8(0x26) -#define TCNT0_0 0 -#define TCNT0_1 1 -#define TCNT0_2 2 -#define TCNT0_3 3 -#define TCNT0_4 4 -#define TCNT0_5 5 -#define TCNT0_6 6 -#define TCNT0_7 7 - -#define OCR0A _SFR_IO8(0x27) -#define OCR0A_0 0 -#define OCR0A_1 1 -#define OCR0A_2 2 -#define OCR0A_3 3 -#define OCR0A_4 4 -#define OCR0A_5 5 -#define OCR0A_6 6 -#define OCR0A_7 7 - -#define OCR0B _SFR_IO8(0x28) -#define OCR0B_0 0 -#define OCR0B_1 1 -#define OCR0B_2 2 -#define OCR0B_3 3 -#define OCR0B_4 4 -#define OCR0B_5 5 -#define OCR0B_6 6 -#define OCR0B_7 7 - -#define OCR0_0 0 /* Deprecated */ -#define OCR0_1 1 /* Deprecated */ -#define OCR0_2 2 /* Deprecated */ -#define OCR0_3 3 /* Deprecated */ -#define OCR0_4 4 /* Deprecated */ -#define OCR0_5 5 /* Deprecated */ -#define OCR0_6 6 /* Deprecated */ -#define OCR0_7 7 /* Deprecated */ - -#define PLLCSR _SFR_IO8(0x29) -#define PLOCK 0 -#define PLLE 1 -#define PLLF 2 - -#define SPCR _SFR_IO8(0x2C) -#define SPR0 0 -#define SPR1 1 -#define CPHA 2 -#define CPOL 3 -#define MSTR 4 -#define DORD 5 -#define SPE 6 -#define SPIE 7 - -#define SPSR _SFR_IO8(0x2D) -#define SPI2X 0 -#define WCOL 6 -#define SPIF 7 - -#define SPDR _SFR_IO8(0x2E) -#define SPDR0 0 -#define SPDR1 1 -#define SPDR2 2 -#define SPDR3 3 -#define SPDR4 4 -#define SPDR5 5 -#define SPDR6 6 -#define SPDR7 7 - -#define ACSR _SFR_IO8(0x30) -#define AC0O 0 -#define AC1O 1 -#define AC2O 2 -#define AC0IF 4 -#define AC1IF 5 -#define AC2IF 6 -#define ACCKDIV 7 - -#define SMCR _SFR_IO8(0x33) -#define SE 0 -#define SM0 1 -#define SM1 2 -#define SM2 3 - -#define MCUSR _SFR_IO8(0x34) -#define PORF 0 -#define EXTRF 1 -#define BORF 2 -#define WDRF 3 - -#define MCUCR _SFR_IO8(0x35) -#define IVCE 0 -#define IVSEL 1 -#define PUD 4 -#define SPIPS 7 - -#define SPMCSR _SFR_IO8(0x37) -#define SPMEN 0 -#define PGERS 1 -#define PGWRT 2 -#define BLBSET 3 -#define RWWSRE 4 -#define RWWSB 6 -#define SPMIE 7 - -#define WDTCSR _SFR_MEM8(0x60) -#define WDP0 0 -#define WDP1 1 -#define WDP2 2 -#define WDE 3 -#define WDCE 4 -#define WDP3 5 -#define WDIE 6 -#define WDIF 7 - -#define CLKPR _SFR_MEM8(0x61) -#define CLKPS0 0 -#define CLKPS1 1 -#define CLKPS2 2 -#define CLKPS3 3 -#define CLKPCE 7 - -#define PRR _SFR_MEM8(0x64) -#define PRADC 0 -#define PRUSART0 1 -#define PRSPI 2 -#define PRTIM0 3 -#define PRTIM1 4 -#define PRPSC0 5 -#define PRPSC1 6 -#define PRPSC2 7 - -#define __AVR_HAVE_PRR ((1<, never directly. */ - -#ifndef _AVR_IO_H_ -# error "Include instead of this file." -#endif - -#ifndef _AVR_IOXXX_H_ -# define _AVR_IOXXX_H_ "io90pwm316.h" -#else -# error "Attempt to include more than one file." -#endif - -/* I/O registers */ - -/* Port B Input Pins Address */ -#define PINB _SFR_IO8(0x03) -#define PINB0 0 -#define PINB1 1 -#define PINB2 2 -#define PINB3 3 -#define PINB4 4 -#define PINB5 5 -#define PINB6 6 -#define PINB7 7 - -/* Port B Data Direction Register */ -#define DDRB _SFR_IO8(0x04) -#define DDB0 0 -#define DDB1 1 -#define DDB2 2 -#define DDB3 3 -#define DDB4 4 -#define DDB5 5 -#define DDB6 6 -#define DDB7 7 - -/* Port B Data Register */ -#define PORTB _SFR_IO8(0x05) -#define PB0 0 -#define PB1 1 -#define PB2 2 -#define PB3 3 -#define PB4 4 -#define PB5 5 -#define PB6 6 -#define PB7 7 - -/* Port C Input Pins Address */ -#define PINC _SFR_IO8(0x06) -#define PINC0 0 -#define PINC1 1 -#define PINC2 2 -#define PINC3 3 -#define PINC4 4 -#define PINC5 5 -#define PINC6 6 -#define PINC7 7 - -/* Port C Data Direction Register */ -#define DDRC _SFR_IO8(0x07) -#define DDC0 0 -#define DDC1 1 -#define DDC2 2 -#define DDC3 3 -#define DDC4 4 -#define DDC5 5 -#define DDC6 6 -#define DDC7 7 - -/* Port C Data Register */ -#define PORTC _SFR_IO8(0x08) -#define PC0 0 -#define PC1 1 -#define PC2 2 -#define PC3 3 -#define PC4 4 -#define PC5 5 -#define PC6 6 -#define PC7 7 - -/* Port D Input Pins Address */ -#define PIND _SFR_IO8(0x09) -#define PIND0 0 -#define PIND1 1 -#define PIND2 2 -#define PIND3 3 -#define PIND4 4 -#define PIND5 5 -#define PIND6 6 -#define PIND7 7 - -/* Port D Data Direction Register */ -#define DDRD _SFR_IO8(0x0A) -#define DDD0 0 -#define DDD1 1 -#define DDD2 2 -#define DDD3 3 -#define DDD4 4 -#define DDD5 5 -#define DDD6 6 -#define DDD7 7 - -/* Port D Data Register */ -#define PORTD _SFR_IO8(0x0B) -#define PD0 0 -#define PD1 1 -#define PD2 2 -#define PD3 3 -#define PD4 4 -#define PD5 5 -#define PD6 6 -#define PD7 7 - -/* Port E Input Pins Address */ -#define PINE _SFR_IO8(0x0C) -#define PINE0 0 -#define PINE1 1 -#define PINE2 2 - -/* Port E Data Direction Register */ -#define DDRE _SFR_IO8(0x0D) -#define DDE0 0 -#define DDE1 1 -#define DDE2 2 - -/* Port E Data Register */ -#define PORTE _SFR_IO8(0x0E) -#define PE0 0 -#define PE1 1 -#define PE2 2 - -/* Timer/Counter 0 Interrupt Flag Register */ -#define TIFR0 _SFR_IO8(0x15) -#define TOV0 0 /* Overflow Flag */ -#define OCF0A 1 /* Output Compare Flag 0A */ -#define OCF0B 2 /* Output Compare Flag 0B */ - -/* Timer/Counter1 Interrupt Flag Register */ -#define TIFR1 _SFR_IO8(0x16) -#define TOV1 0 /* Overflow Flag */ -#define OCF1A 1 /* Output Compare Flag 1A*/ -#define OCF1B 2 /* Output Compare Flag 1B*/ -#define ICF1 5 /* Input Capture Flag 1 */ - -/* General Purpose I/O Register 1 */ -#define GPIOR1 _SFR_IO8(0x19) -#define GPIOR10 0 -#define GPIOR11 1 -#define GPIOR12 2 -#define GPIOR13 3 -#define GPIOR14 4 -#define GPIOR15 5 -#define GPIOR16 6 -#define GPIOR17 7 - -/* General Purpose I/O Register 2 */ -#define GPIOR2 _SFR_IO8(0x1A) -#define GPIOR20 0 -#define GPIOR21 1 -#define GPIOR22 2 -#define GPIOR23 3 -#define GPIOR24 4 -#define GPIOR25 5 -#define GPIOR26 6 -#define GPIOR27 7 - -/* General Purpose I/O Register 3 */ -#define GPIOR3 _SFR_IO8(0x1B) -#define GPIOR30 0 -#define GPIOR31 1 -#define GPIOR32 2 -#define GPIOR33 3 -#define GPIOR34 4 -#define GPIOR35 5 -#define GPIOR36 6 -#define GPIOR37 7 - -/* External Interrupt Flag Register */ -#define EIFR _SFR_IO8(0x1C) -#define INTF0 0 -#define INTF1 1 -#define INTF2 2 -#define INTF3 3 - -/* External Interrupt Mask Register */ -#define EIMSK _SFR_IO8(0x1D) -#define INT0 0 /* External Interrupt Request 0 Enable */ -#define INT1 1 /* External Interrupt Request 1 Enable */ -#define INT2 2 /* External Interrupt Request 2 Enable */ -#define INT3 3 /* External Interrupt Request 3 Enable */ - -/* General Purpose I/O Register 0 */ -#define GPIOR0 _SFR_IO8(0x1E) -#define GPIOR00 0 -#define GPIOR01 1 -#define GPIOR02 2 -#define GPIOR03 3 -#define GPIOR04 4 -#define GPIOR05 5 -#define GPIOR06 6 -#define GPIOR07 7 - -/* EEPROM Control Register */ -#define EECR _SFR_IO8(0x1F) -#define EERE 0 /* EEPROM Read Enable */ -#define EEWE 1 /* EEPROM Write Enable */ -#define EEMWE 2 /* EEPROM Master Write Enable */ -#define EERIE 3 /* EEPROM Ready Interrupt Enable */ - -/* EEPROM Data Register */ -#define EEDR _SFR_IO8(0x20) -#define EEDR0 0 -#define EEDR1 1 -#define EEDR2 2 -#define EEDR3 3 -#define EEDR4 4 -#define EEDR5 5 -#define EEDR6 6 -#define EEDR7 7 - -/* The EEPROM Address Registers */ -#define EEAR _SFR_IO16(0x21) -#define EEARL _SFR_IO8(0x21) -#define EEAR0 0 -#define EEAR1 1 -#define EEAR2 2 -#define EEAR3 3 -#define EEAR4 4 -#define EEAR5 5 -#define EEAR6 6 -#define EEAR7 7 -#define EEARH _SFR_IO8(0x22) -#define EEAR8 0 -#define EEAR9 1 -#define EEAR10 2 -#define EEAR11 3 - -/* 6-char sequence denoting where to find the EEPROM registers in memory space. - Adresses denoted in hex syntax with uppercase letters. Used by the EEPROM - subroutines. - First two letters: EECR address. - Second two letters: EEDR address. - Last two letters: EEAR address. */ -#define __EEPROM_REG_LOCATIONS__ 1F2021 - -/* General Timer/Counter Control Register */ -#define GTCCR _SFR_IO8(0x23) -#define PSR10 0 /* Prescaler Reset Timer/Counter1 and Timer/Counter0 */ -#define ICPSEL1 6 /* Timer1 Input Capture Selection Bit */ -#define TSM 7 /* Timer/Counter Synchronization Mode */ - -/* Timer/Counter Control Register A */ -#define TCCR0A _SFR_IO8(0x24) -#define WGM00 0 /* Waveform Generation Mode */ -#define WGM01 1 /* Waveform Generation Mode */ -#define COM0B0 4 /* Compare Output Mode, Fast PWm */ -#define COM0B1 5 /* Compare Output Mode, Fast PWm */ -#define COM0A0 6 /* Compare Output Mode, Phase Correct PWM Mode */ -#define COM0A1 7 /* Compare Output Mode, Phase Correct PWM Mode */ - -/* Timer/Counter Control Register B */ -#define TCCR0B _SFR_IO8(0x25) -#define CS00 0 /* Clock Select */ -#define CS01 1 /* Clock Select */ -#define CS02 2 /* Clock Select */ -#define WGM02 3 /* Waveform Generation Mode */ -#define FOC0B 6 /* Force Output Compare B */ -#define FOC0A 7 /* Force Output Compare A */ - -/* Timer/Counter0 Register */ -#define TCNT0 _SFR_IO8(0x26) -#define TCNT00 0 -#define TCNT01 1 -#define TCNT02 2 -#define TCNT03 3 -#define TCNT04 4 -#define TCNT05 5 -#define TCNT06 6 -#define TCNT07 7 - -/* Timer/Counter0 Output Compare Register A */ -#define OCR0A _SFR_IO8(0x27) -#define OCR0A0 0 -#define OCR0A1 1 -#define OCR0A2 2 -#define OCR0A3 3 -#define OCR0A4 4 -#define OCR0A5 5 -#define OCR0A6 6 -#define OCR0A7 7 - -/* Timer/Counter0 Output Compare Register B */ -#define OCR0B _SFR_IO8(0x28) -#define OCR0B0 0 -#define OCR0B1 1 -#define OCR0B2 2 -#define OCR0B3 3 -#define OCR0B4 4 -#define OCR0B5 5 -#define OCR0B6 6 -#define OCR0B7 7 - -/* PLL Control and Status Register */ -#define PLLCSR _SFR_IO8(0x29) -#define PLOCK 0 /* PLL Lock Detector */ -#define PLLE 1 /* PLL Enable */ -#define PLLF 2 /* PLL Factor */ - -/* SPI Control Register */ -#define SPCR _SFR_IO8(0x2C) -#define SPR0 0 /* SPI Clock Rate Select 0 */ -#define SPR1 1 /* SPI Clock Rate Select 1 */ -#define CPHA 2 /* Clock Phase */ -#define CPOL 3 /* Clock polarity */ -#define MSTR 4 /* Master/Slave Select */ -#define DORD 5 /* Data Order */ -#define SPE 6 /* SPI Enable */ -#define SPIE 7 /* SPI Interrupt Enable */ - -/* SPI Status Register */ -#define SPSR _SFR_IO8(0x2D) -#define SPI2X 0 /* Double SPI Speed Bit */ -#define WCOL 6 /* Write Collision Flag */ -#define SPIF 7 /* SPI Interrupt Flag */ - -/* SPI Data Register */ -#define SPDR _SFR_IO8(0x2E) -#define SPD0 0 -#define SPD1 1 -#define SPD2 2 -#define SPD3 3 -#define SPD4 4 -#define SPD5 5 -#define SPD6 6 -#define SPD7 7 - -/* Analog Comparator Status Register */ -#define ACSR _SFR_IO8(0x30) -#define AC0O 0 /* Analog Comparator 0 Output Bit */ -#define AC1O 1 /* Analog Comparator 1 Output Bit */ -#define AC2O 2 /* Analog Comparator 2 Output Bit */ -#define AC0IF 4 /* Analog Comparator 0 Interrupt Flag Bit */ -#define AC1IF 5 /* Analog Comparator 1 Interrupt Flag Bit */ -#define AC2IF 6 /* Analog Comparator 2 Interrupt Flag Bit */ -#define ACCKDIV 7 /* Analog Comparator Clock Divider */ - -/* Sleep Mode Control Register */ -#define SMCR _SFR_IO8(0x33) -#define SE 0 /* Sleep Enable */ -#define SM0 1 /* Sleep Mode Select bit0 */ -#define SM1 2 /* Sleep Mode Select bit1 */ -#define SM2 3 /* Sleep Mode Select bit2 */ - -/* MCU Status Register */ -#define MCUSR _SFR_IO8(0x34) -#define PORF 0 /* Power-on reset flag */ -#define EXTRF 1 /* External Reset Flag */ -#define BORF 2 /* Brown-out Reset Flag */ -#define WDRF 3 /* Watchdog Reset Flag */ - -/* MCU Control Register */ -#define MCUCR _SFR_IO8(0x35) -#define IVCE 0 /* Interrupt Vector Change Enable */ -#define IVSEL 1 /* Interrupt Vector Select */ -#define PUD 4 /* Pull-up disable */ -#define SPIPS 7 /* SPI Pin Select */ - -/* Store Program Memory Control Register */ -#define SPMCSR _SFR_IO8(0x37) -#define SPMEN 0 /* Store Program Memory Enable */ -#define PGERS 1 /* Page Erase */ -#define PGWRT 2 /* Page Write */ -#define BLBSET 3 /* Boot Lock Bit Set */ -#define RWWSRE 4 /* Read While Write section read enable */ -#define RWWSB 6 /* Read While Write Section Busy */ -#define SPMIE 7 /* SPM Interrupt Enable */ - -/* Watchdog Timer Control Register */ -#define WDTCSR _SFR_MEM8(0x60) -#define WDP0 0 /* Watchdog Timer Prescaler bit0 */ -#define WDP1 1 /* Watchdog Timer Prescaler bit1 */ -#define WDP2 2 /* Watchdog Timer Prescaler bit2 */ -#define WDE 3 /* Watchdog Enable */ -#define WDCE 4 /* Watchdog Change Enable */ -#define WDP3 5 /* Watchdog Timer Prescaler bit3 */ -#define WDIE 6 /* Watchdog Timeout Interrupt Enable */ -#define WDIF 7 /* Watchdog Timeout Interrupt Flag */ - -/* Clock Prescaler Register */ -#define CLKPR _SFR_MEM8(0x61) -#define CLKPS0 0 /* Clock Prescaler Select bit0 */ -#define CLKPS1 1 /* Clock Prescaler Select bit1 */ -#define CLKPS2 2 /* Clock Prescaler Select bit2 */ -#define CLKPS3 3 /* Clock Prescaler Select bit3 */ -#define CLKPCE 7 /* Clock Prescaler Change Enable */ - -/* Power Reduction Register */ -#define PRR _SFR_MEM8(0x64) -#define PRADC 0 /* Power Reduction ADC */ -#define PRUSART0 1 /* Power Reduction USART0 */ -#define PRUSART PRUSART0 /* Define to maintain backward-compatibility */ -#define PRSPI 2 /* Power Reduction Serial Peripheral Interface */ -#define PRTIM0 3 /* Power Reduction Timer/Counter0 */ -#define PRTIM1 4 /* Power Reduction Timer/Counter1 */ -#define PRPSC0 5 /* Power Reduction PSC0 */ -#define PRPSC1 6 /* Power Reduction PSC1 */ -#define PRPSC2 7 /* Power Reduction PSC2 */ - -#define __AVR_HAVE_PRR ((1<, never directly. */ - -#ifndef _AVR_IO_H_ -# error "Include instead of this file." -#endif - -#ifndef _AVR_IOXXX_H_ -# define _AVR_IOXXX_H_ "io90pwm3b.h" -#else -# error "Attempt to include more than one file." -#endif - - -#ifndef _AVR_IO90PWM3B_H_ -#define _AVR_IO90PWM3B_H_ 1 - -/* Registers and associated bit numbers */ - -#define PINB _SFR_IO8(0x03) -#define PINB0 0 -#define PINB1 1 -#define PINB2 2 -#define PINB3 3 -#define PINB4 4 -#define PINB5 5 -#define PINB6 6 -#define PINB7 7 - -#define DDRB _SFR_IO8(0x04) -#define DDB0 0 -#define DDB1 1 -#define DDB2 2 -#define DDB3 3 -#define DDB4 4 -#define DDB5 5 -#define DDB6 6 -#define DDB7 7 - -#define PORTB _SFR_IO8(0x05) -#define PORTB0 0 -#define PORTB1 1 -#define PORTB2 2 -#define PORTB3 3 -#define PORTB4 4 -#define PORTB5 5 -#define PORTB6 6 -#define PORTB7 7 - -#define PINC _SFR_IO8(0x06) -#define PINC0 0 -#define PINC1 1 -#define PINC2 2 -#define PINC3 3 -#define PINC4 4 -#define PINC5 5 -#define PINC6 6 -#define PINC7 7 - -#define DDRC _SFR_IO8(0x07) -#define DDC0 0 -#define DDC1 1 -#define DDC2 2 -#define DDC3 3 -#define DDC4 4 -#define DDC5 5 -#define DDC6 6 -#define DDC7 7 - -#define PORTC _SFR_IO8(0x08) -#define PORTC0 0 -#define PORTC1 1 -#define PORTC2 2 -#define PORTC3 3 -#define PORTC4 4 -#define PORTC5 5 -#define PORTC6 6 -#define PORTC7 7 - -#define PIND _SFR_IO8(0x09) -#define PIND0 0 -#define PIND1 1 -#define PIND2 2 -#define PIND3 3 -#define PIND4 4 -#define PIND5 5 -#define PIND6 6 -#define PIND7 7 - -#define DDRD _SFR_IO8(0x0A) -#define DDD0 0 -#define DDD1 1 -#define DDD2 2 -#define DDD3 3 -#define DDD4 4 -#define DDD5 5 -#define DDD6 6 -#define DDD7 7 - -#define PORTD _SFR_IO8(0x0B) -#define PORTD0 0 -#define PORTD1 1 -#define PORTD2 2 -#define PORTD3 3 -#define PORTD4 4 -#define PORTD5 5 -#define PORTD6 6 -#define PORTD7 7 - -#define PINE _SFR_IO8(0x0C) -#define PINE0 0 -#define PINE1 1 -#define PINE2 2 - -#define DDRE _SFR_IO8(0x0D) -#define DDE0 0 -#define DDE1 1 -#define DDE2 2 - -#define PORTE _SFR_IO8(0x0E) -#define PORTE0 0 -#define PORTE1 1 -#define PORTE2 2 - -#define TIFR0 _SFR_IO8(0x15) -#define TOV0 0 -#define OCF0A 1 -#define OCF0B 2 - -#define TIFR1 _SFR_IO8(0x16) -#define TOV1 0 -#define OCF1A 1 -#define OCF1B 2 -#define ICF1 5 - -#define GPIOR1 _SFR_IO8(0x19) -#define GPIOR10 0 -#define GPIOR11 1 -#define GPIOR12 2 -#define GPIOR13 3 -#define GPIOR14 4 -#define GPIOR15 5 -#define GPIOR16 6 -#define GPIOR17 7 - -#define GPIOR2 _SFR_IO8(0x1A) -#define GPIOR20 0 -#define GPIOR21 1 -#define GPIOR22 2 -#define GPIOR23 3 -#define GPIOR24 4 -#define GPIOR25 5 -#define GPIOR26 6 -#define GPIOR27 7 - -#define GPIOR3 _SFR_IO8(0x1B) -#define GPIOR30 0 -#define GPIOR31 1 -#define GPIOR32 2 -#define GPIOR33 3 -#define GPIOR34 4 -#define GPIOR35 5 -#define GPIOR36 6 -#define GPIOR37 7 - -#define EIFR _SFR_IO8(0x1C) -#define INTF0 0 -#define INTF1 1 -#define INTF2 2 -#define INTF3 3 - -#define EIMSK _SFR_IO8(0x1D) -#define INT0 0 -#define INT1 1 -#define INT2 2 -#define INT3 3 - -#define GPIOR0 _SFR_IO8(0x1E) -#define GPIOR00 0 -#define GPIOR01 1 -#define GPIOR02 2 -#define GPIOR03 3 -#define GPIOR04 4 -#define GPIOR05 5 -#define GPIOR06 6 -#define GPIOR07 7 - -#define EECR _SFR_IO8(0x1F) -#define EERE 0 -#define EEWE 1 -#define EEMWE 2 -#define EERIE 3 -#define EEPM0 4 -#define EEPM1 5 - -#define EEDR _SFR_IO8(0x20) -#define EEDR0 0 -#define EEDR1 1 -#define EEDR2 2 -#define EEDR3 3 -#define EEDR4 4 -#define EEDR5 5 -#define EEDR6 6 -#define EEDR7 7 - -#define EEAR _SFR_IO16(0x21) - -#define EEARL _SFR_IO8(0x21) -#define EEARL0 0 -#define EEARL1 1 -#define EEARL2 2 -#define EEARL3 3 -#define EEARL4 4 -#define EEARL5 5 -#define EEARL6 6 -#define EEARL7 7 - -#define EEARH _SFR_IO8(0x22) -#define EEAR8 0 -#define EEAR9 1 -#define EEAR10 2 -#define EEAR11 3 - -#define GTCCR _SFR_IO8(0x23) -#define PSR10 0 -#define PSRSYNC 0 -#define ICPSEL1 2 -#define TSM 3 - -#define TCCR0A _SFR_IO8(0x24) -#define WGM00 0 -#define WGM01 1 -#define COM0B0 4 -#define COM0B1 5 -#define COM0A0 6 -#define COM0A1 7 - -#define TCCR0B _SFR_IO8(0x25) -#define CS00 0 -#define CS01 1 -#define CS02 2 -#define WGM02 3 -#define FOC0B 6 -#define FOC0A 7 - -#define TCNT0 _SFR_IO8(0x26) -#define TCNT0_0 0 -#define TCNT0_1 1 -#define TCNT0_2 2 -#define TCNT0_3 3 -#define TCNT0_4 4 -#define TCNT0_5 5 -#define TCNT0_6 6 -#define TCNT0_7 7 - -#define OCR0A _SFR_IO8(0x27) -#define OCR0A_0 0 -#define OCR0A_1 1 -#define OCR0A_2 2 -#define OCR0A_3 3 -#define OCR0A_4 4 -#define OCR0A_5 5 -#define OCR0A_6 6 -#define OCR0A_7 7 - -#define OCR0B _SFR_IO8(0x28) -#define OCR0B_0 0 -#define OCR0B_1 1 -#define OCR0B_2 2 -#define OCR0B_3 3 -#define OCR0B_4 4 -#define OCR0B_5 5 -#define OCR0B_6 6 -#define OCR0B_7 7 - -#define OCR0_0 0 /* Deprecated */ -#define OCR0_1 1 /* Deprecated */ -#define OCR0_2 2 /* Deprecated */ -#define OCR0_3 3 /* Deprecated */ -#define OCR0_4 4 /* Deprecated */ -#define OCR0_5 5 /* Deprecated */ -#define OCR0_6 6 /* Deprecated */ -#define OCR0_7 7 /* Deprecated */ - -#define PLLCSR _SFR_IO8(0x29) -#define PLOCK 0 -#define PLLE 1 -#define PLLF 2 - -#define SPCR _SFR_IO8(0x2C) -#define SPR0 0 -#define SPR1 1 -#define CPHA 2 -#define CPOL 3 -#define MSTR 4 -#define DORD 5 -#define SPE 6 -#define SPIE 7 - -#define SPSR _SFR_IO8(0x2D) -#define SPI2X 0 -#define WCOL 6 -#define SPIF 7 - -#define SPDR _SFR_IO8(0x2E) -#define SPDR0 0 -#define SPDR1 1 -#define SPDR2 2 -#define SPDR3 3 -#define SPDR4 4 -#define SPDR5 5 -#define SPDR6 6 -#define SPDR7 7 - -#define ACSR _SFR_IO8(0x30) -#define AC0O 0 -#define AC1O 1 -#define AC2O 2 -#define AC0IF 4 -#define AC1IF 5 -#define AC2IF 6 -#define ACCKDIV 7 - -#define SMCR _SFR_IO8(0x33) -#define SE 0 -#define SM0 1 -#define SM1 2 -#define SM2 3 - -#define MCUSR _SFR_IO8(0x34) -#define PORF 0 -#define EXTRF 1 -#define BORF 2 -#define WDRF 3 - -#define MCUCR _SFR_IO8(0x35) -#define IVCE 0 -#define IVSEL 1 -#define PUD 4 -#define SPIPS 7 - -#define SPMCSR _SFR_IO8(0x37) -#define SPMEN 0 -#define PGERS 1 -#define PGWRT 2 -#define BLBSET 3 -#define RWWSRE 4 -#define RWWSB 6 -#define SPMIE 7 - -#define WDTCSR _SFR_MEM8(0x60) -#define WDP0 0 -#define WDP1 1 -#define WDP2 2 -#define WDE 3 -#define WDCE 4 -#define WDP3 5 -#define WDIE 6 -#define WDIF 7 - -#define CLKPR _SFR_MEM8(0x61) -#define CLKPS0 0 -#define CLKPS1 1 -#define CLKPS2 2 -#define CLKPS3 3 -#define CLKPCE 7 - -#define PRR _SFR_MEM8(0x64) -#define PRADC 0 -#define PRUSART0 1 -#define PRSPI 2 -#define PRTIM0 3 -#define PRTIM1 4 -#define PRPSC0 5 -#define PRPSC1 6 -#define PRPSC2 7 - -#define __AVR_HAVE_PRR ((1<, never directly. */ - -#ifndef _AVR_IO_H_ -# error "Include instead of this file." -#endif - -#ifndef _AVR_IOXXX_H_ -# define _AVR_IOXXX_H_ "io90pwm81.h" -#else -# error "Attempt to include more than one file." -#endif - - -#ifndef _AVR_AT90PWM81_H_ -#define _AVR_AT90PWM81_H_ 1 - - -/* Registers and associated bit numbers. */ - -#define ACSR _SFR_IO8(0x00) -#define AC1O 1 -#define AC2O 2 -#define AC3O 3 -#define AC1IF 5 -#define AC2IF 6 -#define AC3IF 7 - -#define TIMSK1 _SFR_IO8(0x01) -#define TOIE1 0 -#define ICIE1 5 - -#define TIFR1 _SFR_IO8(0x02) -#define TOV1 0 -#define ICF1 5 - -#define PINB _SFR_IO8(0x03) -#define PINB0 0 -#define PINB1 1 -#define PINB2 2 -#define PINB3 3 -#define PINB4 4 -#define PINB5 5 -#define PINB6 6 -#define PINB7 7 - -#define DDRB _SFR_IO8(0x04) -#define DDB0 0 -#define DDB1 1 -#define DDB2 2 -#define DDB3 3 -#define DDB4 4 -#define DDB5 5 -#define DDB6 6 -#define DDB7 7 - -#define PORTB _SFR_IO8(0x05) -#define PORTB0 0 -#define PORTB1 1 -#define PORTB2 2 -#define PORTB3 3 -#define PORTB4 4 -#define PORTB5 5 -#define PORTB6 6 -#define PORTB7 7 - -#define ADCSRA _SFR_IO8(0x06) -#define ADPS0 0 -#define ADPS1 1 -#define ADPS2 2 -#define ADIE 3 -#define ADIF 4 -#define ADATE 5 -#define ADSC 6 -#define ADEN 7 - -#define ADCSRB _SFR_IO8(0x07) -#define ADTS0 0 -#define ADTS1 1 -#define ADTS2 2 -#define ADTS3 3 -#define ADSSEN 4 -#define ADNCDIS 6 -#define ADHSM 7 - -#define ADMUX _SFR_IO8(0x08) -#define MUX0 0 -#define MUX1 1 -#define MUX2 2 -#define MUX3 3 -#define ADLAR 5 -#define REFS0 6 -#define REFS1 7 - -#define PIND _SFR_IO8(0x09) -#define PIND0 0 -#define PIND1 1 -#define PIND2 2 -#define PIND3 3 -#define PIND4 4 -#define PIND5 5 -#define PIND6 6 -#define PIND7 7 - -#define DDRD _SFR_IO8(0x0A) -#define DDD0 0 -#define DDD1 1 -#define DDD2 2 -#define DDD3 3 -#define DDD4 4 -#define DDD5 5 -#define DDD6 6 -#define DDD7 7 - -#define PORTD _SFR_IO8(0x0B) -#define PORTD0 0 -#define PORTD1 1 -#define PORTD2 2 -#define PORTD3 3 -#define PORTD4 4 -#define PORTD5 5 -#define PORTD6 6 -#define PORTD7 7 - -#define PINE _SFR_IO8(0x0C) -#define PINE0 0 -#define PINE1 1 -#define PINE2 2 - -#define DDRE _SFR_IO8(0x0D) -#define DDE0 0 -#define DDE1 1 -#define DDE2 2 - -#define PORTE _SFR_IO8(0x0E) -#define PORTE0 0 -#define PORTE1 1 -#define PORTE2 2 - -#define PIM0 _SFR_IO8(0x0F) -#define PEOPE0 0 -#define PEOEPE0 1 -#define PEVE0A 3 -#define PEVE0B 4 - -#define PIFR0 _SFR_IO8(0x10) -#define PEOP0 0 -#define PRN00 1 -#define PRN01 2 -#define PEV0A 3 -#define PEV0B 4 -#define POAC0A 6 -#define POAC0B 7 - -#define PCNF0 _SFR_IO8(0x11) -#define PCLKSEL0 1 -#define POP0 2 -#define PMODE00 3 -#define PMODE01 4 -#define PLOCK0 5 -#define PALOCK0 6 -#define PFIFTY0 7 - -#define PCTL0 _SFR_IO8(0x12) -#define PRUN0 0 -#define PCCYC0 1 -#define PBFM00 2 -#define PAOC0A 3 -#define PAOC0B 4 -#define PBFM01 5 -#define PPRE00 6 -#define PPRE01 7 - -#define PIM2 _SFR_IO8(0x13) -#define PEOPE2 0 -#define PEOEPE2 1 -#define PEVE2A 3 -#define PEVE2B 4 -#define PSEIE2 5 - -#define PIFR2 _SFR_IO8(0x14) -#define PEOP2 0 -#define PRN20 1 -#define PRN21 2 -#define PEV2A 3 -#define PEV2B 4 -#define PSEI2 5 -#define POAC2A 6 -#define POAC2B 7 - -#define PCNF2 _SFR_IO8(0x15) -#define POME2 0 -#define PCLKSEL2 1 -#define POP2 2 -#define PMODE20 3 -#define PMODE21 4 -#define PLOCK2 5 -#define PALOCK2 6 -#define PFIFTY2 7 - -#define PCTL2 _SFR_IO8(0x16) -#define PRUN2 0 -#define PCCYC2 1 -#define PARUN2 2 -#define PAOC2A 3 -#define PAOC2B 4 -#define PBFM2 5 -#define PPRE20 6 -#define PPRE21 7 - -#define SPCR _SFR_IO8(0x17) -#define SPR0 0 -#define SPR1 1 -#define CPHA 2 -#define CPOL 3 -#define MSTR 4 -#define DORD 5 -#define SPE 6 -#define SPIE 7 - -#define SPSR _SFR_IO8(0x18) -#define SPI2X 0 -#define WCOL 6 -#define SPIF 7 - -#define GPIOR0 _SFR_IO8(0x19) -#define GPIOR00 0 -#define GPIOR01 1 -#define GPIOR02 2 -#define GPIOR03 3 -#define GPIOR04 4 -#define GPIOR05 5 -#define GPIOR06 6 -#define GPIOR07 7 - -#define GPIOR1 _SFR_IO8(0x1A) -#define GPIOR10 0 -#define GPIOR11 1 -#define GPIOR12 2 -#define GPIOR13 3 -#define GPIOR14 4 -#define GPIOR15 5 -#define GPIOR16 6 -#define GPIOR17 7 - -#define GPIOR2 _SFR_IO8(0x1B) -#define GPIOR20 0 -#define GPIOR21 1 -#define GPIOR22 2 -#define GPIOR23 3 -#define GPIOR24 4 -#define GPIOR25 5 -#define GPIOR26 6 -#define GPIOR27 7 - -#define EECR _SFR_IO8(0x1C) -#define EERE 0 -#define EEWE 1 -#define EEMWE 2 -#define EERIE 3 -#define EEPM0 4 -#define EEPM1 5 -#define EEPAGE 6 -#define NVMBSY 7 - -#define EEDR _SFR_IO8(0x1D) -#define EEDR0 0 -#define EEDR1 1 -#define EEDR2 2 -#define EEDR3 3 -#define EEDR4 4 -#define EEDR5 5 -#define EEDR6 6 -#define EEDR7 7 - -#define EEAR _SFR_IO16(0x1E) - -#define EEARL _SFR_IO8(0x1E) -#define EEARL0 0 -#define EEARL1 1 -#define EEARL2 2 -#define EEARL3 3 -#define EEARL4 4 -#define EEARL5 5 -#define EEARL6 6 -#define EEARL7 7 - -#define EEARH _SFR_IO8(0x1F) -#define EEAR8 0 - -#define EIFR _SFR_IO8(0x20) -#define INTF0 0 -#define INTF1 1 -#define INTF2 2 - -#define EIMSK _SFR_IO8(0x21) -#define INT0 0 -#define INT1 1 -#define INT2 2 - -#define OCR0SB _SFR_IO16(0x22) - -#define OCR0SBL _SFR_IO8(0x22) -#define OCR0SB_0 0 -#define OCR0SB_1 1 -#define OCR0SB_2 2 -#define OCR0SB_3 3 -#define OCR0SB_4 4 -#define OCR0SB_5 5 -#define OCR0SB_6 6 -#define OCR0SB_7 7 - -#define OCR0SBH _SFR_IO8(0x23) -#define OCR0SB_8 0 -#define OCR0SB_9 1 -#define OCR0SB_00 2 -#define OCR0SB_01 3 - -#define OCR0RB _SFR_IO16(0x24) - -#define OCR0RBL _SFR_IO8(0x24) -#define OCR0RB_0 0 -#define OCR0RB_1 1 -#define OCR0RB_2 2 -#define OCR0RB_3 3 -#define OCR0RB_4 4 -#define OCR0RB_5 5 -#define OCR0RB_6 6 -#define OCR0RB_7 7 - -#define OCR0RBH _SFR_IO8(0x25) -#define OCR0RB_8 0 -#define OCR0RB_9 1 -#define OCR0RB_00 2 -#define OCR0RB_01 3 -#define OCR0RB_02 4 -#define OCR0RB_03 5 -#define OCR0RB_04 6 -#define OCR0RB_05 7 - -#define OCR2SB _SFR_IO16(0x26) - -#define OCR2SBL _SFR_IO8(0x26) -#define OCR2SB_0 0 -#define OCR2SB_1 1 -#define OCR2SB_2 2 -#define OCR2SB_3 3 -#define OCR2SB_4 4 -#define OCR2SB_5 5 -#define OCR2SB_6 6 -#define OCR2SB_7 7 - -#define OCR2SBH _SFR_IO8(0x27) -#define OCR2SB_8 0 -#define OCR2SB_9 1 -#define OCR2SB_10 2 -#define OCR2SB_11 3 - -#define OCR2RB _SFR_IO16(0x28) - -#define OCR2RBL _SFR_IO8(0x28) -#define OCR2RB_0 0 -#define OCR2RB_1 1 -#define OCR2RB_2 2 -#define OCR2RB_3 3 -#define OCR2RB_4 4 -#define OCR2RB_5 5 -#define OCR2RB_6 6 -#define OCR2RB_7 7 - -#define OCR2RBH _SFR_IO8(0x29) -#define OCR2RB_8 0 -#define OCR2RB_9 1 -#define OCR2RB_10 2 -#define OCR2RB_11 3 -#define OCR2RB_12 4 -#define OCR2RB_13 5 -#define OCR2RB_14 6 -#define OCR2RB_15 7 - -#define OCR0RA _SFR_IO16(0x2A) - -#define OCR0RAL _SFR_IO8(0x2A) -#define OCR0RA_0 0 -#define OCR0RA_1 1 -#define OCR0RA_2 2 -#define OCR0RA_3 3 -#define OCR0RA_4 4 -#define OCR0RA_5 5 -#define OCR0RA_6 6 -#define OCR0RA_7 7 - -#define OCR0RAH _SFR_IO8(0x2B) -#define OCR0RA_8 0 -#define OCR0RA_9 1 -#define OCR0RA_00 2 -#define OCR0RA_01 3 - -#ifndef __ASSEMBLER__ -#define ADC _SFR_IO16(0x2C) -#endif -#define ADCW _SFR_IO16(0x2C) - -#define ADCL _SFR_IO8(0x2C) -#define ADCL0 0 -#define ADCL1 1 -#define ADCL2 2 -#define ADCL3 3 -#define ADCL4 4 -#define ADCL5 5 -#define ADCL6 6 -#define ADCL7 7 - -#define ADCH _SFR_IO8(0x2D) -#define ADCH0 0 -#define ADCH1 1 -#define ADCH2 2 -#define ADCH3 3 -#define ADCH4 4 -#define ADCH5 5 -#define ADCH6 6 -#define ADCH7 7 - -#define OCR2RA _SFR_IO16(0x2E) - -#define OCR2RAL _SFR_IO8(0x2E) -#define OCR2RA_0 0 -#define OCR2RA_1 1 -#define OCR2RA_2 2 -#define OCR2RA_3 3 -#define OCR2RA_4 4 -#define OCR2RA_5 5 -#define OCR2RA_6 6 -#define OCR2RA_7 7 - -#define OCR2RAH _SFR_IO8(0x2F) -#define OCR2RA_8 0 -#define OCR2RA_9 1 -#define OCR2RA_10 2 -#define OCR2RA_11 3 - -#define DWDR _SFR_IO8(0x31) - -#define MSMCR _SFR_IO8(0x32) - -#define SMCR _SFR_IO8(0x33) -#define SE 0 -#define SM0 1 -#define SM1 2 -#define SM2 3 - -#define MCUSR _SFR_IO8(0x34) -#define PORF 0 -#define EXTRF 1 -#define BORF 2 -#define WDRF 3 - -#define MCUCR _SFR_IO8(0x35) -#define IVCE 0 -#define IVSEL 1 -#define CKRC81 2 -#define RSTDIS 3 -#define PUD 4 - -#define SPDR _SFR_IO8(0x36) -#define SPDR0 0 -#define SPDR1 1 -#define SPDR2 2 -#define SPDR3 3 -#define SPDR4 4 -#define SPDR5 5 -#define SPDR6 6 -#define SPDR7 7 - -#define SPMCSR _SFR_IO8(0x37) -#define SPMEN 0 -#define PGERS 1 -#define PGWRT 2 -#define BLBSET 3 -#define RWWSRE 4 -#define SIGRD 5 -#define RWWSB 6 -#define SPMIE 7 - -#define DAC _SFR_IO16(0x38) - -#define DACL _SFR_IO8(0x38) -#define DACL0 0 -#define DACL1 1 -#define DACL2 2 -#define DACL3 3 -#define DACL4 4 -#define DACL5 5 -#define DACL6 6 -#define DACL7 7 - -#define DACH _SFR_IO8(0x39) -#define DACH0 0 -#define DACH1 1 -#define DACH2 2 -#define DACH3 3 -#define DACH4 4 -#define DACH5 5 -#define DACH6 6 -#define DACH7 7 - -#define TCNT1 _SFR_IO16(0x3A) - -#define TCNT1L _SFR_IO8(0x3A) -#define TCNT1L0 0 -#define TCNT1L1 1 -#define TCNT1L2 2 -#define TCNT1L3 3 -#define TCNT1L4 4 -#define TCNT1L5 5 -#define TCNT1L6 6 -#define TCNT1L7 7 - -#define TCNT1H _SFR_IO8(0x3B) -#define TCNT1H0 0 -#define TCNT1H1 1 -#define TCNT1H2 2 -#define TCNT1H3 3 -#define TCNT1H4 4 -#define TCNT1H5 5 -#define TCNT1H6 6 -#define TCNT1H7 7 - -#define OCR0SA _SFR_MEM16(0x60) - -#define OCR0SAL _SFR_MEM8(0x60) -#define OCR0SA_0 0 -#define OCR0SA_1 1 -#define OCR0SA_2 2 -#define OCR0SA_3 3 -#define OCR0SA_4 4 -#define OCR0SA_5 5 -#define OCR0SA_6 6 -#define OCR0SA_7 7 - -#define OCR0SAH _SFR_MEM8(0x61) -#define OCR0SA_8 0 -#define OCR0SA_9 1 -#define OCR0SA_00 2 -#define OCR0SA_01 3 - -#define PFRC0A _SFR_MEM8(0x62) -#define PRFM0A0 0 -#define PRFM0A1 1 -#define PRFM0A2 2 -#define PRFM0A3 3 -#define PFLTE0A 4 -#define PELEV0A 5 -#define PISEL0A 6 -#define PCAE0A 7 - -#define PFRC0B _SFR_MEM8(0x63) -#define PRFM0B0 0 -#define PRFM0B1 1 -#define PRFM0B2 2 -#define PRFM0B3 3 -#define PFLTE0B 4 -#define PELEV0B 5 -#define PISEL0B 6 -#define PCAE0B 7 - -#define OCR2SA _SFR_MEM16(0x64) - -#define OCR2SAL _SFR_MEM8(0x64) -#define OCR2SA_0 0 -#define OCR2SA_1 1 -#define OCR2SA_2 2 -#define OCR2SA_3 3 -#define OCR2SA_4 4 -#define OCR2SA_5 5 -#define OCR2SA_6 6 -#define OCR2SA_7 7 - -#define OCR2SAH _SFR_MEM8(0x65) -#define OCR2SA_8 0 -#define OCR2SA_9 1 -#define OCR2SA_10 2 -#define OCR2SA_11 3 - -#define PFRC2A _SFR_MEM8(0x66) -#define PRFM2A0 0 -#define PRFM2A1 1 -#define PRFM2A2 2 -#define PRFM2A3 3 -#define PFLTE2A 4 -#define PELEV2A 5 -#define PISEL2A 6 -#define PCAE2A 7 - -#define PFRC2B _SFR_MEM8(0x67) -#define PRFM2B0 0 -#define PRFM2B1 1 -#define PRFM2B2 2 -#define PRFM2B3 3 -#define PFLTE2B 4 -#define PELEV2B 5 -#define PISEL2B 6 -#define PCAE2B 7 - -#define PICR0 _SFR_MEM16(0x68) - -#define PICR0L _SFR_MEM8(0x68) -#define PICR0_0 0 -#define PICR0_1 1 -#define PICR0_2 2 -#define PICR0_3 3 -#define PICR0_4 4 -#define PICR0_5 5 -#define PICR0_6 6 -#define PICR0_7 7 - -#define PICR0H _SFR_MEM8(0x69) -#define PICR0_8 0 -#define PICR0_9 1 -#define PICR0_10 2 -#define PICR0_11 3 -#define PCST0 7 - -#define PSOC0 _SFR_MEM8(0x6A) -#define POEN0A 0 -#define POEN0B 2 -#define PSYNC00 4 -#define PSYNC01 5 -#define PISEL0B1 6 -#define PISEL0A1 7 - -#define PICR2 _SFR_MEM16(0x6C) - -#define PICR2L _SFR_MEM8(0x6C) -#define PICR2_0 0 -#define PICR2_1 1 -#define PICR2_2 2 -#define PICR2_3 3 -#define PICR2_4 4 -#define PICR2_5 5 -#define PICR2_6 6 -#define PICR2_7 7 - -#define PICR2H _SFR_MEM8(0x6D) -#define PICR2_8 0 -#define PICR2_9 1 -#define PICR2_10 2 -#define PICR2_11 3 -#define PCST2 7 - -#define PSOC2 _SFR_MEM8(0x6E) -#define POEN2A 0 -#define POEN2C 1 -#define POEN2B 2 -#define POEN2D 3 -#define PSYNC2_0 4 -#define PSYNC2_1 5 -#define POS22 6 -#define POS23 7 - -#define POM2 _SFR_MEM8(0x6F) -#define POMV2A0 0 -#define POMV2A1 1 -#define POMV2A2 2 -#define POMV2A3 3 -#define POMV2B0 4 -#define POMV2B1 5 -#define POMV2B2 6 -#define POMV2B3 7 - -#define PCNFE2 _SFR_MEM8(0x70) -#define PISEL2B1 0 -#define PISEL2A1 1 -#define PELEV2B1 2 -#define PELEV2A1 3 -#define PBFM21 4 -#define PASDLK20 5 -#define PASDLK21 6 -#define PASDLK22 7 - -#define PASDLY2 _SFR_MEM8(0x71) -#define PASDLY2_0 0 -#define PASDLY2_1 1 -#define PASDLY2_2 2 -#define PASDLY2_3 3 -#define PASDLY2_4 4 -#define PASDLY2_5 5 -#define PASDLY2_6 6 -#define PASDLY2_7 7 - -#define DACON _SFR_MEM8(0x76) -#define DAEN 0 -#define DALA 2 -#define DATS0 4 -#define DATS1 5 -#define DATS2 6 -#define DAATE 7 - -#define DIDR0 _SFR_MEM8(0x77) -#define ADC0D 0 -#define ADC1D 1 -#define ADC2D 2 -#define ADC3D 3 -#define ADC4D 4 -#define ADC5D 5 -#define ADC7D 6 -#define ADC8D 7 - -#define DIDR1 _SFR_MEM8(0x78) -#define ADC9D 0 -#define ADC10D 1 -#define AMP0PD 2 -#define ACMP1MD 3 - -#define AMP0CSR _SFR_MEM8(0x79) -#define AMP0TS0 0 -#define AMP0TS1 1 -#define AMP0GS 3 -#define AMP0G0 4 -#define AMP0G1 5 -#define AMP0IS 6 -#define AMP0EN 7 - -#define AC1ECON _SFR_MEM8(0x7A) -#define AC1H0 0 -#define AC1H1 1 -#define AC1H2 2 -#define AC1ICE 3 -#define AC1OE 4 -#define AC1OI 5 - -#define AC2ECON _SFR_MEM8(0x7B) -#define AC2H0 0 -#define AC2H1 1 -#define AC2H2 2 -#define AC2OE 4 -#define AC2OI 5 - -#define AC3ECON _SFR_MEM8(0x7C) -#define AC3H0 0 -#define AC3H1 1 -#define AC3H2 2 -#define AC3OE 4 -#define AC3OI 5 - -#define AC1CON _SFR_MEM8(0x7D) -#define AC1M0 0 -#define AC1M1 1 -#define AC1M2 2 -#define AC1IS0 4 -#define AC1IS1 5 -#define AC1IE 6 -#define AC1EN 7 - -#define AC2CON _SFR_MEM8(0x7E) -#define AC2M0 0 -#define AC2M1 1 -#define AC2M2 2 -#define AC2IS0 4 -#define AC2IS1 5 -#define AC2IE 6 -#define AC2EN 7 - -#define AC3CON _SFR_MEM8(0x7F) -#define AC3M0 0 -#define AC3M1 1 -#define AC3M2 2 -#define AC3OEA 3 -#define AC3IS0 4 -#define AC3IS1 5 -#define AC3IE 6 -#define AC3EN 7 - -#define BGCRR _SFR_MEM8(0x80) -#define BGCR0 0 -#define BGCR1 1 -#define BGCR2 2 -#define BGCR3 3 - -#define BGCCR _SFR_MEM8(0x81) -#define BGCC0 0 -#define BGCC1 1 -#define BGCC2 2 -#define BGCC3 3 - -#define WDTCSR _SFR_MEM8(0x82) -#define WDP0 0 -#define WDP1 1 -#define WDP2 2 -#define WDE 3 -#define WDCE 4 -#define WDP3 5 -#define WDIE 6 -#define WDIF 7 - -#define CLKPR _SFR_MEM8(0x83) -#define CLKPS0 0 -#define CLKPS1 1 -#define CLKPS2 2 -#define CLKPS3 3 -#define CLKPCE 7 - -#define CLKCSR _SFR_MEM8(0x84) -#define CLKC0 0 -#define CLKC1 1 -#define CLKC2 2 -#define CLKC3 3 -#define CLKRDY 4 -#define CLKCCE 7 - -#define CLKSELR _SFR_MEM8(0x85) -#define CKSEL0 0 -#define CKSEL1 1 -#define CKSEL2 2 -#define CKSEL3 3 -#define CSUT0 4 -#define CSUT1 5 -#define COUT 6 - -#define PRR _SFR_MEM8(0x86) -#define PRADC 0 -#define PRSPI 2 -#define PRTIM1 4 -#define PRPSCR 5 -#define PRPSC2 7 - -#define __AVR_HAVE_PRR ((1<, never directly. */ - -#ifndef _AVR_IO_H_ -# error "Include instead of this file." -#endif - -#ifndef _AVR_IOXXX_H_ -# define _AVR_IOXXX_H_ "io90pwmX.h" -#else -# error "Attempt to include more than one file." -#endif - -/* I/O registers */ - -/* Port B Input Pins Address */ -#define PINB _SFR_IO8(0x03) -/* PINB */ -#define PINB7 7 -#define PINB6 6 -#define PINB5 5 -#define PINB4 4 -#define PINB3 3 -#define PINB2 2 -#define PINB1 1 -#define PINB0 0 - -/* Port B Data Direction Register */ -#define DDRB _SFR_IO8(0x04) -/* DDRB */ -#define DDB7 7 -#define DDB6 6 -#define DDB5 5 -#define DDB4 4 -#define DDB3 3 -#define DDB2 2 -#define DDB1 1 -#define DDB0 0 - -/* Port B Data Register */ -#define PORTB _SFR_IO8(0x05) -/* PORTB */ -#define PB7 7 -#define PB6 6 -#define PB5 5 -#define PB4 4 -#define PB3 3 -#define PB2 2 -#define PB1 1 -#define PB0 0 - -/* Port C Input Pins Address */ -#define PINC _SFR_IO8(0x06) -/* PINC */ -#define PINC7 7 -#define PINC6 6 -#define PINC5 5 -#define PINC4 4 -#define PINC3 3 -#define PINC2 2 -#define PINC1 1 -#define PINC0 0 - -/* Port C Data Direction Register */ -#define DDRC _SFR_IO8(0x07) -/* DDRC */ -#define DDC7 7 -#define DDC6 6 -#define DDC5 5 -#define DDC4 4 -#define DDC3 3 -#define DDC2 2 -#define DDC1 1 -#define DDC0 0 - -/* Port C Data Register */ -#define PORTC _SFR_IO8(0x08) -/* PORTC */ -#define PC7 7 -#define PC6 6 -#define PC5 5 -#define PC4 4 -#define PC3 3 -#define PC2 2 -#define PC1 1 -#define PC0 0 - -/* Port D Input Pins Address */ -#define PIND _SFR_IO8(0x09) -/* PIND */ -#define PIND7 7 -#define PIND6 6 -#define PIND5 5 -#define PIND4 4 -#define PIND3 3 -#define PIND2 2 -#define PIND1 1 -#define PIND0 0 - -/* Port D Data Direction Register */ -#define DDRD _SFR_IO8(0x0A) -/* DDRD */ -#define DDD7 7 -#define DDD6 6 -#define DDD5 5 -#define DDD4 4 -#define DDD3 3 -#define DDD2 2 -#define DDD1 1 -#define DDD0 0 - -/* Port D Data Register */ -#define PORTD _SFR_IO8(0x0B) -/* PORTD */ -#define PD7 7 -#define PD6 6 -#define PD5 5 -#define PD4 4 -#define PD3 3 -#define PD2 2 -#define PD1 1 -#define PD0 0 - -/* Port E Input Pins Address */ -#define PINE _SFR_IO8(0x0C) -/* PINE */ -#define PINE2 2 -#define PINE1 1 -#define PINE0 0 - -/* Port E Data Direction Register */ -#define DDRE _SFR_IO8(0x0D) -/* DDRE */ -#define DDE2 2 -#define DDE1 1 -#define DDE0 0 - -/* Port E Data Register */ -#define PORTE _SFR_IO8(0x0E) -/* PORTE */ -#define PE2 2 -#define PE1 1 -#define PE0 0 - -/* Timer/Counter 0 Interrupt Flag Register */ -#define TIFR0 _SFR_IO8(0x15) -/* TIFR0 */ -#define OCF0B 2 /* Output Compare Flag 0B */ -#define OCF0A 1 /* Output Compare Flag 0A */ -#define TOV0 0 /* Overflow Flag */ - -/* Timer/Counter1 Interrupt Flag Register */ -#define TIFR1 _SFR_IO8(0x16) -/* TIFR1 */ -#define ICF1 5 /* Input Capture Flag 1 */ -#define OCF1B 2 /* Output Compare Flag 1B*/ -#define OCF1A 1 /* Output Compare Flag 1A*/ -#define TOV1 0 /* Overflow Flag */ - -/* General Purpose I/O Register 1 */ -#define GPIOR1 _SFR_IO8(0x19) -/* GPIOR1 */ -#define GPIOR17 7 -#define GPIOR16 6 -#define GPIOR15 5 -#define GPIOR14 4 -#define GPIOR13 3 -#define GPIOR12 2 -#define GPIOR11 1 -#define GPIOR10 0 - -/* General Purpose I/O Register 2 */ -#define GPIOR2 _SFR_IO8(0x1A) -/* GPIOR2 */ -#define GPIOR27 7 -#define GPIOR26 6 -#define GPIOR25 5 -#define GPIOR24 4 -#define GPIOR23 3 -#define GPIOR22 2 -#define GPIOR21 1 -#define GPIOR20 0 - -/* General Purpose I/O Register 3 */ -#define GPIOR3 _SFR_IO8(0x1B) -/* GPIOR3 */ -#define GPIOR37 7 -#define GPIOR36 6 -#define GPIOR35 5 -#define GPIOR34 4 -#define GPIOR33 3 -#define GPIOR32 2 -#define GPIOR31 1 -#define GPIOR30 0 - -/* External Interrupt Flag Register */ -#define EIFR _SFR_IO8(0x1C) -/* EIFR */ -#define INTF3 3 -#define INTF2 2 -#define INTF1 1 -#define INTF0 0 - -/* External Interrupt Mask Register */ -#define EIMSK _SFR_IO8(0x1D) -/* EIMSK */ -#define INT3 3 /* External Interrupt Request 3 Enable */ -#define INT2 2 /* External Interrupt Request 2 Enable */ -#define INT1 1 /* External Interrupt Request 1 Enable */ -#define INT0 0 /* External Interrupt Request 0 Enable */ - -/* General Purpose I/O Register 0 */ -#define GPIOR0 _SFR_IO8(0x1E) -/* GPIOR0 */ -#define GPIOR07 7 -#define GPIOR06 6 -#define GPIOR05 5 -#define GPIOR04 4 -#define GPIOR03 3 -#define GPIOR02 2 -#define GPIOR01 1 -#define GPIOR00 0 - -/* EEPROM Control Register */ -#define EECR _SFR_IO8(0x1F) -/* EECR */ -#define EERIE 3 /* EEPROM Ready Interrupt Enable */ -#define EEMWE 2 /* EEPROM Master Write Enable */ -#define EEWE 1 /* EEPROM Write Enable */ -#define EERE 0 /* EEPROM Read Enable */ - -/* EEPROM Data Register */ -#define EEDR _SFR_IO8(0x20) -/* EEDR */ -#define EEDR7 7 -#define EEDR6 6 -#define EEDR5 5 -#define EEDR4 4 -#define EEDR3 3 -#define EEDR2 2 -#define EEDR1 1 -#define EEDR0 0 - -/* The EEPROM Address Registers */ -#define EEAR _SFR_IO16(0x21) -#define EEARL _SFR_IO8(0x21) -#define EEARH _SFR_IO8(0x22) -/* EEARH */ -#define EEAR11 3 -#define EEAR10 2 -#define EEAR9 1 -#define EEAR8 0 -/* EEARL */ -#define EEAR7 7 -#define EEAR6 6 -#define EEAR5 5 -#define EEAR4 4 -#define EEAR3 3 -#define EEAR2 2 -#define EEAR1 1 -#define EEAR0 0 - -/* 6-char sequence denoting where to find the EEPROM registers in memory space. - Adresses denoted in hex syntax with uppercase letters. Used by the EEPROM - subroutines. - First two letters: EECR address. - Second two letters: EEDR address. - Last two letters: EEAR address. */ -#define __EEPROM_REG_LOCATIONS__ 1F2021 - -/* General Timer/Counter Control Register */ -#define GTCCR _SFR_IO8(0x23) -/* GTCCR */ -#define TSM 7 /* Timer/Counter Synchronization Mode */ -#define ICPSEL1 6 /* Timer1 Input Capture Selection Bit */ -#define PSR10 0 /* Prescaler Reset Timer/Counter1 and Timer/Counter0 */ - -/* Timer/Counter Control Register A */ -#define TCCR0A _SFR_IO8(0x24) -/* TCCR0A */ -#define COM0A1 7 /* Compare Output Mode, Phase Correct PWM Mode */ -#define COM0A0 6 /* Compare Output Mode, Phase Correct PWM Mode */ -#define COM0B1 5 /* Compare Output Mode, Fast PWm */ -#define COM0B0 4 /* Compare Output Mode, Fast PWm */ -#define WGM01 1 /* Waveform Generation Mode */ -#define WGM00 0 /* Waveform Generation Mode */ - -/* Timer/Counter Control Register B */ -#define TCCR0B _SFR_IO8(0x25) -/* TCCR0B */ -#define FOC0A 7 /* Force Output Compare A */ -#define FOC0B 6 /* Force Output Compare B */ -#define WGM02 3 /* Waveform Generation Mode */ -#define CS02 2 /* Clock Select */ -#define CS01 1 /* Clock Select */ -#define CS00 0 /* Clock Select */ - -/* Timer/Counter0 Register */ -#define TCNT0 _SFR_IO8(0x26) -/* TCNT0 */ -#define TCNT07 7 -#define TCNT06 6 -#define TCNT05 5 -#define TCNT04 4 -#define TCNT03 3 -#define TCNT02 2 -#define TCNT01 1 -#define TCNT00 0 - -/* Timer/Counter0 Output Compare Register A */ -#define OCR0A _SFR_IO8(0x27) -/* OCR0A */ -#define OCR0A7 7 -#define OCR0A6 6 -#define OCR0A5 5 -#define OCR0A4 4 -#define OCR0A3 3 -#define OCR0A2 2 -#define OCR0A1 1 -#define OCR0A0 0 - -/* Timer/Counter0 Output Compare Register B */ -#define OCR0B _SFR_IO8(0x28) -/* OCR0B */ -#define OCR0B7 7 -#define OCR0B6 6 -#define OCR0B5 5 -#define OCR0B4 4 -#define OCR0B3 3 -#define OCR0B2 2 -#define OCR0B1 1 -#define OCR0B0 0 - -/* PLL Control and Status Register */ -#define PLLCSR _SFR_IO8(0x29) -/* PLLCSR */ -#define PCKE 2 /* PCK Enable */ -/* Bit 2 has been renamed in later versions of the datasheet. */ -#define PLLF 2 /* PLL Factor */ -#define PLLE 1 /* PLL Enable */ -#define PLOCK 0 /* PLL Lock Detector */ - -/* SPI Control Register */ -#define SPCR _SFR_IO8(0x2C) -/* SPCR */ -#define SPIE 7 /* SPI Interrupt Enable */ -#define SPE 6 /* SPI Enable */ -#define DORD 5 /* Data Order */ -#define MSTR 4 /* Master/Slave Select */ -#define CPOL 3 /* Clock polarity */ -#define CPHA 2 /* Clock Phase */ -#define SPR1 1 /* SPI Clock Rate Select 1 */ -#define SPR0 0 /* SPI Clock Rate Select 0 */ - -/* SPI Status Register */ -#define SPSR _SFR_IO8(0x2D) -/* SPSR */ -#define SPIF 7 /* SPI Interrupt Flag */ -#define WCOL 6 /* Write Collision Flag */ -#define SPI2X 0 /* Double SPI Speed Bit */ - -/* SPI Data Register */ -#define SPDR _SFR_IO8(0x2E) -/* SPDR */ -#define SPD7 7 -#define SPD6 6 -#define SPD5 5 -#define SPD4 4 -#define SPD3 3 -#define SPD2 2 -#define SPD1 1 -#define SPD0 0 - -/* Analog Comparator Status Register */ -#define ACSR _SFR_IO8(0x30) -/* ACSR */ -#define ACCKDIV 7 /* Analog Comparator Clock Divider */ -#define AC2IF 6 /* Analog Comparator 2 Interrupt Flag Bit */ -#define AC1IF 5 /* Analog Comparator 1 Interrupt Flag Bit */ -#define AC0IF 4 /* Analog Comparator 0 Interrupt Flag Bit */ -#define AC2O 2 /* Analog Comparator 2 Output Bit */ -#define AC1O 1 /* Analog Comparator 1 Output Bit */ -#define AC0O 0 /* Analog Comparator 0 Output Bit */ - -/* Monitor Data Register */ -#define MONDR _SFR_IO8(0x31) - -/* Monitor Stop Mode Control Register */ -#define MSMCR _SFR_IO8(0x32) - -/* Sleep Mode Control Register */ -#define SMCR _SFR_IO8(0x33) -/* SMCR */ -#define SM2 3 /* Sleep Mode Select bit2 */ -#define SM1 2 /* Sleep Mode Select bit1 */ -#define SM0 1 /* Sleep Mode Select bit0 */ -#define SE 0 /* Sleep Enable */ - -/* MCU Status Register */ -#define MCUSR _SFR_IO8(0x34) -/* MCUSR */ -#define WDRF 3 /* Watchdog Reset Flag */ -#define BORF 2 /* Brown-out Reset Flag */ -#define EXTRF 1 /* External Reset Flag */ -#define PORF 0 /* Power-on reset flag */ - -/* MCU Control Register */ -#define MCUCR _SFR_IO8(0x35) -/* MCUCR */ -#define SPIPS 7 /* SPI Pin Select */ -#define PUD 4 /* Pull-up disable */ -#define IVSEL 1 /* Interrupt Vector Select */ -#define IVCE 0 /* Interrupt Vector Change Enable */ - -/* Store Program Memory Control Register */ -#define SPMCSR _SFR_IO8(0x37) -/* SPMCSR */ -#define SPMIE 7 /* SPM Interrupt Enable */ -#define RWWSB 6 /* Read While Write Section Busy */ -#define RWWSRE 4 /* Read While Write section read enable */ -#define BLBSET 3 /* Boot Lock Bit Set */ -#define PGWRT 2 /* Page Write */ -#define PGERS 1 /* Page Erase */ -#define SPMEN 0 /* Store Program Memory Enable */ - -/* 0x3D..0x3E SP [defined in ] */ -/* 0x3F SREG [defined in ] */ - -/* Watchdog Timer Control Register */ -#define WDTCSR _SFR_MEM8(0x60) -/* WDTCSR */ -#define WDIF 7 /* Watchdog Timeout Interrupt Flag */ -#define WDIE 6 /* Watchdog Timeout Interrupt Enable */ -#define WDP3 5 /* Watchdog Timer Prescaler bit3 */ -#define WDCE 4 /* Watchdog Change Enable */ -#define WDE 3 /* Watchdog Enable */ -#define WDP2 2 /* Watchdog Timer Prescaler bit2 */ -#define WDP1 1 /* Watchdog Timer Prescaler bit1 */ -#define WDP0 0 /* Watchdog Timer Prescaler bit0 */ - -/* Clock Prescaler Register */ -#define CLKPR _SFR_MEM8(0x61) -/* CLKPR */ -#define CLKPCE 7 /* Clock Prescaler Change Enable */ -#define CLKPS3 3 /* Clock Prescaler Select bit3 */ -#define CLKPS2 2 /* Clock Prescaler Select bit2 */ -#define CLKPS1 1 /* Clock Prescaler Select bit1 */ -#define CLKPS0 0 /* Clock Prescaler Select bit0 */ - -/* Power Reduction Register */ -#define PRR _SFR_MEM8(0x64) -/* PRR */ -#define PRPSC2 7 /* Power Reduction PSC2 */ -#define PRPSC1 6 /* Power Reduction PSC1 */ -#define PRPSC0 5 /* Power Reduction PSC0 */ -#define PRTIM1 4 /* Power Reduction Timer/Counter1 */ -#define PRTIM0 3 /* Power Reduction Timer/Counter0 */ -#define PRSPI 2 /* Power Reduction Serial Peripheral Interface */ -#define PRUSART0 1 /* Power Reduction USART */ -#define PRUSART PRUSART0 /* Define to maintain backward-compatibility */ -#define PRADC 0 /* Power Reduction ADC */ - -#define __AVR_HAVE_PRR ((1<, never directly. */ - -#ifndef _AVR_IO_H_ -# error "Include instead of this file." -#endif - -#ifndef _AVR_IOXXX_H_ -# define _AVR_IOXXX_H_ "io90scr100.h" -#else -# error "Attempt to include more than one file." -#endif - - -#ifndef _AVR_AT90SCR100_H_ -#define _AVR_AT90SCR100_H_ 1 - - -/* Registers and associated bit numbers. */ - -#define PINA _SFR_IO8(0x00) -#define PINA0 0 -#define PINA1 1 -#define PINA2 2 -#define PINA3 3 -#define PINA4 4 -#define PINA5 5 -#define PINA6 6 -#define PINA7 7 - -#define DDRA _SFR_IO8(0x01) -#define DDA0 0 -#define DDA1 1 -#define DDA2 2 -#define DDA3 3 -#define DDA4 4 -#define DDA5 5 -#define DDA6 6 -#define DDA7 7 - -#define PORTA _SFR_IO8(0x02) -#define PORTA0 0 -#define PORTA1 1 -#define PORTA2 2 -#define PORTA3 3 -#define PORTA4 4 -#define PORTA5 5 -#define PORTA6 6 -#define PORTA7 7 - -#define PINB _SFR_IO8(0x03) -#define PINB0 0 -#define PINB1 1 -#define PINB2 2 -#define PINB3 3 -#define PINB4 4 -#define PINB5 5 -#define PINB6 6 -#define PINB7 7 - -#define DDRB _SFR_IO8(0x04) -#define DDB0 0 -#define DDB1 1 -#define DDB2 2 -#define DDB3 3 -#define DDB4 4 -#define DDB5 5 -#define DDB6 6 -#define DDB7 7 - -#define PORTB _SFR_IO8(0x05) -#define PORTB0 0 -#define PORTB1 1 -#define PORTB2 2 -#define PORTB3 3 -#define PORTB4 4 -#define PORTB5 5 -#define PORTB6 6 -#define PORTB7 7 - -#define PINC _SFR_IO8(0x06) -#define PINC0 0 -#define PINC1 1 -#define PINC2 2 -#define PINC3 3 -#define PINC4 4 -#define PINC5 5 -#define PINC6 6 -#define PINC7 7 - -#define DDRC _SFR_IO8(0x07) -#define DDC0 0 -#define DDC1 1 -#define DDC2 2 -#define DDC3 3 -#define DDC4 4 -#define DDC5 5 -#define DDC6 6 -#define DDC7 7 - -#define PORTC _SFR_IO8(0x08) -#define PORTC0 0 -#define PORTC1 1 -#define PORTC2 2 -#define PORTC3 3 -#define PORTC4 4 -#define PORTC5 5 -#define PORTC6 6 -#define PORTC7 7 - -#define PIND _SFR_IO8(0x09) -#define PIND0 0 -#define PIND1 1 -#define PIND2 2 -#define PIND3 3 -#define PIND4 4 -#define PIND5 5 -#define PIND6 6 -#define PIND7 7 - -#define DDRD _SFR_IO8(0x0A) -#define DDD0 0 -#define DDD1 1 -#define DDD2 2 -#define DDD3 3 -#define DDD4 4 -#define DDD5 5 -#define DDD6 6 -#define DDD7 7 - -#define PORTD _SFR_IO8(0x0B) -#define PORTD0 0 -#define PORTD1 1 -#define PORTD2 2 -#define PORTD3 3 -#define PORTD4 4 -#define PORTD5 5 -#define PORTD6 6 -#define PORTD7 7 - -#define PINE _SFR_IO8(0x0C) -#define PINE0 0 -#define PINE1 1 -#define PINE2 2 -#define PINE3 3 -#define PINE4 4 -#define PINE5 5 -#define PINE6 6 -#define PINE7 7 - -#define DDRE _SFR_IO8(0x0D) -#define DDE0 0 -#define DDE1 1 -#define DDE2 2 -#define DDE3 3 -#define DDE4 4 -#define DDE5 5 -#define DDE6 6 -#define DDE7 7 - -#define PORTE _SFR_IO8(0x0E) -#define PORTE0 0 -#define PORTE1 1 -#define PORTE2 2 -#define PORTE3 3 -#define PORTE4 4 -#define PORTE5 5 -#define PORTE6 6 -#define PORTE7 7 - -#define TIFR0 _SFR_IO8(0x15) -#define TOV0 0 -#define OCF0A 1 -#define OCF0B 2 - -#define TIFR1 _SFR_IO8(0x16) -#define TOV1 0 -#define OCF1A 1 -#define OCF1B 2 -#define ICF1 5 - -#define TIFR2 _SFR_IO8(0x17) -#define TOV2 0 -#define OCF2A 1 -#define OCF2B 2 - -#define EIRR _SFR_IO8(0x1A) -#define INTD2 2 -#define INTD3 3 - -#define PCIFR _SFR_IO8(0x1B) -#define PCIF0 0 -#define PCIF1 1 -#define PCIF2 2 -#define PCIF3 3 - -#define EIFR _SFR_IO8(0x1C) -#define INTF0 0 -#define INTF1 1 -#define INTF2 2 -#define INTF3 3 - -#define EIMSK _SFR_IO8(0x1D) -#define INT0 0 -#define INT1 1 -#define INT2 2 -#define INT3 3 - -#define GPIOR0 _SFR_IO8(0x1E) -#define GPIOR00 0 -#define GPIOR01 1 -#define GPIOR02 2 -#define GPIOR03 3 -#define GPIOR04 4 -#define GPIOR05 5 -#define GPIOR06 6 -#define GPIOR07 7 - -#define EECR _SFR_IO8(0x1F) -#define EERE 0 -#define EEPE 1 -#define EEMPE 2 -#define EERIE 3 -#define EEPM0 4 -#define EEPM1 5 - -#define EEDR _SFR_IO8(0x20) -#define EEDR0 0 -#define EEDR1 1 -#define EEDR2 2 -#define EEDR3 3 -#define EEDR4 4 -#define EEDR5 5 -#define EEDR6 6 -#define EEDR7 7 - -#define EEAR _SFR_IO16(0x21) - -#define EEARL _SFR_IO8(0x21) -#define EEAR0 0 -#define EEAR1 1 -#define EEAR2 2 -#define EEAR3 3 -#define EEAR4 4 -#define EEAR5 5 -#define EEAR6 6 -#define EEAR7 7 - -#define EEARH _SFR_IO8(0x22) -#define EEAR8 0 -#define EEAR9 1 -#define EEAR10 2 -#define EEAR11 3 - -#define GTCCR _SFR_IO8(0x23) -#define PSRSYNC 0 -#define PSRASY 1 -#define TSM 7 - -#define TCCR0A _SFR_IO8(0x24) -#define WGM00 0 -#define WGM01 1 -#define COM0B0 4 -#define COM0B1 5 -#define COM0A0 6 -#define COM0A1 7 - -#define TCCR0B _SFR_IO8(0x25) -#define CS00 0 -#define CS01 1 -#define CS02 2 -#define WGM02 3 -#define FOC0B 6 -#define FOC0A 7 - -#define TCNT0 _SFR_IO8(0x26) -#define TCNT0_0 0 -#define TCNT0_1 1 -#define TCNT0_2 2 -#define TCNT0_3 3 -#define TCNT0_4 4 -#define TCNT0_5 5 -#define TCNT0_6 6 -#define TCNT0_7 7 - -#define OCR0A _SFR_IO8(0x27) -#define OCR0A_0 0 -#define OCR0A_1 1 -#define OCR0A_2 2 -#define OCR0A_3 3 -#define OCR0A_4 4 -#define OCR0A_5 5 -#define OCR0A_6 6 -#define OCR0A_7 7 - -#define OCR0B _SFR_IO8(0x28) -#define OCR0B_0 0 -#define OCR0B_1 1 -#define OCR0B_2 2 -#define OCR0B_3 3 -#define OCR0B_4 4 -#define OCR0B_5 5 -#define OCR0B_6 6 -#define OCR0B_7 7 - -#define GPIOR1 _SFR_IO8(0x2A) -#define GPIOR10 0 -#define GPIOR11 1 -#define GPIOR12 2 -#define GPIOR13 3 -#define GPIOR14 4 -#define GPIOR15 5 -#define GPIOR16 6 -#define GPIOR17 7 - -#define GPIOR2 _SFR_IO8(0x2B) -#define GPIOR20 0 -#define GPIOR21 1 -#define GPIOR22 2 -#define GPIOR23 3 -#define GPIOR24 4 -#define GPIOR25 5 -#define GPIOR26 6 -#define GPIOR27 7 - -#define SPCR _SFR_IO8(0x2C) -#define SPR0 0 -#define SPR1 1 -#define CPHA 2 -#define CPOL 3 -#define MSTR 4 -#define DORD 5 -#define SPE 6 -#define SPIE 7 - -#define SPSR _SFR_IO8(0x2D) -#define SPI2X 0 -#define WCOL 6 -#define SPIF 7 - -#define SPDR _SFR_IO8(0x2E) -#define SPDR0 0 -#define SPDR1 1 -#define SPDR2 2 -#define SPDR3 3 -#define SPDR4 4 -#define SPDR5 5 -#define SPDR6 6 -#define SPDR7 7 - -#define OCDR _SFR_IO8(0x31) -#define OCDR0 0 -#define OCDR1 1 -#define OCDR2 2 -#define OCDR3 3 -#define OCDR4 4 -#define OCDR5 5 -#define OCDR6 6 -#define OCDR7 7 - -#define SMCR _SFR_IO8(0x33) -#define SE 0 -#define SM0 1 -#define SM1 2 -#define SM2 3 - -#define MCUSR _SFR_IO8(0x34) -#define PORF 0 -#define EXTRF 1 -#define BORF 2 -#define WDRF 3 -#define JTRF 4 - -#define MCUCR _SFR_IO8(0x35) -#define IVCE 0 -#define IVSEL 1 -#define PUD 4 -#define BODSE 5 -#define BODS 6 -#define JTD 7 - -#define SPMCSR _SFR_IO8(0x37) -#define SPMEN 0 -#define PGERS 1 -#define PGWRT 2 -#define BLBSET 3 -#define RWWSRE 4 -#define SIGRD 5 -#define RWWSB 6 -#define SPMIE 7 - -#define RAMPZ _SFR_IO8(0x3B) -#define RAMPZ0 0 - -#define WDTCSR _SFR_MEM8(0x60) -#define WDP0 0 -#define WDP1 1 -#define WDP2 2 -#define WDE 3 -#define WDCE 4 -#define WDP3 5 -#define WDIE 6 -#define WDIF 7 - -#define CLKPR _SFR_MEM8(0x61) -#define CLKPS0 0 -#define CLKPS1 1 -#define CLKPS2 2 -#define CLKPS3 3 -#define CLKPCE 7 - -#define PLLCR _SFR_MEM8(0x62) -#define ON 0 -#define LOCK 1 -#define PLLMUX 7 - -#define SMONCR _SFR_MEM8(0x63) -#define SMONEN 0 -#define SMONIE 1 -#define SMONIF 4 - -#define PRR0 _SFR_MEM8(0x64) -#define PRUSART0 1 -#define PRSPI 2 -#define PRTIM1 3 -#define PRTIM0 5 -#define PRTIM2 6 -#define PRTWI 7 - -#define __AVR_HAVE_PRR0 ((1< instead of this file." -#endif - -#ifndef _AVR_IOXXX_H_ -# define _AVR_IOXXX_H_ "ioa5272.h" -#else -# error "Attempt to include more than one file." -#endif - -/* Registers and associated bit numbers */ - -#define PINA _SFR_IO8(0x00) -#define PINA7 7 -#define PINA6 6 -#define PINA5 5 -#define PINA4 4 -#define PINA3 3 -#define PINA2 2 -#define PINA1 1 -#define PINA0 0 - -#define DDRA _SFR_IO8(0x01) -#define DDRA7 7 -// Inserted "DDA7" from "DDRA7" due to compatibility -#define DDA7 7 -#define DDRA6 6 -// Inserted "DDA6" from "DDRA6" due to compatibility -#define DDA6 6 -#define DDRA5 5 -// Inserted "DDA5" from "DDRA5" due to compatibility -#define DDA5 5 -#define DDRA4 4 -// Inserted "DDA4" from "DDRA4" due to compatibility -#define DDA4 4 -#define DDRA3 3 -// Inserted "DDA3" from "DDRA3" due to compatibility -#define DDA3 3 -#define DDRA2 2 -// Inserted "DDA2" from "DDRA2" due to compatibility -#define DDA2 2 -#define DDRA1 1 -// Inserted "DDA1" from "DDRA1" due to compatibility -#define DDA1 1 -#define DDRA0 0 -// Inserted "DDA0" from "DDRA0" due to compatibility -#define DDA0 0 - -#define PORTA _SFR_IO8(0x02) -#define PORTA7 7 -#define PORTA6 6 -#define PORTA5 5 -#define PORTA4 4 -#define PORTA3 3 -#define PORTA2 2 -#define PORTA1 1 -#define PORTA0 0 - -#define PINB _SFR_IO8(0x03) -#define PINB7 7 -#define PINB6 6 -#define PINB5 5 -#define PINB4 4 -#define PINB3 3 -#define PINB2 2 -#define PINB1 1 -#define PINB0 0 - -#define DDRB _SFR_IO8(0x04) -#define DDRB7 7 -// Inserted "DDB7" from "DDRB7" due to compatibility -#define DDB7 7 -#define DDRB6 6 -// Inserted "DDB6" from "DDRB6" due to compatibility -#define DDB6 6 -#define DDRB5 5 -// Inserted "DDB5" from "DDRB5" due to compatibility -#define DDB5 5 -#define DDRB4 4 -// Inserted "DDB4" from "DDRB4" due to compatibility -#define DDB4 4 -#define DDRB3 3 -// Inserted "DDB3" from "DDRB3" due to compatibility -#define DDB3 3 -#define DDRB2 2 -// Inserted "DDB2" from "DDRB2" due to compatibility -#define DDB2 2 -#define DDRB1 1 -// Inserted "DDB1" from "DDRB1" due to compatibility -#define DDB1 1 -#define DDRB0 0 -// Inserted "DDB0" from "DDRB0" due to compatibility -#define DDB0 0 - -#define PORTB _SFR_IO8(0x05) -#define PORTB7 7 -#define PORTB6 6 -#define PORTB5 5 -#define PORTB4 4 -#define PORTB3 3 -#define PORTB2 2 -#define PORTB1 1 -#define PORTB0 0 - -/* Reserved [0x06..0x11] */ - -#define PORTCR _SFR_IO8(0x12) -#define PUDA 0 -#define PUDB 1 -#define BBMA 4 -#define BBMB 5 - -/* Reserved [0x13..0x14] */ - -#define TIFR0 _SFR_IO8(0x15) -#define TOV0 0 -#define OCF0A 1 - -#define TIFR1 _SFR_IO8(0x16) -#define TOV1 0 -#define OCF1A 1 -#define OCF1B 2 -#define ICF1 5 - -/* Reserved [0x17..0x1A] */ - -#define PCIFR _SFR_IO8(0x1B) -#define PCIF0 0 -#define PCIF1 1 - -#define EIFR _SFR_IO8(0x1C) -#define INTF0 0 -#define INTF1 1 - -#define EIMSK _SFR_IO8(0x1D) -#define INT0 0 -#define INT1 1 - -#define GPIOR0 _SFR_IO8(0x1E) - -#define EECR _SFR_IO8(0x1F) -#define EERE 0 -#define EEPE 1 -#define EEMPE 2 -#define EERIE 3 -#define EEPM0 4 -#define EEPM1 5 - -#define EEDR _SFR_IO8(0x20) - -/* Combine EEARL and EEARH */ -#define EEAR _SFR_IO16(0x21) - -#define EEARL _SFR_IO8(0x21) -#define EEARH _SFR_IO8(0x22) - -#define GTCCR _SFR_IO8(0x23) -#define PSR1 0 -#define PSR0 1 -#define TSM 7 - -/* Reserved [0x24] */ - -#define TCCR0A _SFR_IO8(0x25) -#define WGM00 0 -#define WGM01 1 -#define COM0A0 6 -#define COM0A1 7 - -#define TCCR0B _SFR_IO8(0x26) -#define CS00 0 -#define CS01 1 -#define CS02 2 -#define FOC0A 7 - -#define TCNT2 _SFR_IO8(0x27) - -#define OCR0A _SFR_IO8(0x28) - -/* Reserved [0x29] */ - -#define GPIOR1 _SFR_IO8(0x2A) - -#define GPIOR2 _SFR_IO8(0x2B) - -#define SPCR _SFR_IO8(0x2C) -#define SPR0 0 -#define SPR1 1 -#define CPHA 2 -#define CPOL 3 -#define MSTR 4 -#define DORD 5 -#define SPE 6 -#define SPIE 7 - -#define SPSR _SFR_IO8(0x2D) -#define SPI2X 0 -#define WCOL 6 -#define SPIF 7 - -#define SPDR _SFR_IO8(0x2E) - -/* Reserved [0x2F] */ - -#define ACSR _SFR_IO8(0x30) -#define ACIS0 0 -#define ACIS1 1 -#define ACIC 2 -#define ACIE 3 -#define ACI 4 -#define ACO 5 -#define ACIRS 6 -#define ACD 7 - -#define DWDR _SFR_IO8(0x31) - -/* Reserved [0x32] */ - -#define SMCR _SFR_IO8(0x33) -#define SE 0 -#define SM0 1 -#define SM1 2 - -#define MCUSR _SFR_IO8(0x34) -#define PORF 0 -#define EXTRF 1 -#define BORF 2 -#define WDRF 3 - -#define MCUCR _SFR_IO8(0x35) -#define PUD 4 -#define BODSE 5 -#define BODS 6 - -/* Reserved [0x36] */ - -#define SPMCSR _SFR_IO8(0x37) -#define SPMEN 0 -#define PGERS 1 -#define PGWRT 2 -#define RFLB 3 -#define CTPB 4 -#define SIGRD 5 -#define RWWSB 6 - -/* Reserved [0x38..0x3C] */ - -/* SP [0x3D..0x3E] */ - -/* SREG [0x3F] */ - -#define WDTCR _SFR_MEM8(0x60) -#define WDE 3 -#define WDCE 4 -#define WDP0 0 -#define WDP1 1 -#define WDP2 2 -#define WDP3 5 -#define WDIE 6 -#define WDIF 7 - -#define CLKPR _SFR_MEM8(0x61) -#define CLKPS0 0 -#define CLKPS1 1 -#define CLKPS2 2 -#define CLKPS3 3 -#define CLKPCE 7 - -#define CLKCSR _SFR_MEM8(0x62) -#define CLKC0 0 -#define CLKC1 1 -#define CLKC2 2 -#define CLKC3 3 -#define CLKRDY 4 -#define CLKCCE 7 - -#define CLKSELR _SFR_MEM8(0x63) -#define CSEL0 0 -#define CSEL1 1 -#define CSEL2 2 -#define CSEL3 3 -#define CSUT0 4 -#define CSUT1 5 -#define COUT 6 - -#define PRR _SFR_MEM8(0x64) -#define PRADC 0 -#define PRUSI 1 -#define PRTIM0 2 -#define PRTIM1 3 -#define PRSPI 4 -#define PRLIN 5 - -#define __AVR_HAVE_PRR ((1< instead of this file." -#endif - -#ifndef _AVR_IOXXX_H_ -# define _AVR_IOXXX_H_ "ioa5505.h" -#else -# error "Attempt to include more than one file." -#endif - -/* Registers and associated bit numbers */ - -#define PINA _SFR_IO8(0x00) -#define PINA7 7 -#define PINA6 6 -#define PINA5 5 -#define PINA4 4 -#define PINA3 3 -#define PINA2 2 -#define PINA1 1 -#define PINA0 0 - -#define DDRA _SFR_IO8(0x01) -#define DDRA7 7 -// Inserted "DDA7" from "DDRA7" due to compatibility -#define DDA7 7 -#define DDRA6 6 -// Inserted "DDA6" from "DDRA6" due to compatibility -#define DDA6 6 -#define DDRA5 5 -// Inserted "DDA5" from "DDRA5" due to compatibility -#define DDA5 5 -#define DDRA4 4 -// Inserted "DDA4" from "DDRA4" due to compatibility -#define DDA4 4 -#define DDRA3 3 -// Inserted "DDA3" from "DDRA3" due to compatibility -#define DDA3 3 -#define DDRA2 2 -// Inserted "DDA2" from "DDRA2" due to compatibility -#define DDA2 2 -#define DDRA1 1 -// Inserted "DDA1" from "DDRA1" due to compatibility -#define DDA1 1 -#define DDRA0 0 -// Inserted "DDA0" from "DDRA0" due to compatibility -#define DDA0 0 - -#define PORTA _SFR_IO8(0x02) -#define PORTA7 7 -#define PORTA6 6 -#define PORTA5 5 -#define PORTA4 4 -#define PORTA3 3 -#define PORTA2 2 -#define PORTA1 1 -#define PORTA0 0 - -#define PINB _SFR_IO8(0x03) -#define PINB7 7 -#define PINB6 6 -#define PINB5 5 -#define PINB4 4 -#define PINB3 3 -#define PINB2 2 -#define PINB1 1 -#define PINB0 0 - -#define DDRB _SFR_IO8(0x04) -#define DDRB7 7 -// Inserted "DDB7" from "DDRB7" due to compatibility -#define DDB7 7 -#define DDRB6 6 -// Inserted "DDB6" from "DDRB6" due to compatibility -#define DDB6 6 -#define DDRB5 5 -// Inserted "DDB5" from "DDRB5" due to compatibility -#define DDB5 5 -#define DDRB4 4 -// Inserted "DDB4" from "DDRB4" due to compatibility -#define DDB4 4 -#define DDRB3 3 -// Inserted "DDB3" from "DDRB3" due to compatibility -#define DDB3 3 -#define DDRB2 2 -// Inserted "DDB2" from "DDRB2" due to compatibility -#define DDB2 2 -#define DDRB1 1 -// Inserted "DDB1" from "DDRB1" due to compatibility -#define DDB1 1 -#define DDRB0 0 -// Inserted "DDB0" from "DDRB0" due to compatibility -#define DDB0 0 - -#define PORTB _SFR_IO8(0x05) -#define PORTB7 7 -#define PORTB6 6 -#define PORTB5 5 -#define PORTB4 4 -#define PORTB3 3 -#define PORTB2 2 -#define PORTB1 1 -#define PORTB0 0 - -/* Reserved [0x06..0x11] */ - -#define PORTCR _SFR_IO8(0x12) -#define PUDA 0 -#define PUDB 1 -#define BBMA 4 -#define BBMB 5 - -/* Reserved [0x13..0x14] */ - -#define TIFR0 _SFR_IO8(0x15) -#define TOV0 0 -#define OCF0A 1 - -#define TIFR1 _SFR_IO8(0x16) -#define TOV1 0 -#define OCF1A 1 -#define OCF1B 2 -#define ICF1 5 - -/* Reserved [0x17..0x1A] */ - -#define PCIFR _SFR_IO8(0x1B) -#define PCIF0 0 -#define PCIF1 1 - -#define EIFR _SFR_IO8(0x1C) -#define INTF0 0 -#define INTF1 1 - -#define EIMSK _SFR_IO8(0x1D) -#define INT0 0 -#define INT1 1 - -#define GPIOR0 _SFR_IO8(0x1E) - -#define EECR _SFR_IO8(0x1F) -#define EERE 0 -#define EEPE 1 -#define EEMPE 2 -#define EERIE 3 -#define EEPM0 4 -#define EEPM1 5 - -#define EEDR _SFR_IO8(0x20) - -/* Combine EEARL and EEARH */ -#define EEAR _SFR_IO16(0x21) - -#define EEARL _SFR_IO8(0x21) -#define EEARH _SFR_IO8(0x22) - -#define GTCCR _SFR_IO8(0x23) -#define PSR1 0 -#define PSR0 1 -#define TSM 7 - -/* Reserved [0x24] */ - -#define TCCR0A _SFR_IO8(0x25) -#define WGM00 0 -#define WGM01 1 -#define COM0A0 6 -#define COM0A1 7 - -#define TCCR0B _SFR_IO8(0x26) -#define CS00 0 -#define CS01 1 -#define CS02 2 -#define FOC0A 7 - -#define TCNT2 _SFR_IO8(0x27) - -#define OCR0A _SFR_IO8(0x28) - -/* Reserved [0x29] */ - -#define GPIOR1 _SFR_IO8(0x2A) - -#define GPIOR2 _SFR_IO8(0x2B) - -#define SPCR _SFR_IO8(0x2C) -#define SPR0 0 -#define SPR1 1 -#define CPHA 2 -#define CPOL 3 -#define MSTR 4 -#define DORD 5 -#define SPE 6 -#define SPIE 7 - -#define SPSR _SFR_IO8(0x2D) -#define SPI2X 0 -#define WCOL 6 -#define SPIF 7 - -#define SPDR _SFR_IO8(0x2E) - -/* Reserved [0x2F] */ - -#define ACSR _SFR_IO8(0x30) -#define ACIS0 0 -#define ACIS1 1 -#define ACIC 2 -#define ACIE 3 -#define ACI 4 -#define ACO 5 -#define ACIRS 6 -#define ACD 7 - -#define DWDR _SFR_IO8(0x31) - -/* Reserved [0x32] */ - -#define SMCR _SFR_IO8(0x33) -#define SE 0 -#define SM0 1 -#define SM1 2 - -#define MCUSR _SFR_IO8(0x34) -#define PORF 0 -#define EXTRF 1 -#define BORF 2 -#define WDRF 3 - -#define MCUCR _SFR_IO8(0x35) -#define PUD 4 -#define BODSE 5 -#define BODS 6 - -/* Reserved [0x36] */ - -#define SPMCSR _SFR_IO8(0x37) -#define SPMEN 0 -#define PGERS 1 -#define PGWRT 2 -#define RFLB 3 -#define CTPB 4 -#define SIGRD 5 -#define RWWSB 6 - -/* Reserved [0x38..0x3C] */ - -/* SP [0x3D..0x3E] */ - -/* SREG [0x3F] */ - -#define WDTCR _SFR_MEM8(0x60) -#define WDE 3 -#define WDCE 4 -#define WDP0 0 -#define WDP1 1 -#define WDP2 2 -#define WDP3 5 -#define WDIE 6 -#define WDIF 7 - -#define CLKPR _SFR_MEM8(0x61) -#define CLKPS0 0 -#define CLKPS1 1 -#define CLKPS2 2 -#define CLKPS3 3 -#define CLKPCE 7 - -#define CLKCSR _SFR_MEM8(0x62) -#define CLKC0 0 -#define CLKC1 1 -#define CLKC2 2 -#define CLKC3 3 -#define CLKRDY 4 -#define CLKCCE 7 - -#define CLKSELR _SFR_MEM8(0x63) -#define CSEL0 0 -#define CSEL1 1 -#define CSEL2 2 -#define CSEL3 3 -#define CSUT0 4 -#define CSUT1 5 -#define COUT 6 - -#define PRR _SFR_MEM8(0x64) -#define PRADC 0 -#define PRUSI 1 -#define PRTIM0 2 -#define PRTIM1 3 -#define PRSPI 4 -#define PRLIN 5 - -#define __AVR_HAVE_PRR ((1< instead of this file." -#endif - -#ifndef _AVR_IOXXX_H_ -# define _AVR_IOXXX_H_ "ioa5702m322.h" -#else -# error "Attempt to include more than one file." -#endif - -/* Registers and associated bit numbers */ - -#define GPIOR0 _SFR_IO8(0x00) - -#define PRR1 _SFR_IO8(0x01) -#define PRT1 0 -#define PRT2 1 -#define PRT3 2 -#define PRT4 3 -#define PRT5 4 -#define PRLFR 5 -#define PRLFTP 6 -#define PRLFPH 7 - -#define __AVR_HAVE_PRR1 ((1< instead of this file." -#endif - -#ifndef _AVR_IOXXX_H_ -# define _AVR_IOXXX_H_ "ioa5782.h" -#else -# error "Attempt to include more than one file." -#endif - -/* Registers and associated bit numbers */ - -#define PRR0 _SFR_IO8(0x01) -#define PRSPI 0 -#define PRRXDC 1 -#define PRTXDC 2 -#define PRCRC 3 -#define PRVM 4 -#define PRCO 5 - -#define __AVR_HAVE_PRR0 ((1< instead of this file." -#endif - -#ifndef _AVR_IOXXX_H_ -# define _AVR_IOXXX_H_ "ioa5790.h" -#else -# error "Attempt to include more than one file." -#endif - -/* Registers and associated bit numbers */ - -#define PINB _SFR_IO8(0x03) -#define PINB7 7 -#define PINB6 6 -#define PINB5 5 -#define PINB4 4 -#define PINB3 3 -#define PINB2 2 -#define PINB1 1 -#define PINB0 0 - -#define DDRB _SFR_IO8(0x04) -#define DDRB7 7 -// Inserted "DDB7" from "DDRB7" due to compatibility -#define DDB7 7 -#define DDRB6 6 -// Inserted "DDB6" from "DDRB6" due to compatibility -#define DDB6 6 -#define DDRB5 5 -// Inserted "DDB5" from "DDRB5" due to compatibility -#define DDB5 5 -#define DDRB4 4 -// Inserted "DDB4" from "DDRB4" due to compatibility -#define DDB4 4 -#define DDRB3 3 -// Inserted "DDB3" from "DDRB3" due to compatibility -#define DDB3 3 -#define DDRB2 2 -// Inserted "DDB2" from "DDRB2" due to compatibility -#define DDB2 2 -#define DDRB1 1 -// Inserted "DDB1" from "DDRB1" due to compatibility -#define DDB1 1 -#define DDRB0 0 -// Inserted "DDB0" from "DDRB0" due to compatibility -#define DDB0 0 - -#define PORTB _SFR_IO8(0x05) -#define PORTB7 7 -#define PORTB6 6 -#define PORTB5 5 -#define PORTB4 4 -#define PORTB3 3 -#define PORTB2 2 -#define PORTB1 1 -#define PORTB0 0 - -#define PINC _SFR_IO8(0x06) -#define PINC7 7 -#define PINC6 6 -#define PINC5 5 -#define PINC4 4 -#define PINC3 3 -#define PINC2 2 -#define PINC1 1 -#define PINC0 0 - -#define DDRC _SFR_IO8(0x07) -#define DDRC7 7 -// Inserted "DDC7" from "DDRC7" due to compatibility -#define DDC7 7 -#define DDRC6 6 -// Inserted "DDC6" from "DDRC6" due to compatibility -#define DDC6 6 -#define DDRC5 5 -// Inserted "DDC5" from "DDRC5" due to compatibility -#define DDC5 5 -#define DDRC4 4 -// Inserted "DDC4" from "DDRC4" due to compatibility -#define DDC4 4 -#define DDRC3 3 -// Inserted "DDC3" from "DDRC3" due to compatibility -#define DDC3 3 -#define DDRC2 2 -// Inserted "DDC2" from "DDRC2" due to compatibility -#define DDC2 2 -#define DDRC1 1 -// Inserted "DDC1" from "DDRC1" due to compatibility -#define DDC1 1 -#define DDRC0 0 -// Inserted "DDC0" from "DDRC0" due to compatibility -#define DDC0 0 - -#define PORTC _SFR_IO8(0x08) -#define PORTC7 7 -#define PORTC6 6 -#define PORTC5 5 -#define PORTC4 4 -#define PORTC3 3 -#define PORTC2 2 -#define PORTC1 1 -#define PORTC0 0 - -#define PIND _SFR_IO8(0x09) -#define PIND7 7 -#define PIND6 6 -#define PIND5 5 -#define PIND4 4 -#define PIND3 3 -#define PIND2 2 -#define PIND1 1 -#define PIND0 0 - -#define DDRD _SFR_IO8(0x0A) -#define DDRD7 7 -// Inserted "DDD7" from "DDRD7" due to compatibility -#define DDD7 7 -#define DDRD6 6 -// Inserted "DDD6" from "DDRD6" due to compatibility -#define DDD6 6 -#define DDRD5 5 -// Inserted "DDD5" from "DDRD5" due to compatibility -#define DDD5 5 -#define DDRD4 4 -// Inserted "DDD4" from "DDRD4" due to compatibility -#define DDD4 4 -#define DDRD3 3 -// Inserted "DDD3" from "DDRD3" due to compatibility -#define DDD3 3 -#define DDRD2 2 -// Inserted "DDD2" from "DDRD2" due to compatibility -#define DDD2 2 -#define DDRD1 1 -// Inserted "DDD1" from "DDRD1" due to compatibility -#define DDD1 1 -#define DDRD0 0 -// Inserted "DDD0" from "DDRD0" due to compatibility -#define DDD0 0 - -#define PORTD _SFR_IO8(0x0B) -#define PORTD7 7 -#define PORTD6 6 -#define PORTD5 5 -#define PORTD4 4 -#define PORTD3 3 -#define PORTD2 2 -#define PORTD1 1 -#define PORTD0 0 - -/* Reserved [0x0C] */ - -#define TPCR _SFR_IO8(0x0D) -#define TPMA 0 -#define TPMOD 1 -#define TPMS0 2 -#define TPMS1 3 -#define TPMD0 4 -#define TPMD1 5 -#define TPPSD 6 -#define TPD 7 - -#define TPFR _SFR_IO8(0x0E) -#define TPF 0 -#define TPA 1 -#define TPGAP 2 -#define TPPSW 3 - -#define CMCR _SFR_IO8(0x0F) -#define CMM0 0 -#define CMM1 1 -#define SRCD 2 -#define CO32D 3 -#define CCS 4 -#define ECINS 5 -#define CMONEN 6 -#define CMCCE 7 - -#define CMSR _SFR_IO8(0x10) -#define ECF 0 -#define SXF 1 -#define RTCF 2 - -#define T2CR _SFR_IO8(0x11) -#define T2OTM 0 -#define T2CTM 1 -#define T2CRM 2 -#define T2GRM 3 -#define T2TOP 4 -#define T2RES 5 -#define T2TS 6 -#define T2E 7 - -#define T3CR _SFR_IO8(0x12) -#define T3OTM 0 -#define T3CTM 1 -#define T3CRM 2 -#define T3CPRM 3 -#define T3TOP 4 -#define T3RES 5 -#define T3CPTM 6 -#define T3E 7 - -#define AESCR _SFR_IO8(0x13) -#define AESWK 0 -#define AESWD 1 -#define AESIM 2 -#define AESD 3 -#define AESXOR 4 -#define AESRES 5 -#define AESE 7 - -#define AESSR _SFR_IO8(0x14) -#define AESRF 0 -#define AESERF 7 - -#define TMIFR _SFR_IO8(0x15) -#define TMRXF 0 -#define TMTXF 1 -#define TMTCF 2 -#define TMRXS 3 -#define TMTXS 4 - -#define VMSR _SFR_IO8(0x16) -#define VMF 0 - -#define PCIFR _SFR_IO8(0x17) -#define PCIF0 0 -#define PCIF1 1 - -#define LFFR _SFR_IO8(0x18) -#define LFID0F 0 -#define LFID1F 1 -#define LFFEF 2 -#define LFDBF 3 -#define LFRSF 4 -#define LFSDF 5 -#define LFMDF 6 -#define LFCAF 7 - -#define T0IFR _SFR_IO8(0x19) -#define T0F 0 - -#define T1IFR _SFR_IO8(0x1A) -#define T1F 0 - -#define T2IFR _SFR_IO8(0x1B) -#define T2OFF 0 -#define T2COF 1 - -#define T3IFR _SFR_IO8(0x1C) -#define T3OFF 0 -#define T3COF 1 -#define T3ICF 2 - -#define EIFR _SFR_IO8(0x1D) -#define INTF0 0 - -#define GPIOR _SFR_IO8(0x1E) - -#define EECR _SFR_IO8(0x1F) -#define EERE 0 -#define EEWE 1 -#define EEMWE 2 -#define EERIE 3 -#define EEPM0 4 -#define EEPM1 5 -#define EELP 6 - -#define EEDR _SFR_IO8(0x20) - -/* Combine EEARL and EEARH */ -#define EEAR _SFR_IO16(0x21) - -#define EEARL _SFR_IO8(0x21) -#define EEARH _SFR_IO8(0x22) - -#define EEPR _SFR_IO8(0x23) -#define EEAP0 0 -#define EEAP1 1 -#define EEAP2 2 -#define EEAP3 3 - -#define EECCR _SFR_IO8(0x24) -#define EEL0 0 -#define EEL1 1 -#define EEL2 2 -#define EEL3 3 - -/* Reserved [0x25] */ - -#define PCICR _SFR_IO8(0x26) -#define PCIE0 0 -#define PCIE1 1 - -#define EIMSK _SFR_IO8(0x27) -#define INT0 0 - -#define TMDR _SFR_IO8(0x28) - -#define AESDR _SFR_IO8(0x29) - -#define AESKR _SFR_IO8(0x2A) -#define AESKR0 0 -#define AESKR1 1 -#define AESKR2 2 -#define AESKR3 3 -#define AESKR4 4 -#define AESKR5 5 -#define AESKR6 6 -#define AESKR7 7 - -#define VMCR _SFR_IO8(0x2B) -#define VMLS0 0 -#define VMLS1 1 -#define VMLS2 2 -#define VMLS3 3 -#define VMIM 4 -#define VMPS 5 -#define BODPD 6 -#define BODLS 7 - -#define SPCR _SFR_IO8(0x2C) -#define SPR0 0 -#define SPR1 1 -#define CPHA 2 -#define CPOL 3 -#define MSTR 4 -#define DORD 5 -#define SPE 6 -#define SPIE 7 - -#define SPSR _SFR_IO8(0x2D) -#define SPI2X 0 -#define WCOL 6 -#define SPIF 7 - -#define SPDR _SFR_IO8(0x2E) - -#define LFCR0 _SFR_IO8(0x2F) -#define LFCE1 0 -#define LFCE2 1 -#define LFCE3 2 -#define LFBRS 3 -#define LFRBS 4 -#define LFMG 5 -#define LFVC0 6 -#define LFVC1 7 - -#define LFCR1 _SFR_IO8(0x30) -#define LFM0 0 -#define LFM1 1 -#define LFFM0 2 -#define LFFM1 3 -#define LFRMS 4 -#define LFRMSA 5 -#define LFQCE 6 -#define LFRE 7 - -/* Reserved [0x31] */ - -#define LFRDB _SFR_IO8(0x32) - -#define SMCR _SFR_IO8(0x33) -#define SE 0 -#define SM0 1 -#define SM1 2 -#define SM2 3 - -#define MCUSR _SFR_IO8(0x34) -#define PORF 0 -#define EXTRF 1 -#define BORF 2 -#define WDRF 3 -#define TPRF 5 - -#define MCUCR _SFR_IO8(0x35) -#define IVCE 0 -#define IVSEL 1 -#define PUD 4 - -#define LFSR _SFR_IO8(0x36) -#define LFES 0 -#define LFSD 1 - -#define SPMCSR _SFR_IO8(0x37) -#define SPMEN 0 -#define PGERS 1 -#define PGWRT 2 -#define BLBSET 3 -#define RWWSRE 4 -#define SIGRD 5 -#define RWWSB 6 -#define SPMIE 7 - -#define T1CR _SFR_IO8(0x38) -#define T1PS0 0 -#define T1PS1 1 -#define T1IE 2 -#define T1CS0 3 -#define T1CS1 4 -#define T1E 7 - -#define T0CR _SFR_IO8(0x39) -#define T0PS0 0 -#define T0PS1 1 -#define T0PS2 2 -#define T0IE 3 -#define T0PR 4 - -/* Reserved [0x3A] */ - -#define CMIMR _SFR_IO8(0x3B) -#define ECIE 0 -#define SXIE 1 -#define RTCIE 2 - -#define CLKPR _SFR_IO8(0x3C) -#define CLKPS0 0 -#define CLKPS1 1 -#define CLKPS2 2 -#define CLTPS0 3 -#define CLTPS1 4 -#define CLTPS2 5 -#define CLKPCE 7 - -/* SP [0x3D..0x3E] */ - -/* SREG [0x3F] */ - -#define WDTCR _SFR_MEM8(0x60) -#define WDPS0 0 -#define WDPS1 1 -#define WDPS2 2 -#define WDE 3 -#define WDCE 4 - -/* Reserved [0x61..0x62] */ - -#define PRR0 _SFR_MEM8(0x63) -#define PRLFR 0 -#define PRT1 1 -#define PRT2 2 -#define PRT3 3 -#define PRTM 4 -#define PRCU 5 -#define PRDS 6 -#define PRVM 7 - -#define __AVR_HAVE_PRR0 ((1< instead of this file." -#endif - -#ifndef _AVR_IOXXX_H_ -# define _AVR_IOXXX_H_ "ioa5790n.h" -#else -# error "Attempt to include more than one file." -#endif - -/* Registers and associated bit numbers */ - -#define PINB _SFR_IO8(0x03) -#define PINB7 7 -#define PINB6 6 -#define PINB5 5 -#define PINB4 4 -#define PINB3 3 -#define PINB2 2 -#define PINB1 1 -#define PINB0 0 - -#define DDRB _SFR_IO8(0x04) -#define DDRB7 7 -// Inserted "DDB7" from "DDRB7" due to compatibility -#define DDB7 7 -#define DDRB6 6 -// Inserted "DDB6" from "DDRB6" due to compatibility -#define DDB6 6 -#define DDRB5 5 -// Inserted "DDB5" from "DDRB5" due to compatibility -#define DDB5 5 -#define DDRB4 4 -// Inserted "DDB4" from "DDRB4" due to compatibility -#define DDB4 4 -#define DDRB3 3 -// Inserted "DDB3" from "DDRB3" due to compatibility -#define DDB3 3 -#define DDRB2 2 -// Inserted "DDB2" from "DDRB2" due to compatibility -#define DDB2 2 -#define DDRB1 1 -// Inserted "DDB1" from "DDRB1" due to compatibility -#define DDB1 1 -#define DDRB0 0 -// Inserted "DDB0" from "DDRB0" due to compatibility -#define DDB0 0 - -#define PORTB _SFR_IO8(0x05) -#define PORTB7 7 -#define PORTB6 6 -#define PORTB5 5 -#define PORTB4 4 -#define PORTB3 3 -#define PORTB2 2 -#define PORTB1 1 -#define PORTB0 0 - -#define PINC _SFR_IO8(0x06) -#define PINC7 7 -#define PINC6 6 -#define PINC5 5 -#define PINC4 4 -#define PINC3 3 -#define PINC2 2 -#define PINC1 1 -#define PINC0 0 - -#define DDRC _SFR_IO8(0x07) -#define DDRC7 7 -// Inserted "DDC7" from "DDRC7" due to compatibility -#define DDC7 7 -#define DDRC6 6 -// Inserted "DDC6" from "DDRC6" due to compatibility -#define DDC6 6 -#define DDRC5 5 -// Inserted "DDC5" from "DDRC5" due to compatibility -#define DDC5 5 -#define DDRC4 4 -// Inserted "DDC4" from "DDRC4" due to compatibility -#define DDC4 4 -#define DDRC3 3 -// Inserted "DDC3" from "DDRC3" due to compatibility -#define DDC3 3 -#define DDRC2 2 -// Inserted "DDC2" from "DDRC2" due to compatibility -#define DDC2 2 -#define DDRC1 1 -// Inserted "DDC1" from "DDRC1" due to compatibility -#define DDC1 1 -#define DDRC0 0 -// Inserted "DDC0" from "DDRC0" due to compatibility -#define DDC0 0 - -#define PORTC _SFR_IO8(0x08) -#define PORTC7 7 -#define PORTC6 6 -#define PORTC5 5 -#define PORTC4 4 -#define PORTC3 3 -#define PORTC2 2 -#define PORTC1 1 -#define PORTC0 0 - -#define PIND _SFR_IO8(0x09) -#define PIND7 7 -#define PIND6 6 -#define PIND5 5 -#define PIND4 4 -#define PIND3 3 -#define PIND2 2 -#define PIND1 1 -#define PIND0 0 - -#define DDRD _SFR_IO8(0x0A) -#define DDRD7 7 -// Inserted "DDD7" from "DDRD7" due to compatibility -#define DDD7 7 -#define DDRD6 6 -// Inserted "DDD6" from "DDRD6" due to compatibility -#define DDD6 6 -#define DDRD5 5 -// Inserted "DDD5" from "DDRD5" due to compatibility -#define DDD5 5 -#define DDRD4 4 -// Inserted "DDD4" from "DDRD4" due to compatibility -#define DDD4 4 -#define DDRD3 3 -// Inserted "DDD3" from "DDRD3" due to compatibility -#define DDD3 3 -#define DDRD2 2 -// Inserted "DDD2" from "DDRD2" due to compatibility -#define DDD2 2 -#define DDRD1 1 -// Inserted "DDD1" from "DDRD1" due to compatibility -#define DDD1 1 -#define DDRD0 0 -// Inserted "DDD0" from "DDRD0" due to compatibility -#define DDD0 0 - -#define PORTD _SFR_IO8(0x0B) -#define PORTD7 7 -#define PORTD6 6 -#define PORTD5 5 -#define PORTD4 4 -#define PORTD3 3 -#define PORTD2 2 -#define PORTD1 1 -#define PORTD0 0 - -#define T3CR2 _SFR_IO8(0x0C) -#define T3GRES 0 -#define T3C2TM 1 -#define T3C2RM 2 - -#define TPCR _SFR_IO8(0x0D) -#define TPMA 0 -#define TPMOD 1 -#define TPMS0 2 -#define TPMS1 3 -#define TPMD0 4 -#define TPMD1 5 -#define TPPSD 6 -#define TPD 7 - -#define TPFR _SFR_IO8(0x0E) -#define TPF 0 -#define TPA 1 -#define TPGAP 2 -#define TPPSW 3 - -#define CMCR _SFR_IO8(0x0F) -#define CMM0 0 -#define CMM1 1 -#define SRCD 2 -#define CO32D 3 -#define CCS 4 -#define ECINS 5 -#define CMONEN 6 -#define CMCCE 7 - -#define CMSR _SFR_IO8(0x10) -#define ECF 0 -#define SXF 1 -#define RTCF 2 - -#define T2CR _SFR_IO8(0x11) -#define T2OTM 0 -#define T2CTM 1 -#define T2CRM 2 -#define T2GRM 3 -#define T2TOP 4 -#define T2RES 5 -#define T2TS 6 -#define T2E 7 - -#define T3CR _SFR_IO8(0x12) -#define T3OTM 0 -#define T3CTM 1 -#define T3CRM 2 -#define T3CPRM 3 -#define T3TOP 4 -#define T3RES 5 -#define T3CPTM 6 -#define T3E 7 - -#define AESCR _SFR_IO8(0x13) -#define AESWK 0 -#define AESWD 1 -#define AESIM 2 -#define AESD 3 -#define AESXOR 4 -#define AESRES 5 -#define AESE 7 - -#define AESSR _SFR_IO8(0x14) -#define AESRF 0 -#define AESERF 7 - -#define TMIFR _SFR_IO8(0x15) -#define TMRXF 0 -#define TMTXF 1 -#define TMTCF 2 -#define TMRXS 3 -#define TMTXS 4 - -#define VMSR _SFR_IO8(0x16) -#define VMF 0 - -#define PCIFR _SFR_IO8(0x17) -#define PCIF0 0 -#define PCIF1 1 - -#define LFFR _SFR_IO8(0x18) -#define LFID0F 0 -#define LFID1F 1 -#define LFFEF 2 -#define LFDBF 3 -#define LFRSF 4 -#define LFSDF 5 -#define LFMDF 6 -#define LFCAF 7 - -#define T0IFR _SFR_IO8(0x19) -#define T0F 0 - -#define T1IFR _SFR_IO8(0x1A) -#define T1F 0 - -#define T2IFR _SFR_IO8(0x1B) -#define T2OFF 0 -#define T2COF 1 - -#define T3IFR _SFR_IO8(0x1C) -#define T3OFF 0 -#define T3COF 1 -#define T3ICF 2 -#define T3CO2F 3 - -#define EIFR _SFR_IO8(0x1D) -#define INTF0 0 - -#define GPIOR _SFR_IO8(0x1E) - -#define EECR _SFR_IO8(0x1F) -#define EERE 0 -#define EEWE 1 -#define EEMWE 2 -#define EERIE 3 -#define EEPM0 4 -#define EEPM1 5 -#define EELP 6 -#define NVMBSY 7 - -#define EEDR _SFR_IO8(0x20) - -/* Combine EEARL and EEARH */ -#define EEAR _SFR_IO16(0x21) - -#define EEARL _SFR_IO8(0x21) -#define EEARH _SFR_IO8(0x22) - -#define EEPR _SFR_IO8(0x23) -#define EEAP0 0 -#define EEAP1 1 -#define EEAP2 2 -#define EEAP3 3 - -#define EECCR _SFR_IO8(0x24) -#define EEL0 0 -#define EEL1 1 -#define EEL2 2 -#define EEL3 3 - -#define EECR2 _SFR_IO8(0x25) -#define EEBRE 0 -#define EEPAGE 1 - -#define PCICR _SFR_IO8(0x26) -#define PCIE0 0 -#define PCIE1 1 - -#define EIMSK _SFR_IO8(0x27) -#define INT0 0 - -#define TMDR _SFR_IO8(0x28) - -#define AESDR _SFR_IO8(0x29) - -#define AESKR _SFR_IO8(0x2A) -#define AESKR0 0 -#define AESKR1 1 -#define AESKR2 2 -#define AESKR3 3 -#define AESKR4 4 -#define AESKR5 5 -#define AESKR6 6 -#define AESKR7 7 - -#define VMCR _SFR_IO8(0x2B) -#define VMLS0 0 -#define VMLS1 1 -#define VMLS2 2 -#define VMLS3 3 -#define VMIM 4 -#define VMPS 5 -#define BODPD 6 -#define BODLS 7 - -#define SPCR _SFR_IO8(0x2C) -#define SPR0 0 -#define SPR1 1 -#define CPHA 2 -#define CPOL 3 -#define MSTR 4 -#define DORD 5 -#define SPE 6 -#define SPIE 7 - -#define SPSR _SFR_IO8(0x2D) -#define SPI2X 0 -#define WCOL 6 -#define SPIF 7 - -#define SPDR _SFR_IO8(0x2E) - -#define LFCR0 _SFR_IO8(0x2F) -#define LFCE1 0 -#define LFCE2 1 -#define LFCE3 2 -#define LFBRS 3 -#define LFRBS 4 -#define LFMG 5 -#define LFVC0 6 -#define LFVC1 7 - -#define LFCR1 _SFR_IO8(0x30) -#define LFM0 0 -#define LFM1 1 -#define LFFM0 2 -#define LFFM1 3 -#define LFRMS 4 -#define LFRMSA 5 -#define LFQCE 6 -#define LFRE 7 - -/* Reserved [0x31] */ - -#define LFRDB _SFR_IO8(0x32) - -#define SMCR _SFR_IO8(0x33) -#define SE 0 -#define SM0 1 -#define SM1 2 -#define SM2 3 - -#define MCUSR _SFR_IO8(0x34) -#define PORF 0 -#define EXTRF 1 -#define BORF 2 -#define WDRF 3 -#define TPRF 5 - -#define MCUCR _SFR_IO8(0x35) -#define IVCE 0 -#define IVSEL 1 -#define PUD 4 - -#define LFSR _SFR_IO8(0x36) -#define LFES 0 -#define LFSD 1 - -#define SPMCSR _SFR_IO8(0x37) -#define SPMEN 0 -#define PGERS 1 -#define PGWRT 2 -#define BLBSET 3 -#define RWWSRE 4 -#define SIGRD 5 -#define RWWSB 6 -#define SPMIE 7 - -#define T1CR _SFR_IO8(0x38) -#define T1PS0 0 -#define T1PS1 1 -#define T1IE 2 -#define T1CS0 3 -#define T1CS1 4 -#define T1E 7 - -#define T0CR _SFR_IO8(0x39) -#define T0PS0 0 -#define T0PS1 1 -#define T0PS2 2 -#define T0IE 3 -#define T0PR 4 - -/* Reserved [0x3A] */ - -#define CMIMR _SFR_IO8(0x3B) -#define ECIE 0 -#define SXIE 1 -#define RTCIE 2 - -#define CLKPR _SFR_IO8(0x3C) -#define CLKPS0 0 -#define CLKPS1 1 -#define CLKPS2 2 -#define CLTPS0 3 -#define CLTPS1 4 -#define CLTPS2 5 -#define CLKPCE 7 - -/* SP [0x3D..0x3E] */ - -/* SREG [0x3F] */ - -#define WDTCR _SFR_MEM8(0x60) -#define WDPS0 0 -#define WDPS1 1 -#define WDPS2 2 -#define WDE 3 -#define WDCE 4 - -/* Reserved [0x61..0x62] */ - -#define PRR0 _SFR_MEM8(0x63) -#define PRLFR 0 -#define PRT1 1 -#define PRT2 2 -#define PRT3 3 -#define PRTM 4 -#define PRCU 5 -#define PRDS 6 -#define PRVM 7 - -#define __AVR_HAVE_PRR0 ((1< instead of this file." -#endif - -#ifndef _AVR_IOXXX_H_ -# define _AVR_IOXXX_H_ "ioa5791.h" -#else -# error "Attempt to include more than one file." -#endif - -/* Registers and associated bit numbers */ - -#define PINB _SFR_IO8(0x03) -#define PINB7 7 -#define PINB6 6 -#define PINB5 5 -#define PINB4 4 -#define PINB3 3 -#define PINB2 2 -#define PINB1 1 -#define PINB0 0 - -#define DDRB _SFR_IO8(0x04) -#define DDRB7 7 -// Inserted "DDB7" from "DDRB7" due to compatibility -#define DDB7 7 -#define DDRB6 6 -// Inserted "DDB6" from "DDRB6" due to compatibility -#define DDB6 6 -#define DDRB5 5 -// Inserted "DDB5" from "DDRB5" due to compatibility -#define DDB5 5 -#define DDRB4 4 -// Inserted "DDB4" from "DDRB4" due to compatibility -#define DDB4 4 -#define DDRB3 3 -// Inserted "DDB3" from "DDRB3" due to compatibility -#define DDB3 3 -#define DDRB2 2 -// Inserted "DDB2" from "DDRB2" due to compatibility -#define DDB2 2 -#define DDRB1 1 -// Inserted "DDB1" from "DDRB1" due to compatibility -#define DDB1 1 -#define DDRB0 0 -// Inserted "DDB0" from "DDRB0" due to compatibility -#define DDB0 0 - -#define PORTB _SFR_IO8(0x05) -#define PORTB7 7 -#define PORTB6 6 -#define PORTB5 5 -#define PORTB4 4 -#define PORTB3 3 -#define PORTB2 2 -#define PORTB1 1 -#define PORTB0 0 - -#define PINC _SFR_IO8(0x06) -#define PINC7 7 -#define PINC6 6 -#define PINC5 5 -#define PINC4 4 -#define PINC3 3 -#define PINC2 2 -#define PINC1 1 -#define PINC0 0 - -#define DDRC _SFR_IO8(0x07) -#define DDRC7 7 -// Inserted "DDC7" from "DDRC7" due to compatibility -#define DDC7 7 -#define DDRC6 6 -// Inserted "DDC6" from "DDRC6" due to compatibility -#define DDC6 6 -#define DDRC5 5 -// Inserted "DDC5" from "DDRC5" due to compatibility -#define DDC5 5 -#define DDRC4 4 -// Inserted "DDC4" from "DDRC4" due to compatibility -#define DDC4 4 -#define DDRC3 3 -// Inserted "DDC3" from "DDRC3" due to compatibility -#define DDC3 3 -#define DDRC2 2 -// Inserted "DDC2" from "DDRC2" due to compatibility -#define DDC2 2 -#define DDRC1 1 -// Inserted "DDC1" from "DDRC1" due to compatibility -#define DDC1 1 -#define DDRC0 0 -// Inserted "DDC0" from "DDRC0" due to compatibility -#define DDC0 0 - -#define PORTC _SFR_IO8(0x08) -#define PORTC7 7 -#define PORTC6 6 -#define PORTC5 5 -#define PORTC4 4 -#define PORTC3 3 -#define PORTC2 2 -#define PORTC1 1 -#define PORTC0 0 - -#define PIND _SFR_IO8(0x09) -#define PIND7 7 -#define PIND6 6 -#define PIND5 5 -#define PIND4 4 -#define PIND3 3 -#define PIND2 2 -#define PIND1 1 -#define PIND0 0 - -#define DDRD _SFR_IO8(0x0A) -#define DDRD7 7 -// Inserted "DDD7" from "DDRD7" due to compatibility -#define DDD7 7 -#define DDRD6 6 -// Inserted "DDD6" from "DDRD6" due to compatibility -#define DDD6 6 -#define DDRD5 5 -// Inserted "DDD5" from "DDRD5" due to compatibility -#define DDD5 5 -#define DDRD4 4 -// Inserted "DDD4" from "DDRD4" due to compatibility -#define DDD4 4 -#define DDRD3 3 -// Inserted "DDD3" from "DDRD3" due to compatibility -#define DDD3 3 -#define DDRD2 2 -// Inserted "DDD2" from "DDRD2" due to compatibility -#define DDD2 2 -#define DDRD1 1 -// Inserted "DDD1" from "DDRD1" due to compatibility -#define DDD1 1 -#define DDRD0 0 -// Inserted "DDD0" from "DDRD0" due to compatibility -#define DDD0 0 - -#define PORTD _SFR_IO8(0x0B) -#define PORTD7 7 -#define PORTD6 6 -#define PORTD5 5 -#define PORTD4 4 -#define PORTD3 3 -#define PORTD2 2 -#define PORTD1 1 -#define PORTD0 0 - -#define T3CR2 _SFR_IO8(0x0C) -#define T3GRES 0 -#define T3C2TM 1 -#define T3C2RM 2 - -#define TPCR _SFR_IO8(0x0D) -#define TPMA 0 -#define TPMOD 1 -#define TPMS0 2 -#define TPMS1 3 -#define TPMD0 4 -#define TPMD1 5 -#define TPPSD 6 -#define TPD 7 - -#define TPFR _SFR_IO8(0x0E) -#define TPF 0 -#define TPA 1 -#define TPGAP 2 -#define TPPSW 3 - -#define CMCR _SFR_IO8(0x0F) -#define CMM0 0 -#define CMM1 1 -#define SRCD 2 -#define CO32D 3 -#define CCS 4 -#define ECINS 5 -#define CMONEN 6 -#define CMCCE 7 - -#define CMSR _SFR_IO8(0x10) -#define ECF 0 -#define SXF 1 -#define RTCF 2 - -#define T2CR _SFR_IO8(0x11) -#define T2OTM 0 -#define T2CTM 1 -#define T2CRM 2 -#define T2GRM 3 -#define T2TOP 4 -#define T2RES 5 -#define T2TS 6 -#define T2E 7 - -#define T3CR _SFR_IO8(0x12) -#define T3OTM 0 -#define T3CTM 1 -#define T3CRM 2 -#define T3CPRM 3 -#define T3TOP 4 -#define T3RES 5 -#define T3CPTM 6 -#define T3E 7 - -#define AESCR _SFR_IO8(0x13) -#define AESWK 0 -#define AESWD 1 -#define AESIM 2 -#define AESD 3 -#define AESXOR 4 -#define AESRES 5 -#define AESE 7 - -#define AESSR _SFR_IO8(0x14) -#define AESRF 0 -#define AESERF 7 - -#define TMIFR _SFR_IO8(0x15) -#define TMRXF 0 -#define TMTXF 1 -#define TMTCF 2 -#define TMRXS 3 -#define TMTXS 4 - -#define VMSR _SFR_IO8(0x16) -#define VMF 0 - -#define PCIFR _SFR_IO8(0x17) -#define PCIF0 0 -#define PCIF1 1 - -#define LFFR _SFR_IO8(0x18) -#define LFID0F 0 -#define LFID1F 1 -#define LFFEF 2 -#define LFDBF 3 -#define LFRSF 4 -#define LFSDF 5 -#define LFMDF 6 -#define LFCAF 7 - -#define T0IFR _SFR_IO8(0x19) -#define T0F 0 - -#define T1IFR _SFR_IO8(0x1A) -#define T1F 0 - -#define T2IFR _SFR_IO8(0x1B) -#define T2OFF 0 -#define T2COF 1 - -#define T3IFR _SFR_IO8(0x1C) -#define T3OFF 0 -#define T3COF 1 -#define T3ICF 2 -#define T3CO2F 3 - -#define EIFR _SFR_IO8(0x1D) -#define INTF0 0 - -#define GPIOR _SFR_IO8(0x1E) - -#define EECR _SFR_IO8(0x1F) -#define EERE 0 -#define EEWE 1 -#define EEMWE 2 -#define EERIE 3 -#define EEPM0 4 -#define EEPM1 5 -#define EELP 6 -#define NVMBSY 7 - -#define EEDR _SFR_IO8(0x20) - -/* Combine EEARL and EEARH */ -#define EEAR _SFR_IO16(0x21) - -#define EEARL _SFR_IO8(0x21) -#define EEARH _SFR_IO8(0x22) - -#define EEPR _SFR_IO8(0x23) -#define EEAP0 0 -#define EEAP1 1 -#define EEAP2 2 -#define EEAP3 3 - -#define EECCR _SFR_IO8(0x24) -#define EEL0 0 -#define EEL1 1 -#define EEL2 2 -#define EEL3 3 - -#define EECR2 _SFR_IO8(0x25) -#define EEBRE 0 -#define EEPAGE 1 - -#define PCICR _SFR_IO8(0x26) -#define PCIE0 0 -#define PCIE1 1 - -#define EIMSK _SFR_IO8(0x27) -#define INT0 0 - -#define TMDR _SFR_IO8(0x28) - -#define AESDR _SFR_IO8(0x29) - -#define AESKR _SFR_IO8(0x2A) -#define AESKR0 0 -#define AESKR1 1 -#define AESKR2 2 -#define AESKR3 3 -#define AESKR4 4 -#define AESKR5 5 -#define AESKR6 6 -#define AESKR7 7 - -#define VMCR _SFR_IO8(0x2B) -#define VMLS0 0 -#define VMLS1 1 -#define VMLS2 2 -#define VMLS3 3 -#define VMIM 4 -#define VMPS 5 -#define BODPD 6 -#define BODLS 7 - -#define SPCR _SFR_IO8(0x2C) -#define SPR0 0 -#define SPR1 1 -#define CPHA 2 -#define CPOL 3 -#define MSTR 4 -#define DORD 5 -#define SPE 6 -#define SPIE 7 - -#define SPSR _SFR_IO8(0x2D) -#define SPI2X 0 -#define WCOL 6 -#define SPIF 7 - -#define SPDR _SFR_IO8(0x2E) - -#define LFCR0 _SFR_IO8(0x2F) -#define LFCE1 0 -#define LFCE2 1 -#define LFCE3 2 -#define LFBRS 3 -#define LFRBS 4 -#define LFMG 5 -#define LFVC0 6 -#define LFVC1 7 - -#define LFCR1 _SFR_IO8(0x30) -#define LFM0 0 -#define LFM1 1 -#define LFFM0 2 -#define LFFM1 3 -#define LFRMS 4 -#define LFRMSA 5 -#define LFQCE 6 -#define LFRE 7 - -/* Reserved [0x31] */ - -#define LFRDB _SFR_IO8(0x32) - -#define SMCR _SFR_IO8(0x33) -#define SE 0 -#define SM0 1 -#define SM1 2 -#define SM2 3 - -#define MCUSR _SFR_IO8(0x34) -#define PORF 0 -#define EXTRF 1 -#define BORF 2 -#define WDRF 3 -#define TPRF 5 - -#define MCUCR _SFR_IO8(0x35) -#define IVCE 0 -#define IVSEL 1 -#define PUD 4 - -#define LFSR _SFR_IO8(0x36) -#define LFES 0 -#define LFSD 1 - -#define SPMCSR _SFR_IO8(0x37) -#define SPMEN 0 -#define PGERS 1 -#define PGWRT 2 -#define BLBSET 3 -#define RWWSRE 4 -#define SIGRD 5 -#define RWWSB 6 -#define SPMIE 7 - -#define T1CR _SFR_IO8(0x38) -#define T1PS0 0 -#define T1PS1 1 -#define T1IE 2 -#define T1CS0 3 -#define T1CS1 4 -#define T1E 7 - -#define T0CR _SFR_IO8(0x39) -#define T0PS0 0 -#define T0PS1 1 -#define T0PS2 2 -#define T0IE 3 -#define T0PR 4 - -/* Reserved [0x3A] */ - -#define CMIMR _SFR_IO8(0x3B) -#define ECIE 0 -#define SXIE 1 -#define RTCIE 2 - -#define CLKPR _SFR_IO8(0x3C) -#define CLKPS0 0 -#define CLKPS1 1 -#define CLKPS2 2 -#define CLTPS0 3 -#define CLTPS1 4 -#define CLTPS2 5 -#define CLKPCE 7 - -/* SP [0x3D..0x3E] */ - -/* SREG [0x3F] */ - -#define WDTCR _SFR_MEM8(0x60) -#define WDPS0 0 -#define WDPS1 1 -#define WDPS2 2 -#define WDE 3 -#define WDCE 4 - -/* Reserved [0x61..0x62] */ - -#define PRR0 _SFR_MEM8(0x63) -#define PRLFR 0 -#define PRT1 1 -#define PRT2 2 -#define PRT3 3 -#define PRTM 4 -#define PRCU 5 -#define PRDS 6 -#define PRVM 7 - -#define __AVR_HAVE_PRR0 ((1< instead of this file." -#endif - -#ifndef _AVR_IOXXX_H_ -# define _AVR_IOXXX_H_ "ioa5795.h" -#else -# error "Attempt to include more than one file." -#endif - -/* Registers and associated bit numbers */ - -#define PINB _SFR_IO8(0x03) -#define PINB7 7 -#define PINB6 6 -#define PINB5 5 -#define PINB4 4 -#define PINB3 3 -#define PINB2 2 -#define PINB1 1 -#define PINB0 0 - -#define DDRB _SFR_IO8(0x04) -#define DDRB7 7 -// Inserted "DDB7" from "DDRB7" due to compatibility -#define DDB7 7 -#define DDRB6 6 -// Inserted "DDB6" from "DDRB6" due to compatibility -#define DDB6 6 -#define DDRB5 5 -// Inserted "DDB5" from "DDRB5" due to compatibility -#define DDB5 5 -#define DDRB4 4 -// Inserted "DDB4" from "DDRB4" due to compatibility -#define DDB4 4 -#define DDRB3 3 -// Inserted "DDB3" from "DDRB3" due to compatibility -#define DDB3 3 -#define DDRB2 2 -// Inserted "DDB2" from "DDRB2" due to compatibility -#define DDB2 2 -#define DDRB1 1 -// Inserted "DDB1" from "DDRB1" due to compatibility -#define DDB1 1 -#define DDRB0 0 -// Inserted "DDB0" from "DDRB0" due to compatibility -#define DDB0 0 - -#define PORTB _SFR_IO8(0x05) -#define PORTB7 7 -#define PORTB6 6 -#define PORTB5 5 -#define PORTB4 4 -#define PORTB3 3 -#define PORTB2 2 -#define PORTB1 1 -#define PORTB0 0 - -#define PINC _SFR_IO8(0x06) -#define PINC4 4 -#define PINC3 3 -#define PINC2 2 -#define PINC1 1 -#define PINC0 0 - -#define DDRC _SFR_IO8(0x07) -#define DDRC4 4 -// Inserted "DDC4" from "DDRC4" due to compatibility -#define DDC4 4 -#define DDRC3 3 -// Inserted "DDC3" from "DDRC3" due to compatibility -#define DDC3 3 -#define DDRC2 2 -// Inserted "DDC2" from "DDRC2" due to compatibility -#define DDC2 2 -#define DDRC1 1 -// Inserted "DDC1" from "DDRC1" due to compatibility -#define DDC1 1 -#define DDRC0 0 -// Inserted "DDC0" from "DDRC0" due to compatibility -#define DDC0 0 - -#define PORTC _SFR_IO8(0x08) -#define PORTC4 4 -#define PORTC3 3 -#define PORTC2 2 -#define PORTC1 1 -#define PORTC0 0 - -#define PIND _SFR_IO8(0x09) -#define PIND7 7 -#define PIND6 6 -#define PIND5 5 -#define PIND4 4 -#define PIND3 3 -#define PIND2 2 -#define PIND1 1 -#define PIND0 0 - -#define DDRD _SFR_IO8(0x0A) -#define DDRD7 7 -// Inserted "DDD7" from "DDRD7" due to compatibility -#define DDD7 7 -#define DDRD6 6 -// Inserted "DDD6" from "DDRD6" due to compatibility -#define DDD6 6 -#define DDRD5 5 -// Inserted "DDD5" from "DDRD5" due to compatibility -#define DDD5 5 -#define DDRD4 4 -// Inserted "DDD4" from "DDRD4" due to compatibility -#define DDD4 4 -#define DDRD3 3 -// Inserted "DDD3" from "DDRD3" due to compatibility -#define DDD3 3 -#define DDRD2 2 -// Inserted "DDD2" from "DDRD2" due to compatibility -#define DDD2 2 -#define DDRD1 1 -// Inserted "DDD1" from "DDRD1" due to compatibility -#define DDD1 1 -#define DDRD0 0 -// Inserted "DDD0" from "DDRD0" due to compatibility -#define DDD0 0 - -#define PORTD _SFR_IO8(0x0B) -#define PORTD7 7 -#define PORTD6 6 -#define PORTD5 5 -#define PORTD4 4 -#define PORTD3 3 -#define PORTD2 2 -#define PORTD1 1 -#define PORTD0 0 - -/* Reserved [0x0C] */ - -#define TPCR _SFR_IO8(0x0D) -#define TPMA 0 -#define TPMOD 1 -#define TPMS0 2 -#define TPMS1 3 -#define TPMD0 4 -#define TPMD1 5 -#define TPPSD 6 -#define TPD 7 - -#define TPFR _SFR_IO8(0x0E) -#define TPF 0 -#define TPA 1 -#define TPGAP 2 -#define TPPSW 3 - -#define CMCR _SFR_IO8(0x0F) -#define CMM0 0 -#define CMM1 1 -#define SRCD 2 -#define CO32D 3 -#define CCS 4 -#define ECINS 5 -#define CMONEN 6 -#define CMCCE 7 - -#define CMSR _SFR_IO8(0x10) -#define ECF 0 -#define SXF 1 -#define RTCF 2 - -#define T2CR _SFR_IO8(0x11) -#define T2OTM 0 -#define T2CTM 1 -#define T2CRM 2 -#define T2GRM 3 -#define T2TOP 4 -#define T2RES 5 -#define T2TS 6 -#define T2E 7 - -#define T3CR _SFR_IO8(0x12) -#define T3OTM 0 -#define T3CTM 1 -#define T3CRM 2 -#define T3CPRM 3 -#define T3TOP 4 -#define T3RES 5 -#define T3CPTM 6 -#define T3E 7 - -#define AESCR _SFR_IO8(0x13) -#define AESWK 0 -#define AESWD 1 -#define AESIM 2 -#define AESD 3 -#define AESXOR 4 -#define AESRES 5 -#define AESE 7 - -#define AESSR _SFR_IO8(0x14) -#define AESRF 0 -#define AESERF 7 - -#define TMIFR _SFR_IO8(0x15) -#define TMRXF 0 -#define TMTXF 1 -#define TMTCF 2 -#define TMRXS 3 -#define TMTXS 4 - -#define VMSR _SFR_IO8(0x16) -#define VMF 0 - -#define PCIFR _SFR_IO8(0x17) -#define PCIF0 0 -#define PCIF1 1 - -/* Reserved [0x18] */ - -#define T0IFR _SFR_IO8(0x19) -#define T0F 0 - -#define T1IFR _SFR_IO8(0x1A) -#define T1F 0 - -#define T2IFR _SFR_IO8(0x1B) -#define T2OFF 0 -#define T2COF 1 - -#define T3IFR _SFR_IO8(0x1C) -#define T3OFF 0 -#define T3COF 1 -#define T3ICF 2 - -#define EIFR _SFR_IO8(0x1D) -#define INTF0 0 - -#define GPIOR0 _SFR_IO8(0x1E) - -#define EECR _SFR_IO8(0x1F) -#define EERE 0 -#define EEWE 1 -#define EEMWE 2 -#define EERIE 3 -#define EEPM0 4 -#define EEPM1 5 -#define EELP 6 - -#define EEDR _SFR_IO8(0x20) - -/* Combine EEARL and EEARH */ -#define EEAR _SFR_IO16(0x21) - -#define EEARL _SFR_IO8(0x21) -#define EEARH _SFR_IO8(0x22) - -#define EEPR _SFR_IO8(0x23) -#define EEAP0 0 -#define EEAP1 1 -#define EEAP2 2 -#define EEAP3 3 - -#define EECCR _SFR_IO8(0x24) -#define EEL0 0 -#define EEL1 1 -#define EEL2 2 -#define EEL3 3 - -/* Reserved [0x25] */ - -#define PCICR _SFR_IO8(0x26) -#define PCIE0 0 -#define PCIE1 1 - -#define EIMSK _SFR_IO8(0x27) -#define INT0 0 - -#define TMDR _SFR_IO8(0x28) - -#define AESDR _SFR_IO8(0x29) - -#define AESKR _SFR_IO8(0x2A) -#define AESKR0 0 -#define AESKR1 1 -#define AESKR2 2 -#define AESKR3 3 -#define AESKR4 4 -#define AESKR5 5 -#define AESKR6 6 -#define AESKR7 7 - -#define VMCR _SFR_IO8(0x2B) -#define VMLS0 0 -#define VMLS1 1 -#define VMLS2 2 -#define VMLS3 3 -#define VMIM 4 -#define VMPS 5 -#define BODPD 6 -#define BODLS 7 - -#define SPCR _SFR_IO8(0x2C) -#define SPR0 0 -#define SPR1 1 -#define CPHA 2 -#define CPOL 3 -#define MSTR 4 -#define DORD 5 -#define SPE 6 -#define SPIE 7 - -#define SPSR _SFR_IO8(0x2D) -#define SPI2X 0 -#define WCOL 6 -#define SPIF 7 - -#define SPDR _SFR_IO8(0x2E) - -/* Reserved [0x2F..0x32] */ - -#define SMCR _SFR_IO8(0x33) -#define SE 0 -#define SM0 1 -#define SM1 2 -#define SM2 3 - -#define MCUSR _SFR_IO8(0x34) -#define PORF 0 -#define EXTRF 1 -#define BORF 2 -#define WDRF 3 -#define TPRF 5 - -#define MCUCR _SFR_IO8(0x35) -#define IVCE 0 -#define IVSEL 1 -#define PUD 4 - -/* Reserved [0x36] */ - -#define SPMCSR _SFR_IO8(0x37) -#define SPMEN 0 -#define PGERS 1 -#define PGWRT 2 -#define BLBSET 3 -#define RWWSRE 4 -#define SIGRD 5 -#define RWWSB 6 -#define SPMIE 7 - -#define T1CR _SFR_IO8(0x38) -#define T1PS0 0 -#define T1PS1 1 -#define T1IE 2 -#define T1CS0 3 -#define T1CS1 4 -#define T1E 7 - -#define T0CR _SFR_IO8(0x39) -#define T0PS0 0 -#define T0PS1 1 -#define T0PS2 2 -#define T0IE 3 -#define T0PR 4 - -/* Reserved [0x3A] */ - -#define CMIMR _SFR_IO8(0x3B) -#define ECIE 0 -#define SXIE 1 -#define RTCIE 2 - -#define CLKPR _SFR_IO8(0x3C) -#define CLKPS0 0 -#define CLKPS1 1 -#define CLKPS2 2 -#define CLTPS0 3 -#define CLTPS1 4 -#define CLTPS2 5 -#define CLKPCE 7 - -/* SP [0x3D..0x3E] */ - -/* SREG [0x3F] */ - -#define WDTCR _SFR_MEM8(0x60) -#define WDPS0 0 -#define WDPS1 1 -#define WDPS2 2 -#define WDE 3 -#define WDCE 4 - -/* Reserved [0x61..0x62] */ - -#define PRR0 _SFR_MEM8(0x63) -#define PRT1 1 -#define PRT2 2 -#define PRT3 3 -#define PRTM 4 -#define PRCU 5 -#define PRDS 6 -#define PRVM 7 - -#define __AVR_HAVE_PRR0 ((1< instead of this file." -#endif - -#ifndef _AVR_IOXXX_H_ -# define _AVR_IOXXX_H_ "ioa5831.h" -#else -# error "Attempt to include more than one file." -#endif - -/* Registers and associated bit numbers */ - -#define PRR0 _SFR_IO8(0x01) -#define PRSPI 0 -#define PRRXDC 1 -#define PRTXDC 2 -#define PRCRC 3 -#define PRVM 4 -#define PRCO 5 - -#define __AVR_HAVE_PRR0 ((1< instead of this file." -#endif - -#ifndef _AVR_IOXXX_H_ -# define _AVR_IOXXX_H_ "ioa6285.h" -#else -# error "Attempt to include more than one file." -#endif - -/* Registers and associated bit numbers */ - -#define PINB _SFR_IO8(0x03) -#define PINB7 7 -#define PINB6 6 -#define PINB5 5 -#define PINB4 4 -#define PINB3 3 -#define PINB2 2 -#define PINB1 1 -#define PINB0 0 - -#define DDRB _SFR_IO8(0x04) -#define DDRB7 7 -// Inserted "DDB7" from "DDRB7" due to compatibility -#define DDB7 7 -#define DDRB6 6 -// Inserted "DDB6" from "DDRB6" due to compatibility -#define DDB6 6 -#define DDRB5 5 -// Inserted "DDB5" from "DDRB5" due to compatibility -#define DDB5 5 -#define DDRB4 4 -// Inserted "DDB4" from "DDRB4" due to compatibility -#define DDB4 4 -#define DDRB3 3 -// Inserted "DDB3" from "DDRB3" due to compatibility -#define DDB3 3 -#define DDRB2 2 -// Inserted "DDB2" from "DDRB2" due to compatibility -#define DDB2 2 -#define DDRB1 1 -// Inserted "DDB1" from "DDRB1" due to compatibility -#define DDB1 1 -#define DDRB0 0 -// Inserted "DDB0" from "DDRB0" due to compatibility -#define DDB0 0 - -#define PORTB _SFR_IO8(0x05) -#define PORTB7 7 -#define PORTB6 6 -#define PORTB5 5 -#define PORTB4 4 -#define PORTB3 3 -#define PORTB2 2 -#define PORTB1 1 -#define PORTB0 0 - -#define PINC _SFR_IO8(0x06) -#define PINC2 2 -#define PINC1 1 -#define PINC0 0 - -#define DDRC _SFR_IO8(0x07) -#define DDRC2 2 -// Inserted "DDC2" from "DDRC2" due to compatibility -#define DDC2 2 -#define DDRC1 1 -// Inserted "DDC1" from "DDRC1" due to compatibility -#define DDC1 1 -#define DDRC0 0 -// Inserted "DDC0" from "DDRC0" due to compatibility -#define DDC0 0 - -#define PORTC _SFR_IO8(0x08) -#define PORTC2 2 -#define PORTC1 1 -#define PORTC0 0 - -#define PIND _SFR_IO8(0x09) -#define PIND7 7 -#define PIND6 6 -#define PIND5 5 -#define PIND4 4 -#define PIND3 3 -#define PIND2 2 -#define PIND1 1 -#define PIND0 0 - -#define DDRD _SFR_IO8(0x0A) -#define DDRD7 7 -// Inserted "DDD7" from "DDRD7" due to compatibility -#define DDD7 7 -#define DDRD6 6 -// Inserted "DDD6" from "DDRD6" due to compatibility -#define DDD6 6 -#define DDRD5 5 -// Inserted "DDD5" from "DDRD5" due to compatibility -#define DDD5 5 -#define DDRD4 4 -// Inserted "DDD4" from "DDRD4" due to compatibility -#define DDD4 4 -#define DDRD3 3 -// Inserted "DDD3" from "DDRD3" due to compatibility -#define DDD3 3 -#define DDRD2 2 -// Inserted "DDD2" from "DDRD2" due to compatibility -#define DDD2 2 -#define DDRD1 1 -// Inserted "DDD1" from "DDRD1" due to compatibility -#define DDD1 1 -#define DDRD0 0 -// Inserted "DDD0" from "DDRD0" due to compatibility -#define DDD0 0 - -#define PORTD _SFR_IO8(0x0B) -#define PORTD7 7 -#define PORTD6 6 -#define PORTD5 5 -#define PORTD4 4 -#define PORTD3 3 -#define PORTD2 2 -#define PORTD1 1 -#define PORTD0 0 - -/* Reserved [0x0C..0x0E] */ - -#define CMCR _SFR_IO8(0x0F) -#define CMM0 0 -#define CMM1 1 -#define SRCD 2 -#define CMONEN 3 -#define CCS 4 -#define ECINS 5 -#define CMCCE 7 - -#define CMSR _SFR_IO8(0x10) -#define ECF 0 - -#define T2CRA _SFR_IO8(0x11) -#define T2OTM 0 -#define T2CTM 1 -#define T2CR 2 -#define T2CRM 3 -#define T2ICS 5 -#define T2TS 6 -#define T2E 7 - -#define T2CRB _SFR_IO8(0x12) -#define T2SCE 0 - -/* Reserved [0x13] */ - -#define T3CRA _SFR_IO8(0x14) -#define T3AC 0 -#define T3SCE 1 -#define T3CR 2 -#define T3TS 6 -#define T3E 7 - -/* Reserved [0x15] */ - -#define VMCSR _SFR_IO8(0x16) -#define VMEN 0 -#define VMLS0 1 -#define VMLS1 2 -#define VMLS2 3 -#define VMIM 4 -#define VMF 5 -#define BODPD 6 -#define BODLS 7 - -#define PCIFR _SFR_IO8(0x17) -#define PCIF0 0 -#define PCIF1 1 -#define PCIF2 2 - -#define LFFR _SFR_IO8(0x18) -#define LFWPF 0 -#define LFBF 1 -#define LFEDF 2 -#define LFRF 3 - -#define SSFR _SFR_IO8(0x19) -#define MSENF 0 -#define MSENO 1 - -#define T10IFR _SFR_IO8(0x1A) -#define T0F 0 -#define T1F 1 - -#define T2IFR _SFR_IO8(0x1B) -#define T2OFF 0 -#define T2COF 1 -#define T2ICF 2 -#define T2RXF 3 -#define T2TXF 4 -#define T2TCF 5 - -#define T3IFR _SFR_IO8(0x1C) -#define T3OFF 0 -#define T3COAF 1 -#define T3COBF 2 -#define T3ICF 3 - -#define EIFR _SFR_IO8(0x1D) -#define INTF0 0 -#define INTF1 1 - -#define GPIOR0 _SFR_IO8(0x1E) - -#define EECR _SFR_IO8(0x1F) -#define EERE 0 -#define EEWE 1 -#define EEMWE 2 -#define EERIE 3 -#define EEPM0 4 -#define EEPM1 5 - -#define EEDR _SFR_IO8(0x20) - -/* Combine EEARL and EEARH */ -#define EEAR _SFR_IO16(0x21) - -#define EEARL _SFR_IO8(0x21) -#define EEARH _SFR_IO8(0x22) - -#define PCICR _SFR_IO8(0x23) -#define PCIE0 0 -#define PCIE1 1 -#define PCIE2 2 - -#define EIMSK _SFR_IO8(0x24) -#define INT0 0 -#define INT1 1 - -/* Reserved [0x25..0x26] */ - -#define SVCR _SFR_IO8(0x27) - -#define SCR _SFR_IO8(0x28) -#define SMS 0 -#define SEN0 1 -#define SEN1 2 -#define SMEN 3 - -#define SCCR _SFR_IO8(0x29) -#define SRCC0 0 -#define SRCC1 1 -#define SCCS0 2 -#define SCCS1 3 -#define SCCS2 4 - -#define GPIOR1 _SFR_IO8(0x2A) - -#define GPIOR2 _SFR_IO8(0x2B) - -#define SPCR _SFR_IO8(0x2C) -#define SPR0 0 -#define SPR1 1 -#define CPHA 2 -#define CPOL 3 -#define MSTR 4 -#define DORD 5 -#define SPE 6 -#define SPIE 7 - -#define SPSR _SFR_IO8(0x2D) -#define SPI2X 0 -#define WCOL 6 -#define SPIF 7 - -#define SPDR _SFR_IO8(0x2E) - -#define T2MDR _SFR_IO8(0x2F) - -#define LFRR _SFR_IO8(0x30) - -/* Reserved [0x31] */ - -#define LFCDR _SFR_IO8(0x32) -#define LFDO 0 -#define LFRST 6 -#define LFSCE 7 - -#define SMCR _SFR_IO8(0x33) -#define SE 0 -#define SM0 1 -#define SM1 2 -#define SM2 3 - -#define MCUSR _SFR_IO8(0x34) -#define PORF 0 -#define EXTRF 1 -#define BORF 2 -#define WDRF 3 -#define TSRF 5 - -#define MCUCR _SFR_IO8(0x35) -#define IVCE 0 -#define IVSEL 1 -#define PUD 4 - -#define LFRB _SFR_IO8(0x36) - -#define SPMCSR _SFR_IO8(0x37) -#define SELFPRGEN 0 -#define PGERS 1 -#define PGWRT 2 -#define BLBSET 3 -#define RWWSRE 4 -#define RWWSB 6 -#define SPMIE 7 - -#define T1CR _SFR_IO8(0x38) -#define T1PS0 0 -#define T1PS1 1 -#define T1PS2 2 -#define T1CS0 3 -#define T1CS1 4 -#define T1CS2 5 -#define T1IE 7 - -#define T0CR _SFR_IO8(0x39) -#define T0PAS0 0 -#define T0PAS1 1 -#define T0PAS2 2 -#define T0IE 3 -#define T0PR 4 -#define T0PBS0 5 -#define T0PBS1 6 -#define T0PBS2 7 - -/* Reserved [0x3A] */ - -#define CMIMR _SFR_IO8(0x3B) -#define ECIE 0 - -#define CLKPR _SFR_IO8(0x3C) -#define CLKPS0 0 -#define CLKPS1 1 -#define CLKPS2 2 -#define CLTPS0 3 -#define CLTPS1 4 -#define CLTPS2 5 -#define CLPCE 7 - -/* SP [0x3D..0x3E] */ - -/* SREG [0x3F] */ - -#define WDTCR _SFR_MEM8(0x60) -#define WDPS0 0 -#define WDPS1 1 -#define WDPS2 2 -#define WDE 3 -#define WDCE 4 - -#define SIMSK _SFR_MEM8(0x61) -#define MSIE 0 - -/* Reserved [0x62..0x63] */ - -#define TSCR _SFR_MEM8(0x64) -#define TSSD 0 - -#define SRCCAL _SFR_MEM8(0x65) - -#define FRCCAL _SFR_MEM8(0x66) - -#define MSVCAL _SFR_MEM8(0x67) - -/* Reserved [0x68] */ - -#define EICRA _SFR_MEM8(0x69) -#define ISC00 0 -#define ISC01 1 -#define ISC10 2 -#define ISC11 3 - -#define PCMSK0 _SFR_MEM8(0x6A) -#define PCINT0 0 -#define PCINT1 1 -#define PCINT2 2 -#define PCINT3 3 -#define PCINT4 4 -#define PCINT5 5 -#define PCINT6 6 -#define PCINT7 7 - -#define PCMSK1 _SFR_MEM8(0x6B) -#define PCINT8 0 -#define PCINT9 1 -#define PCINT10 2 - -#define PCMSK2 _SFR_MEM8(0x6C) -#define PCINT16 0 -#define PCINT17 1 -#define PCINT18 2 -#define PCINT19 3 -#define PCINT20 4 -#define PCINT21 5 -#define PCINT22 6 -#define PCINT23 7 - -/* Reserved [0x6D] */ - -#define T2ICRL _SFR_MEM8(0x6E) - -#define T2ICR _SFR_MEM8(0x6F) - -/* Combine T2CORL and T2CORH */ -#define T2COR _SFR_MEM16(0x70) - -#define T2CORL _SFR_MEM8(0x70) -#define T2CORH _SFR_MEM8(0x71) - -#define T2MRA _SFR_MEM8(0x72) -#define T2CS0 0 -#define T2CS1 1 -#define T2CS2 2 -#define T2CE0 3 -#define T2CE1 4 -#define T2CNC 5 -#define T2TP0 6 -#define T2TP1 7 - -#define T2MRB _SFR_MEM8(0x73) -#define T2M0 0 -#define T2M1 1 -#define T2M2 2 -#define T2M3 3 -#define T2TOP 4 -#define T2CPOL 6 -#define T2SSIE 7 - -#define T2IMR _SFR_MEM8(0x74) -#define T2OIM 0 -#define T2CIM 1 -#define T2CPIM 2 -#define T2RXIM 3 -#define T2TXIM 4 -#define T2TCIM 5 - -/* Reserved [0x75] */ - -/* Combine T3ICRL and T3ICRH */ -#define T3ICR _SFR_MEM16(0x76) - -#define T3ICRL _SFR_MEM8(0x76) -#define T3ICRH _SFR_MEM8(0x77) - -/* Combine T3CORAL and T3CORAH */ -#define T3CORA _SFR_MEM16(0x78) - -#define T3CORAL _SFR_MEM8(0x78) -#define T3CORAH _SFR_MEM8(0x79) - -/* Combine T3CORBL and T3CORBH */ -#define T3CORB _SFR_MEM16(0x7A) - -#define T3CORBL _SFR_MEM8(0x7A) -#define T3CORBH _SFR_MEM8(0x7B) - -#define T3MRA _SFR_MEM8(0x7C) -#define T3CS0 0 -#define T3CS1 1 -#define T3CS2 2 -#define T3CE0 3 -#define T3CE1 4 -#define T3CNC 5 -#define T3ICS0 6 -#define T3ICS1 7 - -#define T3MRB _SFR_MEM8(0x7D) -#define T3M0 0 -#define T3M1 1 -#define T3M2 2 -#define T3TOP 4 - -#define T3CRB _SFR_MEM8(0x7E) -#define T3CTMA 0 -#define T3SAMA 1 -#define T3CRMA 2 -#define T3CTMB 3 -#define T3SAMB 4 -#define T3CRMB 5 -#define T3CPRM 6 - -#define T3IMR _SFR_MEM8(0x7F) -#define T3OIM 0 -#define T3CAIM 1 -#define T3CBIM 2 -#define T3CPIM 3 - -/* Reserved [0x80] */ - -#define LFIMR _SFR_MEM8(0x81) -#define LFWIM 0 -#define LFBIM 1 -#define LFEIM 2 - -#define LFRCR _SFR_MEM8(0x82) -#define LFEN 0 -#define LFBM 1 -#define LFWM0 2 -#define LFWM1 3 -#define LFRSS 4 -#define LFCS0 5 -#define LFCS1 6 -#define LFCS2 7 - -#define LFHCR _SFR_MEM8(0x83) - -/* Combine LFIDCL and LFIDCH */ -#define LFIDC _SFR_MEM16(0x84) - -#define LFIDCL _SFR_MEM8(0x84) -#define LFIDCH _SFR_MEM8(0x85) - -/* Combine LFCALL and LFCALH */ -#define LFCAL _SFR_MEM16(0x86) - -#define LFCALL _SFR_MEM8(0x86) -#define LFCALH _SFR_MEM8(0x87) - - - -/* Values and associated defines */ - - -#define SLEEP_MODE_IDLE (0x00<<1) -#define SLEEP_MODE_SENSOR_NOISE_REDUCTION (0x01<<1) -#define SLEEP_MODE_PWR_DOWN (0x02<<1) - -/* Interrupt vectors */ -/* Vector 0 is the reset vector */ -/* External Interrupt Request 0 */ -#define INT0_vect _VECTOR(1) -#define INT0_vect_num 1 - -/* External Interrupt Request 1 */ -#define INT1_vect _VECTOR(2) -#define INT1_vect_num 2 - -/* Pin Change Interrupt Request 0 */ -#define PCINT0_vect _VECTOR(3) -#define PCINT0_vect_num 3 - -/* Pin Change Interrupt Request 1 */ -#define PCINT1_vect _VECTOR(4) -#define PCINT1_vect_num 4 - -/* Pin Change Interrupt Request 2 */ -#define PCINT2_vect _VECTOR(5) -#define PCINT2_vect_num 5 - -/* Voltage Monitor Interrupt */ -#define INTVM_vect _VECTOR(6) -#define INTVM_vect_num 6 - -/* Sensor Interface Interrupt */ -#define SENINT_vect _VECTOR(7) -#define SENINT_vect_num 7 - -/* Timer0 Interval Interrupt */ -#define INTT0_vect _VECTOR(8) -#define INTT0_vect_num 8 - -/* LF-Receiver Wake-up Interrupt */ -#define LFWP_vect _VECTOR(9) -#define LFWP_vect_num 9 - -/* Timer/Counter3 Capture Event */ -#define T3CAP_vect _VECTOR(10) -#define T3CAP_vect_num 10 - -/* Timer/Counter3 Compare Match A */ -#define T3COMA_vect _VECTOR(11) -#define T3COMA_vect_num 11 - -/* Timer/Counter3 Compare Match B */ -#define T3COMB_vect _VECTOR(12) -#define T3COMB_vect_num 12 - -/* Timer/Counter3 Overflow */ -#define T3OVF_vect _VECTOR(13) -#define T3OVF_vect_num 13 - -/* Timer/Counter2 Capture Event */ -#define T2CAP_vect _VECTOR(14) -#define T2CAP_vect_num 14 - -/* Timer/Counter2 Compare Match */ -#define T2COM_vect _VECTOR(15) -#define T2COM_vect_num 15 - -/* Timer/Counter2 Overflow */ -#define T2OVF_vect _VECTOR(16) -#define T2OVF_vect_num 16 - -/* SPI Serial Transfer Complete */ -#define SPISTC_vect _VECTOR(17) -#define SPISTC_vect_num 17 - -/* LF Receive Buffer Interrupt */ -#define LFRXB_vect _VECTOR(18) -#define LFRXB_vect_num 18 - -/* Timer1 Interval Interrupt */ -#define INTT1_vect _VECTOR(19) -#define INTT1_vect_num 19 - -/* Timer2 SSI Receive Buffer Interrupt */ -#define T2RXB_vect _VECTOR(20) -#define T2RXB_vect_num 20 - -/* Timer2 SSI Transmit Buffer Interrupt */ -#define T2TXB_vect _VECTOR(21) -#define T2TXB_vect_num 21 - -/* Timer2 SSI Transmit Complete Interrupt */ -#define T2TXC_vect _VECTOR(22) -#define T2TXC_vect_num 22 - -/* LF-Receiver End of Burst Interrupt */ -#define LFREOB_vect _VECTOR(23) -#define LFREOB_vect_num 23 - -/* External Input Clock break down Interrupt */ -#define EXCM_vect _VECTOR(24) -#define EXCM_vect_num 24 - -/* EEPROM Ready Interrupt */ -#define EEREADY_vect _VECTOR(25) -#define EEREADY_vect_num 25 - -/* Store Program Memory Ready */ -#define SPM_RDY_vect _VECTOR(26) -#define SPM_RDY_vect_num 26 - -#define _VECTORS_SIZE 54 - - -/* Constants */ - -#define SPM_PAGESIZE 64 -#define FLASHSTART 0x0000 -#define FLASHEND 0x1FFF -#define RAMSTART 0x0100 -#define RAMSIZE 512 -#define RAMEND 0x02FF -#define E2START 0 -#define E2SIZE 320 -#define E2PAGESIZE 4 -#define E2END 0x013F -#define XRAMEND RAMEND - - -/* Fuses */ - -#define FUSE_MEMORY_SIZE 2 - -/* Low Fuse Byte */ -#define FUSE_TSRDI (unsigned char)~_BV(0) -#define FUSE_BODEN (unsigned char)~_BV(1) -#define FUSE_FRCFS (unsigned char)~_BV(2) -#define FUSE_WDRCON (unsigned char)~_BV(3) -#define FUSE_SUT_CKSEL0 (unsigned char)~_BV(4) -#define FUSE_SUT_CKSEL1 (unsigned char)~_BV(5) -#define FUSE_CKOUT (unsigned char)~_BV(6) -#define FUSE_CKDIV8 (unsigned char)~_BV(7) -#define LFUSE_DEFAULT (FUSE_BODEN & FUSE_FRCFS & FUSE_WDRCON & FUSE_SUT_CKSEL0 & FUSE_CKDIV8) - - -/* High Fuse Byte */ -#define FUSE_BOOTRST (unsigned char)~_BV(0) -#define FUSE_BOOTSZ0 (unsigned char)~_BV(1) -#define FUSE_BOOTSZ1 (unsigned char)~_BV(2) -#define FUSE_EESAVE (unsigned char)~_BV(3) -#define FUSE_WDTON (unsigned char)~_BV(4) -#define FUSE_SPIEN (unsigned char)~_BV(5) -#define FUSE_DWEN (unsigned char)~_BV(6) -#define FUSE_EELOCK (unsigned char)~_BV(7) -#define HFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_SPIEN) - - - -/* Lock Bits */ -#define __LOCK_BITS_EXIST -#define __BOOT_LOCK_BITS_0_EXIST -#define __BOOT_LOCK_BITS_1_EXIST - - -/* Signature */ -#define SIGNATURE_0 0x1E -#define SIGNATURE_1 0x93 -#define SIGNATURE_2 0x82 - - -#endif /* #ifdef _AVR_ATA6285_H_INCLUDED */ - diff --git a/arduino/hardware/tools/avr/avr/include/avr/ioa6286.h b/arduino/hardware/tools/avr/avr/include/avr/ioa6286.h deleted file mode 100644 index b4837d4..0000000 --- a/arduino/hardware/tools/avr/avr/include/avr/ioa6286.h +++ /dev/null @@ -1,740 +0,0 @@ -/***************************************************************************** - * - * Copyright (C) 2015 Atmel Corporation - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * - * * Neither the name of the copyright holders nor the names of - * contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - ****************************************************************************/ - - -#ifndef _AVR_ATA6286_H_INCLUDED -#define _AVR_ATA6286_H_INCLUDED - - -#ifndef _AVR_IO_H_ -# error "Include instead of this file." -#endif - -#ifndef _AVR_IOXXX_H_ -# define _AVR_IOXXX_H_ "ioa6286.h" -#else -# error "Attempt to include more than one file." -#endif - -/* Registers and associated bit numbers */ - -#define PINB _SFR_IO8(0x03) -#define PINB7 7 -#define PINB6 6 -#define PINB5 5 -#define PINB4 4 -#define PINB3 3 -#define PINB2 2 -#define PINB1 1 -#define PINB0 0 - -#define DDRB _SFR_IO8(0x04) -#define DDRB7 7 -// Inserted "DDB7" from "DDRB7" due to compatibility -#define DDB7 7 -#define DDRB6 6 -// Inserted "DDB6" from "DDRB6" due to compatibility -#define DDB6 6 -#define DDRB5 5 -// Inserted "DDB5" from "DDRB5" due to compatibility -#define DDB5 5 -#define DDRB4 4 -// Inserted "DDB4" from "DDRB4" due to compatibility -#define DDB4 4 -#define DDRB3 3 -// Inserted "DDB3" from "DDRB3" due to compatibility -#define DDB3 3 -#define DDRB2 2 -// Inserted "DDB2" from "DDRB2" due to compatibility -#define DDB2 2 -#define DDRB1 1 -// Inserted "DDB1" from "DDRB1" due to compatibility -#define DDB1 1 -#define DDRB0 0 -// Inserted "DDB0" from "DDRB0" due to compatibility -#define DDB0 0 - -#define PORTB _SFR_IO8(0x05) -#define PORTB7 7 -#define PORTB6 6 -#define PORTB5 5 -#define PORTB4 4 -#define PORTB3 3 -#define PORTB2 2 -#define PORTB1 1 -#define PORTB0 0 - -#define PINC _SFR_IO8(0x06) -#define PINC2 2 -#define PINC1 1 -#define PINC0 0 - -#define DDRC _SFR_IO8(0x07) -#define DDRC2 2 -// Inserted "DDC2" from "DDRC2" due to compatibility -#define DDC2 2 -#define DDRC1 1 -// Inserted "DDC1" from "DDRC1" due to compatibility -#define DDC1 1 -#define DDRC0 0 -// Inserted "DDC0" from "DDRC0" due to compatibility -#define DDC0 0 - -#define PORTC _SFR_IO8(0x08) -#define PORTC2 2 -#define PORTC1 1 -#define PORTC0 0 - -#define PIND _SFR_IO8(0x09) -#define PIND7 7 -#define PIND6 6 -#define PIND5 5 -#define PIND4 4 -#define PIND3 3 -#define PIND2 2 -#define PIND1 1 -#define PIND0 0 - -#define DDRD _SFR_IO8(0x0A) -#define DDRD7 7 -// Inserted "DDD7" from "DDRD7" due to compatibility -#define DDD7 7 -#define DDRD6 6 -// Inserted "DDD6" from "DDRD6" due to compatibility -#define DDD6 6 -#define DDRD5 5 -// Inserted "DDD5" from "DDRD5" due to compatibility -#define DDD5 5 -#define DDRD4 4 -// Inserted "DDD4" from "DDRD4" due to compatibility -#define DDD4 4 -#define DDRD3 3 -// Inserted "DDD3" from "DDRD3" due to compatibility -#define DDD3 3 -#define DDRD2 2 -// Inserted "DDD2" from "DDRD2" due to compatibility -#define DDD2 2 -#define DDRD1 1 -// Inserted "DDD1" from "DDRD1" due to compatibility -#define DDD1 1 -#define DDRD0 0 -// Inserted "DDD0" from "DDRD0" due to compatibility -#define DDD0 0 - -#define PORTD _SFR_IO8(0x0B) -#define PORTD7 7 -#define PORTD6 6 -#define PORTD5 5 -#define PORTD4 4 -#define PORTD3 3 -#define PORTD2 2 -#define PORTD1 1 -#define PORTD0 0 - -/* Reserved [0x0C..0x0E] */ - -#define CMCR _SFR_IO8(0x0F) -#define CMM0 0 -#define CMM1 1 -#define SRCD 2 -#define CMONEN 3 -#define CCS 4 -#define ECINS 5 -#define CMCCE 7 - -#define CMSR _SFR_IO8(0x10) -#define ECF 0 - -#define T2CRA _SFR_IO8(0x11) -#define T2OTM 0 -#define T2CTM 1 -#define T2CR 2 -#define T2CRM 3 -#define T2ICS 5 -#define T2TS 6 -#define T2E 7 - -#define T2CRB _SFR_IO8(0x12) -#define T2SCE 0 - -/* Reserved [0x13] */ - -#define T3CRA _SFR_IO8(0x14) -#define T3AC 0 -#define T3SCE 1 -#define T3CR 2 -#define T3TS 6 -#define T3E 7 - -/* Reserved [0x15] */ - -#define VMCSR _SFR_IO8(0x16) -#define VMEN 0 -#define VMLS0 1 -#define VMLS1 2 -#define VMLS2 3 -#define VMIM 4 -#define VMF 5 -#define BODPD 6 -#define BODLS 7 - -#define PCIFR _SFR_IO8(0x17) -#define PCIF0 0 -#define PCIF1 1 -#define PCIF2 2 - -#define LFFR _SFR_IO8(0x18) -#define LFWPF 0 -#define LFBF 1 -#define LFEDF 2 -#define LFRF 3 - -#define SSFR _SFR_IO8(0x19) -#define MSENF 0 -#define MSENO 1 - -#define T10IFR _SFR_IO8(0x1A) -#define T0F 0 -#define T1F 1 - -#define T2IFR _SFR_IO8(0x1B) -#define T2OFF 0 -#define T2COF 1 -#define T2ICF 2 -#define T2RXF 3 -#define T2TXF 4 -#define T2TCF 5 - -#define T3IFR _SFR_IO8(0x1C) -#define T3OFF 0 -#define T3COAF 1 -#define T3COBF 2 -#define T3ICF 3 - -#define EIFR _SFR_IO8(0x1D) -#define INTF0 0 -#define INTF1 1 - -#define GPIOR0 _SFR_IO8(0x1E) - -#define EECR _SFR_IO8(0x1F) -#define EERE 0 -#define EEWE 1 -#define EEMWE 2 -#define EERIE 3 -#define EEPM0 4 -#define EEPM1 5 - -#define EEDR _SFR_IO8(0x20) - -/* Combine EEARL and EEARH */ -#define EEAR _SFR_IO16(0x21) - -#define EEARL _SFR_IO8(0x21) -#define EEARH _SFR_IO8(0x22) - -#define PCICR _SFR_IO8(0x23) -#define PCIE0 0 -#define PCIE1 1 -#define PCIE2 2 - -#define EIMSK _SFR_IO8(0x24) -#define INT0 0 -#define INT1 1 - -/* Reserved [0x25..0x26] */ - -#define SVCR _SFR_IO8(0x27) - -#define SCR _SFR_IO8(0x28) -#define SMS 0 -#define SEN0 1 -#define SEN1 2 -#define SMEN 3 - -#define SCCR _SFR_IO8(0x29) -#define SRCC0 0 -#define SRCC1 1 -#define SCCS0 2 -#define SCCS1 3 -#define SCCS2 4 - -#define GPIOR1 _SFR_IO8(0x2A) - -#define GPIOR2 _SFR_IO8(0x2B) - -#define SPCR _SFR_IO8(0x2C) -#define SPR0 0 -#define SPR1 1 -#define CPHA 2 -#define CPOL 3 -#define MSTR 4 -#define DORD 5 -#define SPE 6 -#define SPIE 7 - -#define SPSR _SFR_IO8(0x2D) -#define SPI2X 0 -#define WCOL 6 -#define SPIF 7 - -#define SPDR _SFR_IO8(0x2E) - -#define T2MDR _SFR_IO8(0x2F) - -#define LFRR _SFR_IO8(0x30) - -/* Reserved [0x31] */ - -#define LFCDR _SFR_IO8(0x32) -#define LFDO 0 -#define LFRST 6 -#define LFSCE 7 - -#define SMCR _SFR_IO8(0x33) -#define SE 0 -#define SM0 1 -#define SM1 2 -#define SM2 3 - -#define MCUSR _SFR_IO8(0x34) -#define PORF 0 -#define EXTRF 1 -#define BORF 2 -#define WDRF 3 -#define TSRF 5 - -#define MCUCR _SFR_IO8(0x35) -#define IVCE 0 -#define IVSEL 1 -#define PUD 4 - -#define LFRB _SFR_IO8(0x36) - -#define SPMCSR _SFR_IO8(0x37) -#define SELFPRGEN 0 -#define PGERS 1 -#define PGWRT 2 -#define BLBSET 3 -#define RWWSRE 4 -#define RWWSB 6 -#define SPMIE 7 - -#define T1CR _SFR_IO8(0x38) -#define T1PS0 0 -#define T1PS1 1 -#define T1PS2 2 -#define T1CS0 3 -#define T1CS1 4 -#define T1CS2 5 -#define T1IE 7 - -#define T0CR _SFR_IO8(0x39) -#define T0PAS0 0 -#define T0PAS1 1 -#define T0PAS2 2 -#define T0IE 3 -#define T0PR 4 -#define T0PBS0 5 -#define T0PBS1 6 -#define T0PBS2 7 - -/* Reserved [0x3A] */ - -#define CMIMR _SFR_IO8(0x3B) -#define ECIE 0 - -#define CLKPR _SFR_IO8(0x3C) -#define CLKPS0 0 -#define CLKPS1 1 -#define CLKPS2 2 -#define CLTPS0 3 -#define CLTPS1 4 -#define CLTPS2 5 -#define CLPCE 7 - -/* SP [0x3D..0x3E] */ - -/* SREG [0x3F] */ - -#define WDTCR _SFR_MEM8(0x60) -#define WDPS0 0 -#define WDPS1 1 -#define WDPS2 2 -#define WDE 3 -#define WDCE 4 - -#define SIMSK _SFR_MEM8(0x61) -#define MSIE 0 - -/* Reserved [0x62..0x63] */ - -#define TSCR _SFR_MEM8(0x64) -#define TSSD 0 - -#define SRCCAL _SFR_MEM8(0x65) - -#define FRCCAL _SFR_MEM8(0x66) - -#define MSVCAL _SFR_MEM8(0x67) - -/* Reserved [0x68] */ - -#define EICRA _SFR_MEM8(0x69) -#define ISC00 0 -#define ISC01 1 -#define ISC10 2 -#define ISC11 3 - -#define PCMSK0 _SFR_MEM8(0x6A) -#define PCINT0 0 -#define PCINT1 1 -#define PCINT2 2 -#define PCINT3 3 -#define PCINT4 4 -#define PCINT5 5 -#define PCINT6 6 -#define PCINT7 7 - -#define PCMSK1 _SFR_MEM8(0x6B) -#define PCINT8 0 -#define PCINT9 1 -#define PCINT10 2 - -#define PCMSK2 _SFR_MEM8(0x6C) -#define PCINT16 0 -#define PCINT17 1 -#define PCINT18 2 -#define PCINT19 3 -#define PCINT20 4 -#define PCINT21 5 -#define PCINT22 6 -#define PCINT23 7 - -/* Reserved [0x6D] */ - -#define T2ICRL _SFR_MEM8(0x6E) - -#define T2ICR _SFR_MEM8(0x6F) - -/* Combine T2CORL and T2CORH */ -#define T2COR _SFR_MEM16(0x70) - -#define T2CORL _SFR_MEM8(0x70) -#define T2CORH _SFR_MEM8(0x71) - -#define T2MRA _SFR_MEM8(0x72) -#define T2CS0 0 -#define T2CS1 1 -#define T2CS2 2 -#define T2CE0 3 -#define T2CE1 4 -#define T2CNC 5 -#define T2TP0 6 -#define T2TP1 7 - -#define T2MRB _SFR_MEM8(0x73) -#define T2M0 0 -#define T2M1 1 -#define T2M2 2 -#define T2M3 3 -#define T2TOP 4 -#define T2CPOL 6 -#define T2SSIE 7 - -#define T2IMR _SFR_MEM8(0x74) -#define T2OIM 0 -#define T2CIM 1 -#define T2CPIM 2 -#define T2RXIM 3 -#define T2TXIM 4 -#define T2TCIM 5 - -/* Reserved [0x75] */ - -/* Combine T3ICRL and T3ICRH */ -#define T3ICR _SFR_MEM16(0x76) - -#define T3ICRL _SFR_MEM8(0x76) -#define T3ICRH _SFR_MEM8(0x77) - -/* Combine T3CORAL and T3CORAH */ -#define T3CORA _SFR_MEM16(0x78) - -#define T3CORAL _SFR_MEM8(0x78) -#define T3CORAH _SFR_MEM8(0x79) - -/* Combine T3CORBL and T3CORBH */ -#define T3CORB _SFR_MEM16(0x7A) - -#define T3CORBL _SFR_MEM8(0x7A) -#define T3CORBH _SFR_MEM8(0x7B) - -#define T3MRA _SFR_MEM8(0x7C) -#define T3CS0 0 -#define T3CS1 1 -#define T3CS2 2 -#define T3CE0 3 -#define T3CE1 4 -#define T3CNC 5 -#define T3ICS0 6 -#define T3ICS1 7 - -#define T3MRB _SFR_MEM8(0x7D) -#define T3M0 0 -#define T3M1 1 -#define T3M2 2 -#define T3TOP 4 - -#define T3CRB _SFR_MEM8(0x7E) -#define T3CTMA 0 -#define T3SAMA 1 -#define T3CRMA 2 -#define T3CTMB 3 -#define T3SAMB 4 -#define T3CRMB 5 -#define T3CPRM 6 - -#define T3IMR _SFR_MEM8(0x7F) -#define T3OIM 0 -#define T3CAIM 1 -#define T3CBIM 2 -#define T3CPIM 3 - -/* Reserved [0x80] */ - -#define LFIMR _SFR_MEM8(0x81) -#define LFWIM 0 -#define LFBIM 1 -#define LFEIM 2 - -#define LFRCR _SFR_MEM8(0x82) -#define LFEN 0 -#define LFBM 1 -#define LFWM0 2 -#define LFWM1 3 -#define LFRSS 4 -#define LFCS0 5 -#define LFCS1 6 -#define LFCS2 7 - -#define LFHCR _SFR_MEM8(0x83) - -/* Combine LFIDCL and LFIDCH */ -#define LFIDC _SFR_MEM16(0x84) - -#define LFIDCL _SFR_MEM8(0x84) -#define LFIDCH _SFR_MEM8(0x85) - -/* Combine LFCALL and LFCALH */ -#define LFCAL _SFR_MEM16(0x86) - -#define LFCALL _SFR_MEM8(0x86) -#define LFCALH _SFR_MEM8(0x87) - - - -/* Values and associated defines */ - - -#define SLEEP_MODE_IDLE (0x00<<1) -#define SLEEP_MODE_SENSOR_NOISE_REDUCTION (0x01<<1) -#define SLEEP_MODE_PWR_DOWN (0x02<<1) - -/* Interrupt vectors */ -/* Vector 0 is the reset vector */ -/* External Interrupt Request 0 */ -#define INT0_vect _VECTOR(1) -#define INT0_vect_num 1 - -/* External Interrupt Request 1 */ -#define INT1_vect _VECTOR(2) -#define INT1_vect_num 2 - -/* Pin Change Interrupt Request 0 */ -#define PCINT0_vect _VECTOR(3) -#define PCINT0_vect_num 3 - -/* Pin Change Interrupt Request 1 */ -#define PCINT1_vect _VECTOR(4) -#define PCINT1_vect_num 4 - -/* Pin Change Interrupt Request 2 */ -#define PCINT2_vect _VECTOR(5) -#define PCINT2_vect_num 5 - -/* Voltage Monitor Interrupt */ -#define INTVM_vect _VECTOR(6) -#define INTVM_vect_num 6 - -/* Sensor Interface Interrupt */ -#define SENINT_vect _VECTOR(7) -#define SENINT_vect_num 7 - -/* Timer0 Interval Interrupt */ -#define INTT0_vect _VECTOR(8) -#define INTT0_vect_num 8 - -/* LF-Receiver Wake-up Interrupt */ -#define LFWP_vect _VECTOR(9) -#define LFWP_vect_num 9 - -/* Timer/Counter3 Capture Event */ -#define T3CAP_vect _VECTOR(10) -#define T3CAP_vect_num 10 - -/* Timer/Counter3 Compare Match A */ -#define T3COMA_vect _VECTOR(11) -#define T3COMA_vect_num 11 - -/* Timer/Counter3 Compare Match B */ -#define T3COMB_vect _VECTOR(12) -#define T3COMB_vect_num 12 - -/* Timer/Counter3 Overflow */ -#define T3OVF_vect _VECTOR(13) -#define T3OVF_vect_num 13 - -/* Timer/Counter2 Capture Event */ -#define T2CAP_vect _VECTOR(14) -#define T2CAP_vect_num 14 - -/* Timer/Counter2 Compare Match */ -#define T2COM_vect _VECTOR(15) -#define T2COM_vect_num 15 - -/* Timer/Counter2 Overflow */ -#define T2OVF_vect _VECTOR(16) -#define T2OVF_vect_num 16 - -/* SPI Serial Transfer Complete */ -#define SPISTC_vect _VECTOR(17) -#define SPISTC_vect_num 17 - -/* LF Receive Buffer Interrupt */ -#define LFRXB_vect _VECTOR(18) -#define LFRXB_vect_num 18 - -/* Timer1 Interval Interrupt */ -#define INTT1_vect _VECTOR(19) -#define INTT1_vect_num 19 - -/* Timer2 SSI Receive Buffer Interrupt */ -#define T2RXB_vect _VECTOR(20) -#define T2RXB_vect_num 20 - -/* Timer2 SSI Transmit Buffer Interrupt */ -#define T2TXB_vect _VECTOR(21) -#define T2TXB_vect_num 21 - -/* Timer2 SSI Transmit Complete Interrupt */ -#define T2TXC_vect _VECTOR(22) -#define T2TXC_vect_num 22 - -/* LF-Receiver End of Burst Interrupt */ -#define LFREOB_vect _VECTOR(23) -#define LFREOB_vect_num 23 - -/* External Input Clock break down Interrupt */ -#define EXCM_vect _VECTOR(24) -#define EXCM_vect_num 24 - -/* EEPROM Ready Interrupt */ -#define EEREADY_vect _VECTOR(25) -#define EEREADY_vect_num 25 - -/* Store Program Memory Ready */ -#define SPM_RDY_vect _VECTOR(26) -#define SPM_RDY_vect_num 26 - -#define _VECTORS_SIZE 54 - - -/* Constants */ - -#define SPM_PAGESIZE 64 -#define FLASHSTART 0x0000 -#define FLASHEND 0x1FFF -#define RAMSTART 0x0100 -#define RAMSIZE 512 -#define RAMEND 0x02FF -#define E2START 0 -#define E2SIZE 320 -#define E2PAGESIZE 4 -#define E2END 0x013F -#define XRAMEND RAMEND - - -/* Fuses */ - -#define FUSE_MEMORY_SIZE 2 - -/* Low Fuse Byte */ -#define FUSE_TSRDI (unsigned char)~_BV(0) -#define FUSE_BODEN (unsigned char)~_BV(1) -#define FUSE_FRCFS (unsigned char)~_BV(2) -#define FUSE_WDRCON (unsigned char)~_BV(3) -#define FUSE_SUT_CKSEL0 (unsigned char)~_BV(4) -#define FUSE_SUT_CKSEL1 (unsigned char)~_BV(5) -#define FUSE_CKOUT (unsigned char)~_BV(6) -#define FUSE_CKDIV8 (unsigned char)~_BV(7) -#define LFUSE_DEFAULT (FUSE_BODEN & FUSE_FRCFS & FUSE_WDRCON & FUSE_SUT_CKSEL0 & FUSE_CKDIV8) - - -/* High Fuse Byte */ -#define FUSE_BOOTRST (unsigned char)~_BV(0) -#define FUSE_BOOTSZ0 (unsigned char)~_BV(1) -#define FUSE_BOOTSZ1 (unsigned char)~_BV(2) -#define FUSE_EESAVE (unsigned char)~_BV(3) -#define FUSE_WDTON (unsigned char)~_BV(4) -#define FUSE_SPIEN (unsigned char)~_BV(5) -#define FUSE_DWEN (unsigned char)~_BV(6) -#define FUSE_EELOCK (unsigned char)~_BV(7) -#define HFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_SPIEN) - - - -/* Lock Bits */ -#define __LOCK_BITS_EXIST -#define __BOOT_LOCK_BITS_0_EXIST -#define __BOOT_LOCK_BITS_1_EXIST - - -/* Signature */ -#define SIGNATURE_0 0x1E -#define SIGNATURE_1 0x93 -#define SIGNATURE_2 0x82 - - -#endif /* #ifdef _AVR_ATA6286_H_INCLUDED */ - diff --git a/arduino/hardware/tools/avr/avr/include/avr/ioa6289.h b/arduino/hardware/tools/avr/avr/include/avr/ioa6289.h deleted file mode 100644 index 75c7630..0000000 --- a/arduino/hardware/tools/avr/avr/include/avr/ioa6289.h +++ /dev/null @@ -1,847 +0,0 @@ -/* Copyright (c) 2008 Atmel Corporation - All rights reserved. - - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - * Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - * Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in - the documentation and/or other materials provided with the - distribution. - - * Neither the name of the copyright holders nor the names of - contributors may be used to endorse or promote products derived - from this software without specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. */ - -/* $Id: ioa6289.h 2102 2010-03-16 22:52:39Z joerg_wunsch $ */ - -/* avr/ioa6289.h - definitions for ATA6289 */ - -/* This file should only be included from , never directly. */ - -#ifndef _AVR_IO_H_ -# error "Include instead of this file." -#endif - -#ifndef _AVR_IOXXX_H_ -# define _AVR_IOXXX_H_ "ioa6289.h" -#else -# error "Attempt to include more than one file." -#endif - - -#ifndef _AVR_ATA6289_H_ -#define _AVR_ATA6289_H_ 1 - - -/* Registers and associated bit numbers. */ - -#define PINB _SFR_IO8(0x03) -#define PINB0 0 -#define PINB1 1 -#define PINB2 2 -#define PINB3 3 -#define PINB4 4 -#define PINB5 5 -#define PINB6 6 -#define PINB7 7 - -#define DDRB _SFR_IO8(0x04) -#define DDB0 0 -#define DDB1 1 -#define DDB2 2 -#define DDB3 3 -#define DDB4 4 -#define DDB5 5 -#define DDB6 6 -#define DDB7 7 - -#define PORTB _SFR_IO8(0x05) -#define PORTB0 0 -#define PORTB1 1 -#define PORTB2 2 -#define PORTB3 3 -#define PORTB4 4 -#define PORTB5 5 -#define PORTB6 6 -#define PORTB7 7 - -#define PINC _SFR_IO8(0x06) -#define PINC0 0 -#define PINC1 1 - -#define DDRC _SFR_IO8(0x07) - -#define PORTC _SFR_IO8(0x08) -#define PORTC0 0 -#define PORTC1 1 - -#define PIND _SFR_IO8(0x09) -#define PIND0 0 -#define PIND1 1 -#define PIND2 2 -#define PIND3 3 -#define PIND4 4 -#define PIND5 5 -#define PIND6 6 -#define PIND7 7 - -#define DDRD _SFR_IO8(0x0A) -#define DDD0 0 -#define DDD1 1 -#define DDD2 2 -#define DDD3 3 -#define DDD4 4 -#define DDD5 5 -#define DDD6 6 -#define DDD7 7 - -#define PORTD _SFR_IO8(0x0B) -#define PORTD0 0 -#define PORTD1 1 -#define PORTD2 2 -#define PORTD3 3 -#define PORTD4 4 -#define PORTD5 5 -#define PORTD6 6 -#define PORTD7 7 - -#define CMCR _SFR_IO8(0x0F) -#define CMM0 0 -#define CMM1 1 -#define SRCD 2 -#define CMONEN 3 -#define CCS 4 -#define ECINS 5 -#define CMCCE 7 - -#define CMSR _SFR_IO8(0x10) -#define ECF 0 - -#define T2CRA _SFR_IO8(0x11) -#define T2OTM 0 -#define T2CTM 1 -#define T2CR 2 -#define T2CRM 3 -#define T2CPRM 4 -#define T2ICS 5 -#define T2TS 6 -#define T2E 7 - -#define T2CRB _SFR_IO8(0x12) -#define T2SCE 0 - -#define T3CRA _SFR_IO8(0x14) -#define T3AC 0 -#define T3SCE 1 -#define T3CR 2 -#define T3TS 6 -#define T3E 7 - -#define VMCSR _SFR_IO8(0x16) -#define VMEN 0 -#define VMLS0 1 -#define VMLS1 2 -#define VMLS2 3 -#define VMIM 4 -#define VMF 5 -#define BODPD 6 -#define BODLS 7 - -#define PCIFR _SFR_IO8(0x17) -#define PCIF0 0 -#define PCIF1 1 -#define PCIF2 2 - -#define LFFR _SFR_IO8(0x18) -#define LFWPF 0 -#define LFBF 1 -#define LFEDF 2 -#define LFRF 3 - -#define SSFR _SFR_IO8(0x19) -#define MSENF 0 -#define MSENO 1 - -#define T10IFR _SFR_IO8(0x1A) -#define T0F 0 -#define T1F 1 - -#define T2IFR _SFR_IO8(0x1B) -#define T2OFF 0 -#define T2COF 1 -#define T2ICF 2 -#define T2RXF 3 -#define T2TXF 4 -#define T2TCF 5 - -#define T3IFR _SFR_IO8(0x1C) -#define T3OFF 0 -#define T3COAF 1 -#define T3COBF 2 -#define T3ICF 3 - -#define EIFR _SFR_IO8(0x1D) -#define INTF0 0 -#define INTF1 1 - -#define GPIOR0 _SFR_IO8(0x1E) -#define GPIOR00 0 -#define GPIOR01 1 -#define GPIOR02 2 -#define GPIOR03 3 -#define GPIOR04 4 -#define GPIOR05 5 -#define GPIOR06 6 -#define GPIOR07 7 - -#define EECR _SFR_IO8(0x1F) -#define EERE 0 -#define EEWE 1 -#define EEMWE 2 -#define EERIE 3 -#define EEPM0 4 -#define EEPM1 5 - -#define EEDR _SFR_IO8(0x20) -#define EEDR0 0 -#define EEDR1 1 -#define EEDR2 2 -#define EEDR3 3 -#define EEDR4 4 -#define EEDR5 5 -#define EEDR6 6 -#define EEDR7 7 - -#define EEAR _SFR_IO16(0x21) - -#define EEARL _SFR_IO8(0x21) -#define EEAR0 0 -#define EEAR1 1 -#define EEAR2 2 -#define EEAR3 3 -#define EEAR4 4 -#define EEAR5 5 -#define EEAR6 6 -#define EEAR7 7 - -#define EEARH _SFR_IO8(0x22) -#define EEAR8 0 - -#define PCICR _SFR_IO8(0x23) -#define PCIE0 0 -#define PCIE1 1 -#define PCIE2 2 - -#define EIMSK _SFR_IO8(0x24) -#define INT0 0 -#define INT1 1 - -#define SVCR _SFR_IO8(0x27) -#define SVCS0 0 -#define SVCS1 1 -#define SVCS2 2 -#define SVCS3 3 -#define SVCS4 4 - -#define SCR _SFR_IO8(0x28) -#define SMS 0 -#define SEN0 1 -#define SEN1 2 -#define SMEN 3 - -#define SCCR _SFR_IO8(0x29) -#define SRCC0 0 -#define SRCC1 1 -#define SCCS0 2 -#define SCCS1 3 -#define SCCS2 4 - -#define GPIOR1 _SFR_IO8(0x2A) -#define GPIOR10 0 -#define GPIOR11 1 -#define GPIOR12 2 -#define GPIOR13 3 -#define GPIOR14 4 -#define GPIOR15 5 -#define GPIOR16 6 -#define GPIOR17 7 - -#define GPIOR2 _SFR_IO8(0x2B) -#define GPIOR20 0 -#define GPIOR21 1 -#define GPIOR22 2 -#define GPIOR23 3 -#define GPIOR24 4 -#define GPIOR25 5 -#define GPIOR26 6 -#define GPIOR27 7 - -#define SPCR _SFR_IO8(0x2C) -#define SPR0 0 -#define SPR1 1 -#define CPHA 2 -#define CPOL 3 -#define MSTR 4 -#define DORD 5 -#define SPE 6 -#define SPIE 7 - -#define SPSR _SFR_IO8(0x2D) -#define SPI2X 0 -#define WCOL 6 -#define SPIF 7 - -#define SPDR _SFR_IO8(0x2E) -#define SPDR0 0 -#define SPDR1 1 -#define SPDR2 2 -#define SPDR3 3 -#define SPDR4 4 -#define SPDR5 5 -#define SPDR6 6 -#define SPDR7 7 - -#define T2MDR _SFR_IO8(0x2F) -#define T2MDR0 0 -#define T2MDR1 1 -#define T2MDR2 2 -#define T2MDR3 3 -#define T2MDR4 4 -#define T2MDR5 5 -#define T2MDR6 6 -#define T2MDR7 7 - -#define LFRR _SFR_IO8(0x30) -#define LFRR0 0 -#define LFRR1 1 -#define LFRR2 2 -#define LFRR3 3 -#define LFRR4 4 -#define LFRR5 5 -#define LFRR6 6 - -#define LFCDR _SFR_IO8(0x32) -#define LFDO 0 -#define LFRST 6 -#define LFSCE 7 - -#define SMCR _SFR_IO8(0x33) -#define SE 0 -#define SM0 1 -#define SM1 2 -#define SM2 3 - -#define MCUSR _SFR_IO8(0x34) -#define PORF 0 -#define EXTRF 1 -#define BORF 2 -#define WDRF 3 -#define TSRF 5 - -#define MCUCR _SFR_IO8(0x35) -#define IVCE 0 -#define IVSEL 1 -#define PUD 4 - -#define LFRB _SFR_IO8(0x36) -#define LFRB0 0 -#define LFRB1 1 -#define LFRB2 2 -#define LFRB3 3 -#define LFRB4 4 -#define LFRB5 5 -#define LFRB6 6 -#define LFRB7 7 - -#define SPMCSR _SFR_IO8(0x37) -#define SELFPRGEN 0 -#define PGERS 1 -#define PGWRT 2 -#define BLBSET 3 -#define RWWSRE 4 -#define RWWSB 6 -#define SPMIE 7 - -#define T1CR _SFR_IO8(0x38) -#define T1PS0 0 -#define T1PS1 1 -#define T1PS2 2 -#define T1CS0 3 -#define T1CS1 4 -#define T1CS2 5 -#define T1IE 7 - -#define T0CR _SFR_IO8(0x39) -#define T0PAS0 0 -#define T0PAS1 1 -#define T0PAS2 2 -#define T0IE 3 -#define T0PR 4 -#define T0PBS0 5 -#define T0PBS1 6 -#define T0PBS2 7 - -#define CMIMR _SFR_IO8(0x3B) -#define ECIE 0 - -#define CLKPR _SFR_IO8(0x3C) -#define CLKPS0 0 -#define CLKPS1 1 -#define CLKPS2 2 -#define CLTPS0 3 -#define CLTPS1 4 -#define CLTPS2 5 -#define CLPCE 7 - -#define WDTCR _SFR_MEM8(0x60) -#define WDPS0 0 -#define WDPS1 1 -#define WDPS2 2 -#define WDE 3 -#define WDCE 4 - -#define SIMSK _SFR_MEM8(0x61) -#define MSIE 0 - -#define TSCR _SFR_MEM8(0x64) -#define TSSD 0 - -#define SRCCAL _SFR_MEM8(0x65) -#define SCAL0 0 -#define SCAL1 1 -#define SCAL2 2 -#define SCAL3 3 -#define SCAL4 4 -#define SCAL5 5 -#define SCAL6 6 -#define SCAL7 7 - -#define FRCCAL _SFR_MEM8(0x66) -#define FCAL0 0 -#define FCAL1 1 -#define FCAL2 2 -#define FCAL3 3 -#define FCAL4 4 -#define FCAL5 5 -#define FCAL6 6 -#define FCAL7 7 - -#define MSVCAL _SFR_MEM8(0x67) -#define VRCAL0 0 -#define VRCAL1 1 -#define VRCAL2 2 -#define VRCAL3 3 -#define VRCAL4 4 -#define VRCAL5 5 -#define VRCAL6 6 -#define VRCAL7 7 - -#define BGCAL _SFR_MEM8(0x68) -#define BGCAL0 0 -#define BGCAL1 1 -#define BGCAL2 2 -#define BGCAL3 3 -#define BGCAL4 4 -#define BGCAL5 5 -#define BGCAL6 6 -#define BGCAL7 7 - -#define EICRA _SFR_MEM8(0x69) -#define ISC00 0 -#define ISC01 1 -#define ISC10 2 -#define ISC11 3 - -#define PCMSK0 _SFR_MEM8(0x6A) -#define PCINT0 0 -#define PCINT1 1 -#define PCINT2 2 -#define PCINT3 3 -#define PCINT4 4 -#define PCINT5 5 -#define PCINT6 6 -#define PCINT7 7 - -#define PCMSK1 _SFR_MEM8(0x6B) -#define PCINT8 0 -#define PCINT9 1 -#define PCINT10 2 - -#define PCMSK2 _SFR_MEM8(0x6C) -#define PCINT16 0 -#define PCINT17 1 -#define PCINT18 2 -#define PCINT19 3 -#define PCINT20 4 -#define PCINT21 5 -#define PCINT22 6 -#define PCINT23 7 - -#define T2ICR _SFR_MEM16(0x6E) - -#define T2ICRL _SFR_MEM8(0x6E) -#define T2ICRL0 0 -#define T2ICRL1 1 -#define T2ICRL2 2 -#define T2ICRL3 3 -#define T2ICRL4 4 -#define T2ICRL5 5 -#define T2ICRL6 6 -#define T2ICRL7 7 - -#define T2ICRH _SFR_MEM8(0x6F) -#define T2ICRH0 0 -#define T2ICRH1 1 -#define T2ICRH2 2 -#define T2ICRH3 3 -#define T2ICRH4 4 -#define T2ICRH5 5 -#define T2ICRH6 6 -#define T2ICRH7 7 - -#define T2COR _SFR_MEM16(0x70) - -#define T2CORL _SFR_MEM8(0x70) -#define T2CORL0 0 -#define T2CORL1 1 -#define T2CORL2 2 -#define T2CORL3 3 -#define T2CORL4 4 -#define T2CORL5 5 -#define T2CORL6 6 -#define T2CORL7 7 - -#define T2CORH _SFR_MEM8(0x71) -#define T2CORH0 0 -#define T2CORH1 1 -#define T2CORH2 2 -#define T2CORH3 3 -#define T2CORH4 4 -#define T2CORH5 5 -#define T2CORH6 6 -#define T2CORH7 7 - -#define T2MRA _SFR_MEM8(0x72) -#define T2CS0 0 -#define T2CS1 1 -#define T2CS2 2 -#define T2CE0 3 -#define T2CE1 4 -#define T2CNC 5 -#define T2TP0 6 -#define T2TP1 7 - -#define T2MRB _SFR_MEM8(0x73) -#define T2M0 0 -#define T2M1 1 -#define T2M2 2 -#define T2M3 3 -#define T2TOP 4 -#define T2CPOL 6 -#define T2SSIE 7 - -#define T2IMR _SFR_MEM8(0x74) -#define T2OIM 0 -#define T2CIM 1 -#define T2CPIM 2 -#define T2RXIM 3 -#define T2TXIM 4 -#define T2TCIM 5 - -#define T3ICR _SFR_MEM16(0x76) - -#define T3ICRL _SFR_MEM8(0x76) -#define T3ICRL0 0 -#define T3ICRL1 1 -#define T3ICRL2 2 -#define T3ICRL3 3 -#define T3ICRL4 4 -#define T3ICRL5 5 -#define T3ICRL6 6 -#define T3ICRL7 7 - -#define T3ICRH _SFR_MEM8(0x77) -#define T3ICRH0 0 -#define T3ICRH1 1 -#define T3ICRH2 2 -#define T3ICRH3 3 -#define T3ICRH4 4 -#define T3ICRH5 5 -#define T3ICRH6 6 -#define T3ICRH7 7 - -#define T3CORA _SFR_MEM16(0x78) - -#define T3CORAL _SFR_MEM8(0x78) -#define T3CORAL0 0 -#define T3CORAL1 1 -#define T3CORAL2 2 -#define T3CORAL3 3 -#define T3CORAL4 4 -#define T3CORAL5 5 -#define T3CORAL6 6 -#define T3CORAL7 7 - -#define T3CORAH _SFR_MEM8(0x79) -#define T3CORAH0 0 -#define T3CORAH1 1 -#define T3CORAH2 2 -#define T3CORAH3 3 -#define T3CORAH4 4 -#define T3CORAH5 5 -#define T3CORAH6 6 -#define T3CORAH7 7 - -#define T3CORB _SFR_MEM16(0x7A) - -#define T3CORBL _SFR_MEM8(0x7A) -#define T3CORBL0 0 -#define T3CORBL1 1 -#define T3CORBL2 2 -#define T3CORBL3 3 -#define T3CORBL4 4 -#define T3CORBL5 5 -#define T3CORBL6 6 -#define T3CORBL7 7 - -#define T3CORBH _SFR_MEM8(0x7B) -#define T3CORBH0 0 -#define T3CORBH1 1 -#define T3CORBH2 2 -#define T3CORBH3 3 -#define T3CORBH4 4 -#define T3CORBH5 5 -#define T3CORBH6 6 -#define T3CORBH7 7 - -#define T3MRA _SFR_MEM8(0x7C) -#define T3CS0 0 -#define T3CS1 1 -#define T3CS2 2 -#define T3CE0 3 -#define T3CE1 4 -#define T3CNC 5 -#define T3ICS0 6 -#define T3ICS1 7 - -#define T3MRB _SFR_MEM8(0x7D) -#define T3M0 0 -#define T3M1 1 -#define T3M2 2 -#define T3TOP 4 - -#define T3CRB _SFR_MEM8(0x7E) -#define T3CTMA 0 -#define T3SAMA 1 -#define T3CRMA 2 -#define T3CTMB 3 -#define T3SAMB 4 -#define T3CRMB 5 -#define T3CPRM 6 - -#define T3IMR _SFR_MEM8(0x7F) -#define T3OIM 0 -#define T3CAIM 1 -#define T3CBIM 2 -#define T3CPIM 3 - -#define LFIMR _SFR_MEM8(0x81) -#define LFWIM 0 -#define LFBIM 1 -#define LFEIM 2 - -#define LFRCR _SFR_MEM8(0x82) -#define LFEN 0 -#define LFBM 1 -#define LFWM0 2 -#define LFWM1 3 -#define LFRSS 4 -#define LFCS0 5 -#define LFCS1 6 -#define LFCS2 7 - -#define LFHCR _SFR_MEM8(0x83) -#define LFHCR0 0 -#define LFHCR1 1 -#define LFHCR2 2 -#define LFHCR3 3 -#define LFHCR4 4 -#define LFHCR5 5 -#define LFHCR6 6 - -#define LFIDC _SFR_MEM16(0x84) - -#define LFIDCL _SFR_MEM8(0x84) -#define LFIDCL_0 0 -#define LFIDCL_1 1 -#define LFIDCL_2 2 -#define LFIDCL_3 3 -#define LFIDCL_4 4 -#define LFIDCL_5 5 -#define LFIDCL_6 6 -#define LFIDCL_7 7 - -#define LFIDCH _SFR_MEM8(0x85) -#define LFIDCH_8 0 -#define LFIDCH_9 1 -#define LFIDCH_10 2 -#define LFIDCH_11 3 -#define LFIDCH_12 4 -#define LFIDCH_13 5 -#define LFIDCH_14 6 -#define LFIDCH_15 7 - -#define LFCAL _SFR_MEM16(0x86) - -#define LFCALL _SFR_MEM8(0x86) -#define LFCAL_00 0 -#define LFCAL_01 1 -#define LFCAL_02 2 -#define LFCAL_03 3 -#define LFCAL_04 4 -#define LFCAL_05 5 -#define LFCAL_06 6 -#define LFCAL_07 7 - -#define LFCALH _SFR_MEM8(0x87) -#define LFCAL_08 0 -#define LFCAL_09 1 -#define LFCAL_10 2 -#define LFCAL_11 3 -#define LFCAL_12 4 -#define LFCAL_13 5 -#define LFCAL_14 6 -#define LFCAL_15 7 - - -/* Interrupt vectors */ -/* Vector 0 is the reset vector */ -#define INT0_vect_num 1 -#define INT0_vect _VECTOR(1) /* External Interrupt Request 0 */ -#define INT1_vect_num 2 -#define INT1_vect _VECTOR(2) /* External Interrupt Request 1 */ -#define PCINT0_vect_num 3 -#define PCINT0_vect _VECTOR(3) /* Pin Change Interrupt Request 0 */ -#define PCINT1_vect_num 4 -#define PCINT1_vect _VECTOR(4) /* Pin Change Interrupt Request 1 */ -#define PCINT2_vect_num 5 -#define PCINT2_vect _VECTOR(5) /* Pin Change Interrupt Request 2 */ -#define INTVM_vect_num 6 -#define INTVM_vect _VECTOR(6) /* Voltage Monitor Interrupt */ -#define SENINT_vect_num 7 -#define SENINT_vect _VECTOR(7) /* Sensor Interface Interrupt */ -#define INTT0_vect_num 8 -#define INTT0_vect _VECTOR(8) /* Timer0 Interval Interrupt */ -#define LFWP_vect_num 9 -#define LFWP_vect _VECTOR(9) /* LF-Receiver Wake-up Interrupt */ -#define T3CAP_vect_num 10 -#define T3CAP_vect _VECTOR(10) /* Timer/Counter3 Capture Event */ -#define T3COMA_vect_num 11 -#define T3COMA_vect _VECTOR(11) /* Timer/Counter3 Compare Match A */ -#define T3COMB_vect_num 12 -#define T3COMB_vect _VECTOR(12) /* Timer/Counter3 Compare Match B */ -#define T3OVF_vect_num 13 -#define T3OVF_vect _VECTOR(13) /* Timer/Counter3 Overflow */ -#define T2CAP_vect_num 14 -#define T2CAP_vect _VECTOR(14) /* Timer/Counter2 Capture Event */ -#define T2COM_vect_num 15 -#define T2COM_vect _VECTOR(15) /* Timer/Counter2 Compare Match */ -#define T2OVF_vect_num 16 -#define T2OVF_vect _VECTOR(16) /* Timer/Counter2 Overflow */ -#define SPISTC_vect_num 17 -#define SPISTC_vect _VECTOR(17) /* SPI Serial Transfer Complete */ -#define LFRXB_vect_num 18 -#define LFRXB_vect _VECTOR(18) /* LF Receive Buffer Interrupt */ -#define INTT1_vect_num 19 -#define INTT1_vect _VECTOR(19) /* Timer1 Interval Interrupt */ -#define T2RXB_vect_num 20 -#define T2RXB_vect _VECTOR(20) /* Timer2 SSI Receive Buffer Interrupt */ -#define T2TXB_vect_num 21 -#define T2TXB_vect _VECTOR(21) /* Timer2 SSI Transmit Buffer Interrupt */ -#define T2TXC_vect_num 22 -#define T2TXC_vect _VECTOR(22) /* Timer2 SSI Transmit Complete Interrupt */ -#define LFREOB_vect_num 23 -#define LFREOB_vect _VECTOR(23) /* LF-Receiver End of Burst Interrupt */ -#define EXCM_vect_num 24 -#define EXCM_vect _VECTOR(24) /* External Input Clock break down Interrupt */ -#define EEREADY_vect_num 25 -#define EEREADY_vect _VECTOR(25) /* EEPROM Ready Interrupt */ -#define SPM_RDY_vect_num 26 -#define SPM_RDY_vect _VECTOR(26) /* Store Program Memory Ready */ - -#define _VECTOR_SIZE 2 /* Size of individual vector. */ -#define _VECTORS_SIZE (27 * _VECTOR_SIZE) - - -/* Constants */ -#define SPM_PAGESIZE (64) -#define RAMSTART (0x100) -#define RAMSIZE (512) -#define RAMEND (RAMSTART + RAMSIZE - 1) -#define XRAMSTART (NA) -#define XRAMSIZE (0) -#define XRAMEND RAMEND -#define E2END (320 - 1) -#define E2PAGESIZE (4) -#define FLASHEND (8192 - 1) - - -/* Fuses */ -#define FUSE_MEMORY_SIZE 2 - -/* Low Fuse Byte */ -#define FUSE_TSRDI ~_BV(0) /* Disable Temperature shutdown Reset */ -#define FUSE_BODEN ~_BV(1) /* Enable Brown-out detection */ -#define FUSE_FRCFS ~_BV(2) /* Fast RC-Oscillator Frequency select */ -#define FUSE_WDRCON ~_BV(3) /* Enable Watchdog RC-Oscillator */ -#define FUSE_SUT0 ~_BV(4) /* Select start-up time */ -#define FUSE_SUT1 ~_BV(5) /* Select start-up time */ -#define FUSE_CKOUT ~_BV(6) /* Clock output */ -#define FUSE_CKDIV8 ~_BV(7) /* Divide clock by 8 */ -#define LFUSE_DEFAULT (FUSE_CKDIV8 & FUSE_SUT0 & FUSE_WDRCON & FUSE_BODEN) - -/* High Fuse Byte */ -#define FUSE_BOOTRST ~_BV(0) /* Select reset vector */ -#define FUSE_BOOTSZ0 ~_BV(1) /* Boot size select */ -#define FUSE_BOOTSZ1 ~_BV(2) /* Boot size select */ -#define FUSE_EESAVE ~_BV(3) /* EEPROM memory is preserved through chip erase */ -#define FUSE_WDTON ~_BV(4) /* Watchdog Timer Always On */ -#define FUSE_SPIEN ~_BV(5) /* Enable Serial programming and Data Downloading */ -#define FUSE_DWEN ~_BV(6) /* debugWIRE Enable */ -#define FUSE_EELOCK ~_BV(7) /* Upper EEPROM Locked (disabled) */ -#define HFUSE_DEFAULT (FUSE_SPIEN & FUSE_BOOTSZ1 & FUSE_BOOTSZ0) - - -/* Lock Bits */ -#define __LOCK_BITS_EXIST -#define __BOOT_LOCK_BITS_0_EXIST -#define __BOOT_LOCK_BITS_1_EXIST - - -/* Signature */ -#define SIGNATURE_0 0x1E -#define SIGNATURE_1 0x93 -#define SIGNATURE_2 0x82 - -#define SLEEP_MODE_IDLE (0) -#define SLEEP_MODE_SENSOR_NOISE_REDUCTION (_BV(SM0)) -#define SLEEP_MODE_PWR_DOWN (_BV(SM1)) - -#endif /* _AVR_ATA6289_H_ */ - diff --git a/arduino/hardware/tools/avr/avr/include/avr/ioa6612c.h b/arduino/hardware/tools/avr/avr/include/avr/ioa6612c.h deleted file mode 100644 index 19a7209..0000000 --- a/arduino/hardware/tools/avr/avr/include/avr/ioa6612c.h +++ /dev/null @@ -1,795 +0,0 @@ -/***************************************************************************** - * - * Copyright (C) 2015 Atmel Corporation - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * - * * Neither the name of the copyright holders nor the names of - * contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - ****************************************************************************/ - - -#ifndef _AVR_ATA6612C_H_INCLUDED -#define _AVR_ATA6612C_H_INCLUDED - - -#ifndef _AVR_IO_H_ -# error "Include instead of this file." -#endif - -#ifndef _AVR_IOXXX_H_ -# define _AVR_IOXXX_H_ "ioa6612c.h" -#else -# error "Attempt to include more than one file." -#endif - -/* Registers and associated bit numbers */ - -#define PINB _SFR_IO8(0x03) -#define PINB7 7 -#define PINB6 6 -#define PINB5 5 -#define PINB4 4 -#define PINB3 3 -#define PINB2 2 -#define PINB1 1 -#define PINB0 0 - -#define DDRB _SFR_IO8(0x04) -#define DDB0 0 -#define DDB1 1 -#define DDB2 2 -#define DDB3 3 -#define DDB4 4 -#define DDB5 5 -#define DDB6 6 -#define DDB7 7 - -#define PORTB _SFR_IO8(0x05) -#define PORTB7 7 -#define PORTB6 6 -#define PORTB5 5 -#define PORTB4 4 -#define PORTB3 3 -#define PORTB2 2 -#define PORTB1 1 -#define PORTB0 0 - -#define PINC _SFR_IO8(0x06) -#define PINC6 6 -#define PINC5 5 -#define PINC4 4 -#define PINC3 3 -#define PINC2 2 -#define PINC1 1 -#define PINC0 0 - -#define DDRC _SFR_IO8(0x07) -#define DDC0 0 -#define DDC1 1 -#define DDC2 2 -#define DDC3 3 -#define DDC4 4 -#define DDC5 5 -#define DDC6 6 - -#define PORTC _SFR_IO8(0x08) -#define PORTC6 6 -#define PORTC5 5 -#define PORTC4 4 -#define PORTC3 3 -#define PORTC2 2 -#define PORTC1 1 -#define PORTC0 0 - -#define PIND _SFR_IO8(0x09) -#define PIND7 7 -#define PIND6 6 -#define PIND5 5 -#define PIND4 4 -#define PIND3 3 -#define PIND2 2 -#define PIND1 1 -#define PIND0 0 - -#define DDRD _SFR_IO8(0x0A) -#define DDD0 0 -#define DDD1 1 -#define DDD2 2 -#define DDD3 3 -#define DDD4 4 -#define DDD5 5 -#define DDD6 6 -#define DDD7 7 - -#define PORTD _SFR_IO8(0x0B) -#define PORTD7 7 -#define PORTD6 6 -#define PORTD5 5 -#define PORTD4 4 -#define PORTD3 3 -#define PORTD2 2 -#define PORTD1 1 -#define PORTD0 0 - -/* Reserved [0x0C..0x14] */ - -#define TIFR0 _SFR_IO8(0x15) -#define TOV0 0 -#define OCF0A 1 -#define OCF0B 2 - -#define TIFR1 _SFR_IO8(0x16) -#define TOV1 0 -#define OCF1A 1 -#define OCF1B 2 -#define ICF1 5 - -#define TIFR2 _SFR_IO8(0x17) -#define TOV2 0 -#define OCF2A 1 -#define OCF2B 2 - -/* Reserved [0x18..0x1A] */ - -#define PCIFR _SFR_IO8(0x1B) -#define PCIF0 0 -#define PCIF1 1 -#define PCIF2 2 - -#define EIFR _SFR_IO8(0x1C) -#define INTF0 0 -#define INTF1 1 - -#define EIMSK _SFR_IO8(0x1D) -#define INT0 0 -#define INT1 1 - -#define GPIOR0 _SFR_IO8(0x1E) - -#define EECR _SFR_IO8(0x1F) -#define EERE 0 -#define EEPE 1 -#define EEMPE 2 -#define EERIE 3 -#define EEPM0 4 -#define EEPM1 5 - -#define EEDR _SFR_IO8(0x20) - -/* Combine EEARL and EEARH */ -#define EEAR _SFR_IO16(0x21) - -#define EEARL _SFR_IO8(0x21) -#define EEARH _SFR_IO8(0x22) - -#define GTCCR _SFR_IO8(0x23) -#define PSRSYNC 0 -#define TSM 7 -#define PSRASY 1 - -#define TCCR0A _SFR_IO8(0x24) -#define WGM00 0 -#define WGM01 1 -#define COM0B0 4 -#define COM0B1 5 -#define COM0A0 6 -#define COM0A1 7 - -#define TCCR0B _SFR_IO8(0x25) -#define CS00 0 -#define CS01 1 -#define CS02 2 -#define WGM02 3 -#define FOC0B 6 -#define FOC0A 7 - -#define TCNT0 _SFR_IO8(0x26) - -#define OCR0A _SFR_IO8(0x27) - -#define OCR0B _SFR_IO8(0x28) - -/* Reserved [0x29] */ - -#define GPIOR1 _SFR_IO8(0x2A) - -#define GPIOR2 _SFR_IO8(0x2B) - -#define SPCR _SFR_IO8(0x2C) -#define SPR0 0 -#define SPR1 1 -#define CPHA 2 -#define CPOL 3 -#define MSTR 4 -#define DORD 5 -#define SPE 6 -#define SPIE 7 - -#define SPSR _SFR_IO8(0x2D) -#define SPI2X 0 -#define WCOL 6 -#define SPIF 7 - -#define SPDR _SFR_IO8(0x2E) - -/* Reserved [0x2F] */ - -#define ACSR _SFR_IO8(0x30) -#define ACIS0 0 -#define ACIS1 1 -#define ACIC 2 -#define ACIE 3 -#define ACI 4 -#define ACO 5 -#define ACBG 6 -#define ACD 7 - -/* Reserved [0x31..0x32] */ - -#define SMCR _SFR_IO8(0x33) -#define SE 0 -#define SM0 1 -#define SM1 2 -#define SM2 3 - -#define MCUSR _SFR_IO8(0x34) -#define PORF 0 -#define EXTRF 1 -#define BORF 2 -#define WDRF 3 - -#define MCUCR _SFR_IO8(0x35) -#define IVCE 0 -#define IVSEL 1 -#define PUD 4 - -/* Reserved [0x36] */ - -#define SPMCSR _SFR_IO8(0x37) -#define SELFPRGEN 0 -#define PGERS 1 -#define PGWRT 2 -#define BLBSET 3 -#define RWWSRE 4 -#define RWWSB 6 -#define SPMIE 7 - -/* Reserved [0x38..0x3C] */ - -/* SP [0x3D..0x3E] */ - -/* SREG [0x3F] */ - -#define WDTCSR _SFR_MEM8(0x60) -#define WDE 3 -#define WDCE 4 -#define WDP0 0 -#define WDP1 1 -#define WDP2 2 -#define WDP3 5 -#define WDIE 6 -#define WDIF 7 - -#define CLKPR _SFR_MEM8(0x61) -#define CLKPS0 0 -#define CLKPS1 1 -#define CLKPS2 2 -#define CLKPS3 3 -#define CLKPCE 7 - -/* Reserved [0x62..0x63] */ - -#define PRR _SFR_MEM8(0x64) -#define PRADC 0 -#define PRUSART0 1 -#define PRSPI 2 -#define PRTIM1 3 -#define PRTIM0 5 -#define PRTIM2 6 -#define PRTWI 7 - -#define __AVR_HAVE_PRR ((1< instead of this file." -#endif - -#ifndef _AVR_IOXXX_H_ -# define _AVR_IOXXX_H_ "ioa6613c.h" -#else -# error "Attempt to include more than one file." -#endif - -/* Registers and associated bit numbers */ - -#define PINB _SFR_IO8(0x03) -#define PINB7 7 -#define PINB6 6 -#define PINB5 5 -#define PINB4 4 -#define PINB3 3 -#define PINB2 2 -#define PINB1 1 -#define PINB0 0 - -#define DDRB _SFR_IO8(0x04) -#define DDB0 0 -#define DDB1 1 -#define DDB2 2 -#define DDB3 3 -#define DDB4 4 -#define DDB5 5 -#define DDB6 6 -#define DDB7 7 - -#define PORTB _SFR_IO8(0x05) -#define PORTB7 7 -#define PORTB6 6 -#define PORTB5 5 -#define PORTB4 4 -#define PORTB3 3 -#define PORTB2 2 -#define PORTB1 1 -#define PORTB0 0 - -#define PINC _SFR_IO8(0x06) -#define PINC6 6 -#define PINC5 5 -#define PINC4 4 -#define PINC3 3 -#define PINC2 2 -#define PINC1 1 -#define PINC0 0 - -#define DDRC _SFR_IO8(0x07) -#define DDC0 0 -#define DDC1 1 -#define DDC2 2 -#define DDC3 3 -#define DDC4 4 -#define DDC5 5 -#define DDC6 6 - -#define PORTC _SFR_IO8(0x08) -#define PORTC6 6 -#define PORTC5 5 -#define PORTC4 4 -#define PORTC3 3 -#define PORTC2 2 -#define PORTC1 1 -#define PORTC0 0 - -#define PIND _SFR_IO8(0x09) -#define PIND7 7 -#define PIND6 6 -#define PIND5 5 -#define PIND4 4 -#define PIND3 3 -#define PIND2 2 -#define PIND1 1 -#define PIND0 0 - -#define DDRD _SFR_IO8(0x0A) -#define DDD0 0 -#define DDD1 1 -#define DDD2 2 -#define DDD3 3 -#define DDD4 4 -#define DDD5 5 -#define DDD6 6 -#define DDD7 7 - -#define PORTD _SFR_IO8(0x0B) -#define PORTD7 7 -#define PORTD6 6 -#define PORTD5 5 -#define PORTD4 4 -#define PORTD3 3 -#define PORTD2 2 -#define PORTD1 1 -#define PORTD0 0 - -/* Reserved [0x0C..0x14] */ - -#define TIFR0 _SFR_IO8(0x15) -#define TOV0 0 -#define OCF0A 1 -#define OCF0B 2 - -#define TIFR1 _SFR_IO8(0x16) -#define TOV1 0 -#define OCF1A 1 -#define OCF1B 2 -#define ICF1 5 - -#define TIFR2 _SFR_IO8(0x17) -#define TOV2 0 -#define OCF2A 1 -#define OCF2B 2 - -/* Reserved [0x18..0x1A] */ - -#define PCIFR _SFR_IO8(0x1B) -#define PCIF0 0 -#define PCIF1 1 -#define PCIF2 2 - -#define EIFR _SFR_IO8(0x1C) -#define INTF0 0 -#define INTF1 1 - -#define EIMSK _SFR_IO8(0x1D) -#define INT0 0 -#define INT1 1 - -#define GPIOR0 _SFR_IO8(0x1E) - -#define EECR _SFR_IO8(0x1F) -#define EERE 0 -#define EEPE 1 -#define EEMPE 2 -#define EERIE 3 -#define EEPM0 4 -#define EEPM1 5 - -#define EEDR _SFR_IO8(0x20) - -/* Combine EEARL and EEARH */ -#define EEAR _SFR_IO16(0x21) - -#define EEARL _SFR_IO8(0x21) -#define EEARH _SFR_IO8(0x22) - -#define GTCCR _SFR_IO8(0x23) -#define PSRSYNC 0 -#define TSM 7 -#define PSRASY 1 - -#define TCCR0A _SFR_IO8(0x24) -#define WGM00 0 -#define WGM01 1 -#define COM0B0 4 -#define COM0B1 5 -#define COM0A0 6 -#define COM0A1 7 - -#define TCCR0B _SFR_IO8(0x25) -#define CS00 0 -#define CS01 1 -#define CS02 2 -#define WGM02 3 -#define FOC0B 6 -#define FOC0A 7 - -#define TCNT0 _SFR_IO8(0x26) - -#define OCR0A _SFR_IO8(0x27) - -#define OCR0B _SFR_IO8(0x28) - -/* Reserved [0x29] */ - -#define GPIOR1 _SFR_IO8(0x2A) - -#define GPIOR2 _SFR_IO8(0x2B) - -#define SPCR _SFR_IO8(0x2C) -#define SPR0 0 -#define SPR1 1 -#define CPHA 2 -#define CPOL 3 -#define MSTR 4 -#define DORD 5 -#define SPE 6 -#define SPIE 7 - -#define SPSR _SFR_IO8(0x2D) -#define SPI2X 0 -#define WCOL 6 -#define SPIF 7 - -#define SPDR _SFR_IO8(0x2E) - -/* Reserved [0x2F] */ - -#define ACSR _SFR_IO8(0x30) -#define ACIS0 0 -#define ACIS1 1 -#define ACIC 2 -#define ACIE 3 -#define ACI 4 -#define ACO 5 -#define ACBG 6 -#define ACD 7 - -/* Reserved [0x31..0x32] */ - -#define SMCR _SFR_IO8(0x33) -#define SE 0 -#define SM0 1 -#define SM1 2 -#define SM2 3 - -#define MCUSR _SFR_IO8(0x34) -#define PORF 0 -#define EXTRF 1 -#define BORF 2 -#define WDRF 3 - -#define MCUCR _SFR_IO8(0x35) -#define IVCE 0 -#define IVSEL 1 -#define PUD 4 - -/* Reserved [0x36] */ - -#define SPMCSR _SFR_IO8(0x37) -#define SELFPRGEN 0 -#define PGERS 1 -#define PGWRT 2 -#define BLBSET 3 -#define RWWSRE 4 -#define RWWSB 6 -#define SPMIE 7 - -/* Reserved [0x38..0x3C] */ - -/* SP [0x3D..0x3E] */ - -/* SREG [0x3F] */ - -#define WDTCSR _SFR_MEM8(0x60) -#define WDE 3 -#define WDCE 4 -#define WDP0 0 -#define WDP1 1 -#define WDP2 2 -#define WDP3 5 -#define WDIE 6 -#define WDIF 7 - -#define CLKPR _SFR_MEM8(0x61) -#define CLKPS0 0 -#define CLKPS1 1 -#define CLKPS2 2 -#define CLKPS3 3 -#define CLKPCE 7 - -/* Reserved [0x62..0x63] */ - -#define PRR _SFR_MEM8(0x64) -#define PRADC 0 -#define PRUSART0 1 -#define PRSPI 2 -#define PRTIM1 3 -#define PRTIM0 5 -#define PRTIM2 6 -#define PRTWI 7 - -#define __AVR_HAVE_PRR ((1< instead of this file." -#endif - -#ifndef _AVR_IOXXX_H_ -# define _AVR_IOXXX_H_ "ioa6614q.h" -#else -# error "Attempt to include more than one file." -#endif - -/* Registers and associated bit numbers */ - -#define PINB _SFR_IO8(0x03) -#define PINB7 7 -#define PINB6 6 -#define PINB5 5 -#define PINB4 4 -#define PINB3 3 -#define PINB2 2 -#define PINB1 1 -#define PINB0 0 - -#define DDRB _SFR_IO8(0x04) -#define DDB0 0 -#define DDB1 1 -#define DDB2 2 -#define DDB3 3 -#define DDB4 4 -#define DDB5 5 -#define DDB6 6 -#define DDB7 7 - -#define PORTB _SFR_IO8(0x05) -#define PORTB7 7 -#define PORTB6 6 -#define PORTB5 5 -#define PORTB4 4 -#define PORTB3 3 -#define PORTB2 2 -#define PORTB1 1 -#define PORTB0 0 - -#define PINC _SFR_IO8(0x06) -#define PINC6 6 -#define PINC5 5 -#define PINC4 4 -#define PINC3 3 -#define PINC2 2 -#define PINC1 1 -#define PINC0 0 - -#define DDRC _SFR_IO8(0x07) -#define DDC0 0 -#define DDC1 1 -#define DDC2 2 -#define DDC3 3 -#define DDC4 4 -#define DDC5 5 -#define DDC6 6 - -#define PORTC _SFR_IO8(0x08) -#define PORTC6 6 -#define PORTC5 5 -#define PORTC4 4 -#define PORTC3 3 -#define PORTC2 2 -#define PORTC1 1 -#define PORTC0 0 - -#define PIND _SFR_IO8(0x09) -#define PIND7 7 -#define PIND6 6 -#define PIND5 5 -#define PIND4 4 -#define PIND3 3 -#define PIND2 2 -#define PIND1 1 -#define PIND0 0 - -#define DDRD _SFR_IO8(0x0A) -#define DDD0 0 -#define DDD1 1 -#define DDD2 2 -#define DDD3 3 -#define DDD4 4 -#define DDD5 5 -#define DDD6 6 -#define DDD7 7 - -#define PORTD _SFR_IO8(0x0B) -#define PORTD7 7 -#define PORTD6 6 -#define PORTD5 5 -#define PORTD4 4 -#define PORTD3 3 -#define PORTD2 2 -#define PORTD1 1 -#define PORTD0 0 - -/* Reserved [0x0C..0x14] */ - -#define TIFR0 _SFR_IO8(0x15) -#define TOV0 0 -#define OCF0A 1 -#define OCF0B 2 - -#define TIFR1 _SFR_IO8(0x16) -#define TOV1 0 -#define OCF1A 1 -#define OCF1B 2 -#define ICF1 5 - -#define TIFR2 _SFR_IO8(0x17) -#define TOV2 0 -#define OCF2A 1 -#define OCF2B 2 - -/* Reserved [0x18..0x1A] */ - -#define PCIFR _SFR_IO8(0x1B) -#define PCIF0 0 -#define PCIF1 1 -#define PCIF2 2 - -#define EIFR _SFR_IO8(0x1C) -#define INTF0 0 -#define INTF1 1 - -#define EIMSK _SFR_IO8(0x1D) -#define INT0 0 -#define INT1 1 - -#define GPIOR0 _SFR_IO8(0x1E) - -#define EECR _SFR_IO8(0x1F) -#define EERE 0 -#define EEPE 1 -#define EEMPE 2 -#define EERIE 3 -#define EEPM0 4 -#define EEPM1 5 - -#define EEDR _SFR_IO8(0x20) - -/* Combine EEARL and EEARH */ -#define EEAR _SFR_IO16(0x21) - -#define EEARL _SFR_IO8(0x21) -#define EEARH _SFR_IO8(0x22) - -#define GTCCR _SFR_IO8(0x23) -#define PSRSYNC 0 -#define TSM 7 -#define PSRASY 1 - -#define TCCR0A _SFR_IO8(0x24) -#define WGM00 0 -#define WGM01 1 -#define COM0B0 4 -#define COM0B1 5 -#define COM0A0 6 -#define COM0A1 7 - -#define TCCR0B _SFR_IO8(0x25) -#define CS00 0 -#define CS01 1 -#define CS02 2 -#define WGM02 3 -#define FOC0B 6 -#define FOC0A 7 - -#define TCNT0 _SFR_IO8(0x26) - -#define OCR0A _SFR_IO8(0x27) - -#define OCR0B _SFR_IO8(0x28) - -/* Reserved [0x29] */ - -#define GPIOR1 _SFR_IO8(0x2A) - -#define GPIOR2 _SFR_IO8(0x2B) - -#define SPCR _SFR_IO8(0x2C) -#define SPR0 0 -#define SPR1 1 -#define CPHA 2 -#define CPOL 3 -#define MSTR 4 -#define DORD 5 -#define SPE 6 -#define SPIE 7 - -#define SPSR _SFR_IO8(0x2D) -#define SPI2X 0 -#define WCOL 6 -#define SPIF 7 - -#define SPDR _SFR_IO8(0x2E) - -/* Reserved [0x2F] */ - -#define ACSR _SFR_IO8(0x30) -#define ACIS0 0 -#define ACIS1 1 -#define ACIC 2 -#define ACIE 3 -#define ACI 4 -#define ACO 5 -#define ACBG 6 -#define ACD 7 - -/* Reserved [0x31..0x32] */ - -#define SMCR _SFR_IO8(0x33) -#define SE 0 -#define SM0 1 -#define SM1 2 -#define SM2 3 - -#define MCUSR _SFR_IO8(0x34) -#define PORF 0 -#define EXTRF 1 -#define BORF 2 -#define WDRF 3 - -#define MCUCR _SFR_IO8(0x35) -#define IVCE 0 -#define IVSEL 1 -#define PUD 4 -#define BODSE 5 -#define BODS 6 - -/* Reserved [0x36] */ - -#define SPMCSR _SFR_IO8(0x37) -#define SELFPRGEN 0 -#define PGERS 1 -#define PGWRT 2 -#define BLBSET 3 -#define RWWSRE 4 -#define RWWSB 6 -#define SPMIE 7 - -/* Reserved [0x38..0x3C] */ - -/* SP [0x3D..0x3E] */ - -/* SREG [0x3F] */ - -#define WDTCSR _SFR_MEM8(0x60) -#define WDE 3 -#define WDCE 4 -#define WDP0 0 -#define WDP1 1 -#define WDP2 2 -#define WDP3 5 -#define WDIE 6 -#define WDIF 7 - -#define CLKPR _SFR_MEM8(0x61) -#define CLKPS0 0 -#define CLKPS1 1 -#define CLKPS2 2 -#define CLKPS3 3 -#define CLKPCE 7 - -/* Reserved [0x62..0x63] */ - -#define PRR _SFR_MEM8(0x64) -#define PRADC 0 -#define PRUSART0 1 -#define PRSPI 2 -#define PRTIM1 3 -#define PRTIM0 5 -#define PRTIM2 6 -#define PRTWI 7 - -#define __AVR_HAVE_PRR ((1< instead of this file." -#endif - -#ifndef _AVR_IOXXX_H_ -# define _AVR_IOXXX_H_ "ioa6616c.h" -#else -# error "Attempt to include more than one file." -#endif - -/* Registers and associated bit numbers */ - -#define PINA _SFR_IO8(0x00) -#define PINA7 7 -#define PINA6 6 -#define PINA5 5 -#define PINA4 4 -#define PINA3 3 -#define PINA2 2 -#define PINA1 1 -#define PINA0 0 - -#define DDRA _SFR_IO8(0x01) -#define DDA0 0 -#define DDA1 1 -#define DDA2 2 -#define DDA3 3 -#define DDA4 4 -#define DDA5 5 -#define DDA6 6 -#define DDA7 7 - -#define PORTA _SFR_IO8(0x02) -#define PORTA7 7 -#define PORTA6 6 -#define PORTA5 5 -#define PORTA4 4 -#define PORTA3 3 -#define PORTA2 2 -#define PORTA1 1 -#define PORTA0 0 - -#define PINB _SFR_IO8(0x03) -#define PINB7 7 -#define PINB6 6 -#define PINB5 5 -#define PINB4 4 -#define PINB3 3 -#define PINB2 2 -#define PINB1 1 -#define PINB0 0 - -#define DDRB _SFR_IO8(0x04) -#define DDB0 0 -#define DDB1 1 -#define DDB2 2 -#define DDB3 3 -#define DDB4 4 -#define DDB5 5 -#define DDB6 6 -#define DDB7 7 - -#define PORTB _SFR_IO8(0x05) -#define PORTB7 7 -#define PORTB6 6 -#define PORTB5 5 -#define PORTB4 4 -#define PORTB3 3 -#define PORTB2 2 -#define PORTB1 1 -#define PORTB0 0 - -/* Reserved [0x06..0x11] */ - -#define PORTCR _SFR_IO8(0x12) -#define PUDA 0 -#define PUDB 1 -#define BBMA 4 -#define BBMB 5 - -/* Reserved [0x13..0x14] */ - -#define TIFR0 _SFR_IO8(0x15) -#define TOV0 0 -#define OCF0A 1 - -#define TIFR1 _SFR_IO8(0x16) -#define TOV1 0 -#define OCF1A 1 -#define OCF1B 2 -#define ICF1 5 - -/* Reserved [0x17..0x1A] */ - -#define PCIFR _SFR_IO8(0x1B) -#define PCIF0 0 -#define PCIF1 1 - -#define EIFR _SFR_IO8(0x1C) -#define INTF0 0 -#define INTF1 1 - -#define EIMSK _SFR_IO8(0x1D) -#define INT0 0 -#define INT1 1 - -#define GPIOR0 _SFR_IO8(0x1E) -#define GPIOR00 0 -#define GPIOR01 1 -#define GPIOR02 2 -#define GPIOR03 3 -#define GPIOR04 4 -#define GPIOR05 5 -#define GPIOR06 6 -#define GPIOR07 7 - -#define EECR _SFR_IO8(0x1F) -#define EERE 0 -#define EEPE 1 -#define EEMPE 2 -#define EERIE 3 -#define EEPM0 4 -#define EEPM1 5 - -#define EEDR _SFR_IO8(0x20) -#define EEDR0 0 -#define EEDR1 1 -#define EEDR2 2 -#define EEDR3 3 -#define EEDR4 4 -#define EEDR5 5 -#define EEDR6 6 -#define EEDR7 7 - -/* Combine EEARL and EEARH */ -#define EEAR _SFR_IO16(0x21) - -#define EEARL _SFR_IO8(0x21) -#define EEARH _SFR_IO8(0x22) - -#define GTCCR _SFR_IO8(0x23) -#define PSR1 0 -#define PSR0 1 -#define TSM 7 - -/* Reserved [0x24] */ - -#define TCCR0A _SFR_IO8(0x25) -#define WGM00 0 -#define WGM01 1 -#define COM0A0 6 -#define COM0A1 7 - -#define TCCR0B _SFR_IO8(0x26) -#define CS00 0 -#define CS01 1 -#define CS02 2 -#define FOC0A 7 - -#define TCNT0 _SFR_IO8(0x27) -#define TCNT00 0 -#define TCNT01 1 -#define TCNT02 2 -#define TCNT03 3 -#define TCNT04 4 -#define TCNT05 5 -#define TCNT06 6 -#define TCNT07 7 - -#define OCR0A _SFR_IO8(0x28) -#define OCR00 0 -#define OCR01 1 -#define OCR02 2 -#define OCR03 3 -#define OCR04 4 -#define OCR05 5 -#define OCR06 6 -#define OCR07 7 - -/* Reserved [0x29] */ - -#define GPIOR1 _SFR_IO8(0x2A) -#define GPIOR10 0 -#define GPIOR11 1 -#define GPIOR12 2 -#define GPIOR13 3 -#define GPIOR14 4 -#define GPIOR15 5 -#define GPIOR16 6 -#define GPIOR17 7 - -#define GPIOR2 _SFR_IO8(0x2B) -#define GPIOR20 0 -#define GPIOR21 1 -#define GPIOR22 2 -#define GPIOR23 3 -#define GPIOR24 4 -#define GPIOR25 5 -#define GPIOR26 6 -#define GPIOR27 7 - -#define SPCR _SFR_IO8(0x2C) -#define SPR0 0 -#define SPR1 1 -#define CPHA 2 -#define CPOL 3 -#define MSTR 4 -#define DORD 5 -#define SPE 6 -#define SPIE 7 - -#define SPSR _SFR_IO8(0x2D) -#define SPI2X 0 -#define WCOL 6 -#define SPIF 7 - -#define SPDR _SFR_IO8(0x2E) -#define SPDR0 0 -#define SPDR1 1 -#define SPDR2 2 -#define SPDR3 3 -#define SPDR4 4 -#define SPDR5 5 -#define SPDR6 6 -#define SPDR7 7 - -/* Reserved [0x2F] */ - -#define ACSR _SFR_IO8(0x30) -#define ACIS0 0 -#define ACIS1 1 -#define ACIC 2 -#define ACIE 3 -#define ACI 4 -#define ACO 5 -#define ACIRS 6 -#define ACD 7 - -#define DWDR _SFR_IO8(0x31) -#define DWDR0 0 -#define DWDR1 1 -#define DWDR2 2 -#define DWDR3 3 -#define DWDR4 4 -#define DWDR5 5 -#define DWDR6 6 -#define DWDR7 7 - -/* Reserved [0x32] */ - -#define SMCR _SFR_IO8(0x33) -#define SE 0 -#define SM0 1 -#define SM1 2 - -#define MCUSR _SFR_IO8(0x34) -#define PORF 0 -#define EXTRF 1 -#define BORF 2 -#define WDRF 3 - -#define MCUCR _SFR_IO8(0x35) -#define PUD 4 -#define BODSE 5 -#define BODS 6 - -/* Reserved [0x36] */ - -#define SPMCSR _SFR_IO8(0x37) -#define SPMEN 0 -#define PGERS 1 -#define PGWRT 2 -#define RFLB 3 -#define CTPB 4 -#define SIGRD 5 -#define RWWSB 6 - -/* Reserved [0x38..0x3C] */ - -/* SP [0x3D..0x3E] */ - -/* SREG [0x3F] */ - -#define WDTCR _SFR_MEM8(0x60) -#define WDE 3 -#define WDCE 4 -#define WDP0 0 -#define WDP1 1 -#define WDP2 2 -#define WDP3 5 -#define WDIE 6 -#define WDIF 7 - -#define CLKPR _SFR_MEM8(0x61) -#define CLKPS0 0 -#define CLKPS1 1 -#define CLKPS2 2 -#define CLKPS3 3 -#define CLKPCE 7 - -#define CLKCSR _SFR_MEM8(0x62) -#define CLKC0 0 -#define CLKC1 1 -#define CLKC2 2 -#define CLKC3 3 -#define CLKRDY 4 -#define CLKCCE 7 - -#define CLKSELR _SFR_MEM8(0x63) -#define CSEL0 0 -#define CSEL1 1 -#define CSEL2 2 -#define CSEL3 3 -#define CSUT0 4 -#define CSUT1 5 -#define COUT 6 - -#define PRR _SFR_MEM8(0x64) -#define PRADC 0 -#define PRUSI 1 -#define PRTIM0 2 -#define PRTIM1 3 -#define PRSPI 4 -#define PRLIN 5 - -#define __AVR_HAVE_PRR ((1< instead of this file." -#endif - -#ifndef _AVR_IOXXX_H_ -# define _AVR_IOXXX_H_ "ioa6617c.h" -#else -# error "Attempt to include more than one file." -#endif - -/* Registers and associated bit numbers */ - -#define PINA _SFR_IO8(0x00) -#define PINA7 7 -#define PINA6 6 -#define PINA5 5 -#define PINA4 4 -#define PINA3 3 -#define PINA2 2 -#define PINA1 1 -#define PINA0 0 - -#define DDRA _SFR_IO8(0x01) -#define DDA0 0 -#define DDA1 1 -#define DDA2 2 -#define DDA3 3 -#define DDA4 4 -#define DDA5 5 -#define DDA6 6 -#define DDA7 7 - -#define PORTA _SFR_IO8(0x02) -#define PORTA7 7 -#define PORTA6 6 -#define PORTA5 5 -#define PORTA4 4 -#define PORTA3 3 -#define PORTA2 2 -#define PORTA1 1 -#define PORTA0 0 - -#define PINB _SFR_IO8(0x03) -#define PINB7 7 -#define PINB6 6 -#define PINB5 5 -#define PINB4 4 -#define PINB3 3 -#define PINB2 2 -#define PINB1 1 -#define PINB0 0 - -#define DDRB _SFR_IO8(0x04) -#define DDB0 0 -#define DDB1 1 -#define DDB2 2 -#define DDB3 3 -#define DDB4 4 -#define DDB5 5 -#define DDB6 6 -#define DDB7 7 - -#define PORTB _SFR_IO8(0x05) -#define PORTB7 7 -#define PORTB6 6 -#define PORTB5 5 -#define PORTB4 4 -#define PORTB3 3 -#define PORTB2 2 -#define PORTB1 1 -#define PORTB0 0 - -/* Reserved [0x06..0x11] */ - -#define PORTCR _SFR_IO8(0x12) -#define PUDA 0 -#define PUDB 1 -#define BBMA 4 -#define BBMB 5 - -/* Reserved [0x13..0x14] */ - -#define TIFR0 _SFR_IO8(0x15) -#define TOV0 0 -#define OCF0A 1 - -#define TIFR1 _SFR_IO8(0x16) -#define TOV1 0 -#define OCF1A 1 -#define OCF1B 2 -#define ICF1 5 - -/* Reserved [0x17..0x1A] */ - -#define PCIFR _SFR_IO8(0x1B) -#define PCIF0 0 -#define PCIF1 1 - -#define EIFR _SFR_IO8(0x1C) -#define INTF0 0 -#define INTF1 1 - -#define EIMSK _SFR_IO8(0x1D) -#define INT0 0 -#define INT1 1 - -#define GPIOR0 _SFR_IO8(0x1E) -#define GPIOR00 0 -#define GPIOR01 1 -#define GPIOR02 2 -#define GPIOR03 3 -#define GPIOR04 4 -#define GPIOR05 5 -#define GPIOR06 6 -#define GPIOR07 7 - -#define EECR _SFR_IO8(0x1F) -#define EERE 0 -#define EEPE 1 -#define EEMPE 2 -#define EERIE 3 -#define EEPM0 4 -#define EEPM1 5 - -#define EEDR _SFR_IO8(0x20) -#define EEDR0 0 -#define EEDR1 1 -#define EEDR2 2 -#define EEDR3 3 -#define EEDR4 4 -#define EEDR5 5 -#define EEDR6 6 -#define EEDR7 7 - -/* Combine EEARL and EEARH */ -#define EEAR _SFR_IO16(0x21) - -#define EEARL _SFR_IO8(0x21) -#define EEARH _SFR_IO8(0x22) - -#define GTCCR _SFR_IO8(0x23) -#define PSR1 0 -#define PSR0 1 -#define TSM 7 - -/* Reserved [0x24] */ - -#define TCCR0A _SFR_IO8(0x25) -#define WGM00 0 -#define WGM01 1 -#define COM0A0 6 -#define COM0A1 7 - -#define TCCR0B _SFR_IO8(0x26) -#define CS00 0 -#define CS01 1 -#define CS02 2 -#define FOC0A 7 - -#define TCNT0 _SFR_IO8(0x27) -#define TCNT00 0 -#define TCNT01 1 -#define TCNT02 2 -#define TCNT03 3 -#define TCNT04 4 -#define TCNT05 5 -#define TCNT06 6 -#define TCNT07 7 - -#define OCR0A _SFR_IO8(0x28) -#define OCR00 0 -#define OCR01 1 -#define OCR02 2 -#define OCR03 3 -#define OCR04 4 -#define OCR05 5 -#define OCR06 6 -#define OCR07 7 - -/* Reserved [0x29] */ - -#define GPIOR1 _SFR_IO8(0x2A) -#define GPIOR10 0 -#define GPIOR11 1 -#define GPIOR12 2 -#define GPIOR13 3 -#define GPIOR14 4 -#define GPIOR15 5 -#define GPIOR16 6 -#define GPIOR17 7 - -#define GPIOR2 _SFR_IO8(0x2B) -#define GPIOR20 0 -#define GPIOR21 1 -#define GPIOR22 2 -#define GPIOR23 3 -#define GPIOR24 4 -#define GPIOR25 5 -#define GPIOR26 6 -#define GPIOR27 7 - -#define SPCR _SFR_IO8(0x2C) -#define SPR0 0 -#define SPR1 1 -#define CPHA 2 -#define CPOL 3 -#define MSTR 4 -#define DORD 5 -#define SPE 6 -#define SPIE 7 - -#define SPSR _SFR_IO8(0x2D) -#define SPI2X 0 -#define WCOL 6 -#define SPIF 7 - -#define SPDR _SFR_IO8(0x2E) -#define SPDR0 0 -#define SPDR1 1 -#define SPDR2 2 -#define SPDR3 3 -#define SPDR4 4 -#define SPDR5 5 -#define SPDR6 6 -#define SPDR7 7 - -/* Reserved [0x2F] */ - -#define ACSR _SFR_IO8(0x30) -#define ACIS0 0 -#define ACIS1 1 -#define ACIC 2 -#define ACIE 3 -#define ACI 4 -#define ACO 5 -#define ACIRS 6 -#define ACD 7 - -#define DWDR _SFR_IO8(0x31) -#define DWDR0 0 -#define DWDR1 1 -#define DWDR2 2 -#define DWDR3 3 -#define DWDR4 4 -#define DWDR5 5 -#define DWDR6 6 -#define DWDR7 7 - -/* Reserved [0x32] */ - -#define SMCR _SFR_IO8(0x33) -#define SE 0 -#define SM0 1 -#define SM1 2 - -#define MCUSR _SFR_IO8(0x34) -#define PORF 0 -#define EXTRF 1 -#define BORF 2 -#define WDRF 3 - -#define MCUCR _SFR_IO8(0x35) -#define PUD 4 -#define BODSE 5 -#define BODS 6 - -/* Reserved [0x36] */ - -#define SPMCSR _SFR_IO8(0x37) -#define SPMEN 0 -#define PGERS 1 -#define PGWRT 2 -#define RFLB 3 -#define CTPB 4 -#define SIGRD 5 -#define RWWSB 6 - -/* Reserved [0x38..0x3C] */ - -/* SP [0x3D..0x3E] */ - -/* SREG [0x3F] */ - -#define WDTCR _SFR_MEM8(0x60) -#define WDE 3 -#define WDCE 4 -#define WDP0 0 -#define WDP1 1 -#define WDP2 2 -#define WDP3 5 -#define WDIE 6 -#define WDIF 7 - -#define CLKPR _SFR_MEM8(0x61) -#define CLKPS0 0 -#define CLKPS1 1 -#define CLKPS2 2 -#define CLKPS3 3 -#define CLKPCE 7 - -#define CLKCSR _SFR_MEM8(0x62) -#define CLKC0 0 -#define CLKC1 1 -#define CLKC2 2 -#define CLKC3 3 -#define CLKRDY 4 -#define CLKCCE 7 - -#define CLKSELR _SFR_MEM8(0x63) -#define CSEL0 0 -#define CSEL1 1 -#define CSEL2 2 -#define CSEL3 3 -#define CSUT0 4 -#define CSUT1 5 -#define COUT 6 - -#define PRR _SFR_MEM8(0x64) -#define PRADC 0 -#define PRUSI 1 -#define PRTIM0 2 -#define PRTIM1 3 -#define PRSPI 4 -#define PRLIN 5 - -#define __AVR_HAVE_PRR ((1< instead of this file." -#endif - -#ifndef _AVR_IOXXX_H_ -# define _AVR_IOXXX_H_ "ioa664251.h" -#else -# error "Attempt to include more than one file." -#endif - -/* Registers and associated bit numbers */ - -#define PINA _SFR_IO8(0x00) -#define PINA7 7 -#define PINA6 6 -#define PINA5 5 -#define PINA4 4 -#define PINA3 3 -#define PINA2 2 -#define PINA1 1 -#define PINA0 0 - -#define DDRA _SFR_IO8(0x01) -#define DDA0 0 -#define DDA1 1 -#define DDA2 2 -#define DDA3 3 -#define DDA4 4 -#define DDA5 5 -#define DDA6 6 -#define DDA7 7 - -#define PORTA _SFR_IO8(0x02) -#define PORTA7 7 -#define PORTA6 6 -#define PORTA5 5 -#define PORTA4 4 -#define PORTA3 3 -#define PORTA2 2 -#define PORTA1 1 -#define PORTA0 0 - -#define PINB _SFR_IO8(0x03) -#define PINB7 7 -#define PINB6 6 -#define PINB5 5 -#define PINB4 4 -#define PINB3 3 -#define PINB2 2 -#define PINB1 1 -#define PINB0 0 - -#define DDRB _SFR_IO8(0x04) -#define DDB0 0 -#define DDB1 1 -#define DDB2 2 -#define DDB3 3 -#define DDB4 4 -#define DDB5 5 -#define DDB6 6 -#define DDB7 7 - -#define PORTB _SFR_IO8(0x05) -#define PORTB7 7 -#define PORTB6 6 -#define PORTB5 5 -#define PORTB4 4 -#define PORTB3 3 -#define PORTB2 2 -#define PORTB1 1 -#define PORTB0 0 - -/* Reserved [0x06..0x11] */ - -#define PORTCR _SFR_IO8(0x12) -#define PUDA 0 -#define PUDB 1 -#define BBMA 4 -#define BBMB 5 - -/* Reserved [0x13..0x14] */ - -#define TIFR0 _SFR_IO8(0x15) -#define TOV0 0 -#define OCF0A 1 - -#define TIFR1 _SFR_IO8(0x16) -#define TOV1 0 -#define OCF1A 1 -#define OCF1B 2 -#define ICF1 5 - -/* Reserved [0x17..0x1A] */ - -#define PCIFR _SFR_IO8(0x1B) -#define PCIF0 0 -#define PCIF1 1 - -#define EIFR _SFR_IO8(0x1C) -#define INTF0 0 -#define INTF1 1 - -#define EIMSK _SFR_IO8(0x1D) -#define INT0 0 -#define INT1 1 - -#define GPIOR0 _SFR_IO8(0x1E) -#define GPIOR00 0 -#define GPIOR01 1 -#define GPIOR02 2 -#define GPIOR03 3 -#define GPIOR04 4 -#define GPIOR05 5 -#define GPIOR06 6 -#define GPIOR07 7 - -#define EECR _SFR_IO8(0x1F) -#define EERE 0 -#define EEPE 1 -#define EEMPE 2 -#define EERIE 3 -#define EEPM0 4 -#define EEPM1 5 - -#define EEDR _SFR_IO8(0x20) -#define EEDR0 0 -#define EEDR1 1 -#define EEDR2 2 -#define EEDR3 3 -#define EEDR4 4 -#define EEDR5 5 -#define EEDR6 6 -#define EEDR7 7 - -/* Combine EEARL and EEARH */ -#define EEAR _SFR_IO16(0x21) - -#define EEARL _SFR_IO8(0x21) -#define EEARH _SFR_IO8(0x22) - -#define GTCCR _SFR_IO8(0x23) -#define PSR1 0 -#define PSR0 1 -#define TSM 7 - -/* Reserved [0x24] */ - -#define TCCR0A _SFR_IO8(0x25) -#define WGM00 0 -#define WGM01 1 -#define COM0A0 6 -#define COM0A1 7 - -#define TCCR0B _SFR_IO8(0x26) -#define CS00 0 -#define CS01 1 -#define CS02 2 -#define FOC0A 7 - -#define TCNT0 _SFR_IO8(0x27) -#define TCNT00 0 -#define TCNT01 1 -#define TCNT02 2 -#define TCNT03 3 -#define TCNT04 4 -#define TCNT05 5 -#define TCNT06 6 -#define TCNT07 7 - -#define OCR0A _SFR_IO8(0x28) -#define OCR00 0 -#define OCR01 1 -#define OCR02 2 -#define OCR03 3 -#define OCR04 4 -#define OCR05 5 -#define OCR06 6 -#define OCR07 7 - -/* Reserved [0x29] */ - -#define GPIOR1 _SFR_IO8(0x2A) -#define GPIOR10 0 -#define GPIOR11 1 -#define GPIOR12 2 -#define GPIOR13 3 -#define GPIOR14 4 -#define GPIOR15 5 -#define GPIOR16 6 -#define GPIOR17 7 - -#define GPIOR2 _SFR_IO8(0x2B) -#define GPIOR20 0 -#define GPIOR21 1 -#define GPIOR22 2 -#define GPIOR23 3 -#define GPIOR24 4 -#define GPIOR25 5 -#define GPIOR26 6 -#define GPIOR27 7 - -#define SPCR _SFR_IO8(0x2C) -#define SPR0 0 -#define SPR1 1 -#define CPHA 2 -#define CPOL 3 -#define MSTR 4 -#define DORD 5 -#define SPE 6 -#define SPIE 7 - -#define SPSR _SFR_IO8(0x2D) -#define SPI2X 0 -#define WCOL 6 -#define SPIF 7 - -#define SPDR _SFR_IO8(0x2E) -#define SPDR0 0 -#define SPDR1 1 -#define SPDR2 2 -#define SPDR3 3 -#define SPDR4 4 -#define SPDR5 5 -#define SPDR6 6 -#define SPDR7 7 - -/* Reserved [0x2F] */ - -#define ACSR _SFR_IO8(0x30) -#define ACIS0 0 -#define ACIS1 1 -#define ACIC 2 -#define ACIE 3 -#define ACI 4 -#define ACO 5 -#define ACIRS 6 -#define ACD 7 - -#define DWDR _SFR_IO8(0x31) -#define DWDR0 0 -#define DWDR1 1 -#define DWDR2 2 -#define DWDR3 3 -#define DWDR4 4 -#define DWDR5 5 -#define DWDR6 6 -#define DWDR7 7 - -/* Reserved [0x32] */ - -#define SMCR _SFR_IO8(0x33) -#define SE 0 -#define SM0 1 -#define SM1 2 - -#define MCUSR _SFR_IO8(0x34) -#define PORF 0 -#define EXTRF 1 -#define BORF 2 -#define WDRF 3 - -#define MCUCR _SFR_IO8(0x35) -#define PUD 4 -#define BODSE 5 -#define BODS 6 - -/* Reserved [0x36] */ - -#define SPMCSR _SFR_IO8(0x37) -#define SPMEN 0 -#define PGERS 1 -#define PGWRT 2 -#define RFLB 3 -#define CTPB 4 -#define SIGRD 5 -#define RWWSB 6 - -/* Reserved [0x38..0x3C] */ - -/* SP [0x3D..0x3E] */ - -/* SREG [0x3F] */ - -#define WDTCR _SFR_MEM8(0x60) -#define WDE 3 -#define WDCE 4 -#define WDP0 0 -#define WDP1 1 -#define WDP2 2 -#define WDP3 5 -#define WDIE 6 -#define WDIF 7 - -#define CLKPR _SFR_MEM8(0x61) -#define CLKPS0 0 -#define CLKPS1 1 -#define CLKPS2 2 -#define CLKPS3 3 -#define CLKPCE 7 - -#define CLKCSR _SFR_MEM8(0x62) -#define CLKC0 0 -#define CLKC1 1 -#define CLKC2 2 -#define CLKC3 3 -#define CLKRDY 4 -#define CLKCCE 7 - -#define CLKSELR _SFR_MEM8(0x63) -#define CSEL0 0 -#define CSEL1 1 -#define CSEL2 2 -#define CSEL3 3 -#define CSUT0 4 -#define CSUT1 5 -#define COUT 6 - -#define PRR _SFR_MEM8(0x64) -#define PRADC 0 -#define PRUSI 1 -#define PRTIM0 2 -#define PRTIM1 3 -#define PRSPI 4 -#define PRLIN 5 - -#define __AVR_HAVE_PRR ((1< instead of this file." -#endif - -#ifndef _AVR_IOXXX_H_ -# define _AVR_IOXXX_H_ "ioa8210.h" -#else -# error "Attempt to include more than one file." -#endif - -/* Registers and associated bit numbers */ - -#define PRR0 _SFR_IO8(0x01) -#define PRSPI 0 -#define PRRXDC 1 -#define PRTXDC 2 -#define PRCRC 3 -#define PRVM 4 -#define PRCO 5 - -#define __AVR_HAVE_PRR0 ((1< instead of this file." -#endif - -#ifndef _AVR_IOXXX_H_ -# define _AVR_IOXXX_H_ "ioa8510.h" -#else -# error "Attempt to include more than one file." -#endif - -/* Registers and associated bit numbers */ - -#define PRR0 _SFR_IO8(0x01) -#define PRSPI 0 -#define PRRXDC 1 -#define PRTXDC 2 -#define PRCRC 3 -#define PRVM 4 -#define PRCO 5 - -#define __AVR_HAVE_PRR0 ((1<, never directly. */ - -#ifndef _AVR_IO_H_ -# error "Include instead of this file." -#endif - -#ifndef _AVR_IOXXX_H_ -# define _AVR_IOXXX_H_ "ioat94k.h" -#else -# error "Attempt to include more than one file." -#endif - -/* I/O registers */ - -/* UART1 Baud Rate Register */ -#define UBRR1 _SFR_IO8(0x00) - -/* UART1 Control and Status Registers */ -#define UCSR1B _SFR_IO8(0x01) -#define UCSR1A _SFR_IO8(0x02) - -/* UART1 I/O Data Register */ -#define UDR1 _SFR_IO8(0x03) - -/* 0x04 reserved */ - -/* Input Pins, Port E */ -#define PINE _SFR_IO8(0x05) - -/* Data Direction Register, Port E */ -#define DDRE _SFR_IO8(0x06) - -/* Data Register, Port E */ -#define PORTE _SFR_IO8(0x07) - -/* On Chip Debug Register (reserved) */ -#define OCDR _SFR_IO8(0x08) - -/* UART0 Baud Rate Register */ -#define UBRR0 _SFR_IO8(0x09) - -/* UART0 Control and Status Registers */ -#define UCSR0B _SFR_IO8(0x0A) -#define UCSR0A _SFR_IO8(0x0B) - -/* UART0 I/O Data Register */ -#define UDR0 _SFR_IO8(0x0C) - -/* 0x0D..0x0F reserved */ - -/* Input Pins, Port D */ -#define PIND _SFR_IO8(0x10) - -/* Data Direction Register, Port D */ -#define DDRD _SFR_IO8(0x11) - -/* Data Register, Port D */ -#define PORTD _SFR_IO8(0x12) - -/* FPGA I/O Select Control Register */ -#define FISCR _SFR_IO8(0x13) - -/* FPGA I/O Select Registers A, B, C, D */ -#define FISUA _SFR_IO8(0x14) -#define FISUB _SFR_IO8(0x15) -#define FISUC _SFR_IO8(0x16) -#define FISUD _SFR_IO8(0x17) - -/* FPGA Cache Logic(R) registers (top secret, under NDA) */ -#define FPGAX _SFR_IO8(0x18) -#define FPGAY _SFR_IO8(0x19) -#define FPGAZ _SFR_IO8(0x1A) -#define FPGAD _SFR_IO8(0x1B) - -/* TWI stands for "Two Wire Interface" or "TWI Was I2C(tm)" */ - -/* 2-wire Serial Bit Rate Register */ -#define TWBR _SFR_IO8(0x1C) - -/* 2-wire Serial Status Register */ -#define TWSR _SFR_IO8(0x1D) - -/* 2-wire Serial (Slave) Address Register */ -#define TWAR _SFR_IO8(0x1E) - -/* 2-wire Serial Data Register */ -#define TWDR _SFR_IO8(0x1F) - -/* UART Baud Register High */ -#define UBRRH _SFR_IO8(0x20) -#define UBRRHI UBRRH /* New name in datasheet (1138F-FPSLI-06/02) */ - -/* Watchdog Timer Control Register */ -#define WDTCR _SFR_IO8(0x21) - -/* Timer/Counter2 Output Compare Register */ -#define OCR2 _SFR_IO8(0x22) - -/* Timer/Counter2 (8-bit) */ -#define TCNT2 _SFR_IO8(0x23) - -/* Timer/Counter1 Input Capture Register */ -#define ICR1 _SFR_IO16(0x24) -#define ICR1L _SFR_IO8(0x24) -#define ICR1H _SFR_IO8(0x25) - -/* Asynchronous mode StatuS Register */ -#define ASSR _SFR_IO8(0x26) - -/* Timer/Counter2 Control Register */ -#define TCCR2 _SFR_IO8(0x27) - -/* Timer/Counter1 Output Compare RegisterB */ -#define OCR1B _SFR_IO16(0x28) -#define OCR1BL _SFR_IO8(0x28) -#define OCR1BH _SFR_IO8(0x29) - -/* Timer/Counter1 Output Compare RegisterA */ -#define OCR1A _SFR_IO16(0x2A) -#define OCR1AL _SFR_IO8(0x2A) -#define OCR1AH _SFR_IO8(0x2B) - -/* Timer/Counter1 */ -#define TCNT1 _SFR_IO16(0x2C) -#define TCNT1L _SFR_IO8(0x2C) -#define TCNT1H _SFR_IO8(0x2D) - -/* Timer/Counter1 Control Register B */ -#define TCCR1B _SFR_IO8(0x2E) - -/* Timer/Counter1 Control Register A */ -#define TCCR1A _SFR_IO8(0x2F) - -/* Special Function IO Register */ -#define SFIOR _SFR_IO8(0x30) - -/* Timer/Counter0 Output Compare Register */ -#define OCR0 _SFR_IO8(0x31) - -/* Timer/Counter0 (8-bit) */ -#define TCNT0 _SFR_IO8(0x32) - -/* Timer/Counter0 Control Register */ -#define TCCR0 _SFR_IO8(0x33) - -/* 0x34 reserved */ - -/* MCU Control/Status Register */ -#define MCUR _SFR_IO8(0x35) - -/* 2-wire Serial Control Register */ -#define TWCR _SFR_IO8(0x36) - -/* 0x37 reserved */ - -/* Timer/Counter Interrupt Flag Register */ -#define TIFR _SFR_IO8(0x38) - -/* Timer/Counter Interrupt MaSK Register */ -#define TIMSK _SFR_IO8(0x39) - -/* Software Control Register */ -#define SFTCR _SFR_IO8(0x3A) - -/* External Interrupt Mask/Flag Register */ -#define EIMF _SFR_IO8(0x3B) - -/* 0x3C reserved */ - -/* 0x3D..0x3E SP */ - -/* 0x3F SREG */ - -/* Interrupt vectors */ - -#define SIG_FPGA_INTERRUPT0 _VECTOR(1) /* FPGA_INT0 */ -#define SIG_INTERRUPT0 _VECTOR(2) /* EXT_INT0 */ -#define SIG_FPGA_INTERRUPT1 _VECTOR(3) /* FPGA_INT1 */ -#define SIG_INTERRUPT1 _VECTOR(4) /* EXT_INT1 */ -#define SIG_FPGA_INTERRUPT2 _VECTOR(5) /* FPGA_INT2 */ -#define SIG_INTERRUPT2 _VECTOR(6) /* EXT_INT2 */ -#define SIG_FPGA_INTERRUPT3 _VECTOR(7) /* FPGA_INT3 */ -#define SIG_INTERRUPT3 _VECTOR(8) /* EXT_INT3 */ -#define SIG_OUTPUT_COMPARE2 _VECTOR(9) /* TIM2_COMP */ -#define SIG_OVERFLOW2 _VECTOR(10) /* TIM2_OVF */ -#define SIG_INPUT_CAPTURE1 _VECTOR(11) /* TIM1_CAPT */ -#define SIG_OUTPUT_COMPARE1A _VECTOR(12) /* TIM1_COMPA */ -#define SIG_OUTPUT_COMPARE1B _VECTOR(13) /* TIM1_COMPB */ -#define SIG_OVERFLOW1 _VECTOR(14) /* TIM1_OVF */ -#define SIG_OUTPUT_COMPARE0 _VECTOR(15) /* TIM0_COMP */ -#define SIG_OVERFLOW0 _VECTOR(16) /* TIM0_OVF */ -#define SIG_FPGA_INTERRUPT4 _VECTOR(17) /* FPGA_INT4 */ -#define SIG_FPGA_INTERRUPT5 _VECTOR(18) /* FPGA_INT5 */ -#define SIG_FPGA_INTERRUPT6 _VECTOR(19) /* FPGA_INT6 */ -#define SIG_FPGA_INTERRUPT7 _VECTOR(20) /* FPGA_INT7 */ -#define SIG_UART0_RECV _VECTOR(21) /* UART0_RXC */ -#define SIG_UART0_DATA _VECTOR(22) /* UART0_DRE */ -#define SIG_UART0_TRANS _VECTOR(23) /* UART0_TXC */ -#define SIG_FPGA_INTERRUPT8 _VECTOR(24) /* FPGA_INT8 */ -#define SIG_FPGA_INTERRUPT9 _VECTOR(25) /* FPGA_INT9 */ -#define SIG_FPGA_INTERRUPT10 _VECTOR(26) /* FPGA_INT10 */ -#define SIG_FPGA_INTERRUPT11 _VECTOR(27) /* FPGA_INT11 */ -#define SIG_UART1_RECV _VECTOR(28) /* UART1_RXC */ -#define SIG_UART1_DATA _VECTOR(29) /* UART1_DRE */ -#define SIG_UART1_TRANS _VECTOR(30) /* UART1_TXC */ -#define SIG_FPGA_INTERRUPT12 _VECTOR(31) /* FPGA_INT12 */ -#define SIG_FPGA_INTERRUPT13 _VECTOR(32) /* FPGA_INT13 */ -#define SIG_FPGA_INTERRUPT14 _VECTOR(33) /* FPGA_INT14 */ -#define SIG_FPGA_INTERRUPT15 _VECTOR(34) /* FPGA_INT15 */ -#define SIG_2WIRE_SERIAL _VECTOR(35) /* TWS_INT */ - -#define _VECTORS_SIZE 144 - -/* Bit numbers (SFRs alphabetically sorted) */ - -/* ASSR */ -#define AS2 3 -#define TCN2UB 2 -#define OCR2UB 1 -#define TCR2UB 0 - -/* DDRD */ -#define DDD7 7 -#define DDD6 6 -#define DDD5 5 -#define DDD4 4 -#define DDD3 3 -#define DDD2 2 -#define DDD1 1 -#define DDD0 0 - -/* DDRE */ -#define DDE7 7 -#define DDE6 6 -#define DDE5 5 -#define DDE4 4 -#define DDE3 3 -#define DDE2 2 -#define DDE1 1 -#define DDE0 0 - -/* EIMF */ -#define INTF3 7 -#define INTF2 6 -#define INTF1 5 -#define INTF0 4 -#define INT3 3 -#define INT2 2 -#define INT1 1 -#define INT0 0 - -/* FISCR */ -#define FIADR 7 -#define XFIS1 1 -#define XFIS0 0 - -/* FISUA */ -#define FIF3 7 -#define FIF2 6 -#define FIF1 5 -#define FIF0 4 -#define FINT3 3 -#define FINT2 2 -#define FINT1 1 -#define FINT0 0 - -/* FISUB */ -#define FIF7 7 -#define FIF6 6 -#define FIF5 5 -#define FIF4 4 -#define FINT7 3 -#define FINT6 2 -#define FINT5 1 -#define FINT4 0 - -/* FISUC */ -#define FIF11 7 -#define FIF10 6 -#define FIF9 5 -#define FIF8 4 -#define FINT11 3 -#define FINT10 2 -#define FINT9 1 -#define FINT8 0 - -/* FISUD */ -#define FIF15 7 -#define FIF14 6 -#define FIF13 5 -#define FIF12 4 -#define FINT15 3 -#define FINT14 2 -#define FINT13 1 -#define FINT12 0 - -/* MCUR */ -#define JTRF 7 -#define JTD 6 -#define SE 5 -#define SM1 4 -#define SM0 3 -#define PORF 2 -#define WDRF 1 -#define EXTRF 0 - -/* OCDR (reserved) */ -#define IDRD 7 - -/* PIND */ -#define PIND7 7 -#define PIND6 6 -#define PIND5 5 -#define PIND4 4 -#define PIND3 3 -#define PIND2 2 -#define PIND1 1 -#define PIND0 0 - -/* PINE */ -#define PINE7 7 -#define PINE6 6 -#define PINE5 5 -#define PINE4 4 -#define PINE3 3 -#define PINE2 2 -#define PINE1 1 -#define PINE0 0 - -/* PORTD */ -#define PD7 7 -#define PD6 6 -#define PD5 5 -#define PD4 4 -#define PD3 3 -#define PD2 2 -#define PD1 1 -#define PD0 0 - -/* PORTE */ -/* - PE7 = IC1 / INT3 (alternate) - PE6 = OC1A / INT2 (alternate) - PE5 = OC1B / INT1 (alternate) - PE4 = ET11 / INT0 (alternate) - PE3 = OC2 / RX1 (alternate) - PE2 = / TX1 (alternate) - PE1 = OC0 / RX0 (alternate) - PE0 = ET0 / TX0 (alternate) - */ -#define PE7 7 -#define PE6 6 -#define PE5 5 -#define PE4 4 -#define PE3 3 -#define PE2 2 -#define PE1 1 -#define PE0 0 - -/* SFIOR */ -#define PSR2 1 -#define PSR10 0 - -/* SFTCR */ -#define FMXOR 3 -#define WDTS 2 -#define DBG 1 -#define SRST 0 - -/* TCCR0 */ -#define FOC0 7 -#define PWM0 6 -#define COM01 5 -#define COM00 4 -#define CTC0 3 -#define CS02 2 -#define CS01 1 -#define CS00 0 - -/* TCCR1A */ -#define COM1A1 7 -#define COM1A0 6 -#define COM1B1 5 -#define COM1B0 4 -#define FOC1A 3 -#define FOC1B 2 -#define PWM11 1 -#define PWM10 0 - -/* TCCR1B */ -#define ICNC1 7 -#define ICES1 6 -#define ICPE 5 -#define CTC1 3 -#define CS12 2 -#define CS11 1 -#define CS10 0 - -/* TCCR2 */ -#define FOC2 7 -#define PWM2 6 -#define COM21 5 -#define COM20 4 -#define CTC2 3 -#define CS22 2 -#define CS21 1 -#define CS20 0 - -/* TIFR */ -#define TOV1 7 -#define OCF1A 6 -#define OCF1B 5 -#define TOV2 4 -#define ICF1 3 -#define OCF2 2 -#define TOV0 1 -#define OCF0 0 - -/* TIMSK */ -#define TOIE1 7 -#define OCIE1A 6 -#define OCIE1B 5 -#define TOIE2 4 -#define TICIE1 3 -#define OCIE2 2 -#define TOIE0 1 -#define OCIE0 0 - -/* TWAR */ -/* #define TWA 1 */ /* TWA is bits 7:1 */ -#define TWGCE 0 - -/* TWCR */ -#define TWINT 7 -#define TWEA 6 -#define TWSTA 5 -#define TWSTO 4 -#define TWWC 3 -#define TWEN 2 -#define TWIE 0 - -/* TWSR */ -#define TWS7 7 -#define TWS6 6 -#define TWS5 5 -#define TWS4 4 -#define TWS3 3 - -/* UBRRHI - Bits 11..8 of UART1 are bits 7..4 of UBRRHI. - Bits 11..8 of UART0 are bits 3..0 of UBRRHI. */ -/* #define UBRRHI1 4 */ -/* #define UBRRHI0 0 */ - -/* UCSR0A */ -#define RXC0 7 -#define TXC0 6 -#define UDRE0 5 -#define FE0 4 -#define OR0 3 -#define U2X0 1 -#define MPCM0 0 - -/* UCSR0B */ -#define RXCIE0 7 -#define TXCIE0 6 -#define UDRIE0 5 -#define RXEN0 4 -#define TXEN0 3 -#define CHR90 2 -#define RXB80 1 -#define TXB80 0 - -/* UCSR1A */ -#define RXC1 7 -#define TXC1 6 -#define UDRE1 5 -#define FE1 4 -#define OR1 3 -#define U2X1 1 -#define MPCM1 0 - -/* UCSR1B */ -#define RXCIE1 7 -#define TXCIE1 6 -#define UDRIE1 5 -#define RXEN1 4 -#define TXEN1 3 -#define CHR91 2 -#define RXB81 1 -#define TXB81 0 - -/* WDTCR */ -#define WDTOE 4 -#define WDE 3 -#define WDP2 2 -#define WDP1 1 -#define WDP0 0 - -/* - Last memory addresses - depending on configuration, it is possible - to have 20K-32K of program memory and 4K-16K of data memory - (all in the same 36K total of SRAM, loaded from external EEPROM). - */ - -#ifndef RAMSTART -#define RAMSTART 0x60 -#endif - -#ifndef RAMEND -#define RAMEND 0x0FFF -#endif - -#ifndef XRAMEND -#define XRAMEND RAMEND -#endif - -#define E2END 0 - -#ifndef FLASHEND -#define FLASHEND 0x7FFF -#endif - -#define SLEEP_MODE_IDLE 0 -#define SLEEP_MODE_PWR_DOWN _BV(SM1) -#define SLEEP_MODE_PWR_SAVE (_BV(SM0) | _BV(SM1)) - -#endif /* _AVR_IOAT94K_H_ */ diff --git a/arduino/hardware/tools/avr/avr/include/avr/iocan128.h b/arduino/hardware/tools/avr/avr/include/avr/iocan128.h deleted file mode 100644 index bdbfb9f..0000000 --- a/arduino/hardware/tools/avr/avr/include/avr/iocan128.h +++ /dev/null @@ -1,100 +0,0 @@ -/* Copyright (c) 2004,2005, Colin O'Flynn - All rights reserved. - - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - * Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - * Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in - the documentation and/or other materials provided with the - distribution. - - * Neither the name of the copyright holders nor the names of - contributors may be used to endorse or promote products derived - from this software without specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. */ - -/* $Id: iocan128.h 1767 2008-10-17 23:27:53Z arcanum $ */ - -/* iocan128.h - definitions for CAN128 */ - -#ifndef _AVR_IOCAN128_H_ -#define _AVR_IOCAN128_H_ 1 - -#include - -/* Constants */ -#define SPM_PAGESIZE 256 -#define RAMSTART 0x100 -#define RAMEND 0x10FF /* Last On-Chip SRAM Location */ -#define XRAMEND 0xFFFF -#define E2END 0x0FFF -#define E2PAGESIZE 8 -#define FLASHEND 0x1FFFF - - -/* Fuses */ - -#define FUSE_MEMORY_SIZE 3 - -/* Low Fuse Byte */ -#define FUSE_CKSEL0 (unsigned char)~_BV(0) -#define FUSE_CKSEL1 (unsigned char)~_BV(1) -#define FUSE_CKSEL2 (unsigned char)~_BV(2) -#define FUSE_CKSEL3 (unsigned char)~_BV(3) -#define FUSE_SUT0 (unsigned char)~_BV(4) -#define FUSE_SUT1 (unsigned char)~_BV(5) -#define FUSE_CKOUT (unsigned char)~_BV(6) -#define FUSE_CKDIV8 (unsigned char)~_BV(7) -#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8) - -/* High Fuse Byte */ -#define FUSE_BOOTRST (unsigned char)~_BV(0) -#define FUSE_BOOTSZ0 (unsigned char)~_BV(1) -#define FUSE_BOOTSZ1 (unsigned char)~_BV(2) -#define FUSE_EESAVE (unsigned char)~_BV(3) -#define FUSE_WDTON (unsigned char)~_BV(4) -#define FUSE_SPIEN (unsigned char)~_BV(5) -#define FUSE_JTAGEN (unsigned char)~_BV(6) -#define FUSE_OCDEN (unsigned char)~_BV(7) -#define HFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_SPIEN & FUSE_JTAGEN) - -/* Extended Fuse Byte */ -#define FUSE_BODLEVEL0 (unsigned char)~_BV(1) -#define FUSE_BODLEVEL1 (unsigned char)~_BV(2) -#define FUSE_BODLEVEL2 (unsigned char)~_BV(3) -#define EFUSE_DEFAULT (0xFF) - - -/* Lock Bits */ -#define __LOCK_BITS_EXIST -#define __BOOT_LOCK_BITS_0_EXIST -#define __BOOT_LOCK_BITS_1_EXIST - - -/* Signature */ -#define SIGNATURE_0 0x1E -#define SIGNATURE_1 0x97 -#define SIGNATURE_2 0x81 - -#define SLEEP_MODE_IDLE (0x00<<1) -#define SLEEP_MODE_ADC (0x01<<1) -#define SLEEP_MODE_PWR_DOWN (0x02<<1) -#define SLEEP_MODE_PWR_SAVE (0x03<<1) -#define SLEEP_MODE_STANDBY (0x06<<1) - -#endif /* _AVR_IOCAN128_H_ */ diff --git a/arduino/hardware/tools/avr/avr/include/avr/iocan32.h b/arduino/hardware/tools/avr/avr/include/avr/iocan32.h deleted file mode 100644 index f7c148f..0000000 --- a/arduino/hardware/tools/avr/avr/include/avr/iocan32.h +++ /dev/null @@ -1,100 +0,0 @@ -/* Copyright (c) 2004,2005, Anatoly Sokolov - All rights reserved. - - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - * Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - * Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in - the documentation and/or other materials provided with the - distribution. - - * Neither the name of the copyright holders nor the names of - contributors may be used to endorse or promote products derived - from this software without specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. */ - -/* $Id: iocan32.h 2102 2010-03-16 22:52:39Z joerg_wunsch $ */ - -/* iocan32.h - definitions for CAN32 */ - -#ifndef _AVR_IOCAN32_H_ -#define _AVR_IOCAN32_H_ 1 - -#include - -/* Constants */ -#define SPM_PAGESIZE 256 -#define RAMSTART 0x100 -#define RAMEND 0x08FF /* Last On-Chip SRAM Location */ -#define XRAMEND 0xFFFF -#define E2END 0x03FF -#define E2PAGESIZE 8 -#define FLASHEND 0x7FFF - - -/* Fuses */ - -#define FUSE_MEMORY_SIZE 3 - -/* Low Fuse Byte */ -#define FUSE_CKSEL0 (unsigned char)~_BV(0) -#define FUSE_CKSEL1 (unsigned char)~_BV(1) -#define FUSE_CKSEL2 (unsigned char)~_BV(2) -#define FUSE_CKSEL3 (unsigned char)~_BV(3) -#define FUSE_SUT0 (unsigned char)~_BV(4) -#define FUSE_SUT1 (unsigned char)~_BV(5) -#define FUSE_CKOUT (unsigned char)~_BV(6) -#define FUSE_CKDIV8 (unsigned char)~_BV(7) -#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8) - -/* High Fuse Byte */ -#define FUSE_BOOTRST (unsigned char)~_BV(0) -#define FUSE_BOOTSZ0 (unsigned char)~_BV(1) -#define FUSE_BOOTSZ1 (unsigned char)~_BV(2) -#define FUSE_EESAVE (unsigned char)~_BV(3) -#define FUSE_WDTON (unsigned char)~_BV(4) -#define FUSE_SPIEN (unsigned char)~_BV(5) -#define FUSE_JTAGEN (unsigned char)~_BV(6) -#define FUSE_OCDEN (unsigned char)~_BV(7) -#define HFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_SPIEN & FUSE_JTAGEN) - -/* Extended Fuse Byte */ -#define FUSE_BODLEVEL0 (unsigned char)~_BV(1) -#define FUSE_BODLEVEL1 (unsigned char)~_BV(2) -#define FUSE_BODLEVEL2 (unsigned char)~_BV(3) -#define EFUSE_DEFAULT (0xFF) - - -/* Lock Bits */ -#define __LOCK_BITS_EXIST -#define __BOOT_LOCK_BITS_0_EXIST -#define __BOOT_LOCK_BITS_1_EXIST - - -/* Signature */ -#define SIGNATURE_0 0x1E -#define SIGNATURE_1 0x95 -#define SIGNATURE_2 0x81 - -#define SLEEP_MODE_IDLE (0x00<<1) -#define SLEEP_MODE_ADC (0x01<<1) -#define SLEEP_MODE_PWR_DOWN (0x02<<1) -#define SLEEP_MODE_PWR_SAVE (0x03<<1) -#define SLEEP_MODE_STANDBY (0x06<<1) - -#endif /* _AVR_IOCAN32_H_ */ diff --git a/arduino/hardware/tools/avr/avr/include/avr/iocan64.h b/arduino/hardware/tools/avr/avr/include/avr/iocan64.h deleted file mode 100644 index d07929e..0000000 --- a/arduino/hardware/tools/avr/avr/include/avr/iocan64.h +++ /dev/null @@ -1,100 +0,0 @@ -/* Copyright (c) 2004,2005, Anatoly Sokolov - All rights reserved. - - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - * Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - * Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in - the documentation and/or other materials provided with the - distribution. - - * Neither the name of the copyright holders nor the names of - contributors may be used to endorse or promote products derived - from this software without specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. */ - -/* $Id: iocan64.h 2102 2010-03-16 22:52:39Z joerg_wunsch $ */ - -/* iocan64.h - definitions for CAN64 */ - -#ifndef _AVR_IOCAN64_H_ -#define _AVR_IOCAN64_H_ 1 - -#include - -/* Constants */ -#define SPM_PAGESIZE 256 -#define RAMSTART 0x100 -#define RAMEND 0x10FF /* Last On-Chip SRAM Location */ -#define XRAMEND 0xFFFF -#define E2END 0x07FF -#define E2PAGESIZE 8 -#define FLASHEND 0xFFFF - - -/* Fuses */ - -#define FUSE_MEMORY_SIZE 3 - -/* Low Fuse Byte */ -#define FUSE_CKSEL0 (unsigned char)~_BV(0) -#define FUSE_CKSEL1 (unsigned char)~_BV(1) -#define FUSE_CKSEL2 (unsigned char)~_BV(2) -#define FUSE_CKSEL3 (unsigned char)~_BV(3) -#define FUSE_SUT0 (unsigned char)~_BV(4) -#define FUSE_SUT1 (unsigned char)~_BV(5) -#define FUSE_CKOUT (unsigned char)~_BV(6) -#define FUSE_CKDIV8 (unsigned char)~_BV(7) -#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8) - -/* High Fuse Byte */ -#define FUSE_BOOTRST (unsigned char)~_BV(0) -#define FUSE_BOOTSZ0 (unsigned char)~_BV(1) -#define FUSE_BOOTSZ1 (unsigned char)~_BV(2) -#define FUSE_EESAVE (unsigned char)~_BV(3) -#define FUSE_WDTON (unsigned char)~_BV(4) -#define FUSE_SPIEN (unsigned char)~_BV(5) -#define FUSE_JTAGEN (unsigned char)~_BV(6) -#define FUSE_OCDEN (unsigned char)~_BV(7) -#define HFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_SPIEN & FUSE_JTAGEN) - -/* Extended Fuse Byte */ -#define FUSE_BODLEVEL0 (unsigned char)~_BV(1) -#define FUSE_BODLEVEL1 (unsigned char)~_BV(2) -#define FUSE_BODLEVEL2 (unsigned char)~_BV(3) -#define EFUSE_DEFAULT (0xFF) - - -/* Lock Bits */ -#define __LOCK_BITS_EXIST -#define __BOOT_LOCK_BITS_0_EXIST -#define __BOOT_LOCK_BITS_1_EXIST - - -/* Signature */ -#define SIGNATURE_0 0x1E -#define SIGNATURE_1 0x96 -#define SIGNATURE_2 0x81 - -#define SLEEP_MODE_IDLE (0x00<<1) -#define SLEEP_MODE_ADC (0x01<<1) -#define SLEEP_MODE_PWR_DOWN (0x02<<1) -#define SLEEP_MODE_PWR_SAVE (0x03<<1) -#define SLEEP_MODE_STANDBY (0x06<<1) - -#endif /* _AVR_IOCAN64_H_ */ diff --git a/arduino/hardware/tools/avr/avr/include/avr/iocanxx.h b/arduino/hardware/tools/avr/avr/include/avr/iocanxx.h deleted file mode 100644 index cb58e1b..0000000 --- a/arduino/hardware/tools/avr/avr/include/avr/iocanxx.h +++ /dev/null @@ -1,2020 +0,0 @@ -/* Copyright (c) 2004,2005,2006 Colin O'Flynn - All rights reserved. - - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - * Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - * Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in - the documentation and/or other materials provided with the - distribution. - - * Neither the name of the copyright holders nor the names of - contributors may be used to endorse or promote products derived - from this software without specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. */ - -/* $Id: iocanxx.h 2225 2011-03-02 16:27:26Z arcanum $ */ - -/* This file is based largely on: - - iom128.h by Peter Jansen (bit defines) - - iom169.h by Juergen Schilling - (register addresses) - - AT90CAN128 Datasheet (bit defines and register addresses) - - Appnote on Mega128 --> AT90Can128 Conversion (for what registers I need - to change) */ - -/* iocanxx.h - definitions for AT90CAN32, AT90CAN64 and AT90CAN128 */ - -#ifndef _AVR_IOCANXX_H_ -#define _AVR_IOCANXX_H_ 1 - -/* This file should only be included from , never directly. */ - -#ifndef _AVR_IO_H_ -# error "Include instead of this file." -#endif - -#ifndef _AVR_IOXXX_H_ -# define _AVR_IOXXX_H_ "iocanxx.h" -#else -# error "Attempt to include more than one file." -#endif - -/* I/O registers and bit definitions. */ - -/* RegDef: Port A */ -#define PINA _SFR_IO8(0x00) -#define DDRA _SFR_IO8(0x01) -#define PORTA _SFR_IO8(0x02) - -/* RegDef: Port B */ -#define PINB _SFR_IO8(0x03) -#define DDRB _SFR_IO8(0x04) -#define PORTB _SFR_IO8(0x05) - -/* RegDef: Port C */ -#define PINC _SFR_IO8(0x06) -#define DDRC _SFR_IO8(0x07) -#define PORTC _SFR_IO8(0x08) - -/* RegDef: Port D */ -#define PIND _SFR_IO8(0x09) -#define DDRD _SFR_IO8(0x0A) -#define PORTD _SFR_IO8(0x0B) - -/* RegDef: Port E */ -#define PINE _SFR_IO8(0x0C) -#define DDRE _SFR_IO8(0x0D) -#define PORTE _SFR_IO8(0x0E) - -/* RegDef: Port F */ -#define PINF _SFR_IO8(0x0F) -#define DDRF _SFR_IO8(0x10) -#define PORTF _SFR_IO8(0x11) - -/* RegDef: Port G */ -#define PING _SFR_IO8(0x12) -#define DDRG _SFR_IO8(0x13) -#define PORTG _SFR_IO8(0x14) - -/* RegDef: Timer/Counter 0 interrupt Flag Register */ -#define TIFR0 _SFR_IO8(0x15) - -/* RegDef: Timer/Counter 1 interrupt Flag Register */ -#define TIFR1 _SFR_IO8(0x16) - -/* RegDef: Timer/Counter 2 interrupt Flag Register */ -#define TIFR2 _SFR_IO8(0x17) - -/* RegDef: Timer/Counter 3 interrupt Flag Register */ -#define TIFR3 _SFR_IO8(0x18) - -/* RegDef: External Interrupt Flag Register */ -#define EIFR _SFR_IO8(0x1C) - -/* RegDef: External Interrupt Mask Register */ -#define EIMSK _SFR_IO8(0x1D) - -/* RegDef: General Purpose I/O Register 0 */ -#define GPIOR0 _SFR_IO8(0x1E) - -/* RegDef: EEPROM Control Register */ -#define EECR _SFR_IO8(0x1F) - -/* RegDef: EEPROM Data Register */ -#define EEDR _SFR_IO8(0x20) - -/* RegDef: EEPROM Address Register */ -#define EEAR _SFR_IO16(0x21) -#define EEARL _SFR_IO8(0x21) -#define EEARH _SFR_IO8(0x22) - -/* 6-char sequence denoting where to find the EEPROM registers in memory space. - Adresses denoted in hex syntax with uppercase letters. Used by the EEPROM - subroutines. - First two letters: EECR address. - Second two letters: EEDR address. - Last two letters: EEAR address. */ -#define __EEPROM_REG_LOCATIONS__ 1F2021 - -/* RegDef: General Timer/Counter Control Register */ -#define GTCCR _SFR_IO8(0x23) - -/* RegDef: Timer/Counter Control Register A */ -#define TCCR0A _SFR_IO8(0x24) - -/* RegDef: Timer/Counter Register */ -#define TCNT0 _SFR_IO8(0x26) - -/* RegDef: Output Compare Register A */ -#define OCR0A _SFR_IO8(0x27) - -/* RegDef: General Purpose I/O Register 1 */ -#define GPIOR1 _SFR_IO8(0x2A) - -/* RegDef: General Purpose I/O Register 2 */ -#define GPIOR2 _SFR_IO8(0x2B) - -/* RegDef: SPI Control Register */ -#define SPCR _SFR_IO8(0x2C) - -/* RegDef: SPI Status Register */ -#define SPSR _SFR_IO8(0x2D) - -/* RegDef: SPI Data Register */ -#define SPDR _SFR_IO8(0x2E) - -/* RegDef: Analog Comperator Control and Status Register */ -#define ACSR _SFR_IO8(0x30) - -/* RegDef: On-chip Debug Register */ -#define OCDR _SFR_IO8(0x31) - -/* RegDef: Sleep Mode Control Register */ -#define SMCR _SFR_IO8(0x33) - -/* RegDef: MCU Status Register */ -#define MCUSR _SFR_IO8(0x34) - -/* RegDef: MCU Control Rgeister */ -#define MCUCR _SFR_IO8(0x35) - -/* RegDef: Store Program Memory Control and Status Register */ -#define SPMCSR _SFR_IO8(0x37) - -/* RegDef: RAMPZ register. */ -#define RAMPZ _SFR_IO8(0x3B) - -/* RegDef: Watchdog Timer Control Register */ -#define WDTCR _SFR_MEM8(0x60) - -/* RegDef: Clock Prescale Register */ -#define CLKPR _SFR_MEM8(0x61) - -/* RegDef: Oscillator Calibration Register */ -#define OSCCAL _SFR_MEM8(0x66) - -/* RegDef: External Interrupt Control Register A */ -#define EICRA _SFR_MEM8(0x69) - -/* RegDef: External Interrupt Control Register B */ -#define EICRB _SFR_MEM8(0x6A) - -/* RegDef: Timer/Counter 0 Interrupt Mask Register */ -#define TIMSK0 _SFR_MEM8(0x6E) - -/* RegDef: Timer/Counter 1 Interrupt Mask Register */ -#define TIMSK1 _SFR_MEM8(0x6F) - -/* RegDef: Timer/Counter 2 Interrupt Mask Register */ -#define TIMSK2 _SFR_MEM8(0x70) - -/* RegDef: Timer/Counter 3 Interrupt Mask Register */ -#define TIMSK3 _SFR_MEM8(0x71) - -/* RegDef: External Memory Control Register A */ -#define XMCRA _SFR_MEM8(0x74) - -/* RegDef: External Memory Control Register A */ -#define XMCRB _SFR_MEM8(0x75) - -/* RegDef: ADC Data Register */ -#ifndef __ASSEMBLER__ -#define ADC _SFR_MEM16(0x78) -#endif -#define ADCW _SFR_MEM16(0x78) -#define ADCL _SFR_MEM8(0x78) -#define ADCH _SFR_MEM8(0x79) - -/* RegDef: ADC Control and Status Register A */ -#define ADCSRA _SFR_MEM8(0x7A) - -/* RegDef: ADC Control and Status Register B */ -#define ADCSRB _SFR_MEM8(0x7B) - -/* RegDef: ADC Multiplex Selection Register */ -#define ADMUX _SFR_MEM8(0x7C) - -/* RegDef: Digital Input Disable Register 0 */ -#define DIDR0 _SFR_MEM8(0x7E) - -/* RegDef: Digital Input Disable Register 1 */ -#define DIDR1 _SFR_MEM8(0x7F) - -/* RegDef: Timer/Counter1 Control Register A */ -#define TCCR1A _SFR_MEM8(0x80) - -/* RegDef: Timer/Counter1 Control Register B */ -#define TCCR1B _SFR_MEM8(0x81) - -/* RegDef: Timer/Counter1 Control Register C */ -#define TCCR1C _SFR_MEM8(0x82) - -/* RegDef: Timer/Counter1 Register */ -#define TCNT1 _SFR_MEM16(0x84) -#define TCNT1L _SFR_MEM8(0x84) -#define TCNT1H _SFR_MEM8(0x85) - -/* RegDef: Timer/Counter1 Input Capture Register */ -#define ICR1 _SFR_MEM16(0x86) -#define ICR1L _SFR_MEM8(0x86) -#define ICR1H _SFR_MEM8(0x87) - -/* RegDef: Timer/Counter1 Output Compare Register A */ -#define OCR1A _SFR_MEM16(0x88) -#define OCR1AL _SFR_MEM8(0x88) -#define OCR1AH _SFR_MEM8(0x89) - -/* RegDef: Timer/Counter1 Output Compare Register B */ -#define OCR1B _SFR_MEM16(0x8A) -#define OCR1BL _SFR_MEM8(0x8A) -#define OCR1BH _SFR_MEM8(0x8B) - -/* RegDef: Timer/Counter1 Output Compare Register C */ -#define OCR1C _SFR_MEM16(0x8C) -#define OCR1CL _SFR_MEM8(0x8C) -#define OCR1CH _SFR_MEM8(0x8D) - -/* RegDef: Timer/Counter3 Control Register A */ -#define TCCR3A _SFR_MEM8(0x90) - -/* RegDef: Timer/Counter3 Control Register B */ -#define TCCR3B _SFR_MEM8(0x91) - -/* RegDef: Timer/Counter3 Control Register C */ -#define TCCR3C _SFR_MEM8(0x92) - -/* RegDef: Timer/Counter3 Register */ -#define TCNT3 _SFR_MEM16(0x94) -#define TCNT3L _SFR_MEM8(0x94) -#define TCNT3H _SFR_MEM8(0x95) - -/* RegDef: Timer/Counter3 Input Capture Register */ -#define ICR3 _SFR_MEM16(0x96) -#define ICR3L _SFR_MEM8(0x96) -#define ICR3H _SFR_MEM8(0x97) - -/* RegDef: Timer/Counter3 Output Compare Register A */ -#define OCR3A _SFR_MEM16(0x98) -#define OCR3AL _SFR_MEM8(0x98) -#define OCR3AH _SFR_MEM8(0x99) - -/* RegDef: Timer/Counter3 Output Compare Register B */ -#define OCR3B _SFR_MEM16(0x9A) -#define OCR3BL _SFR_MEM8(0x9A) -#define OCR3BH _SFR_MEM8(0x9B) - -/* RegDef: Timer/Counter3 Output Compare Register C */ -#define OCR3C _SFR_MEM16(0x9C) -#define OCR3CL _SFR_MEM8(0x9C) -#define OCR3CH _SFR_MEM8(0x9D) - -/* RegDef: Timer/Counter2 Control Register A */ -#define TCCR2A _SFR_MEM8(0xB0) - -/* RegDef: Timer/Counter2 Register */ -#define TCNT2 _SFR_MEM8(0xB2) - -/* RegDef: Timer/Counter2 Output Compare Register */ -#define OCR2A _SFR_MEM8(0xB3) - -/* RegDef: Asynchronous Status Register */ -#define ASSR _SFR_MEM8(0xB6) - -/* RegDef: TWI Bit Rate Register */ -#define TWBR _SFR_MEM8(0xB8) - -/* RegDef: TWI Status Register */ -#define TWSR _SFR_MEM8(0xB9) - -/* RegDef: TWI (Slave) Address Register */ -#define TWAR _SFR_MEM8(0xBA) - -/* RegDef: TWI Data Register */ -#define TWDR _SFR_MEM8(0xBB) - -/* RegDef: TWI Control Register */ -#define TWCR _SFR_MEM8(0xBC) - -/* RegDef: USART0 Control and Status Register A */ -#define UCSR0A _SFR_MEM8(0xC0) - -/* RegDef: USART0 Control and Status Register B */ -#define UCSR0B _SFR_MEM8(0xC1) - -/* RegDef: USART0 Control and Status Register C */ -#define UCSR0C _SFR_MEM8(0xC2) - -/* RegDef: USART0 Baud Rate Register */ -#define UBRR0 _SFR_MEM16(0xC4) -#define UBRR0L _SFR_MEM8(0xC4) -#define UBRR0H _SFR_MEM8(0xC5) - -/* RegDef: USART0 I/O Data Register */ -#define UDR0 _SFR_MEM8(0xC6) - -/* RegDef: USART1 Control and Status Register A */ -#define UCSR1A _SFR_MEM8(0xC8) - -/* RegDef: USART1 Control and Status Register B */ -#define UCSR1B _SFR_MEM8(0xC9) - -/* RegDef: USART1 Control and Status Register C */ -#define UCSR1C _SFR_MEM8(0xCA) - -/* RegDef: USART1 Baud Rate Register */ -#define UBRR1 _SFR_MEM16(0xCC) -#define UBRR1L _SFR_MEM8(0xCC) -#define UBRR1H _SFR_MEM8(0xCD) - -/* RegDef: USART1 I/O Data Register */ -#define UDR1 _SFR_MEM8(0xCE) - -/* RegDef: CAN General Control Register*/ -#define CANGCON _SFR_MEM8(0xD8) - -/* RegDef: CAN General Status Register*/ -#define CANGSTA _SFR_MEM8(0xD9) - -/* RegDef: CAN General Interrupt Register*/ -#define CANGIT _SFR_MEM8(0xDA) - -/* RegDef: CAN General Interrupt Enable Register*/ -#define CANGIE _SFR_MEM8(0xDB) - -/* Word Definition: CAN Enable MOb Register*/ -#define CANEN _SFR_MEM16(0xDC) - -/* RegDef: CAN Enable MOb Register*/ -#define CANEN2 _SFR_MEM8(0xDC) - -/* RegDef: CAN Enable MOb Register*/ -#define CANEN1 _SFR_MEM8(0xDD) - -/* Word Definition: CAN Enable Interrupt MOb Register*/ -#define CANIE _SFR_MEM16(0xDE) - -/* RegDef: CAN Enable Interrupt MOb Register*/ -#define CANIE2 _SFR_MEM8(0xDE) - -/* RegDef: CAN Enable Interrupt MOb Register*/ -#define CANIE1 _SFR_MEM8(0xDF) - -/* RegDef: CAN Status Interrupt MOb Register*/ -/* - * WARNING: Do not apply the SIT8...SIT14 constants to bits in the CANSIT - * register. - */ -#define CANSIT _SFR_MEM16(0xE0) -#define CANSIT2 _SFR_MEM8(0xE0) -#define CANSIT1 _SFR_MEM8(0xE1) - -/* RegDef: CAN Bit Timing Register 1*/ -#define CANBT1 _SFR_MEM8(0xE2) - -/* RegDef: CAN Bit Timing Register 2*/ -#define CANBT2 _SFR_MEM8(0xE3) - -/* RegDef: CAN Bit Timing Register 3*/ -#define CANBT3 _SFR_MEM8(0xE4) - -/* RegDef: CAN Timer Control Register*/ -#define CANTCON _SFR_MEM8(0xE5) - -/* RegDef: CAN Timer Register*/ -#define CANTIM _SFR_MEM16(0xE6) -#define CANTIML _SFR_MEM8(0xE6) -#define CANTIMH _SFR_MEM8(0xE7) - -/* RegDef: CAN TTC Timer Register*/ -#define CANTTC _SFR_MEM16(0xE8) -#define CANTTCL _SFR_MEM8(0xE8) -#define CANTTCH _SFR_MEM8(0xE9) - -/* RegDef: CAN Transmitt Error Counter Register*/ -#define CANTEC _SFR_MEM8(0xEA) - -/* RegDef: CAN Receive Error Counter Register*/ -#define CANREC _SFR_MEM8(0xEB) - -/* RegDef: CAN Highest Priority MOb Register*/ -#define CANHPMOB _SFR_MEM8(0xEC) - -/* RegDef: CAN Page MOb Register*/ -#define CANPAGE _SFR_MEM8(0xED) - -/* RegDef: CAN MOb Status Register*/ -#define CANSTMOB _SFR_MEM8(0xEE) - -/* RegDef: CAN MOb Control and DLC Register*/ -#define CANCDMOB _SFR_MEM8(0xEF) - -/* RegDef: CAN Identifier Tag Registers*/ -#define CANIDT _SFR_MEM32(0xF0) - -#define CANIDT4 _SFR_MEM8(0xF0) -#define CANIDT3 _SFR_MEM8(0xF1) -#define CANIDT2 _SFR_MEM8(0xF2) -#define CANIDT1 _SFR_MEM8(0xF3) - -/* RegDef: CAN Identifier Mask Registers */ -#define CANIDM _SFR_MEM32(0xF4) - -#define CANIDM4 _SFR_MEM8(0xF4) -#define CANIDM3 _SFR_MEM8(0xF5) -#define CANIDM2 _SFR_MEM8(0xF6) -#define CANIDM1 _SFR_MEM8(0xF7) - -/* RegDef: CAN TTC Timer Register*/ -#define CANSTM _SFR_MEM16(0xF8) -#define CANSTML _SFR_MEM8(0xF8) -#define CANSTMH _SFR_MEM8(0xF9) - -/* RegDef: CAN Message Register*/ -#define CANMSG _SFR_MEM8(0xFA) - -/* Interrupt vectors */ - -/* External Interrupt Request 0 */ -#define INT0_vect_num 1 -#define INT0_vect _VECTOR(1) -#define SIG_INTERRUPT0 _VECTOR(1) - -/* External Interrupt Request 1 */ -#define INT1_vect_num 2 -#define INT1_vect _VECTOR(2) -#define SIG_INTERRUPT1 _VECTOR(2) - -/* External Interrupt Request 2 */ -#define INT2_vect_num 3 -#define INT2_vect _VECTOR(3) -#define SIG_INTERRUPT2 _VECTOR(3) - -/* External Interrupt Request 3 */ -#define INT3_vect_num 4 -#define INT3_vect _VECTOR(4) -#define SIG_INTERRUPT3 _VECTOR(4) - -/* External Interrupt Request 4 */ -#define INT4_vect_num 5 -#define INT4_vect _VECTOR(5) -#define SIG_INTERRUPT4 _VECTOR(5) - -/* External Interrupt Request 5 */ -#define INT5_vect_num 6 -#define INT5_vect _VECTOR(6) -#define SIG_INTERRUPT5 _VECTOR(6) - -/* External Interrupt Request 6 */ -#define INT6_vect_num 7 -#define INT6_vect _VECTOR(7) -#define SIG_INTERRUPT6 _VECTOR(7) - -/* External Interrupt Request 7 */ -#define INT7_vect_num 8 -#define INT7_vect _VECTOR(8) -#define SIG_INTERRUPT7 _VECTOR(8) - -/* Timer/Counter2 Compare Match */ -#define TIMER2_COMP_vect_num 9 -#define TIMER2_COMP_vect _VECTOR(9) -#define SIG_OUTPUT_COMPARE2 _VECTOR(9) - -/* Timer/Counter2 Overflow */ -#define TIMER2_OVF_vect_num 10 -#define TIMER2_OVF_vect _VECTOR(10) -#define SIG_OVERFLOW2 _VECTOR(10) - -/* Timer/Counter1 Capture Event */ -#define TIMER1_CAPT_vect_num 11 -#define TIMER1_CAPT_vect _VECTOR(11) -#define SIG_INPUT_CAPTURE1 _VECTOR(11) - -/* Timer/Counter1 Compare Match A */ -#define TIMER1_COMPA_vect_num 12 -#define TIMER1_COMPA_vect _VECTOR(12) -#define SIG_OUTPUT_COMPARE1A _VECTOR(12) - -/* Timer/Counter Compare Match B */ -#define TIMER1_COMPB_vect_num 13 -#define TIMER1_COMPB_vect _VECTOR(13) -#define SIG_OUTPUT_COMPARE1B _VECTOR(13) - -/* Timer/Counter1 Compare Match C */ -#define TIMER1_COMPC_vect_num 14 -#define TIMER1_COMPC_vect _VECTOR(14) -#define SIG_OUTPUT_COMPARE1C _VECTOR(14) - -/* Timer/Counter1 Overflow */ -#define TIMER1_OVF_vect_num 15 -#define TIMER1_OVF_vect _VECTOR(15) -#define SIG_OVERFLOW1 _VECTOR(15) - -/* Timer/Counter0 Compare Match */ -#define TIMER0_COMP_vect_num 16 -#define TIMER0_COMP_vect _VECTOR(16) -#define SIG_OUTPUT_COMPARE0 _VECTOR(16) - -/* Timer/Counter0 Overflow */ -#define TIMER0_OVF_vect_num 17 -#define TIMER0_OVF_vect _VECTOR(17) -#define SIG_OVERFLOW0 _VECTOR(17) - -/* CAN Transfer Complete or Error */ -#define CANIT_vect_num 18 -#define CANIT_vect _VECTOR(18) -#define SIG_CAN_INTERRUPT1 _VECTOR(18) - -/* CAN Timer Overrun */ -#define OVRIT_vect_num 19 -#define OVRIT_vect _VECTOR(19) -#define SIG_CAN_OVERFLOW1 _VECTOR(19) - -/* SPI Serial Transfer Complete */ -#define SPI_STC_vect_num 20 -#define SPI_STC_vect _VECTOR(20) -#define SIG_SPI _VECTOR(20) - -/* USART0, Rx Complete */ -#define USART0_RX_vect_num 21 -#define USART0_RX_vect _VECTOR(21) -#define SIG_UART0_RECV _VECTOR(21) -#define SIG_USART0_RECV _VECTOR(21) - -/* USART0 Data Register Empty */ -#define USART0_UDRE_vect_num 22 -#define USART0_UDRE_vect _VECTOR(22) -#define SIG_UART0_DATA _VECTOR(22) -#define SIG_USART0_DATA _VECTOR(22) - -/* USART0, Tx Complete */ -#define USART0_TX_vect_num 23 -#define USART0_TX_vect _VECTOR(23) -#define SIG_UART0_TRANS _VECTOR(23) -#define SIG_USART0_TRANS _VECTOR(23) - -/* Analog Comparator */ -#define ANALOG_COMP_vect_num 24 -#define ANALOG_COMP_vect _VECTOR(24) -#define SIG_COMPARATOR _VECTOR(24) - -/* ADC Conversion Complete */ -#define ADC_vect_num 25 -#define ADC_vect _VECTOR(25) -#define SIG_ADC _VECTOR(25) - -/* EEPROM Ready */ -#define EE_READY_vect_num 26 -#define EE_READY_vect _VECTOR(26) -#define SIG_EEPROM_READY _VECTOR(26) - -/* Timer/Counter3 Capture Event */ -#define TIMER3_CAPT_vect_num 27 -#define TIMER3_CAPT_vect _VECTOR(27) -#define SIG_INPUT_CAPTURE3 _VECTOR(27) - -/* Timer/Counter3 Compare Match A */ -#define TIMER3_COMPA_vect_num 28 -#define TIMER3_COMPA_vect _VECTOR(28) -#define SIG_OUTPUT_COMPARE3A _VECTOR(28) - -/* Timer/Counter3 Compare Match B */ -#define TIMER3_COMPB_vect_num 29 -#define TIMER3_COMPB_vect _VECTOR(29) -#define SIG_OUTPUT_COMPARE3B _VECTOR(29) - -/* Timer/Counter3 Compare Match C */ -#define TIMER3_COMPC_vect_num 30 -#define TIMER3_COMPC_vect _VECTOR(30) -#define SIG_OUTPUT_COMPARE3C _VECTOR(30) - -/* Timer/Counter3 Overflow */ -#define TIMER3_OVF_vect_num 31 -#define TIMER3_OVF_vect _VECTOR(31) -#define SIG_OVERFLOW3 _VECTOR(31) - -/* USART1, Rx Complete */ -#define USART1_RX_vect_num 32 -#define USART1_RX_vect _VECTOR(32) -#define SIG_UART1_RECV _VECTOR(32) -#define SIG_USART1_RECV _VECTOR(32) - -/* USART1, Data Register Empty */ -#define USART1_UDRE_vect_num 33 -#define USART1_UDRE_vect _VECTOR(33) -#define SIG_UART1_DATA _VECTOR(33) -#define SIG_USART1_DATA _VECTOR(33) - -/* USART1, Tx Complete */ -#define USART1_TX_vect_num 34 -#define USART1_TX_vect _VECTOR(34) -#define SIG_UART1_TRANS _VECTOR(34) -#define SIG_USART1_TRANS _VECTOR(34) - -/* 2-wire Serial Interface */ -#define TWI_vect_num 35 -#define TWI_vect _VECTOR(35) -#define SIG_2WIRE_SERIAL _VECTOR(35) - -/* Store Program Memory Read */ -#define SPM_READY_vect_num 36 -#define SPM_READY_vect _VECTOR(36) -#define SIG_SPM_READY _VECTOR(36) - -#define _VECTORS_SIZE 148 - -/* The Register Bit names are represented by their bit number (0-7). */ - -/* Register Bits [ASSR] */ -/* Asynchronous Status Register */ -#define EXCLK 4 -#define AS2 3 -#define TCN2UB 2 -#define OCR2UB 1 -#define TCR2UB 0 -/* End Register Bits */ - -/* Register Bits [TWCR] */ -/* 2-wire Control Register - TWCR */ -#define TWINT 7 -#define TWEA 6 -#define TWSTA 5 -#define TWSTO 4 -#define TWWC 3 -#define TWEN 2 -#define TWIE 0 -/* End Register Bits */ - -/* Register Bits [TWAR] */ -/* 2-wire Address Register - TWAR */ -#define TWA6 7 -#define TWA5 6 -#define TWA4 5 -#define TWA3 4 -#define TWA2 3 -#define TWA1 2 -#define TWA0 1 -#define TWGCE 0 -/* End Register Bits */ - -/* Register Bits [TWSR] */ -/* 2-wire Status Register - TWSR */ -#define TWS7 7 -#define TWS6 6 -#define TWS5 5 -#define TWS4 4 -#define TWS3 3 -#define TWPS1 1 -#define TWPS0 0 -/* End Register Bits */ - -/* Register Bits [XMCRB] */ -/* External Memory Control Register B - XMCRB */ -#define XMBK 7 -#define XMM2 2 -#define XMM1 1 -#define XMM0 0 -/* End Register Bits */ - -/* Register Bits [XMCRA] */ -/* External Memory Control Register A - XMCRA */ -#define SRE 7 -#define SRL2 6 -#define SRL1 5 -#define SRL0 4 -#define SRW11 3 -#define SRW10 2 -#define SRW01 1 -#define SRW00 0 -/* End Register Bits */ - -/* Register Bits [RAMPZ] */ -/* RAM Page Z select register - RAMPZ */ -#define RAMPZ0 0 -/* End Register Bits */ - -/* Register Bits [EICRA] */ -/* External Interrupt Control Register A - EICRA */ -#define ISC31 7 -#define ISC30 6 -#define ISC21 5 -#define ISC20 4 -#define ISC11 3 -#define ISC10 2 -#define ISC01 1 -#define ISC00 0 -/* End Register Bits */ - -/* Register Bits [EICRB] */ -/* External Interrupt Control Register B - EICRB */ -#define ISC71 7 -#define ISC70 6 -#define ISC61 5 -#define ISC60 4 -#define ISC51 3 -#define ISC50 2 -#define ISC41 1 -#define ISC40 0 -/* End Register Bits */ - -/* Register Bits [SPMCSR] */ -/* Store Program Memory Control Register - SPMCSR, SPMCR */ -#define SPMIE 7 -#define RWWSB 6 -#define RWWSRE 4 -#define BLBSET 3 -#define PGWRT 2 -#define PGERS 1 -#define SPMEN 0 -/* End Register Bits */ - -/* Register Bits [EIMSK] */ -/* External Interrupt MaSK register - EIMSK */ -#define INT7 7 -#define INT6 6 -#define INT5 5 -#define INT4 4 -#define INT3 3 -#define INT2 2 -#define INT1 1 -#define INT0 0 -/* End Register Bits */ - -/* Register Bits [EIFR] */ -/* External Interrupt Flag Register - EIFR */ -#define INTF7 7 -#define INTF6 6 -#define INTF5 5 -#define INTF4 4 -#define INTF3 3 -#define INTF2 2 -#define INTF1 1 -#define INTF0 0 -/* End Register Bits */ - -/* Register Bits [TCCR2] */ -/* Timer/Counter 2 Control Register - TCCR2 */ -#define FOC2A 7 -#define WGM20 6 -#define COM2A1 5 -#define COM2A0 4 -#define WGM21 3 -#define CS22 2 -#define CS21 1 -#define CS20 0 -/* End Register Bits */ - -/* Register Bits [TCCR1A] */ -/* Timer/Counter 1 Control and Status Register A - TCCR1A */ -#define COM1A1 7 -#define COM1A0 6 -#define COM1B1 5 -#define COM1B0 4 -#define COM1C1 3 -#define COM1C0 2 -#define WGM11 1 -#define WGM10 0 -/* End Register Bits */ - -/* Register Bits [TCCR3A] */ -/* Timer/Counter 3 Control and Status Register A - TCCR3A */ -#define COM3A1 7 -#define COM3A0 6 -#define COM3B1 5 -#define COM3B0 4 -#define COM3C1 3 -#define COM3C0 2 -#define WGM31 1 -#define WGM30 0 -/* End Register Bits */ - -/* Register Bits [TCCR1B] */ -/* Timer/Counter 1 Control and Status Register B - TCCR1B */ -#define ICNC1 7 -#define ICES1 6 -#define WGM13 4 -#define WGM12 3 -#define CS12 2 -#define CS11 1 -#define CS10 0 -/* End Register Bits */ - -/* Register Bits [TCCR3B] */ -/* Timer/Counter 3 Control and Status Register B - TCCR3B */ -#define ICNC3 7 -#define ICES3 6 -#define WGM33 4 -#define WGM32 3 -#define CS32 2 -#define CS31 1 -#define CS30 0 -/* End Register Bits */ - -/* Register Bits [TCCR3C] */ -/* Timer/Counter 3 Control Register C - TCCR3C */ -#define FOC3A 7 -#define FOC3B 6 -#define FOC3C 5 -/* End Register Bits */ - -/* Register Bits [TCCR1C] */ -/* Timer/Counter 1 Control Register C - TCCR1C */ -#define FOC1A 7 -#define FOC1B 6 -#define FOC1C 5 -/* End Register Bits */ - -/* Register Bits [OCDR] */ -/* On-chip Debug Register - OCDR */ -#define IDRD 7 -#define OCDR7 7 -#define OCDR6 6 -#define OCDR5 5 -#define OCDR4 4 -#define OCDR3 3 -#define OCDR2 2 -#define OCDR1 1 -#define OCDR0 0 -/* End Register Bits */ - -/* Register Bits [WDTCR] */ -/* Watchdog Timer Control Register - WDTCR */ -#define WDCE 4 -#define WDE 3 -#define WDP2 2 -#define WDP1 1 -#define WDP0 0 -/* End Register Bits */ - -/* Register Bits [SPSR] */ -/* SPI Status Register - SPSR */ -#define SPIF 7 -#define WCOL 6 -#define SPI2X 0 -/* End Register Bits */ - -/* Register Bits [SPCR] */ -/* SPI Control Register - SPCR */ -#define SPIE 7 -#define SPE 6 -#define DORD 5 -#define MSTR 4 -#define CPOL 3 -#define CPHA 2 -#define SPR1 1 -#define SPR0 0 -/* End Register Bits */ - -/* Register Bits [UCSR1C] */ -/* USART1 Register C - UCSR1C */ -#define UMSEL1 6 -#define UPM11 5 -#define UPM10 4 -#define USBS1 3 -#define UCSZ11 2 -#define UCSZ10 1 -#define UCPOL1 0 -/* End Register Bits */ - -/* Register Bits [UCSR0C] */ -/* USART0 Register C - UCSR0C */ -#define UMSEL0 6 -#define UPM01 5 -#define UPM00 4 -#define USBS0 3 -#define UCSZ01 2 -#define UCSZ00 1 -#define UCPOL0 0 -/* End Register Bits */ - -/* Register Bits [UCSR1A] */ -/* USART1 Status Register A - UCSR1A */ -#define RXC1 7 -#define TXC1 6 -#define UDRE1 5 -#define FE1 4 -#define DOR1 3 -#define UPE1 2 -#define U2X1 1 -#define MPCM1 0 -/* End Register Bits */ - -/* Register Bits [UCSR0A] */ -/* USART0 Status Register A - UCSR0A */ -#define RXC0 7 -#define TXC0 6 -#define UDRE0 5 -#define FE0 4 -#define DOR0 3 -#define UPE0 2 -#define U2X0 1 -#define MPCM0 0 -/* End Register Bits */ - -/* Register Bits [UCSR1B] */ -/* USART1 Control Register B - UCSR1B */ -#define RXCIE1 7 -#define TXCIE1 6 -#define UDRIE1 5 -#define RXEN1 4 -#define TXEN1 3 -#define UCSZ12 2 -#define RXB81 1 -#define TXB81 0 -/* End Register Bits */ - -/* Register Bits [UCSR0B] */ -/* USART0 Control Register B - UCSR0B */ -#define RXCIE0 7 -#define TXCIE0 6 -#define UDRIE0 5 -#define RXEN0 4 -#define TXEN0 3 -#define UCSZ02 2 -#define RXB80 1 -#define TXB80 0 -/* End Register Bits */ - -/* Register Bits [ACSR] */ -/* Analog Comparator Control and Status Register - ACSR */ -#define ACD 7 -#define ACBG 6 -#define ACO 5 -#define ACI 4 -#define ACIE 3 -#define ACIC 2 -#define ACIS1 1 -#define ACIS0 0 -/* End Register Bits */ - -/* Register Bits [ADCSRA] */ -/* ADC Control and status register - ADCSRA */ -#define ADEN 7 -#define ADSC 6 -#define ADATE 5 -#define ADIF 4 -#define ADIE 3 -#define ADPS2 2 -#define ADPS1 1 -#define ADPS0 0 -/* End Register Bits */ - -/* - The ADHSM bit has been removed from all documentation, - as being not needed at all since the comparator has proven - to be fast enough even without feeding it more power. -*/ - -/* Register Bits [ADCSRB] */ -/* ADC Control and status register - ADCSRB */ -#define ACME 6 -#define ADTS2 2 -#define ADTS1 1 -#define ADTS0 0 -/* End Register Bits */ - -/* Register Bits [ADMUX] */ -/* ADC Multiplexer select - ADMUX */ -#define REFS1 7 -#define REFS0 6 -#define ADLAR 5 -#define MUX4 4 -#define MUX3 3 -#define MUX2 2 -#define MUX1 1 -#define MUX0 0 -/* End Register Bits */ - -/* Register Bits [DIDR0] */ -/* Digital Input Disable Register 0 */ -#define ADC7D 7 -#define ADC6D 6 -#define ADC5D 5 -#define ADC4D 4 -#define ADC3D 3 -#define ADC2D 2 -#define ADC1D 1 -#define ADC0D 0 -/* End Register Bits */ - -/* Register Bits [DIDR1] */ -/* Digital Input Disable Register 1 */ -#define AIN1D 1 -#define AIN0D 0 -/* End Register Bits */ - -/* Register Bits [PORTA] */ -/* Port A Data Register - PORTA */ -#define PA7 7 -#define PA6 6 -#define PA5 5 -#define PA4 4 -#define PA3 3 -#define PA2 2 -#define PA1 1 -#define PA0 0 -/* End Register Bits */ - -/* Register Bits [DDRA] */ -/* Port A Data Direction Register - DDRA */ -#define DDA7 7 -#define DDA6 6 -#define DDA5 5 -#define DDA4 4 -#define DDA3 3 -#define DDA2 2 -#define DDA1 1 -#define DDA0 0 -/* End Register Bits */ - -/* Register Bits [PINA] */ -/* Port A Input Pins - PINA */ -#define PINA7 7 -#define PINA6 6 -#define PINA5 5 -#define PINA4 4 -#define PINA3 3 -#define PINA2 2 -#define PINA1 1 -#define PINA0 0 -/* End Register Bits */ - -/* Register Bits [PORTB] */ -/* Port B Data Register - PORTB */ -#define PB7 7 -#define PB6 6 -#define PB5 5 -#define PB4 4 -#define PB3 3 -#define PB2 2 -#define PB1 1 -#define PB0 0 -/* End Register Bits */ - -/* Register Bits [DDRB] */ -/* Port B Data Direction Register - DDRB */ -#define DDB7 7 -#define DDB6 6 -#define DDB5 5 -#define DDB4 4 -#define DDB3 3 -#define DDB2 2 -#define DDB1 1 -#define DDB0 0 -/* End Register Bits */ - -/* Register Bits [PINB] */ -/* Port B Input Pins - PINB */ -#define PINB7 7 -#define PINB6 6 -#define PINB5 5 -#define PINB4 4 -#define PINB3 3 -#define PINB2 2 -#define PINB1 1 -#define PINB0 0 -/* End Register Bits */ - -/* Register Bits [PORTC] */ -/* Port C Data Register - PORTC */ -#define PC7 7 -#define PC6 6 -#define PC5 5 -#define PC4 4 -#define PC3 3 -#define PC2 2 -#define PC1 1 -#define PC0 0 -/* End Register Bits */ - -/* Register Bits [DDRC] */ -/* Port C Data Direction Register - DDRC */ -#define DDC7 7 -#define DDC6 6 -#define DDC5 5 -#define DDC4 4 -#define DDC3 3 -#define DDC2 2 -#define DDC1 1 -#define DDC0 0 -/* End Register Bits */ - -/* Register Bits [PINC] */ -/* Port C Input Pins - PINC */ -#define PINC7 7 -#define PINC6 6 -#define PINC5 5 -#define PINC4 4 -#define PINC3 3 -#define PINC2 2 -#define PINC1 1 -#define PINC0 0 -/* End Register Bits */ - -/* Register Bits [PORTD] */ -/* Port D Data Register - PORTD */ -#define PD7 7 -#define PD6 6 -#define PD5 5 -#define PD4 4 -#define PD3 3 -#define PD2 2 -#define PD1 1 -#define PD0 0 -/* End Register Bits */ - -/* Register Bits [DDRD] */ -/* Port D Data Direction Register - DDRD */ -#define DDD7 7 -#define DDD6 6 -#define DDD5 5 -#define DDD4 4 -#define DDD3 3 -#define DDD2 2 -#define DDD1 1 -#define DDD0 0 -/* End Register Bits */ - -/* Register Bits [PIND] */ -/* Port D Input Pins - PIND */ -#define PIND7 7 -#define PIND6 6 -#define PIND5 5 -#define PIND4 4 -#define PIND3 3 -#define PIND2 2 -#define PIND1 1 -#define PIND0 0 -/* End Register Bits */ - -/* Register Bits [PORTE] */ -/* Port E Data Register - PORTE */ -#define PE7 7 -#define PE6 6 -#define PE5 5 -#define PE4 4 -#define PE3 3 -#define PE2 2 -#define PE1 1 -#define PE0 0 -/* End Register Bits */ - -/* Register Bits [DDRE] */ -/* Port E Data Direction Register - DDRE */ -#define DDE7 7 -#define DDE6 6 -#define DDE5 5 -#define DDE4 4 -#define DDE3 3 -#define DDE2 2 -#define DDE1 1 -#define DDE0 0 -/* End Register Bits */ - -/* Register Bits [PINE] */ -/* Port E Input Pins - PINE */ -#define PINE7 7 -#define PINE6 6 -#define PINE5 5 -#define PINE4 4 -#define PINE3 3 -#define PINE2 2 -#define PINE1 1 -#define PINE0 0 -/* End Register Bits */ - -/* Register Bits [PORTF] */ -/* Port F Data Register - PORTF */ -#define PF7 7 -#define PF6 6 -#define PF5 5 -#define PF4 4 -#define PF3 3 -#define PF2 2 -#define PF1 1 -#define PF0 0 -/* End Register Bits */ - -/* Register Bits [DDRF] */ -/* Port F Data Direction Register - DDRF */ -#define DDF7 7 -#define DDF6 6 -#define DDF5 5 -#define DDF4 4 -#define DDF3 3 -#define DDF2 2 -#define DDF1 1 -#define DDF0 0 -/* End Register Bits */ - -/* Register Bits [PINF] */ -/* Port F Input Pins - PINF */ -#define PINF7 7 -#define PINF6 6 -#define PINF5 5 -#define PINF4 4 -#define PINF3 3 -#define PINF2 2 -#define PINF1 1 -#define PINF0 0 -/* End Register Bits */ - -/* Register Bits [PORTG] */ -/* Port G Data Register - PORTG */ -#define PG4 4 -#define PG3 3 -#define PG2 2 -#define PG1 1 -#define PG0 0 -/* End Register Bits */ - -/* Register Bits [DDRG] */ -/* Port G Data Direction Register - DDRG */ -#define DDG4 4 -#define DDG3 3 -#define DDG2 2 -#define DDG1 1 -#define DDG0 0 -/* End Register Bits */ - -/* Register Bits [PING] */ -/* Port G Input Pins - PING */ -#define PING4 4 -#define PING3 3 -#define PING2 2 -#define PING1 1 -#define PING0 0 -/* End Register Bits */ - - -/* Register Bits [TIFR0] */ -/* Timer/Counter 0 interrupt Flag Register */ -#define OCF0A 1 -#define TOV0 0 -/* End Register Bits */ - -/* Register Bits [TIFR1] */ -/* Timer/Counter 1 interrupt Flag Register */ -#define ICF1 5 -#define OCF1C 3 -#define OCF1B 2 -#define OCF1A 1 -#define TOV1 0 -/* End Register Bits */ - -/* Register Bits [TIFR2] */ -/* Timer/Counter 2 interrupt Flag Register */ -#define OCF2A 1 -#define TOV2 0 -/* End Register Bits */ - -/* Register Bits [TIFR3] */ -/* Timer/Counter 3 interrupt Flag Register */ -#define ICF3 5 -#define OCF3C 3 -#define OCF3B 2 -#define OCF3A 1 -#define TOV3 0 -/* End Register Bits */ - -/* Register Bits [GPIOR0] */ -/* General Purpose I/O Register 0 */ -#define GPIOR07 7 -#define GPIOR06 6 -#define GPIOR05 5 -#define GPIOR04 4 -#define GPIOR03 3 -#define GPIOR02 2 -#define GPIOR01 1 -#define GPIOR00 0 -/* End Register Bits */ - -/* Register Bits [GPIOR1] */ -/* General Purpose I/O Register 1 */ -#define GPIOR17 7 -#define GPIOR16 6 -#define GPIOR15 5 -#define GPIOR14 4 -#define GPIOR13 3 -#define GPIOR12 2 -#define GPIOR11 1 -#define GPIOR10 0 -/* End Register Bits */ - -/* Register Bits [GPIOR2] */ -/* General Purpose I/O Register 2 */ -#define GPIOR27 7 -#define GPIOR26 6 -#define GPIOR25 5 -#define GPIOR24 4 -#define GPIOR23 3 -#define GPIOR22 2 -#define GPIOR21 1 -#define GPIOR20 0 -/* End Register Bits */ - -/* Register Bits [EECR] */ -/* EEPROM Control Register */ -#define EERIE 3 -#define EEMWE 2 -#define EEWE 1 -#define EERE 0 -/* End Register Bits */ - -/* Register Bits [EEDR] */ -/* EEPROM Data Register */ -#define EEDR7 7 -#define EEDR6 6 -#define EEDR5 5 -#define EEDR4 4 -#define EEDR3 3 -#define EEDR2 2 -#define EEDR1 1 -#define EEDR0 0 -/* End Register Bits */ - -/* Register Bits [EEARL] */ -/* EEPROM Address Register */ -#define EEAR7 7 -#define EEAR6 6 -#define EEAR5 5 -#define EEAR4 4 -#define EEAR3 3 -#define EEAR2 2 -#define EEAR1 1 -#define EEAR0 0 -/* End Register Bits */ - -/* Register Bits [EEARH] */ -/* EEPROM Address Register */ -#define EEAR11 3 -#define EEAR10 2 -#define EEAR9 1 -#define EEAR8 0 -/* End Register Bits */ - -/* Register Bits [GTCCR] */ -/* General Timer/Counter Control Register */ -#define TSM 7 -#define PSR2 1 -#define PSR310 0 -/* End Register Bits */ - -/* Register Bits [TCCR0A] */ -/* Timer/Counter Control Register A */ -/* ALSO COVERED IN GENERIC SECTION */ -#define FOC0A 7 -#define WGM00 6 -#define COM0A1 5 -#define COM0A0 4 -#define WGM01 3 -#define CS02 2 -#define CS01 1 -#define CS00 0 -/* End Register Bits */ - -/* Register Bits [OCR0A] */ -/* Output Compare Register A */ -#define OCR0A7 7 -#define OCR0A6 6 -#define OCR0A5 5 -#define OCR0A4 4 -#define OCR0A3 3 -#define OCR0A2 2 -#define OCR0A1 1 -#define OCR0A0 0 -/* End Register Bits */ - - -/* Register Bits [SPIDR] */ -/* SPI Data Register */ -#define SPD7 7 -#define SPD6 6 -#define SPD5 5 -#define SPD4 4 -#define SPD3 3 -#define SPD2 2 -#define SPD1 1 -#define SPD0 0 -/* End Register Bits */ - -/* Register Bits [SMCR] */ -/* Sleep Mode Control Register */ -#define SM2 3 -#define SM1 2 -#define SM0 1 -#define SE 0 -/* End Register Bits */ - -/* Register Bits [MCUSR] */ -/* MCU Status Register */ -#define JTRF 4 -#define WDRF 3 -#define BORF 2 -#define EXTRF 1 -#define PORF 0 -/* End Register Bits */ - -/* Register Bits [MCUCR] */ -/* MCU Control Register */ -#define JTD 7 -#define PUD 4 -#define IVSEL 1 -#define IVCE 0 -/* End Register Bits */ - -/* Register Bits [CLKPR] */ -/* Clock Prescale Register */ -#define CLKPCE 7 -#define CLKPS3 3 -#define CLKPS2 2 -#define CLKPS1 1 -#define CLKPS0 0 -/* End Register Bits */ - -/* Register Bits [OSCCAL] */ -/* Oscillator Calibration Register */ -#define CAL6 6 -#define CAL5 5 -#define CAL4 4 -#define CAL3 3 -#define CAL2 2 -#define CAL1 1 -#define CAL0 0 -/* End Register Bits */ - -/* Register Bits [TIMSK0] */ -/* Timer/Counter 0 interrupt mask Register */ -#define OCIE0A 1 -#define TOIE0 0 -/* End Register Bits */ - -/* Register Bits [TIMSK1] */ -/* Timer/Counter 1 interrupt mask Register */ -#define ICIE1 5 -#define OCIE1C 3 -#define OCIE1B 2 -#define OCIE1A 1 -#define TOIE1 0 -/* End Register Bits */ - -/* Register Bits [TIMSK2] */ -/* Timer/Counter 2 interrupt mask Register */ -#define OCIE2A 1 -#define TOIE2 0 -/* End Register Bits */ - -/* Register Bits [TIMSK3] */ -/* Timer/Counter 3 interrupt mask Register */ -#define ICIE3 5 -#define OCIE3C 3 -#define OCIE3B 2 -#define OCIE3A 1 -#define TOIE3 0 -/* End Register Bits */ - -//Begin CAN specific parts - -/* Register Bits [CANGCON] */ -/* CAN General Control Register */ -#define ABRQ 7 -#define OVRQ 6 -#define TTC 5 -#define SYNTTC 4 -#define LISTEN 3 -#define TEST 2 -#define ENASTB 1 -#define SWRES 0 -/* End Register Bits */ - -/* Register Bits [CANGSTA] */ -/* CAN General Status Register */ -#define OVFG 6 -#define OVRG 6 -#define TXBSY 4 -#define RXBSY 3 -#define ENFG 2 -#define BOFF 1 -#define ERRP 0 -/* End Register Bits */ - -/* Register Bits [CANGIT] */ -/* CAN General Interrupt Register */ -#define CANIT 7 -#define BOFFIT 6 -#define OVRTIM 5 -#define BXOK 4 -#define SERG 3 -#define CERG 2 -#define FERG 1 -#define AERG 0 -/* End Register Bits */ - -/* Register Bits [CANGIE] */ -/* CAN General Interrupt Enable */ -#define ENIT 7 -#define ENBOFF 6 -#define ENRX 5 -#define ENTX 4 -#define ENERR 3 -#define ENBX 2 -#define ENERG 1 -#define ENOVRT 0 -/* End Register Bits */ - -/* Register Bits [CANEN2] */ -/* CAN Enable MOb Register */ -#define ENMOB7 7 -#define ENMOB6 6 -#define ENMOB5 5 -#define ENMOB4 4 -#define ENMOB3 3 -#define ENMOB2 2 -#define ENMOB1 1 -#define ENMOB0 0 -/* End Register Bits */ - -/* Register Bits [CANEN1] */ -/* CAN Enable MOb Register */ -#define ENMOB14 6 -#define ENMOB13 5 -#define ENMOB12 4 -#define ENMOB11 3 -#define ENMOB10 2 -#define ENMOB9 1 -#define ENMOB8 0 -/* End Register Bits */ - -/* Register Bits [CANIE2] */ -/* CAN Interrupt Enable MOb Register */ -#define IEMOB7 7 -#define IEMOB6 6 -#define IEMOB5 5 -#define IEMOB4 4 -#define IEMOB3 3 -#define IEMOB2 2 -#define IEMOB1 1 -#define IEMOB0 0 -/* End Register Bits */ - -/* Register Bits [CANIE1] */ -/* CAN Interrupt Enable MOb Register */ -#define IEMOB14 6 -#define IEMOB13 5 -#define IEMOB12 4 -#define IEMOB11 3 -#define IEMOB10 2 -#define IEMOB9 1 -#define IEMOB8 0 -/* End Register Bits */ - -/* Register Bits [CANSIT2] */ -/* CAN Status Interrupt MOb Register */ -#define SIT7 7 -#define SIT6 6 -#define SIT5 5 -#define SIT4 4 -#define SIT3 3 -#define SIT2 2 -#define SIT1 1 -#define SIT0 0 -/* End Register Bits */ - -/* Register Bits [CANSIT1] */ -/* CAN Status Interrupt MOb Register */ -#define SIT14 6 -#define SIT13 5 -#define SIT12 4 -#define SIT11 3 -#define SIT10 2 -#define SIT9 1 -#define SIT8 0 -/* End Register Bits */ - -/* Register Bits [CANBT1] */ -/* Bit Timing Register 1 */ -#define BRP5 6 -#define BRP4 5 -#define BRP3 4 -#define BRP2 3 -#define BRP1 2 -#define BRP0 1 -/* End Register Bits */ - -/* Register Bits [CANBT2] */ -/* Bit Timing Register 2 */ -#define SJW1 6 -#define SJW0 5 -#define PRS2 3 -#define PRS1 2 -#define PRS0 1 -/* End Register Bits */ - -/* Register Bits [CANBT3] */ -/* Bit Timing Register 3 */ -#define PHS22 6 -#define PHS21 5 -#define PHS20 4 -#define PHS12 3 -#define PHS11 2 -#define PHS10 1 -#define SMP 0 -/* End Register Bits */ - -/* Register Bits [CANTCON] */ -/* CAN Timer Control Register */ -#define TPRSC7 7 -#define TPRSC6 6 -#define TPRSC5 5 -#define TPRSC4 4 -#define TPRSC3 3 -#define TPRSC2 2 -#define TPRSC1 1 -#define TPRSC0 0 -/* End Register Bits */ - -/* Register Bits [CANTIML] */ -/* CAN Timer Register Low */ -#define CANTIM7 7 -#define CANTIM6 6 -#define CANTIM5 5 -#define CANTIM4 4 -#define CANTIM3 3 -#define CANTIM2 2 -#define CANTIM1 1 -#define CANTIM0 0 -/* End Register Bits */ - -/* Register Bits [CANTIMH] */ -/* CAN Timer Register High */ -#define CANTIM15 7 -#define CANTIM14 6 -#define CANTIM13 5 -#define CANTIM12 4 -#define CANTIM11 3 -#define CANTIM10 2 -#define CANTIM9 1 -#define CANTIM8 0 -/* End Register Bits */ - -/* Register Bits [CANTTCL] */ -/* CAN TTC Timer Register Low */ -#define TIMTTC7 7 -#define TIMTTC6 6 -#define TIMTTC5 5 -#define TIMTTC4 4 -#define TIMTTC3 3 -#define TIMTTC2 2 -#define TIMTTC1 1 -#define TIMTTC0 0 -/* End Register Bits */ - -/* Register Bits [CANTTCH] */ -/* CAN TTC Timer Register High */ -#define TIMTTC15 7 -#define TIMTTC14 6 -#define TIMTTC13 5 -#define TIMTTC12 4 -#define TIMTTC11 3 -#define TIMTTC10 2 -#define TIMTTC9 1 -#define TIMTTC8 0 -/* End Register Bits */ - -/* Register Bits [CANTEC] */ -/* CAN Transmitt Error Counter */ -#define TEC7 7 -#define TEC6 6 -#define TEC5 5 -#define TEC4 4 -#define TEC3 3 -#define TEC2 2 -#define TEC1 1 -#define TEC0 0 -/* End Register Bits */ - -/* Register Bits [CANREC] */ -/* CAN Receive Error Counter */ -#define REC7 7 -#define REC6 6 -#define REC5 5 -#define REC4 4 -#define REC3 3 -#define REC2 2 -#define REC1 1 -#define REC0 0 -/* End Register Bits */ - -/* Register Bits [CANHPMOB] */ -/* Highest Priority MOb */ -#define HPMOB3 7 -#define HPMOB2 6 -#define HPMOB1 5 -#define HPMOB0 4 -#define CGP3 3 -#define CGP2 2 -#define CGP1 1 -#define CGP0 0 -/* End Register Bits */ - -/* Register Bits [CANPAGE] */ -/* CAN Page MOb Register */ -#define MOBNB3 7 -#define MOBNB2 6 -#define MOBNB1 5 -#define MOBNB0 4 -#define AINC 3 -#define INDX2 2 -#define INDX1 1 -#define INDX0 0 -/* End Register Bits */ - -/* Register Bits [CANSTMOB] */ -/* CAN MOb Status Register */ -#define DLCW 7 -#define TXOK 6 -#define RXOK 5 -#define BERR 4 -#define SERR 3 -#define CERR 2 -#define FERR 1 -#define AERR 0 -/* End Register Bits */ - -/* Register Bits [CANCDMOB] */ -/* CAN MOb Control and DLC Register */ -#define CONMOB1 7 -#define CONMOB0 6 -#define RPLV 5 -#define IDE 4 -#define DLC3 3 -#define DLC2 2 -#define DLC1 1 -#define DLC0 0 -/* End Register Bits */ - -/* Register Bits [CANIDT4] */ -/* CAN Identifier Tag Register 4 */ -#define IDT4 7 -#define IDT3 6 -#define IDT2 5 -#define IDT1 4 -#define IDT0 3 -#define RTRTAG 2 -#define RB1TAG 1 -#define RB0TAG 0 -/* End Register Bits */ - -/* Register Bits [CANIDT3] */ -/* CAN Identifier Tag Register 3 */ -#define IDT12 7 -#define IDT11 6 -#define IDT10 5 -#define IDT9 4 -#define IDT8 3 -#define IDT7 2 -#define IDT6 1 -#define IDT5 0 -/* End Register Bits */ - -/* Register Bits [CANIDT2] */ -/* CAN Identifier Tag Register 2 */ -#define IDT20 7 -#define IDT19 6 -#define IDT18 5 -#define IDT17 4 -#define IDT16 3 -#define IDT15 2 -#define IDT14 1 -#define IDT13 0 -/* End Register Bits */ - -/* Register Bits [CANIDT1] */ -/* CAN Identifier Tag Register 1 */ -#define IDT28 7 -#define IDT27 6 -#define IDT26 5 -#define IDT25 4 -#define IDT24 3 -#define IDT23 2 -#define IDT22 1 -#define IDT21 0 -/* End Register Bits */ - -/* Register Bits [CANIDM4] */ -/* CAN Identifier Mask Register 4 */ -#define IDMSK4 7 -#define IDMSK3 6 -#define IDMSK2 5 -#define IDMSK1 4 -#define IDMSK0 3 -#define RTRMSK 2 -#define IDEMSK 0 -/* End Register Bits */ - -/* Register Bits [CANIDM3] */ -/* CAN Identifier Mask Register 3 */ -#define IDMSK12 7 -#define IDMSK11 6 -#define IDMSK10 5 -#define IDMSK9 4 -#define IDMSK8 3 -#define IDMSK7 2 -#define IDMSK6 1 -#define IDMSK5 0 -/* End Register Bits */ - -/* Register Bits [CANIDM2] */ -/* CAN Identifier Mask Register 2 */ -#define IDMSK20 7 -#define IDMSK19 6 -#define IDMSK18 5 -#define IDMSK17 4 -#define IDMSK16 3 -#define IDMSK15 2 -#define IDMSK14 1 -#define IDMSK13 0 -/* End Register Bits */ - -/* Register Bits [CANIDM1] */ -/* CAN Identifier Mask Register 1 */ -#define IDMSK28 7 -#define IDMSK27 6 -#define IDMSK26 5 -#define IDMSK25 4 -#define IDMSK24 3 -#define IDMSK23 2 -#define IDMSK22 1 -#define IDMSK21 0 -/* End Register Bits */ - -/* Register Bits [CANSTML] */ -/* CAN Timer Register of some sort, low*/ -#define TIMSTM7 7 -#define TIMSTM6 6 -#define TIMSTM5 5 -#define TIMSTM4 4 -#define TIMSTM3 3 -#define TIMSTM2 2 -#define TIMSTM1 1 -#define TIMSTM0 0 -/* End Register Bits */ - -/* Register Bits [CANSTMH] */ -/* CAN Timer Register of some sort, high */ -#define TIMSTM15 7 -#define TIMSTM14 6 -#define TIMSTM13 5 -#define TIMSTM12 4 -#define TIMSTM11 3 -#define TIMSTM10 2 -#define TIMSTM9 1 -#define TIMSTM8 0 -/* End Register Bits */ - -/* Register Bits [CANMSG] */ -/* CAN Message Register */ -#define MSG7 7 -#define MSG6 6 -#define MSG5 5 -#define MSG4 4 -#define MSG3 3 -#define MSG2 2 -#define MSG1 1 -#define MSG0 0 -/* End Register Bits */ - -/* Begin Verbatim */ - -/* Timer/Counter Control Register (generic) */ -#define FOC 7 -#define WGM0 6 -#define COM1 5 -#define COM0 4 -#define WGM1 3 -#define CS2 2 -#define CS1 1 -#define CS0 0 - -/* Timer/Counter Control Register A (generic) */ -#define COMA1 7 -#define COMA0 6 -#define COMB1 5 -#define COMB0 4 -#define COMC1 3 -#define COMC0 2 -#define WGMA1 1 -#define WGMA0 0 - -/* Timer/Counter Control and Status Register B (generic) */ -#define ICNC 7 -#define ICES 6 -#define WGMB3 4 -#define WGMB2 3 -#define CSB2 2 -#define CSB1 1 -#define CSB0 0 - -/* Timer/Counter Control Register C (generic) */ -#define FOCA 7 -#define FOCB 6 -#define FOCC 5 - -/* Port Data Register (generic) */ -#define PORT7 7 -#define PORT6 6 -#define PORT5 5 -#define PORT4 4 -#define PORT3 3 -#define PORT2 2 -#define PORT1 1 -#define PORT0 0 - -/* Port Data Direction Register (generic) */ -#define DD7 7 -#define DD6 6 -#define DD5 5 -#define DD4 4 -#define DD3 3 -#define DD2 2 -#define DD1 1 -#define DD0 0 - -/* Port Input Pins (generic) */ -#define PIN7 7 -#define PIN6 6 -#define PIN5 5 -#define PIN4 4 -#define PIN3 3 -#define PIN2 2 -#define PIN1 1 -#define PIN0 0 - -/* USART Status Register A (generic) */ -#define RXC 7 -#define TXC 6 -#define UDRE 5 -#define FE 4 -#define DOR 3 -#define UPE 2 -#define U2X 1 -#define MPCM 0 - -/* USART Control Register B (generic) */ -#define RXCIE 7 -#define TXCIE 6 -#define UDRIE 5 -#define RXEN 4 -#define TXEN 3 -#define UCSZ 2 -#define UCSZ2 2 /* new name in datasheet (2467E-AVR-05/02) */ -#define RXB8 1 -#define TXB8 0 - -/* USART Register C (generic) */ -#define UMSEL 6 -#define UPM1 5 -#define UPM0 4 -#define USBS 3 -#define UCSZ1 2 -#define UCSZ0 1 -#define UCPOL 0 - -/* End Verbatim */ - -#endif /* _AVR_IOCANXX_H_ */ diff --git a/arduino/hardware/tools/avr/avr/include/avr/iom103.h b/arduino/hardware/tools/avr/avr/include/avr/iom103.h deleted file mode 100644 index c31a16b..0000000 --- a/arduino/hardware/tools/avr/avr/include/avr/iom103.h +++ /dev/null @@ -1,735 +0,0 @@ -/* Copyright (c) 2002, Marek Michalkiewicz - All rights reserved. - - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - * Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - * Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in - the documentation and/or other materials provided with the - distribution. - - * Neither the name of the copyright holders nor the names of - contributors may be used to endorse or promote products derived - from this software without specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. */ - -/* $Id: iom103.h 2227 2011-03-04 19:35:10Z arcanum $ */ - -/* avr/iom103.h - definitions for ATmega103 */ - -#ifndef _AVR_IOM103_H_ -#define _AVR_IOM103_H_ 1 - -/* This file should only be included from , never directly. */ - -#ifndef _AVR_IO_H_ -# error "Include instead of this file." -#endif - -#ifndef _AVR_IOXXX_H_ -# define _AVR_IOXXX_H_ "iom103.h" -#else -# error "Attempt to include more than one file." -#endif - -/* I/O registers */ - -/* Input Pins, Port F */ -#define PINF _SFR_IO8(0x00) - -/* Input Pins, Port E */ -#define PINE _SFR_IO8(0x01) - -/* Data Direction Register, Port E */ -#define DDRE _SFR_IO8(0x02) - -/* Data Register, Port E */ -#define PORTE _SFR_IO8(0x03) - -/* ADC Data Register */ -#ifndef __ASSEMBLER__ -#define ADC _SFR_IO16(0x04) -#endif -#define ADCW _SFR_IO16(0x04) -#define ADCL _SFR_IO8(0x04) -#define ADCH _SFR_IO8(0x05) - -/* ADC Control and status register */ -#define ADCSR _SFR_IO8(0x06) - -/* ADC Multiplexer select */ -#define ADMUX _SFR_IO8(0x07) - -/* Analog Comparator Control and Status Register */ -#define ACSR _SFR_IO8(0x08) - -/* UART Baud Rate Register */ -#define UBRR _SFR_IO8(0x09) - -/* UART Control Register */ -#define UCR _SFR_IO8(0x0A) - -/* UART Status Register */ -#define USR _SFR_IO8(0x0B) - -/* UART I/O Data Register */ -#define UDR _SFR_IO8(0x0C) - -/* SPI Control Register */ -#define SPCR _SFR_IO8(0x0D) - -/* SPI Status Register */ -#define SPSR _SFR_IO8(0x0E) - -/* SPI I/O Data Register */ -#define SPDR _SFR_IO8(0x0F) - -/* Input Pins, Port D */ -#define PIND _SFR_IO8(0x10) - -/* Data Direction Register, Port D */ -#define DDRD _SFR_IO8(0x11) - -/* Data Register, Port D */ -#define PORTD _SFR_IO8(0x12) - -/* Data Register, Port C */ -#define PORTC _SFR_IO8(0x15) - -/* Input Pins, Port B */ -#define PINB _SFR_IO8(0x16) - -/* Data Direction Register, Port B */ -#define DDRB _SFR_IO8(0x17) - -/* Data Register, Port B */ -#define PORTB _SFR_IO8(0x18) - -/* Input Pins, Port A */ -#define PINA _SFR_IO8(0x19) - -/* Data Direction Register, Port A */ -#define DDRA _SFR_IO8(0x1A) - -/* Data Register, Port A */ -#define PORTA _SFR_IO8(0x1B) - -/* EEPROM Control Register */ -#define EECR _SFR_IO8(0x1C) - -/* EEPROM Data Register */ -#define EEDR _SFR_IO8(0x1D) - -/* EEPROM Address Register */ -#define EEAR _SFR_IO16(0x1E) -#define EEARL _SFR_IO8(0x1E) -#define EEARH _SFR_IO8(0x1F) - -/* Watchdog Timer Control Register */ -#define WDTCR _SFR_IO8(0x21) - -/* Timer2 Output Compare Register */ -#define OCR2 _SFR_IO8(0x23) - -/* Timer/Counter 2 */ -#define TCNT2 _SFR_IO8(0x24) - -/* Timer/Counter 2 Control register */ -#define TCCR2 _SFR_IO8(0x25) - -/* T/C 1 Input Capture Register */ -#define ICR1 _SFR_IO16(0x26) -#define ICR1L _SFR_IO8(0x26) -#define ICR1H _SFR_IO8(0x27) - -/* Timer/Counter1 Output Compare Register B */ -#define OCR1B _SFR_IO16(0x28) -#define OCR1BL _SFR_IO8(0x28) -#define OCR1BH _SFR_IO8(0x29) - -/* Timer/Counter1 Output Compare Register A */ -#define OCR1A _SFR_IO16(0x2A) -#define OCR1AL _SFR_IO8(0x2A) -#define OCR1AH _SFR_IO8(0x2B) - -/* Timer/Counter 1 */ -#define TCNT1 _SFR_IO16(0x2C) -#define TCNT1L _SFR_IO8(0x2C) -#define TCNT1H _SFR_IO8(0x2D) - -/* Timer/Counter 1 Control and Status Register */ -#define TCCR1B _SFR_IO8(0x2E) - -/* Timer/Counter 1 Control Register */ -#define TCCR1A _SFR_IO8(0x2F) - -/* Timer/Counter 0 Asynchronous Control & Status Register */ -#define ASSR _SFR_IO8(0x30) - -/* Output Compare Register 0 */ -#define OCR0 _SFR_IO8(0x31) - -/* Timer/Counter 0 */ -#define TCNT0 _SFR_IO8(0x32) - -/* Timer/Counter 0 Control Register */ -#define TCCR0 _SFR_IO8(0x33) - -/* MCU Status Register */ -#define MCUSR _SFR_IO8(0x34) - -/* MCU general Control Register */ -#define MCUCR _SFR_IO8(0x35) - -/* Timer/Counter Interrupt Flag Register */ -#define TIFR _SFR_IO8(0x36) - -/* Timer/Counter Interrupt MaSK register */ -#define TIMSK _SFR_IO8(0x37) - -/* �xternal Interrupt Flag Register */ -#define EIFR _SFR_IO8(0x38) - -/* External Interrupt MaSK register */ -#define EIMSK _SFR_IO8(0x39) - -/* External Interrupt Control Register */ -#define EICR _SFR_IO8(0x3A) - -/* RAM Page Z select register */ -#define RAMPZ _SFR_IO8(0x3B) - -/* XDIV Divide control register */ -#define XDIV _SFR_IO8(0x3C) - -/* 0x3D..0x3E SP */ - -/* 0x3F SREG */ - -/* Interrupt vectors */ - -/* External Interrupt 0 */ -#define INT0_vect_num 1 -#define INT0_vect _VECTOR(1) -#define SIG_INTERRUPT0 _VECTOR(1) - -/* External Interrupt 1 */ -#define INT1_vect_num 2 -#define INT1_vect _VECTOR(2) -#define SIG_INTERRUPT1 _VECTOR(2) - -/* External Interrupt 2 */ -#define INT2_vect_num 3 -#define INT2_vect _VECTOR(3) -#define SIG_INTERRUPT2 _VECTOR(3) - -/* External Interrupt 3 */ -#define INT3_vect_num 4 -#define INT3_vect _VECTOR(4) -#define SIG_INTERRUPT3 _VECTOR(4) - -/* External Interrupt 4 */ -#define INT4_vect_num 5 -#define INT4_vect _VECTOR(5) -#define SIG_INTERRUPT4 _VECTOR(5) - -/* External Interrupt 5 */ -#define INT5_vect_num 6 -#define INT5_vect _VECTOR(6) -#define SIG_INTERRUPT5 _VECTOR(6) - -/* External Interrupt 6 */ -#define INT6_vect_num 7 -#define INT6_vect _VECTOR(7) -#define SIG_INTERRUPT6 _VECTOR(7) - -/* External Interrupt 7 */ -#define INT7_vect_num 8 -#define INT7_vect _VECTOR(8) -#define SIG_INTERRUPT7 _VECTOR(8) - -/* Timer/Counter2 Compare Match */ -#define TIMER2_COMP_vect_num 9 -#define TIMER2_COMP_vect _VECTOR(9) -#define SIG_OUTPUT_COMPARE2 _VECTOR(9) - -/* Timer/Counter2 Overflow */ -#define TIMER2_OVF_vect_num 10 -#define TIMER2_OVF_vect _VECTOR(10) -#define SIG_OVERFLOW2 _VECTOR(10) - -/* Timer/Counter1 Capture Event */ -#define TIMER1_CAPT_vect_num 11 -#define TIMER1_CAPT_vect _VECTOR(11) -#define SIG_INPUT_CAPTURE1 _VECTOR(11) - -/* Timer/Counter1 Compare Match A */ -#define TIMER1_COMPA_vect_num 12 -#define TIMER1_COMPA_vect _VECTOR(12) -#define SIG_OUTPUT_COMPARE1A _VECTOR(12) - -/* Timer/Counter1 Compare Match B */ -#define TIMER1_COMPB_vect_num 13 -#define TIMER1_COMPB_vect _VECTOR(13) -#define SIG_OUTPUT_COMPARE1B _VECTOR(13) - -/* Timer/Counter1 Overflow */ -#define TIMER1_OVF_vect_num 14 -#define TIMER1_OVF_vect _VECTOR(14) -#define SIG_OVERFLOW1 _VECTOR(14) - -/* Timer/Counter0 Compare Match */ -#define TIMER0_COMP_vect_num 15 -#define TIMER0_COMP_vect _VECTOR(15) -#define SIG_OUTPUT_COMPARE0 _VECTOR(15) - -/* Timer/Counter0 Overflow */ -#define TIMER0_OVF_vect_num 16 -#define TIMER0_OVF_vect _VECTOR(16) -#define SIG_OVERFLOW0 _VECTOR(16) - -/* SPI Serial Transfer Complete */ -#define SPI_STC_vect_num 17 -#define SPI_STC_vect _VECTOR(17) -#define SIG_SPI _VECTOR(17) - -/* UART, Rx Complete */ -#define UART_RX_vect_num 18 -#define UART_RX_vect _VECTOR(18) -#define SIG_UART_RECV _VECTOR(18) - -/* UART Data Register Empty */ -#define UART_UDRE_vect_num 19 -#define UART_UDRE_vect _VECTOR(19) -#define SIG_UART_DATA _VECTOR(19) - -/* UART, Tx Complete */ -#define UART_TX_vect_num 20 -#define UART_TX_vect _VECTOR(20) -#define SIG_UART_TRANS _VECTOR(20) - -/* ADC Conversion Complete */ -#define ADC_vect_num 21 -#define ADC_vect _VECTOR(21) -#define SIG_ADC _VECTOR(21) - -/* EEPROM Ready */ -#define EE_READY_vect_num 22 -#define EE_READY_vect _VECTOR(22) -#define SIG_EEPROM_READY _VECTOR(22) - -/* Analog Comparator */ -#define ANALOG_COMP_vect_num 23 -#define ANALOG_COMP_vect _VECTOR(23) -#define SIG_COMPARATOR _VECTOR(23) - -#define _VECTORS_SIZE 96 - -/* - The Register Bit names are represented by their bit number (0-7). -*/ - -/* XDIV Divide control register*/ -#define XDIVEN 7 -#define XDIV6 6 -#define XDIV5 5 -#define XDIV4 4 -#define XDIV3 3 -#define XDIV2 2 -#define XDIV1 1 -#define XDIV0 0 - -/* RAM Page Z select register */ -#define RAMPZ0 0 - -/* External Interrupt Control Register */ -#define ISC71 7 -#define ISC70 6 -#define ISC61 5 -#define ISC60 4 -#define ISC51 3 -#define ISC50 2 -#define ISC41 1 -#define ISC40 0 - -/* External Interrupt MaSK register */ -#define INT7 7 -#define INT6 6 -#define INT5 5 -#define INT4 4 -#define INT3 3 -#define INT2 2 -#define INT1 1 -#define INT0 0 - -/* �xternal Interrupt Flag Register */ -#define INTF7 7 -#define INTF6 6 -#define INTF5 5 -#define INTF4 4 - -/* Timer/Counter Interrupt MaSK register */ -#define OCIE2 7 -#define TOIE2 6 -#define TICIE1 5 -#define OCIE1A 4 -#define OCIE1B 3 -#define TOIE1 2 -#define OCIE0 1 -#define TOIE0 0 - -/* Timer/Counter Interrupt Flag Register */ -#define OCF2 7 -#define TOV2 6 -#define ICF1 5 -#define OCF1A 4 -#define OCF1B 3 -#define TOV1 2 -#define OCF0 1 -#define TOV0 0 - -/* MCU general Control Register */ -#define SRE 7 -#define SRW 6 -#define SE 5 -#define SM1 4 -#define SM0 3 - -/* MCU Status Register */ -#define EXTRF 1 -#define PORF 0 - -/* Timer/Counter 0 Control Register */ -#define PWM0 6 -#define COM01 5 -#define COM00 4 -#define CTC0 3 -#define CS02 2 -#define CS01 1 -#define CS00 0 - -/* Timer/Counter 0 Asynchronous Control & Status Register */ -#define AS0 3 -#define TCN0UB 2 -#define OCR0UB 1 -#define TCR0UB 0 - -/* Timer/Counter 1 Control Register */ -#define COM1A1 7 -#define COM1A0 6 -#define COM1B1 5 -#define COM1B0 4 -#define PWM11 1 -#define PWM10 0 - -/* Timer/Counter 1 Control and Status Register */ -#define ICNC1 7 -#define ICES1 6 -#define CTC1 3 -#define CS12 2 -#define CS11 1 -#define CS10 0 - -/* Timer/Counter 2 Control register */ -#define PWM2 6 -#define COM21 5 -#define COM20 4 -#define CTC2 3 -#define CS22 2 -#define CS21 1 -#define CS20 0 - -/* Watchdog Timer Control Register */ -#define WDTOE 4 -#define WDE 3 -#define WDP2 2 -#define WDP1 1 -#define WDP0 0 - -/* Data Register, Port A */ -#define PA7 7 -#define PA6 6 -#define PA5 5 -#define PA4 4 -#define PA3 3 -#define PA2 2 -#define PA1 1 -#define PA0 0 - -/* Data Direction Register, Port A */ -#define DDA7 7 -#define DDA6 6 -#define DDA5 5 -#define DDA4 4 -#define DDA3 3 -#define DDA2 2 -#define DDA1 1 -#define DDA0 0 - -/* Input Pins, Port A */ -#define PINA7 7 -#define PINA6 6 -#define PINA5 5 -#define PINA4 4 -#define PINA3 3 -#define PINA2 2 -#define PINA1 1 -#define PINA0 0 - -/* Data Register, Port B */ -#define PB7 7 -#define PB6 6 -#define PB5 5 -#define PB4 4 -#define PB3 3 -#define PB2 2 -#define PB1 1 -#define PB0 0 - -/* Data Direction Register, Port B */ -#define DDB7 7 -#define DDB6 6 -#define DDB5 5 -#define DDB4 4 -#define DDB3 3 -#define DDB2 2 -#define DDB1 1 -#define DDB0 0 - -/* Input Pins, Port B */ -#define PINB7 7 -#define PINB6 6 -#define PINB5 5 -#define PINB4 4 -#define PINB3 3 -#define PINB2 2 -#define PINB1 1 -#define PINB0 0 - -/* Data Register, Port C */ -#define PC7 7 -#define PC6 6 -#define PC5 5 -#define PC4 4 -#define PC3 3 -#define PC2 2 -#define PC1 1 -#define PC0 0 - -/* Data Register, Port D */ -#define PD7 7 -#define PD6 6 -#define PD5 5 -#define PD4 4 -#define PD3 3 -#define PD2 2 -#define PD1 1 -#define PD0 0 - -/* Data Direction Register, Port D */ -#define DDD7 7 -#define DDD6 6 -#define DDD5 5 -#define DDD4 4 -#define DDD3 3 -#define DDD2 2 -#define DDD1 1 -#define DDD0 0 - -/* Input Pins, Port D */ -#define PIND7 7 -#define PIND6 6 -#define PIND5 5 -#define PIND4 4 -#define PIND3 3 -#define PIND2 2 -#define PIND1 1 -#define PIND0 0 - -/* Data Register, Port E */ -#define PE7 7 -#define PE6 6 -#define PE5 5 -#define PE4 4 -#define PE3 3 -#define PE2 2 -#define PE1 1 -#define PE0 0 - -/* Data Direction Register, Port E */ -#define DDE7 7 -#define DDE6 6 -#define DDE5 5 -#define DDE4 4 -#define DDE3 3 -#define DDE2 2 -#define DDE1 1 -#define DDE0 0 - -/* Input Pins, Port E */ -#define PINE7 7 -#define PINE6 6 -#define PINE5 5 -#define PINE4 4 -#define PINE3 3 -#define PINE2 2 -#define PINE1 1 -#define PINE0 0 - -/* Input Pins, Port F */ -#define PINF7 7 -#define PINF6 6 -#define PINF5 5 -#define PINF4 4 -#define PINF3 3 -#define PINF2 2 -#define PINF1 1 -#define PINF0 0 - -/* SPI Status Register */ -#define SPIF 7 -#define WCOL 6 - -/* SPI Control Register */ -#define SPIE 7 -#define SPE 6 -#define DORD 5 -#define MSTR 4 -#define CPOL 3 -#define CPHA 2 -#define SPR1 1 -#define SPR0 0 - -/* UART Status Register */ -#define RXC 7 -#define TXC 6 -#define UDRE 5 -#define FE 4 -#define DOR 3 - -/* UART Control Register */ -#define RXCIE 7 -#define TXCIE 6 -#define UDRIE 5 -#define RXEN 4 -#define TXEN 3 -#define CHR9 2 -#define RXB8 1 -#define TXB8 0 - -/* Analog Comparator Control and Status Register */ -#define ACD 7 -#define ACO 5 -#define ACI 4 -#define ACIE 3 -#define ACIC 2 -#define ACIS1 1 -#define ACIS0 0 - -/* ADC Control and status register */ -#define ADEN 7 -#define ADSC 6 -#define ADFR 5 -#define ADIF 4 -#define ADIE 3 -#define ADPS2 2 -#define ADPS1 1 -#define ADPS0 0 - -/* ADC Multiplexer select */ -#define MUX2 2 -#define MUX1 1 -#define MUX0 0 - -/* EEPROM Control Register */ -#define EERIE 3 -#define EEMWE 2 -#define EEWE 1 -#define EERE 0 - -/* Constants */ -#define RAMSTART 0x60 -#define RAMEND 0x0FFF /*Last On-Chip SRAM Location*/ -#define XRAMEND 0xFFFF -#define E2END 0x0FFF -#define E2PAGESIZE 0 -#define FLASHEND 0x1FFFF - - -/* Fuses */ -#define FUSE_MEMORY_SIZE 1 - -/* Low Fuse Byte */ -#define FUSE_CKSEL0 (unsigned char)~_BV(0) /* Select Clock Source */ -#define FUSE_CKSEL1 (unsigned char)~_BV(1) /* Select Clock Source */ -#define FUSE_CKSEL2 (unsigned char)~_BV(2) /* Select Clock Source */ -#define FUSE_CKSEL3 (unsigned char)~_BV(3) /* Select Clock Source */ -#define FUSE_SUT0 (unsigned char)~_BV(4) /* Select start-up time */ -#define FUSE_SUT1 (unsigned char)~_BV(5) /* Select start-up time */ -#define FUSE_BODEN (unsigned char)~_BV(6) /* Brown out detector enable */ -#define FUSE_BODLEVEL (unsigned char)~_BV(7) /* Brown out detector trigger level */ -#define LFUSE_DEFAULT (FUSE_SUT1 & FUSE_SUT0 & FUSE_CKSEL3 & FUSE_CKSEL2 & FUSE_CKSEL1) - - -/* Lock Bits */ -#define __LOCK_BITS_EXIST - - -/* Signature */ -#define SIGNATURE_0 0x1E -#define SIGNATURE_1 0x97 -#define SIGNATURE_2 0x01 - -#define SLEEP_MODE_IDLE 0 -#define SLEEP_MODE_ADC _BV(SM0) -#define SLEEP_MODE_PWR_DOWN _BV(SM1) -#define SLEEP_MODE_PWR_SAVE (_BV(SM0) | _BV(SM1)) - -/* Deprecated items */ -#if !defined(__AVR_LIBC_DEPRECATED_ENABLE__) - -#pragma GCC system_header - -#pragma GCC poison SIG_INTERRUPT0 -#pragma GCC poison SIG_INTERRUPT1 -#pragma GCC poison SIG_INTERRUPT2 -#pragma GCC poison SIG_INTERRUPT3 -#pragma GCC poison SIG_INTERRUPT4 -#pragma GCC poison SIG_INTERRUPT5 -#pragma GCC poison SIG_INTERRUPT6 -#pragma GCC poison SIG_INTERRUPT7 -#pragma GCC poison SIG_OUTPUT_COMPARE2 -#pragma GCC poison SIG_OVERFLOW2 -#pragma GCC poison SIG_INPUT_CAPTURE1 -#pragma GCC poison SIG_OUTPUT_COMPARE1A -#pragma GCC poison SIG_OUTPUT_COMPARE1B -#pragma GCC poison SIG_OVERFLOW1 -#pragma GCC poison SIG_OUTPUT_COMPARE0 -#pragma GCC poison SIG_OVERFLOW0 -#pragma GCC poison SIG_SPI -#pragma GCC poison SIG_UART_RECV -#pragma GCC poison SIG_UART_DATA -#pragma GCC poison SIG_UART_TRANS -#pragma GCC poison SIG_ADC -#pragma GCC poison SIG_EEPROM_READY -#pragma GCC poison SIG_COMPARATOR - -#endif /* !defined(__AVR_LIBC_DEPRECATED_ENABLE__) */ - - -#endif /* _AVR_IOM103_H_ */ diff --git a/arduino/hardware/tools/avr/avr/include/avr/iom128.h b/arduino/hardware/tools/avr/avr/include/avr/iom128.h deleted file mode 100644 index 1b19839..0000000 --- a/arduino/hardware/tools/avr/avr/include/avr/iom128.h +++ /dev/null @@ -1,1299 +0,0 @@ -/* Copyright (c) 2002, Peter Jansen - Copyright (c) 2007, Atmel Corporation - All rights reserved. - - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - * Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - * Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in - the documentation and/or other materials provided with the - distribution. - - * Neither the name of the copyright holders nor the names of - contributors may be used to endorse or promote products derived - from this software without specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. */ - -/* $Id: iom128.h 2226 2011-03-04 17:47:16Z arcanum $ */ - -/* avr/iom128.h - defines for ATmega128 - - As of 2002-08-27: - - This should be up to date with data sheet 2467E-AVR-05/02 */ - -#ifndef _AVR_IOM128_H_ -#define _AVR_IOM128_H_ 1 - -/* This file should only be included from , never directly. */ - -#ifndef _AVR_IO_H_ -# error "Include instead of this file." -#endif - -#ifndef _AVR_IOXXX_H_ -# define _AVR_IOXXX_H_ "iom128.h" -#else -# error "Attempt to include more than one file." -#endif - -/* I/O registers */ - -/* Input Pins, Port F */ -#define PINF _SFR_IO8(0x00) - -/* Input Pins, Port E */ -#define PINE _SFR_IO8(0x01) - -/* Data Direction Register, Port E */ -#define DDRE _SFR_IO8(0x02) - -/* Data Register, Port E */ -#define PORTE _SFR_IO8(0x03) - -/* ADC Data Register */ -#define ADCW _SFR_IO16(0x04) -#ifndef __ASSEMBLER__ -#define ADC _SFR_IO16(0x04) -#endif -#define ADCL _SFR_IO8(0x04) -#define ADCH _SFR_IO8(0x05) - -/* ADC Control and status register */ -#define ADCSR _SFR_IO8(0x06) -#define ADCSRA _SFR_IO8(0x06) /* new name in datasheet (2467E-AVR-05/02) */ - -/* ADC Multiplexer select */ -#define ADMUX _SFR_IO8(0x07) - -/* Analog Comparator Control and Status Register */ -#define ACSR _SFR_IO8(0x08) - -/* USART0 Baud Rate Register Low */ -#define UBRR0L _SFR_IO8(0x09) - -/* USART0 Control and Status Register B */ -#define UCSR0B _SFR_IO8(0x0A) - -/* USART0 Control and Status Register A */ -#define UCSR0A _SFR_IO8(0x0B) - -/* USART0 I/O Data Register */ -#define UDR0 _SFR_IO8(0x0C) - -/* SPI Control Register */ -#define SPCR _SFR_IO8(0x0D) - -/* SPI Status Register */ -#define SPSR _SFR_IO8(0x0E) - -/* SPI I/O Data Register */ -#define SPDR _SFR_IO8(0x0F) - -/* Input Pins, Port D */ -#define PIND _SFR_IO8(0x10) - -/* Data Direction Register, Port D */ -#define DDRD _SFR_IO8(0x11) - -/* Data Register, Port D */ -#define PORTD _SFR_IO8(0x12) - -/* Input Pins, Port C */ -#define PINC _SFR_IO8(0x13) - -/* Data Direction Register, Port C */ -#define DDRC _SFR_IO8(0x14) - -/* Data Register, Port C */ -#define PORTC _SFR_IO8(0x15) - -/* Input Pins, Port B */ -#define PINB _SFR_IO8(0x16) - -/* Data Direction Register, Port B */ -#define DDRB _SFR_IO8(0x17) - -/* Data Register, Port B */ -#define PORTB _SFR_IO8(0x18) - -/* Input Pins, Port A */ -#define PINA _SFR_IO8(0x19) - -/* Data Direction Register, Port A */ -#define DDRA _SFR_IO8(0x1A) - -/* Data Register, Port A */ -#define PORTA _SFR_IO8(0x1B) - -/* EEPROM Control Register */ -#define EECR _SFR_IO8(0x1C) - -/* EEPROM Data Register */ -#define EEDR _SFR_IO8(0x1D) - -/* EEPROM Address Register */ -#define EEAR _SFR_IO16(0x1E) -#define EEARL _SFR_IO8(0x1E) -#define EEARH _SFR_IO8(0x1F) - -/* Special Function I/O Register */ -#define SFIOR _SFR_IO8(0x20) - -/* Watchdog Timer Control Register */ -#define WDTCR _SFR_IO8(0x21) - -/* On-chip Debug Register */ -#define OCDR _SFR_IO8(0x22) - -/* Timer2 Output Compare Register */ -#define OCR2 _SFR_IO8(0x23) - -/* Timer/Counter 2 */ -#define TCNT2 _SFR_IO8(0x24) - -/* Timer/Counter 2 Control register */ -#define TCCR2 _SFR_IO8(0x25) - -/* T/C 1 Input Capture Register */ -#define ICR1 _SFR_IO16(0x26) -#define ICR1L _SFR_IO8(0x26) -#define ICR1H _SFR_IO8(0x27) - -/* Timer/Counter1 Output Compare Register B */ -#define OCR1B _SFR_IO16(0x28) -#define OCR1BL _SFR_IO8(0x28) -#define OCR1BH _SFR_IO8(0x29) - -/* Timer/Counter1 Output Compare Register A */ -#define OCR1A _SFR_IO16(0x2A) -#define OCR1AL _SFR_IO8(0x2A) -#define OCR1AH _SFR_IO8(0x2B) - -/* Timer/Counter 1 */ -#define TCNT1 _SFR_IO16(0x2C) -#define TCNT1L _SFR_IO8(0x2C) -#define TCNT1H _SFR_IO8(0x2D) - -/* Timer/Counter 1 Control and Status Register */ -#define TCCR1B _SFR_IO8(0x2E) - -/* Timer/Counter 1 Control Register */ -#define TCCR1A _SFR_IO8(0x2F) - -/* Timer/Counter 0 Asynchronous Control & Status Register */ -#define ASSR _SFR_IO8(0x30) - -/* Output Compare Register 0 */ -#define OCR0 _SFR_IO8(0x31) - -/* Timer/Counter 0 */ -#define TCNT0 _SFR_IO8(0x32) - -/* Timer/Counter 0 Control Register */ -#define TCCR0 _SFR_IO8(0x33) - -/* MCU Status Register */ -#define MCUSR _SFR_IO8(0x34) -#define MCUCSR _SFR_IO8(0x34) /* new name in datasheet (2467E-AVR-05/02) */ - -/* MCU general Control Register */ -#define MCUCR _SFR_IO8(0x35) - -/* Timer/Counter Interrupt Flag Register */ -#define TIFR _SFR_IO8(0x36) - -/* Timer/Counter Interrupt MaSK register */ -#define TIMSK _SFR_IO8(0x37) - -/* External Interrupt Flag Register */ -#define EIFR _SFR_IO8(0x38) - -/* External Interrupt MaSK register */ -#define EIMSK _SFR_IO8(0x39) - -/* External Interrupt Control Register B */ -#define EICRB _SFR_IO8(0x3A) - -/* RAM Page Z select register */ -#define RAMPZ _SFR_IO8(0x3B) - -/* XDIV Divide control register */ -#define XDIV _SFR_IO8(0x3C) - -/* 0x3D..0x3E SP */ - -/* 0x3F SREG */ - -/* Extended I/O registers */ - -/* Data Direction Register, Port F */ -#define DDRF _SFR_MEM8(0x61) - -/* Data Register, Port F */ -#define PORTF _SFR_MEM8(0x62) - -/* Input Pins, Port G */ -#define PING _SFR_MEM8(0x63) - -/* Data Direction Register, Port G */ -#define DDRG _SFR_MEM8(0x64) - -/* Data Register, Port G */ -#define PORTG _SFR_MEM8(0x65) - -/* Store Program Memory Control and Status Register */ -#define SPMCR _SFR_MEM8(0x68) -#define SPMCSR _SFR_MEM8(0x68) /* new name in datasheet (2467E-AVR-05/02) */ - -/* External Interrupt Control Register A */ -#define EICRA _SFR_MEM8(0x6A) - -/* External Memory Control Register B */ -#define XMCRB _SFR_MEM8(0x6C) - -/* External Memory Control Register A */ -#define XMCRA _SFR_MEM8(0x6D) - -/* Oscillator Calibration Register */ -#define OSCCAL _SFR_MEM8(0x6F) - -/* 2-wire Serial Interface Bit Rate Register */ -#define TWBR _SFR_MEM8(0x70) - -/* 2-wire Serial Interface Status Register */ -#define TWSR _SFR_MEM8(0x71) - -/* 2-wire Serial Interface Address Register */ -#define TWAR _SFR_MEM8(0x72) - -/* 2-wire Serial Interface Data Register */ -#define TWDR _SFR_MEM8(0x73) - -/* 2-wire Serial Interface Control Register */ -#define TWCR _SFR_MEM8(0x74) - -/* Time Counter 1 Output Compare Register C */ -#define OCR1C _SFR_MEM16(0x78) -#define OCR1CL _SFR_MEM8(0x78) -#define OCR1CH _SFR_MEM8(0x79) - -/* Timer/Counter 1 Control Register C */ -#define TCCR1C _SFR_MEM8(0x7A) - -/* Extended Timer Interrupt Flag Register */ -#define ETIFR _SFR_MEM8(0x7C) - -/* Extended Timer Interrupt Mask Register */ -#define ETIMSK _SFR_MEM8(0x7D) - -/* Timer/Counter 3 Input Capture Register */ -#define ICR3 _SFR_MEM16(0x80) -#define ICR3L _SFR_MEM8(0x80) -#define ICR3H _SFR_MEM8(0x81) - -/* Timer/Counter 3 Output Compare Register C */ -#define OCR3C _SFR_MEM16(0x82) -#define OCR3CL _SFR_MEM8(0x82) -#define OCR3CH _SFR_MEM8(0x83) - -/* Timer/Counter 3 Output Compare Register B */ -#define OCR3B _SFR_MEM16(0x84) -#define OCR3BL _SFR_MEM8(0x84) -#define OCR3BH _SFR_MEM8(0x85) - -/* Timer/Counter 3 Output Compare Register A */ -#define OCR3A _SFR_MEM16(0x86) -#define OCR3AL _SFR_MEM8(0x86) -#define OCR3AH _SFR_MEM8(0x87) - -/* Timer/Counter 3 Counter Register */ -#define TCNT3 _SFR_MEM16(0x88) -#define TCNT3L _SFR_MEM8(0x88) -#define TCNT3H _SFR_MEM8(0x89) - -/* Timer/Counter 3 Control Register B */ -#define TCCR3B _SFR_MEM8(0x8A) - -/* Timer/Counter 3 Control Register A */ -#define TCCR3A _SFR_MEM8(0x8B) - -/* Timer/Counter 3 Control Register C */ -#define TCCR3C _SFR_MEM8(0x8C) - -/* USART0 Baud Rate Register High */ -#define UBRR0H _SFR_MEM8(0x90) - -/* USART0 Control and Status Register C */ -#define UCSR0C _SFR_MEM8(0x95) - -/* USART1 Baud Rate Register High */ -#define UBRR1H _SFR_MEM8(0x98) - -/* USART1 Baud Rate Register Low*/ -#define UBRR1L _SFR_MEM8(0x99) - -/* USART1 Control and Status Register B */ -#define UCSR1B _SFR_MEM8(0x9A) - -/* USART1 Control and Status Register A */ -#define UCSR1A _SFR_MEM8(0x9B) - -/* USART1 I/O Data Register */ -#define UDR1 _SFR_MEM8(0x9C) - -/* USART1 Control and Status Register C */ -#define UCSR1C _SFR_MEM8(0x9D) - -/* Interrupt vectors */ - -/* External Interrupt Request 0 */ -#define INT0_vect_num 1 -#define INT0_vect _VECTOR(1) -#define SIG_INTERRUPT0 _VECTOR(1) - -/* External Interrupt Request 1 */ -#define INT1_vect_num 2 -#define INT1_vect _VECTOR(2) -#define SIG_INTERRUPT1 _VECTOR(2) - -/* External Interrupt Request 2 */ -#define INT2_vect_num 3 -#define INT2_vect _VECTOR(3) -#define SIG_INTERRUPT2 _VECTOR(3) - -/* External Interrupt Request 3 */ -#define INT3_vect_num 4 -#define INT3_vect _VECTOR(4) -#define SIG_INTERRUPT3 _VECTOR(4) - -/* External Interrupt Request 4 */ -#define INT4_vect_num 5 -#define INT4_vect _VECTOR(5) -#define SIG_INTERRUPT4 _VECTOR(5) - -/* External Interrupt Request 5 */ -#define INT5_vect_num 6 -#define INT5_vect _VECTOR(6) -#define SIG_INTERRUPT5 _VECTOR(6) - -/* External Interrupt Request 6 */ -#define INT6_vect_num 7 -#define INT6_vect _VECTOR(7) -#define SIG_INTERRUPT6 _VECTOR(7) - -/* External Interrupt Request 7 */ -#define INT7_vect_num 8 -#define INT7_vect _VECTOR(8) -#define SIG_INTERRUPT7 _VECTOR(8) - -/* Timer/Counter2 Compare Match */ -#define TIMER2_COMP_vect_num 9 -#define TIMER2_COMP_vect _VECTOR(9) -#define SIG_OUTPUT_COMPARE2 _VECTOR(9) - -/* Timer/Counter2 Overflow */ -#define TIMER2_OVF_vect_num 10 -#define TIMER2_OVF_vect _VECTOR(10) -#define SIG_OVERFLOW2 _VECTOR(10) - -/* Timer/Counter1 Capture Event */ -#define TIMER1_CAPT_vect_num 11 -#define TIMER1_CAPT_vect _VECTOR(11) -#define SIG_INPUT_CAPTURE1 _VECTOR(11) - -/* Timer/Counter1 Compare Match A */ -#define TIMER1_COMPA_vect_num 12 -#define TIMER1_COMPA_vect _VECTOR(12) -#define SIG_OUTPUT_COMPARE1A _VECTOR(12) - -/* Timer/Counter Compare Match B */ -#define TIMER1_COMPB_vect_num 13 -#define TIMER1_COMPB_vect _VECTOR(13) -#define SIG_OUTPUT_COMPARE1B _VECTOR(13) - -/* Timer/Counter1 Overflow */ -#define TIMER1_OVF_vect_num 14 -#define TIMER1_OVF_vect _VECTOR(14) -#define SIG_OVERFLOW1 _VECTOR(14) - -/* Timer/Counter0 Compare Match */ -#define TIMER0_COMP_vect_num 15 -#define TIMER0_COMP_vect _VECTOR(15) -#define SIG_OUTPUT_COMPARE0 _VECTOR(15) - -/* Timer/Counter0 Overflow */ -#define TIMER0_OVF_vect_num 16 -#define TIMER0_OVF_vect _VECTOR(16) -#define SIG_OVERFLOW0 _VECTOR(16) - -/* SPI Serial Transfer Complete */ -#define SPI_STC_vect_num 17 -#define SPI_STC_vect _VECTOR(17) -#define SIG_SPI _VECTOR(17) - -/* USART0, Rx Complete */ -#define USART0_RX_vect_num 18 -#define USART0_RX_vect _VECTOR(18) -#define SIG_USART0_RECV _VECTOR(18) -#define SIG_UART0_RECV _VECTOR(18) - -/* USART0 Data Register Empty */ -#define USART0_UDRE_vect_num 19 -#define USART0_UDRE_vect _VECTOR(19) -#define SIG_USART0_DATA _VECTOR(19) -#define SIG_UART0_DATA _VECTOR(19) - -/* USART0, Tx Complete */ -#define USART0_TX_vect_num 20 -#define USART0_TX_vect _VECTOR(20) -#define SIG_USART0_TRANS _VECTOR(20) -#define SIG_UART0_TRANS _VECTOR(20) - -/* ADC Conversion Complete */ -#define ADC_vect_num 21 -#define ADC_vect _VECTOR(21) -#define SIG_ADC _VECTOR(21) - -/* EEPROM Ready */ -#define EE_READY_vect _VECTOR(22) -#define EE_READY_vect _VECTOR(22) -#define SIG_EEPROM_READY _VECTOR(22) - -/* Analog Comparator */ -#define ANALOG_COMP_vect_num 23 -#define ANALOG_COMP_vect _VECTOR(23) -#define SIG_COMPARATOR _VECTOR(23) - -/* Timer/Counter1 Compare Match C */ -#define TIMER1_COMPC_vect_num 24 -#define TIMER1_COMPC_vect _VECTOR(24) -#define SIG_OUTPUT_COMPARE1C _VECTOR(24) - -/* Timer/Counter3 Capture Event */ -#define TIMER3_CAPT_vect_num 25 -#define TIMER3_CAPT_vect _VECTOR(25) -#define SIG_INPUT_CAPTURE3 _VECTOR(25) - -/* Timer/Counter3 Compare Match A */ -#define TIMER3_COMPA_vect_num 26 -#define TIMER3_COMPA_vect _VECTOR(26) -#define SIG_OUTPUT_COMPARE3A _VECTOR(26) - -/* Timer/Counter3 Compare Match B */ -#define TIMER3_COMPB_vect_num 27 -#define TIMER3_COMPB_vect _VECTOR(27) -#define SIG_OUTPUT_COMPARE3B _VECTOR(27) - -/* Timer/Counter3 Compare Match C */ -#define TIMER3_COMPC_vect_num 28 -#define TIMER3_COMPC_vect _VECTOR(28) -#define SIG_OUTPUT_COMPARE3C _VECTOR(28) - -/* Timer/Counter3 Overflow */ -#define TIMER3_OVF_vect_num 29 -#define TIMER3_OVF_vect _VECTOR(29) -#define SIG_OVERFLOW3 _VECTOR(29) - -/* USART1, Rx Complete */ -#define USART1_RX_vect_num 30 -#define USART1_RX_vect _VECTOR(30) -#define SIG_USART1_RECV _VECTOR(30) -#define SIG_UART1_RECV _VECTOR(30) - -/* USART1, Data Register Empty */ -#define USART1_UDRE_vect_num 31 -#define USART1_UDRE_vect _VECTOR(31) -#define SIG_USART1_DATA _VECTOR(31) -#define SIG_UART1_DATA _VECTOR(31) - -/* USART1, Tx Complete */ -#define USART1_TX_vect_num 32 -#define USART1_TX_vect _VECTOR(32) -#define SIG_USART1_TRANS _VECTOR(32) -#define SIG_UART1_TRANS _VECTOR(32) - -/* 2-wire Serial Interface */ -#define TWI_vect_num 33 -#define TWI_vect _VECTOR(33) -#define SIG_2WIRE_SERIAL _VECTOR(33) - -/* Store Program Memory Read */ -#define SPM_READY_vect_num 34 -#define SPM_READY_vect _VECTOR(34) -#define SPM_READY_vect _VECTOR(34) -#define SIG_SPM_READY _VECTOR(34) - -#define _VECTORS_SIZE 140 - -/* - The Register Bit names are represented by their bit number (0-7). -*/ - -/* 2-wire Control Register - TWCR */ -#define TWINT 7 -#define TWEA 6 -#define TWSTA 5 -#define TWSTO 4 -#define TWWC 3 -#define TWEN 2 -#define TWIE 0 - -/* 2-wire Address Register - TWAR */ -#define TWA6 7 -#define TWA5 6 -#define TWA4 5 -#define TWA3 4 -#define TWA2 3 -#define TWA1 2 -#define TWA0 1 -#define TWGCE 0 - -/* 2-wire Status Register - TWSR */ -#define TWS7 7 -#define TWS6 6 -#define TWS5 5 -#define TWS4 4 -#define TWS3 3 -#define TWPS1 1 -#define TWPS0 0 - -/* External Memory Control Register A - XMCRA */ -#define SRL2 6 -#define SRL1 5 -#define SRL0 4 -#define SRW01 3 -#define SRW00 2 -#define SRW11 1 - -/* External Memory Control Register B - XMCRA */ -#define XMBK 7 -#define XMM2 2 -#define XMM1 1 -#define XMM0 0 - -/* XDIV Divide control register - XDIV */ -#define XDIVEN 7 -#define XDIV6 6 -#define XDIV5 5 -#define XDIV4 4 -#define XDIV3 3 -#define XDIV2 2 -#define XDIV1 1 -#define XDIV0 0 - -/* RAM Page Z select register - RAMPZ */ -#define RAMPZ0 0 - -/* External Interrupt Control Register A - EICRA */ -#define ISC31 7 -#define ISC30 6 -#define ISC21 5 -#define ISC20 4 -#define ISC11 3 -#define ISC10 2 -#define ISC01 1 -#define ISC00 0 - -/* External Interrupt Control Register B - EICRB */ -#define ISC71 7 -#define ISC70 6 -#define ISC61 5 -#define ISC60 4 -#define ISC51 3 -#define ISC50 2 -#define ISC41 1 -#define ISC40 0 - -/* Store Program Memory Control Register - SPMCSR, SPMCR */ -#define SPMIE 7 -#define RWWSB 6 -#define RWWSRE 4 -#define BLBSET 3 -#define PGWRT 2 -#define PGERS 1 -#define SPMEN 0 - -/* External Interrupt MaSK register - EIMSK */ -#define INT7 7 -#define INT6 6 -#define INT5 5 -#define INT4 4 -#define INT3 3 -#define INT2 2 -#define INT1 1 -#define INT0 0 - -/* External Interrupt Flag Register - EIFR */ -#define INTF7 7 -#define INTF6 6 -#define INTF5 5 -#define INTF4 4 -#define INTF3 3 -#define INTF2 2 -#define INTF1 1 -#define INTF0 0 - -/* Timer/Counter Interrupt MaSK register - TIMSK */ -#define OCIE2 7 -#define TOIE2 6 -#define TICIE1 5 -#define OCIE1A 4 -#define OCIE1B 3 -#define TOIE1 2 -#define OCIE0 1 -#define TOIE0 0 - -/* Timer/Counter Interrupt Flag Register - TIFR */ -#define OCF2 7 -#define TOV2 6 -#define ICF1 5 -#define OCF1A 4 -#define OCF1B 3 -#define TOV1 2 -#define OCF0 1 -#define TOV0 0 - -/* Extended Timer Interrupt MaSK register - ETIMSK */ -#define TICIE3 5 -#define OCIE3A 4 -#define OCIE3B 3 -#define TOIE3 2 -#define OCIE3C 1 -#define OCIE1C 0 - -/* Extended Timer Interrupt Flag Register - ETIFR */ -#define ICF3 5 -#define OCF3A 4 -#define OCF3B 3 -#define TOV3 2 -#define OCF3C 1 -#define OCF1C 0 - -/* MCU general Control Register - MCUCR */ -#define SRE 7 -#define SRW 6 -#define SRW10 6 /* new name in datasheet (2467E-AVR-05/02) */ -#define SE 5 -#define SM1 4 -#define SM0 3 -#define SM2 2 -#define IVSEL 1 -#define IVCE 0 - -/* MCU Status Register - MCUSR, MCUCSR */ -#define JTD 7 -#define JTRF 4 -#define WDRF 3 -#define BORF 2 -#define EXTRF 1 -#define PORF 0 - -/* Timer/Counter Control Register (generic) */ -#define FOC 7 -#define WGM0 6 -#define COM1 5 -#define COM0 4 -#define WGM1 3 -#define CS2 2 -#define CS1 1 -#define CS0 0 - -/* Timer/Counter 0 Control Register - TCCR0 */ -#define FOC0 7 -#define WGM00 6 -#define COM01 5 -#define COM00 4 -#define WGM01 3 -#define CS02 2 -#define CS01 1 -#define CS00 0 - -/* Timer/Counter 2 Control Register - TCCR2 */ -#define FOC2 7 -#define WGM20 6 -#define COM21 5 -#define COM20 4 -#define WGM21 3 -#define CS22 2 -#define CS21 1 -#define CS20 0 - -/* Timer/Counter 0 Asynchronous Control & Status Register - ASSR */ -#define AS0 3 -#define TCN0UB 2 -#define OCR0UB 1 -#define TCR0UB 0 - -/* Timer/Counter Control Register A (generic) */ -#define COMA1 7 -#define COMA0 6 -#define COMB1 5 -#define COMB0 4 -#define COMC1 3 -#define COMC0 2 -#define WGMA1 1 -#define WGMA0 0 - -/* Timer/Counter 1 Control and Status Register A - TCCR1A */ -#define COM1A1 7 -#define COM1A0 6 -#define COM1B1 5 -#define COM1B0 4 -#define COM1C1 3 -#define COM1C0 2 -#define WGM11 1 -#define WGM10 0 - -/* Timer/Counter 3 Control and Status Register A - TCCR3A */ -#define COM3A1 7 -#define COM3A0 6 -#define COM3B1 5 -#define COM3B0 4 -#define COM3C1 3 -#define COM3C0 2 -#define WGM31 1 -#define WGM30 0 - -/* Timer/Counter Control and Status Register B (generic) */ -#define ICNC 7 -#define ICES 6 -#define WGMB3 4 -#define WGMB2 3 -#define CSB2 2 -#define CSB1 1 -#define CSB0 0 - -/* Timer/Counter 1 Control and Status Register B - TCCR1B */ -#define ICNC1 7 -#define ICES1 6 -#define WGM13 4 -#define WGM12 3 -#define CS12 2 -#define CS11 1 -#define CS10 0 - -/* Timer/Counter 3 Control and Status Register B - TCCR3B */ -#define ICNC3 7 -#define ICES3 6 -#define WGM33 4 -#define WGM32 3 -#define CS32 2 -#define CS31 1 -#define CS30 0 - -/* Timer/Counter Control Register C (generic) */ -#define FOCA 7 -#define FOCB 6 -#define FOCC 5 - -/* Timer/Counter 3 Control Register C - TCCR3C */ -#define FOC3A 7 -#define FOC3B 6 -#define FOC3C 5 - -/* Timer/Counter 1 Control Register C - TCCR1C */ -#define FOC1A 7 -#define FOC1B 6 -#define FOC1C 5 - -/* On-chip Debug Register - OCDR */ -#define IDRD 7 -#define OCDR7 7 -#define OCDR6 6 -#define OCDR5 5 -#define OCDR4 4 -#define OCDR3 3 -#define OCDR2 2 -#define OCDR1 1 -#define OCDR0 0 - -/* Watchdog Timer Control Register - WDTCR */ -#define WDCE 4 -#define WDE 3 -#define WDP2 2 -#define WDP1 1 -#define WDP0 0 - -/* - The ADHSM bit has been removed from all documentation, - as being not needed at all since the comparator has proven - to be fast enough even without feeding it more power. -*/ - -/* Special Function I/O Register - SFIOR */ -#define TSM 7 -#define ACME 3 -#define PUD 2 -#define PSR0 1 -#define PSR321 0 - -/* SPI Status Register - SPSR */ -#define SPIF 7 -#define WCOL 6 -#define SPI2X 0 - -/* SPI Control Register - SPCR */ -#define SPIE 7 -#define SPE 6 -#define DORD 5 -#define MSTR 4 -#define CPOL 3 -#define CPHA 2 -#define SPR1 1 -#define SPR0 0 - -/* USART Register C (generic) */ -#define UMSEL 6 -#define UPM1 5 -#define UPM0 4 -#define USBS 3 -#define UCSZ1 2 -#define UCSZ0 1 -#define UCPOL 0 - -/* USART1 Register C - UCSR1C */ -#define UMSEL1 6 -#define UPM11 5 -#define UPM10 4 -#define USBS1 3 -#define UCSZ11 2 -#define UCSZ10 1 -#define UCPOL1 0 - -/* USART0 Register C - UCSR0C */ -#define UMSEL0 6 -#define UPM01 5 -#define UPM00 4 -#define USBS0 3 -#define UCSZ01 2 -#define UCSZ00 1 -#define UCPOL0 0 - -/* USART Status Register A (generic) */ -#define RXC 7 -#define TXC 6 -#define UDRE 5 -#define FE 4 -#define DOR 3 -#define UPE 2 -#define U2X 1 -#define MPCM 0 - -/* USART1 Status Register A - UCSR1A */ -#define RXC1 7 -#define TXC1 6 -#define UDRE1 5 -#define FE1 4 -#define DOR1 3 -#define UPE1 2 -#define U2X1 1 -#define MPCM1 0 - -/* USART0 Status Register A - UCSR0A */ -#define RXC0 7 -#define TXC0 6 -#define UDRE0 5 -#define FE0 4 -#define DOR0 3 -#define UPE0 2 -#define U2X0 1 -#define MPCM0 0 - -/* USART Control Register B (generic) */ -#define RXCIE 7 -#define TXCIE 6 -#define UDRIE 5 -#define RXEN 4 -#define TXEN 3 -#define UCSZ 2 -#define UCSZ2 2 /* new name in datasheet (2467E-AVR-05/02) */ -#define RXB8 1 -#define TXB8 0 - -/* USART1 Control Register B - UCSR1B */ -#define RXCIE1 7 -#define TXCIE1 6 -#define UDRIE1 5 -#define RXEN1 4 -#define TXEN1 3 -#define UCSZ12 2 -#define RXB81 1 -#define TXB81 0 - -/* USART0 Control Register B - UCSR0B */ -#define RXCIE0 7 -#define TXCIE0 6 -#define UDRIE0 5 -#define RXEN0 4 -#define TXEN0 3 -#define UCSZ02 2 -#define RXB80 1 -#define TXB80 0 - -/* Analog Comparator Control and Status Register - ACSR */ -#define ACD 7 -#define ACBG 6 -#define ACO 5 -#define ACI 4 -#define ACIE 3 -#define ACIC 2 -#define ACIS1 1 -#define ACIS0 0 - -/* ADC Control and status register - ADCSRA */ -#define ADEN 7 -#define ADSC 6 -#define ADFR 5 -#define ADIF 4 -#define ADIE 3 -#define ADPS2 2 -#define ADPS1 1 -#define ADPS0 0 - -/* ADC Multiplexer select - ADMUX */ -#define REFS1 7 -#define REFS0 6 -#define ADLAR 5 -#define MUX4 4 -#define MUX3 3 -#define MUX2 2 -#define MUX1 1 -#define MUX0 0 - -/* Port A Data Register - PORTA */ -#define PA7 7 -#define PA6 6 -#define PA5 5 -#define PA4 4 -#define PA3 3 -#define PA2 2 -#define PA1 1 -#define PA0 0 - -/* Port A Data Direction Register - DDRA */ -#define DDA7 7 -#define DDA6 6 -#define DDA5 5 -#define DDA4 4 -#define DDA3 3 -#define DDA2 2 -#define DDA1 1 -#define DDA0 0 - -/* Port A Input Pins - PINA */ -#define PINA7 7 -#define PINA6 6 -#define PINA5 5 -#define PINA4 4 -#define PINA3 3 -#define PINA2 2 -#define PINA1 1 -#define PINA0 0 - -/* Port B Data Register - PORTB */ -#define PB7 7 -#define PB6 6 -#define PB5 5 -#define PB4 4 -#define PB3 3 -#define PB2 2 -#define PB1 1 -#define PB0 0 - -/* Port B Data Direction Register - DDRB */ -#define DDB7 7 -#define DDB6 6 -#define DDB5 5 -#define DDB4 4 -#define DDB3 3 -#define DDB2 2 -#define DDB1 1 -#define DDB0 0 - -/* Port B Input Pins - PINB */ -#define PINB7 7 -#define PINB6 6 -#define PINB5 5 -#define PINB4 4 -#define PINB3 3 -#define PINB2 2 -#define PINB1 1 -#define PINB0 0 - -/* Port C Data Register - PORTC */ -#define PC7 7 -#define PC6 6 -#define PC5 5 -#define PC4 4 -#define PC3 3 -#define PC2 2 -#define PC1 1 -#define PC0 0 - -/* Port C Data Direction Register - DDRC */ -#define DDC7 7 -#define DDC6 6 -#define DDC5 5 -#define DDC4 4 -#define DDC3 3 -#define DDC2 2 -#define DDC1 1 -#define DDC0 0 - -/* Port C Input Pins - PINC */ -#define PINC7 7 -#define PINC6 6 -#define PINC5 5 -#define PINC4 4 -#define PINC3 3 -#define PINC2 2 -#define PINC1 1 -#define PINC0 0 - -/* Port D Data Register - PORTD */ -#define PD7 7 -#define PD6 6 -#define PD5 5 -#define PD4 4 -#define PD3 3 -#define PD2 2 -#define PD1 1 -#define PD0 0 - -/* Port D Data Direction Register - DDRD */ -#define DDD7 7 -#define DDD6 6 -#define DDD5 5 -#define DDD4 4 -#define DDD3 3 -#define DDD2 2 -#define DDD1 1 -#define DDD0 0 - -/* Port D Input Pins - PIND */ -#define PIND7 7 -#define PIND6 6 -#define PIND5 5 -#define PIND4 4 -#define PIND3 3 -#define PIND2 2 -#define PIND1 1 -#define PIND0 0 - -/* Port E Data Register - PORTE */ -#define PE7 7 -#define PE6 6 -#define PE5 5 -#define PE4 4 -#define PE3 3 -#define PE2 2 -#define PE1 1 -#define PE0 0 - -/* Port E Data Direction Register - DDRE */ -#define DDE7 7 -#define DDE6 6 -#define DDE5 5 -#define DDE4 4 -#define DDE3 3 -#define DDE2 2 -#define DDE1 1 -#define DDE0 0 - -/* Port E Input Pins - PINE */ -#define PINE7 7 -#define PINE6 6 -#define PINE5 5 -#define PINE4 4 -#define PINE3 3 -#define PINE2 2 -#define PINE1 1 -#define PINE0 0 - -/* Port F Data Register - PORTF */ -#define PF7 7 -#define PF6 6 -#define PF5 5 -#define PF4 4 -#define PF3 3 -#define PF2 2 -#define PF1 1 -#define PF0 0 - -/* Port F Data Direction Register - DDRF */ -#define DDF7 7 -#define DDF6 6 -#define DDF5 5 -#define DDF4 4 -#define DDF3 3 -#define DDF2 2 -#define DDF1 1 -#define DDF0 0 - -/* Port F Input Pins - PINF */ -#define PINF7 7 -#define PINF6 6 -#define PINF5 5 -#define PINF4 4 -#define PINF3 3 -#define PINF2 2 -#define PINF1 1 -#define PINF0 0 - -/* Port G Data Register - PORTG */ -#define PG4 4 -#define PG3 3 -#define PG2 2 -#define PG1 1 -#define PG0 0 - -/* Port G Data Direction Register - DDRG */ -#define DDG4 4 -#define DDG3 3 -#define DDG2 2 -#define DDG1 1 -#define DDG0 0 - -/* Port G Input Pins - PING */ -#define PING4 4 -#define PING3 3 -#define PING2 2 -#define PING1 1 -#define PING0 0 - -/* EEPROM Control Register */ -#define EERIE 3 -#define EEMWE 2 -#define EEWE 1 -#define EERE 0 - -/* Constants */ -#define SPM_PAGESIZE 256 -#define RAMSTART 0x100 -#define RAMEND 0x10FF /* Last On-Chip SRAM Location */ -#define XRAMEND 0xFFFF -#define E2END 0x0FFF -#define E2PAGESIZE 8 -#define FLASHEND 0x1FFFF - - -/* Fuses */ - -#define FUSE_MEMORY_SIZE 3 - -/* Low Fuse Byte */ -#define FUSE_CKSEL0 (unsigned char)~_BV(0) -#define FUSE_CKSEL1 (unsigned char)~_BV(1) -#define FUSE_CKSEL2 (unsigned char)~_BV(2) -#define FUSE_CKSEL3 (unsigned char)~_BV(3) -#define FUSE_SUT0 (unsigned char)~_BV(4) -#define FUSE_SUT1 (unsigned char)~_BV(5) -#define FUSE_BODEN (unsigned char)~_BV(6) -#define FUSE_BODLEVEL (unsigned char)~_BV(7) -#define LFUSE_DEFAULT (FUSE_CKSEL1 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0) - -/* High Fuse Byte */ -#define FUSE_BOOTRST (unsigned char)~_BV(0) -#define FUSE_BOOTSZ0 (unsigned char)~_BV(1) -#define FUSE_BOOTSZ1 (unsigned char)~_BV(2) -#define FUSE_EESAVE (unsigned char)~_BV(3) -#define FUSE_CKOPT (unsigned char)~_BV(4) -#define FUSE_SPIEN (unsigned char)~_BV(5) -#define FUSE_JTAGEN (unsigned char)~_BV(6) -#define FUSE_OCDEN (unsigned char)~_BV(7) -#define HFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_SPIEN & FUSE_JTAGEN) - -/* Extended Fuse Byte */ -#define FUSE_WDTON (unsigned char)~_BV(0) -#define FUSE_M103C (unsigned char)~_BV(1) -#define EFUSE_DEFAULT (FUSE_M103C) - - -/* Lock Bits */ -#define __LOCK_BITS_EXIST -#define __BOOT_LOCK_BITS_0_EXIST -#define __BOOT_LOCK_BITS_1_EXIST - - -/* Signature */ -#define SIGNATURE_0 0x1E -#define SIGNATURE_1 0x97 -#define SIGNATURE_2 0x02 - - - -/* Deprecated items */ -#if !defined(__AVR_LIBC_DEPRECATED_ENABLE__) - -#pragma GCC system_header - -#pragma GCC poison MCUSR -#pragma GCC poison SPMCR - -#pragma GCC poison SIG_INTERRUPT0 -#pragma GCC poison SIG_INTERRUPT1 -#pragma GCC poison SIG_INTERRUPT2 -#pragma GCC poison SIG_INTERRUPT3 -#pragma GCC poison SIG_INTERRUPT4 -#pragma GCC poison SIG_INTERRUPT5 -#pragma GCC poison SIG_INTERRUPT6 -#pragma GCC poison SIG_INTERRUPT7 -#pragma GCC poison SIG_OUTPUT_COMPARE2 -#pragma GCC poison SIG_OVERFLOW2 -#pragma GCC poison SIG_INPUT_CAPTURE1 -#pragma GCC poison SIG_OUTPUT_COMPARE1A -#pragma GCC poison SIG_OUTPUT_COMPARE1B -#pragma GCC poison SIG_OVERFLOW1 -#pragma GCC poison SIG_OUTPUT_COMPARE0 -#pragma GCC poison SIG_OVERFLOW0 -#pragma GCC poison SIG_SPI -#pragma GCC poison SIG_USART0_RECV -#pragma GCC poison SIG_UART0_RECV -#pragma GCC poison SIG_USART0_DATA -#pragma GCC poison SIG_UART0_DATA -#pragma GCC poison SIG_USART0_TRANS -#pragma GCC poison SIG_UART0_TRANS -#pragma GCC poison SIG_ADC -#pragma GCC poison SIG_EEPROM_READY -#pragma GCC poison SIG_COMPARATOR -#pragma GCC poison SIG_OUTPUT_COMPARE1C -#pragma GCC poison SIG_INPUT_CAPTURE3 -#pragma GCC poison SIG_OUTPUT_COMPARE3A -#pragma GCC poison SIG_OUTPUT_COMPARE3B -#pragma GCC poison SIG_OUTPUT_COMPARE3C -#pragma GCC poison SIG_OVERFLOW3 -#pragma GCC poison SIG_USART1_RECV -#pragma GCC poison SIG_UART1_RECV -#pragma GCC poison SIG_USART1_DATA -#pragma GCC poison SIG_UART1_DATA -#pragma GCC poison SIG_USART1_TRANS -#pragma GCC poison SIG_UART1_TRANS -#pragma GCC poison SIG_2WIRE_SERIAL -#pragma GCC poison SIG_SPM_READY - - -#endif /* !defined(__AVR_LIBC_DEPRECATED_ENABLE__) */ - -#define SLEEP_MODE_IDLE (0x00<<2) -#define SLEEP_MODE_ADC (0x02<<2) -#define SLEEP_MODE_PWR_DOWN (0x04<<2) -#define SLEEP_MODE_PWR_SAVE (0x06<<2) -#define SLEEP_MODE_STANDBY (0x05<<2) -#define SLEEP_MODE_EXT_STANDBY (0x07<<2) - -#endif /* _AVR_IOM128_H_ */ diff --git a/arduino/hardware/tools/avr/avr/include/avr/iom1280.h b/arduino/hardware/tools/avr/avr/include/avr/iom1280.h deleted file mode 100644 index 54f477f..0000000 --- a/arduino/hardware/tools/avr/avr/include/avr/iom1280.h +++ /dev/null @@ -1,101 +0,0 @@ -/* Copyright (c) 2005 Anatoly Sokolov - All rights reserved. - - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - * Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - * Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in - the documentation and/or other materials provided with the - distribution. - - * Neither the name of the copyright holders nor the names of - contributors may be used to endorse or promote products derived - from this software without specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. */ - -/* $Id: iom1280.h 2102 2010-03-16 22:52:39Z joerg_wunsch $ */ - -/* avr/iom1280.h - definitions for ATmega1280 */ - -#ifndef _AVR_IOM1280_H_ -#define _AVR_IOM1280_H_ 1 - -#include - -/* Constants */ -#define SPM_PAGESIZE 256 -#define RAMSTART 0x200 -#define RAMEND 0x21FF -#define XRAMEND 0xFFFF -#define E2END 0xFFF -#define E2PAGESIZE 8 -#define FLASHEND 0x1FFFF - - -/* Fuses */ - -#define FUSE_MEMORY_SIZE 3 - -/* Low Fuse Byte */ -#define FUSE_CKSEL0 (unsigned char)~_BV(0) -#define FUSE_CKSEL1 (unsigned char)~_BV(1) -#define FUSE_CKSEL2 (unsigned char)~_BV(2) -#define FUSE_CKSEL3 (unsigned char)~_BV(3) -#define FUSE_SUT0 (unsigned char)~_BV(4) -#define FUSE_SUT1 (unsigned char)~_BV(5) -#define FUSE_CKOUT (unsigned char)~_BV(6) -#define FUSE_CKDIV8 (unsigned char)~_BV(7) -#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8) - -/* High Fuse Byte */ -#define FUSE_BOOTRST (unsigned char)~_BV(0) -#define FUSE_BOOTSZ0 (unsigned char)~_BV(1) -#define FUSE_BOOTSZ1 (unsigned char)~_BV(2) -#define FUSE_EESAVE (unsigned char)~_BV(3) -#define FUSE_WDTON (unsigned char)~_BV(4) -#define FUSE_SPIEN (unsigned char)~_BV(5) -#define FUSE_JTAGEN (unsigned char)~_BV(6) -#define FUSE_OCDEN (unsigned char)~_BV(7) -#define HFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_SPIEN & FUSE_JTAGEN) - -/* Extended Fuse Byte */ -#define FUSE_BODLEVEL0 (unsigned char)~_BV(0) -#define FUSE_BODLEVEL1 (unsigned char)~_BV(1) -#define FUSE_BODLEVEL2 (unsigned char)~_BV(2) -#define EFUSE_DEFAULT (0xFF) - - -/* Lock Bits */ -#define __LOCK_BITS_EXIST -#define __BOOT_LOCK_BITS_0_EXIST -#define __BOOT_LOCK_BITS_1_EXIST - - -/* Signature */ -#define SIGNATURE_0 0x1E -#define SIGNATURE_1 0x97 -#define SIGNATURE_2 0x03 - -#define SLEEP_MODE_IDLE (0x00<<1) -#define SLEEP_MODE_ADC (0x01<<1) -#define SLEEP_MODE_PWR_DOWN (0x02<<1) -#define SLEEP_MODE_PWR_SAVE (0x03<<1) -#define SLEEP_MODE_STANDBY (0x06<<1) -#define SLEEP_MODE_EXT_STANDBY (0x07<<1) - -#endif /* _AVR_IOM1280_H_ */ diff --git a/arduino/hardware/tools/avr/avr/include/avr/iom1281.h b/arduino/hardware/tools/avr/avr/include/avr/iom1281.h deleted file mode 100644 index 07df33e..0000000 --- a/arduino/hardware/tools/avr/avr/include/avr/iom1281.h +++ /dev/null @@ -1,101 +0,0 @@ -/* Copyright (c) 2005 Anatoly Sokolov - All rights reserved. - - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - * Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - * Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in - the documentation and/or other materials provided with the - distribution. - - * Neither the name of the copyright holders nor the names of - contributors may be used to endorse or promote products derived - from this software without specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. */ - -/* $Id: iom1281.h 2115 2010-04-05 23:19:53Z arcanum $ */ - -/* avr/iom1281.h - definitions for ATmega1281 */ - -#ifndef _AVR_IOM1281_H_ -#define _AVR_IOM1281_H_ 1 - -#include - -/* Constants */ -#define SPM_PAGESIZE 256 -#define RAMSTART (0x200) -#define RAMEND 0x21FF -#define XRAMEND 0xFFFF -#define E2END 0xFFF -#define E2PAGESIZE 8 -#define FLASHEND 0x1FFFF - - -/* Fuses */ - -#define FUSE_MEMORY_SIZE 3 - -/* Low Fuse Byte */ -#define FUSE_CKSEL0 (unsigned char)~_BV(0) -#define FUSE_CKSEL1 (unsigned char)~_BV(1) -#define FUSE_CKSEL2 (unsigned char)~_BV(2) -#define FUSE_CKSEL3 (unsigned char)~_BV(3) -#define FUSE_SUT0 (unsigned char)~_BV(4) -#define FUSE_SUT1 (unsigned char)~_BV(5) -#define FUSE_CKOUT (unsigned char)~_BV(6) -#define FUSE_CKDIV8 (unsigned char)~_BV(7) -#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8) - -/* High Fuse Byte */ -#define FUSE_BOOTRST (unsigned char)~_BV(0) -#define FUSE_BOOTSZ0 (unsigned char)~_BV(1) -#define FUSE_BOOTSZ1 (unsigned char)~_BV(2) -#define FUSE_EESAVE (unsigned char)~_BV(3) -#define FUSE_WDTON (unsigned char)~_BV(4) -#define FUSE_SPIEN (unsigned char)~_BV(5) -#define FUSE_JTAGEN (unsigned char)~_BV(6) -#define FUSE_OCDEN (unsigned char)~_BV(7) -#define HFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_SPIEN & FUSE_JTAGEN) - -/* Extended Fuse Byte */ -#define FUSE_BODLEVEL0 (unsigned char)~_BV(0) -#define FUSE_BODLEVEL1 (unsigned char)~_BV(1) -#define FUSE_BODLEVEL2 (unsigned char)~_BV(2) -#define EFUSE_DEFAULT (0xFF) - - -/* Lock Bits */ -#define __LOCK_BITS_EXIST -#define __BOOT_LOCK_BITS_0_EXIST -#define __BOOT_LOCK_BITS_1_EXIST - - -/* Signature */ -#define SIGNATURE_0 0x1E -#define SIGNATURE_1 0x97 -#define SIGNATURE_2 0x04 - -#define SLEEP_MODE_IDLE (0x00<<1) -#define SLEEP_MODE_ADC (0x01<<1) -#define SLEEP_MODE_PWR_DOWN (0x02<<1) -#define SLEEP_MODE_PWR_SAVE (0x03<<1) -#define SLEEP_MODE_STANDBY (0x06<<1) -#define SLEEP_MODE_EXT_STANDBY (0x07<<1) - -#endif /* _AVR_IOM1281_H_ */ diff --git a/arduino/hardware/tools/avr/avr/include/avr/iom1284.h b/arduino/hardware/tools/avr/avr/include/avr/iom1284.h deleted file mode 100644 index b2015c0..0000000 --- a/arduino/hardware/tools/avr/avr/include/avr/iom1284.h +++ /dev/null @@ -1,1099 +0,0 @@ -/***************************************************************************** - * - * Copyright (C) 2015 Atmel Corporation - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * - * * Neither the name of the copyright holders nor the names of - * contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - ****************************************************************************/ - - -#ifndef _AVR_ATMEGA1284_H_INCLUDED -#define _AVR_ATMEGA1284_H_INCLUDED - - -#ifndef _AVR_IO_H_ -# error "Include instead of this file." -#endif - -#ifndef _AVR_IOXXX_H_ -# define _AVR_IOXXX_H_ "iom1284.h" -#else -# error "Attempt to include more than one file." -#endif - -/* Registers and associated bit numbers */ - -#define PINA _SFR_IO8(0x00) -#define PINA7 7 -#define PINA6 6 -#define PINA5 5 -#define PINA4 4 -#define PINA3 3 -#define PINA2 2 -#define PINA1 1 -#define PINA0 0 - -#define DDRA _SFR_IO8(0x01) -#define DDRA7 7 -// Inserted "DDA7" from "DDRA7" due to compatibility -#define DDA7 7 -#define DDRA6 6 -// Inserted "DDA6" from "DDRA6" due to compatibility -#define DDA6 6 -#define DDRA5 5 -// Inserted "DDA5" from "DDRA5" due to compatibility -#define DDA5 5 -#define DDRA4 4 -// Inserted "DDA4" from "DDRA4" due to compatibility -#define DDA4 4 -#define DDRA3 3 -// Inserted "DDA3" from "DDRA3" due to compatibility -#define DDA3 3 -#define DDRA2 2 -// Inserted "DDA2" from "DDRA2" due to compatibility -#define DDA2 2 -#define DDRA1 1 -// Inserted "DDA1" from "DDRA1" due to compatibility -#define DDA1 1 -#define DDRA0 0 -// Inserted "DDA0" from "DDRA0" due to compatibility -#define DDA0 0 - -#define PORTA _SFR_IO8(0x02) -#define PORTA7 7 -#define PORTA6 6 -#define PORTA5 5 -#define PORTA4 4 -#define PORTA3 3 -#define PORTA2 2 -#define PORTA1 1 -#define PORTA0 0 - -#define PINB _SFR_IO8(0x03) -#define PINB7 7 -#define PINB6 6 -#define PINB5 5 -#define PINB4 4 -#define PINB3 3 -#define PINB2 2 -#define PINB1 1 -#define PINB0 0 - -#define DDRB _SFR_IO8(0x04) -#define DDRB7 7 -// Inserted "DDB7" from "DDRB7" due to compatibility -#define DDB7 7 -#define DDRB6 6 -// Inserted "DDB6" from "DDRB6" due to compatibility -#define DDB6 6 -#define DDRB5 5 -// Inserted "DDB5" from "DDRB5" due to compatibility -#define DDB5 5 -#define DDRB4 4 -// Inserted "DDB4" from "DDRB4" due to compatibility -#define DDB4 4 -#define DDRB3 3 -// Inserted "DDB3" from "DDRB3" due to compatibility -#define DDB3 3 -#define DDRB2 2 -// Inserted "DDB2" from "DDRB2" due to compatibility -#define DDB2 2 -#define DDRB1 1 -// Inserted "DDB1" from "DDRB1" due to compatibility -#define DDB1 1 -#define DDRB0 0 -// Inserted "DDB0" from "DDRB0" due to compatibility -#define DDB0 0 - -#define PORTB _SFR_IO8(0x05) -#define PORTB7 7 -#define PORTB6 6 -#define PORTB5 5 -#define PORTB4 4 -#define PORTB3 3 -#define PORTB2 2 -#define PORTB1 1 -#define PORTB0 0 - -#define PINC _SFR_IO8(0x06) -#define PINC7 7 -#define PINC6 6 -#define PINC5 5 -#define PINC4 4 -#define PINC3 3 -#define PINC2 2 -#define PINC1 1 -#define PINC0 0 - -#define DDRC _SFR_IO8(0x07) -#define DDRC7 7 -// Inserted "DDC7" from "DDRC7" due to compatibility -#define DDC7 7 -#define DDRC6 6 -// Inserted "DDC6" from "DDRC6" due to compatibility -#define DDC6 6 -#define DDRC5 5 -// Inserted "DDC5" from "DDRC5" due to compatibility -#define DDC5 5 -#define DDRC4 4 -// Inserted "DDC4" from "DDRC4" due to compatibility -#define DDC4 4 -#define DDRC3 3 -// Inserted "DDC3" from "DDRC3" due to compatibility -#define DDC3 3 -#define DDRC2 2 -// Inserted "DDC2" from "DDRC2" due to compatibility -#define DDC2 2 -#define DDRC1 1 -// Inserted "DDC1" from "DDRC1" due to compatibility -#define DDC1 1 -#define DDRC0 0 -// Inserted "DDC0" from "DDRC0" due to compatibility -#define DDC0 0 - -#define PORTC _SFR_IO8(0x08) -#define PORTC7 7 -#define PORTC6 6 -#define PORTC5 5 -#define PORTC4 4 -#define PORTC3 3 -#define PORTC2 2 -#define PORTC1 1 -#define PORTC0 0 - -#define PIND _SFR_IO8(0x09) -#define PIND7 7 -#define PIND6 6 -#define PIND5 5 -#define PIND4 4 -#define PIND3 3 -#define PIND2 2 -#define PIND1 1 -#define PIND0 0 - -#define DDRD _SFR_IO8(0x0A) -#define DDRD7 7 -// Inserted "DDD7" from "DDRD7" due to compatibility -#define DDD7 7 -#define DDRD6 6 -// Inserted "DDD6" from "DDRD6" due to compatibility -#define DDD6 6 -#define DDRD5 5 -// Inserted "DDD5" from "DDRD5" due to compatibility -#define DDD5 5 -#define DDRD4 4 -// Inserted "DDD4" from "DDRD4" due to compatibility -#define DDD4 4 -#define DDRD3 3 -// Inserted "DDD3" from "DDRD3" due to compatibility -#define DDD3 3 -#define DDRD2 2 -// Inserted "DDD2" from "DDRD2" due to compatibility -#define DDD2 2 -#define DDRD1 1 -// Inserted "DDD1" from "DDRD1" due to compatibility -#define DDD1 1 -#define DDRD0 0 -// Inserted "DDD0" from "DDRD0" due to compatibility -#define DDD0 0 - -#define PORTD _SFR_IO8(0x0B) -#define PORTD7 7 -#define PORTD6 6 -#define PORTD5 5 -#define PORTD4 4 -#define PORTD3 3 -#define PORTD2 2 -#define PORTD1 1 -#define PORTD0 0 - -/* Reserved [0x0C..0x14] */ - -#define TIFR0 _SFR_IO8(0x15) -#define TOV0 0 -#define OCF0A 1 -#define OCF0B 2 - -#define TIFR1 _SFR_IO8(0x16) -#define TOV1 0 -#define OCF1A 1 -#define OCF1B 2 -#define ICF1 5 - -#define TIFR2 _SFR_IO8(0x17) -#define TOV2 0 -#define OCF2A 1 -#define OCF2B 2 - -#define TIFR3 _SFR_IO8(0x18) -#define TOV3 0 -#define OCF3A 1 -#define OCF3B 2 -#define ICF3 5 - -/* Reserved [0x19..0x1A] */ - -#define PCIFR _SFR_IO8(0x1B) -#define PCIF0 0 -#define PCIF1 1 -#define PCIF2 2 -#define PCIF3 3 - -#define EIFR _SFR_IO8(0x1C) -#define INTF0 0 -#define INTF1 1 -#define INTF2 2 - -#define EIMSK _SFR_IO8(0x1D) -#define INT0 0 -#define INT1 1 -#define INT2 2 - -#define GPIOR0 _SFR_IO8(0x1E) -#define GPIOR00 0 -#define GPIOR01 1 -#define GPIOR02 2 -#define GPIOR03 3 -#define GPIOR04 4 -#define GPIOR05 5 -#define GPIOR06 6 -#define GPIOR07 7 - -#define EECR _SFR_IO8(0x1F) -#define EERE 0 -#define EEPE 1 -#define EEMPE 2 -#define EERIE 3 -#define EEPM0 4 -#define EEPM1 5 - -#define EEDR _SFR_IO8(0x20) - -/* Combine EEARL and EEARH */ -#define EEAR _SFR_IO16(0x21) - -#define EEARL _SFR_IO8(0x21) -#define EEARH _SFR_IO8(0x22) - -#define GTCCR _SFR_IO8(0x23) -#define PSRSYNC 0 -#define TSM 7 -#define PSRASY 1 - -#define TCCR0A _SFR_IO8(0x24) -#define WGM00 0 -#define WGM01 1 -#define COM0B0 4 -#define COM0B1 5 -#define COM0A0 6 -#define COM0A1 7 - -#define TCCR0B _SFR_IO8(0x25) -#define CS00 0 -#define CS01 1 -#define CS02 2 -#define WGM02 3 -#define FOC0B 6 -#define FOC0A 7 - -#define TCNT0 _SFR_IO8(0x26) - -#define OCR0A _SFR_IO8(0x27) - -#define OCR0B _SFR_IO8(0x28) - -/* Reserved [0x29] */ - -#define GPIOR1 _SFR_IO8(0x2A) -#define GPIOR10 0 -#define GPIOR11 1 -#define GPIOR12 2 -#define GPIOR13 3 -#define GPIOR14 4 -#define GPIOR15 5 -#define GPIOR16 6 -#define GPIOR17 7 - -#define GPIOR2 _SFR_IO8(0x2B) -#define GPIOR20 0 -#define GPIOR21 1 -#define GPIOR22 2 -#define GPIOR23 3 -#define GPIOR24 4 -#define GPIOR25 5 -#define GPIOR26 6 -#define GPIOR27 7 - -#define SPCR _SFR_IO8(0x2C) -#define SPR0 0 -#define SPR1 1 -#define CPHA 2 -#define CPOL 3 -#define MSTR 4 -#define DORD 5 -#define SPE 6 -#define SPIE 7 - -#define SPSR _SFR_IO8(0x2D) -#define SPI2X 0 -#define WCOL 6 -#define SPIF 7 - -#define SPDR _SFR_IO8(0x2E) - -/* Reserved [0x2F] */ - -#define ACSR _SFR_IO8(0x30) -#define ACIS0 0 -#define ACIS1 1 -#define ACIC 2 -#define ACIE 3 -#define ACI 4 -#define ACO 5 -#define ACBG 6 -#define ACD 7 - -#define OCDR _SFR_IO8(0x31) -#define OCDR7 7 -#define OCDR6 6 -#define OCDR5 5 -#define OCDR4 4 -#define OCDR3 3 -#define OCDR2 2 -#define OCDR1 1 -#define OCDR0 0 - -/* Reserved [0x32] */ - -#define SMCR _SFR_IO8(0x33) -#define SE 0 -#define SM0 1 -#define SM1 2 -#define SM2 3 - -#define MCUSR _SFR_IO8(0x34) -#define JTRF 4 -#define PORF 0 -#define EXTRF 1 -#define BORF 2 -#define WDRF 3 - -#define MCUCR _SFR_IO8(0x35) -#define JTD 7 -#define IVCE 0 -#define IVSEL 1 -#define PUD 4 - -/* Reserved [0x36] */ - -#define SPMCSR _SFR_IO8(0x37) -#define SPMEN 0 -#define PGERS 1 -#define PGWRT 2 -#define BLBSET 3 -#define RWWSRE 4 -#define SIGRD 5 -#define RWWSB 6 -#define SPMIE 7 - -/* Reserved [0x38..0x3A] */ - -#define RAMPZ _SFR_IO8(0x3B) - -/* Reserved [0x3C] */ - -/* SP [0x3D..0x3E] */ - -/* SREG [0x3F] */ - -#define WDTCSR _SFR_MEM8(0x60) -#define WDE 3 -#define WDCE 4 -#define WDP0 0 -#define WDP1 1 -#define WDP2 2 -#define WDP3 5 -#define WDIE 6 -#define WDIF 7 - -#define CLKPR _SFR_MEM8(0x61) -#define CLKPS0 0 -#define CLKPS1 1 -#define CLKPS2 2 -#define CLKPS3 3 -#define CLKPCE 7 - -/* Reserved [0x62..0x63] */ - -#define PRR0 _SFR_MEM8(0x64) -#define PRADC 0 -#define PRSPI 2 -#define PRTIM1 3 -#define PRUSART0 1 -#define PRUSART1 4 -#define PRTIM0 5 -#define PRTIM2 6 -#define PRTWI 7 - -#define __AVR_HAVE_PRR0 ((1<, never directly. */ - -#ifndef _AVR_IO_H_ -# error "Include instead of this file." -#endif - -#ifndef _AVR_IOXXX_H_ -# define _AVR_IOXXX_H_ "iom1284p.h" -#else -# error "Attempt to include more than one file." -#endif - - -#ifndef _AVR_IOM1284P_H_ -#define _AVR_IOM1284P_H_ 1 - - -/* Registers and associated bit numbers */ - -#define PINA _SFR_IO8(0x00) -#define PINA0 0 -#define PINA1 1 -#define PINA2 2 -#define PINA3 3 -#define PINA4 4 -#define PINA5 5 -#define PINA6 6 -#define PINA7 7 - -#define DDRA _SFR_IO8(0x01) -#define DDA0 0 -#define DDA1 1 -#define DDA2 2 -#define DDA3 3 -#define DDA4 4 -#define DDA5 5 -#define DDA6 6 -#define DDA7 7 - -#define PORTA _SFR_IO8(0x02) -#define PORTA0 0 -#define PORTA1 1 -#define PORTA2 2 -#define PORTA3 3 -#define PORTA4 4 -#define PORTA5 5 -#define PORTA6 6 -#define PORTA7 7 - -#define PINB _SFR_IO8(0x03) -#define PINB0 0 -#define PINB1 1 -#define PINB2 2 -#define PINB3 3 -#define PINB4 4 -#define PINB5 5 -#define PINB6 6 -#define PINB7 7 - -#define DDRB _SFR_IO8(0x04) -#define DDB0 0 -#define DDB1 1 -#define DDB2 2 -#define DDB3 3 -#define DDB4 4 -#define DDB5 5 -#define DDB6 6 -#define DDB7 7 - -#define PORTB _SFR_IO8(0x05) -#define PORTB0 0 -#define PORTB1 1 -#define PORTB2 2 -#define PORTB3 3 -#define PORTB4 4 -#define PORTB5 5 -#define PORTB6 6 -#define PORTB7 7 - -#define PINC _SFR_IO8(0x06) -#define PINC0 0 -#define PINC1 1 -#define PINC2 2 -#define PINC3 3 -#define PINC4 4 -#define PINC5 5 -#define PINC6 6 -#define PINC7 7 - -#define DDRC _SFR_IO8(0x07) -#define DDC0 0 -#define DDC1 1 -#define DDC2 2 -#define DDC3 3 -#define DDC4 4 -#define DDC5 5 -#define DDC6 6 -#define DDC7 7 - -#define PORTC _SFR_IO8(0x08) -#define PORTC0 0 -#define PORTC1 1 -#define PORTC2 2 -#define PORTC3 3 -#define PORTC4 4 -#define PORTC5 5 -#define PORTC6 6 -#define PORTC7 7 - -#define PIND _SFR_IO8(0x09) -#define PIND0 0 -#define PIND1 1 -#define PIND2 2 -#define PIND3 3 -#define PIND4 4 -#define PIND5 5 -#define PIND6 6 -#define PIND7 7 - -#define DDRD _SFR_IO8(0x0A) -#define DDD0 0 -#define DDD1 1 -#define DDD2 2 -#define DDD3 3 -#define DDD4 4 -#define DDD5 5 -#define DDD6 6 -#define DDD7 7 - -#define PORTD _SFR_IO8(0x0B) -#define PORTD0 0 -#define PORTD1 1 -#define PORTD2 2 -#define PORTD3 3 -#define PORTD4 4 -#define PORTD5 5 -#define PORTD6 6 -#define PORTD7 7 - -#define TIFR0 _SFR_IO8(0x15) -#define TOV0 0 -#define OCF0A 1 -#define OCF0B 2 - -#define TIFR1 _SFR_IO8(0x16) -#define TOV1 0 -#define OCF1A 1 -#define OCF1B 2 -#define ICF1 5 - -#define TIFR2 _SFR_IO8(0x17) -#define TOV2 0 -#define OCF2A 1 -#define OCF2B 2 - -#define TIFR3 _SFR_IO8(0x18) -#define TOV3 0 -#define OCF3A 1 -#define OCF3B 2 -#define ICF3 5 - -#define PCIFR _SFR_IO8(0x1B) -#define PCIF0 0 -#define PCIF1 1 -#define PCIF2 2 -#define PCIF3 3 - -#define EIFR _SFR_IO8(0x1C) -#define INTF0 0 -#define INTF1 1 -#define INTF2 2 - -#define EIMSK _SFR_IO8(0x1D) -#define INT0 0 -#define INT1 1 -#define INT2 2 - -#define GPIOR0 _SFR_IO8(0x1E) -#define GPIOR00 0 -#define GPIOR01 1 -#define GPIOR02 2 -#define GPIOR03 3 -#define GPIOR04 4 -#define GPIOR05 5 -#define GPIOR06 6 -#define GPIOR07 7 - -#define EECR _SFR_IO8(0x1F) -#define EERE 0 -#define EEPE 1 -#define EEMPE 2 -#define EERIE 3 -#define EEPM0 4 -#define EEPM1 5 - -#define EEDR _SFR_IO8(0x20) -#define EEDR0 0 -#define EEDR1 1 -#define EEDR2 2 -#define EEDR3 3 -#define EEDR4 4 -#define EEDR5 5 -#define EEDR6 6 -#define EEDR7 7 - -#define EEAR _SFR_IO16(0x21) - -#define EEARL _SFR_IO8(0x21) -#define EEAR0 0 -#define EEAR1 1 -#define EEAR2 2 -#define EEAR3 3 -#define EEAR4 4 -#define EEAR5 5 -#define EEAR6 6 -#define EEAR7 7 - -#define EEARH _SFR_IO8(0x22) -#define EEAR8 0 -#define EEAR9 1 -#define EEAR10 2 -#define EEAR11 3 - -#define GTCCR _SFR_IO8(0x23) -#define PSRSYNC 0 -#define PSRASY 1 -#define TSM 7 - -#define TCCR0A _SFR_IO8(0x24) -#define WGM00 0 -#define WGM01 1 -#define COM0B0 4 -#define COM0B1 5 -#define COM0A0 6 -#define COM0A1 7 - -#define TCCR0B _SFR_IO8(0x25) -#define CS00 0 -#define CS01 1 -#define CS02 2 -#define WGM02 3 -#define FOC0B 6 -#define FOC0A 7 - -#define TCNT0 _SFR_IO8(0x26) -#define TCNT0_0 0 -#define TCNT0_1 1 -#define TCNT0_2 2 -#define TCNT0_3 3 -#define TCNT0_4 4 -#define TCNT0_5 5 -#define TCNT0_6 6 -#define TCNT0_7 7 - -#define OCR0A _SFR_IO8(0x27) -#define OCR0A_0 0 -#define OCR0A_1 1 -#define OCR0A_2 2 -#define OCR0A_3 3 -#define OCR0A_4 4 -#define OCR0A_5 5 -#define OCR0A_6 6 -#define OCR0A_7 7 - -#define OCR0B _SFR_IO8(0x28) -#define OCR0B_0 0 -#define OCR0B_1 1 -#define OCR0B_2 2 -#define OCR0B_3 3 -#define OCR0B_4 4 -#define OCR0B_5 5 -#define OCR0B_6 6 -#define OCR0B_7 7 - -#define GPIOR1 _SFR_IO8(0x2A) -#define GPIOR10 0 -#define GPIOR11 1 -#define GPIOR12 2 -#define GPIOR13 3 -#define GPIOR14 4 -#define GPIOR15 5 -#define GPIOR16 6 -#define GPIOR17 7 - -#define GPIOR2 _SFR_IO8(0x2B) -#define GPIOR20 0 -#define GPIOR21 1 -#define GPIOR22 2 -#define GPIOR23 3 -#define GPIOR24 4 -#define GPIOR25 5 -#define GPIOR26 6 -#define GPIOR27 7 - -#define SPCR _SFR_IO8(0x2C) -#define SPR0 0 -#define SPR1 1 -#define CPHA 2 -#define CPOL 3 -#define MSTR 4 -#define DORD 5 -#define SPE 6 -#define SPIE 7 - -#define SPSR _SFR_IO8(0x2D) -#define SPI2X 0 -#define WCOL 6 -#define SPIF 7 - -#define SPDR _SFR_IO8(0x2E) -#define SPDR0 0 -#define SPDR1 1 -#define SPDR2 2 -#define SPDR3 3 -#define SPDR4 4 -#define SPDR5 5 -#define SPDR6 6 -#define SPDR7 7 - -#define ACSR _SFR_IO8(0x30) -#define ACIS0 0 -#define ACIS1 1 -#define ACIC 2 -#define ACIE 3 -#define ACI 4 -#define ACO 5 -#define ACBG 6 -#define ACD 7 - -#define OCDR _SFR_IO8(0x31) -#define OCDR0 0 -#define OCDR1 1 -#define OCDR2 2 -#define OCDR3 3 -#define OCDR4 4 -#define OCDR5 5 -#define OCDR6 6 -#define OCDR7 7 - -#define SMCR _SFR_IO8(0x33) -#define SE 0 -#define SM0 1 -#define SM1 2 -#define SM2 3 - -#define MCUSR _SFR_IO8(0x34) -#define PORF 0 -#define EXTRF 1 -#define BORF 2 -#define WDRF 3 -#define JTRF 4 - -#define MCUCR _SFR_IO8(0x35) -#define IVCE 0 -#define IVSEL 1 -#define PUD 4 -#define BODSE 5 -#define BODS 6 -#define JTD 7 - -#define SPMCSR _SFR_IO8(0x37) -#define SPMEN 0 -#define PGERS 1 -#define PGWRT 2 -#define BLBSET 3 -#define RWWSRE 4 -#define SIGRD 5 -#define RWWSB 6 -#define SPMIE 7 - -#define RAMPZ _SFR_IO8(0x3B) -#define RAMPZ0 0 - -#define WDTCSR _SFR_MEM8(0x60) -#define WDP0 0 -#define WDP1 1 -#define WDP2 2 -#define WDE 3 -#define WDCE 4 -#define WDP3 5 -#define WDIE 6 -#define WDIF 7 - -#define CLKPR _SFR_MEM8(0x61) -#define CLKPS0 0 -#define CLKPS1 1 -#define CLKPS2 2 -#define CLKPS3 3 -#define CLKPCE 7 - -#define PRR0 _SFR_MEM8(0x64) -#define PRADC 0 -#define PRUSART0 1 -#define PRSPI 2 -#define PRTIM1 3 -#define PRUSART1 4 -#define PRTIM0 5 -#define PRTIM2 6 -#define PRTWI 7 - -#define __AVR_HAVE_PRR0 ((1< instead of this file." -#endif - -#ifndef _AVR_IOXXX_H_ -# define _AVR_IOXXX_H_ "iom1284rfr2.h" -#else -# error "Attempt to include more than one file." -#endif - -/* Registers and associated bit numbers */ - -#define PINA _SFR_IO8(0x00) -#define PINA7 7 -#define PINA6 6 -#define PINA5 5 -#define PINA4 4 -#define PINA3 3 -#define PINA2 2 -#define PINA1 1 -#define PINA0 0 - -#define DDRA _SFR_IO8(0x01) -#define DDRA7 7 -// Inserted "DDA7" from "DDRA7" due to compatibility -#define DDA7 7 -#define DDRA6 6 -// Inserted "DDA6" from "DDRA6" due to compatibility -#define DDA6 6 -#define DDRA5 5 -// Inserted "DDA5" from "DDRA5" due to compatibility -#define DDA5 5 -#define DDRA4 4 -// Inserted "DDA4" from "DDRA4" due to compatibility -#define DDA4 4 -#define DDRA3 3 -// Inserted "DDA3" from "DDRA3" due to compatibility -#define DDA3 3 -#define DDRA2 2 -// Inserted "DDA2" from "DDRA2" due to compatibility -#define DDA2 2 -#define DDRA1 1 -// Inserted "DDA1" from "DDRA1" due to compatibility -#define DDA1 1 -#define DDRA0 0 -// Inserted "DDA0" from "DDRA0" due to compatibility -#define DDA0 0 - -#define PORTA _SFR_IO8(0x02) -#define PORTA7 7 -#define PORTA6 6 -#define PORTA5 5 -#define PORTA4 4 -#define PORTA3 3 -#define PORTA2 2 -#define PORTA1 1 -#define PORTA0 0 - -#define PINB _SFR_IO8(0x03) -#define PINB7 7 -#define PINB6 6 -#define PINB5 5 -#define PINB4 4 -#define PINB3 3 -#define PINB2 2 -#define PINB1 1 -#define PINB0 0 - -#define DDRB _SFR_IO8(0x04) -#define DDRB7 7 -// Inserted "DDB7" from "DDRB7" due to compatibility -#define DDB7 7 -#define DDRB6 6 -// Inserted "DDB6" from "DDRB6" due to compatibility -#define DDB6 6 -#define DDRB5 5 -// Inserted "DDB5" from "DDRB5" due to compatibility -#define DDB5 5 -#define DDRB4 4 -// Inserted "DDB4" from "DDRB4" due to compatibility -#define DDB4 4 -#define DDRB3 3 -// Inserted "DDB3" from "DDRB3" due to compatibility -#define DDB3 3 -#define DDRB2 2 -// Inserted "DDB2" from "DDRB2" due to compatibility -#define DDB2 2 -#define DDRB1 1 -// Inserted "DDB1" from "DDRB1" due to compatibility -#define DDB1 1 -#define DDRB0 0 -// Inserted "DDB0" from "DDRB0" due to compatibility -#define DDB0 0 - -#define PORTB _SFR_IO8(0x05) -#define PORTB7 7 -#define PORTB6 6 -#define PORTB5 5 -#define PORTB4 4 -#define PORTB3 3 -#define PORTB2 2 -#define PORTB1 1 -#define PORTB0 0 - -#define PINC _SFR_IO8(0x06) -#define PINC7 7 -#define PINC6 6 -#define PINC5 5 -#define PINC4 4 -#define PINC3 3 -#define PINC2 2 -#define PINC1 1 -#define PINC0 0 - -#define DDRC _SFR_IO8(0x07) -#define DDRC7 7 -// Inserted "DDC7" from "DDRC7" due to compatibility -#define DDC7 7 -#define DDRC6 6 -// Inserted "DDC6" from "DDRC6" due to compatibility -#define DDC6 6 -#define DDRC5 5 -// Inserted "DDC5" from "DDRC5" due to compatibility -#define DDC5 5 -#define DDRC4 4 -// Inserted "DDC4" from "DDRC4" due to compatibility -#define DDC4 4 -#define DDRC3 3 -// Inserted "DDC3" from "DDRC3" due to compatibility -#define DDC3 3 -#define DDRC2 2 -// Inserted "DDC2" from "DDRC2" due to compatibility -#define DDC2 2 -#define DDRC1 1 -// Inserted "DDC1" from "DDRC1" due to compatibility -#define DDC1 1 -#define DDRC0 0 -// Inserted "DDC0" from "DDRC0" due to compatibility -#define DDC0 0 - -#define PORTC _SFR_IO8(0x08) -#define PORTC7 7 -#define PORTC6 6 -#define PORTC5 5 -#define PORTC4 4 -#define PORTC3 3 -#define PORTC2 2 -#define PORTC1 1 -#define PORTC0 0 - -#define PIND _SFR_IO8(0x09) -#define PIND7 7 -#define PIND6 6 -#define PIND5 5 -#define PIND4 4 -#define PIND3 3 -#define PIND2 2 -#define PIND1 1 -#define PIND0 0 - -#define DDRD _SFR_IO8(0x0A) -#define DDRD7 7 -// Inserted "DDD7" from "DDRD7" due to compatibility -#define DDD7 7 -#define DDRD6 6 -// Inserted "DDD6" from "DDRD6" due to compatibility -#define DDD6 6 -#define DDRD5 5 -// Inserted "DDD5" from "DDRD5" due to compatibility -#define DDD5 5 -#define DDRD4 4 -// Inserted "DDD4" from "DDRD4" due to compatibility -#define DDD4 4 -#define DDRD3 3 -// Inserted "DDD3" from "DDRD3" due to compatibility -#define DDD3 3 -#define DDRD2 2 -// Inserted "DDD2" from "DDRD2" due to compatibility -#define DDD2 2 -#define DDRD1 1 -// Inserted "DDD1" from "DDRD1" due to compatibility -#define DDD1 1 -#define DDRD0 0 -// Inserted "DDD0" from "DDRD0" due to compatibility -#define DDD0 0 - -#define PORTD _SFR_IO8(0x0B) -#define PORTD7 7 -#define PORTD6 6 -#define PORTD5 5 -#define PORTD4 4 -#define PORTD3 3 -#define PORTD2 2 -#define PORTD1 1 -#define PORTD0 0 - -#define PINE _SFR_IO8(0x0C) -#define PINE7 7 -#define PINE6 6 -#define PINE5 5 -#define PINE4 4 -#define PINE3 3 -#define PINE2 2 -#define PINE1 1 -#define PINE0 0 - -#define DDRE _SFR_IO8(0x0D) -#define DDRE7 7 -// Inserted "DDE7" from "DDRE7" due to compatibility -#define DDE7 7 -#define DDRE6 6 -// Inserted "DDE6" from "DDRE6" due to compatibility -#define DDE6 6 -#define DDRE5 5 -// Inserted "DDE5" from "DDRE5" due to compatibility -#define DDE5 5 -#define DDRE4 4 -// Inserted "DDE4" from "DDRE4" due to compatibility -#define DDE4 4 -#define DDRE3 3 -// Inserted "DDE3" from "DDRE3" due to compatibility -#define DDE3 3 -#define DDRE2 2 -// Inserted "DDE2" from "DDRE2" due to compatibility -#define DDE2 2 -#define DDRE1 1 -// Inserted "DDE1" from "DDRE1" due to compatibility -#define DDE1 1 -#define DDRE0 0 -// Inserted "DDE0" from "DDRE0" due to compatibility -#define DDE0 0 - -#define PORTE _SFR_IO8(0x0E) -#define PORTE7 7 -#define PORTE6 6 -#define PORTE5 5 -#define PORTE4 4 -#define PORTE3 3 -#define PORTE2 2 -#define PORTE1 1 -#define PORTE0 0 - -#define PINF _SFR_IO8(0x0F) -#define PINF7 7 -#define PINF6 6 -#define PINF5 5 -#define PINF4 4 -#define PINF3 3 -#define PINF2 2 -#define PINF1 1 -#define PINF0 0 - -#define DDRF _SFR_IO8(0x10) -#define DDRF7 7 -// Inserted "DDF7" from "DDRF7" due to compatibility -#define DDF7 7 -#define DDRF6 6 -// Inserted "DDF6" from "DDRF6" due to compatibility -#define DDF6 6 -#define DDRF5 5 -// Inserted "DDF5" from "DDRF5" due to compatibility -#define DDF5 5 -#define DDRF4 4 -// Inserted "DDF4" from "DDRF4" due to compatibility -#define DDF4 4 -#define DDRF3 3 -// Inserted "DDF3" from "DDRF3" due to compatibility -#define DDF3 3 -#define DDRF2 2 -// Inserted "DDF2" from "DDRF2" due to compatibility -#define DDF2 2 -#define DDRF1 1 -// Inserted "DDF1" from "DDRF1" due to compatibility -#define DDF1 1 -#define DDRF0 0 -// Inserted "DDF0" from "DDRF0" due to compatibility -#define DDF0 0 - -#define PORTF _SFR_IO8(0x11) -#define PORTF7 7 -#define PORTF6 6 -#define PORTF5 5 -#define PORTF4 4 -#define PORTF3 3 -#define PORTF2 2 -#define PORTF1 1 -#define PORTF0 0 - -#define PING _SFR_IO8(0x12) -#define PING7 7 -#define PING6 6 -#define PING5 5 -#define PING4 4 -#define PING3 3 -#define PING2 2 -#define PING1 1 -#define PING0 0 - -#define DDRG _SFR_IO8(0x13) -#define DDRG7 7 -// Inserted "DDG7" from "DDRG7" due to compatibility -#define DDG7 7 -#define DDRG6 6 -// Inserted "DDG6" from "DDRG6" due to compatibility -#define DDG6 6 -#define DDRG5 5 -// Inserted "DDG5" from "DDRG5" due to compatibility -#define DDG5 5 -#define DDRG4 4 -// Inserted "DDG4" from "DDRG4" due to compatibility -#define DDG4 4 -#define DDRG3 3 -// Inserted "DDG3" from "DDRG3" due to compatibility -#define DDG3 3 -#define DDRG2 2 -// Inserted "DDG2" from "DDRG2" due to compatibility -#define DDG2 2 -#define DDRG1 1 -// Inserted "DDG1" from "DDRG1" due to compatibility -#define DDG1 1 -#define DDRG0 0 -// Inserted "DDG0" from "DDRG0" due to compatibility -#define DDG0 0 - -#define PORTG _SFR_IO8(0x14) -#define PORTG7 7 -#define PORTG6 6 -#define PORTG5 5 -#define PORTG4 4 -#define PORTG3 3 -#define PORTG2 2 -#define PORTG1 1 -#define PORTG0 0 - -#define TIFR0 _SFR_IO8(0x15) -#define TOV0 0 -#define OCF0A 1 -#define OCF0B 2 -#define Res0 3 -#define Res1 4 -#define Res2 5 -#define Res3 6 -#define Res4 7 - -#define TIFR1 _SFR_IO8(0x16) -#define TOV1 0 -#define OCF1A 1 -#define OCF1B 2 -#define OCF1C 3 -#define ICF1 5 - -#define TIFR2 _SFR_IO8(0x17) -#define TOV2 0 -#define OCF2A 1 -#define OCF2B 2 - -#define TIFR3 _SFR_IO8(0x18) -#define TOV3 0 -#define OCF3A 1 -#define OCF3B 2 -#define OCF3C 3 -#define ICF3 5 - -#define TIFR4 _SFR_IO8(0x19) -#define TOV4 0 -#define OCF4A 1 -#define OCF4B 2 -#define OCF4C 3 -#define ICF4 5 - -#define TIFR5 _SFR_IO8(0x1A) -#define TOV5 0 -#define OCF5A 1 -#define OCF5B 2 -#define OCF5C 3 -#define ICF5 5 - -#define PCIFR _SFR_IO8(0x1B) -#define PCIF0 0 -#define PCIF1 1 -#define PCIF2 2 - -#define EIFR _SFR_IO8(0x1C) -#define INTF0 0 -#define INTF1 1 -#define INTF2 2 -#define INTF3 3 -#define INTF4 4 -#define INTF5 5 -#define INTF6 6 -#define INTF7 7 - -#define EIMSK _SFR_IO8(0x1D) -#define INT0 0 -#define INT1 1 -#define INT2 2 -#define INT3 3 -#define INT4 4 -#define INT5 5 -#define INT6 6 -#define INT7 7 - -#define GPIOR0 _SFR_IO8(0x1E) -#define GPIOR00 0 -#define GPIOR01 1 -#define GPIOR02 2 -#define GPIOR03 3 -#define GPIOR04 4 -#define GPIOR05 5 -#define GPIOR06 6 -#define GPIOR07 7 - -#define EECR _SFR_IO8(0x1F) -#define EERE 0 -#define EEPE 1 -#define EEMPE 2 -#define EERIE 3 -#define EEPM0 4 -#define EEPM1 5 - -#define EEDR _SFR_IO8(0x20) - -/* Combine EEARL and EEARH */ -#define EEAR _SFR_IO16(0x21) - -#define EEARL _SFR_IO8(0x21) -#define EEARH _SFR_IO8(0x22) - -#define GTCCR _SFR_IO8(0x23) -#define PSRSYNC 0 -#define PSRASY 1 -#define TSM 7 - -#define TCCR0A _SFR_IO8(0x24) -#define WGM00 0 -#define WGM01 1 -#define COM0B0 4 -#define COM0B1 5 -#define COM0A0 6 -#define COM0A1 7 - -#define TCCR0B _SFR_IO8(0x25) -#define CS00 0 -#define CS01 1 -#define CS02 2 -#define WGM02 3 -#define FOC0B 6 -#define FOC0A 7 - -#define TCNT0 _SFR_IO8(0x26) - -#define OCR0A _SFR_IO8(0x27) - -#define OCR0B _SFR_IO8(0x28) - -/* Reserved [0x29] */ - -#define GPIOR1 _SFR_IO8(0x2A) -#define GPIOR10 0 -#define GPIOR11 1 -#define GPIOR12 2 -#define GPIOR13 3 -#define GPIOR14 4 -#define GPIOR15 5 -#define GPIOR16 6 -#define GPIOR17 7 - -#define GPIOR2 _SFR_IO8(0x2B) -#define GPIOR20 0 -#define GPIOR21 1 -#define GPIOR22 2 -#define GPIOR23 3 -#define GPIOR24 4 -#define GPIOR25 5 -#define GPIOR26 6 -#define GPIOR27 7 - -#define SPCR _SFR_IO8(0x2C) -#define SPR0 0 -#define SPR1 1 -#define CPHA 2 -#define CPOL 3 -#define MSTR 4 -#define DORD 5 -#define SPE 6 -#define SPIE 7 - -#define SPSR _SFR_IO8(0x2D) -#define SPI2X 0 -#define WCOL 6 -#define SPIF 7 - -#define SPDR _SFR_IO8(0x2E) - -/* Reserved [0x2F] */ - -#define ACSR _SFR_IO8(0x30) -#define ACIS0 0 -#define ACIS1 1 -#define ACIC 2 -#define ACIE 3 -#define ACI 4 -#define ACO 5 -#define ACBG 6 -#define ACD 7 - -#define OCDR _SFR_IO8(0x31) -#define OCDR0 0 -#define OCDR1 1 -#define OCDR2 2 -#define OCDR3 3 -#define OCDR4 4 -#define OCDR5 5 -#define OCDR6 6 -#define OCDR7 7 - -/* Reserved [0x32] */ - -#define SMCR _SFR_IO8(0x33) -#define SE 0 -#define SM0 1 -#define SM1 2 -#define SM2 3 - -#define MCUSR _SFR_IO8(0x34) -#define JTRF 4 -#define PORF 0 -#define EXTRF 1 -#define BORF 2 -#define WDRF 3 - -#define MCUCR _SFR_IO8(0x35) -#define JTD 7 -#define IVCE 0 -#define IVSEL 1 -#define PUD 4 - -/* Reserved [0x36] */ - -#define SPMCSR _SFR_IO8(0x37) -#define SPMEN 0 -#define PGERS 1 -#define PGWRT 2 -#define BLBSET 3 -#define RWWSRE 4 -#define SIGRD 5 -#define RWWSB 6 -#define SPMIE 7 - -/* Reserved [0x38..0x3A] */ - -#define RAMPZ _SFR_IO8(0x3B) -#define RAMPZ0 0 -#define Res5 6 -#define Res6 7 - -/* Reserved [0x3C] */ - -/* SP [0x3D..0x3E] */ - -/* SREG [0x3F] */ - -#define WDTCSR _SFR_MEM8(0x60) -#define WDE 3 -#define WDCE 4 -#define WDP0 0 -#define WDP1 1 -#define WDP2 2 -#define WDP3 5 -#define WDIE 6 -#define WDIF 7 - -#define CLKPR _SFR_MEM8(0x61) -#define CLKPS0 0 -#define CLKPS1 1 -#define CLKPS2 2 -#define CLKPS3 3 -#define CLKPCE 7 - -/* Reserved [0x62] */ - -#define PRR2 _SFR_MEM8(0x63) -#define PRRAM0 0 -#define PRRAM1 1 -#define PRRAM2 2 -#define PRRAM3 3 - -#define __AVR_HAVE_PRR2 ((1< instead of this file." -#endif - -#ifndef _AVR_IOXXX_H_ -# define _AVR_IOXXX_H_ "iom128a.h" -#else -# error "Attempt to include more than one file." -#endif - -/* Registers and associated bit numbers */ - -#define PINF _SFR_IO8(0x00) -#define PINF7 7 -#define PINF6 6 -#define PINF5 5 -#define PINF4 4 -#define PINF3 3 -#define PINF2 2 -#define PINF1 1 -#define PINF0 0 - -#define PINE _SFR_IO8(0x01) -#define PINE7 7 -#define PINE6 6 -#define PINE5 5 -#define PINE4 4 -#define PINE3 3 -#define PINE2 2 -#define PINE1 1 -#define PINE0 0 - -#define DDRE _SFR_IO8(0x02) -#define DDRE7 7 -// Inserted "DDE7" from "DDRE7" due to compatibility -#define DDE7 7 -#define DDRE6 6 -// Inserted "DDE6" from "DDRE6" due to compatibility -#define DDE6 6 -#define DDRE5 5 -// Inserted "DDE5" from "DDRE5" due to compatibility -#define DDE5 5 -#define DDRE4 4 -// Inserted "DDE4" from "DDRE4" due to compatibility -#define DDE4 4 -#define DDRE3 3 -// Inserted "DDE3" from "DDRE3" due to compatibility -#define DDE3 3 -#define DDRE2 2 -// Inserted "DDE2" from "DDRE2" due to compatibility -#define DDE2 2 -#define DDRE1 1 -// Inserted "DDE1" from "DDRE1" due to compatibility -#define DDE1 1 -#define DDRE0 0 -// Inserted "DDE0" from "DDRE0" due to compatibility -#define DDE0 0 - -#define PORTE _SFR_IO8(0x03) -#define PORTE7 7 -#define PORTE6 6 -#define PORTE5 5 -#define PORTE4 4 -#define PORTE3 3 -#define PORTE2 2 -#define PORTE1 1 -#define PORTE0 0 - -/* Combine ADCL and ADCH */ -#ifndef __ASSEMBLER__ -#define ADC _SFR_IO16(0x04) -#endif -#define ADCW _SFR_IO16(0x04) - -#define ADCL _SFR_IO8(0x04) -#define ADCH _SFR_IO8(0x05) - -#define ADCSRA _SFR_IO8(0x06) -#define ADPS0 0 -#define ADPS1 1 -#define ADPS2 2 -#define ADIE 3 -#define ADIF 4 -#define ADFR 5 -#define ADSC 6 -#define ADEN 7 - -#define ADMUX _SFR_IO8(0x07) -#define MUX0 0 -#define MUX1 1 -#define MUX2 2 -#define MUX3 3 -#define MUX4 4 -#define ADLAR 5 -#define REFS0 6 -#define REFS1 7 - -#define ACSR _SFR_IO8(0x08) -#define ACIS0 0 -#define ACIS1 1 -#define ACIC 2 -#define ACIE 3 -#define ACI 4 -#define ACO 5 -#define ACBG 6 -#define ACD 7 - -#define UBRR0L _SFR_IO8(0x09) - -#define UCSR0B _SFR_IO8(0x0A) -#define TXB80 0 -#define RXB80 1 -#define UCSZ02 2 -#define TXEN0 3 -#define RXEN0 4 -#define UDRIE0 5 -#define TXCIE0 6 -#define RXCIE0 7 - -#define UCSR0A _SFR_IO8(0x0B) -#define MPCM0 0 -#define U2X0 1 -#define UPE0 2 -#define DOR0 3 -#define FE0 4 -#define UDRE0 5 -#define TXC0 6 -#define RXC0 7 - -#define UDR0 _SFR_IO8(0x0C) - -#define SPCR _SFR_IO8(0x0D) -#define SPR0 0 -#define SPR1 1 -#define CPHA 2 -#define CPOL 3 -#define MSTR 4 -#define DORD 5 -#define SPE 6 -#define SPIE 7 - -#define SPSR _SFR_IO8(0x0E) -#define SPI2X 0 -#define WCOL 6 -#define SPIF 7 - -#define SPDR _SFR_IO8(0x0F) - -#define PIND _SFR_IO8(0x10) -#define PIND7 7 -#define PIND6 6 -#define PIND5 5 -#define PIND4 4 -#define PIND3 3 -#define PIND2 2 -#define PIND1 1 -#define PIND0 0 - -#define DDRD _SFR_IO8(0x11) -#define DDRD7 7 -// Inserted "DDD7" from "DDRD7" due to compatibility -#define DDD7 7 -#define DDRD6 6 -// Inserted "DDD6" from "DDRD6" due to compatibility -#define DDD6 6 -#define DDRD5 5 -// Inserted "DDD5" from "DDRD5" due to compatibility -#define DDD5 5 -#define DDRD4 4 -// Inserted "DDD4" from "DDRD4" due to compatibility -#define DDD4 4 -#define DDRD3 3 -// Inserted "DDD3" from "DDRD3" due to compatibility -#define DDD3 3 -#define DDRD2 2 -// Inserted "DDD2" from "DDRD2" due to compatibility -#define DDD2 2 -#define DDRD1 1 -// Inserted "DDD1" from "DDRD1" due to compatibility -#define DDD1 1 -#define DDRD0 0 -// Inserted "DDD0" from "DDRD0" due to compatibility -#define DDD0 0 - -#define PORTD _SFR_IO8(0x12) -#define PORTD7 7 -#define PORTD6 6 -#define PORTD5 5 -#define PORTD4 4 -#define PORTD3 3 -#define PORTD2 2 -#define PORTD1 1 -#define PORTD0 0 - -#define PINC _SFR_IO8(0x13) -#define PINC7 7 -#define PINC6 6 -#define PINC5 5 -#define PINC4 4 -#define PINC3 3 -#define PINC2 2 -#define PINC1 1 -#define PINC0 0 - -#define DDRC _SFR_IO8(0x14) -#define DDRC7 7 -// Inserted "DDC7" from "DDRC7" due to compatibility -#define DDC7 7 -#define DDRC6 6 -// Inserted "DDC6" from "DDRC6" due to compatibility -#define DDC6 6 -#define DDRC5 5 -// Inserted "DDC5" from "DDRC5" due to compatibility -#define DDC5 5 -#define DDRC4 4 -// Inserted "DDC4" from "DDRC4" due to compatibility -#define DDC4 4 -#define DDRC3 3 -// Inserted "DDC3" from "DDRC3" due to compatibility -#define DDC3 3 -#define DDRC2 2 -// Inserted "DDC2" from "DDRC2" due to compatibility -#define DDC2 2 -#define DDRC1 1 -// Inserted "DDC1" from "DDRC1" due to compatibility -#define DDC1 1 -#define DDRC0 0 -// Inserted "DDC0" from "DDRC0" due to compatibility -#define DDC0 0 - -#define PORTC _SFR_IO8(0x15) -#define PORTC7 7 -#define PORTC6 6 -#define PORTC5 5 -#define PORTC4 4 -#define PORTC3 3 -#define PORTC2 2 -#define PORTC1 1 -#define PORTC0 0 - -#define PINB _SFR_IO8(0x16) -#define PINB7 7 -#define PINB6 6 -#define PINB5 5 -#define PINB4 4 -#define PINB3 3 -#define PINB2 2 -#define PINB1 1 -#define PINB0 0 - -#define DDRB _SFR_IO8(0x17) -#define DDRB7 7 -// Inserted "DDB7" from "DDRB7" due to compatibility -#define DDB7 7 -#define DDRB6 6 -// Inserted "DDB6" from "DDRB6" due to compatibility -#define DDB6 6 -#define DDRB5 5 -// Inserted "DDB5" from "DDRB5" due to compatibility -#define DDB5 5 -#define DDRB4 4 -// Inserted "DDB4" from "DDRB4" due to compatibility -#define DDB4 4 -#define DDRB3 3 -// Inserted "DDB3" from "DDRB3" due to compatibility -#define DDB3 3 -#define DDRB2 2 -// Inserted "DDB2" from "DDRB2" due to compatibility -#define DDB2 2 -#define DDRB1 1 -// Inserted "DDB1" from "DDRB1" due to compatibility -#define DDB1 1 -#define DDRB0 0 -// Inserted "DDB0" from "DDRB0" due to compatibility -#define DDB0 0 - -#define PORTB _SFR_IO8(0x18) -#define PORTB7 7 -#define PORTB6 6 -#define PORTB5 5 -#define PORTB4 4 -#define PORTB3 3 -#define PORTB2 2 -#define PORTB1 1 -#define PORTB0 0 - -#define PINA _SFR_IO8(0x19) -#define PINA7 7 -#define PINA6 6 -#define PINA5 5 -#define PINA4 4 -#define PINA3 3 -#define PINA2 2 -#define PINA1 1 -#define PINA0 0 - -#define DDRA _SFR_IO8(0x1A) -#define DDRA7 7 -// Inserted "DDA7" from "DDRA7" due to compatibility -#define DDA7 7 -#define DDRA6 6 -// Inserted "DDA6" from "DDRA6" due to compatibility -#define DDA6 6 -#define DDRA5 5 -// Inserted "DDA5" from "DDRA5" due to compatibility -#define DDA5 5 -#define DDRA4 4 -// Inserted "DDA4" from "DDRA4" due to compatibility -#define DDA4 4 -#define DDRA3 3 -// Inserted "DDA3" from "DDRA3" due to compatibility -#define DDA3 3 -#define DDRA2 2 -// Inserted "DDA2" from "DDRA2" due to compatibility -#define DDA2 2 -#define DDRA1 1 -// Inserted "DDA1" from "DDRA1" due to compatibility -#define DDA1 1 -#define DDRA0 0 -// Inserted "DDA0" from "DDRA0" due to compatibility -#define DDA0 0 - -#define PORTA _SFR_IO8(0x1B) -#define PORTA7 7 -#define PORTA6 6 -#define PORTA5 5 -#define PORTA4 4 -#define PORTA3 3 -#define PORTA2 2 -#define PORTA1 1 -#define PORTA0 0 - -#define EECR _SFR_IO8(0x1C) -#define EERE 0 -#define EEWE 1 -#define EEMWE 2 -#define EERIE 3 - -#define EEDR _SFR_IO8(0x1D) - -/* Combine EEARL and EEARH */ -#define EEAR _SFR_IO16(0x1E) - -#define EEARL _SFR_IO8(0x1E) -#define EEARH _SFR_IO8(0x1F) - -#define SFIOR _SFR_IO8(0x20) -#define ACME 3 -#define PSR321 0 -#define PSR0 1 -#define PUD 2 -#define TSM 7 - -#define WDTCR _SFR_IO8(0x21) -#define WDP0 0 -#define WDP1 1 -#define WDP2 2 -#define WDE 3 -#define WDCE 4 - -#define OCDR _SFR_IO8(0x22) -#define OCDR0 0 -#define OCDR1 1 -#define OCDR2 2 -#define OCDR3 3 -#define OCDR4 4 -#define OCDR5 5 -#define OCDR6 6 -#define OCDR7 7 - -#define OCR2 _SFR_IO8(0x23) - -#define TCNT2 _SFR_IO8(0x24) - -#define TCCR2 _SFR_IO8(0x25) -#define CS20 0 -#define CS21 1 -#define CS22 2 -#define WGM21 3 -#define COM20 4 -#define COM21 5 -#define WGM20 6 -#define FOC2 7 - -/* Combine ICR1L and ICR1H */ -#define ICR1 _SFR_IO16(0x26) - -#define ICR1L _SFR_IO8(0x26) -#define ICR1H _SFR_IO8(0x27) - -/* Combine OCR1BL and OCR1BH */ -#define OCR1B _SFR_IO16(0x28) - -#define OCR1BL _SFR_IO8(0x28) -#define OCR1BH _SFR_IO8(0x29) - -/* Combine OCR1AL and OCR1AH */ -#define OCR1A _SFR_IO16(0x2A) - -#define OCR1AL _SFR_IO8(0x2A) -#define OCR1AH _SFR_IO8(0x2B) - -/* Combine TCNT1L and TCNT1H */ -#define TCNT1 _SFR_IO16(0x2C) - -#define TCNT1L _SFR_IO8(0x2C) -#define TCNT1H _SFR_IO8(0x2D) - -#define TCCR1B _SFR_IO8(0x2E) -#define CS10 0 -#define CS11 1 -#define CS12 2 -#define WGM12 3 -#define WGM13 4 -#define ICES1 6 -#define ICNC1 7 - -#define TCCR1A _SFR_IO8(0x2F) -#define WGM10 0 -#define WGM11 1 -#define COM1C0 2 -#define COM1C1 3 -#define COM1B0 4 -#define COM1B1 5 -#define COM1A0 6 -#define COM1A1 7 - -#define ASSR _SFR_IO8(0x30) -#define TCR0UB 0 -#define OCR0UB 1 -#define TCN0UB 2 -#define AS0 3 - -#define OCR0 _SFR_IO8(0x31) - -#define TCNT0 _SFR_IO8(0x32) - -#define TCCR0 _SFR_IO8(0x33) -#define CS00 0 -#define CS01 1 -#define CS02 2 -#define WGM01 3 -#define COM00 4 -#define COM01 5 -#define WGM00 6 -#define FOC0 7 - -#define MCUCSR _SFR_IO8(0x34) -#define PORF 0 -#define EXTRF 1 -#define BORF 2 -#define WDRF 3 -#define JTRF 4 -#define JTD 7 - -#define MCUCR _SFR_IO8(0x35) -#define IVCE 0 -#define IVSEL 1 -#define SM2 2 -#define SM0 3 -#define SM1 4 -#define SE 5 -#define SRW10 6 -#define SRE 7 - -#define TIFR _SFR_IO8(0x36) -#define TOV0 0 -#define OCF0 1 -#define TOV1 2 -#define OCF1B 3 -#define OCF1A 4 -#define ICF1 5 -#define TOV2 6 -#define OCF2 7 - -#define TIMSK _SFR_IO8(0x37) -#define TOIE0 0 -#define OCIE0 1 -#define TOIE1 2 -#define OCIE1B 3 -#define OCIE1A 4 -#define TICIE1 5 -#define TOIE2 6 -#define OCIE2 7 - -#define EIFR _SFR_IO8(0x38) -#define INTF0 0 -#define INTF1 1 -#define INTF2 2 -#define INTF3 3 -#define INTF4 4 -#define INTF5 5 -#define INTF6 6 -#define INTF7 7 - -#define EIMSK _SFR_IO8(0x39) -#define INT0 0 -#define INT1 1 -#define INT2 2 -#define INT3 3 -#define INT4 4 -#define INT5 5 -#define INT6 6 -#define INT7 7 - -#define EICRB _SFR_IO8(0x3A) -#define ISC40 0 -#define ISC41 1 -#define ISC50 2 -#define ISC51 3 -#define ISC60 4 -#define ISC61 5 -#define ISC70 6 -#define ISC71 7 - -#define RAMPZ _SFR_IO8(0x3B) -#define RAMPZ0 0 - -#define XDIV _SFR_IO8(0x3C) - -/* SP [0x3D..0x3E] */ - -/* SREG [0x3F] */ - -/* Reserved [0x40..0x60] */ - -#define DDRF _SFR_MEM8(0x61) -#define DDRF7 7 -// Inserted "DDF7" from "DDRF7" due to compatibility -#define DDF7 7 -#define DDRF6 6 -// Inserted "DDF6" from "DDRF6" due to compatibility -#define DDF6 6 -#define DDRF5 5 -// Inserted "DDF5" from "DDRF5" due to compatibility -#define DDF5 5 -#define DDRF4 4 -// Inserted "DDF4" from "DDRF4" due to compatibility -#define DDF4 4 -#define DDRF3 3 -// Inserted "DDF3" from "DDRF3" due to compatibility -#define DDF3 3 -#define DDRF2 2 -// Inserted "DDF2" from "DDRF2" due to compatibility -#define DDF2 2 -#define DDRF1 1 -// Inserted "DDF1" from "DDRF1" due to compatibility -#define DDF1 1 -#define DDRF0 0 -// Inserted "DDF0" from "DDRF0" due to compatibility -#define DDF0 0 - -#define PORTF _SFR_MEM8(0x62) -#define PORTF7 7 -#define PORTF6 6 -#define PORTF5 5 -#define PORTF4 4 -#define PORTF3 3 -#define PORTF2 2 -#define PORTF1 1 -#define PORTF0 0 - -#define PING _SFR_MEM8(0x63) -#define PING4 4 -#define PING3 3 -#define PING2 2 -#define PING1 1 -#define PING0 0 - -#define DDRG _SFR_MEM8(0x64) -#define DDRG4 4 -// Inserted "DDG4" from "DDRG4" due to compatibility -#define DDG4 4 -#define DDRG3 3 -// Inserted "DDG3" from "DDRG3" due to compatibility -#define DDG3 3 -#define DDRG2 2 -// Inserted "DDG2" from "DDRG2" due to compatibility -#define DDG2 2 -#define DDRG1 1 -// Inserted "DDG1" from "DDRG1" due to compatibility -#define DDG1 1 -#define DDRG0 0 -// Inserted "DDG0" from "DDRG0" due to compatibility -#define DDG0 0 - -#define PORTG _SFR_MEM8(0x65) -#define PORTG4 4 -#define PORTG3 3 -#define PORTG2 2 -#define PORTG1 1 -#define PORTG0 0 - -/* Reserved [0x66..0x67] */ - -#define SPMCSR _SFR_MEM8(0x68) -#define SPMEN 0 -#define PGERS 1 -#define PGWRT 2 -#define BLBSET 3 -#define RWWSRE 4 -#define RWWSB 6 -#define SPMIE 7 - -/* Reserved [0x69] */ - -#define EICRA _SFR_MEM8(0x6A) -#define ISC00 0 -#define ISC01 1 -#define ISC10 2 -#define ISC11 3 -#define ISC20 4 -#define ISC21 5 -#define ISC30 6 -#define ISC31 7 - -/* Reserved [0x6B] */ - -#define XMCRB _SFR_MEM8(0x6C) -#define XMM0 0 -#define XMM1 1 -#define XMM2 2 -#define XMBK 7 - -#define XMCRA _SFR_MEM8(0x6D) -#define SRW11 1 -#define SRW00 2 -#define SRW01 3 -#define SRL0 4 -#define SRL1 5 -#define SRL2 6 - -/* Reserved [0x6E] */ - -#define OSCCAL _SFR_MEM8(0x6F) -#define OSCCAL0 0 -#define OSCCAL1 1 -#define OSCCAL2 2 -#define OSCCAL3 3 -#define OSCCAL4 4 -#define OSCCAL5 5 -#define OSCCAL6 6 -#define OSCCAL7 7 - -#define TWBR _SFR_MEM8(0x70) - -#define TWSR _SFR_MEM8(0x71) -#define TWPS0 0 -#define TWPS1 1 -#define TWS3 3 -#define TWS4 4 -#define TWS5 5 -#define TWS6 6 -#define TWS7 7 - -#define TWAR _SFR_MEM8(0x72) -#define TWGCE 0 -#define TWA0 1 -#define TWA1 2 -#define TWA2 3 -#define TWA3 4 -#define TWA4 5 -#define TWA5 6 -#define TWA6 7 - -#define TWDR _SFR_MEM8(0x73) - -#define TWCR _SFR_MEM8(0x74) -#define TWIE 0 -#define TWEN 2 -#define TWWC 3 -#define TWSTO 4 -#define TWSTA 5 -#define TWEA 6 -#define TWINT 7 - -/* Reserved [0x75..0x77] */ - -/* Combine OCR1CL and OCR1CH */ -#define OCR1C _SFR_MEM16(0x78) - -#define OCR1CL _SFR_MEM8(0x78) -#define OCR1CH _SFR_MEM8(0x79) - -#define TCCR1C _SFR_MEM8(0x7A) -#define FOC1C 5 -#define FOC1B 6 -#define FOC1A 7 - -/* Reserved [0x7B] */ - -#define ETIFR _SFR_MEM8(0x7C) -#define OCF1C 0 -#define OCF3C 1 -#define TOV3 2 -#define OCF3B 3 -#define OCF3A 4 -#define ICF3 5 - -#define ETIMSK _SFR_MEM8(0x7D) -#define OCIE1C 0 -#define OCIE3C 1 -#define TOIE3 2 -#define OCIE3B 3 -#define OCIE3A 4 -#define TICIE3 5 - -/* Reserved [0x7E..0x7F] */ - -/* Combine ICR3L and ICR3H */ -#define ICR3 _SFR_MEM16(0x80) - -#define ICR3L _SFR_MEM8(0x80) -#define ICR3H _SFR_MEM8(0x81) - -/* Combine OCR3CL and OCR3CH */ -#define OCR3C _SFR_MEM16(0x82) - -#define OCR3CL _SFR_MEM8(0x82) -#define OCR3CH _SFR_MEM8(0x83) - -/* Combine OCR3BL and OCR3BH */ -#define OCR3B _SFR_MEM16(0x84) - -#define OCR3BL _SFR_MEM8(0x84) -#define OCR3BH _SFR_MEM8(0x85) - -/* Combine OCR3AL and OCR3AH */ -#define OCR3A _SFR_MEM16(0x86) - -#define OCR3AL _SFR_MEM8(0x86) -#define OCR3AH _SFR_MEM8(0x87) - -/* Combine TCNT3L and TCNT3H */ -#define TCNT3 _SFR_MEM16(0x88) - -#define TCNT3L _SFR_MEM8(0x88) -#define TCNT3H _SFR_MEM8(0x89) - -#define TCCR3B _SFR_MEM8(0x8A) -#define CS30 0 -#define CS31 1 -#define CS32 2 -#define WGM32 3 -#define WGM33 4 -#define ICES3 6 -#define ICNC3 7 - -#define TCCR3A _SFR_MEM8(0x8B) -#define WGM30 0 -#define WGM31 1 -#define COM3C0 2 -#define COM3C1 3 -#define COM3B0 4 -#define COM3B1 5 -#define COM3A0 6 -#define COM3A1 7 - -#define TCCR3C _SFR_MEM8(0x8C) -#define FOC3C 5 -#define FOC3B 6 -#define FOC3A 7 - -/* Reserved [0x8D..0x8F] */ - -#define UBRR0H _SFR_MEM8(0x90) - -/* Reserved [0x91..0x94] */ - -#define UCSR0C _SFR_MEM8(0x95) -#define UCPOL0 0 -#define UCSZ00 1 -#define UCSZ01 2 -#define USBS0 3 -#define UPM00 4 -#define UPM01 5 -#define UMSEL0 6 - -/* Reserved [0x96..0x97] */ - -#define UBRR1H _SFR_MEM8(0x98) - -#define UBRR1L _SFR_MEM8(0x99) - -#define UCSR1B _SFR_MEM8(0x9A) -#define TXB81 0 -#define RXB81 1 -#define UCSZ12 2 -#define TXEN1 3 -#define RXEN1 4 -#define UDRIE1 5 -#define TXCIE1 6 -#define RXCIE1 7 - -#define UCSR1A _SFR_MEM8(0x9B) -#define MPCM1 0 -#define U2X1 1 -#define UPE1 2 -#define DOR1 3 -#define FE1 4 -#define UDRE1 5 -#define TXC1 6 -#define RXC1 7 - -#define UDR1 _SFR_MEM8(0x9C) - -#define UCSR1C _SFR_MEM8(0x9D) -#define UCPOL1 0 -#define UCSZ10 1 -#define UCSZ11 2 -#define USBS1 3 -#define UPM10 4 -#define UPM11 5 -#define UMSEL1 6 - - - -/* Values and associated defines */ - - -#define SLEEP_MODE_IDLE (0x00<<2) -#define SLEEP_MODE_ADC (0x02<<2) -#define SLEEP_MODE_PWR_DOWN (0x04<<2) -#define SLEEP_MODE_PWR_SAVE (0x06<<2) -#define SLEEP_MODE_STANDBY (0x05<<2) -#define SLEEP_MODE_EXT_STANDBY (0x07<<2) - -/* Interrupt vectors */ -/* Vector 0 is the reset vector */ -/* External Interrupt Request 0 */ -#define INT0_vect _VECTOR(1) -#define INT0_vect_num 1 - -/* External Interrupt Request 1 */ -#define INT1_vect _VECTOR(2) -#define INT1_vect_num 2 - -/* External Interrupt Request 2 */ -#define INT2_vect _VECTOR(3) -#define INT2_vect_num 3 - -/* External Interrupt Request 3 */ -#define INT3_vect _VECTOR(4) -#define INT3_vect_num 4 - -/* External Interrupt Request 4 */ -#define INT4_vect _VECTOR(5) -#define INT4_vect_num 5 - -/* External Interrupt Request 5 */ -#define INT5_vect _VECTOR(6) -#define INT5_vect_num 6 - -/* External Interrupt Request 6 */ -#define INT6_vect _VECTOR(7) -#define INT6_vect_num 7 - -/* External Interrupt Request 7 */ -#define INT7_vect _VECTOR(8) -#define INT7_vect_num 8 - -/* Timer/Counter2 Compare Match */ -#define TIMER2_COMP_vect _VECTOR(9) -#define TIMER2_COMP_vect_num 9 - -/* Timer/Counter2 Overflow */ -#define TIMER2_OVF_vect _VECTOR(10) -#define TIMER2_OVF_vect_num 10 - -/* Timer/Counter1 Capture Event */ -#define TIMER1_CAPT_vect _VECTOR(11) -#define TIMER1_CAPT_vect_num 11 - -/* Timer/Counter1 Compare Match A */ -#define TIMER1_COMPA_vect _VECTOR(12) -#define TIMER1_COMPA_vect_num 12 - -/* Timer/Counter Compare Match B */ -#define TIMER1_COMPB_vect _VECTOR(13) -#define TIMER1_COMPB_vect_num 13 - -/* Timer/Counter1 Overflow */ -#define TIMER1_OVF_vect _VECTOR(14) -#define TIMER1_OVF_vect_num 14 - -/* Timer/Counter0 Compare Match */ -#define TIMER0_COMP_vect _VECTOR(15) -#define TIMER0_COMP_vect_num 15 - -/* Timer/Counter0 Overflow */ -#define TIMER0_OVF_vect _VECTOR(16) -#define TIMER0_OVF_vect_num 16 - -/* SPI Serial Transfer Complete */ -#define SPI_STC_vect _VECTOR(17) -#define SPI_STC_vect_num 17 - -/* USART0, Rx Complete */ -#define USART0_RX_vect _VECTOR(18) -#define USART0_RX_vect_num 18 - -/* USART0 Data Register Empty */ -#define USART0_UDRE_vect _VECTOR(19) -#define USART0_UDRE_vect_num 19 - -/* USART0, Tx Complete */ -#define USART0_TX_vect _VECTOR(20) -#define USART0_TX_vect_num 20 - -/* ADC Conversion Complete */ -#define ADC_vect _VECTOR(21) -#define ADC_vect_num 21 - -/* EEPROM Ready */ -#define EE_READY_vect _VECTOR(22) -#define EE_READY_vect_num 22 - -/* Analog Comparator */ -#define ANALOG_COMP_vect _VECTOR(23) -#define ANALOG_COMP_vect_num 23 - -/* Timer/Counter1 Compare Match C */ -#define TIMER1_COMPC_vect _VECTOR(24) -#define TIMER1_COMPC_vect_num 24 - -/* Timer/Counter3 Capture Event */ -#define TIMER3_CAPT_vect _VECTOR(25) -#define TIMER3_CAPT_vect_num 25 - -/* Timer/Counter3 Compare Match A */ -#define TIMER3_COMPA_vect _VECTOR(26) -#define TIMER3_COMPA_vect_num 26 - -/* Timer/Counter3 Compare Match B */ -#define TIMER3_COMPB_vect _VECTOR(27) -#define TIMER3_COMPB_vect_num 27 - -/* Timer/Counter3 Compare Match C */ -#define TIMER3_COMPC_vect _VECTOR(28) -#define TIMER3_COMPC_vect_num 28 - -/* Timer/Counter3 Overflow */ -#define TIMER3_OVF_vect _VECTOR(29) -#define TIMER3_OVF_vect_num 29 - -/* USART1, Rx Complete */ -#define USART1_RX_vect _VECTOR(30) -#define USART1_RX_vect_num 30 - -/* USART1, Data Register Empty */ -#define USART1_UDRE_vect _VECTOR(31) -#define USART1_UDRE_vect_num 31 - -/* USART1, Tx Complete */ -#define USART1_TX_vect _VECTOR(32) -#define USART1_TX_vect_num 32 - -/* 2-wire Serial Interface */ -#define TWI_vect _VECTOR(33) -#define TWI_vect_num 33 - -/* Store Program Memory Read */ -#define SPM_READY_vect _VECTOR(34) -#define SPM_READY_vect_num 34 - -#define _VECTORS_SIZE 140 - - -/* Constants */ - -#define SPM_PAGESIZE 256 -#define FLASHSTART 0x0000 -#define FLASHEND 0x1FFFF -#define RAMSTART 0x0100 -#define RAMSIZE 4096 -#define RAMEND 0x10FF -#define E2START 0 -#define E2SIZE 4096 -#define E2PAGESIZE 8 -#define E2END 0x0FFF -#define XRAMEND RAMEND - - -/* Fuses */ - -#define FUSE_MEMORY_SIZE 3 - -/* Low Fuse Byte */ -#define FUSE_SUT_CKSEL0 (unsigned char)~_BV(0) -#define FUSE_SUT_CKSEL1 (unsigned char)~_BV(1) -#define FUSE_SUT_CKSEL2 (unsigned char)~_BV(2) -#define FUSE_SUT_CKSEL3 (unsigned char)~_BV(3) -#define FUSE_SUT_CKSEL4 (unsigned char)~_BV(4) -#define FUSE_SUT_CKSEL5 (unsigned char)~_BV(5) -#define FUSE_BODEN (unsigned char)~_BV(6) -#define FUSE_BODLEVEL (unsigned char)~_BV(7) -#define LFUSE_DEFAULT (FUSE_SUT_CKSEL1 & FUSE_SUT_CKSEL2 & FUSE_SUT_CKSEL3 & FUSE_SUT_CKSEL4) - - -/* High Fuse Byte */ -#define FUSE_BOOTRST (unsigned char)~_BV(0) -#define FUSE_BOOTSZ0 (unsigned char)~_BV(1) -#define FUSE_BOOTSZ1 (unsigned char)~_BV(2) -#define FUSE_EESAVE (unsigned char)~_BV(3) -#define FUSE_CKOPT (unsigned char)~_BV(4) -#define FUSE_SPIEN (unsigned char)~_BV(5) -#define FUSE_JTAGEN (unsigned char)~_BV(6) -#define FUSE_OCDEN (unsigned char)~_BV(7) -#define HFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_SPIEN & FUSE_JTAGEN) - - -/* Extended Fuse Byte */ -#define FUSE_WDTON (unsigned char)~_BV(0) -#define FUSE_M103C (unsigned char)~_BV(1) -#define EFUSE_DEFAULT (FUSE_M103C) - - - -/* Lock Bits */ -#define __LOCK_BITS_EXIST -#define __BOOT_LOCK_BITS_0_EXIST -#define __BOOT_LOCK_BITS_1_EXIST - - -/* Signature */ -#define SIGNATURE_0 0x1E -#define SIGNATURE_1 0x97 -#define SIGNATURE_2 0x02 - - -#endif /* #ifdef _AVR_ATMEGA128A_H_INCLUDED */ - diff --git a/arduino/hardware/tools/avr/avr/include/avr/iom128rfa1.h b/arduino/hardware/tools/avr/avr/include/avr/iom128rfa1.h deleted file mode 100644 index 77b814b..0000000 --- a/arduino/hardware/tools/avr/avr/include/avr/iom128rfa1.h +++ /dev/null @@ -1,5385 +0,0 @@ -/* Copyright (c) 2009 Atmel Corporation - All rights reserved. - - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - * Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - * Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in - the documentation and/or other materials provided with the - distribution. - - * Neither the name of the copyright holders nor the names of - contributors may be used to endorse or promote products derived - from this software without specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. */ - -/* $Id: iom128rfa1.h 2009 2009-07-01 14:57:41Z joerg_wunsch $ */ - -/* avr/iom128rfa1.h - definitions for ATmega128RFA1 */ - -#ifndef _AVR_IOM128RFA1_H_ -#define _AVR_IOM128RFA1_H_ 1 - -/* This file should only be included from , never directly. */ - -#ifndef _AVR_IO_H_ -# error "Include instead of this file." -#endif - -#ifndef _AVR_IOXXX_H_ -# define _AVR_IOXXX_H_ "iom128rfa1.h" -#else -# error "Attempt to include more than one file." -#endif - -#include - -#ifndef __ASSEMBLER__ -# define _MMIO_BYTE_STRUCT(mem_addr,type) (*(volatile type *)(mem_addr)) -# define _SFR_IO8_STRUCT(io_addr,type) _MMIO_BYTE_STRUCT((io_addr) + 0x20, type) -# define _SFR_MEM8_STRUCT(io_addr,type) _MMIO_BYTE_STRUCT((io_addr), type) -#endif /* __ASSEMBLER__ */ - -/* - * USAGE: - * - * simple register assignment: - * TIFR1 = 0x17 - * subregister assignment: - * TIFR1_struct.ocf1a = 1 - * (subregister names are converted to small letters) - */ - - -/* Port A Input Pins Address */ -#define PINA _SFR_IO8(0x00) - - /* PINA */ - -#define PINA0 0 -#define PINA1 1 -#define PINA2 2 -#define PINA3 3 -#define PINA4 4 -#define PINA5 5 -#define PINA6 6 -#define PINA7 7 - -/* Port A Data Direction Register */ -#define DDRA _SFR_IO8(0x01) - - /* DDRA */ - -#define DDA0 0 -#define DDA1 1 -#define DDA2 2 -#define DDA3 3 -#define DDA4 4 -#define DDA5 5 -#define DDA6 6 -#define DDA7 7 - -/* Port A Data Register */ -#define PORTA _SFR_IO8(0x02) - - /* PORTA */ - -#define PORTA0 0 -#define PA0 0 -#define PORTA1 1 -#define PA1 1 -#define PORTA2 2 -#define PA2 2 -#define PORTA3 3 -#define PA3 3 -#define PORTA4 4 -#define PA4 4 -#define PORTA5 5 -#define PA5 5 -#define PORTA6 6 -#define PA6 6 -#define PORTA7 7 -#define PA7 7 - -/* Port B Input Pins Address */ -#define PINB _SFR_IO8(0x03) - - /* PINB */ - -#define PINB0 0 -#define PINB1 1 -#define PINB2 2 -#define PINB3 3 -#define PINB4 4 -#define PINB5 5 -#define PINB6 6 -#define PINB7 7 - -/* Port B Data Direction Register */ -#define DDRB _SFR_IO8(0x04) - - /* DDRB */ - -#define DDB0 0 -#define DDB1 1 -#define DDB2 2 -#define DDB3 3 -#define DDB4 4 -#define DDB5 5 -#define DDB6 6 -#define DDB7 7 - -/* Port B Data Register */ -#define PORTB _SFR_IO8(0x05) - - /* PORTB */ - -#define PORTB0 0 -#define PB0 0 -#define PORTB1 1 -#define PB1 1 -#define PORTB2 2 -#define PB2 2 -#define PORTB3 3 -#define PB3 3 -#define PORTB4 4 -#define PB4 4 -#define PORTB5 5 -#define PB5 5 -#define PORTB6 6 -#define PB6 6 -#define PORTB7 7 -#define PB7 7 - -/* Port C Input Pins Address */ -#define PINC _SFR_IO8(0x06) - - /* PINC */ - -#define PINC0 0 -#define PINC1 1 -#define PINC2 2 -#define PINC3 3 -#define PINC4 4 -#define PINC5 5 -#define PINC6 6 -#define PINC7 7 - -/* Port C Data Direction Register */ -#define DDRC _SFR_IO8(0x07) - - /* DDRC */ - -#define DDC0 0 -#define DDC1 1 -#define DDC2 2 -#define DDC3 3 -#define DDC4 4 -#define DDC5 5 -#define DDC6 6 -#define DDC7 7 - -/* Port C Data Register */ -#define PORTC _SFR_IO8(0x08) - - /* PORTC */ - -#define PORTC0 0 -#define PC0 0 -#define PORTC1 1 -#define PC1 1 -#define PORTC2 2 -#define PC2 2 -#define PORTC3 3 -#define PC3 3 -#define PORTC4 4 -#define PC4 4 -#define PORTC5 5 -#define PC5 5 -#define PORTC6 6 -#define PC6 6 -#define PORTC7 7 -#define PC7 7 - -/* Port D Input Pins Address */ -#define PIND _SFR_IO8(0x09) - - /* PIND */ - -#define PIND0 0 -#define PIND1 1 -#define PIND2 2 -#define PIND3 3 -#define PIND4 4 -#define PIND5 5 -#define PIND6 6 -#define PIND7 7 - -/* Port D Data Direction Register */ -#define DDRD _SFR_IO8(0x0A) - - /* DDRD */ - -#define DDD0 0 -#define DDD1 1 -#define DDD2 2 -#define DDD3 3 -#define DDD4 4 -#define DDD5 5 -#define DDD6 6 -#define DDD7 7 - -/* Port D Data Register */ -#define PORTD _SFR_IO8(0x0B) - - /* PORTD */ - -#define PORTD0 0 -#define PD0 0 -#define PORTD1 1 -#define PD1 1 -#define PORTD2 2 -#define PD2 2 -#define PORTD3 3 -#define PD3 3 -#define PORTD4 4 -#define PD4 4 -#define PORTD5 5 -#define PD5 5 -#define PORTD6 6 -#define PD6 6 -#define PORTD7 7 -#define PD7 7 - -/* Port E Input Pins Address */ -#define PINE _SFR_IO8(0x0C) - - /* PINE */ - -#define PINE0 0 -#define PINE1 1 -#define PINE2 2 -#define PINE3 3 -#define PINE4 4 -#define PINE5 5 -#define PINE6 6 -#define PINE7 7 - -/* Port E Data Direction Register */ -#define DDRE _SFR_IO8(0x0D) - - /* DDRE */ - -#define DDE0 0 -#define DDE1 1 -#define DDE2 2 -#define DDE3 3 -#define DDE4 4 -#define DDE5 5 -#define DDE6 6 -#define DDE7 7 - -/* Port E Data Register */ -#define PORTE _SFR_IO8(0x0E) - - /* PORTE */ - -#define PORTE0 0 -#define PE0 0 -#define PORTE1 1 -#define PE1 1 -#define PORTE2 2 -#define PE2 2 -#define PORTE3 3 -#define PE3 3 -#define PORTE4 4 -#define PE4 4 -#define PORTE5 5 -#define PE5 5 -#define PORTE6 6 -#define PE6 6 -#define PORTE7 7 -#define PE7 7 - -/* Port F Input Pins Address */ -#define PINF _SFR_IO8(0x0F) - - /* PINF */ - -#define PINF0 0 -#define PINF1 1 -#define PINF2 2 -#define PINF3 3 -#define PINF4 4 -#define PINF5 5 -#define PINF6 6 -#define PINF7 7 - -/* Port F Data Direction Register */ -#define DDRF _SFR_IO8(0x10) - - /* DDRF */ - -#define DDF0 0 -#define DDF1 1 -#define DDF2 2 -#define DDF3 3 -#define DDF4 4 -#define DDF5 5 -#define DDF6 6 -#define DDF7 7 - -/* Port F Data Register */ -#define PORTF _SFR_IO8(0x11) - - /* PORTF */ - -#define PORTF0 0 -#define PF0 0 -#define PORTF1 1 -#define PF1 1 -#define PORTF2 2 -#define PF2 2 -#define PORTF3 3 -#define PF3 3 -#define PORTF4 4 -#define PF4 4 -#define PORTF5 5 -#define PF5 5 -#define PORTF6 6 -#define PF6 6 -#define PORTF7 7 -#define PF7 7 - -/* Port G Input Pins Address */ -#define PING _SFR_IO8(0x12) - - /* PING */ - -#define PING0 0 -#define PING1 1 -#define PING2 2 -#define PING3 3 -#define PING4 4 -#define PING5 5 - -/* Port G Data Direction Register */ -#define DDRG _SFR_IO8(0x13) - - /* DDRG */ - -#define DDG0 0 -#define DDG1 1 -#define DDG2 2 -#define DDG3 3 -#define DDG4 4 -#define DDG5 5 - -/* Port G Data Register */ -#define PORTG _SFR_IO8(0x14) - - /* PORTG */ - -#define PORTG0 0 -#define PG0 0 -#define PORTG1 1 -#define PG1 1 -#define PORTG2 2 -#define PG2 2 -#define PORTG3 3 -#define PG3 3 -#define PORTG4 4 -#define PG4 4 -#define PORTG5 5 -#define PG5 5 - -/* Timer/Counter0 Interrupt Flag Register */ -#define TIFR0 _SFR_IO8(0x15) - -#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) - -struct __reg_TIFR0 { - unsigned int tov0 : 1; /* Timer/Counter0 Overflow Flag */ - unsigned int ocf0a : 1; /* Timer/Counter0 Output Compare A Match Flag */ - unsigned int ocf0b : 1; /* Timer/Counter0 Output Compare B Match Flag */ - unsigned int : 5; -}; - -#define TIFR0_struct _SFR_IO8_STRUCT(0x15, struct __reg_TIFR0) - -#endif /* __ASSEMBLER__ */ - - /* TIFR0 */ - -#define TOV0 0 -#define OCF0A 1 -#define OCF0B 2 - -/* Timer/Counter1 Interrupt Flag Register */ -#define TIFR1 _SFR_IO8(0x16) - -#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) - -struct __reg_TIFR1 { - unsigned int tov1 : 1; /* Timer/Counter1 Overflow Flag */ - unsigned int ocf1a : 1; /* Timer/Counter1 Output Compare A Match Flag */ - unsigned int ocf1b : 1; /* Timer/Counter1 Output Compare B Match Flag */ - unsigned int ocf1c : 1; /* Timer/Counter1 Output Compare C Match Flag */ - unsigned int : 1; - unsigned int icf1 : 1; /* Timer/Counter1 Input Capture Flag */ - unsigned int : 2; -}; - -#define TIFR1_struct _SFR_IO8_STRUCT(0x16, struct __reg_TIFR1) - -#endif /* __ASSEMBLER__ */ - - /* TIFR1 */ - -#define TOV1 0 -#define OCF1A 1 -#define OCF1B 2 -#define OCF1C 3 -#define ICF1 5 - -/* Timer/Counter Interrupt Flag Register */ -#define TIFR2 _SFR_IO8(0x17) - -#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) - -struct __reg_TIFR2 { - unsigned int tov2 : 1; /* Timer/Counter2 Overflow Flag */ - unsigned int ocf2a : 1; /* Output Compare Flag 2 A */ - unsigned int ocf2b : 1; /* Output Compare Flag 2 B */ - unsigned int : 5; -}; - -#define TIFR2_struct _SFR_IO8_STRUCT(0x17, struct __reg_TIFR2) - -#endif /* __ASSEMBLER__ */ - - /* TIFR2 */ - -#define TOV2 0 -#define OCF2A 1 -#define OCF2B 2 - -/* Timer/Counter3 Interrupt Flag Register */ -#define TIFR3 _SFR_IO8(0x18) - -#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) - -struct __reg_TIFR3 { - unsigned int tov3 : 1; /* Timer/Counter3 Overflow Flag */ - unsigned int ocf3a : 1; /* Timer/Counter3 Output Compare A Match Flag */ - unsigned int ocf3b : 1; /* Timer/Counter3 Output Compare B Match Flag */ - unsigned int ocf3c : 1; /* Timer/Counter3 Output Compare C Match Flag */ - unsigned int : 1; - unsigned int icf3 : 1; /* Timer/Counter3 Input Capture Flag */ - unsigned int : 2; -}; - -#define TIFR3_struct _SFR_IO8_STRUCT(0x18, struct __reg_TIFR3) - -#endif /* __ASSEMBLER__ */ - - /* TIFR3 */ - -#define TOV3 0 -#define OCF3A 1 -#define OCF3B 2 -#define OCF3C 3 -#define ICF3 5 - -/* Timer/Counter4 Interrupt Flag Register */ -#define TIFR4 _SFR_IO8(0x19) - -#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) - -struct __reg_TIFR4 { - unsigned int tov4 : 1; /* Timer/Counter4 Overflow Flag */ - unsigned int ocf4a : 1; /* Timer/Counter4 Output Compare A Match Flag */ - unsigned int ocf4b : 1; /* Timer/Counter4 Output Compare B Match Flag */ - unsigned int ocf4c : 1; /* Timer/Counter4 Output Compare C Match Flag */ - unsigned int : 1; - unsigned int icf4 : 1; /* Timer/Counter4 Input Capture Flag */ - unsigned int : 2; -}; - -#define TIFR4_struct _SFR_IO8_STRUCT(0x19, struct __reg_TIFR4) - -#endif /* __ASSEMBLER__ */ - - /* TIFR4 */ - -#define TOV4 0 -#define OCF4A 1 -#define OCF4B 2 -#define OCF4C 3 -#define ICF4 5 - -/* Timer/Counter5 Interrupt Flag Register */ -#define TIFR5 _SFR_IO8(0x1A) - -#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) - -struct __reg_TIFR5 { - unsigned int tov5 : 1; /* Timer/Counter5 Overflow Flag */ - unsigned int ocf5a : 1; /* Timer/Counter5 Output Compare A Match Flag */ - unsigned int ocf5b : 1; /* Timer/Counter5 Output Compare B Match Flag */ - unsigned int ocf5c : 1; /* Timer/Counter5 Output Compare C Match Flag */ - unsigned int : 1; - unsigned int icf5 : 1; /* Timer/Counter5 Input Capture Flag */ - unsigned int : 2; -}; - -#define TIFR5_struct _SFR_IO8_STRUCT(0x1a, struct __reg_TIFR5) - -#endif /* __ASSEMBLER__ */ - - /* TIFR5 */ - -#define TOV5 0 -#define OCF5A 1 -#define OCF5B 2 -#define OCF5C 3 -#define ICF5 5 - -/* Pin Change Interrupt Flag Register */ -#define PCIFR _SFR_IO8(0x1B) - -#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) - -struct __reg_PCIFR { - unsigned int pcif : 3; /* Pin Change Interrupt Flag 2 */ - unsigned int : 5; -}; - -#define PCIFR_struct _SFR_IO8_STRUCT(0x1b, struct __reg_PCIFR) - -#endif /* __ASSEMBLER__ */ - - /* PCIFR */ - -#define PCIF0 0 -#define PCIF1 1 -#define PCIF2 2 - -/* External Interrupt Flag Register */ -#define EIFR _SFR_IO8(0x1C) - -#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) - -struct __reg_EIFR { - unsigned int intf : 8; /* External Interrupt Flag */ -}; - -#define EIFR_struct _SFR_IO8_STRUCT(0x1c, struct __reg_EIFR) - -#endif /* __ASSEMBLER__ */ - - /* EIFR */ - -#define INTF0 0 -#define INTF1 1 -#define INTF2 2 -#define INTF3 3 -#define INTF4 4 -#define INTF5 5 -#define INTF6 6 -#define INTF7 7 - -/* External Interrupt Mask Register */ -#define EIMSK _SFR_IO8(0x1D) - -#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) - -struct __reg_EIMSK { - unsigned int intm : 8; /* External Interrupt Request Enable */ -}; - -#define EIMSK_struct _SFR_IO8_STRUCT(0x1d, struct __reg_EIMSK) - -#endif /* __ASSEMBLER__ */ - - /* EIMSK */ - -#define INT0 0 -#define INT1 1 -#define INT2 2 -#define INT3 3 -#define INT4 4 -#define INT5 5 -#define INT6 6 -#define INT7 7 - -/* General Purpose IO Register 0 */ -#define GPIOR0 _SFR_IO8(0x1E) - -#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) - -struct __reg_GPIOR0 { - unsigned int gpior0 : 8; /* General Purpose I/O Register 0 Value */ -}; - -#define GPIOR0_struct _SFR_IO8_STRUCT(0x1e, struct __reg_GPIOR0) - -#endif /* __ASSEMBLER__ */ - - /* GPIOR0 */ - -#define GPIOR00 0 -#define GPIOR01 1 -#define GPIOR02 2 -#define GPIOR03 3 -#define GPIOR04 4 -#define GPIOR05 5 -#define GPIOR06 6 -#define GPIOR07 7 - -/* 6-char sequence denoting where to find the EEPROM registers in memory space. - Adresses denoted in hex syntax with uppercase letters. Used by the EEPROM - subroutines. - First two letters: EECR address. - Second two letters: EEDR address. - Last two letters: EEAR address. */ - -#define __EEPROM_REG_LOCATIONS__ 1F2021 - -/* EEPROM Control Register */ -#define EECR _SFR_IO8(0x1F) - -#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) - -struct __reg_EECR { - unsigned int eere : 1; /* EEPROM Read Enable */ - unsigned int eepe : 1; /* EEPROM Programming Enable */ - unsigned int eempe : 1; /* EEPROM Master Write Enable */ - unsigned int eerie : 1; /* EEPROM Ready Interrupt Enable */ - unsigned int eepm : 2; /* EEPROM Programming Mode */ - unsigned int : 2; -}; - -#define EECR_struct _SFR_IO8_STRUCT(0x1f, struct __reg_EECR) - -#endif /* __ASSEMBLER__ */ - - /* EECR */ - -#define EERE 0 -#define EEPE 1 -#define EEMPE 2 -#define EERIE 3 -#define EEPM0 4 -#define EEPM1 5 - -/* EEPROM Data Register */ -#define EEDR _SFR_IO8(0x20) - - /* EEDR */ - -#define EEDR0 0 -#define EEDR1 1 -#define EEDR2 2 -#define EEDR3 3 -#define EEDR4 4 -#define EEDR5 5 -#define EEDR6 6 -#define EEDR7 7 - -/* EEPROM Address Register Bytes */ -#define EEAR _SFR_IO16(0x21) -#define EEARL _SFR_IO8(0x21) -#define EEARH _SFR_IO8(0x22) - -/* General Timer/Counter Control Register */ -#define GTCCR _SFR_IO8(0x23) - -#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) - -struct __reg_GTCCR { - unsigned int psrsync : 1; /* Prescaler Reset for Synchronous Timer/Counters */ - unsigned int psrasy : 1; /* Prescaler Reset Timer/Counter2 */ - unsigned int : 5; - unsigned int tsm : 1; /* Timer/Counter Synchronization Mode */ -}; - -#define GTCCR_struct _SFR_IO8_STRUCT(0x23, struct __reg_GTCCR) - -#endif /* __ASSEMBLER__ */ - - /* GTCCR */ - -#define PSRSYNC 0 -#define PSR10 0 -#define PSRASY 1 -#define PSR2 1 -#define TSM 7 - -/* Timer/Counter0 Control Register A */ -#define TCCR0A _SFR_IO8(0x24) - -#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) - -struct __reg_TCCR0A { - unsigned int wgm0 : 2; /* Waveform Generation Mode */ - unsigned int : 2; - unsigned int com0b : 2; /* Compare Match Output B Mode */ - unsigned int com0a : 2; /* Compare Match Output A Mode */ -}; - -#define TCCR0A_struct _SFR_IO8_STRUCT(0x24, struct __reg_TCCR0A) - -#endif /* __ASSEMBLER__ */ - - /* TCCR0A */ - -#define WGM00 0 -#define WGM01 1 -#define COM0B0 4 -#define COM0B1 5 -#define COM0A0 6 -#define COM0A1 7 - -/* Timer/Counter0 Control Register B */ -#define TCCR0B _SFR_IO8(0x25) - -#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) - -struct __reg_TCCR0B { - unsigned int cs0 : 3; /* Clock Select */ - unsigned int wgm02 : 1; /* */ - unsigned int : 2; - unsigned int foc0b : 1; /* Force Output Compare B */ - unsigned int foc0a : 1; /* Force Output Compare A */ -}; - -#define TCCR0B_struct _SFR_IO8_STRUCT(0x25, struct __reg_TCCR0B) - -#endif /* __ASSEMBLER__ */ - - /* TCCR0B */ - -#define CS00 0 -#define CS01 1 -#define CS02 2 -#define WGM02 3 -#define FOC0B 6 -#define FOC0A 7 - -/* Timer/Counter0 Register */ -#define TCNT0 _SFR_IO8(0x26) - - /* TCNT0 */ - -#define TCNT0_0 0 -#define TCNT0_1 1 -#define TCNT0_2 2 -#define TCNT0_3 3 -#define TCNT0_4 4 -#define TCNT0_5 5 -#define TCNT0_6 6 -#define TCNT0_7 7 - -/* Timer/Counter0 Output Compare Register */ -#define OCR0A _SFR_IO8(0x27) - - /* OCR0A */ - -#define OCR0A_0 0 -#define OCR0A_1 1 -#define OCR0A_2 2 -#define OCR0A_3 3 -#define OCR0A_4 4 -#define OCR0A_5 5 -#define OCR0A_6 6 -#define OCR0A_7 7 - -/* Timer/Counter0 Output Compare Register B */ -#define OCR0B _SFR_IO8(0x28) - - /* OCR0B */ - -#define OCR0B_0 0 -#define OCR0B_1 1 -#define OCR0B_2 2 -#define OCR0B_3 3 -#define OCR0B_4 4 -#define OCR0B_5 5 -#define OCR0B_6 6 -#define OCR0B_7 7 - -/* General Purpose IO Register 1 */ -#define GPIOR1 _SFR_IO8(0x2A) - -#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) - -struct __reg_GPIOR1 { - unsigned int gpior1 : 8; /* General Purpose I/O Register 1 Value */ -}; - -#define GPIOR1_struct _SFR_IO8_STRUCT(0x2a, struct __reg_GPIOR1) - -#endif /* __ASSEMBLER__ */ - - /* GPIOR1 */ - -#define GPIOR10 0 -#define GPIOR11 1 -#define GPIOR12 2 -#define GPIOR13 3 -#define GPIOR14 4 -#define GPIOR15 5 -#define GPIOR16 6 -#define GPIOR17 7 - -/* General Purpose I/O Register 2 */ -#define GPIOR2 _SFR_IO8(0x2B) - -#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) - -struct __reg_GPIOR2 { - unsigned int gpior2 : 8; /* General Purpose I/O Register 2 Value */ -}; - -#define GPIOR2_struct _SFR_IO8_STRUCT(0x2b, struct __reg_GPIOR2) - -#endif /* __ASSEMBLER__ */ - - /* GPIOR2 */ - -#define GPIOR20 0 -#define GPIOR21 1 -#define GPIOR22 2 -#define GPIOR23 3 -#define GPIOR24 4 -#define GPIOR25 5 -#define GPIOR26 6 -#define GPIOR27 7 - -/* SPI Control Register */ -#define SPCR _SFR_IO8(0x2C) - -#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) - -struct __reg_SPCR { - unsigned int spr : 2; /* SPI Clock Rate Select 1 and 0 */ - unsigned int cpha : 1; /* Clock Phase */ - unsigned int cpol : 1; /* Clock polarity */ - unsigned int mstr : 1; /* Master/Slave Select */ - unsigned int dord : 1; /* Data Order */ - unsigned int spe : 1; /* SPI Enable */ - unsigned int spie : 1; /* SPI Interrupt Enable */ -}; - -#define SPCR_struct _SFR_IO8_STRUCT(0x2c, struct __reg_SPCR) - -#endif /* __ASSEMBLER__ */ - - /* SPCR */ - -#define SPR0 0 -#define SPR1 1 -#define CPHA 2 -#define CPOL 3 -#define MSTR 4 -#define DORD 5 -#define SPE 6 -#define SPIE 7 - -/* SPI Status Register */ -#define SPSR _SFR_IO8(0x2D) - -#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) - -struct __reg_SPSR { - unsigned int spi2x : 1; /* Double SPI Speed Bit */ - unsigned int : 5; - unsigned int wcol : 1; /* Write Collision Flag */ - unsigned int spif : 1; /* SPI Interrupt Flag */ -}; - -#define SPSR_struct _SFR_IO8_STRUCT(0x2d, struct __reg_SPSR) - -#endif /* __ASSEMBLER__ */ - - /* SPSR */ - -#define SPI2X 0 -#define WCOL 6 -#define SPIF 7 - -/* SPI Data Register */ -#define SPDR _SFR_IO8(0x2E) - - /* SPDR */ - -#define SPDR0 0 -#define SPDR1 1 -#define SPDR2 2 -#define SPDR3 3 -#define SPDR4 4 -#define SPDR5 5 -#define SPDR6 6 -#define SPDR7 7 - -/* Analog Comparator Control And Status Register */ -#define ACSR _SFR_IO8(0x30) - -#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) - -struct __reg_ACSR { - unsigned int acis : 2; /* Analog Comparator Interrupt Mode Select */ - unsigned int acic : 1; /* Analog Comparator Input Capture Enable */ - unsigned int acie : 1; /* Analog Comparator Interrupt Enable */ - unsigned int aci : 1; /* Analog Comparator Interrupt Flag */ - unsigned int aco : 1; /* Analog Compare Output */ - unsigned int acbg : 1; /* Analog Comparator Bandgap Select */ - unsigned int acd : 1; /* Analog Comparator Disable */ -}; - -#define ACSR_struct _SFR_IO8_STRUCT(0x30, struct __reg_ACSR) - -#endif /* __ASSEMBLER__ */ - - /* ACSR */ - -#define ACIS0 0 -#define ACIS1 1 -#define ACIC 2 -#define ACIE 3 -#define ACI 4 -#define ACO 5 -#define ACBG 6 -#define ACD 7 - -/* On-Chip Debug Register */ -#define OCDR _SFR_IO8(0x31) - -#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) - -struct __reg_OCDR { - unsigned int ocdr : 8; /* On-Chip Debug Register Data */ -}; - -#define OCDR_struct _SFR_IO8_STRUCT(0x31, struct __reg_OCDR) - -#endif /* __ASSEMBLER__ */ - - /* OCDR */ - -#define OCDR0 0 -#define OCDR1 1 -#define OCDR2 2 -#define OCDR3 3 -#define OCDR4 4 -#define OCDR5 5 -#define OCDR6 6 -#define OCDR7 7 -#define IDRD 7 - -/* Sleep Mode Control Register */ -#define SMCR _SFR_IO8(0x33) - -#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) - -struct __reg_SMCR { - unsigned int se : 1; /* Sleep Enable */ - unsigned int sm : 3; /* Sleep Mode Select bits */ - unsigned int : 4; -}; - -#define SMCR_struct _SFR_IO8_STRUCT(0x33, struct __reg_SMCR) - -#endif /* __ASSEMBLER__ */ - - /* SMCR */ - -#define SE 0 -#define SM0 1 -#define SM1 2 -#define SM2 3 - -/* MCU Status Register */ -#define MCUSR _SFR_IO8(0x34) - -#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) - -struct __reg_MCUSR { - unsigned int porf : 1; /* Power-on Reset Flag */ - unsigned int extrf : 1; /* External Reset Flag */ - unsigned int borf : 1; /* Brown-out Reset Flag */ - unsigned int wdrf : 1; /* Watchdog Reset Flag */ - unsigned int jtrf : 1; /* JTAG Reset Flag */ - unsigned int : 3; -}; - -#define MCUSR_struct _SFR_IO8_STRUCT(0x34, struct __reg_MCUSR) - -#endif /* __ASSEMBLER__ */ - - /* MCUSR */ - -#define PORF 0 -#define EXTRF 1 -#define BORF 2 -#define WDRF 3 -#define JTRF 4 - -/* MCU Control Register */ -#define MCUCR _SFR_IO8(0x35) - -#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) - -struct __reg_MCUCR { - unsigned int ivce : 1; /* Interrupt Vector Change Enable */ - unsigned int ivsel : 1; /* Interrupt Vector Select */ - unsigned int : 2; - unsigned int pud : 1; /* Pull-up Disable */ - unsigned int : 2; - unsigned int jtd : 1; /* JTAG Interface Disable */ -}; - -#define MCUCR_struct _SFR_IO8_STRUCT(0x35, struct __reg_MCUCR) - -#endif /* __ASSEMBLER__ */ - - /* MCUCR */ - -#define IVCE 0 -#define IVSEL 1 -#define PUD 4 -#define JTD 7 - -/* Store Program Memory Control Register */ -#define SPMCSR _SFR_IO8(0x37) - -#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) - -struct __reg_SPMCSR { - unsigned int spmen : 1; /* Store Program Memory Enable */ - unsigned int pgers : 1; /* Page Erase */ - unsigned int pgwrt : 1; /* Page Write */ - unsigned int blbset : 1; /* Boot Lock Bit Set */ - unsigned int rwwsre : 1; /* Read While Write Section Read Enable */ - unsigned int sigrd : 1; /* Signature Row Read */ - unsigned int rwwsb : 1; /* Read While Write Section Busy */ - unsigned int spmie : 1; /* SPM Interrupt Enable */ -}; - -#define SPMCSR_struct _SFR_IO8_STRUCT(0x37, struct __reg_SPMCSR) - -#endif /* __ASSEMBLER__ */ - - /* SPMCSR */ - -#define SPMEN 0 -#define PGERS 1 -#define PGWRT 2 -#define BLBSET 3 -#define RWWSRE 4 -#define SIGRD 5 -#define RWWSB 6 -#define SPMIE 7 - -/* Extended Z-pointer Register for ELPM/SPM */ -#define RAMPZ _SFR_IO8(0x3B) - -#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) - -struct __reg_RAMPZ { - unsigned int rampz : 2; /* Extended Z-Pointer Value */ - unsigned int : 6; -}; - -#define RAMPZ_struct _SFR_IO8_STRUCT(0x3b, struct __reg_RAMPZ) - -#endif /* __ASSEMBLER__ */ - - /* RAMPZ */ - -#define RAMPZ0 0 -#define RAMPZ1 1 - -/* Stack Pointer */ -#define SP _SFR_IO16(0x3D) -#define SPL _SFR_IO8(0x3D) -#define SPH _SFR_IO8(0x3E) - -/* Status Register */ -#define SREG _SFR_IO8(0x3F) - -#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) - -struct __reg_SREG { - unsigned int c : 1; /* Carry Flag */ - unsigned int z : 1; /* Zero Flag */ - unsigned int n : 1; /* Negative Flag */ - unsigned int v : 1; /* Two's Complement Overflow Flag */ - unsigned int s : 1; /* Sign Bit */ - unsigned int h : 1; /* Half Carry Flag */ - unsigned int t : 1; /* Bit Copy Storage */ - unsigned int i : 1; /* Global Interrupt Enable */ -}; - -#define SREG_struct _SFR_IO8_STRUCT(0x3f, struct __reg_SREG) - -#endif /* __ASSEMBLER__ */ - - /* SREG */ - -#define SREG_C 0 -#define SREG_Z 1 -#define SREG_N 2 -#define SREG_V 3 -#define SREG_S 4 -#define SREG_H 5 -#define SREG_T 6 -#define SREG_I 7 - -/* Watchdog Timer Control Register */ -#define WDTCSR _SFR_MEM8(0x60) - -#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) - -struct __reg_WDTCSR { - unsigned int wdp : 3; /* Watchdog Timer Prescaler bits */ - unsigned int wde : 1; /* Watch Dog Enable */ - unsigned int wdce : 1; /* Watchdog Change Enable */ - unsigned int : 1; - unsigned int wdie : 1; /* Watchdog Timeout Interrupt Enable */ - unsigned int wdif : 1; /* Watchdog Timeout Interrupt Flag */ -}; - -#define WDTCSR_struct _SFR_MEM8_STRUCT(0x60, struct __reg_WDTCSR) - -#endif /* __ASSEMBLER__ */ - - /* WDTCSR */ - -#define WDP0 0 -#define WDP1 1 -#define WDP2 2 -#define WDE 3 -#define WDCE 4 -#define WDP3 5 -#define WDIE 6 -#define WDIF 7 - -/* Clock Prescale Register */ -#define CLKPR _SFR_MEM8(0x61) - -#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) - -struct __reg_CLKPR { - unsigned int clkps : 4; /* Clock Prescaler Select Bits */ - unsigned int : 3; - unsigned int clkpce : 1; /* Clock Prescaler Change Enable */ -}; - -#define CLKPR_struct _SFR_MEM8_STRUCT(0x61, struct __reg_CLKPR) - -#endif /* __ASSEMBLER__ */ - - /* CLKPR */ - -#define CLKPS0 0 -#define CLKPS1 1 -#define CLKPS2 2 -#define CLKPS3 3 -#define CLKPCE 7 - -/* Power Reduction Register 2 */ -#define PRR2 _SFR_MEM8(0x63) - -#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) - -struct __reg_PRR2 { - unsigned int prram : 4; /* Power Reduction SRAM 3 */ - unsigned int : 4; -}; - -#define PRR2_struct _SFR_MEM8_STRUCT(0x63, struct __reg_PRR2) - -#endif /* __ASSEMBLER__ */ - - /* PRR2 */ - -#define PRRAM0 0 -#define PRRAM1 1 -#define PRRAM2 2 -#define PRRAM3 3 - -#define __AVR_HAVE_PRR2 ((1< instead of this file." -#endif - -#ifndef _AVR_IOXXX_H_ -# define _AVR_IOXXX_H_ "iom128rfr2.h" -#else -# error "Attempt to include more than one file." -#endif - -/* Registers and associated bit numbers */ - -#define PINA _SFR_IO8(0x00) -#define PINA7 7 -#define PINA6 6 -#define PINA5 5 -#define PINA4 4 -#define PINA3 3 -#define PINA2 2 -#define PINA1 1 -#define PINA0 0 - -#define DDRA _SFR_IO8(0x01) -#define DDRA7 7 -// Inserted "DDA7" from "DDRA7" due to compatibility -#define DDA7 7 -#define DDRA6 6 -// Inserted "DDA6" from "DDRA6" due to compatibility -#define DDA6 6 -#define DDRA5 5 -// Inserted "DDA5" from "DDRA5" due to compatibility -#define DDA5 5 -#define DDRA4 4 -// Inserted "DDA4" from "DDRA4" due to compatibility -#define DDA4 4 -#define DDRA3 3 -// Inserted "DDA3" from "DDRA3" due to compatibility -#define DDA3 3 -#define DDRA2 2 -// Inserted "DDA2" from "DDRA2" due to compatibility -#define DDA2 2 -#define DDRA1 1 -// Inserted "DDA1" from "DDRA1" due to compatibility -#define DDA1 1 -#define DDRA0 0 -// Inserted "DDA0" from "DDRA0" due to compatibility -#define DDA0 0 - -#define PORTA _SFR_IO8(0x02) -#define PORTA7 7 -#define PORTA6 6 -#define PORTA5 5 -#define PORTA4 4 -#define PORTA3 3 -#define PORTA2 2 -#define PORTA1 1 -#define PORTA0 0 - -#define PINB _SFR_IO8(0x03) -#define PINB7 7 -#define PINB6 6 -#define PINB5 5 -#define PINB4 4 -#define PINB3 3 -#define PINB2 2 -#define PINB1 1 -#define PINB0 0 - -#define DDRB _SFR_IO8(0x04) -#define DDRB7 7 -// Inserted "DDB7" from "DDRB7" due to compatibility -#define DDB7 7 -#define DDRB6 6 -// Inserted "DDB6" from "DDRB6" due to compatibility -#define DDB6 6 -#define DDRB5 5 -// Inserted "DDB5" from "DDRB5" due to compatibility -#define DDB5 5 -#define DDRB4 4 -// Inserted "DDB4" from "DDRB4" due to compatibility -#define DDB4 4 -#define DDRB3 3 -// Inserted "DDB3" from "DDRB3" due to compatibility -#define DDB3 3 -#define DDRB2 2 -// Inserted "DDB2" from "DDRB2" due to compatibility -#define DDB2 2 -#define DDRB1 1 -// Inserted "DDB1" from "DDRB1" due to compatibility -#define DDB1 1 -#define DDRB0 0 -// Inserted "DDB0" from "DDRB0" due to compatibility -#define DDB0 0 - -#define PORTB _SFR_IO8(0x05) -#define PORTB7 7 -#define PORTB6 6 -#define PORTB5 5 -#define PORTB4 4 -#define PORTB3 3 -#define PORTB2 2 -#define PORTB1 1 -#define PORTB0 0 - -#define PINC _SFR_IO8(0x06) -#define PINC7 7 -#define PINC6 6 -#define PINC5 5 -#define PINC4 4 -#define PINC3 3 -#define PINC2 2 -#define PINC1 1 -#define PINC0 0 - -#define DDRC _SFR_IO8(0x07) -#define DDRC7 7 -// Inserted "DDC7" from "DDRC7" due to compatibility -#define DDC7 7 -#define DDRC6 6 -// Inserted "DDC6" from "DDRC6" due to compatibility -#define DDC6 6 -#define DDRC5 5 -// Inserted "DDC5" from "DDRC5" due to compatibility -#define DDC5 5 -#define DDRC4 4 -// Inserted "DDC4" from "DDRC4" due to compatibility -#define DDC4 4 -#define DDRC3 3 -// Inserted "DDC3" from "DDRC3" due to compatibility -#define DDC3 3 -#define DDRC2 2 -// Inserted "DDC2" from "DDRC2" due to compatibility -#define DDC2 2 -#define DDRC1 1 -// Inserted "DDC1" from "DDRC1" due to compatibility -#define DDC1 1 -#define DDRC0 0 -// Inserted "DDC0" from "DDRC0" due to compatibility -#define DDC0 0 - -#define PORTC _SFR_IO8(0x08) -#define PORTC7 7 -#define PORTC6 6 -#define PORTC5 5 -#define PORTC4 4 -#define PORTC3 3 -#define PORTC2 2 -#define PORTC1 1 -#define PORTC0 0 - -#define PIND _SFR_IO8(0x09) -#define PIND7 7 -#define PIND6 6 -#define PIND5 5 -#define PIND4 4 -#define PIND3 3 -#define PIND2 2 -#define PIND1 1 -#define PIND0 0 - -#define DDRD _SFR_IO8(0x0A) -#define DDRD7 7 -// Inserted "DDD7" from "DDRD7" due to compatibility -#define DDD7 7 -#define DDRD6 6 -// Inserted "DDD6" from "DDRD6" due to compatibility -#define DDD6 6 -#define DDRD5 5 -// Inserted "DDD5" from "DDRD5" due to compatibility -#define DDD5 5 -#define DDRD4 4 -// Inserted "DDD4" from "DDRD4" due to compatibility -#define DDD4 4 -#define DDRD3 3 -// Inserted "DDD3" from "DDRD3" due to compatibility -#define DDD3 3 -#define DDRD2 2 -// Inserted "DDD2" from "DDRD2" due to compatibility -#define DDD2 2 -#define DDRD1 1 -// Inserted "DDD1" from "DDRD1" due to compatibility -#define DDD1 1 -#define DDRD0 0 -// Inserted "DDD0" from "DDRD0" due to compatibility -#define DDD0 0 - -#define PORTD _SFR_IO8(0x0B) -#define PORTD7 7 -#define PORTD6 6 -#define PORTD5 5 -#define PORTD4 4 -#define PORTD3 3 -#define PORTD2 2 -#define PORTD1 1 -#define PORTD0 0 - -#define PINE _SFR_IO8(0x0C) -#define PINE7 7 -#define PINE6 6 -#define PINE5 5 -#define PINE4 4 -#define PINE3 3 -#define PINE2 2 -#define PINE1 1 -#define PINE0 0 - -#define DDRE _SFR_IO8(0x0D) -#define DDRE7 7 -// Inserted "DDE7" from "DDRE7" due to compatibility -#define DDE7 7 -#define DDRE6 6 -// Inserted "DDE6" from "DDRE6" due to compatibility -#define DDE6 6 -#define DDRE5 5 -// Inserted "DDE5" from "DDRE5" due to compatibility -#define DDE5 5 -#define DDRE4 4 -// Inserted "DDE4" from "DDRE4" due to compatibility -#define DDE4 4 -#define DDRE3 3 -// Inserted "DDE3" from "DDRE3" due to compatibility -#define DDE3 3 -#define DDRE2 2 -// Inserted "DDE2" from "DDRE2" due to compatibility -#define DDE2 2 -#define DDRE1 1 -// Inserted "DDE1" from "DDRE1" due to compatibility -#define DDE1 1 -#define DDRE0 0 -// Inserted "DDE0" from "DDRE0" due to compatibility -#define DDE0 0 - -#define PORTE _SFR_IO8(0x0E) -#define PORTE7 7 -#define PORTE6 6 -#define PORTE5 5 -#define PORTE4 4 -#define PORTE3 3 -#define PORTE2 2 -#define PORTE1 1 -#define PORTE0 0 - -#define PINF _SFR_IO8(0x0F) -#define PINF7 7 -#define PINF6 6 -#define PINF5 5 -#define PINF4 4 -#define PINF3 3 -#define PINF2 2 -#define PINF1 1 -#define PINF0 0 - -#define DDRF _SFR_IO8(0x10) -#define DDRF7 7 -// Inserted "DDF7" from "DDRF7" due to compatibility -#define DDF7 7 -#define DDRF6 6 -// Inserted "DDF6" from "DDRF6" due to compatibility -#define DDF6 6 -#define DDRF5 5 -// Inserted "DDF5" from "DDRF5" due to compatibility -#define DDF5 5 -#define DDRF4 4 -// Inserted "DDF4" from "DDRF4" due to compatibility -#define DDF4 4 -#define DDRF3 3 -// Inserted "DDF3" from "DDRF3" due to compatibility -#define DDF3 3 -#define DDRF2 2 -// Inserted "DDF2" from "DDRF2" due to compatibility -#define DDF2 2 -#define DDRF1 1 -// Inserted "DDF1" from "DDRF1" due to compatibility -#define DDF1 1 -#define DDRF0 0 -// Inserted "DDF0" from "DDRF0" due to compatibility -#define DDF0 0 - -#define PORTF _SFR_IO8(0x11) -#define PORTF7 7 -#define PORTF6 6 -#define PORTF5 5 -#define PORTF4 4 -#define PORTF3 3 -#define PORTF2 2 -#define PORTF1 1 -#define PORTF0 0 - -#define PING _SFR_IO8(0x12) -#define PING7 7 -#define PING6 6 -#define PING5 5 -#define PING4 4 -#define PING3 3 -#define PING2 2 -#define PING1 1 -#define PING0 0 - -#define DDRG _SFR_IO8(0x13) -#define DDRG7 7 -// Inserted "DDG7" from "DDRG7" due to compatibility -#define DDG7 7 -#define DDRG6 6 -// Inserted "DDG6" from "DDRG6" due to compatibility -#define DDG6 6 -#define DDRG5 5 -// Inserted "DDG5" from "DDRG5" due to compatibility -#define DDG5 5 -#define DDRG4 4 -// Inserted "DDG4" from "DDRG4" due to compatibility -#define DDG4 4 -#define DDRG3 3 -// Inserted "DDG3" from "DDRG3" due to compatibility -#define DDG3 3 -#define DDRG2 2 -// Inserted "DDG2" from "DDRG2" due to compatibility -#define DDG2 2 -#define DDRG1 1 -// Inserted "DDG1" from "DDRG1" due to compatibility -#define DDG1 1 -#define DDRG0 0 -// Inserted "DDG0" from "DDRG0" due to compatibility -#define DDG0 0 - -#define PORTG _SFR_IO8(0x14) -#define PORTG7 7 -#define PORTG6 6 -#define PORTG5 5 -#define PORTG4 4 -#define PORTG3 3 -#define PORTG2 2 -#define PORTG1 1 -#define PORTG0 0 - -#define TIFR0 _SFR_IO8(0x15) -#define TOV0 0 -#define OCF0A 1 -#define OCF0B 2 -#define Res0 3 -#define Res1 4 -#define Res2 5 -#define Res3 6 -#define Res4 7 - -#define TIFR1 _SFR_IO8(0x16) -#define TOV1 0 -#define OCF1A 1 -#define OCF1B 2 -#define OCF1C 3 -#define ICF1 5 - -#define TIFR2 _SFR_IO8(0x17) -#define TOV2 0 -#define OCF2A 1 -#define OCF2B 2 - -#define TIFR3 _SFR_IO8(0x18) -#define TOV3 0 -#define OCF3A 1 -#define OCF3B 2 -#define OCF3C 3 -#define ICF3 5 - -#define TIFR4 _SFR_IO8(0x19) -#define TOV4 0 -#define OCF4A 1 -#define OCF4B 2 -#define OCF4C 3 -#define ICF4 5 - -#define TIFR5 _SFR_IO8(0x1A) -#define TOV5 0 -#define OCF5A 1 -#define OCF5B 2 -#define OCF5C 3 -#define ICF5 5 - -#define PCIFR _SFR_IO8(0x1B) -#define PCIF0 0 -#define PCIF1 1 -#define PCIF2 2 - -#define EIFR _SFR_IO8(0x1C) -#define INTF0 0 -#define INTF1 1 -#define INTF2 2 -#define INTF3 3 -#define INTF4 4 -#define INTF5 5 -#define INTF6 6 -#define INTF7 7 - -#define EIMSK _SFR_IO8(0x1D) -#define INT0 0 -#define INT1 1 -#define INT2 2 -#define INT3 3 -#define INT4 4 -#define INT5 5 -#define INT6 6 -#define INT7 7 - -#define GPIOR0 _SFR_IO8(0x1E) -#define GPIOR00 0 -#define GPIOR01 1 -#define GPIOR02 2 -#define GPIOR03 3 -#define GPIOR04 4 -#define GPIOR05 5 -#define GPIOR06 6 -#define GPIOR07 7 - -#define EECR _SFR_IO8(0x1F) -#define EERE 0 -#define EEPE 1 -#define EEMPE 2 -#define EERIE 3 -#define EEPM0 4 -#define EEPM1 5 - -#define EEDR _SFR_IO8(0x20) - -/* Combine EEARL and EEARH */ -#define EEAR _SFR_IO16(0x21) - -#define EEARL _SFR_IO8(0x21) -#define EEARH _SFR_IO8(0x22) - -#define GTCCR _SFR_IO8(0x23) -#define PSRSYNC 0 -#define PSRASY 1 -#define TSM 7 - -#define TCCR0A _SFR_IO8(0x24) -#define WGM00 0 -#define WGM01 1 -#define COM0B0 4 -#define COM0B1 5 -#define COM0A0 6 -#define COM0A1 7 - -#define TCCR0B _SFR_IO8(0x25) -#define CS00 0 -#define CS01 1 -#define CS02 2 -#define WGM02 3 -#define FOC0B 6 -#define FOC0A 7 - -#define TCNT0 _SFR_IO8(0x26) - -#define OCR0A _SFR_IO8(0x27) - -#define OCR0B _SFR_IO8(0x28) - -/* Reserved [0x29] */ - -#define GPIOR1 _SFR_IO8(0x2A) -#define GPIOR10 0 -#define GPIOR11 1 -#define GPIOR12 2 -#define GPIOR13 3 -#define GPIOR14 4 -#define GPIOR15 5 -#define GPIOR16 6 -#define GPIOR17 7 - -#define GPIOR2 _SFR_IO8(0x2B) -#define GPIOR20 0 -#define GPIOR21 1 -#define GPIOR22 2 -#define GPIOR23 3 -#define GPIOR24 4 -#define GPIOR25 5 -#define GPIOR26 6 -#define GPIOR27 7 - -#define SPCR _SFR_IO8(0x2C) -#define SPR0 0 -#define SPR1 1 -#define CPHA 2 -#define CPOL 3 -#define MSTR 4 -#define DORD 5 -#define SPE 6 -#define SPIE 7 - -#define SPSR _SFR_IO8(0x2D) -#define SPI2X 0 -#define WCOL 6 -#define SPIF 7 - -#define SPDR _SFR_IO8(0x2E) - -/* Reserved [0x2F] */ - -#define ACSR _SFR_IO8(0x30) -#define ACIS0 0 -#define ACIS1 1 -#define ACIC 2 -#define ACIE 3 -#define ACI 4 -#define ACO 5 -#define ACBG 6 -#define ACD 7 - -#define OCDR _SFR_IO8(0x31) -#define OCDR0 0 -#define OCDR1 1 -#define OCDR2 2 -#define OCDR3 3 -#define OCDR4 4 -#define OCDR5 5 -#define OCDR6 6 -#define OCDR7 7 - -/* Reserved [0x32] */ - -#define SMCR _SFR_IO8(0x33) -#define SE 0 -#define SM0 1 -#define SM1 2 -#define SM2 3 - -#define MCUSR _SFR_IO8(0x34) -#define JTRF 4 -#define PORF 0 -#define EXTRF 1 -#define BORF 2 -#define WDRF 3 - -#define MCUCR _SFR_IO8(0x35) -#define JTD 7 -#define IVCE 0 -#define IVSEL 1 -#define PUD 4 - -/* Reserved [0x36] */ - -#define SPMCSR _SFR_IO8(0x37) -#define SPMEN 0 -#define PGERS 1 -#define PGWRT 2 -#define BLBSET 3 -#define RWWSRE 4 -#define SIGRD 5 -#define RWWSB 6 -#define SPMIE 7 - -/* Reserved [0x38..0x3A] */ - -#define RAMPZ _SFR_IO8(0x3B) -#define RAMPZ0 0 -#define Res5 6 -#define Res6 7 - -/* Reserved [0x3C] */ - -/* SP [0x3D..0x3E] */ - -/* SREG [0x3F] */ - -#define WDTCSR _SFR_MEM8(0x60) -#define WDE 3 -#define WDCE 4 -#define WDP0 0 -#define WDP1 1 -#define WDP2 2 -#define WDP3 5 -#define WDIE 6 -#define WDIF 7 - -#define CLKPR _SFR_MEM8(0x61) -#define CLKPS0 0 -#define CLKPS1 1 -#define CLKPS2 2 -#define CLKPS3 3 -#define CLKPCE 7 - -/* Reserved [0x62] */ - -#define PRR2 _SFR_MEM8(0x63) -#define PRRAM0 0 -#define PRRAM1 1 -#define PRRAM2 2 -#define PRRAM3 3 - -#define __AVR_HAVE_PRR2 ((1<, never directly. */ - -#ifndef _AVR_IO_H_ -# error "Include instead of this file." -#endif - -#ifndef _AVR_IOXXX_H_ -# define _AVR_IOXXX_H_ "iom16.h" -#else -# error "Attempt to include more than one file." -#endif - -/* Registers and associated bit numbers */ - -#define TWBR _SFR_IO8(0x00) - -#define TWSR _SFR_IO8(0x01) -#define TWPS0 0 -#define TWPS1 1 -#define TWS3 3 -#define TWS4 4 -#define TWS5 5 -#define TWS6 6 -#define TWS7 7 - -#define TWAR _SFR_IO8(0x02) -#define TWGCE 0 -#define TWA0 1 -#define TWA1 2 -#define TWA2 3 -#define TWA3 4 -#define TWA4 5 -#define TWA5 6 -#define TWA6 7 - -#define TWDR _SFR_IO8(0x03) - -/* Combine ADCL and ADCH */ -#ifndef __ASSEMBLER__ -#define ADC _SFR_IO16(0x04) -#endif -#define ADCW _SFR_IO16(0x04) -#define ADCL _SFR_IO8(0x04) -#define ADCH _SFR_IO8(0x05) - -#define ADCSRA _SFR_IO8(0x06) -#define ADPS0 0 -#define ADPS1 1 -#define ADPS2 2 -#define ADIE 3 -#define ADIF 4 -#define ADATE 5 -#define ADSC 6 -#define ADEN 7 - -#define ADMUX _SFR_IO8(0x07) -#define MUX0 0 -#define MUX1 1 -#define MUX2 2 -#define MUX3 3 -#define MUX4 4 -#define ADLAR 5 -#define REFS0 6 -#define REFS1 7 - -#define ACSR _SFR_IO8(0x08) -#define ACIS0 0 -#define ACIS1 1 -#define ACIC 2 -#define ACIE 3 -#define ACI 4 -#define ACO 5 -#define ACBG 6 -#define ACD 7 - -#define UBRRL _SFR_IO8(0x09) - -#define UCSRB _SFR_IO8(0x0A) -#define TXB8 0 -#define RXB8 1 -#define UCSZ2 2 -#define TXEN 3 -#define RXEN 4 -#define UDRIE 5 -#define TXCIE 6 -#define RXCIE 7 - -#define UCSRA _SFR_IO8(0x0B) -#define MPCM 0 -#define U2X 1 -#define PE 2 -#define DOR 3 -#define FE 4 -#define UDRE 5 -#define TXC 6 -#define RXC 7 - -#define UDR _SFR_IO8(0x0C) - -#define SPCR _SFR_IO8(0x0D) -#define SPR0 0 -#define SPR1 1 -#define CPHA 2 -#define CPOL 3 -#define MSTR 4 -#define DORD 5 -#define SPE 6 -#define SPIE 7 - -#define SPSR _SFR_IO8(0x0E) -#define SPI2X 0 -#define WCOL 6 -#define SPIF 7 - -#define SPDR _SFR_IO8(0x0F) - -#define PIND _SFR_IO8(0x10) -#define PIND0 0 -#define PIND1 1 -#define PIND2 2 -#define PIND3 3 -#define PIND4 4 -#define PIND5 5 -#define PIND6 6 -#define PIND7 7 - -#define DDRD _SFR_IO8(0x11) -#define DDD0 0 -#define DDD1 1 -#define DDD2 2 -#define DDD3 3 -#define DDD4 4 -#define DDD5 5 -#define DDD6 6 -#define DDD7 7 - -#define PORTD _SFR_IO8(0x12) -#define PD0 0 -#define PD1 1 -#define PD2 2 -#define PD3 3 -#define PD4 4 -#define PD5 5 -#define PD6 6 -#define PD7 7 - -#define PINC _SFR_IO8(0x13) -#define PINC0 0 -#define PINC1 1 -#define PINC2 2 -#define PINC3 3 -#define PINC4 4 -#define PINC5 5 -#define PINC6 6 -#define PINC7 7 - -#define DDRC _SFR_IO8(0x14) -#define DDC0 0 -#define DDC1 1 -#define DDC2 2 -#define DDC3 3 -#define DDC4 4 -#define DDC5 5 -#define DDC6 6 -#define DDC7 7 - -#define PORTC _SFR_IO8(0x15) -#define PC0 0 -#define PC1 1 -#define PC2 2 -#define PC3 3 -#define PC4 4 -#define PC5 5 -#define PC6 6 -#define PC7 7 - -#define PINB _SFR_IO8(0x16) -#define PINB0 0 -#define PINB1 1 -#define PINB2 2 -#define PINB3 3 -#define PINB4 4 -#define PINB5 5 -#define PINB6 6 -#define PINB7 7 - -#define DDRB _SFR_IO8(0x17) -#define DDB0 0 -#define DDB1 1 -#define DDB2 2 -#define DDB3 3 -#define DDB4 4 -#define DDB5 5 -#define DDB6 6 -#define DDB7 7 - -#define PORTB _SFR_IO8(0x18) -#define PB0 0 -#define PB1 1 -#define PB2 2 -#define PB3 3 -#define PB4 4 -#define PB5 5 -#define PB6 6 -#define PB7 7 - -#define PINA _SFR_IO8(0x19) -#define PINA0 0 -#define PINA1 1 -#define PINA2 2 -#define PINA3 3 -#define PINA4 4 -#define PINA5 5 -#define PINA6 6 -#define PINA7 7 - -#define DDRA _SFR_IO8(0x1A) -#define DDA0 0 -#define DDA1 1 -#define DDA2 2 -#define DDA3 3 -#define DDA4 4 -#define DDA5 5 -#define DDA6 6 -#define DDA7 7 - -#define PORTA _SFR_IO8(0x1B) -#define PA0 0 -#define PA1 1 -#define PA2 2 -#define PA3 3 -#define PA4 4 -#define PA5 5 -#define PA6 6 -#define PA7 7 - -/* EEPROM Control Register */ -#define EECR _SFR_IO8(0x1C) -#define EERE 0 -#define EEWE 1 -#define EEMWE 2 -#define EERIE 3 - -/* EEPROM Data Register */ -#define EEDR _SFR_IO8(0x1D) - -/* EEPROM Address Register */ -#define EEAR _SFR_IO16(0x1E) -#define EEARL _SFR_IO8(0x1E) -#define EEARH _SFR_IO8(0x1F) - -#define UCSRC _SFR_IO8(0x20) -#define UCPOL 0 -#define UCSZ0 1 -#define UCSZ1 2 -#define USBS 3 -#define UPM0 4 -#define UPM1 5 -#define UMSEL 6 -#define URSEL 7 - -#define UBRRH _SFR_IO8(0x20) -#define URSEL 7 - -#define WDTCR _SFR_IO8(0x21) -#define WDP0 0 -#define WDP1 1 -#define WDP2 2 -#define WDE 3 -#define WDTOE 4 - -#define ASSR _SFR_IO8(0x22) -#define TCR2UB 0 -#define OCR2UB 1 -#define TCN2UB 2 -#define AS2 3 - -#define OCR2 _SFR_IO8(0x23) - -#define TCNT2 _SFR_IO8(0x24) - -#define TCCR2 _SFR_IO8(0x25) -#define CS20 0 -#define CS21 1 -#define CS22 2 -#define WGM21 3 -#define COM20 4 -#define COM21 5 -#define WGM20 6 -#define FOC2 7 - -/* Combine ICR1L and ICR1H */ -#define ICR1 _SFR_IO16(0x26) - -#define ICR1L _SFR_IO8(0x26) -#define ICR1H _SFR_IO8(0x27) - -/* Combine OCR1BL and OCR1BH */ -#define OCR1B _SFR_IO16(0x28) - -#define OCR1BL _SFR_IO8(0x28) -#define OCR1BH _SFR_IO8(0x29) - -/* Combine OCR1AL and OCR1AH */ -#define OCR1A _SFR_IO16(0x2A) - -#define OCR1AL _SFR_IO8(0x2A) -#define OCR1AH _SFR_IO8(0x2B) - -/* Combine TCNT1L and TCNT1H */ -#define TCNT1 _SFR_IO16(0x2C) - -#define TCNT1L _SFR_IO8(0x2C) -#define TCNT1H _SFR_IO8(0x2D) - -#define TCCR1B _SFR_IO8(0x2E) -#define CS10 0 -#define CS11 1 -#define CS12 2 -#define WGM12 3 -#define WGM13 4 -#define ICES1 6 -#define ICNC1 7 - -#define TCCR1A _SFR_IO8(0x2F) -#define WGM10 0 -#define WGM11 1 -#define FOC1B 2 -#define FOC1A 3 -#define COM1B0 4 -#define COM1B1 5 -#define COM1A0 6 -#define COM1A1 7 - -/* - The ADHSM bit has been removed from all documentation, - as being not needed at all since the comparator has proven - to be fast enough even without feeding it more power. -*/ - -#define SFIOR _SFR_IO8(0x30) -#define PSR10 0 -#define PSR2 1 -#define PUD 2 -#define ACME 3 -#define ADTS0 5 -#define ADTS1 6 -#define ADTS2 7 - -#define OSCCAL _SFR_IO8(0x31) - -#define OCDR _SFR_IO8(0x31) - -#define TCNT0 _SFR_IO8(0x32) - -#define TCCR0 _SFR_IO8(0x33) -#define CS00 0 -#define CS01 1 -#define CS02 2 -#define WGM01 3 -#define COM00 4 -#define COM01 5 -#define WGM00 6 -#define FOC0 7 - -#define MCUCSR _SFR_IO8(0x34) -#define PORF 0 -#define EXTRF 1 -#define BORF 2 -#define WDRF 3 -#define JTRF 4 -#define ISC2 6 -#define JTD 7 - -#define MCUCR _SFR_IO8(0x35) -#define ISC00 0 -#define ISC01 1 -#define ISC10 2 -#define ISC11 3 -#define SM0 4 -#define SM1 5 -#define SE 6 -#define SM2 7 - -#define TWCR _SFR_IO8(0x36) -#define TWIE 0 -#define TWEN 2 -#define TWWC 3 -#define TWSTO 4 -#define TWSTA 5 -#define TWEA 6 -#define TWINT 7 - -#define SPMCR _SFR_IO8(0x37) -#define SPMEN 0 -#define PGERS 1 -#define PGWRT 2 -#define BLBSET 3 -#define RWWSRE 4 -#define RWWSB 6 -#define SPMIE 7 - -#define TIFR _SFR_IO8(0x38) -#define TOV0 0 -#define OCF0 1 -#define TOV1 2 -#define OCF1B 3 -#define OCF1A 4 -#define ICF1 5 -#define TOV2 6 -#define OCF2 7 - -#define TIMSK _SFR_IO8(0x39) -#define TOIE0 0 -#define OCIE0 1 -#define TOIE1 2 -#define OCIE1B 3 -#define OCIE1A 4 -#define TICIE1 5 -#define TOIE2 6 -#define OCIE2 7 - -#define GIFR _SFR_IO8(0x3A) -#define INTF2 5 -#define INTF0 6 -#define INTF1 7 - -#define GICR _SFR_IO8(0x3B) -#define IVCE 0 -#define IVSEL 1 -#define INT2 5 -#define INT0 6 -#define INT1 7 - -#define OCR0 _SFR_IO8(0x3C) - -/* SP [0x3D..0x3E] */ -/* SREG [0x3F] */ - - -/* Interrupt vectors */ -/* Vector 0 is the reset vector. */ -/* External Interrupt Request 0 */ -#define INT0_vect_num 1 -#define INT0_vect _VECTOR(1) -#define SIG_INTERRUPT0 _VECTOR(1) - -/* External Interrupt Request 1 */ -#define INT1_vect_num 2 -#define INT1_vect _VECTOR(2) -#define SIG_INTERRUPT1 _VECTOR(2) - -/* Timer/Counter2 Compare Match */ -#define TIMER2_COMP_vect_num 3 -#define TIMER2_COMP_vect _VECTOR(3) -#define SIG_OUTPUT_COMPARE2 _VECTOR(3) - -/* Timer/Counter2 Overflow */ -#define TIMER2_OVF_vect_num 4 -#define TIMER2_OVF_vect _VECTOR(4) -#define SIG_OVERFLOW2 _VECTOR(4) - -/* Timer/Counter1 Capture Event */ -#define TIMER1_CAPT_vect_num 5 -#define TIMER1_CAPT_vect _VECTOR(5) -#define SIG_INPUT_CAPTURE1 _VECTOR(5) - -/* Timer/Counter1 Compare Match A */ -#define TIMER1_COMPA_vect_num 6 -#define TIMER1_COMPA_vect _VECTOR(6) -#define SIG_OUTPUT_COMPARE1A _VECTOR(6) - -/* Timer/Counter1 Compare Match B */ -#define TIMER1_COMPB_vect_num 7 -#define TIMER1_COMPB_vect _VECTOR(7) -#define SIG_OUTPUT_COMPARE1B _VECTOR(7) - -/* Timer/Counter1 Overflow */ -#define TIMER1_OVF_vect_num 8 -#define TIMER1_OVF_vect _VECTOR(8) -#define SIG_OVERFLOW1 _VECTOR(8) - -/* Timer/Counter0 Overflow */ -#define TIMER0_OVF_vect_num 9 -#define TIMER0_OVF_vect _VECTOR(9) -#define SIG_OVERFLOW0 _VECTOR(9) - -/* Serial Transfer Complete */ -#define SPI_STC_vect_num 10 -#define SPI_STC_vect _VECTOR(10) -#define SIG_SPI _VECTOR(10) - -/* USART, Rx Complete */ -#define USART_RXC_vect_num 11 -#define USART_RXC_vect _VECTOR(11) -#define SIG_USART_RECV _VECTOR(11) -#define SIG_UART_RECV _VECTOR(11) - -/* USART Data Register Empty */ -#define USART_UDRE_vect_num 12 -#define USART_UDRE_vect _VECTOR(12) -#define SIG_USART_DATA _VECTOR(12) -#define SIG_UART_DATA _VECTOR(12) - -/* USART, Tx Complete */ -#define USART_TXC_vect_num 13 -#define USART_TXC_vect _VECTOR(13) -#define SIG_USART_TRANS _VECTOR(13) -#define SIG_UART_TRANS _VECTOR(13) - -/* ADC Conversion Complete */ -#define ADC_vect_num 14 -#define ADC_vect _VECTOR(14) -#define SIG_ADC _VECTOR(14) - -/* EEPROM Ready */ -#define EE_RDY_vect_num 15 -#define EE_RDY_vect _VECTOR(15) -#define SIG_EEPROM_READY _VECTOR(15) - -/* Analog Comparator */ -#define ANA_COMP_vect_num 16 -#define ANA_COMP_vect _VECTOR(16) -#define SIG_COMPARATOR _VECTOR(16) - -/* 2-wire Serial Interface */ -#define TWI_vect_num 17 -#define TWI_vect _VECTOR(17) -#define SIG_2WIRE_SERIAL _VECTOR(17) - -/* External Interrupt Request 2 */ -#define INT2_vect_num 18 -#define INT2_vect _VECTOR(18) -#define SIG_INTERRUPT2 _VECTOR(18) - -/* Timer/Counter0 Compare Match */ -#define TIMER0_COMP_vect_num 19 -#define TIMER0_COMP_vect _VECTOR(19) -#define SIG_OUTPUT_COMPARE0 _VECTOR(19) - -/* Store Program Memory Ready */ -#define SPM_RDY_vect_num 20 -#define SPM_RDY_vect _VECTOR(20) -#define SIG_SPM_READY _VECTOR(20) - -#define _VECTORS_SIZE 84 - - -/* Constants */ -#define SPM_PAGESIZE 128 -#define RAMSTART (0x60) -#define RAMEND 0x45F -#define XRAMEND RAMEND -#define E2END 0x1FF -#define E2PAGESIZE 4 -#define FLASHEND 0x3FFF - - -/* Fuses */ - -#define FUSE_MEMORY_SIZE 2 - -/* Low Fuse Byte */ -#define FUSE_CKSEL0 (unsigned char)~_BV(0) -#define FUSE_CKSEL1 (unsigned char)~_BV(1) -#define FUSE_CKSEL2 (unsigned char)~_BV(2) -#define FUSE_CKSEL3 (unsigned char)~_BV(3) -#define FUSE_SUT0 (unsigned char)~_BV(4) -#define FUSE_SUT1 (unsigned char)~_BV(5) -#define FUSE_BODEN (unsigned char)~_BV(6) -#define FUSE_BODLEVEL (unsigned char)~_BV(7) -#define LFUSE_DEFAULT (FUSE_CKSEL1 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0) - -/* High Fuse Byte */ -#define FUSE_BOOTRST (unsigned char)~_BV(0) -#define FUSE_BOOTSZ0 (unsigned char)~_BV(1) -#define FUSE_BOOTSZ1 (unsigned char)~_BV(2) -#define FUSE_EESAVE (unsigned char)~_BV(3) -#define FUSE_CKOPT (unsigned char)~_BV(4) -#define FUSE_SPIEN (unsigned char)~_BV(5) -#define FUSE_JTAGEN (unsigned char)~_BV(6) -#define FUSE_OCDEN (unsigned char)~_BV(7) -#define HFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_SPIEN & FUSE_JTAGEN) - - -/* Lock Bits */ -#define __LOCK_BITS_EXIST -#define __BOOT_LOCK_BITS_0_EXIST -#define __BOOT_LOCK_BITS_1_EXIST - - -/* Signature */ -#define SIGNATURE_0 0x1E -#define SIGNATURE_1 0x94 -#define SIGNATURE_2 0x03 - - - -/* Deprecated items */ -#if !defined(__AVR_LIBC_DEPRECATED_ENABLE__) - -#pragma GCC system_header - -#pragma GCC poison - -#pragma GCC poison SIG_INTERRUPT0 -#pragma GCC poison SIG_INTERRUPT1 -#pragma GCC poison SIG_OUTPUT_COMPARE2 -#pragma GCC poison SIG_OVERFLOW2 -#pragma GCC poison SIG_INPUT_CAPTURE1 -#pragma GCC poison SIG_OUTPUT_COMPARE1A -#pragma GCC poison SIG_OUTPUT_COMPARE1B -#pragma GCC poison SIG_OVERFLOW1 -#pragma GCC poison SIG_OVERFLOW0 -#pragma GCC poison SIG_SPI -#pragma GCC poison SIG_USART_RECV -#pragma GCC poison SIG_UART_RECV -#pragma GCC poison SIG_USART_DATA -#pragma GCC poison SIG_UART_DATA -#pragma GCC poison SIG_USART_TRANS -#pragma GCC poison SIG_UART_TRANS -#pragma GCC poison SIG_ADC -#pragma GCC poison SIG_EEPROM_READY -#pragma GCC poison SIG_COMPARATOR -#pragma GCC poison SIG_2WIRE_SERIAL -#pragma GCC poison SIG_INTERRUPT2 -#pragma GCC poison SIG_OUTPUT_COMPARE0 -#pragma GCC poison SIG_SPM_READY - -#endif /* !defined(__AVR_LIBC_DEPRECATED_ENABLE__) */ - -#define SLEEP_MODE_IDLE (0x00<<4) -#define SLEEP_MODE_ADC (0x01<<4) -#define SLEEP_MODE_PWR_DOWN (0x02<<4) -#define SLEEP_MODE_PWR_SAVE (0x03<<4) -#define SLEEP_MODE_STANDBY (0x0A<<4) -#define SLEEP_MODE_EXT_STANDBY (0x0B<<4) - -#endif /* _AVR_IOM16_H_ */ diff --git a/arduino/hardware/tools/avr/avr/include/avr/iom161.h b/arduino/hardware/tools/avr/avr/include/avr/iom161.h deleted file mode 100644 index a5f6f9e..0000000 --- a/arduino/hardware/tools/avr/avr/include/avr/iom161.h +++ /dev/null @@ -1,726 +0,0 @@ -/* Copyright (c) 2002, Marek Michalkiewicz - All rights reserved. - - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - * Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - * Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in - the documentation and/or other materials provided with the - distribution. - - * Neither the name of the copyright holders nor the names of - contributors may be used to endorse or promote products derived - from this software without specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. */ - -/* $Id: iom161.h 2229 2011-03-05 17:00:18Z arcanum $ */ - -/* avr/iom161.h - definitions for ATmega161 */ - -#ifndef _AVR_IOM161_H_ -#define _AVR_IOM161_H_ 1 - -/* This file should only be included from , never directly. */ - -#ifndef _AVR_IO_H_ -# error "Include instead of this file." -#endif - -#ifndef _AVR_IOXXX_H_ -# define _AVR_IOXXX_H_ "iom161.h" -#else -# error "Attempt to include more than one file." -#endif - -/* I/O registers */ - -/* UART1 Baud Rate Register */ -#define UBRR1 _SFR_IO8(0x00) - -/* UART1 Control and Status Registers */ -#define UCSR1B _SFR_IO8(0x01) -#define UCSR1A _SFR_IO8(0x02) - -/* UART1 I/O Data Register */ -#define UDR1 _SFR_IO8(0x03) - -/* 0x04 reserved */ - -/* Input Pins, Port E */ -#define PINE _SFR_IO8(0x05) - -/* Data Direction Register, Port E */ -#define DDRE _SFR_IO8(0x06) - -/* Data Register, Port E */ -#define PORTE _SFR_IO8(0x07) - -/* Analog Comparator Control and Status Register */ -#define ACSR _SFR_IO8(0x08) - -/* UART0 Baud Rate Register */ -#define UBRR0 _SFR_IO8(0x09) - -/* UART0 Control and Status Registers */ -#define UCSR0B _SFR_IO8(0x0A) -#define UCSR0A _SFR_IO8(0x0B) - -/* UART0 I/O Data Register */ -#define UDR0 _SFR_IO8(0x0C) - -/* SPI Control Register */ -#define SPCR _SFR_IO8(0x0D) - -/* SPI Status Register */ -#define SPSR _SFR_IO8(0x0E) - -/* SPI I/O Data Register */ -#define SPDR _SFR_IO8(0x0F) - -/* Input Pins, Port D */ -#define PIND _SFR_IO8(0x10) - -/* Data Direction Register, Port D */ -#define DDRD _SFR_IO8(0x11) - -/* Data Register, Port D */ -#define PORTD _SFR_IO8(0x12) - -/* Input Pins, Port C */ -#define PINC _SFR_IO8(0x13) - -/* Data Direction Register, Port C */ -#define DDRC _SFR_IO8(0x14) - -/* Data Register, Port C */ -#define PORTC _SFR_IO8(0x15) - -/* Input Pins, Port B */ -#define PINB _SFR_IO8(0x16) - -/* Data Direction Register, Port B */ -#define DDRB _SFR_IO8(0x17) - -/* Data Register, Port B */ -#define PORTB _SFR_IO8(0x18) - -/* Input Pins, Port A */ -#define PINA _SFR_IO8(0x19) - -/* Data Direction Register, Port A */ -#define DDRA _SFR_IO8(0x1A) - -/* Data Register, Port A */ -#define PORTA _SFR_IO8(0x1B) - -/* EEPROM Control Register */ -#define EECR _SFR_IO8(0x1C) - -/* EEPROM Data Register */ -#define EEDR _SFR_IO8(0x1D) - -/* EEPROM Address Register */ -#define EEAR _SFR_IO16(0x1E) -#define EEARL _SFR_IO8(0x1E) -#define EEARH _SFR_IO8(0x1F) - -/* UART Baud Register HIgh */ -#define UBRRH _SFR_IO8(0x20) - -/* Watchdog Timer Control Register */ -#define WDTCR _SFR_IO8(0x21) - -/* Timer/Counter2 Output Compare Register */ -#define OCR2 _SFR_IO8(0x22) - -/* Timer/Counter2 (8-bit) */ -#define TCNT2 _SFR_IO8(0x23) - -/* Timer/Counter1 Input Capture Register */ -#define ICR1 _SFR_IO16(0x24) -#define ICR1L _SFR_IO8(0x24) -#define ICR1H _SFR_IO8(0x25) - -/* ASynchronous mode Status Register */ -#define ASSR _SFR_IO8(0x26) - -/* Timer/Counter2 Control Register */ -#define TCCR2 _SFR_IO8(0x27) - -/* Timer/Counter1 Output Compare RegisterB */ -#define OCR1B _SFR_IO16(0x28) -#define OCR1BL _SFR_IO8(0x28) -#define OCR1BH _SFR_IO8(0x29) - -/* Timer/Counter1 Output Compare RegisterA */ -#define OCR1A _SFR_IO16(0x2A) -#define OCR1AL _SFR_IO8(0x2A) -#define OCR1AH _SFR_IO8(0x2B) - -/* Timer/Counter1 */ -#define TCNT1 _SFR_IO16(0x2C) -#define TCNT1L _SFR_IO8(0x2C) -#define TCNT1H _SFR_IO8(0x2D) - -/* Timer/Counter1 Control Register B */ -#define TCCR1B _SFR_IO8(0x2E) - -/* Timer/Counter1 Control Register A */ -#define TCCR1A _SFR_IO8(0x2F) - -/* Special Function IO Register */ -#define SFIOR _SFR_IO8(0x30) - -/* Timer/Counter0 Output Compare Register */ -#define OCR0 _SFR_IO8(0x31) - -/* Timer/Counter0 (8-bit) */ -#define TCNT0 _SFR_IO8(0x32) - -/* Timer/Counter0 Control Register */ -#define TCCR0 _SFR_IO8(0x33) - -/* MCU general Status Register */ -#define MCUSR _SFR_IO8(0x34) - -/* MCU general Control Register */ -#define MCUCR _SFR_IO8(0x35) - -/* Extended MCU general Control Register */ -#define EMCUCR _SFR_IO8(0x36) - -/* Store Program Memory Control Register */ -#define SPMCR _SFR_IO8(0x37) - -/* Timer/Counter Interrupt Flag Register */ -#define TIFR _SFR_IO8(0x38) - -/* Timer/Counter Interrupt MaSK Register */ -#define TIMSK _SFR_IO8(0x39) - -/* General Interrupt Flag Register */ -#define GIFR _SFR_IO8(0x3A) - -/* General Interrupt MaSK register */ -#define GIMSK _SFR_IO8(0x3B) - -/* 0x3C reserved */ - -/* 0x3D..0x3E SP */ - -/* 0x3F SREG */ - -/* Interrupt vectors */ - -/* External Interrupt 0 */ -#define INT0_vect_num 1 -#define INT0_vect _VECTOR(1) -#define SIG_INTERRUPT0 _VECTOR(1) - -/* External Interrupt 1 */ -#define INT1_vect_num 2 -#define INT1_vect _VECTOR(2) -#define SIG_INTERRUPT1 _VECTOR(2) - -/* External Interrupt 2 */ -#define INT2_vect_num 3 -#define INT2_vect _VECTOR(3) -#define SIG_INTERRUPT2 _VECTOR(3) - -/* Timer/Counter2 Compare Match */ -#define TIMER2_COMP_vect_num 4 -#define TIMER2_COMP_vect _VECTOR(4) -#define SIG_OUTPUT_COMPARE2 _VECTOR(4) - -/* Timer/Counter2 Overflow */ -#define TIMER2_OVF_vect_num 5 -#define TIMER2_OVF_vect _VECTOR(5) -#define SIG_OVERFLOW2 _VECTOR(5) - -/* Timer/Counter1 Capture Event */ -#define TIMER1_CAPT_vect_num 6 -#define TIMER1_CAPT_vect _VECTOR(6) -#define SIG_INPUT_CAPTURE1 _VECTOR(6) - -/* Timer/Counter1 Compare Match A */ -#define TIMER1_COMPA_vect_num 7 -#define TIMER1_COMPA_vect _VECTOR(7) -#define SIG_OUTPUT_COMPARE1A _VECTOR(7) - -/* Timer/Counter1 Compare Match B */ -#define TIMER1_COMPB_vect_num 8 -#define TIMER1_COMPB_vect _VECTOR(8) -#define SIG_OUTPUT_COMPARE1B _VECTOR(8) - -/* Timer/Counter1 Overflow */ -#define TIMER1_OVF_vect_num 9 -#define TIMER1_OVF_vect _VECTOR(9) -#define SIG_OVERFLOW1 _VECTOR(9) - -/* Timer/Counter0 Compare Match */ -#define TIMER0_COMP_vect_num 10 -#define TIMER0_COMP_vect _VECTOR(10) -#define SIG_OUTPUT_COMPARE0 _VECTOR(10) - -/* Timer/Counter0 Overflow */ -#define TIMER0_OVF_vect_num 11 -#define TIMER0_OVF_vect _VECTOR(11) -#define SIG_OVERFLOW0 _VECTOR(11) - -/* Serial Transfer Complete */ -#define SPI_STC_vect_num 12 -#define SPI_STC_vect _VECTOR(12) -#define SIG_SPI _VECTOR(12) - -/* UART0, Rx Complete */ -#define UART0_RX_vect_num 13 -#define UART0_RX_vect _VECTOR(13) -#define SIG_UART0_RECV _VECTOR(13) - -/* UART1, Rx Complete */ -#define UART1_RX_vect_num 14 -#define UART1_RX_vect _VECTOR(14) -#define SIG_UART1_RECV _VECTOR(14) - -/* UART0 Data Register Empty */ -#define UART0_UDRE_vect_num 15 -#define UART0_UDRE_vect _VECTOR(15) -#define SIG_UART0_DATA _VECTOR(15) - -/* UART1 Data Register Empty */ -#define UART1_UDRE_vect_num 16 -#define UART1_UDRE_vect _VECTOR(16) -#define SIG_UART1_DATA _VECTOR(16) - -/* UART0, Tx Complete */ -#define UART0_TX_vect_num 17 -#define UART0_TX_vect _VECTOR(17) -#define SIG_UART0_TRANS _VECTOR(17) - -/* UART1, Tx Complete */ -#define UART1_TX_vect_num 18 -#define UART1_TX_vect _VECTOR(18) -#define SIG_UART1_TRANS _VECTOR(18) - -/* EEPROM Ready */ -#define EE_RDY_vect_num 19 -#define EE_RDY_vect _VECTOR(19) -#define SIG_EEPROM_READY _VECTOR(19) - -/* Analog Comparator */ -#define ANA_COMP_vect_num 20 -#define ANA_COMP_vect _VECTOR(20) -#define SIG_COMPARATOR _VECTOR(20) - -#define _VECTORS_SIZE 84 - -/* Bit numbers */ - -/* GIMSK */ -#define INT1 7 -#define INT0 6 -#define INT2 5 - -/* GIFR */ -#define INTF1 7 -#define INTF0 6 -#define INTF2 5 - -/* TIMSK */ -#define TOIE1 7 -#define OCIE1A 6 -#define OCIE1B 5 -#define TOIE2 4 -#define TICIE1 3 -#define OCIE2 2 -#define TOIE0 1 -#define OCIE0 0 - -/* TIFR */ -#define TOV1 7 -#define OCF1A 6 -#define OCF1B 5 -#define TOV2 4 -#define ICF1 3 -#define OCF2 2 -#define TOV0 1 -#define OCF0 0 - -/* MCUCR */ -#define SRE 7 -#define SRW10 6 -#define SE 5 -#define SM1 4 -#define ISC11 3 -#define ISC10 2 -#define ISC01 1 -#define ISC00 0 - -/* EMCUCR */ -#define SM0 7 -#define SRL2 6 -#define SRL1 5 -#define SRL0 4 -#define SRW01 3 -#define SRW00 2 -#define SRW11 1 -#define ISC2 0 - -/* SPMCR */ -#define BLBSET 3 -#define PGWRT 2 -#define PGERS 1 -#define SPMEN 0 - -/* SFIOR */ -#define PSR2 1 -#define PSR10 0 - -/* TCCR0 */ -#define FOC0 7 -#define PWM0 6 -#define COM01 5 -#define COM00 4 -#define CTC0 3 -#define CS02 2 -#define CS01 1 -#define CS00 0 - -/* TCCR2 */ -#define FOC2 7 -#define PWM2 6 -#define COM21 5 -#define COM20 4 -#define CTC2 3 -#define CS22 2 -#define CS21 1 -#define CS20 0 - -/* ASSR */ -#define AS2 3 -#define TCN2UB 2 -#define OCR2UB 1 -#define TCR2UB 0 - -/* TCCR1A */ -#define COM1A1 7 -#define COM1A0 6 -#define COM1B1 5 -#define COM1B0 4 -#define FOC1A 3 -#define FOC1B 2 -#define PWM11 1 -#define PWM10 0 - -/* TCCR1B */ -#define ICNC1 7 -#define ICES1 6 -#define CTC1 3 -#define CS12 2 -#define CS11 1 -#define CS10 0 - -/* WDTCR */ -#define WDTOE 4 -#define WDE 3 -#define WDP2 2 -#define WDP1 1 -#define WDP0 0 - -/* PORTA */ -#define PA7 7 -#define PA6 6 -#define PA5 5 -#define PA4 4 -#define PA3 3 -#define PA2 2 -#define PA1 1 -#define PA0 0 - -/* DDRA */ -#define DDA7 7 -#define DDA6 6 -#define DDA5 5 -#define DDA4 4 -#define DDA3 3 -#define DDA2 2 -#define DDA1 1 -#define DDA0 0 - -/* PINA */ -#define PINA7 7 -#define PINA6 6 -#define PINA5 5 -#define PINA4 4 -#define PINA3 3 -#define PINA2 2 -#define PINA1 1 -#define PINA0 0 - -/* - PB7 = SCK - PB6 = MISO - PB5 = MOSI - PB4 = SS# - PB3 = TXD1 / AIN1 - PB2 = RXD1 / AIN0 - PB1 = OC2 / T1 - PB0 = OC0 / T0 - */ - -/* PORTB */ -#define PB7 7 -#define PB6 6 -#define PB5 5 -#define PB4 4 -#define PB3 3 -#define PB2 2 -#define PB1 1 -#define PB0 0 - -/* DDRB */ -#define DDB7 7 -#define DDB6 6 -#define DDB5 5 -#define DDB4 4 -#define DDB3 3 -#define DDB2 2 -#define DDB1 1 -#define DDB0 0 - -/* PINB */ -#define PINB7 7 -#define PINB6 6 -#define PINB5 5 -#define PINB4 4 -#define PINB3 3 -#define PINB2 2 -#define PINB1 1 -#define PINB0 0 - -/* PORTC */ -#define PC7 7 -#define PC6 6 -#define PC5 5 -#define PC4 4 -#define PC3 3 -#define PC2 2 -#define PC1 1 -#define PC0 0 - -/* DDRC */ -#define DDC7 7 -#define DDC6 6 -#define DDC5 5 -#define DDC4 4 -#define DDC3 3 -#define DDC2 2 -#define DDC1 1 -#define DDC0 0 - -/* PINC */ -#define PINC7 7 -#define PINC6 6 -#define PINC5 5 -#define PINC4 4 -#define PINC3 3 -#define PINC2 2 -#define PINC1 1 -#define PINC0 0 - -/* - PD7 = RD# - PD6 = WR# - PD5 = TOSC2 / OC1A - PD4 = TOSC1 - PD3 = INT1 - PD2 = INT0 - PD1 = TXD0 - PD0 = RXD0 - */ - -/* PORTD */ -#define PD7 7 -#define PD6 6 -#define PD5 5 -#define PD4 4 -#define PD3 3 -#define PD2 2 -#define PD1 1 -#define PD0 0 - -/* DDRD */ -#define DDD7 7 -#define DDD6 6 -#define DDD5 5 -#define DDD4 4 -#define DDD3 3 -#define DDD2 2 -#define DDD1 1 -#define DDD0 0 - -/* PIND */ -#define PIND7 7 -#define PIND6 6 -#define PIND5 5 -#define PIND4 4 -#define PIND3 3 -#define PIND2 2 -#define PIND1 1 -#define PIND0 0 - -/* - PE2 = ALE - PE1 = OC1B - PE0 = ICP / INT2 - */ - -/* PORTE */ -#define PE2 2 -#define PE1 1 -#define PE0 0 - -/* DDRE */ -#define DDE2 2 -#define DDE1 1 -#define DDE0 0 - -/* PINE */ -#define PINE2 2 -#define PINE1 1 -#define PINE0 0 - -/* SPSR */ -#define SPIF 7 -#define WCOL 6 -#define SPI2X 0 - -/* SPCR */ -#define SPIE 7 -#define SPE 6 -#define DORD 5 -#define MSTR 4 -#define CPOL 3 -#define CPHA 2 -#define SPR1 1 -#define SPR0 0 - -/* UCSR0A, UCSR1A */ -#define RXC 7 -#define TXC 6 -#define UDRE 5 -#define FE 4 -#define DOR 3 -#define U2X 1 -#define MPCM 0 - -/* UCSR0B, UCSR1B */ -#define RXCIE 7 -#define TXCIE 6 -#define UDRIE 5 -#define RXEN 4 -#define TXEN 3 -#define CHR9 2 -#define RXB8 1 -#define TXB8 0 - -/* ACSR */ -#define ACD 7 -#define AINBG 6 -#define ACO 5 -#define ACI 4 -#define ACIE 3 -#define ACIC 2 -#define ACIS1 1 -#define ACIS0 0 - -/* EEPROM Control Register */ -#define EERIE 3 -#define EEMWE 2 -#define EEWE 1 -#define EERE 0 - -/* Constants */ -#define SPM_PAGESIZE 128 -#define RAMSTART 0x60 -#define RAMEND 0x45F -#define XRAMEND 0xFFFF -#define E2END 0x1FF -#define E2PAGESIZE 0 -#define FLASHEND 0x3FFF - - -/* Fuses */ - -#define FUSE_MEMORY_SIZE 1 - -/* Fuse Byte */ -#define FUSE_CKSEL0 (unsigned char)~_BV(0) -#define FUSE_CKSEL1 (unsigned char)~_BV(1) -#define FUSE_CKSEL2 (unsigned char)~_BV(2) -#define FUSE_SUT (unsigned char)~_BV(4) -#define FUSE_SPIEN (unsigned char)~_BV(5) -#define FUSE_BOOTRST (unsigned char)~_BV(6) -#define FUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_SPIEN) - - -/* Lock Bits */ -#define __LOCK_BITS_EXIST -#define __BOOT_LOCK_BITS_0_EXIST -#define __BOOT_LOCK_BITS_1_EXIST - - -/* Signature */ -#define SIGNATURE_0 0x1E -#define SIGNATURE_1 0x94 -#define SIGNATURE_2 0x01 - -#define SLEEP_MODE_IDLE 0 -#define SLEEP_MODE_PWR_DOWN 1 -#define SLEEP_MODE_PWR_SAVE 2 - -/* Deprecated items */ -#if !defined(__AVR_LIBC_DEPRECATED_ENABLE__) - -#pragma GCC system_header - -#pragma GCC poison SIG_INTERRUPT0 -#pragma GCC poison SIG_INTERRUPT1 -#pragma GCC poison SIG_INTERRUPT2 -#pragma GCC poison SIG_OUTPUT_COMPARE2 -#pragma GCC poison SIG_OVERFLOW2 -#pragma GCC poison SIG_INPUT_CAPTURE1 -#pragma GCC poison SIG_OUTPUT_COMPARE1A -#pragma GCC poison SIG_OUTPUT_COMPARE1B -#pragma GCC poison SIG_OVERFLOW1 -#pragma GCC poison SIG_OUTPUT_COMPARE0 -#pragma GCC poison SIG_OVERFLOW0 -#pragma GCC poison SIG_SPI -#pragma GCC poison SIG_UART0_RECV -#pragma GCC poison SIG_UART1_RECV -#pragma GCC poison SIG_UART0_DATA -#pragma GCC poison SIG_UART1_DATA -#pragma GCC poison SIG_UART0_TRANS -#pragma GCC poison SIG_UART1_TRANS -#pragma GCC poison SIG_EEPROM_READY -#pragma GCC poison SIG_COMPARATOR - -#endif /* !defined(__AVR_LIBC_DEPRECATED_ENABLE__) */ - - -#endif /* _AVR_IOM161_H_ */ diff --git a/arduino/hardware/tools/avr/avr/include/avr/iom162.h b/arduino/hardware/tools/avr/avr/include/avr/iom162.h deleted file mode 100644 index 08533c9..0000000 --- a/arduino/hardware/tools/avr/avr/include/avr/iom162.h +++ /dev/null @@ -1,1022 +0,0 @@ -/* Copyright (c) 2002, Nils Kristian Strom - All rights reserved. - - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - * Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - * Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in - the documentation and/or other materials provided with the - distribution. - - * Neither the name of the copyright holders nor the names of - contributors may be used to endorse or promote products derived - from this software without specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. */ - -/* $Id: iom162.h 2230 2011-03-06 02:42:04Z arcanum $ */ - -/* iom162.h - definitions for ATmega162 */ - -#ifndef _AVR_IOM162_H_ -#define _AVR_IOM162_H_ 1 - -/* This file should only be included from , never directly. */ - -#ifndef _AVR_IO_H_ -# error "Include instead of this file." -#endif - -#ifndef _AVR_IOXXX_H_ -# define _AVR_IOXXX_H_ "iom162.h" -#else -# error "Attempt to include more than one file." -#endif - -/* Memory mapped I/O registers */ - -/* Timer/Counter3 Control Register A */ -#define TCCR3A _SFR_MEM8(0x8B) - -/* Timer/Counter3 Control Register B */ -#define TCCR3B _SFR_MEM8(0x8A) - -/* Timer/Counter3 - Counter Register */ -#define TCNT3H _SFR_MEM8(0x89) -#define TCNT3L _SFR_MEM8(0x88) -#define TCNT3 _SFR_MEM16(0x88) - -/* Timer/Counter3 - Output Compare Register A */ -#define OCR3AH _SFR_MEM8(0x87) -#define OCR3AL _SFR_MEM8(0x86) -#define OCR3A _SFR_MEM16(0x86) - -/* Timer/Counter3 - Output Compare Register B */ -#define OCR3BH _SFR_MEM8(0x85) -#define OCR3BL _SFR_MEM8(0x84) -#define OCR3B _SFR_MEM16(0x84) - -/* Timer/Counter3 - Input Capture Register */ -#define ICR3H _SFR_MEM8(0x81) -#define ICR3L _SFR_MEM8(0x80) -#define ICR3 _SFR_MEM16(0x80) - -/* Extended Timer/Counter Interrupt Mask */ -#define ETIMSK _SFR_MEM8(0x7D) - -/* Extended Timer/Counter Interrupt Flag Register */ -#define ETIFR _SFR_MEM8(0x7C) - -/* Pin Change Mask Register 1 */ -#define PCMSK1 _SFR_MEM8(0x6C) - -/* Pin Change Mask Register 0 */ -#define PCMSK0 _SFR_MEM8(0x6B) - -/* Clock PRescale */ -#define CLKPR _SFR_MEM8(0x61) - - -/* Standard I/O registers */ - -/* 0x3F SREG */ -/* 0x3D..0x3E SP */ -#define UBRR1H _SFR_IO8(0x3C) /* USART 1 Baud Rate Register High Byte, Shared with UCSR1C */ -#define UCSR1C _SFR_IO8(0x3C) /* USART 1 Control and Status Register, Shared with UBRR1H */ -#define GICR _SFR_IO8(0x3B) /* General Interrupt Control Register */ -#define GIFR _SFR_IO8(0x3A) /* General Interrupt Flag Register */ -#define TIMSK _SFR_IO8(0x39) /* Timer Interrupt Mask */ -#define TIFR _SFR_IO8(0x38) /* Timer Interrupt Flag Register */ -#define SPMCR _SFR_IO8(0x37) /* Store Program Memory Control Register */ -#define EMCUCR _SFR_IO8(0x36) /* Extended MCU Control Register */ -#define MCUCR _SFR_IO8(0x35) /* MCU Control Register */ -#define MCUCSR _SFR_IO8(0x34) /* MCU Control and Status Register */ -#define TCCR0 _SFR_IO8(0x33) /* Timer/Counter 0 Control Register */ -#define TCNT0 _SFR_IO8(0x32) /* TImer/Counter 0 */ -#define OCR0 _SFR_IO8(0x31) /* Output Compare Register 0 */ -#define SFIOR _SFR_IO8(0x30) /* Special Function I/O Register */ -#define TCCR1A _SFR_IO8(0x2F) /* Timer/Counter 1 Control Register A */ -#define TCCR1B _SFR_IO8(0x2E) /* Timer/Counter 1 Control Register A */ -#define TCNT1H _SFR_IO8(0x2D) /* Timer/Counter 1 High Byte */ -#define TCNT1L _SFR_IO8(0x2C) /* Timer/Counter 1 Low Byte */ -#define TCNT1 _SFR_IO16(0x2C) /* Timer/Counter 1 */ -#define OCR1AH _SFR_IO8(0x2B) /* Timer/Counter 1 Output Compare Register A High Byte */ -#define OCR1AL _SFR_IO8(0x2A) /* Timer/Counter 1 Output Compare Register A Low Byte */ -#define OCR1A _SFR_IO16(0x2A) /* Timer/Counter 1 Output Compare Register A */ -#define OCR1BH _SFR_IO8(0x29) /* Timer/Counter 1 Output Compare Register B High Byte */ -#define OCR1BL _SFR_IO8(0x28) /* Timer/Counter 1 Output Compare Register B Low Byte */ -#define OCR1B _SFR_IO16(0x28) /* Timer/Counter 1 Output Compare Register B */ -#define TCCR2 _SFR_IO8(0x27) /* Timer/Counter 2 Control Register */ -#define ASSR _SFR_IO8(0x26) /* Asynchronous Status Register */ -#define ICR1H _SFR_IO8(0x25) /* Input Capture Register 1 High Byte */ -#define ICR1L _SFR_IO8(0x24) /* Input Capture Register 1 Low Byte */ -#define ICR1 _SFR_IO16(0x24) /* Input Capture Register 1 */ -#define TCNT2 _SFR_IO8(0x23) /* Timer/Counter 2 */ -#define OCR2 _SFR_IO8(0x22) /* Timer/Counter 2 Output Compare Register */ -#define WDTCR _SFR_IO8(0x21) /* Watchdow Timer Control Register */ -#define UBRR0H _SFR_IO8(0x20) /* USART 0 Baud-Rate Register High Byte, Shared with UCSR0C */ -#define UCSR0C _SFR_IO8(0x20) /* USART 0 Control and Status Register C, Shared with UBRR0H */ -#define EEARH _SFR_IO8(0x1F) /* EEPROM Address Register High Byte */ -#define EEARL _SFR_IO8(0x1E) /* EEPROM Address Register Low Byte */ -#define EEAR _SFR_IO16(0x1E) /* EEPROM Address Register */ -#define EEDR _SFR_IO8(0x1D) /* EEPROM Data Register */ -#define EECR _SFR_IO8(0x1C) /* EEPROM Control Register */ -#define PORTA _SFR_IO8(0x1B) /* Port A */ -#define DDRA _SFR_IO8(0x1A) /* Port A Data Direction Register */ -#define PINA _SFR_IO8(0x19) /* Port A Pin Register */ -#define PORTB _SFR_IO8(0x18) /* Port B */ -#define DDRB _SFR_IO8(0x17) /* Port B Data Direction Register */ -#define PINB _SFR_IO8(0x16) /* Port B Pin Register */ -#define PORTC _SFR_IO8(0x15) /* Port C */ -#define DDRC _SFR_IO8(0x14) /* Port C Data Direction Register */ -#define PINC _SFR_IO8(0x13) /* Port C Pin Register */ -#define PORTD _SFR_IO8(0x12) /* Port D */ -#define DDRD _SFR_IO8(0x11) /* Port D Data Direction Register */ -#define PIND _SFR_IO8(0x10) /* Port D Pin Register */ -#define SPDR _SFR_IO8(0x0F) /* SPI Data Register */ -#define SPSR _SFR_IO8(0x0E) /* SPI Status Register */ -#define SPCR _SFR_IO8(0x0D) /* SPI Control Register */ -#define UDR0 _SFR_IO8(0x0C) /* USART 0 Data Register */ -#define UCSR0A _SFR_IO8(0x0B) /* USART 0 Control and Status Register A */ -#define UCSR0B _SFR_IO8(0x0A) /* USART 0 Control and Status Register B */ -#define UBRR0L _SFR_IO8(0x09) /* USART 0 Baud-Rate Register Low Byte */ -#define ACSR _SFR_IO8(0x08) /* Analog Comparator Status Register */ -#define PORTE _SFR_IO8(0x07) /* Port E */ -#define DDRE _SFR_IO8(0x06) /* Port E Data Direction Register */ -#define PINE _SFR_IO8(0x05) /* Port E Pin Register */ -#define OSCCAL _SFR_IO8(0x04) /* Oscillator Calibration, Shared with OCDR */ -#define OCDR _SFR_IO8(0x04) /* On-Chip Debug Register, Shared with OSCCAL */ -#define UDR1 _SFR_IO8(0x03) /* USART 1 Data Register */ -#define UCSR1A _SFR_IO8(0x02) /* USART 1 Control and Status Register A */ -#define UCSR1B _SFR_IO8(0x01) /* USART 1 Control and Status Register B */ -#define UBRR1L _SFR_IO8(0x00) /* USART 0 Baud Rate Register High Byte */ - - -/* Interrupt vectors (byte addresses) */ - -/* External Interrupt Request 0 */ -#define INT0_vect_num 1 -#define INT0_vect _VECTOR(1) -#define SIG_INTERRUPT0 _VECTOR(1) - -/* External Interrupt Request 1 */ -#define INT1_vect_num 2 -#define INT1_vect _VECTOR(2) -#define SIG_INTERRUPT1 _VECTOR(2) - -/* External Interrupt Request 2 */ -#define INT2_vect_num 3 -#define INT2_vect _VECTOR(3) -#define SIG_INTERRUPT2 _VECTOR(3) - -/* Pin Change Interrupt Request 0 */ -#define PCINT0_vect_num 4 -#define PCINT0_vect _VECTOR(4) -#define SIG_PIN_CHANGE0 _VECTOR(4) - -/* Pin Change Interrupt Request 1 */ -#define PCINT1_vect_num 5 -#define PCINT1_vect _VECTOR(5) -#define SIG_PIN_CHANGE1 _VECTOR(5) - -/* Timer/Counter3 Capture Event */ -#define TIMER3_CAPT_vect_num 6 -#define TIMER3_CAPT_vect _VECTOR(6) -#define SIG_INPUT_CAPTURE3 _VECTOR(6) - -/* Timer/Counter3 Compare Match A */ -#define TIMER3_COMPA_vect_num 7 -#define TIMER3_COMPA_vect _VECTOR(7) -#define SIG_OUTPUT_COMPARE3A _VECTOR(7) - -/* Timer/Counter3 Compare Match B */ -#define TIMER3_COMPB_vect_num 8 -#define TIMER3_COMPB_vect _VECTOR(8) -#define SIG_OUTPUT_COMPARE3B _VECTOR(8) - -/* Timer/Counter3 Overflow */ -#define TIMER3_OVF_vect_num 9 -#define TIMER3_OVF_vect _VECTOR(9) -#define SIG_OVERFLOW3 _VECTOR(9) - -/* Timer/Counter2 Compare Match */ -#define TIMER2_COMP_vect_num 10 -#define TIMER2_COMP_vect _VECTOR(10) -#define SIG_OUTPUT_COMPARE2 _VECTOR(10) - -/* Timer/Counter2 Overflow */ -#define TIMER2_OVF_vect_num 11 -#define TIMER2_OVF_vect _VECTOR(11) -#define SIG_OVERFLOW2 _VECTOR(11) - -/* Timer/Counter1 Capture Event */ -#define TIMER1_CAPT_vect_num 12 -#define TIMER1_CAPT_vect _VECTOR(12) -#define SIG_INPUT_CAPTURE1 _VECTOR(12) - -/* Timer/Counter1 Compare Match A */ -#define TIMER1_COMPA_vect_num 13 -#define TIMER1_COMPA_vect _VECTOR(13) -#define SIG_OUTPUT_COMPARE1A _VECTOR(13) - -/* Timer/Counter Compare Match B */ -#define TIMER1_COMPB_vect_num 14 -#define TIMER1_COMPB_vect _VECTOR(14) -#define SIG_OUTPUT_COMPARE1B _VECTOR(14) - -/* Timer/Counter1 Overflow */ -#define TIMER1_OVF_vect_num 15 -#define TIMER1_OVF_vect _VECTOR(15) -#define SIG_OVERFLOW1 _VECTOR(15) - -/* Timer/Counter0 Compare Match */ -#define TIMER0_COMP_vect_num 16 -#define TIMER0_COMP_vect _VECTOR(16) -#define SIG_OUTPUT_COMPARE0 _VECTOR(16) - -/* Timer/Counter0 Overflow */ -#define TIMER0_OVF_vect_num 17 -#define TIMER0_OVF_vect _VECTOR(17) -#define SIG_OVERFLOW0 _VECTOR(17) - -/* SPI Serial Transfer Complete */ -#define SPI_STC_vect_num 18 -#define SPI_STC_vect _VECTOR(18) -#define SIG_SPI _VECTOR(18) - -/* USART0, Rx Complete */ -#define USART0_RXC_vect_num 19 -#define USART0_RXC_vect _VECTOR(19) -#define SIG_USART0_RECV _VECTOR(19) - -/* USART1, Rx Complete */ -#define USART1_RXC_vect_num 20 -#define USART1_RXC_vect _VECTOR(20) -#define SIG_USART1_RECV _VECTOR(20) - -/* USART0 Data register Empty */ -#define USART0_UDRE_vect_num 21 -#define USART0_UDRE_vect _VECTOR(21) -#define SIG_USART0_DATA _VECTOR(21) - -/* USART1, Data register Empty */ -#define USART1_UDRE_vect_num 22 -#define USART1_UDRE_vect _VECTOR(22) -#define SIG_USART1_DATA _VECTOR(22) - -/* USART0, Tx Complete */ -#define USART0_TXC_vect_num 23 -#define USART0_TXC_vect _VECTOR(23) -#define SIG_USART0_TRANS _VECTOR(23) - -/* USART1, Tx Complete */ -#define USART1_TXC_vect_num 24 -#define USART1_TXC_vect _VECTOR(24) -#define SIG_USART1_TRANS _VECTOR(24) - -/* EEPROM Ready */ -#define EE_RDY_vect_num 25 -#define EE_RDY_vect _VECTOR(25) -#define SIG_EEPROM_READY _VECTOR(25) - -/* Analog Comparator */ -#define ANA_COMP_vect_num 26 -#define ANA_COMP_vect _VECTOR(26) -#define SIG_COMPARATOR _VECTOR(26) - -/* Store Program Memory Read */ -#define SPM_RDY_vect_num 27 -#define SPM_RDY_vect _VECTOR(27) -#define SIG_SPM_READY _VECTOR(27) - -#define _VECTORS_SIZE 112 /* = (num vec+1) * 4 */ - - - - - -/* TCCR3B bit definitions, memory mapped I/O */ - -#define ICNC3 7 -#define ICES3 6 -#define WGM33 4 -#define WGM32 3 -#define CS32 2 -#define CS31 1 -#define CS30 0 - - - -/* TCCR3A bit definitions, memory mapped I/O */ - -#define COM3A1 7 -#define COM3A0 6 -#define COM3B1 5 -#define COM3B0 4 -#define FOC3A 3 -#define FOC3B 2 -#define WGM31 1 -#define WGM30 0 - - - -/* ETIMSK bit definitions, memory mapped I/O */ - -#define TICIE3 5 -#define OCIE3A 4 -#define OCIE3B 3 -#define TOIE3 2 - - - -/* ETIFR bit definitions, memory mapped I/O */ - -#define ICF3 5 -#define OCF3A 4 -#define OCF3B 3 -#define TOV3 2 - - - -/* PCMSK1 bit definitions, memory mapped I/O */ -#define PCINT15 7 -#define PCINT14 6 -#define PCINT13 5 -#define PCINT12 4 -#define PCINT11 3 -#define PCINT10 2 -#define PCINT9 1 -#define PCINT8 0 - - - -/* PCMSK0 bit definitions, memory mapped I/O */ - -#define PCINT7 7 -#define PCINT6 6 -#define PCINT5 5 -#define PCINT4 4 -#define PCINT3 3 -#define PCINT2 2 -#define PCINT1 1 -#define PCINT0 0 - - - -/* CLKPR bit definitions, memory mapped I/O */ - -#define CLKPCE 7 -#define CLKPS3 3 -#define CLKPS2 2 -#define CLKPS1 1 -#define CLKPS0 0 - - - -/* SPH bit definitions */ - -#define SP15 15 -#define SP14 14 -#define SP13 13 -#define SP12 12 -#define SP11 11 -#define SP10 10 -#define SP9 9 -#define SP8 8 - - - -/* SPL bit definitions */ - -#define SP7 7 -#define SP6 6 -#define SP5 5 -#define SP4 4 -#define SP3 3 -#define SP2 2 -#define SP1 1 -#define SP0 0 - - - -/* UBRR1H bit definitions */ - -#define URSEL1 7 -#define UBRR111 3 -#define UBRR110 2 -#define UBRR19 1 -#define UBRR18 0 - - - -/* UCSR1C bit definitions */ - -#define URSEL1 7 -#define UMSEL1 6 -#define UPM11 5 -#define UPM10 4 -#define USBS1 3 -#define UCSZ11 2 -#define UCSZ10 1 -#define UCPOL1 0 - - - -/* GICR bit definitions */ - -#define INT1 7 -#define INT0 6 -#define INT2 5 -#define PCIE1 4 -#define PCIE0 3 -#define IVSEL 1 -#define IVCE 0 - - - -/* GIFR bit definitions */ - -#define INTF1 7 -#define INTF0 6 -#define INTF2 5 -#define PCIF1 4 -#define PCIF0 3 - - - -/* TIMSK bit definitions */ - -#define TOIE1 7 -#define OCIE1A 6 -#define OCIE1B 5 -#define OCIE2 4 -#define TICIE1 3 -#define TOIE2 2 -#define TOIE0 1 -#define OCIE0 0 - - - -/* TIFR bit definitions */ - -#define TOV1 7 -#define OCF1A 6 -#define OCF1B 5 -#define OCF2 4 -#define ICF1 3 -#define TOV2 2 -#define TOV0 1 -#define OCF0 0 - - - -/* SPMCR bit definitions */ - -#define SPMIE 7 -#define RWWSB 6 -#define RWWSRE 4 -#define BLBSET 3 -#define PGWRT 2 -#define PGERS 1 -#define SPMEN 0 - - - -/* EMCUCR bit definitions */ - -#define SM0 7 -#define SRL2 6 -#define SRL1 5 -#define SRL0 4 -#define SRW01 3 -#define SRW00 2 -#define SRW11 1 -#define ISC2 0 - - - -/* MCUCR bit definitions */ - -#define SRE 7 -#define SRW10 6 -#define SE 5 -#define SM1 4 -#define ISC11 3 -#define ISC10 2 -#define ISC01 1 -#define ISC00 0 - - - -/* MCUCSR bit definitions */ - -#define JTD 7 -#define SM2 5 -#define JTRF 4 -#define WDRF 3 -#define BORF 2 -#define EXTRF 1 -#define PORF 0 - - - -/* TCCR0 bit definitions */ - -#define FOC0 7 -#define WGM00 6 -#define COM01 5 -#define COM00 4 -#define WGM01 3 -#define CS02 2 -#define CS01 1 -#define CS00 0 - - - -/* SFIOR bit definitions */ - -#define TSM 7 -#define XMBK 6 -#define XMM2 5 -#define XMM1 4 -#define XMM0 3 -#define PUD 2 -#define PSR2 1 -#define PSR310 0 - - - -/* TCCR1A bit definitions */ - -#define COM1A1 7 -#define COM1A0 6 -#define COM1B1 5 -#define COM1B0 4 -#define FOC1A 3 -#define FOC1B 2 -#define WGM11 1 -#define WGM10 0 - - - - -/* TCCR1B bit definitions */ - -#define ICNC1 7 /* Input Capture Noise Canceler */ -#define ICES1 6 /* Input Capture Edge Select */ -#define WGM13 4 /* Waveform Generation Mode 3 */ -#define WGM12 3 /* Waveform Generation Mode 2 */ -#define CS12 2 /* Clock Select 2 */ -#define CS11 1 /* Clock Select 1 */ -#define CS10 0 /* Clock Select 0 */ - - - -/* TCCR2 bit definitions */ - -#define FOC2 7 -#define WGM20 6 -#define COM21 5 -#define COM20 4 -#define WGM21 3 -#define CS22 2 -#define CS21 1 -#define CS20 0 - - - -/* ASSR bit definitions */ - -#define AS2 3 -#define TCN2UB 2 -#define TCON2UB 2 /* Kept for backwards compatibility. */ -#define OCR2UB 1 -#define TCR2UB 0 - - - -/* WDTCR bit definitions */ - -#define WDCE 4 -#define WDE 3 -#define WDP2 2 -#define WDP1 1 -#define WDP0 0 - - - -/* UBRR0H bif definitions */ - -#define URSEL0 7 -#define UBRR011 3 -#define UBRR010 2 -#define UBRR09 1 -#define UBRR08 0 - - - -/* UCSR0C bit definitions */ - -#define URSEL0 7 -#define UMSEL0 6 -#define UPM01 5 -#define UPM00 4 -#define USBS0 3 -#define UCSZ01 2 -#define UCSZ00 1 -#define UCPOL0 0 - - - -/* EEARH bit definitions */ - -#define EEAR8 0 - - - -/* EECR bit definitions */ - -#define EERIE 3 -#define EEMWE 2 -#define EEWE 1 -#define EERE 0 - - - -/* PORTA bit definitions */ - -#define PA7 7 -#define PA6 6 -#define PA5 5 -#define PA4 4 -#define PA3 3 -#define PA2 2 -#define PA1 1 -#define PA0 0 - - - -/* DDRA bit definitions */ - -#define DDA7 7 -#define DDA6 6 -#define DDA5 5 -#define DDA4 4 -#define DDA3 3 -#define DDA2 2 -#define DDA1 1 -#define DDA0 0 - - - -/* PINA bit definitions */ - -#define PINA7 7 -#define PINA6 6 -#define PINA5 5 -#define PINA4 4 -#define PINA3 3 -#define PINA2 2 -#define PINA1 1 -#define PINA0 0 - - -/* PORTB bit definitions */ - -#define PB7 7 -#define PB6 6 -#define PB5 5 -#define PB4 4 -#define PB3 3 -#define PB2 2 -#define PB1 1 -#define PB0 0 - - - -/* DDRB bit definitions */ - -#define DDB7 7 -#define DDB6 6 -#define DDB5 5 -#define DDB4 4 -#define DDB3 3 -#define DDB2 2 -#define DDB1 1 -#define DDB0 0 - - - -/* PINB bit definitions */ - -#define PINB7 7 -#define PINB6 6 -#define PINB5 5 -#define PINB4 4 -#define PINB3 3 -#define PINB2 2 -#define PINB1 1 -#define PINB0 0 - - - -/* PORTC bit definitions */ - -#define PC7 7 -#define PC6 6 -#define PC5 5 -#define PC4 4 -#define PC3 3 -#define PC2 2 -#define PC1 1 -#define PC0 0 - - - -/* DDRC bit definitions */ - -#define DDC7 7 -#define DDC6 6 -#define DDC5 5 -#define DDC4 4 -#define DDC3 3 -#define DDC2 2 -#define DDC1 1 -#define DDC0 0 - - - -/* PINC bit definitions */ - -#define PINC7 7 -#define PINC6 6 -#define PINC5 5 -#define PINC4 4 -#define PINC3 3 -#define PINC2 2 -#define PINC1 1 -#define PINC0 0 - - - -/* PORTD bit definitions */ - -#define PD7 7 -#define PD6 6 -#define PD5 5 -#define PD4 4 -#define PD3 3 -#define PD2 2 -#define PD1 1 -#define PD0 0 - - - -/* DDRD bit definitions */ - -#define DDD7 7 -#define DDD6 6 -#define DDD5 5 -#define DDD4 4 -#define DDD3 3 -#define DDD2 2 -#define DDD1 1 -#define DDD0 0 - - - -/* PIND bit definitions */ - -#define PIND7 7 -#define PIND6 6 -#define PIND5 5 -#define PIND4 4 -#define PIND3 3 -#define PIND2 2 -#define PIND1 1 -#define PIND0 0 - - - -/* SPSR bit definitions */ - -#define SPIF 7 -#define WCOL 6 -#define SPI2X 0 - - - -/* SPCR bit definitions */ - -#define SPIE 7 -#define SPE 6 -#define DORD 5 -#define MSTR 4 -#define CPOL 3 -#define CPHA 2 -#define SPR1 1 -#define SPR0 0 - - - -/* UCSR0A bit definitions */ - -#define RXC0 7 -#define TXC0 6 -#define UDRE0 5 -#define FE0 4 -#define DOR0 3 -#define UPE0 2 -#define U2X0 1 -#define MPCM0 0 - - - -/* UCSR0B bit definitions */ - -#define RXCIE0 7 -#define TXCIE0 6 -#define UDRIE0 5 -#define RXEN0 4 -#define TXEN0 3 -#define UCSZ02 2 -#define RXB80 1 -#define TXB80 0 - - - -/* ACSR bit definitions */ - -#define ACD 7 -#define ACBG 6 -#define ACO 5 -#define ACI 4 -#define ACIE 3 -#define ACIC 2 -#define ACIS1 1 -#define ACIS0 0 - - - -/* PORTE bit definitions */ - -#define PE2 2 -#define PE1 1 -#define PE0 0 - - - -/* DDRE bit definitions */ - -#define DDE2 2 -#define DDE1 1 -#define DDE0 0 - - - -/* PINE bit definitions */ - -#define PINE2 2 -#define PINE1 1 -#define PINE0 0 - - - -/* UCSR1A bit definitions */ - -#define RXC1 7 -#define TXC1 6 -#define UDRE1 5 -#define FE1 4 -#define DOR1 3 -#define UPE1 2 -#define U2X1 1 -#define MPCM1 0 - - - -/* UCSR1B bit definitions */ - -#define RXCIE1 7 -#define TXCIE1 6 -#define UDRIE1 5 -#define RXEN1 4 -#define TXEN1 3 -#define UCSZ12 2 -#define RXB81 1 -#define TXB81 0 - - -/* Constants */ -#define SPM_PAGESIZE 128 -#define RAMSTART 0x100 -#define RAMEND 0x4FF -#define XRAMEND 0xFFFF -#define E2END 0x1FF -#define E2PAGESIZE 4 -#define FLASHEND 0x3FFF - - -/* Fuses */ - -#define FUSE_MEMORY_SIZE 3 - -/* Low Fuse Byte */ -#define FUSE_CKSEL0 (unsigned char)~_BV(0) -#define FUSE_CKSEL1 (unsigned char)~_BV(1) -#define FUSE_CKSEL2 (unsigned char)~_BV(2) -#define FUSE_CKSEL3 (unsigned char)~_BV(3) -#define FUSE_SUT0 (unsigned char)~_BV(4) -#define FUSE_SUT1 (unsigned char)~_BV(5) -#define FUSE_CKOUT (unsigned char)~_BV(6) -#define FUSE_CKDIV8 (unsigned char)~_BV(7) -#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8) - -/* High Fuse Byte */ -#define FUSE_BOOTRST (unsigned char)~_BV(0) -#define FUSE_BOOTSZ0 (unsigned char)~_BV(1) -#define FUSE_BOOTSZ1 (unsigned char)~_BV(2) -#define FUSE_EESAVE (unsigned char)~_BV(3) -#define FUSE_WDTON (unsigned char)~_BV(4) -#define FUSE_SPIEN (unsigned char)~_BV(5) -#define FUSE_JTAGEN (unsigned char)~_BV(6) -#define FUSE_OCDEN (unsigned char)~_BV(7) -#define HFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_SPIEN & FUSE_JTAGEN) - -/* Extended Fuse Byte */ -#define FUSE_BODLEVEL0 (unsigned char)~_BV(1) -#define FUSE_BODLEVEL1 (unsigned char)~_BV(2) -#define FUSE_BODLEVEL2 (unsigned char)~_BV(3) -#define FUSE_M161C (unsigned char)~_BV(4) -#define EFUSE_DEFAULT (0xFF) - - -/* Lock Bits */ -#define __LOCK_BITS_EXIST -#define __BOOT_LOCK_BITS_0_EXIST -#define __BOOT_LOCK_BITS_1_EXIST - - -/* Signature */ -#define SIGNATURE_0 0x1E -#define SIGNATURE_1 0x94 -#define SIGNATURE_2 0x04 - -#define SLEEP_MODE_IDLE 0 -#define SLEEP_MODE_PWR_DOWN 1 -#define SLEEP_MODE_PWR_SAVE 2 -#define SLEEP_MODE_ADC 3 -#define SLEEP_MODE_STANDBY 4 -#define SLEEP_MODE_EXT_STANDBY 5 - -/* Deprecated items */ -#if !defined(__AVR_LIBC_DEPRECATED_ENABLE__) - -#pragma GCC system_header - -#pragma GCC poison SIG_INTERRUPT0 -#pragma GCC poison SIG_INTERRUPT1 -#pragma GCC poison SIG_INTERRUPT2 -#pragma GCC poison SIG_PIN_CHANGE0 -#pragma GCC poison SIG_PIN_CHANGE1 -#pragma GCC poison SIG_INPUT_CAPTURE3 -#pragma GCC poison SIG_OUTPUT_COMPARE3A -#pragma GCC poison SIG_OUTPUT_COMPARE3B -#pragma GCC poison SIG_OVERFLOW3 -#pragma GCC poison SIG_OUTPUT_COMPARE2 -#pragma GCC poison SIG_OVERFLOW2 -#pragma GCC poison SIG_INPUT_CAPTURE1 -#pragma GCC poison SIG_OUTPUT_COMPARE1A -#pragma GCC poison SIG_OUTPUT_COMPARE1B -#pragma GCC poison SIG_OVERFLOW1 -#pragma GCC poison SIG_OUTPUT_COMPARE0 -#pragma GCC poison SIG_OVERFLOW0 -#pragma GCC poison SIG_SPI -#pragma GCC poison SIG_USART0_RECV -#pragma GCC poison SIG_USART1_RECV -#pragma GCC poison SIG_USART0_DATA -#pragma GCC poison SIG_USART1_DATA -#pragma GCC poison SIG_USART0_TRANS -#pragma GCC poison SIG_USART1_TRANS -#pragma GCC poison SIG_EEPROM_READY -#pragma GCC poison SIG_COMPARATOR -#pragma GCC poison SIG_SPM_READY - -#endif /* !defined(__AVR_LIBC_DEPRECATED_ENABLE__) */ - - -#endif /* _AVR_IOM162_H_ */ diff --git a/arduino/hardware/tools/avr/avr/include/avr/iom163.h b/arduino/hardware/tools/avr/avr/include/avr/iom163.h deleted file mode 100644 index 160abf3..0000000 --- a/arduino/hardware/tools/avr/avr/include/avr/iom163.h +++ /dev/null @@ -1,686 +0,0 @@ -/* Copyright (c) 2002, Marek Michalkiewicz - All rights reserved. - - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - * Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - * Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in - the documentation and/or other materials provided with the - distribution. - - * Neither the name of the copyright holders nor the names of - contributors may be used to endorse or promote products derived - from this software without specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. */ - -/* $Id: iom163.h 2231 2011-03-07 05:06:55Z arcanum $ */ - -/* avr/iom163.h - definitions for ATmega163 */ - -#ifndef _AVR_IOM163_H_ -#define _AVR_IOM163_H_ 1 - -/* This file should only be included from , never directly. */ - -#ifndef _AVR_IO_H_ -# error "Include instead of this file." -#endif - -#ifndef _AVR_IOXXX_H_ -# define _AVR_IOXXX_H_ "iom163.h" -#else -# error "Attempt to include more than one file." -#endif - -/* I/O registers */ - -#define TWBR _SFR_IO8(0x00) -#define TWSR _SFR_IO8(0x01) -#define TWAR _SFR_IO8(0x02) -#define TWDR _SFR_IO8(0x03) - -/* ADC */ -#ifndef __ASSEMBLER__ -#define ADC _SFR_IO16(0x04) -#endif -#define ADCW _SFR_IO16(0x04) -#define ADCL _SFR_IO8(0x04) -#define ADCH _SFR_IO8(0x05) -#define ADCSR _SFR_IO8(0x06) -#define ADMUX _SFR_IO8(0x07) - -/* analog comparator */ -#define ACSR _SFR_IO8(0x08) - -/* UART */ -#define UBRR _SFR_IO8(0x09) -#define UCSRB _SFR_IO8(0x0A) -#define UCSRA _SFR_IO8(0x0B) -#define UDR _SFR_IO8(0x0C) - -/* SPI */ -#define SPCR _SFR_IO8(0x0D) -#define SPSR _SFR_IO8(0x0E) -#define SPDR _SFR_IO8(0x0F) - -/* Port D */ -#define PIND _SFR_IO8(0x10) -#define DDRD _SFR_IO8(0x11) -#define PORTD _SFR_IO8(0x12) - -/* Port C */ -#define PINC _SFR_IO8(0x13) -#define DDRC _SFR_IO8(0x14) -#define PORTC _SFR_IO8(0x15) - -/* Port B */ -#define PINB _SFR_IO8(0x16) -#define DDRB _SFR_IO8(0x17) -#define PORTB _SFR_IO8(0x18) - -/* Port A */ -#define PINA _SFR_IO8(0x19) -#define DDRA _SFR_IO8(0x1A) -#define PORTA _SFR_IO8(0x1B) - -/* EEPROM Control Register */ -#define EECR _SFR_IO8(0x1C) - -/* EEPROM Data Register */ -#define EEDR _SFR_IO8(0x1D) - -/* EEPROM Address Register */ -#define EEAR _SFR_IO16(0x1E) -#define EEARL _SFR_IO8(0x1E) -#define EEARH _SFR_IO8(0x1F) - -#define UBRRHI _SFR_IO8(0x20) - -#define WDTCR _SFR_IO8(0x21) - -#define ASSR _SFR_IO8(0x22) - -/* Timer 2 */ -#define OCR2 _SFR_IO8(0x23) -#define TCNT2 _SFR_IO8(0x24) -#define TCCR2 _SFR_IO8(0x25) - -/* Timer 1 */ -#define ICR1 _SFR_IO16(0x26) -#define ICR1L _SFR_IO8(0x26) -#define ICR1H _SFR_IO8(0x27) -#define OCR1B _SFR_IO16(0x28) -#define OCR1BL _SFR_IO8(0x28) -#define OCR1BH _SFR_IO8(0x29) -#define OCR1A _SFR_IO16(0x2A) -#define OCR1AL _SFR_IO8(0x2A) -#define OCR1AH _SFR_IO8(0x2B) -#define TCNT1 _SFR_IO16(0x2C) -#define TCNT1L _SFR_IO8(0x2C) -#define TCNT1H _SFR_IO8(0x2D) -#define TCCR1B _SFR_IO8(0x2E) -#define TCCR1A _SFR_IO8(0x2F) - -#define SFIOR _SFR_IO8(0x30) - -#define OSCCAL _SFR_IO8(0x31) - -/* Timer 0 */ -#define TCNT0 _SFR_IO8(0x32) -#define TCCR0 _SFR_IO8(0x33) - -#define MCUSR _SFR_IO8(0x34) -#define MCUCR _SFR_IO8(0x35) - -#define TWCR _SFR_IO8(0x36) - -#define SPMCR _SFR_IO8(0x37) - -#define TIFR _SFR_IO8(0x38) -#define TIMSK _SFR_IO8(0x39) - -#define GIFR _SFR_IO8(0x3A) -#define GIMSK _SFR_IO8(0x3B) - -/* 0x3C reserved */ - -/* 0x3D..0x3E SP */ - -/* 0x3F SREG */ - -/* Interrupt vectors */ - -/* External Interrupt 0 */ -#define INT0_vect_num 1 -#define INT0_vect _VECTOR(1) -#define SIG_INTERRUPT0 _VECTOR(1) - -/* External Interrupt 1 */ -#define INT1_vect_num 2 -#define INT1_vect _VECTOR(2) -#define SIG_INTERRUPT1 _VECTOR(2) - -/* Timer/Counter2 Compare Match */ -#define TIMER2_COMP_vect_num 3 -#define TIMER2_COMP_vect _VECTOR(3) -#define SIG_OUTPUT_COMPARE2 _VECTOR(3) - -/* Timer/Counter2 Overflow */ -#define TIMER2_OVF_vect_num 4 -#define TIMER2_OVF_vect _VECTOR(4) -#define SIG_OVERFLOW2 _VECTOR(4) - -/* Timer/Counter1 Capture Event */ -#define TIMER1_CAPT_vect_num 5 -#define TIMER1_CAPT_vect _VECTOR(5) -#define SIG_INPUT_CAPTURE1 _VECTOR(5) - -/* Timer/Counter1 Compare Match A */ -#define TIMER1_COMPA_vect_num 6 -#define TIMER1_COMPA_vect _VECTOR(6) -#define SIG_OUTPUT_COMPARE1A _VECTOR(6) - -/* Timer/Counter1 Compare Match B */ -#define TIMER1_COMPB_vect_num 7 -#define TIMER1_COMPB_vect _VECTOR(7) -#define SIG_OUTPUT_COMPARE1B _VECTOR(7) - -/* Timer/Counter1 Overflow */ -#define TIMER1_OVF_vect_num 8 -#define TIMER1_OVF_vect _VECTOR(8) -#define SIG_OVERFLOW1 _VECTOR(8) - -/* Timer/Counter0 Overflow */ -#define TIMER0_OVF_vect_num 9 -#define TIMER0_OVF_vect _VECTOR(9) -#define SIG_OVERFLOW0 _VECTOR(9) - -/* SPI Serial Transfer Complete */ -#define SPI_STC_vect_num 10 -#define SPI_STC_vect _VECTOR(10) -#define SIG_SPI _VECTOR(10) - -/* UART, RX Complete */ -#define UART_RX_vect_num 11 -#define UART_RX_vect _VECTOR(11) -#define SIG_UART_RECV _VECTOR(11) - -/* UART Data Register Empty */ -#define UART_UDRE_vect_num 12 -#define UART_UDRE_vect _VECTOR(12) -#define SIG_UART_DATA _VECTOR(12) - -/* UART, TX Complete */ -#define UART_TX_vect_num 13 -#define UART_TX_vect _VECTOR(13) -#define SIG_UART_TRANS _VECTOR(13) - -/* ADC Conversion Complete */ -#define ADC_vect_num 14 -#define ADC_vect _VECTOR(14) -#define SIG_ADC _VECTOR(14) - -/* EEPROM Ready */ -#define EE_RDY_vect_num 15 -#define EE_RDY_vect _VECTOR(15) -#define SIG_EEPROM_READY _VECTOR(15) - -/* Analog Comparator */ -#define ANA_COMP_vect_num 16 -#define ANA_COMP_vect _VECTOR(16) -#define SIG_COMPARATOR _VECTOR(16) - -/* 2-Wire Serial Interface */ -#define TWI_vect_num 17 -#define TWI_vect _VECTOR(17) -#define SIG_2WIRE_SERIAL _VECTOR(17) - -#define _VECTORS_SIZE 72 - -/* Bit numbers */ - -/* GIMSK */ -#define INT1 7 -#define INT0 6 -/* bit 5 reserved, undefined */ -/* bits 4-0 reserved */ - -/* GIFR */ -#define INTF1 7 -#define INTF0 6 -/* bits 5-0 reserved */ - -/* TIMSK */ -#define OCIE2 7 -#define TOIE2 6 -#define TICIE1 5 -#define OCIE1A 4 -#define OCIE1B 3 -#define TOIE1 2 -/* bit 1 reserved */ -#define TOIE0 0 - -/* TIFR */ -#define OCF2 7 -#define TOV2 6 -#define ICF1 5 -#define OCF1A 4 -#define OCF1B 3 -#define TOV1 2 -/* bit 1 reserved, undefined */ -#define TOV0 0 - -/* SPMCR */ -/* bit 7 reserved */ -#define ASB 6 -/* bit 5 reserved */ -#define ASRE 4 -#define BLBSET 3 -#define PGWRT 2 -#define PGERS 1 -#define SPMEN 0 - -/* TWCR */ -#define TWINT 7 -#define TWEA 6 -#define TWSTA 5 -#define TWSTO 4 -#define TWWC 3 -#define TWEN 2 -/* bit 1 reserved */ -#define TWIE 0 - -/* TWAR */ -#define TWGCE 0 - -/* TWSR */ -#define TWS7 7 -#define TWS6 6 -#define TWS5 5 -#define TWS4 4 -#define TWS3 3 -/* bits 2-0 reserved */ - -/* MCUCR */ -/* bit 7 reserved */ -#define SE 6 -#define SM1 5 -#define SM0 4 -#define ISC11 3 -#define ISC10 2 -#define ISC01 1 -#define ISC00 0 - -/* MCUSR */ -/* bits 7-4 reserved */ -#define WDRF 3 -#define BORF 2 -#define EXTRF 1 -#define PORF 0 - -/* SFIOR */ -/* bits 7-4 reserved */ -#define ACME 3 -#define PUD 2 -#define PSR2 1 -#define PSR10 0 - -/* TCCR0 */ -/* bits 7-3 reserved */ -#define CS02 2 -#define CS01 1 -#define CS00 0 - -/* TCCR2 */ -#define FOC2 7 -#define PWM2 6 -#define COM21 5 -#define COM20 4 -#define CTC2 3 -#define CS22 2 -#define CS21 1 -#define CS20 0 - -/* ASSR */ -/* bits 7-4 reserved */ -#define AS2 3 -#define TCN2UB 2 -#define OCR2UB 1 -#define TCR2UB 0 - -/* TCCR1A */ -#define COM1A1 7 -#define COM1A0 6 -#define COM1B1 5 -#define COM1B0 4 -#define FOC1A 3 -#define FOC1B 2 -#define PWM11 1 -#define PWM10 0 - -/* TCCR1B */ -#define ICNC1 7 -#define ICES1 6 -/* bits 5-4 reserved */ -#define CTC1 3 -#define CS12 2 -#define CS11 1 -#define CS10 0 - -/* WDTCR */ -/* bits 7-5 reserved */ -#define WDTOE 4 -#define WDE 3 -#define WDP2 2 -#define WDP1 1 -#define WDP0 0 - -/* PA7-PA0 = ADC7-ADC0 */ -/* PORTA */ -#define PA7 7 -#define PA6 6 -#define PA5 5 -#define PA4 4 -#define PA3 3 -#define PA2 2 -#define PA1 1 -#define PA0 0 - -/* DDRA */ -#define DDA7 7 -#define DDA6 6 -#define DDA5 5 -#define DDA4 4 -#define DDA3 3 -#define DDA2 2 -#define DDA1 1 -#define DDA0 0 - -/* PINA */ -#define PINA7 7 -#define PINA6 6 -#define PINA5 5 -#define PINA4 4 -#define PINA3 3 -#define PINA2 2 -#define PINA1 1 -#define PINA0 0 - -/* - PB7 = SCK - PB6 = MISO - PB5 = MOSI - PB4 = SS# - PB3 = AIN1 - PB2 = AIN0 - PB1 = T1 - PB0 = T0 - */ - -/* PORTB */ -#define PB7 7 -#define PB6 6 -#define PB5 5 -#define PB4 4 -#define PB3 3 -#define PB2 2 -#define PB1 1 -#define PB0 0 - -/* DDRB */ -#define DDB7 7 -#define DDB6 6 -#define DDB5 5 -#define DDB4 4 -#define DDB3 3 -#define DDB2 2 -#define DDB1 1 -#define DDB0 0 - -/* PINB */ -#define PINB7 7 -#define PINB6 6 -#define PINB5 5 -#define PINB4 4 -#define PINB3 3 -#define PINB2 2 -#define PINB1 1 -#define PINB0 0 - -/* - PC7 = TOSC2 - PC6 = TOSC1 - PC1 = SDA - PC0 = SCL - */ -/* PORTC */ -#define PC7 7 -#define PC6 6 -#define PC5 5 -#define PC4 4 -#define PC3 3 -#define PC2 2 -#define PC1 1 -#define PC0 0 - -/* DDRC */ -#define DDC7 7 -#define DDC6 6 -#define DDC5 5 -#define DDC4 4 -#define DDC3 3 -#define DDC2 2 -#define DDC1 1 -#define DDC0 0 - -/* PINC */ -#define PINC7 7 -#define PINC6 6 -#define PINC5 5 -#define PINC4 4 -#define PINC3 3 -#define PINC2 2 -#define PINC1 1 -#define PINC0 0 - -/* - PD7 = OC2 - PD6 = ICP - PD5 = OC1A - PD4 = OC1B - PD3 = INT1 - PD2 = INT0 - PD1 = TXD - PD0 = RXD - */ - -/* PORTD */ -#define PD7 7 -#define PD6 6 -#define PD5 5 -#define PD4 4 -#define PD3 3 -#define PD2 2 -#define PD1 1 -#define PD0 0 - -/* DDRD */ -#define DDD7 7 -#define DDD6 6 -#define DDD5 5 -#define DDD4 4 -#define DDD3 3 -#define DDD2 2 -#define DDD1 1 -#define DDD0 0 - -/* PIND */ -#define PIND7 7 -#define PIND6 6 -#define PIND5 5 -#define PIND4 4 -#define PIND3 3 -#define PIND2 2 -#define PIND1 1 -#define PIND0 0 - -/* SPSR */ -#define SPIF 7 -#define WCOL 6 -/* bits 5-1 reserved */ -#define SPI2X 0 - -/* SPCR */ -#define SPIE 7 -#define SPE 6 -#define DORD 5 -#define MSTR 4 -#define CPOL 3 -#define CPHA 2 -#define SPR1 1 -#define SPR0 0 - -/* UCSRA */ -#define RXC 7 -#define TXC 6 -#define UDRE 5 -#define FE 4 -#define DOR 3 -/* bit 2 reserved */ -#define U2X 1 -#define MPCM 0 - -/* UCSRB */ -#define RXCIE 7 -#define TXCIE 6 -#define UDRIE 5 -#define RXEN 4 -#define TXEN 3 -#define CHR9 2 -#define RXB8 1 -#define TXB8 0 - -/* ACSR */ -#define ACD 7 -#define AINBG 6 -#define ACO 5 -#define ACI 4 -#define ACIE 3 -#define ACIC 2 -#define ACIS1 1 -#define ACIS0 0 - -/* ADCSR */ -#define ADEN 7 -#define ADSC 6 -#define ADFR 5 -#define ADIF 4 -#define ADIE 3 -#define ADPS2 2 -#define ADPS1 1 -#define ADPS0 0 - -/* ADMUX */ -#define REFS1 7 -#define REFS0 6 -#define ADLAR 5 -#define MUX4 4 -#define MUX3 3 -#define MUX2 2 -#define MUX1 1 -#define MUX0 0 - -/* EEPROM Control Register */ -#define EERIE 3 -#define EEMWE 2 -#define EEWE 1 -#define EERE 0 - -/* Constants */ -#define SPM_PAGESIZE 128 -#define RAMSTART 0x60 -#define RAMEND 0x45F -#define XRAMEND RAMEND -#define E2END 0x1FF -#define E2PAGESIZE 0 -#define FLASHEND 0x3FFF - - -/* Fuses */ - -#define FUSE_MEMORY_SIZE 2 - -/* Low Fuse Byte */ -#define FUSE_CKSEL0 (unsigned char)~_BV(0) -#define FUSE_CKSEL1 (unsigned char)~_BV(1) -#define FUSE_CKSEL2 (unsigned char)~_BV(2) -#define FUSE_CKSEL3 (unsigned char)~_BV(3) -#define FUSE_SPIEN (unsigned char)~_BV(5) -#define FUSE_BODEN (unsigned char)~_BV(6) -#define FUSE_BODLEVEL (unsigned char)~_BV(7) -#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SPIEN) - -/* High Fuse Byte */ -#define FUSE_BOOTRST (unsigned char)~_BV(0) -#define FUSE_BOOTSZ0 (unsigned char)~_BV(1) -#define FUSE_BOOTSZ1 (unsigned char)~_BV(2) -#define HFUSE_DEFAULT (0xFF) - - -/* Lock Bits */ -#define __LOCK_BITS_EXIST -#define __BOOT_LOCK_BITS_0_EXIST -#define __BOOT_LOCK_BITS_1_EXIST - - -/* Signature */ -#define SIGNATURE_0 0x1E -#define SIGNATURE_1 0x94 -#define SIGNATURE_2 0x02 - -#define SLEEP_MODE_IDLE 0 -#define SLEEP_MODE_ADC _BV(SM0) -#define SLEEP_MODE_PWR_DOWN _BV(SM1) -#define SLEEP_MODE_PWR_SAVE (_BV(SM0) | _BV(SM1)) - -/* Deprecated items */ -#if !defined(__AVR_LIBC_DEPRECATED_ENABLE__) - -#pragma GCC system_header - -#pragma GCC poison SIG_INTERRUPT0 -#pragma GCC poison SIG_INTERRUPT1 -#pragma GCC poison SIG_OUTPUT_COMPARE2 -#pragma GCC poison SIG_OVERFLOW2 -#pragma GCC poison SIG_INPUT_CAPTURE1 -#pragma GCC poison SIG_OUTPUT_COMPARE1A -#pragma GCC poison SIG_OUTPUT_COMPARE1B -#pragma GCC poison SIG_OVERFLOW1 -#pragma GCC poison SIG_OVERFLOW0 -#pragma GCC poison SIG_SPI -#pragma GCC poison SIG_UART_RECV -#pragma GCC poison SIG_UART_DATA -#pragma GCC poison SIG_UART_TRANS -#pragma GCC poison SIG_ADC -#pragma GCC poison SIG_EEPROM_READY -#pragma GCC poison SIG_COMPARATOR -#pragma GCC poison SIG_2WIRE_SERIAL - -#endif /* !defined(__AVR_LIBC_DEPRECATED_ENABLE__) */ - -#endif /* _AVR_IOM163_H_ */ diff --git a/arduino/hardware/tools/avr/avr/include/avr/iom164.h b/arduino/hardware/tools/avr/avr/include/avr/iom164.h deleted file mode 100644 index 0b12b8b..0000000 --- a/arduino/hardware/tools/avr/avr/include/avr/iom164.h +++ /dev/null @@ -1,101 +0,0 @@ -/* Copyright (c) 2005, 2006 Anatoly Sokolov - All rights reserved. - - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - * Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - * Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in - the documentation and/or other materials provided with the - distribution. - - * Neither the name of the copyright holders nor the names of - contributors may be used to endorse or promote products derived - from this software without specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. */ - -/* avr/iom164.h - definitions for ATmega164 */ - -/* $Id: iom164.h 2115 2010-04-05 23:19:53Z arcanum $ */ - -#ifndef _AVR_IOM164_H_ -#define _AVR_IOM164_H_ 1 - -#include - -/* Constants */ -#define SPM_PAGESIZE 128 -#define RAMSTART (0x100) -#define RAMEND 0x04FF -#define XRAMEND RAMEND -#define E2END 0x1FF -#define E2PAGESIZE 4 -#define FLASHEND 0x3FFF - - -/* Fuses */ - -#define FUSE_MEMORY_SIZE 3 - -/* Low Fuse Byte */ -#define FUSE_CKSEL0 (unsigned char)~_BV(0) -#define FUSE_CKSEL1 (unsigned char)~_BV(1) -#define FUSE_CKSEL2 (unsigned char)~_BV(2) -#define FUSE_CKSEL3 (unsigned char)~_BV(3) -#define FUSE_SUT0 (unsigned char)~_BV(4) -#define FUSE_SUT1 (unsigned char)~_BV(5) -#define FUSE_CKOUT (unsigned char)~_BV(6) -#define FUSE_CKDIV8 (unsigned char)~_BV(7) -#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_SUT1 & FUSE_CKDIV8) - -/* High Fuse Byte */ -#define FUSE_BOOTRST (unsigned char)~_BV(0) -#define FUSE_BOOTSZ0 (unsigned char)~_BV(1) -#define FUSE_BOOTSZ1 (unsigned char)~_BV(2) -#define FUSE_EESAVE (unsigned char)~_BV(3) -#define FUSE_WDTON (unsigned char)~_BV(4) -#define FUSE_SPIEN (unsigned char)~_BV(5) -#define FUSE_JTAGEN (unsigned char)~_BV(6) -#define FUSE_OCDEN (unsigned char)~_BV(7) -#define HFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_SPIEN & FUSE_JTAGEN) - -/* Extended Fuse Byte */ -#define FUSE_BODLEVEL0 (unsigned char)~_BV(0) -#define FUSE_BODLEVEL1 (unsigned char)~_BV(1) -#define FUSE_BODLEVEL2 (unsigned char)~_BV(2) -#define EFUSE_DEFAULT (0xFF) - - -/* Lock Bits */ -#define __LOCK_BITS_EXIST -#define __BOOT_LOCK_BITS_0_EXIST -#define __BOOT_LOCK_BITS_1_EXIST - - -/* Signature (ATmega164P) */ -#define SIGNATURE_0 0x1E -#define SIGNATURE_1 0x94 -#define SIGNATURE_2 0x0A - -#define SLEEP_MODE_IDLE (0x00<<1) -#define SLEEP_MODE_ADC (0x01<<1) -#define SLEEP_MODE_PWR_DOWN (0x02<<1) -#define SLEEP_MODE_PWR_SAVE (0x03<<1) -#define SLEEP_MODE_STANDBY (0x06<<1) -#define SLEEP_MODE_EXT_STANDBY (0x07<<1) - -#endif /* _AVR_IOM164_H_ */ diff --git a/arduino/hardware/tools/avr/avr/include/avr/iom164a.h b/arduino/hardware/tools/avr/avr/include/avr/iom164a.h deleted file mode 100644 index 4b9d790..0000000 --- a/arduino/hardware/tools/avr/avr/include/avr/iom164a.h +++ /dev/null @@ -1,34 +0,0 @@ -/***************************************************************************** - * - * Copyright (C) 2011 Atmel Corporation - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * - * * Neither the name of the copyright holders nor the names of - * contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - ****************************************************************************/ - -#include "iom164.h" diff --git a/arduino/hardware/tools/avr/avr/include/avr/iom164p.h b/arduino/hardware/tools/avr/avr/include/avr/iom164p.h deleted file mode 100644 index 4b9d790..0000000 --- a/arduino/hardware/tools/avr/avr/include/avr/iom164p.h +++ /dev/null @@ -1,34 +0,0 @@ -/***************************************************************************** - * - * Copyright (C) 2011 Atmel Corporation - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * - * * Neither the name of the copyright holders nor the names of - * contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - ****************************************************************************/ - -#include "iom164.h" diff --git a/arduino/hardware/tools/avr/avr/include/avr/iom164pa.h b/arduino/hardware/tools/avr/avr/include/avr/iom164pa.h deleted file mode 100644 index 3ecedeb..0000000 --- a/arduino/hardware/tools/avr/avr/include/avr/iom164pa.h +++ /dev/null @@ -1,1016 +0,0 @@ -/***************************************************************************** - * - * Copyright (C) 2015 Atmel Corporation - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * - * * Neither the name of the copyright holders nor the names of - * contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - ****************************************************************************/ - - -#ifndef _AVR_ATMEGA164PA_H_INCLUDED -#define _AVR_ATMEGA164PA_H_INCLUDED - - -#ifndef _AVR_IO_H_ -# error "Include instead of this file." -#endif - -#ifndef _AVR_IOXXX_H_ -# define _AVR_IOXXX_H_ "iom164pa.h" -#else -# error "Attempt to include more than one file." -#endif - -/* Registers and associated bit numbers */ - -#define PINA _SFR_IO8(0x00) -#define PINA7 7 -#define PINA6 6 -#define PINA5 5 -#define PINA4 4 -#define PINA3 3 -#define PINA2 2 -#define PINA1 1 -#define PINA0 0 - -#define DDRA _SFR_IO8(0x01) -#define DDRA7 7 -// Inserted "DDA7" from "DDRA7" due to compatibility -#define DDA7 7 -#define DDRA6 6 -// Inserted "DDA6" from "DDRA6" due to compatibility -#define DDA6 6 -#define DDRA5 5 -// Inserted "DDA5" from "DDRA5" due to compatibility -#define DDA5 5 -#define DDRA4 4 -// Inserted "DDA4" from "DDRA4" due to compatibility -#define DDA4 4 -#define DDRA3 3 -// Inserted "DDA3" from "DDRA3" due to compatibility -#define DDA3 3 -#define DDRA2 2 -// Inserted "DDA2" from "DDRA2" due to compatibility -#define DDA2 2 -#define DDRA1 1 -// Inserted "DDA1" from "DDRA1" due to compatibility -#define DDA1 1 -#define DDRA0 0 -// Inserted "DDA0" from "DDRA0" due to compatibility -#define DDA0 0 - -#define PORTA _SFR_IO8(0x02) -#define PORTA7 7 -#define PORTA6 6 -#define PORTA5 5 -#define PORTA4 4 -#define PORTA3 3 -#define PORTA2 2 -#define PORTA1 1 -#define PORTA0 0 - -#define PINB _SFR_IO8(0x03) -#define PINB7 7 -#define PINB6 6 -#define PINB5 5 -#define PINB4 4 -#define PINB3 3 -#define PINB2 2 -#define PINB1 1 -#define PINB0 0 - -#define DDRB _SFR_IO8(0x04) -#define DDRB7 7 -// Inserted "DDB7" from "DDRB7" due to compatibility -#define DDB7 7 -#define DDRB6 6 -// Inserted "DDB6" from "DDRB6" due to compatibility -#define DDB6 6 -#define DDRB5 5 -// Inserted "DDB5" from "DDRB5" due to compatibility -#define DDB5 5 -#define DDRB4 4 -// Inserted "DDB4" from "DDRB4" due to compatibility -#define DDB4 4 -#define DDRB3 3 -// Inserted "DDB3" from "DDRB3" due to compatibility -#define DDB3 3 -#define DDRB2 2 -// Inserted "DDB2" from "DDRB2" due to compatibility -#define DDB2 2 -#define DDRB1 1 -// Inserted "DDB1" from "DDRB1" due to compatibility -#define DDB1 1 -#define DDRB0 0 -// Inserted "DDB0" from "DDRB0" due to compatibility -#define DDB0 0 - -#define PORTB _SFR_IO8(0x05) -#define PORTB7 7 -#define PORTB6 6 -#define PORTB5 5 -#define PORTB4 4 -#define PORTB3 3 -#define PORTB2 2 -#define PORTB1 1 -#define PORTB0 0 - -#define PINC _SFR_IO8(0x06) -#define PINC7 7 -#define PINC6 6 -#define PINC5 5 -#define PINC4 4 -#define PINC3 3 -#define PINC2 2 -#define PINC1 1 -#define PINC0 0 - -#define DDRC _SFR_IO8(0x07) -#define DDRC7 7 -// Inserted "DDC7" from "DDRC7" due to compatibility -#define DDC7 7 -#define DDRC6 6 -// Inserted "DDC6" from "DDRC6" due to compatibility -#define DDC6 6 -#define DDRC5 5 -// Inserted "DDC5" from "DDRC5" due to compatibility -#define DDC5 5 -#define DDRC4 4 -// Inserted "DDC4" from "DDRC4" due to compatibility -#define DDC4 4 -#define DDRC3 3 -// Inserted "DDC3" from "DDRC3" due to compatibility -#define DDC3 3 -#define DDRC2 2 -// Inserted "DDC2" from "DDRC2" due to compatibility -#define DDC2 2 -#define DDRC1 1 -// Inserted "DDC1" from "DDRC1" due to compatibility -#define DDC1 1 -#define DDRC0 0 -// Inserted "DDC0" from "DDRC0" due to compatibility -#define DDC0 0 - -#define PORTC _SFR_IO8(0x08) -#define PORTC7 7 -#define PORTC6 6 -#define PORTC5 5 -#define PORTC4 4 -#define PORTC3 3 -#define PORTC2 2 -#define PORTC1 1 -#define PORTC0 0 - -#define PIND _SFR_IO8(0x09) -#define PIND7 7 -#define PIND6 6 -#define PIND5 5 -#define PIND4 4 -#define PIND3 3 -#define PIND2 2 -#define PIND1 1 -#define PIND0 0 - -#define DDRD _SFR_IO8(0x0A) -#define DDRD7 7 -// Inserted "DDD7" from "DDRD7" due to compatibility -#define DDD7 7 -#define DDRD6 6 -// Inserted "DDD6" from "DDRD6" due to compatibility -#define DDD6 6 -#define DDRD5 5 -// Inserted "DDD5" from "DDRD5" due to compatibility -#define DDD5 5 -#define DDRD4 4 -// Inserted "DDD4" from "DDRD4" due to compatibility -#define DDD4 4 -#define DDRD3 3 -// Inserted "DDD3" from "DDRD3" due to compatibility -#define DDD3 3 -#define DDRD2 2 -// Inserted "DDD2" from "DDRD2" due to compatibility -#define DDD2 2 -#define DDRD1 1 -// Inserted "DDD1" from "DDRD1" due to compatibility -#define DDD1 1 -#define DDRD0 0 -// Inserted "DDD0" from "DDRD0" due to compatibility -#define DDD0 0 - -#define PORTD _SFR_IO8(0x0B) -#define PORTD7 7 -#define PORTD6 6 -#define PORTD5 5 -#define PORTD4 4 -#define PORTD3 3 -#define PORTD2 2 -#define PORTD1 1 -#define PORTD0 0 - -/* Reserved [0x0C..0x14] */ - -#define TIFR0 _SFR_IO8(0x15) -#define TOV0 0 -#define OCF0A 1 -#define OCF0B 2 - -#define TIFR1 _SFR_IO8(0x16) -#define TOV1 0 -#define OCF1A 1 -#define OCF1B 2 -#define ICF1 5 - -#define TIFR2 _SFR_IO8(0x17) -#define TOV2 0 -#define OCF2A 1 -#define OCF2B 2 - -/* Reserved [0x18..0x1A] */ - -#define PCIFR _SFR_IO8(0x1B) -#define PCIF0 0 -#define PCIF1 1 -#define PCIF2 2 -#define PCIF3 3 - -#define EIFR _SFR_IO8(0x1C) -#define INTF0 0 -#define INTF1 1 -#define INTF2 2 - -#define EIMSK _SFR_IO8(0x1D) -#define INT0 0 -#define INT1 1 -#define INT2 2 - -#define GPIOR0 _SFR_IO8(0x1E) -#define GPIOR00 0 -#define GPIOR01 1 -#define GPIOR02 2 -#define GPIOR03 3 -#define GPIOR04 4 -#define GPIOR05 5 -#define GPIOR06 6 -#define GPIOR07 7 - -#define EECR _SFR_IO8(0x1F) -#define EERE 0 -#define EEPE 1 -#define EEMPE 2 -#define EERIE 3 -#define EEPM0 4 -#define EEPM1 5 - -#define EEDR _SFR_IO8(0x20) - -/* Combine EEARL and EEARH */ -#define EEAR _SFR_IO16(0x21) - -#define EEARL _SFR_IO8(0x21) -#define EEARH _SFR_IO8(0x22) - -#define GTCCR _SFR_IO8(0x23) -#define PSRSYNC 0 -#define TSM 7 -#define PSRASY 1 - -#define TCCR0A _SFR_IO8(0x24) -#define WGM00 0 -#define WGM01 1 -#define COM0B0 4 -#define COM0B1 5 -#define COM0A0 6 -#define COM0A1 7 - -#define TCCR0B _SFR_IO8(0x25) -#define CS00 0 -#define CS01 1 -#define CS02 2 -#define WGM02 3 -#define FOC0B 6 -#define FOC0A 7 - -#define TCNT0 _SFR_IO8(0x26) - -#define OCR0A _SFR_IO8(0x27) - -#define OCR0B _SFR_IO8(0x28) - -/* Reserved [0x29] */ - -#define GPIOR1 _SFR_IO8(0x2A) -#define GPIOR10 0 -#define GPIOR11 1 -#define GPIOR12 2 -#define GPIOR13 3 -#define GPIOR14 4 -#define GPIOR15 5 -#define GPIOR16 6 -#define GPIOR17 7 - -#define GPIOR2 _SFR_IO8(0x2B) -#define GPIOR20 0 -#define GPIOR21 1 -#define GPIOR22 2 -#define GPIOR23 3 -#define GPIOR24 4 -#define GPIOR25 5 -#define GPIOR26 6 -#define GPIOR27 7 - -#define SPCR0 _SFR_IO8(0x2C) -#define SPR00 0 -#define SPR10 1 -#define CPHA0 2 -#define CPOL0 3 -#define MSTR0 4 -#define DORD0 5 -#define SPE0 6 -#define SPIE0 7 - -#define SPSR0 _SFR_IO8(0x2D) -#define SPI2X0 0 -#define WCOL0 6 -#define SPIF0 7 - -#define SPDR0 _SFR_IO8(0x2E) - -/* Reserved [0x2F] */ - -#define ACSR _SFR_IO8(0x30) -#define ACIS0 0 -#define ACIS1 1 -#define ACIC 2 -#define ACIE 3 -#define ACI 4 -#define ACO 5 -#define ACBG 6 -#define ACD 7 - -#define OCDR _SFR_IO8(0x31) -#define OCDR7 7 -#define OCDR6 6 -#define OCDR5 5 -#define OCDR4 4 -#define OCDR3 3 -#define OCDR2 2 -#define OCDR1 1 -#define OCDR0 0 - -/* Reserved [0x32] */ - -#define SMCR _SFR_IO8(0x33) -#define SE 0 -#define SM0 1 -#define SM1 2 -#define SM2 3 - -#define MCUSR _SFR_IO8(0x34) -#define JTRF 4 -#define PORF 0 -#define EXTRF 1 -#define BORF 2 -#define WDRF 3 - -#define MCUCR _SFR_IO8(0x35) -#define JTD 7 -#define IVCE 0 -#define IVSEL 1 -#define PUD 4 -#define BODSE 5 -#define BODS 6 - -/* Reserved [0x36] */ - -#define SPMCSR _SFR_IO8(0x37) -#define SPMEN 0 -#define PGERS 1 -#define PGWRT 2 -#define BLBSET 3 -#define RWWSRE 4 -#define SIGRD 5 -#define RWWSB 6 -#define SPMIE 7 - -/* Reserved [0x38..0x3C] */ - -/* SP [0x3D..0x3E] */ - -/* SREG [0x3F] */ - -#define WDTCSR _SFR_MEM8(0x60) -#define WDE 3 -#define WDCE 4 -#define WDP0 0 -#define WDP1 1 -#define WDP2 2 -#define WDP3 5 -#define WDIE 6 -#define WDIF 7 - -#define CLKPR _SFR_MEM8(0x61) -#define CLKPS0 0 -#define CLKPS1 1 -#define CLKPS2 2 -#define CLKPS3 3 -#define CLKPCE 7 - -/* Reserved [0x62..0x63] */ - -#define PRR0 _SFR_MEM8(0x64) -#define PRADC 0 -#define PRSPI 2 -#define PRTIM1 3 -#define PRUSART0 1 -#define PRUSART1 4 -#define PRTIM0 5 -#define PRTIM2 6 -#define PRTWI 7 - -#define __AVR_HAVE_PRR0 ((1<, never directly. */ - -#ifndef _AVR_IO_H_ -# error "Include instead of this file." -#endif - -#ifndef _AVR_IOXXX_H_ -# define _AVR_IOXXX_H_ "iom165.h" -#else -# error "Attempt to include more than one file." -#endif - -/* Registers and associated bit numbers */ - -#define PINA _SFR_IO8(0x00) -#define PINA7 7 -#define PINA6 6 -#define PINA5 5 -#define PINA4 4 -#define PINA3 3 -#define PINA2 2 -#define PINA1 1 -#define PINA0 0 - -#define DDRA _SFR_IO8(0x01) -#define DDA7 7 -#define DDA6 6 -#define DDA5 5 -#define DDA4 4 -#define DDA3 3 -#define DDA2 2 -#define DDA1 1 -#define DDA0 0 - -#define PORTA _SFR_IO8(0x02) -#define PA7 7 -#define PA6 6 -#define PA5 5 -#define PA4 4 -#define PA3 3 -#define PA2 2 -#define PA1 1 -#define PA0 0 - -#define PINB _SFR_IO8(0x03) -#define PINB7 7 -#define PINB6 6 -#define PINB5 5 -#define PINB4 4 -#define PINB3 3 -#define PINB2 2 -#define PINB1 1 -#define PINB0 0 - -#define DDRB _SFR_IO8(0x04) -#define DDB7 7 -#define DDB6 6 -#define DDB5 5 -#define DDB4 4 -#define DDB3 3 -#define DDB2 2 -#define DDB1 1 -#define DDB0 0 - -#define PORTB _SFR_IO8(0x05) -#define PB7 7 -#define PB6 6 -#define PB5 5 -#define PB4 4 -#define PB3 3 -#define PB2 2 -#define PB1 1 -#define PB0 0 - -#define PINC _SFR_IO8(0x06) -#define PINC7 7 -#define PINC6 6 -#define PINC5 5 -#define PINC4 4 -#define PINC3 3 -#define PINC2 2 -#define PINC1 1 -#define PINC0 0 - -#define DDRC _SFR_IO8(0x07) -#define DDC7 7 -#define DDC6 6 -#define DDC5 5 -#define DDC4 4 -#define DDC3 3 -#define DDC2 2 -#define DDC1 1 -#define DDC0 0 - -#define PORTC _SFR_IO8(0x08) -#define PC7 7 -#define PC6 6 -#define PC5 5 -#define PC4 4 -#define PC3 3 -#define PC2 2 -#define PC1 1 -#define PC0 0 - -#define PIND _SFR_IO8(0x09) -#define PIND7 7 -#define PIND6 6 -#define PIND5 5 -#define PIND4 4 -#define PIND3 3 -#define PIND2 2 -#define PIND1 1 -#define PIND0 0 - -#define DDRD _SFR_IO8(0x0A) -#define DDD7 7 -#define DDD6 6 -#define DDD5 5 -#define DDD4 4 -#define DDD3 3 -#define DDD2 2 -#define DDD1 1 -#define DDD0 0 - -#define PORTD _SFR_IO8(0x0B) -#define PD7 7 -#define PD6 6 -#define PD5 5 -#define PD4 4 -#define PD3 3 -#define PD2 2 -#define PD1 1 -#define PD0 0 - -#define PINE _SFR_IO8(0x0C) -#define PINE7 7 -#define PINE6 6 -#define PINE5 5 -#define PINE4 4 -#define PINE3 3 -#define PINE2 2 -#define PINE1 1 -#define PINE0 0 - -#define DDRE _SFR_IO8(0x0D) -#define DDE7 7 -#define DDE6 6 -#define DDE5 5 -#define DDE4 4 -#define DDE3 3 -#define DDE2 2 -#define DDE1 1 -#define DDE0 0 - -#define PORTE _SFR_IO8(0x0E) -#define PE7 7 -#define PE6 6 -#define PE5 5 -#define PE4 4 -#define PE3 3 -#define PE2 2 -#define PE1 1 -#define PE0 0 - -#define PINF _SFR_IO8(0x0F) -#define PINF7 7 -#define PINF6 6 -#define PINF5 5 -#define PINF4 4 -#define PINF3 3 -#define PINF2 2 -#define PINF1 1 -#define PINF0 0 - -#define DDRF _SFR_IO8(0x10) -#define DDF7 7 -#define DDF6 6 -#define DDF5 5 -#define DDF4 4 -#define DDF3 3 -#define DDF2 2 -#define DDF1 1 -#define DDF0 0 - -#define PORTF _SFR_IO8(0x11) -#define PF7 7 -#define PF6 6 -#define PF5 5 -#define PF4 4 -#define PF3 3 -#define PF2 2 -#define PF1 1 -#define PF0 0 - -#define PING _SFR_IO8(0x12) -#define PING4 4 -#define PING3 3 -#define PING2 2 -#define PING1 1 -#define PING0 0 - -#define DDRG _SFR_IO8(0x13) -#define DDG4 4 -#define DDG3 3 -#define DDG2 2 -#define DDG1 1 -#define DDG0 0 - -#define PORTG _SFR_IO8(0x14) -#define PG4 4 -#define PG3 3 -#define PG2 2 -#define PG1 1 -#define PG0 0 - -#define TIFR0 _SFR_IO8(0x15) -#define TOV0 0 -#define OCF0A 1 - -#define TIFR1 _SFR_IO8(0x16) -#define TOV1 0 -#define OCF1A 1 -#define OCF1B 2 -#define ICF1 5 - -#define TIFR2 _SFR_IO8(0x17) -#define TOV2 0 -#define OCF2A 1 - -/* Reserved [0x18..0x1B] */ - -#define EIFR _SFR_IO8(0x1C) -#define INTF0 0 -#define PCIF0 6 -#define PCIF1 7 - -#define EIMSK _SFR_IO8(0x1D) -#define INT0 0 -#define PCIE0 6 -#define PCIE1 7 - -#define GPIOR0 _SFR_IO8(0x1E) - -#define EECR _SFR_IO8(0x1F) -#define EERE 0 -#define EEWE 1 -#define EEMWE 2 -#define EERIE 3 - -#define EEDR _SFR_IO8(0X20) - -/* Combine EEARL and EEARH */ -#define EEAR _SFR_IO16(0x21) -#define EEARL _SFR_IO8(0x21) -#define EEARH _SFR_IO8(0X22) - -/* 6-char sequence denoting where to find the EEPROM registers in memory space. - Adresses denoted in hex syntax with uppercase letters. Used by the EEPROM - subroutines. - First two letters: EECR address. - Second two letters: EEDR address. - Last two letters: EEAR address. */ -#define __EEPROM_REG_LOCATIONS__ 1F2021 - -#define GTCCR _SFR_IO8(0x23) -#define PSR10 0 -#define PSR2 1 -#define TSM 7 - -#define TCCR0A _SFR_IO8(0x24) -#define CS00 0 -#define CS01 1 -#define CS02 2 -#define WGM01 3 -#define COM0A0 4 -#define COM0A1 5 -#define WGM00 6 -#define FOC0A 7 - -/* Reserved [0x25] */ - -#define TCNT0 _SFR_IO8(0X26) - -#define OCR0A _SFR_IO8(0X27) - -/* Reserved [0x28..0x29] */ - -#define GPIOR1 _SFR_IO8(0x2A) - -#define GPIOR2 _SFR_IO8(0x2B) - -#define SPCR _SFR_IO8(0x2C) -#define SPR0 0 -#define SPR1 1 -#define CPHA 2 -#define CPOL 3 -#define MSTR 4 -#define DORD 5 -#define SPE 6 -#define SPIE 7 - -#define SPSR _SFR_IO8(0x2D) -#define SPI2X 0 -#define WCOL 6 -#define SPIF 7 - -#define SPDR _SFR_IO8(0X2E) - -/* Reserved [0x2F] */ - -#define ACSR _SFR_IO8(0x30) -#define ACIS0 0 -#define ACIS1 1 -#define ACIC 2 -#define ACIE 3 -#define ACI 4 -#define ACO 5 -#define ACBG 6 -#define ACD 7 - -#define OCDR _SFR_IO8(0x31) -#define OCDR0 0 -#define OCDR1 1 -#define OCDR2 2 -#define OCDR3 3 -#define OCDR4 4 -#define OCDR5 5 -#define OCDR6 6 -#define OCD 7 // The datasheet defines this but IMO it should be OCDR7. -#define OCDR7 7 -#define IDRD 7 - -/* Reserved [0x32] */ - -#define SMCR _SFR_IO8(0x33) -#define SE 0 -#define SM0 1 -#define SM1 2 -#define SM2 3 - -#define MCUSR _SFR_IO8(0x34) -#define PORF 0 -#define EXTRF 1 -#define BORF 2 -#define WDRF 3 -#define JTRF 4 - -#define MCUCR _SFR_IO8(0X35) -#define IVCE 0 -#define IVSEL 1 -#define PUD 4 -#define JTD 7 - -/* Reserved [0x36] */ - -#define SPMCSR _SFR_IO8(0x37) -#define SPMEN 0 -#define PGERS 1 -#define PGWRT 2 -#define BLBSET 3 -#define RWWSRE 4 -#define RWWSB 6 -#define SPMIE 7 - -/* Reserved [0x38..0x3C] */ - -/* SP [0x3D..0x3E] */ -/* SREG [0x3F] */ - -#define WDTCR _SFR_MEM8(0x60) -#define WDP0 0 -#define WDP1 1 -#define WDP2 2 -#define WDE 3 -#define WDCE 4 - -#define CLKPR _SFR_MEM8(0x61) -#define CLKPS0 0 -#define CLKPS1 1 -#define CLKPS2 2 -#define CLKPS3 3 -#define CLKPCE 7 - -/* Reserved [0x62..0x63] */ - -#define PRR _SFR_MEM8(0x64) -#define PRADC 0 -#define PRUSART0 1 -#define PRSPI 2 -#define PRTIM1 3 - -#define __AVR_HAVE_PRR ((1< instead of this file." -#endif - -#ifndef _AVR_IOXXX_H_ -# define _AVR_IOXXX_H_ "iom165a.h" -#else -# error "Attempt to include more than one file." -#endif - -/* Registers and associated bit numbers */ - -#define PINA _SFR_IO8(0x00) -#define PINA7 7 -#define PINA6 6 -#define PINA5 5 -#define PINA4 4 -#define PINA3 3 -#define PINA2 2 -#define PINA1 1 -#define PINA0 0 - -#define DDRA _SFR_IO8(0x01) -#define DDRA7 7 -#define DDRA6 6 -#define DDRA5 5 -#define DDRA4 4 -#define DDRA3 3 -#define DDRA2 2 -#define DDRA1 1 -#define DDRA0 0 - -#define PORTA _SFR_IO8(0x02) -#define PORTA7 7 -#define PORTA6 6 -#define PORTA5 5 -#define PORTA4 4 -#define PORTA3 3 -#define PORTA2 2 -#define PORTA1 1 -#define PORTA0 0 - -#define PINB _SFR_IO8(0x03) -#define PINB7 7 -#define PINB6 6 -#define PINB5 5 -#define PINB4 4 -#define PINB3 3 -#define PINB2 2 -#define PINB1 1 -#define PINB0 0 - -#define DDRB _SFR_IO8(0x04) -#define DDRB7 7 -#define DDRB6 6 -#define DDRB5 5 -#define DDRB4 4 -#define DDRB3 3 -#define DDRB2 2 -#define DDRB1 1 -#define DDRB0 0 - -#define PORTB _SFR_IO8(0x05) -#define PORTB7 7 -#define PORTB6 6 -#define PORTB5 5 -#define PORTB4 4 -#define PORTB3 3 -#define PORTB2 2 -#define PORTB1 1 -#define PORTB0 0 - -#define PINC _SFR_IO8(0x06) -#define PINC7 7 -#define PINC6 6 -#define PINC5 5 -#define PINC4 4 -#define PINC3 3 -#define PINC2 2 -#define PINC1 1 -#define PINC0 0 - -#define DDRC _SFR_IO8(0x07) -#define DDRC7 7 -#define DDRC6 6 -#define DDRC5 5 -#define DDRC4 4 -#define DDRC3 3 -#define DDRC2 2 -#define DDRC1 1 -#define DDRC0 0 - -#define PORTC _SFR_IO8(0x08) -#define PORTC7 7 -#define PORTC6 6 -#define PORTC5 5 -#define PORTC4 4 -#define PORTC3 3 -#define PORTC2 2 -#define PORTC1 1 -#define PORTC0 0 - -#define PIND _SFR_IO8(0x09) -#define PIND7 7 -#define PIND6 6 -#define PIND5 5 -#define PIND4 4 -#define PIND3 3 -#define PIND2 2 -#define PIND1 1 -#define PIND0 0 - -#define DDRD _SFR_IO8(0x0A) -#define DDRD7 7 -#define DDRD6 6 -#define DDRD5 5 -#define DDRD4 4 -#define DDRD3 3 -#define DDRD2 2 -#define DDRD1 1 -#define DDRD0 0 - -#define PORTD _SFR_IO8(0x0B) -#define PORTD7 7 -#define PORTD6 6 -#define PORTD5 5 -#define PORTD4 4 -#define PORTD3 3 -#define PORTD2 2 -#define PORTD1 1 -#define PORTD0 0 - -#define PINE _SFR_IO8(0x0C) -#define PINE7 7 -#define PINE6 6 -#define PINE5 5 -#define PINE4 4 -#define PINE3 3 -#define PINE2 2 -#define PINE1 1 -#define PINE0 0 - -#define DDRE _SFR_IO8(0x0D) -#define DDRE7 7 -#define DDRE6 6 -#define DDRE5 5 -#define DDRE4 4 -#define DDRE3 3 -#define DDRE2 2 -#define DDRE1 1 -#define DDRE0 0 - -#define PORTE _SFR_IO8(0x0E) -#define PORTE7 7 -#define PORTE6 6 -#define PORTE5 5 -#define PORTE4 4 -#define PORTE3 3 -#define PORTE2 2 -#define PORTE1 1 -#define PORTE0 0 - -#define PINF _SFR_IO8(0x0F) -#define PINF7 7 -#define PINF6 6 -#define PINF5 5 -#define PINF4 4 -#define PINF3 3 -#define PINF2 2 -#define PINF1 1 -#define PINF0 0 - -#define DDRF _SFR_IO8(0x10) -#define DDRF7 7 -#define DDRF6 6 -#define DDRF5 5 -#define DDRF4 4 -#define DDRF3 3 -#define DDRF2 2 -#define DDRF1 1 -#define DDRF0 0 - -#define PORTF _SFR_IO8(0x11) -#define PORTF7 7 -#define PORTF6 6 -#define PORTF5 5 -#define PORTF4 4 -#define PORTF3 3 -#define PORTF2 2 -#define PORTF1 1 -#define PORTF0 0 - -#define PING _SFR_IO8(0x12) -#define PING5 5 -#define PING4 4 -#define PING3 3 -#define PING2 2 -#define PING1 1 -#define PING0 0 - -#define DDRG _SFR_IO8(0x13) -#define DDRG4 4 -#define DDRG3 3 -#define DDRG2 2 -#define DDRG1 1 -#define DDRG0 0 - -#define PORTG _SFR_IO8(0x14) -#define PORTG4 4 -#define PORTG3 3 -#define PORTG2 2 -#define PORTG1 1 -#define PORTG0 0 - -#define TIFR0 _SFR_IO8(0x15) -#define TOV0 0 -#define OCF0A 1 - -#define TIFR1 _SFR_IO8(0x16) -#define TOV1 0 -#define OCF1A 1 -#define OCF1B 2 -#define ICF1 5 - -#define TIFR2 _SFR_IO8(0x17) -#define TOV2 0 -#define OCF2A 1 - -/* Reserved [0x18..0x1B] */ - -#define EIFR _SFR_IO8(0x1C) -#define INTF0 0 -#define PCIF0 4 -#define PCIF1 5 - -#define EIMSK _SFR_IO8(0x1D) -#define INT0 0 -#define PCIE0 4 -#define PCIE1 5 - -#define GPIOR0 _SFR_IO8(0x1E) - -#define EECR _SFR_IO8(0x1F) -#define EERE 0 -#define EEWE 1 -#define EEMWE 2 -#define EERIE 3 - -#define EEDR _SFR_IO8(0x20) - -/* Combine EEARL and EEARH */ -#define EEAR _SFR_IO16(0x21) - -#define EEARL _SFR_IO8(0x21) -#define EEARH _SFR_IO8(0x22) - -#define GTCCR _SFR_IO8(0x23) -#define PSR310 0 -#define TSM 7 -#define PSR2 1 - -#define TCCR0A _SFR_IO8(0x24) -#define CS00 0 -#define CS01 1 -#define CS02 2 -#define WGM01 3 -#define COM0A0 4 -#define COM0A1 5 -#define WGM00 6 -#define FOC0A 7 - -/* Reserved [0x25] */ - -#define TCNT0 _SFR_IO8(0x26) - -#define OCR0A _SFR_IO8(0x27) - -/* Reserved [0x28..0x29] */ - -#define GPIOR1 _SFR_IO8(0x2A) - -#define GPIOR2 _SFR_IO8(0x2B) - -#define SPCR _SFR_IO8(0x2C) -#define SPR0 0 -#define SPR1 1 -#define CPHA 2 -#define CPOL 3 -#define MSTR 4 -#define DORD 5 -#define SPE 6 -#define SPIE 7 - -#define SPSR _SFR_IO8(0x2D) -#define SPI2X 0 -#define WCOL 6 -#define SPIF 7 - -#define SPDR _SFR_IO8(0x2E) - -/* Reserved [0x2F] */ - -#define ACSR _SFR_IO8(0x30) -#define ACIS0 0 -#define ACIS1 1 -#define ACIC 2 -#define ACIE 3 -#define ACI 4 -#define ACO 5 -#define ACBG 6 -#define ACD 7 - -#define OCDR _SFR_IO8(0x31) -#define OCDR7 7 -#define OCDR6 6 -#define OCDR5 5 -#define OCDR4 4 -#define OCDR3 3 -#define OCDR2 2 -#define OCDR1 1 -#define OCDR0 0 - -/* Reserved [0x32] */ - -#define SMCR _SFR_IO8(0x33) -#define SE 0 -#define SM0 1 -#define SM1 2 -#define SM2 3 - -#define MCUSR _SFR_IO8(0x34) -#define JTRF 4 -#define PORF 0 -#define EXTRF 1 -#define BORF 2 -#define WDRF 3 - -#define MCUCR _SFR_IO8(0x35) -#define JTD 7 -#define IVCE 0 -#define IVSEL 1 -#define PUD 4 - -/* Reserved [0x36] */ - -#define SPMCSR _SFR_IO8(0x37) -#define SPMEN 0 -#define PGERS 1 -#define PGWRT 2 -#define BLBSET 3 -#define RWWSRE 4 -#define RWWSB 6 -#define SPMIE 7 - -/* Reserved [0x38..0x3C] */ - -/* SP [0x3D..0x3E] */ - -/* SREG [0x3F] */ - -#define WDTCR _SFR_MEM8(0x60) -#define WDP0 0 -#define WDP1 1 -#define WDP2 2 -#define WDE 3 -#define WDCE 4 - -#define CLKPR _SFR_MEM8(0x61) -#define CLKPS0 0 -#define CLKPS1 1 -#define CLKPS2 2 -#define CLKPS3 3 -#define CLKPCE 7 - -/* Reserved [0x62..0x63] */ - -#define PRR _SFR_MEM8(0x64) -#define PRADC 0 -#define PRUSART0 1 -#define PRSPI 2 -#define PRTIM1 3 - -#define __AVR_HAVE_PRR ((1< - All rights reserved. - - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - * Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - * Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in - the documentation and/or other materials provided with the - distribution. - - * Neither the name of the copyright holders nor the names of - contributors may be used to endorse or promote products derived - from this software without specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. */ - -/* $Id: iom165p.h 2231 2011-03-07 05:06:55Z arcanum $ */ - -/* avr/iom165p.h - definitions for ATmega165P */ - -#ifndef _AVR_IOM165P_H_ -#define _AVR_IOM165P_H_ 1 - -/* This file should only be included from , never directly. */ - -#ifndef _AVR_IO_H_ -# error "Include instead of this file." -#endif - -#ifndef _AVR_IOXXX_H_ -# define _AVR_IOXXX_H_ "iom165p.h" -#else -# error "Attempt to include more than one file." -#endif - -/* Registers and associated bit numbers */ - -#define PINA _SFR_IO8(0x00) -#define PINA7 7 -#define PINA6 6 -#define PINA5 5 -#define PINA4 4 -#define PINA3 3 -#define PINA2 2 -#define PINA1 1 -#define PINA0 0 - -#define DDRA _SFR_IO8(0x01) -#define DDA7 7 -#define DDA6 6 -#define DDA5 5 -#define DDA4 4 -#define DDA3 3 -#define DDA2 2 -#define DDA1 1 -#define DDA0 0 - -#define PORTA _SFR_IO8(0x02) -#define PA7 7 -#define PA6 6 -#define PA5 5 -#define PA4 4 -#define PA3 3 -#define PA2 2 -#define PA1 1 -#define PA0 0 - -#define PINB _SFR_IO8(0x03) -#define PINB7 7 -#define PINB6 6 -#define PINB5 5 -#define PINB4 4 -#define PINB3 3 -#define PINB2 2 -#define PINB1 1 -#define PINB0 0 - -#define DDRB _SFR_IO8(0x04) -#define DDB7 7 -#define DDB6 6 -#define DDB5 5 -#define DDB4 4 -#define DDB3 3 -#define DDB2 2 -#define DDB1 1 -#define DDB0 0 - -#define PORTB _SFR_IO8(0x05) -#define PB7 7 -#define PB6 6 -#define PB5 5 -#define PB4 4 -#define PB3 3 -#define PB2 2 -#define PB1 1 -#define PB0 0 - -#define PINC _SFR_IO8(0x06) -#define PINC7 7 -#define PINC6 6 -#define PINC5 5 -#define PINC4 4 -#define PINC3 3 -#define PINC2 2 -#define PINC1 1 -#define PINC0 0 - -#define DDRC _SFR_IO8(0x07) -#define DDC7 7 -#define DDC6 6 -#define DDC5 5 -#define DDC4 4 -#define DDC3 3 -#define DDC2 2 -#define DDC1 1 -#define DDC0 0 - -#define PORTC _SFR_IO8(0x08) -#define PC7 7 -#define PC6 6 -#define PC5 5 -#define PC4 4 -#define PC3 3 -#define PC2 2 -#define PC1 1 -#define PC0 0 - -#define PIND _SFR_IO8(0x09) -#define PIND7 7 -#define PIND6 6 -#define PIND5 5 -#define PIND4 4 -#define PIND3 3 -#define PIND2 2 -#define PIND1 1 -#define PIND0 0 - -#define DDRD _SFR_IO8(0x0A) -#define DDD7 7 -#define DDD6 6 -#define DDD5 5 -#define DDD4 4 -#define DDD3 3 -#define DDD2 2 -#define DDD1 1 -#define DDD0 0 - -#define PORTD _SFR_IO8(0x0B) -#define PD7 7 -#define PD6 6 -#define PD5 5 -#define PD4 4 -#define PD3 3 -#define PD2 2 -#define PD1 1 -#define PD0 0 - -#define PINE _SFR_IO8(0x0C) -#define PINE7 7 -#define PINE6 6 -#define PINE5 5 -#define PINE4 4 -#define PINE3 3 -#define PINE2 2 -#define PINE1 1 -#define PINE0 0 - -#define DDRE _SFR_IO8(0x0D) -#define DDE7 7 -#define DDE6 6 -#define DDE5 5 -#define DDE4 4 -#define DDE3 3 -#define DDE2 2 -#define DDE1 1 -#define DDE0 0 - -#define PORTE _SFR_IO8(0x0E) -#define PE7 7 -#define PE6 6 -#define PE5 5 -#define PE4 4 -#define PE3 3 -#define PE2 2 -#define PE1 1 -#define PE0 0 - -#define PINF _SFR_IO8(0x0F) -#define PINF7 7 -#define PINF6 6 -#define PINF5 5 -#define PINF4 4 -#define PINF3 3 -#define PINF2 2 -#define PINF1 1 -#define PINF0 0 - -#define DDRF _SFR_IO8(0x10) -#define DDF7 7 -#define DDF6 6 -#define DDF5 5 -#define DDF4 4 -#define DDF3 3 -#define DDF2 2 -#define DDF1 1 -#define DDF0 0 - -#define PORTF _SFR_IO8(0x11) -#define PF7 7 -#define PF6 6 -#define PF5 5 -#define PF4 4 -#define PF3 3 -#define PF2 2 -#define PF1 1 -#define PF0 0 - -#define PING _SFR_IO8(0x12) -#define PING5 5 -#define PING4 4 -#define PING3 3 -#define PING2 2 -#define PING1 1 -#define PING0 0 - -#define DDRG _SFR_IO8(0x13) -#define DDG4 4 -#define DDG3 3 -#define DDG2 2 -#define DDG1 1 -#define DDG0 0 - -#define PORTG _SFR_IO8(0x14) -#define PG4 4 -#define PG3 3 -#define PG2 2 -#define PG1 1 -#define PG0 0 - -#define TIFR0 _SFR_IO8(0x15) -#define TOV0 0 -#define OCF0A 1 - -#define TIFR1 _SFR_IO8(0x16) -#define TOV1 0 -#define OCF1A 1 -#define OCF1B 2 -#define ICF1 5 - -#define TIFR2 _SFR_IO8(0x17) -#define TOV2 0 -#define OCF2A 1 - -/* Reserved [0x18..0x1B] */ - -#define EIFR _SFR_IO8(0x1C) -#define INTF0 0 -#define PCIF0 6 -#define PCIF1 7 - -#define EIMSK _SFR_IO8(0x1D) -#define INT0 0 -#define PCIE0 6 -#define PCIE1 7 - -#define GPIOR0 _SFR_IO8(0x1E) - -#define EECR _SFR_IO8(0x1F) -#define EERE 0 -#define EEWE 1 -#define EEMWE 2 -#define EERIE 3 - -#define EEDR _SFR_IO8(0X20) - -/* Combine EEARL and EEARH */ -#define EEAR _SFR_IO16(0x21) -#define EEARL _SFR_IO8(0x21) -#define EEARH _SFR_IO8(0X22) - -/* 6-char sequence denoting where to find the EEPROM registers in memory space. - Adresses denoted in hex syntax with uppercase letters. Used by the EEPROM - subroutines. - First two letters: EECR address. - Second two letters: EEDR address. - Last two letters: EEAR address. */ -#define __EEPROM_REG_LOCATIONS__ 1F2021 - -#define GTCCR _SFR_IO8(0x23) -#define PSR10 0 -#define PSR2 1 -#define TSM 7 - -#define TCCR0A _SFR_IO8(0x24) -#define CS00 0 -#define CS01 1 -#define CS02 2 -#define WGM01 3 -#define COM0A0 4 -#define COM0A1 5 -#define WGM00 6 -#define FOC0A 7 - -/* Reserved [0x25] */ - -#define TCNT0 _SFR_IO8(0X26) - -#define OCR0A _SFR_IO8(0X27) - -/* Reserved [0x28..0x29] */ - -#define GPIOR1 _SFR_IO8(0x2A) - -#define GPIOR2 _SFR_IO8(0x2B) - -#define SPCR _SFR_IO8(0x2C) -#define SPR0 0 -#define SPR1 1 -#define CPHA 2 -#define CPOL 3 -#define MSTR 4 -#define DORD 5 -#define SPE 6 -#define SPIE 7 - -#define SPSR _SFR_IO8(0x2D) -#define SPI2X 0 -#define WCOL 6 -#define SPIF 7 - -#define SPDR _SFR_IO8(0X2E) - -/* Reserved [0x2F] */ - -#define ACSR _SFR_IO8(0x30) -#define ACIS0 0 -#define ACIS1 1 -#define ACIC 2 -#define ACIE 3 -#define ACI 4 -#define ACO 5 -#define ACBG 6 -#define ACD 7 - -#define OCDR _SFR_IO8(0x31) -#define OCDR0 0 -#define OCDR1 1 -#define OCDR2 2 -#define OCDR3 3 -#define OCDR4 4 -#define OCDR5 5 -#define OCDR6 6 -#define OCD 7 // The datasheet defines this but IMO it should be OCDR7. -#define OCDR7 7 -#define IDRD 7 - -/* Reserved [0x32] */ - -#define SMCR _SFR_IO8(0x33) -#define SE 0 -#define SM0 1 -#define SM1 2 -#define SM2 3 - -#define MCUSR _SFR_IO8(0x34) -#define PORF 0 -#define EXTRF 1 -#define BORF 2 -#define WDRF 3 -#define JTRF 4 - -#define MCUCR _SFR_IO8(0X35) -#define IVCE 0 -#define IVSEL 1 -#define PUD 4 -#define JTD 7 - -/* Reserved [0x36] */ - -#define SPMCSR _SFR_IO8(0x37) -#define SPMEN 0 -#define PGERS 1 -#define PGWRT 2 -#define BLBSET 3 -#define RWWSRE 4 -#define RWWSB 6 -#define SPMIE 7 - -/* Reserved [0x38..0x3C] */ - -/* SP [0x3D..0x3E] */ -/* SREG [0x3F] */ - -#define WDTCR _SFR_MEM8(0x60) -#define WDP0 0 -#define WDP1 1 -#define WDP2 2 -#define WDE 3 -#define WDCE 4 - -#define CLKPR _SFR_MEM8(0x61) -#define CLKPS0 0 -#define CLKPS1 1 -#define CLKPS2 2 -#define CLKPS3 3 -#define CLKPCE 7 - -/* Reserved [0x62..0x63] */ - -#define PRR _SFR_MEM8(0x64) -#define PRADC 0 -#define PRUSART0 1 -#define PRSPI 2 -#define PRTIM1 3 - -#define __AVR_HAVE_PRR ((1< instead of this file." -#endif - -#ifndef _AVR_IOXXX_H_ -# define _AVR_IOXXX_H_ "iom165pa.h" -#else -# error "Attempt to include more than one file." -#endif - -/* Registers and associated bit numbers */ - -#define PINA _SFR_IO8(0x00) -#define PINA7 7 -#define PINA6 6 -#define PINA5 5 -#define PINA4 4 -#define PINA3 3 -#define PINA2 2 -#define PINA1 1 -#define PINA0 0 - -#define DDRA _SFR_IO8(0x01) -#define DDRA7 7 -// Inserted "DDA7" from "DDRA7" due to compatibility -#define DDA7 7 -#define DDRA6 6 -// Inserted "DDA6" from "DDRA6" due to compatibility -#define DDA6 6 -#define DDRA5 5 -// Inserted "DDA5" from "DDRA5" due to compatibility -#define DDA5 5 -#define DDRA4 4 -// Inserted "DDA4" from "DDRA4" due to compatibility -#define DDA4 4 -#define DDRA3 3 -// Inserted "DDA3" from "DDRA3" due to compatibility -#define DDA3 3 -#define DDRA2 2 -// Inserted "DDA2" from "DDRA2" due to compatibility -#define DDA2 2 -#define DDRA1 1 -// Inserted "DDA1" from "DDRA1" due to compatibility -#define DDA1 1 -#define DDRA0 0 -// Inserted "DDA0" from "DDRA0" due to compatibility -#define DDA0 0 - -#define PORTA _SFR_IO8(0x02) -#define PORTA7 7 -#define PORTA6 6 -#define PORTA5 5 -#define PORTA4 4 -#define PORTA3 3 -#define PORTA2 2 -#define PORTA1 1 -#define PORTA0 0 - -#define PINB _SFR_IO8(0x03) -#define PINB7 7 -#define PINB6 6 -#define PINB5 5 -#define PINB4 4 -#define PINB3 3 -#define PINB2 2 -#define PINB1 1 -#define PINB0 0 - -#define DDRB _SFR_IO8(0x04) -#define DDRB7 7 -// Inserted "DDB7" from "DDRB7" due to compatibility -#define DDB7 7 -#define DDRB6 6 -// Inserted "DDB6" from "DDRB6" due to compatibility -#define DDB6 6 -#define DDRB5 5 -// Inserted "DDB5" from "DDRB5" due to compatibility -#define DDB5 5 -#define DDRB4 4 -// Inserted "DDB4" from "DDRB4" due to compatibility -#define DDB4 4 -#define DDRB3 3 -// Inserted "DDB3" from "DDRB3" due to compatibility -#define DDB3 3 -#define DDRB2 2 -// Inserted "DDB2" from "DDRB2" due to compatibility -#define DDB2 2 -#define DDRB1 1 -// Inserted "DDB1" from "DDRB1" due to compatibility -#define DDB1 1 -#define DDRB0 0 -// Inserted "DDB0" from "DDRB0" due to compatibility -#define DDB0 0 - -#define PORTB _SFR_IO8(0x05) -#define PORTB7 7 -#define PORTB6 6 -#define PORTB5 5 -#define PORTB4 4 -#define PORTB3 3 -#define PORTB2 2 -#define PORTB1 1 -#define PORTB0 0 - -#define PINC _SFR_IO8(0x06) -#define PINC7 7 -#define PINC6 6 -#define PINC5 5 -#define PINC4 4 -#define PINC3 3 -#define PINC2 2 -#define PINC1 1 -#define PINC0 0 - -#define DDRC _SFR_IO8(0x07) -#define DDRC7 7 -// Inserted "DDC7" from "DDRC7" due to compatibility -#define DDC7 7 -#define DDRC6 6 -// Inserted "DDC6" from "DDRC6" due to compatibility -#define DDC6 6 -#define DDRC5 5 -// Inserted "DDC5" from "DDRC5" due to compatibility -#define DDC5 5 -#define DDRC4 4 -// Inserted "DDC4" from "DDRC4" due to compatibility -#define DDC4 4 -#define DDRC3 3 -// Inserted "DDC3" from "DDRC3" due to compatibility -#define DDC3 3 -#define DDRC2 2 -// Inserted "DDC2" from "DDRC2" due to compatibility -#define DDC2 2 -#define DDRC1 1 -// Inserted "DDC1" from "DDRC1" due to compatibility -#define DDC1 1 -#define DDRC0 0 -// Inserted "DDC0" from "DDRC0" due to compatibility -#define DDC0 0 - -#define PORTC _SFR_IO8(0x08) -#define PORTC7 7 -#define PORTC6 6 -#define PORTC5 5 -#define PORTC4 4 -#define PORTC3 3 -#define PORTC2 2 -#define PORTC1 1 -#define PORTC0 0 - -#define PIND _SFR_IO8(0x09) -#define PIND7 7 -#define PIND6 6 -#define PIND5 5 -#define PIND4 4 -#define PIND3 3 -#define PIND2 2 -#define PIND1 1 -#define PIND0 0 - -#define DDRD _SFR_IO8(0x0A) -#define DDRD7 7 -// Inserted "DDD7" from "DDRD7" due to compatibility -#define DDD7 7 -#define DDRD6 6 -// Inserted "DDD6" from "DDRD6" due to compatibility -#define DDD6 6 -#define DDRD5 5 -// Inserted "DDD5" from "DDRD5" due to compatibility -#define DDD5 5 -#define DDRD4 4 -// Inserted "DDD4" from "DDRD4" due to compatibility -#define DDD4 4 -#define DDRD3 3 -// Inserted "DDD3" from "DDRD3" due to compatibility -#define DDD3 3 -#define DDRD2 2 -// Inserted "DDD2" from "DDRD2" due to compatibility -#define DDD2 2 -#define DDRD1 1 -// Inserted "DDD1" from "DDRD1" due to compatibility -#define DDD1 1 -#define DDRD0 0 -// Inserted "DDD0" from "DDRD0" due to compatibility -#define DDD0 0 - -#define PORTD _SFR_IO8(0x0B) -#define PORTD7 7 -#define PORTD6 6 -#define PORTD5 5 -#define PORTD4 4 -#define PORTD3 3 -#define PORTD2 2 -#define PORTD1 1 -#define PORTD0 0 - -#define PINE _SFR_IO8(0x0C) -#define PINE7 7 -#define PINE6 6 -#define PINE5 5 -#define PINE4 4 -#define PINE3 3 -#define PINE2 2 -#define PINE1 1 -#define PINE0 0 - -#define DDRE _SFR_IO8(0x0D) -#define DDRE7 7 -// Inserted "DDE7" from "DDRE7" due to compatibility -#define DDE7 7 -#define DDRE6 6 -// Inserted "DDE6" from "DDRE6" due to compatibility -#define DDE6 6 -#define DDRE5 5 -// Inserted "DDE5" from "DDRE5" due to compatibility -#define DDE5 5 -#define DDRE4 4 -// Inserted "DDE4" from "DDRE4" due to compatibility -#define DDE4 4 -#define DDRE3 3 -// Inserted "DDE3" from "DDRE3" due to compatibility -#define DDE3 3 -#define DDRE2 2 -// Inserted "DDE2" from "DDRE2" due to compatibility -#define DDE2 2 -#define DDRE1 1 -// Inserted "DDE1" from "DDRE1" due to compatibility -#define DDE1 1 -#define DDRE0 0 -// Inserted "DDE0" from "DDRE0" due to compatibility -#define DDE0 0 - -#define PORTE _SFR_IO8(0x0E) -#define PORTE7 7 -#define PORTE6 6 -#define PORTE5 5 -#define PORTE4 4 -#define PORTE3 3 -#define PORTE2 2 -#define PORTE1 1 -#define PORTE0 0 - -#define PINF _SFR_IO8(0x0F) -#define PINF7 7 -#define PINF6 6 -#define PINF5 5 -#define PINF4 4 -#define PINF3 3 -#define PINF2 2 -#define PINF1 1 -#define PINF0 0 - -#define DDRF _SFR_IO8(0x10) -#define DDRF7 7 -// Inserted "DDF7" from "DDRF7" due to compatibility -#define DDF7 7 -#define DDRF6 6 -// Inserted "DDF6" from "DDRF6" due to compatibility -#define DDF6 6 -#define DDRF5 5 -// Inserted "DDF5" from "DDRF5" due to compatibility -#define DDF5 5 -#define DDRF4 4 -// Inserted "DDF4" from "DDRF4" due to compatibility -#define DDF4 4 -#define DDRF3 3 -// Inserted "DDF3" from "DDRF3" due to compatibility -#define DDF3 3 -#define DDRF2 2 -// Inserted "DDF2" from "DDRF2" due to compatibility -#define DDF2 2 -#define DDRF1 1 -// Inserted "DDF1" from "DDRF1" due to compatibility -#define DDF1 1 -#define DDRF0 0 -// Inserted "DDF0" from "DDRF0" due to compatibility -#define DDF0 0 - -#define PORTF _SFR_IO8(0x11) -#define PORTF7 7 -#define PORTF6 6 -#define PORTF5 5 -#define PORTF4 4 -#define PORTF3 3 -#define PORTF2 2 -#define PORTF1 1 -#define PORTF0 0 - -#define PING _SFR_IO8(0x12) -#define PING5 5 -#define PING4 4 -#define PING3 3 -#define PING2 2 -#define PING1 1 -#define PING0 0 - -#define DDRG _SFR_IO8(0x13) -#define DDRG4 4 -// Inserted "DDG4" from "DDRG4" due to compatibility -#define DDG4 4 -#define DDRG3 3 -// Inserted "DDG3" from "DDRG3" due to compatibility -#define DDG3 3 -#define DDRG2 2 -// Inserted "DDG2" from "DDRG2" due to compatibility -#define DDG2 2 -#define DDRG1 1 -// Inserted "DDG1" from "DDRG1" due to compatibility -#define DDG1 1 -#define DDRG0 0 -// Inserted "DDG0" from "DDRG0" due to compatibility -#define DDG0 0 - -#define PORTG _SFR_IO8(0x14) -#define PORTG4 4 -#define PORTG3 3 -#define PORTG2 2 -#define PORTG1 1 -#define PORTG0 0 - -#define TIFR0 _SFR_IO8(0x15) -#define TOV0 0 -#define OCF0A 1 - -#define TIFR1 _SFR_IO8(0x16) -#define TOV1 0 -#define OCF1A 1 -#define OCF1B 2 -#define ICF1 5 - -#define TIFR2 _SFR_IO8(0x17) -#define TOV2 0 -#define OCF2A 1 - -/* Reserved [0x18..0x1B] */ - -#define EIFR _SFR_IO8(0x1C) -#define INTF0 0 -#define PCIF0 4 -#define PCIF1 5 - -#define EIMSK _SFR_IO8(0x1D) -#define INT0 0 -#define PCIE0 4 -#define PCIE1 5 - -#define GPIOR0 _SFR_IO8(0x1E) - -#define EECR _SFR_IO8(0x1F) -#define EERE 0 -#define EEWE 1 -#define EEMWE 2 -#define EERIE 3 - -#define EEDR _SFR_IO8(0x20) - -/* Combine EEARL and EEARH */ -#define EEAR _SFR_IO16(0x21) - -#define EEARL _SFR_IO8(0x21) -#define EEARH _SFR_IO8(0x22) - -#define GTCCR _SFR_IO8(0x23) -#define PSR310 0 -#define TSM 7 -#define PSR2 1 - -#define TCCR0A _SFR_IO8(0x24) -#define CS00 0 -#define CS01 1 -#define CS02 2 -#define WGM01 3 -#define COM0A0 4 -#define COM0A1 5 -#define WGM00 6 -#define FOC0A 7 - -/* Reserved [0x25] */ - -#define TCNT0 _SFR_IO8(0x26) - -#define OCR0A _SFR_IO8(0x27) - -/* Reserved [0x28..0x29] */ - -#define GPIOR1 _SFR_IO8(0x2A) - -#define GPIOR2 _SFR_IO8(0x2B) - -#define SPCR _SFR_IO8(0x2C) -#define SPR0 0 -#define SPR1 1 -#define CPHA 2 -#define CPOL 3 -#define MSTR 4 -#define DORD 5 -#define SPE 6 -#define SPIE 7 - -#define SPSR _SFR_IO8(0x2D) -#define SPI2X 0 -#define WCOL 6 -#define SPIF 7 - -#define SPDR _SFR_IO8(0x2E) - -/* Reserved [0x2F] */ - -#define ACSR _SFR_IO8(0x30) -#define ACIS0 0 -#define ACIS1 1 -#define ACIC 2 -#define ACIE 3 -#define ACI 4 -#define ACO 5 -#define ACBG 6 -#define ACD 7 - -#define OCDR _SFR_IO8(0x31) -#define OCDR7 7 -#define OCDR6 6 -#define OCDR5 5 -#define OCDR4 4 -#define OCDR3 3 -#define OCDR2 2 -#define OCDR1 1 -#define OCDR0 0 - -/* Reserved [0x32] */ - -#define SMCR _SFR_IO8(0x33) -#define SE 0 -#define SM0 1 -#define SM1 2 -#define SM2 3 - -#define MCUSR _SFR_IO8(0x34) -#define JTRF 4 -#define PORF 0 -#define EXTRF 1 -#define BORF 2 -#define WDRF 3 - -#define MCUCR _SFR_IO8(0x35) -#define JTD 7 -#define IVCE 0 -#define IVSEL 1 -#define PUD 4 -#define BODSE 5 -#define BODS 6 - -/* Reserved [0x36] */ - -#define SPMCSR _SFR_IO8(0x37) -#define SPMEN 0 -#define PGERS 1 -#define PGWRT 2 -#define BLBSET 3 -#define RWWSRE 4 -#define RWWSB 6 -#define SPMIE 7 - -/* Reserved [0x38..0x3C] */ - -/* SP [0x3D..0x3E] */ - -/* SREG [0x3F] */ - -#define WDTCR _SFR_MEM8(0x60) -#define WDP0 0 -#define WDP1 1 -#define WDP2 2 -#define WDE 3 -#define WDCE 4 - -#define CLKPR _SFR_MEM8(0x61) -#define CLKPS0 0 -#define CLKPS1 1 -#define CLKPS2 2 -#define CLKPS3 3 -#define CLKPCE 7 - -/* Reserved [0x62..0x63] */ - -#define PRR _SFR_MEM8(0x64) -#define PRADC 0 -#define PRUSART0 1 -#define PRSPI 2 -#define PRTIM1 3 - -#define __AVR_HAVE_PRR ((1< - -/* Constants */ -#define SPM_PAGESIZE 128 -#define RAMSTART (0x100) -#define RAMEND 0x4FF -#define XRAMEND RAMEND -#define E2END 0x1FF -#define E2PAGESIZE 4 -#define FLASHEND 0x3FFF - - -/* Fuses */ -#define FUSE_MEMORY_SIZE 3 - -/* Low Fuse Byte */ -#define FUSE_CKSEL0 (unsigned char)~_BV(0) /* Select Clock Source */ -#define FUSE_CKSEL1 (unsigned char)~_BV(1) /* Select Clock Source */ -#define FUSE_CKSEL2 (unsigned char)~_BV(2) /* Select Clock Source */ -#define FUSE_CKSEL3 (unsigned char)~_BV(3) /* Select Clock Source */ -#define FUSE_SUT0 (unsigned char)~_BV(4) /* Select start-up time */ -#define FUSE_SUT1 (unsigned char)~_BV(5) /* Select start-up time */ -#define FUSE_CKOUT (unsigned char)~_BV(6) /* Clock output */ -#define FUSE_CKDIV8 (unsigned char)~_BV(7) /* Divide clock by 8 */ -#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8) - -/* High Fuse Byte */ -#define FUSE_BODLEVEL0 (unsigned char)~_BV(0) /* Brown-out Detector trigger level */ -#define FUSE_BODLEVEL1 (unsigned char)~_BV(1) /* Brown-out Detector trigger level */ -#define FUSE_BODLEVEL2 (unsigned char)~_BV(2) /* Brown-out Detector trigger level */ -#define FUSE_EESAVE (unsigned char)~_BV(3) /* EEPROM memory is preserved through chip erase */ -#define FUSE_WDTON (unsigned char)~_BV(4) /* Watchdog Timer Always On */ -#define FUSE_SPIEN (unsigned char)~_BV(5) /* Enable Serial programming and Data Downloading */ -#define FUSE_DWEN (unsigned char)~_BV(6) /* debugWIRE Enable */ -#define FUSE_RSTDISBL (unsigned char)~_BV(7) /* External reset disable */ -#define HFUSE_DEFAULT (FUSE_SPIEN) - -/* Extended Fuse Byte */ -#define FUSE_BOOTRST (unsigned char)~_BV(0) -#define FUSE_BOOTSZ0 (unsigned char)~_BV(1) -#define FUSE_BOOTSZ1 (unsigned char)~_BV(2) -#define EFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1) - - -/* Lock Bits */ -#define __LOCK_BITS_EXIST -#define __BOOT_LOCK_BITS_0_EXIST -#define __BOOT_LOCK_BITS_1_EXIST - - -/* Signature */ -#define SIGNATURE_0 0x1E -#define SIGNATURE_1 0x94 -#define SIGNATURE_2 0x06 - -#define SLEEP_MODE_IDLE (0x00<<1) -#define SLEEP_MODE_ADC (0x01<<1) -#define SLEEP_MODE_PWR_DOWN (0x02<<1) -#define SLEEP_MODE_PWR_SAVE (0x03<<1) -#define SLEEP_MODE_STANDBY (0x06<<1) - -#endif /* _AVR_IOM168_H_ */ diff --git a/arduino/hardware/tools/avr/avr/include/avr/iom168a.h b/arduino/hardware/tools/avr/avr/include/avr/iom168a.h deleted file mode 100644 index 3438434..0000000 --- a/arduino/hardware/tools/avr/avr/include/avr/iom168a.h +++ /dev/null @@ -1,35 +0,0 @@ -/***************************************************************************** - * - * Copyright (C) 2011 Atmel Corporation - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * - * * Neither the name of the copyright holders nor the names of - * contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - ****************************************************************************/ - -#include "iom168.h" -#define SLEEP_MODE_EXT_STANDBY (0x07<<1) diff --git a/arduino/hardware/tools/avr/avr/include/avr/iom168p.h b/arduino/hardware/tools/avr/avr/include/avr/iom168p.h deleted file mode 100644 index 78a8e3a..0000000 --- a/arduino/hardware/tools/avr/avr/include/avr/iom168p.h +++ /dev/null @@ -1,942 +0,0 @@ -/* Copyright (c) 2007 Atmel Corporation - All rights reserved. - - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - * Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - * Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in - the documentation and/or other materials provided with the - distribution. - - * Neither the name of the copyright holders nor the names of - contributors may be used to endorse or promote products derived - from this software without specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. -*/ - -/* $Id: iom168p.h 2225 2011-03-02 16:27:26Z arcanum $ */ - -/* avr/iom168p.h - definitions for ATmega168P. */ - -/* This file should only be included from , never directly. */ - -#ifndef _AVR_IO_H_ -# error "Include instead of this file." -#endif - -#ifndef _AVR_IOXXX_H_ -# define _AVR_IOXXX_H_ "iom168p.h" -#else -# error "Attempt to include more than one file." -#endif - - -#ifndef _AVR_IOM168P_H_ -#define _AVR_IOM168P_H_ 1 - -/* Registers and associated bit numbers */ - -#define PINB _SFR_IO8(0x03) -#define PINB0 0 -#define PINB1 1 -#define PINB2 2 -#define PINB3 3 -#define PINB4 4 -#define PINB5 5 -#define PINB6 6 -#define PINB7 7 - -#define DDRB _SFR_IO8(0x04) -#define DDB0 0 -#define DDB1 1 -#define DDB2 2 -#define DDB3 3 -#define DDB4 4 -#define DDB5 5 -#define DDB6 6 -#define DDB7 7 - -#define PORTB _SFR_IO8(0x05) -#define PORTB0 0 -#define PORTB1 1 -#define PORTB2 2 -#define PORTB3 3 -#define PORTB4 4 -#define PORTB5 5 -#define PORTB6 6 -#define PORTB7 7 - -#define PINC _SFR_IO8(0x06) -#define PINC0 0 -#define PINC1 1 -#define PINC2 2 -#define PINC3 3 -#define PINC4 4 -#define PINC5 5 -#define PINC6 6 - -#define DDRC _SFR_IO8(0x07) -#define DDC0 0 -#define DDC1 1 -#define DDC2 2 -#define DDC3 3 -#define DDC4 4 -#define DDC5 5 -#define DDC6 6 - -#define PORTC _SFR_IO8(0x08) -#define PORTC0 0 -#define PORTC1 1 -#define PORTC2 2 -#define PORTC3 3 -#define PORTC4 4 -#define PORTC5 5 -#define PORTC6 6 - -#define PIND _SFR_IO8(0x09) -#define PIND0 0 -#define PIND1 1 -#define PIND2 2 -#define PIND3 3 -#define PIND4 4 -#define PIND5 5 -#define PIND6 6 -#define PIND7 7 - -#define DDRD _SFR_IO8(0x0A) -#define DDD0 0 -#define DDD1 1 -#define DDD2 2 -#define DDD3 3 -#define DDD4 4 -#define DDD5 5 -#define DDD6 6 -#define DDD7 7 - -#define PORTD _SFR_IO8(0x0B) -#define PORTD0 0 -#define PORTD1 1 -#define PORTD2 2 -#define PORTD3 3 -#define PORTD4 4 -#define PORTD5 5 -#define PORTD6 6 -#define PORTD7 7 - -#define TIFR0 _SFR_IO8(0x15) -#define TOV0 0 -#define OCF0A 1 -#define OCF0B 2 - -#define TIFR1 _SFR_IO8(0x16) -#define TOV1 0 -#define OCF1A 1 -#define OCF1B 2 -#define ICF1 5 - -#define TIFR2 _SFR_IO8(0x17) -#define TOV2 0 -#define OCF2A 1 -#define OCF2B 2 - -#define PCIFR _SFR_IO8(0x1B) -#define PCIF0 0 -#define PCIF1 1 -#define PCIF2 2 - -#define EIFR _SFR_IO8(0x1C) -#define INTF0 0 -#define INTF1 1 - -#define EIMSK _SFR_IO8(0x1D) -#define INT0 0 -#define INT1 1 - -#define GPIOR0 _SFR_IO8(0x1E) -#define GPIOR00 0 -#define GPIOR01 1 -#define GPIOR02 2 -#define GPIOR03 3 -#define GPIOR04 4 -#define GPIOR05 5 -#define GPIOR06 6 -#define GPIOR07 7 - -#define EECR _SFR_IO8(0x1F) -#define EERE 0 -#define EEPE 1 -#define EEMPE 2 -#define EERIE 3 -#define EEPM0 4 -#define EEPM1 5 - -#define EEDR _SFR_IO8(0x20) -#define EEDR0 0 -#define EEDR1 1 -#define EEDR2 2 -#define EEDR3 3 -#define EEDR4 4 -#define EEDR5 5 -#define EEDR6 6 -#define EEDR7 7 - -#define EEAR _SFR_IO16(0x21) - -#define EEARL _SFR_IO8(0x21) -#define EEAR0 0 -#define EEAR1 1 -#define EEAR2 2 -#define EEAR3 3 -#define EEAR4 4 -#define EEAR5 5 -#define EEAR6 6 -#define EEAR7 7 - -#define EEARH _SFR_IO8(0x22) -#define EEAR8 0 - -#define EEPROM_REG_LOCATIONS 1F2021 - -#define GTCCR _SFR_IO8(0x23) -#define PSRSYNC 0 -#define PSRASY 1 -#define TSM 7 - -#define TCCR0A _SFR_IO8(0x24) -#define WGM00 0 -#define WGM01 1 -#define COM0B0 4 -#define COM0B1 5 -#define COM0A0 6 -#define COM0A1 7 - -#define TCCR0B _SFR_IO8(0x25) -#define CS00 0 -#define CS01 1 -#define CS02 2 -#define WGM02 3 -#define FOC0B 6 -#define FOC0A 7 - -#define TCNT0 _SFR_IO8(0x26) -#define TCNT0_0 0 -#define TCNT0_1 1 -#define TCNT0_2 2 -#define TCNT0_3 3 -#define TCNT0_4 4 -#define TCNT0_5 5 -#define TCNT0_6 6 -#define TCNT0_7 7 - -#define OCR0A _SFR_IO8(0x27) -#define OCR0A_0 0 -#define OCR0A_1 1 -#define OCR0A_2 2 -#define OCR0A_3 3 -#define OCR0A_4 4 -#define OCR0A_5 5 -#define OCR0A_6 6 -#define OCR0A_7 7 - -#define OCR0B _SFR_IO8(0x28) -#define OCR0B_0 0 -#define OCR0B_1 1 -#define OCR0B_2 2 -#define OCR0B_3 3 -#define OCR0B_4 4 -#define OCR0B_5 5 -#define OCR0B_6 6 -#define OCR0B_7 7 - -#define GPIOR1 _SFR_IO8(0x2A) -#define GPIOR10 0 -#define GPIOR11 1 -#define GPIOR12 2 -#define GPIOR13 3 -#define GPIOR14 4 -#define GPIOR15 5 -#define GPIOR16 6 -#define GPIOR17 7 - -#define GPIOR2 _SFR_IO8(0x2B) -#define GPIOR20 0 -#define GPIOR21 1 -#define GPIOR22 2 -#define GPIOR23 3 -#define GPIOR24 4 -#define GPIOR25 5 -#define GPIOR26 6 -#define GPIOR27 7 - -#define SPCR _SFR_IO8(0x2C) -#define SPR0 0 -#define SPR1 1 -#define CPHA 2 -#define CPOL 3 -#define MSTR 4 -#define DORD 5 -#define SPE 6 -#define SPIE 7 - -#define SPSR _SFR_IO8(0x2D) -#define SPI2X 0 -#define WCOL 6 -#define SPIF 7 - -#define SPDR _SFR_IO8(0x2E) -#define SPDR0 0 -#define SPDR1 1 -#define SPDR2 2 -#define SPDR3 3 -#define SPDR4 4 -#define SPDR5 5 -#define SPDR6 6 -#define SPDR7 7 - -#define ACSR _SFR_IO8(0x30) -#define ACIS0 0 -#define ACIS1 1 -#define ACIC 2 -#define ACIE 3 -#define ACI 4 -#define ACO 5 -#define ACBG 6 -#define ACD 7 - -#define SMCR _SFR_IO8(0x33) -#define SE 0 -#define SM0 1 -#define SM1 2 -#define SM2 3 - -#define MCUSR _SFR_IO8(0x34) -#define PORF 0 -#define EXTRF 1 -#define BORF 2 -#define WDRF 3 - -#define MCUCR _SFR_IO8(0x35) -#define IVCE 0 -#define IVSEL 1 -#define PUD 4 -#define BODSE 5 -#define BODS 6 - -#define SPMCSR _SFR_IO8(0x37) -#define SELFPRGEN 0 -#define SPMEN 0 -#define PGERS 1 -#define PGWRT 2 -#define BLBSET 3 -#define RWWSRE 4 -#define SIGRD 5 -#define RWWSB 6 -#define SPMIE 7 - -#define WDTCSR _SFR_MEM8(0x60) -#define WDP0 0 -#define WDP1 1 -#define WDP2 2 -#define WDE 3 -#define WDCE 4 -#define WDP3 5 -#define WDIE 6 -#define WDIF 7 - -#define CLKPR _SFR_MEM8(0x61) -#define CLKPS0 0 -#define CLKPS1 1 -#define CLKPS2 2 -#define CLKPS3 3 -#define CLKPCE 7 - -#define PRR _SFR_MEM8(0x64) -#define PRADC 0 -#define PRUSART0 1 -#define PRSPI 2 -#define PRTIM1 3 -#define PRTIM0 5 -#define PRTIM2 6 -#define PRTWI 7 - -#define __AVR_HAVE_PRR ((1< instead of this file." -#endif - -#ifndef _AVR_IOXXX_H_ -# define _AVR_IOXXX_H_ "iom168pa.h" -#else -# error "Attempt to include more than one file." -#endif - -/* Registers and associated bit numbers */ - -#define PINB _SFR_IO8(0x03) -#define PINB7 7 -#define PINB6 6 -#define PINB5 5 -#define PINB4 4 -#define PINB3 3 -#define PINB2 2 -#define PINB1 1 -#define PINB0 0 - -#define DDRB _SFR_IO8(0x04) -#define DDRB7 7 -// Inserted "DDB7" from "DDRB7" due to compatibility -#define DDB7 7 -#define DDRB6 6 -// Inserted "DDB6" from "DDRB6" due to compatibility -#define DDB6 6 -#define DDRB5 5 -// Inserted "DDB5" from "DDRB5" due to compatibility -#define DDB5 5 -#define DDRB4 4 -// Inserted "DDB4" from "DDRB4" due to compatibility -#define DDB4 4 -#define DDRB3 3 -// Inserted "DDB3" from "DDRB3" due to compatibility -#define DDB3 3 -#define DDRB2 2 -// Inserted "DDB2" from "DDRB2" due to compatibility -#define DDB2 2 -#define DDRB1 1 -// Inserted "DDB1" from "DDRB1" due to compatibility -#define DDB1 1 -#define DDRB0 0 -// Inserted "DDB0" from "DDRB0" due to compatibility -#define DDB0 0 - -#define PORTB _SFR_IO8(0x05) -#define PORTB7 7 -#define PORTB6 6 -#define PORTB5 5 -#define PORTB4 4 -#define PORTB3 3 -#define PORTB2 2 -#define PORTB1 1 -#define PORTB0 0 - -#define PINC _SFR_IO8(0x06) -#define PINC6 6 -#define PINC5 5 -#define PINC4 4 -#define PINC3 3 -#define PINC2 2 -#define PINC1 1 -#define PINC0 0 - -#define DDRC _SFR_IO8(0x07) -#define DDRC6 6 -// Inserted "DDC6" from "DDRC6" due to compatibility -#define DDC6 6 -#define DDRC5 5 -// Inserted "DDC5" from "DDRC5" due to compatibility -#define DDC5 5 -#define DDRC4 4 -// Inserted "DDC4" from "DDRC4" due to compatibility -#define DDC4 4 -#define DDRC3 3 -// Inserted "DDC3" from "DDRC3" due to compatibility -#define DDC3 3 -#define DDRC2 2 -// Inserted "DDC2" from "DDRC2" due to compatibility -#define DDC2 2 -#define DDRC1 1 -// Inserted "DDC1" from "DDRC1" due to compatibility -#define DDC1 1 -#define DDRC0 0 -// Inserted "DDC0" from "DDRC0" due to compatibility -#define DDC0 0 - -#define PORTC _SFR_IO8(0x08) -#define PORTC6 6 -#define PORTC5 5 -#define PORTC4 4 -#define PORTC3 3 -#define PORTC2 2 -#define PORTC1 1 -#define PORTC0 0 - -#define PIND _SFR_IO8(0x09) -#define PIND7 7 -#define PIND6 6 -#define PIND5 5 -#define PIND4 4 -#define PIND3 3 -#define PIND2 2 -#define PIND1 1 -#define PIND0 0 - -#define DDRD _SFR_IO8(0x0A) -#define DDRD7 7 -// Inserted "DDD7" from "DDRD7" due to compatibility -#define DDD7 7 -#define DDRD6 6 -// Inserted "DDD6" from "DDRD6" due to compatibility -#define DDD6 6 -#define DDRD5 5 -// Inserted "DDD5" from "DDRD5" due to compatibility -#define DDD5 5 -#define DDRD4 4 -// Inserted "DDD4" from "DDRD4" due to compatibility -#define DDD4 4 -#define DDRD3 3 -// Inserted "DDD3" from "DDRD3" due to compatibility -#define DDD3 3 -#define DDRD2 2 -// Inserted "DDD2" from "DDRD2" due to compatibility -#define DDD2 2 -#define DDRD1 1 -// Inserted "DDD1" from "DDRD1" due to compatibility -#define DDD1 1 -#define DDRD0 0 -// Inserted "DDD0" from "DDRD0" due to compatibility -#define DDD0 0 - -#define PORTD _SFR_IO8(0x0B) -#define PORTD7 7 -#define PORTD6 6 -#define PORTD5 5 -#define PORTD4 4 -#define PORTD3 3 -#define PORTD2 2 -#define PORTD1 1 -#define PORTD0 0 - -/* Reserved [0x0C..0x14] */ - -#define TIFR0 _SFR_IO8(0x15) -#define TOV0 0 -#define OCF0A 1 -#define OCF0B 2 - -#define TIFR1 _SFR_IO8(0x16) -#define TOV1 0 -#define OCF1A 1 -#define OCF1B 2 -#define ICF1 5 - -#define TIFR2 _SFR_IO8(0x17) -#define TOV2 0 -#define OCF2A 1 -#define OCF2B 2 - -/* Reserved [0x18..0x1A] */ - -#define PCIFR _SFR_IO8(0x1B) -#define PCIF0 0 -#define PCIF1 1 -#define PCIF2 2 - -#define EIFR _SFR_IO8(0x1C) -#define INTF0 0 -#define INTF1 1 - -#define EIMSK _SFR_IO8(0x1D) -#define INT0 0 -#define INT1 1 - -#define GPIOR0 _SFR_IO8(0x1E) - -#define EECR _SFR_IO8(0x1F) -#define EERE 0 -#define EEPE 1 -#define EEMPE 2 -#define EERIE 3 -#define EEPM0 4 -#define EEPM1 5 - -#define EEDR _SFR_IO8(0x20) - -/* Combine EEARL and EEARH */ -#define EEAR _SFR_IO16(0x21) - -#define EEARL _SFR_IO8(0x21) -#define EEARH _SFR_IO8(0x22) - -#define GTCCR _SFR_IO8(0x23) -#define PSRSYNC 0 -#define TSM 7 -#define PSRASY 1 - -#define TCCR0A _SFR_IO8(0x24) -#define WGM00 0 -#define WGM01 1 -#define COM0B0 4 -#define COM0B1 5 -#define COM0A0 6 -#define COM0A1 7 - -#define TCCR0B _SFR_IO8(0x25) -#define CS00 0 -#define CS01 1 -#define CS02 2 -#define WGM02 3 -#define FOC0B 6 -#define FOC0A 7 - -#define TCNT0 _SFR_IO8(0x26) - -#define OCR0A _SFR_IO8(0x27) - -#define OCR0B _SFR_IO8(0x28) - -/* Reserved [0x29] */ - -#define GPIOR1 _SFR_IO8(0x2A) - -#define GPIOR2 _SFR_IO8(0x2B) - -#define SPCR _SFR_IO8(0x2C) -#define SPR0 0 -#define SPR1 1 -#define CPHA 2 -#define CPOL 3 -#define MSTR 4 -#define DORD 5 -#define SPE 6 -#define SPIE 7 - -#define SPSR _SFR_IO8(0x2D) -#define SPI2X 0 -#define WCOL 6 -#define SPIF 7 - -#define SPDR _SFR_IO8(0x2E) - -/* Reserved [0x2F] */ - -#define ACSR _SFR_IO8(0x30) -#define ACIS0 0 -#define ACIS1 1 -#define ACIC 2 -#define ACIE 3 -#define ACI 4 -#define ACO 5 -#define ACBG 6 -#define ACD 7 - -/* Reserved [0x31..0x32] */ - -#define SMCR _SFR_IO8(0x33) -#define SE 0 -#define SM0 1 -#define SM1 2 -#define SM2 3 - -#define MCUSR _SFR_IO8(0x34) -#define PORF 0 -#define EXTRF 1 -#define BORF 2 -#define WDRF 3 - -#define MCUCR _SFR_IO8(0x35) -#define IVCE 0 -#define IVSEL 1 -#define PUD 4 -#define BODSE 5 -#define BODS 6 - -/* Reserved [0x36] */ - -#define SPMCSR _SFR_IO8(0x37) -#define SPMEN 0 -#define PGERS 1 -#define PGWRT 2 -#define BLBSET 3 -#define RWWSRE 4 -#define SIGRD 5 -#define RWWSB 6 -#define SPMIE 7 - -/* Reserved [0x38..0x3C] */ - -/* SP [0x3D..0x3E] */ - -/* SREG [0x3F] */ - -#define WDTCSR _SFR_MEM8(0x60) -#define WDE 3 -#define WDCE 4 -#define WDP0 0 -#define WDP1 1 -#define WDP2 2 -#define WDP3 5 -#define WDIE 6 -#define WDIF 7 - -#define CLKPR _SFR_MEM8(0x61) -#define CLKPS0 0 -#define CLKPS1 1 -#define CLKPS2 2 -#define CLKPS3 3 -#define CLKPCE 7 - -/* Reserved [0x62..0x63] */ - -#define PRR _SFR_MEM8(0x64) -#define PRADC 0 -#define PRUSART0 1 -#define PRSPI 2 -#define PRTIM1 3 -#define PRTIM0 5 -#define PRTIM2 6 -#define PRTWI 7 - -#define __AVR_HAVE_PRR ((1< instead of this file." -#endif - -#ifndef _AVR_IOXXX_H_ -# define _AVR_IOXXX_H_ "iom168pb.h" -#else -# error "Attempt to include more than one file." -#endif - -/* Registers and associated bit numbers */ - -#define PINB _SFR_IO8(0x03) -#define PINB7 7 -#define PINB6 6 -#define PINB5 5 -#define PINB4 4 -#define PINB3 3 -#define PINB2 2 -#define PINB1 1 -#define PINB0 0 - -#define DDRB _SFR_IO8(0x04) -#define DDRB7 7 -// Inserted "DDB7" from "DDRB7" due to compatibility -#define DDB7 7 -#define DDRB6 6 -// Inserted "DDB6" from "DDRB6" due to compatibility -#define DDB6 6 -#define DDRB5 5 -// Inserted "DDB5" from "DDRB5" due to compatibility -#define DDB5 5 -#define DDRB4 4 -// Inserted "DDB4" from "DDRB4" due to compatibility -#define DDB4 4 -#define DDRB3 3 -// Inserted "DDB3" from "DDRB3" due to compatibility -#define DDB3 3 -#define DDRB2 2 -// Inserted "DDB2" from "DDRB2" due to compatibility -#define DDB2 2 -#define DDRB1 1 -// Inserted "DDB1" from "DDRB1" due to compatibility -#define DDB1 1 -#define DDRB0 0 -// Inserted "DDB0" from "DDRB0" due to compatibility -#define DDB0 0 - -#define PORTB _SFR_IO8(0x05) -#define PORTB7 7 -#define PORTB6 6 -#define PORTB5 5 -#define PORTB4 4 -#define PORTB3 3 -#define PORTB2 2 -#define PORTB1 1 -#define PORTB0 0 - -#define PINC _SFR_IO8(0x06) -#define PINC6 6 -#define PINC5 5 -#define PINC4 4 -#define PINC3 3 -#define PINC2 2 -#define PINC1 1 -#define PINC0 0 - -#define DDRC _SFR_IO8(0x07) -#define DDRC6 6 -// Inserted "DDC6" from "DDRC6" due to compatibility -#define DDC6 6 -#define DDRC5 5 -// Inserted "DDC5" from "DDRC5" due to compatibility -#define DDC5 5 -#define DDRC4 4 -// Inserted "DDC4" from "DDRC4" due to compatibility -#define DDC4 4 -#define DDRC3 3 -// Inserted "DDC3" from "DDRC3" due to compatibility -#define DDC3 3 -#define DDRC2 2 -// Inserted "DDC2" from "DDRC2" due to compatibility -#define DDC2 2 -#define DDRC1 1 -// Inserted "DDC1" from "DDRC1" due to compatibility -#define DDC1 1 -#define DDRC0 0 -// Inserted "DDC0" from "DDRC0" due to compatibility -#define DDC0 0 - -#define PORTC _SFR_IO8(0x08) -#define PORTC6 6 -#define PORTC5 5 -#define PORTC4 4 -#define PORTC3 3 -#define PORTC2 2 -#define PORTC1 1 -#define PORTC0 0 - -#define PIND _SFR_IO8(0x09) -#define PIND7 7 -#define PIND6 6 -#define PIND5 5 -#define PIND4 4 -#define PIND3 3 -#define PIND2 2 -#define PIND1 1 -#define PIND0 0 - -#define DDRD _SFR_IO8(0x0A) -#define DDRD7 7 -// Inserted "DDD7" from "DDRD7" due to compatibility -#define DDD7 7 -#define DDRD6 6 -// Inserted "DDD6" from "DDRD6" due to compatibility -#define DDD6 6 -#define DDRD5 5 -// Inserted "DDD5" from "DDRD5" due to compatibility -#define DDD5 5 -#define DDRD4 4 -// Inserted "DDD4" from "DDRD4" due to compatibility -#define DDD4 4 -#define DDRD3 3 -// Inserted "DDD3" from "DDRD3" due to compatibility -#define DDD3 3 -#define DDRD2 2 -// Inserted "DDD2" from "DDRD2" due to compatibility -#define DDD2 2 -#define DDRD1 1 -// Inserted "DDD1" from "DDRD1" due to compatibility -#define DDD1 1 -#define DDRD0 0 -// Inserted "DDD0" from "DDRD0" due to compatibility -#define DDD0 0 - -#define PORTD _SFR_IO8(0x0B) -#define PORTD7 7 -#define PORTD6 6 -#define PORTD5 5 -#define PORTD4 4 -#define PORTD3 3 -#define PORTD2 2 -#define PORTD1 1 -#define PORTD0 0 - -#define PINE _SFR_IO8(0x0C) -#define PINE3 3 -#define PINE2 2 -#define PINE1 1 -#define PINE0 0 - -#define DDRE _SFR_IO8(0x0D) -#define DDRE3 3 -// Inserted "DDE3" from "DDRE3" due to compatibility -#define DDE3 3 -#define DDRE2 2 -// Inserted "DDE2" from "DDRE2" due to compatibility -#define DDE2 2 -#define DDRE1 1 -// Inserted "DDE1" from "DDRE1" due to compatibility -#define DDE1 1 -#define DDRE0 0 -// Inserted "DDE0" from "DDRE0" due to compatibility -#define DDE0 0 - -#define PORTE _SFR_IO8(0x0E) -#define PORTE3 3 -#define PORTE2 2 -#define PORTE1 1 -#define PORTE0 0 - -#define ACSRB _SFR_IO8(0x0F) -#define ACOE 0 - -/* Reserved [0x10..0x14] */ - -#define TIFR0 _SFR_IO8(0x15) -#define TOV0 0 -#define OCF0A 1 -#define OCF0B 2 - -#define TIFR1 _SFR_IO8(0x16) -#define TOV1 0 -#define OCF1A 1 -#define OCF1B 2 -#define ICF1 5 - -#define TIFR2 _SFR_IO8(0x17) -#define TOV2 0 -#define OCF2A 1 -#define OCF2B 2 - -/* Reserved [0x18..0x1A] */ - -#define PCIFR _SFR_IO8(0x1B) -#define PCIF0 0 -#define PCIF1 1 -#define PCIF2 2 - -#define EIFR _SFR_IO8(0x1C) -#define INTF0 0 -#define INTF1 1 - -#define EIMSK _SFR_IO8(0x1D) -#define INT0 0 -#define INT1 1 - -#define GPIOR0 _SFR_IO8(0x1E) - -#define EECR _SFR_IO8(0x1F) -#define EERE 0 -#define EEPE 1 -#define EEMPE 2 -#define EERIE 3 -#define EEPM0 4 -#define EEPM1 5 - -#define EEDR _SFR_IO8(0x20) - -/* Combine EEARL and EEARH */ -#define EEAR _SFR_IO16(0x21) - -#define EEARL _SFR_IO8(0x21) -#define EEARH _SFR_IO8(0x22) - -#define GTCCR _SFR_IO8(0x23) -#define PSRSYNC 0 -#define TSM 7 -#define PSRASY 1 - -#define TCCR0A _SFR_IO8(0x24) -#define WGM00 0 -#define WGM01 1 -#define COM0B0 4 -#define COM0B1 5 -#define COM0A0 6 -#define COM0A1 7 - -#define TCCR0B _SFR_IO8(0x25) -#define CS00 0 -#define CS01 1 -#define CS02 2 -#define WGM02 3 -#define FOC0B 6 -#define FOC0A 7 - -#define TCNT0 _SFR_IO8(0x26) - -#define OCR0A _SFR_IO8(0x27) - -#define OCR0B _SFR_IO8(0x28) - -/* Reserved [0x29] */ - -#define GPIOR1 _SFR_IO8(0x2A) - -#define GPIOR2 _SFR_IO8(0x2B) - -#define SPCR _SFR_IO8(0x2C) -#define SPR0 0 -#define SPR1 1 -#define CPHA 2 -#define CPOL 3 -#define MSTR 4 -#define DORD 5 -#define SPE 6 -#define SPIE 7 - -#define SPSR _SFR_IO8(0x2D) -#define SPI2X 0 -#define WCOL 6 -#define SPIF 7 - -#define SPDR _SFR_IO8(0x2E) - -/* Reserved [0x2F] */ - -#define ACSR _SFR_IO8(0x30) -#define ACIS0 0 -#define ACIS1 1 -#define ACIC 2 -#define ACIE 3 -#define ACI 4 -#define ACO 5 -#define ACBG 6 -#define ACD 7 - -/* Reserved [0x31..0x32] */ - -#define SMCR _SFR_IO8(0x33) -#define SE 0 -#define SM0 1 -#define SM1 2 -#define SM2 3 - -#define MCUSR _SFR_IO8(0x34) -#define PORF 0 -#define EXTRF 1 -#define BORF 2 -#define WDRF 3 - -#define MCUCR _SFR_IO8(0x35) -#define IVCE 0 -#define IVSEL 1 -#define PUD 4 -#define BODSE 5 -#define BODS 6 - -/* Reserved [0x36] */ - -#define SPMCSR _SFR_IO8(0x37) -#define SPMEN 0 -#define PGERS 1 -#define PGWRT 2 -#define BLBSET 3 -#define RWWSRE 4 -#define SIGRD 5 -#define RWWSB 6 -#define SPMIE 7 - -/* Reserved [0x38..0x3C] */ - -/* SP [0x3D..0x3E] */ - -/* SREG [0x3F] */ - -#define WDTCSR _SFR_MEM8(0x60) -#define WDE 3 -#define WDCE 4 -#define WDP0 0 -#define WDP1 1 -#define WDP2 2 -#define WDP3 5 -#define WDIE 6 -#define WDIF 7 - -#define CLKPR _SFR_MEM8(0x61) -#define CLKPS0 0 -#define CLKPS1 1 -#define CLKPS2 2 -#define CLKPS3 3 -#define CLKPCE 7 - -/* Reserved [0x62..0x63] */ - -#define PRR _SFR_MEM8(0x64) -#define PRADC 0 -#define PRUSART0 1 -#define PRSPI 2 -#define PRTIM1 3 -#define PRTIM0 5 -#define PRTIM2 6 -#define PRTWI 7 - -#define __AVR_HAVE_PRR ((1< - Eric B. Weddington - All rights reserved. - - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - * Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - * Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in - the documentation and/or other materials provided with the - distribution. - - * Neither the name of the copyright holders nor the names of - contributors may be used to endorse or promote products derived - from this software without specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. */ - -/* $Id: iom169.h 2231 2011-03-07 05:06:55Z arcanum $ */ - -/* iom169.h - definitions for ATmega169 */ - -/* This should be up to date with data sheet version 2514J-AVR-12/03. */ - -#ifndef _AVR_IOM169_H_ -#define _AVR_IOM169_H_ 1 - -/* This file should only be included from , never directly. */ - -#ifndef _AVR_IO_H_ -# error "Include instead of this file." -#endif - -#ifndef _AVR_IOXXX_H_ -# define _AVR_IOXXX_H_ "iom169.h" -#else -# error "Attempt to include more than one file." -#endif - -/* I/O registers */ - -/* Port A */ -#define PINA _SFR_IO8(0x00) -#define DDRA _SFR_IO8(0x01) -#define PORTA _SFR_IO8(0x02) - -/* Port B */ -#define PINB _SFR_IO8(0x03) -#define DDRB _SFR_IO8(0x04) -#define PORTB _SFR_IO8(0x05) - -/* Port C */ -#define PINC _SFR_IO8(0x06) -#define DDRC _SFR_IO8(0x07) -#define PORTC _SFR_IO8(0x08) - -/* Port D */ -#define PIND _SFR_IO8(0x09) -#define DDRD _SFR_IO8(0x0A) -#define PORTD _SFR_IO8(0x0B) - -/* Port E */ -#define PINE _SFR_IO8(0x0C) -#define DDRE _SFR_IO8(0x0D) -#define PORTE _SFR_IO8(0x0E) - -/* Port F */ -#define PINF _SFR_IO8(0x0F) -#define DDRF _SFR_IO8(0x10) -#define PORTF _SFR_IO8(0x11) - -/* Port G */ -#define PING _SFR_IO8(0x12) -#define DDRG _SFR_IO8(0x13) -#define PORTG _SFR_IO8(0x14) - -/* Timer/Counter 0 interrupt Flag Register */ -#define TIFR0 _SFR_IO8(0x15) - -/* Timer/Counter 1 interrupt Flag Register */ -#define TIFR1 _SFR_IO8(0x16) - -/* Timer/Counter 2 interrupt Flag Register */ -#define TIFR2 _SFR_IO8(0x17) - -/* External Interrupt Flag Register */ -#define EIFR _SFR_IO8(0x1C) - -/* External Interrupt Mask Register */ -#define EIMSK _SFR_IO8(0x1D) - -/* General Purpose I/O Register 0 */ -#define GPIOR0 _SFR_IO8(0x1E) - -#define EECR _SFR_IO8(0x1F) - -#define EEDR _SFR_IO8(0X20) - -/* Combine EEARL and EEARH */ -#define EEAR _SFR_IO16(0x21) -#define EEARL _SFR_IO8(0x21) -#define EEARH _SFR_IO8(0X22) - -/* 6-char sequence denoting where to find the EEPROM registers in memory space. - Adresses denoted in hex syntax with uppercase letters. Used by the EEPROM - subroutines. - First two letters: EECR address. - Second two letters: EEDR address. - Last two letters: EEAR address. */ -#define __EEPROM_REG_LOCATIONS__ 1F2021 - -/* General Timer/Counter Control Register */ -#define GTCCR _SFR_IO8(0x23) - -/* Timer/Counter Control Register A */ -#define TCCR0A _SFR_IO8(0x24) - -/* Timer/Counter Register */ -#define TCNT0 _SFR_IO8(0x26) - -/* Output Compare Register A */ -#define OCR0A _SFR_IO8(0x27) - -/* General Purpose I/O Register 1 */ -#define GPIOR1 _SFR_IO8(0x2A) - -/* General Purpose I/O Register 2 */ -#define GPIOR2 _SFR_IO8(0x2B) - -/* SPI Control Register */ -#define SPCR _SFR_IO8(0x2C) - -/* SPI Status Register */ -#define SPSR _SFR_IO8(0x2D) - -/* SPI Data Register */ -#define SPDR _SFR_IO8(0x2E) - -/* Analog Comperator Control and Status Register */ -#define ACSR _SFR_IO8(0x30) - -/* On-chip Debug Register */ -#define OCDR _SFR_IO8(0x31) - -/* Sleep Mode Control Register */ -#define SMCR _SFR_IO8(0x33) - -/* MCU Status Register */ -#define MCUSR _SFR_IO8(0x34) - -/* MCU Control Rgeister */ -#define MCUCR _SFR_IO8(0x35) - -/* Store Program Memory Control and Status Register */ -#define SPMCSR _SFR_IO8(0x37) - -/* Watchdog Timer Control Register */ -#define WDTCR _SFR_MEM8(0x60) - -/* Clock Prescale Register */ -#define CLKPR _SFR_MEM8(0x61) - -#define PRR _SFR_MEM8(0x64) -#define PRADC 0 -#define PRUSART0 1 -#define PRSPI 2 -#define PRTIM1 3 -#define PRLCD 4 - -#define __AVR_HAVE_PRR ((1< - Eric B. Weddington - Anatoly Sokolov - All rights reserved. - - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - * Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - * Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in - the documentation and/or other materials provided with the - distribution. - - * Neither the name of the copyright holders nor the names of - contributors may be used to endorse or promote products derived - from this software without specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. */ - -/* $Id: iom169p.h 2231 2011-03-07 05:06:55Z arcanum $ */ - -/* iom169p.h - definitions for ATmega169P */ - -#ifndef _AVR_IOM169P_H_ -#define _AVR_IOM169P_H_ 1 - -/* This file should only be included from , never directly. */ - -#ifndef _AVR_IO_H_ -# error "Include instead of this file." -#endif - -#ifndef _AVR_IOXXX_H_ -# define _AVR_IOXXX_H_ "iom169p.h" -#else -# error "Attempt to include more than one file." -#endif - -/* I/O registers */ - -/* Port A */ -#define PINA _SFR_IO8(0x00) -#define PINA7 7 -#define PINA6 6 -#define PINA5 5 -#define PINA4 4 -#define PINA3 3 -#define PINA2 2 -#define PINA1 1 -#define PINA0 0 - -#define DDRA _SFR_IO8(0x01) -#define DDA7 7 -#define DDA6 6 -#define DDA5 5 -#define DDA4 4 -#define DDA3 3 -#define DDA2 2 -#define DDA1 1 -#define DDA0 0 - -#define PORTA _SFR_IO8(0x02) -#define PA7 7 -#define PA6 6 -#define PA5 5 -#define PA4 4 -#define PA3 3 -#define PA2 2 -#define PA1 1 -#define PA0 0 - -/* Port B */ -#define PINB _SFR_IO8(0x03) -#define PINB7 7 -#define PINB6 6 -#define PINB5 5 -#define PINB4 4 -#define PINB3 3 -#define PINB2 2 -#define PINB1 1 -#define PINB0 0 - -#define DDRB _SFR_IO8(0x04) -#define DDB7 7 -#define DDB6 6 -#define DDB5 5 -#define DDB4 4 -#define DDB3 3 -#define DDB2 2 -#define DDB1 1 -#define DDB0 0 - -#define PORTB _SFR_IO8(0x05) -#define PB7 7 -#define PB6 6 -#define PB5 5 -#define PB4 4 -#define PB3 3 -#define PB2 2 -#define PB1 1 -#define PB0 0 - -/* Port C */ -#define PINC _SFR_IO8(0x06) -#define PINC7 7 -#define PINC6 6 -#define PINC5 5 -#define PINC4 4 -#define PINC3 3 -#define PINC2 2 -#define PINC1 1 -#define PINC0 0 - -#define DDRC _SFR_IO8(0x07) -#define DDC7 7 -#define DDC6 6 -#define DDC5 5 -#define DDC4 4 -#define DDC3 3 -#define DDC2 2 -#define DDC1 1 -#define DDC0 0 - -#define PORTC _SFR_IO8(0x08) -#define PC7 7 -#define PC6 6 -#define PC5 5 -#define PC4 4 -#define PC3 3 -#define PC2 2 -#define PC1 1 -#define PC0 0 - -/* Port D */ -#define PIND _SFR_IO8(0x09) -#define PIND7 7 -#define PIND6 6 -#define PIND5 5 -#define PIND4 4 -#define PIND3 3 -#define PIND2 2 -#define PIND1 1 -#define PIND0 0 - -#define DDRD _SFR_IO8(0x0A) -#define DDD7 7 -#define DDD6 6 -#define DDD5 5 -#define DDD4 4 -#define DDD3 3 -#define DDD2 2 -#define DDD1 1 -#define DDD0 0 - -#define PORTD _SFR_IO8(0x0B) -#define PD7 7 -#define PD6 6 -#define PD5 5 -#define PD4 4 -#define PD3 3 -#define PD2 2 -#define PD1 1 -#define PD0 0 - -/* Port E */ -#define PINE _SFR_IO8(0x0C) -#define PINE7 7 -#define PINE6 6 -#define PINE5 5 -#define PINE4 4 -#define PINE3 3 -#define PINE2 2 -#define PINE1 1 -#define PINE0 0 - -#define DDRE _SFR_IO8(0x0D) -#define DDE7 7 -#define DDE6 6 -#define DDE5 5 -#define DDE4 4 -#define DDE3 3 -#define DDE2 2 -#define DDE1 1 -#define DDE0 0 - -#define PORTE _SFR_IO8(0x0E) -#define PE7 7 -#define PE6 6 -#define PE5 5 -#define PE4 4 -#define PE3 3 -#define PE2 2 -#define PE1 1 -#define PE0 0 - -/* Port F */ -#define PINF _SFR_IO8(0x0F) -#define PINF7 7 -#define PINF6 6 -#define PINF5 5 -#define PINF4 4 -#define PINF3 3 -#define PINF2 2 -#define PINF1 1 -#define PINF0 0 - -#define DDRF _SFR_IO8(0x10) -#define DDF7 7 -#define DDF6 6 -#define DDF5 5 -#define DDF4 4 -#define DDF3 3 -#define DDF2 2 -#define DDF1 1 -#define DDF0 0 - -#define PORTF _SFR_IO8(0x11) -#define PF7 7 -#define PF6 6 -#define PF5 5 -#define PF4 4 -#define PF3 3 -#define PF2 2 -#define PF1 1 -#define PF0 0 - -/* Port G */ -#define PING _SFR_IO8(0x12) -#define PING5 5 -#define PING4 4 -#define PING3 3 -#define PING2 2 -#define PING1 1 -#define PING0 0 - -#define DDRG _SFR_IO8(0x13) -#define DDG4 4 -#define DDG3 3 -#define DDG2 2 -#define DDG1 1 -#define DDG0 0 - -#define PORTG _SFR_IO8(0x14) -#define PG4 4 -#define PG3 3 -#define PG2 2 -#define PG1 1 -#define PG0 0 - -/* Timer/Counter 0 interrupt Flag Register */ -#define TIFR0 _SFR_IO8(0x15) -#define OCF0A 1 -#define TOV0 0 - -/* Timer/Counter 1 interrupt Flag Register */ -#define TIFR1 _SFR_IO8(0x16) -#define ICF1 5 -#define OCF1B 2 -#define OCF1A 1 -#define TOV1 0 - -/* Timer/Counter 2 interrupt Flag Register */ -#define TIFR2 _SFR_IO8(0x17) -#define OCF2A 1 -#define TOV2 0 - -/* External Interrupt Flag Register */ -#define EIFR _SFR_IO8(0x1C) -#define PCIF1 7 -#define PCIF0 6 -#define INTF0 0 - -/* External Interrupt Mask Register */ -#define EIMSK _SFR_IO8(0x1D) -#define PCIE1 7 -#define PCIE0 6 -#define INT0 0 - -/* General Purpose I/O Register 0 */ -#define GPIOR0 _SFR_IO8(0x1E) - -#define EECR _SFR_IO8(0x1F) -#define EERIE 3 -#define EEMWE 2 -#define EEWE 1 -#define EERE 0 - -#define EEDR _SFR_IO8(0X20) - -/* Combine EEARL and EEARH */ -#define EEAR _SFR_IO16(0x21) -#define EEARL _SFR_IO8(0x21) -#define EEARH _SFR_IO8(0X22) - -/* 6-char sequence denoting where to find the EEPROM registers in memory space. - Adresses denoted in hex syntax with uppercase letters. Used by the EEPROM - subroutines. - First two letters: EECR address. - Second two letters: EEDR address. - Last two letters: EEAR address. */ -#define __EEPROM_REG_LOCATIONS__ 1F2021 - -/* General Timer/Counter Control Register */ -#define GTCCR _SFR_IO8(0x23) -#define TSM 7 -#define PSR2 1 -#define PSR10 0 - -/* Timer/Counter Control Register A */ -#define TCCR0A _SFR_IO8(0x24) -#define FOC0A 7 -#define WGM00 6 -#define COM0A1 5 -#define COM0A0 4 -#define WGM01 3 -#define CS02 2 -#define CS01 1 -#define CS00 0 - -/* Timer/Counter Register */ -#define TCNT0 _SFR_IO8(0x26) - -/* Output Compare Register A */ -#define OCR0A _SFR_IO8(0x27) - -/* General Purpose I/O Register 1 */ -#define GPIOR1 _SFR_IO8(0x2A) - -/* General Purpose I/O Register 2 */ -#define GPIOR2 _SFR_IO8(0x2B) - -/* SPI Control Register */ -#define SPCR _SFR_IO8(0x2C) -#define SPIE 7 -#define SPE 6 -#define DORD 5 -#define MSTR 4 -#define CPOL 3 -#define CPHA 2 -#define SPR1 1 -#define SPR0 0 - -/* SPI Status Register */ -#define SPSR _SFR_IO8(0x2D) -#define SPIF 7 -#define WCOL 6 -#define SPI2X 0 - -/* SPI Data Register */ -#define SPDR _SFR_IO8(0x2E) - -/* Analog Comperator Control and Status Register */ -#define ACSR _SFR_IO8(0x30) -#define ACD 7 -#define ACBG 6 -#define ACO 5 -#define ACI 4 -#define ACIE 3 -#define ACIC 2 -#define ACIS1 1 -#define ACIS0 0 - -/* On-chip Debug Register */ -#define OCDR _SFR_IO8(0x31) -#define IDRD 7 -#define OCDR7 7 -#define OCDR6 6 -#define OCDR5 5 -#define OCDR4 4 -#define OCDR3 3 -#define OCDR2 2 -#define OCDR1 1 -#define OCDR0 0 - -/* Sleep Mode Control Register */ -#define SMCR _SFR_IO8(0x33) -#define SM2 3 -#define SM1 2 -#define SM0 1 -#define SE 0 - -/* MCU Status Register */ -#define MCUSR _SFR_IO8(0x34) -#define JTRF 4 -#define WDRF 3 -#define BORF 2 -#define EXTRF 1 -#define PORF 0 - -/* MCU Control Rgeister */ -#define MCUCR _SFR_IO8(0x35) -#define JTD 7 -#define PUD 4 -#define IVSEL 1 -#define IVCE 0 - -/* Store Program Memory Control and Status Register */ -#define SPMCSR _SFR_IO8(0x37) -#define SPMIE 7 -#define RWWSB 6 -#define RWWSRE 4 -#define BLBSET 3 -#define PGWRT 2 -#define PGERS 1 -#define SPMEN 0 - -/* Watchdog Timer Control Register */ -#define WDTCR _SFR_MEM8(0x60) -#define WDCE 4 -#define WDE 3 -#define WDP2 2 -#define WDP1 1 -#define WDP0 0 - -/* Clock Prescale Register */ -#define CLKPR _SFR_MEM8(0x61) -#define CLKPCE 7 -#define CLKPS3 3 -#define CLKPS2 2 -#define CLKPS1 1 -#define CLKPS0 0 - -#define PRR _SFR_MEM8(0x64) -#define PRADC 0 -#define PRUSART0 1 -#define PRSPI 2 -#define PRTIM1 3 -#define PRLCD 4 - -#define __AVR_HAVE_PRR ((1<, never directly. */ - -#ifndef _AVR_IO_H_ -# error "Include instead of this file." -#endif - -#ifndef _AVR_IOXXX_H_ -# define _AVR_IOXXX_H_ "iom169pa.h" -#else -# error "Attempt to include more than one file." -#endif - - -#ifndef _AVR_ATmega169PA_H_ -#define _AVR_ATmega169PA_H_ 1 - - -/* Registers and associated bit numbers. */ - -#define PINA _SFR_IO8(0x00) -#define PINA0 0 -#define PINA1 1 -#define PINA2 2 -#define PINA3 3 -#define PINA4 4 -#define PINA5 5 -#define PINA6 6 -#define PINA7 7 - -#define DDRA _SFR_IO8(0x01) -#define DDA0 0 -#define DDA1 1 -#define DDA2 2 -#define DDA3 3 -#define DDA4 4 -#define DDA5 5 -#define DDA6 6 -#define DDA7 7 - -#define PORTA _SFR_IO8(0x02) -#define PORTA0 0 -#define PORTA1 1 -#define PORTA2 2 -#define PORTA3 3 -#define PORTA4 4 -#define PORTA5 5 -#define PORTA6 6 -#define PORTA7 7 - -#define PINB _SFR_IO8(0x03) -#define PINB0 0 -#define PINB1 1 -#define PINB2 2 -#define PINB3 3 -#define PINB4 4 -#define PINB5 5 -#define PINB6 6 -#define PINB7 7 - -#define DDRB _SFR_IO8(0x04) -#define DDB0 0 -#define DDB1 1 -#define DDB2 2 -#define DDB3 3 -#define DDB4 4 -#define DDB5 5 -#define DDB6 6 -#define DDB7 7 - -#define PORTB _SFR_IO8(0x05) -#define PORTB0 0 -#define PORTB1 1 -#define PORTB2 2 -#define PORTB3 3 -#define PORTB4 4 -#define PORTB5 5 -#define PORTB6 6 -#define PORTB7 7 - -#define PINC _SFR_IO8(0x06) -#define PINC0 0 -#define PINC1 1 -#define PINC2 2 -#define PINC3 3 -#define PINC4 4 -#define PINC5 5 -#define PINC6 6 -#define PINC7 7 - -#define DDRC _SFR_IO8(0x07) -#define DDC0 0 -#define DDC1 1 -#define DDC2 2 -#define DDC3 3 -#define DDC4 4 -#define DDC5 5 -#define DDC6 6 -#define DDC7 7 - -#define PORTC _SFR_IO8(0x08) -#define PORTC0 0 -#define PORTC1 1 -#define PORTC2 2 -#define PORTC3 3 -#define PORTC4 4 -#define PORTC5 5 -#define PORTC6 6 -#define PORTC7 7 - -#define PIND _SFR_IO8(0x09) -#define PIND0 0 -#define PIND1 1 -#define PIND2 2 -#define PIND3 3 -#define PIND4 4 -#define PIND5 5 -#define PIND6 6 -#define PIND7 7 - -#define DDRD _SFR_IO8(0x0A) -#define DDD0 0 -#define DDD1 1 -#define DDD2 2 -#define DDD3 3 -#define DDD4 4 -#define DDD5 5 -#define DDD6 6 -#define DDD7 7 - -#define PORTD _SFR_IO8(0x0B) -#define PORTD0 0 -#define PORTD1 1 -#define PORTD2 2 -#define PORTD3 3 -#define PORTD4 4 -#define PORTD5 5 -#define PORTD6 6 -#define PORTD7 7 - -#define PINE _SFR_IO8(0x0C) -#define PINE0 0 -#define PINE1 1 -#define PINE2 2 -#define PINE3 3 -#define PINE4 4 -#define PINE5 5 -#define PINE6 6 -#define PINE7 7 - -#define DDRE _SFR_IO8(0x0D) -#define DDE0 0 -#define DDE1 1 -#define DDE2 2 -#define DDE3 3 -#define DDE4 4 -#define DDE5 5 -#define DDE6 6 -#define DDE7 7 - -#define PORTE _SFR_IO8(0x0E) -#define PORTE0 0 -#define PORTE1 1 -#define PORTE2 2 -#define PORTE3 3 -#define PORTE4 4 -#define PORTE5 5 -#define PORTE6 6 -#define PORTE7 7 - -#define PINF _SFR_IO8(0x0F) -#define PINF0 0 -#define PINF1 1 -#define PINF2 2 -#define PINF3 3 -#define PINF4 4 -#define PINF5 5 -#define PINF6 6 -#define PINF7 7 - -#define DDRF _SFR_IO8(0x10) -#define DDF0 0 -#define DDF1 1 -#define DDF2 2 -#define DDF3 3 -#define DDF4 4 -#define DDF5 5 -#define DDF6 6 -#define DDF7 7 - -#define PORTF _SFR_IO8(0x11) -#define PORTF0 0 -#define PORTF1 1 -#define PORTF2 2 -#define PORTF3 3 -#define PORTF4 4 -#define PORTF5 5 -#define PORTF6 6 -#define PORTF7 7 - -#define PING _SFR_IO8(0x12) -#define PING0 0 -#define PING1 1 -#define PING2 2 -#define PING3 3 -#define PING4 4 -#define PING5 5 - -#define DDRG _SFR_IO8(0x13) -#define DDG0 0 -#define DDG1 1 -#define DDG2 2 -#define DDG3 3 -#define DDG4 4 -#define DDG5 5 - -#define PORTG _SFR_IO8(0x14) -#define PORTG0 0 -#define PORTG1 1 -#define PORTG2 2 -#define PORTG3 3 -#define PORTG4 4 -#define PORTG5 5 - -#define TIFR0 _SFR_IO8(0x15) -#define TOV0 0 -#define OCF0A 1 - -#define TIFR1 _SFR_IO8(0x16) -#define TOV1 0 -#define OCF1A 1 -#define OCF1B 2 -#define ICF1 5 - -#define TIFR2 _SFR_IO8(0x17) -#define TOV2 0 -#define OCF2A 1 - -#define EIFR _SFR_IO8(0x1C) -#define INTF0 0 -#define PCIF0 4 -#define PCIF1 5 - -#define EIMSK _SFR_IO8(0x1D) -#define INT0 0 -#define PCIE0 4 -#define PCIE1 5 - -#define GPIOR0 _SFR_IO8(0x1E) -#define GPIOR00 0 -#define GPIOR01 1 -#define GPIOR02 2 -#define GPIOR03 3 -#define GPIOR04 4 -#define GPIOR05 5 -#define GPIOR06 6 -#define GPIOR07 7 - -#define EECR _SFR_IO8(0x1F) -#define EERE 0 -#define EEWE 1 -#define EEMWE 2 -#define EERIE 3 - -#define EEDR _SFR_IO8(0x20) -#define EEDR0 0 -#define EEDR1 1 -#define EEDR2 2 -#define EEDR3 3 -#define EEDR4 4 -#define EEDR5 5 -#define EEDR6 6 -#define EEDR7 7 - -#define EEAR _SFR_IO16(0x21) - -#define EEARL _SFR_IO8(0x21) -#define EEAR0 0 -#define EEAR1 1 -#define EEAR2 2 -#define EEAR3 3 -#define EEAR4 4 -#define EEAR5 5 -#define EEAR6 6 -#define EEAR7 7 - -#define EEARH _SFR_IO8(0x22) -#define EEAR8 0 - -#define GTCCR _SFR_IO8(0x23) -#define PSR310 0 -#define PSR2 1 -#define TSM 7 - -#define TCCR0A _SFR_IO8(0x24) -#define CS00 0 -#define CS01 1 -#define CS02 2 -#define WGM01 3 -#define COM0A0 4 -#define COM0A1 5 -#define WGM00 6 -#define FOC0A 7 - -#define TCNT0 _SFR_IO8(0x26) -#define TCNT0_0 0 -#define TCNT0_1 1 -#define TCNT0_2 2 -#define TCNT0_3 3 -#define TCNT0_4 4 -#define TCNT0_5 5 -#define TCNT0_6 6 -#define TCNT0_7 7 - -#define OCR0A _SFR_IO8(0x27) -#define OCR0A0 0 -#define OCR0A1 1 -#define OCR0A2 2 -#define OCR0A3 3 -#define OCR0A4 4 -#define OCR0A5 5 -#define OCR0A6 6 -#define OCR0A7 7 - -#define GPIOR1 _SFR_IO8(0x2A) -#define GPIOR10 0 -#define GPIOR11 1 -#define GPIOR12 2 -#define GPIOR13 3 -#define GPIOR14 4 -#define GPIOR15 5 -#define GPIOR16 6 -#define GPIOR17 7 - -#define GPIOR2 _SFR_IO8(0x2B) -#define GPIOR20 0 -#define GPIOR21 1 -#define GPIOR22 2 -#define GPIOR23 3 -#define GPIOR24 4 -#define GPIOR25 5 -#define GPIOR26 6 -#define GPIOR27 7 - -#define SPCR _SFR_IO8(0x2C) -#define SPR0 0 -#define SPR1 1 -#define CPHA 2 -#define CPOL 3 -#define MSTR 4 -#define DORD 5 -#define SPE 6 -#define SPIE 7 - -#define SPSR _SFR_IO8(0x2D) -#define SPI2X 0 -#define WCOL 6 -#define SPIF 7 - -#define SPDR _SFR_IO8(0x2E) -#define SPDR0 0 -#define SPDR1 1 -#define SPDR2 2 -#define SPDR3 3 -#define SPDR4 4 -#define SPDR5 5 -#define SPDR6 6 -#define SPDR7 7 - -#define ACSR _SFR_IO8(0x30) -#define ACIS0 0 -#define ACIS1 1 -#define ACIC 2 -#define ACIE 3 -#define ACI 4 -#define ACO 5 -#define ACBG 6 -#define ACD 7 - -#define OCDR _SFR_IO8(0x31) -#define OCDR0 0 -#define OCDR1 1 -#define OCDR2 2 -#define OCDR3 3 -#define OCDR4 4 -#define OCDR5 5 -#define OCDR6 6 -#define OCDR7 7 - -#define SMCR _SFR_IO8(0x33) -#define SE 0 -#define SM0 1 -#define SM1 2 -#define SM2 3 - -#define MCUSR _SFR_IO8(0x34) -#define PORF 0 -#define EXTRF 1 -#define BORF 2 -#define WDRF 3 -#define JTRF 4 - -#define MCUCR _SFR_IO8(0x35) -#define IVCE 0 -#define IVSEL 1 -#define PUD 4 -#define BODSE 5 -#define BODS 6 -#define JTD 7 - -#define SPMCSR _SFR_IO8(0x37) -#define SPMEN 0 -#define PGERS 1 -#define PGWRT 2 -#define BLBSET 3 -#define RWWSRE 4 -#define RWWSB 6 -#define SPMIE 7 - -#define WDTCR _SFR_MEM8(0x60) -#define WDP0 0 -#define WDP1 1 -#define WDP2 2 -#define WDE 3 -#define WDCE 4 - -#define CLKPR _SFR_MEM8(0x61) -#define CLKPS0 0 -#define CLKPS1 1 -#define CLKPS2 2 -#define CLKPS3 3 -#define CLKPCE 7 - -#define PRR _SFR_MEM8(0x64) -#define PRADC 0 -#define PRUSART0 1 -#define PRSPI 2 -#define PRTIM1 3 -#define PRLCD 4 - -#define __AVR_HAVE_PRR ((1<, never directly. */ - -#ifndef _AVR_IO_H_ -# error "Include instead of this file." -#endif - -#ifndef _AVR_IOXXX_H_ -# define _AVR_IOXXX_H_ "iom16a.h" -#else -# error "Attempt to include more than one file." -#endif - - -#ifndef _AVR_ATmega16A_H_ -#define _AVR_ATmega16A_H_ 1 - - -/* Registers and associated bit numbers. */ - -#define TWBR _SFR_IO8(0x00) -#define TWBR0 0 -#define TWBR1 1 -#define TWBR2 2 -#define TWBR3 3 -#define TWBR4 4 -#define TWBR5 5 -#define TWBR6 6 -#define TWBR7 7 - -#define TWSR _SFR_IO8(0x01) -#define TWPS0 0 -#define TWPS1 1 -#define TWS3 3 -#define TWS4 4 -#define TWS5 5 -#define TWS6 6 -#define TWS7 7 - -#define TWAR _SFR_IO8(0x02) -#define TWGCE 0 -#define TWA0 1 -#define TWA1 2 -#define TWA2 3 -#define TWA3 4 -#define TWA4 5 -#define TWA5 6 -#define TWA6 7 - -#define TWDR _SFR_IO8(0x03) -#define TWD0 0 -#define TWD1 1 -#define TWD2 2 -#define TWD3 3 -#define TWD4 4 -#define TWD5 5 -#define TWD6 6 -#define TWD7 7 - -#ifndef __ASSEMBLER__ -#define ADC _SFR_IO16(0x04) -#endif -#define ADCW _SFR_IO16(0x04) - -#define ADCL _SFR_IO8(0x04) -#define ADCL0 0 -#define ADCL1 1 -#define ADCL2 2 -#define ADCL3 3 -#define ADCL4 4 -#define ADCL5 5 -#define ADCL6 6 -#define ADCL7 7 - -#define ADCH _SFR_IO8(0x05) -#define ADCH0 0 -#define ADCH1 1 -#define ADCH2 2 -#define ADCH3 3 -#define ADCH4 4 -#define ADCH5 5 -#define ADCH6 6 -#define ADCH7 7 - -#define ADCSRA _SFR_IO8(0x06) -#define ADPS0 0 -#define ADPS1 1 -#define ADPS2 2 -#define ADIE 3 -#define ADIF 4 -#define ADATE 5 -#define ADSC 6 -#define ADEN 7 - -#define ADMUX _SFR_IO8(0x07) -#define MUX0 0 -#define MUX1 1 -#define MUX2 2 -#define MUX3 3 -#define MUX4 4 -#define ADLAR 5 -#define REFS0 6 -#define REFS1 7 - -#define ACSR _SFR_IO8(0x08) -#define ACIS0 0 -#define ACIS1 1 -#define ACIC 2 -#define ACIE 3 -#define ACI 4 -#define ACO 5 -#define ACBG 6 -#define ACD 7 - -#define UBRRL _SFR_IO8(0x09) -#define UBRR0 0 -#define UBRR1 1 -#define UBRR2 2 -#define UBRR3 3 -#define UBRR4 4 -#define UBRR5 5 -#define UBRR6 6 -#define UBRR7 7 - -#define UCSRB _SFR_IO8(0x0A) -#define TXB8 0 -#define RXB8 1 -#define UCSZ2 2 -#define TXEN 3 -#define RXEN 4 -#define UDRIE 5 -#define TXCIE 6 -#define RXCIE 7 - -#define UCSRA _SFR_IO8(0x0B) -#define MPCM 0 -#define U2X 1 -#define UPE 2 -#define DOR 3 -#define FE 4 -#define UDRE 5 -#define TXC 6 -#define RXC 7 - -#define UDR _SFR_IO8(0x0C) -#define UDR0 0 -#define UDR1 1 -#define UDR2 2 -#define UDR3 3 -#define UDR4 4 -#define UDR5 5 -#define UDR6 6 -#define UDR7 7 - -#define SPCR _SFR_IO8(0x0D) -#define SPR0 0 -#define SPR1 1 -#define CPHA 2 -#define CPOL 3 -#define MSTR 4 -#define DORD 5 -#define SPE 6 -#define SPIE 7 - -#define SPSR _SFR_IO8(0x0E) -#define SPI2X 0 -#define WCOL 6 -#define SPIF 7 - -#define SPDR _SFR_IO8(0x0F) -#define SPDR0 0 -#define SPDR1 1 -#define SPDR2 2 -#define SPDR3 3 -#define SPDR4 4 -#define SPDR5 5 -#define SPDR6 6 -#define SPDR7 7 - -#define PIND _SFR_IO8(0x10) -#define PIND0 0 -#define PIND1 1 -#define PIND2 2 -#define PIND3 3 -#define PIND4 4 -#define PIND5 5 -#define PIND6 6 -#define PIND7 7 - -#define DDRD _SFR_IO8(0x11) -#define DDD0 0 -#define DDD1 1 -#define DDD2 2 -#define DDD3 3 -#define DDD4 4 -#define DDD5 5 -#define DDD6 6 -#define DDD7 7 - -#define PORTD _SFR_IO8(0x12) -#define PORTD0 0 -#define PORTD1 1 -#define PORTD2 2 -#define PORTD3 3 -#define PORTD4 4 -#define PORTD5 5 -#define PORTD6 6 -#define PORTD7 7 - -#define PINC _SFR_IO8(0x13) -#define PINC0 0 -#define PINC1 1 -#define PINC2 2 -#define PINC3 3 -#define PINC4 4 -#define PINC5 5 -#define PINC6 6 -#define PINC7 7 - -#define DDRC _SFR_IO8(0x14) -#define DDC0 0 -#define DDC1 1 -#define DDC2 2 -#define DDC3 3 -#define DDC4 4 -#define DDC5 5 -#define DDC6 6 -#define DDC7 7 - -#define PORTC _SFR_IO8(0x15) -#define PORTC0 0 -#define PORTC1 1 -#define PORTC2 2 -#define PORTC3 3 -#define PORTC4 4 -#define PORTC5 5 -#define PORTC6 6 -#define PORTC7 7 - -#define PINB _SFR_IO8(0x16) -#define PINB0 0 -#define PINB1 1 -#define PINB2 2 -#define PINB3 3 -#define PINB4 4 -#define PINB5 5 -#define PINB6 6 -#define PINB7 7 - -#define DDRB _SFR_IO8(0x17) -#define DDB0 0 -#define DDB1 1 -#define DDB2 2 -#define DDB3 3 -#define DDB4 4 -#define DDB5 5 -#define DDB6 6 -#define DDB7 7 - -#define PORTB _SFR_IO8(0x18) -#define PORTB0 0 -#define PORTB1 1 -#define PORTB2 2 -#define PORTB3 3 -#define PORTB4 4 -#define PORTB5 5 -#define PORTB6 6 -#define PORTB7 7 - -#define PINA _SFR_IO8(0x19) -#define PINA0 0 -#define PINA1 1 -#define PINA2 2 -#define PINA3 3 -#define PINA4 4 -#define PINA5 5 -#define PINA6 6 -#define PINA7 7 - -#define DDRA _SFR_IO8(0x1A) -#define DDA0 0 -#define DDA1 1 -#define DDA2 2 -#define DDA3 3 -#define DDA4 4 -#define DDA5 5 -#define DDA6 6 -#define DDA7 7 - -#define PORTA _SFR_IO8(0x1B) -#define PORTA0 0 -#define PORTA1 1 -#define PORTA2 2 -#define PORTA3 3 -#define PORTA4 4 -#define PORTA5 5 -#define PORTA6 6 -#define PORTA7 7 - -#define EECR _SFR_IO8(0x1C) -#define EERE 0 -#define EEWE 1 -#define EEMWE 2 -#define EERIE 3 - -#define EEDR _SFR_IO8(0x1D) -#define EEDR0 0 -#define EEDR1 1 -#define EEDR2 2 -#define EEDR3 3 -#define EEDR4 4 -#define EEDR5 5 -#define EEDR6 6 -#define EEDR7 7 - -#define EEAR _SFR_IO16(0x1E) - -#define EEARL _SFR_IO8(0x1E) -#define EEAR0 0 -#define EEAR1 1 -#define EEAR2 2 -#define EEAR3 3 -#define EEAR4 4 -#define EEAR5 5 -#define EEAR6 6 -#define EEAR7 7 - -#define EEARH _SFR_IO8(0x1F) -#define EEAR8 0 - -#define UBRRH _SFR_IO8(0x20) -#define UBRR8 0 -#define UBRR9 1 -#define UBRR10 2 -#define UBRR11 3 - -#define UCSRC _SFR_IO8(0x20) -#define UCPOL 0 -#define UCSZ0 1 -#define UCSZ1 2 -#define USBS 3 -#define UPM0 4 -#define UPM1 5 -#define UMSEL 6 -#define URSEL 7 - -#define WDTCR _SFR_IO8(0x21) -#define WDP0 0 -#define WDP1 1 -#define WDP2 2 -#define WDE 3 -#define WDTOE 4 - -#define ASSR _SFR_IO8(0x22) -#define TCR2UB 0 -#define OCR2UB 1 -#define TCN2UB 2 -#define AS2 3 - -#define OCR2 _SFR_IO8(0x23) -#define OCR2_0 0 -#define OCR2_1 1 -#define OCR2_2 2 -#define OCR2_3 3 -#define OCR2_4 4 -#define OCR2_5 5 -#define OCR2_6 6 -#define OCR2_7 7 - -#define TCNT2 _SFR_IO8(0x24) -#define TCNT2_0 0 -#define TCNT2_1 1 -#define TCNT2_2 2 -#define TCNT2_3 3 -#define TCNT2_4 4 -#define TCNT2_5 5 -#define TCNT2_6 6 -#define TCNT2_7 7 - -#define TCCR2 _SFR_IO8(0x25) -#define CS20 0 -#define CS21 1 -#define CS22 2 -#define WGM21 3 -#define COM20 4 -#define COM21 5 -#define WGM20 6 -#define FOC2 7 - -#define ICR1 _SFR_IO16(0x26) - -#define ICR1L _SFR_IO8(0x26) -#define ICR1L0 0 -#define ICR1L1 1 -#define ICR1L2 2 -#define ICR1L3 3 -#define ICR1L4 4 -#define ICR1L5 5 -#define ICR1L6 6 -#define ICR1L7 7 - -#define ICR1H _SFR_IO8(0x27) -#define ICR1H0 0 -#define ICR1H1 1 -#define ICR1H2 2 -#define ICR1H3 3 -#define ICR1H4 4 -#define ICR1H5 5 -#define ICR1H6 6 -#define ICR1H7 7 - -#define OCR1B _SFR_IO16(0x28) - -#define OCR1BL _SFR_IO8(0x28) -#define OCR1BL0 0 -#define OCR1BL1 1 -#define OCR1BL2 2 -#define OCR1BL3 3 -#define OCR1BL4 4 -#define OCR1BL5 5 -#define OCR1BL6 6 -#define OCR1BL7 7 - -#define OCR1BH _SFR_IO8(0x29) -#define OCR1BH0 0 -#define OCR1BH1 1 -#define OCR1BH2 2 -#define OCR1BH3 3 -#define OCR1BH4 4 -#define OCR1BH5 5 -#define OCR1BH6 6 -#define OCR1BH7 7 - -#define OCR1A _SFR_IO16(0x2A) - -#define OCR1AL _SFR_IO8(0x2A) -#define OCR1AL0 0 -#define OCR1AL1 1 -#define OCR1AL2 2 -#define OCR1AL3 3 -#define OCR1AL4 4 -#define OCR1AL5 5 -#define OCR1AL6 6 -#define OCR1AL7 7 - -#define OCR1AH _SFR_IO8(0x2B) -#define OCR1AH0 0 -#define OCR1AH1 1 -#define OCR1AH2 2 -#define OCR1AH3 3 -#define OCR1AH4 4 -#define OCR1AH5 5 -#define OCR1AH6 6 -#define OCR1AH7 7 - -#define TCNT1 _SFR_IO16(0x2C) - -#define TCNT1L _SFR_IO8(0x2C) -#define TCNT1L0 0 -#define TCNT1L1 1 -#define TCNT1L2 2 -#define TCNT1L3 3 -#define TCNT1L4 4 -#define TCNT1L5 5 -#define TCNT1L6 6 -#define TCNT1L7 7 - -#define TCNT1H _SFR_IO8(0x2D) -#define TCNT1H0 0 -#define TCNT1H1 1 -#define TCNT1H2 2 -#define TCNT1H3 3 -#define TCNT1H4 4 -#define TCNT1H5 5 -#define TCNT1H6 6 -#define TCNT1H7 7 - -#define TCCR1B _SFR_IO8(0x2E) -#define CS10 0 -#define CS11 1 -#define CS12 2 -#define WGM12 3 -#define WGM13 4 -#define ICES1 6 -#define ICNC1 7 - -#define TCCR1A _SFR_IO8(0x2F) -#define WGM10 0 -#define WGM11 1 -#define FOC1B 2 -#define FOC1A 3 -#define COM1B0 4 -#define COM1B1 5 -#define COM1A0 6 -#define COM1A1 7 - -#define SFIOR _SFR_IO8(0x30) -#define PSR10 0 -#define PSR2 1 -#define PUD 2 -#define ACME 3 -#define ADTS0 5 -#define ADTS1 6 -#define ADTS2 7 - -#define OSCCAL _SFR_IO8(0x31) -#define CAL0 0 -#define CAL1 1 -#define CAL2 2 -#define CAL3 3 -#define CAL4 4 -#define CAL5 5 -#define CAL6 6 -#define CAL7 7 - -#define OCDR _SFR_IO8(0x31) -#define OCDR0 0 -#define OCDR1 1 -#define OCDR2 2 -#define OCDR3 3 -#define OCDR4 4 -#define OCDR5 5 -#define OCDR6 6 -#define OCDR7 7 - -#define TCNT0 _SFR_IO8(0x32) -#define TCNT0_0 0 -#define TCNT0_1 1 -#define TCNT0_2 2 -#define TCNT0_3 3 -#define TCNT0_4 4 -#define TCNT0_5 5 -#define TCNT0_6 6 -#define TCNT0_7 7 - -#define TCCR0 _SFR_IO8(0x33) -#define CS00 0 -#define CS01 1 -#define CS02 2 -#define WGM01 3 -#define COM00 4 -#define COM01 5 -#define WGM00 6 -#define FOC0 7 - -#define MCUCSR _SFR_IO8(0x34) -#define PORF 0 -#define EXTRF 1 -#define BORF 2 -#define WDRF 3 -#define JTRF 4 -#define ISC2 6 -#define JTD 7 - -#define MCUCR _SFR_IO8(0x35) -#define ISC00 0 -#define ISC01 1 -#define ISC10 2 -#define ISC11 3 -#define SM0 4 -#define SM1 5 -#define SE 6 -#define SM2 7 - -#define TWCR _SFR_IO8(0x36) -#define TWIE 0 -#define TWEN 2 -#define TWWC 3 -#define TWSTO 4 -#define TWSTA 5 -#define TWEA 6 -#define TWINT 7 - -#define SPMCSR _SFR_IO8(0x37) -#define SPMEN 0 -#define PGERS 1 -#define PGWRT 2 -#define BLBSET 3 -#define RWWSRE 4 -#define RWWSB 6 -#define SPMIE 7 - -#define TIFR _SFR_IO8(0x38) -#define TOV0 0 -#define OCF0 1 -#define TOV1 2 -#define OCF1B 3 -#define OCF1A 4 -#define ICF1 5 -#define TOV2 6 -#define OCF2 7 - -#define TIMSK _SFR_IO8(0x39) -#define TOIE0 0 -#define OCIE0 1 -#define TOIE1 2 -#define OCIE1B 3 -#define OCIE1A 4 -#define TICIE1 5 -#define TOIE2 6 -#define OCIE2 7 - -#define GIFR _SFR_IO8(0x3A) -#define INTF2 5 -#define INTF0 6 -#define INTF1 7 - -#define GICR _SFR_IO8(0x3B) -#define IVCE 0 -#define IVSEL 1 -#define INT2 5 -#define INT0 6 -#define INT1 7 - -#define OCR0 _SFR_IO8(0x3C) -#define OCR0_0 0 -#define OCR0_1 1 -#define OCR0_2 2 -#define OCR0_3 3 -#define OCR0_4 4 -#define OCR0_5 5 -#define OCR0_6 6 -#define OCR0_7 7 - - -/* Interrupt vectors */ -/* Vector 0 is the reset vector */ -#define INT0_vect_num 1 -#define INT0_vect _VECTOR(1) /* External Interrupt Request 0 */ -#define INT1_vect_num 2 -#define INT1_vect _VECTOR(2) /* External Interrupt Request 1 */ -#define TIMER2_COMP_vect_num 3 -#define TIMER2_COMP_vect _VECTOR(3) /* Timer/Counter2 Compare Match */ -#define TIMER2_OVF_vect_num 4 -#define TIMER2_OVF_vect _VECTOR(4) /* Timer/Counter2 Overflow */ -#define TIMER1_CAPT_vect_num 5 -#define TIMER1_CAPT_vect _VECTOR(5) /* Timer/Counter1 Capture Event */ -#define TIMER1_COMPA_vect_num 6 -#define TIMER1_COMPA_vect _VECTOR(6) /* Timer/Counter1 Compare Match A */ -#define TIMER1_COMPB_vect_num 7 -#define TIMER1_COMPB_vect _VECTOR(7) /* Timer/Counter1 Compare Match B */ -#define TIMER1_OVF_vect_num 8 -#define TIMER1_OVF_vect _VECTOR(8) /* Timer/Counter1 Overflow */ -#define TIMER0_OVF_vect_num 9 -#define TIMER0_OVF_vect _VECTOR(9) /* Timer/Counter0 Overflow */ -#define SPI_STC_vect_num 10 -#define SPI_STC_vect _VECTOR(10) /* Serial Transfer Complete */ - -/* The following vectors use an inconsistent (to the ATmega16 etc.) - naming scheme. The inconsistent names are preserved here for softwares - that already use them: */ -#define USARTRXC_vect_num 11 -#define USARTRXC_vect _VECTOR(11) /* USART, Rx Complete */ -#define USARTUDRE_vect_num 12 -#define USARTUDRE_vect _VECTOR(12) /* USART Data Register Empty */ -#define USARTTXC_vect_num 13 -#define USARTTXC_vect _VECTOR(13) /* USART, Tx Complete */ -/* The "classic" designators: */ -#define USART_RXC_vect_num 11 -#define USART_RXC_vect _VECTOR(11) /* USART, Rx Complete */ -#define USART_UDRE_vect_num 12 -#define USART_UDRE_vect _VECTOR(12) /* USART Data Register Empty */ -#define USART_TXC_vect_num 13 -#define USART_TXC_vect _VECTOR(13) /* USART, Tx Complete */ - -#define ADC_vect_num 14 -#define ADC_vect _VECTOR(14) /* ADC Conversion Complete */ -#define EE_RDY_vect_num 15 -#define EE_RDY_vect _VECTOR(15) /* EEPROM Ready */ -#define ANA_COMP_vect_num 16 -#define ANA_COMP_vect _VECTOR(16) /* Analog Comparator */ -#define TWI_vect_num 17 -#define TWI_vect _VECTOR(17) /* 2-wire Serial Interface */ -#define INT2_vect_num 18 -#define INT2_vect _VECTOR(18) /* External Interrupt Request 2 */ -#define TIMER0_COMP_vect_num 19 -#define TIMER0_COMP_vect _VECTOR(19) /* Timer/Counter0 Compare Match */ -#define SPM_RDY_vect_num 20 -#define SPM_RDY_vect _VECTOR(20) /* Store Program Memory Ready */ - -#define _VECTOR_SIZE 4 /* Size of individual vector. */ -#define _VECTORS_SIZE (21 * _VECTOR_SIZE) - - -/* Constants */ -#define SPM_PAGESIZE (128) -#define RAMSTART (0x60) -#define RAMSIZE (1024) -#define RAMEND (RAMSTART + RAMSIZE - 1) -#define XRAMSTART (NA) -#define XRAMSIZE (0) -#define XRAMEND (RAMEND) -#define E2END (0x1FF) -#define E2PAGESIZE (4) -#define FLASHEND (0x3FFF) - - -/* Fuses */ -#define FUSE_MEMORY_SIZE 2 - -/* Low Fuse Byte */ -#define FUSE_CKSEL0 (unsigned char)~_BV(0) /* Select Clock Source */ -#define FUSE_CKSEL1 (unsigned char)~_BV(1) /* Select Clock Source */ -#define FUSE_CKSEL2 (unsigned char)~_BV(2) /* Select Clock Source */ -#define FUSE_CKSEL3 (unsigned char)~_BV(3) /* Select Clock Source */ -#define FUSE_SUT0 (unsigned char)~_BV(4) /* Select start-up time */ -#define FUSE_SUT1 (unsigned char)~_BV(5) /* Select start-up time */ -#define FUSE_BODEN (unsigned char)~_BV(6) /* Brown out detector enable */ -#define FUSE_BODLEVEL (unsigned char)~_BV(7) /* Brown out detector trigger level */ -#define LFUSE_DEFAULT (FUSE_SUT1 & FUSE_SUT0 & FUSE_CKSEL3 & FUSE_CKSEL2 & FUSE_CKSEL1) - -/* High Fuse Byte */ -#define FUSE_BOOTRST (unsigned char)~_BV(0) /* Select Reset Vector */ -#define FUSE_BOOTSZ0 (unsigned char)~_BV(1) /* Select Boot Size */ -#define FUSE_BOOTSZ1 (unsigned char)~_BV(2) /* Select Boot Size */ -#define FUSE_EESAVE (unsigned char)~_BV(3) /* EEPROM memory is preserved through chip erase */ -#define FUSE_CKOPT (unsigned char)~_BV(4) /* Oscillator Options */ -#define FUSE_SPIEN (unsigned char)~_BV(5) /* Enable Serial programming and Data Downloading */ -#define FUSE_JTAGEN (unsigned char)~_BV(6) /* Enable JTAG */ -#define FUSE_OCDEN (unsigned char)~_BV(7) /* Enable OCD */ -#define HFUSE_DEFAULT (FUSE_JTAGEN & FUSE_SPIEN & FUSE_BOOTSZ1 & FUSE_BOOTSZ0) - - -/* Lock Bits */ -#define __LOCK_BITS_EXIST -#define __BOOT_LOCK_BITS_0_EXIST -#define __BOOT_LOCK_BITS_1_EXIST - - -/* Signature */ -#define SIGNATURE_0 0x1E -#define SIGNATURE_1 0x94 -#define SIGNATURE_2 0x03 - - -/* Device Pin Definitions */ -#define MOSI_DDR DDRB -#define MOSI_PORT PORTB -#define MOSI_PIN PINB -#define MOSI_BIT 5 - -#define MISO_DDR DDRB -#define MISO_PORT PORTB -#define MISO_PIN PINB -#define MISO_BIT 6 - -#define PB7_SCK_DDR DDRB7_SCK -#define PB7_SCK_PORT PORTB7_SCK -#define PB7_SCK_PIN PINB7_SCK -#define PB7_SCK_BIT 7_SCK - -#define RXD_DDR DDRD -#define RXD_PORT PORTD -#define RXD_PIN PIND -#define RXD_BIT 0 - -#define TXD_DDR DDRD -#define TXD_PORT PORTD -#define TXD_PIN PIND -#define TXD_BIT 1 - -#define INT0_DDR DDRD -#define INT0_PORT PORTD -#define INT0_PIN PIND -#define INT0_BIT 2 - -#define INT1_DDR DDRD -#define INT1_PORT PORTD -#define INT1_PIN PIND -#define INT1_BIT 3 - -#define OC1B_DDR DDRD -#define OC1B_PORT PORTD -#define OC1B_PIN PIND -#define OC1B_BIT 4 - -#define OC1A_DDR DDRD -#define OC1A_PORT PORTD -#define OC1A_PIN PIND -#define OC1A_BIT 5 - -#define ICP_DDR DDRD -#define ICP_PORT PORTD -#define ICP_PIN PIND -#define ICP_BIT 6 - -#define OC2_DDR DDRD -#define OC2_PORT PORTD -#define OC2_PIN PIND -#define OC2_BIT 7 - -#define SCL_DDR DDRC -#define SCL_PORT PORTC -#define SCL_PIN PINC -#define SCL_BIT 0 - -#define SDA_DDR DDRC -#define SDA_PORT PORTC -#define SDA_PIN PINC -#define SDA_BIT 1 - -#define PC3_DDR DDRC -#define PC3_PORT PORTC -#define PC3_PIN PINC -#define PC3_BIT 3 - -#define PC4_DDR DDRC -#define PC4_PORT PORTC -#define PC4_PIN PINC -#define PC4_BIT 4 - -#define PC5_DDR DDRC -#define PC5_PORT PORTC -#define PC5_PIN PINC -#define PC5_BIT 5 - -#define ADC7_DDR DDRA -#define ADC7_PORT PORTA -#define ADC7_PIN PINA -#define ADC7_BIT 7 - -#define ADC6_DDR DDRA -#define ADC6_PORT PORTA -#define ADC6_PIN PINA -#define ADC6_BIT 6 - -#define ADc5_DDR DDRA -#define ADc5_PORT PORTA -#define ADc5_PIN PINA -#define ADc5_BIT 5 - -#define ADC4_DDR DDRA -#define ADC4_PORT PORTA -#define ADC4_PIN PINA -#define ADC4_BIT 4 - -#define ADC3_DDR DDRA -#define ADC3_PORT PORTA -#define ADC3_PIN PINA -#define ADC3_BIT 3 - -#define ADC2_DDR DDRA -#define ADC2_PORT PORTA -#define ADC2_PIN PINA -#define ADC2_BIT 2 - -#define ADC1_DDR DDRA -#define ADC1_PORT PORTA -#define ADC1_PIN PINA -#define ADC1_BIT 1 - -#define ADC0_DDR DDRA -#define ADC0_PORT PORTA -#define ADC0_PIN PINA -#define ADC0_BIT 0 - -#define T0_DDR DDRB -#define T0_PORT PORTB -#define T0_PIN PINB -#define T0_BIT 0 - -#define T1_DDR DDRB -#define T1_PORT PORTB -#define T1_PIN PINB -#define T1_BIT 1 - -#define AIN0_DDR DDRB -#define AIN0_PORT PORTB -#define AIN0_PIN PINB -#define AIN0_BIT 2 - -#define AIN1_DDR DDRB -#define AIN1_PORT PORTB -#define AIN1_PIN PINB -#define AIN1_BIT 3 - -#define SS_DDR DDRB -#define SS_PORT PORTB -#define SS_PIN PINB -#define SS_BIT 4 - -#define SLEEP_MODE_IDLE (0x00<<4) -#define SLEEP_MODE_ADC (0x01<<4) -#define SLEEP_MODE_PWR_DOWN (0x02<<4) -#define SLEEP_MODE_PWR_SAVE (0x03<<4) -#define SLEEP_MODE_STANDBY (0x0A<<4) -#define SLEEP_MODE_EXT_STANDBY (0x0B<<4) - -#endif /* _AVR_ATmega16A_H_ */ - diff --git a/arduino/hardware/tools/avr/avr/include/avr/iom16hva.h b/arduino/hardware/tools/avr/avr/include/avr/iom16hva.h deleted file mode 100644 index ba1caaf..0000000 --- a/arduino/hardware/tools/avr/avr/include/avr/iom16hva.h +++ /dev/null @@ -1,80 +0,0 @@ -/* Copyright (c) 2007, Anatoly Sokolov - All rights reserved. - - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - * Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - * Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in - the documentation and/or other materials provided with the - distribution. - - * Neither the name of the copyright holders nor the names of - contributors may be used to endorse or promote products derived - from this software without specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. */ - -/* $Id: iom16hva.h 2102 2010-03-16 22:52:39Z joerg_wunsch $ */ - -/* iom16hva.h - definitions for ATmega16HVA. */ - -#ifndef _AVR_IOM16HVA_H_ -#define _AVR_IOM16HVA_H_ 1 - -#include - -/* Constants */ -#define SPM_PAGESIZE 128 -#define RAMSTART 0x100 -#define RAMEND 0x2FF -#define XRAMEND RAMEND -#define E2END 0xFF -#define E2PAGESIZE 4 -#define FLASHEND 0x3FFF - - -/* Fuses */ - -#define FUSE_MEMORY_SIZE 1 - -/* Low Fuse Byte */ -#define FUSE_SUT0 (unsigned char)~_BV(0) -#define FUSE_SUT1 (unsigned char)~_BV(1) -#define FUSE_SUT2 (unsigned char)~_BV(2) -#define FUSE_SELFPRGEN (unsigned char)~_BV(3) -#define FUSE_DWEN (unsigned char)~_BV(4) -#define FUSE_SPIEN (unsigned char)~_BV(5) -#define FUSE_EESAVE (unsigned char)~_BV(6) -#define FUSE_WDTON (unsigned char)~_BV(7) -#define FUSE_DEFAULT (FUSE_SPIEN) - - -/* Lock Bits */ -#define __LOCK_BITS_EXIST - - -/* Signature */ -#define SIGNATURE_0 0x1E -#define SIGNATURE_1 0x94 -#define SIGNATURE_2 0x0C - -#define SLEEP_MODE_IDLE (0x00<<1) -#define SLEEP_MODE_ADC (0x01<<1) -#define SLEEP_MODE_PWR_SAVE (0x03<<1) -#define SLEEP_MODE_PWR_OFF (0x04<<1) - -#endif /* _AVR_IOM16HVA_H_ */ diff --git a/arduino/hardware/tools/avr/avr/include/avr/iom16hva2.h b/arduino/hardware/tools/avr/avr/include/avr/iom16hva2.h deleted file mode 100644 index 2ca27e5..0000000 --- a/arduino/hardware/tools/avr/avr/include/avr/iom16hva2.h +++ /dev/null @@ -1,883 +0,0 @@ -/* Copyright (c) 2009 Atmel Corporation - All rights reserved. - - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - * Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - * Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in - the documentation and/or other materials provided with the - distribution. - - * Neither the name of the copyright holders nor the names of - contributors may be used to endorse or promote products derived - from this software without specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. */ - -/* $Id: iom16hva2.h 2192 2010-11-08 13:53:24Z arcanum $ */ - -/* avr/iom16hva2.h - definitions for ATmega16HVA2 */ - -/* This file should only be included from , never directly. */ - -#ifndef _AVR_IO_H_ -# error "Include instead of this file." -#endif - -#ifndef _AVR_IOXXX_H_ -# define _AVR_IOXXX_H_ "iom16hva2.h" -#else -# error "Attempt to include more than one file." -#endif - - -#ifndef _AVR_ATmega16HVA2_H_ -#define _AVR_ATmega16HVA2_H_ 1 - - -/* Registers and associated bit numbers. */ - -#define PINA _SFR_IO8(0x00) -#define PINA0 0 -#define PINA1 1 - -#define DDRA _SFR_IO8(0x01) -#define DDA0 0 -#define DDA1 1 - -#define PORTA _SFR_IO8(0x02) -#define PORTA0 0 -#define PORTA1 1 - -#define PINB _SFR_IO8(0x03) -#define PINB0 0 -#define PINB1 1 -#define PINB2 2 -#define PINB3 3 - -#define DDRB _SFR_IO8(0x04) -#define DDB0 0 -#define DDB1 1 -#define DDB2 2 -#define DDB3 3 - -#define PORTB _SFR_IO8(0x05) -#define PORTB0 0 -#define PORTB1 1 -#define PORTB2 2 -#define PORTB3 3 - -#define PINC _SFR_IO8(0x06) -#define PINC0 0 - -#define PORTC _SFR_IO8(0x08) -#define PORTC0 0 - -#define TIFR0 _SFR_IO8(0x15) -#define TOV0 0 -#define OCF0A 1 -#define OCF0B 2 -#define ICF0 3 - -#define TIFR1 _SFR_IO8(0x16) -#define TOV1 0 -#define OCF1A 1 -#define OCF1B 2 -#define ICF1 3 - -#define OSICSR _SFR_IO8(0x17) -#define OSIEN 0 -#define OSIST 1 -#define OSISEL0 4 - -#define PCIFR _SFR_IO8(0x1B) -#define PCIF0 0 - -#define EIFR _SFR_IO8(0x1C) -#define INTF0 0 -#define INTF1 1 -#define INTF2 2 - -#define EIMSK _SFR_IO8(0x1D) -#define INT0 0 -#define INT1 1 -#define INT2 2 - -#define GPIOR0 _SFR_IO8(0x1E) -#define GPIOR00 0 -#define GPIOR01 1 -#define GPIOR02 2 -#define GPIOR03 3 -#define GPIOR04 4 -#define GPIOR05 5 -#define GPIOR06 6 -#define GPIOR07 7 - -#define EECR _SFR_IO8(0x1F) -#define EERE 0 -#define EEPE 1 -#define EEMPE 2 -#define EERIE 3 -#define EEPM0 4 -#define EEPM1 5 - -#define EEDR _SFR_IO8(0x20) -#define EEDR0 0 -#define EEDR1 1 -#define EEDR2 2 -#define EEDR3 3 -#define EEDR4 4 -#define EEDR5 5 -#define EEDR6 6 -#define EEDR7 7 - -#define EEAR _SFR_IO8(0x21) -#define EEAR0 0 -#define EEAR1 1 -#define EEAR2 2 -#define EEAR3 3 -#define EEAR4 4 -#define EEAR5 5 -#define EEAR6 6 -#define EEAR7 7 - -#define GTCCR _SFR_IO8(0x23) -#define PSRSYNC 0 -#define TSM 7 - -#define TCCR0A _SFR_IO8(0x24) -#define WGM00 0 -#define ICS0 3 -#define ICES0 4 -#define ICNC0 5 -#define ICEN0 6 -#define TCW0 7 - -#define TCCR0B _SFR_IO8(0x25) -#define CS00 0 -#define CS01 1 -#define CS02 2 - -#define TCNT0 _SFR_IO16(0x26) - -#define TCNT0L _SFR_IO8(0x26) -#define TCNT0L0 0 -#define TCNT0L1 1 -#define TCNT0L2 2 -#define TCNT0L3 3 -#define TCNT0L4 4 -#define TCNT0L5 5 -#define TCNT0L6 6 -#define TCNT0L7 7 - -#define TCNT0H _SFR_IO8(0x27) -#define TCNT0H0 0 -#define TCNT0H1 1 -#define TCNT0H2 2 -#define TCNT0H3 3 -#define TCNT0H4 4 -#define TCNT0H5 5 -#define TCNT0H6 6 -#define TCNT0H7 7 - -#define OCR0A _SFR_IO8(0x28) -#define OCR0A0 0 -#define OCR0A1 1 -#define OCR0A2 2 -#define OCR0A3 3 -#define OCR0A4 4 -#define OCR0A5 5 -#define OCR0A6 6 -#define OCR0A7 7 - -#define OCR0B _SFR_IO8(0x29) -#define OCR0B0 0 -#define OCR0B1 1 -#define OCR0B2 2 -#define OCR0B3 3 -#define OCR0B4 4 -#define OCR0B5 5 -#define OCR0B6 6 -#define OCR0B7 7 - -#define GPIOR1 _SFR_IO8(0x2A) -#define GPIOR10 0 -#define GPIOR11 1 -#define GPIOR12 2 -#define GPIOR13 3 -#define GPIOR14 4 -#define GPIOR15 5 -#define GPIOR16 6 -#define GPIOR17 7 - -#define GPIOR2 _SFR_IO8(0x2B) -#define GPIOR20 0 -#define GPIOR21 1 -#define GPIOR22 2 -#define GPIOR23 3 -#define GPIOR24 4 -#define GPIOR25 5 -#define GPIOR26 6 -#define GPIOR27 7 - -#define SPCR _SFR_IO8(0x2C) -#define SPR0 0 -#define SPR1 1 -#define CPHA 2 -#define CPOL 3 -#define MSTR 4 -#define DORD 5 -#define SPE 6 -#define SPIE 7 - -#define SPSR _SFR_IO8(0x2D) -#define SPI2X 0 -#define WCOL 6 -#define SPIF 7 - -#define SPDR _SFR_IO8(0x2E) -#define SPDR0 0 -#define SPDR1 1 -#define SPDR2 2 -#define SPDR3 3 -#define SPDR4 4 -#define SPDR5 5 -#define SPDR6 6 -#define SPDR7 7 - -#define DWDR _SFR_IO8(0x31) - -#define SMCR _SFR_IO8(0x33) -#define SE 0 -#define SM0 1 -#define SM1 2 -#define SM2 3 - -#define MCUSR _SFR_IO8(0x34) -#define PORF 0 -#define EXTRF 1 -#define BODRF 2 -#define WDRF 3 -#define OCDRF 4 - -#define MCUCR _SFR_IO8(0x35) -#define PUD 4 -#define CKOE 5 - -#define SPMCSR _SFR_IO8(0x37) -#define SPMEN 0 -#define PGERS 1 -#define PGWRT 2 -#define RFLB 3 -#define CTPB 4 -#define SIGRD 5 - -#define WDTCSR _SFR_MEM8(0x60) -#define WDP0 0 -#define WDP1 1 -#define WDP2 2 -#define WDE 3 -#define WDCE 4 -#define WDP3 5 -#define WDIE 6 -#define WDIF 7 - -#define CLKPR _SFR_MEM8(0x61) -#define CLKPS0 0 -#define CLKPS1 1 -#define CLKPCE 7 - -#define PRR0 _SFR_MEM8(0x64) -#define PRVADC 0 -#define PRTIM0 1 -#define PRTIM1 2 -#define PRSPI 3 -#define PRVRM 5 - -#define __AVR_HAVE_PRR0 ((1<, never directly. */ - -#ifndef _AVR_IO_H_ -# error "Include instead of this file." -#endif - -#ifndef _AVR_IOXXX_H_ -# define _AVR_IOXXX_H_ "iom16hvb.h" -#else -# error "Attempt to include more than one file." -#endif - - -#ifndef _AVR_ATmega16HVB_H_ -#define _AVR_ATmega16HVB_H_ 1 - - -/* Registers and associated bit numbers. */ - -#define PINA _SFR_IO8(0x00) -#define PINA0 0 -#define PINA1 1 -#define PINA2 2 -#define PINA3 3 - -#define DDRA _SFR_IO8(0x01) -#define DDA0 0 -#define DDA1 1 -#define DDA2 2 -#define DDA3 3 - -#define PORTA _SFR_IO8(0x02) -#define PORTA0 0 -#define PORTA1 1 -#define PORTA2 2 -#define PORTA3 3 - -#define PINB _SFR_IO8(0x03) -#define PINB0 0 -#define PINB1 1 -#define PINB2 2 -#define PINB3 3 -#define PINB4 4 -#define PINB5 5 -#define PINB6 6 -#define PINB7 7 - -#define DDRB _SFR_IO8(0x04) -#define DDB0 0 -#define DDB1 1 -#define DDB2 2 -#define DDB3 3 -#define DDB4 4 -#define DDB5 5 -#define DDB6 6 -#define DDB7 7 - -#define PORTB _SFR_IO8(0x05) -#define PORTB0 0 -#define PORTB1 1 -#define PORTB2 2 -#define PORTB3 3 -#define PORTB4 4 -#define PORTB5 5 -#define PORTB6 6 -#define PORTB7 7 - -#define PINC _SFR_IO8(0x06) -#define PINC0 0 -#define PINC1 1 -#define PINC2 2 -#define PINC3 3 -#define PINC4 4 - -#define PORTC _SFR_IO8(0x08) -#define PORTC0 0 -#define PORTC1 1 -#define PORTC2 2 -#define PORTC3 3 -#define PORTC4 4 -#define PORTC5 5 - -#define TIFR0 _SFR_IO8(0x15) -#define TOV0 0 -#define OCF0A 1 -#define OCF0B 2 -#define ICF0 3 - -#define TIFR1 _SFR_IO8(0x16) -#define TOV1 0 -#define OCF1A 1 -#define OCF1B 2 -#define ICF1 3 - -#define OSICSR _SFR_IO8(0x17) -#define OSIEN 0 -#define OSIST 1 -#define OSISEL0 4 - -#define PCIFR _SFR_IO8(0x1B) -#define PCIF0 0 -#define PCIF1 1 - -#define EIFR _SFR_IO8(0x1C) -#define INTF0 0 -#define INTF1 1 -#define INTF2 2 -#define INTF3 3 - -#define EIMSK _SFR_IO8(0x1D) -#define INT0 0 -#define INT1 1 -#define INT2 2 -#define INT3 3 - -#define GPIOR0 _SFR_IO8(0x1E) -#define GPIOR00 0 -#define GPIOR01 1 -#define GPIOR02 2 -#define GPIOR03 3 -#define GPIOR04 4 -#define GPIOR05 5 -#define GPIOR06 6 -#define GPIOR07 7 - -#define EECR _SFR_IO8(0x1F) -#define EERE 0 -#define EEPE 1 -#define EEMPE 2 -#define EERIE 3 -#define EEPM0 4 -#define EEPM1 5 - -#define EEDR _SFR_IO8(0x20) -#define EEDR0 0 -#define EEDR1 1 -#define EEDR2 2 -#define EEDR3 3 -#define EEDR4 4 -#define EEDR5 5 -#define EEDR6 6 -#define EEDR7 7 - -#define EEAR _SFR_IO16(0x21) - -#define EEARL _SFR_IO8(0x21) -#define EEAR0 0 -#define EEAR1 1 -#define EEAR2 2 -#define EEAR3 3 -#define EEAR4 4 -#define EEAR5 5 -#define EEAR6 6 -#define EEAR7 7 - -#define EEARH _SFR_IO8(0x22) -#define EEAR8 0 -#define EEAR9 1 - -#define GTCCR _SFR_IO8(0x23) -#define PSRSYNC 0 -#define TSM 7 - -#define TCCR0A _SFR_IO8(0x24) -#define WGM00 0 -#define ICS0 3 -#define ICES0 4 -#define ICNC0 5 -#define ICEN0 6 -#define TCW0 7 - -#define TCCR0B _SFR_IO8(0x25) -#define CS00 0 -#define CS01 1 -#define CS02 2 - -#define TCNT0 _SFR_IO16(0x26) - -#define TCNT0L _SFR_IO8(0x26) -#define TCNT0L0 0 -#define TCNT0L1 1 -#define TCNT0L2 2 -#define TCNT0L3 3 -#define TCNT0L4 4 -#define TCNT0L5 5 -#define TCNT0L6 6 -#define TCNT0L7 7 - -#define TCNT0H _SFR_IO8(0x27) -#define TCNT0H0 0 -#define TCNT0H1 1 -#define TCNT0H2 2 -#define TCNT0H3 3 -#define TCNT0H4 4 -#define TCNT0H5 5 -#define TCNT0H6 6 -#define TCNT0H7 7 - -#define OCR0A _SFR_IO8(0x28) -#define OCR0A0 0 -#define OCR0A1 1 -#define OCR0A2 2 -#define OCR0A3 3 -#define OCR0A4 4 -#define OCR0A5 5 -#define OCR0A6 6 -#define OCR0A7 7 - -#define OCR0B _SFR_IO8(0x29) -#define OCR0B0 0 -#define OCR0B1 1 -#define OCR0B2 2 -#define OCR0B3 3 -#define OCR0B4 4 -#define OCR0B5 5 -#define OCR0B6 6 -#define OCR0B7 7 - -#define GPIOR1 _SFR_IO8(0x2A) -#define GPIOR10 0 -#define GPIOR11 1 -#define GPIOR12 2 -#define GPIOR13 3 -#define GPIOR14 4 -#define GPIOR15 5 -#define GPIOR16 6 -#define GPIOR17 7 - -#define GPIOR2 _SFR_IO8(0x2B) -#define GPIOR20 0 -#define GPIOR21 1 -#define GPIOR22 2 -#define GPIOR23 3 -#define GPIOR24 4 -#define GPIOR25 5 -#define GPIOR26 6 -#define GPIOR27 7 - -#define SPCR _SFR_IO8(0x2C) -#define SPR0 0 -#define SPR1 1 -#define CPHA 2 -#define CPOL 3 -#define MSTR 4 -#define DORD 5 -#define SPE 6 -#define SPIE 7 - -#define SPSR _SFR_IO8(0x2D) -#define SPI2X 0 -#define WCOL 6 -#define SPIF 7 - -#define SPDR _SFR_IO8(0x2E) -#define SPDR0 0 -#define SPDR1 1 -#define SPDR2 2 -#define SPDR3 3 -#define SPDR4 4 -#define SPDR5 5 -#define SPDR6 6 -#define SPDR7 7 - -#define DWDR _SFR_IO8(0x31) - -#define SMCR _SFR_IO8(0x33) -#define SE 0 -#define SM0 1 -#define SM1 2 -#define SM2 3 - -#define MCUSR _SFR_IO8(0x34) -#define PORF 0 -#define EXTRF 1 -#define BODRF 2 -#define WDRF 3 -#define OCDRF 4 - -#define MCUCR _SFR_IO8(0x35) -#define IVCE 0 -#define IVSEL 1 -#define PUD 4 -#define CKOE 5 - -#define SPMCSR _SFR_IO8(0x37) -#define SPMEN 0 -#define PGERS 1 -#define PGWRT 2 -#define LBSET 3 -#define RWWSRE 4 -#define SIGRD 5 -#define RWWSB 6 -#define SPMIE 7 - -#define WDTCSR _SFR_MEM8(0x60) -#define WDP0 0 -#define WDP1 1 -#define WDP2 2 -#define WDE 3 -#define WDCE 4 -#define WDP3 5 -#define WDIE 6 -#define WDIF 7 - -#define CLKPR _SFR_MEM8(0x61) -#define CLKPS0 0 -#define CLKPS1 1 -#define CLKPCE 7 - -#define PRR0 _SFR_MEM8(0x64) -#define PRVADC 0 -#define PRTIM0 1 -#define PRTIM1 2 -#define PRSPI 3 -#define PRVRM 5 -#define PRTWI 6 - -#define __AVR_HAVE_PRR0 ((1<, never directly. */ - -#ifndef _AVR_IO_H_ -# error "Include instead of this file." -#endif - -#ifndef _AVR_IOXXX_H_ -# define _AVR_IOXXX_H_ "iom16hvbrevb.h" -#else -# error "Attempt to include more than one file." -#endif - - -#ifndef _AVR_ATmega16HVBREVB_H_ -#define _AVR_ATmega16HVBREVB_H_ 1 - - -/* Registers and associated bit numbers. */ - -#define PINA _SFR_IO8(0x00) -#define PINA0 0 -#define PINA1 1 -#define PINA2 2 -#define PINA3 3 - -#define DDRA _SFR_IO8(0x01) -#define DDA0 0 -#define DDA1 1 -#define DDA2 2 -#define DDA3 3 - -#define PORTA _SFR_IO8(0x02) -#define PORTA0 0 -#define PORTA1 1 -#define PORTA2 2 -#define PORTA3 3 - -#define PINB _SFR_IO8(0x03) -#define PINB0 0 -#define PINB1 1 -#define PINB2 2 -#define PINB3 3 -#define PINB4 4 -#define PINB5 5 -#define PINB6 6 -#define PINB7 7 - -#define DDRB _SFR_IO8(0x04) -#define DDB0 0 -#define DDB1 1 -#define DDB2 2 -#define DDB3 3 -#define DDB4 4 -#define DDB5 5 -#define DDB6 6 -#define DDB7 7 - -#define PORTB _SFR_IO8(0x05) -#define PORTB0 0 -#define PORTB1 1 -#define PORTB2 2 -#define PORTB3 3 -#define PORTB4 4 -#define PORTB5 5 -#define PORTB6 6 -#define PORTB7 7 - -#define PINC _SFR_IO8(0x06) -#define PINC0 0 -#define PINC1 1 -#define PINC2 2 -#define PINC3 3 -#define PINC4 4 - -#define PORTC _SFR_IO8(0x08) -#define PORTC0 0 -#define PORTC1 1 -#define PORTC2 2 -#define PORTC3 3 -#define PORTC4 4 -#define PORTC5 5 - -#define TIFR0 _SFR_IO8(0x15) -#define TOV0 0 -#define OCF0A 1 -#define OCF0B 2 -#define ICF0 3 - -#define TIFR1 _SFR_IO8(0x16) -#define TOV1 0 -#define OCF1A 1 -#define OCF1B 2 -#define ICF1 3 - -#define OSICSR _SFR_IO8(0x17) -#define OSIEN 0 -#define OSIST 1 -#define OSISEL0 4 - -#define PCIFR _SFR_IO8(0x1B) -#define PCIF0 0 -#define PCIF1 1 - -#define EIFR _SFR_IO8(0x1C) -#define INTF0 0 -#define INTF1 1 -#define INTF2 2 -#define INTF3 3 - -#define EIMSK _SFR_IO8(0x1D) -#define INT0 0 -#define INT1 1 -#define INT2 2 -#define INT3 3 - -#define GPIOR0 _SFR_IO8(0x1E) -#define GPIOR00 0 -#define GPIOR01 1 -#define GPIOR02 2 -#define GPIOR03 3 -#define GPIOR04 4 -#define GPIOR05 5 -#define GPIOR06 6 -#define GPIOR07 7 - -#define EECR _SFR_IO8(0x1F) -#define EERE 0 -#define EEPE 1 -#define EEMPE 2 -#define EERIE 3 -#define EEPM0 4 -#define EEPM1 5 - -#define EEDR _SFR_IO8(0x20) -#define EEDR0 0 -#define EEDR1 1 -#define EEDR2 2 -#define EEDR3 3 -#define EEDR4 4 -#define EEDR5 5 -#define EEDR6 6 -#define EEDR7 7 - -#define EEAR _SFR_IO16(0x21) - -#define EEARL _SFR_IO8(0x21) -#define EEAR0 0 -#define EEAR1 1 -#define EEAR2 2 -#define EEAR3 3 -#define EEAR4 4 -#define EEAR5 5 -#define EEAR6 6 -#define EEAR7 7 - -#define EEARH _SFR_IO8(0x22) -#define EEAR8 0 -#define EEAR9 1 - -#define GTCCR _SFR_IO8(0x23) -#define PSRSYNC 0 -#define TSM 7 - -#define TCCR0A _SFR_IO8(0x24) -#define WGM00 0 -#define ICS0 3 -#define ICES0 4 -#define ICNC0 5 -#define ICEN0 6 -#define TCW0 7 - -#define TCCR0B _SFR_IO8(0x25) -#define CS00 0 -#define CS01 1 -#define CS02 2 - -#define TCNT0 _SFR_IO16(0x26) - -#define TCNT0L _SFR_IO8(0x26) -#define TCNT0L0 0 -#define TCNT0L1 1 -#define TCNT0L2 2 -#define TCNT0L3 3 -#define TCNT0L4 4 -#define TCNT0L5 5 -#define TCNT0L6 6 -#define TCNT0L7 7 - -#define TCNT0H _SFR_IO8(0x27) -#define TCNT0H0 0 -#define TCNT0H1 1 -#define TCNT0H2 2 -#define TCNT0H3 3 -#define TCNT0H4 4 -#define TCNT0H5 5 -#define TCNT0H6 6 -#define TCNT0H7 7 - -#define OCR0A _SFR_IO8(0x28) -#define OCR0A0 0 -#define OCR0A1 1 -#define OCR0A2 2 -#define OCR0A3 3 -#define OCR0A4 4 -#define OCR0A5 5 -#define OCR0A6 6 -#define OCR0A7 7 - -#define OCR0B _SFR_IO8(0x29) -#define OCR0B0 0 -#define OCR0B1 1 -#define OCR0B2 2 -#define OCR0B3 3 -#define OCR0B4 4 -#define OCR0B5 5 -#define OCR0B6 6 -#define OCR0B7 7 - -#define GPIOR1 _SFR_IO8(0x2A) -#define GPIOR10 0 -#define GPIOR11 1 -#define GPIOR12 2 -#define GPIOR13 3 -#define GPIOR14 4 -#define GPIOR15 5 -#define GPIOR16 6 -#define GPIOR17 7 - -#define GPIOR2 _SFR_IO8(0x2B) -#define GPIOR20 0 -#define GPIOR21 1 -#define GPIOR22 2 -#define GPIOR23 3 -#define GPIOR24 4 -#define GPIOR25 5 -#define GPIOR26 6 -#define GPIOR27 7 - -#define SPCR _SFR_IO8(0x2C) -#define SPR0 0 -#define SPR1 1 -#define CPHA 2 -#define CPOL 3 -#define MSTR 4 -#define DORD 5 -#define SPE 6 -#define SPIE 7 - -#define SPSR _SFR_IO8(0x2D) -#define SPI2X 0 -#define WCOL 6 -#define SPIF 7 - -#define SPDR _SFR_IO8(0x2E) -#define SPDR0 0 -#define SPDR1 1 -#define SPDR2 2 -#define SPDR3 3 -#define SPDR4 4 -#define SPDR5 5 -#define SPDR6 6 -#define SPDR7 7 - -#define DWDR _SFR_IO8(0x31) - -#define SMCR _SFR_IO8(0x33) -#define SE 0 -#define SM0 1 -#define SM1 2 -#define SM2 3 - -#define MCUSR _SFR_IO8(0x34) -#define PORF 0 -#define EXTRF 1 -#define BODRF 2 -#define WDRF 3 -#define OCDRF 4 - -#define MCUCR _SFR_IO8(0x35) -#define IVCE 0 -#define IVSEL 1 -#define PUD 4 -#define CKOE 5 - -#define SPMCSR _SFR_IO8(0x37) -#define SPMEN 0 -#define PGERS 1 -#define PGWRT 2 -#define LBSET 3 -#define RWWSRE 4 -#define SIGRD 5 -#define RWWSB 6 -#define SPMIE 7 - -#define WDTCSR _SFR_MEM8(0x60) -#define WDP0 0 -#define WDP1 1 -#define WDP2 2 -#define WDE 3 -#define WDCE 4 -#define WDP3 5 -#define WDIE 6 -#define WDIF 7 - -#define CLKPR _SFR_MEM8(0x61) -#define CLKPS0 0 -#define CLKPS1 1 -#define CLKPCE 7 - -#define PRR0 _SFR_MEM8(0x64) -#define PRVADC 0 -#define PRTIM0 1 -#define PRTIM1 2 -#define PRSPI 3 -#define PRVRM 5 -#define PRTWI 6 - -#define __AVR_HAVE_PRR0 ((1<, never directly. */ - -#ifndef _AVR_IO_H_ -# error "Include instead of this file." -#endif - -#ifndef _AVR_IOXXX_H_ -# define _AVR_IOXXX_H_ "iom16m1.h" -#else -# error "Attempt to include more than one file." -#endif - - -#ifndef _AVR_ATmega16M1_H_ -#define _AVR_ATmega16M1_H_ 1 - - -/* Registers and associated bit numbers. */ - -#define PINB _SFR_IO8(0x03) -#define PINB0 0 -#define PINB1 1 -#define PINB2 2 -#define PINB3 3 -#define PINB4 4 -#define PINB5 5 -#define PINB6 6 -#define PINB7 7 - -#define DDRB _SFR_IO8(0x04) -#define DDB0 0 -#define DDB1 1 -#define DDB2 2 -#define DDB3 3 -#define DDB4 4 -#define DDB5 5 -#define DDB6 6 -#define DDB7 7 - -#define PORTB _SFR_IO8(0x05) -#define PORTB0 0 -#define PORTB1 1 -#define PORTB2 2 -#define PORTB3 3 -#define PORTB4 4 -#define PORTB5 5 -#define PORTB6 6 -#define PORTB7 7 - -#define PINC _SFR_IO8(0x06) -#define PINC0 0 -#define PINC1 1 -#define PINC2 2 -#define PINC3 3 -#define PINC4 4 -#define PINC5 5 -#define PINC6 6 -#define PINC7 7 - -#define DDRC _SFR_IO8(0x07) -#define DDC0 0 -#define DDC1 1 -#define DDC2 2 -#define DDC3 3 -#define DDC4 4 -#define DDC5 5 -#define DDC6 6 -#define DDC7 7 - -#define PORTC _SFR_IO8(0x08) -#define PORTC0 0 -#define PORTC1 1 -#define PORTC2 2 -#define PORTC3 3 -#define PORTC4 4 -#define PORTC5 5 -#define PORTC6 6 -#define PORTC7 7 - -#define PIND _SFR_IO8(0x09) -#define PIND0 0 -#define PIND1 1 -#define PIND2 2 -#define PIND3 3 -#define PIND4 4 -#define PIND5 5 -#define PIND6 6 -#define PIND7 7 - -#define DDRD _SFR_IO8(0x0A) -#define DDD0 0 -#define DDD1 1 -#define DDD2 2 -#define DDD3 3 -#define DDD4 4 -#define DDD5 5 -#define DDD6 6 -#define DDD7 7 - -#define PORTD _SFR_IO8(0x0B) -#define PORTD0 0 -#define PORTD1 1 -#define PORTD2 2 -#define PORTD3 3 -#define PORTD4 4 -#define PORTD5 5 -#define PORTD6 6 -#define PORTD7 7 - -#define PINE _SFR_IO8(0x0C) -#define PINE0 0 -#define PINE1 1 -#define PINE2 2 - -#define DDRE _SFR_IO8(0x0D) -#define DDE0 0 -#define DDE1 1 -#define DDE2 2 - -#define PORTE _SFR_IO8(0x0E) -#define PORTE0 0 -#define PORTE1 1 -#define PORTE2 2 - -#define TIFR0 _SFR_IO8(0x15) -#define TOV0 0 -#define OCF0A 1 -#define OCF0B 2 - -#define TIFR1 _SFR_IO8(0x16) -#define TOV1 0 -#define OCF1A 1 -#define OCF1B 2 -#define ICF1 5 - -#define GPIOR1 _SFR_IO8(0x19) -#define GPIOR10 0 -#define GPIOR11 1 -#define GPIOR12 2 -#define GPIOR13 3 -#define GPIOR14 4 -#define GPIOR15 5 -#define GPIOR16 6 -#define GPIOR17 7 - -#define GPIOR2 _SFR_IO8(0x1A) -#define GPIOR20 0 -#define GPIOR21 1 -#define GPIOR22 2 -#define GPIOR23 3 -#define GPIOR24 4 -#define GPIOR25 5 -#define GPIOR26 6 -#define GPIOR27 7 - -#define PCIFR _SFR_IO8(0x1B) -#define PCIF0 0 -#define PCIF1 1 -#define PCIF2 2 -#define PCIF3 3 - -#define EIFR _SFR_IO8(0x1C) -#define INTF0 0 -#define INTF1 1 -#define INTF2 2 -#define INTF3 3 - -#define EIMSK _SFR_IO8(0x1D) -#define INT0 0 -#define INT1 1 -#define INT2 2 -#define INT3 3 - -#define GPIOR0 _SFR_IO8(0x1E) -#define GPIOR00 0 -#define GPIOR01 1 -#define GPIOR02 2 -#define GPIOR03 3 -#define GPIOR04 4 -#define GPIOR05 5 -#define GPIOR06 6 -#define GPIOR07 7 - -#define EECR _SFR_IO8(0x1F) -#define EERE 0 -#define EEWE 1 -#define EEMWE 2 -#define EERIE 3 -#define EEPM0 4 -#define EEPM1 5 - -#define EEDR _SFR_IO8(0x20) -#define EEDR0 0 -#define EEDR1 1 -#define EEDR2 2 -#define EEDR3 3 -#define EEDR4 4 -#define EEDR5 5 -#define EEDR6 6 -#define EEDR7 7 - -#define EEAR _SFR_IO16(0x21) - -#define EEARL _SFR_IO8(0x21) -#define EEAR0 0 -#define EEAR1 1 -#define EEAR2 2 -#define EEAR3 3 -#define EEAR4 4 -#define EEAR5 5 -#define EEAR6 6 -#define EEAR7 7 - -#define EEARH _SFR_IO8(0x22) -#define EEAR8 0 -#define EEAR9 1 - -#define GTCCR _SFR_IO8(0x23) -#define PSR10 0 -#define PSRSYNC 0 -#define ICPSEL1 6 -#define TSM 7 - -#define TCCR0A _SFR_IO8(0x24) -#define WGM00 0 -#define WGM01 1 -#define COM0B0 4 -#define COM0B1 5 -#define COM0A0 6 -#define COM0A1 7 - -#define TCCR0B _SFR_IO8(0x25) -#define CS00 0 -#define CS01 1 -#define CS02 2 -#define WGM02 3 -#define FOC0B 6 -#define FOC0A 7 - -#define TCNT0 _SFR_IO8(0x26) -#define TCNT0_0 0 -#define TCNT0_1 1 -#define TCNT0_2 2 -#define TCNT0_3 3 -#define TCNT0_4 4 -#define TCNT0_5 5 -#define TCNT0_6 6 -#define TCNT0_7 7 - -#define OCR0A _SFR_IO8(0x27) -#define OCR0A_0 0 -#define OCR0A_1 1 -#define OCR0A_2 2 -#define OCR0A_3 3 -#define OCR0A_4 4 -#define OCR0A_5 5 -#define OCR0A_6 6 -#define OCR0A_7 7 - -#define OCR0B _SFR_IO8(0x28) -#define OCR0B_0 0 -#define OCR0B_1 1 -#define OCR0B_2 2 -#define OCR0B_3 3 -#define OCR0B_4 4 -#define OCR0B_5 5 -#define OCR0B_6 6 -#define OCR0B_7 7 - -#define PLLCSR _SFR_IO8(0x29) -#define PLOCK 0 -#define PLLE 1 -#define PLLF 2 - -#define SPCR _SFR_IO8(0x2C) -#define SPR0 0 -#define SPR1 1 -#define CPHA 2 -#define CPOL 3 -#define MSTR 4 -#define DORD 5 -#define SPE 6 -#define SPIE 7 - -#define SPSR _SFR_IO8(0x2D) -#define SPI2X 0 -#define WCOL 6 -#define SPIF 7 - -#define SPDR _SFR_IO8(0x2E) -#define SPDR0 0 -#define SPDR1 1 -#define SPDR2 2 -#define SPDR3 3 -#define SPDR4 4 -#define SPDR5 5 -#define SPDR6 6 -#define SPDR7 7 - -#define ACSR _SFR_IO8(0x30) -#define AC0O 0 -#define AC1O 1 -#define AC2O 2 -#define AC3O 3 -#define AC0IF 4 -#define AC1IF 5 -#define AC2IF 6 -#define AC3IF 7 - -#define DWDR _SFR_IO8(0x31) - -#define SMCR _SFR_IO8(0x33) -#define SE 0 -#define SM0 1 -#define SM1 2 -#define SM2 3 - -#define MCUSR _SFR_IO8(0x34) -#define PORF 0 -#define EXTRF 1 -#define BORF 2 -#define WDRF 3 - -#define MCUCR _SFR_IO8(0x35) -#define IVCE 0 -#define IVSEL 1 -#define PUD 4 -#define SPIPS 7 - -#define SPMCSR _SFR_IO8(0x37) -#define SPMEN 0 -#define PGERS 1 -#define PGWRT 2 -#define BLBSET 3 -#define RWWSRE 4 -#define SIGRD 5 -#define RWWSB 6 -#define SPMIE 7 - -#define WDTCSR _SFR_MEM8(0x60) -#define WDP0 0 -#define WDP1 1 -#define WDP2 2 -#define WDE 3 -#define WDCE 4 -#define WDP3 5 -#define WDIE 6 -#define WDIF 7 - -#define CLKPR _SFR_MEM8(0x61) -#define CLKPS0 0 -#define CLKPS1 1 -#define CLKPS2 2 -#define CLKPS3 3 -#define CLKPCE 7 - -#define PRR _SFR_MEM8(0x64) -#define PRADC 0 -#define PRLIN 1 -#define PRSPI 2 -#define PRTIM0 3 -#define PRTIM1 4 -#define PRPSC 5 -#define PRCAN 6 - -#define __AVR_HAVE_PRR ((1<, never directly. */ - -#ifndef _AVR_IO_H_ -# error "Include instead of this file." -#endif - -#ifndef _AVR_IOXXX_H_ -# define _AVR_IOXXX_H_ "iom16u2.h" -#else -# error "Attempt to include more than one file." -#endif - - -#ifndef _AVR_ATmega16U2_H_ -#define _AVR_ATmega16U2_H_ 1 - - -/* Registers and associated bit numbers. */ - -#define PINB _SFR_IO8(0x03) -#define PINB0 0 -#define PINB1 1 -#define PINB2 2 -#define PINB3 3 -#define PINB4 4 -#define PINB5 5 -#define PINB6 6 -#define PINB7 7 - -#define DDRB _SFR_IO8(0x04) -#define DDB0 0 -#define DDB1 1 -#define DDB2 2 -#define DDB3 3 -#define DDB4 4 -#define DDB5 5 -#define DDB6 6 -#define DDB7 7 - -#define PORTB _SFR_IO8(0x05) -#define PORTB0 0 -#define PORTB1 1 -#define PORTB2 2 -#define PORTB3 3 -#define PORTB4 4 -#define PORTB5 5 -#define PORTB6 6 -#define PORTB7 7 - -#define PINC _SFR_IO8(0x06) -#define PINC0 0 -#define PINC1 1 -#define PINC2 2 -#define PINC4 4 -#define PINC5 5 -#define PINC6 6 -#define PINC7 7 - -#define DDRC _SFR_IO8(0x07) -#define DDC0 0 -#define DDC1 1 -#define DDC2 2 -#define DDC4 4 -#define DDC5 5 -#define DDC6 6 -#define DDC7 7 - -#define PORTC _SFR_IO8(0x08) -#define PORTC0 0 -#define PORTC1 1 -#define PORTC2 2 -#define PORTC4 4 -#define PORTC5 5 -#define PORTC6 6 -#define PORTC7 7 - -#define PIND _SFR_IO8(0x09) -#define PIND0 0 -#define PIND1 1 -#define PIND2 2 -#define PIND3 3 -#define PIND4 4 -#define PIND5 5 -#define PIND6 6 -#define PIND7 7 - -#define DDRD _SFR_IO8(0x0A) -#define DDD0 0 -#define DDD1 1 -#define DDD2 2 -#define DDD3 3 -#define DDD4 4 -#define DDD5 5 -#define DDD6 6 -#define DDD7 7 - -#define PORTD _SFR_IO8(0x0B) -#define PORTD0 0 -#define PORTD1 1 -#define PORTD2 2 -#define PORTD3 3 -#define PORTD4 4 -#define PORTD5 5 -#define PORTD6 6 -#define PORTD7 7 - -#define TIFR0 _SFR_IO8(0x15) -#define TOV0 0 -#define OCF0A 1 -#define OCF0B 2 - -#define TIFR1 _SFR_IO8(0x16) -#define TOV1 0 -#define OCF1A 1 -#define OCF1B 2 -#define OCF1C 3 -#define ICF1 5 - -#define PCIFR _SFR_IO8(0x1B) -#define PCIF0 0 -#define PCIF1 1 - -#define EIFR _SFR_IO8(0x1C) -#define INTF0 0 -#define INTF1 1 -#define INTF2 2 -#define INTF3 3 -#define INTF4 4 -#define INTF5 5 -#define INTF6 6 -#define INTF7 7 - -#define EIMSK _SFR_IO8(0x1D) -#define INT0 0 -#define INT1 1 -#define INT2 2 -#define INT3 3 -#define INT4 4 -#define INT5 5 -#define INT6 6 -#define INT7 7 - -#define GPIOR0 _SFR_IO8(0x1E) -#define GPIOR00 0 -#define GPIOR01 1 -#define GPIOR02 2 -#define GPIOR03 3 -#define GPIOR04 4 -#define GPIOR05 5 -#define GPIOR06 6 -#define GPIOR07 7 - -#define EECR _SFR_IO8(0x1F) -#define EERE 0 -#define EEPE 1 -#define EEMPE 2 -#define EERIE 3 -#define EEPM0 4 -#define EEPM1 5 - -#define EEDR _SFR_IO8(0x20) -#define EEDR0 0 -#define EEDR1 1 -#define EEDR2 2 -#define EEDR3 3 -#define EEDR4 4 -#define EEDR5 5 -#define EEDR6 6 -#define EEDR7 7 - -#define EEAR _SFR_IO16(0x21) - -#define EEARL _SFR_IO8(0x21) -#define EEAR0 0 -#define EEAR1 1 -#define EEAR2 2 -#define EEAR3 3 -#define EEAR4 4 -#define EEAR5 5 -#define EEAR6 6 -#define EEAR7 7 - -#define EEARH _SFR_IO8(0x22) -#define EEAR8 0 -#define EEAR9 1 -#define EEAR10 2 -#define EEAR11 3 - -#define GTCCR _SFR_IO8(0x23) -#define PSRSYNC 0 -#define TSM 7 - -#define TCCR0A _SFR_IO8(0x24) -#define WGM00 0 -#define WGM01 1 -#define COM0B0 4 -#define COM0B1 5 -#define COM0A0 6 -#define COM0A1 7 - -#define TCCR0B _SFR_IO8(0x25) -#define CS00 0 -#define CS01 1 -#define CS02 2 -#define WGM02 3 -#define FOC0B 6 -#define FOC0A 7 - -#define TCNT0 _SFR_IO8(0x26) -#define TCNT0_0 0 -#define TCNT0_1 1 -#define TCNT0_2 2 -#define TCNT0_3 3 -#define TCNT0_4 4 -#define TCNT0_5 5 -#define TCNT0_6 6 -#define TCNT0_7 7 - -#define OCR0A _SFR_IO8(0x27) -#define OCR0A_0 0 -#define OCR0A_1 1 -#define OCR0A_2 2 -#define OCR0A_3 3 -#define OCR0A_4 4 -#define OCR0A_5 5 -#define OCR0A_6 6 -#define OCR0A_7 7 - -#define OCR0B _SFR_IO8(0x28) -#define OCR0B_0 0 -#define OCR0B_1 1 -#define OCR0B_2 2 -#define OCR0B_3 3 -#define OCR0B_4 4 -#define OCR0B_5 5 -#define OCR0B_6 6 -#define OCR0B_7 7 - -#define PLLCSR _SFR_IO8(0x29) -#define PLOCK 0 -#define PLLE 1 -#define PLLP0 2 -#define PLLP1 3 -#define PLLP2 4 - -#define GPIOR1 _SFR_IO8(0x2A) -#define GPIOR10 0 -#define GPIOR11 1 -#define GPIOR12 2 -#define GPIOR13 3 -#define GPIOR14 4 -#define GPIOR15 5 -#define GPIOR16 6 -#define GPIOR17 7 - -#define GPIOR2 _SFR_IO8(0x2B) -#define GPIOR20 0 -#define GPIOR21 1 -#define GPIOR22 2 -#define GPIOR23 3 -#define GPIOR24 4 -#define GPIOR25 5 -#define GPIOR26 6 -#define GPIOR27 7 - -#define SPCR _SFR_IO8(0x2C) -#define SPR0 0 -#define SPR1 1 -#define CPHA 2 -#define CPOL 3 -#define MSTR 4 -#define DORD 5 -#define SPE 6 -#define SPIE 7 - -#define SPSR _SFR_IO8(0x2D) -#define SPI2X 0 -#define WCOL 6 -#define SPIF 7 - -#define SPDR _SFR_IO8(0x2E) -#define SPDR0 0 -#define SPDR1 1 -#define SPDR2 2 -#define SPDR3 3 -#define SPDR4 4 -#define SPDR5 5 -#define SPDR6 6 -#define SPDR7 7 - -#define ACSR _SFR_IO8(0x30) -#define ACIS0 0 -#define ACIS1 1 -#define ACIC 2 -#define ACIE 3 -#define ACI 4 -#define ACO 5 -#define ACBG 6 -#define ACD 7 - -#define DWDR _SFR_IO8(0x31) -#define DWDR0 0 -#define DWDR1 1 -#define DWDR2 2 -#define DWDR3 3 -#define DWDR4 4 -#define DWDR5 5 -#define DWDR6 6 -#define DWDR7 7 - -#define SMCR _SFR_IO8(0x33) -#define SE 0 -#define SM0 1 -#define SM1 2 -#define SM2 3 - -#define MCUSR _SFR_IO8(0x34) -#define PORF 0 -#define EXTRF 1 -#define BORF 2 -#define WDRF 3 -#define USBRF 5 - -#define MCUCR _SFR_IO8(0x35) -#define IVCE 0 -#define IVSEL 1 -#define PUD 4 - -#define SPMCSR _SFR_IO8(0x37) -#define SPMEN 0 -#define PGERS 1 -#define PGWRT 2 -#define BLBSET 3 -#define RWWSRE 4 -#define SIGRD 5 -#define RWWSB 6 -#define SPMIE 7 - -#define EIND _SFR_IO8(0x3C) -#define EIND0 0 - -#define WDTCSR _SFR_MEM8(0x60) -#define WDP0 0 -#define WDP1 1 -#define WDP2 2 -#define WDE 3 -#define WDCE 4 -#define WDP3 5 -#define WDIE 6 -#define WDIF 7 - -#define CLKPR _SFR_MEM8(0x61) -#define CLKPS0 0 -#define CLKPS1 1 -#define CLKPS2 2 -#define CLKPS3 3 -#define CLKPCE 7 - -#define WDTCKD _SFR_MEM8(0x62) -#define WCLKD0 0 -#define WCLKD1 1 -#define WDEWIE 2 -#define WDEWIF 3 - -#define REGCR _SFR_MEM8(0x63) -#define REGDIS 0 - -#define PRR0 _SFR_MEM8(0x64) -#define PRSPI 2 -#define PRTIM1 3 -#define PRTIM0 5 - -#define __AVR_HAVE_PRR0 ((1<, never directly. */ - -#ifndef _AVR_IO_H_ -# error "Include instead of this file." -#endif - -#ifndef _AVR_IOXXX_H_ -# define _AVR_IOXXX_H_ "iom16u4.h" -#else -# error "Attempt to include more than one file." -#endif - - -#ifndef _AVR_ATmega16U4_H_ -#define _AVR_ATmega16U4_H_ 1 - - -/* Registers and associated bit numbers. */ - -#define PINB _SFR_IO8(0x03) -#define PINB0 0 -#define PINB1 1 -#define PINB2 2 -#define PINB3 3 -#define PINB4 4 -#define PINB5 5 -#define PINB6 6 -#define PINB7 7 - -#define DDRB _SFR_IO8(0x04) -#define DDB0 0 -#define DDB1 1 -#define DDB2 2 -#define DDB3 3 -#define DDB4 4 -#define DDB5 5 -#define DDB6 6 -#define DDB7 7 - -#define PORTB _SFR_IO8(0x05) -#define PORTB0 0 -#define PORTB1 1 -#define PORTB2 2 -#define PORTB3 3 -#define PORTB4 4 -#define PORTB5 5 -#define PORTB6 6 -#define PORTB7 7 - -#define PINC _SFR_IO8(0x06) -#define PINC6 6 -#define PINC7 7 - -#define DDRC _SFR_IO8(0x07) -#define DDC6 6 -#define DDC7 7 - -#define PORTC _SFR_IO8(0x08) -#define PORTC6 6 -#define PORTC7 7 - -#define PIND _SFR_IO8(0x09) -#define PIND0 0 -#define PIND1 1 -#define PIND2 2 -#define PIND3 3 -#define PIND4 4 -#define PIND5 5 -#define PIND6 6 -#define PIND7 7 - -#define DDRD _SFR_IO8(0x0A) -#define DDD0 0 -#define DDD1 1 -#define DDD2 2 -#define DDD3 3 -#define DDD4 4 -#define DDD5 5 -#define DDD6 6 -#define DDD7 7 - -#define PORTD _SFR_IO8(0x0B) -#define PORTD0 0 -#define PORTD1 1 -#define PORTD2 2 -#define PORTD3 3 -#define PORTD4 4 -#define PORTD5 5 -#define PORTD6 6 -#define PORTD7 7 - -#define PINE _SFR_IO8(0x0C) -#define PINE2 2 -#define PINE6 6 - -#define DDRE _SFR_IO8(0x0D) -#define DDE2 2 -#define DDE6 6 - -#define PORTE _SFR_IO8(0x0E) -#define PORTE2 2 -#define PORTE6 6 - -#define PINF _SFR_IO8(0x0F) -#define PINF0 0 -#define PINF1 1 -#define PINF4 4 -#define PINF5 5 -#define PINF6 6 -#define PINF7 7 - -#define DDRF _SFR_IO8(0x10) -#define DDF0 0 -#define DDF1 1 -#define DDF4 4 -#define DDF5 5 -#define DDF6 6 -#define DDF7 7 - -#define PORTF _SFR_IO8(0x11) -#define PORTF0 0 -#define PORTF1 1 -#define PORTF4 4 -#define PORTF5 5 -#define PORTF6 6 -#define PORTF7 7 - -#define TIFR0 _SFR_IO8(0x15) -#define TOV0 0 -#define OCF0A 1 -#define OCF0B 2 - -#define TIFR1 _SFR_IO8(0x16) -#define TOV1 0 -#define OCF1A 1 -#define OCF1B 2 -#define OCF1C 3 -#define ICF1 5 - -#define TIFR2 _SFR_IO8(0x17) - -#define TIFR3 _SFR_IO8(0x18) -#define TOV3 0 -#define OCF3A 1 -#define OCF3B 2 -#define OCF3C 3 -#define ICF3 5 - -#define TIFR4 _SFR_IO8(0x19) -#define TOV4 2 -#define OCF4B 5 -#define OCF4A 6 -#define OCF4D 7 - -#define PCIFR _SFR_IO8(0x1B) -#define PCIF0 0 - -#define EIFR _SFR_IO8(0x1C) -#define INTF0 0 -#define INTF1 1 -#define INTF2 2 -#define INTF3 3 -#define INTF4 4 -#define INTF5 5 -#define INTF6 6 -#define INTF7 7 - -#define EIMSK _SFR_IO8(0x1D) -#define INT0 0 -#define INT1 1 -#define INT2 2 -#define INT3 3 -#define INT4 4 -#define INT5 5 -#define INT6 6 -#define INT7 7 - -#define GPIOR0 _SFR_IO8(0x1E) -#define GPIOR00 0 -#define GPIOR01 1 -#define GPIOR02 2 -#define GPIOR03 3 -#define GPIOR04 4 -#define GPIOR05 5 -#define GPIOR06 6 -#define GPIOR07 7 - -#define EECR _SFR_IO8(0x1F) -#define EERE 0 -#define EEPE 1 -#define EEMPE 2 -#define EERIE 3 -#define EEPM0 4 -#define EEPM1 5 - -#define EEDR _SFR_IO8(0x20) -#define EEDR0 0 -#define EEDR1 1 -#define EEDR2 2 -#define EEDR3 3 -#define EEDR4 4 -#define EEDR5 5 -#define EEDR6 6 -#define EEDR7 7 - -#define EEAR _SFR_IO16(0x21) - -#define EEARL _SFR_IO8(0x21) -#define EEAR0 0 -#define EEAR1 1 -#define EEAR2 2 -#define EEAR3 3 -#define EEAR4 4 -#define EEAR5 5 -#define EEAR6 6 -#define EEAR7 7 - -#define EEARH _SFR_IO8(0x22) -#define EEAR8 0 -#define EEAR9 1 -#define EEAR10 2 -#define EEAR11 3 - -#define GTCCR _SFR_IO8(0x23) -#define PSRSYNC 0 -#define TSM 7 - -#define TCCR0A _SFR_IO8(0x24) -#define WGM00 0 -#define WGM01 1 -#define COM0B0 4 -#define COM0B1 5 -#define COM0A0 6 -#define COM0A1 7 - -#define TCCR0B _SFR_IO8(0x25) -#define CS00 0 -#define CS01 1 -#define CS02 2 -#define WGM02 3 -#define FOC0B 6 -#define FOC0A 7 - -#define TCNT0 _SFR_IO8(0x26) -#define TCNT0_0 0 -#define TCNT0_1 1 -#define TCNT0_2 2 -#define TCNT0_3 3 -#define TCNT0_4 4 -#define TCNT0_5 5 -#define TCNT0_6 6 -#define TCNT0_7 7 - -#define OCR0A _SFR_IO8(0x27) -#define OCROA_0 0 -#define OCROA_1 1 -#define OCROA_2 2 -#define OCROA_3 3 -#define OCROA_4 4 -#define OCROA_5 5 -#define OCROA_6 6 -#define OCROA_7 7 - -#define OCR0B _SFR_IO8(0x28) -#define OCR0B_0 0 -#define OCR0B_1 1 -#define OCR0B_2 2 -#define OCR0B_3 3 -#define OCR0B_4 4 -#define OCR0B_5 5 -#define OCR0B_6 6 -#define OCR0B_7 7 - -#define PLLCSR _SFR_IO8(0x29) -#define PLOCK 0 -#define PLLE 1 -#define PINDIV 4 - -#define GPIOR1 _SFR_IO8(0x2A) -#define GPIOR10 0 -#define GPIOR11 1 -#define GPIOR12 2 -#define GPIOR13 3 -#define GPIOR14 4 -#define GPIOR15 5 -#define GPIOR16 6 -#define GPIOR17 7 - -#define GPIOR2 _SFR_IO8(0x2B) -#define GPIOR20 0 -#define GPIOR21 1 -#define GPIOR22 2 -#define GPIOR23 3 -#define GPIOR24 4 -#define GPIOR25 5 -#define GPIOR26 6 -#define GPIOR27 7 - -#define SPCR _SFR_IO8(0x2C) -#define SPR0 0 -#define SPR1 1 -#define CPHA 2 -#define CPOL 3 -#define MSTR 4 -#define DORD 5 -#define SPE 6 -#define SPIE 7 - -#define SPSR _SFR_IO8(0x2D) -#define SPI2X 0 -#define WCOL 6 -#define SPIF 7 - -#define SPDR _SFR_IO8(0x2E) -#define SPDR0 0 -#define SPDR1 1 -#define SPDR2 2 -#define SPDR3 3 -#define SPDR4 4 -#define SPDR5 5 -#define SPDR6 6 -#define SPDR7 7 - -#define ACSR _SFR_IO8(0x30) -#define ACIS0 0 -#define ACIS1 1 -#define ACIC 2 -#define ACIE 3 -#define ACI 4 -#define ACO 5 -#define ACBG 6 -#define ACD 7 - -#define OCDR _SFR_IO8(0x31) -#define OCDR0 0 -#define OCDR1 1 -#define OCDR2 2 -#define OCDR3 3 -#define OCDR4 4 -#define OCDR5 5 -#define OCDR6 6 -#define OCDR7 7 - -#define PLLFRQ _SFR_IO8(0x32) -#define PDIV0 0 -#define PDIV1 1 -#define PDIV2 2 -#define PDIV3 3 -#define PLLTM0 4 -#define PLLTM1 5 -#define PLLUSB 6 -#define PINMUX 7 - -#define SMCR _SFR_IO8(0x33) -#define SE 0 -#define SM0 1 -#define SM1 2 -#define SM2 3 - -#define MCUSR _SFR_IO8(0x34) -#define PORF 0 -#define EXTRF 1 -#define BORF 2 -#define WDRF 3 -#define JTRF 4 - -#define MCUCR _SFR_IO8(0x35) -#define IVCE 0 -#define IVSEL 1 -#define PUD 4 -#define JTD 7 - -#define SPMCSR _SFR_IO8(0x37) -#define SPMEN 0 -#define PGERS 1 -#define PGWRT 2 -#define BLBSET 3 -#define RWWSRE 4 -#define SIGRD 5 -#define RWWSB 6 -#define SPMIE 7 - -#define RAMPZ _SFR_IO8(0x3B) -#define RAMPZ0 0 - -#define EIND _SFR_IO8(0x3C) -#define EIND0 0 - -#define WDTCSR _SFR_MEM8(0x60) -#define WDP0 0 -#define WDP1 1 -#define WDP2 2 -#define WDE 3 -#define WDCE 4 -#define WDP3 5 -#define WDIE 6 -#define WDIF 7 - -#define CLKPR _SFR_MEM8(0x61) -#define CLKPS0 0 -#define CLKPS1 1 -#define CLKPS2 2 -#define CLKPS3 3 -#define CLKPCE 7 - -#define PRR0 _SFR_MEM8(0x64) -#define PRADC 0 -#define PRUSART0 1 -#define PRSPI 2 -#define PRTIM1 3 -#define PRTIM0 5 -#define PRTIM2 6 -#define PRTWI 7 - -#define __AVR_HAVE_PRR0 ((1< - -/* Constants */ -#define SPM_PAGESIZE 256 -#define RAMSTART 0x200 -#define RAMEND 0x21FF -#define XRAMEND 0xFFFF -#define E2END 0xFFF -#define E2PAGESIZE 8 -#define FLASHEND 0x3FFFF - - -/* Fuses */ - -#define FUSE_MEMORY_SIZE 3 - -/* Low Fuse Byte */ -#define FUSE_CKSEL0 (unsigned char)~_BV(0) -#define FUSE_CKSEL1 (unsigned char)~_BV(1) -#define FUSE_CKSEL2 (unsigned char)~_BV(2) -#define FUSE_CKSEL3 (unsigned char)~_BV(3) -#define FUSE_SUT0 (unsigned char)~_BV(4) -#define FUSE_SUT1 (unsigned char)~_BV(5) -#define FUSE_CKOUT (unsigned char)~_BV(6) -#define FUSE_CKDIV8 (unsigned char)~_BV(7) -#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8) - -/* High Fuse Byte */ -#define FUSE_BOOTRST (unsigned char)~_BV(0) -#define FUSE_BOOTSZ0 (unsigned char)~_BV(1) -#define FUSE_BOOTSZ1 (unsigned char)~_BV(2) -#define FUSE_EESAVE (unsigned char)~_BV(3) -#define FUSE_WDTON (unsigned char)~_BV(4) -#define FUSE_SPIEN (unsigned char)~_BV(5) -#define FUSE_JTAGEN (unsigned char)~_BV(6) -#define FUSE_OCDEN (unsigned char)~_BV(7) -#define HFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_SPIEN & FUSE_JTAGEN) - -/* Extended Fuse Byte */ -#define FUSE_BODLEVEL0 (unsigned char)~_BV(0) -#define FUSE_BODLEVEL1 (unsigned char)~_BV(1) -#define FUSE_BODLEVEL2 (unsigned char)~_BV(2) -#define EFUSE_DEFAULT (0xFF) - - -/* Lock Bits */ -#define __LOCK_BITS_EXIST -#define __BOOT_LOCK_BITS_0_EXIST -#define __BOOT_LOCK_BITS_1_EXIST - - -/* Signature */ -#define SIGNATURE_0 0x1E -#define SIGNATURE_1 0x98 -#define SIGNATURE_2 0x01 - -#define SLEEP_MODE_IDLE (0x00<<1) -#define SLEEP_MODE_ADC (0x01<<1) -#define SLEEP_MODE_PWR_DOWN (0x02<<1) -#define SLEEP_MODE_PWR_SAVE (0x03<<1) -#define SLEEP_MODE_STANDBY (0x06<<1) -#define SLEEP_MODE_EXT_STANDBY (0x07<<1) - -#endif /* _AVR_IOM2560_H_ */ diff --git a/arduino/hardware/tools/avr/avr/include/avr/iom2561.h b/arduino/hardware/tools/avr/avr/include/avr/iom2561.h deleted file mode 100644 index cd065c5..0000000 --- a/arduino/hardware/tools/avr/avr/include/avr/iom2561.h +++ /dev/null @@ -1,101 +0,0 @@ -/* Copyright (c) 2005 Anatoly Sokolov - All rights reserved. - - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - * Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - * Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in - the documentation and/or other materials provided with the - distribution. - - * Neither the name of the copyright holders nor the names of - contributors may be used to endorse or promote products derived - from this software without specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. */ - -/* $Id */ - -/* avr/iom2561.h - definitions for ATmega2561 */ - -#ifndef _AVR_IOM2561_H_ -#define _AVR_IOM2561_H_ 1 - -#include - -/* Constants */ -#define SPM_PAGESIZE 256 -#define RAMSTART 0x200 -#define RAMEND 0x21FF -#define XRAMEND 0xFFFF -#define E2END 0xFFF -#define E2PAGESIZE 8 -#define FLASHEND 0x3FFFF - - -/* Fuses */ - -#define FUSE_MEMORY_SIZE 3 - -/* Low Fuse Byte */ -#define FUSE_CKSEL0 (unsigned char)~_BV(0) -#define FUSE_CKSEL1 (unsigned char)~_BV(1) -#define FUSE_CKSEL2 (unsigned char)~_BV(2) -#define FUSE_CKSEL3 (unsigned char)~_BV(3) -#define FUSE_SUT0 (unsigned char)~_BV(4) -#define FUSE_SUT1 (unsigned char)~_BV(5) -#define FUSE_CKOUT (unsigned char)~_BV(6) -#define FUSE_CKDIV8 (unsigned char)~_BV(7) -#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8) - -/* High Fuse Byte */ -#define FUSE_BOOTRST (unsigned char)~_BV(0) -#define FUSE_BOOTSZ0 (unsigned char)~_BV(1) -#define FUSE_BOOTSZ1 (unsigned char)~_BV(2) -#define FUSE_EESAVE (unsigned char)~_BV(3) -#define FUSE_WDTON (unsigned char)~_BV(4) -#define FUSE_SPIEN (unsigned char)~_BV(5) -#define FUSE_JTAGEN (unsigned char)~_BV(6) -#define FUSE_OCDEN (unsigned char)~_BV(7) -#define HFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_SPIEN & FUSE_JTAGEN) - -/* Extended Fuse Byte */ -#define FUSE_BODLEVEL0 (unsigned char)~_BV(0) -#define FUSE_BODLEVEL1 (unsigned char)~_BV(1) -#define FUSE_BODLEVEL2 (unsigned char)~_BV(2) -#define EFUSE_DEFAULT (0xFF) - - -/* Lock Bits */ -#define __LOCK_BITS_EXIST -#define __BOOT_LOCK_BITS_0_EXIST -#define __BOOT_LOCK_BITS_1_EXIST - - -/* Signature */ -#define SIGNATURE_0 0x1E -#define SIGNATURE_1 0x98 -#define SIGNATURE_2 0x02 - -#define SLEEP_MODE_IDLE (0x00<<1) -#define SLEEP_MODE_ADC (0x01<<1) -#define SLEEP_MODE_PWR_DOWN (0x02<<1) -#define SLEEP_MODE_PWR_SAVE (0x03<<1) -#define SLEEP_MODE_STANDBY (0x06<<1) -#define SLEEP_MODE_EXT_STANDBY (0x07<<1) - -#endif /* _AVR_IOM2561_H_ */ diff --git a/arduino/hardware/tools/avr/avr/include/avr/iom2564rfr2.h b/arduino/hardware/tools/avr/avr/include/avr/iom2564rfr2.h deleted file mode 100644 index 3870f8a..0000000 --- a/arduino/hardware/tools/avr/avr/include/avr/iom2564rfr2.h +++ /dev/null @@ -1,2691 +0,0 @@ -/***************************************************************************** - * - * Copyright (C) 2015 Atmel Corporation - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * - * * Neither the name of the copyright holders nor the names of - * contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - ****************************************************************************/ - - -#ifndef _AVR_ATMEGA2564RFR2_H_INCLUDED -#define _AVR_ATMEGA2564RFR2_H_INCLUDED - - -#ifndef _AVR_IO_H_ -# error "Include instead of this file." -#endif - -#ifndef _AVR_IOXXX_H_ -# define _AVR_IOXXX_H_ "iom2564rfr2.h" -#else -# error "Attempt to include more than one file." -#endif - -/* Registers and associated bit numbers */ - -#define PINA _SFR_IO8(0x00) -#define PINA7 7 -#define PINA6 6 -#define PINA5 5 -#define PINA4 4 -#define PINA3 3 -#define PINA2 2 -#define PINA1 1 -#define PINA0 0 - -#define DDRA _SFR_IO8(0x01) -#define DDRA7 7 -// Inserted "DDA7" from "DDRA7" due to compatibility -#define DDA7 7 -#define DDRA6 6 -// Inserted "DDA6" from "DDRA6" due to compatibility -#define DDA6 6 -#define DDRA5 5 -// Inserted "DDA5" from "DDRA5" due to compatibility -#define DDA5 5 -#define DDRA4 4 -// Inserted "DDA4" from "DDRA4" due to compatibility -#define DDA4 4 -#define DDRA3 3 -// Inserted "DDA3" from "DDRA3" due to compatibility -#define DDA3 3 -#define DDRA2 2 -// Inserted "DDA2" from "DDRA2" due to compatibility -#define DDA2 2 -#define DDRA1 1 -// Inserted "DDA1" from "DDRA1" due to compatibility -#define DDA1 1 -#define DDRA0 0 -// Inserted "DDA0" from "DDRA0" due to compatibility -#define DDA0 0 - -#define PORTA _SFR_IO8(0x02) -#define PORTA7 7 -#define PORTA6 6 -#define PORTA5 5 -#define PORTA4 4 -#define PORTA3 3 -#define PORTA2 2 -#define PORTA1 1 -#define PORTA0 0 - -#define PINB _SFR_IO8(0x03) -#define PINB7 7 -#define PINB6 6 -#define PINB5 5 -#define PINB4 4 -#define PINB3 3 -#define PINB2 2 -#define PINB1 1 -#define PINB0 0 - -#define DDRB _SFR_IO8(0x04) -#define DDRB7 7 -// Inserted "DDB7" from "DDRB7" due to compatibility -#define DDB7 7 -#define DDRB6 6 -// Inserted "DDB6" from "DDRB6" due to compatibility -#define DDB6 6 -#define DDRB5 5 -// Inserted "DDB5" from "DDRB5" due to compatibility -#define DDB5 5 -#define DDRB4 4 -// Inserted "DDB4" from "DDRB4" due to compatibility -#define DDB4 4 -#define DDRB3 3 -// Inserted "DDB3" from "DDRB3" due to compatibility -#define DDB3 3 -#define DDRB2 2 -// Inserted "DDB2" from "DDRB2" due to compatibility -#define DDB2 2 -#define DDRB1 1 -// Inserted "DDB1" from "DDRB1" due to compatibility -#define DDB1 1 -#define DDRB0 0 -// Inserted "DDB0" from "DDRB0" due to compatibility -#define DDB0 0 - -#define PORTB _SFR_IO8(0x05) -#define PORTB7 7 -#define PORTB6 6 -#define PORTB5 5 -#define PORTB4 4 -#define PORTB3 3 -#define PORTB2 2 -#define PORTB1 1 -#define PORTB0 0 - -#define PINC _SFR_IO8(0x06) -#define PINC7 7 -#define PINC6 6 -#define PINC5 5 -#define PINC4 4 -#define PINC3 3 -#define PINC2 2 -#define PINC1 1 -#define PINC0 0 - -#define DDRC _SFR_IO8(0x07) -#define DDRC7 7 -// Inserted "DDC7" from "DDRC7" due to compatibility -#define DDC7 7 -#define DDRC6 6 -// Inserted "DDC6" from "DDRC6" due to compatibility -#define DDC6 6 -#define DDRC5 5 -// Inserted "DDC5" from "DDRC5" due to compatibility -#define DDC5 5 -#define DDRC4 4 -// Inserted "DDC4" from "DDRC4" due to compatibility -#define DDC4 4 -#define DDRC3 3 -// Inserted "DDC3" from "DDRC3" due to compatibility -#define DDC3 3 -#define DDRC2 2 -// Inserted "DDC2" from "DDRC2" due to compatibility -#define DDC2 2 -#define DDRC1 1 -// Inserted "DDC1" from "DDRC1" due to compatibility -#define DDC1 1 -#define DDRC0 0 -// Inserted "DDC0" from "DDRC0" due to compatibility -#define DDC0 0 - -#define PORTC _SFR_IO8(0x08) -#define PORTC7 7 -#define PORTC6 6 -#define PORTC5 5 -#define PORTC4 4 -#define PORTC3 3 -#define PORTC2 2 -#define PORTC1 1 -#define PORTC0 0 - -#define PIND _SFR_IO8(0x09) -#define PIND7 7 -#define PIND6 6 -#define PIND5 5 -#define PIND4 4 -#define PIND3 3 -#define PIND2 2 -#define PIND1 1 -#define PIND0 0 - -#define DDRD _SFR_IO8(0x0A) -#define DDRD7 7 -// Inserted "DDD7" from "DDRD7" due to compatibility -#define DDD7 7 -#define DDRD6 6 -// Inserted "DDD6" from "DDRD6" due to compatibility -#define DDD6 6 -#define DDRD5 5 -// Inserted "DDD5" from "DDRD5" due to compatibility -#define DDD5 5 -#define DDRD4 4 -// Inserted "DDD4" from "DDRD4" due to compatibility -#define DDD4 4 -#define DDRD3 3 -// Inserted "DDD3" from "DDRD3" due to compatibility -#define DDD3 3 -#define DDRD2 2 -// Inserted "DDD2" from "DDRD2" due to compatibility -#define DDD2 2 -#define DDRD1 1 -// Inserted "DDD1" from "DDRD1" due to compatibility -#define DDD1 1 -#define DDRD0 0 -// Inserted "DDD0" from "DDRD0" due to compatibility -#define DDD0 0 - -#define PORTD _SFR_IO8(0x0B) -#define PORTD7 7 -#define PORTD6 6 -#define PORTD5 5 -#define PORTD4 4 -#define PORTD3 3 -#define PORTD2 2 -#define PORTD1 1 -#define PORTD0 0 - -#define PINE _SFR_IO8(0x0C) -#define PINE7 7 -#define PINE6 6 -#define PINE5 5 -#define PINE4 4 -#define PINE3 3 -#define PINE2 2 -#define PINE1 1 -#define PINE0 0 - -#define DDRE _SFR_IO8(0x0D) -#define DDRE7 7 -// Inserted "DDE7" from "DDRE7" due to compatibility -#define DDE7 7 -#define DDRE6 6 -// Inserted "DDE6" from "DDRE6" due to compatibility -#define DDE6 6 -#define DDRE5 5 -// Inserted "DDE5" from "DDRE5" due to compatibility -#define DDE5 5 -#define DDRE4 4 -// Inserted "DDE4" from "DDRE4" due to compatibility -#define DDE4 4 -#define DDRE3 3 -// Inserted "DDE3" from "DDRE3" due to compatibility -#define DDE3 3 -#define DDRE2 2 -// Inserted "DDE2" from "DDRE2" due to compatibility -#define DDE2 2 -#define DDRE1 1 -// Inserted "DDE1" from "DDRE1" due to compatibility -#define DDE1 1 -#define DDRE0 0 -// Inserted "DDE0" from "DDRE0" due to compatibility -#define DDE0 0 - -#define PORTE _SFR_IO8(0x0E) -#define PORTE7 7 -#define PORTE6 6 -#define PORTE5 5 -#define PORTE4 4 -#define PORTE3 3 -#define PORTE2 2 -#define PORTE1 1 -#define PORTE0 0 - -#define PINF _SFR_IO8(0x0F) -#define PINF7 7 -#define PINF6 6 -#define PINF5 5 -#define PINF4 4 -#define PINF3 3 -#define PINF2 2 -#define PINF1 1 -#define PINF0 0 - -#define DDRF _SFR_IO8(0x10) -#define DDRF7 7 -// Inserted "DDF7" from "DDRF7" due to compatibility -#define DDF7 7 -#define DDRF6 6 -// Inserted "DDF6" from "DDRF6" due to compatibility -#define DDF6 6 -#define DDRF5 5 -// Inserted "DDF5" from "DDRF5" due to compatibility -#define DDF5 5 -#define DDRF4 4 -// Inserted "DDF4" from "DDRF4" due to compatibility -#define DDF4 4 -#define DDRF3 3 -// Inserted "DDF3" from "DDRF3" due to compatibility -#define DDF3 3 -#define DDRF2 2 -// Inserted "DDF2" from "DDRF2" due to compatibility -#define DDF2 2 -#define DDRF1 1 -// Inserted "DDF1" from "DDRF1" due to compatibility -#define DDF1 1 -#define DDRF0 0 -// Inserted "DDF0" from "DDRF0" due to compatibility -#define DDF0 0 - -#define PORTF _SFR_IO8(0x11) -#define PORTF7 7 -#define PORTF6 6 -#define PORTF5 5 -#define PORTF4 4 -#define PORTF3 3 -#define PORTF2 2 -#define PORTF1 1 -#define PORTF0 0 - -#define PING _SFR_IO8(0x12) -#define PING7 7 -#define PING6 6 -#define PING5 5 -#define PING4 4 -#define PING3 3 -#define PING2 2 -#define PING1 1 -#define PING0 0 - -#define DDRG _SFR_IO8(0x13) -#define DDRG7 7 -// Inserted "DDG7" from "DDRG7" due to compatibility -#define DDG7 7 -#define DDRG6 6 -// Inserted "DDG6" from "DDRG6" due to compatibility -#define DDG6 6 -#define DDRG5 5 -// Inserted "DDG5" from "DDRG5" due to compatibility -#define DDG5 5 -#define DDRG4 4 -// Inserted "DDG4" from "DDRG4" due to compatibility -#define DDG4 4 -#define DDRG3 3 -// Inserted "DDG3" from "DDRG3" due to compatibility -#define DDG3 3 -#define DDRG2 2 -// Inserted "DDG2" from "DDRG2" due to compatibility -#define DDG2 2 -#define DDRG1 1 -// Inserted "DDG1" from "DDRG1" due to compatibility -#define DDG1 1 -#define DDRG0 0 -// Inserted "DDG0" from "DDRG0" due to compatibility -#define DDG0 0 - -#define PORTG _SFR_IO8(0x14) -#define PORTG7 7 -#define PORTG6 6 -#define PORTG5 5 -#define PORTG4 4 -#define PORTG3 3 -#define PORTG2 2 -#define PORTG1 1 -#define PORTG0 0 - -#define TIFR0 _SFR_IO8(0x15) -#define TOV0 0 -#define OCF0A 1 -#define OCF0B 2 -#define Res0 3 -#define Res1 4 -#define Res2 5 -#define Res3 6 -#define Res4 7 - -#define TIFR1 _SFR_IO8(0x16) -#define TOV1 0 -#define OCF1A 1 -#define OCF1B 2 -#define OCF1C 3 -#define ICF1 5 - -#define TIFR2 _SFR_IO8(0x17) -#define TOV2 0 -#define OCF2A 1 -#define OCF2B 2 - -#define TIFR3 _SFR_IO8(0x18) -#define TOV3 0 -#define OCF3A 1 -#define OCF3B 2 -#define OCF3C 3 -#define ICF3 5 - -#define TIFR4 _SFR_IO8(0x19) -#define TOV4 0 -#define OCF4A 1 -#define OCF4B 2 -#define OCF4C 3 -#define ICF4 5 - -#define TIFR5 _SFR_IO8(0x1A) -#define TOV5 0 -#define OCF5A 1 -#define OCF5B 2 -#define OCF5C 3 -#define ICF5 5 - -#define PCIFR _SFR_IO8(0x1B) -#define PCIF0 0 -#define PCIF1 1 -#define PCIF2 2 - -#define EIFR _SFR_IO8(0x1C) -#define INTF0 0 -#define INTF1 1 -#define INTF2 2 -#define INTF3 3 -#define INTF4 4 -#define INTF5 5 -#define INTF6 6 -#define INTF7 7 - -#define EIMSK _SFR_IO8(0x1D) -#define INT0 0 -#define INT1 1 -#define INT2 2 -#define INT3 3 -#define INT4 4 -#define INT5 5 -#define INT6 6 -#define INT7 7 - -#define GPIOR0 _SFR_IO8(0x1E) -#define GPIOR00 0 -#define GPIOR01 1 -#define GPIOR02 2 -#define GPIOR03 3 -#define GPIOR04 4 -#define GPIOR05 5 -#define GPIOR06 6 -#define GPIOR07 7 - -#define EECR _SFR_IO8(0x1F) -#define EERE 0 -#define EEPE 1 -#define EEMPE 2 -#define EERIE 3 -#define EEPM0 4 -#define EEPM1 5 - -#define EEDR _SFR_IO8(0x20) - -/* Combine EEARL and EEARH */ -#define EEAR _SFR_IO16(0x21) - -#define EEARL _SFR_IO8(0x21) -#define EEARH _SFR_IO8(0x22) - -#define GTCCR _SFR_IO8(0x23) -#define PSRSYNC 0 -#define PSRASY 1 -#define TSM 7 - -#define TCCR0A _SFR_IO8(0x24) -#define WGM00 0 -#define WGM01 1 -#define COM0B0 4 -#define COM0B1 5 -#define COM0A0 6 -#define COM0A1 7 - -#define TCCR0B _SFR_IO8(0x25) -#define CS00 0 -#define CS01 1 -#define CS02 2 -#define WGM02 3 -#define FOC0B 6 -#define FOC0A 7 - -#define TCNT0 _SFR_IO8(0x26) - -#define OCR0A _SFR_IO8(0x27) - -#define OCR0B _SFR_IO8(0x28) - -/* Reserved [0x29] */ - -#define GPIOR1 _SFR_IO8(0x2A) -#define GPIOR10 0 -#define GPIOR11 1 -#define GPIOR12 2 -#define GPIOR13 3 -#define GPIOR14 4 -#define GPIOR15 5 -#define GPIOR16 6 -#define GPIOR17 7 - -#define GPIOR2 _SFR_IO8(0x2B) -#define GPIOR20 0 -#define GPIOR21 1 -#define GPIOR22 2 -#define GPIOR23 3 -#define GPIOR24 4 -#define GPIOR25 5 -#define GPIOR26 6 -#define GPIOR27 7 - -#define SPCR _SFR_IO8(0x2C) -#define SPR0 0 -#define SPR1 1 -#define CPHA 2 -#define CPOL 3 -#define MSTR 4 -#define DORD 5 -#define SPE 6 -#define SPIE 7 - -#define SPSR _SFR_IO8(0x2D) -#define SPI2X 0 -#define WCOL 6 -#define SPIF 7 - -#define SPDR _SFR_IO8(0x2E) - -/* Reserved [0x2F] */ - -#define ACSR _SFR_IO8(0x30) -#define ACIS0 0 -#define ACIS1 1 -#define ACIC 2 -#define ACIE 3 -#define ACI 4 -#define ACO 5 -#define ACBG 6 -#define ACD 7 - -#define OCDR _SFR_IO8(0x31) -#define OCDR0 0 -#define OCDR1 1 -#define OCDR2 2 -#define OCDR3 3 -#define OCDR4 4 -#define OCDR5 5 -#define OCDR6 6 -#define OCDR7 7 - -/* Reserved [0x32] */ - -#define SMCR _SFR_IO8(0x33) -#define SE 0 -#define SM0 1 -#define SM1 2 -#define SM2 3 - -#define MCUSR _SFR_IO8(0x34) -#define JTRF 4 -#define PORF 0 -#define EXTRF 1 -#define BORF 2 -#define WDRF 3 - -#define MCUCR _SFR_IO8(0x35) -#define JTD 7 -#define IVCE 0 -#define IVSEL 1 -#define PUD 4 - -/* Reserved [0x36] */ - -#define SPMCSR _SFR_IO8(0x37) -#define SPMEN 0 -#define PGERS 1 -#define PGWRT 2 -#define BLBSET 3 -#define RWWSRE 4 -#define SIGRD 5 -#define RWWSB 6 -#define SPMIE 7 - -/* Reserved [0x38..0x3A] */ - -#define RAMPZ _SFR_IO8(0x3B) -#define RAMPZ0 0 -#define RAMPZ1 1 -#define Res5 7 - -#define EIND _SFR_IO8(0x3C) - -/* SP [0x3D..0x3E] */ - -/* SREG [0x3F] */ - -#define WDTCSR _SFR_MEM8(0x60) -#define WDE 3 -#define WDCE 4 -#define WDP0 0 -#define WDP1 1 -#define WDP2 2 -#define WDP3 5 -#define WDIE 6 -#define WDIF 7 - -#define CLKPR _SFR_MEM8(0x61) -#define CLKPS0 0 -#define CLKPS1 1 -#define CLKPS2 2 -#define CLKPS3 3 -#define CLKPCE 7 - -/* Reserved [0x62] */ - -#define PRR2 _SFR_MEM8(0x63) -#define PRRAM0 0 -#define PRRAM1 1 -#define PRRAM2 2 -#define PRRAM3 3 - -#define __AVR_HAVE_PRR2 ((1< instead of this file." -#endif - -#ifndef _AVR_IOXXX_H_ -# define _AVR_IOXXX_H_ "iom256rfr2.h" -#else -# error "Attempt to include more than one file." -#endif - -/* Registers and associated bit numbers */ - -#define PINA _SFR_IO8(0x00) -#define PINA7 7 -#define PINA6 6 -#define PINA5 5 -#define PINA4 4 -#define PINA3 3 -#define PINA2 2 -#define PINA1 1 -#define PINA0 0 - -#define DDRA _SFR_IO8(0x01) -#define DDRA7 7 -// Inserted "DDA7" from "DDRA7" due to compatibility -#define DDA7 7 -#define DDRA6 6 -// Inserted "DDA6" from "DDRA6" due to compatibility -#define DDA6 6 -#define DDRA5 5 -// Inserted "DDA5" from "DDRA5" due to compatibility -#define DDA5 5 -#define DDRA4 4 -// Inserted "DDA4" from "DDRA4" due to compatibility -#define DDA4 4 -#define DDRA3 3 -// Inserted "DDA3" from "DDRA3" due to compatibility -#define DDA3 3 -#define DDRA2 2 -// Inserted "DDA2" from "DDRA2" due to compatibility -#define DDA2 2 -#define DDRA1 1 -// Inserted "DDA1" from "DDRA1" due to compatibility -#define DDA1 1 -#define DDRA0 0 -// Inserted "DDA0" from "DDRA0" due to compatibility -#define DDA0 0 - -#define PORTA _SFR_IO8(0x02) -#define PORTA7 7 -#define PORTA6 6 -#define PORTA5 5 -#define PORTA4 4 -#define PORTA3 3 -#define PORTA2 2 -#define PORTA1 1 -#define PORTA0 0 - -#define PINB _SFR_IO8(0x03) -#define PINB7 7 -#define PINB6 6 -#define PINB5 5 -#define PINB4 4 -#define PINB3 3 -#define PINB2 2 -#define PINB1 1 -#define PINB0 0 - -#define DDRB _SFR_IO8(0x04) -#define DDRB7 7 -// Inserted "DDB7" from "DDRB7" due to compatibility -#define DDB7 7 -#define DDRB6 6 -// Inserted "DDB6" from "DDRB6" due to compatibility -#define DDB6 6 -#define DDRB5 5 -// Inserted "DDB5" from "DDRB5" due to compatibility -#define DDB5 5 -#define DDRB4 4 -// Inserted "DDB4" from "DDRB4" due to compatibility -#define DDB4 4 -#define DDRB3 3 -// Inserted "DDB3" from "DDRB3" due to compatibility -#define DDB3 3 -#define DDRB2 2 -// Inserted "DDB2" from "DDRB2" due to compatibility -#define DDB2 2 -#define DDRB1 1 -// Inserted "DDB1" from "DDRB1" due to compatibility -#define DDB1 1 -#define DDRB0 0 -// Inserted "DDB0" from "DDRB0" due to compatibility -#define DDB0 0 - -#define PORTB _SFR_IO8(0x05) -#define PORTB7 7 -#define PORTB6 6 -#define PORTB5 5 -#define PORTB4 4 -#define PORTB3 3 -#define PORTB2 2 -#define PORTB1 1 -#define PORTB0 0 - -#define PINC _SFR_IO8(0x06) -#define PINC7 7 -#define PINC6 6 -#define PINC5 5 -#define PINC4 4 -#define PINC3 3 -#define PINC2 2 -#define PINC1 1 -#define PINC0 0 - -#define DDRC _SFR_IO8(0x07) -#define DDRC7 7 -// Inserted "DDC7" from "DDRC7" due to compatibility -#define DDC7 7 -#define DDRC6 6 -// Inserted "DDC6" from "DDRC6" due to compatibility -#define DDC6 6 -#define DDRC5 5 -// Inserted "DDC5" from "DDRC5" due to compatibility -#define DDC5 5 -#define DDRC4 4 -// Inserted "DDC4" from "DDRC4" due to compatibility -#define DDC4 4 -#define DDRC3 3 -// Inserted "DDC3" from "DDRC3" due to compatibility -#define DDC3 3 -#define DDRC2 2 -// Inserted "DDC2" from "DDRC2" due to compatibility -#define DDC2 2 -#define DDRC1 1 -// Inserted "DDC1" from "DDRC1" due to compatibility -#define DDC1 1 -#define DDRC0 0 -// Inserted "DDC0" from "DDRC0" due to compatibility -#define DDC0 0 - -#define PORTC _SFR_IO8(0x08) -#define PORTC7 7 -#define PORTC6 6 -#define PORTC5 5 -#define PORTC4 4 -#define PORTC3 3 -#define PORTC2 2 -#define PORTC1 1 -#define PORTC0 0 - -#define PIND _SFR_IO8(0x09) -#define PIND7 7 -#define PIND6 6 -#define PIND5 5 -#define PIND4 4 -#define PIND3 3 -#define PIND2 2 -#define PIND1 1 -#define PIND0 0 - -#define DDRD _SFR_IO8(0x0A) -#define DDRD7 7 -// Inserted "DDD7" from "DDRD7" due to compatibility -#define DDD7 7 -#define DDRD6 6 -// Inserted "DDD6" from "DDRD6" due to compatibility -#define DDD6 6 -#define DDRD5 5 -// Inserted "DDD5" from "DDRD5" due to compatibility -#define DDD5 5 -#define DDRD4 4 -// Inserted "DDD4" from "DDRD4" due to compatibility -#define DDD4 4 -#define DDRD3 3 -// Inserted "DDD3" from "DDRD3" due to compatibility -#define DDD3 3 -#define DDRD2 2 -// Inserted "DDD2" from "DDRD2" due to compatibility -#define DDD2 2 -#define DDRD1 1 -// Inserted "DDD1" from "DDRD1" due to compatibility -#define DDD1 1 -#define DDRD0 0 -// Inserted "DDD0" from "DDRD0" due to compatibility -#define DDD0 0 - -#define PORTD _SFR_IO8(0x0B) -#define PORTD7 7 -#define PORTD6 6 -#define PORTD5 5 -#define PORTD4 4 -#define PORTD3 3 -#define PORTD2 2 -#define PORTD1 1 -#define PORTD0 0 - -#define PINE _SFR_IO8(0x0C) -#define PINE7 7 -#define PINE6 6 -#define PINE5 5 -#define PINE4 4 -#define PINE3 3 -#define PINE2 2 -#define PINE1 1 -#define PINE0 0 - -#define DDRE _SFR_IO8(0x0D) -#define DDRE7 7 -// Inserted "DDE7" from "DDRE7" due to compatibility -#define DDE7 7 -#define DDRE6 6 -// Inserted "DDE6" from "DDRE6" due to compatibility -#define DDE6 6 -#define DDRE5 5 -// Inserted "DDE5" from "DDRE5" due to compatibility -#define DDE5 5 -#define DDRE4 4 -// Inserted "DDE4" from "DDRE4" due to compatibility -#define DDE4 4 -#define DDRE3 3 -// Inserted "DDE3" from "DDRE3" due to compatibility -#define DDE3 3 -#define DDRE2 2 -// Inserted "DDE2" from "DDRE2" due to compatibility -#define DDE2 2 -#define DDRE1 1 -// Inserted "DDE1" from "DDRE1" due to compatibility -#define DDE1 1 -#define DDRE0 0 -// Inserted "DDE0" from "DDRE0" due to compatibility -#define DDE0 0 - -#define PORTE _SFR_IO8(0x0E) -#define PORTE7 7 -#define PORTE6 6 -#define PORTE5 5 -#define PORTE4 4 -#define PORTE3 3 -#define PORTE2 2 -#define PORTE1 1 -#define PORTE0 0 - -#define PINF _SFR_IO8(0x0F) -#define PINF7 7 -#define PINF6 6 -#define PINF5 5 -#define PINF4 4 -#define PINF3 3 -#define PINF2 2 -#define PINF1 1 -#define PINF0 0 - -#define DDRF _SFR_IO8(0x10) -#define DDRF7 7 -// Inserted "DDF7" from "DDRF7" due to compatibility -#define DDF7 7 -#define DDRF6 6 -// Inserted "DDF6" from "DDRF6" due to compatibility -#define DDF6 6 -#define DDRF5 5 -// Inserted "DDF5" from "DDRF5" due to compatibility -#define DDF5 5 -#define DDRF4 4 -// Inserted "DDF4" from "DDRF4" due to compatibility -#define DDF4 4 -#define DDRF3 3 -// Inserted "DDF3" from "DDRF3" due to compatibility -#define DDF3 3 -#define DDRF2 2 -// Inserted "DDF2" from "DDRF2" due to compatibility -#define DDF2 2 -#define DDRF1 1 -// Inserted "DDF1" from "DDRF1" due to compatibility -#define DDF1 1 -#define DDRF0 0 -// Inserted "DDF0" from "DDRF0" due to compatibility -#define DDF0 0 - -#define PORTF _SFR_IO8(0x11) -#define PORTF7 7 -#define PORTF6 6 -#define PORTF5 5 -#define PORTF4 4 -#define PORTF3 3 -#define PORTF2 2 -#define PORTF1 1 -#define PORTF0 0 - -#define PING _SFR_IO8(0x12) -#define PING7 7 -#define PING6 6 -#define PING5 5 -#define PING4 4 -#define PING3 3 -#define PING2 2 -#define PING1 1 -#define PING0 0 - -#define DDRG _SFR_IO8(0x13) -#define DDRG7 7 -// Inserted "DDG7" from "DDRG7" due to compatibility -#define DDG7 7 -#define DDRG6 6 -// Inserted "DDG6" from "DDRG6" due to compatibility -#define DDG6 6 -#define DDRG5 5 -// Inserted "DDG5" from "DDRG5" due to compatibility -#define DDG5 5 -#define DDRG4 4 -// Inserted "DDG4" from "DDRG4" due to compatibility -#define DDG4 4 -#define DDRG3 3 -// Inserted "DDG3" from "DDRG3" due to compatibility -#define DDG3 3 -#define DDRG2 2 -// Inserted "DDG2" from "DDRG2" due to compatibility -#define DDG2 2 -#define DDRG1 1 -// Inserted "DDG1" from "DDRG1" due to compatibility -#define DDG1 1 -#define DDRG0 0 -// Inserted "DDG0" from "DDRG0" due to compatibility -#define DDG0 0 - -#define PORTG _SFR_IO8(0x14) -#define PORTG7 7 -#define PORTG6 6 -#define PORTG5 5 -#define PORTG4 4 -#define PORTG3 3 -#define PORTG2 2 -#define PORTG1 1 -#define PORTG0 0 - -#define TIFR0 _SFR_IO8(0x15) -#define TOV0 0 -#define OCF0A 1 -#define OCF0B 2 -#define Res0 3 -#define Res1 4 -#define Res2 5 -#define Res3 6 -#define Res4 7 - -#define TIFR1 _SFR_IO8(0x16) -#define TOV1 0 -#define OCF1A 1 -#define OCF1B 2 -#define OCF1C 3 -#define ICF1 5 - -#define TIFR2 _SFR_IO8(0x17) -#define TOV2 0 -#define OCF2A 1 -#define OCF2B 2 - -#define TIFR3 _SFR_IO8(0x18) -#define TOV3 0 -#define OCF3A 1 -#define OCF3B 2 -#define OCF3C 3 -#define ICF3 5 - -#define TIFR4 _SFR_IO8(0x19) -#define TOV4 0 -#define OCF4A 1 -#define OCF4B 2 -#define OCF4C 3 -#define ICF4 5 - -#define TIFR5 _SFR_IO8(0x1A) -#define TOV5 0 -#define OCF5A 1 -#define OCF5B 2 -#define OCF5C 3 -#define ICF5 5 - -#define PCIFR _SFR_IO8(0x1B) -#define PCIF0 0 -#define PCIF1 1 -#define PCIF2 2 - -#define EIFR _SFR_IO8(0x1C) -#define INTF0 0 -#define INTF1 1 -#define INTF2 2 -#define INTF3 3 -#define INTF4 4 -#define INTF5 5 -#define INTF6 6 -#define INTF7 7 - -#define EIMSK _SFR_IO8(0x1D) -#define INT0 0 -#define INT1 1 -#define INT2 2 -#define INT3 3 -#define INT4 4 -#define INT5 5 -#define INT6 6 -#define INT7 7 - -#define GPIOR0 _SFR_IO8(0x1E) -#define GPIOR00 0 -#define GPIOR01 1 -#define GPIOR02 2 -#define GPIOR03 3 -#define GPIOR04 4 -#define GPIOR05 5 -#define GPIOR06 6 -#define GPIOR07 7 - -#define EECR _SFR_IO8(0x1F) -#define EERE 0 -#define EEPE 1 -#define EEMPE 2 -#define EERIE 3 -#define EEPM0 4 -#define EEPM1 5 - -#define EEDR _SFR_IO8(0x20) - -/* Combine EEARL and EEARH */ -#define EEAR _SFR_IO16(0x21) - -#define EEARL _SFR_IO8(0x21) -#define EEARH _SFR_IO8(0x22) - -#define GTCCR _SFR_IO8(0x23) -#define PSRSYNC 0 -#define PSRASY 1 -#define TSM 7 - -#define TCCR0A _SFR_IO8(0x24) -#define WGM00 0 -#define WGM01 1 -#define COM0B0 4 -#define COM0B1 5 -#define COM0A0 6 -#define COM0A1 7 - -#define TCCR0B _SFR_IO8(0x25) -#define CS00 0 -#define CS01 1 -#define CS02 2 -#define WGM02 3 -#define FOC0B 6 -#define FOC0A 7 - -#define TCNT0 _SFR_IO8(0x26) - -#define OCR0A _SFR_IO8(0x27) - -#define OCR0B _SFR_IO8(0x28) - -/* Reserved [0x29] */ - -#define GPIOR1 _SFR_IO8(0x2A) -#define GPIOR10 0 -#define GPIOR11 1 -#define GPIOR12 2 -#define GPIOR13 3 -#define GPIOR14 4 -#define GPIOR15 5 -#define GPIOR16 6 -#define GPIOR17 7 - -#define GPIOR2 _SFR_IO8(0x2B) -#define GPIOR20 0 -#define GPIOR21 1 -#define GPIOR22 2 -#define GPIOR23 3 -#define GPIOR24 4 -#define GPIOR25 5 -#define GPIOR26 6 -#define GPIOR27 7 - -#define SPCR _SFR_IO8(0x2C) -#define SPR0 0 -#define SPR1 1 -#define CPHA 2 -#define CPOL 3 -#define MSTR 4 -#define DORD 5 -#define SPE 6 -#define SPIE 7 - -#define SPSR _SFR_IO8(0x2D) -#define SPI2X 0 -#define WCOL 6 -#define SPIF 7 - -#define SPDR _SFR_IO8(0x2E) - -/* Reserved [0x2F] */ - -#define ACSR _SFR_IO8(0x30) -#define ACIS0 0 -#define ACIS1 1 -#define ACIC 2 -#define ACIE 3 -#define ACI 4 -#define ACO 5 -#define ACBG 6 -#define ACD 7 - -#define OCDR _SFR_IO8(0x31) -#define OCDR0 0 -#define OCDR1 1 -#define OCDR2 2 -#define OCDR3 3 -#define OCDR4 4 -#define OCDR5 5 -#define OCDR6 6 -#define OCDR7 7 - -/* Reserved [0x32] */ - -#define SMCR _SFR_IO8(0x33) -#define SE 0 -#define SM0 1 -#define SM1 2 -#define SM2 3 - -#define MCUSR _SFR_IO8(0x34) -#define JTRF 4 -#define PORF 0 -#define EXTRF 1 -#define BORF 2 -#define WDRF 3 - -#define MCUCR _SFR_IO8(0x35) -#define JTD 7 -#define IVCE 0 -#define IVSEL 1 -#define PUD 4 - -/* Reserved [0x36] */ - -#define SPMCSR _SFR_IO8(0x37) -#define SPMEN 0 -#define PGERS 1 -#define PGWRT 2 -#define BLBSET 3 -#define RWWSRE 4 -#define SIGRD 5 -#define RWWSB 6 -#define SPMIE 7 - -/* Reserved [0x38..0x3A] */ - -#define RAMPZ _SFR_IO8(0x3B) -#define RAMPZ0 0 -#define RAMPZ1 1 -#define Res5 7 - -#define EIND _SFR_IO8(0x3C) - -/* SP [0x3D..0x3E] */ - -/* SREG [0x3F] */ - -#define WDTCSR _SFR_MEM8(0x60) -#define WDE 3 -#define WDCE 4 -#define WDP0 0 -#define WDP1 1 -#define WDP2 2 -#define WDP3 5 -#define WDIE 6 -#define WDIF 7 - -#define CLKPR _SFR_MEM8(0x61) -#define CLKPS0 0 -#define CLKPS1 1 -#define CLKPS2 2 -#define CLKPS3 3 -#define CLKPCE 7 - -/* Reserved [0x62] */ - -#define PRR2 _SFR_MEM8(0x63) -#define PRRAM0 0 -#define PRRAM1 1 -#define PRRAM2 2 -#define PRRAM3 3 - -#define __AVR_HAVE_PRR2 ((1<, never directly. */ - -#ifndef _AVR_IO_H_ -# error "Include instead of this file." -#endif - -#ifndef _AVR_IOXXX_H_ -# define _AVR_IOXXX_H_ "iom3000.h" -#else -# error "Attempt to include more than one file." -#endif - - -#ifndef _AVR_IOM3000_H_ -#define _AVR_IOM3000_H_ 1 - -/* Registers and associated bit numbers */ - -#define IPD _SFR_IO16(0x00) -#define IPDL _SFR_IO8(0x00) -#define IPDH _SFR_IO8(0x01) -#define IPA _SFR_IO16(0x02) -#define IPAL _SFR_IO8(0x02) -#define IPAH _SFR_IO8(0x03) -#define IPCR _SFR_IO8(0x04) -#define ADRSLT _SFR_IO16(0x05) -#define ADRSLTL _SFR_IO8(0x05) /* Alias. */ -#define ADRSLTH _SFR_IO8(0x06) /* Alias. */ -#define ADRSLTLO _SFR_IO8(0x05) /* Name according to datasheet. */ -#define ADRSLTHI _SFR_IO8(0x06) /* Name according to datasheet. */ -#define ADCSR _SFR_IO8(0x07) -#define AMUXCTL _SFR_IO8(0x0B) -#define MSPCR _SFR_IO8(0x0C) -#define USPCR _SFR_IO8(0x0C) -#define MSPSR _SFR_IO8(0x0D) -#define USPSR _SFR_IO8(0x0D) -#define MSPDR _SFR_IO8(0x0E) -#define USPDR _SFR_IO8(0x0E) -#define WDTCR _SFR_IO8(0x0F) -#define USR _SFR_IO8(0x11) -#define UCRA _SFR_IO8(0x12) -#define UCRB _SFR_IO8(0x13) -#define UBRR _SFR_IO8(0x14) -#define UBRRL _SFR_IO8(0x14) /* Alias. */ -#define UBRRH _SFR_IO8(0x15) /* Alias. */ -#define UBRRLO _SFR_IO8(0x14) /* Name according to datasheet. */ -#define UBRRHI _SFR_IO8(0x15) /* Name according to datasheet. */ -#define GIFR _SFR_IO8(0x16) -#define GIMSK _SFR_IO8(0x17) -#define DACVAL _SFR_IO16(0x18) -#define DACVALL _SFR_IO8(0x18) /* Alias. */ -#define DACVALH _SFR_IO8(0x19) /* Alias. */ -#define DACVALLO _SFR_IO8(0x18) /* Name according to datasheet. */ -#define DACVALHI _SFR_IO8(0x19) /* Name according to datasheet. */ -#define BGPPIN _SFR_IO8(0x1A) -#define BGPDDR _SFR_IO8(0x1B) -#define BGPPORT _SFR_IO8(0x1C) -#define AGPPIN _SFR_IO8(0x1D) -#define AGPDDR _SFR_IO8(0x1E) -#define AGPPORT _SFR_IO8(0x1F) -#define EXTCCR1A _SFR_IO8(0x20) -#define EXTCCR1B _SFR_IO8(0x21) -#define EXTCNT1 _SFR_IO16(0x22) -#define EXTCNT1L _SFR_IO8(0x22) -#define EXTCNT1H _SFR_IO8(0x23) -#define EXOCR1A _SFR_IO16(0x24) -#define EXOCR1AL _SFR_IO8(0x24) -#define EXOCR1AH _SFR_IO8(0x25) -#define EXOCR1B _SFR_IO16(0x26) -#define EXOCR1BL _SFR_IO8(0x26) -#define EXOCR1BH _SFR_IO8(0x27) -#define EXTIFR _SFR_IO8(0x2A) -#define EXTIMSK _SFR_IO8(0x2B) -#define EXTCNT _SFR_IO8(0x2C) -#define EXTCCR0 _SFR_IO8(0x2D) -#define CGPPIN _SFR_IO8(0x30) -#define CGPDDR _SFR_IO8(0x31) -#define CGPPORT _SFR_IO8(0x32) -#define MCSR _SFR_IO8(0x33) - - -#define CDIVCAN _SFR_MEM8(0x100) -#define CBTR1 _SFR_MEM8(0x101) -#define CBTR2 _SFR_MEM8(0x102) -#define CBTR3 _SFR_MEM8(0x103) -#define CMCR _SFR_MEM8(0x104) -#define CRAFEN _SFR_MEM8(0x105) -#define CTARR _SFR_MEM8(0x106) -#define CIER _SFR_MEM8(0x107) -#define CCFLG _SFR_MEM8(0x108) -#define CCISR _SFR_MEM8(0x109) -#define CIDAH0 _SFR_MEM8(0x10A) -#define CIDAH1 _SFR_MEM8(0x10B) -#define CEFR _SFR_MEM8(0x10C) -#define CRXERR _SFR_MEM8(0x10D) -#define CTXERR _SFR_MEM8(0x10E) -#define CVER _SFR_MEM8(0x10F) -#define CIDAC0R _SFR_MEM32(0x110) -#define CIDM0R _SFR_MEM32(0x114) -#define CIDAC1R _SFR_MEM32(0x118) -#define CIDM1R _SFR_MEM32(0x11C) -#define CIDAC2R _SFR_MEM32(0x120) -#define CIDM2R _SFR_MEM32(0x124) -#define CIDAC3R _SFR_MEM32(0x128) -#define CIDM3R _SFR_MEM32(0x12C) -#define CIDAC4R _SFR_MEM32(0x130) -#define CIDM4R _SFR_MEM32(0x134) -#define CIDAC5R _SFR_MEM32(0x138) -#define CIDM5R _SFR_MEM32(0x13C) -#define CIDAC6R _SFR_MEM32(0x140) -#define CIDM6R _SFR_MEM32(0x144) -#define CTXB0 ((volatile uint8_t [16])(0x150)) -#define CTXB1 ((volatile uint8_t [16])(0x160)) -#define CTXB2 ((volatile uint8_t [16])(0x170)) -#define CRXB0 ((volatile uint8_t [16])(0x180)) -#define CRXB1 ((volatile uint8_t [16])(0x190)) -#define PWMMSK _SFR_MEM8(0x200) -#define PWMPER _SFR_MEM8(0x201) -#define PWMSFRQ _SFR_MEM8(0x202) -#define PWMCTL _SFR_MEM8(0x203) -#define CURIRUN _SFR_MEM8(0x204) -#define CURIRED _SFR_MEM8(0x205) -#define CURRDLY _SFR_MEM16(0x206) -#define VELLOW1 _SFR_MEM8(0x208) -#define VELLOW2 _SFR_MEM8(0x209) -#define VELLOW3 _SFR_MEM8(0x20A) -#define VELHI1 _SFR_MEM8(0x20B) -#define VELHI2 _SFR_MEM8(0x20C) -#define VELHI3 _SFR_MEM8(0x20D) -#define VELDEC1 _SFR_MEM8(0x20E) -#define VELDEC2 _SFR_MEM8(0x20F) -#define VELDEC3 _SFR_MEM8(0x210) -#define VELACC1 _SFR_MEM8(0x211) -#define VELACC2 _SFR_MEM8(0x212) -#define VELACC3 _SFR_MEM8(0x213) -#define VELCVEL _SFR_MEM8(0x214) -/* -#define VELCVEL _SFR_MEM8(0x215) -#define VELCVEL _SFR_MEM8(0x216) -*/ -#define VELTVEL _SFR_MEM8(0x217) -/* -#define VELTVEL _SFR_MEM8(0x218) -#define VELTVEL _SFR_MEM8(0x219) -*/ -#define VELVGCTL _SFR_MEM8(0x21A) -#define VELSTB _SFR_MEM8(0x21B) -#define VELIFLG _SFR_MEM8(0x21C) -#define VELIMSK _SFR_MEM8(0x21D) -#define IDXTRT _SFR_MEM32(0x21E) -#define IDXENT _SFR_MEM32(0x222) -#define IDXMSDT _SFR_MEM16(0x226) -#define IDXPOT _SFR_MEM32(0x228) -#define IDXPOS _SFR_MEM32(0x22C) -#define IDXENC _SFR_MEM32(0x230) -#define IDXCTRL _SFR_MEM8(0x234) -#define IDXSTRB _SFR_MEM8(0x235) -#define IDXCPTP _SFR_MEM32(0x236) -#define IDXIFLG _SFR_MEM8(0x23A) -#define IDXIMSK _SFR_MEM8(0x23B) -#define SCIO _SFR_MEM8(0x23C) -#define SCSW _SFR_MEM8(0x23D) -#define SCRF _SFR_MEM32(0x23E) -#define IOF _SFR_MEM8(0x242) -#define MSELR _SFR_MEM8(0x243) -#define STAT _SFR_MEM8(0x244) -#define SPWMCTL _SFR_MEM8(0x245) -#define SINDAC _SFR_MEM16(0x280) -#define SINDACL _SFR_MEM8(0x280) -#define SINDACH _SFR_MEM8(0x281) -#define COSDAC _SFR_MEM8(0x282) -#define COSDACL _SFR_MEM8(0x282) -#define COSDACH _SFR_MEM8(0x283) -#define GAINDAC _SFR_MEM8(0x284) -#define DACCTRL _SFR_MEM8(0x285) -#define INTCCR1A _SFR_MEM8(0x800) -#define INTCCR1B _SFR_MEM8(0x801) -#define INTCNT1 _SFR_MEM16(0x802) -#define INTCNT1L _SFR_MEM8(0x802) -#define INTCNT1H _SFR_MEM8(0x803) -#define INOCR1A _SFR_MEM16(0x804) -#define INOCR1AL _SFR_MEM8(0x804) -#define INOCR1AH _SFR_MEM8(0x805) -#define INOCR1B _SFR_MEM16(0x806) /* Data sheet says 0x807-0x808, but I believe this is wrong due to conflict with INTCNT. */ -#define INOCR1BL _SFR_MEM8(0x806) -#define INOCR1BH _SFR_MEM8(0x807) -#define INTCNT _SFR_MEM8(0x808) -#define INTCCR0 _SFR_MEM8(0x809) -#define INTIFR _SFR_MEM8(0x80A) -#define INTIMSK _SFR_MEM8(0x80B) - - -/* Constants */ -#define RAMSTART 0x1000 -#define RAMEND 0x1FFF /* Last On-Chip SRAM Location */ -#define E2END 0x0 -#define E2PAGESIZE 0 -#define FLASHEND 0xFFFF -#define _VECTORS_SIZE 0 - - -#endif /* _AVR_IOM3000_H_ */ - diff --git a/arduino/hardware/tools/avr/avr/include/avr/iom32.h b/arduino/hardware/tools/avr/avr/include/avr/iom32.h deleted file mode 100644 index 11b9d4e..0000000 --- a/arduino/hardware/tools/avr/avr/include/avr/iom32.h +++ /dev/null @@ -1,755 +0,0 @@ -/* Copyright (c) 2002, Steinar Haugen - All rights reserved. - - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - * Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - * Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in - the documentation and/or other materials provided with the - distribution. - - * Neither the name of the copyright holders nor the names of - contributors may be used to endorse or promote products derived - from this software without specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. */ - -/* $Id: iom32.h 2233 2011-03-15 15:49:50Z arcanum $ */ - -/* avr/iom32.h - definitions for ATmega32 */ - -#ifndef _AVR_IOM32_H_ -#define _AVR_IOM32_H_ 1 - -/* This file should only be included from , never directly. */ - -#ifndef _AVR_IO_H_ -# error "Include instead of this file." -#endif - -#ifndef _AVR_IOXXX_H_ -# define _AVR_IOXXX_H_ "iom32.h" -#else -# error "Attempt to include more than one file." -#endif - -/* I/O registers */ - -/* TWI stands for "Two Wire Interface" or "TWI Was I2C(tm)" */ -#define TWBR _SFR_IO8(0x00) -#define TWSR _SFR_IO8(0x01) -#define TWAR _SFR_IO8(0x02) -#define TWDR _SFR_IO8(0x03) - -/* ADC */ -#ifndef __ASSEMBLER__ -#define ADC _SFR_IO16(0x04) -#endif -#define ADCW _SFR_IO16(0x04) -#define ADCL _SFR_IO8(0x04) -#define ADCH _SFR_IO8(0x05) -#define ADCSRA _SFR_IO8(0x06) -#define ADMUX _SFR_IO8(0x07) - -/* analog comparator */ -#define ACSR _SFR_IO8(0x08) - -/* USART */ -#define UBRRL _SFR_IO8(0x09) -#define UCSRB _SFR_IO8(0x0A) -#define UCSRA _SFR_IO8(0x0B) -#define UDR _SFR_IO8(0x0C) - -/* SPI */ -#define SPCR _SFR_IO8(0x0D) -#define SPSR _SFR_IO8(0x0E) -#define SPDR _SFR_IO8(0x0F) - -/* Port D */ -#define PIND _SFR_IO8(0x10) -#define DDRD _SFR_IO8(0x11) -#define PORTD _SFR_IO8(0x12) - -/* Port C */ -#define PINC _SFR_IO8(0x13) -#define DDRC _SFR_IO8(0x14) -#define PORTC _SFR_IO8(0x15) - -/* Port B */ -#define PINB _SFR_IO8(0x16) -#define DDRB _SFR_IO8(0x17) -#define PORTB _SFR_IO8(0x18) - -/* Port A */ -#define PINA _SFR_IO8(0x19) -#define DDRA _SFR_IO8(0x1A) -#define PORTA _SFR_IO8(0x1B) - -/* EEPROM Control Register */ -#define EECR _SFR_IO8(0x1C) - -/* EEPROM Data Register */ -#define EEDR _SFR_IO8(0x1D) - -/* EEPROM Address Register */ -#define EEAR _SFR_IO16(0x1E) -#define EEARL _SFR_IO8(0x1E) -#define EEARH _SFR_IO8(0x1F) - -#define UBRRH _SFR_IO8(0x20) -#define UCSRC UBRRH - -#define WDTCR _SFR_IO8(0x21) - -#define ASSR _SFR_IO8(0x22) - -/* Timer 2 */ -#define OCR2 _SFR_IO8(0x23) -#define TCNT2 _SFR_IO8(0x24) -#define TCCR2 _SFR_IO8(0x25) - -/* Timer 1 */ -#define ICR1 _SFR_IO16(0x26) -#define ICR1L _SFR_IO8(0x26) -#define ICR1H _SFR_IO8(0x27) -#define OCR1B _SFR_IO16(0x28) -#define OCR1BL _SFR_IO8(0x28) -#define OCR1BH _SFR_IO8(0x29) -#define OCR1A _SFR_IO16(0x2A) -#define OCR1AL _SFR_IO8(0x2A) -#define OCR1AH _SFR_IO8(0x2B) -#define TCNT1 _SFR_IO16(0x2C) -#define TCNT1L _SFR_IO8(0x2C) -#define TCNT1H _SFR_IO8(0x2D) -#define TCCR1B _SFR_IO8(0x2E) -#define TCCR1A _SFR_IO8(0x2F) - -#define SFIOR _SFR_IO8(0x30) - -#define OSCCAL _SFR_IO8(0x31) -#define OCDR OSCCAL - -/* Timer 0 */ -#define TCNT0 _SFR_IO8(0x32) -#define TCCR0 _SFR_IO8(0x33) - -#define MCUSR _SFR_IO8(0x34) -#define MCUCSR MCUSR -#define MCUCR _SFR_IO8(0x35) - -#define TWCR _SFR_IO8(0x36) - -#define SPMCR _SFR_IO8(0x37) - -#define TIFR _SFR_IO8(0x38) -#define TIMSK _SFR_IO8(0x39) - -#define GIFR _SFR_IO8(0x3A) -#define GIMSK _SFR_IO8(0x3B) -#define GICR GIMSK - -#define OCR0 _SFR_IO8(0x3C) - -/* 0x3D..0x3E SP */ - -/* 0x3F SREG */ - -/* Interrupt vectors */ - -/* External Interrupt Request 0 */ -#define INT0_vect_num 1 -#define INT0_vect _VECTOR(1) -#define SIG_INTERRUPT0 _VECTOR(1) - -/* External Interrupt Request 1 */ -#define INT1_vect_num 2 -#define INT1_vect _VECTOR(2) -#define SIG_INTERRUPT1 _VECTOR(2) - -/* External Interrupt Request 2 */ -#define INT2_vect_num 3 -#define INT2_vect _VECTOR(3) -#define SIG_INTERRUPT2 _VECTOR(3) - -/* Timer/Counter2 Compare Match */ -#define TIMER2_COMP_vect_num 4 -#define TIMER2_COMP_vect _VECTOR(4) -#define SIG_OUTPUT_COMPARE2 _VECTOR(4) - -/* Timer/Counter2 Overflow */ -#define TIMER2_OVF_vect_num 5 -#define TIMER2_OVF_vect _VECTOR(5) -#define SIG_OVERFLOW2 _VECTOR(5) - -/* Timer/Counter1 Capture Event */ -#define TIMER1_CAPT_vect_num 6 -#define TIMER1_CAPT_vect _VECTOR(6) -#define SIG_INPUT_CAPTURE1 _VECTOR(6) - -/* Timer/Counter1 Compare Match A */ -#define TIMER1_COMPA_vect_num 7 -#define TIMER1_COMPA_vect _VECTOR(7) -#define SIG_OUTPUT_COMPARE1A _VECTOR(7) - -/* Timer/Counter1 Compare Match B */ -#define TIMER1_COMPB_vect_num 8 -#define TIMER1_COMPB_vect _VECTOR(8) -#define SIG_OUTPUT_COMPARE1B _VECTOR(8) - -/* Timer/Counter1 Overflow */ -#define TIMER1_OVF_vect_num 9 -#define TIMER1_OVF_vect _VECTOR(9) -#define SIG_OVERFLOW1 _VECTOR(9) - -/* Timer/Counter0 Compare Match */ -#define TIMER0_COMP_vect_num 10 -#define TIMER0_COMP_vect _VECTOR(10) -#define SIG_OUTPUT_COMPARE0 _VECTOR(10) - -/* Timer/Counter0 Overflow */ -#define TIMER0_OVF_vect_num 11 -#define TIMER0_OVF_vect _VECTOR(11) -#define SIG_OVERFLOW0 _VECTOR(11) - -/* Serial Transfer Complete */ -#define SPI_STC_vect_num 12 -#define SPI_STC_vect _VECTOR(12) -#define SIG_SPI _VECTOR(12) - -/* USART, Rx Complete */ -#define USART_RXC_vect_num 13 -#define USART_RXC_vect _VECTOR(13) -#define SIG_USART_RECV _VECTOR(13) -#define SIG_UART_RECV _VECTOR(13) - -/* USART Data Register Empty */ -#define USART_UDRE_vect_num 14 -#define USART_UDRE_vect _VECTOR(14) -#define SIG_USART_DATA _VECTOR(14) -#define SIG_UART_DATA _VECTOR(14) - -/* USART, Tx Complete */ -#define USART_TXC_vect_num 15 -#define USART_TXC_vect _VECTOR(15) -#define SIG_USART_TRANS _VECTOR(15) -#define SIG_UART_TRANS _VECTOR(15) - -/* ADC Conversion Complete */ -#define ADC_vect_num 16 -#define ADC_vect _VECTOR(16) -#define SIG_ADC _VECTOR(16) - -/* EEPROM Ready */ -#define EE_RDY_vect_num 17 -#define EE_RDY_vect _VECTOR(17) -#define SIG_EEPROM_READY _VECTOR(17) - -/* Analog Comparator */ -#define ANA_COMP_vect_num 18 -#define ANA_COMP_vect _VECTOR(18) -#define SIG_COMPARATOR _VECTOR(18) - -/* 2-wire Serial Interface */ -#define TWI_vect_num 19 -#define TWI_vect _VECTOR(19) -#define SIG_2WIRE_SERIAL _VECTOR(19) - -/* Store Program Memory Ready */ -#define SPM_RDY_vect_num 20 -#define SPM_RDY_vect _VECTOR(20) -#define SIG_SPM_READY _VECTOR(20) - -#define _VECTORS_SIZE 84 - -/* Bit numbers */ - -/* GICR */ -#define INT1 7 -#define INT0 6 -#define INT2 5 -#define IVSEL 1 -#define IVCE 0 - -/* GIFR */ -#define INTF1 7 -#define INTF0 6 -#define INTF2 5 - -/* TIMSK */ -#define OCIE2 7 -#define TOIE2 6 -#define TICIE1 5 -#define OCIE1A 4 -#define OCIE1B 3 -#define TOIE1 2 -#define OCIE0 1 -#define TOIE0 0 - -/* TIFR */ -#define OCF2 7 -#define TOV2 6 -#define ICF1 5 -#define OCF1A 4 -#define OCF1B 3 -#define TOV1 2 -#define OCF0 1 -#define TOV0 0 - -/* SPMCR */ -#define SPMIE 7 -#define RWWSB 6 -/* bit 5 reserved */ -#define RWWSRE 4 -#define BLBSET 3 -#define PGWRT 2 -#define PGERS 1 -#define SPMEN 0 - -/* TWCR */ -#define TWINT 7 -#define TWEA 6 -#define TWSTA 5 -#define TWSTO 4 -#define TWWC 3 -#define TWEN 2 -/* bit 1 reserved */ -#define TWIE 0 - -/* TWAR */ -#define TWA6 7 -#define TWA5 6 -#define TWA4 5 -#define TWA3 4 -#define TWA2 3 -#define TWA1 2 -#define TWA0 1 -#define TWGCE 0 - -/* TWSR */ -#define TWS7 7 -#define TWS6 6 -#define TWS5 5 -#define TWS4 4 -#define TWS3 3 -/* bit 2 reserved */ -#define TWPS1 1 -#define TWPS0 0 - -/* MCUCR */ -#define SE 7 -#define SM2 6 -#define SM1 5 -#define SM0 4 -#define ISC11 3 -#define ISC10 2 -#define ISC01 1 -#define ISC00 0 - -/* MCUCSR */ -#define JTD 7 -#define ISC2 6 -/* bit 5 reserved */ -#define JTRF 4 -#define WDRF 3 -#define BORF 2 -#define EXTRF 1 -#define PORF 0 - -/* SFIOR */ -#define ADTS2 7 -#define ADTS1 6 -#define ADTS0 5 -/* bit 4 reserved */ -#define ACME 3 -#define PUD 2 -#define PSR2 1 -#define PSR10 0 - -/* TCCR0 */ -#define FOC0 7 -#define WGM00 6 -#define COM01 5 -#define COM00 4 -#define WGM01 3 -#define CS02 2 -#define CS01 1 -#define CS00 0 - -/* TCCR2 */ -#define FOC2 7 -#define WGM20 6 -#define COM21 5 -#define COM20 4 -#define WGM21 3 -#define CS22 2 -#define CS21 1 -#define CS20 0 - -/* ASSR */ -/* bits 7-4 reserved */ -#define AS2 3 -#define TCN2UB 2 -#define OCR2UB 1 -#define TCR2UB 0 - -/* TCCR1A */ -#define COM1A1 7 -#define COM1A0 6 -#define COM1B1 5 -#define COM1B0 4 -#define FOC1A 3 -#define FOC1B 2 -#define WGM11 1 -#define WGM10 0 - -/* TCCR1B */ -#define ICNC1 7 -#define ICES1 6 -/* bit 5 reserved */ -#define WGM13 4 -#define WGM12 3 -#define CS12 2 -#define CS11 1 -#define CS10 0 - -/* WDTCR */ -/* bits 7-5 reserved */ -#define WDTOE 4 -#define WDE 3 -#define WDP2 2 -#define WDP1 1 -#define WDP0 0 - -/* PA7-PA0 = ADC7-ADC0 */ -/* PORTA */ -#define PA7 7 -#define PA6 6 -#define PA5 5 -#define PA4 4 -#define PA3 3 -#define PA2 2 -#define PA1 1 -#define PA0 0 - -/* DDRA */ -#define DDA7 7 -#define DDA6 6 -#define DDA5 5 -#define DDA4 4 -#define DDA3 3 -#define DDA2 2 -#define DDA1 1 -#define DDA0 0 - -/* PINA */ -#define PINA7 7 -#define PINA6 6 -#define PINA5 5 -#define PINA4 4 -#define PINA3 3 -#define PINA2 2 -#define PINA1 1 -#define PINA0 0 - -/* - PB7 = SCK - PB6 = MISO - PB5 = MOSI - PB4 = SS# - PB3 = OC0/AIN1 - PB2 = INT2/AIN0 - PB1 = T1 - PB0 = XCK/T0 - */ - -/* PORTB */ -#define PB7 7 -#define PB6 6 -#define PB5 5 -#define PB4 4 -#define PB3 3 -#define PB2 2 -#define PB1 1 -#define PB0 0 - -/* DDRB */ -#define DDB7 7 -#define DDB6 6 -#define DDB5 5 -#define DDB4 4 -#define DDB3 3 -#define DDB2 2 -#define DDB1 1 -#define DDB0 0 - -/* PINB */ -#define PINB7 7 -#define PINB6 6 -#define PINB5 5 -#define PINB4 4 -#define PINB3 3 -#define PINB2 2 -#define PINB1 1 -#define PINB0 0 - -/* - PC7 = TOSC2 - PC6 = TOSC1 - PC1 = SDA - PC0 = SCL - */ -/* PORTC */ -#define PC7 7 -#define PC6 6 -#define PC5 5 -#define PC4 4 -#define PC3 3 -#define PC2 2 -#define PC1 1 -#define PC0 0 - -/* DDRC */ -#define DDC7 7 -#define DDC6 6 -#define DDC5 5 -#define DDC4 4 -#define DDC3 3 -#define DDC2 2 -#define DDC1 1 -#define DDC0 0 - -/* PINC */ -#define PINC7 7 -#define PINC6 6 -#define PINC5 5 -#define PINC4 4 -#define PINC3 3 -#define PINC2 2 -#define PINC1 1 -#define PINC0 0 - -/* - PD7 = OC2 - PD6 = ICP - PD5 = OC1A - PD4 = OC1B - PD3 = INT1 - PD2 = INT0 - PD1 = TXD - PD0 = RXD - */ - -/* PORTD */ -#define PD7 7 -#define PD6 6 -#define PD5 5 -#define PD4 4 -#define PD3 3 -#define PD2 2 -#define PD1 1 -#define PD0 0 - -/* DDRD */ -#define DDD7 7 -#define DDD6 6 -#define DDD5 5 -#define DDD4 4 -#define DDD3 3 -#define DDD2 2 -#define DDD1 1 -#define DDD0 0 - -/* PIND */ -#define PIND7 7 -#define PIND6 6 -#define PIND5 5 -#define PIND4 4 -#define PIND3 3 -#define PIND2 2 -#define PIND1 1 -#define PIND0 0 - -/* SPSR */ -#define SPIF 7 -#define WCOL 6 -/* bits 5-1 reserved */ -#define SPI2X 0 - -/* SPCR */ -#define SPIE 7 -#define SPE 6 -#define DORD 5 -#define MSTR 4 -#define CPOL 3 -#define CPHA 2 -#define SPR1 1 -#define SPR0 0 - -/* UCSRA */ -#define RXC 7 -#define TXC 6 -#define UDRE 5 -#define FE 4 -#define DOR 3 -#define PE 2 -#define U2X 1 -#define MPCM 0 - -/* UCSRB */ -#define RXCIE 7 -#define TXCIE 6 -#define UDRIE 5 -#define RXEN 4 -#define TXEN 3 -#define UCSZ2 2 -#define RXB8 1 -#define TXB8 0 - -/* UCSRC */ -#define URSEL 7 -#define UMSEL 6 -#define UPM1 5 -#define UPM0 4 -#define USBS 3 -#define UCSZ1 2 -#define UCSZ0 1 -#define UCPOL 0 - -/* ACSR */ -#define ACD 7 -#define ACBG 6 -#define ACO 5 -#define ACI 4 -#define ACIE 3 -#define ACIC 2 -#define ACIS1 1 -#define ACIS0 0 - -/* ADCSRA */ -#define ADEN 7 -#define ADSC 6 -#define ADATE 5 -#define ADIF 4 -#define ADIE 3 -#define ADPS2 2 -#define ADPS1 1 -#define ADPS0 0 - -/* ADMUX */ -#define REFS1 7 -#define REFS0 6 -#define ADLAR 5 -#define MUX4 4 -#define MUX3 3 -#define MUX2 2 -#define MUX1 1 -#define MUX0 0 - -/* EEPROM Control Register */ -#define EERIE 3 -#define EEMWE 2 -#define EEWE 1 -#define EERE 0 - -/* Constants */ -#define SPM_PAGESIZE 128 -#define RAMSTART (0x60) -#define RAMEND 0x85F -#define XRAMEND RAMEND -#define E2END 0x3FF -#define E2PAGESIZE 4 -#define FLASHEND 0x7FFF - - -/* Fuses */ - -#define FUSE_MEMORY_SIZE 2 - -/* Low Fuse Byte */ -#define FUSE_CKSEL0 (unsigned char)~_BV(0) -#define FUSE_CKSEL1 (unsigned char)~_BV(1) -#define FUSE_CKSEL2 (unsigned char)~_BV(2) -#define FUSE_CKSEL3 (unsigned char)~_BV(3) -#define FUSE_SUT0 (unsigned char)~_BV(4) -#define FUSE_SUT1 (unsigned char)~_BV(5) -#define FUSE_BODEN (unsigned char)~_BV(6) -#define FUSE_BODLEVEL (unsigned char)~_BV(7) -#define LFUSE_DEFAULT (FUSE_CKSEL1 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0) - -/* High Fuse Byte */ -#define FUSE_BOOTRST (unsigned char)~_BV(0) -#define FUSE_BOOTSZ0 (unsigned char)~_BV(1) -#define FUSE_BOOTSZ1 (unsigned char)~_BV(2) -#define FUSE_EESAVE (unsigned char)~_BV(3) -#define FUSE_CKOPT (unsigned char)~_BV(4) -#define FUSE_SPIEN (unsigned char)~_BV(5) -#define FUSE_JTAGEN (unsigned char)~_BV(6) -#define FUSE_OCDEN (unsigned char)~_BV(7) -#define HFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_SPIEN & FUSE_JTAGEN) - - -/* Lock Bits */ -#define __LOCK_BITS_EXIST -#define __BOOT_LOCK_BITS_0_EXIST -#define __BOOT_LOCK_BITS_1_EXIST - - -/* Signature */ -#define SIGNATURE_0 0x1E -#define SIGNATURE_1 0x95 -#define SIGNATURE_2 0x02 - - -/* Deprecated items */ -#if !defined(__AVR_LIBC_DEPRECATED_ENABLE__) - -#pragma GCC system_header - -#pragma GCC poison SIG_INTERRUPT0 -#pragma GCC poison SIG_INTERRUPT1 -#pragma GCC poison SIG_INTERRUPT2 -#pragma GCC poison SIG_OUTPUT_COMPARE2 -#pragma GCC poison SIG_OVERFLOW2 -#pragma GCC poison SIG_INPUT_CAPTURE1 -#pragma GCC poison SIG_OUTPUT_COMPARE1A -#pragma GCC poison SIG_OUTPUT_COMPARE1B -#pragma GCC poison SIG_OVERFLOW1 -#pragma GCC poison SIG_OUTPUT_COMPARE0 -#pragma GCC poison SIG_OVERFLOW0 -#pragma GCC poison SIG_SPI -#pragma GCC poison SIG_USART_RECV -#pragma GCC poison SIG_UART_RECV -#pragma GCC poison SIG_USART_DATA -#pragma GCC poison SIG_UART_DATA -#pragma GCC poison SIG_USART_TRANS -#pragma GCC poison SIG_UART_TRANS -#pragma GCC poison SIG_ADC -#pragma GCC poison SIG_EEPROM_READY -#pragma GCC poison SIG_COMPARATOR -#pragma GCC poison SIG_2WIRE_SERIAL -#pragma GCC poison SIG_SPM_READY - -#endif /* !defined(__AVR_LIBC_DEPRECATED_ENABLE__) */ - -#define SLEEP_MODE_IDLE (0x00<<4) -#define SLEEP_MODE_ADC (0x01<<4) -#define SLEEP_MODE_PWR_DOWN (0x02<<4) -#define SLEEP_MODE_PWR_SAVE (0x03<<4) -#define SLEEP_MODE_STANDBY (0x06<<4) -#define SLEEP_MODE_EXT_STANDBY (0x07<<4) - -#endif /* _AVR_IOM32_H_ */ diff --git a/arduino/hardware/tools/avr/avr/include/avr/iom3208.h b/arduino/hardware/tools/avr/avr/include/avr/iom3208.h deleted file mode 100644 index 6d6c516..0000000 --- a/arduino/hardware/tools/avr/avr/include/avr/iom3208.h +++ /dev/null @@ -1,5385 +0,0 @@ -/***************************************************************************** - * - * Copyright (C) 2017 Atmel Corporation, a wholly owned subsidiary of Microchip Technology Inc. - * All rights reserved. - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - ****************************************************************************/ - - -#ifndef _AVR_IO_H_ -# error "Include instead of this file." -#endif - -#ifndef _AVR_IOXXX_H_ -# define _AVR_IOXXX_H_ "iom3208.h" -#else -# error "Attempt to include more than one file." -#endif - -#ifndef _AVR_ATMEGA3208_H_INCLUDED -#define _AVR_ATMEGA3208_H_INCLUDED - -/* Ungrouped common registers */ -#define CCP _SFR_MEM8(0x0034) /* Configuration Change Protection */ -#define RAMPZ _SFR_MEM8(0x003B) /* Extended Z-pointer Register */ -#define SPH _SFR_MEM8(0x003E) /* Stack Pointer High */ -#define SPL _SFR_MEM8(0x003D) /* Stack Pointer Low */ -#define SREG _SFR_MEM8(0x003F) /* Status Register */ - -#define GPIOR0 _SFR_MEM8(0x001C) /* General Purpose IO Register 0 */ -#define GPIOR1 _SFR_MEM8(0x001D) /* General Purpose IO Register 1 */ -#define GPIOR2 _SFR_MEM8(0x001E) /* General Purpose IO Register 2 */ -#define GPIOR3 _SFR_MEM8(0x001F) /* General Purpose IO Register 3 */ - -/* Deprecated */ -#define GPIO0 _SFR_MEM8(0x001C) /* General Purpose IO Register 0 */ -#define GPIO1 _SFR_MEM8(0x001D) /* General Purpose IO Register 1 */ -#define GPIO2 _SFR_MEM8(0x001E) /* General Purpose IO Register 2 */ -#define GPIO3 _SFR_MEM8(0x001F) /* General Purpose IO Register 3 */ - -/* C Language Only */ -#if !defined (__ASSEMBLER__) - -#include - -typedef volatile uint8_t register8_t; -typedef volatile uint16_t register16_t; -typedef volatile uint32_t register32_t; - - -#ifdef _WORDREGISTER -#undef _WORDREGISTER -#endif -#define _WORDREGISTER(regname) \ - __extension__ union \ - { \ - register16_t regname; \ - struct \ - { \ - register8_t regname ## L; \ - register8_t regname ## H; \ - }; \ - } - -#ifdef _DWORDREGISTER -#undef _DWORDREGISTER -#endif -#define _DWORDREGISTER(regname) \ - __extension__ union \ - { \ - register32_t regname; \ - struct \ - { \ - register8_t regname ## 0; \ - register8_t regname ## 1; \ - register8_t regname ## 2; \ - register8_t regname ## 3; \ - }; \ - } - - -/* -========================================================================== -IO Module Structures -========================================================================== -*/ - - -/* --------------------------------------------------------------------------- -AC - Analog Comparator --------------------------------------------------------------------------- -*/ - -/* Analog Comparator */ -typedef struct AC_struct -{ - register8_t CTRLA; /* Control A */ - register8_t reserved_0x01; - register8_t MUXCTRLA; /* Mux Control A */ - register8_t reserved_0x03; - register8_t DACREF; /* Referance scale control */ - register8_t reserved_0x05; - register8_t INTCTRL; /* Interrupt Control */ - register8_t STATUS; /* Status */ -} AC_t; - -/* Hysteresis Mode select */ -typedef enum AC_HYSMODE_enum -{ - AC_HYSMODE_OFF_gc = (0x00<<1), /* No hysteresis */ - AC_HYSMODE_10mV_gc = (0x01<<1), /* 10mV hysteresis */ - AC_HYSMODE_25mV_gc = (0x02<<1), /* 25mV hysteresis */ - AC_HYSMODE_50mV_gc = (0x03<<1), /* 50mV hysteresis */ -} AC_HYSMODE_t; - -/* Interrupt Mode select */ -typedef enum AC_INTMODE_enum -{ - AC_INTMODE_BOTHEDGE_gc = (0x00<<4), /* Any Edge */ - AC_INTMODE_NEGEDGE_gc = (0x02<<4), /* Negative Edge */ - AC_INTMODE_POSEDGE_gc = (0x03<<4), /* Positive Edge */ -} AC_INTMODE_t; - -/* Low Power Mode select */ -typedef enum AC_LPMODE_enum -{ - AC_LPMODE_DIS_gc = (0x00<<3), /* Low power mode disabled */ - AC_LPMODE_EN_gc = (0x01<<3), /* Low power mode enabled */ -} AC_LPMODE_t; - -/* Negative Input MUX Selection select */ -typedef enum AC_MUXNEG_enum -{ - AC_MUXNEG_PIN0_gc = (0x00<<0), /* Negative Pin 0 */ - AC_MUXNEG_PIN1_gc = (0x01<<0), /* Negative Pin 1 */ - AC_MUXNEG_PIN2_gc = (0x02<<0), /* Negative Pin 2 */ - AC_MUXNEG_DACREF_gc = (0x03<<0), /* DAC Voltage Reference */ -} AC_MUXNEG_t; - -/* Positive Input MUX Selection select */ -typedef enum AC_MUXPOS_enum -{ - AC_MUXPOS_PIN0_gc = (0x00<<3), /* Positive Pin 0 */ - AC_MUXPOS_PIN1_gc = (0x01<<3), /* Positive Pin 1 */ - AC_MUXPOS_PIN2_gc = (0x02<<3), /* Positive Pin 2 */ - AC_MUXPOS_PIN3_gc = (0x03<<3), /* Positive Pin 3 */ -} AC_MUXPOS_t; - -/* --------------------------------------------------------------------------- -ADC - Analog to Digital Converter --------------------------------------------------------------------------- -*/ - -/* Analog to Digital Converter */ -typedef struct ADC_struct -{ - register8_t CTRLA; /* Control A */ - register8_t CTRLB; /* Control B */ - register8_t CTRLC; /* Control C */ - register8_t CTRLD; /* Control D */ - register8_t CTRLE; /* Control E */ - register8_t SAMPCTRL; /* Sample Control */ - register8_t MUXPOS; /* Positive mux input */ - register8_t reserved_0x07; - register8_t COMMAND; /* Command */ - register8_t EVCTRL; /* Event Control */ - register8_t INTCTRL; /* Interrupt Control */ - register8_t INTFLAGS; /* Interrupt Flags */ - register8_t DBGCTRL; /* Debug Control */ - register8_t TEMP; /* Temporary Data */ - register8_t reserved_0x0E; - register8_t reserved_0x0F; - _WORDREGISTER(RES); /* ADC Accumulator Result */ - _WORDREGISTER(WINLT); /* Window comparator low threshold */ - _WORDREGISTER(WINHT); /* Window comparator high threshold */ - register8_t CALIB; /* Calibration */ - register8_t reserved_0x17; -} ADC_t; - -/* Automatic Sampling Delay Variation select */ -typedef enum ADC_ASDV_enum -{ - ADC_ASDV_ASVOFF_gc = (0x00<<4), /* The Automatic Sampling Delay Variation is disabled */ - ADC_ASDV_ASVON_gc = (0x01<<4), /* The Automatic Sampling Delay Variation is enabled */ -} ADC_ASDV_t; - -/* Duty Cycle select */ -typedef enum ADC_DUTYCYC_enum -{ - ADC_DUTYCYC_DUTY50_gc = (0x00<<0), /* 50% Duty cycle */ - ADC_DUTYCYC_DUTY25_gc = (0x01<<0), /* 25% Duty cycle */ -} ADC_DUTYCYC_t; - -/* Initial Delay Selection select */ -typedef enum ADC_INITDLY_enum -{ - ADC_INITDLY_DLY0_gc = (0x00<<5), /* Delay 0 CLK_ADC cycles */ - ADC_INITDLY_DLY16_gc = (0x01<<5), /* Delay 16 CLK_ADC cycles */ - ADC_INITDLY_DLY32_gc = (0x02<<5), /* Delay 32 CLK_ADC cycles */ - ADC_INITDLY_DLY64_gc = (0x03<<5), /* Delay 64 CLK_ADC cycles */ - ADC_INITDLY_DLY128_gc = (0x04<<5), /* Delay 128 CLK_ADC cycles */ - ADC_INITDLY_DLY256_gc = (0x05<<5), /* Delay 256 CLK_ADC cycles */ -} ADC_INITDLY_t; - -/* Analog Channel Selection Bits select */ -typedef enum ADC_MUXPOS_enum -{ - ADC_MUXPOS_AIN0_gc = (0x00<<0), /* ADC input pin 0 */ - ADC_MUXPOS_AIN1_gc = (0x01<<0), /* ADC input pin 1 */ - ADC_MUXPOS_DACREF_gc = (0x1C<<0), /* AC DAC Reference */ - ADC_MUXPOS_TEMPSENSE_gc = (0x1E<<0), /* Temperature sensor */ - ADC_MUXPOS_GND_gc = (0x1F<<0), /* 0V (GND) */ - ADC_MUXPOS_AIN2_gc = (0x02<<0), /* ADC input pin 2 */ - ADC_MUXPOS_AIN3_gc = (0x03<<0), /* ADC input pin 3 */ - ADC_MUXPOS_AIN4_gc = (0x04<<0), /* ADC input pin 4 */ - ADC_MUXPOS_AIN5_gc = (0x05<<0), /* ADC input pin 5 */ - ADC_MUXPOS_AIN6_gc = (0x06<<0), /* ADC input pin 6 */ - ADC_MUXPOS_AIN7_gc = (0x07<<0), /* ADC input pin 7 */ - ADC_MUXPOS_AIN8_gc = (0x08<<0), /* ADC input pin 8 */ - ADC_MUXPOS_AIN9_gc = (0x09<<0), /* ADC input pin 9 */ - ADC_MUXPOS_AIN10_gc = (0x0A<<0), /* ADC input pin 10 */ - ADC_MUXPOS_AIN11_gc = (0x0B<<0), /* ADC input pin 11 */ - ADC_MUXPOS_AIN12_gc = (0x0C<<0), /* ADC input pin 12 */ - ADC_MUXPOS_AIN13_gc = (0x0D<<0), /* ADC input pin 13 */ - ADC_MUXPOS_AIN14_gc = (0x0E<<0), /* ADC input pin 14 */ - ADC_MUXPOS_AIN15_gc = (0x0F<<0), /* ADC input pin 15 */ -} ADC_MUXPOS_t; - -/* Clock Pre-scaler select */ -typedef enum ADC_PRESC_enum -{ - ADC_PRESC_DIV2_gc = (0x00<<0), /* CLK_PER divided by 2 */ - ADC_PRESC_DIV4_gc = (0x01<<0), /* CLK_PER divided by 4 */ - ADC_PRESC_DIV8_gc = (0x02<<0), /* CLK_PER divided by 8 */ - ADC_PRESC_DIV16_gc = (0x03<<0), /* CLK_PER divided by 16 */ - ADC_PRESC_DIV32_gc = (0x04<<0), /* CLK_PER divided by 32 */ - ADC_PRESC_DIV64_gc = (0x05<<0), /* CLK_PER divided by 64 */ - ADC_PRESC_DIV128_gc = (0x06<<0), /* CLK_PER divided by 128 */ - ADC_PRESC_DIV256_gc = (0x07<<0), /* CLK_PER divided by 256 */ -} ADC_PRESC_t; - -/* Reference Selection select */ -typedef enum ADC_REFSEL_enum -{ - ADC_REFSEL_INTREF_gc = (0x00<<4), /* Internal reference */ - ADC_REFSEL_VDDREF_gc = (0x01<<4), /* VDD */ - ADC_REFSEL_VREFA_gc = (0x02<<4), /* External reference */ -} ADC_REFSEL_t; - -/* ADC Resolution select */ -typedef enum ADC_RESSEL_enum -{ - ADC_RESSEL_10BIT_gc = (0x00<<2), /* 10-bit mode */ - ADC_RESSEL_8BIT_gc = (0x01<<2), /* 8-bit mode */ -} ADC_RESSEL_t; - -/* Accumulation Samples select */ -typedef enum ADC_SAMPNUM_enum -{ - ADC_SAMPNUM_ACC1_gc = (0x00<<0), /* 1 ADC sample */ - ADC_SAMPNUM_ACC2_gc = (0x01<<0), /* Accumulate 2 samples */ - ADC_SAMPNUM_ACC4_gc = (0x02<<0), /* Accumulate 4 samples */ - ADC_SAMPNUM_ACC8_gc = (0x03<<0), /* Accumulate 8 samples */ - ADC_SAMPNUM_ACC16_gc = (0x04<<0), /* Accumulate 16 samples */ - ADC_SAMPNUM_ACC32_gc = (0x05<<0), /* Accumulate 32 samples */ - ADC_SAMPNUM_ACC64_gc = (0x06<<0), /* Accumulate 64 samples */ -} ADC_SAMPNUM_t; - -/* Window Comparator Mode select */ -typedef enum ADC_WINCM_enum -{ - ADC_WINCM_NONE_gc = (0x00<<0), /* No Window Comparison */ - ADC_WINCM_BELOW_gc = (0x01<<0), /* Below Window */ - ADC_WINCM_ABOVE_gc = (0x02<<0), /* Above Window */ - ADC_WINCM_INSIDE_gc = (0x03<<0), /* Inside Window */ - ADC_WINCM_OUTSIDE_gc = (0x04<<0), /* Outside Window */ -} ADC_WINCM_t; - -/* --------------------------------------------------------------------------- -BOD - Bod interface --------------------------------------------------------------------------- -*/ - -/* Bod interface */ -typedef struct BOD_struct -{ - register8_t CTRLA; /* Control A */ - register8_t CTRLB; /* Control B */ - register8_t reserved_0x02; - register8_t reserved_0x03; - register8_t reserved_0x04; - register8_t reserved_0x05; - register8_t reserved_0x06; - register8_t reserved_0x07; - register8_t VLMCTRLA; /* Voltage level monitor Control */ - register8_t INTCTRL; /* Voltage level monitor interrupt Control */ - register8_t INTFLAGS; /* Voltage level monitor interrupt Flags */ - register8_t STATUS; /* Voltage level monitor status */ - register8_t reserved_0x0C; - register8_t reserved_0x0D; - register8_t reserved_0x0E; - register8_t reserved_0x0F; -} BOD_t; - -/* Operation in active mode select */ -typedef enum BOD_ACTIVE_enum -{ - BOD_ACTIVE_DIS_gc = (0x00<<2), /* Disabled */ - BOD_ACTIVE_ENABLED_gc = (0x01<<2), /* Enabled */ - BOD_ACTIVE_SAMPLED_gc = (0x02<<2), /* Sampled */ - BOD_ACTIVE_ENWAKE_gc = (0x03<<2), /* Enabled with wake-up halted until BOD is ready */ -} BOD_ACTIVE_t; - -/* Bod level select */ -typedef enum BOD_LVL_enum -{ - BOD_LVL_BODLEVEL0_gc = (0x00<<0), /* 1.8 V */ - BOD_LVL_BODLEVEL1_gc = (0x01<<0), /* 2.1 V */ - BOD_LVL_BODLEVEL2_gc = (0x02<<0), /* 2.6 V */ - BOD_LVL_BODLEVEL3_gc = (0x03<<0), /* 2.9 V */ - BOD_LVL_BODLEVEL4_gc = (0x04<<0), /* 3.3 V */ - BOD_LVL_BODLEVEL5_gc = (0x05<<0), /* 3.7 V */ - BOD_LVL_BODLEVEL6_gc = (0x06<<0), /* 4.0 V */ - BOD_LVL_BODLEVEL7_gc = (0x07<<0), /* 4.2 V */ -} BOD_LVL_t; - -/* Sample frequency select */ -typedef enum BOD_SAMPFREQ_enum -{ - BOD_SAMPFREQ_1KHZ_gc = (0x00<<4), /* 1kHz sampling frequency */ - BOD_SAMPFREQ_125HZ_gc = (0x01<<4), /* 125kHz sampling frequency */ -} BOD_SAMPFREQ_t; - -/* Operation in sleep mode select */ -typedef enum BOD_SLEEP_enum -{ - BOD_SLEEP_DIS_gc = (0x00<<0), /* Disabled */ - BOD_SLEEP_ENABLED_gc = (0x01<<0), /* Enabled */ - BOD_SLEEP_SAMPLED_gc = (0x02<<0), /* Sampled */ -} BOD_SLEEP_t; - -/* Configuration select */ -typedef enum BOD_VLMCFG_enum -{ - BOD_VLMCFG_BELOW_gc = (0x00<<1), /* Interrupt when supply goes below VLM level */ - BOD_VLMCFG_ABOVE_gc = (0x01<<1), /* Interrupt when supply goes above VLM level */ - BOD_VLMCFG_CROSS_gc = (0x02<<1), /* Interrupt when supply crosses VLM level */ -} BOD_VLMCFG_t; - -/* voltage level monitor level select */ -typedef enum BOD_VLMLVL_enum -{ - BOD_VLMLVL_5ABOVE_gc = (0x00<<0), /* VLM threshold 5% above BOD level */ - BOD_VLMLVL_15ABOVE_gc = (0x01<<0), /* VLM threshold 15% above BOD level */ - BOD_VLMLVL_25ABOVE_gc = (0x02<<0), /* VLM threshold 25% above BOD level */ -} BOD_VLMLVL_t; - -/* --------------------------------------------------------------------------- -CCL - Configurable Custom Logic --------------------------------------------------------------------------- -*/ - -/* Configurable Custom Logic */ -typedef struct CCL_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t SEQCTRL0; /* Sequential Control 0 */ - register8_t reserved_0x02; - register8_t reserved_0x03; - register8_t reserved_0x04; - register8_t INTCTRL0; /* Interrupt Control 0 */ - register8_t reserved_0x06; - register8_t INTFLAGS; /* Interrupt Flags */ - register8_t LUT0CTRLA; /* LUT Control 0 A */ - register8_t LUT0CTRLB; /* LUT Control 0 B */ - register8_t LUT0CTRLC; /* LUT Control 0 C */ - register8_t TRUTH0; /* Truth 0 */ - register8_t LUT1CTRLA; /* LUT Control 1 A */ - register8_t LUT1CTRLB; /* LUT Control 1 B */ - register8_t LUT1CTRLC; /* LUT Control 1 C */ - register8_t TRUTH1; /* Truth 1 */ - register8_t LUT2CTRLA; /* LUT Control 2 A */ - register8_t LUT2CTRLB; /* LUT Control 2 B */ - register8_t LUT2CTRLC; /* LUT Control 2 C */ - register8_t TRUTH2; /* Truth 2 */ - register8_t LUT3CTRLA; /* LUT Control 3 A */ - register8_t LUT3CTRLB; /* LUT Control 3 B */ - register8_t LUT3CTRLC; /* LUT Control 3 C */ - register8_t TRUTH3; /* Truth 3 */ - register8_t reserved_0x18; - register8_t reserved_0x19; - register8_t reserved_0x1A; - register8_t reserved_0x1B; - register8_t reserved_0x1C; - register8_t reserved_0x1D; - register8_t reserved_0x1E; - register8_t reserved_0x1F; - register8_t reserved_0x20; - register8_t reserved_0x21; - register8_t reserved_0x22; - register8_t reserved_0x23; - register8_t reserved_0x24; - register8_t reserved_0x25; - register8_t reserved_0x26; - register8_t reserved_0x27; - register8_t reserved_0x28; - register8_t reserved_0x29; - register8_t reserved_0x2A; - register8_t reserved_0x2B; - register8_t reserved_0x2C; - register8_t reserved_0x2D; - register8_t reserved_0x2E; - register8_t reserved_0x2F; - register8_t reserved_0x30; - register8_t reserved_0x31; - register8_t reserved_0x32; - register8_t reserved_0x33; - register8_t reserved_0x34; - register8_t reserved_0x35; - register8_t reserved_0x36; - register8_t reserved_0x37; - register8_t reserved_0x38; - register8_t reserved_0x39; - register8_t reserved_0x3A; - register8_t reserved_0x3B; - register8_t reserved_0x3C; - register8_t reserved_0x3D; - register8_t reserved_0x3E; - register8_t reserved_0x3F; -} CCL_t; - -/* Clock Source Selection select */ -typedef enum CCL_CLKSRC_enum -{ - CCL_CLKSRC_CLKPER_gc = (0x00<<1), /* CLK_PER is clocking the LUT */ - CCL_CLKSRC_IN2_gc = (0x01<<1), /* IN[2] is clocking the LUT */ - CCL_CLKSRC_OSC20M_gc = (0x02<<1), /* 20MHz oscillator before prescaler is clocking the LUT */ - CCL_CLKSRC_OSCULP32K_gc = (0x03<<1), /* 32kHz oscillator is clocking the LUT */ - CCL_CLKSRC_OSCULP1K_gc = (0x04<<1), /* 32kHz oscillator after DIV32 is clocking the LUT */ -} CCL_CLKSRC_t; - -/* Edge Detection Enable select */ -typedef enum CCL_EDGEDET_enum -{ - CCL_EDGEDET_DIS_gc = (0x00<<7), /* Edge detector is disabled */ - CCL_EDGEDET_EN_gc = (0x01<<7), /* Edge detector is enabled */ -} CCL_EDGEDET_t; - -/* Filter Selection select */ -typedef enum CCL_FILTSEL_enum -{ - CCL_FILTSEL_DISABLE_gc = (0x00<<4), /* Filter disabled */ - CCL_FILTSEL_SYNCH_gc = (0x01<<4), /* Synchronizer enabled */ - CCL_FILTSEL_FILTER_gc = (0x02<<4), /* Filter enabled */ -} CCL_FILTSEL_t; - -/* LUT Input 0 Source Selection select */ -typedef enum CCL_INSEL0_enum -{ - CCL_INSEL0_MASK_gc = (0x00<<0), /* Masked input */ - CCL_INSEL0_FEEDBACK_gc = (0x01<<0), /* Feedback input source */ - CCL_INSEL0_LINK_gc = (0x02<<0), /* Linked LUT input source */ - CCL_INSEL0_EVENTA_gc = (0x03<<0), /* Event input source A */ - CCL_INSEL0_EVENTB_gc = (0x04<<0), /* Event input source B */ - CCL_INSEL0_IO_gc = (0x05<<0), /* IO pin LUTn-IN0 input source */ - CCL_INSEL0_AC0_gc = (0x06<<0), /* AC0 OUT input source */ - CCL_INSEL0_USART0_gc = (0x08<<0), /* USART0 TXD input source */ - CCL_INSEL0_SPI0_gc = (0x09<<0), /* SPI0 MOSI input source */ - CCL_INSEL0_TCA0_gc = (0x0A<<0), /* TCA0 WO0 input source */ - CCL_INSEL0_TCB0_gc = (0x0C<<0), /* TCB0 WO input source */ - CCL_INSEL0_TCD0_gc = (0x0D<<0), /* TCD0 WOA input source */ -} CCL_INSEL0_t; - -/* LUT Input 1 Source Selection select */ -typedef enum CCL_INSEL1_enum -{ - CCL_INSEL1_MASK_gc = (0x00<<4), /* Masked input */ - CCL_INSEL1_FEEDBACK_gc = (0x01<<4), /* Feedback input source */ - CCL_INSEL1_LINK_gc = (0x02<<4), /* Linked LUT input source */ - CCL_INSEL1_EVENTA_gc = (0x03<<4), /* Event input source A */ - CCL_INSEL1_EVENTB_gc = (0x04<<4), /* Event input source B */ - CCL_INSEL1_IO_gc = (0x05<<4), /* IO pin LUTn-N1 input source */ - CCL_INSEL1_AC0_gc = (0x06<<4), /* AC0 OUT input source */ - CCL_INSEL1_USART1_gc = (0x08<<4), /* USART1 TXD input source */ - CCL_INSEL1_SPI0_gc = (0x09<<4), /* SPI0 MOSI input source */ - CCL_INSEL1_TCA0_gc = (0x0A<<4), /* TCA0 WO1 input source */ - CCL_INSEL1_TCB1_gc = (0x0C<<4), /* TCB1 WO input source */ - CCL_INSEL1_TCD0_gc = (0x0D<<4), /* TCD0 WOB input soruce */ -} CCL_INSEL1_t; - -/* LUT Input 2 Source Selection select */ -typedef enum CCL_INSEL2_enum -{ - CCL_INSEL2_MASK_gc = (0x00<<0), /* Masked input */ - CCL_INSEL2_FEEDBACK_gc = (0x01<<0), /* Feedback input source */ - CCL_INSEL2_LINK_gc = (0x02<<0), /* Linked LUT input source */ - CCL_INSEL2_EVENTA_gc = (0x03<<0), /* Event input source A */ - CCL_INSEL2_EVENTB_gc = (0x04<<0), /* Event input source B */ - CCL_INSEL2_IO_gc = (0x05<<0), /* IO pin LUTn-IN2 input source */ - CCL_INSEL2_AC0_gc = (0x06<<0), /* AC0 OUT input source */ - CCL_INSEL2_USART2_gc = (0x08<<0), /* USART2 TXD input source */ - CCL_INSEL2_SPI0_gc = (0x09<<0), /* SPI0 SCK input source */ - CCL_INSEL2_TCA0_gc = (0x0A<<0), /* TCA0 WO2 input source */ - CCL_INSEL2_TCB2_gc = (0x0C<<0), /* TCB2 WO input source */ - CCL_INSEL2_TCD0_gc = (0x0D<<0), /* TCD0 WOC input source */ -} CCL_INSEL2_t; - -/* Interrupt Mode for LUT0 select */ -typedef enum CCL_INTMODE0_enum -{ - CCL_INTMODE0_BOTH_gc = (0x00<<0), /* Sense both edges */ - CCL_INTMODE0_FALLING_gc = (0x01<<0), /* Sense falling edge */ - CCL_INTMODE0_RISING_gc = (0x02<<0), /* Sense rising edge */ - CCL_INTMODE0_INTDISABLE_gc = (0x03<<0), /* Interrupt disabled */ -} CCL_INTMODE0_t; - -/* Interrupt Mode for LUT1 select */ -typedef enum CCL_INTMODE1_enum -{ - CCL_INTMODE1_BOTH_gc = (0x00<<2), /* Sense both edges */ - CCL_INTMODE1_FALLING_gc = (0x01<<2), /* Sense falling edge */ - CCL_INTMODE1_RISING_gc = (0x02<<2), /* Sense rising edge */ - CCL_INTMODE1_INTDISABLE_gc = (0x03<<2), /* Interrupt disabled */ -} CCL_INTMODE1_t; - -/* Interrupt Mode for LUT2 select */ -typedef enum CCL_INTMODE2_enum -{ - CCL_INTMODE2_BOTH_gc = (0x00<<4), /* Sense both edges */ - CCL_INTMODE2_FALLING_gc = (0x01<<4), /* Sense falling edge */ - CCL_INTMODE2_RISING_gc = (0x02<<4), /* Sense rising edge */ - CCL_INTMODE2_INTDISABLE_gc = (0x03<<4), /* Interrupt disabled */ -} CCL_INTMODE2_t; - -/* Interrupt Mode for LUT3 select */ -typedef enum CCL_INTMODE3_enum -{ - CCL_INTMODE3_BOTH_gc = (0x00<<6), /* Sense both edges */ - CCL_INTMODE3_FALLING_gc = (0x01<<6), /* Sense falling edge */ - CCL_INTMODE3_RISING_gc = (0x02<<6), /* Sense rising edge */ - CCL_INTMODE3_INTDISABLE_gc = (0x03<<6), /* Interrupt disabled */ -} CCL_INTMODE3_t; - -/* Sequential Selection select */ -typedef enum CCL_SEQSEL_enum -{ - CCL_SEQSEL_DISABLE_gc = (0x00<<0), /* Sequential logic disabled */ - CCL_SEQSEL_DFF_gc = (0x01<<0), /* D FlipFlop */ - CCL_SEQSEL_JK_gc = (0x02<<0), /* JK FlipFlop */ - CCL_SEQSEL_LATCH_gc = (0x03<<0), /* D Latch */ - CCL_SEQSEL_RS_gc = (0x04<<0), /* RS Latch */ -} CCL_SEQSEL_t; - -/* --------------------------------------------------------------------------- -CLKCTRL - Clock controller --------------------------------------------------------------------------- -*/ - -/* Clock controller */ -typedef struct CLKCTRL_struct -{ - register8_t MCLKCTRLA; /* MCLK Control A */ - register8_t MCLKCTRLB; /* MCLK Control B */ - register8_t MCLKLOCK; /* MCLK Lock */ - register8_t MCLKSTATUS; /* MCLK Status */ - register8_t reserved_0x04; - register8_t reserved_0x05; - register8_t reserved_0x06; - register8_t reserved_0x07; - register8_t reserved_0x08; - register8_t reserved_0x09; - register8_t reserved_0x0A; - register8_t reserved_0x0B; - register8_t reserved_0x0C; - register8_t reserved_0x0D; - register8_t reserved_0x0E; - register8_t reserved_0x0F; - register8_t OSC20MCTRLA; /* OSC20M Control A */ - register8_t OSC20MCALIBA; /* OSC20M Calibration A */ - register8_t OSC20MCALIBB; /* OSC20M Calibration B */ - register8_t reserved_0x13; - register8_t reserved_0x14; - register8_t reserved_0x15; - register8_t reserved_0x16; - register8_t reserved_0x17; - register8_t OSC32KCTRLA; /* OSC32K Control A */ - register8_t OSC32KCALIB; /* OSC32K Calibration */ - register8_t reserved_0x1A; - register8_t reserved_0x1B; - register8_t XOSC32KCTRLA; /* XOSC32K Control A */ - register8_t reserved_0x1D; - register8_t reserved_0x1E; - register8_t reserved_0x1F; -} CLKCTRL_t; - -/* clock select select */ -typedef enum CLKCTRL_CLKSEL_enum -{ - CLKCTRL_CLKSEL_OSC20M_gc = (0x00<<0), /* 20MHz oscillator */ - CLKCTRL_CLKSEL_OSCULP32K_gc = (0x01<<0), /* 32KHz oscillator */ - CLKCTRL_CLKSEL_XOSC32K_gc = (0x02<<0), /* 32.768kHz crystal oscillator */ - CLKCTRL_CLKSEL_EXTCLK_gc = (0x03<<0), /* External clock */ -} CLKCTRL_CLKSEL_t; - -/* Crystal startup time select */ -typedef enum CLKCTRL_CSUT_enum -{ - CLKCTRL_CSUT_1K_gc = (0x00<<4), /* 1k cycles */ - CLKCTRL_CSUT_16K_gc = (0x01<<4), /* 16k cycles */ - CLKCTRL_CSUT_32K_gc = (0x02<<4), /* 32k cycles */ - CLKCTRL_CSUT_64K_gc = (0x03<<4), /* 64k cycles */ -} CLKCTRL_CSUT_t; - -/* Prescaler division select */ -typedef enum CLKCTRL_PDIV_enum -{ - CLKCTRL_PDIV_2X_gc = (0x00<<1), /* 2X */ - CLKCTRL_PDIV_4X_gc = (0x01<<1), /* 4X */ - CLKCTRL_PDIV_8X_gc = (0x02<<1), /* 8X */ - CLKCTRL_PDIV_16X_gc = (0x03<<1), /* 16X */ - CLKCTRL_PDIV_32X_gc = (0x04<<1), /* 32X */ - CLKCTRL_PDIV_64X_gc = (0x05<<1), /* 64X */ - CLKCTRL_PDIV_6X_gc = (0x08<<1), /* 6X */ - CLKCTRL_PDIV_10X_gc = (0x09<<1), /* 10X */ - CLKCTRL_PDIV_12X_gc = (0x0A<<1), /* 12X */ - CLKCTRL_PDIV_24X_gc = (0x0B<<1), /* 24X */ - CLKCTRL_PDIV_48X_gc = (0x0C<<1), /* 48X */ -} CLKCTRL_PDIV_t; - -/* --------------------------------------------------------------------------- -CPU - CPU --------------------------------------------------------------------------- -*/ - -/* CCP signature select */ -typedef enum CCP_enum -{ - CCP_SPM_gc = (0x9D<<0), /* SPM Instruction Protection */ - CCP_IOREG_gc = (0xD8<<0), /* IO Register Protection */ -} CCP_t; - -/* --------------------------------------------------------------------------- -CPUINT - Interrupt Controller --------------------------------------------------------------------------- -*/ - -/* Interrupt Controller */ -typedef struct CPUINT_struct -{ - register8_t CTRLA; /* Control A */ - register8_t STATUS; /* Status */ - register8_t LVL0PRI; /* Interrupt Level 0 Priority */ - register8_t LVL1VEC; /* Interrupt Level 1 Priority Vector */ -} CPUINT_t; - - -/* --------------------------------------------------------------------------- -CRCSCAN - CRCSCAN --------------------------------------------------------------------------- -*/ - -/* CRCSCAN */ -typedef struct CRCSCAN_struct -{ - register8_t CTRLA; /* Control A */ - register8_t CTRLB; /* Control B */ - register8_t STATUS; /* Status */ - register8_t reserved_0x03; -} CRCSCAN_t; - -/* CRC Flash Access Mode select */ -typedef enum CRCSCAN_MODE_enum -{ - CRCSCAN_MODE_PRIORITY_gc = (0x00<<4), /* Priority to flash */ - CRCSCAN_MODE_RESERVED_gc = (0x01<<4), /* Reserved */ - CRCSCAN_MODE_BACKGROUND_gc = (0x02<<4), /* Lowest priority to flash */ - CRCSCAN_MODE_CONTINUOUS_gc = (0x03<<4), /* Continuous checks in background */ -} CRCSCAN_MODE_t; - -/* CRC Source select */ -typedef enum CRCSCAN_SRC_enum -{ - CRCSCAN_SRC_FLASH_gc = (0x00<<0), /* CRC on entire flash */ - CRCSCAN_SRC_APPLICATION_gc = (0x01<<0), /* CRC on boot and appl section of flash */ - CRCSCAN_SRC_BOOT_gc = (0x02<<0), /* CRC on boot section of flash */ -} CRCSCAN_SRC_t; - -/* --------------------------------------------------------------------------- -EVSYS - Event System --------------------------------------------------------------------------- -*/ - -/* Event System */ -typedef struct EVSYS_struct -{ - register8_t STROBE; /* Channel Strobe */ - register8_t reserved_0x01; - register8_t reserved_0x02; - register8_t reserved_0x03; - register8_t reserved_0x04; - register8_t reserved_0x05; - register8_t reserved_0x06; - register8_t reserved_0x07; - register8_t reserved_0x08; - register8_t reserved_0x09; - register8_t reserved_0x0A; - register8_t reserved_0x0B; - register8_t reserved_0x0C; - register8_t reserved_0x0D; - register8_t reserved_0x0E; - register8_t reserved_0x0F; - register8_t CHANNEL0; /* Multiplexer Channel 0 */ - register8_t CHANNEL1; /* Multiplexer Channel 1 */ - register8_t CHANNEL2; /* Multiplexer Channel 2 */ - register8_t CHANNEL3; /* Multiplexer Channel 3 */ - register8_t CHANNEL4; /* Multiplexer Channel 4 */ - register8_t CHANNEL5; /* Multiplexer Channel 5 */ - register8_t reserved_0x16; - register8_t reserved_0x17; - register8_t reserved_0x18; - register8_t reserved_0x19; - register8_t reserved_0x1A; - register8_t reserved_0x1B; - register8_t reserved_0x1C; - register8_t reserved_0x1D; - register8_t reserved_0x1E; - register8_t reserved_0x1F; - register8_t USERCCLLUT0A; /* User CCL LUT0 Event A */ - register8_t USERCCLLUT0B; /* User CCL LUT0 Event B */ - register8_t USERCCLLUT1A; /* User CCL LUT1 Event A */ - register8_t USERCCLLUT1B; /* User CCL LUT1 Event B */ - register8_t USERCCLLUT2A; /* User CCL LUT2 Event A */ - register8_t USERCCLLUT2B; /* User CCL LUT2 Event B */ - register8_t USERCCLLUT3A; /* User CCL LUT3 Event A */ - register8_t USERCCLLUT3B; /* User CCL LUT3 Event B */ - register8_t USERADC0; /* User ADC0 */ - register8_t USEREVOUTA; /* User EVOUT Port A */ - register8_t USEREVOUTB; /* User EVOUT Port B */ - register8_t USEREVOUTC; /* User EVOUT Port C */ - register8_t USEREVOUTD; /* User EVOUT Port D */ - register8_t USEREVOUTE; /* User EVOUT Port E */ - register8_t USEREVOUTF; /* User EVOUT Port F */ - register8_t USERUSART0; /* User USART0 */ - register8_t USERUSART1; /* User USART1 */ - register8_t USERUSART2; /* User USART2 */ - register8_t USERUSART3; /* User USART3 */ - register8_t USERTCA0; /* User TCA0 */ - register8_t USERTCB0; /* User TCB0 */ - register8_t USERTCB1; /* User TCB1 */ - register8_t USERTCB2; /* User TCB2 */ - register8_t USERTCB3; /* User TCB3 */ - register8_t reserved_0x38; - register8_t reserved_0x39; - register8_t reserved_0x3A; - register8_t reserved_0x3B; - register8_t reserved_0x3C; - register8_t reserved_0x3D; - register8_t reserved_0x3E; - register8_t reserved_0x3F; -} EVSYS_t; - -/* Channel selector select */ -typedef enum EVSYS_CHANNEL_enum -{ - EVSYS_CHANNEL_OFF_gc = (0x00<<0), /* Off */ - EVSYS_CHANNEL_CHANNEL0_gc = (0x01<<0), /* Connect user to event channel 0 */ - EVSYS_CHANNEL_CHANNEL1_gc = (0x02<<0), /* Connect user to event channel 1 */ - EVSYS_CHANNEL_CHANNEL2_gc = (0x03<<0), /* Connect user to event channel 2 */ - EVSYS_CHANNEL_CHANNEL3_gc = (0x04<<0), /* Connect user to event channel 3 */ - EVSYS_CHANNEL_CHANNEL4_gc = (0x05<<0), /* Connect user to event channel 4 */ - EVSYS_CHANNEL_CHANNEL5_gc = (0x06<<0), /* Connect user to event channel 5 */ -} EVSYS_CHANNEL_t; - -/* Generator selector select */ -typedef enum EVSYS_GENERATOR_enum -{ - EVSYS_GENERATOR_OFF_gc = (0x00<<0), /* Off */ - EVSYS_GENERATOR_UPDI_gc = (0x01<<0), /* Unified Program and Debug Interface */ - EVSYS_GENERATOR_CCL_LUT0_gc = (0x10<<0), /* Configurable Custom Logic LUT0 */ - EVSYS_GENERATOR_CCL_LUT1_gc = (0x11<<0), /* Configurable Custom Logic LUT1 */ - EVSYS_GENERATOR_CCL_LUT2_gc = (0x12<<0), /* Configurable Custom Logic LUT2 */ - EVSYS_GENERATOR_CCL_LUT3_gc = (0x13<<0), /* Configurable Custom Logic LUT3 */ - EVSYS_GENERATOR_OSC_TEST_gc = (0x02<<0), /* Oscillator test event */ - EVSYS_GENERATOR_AC0_OUT_gc = (0x20<<0), /* Analog Comparator 0 out */ - EVSYS_GENERATOR_ADC0_COMP_gc = (0x24<<0), /* ADC 0 Comparator Event */ - EVSYS_GENERATOR_PORT0_PIN0_gc = (0x40<<0), /* Port 0 Pin 0 */ - EVSYS_GENERATOR_PORT0_PIN1_gc = (0x41<<0), /* Port 0 Pin 1 */ - EVSYS_GENERATOR_PORT0_PIN2_gc = (0x42<<0), /* Port 0 Pin 2 */ - EVSYS_GENERATOR_PORT0_PIN3_gc = (0x43<<0), /* Port 0 Pin 3 */ - EVSYS_GENERATOR_PORT0_PIN4_gc = (0x44<<0), /* Port 0 Pin 4 */ - EVSYS_GENERATOR_PORT0_PIN5_gc = (0x45<<0), /* Port 0 Pin 5 */ - EVSYS_GENERATOR_PORT0_PIN6_gc = (0x46<<0), /* Port 0 Pin 6 */ - EVSYS_GENERATOR_PORT0_PIN7_gc = (0x47<<0), /* Port 0 Pin 7 */ - EVSYS_GENERATOR_PORT1_PIN0_gc = (0x48<<0), /* Port 1 Pin 0 */ - EVSYS_GENERATOR_PORT1_PIN1_gc = (0x49<<0), /* Port 1 Pin 1 */ - EVSYS_GENERATOR_PORT1_PIN2_gc = (0x4A<<0), /* Port 1 Pin 2 */ - EVSYS_GENERATOR_PORT1_PIN3_gc = (0x4B<<0), /* Port 1 Pin 3 */ - EVSYS_GENERATOR_PORT1_PIN4_gc = (0x4C<<0), /* Port 1 Pin 4 */ - EVSYS_GENERATOR_PORT1_PIN5_gc = (0x4D<<0), /* Port 1 Pin 5 */ - EVSYS_GENERATOR_PORT1_PIN6_gc = (0x4E<<0), /* Port 1 Pin 6 */ - EVSYS_GENERATOR_PORT1_PIN7_gc = (0x4F<<0), /* Port 1 Pin 7 */ - EVSYS_GENERATOR_RTC_OVF_gc = (0x06<<0), /* Real Time Counter overflow */ - EVSYS_GENERATOR_USART0_XCK_gc = (0x60<<0), /* USART 0 Xclock */ - EVSYS_GENERATOR_USART1_XCK_gc = (0x61<<0), /* USART 1 Xclock */ - EVSYS_GENERATOR_USART2_XCK_gc = (0x62<<0), /* USART 2 Xclock */ - EVSYS_GENERATOR_USART3_XCK_gc = (0x63<<0), /* USART 3 Xclock */ - EVSYS_GENERATOR_SPI0_SCK_gc = (0x68<<0), /* SPI 0 Sclock */ - EVSYS_GENERATOR_RTC_CMP_gc = (0x07<<0), /* Real Time Counter compare */ - EVSYS_GENERATOR_RTC_PIT0_gc = (0x08<<0), /* Periodic Interrupt Timer output 0 */ - EVSYS_GENERATOR_TCA0_OVF_gc = (0x80<<0), /* Timer/Counter A0 overflow */ - EVSYS_GENERATOR_TCA0_ERR_gc = (0x81<<0), /* Timer/Counter A0 error */ - EVSYS_GENERATOR_TCA0_CMP0_gc = (0x84<<0), /* Timer/Counter A0 compare 0 */ - EVSYS_GENERATOR_TCA0_CMP1_gc = (0x85<<0), /* Timer/Counter A0 compare 1 */ - EVSYS_GENERATOR_TCA0_CMP2_gc = (0x86<<0), /* Timer/Counter A0 compare 2 */ - EVSYS_GENERATOR_RTC_PIT1_gc = (0x09<<0), /* Periodic Interrupt Timer output 1 */ - EVSYS_GENERATOR_RTC_PIT2_gc = (0x0A<<0), /* Periodic Interrupt Timer output 2 */ - EVSYS_GENERATOR_TCB0_CMP0_gc = (0xA0<<0), /* Timer/Counter B0 compare 0 */ - EVSYS_GENERATOR_TCB1_CMP0_gc = (0xA2<<0), /* Timer/Counter B1 compare 0 */ - EVSYS_GENERATOR_TCB2_CMP0_gc = (0xA4<<0), /* Timer/Counter B2 compare 0 */ - EVSYS_GENERATOR_TCB3_CMP0_gc = (0xA6<<0), /* Timer/Counter B3 compare 0 */ - EVSYS_GENERATOR_RTC_PIT3_gc = (0x0B<<0), /* Periodic Interrupt Timer output 3 */ -} EVSYS_GENERATOR_t; - -/* Software event on channels select */ -typedef enum EVSYS_STROBE0_enum -{ - EVSYS_STROBE0_EV_STROBE_CH0_gc = (0x01<<0), /* */ - EVSYS_STROBE0_EV_STROBE_CH1_gc = (0x02<<0), /* */ - EVSYS_STROBE0_EV_STROBE_CH2_gc = (0x04<<0), /* */ - EVSYS_STROBE0_EV_STROBE_CH3_gc = (0x08<<0), /* */ - EVSYS_STROBE0_EV_STROBE_CH4_gc = (0x10<<0), /* */ - EVSYS_STROBE0_EV_STROBE_CH5_gc = (0x20<<0), /* */ - EVSYS_STROBE0_EV_STROBE_CH6_gc = (0x40<<0), /* */ - EVSYS_STROBE0_EV_STROBE_CH7_gc = (0x80<<0), /* */ -} EVSYS_STROBE0_t; - -/* --------------------------------------------------------------------------- -FUSE - Fuses --------------------------------------------------------------------------- -*/ - -/* Fuses */ -typedef struct FUSE_struct -{ - register8_t WDTCFG; /* Watchdog Configuration */ - register8_t BODCFG; /* BOD Configuration */ - register8_t OSCCFG; /* Oscillator Configuration */ - register8_t reserved_0x03; - register8_t TCD0CFG; /* TCD0 Configuration */ - register8_t SYSCFG0; /* System Configuration 0 */ - register8_t SYSCFG1; /* System Configuration 1 */ - register8_t APPEND; /* Application Code Section End */ - register8_t BOOTEND; /* Boot Section End */ - register8_t reserved_0x09; -} FUSE_t; - - -/* avr-libc typedef for avr/fuse.h */ -typedef FUSE_t NVM_FUSES_t; - -/* BOD Operation in Active Mode select */ -typedef enum ACTIVE_enum -{ - ACTIVE_DIS_gc = (0x00<<2), /* Disabled */ - ACTIVE_ENABLED_gc = (0x01<<2), /* Enabled */ - ACTIVE_SAMPLED_gc = (0x02<<2), /* Sampled */ - ACTIVE_ENWAKE_gc = (0x03<<2), /* Enabled with wake-up halted until BOD is ready */ -} ACTIVE_t; - -/* CRC Source select */ -typedef enum CRCSRC_enum -{ - CRCSRC_FLASH_gc = (0x00<<6), /* The CRC is performed on the entire Flash (boot, application code and application data section). */ - CRCSRC_BOOT_gc = (0x01<<6), /* The CRC is performed on the boot section of Flash */ - CRCSRC_BOOTAPP_gc = (0x02<<6), /* The CRC is performed on the boot and application code section of Flash */ - CRCSRC_NOCRC_gc = (0x03<<6), /* Disable CRC. */ -} CRCSRC_t; - -/* Frequency Select select */ -typedef enum FREQSEL_enum -{ - FREQSEL_16MHZ_gc = (0x01<<0), /* 16 MHz */ - FREQSEL_20MHZ_gc = (0x02<<0), /* 20 MHz */ -} FREQSEL_t; - -/* BOD Level select */ -typedef enum LVL_enum -{ - LVL_BODLEVEL0_gc = (0x00<<5), /* 1.8 V */ - LVL_BODLEVEL1_gc = (0x01<<5), /* 2.1 V */ - LVL_BODLEVEL2_gc = (0x02<<5), /* 2.6 V */ - LVL_BODLEVEL3_gc = (0x03<<5), /* 2.9 V */ - LVL_BODLEVEL4_gc = (0x04<<5), /* 3.3 V */ - LVL_BODLEVEL5_gc = (0x05<<5), /* 3.7 V */ - LVL_BODLEVEL6_gc = (0x06<<5), /* 4.0 V */ - LVL_BODLEVEL7_gc = (0x07<<5), /* 4.2 V */ -} LVL_t; - -/* Watchdog Timeout Period select */ -typedef enum PERIOD_enum -{ - PERIOD_OFF_gc = (0x00<<0), /* Off */ - PERIOD_8CLK_gc = (0x01<<0), /* 8 cycles (8ms) */ - PERIOD_16CLK_gc = (0x02<<0), /* 16 cycles (16ms) */ - PERIOD_32CLK_gc = (0x03<<0), /* 32 cycles (32ms) */ - PERIOD_64CLK_gc = (0x04<<0), /* 64 cycles (64ms) */ - PERIOD_128CLK_gc = (0x05<<0), /* 128 cycles (0.128s) */ - PERIOD_256CLK_gc = (0x06<<0), /* 256 cycles (0.256s) */ - PERIOD_512CLK_gc = (0x07<<0), /* 512 cycles (0.512s) */ - PERIOD_1KCLK_gc = (0x08<<0), /* 1K cycles (1.0s) */ - PERIOD_2KCLK_gc = (0x09<<0), /* 2K cycles (2.0s) */ - PERIOD_4KCLK_gc = (0x0A<<0), /* 4K cycles (4.1s) */ - PERIOD_8KCLK_gc = (0x0B<<0), /* 8K cycles (8.2s) */ -} PERIOD_t; - -/* Reset Pin Configuration select */ -typedef enum RSTPINCFG_enum -{ - RSTPINCFG_GPIO_gc = (0x00<<2), /* GPIO mode */ - RSTPINCFG_UPDI_gc = (0x01<<2), /* UPDI mode */ - RSTPINCFG_RST_gc = (0x02<<2), /* Reset mode */ - RSTPINCFG_PDIRST_gc = (0x03<<2), /* PDI on PDI pad, reset on alternative reset pad */ -} RSTPINCFG_t; - -/* BOD Sample Frequency select */ -typedef enum SAMPFREQ_enum -{ - SAMPFREQ_1KHZ_gc = (0x00<<4), /* 1kHz sampling frequency */ - SAMPFREQ_125HZ_gc = (0x01<<4), /* 125kHz sampling frequency */ -} SAMPFREQ_t; - -/* BOD Operation in Sleep Mode select */ -typedef enum SLEEP_enum -{ - SLEEP_DIS_gc = (0x00<<0), /* Disabled */ - SLEEP_ENABLED_gc = (0x01<<0), /* Enabled */ - SLEEP_SAMPLED_gc = (0x02<<0), /* Sampled */ -} SLEEP_t; - -/* Startup Time select */ -typedef enum SUT_enum -{ - SUT_0MS_gc = (0x00<<0), /* 0 ms */ - SUT_1MS_gc = (0x01<<0), /* 1 ms */ - SUT_2MS_gc = (0x02<<0), /* 2 ms */ - SUT_4MS_gc = (0x03<<0), /* 4 ms */ - SUT_8MS_gc = (0x04<<0), /* 8 ms */ - SUT_16MS_gc = (0x05<<0), /* 16 ms */ - SUT_32MS_gc = (0x06<<0), /* 32 ms */ - SUT_64MS_gc = (0x07<<0), /* 64 ms */ -} SUT_t; - -/* Watchdog Window Timeout Period select */ -typedef enum WINDOW_enum -{ - WINDOW_OFF_gc = (0x00<<4), /* Off */ - WINDOW_8CLK_gc = (0x01<<4), /* 8 cycles (8ms) */ - WINDOW_16CLK_gc = (0x02<<4), /* 16 cycles (16ms) */ - WINDOW_32CLK_gc = (0x03<<4), /* 32 cycles (32ms) */ - WINDOW_64CLK_gc = (0x04<<4), /* 64 cycles (64ms) */ - WINDOW_128CLK_gc = (0x05<<4), /* 128 cycles (0.128s) */ - WINDOW_256CLK_gc = (0x06<<4), /* 256 cycles (0.256s) */ - WINDOW_512CLK_gc = (0x07<<4), /* 512 cycles (0.512s) */ - WINDOW_1KCLK_gc = (0x08<<4), /* 1K cycles (1.0s) */ - WINDOW_2KCLK_gc = (0x09<<4), /* 2K cycles (2.0s) */ - WINDOW_4KCLK_gc = (0x0A<<4), /* 4K cycles (4.1s) */ - WINDOW_8KCLK_gc = (0x0B<<4), /* 8K cycles (8.2s) */ -} WINDOW_t; - -/* --------------------------------------------------------------------------- -LOCKBIT - Lockbit --------------------------------------------------------------------------- -*/ - -/* Lockbit */ -typedef struct LOCKBIT_struct -{ - register8_t LOCKBIT; /* Lock Bits */ - register8_t reserved_0x01; -} LOCKBIT_t; - -/* Lock Bits select */ -typedef enum LB_enum -{ - LB_RWLOCK_gc = (0x3A<<0), /* Read and write lock */ - LB_NOLOCK_gc = (0xC5<<0), /* No locks */ -} LB_t; - -/* --------------------------------------------------------------------------- -NVMBIST - BIST in the NVMCTRL module --------------------------------------------------------------------------- -*/ - -/* BIST in the NVMCTRL module */ -typedef struct NVMBIST_struct -{ - register8_t CTRLA; /* Control A */ - register8_t ADDRPAT; /* Address pattern */ - register8_t DATAPAT; /* Data pattern */ - register8_t STATUS; /* Status */ - _WORDREGISTER(CNT); /* */ - _DWORDREGISTER(END); /* */ - register8_t reserved_0x0A; - register8_t reserved_0x0B; - register8_t reserved_0x0C; - register8_t reserved_0x0D; - register8_t reserved_0x0E; - register8_t reserved_0x0F; -} NVMBIST_t; - -/* Address mode select */ -typedef enum NVMBIST_AMODE_enum -{ - NVMBIST_AMODE_NORMAL_gc = (0x00<<4), /* No special address pattern */ - NVMBIST_AMODE_COMPLEMENT_gc = (0x04<<4), /* Post complement address */ -} NVMBIST_AMODE_t; - -/* Command select */ -typedef enum NVMBIST_CMD_enum -{ - NVMBIST_CMD_NOCMD_gc = (0x00<<0), /* No effect */ - NVMBIST_CMD_START_gc = (0x01<<0), /* Start BIST testing */ - NVMBIST_CMD_RESTART_gc = (0x02<<0), /* Re-start BIST testing */ - NVMBIST_CMD_BREAK_gc = (0x03<<0), /* Stop BIST and go to BREAK state */ -} NVMBIST_CMD_t; - -/* Data check pattern select */ -typedef enum NVMBIST_PATTERN_enum -{ - NVMBIST_PATTERN_ZEROES_gc = (0x00<<0), /* All flash programmed */ - NVMBIST_PATTERN_CHECK_gc = (0x01<<0), /* Physical checkerboard in flash */ - NVMBIST_PATTERN_INVCHECK_gc = (0x02<<0), /* Inverse physical checkerboard in flash */ - NVMBIST_PATTERN_ONES_gc = (0x03<<0), /* All flash unprogrammed */ -} NVMBIST_PATTERN_t; - -/* FSM State select */ -typedef enum NVMBIST_STATE_enum -{ - NVMBIST_STATE_IDLE_gc = (0x00<<0), /* Reset state */ - NVMBIST_STATE_BREAK_gc = (0x01<<0), /* Break command used */ - NVMBIST_STATE_FAILED0_gc = (0x04<<0), /* Test failed, data from last address */ - NVMBIST_STATE_FAILED1_gc = (0x05<<0), /* Test failed, data from address-1 */ - NVMBIST_STATE_FAILED2_gc = (0x06<<0), /* Test failed, data from address-2 */ - NVMBIST_STATE_SUCCESS_gc = (0x07<<0), /* Test success */ - NVMBIST_STATE_START0_gc = (0x08<<0), /* Startup, fetching first data */ - NVMBIST_STATE_START1_gc = (0x09<<0), /* Startup, fetching second data */ - NVMBIST_STATE_RESTART0_gc = (0x0A<<0), /* Re-start from BREAK or FAILED2 */ - NVMBIST_STATE_RESTART1_gc = (0x0B<<0), /* Re-start from FAILED1 */ - NVMBIST_STATE_RUNNING_gc = (0x0C<<0), /* Test running */ - NVMBIST_STATE_FINISH0_gc = (0x0E<<0), /* Check last word */ - NVMBIST_STATE_FINISH1_gc = (0x0F<<0), /* Count faults in last word */ -} NVMBIST_STATE_t; - -/* X address mode select */ -typedef enum NVMBIST_XMODE_enum -{ - NVMBIST_XMODE_STATIC_gc = (0x00<<0), /* X static */ - NVMBIST_XMODE_CARRY_gc = (0x01<<0), /* Carry/borrow from Y */ - NVMBIST_XMODE_INC_gc = (0x02<<0), /* X increment each cycle */ - NVMBIST_XMODE_DEC_gc = (0x03<<0), /* X decrement each cycle */ -} NVMBIST_XMODE_t; - -/* Y address mode select */ -typedef enum NVMBIST_YMODE_enum -{ - NVMBIST_YMODE_STATIC_gc = (0x00<<2), /* Y static */ - NVMBIST_YMODE_CARRY_gc = (0x01<<2), /* Carry/borrow from X */ - NVMBIST_YMODE_INC_gc = (0x02<<2), /* Y increment each cycle */ - NVMBIST_YMODE_DEC_gc = (0x03<<2), /* Y decrement each cycle */ -} NVMBIST_YMODE_t; - -/* --------------------------------------------------------------------------- -NVMCTRL - Non-volatile Memory Controller --------------------------------------------------------------------------- -*/ - -/* Non-volatile Memory Controller */ -typedef struct NVMCTRL_struct -{ - register8_t CTRLA; /* Control A */ - register8_t CTRLB; /* Control B */ - register8_t STATUS; /* Status */ - register8_t INTCTRL; /* Interrupt Control */ - register8_t INTFLAGS; /* Interrupt Flags */ - register8_t reserved_0x05; - _WORDREGISTER(DATA); /* Data */ - _WORDREGISTER(ADDR); /* Address */ - register8_t reserved_0x0A; - register8_t reserved_0x0B; - register8_t reserved_0x0C; - register8_t reserved_0x0D; - register8_t reserved_0x0E; - register8_t reserved_0x0F; -} NVMCTRL_t; - -/* Command select */ -typedef enum NVMCTRL_CMD_enum -{ - NVMCTRL_CMD_NONE_gc = (0x00<<0), /* No Command */ - NVMCTRL_CMD_PAGEWRITE_gc = (0x01<<0), /* Write page */ - NVMCTRL_CMD_PAGEERASE_gc = (0x02<<0), /* Erase page */ - NVMCTRL_CMD_PAGEERASEWRITE_gc = (0x03<<0), /* Erase and write page */ - NVMCTRL_CMD_PAGEBUFCLR_gc = (0x04<<0), /* Page buffer clear */ - NVMCTRL_CMD_CHIPERASE_gc = (0x05<<0), /* Chip erase */ - NVMCTRL_CMD_EEERASE_gc = (0x06<<0), /* EEPROM erase */ - NVMCTRL_CMD_FUSEWRITE_gc = (0x07<<0), /* Write fuse (PDI only) */ -} NVMCTRL_CMD_t; - -/* --------------------------------------------------------------------------- -PORT - I/O Ports --------------------------------------------------------------------------- -*/ - -/* I/O Ports */ -typedef struct PORT_struct -{ - register8_t DIR; /* Data Direction */ - register8_t DIRSET; /* Data Direction Set */ - register8_t DIRCLR; /* Data Direction Clear */ - register8_t DIRTGL; /* Data Direction Toggle */ - register8_t OUT; /* Output Value */ - register8_t OUTSET; /* Output Value Set */ - register8_t OUTCLR; /* Output Value Clear */ - register8_t OUTTGL; /* Output Value Toggle */ - register8_t IN; /* Input Value */ - register8_t INTFLAGS; /* Interrupt Flags */ - register8_t PORTCTRL; /* Port Control */ - register8_t reserved_0x0B; - register8_t reserved_0x0C; - register8_t reserved_0x0D; - register8_t reserved_0x0E; - register8_t reserved_0x0F; - register8_t PIN0CTRL; /* Pin 0 Control */ - register8_t PIN1CTRL; /* Pin 1 Control */ - register8_t PIN2CTRL; /* Pin 2 Control */ - register8_t PIN3CTRL; /* Pin 3 Control */ - register8_t PIN4CTRL; /* Pin 4 Control */ - register8_t PIN5CTRL; /* Pin 5 Control */ - register8_t PIN6CTRL; /* Pin 6 Control */ - register8_t PIN7CTRL; /* Pin 7 Control */ - register8_t reserved_0x18; - register8_t reserved_0x19; - register8_t reserved_0x1A; - register8_t reserved_0x1B; - register8_t reserved_0x1C; - register8_t reserved_0x1D; - register8_t reserved_0x1E; - register8_t reserved_0x1F; -} PORT_t; - -/* Input/Sense Configuration select */ -typedef enum PORT_ISC_enum -{ - PORT_ISC_INTDISABLE_gc = (0x00<<0), /* Interrupt disabled but input buffer enabled */ - PORT_ISC_BOTHEDGES_gc = (0x01<<0), /* Sense Both Edges */ - PORT_ISC_RISING_gc = (0x02<<0), /* Sense Rising Edge */ - PORT_ISC_FALLING_gc = (0x03<<0), /* Sense Falling Edge */ - PORT_ISC_INPUT_DISABLE_gc = (0x04<<0), /* Digital Input Buffer disabled */ - PORT_ISC_LEVEL_gc = (0x05<<0), /* Sense low Level */ -} PORT_ISC_t; - -/* --------------------------------------------------------------------------- -PORTMUX - Port Multiplexer --------------------------------------------------------------------------- -*/ - -/* Port Multiplexer */ -typedef struct PORTMUX_struct -{ - register8_t EVSYSROUTEA; /* Port Multiplexer EVSYS */ - register8_t CCLROUTEA; /* Port Multiplexer CCL */ - register8_t USARTROUTEA; /* Port Multiplexer USART register A */ - register8_t TWISPIROUTEA; /* Port Multiplexer TWI and SPI */ - register8_t TCAROUTEA; /* Port Multiplexer TCA */ - register8_t TCBROUTEA; /* Port Multiplexer TCB */ - register8_t reserved_0x06; - register8_t reserved_0x07; - register8_t reserved_0x08; - register8_t reserved_0x09; - register8_t reserved_0x0A; - register8_t reserved_0x0B; - register8_t reserved_0x0C; - register8_t reserved_0x0D; - register8_t reserved_0x0E; - register8_t reserved_0x0F; -} PORTMUX_t; - -/* Port Multiplexer SPI0 select */ -typedef enum PORTMUX_SPI0_enum -{ - PORTMUX_SPI0_DEFAULT_gc = (0x00<<0), /* SPI0 on PA[7:4] */ - PORTMUX_SPI0_ALT1_gc = (0x01<<0), /* SPI0 on PC[3:0] */ - PORTMUX_SPI0_ALT2_gc = (0x02<<0), /* SPI0 on PE[3:0] */ - PORTMUX_SPI0_NONE_gc = (0x03<<0), /* Not connected to any pins */ -} PORTMUX_SPI0_t; - -/* Port Multiplexer TCA0 select */ -typedef enum PORTMUX_TCA0_enum -{ - PORTMUX_TCA0_PORTA_gc = (0x00<<0), /* TCA0 pins on PA[5:0] */ - PORTMUX_TCA0_PORTB_gc = (0x01<<0), /* TCA0 pins on PB[5:0] */ - PORTMUX_TCA0_PORTC_gc = (0x02<<0), /* TCA0 pins on PC[5:0] */ - PORTMUX_TCA0_PORTD_gc = (0x03<<0), /* TCA0 pins on PD[5:0] */ - PORTMUX_TCA0_PORTE_gc = (0x04<<0), /* TCA0 pins on PE[5:0] */ - PORTMUX_TCA0_PORTF_gc = (0x05<<0), /* TCA0 pins on PF[5:0] */ -} PORTMUX_TCA0_t; - -/* Port Multiplexer TWI0 select */ -typedef enum PORTMUX_TWI0_enum -{ - PORTMUX_TWI0_DEFAULT_gc = (0x00<<4), /* SCL/SDA on PA[3:2], Slave mode on PC[3:2] in dual TWI mode */ - PORTMUX_TWI0_ALT1_gc = (0x01<<4), /* SCL/SDA on PA[3:2], Slave mode on PF[3:2] in dual TWI mode */ - PORTMUX_TWI0_ALT2_gc = (0x02<<4), /* SCL/SDA on PC[3:2], Slave mode on PF[3:2] in dual TWI mode */ - PORTMUX_TWI0_NONE_gc = (0x03<<4), /* Not connected to any pins */ -} PORTMUX_TWI0_t; - -/* Port Multiplexer USART0 select */ -typedef enum PORTMUX_USART0_enum -{ - PORTMUX_USART0_DEFAULT_gc = (0x00<<0), /* USART0 on PA[3:0] */ - PORTMUX_USART0_ALT1_gc = (0x01<<0), /* USART0 on PA[7:4] */ - PORTMUX_USART0_NONE_gc = (0x03<<0), /* Not connected to any pins */ -} PORTMUX_USART0_t; - -/* Port Multiplexer USART1 select */ -typedef enum PORTMUX_USART1_enum -{ - PORTMUX_USART1_DEFAULT_gc = (0x00<<2), /* USART1 on PC[3:0] */ - PORTMUX_USART1_ALT1_gc = (0x01<<2), /* USART1 on PC[7:4] */ - PORTMUX_USART1_NONE_gc = (0x03<<2), /* Not connected to any pins */ -} PORTMUX_USART1_t; - -/* Port Multiplexer USART2 select */ -typedef enum PORTMUX_USART2_enum -{ - PORTMUX_USART2_DEFAULT_gc = (0x00<<4), /* USART2 on PF[3:0] */ - PORTMUX_USART2_ALT1_gc = (0x01<<4), /* USART2 on PF[5:4] */ - PORTMUX_USART2_NONE_gc = (0x03<<4), /* Not connected to any pins */ -} PORTMUX_USART2_t; - -/* Port Multiplexer USART3 select */ -typedef enum PORTMUX_USART3_enum -{ - PORTMUX_USART3_DEFAULT_gc = (0x00<<6), /* USART3 on PB[3:0] */ - PORTMUX_USART3_ALT1_gc = (0x01<<6), /* USART3 on PB[5:4] */ - PORTMUX_USART3_NONE_gc = (0x03<<6), /* Not connected to any pins */ -} PORTMUX_USART3_t; - -/* --------------------------------------------------------------------------- -RSTCTRL - Reset controller --------------------------------------------------------------------------- -*/ - -/* Reset controller */ -typedef struct RSTCTRL_struct -{ - register8_t RSTFR; /* Reset Flags */ - register8_t SWRR; /* Software Reset */ - register8_t reserved_0x02; - register8_t reserved_0x03; -} RSTCTRL_t; - - -/* --------------------------------------------------------------------------- -RTC - Real-Time Counter --------------------------------------------------------------------------- -*/ - -/* Real-Time Counter */ -typedef struct RTC_struct -{ - register8_t CTRLA; /* Control A */ - register8_t STATUS; /* Status */ - register8_t INTCTRL; /* Interrupt Control */ - register8_t INTFLAGS; /* Interrupt Flags */ - register8_t TEMP; /* Temporary */ - register8_t DBGCTRL; /* Debug control */ - register8_t reserved_0x06; - register8_t CLKSEL; /* Clock Select */ - _WORDREGISTER(CNT); /* Counter */ - _WORDREGISTER(PER); /* Period */ - _WORDREGISTER(CMP); /* Compare */ - register8_t reserved_0x0E; - register8_t reserved_0x0F; - register8_t PITCTRLA; /* PIT Control A */ - register8_t PITSTATUS; /* PIT Status */ - register8_t PITINTCTRL; /* PIT Interrupt Control */ - register8_t PITINTFLAGS; /* PIT Interrupt Flags */ - register8_t reserved_0x14; - register8_t PITDBGCTRL; /* PIT Debug control */ - register8_t reserved_0x16; - register8_t reserved_0x17; - register8_t reserved_0x18; - register8_t reserved_0x19; - register8_t reserved_0x1A; - register8_t reserved_0x1B; - register8_t reserved_0x1C; - register8_t reserved_0x1D; - register8_t reserved_0x1E; - register8_t reserved_0x1F; -} RTC_t; - -/* Clock Select select */ -typedef enum RTC_CLKSEL_enum -{ - RTC_CLKSEL_INT32K_gc = (0x00<<0), /* Internal 32kHz OSC */ - RTC_CLKSEL_INT1K_gc = (0x01<<0), /* Internal 1kHz OSC */ - RTC_CLKSEL_TOSC32K_gc = (0x02<<0), /* 32KHz Crystal OSC */ - RTC_CLKSEL_EXTCLK_gc = (0x03<<0), /* External Clock */ -} RTC_CLKSEL_t; - -/* Period select */ -typedef enum RTC_PERIOD_enum -{ - RTC_PERIOD_OFF_gc = (0x00<<3), /* Off */ - RTC_PERIOD_CYC4_gc = (0x01<<3), /* RTC Clock Cycles 4 */ - RTC_PERIOD_CYC8_gc = (0x02<<3), /* RTC Clock Cycles 8 */ - RTC_PERIOD_CYC16_gc = (0x03<<3), /* RTC Clock Cycles 16 */ - RTC_PERIOD_CYC32_gc = (0x04<<3), /* RTC Clock Cycles 32 */ - RTC_PERIOD_CYC64_gc = (0x05<<3), /* RTC Clock Cycles 64 */ - RTC_PERIOD_CYC128_gc = (0x06<<3), /* RTC Clock Cycles 128 */ - RTC_PERIOD_CYC256_gc = (0x07<<3), /* RTC Clock Cycles 256 */ - RTC_PERIOD_CYC512_gc = (0x08<<3), /* RTC Clock Cycles 512 */ - RTC_PERIOD_CYC1024_gc = (0x09<<3), /* RTC Clock Cycles 1024 */ - RTC_PERIOD_CYC2048_gc = (0x0A<<3), /* RTC Clock Cycles 2048 */ - RTC_PERIOD_CYC4096_gc = (0x0B<<3), /* RTC Clock Cycles 4096 */ - RTC_PERIOD_CYC8192_gc = (0x0C<<3), /* RTC Clock Cycles 8192 */ - RTC_PERIOD_CYC16384_gc = (0x0D<<3), /* RTC Clock Cycles 16384 */ - RTC_PERIOD_CYC32768_gc = (0x0E<<3), /* RTC Clock Cycles 32768 */ -} RTC_PERIOD_t; - -/* Prescaling Factor select */ -typedef enum RTC_PRESCALER_enum -{ - RTC_PRESCALER_DIV1_gc = (0x00<<3), /* RTC Clock / 1 */ - RTC_PRESCALER_DIV2_gc = (0x01<<3), /* RTC Clock / 2 */ - RTC_PRESCALER_DIV4_gc = (0x02<<3), /* RTC Clock / 4 */ - RTC_PRESCALER_DIV8_gc = (0x03<<3), /* RTC Clock / 8 */ - RTC_PRESCALER_DIV16_gc = (0x04<<3), /* RTC Clock / 16 */ - RTC_PRESCALER_DIV32_gc = (0x05<<3), /* RTC Clock / 32 */ - RTC_PRESCALER_DIV64_gc = (0x06<<3), /* RTC Clock / 64 */ - RTC_PRESCALER_DIV128_gc = (0x07<<3), /* RTC Clock / 128 */ - RTC_PRESCALER_DIV256_gc = (0x08<<3), /* RTC Clock / 256 */ - RTC_PRESCALER_DIV512_gc = (0x09<<3), /* RTC Clock / 512 */ - RTC_PRESCALER_DIV1024_gc = (0x0A<<3), /* RTC Clock / 1024 */ - RTC_PRESCALER_DIV2048_gc = (0x0B<<3), /* RTC Clock / 2048 */ - RTC_PRESCALER_DIV4096_gc = (0x0C<<3), /* RTC Clock / 4096 */ - RTC_PRESCALER_DIV8192_gc = (0x0D<<3), /* RTC Clock / 8192 */ - RTC_PRESCALER_DIV16384_gc = (0x0E<<3), /* RTC Clock / 16384 */ - RTC_PRESCALER_DIV32768_gc = (0x0F<<3), /* RTC Clock / 32768 */ -} RTC_PRESCALER_t; - -/* --------------------------------------------------------------------------- -SIGROW - Signature row --------------------------------------------------------------------------- -*/ - -/* Signature row */ -typedef struct SIGROW_struct -{ - register8_t DEVICEID0; /* Device ID Byte 0 */ - register8_t DEVICEID1; /* Device ID Byte 1 */ - register8_t DEVICEID2; /* Device ID Byte 2 */ - register8_t SERNUM0; /* Serial Number Byte 0 */ - register8_t SERNUM1; /* Serial Number Byte 1 */ - register8_t SERNUM2; /* Serial Number Byte 2 */ - register8_t SERNUM3; /* Serial Number Byte 3 */ - register8_t SERNUM4; /* Serial Number Byte 4 */ - register8_t SERNUM5; /* Serial Number Byte 5 */ - register8_t SERNUM6; /* Serial Number Byte 6 */ - register8_t SERNUM7; /* Serial Number Byte 7 */ - register8_t SERNUM8; /* Serial Number Byte 8 */ - register8_t SERNUM9; /* Serial Number Byte 9 */ - register8_t reserved_0x0D; - register8_t reserved_0x0E; - register8_t reserved_0x0F; - register8_t reserved_0x10; - register8_t reserved_0x11; - register8_t reserved_0x12; - register8_t reserved_0x13; - register8_t OSCCAL32K; /* Oscillator Calibration for 32kHz ULP */ - register8_t reserved_0x15; - register8_t reserved_0x16; - register8_t reserved_0x17; - register8_t OSCCAL16M0; /* Oscillator Calibration 16 MHz Byte 0 */ - register8_t OSCCAL16M1; /* Oscillator Calibration 16 MHz Byte 1 */ - register8_t OSCCAL20M0; /* Oscillator Calibration 20 MHz Byte 0 */ - register8_t OSCCAL20M1; /* Oscillator Calibration 20 MHz Byte 1 */ - register8_t reserved_0x1C; - register8_t reserved_0x1D; - register8_t reserved_0x1E; - register8_t reserved_0x1F; - register8_t TEMPSENSE0; /* Temperature Sensor Calibration Byte 0 */ - register8_t TEMPSENSE1; /* Temperature Sensor Calibration Byte 1 */ - register8_t OSC16ERR3V; /* OSC16 error at 3V */ - register8_t OSC16ERR5V; /* OSC16 error at 5V */ - register8_t OSC20ERR3V; /* OSC20 error at 3V */ - register8_t OSC20ERR5V; /* OSC20 error at 5V */ - register8_t reserved_0x26; - register8_t reserved_0x27; - register8_t reserved_0x28; - register8_t reserved_0x29; - register8_t reserved_0x2A; - register8_t reserved_0x2B; - register8_t reserved_0x2C; - register8_t reserved_0x2D; - register8_t reserved_0x2E; - register8_t CHECKSUM1; /* CRC Checksum Byte 1 */ - register8_t reserved_0x30; - register8_t reserved_0x31; - register8_t reserved_0x32; - register8_t reserved_0x33; - register8_t reserved_0x34; - register8_t reserved_0x35; - register8_t reserved_0x36; - register8_t reserved_0x37; - register8_t reserved_0x38; - register8_t reserved_0x39; - register8_t reserved_0x3A; - register8_t reserved_0x3B; - register8_t reserved_0x3C; - register8_t reserved_0x3D; - register8_t reserved_0x3E; - register8_t reserved_0x3F; -} SIGROW_t; - - -/* --------------------------------------------------------------------------- -SLPCTRL - Sleep Controller --------------------------------------------------------------------------- -*/ - -/* Sleep Controller */ -typedef struct SLPCTRL_struct -{ - register8_t CTRLA; /* Control */ - register8_t reserved_0x01; -} SLPCTRL_t; - -/* Sleep mode select */ -typedef enum SLPCTRL_SMODE_enum -{ - SLPCTRL_SMODE_IDLE_gc = (0x00<<1), /* Idle mode */ - SLPCTRL_SMODE_STDBY_gc = (0x01<<1), /* Standby Mode */ - SLPCTRL_SMODE_PDOWN_gc = (0x02<<1), /* Power-down Mode */ -} SLPCTRL_SMODE_t; - -#define SLEEP_MODE_IDLE (0x00<<1) -#define SLEEP_MODE_STANDBY (0x01<<1) -#define SLEEP_MODE_PWR_DOWN (0x02<<1) -/* --------------------------------------------------------------------------- -SPI - Serial Peripheral Interface --------------------------------------------------------------------------- -*/ - -/* Serial Peripheral Interface */ -typedef struct SPI_struct -{ - register8_t CTRLA; /* Control A */ - register8_t CTRLB; /* Control B */ - register8_t INTCTRL; /* Interrupt Control */ - register8_t INTFLAGS; /* Interrupt Flags */ - register8_t DATA; /* Data */ - register8_t reserved_0x05; - register8_t reserved_0x06; - register8_t reserved_0x07; -} SPI_t; - -/* SPI Mode select */ -typedef enum SPI_MODE_enum -{ - SPI_MODE_0_gc = (0x00<<0), /* SPI Mode 0 */ - SPI_MODE_1_gc = (0x01<<0), /* SPI Mode 1 */ - SPI_MODE_2_gc = (0x02<<0), /* SPI Mode 2 */ - SPI_MODE_3_gc = (0x03<<0), /* SPI Mode 3 */ -} SPI_MODE_t; - -/* Prescaler select */ -typedef enum SPI_PRESC_enum -{ - SPI_PRESC_DIV4_gc = (0x00<<1), /* System Clock / 4 */ - SPI_PRESC_DIV16_gc = (0x01<<1), /* System Clock / 16 */ - SPI_PRESC_DIV64_gc = (0x02<<1), /* System Clock / 64 */ - SPI_PRESC_DIV128_gc = (0x03<<1), /* System Clock / 128 */ -} SPI_PRESC_t; - -/* --------------------------------------------------------------------------- -SYSCFG - System Configuration Registers --------------------------------------------------------------------------- -*/ - -/* System Configuration Registers */ -typedef struct SYSCFG_struct -{ - register8_t reserved_0x00; - register8_t REVID; /* Revision ID */ - register8_t EXTBRK; /* External Break */ - register8_t reserved_0x03; - register8_t reserved_0x04; - register8_t reserved_0x05; - register8_t reserved_0x06; - register8_t reserved_0x07; - register8_t reserved_0x08; - register8_t reserved_0x09; - register8_t reserved_0x0A; - register8_t reserved_0x0B; - register8_t reserved_0x0C; - register8_t reserved_0x0D; - register8_t reserved_0x0E; - register8_t reserved_0x0F; - register8_t reserved_0x10; - register8_t reserved_0x11; - register8_t reserved_0x12; - register8_t reserved_0x13; - register8_t reserved_0x14; - register8_t reserved_0x15; - register8_t reserved_0x16; - register8_t reserved_0x17; - register8_t OCDM; /* OCD Message Register */ - register8_t OCDMS; /* OCD Message Status */ - register8_t reserved_0x1A; - register8_t reserved_0x1B; - register8_t reserved_0x1C; - register8_t reserved_0x1D; - register8_t reserved_0x1E; - register8_t reserved_0x1F; -} SYSCFG_t; - - -/* --------------------------------------------------------------------------- -TCA - 16-bit Timer/Counter Type A --------------------------------------------------------------------------- -*/ - -/* 16-bit Timer/Counter Type A - Single Mode */ -typedef struct TCA_SINGLE_struct -{ - register8_t CTRLA; /* Control A */ - register8_t CTRLB; /* Control B */ - register8_t CTRLC; /* Control C */ - register8_t CTRLD; /* Control D */ - register8_t CTRLECLR; /* Control E Clear */ - register8_t CTRLESET; /* Control E Set */ - register8_t CTRLFCLR; /* Control F Clear */ - register8_t CTRLFSET; /* Control F Set */ - register8_t reserved_0x08; - register8_t EVCTRL; /* Event Control */ - register8_t INTCTRL; /* Interrupt Control */ - register8_t INTFLAGS; /* Interrupt Flags */ - register8_t reserved_0x0C; - register8_t reserved_0x0D; - register8_t DBGCTRL; /* Degbug Control */ - register8_t TEMP; /* Temporary data for 16-bit Access */ - register8_t reserved_0x10; - register8_t reserved_0x11; - register8_t reserved_0x12; - register8_t reserved_0x13; - register8_t reserved_0x14; - register8_t reserved_0x15; - register8_t reserved_0x16; - register8_t reserved_0x17; - register8_t reserved_0x18; - register8_t reserved_0x19; - register8_t reserved_0x1A; - register8_t reserved_0x1B; - register8_t reserved_0x1C; - register8_t reserved_0x1D; - register8_t reserved_0x1E; - register8_t reserved_0x1F; - _WORDREGISTER(CNT); /* Count */ - register8_t reserved_0x22; - register8_t reserved_0x23; - register8_t reserved_0x24; - register8_t reserved_0x25; - _WORDREGISTER(PER); /* Period */ - _WORDREGISTER(CMP0); /* Compare 0 */ - _WORDREGISTER(CMP1); /* Compare 1 */ - _WORDREGISTER(CMP2); /* Compare 2 */ - register8_t reserved_0x2E; - register8_t reserved_0x2F; - register8_t reserved_0x30; - register8_t reserved_0x31; - register8_t reserved_0x32; - register8_t reserved_0x33; - register8_t reserved_0x34; - register8_t reserved_0x35; - _WORDREGISTER(PERBUF); /* Period Buffer */ - _WORDREGISTER(CMP0BUF); /* Compare 0 Buffer */ - _WORDREGISTER(CMP1BUF); /* Compare 1 Buffer */ - _WORDREGISTER(CMP2BUF); /* Compare 2 Buffer */ - register8_t reserved_0x3E; - register8_t reserved_0x3F; -} TCA_SINGLE_t; - - -/* 16-bit Timer/Counter Type A - Split Mode */ -typedef struct TCA_SPLIT_struct -{ - register8_t CTRLA; /* Control A */ - register8_t CTRLB; /* Control B */ - register8_t CTRLC; /* Control C */ - register8_t CTRLD; /* Control D */ - register8_t CTRLECLR; /* Control E Clear */ - register8_t CTRLESET; /* Control E Set */ - register8_t reserved_0x06; - register8_t reserved_0x07; - register8_t reserved_0x08; - register8_t reserved_0x09; - register8_t INTCTRL; /* Interrupt Control */ - register8_t INTFLAGS; /* Interrupt Flags */ - register8_t reserved_0x0C; - register8_t reserved_0x0D; - register8_t DBGCTRL; /* Degbug Control */ - register8_t reserved_0x0F; - register8_t reserved_0x10; - register8_t reserved_0x11; - register8_t reserved_0x12; - register8_t reserved_0x13; - register8_t reserved_0x14; - register8_t reserved_0x15; - register8_t reserved_0x16; - register8_t reserved_0x17; - register8_t reserved_0x18; - register8_t reserved_0x19; - register8_t reserved_0x1A; - register8_t reserved_0x1B; - register8_t reserved_0x1C; - register8_t reserved_0x1D; - register8_t reserved_0x1E; - register8_t reserved_0x1F; - register8_t LCNT; /* Low Count */ - register8_t HCNT; /* High Count */ - register8_t reserved_0x22; - register8_t reserved_0x23; - register8_t reserved_0x24; - register8_t reserved_0x25; - register8_t LPER; /* Low Period */ - register8_t HPER; /* High Period */ - register8_t LCMP0; /* Low Compare */ - register8_t HCMP0; /* High Compare */ - register8_t LCMP1; /* Low Compare */ - register8_t HCMP1; /* High Compare */ - register8_t LCMP2; /* Low Compare */ - register8_t HCMP2; /* High Compare */ - register8_t reserved_0x2E; - register8_t reserved_0x2F; - register8_t reserved_0x30; - register8_t reserved_0x31; - register8_t reserved_0x32; - register8_t reserved_0x33; - register8_t reserved_0x34; - register8_t reserved_0x35; - register8_t reserved_0x36; - register8_t reserved_0x37; - register8_t reserved_0x38; - register8_t reserved_0x39; - register8_t reserved_0x3A; - register8_t reserved_0x3B; - register8_t reserved_0x3C; - register8_t reserved_0x3D; - register8_t reserved_0x3E; - register8_t reserved_0x3F; -} TCA_SPLIT_t; - - -/* 16-bit Timer/Counter Type A */ -typedef union TCA_union -{ - TCA_SINGLE_t SINGLE; /* 16-bit Timer/Counter Type A - Single Mode */ - TCA_SPLIT_t SPLIT; /* 16-bit Timer/Counter Type A - Split Mode */ -} TCA_t; - -/* Clock Selection select */ -typedef enum TCA_SINGLE_CLKSEL_enum -{ - TCA_SINGLE_CLKSEL_DIV1_gc = (0x00<<1), /* System Clock */ - TCA_SINGLE_CLKSEL_DIV2_gc = (0x01<<1), /* System Clock / 2 */ - TCA_SINGLE_CLKSEL_DIV4_gc = (0x02<<1), /* System Clock / 4 */ - TCA_SINGLE_CLKSEL_DIV8_gc = (0x03<<1), /* System Clock / 8 */ - TCA_SINGLE_CLKSEL_DIV16_gc = (0x04<<1), /* System Clock / 16 */ - TCA_SINGLE_CLKSEL_DIV64_gc = (0x05<<1), /* System Clock / 64 */ - TCA_SINGLE_CLKSEL_DIV256_gc = (0x06<<1), /* System Clock / 256 */ - TCA_SINGLE_CLKSEL_DIV1024_gc = (0x07<<1), /* System Clock / 1024 */ -} TCA_SINGLE_CLKSEL_t; - -/* Command select */ -typedef enum TCA_SINGLE_CMD_enum -{ - TCA_SINGLE_CMD_NONE_gc = (0x00<<2), /* No Command */ - TCA_SINGLE_CMD_UPDATE_gc = (0x01<<2), /* Force Update */ - TCA_SINGLE_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ - TCA_SINGLE_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ -} TCA_SINGLE_CMD_t; - -/* Direction select */ -typedef enum TCA_SINGLE_DIR_enum -{ - TCA_SINGLE_DIR_UP_gc = (0x00<<0), /* Count up */ - TCA_SINGLE_DIR_DOWN_gc = (0x01<<0), /* Count down */ -} TCA_SINGLE_DIR_t; - -/* Event Action select */ -typedef enum TCA_SINGLE_EVACT_enum -{ - TCA_SINGLE_EVACT_POSEDGE_gc = (0x00<<1), /* Count on positive edge event */ - TCA_SINGLE_EVACT_ANYEDGE_gc = (0x01<<1), /* Count on any edge event */ - TCA_SINGLE_EVACT_HIGHLVL_gc = (0x02<<1), /* Count on prescaled clock while event line is 1. */ - TCA_SINGLE_EVACT_UPDOWN_gc = (0x03<<1), /* Count on prescaled clock. Event controls count direction. Up-count when event line is 0, down-count when event line is 1. */ -} TCA_SINGLE_EVACT_t; - -/* Waveform generation mode select */ -typedef enum TCA_SINGLE_WGMODE_enum -{ - TCA_SINGLE_WGMODE_NORMAL_gc = (0x00<<0), /* Normal Mode */ - TCA_SINGLE_WGMODE_FRQ_gc = (0x01<<0), /* Frequency Generation Mode */ - TCA_SINGLE_WGMODE_SINGLESLOPE_gc = (0x03<<0), /* Single Slope PWM */ - TCA_SINGLE_WGMODE_DSTOP_gc = (0x05<<0), /* Dual Slope PWM, overflow on TOP */ - TCA_SINGLE_WGMODE_DSBOTH_gc = (0x06<<0), /* Dual Slope PWM, overflow on TOP and BOTTOM */ - TCA_SINGLE_WGMODE_DSBOTTOM_gc = (0x07<<0), /* Dual Slope PWM, overflow on BOTTOM */ -} TCA_SINGLE_WGMODE_t; - -/* Clock Selection select */ -typedef enum TCA_SPLIT_CLKSEL_enum -{ - TCA_SPLIT_CLKSEL_DIV1_gc = (0x00<<1), /* System Clock */ - TCA_SPLIT_CLKSEL_DIV2_gc = (0x01<<1), /* System Clock / 2 */ - TCA_SPLIT_CLKSEL_DIV4_gc = (0x02<<1), /* System Clock / 4 */ - TCA_SPLIT_CLKSEL_DIV8_gc = (0x03<<1), /* System Clock / 8 */ - TCA_SPLIT_CLKSEL_DIV16_gc = (0x04<<1), /* System Clock / 16 */ - TCA_SPLIT_CLKSEL_DIV64_gc = (0x05<<1), /* System Clock / 64 */ - TCA_SPLIT_CLKSEL_DIV256_gc = (0x06<<1), /* System Clock / 256 */ - TCA_SPLIT_CLKSEL_DIV1024_gc = (0x07<<1), /* System Clock / 1024 */ -} TCA_SPLIT_CLKSEL_t; - -/* Command select */ -typedef enum TCA_SPLIT_CMD_enum -{ - TCA_SPLIT_CMD_NONE_gc = (0x00<<2), /* No Command */ - TCA_SPLIT_CMD_UPDATE_gc = (0x01<<2), /* Force Update */ - TCA_SPLIT_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ - TCA_SPLIT_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ -} TCA_SPLIT_CMD_t; - -/* --------------------------------------------------------------------------- -TCB - 16-bit Timer Type B --------------------------------------------------------------------------- -*/ - -/* 16-bit Timer Type B */ -typedef struct TCB_struct -{ - register8_t CTRLA; /* Control A */ - register8_t CTRLB; /* Control Register B */ - register8_t reserved_0x02; - register8_t reserved_0x03; - register8_t EVCTRL; /* Event Control */ - register8_t INTCTRL; /* Interrupt Control */ - register8_t INTFLAGS; /* Interrupt Flags */ - register8_t STATUS; /* Status */ - register8_t DBGCTRL; /* Debug Control */ - register8_t TEMP; /* Temporary Value */ - _WORDREGISTER(CNT); /* Count */ - _WORDREGISTER(CCMP); /* Compare or Capture */ - register8_t reserved_0x0E; - register8_t reserved_0x0F; -} TCB_t; - -/* Clock Select select */ -typedef enum TCB_CLKSEL_enum -{ - TCB_CLKSEL_CLKDIV1_gc = (0x00<<1), /* CLK_PER (No Prescaling) */ - TCB_CLKSEL_CLKDIV2_gc = (0x01<<1), /* CLK_PER/2 (From Prescaler) */ - TCB_CLKSEL_CLKTCA_gc = (0x02<<1), /* Use Clock from TCA */ -} TCB_CLKSEL_t; - -/* Timer Mode select */ -typedef enum TCB_CNTMODE_enum -{ - TCB_CNTMODE_INT_gc = (0x00<<0), /* Periodic Interrupt */ - TCB_CNTMODE_TIMEOUT_gc = (0x01<<0), /* Periodic Timeout */ - TCB_CNTMODE_CAPT_gc = (0x02<<0), /* Input Capture Event */ - TCB_CNTMODE_FRQ_gc = (0x03<<0), /* Input Capture Frequency measurement */ - TCB_CNTMODE_PW_gc = (0x04<<0), /* Input Capture Pulse-Width measurement */ - TCB_CNTMODE_FRQPW_gc = (0x05<<0), /* Input Capture Frequency and Pulse-Width measurement */ - TCB_CNTMODE_SINGLE_gc = (0x06<<0), /* Single Shot */ - TCB_CNTMODE_PWM8_gc = (0x07<<0), /* 8-bit PWM */ -} TCB_CNTMODE_t; - -/* --------------------------------------------------------------------------- -TWI - Two-Wire Interface --------------------------------------------------------------------------- -*/ - -/* Two-Wire Interface */ -typedef struct TWI_struct -{ - register8_t CTRLA; /* Control A */ - register8_t BRIDGECTRL; /* Bridge Control */ - register8_t DBGCTRL; /* Debug Control Register */ - register8_t MCTRLA; /* Master Control A */ - register8_t MCTRLB; /* Master Control B */ - register8_t MSTATUS; /* Master Status */ - register8_t MBAUD; /* Master Baurd Rate Control */ - register8_t MADDR; /* Master Address */ - register8_t MDATA; /* Master Data */ - register8_t SCTRLA; /* Slave Control A */ - register8_t SCTRLB; /* Slave Control B */ - register8_t SSTATUS; /* Slave Status */ - register8_t SADDR; /* Slave Address */ - register8_t SDATA; /* Slave Data */ - register8_t SADDRMASK; /* Slave Address Mask */ - register8_t reserved_0x0F; -} TWI_t; - -/* Acknowledge Action select */ -typedef enum TWI_ACKACT_enum -{ - TWI_ACKACT_ACK_gc = (0x00<<2), /* Send ACK */ - TWI_ACKACT_NACK_gc = (0x01<<2), /* Send NACK */ -} TWI_ACKACT_t; - -/* Slave Address or Stop select */ -typedef enum TWI_AP_enum -{ - TWI_AP_STOP_gc = (0x00<<0), /* Stop condition generated APIF */ - TWI_AP_ADR_gc = (0x01<<0), /* Address detection generated APIF */ -} TWI_AP_t; - -/* Bus State select */ -typedef enum TWI_BUSSTATE_enum -{ - TWI_BUSSTATE_UNKNOWN_gc = (0x00<<0), /* Unknown Bus State */ - TWI_BUSSTATE_IDLE_gc = (0x01<<0), /* Bus is Idle */ - TWI_BUSSTATE_OWNER_gc = (0x02<<0), /* This Module Controls The Bus */ - TWI_BUSSTATE_BUSY_gc = (0x03<<0), /* The Bus is Busy */ -} TWI_BUSSTATE_t; - -/* Command select */ -typedef enum TWI_MCMD_enum -{ - TWI_MCMD_NOACT_gc = (0x00<<0), /* No Action */ - TWI_MCMD_REPSTART_gc = (0x01<<0), /* Issue Repeated Start Condition */ - TWI_MCMD_RECVTRANS_gc = (0x02<<0), /* Receive or Transmit Data, depending on DIR */ - TWI_MCMD_STOP_gc = (0x03<<0), /* Issue Stop Condition */ -} TWI_MCMD_t; - -/* Command select */ -typedef enum TWI_SCMD_enum -{ - TWI_SCMD_NOACT_gc = (0x00<<0), /* No Action */ - TWI_SCMD_COMPTRANS_gc = (0x02<<0), /* Used To Complete a Transaction */ - TWI_SCMD_RESPONSE_gc = (0x03<<0), /* Used in Response to Address/Data Interrupt */ -} TWI_SCMD_t; - -/* SDA Hold Time select */ -typedef enum TWI_SDAHOLD_enum -{ - TWI_SDAHOLD_OFF_gc = (0x00<<2), /* SDA hold time off */ - TWI_SDAHOLD_50NS_gc = (0x01<<2), /* Typical 50ns hold time */ - TWI_SDAHOLD_300NS_gc = (0x02<<2), /* Typical 300ns hold time */ - TWI_SDAHOLD_500NS_gc = (0x03<<2), /* Typical 500ns hold time */ -} TWI_SDAHOLD_t; - -/* SDA Setup Time select */ -typedef enum TWI_SDASETUP_enum -{ - TWI_SDASETUP_4CYC_gc = (0x00<<4), /* SDA setup time is 4 clock cycles */ - TWI_SDASETUP_8CYC_gc = (0x01<<4), /* SDA setup time is 8 clock cycles */ -} TWI_SDASETUP_t; - -/* Inactive Bus Timeout select */ -typedef enum TWI_TIMEOUT_enum -{ - TWI_TIMEOUT_DISABLED_gc = (0x00<<2), /* Bus Timeout Disabled */ - TWI_TIMEOUT_50US_gc = (0x01<<2), /* 50 Microseconds */ - TWI_TIMEOUT_100US_gc = (0x02<<2), /* 100 Microseconds */ - TWI_TIMEOUT_200US_gc = (0x03<<2), /* 200 Microseconds */ -} TWI_TIMEOUT_t; - -/* --------------------------------------------------------------------------- -USART - Universal Synchronous and Asynchronous Receiver and Transmitter --------------------------------------------------------------------------- -*/ - -/* Universal Synchronous and Asynchronous Receiver and Transmitter */ -typedef struct USART_struct -{ - register8_t RXDATAL; /* Receive Data Low Byte */ - register8_t RXDATAH; /* Receive Data High Byte */ - register8_t TXDATAL; /* Transmit Data Low Byte */ - register8_t TXDATAH; /* Transmit Data High Byte */ - register8_t STATUS; /* Status */ - register8_t CTRLA; /* Control A */ - register8_t CTRLB; /* Control B */ - register8_t CTRLC; /* Control C */ - _WORDREGISTER(BAUD); /* Baud Rate */ - register8_t CTRLD; /* Control D */ - register8_t DBGCTRL; /* Debug Control */ - register8_t EVCTRL; /* Event Control */ - register8_t TXPLCTRL; /* IRCOM Transmitter Pulse Length Control */ - register8_t RXPLCTRL; /* IRCOM Receiver Pulse Length Control */ - register8_t reserved_0x0F; -} USART_t; - -/* Character Size select */ -typedef enum USART_CHSIZE_enum -{ - USART_CHSIZE_5BIT_gc = (0x00<<0), /* Character size: 5 bit */ - USART_CHSIZE_6BIT_gc = (0x01<<0), /* Character size: 6 bit */ - USART_CHSIZE_7BIT_gc = (0x02<<0), /* Character size: 7 bit */ - USART_CHSIZE_8BIT_gc = (0x03<<0), /* Character size: 8 bit */ - USART_CHSIZE_9BITL_gc = (0x06<<0), /* Character size: 9 bit read low byte first */ - USART_CHSIZE_9BITH_gc = (0x07<<0), /* Character size: 9 bit read high byte first */ -} USART_CHSIZE_t; - -/* Communication Mode select */ -typedef enum USART_CMODE_enum -{ - USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6), /* Asynchronous Mode */ - USART_CMODE_SYNCHRONOUS_gc = (0x01<<6), /* Synchronous Mode */ - USART_CMODE_IRCOM_gc = (0x02<<6), /* Infrared Communication */ - USART_CMODE_MSPI_gc = (0x03<<6), /* Master SPI Mode */ -} USART_CMODE_t; - -/* Parity Mode select */ -typedef enum USART_PMODE_enum -{ - USART_PMODE_DISABLED_gc = (0x00<<4), /* No Parity */ - USART_PMODE_EVEN_gc = (0x02<<4), /* Even Parity */ - USART_PMODE_ODD_gc = (0x03<<4), /* Odd Parity */ -} USART_PMODE_t; - -/* RS485 Mode internal transmitter select */ -typedef enum USART_RS485_enum -{ - USART_RS485_OFF_gc = (0x00<<0), /* RS485 Mode disabled */ - USART_RS485_EXT_gc = (0x01<<0), /* RS485 Mode External drive */ - USART_RS485_INT_gc = (0x02<<0), /* RS485 Mode Internal drive */ -} USART_RS485_t; - -/* Receiver Mode select */ -typedef enum USART_RXMODE_enum -{ - USART_RXMODE_NORMAL_gc = (0x00<<1), /* Normal mode */ - USART_RXMODE_CLK2X_gc = (0x01<<1), /* CLK2x mode */ - USART_RXMODE_GENAUTO_gc = (0x02<<1), /* Generic autobaud mode */ - USART_RXMODE_LINAUTO_gc = (0x03<<1), /* LIN constrained autobaud mode */ -} USART_RXMODE_t; - -/* Stop Bit Mode select */ -typedef enum USART_SBMODE_enum -{ - USART_SBMODE_1BIT_gc = (0x00<<3), /* 1 stop bit */ - USART_SBMODE_2BIT_gc = (0x01<<3), /* 2 stop bits */ -} USART_SBMODE_t; - -/* --------------------------------------------------------------------------- -USERROW - User Row --------------------------------------------------------------------------- -*/ - -/* User Row */ -typedef struct USERROW_struct -{ - register8_t USERROW0; /* User Row Byte 0 */ - register8_t USERROW1; /* User Row Byte 1 */ - register8_t USERROW2; /* User Row Byte 2 */ - register8_t USERROW3; /* User Row Byte 3 */ - register8_t USERROW4; /* User Row Byte 4 */ - register8_t USERROW5; /* User Row Byte 5 */ - register8_t USERROW6; /* User Row Byte 6 */ - register8_t USERROW7; /* User Row Byte 7 */ - register8_t USERROW8; /* User Row Byte 8 */ - register8_t USERROW9; /* User Row Byte 9 */ - register8_t USERROW10; /* User Row Byte 10 */ - register8_t USERROW11; /* User Row Byte 11 */ - register8_t USERROW12; /* User Row Byte 12 */ - register8_t USERROW13; /* User Row Byte 13 */ - register8_t USERROW14; /* User Row Byte 14 */ - register8_t USERROW15; /* User Row Byte 15 */ - register8_t USERROW16; /* User Row Byte 16 */ - register8_t USERROW17; /* User Row Byte 17 */ - register8_t USERROW18; /* User Row Byte 18 */ - register8_t USERROW19; /* User Row Byte 19 */ - register8_t USERROW20; /* User Row Byte 20 */ - register8_t USERROW21; /* User Row Byte 21 */ - register8_t USERROW22; /* User Row Byte 22 */ - register8_t USERROW23; /* User Row Byte 23 */ - register8_t USERROW24; /* User Row Byte 24 */ - register8_t USERROW25; /* User Row Byte 25 */ - register8_t USERROW26; /* User Row Byte 26 */ - register8_t USERROW27; /* User Row Byte 27 */ - register8_t USERROW28; /* User Row Byte 28 */ - register8_t USERROW29; /* User Row Byte 29 */ - register8_t USERROW30; /* User Row Byte 30 */ - register8_t USERROW31; /* User Row Byte 31 */ - register8_t USERROW32; /* User Row Byte 32 */ - register8_t USERROW33; /* User Row Byte 33 */ - register8_t USERROW34; /* User Row Byte 34 */ - register8_t USERROW35; /* User Row Byte 35 */ - register8_t USERROW36; /* User Row Byte 36 */ - register8_t USERROW37; /* User Row Byte 37 */ - register8_t USERROW38; /* User Row Byte 38 */ - register8_t USERROW39; /* User Row Byte 39 */ - register8_t USERROW40; /* User Row Byte 40 */ - register8_t USERROW41; /* User Row Byte 41 */ - register8_t USERROW42; /* User Row Byte 42 */ - register8_t USERROW43; /* User Row Byte 43 */ - register8_t USERROW44; /* User Row Byte 44 */ - register8_t USERROW45; /* User Row Byte 45 */ - register8_t USERROW46; /* User Row Byte 46 */ - register8_t USERROW47; /* User Row Byte 47 */ - register8_t USERROW48; /* User Row Byte 48 */ - register8_t USERROW49; /* User Row Byte 49 */ - register8_t USERROW50; /* User Row Byte 50 */ - register8_t USERROW51; /* User Row Byte 51 */ - register8_t USERROW52; /* User Row Byte 52 */ - register8_t USERROW53; /* User Row Byte 53 */ - register8_t USERROW54; /* User Row Byte 54 */ - register8_t USERROW55; /* User Row Byte 55 */ - register8_t USERROW56; /* User Row Byte 56 */ - register8_t USERROW57; /* User Row Byte 57 */ - register8_t USERROW58; /* User Row Byte 58 */ - register8_t USERROW59; /* User Row Byte 59 */ - register8_t USERROW60; /* User Row Byte 60 */ - register8_t USERROW61; /* User Row Byte 61 */ - register8_t USERROW62; /* User Row Byte 62 */ - register8_t USERROW63; /* User Row Byte 63 */ -} USERROW_t; - - -/* --------------------------------------------------------------------------- -VPORT - Virtual Ports --------------------------------------------------------------------------- -*/ - -/* Virtual Ports */ -typedef struct VPORT_struct -{ - register8_t DIR; /* Data Direction */ - register8_t OUT; /* Output Value */ - register8_t IN; /* Input Value */ - register8_t INTFLAGS; /* Interrupt Flags */ -} VPORT_t; - - -/* --------------------------------------------------------------------------- -VREF - Voltage reference --------------------------------------------------------------------------- -*/ - -/* Voltage reference */ -typedef struct VREF_struct -{ - register8_t CTRLA; /* Control A */ - register8_t CTRLB; /* Control B */ -} VREF_t; - -/* AC0 reference select select */ -typedef enum VREF_AC0REFSEL_enum -{ - VREF_AC0REFSEL_0V55_gc = (0x00<<0), /* Voltage reference at 0.55V */ - VREF_AC0REFSEL_1V1_gc = (0x01<<0), /* Voltage reference at 1.1V */ - VREF_AC0REFSEL_2V5_gc = (0x02<<0), /* Voltage reference at 2.5V */ - VREF_AC0REFSEL_4V34_gc = (0x03<<0), /* Voltage reference at 4.34V */ - VREF_AC0REFSEL_1V5_gc = (0x04<<0), /* Voltage reference at 1.5V */ -} VREF_AC0REFSEL_t; - -/* ADC0 reference select select */ -typedef enum VREF_ADC0REFSEL_enum -{ - VREF_ADC0REFSEL_0V55_gc = (0x00<<4), /* Voltage reference at 0.55V */ - VREF_ADC0REFSEL_1V1_gc = (0x01<<4), /* Voltage reference at 1.1V */ - VREF_ADC0REFSEL_2V5_gc = (0x02<<4), /* Voltage reference at 2.5V */ - VREF_ADC0REFSEL_4V34_gc = (0x03<<4), /* Voltage reference at 4.34V */ - VREF_ADC0REFSEL_1V5_gc = (0x04<<4), /* Voltage reference at 1.5V */ -} VREF_ADC0REFSEL_t; - -/* --------------------------------------------------------------------------- -WDT - Watch-Dog Timer --------------------------------------------------------------------------- -*/ - -/* Watch-Dog Timer */ -typedef struct WDT_struct -{ - register8_t CTRLA; /* Control A */ - register8_t STATUS; /* Status */ -} WDT_t; - -/* Period select */ -typedef enum WDT_PERIOD_enum -{ - WDT_PERIOD_OFF_gc = (0x00<<0), /* Off */ - WDT_PERIOD_8CLK_gc = (0x01<<0), /* 8 cycles (8ms) */ - WDT_PERIOD_16CLK_gc = (0x02<<0), /* 16 cycles (16ms) */ - WDT_PERIOD_32CLK_gc = (0x03<<0), /* 32 cycles (32ms) */ - WDT_PERIOD_64CLK_gc = (0x04<<0), /* 64 cycles (64ms) */ - WDT_PERIOD_128CLK_gc = (0x05<<0), /* 128 cycles (0.128s) */ - WDT_PERIOD_256CLK_gc = (0x06<<0), /* 256 cycles (0.256s) */ - WDT_PERIOD_512CLK_gc = (0x07<<0), /* 512 cycles (0.512s) */ - WDT_PERIOD_1KCLK_gc = (0x08<<0), /* 1K cycles (1.0s) */ - WDT_PERIOD_2KCLK_gc = (0x09<<0), /* 2K cycles (2.0s) */ - WDT_PERIOD_4KCLK_gc = (0x0A<<0), /* 4K cycles (4.1s) */ - WDT_PERIOD_8KCLK_gc = (0x0B<<0), /* 8K cycles (8.2s) */ -} WDT_PERIOD_t; - -/* Window select */ -typedef enum WDT_WINDOW_enum -{ - WDT_WINDOW_OFF_gc = (0x00<<4), /* Off */ - WDT_WINDOW_8CLK_gc = (0x01<<4), /* 8 cycles (8ms) */ - WDT_WINDOW_16CLK_gc = (0x02<<4), /* 16 cycles (16ms) */ - WDT_WINDOW_32CLK_gc = (0x03<<4), /* 32 cycles (32ms) */ - WDT_WINDOW_64CLK_gc = (0x04<<4), /* 64 cycles (64ms) */ - WDT_WINDOW_128CLK_gc = (0x05<<4), /* 128 cycles (0.128s) */ - WDT_WINDOW_256CLK_gc = (0x06<<4), /* 256 cycles (0.256s) */ - WDT_WINDOW_512CLK_gc = (0x07<<4), /* 512 cycles (0.512s) */ - WDT_WINDOW_1KCLK_gc = (0x08<<4), /* 1K cycles (1.0s) */ - WDT_WINDOW_2KCLK_gc = (0x09<<4), /* 2K cycles (2.0s) */ - WDT_WINDOW_4KCLK_gc = (0x0A<<4), /* 4K cycles (4.1s) */ - WDT_WINDOW_8KCLK_gc = (0x0B<<4), /* 8K cycles (8.2s) */ -} WDT_WINDOW_t; -/* -========================================================================== -IO Module Instances. Mapped to memory. -========================================================================== -*/ - -#define VPORTA (*(VPORT_t *) 0x0000) /* Virtual Ports */ -#define VPORTB (*(VPORT_t *) 0x0004) /* Virtual Ports */ -#define VPORTC (*(VPORT_t *) 0x0008) /* Virtual Ports */ -#define VPORTD (*(VPORT_t *) 0x000C) /* Virtual Ports */ -#define VPORTE (*(VPORT_t *) 0x0010) /* Virtual Ports */ -#define VPORTF (*(VPORT_t *) 0x0014) /* Virtual Ports */ -#define RSTCTRL (*(RSTCTRL_t *) 0x0040) /* Reset controller */ -#define SLPCTRL (*(SLPCTRL_t *) 0x0050) /* Sleep Controller */ -#define CLKCTRL (*(CLKCTRL_t *) 0x0060) /* Clock controller */ -#define BOD (*(BOD_t *) 0x0080) /* Bod interface */ -#define VREF (*(VREF_t *) 0x00A0) /* Voltage reference */ -#define NVMBIST (*(NVMBIST_t *) 0x00C0) /* BIST in the NVMCTRL module */ -#define WDT (*(WDT_t *) 0x0100) /* Watch-Dog Timer */ -#define CPUINT (*(CPUINT_t *) 0x0110) /* Interrupt Controller */ -#define CRCSCAN (*(CRCSCAN_t *) 0x0120) /* CRCSCAN */ -#define RTC (*(RTC_t *) 0x0140) /* Real-Time Counter */ -#define EVSYS (*(EVSYS_t *) 0x0180) /* Event System */ -#define CCL (*(CCL_t *) 0x01C0) /* Configurable Custom Logic */ -#define PORTA (*(PORT_t *) 0x0400) /* I/O Ports */ -#define PORTB (*(PORT_t *) 0x0420) /* I/O Ports */ -#define PORTC (*(PORT_t *) 0x0440) /* I/O Ports */ -#define PORTD (*(PORT_t *) 0x0460) /* I/O Ports */ -#define PORTE (*(PORT_t *) 0x0480) /* I/O Ports */ -#define PORTF (*(PORT_t *) 0x04A0) /* I/O Ports */ -#define PORTMUX (*(PORTMUX_t *) 0x05E0) /* Port Multiplexer */ -#define ADC0 (*(ADC_t *) 0x0600) /* Analog to Digital Converter */ -#define AC0 (*(AC_t *) 0x0680) /* Analog Comparator */ -#define USART0 (*(USART_t *) 0x0800) /* Universal Synchronous and Asynchronous Receiver and Transmitter */ -#define USART1 (*(USART_t *) 0x0820) /* Universal Synchronous and Asynchronous Receiver and Transmitter */ -#define TWI0 (*(TWI_t *) 0x08A0) /* Two-Wire Interface */ -#define SPI0 (*(SPI_t *) 0x08C0) /* Serial Peripheral Interface */ -#define TCA0 (*(TCA_t *) 0x0A00) /* 16-bit Timer/Counter Type A */ -#define TCB0 (*(TCB_t *) 0x0A80) /* 16-bit Timer Type B */ -#define TCB1 (*(TCB_t *) 0x0A90) /* 16-bit Timer Type B */ -#define TCB2 (*(TCB_t *) 0x0AA0) /* 16-bit Timer Type B */ -#define SYSCFG (*(SYSCFG_t *) 0x0F00) /* System Configuration Registers */ -#define NVMCTRL (*(NVMCTRL_t *) 0x1000) /* Non-volatile Memory Controller */ -#define SIGROW (*(SIGROW_t *) 0x1100) /* Signature row */ -#define FUSE (*(FUSE_t *) 0x1280) /* Fuses */ -#define LOCKBIT (*(LOCKBIT_t *) 0x128A) /* Lockbit */ -#define USERROW (*(USERROW_t *) 0x1300) /* User Row */ - -#endif /* !defined (__ASSEMBLER__) */ - - -/* ========== Flattened fully qualified IO register names ========== */ - - -/* VPORT (VPORTA) - Virtual Ports */ -#define VPORTA_DIR _SFR_MEM8(0x0000) -#define VPORTA_OUT _SFR_MEM8(0x0001) -#define VPORTA_IN _SFR_MEM8(0x0002) -#define VPORTA_INTFLAGS _SFR_MEM8(0x0003) - - -/* VPORT (VPORTB) - Virtual Ports */ -#define VPORTB_DIR _SFR_MEM8(0x0004) -#define VPORTB_OUT _SFR_MEM8(0x0005) -#define VPORTB_IN _SFR_MEM8(0x0006) -#define VPORTB_INTFLAGS _SFR_MEM8(0x0007) - - -/* VPORT (VPORTC) - Virtual Ports */ -#define VPORTC_DIR _SFR_MEM8(0x0008) -#define VPORTC_OUT _SFR_MEM8(0x0009) -#define VPORTC_IN _SFR_MEM8(0x000A) -#define VPORTC_INTFLAGS _SFR_MEM8(0x000B) - - -/* VPORT (VPORTD) - Virtual Ports */ -#define VPORTD_DIR _SFR_MEM8(0x000C) -#define VPORTD_OUT _SFR_MEM8(0x000D) -#define VPORTD_IN _SFR_MEM8(0x000E) -#define VPORTD_INTFLAGS _SFR_MEM8(0x000F) - - -/* VPORT (VPORTE) - Virtual Ports */ -#define VPORTE_DIR _SFR_MEM8(0x0010) -#define VPORTE_OUT _SFR_MEM8(0x0011) -#define VPORTE_IN _SFR_MEM8(0x0012) -#define VPORTE_INTFLAGS _SFR_MEM8(0x0013) - - -/* VPORT (VPORTF) - Virtual Ports */ -#define VPORTF_DIR _SFR_MEM8(0x0014) -#define VPORTF_OUT _SFR_MEM8(0x0015) -#define VPORTF_IN _SFR_MEM8(0x0016) -#define VPORTF_INTFLAGS _SFR_MEM8(0x0017) - - -/* GPIO - General Purpose IO */ -#define GPIO_GPIOR0 _SFR_MEM8(0x001C) -#define GPIO_GPIOR1 _SFR_MEM8(0x001D) -#define GPIO_GPIOR2 _SFR_MEM8(0x001E) -#define GPIO_GPIOR3 _SFR_MEM8(0x001F) - - -/* Deprecated */ -#define GPIO_GPIO0 _SFR_MEM8(0x001C) -#define GPIO_GPIO1 _SFR_MEM8(0x001D) -#define GPIO_GPIO2 _SFR_MEM8(0x001E) -#define GPIO_GPIO3 _SFR_MEM8(0x001F) - - -/* CPU - CPU */ -#define CPU_CCP _SFR_MEM8(0x0034) -#define CPU_RAMPZ _SFR_MEM8(0x003B) -#define CPU_SPL _SFR_MEM8(0x003D) -#define CPU_SPH _SFR_MEM8(0x003E) -#define CPU_SREG _SFR_MEM8(0x003F) - - -/* RSTCTRL - Reset controller */ -#define RSTCTRL_RSTFR _SFR_MEM8(0x0040) -#define RSTCTRL_SWRR _SFR_MEM8(0x0041) - - -/* SLPCTRL - Sleep Controller */ -#define SLPCTRL_CTRLA _SFR_MEM8(0x0050) - - -/* CLKCTRL - Clock controller */ -#define CLKCTRL_MCLKCTRLA _SFR_MEM8(0x0060) -#define CLKCTRL_MCLKCTRLB _SFR_MEM8(0x0061) -#define CLKCTRL_MCLKLOCK _SFR_MEM8(0x0062) -#define CLKCTRL_MCLKSTATUS _SFR_MEM8(0x0063) -#define CLKCTRL_OSC20MCTRLA _SFR_MEM8(0x0070) -#define CLKCTRL_OSC20MCALIBA _SFR_MEM8(0x0071) -#define CLKCTRL_OSC20MCALIBB _SFR_MEM8(0x0072) -#define CLKCTRL_OSC32KCTRLA _SFR_MEM8(0x0078) -#define CLKCTRL_OSC32KCALIB _SFR_MEM8(0x0079) -#define CLKCTRL_XOSC32KCTRLA _SFR_MEM8(0x007C) - - -/* BOD - Bod interface */ -#define BOD_CTRLA _SFR_MEM8(0x0080) -#define BOD_CTRLB _SFR_MEM8(0x0081) -#define BOD_VLMCTRLA _SFR_MEM8(0x0088) -#define BOD_INTCTRL _SFR_MEM8(0x0089) -#define BOD_INTFLAGS _SFR_MEM8(0x008A) -#define BOD_STATUS _SFR_MEM8(0x008B) - - -/* VREF - Voltage reference */ -#define VREF_CTRLA _SFR_MEM8(0x00A0) -#define VREF_CTRLB _SFR_MEM8(0x00A1) - - -/* NVMBIST - BIST in the NVMCTRL module */ -#define NVMBIST_CTRLA _SFR_MEM8(0x00C0) -#define NVMBIST_ADDRPAT _SFR_MEM8(0x00C1) -#define NVMBIST_DATAPAT _SFR_MEM8(0x00C2) -#define NVMBIST_STATUS _SFR_MEM8(0x00C3) -#define NVMBIST_CNT _SFR_MEM16(0x00C4) -#define NVMBIST_CNTL _SFR_MEM8(0x00C4) -#define NVMBIST_CNTH _SFR_MEM8(0x00C5) -#define NVMBIST_END _SFR_MEM32(0x00C6) -#define NVMBIST_END0 _SFR_MEM8(0x00C6) -#define NVMBIST_END1 _SFR_MEM8(0x00C7) -#define NVMBIST_END2 _SFR_MEM8(0x00C8) -#define NVMBIST_END3 _SFR_MEM8(0x00C9) - - -/* WDT - Watch-Dog Timer */ -#define WDT_CTRLA _SFR_MEM8(0x0100) -#define WDT_STATUS _SFR_MEM8(0x0101) - - -/* CPUINT - Interrupt Controller */ -#define CPUINT_CTRLA _SFR_MEM8(0x0110) -#define CPUINT_STATUS _SFR_MEM8(0x0111) -#define CPUINT_LVL0PRI _SFR_MEM8(0x0112) -#define CPUINT_LVL1VEC _SFR_MEM8(0x0113) - - -/* CRCSCAN - CRCSCAN */ -#define CRCSCAN_CTRLA _SFR_MEM8(0x0120) -#define CRCSCAN_CTRLB _SFR_MEM8(0x0121) -#define CRCSCAN_STATUS _SFR_MEM8(0x0122) - - -/* RTC - Real-Time Counter */ -#define RTC_CTRLA _SFR_MEM8(0x0140) -#define RTC_STATUS _SFR_MEM8(0x0141) -#define RTC_INTCTRL _SFR_MEM8(0x0142) -#define RTC_INTFLAGS _SFR_MEM8(0x0143) -#define RTC_TEMP _SFR_MEM8(0x0144) -#define RTC_DBGCTRL _SFR_MEM8(0x0145) -#define RTC_CLKSEL _SFR_MEM8(0x0147) -#define RTC_CNT _SFR_MEM16(0x0148) -#define RTC_CNTL _SFR_MEM8(0x0148) -#define RTC_CNTH _SFR_MEM8(0x0149) -#define RTC_PER _SFR_MEM16(0x014A) -#define RTC_PERL _SFR_MEM8(0x014A) -#define RTC_PERH _SFR_MEM8(0x014B) -#define RTC_CMP _SFR_MEM16(0x014C) -#define RTC_CMPL _SFR_MEM8(0x014C) -#define RTC_CMPH _SFR_MEM8(0x014D) -#define RTC_PITCTRLA _SFR_MEM8(0x0150) -#define RTC_PITSTATUS _SFR_MEM8(0x0151) -#define RTC_PITINTCTRL _SFR_MEM8(0x0152) -#define RTC_PITINTFLAGS _SFR_MEM8(0x0153) -#define RTC_PITDBGCTRL _SFR_MEM8(0x0155) - - -/* EVSYS - Event System */ -#define EVSYS_STROBE _SFR_MEM8(0x0180) -#define EVSYS_CHANNEL0 _SFR_MEM8(0x0190) -#define EVSYS_CHANNEL1 _SFR_MEM8(0x0191) -#define EVSYS_CHANNEL2 _SFR_MEM8(0x0192) -#define EVSYS_CHANNEL3 _SFR_MEM8(0x0193) -#define EVSYS_CHANNEL4 _SFR_MEM8(0x0194) -#define EVSYS_CHANNEL5 _SFR_MEM8(0x0195) -#define EVSYS_USERCCLLUT0A _SFR_MEM8(0x01A0) -#define EVSYS_USERCCLLUT0B _SFR_MEM8(0x01A1) -#define EVSYS_USERCCLLUT1A _SFR_MEM8(0x01A2) -#define EVSYS_USERCCLLUT1B _SFR_MEM8(0x01A3) -#define EVSYS_USERCCLLUT2A _SFR_MEM8(0x01A4) -#define EVSYS_USERCCLLUT2B _SFR_MEM8(0x01A5) -#define EVSYS_USERCCLLUT3A _SFR_MEM8(0x01A6) -#define EVSYS_USERCCLLUT3B _SFR_MEM8(0x01A7) -#define EVSYS_USERADC0 _SFR_MEM8(0x01A8) -#define EVSYS_USEREVOUTA _SFR_MEM8(0x01A9) -#define EVSYS_USEREVOUTB _SFR_MEM8(0x01AA) -#define EVSYS_USEREVOUTC _SFR_MEM8(0x01AB) -#define EVSYS_USEREVOUTD _SFR_MEM8(0x01AC) -#define EVSYS_USEREVOUTE _SFR_MEM8(0x01AD) -#define EVSYS_USEREVOUTF _SFR_MEM8(0x01AE) -#define EVSYS_USERUSART0 _SFR_MEM8(0x01AF) -#define EVSYS_USERUSART1 _SFR_MEM8(0x01B0) -#define EVSYS_USERUSART2 _SFR_MEM8(0x01B1) -#define EVSYS_USERUSART3 _SFR_MEM8(0x01B2) -#define EVSYS_USERTCA0 _SFR_MEM8(0x01B3) -#define EVSYS_USERTCB0 _SFR_MEM8(0x01B4) -#define EVSYS_USERTCB1 _SFR_MEM8(0x01B5) -#define EVSYS_USERTCB2 _SFR_MEM8(0x01B6) -#define EVSYS_USERTCB3 _SFR_MEM8(0x01B7) - - -/* CCL - Configurable Custom Logic */ -#define CCL_CTRLA _SFR_MEM8(0x01C0) -#define CCL_SEQCTRL0 _SFR_MEM8(0x01C1) -#define CCL_INTCTRL0 _SFR_MEM8(0x01C5) -#define CCL_INTFLAGS _SFR_MEM8(0x01C7) -#define CCL_LUT0CTRLA _SFR_MEM8(0x01C8) -#define CCL_LUT0CTRLB _SFR_MEM8(0x01C9) -#define CCL_LUT0CTRLC _SFR_MEM8(0x01CA) -#define CCL_TRUTH0 _SFR_MEM8(0x01CB) -#define CCL_LUT1CTRLA _SFR_MEM8(0x01CC) -#define CCL_LUT1CTRLB _SFR_MEM8(0x01CD) -#define CCL_LUT1CTRLC _SFR_MEM8(0x01CE) -#define CCL_TRUTH1 _SFR_MEM8(0x01CF) -#define CCL_LUT2CTRLA _SFR_MEM8(0x01D0) -#define CCL_LUT2CTRLB _SFR_MEM8(0x01D1) -#define CCL_LUT2CTRLC _SFR_MEM8(0x01D2) -#define CCL_TRUTH2 _SFR_MEM8(0x01D3) -#define CCL_LUT3CTRLA _SFR_MEM8(0x01D4) -#define CCL_LUT3CTRLB _SFR_MEM8(0x01D5) -#define CCL_LUT3CTRLC _SFR_MEM8(0x01D6) -#define CCL_TRUTH3 _SFR_MEM8(0x01D7) - - -/* PORT (PORTA) - I/O Ports */ -#define PORTA_DIR _SFR_MEM8(0x0400) -#define PORTA_DIRSET _SFR_MEM8(0x0401) -#define PORTA_DIRCLR _SFR_MEM8(0x0402) -#define PORTA_DIRTGL _SFR_MEM8(0x0403) -#define PORTA_OUT _SFR_MEM8(0x0404) -#define PORTA_OUTSET _SFR_MEM8(0x0405) -#define PORTA_OUTCLR _SFR_MEM8(0x0406) -#define PORTA_OUTTGL _SFR_MEM8(0x0407) -#define PORTA_IN _SFR_MEM8(0x0408) -#define PORTA_INTFLAGS _SFR_MEM8(0x0409) -#define PORTA_PORTCTRL _SFR_MEM8(0x040A) -#define PORTA_PIN0CTRL _SFR_MEM8(0x0410) -#define PORTA_PIN1CTRL _SFR_MEM8(0x0411) -#define PORTA_PIN2CTRL _SFR_MEM8(0x0412) -#define PORTA_PIN3CTRL _SFR_MEM8(0x0413) -#define PORTA_PIN4CTRL _SFR_MEM8(0x0414) -#define PORTA_PIN5CTRL _SFR_MEM8(0x0415) -#define PORTA_PIN6CTRL _SFR_MEM8(0x0416) -#define PORTA_PIN7CTRL _SFR_MEM8(0x0417) - - -/* PORT (PORTB) - I/O Ports */ -#define PORTB_DIR _SFR_MEM8(0x0420) -#define PORTB_DIRSET _SFR_MEM8(0x0421) -#define PORTB_DIRCLR _SFR_MEM8(0x0422) -#define PORTB_DIRTGL _SFR_MEM8(0x0423) -#define PORTB_OUT _SFR_MEM8(0x0424) -#define PORTB_OUTSET _SFR_MEM8(0x0425) -#define PORTB_OUTCLR _SFR_MEM8(0x0426) -#define PORTB_OUTTGL _SFR_MEM8(0x0427) -#define PORTB_IN _SFR_MEM8(0x0428) -#define PORTB_INTFLAGS _SFR_MEM8(0x0429) -#define PORTB_PORTCTRL _SFR_MEM8(0x042A) -#define PORTB_PIN0CTRL _SFR_MEM8(0x0430) -#define PORTB_PIN1CTRL _SFR_MEM8(0x0431) -#define PORTB_PIN2CTRL _SFR_MEM8(0x0432) -#define PORTB_PIN3CTRL _SFR_MEM8(0x0433) -#define PORTB_PIN4CTRL _SFR_MEM8(0x0434) -#define PORTB_PIN5CTRL _SFR_MEM8(0x0435) -#define PORTB_PIN6CTRL _SFR_MEM8(0x0436) -#define PORTB_PIN7CTRL _SFR_MEM8(0x0437) - - -/* PORT (PORTC) - I/O Ports */ -#define PORTC_DIR _SFR_MEM8(0x0440) -#define PORTC_DIRSET _SFR_MEM8(0x0441) -#define PORTC_DIRCLR _SFR_MEM8(0x0442) -#define PORTC_DIRTGL _SFR_MEM8(0x0443) -#define PORTC_OUT _SFR_MEM8(0x0444) -#define PORTC_OUTSET _SFR_MEM8(0x0445) -#define PORTC_OUTCLR _SFR_MEM8(0x0446) -#define PORTC_OUTTGL _SFR_MEM8(0x0447) -#define PORTC_IN _SFR_MEM8(0x0448) -#define PORTC_INTFLAGS _SFR_MEM8(0x0449) -#define PORTC_PORTCTRL _SFR_MEM8(0x044A) -#define PORTC_PIN0CTRL _SFR_MEM8(0x0450) -#define PORTC_PIN1CTRL _SFR_MEM8(0x0451) -#define PORTC_PIN2CTRL _SFR_MEM8(0x0452) -#define PORTC_PIN3CTRL _SFR_MEM8(0x0453) -#define PORTC_PIN4CTRL _SFR_MEM8(0x0454) -#define PORTC_PIN5CTRL _SFR_MEM8(0x0455) -#define PORTC_PIN6CTRL _SFR_MEM8(0x0456) -#define PORTC_PIN7CTRL _SFR_MEM8(0x0457) - - -/* PORT (PORTD) - I/O Ports */ -#define PORTD_DIR _SFR_MEM8(0x0460) -#define PORTD_DIRSET _SFR_MEM8(0x0461) -#define PORTD_DIRCLR _SFR_MEM8(0x0462) -#define PORTD_DIRTGL _SFR_MEM8(0x0463) -#define PORTD_OUT _SFR_MEM8(0x0464) -#define PORTD_OUTSET _SFR_MEM8(0x0465) -#define PORTD_OUTCLR _SFR_MEM8(0x0466) -#define PORTD_OUTTGL _SFR_MEM8(0x0467) -#define PORTD_IN _SFR_MEM8(0x0468) -#define PORTD_INTFLAGS _SFR_MEM8(0x0469) -#define PORTD_PORTCTRL _SFR_MEM8(0x046A) -#define PORTD_PIN0CTRL _SFR_MEM8(0x0470) -#define PORTD_PIN1CTRL _SFR_MEM8(0x0471) -#define PORTD_PIN2CTRL _SFR_MEM8(0x0472) -#define PORTD_PIN3CTRL _SFR_MEM8(0x0473) -#define PORTD_PIN4CTRL _SFR_MEM8(0x0474) -#define PORTD_PIN5CTRL _SFR_MEM8(0x0475) -#define PORTD_PIN6CTRL _SFR_MEM8(0x0476) -#define PORTD_PIN7CTRL _SFR_MEM8(0x0477) - - -/* PORT (PORTE) - I/O Ports */ -#define PORTE_DIR _SFR_MEM8(0x0480) -#define PORTE_DIRSET _SFR_MEM8(0x0481) -#define PORTE_DIRCLR _SFR_MEM8(0x0482) -#define PORTE_DIRTGL _SFR_MEM8(0x0483) -#define PORTE_OUT _SFR_MEM8(0x0484) -#define PORTE_OUTSET _SFR_MEM8(0x0485) -#define PORTE_OUTCLR _SFR_MEM8(0x0486) -#define PORTE_OUTTGL _SFR_MEM8(0x0487) -#define PORTE_IN _SFR_MEM8(0x0488) -#define PORTE_INTFLAGS _SFR_MEM8(0x0489) -#define PORTE_PORTCTRL _SFR_MEM8(0x048A) -#define PORTE_PIN0CTRL _SFR_MEM8(0x0490) -#define PORTE_PIN1CTRL _SFR_MEM8(0x0491) -#define PORTE_PIN2CTRL _SFR_MEM8(0x0492) -#define PORTE_PIN3CTRL _SFR_MEM8(0x0493) -#define PORTE_PIN4CTRL _SFR_MEM8(0x0494) -#define PORTE_PIN5CTRL _SFR_MEM8(0x0495) -#define PORTE_PIN6CTRL _SFR_MEM8(0x0496) -#define PORTE_PIN7CTRL _SFR_MEM8(0x0497) - - -/* PORT (PORTF) - I/O Ports */ -#define PORTF_DIR _SFR_MEM8(0x04A0) -#define PORTF_DIRSET _SFR_MEM8(0x04A1) -#define PORTF_DIRCLR _SFR_MEM8(0x04A2) -#define PORTF_DIRTGL _SFR_MEM8(0x04A3) -#define PORTF_OUT _SFR_MEM8(0x04A4) -#define PORTF_OUTSET _SFR_MEM8(0x04A5) -#define PORTF_OUTCLR _SFR_MEM8(0x04A6) -#define PORTF_OUTTGL _SFR_MEM8(0x04A7) -#define PORTF_IN _SFR_MEM8(0x04A8) -#define PORTF_INTFLAGS _SFR_MEM8(0x04A9) -#define PORTF_PORTCTRL _SFR_MEM8(0x04AA) -#define PORTF_PIN0CTRL _SFR_MEM8(0x04B0) -#define PORTF_PIN1CTRL _SFR_MEM8(0x04B1) -#define PORTF_PIN2CTRL _SFR_MEM8(0x04B2) -#define PORTF_PIN3CTRL _SFR_MEM8(0x04B3) -#define PORTF_PIN4CTRL _SFR_MEM8(0x04B4) -#define PORTF_PIN5CTRL _SFR_MEM8(0x04B5) -#define PORTF_PIN6CTRL _SFR_MEM8(0x04B6) -#define PORTF_PIN7CTRL _SFR_MEM8(0x04B7) - - -/* PORTMUX - Port Multiplexer */ -#define PORTMUX_EVSYSROUTEA _SFR_MEM8(0x05E0) -#define PORTMUX_CCLROUTEA _SFR_MEM8(0x05E1) -#define PORTMUX_USARTROUTEA _SFR_MEM8(0x05E2) -#define PORTMUX_TWISPIROUTEA _SFR_MEM8(0x05E3) -#define PORTMUX_TCAROUTEA _SFR_MEM8(0x05E4) -#define PORTMUX_TCBROUTEA _SFR_MEM8(0x05E5) - - -/* ADC (ADC0) - Analog to Digital Converter */ -#define ADC0_CTRLA _SFR_MEM8(0x0600) -#define ADC0_CTRLB _SFR_MEM8(0x0601) -#define ADC0_CTRLC _SFR_MEM8(0x0602) -#define ADC0_CTRLD _SFR_MEM8(0x0603) -#define ADC0_CTRLE _SFR_MEM8(0x0604) -#define ADC0_SAMPCTRL _SFR_MEM8(0x0605) -#define ADC0_MUXPOS _SFR_MEM8(0x0606) -#define ADC0_COMMAND _SFR_MEM8(0x0608) -#define ADC0_EVCTRL _SFR_MEM8(0x0609) -#define ADC0_INTCTRL _SFR_MEM8(0x060A) -#define ADC0_INTFLAGS _SFR_MEM8(0x060B) -#define ADC0_DBGCTRL _SFR_MEM8(0x060C) -#define ADC0_TEMP _SFR_MEM8(0x060D) -#define ADC0_RES _SFR_MEM16(0x0610) -#define ADC0_RESL _SFR_MEM8(0x0610) -#define ADC0_RESH _SFR_MEM8(0x0611) -#define ADC0_WINLT _SFR_MEM16(0x0612) -#define ADC0_WINLTL _SFR_MEM8(0x0612) -#define ADC0_WINLTH _SFR_MEM8(0x0613) -#define ADC0_WINHT _SFR_MEM16(0x0614) -#define ADC0_WINHTL _SFR_MEM8(0x0614) -#define ADC0_WINHTH _SFR_MEM8(0x0615) -#define ADC0_CALIB _SFR_MEM8(0x0616) - - -/* AC (AC0) - Analog Comparator */ -#define AC0_CTRLA _SFR_MEM8(0x0680) -#define AC0_MUXCTRLA _SFR_MEM8(0x0682) -#define AC0_DACREF _SFR_MEM8(0x0684) -#define AC0_INTCTRL _SFR_MEM8(0x0686) -#define AC0_STATUS _SFR_MEM8(0x0687) - - -/* USART (USART0) - Universal Synchronous and Asynchronous Receiver and Transmitter */ -#define USART0_RXDATAL _SFR_MEM8(0x0800) -#define USART0_RXDATAH _SFR_MEM8(0x0801) -#define USART0_TXDATAL _SFR_MEM8(0x0802) -#define USART0_TXDATAH _SFR_MEM8(0x0803) -#define USART0_STATUS _SFR_MEM8(0x0804) -#define USART0_CTRLA _SFR_MEM8(0x0805) -#define USART0_CTRLB _SFR_MEM8(0x0806) -#define USART0_CTRLC _SFR_MEM8(0x0807) -#define USART0_BAUD _SFR_MEM16(0x0808) -#define USART0_BAUDL _SFR_MEM8(0x0808) -#define USART0_BAUDH _SFR_MEM8(0x0809) -#define USART0_CTRLD _SFR_MEM8(0x080A) -#define USART0_DBGCTRL _SFR_MEM8(0x080B) -#define USART0_EVCTRL _SFR_MEM8(0x080C) -#define USART0_TXPLCTRL _SFR_MEM8(0x080D) -#define USART0_RXPLCTRL _SFR_MEM8(0x080E) - - -/* USART (USART1) - Universal Synchronous and Asynchronous Receiver and Transmitter */ -#define USART1_RXDATAL _SFR_MEM8(0x0820) -#define USART1_RXDATAH _SFR_MEM8(0x0821) -#define USART1_TXDATAL _SFR_MEM8(0x0822) -#define USART1_TXDATAH _SFR_MEM8(0x0823) -#define USART1_STATUS _SFR_MEM8(0x0824) -#define USART1_CTRLA _SFR_MEM8(0x0825) -#define USART1_CTRLB _SFR_MEM8(0x0826) -#define USART1_CTRLC _SFR_MEM8(0x0827) -#define USART1_BAUD _SFR_MEM16(0x0828) -#define USART1_BAUDL _SFR_MEM8(0x0828) -#define USART1_BAUDH _SFR_MEM8(0x0829) -#define USART1_CTRLD _SFR_MEM8(0x082A) -#define USART1_DBGCTRL _SFR_MEM8(0x082B) -#define USART1_EVCTRL _SFR_MEM8(0x082C) -#define USART1_TXPLCTRL _SFR_MEM8(0x082D) -#define USART1_RXPLCTRL _SFR_MEM8(0x082E) - - -/* TWI (TWI0) - Two-Wire Interface */ -#define TWI0_CTRLA _SFR_MEM8(0x08A0) -#define TWI0_BRIDGECTRL _SFR_MEM8(0x08A1) -#define TWI0_DBGCTRL _SFR_MEM8(0x08A2) -#define TWI0_MCTRLA _SFR_MEM8(0x08A3) -#define TWI0_MCTRLB _SFR_MEM8(0x08A4) -#define TWI0_MSTATUS _SFR_MEM8(0x08A5) -#define TWI0_MBAUD _SFR_MEM8(0x08A6) -#define TWI0_MADDR _SFR_MEM8(0x08A7) -#define TWI0_MDATA _SFR_MEM8(0x08A8) -#define TWI0_SCTRLA _SFR_MEM8(0x08A9) -#define TWI0_SCTRLB _SFR_MEM8(0x08AA) -#define TWI0_SSTATUS _SFR_MEM8(0x08AB) -#define TWI0_SADDR _SFR_MEM8(0x08AC) -#define TWI0_SDATA _SFR_MEM8(0x08AD) -#define TWI0_SADDRMASK _SFR_MEM8(0x08AE) - - -/* SPI (SPI0) - Serial Peripheral Interface */ -#define SPI0_CTRLA _SFR_MEM8(0x08C0) -#define SPI0_CTRLB _SFR_MEM8(0x08C1) -#define SPI0_INTCTRL _SFR_MEM8(0x08C2) -#define SPI0_INTFLAGS _SFR_MEM8(0x08C3) -#define SPI0_DATA _SFR_MEM8(0x08C4) - - -/* TCA (TCA0) - 16-bit Timer/Counter Type A */ -#define TCA0_SINGLE_CTRLA _SFR_MEM8(0x0A00) -#define TCA0_SINGLE_CTRLB _SFR_MEM8(0x0A01) -#define TCA0_SINGLE_CTRLC _SFR_MEM8(0x0A02) -#define TCA0_SINGLE_CTRLD _SFR_MEM8(0x0A03) -#define TCA0_SINGLE_CTRLECLR _SFR_MEM8(0x0A04) -#define TCA0_SINGLE_CTRLESET _SFR_MEM8(0x0A05) -#define TCA0_SINGLE_CTRLFCLR _SFR_MEM8(0x0A06) -#define TCA0_SINGLE_CTRLFSET _SFR_MEM8(0x0A07) -#define TCA0_SINGLE_EVCTRL _SFR_MEM8(0x0A09) -#define TCA0_SINGLE_INTCTRL _SFR_MEM8(0x0A0A) -#define TCA0_SINGLE_INTFLAGS _SFR_MEM8(0x0A0B) -#define TCA0_SINGLE_DBGCTRL _SFR_MEM8(0x0A0E) -#define TCA0_SINGLE_TEMP _SFR_MEM8(0x0A0F) -#define TCA0_SINGLE_CNT _SFR_MEM16(0x0A20) -#define TCA0_SINGLE_PER _SFR_MEM16(0x0A26) -#define TCA0_SINGLE_CMP0 _SFR_MEM16(0x0A28) -#define TCA0_SINGLE_CMP1 _SFR_MEM16(0x0A2A) -#define TCA0_SINGLE_CMP2 _SFR_MEM16(0x0A2C) -#define TCA0_SINGLE_PERBUF _SFR_MEM16(0x0A36) -#define TCA0_SINGLE_CMP0BUF _SFR_MEM16(0x0A38) -#define TCA0_SINGLE_CMP1BUF _SFR_MEM16(0x0A3A) -#define TCA0_SINGLE_CMP2BUF _SFR_MEM16(0x0A3C) - - -#define TCA0_SPLIT_CTRLA _SFR_MEM8(0x0A00) -#define TCA0_SPLIT_CTRLB _SFR_MEM8(0x0A01) -#define TCA0_SPLIT_CTRLC _SFR_MEM8(0x0A02) -#define TCA0_SPLIT_CTRLD _SFR_MEM8(0x0A03) -#define TCA0_SPLIT_CTRLECLR _SFR_MEM8(0x0A04) -#define TCA0_SPLIT_CTRLESET _SFR_MEM8(0x0A05) -#define TCA0_SPLIT_INTCTRL _SFR_MEM8(0x0A0A) -#define TCA0_SPLIT_INTFLAGS _SFR_MEM8(0x0A0B) -#define TCA0_SPLIT_DBGCTRL _SFR_MEM8(0x0A0E) -#define TCA0_SPLIT_LCNT _SFR_MEM8(0x0A20) -#define TCA0_SPLIT_HCNT _SFR_MEM8(0x0A21) -#define TCA0_SPLIT_LPER _SFR_MEM8(0x0A26) -#define TCA0_SPLIT_HPER _SFR_MEM8(0x0A27) -#define TCA0_SPLIT_LCMP0 _SFR_MEM8(0x0A28) -#define TCA0_SPLIT_HCMP0 _SFR_MEM8(0x0A29) -#define TCA0_SPLIT_LCMP1 _SFR_MEM8(0x0A2A) -#define TCA0_SPLIT_HCMP1 _SFR_MEM8(0x0A2B) -#define TCA0_SPLIT_LCMP2 _SFR_MEM8(0x0A2C) -#define TCA0_SPLIT_HCMP2 _SFR_MEM8(0x0A2D) - - - - -/* TCB (TCB0) - 16-bit Timer Type B */ -#define TCB0_CTRLA _SFR_MEM8(0x0A80) -#define TCB0_CTRLB _SFR_MEM8(0x0A81) -#define TCB0_EVCTRL _SFR_MEM8(0x0A84) -#define TCB0_INTCTRL _SFR_MEM8(0x0A85) -#define TCB0_INTFLAGS _SFR_MEM8(0x0A86) -#define TCB0_STATUS _SFR_MEM8(0x0A87) -#define TCB0_DBGCTRL _SFR_MEM8(0x0A88) -#define TCB0_TEMP _SFR_MEM8(0x0A89) -#define TCB0_CNT _SFR_MEM16(0x0A8A) -#define TCB0_CNTL _SFR_MEM8(0x0A8A) -#define TCB0_CNTH _SFR_MEM8(0x0A8B) -#define TCB0_CCMP _SFR_MEM16(0x0A8C) -#define TCB0_CCMPL _SFR_MEM8(0x0A8C) -#define TCB0_CCMPH _SFR_MEM8(0x0A8D) - - -/* TCB (TCB1) - 16-bit Timer Type B */ -#define TCB1_CTRLA _SFR_MEM8(0x0A90) -#define TCB1_CTRLB _SFR_MEM8(0x0A91) -#define TCB1_EVCTRL _SFR_MEM8(0x0A94) -#define TCB1_INTCTRL _SFR_MEM8(0x0A95) -#define TCB1_INTFLAGS _SFR_MEM8(0x0A96) -#define TCB1_STATUS _SFR_MEM8(0x0A97) -#define TCB1_DBGCTRL _SFR_MEM8(0x0A98) -#define TCB1_TEMP _SFR_MEM8(0x0A99) -#define TCB1_CNT _SFR_MEM16(0x0A9A) -#define TCB1_CNTL _SFR_MEM8(0x0A9A) -#define TCB1_CNTH _SFR_MEM8(0x0A9B) -#define TCB1_CCMP _SFR_MEM16(0x0A9C) -#define TCB1_CCMPL _SFR_MEM8(0x0A9C) -#define TCB1_CCMPH _SFR_MEM8(0x0A9D) - - -/* TCB (TCB2) - 16-bit Timer Type B */ -#define TCB2_CTRLA _SFR_MEM8(0x0AA0) -#define TCB2_CTRLB _SFR_MEM8(0x0AA1) -#define TCB2_EVCTRL _SFR_MEM8(0x0AA4) -#define TCB2_INTCTRL _SFR_MEM8(0x0AA5) -#define TCB2_INTFLAGS _SFR_MEM8(0x0AA6) -#define TCB2_STATUS _SFR_MEM8(0x0AA7) -#define TCB2_DBGCTRL _SFR_MEM8(0x0AA8) -#define TCB2_TEMP _SFR_MEM8(0x0AA9) -#define TCB2_CNT _SFR_MEM16(0x0AAA) -#define TCB2_CNTL _SFR_MEM8(0x0AAA) -#define TCB2_CNTH _SFR_MEM8(0x0AAB) -#define TCB2_CCMP _SFR_MEM16(0x0AAC) -#define TCB2_CCMPL _SFR_MEM8(0x0AAC) -#define TCB2_CCMPH _SFR_MEM8(0x0AAD) - - -/* SYSCFG - System Configuration Registers */ -#define SYSCFG_REVID _SFR_MEM8(0x0F01) -#define SYSCFG_EXTBRK _SFR_MEM8(0x0F02) -#define SYSCFG_OCDM _SFR_MEM8(0x0F18) -#define SYSCFG_OCDMS _SFR_MEM8(0x0F19) - - -/* NVMCTRL - Non-volatile Memory Controller */ -#define NVMCTRL_CTRLA _SFR_MEM8(0x1000) -#define NVMCTRL_CTRLB _SFR_MEM8(0x1001) -#define NVMCTRL_STATUS _SFR_MEM8(0x1002) -#define NVMCTRL_INTCTRL _SFR_MEM8(0x1003) -#define NVMCTRL_INTFLAGS _SFR_MEM8(0x1004) -#define NVMCTRL_DATA _SFR_MEM16(0x1006) -#define NVMCTRL_DATAL _SFR_MEM8(0x1006) -#define NVMCTRL_DATAH _SFR_MEM8(0x1007) -#define NVMCTRL_ADDR _SFR_MEM16(0x1008) -#define NVMCTRL_ADDRL _SFR_MEM8(0x1008) -#define NVMCTRL_ADDRH _SFR_MEM8(0x1009) - - -/* SIGROW - Signature row */ -#define SIGROW_DEVICEID0 _SFR_MEM8(0x1100) -#define SIGROW_DEVICEID1 _SFR_MEM8(0x1101) -#define SIGROW_DEVICEID2 _SFR_MEM8(0x1102) -#define SIGROW_SERNUM0 _SFR_MEM8(0x1103) -#define SIGROW_SERNUM1 _SFR_MEM8(0x1104) -#define SIGROW_SERNUM2 _SFR_MEM8(0x1105) -#define SIGROW_SERNUM3 _SFR_MEM8(0x1106) -#define SIGROW_SERNUM4 _SFR_MEM8(0x1107) -#define SIGROW_SERNUM5 _SFR_MEM8(0x1108) -#define SIGROW_SERNUM6 _SFR_MEM8(0x1109) -#define SIGROW_SERNUM7 _SFR_MEM8(0x110A) -#define SIGROW_SERNUM8 _SFR_MEM8(0x110B) -#define SIGROW_SERNUM9 _SFR_MEM8(0x110C) -#define SIGROW_OSCCAL32K _SFR_MEM8(0x1114) -#define SIGROW_OSCCAL16M0 _SFR_MEM8(0x1118) -#define SIGROW_OSCCAL16M1 _SFR_MEM8(0x1119) -#define SIGROW_OSCCAL20M0 _SFR_MEM8(0x111A) -#define SIGROW_OSCCAL20M1 _SFR_MEM8(0x111B) -#define SIGROW_TEMPSENSE0 _SFR_MEM8(0x1120) -#define SIGROW_TEMPSENSE1 _SFR_MEM8(0x1121) -#define SIGROW_OSC16ERR3V _SFR_MEM8(0x1122) -#define SIGROW_OSC16ERR5V _SFR_MEM8(0x1123) -#define SIGROW_OSC20ERR3V _SFR_MEM8(0x1124) -#define SIGROW_OSC20ERR5V _SFR_MEM8(0x1125) -#define SIGROW_CHECKSUM1 _SFR_MEM8(0x112F) - - -/* FUSE - Fuses */ -#define FUSE_WDTCFG _SFR_MEM8(0x1280) -#define FUSE_BODCFG _SFR_MEM8(0x1281) -#define FUSE_OSCCFG _SFR_MEM8(0x1282) -#define FUSE_TCD0CFG _SFR_MEM8(0x1284) -#define FUSE_SYSCFG0 _SFR_MEM8(0x1285) -#define FUSE_SYSCFG1 _SFR_MEM8(0x1286) -#define FUSE_APPEND _SFR_MEM8(0x1287) -#define FUSE_BOOTEND _SFR_MEM8(0x1288) - - -/* LOCKBIT - Lockbit */ -#define LOCKBIT_LOCKBIT _SFR_MEM8(0x128A) - - -/* USERROW - User Row */ -#define USERROW_USERROW0 _SFR_MEM8(0x1300) -#define USERROW_USERROW1 _SFR_MEM8(0x1301) -#define USERROW_USERROW2 _SFR_MEM8(0x1302) -#define USERROW_USERROW3 _SFR_MEM8(0x1303) -#define USERROW_USERROW4 _SFR_MEM8(0x1304) -#define USERROW_USERROW5 _SFR_MEM8(0x1305) -#define USERROW_USERROW6 _SFR_MEM8(0x1306) -#define USERROW_USERROW7 _SFR_MEM8(0x1307) -#define USERROW_USERROW8 _SFR_MEM8(0x1308) -#define USERROW_USERROW9 _SFR_MEM8(0x1309) -#define USERROW_USERROW10 _SFR_MEM8(0x130A) -#define USERROW_USERROW11 _SFR_MEM8(0x130B) -#define USERROW_USERROW12 _SFR_MEM8(0x130C) -#define USERROW_USERROW13 _SFR_MEM8(0x130D) -#define USERROW_USERROW14 _SFR_MEM8(0x130E) -#define USERROW_USERROW15 _SFR_MEM8(0x130F) -#define USERROW_USERROW16 _SFR_MEM8(0x1310) -#define USERROW_USERROW17 _SFR_MEM8(0x1311) -#define USERROW_USERROW18 _SFR_MEM8(0x1312) -#define USERROW_USERROW19 _SFR_MEM8(0x1313) -#define USERROW_USERROW20 _SFR_MEM8(0x1314) -#define USERROW_USERROW21 _SFR_MEM8(0x1315) -#define USERROW_USERROW22 _SFR_MEM8(0x1316) -#define USERROW_USERROW23 _SFR_MEM8(0x1317) -#define USERROW_USERROW24 _SFR_MEM8(0x1318) -#define USERROW_USERROW25 _SFR_MEM8(0x1319) -#define USERROW_USERROW26 _SFR_MEM8(0x131A) -#define USERROW_USERROW27 _SFR_MEM8(0x131B) -#define USERROW_USERROW28 _SFR_MEM8(0x131C) -#define USERROW_USERROW29 _SFR_MEM8(0x131D) -#define USERROW_USERROW30 _SFR_MEM8(0x131E) -#define USERROW_USERROW31 _SFR_MEM8(0x131F) -#define USERROW_USERROW32 _SFR_MEM8(0x1320) -#define USERROW_USERROW33 _SFR_MEM8(0x1321) -#define USERROW_USERROW34 _SFR_MEM8(0x1322) -#define USERROW_USERROW35 _SFR_MEM8(0x1323) -#define USERROW_USERROW36 _SFR_MEM8(0x1324) -#define USERROW_USERROW37 _SFR_MEM8(0x1325) -#define USERROW_USERROW38 _SFR_MEM8(0x1326) -#define USERROW_USERROW39 _SFR_MEM8(0x1327) -#define USERROW_USERROW40 _SFR_MEM8(0x1328) -#define USERROW_USERROW41 _SFR_MEM8(0x1329) -#define USERROW_USERROW42 _SFR_MEM8(0x132A) -#define USERROW_USERROW43 _SFR_MEM8(0x132B) -#define USERROW_USERROW44 _SFR_MEM8(0x132C) -#define USERROW_USERROW45 _SFR_MEM8(0x132D) -#define USERROW_USERROW46 _SFR_MEM8(0x132E) -#define USERROW_USERROW47 _SFR_MEM8(0x132F) -#define USERROW_USERROW48 _SFR_MEM8(0x1330) -#define USERROW_USERROW49 _SFR_MEM8(0x1331) -#define USERROW_USERROW50 _SFR_MEM8(0x1332) -#define USERROW_USERROW51 _SFR_MEM8(0x1333) -#define USERROW_USERROW52 _SFR_MEM8(0x1334) -#define USERROW_USERROW53 _SFR_MEM8(0x1335) -#define USERROW_USERROW54 _SFR_MEM8(0x1336) -#define USERROW_USERROW55 _SFR_MEM8(0x1337) -#define USERROW_USERROW56 _SFR_MEM8(0x1338) -#define USERROW_USERROW57 _SFR_MEM8(0x1339) -#define USERROW_USERROW58 _SFR_MEM8(0x133A) -#define USERROW_USERROW59 _SFR_MEM8(0x133B) -#define USERROW_USERROW60 _SFR_MEM8(0x133C) -#define USERROW_USERROW61 _SFR_MEM8(0x133D) -#define USERROW_USERROW62 _SFR_MEM8(0x133E) -#define USERROW_USERROW63 _SFR_MEM8(0x133F) - - - -/*================== Bitfield Definitions ================== */ - -/* AC - Analog Comparator */ -/* AC.CTRLA bit masks and bit positions */ -#define AC_ENABLE_bm 0x01 /* Enable bit mask. */ -#define AC_ENABLE_bp 0 /* Enable bit position. */ -#define AC_HYSMODE_gm 0x06 /* Hysteresis Mode group mask. */ -#define AC_HYSMODE_gp 1 /* Hysteresis Mode group position. */ -#define AC_HYSMODE0_bm (1<<1) /* Hysteresis Mode bit 0 mask. */ -#define AC_HYSMODE0_bp 1 /* Hysteresis Mode bit 0 position. */ -#define AC_HYSMODE1_bm (1<<2) /* Hysteresis Mode bit 1 mask. */ -#define AC_HYSMODE1_bp 2 /* Hysteresis Mode bit 1 position. */ -#define AC_LPMODE_bm 0x08 /* Low Power Mode bit mask. */ -#define AC_LPMODE_bp 3 /* Low Power Mode bit position. */ -#define AC_INTMODE_gm 0x30 /* Interrupt Mode group mask. */ -#define AC_INTMODE_gp 4 /* Interrupt Mode group position. */ -#define AC_INTMODE0_bm (1<<4) /* Interrupt Mode bit 0 mask. */ -#define AC_INTMODE0_bp 4 /* Interrupt Mode bit 0 position. */ -#define AC_INTMODE1_bm (1<<5) /* Interrupt Mode bit 1 mask. */ -#define AC_INTMODE1_bp 5 /* Interrupt Mode bit 1 position. */ -#define AC_OUTEN_bm 0x40 /* Output Buffer Enable bit mask. */ -#define AC_OUTEN_bp 6 /* Output Buffer Enable bit position. */ -#define AC_RUNSTDBY_bm 0x80 /* Run in Standby Mode bit mask. */ -#define AC_RUNSTDBY_bp 7 /* Run in Standby Mode bit position. */ - -/* AC.MUXCTRLA bit masks and bit positions */ -#define AC_MUXNEG_gm 0x03 /* Negative Input MUX Selection group mask. */ -#define AC_MUXNEG_gp 0 /* Negative Input MUX Selection group position. */ -#define AC_MUXNEG0_bm (1<<0) /* Negative Input MUX Selection bit 0 mask. */ -#define AC_MUXNEG0_bp 0 /* Negative Input MUX Selection bit 0 position. */ -#define AC_MUXNEG1_bm (1<<1) /* Negative Input MUX Selection bit 1 mask. */ -#define AC_MUXNEG1_bp 1 /* Negative Input MUX Selection bit 1 position. */ -#define AC_MUXPOS_gm 0x18 /* Positive Input MUX Selection group mask. */ -#define AC_MUXPOS_gp 3 /* Positive Input MUX Selection group position. */ -#define AC_MUXPOS0_bm (1<<3) /* Positive Input MUX Selection bit 0 mask. */ -#define AC_MUXPOS0_bp 3 /* Positive Input MUX Selection bit 0 position. */ -#define AC_MUXPOS1_bm (1<<4) /* Positive Input MUX Selection bit 1 mask. */ -#define AC_MUXPOS1_bp 4 /* Positive Input MUX Selection bit 1 position. */ -#define AC_INVERT_bm 0x80 /* Invert AC Output bit mask. */ -#define AC_INVERT_bp 7 /* Invert AC Output bit position. */ - -/* AC.DACREF bit masks and bit positions */ -#define AC_DATA_gm 0xFF /* DAC voltage reference group mask. */ -#define AC_DATA_gp 0 /* DAC voltage reference group position. */ -#define AC_DATA0_bm (1<<0) /* DAC voltage reference bit 0 mask. */ -#define AC_DATA0_bp 0 /* DAC voltage reference bit 0 position. */ -#define AC_DATA1_bm (1<<1) /* DAC voltage reference bit 1 mask. */ -#define AC_DATA1_bp 1 /* DAC voltage reference bit 1 position. */ -#define AC_DATA2_bm (1<<2) /* DAC voltage reference bit 2 mask. */ -#define AC_DATA2_bp 2 /* DAC voltage reference bit 2 position. */ -#define AC_DATA3_bm (1<<3) /* DAC voltage reference bit 3 mask. */ -#define AC_DATA3_bp 3 /* DAC voltage reference bit 3 position. */ -#define AC_DATA4_bm (1<<4) /* DAC voltage reference bit 4 mask. */ -#define AC_DATA4_bp 4 /* DAC voltage reference bit 4 position. */ -#define AC_DATA5_bm (1<<5) /* DAC voltage reference bit 5 mask. */ -#define AC_DATA5_bp 5 /* DAC voltage reference bit 5 position. */ -#define AC_DATA6_bm (1<<6) /* DAC voltage reference bit 6 mask. */ -#define AC_DATA6_bp 6 /* DAC voltage reference bit 6 position. */ -#define AC_DATA7_bm (1<<7) /* DAC voltage reference bit 7 mask. */ -#define AC_DATA7_bp 7 /* DAC voltage reference bit 7 position. */ - -/* AC.INTCTRL bit masks and bit positions */ -#define AC_CMP_bm 0x01 /* Analog Comparator 0 Interrupt Enable bit mask. */ -#define AC_CMP_bp 0 /* Analog Comparator 0 Interrupt Enable bit position. */ - -/* AC.STATUS bit masks and bit positions */ -/* AC_CMP is already defined. */ -#define AC_STATE_bm 0x10 /* Analog Comparator State bit mask. */ -#define AC_STATE_bp 4 /* Analog Comparator State bit position. */ - -/* ADC - Analog to Digital Converter */ -/* ADC.CTRLA bit masks and bit positions */ -#define ADC_ENABLE_bm 0x01 /* ADC Enable bit mask. */ -#define ADC_ENABLE_bp 0 /* ADC Enable bit position. */ -#define ADC_FREERUN_bm 0x02 /* ADC Freerun mode bit mask. */ -#define ADC_FREERUN_bp 1 /* ADC Freerun mode bit position. */ -#define ADC_RESSEL_bm 0x04 /* ADC Resolution bit mask. */ -#define ADC_RESSEL_bp 2 /* ADC Resolution bit position. */ -#define ADC_RUNSTBY_bm 0x80 /* Run standby mode bit mask. */ -#define ADC_RUNSTBY_bp 7 /* Run standby mode bit position. */ - -/* ADC.CTRLB bit masks and bit positions */ -#define ADC_SAMPNUM_gm 0x07 /* Accumulation Samples group mask. */ -#define ADC_SAMPNUM_gp 0 /* Accumulation Samples group position. */ -#define ADC_SAMPNUM0_bm (1<<0) /* Accumulation Samples bit 0 mask. */ -#define ADC_SAMPNUM0_bp 0 /* Accumulation Samples bit 0 position. */ -#define ADC_SAMPNUM1_bm (1<<1) /* Accumulation Samples bit 1 mask. */ -#define ADC_SAMPNUM1_bp 1 /* Accumulation Samples bit 1 position. */ -#define ADC_SAMPNUM2_bm (1<<2) /* Accumulation Samples bit 2 mask. */ -#define ADC_SAMPNUM2_bp 2 /* Accumulation Samples bit 2 position. */ - -/* ADC.CTRLC bit masks and bit positions */ -#define ADC_PRESC_gm 0x07 /* Clock Pre-scaler group mask. */ -#define ADC_PRESC_gp 0 /* Clock Pre-scaler group position. */ -#define ADC_PRESC0_bm (1<<0) /* Clock Pre-scaler bit 0 mask. */ -#define ADC_PRESC0_bp 0 /* Clock Pre-scaler bit 0 position. */ -#define ADC_PRESC1_bm (1<<1) /* Clock Pre-scaler bit 1 mask. */ -#define ADC_PRESC1_bp 1 /* Clock Pre-scaler bit 1 position. */ -#define ADC_PRESC2_bm (1<<2) /* Clock Pre-scaler bit 2 mask. */ -#define ADC_PRESC2_bp 2 /* Clock Pre-scaler bit 2 position. */ -#define ADC_REFSEL_gm 0x30 /* Reference Selection group mask. */ -#define ADC_REFSEL_gp 4 /* Reference Selection group position. */ -#define ADC_REFSEL0_bm (1<<4) /* Reference Selection bit 0 mask. */ -#define ADC_REFSEL0_bp 4 /* Reference Selection bit 0 position. */ -#define ADC_REFSEL1_bm (1<<5) /* Reference Selection bit 1 mask. */ -#define ADC_REFSEL1_bp 5 /* Reference Selection bit 1 position. */ -#define ADC_SAMPCAP_bm 0x40 /* Sample Capacitance Selection bit mask. */ -#define ADC_SAMPCAP_bp 6 /* Sample Capacitance Selection bit position. */ - -/* ADC.CTRLD bit masks and bit positions */ -#define ADC_SAMPDLY_gm 0x0F /* Sampling Delay Selection group mask. */ -#define ADC_SAMPDLY_gp 0 /* Sampling Delay Selection group position. */ -#define ADC_SAMPDLY0_bm (1<<0) /* Sampling Delay Selection bit 0 mask. */ -#define ADC_SAMPDLY0_bp 0 /* Sampling Delay Selection bit 0 position. */ -#define ADC_SAMPDLY1_bm (1<<1) /* Sampling Delay Selection bit 1 mask. */ -#define ADC_SAMPDLY1_bp 1 /* Sampling Delay Selection bit 1 position. */ -#define ADC_SAMPDLY2_bm (1<<2) /* Sampling Delay Selection bit 2 mask. */ -#define ADC_SAMPDLY2_bp 2 /* Sampling Delay Selection bit 2 position. */ -#define ADC_SAMPDLY3_bm (1<<3) /* Sampling Delay Selection bit 3 mask. */ -#define ADC_SAMPDLY3_bp 3 /* Sampling Delay Selection bit 3 position. */ -#define ADC_ASDV_bm 0x10 /* Automatic Sampling Delay Variation bit mask. */ -#define ADC_ASDV_bp 4 /* Automatic Sampling Delay Variation bit position. */ -#define ADC_INITDLY_gm 0xE0 /* Initial Delay Selection group mask. */ -#define ADC_INITDLY_gp 5 /* Initial Delay Selection group position. */ -#define ADC_INITDLY0_bm (1<<5) /* Initial Delay Selection bit 0 mask. */ -#define ADC_INITDLY0_bp 5 /* Initial Delay Selection bit 0 position. */ -#define ADC_INITDLY1_bm (1<<6) /* Initial Delay Selection bit 1 mask. */ -#define ADC_INITDLY1_bp 6 /* Initial Delay Selection bit 1 position. */ -#define ADC_INITDLY2_bm (1<<7) /* Initial Delay Selection bit 2 mask. */ -#define ADC_INITDLY2_bp 7 /* Initial Delay Selection bit 2 position. */ - -/* ADC.CTRLE bit masks and bit positions */ -#define ADC_WINCM_gm 0x07 /* Window Comparator Mode group mask. */ -#define ADC_WINCM_gp 0 /* Window Comparator Mode group position. */ -#define ADC_WINCM0_bm (1<<0) /* Window Comparator Mode bit 0 mask. */ -#define ADC_WINCM0_bp 0 /* Window Comparator Mode bit 0 position. */ -#define ADC_WINCM1_bm (1<<1) /* Window Comparator Mode bit 1 mask. */ -#define ADC_WINCM1_bp 1 /* Window Comparator Mode bit 1 position. */ -#define ADC_WINCM2_bm (1<<2) /* Window Comparator Mode bit 2 mask. */ -#define ADC_WINCM2_bp 2 /* Window Comparator Mode bit 2 position. */ - -/* ADC.SAMPCTRL bit masks and bit positions */ -#define ADC_SAMPLEN_gm 0x1F /* Sample lenght group mask. */ -#define ADC_SAMPLEN_gp 0 /* Sample lenght group position. */ -#define ADC_SAMPLEN0_bm (1<<0) /* Sample lenght bit 0 mask. */ -#define ADC_SAMPLEN0_bp 0 /* Sample lenght bit 0 position. */ -#define ADC_SAMPLEN1_bm (1<<1) /* Sample lenght bit 1 mask. */ -#define ADC_SAMPLEN1_bp 1 /* Sample lenght bit 1 position. */ -#define ADC_SAMPLEN2_bm (1<<2) /* Sample lenght bit 2 mask. */ -#define ADC_SAMPLEN2_bp 2 /* Sample lenght bit 2 position. */ -#define ADC_SAMPLEN3_bm (1<<3) /* Sample lenght bit 3 mask. */ -#define ADC_SAMPLEN3_bp 3 /* Sample lenght bit 3 position. */ -#define ADC_SAMPLEN4_bm (1<<4) /* Sample lenght bit 4 mask. */ -#define ADC_SAMPLEN4_bp 4 /* Sample lenght bit 4 position. */ - -/* ADC.MUXPOS bit masks and bit positions */ -#define ADC_MUXPOS_gm 0x1F /* Analog Channel Selection Bits group mask. */ -#define ADC_MUXPOS_gp 0 /* Analog Channel Selection Bits group position. */ -#define ADC_MUXPOS0_bm (1<<0) /* Analog Channel Selection Bits bit 0 mask. */ -#define ADC_MUXPOS0_bp 0 /* Analog Channel Selection Bits bit 0 position. */ -#define ADC_MUXPOS1_bm (1<<1) /* Analog Channel Selection Bits bit 1 mask. */ -#define ADC_MUXPOS1_bp 1 /* Analog Channel Selection Bits bit 1 position. */ -#define ADC_MUXPOS2_bm (1<<2) /* Analog Channel Selection Bits bit 2 mask. */ -#define ADC_MUXPOS2_bp 2 /* Analog Channel Selection Bits bit 2 position. */ -#define ADC_MUXPOS3_bm (1<<3) /* Analog Channel Selection Bits bit 3 mask. */ -#define ADC_MUXPOS3_bp 3 /* Analog Channel Selection Bits bit 3 position. */ -#define ADC_MUXPOS4_bm (1<<4) /* Analog Channel Selection Bits bit 4 mask. */ -#define ADC_MUXPOS4_bp 4 /* Analog Channel Selection Bits bit 4 position. */ - -/* ADC.COMMAND bit masks and bit positions */ -#define ADC_STCONV_bm 0x01 /* Start Conversion Operation bit mask. */ -#define ADC_STCONV_bp 0 /* Start Conversion Operation bit position. */ - -/* ADC.EVCTRL bit masks and bit positions */ -#define ADC_STARTEI_bm 0x01 /* Start Event Input Enable bit mask. */ -#define ADC_STARTEI_bp 0 /* Start Event Input Enable bit position. */ - -/* ADC.INTCTRL bit masks and bit positions */ -#define ADC_RESRDY_bm 0x01 /* Result Ready Interrupt Enable bit mask. */ -#define ADC_RESRDY_bp 0 /* Result Ready Interrupt Enable bit position. */ -#define ADC_WCMP_bm 0x02 /* Window Comparator Interrupt Enable bit mask. */ -#define ADC_WCMP_bp 1 /* Window Comparator Interrupt Enable bit position. */ - -/* ADC.INTFLAGS bit masks and bit positions */ -/* ADC_RESRDY is already defined. */ -/* ADC_WCMP is already defined. */ - -/* ADC.DBGCTRL bit masks and bit positions */ -#define ADC_DBGRUN_bm 0x01 /* Debug run bit mask. */ -#define ADC_DBGRUN_bp 0 /* Debug run bit position. */ - -/* ADC.TEMP bit masks and bit positions */ -#define ADC_TEMP_gm 0xFF /* Temporary group mask. */ -#define ADC_TEMP_gp 0 /* Temporary group position. */ -#define ADC_TEMP0_bm (1<<0) /* Temporary bit 0 mask. */ -#define ADC_TEMP0_bp 0 /* Temporary bit 0 position. */ -#define ADC_TEMP1_bm (1<<1) /* Temporary bit 1 mask. */ -#define ADC_TEMP1_bp 1 /* Temporary bit 1 position. */ -#define ADC_TEMP2_bm (1<<2) /* Temporary bit 2 mask. */ -#define ADC_TEMP2_bp 2 /* Temporary bit 2 position. */ -#define ADC_TEMP3_bm (1<<3) /* Temporary bit 3 mask. */ -#define ADC_TEMP3_bp 3 /* Temporary bit 3 position. */ -#define ADC_TEMP4_bm (1<<4) /* Temporary bit 4 mask. */ -#define ADC_TEMP4_bp 4 /* Temporary bit 4 position. */ -#define ADC_TEMP5_bm (1<<5) /* Temporary bit 5 mask. */ -#define ADC_TEMP5_bp 5 /* Temporary bit 5 position. */ -#define ADC_TEMP6_bm (1<<6) /* Temporary bit 6 mask. */ -#define ADC_TEMP6_bp 6 /* Temporary bit 6 position. */ -#define ADC_TEMP7_bm (1<<7) /* Temporary bit 7 mask. */ -#define ADC_TEMP7_bp 7 /* Temporary bit 7 position. */ - - - - -/* ADC.CALIB bit masks and bit positions */ -#define ADC_DUTYCYC_bm 0x01 /* Duty Cycle bit mask. */ -#define ADC_DUTYCYC_bp 0 /* Duty Cycle bit position. */ - -/* BOD - Bod interface */ -/* BOD.CTRLA bit masks and bit positions */ -#define BOD_SLEEP_gm 0x03 /* Operation in sleep mode group mask. */ -#define BOD_SLEEP_gp 0 /* Operation in sleep mode group position. */ -#define BOD_SLEEP0_bm (1<<0) /* Operation in sleep mode bit 0 mask. */ -#define BOD_SLEEP0_bp 0 /* Operation in sleep mode bit 0 position. */ -#define BOD_SLEEP1_bm (1<<1) /* Operation in sleep mode bit 1 mask. */ -#define BOD_SLEEP1_bp 1 /* Operation in sleep mode bit 1 position. */ -#define BOD_ACTIVE_gm 0x0C /* Operation in active mode group mask. */ -#define BOD_ACTIVE_gp 2 /* Operation in active mode group position. */ -#define BOD_ACTIVE0_bm (1<<2) /* Operation in active mode bit 0 mask. */ -#define BOD_ACTIVE0_bp 2 /* Operation in active mode bit 0 position. */ -#define BOD_ACTIVE1_bm (1<<3) /* Operation in active mode bit 1 mask. */ -#define BOD_ACTIVE1_bp 3 /* Operation in active mode bit 1 position. */ -#define BOD_SAMPFREQ_bm 0x10 /* Sample frequency bit mask. */ -#define BOD_SAMPFREQ_bp 4 /* Sample frequency bit position. */ - -/* BOD.CTRLB bit masks and bit positions */ -#define BOD_LVL_gm 0x07 /* Bod level group mask. */ -#define BOD_LVL_gp 0 /* Bod level group position. */ -#define BOD_LVL0_bm (1<<0) /* Bod level bit 0 mask. */ -#define BOD_LVL0_bp 0 /* Bod level bit 0 position. */ -#define BOD_LVL1_bm (1<<1) /* Bod level bit 1 mask. */ -#define BOD_LVL1_bp 1 /* Bod level bit 1 position. */ -#define BOD_LVL2_bm (1<<2) /* Bod level bit 2 mask. */ -#define BOD_LVL2_bp 2 /* Bod level bit 2 position. */ - -/* BOD.VLMCTRLA bit masks and bit positions */ -#define BOD_VLMLVL_gm 0x03 /* voltage level monitor level group mask. */ -#define BOD_VLMLVL_gp 0 /* voltage level monitor level group position. */ -#define BOD_VLMLVL0_bm (1<<0) /* voltage level monitor level bit 0 mask. */ -#define BOD_VLMLVL0_bp 0 /* voltage level monitor level bit 0 position. */ -#define BOD_VLMLVL1_bm (1<<1) /* voltage level monitor level bit 1 mask. */ -#define BOD_VLMLVL1_bp 1 /* voltage level monitor level bit 1 position. */ - -/* BOD.INTCTRL bit masks and bit positions */ -#define BOD_VLMIE_bm 0x01 /* voltage level monitor interrrupt enable bit mask. */ -#define BOD_VLMIE_bp 0 /* voltage level monitor interrrupt enable bit position. */ -#define BOD_VLMCFG_gm 0x06 /* Configuration group mask. */ -#define BOD_VLMCFG_gp 1 /* Configuration group position. */ -#define BOD_VLMCFG0_bm (1<<1) /* Configuration bit 0 mask. */ -#define BOD_VLMCFG0_bp 1 /* Configuration bit 0 position. */ -#define BOD_VLMCFG1_bm (1<<2) /* Configuration bit 1 mask. */ -#define BOD_VLMCFG1_bp 2 /* Configuration bit 1 position. */ - -/* BOD.INTFLAGS bit masks and bit positions */ -#define BOD_VLMIF_bm 0x01 /* Voltage level monitor interrupt flag bit mask. */ -#define BOD_VLMIF_bp 0 /* Voltage level monitor interrupt flag bit position. */ - -/* BOD.STATUS bit masks and bit positions */ -#define BOD_VLMS_bm 0x01 /* Voltage level monitor status bit mask. */ -#define BOD_VLMS_bp 0 /* Voltage level monitor status bit position. */ - -/* CCL - Configurable Custom Logic */ -/* CCL.CTRLA bit masks and bit positions */ -#define CCL_ENABLE_bm 0x01 /* Enable bit mask. */ -#define CCL_ENABLE_bp 0 /* Enable bit position. */ -#define CCL_RUNSTDBY_bm 0x40 /* Run in Standby bit mask. */ -#define CCL_RUNSTDBY_bp 6 /* Run in Standby bit position. */ - -/* CCL.SEQCTRL0 bit masks and bit positions */ -#define CCL_SEQSEL_gm 0x07 /* Sequential Selection group mask. */ -#define CCL_SEQSEL_gp 0 /* Sequential Selection group position. */ -#define CCL_SEQSEL0_bm (1<<0) /* Sequential Selection bit 0 mask. */ -#define CCL_SEQSEL0_bp 0 /* Sequential Selection bit 0 position. */ -#define CCL_SEQSEL1_bm (1<<1) /* Sequential Selection bit 1 mask. */ -#define CCL_SEQSEL1_bp 1 /* Sequential Selection bit 1 position. */ -#define CCL_SEQSEL2_bm (1<<2) /* Sequential Selection bit 2 mask. */ -#define CCL_SEQSEL2_bp 2 /* Sequential Selection bit 2 position. */ - -/* CCL.INTCTRL0 bit masks and bit positions */ -#define CCL_INTMODE0_gm 0x03 /* Interrupt Mode for LUT0 group mask. */ -#define CCL_INTMODE0_gp 0 /* Interrupt Mode for LUT0 group position. */ -#define CCL_INTMODE00_bm (1<<0) /* Interrupt Mode for LUT0 bit 0 mask. */ -#define CCL_INTMODE00_bp 0 /* Interrupt Mode for LUT0 bit 0 position. */ -#define CCL_INTMODE01_bm (1<<1) /* Interrupt Mode for LUT0 bit 1 mask. */ -#define CCL_INTMODE01_bp 1 /* Interrupt Mode for LUT0 bit 1 position. */ -#define CCL_INTMODE1_gm 0x0C /* Interrupt Mode for LUT1 group mask. */ -#define CCL_INTMODE1_gp 2 /* Interrupt Mode for LUT1 group position. */ -#define CCL_INTMODE10_bm (1<<2) /* Interrupt Mode for LUT1 bit 0 mask. */ -#define CCL_INTMODE10_bp 2 /* Interrupt Mode for LUT1 bit 0 position. */ -#define CCL_INTMODE11_bm (1<<3) /* Interrupt Mode for LUT1 bit 1 mask. */ -#define CCL_INTMODE11_bp 3 /* Interrupt Mode for LUT1 bit 1 position. */ -#define CCL_INTMODE2_gm 0x30 /* Interrupt Mode for LUT2 group mask. */ -#define CCL_INTMODE2_gp 4 /* Interrupt Mode for LUT2 group position. */ -#define CCL_INTMODE20_bm (1<<4) /* Interrupt Mode for LUT2 bit 0 mask. */ -#define CCL_INTMODE20_bp 4 /* Interrupt Mode for LUT2 bit 0 position. */ -#define CCL_INTMODE21_bm (1<<5) /* Interrupt Mode for LUT2 bit 1 mask. */ -#define CCL_INTMODE21_bp 5 /* Interrupt Mode for LUT2 bit 1 position. */ -#define CCL_INTMODE3_gm 0xC0 /* Interrupt Mode for LUT3 group mask. */ -#define CCL_INTMODE3_gp 6 /* Interrupt Mode for LUT3 group position. */ -#define CCL_INTMODE30_bm (1<<6) /* Interrupt Mode for LUT3 bit 0 mask. */ -#define CCL_INTMODE30_bp 6 /* Interrupt Mode for LUT3 bit 0 position. */ -#define CCL_INTMODE31_bm (1<<7) /* Interrupt Mode for LUT3 bit 1 mask. */ -#define CCL_INTMODE31_bp 7 /* Interrupt Mode for LUT3 bit 1 position. */ - -/* CCL.INTFLAGS bit masks and bit positions */ -#define CCL_INT_gm 0x0F /* Interrupt Flags group mask. */ -#define CCL_INT_gp 0 /* Interrupt Flags group position. */ -#define CCL_INT0_bm (1<<0) /* Interrupt Flags bit 0 mask. */ -#define CCL_INT0_bp 0 /* Interrupt Flags bit 0 position. */ -#define CCL_INT1_bm (1<<1) /* Interrupt Flags bit 1 mask. */ -#define CCL_INT1_bp 1 /* Interrupt Flags bit 1 position. */ -#define CCL_INT2_bm (1<<2) /* Interrupt Flags bit 2 mask. */ -#define CCL_INT2_bp 2 /* Interrupt Flags bit 2 position. */ -#define CCL_INT3_bm (1<<3) /* Interrupt Flags bit 3 mask. */ -#define CCL_INT3_bp 3 /* Interrupt Flags bit 3 position. */ - -/* CCL.LUT0CTRLA bit masks and bit positions */ -/* CCL_ENABLE is already defined. */ -#define CCL_CLKSRC_gm 0x0E /* Clock Source Selection group mask. */ -#define CCL_CLKSRC_gp 1 /* Clock Source Selection group position. */ -#define CCL_CLKSRC0_bm (1<<1) /* Clock Source Selection bit 0 mask. */ -#define CCL_CLKSRC0_bp 1 /* Clock Source Selection bit 0 position. */ -#define CCL_CLKSRC1_bm (1<<2) /* Clock Source Selection bit 1 mask. */ -#define CCL_CLKSRC1_bp 2 /* Clock Source Selection bit 1 position. */ -#define CCL_CLKSRC2_bm (1<<3) /* Clock Source Selection bit 2 mask. */ -#define CCL_CLKSRC2_bp 3 /* Clock Source Selection bit 2 position. */ -#define CCL_FILTSEL_gm 0x30 /* Filter Selection group mask. */ -#define CCL_FILTSEL_gp 4 /* Filter Selection group position. */ -#define CCL_FILTSEL0_bm (1<<4) /* Filter Selection bit 0 mask. */ -#define CCL_FILTSEL0_bp 4 /* Filter Selection bit 0 position. */ -#define CCL_FILTSEL1_bm (1<<5) /* Filter Selection bit 1 mask. */ -#define CCL_FILTSEL1_bp 5 /* Filter Selection bit 1 position. */ -#define CCL_OUTEN_bm 0x40 /* Output Enable bit mask. */ -#define CCL_OUTEN_bp 6 /* Output Enable bit position. */ -#define CCL_EDGEDET_bm 0x80 /* Edge Detection Enable bit mask. */ -#define CCL_EDGEDET_bp 7 /* Edge Detection Enable bit position. */ - -/* CCL.LUT0CTRLB bit masks and bit positions */ -#define CCL_INSEL0_gm 0x0F /* LUT Input 0 Source Selection group mask. */ -#define CCL_INSEL0_gp 0 /* LUT Input 0 Source Selection group position. */ -#define CCL_INSEL00_bm (1<<0) /* LUT Input 0 Source Selection bit 0 mask. */ -#define CCL_INSEL00_bp 0 /* LUT Input 0 Source Selection bit 0 position. */ -#define CCL_INSEL01_bm (1<<1) /* LUT Input 0 Source Selection bit 1 mask. */ -#define CCL_INSEL01_bp 1 /* LUT Input 0 Source Selection bit 1 position. */ -#define CCL_INSEL02_bm (1<<2) /* LUT Input 0 Source Selection bit 2 mask. */ -#define CCL_INSEL02_bp 2 /* LUT Input 0 Source Selection bit 2 position. */ -#define CCL_INSEL03_bm (1<<3) /* LUT Input 0 Source Selection bit 3 mask. */ -#define CCL_INSEL03_bp 3 /* LUT Input 0 Source Selection bit 3 position. */ -#define CCL_INSEL1_gm 0xF0 /* LUT Input 1 Source Selection group mask. */ -#define CCL_INSEL1_gp 4 /* LUT Input 1 Source Selection group position. */ -#define CCL_INSEL10_bm (1<<4) /* LUT Input 1 Source Selection bit 0 mask. */ -#define CCL_INSEL10_bp 4 /* LUT Input 1 Source Selection bit 0 position. */ -#define CCL_INSEL11_bm (1<<5) /* LUT Input 1 Source Selection bit 1 mask. */ -#define CCL_INSEL11_bp 5 /* LUT Input 1 Source Selection bit 1 position. */ -#define CCL_INSEL12_bm (1<<6) /* LUT Input 1 Source Selection bit 2 mask. */ -#define CCL_INSEL12_bp 6 /* LUT Input 1 Source Selection bit 2 position. */ -#define CCL_INSEL13_bm (1<<7) /* LUT Input 1 Source Selection bit 3 mask. */ -#define CCL_INSEL13_bp 7 /* LUT Input 1 Source Selection bit 3 position. */ - -/* CCL.LUT0CTRLC bit masks and bit positions */ -#define CCL_INSEL2_gm 0x0F /* LUT Input 2 Source Selection group mask. */ -#define CCL_INSEL2_gp 0 /* LUT Input 2 Source Selection group position. */ -#define CCL_INSEL20_bm (1<<0) /* LUT Input 2 Source Selection bit 0 mask. */ -#define CCL_INSEL20_bp 0 /* LUT Input 2 Source Selection bit 0 position. */ -#define CCL_INSEL21_bm (1<<1) /* LUT Input 2 Source Selection bit 1 mask. */ -#define CCL_INSEL21_bp 1 /* LUT Input 2 Source Selection bit 1 position. */ -#define CCL_INSEL22_bm (1<<2) /* LUT Input 2 Source Selection bit 2 mask. */ -#define CCL_INSEL22_bp 2 /* LUT Input 2 Source Selection bit 2 position. */ -#define CCL_INSEL23_bm (1<<3) /* LUT Input 2 Source Selection bit 3 mask. */ -#define CCL_INSEL23_bp 3 /* LUT Input 2 Source Selection bit 3 position. */ - - -/* CCL.LUT1CTRLA bit masks and bit positions */ -/* CCL_ENABLE is already defined. */ -/* CCL_CLKSRC is already defined. */ -/* CCL_FILTSEL is already defined. */ -/* CCL_OUTEN is already defined. */ -/* CCL_EDGEDET is already defined. */ - -/* CCL.LUT1CTRLB bit masks and bit positions */ -/* CCL_INSEL0 is already defined. */ -/* CCL_INSEL1 is already defined. */ - -/* CCL.LUT1CTRLC bit masks and bit positions */ -/* CCL_INSEL2 is already defined. */ - - -/* CCL.LUT2CTRLA bit masks and bit positions */ -/* CCL_ENABLE is already defined. */ -/* CCL_CLKSRC is already defined. */ -/* CCL_FILTSEL is already defined. */ -/* CCL_OUTEN is already defined. */ -/* CCL_EDGEDET is already defined. */ - -/* CCL.LUT2CTRLB bit masks and bit positions */ -/* CCL_INSEL0 is already defined. */ -/* CCL_INSEL1 is already defined. */ - -/* CCL.LUT2CTRLC bit masks and bit positions */ -/* CCL_INSEL2 is already defined. */ - - -/* CCL.LUT3CTRLA bit masks and bit positions */ -/* CCL_ENABLE is already defined. */ -/* CCL_CLKSRC is already defined. */ -/* CCL_FILTSEL is already defined. */ -/* CCL_OUTEN is already defined. */ -/* CCL_EDGEDET is already defined. */ - -/* CCL.LUT3CTRLB bit masks and bit positions */ -/* CCL_INSEL0 is already defined. */ -/* CCL_INSEL1 is already defined. */ - -/* CCL.LUT3CTRLC bit masks and bit positions */ -/* CCL_INSEL2 is already defined. */ - - -/* CLKCTRL - Clock controller */ -/* CLKCTRL.MCLKCTRLA bit masks and bit positions */ -#define CLKCTRL_CLKSEL_gm 0x03 /* clock select group mask. */ -#define CLKCTRL_CLKSEL_gp 0 /* clock select group position. */ -#define CLKCTRL_CLKSEL0_bm (1<<0) /* clock select bit 0 mask. */ -#define CLKCTRL_CLKSEL0_bp 0 /* clock select bit 0 position. */ -#define CLKCTRL_CLKSEL1_bm (1<<1) /* clock select bit 1 mask. */ -#define CLKCTRL_CLKSEL1_bp 1 /* clock select bit 1 position. */ -#define CLKCTRL_CLKOUT_bm 0x80 /* System clock out bit mask. */ -#define CLKCTRL_CLKOUT_bp 7 /* System clock out bit position. */ - -/* CLKCTRL.MCLKCTRLB bit masks and bit positions */ -#define CLKCTRL_PEN_bm 0x01 /* Prescaler enable bit mask. */ -#define CLKCTRL_PEN_bp 0 /* Prescaler enable bit position. */ -#define CLKCTRL_PDIV_gm 0x1E /* Prescaler division group mask. */ -#define CLKCTRL_PDIV_gp 1 /* Prescaler division group position. */ -#define CLKCTRL_PDIV0_bm (1<<1) /* Prescaler division bit 0 mask. */ -#define CLKCTRL_PDIV0_bp 1 /* Prescaler division bit 0 position. */ -#define CLKCTRL_PDIV1_bm (1<<2) /* Prescaler division bit 1 mask. */ -#define CLKCTRL_PDIV1_bp 2 /* Prescaler division bit 1 position. */ -#define CLKCTRL_PDIV2_bm (1<<3) /* Prescaler division bit 2 mask. */ -#define CLKCTRL_PDIV2_bp 3 /* Prescaler division bit 2 position. */ -#define CLKCTRL_PDIV3_bm (1<<4) /* Prescaler division bit 3 mask. */ -#define CLKCTRL_PDIV3_bp 4 /* Prescaler division bit 3 position. */ - -/* CLKCTRL.MCLKLOCK bit masks and bit positions */ -#define CLKCTRL_LOCKEN_bm 0x01 /* lock ebable bit mask. */ -#define CLKCTRL_LOCKEN_bp 0 /* lock ebable bit position. */ - -/* CLKCTRL.MCLKSTATUS bit masks and bit positions */ -#define CLKCTRL_SOSC_bm 0x01 /* System Oscillator changing bit mask. */ -#define CLKCTRL_SOSC_bp 0 /* System Oscillator changing bit position. */ -#define CLKCTRL_OSC20MS_bm 0x10 /* 20MHz oscillator status bit mask. */ -#define CLKCTRL_OSC20MS_bp 4 /* 20MHz oscillator status bit position. */ -#define CLKCTRL_OSC32KS_bm 0x20 /* 32KHz oscillator status bit mask. */ -#define CLKCTRL_OSC32KS_bp 5 /* 32KHz oscillator status bit position. */ -#define CLKCTRL_XOSC32KS_bm 0x40 /* 32.768 kHz Crystal Oscillator status bit mask. */ -#define CLKCTRL_XOSC32KS_bp 6 /* 32.768 kHz Crystal Oscillator status bit position. */ -#define CLKCTRL_EXTS_bm 0x80 /* External Clock status bit mask. */ -#define CLKCTRL_EXTS_bp 7 /* External Clock status bit position. */ - -/* CLKCTRL.OSC20MCTRLA bit masks and bit positions */ -#define CLKCTRL_RUNSTDBY_bm 0x02 /* Run standby bit mask. */ -#define CLKCTRL_RUNSTDBY_bp 1 /* Run standby bit position. */ - -/* CLKCTRL.OSC20MCALIBA bit masks and bit positions */ -#define CLKCTRL_CAL20M_gm 0x7F /* Calibration group mask. */ -#define CLKCTRL_CAL20M_gp 0 /* Calibration group position. */ -#define CLKCTRL_CAL20M0_bm (1<<0) /* Calibration bit 0 mask. */ -#define CLKCTRL_CAL20M0_bp 0 /* Calibration bit 0 position. */ -#define CLKCTRL_CAL20M1_bm (1<<1) /* Calibration bit 1 mask. */ -#define CLKCTRL_CAL20M1_bp 1 /* Calibration bit 1 position. */ -#define CLKCTRL_CAL20M2_bm (1<<2) /* Calibration bit 2 mask. */ -#define CLKCTRL_CAL20M2_bp 2 /* Calibration bit 2 position. */ -#define CLKCTRL_CAL20M3_bm (1<<3) /* Calibration bit 3 mask. */ -#define CLKCTRL_CAL20M3_bp 3 /* Calibration bit 3 position. */ -#define CLKCTRL_CAL20M4_bm (1<<4) /* Calibration bit 4 mask. */ -#define CLKCTRL_CAL20M4_bp 4 /* Calibration bit 4 position. */ -#define CLKCTRL_CAL20M5_bm (1<<5) /* Calibration bit 5 mask. */ -#define CLKCTRL_CAL20M5_bp 5 /* Calibration bit 5 position. */ -#define CLKCTRL_CAL20M6_bm (1<<6) /* Calibration bit 6 mask. */ -#define CLKCTRL_CAL20M6_bp 6 /* Calibration bit 6 position. */ -#define CLKCTRL_CALSEL20M_bm 0x80 /* Calibration freq select bit mask. */ -#define CLKCTRL_CALSEL20M_bp 7 /* Calibration freq select bit position. */ - -/* CLKCTRL.OSC20MCALIBB bit masks and bit positions */ -#define CLKCTRL_TEMPCAL20M_gm 0x0F /* Oscillator temperature coefficient group mask. */ -#define CLKCTRL_TEMPCAL20M_gp 0 /* Oscillator temperature coefficient group position. */ -#define CLKCTRL_TEMPCAL20M0_bm (1<<0) /* Oscillator temperature coefficient bit 0 mask. */ -#define CLKCTRL_TEMPCAL20M0_bp 0 /* Oscillator temperature coefficient bit 0 position. */ -#define CLKCTRL_TEMPCAL20M1_bm (1<<1) /* Oscillator temperature coefficient bit 1 mask. */ -#define CLKCTRL_TEMPCAL20M1_bp 1 /* Oscillator temperature coefficient bit 1 position. */ -#define CLKCTRL_TEMPCAL20M2_bm (1<<2) /* Oscillator temperature coefficient bit 2 mask. */ -#define CLKCTRL_TEMPCAL20M2_bp 2 /* Oscillator temperature coefficient bit 2 position. */ -#define CLKCTRL_TEMPCAL20M3_bm (1<<3) /* Oscillator temperature coefficient bit 3 mask. */ -#define CLKCTRL_TEMPCAL20M3_bp 3 /* Oscillator temperature coefficient bit 3 position. */ -#define CLKCTRL_LOCK_bm 0x80 /* Lock bit mask. */ -#define CLKCTRL_LOCK_bp 7 /* Lock bit position. */ - -/* CLKCTRL.OSC32KCTRLA bit masks and bit positions */ -/* CLKCTRL_RUNSTDBY is already defined. */ - -/* CLKCTRL.OSC32KCALIB bit masks and bit positions */ -#define CLKCTRL_CAL32K_gm 0x3F /* Calibration group mask. */ -#define CLKCTRL_CAL32K_gp 0 /* Calibration group position. */ -#define CLKCTRL_CAL32K0_bm (1<<0) /* Calibration bit 0 mask. */ -#define CLKCTRL_CAL32K0_bp 0 /* Calibration bit 0 position. */ -#define CLKCTRL_CAL32K1_bm (1<<1) /* Calibration bit 1 mask. */ -#define CLKCTRL_CAL32K1_bp 1 /* Calibration bit 1 position. */ -#define CLKCTRL_CAL32K2_bm (1<<2) /* Calibration bit 2 mask. */ -#define CLKCTRL_CAL32K2_bp 2 /* Calibration bit 2 position. */ -#define CLKCTRL_CAL32K3_bm (1<<3) /* Calibration bit 3 mask. */ -#define CLKCTRL_CAL32K3_bp 3 /* Calibration bit 3 position. */ -#define CLKCTRL_CAL32K4_bm (1<<4) /* Calibration bit 4 mask. */ -#define CLKCTRL_CAL32K4_bp 4 /* Calibration bit 4 position. */ -#define CLKCTRL_CAL32K5_bm (1<<5) /* Calibration bit 5 mask. */ -#define CLKCTRL_CAL32K5_bp 5 /* Calibration bit 5 position. */ - -/* CLKCTRL.XOSC32KCTRLA bit masks and bit positions */ -#define CLKCTRL_ENABLE_bm 0x01 /* Enable bit mask. */ -#define CLKCTRL_ENABLE_bp 0 /* Enable bit position. */ -/* CLKCTRL_RUNSTDBY is already defined. */ -#define CLKCTRL_SEL_bm 0x04 /* Select bit mask. */ -#define CLKCTRL_SEL_bp 2 /* Select bit position. */ -#define CLKCTRL_CSUT_gm 0x30 /* Crystal startup time group mask. */ -#define CLKCTRL_CSUT_gp 4 /* Crystal startup time group position. */ -#define CLKCTRL_CSUT0_bm (1<<4) /* Crystal startup time bit 0 mask. */ -#define CLKCTRL_CSUT0_bp 4 /* Crystal startup time bit 0 position. */ -#define CLKCTRL_CSUT1_bm (1<<5) /* Crystal startup time bit 1 mask. */ -#define CLKCTRL_CSUT1_bp 5 /* Crystal startup time bit 1 position. */ - -/* CPU - CPU */ -/* CPU.CCP bit masks and bit positions */ -#define CPU_CCP_gm 0xFF /* CCP signature group mask. */ -#define CPU_CCP_gp 0 /* CCP signature group position. */ -#define CPU_CCP0_bm (1<<0) /* CCP signature bit 0 mask. */ -#define CPU_CCP0_bp 0 /* CCP signature bit 0 position. */ -#define CPU_CCP1_bm (1<<1) /* CCP signature bit 1 mask. */ -#define CPU_CCP1_bp 1 /* CCP signature bit 1 position. */ -#define CPU_CCP2_bm (1<<2) /* CCP signature bit 2 mask. */ -#define CPU_CCP2_bp 2 /* CCP signature bit 2 position. */ -#define CPU_CCP3_bm (1<<3) /* CCP signature bit 3 mask. */ -#define CPU_CCP3_bp 3 /* CCP signature bit 3 position. */ -#define CPU_CCP4_bm (1<<4) /* CCP signature bit 4 mask. */ -#define CPU_CCP4_bp 4 /* CCP signature bit 4 position. */ -#define CPU_CCP5_bm (1<<5) /* CCP signature bit 5 mask. */ -#define CPU_CCP5_bp 5 /* CCP signature bit 5 position. */ -#define CPU_CCP6_bm (1<<6) /* CCP signature bit 6 mask. */ -#define CPU_CCP6_bp 6 /* CCP signature bit 6 position. */ -#define CPU_CCP7_bm (1<<7) /* CCP signature bit 7 mask. */ -#define CPU_CCP7_bp 7 /* CCP signature bit 7 position. */ - - - - -/* CPU.SREG bit masks and bit positions */ -#define CPU_C_bm 0x01 /* Carry Flag bit mask. */ -#define CPU_C_bp 0 /* Carry Flag bit position. */ -#define CPU_Z_bm 0x02 /* Zero Flag bit mask. */ -#define CPU_Z_bp 1 /* Zero Flag bit position. */ -#define CPU_N_bm 0x04 /* Negative Flag bit mask. */ -#define CPU_N_bp 2 /* Negative Flag bit position. */ -#define CPU_V_bm 0x08 /* Two's Complement Overflow Flag bit mask. */ -#define CPU_V_bp 3 /* Two's Complement Overflow Flag bit position. */ -#define CPU_S_bm 0x10 /* N Exclusive Or V Flag bit mask. */ -#define CPU_S_bp 4 /* N Exclusive Or V Flag bit position. */ -#define CPU_H_bm 0x20 /* Half Carry Flag bit mask. */ -#define CPU_H_bp 5 /* Half Carry Flag bit position. */ -#define CPU_T_bm 0x40 /* Transfer Bit bit mask. */ -#define CPU_T_bp 6 /* Transfer Bit bit position. */ -#define CPU_I_bm 0x80 /* Global Interrupt Enable Flag bit mask. */ -#define CPU_I_bp 7 /* Global Interrupt Enable Flag bit position. */ - -/* CPUINT - Interrupt Controller */ -/* CPUINT.CTRLA bit masks and bit positions */ -#define CPUINT_LVL0RR_bm 0x01 /* Round-robin Scheduling Enable bit mask. */ -#define CPUINT_LVL0RR_bp 0 /* Round-robin Scheduling Enable bit position. */ -#define CPUINT_CVT_bm 0x20 /* Compact Vector Table bit mask. */ -#define CPUINT_CVT_bp 5 /* Compact Vector Table bit position. */ -#define CPUINT_IVSEL_bm 0x40 /* Interrupt Vector Select bit mask. */ -#define CPUINT_IVSEL_bp 6 /* Interrupt Vector Select bit position. */ - -/* CPUINT.STATUS bit masks and bit positions */ -#define CPUINT_LVL0EX_bm 0x01 /* Level 0 Interrupt Executing bit mask. */ -#define CPUINT_LVL0EX_bp 0 /* Level 0 Interrupt Executing bit position. */ -#define CPUINT_LVL1EX_bm 0x02 /* Level 1 Interrupt Executing bit mask. */ -#define CPUINT_LVL1EX_bp 1 /* Level 1 Interrupt Executing bit position. */ -#define CPUINT_NMIEX_bm 0x80 /* Non-maskable Interrupt Executing bit mask. */ -#define CPUINT_NMIEX_bp 7 /* Non-maskable Interrupt Executing bit position. */ - -/* CPUINT.LVL0PRI bit masks and bit positions */ -#define CPUINT_LVL0PRI_gm 0xFF /* Interrupt Level Priority group mask. */ -#define CPUINT_LVL0PRI_gp 0 /* Interrupt Level Priority group position. */ -#define CPUINT_LVL0PRI0_bm (1<<0) /* Interrupt Level Priority bit 0 mask. */ -#define CPUINT_LVL0PRI0_bp 0 /* Interrupt Level Priority bit 0 position. */ -#define CPUINT_LVL0PRI1_bm (1<<1) /* Interrupt Level Priority bit 1 mask. */ -#define CPUINT_LVL0PRI1_bp 1 /* Interrupt Level Priority bit 1 position. */ -#define CPUINT_LVL0PRI2_bm (1<<2) /* Interrupt Level Priority bit 2 mask. */ -#define CPUINT_LVL0PRI2_bp 2 /* Interrupt Level Priority bit 2 position. */ -#define CPUINT_LVL0PRI3_bm (1<<3) /* Interrupt Level Priority bit 3 mask. */ -#define CPUINT_LVL0PRI3_bp 3 /* Interrupt Level Priority bit 3 position. */ -#define CPUINT_LVL0PRI4_bm (1<<4) /* Interrupt Level Priority bit 4 mask. */ -#define CPUINT_LVL0PRI4_bp 4 /* Interrupt Level Priority bit 4 position. */ -#define CPUINT_LVL0PRI5_bm (1<<5) /* Interrupt Level Priority bit 5 mask. */ -#define CPUINT_LVL0PRI5_bp 5 /* Interrupt Level Priority bit 5 position. */ -#define CPUINT_LVL0PRI6_bm (1<<6) /* Interrupt Level Priority bit 6 mask. */ -#define CPUINT_LVL0PRI6_bp 6 /* Interrupt Level Priority bit 6 position. */ -#define CPUINT_LVL0PRI7_bm (1<<7) /* Interrupt Level Priority bit 7 mask. */ -#define CPUINT_LVL0PRI7_bp 7 /* Interrupt Level Priority bit 7 position. */ - -/* CPUINT.LVL1VEC bit masks and bit positions */ -#define CPUINT_LVL1VEC_gm 0xFF /* Interrupt Vector with High Priority group mask. */ -#define CPUINT_LVL1VEC_gp 0 /* Interrupt Vector with High Priority group position. */ -#define CPUINT_LVL1VEC0_bm (1<<0) /* Interrupt Vector with High Priority bit 0 mask. */ -#define CPUINT_LVL1VEC0_bp 0 /* Interrupt Vector with High Priority bit 0 position. */ -#define CPUINT_LVL1VEC1_bm (1<<1) /* Interrupt Vector with High Priority bit 1 mask. */ -#define CPUINT_LVL1VEC1_bp 1 /* Interrupt Vector with High Priority bit 1 position. */ -#define CPUINT_LVL1VEC2_bm (1<<2) /* Interrupt Vector with High Priority bit 2 mask. */ -#define CPUINT_LVL1VEC2_bp 2 /* Interrupt Vector with High Priority bit 2 position. */ -#define CPUINT_LVL1VEC3_bm (1<<3) /* Interrupt Vector with High Priority bit 3 mask. */ -#define CPUINT_LVL1VEC3_bp 3 /* Interrupt Vector with High Priority bit 3 position. */ -#define CPUINT_LVL1VEC4_bm (1<<4) /* Interrupt Vector with High Priority bit 4 mask. */ -#define CPUINT_LVL1VEC4_bp 4 /* Interrupt Vector with High Priority bit 4 position. */ -#define CPUINT_LVL1VEC5_bm (1<<5) /* Interrupt Vector with High Priority bit 5 mask. */ -#define CPUINT_LVL1VEC5_bp 5 /* Interrupt Vector with High Priority bit 5 position. */ -#define CPUINT_LVL1VEC6_bm (1<<6) /* Interrupt Vector with High Priority bit 6 mask. */ -#define CPUINT_LVL1VEC6_bp 6 /* Interrupt Vector with High Priority bit 6 position. */ -#define CPUINT_LVL1VEC7_bm (1<<7) /* Interrupt Vector with High Priority bit 7 mask. */ -#define CPUINT_LVL1VEC7_bp 7 /* Interrupt Vector with High Priority bit 7 position. */ - -/* CRCSCAN - CRCSCAN */ -/* CRCSCAN.CTRLA bit masks and bit positions */ -#define CRCSCAN_ENABLE_bm 0x01 /* Enable CRC scan bit mask. */ -#define CRCSCAN_ENABLE_bp 0 /* Enable CRC scan bit position. */ -#define CRCSCAN_NMIEN_bm 0x02 /* Enable NMI Trigger bit mask. */ -#define CRCSCAN_NMIEN_bp 1 /* Enable NMI Trigger bit position. */ -#define CRCSCAN_RESET_bm 0x80 /* Reset CRC scan bit mask. */ -#define CRCSCAN_RESET_bp 7 /* Reset CRC scan bit position. */ - -/* CRCSCAN.CTRLB bit masks and bit positions */ -#define CRCSCAN_SRC_gm 0x03 /* CRC Source group mask. */ -#define CRCSCAN_SRC_gp 0 /* CRC Source group position. */ -#define CRCSCAN_SRC0_bm (1<<0) /* CRC Source bit 0 mask. */ -#define CRCSCAN_SRC0_bp 0 /* CRC Source bit 0 position. */ -#define CRCSCAN_SRC1_bm (1<<1) /* CRC Source bit 1 mask. */ -#define CRCSCAN_SRC1_bp 1 /* CRC Source bit 1 position. */ -#define CRCSCAN_MODE_gm 0x30 /* CRC Flash Access Mode group mask. */ -#define CRCSCAN_MODE_gp 4 /* CRC Flash Access Mode group position. */ -#define CRCSCAN_MODE0_bm (1<<4) /* CRC Flash Access Mode bit 0 mask. */ -#define CRCSCAN_MODE0_bp 4 /* CRC Flash Access Mode bit 0 position. */ -#define CRCSCAN_MODE1_bm (1<<5) /* CRC Flash Access Mode bit 1 mask. */ -#define CRCSCAN_MODE1_bp 5 /* CRC Flash Access Mode bit 1 position. */ - -/* CRCSCAN.STATUS bit masks and bit positions */ -#define CRCSCAN_BUSY_bm 0x01 /* CRC Busy bit mask. */ -#define CRCSCAN_BUSY_bp 0 /* CRC Busy bit position. */ -#define CRCSCAN_OK_bm 0x02 /* CRC Ok bit mask. */ -#define CRCSCAN_OK_bp 1 /* CRC Ok bit position. */ - -/* EVSYS - Event System */ -/* EVSYS.STROBE bit masks and bit positions */ -#define EVSYS_STROBE0_gm 0xFF /* Software event on channels group mask. */ -#define EVSYS_STROBE0_gp 0 /* Software event on channels group position. */ -#define EVSYS_STROBE00_bm (1<<0) /* Software event on channels bit 0 mask. */ -#define EVSYS_STROBE00_bp 0 /* Software event on channels bit 0 position. */ -#define EVSYS_STROBE01_bm (1<<1) /* Software event on channels bit 1 mask. */ -#define EVSYS_STROBE01_bp 1 /* Software event on channels bit 1 position. */ -#define EVSYS_STROBE02_bm (1<<2) /* Software event on channels bit 2 mask. */ -#define EVSYS_STROBE02_bp 2 /* Software event on channels bit 2 position. */ -#define EVSYS_STROBE03_bm (1<<3) /* Software event on channels bit 3 mask. */ -#define EVSYS_STROBE03_bp 3 /* Software event on channels bit 3 position. */ -#define EVSYS_STROBE04_bm (1<<4) /* Software event on channels bit 4 mask. */ -#define EVSYS_STROBE04_bp 4 /* Software event on channels bit 4 position. */ -#define EVSYS_STROBE05_bm (1<<5) /* Software event on channels bit 5 mask. */ -#define EVSYS_STROBE05_bp 5 /* Software event on channels bit 5 position. */ -#define EVSYS_STROBE06_bm (1<<6) /* Software event on channels bit 6 mask. */ -#define EVSYS_STROBE06_bp 6 /* Software event on channels bit 6 position. */ -#define EVSYS_STROBE07_bm (1<<7) /* Software event on channels bit 7 mask. */ -#define EVSYS_STROBE07_bp 7 /* Software event on channels bit 7 position. */ - -/* EVSYS.CHANNEL0 bit masks and bit positions */ -#define EVSYS_GENERATOR_gm 0xFF /* Generator selector group mask. */ -#define EVSYS_GENERATOR_gp 0 /* Generator selector group position. */ -#define EVSYS_GENERATOR0_bm (1<<0) /* Generator selector bit 0 mask. */ -#define EVSYS_GENERATOR0_bp 0 /* Generator selector bit 0 position. */ -#define EVSYS_GENERATOR1_bm (1<<1) /* Generator selector bit 1 mask. */ -#define EVSYS_GENERATOR1_bp 1 /* Generator selector bit 1 position. */ -#define EVSYS_GENERATOR2_bm (1<<2) /* Generator selector bit 2 mask. */ -#define EVSYS_GENERATOR2_bp 2 /* Generator selector bit 2 position. */ -#define EVSYS_GENERATOR3_bm (1<<3) /* Generator selector bit 3 mask. */ -#define EVSYS_GENERATOR3_bp 3 /* Generator selector bit 3 position. */ -#define EVSYS_GENERATOR4_bm (1<<4) /* Generator selector bit 4 mask. */ -#define EVSYS_GENERATOR4_bp 4 /* Generator selector bit 4 position. */ -#define EVSYS_GENERATOR5_bm (1<<5) /* Generator selector bit 5 mask. */ -#define EVSYS_GENERATOR5_bp 5 /* Generator selector bit 5 position. */ -#define EVSYS_GENERATOR6_bm (1<<6) /* Generator selector bit 6 mask. */ -#define EVSYS_GENERATOR6_bp 6 /* Generator selector bit 6 position. */ -#define EVSYS_GENERATOR7_bm (1<<7) /* Generator selector bit 7 mask. */ -#define EVSYS_GENERATOR7_bp 7 /* Generator selector bit 7 position. */ - -/* EVSYS.CHANNEL1 bit masks and bit positions */ -/* EVSYS_GENERATOR is already defined. */ - -/* EVSYS.CHANNEL2 bit masks and bit positions */ -/* EVSYS_GENERATOR is already defined. */ - -/* EVSYS.CHANNEL3 bit masks and bit positions */ -/* EVSYS_GENERATOR is already defined. */ - -/* EVSYS.CHANNEL4 bit masks and bit positions */ -/* EVSYS_GENERATOR is already defined. */ - -/* EVSYS.CHANNEL5 bit masks and bit positions */ -/* EVSYS_GENERATOR is already defined. */ - -/* EVSYS.USERCCLLUT0A bit masks and bit positions */ -#define EVSYS_CHANNEL_gm 0xFF /* Channel selector group mask. */ -#define EVSYS_CHANNEL_gp 0 /* Channel selector group position. */ -#define EVSYS_CHANNEL0_bm (1<<0) /* Channel selector bit 0 mask. */ -#define EVSYS_CHANNEL0_bp 0 /* Channel selector bit 0 position. */ -#define EVSYS_CHANNEL1_bm (1<<1) /* Channel selector bit 1 mask. */ -#define EVSYS_CHANNEL1_bp 1 /* Channel selector bit 1 position. */ -#define EVSYS_CHANNEL2_bm (1<<2) /* Channel selector bit 2 mask. */ -#define EVSYS_CHANNEL2_bp 2 /* Channel selector bit 2 position. */ -#define EVSYS_CHANNEL3_bm (1<<3) /* Channel selector bit 3 mask. */ -#define EVSYS_CHANNEL3_bp 3 /* Channel selector bit 3 position. */ -#define EVSYS_CHANNEL4_bm (1<<4) /* Channel selector bit 4 mask. */ -#define EVSYS_CHANNEL4_bp 4 /* Channel selector bit 4 position. */ -#define EVSYS_CHANNEL5_bm (1<<5) /* Channel selector bit 5 mask. */ -#define EVSYS_CHANNEL5_bp 5 /* Channel selector bit 5 position. */ -#define EVSYS_CHANNEL6_bm (1<<6) /* Channel selector bit 6 mask. */ -#define EVSYS_CHANNEL6_bp 6 /* Channel selector bit 6 position. */ -#define EVSYS_CHANNEL7_bm (1<<7) /* Channel selector bit 7 mask. */ -#define EVSYS_CHANNEL7_bp 7 /* Channel selector bit 7 position. */ - -/* EVSYS.USERCCLLUT0B bit masks and bit positions */ -/* EVSYS_CHANNEL is already defined. */ - -/* EVSYS.USERCCLLUT1A bit masks and bit positions */ -/* EVSYS_CHANNEL is already defined. */ - -/* EVSYS.USERCCLLUT1B bit masks and bit positions */ -/* EVSYS_CHANNEL is already defined. */ - -/* EVSYS.USERCCLLUT2A bit masks and bit positions */ -/* EVSYS_CHANNEL is already defined. */ - -/* EVSYS.USERCCLLUT2B bit masks and bit positions */ -/* EVSYS_CHANNEL is already defined. */ - -/* EVSYS.USERCCLLUT3A bit masks and bit positions */ -/* EVSYS_CHANNEL is already defined. */ - -/* EVSYS.USERCCLLUT3B bit masks and bit positions */ -/* EVSYS_CHANNEL is already defined. */ - -/* EVSYS.USERADC0 bit masks and bit positions */ -/* EVSYS_CHANNEL is already defined. */ - -/* EVSYS.USEREVOUTA bit masks and bit positions */ -/* EVSYS_CHANNEL is already defined. */ - -/* EVSYS.USEREVOUTB bit masks and bit positions */ -/* EVSYS_CHANNEL is already defined. */ - -/* EVSYS.USEREVOUTC bit masks and bit positions */ -/* EVSYS_CHANNEL is already defined. */ - -/* EVSYS.USEREVOUTD bit masks and bit positions */ -/* EVSYS_CHANNEL is already defined. */ - -/* EVSYS.USEREVOUTE bit masks and bit positions */ -/* EVSYS_CHANNEL is already defined. */ - -/* EVSYS.USEREVOUTF bit masks and bit positions */ -/* EVSYS_CHANNEL is already defined. */ - -/* EVSYS.USERUSART0 bit masks and bit positions */ -/* EVSYS_CHANNEL is already defined. */ - -/* EVSYS.USERUSART1 bit masks and bit positions */ -/* EVSYS_CHANNEL is already defined. */ - -/* EVSYS.USERUSART2 bit masks and bit positions */ -/* EVSYS_CHANNEL is already defined. */ - -/* EVSYS.USERUSART3 bit masks and bit positions */ -/* EVSYS_CHANNEL is already defined. */ - -/* EVSYS.USERTCA0 bit masks and bit positions */ -/* EVSYS_CHANNEL is already defined. */ - -/* EVSYS.USERTCB0 bit masks and bit positions */ -/* EVSYS_CHANNEL is already defined. */ - -/* EVSYS.USERTCB1 bit masks and bit positions */ -/* EVSYS_CHANNEL is already defined. */ - -/* EVSYS.USERTCB2 bit masks and bit positions */ -/* EVSYS_CHANNEL is already defined. */ - -/* EVSYS.USERTCB3 bit masks and bit positions */ -/* EVSYS_CHANNEL is already defined. */ - -/* FUSE - Fuses */ -/* FUSE.WDTCFG bit masks and bit positions */ -#define FUSE_PERIOD_gm 0x0F /* Watchdog Timeout Period group mask. */ -#define FUSE_PERIOD_gp 0 /* Watchdog Timeout Period group position. */ -#define FUSE_PERIOD0_bm (1<<0) /* Watchdog Timeout Period bit 0 mask. */ -#define FUSE_PERIOD0_bp 0 /* Watchdog Timeout Period bit 0 position. */ -#define FUSE_PERIOD1_bm (1<<1) /* Watchdog Timeout Period bit 1 mask. */ -#define FUSE_PERIOD1_bp 1 /* Watchdog Timeout Period bit 1 position. */ -#define FUSE_PERIOD2_bm (1<<2) /* Watchdog Timeout Period bit 2 mask. */ -#define FUSE_PERIOD2_bp 2 /* Watchdog Timeout Period bit 2 position. */ -#define FUSE_PERIOD3_bm (1<<3) /* Watchdog Timeout Period bit 3 mask. */ -#define FUSE_PERIOD3_bp 3 /* Watchdog Timeout Period bit 3 position. */ -#define FUSE_WINDOW_gm 0xF0 /* Watchdog Window Timeout Period group mask. */ -#define FUSE_WINDOW_gp 4 /* Watchdog Window Timeout Period group position. */ -#define FUSE_WINDOW0_bm (1<<4) /* Watchdog Window Timeout Period bit 0 mask. */ -#define FUSE_WINDOW0_bp 4 /* Watchdog Window Timeout Period bit 0 position. */ -#define FUSE_WINDOW1_bm (1<<5) /* Watchdog Window Timeout Period bit 1 mask. */ -#define FUSE_WINDOW1_bp 5 /* Watchdog Window Timeout Period bit 1 position. */ -#define FUSE_WINDOW2_bm (1<<6) /* Watchdog Window Timeout Period bit 2 mask. */ -#define FUSE_WINDOW2_bp 6 /* Watchdog Window Timeout Period bit 2 position. */ -#define FUSE_WINDOW3_bm (1<<7) /* Watchdog Window Timeout Period bit 3 mask. */ -#define FUSE_WINDOW3_bp 7 /* Watchdog Window Timeout Period bit 3 position. */ - -/* FUSE.BODCFG bit masks and bit positions */ -#define FUSE_SLEEP_gm 0x03 /* BOD Operation in Sleep Mode group mask. */ -#define FUSE_SLEEP_gp 0 /* BOD Operation in Sleep Mode group position. */ -#define FUSE_SLEEP0_bm (1<<0) /* BOD Operation in Sleep Mode bit 0 mask. */ -#define FUSE_SLEEP0_bp 0 /* BOD Operation in Sleep Mode bit 0 position. */ -#define FUSE_SLEEP1_bm (1<<1) /* BOD Operation in Sleep Mode bit 1 mask. */ -#define FUSE_SLEEP1_bp 1 /* BOD Operation in Sleep Mode bit 1 position. */ -#define FUSE_ACTIVE_gm 0x0C /* BOD Operation in Active Mode group mask. */ -#define FUSE_ACTIVE_gp 2 /* BOD Operation in Active Mode group position. */ -#define FUSE_ACTIVE0_bm (1<<2) /* BOD Operation in Active Mode bit 0 mask. */ -#define FUSE_ACTIVE0_bp 2 /* BOD Operation in Active Mode bit 0 position. */ -#define FUSE_ACTIVE1_bm (1<<3) /* BOD Operation in Active Mode bit 1 mask. */ -#define FUSE_ACTIVE1_bp 3 /* BOD Operation in Active Mode bit 1 position. */ -#define FUSE_SAMPFREQ_bm 0x10 /* BOD Sample Frequency bit mask. */ -#define FUSE_SAMPFREQ_bp 4 /* BOD Sample Frequency bit position. */ -#define FUSE_LVL_gm 0xE0 /* BOD Level group mask. */ -#define FUSE_LVL_gp 5 /* BOD Level group position. */ -#define FUSE_LVL0_bm (1<<5) /* BOD Level bit 0 mask. */ -#define FUSE_LVL0_bp 5 /* BOD Level bit 0 position. */ -#define FUSE_LVL1_bm (1<<6) /* BOD Level bit 1 mask. */ -#define FUSE_LVL1_bp 6 /* BOD Level bit 1 position. */ -#define FUSE_LVL2_bm (1<<7) /* BOD Level bit 2 mask. */ -#define FUSE_LVL2_bp 7 /* BOD Level bit 2 position. */ - -/* FUSE.OSCCFG bit masks and bit positions */ -#define FUSE_FREQSEL_gm 0x03 /* Frequency Select group mask. */ -#define FUSE_FREQSEL_gp 0 /* Frequency Select group position. */ -#define FUSE_FREQSEL0_bm (1<<0) /* Frequency Select bit 0 mask. */ -#define FUSE_FREQSEL0_bp 0 /* Frequency Select bit 0 position. */ -#define FUSE_FREQSEL1_bm (1<<1) /* Frequency Select bit 1 mask. */ -#define FUSE_FREQSEL1_bp 1 /* Frequency Select bit 1 position. */ -#define FUSE_OSCLOCK_bm 0x80 /* Oscillator Lock bit mask. */ -#define FUSE_OSCLOCK_bp 7 /* Oscillator Lock bit position. */ - -/* FUSE.TCD0CFG bit masks and bit positions */ -#define FUSE_CMPA_bm 0x01 /* Compare A Default Output Value bit mask. */ -#define FUSE_CMPA_bp 0 /* Compare A Default Output Value bit position. */ -#define FUSE_CMPB_bm 0x02 /* Compare B Default Output Value bit mask. */ -#define FUSE_CMPB_bp 1 /* Compare B Default Output Value bit position. */ -#define FUSE_CMPC_bm 0x04 /* Compare C Default Output Value bit mask. */ -#define FUSE_CMPC_bp 2 /* Compare C Default Output Value bit position. */ -#define FUSE_CMPD_bm 0x08 /* Compare D Default Output Value bit mask. */ -#define FUSE_CMPD_bp 3 /* Compare D Default Output Value bit position. */ -#define FUSE_CMPAEN_bm 0x10 /* Compare A Output Enable bit mask. */ -#define FUSE_CMPAEN_bp 4 /* Compare A Output Enable bit position. */ -#define FUSE_CMPBEN_bm 0x20 /* Compare B Output Enable bit mask. */ -#define FUSE_CMPBEN_bp 5 /* Compare B Output Enable bit position. */ -#define FUSE_CMPCEN_bm 0x40 /* Compare C Output Enable bit mask. */ -#define FUSE_CMPCEN_bp 6 /* Compare C Output Enable bit position. */ -#define FUSE_CMPDEN_bm 0x80 /* Compare D Output Enable bit mask. */ -#define FUSE_CMPDEN_bp 7 /* Compare D Output Enable bit position. */ - -/* FUSE.SYSCFG0 bit masks and bit positions */ -#define FUSE_EESAVE_bm 0x01 /* EEPROM Save bit mask. */ -#define FUSE_EESAVE_bp 0 /* EEPROM Save bit position. */ -#define FUSE_RSTPINCFG_gm 0x0C /* Reset Pin Configuration group mask. */ -#define FUSE_RSTPINCFG_gp 2 /* Reset Pin Configuration group position. */ -#define FUSE_RSTPINCFG0_bm (1<<2) /* Reset Pin Configuration bit 0 mask. */ -#define FUSE_RSTPINCFG0_bp 2 /* Reset Pin Configuration bit 0 position. */ -#define FUSE_RSTPINCFG1_bm (1<<3) /* Reset Pin Configuration bit 1 mask. */ -#define FUSE_RSTPINCFG1_bp 3 /* Reset Pin Configuration bit 1 position. */ -#define FUSE_CRCSRC_gm 0xC0 /* CRC Source group mask. */ -#define FUSE_CRCSRC_gp 6 /* CRC Source group position. */ -#define FUSE_CRCSRC0_bm (1<<6) /* CRC Source bit 0 mask. */ -#define FUSE_CRCSRC0_bp 6 /* CRC Source bit 0 position. */ -#define FUSE_CRCSRC1_bm (1<<7) /* CRC Source bit 1 mask. */ -#define FUSE_CRCSRC1_bp 7 /* CRC Source bit 1 position. */ - -/* FUSE.SYSCFG1 bit masks and bit positions */ -#define FUSE_SUT_gm 0x07 /* Startup Time group mask. */ -#define FUSE_SUT_gp 0 /* Startup Time group position. */ -#define FUSE_SUT0_bm (1<<0) /* Startup Time bit 0 mask. */ -#define FUSE_SUT0_bp 0 /* Startup Time bit 0 position. */ -#define FUSE_SUT1_bm (1<<1) /* Startup Time bit 1 mask. */ -#define FUSE_SUT1_bp 1 /* Startup Time bit 1 position. */ -#define FUSE_SUT2_bm (1<<2) /* Startup Time bit 2 mask. */ -#define FUSE_SUT2_bp 2 /* Startup Time bit 2 position. */ - - - - - - - -/* LOCKBIT - Lockbit */ -/* LOCKBIT.LOCKBIT bit masks and bit positions */ -#define LOCKBIT_LB_gm 0xFF /* Lock Bits group mask. */ -#define LOCKBIT_LB_gp 0 /* Lock Bits group position. */ -#define LOCKBIT_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ -#define LOCKBIT_LB0_bp 0 /* Lock Bits bit 0 position. */ -#define LOCKBIT_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ -#define LOCKBIT_LB1_bp 1 /* Lock Bits bit 1 position. */ -#define LOCKBIT_LB2_bm (1<<2) /* Lock Bits bit 2 mask. */ -#define LOCKBIT_LB2_bp 2 /* Lock Bits bit 2 position. */ -#define LOCKBIT_LB3_bm (1<<3) /* Lock Bits bit 3 mask. */ -#define LOCKBIT_LB3_bp 3 /* Lock Bits bit 3 position. */ -#define LOCKBIT_LB4_bm (1<<4) /* Lock Bits bit 4 mask. */ -#define LOCKBIT_LB4_bp 4 /* Lock Bits bit 4 position. */ -#define LOCKBIT_LB5_bm (1<<5) /* Lock Bits bit 5 mask. */ -#define LOCKBIT_LB5_bp 5 /* Lock Bits bit 5 position. */ -#define LOCKBIT_LB6_bm (1<<6) /* Lock Bits bit 6 mask. */ -#define LOCKBIT_LB6_bp 6 /* Lock Bits bit 6 position. */ -#define LOCKBIT_LB7_bm (1<<7) /* Lock Bits bit 7 mask. */ -#define LOCKBIT_LB7_bp 7 /* Lock Bits bit 7 position. */ - -/* NVMBIST - BIST in the NVMCTRL module */ -/* NVMBIST.CTRLA bit masks and bit positions */ -#define NVMBIST_CMD_gm 0x07 /* Command group mask. */ -#define NVMBIST_CMD_gp 0 /* Command group position. */ -#define NVMBIST_CMD0_bm (1<<0) /* Command bit 0 mask. */ -#define NVMBIST_CMD0_bp 0 /* Command bit 0 position. */ -#define NVMBIST_CMD1_bm (1<<1) /* Command bit 1 mask. */ -#define NVMBIST_CMD1_bp 1 /* Command bit 1 position. */ -#define NVMBIST_CMD2_bm (1<<2) /* Command bit 2 mask. */ -#define NVMBIST_CMD2_bp 2 /* Command bit 2 position. */ -#define NVMBIST_SAF_bm 0x08 /* Stop at fault bit mask. */ -#define NVMBIST_SAF_bp 3 /* Stop at fault bit position. */ - -/* NVMBIST.ADDRPAT bit masks and bit positions */ -#define NVMBIST_XMODE_gm 0x03 /* X address mode group mask. */ -#define NVMBIST_XMODE_gp 0 /* X address mode group position. */ -#define NVMBIST_XMODE0_bm (1<<0) /* X address mode bit 0 mask. */ -#define NVMBIST_XMODE0_bp 0 /* X address mode bit 0 position. */ -#define NVMBIST_XMODE1_bm (1<<1) /* X address mode bit 1 mask. */ -#define NVMBIST_XMODE1_bp 1 /* X address mode bit 1 position. */ -#define NVMBIST_YMODE_gm 0x0C /* Y address mode group mask. */ -#define NVMBIST_YMODE_gp 2 /* Y address mode group position. */ -#define NVMBIST_YMODE0_bm (1<<2) /* Y address mode bit 0 mask. */ -#define NVMBIST_YMODE0_bp 2 /* Y address mode bit 0 position. */ -#define NVMBIST_YMODE1_bm (1<<3) /* Y address mode bit 1 mask. */ -#define NVMBIST_YMODE1_bp 3 /* Y address mode bit 1 position. */ -#define NVMBIST_AMODE_gm 0x70 /* Address mode group mask. */ -#define NVMBIST_AMODE_gp 4 /* Address mode group position. */ -#define NVMBIST_AMODE0_bm (1<<4) /* Address mode bit 0 mask. */ -#define NVMBIST_AMODE0_bp 4 /* Address mode bit 0 position. */ -#define NVMBIST_AMODE1_bm (1<<5) /* Address mode bit 1 mask. */ -#define NVMBIST_AMODE1_bp 5 /* Address mode bit 1 position. */ -#define NVMBIST_AMODE2_bm (1<<6) /* Address mode bit 2 mask. */ -#define NVMBIST_AMODE2_bp 6 /* Address mode bit 2 position. */ - -/* NVMBIST.DATAPAT bit masks and bit positions */ -#define NVMBIST_PATTERN_gm 0x03 /* Data check pattern group mask. */ -#define NVMBIST_PATTERN_gp 0 /* Data check pattern group position. */ -#define NVMBIST_PATTERN0_bm (1<<0) /* Data check pattern bit 0 mask. */ -#define NVMBIST_PATTERN0_bp 0 /* Data check pattern bit 0 position. */ -#define NVMBIST_PATTERN1_bm (1<<1) /* Data check pattern bit 1 mask. */ -#define NVMBIST_PATTERN1_bp 1 /* Data check pattern bit 1 position. */ - -/* NVMBIST.STATUS bit masks and bit positions */ -#define NVMBIST_STATE_gm 0x0F /* FSM State group mask. */ -#define NVMBIST_STATE_gp 0 /* FSM State group position. */ -#define NVMBIST_STATE0_bm (1<<0) /* FSM State bit 0 mask. */ -#define NVMBIST_STATE0_bp 0 /* FSM State bit 0 position. */ -#define NVMBIST_STATE1_bm (1<<1) /* FSM State bit 1 mask. */ -#define NVMBIST_STATE1_bp 1 /* FSM State bit 1 position. */ -#define NVMBIST_STATE2_bm (1<<2) /* FSM State bit 2 mask. */ -#define NVMBIST_STATE2_bp 2 /* FSM State bit 2 position. */ -#define NVMBIST_STATE3_bm (1<<3) /* FSM State bit 3 mask. */ -#define NVMBIST_STATE3_bp 3 /* FSM State bit 3 position. */ - -/* NVMBIST.CNT bit masks and bit positions */ -#define NVMBIST_CNT_gm 0x7FF /* Faults counter group mask. */ -#define NVMBIST_CNT_gp 0 /* Faults counter group position. */ -#define NVMBIST_CNT0_bm (1<<0) /* Faults counter bit 0 mask. */ -#define NVMBIST_CNT0_bp 0 /* Faults counter bit 0 position. */ -#define NVMBIST_CNT1_bm (1<<1) /* Faults counter bit 1 mask. */ -#define NVMBIST_CNT1_bp 1 /* Faults counter bit 1 position. */ -#define NVMBIST_CNT2_bm (1<<2) /* Faults counter bit 2 mask. */ -#define NVMBIST_CNT2_bp 2 /* Faults counter bit 2 position. */ -#define NVMBIST_CNT3_bm (1<<3) /* Faults counter bit 3 mask. */ -#define NVMBIST_CNT3_bp 3 /* Faults counter bit 3 position. */ -#define NVMBIST_CNT4_bm (1<<4) /* Faults counter bit 4 mask. */ -#define NVMBIST_CNT4_bp 4 /* Faults counter bit 4 position. */ -#define NVMBIST_CNT5_bm (1<<5) /* Faults counter bit 5 mask. */ -#define NVMBIST_CNT5_bp 5 /* Faults counter bit 5 position. */ -#define NVMBIST_CNT6_bm (1<<6) /* Faults counter bit 6 mask. */ -#define NVMBIST_CNT6_bp 6 /* Faults counter bit 6 position. */ -#define NVMBIST_CNT7_bm (1<<7) /* Faults counter bit 7 mask. */ -#define NVMBIST_CNT7_bp 7 /* Faults counter bit 7 position. */ -#define NVMBIST_CNT8_bm (1<<8) /* Faults counter bit 8 mask. */ -#define NVMBIST_CNT8_bp 8 /* Faults counter bit 8 position. */ -#define NVMBIST_CNT9_bm (1<<9) /* Faults counter bit 9 mask. */ -#define NVMBIST_CNT9_bp 9 /* Faults counter bit 9 position. */ -#define NVMBIST_CNT10_bm (1<<10) /* Faults counter bit 10 mask. */ -#define NVMBIST_CNT10_bp 10 /* Faults counter bit 10 position. */ - -/* NVMBIST.END bit masks and bit positions */ -#define NVMBIST_END_gm 0xFFFFFF /* group mask. */ -#define NVMBIST_END_gp 0 /* group position. */ -#define NVMBIST_END0_bm (1<<0) /* bit 0 mask. */ -#define NVMBIST_END0_bp 0 /* bit 0 position. */ -#define NVMBIST_END1_bm (1<<1) /* bit 1 mask. */ -#define NVMBIST_END1_bp 1 /* bit 1 position. */ -#define NVMBIST_END2_bm (1<<2) /* bit 2 mask. */ -#define NVMBIST_END2_bp 2 /* bit 2 position. */ -#define NVMBIST_END3_bm (1<<3) /* bit 3 mask. */ -#define NVMBIST_END3_bp 3 /* bit 3 position. */ -#define NVMBIST_END4_bm (1<<4) /* bit 4 mask. */ -#define NVMBIST_END4_bp 4 /* bit 4 position. */ -#define NVMBIST_END5_bm (1<<5) /* bit 5 mask. */ -#define NVMBIST_END5_bp 5 /* bit 5 position. */ -#define NVMBIST_END6_bm (1<<6) /* bit 6 mask. */ -#define NVMBIST_END6_bp 6 /* bit 6 position. */ -#define NVMBIST_END7_bm (1<<7) /* bit 7 mask. */ -#define NVMBIST_END7_bp 7 /* bit 7 position. */ -#define NVMBIST_END8_bm (1<<8) /* bit 8 mask. */ -#define NVMBIST_END8_bp 8 /* bit 8 position. */ -#define NVMBIST_END9_bm (1<<9) /* bit 9 mask. */ -#define NVMBIST_END9_bp 9 /* bit 9 position. */ -#define NVMBIST_END10_bm (1<<10) /* bit 10 mask. */ -#define NVMBIST_END10_bp 10 /* bit 10 position. */ -#define NVMBIST_END11_bm (1<<11) /* bit 11 mask. */ -#define NVMBIST_END11_bp 11 /* bit 11 position. */ -#define NVMBIST_END12_bm (1<<12) /* bit 12 mask. */ -#define NVMBIST_END12_bp 12 /* bit 12 position. */ -#define NVMBIST_END13_bm (1<<13) /* bit 13 mask. */ -#define NVMBIST_END13_bp 13 /* bit 13 position. */ -#define NVMBIST_END14_bm (1<<14) /* bit 14 mask. */ -#define NVMBIST_END14_bp 14 /* bit 14 position. */ -#define NVMBIST_END15_bm (1<<15) /* bit 15 mask. */ -#define NVMBIST_END15_bp 15 /* bit 15 position. */ -#define NVMBIST_END16_bm (1<<16) /* bit 16 mask. */ -#define NVMBIST_END16_bp 16 /* bit 16 position. */ -#define NVMBIST_END17_bm (1<<17) /* bit 17 mask. */ -#define NVMBIST_END17_bp 17 /* bit 17 position. */ -#define NVMBIST_END18_bm (1<<18) /* bit 18 mask. */ -#define NVMBIST_END18_bp 18 /* bit 18 position. */ -#define NVMBIST_END19_bm (1<<19) /* bit 19 mask. */ -#define NVMBIST_END19_bp 19 /* bit 19 position. */ -#define NVMBIST_END20_bm (1<<20) /* bit 20 mask. */ -#define NVMBIST_END20_bp 20 /* bit 20 position. */ -#define NVMBIST_END21_bm (1<<21) /* bit 21 mask. */ -#define NVMBIST_END21_bp 21 /* bit 21 position. */ -#define NVMBIST_END22_bm (1<<22) /* bit 22 mask. */ -#define NVMBIST_END22_bp 22 /* bit 22 position. */ -#define NVMBIST_END23_bm (1<<23) /* bit 23 mask. */ -#define NVMBIST_END23_bp 23 /* bit 23 position. */ - -/* NVMCTRL - Non-volatile Memory Controller */ -/* NVMCTRL.CTRLA bit masks and bit positions */ -#define NVMCTRL_CMD_gm 0x07 /* Command group mask. */ -#define NVMCTRL_CMD_gp 0 /* Command group position. */ -#define NVMCTRL_CMD0_bm (1<<0) /* Command bit 0 mask. */ -#define NVMCTRL_CMD0_bp 0 /* Command bit 0 position. */ -#define NVMCTRL_CMD1_bm (1<<1) /* Command bit 1 mask. */ -#define NVMCTRL_CMD1_bp 1 /* Command bit 1 position. */ -#define NVMCTRL_CMD2_bm (1<<2) /* Command bit 2 mask. */ -#define NVMCTRL_CMD2_bp 2 /* Command bit 2 position. */ - -/* NVMCTRL.CTRLB bit masks and bit positions */ -#define NVMCTRL_APCWP_bm 0x01 /* Application code write protect bit mask. */ -#define NVMCTRL_APCWP_bp 0 /* Application code write protect bit position. */ -#define NVMCTRL_BOOTLOCK_bm 0x02 /* Boot Lock bit mask. */ -#define NVMCTRL_BOOTLOCK_bp 1 /* Boot Lock bit position. */ - -/* NVMCTRL.STATUS bit masks and bit positions */ -#define NVMCTRL_FBUSY_bm 0x01 /* Flash busy bit mask. */ -#define NVMCTRL_FBUSY_bp 0 /* Flash busy bit position. */ -#define NVMCTRL_EEBUSY_bm 0x02 /* EEPROM busy bit mask. */ -#define NVMCTRL_EEBUSY_bp 1 /* EEPROM busy bit position. */ -#define NVMCTRL_WRERROR_bm 0x04 /* Write error bit mask. */ -#define NVMCTRL_WRERROR_bp 2 /* Write error bit position. */ - -/* NVMCTRL.INTCTRL bit masks and bit positions */ -#define NVMCTRL_EEREADY_bm 0x01 /* EEPROM Ready bit mask. */ -#define NVMCTRL_EEREADY_bp 0 /* EEPROM Ready bit position. */ - -/* NVMCTRL.INTFLAGS bit masks and bit positions */ -/* NVMCTRL_EEREADY is already defined. */ - - - - - - - - - - - - -/* PORT - I/O Ports */ -/* PORT.INTFLAGS bit masks and bit positions */ -#define PORT_INT_gm 0xFF /* Pin Interrupt group mask. */ -#define PORT_INT_gp 0 /* Pin Interrupt group position. */ -#define PORT_INT0_bm (1<<0) /* Pin Interrupt bit 0 mask. */ -#define PORT_INT0_bp 0 /* Pin Interrupt bit 0 position. */ -#define PORT_INT1_bm (1<<1) /* Pin Interrupt bit 1 mask. */ -#define PORT_INT1_bp 1 /* Pin Interrupt bit 1 position. */ -#define PORT_INT2_bm (1<<2) /* Pin Interrupt bit 2 mask. */ -#define PORT_INT2_bp 2 /* Pin Interrupt bit 2 position. */ -#define PORT_INT3_bm (1<<3) /* Pin Interrupt bit 3 mask. */ -#define PORT_INT3_bp 3 /* Pin Interrupt bit 3 position. */ -#define PORT_INT4_bm (1<<4) /* Pin Interrupt bit 4 mask. */ -#define PORT_INT4_bp 4 /* Pin Interrupt bit 4 position. */ -#define PORT_INT5_bm (1<<5) /* Pin Interrupt bit 5 mask. */ -#define PORT_INT5_bp 5 /* Pin Interrupt bit 5 position. */ -#define PORT_INT6_bm (1<<6) /* Pin Interrupt bit 6 mask. */ -#define PORT_INT6_bp 6 /* Pin Interrupt bit 6 position. */ -#define PORT_INT7_bm (1<<7) /* Pin Interrupt bit 7 mask. */ -#define PORT_INT7_bp 7 /* Pin Interrupt bit 7 position. */ - -/* PORT.PORTCTRL bit masks and bit positions */ -#define PORT_SRL_bm 0x01 /* Slew Rate Limit Enable bit mask. */ -#define PORT_SRL_bp 0 /* Slew Rate Limit Enable bit position. */ - -/* PORT.PIN0CTRL bit masks and bit positions */ -#define PORT_ISC_gm 0x07 /* Input/Sense Configuration group mask. */ -#define PORT_ISC_gp 0 /* Input/Sense Configuration group position. */ -#define PORT_ISC0_bm (1<<0) /* Input/Sense Configuration bit 0 mask. */ -#define PORT_ISC0_bp 0 /* Input/Sense Configuration bit 0 position. */ -#define PORT_ISC1_bm (1<<1) /* Input/Sense Configuration bit 1 mask. */ -#define PORT_ISC1_bp 1 /* Input/Sense Configuration bit 1 position. */ -#define PORT_ISC2_bm (1<<2) /* Input/Sense Configuration bit 2 mask. */ -#define PORT_ISC2_bp 2 /* Input/Sense Configuration bit 2 position. */ -#define PORT_PULLUPEN_bm 0x08 /* Pullup enable bit mask. */ -#define PORT_PULLUPEN_bp 3 /* Pullup enable bit position. */ -#define PORT_INVEN_bm 0x80 /* Inverted I/O Enable bit mask. */ -#define PORT_INVEN_bp 7 /* Inverted I/O Enable bit position. */ - -/* PORT.PIN1CTRL bit masks and bit positions */ -/* PORT_ISC is already defined. */ -/* PORT_PULLUPEN is already defined. */ -/* PORT_INVEN is already defined. */ - -/* PORT.PIN2CTRL bit masks and bit positions */ -/* PORT_ISC is already defined. */ -/* PORT_PULLUPEN is already defined. */ -/* PORT_INVEN is already defined. */ - -/* PORT.PIN3CTRL bit masks and bit positions */ -/* PORT_ISC is already defined. */ -/* PORT_PULLUPEN is already defined. */ -/* PORT_INVEN is already defined. */ - -/* PORT.PIN4CTRL bit masks and bit positions */ -/* PORT_ISC is already defined. */ -/* PORT_PULLUPEN is already defined. */ -/* PORT_INVEN is already defined. */ - -/* PORT.PIN5CTRL bit masks and bit positions */ -/* PORT_ISC is already defined. */ -/* PORT_PULLUPEN is already defined. */ -/* PORT_INVEN is already defined. */ - -/* PORT.PIN6CTRL bit masks and bit positions */ -/* PORT_ISC is already defined. */ -/* PORT_PULLUPEN is already defined. */ -/* PORT_INVEN is already defined. */ - -/* PORT.PIN7CTRL bit masks and bit positions */ -/* PORT_ISC is already defined. */ -/* PORT_PULLUPEN is already defined. */ -/* PORT_INVEN is already defined. */ - -/* PORTMUX - Port Multiplexer */ -/* PORTMUX.EVSYSROUTEA bit masks and bit positions */ -#define PORTMUX_EVOUT0_bm 0x01 /* Event Output 0 bit mask. */ -#define PORTMUX_EVOUT0_bp 0 /* Event Output 0 bit position. */ -#define PORTMUX_EVOUT1_bm 0x02 /* Event Output 1 bit mask. */ -#define PORTMUX_EVOUT1_bp 1 /* Event Output 1 bit position. */ -#define PORTMUX_EVOUT2_bm 0x04 /* Event Output 2 bit mask. */ -#define PORTMUX_EVOUT2_bp 2 /* Event Output 2 bit position. */ -#define PORTMUX_EVOUT3_bm 0x08 /* Event Output 3 bit mask. */ -#define PORTMUX_EVOUT3_bp 3 /* Event Output 3 bit position. */ -#define PORTMUX_EVOUT4_bm 0x10 /* Event Output 4 bit mask. */ -#define PORTMUX_EVOUT4_bp 4 /* Event Output 4 bit position. */ -#define PORTMUX_EVOUT5_bm 0x20 /* Event Output 5 bit mask. */ -#define PORTMUX_EVOUT5_bp 5 /* Event Output 5 bit position. */ - -/* PORTMUX.CCLROUTEA bit masks and bit positions */ -#define PORTMUX_LUT0_bm 0x01 /* CCL LUT0 bit mask. */ -#define PORTMUX_LUT0_bp 0 /* CCL LUT0 bit position. */ -#define PORTMUX_LUT1_bm 0x02 /* CCL LUT1 bit mask. */ -#define PORTMUX_LUT1_bp 1 /* CCL LUT1 bit position. */ -#define PORTMUX_LUT2_bm 0x04 /* CCL LUT2 bit mask. */ -#define PORTMUX_LUT2_bp 2 /* CCL LUT2 bit position. */ -#define PORTMUX_LUT3_bm 0x08 /* CCL LUT3 bit mask. */ -#define PORTMUX_LUT3_bp 3 /* CCL LUT3 bit position. */ - -/* PORTMUX.USARTROUTEA bit masks and bit positions */ -#define PORTMUX_USART0_gm 0x03 /* Port Multiplexer USART0 group mask. */ -#define PORTMUX_USART0_gp 0 /* Port Multiplexer USART0 group position. */ -#define PORTMUX_USART00_bm (1<<0) /* Port Multiplexer USART0 bit 0 mask. */ -#define PORTMUX_USART00_bp 0 /* Port Multiplexer USART0 bit 0 position. */ -#define PORTMUX_USART01_bm (1<<1) /* Port Multiplexer USART0 bit 1 mask. */ -#define PORTMUX_USART01_bp 1 /* Port Multiplexer USART0 bit 1 position. */ -#define PORTMUX_USART1_gm 0x0C /* Port Multiplexer USART1 group mask. */ -#define PORTMUX_USART1_gp 2 /* Port Multiplexer USART1 group position. */ -#define PORTMUX_USART10_bm (1<<2) /* Port Multiplexer USART1 bit 0 mask. */ -#define PORTMUX_USART10_bp 2 /* Port Multiplexer USART1 bit 0 position. */ -#define PORTMUX_USART11_bm (1<<3) /* Port Multiplexer USART1 bit 1 mask. */ -#define PORTMUX_USART11_bp 3 /* Port Multiplexer USART1 bit 1 position. */ -#define PORTMUX_USART2_gm 0x30 /* Port Multiplexer USART2 group mask. */ -#define PORTMUX_USART2_gp 4 /* Port Multiplexer USART2 group position. */ -#define PORTMUX_USART20_bm (1<<4) /* Port Multiplexer USART2 bit 0 mask. */ -#define PORTMUX_USART20_bp 4 /* Port Multiplexer USART2 bit 0 position. */ -#define PORTMUX_USART21_bm (1<<5) /* Port Multiplexer USART2 bit 1 mask. */ -#define PORTMUX_USART21_bp 5 /* Port Multiplexer USART2 bit 1 position. */ -#define PORTMUX_USART3_gm 0xC0 /* Port Multiplexer USART3 group mask. */ -#define PORTMUX_USART3_gp 6 /* Port Multiplexer USART3 group position. */ -#define PORTMUX_USART30_bm (1<<6) /* Port Multiplexer USART3 bit 0 mask. */ -#define PORTMUX_USART30_bp 6 /* Port Multiplexer USART3 bit 0 position. */ -#define PORTMUX_USART31_bm (1<<7) /* Port Multiplexer USART3 bit 1 mask. */ -#define PORTMUX_USART31_bp 7 /* Port Multiplexer USART3 bit 1 position. */ - -/* PORTMUX.TWISPIROUTEA bit masks and bit positions */ -#define PORTMUX_SPI0_gm 0x03 /* Port Multiplexer SPI0 group mask. */ -#define PORTMUX_SPI0_gp 0 /* Port Multiplexer SPI0 group position. */ -#define PORTMUX_SPI00_bm (1<<0) /* Port Multiplexer SPI0 bit 0 mask. */ -#define PORTMUX_SPI00_bp 0 /* Port Multiplexer SPI0 bit 0 position. */ -#define PORTMUX_SPI01_bm (1<<1) /* Port Multiplexer SPI0 bit 1 mask. */ -#define PORTMUX_SPI01_bp 1 /* Port Multiplexer SPI0 bit 1 position. */ -#define PORTMUX_TWI0_gm 0x30 /* Port Multiplexer TWI0 group mask. */ -#define PORTMUX_TWI0_gp 4 /* Port Multiplexer TWI0 group position. */ -#define PORTMUX_TWI00_bm (1<<4) /* Port Multiplexer TWI0 bit 0 mask. */ -#define PORTMUX_TWI00_bp 4 /* Port Multiplexer TWI0 bit 0 position. */ -#define PORTMUX_TWI01_bm (1<<5) /* Port Multiplexer TWI0 bit 1 mask. */ -#define PORTMUX_TWI01_bp 5 /* Port Multiplexer TWI0 bit 1 position. */ - -/* PORTMUX.TCAROUTEA bit masks and bit positions */ -#define PORTMUX_TCA0_gm 0x07 /* Port Multiplexer TCA0 group mask. */ -#define PORTMUX_TCA0_gp 0 /* Port Multiplexer TCA0 group position. */ -#define PORTMUX_TCA00_bm (1<<0) /* Port Multiplexer TCA0 bit 0 mask. */ -#define PORTMUX_TCA00_bp 0 /* Port Multiplexer TCA0 bit 0 position. */ -#define PORTMUX_TCA01_bm (1<<1) /* Port Multiplexer TCA0 bit 1 mask. */ -#define PORTMUX_TCA01_bp 1 /* Port Multiplexer TCA0 bit 1 position. */ -#define PORTMUX_TCA02_bm (1<<2) /* Port Multiplexer TCA0 bit 2 mask. */ -#define PORTMUX_TCA02_bp 2 /* Port Multiplexer TCA0 bit 2 position. */ - -/* PORTMUX.TCBROUTEA bit masks and bit positions */ -#define PORTMUX_TCB0_bm 0x01 /* Port Multiplexer TCB0 bit mask. */ -#define PORTMUX_TCB0_bp 0 /* Port Multiplexer TCB0 bit position. */ -#define PORTMUX_TCB1_bm 0x02 /* Port Multiplexer TCB1 bit mask. */ -#define PORTMUX_TCB1_bp 1 /* Port Multiplexer TCB1 bit position. */ -#define PORTMUX_TCB2_bm 0x04 /* Port Multiplexer TCB2 bit mask. */ -#define PORTMUX_TCB2_bp 2 /* Port Multiplexer TCB2 bit position. */ -#define PORTMUX_TCB3_bm 0x08 /* Port Multiplexer TCB3 bit mask. */ -#define PORTMUX_TCB3_bp 3 /* Port Multiplexer TCB3 bit position. */ - -/* RSTCTRL - Reset controller */ -/* RSTCTRL.RSTFR bit masks and bit positions */ -#define RSTCTRL_PORF_bm 0x01 /* Power on Reset flag bit mask. */ -#define RSTCTRL_PORF_bp 0 /* Power on Reset flag bit position. */ -#define RSTCTRL_BORF_bm 0x02 /* Brown out detector Reset flag bit mask. */ -#define RSTCTRL_BORF_bp 1 /* Brown out detector Reset flag bit position. */ -#define RSTCTRL_EXTRF_bm 0x04 /* External Reset flag bit mask. */ -#define RSTCTRL_EXTRF_bp 2 /* External Reset flag bit position. */ -#define RSTCTRL_WDRF_bm 0x08 /* Watch dog Reset flag bit mask. */ -#define RSTCTRL_WDRF_bp 3 /* Watch dog Reset flag bit position. */ -#define RSTCTRL_SWRF_bm 0x10 /* Software Reset flag bit mask. */ -#define RSTCTRL_SWRF_bp 4 /* Software Reset flag bit position. */ -#define RSTCTRL_UPDIRF_bm 0x20 /* UPDI Reset flag bit mask. */ -#define RSTCTRL_UPDIRF_bp 5 /* UPDI Reset flag bit position. */ - -/* RSTCTRL.SWRR bit masks and bit positions */ -#define RSTCTRL_SWRE_bm 0x01 /* Software reset enable bit mask. */ -#define RSTCTRL_SWRE_bp 0 /* Software reset enable bit position. */ - -/* RTC - Real-Time Counter */ -/* RTC.CTRLA bit masks and bit positions */ -#define RTC_RTCEN_bm 0x01 /* Enable bit mask. */ -#define RTC_RTCEN_bp 0 /* Enable bit position. */ -#define RTC_PRESCALER_gm 0x78 /* Prescaling Factor group mask. */ -#define RTC_PRESCALER_gp 3 /* Prescaling Factor group position. */ -#define RTC_PRESCALER0_bm (1<<3) /* Prescaling Factor bit 0 mask. */ -#define RTC_PRESCALER0_bp 3 /* Prescaling Factor bit 0 position. */ -#define RTC_PRESCALER1_bm (1<<4) /* Prescaling Factor bit 1 mask. */ -#define RTC_PRESCALER1_bp 4 /* Prescaling Factor bit 1 position. */ -#define RTC_PRESCALER2_bm (1<<5) /* Prescaling Factor bit 2 mask. */ -#define RTC_PRESCALER2_bp 5 /* Prescaling Factor bit 2 position. */ -#define RTC_PRESCALER3_bm (1<<6) /* Prescaling Factor bit 3 mask. */ -#define RTC_PRESCALER3_bp 6 /* Prescaling Factor bit 3 position. */ -#define RTC_RUNSTDBY_bm 0x80 /* Run In Standby bit mask. */ -#define RTC_RUNSTDBY_bp 7 /* Run In Standby bit position. */ - -/* RTC.STATUS bit masks and bit positions */ -#define RTC_CTRLABUSY_bm 0x01 /* CTRLA Synchronization Busy Flag bit mask. */ -#define RTC_CTRLABUSY_bp 0 /* CTRLA Synchronization Busy Flag bit position. */ -#define RTC_CNTBUSY_bm 0x02 /* Count Synchronization Busy Flag bit mask. */ -#define RTC_CNTBUSY_bp 1 /* Count Synchronization Busy Flag bit position. */ -#define RTC_PERBUSY_bm 0x04 /* Period Synchronization Busy Flag bit mask. */ -#define RTC_PERBUSY_bp 2 /* Period Synchronization Busy Flag bit position. */ -#define RTC_CMPBUSY_bm 0x08 /* Comparator Synchronization Busy Flag bit mask. */ -#define RTC_CMPBUSY_bp 3 /* Comparator Synchronization Busy Flag bit position. */ - -/* RTC.INTCTRL bit masks and bit positions */ -#define RTC_OVF_bm 0x01 /* Overflow Interrupt enable bit mask. */ -#define RTC_OVF_bp 0 /* Overflow Interrupt enable bit position. */ -#define RTC_CMP_bm 0x02 /* Compare Match Interrupt enable bit mask. */ -#define RTC_CMP_bp 1 /* Compare Match Interrupt enable bit position. */ - -/* RTC.INTFLAGS bit masks and bit positions */ -/* RTC_OVF is already defined. */ -/* RTC_CMP is already defined. */ - - -/* RTC.DBGCTRL bit masks and bit positions */ -#define RTC_DBGRUN_bm 0x01 /* Run in debug bit mask. */ -#define RTC_DBGRUN_bp 0 /* Run in debug bit position. */ - -/* RTC.CLKSEL bit masks and bit positions */ -#define RTC_CLKSEL_gm 0x03 /* Clock Select group mask. */ -#define RTC_CLKSEL_gp 0 /* Clock Select group position. */ -#define RTC_CLKSEL0_bm (1<<0) /* Clock Select bit 0 mask. */ -#define RTC_CLKSEL0_bp 0 /* Clock Select bit 0 position. */ -#define RTC_CLKSEL1_bm (1<<1) /* Clock Select bit 1 mask. */ -#define RTC_CLKSEL1_bp 1 /* Clock Select bit 1 position. */ - - - - -/* RTC.PITCTRLA bit masks and bit positions */ -#define RTC_PITEN_bm 0x01 /* Enable bit mask. */ -#define RTC_PITEN_bp 0 /* Enable bit position. */ -#define RTC_PERIOD_gm 0x78 /* Period group mask. */ -#define RTC_PERIOD_gp 3 /* Period group position. */ -#define RTC_PERIOD0_bm (1<<3) /* Period bit 0 mask. */ -#define RTC_PERIOD0_bp 3 /* Period bit 0 position. */ -#define RTC_PERIOD1_bm (1<<4) /* Period bit 1 mask. */ -#define RTC_PERIOD1_bp 4 /* Period bit 1 position. */ -#define RTC_PERIOD2_bm (1<<5) /* Period bit 2 mask. */ -#define RTC_PERIOD2_bp 5 /* Period bit 2 position. */ -#define RTC_PERIOD3_bm (1<<6) /* Period bit 3 mask. */ -#define RTC_PERIOD3_bp 6 /* Period bit 3 position. */ - -/* RTC.PITSTATUS bit masks and bit positions */ -#define RTC_CTRLBUSY_bm 0x01 /* CTRLA Synchronization Busy Flag bit mask. */ -#define RTC_CTRLBUSY_bp 0 /* CTRLA Synchronization Busy Flag bit position. */ - -/* RTC.PITINTCTRL bit masks and bit positions */ -#define RTC_PI_bm 0x01 /* Periodic Interrupt bit mask. */ -#define RTC_PI_bp 0 /* Periodic Interrupt bit position. */ - -/* RTC.PITINTFLAGS bit masks and bit positions */ -/* RTC_PI is already defined. */ - -/* RTC.PITDBGCTRL bit masks and bit positions */ -/* RTC_DBGRUN is already defined. */ - - - - - - - - - - - - - - - - - - - - - - - - - - -/* SLPCTRL - Sleep Controller */ -/* SLPCTRL.CTRLA bit masks and bit positions */ -#define SLPCTRL_SEN_bm 0x01 /* Sleep enable bit mask. */ -#define SLPCTRL_SEN_bp 0 /* Sleep enable bit position. */ -#define SLPCTRL_SMODE_gm 0x06 /* Sleep mode group mask. */ -#define SLPCTRL_SMODE_gp 1 /* Sleep mode group position. */ -#define SLPCTRL_SMODE0_bm (1<<1) /* Sleep mode bit 0 mask. */ -#define SLPCTRL_SMODE0_bp 1 /* Sleep mode bit 0 position. */ -#define SLPCTRL_SMODE1_bm (1<<2) /* Sleep mode bit 1 mask. */ -#define SLPCTRL_SMODE1_bp 2 /* Sleep mode bit 1 position. */ - -/* SPI - Serial Peripheral Interface */ -/* SPI.CTRLA bit masks and bit positions */ -#define SPI_ENABLE_bm 0x01 /* Enable Module bit mask. */ -#define SPI_ENABLE_bp 0 /* Enable Module bit position. */ -#define SPI_PRESC_gm 0x06 /* Prescaler group mask. */ -#define SPI_PRESC_gp 1 /* Prescaler group position. */ -#define SPI_PRESC0_bm (1<<1) /* Prescaler bit 0 mask. */ -#define SPI_PRESC0_bp 1 /* Prescaler bit 0 position. */ -#define SPI_PRESC1_bm (1<<2) /* Prescaler bit 1 mask. */ -#define SPI_PRESC1_bp 2 /* Prescaler bit 1 position. */ -#define SPI_CLK2X_bm 0x10 /* Enable Double Speed bit mask. */ -#define SPI_CLK2X_bp 4 /* Enable Double Speed bit position. */ -#define SPI_MASTER_bm 0x20 /* Master Operation Enable bit mask. */ -#define SPI_MASTER_bp 5 /* Master Operation Enable bit position. */ -#define SPI_DORD_bm 0x40 /* Data Order Setting bit mask. */ -#define SPI_DORD_bp 6 /* Data Order Setting bit position. */ - -/* SPI.CTRLB bit masks and bit positions */ -#define SPI_MODE_gm 0x03 /* SPI Mode group mask. */ -#define SPI_MODE_gp 0 /* SPI Mode group position. */ -#define SPI_MODE0_bm (1<<0) /* SPI Mode bit 0 mask. */ -#define SPI_MODE0_bp 0 /* SPI Mode bit 0 position. */ -#define SPI_MODE1_bm (1<<1) /* SPI Mode bit 1 mask. */ -#define SPI_MODE1_bp 1 /* SPI Mode bit 1 position. */ -#define SPI_SSD_bm 0x04 /* Slave Select Disable bit mask. */ -#define SPI_SSD_bp 2 /* Slave Select Disable bit position. */ -#define SPI_BUFWR_bm 0x40 /* Buffer Write Mode bit mask. */ -#define SPI_BUFWR_bp 6 /* Buffer Write Mode bit position. */ -#define SPI_BUFEN_bm 0x80 /* Buffer Mode Enable bit mask. */ -#define SPI_BUFEN_bp 7 /* Buffer Mode Enable bit position. */ - -/* SPI.INTCTRL bit masks and bit positions */ -#define SPI_IE_bm 0x01 /* Interrupt Enable bit mask. */ -#define SPI_IE_bp 0 /* Interrupt Enable bit position. */ -#define SPI_SSIE_bm 0x10 /* Slave Select Trigger Interrupt Enable bit mask. */ -#define SPI_SSIE_bp 4 /* Slave Select Trigger Interrupt Enable bit position. */ -#define SPI_DREIE_bm 0x20 /* Data Register Empty Interrupt Enable bit mask. */ -#define SPI_DREIE_bp 5 /* Data Register Empty Interrupt Enable bit position. */ -#define SPI_TXCIE_bm 0x40 /* Transfer Complete Interrupt Enable bit mask. */ -#define SPI_TXCIE_bp 6 /* Transfer Complete Interrupt Enable bit position. */ -#define SPI_RXCIE_bm 0x80 /* Receive Complete Interrupt Enable bit mask. */ -#define SPI_RXCIE_bp 7 /* Receive Complete Interrupt Enable bit position. */ - -/* SPI.INTFLAGS bit masks and bit positions */ -#define SPI_BUFOVF_bm 0x01 /* Buffer Overflow bit mask. */ -#define SPI_BUFOVF_bp 0 /* Buffer Overflow bit position. */ -#define SPI_SSIF_bm 0x10 /* Slave Select Trigger Interrupt Flag bit mask. */ -#define SPI_SSIF_bp 4 /* Slave Select Trigger Interrupt Flag bit position. */ -#define SPI_DREIF_bm 0x20 /* Data Register Empty Interrupt Flag bit mask. */ -#define SPI_DREIF_bp 5 /* Data Register Empty Interrupt Flag bit position. */ -#define SPI_TXCIF_bm 0x40 /* Transfer Complete Interrupt Flag bit mask. */ -#define SPI_TXCIF_bp 6 /* Transfer Complete Interrupt Flag bit position. */ -#define SPI_WRCOL_bm 0x40 /* Write Collision bit mask. */ -#define SPI_WRCOL_bp 6 /* Write Collision bit position. */ -#define SPI_RXCIF_bm 0x80 /* Receive Complete Interrupt Flag bit mask. */ -#define SPI_RXCIF_bp 7 /* Receive Complete Interrupt Flag bit position. */ -#define SPI_IF_bm 0x80 /* Interrupt Flag bit mask. */ -#define SPI_IF_bp 7 /* Interrupt Flag bit position. */ - - - -/* SYSCFG - System Configuration Registers */ -/* SYSCFG.EXTBRK bit masks and bit positions */ -#define SYSCFG_ENEXTBRK_bm 0x01 /* External break enable bit mask. */ -#define SYSCFG_ENEXTBRK_bp 0 /* External break enable bit position. */ - - -/* SYSCFG.OCDMS bit masks and bit positions */ -#define SYSCFG_OCDMR_bm 0x01 /* OCD Message Read bit mask. */ -#define SYSCFG_OCDMR_bp 0 /* OCD Message Read bit position. */ - -/* TCA - 16-bit Timer/Counter Type A */ -/* TCA_SINGLE.CTRLA bit masks and bit positions */ -#define TCA_SINGLE_ENABLE_bm 0x01 /* Module Enable bit mask. */ -#define TCA_SINGLE_ENABLE_bp 0 /* Module Enable bit position. */ -#define TCA_SINGLE_CLKSEL_gm 0x0E /* Clock Selection group mask. */ -#define TCA_SINGLE_CLKSEL_gp 1 /* Clock Selection group position. */ -#define TCA_SINGLE_CLKSEL0_bm (1<<1) /* Clock Selection bit 0 mask. */ -#define TCA_SINGLE_CLKSEL0_bp 1 /* Clock Selection bit 0 position. */ -#define TCA_SINGLE_CLKSEL1_bm (1<<2) /* Clock Selection bit 1 mask. */ -#define TCA_SINGLE_CLKSEL1_bp 2 /* Clock Selection bit 1 position. */ -#define TCA_SINGLE_CLKSEL2_bm (1<<3) /* Clock Selection bit 2 mask. */ -#define TCA_SINGLE_CLKSEL2_bp 3 /* Clock Selection bit 2 position. */ - -/* TCA_SINGLE.CTRLB bit masks and bit positions */ -#define TCA_SINGLE_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ -#define TCA_SINGLE_WGMODE_gp 0 /* Waveform generation mode group position. */ -#define TCA_SINGLE_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ -#define TCA_SINGLE_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ -#define TCA_SINGLE_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ -#define TCA_SINGLE_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ -#define TCA_SINGLE_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ -#define TCA_SINGLE_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ -#define TCA_SINGLE_ALUPD_bm 0x08 /* Auto Lock Update bit mask. */ -#define TCA_SINGLE_ALUPD_bp 3 /* Auto Lock Update bit position. */ -#define TCA_SINGLE_CMP0EN_bm 0x10 /* Compare 0 Enable bit mask. */ -#define TCA_SINGLE_CMP0EN_bp 4 /* Compare 0 Enable bit position. */ -#define TCA_SINGLE_CMP1EN_bm 0x20 /* Compare 1 Enable bit mask. */ -#define TCA_SINGLE_CMP1EN_bp 5 /* Compare 1 Enable bit position. */ -#define TCA_SINGLE_CMP2EN_bm 0x40 /* Compare 2 Enable bit mask. */ -#define TCA_SINGLE_CMP2EN_bp 6 /* Compare 2 Enable bit position. */ - -/* TCA_SINGLE.CTRLC bit masks and bit positions */ -#define TCA_SINGLE_CMP0OV_bm 0x01 /* Compare 0 Waveform Output Value bit mask. */ -#define TCA_SINGLE_CMP0OV_bp 0 /* Compare 0 Waveform Output Value bit position. */ -#define TCA_SINGLE_CMP1OV_bm 0x02 /* Compare 1 Waveform Output Value bit mask. */ -#define TCA_SINGLE_CMP1OV_bp 1 /* Compare 1 Waveform Output Value bit position. */ -#define TCA_SINGLE_CMP2OV_bm 0x04 /* Compare 2 Waveform Output Value bit mask. */ -#define TCA_SINGLE_CMP2OV_bp 2 /* Compare 2 Waveform Output Value bit position. */ - -/* TCA_SINGLE.CTRLD bit masks and bit positions */ -#define TCA_SINGLE_SPLITM_bm 0x01 /* Split Mode Enable bit mask. */ -#define TCA_SINGLE_SPLITM_bp 0 /* Split Mode Enable bit position. */ - -/* TCA_SINGLE.CTRLECLR bit masks and bit positions */ -#define TCA_SINGLE_DIR_bm 0x01 /* Direction bit mask. */ -#define TCA_SINGLE_DIR_bp 0 /* Direction bit position. */ -#define TCA_SINGLE_LUPD_bm 0x02 /* Lock Update bit mask. */ -#define TCA_SINGLE_LUPD_bp 1 /* Lock Update bit position. */ -#define TCA_SINGLE_CMD_gm 0x0C /* Command group mask. */ -#define TCA_SINGLE_CMD_gp 2 /* Command group position. */ -#define TCA_SINGLE_CMD0_bm (1<<2) /* Command bit 0 mask. */ -#define TCA_SINGLE_CMD0_bp 2 /* Command bit 0 position. */ -#define TCA_SINGLE_CMD1_bm (1<<3) /* Command bit 1 mask. */ -#define TCA_SINGLE_CMD1_bp 3 /* Command bit 1 position. */ - -/* TCA_SINGLE.CTRLESET bit masks and bit positions */ -/* TCA_SINGLE_DIR is already defined. */ -/* TCA_SINGLE_LUPD is already defined. */ -/* TCA_SINGLE_CMD is already defined. */ - -/* TCA_SINGLE.CTRLFCLR bit masks and bit positions */ -#define TCA_SINGLE_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ -#define TCA_SINGLE_PERBV_bp 0 /* Period Buffer Valid bit position. */ -#define TCA_SINGLE_CMP0BV_bm 0x02 /* Compare 0 Buffer Valid bit mask. */ -#define TCA_SINGLE_CMP0BV_bp 1 /* Compare 0 Buffer Valid bit position. */ -#define TCA_SINGLE_CMP1BV_bm 0x04 /* Compare 1 Buffer Valid bit mask. */ -#define TCA_SINGLE_CMP1BV_bp 2 /* Compare 1 Buffer Valid bit position. */ -#define TCA_SINGLE_CMP2BV_bm 0x08 /* Compare 2 Buffer Valid bit mask. */ -#define TCA_SINGLE_CMP2BV_bp 3 /* Compare 2 Buffer Valid bit position. */ - -/* TCA_SINGLE.CTRLFSET bit masks and bit positions */ -/* TCA_SINGLE_PERBV is already defined. */ -/* TCA_SINGLE_CMP0BV is already defined. */ -/* TCA_SINGLE_CMP1BV is already defined. */ -/* TCA_SINGLE_CMP2BV is already defined. */ - -/* TCA_SINGLE.EVCTRL bit masks and bit positions */ -#define TCA_SINGLE_CNTEI_bm 0x01 /* Count on Event Input bit mask. */ -#define TCA_SINGLE_CNTEI_bp 0 /* Count on Event Input bit position. */ -#define TCA_SINGLE_EVACT_gm 0x06 /* Event Action group mask. */ -#define TCA_SINGLE_EVACT_gp 1 /* Event Action group position. */ -#define TCA_SINGLE_EVACT0_bm (1<<1) /* Event Action bit 0 mask. */ -#define TCA_SINGLE_EVACT0_bp 1 /* Event Action bit 0 position. */ -#define TCA_SINGLE_EVACT1_bm (1<<2) /* Event Action bit 1 mask. */ -#define TCA_SINGLE_EVACT1_bp 2 /* Event Action bit 1 position. */ - -/* TCA_SINGLE.INTCTRL bit masks and bit positions */ -#define TCA_SINGLE_OVF_bm 0x01 /* Overflow Interrupt bit mask. */ -#define TCA_SINGLE_OVF_bp 0 /* Overflow Interrupt bit position. */ -#define TCA_SINGLE_CMP0_bm 0x10 /* Compare 0 Interrupt bit mask. */ -#define TCA_SINGLE_CMP0_bp 4 /* Compare 0 Interrupt bit position. */ -#define TCA_SINGLE_CMP1_bm 0x20 /* Compare 1 Interrupt bit mask. */ -#define TCA_SINGLE_CMP1_bp 5 /* Compare 1 Interrupt bit position. */ -#define TCA_SINGLE_CMP2_bm 0x40 /* Compare 2 Interrupt bit mask. */ -#define TCA_SINGLE_CMP2_bp 6 /* Compare 2 Interrupt bit position. */ - -/* TCA_SINGLE.INTFLAGS bit masks and bit positions */ -/* TCA_SINGLE_OVF is already defined. */ -/* TCA_SINGLE_CMP0 is already defined. */ -/* TCA_SINGLE_CMP1 is already defined. */ -/* TCA_SINGLE_CMP2 is already defined. */ - -/* TCA_SINGLE.DBGCTRL bit masks and bit positions */ -#define TCA_SINGLE_DBGRUN_bm 0x01 /* Debug Run bit mask. */ -#define TCA_SINGLE_DBGRUN_bp 0 /* Debug Run bit position. */ - - - - - - - - - - - -/* TCA_SPLIT.CTRLA bit masks and bit positions */ -#define TCA_SPLIT_ENABLE_bm 0x01 /* Module Enable bit mask. */ -#define TCA_SPLIT_ENABLE_bp 0 /* Module Enable bit position. */ -#define TCA_SPLIT_CLKSEL_gm 0x0E /* Clock Selection group mask. */ -#define TCA_SPLIT_CLKSEL_gp 1 /* Clock Selection group position. */ -#define TCA_SPLIT_CLKSEL0_bm (1<<1) /* Clock Selection bit 0 mask. */ -#define TCA_SPLIT_CLKSEL0_bp 1 /* Clock Selection bit 0 position. */ -#define TCA_SPLIT_CLKSEL1_bm (1<<2) /* Clock Selection bit 1 mask. */ -#define TCA_SPLIT_CLKSEL1_bp 2 /* Clock Selection bit 1 position. */ -#define TCA_SPLIT_CLKSEL2_bm (1<<3) /* Clock Selection bit 2 mask. */ -#define TCA_SPLIT_CLKSEL2_bp 3 /* Clock Selection bit 2 position. */ - -/* TCA_SPLIT.CTRLB bit masks and bit positions */ -#define TCA_SPLIT_LCMP0EN_bm 0x01 /* Low Compare 0 Enable bit mask. */ -#define TCA_SPLIT_LCMP0EN_bp 0 /* Low Compare 0 Enable bit position. */ -#define TCA_SPLIT_LCMP1EN_bm 0x02 /* Low Compare 1 Enable bit mask. */ -#define TCA_SPLIT_LCMP1EN_bp 1 /* Low Compare 1 Enable bit position. */ -#define TCA_SPLIT_LCMP2EN_bm 0x04 /* Low Compare 2 Enable bit mask. */ -#define TCA_SPLIT_LCMP2EN_bp 2 /* Low Compare 2 Enable bit position. */ -#define TCA_SPLIT_HCMP0EN_bm 0x10 /* High Compare 0 Enable bit mask. */ -#define TCA_SPLIT_HCMP0EN_bp 4 /* High Compare 0 Enable bit position. */ -#define TCA_SPLIT_HCMP1EN_bm 0x20 /* High Compare 1 Enable bit mask. */ -#define TCA_SPLIT_HCMP1EN_bp 5 /* High Compare 1 Enable bit position. */ -#define TCA_SPLIT_HCMP2EN_bm 0x40 /* High Compare 2 Enable bit mask. */ -#define TCA_SPLIT_HCMP2EN_bp 6 /* High Compare 2 Enable bit position. */ - -/* TCA_SPLIT.CTRLC bit masks and bit positions */ -#define TCA_SPLIT_LCMP0OV_bm 0x01 /* Low Compare 0 Output Value bit mask. */ -#define TCA_SPLIT_LCMP0OV_bp 0 /* Low Compare 0 Output Value bit position. */ -#define TCA_SPLIT_LCMP1OV_bm 0x02 /* Low Compare 1 Output Value bit mask. */ -#define TCA_SPLIT_LCMP1OV_bp 1 /* Low Compare 1 Output Value bit position. */ -#define TCA_SPLIT_LCMP2OV_bm 0x04 /* Low Compare 2 Output Value bit mask. */ -#define TCA_SPLIT_LCMP2OV_bp 2 /* Low Compare 2 Output Value bit position. */ -#define TCA_SPLIT_HCMP0OV_bm 0x10 /* High Compare 0 Output Value bit mask. */ -#define TCA_SPLIT_HCMP0OV_bp 4 /* High Compare 0 Output Value bit position. */ -#define TCA_SPLIT_HCMP1OV_bm 0x20 /* High Compare 1 Output Value bit mask. */ -#define TCA_SPLIT_HCMP1OV_bp 5 /* High Compare 1 Output Value bit position. */ -#define TCA_SPLIT_HCMP2OV_bm 0x40 /* High Compare 2 Output Value bit mask. */ -#define TCA_SPLIT_HCMP2OV_bp 6 /* High Compare 2 Output Value bit position. */ - -/* TCA_SPLIT.CTRLD bit masks and bit positions */ -#define TCA_SPLIT_SPLITM_bm 0x01 /* Split Mode Enable bit mask. */ -#define TCA_SPLIT_SPLITM_bp 0 /* Split Mode Enable bit position. */ - -/* TCA_SPLIT.CTRLECLR bit masks and bit positions */ -#define TCA_SPLIT_CMD_gm 0x0C /* Command group mask. */ -#define TCA_SPLIT_CMD_gp 2 /* Command group position. */ -#define TCA_SPLIT_CMD0_bm (1<<2) /* Command bit 0 mask. */ -#define TCA_SPLIT_CMD0_bp 2 /* Command bit 0 position. */ -#define TCA_SPLIT_CMD1_bm (1<<3) /* Command bit 1 mask. */ -#define TCA_SPLIT_CMD1_bp 3 /* Command bit 1 position. */ - -/* TCA_SPLIT.CTRLESET bit masks and bit positions */ -/* TCA_SPLIT_CMD is already defined. */ - -/* TCA_SPLIT.INTCTRL bit masks and bit positions */ -#define TCA_SPLIT_LUNF_bm 0x01 /* Low Underflow Interrupt Enable bit mask. */ -#define TCA_SPLIT_LUNF_bp 0 /* Low Underflow Interrupt Enable bit position. */ -#define TCA_SPLIT_HUNF_bm 0x02 /* High Underflow Interrupt Enable bit mask. */ -#define TCA_SPLIT_HUNF_bp 1 /* High Underflow Interrupt Enable bit position. */ -#define TCA_SPLIT_LCMP0_bm 0x10 /* Low Compare 0 Interrupt Enable bit mask. */ -#define TCA_SPLIT_LCMP0_bp 4 /* Low Compare 0 Interrupt Enable bit position. */ -#define TCA_SPLIT_LCMP1_bm 0x20 /* Low Compare 1 Interrupt Enable bit mask. */ -#define TCA_SPLIT_LCMP1_bp 5 /* Low Compare 1 Interrupt Enable bit position. */ -#define TCA_SPLIT_LCMP2_bm 0x40 /* Low Compare 2 Interrupt Enable bit mask. */ -#define TCA_SPLIT_LCMP2_bp 6 /* Low Compare 2 Interrupt Enable bit position. */ - -/* TCA_SPLIT.INTFLAGS bit masks and bit positions */ -/* TCA_SPLIT_LUNF is already defined. */ -/* TCA_SPLIT_HUNF is already defined. */ -/* TCA_SPLIT_LCMP0 is already defined. */ -/* TCA_SPLIT_LCMP1 is already defined. */ -/* TCA_SPLIT_LCMP2 is already defined. */ - -/* TCA_SPLIT.DBGCTRL bit masks and bit positions */ -#define TCA_SPLIT_DBGRUN_bm 0x01 /* Debug Run bit mask. */ -#define TCA_SPLIT_DBGRUN_bp 0 /* Debug Run bit position. */ - - - - - - - - - - - -/* TCB - 16-bit Timer Type B */ -/* TCB.CTRLA bit masks and bit positions */ -#define TCB_ENABLE_bm 0x01 /* Enable bit mask. */ -#define TCB_ENABLE_bp 0 /* Enable bit position. */ -#define TCB_CLKSEL_gm 0x06 /* Clock Select group mask. */ -#define TCB_CLKSEL_gp 1 /* Clock Select group position. */ -#define TCB_CLKSEL0_bm (1<<1) /* Clock Select bit 0 mask. */ -#define TCB_CLKSEL0_bp 1 /* Clock Select bit 0 position. */ -#define TCB_CLKSEL1_bm (1<<2) /* Clock Select bit 1 mask. */ -#define TCB_CLKSEL1_bp 2 /* Clock Select bit 1 position. */ -#define TCB_SYNCUPD_bm 0x10 /* Synchronize Update bit mask. */ -#define TCB_SYNCUPD_bp 4 /* Synchronize Update bit position. */ -#define TCB_RUNSTDBY_bm 0x40 /* Run Standby bit mask. */ -#define TCB_RUNSTDBY_bp 6 /* Run Standby bit position. */ - -/* TCB.CTRLB bit masks and bit positions */ -#define TCB_CNTMODE_gm 0x07 /* Timer Mode group mask. */ -#define TCB_CNTMODE_gp 0 /* Timer Mode group position. */ -#define TCB_CNTMODE0_bm (1<<0) /* Timer Mode bit 0 mask. */ -#define TCB_CNTMODE0_bp 0 /* Timer Mode bit 0 position. */ -#define TCB_CNTMODE1_bm (1<<1) /* Timer Mode bit 1 mask. */ -#define TCB_CNTMODE1_bp 1 /* Timer Mode bit 1 position. */ -#define TCB_CNTMODE2_bm (1<<2) /* Timer Mode bit 2 mask. */ -#define TCB_CNTMODE2_bp 2 /* Timer Mode bit 2 position. */ -#define TCB_CCMPEN_bm 0x10 /* Pin Output Enable bit mask. */ -#define TCB_CCMPEN_bp 4 /* Pin Output Enable bit position. */ -#define TCB_CCMPINIT_bm 0x20 /* Pin Initial State bit mask. */ -#define TCB_CCMPINIT_bp 5 /* Pin Initial State bit position. */ -#define TCB_ASYNC_bm 0x40 /* Asynchronous Enable bit mask. */ -#define TCB_ASYNC_bp 6 /* Asynchronous Enable bit position. */ - -/* TCB.EVCTRL bit masks and bit positions */ -#define TCB_CAPTEI_bm 0x01 /* Event Input Enable bit mask. */ -#define TCB_CAPTEI_bp 0 /* Event Input Enable bit position. */ -#define TCB_EDGE_bm 0x10 /* Event Edge bit mask. */ -#define TCB_EDGE_bp 4 /* Event Edge bit position. */ -#define TCB_FILTER_bm 0x40 /* Input Capture Noise Cancellation Filter bit mask. */ -#define TCB_FILTER_bp 6 /* Input Capture Noise Cancellation Filter bit position. */ - -/* TCB.INTCTRL bit masks and bit positions */ -#define TCB_CAPT_bm 0x01 /* Capture or Timeout bit mask. */ -#define TCB_CAPT_bp 0 /* Capture or Timeout bit position. */ - -/* TCB.INTFLAGS bit masks and bit positions */ -/* TCB_CAPT is already defined. */ - -/* TCB.STATUS bit masks and bit positions */ -#define TCB_RUN_bm 0x01 /* Run bit mask. */ -#define TCB_RUN_bp 0 /* Run bit position. */ - -/* TCB.DBGCTRL bit masks and bit positions */ -#define TCB_DBGRUN_bm 0x01 /* Debug Run bit mask. */ -#define TCB_DBGRUN_bp 0 /* Debug Run bit position. */ - - - - -/* TWI - Two-Wire Interface */ -/* TWI.CTRLA bit masks and bit positions */ -#define TWI_FMPEN_bm 0x02 /* FM Plus Enable bit mask. */ -#define TWI_FMPEN_bp 1 /* FM Plus Enable bit position. */ -#define TWI_SDAHOLD_gm 0x0C /* SDA Hold Time group mask. */ -#define TWI_SDAHOLD_gp 2 /* SDA Hold Time group position. */ -#define TWI_SDAHOLD0_bm (1<<2) /* SDA Hold Time bit 0 mask. */ -#define TWI_SDAHOLD0_bp 2 /* SDA Hold Time bit 0 position. */ -#define TWI_SDAHOLD1_bm (1<<3) /* SDA Hold Time bit 1 mask. */ -#define TWI_SDAHOLD1_bp 3 /* SDA Hold Time bit 1 position. */ -#define TWI_SDASETUP_bm 0x10 /* SDA Setup Time bit mask. */ -#define TWI_SDASETUP_bp 4 /* SDA Setup Time bit position. */ - -/* TWI.BRIDGECTRL bit masks and bit positions */ -#define TWI_ENABLE_bm 0x01 /* Bridge Enable bit mask. */ -#define TWI_ENABLE_bp 0 /* Bridge Enable bit position. */ -/* TWI_FMPEN is already defined. */ -/* TWI_SDAHOLD is already defined. */ - -/* TWI.DBGCTRL bit masks and bit positions */ -#define TWI_DBGRUN_bm 0x01 /* Debug Run bit mask. */ -#define TWI_DBGRUN_bp 0 /* Debug Run bit position. */ - -/* TWI.MCTRLA bit masks and bit positions */ -/* TWI_ENABLE is already defined. */ -#define TWI_SMEN_bm 0x02 /* Smart Mode Enable bit mask. */ -#define TWI_SMEN_bp 1 /* Smart Mode Enable bit position. */ -#define TWI_TIMEOUT_gm 0x0C /* Inactive Bus Timeout group mask. */ -#define TWI_TIMEOUT_gp 2 /* Inactive Bus Timeout group position. */ -#define TWI_TIMEOUT0_bm (1<<2) /* Inactive Bus Timeout bit 0 mask. */ -#define TWI_TIMEOUT0_bp 2 /* Inactive Bus Timeout bit 0 position. */ -#define TWI_TIMEOUT1_bm (1<<3) /* Inactive Bus Timeout bit 1 mask. */ -#define TWI_TIMEOUT1_bp 3 /* Inactive Bus Timeout bit 1 position. */ -#define TWI_QCEN_bm 0x10 /* Quick Command Enable bit mask. */ -#define TWI_QCEN_bp 4 /* Quick Command Enable bit position. */ -#define TWI_WIEN_bm 0x40 /* Write Interrupt Enable bit mask. */ -#define TWI_WIEN_bp 6 /* Write Interrupt Enable bit position. */ -#define TWI_RIEN_bm 0x80 /* Read Interrupt Enable bit mask. */ -#define TWI_RIEN_bp 7 /* Read Interrupt Enable bit position. */ - -/* TWI.MCTRLB bit masks and bit positions */ -#define TWI_MCMD_gm 0x03 /* Command group mask. */ -#define TWI_MCMD_gp 0 /* Command group position. */ -#define TWI_MCMD0_bm (1<<0) /* Command bit 0 mask. */ -#define TWI_MCMD0_bp 0 /* Command bit 0 position. */ -#define TWI_MCMD1_bm (1<<1) /* Command bit 1 mask. */ -#define TWI_MCMD1_bp 1 /* Command bit 1 position. */ -#define TWI_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ -#define TWI_ACKACT_bp 2 /* Acknowledge Action bit position. */ -#define TWI_FLUSH_bm 0x08 /* Flush bit mask. */ -#define TWI_FLUSH_bp 3 /* Flush bit position. */ - -/* TWI.MSTATUS bit masks and bit positions */ -#define TWI_BUSSTATE_gm 0x03 /* Bus State group mask. */ -#define TWI_BUSSTATE_gp 0 /* Bus State group position. */ -#define TWI_BUSSTATE0_bm (1<<0) /* Bus State bit 0 mask. */ -#define TWI_BUSSTATE0_bp 0 /* Bus State bit 0 position. */ -#define TWI_BUSSTATE1_bm (1<<1) /* Bus State bit 1 mask. */ -#define TWI_BUSSTATE1_bp 1 /* Bus State bit 1 position. */ -#define TWI_BUSERR_bm 0x04 /* Bus Error bit mask. */ -#define TWI_BUSERR_bp 2 /* Bus Error bit position. */ -#define TWI_ARBLOST_bm 0x08 /* Arbitration Lost bit mask. */ -#define TWI_ARBLOST_bp 3 /* Arbitration Lost bit position. */ -#define TWI_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ -#define TWI_RXACK_bp 4 /* Received Acknowledge bit position. */ -#define TWI_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ -#define TWI_CLKHOLD_bp 5 /* Clock Hold bit position. */ -#define TWI_WIF_bm 0x40 /* Write Interrupt Flag bit mask. */ -#define TWI_WIF_bp 6 /* Write Interrupt Flag bit position. */ -#define TWI_RIF_bm 0x80 /* Read Interrupt Flag bit mask. */ -#define TWI_RIF_bp 7 /* Read Interrupt Flag bit position. */ - - - - -/* TWI.SCTRLA bit masks and bit positions */ -/* TWI_ENABLE is already defined. */ -/* TWI_SMEN is already defined. */ -#define TWI_PMEN_bm 0x04 /* Promiscuous Mode Enable bit mask. */ -#define TWI_PMEN_bp 2 /* Promiscuous Mode Enable bit position. */ -#define TWI_PIEN_bm 0x20 /* Stop Interrupt Enable bit mask. */ -#define TWI_PIEN_bp 5 /* Stop Interrupt Enable bit position. */ -#define TWI_APIEN_bm 0x40 /* Address/Stop Interrupt Enable bit mask. */ -#define TWI_APIEN_bp 6 /* Address/Stop Interrupt Enable bit position. */ -#define TWI_DIEN_bm 0x80 /* Data Interrupt Enable bit mask. */ -#define TWI_DIEN_bp 7 /* Data Interrupt Enable bit position. */ - -/* TWI.SCTRLB bit masks and bit positions */ -#define TWI_SCMD_gm 0x03 /* Command group mask. */ -#define TWI_SCMD_gp 0 /* Command group position. */ -#define TWI_SCMD0_bm (1<<0) /* Command bit 0 mask. */ -#define TWI_SCMD0_bp 0 /* Command bit 0 position. */ -#define TWI_SCMD1_bm (1<<1) /* Command bit 1 mask. */ -#define TWI_SCMD1_bp 1 /* Command bit 1 position. */ -/* TWI_ACKACT is already defined. */ - -/* TWI.SSTATUS bit masks and bit positions */ -#define TWI_AP_bm 0x01 /* Slave Address or Stop bit mask. */ -#define TWI_AP_bp 0 /* Slave Address or Stop bit position. */ -#define TWI_DIR_bm 0x02 /* Read/Write Direction bit mask. */ -#define TWI_DIR_bp 1 /* Read/Write Direction bit position. */ -/* TWI_BUSERR is already defined. */ -#define TWI_COLL_bm 0x08 /* Collision bit mask. */ -#define TWI_COLL_bp 3 /* Collision bit position. */ -/* TWI_RXACK is already defined. */ -/* TWI_CLKHOLD is already defined. */ -#define TWI_APIF_bm 0x40 /* Address/Stop Interrupt Flag bit mask. */ -#define TWI_APIF_bp 6 /* Address/Stop Interrupt Flag bit position. */ -#define TWI_DIF_bm 0x80 /* Data Interrupt Flag bit mask. */ -#define TWI_DIF_bp 7 /* Data Interrupt Flag bit position. */ - - - -/* TWI.SADDRMASK bit masks and bit positions */ -#define TWI_ADDREN_bm 0x01 /* Address Enable bit mask. */ -#define TWI_ADDREN_bp 0 /* Address Enable bit position. */ -#define TWI_ADDRMASK_gm 0xFE /* Address Mask group mask. */ -#define TWI_ADDRMASK_gp 1 /* Address Mask group position. */ -#define TWI_ADDRMASK0_bm (1<<1) /* Address Mask bit 0 mask. */ -#define TWI_ADDRMASK0_bp 1 /* Address Mask bit 0 position. */ -#define TWI_ADDRMASK1_bm (1<<2) /* Address Mask bit 1 mask. */ -#define TWI_ADDRMASK1_bp 2 /* Address Mask bit 1 position. */ -#define TWI_ADDRMASK2_bm (1<<3) /* Address Mask bit 2 mask. */ -#define TWI_ADDRMASK2_bp 3 /* Address Mask bit 2 position. */ -#define TWI_ADDRMASK3_bm (1<<4) /* Address Mask bit 3 mask. */ -#define TWI_ADDRMASK3_bp 4 /* Address Mask bit 3 position. */ -#define TWI_ADDRMASK4_bm (1<<5) /* Address Mask bit 4 mask. */ -#define TWI_ADDRMASK4_bp 5 /* Address Mask bit 4 position. */ -#define TWI_ADDRMASK5_bm (1<<6) /* Address Mask bit 5 mask. */ -#define TWI_ADDRMASK5_bp 6 /* Address Mask bit 5 position. */ -#define TWI_ADDRMASK6_bm (1<<7) /* Address Mask bit 6 mask. */ -#define TWI_ADDRMASK6_bp 7 /* Address Mask bit 6 position. */ - -/* USART - Universal Synchronous and Asynchronous Receiver and Transmitter */ -/* USART.RXDATAL bit masks and bit positions */ -#define USART_DATA_gm 0xFF /* RX Data group mask. */ -#define USART_DATA_gp 0 /* RX Data group position. */ -#define USART_DATA0_bm (1<<0) /* RX Data bit 0 mask. */ -#define USART_DATA0_bp 0 /* RX Data bit 0 position. */ -#define USART_DATA1_bm (1<<1) /* RX Data bit 1 mask. */ -#define USART_DATA1_bp 1 /* RX Data bit 1 position. */ -#define USART_DATA2_bm (1<<2) /* RX Data bit 2 mask. */ -#define USART_DATA2_bp 2 /* RX Data bit 2 position. */ -#define USART_DATA3_bm (1<<3) /* RX Data bit 3 mask. */ -#define USART_DATA3_bp 3 /* RX Data bit 3 position. */ -#define USART_DATA4_bm (1<<4) /* RX Data bit 4 mask. */ -#define USART_DATA4_bp 4 /* RX Data bit 4 position. */ -#define USART_DATA5_bm (1<<5) /* RX Data bit 5 mask. */ -#define USART_DATA5_bp 5 /* RX Data bit 5 position. */ -#define USART_DATA6_bm (1<<6) /* RX Data bit 6 mask. */ -#define USART_DATA6_bp 6 /* RX Data bit 6 position. */ -#define USART_DATA7_bm (1<<7) /* RX Data bit 7 mask. */ -#define USART_DATA7_bp 7 /* RX Data bit 7 position. */ - -/* USART.RXDATAH bit masks and bit positions */ -#define USART_DATA8_bm 0x01 /* Receiver Data Register bit mask. */ -#define USART_DATA8_bp 0 /* Receiver Data Register bit position. */ -#define USART_PERR_bm 0x02 /* Parity Error bit mask. */ -#define USART_PERR_bp 1 /* Parity Error bit position. */ -#define USART_FERR_bm 0x04 /* Frame Error bit mask. */ -#define USART_FERR_bp 2 /* Frame Error bit position. */ -#define USART_BUFOVF_bm 0x40 /* Buffer Overflow bit mask. */ -#define USART_BUFOVF_bp 6 /* Buffer Overflow bit position. */ -#define USART_RXCIF_bm 0x80 /* Receive Complete Interrupt Flag bit mask. */ -#define USART_RXCIF_bp 7 /* Receive Complete Interrupt Flag bit position. */ - -/* USART.TXDATAL bit masks and bit positions */ -/* USART_DATA is already defined. */ - -/* USART.TXDATAH bit masks and bit positions */ -/* USART_DATA8 is already defined. */ - -/* USART.STATUS bit masks and bit positions */ -#define USART_WFB_bm 0x01 /* Wait For Break bit mask. */ -#define USART_WFB_bp 0 /* Wait For Break bit position. */ -#define USART_BDF_bm 0x02 /* Break Detected Flag bit mask. */ -#define USART_BDF_bp 1 /* Break Detected Flag bit position. */ -#define USART_ISFIF_bm 0x08 /* Inconsistent Sync Field Interrupt Flag bit mask. */ -#define USART_ISFIF_bp 3 /* Inconsistent Sync Field Interrupt Flag bit position. */ -#define USART_RXSIF_bm 0x10 /* Receive Start Interrupt bit mask. */ -#define USART_RXSIF_bp 4 /* Receive Start Interrupt bit position. */ -#define USART_DREIF_bm 0x20 /* Data Register Empty Flag bit mask. */ -#define USART_DREIF_bp 5 /* Data Register Empty Flag bit position. */ -#define USART_TXCIF_bm 0x40 /* Transmit Interrupt Flag bit mask. */ -#define USART_TXCIF_bp 6 /* Transmit Interrupt Flag bit position. */ -/* USART_RXCIF is already defined. */ - -/* USART.CTRLA bit masks and bit positions */ -#define USART_RS485_gm 0x03 /* RS485 Mode internal transmitter group mask. */ -#define USART_RS485_gp 0 /* RS485 Mode internal transmitter group position. */ -#define USART_RS4850_bm (1<<0) /* RS485 Mode internal transmitter bit 0 mask. */ -#define USART_RS4850_bp 0 /* RS485 Mode internal transmitter bit 0 position. */ -#define USART_RS4851_bm (1<<1) /* RS485 Mode internal transmitter bit 1 mask. */ -#define USART_RS4851_bp 1 /* RS485 Mode internal transmitter bit 1 position. */ -#define USART_ABEIE_bm 0x04 /* Auto-baud Error Interrupt Enable bit mask. */ -#define USART_ABEIE_bp 2 /* Auto-baud Error Interrupt Enable bit position. */ -#define USART_LBME_bm 0x08 /* Loop-back Mode Enable bit mask. */ -#define USART_LBME_bp 3 /* Loop-back Mode Enable bit position. */ -#define USART_RXSIE_bm 0x10 /* Receiver Start Frame Interrupt Enable bit mask. */ -#define USART_RXSIE_bp 4 /* Receiver Start Frame Interrupt Enable bit position. */ -#define USART_DREIE_bm 0x20 /* Data Register Empty Interrupt Enable bit mask. */ -#define USART_DREIE_bp 5 /* Data Register Empty Interrupt Enable bit position. */ -#define USART_TXCIE_bm 0x40 /* Transmit Complete Interrupt Enable bit mask. */ -#define USART_TXCIE_bp 6 /* Transmit Complete Interrupt Enable bit position. */ -#define USART_RXCIE_bm 0x80 /* Receive Complete Interrupt Enable bit mask. */ -#define USART_RXCIE_bp 7 /* Receive Complete Interrupt Enable bit position. */ - -/* USART.CTRLB bit masks and bit positions */ -#define USART_MPCM_bm 0x01 /* Multi-processor Communication Mode bit mask. */ -#define USART_MPCM_bp 0 /* Multi-processor Communication Mode bit position. */ -#define USART_RXMODE_gm 0x06 /* Receiver Mode group mask. */ -#define USART_RXMODE_gp 1 /* Receiver Mode group position. */ -#define USART_RXMODE0_bm (1<<1) /* Receiver Mode bit 0 mask. */ -#define USART_RXMODE0_bp 1 /* Receiver Mode bit 0 position. */ -#define USART_RXMODE1_bm (1<<2) /* Receiver Mode bit 1 mask. */ -#define USART_RXMODE1_bp 2 /* Receiver Mode bit 1 position. */ -#define USART_ODME_bm 0x08 /* Open Drain Mode Enable bit mask. */ -#define USART_ODME_bp 3 /* Open Drain Mode Enable bit position. */ -#define USART_SFDEN_bm 0x10 /* Start Frame Detection Enable bit mask. */ -#define USART_SFDEN_bp 4 /* Start Frame Detection Enable bit position. */ -#define USART_TXEN_bm 0x40 /* Transmitter Enable bit mask. */ -#define USART_TXEN_bp 6 /* Transmitter Enable bit position. */ -#define USART_RXEN_bm 0x80 /* Reciever enable bit mask. */ -#define USART_RXEN_bp 7 /* Reciever enable bit position. */ - -/* USART.CTRLC bit masks and bit positions */ -#define USART_UCPHA_bm 0x02 /* SPI Master Mode, Clock Phase bit mask. */ -#define USART_UCPHA_bp 1 /* SPI Master Mode, Clock Phase bit position. */ -#define USART_UDORD_bm 0x04 /* SPI Master Mode, Data Order bit mask. */ -#define USART_UDORD_bp 2 /* SPI Master Mode, Data Order bit position. */ -#define USART_CHSIZE_gm 0x07 /* Character Size group mask. */ -#define USART_CHSIZE_gp 0 /* Character Size group position. */ -#define USART_CHSIZE0_bm (1<<0) /* Character Size bit 0 mask. */ -#define USART_CHSIZE0_bp 0 /* Character Size bit 0 position. */ -#define USART_CHSIZE1_bm (1<<1) /* Character Size bit 1 mask. */ -#define USART_CHSIZE1_bp 1 /* Character Size bit 1 position. */ -#define USART_CHSIZE2_bm (1<<2) /* Character Size bit 2 mask. */ -#define USART_CHSIZE2_bp 2 /* Character Size bit 2 position. */ -#define USART_SBMODE_bm 0x08 /* Stop Bit Mode bit mask. */ -#define USART_SBMODE_bp 3 /* Stop Bit Mode bit position. */ -#define USART_PMODE_gm 0x30 /* Parity Mode group mask. */ -#define USART_PMODE_gp 4 /* Parity Mode group position. */ -#define USART_PMODE0_bm (1<<4) /* Parity Mode bit 0 mask. */ -#define USART_PMODE0_bp 4 /* Parity Mode bit 0 position. */ -#define USART_PMODE1_bm (1<<5) /* Parity Mode bit 1 mask. */ -#define USART_PMODE1_bp 5 /* Parity Mode bit 1 position. */ -#define USART_CMODE_gm 0xC0 /* Communication Mode group mask. */ -#define USART_CMODE_gp 6 /* Communication Mode group position. */ -#define USART_CMODE0_bm (1<<6) /* Communication Mode bit 0 mask. */ -#define USART_CMODE0_bp 6 /* Communication Mode bit 0 position. */ -#define USART_CMODE1_bm (1<<7) /* Communication Mode bit 1 mask. */ -#define USART_CMODE1_bp 7 /* Communication Mode bit 1 position. */ - - - -/* USART.DBGCTRL bit masks and bit positions */ -#define USART_DBGRUN_bm 0x01 /* Debug Run bit mask. */ -#define USART_DBGRUN_bp 0 /* Debug Run bit position. */ -#define USART_ABMBP_bm 0x80 /* Autobaud majority voter bypass bit mask. */ -#define USART_ABMBP_bp 7 /* Autobaud majority voter bypass bit position. */ - -/* USART.EVCTRL bit masks and bit positions */ -#define USART_IREI_bm 0x01 /* IrDA Event Input Enable bit mask. */ -#define USART_IREI_bp 0 /* IrDA Event Input Enable bit position. */ - -/* USART.TXPLCTRL bit masks and bit positions */ -#define USART_TXPL_gm 0xFF /* Transmit pulse length group mask. */ -#define USART_TXPL_gp 0 /* Transmit pulse length group position. */ -#define USART_TXPL0_bm (1<<0) /* Transmit pulse length bit 0 mask. */ -#define USART_TXPL0_bp 0 /* Transmit pulse length bit 0 position. */ -#define USART_TXPL1_bm (1<<1) /* Transmit pulse length bit 1 mask. */ -#define USART_TXPL1_bp 1 /* Transmit pulse length bit 1 position. */ -#define USART_TXPL2_bm (1<<2) /* Transmit pulse length bit 2 mask. */ -#define USART_TXPL2_bp 2 /* Transmit pulse length bit 2 position. */ -#define USART_TXPL3_bm (1<<3) /* Transmit pulse length bit 3 mask. */ -#define USART_TXPL3_bp 3 /* Transmit pulse length bit 3 position. */ -#define USART_TXPL4_bm (1<<4) /* Transmit pulse length bit 4 mask. */ -#define USART_TXPL4_bp 4 /* Transmit pulse length bit 4 position. */ -#define USART_TXPL5_bm (1<<5) /* Transmit pulse length bit 5 mask. */ -#define USART_TXPL5_bp 5 /* Transmit pulse length bit 5 position. */ -#define USART_TXPL6_bm (1<<6) /* Transmit pulse length bit 6 mask. */ -#define USART_TXPL6_bp 6 /* Transmit pulse length bit 6 position. */ -#define USART_TXPL7_bm (1<<7) /* Transmit pulse length bit 7 mask. */ -#define USART_TXPL7_bp 7 /* Transmit pulse length bit 7 position. */ - -/* USART.RXPLCTRL bit masks and bit positions */ -#define USART_RXPL_gm 0x7F /* Receiver Pulse Lenght group mask. */ -#define USART_RXPL_gp 0 /* Receiver Pulse Lenght group position. */ -#define USART_RXPL0_bm (1<<0) /* Receiver Pulse Lenght bit 0 mask. */ -#define USART_RXPL0_bp 0 /* Receiver Pulse Lenght bit 0 position. */ -#define USART_RXPL1_bm (1<<1) /* Receiver Pulse Lenght bit 1 mask. */ -#define USART_RXPL1_bp 1 /* Receiver Pulse Lenght bit 1 position. */ -#define USART_RXPL2_bm (1<<2) /* Receiver Pulse Lenght bit 2 mask. */ -#define USART_RXPL2_bp 2 /* Receiver Pulse Lenght bit 2 position. */ -#define USART_RXPL3_bm (1<<3) /* Receiver Pulse Lenght bit 3 mask. */ -#define USART_RXPL3_bp 3 /* Receiver Pulse Lenght bit 3 position. */ -#define USART_RXPL4_bm (1<<4) /* Receiver Pulse Lenght bit 4 mask. */ -#define USART_RXPL4_bp 4 /* Receiver Pulse Lenght bit 4 position. */ -#define USART_RXPL5_bm (1<<5) /* Receiver Pulse Lenght bit 5 mask. */ -#define USART_RXPL5_bp 5 /* Receiver Pulse Lenght bit 5 position. */ -#define USART_RXPL6_bm (1<<6) /* Receiver Pulse Lenght bit 6 mask. */ -#define USART_RXPL6_bp 6 /* Receiver Pulse Lenght bit 6 position. */ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -/* VPORT - Virtual Ports */ -/* VPORT.INTFLAGS bit masks and bit positions */ -#define VPORT_INT_gm 0xFF /* Pin Interrupt group mask. */ -#define VPORT_INT_gp 0 /* Pin Interrupt group position. */ -#define VPORT_INT0_bm (1<<0) /* Pin Interrupt bit 0 mask. */ -#define VPORT_INT0_bp 0 /* Pin Interrupt bit 0 position. */ -#define VPORT_INT1_bm (1<<1) /* Pin Interrupt bit 1 mask. */ -#define VPORT_INT1_bp 1 /* Pin Interrupt bit 1 position. */ -#define VPORT_INT2_bm (1<<2) /* Pin Interrupt bit 2 mask. */ -#define VPORT_INT2_bp 2 /* Pin Interrupt bit 2 position. */ -#define VPORT_INT3_bm (1<<3) /* Pin Interrupt bit 3 mask. */ -#define VPORT_INT3_bp 3 /* Pin Interrupt bit 3 position. */ -#define VPORT_INT4_bm (1<<4) /* Pin Interrupt bit 4 mask. */ -#define VPORT_INT4_bp 4 /* Pin Interrupt bit 4 position. */ -#define VPORT_INT5_bm (1<<5) /* Pin Interrupt bit 5 mask. */ -#define VPORT_INT5_bp 5 /* Pin Interrupt bit 5 position. */ -#define VPORT_INT6_bm (1<<6) /* Pin Interrupt bit 6 mask. */ -#define VPORT_INT6_bp 6 /* Pin Interrupt bit 6 position. */ -#define VPORT_INT7_bm (1<<7) /* Pin Interrupt bit 7 mask. */ -#define VPORT_INT7_bp 7 /* Pin Interrupt bit 7 position. */ - -/* VREF - Voltage reference */ -/* VREF.CTRLA bit masks and bit positions */ -#define VREF_AC0REFSEL_gm 0x07 /* AC0 reference select group mask. */ -#define VREF_AC0REFSEL_gp 0 /* AC0 reference select group position. */ -#define VREF_AC0REFSEL0_bm (1<<0) /* AC0 reference select bit 0 mask. */ -#define VREF_AC0REFSEL0_bp 0 /* AC0 reference select bit 0 position. */ -#define VREF_AC0REFSEL1_bm (1<<1) /* AC0 reference select bit 1 mask. */ -#define VREF_AC0REFSEL1_bp 1 /* AC0 reference select bit 1 position. */ -#define VREF_AC0REFSEL2_bm (1<<2) /* AC0 reference select bit 2 mask. */ -#define VREF_AC0REFSEL2_bp 2 /* AC0 reference select bit 2 position. */ -#define VREF_ADC0REFSEL_gm 0x70 /* ADC0 reference select group mask. */ -#define VREF_ADC0REFSEL_gp 4 /* ADC0 reference select group position. */ -#define VREF_ADC0REFSEL0_bm (1<<4) /* ADC0 reference select bit 0 mask. */ -#define VREF_ADC0REFSEL0_bp 4 /* ADC0 reference select bit 0 position. */ -#define VREF_ADC0REFSEL1_bm (1<<5) /* ADC0 reference select bit 1 mask. */ -#define VREF_ADC0REFSEL1_bp 5 /* ADC0 reference select bit 1 position. */ -#define VREF_ADC0REFSEL2_bm (1<<6) /* ADC0 reference select bit 2 mask. */ -#define VREF_ADC0REFSEL2_bp 6 /* ADC0 reference select bit 2 position. */ - -/* VREF.CTRLB bit masks and bit positions */ -#define VREF_AC0REFEN_bm 0x01 /* AC0 DACREF reference enable bit mask. */ -#define VREF_AC0REFEN_bp 0 /* AC0 DACREF reference enable bit position. */ -#define VREF_ADC0REFEN_bm 0x02 /* ADC0 reference enable bit mask. */ -#define VREF_ADC0REFEN_bp 1 /* ADC0 reference enable bit position. */ -#define VREF_NVMREFEN_bm 0x04 /* NVM reference enable bit mask. */ -#define VREF_NVMREFEN_bp 2 /* NVM reference enable bit position. */ - -/* WDT - Watch-Dog Timer */ -/* WDT.CTRLA bit masks and bit positions */ -#define WDT_PERIOD_gm 0x0F /* Period group mask. */ -#define WDT_PERIOD_gp 0 /* Period group position. */ -#define WDT_PERIOD0_bm (1<<0) /* Period bit 0 mask. */ -#define WDT_PERIOD0_bp 0 /* Period bit 0 position. */ -#define WDT_PERIOD1_bm (1<<1) /* Period bit 1 mask. */ -#define WDT_PERIOD1_bp 1 /* Period bit 1 position. */ -#define WDT_PERIOD2_bm (1<<2) /* Period bit 2 mask. */ -#define WDT_PERIOD2_bp 2 /* Period bit 2 position. */ -#define WDT_PERIOD3_bm (1<<3) /* Period bit 3 mask. */ -#define WDT_PERIOD3_bp 3 /* Period bit 3 position. */ -#define WDT_WINDOW_gm 0xF0 /* Window group mask. */ -#define WDT_WINDOW_gp 4 /* Window group position. */ -#define WDT_WINDOW0_bm (1<<4) /* Window bit 0 mask. */ -#define WDT_WINDOW0_bp 4 /* Window bit 0 position. */ -#define WDT_WINDOW1_bm (1<<5) /* Window bit 1 mask. */ -#define WDT_WINDOW1_bp 5 /* Window bit 1 position. */ -#define WDT_WINDOW2_bm (1<<6) /* Window bit 2 mask. */ -#define WDT_WINDOW2_bp 6 /* Window bit 2 position. */ -#define WDT_WINDOW3_bm (1<<7) /* Window bit 3 mask. */ -#define WDT_WINDOW3_bp 7 /* Window bit 3 position. */ - -/* WDT.STATUS bit masks and bit positions */ -#define WDT_SYNCBUSY_bm 0x01 /* Syncronization busy bit mask. */ -#define WDT_SYNCBUSY_bp 0 /* Syncronization busy bit position. */ -#define WDT_LOCK_bm 0x80 /* Lock enable bit mask. */ -#define WDT_LOCK_bp 7 /* Lock enable bit position. */ - - - -// Generic Port Pins - -#define PIN0_bm 0x01 -#define PIN0_bp 0 -#define PIN1_bm 0x02 -#define PIN1_bp 1 -#define PIN2_bm 0x04 -#define PIN2_bp 2 -#define PIN3_bm 0x08 -#define PIN3_bp 3 -#define PIN4_bm 0x10 -#define PIN4_bp 4 -#define PIN5_bm 0x20 -#define PIN5_bp 5 -#define PIN6_bm 0x40 -#define PIN6_bp 6 -#define PIN7_bm 0x80 -#define PIN7_bp 7 - -/* ========== Interrupt Vector Definitions ========== */ -/* Vector 0 is the reset vector */ - -/* CRCSCAN interrupt vectors */ -#define CRCSCAN_NMI_vect_num 1 -#define CRCSCAN_NMI_vect _VECTOR(1) /* */ - -/* BOD interrupt vectors */ -#define BOD_VLM_vect_num 2 -#define BOD_VLM_vect _VECTOR(2) /* */ - -/* RTC interrupt vectors */ -#define RTC_CNT_vect_num 3 -#define RTC_CNT_vect _VECTOR(3) /* */ -#define RTC_PIT_vect_num 4 -#define RTC_PIT_vect _VECTOR(4) /* */ - -/* CCL interrupt vectors */ -#define CCL_CCL_vect_num 5 -#define CCL_CCL_vect _VECTOR(5) /* */ - -/* PORTA interrupt vectors */ -#define PORTA_PORT_vect_num 6 -#define PORTA_PORT_vect _VECTOR(6) /* */ - -/* TCA0 interrupt vectors */ -#define TCA0_LUNF_vect_num 7 -#define TCA0_LUNF_vect _VECTOR(7) /* */ -#define TCA0_OVF_vect_num 7 -#define TCA0_OVF_vect _VECTOR(7) /* */ -#define TCA0_HUNF_vect_num 8 -#define TCA0_HUNF_vect _VECTOR(8) /* */ -#define TCA0_LCMP0_vect_num 9 -#define TCA0_LCMP0_vect _VECTOR(9) /* */ -#define TCA0_CMP0_vect_num 9 -#define TCA0_CMP0_vect _VECTOR(9) /* */ -#define TCA0_CMP1_vect_num 10 -#define TCA0_CMP1_vect _VECTOR(10) /* */ -#define TCA0_LCMP1_vect_num 10 -#define TCA0_LCMP1_vect _VECTOR(10) /* */ -#define TCA0_CMP2_vect_num 11 -#define TCA0_CMP2_vect _VECTOR(11) /* */ -#define TCA0_LCMP2_vect_num 11 -#define TCA0_LCMP2_vect _VECTOR(11) /* */ - -/* TCB0 interrupt vectors */ -#define TCB0_INT_vect_num 12 -#define TCB0_INT_vect _VECTOR(12) /* */ - -/* TCB1 interrupt vectors */ -#define TCB1_INT_vect_num 13 -#define TCB1_INT_vect _VECTOR(13) /* */ - -/* TWI0 interrupt vectors */ -#define TWI0_TWIS_vect_num 14 -#define TWI0_TWIS_vect _VECTOR(14) /* */ -#define TWI0_TWIM_vect_num 15 -#define TWI0_TWIM_vect _VECTOR(15) /* */ - -/* SPI0 interrupt vectors */ -#define SPI0_INT_vect_num 16 -#define SPI0_INT_vect _VECTOR(16) /* */ - -/* USART0 interrupt vectors */ -#define USART0_RXC_vect_num 17 -#define USART0_RXC_vect _VECTOR(17) /* */ -#define USART0_DRE_vect_num 18 -#define USART0_DRE_vect _VECTOR(18) /* */ -#define USART0_TXC_vect_num 19 -#define USART0_TXC_vect _VECTOR(19) /* */ - -/* PORTD interrupt vectors */ -#define PORTD_PORT_vect_num 20 -#define PORTD_PORT_vect _VECTOR(20) /* */ - -/* AC0 interrupt vectors */ -#define AC0_AC_vect_num 21 -#define AC0_AC_vect _VECTOR(21) /* */ - -/* ADC0 interrupt vectors */ -#define ADC0_RESRDY_vect_num 22 -#define ADC0_RESRDY_vect _VECTOR(22) /* */ -#define ADC0_WCOMP_vect_num 23 -#define ADC0_WCOMP_vect _VECTOR(23) /* */ - -/* PORTC interrupt vectors */ -#define PORTC_PORT_vect_num 24 -#define PORTC_PORT_vect _VECTOR(24) /* */ - -/* TCB2 interrupt vectors */ -#define TCB2_INT_vect_num 25 -#define TCB2_INT_vect _VECTOR(25) /* */ - -/* USART1 interrupt vectors */ -#define USART1_RXC_vect_num 26 -#define USART1_RXC_vect _VECTOR(26) /* */ -#define USART1_DRE_vect_num 27 -#define USART1_DRE_vect _VECTOR(27) /* */ -#define USART1_TXC_vect_num 28 -#define USART1_TXC_vect _VECTOR(28) /* */ - -/* PORTF interrupt vectors */ -#define PORTF_PORT_vect_num 29 -#define PORTF_PORT_vect _VECTOR(29) /* */ - -/* NVMCTRL interrupt vectors */ -#define NVMCTRL_EE_vect_num 30 -#define NVMCTRL_EE_vect _VECTOR(30) /* */ - -/* PORTB interrupt vectors */ -#define PORTB_PORT_vect_num 34 -#define PORTB_PORT_vect _VECTOR(34) /* */ - -/* PORTE interrupt vectors */ -#define PORTE_PORT_vect_num 35 -#define PORTE_PORT_vect _VECTOR(35) /* */ - -#define _VECTOR_SIZE 4 /* Size of individual vector. */ -#define _VECTORS_SIZE (36 * _VECTOR_SIZE) - - -/* ========== Constants ========== */ - -#define DATAMEM_START (0x0000) -#define DATAMEM_SIZE (32768) -#define DATAMEM_END (DATAMEM_START + DATAMEM_SIZE - 1) - -#define EEPROM_START (0x1400) -#define EEPROM_SIZE (256) -#define EEPROM_PAGE_SIZE (64) -#define EEPROM_END (EEPROM_START + EEPROM_SIZE - 1) - -/* Added MAPPED_EEPROM segment names for avr-libc */ -#define MAPPED_EEPROM_START (EEPROM_START) -#define MAPPED_EEPROM_SIZE (EEPROM_SIZE) -#define MAPPED_EEPROM_PAGE_SIZE (EEPROM_PAGE_SIZE) -#define MAPPED_EEPROM_END (MAPPED_EEPROM_START + MAPPED_EEPROM_SIZE - 1) - -#define FUSES_START (0x1280) -#define FUSES_SIZE (10) -#define FUSES_PAGE_SIZE (64) -#define FUSES_END (FUSES_START + FUSES_SIZE - 1) - -#define INTERNAL_SRAM_START (0x3000) -#define INTERNAL_SRAM_SIZE (4096) -#define INTERNAL_SRAM_PAGE_SIZE (0) -#define INTERNAL_SRAM_END (INTERNAL_SRAM_START + INTERNAL_SRAM_SIZE - 1) - -#define IO_START (0x0000) -#define IO_SIZE (4352) -#define IO_PAGE_SIZE (0) -#define IO_END (IO_START + IO_SIZE - 1) - -#define LOCKBITS_START (0x128A) -#define LOCKBITS_SIZE (1) -#define LOCKBITS_PAGE_SIZE (64) -#define LOCKBITS_END (LOCKBITS_START + LOCKBITS_SIZE - 1) - -#define MAPPED_PROGMEM_START (0x4000) -#define MAPPED_PROGMEM_SIZE (32768) -#define MAPPED_PROGMEM_PAGE_SIZE (128) -#define MAPPED_PROGMEM_END (MAPPED_PROGMEM_START + MAPPED_PROGMEM_SIZE - 1) - -#define PROD_SIGNATURES_START (0x1103) -#define PROD_SIGNATURES_SIZE (125) -#define PROD_SIGNATURES_PAGE_SIZE (128) -#define PROD_SIGNATURES_END (PROD_SIGNATURES_START + PROD_SIGNATURES_SIZE - 1) - -#define SIGNATURES_START (0x1100) -#define SIGNATURES_SIZE (3) -#define SIGNATURES_PAGE_SIZE (128) -#define SIGNATURES_END (SIGNATURES_START + SIGNATURES_SIZE - 1) - -#define USER_SIGNATURES_START (0x1300) -#define USER_SIGNATURES_SIZE (64) -#define USER_SIGNATURES_PAGE_SIZE (64) -#define USER_SIGNATURES_END (USER_SIGNATURES_START + USER_SIGNATURES_SIZE - 1) - -#define PROGMEM_START (0x0000) -#define PROGMEM_SIZE (32768) -#define PROGMEM_END (PROGMEM_START + PROGMEM_SIZE - 1) - -#define PROGMEM_START (0x0000) -#define PROGMEM_SIZE (32768) -#define PROGMEM_PAGE_SIZE (128) -#define PROGMEM_END (PROGMEM_START + PROGMEM_SIZE - 1) - -#define FLASHSTART PROGMEM_START -#define FLASHEND PROGMEM_END -#define RAMSTART INTERNAL_SRAM_START -#define RAMSIZE INTERNAL_SRAM_SIZE -#define RAMEND INTERNAL_SRAM_END -#define E2END EEPROM_END -#define E2PAGESIZE EEPROM_PAGE_SIZE - - -/* ========== Fuses ========== */ -#define FUSE_MEMORY_SIZE 9 - -/* Fuse Byte 0 Reserved */ - -/* Fuse Byte 1 Reserved */ - -/* Fuse Byte 2 Reserved */ - -/* Fuse Byte 3 Reserved */ - -/* Fuse Byte 4 Reserved */ - -/* Fuse Byte 5 Reserved */ - -/* Fuse Byte 6 Reserved */ - -/* Fuse Byte 7 */ - -/* Fuse Byte 8 */ -#define FUSE_SLEEP0 (unsigned char)~_BV(0) /* BOD Operation in Sleep Mode Bit 0 */ -#define FUSE_SLEEP1 (unsigned char)~_BV(1) /* BOD Operation in Sleep Mode Bit 1 */ -#define FUSE_ACTIVE0 (unsigned char)~_BV(2) /* BOD Operation in Active Mode Bit 0 */ -#define FUSE_ACTIVE1 (unsigned char)~_BV(3) /* BOD Operation in Active Mode Bit 1 */ -#define FUSE_SAMPFREQ (unsigned char)~_BV(4) /* BOD Sample Frequency */ -#define FUSE_LVL0 (unsigned char)~_BV(5) /* BOD Level Bit 0 */ -#define FUSE_LVL1 (unsigned char)~_BV(6) /* BOD Level Bit 1 */ -#define FUSE_LVL2 (unsigned char)~_BV(7) /* BOD Level Bit 2 */ - -/* Fuse Byte 9 */ - -/* Fuse Byte 10 */ -#define FUSE_FREQSEL0 (unsigned char)~_BV(0) /* Frequency Select Bit 0 */ -#define FUSE_FREQSEL1 (unsigned char)~_BV(1) /* Frequency Select Bit 1 */ -#define FUSE_OSCLOCK (unsigned char)~_BV(7) /* Oscillator Lock */ - -/* Fuse Byte 11 */ -#define FUSE_EESAVE (unsigned char)~_BV(0) /* EEPROM Save */ -#define FUSE_RSTPINCFG0 (unsigned char)~_BV(2) /* Reset Pin Configuration Bit 0 */ -#define FUSE_RSTPINCFG1 (unsigned char)~_BV(3) /* Reset Pin Configuration Bit 1 */ -#define FUSE_CRCSRC0 (unsigned char)~_BV(6) /* CRC Source Bit 0 */ -#define FUSE_CRCSRC1 (unsigned char)~_BV(7) /* CRC Source Bit 1 */ - -/* Fuse Byte 12 */ -#define FUSE_SUT0 (unsigned char)~_BV(0) /* Startup Time Bit 0 */ -#define FUSE_SUT1 (unsigned char)~_BV(1) /* Startup Time Bit 1 */ -#define FUSE_SUT2 (unsigned char)~_BV(2) /* Startup Time Bit 2 */ - -/* Fuse Byte 13 */ -#define FUSE_CMPA (unsigned char)~_BV(0) /* Compare A Default Output Value */ -#define FUSE_CMPB (unsigned char)~_BV(1) /* Compare B Default Output Value */ -#define FUSE_CMPC (unsigned char)~_BV(2) /* Compare C Default Output Value */ -#define FUSE_CMPD (unsigned char)~_BV(3) /* Compare D Default Output Value */ -#define FUSE_CMPAEN (unsigned char)~_BV(4) /* Compare A Output Enable */ -#define FUSE_CMPBEN (unsigned char)~_BV(5) /* Compare B Output Enable */ -#define FUSE_CMPCEN (unsigned char)~_BV(6) /* Compare C Output Enable */ -#define FUSE_CMPDEN (unsigned char)~_BV(7) /* Compare D Output Enable */ - -/* Fuse Byte 14 */ -#define FUSE_PERIOD0 (unsigned char)~_BV(0) /* Watchdog Timeout Period Bit 0 */ -#define FUSE_PERIOD1 (unsigned char)~_BV(1) /* Watchdog Timeout Period Bit 1 */ -#define FUSE_PERIOD2 (unsigned char)~_BV(2) /* Watchdog Timeout Period Bit 2 */ -#define FUSE_PERIOD3 (unsigned char)~_BV(3) /* Watchdog Timeout Period Bit 3 */ -#define FUSE_WINDOW0 (unsigned char)~_BV(4) /* Watchdog Window Timeout Period Bit 0 */ -#define FUSE_WINDOW1 (unsigned char)~_BV(5) /* Watchdog Window Timeout Period Bit 1 */ -#define FUSE_WINDOW2 (unsigned char)~_BV(6) /* Watchdog Window Timeout Period Bit 2 */ -#define FUSE_WINDOW3 (unsigned char)~_BV(7) /* Watchdog Window Timeout Period Bit 3 */ - -/* ========== Lock Bits ========== */ -#define __LOCK_BITS_EXIST - -/* ========== Signature ========== */ -#define SIGNATURE_0 0x1E -#define SIGNATURE_1 0x95 -#define SIGNATURE_2 0x52 - - -#endif /* #ifdef _AVR_ATMEGA3208_H_INCLUDED */ - diff --git a/arduino/hardware/tools/avr/avr/include/avr/iom3209.h b/arduino/hardware/tools/avr/avr/include/avr/iom3209.h deleted file mode 100644 index 1616f4c..0000000 --- a/arduino/hardware/tools/avr/avr/include/avr/iom3209.h +++ /dev/null @@ -1,5395 +0,0 @@ -/***************************************************************************** - * - * Copyright (C) 2017 Atmel Corporation, a wholly owned subsidiary of Microchip Technology Inc. - * All rights reserved. - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - ****************************************************************************/ - - -#ifndef _AVR_IO_H_ -# error "Include instead of this file." -#endif - -#ifndef _AVR_IOXXX_H_ -# define _AVR_IOXXX_H_ "iom3209.h" -#else -# error "Attempt to include more than one file." -#endif - -#ifndef _AVR_ATMEGA3209_H_INCLUDED -#define _AVR_ATMEGA3209_H_INCLUDED - -/* Ungrouped common registers */ -#define CCP _SFR_MEM8(0x0034) /* Configuration Change Protection */ -#define RAMPZ _SFR_MEM8(0x003B) /* Extended Z-pointer Register */ -#define SPH _SFR_MEM8(0x003E) /* Stack Pointer High */ -#define SPL _SFR_MEM8(0x003D) /* Stack Pointer Low */ -#define SREG _SFR_MEM8(0x003F) /* Status Register */ - -#define GPIOR0 _SFR_MEM8(0x001C) /* General Purpose IO Register 0 */ -#define GPIOR1 _SFR_MEM8(0x001D) /* General Purpose IO Register 1 */ -#define GPIOR2 _SFR_MEM8(0x001E) /* General Purpose IO Register 2 */ -#define GPIOR3 _SFR_MEM8(0x001F) /* General Purpose IO Register 3 */ - -/* Deprecated */ -#define GPIO0 _SFR_MEM8(0x001C) /* General Purpose IO Register 0 */ -#define GPIO1 _SFR_MEM8(0x001D) /* General Purpose IO Register 1 */ -#define GPIO2 _SFR_MEM8(0x001E) /* General Purpose IO Register 2 */ -#define GPIO3 _SFR_MEM8(0x001F) /* General Purpose IO Register 3 */ - -/* C Language Only */ -#if !defined (__ASSEMBLER__) - -#include - -typedef volatile uint8_t register8_t; -typedef volatile uint16_t register16_t; -typedef volatile uint32_t register32_t; - - -#ifdef _WORDREGISTER -#undef _WORDREGISTER -#endif -#define _WORDREGISTER(regname) \ - __extension__ union \ - { \ - register16_t regname; \ - struct \ - { \ - register8_t regname ## L; \ - register8_t regname ## H; \ - }; \ - } - -#ifdef _DWORDREGISTER -#undef _DWORDREGISTER -#endif -#define _DWORDREGISTER(regname) \ - __extension__ union \ - { \ - register32_t regname; \ - struct \ - { \ - register8_t regname ## 0; \ - register8_t regname ## 1; \ - register8_t regname ## 2; \ - register8_t regname ## 3; \ - }; \ - } - - -/* -========================================================================== -IO Module Structures -========================================================================== -*/ - - -/* --------------------------------------------------------------------------- -AC - Analog Comparator --------------------------------------------------------------------------- -*/ - -/* Analog Comparator */ -typedef struct AC_struct -{ - register8_t CTRLA; /* Control A */ - register8_t reserved_0x01; - register8_t MUXCTRLA; /* Mux Control A */ - register8_t reserved_0x03; - register8_t DACREF; /* Referance scale control */ - register8_t reserved_0x05; - register8_t INTCTRL; /* Interrupt Control */ - register8_t STATUS; /* Status */ -} AC_t; - -/* Hysteresis Mode select */ -typedef enum AC_HYSMODE_enum -{ - AC_HYSMODE_OFF_gc = (0x00<<1), /* No hysteresis */ - AC_HYSMODE_10mV_gc = (0x01<<1), /* 10mV hysteresis */ - AC_HYSMODE_25mV_gc = (0x02<<1), /* 25mV hysteresis */ - AC_HYSMODE_50mV_gc = (0x03<<1), /* 50mV hysteresis */ -} AC_HYSMODE_t; - -/* Interrupt Mode select */ -typedef enum AC_INTMODE_enum -{ - AC_INTMODE_BOTHEDGE_gc = (0x00<<4), /* Any Edge */ - AC_INTMODE_NEGEDGE_gc = (0x02<<4), /* Negative Edge */ - AC_INTMODE_POSEDGE_gc = (0x03<<4), /* Positive Edge */ -} AC_INTMODE_t; - -/* Low Power Mode select */ -typedef enum AC_LPMODE_enum -{ - AC_LPMODE_DIS_gc = (0x00<<3), /* Low power mode disabled */ - AC_LPMODE_EN_gc = (0x01<<3), /* Low power mode enabled */ -} AC_LPMODE_t; - -/* Negative Input MUX Selection select */ -typedef enum AC_MUXNEG_enum -{ - AC_MUXNEG_PIN0_gc = (0x00<<0), /* Negative Pin 0 */ - AC_MUXNEG_PIN1_gc = (0x01<<0), /* Negative Pin 1 */ - AC_MUXNEG_PIN2_gc = (0x02<<0), /* Negative Pin 2 */ - AC_MUXNEG_DACREF_gc = (0x03<<0), /* DAC Voltage Reference */ -} AC_MUXNEG_t; - -/* Positive Input MUX Selection select */ -typedef enum AC_MUXPOS_enum -{ - AC_MUXPOS_PIN0_gc = (0x00<<3), /* Positive Pin 0 */ - AC_MUXPOS_PIN1_gc = (0x01<<3), /* Positive Pin 1 */ - AC_MUXPOS_PIN2_gc = (0x02<<3), /* Positive Pin 2 */ - AC_MUXPOS_PIN3_gc = (0x03<<3), /* Positive Pin 3 */ -} AC_MUXPOS_t; - -/* --------------------------------------------------------------------------- -ADC - Analog to Digital Converter --------------------------------------------------------------------------- -*/ - -/* Analog to Digital Converter */ -typedef struct ADC_struct -{ - register8_t CTRLA; /* Control A */ - register8_t CTRLB; /* Control B */ - register8_t CTRLC; /* Control C */ - register8_t CTRLD; /* Control D */ - register8_t CTRLE; /* Control E */ - register8_t SAMPCTRL; /* Sample Control */ - register8_t MUXPOS; /* Positive mux input */ - register8_t reserved_0x07; - register8_t COMMAND; /* Command */ - register8_t EVCTRL; /* Event Control */ - register8_t INTCTRL; /* Interrupt Control */ - register8_t INTFLAGS; /* Interrupt Flags */ - register8_t DBGCTRL; /* Debug Control */ - register8_t TEMP; /* Temporary Data */ - register8_t reserved_0x0E; - register8_t reserved_0x0F; - _WORDREGISTER(RES); /* ADC Accumulator Result */ - _WORDREGISTER(WINLT); /* Window comparator low threshold */ - _WORDREGISTER(WINHT); /* Window comparator high threshold */ - register8_t CALIB; /* Calibration */ - register8_t reserved_0x17; -} ADC_t; - -/* Automatic Sampling Delay Variation select */ -typedef enum ADC_ASDV_enum -{ - ADC_ASDV_ASVOFF_gc = (0x00<<4), /* The Automatic Sampling Delay Variation is disabled */ - ADC_ASDV_ASVON_gc = (0x01<<4), /* The Automatic Sampling Delay Variation is enabled */ -} ADC_ASDV_t; - -/* Duty Cycle select */ -typedef enum ADC_DUTYCYC_enum -{ - ADC_DUTYCYC_DUTY50_gc = (0x00<<0), /* 50% Duty cycle */ - ADC_DUTYCYC_DUTY25_gc = (0x01<<0), /* 25% Duty cycle */ -} ADC_DUTYCYC_t; - -/* Initial Delay Selection select */ -typedef enum ADC_INITDLY_enum -{ - ADC_INITDLY_DLY0_gc = (0x00<<5), /* Delay 0 CLK_ADC cycles */ - ADC_INITDLY_DLY16_gc = (0x01<<5), /* Delay 16 CLK_ADC cycles */ - ADC_INITDLY_DLY32_gc = (0x02<<5), /* Delay 32 CLK_ADC cycles */ - ADC_INITDLY_DLY64_gc = (0x03<<5), /* Delay 64 CLK_ADC cycles */ - ADC_INITDLY_DLY128_gc = (0x04<<5), /* Delay 128 CLK_ADC cycles */ - ADC_INITDLY_DLY256_gc = (0x05<<5), /* Delay 256 CLK_ADC cycles */ -} ADC_INITDLY_t; - -/* Analog Channel Selection Bits select */ -typedef enum ADC_MUXPOS_enum -{ - ADC_MUXPOS_AIN0_gc = (0x00<<0), /* ADC input pin 0 */ - ADC_MUXPOS_AIN1_gc = (0x01<<0), /* ADC input pin 1 */ - ADC_MUXPOS_DACREF_gc = (0x1C<<0), /* AC DAC Reference */ - ADC_MUXPOS_TEMPSENSE_gc = (0x1E<<0), /* Temperature sensor */ - ADC_MUXPOS_GND_gc = (0x1F<<0), /* 0V (GND) */ - ADC_MUXPOS_AIN2_gc = (0x02<<0), /* ADC input pin 2 */ - ADC_MUXPOS_AIN3_gc = (0x03<<0), /* ADC input pin 3 */ - ADC_MUXPOS_AIN4_gc = (0x04<<0), /* ADC input pin 4 */ - ADC_MUXPOS_AIN5_gc = (0x05<<0), /* ADC input pin 5 */ - ADC_MUXPOS_AIN6_gc = (0x06<<0), /* ADC input pin 6 */ - ADC_MUXPOS_AIN7_gc = (0x07<<0), /* ADC input pin 7 */ - ADC_MUXPOS_AIN8_gc = (0x08<<0), /* ADC input pin 8 */ - ADC_MUXPOS_AIN9_gc = (0x09<<0), /* ADC input pin 9 */ - ADC_MUXPOS_AIN10_gc = (0x0A<<0), /* ADC input pin 10 */ - ADC_MUXPOS_AIN11_gc = (0x0B<<0), /* ADC input pin 11 */ - ADC_MUXPOS_AIN12_gc = (0x0C<<0), /* ADC input pin 12 */ - ADC_MUXPOS_AIN13_gc = (0x0D<<0), /* ADC input pin 13 */ - ADC_MUXPOS_AIN14_gc = (0x0E<<0), /* ADC input pin 14 */ - ADC_MUXPOS_AIN15_gc = (0x0F<<0), /* ADC input pin 15 */ -} ADC_MUXPOS_t; - -/* Clock Pre-scaler select */ -typedef enum ADC_PRESC_enum -{ - ADC_PRESC_DIV2_gc = (0x00<<0), /* CLK_PER divided by 2 */ - ADC_PRESC_DIV4_gc = (0x01<<0), /* CLK_PER divided by 4 */ - ADC_PRESC_DIV8_gc = (0x02<<0), /* CLK_PER divided by 8 */ - ADC_PRESC_DIV16_gc = (0x03<<0), /* CLK_PER divided by 16 */ - ADC_PRESC_DIV32_gc = (0x04<<0), /* CLK_PER divided by 32 */ - ADC_PRESC_DIV64_gc = (0x05<<0), /* CLK_PER divided by 64 */ - ADC_PRESC_DIV128_gc = (0x06<<0), /* CLK_PER divided by 128 */ - ADC_PRESC_DIV256_gc = (0x07<<0), /* CLK_PER divided by 256 */ -} ADC_PRESC_t; - -/* Reference Selection select */ -typedef enum ADC_REFSEL_enum -{ - ADC_REFSEL_INTREF_gc = (0x00<<4), /* Internal reference */ - ADC_REFSEL_VDDREF_gc = (0x01<<4), /* VDD */ - ADC_REFSEL_VREFA_gc = (0x02<<4), /* External reference */ -} ADC_REFSEL_t; - -/* ADC Resolution select */ -typedef enum ADC_RESSEL_enum -{ - ADC_RESSEL_10BIT_gc = (0x00<<2), /* 10-bit mode */ - ADC_RESSEL_8BIT_gc = (0x01<<2), /* 8-bit mode */ -} ADC_RESSEL_t; - -/* Accumulation Samples select */ -typedef enum ADC_SAMPNUM_enum -{ - ADC_SAMPNUM_ACC1_gc = (0x00<<0), /* 1 ADC sample */ - ADC_SAMPNUM_ACC2_gc = (0x01<<0), /* Accumulate 2 samples */ - ADC_SAMPNUM_ACC4_gc = (0x02<<0), /* Accumulate 4 samples */ - ADC_SAMPNUM_ACC8_gc = (0x03<<0), /* Accumulate 8 samples */ - ADC_SAMPNUM_ACC16_gc = (0x04<<0), /* Accumulate 16 samples */ - ADC_SAMPNUM_ACC32_gc = (0x05<<0), /* Accumulate 32 samples */ - ADC_SAMPNUM_ACC64_gc = (0x06<<0), /* Accumulate 64 samples */ -} ADC_SAMPNUM_t; - -/* Window Comparator Mode select */ -typedef enum ADC_WINCM_enum -{ - ADC_WINCM_NONE_gc = (0x00<<0), /* No Window Comparison */ - ADC_WINCM_BELOW_gc = (0x01<<0), /* Below Window */ - ADC_WINCM_ABOVE_gc = (0x02<<0), /* Above Window */ - ADC_WINCM_INSIDE_gc = (0x03<<0), /* Inside Window */ - ADC_WINCM_OUTSIDE_gc = (0x04<<0), /* Outside Window */ -} ADC_WINCM_t; - -/* --------------------------------------------------------------------------- -BOD - Bod interface --------------------------------------------------------------------------- -*/ - -/* Bod interface */ -typedef struct BOD_struct -{ - register8_t CTRLA; /* Control A */ - register8_t CTRLB; /* Control B */ - register8_t reserved_0x02; - register8_t reserved_0x03; - register8_t reserved_0x04; - register8_t reserved_0x05; - register8_t reserved_0x06; - register8_t reserved_0x07; - register8_t VLMCTRLA; /* Voltage level monitor Control */ - register8_t INTCTRL; /* Voltage level monitor interrupt Control */ - register8_t INTFLAGS; /* Voltage level monitor interrupt Flags */ - register8_t STATUS; /* Voltage level monitor status */ - register8_t reserved_0x0C; - register8_t reserved_0x0D; - register8_t reserved_0x0E; - register8_t reserved_0x0F; -} BOD_t; - -/* Operation in active mode select */ -typedef enum BOD_ACTIVE_enum -{ - BOD_ACTIVE_DIS_gc = (0x00<<2), /* Disabled */ - BOD_ACTIVE_ENABLED_gc = (0x01<<2), /* Enabled */ - BOD_ACTIVE_SAMPLED_gc = (0x02<<2), /* Sampled */ - BOD_ACTIVE_ENWAKE_gc = (0x03<<2), /* Enabled with wake-up halted until BOD is ready */ -} BOD_ACTIVE_t; - -/* Bod level select */ -typedef enum BOD_LVL_enum -{ - BOD_LVL_BODLEVEL0_gc = (0x00<<0), /* 1.8 V */ - BOD_LVL_BODLEVEL1_gc = (0x01<<0), /* 2.1 V */ - BOD_LVL_BODLEVEL2_gc = (0x02<<0), /* 2.6 V */ - BOD_LVL_BODLEVEL3_gc = (0x03<<0), /* 2.9 V */ - BOD_LVL_BODLEVEL4_gc = (0x04<<0), /* 3.3 V */ - BOD_LVL_BODLEVEL5_gc = (0x05<<0), /* 3.7 V */ - BOD_LVL_BODLEVEL6_gc = (0x06<<0), /* 4.0 V */ - BOD_LVL_BODLEVEL7_gc = (0x07<<0), /* 4.2 V */ -} BOD_LVL_t; - -/* Sample frequency select */ -typedef enum BOD_SAMPFREQ_enum -{ - BOD_SAMPFREQ_1KHZ_gc = (0x00<<4), /* 1kHz sampling frequency */ - BOD_SAMPFREQ_125HZ_gc = (0x01<<4), /* 125kHz sampling frequency */ -} BOD_SAMPFREQ_t; - -/* Operation in sleep mode select */ -typedef enum BOD_SLEEP_enum -{ - BOD_SLEEP_DIS_gc = (0x00<<0), /* Disabled */ - BOD_SLEEP_ENABLED_gc = (0x01<<0), /* Enabled */ - BOD_SLEEP_SAMPLED_gc = (0x02<<0), /* Sampled */ -} BOD_SLEEP_t; - -/* Configuration select */ -typedef enum BOD_VLMCFG_enum -{ - BOD_VLMCFG_BELOW_gc = (0x00<<1), /* Interrupt when supply goes below VLM level */ - BOD_VLMCFG_ABOVE_gc = (0x01<<1), /* Interrupt when supply goes above VLM level */ - BOD_VLMCFG_CROSS_gc = (0x02<<1), /* Interrupt when supply crosses VLM level */ -} BOD_VLMCFG_t; - -/* voltage level monitor level select */ -typedef enum BOD_VLMLVL_enum -{ - BOD_VLMLVL_5ABOVE_gc = (0x00<<0), /* VLM threshold 5% above BOD level */ - BOD_VLMLVL_15ABOVE_gc = (0x01<<0), /* VLM threshold 15% above BOD level */ - BOD_VLMLVL_25ABOVE_gc = (0x02<<0), /* VLM threshold 25% above BOD level */ -} BOD_VLMLVL_t; - -/* --------------------------------------------------------------------------- -CCL - Configurable Custom Logic --------------------------------------------------------------------------- -*/ - -/* Configurable Custom Logic */ -typedef struct CCL_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t SEQCTRL0; /* Sequential Control 0 */ - register8_t reserved_0x02; - register8_t reserved_0x03; - register8_t reserved_0x04; - register8_t INTCTRL0; /* Interrupt Control 0 */ - register8_t reserved_0x06; - register8_t INTFLAGS; /* Interrupt Flags */ - register8_t LUT0CTRLA; /* LUT Control 0 A */ - register8_t LUT0CTRLB; /* LUT Control 0 B */ - register8_t LUT0CTRLC; /* LUT Control 0 C */ - register8_t TRUTH0; /* Truth 0 */ - register8_t LUT1CTRLA; /* LUT Control 1 A */ - register8_t LUT1CTRLB; /* LUT Control 1 B */ - register8_t LUT1CTRLC; /* LUT Control 1 C */ - register8_t TRUTH1; /* Truth 1 */ - register8_t LUT2CTRLA; /* LUT Control 2 A */ - register8_t LUT2CTRLB; /* LUT Control 2 B */ - register8_t LUT2CTRLC; /* LUT Control 2 C */ - register8_t TRUTH2; /* Truth 2 */ - register8_t LUT3CTRLA; /* LUT Control 3 A */ - register8_t LUT3CTRLB; /* LUT Control 3 B */ - register8_t LUT3CTRLC; /* LUT Control 3 C */ - register8_t TRUTH3; /* Truth 3 */ - register8_t reserved_0x18; - register8_t reserved_0x19; - register8_t reserved_0x1A; - register8_t reserved_0x1B; - register8_t reserved_0x1C; - register8_t reserved_0x1D; - register8_t reserved_0x1E; - register8_t reserved_0x1F; - register8_t reserved_0x20; - register8_t reserved_0x21; - register8_t reserved_0x22; - register8_t reserved_0x23; - register8_t reserved_0x24; - register8_t reserved_0x25; - register8_t reserved_0x26; - register8_t reserved_0x27; - register8_t reserved_0x28; - register8_t reserved_0x29; - register8_t reserved_0x2A; - register8_t reserved_0x2B; - register8_t reserved_0x2C; - register8_t reserved_0x2D; - register8_t reserved_0x2E; - register8_t reserved_0x2F; - register8_t reserved_0x30; - register8_t reserved_0x31; - register8_t reserved_0x32; - register8_t reserved_0x33; - register8_t reserved_0x34; - register8_t reserved_0x35; - register8_t reserved_0x36; - register8_t reserved_0x37; - register8_t reserved_0x38; - register8_t reserved_0x39; - register8_t reserved_0x3A; - register8_t reserved_0x3B; - register8_t reserved_0x3C; - register8_t reserved_0x3D; - register8_t reserved_0x3E; - register8_t reserved_0x3F; -} CCL_t; - -/* Clock Source Selection select */ -typedef enum CCL_CLKSRC_enum -{ - CCL_CLKSRC_CLKPER_gc = (0x00<<1), /* CLK_PER is clocking the LUT */ - CCL_CLKSRC_IN2_gc = (0x01<<1), /* IN[2] is clocking the LUT */ - CCL_CLKSRC_OSC20M_gc = (0x02<<1), /* 20MHz oscillator before prescaler is clocking the LUT */ - CCL_CLKSRC_OSCULP32K_gc = (0x03<<1), /* 32kHz oscillator is clocking the LUT */ - CCL_CLKSRC_OSCULP1K_gc = (0x04<<1), /* 32kHz oscillator after DIV32 is clocking the LUT */ -} CCL_CLKSRC_t; - -/* Edge Detection Enable select */ -typedef enum CCL_EDGEDET_enum -{ - CCL_EDGEDET_DIS_gc = (0x00<<7), /* Edge detector is disabled */ - CCL_EDGEDET_EN_gc = (0x01<<7), /* Edge detector is enabled */ -} CCL_EDGEDET_t; - -/* Filter Selection select */ -typedef enum CCL_FILTSEL_enum -{ - CCL_FILTSEL_DISABLE_gc = (0x00<<4), /* Filter disabled */ - CCL_FILTSEL_SYNCH_gc = (0x01<<4), /* Synchronizer enabled */ - CCL_FILTSEL_FILTER_gc = (0x02<<4), /* Filter enabled */ -} CCL_FILTSEL_t; - -/* LUT Input 0 Source Selection select */ -typedef enum CCL_INSEL0_enum -{ - CCL_INSEL0_MASK_gc = (0x00<<0), /* Masked input */ - CCL_INSEL0_FEEDBACK_gc = (0x01<<0), /* Feedback input source */ - CCL_INSEL0_LINK_gc = (0x02<<0), /* Linked LUT input source */ - CCL_INSEL0_EVENTA_gc = (0x03<<0), /* Event input source A */ - CCL_INSEL0_EVENTB_gc = (0x04<<0), /* Event input source B */ - CCL_INSEL0_IO_gc = (0x05<<0), /* IO pin LUTn-IN0 input source */ - CCL_INSEL0_AC0_gc = (0x06<<0), /* AC0 OUT input source */ - CCL_INSEL0_USART0_gc = (0x08<<0), /* USART0 TXD input source */ - CCL_INSEL0_SPI0_gc = (0x09<<0), /* SPI0 MOSI input source */ - CCL_INSEL0_TCA0_gc = (0x0A<<0), /* TCA0 WO0 input source */ - CCL_INSEL0_TCB0_gc = (0x0C<<0), /* TCB0 WO input source */ - CCL_INSEL0_TCD0_gc = (0x0D<<0), /* TCD0 WOA input source */ -} CCL_INSEL0_t; - -/* LUT Input 1 Source Selection select */ -typedef enum CCL_INSEL1_enum -{ - CCL_INSEL1_MASK_gc = (0x00<<4), /* Masked input */ - CCL_INSEL1_FEEDBACK_gc = (0x01<<4), /* Feedback input source */ - CCL_INSEL1_LINK_gc = (0x02<<4), /* Linked LUT input source */ - CCL_INSEL1_EVENTA_gc = (0x03<<4), /* Event input source A */ - CCL_INSEL1_EVENTB_gc = (0x04<<4), /* Event input source B */ - CCL_INSEL1_IO_gc = (0x05<<4), /* IO pin LUTn-N1 input source */ - CCL_INSEL1_AC0_gc = (0x06<<4), /* AC0 OUT input source */ - CCL_INSEL1_USART1_gc = (0x08<<4), /* USART1 TXD input source */ - CCL_INSEL1_SPI0_gc = (0x09<<4), /* SPI0 MOSI input source */ - CCL_INSEL1_TCA0_gc = (0x0A<<4), /* TCA0 WO1 input source */ - CCL_INSEL1_TCB1_gc = (0x0C<<4), /* TCB1 WO input source */ - CCL_INSEL1_TCD0_gc = (0x0D<<4), /* TCD0 WOB input soruce */ -} CCL_INSEL1_t; - -/* LUT Input 2 Source Selection select */ -typedef enum CCL_INSEL2_enum -{ - CCL_INSEL2_MASK_gc = (0x00<<0), /* Masked input */ - CCL_INSEL2_FEEDBACK_gc = (0x01<<0), /* Feedback input source */ - CCL_INSEL2_LINK_gc = (0x02<<0), /* Linked LUT input source */ - CCL_INSEL2_EVENTA_gc = (0x03<<0), /* Event input source A */ - CCL_INSEL2_EVENTB_gc = (0x04<<0), /* Event input source B */ - CCL_INSEL2_IO_gc = (0x05<<0), /* IO pin LUTn-IN2 input source */ - CCL_INSEL2_AC0_gc = (0x06<<0), /* AC0 OUT input source */ - CCL_INSEL2_USART2_gc = (0x08<<0), /* USART2 TXD input source */ - CCL_INSEL2_SPI0_gc = (0x09<<0), /* SPI0 SCK input source */ - CCL_INSEL2_TCA0_gc = (0x0A<<0), /* TCA0 WO2 input source */ - CCL_INSEL2_TCB2_gc = (0x0C<<0), /* TCB2 WO input source */ - CCL_INSEL2_TCD0_gc = (0x0D<<0), /* TCD0 WOC input source */ -} CCL_INSEL2_t; - -/* Interrupt Mode for LUT0 select */ -typedef enum CCL_INTMODE0_enum -{ - CCL_INTMODE0_BOTH_gc = (0x00<<0), /* Sense both edges */ - CCL_INTMODE0_FALLING_gc = (0x01<<0), /* Sense falling edge */ - CCL_INTMODE0_RISING_gc = (0x02<<0), /* Sense rising edge */ - CCL_INTMODE0_INTDISABLE_gc = (0x03<<0), /* Interrupt disabled */ -} CCL_INTMODE0_t; - -/* Interrupt Mode for LUT1 select */ -typedef enum CCL_INTMODE1_enum -{ - CCL_INTMODE1_BOTH_gc = (0x00<<2), /* Sense both edges */ - CCL_INTMODE1_FALLING_gc = (0x01<<2), /* Sense falling edge */ - CCL_INTMODE1_RISING_gc = (0x02<<2), /* Sense rising edge */ - CCL_INTMODE1_INTDISABLE_gc = (0x03<<2), /* Interrupt disabled */ -} CCL_INTMODE1_t; - -/* Interrupt Mode for LUT2 select */ -typedef enum CCL_INTMODE2_enum -{ - CCL_INTMODE2_BOTH_gc = (0x00<<4), /* Sense both edges */ - CCL_INTMODE2_FALLING_gc = (0x01<<4), /* Sense falling edge */ - CCL_INTMODE2_RISING_gc = (0x02<<4), /* Sense rising edge */ - CCL_INTMODE2_INTDISABLE_gc = (0x03<<4), /* Interrupt disabled */ -} CCL_INTMODE2_t; - -/* Interrupt Mode for LUT3 select */ -typedef enum CCL_INTMODE3_enum -{ - CCL_INTMODE3_BOTH_gc = (0x00<<6), /* Sense both edges */ - CCL_INTMODE3_FALLING_gc = (0x01<<6), /* Sense falling edge */ - CCL_INTMODE3_RISING_gc = (0x02<<6), /* Sense rising edge */ - CCL_INTMODE3_INTDISABLE_gc = (0x03<<6), /* Interrupt disabled */ -} CCL_INTMODE3_t; - -/* Sequential Selection select */ -typedef enum CCL_SEQSEL_enum -{ - CCL_SEQSEL_DISABLE_gc = (0x00<<0), /* Sequential logic disabled */ - CCL_SEQSEL_DFF_gc = (0x01<<0), /* D FlipFlop */ - CCL_SEQSEL_JK_gc = (0x02<<0), /* JK FlipFlop */ - CCL_SEQSEL_LATCH_gc = (0x03<<0), /* D Latch */ - CCL_SEQSEL_RS_gc = (0x04<<0), /* RS Latch */ -} CCL_SEQSEL_t; - -/* --------------------------------------------------------------------------- -CLKCTRL - Clock controller --------------------------------------------------------------------------- -*/ - -/* Clock controller */ -typedef struct CLKCTRL_struct -{ - register8_t MCLKCTRLA; /* MCLK Control A */ - register8_t MCLKCTRLB; /* MCLK Control B */ - register8_t MCLKLOCK; /* MCLK Lock */ - register8_t MCLKSTATUS; /* MCLK Status */ - register8_t reserved_0x04; - register8_t reserved_0x05; - register8_t reserved_0x06; - register8_t reserved_0x07; - register8_t reserved_0x08; - register8_t reserved_0x09; - register8_t reserved_0x0A; - register8_t reserved_0x0B; - register8_t reserved_0x0C; - register8_t reserved_0x0D; - register8_t reserved_0x0E; - register8_t reserved_0x0F; - register8_t OSC20MCTRLA; /* OSC20M Control A */ - register8_t OSC20MCALIBA; /* OSC20M Calibration A */ - register8_t OSC20MCALIBB; /* OSC20M Calibration B */ - register8_t reserved_0x13; - register8_t reserved_0x14; - register8_t reserved_0x15; - register8_t reserved_0x16; - register8_t reserved_0x17; - register8_t OSC32KCTRLA; /* OSC32K Control A */ - register8_t OSC32KCALIB; /* OSC32K Calibration */ - register8_t reserved_0x1A; - register8_t reserved_0x1B; - register8_t XOSC32KCTRLA; /* XOSC32K Control A */ - register8_t reserved_0x1D; - register8_t reserved_0x1E; - register8_t reserved_0x1F; -} CLKCTRL_t; - -/* clock select select */ -typedef enum CLKCTRL_CLKSEL_enum -{ - CLKCTRL_CLKSEL_OSC20M_gc = (0x00<<0), /* 20MHz oscillator */ - CLKCTRL_CLKSEL_OSCULP32K_gc = (0x01<<0), /* 32KHz oscillator */ - CLKCTRL_CLKSEL_XOSC32K_gc = (0x02<<0), /* 32.768kHz crystal oscillator */ - CLKCTRL_CLKSEL_EXTCLK_gc = (0x03<<0), /* External clock */ -} CLKCTRL_CLKSEL_t; - -/* Crystal startup time select */ -typedef enum CLKCTRL_CSUT_enum -{ - CLKCTRL_CSUT_1K_gc = (0x00<<4), /* 1k cycles */ - CLKCTRL_CSUT_16K_gc = (0x01<<4), /* 16k cycles */ - CLKCTRL_CSUT_32K_gc = (0x02<<4), /* 32k cycles */ - CLKCTRL_CSUT_64K_gc = (0x03<<4), /* 64k cycles */ -} CLKCTRL_CSUT_t; - -/* Prescaler division select */ -typedef enum CLKCTRL_PDIV_enum -{ - CLKCTRL_PDIV_2X_gc = (0x00<<1), /* 2X */ - CLKCTRL_PDIV_4X_gc = (0x01<<1), /* 4X */ - CLKCTRL_PDIV_8X_gc = (0x02<<1), /* 8X */ - CLKCTRL_PDIV_16X_gc = (0x03<<1), /* 16X */ - CLKCTRL_PDIV_32X_gc = (0x04<<1), /* 32X */ - CLKCTRL_PDIV_64X_gc = (0x05<<1), /* 64X */ - CLKCTRL_PDIV_6X_gc = (0x08<<1), /* 6X */ - CLKCTRL_PDIV_10X_gc = (0x09<<1), /* 10X */ - CLKCTRL_PDIV_12X_gc = (0x0A<<1), /* 12X */ - CLKCTRL_PDIV_24X_gc = (0x0B<<1), /* 24X */ - CLKCTRL_PDIV_48X_gc = (0x0C<<1), /* 48X */ -} CLKCTRL_PDIV_t; - -/* --------------------------------------------------------------------------- -CPU - CPU --------------------------------------------------------------------------- -*/ - -/* CCP signature select */ -typedef enum CCP_enum -{ - CCP_SPM_gc = (0x9D<<0), /* SPM Instruction Protection */ - CCP_IOREG_gc = (0xD8<<0), /* IO Register Protection */ -} CCP_t; - -/* --------------------------------------------------------------------------- -CPUINT - Interrupt Controller --------------------------------------------------------------------------- -*/ - -/* Interrupt Controller */ -typedef struct CPUINT_struct -{ - register8_t CTRLA; /* Control A */ - register8_t STATUS; /* Status */ - register8_t LVL0PRI; /* Interrupt Level 0 Priority */ - register8_t LVL1VEC; /* Interrupt Level 1 Priority Vector */ -} CPUINT_t; - - -/* --------------------------------------------------------------------------- -CRCSCAN - CRCSCAN --------------------------------------------------------------------------- -*/ - -/* CRCSCAN */ -typedef struct CRCSCAN_struct -{ - register8_t CTRLA; /* Control A */ - register8_t CTRLB; /* Control B */ - register8_t STATUS; /* Status */ - register8_t reserved_0x03; -} CRCSCAN_t; - -/* CRC Flash Access Mode select */ -typedef enum CRCSCAN_MODE_enum -{ - CRCSCAN_MODE_PRIORITY_gc = (0x00<<4), /* Priority to flash */ - CRCSCAN_MODE_RESERVED_gc = (0x01<<4), /* Reserved */ - CRCSCAN_MODE_BACKGROUND_gc = (0x02<<4), /* Lowest priority to flash */ - CRCSCAN_MODE_CONTINUOUS_gc = (0x03<<4), /* Continuous checks in background */ -} CRCSCAN_MODE_t; - -/* CRC Source select */ -typedef enum CRCSCAN_SRC_enum -{ - CRCSCAN_SRC_FLASH_gc = (0x00<<0), /* CRC on entire flash */ - CRCSCAN_SRC_APPLICATION_gc = (0x01<<0), /* CRC on boot and appl section of flash */ - CRCSCAN_SRC_BOOT_gc = (0x02<<0), /* CRC on boot section of flash */ -} CRCSCAN_SRC_t; - -/* --------------------------------------------------------------------------- -EVSYS - Event System --------------------------------------------------------------------------- -*/ - -/* Event System */ -typedef struct EVSYS_struct -{ - register8_t STROBE; /* Channel Strobe */ - register8_t reserved_0x01; - register8_t reserved_0x02; - register8_t reserved_0x03; - register8_t reserved_0x04; - register8_t reserved_0x05; - register8_t reserved_0x06; - register8_t reserved_0x07; - register8_t reserved_0x08; - register8_t reserved_0x09; - register8_t reserved_0x0A; - register8_t reserved_0x0B; - register8_t reserved_0x0C; - register8_t reserved_0x0D; - register8_t reserved_0x0E; - register8_t reserved_0x0F; - register8_t CHANNEL0; /* Multiplexer Channel 0 */ - register8_t CHANNEL1; /* Multiplexer Channel 1 */ - register8_t CHANNEL2; /* Multiplexer Channel 2 */ - register8_t CHANNEL3; /* Multiplexer Channel 3 */ - register8_t CHANNEL4; /* Multiplexer Channel 4 */ - register8_t CHANNEL5; /* Multiplexer Channel 5 */ - register8_t CHANNEL6; /* Multiplexer Channel 6 */ - register8_t CHANNEL7; /* Multiplexer Channel 7 */ - register8_t reserved_0x18; - register8_t reserved_0x19; - register8_t reserved_0x1A; - register8_t reserved_0x1B; - register8_t reserved_0x1C; - register8_t reserved_0x1D; - register8_t reserved_0x1E; - register8_t reserved_0x1F; - register8_t USERCCLLUT0A; /* User CCL LUT0 Event A */ - register8_t USERCCLLUT0B; /* User CCL LUT0 Event B */ - register8_t USERCCLLUT1A; /* User CCL LUT1 Event A */ - register8_t USERCCLLUT1B; /* User CCL LUT1 Event B */ - register8_t USERCCLLUT2A; /* User CCL LUT2 Event A */ - register8_t USERCCLLUT2B; /* User CCL LUT2 Event B */ - register8_t USERCCLLUT3A; /* User CCL LUT3 Event A */ - register8_t USERCCLLUT3B; /* User CCL LUT3 Event B */ - register8_t USERADC0; /* User ADC0 */ - register8_t USEREVOUTA; /* User EVOUT Port A */ - register8_t USEREVOUTB; /* User EVOUT Port B */ - register8_t USEREVOUTC; /* User EVOUT Port C */ - register8_t USEREVOUTD; /* User EVOUT Port D */ - register8_t USEREVOUTE; /* User EVOUT Port E */ - register8_t USEREVOUTF; /* User EVOUT Port F */ - register8_t USERUSART0; /* User USART0 */ - register8_t USERUSART1; /* User USART1 */ - register8_t USERUSART2; /* User USART2 */ - register8_t USERUSART3; /* User USART3 */ - register8_t USERTCA0; /* User TCA0 */ - register8_t USERTCB0; /* User TCB0 */ - register8_t USERTCB1; /* User TCB1 */ - register8_t USERTCB2; /* User TCB2 */ - register8_t USERTCB3; /* User TCB3 */ - register8_t reserved_0x38; - register8_t reserved_0x39; - register8_t reserved_0x3A; - register8_t reserved_0x3B; - register8_t reserved_0x3C; - register8_t reserved_0x3D; - register8_t reserved_0x3E; - register8_t reserved_0x3F; -} EVSYS_t; - -/* Channel selector select */ -typedef enum EVSYS_CHANNEL_enum -{ - EVSYS_CHANNEL_OFF_gc = (0x00<<0), /* Off */ - EVSYS_CHANNEL_CHANNEL0_gc = (0x01<<0), /* Connect user to event channel 0 */ - EVSYS_CHANNEL_CHANNEL1_gc = (0x02<<0), /* Connect user to event channel 1 */ - EVSYS_CHANNEL_CHANNEL2_gc = (0x03<<0), /* Connect user to event channel 2 */ - EVSYS_CHANNEL_CHANNEL3_gc = (0x04<<0), /* Connect user to event channel 3 */ - EVSYS_CHANNEL_CHANNEL4_gc = (0x05<<0), /* Connect user to event channel 4 */ - EVSYS_CHANNEL_CHANNEL5_gc = (0x06<<0), /* Connect user to event channel 5 */ - EVSYS_CHANNEL_CHANNEL6_gc = (0x07<<0), /* Connect user to event channel 6 */ - EVSYS_CHANNEL_CHANNEL7_gc = (0x08<<0), /* Connect user to event channel 7 */ -} EVSYS_CHANNEL_t; - -/* Generator selector select */ -typedef enum EVSYS_GENERATOR_enum -{ - EVSYS_GENERATOR_OFF_gc = (0x00<<0), /* Off */ - EVSYS_GENERATOR_UPDI_gc = (0x01<<0), /* Unified Program and Debug Interface */ - EVSYS_GENERATOR_CCL_LUT0_gc = (0x10<<0), /* Configurable Custom Logic LUT0 */ - EVSYS_GENERATOR_CCL_LUT1_gc = (0x11<<0), /* Configurable Custom Logic LUT1 */ - EVSYS_GENERATOR_CCL_LUT2_gc = (0x12<<0), /* Configurable Custom Logic LUT2 */ - EVSYS_GENERATOR_CCL_LUT3_gc = (0x13<<0), /* Configurable Custom Logic LUT3 */ - EVSYS_GENERATOR_OSC_TEST_gc = (0x02<<0), /* Oscillator test event */ - EVSYS_GENERATOR_AC0_OUT_gc = (0x20<<0), /* Analog Comparator 0 out */ - EVSYS_GENERATOR_ADC0_COMP_gc = (0x24<<0), /* ADC 0 Comparator Event */ - EVSYS_GENERATOR_PORT0_PIN0_gc = (0x40<<0), /* Port 0 Pin 0 */ - EVSYS_GENERATOR_PORT0_PIN1_gc = (0x41<<0), /* Port 0 Pin 1 */ - EVSYS_GENERATOR_PORT0_PIN2_gc = (0x42<<0), /* Port 0 Pin 2 */ - EVSYS_GENERATOR_PORT0_PIN3_gc = (0x43<<0), /* Port 0 Pin 3 */ - EVSYS_GENERATOR_PORT0_PIN4_gc = (0x44<<0), /* Port 0 Pin 4 */ - EVSYS_GENERATOR_PORT0_PIN5_gc = (0x45<<0), /* Port 0 Pin 5 */ - EVSYS_GENERATOR_PORT0_PIN6_gc = (0x46<<0), /* Port 0 Pin 6 */ - EVSYS_GENERATOR_PORT0_PIN7_gc = (0x47<<0), /* Port 0 Pin 7 */ - EVSYS_GENERATOR_PORT1_PIN0_gc = (0x48<<0), /* Port 1 Pin 0 */ - EVSYS_GENERATOR_PORT1_PIN1_gc = (0x49<<0), /* Port 1 Pin 1 */ - EVSYS_GENERATOR_PORT1_PIN2_gc = (0x4A<<0), /* Port 1 Pin 2 */ - EVSYS_GENERATOR_PORT1_PIN3_gc = (0x4B<<0), /* Port 1 Pin 3 */ - EVSYS_GENERATOR_PORT1_PIN4_gc = (0x4C<<0), /* Port 1 Pin 4 */ - EVSYS_GENERATOR_PORT1_PIN5_gc = (0x4D<<0), /* Port 1 Pin 5 */ - EVSYS_GENERATOR_PORT1_PIN6_gc = (0x4E<<0), /* Port 1 Pin 6 */ - EVSYS_GENERATOR_PORT1_PIN7_gc = (0x4F<<0), /* Port 1 Pin 7 */ - EVSYS_GENERATOR_RTC_OVF_gc = (0x06<<0), /* Real Time Counter overflow */ - EVSYS_GENERATOR_USART0_XCK_gc = (0x60<<0), /* USART 0 Xclock */ - EVSYS_GENERATOR_USART1_XCK_gc = (0x61<<0), /* USART 1 Xclock */ - EVSYS_GENERATOR_USART2_XCK_gc = (0x62<<0), /* USART 2 Xclock */ - EVSYS_GENERATOR_USART3_XCK_gc = (0x63<<0), /* USART 3 Xclock */ - EVSYS_GENERATOR_SPI0_SCK_gc = (0x68<<0), /* SPI 0 Sclock */ - EVSYS_GENERATOR_RTC_CMP_gc = (0x07<<0), /* Real Time Counter compare */ - EVSYS_GENERATOR_RTC_PIT0_gc = (0x08<<0), /* Periodic Interrupt Timer output 0 */ - EVSYS_GENERATOR_TCA0_OVF_gc = (0x80<<0), /* Timer/Counter A0 overflow */ - EVSYS_GENERATOR_TCA0_ERR_gc = (0x81<<0), /* Timer/Counter A0 error */ - EVSYS_GENERATOR_TCA0_CMP0_gc = (0x84<<0), /* Timer/Counter A0 compare 0 */ - EVSYS_GENERATOR_TCA0_CMP1_gc = (0x85<<0), /* Timer/Counter A0 compare 1 */ - EVSYS_GENERATOR_TCA0_CMP2_gc = (0x86<<0), /* Timer/Counter A0 compare 2 */ - EVSYS_GENERATOR_RTC_PIT1_gc = (0x09<<0), /* Periodic Interrupt Timer output 1 */ - EVSYS_GENERATOR_RTC_PIT2_gc = (0x0A<<0), /* Periodic Interrupt Timer output 2 */ - EVSYS_GENERATOR_TCB0_CMP0_gc = (0xA0<<0), /* Timer/Counter B0 compare 0 */ - EVSYS_GENERATOR_TCB1_CMP0_gc = (0xA2<<0), /* Timer/Counter B1 compare 0 */ - EVSYS_GENERATOR_TCB2_CMP0_gc = (0xA4<<0), /* Timer/Counter B2 compare 0 */ - EVSYS_GENERATOR_TCB3_CMP0_gc = (0xA6<<0), /* Timer/Counter B3 compare 0 */ - EVSYS_GENERATOR_RTC_PIT3_gc = (0x0B<<0), /* Periodic Interrupt Timer output 3 */ -} EVSYS_GENERATOR_t; - -/* Software event on channels select */ -typedef enum EVSYS_STROBE0_enum -{ - EVSYS_STROBE0_EV_STROBE_CH0_gc = (0x01<<0), /* */ - EVSYS_STROBE0_EV_STROBE_CH1_gc = (0x02<<0), /* */ - EVSYS_STROBE0_EV_STROBE_CH2_gc = (0x04<<0), /* */ - EVSYS_STROBE0_EV_STROBE_CH3_gc = (0x08<<0), /* */ - EVSYS_STROBE0_EV_STROBE_CH4_gc = (0x10<<0), /* */ - EVSYS_STROBE0_EV_STROBE_CH5_gc = (0x20<<0), /* */ - EVSYS_STROBE0_EV_STROBE_CH6_gc = (0x40<<0), /* */ - EVSYS_STROBE0_EV_STROBE_CH7_gc = (0x80<<0), /* */ -} EVSYS_STROBE0_t; - -/* --------------------------------------------------------------------------- -FUSE - Fuses --------------------------------------------------------------------------- -*/ - -/* Fuses */ -typedef struct FUSE_struct -{ - register8_t WDTCFG; /* Watchdog Configuration */ - register8_t BODCFG; /* BOD Configuration */ - register8_t OSCCFG; /* Oscillator Configuration */ - register8_t reserved_0x03; - register8_t TCD0CFG; /* TCD0 Configuration */ - register8_t SYSCFG0; /* System Configuration 0 */ - register8_t SYSCFG1; /* System Configuration 1 */ - register8_t APPEND; /* Application Code Section End */ - register8_t BOOTEND; /* Boot Section End */ - register8_t reserved_0x09; -} FUSE_t; - - -/* avr-libc typedef for avr/fuse.h */ -typedef FUSE_t NVM_FUSES_t; - -/* BOD Operation in Active Mode select */ -typedef enum ACTIVE_enum -{ - ACTIVE_DIS_gc = (0x00<<2), /* Disabled */ - ACTIVE_ENABLED_gc = (0x01<<2), /* Enabled */ - ACTIVE_SAMPLED_gc = (0x02<<2), /* Sampled */ - ACTIVE_ENWAKE_gc = (0x03<<2), /* Enabled with wake-up halted until BOD is ready */ -} ACTIVE_t; - -/* CRC Source select */ -typedef enum CRCSRC_enum -{ - CRCSRC_FLASH_gc = (0x00<<6), /* The CRC is performed on the entire Flash (boot, application code and application data section). */ - CRCSRC_BOOT_gc = (0x01<<6), /* The CRC is performed on the boot section of Flash */ - CRCSRC_BOOTAPP_gc = (0x02<<6), /* The CRC is performed on the boot and application code section of Flash */ - CRCSRC_NOCRC_gc = (0x03<<6), /* Disable CRC. */ -} CRCSRC_t; - -/* Frequency Select select */ -typedef enum FREQSEL_enum -{ - FREQSEL_16MHZ_gc = (0x01<<0), /* 16 MHz */ - FREQSEL_20MHZ_gc = (0x02<<0), /* 20 MHz */ -} FREQSEL_t; - -/* BOD Level select */ -typedef enum LVL_enum -{ - LVL_BODLEVEL0_gc = (0x00<<5), /* 1.8 V */ - LVL_BODLEVEL1_gc = (0x01<<5), /* 2.1 V */ - LVL_BODLEVEL2_gc = (0x02<<5), /* 2.6 V */ - LVL_BODLEVEL3_gc = (0x03<<5), /* 2.9 V */ - LVL_BODLEVEL4_gc = (0x04<<5), /* 3.3 V */ - LVL_BODLEVEL5_gc = (0x05<<5), /* 3.7 V */ - LVL_BODLEVEL6_gc = (0x06<<5), /* 4.0 V */ - LVL_BODLEVEL7_gc = (0x07<<5), /* 4.2 V */ -} LVL_t; - -/* Watchdog Timeout Period select */ -typedef enum PERIOD_enum -{ - PERIOD_OFF_gc = (0x00<<0), /* Off */ - PERIOD_8CLK_gc = (0x01<<0), /* 8 cycles (8ms) */ - PERIOD_16CLK_gc = (0x02<<0), /* 16 cycles (16ms) */ - PERIOD_32CLK_gc = (0x03<<0), /* 32 cycles (32ms) */ - PERIOD_64CLK_gc = (0x04<<0), /* 64 cycles (64ms) */ - PERIOD_128CLK_gc = (0x05<<0), /* 128 cycles (0.128s) */ - PERIOD_256CLK_gc = (0x06<<0), /* 256 cycles (0.256s) */ - PERIOD_512CLK_gc = (0x07<<0), /* 512 cycles (0.512s) */ - PERIOD_1KCLK_gc = (0x08<<0), /* 1K cycles (1.0s) */ - PERIOD_2KCLK_gc = (0x09<<0), /* 2K cycles (2.0s) */ - PERIOD_4KCLK_gc = (0x0A<<0), /* 4K cycles (4.1s) */ - PERIOD_8KCLK_gc = (0x0B<<0), /* 8K cycles (8.2s) */ -} PERIOD_t; - -/* Reset Pin Configuration select */ -typedef enum RSTPINCFG_enum -{ - RSTPINCFG_GPIO_gc = (0x00<<2), /* GPIO mode */ - RSTPINCFG_UPDI_gc = (0x01<<2), /* UPDI mode */ - RSTPINCFG_RST_gc = (0x02<<2), /* Reset mode */ - RSTPINCFG_PDIRST_gc = (0x03<<2), /* PDI on PDI pad, reset on alternative reset pad */ -} RSTPINCFG_t; - -/* BOD Sample Frequency select */ -typedef enum SAMPFREQ_enum -{ - SAMPFREQ_1KHZ_gc = (0x00<<4), /* 1kHz sampling frequency */ - SAMPFREQ_125HZ_gc = (0x01<<4), /* 125kHz sampling frequency */ -} SAMPFREQ_t; - -/* BOD Operation in Sleep Mode select */ -typedef enum SLEEP_enum -{ - SLEEP_DIS_gc = (0x00<<0), /* Disabled */ - SLEEP_ENABLED_gc = (0x01<<0), /* Enabled */ - SLEEP_SAMPLED_gc = (0x02<<0), /* Sampled */ -} SLEEP_t; - -/* Startup Time select */ -typedef enum SUT_enum -{ - SUT_0MS_gc = (0x00<<0), /* 0 ms */ - SUT_1MS_gc = (0x01<<0), /* 1 ms */ - SUT_2MS_gc = (0x02<<0), /* 2 ms */ - SUT_4MS_gc = (0x03<<0), /* 4 ms */ - SUT_8MS_gc = (0x04<<0), /* 8 ms */ - SUT_16MS_gc = (0x05<<0), /* 16 ms */ - SUT_32MS_gc = (0x06<<0), /* 32 ms */ - SUT_64MS_gc = (0x07<<0), /* 64 ms */ -} SUT_t; - -/* Watchdog Window Timeout Period select */ -typedef enum WINDOW_enum -{ - WINDOW_OFF_gc = (0x00<<4), /* Off */ - WINDOW_8CLK_gc = (0x01<<4), /* 8 cycles (8ms) */ - WINDOW_16CLK_gc = (0x02<<4), /* 16 cycles (16ms) */ - WINDOW_32CLK_gc = (0x03<<4), /* 32 cycles (32ms) */ - WINDOW_64CLK_gc = (0x04<<4), /* 64 cycles (64ms) */ - WINDOW_128CLK_gc = (0x05<<4), /* 128 cycles (0.128s) */ - WINDOW_256CLK_gc = (0x06<<4), /* 256 cycles (0.256s) */ - WINDOW_512CLK_gc = (0x07<<4), /* 512 cycles (0.512s) */ - WINDOW_1KCLK_gc = (0x08<<4), /* 1K cycles (1.0s) */ - WINDOW_2KCLK_gc = (0x09<<4), /* 2K cycles (2.0s) */ - WINDOW_4KCLK_gc = (0x0A<<4), /* 4K cycles (4.1s) */ - WINDOW_8KCLK_gc = (0x0B<<4), /* 8K cycles (8.2s) */ -} WINDOW_t; - -/* --------------------------------------------------------------------------- -LOCKBIT - Lockbit --------------------------------------------------------------------------- -*/ - -/* Lockbit */ -typedef struct LOCKBIT_struct -{ - register8_t LOCKBIT; /* Lock Bits */ - register8_t reserved_0x01; -} LOCKBIT_t; - -/* Lock Bits select */ -typedef enum LB_enum -{ - LB_RWLOCK_gc = (0x3A<<0), /* Read and write lock */ - LB_NOLOCK_gc = (0xC5<<0), /* No locks */ -} LB_t; - -/* --------------------------------------------------------------------------- -NVMBIST - BIST in the NVMCTRL module --------------------------------------------------------------------------- -*/ - -/* BIST in the NVMCTRL module */ -typedef struct NVMBIST_struct -{ - register8_t CTRLA; /* Control A */ - register8_t ADDRPAT; /* Address pattern */ - register8_t DATAPAT; /* Data pattern */ - register8_t STATUS; /* Status */ - _WORDREGISTER(CNT); /* */ - _DWORDREGISTER(END); /* */ - register8_t reserved_0x0A; - register8_t reserved_0x0B; - register8_t reserved_0x0C; - register8_t reserved_0x0D; - register8_t reserved_0x0E; - register8_t reserved_0x0F; -} NVMBIST_t; - -/* Address mode select */ -typedef enum NVMBIST_AMODE_enum -{ - NVMBIST_AMODE_NORMAL_gc = (0x00<<4), /* No special address pattern */ - NVMBIST_AMODE_COMPLEMENT_gc = (0x04<<4), /* Post complement address */ -} NVMBIST_AMODE_t; - -/* Command select */ -typedef enum NVMBIST_CMD_enum -{ - NVMBIST_CMD_NOCMD_gc = (0x00<<0), /* No effect */ - NVMBIST_CMD_START_gc = (0x01<<0), /* Start BIST testing */ - NVMBIST_CMD_RESTART_gc = (0x02<<0), /* Re-start BIST testing */ - NVMBIST_CMD_BREAK_gc = (0x03<<0), /* Stop BIST and go to BREAK state */ -} NVMBIST_CMD_t; - -/* Data check pattern select */ -typedef enum NVMBIST_PATTERN_enum -{ - NVMBIST_PATTERN_ZEROES_gc = (0x00<<0), /* All flash programmed */ - NVMBIST_PATTERN_CHECK_gc = (0x01<<0), /* Physical checkerboard in flash */ - NVMBIST_PATTERN_INVCHECK_gc = (0x02<<0), /* Inverse physical checkerboard in flash */ - NVMBIST_PATTERN_ONES_gc = (0x03<<0), /* All flash unprogrammed */ -} NVMBIST_PATTERN_t; - -/* FSM State select */ -typedef enum NVMBIST_STATE_enum -{ - NVMBIST_STATE_IDLE_gc = (0x00<<0), /* Reset state */ - NVMBIST_STATE_BREAK_gc = (0x01<<0), /* Break command used */ - NVMBIST_STATE_FAILED0_gc = (0x04<<0), /* Test failed, data from last address */ - NVMBIST_STATE_FAILED1_gc = (0x05<<0), /* Test failed, data from address-1 */ - NVMBIST_STATE_FAILED2_gc = (0x06<<0), /* Test failed, data from address-2 */ - NVMBIST_STATE_SUCCESS_gc = (0x07<<0), /* Test success */ - NVMBIST_STATE_START0_gc = (0x08<<0), /* Startup, fetching first data */ - NVMBIST_STATE_START1_gc = (0x09<<0), /* Startup, fetching second data */ - NVMBIST_STATE_RESTART0_gc = (0x0A<<0), /* Re-start from BREAK or FAILED2 */ - NVMBIST_STATE_RESTART1_gc = (0x0B<<0), /* Re-start from FAILED1 */ - NVMBIST_STATE_RUNNING_gc = (0x0C<<0), /* Test running */ - NVMBIST_STATE_FINISH0_gc = (0x0E<<0), /* Check last word */ - NVMBIST_STATE_FINISH1_gc = (0x0F<<0), /* Count faults in last word */ -} NVMBIST_STATE_t; - -/* X address mode select */ -typedef enum NVMBIST_XMODE_enum -{ - NVMBIST_XMODE_STATIC_gc = (0x00<<0), /* X static */ - NVMBIST_XMODE_CARRY_gc = (0x01<<0), /* Carry/borrow from Y */ - NVMBIST_XMODE_INC_gc = (0x02<<0), /* X increment each cycle */ - NVMBIST_XMODE_DEC_gc = (0x03<<0), /* X decrement each cycle */ -} NVMBIST_XMODE_t; - -/* Y address mode select */ -typedef enum NVMBIST_YMODE_enum -{ - NVMBIST_YMODE_STATIC_gc = (0x00<<2), /* Y static */ - NVMBIST_YMODE_CARRY_gc = (0x01<<2), /* Carry/borrow from X */ - NVMBIST_YMODE_INC_gc = (0x02<<2), /* Y increment each cycle */ - NVMBIST_YMODE_DEC_gc = (0x03<<2), /* Y decrement each cycle */ -} NVMBIST_YMODE_t; - -/* --------------------------------------------------------------------------- -NVMCTRL - Non-volatile Memory Controller --------------------------------------------------------------------------- -*/ - -/* Non-volatile Memory Controller */ -typedef struct NVMCTRL_struct -{ - register8_t CTRLA; /* Control A */ - register8_t CTRLB; /* Control B */ - register8_t STATUS; /* Status */ - register8_t INTCTRL; /* Interrupt Control */ - register8_t INTFLAGS; /* Interrupt Flags */ - register8_t reserved_0x05; - _WORDREGISTER(DATA); /* Data */ - _WORDREGISTER(ADDR); /* Address */ - register8_t reserved_0x0A; - register8_t reserved_0x0B; - register8_t reserved_0x0C; - register8_t reserved_0x0D; - register8_t reserved_0x0E; - register8_t reserved_0x0F; -} NVMCTRL_t; - -/* Command select */ -typedef enum NVMCTRL_CMD_enum -{ - NVMCTRL_CMD_NONE_gc = (0x00<<0), /* No Command */ - NVMCTRL_CMD_PAGEWRITE_gc = (0x01<<0), /* Write page */ - NVMCTRL_CMD_PAGEERASE_gc = (0x02<<0), /* Erase page */ - NVMCTRL_CMD_PAGEERASEWRITE_gc = (0x03<<0), /* Erase and write page */ - NVMCTRL_CMD_PAGEBUFCLR_gc = (0x04<<0), /* Page buffer clear */ - NVMCTRL_CMD_CHIPERASE_gc = (0x05<<0), /* Chip erase */ - NVMCTRL_CMD_EEERASE_gc = (0x06<<0), /* EEPROM erase */ - NVMCTRL_CMD_FUSEWRITE_gc = (0x07<<0), /* Write fuse (PDI only) */ -} NVMCTRL_CMD_t; - -/* --------------------------------------------------------------------------- -PORT - I/O Ports --------------------------------------------------------------------------- -*/ - -/* I/O Ports */ -typedef struct PORT_struct -{ - register8_t DIR; /* Data Direction */ - register8_t DIRSET; /* Data Direction Set */ - register8_t DIRCLR; /* Data Direction Clear */ - register8_t DIRTGL; /* Data Direction Toggle */ - register8_t OUT; /* Output Value */ - register8_t OUTSET; /* Output Value Set */ - register8_t OUTCLR; /* Output Value Clear */ - register8_t OUTTGL; /* Output Value Toggle */ - register8_t IN; /* Input Value */ - register8_t INTFLAGS; /* Interrupt Flags */ - register8_t PORTCTRL; /* Port Control */ - register8_t reserved_0x0B; - register8_t reserved_0x0C; - register8_t reserved_0x0D; - register8_t reserved_0x0E; - register8_t reserved_0x0F; - register8_t PIN0CTRL; /* Pin 0 Control */ - register8_t PIN1CTRL; /* Pin 1 Control */ - register8_t PIN2CTRL; /* Pin 2 Control */ - register8_t PIN3CTRL; /* Pin 3 Control */ - register8_t PIN4CTRL; /* Pin 4 Control */ - register8_t PIN5CTRL; /* Pin 5 Control */ - register8_t PIN6CTRL; /* Pin 6 Control */ - register8_t PIN7CTRL; /* Pin 7 Control */ - register8_t reserved_0x18; - register8_t reserved_0x19; - register8_t reserved_0x1A; - register8_t reserved_0x1B; - register8_t reserved_0x1C; - register8_t reserved_0x1D; - register8_t reserved_0x1E; - register8_t reserved_0x1F; -} PORT_t; - -/* Input/Sense Configuration select */ -typedef enum PORT_ISC_enum -{ - PORT_ISC_INTDISABLE_gc = (0x00<<0), /* Interrupt disabled but input buffer enabled */ - PORT_ISC_BOTHEDGES_gc = (0x01<<0), /* Sense Both Edges */ - PORT_ISC_RISING_gc = (0x02<<0), /* Sense Rising Edge */ - PORT_ISC_FALLING_gc = (0x03<<0), /* Sense Falling Edge */ - PORT_ISC_INPUT_DISABLE_gc = (0x04<<0), /* Digital Input Buffer disabled */ - PORT_ISC_LEVEL_gc = (0x05<<0), /* Sense low Level */ -} PORT_ISC_t; - -/* --------------------------------------------------------------------------- -PORTMUX - Port Multiplexer --------------------------------------------------------------------------- -*/ - -/* Port Multiplexer */ -typedef struct PORTMUX_struct -{ - register8_t EVSYSROUTEA; /* Port Multiplexer EVSYS */ - register8_t CCLROUTEA; /* Port Multiplexer CCL */ - register8_t USARTROUTEA; /* Port Multiplexer USART register A */ - register8_t TWISPIROUTEA; /* Port Multiplexer TWI and SPI */ - register8_t TCAROUTEA; /* Port Multiplexer TCA */ - register8_t TCBROUTEA; /* Port Multiplexer TCB */ - register8_t reserved_0x06; - register8_t reserved_0x07; - register8_t reserved_0x08; - register8_t reserved_0x09; - register8_t reserved_0x0A; - register8_t reserved_0x0B; - register8_t reserved_0x0C; - register8_t reserved_0x0D; - register8_t reserved_0x0E; - register8_t reserved_0x0F; -} PORTMUX_t; - -/* Port Multiplexer SPI0 select */ -typedef enum PORTMUX_SPI0_enum -{ - PORTMUX_SPI0_DEFAULT_gc = (0x00<<0), /* SPI0 on PA[7:4] */ - PORTMUX_SPI0_ALT1_gc = (0x01<<0), /* SPI0 on PC[3:0] */ - PORTMUX_SPI0_ALT2_gc = (0x02<<0), /* SPI0 on PE[3:0] */ - PORTMUX_SPI0_NONE_gc = (0x03<<0), /* Not connected to any pins */ -} PORTMUX_SPI0_t; - -/* Port Multiplexer TCA0 select */ -typedef enum PORTMUX_TCA0_enum -{ - PORTMUX_TCA0_PORTA_gc = (0x00<<0), /* TCA0 pins on PA[5:0] */ - PORTMUX_TCA0_PORTB_gc = (0x01<<0), /* TCA0 pins on PB[5:0] */ - PORTMUX_TCA0_PORTC_gc = (0x02<<0), /* TCA0 pins on PC[5:0] */ - PORTMUX_TCA0_PORTD_gc = (0x03<<0), /* TCA0 pins on PD[5:0] */ - PORTMUX_TCA0_PORTE_gc = (0x04<<0), /* TCA0 pins on PE[5:0] */ - PORTMUX_TCA0_PORTF_gc = (0x05<<0), /* TCA0 pins on PF[5:0] */ -} PORTMUX_TCA0_t; - -/* Port Multiplexer TWI0 select */ -typedef enum PORTMUX_TWI0_enum -{ - PORTMUX_TWI0_DEFAULT_gc = (0x00<<4), /* SCL/SDA on PA[3:2], Slave mode on PC[3:2] in dual TWI mode */ - PORTMUX_TWI0_ALT1_gc = (0x01<<4), /* SCL/SDA on PA[3:2], Slave mode on PF[3:2] in dual TWI mode */ - PORTMUX_TWI0_ALT2_gc = (0x02<<4), /* SCL/SDA on PC[3:2], Slave mode on PF[3:2] in dual TWI mode */ - PORTMUX_TWI0_NONE_gc = (0x03<<4), /* Not connected to any pins */ -} PORTMUX_TWI0_t; - -/* Port Multiplexer USART0 select */ -typedef enum PORTMUX_USART0_enum -{ - PORTMUX_USART0_DEFAULT_gc = (0x00<<0), /* USART0 on PA[3:0] */ - PORTMUX_USART0_ALT1_gc = (0x01<<0), /* USART0 on PA[7:4] */ - PORTMUX_USART0_NONE_gc = (0x03<<0), /* Not connected to any pins */ -} PORTMUX_USART0_t; - -/* Port Multiplexer USART1 select */ -typedef enum PORTMUX_USART1_enum -{ - PORTMUX_USART1_DEFAULT_gc = (0x00<<2), /* USART1 on PC[3:0] */ - PORTMUX_USART1_ALT1_gc = (0x01<<2), /* USART1 on PC[7:4] */ - PORTMUX_USART1_NONE_gc = (0x03<<2), /* Not connected to any pins */ -} PORTMUX_USART1_t; - -/* Port Multiplexer USART2 select */ -typedef enum PORTMUX_USART2_enum -{ - PORTMUX_USART2_DEFAULT_gc = (0x00<<4), /* USART2 on PF[3:0] */ - PORTMUX_USART2_ALT1_gc = (0x01<<4), /* USART2 on PF[5:4] */ - PORTMUX_USART2_NONE_gc = (0x03<<4), /* Not connected to any pins */ -} PORTMUX_USART2_t; - -/* Port Multiplexer USART3 select */ -typedef enum PORTMUX_USART3_enum -{ - PORTMUX_USART3_DEFAULT_gc = (0x00<<6), /* USART3 on PB[3:0] */ - PORTMUX_USART3_ALT1_gc = (0x01<<6), /* USART3 on PB[5:4] */ - PORTMUX_USART3_NONE_gc = (0x03<<6), /* Not connected to any pins */ -} PORTMUX_USART3_t; - -/* --------------------------------------------------------------------------- -RSTCTRL - Reset controller --------------------------------------------------------------------------- -*/ - -/* Reset controller */ -typedef struct RSTCTRL_struct -{ - register8_t RSTFR; /* Reset Flags */ - register8_t SWRR; /* Software Reset */ - register8_t reserved_0x02; - register8_t reserved_0x03; -} RSTCTRL_t; - - -/* --------------------------------------------------------------------------- -RTC - Real-Time Counter --------------------------------------------------------------------------- -*/ - -/* Real-Time Counter */ -typedef struct RTC_struct -{ - register8_t CTRLA; /* Control A */ - register8_t STATUS; /* Status */ - register8_t INTCTRL; /* Interrupt Control */ - register8_t INTFLAGS; /* Interrupt Flags */ - register8_t TEMP; /* Temporary */ - register8_t DBGCTRL; /* Debug control */ - register8_t reserved_0x06; - register8_t CLKSEL; /* Clock Select */ - _WORDREGISTER(CNT); /* Counter */ - _WORDREGISTER(PER); /* Period */ - _WORDREGISTER(CMP); /* Compare */ - register8_t reserved_0x0E; - register8_t reserved_0x0F; - register8_t PITCTRLA; /* PIT Control A */ - register8_t PITSTATUS; /* PIT Status */ - register8_t PITINTCTRL; /* PIT Interrupt Control */ - register8_t PITINTFLAGS; /* PIT Interrupt Flags */ - register8_t reserved_0x14; - register8_t PITDBGCTRL; /* PIT Debug control */ - register8_t reserved_0x16; - register8_t reserved_0x17; - register8_t reserved_0x18; - register8_t reserved_0x19; - register8_t reserved_0x1A; - register8_t reserved_0x1B; - register8_t reserved_0x1C; - register8_t reserved_0x1D; - register8_t reserved_0x1E; - register8_t reserved_0x1F; -} RTC_t; - -/* Clock Select select */ -typedef enum RTC_CLKSEL_enum -{ - RTC_CLKSEL_INT32K_gc = (0x00<<0), /* Internal 32kHz OSC */ - RTC_CLKSEL_INT1K_gc = (0x01<<0), /* Internal 1kHz OSC */ - RTC_CLKSEL_TOSC32K_gc = (0x02<<0), /* 32KHz Crystal OSC */ - RTC_CLKSEL_EXTCLK_gc = (0x03<<0), /* External Clock */ -} RTC_CLKSEL_t; - -/* Period select */ -typedef enum RTC_PERIOD_enum -{ - RTC_PERIOD_OFF_gc = (0x00<<3), /* Off */ - RTC_PERIOD_CYC4_gc = (0x01<<3), /* RTC Clock Cycles 4 */ - RTC_PERIOD_CYC8_gc = (0x02<<3), /* RTC Clock Cycles 8 */ - RTC_PERIOD_CYC16_gc = (0x03<<3), /* RTC Clock Cycles 16 */ - RTC_PERIOD_CYC32_gc = (0x04<<3), /* RTC Clock Cycles 32 */ - RTC_PERIOD_CYC64_gc = (0x05<<3), /* RTC Clock Cycles 64 */ - RTC_PERIOD_CYC128_gc = (0x06<<3), /* RTC Clock Cycles 128 */ - RTC_PERIOD_CYC256_gc = (0x07<<3), /* RTC Clock Cycles 256 */ - RTC_PERIOD_CYC512_gc = (0x08<<3), /* RTC Clock Cycles 512 */ - RTC_PERIOD_CYC1024_gc = (0x09<<3), /* RTC Clock Cycles 1024 */ - RTC_PERIOD_CYC2048_gc = (0x0A<<3), /* RTC Clock Cycles 2048 */ - RTC_PERIOD_CYC4096_gc = (0x0B<<3), /* RTC Clock Cycles 4096 */ - RTC_PERIOD_CYC8192_gc = (0x0C<<3), /* RTC Clock Cycles 8192 */ - RTC_PERIOD_CYC16384_gc = (0x0D<<3), /* RTC Clock Cycles 16384 */ - RTC_PERIOD_CYC32768_gc = (0x0E<<3), /* RTC Clock Cycles 32768 */ -} RTC_PERIOD_t; - -/* Prescaling Factor select */ -typedef enum RTC_PRESCALER_enum -{ - RTC_PRESCALER_DIV1_gc = (0x00<<3), /* RTC Clock / 1 */ - RTC_PRESCALER_DIV2_gc = (0x01<<3), /* RTC Clock / 2 */ - RTC_PRESCALER_DIV4_gc = (0x02<<3), /* RTC Clock / 4 */ - RTC_PRESCALER_DIV8_gc = (0x03<<3), /* RTC Clock / 8 */ - RTC_PRESCALER_DIV16_gc = (0x04<<3), /* RTC Clock / 16 */ - RTC_PRESCALER_DIV32_gc = (0x05<<3), /* RTC Clock / 32 */ - RTC_PRESCALER_DIV64_gc = (0x06<<3), /* RTC Clock / 64 */ - RTC_PRESCALER_DIV128_gc = (0x07<<3), /* RTC Clock / 128 */ - RTC_PRESCALER_DIV256_gc = (0x08<<3), /* RTC Clock / 256 */ - RTC_PRESCALER_DIV512_gc = (0x09<<3), /* RTC Clock / 512 */ - RTC_PRESCALER_DIV1024_gc = (0x0A<<3), /* RTC Clock / 1024 */ - RTC_PRESCALER_DIV2048_gc = (0x0B<<3), /* RTC Clock / 2048 */ - RTC_PRESCALER_DIV4096_gc = (0x0C<<3), /* RTC Clock / 4096 */ - RTC_PRESCALER_DIV8192_gc = (0x0D<<3), /* RTC Clock / 8192 */ - RTC_PRESCALER_DIV16384_gc = (0x0E<<3), /* RTC Clock / 16384 */ - RTC_PRESCALER_DIV32768_gc = (0x0F<<3), /* RTC Clock / 32768 */ -} RTC_PRESCALER_t; - -/* --------------------------------------------------------------------------- -SIGROW - Signature row --------------------------------------------------------------------------- -*/ - -/* Signature row */ -typedef struct SIGROW_struct -{ - register8_t DEVICEID0; /* Device ID Byte 0 */ - register8_t DEVICEID1; /* Device ID Byte 1 */ - register8_t DEVICEID2; /* Device ID Byte 2 */ - register8_t SERNUM0; /* Serial Number Byte 0 */ - register8_t SERNUM1; /* Serial Number Byte 1 */ - register8_t SERNUM2; /* Serial Number Byte 2 */ - register8_t SERNUM3; /* Serial Number Byte 3 */ - register8_t SERNUM4; /* Serial Number Byte 4 */ - register8_t SERNUM5; /* Serial Number Byte 5 */ - register8_t SERNUM6; /* Serial Number Byte 6 */ - register8_t SERNUM7; /* Serial Number Byte 7 */ - register8_t SERNUM8; /* Serial Number Byte 8 */ - register8_t SERNUM9; /* Serial Number Byte 9 */ - register8_t reserved_0x0D; - register8_t reserved_0x0E; - register8_t reserved_0x0F; - register8_t reserved_0x10; - register8_t reserved_0x11; - register8_t reserved_0x12; - register8_t reserved_0x13; - register8_t OSCCAL32K; /* Oscillator Calibration for 32kHz ULP */ - register8_t reserved_0x15; - register8_t reserved_0x16; - register8_t reserved_0x17; - register8_t OSCCAL16M0; /* Oscillator Calibration 16 MHz Byte 0 */ - register8_t OSCCAL16M1; /* Oscillator Calibration 16 MHz Byte 1 */ - register8_t OSCCAL20M0; /* Oscillator Calibration 20 MHz Byte 0 */ - register8_t OSCCAL20M1; /* Oscillator Calibration 20 MHz Byte 1 */ - register8_t reserved_0x1C; - register8_t reserved_0x1D; - register8_t reserved_0x1E; - register8_t reserved_0x1F; - register8_t TEMPSENSE0; /* Temperature Sensor Calibration Byte 0 */ - register8_t TEMPSENSE1; /* Temperature Sensor Calibration Byte 1 */ - register8_t OSC16ERR3V; /* OSC16 error at 3V */ - register8_t OSC16ERR5V; /* OSC16 error at 5V */ - register8_t OSC20ERR3V; /* OSC20 error at 3V */ - register8_t OSC20ERR5V; /* OSC20 error at 5V */ - register8_t reserved_0x26; - register8_t reserved_0x27; - register8_t reserved_0x28; - register8_t reserved_0x29; - register8_t reserved_0x2A; - register8_t reserved_0x2B; - register8_t reserved_0x2C; - register8_t reserved_0x2D; - register8_t reserved_0x2E; - register8_t CHECKSUM1; /* CRC Checksum Byte 1 */ - register8_t reserved_0x30; - register8_t reserved_0x31; - register8_t reserved_0x32; - register8_t reserved_0x33; - register8_t reserved_0x34; - register8_t reserved_0x35; - register8_t reserved_0x36; - register8_t reserved_0x37; - register8_t reserved_0x38; - register8_t reserved_0x39; - register8_t reserved_0x3A; - register8_t reserved_0x3B; - register8_t reserved_0x3C; - register8_t reserved_0x3D; - register8_t reserved_0x3E; - register8_t reserved_0x3F; -} SIGROW_t; - - -/* --------------------------------------------------------------------------- -SLPCTRL - Sleep Controller --------------------------------------------------------------------------- -*/ - -/* Sleep Controller */ -typedef struct SLPCTRL_struct -{ - register8_t CTRLA; /* Control */ - register8_t reserved_0x01; -} SLPCTRL_t; - -/* Sleep mode select */ -typedef enum SLPCTRL_SMODE_enum -{ - SLPCTRL_SMODE_IDLE_gc = (0x00<<1), /* Idle mode */ - SLPCTRL_SMODE_STDBY_gc = (0x01<<1), /* Standby Mode */ - SLPCTRL_SMODE_PDOWN_gc = (0x02<<1), /* Power-down Mode */ -} SLPCTRL_SMODE_t; - -#define SLEEP_MODE_IDLE (0x00<<1) -#define SLEEP_MODE_STANDBY (0x01<<1) -#define SLEEP_MODE_PWR_DOWN (0x02<<1) -/* --------------------------------------------------------------------------- -SPI - Serial Peripheral Interface --------------------------------------------------------------------------- -*/ - -/* Serial Peripheral Interface */ -typedef struct SPI_struct -{ - register8_t CTRLA; /* Control A */ - register8_t CTRLB; /* Control B */ - register8_t INTCTRL; /* Interrupt Control */ - register8_t INTFLAGS; /* Interrupt Flags */ - register8_t DATA; /* Data */ - register8_t reserved_0x05; - register8_t reserved_0x06; - register8_t reserved_0x07; -} SPI_t; - -/* SPI Mode select */ -typedef enum SPI_MODE_enum -{ - SPI_MODE_0_gc = (0x00<<0), /* SPI Mode 0 */ - SPI_MODE_1_gc = (0x01<<0), /* SPI Mode 1 */ - SPI_MODE_2_gc = (0x02<<0), /* SPI Mode 2 */ - SPI_MODE_3_gc = (0x03<<0), /* SPI Mode 3 */ -} SPI_MODE_t; - -/* Prescaler select */ -typedef enum SPI_PRESC_enum -{ - SPI_PRESC_DIV4_gc = (0x00<<1), /* System Clock / 4 */ - SPI_PRESC_DIV16_gc = (0x01<<1), /* System Clock / 16 */ - SPI_PRESC_DIV64_gc = (0x02<<1), /* System Clock / 64 */ - SPI_PRESC_DIV128_gc = (0x03<<1), /* System Clock / 128 */ -} SPI_PRESC_t; - -/* --------------------------------------------------------------------------- -SYSCFG - System Configuration Registers --------------------------------------------------------------------------- -*/ - -/* System Configuration Registers */ -typedef struct SYSCFG_struct -{ - register8_t reserved_0x00; - register8_t REVID; /* Revision ID */ - register8_t EXTBRK; /* External Break */ - register8_t reserved_0x03; - register8_t reserved_0x04; - register8_t reserved_0x05; - register8_t reserved_0x06; - register8_t reserved_0x07; - register8_t reserved_0x08; - register8_t reserved_0x09; - register8_t reserved_0x0A; - register8_t reserved_0x0B; - register8_t reserved_0x0C; - register8_t reserved_0x0D; - register8_t reserved_0x0E; - register8_t reserved_0x0F; - register8_t reserved_0x10; - register8_t reserved_0x11; - register8_t reserved_0x12; - register8_t reserved_0x13; - register8_t reserved_0x14; - register8_t reserved_0x15; - register8_t reserved_0x16; - register8_t reserved_0x17; - register8_t OCDM; /* OCD Message Register */ - register8_t OCDMS; /* OCD Message Status */ - register8_t reserved_0x1A; - register8_t reserved_0x1B; - register8_t reserved_0x1C; - register8_t reserved_0x1D; - register8_t reserved_0x1E; - register8_t reserved_0x1F; -} SYSCFG_t; - - -/* --------------------------------------------------------------------------- -TCA - 16-bit Timer/Counter Type A --------------------------------------------------------------------------- -*/ - -/* 16-bit Timer/Counter Type A - Single Mode */ -typedef struct TCA_SINGLE_struct -{ - register8_t CTRLA; /* Control A */ - register8_t CTRLB; /* Control B */ - register8_t CTRLC; /* Control C */ - register8_t CTRLD; /* Control D */ - register8_t CTRLECLR; /* Control E Clear */ - register8_t CTRLESET; /* Control E Set */ - register8_t CTRLFCLR; /* Control F Clear */ - register8_t CTRLFSET; /* Control F Set */ - register8_t reserved_0x08; - register8_t EVCTRL; /* Event Control */ - register8_t INTCTRL; /* Interrupt Control */ - register8_t INTFLAGS; /* Interrupt Flags */ - register8_t reserved_0x0C; - register8_t reserved_0x0D; - register8_t DBGCTRL; /* Degbug Control */ - register8_t TEMP; /* Temporary data for 16-bit Access */ - register8_t reserved_0x10; - register8_t reserved_0x11; - register8_t reserved_0x12; - register8_t reserved_0x13; - register8_t reserved_0x14; - register8_t reserved_0x15; - register8_t reserved_0x16; - register8_t reserved_0x17; - register8_t reserved_0x18; - register8_t reserved_0x19; - register8_t reserved_0x1A; - register8_t reserved_0x1B; - register8_t reserved_0x1C; - register8_t reserved_0x1D; - register8_t reserved_0x1E; - register8_t reserved_0x1F; - _WORDREGISTER(CNT); /* Count */ - register8_t reserved_0x22; - register8_t reserved_0x23; - register8_t reserved_0x24; - register8_t reserved_0x25; - _WORDREGISTER(PER); /* Period */ - _WORDREGISTER(CMP0); /* Compare 0 */ - _WORDREGISTER(CMP1); /* Compare 1 */ - _WORDREGISTER(CMP2); /* Compare 2 */ - register8_t reserved_0x2E; - register8_t reserved_0x2F; - register8_t reserved_0x30; - register8_t reserved_0x31; - register8_t reserved_0x32; - register8_t reserved_0x33; - register8_t reserved_0x34; - register8_t reserved_0x35; - _WORDREGISTER(PERBUF); /* Period Buffer */ - _WORDREGISTER(CMP0BUF); /* Compare 0 Buffer */ - _WORDREGISTER(CMP1BUF); /* Compare 1 Buffer */ - _WORDREGISTER(CMP2BUF); /* Compare 2 Buffer */ - register8_t reserved_0x3E; - register8_t reserved_0x3F; -} TCA_SINGLE_t; - - -/* 16-bit Timer/Counter Type A - Split Mode */ -typedef struct TCA_SPLIT_struct -{ - register8_t CTRLA; /* Control A */ - register8_t CTRLB; /* Control B */ - register8_t CTRLC; /* Control C */ - register8_t CTRLD; /* Control D */ - register8_t CTRLECLR; /* Control E Clear */ - register8_t CTRLESET; /* Control E Set */ - register8_t reserved_0x06; - register8_t reserved_0x07; - register8_t reserved_0x08; - register8_t reserved_0x09; - register8_t INTCTRL; /* Interrupt Control */ - register8_t INTFLAGS; /* Interrupt Flags */ - register8_t reserved_0x0C; - register8_t reserved_0x0D; - register8_t DBGCTRL; /* Degbug Control */ - register8_t reserved_0x0F; - register8_t reserved_0x10; - register8_t reserved_0x11; - register8_t reserved_0x12; - register8_t reserved_0x13; - register8_t reserved_0x14; - register8_t reserved_0x15; - register8_t reserved_0x16; - register8_t reserved_0x17; - register8_t reserved_0x18; - register8_t reserved_0x19; - register8_t reserved_0x1A; - register8_t reserved_0x1B; - register8_t reserved_0x1C; - register8_t reserved_0x1D; - register8_t reserved_0x1E; - register8_t reserved_0x1F; - register8_t LCNT; /* Low Count */ - register8_t HCNT; /* High Count */ - register8_t reserved_0x22; - register8_t reserved_0x23; - register8_t reserved_0x24; - register8_t reserved_0x25; - register8_t LPER; /* Low Period */ - register8_t HPER; /* High Period */ - register8_t LCMP0; /* Low Compare */ - register8_t HCMP0; /* High Compare */ - register8_t LCMP1; /* Low Compare */ - register8_t HCMP1; /* High Compare */ - register8_t LCMP2; /* Low Compare */ - register8_t HCMP2; /* High Compare */ - register8_t reserved_0x2E; - register8_t reserved_0x2F; - register8_t reserved_0x30; - register8_t reserved_0x31; - register8_t reserved_0x32; - register8_t reserved_0x33; - register8_t reserved_0x34; - register8_t reserved_0x35; - register8_t reserved_0x36; - register8_t reserved_0x37; - register8_t reserved_0x38; - register8_t reserved_0x39; - register8_t reserved_0x3A; - register8_t reserved_0x3B; - register8_t reserved_0x3C; - register8_t reserved_0x3D; - register8_t reserved_0x3E; - register8_t reserved_0x3F; -} TCA_SPLIT_t; - - -/* 16-bit Timer/Counter Type A */ -typedef union TCA_union -{ - TCA_SINGLE_t SINGLE; /* 16-bit Timer/Counter Type A - Single Mode */ - TCA_SPLIT_t SPLIT; /* 16-bit Timer/Counter Type A - Split Mode */ -} TCA_t; - -/* Clock Selection select */ -typedef enum TCA_SINGLE_CLKSEL_enum -{ - TCA_SINGLE_CLKSEL_DIV1_gc = (0x00<<1), /* System Clock */ - TCA_SINGLE_CLKSEL_DIV2_gc = (0x01<<1), /* System Clock / 2 */ - TCA_SINGLE_CLKSEL_DIV4_gc = (0x02<<1), /* System Clock / 4 */ - TCA_SINGLE_CLKSEL_DIV8_gc = (0x03<<1), /* System Clock / 8 */ - TCA_SINGLE_CLKSEL_DIV16_gc = (0x04<<1), /* System Clock / 16 */ - TCA_SINGLE_CLKSEL_DIV64_gc = (0x05<<1), /* System Clock / 64 */ - TCA_SINGLE_CLKSEL_DIV256_gc = (0x06<<1), /* System Clock / 256 */ - TCA_SINGLE_CLKSEL_DIV1024_gc = (0x07<<1), /* System Clock / 1024 */ -} TCA_SINGLE_CLKSEL_t; - -/* Command select */ -typedef enum TCA_SINGLE_CMD_enum -{ - TCA_SINGLE_CMD_NONE_gc = (0x00<<2), /* No Command */ - TCA_SINGLE_CMD_UPDATE_gc = (0x01<<2), /* Force Update */ - TCA_SINGLE_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ - TCA_SINGLE_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ -} TCA_SINGLE_CMD_t; - -/* Direction select */ -typedef enum TCA_SINGLE_DIR_enum -{ - TCA_SINGLE_DIR_UP_gc = (0x00<<0), /* Count up */ - TCA_SINGLE_DIR_DOWN_gc = (0x01<<0), /* Count down */ -} TCA_SINGLE_DIR_t; - -/* Event Action select */ -typedef enum TCA_SINGLE_EVACT_enum -{ - TCA_SINGLE_EVACT_POSEDGE_gc = (0x00<<1), /* Count on positive edge event */ - TCA_SINGLE_EVACT_ANYEDGE_gc = (0x01<<1), /* Count on any edge event */ - TCA_SINGLE_EVACT_HIGHLVL_gc = (0x02<<1), /* Count on prescaled clock while event line is 1. */ - TCA_SINGLE_EVACT_UPDOWN_gc = (0x03<<1), /* Count on prescaled clock. Event controls count direction. Up-count when event line is 0, down-count when event line is 1. */ -} TCA_SINGLE_EVACT_t; - -/* Waveform generation mode select */ -typedef enum TCA_SINGLE_WGMODE_enum -{ - TCA_SINGLE_WGMODE_NORMAL_gc = (0x00<<0), /* Normal Mode */ - TCA_SINGLE_WGMODE_FRQ_gc = (0x01<<0), /* Frequency Generation Mode */ - TCA_SINGLE_WGMODE_SINGLESLOPE_gc = (0x03<<0), /* Single Slope PWM */ - TCA_SINGLE_WGMODE_DSTOP_gc = (0x05<<0), /* Dual Slope PWM, overflow on TOP */ - TCA_SINGLE_WGMODE_DSBOTH_gc = (0x06<<0), /* Dual Slope PWM, overflow on TOP and BOTTOM */ - TCA_SINGLE_WGMODE_DSBOTTOM_gc = (0x07<<0), /* Dual Slope PWM, overflow on BOTTOM */ -} TCA_SINGLE_WGMODE_t; - -/* Clock Selection select */ -typedef enum TCA_SPLIT_CLKSEL_enum -{ - TCA_SPLIT_CLKSEL_DIV1_gc = (0x00<<1), /* System Clock */ - TCA_SPLIT_CLKSEL_DIV2_gc = (0x01<<1), /* System Clock / 2 */ - TCA_SPLIT_CLKSEL_DIV4_gc = (0x02<<1), /* System Clock / 4 */ - TCA_SPLIT_CLKSEL_DIV8_gc = (0x03<<1), /* System Clock / 8 */ - TCA_SPLIT_CLKSEL_DIV16_gc = (0x04<<1), /* System Clock / 16 */ - TCA_SPLIT_CLKSEL_DIV64_gc = (0x05<<1), /* System Clock / 64 */ - TCA_SPLIT_CLKSEL_DIV256_gc = (0x06<<1), /* System Clock / 256 */ - TCA_SPLIT_CLKSEL_DIV1024_gc = (0x07<<1), /* System Clock / 1024 */ -} TCA_SPLIT_CLKSEL_t; - -/* Command select */ -typedef enum TCA_SPLIT_CMD_enum -{ - TCA_SPLIT_CMD_NONE_gc = (0x00<<2), /* No Command */ - TCA_SPLIT_CMD_UPDATE_gc = (0x01<<2), /* Force Update */ - TCA_SPLIT_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ - TCA_SPLIT_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ -} TCA_SPLIT_CMD_t; - -/* --------------------------------------------------------------------------- -TCB - 16-bit Timer Type B --------------------------------------------------------------------------- -*/ - -/* 16-bit Timer Type B */ -typedef struct TCB_struct -{ - register8_t CTRLA; /* Control A */ - register8_t CTRLB; /* Control Register B */ - register8_t reserved_0x02; - register8_t reserved_0x03; - register8_t EVCTRL; /* Event Control */ - register8_t INTCTRL; /* Interrupt Control */ - register8_t INTFLAGS; /* Interrupt Flags */ - register8_t STATUS; /* Status */ - register8_t DBGCTRL; /* Debug Control */ - register8_t TEMP; /* Temporary Value */ - _WORDREGISTER(CNT); /* Count */ - _WORDREGISTER(CCMP); /* Compare or Capture */ - register8_t reserved_0x0E; - register8_t reserved_0x0F; -} TCB_t; - -/* Clock Select select */ -typedef enum TCB_CLKSEL_enum -{ - TCB_CLKSEL_CLKDIV1_gc = (0x00<<1), /* CLK_PER (No Prescaling) */ - TCB_CLKSEL_CLKDIV2_gc = (0x01<<1), /* CLK_PER/2 (From Prescaler) */ - TCB_CLKSEL_CLKTCA_gc = (0x02<<1), /* Use Clock from TCA */ -} TCB_CLKSEL_t; - -/* Timer Mode select */ -typedef enum TCB_CNTMODE_enum -{ - TCB_CNTMODE_INT_gc = (0x00<<0), /* Periodic Interrupt */ - TCB_CNTMODE_TIMEOUT_gc = (0x01<<0), /* Periodic Timeout */ - TCB_CNTMODE_CAPT_gc = (0x02<<0), /* Input Capture Event */ - TCB_CNTMODE_FRQ_gc = (0x03<<0), /* Input Capture Frequency measurement */ - TCB_CNTMODE_PW_gc = (0x04<<0), /* Input Capture Pulse-Width measurement */ - TCB_CNTMODE_FRQPW_gc = (0x05<<0), /* Input Capture Frequency and Pulse-Width measurement */ - TCB_CNTMODE_SINGLE_gc = (0x06<<0), /* Single Shot */ - TCB_CNTMODE_PWM8_gc = (0x07<<0), /* 8-bit PWM */ -} TCB_CNTMODE_t; - -/* --------------------------------------------------------------------------- -TWI - Two-Wire Interface --------------------------------------------------------------------------- -*/ - -/* Two-Wire Interface */ -typedef struct TWI_struct -{ - register8_t CTRLA; /* Control A */ - register8_t BRIDGECTRL; /* Bridge Control */ - register8_t DBGCTRL; /* Debug Control Register */ - register8_t MCTRLA; /* Master Control A */ - register8_t MCTRLB; /* Master Control B */ - register8_t MSTATUS; /* Master Status */ - register8_t MBAUD; /* Master Baurd Rate Control */ - register8_t MADDR; /* Master Address */ - register8_t MDATA; /* Master Data */ - register8_t SCTRLA; /* Slave Control A */ - register8_t SCTRLB; /* Slave Control B */ - register8_t SSTATUS; /* Slave Status */ - register8_t SADDR; /* Slave Address */ - register8_t SDATA; /* Slave Data */ - register8_t SADDRMASK; /* Slave Address Mask */ - register8_t reserved_0x0F; -} TWI_t; - -/* Acknowledge Action select */ -typedef enum TWI_ACKACT_enum -{ - TWI_ACKACT_ACK_gc = (0x00<<2), /* Send ACK */ - TWI_ACKACT_NACK_gc = (0x01<<2), /* Send NACK */ -} TWI_ACKACT_t; - -/* Slave Address or Stop select */ -typedef enum TWI_AP_enum -{ - TWI_AP_STOP_gc = (0x00<<0), /* Stop condition generated APIF */ - TWI_AP_ADR_gc = (0x01<<0), /* Address detection generated APIF */ -} TWI_AP_t; - -/* Bus State select */ -typedef enum TWI_BUSSTATE_enum -{ - TWI_BUSSTATE_UNKNOWN_gc = (0x00<<0), /* Unknown Bus State */ - TWI_BUSSTATE_IDLE_gc = (0x01<<0), /* Bus is Idle */ - TWI_BUSSTATE_OWNER_gc = (0x02<<0), /* This Module Controls The Bus */ - TWI_BUSSTATE_BUSY_gc = (0x03<<0), /* The Bus is Busy */ -} TWI_BUSSTATE_t; - -/* Command select */ -typedef enum TWI_MCMD_enum -{ - TWI_MCMD_NOACT_gc = (0x00<<0), /* No Action */ - TWI_MCMD_REPSTART_gc = (0x01<<0), /* Issue Repeated Start Condition */ - TWI_MCMD_RECVTRANS_gc = (0x02<<0), /* Receive or Transmit Data, depending on DIR */ - TWI_MCMD_STOP_gc = (0x03<<0), /* Issue Stop Condition */ -} TWI_MCMD_t; - -/* Command select */ -typedef enum TWI_SCMD_enum -{ - TWI_SCMD_NOACT_gc = (0x00<<0), /* No Action */ - TWI_SCMD_COMPTRANS_gc = (0x02<<0), /* Used To Complete a Transaction */ - TWI_SCMD_RESPONSE_gc = (0x03<<0), /* Used in Response to Address/Data Interrupt */ -} TWI_SCMD_t; - -/* SDA Hold Time select */ -typedef enum TWI_SDAHOLD_enum -{ - TWI_SDAHOLD_OFF_gc = (0x00<<2), /* SDA hold time off */ - TWI_SDAHOLD_50NS_gc = (0x01<<2), /* Typical 50ns hold time */ - TWI_SDAHOLD_300NS_gc = (0x02<<2), /* Typical 300ns hold time */ - TWI_SDAHOLD_500NS_gc = (0x03<<2), /* Typical 500ns hold time */ -} TWI_SDAHOLD_t; - -/* SDA Setup Time select */ -typedef enum TWI_SDASETUP_enum -{ - TWI_SDASETUP_4CYC_gc = (0x00<<4), /* SDA setup time is 4 clock cycles */ - TWI_SDASETUP_8CYC_gc = (0x01<<4), /* SDA setup time is 8 clock cycles */ -} TWI_SDASETUP_t; - -/* Inactive Bus Timeout select */ -typedef enum TWI_TIMEOUT_enum -{ - TWI_TIMEOUT_DISABLED_gc = (0x00<<2), /* Bus Timeout Disabled */ - TWI_TIMEOUT_50US_gc = (0x01<<2), /* 50 Microseconds */ - TWI_TIMEOUT_100US_gc = (0x02<<2), /* 100 Microseconds */ - TWI_TIMEOUT_200US_gc = (0x03<<2), /* 200 Microseconds */ -} TWI_TIMEOUT_t; - -/* --------------------------------------------------------------------------- -USART - Universal Synchronous and Asynchronous Receiver and Transmitter --------------------------------------------------------------------------- -*/ - -/* Universal Synchronous and Asynchronous Receiver and Transmitter */ -typedef struct USART_struct -{ - register8_t RXDATAL; /* Receive Data Low Byte */ - register8_t RXDATAH; /* Receive Data High Byte */ - register8_t TXDATAL; /* Transmit Data Low Byte */ - register8_t TXDATAH; /* Transmit Data High Byte */ - register8_t STATUS; /* Status */ - register8_t CTRLA; /* Control A */ - register8_t CTRLB; /* Control B */ - register8_t CTRLC; /* Control C */ - _WORDREGISTER(BAUD); /* Baud Rate */ - register8_t CTRLD; /* Control D */ - register8_t DBGCTRL; /* Debug Control */ - register8_t EVCTRL; /* Event Control */ - register8_t TXPLCTRL; /* IRCOM Transmitter Pulse Length Control */ - register8_t RXPLCTRL; /* IRCOM Receiver Pulse Length Control */ - register8_t reserved_0x0F; -} USART_t; - -/* Character Size select */ -typedef enum USART_CHSIZE_enum -{ - USART_CHSIZE_5BIT_gc = (0x00<<0), /* Character size: 5 bit */ - USART_CHSIZE_6BIT_gc = (0x01<<0), /* Character size: 6 bit */ - USART_CHSIZE_7BIT_gc = (0x02<<0), /* Character size: 7 bit */ - USART_CHSIZE_8BIT_gc = (0x03<<0), /* Character size: 8 bit */ - USART_CHSIZE_9BITL_gc = (0x06<<0), /* Character size: 9 bit read low byte first */ - USART_CHSIZE_9BITH_gc = (0x07<<0), /* Character size: 9 bit read high byte first */ -} USART_CHSIZE_t; - -/* Communication Mode select */ -typedef enum USART_CMODE_enum -{ - USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6), /* Asynchronous Mode */ - USART_CMODE_SYNCHRONOUS_gc = (0x01<<6), /* Synchronous Mode */ - USART_CMODE_IRCOM_gc = (0x02<<6), /* Infrared Communication */ - USART_CMODE_MSPI_gc = (0x03<<6), /* Master SPI Mode */ -} USART_CMODE_t; - -/* Parity Mode select */ -typedef enum USART_PMODE_enum -{ - USART_PMODE_DISABLED_gc = (0x00<<4), /* No Parity */ - USART_PMODE_EVEN_gc = (0x02<<4), /* Even Parity */ - USART_PMODE_ODD_gc = (0x03<<4), /* Odd Parity */ -} USART_PMODE_t; - -/* RS485 Mode internal transmitter select */ -typedef enum USART_RS485_enum -{ - USART_RS485_OFF_gc = (0x00<<0), /* RS485 Mode disabled */ - USART_RS485_EXT_gc = (0x01<<0), /* RS485 Mode External drive */ - USART_RS485_INT_gc = (0x02<<0), /* RS485 Mode Internal drive */ -} USART_RS485_t; - -/* Receiver Mode select */ -typedef enum USART_RXMODE_enum -{ - USART_RXMODE_NORMAL_gc = (0x00<<1), /* Normal mode */ - USART_RXMODE_CLK2X_gc = (0x01<<1), /* CLK2x mode */ - USART_RXMODE_GENAUTO_gc = (0x02<<1), /* Generic autobaud mode */ - USART_RXMODE_LINAUTO_gc = (0x03<<1), /* LIN constrained autobaud mode */ -} USART_RXMODE_t; - -/* Stop Bit Mode select */ -typedef enum USART_SBMODE_enum -{ - USART_SBMODE_1BIT_gc = (0x00<<3), /* 1 stop bit */ - USART_SBMODE_2BIT_gc = (0x01<<3), /* 2 stop bits */ -} USART_SBMODE_t; - -/* --------------------------------------------------------------------------- -USERROW - User Row --------------------------------------------------------------------------- -*/ - -/* User Row */ -typedef struct USERROW_struct -{ - register8_t USERROW0; /* User Row Byte 0 */ - register8_t USERROW1; /* User Row Byte 1 */ - register8_t USERROW2; /* User Row Byte 2 */ - register8_t USERROW3; /* User Row Byte 3 */ - register8_t USERROW4; /* User Row Byte 4 */ - register8_t USERROW5; /* User Row Byte 5 */ - register8_t USERROW6; /* User Row Byte 6 */ - register8_t USERROW7; /* User Row Byte 7 */ - register8_t USERROW8; /* User Row Byte 8 */ - register8_t USERROW9; /* User Row Byte 9 */ - register8_t USERROW10; /* User Row Byte 10 */ - register8_t USERROW11; /* User Row Byte 11 */ - register8_t USERROW12; /* User Row Byte 12 */ - register8_t USERROW13; /* User Row Byte 13 */ - register8_t USERROW14; /* User Row Byte 14 */ - register8_t USERROW15; /* User Row Byte 15 */ - register8_t USERROW16; /* User Row Byte 16 */ - register8_t USERROW17; /* User Row Byte 17 */ - register8_t USERROW18; /* User Row Byte 18 */ - register8_t USERROW19; /* User Row Byte 19 */ - register8_t USERROW20; /* User Row Byte 20 */ - register8_t USERROW21; /* User Row Byte 21 */ - register8_t USERROW22; /* User Row Byte 22 */ - register8_t USERROW23; /* User Row Byte 23 */ - register8_t USERROW24; /* User Row Byte 24 */ - register8_t USERROW25; /* User Row Byte 25 */ - register8_t USERROW26; /* User Row Byte 26 */ - register8_t USERROW27; /* User Row Byte 27 */ - register8_t USERROW28; /* User Row Byte 28 */ - register8_t USERROW29; /* User Row Byte 29 */ - register8_t USERROW30; /* User Row Byte 30 */ - register8_t USERROW31; /* User Row Byte 31 */ - register8_t USERROW32; /* User Row Byte 32 */ - register8_t USERROW33; /* User Row Byte 33 */ - register8_t USERROW34; /* User Row Byte 34 */ - register8_t USERROW35; /* User Row Byte 35 */ - register8_t USERROW36; /* User Row Byte 36 */ - register8_t USERROW37; /* User Row Byte 37 */ - register8_t USERROW38; /* User Row Byte 38 */ - register8_t USERROW39; /* User Row Byte 39 */ - register8_t USERROW40; /* User Row Byte 40 */ - register8_t USERROW41; /* User Row Byte 41 */ - register8_t USERROW42; /* User Row Byte 42 */ - register8_t USERROW43; /* User Row Byte 43 */ - register8_t USERROW44; /* User Row Byte 44 */ - register8_t USERROW45; /* User Row Byte 45 */ - register8_t USERROW46; /* User Row Byte 46 */ - register8_t USERROW47; /* User Row Byte 47 */ - register8_t USERROW48; /* User Row Byte 48 */ - register8_t USERROW49; /* User Row Byte 49 */ - register8_t USERROW50; /* User Row Byte 50 */ - register8_t USERROW51; /* User Row Byte 51 */ - register8_t USERROW52; /* User Row Byte 52 */ - register8_t USERROW53; /* User Row Byte 53 */ - register8_t USERROW54; /* User Row Byte 54 */ - register8_t USERROW55; /* User Row Byte 55 */ - register8_t USERROW56; /* User Row Byte 56 */ - register8_t USERROW57; /* User Row Byte 57 */ - register8_t USERROW58; /* User Row Byte 58 */ - register8_t USERROW59; /* User Row Byte 59 */ - register8_t USERROW60; /* User Row Byte 60 */ - register8_t USERROW61; /* User Row Byte 61 */ - register8_t USERROW62; /* User Row Byte 62 */ - register8_t USERROW63; /* User Row Byte 63 */ -} USERROW_t; - - -/* --------------------------------------------------------------------------- -VPORT - Virtual Ports --------------------------------------------------------------------------- -*/ - -/* Virtual Ports */ -typedef struct VPORT_struct -{ - register8_t DIR; /* Data Direction */ - register8_t OUT; /* Output Value */ - register8_t IN; /* Input Value */ - register8_t INTFLAGS; /* Interrupt Flags */ -} VPORT_t; - - -/* --------------------------------------------------------------------------- -VREF - Voltage reference --------------------------------------------------------------------------- -*/ - -/* Voltage reference */ -typedef struct VREF_struct -{ - register8_t CTRLA; /* Control A */ - register8_t CTRLB; /* Control B */ -} VREF_t; - -/* AC0 reference select select */ -typedef enum VREF_AC0REFSEL_enum -{ - VREF_AC0REFSEL_0V55_gc = (0x00<<0), /* Voltage reference at 0.55V */ - VREF_AC0REFSEL_1V1_gc = (0x01<<0), /* Voltage reference at 1.1V */ - VREF_AC0REFSEL_2V5_gc = (0x02<<0), /* Voltage reference at 2.5V */ - VREF_AC0REFSEL_4V34_gc = (0x03<<0), /* Voltage reference at 4.34V */ - VREF_AC0REFSEL_1V5_gc = (0x04<<0), /* Voltage reference at 1.5V */ -} VREF_AC0REFSEL_t; - -/* ADC0 reference select select */ -typedef enum VREF_ADC0REFSEL_enum -{ - VREF_ADC0REFSEL_0V55_gc = (0x00<<4), /* Voltage reference at 0.55V */ - VREF_ADC0REFSEL_1V1_gc = (0x01<<4), /* Voltage reference at 1.1V */ - VREF_ADC0REFSEL_2V5_gc = (0x02<<4), /* Voltage reference at 2.5V */ - VREF_ADC0REFSEL_4V34_gc = (0x03<<4), /* Voltage reference at 4.34V */ - VREF_ADC0REFSEL_1V5_gc = (0x04<<4), /* Voltage reference at 1.5V */ -} VREF_ADC0REFSEL_t; - -/* --------------------------------------------------------------------------- -WDT - Watch-Dog Timer --------------------------------------------------------------------------- -*/ - -/* Watch-Dog Timer */ -typedef struct WDT_struct -{ - register8_t CTRLA; /* Control A */ - register8_t STATUS; /* Status */ -} WDT_t; - -/* Period select */ -typedef enum WDT_PERIOD_enum -{ - WDT_PERIOD_OFF_gc = (0x00<<0), /* Off */ - WDT_PERIOD_8CLK_gc = (0x01<<0), /* 8 cycles (8ms) */ - WDT_PERIOD_16CLK_gc = (0x02<<0), /* 16 cycles (16ms) */ - WDT_PERIOD_32CLK_gc = (0x03<<0), /* 32 cycles (32ms) */ - WDT_PERIOD_64CLK_gc = (0x04<<0), /* 64 cycles (64ms) */ - WDT_PERIOD_128CLK_gc = (0x05<<0), /* 128 cycles (0.128s) */ - WDT_PERIOD_256CLK_gc = (0x06<<0), /* 256 cycles (0.256s) */ - WDT_PERIOD_512CLK_gc = (0x07<<0), /* 512 cycles (0.512s) */ - WDT_PERIOD_1KCLK_gc = (0x08<<0), /* 1K cycles (1.0s) */ - WDT_PERIOD_2KCLK_gc = (0x09<<0), /* 2K cycles (2.0s) */ - WDT_PERIOD_4KCLK_gc = (0x0A<<0), /* 4K cycles (4.1s) */ - WDT_PERIOD_8KCLK_gc = (0x0B<<0), /* 8K cycles (8.2s) */ -} WDT_PERIOD_t; - -/* Window select */ -typedef enum WDT_WINDOW_enum -{ - WDT_WINDOW_OFF_gc = (0x00<<4), /* Off */ - WDT_WINDOW_8CLK_gc = (0x01<<4), /* 8 cycles (8ms) */ - WDT_WINDOW_16CLK_gc = (0x02<<4), /* 16 cycles (16ms) */ - WDT_WINDOW_32CLK_gc = (0x03<<4), /* 32 cycles (32ms) */ - WDT_WINDOW_64CLK_gc = (0x04<<4), /* 64 cycles (64ms) */ - WDT_WINDOW_128CLK_gc = (0x05<<4), /* 128 cycles (0.128s) */ - WDT_WINDOW_256CLK_gc = (0x06<<4), /* 256 cycles (0.256s) */ - WDT_WINDOW_512CLK_gc = (0x07<<4), /* 512 cycles (0.512s) */ - WDT_WINDOW_1KCLK_gc = (0x08<<4), /* 1K cycles (1.0s) */ - WDT_WINDOW_2KCLK_gc = (0x09<<4), /* 2K cycles (2.0s) */ - WDT_WINDOW_4KCLK_gc = (0x0A<<4), /* 4K cycles (4.1s) */ - WDT_WINDOW_8KCLK_gc = (0x0B<<4), /* 8K cycles (8.2s) */ -} WDT_WINDOW_t; -/* -========================================================================== -IO Module Instances. Mapped to memory. -========================================================================== -*/ - -#define VPORTA (*(VPORT_t *) 0x0000) /* Virtual Ports */ -#define VPORTB (*(VPORT_t *) 0x0004) /* Virtual Ports */ -#define VPORTC (*(VPORT_t *) 0x0008) /* Virtual Ports */ -#define VPORTD (*(VPORT_t *) 0x000C) /* Virtual Ports */ -#define VPORTE (*(VPORT_t *) 0x0010) /* Virtual Ports */ -#define VPORTF (*(VPORT_t *) 0x0014) /* Virtual Ports */ -#define RSTCTRL (*(RSTCTRL_t *) 0x0040) /* Reset controller */ -#define SLPCTRL (*(SLPCTRL_t *) 0x0050) /* Sleep Controller */ -#define CLKCTRL (*(CLKCTRL_t *) 0x0060) /* Clock controller */ -#define BOD (*(BOD_t *) 0x0080) /* Bod interface */ -#define VREF (*(VREF_t *) 0x00A0) /* Voltage reference */ -#define NVMBIST (*(NVMBIST_t *) 0x00C0) /* BIST in the NVMCTRL module */ -#define WDT (*(WDT_t *) 0x0100) /* Watch-Dog Timer */ -#define CPUINT (*(CPUINT_t *) 0x0110) /* Interrupt Controller */ -#define CRCSCAN (*(CRCSCAN_t *) 0x0120) /* CRCSCAN */ -#define RTC (*(RTC_t *) 0x0140) /* Real-Time Counter */ -#define EVSYS (*(EVSYS_t *) 0x0180) /* Event System */ -#define CCL (*(CCL_t *) 0x01C0) /* Configurable Custom Logic */ -#define PORTA (*(PORT_t *) 0x0400) /* I/O Ports */ -#define PORTB (*(PORT_t *) 0x0420) /* I/O Ports */ -#define PORTC (*(PORT_t *) 0x0440) /* I/O Ports */ -#define PORTD (*(PORT_t *) 0x0460) /* I/O Ports */ -#define PORTE (*(PORT_t *) 0x0480) /* I/O Ports */ -#define PORTF (*(PORT_t *) 0x04A0) /* I/O Ports */ -#define PORTMUX (*(PORTMUX_t *) 0x05E0) /* Port Multiplexer */ -#define ADC0 (*(ADC_t *) 0x0600) /* Analog to Digital Converter */ -#define AC0 (*(AC_t *) 0x0680) /* Analog Comparator */ -#define USART0 (*(USART_t *) 0x0800) /* Universal Synchronous and Asynchronous Receiver and Transmitter */ -#define USART1 (*(USART_t *) 0x0820) /* Universal Synchronous and Asynchronous Receiver and Transmitter */ -#define TWI0 (*(TWI_t *) 0x08A0) /* Two-Wire Interface */ -#define SPI0 (*(SPI_t *) 0x08C0) /* Serial Peripheral Interface */ -#define TCA0 (*(TCA_t *) 0x0A00) /* 16-bit Timer/Counter Type A */ -#define TCB0 (*(TCB_t *) 0x0A80) /* 16-bit Timer Type B */ -#define TCB1 (*(TCB_t *) 0x0A90) /* 16-bit Timer Type B */ -#define TCB2 (*(TCB_t *) 0x0AA0) /* 16-bit Timer Type B */ -#define SYSCFG (*(SYSCFG_t *) 0x0F00) /* System Configuration Registers */ -#define NVMCTRL (*(NVMCTRL_t *) 0x1000) /* Non-volatile Memory Controller */ -#define SIGROW (*(SIGROW_t *) 0x1100) /* Signature row */ -#define FUSE (*(FUSE_t *) 0x1280) /* Fuses */ -#define LOCKBIT (*(LOCKBIT_t *) 0x128A) /* Lockbit */ -#define USERROW (*(USERROW_t *) 0x1300) /* User Row */ - -#endif /* !defined (__ASSEMBLER__) */ - - -/* ========== Flattened fully qualified IO register names ========== */ - - -/* VPORT (VPORTA) - Virtual Ports */ -#define VPORTA_DIR _SFR_MEM8(0x0000) -#define VPORTA_OUT _SFR_MEM8(0x0001) -#define VPORTA_IN _SFR_MEM8(0x0002) -#define VPORTA_INTFLAGS _SFR_MEM8(0x0003) - - -/* VPORT (VPORTB) - Virtual Ports */ -#define VPORTB_DIR _SFR_MEM8(0x0004) -#define VPORTB_OUT _SFR_MEM8(0x0005) -#define VPORTB_IN _SFR_MEM8(0x0006) -#define VPORTB_INTFLAGS _SFR_MEM8(0x0007) - - -/* VPORT (VPORTC) - Virtual Ports */ -#define VPORTC_DIR _SFR_MEM8(0x0008) -#define VPORTC_OUT _SFR_MEM8(0x0009) -#define VPORTC_IN _SFR_MEM8(0x000A) -#define VPORTC_INTFLAGS _SFR_MEM8(0x000B) - - -/* VPORT (VPORTD) - Virtual Ports */ -#define VPORTD_DIR _SFR_MEM8(0x000C) -#define VPORTD_OUT _SFR_MEM8(0x000D) -#define VPORTD_IN _SFR_MEM8(0x000E) -#define VPORTD_INTFLAGS _SFR_MEM8(0x000F) - - -/* VPORT (VPORTE) - Virtual Ports */ -#define VPORTE_DIR _SFR_MEM8(0x0010) -#define VPORTE_OUT _SFR_MEM8(0x0011) -#define VPORTE_IN _SFR_MEM8(0x0012) -#define VPORTE_INTFLAGS _SFR_MEM8(0x0013) - - -/* VPORT (VPORTF) - Virtual Ports */ -#define VPORTF_DIR _SFR_MEM8(0x0014) -#define VPORTF_OUT _SFR_MEM8(0x0015) -#define VPORTF_IN _SFR_MEM8(0x0016) -#define VPORTF_INTFLAGS _SFR_MEM8(0x0017) - - -/* GPIO - General Purpose IO */ -#define GPIO_GPIOR0 _SFR_MEM8(0x001C) -#define GPIO_GPIOR1 _SFR_MEM8(0x001D) -#define GPIO_GPIOR2 _SFR_MEM8(0x001E) -#define GPIO_GPIOR3 _SFR_MEM8(0x001F) - - -/* Deprecated */ -#define GPIO_GPIO0 _SFR_MEM8(0x001C) -#define GPIO_GPIO1 _SFR_MEM8(0x001D) -#define GPIO_GPIO2 _SFR_MEM8(0x001E) -#define GPIO_GPIO3 _SFR_MEM8(0x001F) - - -/* CPU - CPU */ -#define CPU_CCP _SFR_MEM8(0x0034) -#define CPU_RAMPZ _SFR_MEM8(0x003B) -#define CPU_SPL _SFR_MEM8(0x003D) -#define CPU_SPH _SFR_MEM8(0x003E) -#define CPU_SREG _SFR_MEM8(0x003F) - - -/* RSTCTRL - Reset controller */ -#define RSTCTRL_RSTFR _SFR_MEM8(0x0040) -#define RSTCTRL_SWRR _SFR_MEM8(0x0041) - - -/* SLPCTRL - Sleep Controller */ -#define SLPCTRL_CTRLA _SFR_MEM8(0x0050) - - -/* CLKCTRL - Clock controller */ -#define CLKCTRL_MCLKCTRLA _SFR_MEM8(0x0060) -#define CLKCTRL_MCLKCTRLB _SFR_MEM8(0x0061) -#define CLKCTRL_MCLKLOCK _SFR_MEM8(0x0062) -#define CLKCTRL_MCLKSTATUS _SFR_MEM8(0x0063) -#define CLKCTRL_OSC20MCTRLA _SFR_MEM8(0x0070) -#define CLKCTRL_OSC20MCALIBA _SFR_MEM8(0x0071) -#define CLKCTRL_OSC20MCALIBB _SFR_MEM8(0x0072) -#define CLKCTRL_OSC32KCTRLA _SFR_MEM8(0x0078) -#define CLKCTRL_OSC32KCALIB _SFR_MEM8(0x0079) -#define CLKCTRL_XOSC32KCTRLA _SFR_MEM8(0x007C) - - -/* BOD - Bod interface */ -#define BOD_CTRLA _SFR_MEM8(0x0080) -#define BOD_CTRLB _SFR_MEM8(0x0081) -#define BOD_VLMCTRLA _SFR_MEM8(0x0088) -#define BOD_INTCTRL _SFR_MEM8(0x0089) -#define BOD_INTFLAGS _SFR_MEM8(0x008A) -#define BOD_STATUS _SFR_MEM8(0x008B) - - -/* VREF - Voltage reference */ -#define VREF_CTRLA _SFR_MEM8(0x00A0) -#define VREF_CTRLB _SFR_MEM8(0x00A1) - - -/* NVMBIST - BIST in the NVMCTRL module */ -#define NVMBIST_CTRLA _SFR_MEM8(0x00C0) -#define NVMBIST_ADDRPAT _SFR_MEM8(0x00C1) -#define NVMBIST_DATAPAT _SFR_MEM8(0x00C2) -#define NVMBIST_STATUS _SFR_MEM8(0x00C3) -#define NVMBIST_CNT _SFR_MEM16(0x00C4) -#define NVMBIST_CNTL _SFR_MEM8(0x00C4) -#define NVMBIST_CNTH _SFR_MEM8(0x00C5) -#define NVMBIST_END _SFR_MEM32(0x00C6) -#define NVMBIST_END0 _SFR_MEM8(0x00C6) -#define NVMBIST_END1 _SFR_MEM8(0x00C7) -#define NVMBIST_END2 _SFR_MEM8(0x00C8) -#define NVMBIST_END3 _SFR_MEM8(0x00C9) - - -/* WDT - Watch-Dog Timer */ -#define WDT_CTRLA _SFR_MEM8(0x0100) -#define WDT_STATUS _SFR_MEM8(0x0101) - - -/* CPUINT - Interrupt Controller */ -#define CPUINT_CTRLA _SFR_MEM8(0x0110) -#define CPUINT_STATUS _SFR_MEM8(0x0111) -#define CPUINT_LVL0PRI _SFR_MEM8(0x0112) -#define CPUINT_LVL1VEC _SFR_MEM8(0x0113) - - -/* CRCSCAN - CRCSCAN */ -#define CRCSCAN_CTRLA _SFR_MEM8(0x0120) -#define CRCSCAN_CTRLB _SFR_MEM8(0x0121) -#define CRCSCAN_STATUS _SFR_MEM8(0x0122) - - -/* RTC - Real-Time Counter */ -#define RTC_CTRLA _SFR_MEM8(0x0140) -#define RTC_STATUS _SFR_MEM8(0x0141) -#define RTC_INTCTRL _SFR_MEM8(0x0142) -#define RTC_INTFLAGS _SFR_MEM8(0x0143) -#define RTC_TEMP _SFR_MEM8(0x0144) -#define RTC_DBGCTRL _SFR_MEM8(0x0145) -#define RTC_CLKSEL _SFR_MEM8(0x0147) -#define RTC_CNT _SFR_MEM16(0x0148) -#define RTC_CNTL _SFR_MEM8(0x0148) -#define RTC_CNTH _SFR_MEM8(0x0149) -#define RTC_PER _SFR_MEM16(0x014A) -#define RTC_PERL _SFR_MEM8(0x014A) -#define RTC_PERH _SFR_MEM8(0x014B) -#define RTC_CMP _SFR_MEM16(0x014C) -#define RTC_CMPL _SFR_MEM8(0x014C) -#define RTC_CMPH _SFR_MEM8(0x014D) -#define RTC_PITCTRLA _SFR_MEM8(0x0150) -#define RTC_PITSTATUS _SFR_MEM8(0x0151) -#define RTC_PITINTCTRL _SFR_MEM8(0x0152) -#define RTC_PITINTFLAGS _SFR_MEM8(0x0153) -#define RTC_PITDBGCTRL _SFR_MEM8(0x0155) - - -/* EVSYS - Event System */ -#define EVSYS_STROBE _SFR_MEM8(0x0180) -#define EVSYS_CHANNEL0 _SFR_MEM8(0x0190) -#define EVSYS_CHANNEL1 _SFR_MEM8(0x0191) -#define EVSYS_CHANNEL2 _SFR_MEM8(0x0192) -#define EVSYS_CHANNEL3 _SFR_MEM8(0x0193) -#define EVSYS_CHANNEL4 _SFR_MEM8(0x0194) -#define EVSYS_CHANNEL5 _SFR_MEM8(0x0195) -#define EVSYS_CHANNEL6 _SFR_MEM8(0x0196) -#define EVSYS_CHANNEL7 _SFR_MEM8(0x0197) -#define EVSYS_USERCCLLUT0A _SFR_MEM8(0x01A0) -#define EVSYS_USERCCLLUT0B _SFR_MEM8(0x01A1) -#define EVSYS_USERCCLLUT1A _SFR_MEM8(0x01A2) -#define EVSYS_USERCCLLUT1B _SFR_MEM8(0x01A3) -#define EVSYS_USERCCLLUT2A _SFR_MEM8(0x01A4) -#define EVSYS_USERCCLLUT2B _SFR_MEM8(0x01A5) -#define EVSYS_USERCCLLUT3A _SFR_MEM8(0x01A6) -#define EVSYS_USERCCLLUT3B _SFR_MEM8(0x01A7) -#define EVSYS_USERADC0 _SFR_MEM8(0x01A8) -#define EVSYS_USEREVOUTA _SFR_MEM8(0x01A9) -#define EVSYS_USEREVOUTB _SFR_MEM8(0x01AA) -#define EVSYS_USEREVOUTC _SFR_MEM8(0x01AB) -#define EVSYS_USEREVOUTD _SFR_MEM8(0x01AC) -#define EVSYS_USEREVOUTE _SFR_MEM8(0x01AD) -#define EVSYS_USEREVOUTF _SFR_MEM8(0x01AE) -#define EVSYS_USERUSART0 _SFR_MEM8(0x01AF) -#define EVSYS_USERUSART1 _SFR_MEM8(0x01B0) -#define EVSYS_USERUSART2 _SFR_MEM8(0x01B1) -#define EVSYS_USERUSART3 _SFR_MEM8(0x01B2) -#define EVSYS_USERTCA0 _SFR_MEM8(0x01B3) -#define EVSYS_USERTCB0 _SFR_MEM8(0x01B4) -#define EVSYS_USERTCB1 _SFR_MEM8(0x01B5) -#define EVSYS_USERTCB2 _SFR_MEM8(0x01B6) -#define EVSYS_USERTCB3 _SFR_MEM8(0x01B7) - - -/* CCL - Configurable Custom Logic */ -#define CCL_CTRLA _SFR_MEM8(0x01C0) -#define CCL_SEQCTRL0 _SFR_MEM8(0x01C1) -#define CCL_INTCTRL0 _SFR_MEM8(0x01C5) -#define CCL_INTFLAGS _SFR_MEM8(0x01C7) -#define CCL_LUT0CTRLA _SFR_MEM8(0x01C8) -#define CCL_LUT0CTRLB _SFR_MEM8(0x01C9) -#define CCL_LUT0CTRLC _SFR_MEM8(0x01CA) -#define CCL_TRUTH0 _SFR_MEM8(0x01CB) -#define CCL_LUT1CTRLA _SFR_MEM8(0x01CC) -#define CCL_LUT1CTRLB _SFR_MEM8(0x01CD) -#define CCL_LUT1CTRLC _SFR_MEM8(0x01CE) -#define CCL_TRUTH1 _SFR_MEM8(0x01CF) -#define CCL_LUT2CTRLA _SFR_MEM8(0x01D0) -#define CCL_LUT2CTRLB _SFR_MEM8(0x01D1) -#define CCL_LUT2CTRLC _SFR_MEM8(0x01D2) -#define CCL_TRUTH2 _SFR_MEM8(0x01D3) -#define CCL_LUT3CTRLA _SFR_MEM8(0x01D4) -#define CCL_LUT3CTRLB _SFR_MEM8(0x01D5) -#define CCL_LUT3CTRLC _SFR_MEM8(0x01D6) -#define CCL_TRUTH3 _SFR_MEM8(0x01D7) - - -/* PORT (PORTA) - I/O Ports */ -#define PORTA_DIR _SFR_MEM8(0x0400) -#define PORTA_DIRSET _SFR_MEM8(0x0401) -#define PORTA_DIRCLR _SFR_MEM8(0x0402) -#define PORTA_DIRTGL _SFR_MEM8(0x0403) -#define PORTA_OUT _SFR_MEM8(0x0404) -#define PORTA_OUTSET _SFR_MEM8(0x0405) -#define PORTA_OUTCLR _SFR_MEM8(0x0406) -#define PORTA_OUTTGL _SFR_MEM8(0x0407) -#define PORTA_IN _SFR_MEM8(0x0408) -#define PORTA_INTFLAGS _SFR_MEM8(0x0409) -#define PORTA_PORTCTRL _SFR_MEM8(0x040A) -#define PORTA_PIN0CTRL _SFR_MEM8(0x0410) -#define PORTA_PIN1CTRL _SFR_MEM8(0x0411) -#define PORTA_PIN2CTRL _SFR_MEM8(0x0412) -#define PORTA_PIN3CTRL _SFR_MEM8(0x0413) -#define PORTA_PIN4CTRL _SFR_MEM8(0x0414) -#define PORTA_PIN5CTRL _SFR_MEM8(0x0415) -#define PORTA_PIN6CTRL _SFR_MEM8(0x0416) -#define PORTA_PIN7CTRL _SFR_MEM8(0x0417) - - -/* PORT (PORTB) - I/O Ports */ -#define PORTB_DIR _SFR_MEM8(0x0420) -#define PORTB_DIRSET _SFR_MEM8(0x0421) -#define PORTB_DIRCLR _SFR_MEM8(0x0422) -#define PORTB_DIRTGL _SFR_MEM8(0x0423) -#define PORTB_OUT _SFR_MEM8(0x0424) -#define PORTB_OUTSET _SFR_MEM8(0x0425) -#define PORTB_OUTCLR _SFR_MEM8(0x0426) -#define PORTB_OUTTGL _SFR_MEM8(0x0427) -#define PORTB_IN _SFR_MEM8(0x0428) -#define PORTB_INTFLAGS _SFR_MEM8(0x0429) -#define PORTB_PORTCTRL _SFR_MEM8(0x042A) -#define PORTB_PIN0CTRL _SFR_MEM8(0x0430) -#define PORTB_PIN1CTRL _SFR_MEM8(0x0431) -#define PORTB_PIN2CTRL _SFR_MEM8(0x0432) -#define PORTB_PIN3CTRL _SFR_MEM8(0x0433) -#define PORTB_PIN4CTRL _SFR_MEM8(0x0434) -#define PORTB_PIN5CTRL _SFR_MEM8(0x0435) -#define PORTB_PIN6CTRL _SFR_MEM8(0x0436) -#define PORTB_PIN7CTRL _SFR_MEM8(0x0437) - - -/* PORT (PORTC) - I/O Ports */ -#define PORTC_DIR _SFR_MEM8(0x0440) -#define PORTC_DIRSET _SFR_MEM8(0x0441) -#define PORTC_DIRCLR _SFR_MEM8(0x0442) -#define PORTC_DIRTGL _SFR_MEM8(0x0443) -#define PORTC_OUT _SFR_MEM8(0x0444) -#define PORTC_OUTSET _SFR_MEM8(0x0445) -#define PORTC_OUTCLR _SFR_MEM8(0x0446) -#define PORTC_OUTTGL _SFR_MEM8(0x0447) -#define PORTC_IN _SFR_MEM8(0x0448) -#define PORTC_INTFLAGS _SFR_MEM8(0x0449) -#define PORTC_PORTCTRL _SFR_MEM8(0x044A) -#define PORTC_PIN0CTRL _SFR_MEM8(0x0450) -#define PORTC_PIN1CTRL _SFR_MEM8(0x0451) -#define PORTC_PIN2CTRL _SFR_MEM8(0x0452) -#define PORTC_PIN3CTRL _SFR_MEM8(0x0453) -#define PORTC_PIN4CTRL _SFR_MEM8(0x0454) -#define PORTC_PIN5CTRL _SFR_MEM8(0x0455) -#define PORTC_PIN6CTRL _SFR_MEM8(0x0456) -#define PORTC_PIN7CTRL _SFR_MEM8(0x0457) - - -/* PORT (PORTD) - I/O Ports */ -#define PORTD_DIR _SFR_MEM8(0x0460) -#define PORTD_DIRSET _SFR_MEM8(0x0461) -#define PORTD_DIRCLR _SFR_MEM8(0x0462) -#define PORTD_DIRTGL _SFR_MEM8(0x0463) -#define PORTD_OUT _SFR_MEM8(0x0464) -#define PORTD_OUTSET _SFR_MEM8(0x0465) -#define PORTD_OUTCLR _SFR_MEM8(0x0466) -#define PORTD_OUTTGL _SFR_MEM8(0x0467) -#define PORTD_IN _SFR_MEM8(0x0468) -#define PORTD_INTFLAGS _SFR_MEM8(0x0469) -#define PORTD_PORTCTRL _SFR_MEM8(0x046A) -#define PORTD_PIN0CTRL _SFR_MEM8(0x0470) -#define PORTD_PIN1CTRL _SFR_MEM8(0x0471) -#define PORTD_PIN2CTRL _SFR_MEM8(0x0472) -#define PORTD_PIN3CTRL _SFR_MEM8(0x0473) -#define PORTD_PIN4CTRL _SFR_MEM8(0x0474) -#define PORTD_PIN5CTRL _SFR_MEM8(0x0475) -#define PORTD_PIN6CTRL _SFR_MEM8(0x0476) -#define PORTD_PIN7CTRL _SFR_MEM8(0x0477) - - -/* PORT (PORTE) - I/O Ports */ -#define PORTE_DIR _SFR_MEM8(0x0480) -#define PORTE_DIRSET _SFR_MEM8(0x0481) -#define PORTE_DIRCLR _SFR_MEM8(0x0482) -#define PORTE_DIRTGL _SFR_MEM8(0x0483) -#define PORTE_OUT _SFR_MEM8(0x0484) -#define PORTE_OUTSET _SFR_MEM8(0x0485) -#define PORTE_OUTCLR _SFR_MEM8(0x0486) -#define PORTE_OUTTGL _SFR_MEM8(0x0487) -#define PORTE_IN _SFR_MEM8(0x0488) -#define PORTE_INTFLAGS _SFR_MEM8(0x0489) -#define PORTE_PORTCTRL _SFR_MEM8(0x048A) -#define PORTE_PIN0CTRL _SFR_MEM8(0x0490) -#define PORTE_PIN1CTRL _SFR_MEM8(0x0491) -#define PORTE_PIN2CTRL _SFR_MEM8(0x0492) -#define PORTE_PIN3CTRL _SFR_MEM8(0x0493) -#define PORTE_PIN4CTRL _SFR_MEM8(0x0494) -#define PORTE_PIN5CTRL _SFR_MEM8(0x0495) -#define PORTE_PIN6CTRL _SFR_MEM8(0x0496) -#define PORTE_PIN7CTRL _SFR_MEM8(0x0497) - - -/* PORT (PORTF) - I/O Ports */ -#define PORTF_DIR _SFR_MEM8(0x04A0) -#define PORTF_DIRSET _SFR_MEM8(0x04A1) -#define PORTF_DIRCLR _SFR_MEM8(0x04A2) -#define PORTF_DIRTGL _SFR_MEM8(0x04A3) -#define PORTF_OUT _SFR_MEM8(0x04A4) -#define PORTF_OUTSET _SFR_MEM8(0x04A5) -#define PORTF_OUTCLR _SFR_MEM8(0x04A6) -#define PORTF_OUTTGL _SFR_MEM8(0x04A7) -#define PORTF_IN _SFR_MEM8(0x04A8) -#define PORTF_INTFLAGS _SFR_MEM8(0x04A9) -#define PORTF_PORTCTRL _SFR_MEM8(0x04AA) -#define PORTF_PIN0CTRL _SFR_MEM8(0x04B0) -#define PORTF_PIN1CTRL _SFR_MEM8(0x04B1) -#define PORTF_PIN2CTRL _SFR_MEM8(0x04B2) -#define PORTF_PIN3CTRL _SFR_MEM8(0x04B3) -#define PORTF_PIN4CTRL _SFR_MEM8(0x04B4) -#define PORTF_PIN5CTRL _SFR_MEM8(0x04B5) -#define PORTF_PIN6CTRL _SFR_MEM8(0x04B6) -#define PORTF_PIN7CTRL _SFR_MEM8(0x04B7) - - -/* PORTMUX - Port Multiplexer */ -#define PORTMUX_EVSYSROUTEA _SFR_MEM8(0x05E0) -#define PORTMUX_CCLROUTEA _SFR_MEM8(0x05E1) -#define PORTMUX_USARTROUTEA _SFR_MEM8(0x05E2) -#define PORTMUX_TWISPIROUTEA _SFR_MEM8(0x05E3) -#define PORTMUX_TCAROUTEA _SFR_MEM8(0x05E4) -#define PORTMUX_TCBROUTEA _SFR_MEM8(0x05E5) - - -/* ADC (ADC0) - Analog to Digital Converter */ -#define ADC0_CTRLA _SFR_MEM8(0x0600) -#define ADC0_CTRLB _SFR_MEM8(0x0601) -#define ADC0_CTRLC _SFR_MEM8(0x0602) -#define ADC0_CTRLD _SFR_MEM8(0x0603) -#define ADC0_CTRLE _SFR_MEM8(0x0604) -#define ADC0_SAMPCTRL _SFR_MEM8(0x0605) -#define ADC0_MUXPOS _SFR_MEM8(0x0606) -#define ADC0_COMMAND _SFR_MEM8(0x0608) -#define ADC0_EVCTRL _SFR_MEM8(0x0609) -#define ADC0_INTCTRL _SFR_MEM8(0x060A) -#define ADC0_INTFLAGS _SFR_MEM8(0x060B) -#define ADC0_DBGCTRL _SFR_MEM8(0x060C) -#define ADC0_TEMP _SFR_MEM8(0x060D) -#define ADC0_RES _SFR_MEM16(0x0610) -#define ADC0_RESL _SFR_MEM8(0x0610) -#define ADC0_RESH _SFR_MEM8(0x0611) -#define ADC0_WINLT _SFR_MEM16(0x0612) -#define ADC0_WINLTL _SFR_MEM8(0x0612) -#define ADC0_WINLTH _SFR_MEM8(0x0613) -#define ADC0_WINHT _SFR_MEM16(0x0614) -#define ADC0_WINHTL _SFR_MEM8(0x0614) -#define ADC0_WINHTH _SFR_MEM8(0x0615) -#define ADC0_CALIB _SFR_MEM8(0x0616) - - -/* AC (AC0) - Analog Comparator */ -#define AC0_CTRLA _SFR_MEM8(0x0680) -#define AC0_MUXCTRLA _SFR_MEM8(0x0682) -#define AC0_DACREF _SFR_MEM8(0x0684) -#define AC0_INTCTRL _SFR_MEM8(0x0686) -#define AC0_STATUS _SFR_MEM8(0x0687) - - -/* USART (USART0) - Universal Synchronous and Asynchronous Receiver and Transmitter */ -#define USART0_RXDATAL _SFR_MEM8(0x0800) -#define USART0_RXDATAH _SFR_MEM8(0x0801) -#define USART0_TXDATAL _SFR_MEM8(0x0802) -#define USART0_TXDATAH _SFR_MEM8(0x0803) -#define USART0_STATUS _SFR_MEM8(0x0804) -#define USART0_CTRLA _SFR_MEM8(0x0805) -#define USART0_CTRLB _SFR_MEM8(0x0806) -#define USART0_CTRLC _SFR_MEM8(0x0807) -#define USART0_BAUD _SFR_MEM16(0x0808) -#define USART0_BAUDL _SFR_MEM8(0x0808) -#define USART0_BAUDH _SFR_MEM8(0x0809) -#define USART0_CTRLD _SFR_MEM8(0x080A) -#define USART0_DBGCTRL _SFR_MEM8(0x080B) -#define USART0_EVCTRL _SFR_MEM8(0x080C) -#define USART0_TXPLCTRL _SFR_MEM8(0x080D) -#define USART0_RXPLCTRL _SFR_MEM8(0x080E) - - -/* USART (USART1) - Universal Synchronous and Asynchronous Receiver and Transmitter */ -#define USART1_RXDATAL _SFR_MEM8(0x0820) -#define USART1_RXDATAH _SFR_MEM8(0x0821) -#define USART1_TXDATAL _SFR_MEM8(0x0822) -#define USART1_TXDATAH _SFR_MEM8(0x0823) -#define USART1_STATUS _SFR_MEM8(0x0824) -#define USART1_CTRLA _SFR_MEM8(0x0825) -#define USART1_CTRLB _SFR_MEM8(0x0826) -#define USART1_CTRLC _SFR_MEM8(0x0827) -#define USART1_BAUD _SFR_MEM16(0x0828) -#define USART1_BAUDL _SFR_MEM8(0x0828) -#define USART1_BAUDH _SFR_MEM8(0x0829) -#define USART1_CTRLD _SFR_MEM8(0x082A) -#define USART1_DBGCTRL _SFR_MEM8(0x082B) -#define USART1_EVCTRL _SFR_MEM8(0x082C) -#define USART1_TXPLCTRL _SFR_MEM8(0x082D) -#define USART1_RXPLCTRL _SFR_MEM8(0x082E) - - -/* TWI (TWI0) - Two-Wire Interface */ -#define TWI0_CTRLA _SFR_MEM8(0x08A0) -#define TWI0_BRIDGECTRL _SFR_MEM8(0x08A1) -#define TWI0_DBGCTRL _SFR_MEM8(0x08A2) -#define TWI0_MCTRLA _SFR_MEM8(0x08A3) -#define TWI0_MCTRLB _SFR_MEM8(0x08A4) -#define TWI0_MSTATUS _SFR_MEM8(0x08A5) -#define TWI0_MBAUD _SFR_MEM8(0x08A6) -#define TWI0_MADDR _SFR_MEM8(0x08A7) -#define TWI0_MDATA _SFR_MEM8(0x08A8) -#define TWI0_SCTRLA _SFR_MEM8(0x08A9) -#define TWI0_SCTRLB _SFR_MEM8(0x08AA) -#define TWI0_SSTATUS _SFR_MEM8(0x08AB) -#define TWI0_SADDR _SFR_MEM8(0x08AC) -#define TWI0_SDATA _SFR_MEM8(0x08AD) -#define TWI0_SADDRMASK _SFR_MEM8(0x08AE) - - -/* SPI (SPI0) - Serial Peripheral Interface */ -#define SPI0_CTRLA _SFR_MEM8(0x08C0) -#define SPI0_CTRLB _SFR_MEM8(0x08C1) -#define SPI0_INTCTRL _SFR_MEM8(0x08C2) -#define SPI0_INTFLAGS _SFR_MEM8(0x08C3) -#define SPI0_DATA _SFR_MEM8(0x08C4) - - -/* TCA (TCA0) - 16-bit Timer/Counter Type A */ -#define TCA0_SINGLE_CTRLA _SFR_MEM8(0x0A00) -#define TCA0_SINGLE_CTRLB _SFR_MEM8(0x0A01) -#define TCA0_SINGLE_CTRLC _SFR_MEM8(0x0A02) -#define TCA0_SINGLE_CTRLD _SFR_MEM8(0x0A03) -#define TCA0_SINGLE_CTRLECLR _SFR_MEM8(0x0A04) -#define TCA0_SINGLE_CTRLESET _SFR_MEM8(0x0A05) -#define TCA0_SINGLE_CTRLFCLR _SFR_MEM8(0x0A06) -#define TCA0_SINGLE_CTRLFSET _SFR_MEM8(0x0A07) -#define TCA0_SINGLE_EVCTRL _SFR_MEM8(0x0A09) -#define TCA0_SINGLE_INTCTRL _SFR_MEM8(0x0A0A) -#define TCA0_SINGLE_INTFLAGS _SFR_MEM8(0x0A0B) -#define TCA0_SINGLE_DBGCTRL _SFR_MEM8(0x0A0E) -#define TCA0_SINGLE_TEMP _SFR_MEM8(0x0A0F) -#define TCA0_SINGLE_CNT _SFR_MEM16(0x0A20) -#define TCA0_SINGLE_PER _SFR_MEM16(0x0A26) -#define TCA0_SINGLE_CMP0 _SFR_MEM16(0x0A28) -#define TCA0_SINGLE_CMP1 _SFR_MEM16(0x0A2A) -#define TCA0_SINGLE_CMP2 _SFR_MEM16(0x0A2C) -#define TCA0_SINGLE_PERBUF _SFR_MEM16(0x0A36) -#define TCA0_SINGLE_CMP0BUF _SFR_MEM16(0x0A38) -#define TCA0_SINGLE_CMP1BUF _SFR_MEM16(0x0A3A) -#define TCA0_SINGLE_CMP2BUF _SFR_MEM16(0x0A3C) - - -#define TCA0_SPLIT_CTRLA _SFR_MEM8(0x0A00) -#define TCA0_SPLIT_CTRLB _SFR_MEM8(0x0A01) -#define TCA0_SPLIT_CTRLC _SFR_MEM8(0x0A02) -#define TCA0_SPLIT_CTRLD _SFR_MEM8(0x0A03) -#define TCA0_SPLIT_CTRLECLR _SFR_MEM8(0x0A04) -#define TCA0_SPLIT_CTRLESET _SFR_MEM8(0x0A05) -#define TCA0_SPLIT_INTCTRL _SFR_MEM8(0x0A0A) -#define TCA0_SPLIT_INTFLAGS _SFR_MEM8(0x0A0B) -#define TCA0_SPLIT_DBGCTRL _SFR_MEM8(0x0A0E) -#define TCA0_SPLIT_LCNT _SFR_MEM8(0x0A20) -#define TCA0_SPLIT_HCNT _SFR_MEM8(0x0A21) -#define TCA0_SPLIT_LPER _SFR_MEM8(0x0A26) -#define TCA0_SPLIT_HPER _SFR_MEM8(0x0A27) -#define TCA0_SPLIT_LCMP0 _SFR_MEM8(0x0A28) -#define TCA0_SPLIT_HCMP0 _SFR_MEM8(0x0A29) -#define TCA0_SPLIT_LCMP1 _SFR_MEM8(0x0A2A) -#define TCA0_SPLIT_HCMP1 _SFR_MEM8(0x0A2B) -#define TCA0_SPLIT_LCMP2 _SFR_MEM8(0x0A2C) -#define TCA0_SPLIT_HCMP2 _SFR_MEM8(0x0A2D) - - - - -/* TCB (TCB0) - 16-bit Timer Type B */ -#define TCB0_CTRLA _SFR_MEM8(0x0A80) -#define TCB0_CTRLB _SFR_MEM8(0x0A81) -#define TCB0_EVCTRL _SFR_MEM8(0x0A84) -#define TCB0_INTCTRL _SFR_MEM8(0x0A85) -#define TCB0_INTFLAGS _SFR_MEM8(0x0A86) -#define TCB0_STATUS _SFR_MEM8(0x0A87) -#define TCB0_DBGCTRL _SFR_MEM8(0x0A88) -#define TCB0_TEMP _SFR_MEM8(0x0A89) -#define TCB0_CNT _SFR_MEM16(0x0A8A) -#define TCB0_CNTL _SFR_MEM8(0x0A8A) -#define TCB0_CNTH _SFR_MEM8(0x0A8B) -#define TCB0_CCMP _SFR_MEM16(0x0A8C) -#define TCB0_CCMPL _SFR_MEM8(0x0A8C) -#define TCB0_CCMPH _SFR_MEM8(0x0A8D) - - -/* TCB (TCB1) - 16-bit Timer Type B */ -#define TCB1_CTRLA _SFR_MEM8(0x0A90) -#define TCB1_CTRLB _SFR_MEM8(0x0A91) -#define TCB1_EVCTRL _SFR_MEM8(0x0A94) -#define TCB1_INTCTRL _SFR_MEM8(0x0A95) -#define TCB1_INTFLAGS _SFR_MEM8(0x0A96) -#define TCB1_STATUS _SFR_MEM8(0x0A97) -#define TCB1_DBGCTRL _SFR_MEM8(0x0A98) -#define TCB1_TEMP _SFR_MEM8(0x0A99) -#define TCB1_CNT _SFR_MEM16(0x0A9A) -#define TCB1_CNTL _SFR_MEM8(0x0A9A) -#define TCB1_CNTH _SFR_MEM8(0x0A9B) -#define TCB1_CCMP _SFR_MEM16(0x0A9C) -#define TCB1_CCMPL _SFR_MEM8(0x0A9C) -#define TCB1_CCMPH _SFR_MEM8(0x0A9D) - - -/* TCB (TCB2) - 16-bit Timer Type B */ -#define TCB2_CTRLA _SFR_MEM8(0x0AA0) -#define TCB2_CTRLB _SFR_MEM8(0x0AA1) -#define TCB2_EVCTRL _SFR_MEM8(0x0AA4) -#define TCB2_INTCTRL _SFR_MEM8(0x0AA5) -#define TCB2_INTFLAGS _SFR_MEM8(0x0AA6) -#define TCB2_STATUS _SFR_MEM8(0x0AA7) -#define TCB2_DBGCTRL _SFR_MEM8(0x0AA8) -#define TCB2_TEMP _SFR_MEM8(0x0AA9) -#define TCB2_CNT _SFR_MEM16(0x0AAA) -#define TCB2_CNTL _SFR_MEM8(0x0AAA) -#define TCB2_CNTH _SFR_MEM8(0x0AAB) -#define TCB2_CCMP _SFR_MEM16(0x0AAC) -#define TCB2_CCMPL _SFR_MEM8(0x0AAC) -#define TCB2_CCMPH _SFR_MEM8(0x0AAD) - - -/* SYSCFG - System Configuration Registers */ -#define SYSCFG_REVID _SFR_MEM8(0x0F01) -#define SYSCFG_EXTBRK _SFR_MEM8(0x0F02) -#define SYSCFG_OCDM _SFR_MEM8(0x0F18) -#define SYSCFG_OCDMS _SFR_MEM8(0x0F19) - - -/* NVMCTRL - Non-volatile Memory Controller */ -#define NVMCTRL_CTRLA _SFR_MEM8(0x1000) -#define NVMCTRL_CTRLB _SFR_MEM8(0x1001) -#define NVMCTRL_STATUS _SFR_MEM8(0x1002) -#define NVMCTRL_INTCTRL _SFR_MEM8(0x1003) -#define NVMCTRL_INTFLAGS _SFR_MEM8(0x1004) -#define NVMCTRL_DATA _SFR_MEM16(0x1006) -#define NVMCTRL_DATAL _SFR_MEM8(0x1006) -#define NVMCTRL_DATAH _SFR_MEM8(0x1007) -#define NVMCTRL_ADDR _SFR_MEM16(0x1008) -#define NVMCTRL_ADDRL _SFR_MEM8(0x1008) -#define NVMCTRL_ADDRH _SFR_MEM8(0x1009) - - -/* SIGROW - Signature row */ -#define SIGROW_DEVICEID0 _SFR_MEM8(0x1100) -#define SIGROW_DEVICEID1 _SFR_MEM8(0x1101) -#define SIGROW_DEVICEID2 _SFR_MEM8(0x1102) -#define SIGROW_SERNUM0 _SFR_MEM8(0x1103) -#define SIGROW_SERNUM1 _SFR_MEM8(0x1104) -#define SIGROW_SERNUM2 _SFR_MEM8(0x1105) -#define SIGROW_SERNUM3 _SFR_MEM8(0x1106) -#define SIGROW_SERNUM4 _SFR_MEM8(0x1107) -#define SIGROW_SERNUM5 _SFR_MEM8(0x1108) -#define SIGROW_SERNUM6 _SFR_MEM8(0x1109) -#define SIGROW_SERNUM7 _SFR_MEM8(0x110A) -#define SIGROW_SERNUM8 _SFR_MEM8(0x110B) -#define SIGROW_SERNUM9 _SFR_MEM8(0x110C) -#define SIGROW_OSCCAL32K _SFR_MEM8(0x1114) -#define SIGROW_OSCCAL16M0 _SFR_MEM8(0x1118) -#define SIGROW_OSCCAL16M1 _SFR_MEM8(0x1119) -#define SIGROW_OSCCAL20M0 _SFR_MEM8(0x111A) -#define SIGROW_OSCCAL20M1 _SFR_MEM8(0x111B) -#define SIGROW_TEMPSENSE0 _SFR_MEM8(0x1120) -#define SIGROW_TEMPSENSE1 _SFR_MEM8(0x1121) -#define SIGROW_OSC16ERR3V _SFR_MEM8(0x1122) -#define SIGROW_OSC16ERR5V _SFR_MEM8(0x1123) -#define SIGROW_OSC20ERR3V _SFR_MEM8(0x1124) -#define SIGROW_OSC20ERR5V _SFR_MEM8(0x1125) -#define SIGROW_CHECKSUM1 _SFR_MEM8(0x112F) - - -/* FUSE - Fuses */ -#define FUSE_WDTCFG _SFR_MEM8(0x1280) -#define FUSE_BODCFG _SFR_MEM8(0x1281) -#define FUSE_OSCCFG _SFR_MEM8(0x1282) -#define FUSE_TCD0CFG _SFR_MEM8(0x1284) -#define FUSE_SYSCFG0 _SFR_MEM8(0x1285) -#define FUSE_SYSCFG1 _SFR_MEM8(0x1286) -#define FUSE_APPEND _SFR_MEM8(0x1287) -#define FUSE_BOOTEND _SFR_MEM8(0x1288) - - -/* LOCKBIT - Lockbit */ -#define LOCKBIT_LOCKBIT _SFR_MEM8(0x128A) - - -/* USERROW - User Row */ -#define USERROW_USERROW0 _SFR_MEM8(0x1300) -#define USERROW_USERROW1 _SFR_MEM8(0x1301) -#define USERROW_USERROW2 _SFR_MEM8(0x1302) -#define USERROW_USERROW3 _SFR_MEM8(0x1303) -#define USERROW_USERROW4 _SFR_MEM8(0x1304) -#define USERROW_USERROW5 _SFR_MEM8(0x1305) -#define USERROW_USERROW6 _SFR_MEM8(0x1306) -#define USERROW_USERROW7 _SFR_MEM8(0x1307) -#define USERROW_USERROW8 _SFR_MEM8(0x1308) -#define USERROW_USERROW9 _SFR_MEM8(0x1309) -#define USERROW_USERROW10 _SFR_MEM8(0x130A) -#define USERROW_USERROW11 _SFR_MEM8(0x130B) -#define USERROW_USERROW12 _SFR_MEM8(0x130C) -#define USERROW_USERROW13 _SFR_MEM8(0x130D) -#define USERROW_USERROW14 _SFR_MEM8(0x130E) -#define USERROW_USERROW15 _SFR_MEM8(0x130F) -#define USERROW_USERROW16 _SFR_MEM8(0x1310) -#define USERROW_USERROW17 _SFR_MEM8(0x1311) -#define USERROW_USERROW18 _SFR_MEM8(0x1312) -#define USERROW_USERROW19 _SFR_MEM8(0x1313) -#define USERROW_USERROW20 _SFR_MEM8(0x1314) -#define USERROW_USERROW21 _SFR_MEM8(0x1315) -#define USERROW_USERROW22 _SFR_MEM8(0x1316) -#define USERROW_USERROW23 _SFR_MEM8(0x1317) -#define USERROW_USERROW24 _SFR_MEM8(0x1318) -#define USERROW_USERROW25 _SFR_MEM8(0x1319) -#define USERROW_USERROW26 _SFR_MEM8(0x131A) -#define USERROW_USERROW27 _SFR_MEM8(0x131B) -#define USERROW_USERROW28 _SFR_MEM8(0x131C) -#define USERROW_USERROW29 _SFR_MEM8(0x131D) -#define USERROW_USERROW30 _SFR_MEM8(0x131E) -#define USERROW_USERROW31 _SFR_MEM8(0x131F) -#define USERROW_USERROW32 _SFR_MEM8(0x1320) -#define USERROW_USERROW33 _SFR_MEM8(0x1321) -#define USERROW_USERROW34 _SFR_MEM8(0x1322) -#define USERROW_USERROW35 _SFR_MEM8(0x1323) -#define USERROW_USERROW36 _SFR_MEM8(0x1324) -#define USERROW_USERROW37 _SFR_MEM8(0x1325) -#define USERROW_USERROW38 _SFR_MEM8(0x1326) -#define USERROW_USERROW39 _SFR_MEM8(0x1327) -#define USERROW_USERROW40 _SFR_MEM8(0x1328) -#define USERROW_USERROW41 _SFR_MEM8(0x1329) -#define USERROW_USERROW42 _SFR_MEM8(0x132A) -#define USERROW_USERROW43 _SFR_MEM8(0x132B) -#define USERROW_USERROW44 _SFR_MEM8(0x132C) -#define USERROW_USERROW45 _SFR_MEM8(0x132D) -#define USERROW_USERROW46 _SFR_MEM8(0x132E) -#define USERROW_USERROW47 _SFR_MEM8(0x132F) -#define USERROW_USERROW48 _SFR_MEM8(0x1330) -#define USERROW_USERROW49 _SFR_MEM8(0x1331) -#define USERROW_USERROW50 _SFR_MEM8(0x1332) -#define USERROW_USERROW51 _SFR_MEM8(0x1333) -#define USERROW_USERROW52 _SFR_MEM8(0x1334) -#define USERROW_USERROW53 _SFR_MEM8(0x1335) -#define USERROW_USERROW54 _SFR_MEM8(0x1336) -#define USERROW_USERROW55 _SFR_MEM8(0x1337) -#define USERROW_USERROW56 _SFR_MEM8(0x1338) -#define USERROW_USERROW57 _SFR_MEM8(0x1339) -#define USERROW_USERROW58 _SFR_MEM8(0x133A) -#define USERROW_USERROW59 _SFR_MEM8(0x133B) -#define USERROW_USERROW60 _SFR_MEM8(0x133C) -#define USERROW_USERROW61 _SFR_MEM8(0x133D) -#define USERROW_USERROW62 _SFR_MEM8(0x133E) -#define USERROW_USERROW63 _SFR_MEM8(0x133F) - - - -/*================== Bitfield Definitions ================== */ - -/* AC - Analog Comparator */ -/* AC.CTRLA bit masks and bit positions */ -#define AC_ENABLE_bm 0x01 /* Enable bit mask. */ -#define AC_ENABLE_bp 0 /* Enable bit position. */ -#define AC_HYSMODE_gm 0x06 /* Hysteresis Mode group mask. */ -#define AC_HYSMODE_gp 1 /* Hysteresis Mode group position. */ -#define AC_HYSMODE0_bm (1<<1) /* Hysteresis Mode bit 0 mask. */ -#define AC_HYSMODE0_bp 1 /* Hysteresis Mode bit 0 position. */ -#define AC_HYSMODE1_bm (1<<2) /* Hysteresis Mode bit 1 mask. */ -#define AC_HYSMODE1_bp 2 /* Hysteresis Mode bit 1 position. */ -#define AC_LPMODE_bm 0x08 /* Low Power Mode bit mask. */ -#define AC_LPMODE_bp 3 /* Low Power Mode bit position. */ -#define AC_INTMODE_gm 0x30 /* Interrupt Mode group mask. */ -#define AC_INTMODE_gp 4 /* Interrupt Mode group position. */ -#define AC_INTMODE0_bm (1<<4) /* Interrupt Mode bit 0 mask. */ -#define AC_INTMODE0_bp 4 /* Interrupt Mode bit 0 position. */ -#define AC_INTMODE1_bm (1<<5) /* Interrupt Mode bit 1 mask. */ -#define AC_INTMODE1_bp 5 /* Interrupt Mode bit 1 position. */ -#define AC_OUTEN_bm 0x40 /* Output Buffer Enable bit mask. */ -#define AC_OUTEN_bp 6 /* Output Buffer Enable bit position. */ -#define AC_RUNSTDBY_bm 0x80 /* Run in Standby Mode bit mask. */ -#define AC_RUNSTDBY_bp 7 /* Run in Standby Mode bit position. */ - -/* AC.MUXCTRLA bit masks and bit positions */ -#define AC_MUXNEG_gm 0x03 /* Negative Input MUX Selection group mask. */ -#define AC_MUXNEG_gp 0 /* Negative Input MUX Selection group position. */ -#define AC_MUXNEG0_bm (1<<0) /* Negative Input MUX Selection bit 0 mask. */ -#define AC_MUXNEG0_bp 0 /* Negative Input MUX Selection bit 0 position. */ -#define AC_MUXNEG1_bm (1<<1) /* Negative Input MUX Selection bit 1 mask. */ -#define AC_MUXNEG1_bp 1 /* Negative Input MUX Selection bit 1 position. */ -#define AC_MUXPOS_gm 0x18 /* Positive Input MUX Selection group mask. */ -#define AC_MUXPOS_gp 3 /* Positive Input MUX Selection group position. */ -#define AC_MUXPOS0_bm (1<<3) /* Positive Input MUX Selection bit 0 mask. */ -#define AC_MUXPOS0_bp 3 /* Positive Input MUX Selection bit 0 position. */ -#define AC_MUXPOS1_bm (1<<4) /* Positive Input MUX Selection bit 1 mask. */ -#define AC_MUXPOS1_bp 4 /* Positive Input MUX Selection bit 1 position. */ -#define AC_INVERT_bm 0x80 /* Invert AC Output bit mask. */ -#define AC_INVERT_bp 7 /* Invert AC Output bit position. */ - -/* AC.DACREF bit masks and bit positions */ -#define AC_DATA_gm 0xFF /* DAC voltage reference group mask. */ -#define AC_DATA_gp 0 /* DAC voltage reference group position. */ -#define AC_DATA0_bm (1<<0) /* DAC voltage reference bit 0 mask. */ -#define AC_DATA0_bp 0 /* DAC voltage reference bit 0 position. */ -#define AC_DATA1_bm (1<<1) /* DAC voltage reference bit 1 mask. */ -#define AC_DATA1_bp 1 /* DAC voltage reference bit 1 position. */ -#define AC_DATA2_bm (1<<2) /* DAC voltage reference bit 2 mask. */ -#define AC_DATA2_bp 2 /* DAC voltage reference bit 2 position. */ -#define AC_DATA3_bm (1<<3) /* DAC voltage reference bit 3 mask. */ -#define AC_DATA3_bp 3 /* DAC voltage reference bit 3 position. */ -#define AC_DATA4_bm (1<<4) /* DAC voltage reference bit 4 mask. */ -#define AC_DATA4_bp 4 /* DAC voltage reference bit 4 position. */ -#define AC_DATA5_bm (1<<5) /* DAC voltage reference bit 5 mask. */ -#define AC_DATA5_bp 5 /* DAC voltage reference bit 5 position. */ -#define AC_DATA6_bm (1<<6) /* DAC voltage reference bit 6 mask. */ -#define AC_DATA6_bp 6 /* DAC voltage reference bit 6 position. */ -#define AC_DATA7_bm (1<<7) /* DAC voltage reference bit 7 mask. */ -#define AC_DATA7_bp 7 /* DAC voltage reference bit 7 position. */ - -/* AC.INTCTRL bit masks and bit positions */ -#define AC_CMP_bm 0x01 /* Analog Comparator 0 Interrupt Enable bit mask. */ -#define AC_CMP_bp 0 /* Analog Comparator 0 Interrupt Enable bit position. */ - -/* AC.STATUS bit masks and bit positions */ -/* AC_CMP is already defined. */ -#define AC_STATE_bm 0x10 /* Analog Comparator State bit mask. */ -#define AC_STATE_bp 4 /* Analog Comparator State bit position. */ - -/* ADC - Analog to Digital Converter */ -/* ADC.CTRLA bit masks and bit positions */ -#define ADC_ENABLE_bm 0x01 /* ADC Enable bit mask. */ -#define ADC_ENABLE_bp 0 /* ADC Enable bit position. */ -#define ADC_FREERUN_bm 0x02 /* ADC Freerun mode bit mask. */ -#define ADC_FREERUN_bp 1 /* ADC Freerun mode bit position. */ -#define ADC_RESSEL_bm 0x04 /* ADC Resolution bit mask. */ -#define ADC_RESSEL_bp 2 /* ADC Resolution bit position. */ -#define ADC_RUNSTBY_bm 0x80 /* Run standby mode bit mask. */ -#define ADC_RUNSTBY_bp 7 /* Run standby mode bit position. */ - -/* ADC.CTRLB bit masks and bit positions */ -#define ADC_SAMPNUM_gm 0x07 /* Accumulation Samples group mask. */ -#define ADC_SAMPNUM_gp 0 /* Accumulation Samples group position. */ -#define ADC_SAMPNUM0_bm (1<<0) /* Accumulation Samples bit 0 mask. */ -#define ADC_SAMPNUM0_bp 0 /* Accumulation Samples bit 0 position. */ -#define ADC_SAMPNUM1_bm (1<<1) /* Accumulation Samples bit 1 mask. */ -#define ADC_SAMPNUM1_bp 1 /* Accumulation Samples bit 1 position. */ -#define ADC_SAMPNUM2_bm (1<<2) /* Accumulation Samples bit 2 mask. */ -#define ADC_SAMPNUM2_bp 2 /* Accumulation Samples bit 2 position. */ - -/* ADC.CTRLC bit masks and bit positions */ -#define ADC_PRESC_gm 0x07 /* Clock Pre-scaler group mask. */ -#define ADC_PRESC_gp 0 /* Clock Pre-scaler group position. */ -#define ADC_PRESC0_bm (1<<0) /* Clock Pre-scaler bit 0 mask. */ -#define ADC_PRESC0_bp 0 /* Clock Pre-scaler bit 0 position. */ -#define ADC_PRESC1_bm (1<<1) /* Clock Pre-scaler bit 1 mask. */ -#define ADC_PRESC1_bp 1 /* Clock Pre-scaler bit 1 position. */ -#define ADC_PRESC2_bm (1<<2) /* Clock Pre-scaler bit 2 mask. */ -#define ADC_PRESC2_bp 2 /* Clock Pre-scaler bit 2 position. */ -#define ADC_REFSEL_gm 0x30 /* Reference Selection group mask. */ -#define ADC_REFSEL_gp 4 /* Reference Selection group position. */ -#define ADC_REFSEL0_bm (1<<4) /* Reference Selection bit 0 mask. */ -#define ADC_REFSEL0_bp 4 /* Reference Selection bit 0 position. */ -#define ADC_REFSEL1_bm (1<<5) /* Reference Selection bit 1 mask. */ -#define ADC_REFSEL1_bp 5 /* Reference Selection bit 1 position. */ -#define ADC_SAMPCAP_bm 0x40 /* Sample Capacitance Selection bit mask. */ -#define ADC_SAMPCAP_bp 6 /* Sample Capacitance Selection bit position. */ - -/* ADC.CTRLD bit masks and bit positions */ -#define ADC_SAMPDLY_gm 0x0F /* Sampling Delay Selection group mask. */ -#define ADC_SAMPDLY_gp 0 /* Sampling Delay Selection group position. */ -#define ADC_SAMPDLY0_bm (1<<0) /* Sampling Delay Selection bit 0 mask. */ -#define ADC_SAMPDLY0_bp 0 /* Sampling Delay Selection bit 0 position. */ -#define ADC_SAMPDLY1_bm (1<<1) /* Sampling Delay Selection bit 1 mask. */ -#define ADC_SAMPDLY1_bp 1 /* Sampling Delay Selection bit 1 position. */ -#define ADC_SAMPDLY2_bm (1<<2) /* Sampling Delay Selection bit 2 mask. */ -#define ADC_SAMPDLY2_bp 2 /* Sampling Delay Selection bit 2 position. */ -#define ADC_SAMPDLY3_bm (1<<3) /* Sampling Delay Selection bit 3 mask. */ -#define ADC_SAMPDLY3_bp 3 /* Sampling Delay Selection bit 3 position. */ -#define ADC_ASDV_bm 0x10 /* Automatic Sampling Delay Variation bit mask. */ -#define ADC_ASDV_bp 4 /* Automatic Sampling Delay Variation bit position. */ -#define ADC_INITDLY_gm 0xE0 /* Initial Delay Selection group mask. */ -#define ADC_INITDLY_gp 5 /* Initial Delay Selection group position. */ -#define ADC_INITDLY0_bm (1<<5) /* Initial Delay Selection bit 0 mask. */ -#define ADC_INITDLY0_bp 5 /* Initial Delay Selection bit 0 position. */ -#define ADC_INITDLY1_bm (1<<6) /* Initial Delay Selection bit 1 mask. */ -#define ADC_INITDLY1_bp 6 /* Initial Delay Selection bit 1 position. */ -#define ADC_INITDLY2_bm (1<<7) /* Initial Delay Selection bit 2 mask. */ -#define ADC_INITDLY2_bp 7 /* Initial Delay Selection bit 2 position. */ - -/* ADC.CTRLE bit masks and bit positions */ -#define ADC_WINCM_gm 0x07 /* Window Comparator Mode group mask. */ -#define ADC_WINCM_gp 0 /* Window Comparator Mode group position. */ -#define ADC_WINCM0_bm (1<<0) /* Window Comparator Mode bit 0 mask. */ -#define ADC_WINCM0_bp 0 /* Window Comparator Mode bit 0 position. */ -#define ADC_WINCM1_bm (1<<1) /* Window Comparator Mode bit 1 mask. */ -#define ADC_WINCM1_bp 1 /* Window Comparator Mode bit 1 position. */ -#define ADC_WINCM2_bm (1<<2) /* Window Comparator Mode bit 2 mask. */ -#define ADC_WINCM2_bp 2 /* Window Comparator Mode bit 2 position. */ - -/* ADC.SAMPCTRL bit masks and bit positions */ -#define ADC_SAMPLEN_gm 0x1F /* Sample lenght group mask. */ -#define ADC_SAMPLEN_gp 0 /* Sample lenght group position. */ -#define ADC_SAMPLEN0_bm (1<<0) /* Sample lenght bit 0 mask. */ -#define ADC_SAMPLEN0_bp 0 /* Sample lenght bit 0 position. */ -#define ADC_SAMPLEN1_bm (1<<1) /* Sample lenght bit 1 mask. */ -#define ADC_SAMPLEN1_bp 1 /* Sample lenght bit 1 position. */ -#define ADC_SAMPLEN2_bm (1<<2) /* Sample lenght bit 2 mask. */ -#define ADC_SAMPLEN2_bp 2 /* Sample lenght bit 2 position. */ -#define ADC_SAMPLEN3_bm (1<<3) /* Sample lenght bit 3 mask. */ -#define ADC_SAMPLEN3_bp 3 /* Sample lenght bit 3 position. */ -#define ADC_SAMPLEN4_bm (1<<4) /* Sample lenght bit 4 mask. */ -#define ADC_SAMPLEN4_bp 4 /* Sample lenght bit 4 position. */ - -/* ADC.MUXPOS bit masks and bit positions */ -#define ADC_MUXPOS_gm 0x1F /* Analog Channel Selection Bits group mask. */ -#define ADC_MUXPOS_gp 0 /* Analog Channel Selection Bits group position. */ -#define ADC_MUXPOS0_bm (1<<0) /* Analog Channel Selection Bits bit 0 mask. */ -#define ADC_MUXPOS0_bp 0 /* Analog Channel Selection Bits bit 0 position. */ -#define ADC_MUXPOS1_bm (1<<1) /* Analog Channel Selection Bits bit 1 mask. */ -#define ADC_MUXPOS1_bp 1 /* Analog Channel Selection Bits bit 1 position. */ -#define ADC_MUXPOS2_bm (1<<2) /* Analog Channel Selection Bits bit 2 mask. */ -#define ADC_MUXPOS2_bp 2 /* Analog Channel Selection Bits bit 2 position. */ -#define ADC_MUXPOS3_bm (1<<3) /* Analog Channel Selection Bits bit 3 mask. */ -#define ADC_MUXPOS3_bp 3 /* Analog Channel Selection Bits bit 3 position. */ -#define ADC_MUXPOS4_bm (1<<4) /* Analog Channel Selection Bits bit 4 mask. */ -#define ADC_MUXPOS4_bp 4 /* Analog Channel Selection Bits bit 4 position. */ - -/* ADC.COMMAND bit masks and bit positions */ -#define ADC_STCONV_bm 0x01 /* Start Conversion Operation bit mask. */ -#define ADC_STCONV_bp 0 /* Start Conversion Operation bit position. */ - -/* ADC.EVCTRL bit masks and bit positions */ -#define ADC_STARTEI_bm 0x01 /* Start Event Input Enable bit mask. */ -#define ADC_STARTEI_bp 0 /* Start Event Input Enable bit position. */ - -/* ADC.INTCTRL bit masks and bit positions */ -#define ADC_RESRDY_bm 0x01 /* Result Ready Interrupt Enable bit mask. */ -#define ADC_RESRDY_bp 0 /* Result Ready Interrupt Enable bit position. */ -#define ADC_WCMP_bm 0x02 /* Window Comparator Interrupt Enable bit mask. */ -#define ADC_WCMP_bp 1 /* Window Comparator Interrupt Enable bit position. */ - -/* ADC.INTFLAGS bit masks and bit positions */ -/* ADC_RESRDY is already defined. */ -/* ADC_WCMP is already defined. */ - -/* ADC.DBGCTRL bit masks and bit positions */ -#define ADC_DBGRUN_bm 0x01 /* Debug run bit mask. */ -#define ADC_DBGRUN_bp 0 /* Debug run bit position. */ - -/* ADC.TEMP bit masks and bit positions */ -#define ADC_TEMP_gm 0xFF /* Temporary group mask. */ -#define ADC_TEMP_gp 0 /* Temporary group position. */ -#define ADC_TEMP0_bm (1<<0) /* Temporary bit 0 mask. */ -#define ADC_TEMP0_bp 0 /* Temporary bit 0 position. */ -#define ADC_TEMP1_bm (1<<1) /* Temporary bit 1 mask. */ -#define ADC_TEMP1_bp 1 /* Temporary bit 1 position. */ -#define ADC_TEMP2_bm (1<<2) /* Temporary bit 2 mask. */ -#define ADC_TEMP2_bp 2 /* Temporary bit 2 position. */ -#define ADC_TEMP3_bm (1<<3) /* Temporary bit 3 mask. */ -#define ADC_TEMP3_bp 3 /* Temporary bit 3 position. */ -#define ADC_TEMP4_bm (1<<4) /* Temporary bit 4 mask. */ -#define ADC_TEMP4_bp 4 /* Temporary bit 4 position. */ -#define ADC_TEMP5_bm (1<<5) /* Temporary bit 5 mask. */ -#define ADC_TEMP5_bp 5 /* Temporary bit 5 position. */ -#define ADC_TEMP6_bm (1<<6) /* Temporary bit 6 mask. */ -#define ADC_TEMP6_bp 6 /* Temporary bit 6 position. */ -#define ADC_TEMP7_bm (1<<7) /* Temporary bit 7 mask. */ -#define ADC_TEMP7_bp 7 /* Temporary bit 7 position. */ - - - - -/* ADC.CALIB bit masks and bit positions */ -#define ADC_DUTYCYC_bm 0x01 /* Duty Cycle bit mask. */ -#define ADC_DUTYCYC_bp 0 /* Duty Cycle bit position. */ - -/* BOD - Bod interface */ -/* BOD.CTRLA bit masks and bit positions */ -#define BOD_SLEEP_gm 0x03 /* Operation in sleep mode group mask. */ -#define BOD_SLEEP_gp 0 /* Operation in sleep mode group position. */ -#define BOD_SLEEP0_bm (1<<0) /* Operation in sleep mode bit 0 mask. */ -#define BOD_SLEEP0_bp 0 /* Operation in sleep mode bit 0 position. */ -#define BOD_SLEEP1_bm (1<<1) /* Operation in sleep mode bit 1 mask. */ -#define BOD_SLEEP1_bp 1 /* Operation in sleep mode bit 1 position. */ -#define BOD_ACTIVE_gm 0x0C /* Operation in active mode group mask. */ -#define BOD_ACTIVE_gp 2 /* Operation in active mode group position. */ -#define BOD_ACTIVE0_bm (1<<2) /* Operation in active mode bit 0 mask. */ -#define BOD_ACTIVE0_bp 2 /* Operation in active mode bit 0 position. */ -#define BOD_ACTIVE1_bm (1<<3) /* Operation in active mode bit 1 mask. */ -#define BOD_ACTIVE1_bp 3 /* Operation in active mode bit 1 position. */ -#define BOD_SAMPFREQ_bm 0x10 /* Sample frequency bit mask. */ -#define BOD_SAMPFREQ_bp 4 /* Sample frequency bit position. */ - -/* BOD.CTRLB bit masks and bit positions */ -#define BOD_LVL_gm 0x07 /* Bod level group mask. */ -#define BOD_LVL_gp 0 /* Bod level group position. */ -#define BOD_LVL0_bm (1<<0) /* Bod level bit 0 mask. */ -#define BOD_LVL0_bp 0 /* Bod level bit 0 position. */ -#define BOD_LVL1_bm (1<<1) /* Bod level bit 1 mask. */ -#define BOD_LVL1_bp 1 /* Bod level bit 1 position. */ -#define BOD_LVL2_bm (1<<2) /* Bod level bit 2 mask. */ -#define BOD_LVL2_bp 2 /* Bod level bit 2 position. */ - -/* BOD.VLMCTRLA bit masks and bit positions */ -#define BOD_VLMLVL_gm 0x03 /* voltage level monitor level group mask. */ -#define BOD_VLMLVL_gp 0 /* voltage level monitor level group position. */ -#define BOD_VLMLVL0_bm (1<<0) /* voltage level monitor level bit 0 mask. */ -#define BOD_VLMLVL0_bp 0 /* voltage level monitor level bit 0 position. */ -#define BOD_VLMLVL1_bm (1<<1) /* voltage level monitor level bit 1 mask. */ -#define BOD_VLMLVL1_bp 1 /* voltage level monitor level bit 1 position. */ - -/* BOD.INTCTRL bit masks and bit positions */ -#define BOD_VLMIE_bm 0x01 /* voltage level monitor interrrupt enable bit mask. */ -#define BOD_VLMIE_bp 0 /* voltage level monitor interrrupt enable bit position. */ -#define BOD_VLMCFG_gm 0x06 /* Configuration group mask. */ -#define BOD_VLMCFG_gp 1 /* Configuration group position. */ -#define BOD_VLMCFG0_bm (1<<1) /* Configuration bit 0 mask. */ -#define BOD_VLMCFG0_bp 1 /* Configuration bit 0 position. */ -#define BOD_VLMCFG1_bm (1<<2) /* Configuration bit 1 mask. */ -#define BOD_VLMCFG1_bp 2 /* Configuration bit 1 position. */ - -/* BOD.INTFLAGS bit masks and bit positions */ -#define BOD_VLMIF_bm 0x01 /* Voltage level monitor interrupt flag bit mask. */ -#define BOD_VLMIF_bp 0 /* Voltage level monitor interrupt flag bit position. */ - -/* BOD.STATUS bit masks and bit positions */ -#define BOD_VLMS_bm 0x01 /* Voltage level monitor status bit mask. */ -#define BOD_VLMS_bp 0 /* Voltage level monitor status bit position. */ - -/* CCL - Configurable Custom Logic */ -/* CCL.CTRLA bit masks and bit positions */ -#define CCL_ENABLE_bm 0x01 /* Enable bit mask. */ -#define CCL_ENABLE_bp 0 /* Enable bit position. */ -#define CCL_RUNSTDBY_bm 0x40 /* Run in Standby bit mask. */ -#define CCL_RUNSTDBY_bp 6 /* Run in Standby bit position. */ - -/* CCL.SEQCTRL0 bit masks and bit positions */ -#define CCL_SEQSEL_gm 0x07 /* Sequential Selection group mask. */ -#define CCL_SEQSEL_gp 0 /* Sequential Selection group position. */ -#define CCL_SEQSEL0_bm (1<<0) /* Sequential Selection bit 0 mask. */ -#define CCL_SEQSEL0_bp 0 /* Sequential Selection bit 0 position. */ -#define CCL_SEQSEL1_bm (1<<1) /* Sequential Selection bit 1 mask. */ -#define CCL_SEQSEL1_bp 1 /* Sequential Selection bit 1 position. */ -#define CCL_SEQSEL2_bm (1<<2) /* Sequential Selection bit 2 mask. */ -#define CCL_SEQSEL2_bp 2 /* Sequential Selection bit 2 position. */ - -/* CCL.INTCTRL0 bit masks and bit positions */ -#define CCL_INTMODE0_gm 0x03 /* Interrupt Mode for LUT0 group mask. */ -#define CCL_INTMODE0_gp 0 /* Interrupt Mode for LUT0 group position. */ -#define CCL_INTMODE00_bm (1<<0) /* Interrupt Mode for LUT0 bit 0 mask. */ -#define CCL_INTMODE00_bp 0 /* Interrupt Mode for LUT0 bit 0 position. */ -#define CCL_INTMODE01_bm (1<<1) /* Interrupt Mode for LUT0 bit 1 mask. */ -#define CCL_INTMODE01_bp 1 /* Interrupt Mode for LUT0 bit 1 position. */ -#define CCL_INTMODE1_gm 0x0C /* Interrupt Mode for LUT1 group mask. */ -#define CCL_INTMODE1_gp 2 /* Interrupt Mode for LUT1 group position. */ -#define CCL_INTMODE10_bm (1<<2) /* Interrupt Mode for LUT1 bit 0 mask. */ -#define CCL_INTMODE10_bp 2 /* Interrupt Mode for LUT1 bit 0 position. */ -#define CCL_INTMODE11_bm (1<<3) /* Interrupt Mode for LUT1 bit 1 mask. */ -#define CCL_INTMODE11_bp 3 /* Interrupt Mode for LUT1 bit 1 position. */ -#define CCL_INTMODE2_gm 0x30 /* Interrupt Mode for LUT2 group mask. */ -#define CCL_INTMODE2_gp 4 /* Interrupt Mode for LUT2 group position. */ -#define CCL_INTMODE20_bm (1<<4) /* Interrupt Mode for LUT2 bit 0 mask. */ -#define CCL_INTMODE20_bp 4 /* Interrupt Mode for LUT2 bit 0 position. */ -#define CCL_INTMODE21_bm (1<<5) /* Interrupt Mode for LUT2 bit 1 mask. */ -#define CCL_INTMODE21_bp 5 /* Interrupt Mode for LUT2 bit 1 position. */ -#define CCL_INTMODE3_gm 0xC0 /* Interrupt Mode for LUT3 group mask. */ -#define CCL_INTMODE3_gp 6 /* Interrupt Mode for LUT3 group position. */ -#define CCL_INTMODE30_bm (1<<6) /* Interrupt Mode for LUT3 bit 0 mask. */ -#define CCL_INTMODE30_bp 6 /* Interrupt Mode for LUT3 bit 0 position. */ -#define CCL_INTMODE31_bm (1<<7) /* Interrupt Mode for LUT3 bit 1 mask. */ -#define CCL_INTMODE31_bp 7 /* Interrupt Mode for LUT3 bit 1 position. */ - -/* CCL.INTFLAGS bit masks and bit positions */ -#define CCL_INT_gm 0x0F /* Interrupt Flags group mask. */ -#define CCL_INT_gp 0 /* Interrupt Flags group position. */ -#define CCL_INT0_bm (1<<0) /* Interrupt Flags bit 0 mask. */ -#define CCL_INT0_bp 0 /* Interrupt Flags bit 0 position. */ -#define CCL_INT1_bm (1<<1) /* Interrupt Flags bit 1 mask. */ -#define CCL_INT1_bp 1 /* Interrupt Flags bit 1 position. */ -#define CCL_INT2_bm (1<<2) /* Interrupt Flags bit 2 mask. */ -#define CCL_INT2_bp 2 /* Interrupt Flags bit 2 position. */ -#define CCL_INT3_bm (1<<3) /* Interrupt Flags bit 3 mask. */ -#define CCL_INT3_bp 3 /* Interrupt Flags bit 3 position. */ - -/* CCL.LUT0CTRLA bit masks and bit positions */ -/* CCL_ENABLE is already defined. */ -#define CCL_CLKSRC_gm 0x0E /* Clock Source Selection group mask. */ -#define CCL_CLKSRC_gp 1 /* Clock Source Selection group position. */ -#define CCL_CLKSRC0_bm (1<<1) /* Clock Source Selection bit 0 mask. */ -#define CCL_CLKSRC0_bp 1 /* Clock Source Selection bit 0 position. */ -#define CCL_CLKSRC1_bm (1<<2) /* Clock Source Selection bit 1 mask. */ -#define CCL_CLKSRC1_bp 2 /* Clock Source Selection bit 1 position. */ -#define CCL_CLKSRC2_bm (1<<3) /* Clock Source Selection bit 2 mask. */ -#define CCL_CLKSRC2_bp 3 /* Clock Source Selection bit 2 position. */ -#define CCL_FILTSEL_gm 0x30 /* Filter Selection group mask. */ -#define CCL_FILTSEL_gp 4 /* Filter Selection group position. */ -#define CCL_FILTSEL0_bm (1<<4) /* Filter Selection bit 0 mask. */ -#define CCL_FILTSEL0_bp 4 /* Filter Selection bit 0 position. */ -#define CCL_FILTSEL1_bm (1<<5) /* Filter Selection bit 1 mask. */ -#define CCL_FILTSEL1_bp 5 /* Filter Selection bit 1 position. */ -#define CCL_OUTEN_bm 0x40 /* Output Enable bit mask. */ -#define CCL_OUTEN_bp 6 /* Output Enable bit position. */ -#define CCL_EDGEDET_bm 0x80 /* Edge Detection Enable bit mask. */ -#define CCL_EDGEDET_bp 7 /* Edge Detection Enable bit position. */ - -/* CCL.LUT0CTRLB bit masks and bit positions */ -#define CCL_INSEL0_gm 0x0F /* LUT Input 0 Source Selection group mask. */ -#define CCL_INSEL0_gp 0 /* LUT Input 0 Source Selection group position. */ -#define CCL_INSEL00_bm (1<<0) /* LUT Input 0 Source Selection bit 0 mask. */ -#define CCL_INSEL00_bp 0 /* LUT Input 0 Source Selection bit 0 position. */ -#define CCL_INSEL01_bm (1<<1) /* LUT Input 0 Source Selection bit 1 mask. */ -#define CCL_INSEL01_bp 1 /* LUT Input 0 Source Selection bit 1 position. */ -#define CCL_INSEL02_bm (1<<2) /* LUT Input 0 Source Selection bit 2 mask. */ -#define CCL_INSEL02_bp 2 /* LUT Input 0 Source Selection bit 2 position. */ -#define CCL_INSEL03_bm (1<<3) /* LUT Input 0 Source Selection bit 3 mask. */ -#define CCL_INSEL03_bp 3 /* LUT Input 0 Source Selection bit 3 position. */ -#define CCL_INSEL1_gm 0xF0 /* LUT Input 1 Source Selection group mask. */ -#define CCL_INSEL1_gp 4 /* LUT Input 1 Source Selection group position. */ -#define CCL_INSEL10_bm (1<<4) /* LUT Input 1 Source Selection bit 0 mask. */ -#define CCL_INSEL10_bp 4 /* LUT Input 1 Source Selection bit 0 position. */ -#define CCL_INSEL11_bm (1<<5) /* LUT Input 1 Source Selection bit 1 mask. */ -#define CCL_INSEL11_bp 5 /* LUT Input 1 Source Selection bit 1 position. */ -#define CCL_INSEL12_bm (1<<6) /* LUT Input 1 Source Selection bit 2 mask. */ -#define CCL_INSEL12_bp 6 /* LUT Input 1 Source Selection bit 2 position. */ -#define CCL_INSEL13_bm (1<<7) /* LUT Input 1 Source Selection bit 3 mask. */ -#define CCL_INSEL13_bp 7 /* LUT Input 1 Source Selection bit 3 position. */ - -/* CCL.LUT0CTRLC bit masks and bit positions */ -#define CCL_INSEL2_gm 0x0F /* LUT Input 2 Source Selection group mask. */ -#define CCL_INSEL2_gp 0 /* LUT Input 2 Source Selection group position. */ -#define CCL_INSEL20_bm (1<<0) /* LUT Input 2 Source Selection bit 0 mask. */ -#define CCL_INSEL20_bp 0 /* LUT Input 2 Source Selection bit 0 position. */ -#define CCL_INSEL21_bm (1<<1) /* LUT Input 2 Source Selection bit 1 mask. */ -#define CCL_INSEL21_bp 1 /* LUT Input 2 Source Selection bit 1 position. */ -#define CCL_INSEL22_bm (1<<2) /* LUT Input 2 Source Selection bit 2 mask. */ -#define CCL_INSEL22_bp 2 /* LUT Input 2 Source Selection bit 2 position. */ -#define CCL_INSEL23_bm (1<<3) /* LUT Input 2 Source Selection bit 3 mask. */ -#define CCL_INSEL23_bp 3 /* LUT Input 2 Source Selection bit 3 position. */ - - -/* CCL.LUT1CTRLA bit masks and bit positions */ -/* CCL_ENABLE is already defined. */ -/* CCL_CLKSRC is already defined. */ -/* CCL_FILTSEL is already defined. */ -/* CCL_OUTEN is already defined. */ -/* CCL_EDGEDET is already defined. */ - -/* CCL.LUT1CTRLB bit masks and bit positions */ -/* CCL_INSEL0 is already defined. */ -/* CCL_INSEL1 is already defined. */ - -/* CCL.LUT1CTRLC bit masks and bit positions */ -/* CCL_INSEL2 is already defined. */ - - -/* CCL.LUT2CTRLA bit masks and bit positions */ -/* CCL_ENABLE is already defined. */ -/* CCL_CLKSRC is already defined. */ -/* CCL_FILTSEL is already defined. */ -/* CCL_OUTEN is already defined. */ -/* CCL_EDGEDET is already defined. */ - -/* CCL.LUT2CTRLB bit masks and bit positions */ -/* CCL_INSEL0 is already defined. */ -/* CCL_INSEL1 is already defined. */ - -/* CCL.LUT2CTRLC bit masks and bit positions */ -/* CCL_INSEL2 is already defined. */ - - -/* CCL.LUT3CTRLA bit masks and bit positions */ -/* CCL_ENABLE is already defined. */ -/* CCL_CLKSRC is already defined. */ -/* CCL_FILTSEL is already defined. */ -/* CCL_OUTEN is already defined. */ -/* CCL_EDGEDET is already defined. */ - -/* CCL.LUT3CTRLB bit masks and bit positions */ -/* CCL_INSEL0 is already defined. */ -/* CCL_INSEL1 is already defined. */ - -/* CCL.LUT3CTRLC bit masks and bit positions */ -/* CCL_INSEL2 is already defined. */ - - -/* CLKCTRL - Clock controller */ -/* CLKCTRL.MCLKCTRLA bit masks and bit positions */ -#define CLKCTRL_CLKSEL_gm 0x03 /* clock select group mask. */ -#define CLKCTRL_CLKSEL_gp 0 /* clock select group position. */ -#define CLKCTRL_CLKSEL0_bm (1<<0) /* clock select bit 0 mask. */ -#define CLKCTRL_CLKSEL0_bp 0 /* clock select bit 0 position. */ -#define CLKCTRL_CLKSEL1_bm (1<<1) /* clock select bit 1 mask. */ -#define CLKCTRL_CLKSEL1_bp 1 /* clock select bit 1 position. */ -#define CLKCTRL_CLKOUT_bm 0x80 /* System clock out bit mask. */ -#define CLKCTRL_CLKOUT_bp 7 /* System clock out bit position. */ - -/* CLKCTRL.MCLKCTRLB bit masks and bit positions */ -#define CLKCTRL_PEN_bm 0x01 /* Prescaler enable bit mask. */ -#define CLKCTRL_PEN_bp 0 /* Prescaler enable bit position. */ -#define CLKCTRL_PDIV_gm 0x1E /* Prescaler division group mask. */ -#define CLKCTRL_PDIV_gp 1 /* Prescaler division group position. */ -#define CLKCTRL_PDIV0_bm (1<<1) /* Prescaler division bit 0 mask. */ -#define CLKCTRL_PDIV0_bp 1 /* Prescaler division bit 0 position. */ -#define CLKCTRL_PDIV1_bm (1<<2) /* Prescaler division bit 1 mask. */ -#define CLKCTRL_PDIV1_bp 2 /* Prescaler division bit 1 position. */ -#define CLKCTRL_PDIV2_bm (1<<3) /* Prescaler division bit 2 mask. */ -#define CLKCTRL_PDIV2_bp 3 /* Prescaler division bit 2 position. */ -#define CLKCTRL_PDIV3_bm (1<<4) /* Prescaler division bit 3 mask. */ -#define CLKCTRL_PDIV3_bp 4 /* Prescaler division bit 3 position. */ - -/* CLKCTRL.MCLKLOCK bit masks and bit positions */ -#define CLKCTRL_LOCKEN_bm 0x01 /* lock ebable bit mask. */ -#define CLKCTRL_LOCKEN_bp 0 /* lock ebable bit position. */ - -/* CLKCTRL.MCLKSTATUS bit masks and bit positions */ -#define CLKCTRL_SOSC_bm 0x01 /* System Oscillator changing bit mask. */ -#define CLKCTRL_SOSC_bp 0 /* System Oscillator changing bit position. */ -#define CLKCTRL_OSC20MS_bm 0x10 /* 20MHz oscillator status bit mask. */ -#define CLKCTRL_OSC20MS_bp 4 /* 20MHz oscillator status bit position. */ -#define CLKCTRL_OSC32KS_bm 0x20 /* 32KHz oscillator status bit mask. */ -#define CLKCTRL_OSC32KS_bp 5 /* 32KHz oscillator status bit position. */ -#define CLKCTRL_XOSC32KS_bm 0x40 /* 32.768 kHz Crystal Oscillator status bit mask. */ -#define CLKCTRL_XOSC32KS_bp 6 /* 32.768 kHz Crystal Oscillator status bit position. */ -#define CLKCTRL_EXTS_bm 0x80 /* External Clock status bit mask. */ -#define CLKCTRL_EXTS_bp 7 /* External Clock status bit position. */ - -/* CLKCTRL.OSC20MCTRLA bit masks and bit positions */ -#define CLKCTRL_RUNSTDBY_bm 0x02 /* Run standby bit mask. */ -#define CLKCTRL_RUNSTDBY_bp 1 /* Run standby bit position. */ - -/* CLKCTRL.OSC20MCALIBA bit masks and bit positions */ -#define CLKCTRL_CAL20M_gm 0x7F /* Calibration group mask. */ -#define CLKCTRL_CAL20M_gp 0 /* Calibration group position. */ -#define CLKCTRL_CAL20M0_bm (1<<0) /* Calibration bit 0 mask. */ -#define CLKCTRL_CAL20M0_bp 0 /* Calibration bit 0 position. */ -#define CLKCTRL_CAL20M1_bm (1<<1) /* Calibration bit 1 mask. */ -#define CLKCTRL_CAL20M1_bp 1 /* Calibration bit 1 position. */ -#define CLKCTRL_CAL20M2_bm (1<<2) /* Calibration bit 2 mask. */ -#define CLKCTRL_CAL20M2_bp 2 /* Calibration bit 2 position. */ -#define CLKCTRL_CAL20M3_bm (1<<3) /* Calibration bit 3 mask. */ -#define CLKCTRL_CAL20M3_bp 3 /* Calibration bit 3 position. */ -#define CLKCTRL_CAL20M4_bm (1<<4) /* Calibration bit 4 mask. */ -#define CLKCTRL_CAL20M4_bp 4 /* Calibration bit 4 position. */ -#define CLKCTRL_CAL20M5_bm (1<<5) /* Calibration bit 5 mask. */ -#define CLKCTRL_CAL20M5_bp 5 /* Calibration bit 5 position. */ -#define CLKCTRL_CAL20M6_bm (1<<6) /* Calibration bit 6 mask. */ -#define CLKCTRL_CAL20M6_bp 6 /* Calibration bit 6 position. */ -#define CLKCTRL_CALSEL20M_bm 0x80 /* Calibration freq select bit mask. */ -#define CLKCTRL_CALSEL20M_bp 7 /* Calibration freq select bit position. */ - -/* CLKCTRL.OSC20MCALIBB bit masks and bit positions */ -#define CLKCTRL_TEMPCAL20M_gm 0x0F /* Oscillator temperature coefficient group mask. */ -#define CLKCTRL_TEMPCAL20M_gp 0 /* Oscillator temperature coefficient group position. */ -#define CLKCTRL_TEMPCAL20M0_bm (1<<0) /* Oscillator temperature coefficient bit 0 mask. */ -#define CLKCTRL_TEMPCAL20M0_bp 0 /* Oscillator temperature coefficient bit 0 position. */ -#define CLKCTRL_TEMPCAL20M1_bm (1<<1) /* Oscillator temperature coefficient bit 1 mask. */ -#define CLKCTRL_TEMPCAL20M1_bp 1 /* Oscillator temperature coefficient bit 1 position. */ -#define CLKCTRL_TEMPCAL20M2_bm (1<<2) /* Oscillator temperature coefficient bit 2 mask. */ -#define CLKCTRL_TEMPCAL20M2_bp 2 /* Oscillator temperature coefficient bit 2 position. */ -#define CLKCTRL_TEMPCAL20M3_bm (1<<3) /* Oscillator temperature coefficient bit 3 mask. */ -#define CLKCTRL_TEMPCAL20M3_bp 3 /* Oscillator temperature coefficient bit 3 position. */ -#define CLKCTRL_LOCK_bm 0x80 /* Lock bit mask. */ -#define CLKCTRL_LOCK_bp 7 /* Lock bit position. */ - -/* CLKCTRL.OSC32KCTRLA bit masks and bit positions */ -/* CLKCTRL_RUNSTDBY is already defined. */ - -/* CLKCTRL.OSC32KCALIB bit masks and bit positions */ -#define CLKCTRL_CAL32K_gm 0x3F /* Calibration group mask. */ -#define CLKCTRL_CAL32K_gp 0 /* Calibration group position. */ -#define CLKCTRL_CAL32K0_bm (1<<0) /* Calibration bit 0 mask. */ -#define CLKCTRL_CAL32K0_bp 0 /* Calibration bit 0 position. */ -#define CLKCTRL_CAL32K1_bm (1<<1) /* Calibration bit 1 mask. */ -#define CLKCTRL_CAL32K1_bp 1 /* Calibration bit 1 position. */ -#define CLKCTRL_CAL32K2_bm (1<<2) /* Calibration bit 2 mask. */ -#define CLKCTRL_CAL32K2_bp 2 /* Calibration bit 2 position. */ -#define CLKCTRL_CAL32K3_bm (1<<3) /* Calibration bit 3 mask. */ -#define CLKCTRL_CAL32K3_bp 3 /* Calibration bit 3 position. */ -#define CLKCTRL_CAL32K4_bm (1<<4) /* Calibration bit 4 mask. */ -#define CLKCTRL_CAL32K4_bp 4 /* Calibration bit 4 position. */ -#define CLKCTRL_CAL32K5_bm (1<<5) /* Calibration bit 5 mask. */ -#define CLKCTRL_CAL32K5_bp 5 /* Calibration bit 5 position. */ - -/* CLKCTRL.XOSC32KCTRLA bit masks and bit positions */ -#define CLKCTRL_ENABLE_bm 0x01 /* Enable bit mask. */ -#define CLKCTRL_ENABLE_bp 0 /* Enable bit position. */ -/* CLKCTRL_RUNSTDBY is already defined. */ -#define CLKCTRL_SEL_bm 0x04 /* Select bit mask. */ -#define CLKCTRL_SEL_bp 2 /* Select bit position. */ -#define CLKCTRL_CSUT_gm 0x30 /* Crystal startup time group mask. */ -#define CLKCTRL_CSUT_gp 4 /* Crystal startup time group position. */ -#define CLKCTRL_CSUT0_bm (1<<4) /* Crystal startup time bit 0 mask. */ -#define CLKCTRL_CSUT0_bp 4 /* Crystal startup time bit 0 position. */ -#define CLKCTRL_CSUT1_bm (1<<5) /* Crystal startup time bit 1 mask. */ -#define CLKCTRL_CSUT1_bp 5 /* Crystal startup time bit 1 position. */ - -/* CPU - CPU */ -/* CPU.CCP bit masks and bit positions */ -#define CPU_CCP_gm 0xFF /* CCP signature group mask. */ -#define CPU_CCP_gp 0 /* CCP signature group position. */ -#define CPU_CCP0_bm (1<<0) /* CCP signature bit 0 mask. */ -#define CPU_CCP0_bp 0 /* CCP signature bit 0 position. */ -#define CPU_CCP1_bm (1<<1) /* CCP signature bit 1 mask. */ -#define CPU_CCP1_bp 1 /* CCP signature bit 1 position. */ -#define CPU_CCP2_bm (1<<2) /* CCP signature bit 2 mask. */ -#define CPU_CCP2_bp 2 /* CCP signature bit 2 position. */ -#define CPU_CCP3_bm (1<<3) /* CCP signature bit 3 mask. */ -#define CPU_CCP3_bp 3 /* CCP signature bit 3 position. */ -#define CPU_CCP4_bm (1<<4) /* CCP signature bit 4 mask. */ -#define CPU_CCP4_bp 4 /* CCP signature bit 4 position. */ -#define CPU_CCP5_bm (1<<5) /* CCP signature bit 5 mask. */ -#define CPU_CCP5_bp 5 /* CCP signature bit 5 position. */ -#define CPU_CCP6_bm (1<<6) /* CCP signature bit 6 mask. */ -#define CPU_CCP6_bp 6 /* CCP signature bit 6 position. */ -#define CPU_CCP7_bm (1<<7) /* CCP signature bit 7 mask. */ -#define CPU_CCP7_bp 7 /* CCP signature bit 7 position. */ - - - - -/* CPU.SREG bit masks and bit positions */ -#define CPU_C_bm 0x01 /* Carry Flag bit mask. */ -#define CPU_C_bp 0 /* Carry Flag bit position. */ -#define CPU_Z_bm 0x02 /* Zero Flag bit mask. */ -#define CPU_Z_bp 1 /* Zero Flag bit position. */ -#define CPU_N_bm 0x04 /* Negative Flag bit mask. */ -#define CPU_N_bp 2 /* Negative Flag bit position. */ -#define CPU_V_bm 0x08 /* Two's Complement Overflow Flag bit mask. */ -#define CPU_V_bp 3 /* Two's Complement Overflow Flag bit position. */ -#define CPU_S_bm 0x10 /* N Exclusive Or V Flag bit mask. */ -#define CPU_S_bp 4 /* N Exclusive Or V Flag bit position. */ -#define CPU_H_bm 0x20 /* Half Carry Flag bit mask. */ -#define CPU_H_bp 5 /* Half Carry Flag bit position. */ -#define CPU_T_bm 0x40 /* Transfer Bit bit mask. */ -#define CPU_T_bp 6 /* Transfer Bit bit position. */ -#define CPU_I_bm 0x80 /* Global Interrupt Enable Flag bit mask. */ -#define CPU_I_bp 7 /* Global Interrupt Enable Flag bit position. */ - -/* CPUINT - Interrupt Controller */ -/* CPUINT.CTRLA bit masks and bit positions */ -#define CPUINT_LVL0RR_bm 0x01 /* Round-robin Scheduling Enable bit mask. */ -#define CPUINT_LVL0RR_bp 0 /* Round-robin Scheduling Enable bit position. */ -#define CPUINT_CVT_bm 0x20 /* Compact Vector Table bit mask. */ -#define CPUINT_CVT_bp 5 /* Compact Vector Table bit position. */ -#define CPUINT_IVSEL_bm 0x40 /* Interrupt Vector Select bit mask. */ -#define CPUINT_IVSEL_bp 6 /* Interrupt Vector Select bit position. */ - -/* CPUINT.STATUS bit masks and bit positions */ -#define CPUINT_LVL0EX_bm 0x01 /* Level 0 Interrupt Executing bit mask. */ -#define CPUINT_LVL0EX_bp 0 /* Level 0 Interrupt Executing bit position. */ -#define CPUINT_LVL1EX_bm 0x02 /* Level 1 Interrupt Executing bit mask. */ -#define CPUINT_LVL1EX_bp 1 /* Level 1 Interrupt Executing bit position. */ -#define CPUINT_NMIEX_bm 0x80 /* Non-maskable Interrupt Executing bit mask. */ -#define CPUINT_NMIEX_bp 7 /* Non-maskable Interrupt Executing bit position. */ - -/* CPUINT.LVL0PRI bit masks and bit positions */ -#define CPUINT_LVL0PRI_gm 0xFF /* Interrupt Level Priority group mask. */ -#define CPUINT_LVL0PRI_gp 0 /* Interrupt Level Priority group position. */ -#define CPUINT_LVL0PRI0_bm (1<<0) /* Interrupt Level Priority bit 0 mask. */ -#define CPUINT_LVL0PRI0_bp 0 /* Interrupt Level Priority bit 0 position. */ -#define CPUINT_LVL0PRI1_bm (1<<1) /* Interrupt Level Priority bit 1 mask. */ -#define CPUINT_LVL0PRI1_bp 1 /* Interrupt Level Priority bit 1 position. */ -#define CPUINT_LVL0PRI2_bm (1<<2) /* Interrupt Level Priority bit 2 mask. */ -#define CPUINT_LVL0PRI2_bp 2 /* Interrupt Level Priority bit 2 position. */ -#define CPUINT_LVL0PRI3_bm (1<<3) /* Interrupt Level Priority bit 3 mask. */ -#define CPUINT_LVL0PRI3_bp 3 /* Interrupt Level Priority bit 3 position. */ -#define CPUINT_LVL0PRI4_bm (1<<4) /* Interrupt Level Priority bit 4 mask. */ -#define CPUINT_LVL0PRI4_bp 4 /* Interrupt Level Priority bit 4 position. */ -#define CPUINT_LVL0PRI5_bm (1<<5) /* Interrupt Level Priority bit 5 mask. */ -#define CPUINT_LVL0PRI5_bp 5 /* Interrupt Level Priority bit 5 position. */ -#define CPUINT_LVL0PRI6_bm (1<<6) /* Interrupt Level Priority bit 6 mask. */ -#define CPUINT_LVL0PRI6_bp 6 /* Interrupt Level Priority bit 6 position. */ -#define CPUINT_LVL0PRI7_bm (1<<7) /* Interrupt Level Priority bit 7 mask. */ -#define CPUINT_LVL0PRI7_bp 7 /* Interrupt Level Priority bit 7 position. */ - -/* CPUINT.LVL1VEC bit masks and bit positions */ -#define CPUINT_LVL1VEC_gm 0xFF /* Interrupt Vector with High Priority group mask. */ -#define CPUINT_LVL1VEC_gp 0 /* Interrupt Vector with High Priority group position. */ -#define CPUINT_LVL1VEC0_bm (1<<0) /* Interrupt Vector with High Priority bit 0 mask. */ -#define CPUINT_LVL1VEC0_bp 0 /* Interrupt Vector with High Priority bit 0 position. */ -#define CPUINT_LVL1VEC1_bm (1<<1) /* Interrupt Vector with High Priority bit 1 mask. */ -#define CPUINT_LVL1VEC1_bp 1 /* Interrupt Vector with High Priority bit 1 position. */ -#define CPUINT_LVL1VEC2_bm (1<<2) /* Interrupt Vector with High Priority bit 2 mask. */ -#define CPUINT_LVL1VEC2_bp 2 /* Interrupt Vector with High Priority bit 2 position. */ -#define CPUINT_LVL1VEC3_bm (1<<3) /* Interrupt Vector with High Priority bit 3 mask. */ -#define CPUINT_LVL1VEC3_bp 3 /* Interrupt Vector with High Priority bit 3 position. */ -#define CPUINT_LVL1VEC4_bm (1<<4) /* Interrupt Vector with High Priority bit 4 mask. */ -#define CPUINT_LVL1VEC4_bp 4 /* Interrupt Vector with High Priority bit 4 position. */ -#define CPUINT_LVL1VEC5_bm (1<<5) /* Interrupt Vector with High Priority bit 5 mask. */ -#define CPUINT_LVL1VEC5_bp 5 /* Interrupt Vector with High Priority bit 5 position. */ -#define CPUINT_LVL1VEC6_bm (1<<6) /* Interrupt Vector with High Priority bit 6 mask. */ -#define CPUINT_LVL1VEC6_bp 6 /* Interrupt Vector with High Priority bit 6 position. */ -#define CPUINT_LVL1VEC7_bm (1<<7) /* Interrupt Vector with High Priority bit 7 mask. */ -#define CPUINT_LVL1VEC7_bp 7 /* Interrupt Vector with High Priority bit 7 position. */ - -/* CRCSCAN - CRCSCAN */ -/* CRCSCAN.CTRLA bit masks and bit positions */ -#define CRCSCAN_ENABLE_bm 0x01 /* Enable CRC scan bit mask. */ -#define CRCSCAN_ENABLE_bp 0 /* Enable CRC scan bit position. */ -#define CRCSCAN_NMIEN_bm 0x02 /* Enable NMI Trigger bit mask. */ -#define CRCSCAN_NMIEN_bp 1 /* Enable NMI Trigger bit position. */ -#define CRCSCAN_RESET_bm 0x80 /* Reset CRC scan bit mask. */ -#define CRCSCAN_RESET_bp 7 /* Reset CRC scan bit position. */ - -/* CRCSCAN.CTRLB bit masks and bit positions */ -#define CRCSCAN_SRC_gm 0x03 /* CRC Source group mask. */ -#define CRCSCAN_SRC_gp 0 /* CRC Source group position. */ -#define CRCSCAN_SRC0_bm (1<<0) /* CRC Source bit 0 mask. */ -#define CRCSCAN_SRC0_bp 0 /* CRC Source bit 0 position. */ -#define CRCSCAN_SRC1_bm (1<<1) /* CRC Source bit 1 mask. */ -#define CRCSCAN_SRC1_bp 1 /* CRC Source bit 1 position. */ -#define CRCSCAN_MODE_gm 0x30 /* CRC Flash Access Mode group mask. */ -#define CRCSCAN_MODE_gp 4 /* CRC Flash Access Mode group position. */ -#define CRCSCAN_MODE0_bm (1<<4) /* CRC Flash Access Mode bit 0 mask. */ -#define CRCSCAN_MODE0_bp 4 /* CRC Flash Access Mode bit 0 position. */ -#define CRCSCAN_MODE1_bm (1<<5) /* CRC Flash Access Mode bit 1 mask. */ -#define CRCSCAN_MODE1_bp 5 /* CRC Flash Access Mode bit 1 position. */ - -/* CRCSCAN.STATUS bit masks and bit positions */ -#define CRCSCAN_BUSY_bm 0x01 /* CRC Busy bit mask. */ -#define CRCSCAN_BUSY_bp 0 /* CRC Busy bit position. */ -#define CRCSCAN_OK_bm 0x02 /* CRC Ok bit mask. */ -#define CRCSCAN_OK_bp 1 /* CRC Ok bit position. */ - -/* EVSYS - Event System */ -/* EVSYS.STROBE bit masks and bit positions */ -#define EVSYS_STROBE0_gm 0xFF /* Software event on channels group mask. */ -#define EVSYS_STROBE0_gp 0 /* Software event on channels group position. */ -#define EVSYS_STROBE00_bm (1<<0) /* Software event on channels bit 0 mask. */ -#define EVSYS_STROBE00_bp 0 /* Software event on channels bit 0 position. */ -#define EVSYS_STROBE01_bm (1<<1) /* Software event on channels bit 1 mask. */ -#define EVSYS_STROBE01_bp 1 /* Software event on channels bit 1 position. */ -#define EVSYS_STROBE02_bm (1<<2) /* Software event on channels bit 2 mask. */ -#define EVSYS_STROBE02_bp 2 /* Software event on channels bit 2 position. */ -#define EVSYS_STROBE03_bm (1<<3) /* Software event on channels bit 3 mask. */ -#define EVSYS_STROBE03_bp 3 /* Software event on channels bit 3 position. */ -#define EVSYS_STROBE04_bm (1<<4) /* Software event on channels bit 4 mask. */ -#define EVSYS_STROBE04_bp 4 /* Software event on channels bit 4 position. */ -#define EVSYS_STROBE05_bm (1<<5) /* Software event on channels bit 5 mask. */ -#define EVSYS_STROBE05_bp 5 /* Software event on channels bit 5 position. */ -#define EVSYS_STROBE06_bm (1<<6) /* Software event on channels bit 6 mask. */ -#define EVSYS_STROBE06_bp 6 /* Software event on channels bit 6 position. */ -#define EVSYS_STROBE07_bm (1<<7) /* Software event on channels bit 7 mask. */ -#define EVSYS_STROBE07_bp 7 /* Software event on channels bit 7 position. */ - -/* EVSYS.CHANNEL0 bit masks and bit positions */ -#define EVSYS_GENERATOR_gm 0xFF /* Generator selector group mask. */ -#define EVSYS_GENERATOR_gp 0 /* Generator selector group position. */ -#define EVSYS_GENERATOR0_bm (1<<0) /* Generator selector bit 0 mask. */ -#define EVSYS_GENERATOR0_bp 0 /* Generator selector bit 0 position. */ -#define EVSYS_GENERATOR1_bm (1<<1) /* Generator selector bit 1 mask. */ -#define EVSYS_GENERATOR1_bp 1 /* Generator selector bit 1 position. */ -#define EVSYS_GENERATOR2_bm (1<<2) /* Generator selector bit 2 mask. */ -#define EVSYS_GENERATOR2_bp 2 /* Generator selector bit 2 position. */ -#define EVSYS_GENERATOR3_bm (1<<3) /* Generator selector bit 3 mask. */ -#define EVSYS_GENERATOR3_bp 3 /* Generator selector bit 3 position. */ -#define EVSYS_GENERATOR4_bm (1<<4) /* Generator selector bit 4 mask. */ -#define EVSYS_GENERATOR4_bp 4 /* Generator selector bit 4 position. */ -#define EVSYS_GENERATOR5_bm (1<<5) /* Generator selector bit 5 mask. */ -#define EVSYS_GENERATOR5_bp 5 /* Generator selector bit 5 position. */ -#define EVSYS_GENERATOR6_bm (1<<6) /* Generator selector bit 6 mask. */ -#define EVSYS_GENERATOR6_bp 6 /* Generator selector bit 6 position. */ -#define EVSYS_GENERATOR7_bm (1<<7) /* Generator selector bit 7 mask. */ -#define EVSYS_GENERATOR7_bp 7 /* Generator selector bit 7 position. */ - -/* EVSYS.CHANNEL1 bit masks and bit positions */ -/* EVSYS_GENERATOR is already defined. */ - -/* EVSYS.CHANNEL2 bit masks and bit positions */ -/* EVSYS_GENERATOR is already defined. */ - -/* EVSYS.CHANNEL3 bit masks and bit positions */ -/* EVSYS_GENERATOR is already defined. */ - -/* EVSYS.CHANNEL4 bit masks and bit positions */ -/* EVSYS_GENERATOR is already defined. */ - -/* EVSYS.CHANNEL5 bit masks and bit positions */ -/* EVSYS_GENERATOR is already defined. */ - -/* EVSYS.CHANNEL6 bit masks and bit positions */ -/* EVSYS_GENERATOR is already defined. */ - -/* EVSYS.CHANNEL7 bit masks and bit positions */ -/* EVSYS_GENERATOR is already defined. */ - -/* EVSYS.USERCCLLUT0A bit masks and bit positions */ -#define EVSYS_CHANNEL_gm 0xFF /* Channel selector group mask. */ -#define EVSYS_CHANNEL_gp 0 /* Channel selector group position. */ -#define EVSYS_CHANNEL0_bm (1<<0) /* Channel selector bit 0 mask. */ -#define EVSYS_CHANNEL0_bp 0 /* Channel selector bit 0 position. */ -#define EVSYS_CHANNEL1_bm (1<<1) /* Channel selector bit 1 mask. */ -#define EVSYS_CHANNEL1_bp 1 /* Channel selector bit 1 position. */ -#define EVSYS_CHANNEL2_bm (1<<2) /* Channel selector bit 2 mask. */ -#define EVSYS_CHANNEL2_bp 2 /* Channel selector bit 2 position. */ -#define EVSYS_CHANNEL3_bm (1<<3) /* Channel selector bit 3 mask. */ -#define EVSYS_CHANNEL3_bp 3 /* Channel selector bit 3 position. */ -#define EVSYS_CHANNEL4_bm (1<<4) /* Channel selector bit 4 mask. */ -#define EVSYS_CHANNEL4_bp 4 /* Channel selector bit 4 position. */ -#define EVSYS_CHANNEL5_bm (1<<5) /* Channel selector bit 5 mask. */ -#define EVSYS_CHANNEL5_bp 5 /* Channel selector bit 5 position. */ -#define EVSYS_CHANNEL6_bm (1<<6) /* Channel selector bit 6 mask. */ -#define EVSYS_CHANNEL6_bp 6 /* Channel selector bit 6 position. */ -#define EVSYS_CHANNEL7_bm (1<<7) /* Channel selector bit 7 mask. */ -#define EVSYS_CHANNEL7_bp 7 /* Channel selector bit 7 position. */ - -/* EVSYS.USERCCLLUT0B bit masks and bit positions */ -/* EVSYS_CHANNEL is already defined. */ - -/* EVSYS.USERCCLLUT1A bit masks and bit positions */ -/* EVSYS_CHANNEL is already defined. */ - -/* EVSYS.USERCCLLUT1B bit masks and bit positions */ -/* EVSYS_CHANNEL is already defined. */ - -/* EVSYS.USERCCLLUT2A bit masks and bit positions */ -/* EVSYS_CHANNEL is already defined. */ - -/* EVSYS.USERCCLLUT2B bit masks and bit positions */ -/* EVSYS_CHANNEL is already defined. */ - -/* EVSYS.USERCCLLUT3A bit masks and bit positions */ -/* EVSYS_CHANNEL is already defined. */ - -/* EVSYS.USERCCLLUT3B bit masks and bit positions */ -/* EVSYS_CHANNEL is already defined. */ - -/* EVSYS.USERADC0 bit masks and bit positions */ -/* EVSYS_CHANNEL is already defined. */ - -/* EVSYS.USEREVOUTA bit masks and bit positions */ -/* EVSYS_CHANNEL is already defined. */ - -/* EVSYS.USEREVOUTB bit masks and bit positions */ -/* EVSYS_CHANNEL is already defined. */ - -/* EVSYS.USEREVOUTC bit masks and bit positions */ -/* EVSYS_CHANNEL is already defined. */ - -/* EVSYS.USEREVOUTD bit masks and bit positions */ -/* EVSYS_CHANNEL is already defined. */ - -/* EVSYS.USEREVOUTE bit masks and bit positions */ -/* EVSYS_CHANNEL is already defined. */ - -/* EVSYS.USEREVOUTF bit masks and bit positions */ -/* EVSYS_CHANNEL is already defined. */ - -/* EVSYS.USERUSART0 bit masks and bit positions */ -/* EVSYS_CHANNEL is already defined. */ - -/* EVSYS.USERUSART1 bit masks and bit positions */ -/* EVSYS_CHANNEL is already defined. */ - -/* EVSYS.USERUSART2 bit masks and bit positions */ -/* EVSYS_CHANNEL is already defined. */ - -/* EVSYS.USERUSART3 bit masks and bit positions */ -/* EVSYS_CHANNEL is already defined. */ - -/* EVSYS.USERTCA0 bit masks and bit positions */ -/* EVSYS_CHANNEL is already defined. */ - -/* EVSYS.USERTCB0 bit masks and bit positions */ -/* EVSYS_CHANNEL is already defined. */ - -/* EVSYS.USERTCB1 bit masks and bit positions */ -/* EVSYS_CHANNEL is already defined. */ - -/* EVSYS.USERTCB2 bit masks and bit positions */ -/* EVSYS_CHANNEL is already defined. */ - -/* EVSYS.USERTCB3 bit masks and bit positions */ -/* EVSYS_CHANNEL is already defined. */ - -/* FUSE - Fuses */ -/* FUSE.WDTCFG bit masks and bit positions */ -#define FUSE_PERIOD_gm 0x0F /* Watchdog Timeout Period group mask. */ -#define FUSE_PERIOD_gp 0 /* Watchdog Timeout Period group position. */ -#define FUSE_PERIOD0_bm (1<<0) /* Watchdog Timeout Period bit 0 mask. */ -#define FUSE_PERIOD0_bp 0 /* Watchdog Timeout Period bit 0 position. */ -#define FUSE_PERIOD1_bm (1<<1) /* Watchdog Timeout Period bit 1 mask. */ -#define FUSE_PERIOD1_bp 1 /* Watchdog Timeout Period bit 1 position. */ -#define FUSE_PERIOD2_bm (1<<2) /* Watchdog Timeout Period bit 2 mask. */ -#define FUSE_PERIOD2_bp 2 /* Watchdog Timeout Period bit 2 position. */ -#define FUSE_PERIOD3_bm (1<<3) /* Watchdog Timeout Period bit 3 mask. */ -#define FUSE_PERIOD3_bp 3 /* Watchdog Timeout Period bit 3 position. */ -#define FUSE_WINDOW_gm 0xF0 /* Watchdog Window Timeout Period group mask. */ -#define FUSE_WINDOW_gp 4 /* Watchdog Window Timeout Period group position. */ -#define FUSE_WINDOW0_bm (1<<4) /* Watchdog Window Timeout Period bit 0 mask. */ -#define FUSE_WINDOW0_bp 4 /* Watchdog Window Timeout Period bit 0 position. */ -#define FUSE_WINDOW1_bm (1<<5) /* Watchdog Window Timeout Period bit 1 mask. */ -#define FUSE_WINDOW1_bp 5 /* Watchdog Window Timeout Period bit 1 position. */ -#define FUSE_WINDOW2_bm (1<<6) /* Watchdog Window Timeout Period bit 2 mask. */ -#define FUSE_WINDOW2_bp 6 /* Watchdog Window Timeout Period bit 2 position. */ -#define FUSE_WINDOW3_bm (1<<7) /* Watchdog Window Timeout Period bit 3 mask. */ -#define FUSE_WINDOW3_bp 7 /* Watchdog Window Timeout Period bit 3 position. */ - -/* FUSE.BODCFG bit masks and bit positions */ -#define FUSE_SLEEP_gm 0x03 /* BOD Operation in Sleep Mode group mask. */ -#define FUSE_SLEEP_gp 0 /* BOD Operation in Sleep Mode group position. */ -#define FUSE_SLEEP0_bm (1<<0) /* BOD Operation in Sleep Mode bit 0 mask. */ -#define FUSE_SLEEP0_bp 0 /* BOD Operation in Sleep Mode bit 0 position. */ -#define FUSE_SLEEP1_bm (1<<1) /* BOD Operation in Sleep Mode bit 1 mask. */ -#define FUSE_SLEEP1_bp 1 /* BOD Operation in Sleep Mode bit 1 position. */ -#define FUSE_ACTIVE_gm 0x0C /* BOD Operation in Active Mode group mask. */ -#define FUSE_ACTIVE_gp 2 /* BOD Operation in Active Mode group position. */ -#define FUSE_ACTIVE0_bm (1<<2) /* BOD Operation in Active Mode bit 0 mask. */ -#define FUSE_ACTIVE0_bp 2 /* BOD Operation in Active Mode bit 0 position. */ -#define FUSE_ACTIVE1_bm (1<<3) /* BOD Operation in Active Mode bit 1 mask. */ -#define FUSE_ACTIVE1_bp 3 /* BOD Operation in Active Mode bit 1 position. */ -#define FUSE_SAMPFREQ_bm 0x10 /* BOD Sample Frequency bit mask. */ -#define FUSE_SAMPFREQ_bp 4 /* BOD Sample Frequency bit position. */ -#define FUSE_LVL_gm 0xE0 /* BOD Level group mask. */ -#define FUSE_LVL_gp 5 /* BOD Level group position. */ -#define FUSE_LVL0_bm (1<<5) /* BOD Level bit 0 mask. */ -#define FUSE_LVL0_bp 5 /* BOD Level bit 0 position. */ -#define FUSE_LVL1_bm (1<<6) /* BOD Level bit 1 mask. */ -#define FUSE_LVL1_bp 6 /* BOD Level bit 1 position. */ -#define FUSE_LVL2_bm (1<<7) /* BOD Level bit 2 mask. */ -#define FUSE_LVL2_bp 7 /* BOD Level bit 2 position. */ - -/* FUSE.OSCCFG bit masks and bit positions */ -#define FUSE_FREQSEL_gm 0x03 /* Frequency Select group mask. */ -#define FUSE_FREQSEL_gp 0 /* Frequency Select group position. */ -#define FUSE_FREQSEL0_bm (1<<0) /* Frequency Select bit 0 mask. */ -#define FUSE_FREQSEL0_bp 0 /* Frequency Select bit 0 position. */ -#define FUSE_FREQSEL1_bm (1<<1) /* Frequency Select bit 1 mask. */ -#define FUSE_FREQSEL1_bp 1 /* Frequency Select bit 1 position. */ -#define FUSE_OSCLOCK_bm 0x80 /* Oscillator Lock bit mask. */ -#define FUSE_OSCLOCK_bp 7 /* Oscillator Lock bit position. */ - -/* FUSE.TCD0CFG bit masks and bit positions */ -#define FUSE_CMPA_bm 0x01 /* Compare A Default Output Value bit mask. */ -#define FUSE_CMPA_bp 0 /* Compare A Default Output Value bit position. */ -#define FUSE_CMPB_bm 0x02 /* Compare B Default Output Value bit mask. */ -#define FUSE_CMPB_bp 1 /* Compare B Default Output Value bit position. */ -#define FUSE_CMPC_bm 0x04 /* Compare C Default Output Value bit mask. */ -#define FUSE_CMPC_bp 2 /* Compare C Default Output Value bit position. */ -#define FUSE_CMPD_bm 0x08 /* Compare D Default Output Value bit mask. */ -#define FUSE_CMPD_bp 3 /* Compare D Default Output Value bit position. */ -#define FUSE_CMPAEN_bm 0x10 /* Compare A Output Enable bit mask. */ -#define FUSE_CMPAEN_bp 4 /* Compare A Output Enable bit position. */ -#define FUSE_CMPBEN_bm 0x20 /* Compare B Output Enable bit mask. */ -#define FUSE_CMPBEN_bp 5 /* Compare B Output Enable bit position. */ -#define FUSE_CMPCEN_bm 0x40 /* Compare C Output Enable bit mask. */ -#define FUSE_CMPCEN_bp 6 /* Compare C Output Enable bit position. */ -#define FUSE_CMPDEN_bm 0x80 /* Compare D Output Enable bit mask. */ -#define FUSE_CMPDEN_bp 7 /* Compare D Output Enable bit position. */ - -/* FUSE.SYSCFG0 bit masks and bit positions */ -#define FUSE_EESAVE_bm 0x01 /* EEPROM Save bit mask. */ -#define FUSE_EESAVE_bp 0 /* EEPROM Save bit position. */ -#define FUSE_RSTPINCFG_gm 0x0C /* Reset Pin Configuration group mask. */ -#define FUSE_RSTPINCFG_gp 2 /* Reset Pin Configuration group position. */ -#define FUSE_RSTPINCFG0_bm (1<<2) /* Reset Pin Configuration bit 0 mask. */ -#define FUSE_RSTPINCFG0_bp 2 /* Reset Pin Configuration bit 0 position. */ -#define FUSE_RSTPINCFG1_bm (1<<3) /* Reset Pin Configuration bit 1 mask. */ -#define FUSE_RSTPINCFG1_bp 3 /* Reset Pin Configuration bit 1 position. */ -#define FUSE_CRCSRC_gm 0xC0 /* CRC Source group mask. */ -#define FUSE_CRCSRC_gp 6 /* CRC Source group position. */ -#define FUSE_CRCSRC0_bm (1<<6) /* CRC Source bit 0 mask. */ -#define FUSE_CRCSRC0_bp 6 /* CRC Source bit 0 position. */ -#define FUSE_CRCSRC1_bm (1<<7) /* CRC Source bit 1 mask. */ -#define FUSE_CRCSRC1_bp 7 /* CRC Source bit 1 position. */ - -/* FUSE.SYSCFG1 bit masks and bit positions */ -#define FUSE_SUT_gm 0x07 /* Startup Time group mask. */ -#define FUSE_SUT_gp 0 /* Startup Time group position. */ -#define FUSE_SUT0_bm (1<<0) /* Startup Time bit 0 mask. */ -#define FUSE_SUT0_bp 0 /* Startup Time bit 0 position. */ -#define FUSE_SUT1_bm (1<<1) /* Startup Time bit 1 mask. */ -#define FUSE_SUT1_bp 1 /* Startup Time bit 1 position. */ -#define FUSE_SUT2_bm (1<<2) /* Startup Time bit 2 mask. */ -#define FUSE_SUT2_bp 2 /* Startup Time bit 2 position. */ - - - - - - - -/* LOCKBIT - Lockbit */ -/* LOCKBIT.LOCKBIT bit masks and bit positions */ -#define LOCKBIT_LB_gm 0xFF /* Lock Bits group mask. */ -#define LOCKBIT_LB_gp 0 /* Lock Bits group position. */ -#define LOCKBIT_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ -#define LOCKBIT_LB0_bp 0 /* Lock Bits bit 0 position. */ -#define LOCKBIT_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ -#define LOCKBIT_LB1_bp 1 /* Lock Bits bit 1 position. */ -#define LOCKBIT_LB2_bm (1<<2) /* Lock Bits bit 2 mask. */ -#define LOCKBIT_LB2_bp 2 /* Lock Bits bit 2 position. */ -#define LOCKBIT_LB3_bm (1<<3) /* Lock Bits bit 3 mask. */ -#define LOCKBIT_LB3_bp 3 /* Lock Bits bit 3 position. */ -#define LOCKBIT_LB4_bm (1<<4) /* Lock Bits bit 4 mask. */ -#define LOCKBIT_LB4_bp 4 /* Lock Bits bit 4 position. */ -#define LOCKBIT_LB5_bm (1<<5) /* Lock Bits bit 5 mask. */ -#define LOCKBIT_LB5_bp 5 /* Lock Bits bit 5 position. */ -#define LOCKBIT_LB6_bm (1<<6) /* Lock Bits bit 6 mask. */ -#define LOCKBIT_LB6_bp 6 /* Lock Bits bit 6 position. */ -#define LOCKBIT_LB7_bm (1<<7) /* Lock Bits bit 7 mask. */ -#define LOCKBIT_LB7_bp 7 /* Lock Bits bit 7 position. */ - -/* NVMBIST - BIST in the NVMCTRL module */ -/* NVMBIST.CTRLA bit masks and bit positions */ -#define NVMBIST_CMD_gm 0x07 /* Command group mask. */ -#define NVMBIST_CMD_gp 0 /* Command group position. */ -#define NVMBIST_CMD0_bm (1<<0) /* Command bit 0 mask. */ -#define NVMBIST_CMD0_bp 0 /* Command bit 0 position. */ -#define NVMBIST_CMD1_bm (1<<1) /* Command bit 1 mask. */ -#define NVMBIST_CMD1_bp 1 /* Command bit 1 position. */ -#define NVMBIST_CMD2_bm (1<<2) /* Command bit 2 mask. */ -#define NVMBIST_CMD2_bp 2 /* Command bit 2 position. */ -#define NVMBIST_SAF_bm 0x08 /* Stop at fault bit mask. */ -#define NVMBIST_SAF_bp 3 /* Stop at fault bit position. */ - -/* NVMBIST.ADDRPAT bit masks and bit positions */ -#define NVMBIST_XMODE_gm 0x03 /* X address mode group mask. */ -#define NVMBIST_XMODE_gp 0 /* X address mode group position. */ -#define NVMBIST_XMODE0_bm (1<<0) /* X address mode bit 0 mask. */ -#define NVMBIST_XMODE0_bp 0 /* X address mode bit 0 position. */ -#define NVMBIST_XMODE1_bm (1<<1) /* X address mode bit 1 mask. */ -#define NVMBIST_XMODE1_bp 1 /* X address mode bit 1 position. */ -#define NVMBIST_YMODE_gm 0x0C /* Y address mode group mask. */ -#define NVMBIST_YMODE_gp 2 /* Y address mode group position. */ -#define NVMBIST_YMODE0_bm (1<<2) /* Y address mode bit 0 mask. */ -#define NVMBIST_YMODE0_bp 2 /* Y address mode bit 0 position. */ -#define NVMBIST_YMODE1_bm (1<<3) /* Y address mode bit 1 mask. */ -#define NVMBIST_YMODE1_bp 3 /* Y address mode bit 1 position. */ -#define NVMBIST_AMODE_gm 0x70 /* Address mode group mask. */ -#define NVMBIST_AMODE_gp 4 /* Address mode group position. */ -#define NVMBIST_AMODE0_bm (1<<4) /* Address mode bit 0 mask. */ -#define NVMBIST_AMODE0_bp 4 /* Address mode bit 0 position. */ -#define NVMBIST_AMODE1_bm (1<<5) /* Address mode bit 1 mask. */ -#define NVMBIST_AMODE1_bp 5 /* Address mode bit 1 position. */ -#define NVMBIST_AMODE2_bm (1<<6) /* Address mode bit 2 mask. */ -#define NVMBIST_AMODE2_bp 6 /* Address mode bit 2 position. */ - -/* NVMBIST.DATAPAT bit masks and bit positions */ -#define NVMBIST_PATTERN_gm 0x03 /* Data check pattern group mask. */ -#define NVMBIST_PATTERN_gp 0 /* Data check pattern group position. */ -#define NVMBIST_PATTERN0_bm (1<<0) /* Data check pattern bit 0 mask. */ -#define NVMBIST_PATTERN0_bp 0 /* Data check pattern bit 0 position. */ -#define NVMBIST_PATTERN1_bm (1<<1) /* Data check pattern bit 1 mask. */ -#define NVMBIST_PATTERN1_bp 1 /* Data check pattern bit 1 position. */ - -/* NVMBIST.STATUS bit masks and bit positions */ -#define NVMBIST_STATE_gm 0x0F /* FSM State group mask. */ -#define NVMBIST_STATE_gp 0 /* FSM State group position. */ -#define NVMBIST_STATE0_bm (1<<0) /* FSM State bit 0 mask. */ -#define NVMBIST_STATE0_bp 0 /* FSM State bit 0 position. */ -#define NVMBIST_STATE1_bm (1<<1) /* FSM State bit 1 mask. */ -#define NVMBIST_STATE1_bp 1 /* FSM State bit 1 position. */ -#define NVMBIST_STATE2_bm (1<<2) /* FSM State bit 2 mask. */ -#define NVMBIST_STATE2_bp 2 /* FSM State bit 2 position. */ -#define NVMBIST_STATE3_bm (1<<3) /* FSM State bit 3 mask. */ -#define NVMBIST_STATE3_bp 3 /* FSM State bit 3 position. */ - -/* NVMBIST.CNT bit masks and bit positions */ -#define NVMBIST_CNT_gm 0x7FF /* Faults counter group mask. */ -#define NVMBIST_CNT_gp 0 /* Faults counter group position. */ -#define NVMBIST_CNT0_bm (1<<0) /* Faults counter bit 0 mask. */ -#define NVMBIST_CNT0_bp 0 /* Faults counter bit 0 position. */ -#define NVMBIST_CNT1_bm (1<<1) /* Faults counter bit 1 mask. */ -#define NVMBIST_CNT1_bp 1 /* Faults counter bit 1 position. */ -#define NVMBIST_CNT2_bm (1<<2) /* Faults counter bit 2 mask. */ -#define NVMBIST_CNT2_bp 2 /* Faults counter bit 2 position. */ -#define NVMBIST_CNT3_bm (1<<3) /* Faults counter bit 3 mask. */ -#define NVMBIST_CNT3_bp 3 /* Faults counter bit 3 position. */ -#define NVMBIST_CNT4_bm (1<<4) /* Faults counter bit 4 mask. */ -#define NVMBIST_CNT4_bp 4 /* Faults counter bit 4 position. */ -#define NVMBIST_CNT5_bm (1<<5) /* Faults counter bit 5 mask. */ -#define NVMBIST_CNT5_bp 5 /* Faults counter bit 5 position. */ -#define NVMBIST_CNT6_bm (1<<6) /* Faults counter bit 6 mask. */ -#define NVMBIST_CNT6_bp 6 /* Faults counter bit 6 position. */ -#define NVMBIST_CNT7_bm (1<<7) /* Faults counter bit 7 mask. */ -#define NVMBIST_CNT7_bp 7 /* Faults counter bit 7 position. */ -#define NVMBIST_CNT8_bm (1<<8) /* Faults counter bit 8 mask. */ -#define NVMBIST_CNT8_bp 8 /* Faults counter bit 8 position. */ -#define NVMBIST_CNT9_bm (1<<9) /* Faults counter bit 9 mask. */ -#define NVMBIST_CNT9_bp 9 /* Faults counter bit 9 position. */ -#define NVMBIST_CNT10_bm (1<<10) /* Faults counter bit 10 mask. */ -#define NVMBIST_CNT10_bp 10 /* Faults counter bit 10 position. */ - -/* NVMBIST.END bit masks and bit positions */ -#define NVMBIST_END_gm 0xFFFFFF /* group mask. */ -#define NVMBIST_END_gp 0 /* group position. */ -#define NVMBIST_END0_bm (1<<0) /* bit 0 mask. */ -#define NVMBIST_END0_bp 0 /* bit 0 position. */ -#define NVMBIST_END1_bm (1<<1) /* bit 1 mask. */ -#define NVMBIST_END1_bp 1 /* bit 1 position. */ -#define NVMBIST_END2_bm (1<<2) /* bit 2 mask. */ -#define NVMBIST_END2_bp 2 /* bit 2 position. */ -#define NVMBIST_END3_bm (1<<3) /* bit 3 mask. */ -#define NVMBIST_END3_bp 3 /* bit 3 position. */ -#define NVMBIST_END4_bm (1<<4) /* bit 4 mask. */ -#define NVMBIST_END4_bp 4 /* bit 4 position. */ -#define NVMBIST_END5_bm (1<<5) /* bit 5 mask. */ -#define NVMBIST_END5_bp 5 /* bit 5 position. */ -#define NVMBIST_END6_bm (1<<6) /* bit 6 mask. */ -#define NVMBIST_END6_bp 6 /* bit 6 position. */ -#define NVMBIST_END7_bm (1<<7) /* bit 7 mask. */ -#define NVMBIST_END7_bp 7 /* bit 7 position. */ -#define NVMBIST_END8_bm (1<<8) /* bit 8 mask. */ -#define NVMBIST_END8_bp 8 /* bit 8 position. */ -#define NVMBIST_END9_bm (1<<9) /* bit 9 mask. */ -#define NVMBIST_END9_bp 9 /* bit 9 position. */ -#define NVMBIST_END10_bm (1<<10) /* bit 10 mask. */ -#define NVMBIST_END10_bp 10 /* bit 10 position. */ -#define NVMBIST_END11_bm (1<<11) /* bit 11 mask. */ -#define NVMBIST_END11_bp 11 /* bit 11 position. */ -#define NVMBIST_END12_bm (1<<12) /* bit 12 mask. */ -#define NVMBIST_END12_bp 12 /* bit 12 position. */ -#define NVMBIST_END13_bm (1<<13) /* bit 13 mask. */ -#define NVMBIST_END13_bp 13 /* bit 13 position. */ -#define NVMBIST_END14_bm (1<<14) /* bit 14 mask. */ -#define NVMBIST_END14_bp 14 /* bit 14 position. */ -#define NVMBIST_END15_bm (1<<15) /* bit 15 mask. */ -#define NVMBIST_END15_bp 15 /* bit 15 position. */ -#define NVMBIST_END16_bm (1<<16) /* bit 16 mask. */ -#define NVMBIST_END16_bp 16 /* bit 16 position. */ -#define NVMBIST_END17_bm (1<<17) /* bit 17 mask. */ -#define NVMBIST_END17_bp 17 /* bit 17 position. */ -#define NVMBIST_END18_bm (1<<18) /* bit 18 mask. */ -#define NVMBIST_END18_bp 18 /* bit 18 position. */ -#define NVMBIST_END19_bm (1<<19) /* bit 19 mask. */ -#define NVMBIST_END19_bp 19 /* bit 19 position. */ -#define NVMBIST_END20_bm (1<<20) /* bit 20 mask. */ -#define NVMBIST_END20_bp 20 /* bit 20 position. */ -#define NVMBIST_END21_bm (1<<21) /* bit 21 mask. */ -#define NVMBIST_END21_bp 21 /* bit 21 position. */ -#define NVMBIST_END22_bm (1<<22) /* bit 22 mask. */ -#define NVMBIST_END22_bp 22 /* bit 22 position. */ -#define NVMBIST_END23_bm (1<<23) /* bit 23 mask. */ -#define NVMBIST_END23_bp 23 /* bit 23 position. */ - -/* NVMCTRL - Non-volatile Memory Controller */ -/* NVMCTRL.CTRLA bit masks and bit positions */ -#define NVMCTRL_CMD_gm 0x07 /* Command group mask. */ -#define NVMCTRL_CMD_gp 0 /* Command group position. */ -#define NVMCTRL_CMD0_bm (1<<0) /* Command bit 0 mask. */ -#define NVMCTRL_CMD0_bp 0 /* Command bit 0 position. */ -#define NVMCTRL_CMD1_bm (1<<1) /* Command bit 1 mask. */ -#define NVMCTRL_CMD1_bp 1 /* Command bit 1 position. */ -#define NVMCTRL_CMD2_bm (1<<2) /* Command bit 2 mask. */ -#define NVMCTRL_CMD2_bp 2 /* Command bit 2 position. */ - -/* NVMCTRL.CTRLB bit masks and bit positions */ -#define NVMCTRL_APCWP_bm 0x01 /* Application code write protect bit mask. */ -#define NVMCTRL_APCWP_bp 0 /* Application code write protect bit position. */ -#define NVMCTRL_BOOTLOCK_bm 0x02 /* Boot Lock bit mask. */ -#define NVMCTRL_BOOTLOCK_bp 1 /* Boot Lock bit position. */ - -/* NVMCTRL.STATUS bit masks and bit positions */ -#define NVMCTRL_FBUSY_bm 0x01 /* Flash busy bit mask. */ -#define NVMCTRL_FBUSY_bp 0 /* Flash busy bit position. */ -#define NVMCTRL_EEBUSY_bm 0x02 /* EEPROM busy bit mask. */ -#define NVMCTRL_EEBUSY_bp 1 /* EEPROM busy bit position. */ -#define NVMCTRL_WRERROR_bm 0x04 /* Write error bit mask. */ -#define NVMCTRL_WRERROR_bp 2 /* Write error bit position. */ - -/* NVMCTRL.INTCTRL bit masks and bit positions */ -#define NVMCTRL_EEREADY_bm 0x01 /* EEPROM Ready bit mask. */ -#define NVMCTRL_EEREADY_bp 0 /* EEPROM Ready bit position. */ - -/* NVMCTRL.INTFLAGS bit masks and bit positions */ -/* NVMCTRL_EEREADY is already defined. */ - - - - - - - - - - - - -/* PORT - I/O Ports */ -/* PORT.INTFLAGS bit masks and bit positions */ -#define PORT_INT_gm 0xFF /* Pin Interrupt group mask. */ -#define PORT_INT_gp 0 /* Pin Interrupt group position. */ -#define PORT_INT0_bm (1<<0) /* Pin Interrupt bit 0 mask. */ -#define PORT_INT0_bp 0 /* Pin Interrupt bit 0 position. */ -#define PORT_INT1_bm (1<<1) /* Pin Interrupt bit 1 mask. */ -#define PORT_INT1_bp 1 /* Pin Interrupt bit 1 position. */ -#define PORT_INT2_bm (1<<2) /* Pin Interrupt bit 2 mask. */ -#define PORT_INT2_bp 2 /* Pin Interrupt bit 2 position. */ -#define PORT_INT3_bm (1<<3) /* Pin Interrupt bit 3 mask. */ -#define PORT_INT3_bp 3 /* Pin Interrupt bit 3 position. */ -#define PORT_INT4_bm (1<<4) /* Pin Interrupt bit 4 mask. */ -#define PORT_INT4_bp 4 /* Pin Interrupt bit 4 position. */ -#define PORT_INT5_bm (1<<5) /* Pin Interrupt bit 5 mask. */ -#define PORT_INT5_bp 5 /* Pin Interrupt bit 5 position. */ -#define PORT_INT6_bm (1<<6) /* Pin Interrupt bit 6 mask. */ -#define PORT_INT6_bp 6 /* Pin Interrupt bit 6 position. */ -#define PORT_INT7_bm (1<<7) /* Pin Interrupt bit 7 mask. */ -#define PORT_INT7_bp 7 /* Pin Interrupt bit 7 position. */ - -/* PORT.PORTCTRL bit masks and bit positions */ -#define PORT_SRL_bm 0x01 /* Slew Rate Limit Enable bit mask. */ -#define PORT_SRL_bp 0 /* Slew Rate Limit Enable bit position. */ - -/* PORT.PIN0CTRL bit masks and bit positions */ -#define PORT_ISC_gm 0x07 /* Input/Sense Configuration group mask. */ -#define PORT_ISC_gp 0 /* Input/Sense Configuration group position. */ -#define PORT_ISC0_bm (1<<0) /* Input/Sense Configuration bit 0 mask. */ -#define PORT_ISC0_bp 0 /* Input/Sense Configuration bit 0 position. */ -#define PORT_ISC1_bm (1<<1) /* Input/Sense Configuration bit 1 mask. */ -#define PORT_ISC1_bp 1 /* Input/Sense Configuration bit 1 position. */ -#define PORT_ISC2_bm (1<<2) /* Input/Sense Configuration bit 2 mask. */ -#define PORT_ISC2_bp 2 /* Input/Sense Configuration bit 2 position. */ -#define PORT_PULLUPEN_bm 0x08 /* Pullup enable bit mask. */ -#define PORT_PULLUPEN_bp 3 /* Pullup enable bit position. */ -#define PORT_INVEN_bm 0x80 /* Inverted I/O Enable bit mask. */ -#define PORT_INVEN_bp 7 /* Inverted I/O Enable bit position. */ - -/* PORT.PIN1CTRL bit masks and bit positions */ -/* PORT_ISC is already defined. */ -/* PORT_PULLUPEN is already defined. */ -/* PORT_INVEN is already defined. */ - -/* PORT.PIN2CTRL bit masks and bit positions */ -/* PORT_ISC is already defined. */ -/* PORT_PULLUPEN is already defined. */ -/* PORT_INVEN is already defined. */ - -/* PORT.PIN3CTRL bit masks and bit positions */ -/* PORT_ISC is already defined. */ -/* PORT_PULLUPEN is already defined. */ -/* PORT_INVEN is already defined. */ - -/* PORT.PIN4CTRL bit masks and bit positions */ -/* PORT_ISC is already defined. */ -/* PORT_PULLUPEN is already defined. */ -/* PORT_INVEN is already defined. */ - -/* PORT.PIN5CTRL bit masks and bit positions */ -/* PORT_ISC is already defined. */ -/* PORT_PULLUPEN is already defined. */ -/* PORT_INVEN is already defined. */ - -/* PORT.PIN6CTRL bit masks and bit positions */ -/* PORT_ISC is already defined. */ -/* PORT_PULLUPEN is already defined. */ -/* PORT_INVEN is already defined. */ - -/* PORT.PIN7CTRL bit masks and bit positions */ -/* PORT_ISC is already defined. */ -/* PORT_PULLUPEN is already defined. */ -/* PORT_INVEN is already defined. */ - -/* PORTMUX - Port Multiplexer */ -/* PORTMUX.EVSYSROUTEA bit masks and bit positions */ -#define PORTMUX_EVOUT0_bm 0x01 /* Event Output 0 bit mask. */ -#define PORTMUX_EVOUT0_bp 0 /* Event Output 0 bit position. */ -#define PORTMUX_EVOUT1_bm 0x02 /* Event Output 1 bit mask. */ -#define PORTMUX_EVOUT1_bp 1 /* Event Output 1 bit position. */ -#define PORTMUX_EVOUT2_bm 0x04 /* Event Output 2 bit mask. */ -#define PORTMUX_EVOUT2_bp 2 /* Event Output 2 bit position. */ -#define PORTMUX_EVOUT3_bm 0x08 /* Event Output 3 bit mask. */ -#define PORTMUX_EVOUT3_bp 3 /* Event Output 3 bit position. */ -#define PORTMUX_EVOUT4_bm 0x10 /* Event Output 4 bit mask. */ -#define PORTMUX_EVOUT4_bp 4 /* Event Output 4 bit position. */ -#define PORTMUX_EVOUT5_bm 0x20 /* Event Output 5 bit mask. */ -#define PORTMUX_EVOUT5_bp 5 /* Event Output 5 bit position. */ - -/* PORTMUX.CCLROUTEA bit masks and bit positions */ -#define PORTMUX_LUT0_bm 0x01 /* CCL LUT0 bit mask. */ -#define PORTMUX_LUT0_bp 0 /* CCL LUT0 bit position. */ -#define PORTMUX_LUT1_bm 0x02 /* CCL LUT1 bit mask. */ -#define PORTMUX_LUT1_bp 1 /* CCL LUT1 bit position. */ -#define PORTMUX_LUT2_bm 0x04 /* CCL LUT2 bit mask. */ -#define PORTMUX_LUT2_bp 2 /* CCL LUT2 bit position. */ -#define PORTMUX_LUT3_bm 0x08 /* CCL LUT3 bit mask. */ -#define PORTMUX_LUT3_bp 3 /* CCL LUT3 bit position. */ - -/* PORTMUX.USARTROUTEA bit masks and bit positions */ -#define PORTMUX_USART0_gm 0x03 /* Port Multiplexer USART0 group mask. */ -#define PORTMUX_USART0_gp 0 /* Port Multiplexer USART0 group position. */ -#define PORTMUX_USART00_bm (1<<0) /* Port Multiplexer USART0 bit 0 mask. */ -#define PORTMUX_USART00_bp 0 /* Port Multiplexer USART0 bit 0 position. */ -#define PORTMUX_USART01_bm (1<<1) /* Port Multiplexer USART0 bit 1 mask. */ -#define PORTMUX_USART01_bp 1 /* Port Multiplexer USART0 bit 1 position. */ -#define PORTMUX_USART1_gm 0x0C /* Port Multiplexer USART1 group mask. */ -#define PORTMUX_USART1_gp 2 /* Port Multiplexer USART1 group position. */ -#define PORTMUX_USART10_bm (1<<2) /* Port Multiplexer USART1 bit 0 mask. */ -#define PORTMUX_USART10_bp 2 /* Port Multiplexer USART1 bit 0 position. */ -#define PORTMUX_USART11_bm (1<<3) /* Port Multiplexer USART1 bit 1 mask. */ -#define PORTMUX_USART11_bp 3 /* Port Multiplexer USART1 bit 1 position. */ -#define PORTMUX_USART2_gm 0x30 /* Port Multiplexer USART2 group mask. */ -#define PORTMUX_USART2_gp 4 /* Port Multiplexer USART2 group position. */ -#define PORTMUX_USART20_bm (1<<4) /* Port Multiplexer USART2 bit 0 mask. */ -#define PORTMUX_USART20_bp 4 /* Port Multiplexer USART2 bit 0 position. */ -#define PORTMUX_USART21_bm (1<<5) /* Port Multiplexer USART2 bit 1 mask. */ -#define PORTMUX_USART21_bp 5 /* Port Multiplexer USART2 bit 1 position. */ -#define PORTMUX_USART3_gm 0xC0 /* Port Multiplexer USART3 group mask. */ -#define PORTMUX_USART3_gp 6 /* Port Multiplexer USART3 group position. */ -#define PORTMUX_USART30_bm (1<<6) /* Port Multiplexer USART3 bit 0 mask. */ -#define PORTMUX_USART30_bp 6 /* Port Multiplexer USART3 bit 0 position. */ -#define PORTMUX_USART31_bm (1<<7) /* Port Multiplexer USART3 bit 1 mask. */ -#define PORTMUX_USART31_bp 7 /* Port Multiplexer USART3 bit 1 position. */ - -/* PORTMUX.TWISPIROUTEA bit masks and bit positions */ -#define PORTMUX_SPI0_gm 0x03 /* Port Multiplexer SPI0 group mask. */ -#define PORTMUX_SPI0_gp 0 /* Port Multiplexer SPI0 group position. */ -#define PORTMUX_SPI00_bm (1<<0) /* Port Multiplexer SPI0 bit 0 mask. */ -#define PORTMUX_SPI00_bp 0 /* Port Multiplexer SPI0 bit 0 position. */ -#define PORTMUX_SPI01_bm (1<<1) /* Port Multiplexer SPI0 bit 1 mask. */ -#define PORTMUX_SPI01_bp 1 /* Port Multiplexer SPI0 bit 1 position. */ -#define PORTMUX_TWI0_gm 0x30 /* Port Multiplexer TWI0 group mask. */ -#define PORTMUX_TWI0_gp 4 /* Port Multiplexer TWI0 group position. */ -#define PORTMUX_TWI00_bm (1<<4) /* Port Multiplexer TWI0 bit 0 mask. */ -#define PORTMUX_TWI00_bp 4 /* Port Multiplexer TWI0 bit 0 position. */ -#define PORTMUX_TWI01_bm (1<<5) /* Port Multiplexer TWI0 bit 1 mask. */ -#define PORTMUX_TWI01_bp 5 /* Port Multiplexer TWI0 bit 1 position. */ - -/* PORTMUX.TCAROUTEA bit masks and bit positions */ -#define PORTMUX_TCA0_gm 0x07 /* Port Multiplexer TCA0 group mask. */ -#define PORTMUX_TCA0_gp 0 /* Port Multiplexer TCA0 group position. */ -#define PORTMUX_TCA00_bm (1<<0) /* Port Multiplexer TCA0 bit 0 mask. */ -#define PORTMUX_TCA00_bp 0 /* Port Multiplexer TCA0 bit 0 position. */ -#define PORTMUX_TCA01_bm (1<<1) /* Port Multiplexer TCA0 bit 1 mask. */ -#define PORTMUX_TCA01_bp 1 /* Port Multiplexer TCA0 bit 1 position. */ -#define PORTMUX_TCA02_bm (1<<2) /* Port Multiplexer TCA0 bit 2 mask. */ -#define PORTMUX_TCA02_bp 2 /* Port Multiplexer TCA0 bit 2 position. */ - -/* PORTMUX.TCBROUTEA bit masks and bit positions */ -#define PORTMUX_TCB0_bm 0x01 /* Port Multiplexer TCB0 bit mask. */ -#define PORTMUX_TCB0_bp 0 /* Port Multiplexer TCB0 bit position. */ -#define PORTMUX_TCB1_bm 0x02 /* Port Multiplexer TCB1 bit mask. */ -#define PORTMUX_TCB1_bp 1 /* Port Multiplexer TCB1 bit position. */ -#define PORTMUX_TCB2_bm 0x04 /* Port Multiplexer TCB2 bit mask. */ -#define PORTMUX_TCB2_bp 2 /* Port Multiplexer TCB2 bit position. */ -#define PORTMUX_TCB3_bm 0x08 /* Port Multiplexer TCB3 bit mask. */ -#define PORTMUX_TCB3_bp 3 /* Port Multiplexer TCB3 bit position. */ - -/* RSTCTRL - Reset controller */ -/* RSTCTRL.RSTFR bit masks and bit positions */ -#define RSTCTRL_PORF_bm 0x01 /* Power on Reset flag bit mask. */ -#define RSTCTRL_PORF_bp 0 /* Power on Reset flag bit position. */ -#define RSTCTRL_BORF_bm 0x02 /* Brown out detector Reset flag bit mask. */ -#define RSTCTRL_BORF_bp 1 /* Brown out detector Reset flag bit position. */ -#define RSTCTRL_EXTRF_bm 0x04 /* External Reset flag bit mask. */ -#define RSTCTRL_EXTRF_bp 2 /* External Reset flag bit position. */ -#define RSTCTRL_WDRF_bm 0x08 /* Watch dog Reset flag bit mask. */ -#define RSTCTRL_WDRF_bp 3 /* Watch dog Reset flag bit position. */ -#define RSTCTRL_SWRF_bm 0x10 /* Software Reset flag bit mask. */ -#define RSTCTRL_SWRF_bp 4 /* Software Reset flag bit position. */ -#define RSTCTRL_UPDIRF_bm 0x20 /* UPDI Reset flag bit mask. */ -#define RSTCTRL_UPDIRF_bp 5 /* UPDI Reset flag bit position. */ - -/* RSTCTRL.SWRR bit masks and bit positions */ -#define RSTCTRL_SWRE_bm 0x01 /* Software reset enable bit mask. */ -#define RSTCTRL_SWRE_bp 0 /* Software reset enable bit position. */ - -/* RTC - Real-Time Counter */ -/* RTC.CTRLA bit masks and bit positions */ -#define RTC_RTCEN_bm 0x01 /* Enable bit mask. */ -#define RTC_RTCEN_bp 0 /* Enable bit position. */ -#define RTC_PRESCALER_gm 0x78 /* Prescaling Factor group mask. */ -#define RTC_PRESCALER_gp 3 /* Prescaling Factor group position. */ -#define RTC_PRESCALER0_bm (1<<3) /* Prescaling Factor bit 0 mask. */ -#define RTC_PRESCALER0_bp 3 /* Prescaling Factor bit 0 position. */ -#define RTC_PRESCALER1_bm (1<<4) /* Prescaling Factor bit 1 mask. */ -#define RTC_PRESCALER1_bp 4 /* Prescaling Factor bit 1 position. */ -#define RTC_PRESCALER2_bm (1<<5) /* Prescaling Factor bit 2 mask. */ -#define RTC_PRESCALER2_bp 5 /* Prescaling Factor bit 2 position. */ -#define RTC_PRESCALER3_bm (1<<6) /* Prescaling Factor bit 3 mask. */ -#define RTC_PRESCALER3_bp 6 /* Prescaling Factor bit 3 position. */ -#define RTC_RUNSTDBY_bm 0x80 /* Run In Standby bit mask. */ -#define RTC_RUNSTDBY_bp 7 /* Run In Standby bit position. */ - -/* RTC.STATUS bit masks and bit positions */ -#define RTC_CTRLABUSY_bm 0x01 /* CTRLA Synchronization Busy Flag bit mask. */ -#define RTC_CTRLABUSY_bp 0 /* CTRLA Synchronization Busy Flag bit position. */ -#define RTC_CNTBUSY_bm 0x02 /* Count Synchronization Busy Flag bit mask. */ -#define RTC_CNTBUSY_bp 1 /* Count Synchronization Busy Flag bit position. */ -#define RTC_PERBUSY_bm 0x04 /* Period Synchronization Busy Flag bit mask. */ -#define RTC_PERBUSY_bp 2 /* Period Synchronization Busy Flag bit position. */ -#define RTC_CMPBUSY_bm 0x08 /* Comparator Synchronization Busy Flag bit mask. */ -#define RTC_CMPBUSY_bp 3 /* Comparator Synchronization Busy Flag bit position. */ - -/* RTC.INTCTRL bit masks and bit positions */ -#define RTC_OVF_bm 0x01 /* Overflow Interrupt enable bit mask. */ -#define RTC_OVF_bp 0 /* Overflow Interrupt enable bit position. */ -#define RTC_CMP_bm 0x02 /* Compare Match Interrupt enable bit mask. */ -#define RTC_CMP_bp 1 /* Compare Match Interrupt enable bit position. */ - -/* RTC.INTFLAGS bit masks and bit positions */ -/* RTC_OVF is already defined. */ -/* RTC_CMP is already defined. */ - - -/* RTC.DBGCTRL bit masks and bit positions */ -#define RTC_DBGRUN_bm 0x01 /* Run in debug bit mask. */ -#define RTC_DBGRUN_bp 0 /* Run in debug bit position. */ - -/* RTC.CLKSEL bit masks and bit positions */ -#define RTC_CLKSEL_gm 0x03 /* Clock Select group mask. */ -#define RTC_CLKSEL_gp 0 /* Clock Select group position. */ -#define RTC_CLKSEL0_bm (1<<0) /* Clock Select bit 0 mask. */ -#define RTC_CLKSEL0_bp 0 /* Clock Select bit 0 position. */ -#define RTC_CLKSEL1_bm (1<<1) /* Clock Select bit 1 mask. */ -#define RTC_CLKSEL1_bp 1 /* Clock Select bit 1 position. */ - - - - -/* RTC.PITCTRLA bit masks and bit positions */ -#define RTC_PITEN_bm 0x01 /* Enable bit mask. */ -#define RTC_PITEN_bp 0 /* Enable bit position. */ -#define RTC_PERIOD_gm 0x78 /* Period group mask. */ -#define RTC_PERIOD_gp 3 /* Period group position. */ -#define RTC_PERIOD0_bm (1<<3) /* Period bit 0 mask. */ -#define RTC_PERIOD0_bp 3 /* Period bit 0 position. */ -#define RTC_PERIOD1_bm (1<<4) /* Period bit 1 mask. */ -#define RTC_PERIOD1_bp 4 /* Period bit 1 position. */ -#define RTC_PERIOD2_bm (1<<5) /* Period bit 2 mask. */ -#define RTC_PERIOD2_bp 5 /* Period bit 2 position. */ -#define RTC_PERIOD3_bm (1<<6) /* Period bit 3 mask. */ -#define RTC_PERIOD3_bp 6 /* Period bit 3 position. */ - -/* RTC.PITSTATUS bit masks and bit positions */ -#define RTC_CTRLBUSY_bm 0x01 /* CTRLA Synchronization Busy Flag bit mask. */ -#define RTC_CTRLBUSY_bp 0 /* CTRLA Synchronization Busy Flag bit position. */ - -/* RTC.PITINTCTRL bit masks and bit positions */ -#define RTC_PI_bm 0x01 /* Periodic Interrupt bit mask. */ -#define RTC_PI_bp 0 /* Periodic Interrupt bit position. */ - -/* RTC.PITINTFLAGS bit masks and bit positions */ -/* RTC_PI is already defined. */ - -/* RTC.PITDBGCTRL bit masks and bit positions */ -/* RTC_DBGRUN is already defined. */ - - - - - - - - - - - - - - - - - - - - - - - - - - -/* SLPCTRL - Sleep Controller */ -/* SLPCTRL.CTRLA bit masks and bit positions */ -#define SLPCTRL_SEN_bm 0x01 /* Sleep enable bit mask. */ -#define SLPCTRL_SEN_bp 0 /* Sleep enable bit position. */ -#define SLPCTRL_SMODE_gm 0x06 /* Sleep mode group mask. */ -#define SLPCTRL_SMODE_gp 1 /* Sleep mode group position. */ -#define SLPCTRL_SMODE0_bm (1<<1) /* Sleep mode bit 0 mask. */ -#define SLPCTRL_SMODE0_bp 1 /* Sleep mode bit 0 position. */ -#define SLPCTRL_SMODE1_bm (1<<2) /* Sleep mode bit 1 mask. */ -#define SLPCTRL_SMODE1_bp 2 /* Sleep mode bit 1 position. */ - -/* SPI - Serial Peripheral Interface */ -/* SPI.CTRLA bit masks and bit positions */ -#define SPI_ENABLE_bm 0x01 /* Enable Module bit mask. */ -#define SPI_ENABLE_bp 0 /* Enable Module bit position. */ -#define SPI_PRESC_gm 0x06 /* Prescaler group mask. */ -#define SPI_PRESC_gp 1 /* Prescaler group position. */ -#define SPI_PRESC0_bm (1<<1) /* Prescaler bit 0 mask. */ -#define SPI_PRESC0_bp 1 /* Prescaler bit 0 position. */ -#define SPI_PRESC1_bm (1<<2) /* Prescaler bit 1 mask. */ -#define SPI_PRESC1_bp 2 /* Prescaler bit 1 position. */ -#define SPI_CLK2X_bm 0x10 /* Enable Double Speed bit mask. */ -#define SPI_CLK2X_bp 4 /* Enable Double Speed bit position. */ -#define SPI_MASTER_bm 0x20 /* Master Operation Enable bit mask. */ -#define SPI_MASTER_bp 5 /* Master Operation Enable bit position. */ -#define SPI_DORD_bm 0x40 /* Data Order Setting bit mask. */ -#define SPI_DORD_bp 6 /* Data Order Setting bit position. */ - -/* SPI.CTRLB bit masks and bit positions */ -#define SPI_MODE_gm 0x03 /* SPI Mode group mask. */ -#define SPI_MODE_gp 0 /* SPI Mode group position. */ -#define SPI_MODE0_bm (1<<0) /* SPI Mode bit 0 mask. */ -#define SPI_MODE0_bp 0 /* SPI Mode bit 0 position. */ -#define SPI_MODE1_bm (1<<1) /* SPI Mode bit 1 mask. */ -#define SPI_MODE1_bp 1 /* SPI Mode bit 1 position. */ -#define SPI_SSD_bm 0x04 /* Slave Select Disable bit mask. */ -#define SPI_SSD_bp 2 /* Slave Select Disable bit position. */ -#define SPI_BUFWR_bm 0x40 /* Buffer Write Mode bit mask. */ -#define SPI_BUFWR_bp 6 /* Buffer Write Mode bit position. */ -#define SPI_BUFEN_bm 0x80 /* Buffer Mode Enable bit mask. */ -#define SPI_BUFEN_bp 7 /* Buffer Mode Enable bit position. */ - -/* SPI.INTCTRL bit masks and bit positions */ -#define SPI_IE_bm 0x01 /* Interrupt Enable bit mask. */ -#define SPI_IE_bp 0 /* Interrupt Enable bit position. */ -#define SPI_SSIE_bm 0x10 /* Slave Select Trigger Interrupt Enable bit mask. */ -#define SPI_SSIE_bp 4 /* Slave Select Trigger Interrupt Enable bit position. */ -#define SPI_DREIE_bm 0x20 /* Data Register Empty Interrupt Enable bit mask. */ -#define SPI_DREIE_bp 5 /* Data Register Empty Interrupt Enable bit position. */ -#define SPI_TXCIE_bm 0x40 /* Transfer Complete Interrupt Enable bit mask. */ -#define SPI_TXCIE_bp 6 /* Transfer Complete Interrupt Enable bit position. */ -#define SPI_RXCIE_bm 0x80 /* Receive Complete Interrupt Enable bit mask. */ -#define SPI_RXCIE_bp 7 /* Receive Complete Interrupt Enable bit position. */ - -/* SPI.INTFLAGS bit masks and bit positions */ -#define SPI_BUFOVF_bm 0x01 /* Buffer Overflow bit mask. */ -#define SPI_BUFOVF_bp 0 /* Buffer Overflow bit position. */ -#define SPI_SSIF_bm 0x10 /* Slave Select Trigger Interrupt Flag bit mask. */ -#define SPI_SSIF_bp 4 /* Slave Select Trigger Interrupt Flag bit position. */ -#define SPI_DREIF_bm 0x20 /* Data Register Empty Interrupt Flag bit mask. */ -#define SPI_DREIF_bp 5 /* Data Register Empty Interrupt Flag bit position. */ -#define SPI_TXCIF_bm 0x40 /* Transfer Complete Interrupt Flag bit mask. */ -#define SPI_TXCIF_bp 6 /* Transfer Complete Interrupt Flag bit position. */ -#define SPI_WRCOL_bm 0x40 /* Write Collision bit mask. */ -#define SPI_WRCOL_bp 6 /* Write Collision bit position. */ -#define SPI_RXCIF_bm 0x80 /* Receive Complete Interrupt Flag bit mask. */ -#define SPI_RXCIF_bp 7 /* Receive Complete Interrupt Flag bit position. */ -#define SPI_IF_bm 0x80 /* Interrupt Flag bit mask. */ -#define SPI_IF_bp 7 /* Interrupt Flag bit position. */ - - - -/* SYSCFG - System Configuration Registers */ -/* SYSCFG.EXTBRK bit masks and bit positions */ -#define SYSCFG_ENEXTBRK_bm 0x01 /* External break enable bit mask. */ -#define SYSCFG_ENEXTBRK_bp 0 /* External break enable bit position. */ - - -/* SYSCFG.OCDMS bit masks and bit positions */ -#define SYSCFG_OCDMR_bm 0x01 /* OCD Message Read bit mask. */ -#define SYSCFG_OCDMR_bp 0 /* OCD Message Read bit position. */ - -/* TCA - 16-bit Timer/Counter Type A */ -/* TCA_SINGLE.CTRLA bit masks and bit positions */ -#define TCA_SINGLE_ENABLE_bm 0x01 /* Module Enable bit mask. */ -#define TCA_SINGLE_ENABLE_bp 0 /* Module Enable bit position. */ -#define TCA_SINGLE_CLKSEL_gm 0x0E /* Clock Selection group mask. */ -#define TCA_SINGLE_CLKSEL_gp 1 /* Clock Selection group position. */ -#define TCA_SINGLE_CLKSEL0_bm (1<<1) /* Clock Selection bit 0 mask. */ -#define TCA_SINGLE_CLKSEL0_bp 1 /* Clock Selection bit 0 position. */ -#define TCA_SINGLE_CLKSEL1_bm (1<<2) /* Clock Selection bit 1 mask. */ -#define TCA_SINGLE_CLKSEL1_bp 2 /* Clock Selection bit 1 position. */ -#define TCA_SINGLE_CLKSEL2_bm (1<<3) /* Clock Selection bit 2 mask. */ -#define TCA_SINGLE_CLKSEL2_bp 3 /* Clock Selection bit 2 position. */ - -/* TCA_SINGLE.CTRLB bit masks and bit positions */ -#define TCA_SINGLE_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ -#define TCA_SINGLE_WGMODE_gp 0 /* Waveform generation mode group position. */ -#define TCA_SINGLE_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ -#define TCA_SINGLE_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ -#define TCA_SINGLE_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ -#define TCA_SINGLE_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ -#define TCA_SINGLE_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ -#define TCA_SINGLE_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ -#define TCA_SINGLE_ALUPD_bm 0x08 /* Auto Lock Update bit mask. */ -#define TCA_SINGLE_ALUPD_bp 3 /* Auto Lock Update bit position. */ -#define TCA_SINGLE_CMP0EN_bm 0x10 /* Compare 0 Enable bit mask. */ -#define TCA_SINGLE_CMP0EN_bp 4 /* Compare 0 Enable bit position. */ -#define TCA_SINGLE_CMP1EN_bm 0x20 /* Compare 1 Enable bit mask. */ -#define TCA_SINGLE_CMP1EN_bp 5 /* Compare 1 Enable bit position. */ -#define TCA_SINGLE_CMP2EN_bm 0x40 /* Compare 2 Enable bit mask. */ -#define TCA_SINGLE_CMP2EN_bp 6 /* Compare 2 Enable bit position. */ - -/* TCA_SINGLE.CTRLC bit masks and bit positions */ -#define TCA_SINGLE_CMP0OV_bm 0x01 /* Compare 0 Waveform Output Value bit mask. */ -#define TCA_SINGLE_CMP0OV_bp 0 /* Compare 0 Waveform Output Value bit position. */ -#define TCA_SINGLE_CMP1OV_bm 0x02 /* Compare 1 Waveform Output Value bit mask. */ -#define TCA_SINGLE_CMP1OV_bp 1 /* Compare 1 Waveform Output Value bit position. */ -#define TCA_SINGLE_CMP2OV_bm 0x04 /* Compare 2 Waveform Output Value bit mask. */ -#define TCA_SINGLE_CMP2OV_bp 2 /* Compare 2 Waveform Output Value bit position. */ - -/* TCA_SINGLE.CTRLD bit masks and bit positions */ -#define TCA_SINGLE_SPLITM_bm 0x01 /* Split Mode Enable bit mask. */ -#define TCA_SINGLE_SPLITM_bp 0 /* Split Mode Enable bit position. */ - -/* TCA_SINGLE.CTRLECLR bit masks and bit positions */ -#define TCA_SINGLE_DIR_bm 0x01 /* Direction bit mask. */ -#define TCA_SINGLE_DIR_bp 0 /* Direction bit position. */ -#define TCA_SINGLE_LUPD_bm 0x02 /* Lock Update bit mask. */ -#define TCA_SINGLE_LUPD_bp 1 /* Lock Update bit position. */ -#define TCA_SINGLE_CMD_gm 0x0C /* Command group mask. */ -#define TCA_SINGLE_CMD_gp 2 /* Command group position. */ -#define TCA_SINGLE_CMD0_bm (1<<2) /* Command bit 0 mask. */ -#define TCA_SINGLE_CMD0_bp 2 /* Command bit 0 position. */ -#define TCA_SINGLE_CMD1_bm (1<<3) /* Command bit 1 mask. */ -#define TCA_SINGLE_CMD1_bp 3 /* Command bit 1 position. */ - -/* TCA_SINGLE.CTRLESET bit masks and bit positions */ -/* TCA_SINGLE_DIR is already defined. */ -/* TCA_SINGLE_LUPD is already defined. */ -/* TCA_SINGLE_CMD is already defined. */ - -/* TCA_SINGLE.CTRLFCLR bit masks and bit positions */ -#define TCA_SINGLE_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ -#define TCA_SINGLE_PERBV_bp 0 /* Period Buffer Valid bit position. */ -#define TCA_SINGLE_CMP0BV_bm 0x02 /* Compare 0 Buffer Valid bit mask. */ -#define TCA_SINGLE_CMP0BV_bp 1 /* Compare 0 Buffer Valid bit position. */ -#define TCA_SINGLE_CMP1BV_bm 0x04 /* Compare 1 Buffer Valid bit mask. */ -#define TCA_SINGLE_CMP1BV_bp 2 /* Compare 1 Buffer Valid bit position. */ -#define TCA_SINGLE_CMP2BV_bm 0x08 /* Compare 2 Buffer Valid bit mask. */ -#define TCA_SINGLE_CMP2BV_bp 3 /* Compare 2 Buffer Valid bit position. */ - -/* TCA_SINGLE.CTRLFSET bit masks and bit positions */ -/* TCA_SINGLE_PERBV is already defined. */ -/* TCA_SINGLE_CMP0BV is already defined. */ -/* TCA_SINGLE_CMP1BV is already defined. */ -/* TCA_SINGLE_CMP2BV is already defined. */ - -/* TCA_SINGLE.EVCTRL bit masks and bit positions */ -#define TCA_SINGLE_CNTEI_bm 0x01 /* Count on Event Input bit mask. */ -#define TCA_SINGLE_CNTEI_bp 0 /* Count on Event Input bit position. */ -#define TCA_SINGLE_EVACT_gm 0x06 /* Event Action group mask. */ -#define TCA_SINGLE_EVACT_gp 1 /* Event Action group position. */ -#define TCA_SINGLE_EVACT0_bm (1<<1) /* Event Action bit 0 mask. */ -#define TCA_SINGLE_EVACT0_bp 1 /* Event Action bit 0 position. */ -#define TCA_SINGLE_EVACT1_bm (1<<2) /* Event Action bit 1 mask. */ -#define TCA_SINGLE_EVACT1_bp 2 /* Event Action bit 1 position. */ - -/* TCA_SINGLE.INTCTRL bit masks and bit positions */ -#define TCA_SINGLE_OVF_bm 0x01 /* Overflow Interrupt bit mask. */ -#define TCA_SINGLE_OVF_bp 0 /* Overflow Interrupt bit position. */ -#define TCA_SINGLE_CMP0_bm 0x10 /* Compare 0 Interrupt bit mask. */ -#define TCA_SINGLE_CMP0_bp 4 /* Compare 0 Interrupt bit position. */ -#define TCA_SINGLE_CMP1_bm 0x20 /* Compare 1 Interrupt bit mask. */ -#define TCA_SINGLE_CMP1_bp 5 /* Compare 1 Interrupt bit position. */ -#define TCA_SINGLE_CMP2_bm 0x40 /* Compare 2 Interrupt bit mask. */ -#define TCA_SINGLE_CMP2_bp 6 /* Compare 2 Interrupt bit position. */ - -/* TCA_SINGLE.INTFLAGS bit masks and bit positions */ -/* TCA_SINGLE_OVF is already defined. */ -/* TCA_SINGLE_CMP0 is already defined. */ -/* TCA_SINGLE_CMP1 is already defined. */ -/* TCA_SINGLE_CMP2 is already defined. */ - -/* TCA_SINGLE.DBGCTRL bit masks and bit positions */ -#define TCA_SINGLE_DBGRUN_bm 0x01 /* Debug Run bit mask. */ -#define TCA_SINGLE_DBGRUN_bp 0 /* Debug Run bit position. */ - - - - - - - - - - - -/* TCA_SPLIT.CTRLA bit masks and bit positions */ -#define TCA_SPLIT_ENABLE_bm 0x01 /* Module Enable bit mask. */ -#define TCA_SPLIT_ENABLE_bp 0 /* Module Enable bit position. */ -#define TCA_SPLIT_CLKSEL_gm 0x0E /* Clock Selection group mask. */ -#define TCA_SPLIT_CLKSEL_gp 1 /* Clock Selection group position. */ -#define TCA_SPLIT_CLKSEL0_bm (1<<1) /* Clock Selection bit 0 mask. */ -#define TCA_SPLIT_CLKSEL0_bp 1 /* Clock Selection bit 0 position. */ -#define TCA_SPLIT_CLKSEL1_bm (1<<2) /* Clock Selection bit 1 mask. */ -#define TCA_SPLIT_CLKSEL1_bp 2 /* Clock Selection bit 1 position. */ -#define TCA_SPLIT_CLKSEL2_bm (1<<3) /* Clock Selection bit 2 mask. */ -#define TCA_SPLIT_CLKSEL2_bp 3 /* Clock Selection bit 2 position. */ - -/* TCA_SPLIT.CTRLB bit masks and bit positions */ -#define TCA_SPLIT_LCMP0EN_bm 0x01 /* Low Compare 0 Enable bit mask. */ -#define TCA_SPLIT_LCMP0EN_bp 0 /* Low Compare 0 Enable bit position. */ -#define TCA_SPLIT_LCMP1EN_bm 0x02 /* Low Compare 1 Enable bit mask. */ -#define TCA_SPLIT_LCMP1EN_bp 1 /* Low Compare 1 Enable bit position. */ -#define TCA_SPLIT_LCMP2EN_bm 0x04 /* Low Compare 2 Enable bit mask. */ -#define TCA_SPLIT_LCMP2EN_bp 2 /* Low Compare 2 Enable bit position. */ -#define TCA_SPLIT_HCMP0EN_bm 0x10 /* High Compare 0 Enable bit mask. */ -#define TCA_SPLIT_HCMP0EN_bp 4 /* High Compare 0 Enable bit position. */ -#define TCA_SPLIT_HCMP1EN_bm 0x20 /* High Compare 1 Enable bit mask. */ -#define TCA_SPLIT_HCMP1EN_bp 5 /* High Compare 1 Enable bit position. */ -#define TCA_SPLIT_HCMP2EN_bm 0x40 /* High Compare 2 Enable bit mask. */ -#define TCA_SPLIT_HCMP2EN_bp 6 /* High Compare 2 Enable bit position. */ - -/* TCA_SPLIT.CTRLC bit masks and bit positions */ -#define TCA_SPLIT_LCMP0OV_bm 0x01 /* Low Compare 0 Output Value bit mask. */ -#define TCA_SPLIT_LCMP0OV_bp 0 /* Low Compare 0 Output Value bit position. */ -#define TCA_SPLIT_LCMP1OV_bm 0x02 /* Low Compare 1 Output Value bit mask. */ -#define TCA_SPLIT_LCMP1OV_bp 1 /* Low Compare 1 Output Value bit position. */ -#define TCA_SPLIT_LCMP2OV_bm 0x04 /* Low Compare 2 Output Value bit mask. */ -#define TCA_SPLIT_LCMP2OV_bp 2 /* Low Compare 2 Output Value bit position. */ -#define TCA_SPLIT_HCMP0OV_bm 0x10 /* High Compare 0 Output Value bit mask. */ -#define TCA_SPLIT_HCMP0OV_bp 4 /* High Compare 0 Output Value bit position. */ -#define TCA_SPLIT_HCMP1OV_bm 0x20 /* High Compare 1 Output Value bit mask. */ -#define TCA_SPLIT_HCMP1OV_bp 5 /* High Compare 1 Output Value bit position. */ -#define TCA_SPLIT_HCMP2OV_bm 0x40 /* High Compare 2 Output Value bit mask. */ -#define TCA_SPLIT_HCMP2OV_bp 6 /* High Compare 2 Output Value bit position. */ - -/* TCA_SPLIT.CTRLD bit masks and bit positions */ -#define TCA_SPLIT_SPLITM_bm 0x01 /* Split Mode Enable bit mask. */ -#define TCA_SPLIT_SPLITM_bp 0 /* Split Mode Enable bit position. */ - -/* TCA_SPLIT.CTRLECLR bit masks and bit positions */ -#define TCA_SPLIT_CMD_gm 0x0C /* Command group mask. */ -#define TCA_SPLIT_CMD_gp 2 /* Command group position. */ -#define TCA_SPLIT_CMD0_bm (1<<2) /* Command bit 0 mask. */ -#define TCA_SPLIT_CMD0_bp 2 /* Command bit 0 position. */ -#define TCA_SPLIT_CMD1_bm (1<<3) /* Command bit 1 mask. */ -#define TCA_SPLIT_CMD1_bp 3 /* Command bit 1 position. */ - -/* TCA_SPLIT.CTRLESET bit masks and bit positions */ -/* TCA_SPLIT_CMD is already defined. */ - -/* TCA_SPLIT.INTCTRL bit masks and bit positions */ -#define TCA_SPLIT_LUNF_bm 0x01 /* Low Underflow Interrupt Enable bit mask. */ -#define TCA_SPLIT_LUNF_bp 0 /* Low Underflow Interrupt Enable bit position. */ -#define TCA_SPLIT_HUNF_bm 0x02 /* High Underflow Interrupt Enable bit mask. */ -#define TCA_SPLIT_HUNF_bp 1 /* High Underflow Interrupt Enable bit position. */ -#define TCA_SPLIT_LCMP0_bm 0x10 /* Low Compare 0 Interrupt Enable bit mask. */ -#define TCA_SPLIT_LCMP0_bp 4 /* Low Compare 0 Interrupt Enable bit position. */ -#define TCA_SPLIT_LCMP1_bm 0x20 /* Low Compare 1 Interrupt Enable bit mask. */ -#define TCA_SPLIT_LCMP1_bp 5 /* Low Compare 1 Interrupt Enable bit position. */ -#define TCA_SPLIT_LCMP2_bm 0x40 /* Low Compare 2 Interrupt Enable bit mask. */ -#define TCA_SPLIT_LCMP2_bp 6 /* Low Compare 2 Interrupt Enable bit position. */ - -/* TCA_SPLIT.INTFLAGS bit masks and bit positions */ -/* TCA_SPLIT_LUNF is already defined. */ -/* TCA_SPLIT_HUNF is already defined. */ -/* TCA_SPLIT_LCMP0 is already defined. */ -/* TCA_SPLIT_LCMP1 is already defined. */ -/* TCA_SPLIT_LCMP2 is already defined. */ - -/* TCA_SPLIT.DBGCTRL bit masks and bit positions */ -#define TCA_SPLIT_DBGRUN_bm 0x01 /* Debug Run bit mask. */ -#define TCA_SPLIT_DBGRUN_bp 0 /* Debug Run bit position. */ - - - - - - - - - - - -/* TCB - 16-bit Timer Type B */ -/* TCB.CTRLA bit masks and bit positions */ -#define TCB_ENABLE_bm 0x01 /* Enable bit mask. */ -#define TCB_ENABLE_bp 0 /* Enable bit position. */ -#define TCB_CLKSEL_gm 0x06 /* Clock Select group mask. */ -#define TCB_CLKSEL_gp 1 /* Clock Select group position. */ -#define TCB_CLKSEL0_bm (1<<1) /* Clock Select bit 0 mask. */ -#define TCB_CLKSEL0_bp 1 /* Clock Select bit 0 position. */ -#define TCB_CLKSEL1_bm (1<<2) /* Clock Select bit 1 mask. */ -#define TCB_CLKSEL1_bp 2 /* Clock Select bit 1 position. */ -#define TCB_SYNCUPD_bm 0x10 /* Synchronize Update bit mask. */ -#define TCB_SYNCUPD_bp 4 /* Synchronize Update bit position. */ -#define TCB_RUNSTDBY_bm 0x40 /* Run Standby bit mask. */ -#define TCB_RUNSTDBY_bp 6 /* Run Standby bit position. */ - -/* TCB.CTRLB bit masks and bit positions */ -#define TCB_CNTMODE_gm 0x07 /* Timer Mode group mask. */ -#define TCB_CNTMODE_gp 0 /* Timer Mode group position. */ -#define TCB_CNTMODE0_bm (1<<0) /* Timer Mode bit 0 mask. */ -#define TCB_CNTMODE0_bp 0 /* Timer Mode bit 0 position. */ -#define TCB_CNTMODE1_bm (1<<1) /* Timer Mode bit 1 mask. */ -#define TCB_CNTMODE1_bp 1 /* Timer Mode bit 1 position. */ -#define TCB_CNTMODE2_bm (1<<2) /* Timer Mode bit 2 mask. */ -#define TCB_CNTMODE2_bp 2 /* Timer Mode bit 2 position. */ -#define TCB_CCMPEN_bm 0x10 /* Pin Output Enable bit mask. */ -#define TCB_CCMPEN_bp 4 /* Pin Output Enable bit position. */ -#define TCB_CCMPINIT_bm 0x20 /* Pin Initial State bit mask. */ -#define TCB_CCMPINIT_bp 5 /* Pin Initial State bit position. */ -#define TCB_ASYNC_bm 0x40 /* Asynchronous Enable bit mask. */ -#define TCB_ASYNC_bp 6 /* Asynchronous Enable bit position. */ - -/* TCB.EVCTRL bit masks and bit positions */ -#define TCB_CAPTEI_bm 0x01 /* Event Input Enable bit mask. */ -#define TCB_CAPTEI_bp 0 /* Event Input Enable bit position. */ -#define TCB_EDGE_bm 0x10 /* Event Edge bit mask. */ -#define TCB_EDGE_bp 4 /* Event Edge bit position. */ -#define TCB_FILTER_bm 0x40 /* Input Capture Noise Cancellation Filter bit mask. */ -#define TCB_FILTER_bp 6 /* Input Capture Noise Cancellation Filter bit position. */ - -/* TCB.INTCTRL bit masks and bit positions */ -#define TCB_CAPT_bm 0x01 /* Capture or Timeout bit mask. */ -#define TCB_CAPT_bp 0 /* Capture or Timeout bit position. */ - -/* TCB.INTFLAGS bit masks and bit positions */ -/* TCB_CAPT is already defined. */ - -/* TCB.STATUS bit masks and bit positions */ -#define TCB_RUN_bm 0x01 /* Run bit mask. */ -#define TCB_RUN_bp 0 /* Run bit position. */ - -/* TCB.DBGCTRL bit masks and bit positions */ -#define TCB_DBGRUN_bm 0x01 /* Debug Run bit mask. */ -#define TCB_DBGRUN_bp 0 /* Debug Run bit position. */ - - - - -/* TWI - Two-Wire Interface */ -/* TWI.CTRLA bit masks and bit positions */ -#define TWI_FMPEN_bm 0x02 /* FM Plus Enable bit mask. */ -#define TWI_FMPEN_bp 1 /* FM Plus Enable bit position. */ -#define TWI_SDAHOLD_gm 0x0C /* SDA Hold Time group mask. */ -#define TWI_SDAHOLD_gp 2 /* SDA Hold Time group position. */ -#define TWI_SDAHOLD0_bm (1<<2) /* SDA Hold Time bit 0 mask. */ -#define TWI_SDAHOLD0_bp 2 /* SDA Hold Time bit 0 position. */ -#define TWI_SDAHOLD1_bm (1<<3) /* SDA Hold Time bit 1 mask. */ -#define TWI_SDAHOLD1_bp 3 /* SDA Hold Time bit 1 position. */ -#define TWI_SDASETUP_bm 0x10 /* SDA Setup Time bit mask. */ -#define TWI_SDASETUP_bp 4 /* SDA Setup Time bit position. */ - -/* TWI.BRIDGECTRL bit masks and bit positions */ -#define TWI_ENABLE_bm 0x01 /* Bridge Enable bit mask. */ -#define TWI_ENABLE_bp 0 /* Bridge Enable bit position. */ -/* TWI_FMPEN is already defined. */ -/* TWI_SDAHOLD is already defined. */ - -/* TWI.DBGCTRL bit masks and bit positions */ -#define TWI_DBGRUN_bm 0x01 /* Debug Run bit mask. */ -#define TWI_DBGRUN_bp 0 /* Debug Run bit position. */ - -/* TWI.MCTRLA bit masks and bit positions */ -/* TWI_ENABLE is already defined. */ -#define TWI_SMEN_bm 0x02 /* Smart Mode Enable bit mask. */ -#define TWI_SMEN_bp 1 /* Smart Mode Enable bit position. */ -#define TWI_TIMEOUT_gm 0x0C /* Inactive Bus Timeout group mask. */ -#define TWI_TIMEOUT_gp 2 /* Inactive Bus Timeout group position. */ -#define TWI_TIMEOUT0_bm (1<<2) /* Inactive Bus Timeout bit 0 mask. */ -#define TWI_TIMEOUT0_bp 2 /* Inactive Bus Timeout bit 0 position. */ -#define TWI_TIMEOUT1_bm (1<<3) /* Inactive Bus Timeout bit 1 mask. */ -#define TWI_TIMEOUT1_bp 3 /* Inactive Bus Timeout bit 1 position. */ -#define TWI_QCEN_bm 0x10 /* Quick Command Enable bit mask. */ -#define TWI_QCEN_bp 4 /* Quick Command Enable bit position. */ -#define TWI_WIEN_bm 0x40 /* Write Interrupt Enable bit mask. */ -#define TWI_WIEN_bp 6 /* Write Interrupt Enable bit position. */ -#define TWI_RIEN_bm 0x80 /* Read Interrupt Enable bit mask. */ -#define TWI_RIEN_bp 7 /* Read Interrupt Enable bit position. */ - -/* TWI.MCTRLB bit masks and bit positions */ -#define TWI_MCMD_gm 0x03 /* Command group mask. */ -#define TWI_MCMD_gp 0 /* Command group position. */ -#define TWI_MCMD0_bm (1<<0) /* Command bit 0 mask. */ -#define TWI_MCMD0_bp 0 /* Command bit 0 position. */ -#define TWI_MCMD1_bm (1<<1) /* Command bit 1 mask. */ -#define TWI_MCMD1_bp 1 /* Command bit 1 position. */ -#define TWI_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ -#define TWI_ACKACT_bp 2 /* Acknowledge Action bit position. */ -#define TWI_FLUSH_bm 0x08 /* Flush bit mask. */ -#define TWI_FLUSH_bp 3 /* Flush bit position. */ - -/* TWI.MSTATUS bit masks and bit positions */ -#define TWI_BUSSTATE_gm 0x03 /* Bus State group mask. */ -#define TWI_BUSSTATE_gp 0 /* Bus State group position. */ -#define TWI_BUSSTATE0_bm (1<<0) /* Bus State bit 0 mask. */ -#define TWI_BUSSTATE0_bp 0 /* Bus State bit 0 position. */ -#define TWI_BUSSTATE1_bm (1<<1) /* Bus State bit 1 mask. */ -#define TWI_BUSSTATE1_bp 1 /* Bus State bit 1 position. */ -#define TWI_BUSERR_bm 0x04 /* Bus Error bit mask. */ -#define TWI_BUSERR_bp 2 /* Bus Error bit position. */ -#define TWI_ARBLOST_bm 0x08 /* Arbitration Lost bit mask. */ -#define TWI_ARBLOST_bp 3 /* Arbitration Lost bit position. */ -#define TWI_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ -#define TWI_RXACK_bp 4 /* Received Acknowledge bit position. */ -#define TWI_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ -#define TWI_CLKHOLD_bp 5 /* Clock Hold bit position. */ -#define TWI_WIF_bm 0x40 /* Write Interrupt Flag bit mask. */ -#define TWI_WIF_bp 6 /* Write Interrupt Flag bit position. */ -#define TWI_RIF_bm 0x80 /* Read Interrupt Flag bit mask. */ -#define TWI_RIF_bp 7 /* Read Interrupt Flag bit position. */ - - - - -/* TWI.SCTRLA bit masks and bit positions */ -/* TWI_ENABLE is already defined. */ -/* TWI_SMEN is already defined. */ -#define TWI_PMEN_bm 0x04 /* Promiscuous Mode Enable bit mask. */ -#define TWI_PMEN_bp 2 /* Promiscuous Mode Enable bit position. */ -#define TWI_PIEN_bm 0x20 /* Stop Interrupt Enable bit mask. */ -#define TWI_PIEN_bp 5 /* Stop Interrupt Enable bit position. */ -#define TWI_APIEN_bm 0x40 /* Address/Stop Interrupt Enable bit mask. */ -#define TWI_APIEN_bp 6 /* Address/Stop Interrupt Enable bit position. */ -#define TWI_DIEN_bm 0x80 /* Data Interrupt Enable bit mask. */ -#define TWI_DIEN_bp 7 /* Data Interrupt Enable bit position. */ - -/* TWI.SCTRLB bit masks and bit positions */ -#define TWI_SCMD_gm 0x03 /* Command group mask. */ -#define TWI_SCMD_gp 0 /* Command group position. */ -#define TWI_SCMD0_bm (1<<0) /* Command bit 0 mask. */ -#define TWI_SCMD0_bp 0 /* Command bit 0 position. */ -#define TWI_SCMD1_bm (1<<1) /* Command bit 1 mask. */ -#define TWI_SCMD1_bp 1 /* Command bit 1 position. */ -/* TWI_ACKACT is already defined. */ - -/* TWI.SSTATUS bit masks and bit positions */ -#define TWI_AP_bm 0x01 /* Slave Address or Stop bit mask. */ -#define TWI_AP_bp 0 /* Slave Address or Stop bit position. */ -#define TWI_DIR_bm 0x02 /* Read/Write Direction bit mask. */ -#define TWI_DIR_bp 1 /* Read/Write Direction bit position. */ -/* TWI_BUSERR is already defined. */ -#define TWI_COLL_bm 0x08 /* Collision bit mask. */ -#define TWI_COLL_bp 3 /* Collision bit position. */ -/* TWI_RXACK is already defined. */ -/* TWI_CLKHOLD is already defined. */ -#define TWI_APIF_bm 0x40 /* Address/Stop Interrupt Flag bit mask. */ -#define TWI_APIF_bp 6 /* Address/Stop Interrupt Flag bit position. */ -#define TWI_DIF_bm 0x80 /* Data Interrupt Flag bit mask. */ -#define TWI_DIF_bp 7 /* Data Interrupt Flag bit position. */ - - - -/* TWI.SADDRMASK bit masks and bit positions */ -#define TWI_ADDREN_bm 0x01 /* Address Enable bit mask. */ -#define TWI_ADDREN_bp 0 /* Address Enable bit position. */ -#define TWI_ADDRMASK_gm 0xFE /* Address Mask group mask. */ -#define TWI_ADDRMASK_gp 1 /* Address Mask group position. */ -#define TWI_ADDRMASK0_bm (1<<1) /* Address Mask bit 0 mask. */ -#define TWI_ADDRMASK0_bp 1 /* Address Mask bit 0 position. */ -#define TWI_ADDRMASK1_bm (1<<2) /* Address Mask bit 1 mask. */ -#define TWI_ADDRMASK1_bp 2 /* Address Mask bit 1 position. */ -#define TWI_ADDRMASK2_bm (1<<3) /* Address Mask bit 2 mask. */ -#define TWI_ADDRMASK2_bp 3 /* Address Mask bit 2 position. */ -#define TWI_ADDRMASK3_bm (1<<4) /* Address Mask bit 3 mask. */ -#define TWI_ADDRMASK3_bp 4 /* Address Mask bit 3 position. */ -#define TWI_ADDRMASK4_bm (1<<5) /* Address Mask bit 4 mask. */ -#define TWI_ADDRMASK4_bp 5 /* Address Mask bit 4 position. */ -#define TWI_ADDRMASK5_bm (1<<6) /* Address Mask bit 5 mask. */ -#define TWI_ADDRMASK5_bp 6 /* Address Mask bit 5 position. */ -#define TWI_ADDRMASK6_bm (1<<7) /* Address Mask bit 6 mask. */ -#define TWI_ADDRMASK6_bp 7 /* Address Mask bit 6 position. */ - -/* USART - Universal Synchronous and Asynchronous Receiver and Transmitter */ -/* USART.RXDATAL bit masks and bit positions */ -#define USART_DATA_gm 0xFF /* RX Data group mask. */ -#define USART_DATA_gp 0 /* RX Data group position. */ -#define USART_DATA0_bm (1<<0) /* RX Data bit 0 mask. */ -#define USART_DATA0_bp 0 /* RX Data bit 0 position. */ -#define USART_DATA1_bm (1<<1) /* RX Data bit 1 mask. */ -#define USART_DATA1_bp 1 /* RX Data bit 1 position. */ -#define USART_DATA2_bm (1<<2) /* RX Data bit 2 mask. */ -#define USART_DATA2_bp 2 /* RX Data bit 2 position. */ -#define USART_DATA3_bm (1<<3) /* RX Data bit 3 mask. */ -#define USART_DATA3_bp 3 /* RX Data bit 3 position. */ -#define USART_DATA4_bm (1<<4) /* RX Data bit 4 mask. */ -#define USART_DATA4_bp 4 /* RX Data bit 4 position. */ -#define USART_DATA5_bm (1<<5) /* RX Data bit 5 mask. */ -#define USART_DATA5_bp 5 /* RX Data bit 5 position. */ -#define USART_DATA6_bm (1<<6) /* RX Data bit 6 mask. */ -#define USART_DATA6_bp 6 /* RX Data bit 6 position. */ -#define USART_DATA7_bm (1<<7) /* RX Data bit 7 mask. */ -#define USART_DATA7_bp 7 /* RX Data bit 7 position. */ - -/* USART.RXDATAH bit masks and bit positions */ -#define USART_DATA8_bm 0x01 /* Receiver Data Register bit mask. */ -#define USART_DATA8_bp 0 /* Receiver Data Register bit position. */ -#define USART_PERR_bm 0x02 /* Parity Error bit mask. */ -#define USART_PERR_bp 1 /* Parity Error bit position. */ -#define USART_FERR_bm 0x04 /* Frame Error bit mask. */ -#define USART_FERR_bp 2 /* Frame Error bit position. */ -#define USART_BUFOVF_bm 0x40 /* Buffer Overflow bit mask. */ -#define USART_BUFOVF_bp 6 /* Buffer Overflow bit position. */ -#define USART_RXCIF_bm 0x80 /* Receive Complete Interrupt Flag bit mask. */ -#define USART_RXCIF_bp 7 /* Receive Complete Interrupt Flag bit position. */ - -/* USART.TXDATAL bit masks and bit positions */ -/* USART_DATA is already defined. */ - -/* USART.TXDATAH bit masks and bit positions */ -/* USART_DATA8 is already defined. */ - -/* USART.STATUS bit masks and bit positions */ -#define USART_WFB_bm 0x01 /* Wait For Break bit mask. */ -#define USART_WFB_bp 0 /* Wait For Break bit position. */ -#define USART_BDF_bm 0x02 /* Break Detected Flag bit mask. */ -#define USART_BDF_bp 1 /* Break Detected Flag bit position. */ -#define USART_ISFIF_bm 0x08 /* Inconsistent Sync Field Interrupt Flag bit mask. */ -#define USART_ISFIF_bp 3 /* Inconsistent Sync Field Interrupt Flag bit position. */ -#define USART_RXSIF_bm 0x10 /* Receive Start Interrupt bit mask. */ -#define USART_RXSIF_bp 4 /* Receive Start Interrupt bit position. */ -#define USART_DREIF_bm 0x20 /* Data Register Empty Flag bit mask. */ -#define USART_DREIF_bp 5 /* Data Register Empty Flag bit position. */ -#define USART_TXCIF_bm 0x40 /* Transmit Interrupt Flag bit mask. */ -#define USART_TXCIF_bp 6 /* Transmit Interrupt Flag bit position. */ -/* USART_RXCIF is already defined. */ - -/* USART.CTRLA bit masks and bit positions */ -#define USART_RS485_gm 0x03 /* RS485 Mode internal transmitter group mask. */ -#define USART_RS485_gp 0 /* RS485 Mode internal transmitter group position. */ -#define USART_RS4850_bm (1<<0) /* RS485 Mode internal transmitter bit 0 mask. */ -#define USART_RS4850_bp 0 /* RS485 Mode internal transmitter bit 0 position. */ -#define USART_RS4851_bm (1<<1) /* RS485 Mode internal transmitter bit 1 mask. */ -#define USART_RS4851_bp 1 /* RS485 Mode internal transmitter bit 1 position. */ -#define USART_ABEIE_bm 0x04 /* Auto-baud Error Interrupt Enable bit mask. */ -#define USART_ABEIE_bp 2 /* Auto-baud Error Interrupt Enable bit position. */ -#define USART_LBME_bm 0x08 /* Loop-back Mode Enable bit mask. */ -#define USART_LBME_bp 3 /* Loop-back Mode Enable bit position. */ -#define USART_RXSIE_bm 0x10 /* Receiver Start Frame Interrupt Enable bit mask. */ -#define USART_RXSIE_bp 4 /* Receiver Start Frame Interrupt Enable bit position. */ -#define USART_DREIE_bm 0x20 /* Data Register Empty Interrupt Enable bit mask. */ -#define USART_DREIE_bp 5 /* Data Register Empty Interrupt Enable bit position. */ -#define USART_TXCIE_bm 0x40 /* Transmit Complete Interrupt Enable bit mask. */ -#define USART_TXCIE_bp 6 /* Transmit Complete Interrupt Enable bit position. */ -#define USART_RXCIE_bm 0x80 /* Receive Complete Interrupt Enable bit mask. */ -#define USART_RXCIE_bp 7 /* Receive Complete Interrupt Enable bit position. */ - -/* USART.CTRLB bit masks and bit positions */ -#define USART_MPCM_bm 0x01 /* Multi-processor Communication Mode bit mask. */ -#define USART_MPCM_bp 0 /* Multi-processor Communication Mode bit position. */ -#define USART_RXMODE_gm 0x06 /* Receiver Mode group mask. */ -#define USART_RXMODE_gp 1 /* Receiver Mode group position. */ -#define USART_RXMODE0_bm (1<<1) /* Receiver Mode bit 0 mask. */ -#define USART_RXMODE0_bp 1 /* Receiver Mode bit 0 position. */ -#define USART_RXMODE1_bm (1<<2) /* Receiver Mode bit 1 mask. */ -#define USART_RXMODE1_bp 2 /* Receiver Mode bit 1 position. */ -#define USART_ODME_bm 0x08 /* Open Drain Mode Enable bit mask. */ -#define USART_ODME_bp 3 /* Open Drain Mode Enable bit position. */ -#define USART_SFDEN_bm 0x10 /* Start Frame Detection Enable bit mask. */ -#define USART_SFDEN_bp 4 /* Start Frame Detection Enable bit position. */ -#define USART_TXEN_bm 0x40 /* Transmitter Enable bit mask. */ -#define USART_TXEN_bp 6 /* Transmitter Enable bit position. */ -#define USART_RXEN_bm 0x80 /* Reciever enable bit mask. */ -#define USART_RXEN_bp 7 /* Reciever enable bit position. */ - -/* USART.CTRLC bit masks and bit positions */ -#define USART_UCPHA_bm 0x02 /* SPI Master Mode, Clock Phase bit mask. */ -#define USART_UCPHA_bp 1 /* SPI Master Mode, Clock Phase bit position. */ -#define USART_UDORD_bm 0x04 /* SPI Master Mode, Data Order bit mask. */ -#define USART_UDORD_bp 2 /* SPI Master Mode, Data Order bit position. */ -#define USART_CHSIZE_gm 0x07 /* Character Size group mask. */ -#define USART_CHSIZE_gp 0 /* Character Size group position. */ -#define USART_CHSIZE0_bm (1<<0) /* Character Size bit 0 mask. */ -#define USART_CHSIZE0_bp 0 /* Character Size bit 0 position. */ -#define USART_CHSIZE1_bm (1<<1) /* Character Size bit 1 mask. */ -#define USART_CHSIZE1_bp 1 /* Character Size bit 1 position. */ -#define USART_CHSIZE2_bm (1<<2) /* Character Size bit 2 mask. */ -#define USART_CHSIZE2_bp 2 /* Character Size bit 2 position. */ -#define USART_SBMODE_bm 0x08 /* Stop Bit Mode bit mask. */ -#define USART_SBMODE_bp 3 /* Stop Bit Mode bit position. */ -#define USART_PMODE_gm 0x30 /* Parity Mode group mask. */ -#define USART_PMODE_gp 4 /* Parity Mode group position. */ -#define USART_PMODE0_bm (1<<4) /* Parity Mode bit 0 mask. */ -#define USART_PMODE0_bp 4 /* Parity Mode bit 0 position. */ -#define USART_PMODE1_bm (1<<5) /* Parity Mode bit 1 mask. */ -#define USART_PMODE1_bp 5 /* Parity Mode bit 1 position. */ -#define USART_CMODE_gm 0xC0 /* Communication Mode group mask. */ -#define USART_CMODE_gp 6 /* Communication Mode group position. */ -#define USART_CMODE0_bm (1<<6) /* Communication Mode bit 0 mask. */ -#define USART_CMODE0_bp 6 /* Communication Mode bit 0 position. */ -#define USART_CMODE1_bm (1<<7) /* Communication Mode bit 1 mask. */ -#define USART_CMODE1_bp 7 /* Communication Mode bit 1 position. */ - - - -/* USART.DBGCTRL bit masks and bit positions */ -#define USART_DBGRUN_bm 0x01 /* Debug Run bit mask. */ -#define USART_DBGRUN_bp 0 /* Debug Run bit position. */ -#define USART_ABMBP_bm 0x80 /* Autobaud majority voter bypass bit mask. */ -#define USART_ABMBP_bp 7 /* Autobaud majority voter bypass bit position. */ - -/* USART.EVCTRL bit masks and bit positions */ -#define USART_IREI_bm 0x01 /* IrDA Event Input Enable bit mask. */ -#define USART_IREI_bp 0 /* IrDA Event Input Enable bit position. */ - -/* USART.TXPLCTRL bit masks and bit positions */ -#define USART_TXPL_gm 0xFF /* Transmit pulse length group mask. */ -#define USART_TXPL_gp 0 /* Transmit pulse length group position. */ -#define USART_TXPL0_bm (1<<0) /* Transmit pulse length bit 0 mask. */ -#define USART_TXPL0_bp 0 /* Transmit pulse length bit 0 position. */ -#define USART_TXPL1_bm (1<<1) /* Transmit pulse length bit 1 mask. */ -#define USART_TXPL1_bp 1 /* Transmit pulse length bit 1 position. */ -#define USART_TXPL2_bm (1<<2) /* Transmit pulse length bit 2 mask. */ -#define USART_TXPL2_bp 2 /* Transmit pulse length bit 2 position. */ -#define USART_TXPL3_bm (1<<3) /* Transmit pulse length bit 3 mask. */ -#define USART_TXPL3_bp 3 /* Transmit pulse length bit 3 position. */ -#define USART_TXPL4_bm (1<<4) /* Transmit pulse length bit 4 mask. */ -#define USART_TXPL4_bp 4 /* Transmit pulse length bit 4 position. */ -#define USART_TXPL5_bm (1<<5) /* Transmit pulse length bit 5 mask. */ -#define USART_TXPL5_bp 5 /* Transmit pulse length bit 5 position. */ -#define USART_TXPL6_bm (1<<6) /* Transmit pulse length bit 6 mask. */ -#define USART_TXPL6_bp 6 /* Transmit pulse length bit 6 position. */ -#define USART_TXPL7_bm (1<<7) /* Transmit pulse length bit 7 mask. */ -#define USART_TXPL7_bp 7 /* Transmit pulse length bit 7 position. */ - -/* USART.RXPLCTRL bit masks and bit positions */ -#define USART_RXPL_gm 0x7F /* Receiver Pulse Lenght group mask. */ -#define USART_RXPL_gp 0 /* Receiver Pulse Lenght group position. */ -#define USART_RXPL0_bm (1<<0) /* Receiver Pulse Lenght bit 0 mask. */ -#define USART_RXPL0_bp 0 /* Receiver Pulse Lenght bit 0 position. */ -#define USART_RXPL1_bm (1<<1) /* Receiver Pulse Lenght bit 1 mask. */ -#define USART_RXPL1_bp 1 /* Receiver Pulse Lenght bit 1 position. */ -#define USART_RXPL2_bm (1<<2) /* Receiver Pulse Lenght bit 2 mask. */ -#define USART_RXPL2_bp 2 /* Receiver Pulse Lenght bit 2 position. */ -#define USART_RXPL3_bm (1<<3) /* Receiver Pulse Lenght bit 3 mask. */ -#define USART_RXPL3_bp 3 /* Receiver Pulse Lenght bit 3 position. */ -#define USART_RXPL4_bm (1<<4) /* Receiver Pulse Lenght bit 4 mask. */ -#define USART_RXPL4_bp 4 /* Receiver Pulse Lenght bit 4 position. */ -#define USART_RXPL5_bm (1<<5) /* Receiver Pulse Lenght bit 5 mask. */ -#define USART_RXPL5_bp 5 /* Receiver Pulse Lenght bit 5 position. */ -#define USART_RXPL6_bm (1<<6) /* Receiver Pulse Lenght bit 6 mask. */ -#define USART_RXPL6_bp 6 /* Receiver Pulse Lenght bit 6 position. */ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -/* VPORT - Virtual Ports */ -/* VPORT.INTFLAGS bit masks and bit positions */ -#define VPORT_INT_gm 0xFF /* Pin Interrupt group mask. */ -#define VPORT_INT_gp 0 /* Pin Interrupt group position. */ -#define VPORT_INT0_bm (1<<0) /* Pin Interrupt bit 0 mask. */ -#define VPORT_INT0_bp 0 /* Pin Interrupt bit 0 position. */ -#define VPORT_INT1_bm (1<<1) /* Pin Interrupt bit 1 mask. */ -#define VPORT_INT1_bp 1 /* Pin Interrupt bit 1 position. */ -#define VPORT_INT2_bm (1<<2) /* Pin Interrupt bit 2 mask. */ -#define VPORT_INT2_bp 2 /* Pin Interrupt bit 2 position. */ -#define VPORT_INT3_bm (1<<3) /* Pin Interrupt bit 3 mask. */ -#define VPORT_INT3_bp 3 /* Pin Interrupt bit 3 position. */ -#define VPORT_INT4_bm (1<<4) /* Pin Interrupt bit 4 mask. */ -#define VPORT_INT4_bp 4 /* Pin Interrupt bit 4 position. */ -#define VPORT_INT5_bm (1<<5) /* Pin Interrupt bit 5 mask. */ -#define VPORT_INT5_bp 5 /* Pin Interrupt bit 5 position. */ -#define VPORT_INT6_bm (1<<6) /* Pin Interrupt bit 6 mask. */ -#define VPORT_INT6_bp 6 /* Pin Interrupt bit 6 position. */ -#define VPORT_INT7_bm (1<<7) /* Pin Interrupt bit 7 mask. */ -#define VPORT_INT7_bp 7 /* Pin Interrupt bit 7 position. */ - -/* VREF - Voltage reference */ -/* VREF.CTRLA bit masks and bit positions */ -#define VREF_AC0REFSEL_gm 0x07 /* AC0 reference select group mask. */ -#define VREF_AC0REFSEL_gp 0 /* AC0 reference select group position. */ -#define VREF_AC0REFSEL0_bm (1<<0) /* AC0 reference select bit 0 mask. */ -#define VREF_AC0REFSEL0_bp 0 /* AC0 reference select bit 0 position. */ -#define VREF_AC0REFSEL1_bm (1<<1) /* AC0 reference select bit 1 mask. */ -#define VREF_AC0REFSEL1_bp 1 /* AC0 reference select bit 1 position. */ -#define VREF_AC0REFSEL2_bm (1<<2) /* AC0 reference select bit 2 mask. */ -#define VREF_AC0REFSEL2_bp 2 /* AC0 reference select bit 2 position. */ -#define VREF_ADC0REFSEL_gm 0x70 /* ADC0 reference select group mask. */ -#define VREF_ADC0REFSEL_gp 4 /* ADC0 reference select group position. */ -#define VREF_ADC0REFSEL0_bm (1<<4) /* ADC0 reference select bit 0 mask. */ -#define VREF_ADC0REFSEL0_bp 4 /* ADC0 reference select bit 0 position. */ -#define VREF_ADC0REFSEL1_bm (1<<5) /* ADC0 reference select bit 1 mask. */ -#define VREF_ADC0REFSEL1_bp 5 /* ADC0 reference select bit 1 position. */ -#define VREF_ADC0REFSEL2_bm (1<<6) /* ADC0 reference select bit 2 mask. */ -#define VREF_ADC0REFSEL2_bp 6 /* ADC0 reference select bit 2 position. */ - -/* VREF.CTRLB bit masks and bit positions */ -#define VREF_AC0REFEN_bm 0x01 /* AC0 DACREF reference enable bit mask. */ -#define VREF_AC0REFEN_bp 0 /* AC0 DACREF reference enable bit position. */ -#define VREF_ADC0REFEN_bm 0x02 /* ADC0 reference enable bit mask. */ -#define VREF_ADC0REFEN_bp 1 /* ADC0 reference enable bit position. */ -#define VREF_NVMREFEN_bm 0x04 /* NVM reference enable bit mask. */ -#define VREF_NVMREFEN_bp 2 /* NVM reference enable bit position. */ - -/* WDT - Watch-Dog Timer */ -/* WDT.CTRLA bit masks and bit positions */ -#define WDT_PERIOD_gm 0x0F /* Period group mask. */ -#define WDT_PERIOD_gp 0 /* Period group position. */ -#define WDT_PERIOD0_bm (1<<0) /* Period bit 0 mask. */ -#define WDT_PERIOD0_bp 0 /* Period bit 0 position. */ -#define WDT_PERIOD1_bm (1<<1) /* Period bit 1 mask. */ -#define WDT_PERIOD1_bp 1 /* Period bit 1 position. */ -#define WDT_PERIOD2_bm (1<<2) /* Period bit 2 mask. */ -#define WDT_PERIOD2_bp 2 /* Period bit 2 position. */ -#define WDT_PERIOD3_bm (1<<3) /* Period bit 3 mask. */ -#define WDT_PERIOD3_bp 3 /* Period bit 3 position. */ -#define WDT_WINDOW_gm 0xF0 /* Window group mask. */ -#define WDT_WINDOW_gp 4 /* Window group position. */ -#define WDT_WINDOW0_bm (1<<4) /* Window bit 0 mask. */ -#define WDT_WINDOW0_bp 4 /* Window bit 0 position. */ -#define WDT_WINDOW1_bm (1<<5) /* Window bit 1 mask. */ -#define WDT_WINDOW1_bp 5 /* Window bit 1 position. */ -#define WDT_WINDOW2_bm (1<<6) /* Window bit 2 mask. */ -#define WDT_WINDOW2_bp 6 /* Window bit 2 position. */ -#define WDT_WINDOW3_bm (1<<7) /* Window bit 3 mask. */ -#define WDT_WINDOW3_bp 7 /* Window bit 3 position. */ - -/* WDT.STATUS bit masks and bit positions */ -#define WDT_SYNCBUSY_bm 0x01 /* Syncronization busy bit mask. */ -#define WDT_SYNCBUSY_bp 0 /* Syncronization busy bit position. */ -#define WDT_LOCK_bm 0x80 /* Lock enable bit mask. */ -#define WDT_LOCK_bp 7 /* Lock enable bit position. */ - - - -// Generic Port Pins - -#define PIN0_bm 0x01 -#define PIN0_bp 0 -#define PIN1_bm 0x02 -#define PIN1_bp 1 -#define PIN2_bm 0x04 -#define PIN2_bp 2 -#define PIN3_bm 0x08 -#define PIN3_bp 3 -#define PIN4_bm 0x10 -#define PIN4_bp 4 -#define PIN5_bm 0x20 -#define PIN5_bp 5 -#define PIN6_bm 0x40 -#define PIN6_bp 6 -#define PIN7_bm 0x80 -#define PIN7_bp 7 - -/* ========== Interrupt Vector Definitions ========== */ -/* Vector 0 is the reset vector */ - -/* CRCSCAN interrupt vectors */ -#define CRCSCAN_NMI_vect_num 1 -#define CRCSCAN_NMI_vect _VECTOR(1) /* */ - -/* BOD interrupt vectors */ -#define BOD_VLM_vect_num 2 -#define BOD_VLM_vect _VECTOR(2) /* */ - -/* RTC interrupt vectors */ -#define RTC_CNT_vect_num 3 -#define RTC_CNT_vect _VECTOR(3) /* */ -#define RTC_PIT_vect_num 4 -#define RTC_PIT_vect _VECTOR(4) /* */ - -/* CCL interrupt vectors */ -#define CCL_CCL_vect_num 5 -#define CCL_CCL_vect _VECTOR(5) /* */ - -/* PORTA interrupt vectors */ -#define PORTA_PORT_vect_num 6 -#define PORTA_PORT_vect _VECTOR(6) /* */ - -/* TCA0 interrupt vectors */ -#define TCA0_LUNF_vect_num 7 -#define TCA0_LUNF_vect _VECTOR(7) /* */ -#define TCA0_OVF_vect_num 7 -#define TCA0_OVF_vect _VECTOR(7) /* */ -#define TCA0_HUNF_vect_num 8 -#define TCA0_HUNF_vect _VECTOR(8) /* */ -#define TCA0_LCMP0_vect_num 9 -#define TCA0_LCMP0_vect _VECTOR(9) /* */ -#define TCA0_CMP0_vect_num 9 -#define TCA0_CMP0_vect _VECTOR(9) /* */ -#define TCA0_CMP1_vect_num 10 -#define TCA0_CMP1_vect _VECTOR(10) /* */ -#define TCA0_LCMP1_vect_num 10 -#define TCA0_LCMP1_vect _VECTOR(10) /* */ -#define TCA0_CMP2_vect_num 11 -#define TCA0_CMP2_vect _VECTOR(11) /* */ -#define TCA0_LCMP2_vect_num 11 -#define TCA0_LCMP2_vect _VECTOR(11) /* */ - -/* TCB0 interrupt vectors */ -#define TCB0_INT_vect_num 12 -#define TCB0_INT_vect _VECTOR(12) /* */ - -/* TCB1 interrupt vectors */ -#define TCB1_INT_vect_num 13 -#define TCB1_INT_vect _VECTOR(13) /* */ - -/* TWI0 interrupt vectors */ -#define TWI0_TWIS_vect_num 14 -#define TWI0_TWIS_vect _VECTOR(14) /* */ -#define TWI0_TWIM_vect_num 15 -#define TWI0_TWIM_vect _VECTOR(15) /* */ - -/* SPI0 interrupt vectors */ -#define SPI0_INT_vect_num 16 -#define SPI0_INT_vect _VECTOR(16) /* */ - -/* USART0 interrupt vectors */ -#define USART0_RXC_vect_num 17 -#define USART0_RXC_vect _VECTOR(17) /* */ -#define USART0_DRE_vect_num 18 -#define USART0_DRE_vect _VECTOR(18) /* */ -#define USART0_TXC_vect_num 19 -#define USART0_TXC_vect _VECTOR(19) /* */ - -/* PORTD interrupt vectors */ -#define PORTD_PORT_vect_num 20 -#define PORTD_PORT_vect _VECTOR(20) /* */ - -/* AC0 interrupt vectors */ -#define AC0_AC_vect_num 21 -#define AC0_AC_vect _VECTOR(21) /* */ - -/* ADC0 interrupt vectors */ -#define ADC0_RESRDY_vect_num 22 -#define ADC0_RESRDY_vect _VECTOR(22) /* */ -#define ADC0_WCOMP_vect_num 23 -#define ADC0_WCOMP_vect _VECTOR(23) /* */ - -/* PORTC interrupt vectors */ -#define PORTC_PORT_vect_num 24 -#define PORTC_PORT_vect _VECTOR(24) /* */ - -/* TCB2 interrupt vectors */ -#define TCB2_INT_vect_num 25 -#define TCB2_INT_vect _VECTOR(25) /* */ - -/* USART1 interrupt vectors */ -#define USART1_RXC_vect_num 26 -#define USART1_RXC_vect _VECTOR(26) /* */ -#define USART1_DRE_vect_num 27 -#define USART1_DRE_vect _VECTOR(27) /* */ -#define USART1_TXC_vect_num 28 -#define USART1_TXC_vect _VECTOR(28) /* */ - -/* PORTF interrupt vectors */ -#define PORTF_PORT_vect_num 29 -#define PORTF_PORT_vect _VECTOR(29) /* */ - -/* NVMCTRL interrupt vectors */ -#define NVMCTRL_EE_vect_num 30 -#define NVMCTRL_EE_vect _VECTOR(30) /* */ - -/* PORTB interrupt vectors */ -#define PORTB_PORT_vect_num 34 -#define PORTB_PORT_vect _VECTOR(34) /* */ - -/* PORTE interrupt vectors */ -#define PORTE_PORT_vect_num 35 -#define PORTE_PORT_vect _VECTOR(35) /* */ - -#define _VECTOR_SIZE 4 /* Size of individual vector. */ -#define _VECTORS_SIZE (36 * _VECTOR_SIZE) - - -/* ========== Constants ========== */ - -#define DATAMEM_START (0x0000) -#define DATAMEM_SIZE (32768) -#define DATAMEM_END (DATAMEM_START + DATAMEM_SIZE - 1) - -#define EEPROM_START (0x1400) -#define EEPROM_SIZE (256) -#define EEPROM_PAGE_SIZE (64) -#define EEPROM_END (EEPROM_START + EEPROM_SIZE - 1) - -/* Added MAPPED_EEPROM segment names for avr-libc */ -#define MAPPED_EEPROM_START (EEPROM_START) -#define MAPPED_EEPROM_SIZE (EEPROM_SIZE) -#define MAPPED_EEPROM_PAGE_SIZE (EEPROM_PAGE_SIZE) -#define MAPPED_EEPROM_END (MAPPED_EEPROM_START + MAPPED_EEPROM_SIZE - 1) - -#define FUSES_START (0x1280) -#define FUSES_SIZE (10) -#define FUSES_PAGE_SIZE (64) -#define FUSES_END (FUSES_START + FUSES_SIZE - 1) - -#define INTERNAL_SRAM_START (0x3000) -#define INTERNAL_SRAM_SIZE (4096) -#define INTERNAL_SRAM_PAGE_SIZE (0) -#define INTERNAL_SRAM_END (INTERNAL_SRAM_START + INTERNAL_SRAM_SIZE - 1) - -#define IO_START (0x0000) -#define IO_SIZE (4352) -#define IO_PAGE_SIZE (0) -#define IO_END (IO_START + IO_SIZE - 1) - -#define LOCKBITS_START (0x128A) -#define LOCKBITS_SIZE (1) -#define LOCKBITS_PAGE_SIZE (64) -#define LOCKBITS_END (LOCKBITS_START + LOCKBITS_SIZE - 1) - -#define MAPPED_PROGMEM_START (0x4000) -#define MAPPED_PROGMEM_SIZE (32768) -#define MAPPED_PROGMEM_PAGE_SIZE (128) -#define MAPPED_PROGMEM_END (MAPPED_PROGMEM_START + MAPPED_PROGMEM_SIZE - 1) - -#define PROD_SIGNATURES_START (0x1103) -#define PROD_SIGNATURES_SIZE (125) -#define PROD_SIGNATURES_PAGE_SIZE (128) -#define PROD_SIGNATURES_END (PROD_SIGNATURES_START + PROD_SIGNATURES_SIZE - 1) - -#define SIGNATURES_START (0x1100) -#define SIGNATURES_SIZE (3) -#define SIGNATURES_PAGE_SIZE (128) -#define SIGNATURES_END (SIGNATURES_START + SIGNATURES_SIZE - 1) - -#define USER_SIGNATURES_START (0x1300) -#define USER_SIGNATURES_SIZE (64) -#define USER_SIGNATURES_PAGE_SIZE (64) -#define USER_SIGNATURES_END (USER_SIGNATURES_START + USER_SIGNATURES_SIZE - 1) - -#define PROGMEM_START (0x0000) -#define PROGMEM_SIZE (32768) -#define PROGMEM_END (PROGMEM_START + PROGMEM_SIZE - 1) - -#define PROGMEM_START (0x0000) -#define PROGMEM_SIZE (32768) -#define PROGMEM_PAGE_SIZE (128) -#define PROGMEM_END (PROGMEM_START + PROGMEM_SIZE - 1) - -#define FLASHSTART PROGMEM_START -#define FLASHEND PROGMEM_END -#define RAMSTART INTERNAL_SRAM_START -#define RAMSIZE INTERNAL_SRAM_SIZE -#define RAMEND INTERNAL_SRAM_END -#define E2END EEPROM_END -#define E2PAGESIZE EEPROM_PAGE_SIZE - - -/* ========== Fuses ========== */ -#define FUSE_MEMORY_SIZE 9 - -/* Fuse Byte 0 Reserved */ - -/* Fuse Byte 1 Reserved */ - -/* Fuse Byte 2 Reserved */ - -/* Fuse Byte 3 Reserved */ - -/* Fuse Byte 4 Reserved */ - -/* Fuse Byte 5 Reserved */ - -/* Fuse Byte 6 Reserved */ - -/* Fuse Byte 7 */ - -/* Fuse Byte 8 */ -#define FUSE_SLEEP0 (unsigned char)~_BV(0) /* BOD Operation in Sleep Mode Bit 0 */ -#define FUSE_SLEEP1 (unsigned char)~_BV(1) /* BOD Operation in Sleep Mode Bit 1 */ -#define FUSE_ACTIVE0 (unsigned char)~_BV(2) /* BOD Operation in Active Mode Bit 0 */ -#define FUSE_ACTIVE1 (unsigned char)~_BV(3) /* BOD Operation in Active Mode Bit 1 */ -#define FUSE_SAMPFREQ (unsigned char)~_BV(4) /* BOD Sample Frequency */ -#define FUSE_LVL0 (unsigned char)~_BV(5) /* BOD Level Bit 0 */ -#define FUSE_LVL1 (unsigned char)~_BV(6) /* BOD Level Bit 1 */ -#define FUSE_LVL2 (unsigned char)~_BV(7) /* BOD Level Bit 2 */ - -/* Fuse Byte 9 */ - -/* Fuse Byte 10 */ -#define FUSE_FREQSEL0 (unsigned char)~_BV(0) /* Frequency Select Bit 0 */ -#define FUSE_FREQSEL1 (unsigned char)~_BV(1) /* Frequency Select Bit 1 */ -#define FUSE_OSCLOCK (unsigned char)~_BV(7) /* Oscillator Lock */ - -/* Fuse Byte 11 */ -#define FUSE_EESAVE (unsigned char)~_BV(0) /* EEPROM Save */ -#define FUSE_RSTPINCFG0 (unsigned char)~_BV(2) /* Reset Pin Configuration Bit 0 */ -#define FUSE_RSTPINCFG1 (unsigned char)~_BV(3) /* Reset Pin Configuration Bit 1 */ -#define FUSE_CRCSRC0 (unsigned char)~_BV(6) /* CRC Source Bit 0 */ -#define FUSE_CRCSRC1 (unsigned char)~_BV(7) /* CRC Source Bit 1 */ - -/* Fuse Byte 12 */ -#define FUSE_SUT0 (unsigned char)~_BV(0) /* Startup Time Bit 0 */ -#define FUSE_SUT1 (unsigned char)~_BV(1) /* Startup Time Bit 1 */ -#define FUSE_SUT2 (unsigned char)~_BV(2) /* Startup Time Bit 2 */ - -/* Fuse Byte 13 */ -#define FUSE_CMPA (unsigned char)~_BV(0) /* Compare A Default Output Value */ -#define FUSE_CMPB (unsigned char)~_BV(1) /* Compare B Default Output Value */ -#define FUSE_CMPC (unsigned char)~_BV(2) /* Compare C Default Output Value */ -#define FUSE_CMPD (unsigned char)~_BV(3) /* Compare D Default Output Value */ -#define FUSE_CMPAEN (unsigned char)~_BV(4) /* Compare A Output Enable */ -#define FUSE_CMPBEN (unsigned char)~_BV(5) /* Compare B Output Enable */ -#define FUSE_CMPCEN (unsigned char)~_BV(6) /* Compare C Output Enable */ -#define FUSE_CMPDEN (unsigned char)~_BV(7) /* Compare D Output Enable */ - -/* Fuse Byte 14 */ -#define FUSE_PERIOD0 (unsigned char)~_BV(0) /* Watchdog Timeout Period Bit 0 */ -#define FUSE_PERIOD1 (unsigned char)~_BV(1) /* Watchdog Timeout Period Bit 1 */ -#define FUSE_PERIOD2 (unsigned char)~_BV(2) /* Watchdog Timeout Period Bit 2 */ -#define FUSE_PERIOD3 (unsigned char)~_BV(3) /* Watchdog Timeout Period Bit 3 */ -#define FUSE_WINDOW0 (unsigned char)~_BV(4) /* Watchdog Window Timeout Period Bit 0 */ -#define FUSE_WINDOW1 (unsigned char)~_BV(5) /* Watchdog Window Timeout Period Bit 1 */ -#define FUSE_WINDOW2 (unsigned char)~_BV(6) /* Watchdog Window Timeout Period Bit 2 */ -#define FUSE_WINDOW3 (unsigned char)~_BV(7) /* Watchdog Window Timeout Period Bit 3 */ - -/* ========== Lock Bits ========== */ -#define __LOCK_BITS_EXIST - -/* ========== Signature ========== */ -#define SIGNATURE_0 0x1E -#define SIGNATURE_1 0x95 -#define SIGNATURE_2 0x53 - - -#endif /* #ifdef _AVR_ATMEGA3209_H_INCLUDED */ - diff --git a/arduino/hardware/tools/avr/avr/include/avr/iom323.h b/arduino/hardware/tools/avr/avr/include/avr/iom323.h deleted file mode 100644 index 44ca227..0000000 --- a/arduino/hardware/tools/avr/avr/include/avr/iom323.h +++ /dev/null @@ -1,744 +0,0 @@ -/* Copyright (c) 2002, Marek Michalkiewicz - All rights reserved. - - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - * Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - * Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in - the documentation and/or other materials provided with the - distribution. - - * Neither the name of the copyright holders nor the names of - contributors may be used to endorse or promote products derived - from this software without specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. */ - -/* $Id: iom323.h 2234 2011-03-16 04:32:21Z arcanum $ */ - -/* avr/iom323.h - definitions for ATmega323 */ - -#ifndef _AVR_IOM323_H_ -#define _AVR_IOM323_H_ 1 - -/* This file should only be included from , never directly. */ - -#ifndef _AVR_IO_H_ -# error "Include instead of this file." -#endif - -#ifndef _AVR_IOXXX_H_ -# define _AVR_IOXXX_H_ "iom323.h" -#else -# error "Attempt to include more than one file." -#endif - -/* I/O registers */ - -/* TWI stands for "Two Wire Interface" or "TWI Was I2C(tm)" */ -#define TWBR _SFR_IO8(0x00) -#define TWSR _SFR_IO8(0x01) -#define TWAR _SFR_IO8(0x02) -#define TWDR _SFR_IO8(0x03) - -/* ADC */ -#ifndef __ASSEMBLER__ -#define ADC _SFR_IO16(0x04) -#endif -#define ADCW _SFR_IO16(0x04) -#define ADCL _SFR_IO8(0x04) -#define ADCH _SFR_IO8(0x05) -#define ADCSR _SFR_IO8(0x06) -#define ADMUX _SFR_IO8(0x07) - -/* analog comparator */ -#define ACSR _SFR_IO8(0x08) - -/* UART */ -#define UBRR _SFR_IO8(0x09) -#define UBRRL UBRR -#define UCSRB _SFR_IO8(0x0A) -#define UCSRA _SFR_IO8(0x0B) -#define UDR _SFR_IO8(0x0C) - -/* SPI */ -#define SPCR _SFR_IO8(0x0D) -#define SPSR _SFR_IO8(0x0E) -#define SPDR _SFR_IO8(0x0F) - -/* Port D */ -#define PIND _SFR_IO8(0x10) -#define DDRD _SFR_IO8(0x11) -#define PORTD _SFR_IO8(0x12) - -/* Port C */ -#define PINC _SFR_IO8(0x13) -#define DDRC _SFR_IO8(0x14) -#define PORTC _SFR_IO8(0x15) - -/* Port B */ -#define PINB _SFR_IO8(0x16) -#define DDRB _SFR_IO8(0x17) -#define PORTB _SFR_IO8(0x18) - -/* Port A */ -#define PINA _SFR_IO8(0x19) -#define DDRA _SFR_IO8(0x1A) -#define PORTA _SFR_IO8(0x1B) - -/* EEPROM Control Register */ -#define EECR _SFR_IO8(0x1C) - -/* EEPROM Data Register */ -#define EEDR _SFR_IO8(0x1D) - -/* EEPROM Address Register */ -#define EEAR _SFR_IO16(0x1E) -#define EEARL _SFR_IO8(0x1E) -#define EEARH _SFR_IO8(0x1F) - -#define UBRRH _SFR_IO8(0x20) -#define UCSRC UBRRH - -#define WDTCR _SFR_IO8(0x21) - -#define ASSR _SFR_IO8(0x22) - -/* Timer 2 */ -#define OCR2 _SFR_IO8(0x23) -#define TCNT2 _SFR_IO8(0x24) -#define TCCR2 _SFR_IO8(0x25) - -/* Timer 1 */ -#define ICR1 _SFR_IO16(0x26) -#define ICR1L _SFR_IO8(0x26) -#define ICR1H _SFR_IO8(0x27) -#define OCR1B _SFR_IO16(0x28) -#define OCR1BL _SFR_IO8(0x28) -#define OCR1BH _SFR_IO8(0x29) -#define OCR1A _SFR_IO16(0x2A) -#define OCR1AL _SFR_IO8(0x2A) -#define OCR1AH _SFR_IO8(0x2B) -#define TCNT1 _SFR_IO16(0x2C) -#define TCNT1L _SFR_IO8(0x2C) -#define TCNT1H _SFR_IO8(0x2D) -#define TCCR1B _SFR_IO8(0x2E) -#define TCCR1A _SFR_IO8(0x2F) - -#define SFIOR _SFR_IO8(0x30) - -#define OSCCAL _SFR_IO8(0x31) - -/* Timer 0 */ -#define TCNT0 _SFR_IO8(0x32) -#define TCCR0 _SFR_IO8(0x33) - -#define MCUSR _SFR_IO8(0x34) -#define MCUCSR MCUSR -#define MCUCR _SFR_IO8(0x35) - -#define TWCR _SFR_IO8(0x36) - -#define SPMCR _SFR_IO8(0x37) - -#define TIFR _SFR_IO8(0x38) -#define TIMSK _SFR_IO8(0x39) - -#define GIFR _SFR_IO8(0x3A) -#define GIMSK _SFR_IO8(0x3B) -#define GICR GIMSK - -#define OCR0 _SFR_IO8(0x3C) - -/* 0x3D..0x3E SP */ - -/* 0x3F SREG */ - -/* Interrupt vectors */ - -/* External Interrupt Request 0 */ -#define INT0_vect_num 1 -#define INT0_vect _VECTOR(1) -#define SIG_INTERRUPT0 _VECTOR(1) - -/* External Interrupt Request 1 */ -#define INT1_vect_num 2 -#define INT1_vect _VECTOR(2) -#define SIG_INTERRUPT1 _VECTOR(2) - -/* External Interrupt Request 2 */ -#define INT2_vect_num 3 -#define INT2_vect _VECTOR(3) -#define SIG_INTERRUPT2 _VECTOR(3) - -/* Timer/Counter2 Compare Match */ -#define TIMER2_COMP_vect_num 4 -#define TIMER2_COMP_vect _VECTOR(4) -#define SIG_OUTPUT_COMPARE2 _VECTOR(4) - -/* Timer/Counter2 Overflow */ -#define TIMER2_OVF_vect_num 5 -#define TIMER2_OVF_vect _VECTOR(5) -#define SIG_OVERFLOW2 _VECTOR(5) - -/* Timer/Counter1 Capture Event */ -#define TIMER1_CAPT_vect_num 6 -#define TIMER1_CAPT_vect _VECTOR(6) -#define SIG_INPUT_CAPTURE1 _VECTOR(6) - -/* Timer/Counter1 Compare Match A */ -#define TIMER1_COMPA_vect_num 7 -#define TIMER1_COMPA_vect _VECTOR(7) -#define SIG_OUTPUT_COMPARE1A _VECTOR(7) - -/* Timer/Counter1 Compare Match B */ -#define TIMER1_COMPB_vect_num 8 -#define TIMER1_COMPB_vect _VECTOR(8) -#define SIG_OUTPUT_COMPARE1B _VECTOR(8) - -/* Timer/Counter1 Overflow */ -#define TIMER1_OVF_vect_num 9 -#define TIMER1_OVF_vect _VECTOR(9) -#define SIG_OVERFLOW1 _VECTOR(9) - -/* Timer/Counter0 Compare Match */ -#define TIMER0_COMP_vect_num 10 -#define TIMER0_COMP_vect _VECTOR(10) -#define SIG_OUTPUT_COMPARE0 _VECTOR(10) - -/* Timer/Counter0 Overflow */ -#define TIMER0_OVF_vect_num 11 -#define TIMER0_OVF_vect _VECTOR(11) -#define SIG_OVERFLOW0 _VECTOR(11) - -/* Serial Transfer Complete */ -#define SPI_STC_vect_num 12 -#define SPI_STC_vect _VECTOR(12) -#define SIG_SPI _VECTOR(12) - -/* USART, Rx Complete */ -#define USART_RXC_vect_num 13 -#define USART_RXC_vect _VECTOR(13) -#define SIG_UART_RECV _VECTOR(13) - -/* USART Data Register Empty */ -#define USART_UDRE_vect_num 14 -#define USART_UDRE_vect _VECTOR(14) -#define SIG_UART_DATA _VECTOR(14) - -/* USART, Tx Complete */ -#define USART_TXC_vect_num 15 -#define USART_TXC_vect _VECTOR(15) -#define SIG_UART_TRANS _VECTOR(15) - -/* ADC Conversion Complete */ -#define ADC_vect_num 16 -#define ADC_vect _VECTOR(16) -#define SIG_ADC _VECTOR(16) - -/* EEPROM Ready */ -#define EE_RDY_vect_num 17 -#define EE_RDY_vect _VECTOR(17) -#define SIG_EEPROM_READY _VECTOR(17) - -/* Analog Comparator */ -#define ANA_COMP_vect_num 18 -#define ANA_COMP_vect _VECTOR(18) -#define SIG_COMPARATOR _VECTOR(18) - -/* 2-wire Serial Interface */ -#define TWI_vect_num 19 -#define TWI_vect _VECTOR(19) -#define SIG_2WIRE_SERIAL _VECTOR(19) - -/* Store Program Memory Ready */ -#define SPM_RDY_vect_num 20 -#define SPM_RDY_vect _VECTOR(20) - -#define _VECTORS_SIZE 80 - - -/* Bit numbers */ - -/* GIMSK */ -#define INT1 7 -#define INT0 6 -#define INT2 5 -#define IVSEL 1 -#define IVCE 0 - -/* GIFR */ -#define INTF1 7 -#define INTF0 6 -#define INTF2 5 - -/* TIMSK */ -#define OCIE2 7 -#define TOIE2 6 -#define TICIE1 5 -#define OCIE1A 4 -#define OCIE1B 3 -#define TOIE1 2 -#define OCIE0 1 -#define TOIE0 0 - -/* TIFR */ -#define OCF2 7 -#define TOV2 6 -#define ICF1 5 -#define OCF1A 4 -#define OCF1B 3 -#define TOV1 2 -#define OCF0 1 -#define TOV0 0 - -/* SPMCR */ -#define SPMIE 7 -#define ASB 6 -/* bit 5 reserved */ -#define ASRE 4 -#define BLBSET 3 -#define PGWRT 2 -#define PGERS 1 -#define SPMEN 0 - -/* TWCR */ -#define TWINT 7 -#define TWEA 6 -#define TWSTA 5 -#define TWSTO 4 -#define TWWC 3 -#define TWEN 2 -#define TWI_TST 1 -#define TWIE 0 - -/* TWAR */ -#define TWGCE 0 - -/* TWSR */ -#define TWS7 7 -#define TWS6 6 -#define TWS5 5 -#define TWS4 4 -#define TWS3 3 -/* bits 2-0 reserved */ - -/* MCUCR */ -/* bit 7 reserved (SM2?) */ -#define SE 7 -#define SM2 6 -#define SM1 5 -#define SM0 4 -#define ISC11 3 -#define ISC10 2 -#define ISC01 1 -#define ISC00 0 - -/* MCUCSR */ -#define JTD 7 -#define ISC2 6 -#define EIH 5 -#define JTRF 4 -#define WDRF 3 -#define BORF 2 -#define EXTRF 1 -#define PORF 0 - -/* SFIOR */ -#define RPDD 7 -#define RPDC 6 -#define RPDB 5 -#define RPDA 4 -#define ACME 3 -#define PUD 2 -#define PSR2 1 -#define PSR10 0 - -/* TCCR0 */ -#define FOC0 7 -#define PWM0 6 -#define COM01 5 -#define COM00 4 -#define CTC0 3 -#define CS02 2 -#define CS01 1 -#define CS00 0 - -/* TCCR2 */ -#define FOC2 7 -#define PWM2 6 -#define COM21 5 -#define COM20 4 -#define CTC2 3 -#define CS22 2 -#define CS21 1 -#define CS20 0 - -/* ASSR */ -/* bits 7-4 reserved */ -#define AS2 3 -#define TCN2UB 2 -#define OCR2UB 1 -#define TCR2UB 0 - -/* TCCR1A */ -#define COM1A1 7 -#define COM1A0 6 -#define COM1B1 5 -#define COM1B0 4 -#define FOC1A 3 -#define FOC1B 2 -#define PWM11 1 -#define PWM10 0 - -/* TCCR1B */ -#define ICNC1 7 -#define ICES1 6 -/* bit 5 reserved */ -#define CTC11 4 -#define CTC10 3 -#define CS12 2 -#define CS11 1 -#define CS10 0 - -/* WDTCR */ -/* bits 7-5 reserved */ -#define WDTOE 4 -#define WDE 3 -#define WDP2 2 -#define WDP1 1 -#define WDP0 0 - -/* PA7-PA0 = ADC7-ADC0 */ -/* PORTA */ -#define PA7 7 -#define PA6 6 -#define PA5 5 -#define PA4 4 -#define PA3 3 -#define PA2 2 -#define PA1 1 -#define PA0 0 - -/* DDRA */ -#define DDA7 7 -#define DDA6 6 -#define DDA5 5 -#define DDA4 4 -#define DDA3 3 -#define DDA2 2 -#define DDA1 1 -#define DDA0 0 - -/* PINA */ -#define PINA7 7 -#define PINA6 6 -#define PINA5 5 -#define PINA4 4 -#define PINA3 3 -#define PINA2 2 -#define PINA1 1 -#define PINA0 0 - -/* - PB7 = SCK - PB6 = MISO - PB5 = MOSI - PB4 = SS# - PB3 = AIN1 - PB2 = AIN0 - PB1 = T1 - PB0 = T0 - */ - -/* PORTB */ -#define PB7 7 -#define PB6 6 -#define PB5 5 -#define PB4 4 -#define PB3 3 -#define PB2 2 -#define PB1 1 -#define PB0 0 - -/* DDRB */ -#define DDB7 7 -#define DDB6 6 -#define DDB5 5 -#define DDB4 4 -#define DDB3 3 -#define DDB2 2 -#define DDB1 1 -#define DDB0 0 - -/* PINB */ -#define PINB7 7 -#define PINB6 6 -#define PINB5 5 -#define PINB4 4 -#define PINB3 3 -#define PINB2 2 -#define PINB1 1 -#define PINB0 0 - -/* - PC7 = TOSC2 - PC6 = TOSC1 - PC1 = SDA - PC0 = SCL - */ -/* PORTC */ -#define PC7 7 -#define PC6 6 -#define PC5 5 -#define PC4 4 -#define PC3 3 -#define PC2 2 -#define PC1 1 -#define PC0 0 - -/* DDRC */ -#define DDC7 7 -#define DDC6 6 -#define DDC5 5 -#define DDC4 4 -#define DDC3 3 -#define DDC2 2 -#define DDC1 1 -#define DDC0 0 - -/* PINC */ -#define PINC7 7 -#define PINC6 6 -#define PINC5 5 -#define PINC4 4 -#define PINC3 3 -#define PINC2 2 -#define PINC1 1 -#define PINC0 0 - -/* - PD7 = OC2 - PD6 = ICP - PD5 = OC1A - PD4 = OC1B - PD3 = INT1 - PD2 = INT0 - PD1 = TXD - PD0 = RXD - */ - -/* PORTD */ -#define PD7 7 -#define PD6 6 -#define PD5 5 -#define PD4 4 -#define PD3 3 -#define PD2 2 -#define PD1 1 -#define PD0 0 - -/* DDRD */ -#define DDD7 7 -#define DDD6 6 -#define DDD5 5 -#define DDD4 4 -#define DDD3 3 -#define DDD2 2 -#define DDD1 1 -#define DDD0 0 - -/* PIND */ -#define PIND7 7 -#define PIND6 6 -#define PIND5 5 -#define PIND4 4 -#define PIND3 3 -#define PIND2 2 -#define PIND1 1 -#define PIND0 0 - -/* - PE2 = ALE - PE1 = OC1B - PE0 = ICP / INT2 - */ - -/* SPSR */ -#define SPIF 7 -#define WCOL 6 -#define SPI2X 0 - -/* SPCR */ -#define SPIE 7 -#define SPE 6 -#define DORD 5 -#define MSTR 4 -#define CPOL 3 -#define CPHA 2 -#define SPR1 1 -#define SPR0 0 - -/* UCSRA */ -#define RXC 7 -#define TXC 6 -#define UDRE 5 -#define FE 4 -#define DOR 3 -#define PE 2 -#define U2X 1 -#define MPCM 0 - -/* UCSRB */ -#define RXCIE 7 -#define TXCIE 6 -#define UDRIE 5 -#define RXEN 4 -#define TXEN 3 -#define UCSZ2 2 -#define CHR9 2 -#define RXB8 1 -#define TXB8 0 - -/* UCSRC */ -#define URSEL 7 -#define UMSEL 6 -#define UPM1 5 -#define UPM0 4 -#define USBS 3 -#define UCSZ1 2 -#define UCSZ0 1 -#define UCPOL 0 - -/* ACSR */ -#define ACD 7 -#define AINBG 6 -#define ACO 5 -#define ACI 4 -#define ACIE 3 -#define ACIC 2 -#define ACIS1 1 -#define ACIS0 0 - -/* ADCSR */ -#define ADEN 7 -#define ADSC 6 -#define ADFR 5 -#define ADIF 4 -#define ADIE 3 -#define ADPS2 2 -#define ADPS1 1 -#define ADPS0 0 - -/* ADMUX */ -#define REFS1 7 -#define REFS0 6 -#define ADLAR 5 -#define MUX4 4 -#define MUX3 3 -#define MUX2 2 -#define MUX1 1 -#define MUX0 0 - -/* EEPROM Control Register */ -#define EERIE 3 -#define EEMWE 2 -#define EEWE 1 -#define EERE 0 - -/* Constants */ -#define SPM_PAGESIZE 128 -#define RAMSTART 0x60 -#define RAMEND 0x85F -#define XRAMEND RAMEND -#define E2END 0x3FF -#define E2PAGESIZE 0 -#define FLASHEND 0x7FFF - - -/* Fuses */ - -#define FUSE_MEMORY_SIZE 2 - -/* Low Fuse Byte */ -#define FUSE_CKSEL0 (unsigned char)~_BV(0) -#define FUSE_CKSEL1 (unsigned char)~_BV(1) -#define FUSE_CKSEL2 (unsigned char)~_BV(2) -#define FUSE_CKSEL3 (unsigned char)~_BV(3) -#define FUSE_BODEN (unsigned char)~_BV(6) -#define FUSE_BODLEVEL (unsigned char)~_BV(7) -#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3) - -/* High Fuse Byte */ -#define FUSE_BOOTRST (unsigned char)~_BV(0) -#define FUSE_BOOTSZ0 (unsigned char)~_BV(1) -#define FUSE_BOOTSZ1 (unsigned char)~_BV(2) -#define FUSE_EESAVE (unsigned char)~_BV(3) -#define FUSE_SPIEN (unsigned char)~_BV(5) -#define FUSE_JTAGEN (unsigned char)~_BV(6) -#define FUSE_OCDEN (unsigned char)~_BV(7) -#define HFUSE_DEFAULT (FUSE_SPIEN & FUSE_JTAGEN) - - -/* Lock Bits */ -#define __LOCK_BITS_EXIST -#define __BOOT_LOCK_BITS_0_EXIST -#define __BOOT_LOCK_BITS_1_EXIST - - -/* Signature */ -#define SIGNATURE_0 0x1E -#define SIGNATURE_1 0x95 -#define SIGNATURE_2 0x01 - - -/* Deprecated items */ -#if !defined(__AVR_LIBC_DEPRECATED_ENABLE__) - -#pragma GCC system_header - -#pragma GCC poison SIG_INTERRUPT0 -#pragma GCC poison SIG_INTERRUPT1 -#pragma GCC poison SIG_INTERRUPT2 -#pragma GCC poison SIG_OUTPUT_COMPARE2 -#pragma GCC poison SIG_OVERFLOW2 -#pragma GCC poison SIG_INPUT_CAPTURE1 -#pragma GCC poison SIG_OUTPUT_COMPARE1A -#pragma GCC poison SIG_OUTPUT_COMPARE1B -#pragma GCC poison SIG_OVERFLOW1 -#pragma GCC poison SIG_OUTPUT_COMPARE0 -#pragma GCC poison SIG_OVERFLOW0 -#pragma GCC poison SIG_SPI -#pragma GCC poison SIG_UART_RECV -#pragma GCC poison SIG_UART_DATA -#pragma GCC poison SIG_UART_TRANS -#pragma GCC poison SIG_ADC -#pragma GCC poison SIG_EEPROM_READY -#pragma GCC poison SIG_COMPARATOR -#pragma GCC poison SIG_2WIRE_SERIAL - -#endif /* !defined(__AVR_LIBC_DEPRECATED_ENABLE__) */ - - -#define SLEEP_MODE_IDLE (0x00<<4) -#define SLEEP_MODE_ADC (0x01<<4) -#define SLEEP_MODE_PWR_DOWN (0x02<<4) -#define SLEEP_MODE_PWR_SAVE (0x03<<4) -#define SLEEP_MODE_STANDBY (0x06<<4) -#define SLEEP_MODE_EXT_STANDBY (0x07<<4) - -#endif /* _AVR_IOM323_H_ */ diff --git a/arduino/hardware/tools/avr/avr/include/avr/iom324a.h b/arduino/hardware/tools/avr/avr/include/avr/iom324a.h deleted file mode 100644 index 3ae54fb..0000000 --- a/arduino/hardware/tools/avr/avr/include/avr/iom324a.h +++ /dev/null @@ -1,1014 +0,0 @@ -/***************************************************************************** - * - * Copyright (C) 2015 Atmel Corporation - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * - * * Neither the name of the copyright holders nor the names of - * contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - ****************************************************************************/ - - -#ifndef _AVR_ATMEGA324A_H_INCLUDED -#define _AVR_ATMEGA324A_H_INCLUDED - - -#ifndef _AVR_IO_H_ -# error "Include instead of this file." -#endif - -#ifndef _AVR_IOXXX_H_ -# define _AVR_IOXXX_H_ "iom324a.h" -#else -# error "Attempt to include more than one file." -#endif - -/* Registers and associated bit numbers */ - -#define PINA _SFR_IO8(0x00) -#define PINA7 7 -#define PINA6 6 -#define PINA5 5 -#define PINA4 4 -#define PINA3 3 -#define PINA2 2 -#define PINA1 1 -#define PINA0 0 - -#define DDRA _SFR_IO8(0x01) -#define DDRA7 7 -// Inserted "DDA7" from "DDRA7" due to compatibility -#define DDA7 7 -#define DDRA6 6 -// Inserted "DDA6" from "DDRA6" due to compatibility -#define DDA6 6 -#define DDRA5 5 -// Inserted "DDA5" from "DDRA5" due to compatibility -#define DDA5 5 -#define DDRA4 4 -// Inserted "DDA4" from "DDRA4" due to compatibility -#define DDA4 4 -#define DDRA3 3 -// Inserted "DDA3" from "DDRA3" due to compatibility -#define DDA3 3 -#define DDRA2 2 -// Inserted "DDA2" from "DDRA2" due to compatibility -#define DDA2 2 -#define DDRA1 1 -// Inserted "DDA1" from "DDRA1" due to compatibility -#define DDA1 1 -#define DDRA0 0 -// Inserted "DDA0" from "DDRA0" due to compatibility -#define DDA0 0 - -#define PORTA _SFR_IO8(0x02) -#define PORTA7 7 -#define PORTA6 6 -#define PORTA5 5 -#define PORTA4 4 -#define PORTA3 3 -#define PORTA2 2 -#define PORTA1 1 -#define PORTA0 0 - -#define PINB _SFR_IO8(0x03) -#define PINB7 7 -#define PINB6 6 -#define PINB5 5 -#define PINB4 4 -#define PINB3 3 -#define PINB2 2 -#define PINB1 1 -#define PINB0 0 - -#define DDRB _SFR_IO8(0x04) -#define DDRB7 7 -// Inserted "DDB7" from "DDRB7" due to compatibility -#define DDB7 7 -#define DDRB6 6 -// Inserted "DDB6" from "DDRB6" due to compatibility -#define DDB6 6 -#define DDRB5 5 -// Inserted "DDB5" from "DDRB5" due to compatibility -#define DDB5 5 -#define DDRB4 4 -// Inserted "DDB4" from "DDRB4" due to compatibility -#define DDB4 4 -#define DDRB3 3 -// Inserted "DDB3" from "DDRB3" due to compatibility -#define DDB3 3 -#define DDRB2 2 -// Inserted "DDB2" from "DDRB2" due to compatibility -#define DDB2 2 -#define DDRB1 1 -// Inserted "DDB1" from "DDRB1" due to compatibility -#define DDB1 1 -#define DDRB0 0 -// Inserted "DDB0" from "DDRB0" due to compatibility -#define DDB0 0 - -#define PORTB _SFR_IO8(0x05) -#define PORTB7 7 -#define PORTB6 6 -#define PORTB5 5 -#define PORTB4 4 -#define PORTB3 3 -#define PORTB2 2 -#define PORTB1 1 -#define PORTB0 0 - -#define PINC _SFR_IO8(0x06) -#define PINC7 7 -#define PINC6 6 -#define PINC5 5 -#define PINC4 4 -#define PINC3 3 -#define PINC2 2 -#define PINC1 1 -#define PINC0 0 - -#define DDRC _SFR_IO8(0x07) -#define DDRC7 7 -// Inserted "DDC7" from "DDRC7" due to compatibility -#define DDC7 7 -#define DDRC6 6 -// Inserted "DDC6" from "DDRC6" due to compatibility -#define DDC6 6 -#define DDRC5 5 -// Inserted "DDC5" from "DDRC5" due to compatibility -#define DDC5 5 -#define DDRC4 4 -// Inserted "DDC4" from "DDRC4" due to compatibility -#define DDC4 4 -#define DDRC3 3 -// Inserted "DDC3" from "DDRC3" due to compatibility -#define DDC3 3 -#define DDRC2 2 -// Inserted "DDC2" from "DDRC2" due to compatibility -#define DDC2 2 -#define DDRC1 1 -// Inserted "DDC1" from "DDRC1" due to compatibility -#define DDC1 1 -#define DDRC0 0 -// Inserted "DDC0" from "DDRC0" due to compatibility -#define DDC0 0 - -#define PORTC _SFR_IO8(0x08) -#define PORTC7 7 -#define PORTC6 6 -#define PORTC5 5 -#define PORTC4 4 -#define PORTC3 3 -#define PORTC2 2 -#define PORTC1 1 -#define PORTC0 0 - -#define PIND _SFR_IO8(0x09) -#define PIND7 7 -#define PIND6 6 -#define PIND5 5 -#define PIND4 4 -#define PIND3 3 -#define PIND2 2 -#define PIND1 1 -#define PIND0 0 - -#define DDRD _SFR_IO8(0x0A) -#define DDRD7 7 -// Inserted "DDD7" from "DDRD7" due to compatibility -#define DDD7 7 -#define DDRD6 6 -// Inserted "DDD6" from "DDRD6" due to compatibility -#define DDD6 6 -#define DDRD5 5 -// Inserted "DDD5" from "DDRD5" due to compatibility -#define DDD5 5 -#define DDRD4 4 -// Inserted "DDD4" from "DDRD4" due to compatibility -#define DDD4 4 -#define DDRD3 3 -// Inserted "DDD3" from "DDRD3" due to compatibility -#define DDD3 3 -#define DDRD2 2 -// Inserted "DDD2" from "DDRD2" due to compatibility -#define DDD2 2 -#define DDRD1 1 -// Inserted "DDD1" from "DDRD1" due to compatibility -#define DDD1 1 -#define DDRD0 0 -// Inserted "DDD0" from "DDRD0" due to compatibility -#define DDD0 0 - -#define PORTD _SFR_IO8(0x0B) -#define PORTD7 7 -#define PORTD6 6 -#define PORTD5 5 -#define PORTD4 4 -#define PORTD3 3 -#define PORTD2 2 -#define PORTD1 1 -#define PORTD0 0 - -/* Reserved [0x0C..0x14] */ - -#define TIFR0 _SFR_IO8(0x15) -#define TOV0 0 -#define OCF0A 1 -#define OCF0B 2 - -#define TIFR1 _SFR_IO8(0x16) -#define TOV1 0 -#define OCF1A 1 -#define OCF1B 2 -#define ICF1 5 - -#define TIFR2 _SFR_IO8(0x17) -#define TOV2 0 -#define OCF2A 1 -#define OCF2B 2 - -/* Reserved [0x18..0x1A] */ - -#define PCIFR _SFR_IO8(0x1B) -#define PCIF0 0 -#define PCIF1 1 -#define PCIF2 2 -#define PCIF3 3 - -#define EIFR _SFR_IO8(0x1C) -#define INTF0 0 -#define INTF1 1 -#define INTF2 2 - -#define EIMSK _SFR_IO8(0x1D) -#define INT0 0 -#define INT1 1 -#define INT2 2 - -#define GPIOR0 _SFR_IO8(0x1E) -#define GPIOR00 0 -#define GPIOR01 1 -#define GPIOR02 2 -#define GPIOR03 3 -#define GPIOR04 4 -#define GPIOR05 5 -#define GPIOR06 6 -#define GPIOR07 7 - -#define EECR _SFR_IO8(0x1F) -#define EERE 0 -#define EEPE 1 -#define EEMPE 2 -#define EERIE 3 -#define EEPM0 4 -#define EEPM1 5 - -#define EEDR _SFR_IO8(0x20) - -/* Combine EEARL and EEARH */ -#define EEAR _SFR_IO16(0x21) - -#define EEARL _SFR_IO8(0x21) -#define EEARH _SFR_IO8(0x22) - -#define GTCCR _SFR_IO8(0x23) -#define PSRSYNC 0 -#define TSM 7 -#define PSRASY 1 - -#define TCCR0A _SFR_IO8(0x24) -#define WGM00 0 -#define WGM01 1 -#define COM0B0 4 -#define COM0B1 5 -#define COM0A0 6 -#define COM0A1 7 - -#define TCCR0B _SFR_IO8(0x25) -#define CS00 0 -#define CS01 1 -#define CS02 2 -#define WGM02 3 -#define FOC0B 6 -#define FOC0A 7 - -#define TCNT0 _SFR_IO8(0x26) - -#define OCR0A _SFR_IO8(0x27) - -#define OCR0B _SFR_IO8(0x28) - -/* Reserved [0x29] */ - -#define GPIOR1 _SFR_IO8(0x2A) -#define GPIOR10 0 -#define GPIOR11 1 -#define GPIOR12 2 -#define GPIOR13 3 -#define GPIOR14 4 -#define GPIOR15 5 -#define GPIOR16 6 -#define GPIOR17 7 - -#define GPIOR2 _SFR_IO8(0x2B) -#define GPIOR20 0 -#define GPIOR21 1 -#define GPIOR22 2 -#define GPIOR23 3 -#define GPIOR24 4 -#define GPIOR25 5 -#define GPIOR26 6 -#define GPIOR27 7 - -#define SPCR0 _SFR_IO8(0x2C) -#define SPR00 0 -#define SPR10 1 -#define CPHA0 2 -#define CPOL0 3 -#define MSTR0 4 -#define DORD0 5 -#define SPE0 6 -#define SPIE0 7 - -#define SPSR0 _SFR_IO8(0x2D) -#define SPI2X0 0 -#define WCOL0 6 -#define SPIF0 7 - -#define SPDR0 _SFR_IO8(0x2E) - -/* Reserved [0x2F] */ - -#define ACSR _SFR_IO8(0x30) -#define ACIS0 0 -#define ACIS1 1 -#define ACIC 2 -#define ACIE 3 -#define ACI 4 -#define ACO 5 -#define ACBG 6 -#define ACD 7 - -#define OCDR _SFR_IO8(0x31) -#define OCDR7 7 -#define OCDR6 6 -#define OCDR5 5 -#define OCDR4 4 -#define OCDR3 3 -#define OCDR2 2 -#define OCDR1 1 -#define OCDR0 0 - -/* Reserved [0x32] */ - -#define SMCR _SFR_IO8(0x33) -#define SE 0 -#define SM0 1 -#define SM1 2 -#define SM2 3 - -#define MCUSR _SFR_IO8(0x34) -#define JTRF 4 -#define PORF 0 -#define EXTRF 1 -#define BORF 2 -#define WDRF 3 - -#define MCUCR _SFR_IO8(0x35) -#define JTD 7 -#define IVCE 0 -#define IVSEL 1 -#define PUD 4 - -/* Reserved [0x36] */ - -#define SPMCSR _SFR_IO8(0x37) -#define SPMEN 0 -#define PGERS 1 -#define PGWRT 2 -#define BLBSET 3 -#define RWWSRE 4 -#define SIGRD 5 -#define RWWSB 6 -#define SPMIE 7 - -/* Reserved [0x38..0x3C] */ - -/* SP [0x3D..0x3E] */ - -/* SREG [0x3F] */ - -#define WDTCSR _SFR_MEM8(0x60) -#define WDE 3 -#define WDCE 4 -#define WDP0 0 -#define WDP1 1 -#define WDP2 2 -#define WDP3 5 -#define WDIE 6 -#define WDIF 7 - -#define CLKPR _SFR_MEM8(0x61) -#define CLKPS0 0 -#define CLKPS1 1 -#define CLKPS2 2 -#define CLKPS3 3 -#define CLKPCE 7 - -/* Reserved [0x62..0x63] */ - -#define PRR0 _SFR_MEM8(0x64) -#define PRADC 0 -#define PRUSART0 1 -#define PRSPI 2 -#define PRTIM1 3 -#define PRUSART1 4 -#define PRTIM0 5 -#define PRTIM2 6 -#define PRTWI 7 - -#define __AVR_HAVE_PRR0 ((1< instead of this file." -#endif - -#ifndef _AVR_IOXXX_H_ -# define _AVR_IOXXX_H_ "iom324p.h" -#else -# error "Attempt to include more than one file." -#endif - -/* Registers and associated bit numbers */ - -#define PINA _SFR_IO8(0x00) -#define PINA7 7 -#define PINA6 6 -#define PINA5 5 -#define PINA4 4 -#define PINA3 3 -#define PINA2 2 -#define PINA1 1 -#define PINA0 0 - -#define DDRA _SFR_IO8(0x01) -#define DDRA7 7 -// Inserted "DDA7" from "DDRA7" due to compatibility -#define DDA7 7 -#define DDRA6 6 -// Inserted "DDA6" from "DDRA6" due to compatibility -#define DDA6 6 -#define DDRA5 5 -// Inserted "DDA5" from "DDRA5" due to compatibility -#define DDA5 5 -#define DDRA4 4 -// Inserted "DDA4" from "DDRA4" due to compatibility -#define DDA4 4 -#define DDRA3 3 -// Inserted "DDA3" from "DDRA3" due to compatibility -#define DDA3 3 -#define DDRA2 2 -// Inserted "DDA2" from "DDRA2" due to compatibility -#define DDA2 2 -#define DDRA1 1 -// Inserted "DDA1" from "DDRA1" due to compatibility -#define DDA1 1 -#define DDRA0 0 -// Inserted "DDA0" from "DDRA0" due to compatibility -#define DDA0 0 - -#define PORTA _SFR_IO8(0x02) -#define PORTA7 7 -#define PORTA6 6 -#define PORTA5 5 -#define PORTA4 4 -#define PORTA3 3 -#define PORTA2 2 -#define PORTA1 1 -#define PORTA0 0 - -#define PINB _SFR_IO8(0x03) -#define PINB7 7 -#define PINB6 6 -#define PINB5 5 -#define PINB4 4 -#define PINB3 3 -#define PINB2 2 -#define PINB1 1 -#define PINB0 0 - -#define DDRB _SFR_IO8(0x04) -#define DDRB7 7 -// Inserted "DDB7" from "DDRB7" due to compatibility -#define DDB7 7 -#define DDRB6 6 -// Inserted "DDB6" from "DDRB6" due to compatibility -#define DDB6 6 -#define DDRB5 5 -// Inserted "DDB5" from "DDRB5" due to compatibility -#define DDB5 5 -#define DDRB4 4 -// Inserted "DDB4" from "DDRB4" due to compatibility -#define DDB4 4 -#define DDRB3 3 -// Inserted "DDB3" from "DDRB3" due to compatibility -#define DDB3 3 -#define DDRB2 2 -// Inserted "DDB2" from "DDRB2" due to compatibility -#define DDB2 2 -#define DDRB1 1 -// Inserted "DDB1" from "DDRB1" due to compatibility -#define DDB1 1 -#define DDRB0 0 -// Inserted "DDB0" from "DDRB0" due to compatibility -#define DDB0 0 - -#define PORTB _SFR_IO8(0x05) -#define PORTB7 7 -#define PORTB6 6 -#define PORTB5 5 -#define PORTB4 4 -#define PORTB3 3 -#define PORTB2 2 -#define PORTB1 1 -#define PORTB0 0 - -#define PINC _SFR_IO8(0x06) -#define PINC7 7 -#define PINC6 6 -#define PINC5 5 -#define PINC4 4 -#define PINC3 3 -#define PINC2 2 -#define PINC1 1 -#define PINC0 0 - -#define DDRC _SFR_IO8(0x07) -#define DDRC7 7 -// Inserted "DDC7" from "DDRC7" due to compatibility -#define DDC7 7 -#define DDRC6 6 -// Inserted "DDC6" from "DDRC6" due to compatibility -#define DDC6 6 -#define DDRC5 5 -// Inserted "DDC5" from "DDRC5" due to compatibility -#define DDC5 5 -#define DDRC4 4 -// Inserted "DDC4" from "DDRC4" due to compatibility -#define DDC4 4 -#define DDRC3 3 -// Inserted "DDC3" from "DDRC3" due to compatibility -#define DDC3 3 -#define DDRC2 2 -// Inserted "DDC2" from "DDRC2" due to compatibility -#define DDC2 2 -#define DDRC1 1 -// Inserted "DDC1" from "DDRC1" due to compatibility -#define DDC1 1 -#define DDRC0 0 -// Inserted "DDC0" from "DDRC0" due to compatibility -#define DDC0 0 - -#define PORTC _SFR_IO8(0x08) -#define PORTC7 7 -#define PORTC6 6 -#define PORTC5 5 -#define PORTC4 4 -#define PORTC3 3 -#define PORTC2 2 -#define PORTC1 1 -#define PORTC0 0 - -#define PIND _SFR_IO8(0x09) -#define PIND7 7 -#define PIND6 6 -#define PIND5 5 -#define PIND4 4 -#define PIND3 3 -#define PIND2 2 -#define PIND1 1 -#define PIND0 0 - -#define DDRD _SFR_IO8(0x0A) -#define DDRD7 7 -// Inserted "DDD7" from "DDRD7" due to compatibility -#define DDD7 7 -#define DDRD6 6 -// Inserted "DDD6" from "DDRD6" due to compatibility -#define DDD6 6 -#define DDRD5 5 -// Inserted "DDD5" from "DDRD5" due to compatibility -#define DDD5 5 -#define DDRD4 4 -// Inserted "DDD4" from "DDRD4" due to compatibility -#define DDD4 4 -#define DDRD3 3 -// Inserted "DDD3" from "DDRD3" due to compatibility -#define DDD3 3 -#define DDRD2 2 -// Inserted "DDD2" from "DDRD2" due to compatibility -#define DDD2 2 -#define DDRD1 1 -// Inserted "DDD1" from "DDRD1" due to compatibility -#define DDD1 1 -#define DDRD0 0 -// Inserted "DDD0" from "DDRD0" due to compatibility -#define DDD0 0 - -#define PORTD _SFR_IO8(0x0B) -#define PORTD7 7 -#define PORTD6 6 -#define PORTD5 5 -#define PORTD4 4 -#define PORTD3 3 -#define PORTD2 2 -#define PORTD1 1 -#define PORTD0 0 - -/* Reserved [0x0C..0x14] */ - -#define TIFR0 _SFR_IO8(0x15) -#define TOV0 0 -#define OCF0A 1 -#define OCF0B 2 - -#define TIFR1 _SFR_IO8(0x16) -#define TOV1 0 -#define OCF1A 1 -#define OCF1B 2 -#define ICF1 5 - -#define TIFR2 _SFR_IO8(0x17) -#define TOV2 0 -#define OCF2A 1 -#define OCF2B 2 - -/* Reserved [0x18..0x1A] */ - -#define PCIFR _SFR_IO8(0x1B) -#define PCIF0 0 -#define PCIF1 1 -#define PCIF2 2 -#define PCIF3 3 - -#define EIFR _SFR_IO8(0x1C) -#define INTF0 0 -#define INTF1 1 -#define INTF2 2 - -#define EIMSK _SFR_IO8(0x1D) -#define INT0 0 -#define INT1 1 -#define INT2 2 - -#define GPIOR0 _SFR_IO8(0x1E) -#define GPIOR00 0 -#define GPIOR01 1 -#define GPIOR02 2 -#define GPIOR03 3 -#define GPIOR04 4 -#define GPIOR05 5 -#define GPIOR06 6 -#define GPIOR07 7 - -#define EECR _SFR_IO8(0x1F) -#define EERE 0 -#define EEPE 1 -#define EEMPE 2 -#define EERIE 3 -#define EEPM0 4 -#define EEPM1 5 - -#define EEDR _SFR_IO8(0x20) - -/* Combine EEARL and EEARH */ -#define EEAR _SFR_IO16(0x21) - -#define EEARL _SFR_IO8(0x21) -#define EEARH _SFR_IO8(0x22) - -#define GTCCR _SFR_IO8(0x23) -#define PSRSYNC 0 -#define TSM 7 -#define PSRASY 1 - -#define TCCR0A _SFR_IO8(0x24) -#define WGM00 0 -#define WGM01 1 -#define COM0B0 4 -#define COM0B1 5 -#define COM0A0 6 -#define COM0A1 7 - -#define TCCR0B _SFR_IO8(0x25) -#define CS00 0 -#define CS01 1 -#define CS02 2 -#define WGM02 3 -#define FOC0B 6 -#define FOC0A 7 - -#define TCNT0 _SFR_IO8(0x26) - -#define OCR0A _SFR_IO8(0x27) - -#define OCR0B _SFR_IO8(0x28) - -/* Reserved [0x29] */ - -#define GPIOR1 _SFR_IO8(0x2A) -#define GPIOR10 0 -#define GPIOR11 1 -#define GPIOR12 2 -#define GPIOR13 3 -#define GPIOR14 4 -#define GPIOR15 5 -#define GPIOR16 6 -#define GPIOR17 7 - -#define GPIOR2 _SFR_IO8(0x2B) -#define GPIOR20 0 -#define GPIOR21 1 -#define GPIOR22 2 -#define GPIOR23 3 -#define GPIOR24 4 -#define GPIOR25 5 -#define GPIOR26 6 -#define GPIOR27 7 - -#define SPCR0 _SFR_IO8(0x2C) -#define SPR00 0 -#define SPR10 1 -#define CPHA0 2 -#define CPOL0 3 -#define MSTR0 4 -#define DORD0 5 -#define SPE0 6 -#define SPIE0 7 - -#define SPSR0 _SFR_IO8(0x2D) -#define SPI2X0 0 -#define WCOL0 6 -#define SPIF0 7 - -#define SPDR0 _SFR_IO8(0x2E) - -/* Reserved [0x2F] */ - -#define ACSR _SFR_IO8(0x30) -#define ACIS0 0 -#define ACIS1 1 -#define ACIC 2 -#define ACIE 3 -#define ACI 4 -#define ACO 5 -#define ACBG 6 -#define ACD 7 - -#define OCDR _SFR_IO8(0x31) -#define OCDR7 7 -#define OCDR6 6 -#define OCDR5 5 -#define OCDR4 4 -#define OCDR3 3 -#define OCDR2 2 -#define OCDR1 1 -#define OCDR0 0 - -/* Reserved [0x32] */ - -#define SMCR _SFR_IO8(0x33) -#define SE 0 -#define SM0 1 -#define SM1 2 -#define SM2 3 - -#define MCUSR _SFR_IO8(0x34) -#define JTRF 4 -#define PORF 0 -#define EXTRF 1 -#define BORF 2 -#define WDRF 3 - -#define MCUCR _SFR_IO8(0x35) -#define JTD 7 -#define IVCE 0 -#define IVSEL 1 -#define PUD 4 -#define BODSE 5 -#define BODS 6 - -/* Reserved [0x36] */ - -#define SPMCSR _SFR_IO8(0x37) -#define SPMEN 0 -#define PGERS 1 -#define PGWRT 2 -#define BLBSET 3 -#define RWWSRE 4 -#define SIGRD 5 -#define RWWSB 6 -#define SPMIE 7 - -/* Reserved [0x38..0x3C] */ - -/* SP [0x3D..0x3E] */ - -/* SREG [0x3F] */ - -#define WDTCSR _SFR_MEM8(0x60) -#define WDE 3 -#define WDCE 4 -#define WDP0 0 -#define WDP1 1 -#define WDP2 2 -#define WDP3 5 -#define WDIE 6 -#define WDIF 7 - -#define CLKPR _SFR_MEM8(0x61) -#define CLKPS0 0 -#define CLKPS1 1 -#define CLKPS2 2 -#define CLKPS3 3 -#define CLKPCE 7 - -/* Reserved [0x62..0x63] */ - -#define PRR0 _SFR_MEM8(0x64) -#define PRADC 0 -#define PRUSART0 1 -#define PRSPI 2 -#define PRTIM1 3 -#define PRUSART1 4 -#define PRTIM0 5 -#define PRTIM2 6 -#define PRTWI 7 - -#define __AVR_HAVE_PRR0 ((1<, never directly. */ - -#ifndef _AVR_IO_H_ -# error "Include instead of this file." -#endif - -#ifndef _AVR_IOXXX_H_ -# define _AVR_IOXXX_H_ "iom324pa.h" -#else -# error "Attempt to include more than one file." -#endif - - -#ifndef _AVR_ATmega324PA_H_ -#define _AVR_ATmega324PA_H_ 1 - - -/* Registers and associated bit numbers. */ - -#define PINA _SFR_IO8(0x00) -#define PINA0 0 -#define PINA1 1 -#define PINA2 2 -#define PINA3 3 -#define PINA4 4 -#define PINA5 5 -#define PINA6 6 -#define PINA7 7 - -#define DDRA _SFR_IO8(0x01) -#define DDA0 0 -#define DDA1 1 -#define DDA2 2 -#define DDA3 3 -#define DDA4 4 -#define DDA5 5 -#define DDA6 6 -#define DDA7 7 - -#define PORTA _SFR_IO8(0x02) -#define PORTA0 0 -#define PORTA1 1 -#define PORTA2 2 -#define PORTA3 3 -#define PORTA4 4 -#define PORTA5 5 -#define PORTA6 6 -#define PORTA7 7 - -#define PINB _SFR_IO8(0x03) -#define PINB0 0 -#define PINB1 1 -#define PINB2 2 -#define PINB3 3 -#define PINB4 4 -#define PINB5 5 -#define PINB6 6 -#define PINB7 7 - -#define DDRB _SFR_IO8(0x04) -#define DDB0 0 -#define DDB1 1 -#define DDB2 2 -#define DDB3 3 -#define DDB4 4 -#define DDB5 5 -#define DDB6 6 -#define DDB7 7 - -#define PORTB _SFR_IO8(0x05) -#define PORTB0 0 -#define PORTB1 1 -#define PORTB2 2 -#define PORTB3 3 -#define PORTB4 4 -#define PORTB5 5 -#define PORTB6 6 -#define PORTB7 7 - -#define PINC _SFR_IO8(0x06) -#define PINC0 0 -#define PINC1 1 -#define PINC2 2 -#define PINC3 3 -#define PINC4 4 -#define PINC5 5 -#define PINC6 6 -#define PINC7 7 - -#define DDRC _SFR_IO8(0x07) -#define DDC0 0 -#define DDC1 1 -#define DDC2 2 -#define DDC3 3 -#define DDC4 4 -#define DDC5 5 -#define DDC6 6 -#define DDC7 7 - -#define PORTC _SFR_IO8(0x08) -#define PORTC0 0 -#define PORTC1 1 -#define PORTC2 2 -#define PORTC3 3 -#define PORTC4 4 -#define PORTC5 5 -#define PORTC6 6 -#define PORTC7 7 - -#define PIND _SFR_IO8(0x09) -#define PIND0 0 -#define PIND1 1 -#define PIND2 2 -#define PIND3 3 -#define PIND4 4 -#define PIND5 5 -#define PIND6 6 -#define PIND7 7 - -#define DDRD _SFR_IO8(0x0A) -#define DDD0 0 -#define DDD1 1 -#define DDD2 2 -#define DDD3 3 -#define DDD4 4 -#define DDD5 5 -#define DDD6 6 -#define DDD7 7 - -#define PORTD _SFR_IO8(0x0B) -#define PORTD0 0 -#define PORTD1 1 -#define PORTD2 2 -#define PORTD3 3 -#define PORTD4 4 -#define PORTD5 5 -#define PORTD6 6 -#define PORTD7 7 - -#define TIFR0 _SFR_IO8(0x15) -#define TOV0 0 -#define OCF0A 1 -#define OCF0B 2 - -#define TIFR1 _SFR_IO8(0x16) -#define TOV1 0 -#define OCF1A 1 -#define OCF1B 2 -#define ICF1 5 - -#define TIFR2 _SFR_IO8(0x17) -#define TOV2 0 -#define OCF2A 1 -#define OCF2B 2 - -#define PCIFR _SFR_IO8(0x1B) -#define PCIF0 0 -#define PCIF1 1 -#define PCIF2 2 -#define PCIF3 3 - -#define EIFR _SFR_IO8(0x1C) -#define INTF0 0 -#define INTF1 1 -#define INTF2 2 - -#define EIMSK _SFR_IO8(0x1D) -#define INT0 0 -#define INT1 1 -#define INT2 2 - -#define GPIOR0 _SFR_IO8(0x1E) -#define GPIOR00 0 -#define GPIOR01 1 -#define GPIOR02 2 -#define GPIOR03 3 -#define GPIOR04 4 -#define GPIOR05 5 -#define GPIOR06 6 -#define GPIOR07 7 - -#define EECR _SFR_IO8(0x1F) -#define EERE 0 -#define EEPE 1 -#define EEMPE 2 -#define EERIE 3 -#define EEPM0 4 -#define EEPM1 5 - -#define EEDR _SFR_IO8(0x20) -#define EEDR0 0 -#define EEDR1 1 -#define EEDR2 2 -#define EEDR3 3 -#define EEDR4 4 -#define EEDR5 5 -#define EEDR6 6 -#define EEDR7 7 - -#define EEAR _SFR_IO16(0x21) - -#define EEARL _SFR_IO8(0x21) -#define EEAR0 0 -#define EEAR1 1 -#define EEAR2 2 -#define EEAR3 3 -#define EEAR4 4 -#define EEAR5 5 -#define EEAR6 6 -#define EEAR7 7 - -#define EEARH _SFR_IO8(0x22) -#define EEAR8 0 -#define EEAR9 1 -#define EEAR10 2 -#define EEAR11 3 - -#define GTCCR _SFR_IO8(0x23) -#define PSRSYNC 0 -#define PSRASY 1 -#define TSM 7 - -#define TCCR0A _SFR_IO8(0x24) -#define WGM00 0 -#define WGM01 1 -#define COM0B0 4 -#define COM0B1 5 -#define COM0A0 6 -#define COM0A1 7 - -#define TCCR0B _SFR_IO8(0x25) -#define CS00 0 -#define CS01 1 -#define CS02 2 -#define WGM02 3 -#define FOC0B 6 -#define FOC0A 7 - -#define TCNT0 _SFR_IO8(0x26) -#define TCNT0_0 0 -#define TCNT0_1 1 -#define TCNT0_2 2 -#define TCNT0_3 3 -#define TCNT0_4 4 -#define TCNT0_5 5 -#define TCNT0_6 6 -#define TCNT0_7 7 - -#define OCR0A _SFR_IO8(0x27) -#define OCR0A_0 0 -#define OCR0A_1 1 -#define OCR0A_2 2 -#define OCR0A_3 3 -#define OCR0A_4 4 -#define OCR0A_5 5 -#define OCR0A_6 6 -#define OCR0A_7 7 - -#define OCR0B _SFR_IO8(0x28) -#define OCR0B_0 0 -#define OCR0B_1 1 -#define OCR0B_2 2 -#define OCR0B_3 3 -#define OCR0B_4 4 -#define OCR0B_5 5 -#define OCR0B_6 6 -#define OCR0B_7 7 - -#define GPIOR1 _SFR_IO8(0x2A) -#define GPIOR10 0 -#define GPIOR11 1 -#define GPIOR12 2 -#define GPIOR13 3 -#define GPIOR14 4 -#define GPIOR15 5 -#define GPIOR16 6 -#define GPIOR17 7 - -#define GPIOR2 _SFR_IO8(0x2B) -#define GPIOR20 0 -#define GPIOR21 1 -#define GPIOR22 2 -#define GPIOR23 3 -#define GPIOR24 4 -#define GPIOR25 5 -#define GPIOR26 6 -#define GPIOR27 7 - -#define SPCR0 _SFR_IO8(0x2C) -#define SPR00 0 -#define SPR10 1 -#define CPHA0 2 -#define CPOL0 3 -#define MSTR0 4 -#define DORD0 5 -#define SPE0 6 -#define SPIE0 7 - -#define SPSR0 _SFR_IO8(0x2D) -#define SPI2X0 0 -#define WCOL0 6 -#define SPIF0 7 - -#define SPDR0 _SFR_IO8(0x2E) -#define SPDRB0 0 -#define SPDRB1 1 -#define SPDRB2 2 -#define SPDRB3 3 -#define SPDRB4 4 -#define SPDRB5 5 -#define SPDRB6 6 -#define SPDRB7 7 - -#define ACSR _SFR_IO8(0x30) -#define ACIS0 0 -#define ACIS1 1 -#define ACIC 2 -#define ACIE 3 -#define ACI 4 -#define ACO 5 -#define ACBG 6 -#define ACD 7 - -#define OCDR _SFR_IO8(0x31) -#define OCDR0 0 -#define OCDR1 1 -#define OCDR2 2 -#define OCDR3 3 -#define OCDR4 4 -#define OCDR5 5 -#define OCDR6 6 -#define OCDR7 7 - -#define SMCR _SFR_IO8(0x33) -#define SE 0 -#define SM0 1 -#define SM1 2 -#define SM2 3 - -#define MCUSR _SFR_IO8(0x34) -#define PORF 0 -#define EXTRF 1 -#define BORF 2 -#define WDRF 3 -#define JTRF 4 - -#define MCUCR _SFR_IO8(0x35) -#define IVCE 0 -#define IVSEL 1 -#define PUD 4 -#define BODSE 5 -#define BODS 6 -#define JTD 7 - -#define SPMCSR _SFR_IO8(0x37) -#define SPMEN 0 -#define PGERS 1 -#define PGWRT 2 -#define BLBSET 3 -#define RWWSRE 4 -#define SIGRD 5 -#define RWWSB 6 -#define SPMIE 7 - -#define WDTCSR _SFR_MEM8(0x60) -#define WDP0 0 -#define WDP1 1 -#define WDP2 2 -#define WDE 3 -#define WDCE 4 -#define WDP3 5 -#define WDIE 6 -#define WDIF 7 - -#define CLKPR _SFR_MEM8(0x61) -#define CLKPS0 0 -#define CLKPS1 1 -#define CLKPS2 2 -#define CLKPS3 3 -#define CLKPCE 7 - -#define PRR0 _SFR_MEM8(0x64) -#define PRADC 0 -#define PRUSART0 1 -#define PRSPI 2 -#define PRTIM1 3 -#define PRUSART1 4 -#define PRTIM0 5 -#define PRTIM2 6 -#define PRTWI 7 - -#define __AVR_HAVE_PRR0 ((1< instead of this file." -#endif - -#ifndef _AVR_IOXXX_H_ -# define _AVR_IOXXX_H_ "iom324pb.h" -#else -# error "Attempt to include more than one file." -#endif - -/* Registers and associated bit numbers */ - -#define PINA _SFR_IO8(0x00) -#define PINA7 7 -#define PINA6 6 -#define PINA5 5 -#define PINA4 4 -#define PINA3 3 -#define PINA2 2 -#define PINA1 1 -#define PINA0 0 - -#define DDRA _SFR_IO8(0x01) -#define DDRA7 7 -// Inserted "DDA7" from "DDRA7" due to compatibility -#define DDA7 7 -#define DDRA6 6 -// Inserted "DDA6" from "DDRA6" due to compatibility -#define DDA6 6 -#define DDRA5 5 -// Inserted "DDA5" from "DDRA5" due to compatibility -#define DDA5 5 -#define DDRA4 4 -// Inserted "DDA4" from "DDRA4" due to compatibility -#define DDA4 4 -#define DDRA3 3 -// Inserted "DDA3" from "DDRA3" due to compatibility -#define DDA3 3 -#define DDRA2 2 -// Inserted "DDA2" from "DDRA2" due to compatibility -#define DDA2 2 -#define DDRA1 1 -// Inserted "DDA1" from "DDRA1" due to compatibility -#define DDA1 1 -#define DDRA0 0 -// Inserted "DDA0" from "DDRA0" due to compatibility -#define DDA0 0 - -#define PORTA _SFR_IO8(0x02) -#define PORTA7 7 -#define PORTA6 6 -#define PORTA5 5 -#define PORTA4 4 -#define PORTA3 3 -#define PORTA2 2 -#define PORTA1 1 -#define PORTA0 0 - -#define PINB _SFR_IO8(0x03) -#define PINB7 7 -#define PINB6 6 -#define PINB5 5 -#define PINB4 4 -#define PINB3 3 -#define PINB2 2 -#define PINB1 1 -#define PINB0 0 - -#define DDRB _SFR_IO8(0x04) -#define DDRB7 7 -// Inserted "DDB7" from "DDRB7" due to compatibility -#define DDB7 7 -#define DDRB6 6 -// Inserted "DDB6" from "DDRB6" due to compatibility -#define DDB6 6 -#define DDRB5 5 -// Inserted "DDB5" from "DDRB5" due to compatibility -#define DDB5 5 -#define DDRB4 4 -// Inserted "DDB4" from "DDRB4" due to compatibility -#define DDB4 4 -#define DDRB3 3 -// Inserted "DDB3" from "DDRB3" due to compatibility -#define DDB3 3 -#define DDRB2 2 -// Inserted "DDB2" from "DDRB2" due to compatibility -#define DDB2 2 -#define DDRB1 1 -// Inserted "DDB1" from "DDRB1" due to compatibility -#define DDB1 1 -#define DDRB0 0 -// Inserted "DDB0" from "DDRB0" due to compatibility -#define DDB0 0 - -#define PORTB _SFR_IO8(0x05) -#define PORTB7 7 -#define PORTB6 6 -#define PORTB5 5 -#define PORTB4 4 -#define PORTB3 3 -#define PORTB2 2 -#define PORTB1 1 -#define PORTB0 0 - -#define PINC _SFR_IO8(0x06) -#define PINC7 7 -#define PINC6 6 -#define PINC5 5 -#define PINC4 4 -#define PINC3 3 -#define PINC2 2 -#define PINC1 1 -#define PINC0 0 - -#define DDRC _SFR_IO8(0x07) -#define DDRC7 7 -// Inserted "DDC7" from "DDRC7" due to compatibility -#define DDC7 7 -#define DDRC6 6 -// Inserted "DDC6" from "DDRC6" due to compatibility -#define DDC6 6 -#define DDRC5 5 -// Inserted "DDC5" from "DDRC5" due to compatibility -#define DDC5 5 -#define DDRC4 4 -// Inserted "DDC4" from "DDRC4" due to compatibility -#define DDC4 4 -#define DDRC3 3 -// Inserted "DDC3" from "DDRC3" due to compatibility -#define DDC3 3 -#define DDRC2 2 -// Inserted "DDC2" from "DDRC2" due to compatibility -#define DDC2 2 -#define DDRC1 1 -// Inserted "DDC1" from "DDRC1" due to compatibility -#define DDC1 1 -#define DDRC0 0 -// Inserted "DDC0" from "DDRC0" due to compatibility -#define DDC0 0 - -#define PORTC _SFR_IO8(0x08) -#define PORTC7 7 -#define PORTC6 6 -#define PORTC5 5 -#define PORTC4 4 -#define PORTC3 3 -#define PORTC2 2 -#define PORTC1 1 -#define PORTC0 0 - -#define PIND _SFR_IO8(0x09) -#define PIND7 7 -#define PIND6 6 -#define PIND5 5 -#define PIND4 4 -#define PIND3 3 -#define PIND2 2 -#define PIND1 1 -#define PIND0 0 - -#define DDRD _SFR_IO8(0x0A) -#define DDRD7 7 -// Inserted "DDD7" from "DDRD7" due to compatibility -#define DDD7 7 -#define DDRD6 6 -// Inserted "DDD6" from "DDRD6" due to compatibility -#define DDD6 6 -#define DDRD5 5 -// Inserted "DDD5" from "DDRD5" due to compatibility -#define DDD5 5 -#define DDRD4 4 -// Inserted "DDD4" from "DDRD4" due to compatibility -#define DDD4 4 -#define DDRD3 3 -// Inserted "DDD3" from "DDRD3" due to compatibility -#define DDD3 3 -#define DDRD2 2 -// Inserted "DDD2" from "DDRD2" due to compatibility -#define DDD2 2 -#define DDRD1 1 -// Inserted "DDD1" from "DDRD1" due to compatibility -#define DDD1 1 -#define DDRD0 0 -// Inserted "DDD0" from "DDRD0" due to compatibility -#define DDD0 0 - -#define PORTD _SFR_IO8(0x0B) -#define PORTD7 7 -#define PORTD6 6 -#define PORTD5 5 -#define PORTD4 4 -#define PORTD3 3 -#define PORTD2 2 -#define PORTD1 1 -#define PORTD0 0 - -#define PINE _SFR_IO8(0x0C) -#define PINE6 6 -#define PINE5 5 -#define PINE4 4 -#define PINE3 3 -#define PINE2 2 -#define PINE1 1 -#define PINE0 0 - -#define DDRE _SFR_IO8(0x0D) -#define DDRE6 6 -// Inserted "DDE6" from "DDRE6" due to compatibility -#define DDE6 6 -#define DDRE5 5 -// Inserted "DDE5" from "DDRE5" due to compatibility -#define DDE5 5 -#define DDRE4 4 -// Inserted "DDE4" from "DDRE4" due to compatibility -#define DDE4 4 -#define DDRE3 3 -// Inserted "DDE3" from "DDRE3" due to compatibility -#define DDE3 3 -#define DDRE2 2 -// Inserted "DDE2" from "DDRE2" due to compatibility -#define DDE2 2 -#define DDRE1 1 -// Inserted "DDE1" from "DDRE1" due to compatibility -#define DDE1 1 -#define DDRE0 0 -// Inserted "DDE0" from "DDRE0" due to compatibility -#define DDE0 0 - -#define PORTE _SFR_IO8(0x0E) -#define PORTE6 6 -#define PORTE5 5 -#define PORTE4 4 -#define PORTE3 3 -#define PORTE2 2 -#define PORTE1 1 -#define PORTE0 0 - -/* Reserved [0x0F..0x14] */ - -#define TIFR0 _SFR_IO8(0x15) -#define TOV0 0 -#define OCF0A 1 -#define OCF0B 2 - -#define TIFR1 _SFR_IO8(0x16) -#define TOV1 0 -#define OCF1A 1 -#define OCF1B 2 -#define ICF1 5 - -#define TIFR2 _SFR_IO8(0x17) -#define TOV2 0 -#define OCF2A 1 -#define OCF2B 2 - -#define TIFR3 _SFR_IO8(0x18) -#define TOV3 0 -#define OCF3A 1 -#define OCF3B 2 -#define ICF3 5 - -#define TIFR4 _SFR_IO8(0x19) -#define TOV4 0 -#define OCF4A 1 -#define OCF4B 2 -#define ICF4 5 - -/* Reserved [0x1A] */ - -#define PCIFR _SFR_IO8(0x1B) -#define PCIF0 0 -#define PCIF1 1 -#define PCIF2 2 -#define PCIF3 3 -#define PCIF4 4 - -#define EIFR _SFR_IO8(0x1C) -#define INTF0 0 -#define INTF1 1 -#define INTF2 2 - -#define EIMSK _SFR_IO8(0x1D) -#define INT0 0 -#define INT1 1 -#define INT2 2 - -#define GPIOR0 _SFR_IO8(0x1E) - -#define EECR _SFR_IO8(0x1F) -#define EERE 0 -#define EEPE 1 -#define EEMPE 2 -#define EERIE 3 -#define EEPM0 4 -#define EEPM1 5 - -#define EEDR _SFR_IO8(0x20) - -/* Combine EEARL and EEARH */ -#define EEAR _SFR_IO16(0x21) - -#define EEARL _SFR_IO8(0x21) -#define EEARH _SFR_IO8(0x22) - -#define GTCCR _SFR_IO8(0x23) -#define PSRSYNC 0 -#define PSRASY 1 -#define TSM 7 - -#define TCCR0A _SFR_IO8(0x24) -#define WGM00 0 -#define WGM01 1 -#define COM0B0 4 -#define COM0B1 5 -#define COM0A0 6 -#define COM0A1 7 - -#define TCCR0B _SFR_IO8(0x25) -#define CS00 0 -#define CS01 1 -#define CS02 2 -#define WGM02 3 -#define FOC0B 6 -#define FOC0A 7 - -#define TCNT0 _SFR_IO8(0x26) - -#define OCR0A _SFR_IO8(0x27) - -#define OCR0B _SFR_IO8(0x28) - -/* Reserved [0x29] */ - -#define GPIOR1 _SFR_IO8(0x2A) - -#define GPIOR2 _SFR_IO8(0x2B) - -#define SPCR0 _SFR_IO8(0x2C) -#define SPR0 0 -#define SPR1 1 -#define CPHA 2 -#define CPOL 3 -#define MSTR 4 -#define DORD 5 -#define SPE 6 -#define SPIE 7 - -#define SPSR0 _SFR_IO8(0x2D) -#define SPI2X 0 -#define WCOL 6 -#define SPIF 7 - -#define SPDR0 _SFR_IO8(0x2E) - -#define ACSRB _SFR_IO8(0x2F) -#define ACOE 0 - -#define ACSR _SFR_IO8(0x30) -#define ACIS0 0 -#define ACIS1 1 -#define ACIC 2 -#define ACIE 3 -#define ACI 4 -#define ACO 5 -#define ACBG 6 -#define ACD 7 - -#define OCDR _SFR_IO8(0x31) -#define OCDR7 7 -#define OCDR6 6 -#define OCDR5 5 -#define OCDR4 4 -#define OCDR3 3 -#define OCDR2 2 -#define OCDR1 1 -#define OCDR0 0 - -/* Reserved [0x32] */ - -#define SMCR _SFR_IO8(0x33) -#define SE 0 -#define SM0 1 -#define SM1 2 -#define SM2 3 - -#define MCUSR _SFR_IO8(0x34) -#define JTRF 4 -#define PORF 0 -#define EXTRF 1 -#define BORF 2 -#define WDRF 3 - -#define MCUCR _SFR_IO8(0x35) -#define JTD 7 -#define IVCE 0 -#define IVSEL 1 -#define PUD 4 -#define BODSE 5 -#define BODS 6 - -/* Reserved [0x36] */ - -#define SPMCSR _SFR_IO8(0x37) -#define SPMEN 0 -#define PGERS 1 -#define PGWRT 2 -#define BLBSET 3 -#define RWWSRE 4 -#define SIGRD 5 -#define RWWSB 6 -#define SPMIE 7 - -/* Reserved [0x38..0x3C] */ - -/* SP [0x3D..0x3E] */ - -/* SREG [0x3F] */ - -#define WDTCSR _SFR_MEM8(0x60) -#define WDE 3 -#define WDCE 4 -#define WDP0 0 -#define WDP1 1 -#define WDP2 2 -#define WDP3 5 -#define WDIE 6 -#define WDIF 7 - -#define CLKPR _SFR_MEM8(0x61) -#define CLKPS0 0 -#define CLKPS1 1 -#define CLKPS2 2 -#define CLKPS3 3 -#define CLKPCE 7 - -#define XFDCSR _SFR_MEM8(0x62) -#define XFDIE 0 -#define XFDIF 1 - -#define PRR2 _SFR_MEM8(0x63) -#define PRTWI1 0 -#define PRSPI1 1 -#define PRUSART2 2 -#define PRPTC 3 - -#define __AVR_HAVE_PRR2 ((1<, never directly. */ - -#ifndef _AVR_IO_H_ -# error "Include instead of this file." -#endif - -#ifndef _AVR_IOXXX_H_ -# define _AVR_IOXXX_H_ "iom325.h" -#else -# error "Attempt to include more than one file." -#endif - -/* Registers and associated bit numbers */ - -#define PINA _SFR_IO8(0x00) -#define PINA7 7 -#define PINA6 6 -#define PINA5 5 -#define PINA4 4 -#define PINA3 3 -#define PINA2 2 -#define PINA1 1 -#define PINA0 0 - -#define DDRA _SFR_IO8(0x01) -#define DDA7 7 -#define DDA6 6 -#define DDA5 5 -#define DDA4 4 -#define DDA3 3 -#define DDA2 2 -#define DDA1 1 -#define DDA0 0 - -#define PORTA _SFR_IO8(0x02) -#define PA7 7 -#define PA6 6 -#define PA5 5 -#define PA4 4 -#define PA3 3 -#define PA2 2 -#define PA1 1 -#define PA0 0 - -#define PINB _SFR_IO8(0x03) -#define PINB7 7 -#define PINB6 6 -#define PINB5 5 -#define PINB4 4 -#define PINB3 3 -#define PINB2 2 -#define PINB1 1 -#define PINB0 0 - -#define DDRB _SFR_IO8(0x04) -#define DDB7 7 -#define DDB6 6 -#define DDB5 5 -#define DDB4 4 -#define DDB3 3 -#define DDB2 2 -#define DDB1 1 -#define DDB0 0 - -#define PORTB _SFR_IO8(0x05) -#define PB7 7 -#define PB6 6 -#define PB5 5 -#define PB4 4 -#define PB3 3 -#define PB2 2 -#define PB1 1 -#define PB0 0 - -#define PINC _SFR_IO8(0x06) -#define PINC7 7 -#define PINC6 6 -#define PINC5 5 -#define PINC4 4 -#define PINC3 3 -#define PINC2 2 -#define PINC1 1 -#define PINC0 0 - -#define DDRC _SFR_IO8(0x07) -#define DDC7 7 -#define DDC6 6 -#define DDC5 5 -#define DDC4 4 -#define DDC3 3 -#define DDC2 2 -#define DDC1 1 -#define DDC0 0 - -#define PORTC _SFR_IO8(0x08) -#define PC7 7 -#define PC6 6 -#define PC5 5 -#define PC4 4 -#define PC3 3 -#define PC2 2 -#define PC1 1 -#define PC0 0 - -#define PIND _SFR_IO8(0x09) -#define PIND7 7 -#define PIND6 6 -#define PIND5 5 -#define PIND4 4 -#define PIND3 3 -#define PIND2 2 -#define PIND1 1 -#define PIND0 0 - -#define DDRD _SFR_IO8(0x0A) -#define DDD7 7 -#define DDD6 6 -#define DDD5 5 -#define DDD4 4 -#define DDD3 3 -#define DDD2 2 -#define DDD1 1 -#define DDD0 0 - -#define PORTD _SFR_IO8(0x0B) -#define PD7 7 -#define PD6 6 -#define PD5 5 -#define PD4 4 -#define PD3 3 -#define PD2 2 -#define PD1 1 -#define PD0 0 - -#define PINE _SFR_IO8(0x0C) -#define PINE7 7 -#define PINE6 6 -#define PINE5 5 -#define PINE4 4 -#define PINE3 3 -#define PINE2 2 -#define PINE1 1 -#define PINE0 0 - -#define DDRE _SFR_IO8(0x0D) -#define DDE7 7 -#define DDE6 6 -#define DDE5 5 -#define DDE4 4 -#define DDE3 3 -#define DDE2 2 -#define DDE1 1 -#define DDE0 0 - -#define PORTE _SFR_IO8(0x0E) -#define PE7 7 -#define PE6 6 -#define PE5 5 -#define PE4 4 -#define PE3 3 -#define PE2 2 -#define PE1 1 -#define PE0 0 - -#define PINF _SFR_IO8(0x0F) -#define PINF7 7 -#define PINF6 6 -#define PINF5 5 -#define PINF4 4 -#define PINF3 3 -#define PINF2 2 -#define PINF1 1 -#define PINF0 0 - -#define DDRF _SFR_IO8(0x10) -#define DDF7 7 -#define DDF6 6 -#define DDF5 5 -#define DDF4 4 -#define DDF3 3 -#define DDF2 2 -#define DDF1 1 -#define DDF0 0 - -#define PORTF _SFR_IO8(0x11) -#define PF7 7 -#define PF6 6 -#define PF5 5 -#define PF4 4 -#define PF3 3 -#define PF2 2 -#define PF1 1 -#define PF0 0 - -#define PING _SFR_IO8(0x12) -#define PING5 5 -#define PING4 4 -#define PING3 3 -#define PING2 2 -#define PING1 1 -#define PING0 0 - -#define DDRG _SFR_IO8(0x13) -#define DDG4 4 -#define DDG3 3 -#define DDG2 2 -#define DDG1 1 -#define DDG0 0 - -#define PORTG _SFR_IO8(0x14) -#define PG4 4 -#define PG3 3 -#define PG2 2 -#define PG1 1 -#define PG0 0 - -#define TIFR0 _SFR_IO8(0x15) -#define TOV0 0 -#define OCF0A 1 - -#define TIFR1 _SFR_IO8(0x16) -#define TOV1 0 -#define OCF1A 1 -#define OCF1B 2 -#define ICF1 5 - -#define TIFR2 _SFR_IO8(0x17) -#define TOV2 0 -#define OCF2A 1 - -/* Reserved [0x18..0x1B] */ - -#define EIFR _SFR_IO8(0x1C) -#define INTF0 0 -#define PCIF0 4 -#define PCIF1 5 - -#define EIMSK _SFR_IO8(0x1D) -#define INT0 0 -#define PCIE0 4 -#define PCIE1 5 - -#define GPIOR0 _SFR_IO8(0x1E) - -#define EECR _SFR_IO8(0x1F) -#define EERE 0 -#define EEWE 1 -#define EEMWE 2 -#define EERIE 3 - -#define EEDR _SFR_IO8(0X20) - -/* Combine EEARL and EEARH */ -#define EEAR _SFR_IO16(0x21) -#define EEARL _SFR_IO8(0x21) -#define EEARH _SFR_IO8(0X22) - -/* 6-char sequence denoting where to find the EEPROM registers in memory space. - Adresses denoted in hex syntax with uppercase letters. Used by the EEPROM - subroutines. - First two letters: EECR address. - Second two letters: EEDR address. - Last two letters: EEAR address. */ -#define __EEPROM_REG_LOCATIONS__ 1F2021 - - -#define GTCCR _SFR_IO8(0x23) -#define PSR10 0 -#define PSR2 1 -#define TSM 7 - -#define TCCR0A _SFR_IO8(0x24) -#define CS00 0 -#define CS01 1 -#define CS02 2 -#define WGM01 3 -#define COM0A0 4 -#define COM0A1 5 -#define WGM00 6 -#define FOC0A 7 - -/* Reserved [0x25] */ - -#define TCNT0 _SFR_IO8(0X26) - -#define OCR0A _SFR_IO8(0X27) - -/* Reserved [0x28..0x29] */ - -#define GPIOR1 _SFR_IO8(0x2A) - -#define GPIOR2 _SFR_IO8(0x2B) - -#define SPCR _SFR_IO8(0x2C) -#define SPR0 0 -#define SPR1 1 -#define CPHA 2 -#define CPOL 3 -#define MSTR 4 -#define DORD 5 -#define SPE 6 -#define SPIE 7 - -#define SPSR _SFR_IO8(0x2D) -#define SPI2X 0 -#define WCOL 6 -#define SPIF 7 - -#define SPDR _SFR_IO8(0X2E) - -/* Reserved [0x2F] */ - -#define ACSR _SFR_IO8(0x30) -#define ACIS0 0 -#define ACIS1 1 -#define ACIC 2 -#define ACIE 3 -#define ACI 4 -#define ACO 5 -#define ACBG 6 -#define ACD 7 - -#define OCDR _SFR_IO8(0x31) -#define OCDR0 0 -#define OCDR1 1 -#define OCDR2 2 -#define OCDR3 3 -#define OCDR4 4 -#define OCDR5 5 -#define OCDR6 6 -#define OCDR7 7 -#define IDRD 7 - -/* Reserved [0x32] */ - -#define SMCR _SFR_IO8(0x33) -#define SE 0 -#define SM0 1 -#define SM1 2 -#define SM2 3 - -#define MCUSR _SFR_IO8(0x34) -#define PORF 0 -#define EXTRF 1 -#define BORF 2 -#define WDRF 3 -#define JTRF 4 - -#define MCUCR _SFR_IO8(0X35) -#define IVCE 0 -#define IVSEL 1 -#define PUD 4 -#if defined(__AVR_ATmega325P__) -#define BODSE 5 -#define BODS 6 -#endif -#define JTD 7 - -/* Reserved [0x36] */ - -#define SPMCSR _SFR_IO8(0x37) -#define SPMEN 0 -#define PGERS 1 -#define PGWRT 2 -#define BLBSET 3 -#define RWWSRE 4 -#define RWWSB 6 -#define SPMIE 7 - -/* Reserved [0x38..0x3C] */ - -/* SP [0x3D..0x3E] */ -/* SREG [0x3F] */ - -#define WDTCR _SFR_MEM8(0x60) -#define WDP0 0 -#define WDP1 1 -#define WDP2 2 -#define WDE 3 -#define WDCE 4 - -#define CLKPR _SFR_MEM8(0x61) -#define CLKPS0 0 -#define CLKPS1 1 -#define CLKPS2 2 -#define CLKPS3 3 -#define CLKPCE 7 - -/* Reserved [0x62..0x63] */ - -#define PRR _SFR_MEM8(0x64) -#define PRADC 0 -#define PRUSART0 1 -#define PRSPI 2 -#define PRTIM1 3 - -#define __AVR_HAVE_PRR ((1<, never directly. */ - -#ifndef _AVR_IO_H_ -# error "Include instead of this file." -#endif - -#ifndef _AVR_IOXXX_H_ -# define _AVR_IOXXX_H_ "iom3250.h" -#else -# error "Attempt to include more than one file." -#endif - -/* Registers and associated bit numbers */ - -#define PINA _SFR_IO8(0x00) -#define PINA7 7 -#define PINA6 6 -#define PINA5 5 -#define PINA4 4 -#define PINA3 3 -#define PINA2 2 -#define PINA1 1 -#define PINA0 0 - -#define DDRA _SFR_IO8(0x01) -#define DDA7 7 -#define DDA6 6 -#define DDA5 5 -#define DDA4 4 -#define DDA3 3 -#define DDA2 2 -#define DDA1 1 -#define DDA0 0 - -#define PORTA _SFR_IO8(0x02) -#define PA7 7 -#define PA6 6 -#define PA5 5 -#define PA4 4 -#define PA3 3 -#define PA2 2 -#define PA1 1 -#define PA0 0 - -#define PINB _SFR_IO8(0x03) -#define PINB7 7 -#define PINB6 6 -#define PINB5 5 -#define PINB4 4 -#define PINB3 3 -#define PINB2 2 -#define PINB1 1 -#define PINB0 0 - -#define DDRB _SFR_IO8(0x04) -#define DDB7 7 -#define DDB6 6 -#define DDB5 5 -#define DDB4 4 -#define DDB3 3 -#define DDB2 2 -#define DDB1 1 -#define DDB0 0 - -#define PORTB _SFR_IO8(0x05) -#define PB7 7 -#define PB6 6 -#define PB5 5 -#define PB4 4 -#define PB3 3 -#define PB2 2 -#define PB1 1 -#define PB0 0 - -#define PINC _SFR_IO8(0x06) -#define PINC7 7 -#define PINC6 6 -#define PINC5 5 -#define PINC4 4 -#define PINC3 3 -#define PINC2 2 -#define PINC1 1 -#define PINC0 0 - -#define DDRC _SFR_IO8(0x07) -#define DDC7 7 -#define DDC6 6 -#define DDC5 5 -#define DDC4 4 -#define DDC3 3 -#define DDC2 2 -#define DDC1 1 -#define DDC0 0 - -#define PORTC _SFR_IO8(0x08) -#define PC7 7 -#define PC6 6 -#define PC5 5 -#define PC4 4 -#define PC3 3 -#define PC2 2 -#define PC1 1 -#define PC0 0 - -#define PIND _SFR_IO8(0x09) -#define PIND7 7 -#define PIND6 6 -#define PIND5 5 -#define PIND4 4 -#define PIND3 3 -#define PIND2 2 -#define PIND1 1 -#define PIND0 0 - -#define DDRD _SFR_IO8(0x0A) -#define DDD7 7 -#define DDD6 6 -#define DDD5 5 -#define DDD4 4 -#define DDD3 3 -#define DDD2 2 -#define DDD1 1 -#define DDD0 0 - -#define PORTD _SFR_IO8(0x0B) -#define PD7 7 -#define PD6 6 -#define PD5 5 -#define PD4 4 -#define PD3 3 -#define PD2 2 -#define PD1 1 -#define PD0 0 - -#define PINE _SFR_IO8(0x0C) -#define PINE7 7 -#define PINE6 6 -#define PINE5 5 -#define PINE4 4 -#define PINE3 3 -#define PINE2 2 -#define PINE1 1 -#define PINE0 0 - -#define DDRE _SFR_IO8(0x0D) -#define DDE7 7 -#define DDE6 6 -#define DDE5 5 -#define DDE4 4 -#define DDE3 3 -#define DDE2 2 -#define DDE1 1 -#define DDE0 0 - -#define PORTE _SFR_IO8(0x0E) -#define PE7 7 -#define PE6 6 -#define PE5 5 -#define PE4 4 -#define PE3 3 -#define PE2 2 -#define PE1 1 -#define PE0 0 - -#define PINF _SFR_IO8(0x0F) -#define PINF7 7 -#define PINF6 6 -#define PINF5 5 -#define PINF4 4 -#define PINF3 3 -#define PINF2 2 -#define PINF1 1 -#define PINF0 0 - -#define DDRF _SFR_IO8(0x10) -#define DDF7 7 -#define DDF6 6 -#define DDF5 5 -#define DDF4 4 -#define DDF3 3 -#define DDF2 2 -#define DDF1 1 -#define DDF0 0 - -#define PORTF _SFR_IO8(0x11) -#define PF7 7 -#define PF6 6 -#define PF5 5 -#define PF4 4 -#define PF3 3 -#define PF2 2 -#define PF1 1 -#define PF0 0 - -#define PING _SFR_IO8(0x12) -#define PING5 5 -#define PING4 4 -#define PING3 3 -#define PING2 2 -#define PING1 1 -#define PING0 0 - -#define DDRG _SFR_IO8(0x13) -#define DDG4 4 -#define DDG3 3 -#define DDG2 2 -#define DDG1 1 -#define DDG0 0 - -#define PORTG _SFR_IO8(0x14) -#define PG4 4 -#define PG3 3 -#define PG2 2 -#define PG1 1 -#define PG0 0 - -#define TIFR0 _SFR_IO8(0x15) -#define TOV0 0 -#define OCF0A 1 - -#define TIFR1 _SFR_IO8(0x16) -#define TOV1 0 -#define OCF1A 1 -#define OCF1B 2 -#define ICF1 5 - -#define TIFR2 _SFR_IO8(0x17) -#define TOV2 0 -#define OCF2A 1 - -/* Reserved [0x18..0x1B] */ - -#define EIFR _SFR_IO8(0x1C) -#define INTF0 0 -#define PCIF0 4 -#define PCIF1 5 -#define PCIF2 6 -#define PCIF3 7 - -#define EIMSK _SFR_IO8(0x1D) -#define INT0 0 -#define PCIE0 4 -#define PCIE1 5 -#define PCIE2 6 -#define PCIE3 7 - -#define GPIOR0 _SFR_IO8(0x1E) - -#define EECR _SFR_IO8(0x1F) -#define EERE 0 -#define EEWE 1 -#define EEMWE 2 -#define EERIE 3 - -#define EEDR _SFR_IO8(0X20) - -/* Combine EEARL and EEARH */ -#define EEAR _SFR_IO16(0x21) -#define EEARL _SFR_IO8(0x21) -#define EEARH _SFR_IO8(0X22) - -/* 6-char sequence denoting where to find the EEPROM registers in memory space. - Adresses denoted in hex syntax with uppercase letters. Used by the EEPROM - subroutines. - First two letters: EECR address. - Second two letters: EEDR address. - Last two letters: EEAR address. */ -#define __EEPROM_REG_LOCATIONS__ 1F2021 - -#define GTCCR _SFR_IO8(0x23) -#define PSR10 0 -#define PSR2 1 -#define TSM 7 - -#define TCCR0A _SFR_IO8(0x24) -#define CS00 0 -#define CS01 1 -#define CS02 2 -#define WGM01 3 -#define COM0A0 4 -#define COM0A1 5 -#define WGM00 6 -#define FOC0A 7 - -/* Reserved [0x25] */ - -#define TCNT0 _SFR_IO8(0X26) - -#define OCR0A _SFR_IO8(0X27) - -/* Reserved [0x28..0x29] */ - -#define GPIOR1 _SFR_IO8(0x2A) - -#define GPIOR2 _SFR_IO8(0x2B) - -#define SPCR _SFR_IO8(0x2C) -#define SPR0 0 -#define SPR1 1 -#define CPHA 2 -#define CPOL 3 -#define MSTR 4 -#define DORD 5 -#define SPE 6 -#define SPIE 7 - -#define SPSR _SFR_IO8(0x2D) -#define SPI2X 0 -#define WCOL 6 -#define SPIF 7 - -#define SPDR _SFR_IO8(0X2E) - -/* Reserved [0x2F] */ - -#define ACSR _SFR_IO8(0x30) -#define ACIS0 0 -#define ACIS1 1 -#define ACIC 2 -#define ACIE 3 -#define ACI 4 -#define ACO 5 -#define ACBG 6 -#define ACD 7 - -#define OCDR _SFR_IO8(0x31) -#define OCDR0 0 -#define OCDR1 1 -#define OCDR2 2 -#define OCDR3 3 -#define OCDR4 4 -#define OCDR5 5 -#define OCDR6 6 -#define OCDR7 7 -#define IDRD 7 - -/* Reserved [0x32] */ - -#define SMCR _SFR_IO8(0x33) -#define SE 0 -#define SM0 1 -#define SM1 2 -#define SM2 3 - -#define MCUSR _SFR_IO8(0x34) -#define PORF 0 -#define EXTRF 1 -#define BORF 2 -#define WDRF 3 -#define JTRF 4 - -#define MCUCR _SFR_IO8(0X35) -#define IVCE 0 -#define IVSEL 1 -#define PUD 4 -#if defined(__AVR_ATmega3250P__) -#define BODSE 5 -#define BODS 6 -#endif -#define JTD 7 - -/* Reserved [0x36] */ - -#define SPMCSR _SFR_IO8(0x37) -#define SPMEN 0 -#define PGERS 1 -#define PGWRT 2 -#define BLBSET 3 -#define RWWSRE 4 -#define RWWSB 6 -#define SPMIE 7 - -/* Reserved [0x38..0x3C] */ - -/* SP [0x3D..0x3E] */ -/* SREG [0x3F] */ - -#define WDTCR _SFR_MEM8(0x60) -#define WDP0 0 -#define WDP1 1 -#define WDP2 2 -#define WDE 3 -#define WDCE 4 - -#define CLKPR _SFR_MEM8(0x61) -#define CLKPS0 0 -#define CLKPS1 1 -#define CLKPS2 2 -#define CLKPS3 3 -#define CLKPCE 7 - -/* Reserved [0x62..0x63] */ - -#define PRR _SFR_MEM8(0x64) -#define PRADC 0 -#define PRUSART0 1 -#define PRSPI 2 -#define PRTIM1 3 - -#define __AVR_HAVE_PRR ((1< instead of this file." -#endif - -#ifndef _AVR_IOXXX_H_ -# define _AVR_IOXXX_H_ "iom3250pa.h" -#else -# error "Attempt to include more than one file." -#endif - -/* Registers and associated bit numbers */ - -#define PINA _SFR_IO8(0x00) -#define PINA7 7 -#define PINA6 6 -#define PINA5 5 -#define PINA4 4 -#define PINA3 3 -#define PINA2 2 -#define PINA1 1 -#define PINA0 0 - -#define DDRA _SFR_IO8(0x01) -#define DDRA7 7 -// Inserted "DDA7" from "DDRA7" due to compatibility -#define DDA7 7 -#define DDRA6 6 -// Inserted "DDA6" from "DDRA6" due to compatibility -#define DDA6 6 -#define DDRA5 5 -// Inserted "DDA5" from "DDRA5" due to compatibility -#define DDA5 5 -#define DDRA4 4 -// Inserted "DDA4" from "DDRA4" due to compatibility -#define DDA4 4 -#define DDRA3 3 -// Inserted "DDA3" from "DDRA3" due to compatibility -#define DDA3 3 -#define DDRA2 2 -// Inserted "DDA2" from "DDRA2" due to compatibility -#define DDA2 2 -#define DDRA1 1 -// Inserted "DDA1" from "DDRA1" due to compatibility -#define DDA1 1 -#define DDRA0 0 -// Inserted "DDA0" from "DDRA0" due to compatibility -#define DDA0 0 - -#define PORTA _SFR_IO8(0x02) -#define PORTA7 7 -#define PORTA6 6 -#define PORTA5 5 -#define PORTA4 4 -#define PORTA3 3 -#define PORTA2 2 -#define PORTA1 1 -#define PORTA0 0 - -#define PINB _SFR_IO8(0x03) -#define PINB7 7 -#define PINB6 6 -#define PINB5 5 -#define PINB4 4 -#define PINB3 3 -#define PINB2 2 -#define PINB1 1 -#define PINB0 0 - -#define DDRB _SFR_IO8(0x04) -#define DDRB7 7 -// Inserted "DDB7" from "DDRB7" due to compatibility -#define DDB7 7 -#define DDRB6 6 -// Inserted "DDB6" from "DDRB6" due to compatibility -#define DDB6 6 -#define DDRB5 5 -// Inserted "DDB5" from "DDRB5" due to compatibility -#define DDB5 5 -#define DDRB4 4 -// Inserted "DDB4" from "DDRB4" due to compatibility -#define DDB4 4 -#define DDRB3 3 -// Inserted "DDB3" from "DDRB3" due to compatibility -#define DDB3 3 -#define DDRB2 2 -// Inserted "DDB2" from "DDRB2" due to compatibility -#define DDB2 2 -#define DDRB1 1 -// Inserted "DDB1" from "DDRB1" due to compatibility -#define DDB1 1 -#define DDRB0 0 -// Inserted "DDB0" from "DDRB0" due to compatibility -#define DDB0 0 - -#define PORTB _SFR_IO8(0x05) -#define PORTB7 7 -#define PORTB6 6 -#define PORTB5 5 -#define PORTB4 4 -#define PORTB3 3 -#define PORTB2 2 -#define PORTB1 1 -#define PORTB0 0 - -#define PINC _SFR_IO8(0x06) -#define PINC7 7 -#define PINC6 6 -#define PINC5 5 -#define PINC4 4 -#define PINC3 3 -#define PINC2 2 -#define PINC1 1 -#define PINC0 0 - -#define DDRC _SFR_IO8(0x07) -#define DDRC7 7 -// Inserted "DDC7" from "DDRC7" due to compatibility -#define DDC7 7 -#define DDRC6 6 -// Inserted "DDC6" from "DDRC6" due to compatibility -#define DDC6 6 -#define DDRC5 5 -// Inserted "DDC5" from "DDRC5" due to compatibility -#define DDC5 5 -#define DDRC4 4 -// Inserted "DDC4" from "DDRC4" due to compatibility -#define DDC4 4 -#define DDRC3 3 -// Inserted "DDC3" from "DDRC3" due to compatibility -#define DDC3 3 -#define DDRC2 2 -// Inserted "DDC2" from "DDRC2" due to compatibility -#define DDC2 2 -#define DDRC1 1 -// Inserted "DDC1" from "DDRC1" due to compatibility -#define DDC1 1 -#define DDRC0 0 -// Inserted "DDC0" from "DDRC0" due to compatibility -#define DDC0 0 - -#define PORTC _SFR_IO8(0x08) -#define PORTC7 7 -#define PORTC6 6 -#define PORTC5 5 -#define PORTC4 4 -#define PORTC3 3 -#define PORTC2 2 -#define PORTC1 1 -#define PORTC0 0 - -#define PIND _SFR_IO8(0x09) -#define PIND7 7 -#define PIND6 6 -#define PIND5 5 -#define PIND4 4 -#define PIND3 3 -#define PIND2 2 -#define PIND1 1 -#define PIND0 0 - -#define DDRD _SFR_IO8(0x0A) -#define DDRD7 7 -// Inserted "DDD7" from "DDRD7" due to compatibility -#define DDD7 7 -#define DDRD6 6 -// Inserted "DDD6" from "DDRD6" due to compatibility -#define DDD6 6 -#define DDRD5 5 -// Inserted "DDD5" from "DDRD5" due to compatibility -#define DDD5 5 -#define DDRD4 4 -// Inserted "DDD4" from "DDRD4" due to compatibility -#define DDD4 4 -#define DDRD3 3 -// Inserted "DDD3" from "DDRD3" due to compatibility -#define DDD3 3 -#define DDRD2 2 -// Inserted "DDD2" from "DDRD2" due to compatibility -#define DDD2 2 -#define DDRD1 1 -// Inserted "DDD1" from "DDRD1" due to compatibility -#define DDD1 1 -#define DDRD0 0 -// Inserted "DDD0" from "DDRD0" due to compatibility -#define DDD0 0 - -#define PORTD _SFR_IO8(0x0B) -#define PORTD7 7 -#define PORTD6 6 -#define PORTD5 5 -#define PORTD4 4 -#define PORTD3 3 -#define PORTD2 2 -#define PORTD1 1 -#define PORTD0 0 - -#define PINE _SFR_IO8(0x0C) -#define PINE7 7 -#define PINE6 6 -#define PINE5 5 -#define PINE4 4 -#define PINE3 3 -#define PINE2 2 -#define PINE1 1 -#define PINE0 0 - -#define DDRE _SFR_IO8(0x0D) -#define DDRE7 7 -// Inserted "DDE7" from "DDRE7" due to compatibility -#define DDE7 7 -#define DDRE6 6 -// Inserted "DDE6" from "DDRE6" due to compatibility -#define DDE6 6 -#define DDRE5 5 -// Inserted "DDE5" from "DDRE5" due to compatibility -#define DDE5 5 -#define DDRE4 4 -// Inserted "DDE4" from "DDRE4" due to compatibility -#define DDE4 4 -#define DDRE3 3 -// Inserted "DDE3" from "DDRE3" due to compatibility -#define DDE3 3 -#define DDRE2 2 -// Inserted "DDE2" from "DDRE2" due to compatibility -#define DDE2 2 -#define DDRE1 1 -// Inserted "DDE1" from "DDRE1" due to compatibility -#define DDE1 1 -#define DDRE0 0 -// Inserted "DDE0" from "DDRE0" due to compatibility -#define DDE0 0 - -#define PORTE _SFR_IO8(0x0E) -#define PORTE7 7 -#define PORTE6 6 -#define PORTE5 5 -#define PORTE4 4 -#define PORTE3 3 -#define PORTE2 2 -#define PORTE1 1 -#define PORTE0 0 - -#define PINF _SFR_IO8(0x0F) -#define PINF7 7 -#define PINF6 6 -#define PINF5 5 -#define PINF4 4 -#define PINF3 3 -#define PINF2 2 -#define PINF1 1 -#define PINF0 0 - -#define DDRF _SFR_IO8(0x10) -#define DDRF7 7 -// Inserted "DDF7" from "DDRF7" due to compatibility -#define DDF7 7 -#define DDRF6 6 -// Inserted "DDF6" from "DDRF6" due to compatibility -#define DDF6 6 -#define DDRF5 5 -// Inserted "DDF5" from "DDRF5" due to compatibility -#define DDF5 5 -#define DDRF4 4 -// Inserted "DDF4" from "DDRF4" due to compatibility -#define DDF4 4 -#define DDRF3 3 -// Inserted "DDF3" from "DDRF3" due to compatibility -#define DDF3 3 -#define DDRF2 2 -// Inserted "DDF2" from "DDRF2" due to compatibility -#define DDF2 2 -#define DDRF1 1 -// Inserted "DDF1" from "DDRF1" due to compatibility -#define DDF1 1 -#define DDRF0 0 -// Inserted "DDF0" from "DDRF0" due to compatibility -#define DDF0 0 - -#define PORTF _SFR_IO8(0x11) -#define PORTF7 7 -#define PORTF6 6 -#define PORTF5 5 -#define PORTF4 4 -#define PORTF3 3 -#define PORTF2 2 -#define PORTF1 1 -#define PORTF0 0 - -#define PING _SFR_IO8(0x12) -#define PING5 5 -#define PING4 4 -#define PING3 3 -#define PING2 2 -#define PING1 1 -#define PING0 0 - -#define DDRG _SFR_IO8(0x13) -#define DDRG4 4 -// Inserted "DDG4" from "DDRG4" due to compatibility -#define DDG4 4 -#define DDRG3 3 -// Inserted "DDG3" from "DDRG3" due to compatibility -#define DDG3 3 -#define DDRG2 2 -// Inserted "DDG2" from "DDRG2" due to compatibility -#define DDG2 2 -#define DDRG1 1 -// Inserted "DDG1" from "DDRG1" due to compatibility -#define DDG1 1 -#define DDRG0 0 -// Inserted "DDG0" from "DDRG0" due to compatibility -#define DDG0 0 - -#define PORTG _SFR_IO8(0x14) -#define PORTG4 4 -#define PORTG3 3 -#define PORTG2 2 -#define PORTG1 1 -#define PORTG0 0 - -#define TIFR0 _SFR_IO8(0x15) -#define TOV0 0 -#define OCF0A 1 - -#define TIFR1 _SFR_IO8(0x16) -#define TOV1 0 -#define OCF1A 1 -#define OCF1B 2 -#define ICF1 5 - -#define TIFR2 _SFR_IO8(0x17) -#define TOV2 0 -#define OCF2A 1 - -/* Reserved [0x18..0x1B] */ - -#define EIFR _SFR_IO8(0x1C) -#define INTF0 0 -#define PCIF0 4 -#define PCIF1 5 -#define PCIF2 6 -#define PCIF3 7 - -#define EIMSK _SFR_IO8(0x1D) -#define INT0 0 -#define PCIE0 4 -#define PCIE1 5 -#define PCIE2 6 -#define PCIE3 7 - -#define GPIOR0 _SFR_IO8(0x1E) - -#define EECR _SFR_IO8(0x1F) -#define EERE 0 -#define EEWE 1 -#define EEMWE 2 -#define EERIE 3 - -#define EEDR _SFR_IO8(0x20) - -/* Combine EEARL and EEARH */ -#define EEAR _SFR_IO16(0x21) - -#define EEARL _SFR_IO8(0x21) -#define EEARH _SFR_IO8(0x22) - -#define GTCCR _SFR_IO8(0x23) -#define PSR310 0 -#define TSM 7 -#define PSR2 1 - -#define TCCR0A _SFR_IO8(0x24) -#define CS00 0 -#define CS01 1 -#define CS02 2 -#define WGM01 3 -#define COM0A0 4 -#define COM0A1 5 -#define WGM00 6 -#define FOC0A 7 - -/* Reserved [0x25] */ - -#define TCNT0 _SFR_IO8(0x26) - -#define OCR0A _SFR_IO8(0x27) - -/* Reserved [0x28..0x29] */ - -#define GPIOR1 _SFR_IO8(0x2A) - -#define GPIOR2 _SFR_IO8(0x2B) - -#define SPCR _SFR_IO8(0x2C) -#define SPR0 0 -#define SPR1 1 -#define CPHA 2 -#define CPOL 3 -#define MSTR 4 -#define DORD 5 -#define SPE 6 -#define SPIE 7 - -#define SPSR _SFR_IO8(0x2D) -#define SPI2X 0 -#define WCOL 6 -#define SPIF 7 - -#define SPDR _SFR_IO8(0x2E) - -/* Reserved [0x2F] */ - -#define ACSR _SFR_IO8(0x30) -#define ACIS0 0 -#define ACIS1 1 -#define ACIC 2 -#define ACIE 3 -#define ACI 4 -#define ACO 5 -#define ACBG 6 -#define ACD 7 - -#define OCDR _SFR_IO8(0x31) -#define OCDR7 7 -#define OCDR6 6 -#define OCDR5 5 -#define OCDR4 4 -#define OCDR3 3 -#define OCDR2 2 -#define OCDR1 1 -#define OCDR0 0 - -/* Reserved [0x32] */ - -#define SMCR _SFR_IO8(0x33) -#define SE 0 -#define SM0 1 -#define SM1 2 -#define SM2 3 - -#define MCUSR _SFR_IO8(0x34) -#define JTRF 4 -#define PORF 0 -#define EXTRF 1 -#define BORF 2 -#define WDRF 3 - -#define MCUCR _SFR_IO8(0x35) -#define JTD 7 -#define IVCE 0 -#define IVSEL 1 -#define PUD 4 -#define BODSE 5 -#define BODS 6 - -/* Reserved [0x36] */ - -#define SPMCSR _SFR_IO8(0x37) -#define SPMEN 0 -#define PGERS 1 -#define PGWRT 2 -#define BLBSET 3 -#define RWWSRE 4 -#define RWWSB 6 -#define SPMIE 7 - -/* Reserved [0x38..0x3C] */ - -/* SP [0x3D..0x3E] */ - -/* SREG [0x3F] */ - -#define WDTCR _SFR_MEM8(0x60) -#define WDP0 0 -#define WDP1 1 -#define WDP2 2 -#define WDE 3 -#define WDCE 4 - -#define CLKPR _SFR_MEM8(0x61) -#define CLKPS0 0 -#define CLKPS1 1 -#define CLKPS2 2 -#define CLKPS3 3 -#define CLKPCE 7 - -/* Reserved [0x62..0x63] */ - -#define PRR _SFR_MEM8(0x64) -#define PRADC 0 -#define PRUSART0 1 -#define PRSPI 2 -#define PRTIM1 3 -#define PRLCD 4 - -#define __AVR_HAVE_PRR ((1< instead of this file." -#endif - -#ifndef _AVR_IOXXX_H_ -# define _AVR_IOXXX_H_ "iom325pa.h" -#else -# error "Attempt to include more than one file." -#endif - -/* Registers and associated bit numbers */ - -#define PINA _SFR_IO8(0x00) -#define PINA7 7 -#define PINA6 6 -#define PINA5 5 -#define PINA4 4 -#define PINA3 3 -#define PINA2 2 -#define PINA1 1 -#define PINA0 0 - -#define DDRA _SFR_IO8(0x01) -#define DDRA7 7 -// Inserted "DDA7" from "DDRA7" due to compatibility -#define DDA7 7 -#define DDRA6 6 -// Inserted "DDA6" from "DDRA6" due to compatibility -#define DDA6 6 -#define DDRA5 5 -// Inserted "DDA5" from "DDRA5" due to compatibility -#define DDA5 5 -#define DDRA4 4 -// Inserted "DDA4" from "DDRA4" due to compatibility -#define DDA4 4 -#define DDRA3 3 -// Inserted "DDA3" from "DDRA3" due to compatibility -#define DDA3 3 -#define DDRA2 2 -// Inserted "DDA2" from "DDRA2" due to compatibility -#define DDA2 2 -#define DDRA1 1 -// Inserted "DDA1" from "DDRA1" due to compatibility -#define DDA1 1 -#define DDRA0 0 -// Inserted "DDA0" from "DDRA0" due to compatibility -#define DDA0 0 - -#define PORTA _SFR_IO8(0x02) -#define PORTA7 7 -#define PORTA6 6 -#define PORTA5 5 -#define PORTA4 4 -#define PORTA3 3 -#define PORTA2 2 -#define PORTA1 1 -#define PORTA0 0 - -#define PINB _SFR_IO8(0x03) -#define PINB7 7 -#define PINB6 6 -#define PINB5 5 -#define PINB4 4 -#define PINB3 3 -#define PINB2 2 -#define PINB1 1 -#define PINB0 0 - -#define DDRB _SFR_IO8(0x04) -#define DDRB7 7 -// Inserted "DDB7" from "DDRB7" due to compatibility -#define DDB7 7 -#define DDRB6 6 -// Inserted "DDB6" from "DDRB6" due to compatibility -#define DDB6 6 -#define DDRB5 5 -// Inserted "DDB5" from "DDRB5" due to compatibility -#define DDB5 5 -#define DDRB4 4 -// Inserted "DDB4" from "DDRB4" due to compatibility -#define DDB4 4 -#define DDRB3 3 -// Inserted "DDB3" from "DDRB3" due to compatibility -#define DDB3 3 -#define DDRB2 2 -// Inserted "DDB2" from "DDRB2" due to compatibility -#define DDB2 2 -#define DDRB1 1 -// Inserted "DDB1" from "DDRB1" due to compatibility -#define DDB1 1 -#define DDRB0 0 -// Inserted "DDB0" from "DDRB0" due to compatibility -#define DDB0 0 - -#define PORTB _SFR_IO8(0x05) -#define PORTB7 7 -#define PORTB6 6 -#define PORTB5 5 -#define PORTB4 4 -#define PORTB3 3 -#define PORTB2 2 -#define PORTB1 1 -#define PORTB0 0 - -#define PINC _SFR_IO8(0x06) -#define PINC7 7 -#define PINC6 6 -#define PINC5 5 -#define PINC4 4 -#define PINC3 3 -#define PINC2 2 -#define PINC1 1 -#define PINC0 0 - -#define DDRC _SFR_IO8(0x07) -#define DDRC7 7 -// Inserted "DDC7" from "DDRC7" due to compatibility -#define DDC7 7 -#define DDRC6 6 -// Inserted "DDC6" from "DDRC6" due to compatibility -#define DDC6 6 -#define DDRC5 5 -// Inserted "DDC5" from "DDRC5" due to compatibility -#define DDC5 5 -#define DDRC4 4 -// Inserted "DDC4" from "DDRC4" due to compatibility -#define DDC4 4 -#define DDRC3 3 -// Inserted "DDC3" from "DDRC3" due to compatibility -#define DDC3 3 -#define DDRC2 2 -// Inserted "DDC2" from "DDRC2" due to compatibility -#define DDC2 2 -#define DDRC1 1 -// Inserted "DDC1" from "DDRC1" due to compatibility -#define DDC1 1 -#define DDRC0 0 -// Inserted "DDC0" from "DDRC0" due to compatibility -#define DDC0 0 - -#define PORTC _SFR_IO8(0x08) -#define PORTC7 7 -#define PORTC6 6 -#define PORTC5 5 -#define PORTC4 4 -#define PORTC3 3 -#define PORTC2 2 -#define PORTC1 1 -#define PORTC0 0 - -#define PIND _SFR_IO8(0x09) -#define PIND7 7 -#define PIND6 6 -#define PIND5 5 -#define PIND4 4 -#define PIND3 3 -#define PIND2 2 -#define PIND1 1 -#define PIND0 0 - -#define DDRD _SFR_IO8(0x0A) -#define DDRD7 7 -// Inserted "DDD7" from "DDRD7" due to compatibility -#define DDD7 7 -#define DDRD6 6 -// Inserted "DDD6" from "DDRD6" due to compatibility -#define DDD6 6 -#define DDRD5 5 -// Inserted "DDD5" from "DDRD5" due to compatibility -#define DDD5 5 -#define DDRD4 4 -// Inserted "DDD4" from "DDRD4" due to compatibility -#define DDD4 4 -#define DDRD3 3 -// Inserted "DDD3" from "DDRD3" due to compatibility -#define DDD3 3 -#define DDRD2 2 -// Inserted "DDD2" from "DDRD2" due to compatibility -#define DDD2 2 -#define DDRD1 1 -// Inserted "DDD1" from "DDRD1" due to compatibility -#define DDD1 1 -#define DDRD0 0 -// Inserted "DDD0" from "DDRD0" due to compatibility -#define DDD0 0 - -#define PORTD _SFR_IO8(0x0B) -#define PORTD7 7 -#define PORTD6 6 -#define PORTD5 5 -#define PORTD4 4 -#define PORTD3 3 -#define PORTD2 2 -#define PORTD1 1 -#define PORTD0 0 - -#define PINE _SFR_IO8(0x0C) -#define PINE7 7 -#define PINE6 6 -#define PINE5 5 -#define PINE4 4 -#define PINE3 3 -#define PINE2 2 -#define PINE1 1 -#define PINE0 0 - -#define DDRE _SFR_IO8(0x0D) -#define DDRE7 7 -// Inserted "DDE7" from "DDRE7" due to compatibility -#define DDE7 7 -#define DDRE6 6 -// Inserted "DDE6" from "DDRE6" due to compatibility -#define DDE6 6 -#define DDRE5 5 -// Inserted "DDE5" from "DDRE5" due to compatibility -#define DDE5 5 -#define DDRE4 4 -// Inserted "DDE4" from "DDRE4" due to compatibility -#define DDE4 4 -#define DDRE3 3 -// Inserted "DDE3" from "DDRE3" due to compatibility -#define DDE3 3 -#define DDRE2 2 -// Inserted "DDE2" from "DDRE2" due to compatibility -#define DDE2 2 -#define DDRE1 1 -// Inserted "DDE1" from "DDRE1" due to compatibility -#define DDE1 1 -#define DDRE0 0 -// Inserted "DDE0" from "DDRE0" due to compatibility -#define DDE0 0 - -#define PORTE _SFR_IO8(0x0E) -#define PORTE7 7 -#define PORTE6 6 -#define PORTE5 5 -#define PORTE4 4 -#define PORTE3 3 -#define PORTE2 2 -#define PORTE1 1 -#define PORTE0 0 - -#define PINF _SFR_IO8(0x0F) -#define PINF7 7 -#define PINF6 6 -#define PINF5 5 -#define PINF4 4 -#define PINF3 3 -#define PINF2 2 -#define PINF1 1 -#define PINF0 0 - -#define DDRF _SFR_IO8(0x10) -#define DDRF7 7 -// Inserted "DDF7" from "DDRF7" due to compatibility -#define DDF7 7 -#define DDRF6 6 -// Inserted "DDF6" from "DDRF6" due to compatibility -#define DDF6 6 -#define DDRF5 5 -// Inserted "DDF5" from "DDRF5" due to compatibility -#define DDF5 5 -#define DDRF4 4 -// Inserted "DDF4" from "DDRF4" due to compatibility -#define DDF4 4 -#define DDRF3 3 -// Inserted "DDF3" from "DDRF3" due to compatibility -#define DDF3 3 -#define DDRF2 2 -// Inserted "DDF2" from "DDRF2" due to compatibility -#define DDF2 2 -#define DDRF1 1 -// Inserted "DDF1" from "DDRF1" due to compatibility -#define DDF1 1 -#define DDRF0 0 -// Inserted "DDF0" from "DDRF0" due to compatibility -#define DDF0 0 - -#define PORTF _SFR_IO8(0x11) -#define PORTF7 7 -#define PORTF6 6 -#define PORTF5 5 -#define PORTF4 4 -#define PORTF3 3 -#define PORTF2 2 -#define PORTF1 1 -#define PORTF0 0 - -#define PING _SFR_IO8(0x12) -#define PING5 5 -#define PING4 4 -#define PING3 3 -#define PING2 2 -#define PING1 1 -#define PING0 0 - -#define DDRG _SFR_IO8(0x13) -#define DDRG4 4 -// Inserted "DDG4" from "DDRG4" due to compatibility -#define DDG4 4 -#define DDRG3 3 -// Inserted "DDG3" from "DDRG3" due to compatibility -#define DDG3 3 -#define DDRG2 2 -// Inserted "DDG2" from "DDRG2" due to compatibility -#define DDG2 2 -#define DDRG1 1 -// Inserted "DDG1" from "DDRG1" due to compatibility -#define DDG1 1 -#define DDRG0 0 -// Inserted "DDG0" from "DDRG0" due to compatibility -#define DDG0 0 - -#define PORTG _SFR_IO8(0x14) -#define PORTG4 4 -#define PORTG3 3 -#define PORTG2 2 -#define PORTG1 1 -#define PORTG0 0 - -#define TIFR0 _SFR_IO8(0x15) -#define TOV0 0 -#define OCF0A 1 - -#define TIFR1 _SFR_IO8(0x16) -#define TOV1 0 -#define OCF1A 1 -#define OCF1B 2 -#define ICF1 5 - -#define TIFR2 _SFR_IO8(0x17) -#define TOV2 0 -#define OCF2A 1 - -/* Reserved [0x18..0x1B] */ - -#define EIFR _SFR_IO8(0x1C) -#define INTF0 0 -#define PCIF0 4 -#define PCIF1 5 -#define PCIF2 6 -#define PCIF3 7 - -#define EIMSK _SFR_IO8(0x1D) -#define INT0 0 -#define PCIE0 4 -#define PCIE1 5 -#define PCIE2 6 -#define PCIE3 7 - -#define GPIOR0 _SFR_IO8(0x1E) - -#define EECR _SFR_IO8(0x1F) -#define EERE 0 -#define EEWE 1 -#define EEMWE 2 -#define EERIE 3 - -#define EEDR _SFR_IO8(0x20) - -/* Combine EEARL and EEARH */ -#define EEAR _SFR_IO16(0x21) - -#define EEARL _SFR_IO8(0x21) -#define EEARH _SFR_IO8(0x22) - -#define GTCCR _SFR_IO8(0x23) -#define PSR310 0 -#define TSM 7 -#define PSR2 1 - -#define TCCR0A _SFR_IO8(0x24) -#define CS00 0 -#define CS01 1 -#define CS02 2 -#define WGM01 3 -#define COM0A0 4 -#define COM0A1 5 -#define WGM00 6 -#define FOC0A 7 - -/* Reserved [0x25] */ - -#define TCNT0 _SFR_IO8(0x26) - -#define OCR0A _SFR_IO8(0x27) - -/* Reserved [0x28..0x29] */ - -#define GPIOR1 _SFR_IO8(0x2A) - -#define GPIOR2 _SFR_IO8(0x2B) - -#define SPCR _SFR_IO8(0x2C) -#define SPR0 0 -#define SPR1 1 -#define CPHA 2 -#define CPOL 3 -#define MSTR 4 -#define DORD 5 -#define SPE 6 -#define SPIE 7 - -#define SPSR _SFR_IO8(0x2D) -#define SPI2X 0 -#define WCOL 6 -#define SPIF 7 - -#define SPDR _SFR_IO8(0x2E) - -/* Reserved [0x2F] */ - -#define ACSR _SFR_IO8(0x30) -#define ACIS0 0 -#define ACIS1 1 -#define ACIC 2 -#define ACIE 3 -#define ACI 4 -#define ACO 5 -#define ACBG 6 -#define ACD 7 - -#define OCDR _SFR_IO8(0x31) -#define OCDR7 7 -#define OCDR6 6 -#define OCDR5 5 -#define OCDR4 4 -#define OCDR3 3 -#define OCDR2 2 -#define OCDR1 1 -#define OCDR0 0 - -/* Reserved [0x32] */ - -#define SMCR _SFR_IO8(0x33) -#define SE 0 -#define SM0 1 -#define SM1 2 -#define SM2 3 - -#define MCUSR _SFR_IO8(0x34) -#define JTRF 4 -#define PORF 0 -#define EXTRF 1 -#define BORF 2 -#define WDRF 3 - -#define MCUCR _SFR_IO8(0x35) -#define JTD 7 -#define IVCE 0 -#define IVSEL 1 -#define PUD 4 -#define BODSE 5 -#define BODS 6 - -/* Reserved [0x36] */ - -#define SPMCSR _SFR_IO8(0x37) -#define SPMEN 0 -#define PGERS 1 -#define PGWRT 2 -#define BLBSET 3 -#define RWWSRE 4 -#define RWWSB 6 -#define SPMIE 7 - -/* Reserved [0x38..0x3C] */ - -/* SP [0x3D..0x3E] */ - -/* SREG [0x3F] */ - -#define WDTCR _SFR_MEM8(0x60) -#define WDP0 0 -#define WDP1 1 -#define WDP2 2 -#define WDE 3 -#define WDCE 4 - -#define CLKPR _SFR_MEM8(0x61) -#define CLKPS0 0 -#define CLKPS1 1 -#define CLKPS2 2 -#define CLKPS3 3 -#define CLKPCE 7 - -/* Reserved [0x62..0x63] */ - -#define PRR _SFR_MEM8(0x64) -#define PRADC 0 -#define PRUSART0 1 -#define PRSPI 2 -#define PRTIM1 3 -#define PRLCD 4 - -#define __AVR_HAVE_PRR ((1<, never directly. */ - -#ifndef _AVR_IO_H_ -# error "Include instead of this file." -#endif - -#ifndef _AVR_IOXXX_H_ -# define _AVR_IOXXX_H_ "iom328p.h" -#else -# error "Attempt to include more than one file." -#endif - - -#ifndef _AVR_IOM328P_H_ -#define _AVR_IOM328P_H_ 1 - -/* Registers and associated bit numbers */ - -#define PINB _SFR_IO8(0x03) -#define PINB0 0 -#define PINB1 1 -#define PINB2 2 -#define PINB3 3 -#define PINB4 4 -#define PINB5 5 -#define PINB6 6 -#define PINB7 7 - -#define DDRB _SFR_IO8(0x04) -#define DDB0 0 -#define DDB1 1 -#define DDB2 2 -#define DDB3 3 -#define DDB4 4 -#define DDB5 5 -#define DDB6 6 -#define DDB7 7 - -#define PORTB _SFR_IO8(0x05) -#define PORTB0 0 -#define PORTB1 1 -#define PORTB2 2 -#define PORTB3 3 -#define PORTB4 4 -#define PORTB5 5 -#define PORTB6 6 -#define PORTB7 7 - -#define PINC _SFR_IO8(0x06) -#define PINC0 0 -#define PINC1 1 -#define PINC2 2 -#define PINC3 3 -#define PINC4 4 -#define PINC5 5 -#define PINC6 6 - -#define DDRC _SFR_IO8(0x07) -#define DDC0 0 -#define DDC1 1 -#define DDC2 2 -#define DDC3 3 -#define DDC4 4 -#define DDC5 5 -#define DDC6 6 - -#define PORTC _SFR_IO8(0x08) -#define PORTC0 0 -#define PORTC1 1 -#define PORTC2 2 -#define PORTC3 3 -#define PORTC4 4 -#define PORTC5 5 -#define PORTC6 6 - -#define PIND _SFR_IO8(0x09) -#define PIND0 0 -#define PIND1 1 -#define PIND2 2 -#define PIND3 3 -#define PIND4 4 -#define PIND5 5 -#define PIND6 6 -#define PIND7 7 - -#define DDRD _SFR_IO8(0x0A) -#define DDD0 0 -#define DDD1 1 -#define DDD2 2 -#define DDD3 3 -#define DDD4 4 -#define DDD5 5 -#define DDD6 6 -#define DDD7 7 - -#define PORTD _SFR_IO8(0x0B) -#define PORTD0 0 -#define PORTD1 1 -#define PORTD2 2 -#define PORTD3 3 -#define PORTD4 4 -#define PORTD5 5 -#define PORTD6 6 -#define PORTD7 7 - -#define TIFR0 _SFR_IO8(0x15) -#define TOV0 0 -#define OCF0A 1 -#define OCF0B 2 - -#define TIFR1 _SFR_IO8(0x16) -#define TOV1 0 -#define OCF1A 1 -#define OCF1B 2 -#define ICF1 5 - -#define TIFR2 _SFR_IO8(0x17) -#define TOV2 0 -#define OCF2A 1 -#define OCF2B 2 - -#define PCIFR _SFR_IO8(0x1B) -#define PCIF0 0 -#define PCIF1 1 -#define PCIF2 2 - -#define EIFR _SFR_IO8(0x1C) -#define INTF0 0 -#define INTF1 1 - -#define EIMSK _SFR_IO8(0x1D) -#define INT0 0 -#define INT1 1 - -#define GPIOR0 _SFR_IO8(0x1E) -#define GPIOR00 0 -#define GPIOR01 1 -#define GPIOR02 2 -#define GPIOR03 3 -#define GPIOR04 4 -#define GPIOR05 5 -#define GPIOR06 6 -#define GPIOR07 7 - -#define EECR _SFR_IO8(0x1F) -#define EERE 0 -#define EEPE 1 -#define EEMPE 2 -#define EERIE 3 -#define EEPM0 4 -#define EEPM1 5 - -#define EEDR _SFR_IO8(0x20) -#define EEDR0 0 -#define EEDR1 1 -#define EEDR2 2 -#define EEDR3 3 -#define EEDR4 4 -#define EEDR5 5 -#define EEDR6 6 -#define EEDR7 7 - -#define EEAR _SFR_IO16(0x21) - -#define EEARL _SFR_IO8(0x21) -#define EEAR0 0 -#define EEAR1 1 -#define EEAR2 2 -#define EEAR3 3 -#define EEAR4 4 -#define EEAR5 5 -#define EEAR6 6 -#define EEAR7 7 - -#define EEARH _SFR_IO8(0x22) -#define EEAR8 0 -#define EEAR9 1 - -#define _EEPROM_REG_LOCATIONS_ 1F2021 - -#define GTCCR _SFR_IO8(0x23) -#define PSRSYNC 0 -#define PSRASY 1 -#define TSM 7 - -#define TCCR0A _SFR_IO8(0x24) -#define WGM00 0 -#define WGM01 1 -#define COM0B0 4 -#define COM0B1 5 -#define COM0A0 6 -#define COM0A1 7 - -#define TCCR0B _SFR_IO8(0x25) -#define CS00 0 -#define CS01 1 -#define CS02 2 -#define WGM02 3 -#define FOC0B 6 -#define FOC0A 7 - -#define TCNT0 _SFR_IO8(0x26) -#define TCNT0_0 0 -#define TCNT0_1 1 -#define TCNT0_2 2 -#define TCNT0_3 3 -#define TCNT0_4 4 -#define TCNT0_5 5 -#define TCNT0_6 6 -#define TCNT0_7 7 - -#define OCR0A _SFR_IO8(0x27) -#define OCR0A_0 0 -#define OCR0A_1 1 -#define OCR0A_2 2 -#define OCR0A_3 3 -#define OCR0A_4 4 -#define OCR0A_5 5 -#define OCR0A_6 6 -#define OCR0A_7 7 - -#define OCR0B _SFR_IO8(0x28) -#define OCR0B_0 0 -#define OCR0B_1 1 -#define OCR0B_2 2 -#define OCR0B_3 3 -#define OCR0B_4 4 -#define OCR0B_5 5 -#define OCR0B_6 6 -#define OCR0B_7 7 - -#define GPIOR1 _SFR_IO8(0x2A) -#define GPIOR10 0 -#define GPIOR11 1 -#define GPIOR12 2 -#define GPIOR13 3 -#define GPIOR14 4 -#define GPIOR15 5 -#define GPIOR16 6 -#define GPIOR17 7 - -#define GPIOR2 _SFR_IO8(0x2B) -#define GPIOR20 0 -#define GPIOR21 1 -#define GPIOR22 2 -#define GPIOR23 3 -#define GPIOR24 4 -#define GPIOR25 5 -#define GPIOR26 6 -#define GPIOR27 7 - -#define SPCR _SFR_IO8(0x2C) -#define SPR0 0 -#define SPR1 1 -#define CPHA 2 -#define CPOL 3 -#define MSTR 4 -#define DORD 5 -#define SPE 6 -#define SPIE 7 - -#define SPSR _SFR_IO8(0x2D) -#define SPI2X 0 -#define WCOL 6 -#define SPIF 7 - -#define SPDR _SFR_IO8(0x2E) -#define SPDR0 0 -#define SPDR1 1 -#define SPDR2 2 -#define SPDR3 3 -#define SPDR4 4 -#define SPDR5 5 -#define SPDR6 6 -#define SPDR7 7 - -#define ACSR _SFR_IO8(0x30) -#define ACIS0 0 -#define ACIS1 1 -#define ACIC 2 -#define ACIE 3 -#define ACI 4 -#define ACO 5 -#define ACBG 6 -#define ACD 7 - -#define SMCR _SFR_IO8(0x33) -#define SE 0 -#define SM0 1 -#define SM1 2 -#define SM2 3 - -#define MCUSR _SFR_IO8(0x34) -#define PORF 0 -#define EXTRF 1 -#define BORF 2 -#define WDRF 3 - -#define MCUCR _SFR_IO8(0x35) -#define IVCE 0 -#define IVSEL 1 -#define PUD 4 -#define BODSE 5 -#define BODS 6 - -#define SPMCSR _SFR_IO8(0x37) -#define SELFPRGEN 0 /* only for backwards compatibility with previous - * avr-libc versions; not an official name */ -#define SPMEN 0 -#define PGERS 1 -#define PGWRT 2 -#define BLBSET 3 -#define RWWSRE 4 -#define SIGRD 5 -#define RWWSB 6 -#define SPMIE 7 - -#define WDTCSR _SFR_MEM8(0x60) -#define WDP0 0 -#define WDP1 1 -#define WDP2 2 -#define WDE 3 -#define WDCE 4 -#define WDP3 5 -#define WDIE 6 -#define WDIF 7 - -#define CLKPR _SFR_MEM8(0x61) -#define CLKPS0 0 -#define CLKPS1 1 -#define CLKPS2 2 -#define CLKPS3 3 -#define CLKPCE 7 - -#define PRR _SFR_MEM8(0x64) -#define PRADC 0 -#define PRUSART0 1 -#define PRSPI 2 -#define PRTIM1 3 -#define PRTIM0 5 -#define PRTIM2 6 -#define PRTWI 7 - -#define __AVR_HAVE_PRR ((1< instead of this file." -#endif - -#ifndef _AVR_IOXXX_H_ -# define _AVR_IOXXX_H_ "iom328pb.h" -#else -# error "Attempt to include more than one file." -#endif - -/* Registers and associated bit numbers */ - -#define PINB _SFR_IO8(0x03) -#define PINB7 7 -#define PINB6 6 -#define PINB5 5 -#define PINB4 4 -#define PINB3 3 -#define PINB2 2 -#define PINB1 1 -#define PINB0 0 - -#define DDRB _SFR_IO8(0x04) -#define DDRB7 7 -// Inserted "DDB7" from "DDRB7" due to compatibility -#define DDB7 7 -#define DDRB6 6 -// Inserted "DDB6" from "DDRB6" due to compatibility -#define DDB6 6 -#define DDRB5 5 -// Inserted "DDB5" from "DDRB5" due to compatibility -#define DDB5 5 -#define DDRB4 4 -// Inserted "DDB4" from "DDRB4" due to compatibility -#define DDB4 4 -#define DDRB3 3 -// Inserted "DDB3" from "DDRB3" due to compatibility -#define DDB3 3 -#define DDRB2 2 -// Inserted "DDB2" from "DDRB2" due to compatibility -#define DDB2 2 -#define DDRB1 1 -// Inserted "DDB1" from "DDRB1" due to compatibility -#define DDB1 1 -#define DDRB0 0 -// Inserted "DDB0" from "DDRB0" due to compatibility -#define DDB0 0 - -#define PORTB _SFR_IO8(0x05) -#define PORTB7 7 -#define PORTB6 6 -#define PORTB5 5 -#define PORTB4 4 -#define PORTB3 3 -#define PORTB2 2 -#define PORTB1 1 -#define PORTB0 0 - -#define PINC _SFR_IO8(0x06) -#define PINC6 6 -#define PINC5 5 -#define PINC4 4 -#define PINC3 3 -#define PINC2 2 -#define PINC1 1 -#define PINC0 0 - -#define DDRC _SFR_IO8(0x07) -#define DDRC6 6 -// Inserted "DDC6" from "DDRC6" due to compatibility -#define DDC6 6 -#define DDRC5 5 -// Inserted "DDC5" from "DDRC5" due to compatibility -#define DDC5 5 -#define DDRC4 4 -// Inserted "DDC4" from "DDRC4" due to compatibility -#define DDC4 4 -#define DDRC3 3 -// Inserted "DDC3" from "DDRC3" due to compatibility -#define DDC3 3 -#define DDRC2 2 -// Inserted "DDC2" from "DDRC2" due to compatibility -#define DDC2 2 -#define DDRC1 1 -// Inserted "DDC1" from "DDRC1" due to compatibility -#define DDC1 1 -#define DDRC0 0 -// Inserted "DDC0" from "DDRC0" due to compatibility -#define DDC0 0 - -#define PORTC _SFR_IO8(0x08) -#define PORTC6 6 -#define PORTC5 5 -#define PORTC4 4 -#define PORTC3 3 -#define PORTC2 2 -#define PORTC1 1 -#define PORTC0 0 - -#define PIND _SFR_IO8(0x09) -#define PIND7 7 -#define PIND6 6 -#define PIND5 5 -#define PIND4 4 -#define PIND3 3 -#define PIND2 2 -#define PIND1 1 -#define PIND0 0 - -#define DDRD _SFR_IO8(0x0A) -#define DDRD7 7 -// Inserted "DDD7" from "DDRD7" due to compatibility -#define DDD7 7 -#define DDRD6 6 -// Inserted "DDD6" from "DDRD6" due to compatibility -#define DDD6 6 -#define DDRD5 5 -// Inserted "DDD5" from "DDRD5" due to compatibility -#define DDD5 5 -#define DDRD4 4 -// Inserted "DDD4" from "DDRD4" due to compatibility -#define DDD4 4 -#define DDRD3 3 -// Inserted "DDD3" from "DDRD3" due to compatibility -#define DDD3 3 -#define DDRD2 2 -// Inserted "DDD2" from "DDRD2" due to compatibility -#define DDD2 2 -#define DDRD1 1 -// Inserted "DDD1" from "DDRD1" due to compatibility -#define DDD1 1 -#define DDRD0 0 -// Inserted "DDD0" from "DDRD0" due to compatibility -#define DDD0 0 - -#define PORTD _SFR_IO8(0x0B) -#define PORTD7 7 -#define PORTD6 6 -#define PORTD5 5 -#define PORTD4 4 -#define PORTD3 3 -#define PORTD2 2 -#define PORTD1 1 -#define PORTD0 0 - -#define PINE _SFR_IO8(0x0C) -#define PINE3 3 -#define PINE2 2 -#define PINE1 1 -#define PINE0 0 - -#define DDRE _SFR_IO8(0x0D) -#define DDRE3 3 -// Inserted "DDE3" from "DDRE3" due to compatibility -#define DDE3 3 -#define DDRE2 2 -// Inserted "DDE2" from "DDRE2" due to compatibility -#define DDE2 2 -#define DDRE1 1 -// Inserted "DDE1" from "DDRE1" due to compatibility -#define DDE1 1 -#define DDRE0 0 -// Inserted "DDE0" from "DDRE0" due to compatibility -#define DDE0 0 - -#define PORTE _SFR_IO8(0x0E) -#define PORTE3 3 -#define PORTE2 2 -#define PORTE1 1 -#define PORTE0 0 - -/* Reserved [0x0F..0x14] */ - -#define TIFR0 _SFR_IO8(0x15) -#define TOV0 0 -#define OCF0A 1 -#define OCF0B 2 - -#define TIFR1 _SFR_IO8(0x16) -#define TOV1 0 -#define OCF1A 1 -#define OCF1B 2 -#define ICF1 5 - -#define TIFR2 _SFR_IO8(0x17) -#define TOV2 0 -#define OCF2A 1 -#define OCF2B 2 - -#define TIFR3 _SFR_IO8(0x18) -#define TOV3 0 -#define OCF3A 1 -#define OCF3B 2 - -#define TIFR4 _SFR_IO8(0x19) -#define TOV4 0 -#define OCF4A 1 -#define OCF4B 2 - -/* Reserved [0x1A] */ - -#define PCIFR _SFR_IO8(0x1B) -#define PCIF0 0 -#define PCIF1 1 -#define PCIF2 2 -#define PCIF3 3 - -#define EIFR _SFR_IO8(0x1C) -#define INTF0 0 -#define INTF1 1 - -#define EIMSK _SFR_IO8(0x1D) -#define INT0 0 -#define INT1 1 - -#define GPIOR0 _SFR_IO8(0x1E) - -#define EECR _SFR_IO8(0x1F) -#define EERE 0 -#define EEPE 1 -#define EEMPE 2 -#define EERIE 3 -#define EEPM0 4 -#define EEPM1 5 - -#define EEDR _SFR_IO8(0x20) - -/* Combine EEARL and EEARH */ -#define EEAR _SFR_IO16(0x21) - -#define EEARL _SFR_IO8(0x21) -#define EEARH _SFR_IO8(0x22) - -#define GTCCR _SFR_IO8(0x23) -#define PSRSYNC 0 -#define TSM 7 -#define PSRASY 1 - -#define TCCR0A _SFR_IO8(0x24) -#define WGM00 0 -#define WGM01 1 -#define COM0B0 4 -#define COM0B1 5 -#define COM0A0 6 -#define COM0A1 7 - -#define TCCR0B _SFR_IO8(0x25) -#define CS00 0 -#define CS01 1 -#define CS02 2 -#define WGM02 3 -#define FOC0B 6 -#define FOC0A 7 - -#define TCNT0 _SFR_IO8(0x26) - -#define OCR0A _SFR_IO8(0x27) - -#define OCR0B _SFR_IO8(0x28) - -/* Reserved [0x29] */ - -#define GPIOR1 _SFR_IO8(0x2A) - -#define GPIOR2 _SFR_IO8(0x2B) - -#define SPCR0 _SFR_IO8(0x2C) -#define SPR0 0 -#define SPR1 1 -#define CPHA 2 -#define CPOL 3 -#define MSTR 4 -#define DORD 5 -#define SPE 6 -#define SPIE 7 - -#define SPSR0 _SFR_IO8(0x2D) -#define SPI2X 0 -#define WCOL 6 -#define SPIF 7 - -#define SPDR0 _SFR_IO8(0x2E) - -#define ACSRB _SFR_IO8(0x2F) -#define ACOE 0 - -#define ACSRA _SFR_IO8(0x30) - -#define ACSR _SFR_IO8(0x30) -#define ACIS0 0 -#define ACIS1 1 -#define ACIC 2 -#define ACIE 3 -#define ACI 4 -#define ACO 5 -#define ACBG 6 -#define ACD 7 - -/* Reserved [0x31..0x32] */ - -#define SMCR _SFR_IO8(0x33) -#define SE 0 -#define SM0 1 -#define SM1 2 -#define SM2 3 - -#define MCUSR _SFR_IO8(0x34) -#define PORF 0 -#define EXTRF 1 -#define BORF 2 -#define WDRF 3 - -#define MCUCR _SFR_IO8(0x35) -#define IVCE 0 -#define IVSEL 1 -#define PUD 4 -#define BODSE 5 -#define BODS 6 - -/* Reserved [0x36] */ - -#define SPMCSR _SFR_IO8(0x37) -#define SPMEN 0 -#define PGERS 1 -#define PGWRT 2 -#define BLBSET 3 -#define RWWSRE 4 -#define SIGRD 5 -#define RWWSB 6 -#define SPMIE 7 - -/* Reserved [0x38..0x3C] */ - -/* SP [0x3D..0x3E] */ - -/* SREG [0x3F] */ - -#define WDTCSR _SFR_MEM8(0x60) -#define WDE 3 -#define WDCE 4 -#define WDP0 0 -#define WDP1 1 -#define WDP2 2 -#define WDP3 5 -#define WDIE 6 -#define WDIF 7 - -#define CLKPR _SFR_MEM8(0x61) -#define CLKPS0 0 -#define CLKPS1 1 -#define CLKPS2 2 -#define CLKPS3 3 -#define CLKPCE 7 - -#define XFDCSR _SFR_MEM8(0x62) -#define XFDIE 0 -#define XFDIF 1 - -/* Reserved [0x63] */ - -#define PRR0 _SFR_MEM8(0x64) -#define PRADC 0 -#define PRUSART0 1 -#define PRSPI0 2 -#define PRTIM1 3 -#define PRUSART1 4 -#define PRTIM0 5 -#define PRTIM2 6 -#define PRTWI0 7 - -#define __AVR_HAVE_PRR0 ((1<, never directly. */ - -#ifndef _AVR_IO_H_ -# error "Include instead of this file." -#endif - -#ifndef _AVR_IOXXX_H_ -# define _AVR_IOXXX_H_ "iom329.h" -#else -# error "Attempt to include more than one file." -#endif - -/* Registers and associated bit numbers */ - -#define PINA _SFR_IO8(0x00) -#define PINA7 7 -#define PINA6 6 -#define PINA5 5 -#define PINA4 4 -#define PINA3 3 -#define PINA2 2 -#define PINA1 1 -#define PINA0 0 - -#define DDRA _SFR_IO8(0x01) -#define DDA7 7 -#define DDA6 6 -#define DDA5 5 -#define DDA4 4 -#define DDA3 3 -#define DDA2 2 -#define DDA1 1 -#define DDA0 0 - -#define PORTA _SFR_IO8(0x02) -#define PA7 7 -#define PA6 6 -#define PA5 5 -#define PA4 4 -#define PA3 3 -#define PA2 2 -#define PA1 1 -#define PA0 0 - -#define PINB _SFR_IO8(0x03) -#define PINB7 7 -#define PINB6 6 -#define PINB5 5 -#define PINB4 4 -#define PINB3 3 -#define PINB2 2 -#define PINB1 1 -#define PINB0 0 - -#define DDRB _SFR_IO8(0x04) -#define DDB7 7 -#define DDB6 6 -#define DDB5 5 -#define DDB4 4 -#define DDB3 3 -#define DDB2 2 -#define DDB1 1 -#define DDB0 0 - -#define PORTB _SFR_IO8(0x05) -#define PB7 7 -#define PB6 6 -#define PB5 5 -#define PB4 4 -#define PB3 3 -#define PB2 2 -#define PB1 1 -#define PB0 0 - -#define PINC _SFR_IO8(0x06) -#define PINC7 7 -#define PINC6 6 -#define PINC5 5 -#define PINC4 4 -#define PINC3 3 -#define PINC2 2 -#define PINC1 1 -#define PINC0 0 - -#define DDRC _SFR_IO8(0x07) -#define DDC7 7 -#define DDC6 6 -#define DDC5 5 -#define DDC4 4 -#define DDC3 3 -#define DDC2 2 -#define DDC1 1 -#define DDC0 0 - -#define PORTC _SFR_IO8(0x08) -#define PC7 7 -#define PC6 6 -#define PC5 5 -#define PC4 4 -#define PC3 3 -#define PC2 2 -#define PC1 1 -#define PC0 0 - -#define PIND _SFR_IO8(0x09) -#define PIND7 7 -#define PIND6 6 -#define PIND5 5 -#define PIND4 4 -#define PIND3 3 -#define PIND2 2 -#define PIND1 1 -#define PIND0 0 - -#define DDRD _SFR_IO8(0x0A) -#define DDD7 7 -#define DDD6 6 -#define DDD5 5 -#define DDD4 4 -#define DDD3 3 -#define DDD2 2 -#define DDD1 1 -#define DDD0 0 - -#define PORTD _SFR_IO8(0x0B) -#define PD7 7 -#define PD6 6 -#define PD5 5 -#define PD4 4 -#define PD3 3 -#define PD2 2 -#define PD1 1 -#define PD0 0 - -#define PINE _SFR_IO8(0x0C) -#define PINE7 7 -#define PINE6 6 -#define PINE5 5 -#define PINE4 4 -#define PINE3 3 -#define PINE2 2 -#define PINE1 1 -#define PINE0 0 - -#define DDRE _SFR_IO8(0x0D) -#define DDE7 7 -#define DDE6 6 -#define DDE5 5 -#define DDE4 4 -#define DDE3 3 -#define DDE2 2 -#define DDE1 1 -#define DDE0 0 - -#define PORTE _SFR_IO8(0x0E) -#define PE7 7 -#define PE6 6 -#define PE5 5 -#define PE4 4 -#define PE3 3 -#define PE2 2 -#define PE1 1 -#define PE0 0 - -#define PINF _SFR_IO8(0x0F) -#define PINF7 7 -#define PINF6 6 -#define PINF5 5 -#define PINF4 4 -#define PINF3 3 -#define PINF2 2 -#define PINF1 1 -#define PINF0 0 - -#define DDRF _SFR_IO8(0x10) -#define DDF7 7 -#define DDF6 6 -#define DDF5 5 -#define DDF4 4 -#define DDF3 3 -#define DDF2 2 -#define DDF1 1 -#define DDF0 0 - -#define PORTF _SFR_IO8(0x11) -#define PF7 7 -#define PF6 6 -#define PF5 5 -#define PF4 4 -#define PF3 3 -#define PF2 2 -#define PF1 1 -#define PF0 0 - -#define PING _SFR_IO8(0x12) -#define PING5 5 -#define PING4 4 -#define PING3 3 -#define PING2 2 -#define PING1 1 -#define PING0 0 - -#define DDRG _SFR_IO8(0x13) -#define DDG4 4 -#define DDG3 3 -#define DDG2 2 -#define DDG1 1 -#define DDG0 0 - -#define PORTG _SFR_IO8(0x14) -#define PG4 4 -#define PG3 3 -#define PG2 2 -#define PG1 1 -#define PG0 0 - -#define TIFR0 _SFR_IO8(0x15) -#define TOV0 0 -#define OCF0A 1 - -#define TIFR1 _SFR_IO8(0x16) -#define TOV1 0 -#define OCF1A 1 -#define OCF1B 2 -#define ICF1 5 - -#define TIFR2 _SFR_IO8(0x17) -#define TOV2 0 -#define OCF2A 1 - -/* Reserved [0x18..0x1B] */ - -#define EIFR _SFR_IO8(0x1C) -#define INTF0 0 -#define PCIF0 4 -#define PCIF1 5 - -#define EIMSK _SFR_IO8(0x1D) -#define INT0 0 -#define PCIE0 4 -#define PCIE1 5 - -#define GPIOR0 _SFR_IO8(0x1E) - -#define EECR _SFR_IO8(0x1F) -#define EERIE 3 -#define EEMWE 2 -#define EEWE 1 -#define EERE 0 - -#define EEDR _SFR_IO8(0X20) - -/* Combine EEARL and EEARH */ -#define EEAR _SFR_IO16(0x21) -#define EEARL _SFR_IO8(0x21) -#define EEARH _SFR_IO8(0X22) - -/* 6-char sequence denoting where to find the EEPROM registers in memory space. - Adresses denoted in hex syntax with uppercase letters. Used by the EEPROM - subroutines. - First two letters: EECR address. - Second two letters: EEDR address. - Last two letters: EEAR address. */ -#define __EEPROM_REG_LOCATIONS__ 1F2021 - -#define GTCCR _SFR_IO8(0x23) -#define PSR10 0 -#define PSR2 1 -#define TSM 7 - -#define TCCR0A _SFR_IO8(0x24) -#define CS00 0 -#define CS01 1 -#define CS02 2 -#define WGM01 3 -#define COM0A0 4 -#define COM0A1 5 -#define WGM00 6 -#define FOC0A 7 - -/* Reserved [0x25] */ - -#define TCNT0 _SFR_IO8(0X26) - -#define OCR0A _SFR_IO8(0X27) - -/* Reserved [0x28..0x29] */ - -#define GPIOR1 _SFR_IO8(0x2A) - -#define GPIOR2 _SFR_IO8(0x2B) - -#define SPCR _SFR_IO8(0x2C) -#define SPR0 0 -#define SPR1 1 -#define CPHA 2 -#define CPOL 3 -#define MSTR 4 -#define DORD 5 -#define SPE 6 -#define SPIE 7 - -#define SPSR _SFR_IO8(0x2D) -#define SPI2X 0 -#define WCOL 6 -#define SPIF 7 - -#define SPDR _SFR_IO8(0X2E) - -/* Reserved [0x2F] */ - -#define ACSR _SFR_IO8(0x30) -#define ACIS0 0 -#define ACIS1 1 -#define ACIC 2 -#define ACIE 3 -#define ACI 4 -#define ACO 5 -#define ACBG 6 -#define ACD 7 - -#define OCDR _SFR_IO8(0x31) -#define OCDR0 0 -#define OCDR1 1 -#define OCDR2 2 -#define OCDR3 3 -#define OCDR4 4 -#define OCDR5 5 -#define OCDR6 6 -#define OCDR7 7 -#define IDRD 7 - -/* Reserved [0x32] */ - -#define SMCR _SFR_IO8(0x33) -#define SE 0 -#define SM0 1 -#define SM1 2 -#define SM2 3 - -#define MCUSR _SFR_IO8(0x34) -#define PORF 0 -#define EXTRF 1 -#define BORF 2 -#define WDRF 3 -#define JTRF 4 - -#define MCUCR _SFR_IO8(0X35) -#define IVCE 0 -#define IVSEL 1 -#define PUD 4 -#if defined(__AVR_ATmega329P__) -#define BODSE 5 -#define BODS 6 -#endif -#define JTD 7 - -/* Reserved [0x36] */ - -#define SPMCSR _SFR_IO8(0x37) -#define SPMEN 0 -#define PGERS 1 -#define PGWRT 2 -#define BLBSET 3 -#define RWWSRE 4 -#define RWWSB 6 -#define SPMIE 7 - -/* Reserved [0x38..0x3C] */ - -/* SP [0x3D..0x3E] */ -/* SREG [0x3F] */ - -#define WDTCR _SFR_MEM8(0x60) -#define WDP0 0 -#define WDP1 1 -#define WDP2 2 -#define WDE 3 -#define WDCE 4 - -#define CLKPR _SFR_MEM8(0x61) -#define CLKPS0 0 -#define CLKPS1 1 -#define CLKPS2 2 -#define CLKPS3 3 -#define CLKPCE 7 - -/* Reserved [0x62..0x63] */ - -#define PRR _SFR_MEM8(0x64) -#define PRADC 0 -#define PRUSART0 1 -#define PRSPI 2 -#define PRTIM1 3 -#define PRLCD 4 - -#define __AVR_HAVE_PRR ((1<, never directly. */ - -#ifndef _AVR_IO_H_ -# error "Include instead of this file." -#endif - -#ifndef _AVR_IOXXX_H_ -# define _AVR_IOXXX_H_ "iom3290.h" -#else -# error "Attempt to include more than one file." -#endif - -/* Registers and associated bit numbers */ - -#define PINA _SFR_IO8(0x00) -#define PINA7 7 -#define PINA6 6 -#define PINA5 5 -#define PINA4 4 -#define PINA3 3 -#define PINA2 2 -#define PINA1 1 -#define PINA0 0 - -#define DDRA _SFR_IO8(0x01) -#define DDA7 7 -#define DDA6 6 -#define DDA5 5 -#define DDA4 4 -#define DDA3 3 -#define DDA2 2 -#define DDA1 1 -#define DDA0 0 - -#define PORTA _SFR_IO8(0x02) -#define PA7 7 -#define PA6 6 -#define PA5 5 -#define PA4 4 -#define PA3 3 -#define PA2 2 -#define PA1 1 -#define PA0 0 - -#define PINB _SFR_IO8(0x03) -#define PINB7 7 -#define PINB6 6 -#define PINB5 5 -#define PINB4 4 -#define PINB3 3 -#define PINB2 2 -#define PINB1 1 -#define PINB0 0 - -#define DDRB _SFR_IO8(0x04) -#define DDB7 7 -#define DDB6 6 -#define DDB5 5 -#define DDB4 4 -#define DDB3 3 -#define DDB2 2 -#define DDB1 1 -#define DDB0 0 - -#define PORTB _SFR_IO8(0x05) -#define PB7 7 -#define PB6 6 -#define PB5 5 -#define PB4 4 -#define PB3 3 -#define PB2 2 -#define PB1 1 -#define PB0 0 - -#define PINC _SFR_IO8(0x06) -#define PINC7 7 -#define PINC6 6 -#define PINC5 5 -#define PINC4 4 -#define PINC3 3 -#define PINC2 2 -#define PINC1 1 -#define PINC0 0 - -#define DDRC _SFR_IO8(0x07) -#define DDC7 7 -#define DDC6 6 -#define DDC5 5 -#define DDC4 4 -#define DDC3 3 -#define DDC2 2 -#define DDC1 1 -#define DDC0 0 - -#define PORTC _SFR_IO8(0x08) -#define PC7 7 -#define PC6 6 -#define PC5 5 -#define PC4 4 -#define PC3 3 -#define PC2 2 -#define PC1 1 -#define PC0 0 - -#define PIND _SFR_IO8(0x09) -#define PIND7 7 -#define PIND6 6 -#define PIND5 5 -#define PIND4 4 -#define PIND3 3 -#define PIND2 2 -#define PIND1 1 -#define PIND0 0 - -#define DDRD _SFR_IO8(0x0A) -#define DDD7 7 -#define DDD6 6 -#define DDD5 5 -#define DDD4 4 -#define DDD3 3 -#define DDD2 2 -#define DDD1 1 -#define DDD0 0 - -#define PORTD _SFR_IO8(0x0B) -#define PD7 7 -#define PD6 6 -#define PD5 5 -#define PD4 4 -#define PD3 3 -#define PD2 2 -#define PD1 1 -#define PD0 0 - -#define PINE _SFR_IO8(0x0C) -#define PINE7 7 -#define PINE6 6 -#define PINE5 5 -#define PINE4 4 -#define PINE3 3 -#define PINE2 2 -#define PINE1 1 -#define PINE0 0 - -#define DDRE _SFR_IO8(0x0D) -#define DDE7 7 -#define DDE6 6 -#define DDE5 5 -#define DDE4 4 -#define DDE3 3 -#define DDE2 2 -#define DDE1 1 -#define DDE0 0 - -#define PORTE _SFR_IO8(0x0E) -#define PE7 7 -#define PE6 6 -#define PE5 5 -#define PE4 4 -#define PE3 3 -#define PE2 2 -#define PE1 1 -#define PE0 0 - -#define PINF _SFR_IO8(0x0F) -#define PINF7 7 -#define PINF6 6 -#define PINF5 5 -#define PINF4 4 -#define PINF3 3 -#define PINF2 2 -#define PINF1 1 -#define PINF0 0 - -#define DDRF _SFR_IO8(0x10) -#define DDF7 7 -#define DDF6 6 -#define DDF5 5 -#define DDF4 4 -#define DDF3 3 -#define DDF2 2 -#define DDF1 1 -#define DDF0 0 - -#define PORTF _SFR_IO8(0x11) -#define PF7 7 -#define PF6 6 -#define PF5 5 -#define PF4 4 -#define PF3 3 -#define PF2 2 -#define PF1 1 -#define PF0 0 - -#define PING _SFR_IO8(0x12) -#define PING5 5 -#define PING4 4 -#define PING3 3 -#define PING2 2 -#define PING1 1 -#define PING0 0 - -#define DDRG _SFR_IO8(0x13) -#define DDG4 4 -#define DDG3 3 -#define DDG2 2 -#define DDG1 1 -#define DDG0 0 - -#define PORTG _SFR_IO8(0x14) -#define PG4 4 -#define PG3 3 -#define PG2 2 -#define PG1 1 -#define PG0 0 - -#define TIFR0 _SFR_IO8(0x15) -#define TOV0 0 -#define OCF0A 1 - -#define TIFR1 _SFR_IO8(0x16) -#define TOV1 0 -#define OCF1A 1 -#define OCF1B 2 -#define ICF1 5 - -#define TIFR2 _SFR_IO8(0x17) -#define TOV2 0 -#define OCF2A 1 - -/* Reserved [0x18..0x1B] */ - -#define EIFR _SFR_IO8(0x1C) -#define INTF0 0 -#define PCIF0 4 -#define PCIF1 5 -#define PCIF2 6 -#define PCIF3 7 - -#define EIMSK _SFR_IO8(0x1D) -#define INT0 0 -#define PCIE0 4 -#define PCIE1 5 -#define PCIE2 6 -#define PCIE3 7 - -#define GPIOR0 _SFR_IO8(0x1E) - -#define EECR _SFR_IO8(0x1F) -#define EERIE 3 -#define EEMWE 2 -#define EEWE 1 -#define EERE 0 - -#define EEDR _SFR_IO8(0X20) - -/* Combine EEARL and EEARH */ -#define EEAR _SFR_IO16(0x21) -#define EEARL _SFR_IO8(0x21) -#define EEARH _SFR_IO8(0X22) - -/* 6-char sequence denoting where to find the EEPROM registers in memory space. - Adresses denoted in hex syntax with uppercase letters. Used by the EEPROM - subroutines. - First two letters: EECR address. - Second two letters: EEDR address. - Last two letters: EEAR address. */ -#define __EEPROM_REG_LOCATIONS__ 1F2021 - -#define GTCCR _SFR_IO8(0x23) -#define PSR10 0 -#define PSR2 1 -#define TSM 7 - -#define TCCR0A _SFR_IO8(0x24) -#define CS00 0 -#define CS01 1 -#define CS02 2 -#define WGM01 3 -#define COM0A0 4 -#define COM0A1 5 -#define WGM00 6 -#define FOC0A 7 - -/* Reserved [0x25] */ - -#define TCNT0 _SFR_IO8(0X26) - -#define OCR0A _SFR_IO8(0X27) - -/* Reserved [0x28..0x29] */ - -#define GPIOR1 _SFR_IO8(0x2A) - -#define GPIOR2 _SFR_IO8(0x2B) - -#define SPCR _SFR_IO8(0x2C) -#define SPR0 0 -#define SPR1 1 -#define CPHA 2 -#define CPOL 3 -#define MSTR 4 -#define DORD 5 -#define SPE 6 -#define SPIE 7 - -#define SPSR _SFR_IO8(0x2D) -#define SPI2X 0 -#define WCOL 6 -#define SPIF 7 - -#define SPDR _SFR_IO8(0X2E) - -/* Reserved [0x2F] */ - -#define ACSR _SFR_IO8(0x30) -#define ACIS0 0 -#define ACIS1 1 -#define ACIC 2 -#define ACIE 3 -#define ACI 4 -#define ACO 5 -#define ACBG 6 -#define ACD 7 - -#define OCDR _SFR_IO8(0x31) -#define OCDR0 0 -#define OCDR1 1 -#define OCDR2 2 -#define OCDR3 3 -#define OCDR4 4 -#define OCDR5 5 -#define OCDR6 6 -#define OCDR7 7 -#define IDRD 7 - -/* Reserved [0x32] */ - -#define SMCR _SFR_IO8(0x33) -#define SE 0 -#define SM0 1 -#define SM1 2 -#define SM2 3 - -#define MCUSR _SFR_IO8(0x34) -#define PORF 0 -#define EXTRF 1 -#define BORF 2 -#define WDRF 3 -#define JTRF 4 - -#define MCUCR _SFR_IO8(0X35) -#define IVCE 0 -#define IVSEL 1 -#define PUD 4 -#if defined(__AVR_ATmega3290P__) -#define BODSE 5 -#define BODS 6 -#endif -#define JTD 7 - -/* Reserved [0x36] */ - -#define SPMCSR _SFR_IO8(0x37) -#define SPMEN 0 -#define PGERS 1 -#define PGWRT 2 -#define BLBSET 3 -#define RWWSRE 4 -#define RWWSB 6 -#define SPMIE 7 - -/* Reserved [0x38..0x3C] */ - -/* SP [0x3D..0x3E] */ -/* SREG [0x3F] */ - -#define WDTCR _SFR_MEM8(0x60) -#define WDP0 0 -#define WDP1 1 -#define WDP2 2 -#define WDE 3 -#define WDCE 4 - -#define CLKPR _SFR_MEM8(0x61) -#define CLKPS0 0 -#define CLKPS1 1 -#define CLKPS2 2 -#define CLKPS3 3 -#define CLKPCE 7 - -/* Reserved [0x62..0x63] */ - -#define PRR _SFR_MEM8(0x64) -#define PRADC 0 -#define PRUSART0 1 -#define PRSPI 2 -#define PRTIM1 3 -#define PRLCD 4 - -#define __AVR_HAVE_PRR ((1< instead of this file." -#endif - -#ifndef _AVR_IOXXX_H_ -# define _AVR_IOXXX_H_ "iom3290pa.h" -#else -# error "Attempt to include more than one file." -#endif - -/* Registers and associated bit numbers */ - -#define PINA _SFR_IO8(0x00) -#define PINA7 7 -#define PINA6 6 -#define PINA5 5 -#define PINA4 4 -#define PINA3 3 -#define PINA2 2 -#define PINA1 1 -#define PINA0 0 - -#define DDRA _SFR_IO8(0x01) -#define DDRA7 7 -// Inserted "DDA7" from "DDRA7" due to compatibility -#define DDA7 7 -#define DDRA6 6 -// Inserted "DDA6" from "DDRA6" due to compatibility -#define DDA6 6 -#define DDRA5 5 -// Inserted "DDA5" from "DDRA5" due to compatibility -#define DDA5 5 -#define DDRA4 4 -// Inserted "DDA4" from "DDRA4" due to compatibility -#define DDA4 4 -#define DDRA3 3 -// Inserted "DDA3" from "DDRA3" due to compatibility -#define DDA3 3 -#define DDRA2 2 -// Inserted "DDA2" from "DDRA2" due to compatibility -#define DDA2 2 -#define DDRA1 1 -// Inserted "DDA1" from "DDRA1" due to compatibility -#define DDA1 1 -#define DDRA0 0 -// Inserted "DDA0" from "DDRA0" due to compatibility -#define DDA0 0 - -#define PORTA _SFR_IO8(0x02) -#define PORTA7 7 -#define PORTA6 6 -#define PORTA5 5 -#define PORTA4 4 -#define PORTA3 3 -#define PORTA2 2 -#define PORTA1 1 -#define PORTA0 0 - -#define PINB _SFR_IO8(0x03) -#define PINB7 7 -#define PINB6 6 -#define PINB5 5 -#define PINB4 4 -#define PINB3 3 -#define PINB2 2 -#define PINB1 1 -#define PINB0 0 - -#define DDRB _SFR_IO8(0x04) -#define DDRB7 7 -// Inserted "DDB7" from "DDRB7" due to compatibility -#define DDB7 7 -#define DDRB6 6 -// Inserted "DDB6" from "DDRB6" due to compatibility -#define DDB6 6 -#define DDRB5 5 -// Inserted "DDB5" from "DDRB5" due to compatibility -#define DDB5 5 -#define DDRB4 4 -// Inserted "DDB4" from "DDRB4" due to compatibility -#define DDB4 4 -#define DDRB3 3 -// Inserted "DDB3" from "DDRB3" due to compatibility -#define DDB3 3 -#define DDRB2 2 -// Inserted "DDB2" from "DDRB2" due to compatibility -#define DDB2 2 -#define DDRB1 1 -// Inserted "DDB1" from "DDRB1" due to compatibility -#define DDB1 1 -#define DDRB0 0 -// Inserted "DDB0" from "DDRB0" due to compatibility -#define DDB0 0 - -#define PORTB _SFR_IO8(0x05) -#define PORTB7 7 -#define PORTB6 6 -#define PORTB5 5 -#define PORTB4 4 -#define PORTB3 3 -#define PORTB2 2 -#define PORTB1 1 -#define PORTB0 0 - -#define PINC _SFR_IO8(0x06) -#define PINC7 7 -#define PINC6 6 -#define PINC5 5 -#define PINC4 4 -#define PINC3 3 -#define PINC2 2 -#define PINC1 1 -#define PINC0 0 - -#define DDRC _SFR_IO8(0x07) -#define DDRC7 7 -// Inserted "DDC7" from "DDRC7" due to compatibility -#define DDC7 7 -#define DDRC6 6 -// Inserted "DDC6" from "DDRC6" due to compatibility -#define DDC6 6 -#define DDRC5 5 -// Inserted "DDC5" from "DDRC5" due to compatibility -#define DDC5 5 -#define DDRC4 4 -// Inserted "DDC4" from "DDRC4" due to compatibility -#define DDC4 4 -#define DDRC3 3 -// Inserted "DDC3" from "DDRC3" due to compatibility -#define DDC3 3 -#define DDRC2 2 -// Inserted "DDC2" from "DDRC2" due to compatibility -#define DDC2 2 -#define DDRC1 1 -// Inserted "DDC1" from "DDRC1" due to compatibility -#define DDC1 1 -#define DDRC0 0 -// Inserted "DDC0" from "DDRC0" due to compatibility -#define DDC0 0 - -#define PORTC _SFR_IO8(0x08) -#define PORTC7 7 -#define PORTC6 6 -#define PORTC5 5 -#define PORTC4 4 -#define PORTC3 3 -#define PORTC2 2 -#define PORTC1 1 -#define PORTC0 0 - -#define PIND _SFR_IO8(0x09) -#define PIND7 7 -#define PIND6 6 -#define PIND5 5 -#define PIND4 4 -#define PIND3 3 -#define PIND2 2 -#define PIND1 1 -#define PIND0 0 - -#define DDRD _SFR_IO8(0x0A) -#define DDRD7 7 -// Inserted "DDD7" from "DDRD7" due to compatibility -#define DDD7 7 -#define DDRD6 6 -// Inserted "DDD6" from "DDRD6" due to compatibility -#define DDD6 6 -#define DDRD5 5 -// Inserted "DDD5" from "DDRD5" due to compatibility -#define DDD5 5 -#define DDRD4 4 -// Inserted "DDD4" from "DDRD4" due to compatibility -#define DDD4 4 -#define DDRD3 3 -// Inserted "DDD3" from "DDRD3" due to compatibility -#define DDD3 3 -#define DDRD2 2 -// Inserted "DDD2" from "DDRD2" due to compatibility -#define DDD2 2 -#define DDRD1 1 -// Inserted "DDD1" from "DDRD1" due to compatibility -#define DDD1 1 -#define DDRD0 0 -// Inserted "DDD0" from "DDRD0" due to compatibility -#define DDD0 0 - -#define PORTD _SFR_IO8(0x0B) -#define PORTD7 7 -#define PORTD6 6 -#define PORTD5 5 -#define PORTD4 4 -#define PORTD3 3 -#define PORTD2 2 -#define PORTD1 1 -#define PORTD0 0 - -#define PINE _SFR_IO8(0x0C) -#define PINE7 7 -#define PINE6 6 -#define PINE5 5 -#define PINE4 4 -#define PINE3 3 -#define PINE2 2 -#define PINE1 1 -#define PINE0 0 - -#define DDRE _SFR_IO8(0x0D) -#define DDRE7 7 -// Inserted "DDE7" from "DDRE7" due to compatibility -#define DDE7 7 -#define DDRE6 6 -// Inserted "DDE6" from "DDRE6" due to compatibility -#define DDE6 6 -#define DDRE5 5 -// Inserted "DDE5" from "DDRE5" due to compatibility -#define DDE5 5 -#define DDRE4 4 -// Inserted "DDE4" from "DDRE4" due to compatibility -#define DDE4 4 -#define DDRE3 3 -// Inserted "DDE3" from "DDRE3" due to compatibility -#define DDE3 3 -#define DDRE2 2 -// Inserted "DDE2" from "DDRE2" due to compatibility -#define DDE2 2 -#define DDRE1 1 -// Inserted "DDE1" from "DDRE1" due to compatibility -#define DDE1 1 -#define DDRE0 0 -// Inserted "DDE0" from "DDRE0" due to compatibility -#define DDE0 0 - -#define PORTE _SFR_IO8(0x0E) -#define PORTE7 7 -#define PORTE6 6 -#define PORTE5 5 -#define PORTE4 4 -#define PORTE3 3 -#define PORTE2 2 -#define PORTE1 1 -#define PORTE0 0 - -#define PINF _SFR_IO8(0x0F) -#define PINF7 7 -#define PINF6 6 -#define PINF5 5 -#define PINF4 4 -#define PINF3 3 -#define PINF2 2 -#define PINF1 1 -#define PINF0 0 - -#define DDRF _SFR_IO8(0x10) -#define DDRF7 7 -// Inserted "DDF7" from "DDRF7" due to compatibility -#define DDF7 7 -#define DDRF6 6 -// Inserted "DDF6" from "DDRF6" due to compatibility -#define DDF6 6 -#define DDRF5 5 -// Inserted "DDF5" from "DDRF5" due to compatibility -#define DDF5 5 -#define DDRF4 4 -// Inserted "DDF4" from "DDRF4" due to compatibility -#define DDF4 4 -#define DDRF3 3 -// Inserted "DDF3" from "DDRF3" due to compatibility -#define DDF3 3 -#define DDRF2 2 -// Inserted "DDF2" from "DDRF2" due to compatibility -#define DDF2 2 -#define DDRF1 1 -// Inserted "DDF1" from "DDRF1" due to compatibility -#define DDF1 1 -#define DDRF0 0 -// Inserted "DDF0" from "DDRF0" due to compatibility -#define DDF0 0 - -#define PORTF _SFR_IO8(0x11) -#define PORTF7 7 -#define PORTF6 6 -#define PORTF5 5 -#define PORTF4 4 -#define PORTF3 3 -#define PORTF2 2 -#define PORTF1 1 -#define PORTF0 0 - -#define PING _SFR_IO8(0x12) -#define PING5 5 -#define PING4 4 -#define PING3 3 -#define PING2 2 -#define PING1 1 -#define PING0 0 - -#define DDRG _SFR_IO8(0x13) -#define DDRG4 4 -// Inserted "DDG4" from "DDRG4" due to compatibility -#define DDG4 4 -#define DDRG3 3 -// Inserted "DDG3" from "DDRG3" due to compatibility -#define DDG3 3 -#define DDRG2 2 -// Inserted "DDG2" from "DDRG2" due to compatibility -#define DDG2 2 -#define DDRG1 1 -// Inserted "DDG1" from "DDRG1" due to compatibility -#define DDG1 1 -#define DDRG0 0 -// Inserted "DDG0" from "DDRG0" due to compatibility -#define DDG0 0 - -#define PORTG _SFR_IO8(0x14) -#define PORTG4 4 -#define PORTG3 3 -#define PORTG2 2 -#define PORTG1 1 -#define PORTG0 0 - -#define TIFR0 _SFR_IO8(0x15) -#define TOV0 0 -#define OCF0A 1 - -#define TIFR1 _SFR_IO8(0x16) -#define TOV1 0 -#define OCF1A 1 -#define OCF1B 2 -#define ICF1 5 - -#define TIFR2 _SFR_IO8(0x17) -#define TOV2 0 -#define OCF2A 1 - -/* Reserved [0x18..0x1B] */ - -#define EIFR _SFR_IO8(0x1C) -#define INTF0 0 -#define PCIF0 4 -#define PCIF1 5 -#define PCIF2 6 -#define PCIF3 7 - -#define EIMSK _SFR_IO8(0x1D) -#define INT0 0 -#define PCIE0 4 -#define PCIE1 5 -#define PCIE2 6 -#define PCIE3 7 - -#define GPIOR0 _SFR_IO8(0x1E) - -#define EECR _SFR_IO8(0x1F) -#define EERE 0 -#define EEWE 1 -#define EEMWE 2 -#define EERIE 3 - -#define EEDR _SFR_IO8(0x20) - -/* Combine EEARL and EEARH */ -#define EEAR _SFR_IO16(0x21) - -#define EEARL _SFR_IO8(0x21) -#define EEARH _SFR_IO8(0x22) - -#define GTCCR _SFR_IO8(0x23) -#define PSR310 0 -#define TSM 7 -#define PSR2 1 - -#define TCCR0A _SFR_IO8(0x24) -#define CS00 0 -#define CS01 1 -#define CS02 2 -#define WGM01 3 -#define COM0A0 4 -#define COM0A1 5 -#define WGM00 6 -#define FOC0A 7 - -/* Reserved [0x25] */ - -#define TCNT0 _SFR_IO8(0x26) - -#define OCR0A _SFR_IO8(0x27) - -/* Reserved [0x28..0x29] */ - -#define GPIOR1 _SFR_IO8(0x2A) - -#define GPIOR2 _SFR_IO8(0x2B) - -#define SPCR _SFR_IO8(0x2C) -#define SPR0 0 -#define SPR1 1 -#define CPHA 2 -#define CPOL 3 -#define MSTR 4 -#define DORD 5 -#define SPE 6 -#define SPIE 7 - -#define SPSR _SFR_IO8(0x2D) -#define SPI2X 0 -#define WCOL 6 -#define SPIF 7 - -#define SPDR _SFR_IO8(0x2E) - -/* Reserved [0x2F] */ - -#define ACSR _SFR_IO8(0x30) -#define ACIS0 0 -#define ACIS1 1 -#define ACIC 2 -#define ACIE 3 -#define ACI 4 -#define ACO 5 -#define ACBG 6 -#define ACD 7 - -#define OCDR _SFR_IO8(0x31) -#define OCDR7 7 -#define OCDR6 6 -#define OCDR5 5 -#define OCDR4 4 -#define OCDR3 3 -#define OCDR2 2 -#define OCDR1 1 -#define OCDR0 0 - -/* Reserved [0x32] */ - -#define SMCR _SFR_IO8(0x33) -#define SE 0 -#define SM0 1 -#define SM1 2 -#define SM2 3 - -#define MCUSR _SFR_IO8(0x34) -#define JTRF 4 -#define PORF 0 -#define EXTRF 1 -#define BORF 2 -#define WDRF 3 - -#define MCUCR _SFR_IO8(0x35) -#define JTD 7 -#define IVCE 0 -#define IVSEL 1 -#define PUD 4 -#define BODSE 5 -#define BODS 6 - -/* Reserved [0x36] */ - -#define SPMCSR _SFR_IO8(0x37) -#define SPMEN 0 -#define PGERS 1 -#define PGWRT 2 -#define BLBSET 3 -#define RWWSRE 4 -#define RWWSB 6 -#define SPMIE 7 - -/* Reserved [0x38..0x3C] */ - -/* SP [0x3D..0x3E] */ - -/* SREG [0x3F] */ - -#define WDTCR _SFR_MEM8(0x60) -#define WDP0 0 -#define WDP1 1 -#define WDP2 2 -#define WDE 3 -#define WDCE 4 - -#define CLKPR _SFR_MEM8(0x61) -#define CLKPS0 0 -#define CLKPS1 1 -#define CLKPS2 2 -#define CLKPS3 3 -#define CLKPCE 7 - -/* Reserved [0x62..0x63] */ - -#define PRR _SFR_MEM8(0x64) -#define PRADC 0 -#define PRUSART0 1 -#define PRSPI 2 -#define PRTIM1 3 -#define PRLCD 4 - -#define __AVR_HAVE_PRR ((1< instead of this file." -#endif - -#ifndef _AVR_IOXXX_H_ -# define _AVR_IOXXX_H_ "iom329p.h" -#else -# error "Attempt to include more than one file." -#endif - -/* Registers and associated bit numbers */ - -#define PINA _SFR_IO8(0x00) -#define PINA7 7 -#define PINA6 6 -#define PINA5 5 -#define PINA4 4 -#define PINA3 3 -#define PINA2 2 -#define PINA1 1 -#define PINA0 0 - -#define DDRA _SFR_IO8(0x01) -#define DDRA7 7 -// Inserted "DDA7" from "DDRA7" due to compatibility -#define DDA7 7 -#define DDRA6 6 -// Inserted "DDA6" from "DDRA6" due to compatibility -#define DDA6 6 -#define DDRA5 5 -// Inserted "DDA5" from "DDRA5" due to compatibility -#define DDA5 5 -#define DDRA4 4 -// Inserted "DDA4" from "DDRA4" due to compatibility -#define DDA4 4 -#define DDRA3 3 -// Inserted "DDA3" from "DDRA3" due to compatibility -#define DDA3 3 -#define DDRA2 2 -// Inserted "DDA2" from "DDRA2" due to compatibility -#define DDA2 2 -#define DDRA1 1 -// Inserted "DDA1" from "DDRA1" due to compatibility -#define DDA1 1 -#define DDRA0 0 -// Inserted "DDA0" from "DDRA0" due to compatibility -#define DDA0 0 - -#define PORTA _SFR_IO8(0x02) -#define PORTA7 7 -#define PORTA6 6 -#define PORTA5 5 -#define PORTA4 4 -#define PORTA3 3 -#define PORTA2 2 -#define PORTA1 1 -#define PORTA0 0 - -#define PINB _SFR_IO8(0x03) -#define PINB7 7 -#define PINB6 6 -#define PINB5 5 -#define PINB4 4 -#define PINB3 3 -#define PINB2 2 -#define PINB1 1 -#define PINB0 0 - -#define DDRB _SFR_IO8(0x04) -#define DDRB7 7 -// Inserted "DDB7" from "DDRB7" due to compatibility -#define DDB7 7 -#define DDRB6 6 -// Inserted "DDB6" from "DDRB6" due to compatibility -#define DDB6 6 -#define DDRB5 5 -// Inserted "DDB5" from "DDRB5" due to compatibility -#define DDB5 5 -#define DDRB4 4 -// Inserted "DDB4" from "DDRB4" due to compatibility -#define DDB4 4 -#define DDRB3 3 -// Inserted "DDB3" from "DDRB3" due to compatibility -#define DDB3 3 -#define DDRB2 2 -// Inserted "DDB2" from "DDRB2" due to compatibility -#define DDB2 2 -#define DDRB1 1 -// Inserted "DDB1" from "DDRB1" due to compatibility -#define DDB1 1 -#define DDRB0 0 -// Inserted "DDB0" from "DDRB0" due to compatibility -#define DDB0 0 - -#define PORTB _SFR_IO8(0x05) -#define PORTB7 7 -#define PORTB6 6 -#define PORTB5 5 -#define PORTB4 4 -#define PORTB3 3 -#define PORTB2 2 -#define PORTB1 1 -#define PORTB0 0 - -#define PINC _SFR_IO8(0x06) -#define PINC7 7 -#define PINC6 6 -#define PINC5 5 -#define PINC4 4 -#define PINC3 3 -#define PINC2 2 -#define PINC1 1 -#define PINC0 0 - -#define DDRC _SFR_IO8(0x07) -#define DDRC7 7 -// Inserted "DDC7" from "DDRC7" due to compatibility -#define DDC7 7 -#define DDRC6 6 -// Inserted "DDC6" from "DDRC6" due to compatibility -#define DDC6 6 -#define DDRC5 5 -// Inserted "DDC5" from "DDRC5" due to compatibility -#define DDC5 5 -#define DDRC4 4 -// Inserted "DDC4" from "DDRC4" due to compatibility -#define DDC4 4 -#define DDRC3 3 -// Inserted "DDC3" from "DDRC3" due to compatibility -#define DDC3 3 -#define DDRC2 2 -// Inserted "DDC2" from "DDRC2" due to compatibility -#define DDC2 2 -#define DDRC1 1 -// Inserted "DDC1" from "DDRC1" due to compatibility -#define DDC1 1 -#define DDRC0 0 -// Inserted "DDC0" from "DDRC0" due to compatibility -#define DDC0 0 - -#define PORTC _SFR_IO8(0x08) -#define PORTC7 7 -#define PORTC6 6 -#define PORTC5 5 -#define PORTC4 4 -#define PORTC3 3 -#define PORTC2 2 -#define PORTC1 1 -#define PORTC0 0 - -#define PIND _SFR_IO8(0x09) -#define PIND7 7 -#define PIND6 6 -#define PIND5 5 -#define PIND4 4 -#define PIND3 3 -#define PIND2 2 -#define PIND1 1 -#define PIND0 0 - -#define DDRD _SFR_IO8(0x0A) -#define DDRD7 7 -// Inserted "DDD7" from "DDRD7" due to compatibility -#define DDD7 7 -#define DDRD6 6 -// Inserted "DDD6" from "DDRD6" due to compatibility -#define DDD6 6 -#define DDRD5 5 -// Inserted "DDD5" from "DDRD5" due to compatibility -#define DDD5 5 -#define DDRD4 4 -// Inserted "DDD4" from "DDRD4" due to compatibility -#define DDD4 4 -#define DDRD3 3 -// Inserted "DDD3" from "DDRD3" due to compatibility -#define DDD3 3 -#define DDRD2 2 -// Inserted "DDD2" from "DDRD2" due to compatibility -#define DDD2 2 -#define DDRD1 1 -// Inserted "DDD1" from "DDRD1" due to compatibility -#define DDD1 1 -#define DDRD0 0 -// Inserted "DDD0" from "DDRD0" due to compatibility -#define DDD0 0 - -#define PORTD _SFR_IO8(0x0B) -#define PORTD7 7 -#define PORTD6 6 -#define PORTD5 5 -#define PORTD4 4 -#define PORTD3 3 -#define PORTD2 2 -#define PORTD1 1 -#define PORTD0 0 - -#define PINE _SFR_IO8(0x0C) -#define PINE7 7 -#define PINE6 6 -#define PINE5 5 -#define PINE4 4 -#define PINE3 3 -#define PINE2 2 -#define PINE1 1 -#define PINE0 0 - -#define DDRE _SFR_IO8(0x0D) -#define DDRE7 7 -// Inserted "DDE7" from "DDRE7" due to compatibility -#define DDE7 7 -#define DDRE6 6 -// Inserted "DDE6" from "DDRE6" due to compatibility -#define DDE6 6 -#define DDRE5 5 -// Inserted "DDE5" from "DDRE5" due to compatibility -#define DDE5 5 -#define DDRE4 4 -// Inserted "DDE4" from "DDRE4" due to compatibility -#define DDE4 4 -#define DDRE3 3 -// Inserted "DDE3" from "DDRE3" due to compatibility -#define DDE3 3 -#define DDRE2 2 -// Inserted "DDE2" from "DDRE2" due to compatibility -#define DDE2 2 -#define DDRE1 1 -// Inserted "DDE1" from "DDRE1" due to compatibility -#define DDE1 1 -#define DDRE0 0 -// Inserted "DDE0" from "DDRE0" due to compatibility -#define DDE0 0 - -#define PORTE _SFR_IO8(0x0E) -#define PORTE7 7 -#define PORTE6 6 -#define PORTE5 5 -#define PORTE4 4 -#define PORTE3 3 -#define PORTE2 2 -#define PORTE1 1 -#define PORTE0 0 - -#define PINF _SFR_IO8(0x0F) -#define PINF7 7 -#define PINF6 6 -#define PINF5 5 -#define PINF4 4 -#define PINF3 3 -#define PINF2 2 -#define PINF1 1 -#define PINF0 0 - -#define DDRF _SFR_IO8(0x10) -#define DDRF7 7 -// Inserted "DDF7" from "DDRF7" due to compatibility -#define DDF7 7 -#define DDRF6 6 -// Inserted "DDF6" from "DDRF6" due to compatibility -#define DDF6 6 -#define DDRF5 5 -// Inserted "DDF5" from "DDRF5" due to compatibility -#define DDF5 5 -#define DDRF4 4 -// Inserted "DDF4" from "DDRF4" due to compatibility -#define DDF4 4 -#define DDRF3 3 -// Inserted "DDF3" from "DDRF3" due to compatibility -#define DDF3 3 -#define DDRF2 2 -// Inserted "DDF2" from "DDRF2" due to compatibility -#define DDF2 2 -#define DDRF1 1 -// Inserted "DDF1" from "DDRF1" due to compatibility -#define DDF1 1 -#define DDRF0 0 -// Inserted "DDF0" from "DDRF0" due to compatibility -#define DDF0 0 - -#define PORTF _SFR_IO8(0x11) -#define PORTF7 7 -#define PORTF6 6 -#define PORTF5 5 -#define PORTF4 4 -#define PORTF3 3 -#define PORTF2 2 -#define PORTF1 1 -#define PORTF0 0 - -#define PING _SFR_IO8(0x12) -#define PING5 5 -#define PING4 4 -#define PING3 3 -#define PING2 2 -#define PING1 1 -#define PING0 0 - -#define DDRG _SFR_IO8(0x13) -#define DDRG4 4 -// Inserted "DDG4" from "DDRG4" due to compatibility -#define DDG4 4 -#define DDRG3 3 -// Inserted "DDG3" from "DDRG3" due to compatibility -#define DDG3 3 -#define DDRG2 2 -// Inserted "DDG2" from "DDRG2" due to compatibility -#define DDG2 2 -#define DDRG1 1 -// Inserted "DDG1" from "DDRG1" due to compatibility -#define DDG1 1 -#define DDRG0 0 -// Inserted "DDG0" from "DDRG0" due to compatibility -#define DDG0 0 - -#define PORTG _SFR_IO8(0x14) -#define PORTG4 4 -#define PORTG3 3 -#define PORTG2 2 -#define PORTG1 1 -#define PORTG0 0 - -#define TIFR0 _SFR_IO8(0x15) -#define TOV0 0 -#define OCF0A 1 - -#define TIFR1 _SFR_IO8(0x16) -#define TOV1 0 -#define OCF1A 1 -#define OCF1B 2 -#define ICF1 5 - -#define TIFR2 _SFR_IO8(0x17) -#define TOV2 0 -#define OCF2A 1 - -/* Reserved [0x18..0x1B] */ - -#define EIFR _SFR_IO8(0x1C) -#define INTF0 0 -#define PCIF0 4 -#define PCIF1 5 -#define PCIF2 6 -#define PCIF3 7 - -#define EIMSK _SFR_IO8(0x1D) -#define INT0 0 -#define PCIE0 4 -#define PCIE1 5 -#define PCIE2 6 -#define PCIE3 7 - -#define GPIOR0 _SFR_IO8(0x1E) - -#define EECR _SFR_IO8(0x1F) -#define EERE 0 -#define EEWE 1 -#define EEMWE 2 -#define EERIE 3 - -#define EEDR _SFR_IO8(0x20) - -/* Combine EEARL and EEARH */ -#define EEAR _SFR_IO16(0x21) - -#define EEARL _SFR_IO8(0x21) -#define EEARH _SFR_IO8(0x22) - -#define GTCCR _SFR_IO8(0x23) -#define PSR10 0 -#define TSM 7 -#define PSR2 1 - -#define TCCR0A _SFR_IO8(0x24) -#define CS00 0 -#define CS01 1 -#define CS02 2 -#define WGM01 3 -#define COM0A0 4 -#define COM0A1 5 -#define WGM00 6 -#define FOC0A 7 - -/* Reserved [0x25] */ - -#define TCNT0 _SFR_IO8(0x26) - -#define OCR0A _SFR_IO8(0x27) - -/* Reserved [0x28..0x29] */ - -#define GPIOR1 _SFR_IO8(0x2A) - -#define GPIOR2 _SFR_IO8(0x2B) - -#define SPCR _SFR_IO8(0x2C) -#define SPR0 0 -#define SPR1 1 -#define CPHA 2 -#define CPOL 3 -#define MSTR 4 -#define DORD 5 -#define SPE 6 -#define SPIE 7 - -#define SPSR _SFR_IO8(0x2D) -#define SPI2X 0 -#define WCOL 6 -#define SPIF 7 - -#define SPDR _SFR_IO8(0x2E) - -/* Reserved [0x2F] */ - -#define ACSR _SFR_IO8(0x30) -#define ACIS0 0 -#define ACIS1 1 -#define ACIC 2 -#define ACIE 3 -#define ACI 4 -#define ACO 5 -#define ACBG 6 -#define ACD 7 - -#define OCDR _SFR_IO8(0x31) -#define OCDR7 7 -#define OCDR6 6 -#define OCDR5 5 -#define OCDR4 4 -#define OCDR3 3 -#define OCDR2 2 -#define OCDR1 1 -#define OCDR0 0 - -/* Reserved [0x32] */ - -#define SMCR _SFR_IO8(0x33) -#define SE 0 -#define SM0 1 -#define SM1 2 -#define SM2 3 - -#define MCUSR _SFR_IO8(0x34) -#define JTRF 4 -#define PORF 0 -#define EXTRF 1 -#define BORF 2 -#define WDRF 3 - -#define MCUCR _SFR_IO8(0x35) -#define JTD 7 -#define IVCE 0 -#define IVSEL 1 -#define PUD 4 -#define BODSE 5 -#define BODS 6 - -/* Reserved [0x36] */ - -#define SPMCSR _SFR_IO8(0x37) -#define SPMEN 0 -#define PGERS 1 -#define PGWRT 2 -#define BLBSET 3 -#define RWWSRE 4 -#define RWWSB 6 -#define SPMIE 7 - -/* Reserved [0x38..0x3C] */ - -/* SP [0x3D..0x3E] */ - -/* SREG [0x3F] */ - -#define WDTCR _SFR_MEM8(0x60) -#define WDP0 0 -#define WDP1 1 -#define WDP2 2 -#define WDE 3 -#define WDCE 4 - -#define CLKPR _SFR_MEM8(0x61) -#define CLKPS0 0 -#define CLKPS1 1 -#define CLKPS2 2 -#define CLKPS3 3 -#define CLKPCE 7 - -/* Reserved [0x62..0x63] */ - -#define PRR _SFR_MEM8(0x64) -#define PRADC 0 -#define PRUSART0 1 -#define PRSPI 2 -#define PRTIM1 3 -#define PRLCD 4 - -#define __AVR_HAVE_PRR ((1< instead of this file." -#endif - -#ifndef _AVR_IOXXX_H_ -# define _AVR_IOXXX_H_ "iom32a.h" -#else -# error "Attempt to include more than one file." -#endif - -/* Registers and associated bit numbers */ - -#define TWBR _SFR_IO8(0x00) - -#define TWSR _SFR_IO8(0x01) -#define TWPS0 0 -#define TWPS1 1 -#define TWS3 3 -#define TWS4 4 -#define TWS5 5 -#define TWS6 6 -#define TWS7 7 - -#define TWAR _SFR_IO8(0x02) - -#define TWDR _SFR_IO8(0x03) - -/* Combine ADCL and ADCH */ -#ifndef __ASSEMBLER__ -#define ADC _SFR_IO16(0x04) -#endif -#define ADCW _SFR_IO16(0x04) - -#define ADCL _SFR_IO8(0x04) -#define ADCH _SFR_IO8(0x05) - -#define ADCSRA _SFR_IO8(0x06) -#define ADPS0 0 -#define ADPS1 1 -#define ADPS2 2 -#define ADIE 3 -#define ADIF 4 -#define ADATE 5 -#define ADSC 6 -#define ADEN 7 - -#define ADMUX _SFR_IO8(0x07) -#define MUX0 0 -#define MUX1 1 -#define MUX2 2 -#define MUX3 3 -#define MUX4 4 -#define ADLAR 5 -#define REFS0 6 -#define REFS1 7 - -#define ACSR _SFR_IO8(0x08) -#define ACIS0 0 -#define ACIS1 1 -#define ACIC 2 -#define ACIE 3 -#define ACI 4 -#define ACO 5 -#define ACBG 6 -#define ACD 7 - -#define UBRRL _SFR_IO8(0x09) - -#define UCSRB _SFR_IO8(0x0A) -#define TXB8 0 -#define RXB8 1 -#define UCSZ2 2 -#define TXEN 3 -#define RXEN 4 -#define UDRIE 5 -#define TXCIE 6 -#define RXCIE 7 - -#define UCSRA _SFR_IO8(0x0B) -#define MPCM 0 -#define U2X 1 -#define UPE 2 -#define DOR 3 -#define FE 4 -#define UDRE 5 -#define TXC 6 -#define RXC 7 - -#define UDR _SFR_IO8(0x0C) - -#define SPCR _SFR_IO8(0x0D) -#define SPR0 0 -#define SPR1 1 -#define CPHA 2 -#define CPOL 3 -#define MSTR 4 -#define DORD 5 -#define SPE 6 -#define SPIE 7 - -#define SPSR _SFR_IO8(0x0E) -#define SPI2X 0 -#define WCOL 6 -#define SPIF 7 - -#define SPDR _SFR_IO8(0x0F) - -#define PIND _SFR_IO8(0x10) -#define PIND7 7 -#define PIND6 6 -#define PIND5 5 -#define PIND4 4 -#define PIND3 3 -#define PIND2 2 -#define PIND1 1 -#define PIND0 0 - -#define DDRD _SFR_IO8(0x11) -#define DDRD7 7 -// Inserted "DDD7" from "DDRD7" due to compatibility -#define DDD7 7 -#define DDRD6 6 -// Inserted "DDD6" from "DDRD6" due to compatibility -#define DDD6 6 -#define DDRD5 5 -// Inserted "DDD5" from "DDRD5" due to compatibility -#define DDD5 5 -#define DDRD4 4 -// Inserted "DDD4" from "DDRD4" due to compatibility -#define DDD4 4 -#define DDRD3 3 -// Inserted "DDD3" from "DDRD3" due to compatibility -#define DDD3 3 -#define DDRD2 2 -// Inserted "DDD2" from "DDRD2" due to compatibility -#define DDD2 2 -#define DDRD1 1 -// Inserted "DDD1" from "DDRD1" due to compatibility -#define DDD1 1 -#define DDRD0 0 -// Inserted "DDD0" from "DDRD0" due to compatibility -#define DDD0 0 - -#define PORTD _SFR_IO8(0x12) -#define PORTD7 7 -#define PORTD6 6 -#define PORTD5 5 -#define PORTD4 4 -#define PORTD3 3 -#define PORTD2 2 -#define PORTD1 1 -#define PORTD0 0 - -#define PINC _SFR_IO8(0x13) -#define PINC7 7 -#define PINC6 6 -#define PINC5 5 -#define PINC4 4 -#define PINC3 3 -#define PINC2 2 -#define PINC1 1 -#define PINC0 0 - -#define DDRC _SFR_IO8(0x14) -#define DDRC7 7 -// Inserted "DDC7" from "DDRC7" due to compatibility -#define DDC7 7 -#define DDRC6 6 -// Inserted "DDC6" from "DDRC6" due to compatibility -#define DDC6 6 -#define DDRC5 5 -// Inserted "DDC5" from "DDRC5" due to compatibility -#define DDC5 5 -#define DDRC4 4 -// Inserted "DDC4" from "DDRC4" due to compatibility -#define DDC4 4 -#define DDRC3 3 -// Inserted "DDC3" from "DDRC3" due to compatibility -#define DDC3 3 -#define DDRC2 2 -// Inserted "DDC2" from "DDRC2" due to compatibility -#define DDC2 2 -#define DDRC1 1 -// Inserted "DDC1" from "DDRC1" due to compatibility -#define DDC1 1 -#define DDRC0 0 -// Inserted "DDC0" from "DDRC0" due to compatibility -#define DDC0 0 - -#define PORTC _SFR_IO8(0x15) -#define PORTC7 7 -#define PORTC6 6 -#define PORTC5 5 -#define PORTC4 4 -#define PORTC3 3 -#define PORTC2 2 -#define PORTC1 1 -#define PORTC0 0 - -#define PINB _SFR_IO8(0x16) -#define PINB7 7 -#define PINB6 6 -#define PINB5 5 -#define PINB4 4 -#define PINB3 3 -#define PINB2 2 -#define PINB1 1 -#define PINB0 0 - -#define DDRB _SFR_IO8(0x17) -#define DDRB7 7 -// Inserted "DDB7" from "DDRB7" due to compatibility -#define DDB7 7 -#define DDRB6 6 -// Inserted "DDB6" from "DDRB6" due to compatibility -#define DDB6 6 -#define DDRB5 5 -// Inserted "DDB5" from "DDRB5" due to compatibility -#define DDB5 5 -#define DDRB4 4 -// Inserted "DDB4" from "DDRB4" due to compatibility -#define DDB4 4 -#define DDRB3 3 -// Inserted "DDB3" from "DDRB3" due to compatibility -#define DDB3 3 -#define DDRB2 2 -// Inserted "DDB2" from "DDRB2" due to compatibility -#define DDB2 2 -#define DDRB1 1 -// Inserted "DDB1" from "DDRB1" due to compatibility -#define DDB1 1 -#define DDRB0 0 -// Inserted "DDB0" from "DDRB0" due to compatibility -#define DDB0 0 - -#define PORTB _SFR_IO8(0x18) -#define PORTB7 7 -#define PORTB6 6 -#define PORTB5 5 -#define PORTB4 4 -#define PORTB3 3 -#define PORTB2 2 -#define PORTB1 1 -#define PORTB0 0 - -#define PINA _SFR_IO8(0x19) -#define PINA7 7 -#define PINA6 6 -#define PINA5 5 -#define PINA4 4 -#define PINA3 3 -#define PINA2 2 -#define PINA1 1 -#define PINA0 0 - -#define DDRA _SFR_IO8(0x1A) -#define DDRA7 7 -// Inserted "DDA7" from "DDRA7" due to compatibility -#define DDA7 7 -#define DDRA6 6 -// Inserted "DDA6" from "DDRA6" due to compatibility -#define DDA6 6 -#define DDRA5 5 -// Inserted "DDA5" from "DDRA5" due to compatibility -#define DDA5 5 -#define DDRA4 4 -// Inserted "DDA4" from "DDRA4" due to compatibility -#define DDA4 4 -#define DDRA3 3 -// Inserted "DDA3" from "DDRA3" due to compatibility -#define DDA3 3 -#define DDRA2 2 -// Inserted "DDA2" from "DDRA2" due to compatibility -#define DDA2 2 -#define DDRA1 1 -// Inserted "DDA1" from "DDRA1" due to compatibility -#define DDA1 1 -#define DDRA0 0 -// Inserted "DDA0" from "DDRA0" due to compatibility -#define DDA0 0 - -#define PORTA _SFR_IO8(0x1B) -#define PORTA7 7 -#define PORTA6 6 -#define PORTA5 5 -#define PORTA4 4 -#define PORTA3 3 -#define PORTA2 2 -#define PORTA1 1 -#define PORTA0 0 - -#define EECR _SFR_IO8(0x1C) -#define EERE 0 -#define EEWE 1 -#define EEMWE 2 -#define EERIE 3 - -#define EEDR _SFR_IO8(0x1D) - -/* Combine EEARL and EEARH */ -#define EEAR _SFR_IO16(0x1E) - -#define EEARL _SFR_IO8(0x1E) -#define EEARH _SFR_IO8(0x1F) - -#define UCSRC _SFR_IO8(0x20) -#define UCPOL 0 -#define UCSZ0 1 -#define UCSZ1 2 -#define USBS 3 -#define UPM0 4 -#define UPM1 5 -#define UMSEL 6 -#define URSEL 7 - -#define UBRRH _SFR_IO8(0x20) - -#define WDTCR _SFR_IO8(0x21) -#define WDP0 0 -#define WDP1 1 -#define WDP2 2 -#define WDE 3 -#define WDTOE 4 - -#define ASSR _SFR_IO8(0x22) -#define TCR2UB 0 -#define OCR2UB 1 -#define TCN2UB 2 -#define AS2 3 - -#define OCR2 _SFR_IO8(0x23) - -#define TCNT2 _SFR_IO8(0x24) - -#define TCCR2 _SFR_IO8(0x25) -#define CS20 0 -#define CS21 1 -#define CS22 2 -#define WGM21 3 -#define COM20 4 -#define COM21 5 -#define WGM20 6 -#define FOC2 7 - -/* Combine ICR1L and ICR1H */ -#define ICR1 _SFR_IO16(0x26) - -#define ICR1L _SFR_IO8(0x26) -#define ICR1H _SFR_IO8(0x27) - -/* Combine OCR1BL and OCR1BH */ -#define OCR1B _SFR_IO16(0x28) - -#define OCR1BL _SFR_IO8(0x28) -#define OCR1BH _SFR_IO8(0x29) - -/* Combine OCR1AL and OCR1AH */ -#define OCR1A _SFR_IO16(0x2A) - -#define OCR1AL _SFR_IO8(0x2A) -#define OCR1AH _SFR_IO8(0x2B) - -/* Combine TCNT1L and TCNT1H */ -#define TCNT1 _SFR_IO16(0x2C) - -#define TCNT1L _SFR_IO8(0x2C) -#define TCNT1H _SFR_IO8(0x2D) - -#define TCCR1B _SFR_IO8(0x2E) -#define CS10 0 -#define CS11 1 -#define CS12 2 -#define WGM12 3 -#define WGM13 4 -#define ICES1 6 -#define ICNC1 7 - -#define TCCR1A _SFR_IO8(0x2F) -#define WGM10 0 -#define WGM11 1 -#define FOC1B 2 -#define FOC1A 3 -#define COM1B0 4 -#define COM1B1 5 -#define COM1A0 6 -#define COM1A1 7 - -#define SFIOR _SFR_IO8(0x30) -#define PSR2 0 -#define PSR10 0 -#define PUD 2 -#define ACME 3 -#define ADTS0 5 -#define ADTS1 6 -#define ADTS2 7 - -#define OSCCAL _SFR_IO8(0x31) -#define OSCCAL0 0 -#define OSCCAL1 1 -#define OSCCAL2 2 -#define OSCCAL3 3 -#define OSCCAL4 4 -#define OSCCAL5 5 -#define OSCCAL6 6 -#define OSCCAL7 7 - -#define TCNT0 _SFR_IO8(0x32) - -#define TCCR0 _SFR_IO8(0x33) -#define CS00 0 -#define CS01 1 -#define CS02 2 -#define WGM01 3 -#define COM00 4 -#define COM01 5 -#define WGM00 6 -#define FOC0 7 - -#define MCUCSR _SFR_IO8(0x34) -#define ISC2 6 -#define PORF 0 -#define EXTRF 1 -#define BORF 2 -#define WDRF 3 -#define JTRF 4 -#define JTD 7 - -#define MCUCR _SFR_IO8(0x35) -#define ISC00 0 -#define ISC01 1 -#define ISC10 2 -#define ISC11 3 -#define SM0 4 -#define SM1 5 -#define SM2 6 -#define SE 7 - -#define TWCR _SFR_IO8(0x36) -#define TWIE 0 -#define TWEN 2 -#define TWWC 3 -#define TWSTO 4 -#define TWSTA 5 -#define TWEA 6 -#define TWINT 7 - -#define SPMCR _SFR_IO8(0x37) -#define SPMEN 0 -#define PGERS 1 -#define PGWRT 2 -#define BLBSET 3 -#define RWWSRE 4 -#define RWWSB 6 -#define SPMIE 7 - -#define TIFR _SFR_IO8(0x38) -#define TOV0 0 -#define OCF0 1 -#define TOV2 6 -#define OCF2 7 -#define TOV1 2 -#define OCF1B 3 -#define OCF1A 4 -#define ICF1 5 - -#define TIMSK _SFR_IO8(0x39) -#define TOIE0 0 -#define OCIE0 1 -#define TOIE2 6 -#define OCIE2 7 -#define TOIE1 2 -#define OCIE1B 3 -#define OCIE1A 4 -#define TICIE1 5 - -#define GIFR _SFR_IO8(0x3A) -#define INTF2 5 -#define INTF0 6 -#define INTF1 7 - -#define GICR _SFR_IO8(0x3B) -#define IVCE 0 -#define IVSEL 1 -#define INT2 5 -#define INT0 6 -#define INT1 7 - -#define OCR0 _SFR_IO8(0x3C) - -/* SP [0x3D..0x3E] */ - -/* SREG [0x3F] */ - - - -/* Values and associated defines */ - - -#define SLEEP_MODE_IDLE (0x00<<4) -#define SLEEP_MODE_ADC (0x01<<4) -#define SLEEP_MODE_PWR_DOWN (0x02<<4) -#define SLEEP_MODE_PWR_SAVE (0x03<<4) -#define SLEEP_MODE_STANDBY (0x06<<4) -#define SLEEP_MODE_EXT_STANDBY (0x07<<4) - -/* Interrupt vectors */ -/* Vector 0 is the reset vector */ -/* External Interrupt Request 0 */ -#define INT0_vect _VECTOR(1) -#define INT0_vect_num 1 - -/* External Interrupt Request 1 */ -#define INT1_vect _VECTOR(2) -#define INT1_vect_num 2 - -/* External Interrupt Request 2 */ -#define INT2_vect _VECTOR(3) -#define INT2_vect_num 3 - -/* Timer/Counter2 Compare Match */ -#define TIMER2_COMP_vect _VECTOR(4) -#define TIMER2_COMP_vect_num 4 - -/* Timer/Counter2 Overflow */ -#define TIMER2_OVF_vect _VECTOR(5) -#define TIMER2_OVF_vect_num 5 - -/* Timer/Counter1 Capture Event */ -#define TIMER1_CAPT_vect _VECTOR(6) -#define TIMER1_CAPT_vect_num 6 - -/* Timer/Counter1 Compare Match A */ -#define TIMER1_COMPA_vect _VECTOR(7) -#define TIMER1_COMPA_vect_num 7 - -/* Timer/Counter1 Compare Match B */ -#define TIMER1_COMPB_vect _VECTOR(8) -#define TIMER1_COMPB_vect_num 8 - -/* Timer/Counter1 Overflow */ -#define TIMER1_OVF_vect _VECTOR(9) -#define TIMER1_OVF_vect_num 9 - -/* Timer/Counter0 Compare Match */ -#define TIMER0_COMP_vect _VECTOR(10) -#define TIMER0_COMP_vect_num 10 - -/* Timer/Counter0 Overflow */ -#define TIMER0_OVF_vect _VECTOR(11) -#define TIMER0_OVF_vect_num 11 - -/* Serial Transfer Complete */ -#define SPI_STC_vect _VECTOR(12) -#define SPI_STC_vect_num 12 - -/* USART, Rx Complete */ -#define USART_RXC_vect _VECTOR(13) -#define USART_RXC_vect_num 13 - -/* USART Data Register Empty */ -#define USART_UDRE_vect _VECTOR(14) -#define USART_UDRE_vect_num 14 - -/* USART, Tx Complete */ -#define USART_TXC_vect _VECTOR(15) -#define USART_TXC_vect_num 15 - -/* ADC Conversion Complete */ -#define ADC_vect _VECTOR(16) -#define ADC_vect_num 16 - -/* EEPROM Ready */ -#define EE_RDY_vect _VECTOR(17) -#define EE_RDY_vect_num 17 - -/* Analog Comparator */ -#define ANA_COMP_vect _VECTOR(18) -#define ANA_COMP_vect_num 18 - -/* 2-wire Serial Interface */ -#define TWI_vect _VECTOR(19) -#define TWI_vect_num 19 - -/* Store Program Memory Ready */ -#define SPM_RDY_vect _VECTOR(20) -#define SPM_RDY_vect_num 20 - -#define _VECTORS_SIZE 84 - - -/* Constants */ - -#define SPM_PAGESIZE 128 -#define FLASHSTART 0x0000 -#define FLASHEND 0x7FFF -#define RAMSTART 0x0060 -#define RAMSIZE 2048 -#define RAMEND 0x085F -#define E2START 0 -#define E2SIZE 1024 -#define E2PAGESIZE 4 -#define E2END 0x03FF -#define XRAMEND RAMEND - - -/* Fuses */ - -#define FUSE_MEMORY_SIZE 2 - -/* Low Fuse Byte */ -#define FUSE_SUT_CKSEL0 (unsigned char)~_BV(0) -#define FUSE_SUT_CKSEL1 (unsigned char)~_BV(1) -#define FUSE_SUT_CKSEL2 (unsigned char)~_BV(2) -#define FUSE_SUT_CKSEL3 (unsigned char)~_BV(3) -#define FUSE_SUT_CKSEL4 (unsigned char)~_BV(4) -#define FUSE_SUT_CKSEL5 (unsigned char)~_BV(5) -#define FUSE_BODEN (unsigned char)~_BV(6) -#define FUSE_BODLEVEL (unsigned char)~_BV(7) -#define LFUSE_DEFAULT (FUSE_SUT_CKSEL1 & FUSE_SUT_CKSEL2 & FUSE_SUT_CKSEL3 & FUSE_SUT_CKSEL4) - - -/* High Fuse Byte */ -#define FUSE_BOOTRST (unsigned char)~_BV(0) -#define FUSE_BOOTSZ0 (unsigned char)~_BV(1) -#define FUSE_BOOTSZ1 (unsigned char)~_BV(2) -#define FUSE_EESAVE (unsigned char)~_BV(3) -#define FUSE_CKOPT (unsigned char)~_BV(4) -#define FUSE_SPIEN (unsigned char)~_BV(5) -#define FUSE_JTAGEN (unsigned char)~_BV(6) -#define FUSE_OCDEN (unsigned char)~_BV(7) -#define HFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_SPIEN & FUSE_JTAGEN) - - - -/* Lock Bits */ -#define __LOCK_BITS_EXIST -#define __BOOT_LOCK_BITS_0_EXIST -#define __BOOT_LOCK_BITS_1_EXIST - - -/* Signature */ -#define SIGNATURE_0 0x1E -#define SIGNATURE_1 0x95 -#define SIGNATURE_2 0x02 - - -#endif /* #ifdef _AVR_ATMEGA32A_H_INCLUDED */ - diff --git a/arduino/hardware/tools/avr/avr/include/avr/iom32c1.h b/arduino/hardware/tools/avr/avr/include/avr/iom32c1.h deleted file mode 100644 index e92cfe4..0000000 --- a/arduino/hardware/tools/avr/avr/include/avr/iom32c1.h +++ /dev/null @@ -1,1320 +0,0 @@ -/* Copyright (c) 2009 Atmel Corporation - All rights reserved. - - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - * Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - * Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in - the documentation and/or other materials provided with the - distribution. - - * Neither the name of the copyright holders nor the names of - contributors may be used to endorse or promote products derived - from this software without specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. */ - -/* $Id: iom32c1.h 2183 2010-09-21 05:37:46Z aboyapati $ */ - -/* avr/iom32c1.h - definitions for ATmega32C1 */ - -/* This file should only be included from , never directly. */ - -#ifndef _AVR_IO_H_ -# error "Include instead of this file." -#endif - -#ifndef _AVR_IOXXX_H_ -# define _AVR_IOXXX_H_ "iom32c1.h" -#else -# error "Attempt to include more than one file." -#endif - - -#ifndef _AVR_ATmega32C1_H_ -#define _AVR_ATmega32C1_H_ 1 - - -/* Registers and associated bit numbers. */ - -#define PINB _SFR_IO8(0x03) -#define PINB0 0 -#define PINB1 1 -#define PINB2 2 -#define PINB3 3 -#define PINB4 4 -#define PINB5 5 -#define PINB6 6 -#define PINB7 7 - -#define DDRB _SFR_IO8(0x04) -#define DDB0 0 -#define DDB1 1 -#define DDB2 2 -#define DDB3 3 -#define DDB4 4 -#define DDB5 5 -#define DDB6 6 -#define DDB7 7 - -#define PORTB _SFR_IO8(0x05) -#define PORTB0 0 -#define PORTB1 1 -#define PORTB2 2 -#define PORTB3 3 -#define PORTB4 4 -#define PORTB5 5 -#define PORTB6 6 -#define PORTB7 7 - -#define PINC _SFR_IO8(0x06) -#define PINC0 0 -#define PINC1 1 -#define PINC2 2 -#define PINC3 3 -#define PINC4 4 -#define PINC5 5 -#define PINC6 6 -#define PINC7 7 - -#define DDRC _SFR_IO8(0x07) -#define DDC0 0 -#define DDC1 1 -#define DDC2 2 -#define DDC3 3 -#define DDC4 4 -#define DDC5 5 -#define DDC6 6 -#define DDC7 7 - -#define PORTC _SFR_IO8(0x08) -#define PORTC0 0 -#define PORTC1 1 -#define PORTC2 2 -#define PORTC3 3 -#define PORTC4 4 -#define PORTC5 5 -#define PORTC6 6 -#define PORTC7 7 - -#define PIND _SFR_IO8(0x09) -#define PIND0 0 -#define PIND1 1 -#define PIND2 2 -#define PIND3 3 -#define PIND4 4 -#define PIND5 5 -#define PIND6 6 -#define PIND7 7 - -#define DDRD _SFR_IO8(0x0A) -#define DDD0 0 -#define DDD1 1 -#define DDD2 2 -#define DDD3 3 -#define DDD4 4 -#define DDD5 5 -#define DDD6 6 -#define DDD7 7 - -#define PORTD _SFR_IO8(0x0B) -#define PORTD0 0 -#define PORTD1 1 -#define PORTD2 2 -#define PORTD3 3 -#define PORTD4 4 -#define PORTD5 5 -#define PORTD6 6 -#define PORTD7 7 - -#define PINE _SFR_IO8(0x0C) -#define PINE0 0 -#define PINE1 1 -#define PINE2 2 - -#define DDRE _SFR_IO8(0x0D) -#define DDE0 0 -#define DDE1 1 -#define DDE2 2 - -#define PORTE _SFR_IO8(0x0E) -#define PORTE0 0 -#define PORTE1 1 -#define PORTE2 2 - -#define TIFR0 _SFR_IO8(0x15) -#define TOV0 0 -#define OCF0A 1 -#define OCF0B 2 - -#define TIFR1 _SFR_IO8(0x16) -#define TOV1 0 -#define OCF1A 1 -#define OCF1B 2 -#define ICF1 5 - -#define GPIOR1 _SFR_IO8(0x19) -#define GPIOR10 0 -#define GPIOR11 1 -#define GPIOR12 2 -#define GPIOR13 3 -#define GPIOR14 4 -#define GPIOR15 5 -#define GPIOR16 6 -#define GPIOR17 7 - -#define GPIOR2 _SFR_IO8(0x1A) -#define GPIOR20 0 -#define GPIOR21 1 -#define GPIOR22 2 -#define GPIOR23 3 -#define GPIOR24 4 -#define GPIOR25 5 -#define GPIOR26 6 -#define GPIOR27 7 - -#define PCIFR _SFR_IO8(0x1B) -#define PCIF0 0 -#define PCIF1 1 -#define PCIF2 2 -#define PCIF3 3 - -#define EIFR _SFR_IO8(0x1C) -#define INTF0 0 -#define INTF1 1 -#define INTF2 2 -#define INTF3 3 - -#define EIMSK _SFR_IO8(0x1D) -#define INT0 0 -#define INT1 1 -#define INT2 2 -#define INT3 3 - -#define GPIOR0 _SFR_IO8(0x1E) -#define GPIOR00 0 -#define GPIOR01 1 -#define GPIOR02 2 -#define GPIOR03 3 -#define GPIOR04 4 -#define GPIOR05 5 -#define GPIOR06 6 -#define GPIOR07 7 - -#define EECR _SFR_IO8(0x1F) -#define EERE 0 -#define EEWE 1 -#define EEMWE 2 -#define EERIE 3 -#define EEPM0 4 -#define EEPM1 5 - -#define EEDR _SFR_IO8(0x20) -#define EEDR0 0 -#define EEDR1 1 -#define EEDR2 2 -#define EEDR3 3 -#define EEDR4 4 -#define EEDR5 5 -#define EEDR6 6 -#define EEDR7 7 - -#define EEAR _SFR_IO16(0x21) - -#define EEARL _SFR_IO8(0x21) -#define EEAR0 0 -#define EEAR1 1 -#define EEAR2 2 -#define EEAR3 3 -#define EEAR4 4 -#define EEAR5 5 -#define EEAR6 6 -#define EEAR7 7 - -#define EEARH _SFR_IO8(0x22) -#define EEAR8 0 -#define EEAR9 1 - -#define GTCCR _SFR_IO8(0x23) -#define PSR10 0 -#define PSRSYNC 0 -#define ICPSEL1 6 -#define TSM 7 - -#define TCCR0A _SFR_IO8(0x24) -#define WGM00 0 -#define WGM01 1 -#define COM0B0 4 -#define COM0B1 5 -#define COM0A0 6 -#define COM0A1 7 - -#define TCCR0B _SFR_IO8(0x25) -#define CS00 0 -#define CS01 1 -#define CS02 2 -#define WGM02 3 -#define FOC0B 6 -#define FOC0A 7 - -#define TCNT0 _SFR_IO8(0x26) -#define TCNT0_0 0 -#define TCNT0_1 1 -#define TCNT0_2 2 -#define TCNT0_3 3 -#define TCNT0_4 4 -#define TCNT0_5 5 -#define TCNT0_6 6 -#define TCNT0_7 7 - -#define OCR0A _SFR_IO8(0x27) -#define OCR0A_0 0 -#define OCR0A_1 1 -#define OCR0A_2 2 -#define OCR0A_3 3 -#define OCR0A_4 4 -#define OCR0A_5 5 -#define OCR0A_6 6 -#define OCR0A_7 7 - -#define OCR0B _SFR_IO8(0x28) -#define OCR0B_0 0 -#define OCR0B_1 1 -#define OCR0B_2 2 -#define OCR0B_3 3 -#define OCR0B_4 4 -#define OCR0B_5 5 -#define OCR0B_6 6 -#define OCR0B_7 7 - -#define PLLCSR _SFR_IO8(0x29) -#define PLOCK 0 -#define PLLE 1 -#define PLLF 2 - -#define SPCR _SFR_IO8(0x2C) -#define SPR0 0 -#define SPR1 1 -#define CPHA 2 -#define CPOL 3 -#define MSTR 4 -#define DORD 5 -#define SPE 6 -#define SPIE 7 - -#define SPSR _SFR_IO8(0x2D) -#define SPI2X 0 -#define WCOL 6 -#define SPIF 7 - -#define SPDR _SFR_IO8(0x2E) -#define SPDR0 0 -#define SPDR1 1 -#define SPDR2 2 -#define SPDR3 3 -#define SPDR4 4 -#define SPDR5 5 -#define SPDR6 6 -#define SPDR7 7 - -#define ACSR _SFR_IO8(0x30) -#define AC0O 0 -#define AC1O 1 -#define AC2O 2 -#define AC3O 3 -#define AC0IF 4 -#define AC1IF 5 -#define AC2IF 6 -#define AC3IF 7 - -#define DWDR _SFR_IO8(0x31) - -#define SMCR _SFR_IO8(0x33) -#define SE 0 -#define SM0 1 -#define SM1 2 -#define SM2 3 - -#define MCUSR _SFR_IO8(0x34) -#define PORF 0 -#define EXTRF 1 -#define BORF 2 -#define WDRF 3 - -#define MCUCR _SFR_IO8(0x35) -#define IVCE 0 -#define IVSEL 1 -#define PUD 4 -#define SPIPS 7 - -#define SPMCSR _SFR_IO8(0x37) -#define SPMEN 0 -#define PGERS 1 -#define PGWRT 2 -#define BLBSET 3 -#define RWWSRE 4 -#define SIGRD 5 -#define RWWSB 6 -#define SPMIE 7 - -#define WDTCSR _SFR_MEM8(0x60) -#define WDP0 0 -#define WDP1 1 -#define WDP2 2 -#define WDE 3 -#define WDCE 4 -#define WDP3 5 -#define WDIE 6 -#define WDIF 7 - -#define CLKPR _SFR_MEM8(0x61) -#define CLKPS0 0 -#define CLKPS1 1 -#define CLKPS2 2 -#define CLKPS3 3 -#define CLKPCE 7 - -#define PRR _SFR_MEM8(0x64) -#define PRADC 0 -#define PRLIN 1 -#define PRSPI 2 -#define PRTIM0 3 -#define PRTIM1 4 -#define PRPSC 5 -#define PRCAN 6 - -#define __AVR_HAVE_PRR ((1<, never directly. */ - -#ifndef _AVR_IO_H_ -# error "Include instead of this file." -#endif - -#ifndef _AVR_IOXXX_H_ -# define _AVR_IOXXX_H_ "iom32hvb.h" -#else -# error "Attempt to include more than one file." -#endif - - -#ifndef _AVR_ATmega32HVB_H_ -#define _AVR_ATmega32HVB_H_ 1 - - -/* Registers and associated bit numbers. */ - -#define PINA _SFR_IO8(0x00) -#define PINA0 0 -#define PINA1 1 -#define PINA2 2 -#define PINA3 3 - -#define DDRA _SFR_IO8(0x01) -#define DDA0 0 -#define DDA1 1 -#define DDA2 2 -#define DDA3 3 - -#define PORTA _SFR_IO8(0x02) -#define PORTA0 0 -#define PORTA1 1 -#define PORTA2 2 -#define PORTA3 3 - -#define PINB _SFR_IO8(0x03) -#define PINB0 0 -#define PINB1 1 -#define PINB2 2 -#define PINB3 3 -#define PINB4 4 -#define PINB5 5 -#define PINB6 6 -#define PINB7 7 - -#define DDRB _SFR_IO8(0x04) -#define DDB0 0 -#define DDB1 1 -#define DDB2 2 -#define DDB3 3 -#define DDB4 4 -#define DDB5 5 -#define DDB6 6 -#define DDB7 7 - -#define PORTB _SFR_IO8(0x05) -#define PORTB0 0 -#define PORTB1 1 -#define PORTB2 2 -#define PORTB3 3 -#define PORTB4 4 -#define PORTB5 5 -#define PORTB6 6 -#define PORTB7 7 - -#define PINC _SFR_IO8(0x06) -#define PINC0 0 -#define PINC1 1 -#define PINC2 2 -#define PINC3 3 -#define PINC4 4 - -#define PORTC _SFR_IO8(0x08) -#define PORTC0 0 -#define PORTC1 1 -#define PORTC2 2 -#define PORTC3 3 -#define PORTC4 4 -#define PORTC5 5 - -#define TIFR0 _SFR_IO8(0x15) -#define TOV0 0 -#define OCF0A 1 -#define OCF0B 2 -#define ICF0 3 - -#define TIFR1 _SFR_IO8(0x16) -#define TOV1 0 -#define OCF1A 1 -#define OCF1B 2 -#define ICF1 3 - -#define OSICSR _SFR_IO8(0x17) -#define OSIEN 0 -#define OSIST 1 -#define OSISEL0 4 - -#define PCIFR _SFR_IO8(0x1B) -#define PCIF0 0 -#define PCIF1 1 - -#define EIFR _SFR_IO8(0x1C) -#define INTF0 0 -#define INTF1 1 -#define INTF2 2 -#define INTF3 3 - -#define EIMSK _SFR_IO8(0x1D) -#define INT0 0 -#define INT1 1 -#define INT2 2 -#define INT3 3 - -#define GPIOR0 _SFR_IO8(0x1E) -#define GPIOR00 0 -#define GPIOR01 1 -#define GPIOR02 2 -#define GPIOR03 3 -#define GPIOR04 4 -#define GPIOR05 5 -#define GPIOR06 6 -#define GPIOR07 7 - -#define EECR _SFR_IO8(0x1F) -#define EERE 0 -#define EEPE 1 -#define EEMPE 2 -#define EERIE 3 -#define EEPM0 4 -#define EEPM1 5 - -#define EEDR _SFR_IO8(0x20) -#define EEDR0 0 -#define EEDR1 1 -#define EEDR2 2 -#define EEDR3 3 -#define EEDR4 4 -#define EEDR5 5 -#define EEDR6 6 -#define EEDR7 7 - -#define EEAR _SFR_IO16(0x21) - -#define EEARL _SFR_IO8(0x21) -#define EEAR0 0 -#define EEAR1 1 -#define EEAR2 2 -#define EEAR3 3 -#define EEAR4 4 -#define EEAR5 5 -#define EEAR6 6 -#define EEAR7 7 - -#define EEARH _SFR_IO8(0x22) -#define EEAR8 0 -#define EEAR9 1 - -#define GTCCR _SFR_IO8(0x23) -#define PSRSYNC 0 -#define TSM 7 - -#define TCCR0A _SFR_IO8(0x24) -#define WGM00 0 -#define ICS0 3 -#define ICES0 4 -#define ICNC0 5 -#define ICEN0 6 -#define TCW0 7 - -#define TCCR0B _SFR_IO8(0x25) -#define CS00 0 -#define CS01 1 -#define CS02 2 - -#define TCNT0 _SFR_IO16(0x26) - -#define TCNT0L _SFR_IO8(0x26) -#define TCNT0L0 0 -#define TCNT0L1 1 -#define TCNT0L2 2 -#define TCNT0L3 3 -#define TCNT0L4 4 -#define TCNT0L5 5 -#define TCNT0L6 6 -#define TCNT0L7 7 - -#define TCNT0H _SFR_IO8(0x27) -#define TCNT0H0 0 -#define TCNT0H1 1 -#define TCNT0H2 2 -#define TCNT0H3 3 -#define TCNT0H4 4 -#define TCNT0H5 5 -#define TCNT0H6 6 -#define TCNT0H7 7 - -#define OCR0A _SFR_IO8(0x28) -#define OCR0A0 0 -#define OCR0A1 1 -#define OCR0A2 2 -#define OCR0A3 3 -#define OCR0A4 4 -#define OCR0A5 5 -#define OCR0A6 6 -#define OCR0A7 7 - -#define OCR0B _SFR_IO8(0x29) -#define OCR0B0 0 -#define OCR0B1 1 -#define OCR0B2 2 -#define OCR0B3 3 -#define OCR0B4 4 -#define OCR0B5 5 -#define OCR0B6 6 -#define OCR0B7 7 - -#define GPIOR1 _SFR_IO8(0x2A) -#define GPIOR10 0 -#define GPIOR11 1 -#define GPIOR12 2 -#define GPIOR13 3 -#define GPIOR14 4 -#define GPIOR15 5 -#define GPIOR16 6 -#define GPIOR17 7 - -#define GPIOR2 _SFR_IO8(0x2B) -#define GPIOR20 0 -#define GPIOR21 1 -#define GPIOR22 2 -#define GPIOR23 3 -#define GPIOR24 4 -#define GPIOR25 5 -#define GPIOR26 6 -#define GPIOR27 7 - -#define SPCR _SFR_IO8(0x2C) -#define SPR0 0 -#define SPR1 1 -#define CPHA 2 -#define CPOL 3 -#define MSTR 4 -#define DORD 5 -#define SPE 6 -#define SPIE 7 - -#define SPSR _SFR_IO8(0x2D) -#define SPI2X 0 -#define WCOL 6 -#define SPIF 7 - -#define SPDR _SFR_IO8(0x2E) -#define SPDR0 0 -#define SPDR1 1 -#define SPDR2 2 -#define SPDR3 3 -#define SPDR4 4 -#define SPDR5 5 -#define SPDR6 6 -#define SPDR7 7 - -#define DWDR _SFR_IO8(0x31) - -#define SMCR _SFR_IO8(0x33) -#define SE 0 -#define SM0 1 -#define SM1 2 -#define SM2 3 - -#define MCUSR _SFR_IO8(0x34) -#define PORF 0 -#define EXTRF 1 -#define BODRF 2 -#define WDRF 3 -#define OCDRF 4 - -#define MCUCR _SFR_IO8(0x35) -#define IVCE 0 -#define IVSEL 1 -#define PUD 4 -#define CKOE 5 - -#define SPMCSR _SFR_IO8(0x37) -#define SPMEN 0 -#define PGERS 1 -#define PGWRT 2 -#define LBSET 3 -#define RWWSRE 4 -#define SIGRD 5 -#define RWWSB 6 -#define SPMIE 7 - -#define WDTCSR _SFR_MEM8(0x60) -#define WDP0 0 -#define WDP1 1 -#define WDP2 2 -#define WDE 3 -#define WDCE 4 -#define WDP3 5 -#define WDIE 6 -#define WDIF 7 - -#define CLKPR _SFR_MEM8(0x61) -#define CLKPS0 0 -#define CLKPS1 1 -#define CLKPCE 7 - -#define PRR0 _SFR_MEM8(0x64) -#define PRVADC 0 -#define PRTIM0 1 -#define PRTIM1 2 -#define PRSPI 3 -#define PRVRM 5 -#define PRTWI 6 - -#define __AVR_HAVE_PRR0 ((1<, never directly. */ - -#ifndef _AVR_IO_H_ -# error "Include instead of this file." -#endif - -#ifndef _AVR_IOXXX_H_ -# define _AVR_IOXXX_H_ "iom32hvbrevb.h" -#else -# error "Attempt to include more than one file." -#endif - - -#ifndef _AVR_IOM32HVBREVB_H_ -#define _AVR_IOM32HVBREVB_H_ 1 - -/* Registers and associated bit numbers */ - -#define PINA _SFR_IO8(0x00) -#define PINA0 0 -#define PINA1 1 -#define PINA2 2 -#define PINA3 3 - -#define DDRA _SFR_IO8(0x01) -#define DDA0 0 -#define DDA1 1 -#define DDA2 2 -#define DDA3 3 - -#define PORTA _SFR_IO8(0x02) -#define PORTA0 0 -#define PORTA1 1 -#define PORTA2 2 -#define PORTA3 3 - -#define PINB _SFR_IO8(0x03) -#define PINB0 0 -#define PINB1 1 -#define PINB2 2 -#define PINB3 3 -#define PINB4 4 -#define PINB5 5 -#define PINB6 6 -#define PINB7 7 - -#define DDRB _SFR_IO8(0x04) -#define DDB0 0 -#define DDB1 1 -#define DDB2 2 -#define DDB3 3 -#define DDB4 4 -#define DDB5 5 -#define DDB6 6 -#define DDB7 7 - -#define PORTB _SFR_IO8(0x05) -#define PORTB0 0 -#define PORTB1 1 -#define PORTB2 2 -#define PORTB3 3 -#define PORTB4 4 -#define PORTB5 5 -#define PORTB6 6 -#define PORTB7 7 - -#define PINC _SFR_IO8(0x06) -#define PINC0 0 -#define PINC1 1 -#define PINC2 2 -#define PINC3 3 -#define PINC4 4 - -#define PORTC _SFR_IO8(0x08) -#define PORTC0 0 -#define PORTC1 1 -#define PORTC2 2 -#define PORTC3 3 -#define PORTC4 4 -#define PORTC5 5 - -#define TIFR0 _SFR_IO8(0x15) -#define TOV0 0 -#define OCF0A 1 -#define OCF0B 2 -#define ICF0 3 - -#define TIFR1 _SFR_IO8(0x16) -#define TOV1 0 -#define OCF1A 1 -#define OCF1B 2 -#define ICF1 3 - -#define OSICSR _SFR_IO8(0x17) -#define OSIEN 0 -#define OSIST 1 -#define OSISEL0 4 - -#define PCIFR _SFR_IO8(0x1B) -#define PCIF0 0 -#define PCIF1 1 - -#define EIFR _SFR_IO8(0x1C) -#define INTF0 0 -#define INTF1 1 -#define INTF2 2 -#define INTF3 3 - -#define EIMSK _SFR_IO8(0x1D) -#define INT0 0 -#define INT1 1 -#define INT2 2 -#define INT3 3 - -#define GPIOR0 _SFR_IO8(0x1E) -#define GPIOR00 0 -#define GPIOR01 1 -#define GPIOR02 2 -#define GPIOR03 3 -#define GPIOR04 4 -#define GPIOR05 5 -#define GPIOR06 6 -#define GPIOR07 7 - -#define EECR _SFR_IO8(0x1F) -#define EERE 0 -#define EEPE 1 -#define EEMPE 2 -#define EERIE 3 -#define EEPM0 4 -#define EEPM1 5 - -#define EEDR _SFR_IO8(0x20) -#define EEDR0 0 -#define EEDR1 1 -#define EEDR2 2 -#define EEDR3 3 -#define EEDR4 4 -#define EEDR5 5 -#define EEDR6 6 -#define EEDR7 7 - -#define EEAR _SFR_IO16(0x21) - -#define EEARL _SFR_IO8(0x21) -#define EEAR0 0 -#define EEAR1 1 -#define EEAR2 2 -#define EEAR3 3 -#define EEAR4 4 -#define EEAR5 5 -#define EEAR6 6 -#define EEAR7 7 - -#define EEARH _SFR_IO8(0x22) -#define EEAR8 0 -#define EEAR9 1 - -#define GTCCR _SFR_IO8(0x23) -#define PSRSYNC 0 -#define TSM 7 - -#define TCCR0A _SFR_IO8(0x24) -#define WGM00 0 -#define ICS0 3 -#define ICES0 4 -#define ICNC0 5 -#define ICEN0 6 -#define TCW0 7 - -#define TCCR0B _SFR_IO8(0x25) -#define CS00 0 -#define CS01 1 -#define CS02 2 - -#define TCNT0 _SFR_IO16(0x26) - -#define TCNT0L _SFR_IO8(0x26) -#define TCNT0L0 0 -#define TCNT0L1 1 -#define TCNT0L2 2 -#define TCNT0L3 3 -#define TCNT0L4 4 -#define TCNT0L5 5 -#define TCNT0L6 6 -#define TCNT0L7 7 - -#define TCNT0H _SFR_IO8(0x27) -#define TCNT0H0 0 -#define TCNT0H1 1 -#define TCNT0H2 2 -#define TCNT0H3 3 -#define TCNT0H4 4 -#define TCNT0H5 5 -#define TCNT0H6 6 -#define TCNT0H7 7 - -#define OCR0A _SFR_IO8(0x28) -#define OCR0A0 0 -#define OCR0A1 1 -#define OCR0A2 2 -#define OCR0A3 3 -#define OCR0A4 4 -#define OCR0A5 5 -#define OCR0A6 6 -#define OCR0A7 7 - -#define OCR0B _SFR_IO8(0x29) -#define OCR0B0 0 -#define OCR0B1 1 -#define OCR0B2 2 -#define OCR0B3 3 -#define OCR0B4 4 -#define OCR0B5 5 -#define OCR0B6 6 -#define OCR0B7 7 - -#define GPIOR1 _SFR_IO8(0x2A) -#define GPIOR10 0 -#define GPIOR11 1 -#define GPIOR12 2 -#define GPIOR13 3 -#define GPIOR14 4 -#define GPIOR15 5 -#define GPIOR16 6 -#define GPIOR17 7 - -#define GPIOR2 _SFR_IO8(0x2B) -#define GPIOR20 0 -#define GPIOR21 1 -#define GPIOR22 2 -#define GPIOR23 3 -#define GPIOR24 4 -#define GPIOR25 5 -#define GPIOR26 6 -#define GPIOR27 7 - -#define SPCR _SFR_IO8(0x2C) -#define SPR0 0 -#define SPR1 1 -#define CPHA 2 -#define CPOL 3 -#define MSTR 4 -#define DORD 5 -#define SPE 6 -#define SPIE 7 - -#define SPSR _SFR_IO8(0x2D) -#define SPI2X 0 -#define WCOL 6 -#define SPIF 7 - -#define SPDR _SFR_IO8(0x2E) -#define SPDR0 0 -#define SPDR1 1 -#define SPDR2 2 -#define SPDR3 3 -#define SPDR4 4 -#define SPDR5 5 -#define SPDR6 6 -#define SPDR7 7 - -#define SMCR _SFR_IO8(0x33) -#define SE 0 -#define SM0 1 -#define SM1 2 -#define SM2 3 - -#define MCUSR _SFR_IO8(0x34) -#define PORF 0 -#define EXTRF 1 -#define BODRF 2 -#define WDRF 3 -#define OCDRF 4 - -#define MCUCR _SFR_IO8(0x35) -#define IVCE 0 -#define IVSEL 1 -#define PUD 4 -#define CKOE 5 - -#define SPMCSR _SFR_IO8(0x37) -#define SPMEN 0 -#define PGERS 1 -#define PGWRT 2 -#define LBSET 3 -#define RWWSRE 4 -#define SIGRD 5 -#define RWWSB 6 -#define SPMIE 7 - -#define WDTCSR _SFR_MEM8(0x60) -#define WDP0 0 -#define WDP1 1 -#define WDP2 2 -#define WDE 3 -#define WDCE 4 -#define WDP3 5 -#define WDIE 6 -#define WDIF 7 - -#define CLKPR _SFR_MEM8(0x61) -#define CLKPS0 0 -#define CLKPS1 1 -#define CLKPCE 7 - -#define PRR0 _SFR_MEM8(0x64) -#define PRVADC 0 -#define PRTIM0 1 -#define PRTIM1 2 -#define PRSPI 3 -#define PRVRM 5 -#define PRTWI 6 - -#define __AVR_HAVE_PRR0 ((1<, never directly. */ - -#ifndef _AVR_IO_H_ -# error "Include instead of this file." -#endif - -#ifndef _AVR_IOXXX_H_ -# define _AVR_IOXXX_H_ "iom32m1.h" -#else -# error "Attempt to include more than one file." -#endif - - -#ifndef _AVR_ATmega32M1_H_ -#define _AVR_ATmega32M1_H_ 1 - - -/* Registers and associated bit numbers. */ - -#define PINB _SFR_IO8(0x03) -#define PINB0 0 -#define PINB1 1 -#define PINB2 2 -#define PINB3 3 -#define PINB4 4 -#define PINB5 5 -#define PINB6 6 -#define PINB7 7 - -#define DDRB _SFR_IO8(0x04) -#define DDB0 0 -#define DDB1 1 -#define DDB2 2 -#define DDB3 3 -#define DDB4 4 -#define DDB5 5 -#define DDB6 6 -#define DDB7 7 - -#define PORTB _SFR_IO8(0x05) -#define PORTB0 0 -#define PORTB1 1 -#define PORTB2 2 -#define PORTB3 3 -#define PORTB4 4 -#define PORTB5 5 -#define PORTB6 6 -#define PORTB7 7 - -#define PINC _SFR_IO8(0x06) -#define PINC0 0 -#define PINC1 1 -#define PINC2 2 -#define PINC3 3 -#define PINC4 4 -#define PINC5 5 -#define PINC6 6 -#define PINC7 7 - -#define DDRC _SFR_IO8(0x07) -#define DDC0 0 -#define DDC1 1 -#define DDC2 2 -#define DDC3 3 -#define DDC4 4 -#define DDC5 5 -#define DDC6 6 -#define DDC7 7 - -#define PORTC _SFR_IO8(0x08) -#define PORTC0 0 -#define PORTC1 1 -#define PORTC2 2 -#define PORTC3 3 -#define PORTC4 4 -#define PORTC5 5 -#define PORTC6 6 -#define PORTC7 7 - -#define PIND _SFR_IO8(0x09) -#define PIND0 0 -#define PIND1 1 -#define PIND2 2 -#define PIND3 3 -#define PIND4 4 -#define PIND5 5 -#define PIND6 6 -#define PIND7 7 - -#define DDRD _SFR_IO8(0x0A) -#define DDD0 0 -#define DDD1 1 -#define DDD2 2 -#define DDD3 3 -#define DDD4 4 -#define DDD5 5 -#define DDD6 6 -#define DDD7 7 - -#define PORTD _SFR_IO8(0x0B) -#define PORTD0 0 -#define PORTD1 1 -#define PORTD2 2 -#define PORTD3 3 -#define PORTD4 4 -#define PORTD5 5 -#define PORTD6 6 -#define PORTD7 7 - -#define PINE _SFR_IO8(0x0C) -#define PINE0 0 -#define PINE1 1 -#define PINE2 2 - -#define DDRE _SFR_IO8(0x0D) -#define DDE0 0 -#define DDE1 1 -#define DDE2 2 - -#define PORTE _SFR_IO8(0x0E) -#define PORTE0 0 -#define PORTE1 1 -#define PORTE2 2 - -#define TIFR0 _SFR_IO8(0x15) -#define TOV0 0 -#define OCF0A 1 -#define OCF0B 2 - -#define TIFR1 _SFR_IO8(0x16) -#define TOV1 0 -#define OCF1A 1 -#define OCF1B 2 -#define ICF1 5 - -#define GPIOR1 _SFR_IO8(0x19) -#define GPIOR10 0 -#define GPIOR11 1 -#define GPIOR12 2 -#define GPIOR13 3 -#define GPIOR14 4 -#define GPIOR15 5 -#define GPIOR16 6 -#define GPIOR17 7 - -#define GPIOR2 _SFR_IO8(0x1A) -#define GPIOR20 0 -#define GPIOR21 1 -#define GPIOR22 2 -#define GPIOR23 3 -#define GPIOR24 4 -#define GPIOR25 5 -#define GPIOR26 6 -#define GPIOR27 7 - -#define PCIFR _SFR_IO8(0x1B) -#define PCIF0 0 -#define PCIF1 1 -#define PCIF2 2 -#define PCIF3 3 - -#define EIFR _SFR_IO8(0x1C) -#define INTF0 0 -#define INTF1 1 -#define INTF2 2 -#define INTF3 3 - -#define EIMSK _SFR_IO8(0x1D) -#define INT0 0 -#define INT1 1 -#define INT2 2 -#define INT3 3 - -#define GPIOR0 _SFR_IO8(0x1E) -#define GPIOR00 0 -#define GPIOR01 1 -#define GPIOR02 2 -#define GPIOR03 3 -#define GPIOR04 4 -#define GPIOR05 5 -#define GPIOR06 6 -#define GPIOR07 7 - -#define EECR _SFR_IO8(0x1F) -#define EERE 0 -#define EEWE 1 -#define EEMWE 2 -#define EERIE 3 -#define EEPM0 4 -#define EEPM1 5 - -#define EEDR _SFR_IO8(0x20) -#define EEDR0 0 -#define EEDR1 1 -#define EEDR2 2 -#define EEDR3 3 -#define EEDR4 4 -#define EEDR5 5 -#define EEDR6 6 -#define EEDR7 7 - -#define EEAR _SFR_IO16(0x21) - -#define EEARL _SFR_IO8(0x21) -#define EEAR0 0 -#define EEAR1 1 -#define EEAR2 2 -#define EEAR3 3 -#define EEAR4 4 -#define EEAR5 5 -#define EEAR6 6 -#define EEAR7 7 - -#define EEARH _SFR_IO8(0x22) -#define EEAR8 0 -#define EEAR9 1 - -#define GTCCR _SFR_IO8(0x23) -#define PSR10 0 -#define PSRSYNC 0 -#define ICPSEL1 6 -#define TSM 7 - -#define TCCR0A _SFR_IO8(0x24) -#define WGM00 0 -#define WGM01 1 -#define COM0B0 4 -#define COM0B1 5 -#define COM0A0 6 -#define COM0A1 7 - -#define TCCR0B _SFR_IO8(0x25) -#define CS00 0 -#define CS01 1 -#define CS02 2 -#define WGM02 3 -#define FOC0B 6 -#define FOC0A 7 - -#define TCNT0 _SFR_IO8(0x26) -#define TCNT0_0 0 -#define TCNT0_1 1 -#define TCNT0_2 2 -#define TCNT0_3 3 -#define TCNT0_4 4 -#define TCNT0_5 5 -#define TCNT0_6 6 -#define TCNT0_7 7 - -#define OCR0A _SFR_IO8(0x27) -#define OCR0A_0 0 -#define OCR0A_1 1 -#define OCR0A_2 2 -#define OCR0A_3 3 -#define OCR0A_4 4 -#define OCR0A_5 5 -#define OCR0A_6 6 -#define OCR0A_7 7 - -#define OCR0B _SFR_IO8(0x28) -#define OCR0B_0 0 -#define OCR0B_1 1 -#define OCR0B_2 2 -#define OCR0B_3 3 -#define OCR0B_4 4 -#define OCR0B_5 5 -#define OCR0B_6 6 -#define OCR0B_7 7 - -#define PLLCSR _SFR_IO8(0x29) -#define PLOCK 0 -#define PLLE 1 -#define PLLF 2 - -#define SPCR _SFR_IO8(0x2C) -#define SPR0 0 -#define SPR1 1 -#define CPHA 2 -#define CPOL 3 -#define MSTR 4 -#define DORD 5 -#define SPE 6 -#define SPIE 7 - -#define SPSR _SFR_IO8(0x2D) -#define SPI2X 0 -#define WCOL 6 -#define SPIF 7 - -#define SPDR _SFR_IO8(0x2E) -#define SPDR0 0 -#define SPDR1 1 -#define SPDR2 2 -#define SPDR3 3 -#define SPDR4 4 -#define SPDR5 5 -#define SPDR6 6 -#define SPDR7 7 - -#define ACSR _SFR_IO8(0x30) -#define AC0O 0 -#define AC1O 1 -#define AC2O 2 -#define AC3O 3 -#define AC0IF 4 -#define AC1IF 5 -#define AC2IF 6 -#define AC3IF 7 - -#define DWDR _SFR_IO8(0x31) - -#define SMCR _SFR_IO8(0x33) -#define SE 0 -#define SM0 1 -#define SM1 2 -#define SM2 3 - -#define MCUSR _SFR_IO8(0x34) -#define PORF 0 -#define EXTRF 1 -#define BORF 2 -#define WDRF 3 - -#define MCUCR _SFR_IO8(0x35) -#define IVCE 0 -#define IVSEL 1 -#define PUD 4 -#define SPIPS 7 - -#define SPMCSR _SFR_IO8(0x37) -#define SPMEN 0 -#define PGERS 1 -#define PGWRT 2 -#define BLBSET 3 -#define RWWSRE 4 -#define SIGRD 5 -#define RWWSB 6 -#define SPMIE 7 - -#define WDTCSR _SFR_MEM8(0x60) -#define WDP0 0 -#define WDP1 1 -#define WDP2 2 -#define WDE 3 -#define WDCE 4 -#define WDP3 5 -#define WDIE 6 -#define WDIF 7 - -#define CLKPR _SFR_MEM8(0x61) -#define CLKPS0 0 -#define CLKPS1 1 -#define CLKPS2 2 -#define CLKPS3 3 -#define CLKPCE 7 - -#define PRR _SFR_MEM8(0x64) -#define PRADC 0 -#define PRLIN 1 -#define PRSPI 2 -#define PRTIM0 3 -#define PRTIM1 4 -#define PRPSC 5 -#define PRCAN 6 - -#define __AVR_HAVE_PRR ((1<, never directly. */ - -#ifndef _AVR_IO_H_ -# error "Include instead of this file." -#endif - -#ifndef _AVR_IOXXX_H_ -# define _AVR_IOXXX_H_ "iom32u2.h" -#else -# error "Attempt to include more than one file." -#endif - - -#ifndef _AVR_ATmega32U2_H_ -#define _AVR_ATmega32U2_H_ 1 - - -/* Registers and associated bit numbers. */ - -#define PINB _SFR_IO8(0x03) -#define PINB0 0 -#define PINB1 1 -#define PINB2 2 -#define PINB3 3 -#define PINB4 4 -#define PINB5 5 -#define PINB6 6 -#define PINB7 7 - -#define DDRB _SFR_IO8(0x04) -#define DDB0 0 -#define DDB1 1 -#define DDB2 2 -#define DDB3 3 -#define DDB4 4 -#define DDB5 5 -#define DDB6 6 -#define DDB7 7 - -#define PORTB _SFR_IO8(0x05) -#define PORTB0 0 -#define PORTB1 1 -#define PORTB2 2 -#define PORTB3 3 -#define PORTB4 4 -#define PORTB5 5 -#define PORTB6 6 -#define PORTB7 7 - -#define PINC _SFR_IO8(0x06) -#define PINC0 0 -#define PINC1 1 -#define PINC2 2 -#define PINC4 4 -#define PINC5 5 -#define PINC6 6 -#define PINC7 7 - -#define DDRC _SFR_IO8(0x07) -#define DDC0 0 -#define DDC1 1 -#define DDC2 2 -#define DDC4 4 -#define DDC5 5 -#define DDC6 6 -#define DDC7 7 - -#define PORTC _SFR_IO8(0x08) -#define PORTC0 0 -#define PORTC1 1 -#define PORTC2 2 -#define PORTC4 4 -#define PORTC5 5 -#define PORTC6 6 -#define PORTC7 7 - -#define PIND _SFR_IO8(0x09) -#define PIND0 0 -#define PIND1 1 -#define PIND2 2 -#define PIND3 3 -#define PIND4 4 -#define PIND5 5 -#define PIND6 6 -#define PIND7 7 - -#define DDRD _SFR_IO8(0x0A) -#define DDD0 0 -#define DDD1 1 -#define DDD2 2 -#define DDD3 3 -#define DDD4 4 -#define DDD5 5 -#define DDD6 6 -#define DDD7 7 - -#define PORTD _SFR_IO8(0x0B) -#define PORTD0 0 -#define PORTD1 1 -#define PORTD2 2 -#define PORTD3 3 -#define PORTD4 4 -#define PORTD5 5 -#define PORTD6 6 -#define PORTD7 7 - -#define TIFR0 _SFR_IO8(0x15) -#define TOV0 0 -#define OCF0A 1 -#define OCF0B 2 - -#define TIFR1 _SFR_IO8(0x16) -#define TOV1 0 -#define OCF1A 1 -#define OCF1B 2 -#define OCF1C 3 -#define ICF1 5 - -#define PCIFR _SFR_IO8(0x1B) -#define PCIF0 0 -#define PCIF1 1 - -#define EIFR _SFR_IO8(0x1C) -#define INTF0 0 -#define INTF1 1 -#define INTF2 2 -#define INTF3 3 -#define INTF4 4 -#define INTF5 5 -#define INTF6 6 -#define INTF7 7 - -#define EIMSK _SFR_IO8(0x1D) -#define INT0 0 -#define INT1 1 -#define INT2 2 -#define INT3 3 -#define INT4 4 -#define INT5 5 -#define INT6 6 -#define INT7 7 - -#define GPIOR0 _SFR_IO8(0x1E) -#define GPIOR00 0 -#define GPIOR01 1 -#define GPIOR02 2 -#define GPIOR03 3 -#define GPIOR04 4 -#define GPIOR05 5 -#define GPIOR06 6 -#define GPIOR07 7 - -#define EECR _SFR_IO8(0x1F) -#define EERE 0 -#define EEPE 1 -#define EEMPE 2 -#define EERIE 3 -#define EEPM0 4 -#define EEPM1 5 - -#define EEDR _SFR_IO8(0x20) -#define EEDR0 0 -#define EEDR1 1 -#define EEDR2 2 -#define EEDR3 3 -#define EEDR4 4 -#define EEDR5 5 -#define EEDR6 6 -#define EEDR7 7 - -#define EEAR _SFR_IO16(0x21) - -#define EEARL _SFR_IO8(0x21) -#define EEAR0 0 -#define EEAR1 1 -#define EEAR2 2 -#define EEAR3 3 -#define EEAR4 4 -#define EEAR5 5 -#define EEAR6 6 -#define EEAR7 7 - -#define EEARH _SFR_IO8(0x22) -#define EEAR8 0 -#define EEAR9 1 -#define EEAR10 2 -#define EEAR11 3 - -#define GTCCR _SFR_IO8(0x23) -#define PSRSYNC 0 -#define TSM 7 - -#define TCCR0A _SFR_IO8(0x24) -#define WGM00 0 -#define WGM01 1 -#define COM0B0 4 -#define COM0B1 5 -#define COM0A0 6 -#define COM0A1 7 - -#define TCCR0B _SFR_IO8(0x25) -#define CS00 0 -#define CS01 1 -#define CS02 2 -#define WGM02 3 -#define FOC0B 6 -#define FOC0A 7 - -#define TCNT0 _SFR_IO8(0x26) -#define TCNT0_0 0 -#define TCNT0_1 1 -#define TCNT0_2 2 -#define TCNT0_3 3 -#define TCNT0_4 4 -#define TCNT0_5 5 -#define TCNT0_6 6 -#define TCNT0_7 7 - -#define OCR0A _SFR_IO8(0x27) -#define OCR0A_0 0 -#define OCR0A_1 1 -#define OCR0A_2 2 -#define OCR0A_3 3 -#define OCR0A_4 4 -#define OCR0A_5 5 -#define OCR0A_6 6 -#define OCR0A_7 7 - -#define OCR0B _SFR_IO8(0x28) -#define OCR0B_0 0 -#define OCR0B_1 1 -#define OCR0B_2 2 -#define OCR0B_3 3 -#define OCR0B_4 4 -#define OCR0B_5 5 -#define OCR0B_6 6 -#define OCR0B_7 7 - -#define PLLCSR _SFR_IO8(0x29) -#define PLOCK 0 -#define PLLE 1 -#define PLLP0 2 -#define PLLP1 3 -#define PLLP2 4 - -#define GPIOR1 _SFR_IO8(0x2A) -#define GPIOR10 0 -#define GPIOR11 1 -#define GPIOR12 2 -#define GPIOR13 3 -#define GPIOR14 4 -#define GPIOR15 5 -#define GPIOR16 6 -#define GPIOR17 7 - -#define GPIOR2 _SFR_IO8(0x2B) -#define GPIOR20 0 -#define GPIOR21 1 -#define GPIOR22 2 -#define GPIOR23 3 -#define GPIOR24 4 -#define GPIOR25 5 -#define GPIOR26 6 -#define GPIOR27 7 - -#define SPCR _SFR_IO8(0x2C) -#define SPR0 0 -#define SPR1 1 -#define CPHA 2 -#define CPOL 3 -#define MSTR 4 -#define DORD 5 -#define SPE 6 -#define SPIE 7 - -#define SPSR _SFR_IO8(0x2D) -#define SPI2X 0 -#define WCOL 6 -#define SPIF 7 - -#define SPDR _SFR_IO8(0x2E) -#define SPDR0 0 -#define SPDR1 1 -#define SPDR2 2 -#define SPDR3 3 -#define SPDR4 4 -#define SPDR5 5 -#define SPDR6 6 -#define SPDR7 7 - -#define ACSR _SFR_IO8(0x30) -#define ACIS0 0 -#define ACIS1 1 -#define ACIC 2 -#define ACIE 3 -#define ACI 4 -#define ACO 5 -#define ACBG 6 -#define ACD 7 - -#define DWDR _SFR_IO8(0x31) -#define DWDR0 0 -#define DWDR1 1 -#define DWDR2 2 -#define DWDR3 3 -#define DWDR4 4 -#define DWDR5 5 -#define DWDR6 6 -#define DWDR7 7 - -#define SMCR _SFR_IO8(0x33) -#define SE 0 -#define SM0 1 -#define SM1 2 -#define SM2 3 - -#define MCUSR _SFR_IO8(0x34) -#define PORF 0 -#define EXTRF 1 -#define BORF 2 -#define WDRF 3 -#define USBRF 5 - -#define MCUCR _SFR_IO8(0x35) -#define IVCE 0 -#define IVSEL 1 -#define PUD 4 - -#define SPMCSR _SFR_IO8(0x37) -#define SPMEN 0 -#define PGERS 1 -#define PGWRT 2 -#define BLBSET 3 -#define RWWSRE 4 -#define SIGRD 5 -#define RWWSB 6 -#define SPMIE 7 - -#define EIND _SFR_IO8(0x3C) -#define EIND0 0 - -#define WDTCSR _SFR_MEM8(0x60) -#define WDP0 0 -#define WDP1 1 -#define WDP2 2 -#define WDE 3 -#define WDCE 4 -#define WDP3 5 -#define WDIE 6 -#define WDIF 7 - -#define CLKPR _SFR_MEM8(0x61) -#define CLKPS0 0 -#define CLKPS1 1 -#define CLKPS2 2 -#define CLKPS3 3 -#define CLKPCE 7 - -#define WDTCKD _SFR_MEM8(0x62) -#define WCLKD0 0 -#define WCLKD1 1 -#define WDEWIE 2 -#define WDEWIF 3 - -#define REGCR _SFR_MEM8(0x63) -#define REGDIS 0 - -#define PRR0 _SFR_MEM8(0x64) -#define PRSPI 2 -#define PRTIM1 3 -#define PRTIM0 5 - -#define __AVR_HAVE_PRR0 ((1<, never directly. */ - -#ifndef _AVR_IO_H_ -# error "Include instead of this file." -#endif - -#ifndef _AVR_IOXXX_H_ -# define _AVR_IOXXX_H_ "iom32u4.h" -#else -# error "Attempt to include more than one file." -#endif - - -#ifndef _AVR_IOM32U4_H_ -#define _AVR_IOM32U4_H_ 1 - - -/* Registers and associated bit numbers */ - -#define PINB _SFR_IO8(0x03) -#define PINB0 0 -#define PINB1 1 -#define PINB2 2 -#define PINB3 3 -#define PINB4 4 -#define PINB5 5 -#define PINB6 6 -#define PINB7 7 - -#define DDRB _SFR_IO8(0x04) -#define DDB0 0 -#define DDB1 1 -#define DDB2 2 -#define DDB3 3 -#define DDB4 4 -#define DDB5 5 -#define DDB6 6 -#define DDB7 7 - -#define PORTB _SFR_IO8(0x05) -#define PORTB0 0 -#define PORTB1 1 -#define PORTB2 2 -#define PORTB3 3 -#define PORTB4 4 -#define PORTB5 5 -#define PORTB6 6 -#define PORTB7 7 - -#define PINC _SFR_IO8(0x06) -#define PINC6 6 -#define PINC7 7 - -#define DDRC _SFR_IO8(0x07) -#define DDC6 6 -#define DDC7 7 - -#define PORTC _SFR_IO8(0x08) -#define PORTC6 6 -#define PORTC7 7 - -#define PIND _SFR_IO8(0x09) -#define PIND0 0 -#define PIND1 1 -#define PIND2 2 -#define PIND3 3 -#define PIND4 4 -#define PIND5 5 -#define PIND6 6 -#define PIND7 7 - -#define DDRD _SFR_IO8(0x0A) -#define DDD0 0 -#define DDD1 1 -#define DDD2 2 -#define DDD3 3 -#define DDD4 4 -#define DDD5 5 -#define DDD6 6 -#define DDD7 7 - -#define PORTD _SFR_IO8(0x0B) -#define PORTD0 0 -#define PORTD1 1 -#define PORTD2 2 -#define PORTD3 3 -#define PORTD4 4 -#define PORTD5 5 -#define PORTD6 6 -#define PORTD7 7 - -#define PINE _SFR_IO8(0x0C) -#define PINE2 2 -#define PINE6 6 - -#define DDRE _SFR_IO8(0x0D) -#define DDE2 2 -#define DDE6 6 - -#define PORTE _SFR_IO8(0x0E) -#define PORTE2 2 -#define PORTE6 6 - -#define PINF _SFR_IO8(0x0F) -#define PINF0 0 -#define PINF1 1 -#define PINF4 4 -#define PINF5 5 -#define PINF6 6 -#define PINF7 7 - -#define DDRF _SFR_IO8(0x10) -#define DDF0 0 -#define DDF1 1 -#define DDF4 4 -#define DDF5 5 -#define DDF6 6 -#define DDF7 7 - -#define PORTF _SFR_IO8(0x11) -#define PORTF0 0 -#define PORTF1 1 -#define PORTF4 4 -#define PORTF5 5 -#define PORTF6 6 -#define PORTF7 7 - -#define TIFR0 _SFR_IO8(0x15) -#define TOV0 0 -#define OCF0A 1 -#define OCF0B 2 - -#define TIFR1 _SFR_IO8(0x16) -#define TOV1 0 -#define OCF1A 1 -#define OCF1B 2 -#define OCF1C 3 -#define ICF1 5 - -#define TIFR3 _SFR_IO8(0x18) -#define TOV3 0 -#define OCF3A 1 -#define OCF3B 2 -#define OCF3C 3 -#define ICF3 5 - -#define TIFR4 _SFR_IO8(0x19) -#define TOV4 2 -#define OCF4B 5 -#define OCF4A 6 -#define OCF4D 7 - -#define TIFR5 _SFR_IO8(0x1A) - -#define PCIFR _SFR_IO8(0x1B) -#define PCIF0 0 - -#define EIFR _SFR_IO8(0x1C) -#define INTF0 0 -#define INTF1 1 -#define INTF2 2 -#define INTF3 3 -#define INTF4 4 -#define INTF5 5 -#define INTF6 6 -#define INTF7 7 - -#define EIMSK _SFR_IO8(0x1D) -#define INT0 0 -#define INT1 1 -#define INT2 2 -#define INT3 3 -#define INT4 4 -#define INT5 5 -#define INT6 6 -#define INT7 7 - -#define GPIOR0 _SFR_IO8(0x1E) -#define GPIOR00 0 -#define GPIOR01 1 -#define GPIOR02 2 -#define GPIOR03 3 -#define GPIOR04 4 -#define GPIOR05 5 -#define GPIOR06 6 -#define GPIOR07 7 - -#define EECR _SFR_IO8(0x1F) -#define EERE 0 -#define EEPE 1 -#define EEMPE 2 -#define EERIE 3 -#define EEPM0 4 -#define EEPM1 5 - -#define EEDR _SFR_IO8(0x20) -#define EEDR0 0 -#define EEDR1 1 -#define EEDR2 2 -#define EEDR3 3 -#define EEDR4 4 -#define EEDR5 5 -#define EEDR6 6 -#define EEDR7 7 - -#define EEAR _SFR_IO16(0x21) - -#define EEARL _SFR_IO8(0x21) -#define EEAR0 0 -#define EEAR1 1 -#define EEAR2 2 -#define EEAR3 3 -#define EEAR4 4 -#define EEAR5 5 -#define EEAR6 6 -#define EEAR7 7 - -#define EEARH _SFR_IO8(0x22) -#define EEAR8 0 -#define EEAR9 1 -#define EEAR10 2 -#define EEAR11 3 - -#define GTCCR _SFR_IO8(0x23) -#define PSRSYNC 0 -#define PSRASY 1 -#define TSM 7 - -#define TCCR0A _SFR_IO8(0x24) -#define WGM00 0 -#define WGM01 1 -#define COM0B0 4 -#define COM0B1 5 -#define COM0A0 6 -#define COM0A1 7 - -#define TCCR0B _SFR_IO8(0x25) -#define CS00 0 -#define CS01 1 -#define CS02 2 -#define WGM02 3 -#define FOC0B 6 -#define FOC0A 7 - -#define TCNT0 _SFR_IO8(0x26) -#define TCNT0_0 0 -#define TCNT0_1 1 -#define TCNT0_2 2 -#define TCNT0_3 3 -#define TCNT0_4 4 -#define TCNT0_5 5 -#define TCNT0_6 6 -#define TCNT0_7 7 - -#define OCR0A _SFR_IO8(0x27) -#define OCR0A_0 0 -#define OCR0A_1 1 -#define OCR0A_2 2 -#define OCR0A_3 3 -#define OCR0A_4 4 -#define OCR0A_5 5 -#define OCR0A_6 6 -#define OCR0A_7 7 - -#define OCR0B _SFR_IO8(0x28) -#define OCR0B_0 0 -#define OCR0B_1 1 -#define OCR0B_2 2 -#define OCR0B_3 3 -#define OCR0B_4 4 -#define OCR0B_5 5 -#define OCR0B_6 6 -#define OCR0B_7 7 - -#define PLLCSR _SFR_IO8(0x29) -#define PLOCK 0 -#define PLLE 1 -#define PINDIV 4 - -#define GPIOR1 _SFR_IO8(0x2A) -#define GPIOR10 0 -#define GPIOR11 1 -#define GPIOR12 2 -#define GPIOR13 3 -#define GPIOR14 4 -#define GPIOR15 5 -#define GPIOR16 6 -#define GPIOR17 7 - -#define GPIOR2 _SFR_IO8(0x2B) -#define GPIOR20 0 -#define GPIOR21 1 -#define GPIOR22 2 -#define GPIOR23 3 -#define GPIOR24 4 -#define GPIOR25 5 -#define GPIOR26 6 -#define GPIOR27 7 - -#define SPCR _SFR_IO8(0x2C) -#define SPR0 0 -#define SPR1 1 -#define CPHA 2 -#define CPOL 3 -#define MSTR 4 -#define DORD 5 -#define SPE 6 -#define SPIE 7 - -#define SPSR _SFR_IO8(0x2D) -#define SPI2X 0 -#define WCOL 6 -#define SPIF 7 - -#define SPDR _SFR_IO8(0x2E) -#define SPDR0 0 -#define SPDR1 1 -#define SPDR2 2 -#define SPDR3 3 -#define SPDR4 4 -#define SPDR5 5 -#define SPDR6 6 -#define SPDR7 7 - -#define ACSR _SFR_IO8(0x30) -#define ACIS0 0 -#define ACIS1 1 -#define ACIC 2 -#define ACIE 3 -#define ACI 4 -#define ACO 5 -#define ACBG 6 -#define ACD 7 - -#define OCDR _SFR_IO8(0x31) -#define OCDR0 0 -#define OCDR1 1 -#define OCDR2 2 -#define OCDR3 3 -#define OCDR4 4 -#define OCDR5 5 -#define OCDR6 6 -#define OCDR7 7 - -#define PLLFRQ _SFR_IO8(0x32) -#define PDIV0 0 -#define PDIV1 1 -#define PDIV2 2 -#define PDIV3 3 -#define PLLTM0 4 -#define PLLTM1 5 -#define PLLUSB 6 -#define PINMUX 7 - -#define SMCR _SFR_IO8(0x33) -#define SE 0 -#define SM0 1 -#define SM1 2 -#define SM2 3 - -#define MCUSR _SFR_IO8(0x34) -#define PORF 0 -#define EXTRF 1 -#define BORF 2 -#define WDRF 3 -#define JTRF 4 - -#define MCUCR _SFR_IO8(0x35) -#define IVCE 0 -#define IVSEL 1 -#define PUD 4 -#define JTD 7 - -#define SPMCSR _SFR_IO8(0x37) -#define SPMEN 0 -#define PGERS 1 -#define PGWRT 2 -#define BLBSET 3 -#define RWWSRE 4 -#define SIGRD 5 -#define RWWSB 6 -#define SPMIE 7 - -#define RAMPZ _SFR_IO8(0x3B) -#define RAMPZ0 0 - -#define EIND _SFR_IO8(0x3C) -#define EIND0 0 - -#define WDTCSR _SFR_MEM8(0x60) -#define WDP0 0 -#define WDP1 1 -#define WDP2 2 -#define WDE 3 -#define WDCE 4 -#define WDP3 5 -#define WDIE 6 -#define WDIF 7 - -#define CLKPR _SFR_MEM8(0x61) -#define CLKPS0 0 -#define CLKPS1 1 -#define CLKPS2 2 -#define CLKPS3 3 -#define CLKPCE 7 - -/* Reserved [0x62..0x63] */ - -#define PRR0 _SFR_MEM8(0x64) -#define PRADC 0 -#define PRUSART0 1 -#define PRSPI 2 -#define PRTIM1 3 -#define PRTIM0 5 -#define PRTIM2 6 -#define PRTWI 7 - -#define __AVR_HAVE_PRR0 ((1<, never directly. */ - -#ifndef _AVR_IO_H_ -# error "Include instead of this file." -#endif - -#ifndef _AVR_IOXXX_H_ -# define _AVR_IOXXX_H_ "iom32u6.h" -#else -# error "Attempt to include more than one file." -#endif - - -#ifndef _AVR_ATmega32U6_H_ -#define _AVR_ATmega32U6_H_ 1 - - -/* Registers and associated bit numbers. */ - -#define PINA _SFR_IO8(0x00) -#define PINA0 0 -#define PINA1 1 -#define PINA2 2 -#define PINA3 3 -#define PINA4 4 -#define PINA5 5 -#define PINA6 6 -#define PINA7 7 - -#define DDRA _SFR_IO8(0x01) -#define DDA0 0 -#define DDA1 1 -#define DDA2 2 -#define DDA3 3 -#define DDA4 4 -#define DDA5 5 -#define DDA6 6 -#define DDA7 7 - -#define PORTA _SFR_IO8(0x02) -#define PORTA0 0 -#define PORTA1 1 -#define PORTA2 2 -#define PORTA3 3 -#define PORTA4 4 -#define PORTA5 5 -#define PORTA6 6 -#define PORTA7 7 - -#define PINB _SFR_IO8(0x03) -#define PINB0 0 -#define PINB1 1 -#define PINB2 2 -#define PINB3 3 -#define PINB4 4 -#define PINB5 5 -#define PINB6 6 -#define PINB7 7 - -#define DDRB _SFR_IO8(0x04) -#define DDB0 0 -#define DDB1 1 -#define DDB2 2 -#define DDB3 3 -#define DDB4 4 -#define DDB5 5 -#define DDB6 6 -#define DDB7 7 - -#define PORTB _SFR_IO8(0x05) -#define PORTB0 0 -#define PORTB1 1 -#define PORTB2 2 -#define PORTB3 3 -#define PORTB4 4 -#define PORTB5 5 -#define PORTB6 6 -#define PORTB7 7 - -#define PINC _SFR_IO8(0x06) -#define PINC0 0 -#define PINC1 1 -#define PINC2 2 -#define PINC3 3 -#define PINC4 4 -#define PINC5 5 -#define PINC6 6 -#define PINC7 7 - -#define DDRC _SFR_IO8(0x07) -#define DDC0 0 -#define DDC1 1 -#define DDC2 2 -#define DDC3 3 -#define DDC4 4 -#define DDC5 5 -#define DDC6 6 -#define DDC7 7 - -#define PORTC _SFR_IO8(0x08) -#define PORTC0 0 -#define PORTC1 1 -#define PORTC2 2 -#define PORTC3 3 -#define PORTC4 4 -#define PORTC5 5 -#define PORTC6 6 -#define PORTC7 7 - -#define PIND _SFR_IO8(0x09) -#define PIND0 0 -#define PIND1 1 -#define PIND2 2 -#define PIND3 3 -#define PIND4 4 -#define PIND5 5 -#define PIND6 6 -#define PIND7 7 - -#define DDRD _SFR_IO8(0x0A) -#define DDD0 0 -#define DDD1 1 -#define DDD2 2 -#define DDD3 3 -#define DDD4 4 -#define DDD5 5 -#define DDD6 6 -#define DDD7 7 - -#define PORTD _SFR_IO8(0x0B) -#define PORTD0 0 -#define PORTD1 1 -#define PORTD2 2 -#define PORTD3 3 -#define PORTD4 4 -#define PORTD5 5 -#define PORTD6 6 -#define PORTD7 7 - -#define PINE _SFR_IO8(0x0C) -#define PINE0 0 -#define PINE1 1 -#define PINE2 2 -#define PINE3 3 -#define PINE4 4 -#define PINE5 5 -#define PINE6 6 -#define PINE7 7 - -#define DDRE _SFR_IO8(0x0D) -#define DDE0 0 -#define DDE1 1 -#define DDE2 2 -#define DDE3 3 -#define DDE4 4 -#define DDE5 5 -#define DDE6 6 -#define DDE7 7 - -#define PORTE _SFR_IO8(0x0E) -#define PORTE0 0 -#define PORTE1 1 -#define PORTE2 2 -#define PORTE3 3 -#define PORTE4 4 -#define PORTE5 5 -#define PORTE6 6 -#define PORTE7 7 - -#define PINF _SFR_IO8(0x0F) -#define PINF0 0 -#define PINF1 1 -#define PINF2 2 -#define PINF3 3 -#define PINF4 4 -#define PINF5 5 -#define PINF6 6 -#define PINF7 7 - -#define DDRF _SFR_IO8(0x10) -#define DDF0 0 -#define DDF1 1 -#define DDF2 2 -#define DDF3 3 -#define DDF4 4 -#define DDF5 5 -#define DDF6 6 -#define DDF7 7 - -#define PORTF _SFR_IO8(0x11) -#define PORTF0 0 -#define PORTF1 1 -#define PORTF2 2 -#define PORTF3 3 -#define PORTF4 4 -#define PORTF5 5 -#define PORTF6 6 -#define PORTF7 7 - -#define TIFR0 _SFR_IO8(0x15) -#define TOV0 0 -#define OCF0A 1 -#define OCF0B 2 - -#define TIFR1 _SFR_IO8(0x16) -#define TOV1 0 -#define OCF1A 1 -#define OCF1B 2 -#define OCF1C 3 -#define ICF1 5 - -#define TIFR2 _SFR_IO8(0x17) -#define TOV2 0 -#define OCF2A 1 -#define OCF2B 2 - -#define TIFR3 _SFR_IO8(0x18) -#define TOV3 0 -#define OCF3A 1 -#define OCF3B 2 -#define OCF3C 3 -#define ICF3 5 - -#define PCIFR _SFR_IO8(0x1B) -#define PCIF0 0 - -#define EIFR _SFR_IO8(0x1C) -#define INTF0 0 -#define INTF1 1 -#define INTF2 2 -#define INTF3 3 -#define INTF4 4 -#define INTF5 5 -#define INTF6 6 -#define INTF7 7 - -#define EIMSK _SFR_IO8(0x1D) -#define INT0 0 -#define INT1 1 -#define INT2 2 -#define INT3 3 -#define INT4 4 -#define INT5 5 -#define INT6 6 -#define INT7 7 - -#define GPIOR0 _SFR_IO8(0x1E) -#define GPIOR00 0 -#define GPIOR01 1 -#define GPIOR02 2 -#define GPIOR03 3 -#define GPIOR04 4 -#define GPIOR05 5 -#define GPIOR06 6 -#define GPIOR07 7 - -#define EECR _SFR_IO8(0x1F) -#define EERE 0 -#define EEPE 1 -#define EEMPE 2 -#define EERIE 3 -#define EEPM0 4 -#define EEPM1 5 - -#define EEDR _SFR_IO8(0x20) -#define EEDR0 0 -#define EEDR1 1 -#define EEDR2 2 -#define EEDR3 3 -#define EEDR4 4 -#define EEDR5 5 -#define EEDR6 6 -#define EEDR7 7 - -#define EEAR _SFR_IO16(0x21) - -#define EEARL _SFR_IO8(0x21) -#define EEAR0 0 -#define EEAR1 1 -#define EEAR2 2 -#define EEAR3 3 -#define EEAR4 4 -#define EEAR5 5 -#define EEAR6 6 -#define EEAR7 7 - -#define EEARH _SFR_IO8(0x22) -#define EEAR8 0 -#define EEAR9 1 -#define EEAR10 2 -#define EEAR11 3 - -#define GTCCR _SFR_IO8(0x23) -#define PSRSYNC 0 -#define PSRASY 1 -#define TSM 7 - -#define TCCR0A _SFR_IO8(0x24) -#define WGM00 0 -#define WGM01 1 -#define COM0B0 4 -#define COM0B1 5 -#define COM0A0 6 -#define COM0A1 7 - -#define TCCR0B _SFR_IO8(0x25) -#define CS00 0 -#define CS01 1 -#define CS02 2 -#define WGM02 3 -#define FOC0B 6 -#define FOC0A 7 - -#define TCNT0 _SFR_IO8(0x26) -#define TCNT0_0 0 -#define TCNT0_1 1 -#define TCNT0_2 2 -#define TCNT0_3 3 -#define TCNT0_4 4 -#define TCNT0_5 5 -#define TCNT0_6 6 -#define TCNT0_7 7 - -#define OCR0A _SFR_IO8(0x27) -#define OCR0A_0 0 -#define OCR0A_1 1 -#define OCR0A_2 2 -#define OCR0A_3 3 -#define OCR0A_4 4 -#define OCR0A_5 5 -#define OCR0A_6 6 -#define OCR0A_7 7 - -#define OCR0B _SFR_IO8(0x28) -#define OCR0B_0 0 -#define OCR0B_1 1 -#define OCR0B_2 2 -#define OCR0B_3 3 -#define OCR0B_4 4 -#define OCR0B_5 5 -#define OCR0B_6 6 -#define OCR0B_7 7 - -#define PLLCSR _SFR_IO8(0x29) -#define PLOCK 0 -#define PLLE 1 -#define PLLP0 2 -#define PLLP1 3 -#define PLLP2 4 - -#define GPIOR1 _SFR_IO8(0x2A) -#define GPIOR10 0 -#define GPIOR11 1 -#define GPIOR12 2 -#define GPIOR13 3 -#define GPIOR14 4 -#define GPIOR15 5 -#define GPIOR16 6 -#define GPIOR17 7 - -#define GPIOR2 _SFR_IO8(0x2B) -#define GPIOR20 0 -#define GPIOR21 1 -#define GPIOR22 2 -#define GPIOR23 3 -#define GPIOR24 4 -#define GPIOR25 5 -#define GPIOR26 6 -#define GPIOR27 7 - -#define SPCR _SFR_IO8(0x2C) -#define SPR0 0 -#define SPR1 1 -#define CPHA 2 -#define CPOL 3 -#define MSTR 4 -#define DORD 5 -#define SPE 6 -#define SPIE 7 - -#define SPSR _SFR_IO8(0x2D) -#define SPI2X 0 -#define WCOL 6 -#define SPIF 7 - -#define SPDR _SFR_IO8(0x2E) -#define SPDR0 0 -#define SPDR1 1 -#define SPDR2 2 -#define SPDR3 3 -#define SPDR4 4 -#define SPDR5 5 -#define SPDR6 6 -#define SPDR7 7 - -#define ACSR _SFR_IO8(0x30) -#define ACIS0 0 -#define ACIS1 1 -#define ACIC 2 -#define ACIE 3 -#define ACI 4 -#define ACO 5 -#define ACBG 6 -#define ACD 7 - -#define OCDR _SFR_IO8(0x31) -#define OCDR0 0 -#define OCDR1 1 -#define OCDR2 2 -#define OCDR3 3 -#define OCDR4 4 -#define OCDR5 5 -#define OCDR6 6 -#define OCDR7 7 - -#define SMCR _SFR_IO8(0x33) -#define SE 0 -#define SM0 1 -#define SM1 2 -#define SM2 3 - -#define MCUSR _SFR_IO8(0x34) -#define PORF 0 -#define EXTRF 1 -#define BORF 2 -#define WDRF 3 -#define JTRF 4 - -#define MCUCR _SFR_IO8(0x35) -#define IVCE 0 -#define IVSEL 1 -#define PUD 4 -#define JTD 7 - -#define SPMCSR _SFR_IO8(0x37) -#define SPMEN 0 -#define PGERS 1 -#define PGWRT 2 -#define BLBSET 3 -#define RWWSRE 4 -#define SIGRD 5 -#define RWWSB 6 -#define SPMIE 7 - -#define WDTCSR _SFR_MEM8(0x60) -#define WDP0 0 -#define WDP1 1 -#define WDP2 2 -#define WDE 3 -#define WDCE 4 -#define WDP3 5 -#define WDIE 6 -#define WDIF 7 - -#define CLKPR _SFR_MEM8(0x61) -#define CLKPS0 0 -#define CLKPS1 1 -#define CLKPS2 2 -#define CLKPS3 3 -#define CLKPCE 7 - -#define PRR0 _SFR_MEM8(0x64) -#define PRADC 0 -#define PRSPI 2 -#define PRTIM1 3 -#define PRTIM0 5 -#define PRTIM2 6 -#define PRTWI 7 - -#define __AVR_HAVE_PRR0 ((1<, never directly. */ - -#ifndef _AVR_IO_H_ -# error "Include instead of this file." -#endif - -#ifndef _AVR_IOXXX_H_ -# define _AVR_IOXXX_H_ "iom406.h" -#else -# error "Attempt to include more than one file." -#endif - -/* I/O registers */ - -#define PINA _SFR_IO8(0x00) -#define PINA7 7 -#define PINA6 6 -#define PINA5 5 -#define PINA4 4 -#define PINA3 3 -#define PINA2 2 -#define PINA1 1 -#define PINA0 0 - -#define DDRA _SFR_IO8(0x01) -#define DDA7 7 -#define DDA6 6 -#define DDA5 5 -#define DDA4 4 -#define DDA3 3 -#define DDA2 2 -#define DDA1 1 -#define DDA0 0 - -#define PORTA _SFR_IO8(0x02) -#define PA7 7 -#define PA6 6 -#define PA5 5 -#define PA4 4 -#define PA3 3 -#define PA2 2 -#define PA1 1 -#define PA0 0 - -#define PINB _SFR_IO8(0x03) -#define PINB7 7 -#define PINB6 6 -#define PINB5 5 -#define PINB4 4 -#define PINB3 3 -#define PINB2 2 -#define PINB1 1 -#define PINB0 0 - -#define DDRB _SFR_IO8(0x04) -#define DDB7 7 -#define DDB6 6 -#define DDB5 5 -#define DDB4 4 -#define DDB3 3 -#define DDB2 2 -#define DDB1 1 -#define DDB0 0 - -#define PORTB _SFR_IO8(0x05) -#define PB7 7 -#define PB6 6 -#define PB5 5 -#define PB4 4 -#define PB3 3 -#define PB2 2 -#define PB1 1 -#define PB0 0 - -/* Reserved [0x06..0x07] */ - -#define PORTC _SFR_IO8(0x08) -#define PC0 0 - -#define PIND _SFR_IO8(0x09) -#define PIND1 1 -#define PIND0 0 - -#define DDRD _SFR_IO8(0x0A) -#define DDD1 1 -#define DDD0 0 - -#define PORTD _SFR_IO8(0x0B) -#define PD1 1 -#define PD0 0 - -/* Reserved [0x0C..0x14] */ - -/* Timer/Counter0 Interrupt Flag Register */ -#define TIFR0 _SFR_IO8(0x15) -#define OCF0B 2 -#define OCF0A 1 -#define TOV0 0 - -/* Timer/Counter1 Interrupt Flag Register */ -#define TIFR1 _SFR_IO8(0x16) -#define OCF1A 1 -#define TOV1 0 - -/* Reserved [0x17..0x1A] */ - -/* Pin Change Interrupt Control Register */ -#define PCIFR _SFR_IO8(0x1B) -#define PCIF1 1 -#define PCIF0 0 - -/* External Interrupt Flag Register */ -#define EIFR _SFR_IO8(0x1C) -#define INTF3 3 -#define INTF2 2 -#define INTF1 1 -#define INTF0 0 - -/* External Interrupt MaSK register */ -#define EIMSK _SFR_IO8(0x1D) -#define INT3 3 -#define INT2 2 -#define INT1 1 -#define INT0 0 - -/* General Purpose I/O Register 0 */ -#define GPIOR0 _SFR_IO8(0x1E) - -/* EEPROM Control Register */ -#define EECR _SFR_IO8(0x1F) -#define EEPM1 5 -#define EEPM0 4 -#define EERIE 3 -#define EEMPE 2 -#define EEPE 1 -#define EERE 0 - -/* EEPROM Data Register */ -#define EEDR _SFR_IO8(0x20) - -/* EEPROM Address Register */ -#define EEAR _SFR_IO16(0x21) -#define EEARL _SFR_IO8(0x21) -#define EEARH _SFR_IO8(0x22) - -/* 6-char sequence denoting where to find the EEPROM registers in memory space. - Adresses denoted in hex syntax with uppercase letters. Used by the EEPROM - subroutines. - First two letters: EECR address. - Second two letters: EEDR address. - Last two letters: EEAR address. */ -#define __EEPROM_REG_LOCATIONS__ 1F2021 - -/* General Timer/Counter Control Register */ -#define GTCCR _SFR_IO8(0x23) -#define TSM 7 -#define PSRSYNC 0 - -/* Timer/Counter Control Register A */ -#define TCCR0A _SFR_IO8(0x24) -#define COM0A1 7 -#define COM0A0 6 -#define COM0B1 5 -#define COM0B0 4 -#define WGM01 1 -#define WGM00 0 - -/* Timer/Counter Control Register B */ -#define TCCR0B _SFR_IO8(0x25) -#define FOC0A 7 -#define FOC0B 6 -#define WGM02 3 -#define CS02 2 -#define CS01 1 -#define CS00 0 - -/* Timer/Counter 0 */ -#define TCNT0 _SFR_IO8(0x26) - -/* Output Compare Register A */ -#define OCR0A _SFR_IO8(0x27) - -/* Output Compare Register B */ -#define OCR0B _SFR_IO8(0x28) - -/* Reserved [0x29] */ - -/* General Purpose I/O Register 1 */ -#define GPIOR1 _SFR_IO8(0x2A) - -/* General Purpose I/O Register 2 */ -#define GPIOR2 _SFR_IO8(0x2B) - -/* Reserved [0x2C..0x30] */ - -/* On-chip Debug Register */ -#define OCDR _SFR_IO8(0x31) - -/* Reserved [0x32] */ - -/* Sleep Mode Control Register */ -#define SMCR _SFR_IO8(0x33) -#define SM2 3 -#define SM1 2 -#define SM0 1 -#define SE 0 - -/* MCU Status Register */ -#define MCUSR _SFR_IO8(0x34) -#define JTRF 4 -#define WDRF 3 -#define BODRF 2 -#define EXTRF 1 -#define PORF 0 - -/* MCU general Control Register */ -#define MCUCR _SFR_IO8(0x35) -#define JTD 7 -#define PUD 4 -#define IVSEL 1 -#define IVCE 0 - -/* Reserved [0x36] */ - -/* Store Program Memory Control and Status Register */ -#define SPMCSR _SFR_IO8(0x37) -#define SPMIE 7 -#define RWWSB 6 -#define SIGRD 5 -#define RWWSRE 4 -#define BLBSET 3 -#define PGWRT 2 -#define PGERS 1 -#define SPMEN 0 - -/* Reserved [0x36..0x3C] */ - -/* 0x3D..0x3E SP */ - -/* 0x3F SREG */ - -/* Extended I/O registers */ - -/* Watchdog Timer Control Register */ -#define WDTCSR _SFR_MEM8(0x60) -#define WDIF 7 -#define WDIE 6 -#define WDP3 5 -#define WDCE 4 -#define WDE 3 -#define WDP2 2 -#define WDP1 1 -#define WDP0 0 - -/* Reserved [0x61] */ - -/* Wake-up Timer Control and Status Register */ -#define WUTCSR _SFR_MEM8(0x62) -#define WUTIF 7 -#define WUTIE 6 -#define WUTCF 5 -#define WUTR 4 -#define WUTE 3 -#define WUTP2 2 -#define WUTP1 1 -#define WUTP0 0 - -/* Reserved [0x63] */ - -/* Power Reduction Register 0 */ -#define PRR0 _SFR_MEM8(0x64) -#define PRTWI 3 -#define PRTIM1 2 -#define PRTIM0 1 -#define PRVADC 0 - -#define __AVR_HAVE_PRR0 ((1< - -/* Constants */ -#define SPM_PAGESIZE 64 -#define RAMSTART (0x100) -#define RAMEND 0x2FF -#define XRAMEND RAMEND -#define E2END 0xFF -#define E2PAGESIZE 4 -#define FLASHEND 0xFFF - - -/* Fuses */ -#define FUSE_MEMORY_SIZE 3 - -/* Low Fuse Byte */ -#define FUSE_CKSEL0 (unsigned char)~_BV(0) /* Select Clock Source */ -#define FUSE_CKSEL1 (unsigned char)~_BV(1) /* Select Clock Source */ -#define FUSE_CKSEL2 (unsigned char)~_BV(2) /* Select Clock Source */ -#define FUSE_CKSEL3 (unsigned char)~_BV(3) /* Select Clock Source */ -#define FUSE_SUT0 (unsigned char)~_BV(4) /* Select start-up time */ -#define FUSE_SUT1 (unsigned char)~_BV(5) /* Select start-up time */ -#define FUSE_CKOUT (unsigned char)~_BV(6) /* Clock output */ -#define FUSE_CKDIV8 (unsigned char)~_BV(7) /* Divide clock by 8 */ -#define LFUSE_DEFAULT (FUSE_CKDIV8 & FUSE_SUT0 & FUSE_CKSEL3 & FUSE_CKSEL2 & FUSE_CKSEL0) - -/* High Fuse Byte */ -#define FUSE_BODLEVEL0 (unsigned char)~_BV(0) /* Brown-out Detector trigger level */ -#define FUSE_BODLEVEL1 (unsigned char)~_BV(1) /* Brown-out Detector trigger level */ -#define FUSE_BODLEVEL2 (unsigned char)~_BV(2) /* Brown-out Detector trigger level */ -#define FUSE_EESAVE (unsigned char)~_BV(3) /* EEPROM memory is preserved through chip erase */ -#define FUSE_WDTON (unsigned char)~_BV(4) /* Watchdog Timer Always On */ -#define FUSE_SPIEN (unsigned char)~_BV(5) /* Enable Serial programming and Data Downloading */ -#define FUSE_DWEN (unsigned char)~_BV(6) /* debugWIRE Enable */ -#define FUSE_RSTDISBL (unsigned char)~_BV(7) /* External reset disable */ -#define HFUSE_DEFAULT (FUSE_SPIEN) - -/* Extended Fuse Byte */ -#define FUSE_SELFPRGEN (unsigned char)~_BV(0) /* Self Programming Enable */ -#define EFUSE_DEFAULT (0xFF) - - -/* Lock Bits */ -#define __LOCK_BITS_EXIST - - -/* Signature */ -#define SIGNATURE_0 0x1E -#define SIGNATURE_1 0x92 -#define SIGNATURE_2 0x05 - -#define SLEEP_MODE_IDLE (0x00<<1) -#define SLEEP_MODE_ADC (0x01<<1) -#define SLEEP_MODE_PWR_DOWN (0x02<<1) -#define SLEEP_MODE_PWR_SAVE (0x03<<1) -#define SLEEP_MODE_STANDBY (0x06<<1) - -#endif /* _AVR_IOM48_H_ */ diff --git a/arduino/hardware/tools/avr/avr/include/avr/iom4808.h b/arduino/hardware/tools/avr/avr/include/avr/iom4808.h deleted file mode 100644 index a1df896..0000000 --- a/arduino/hardware/tools/avr/avr/include/avr/iom4808.h +++ /dev/null @@ -1,5413 +0,0 @@ -/***************************************************************************** - * - * Copyright (C) 2017 Atmel Corporation, a wholly owned subsidiary of Microchip Technology Inc. - * All rights reserved. - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - ****************************************************************************/ - - -#ifndef _AVR_IO_H_ -# error "Include instead of this file." -#endif - -#ifndef _AVR_IOXXX_H_ -# define _AVR_IOXXX_H_ "iom4808.h" -#else -# error "Attempt to include more than one file." -#endif - -#ifndef _AVR_ATMEGA4808_H_INCLUDED -#define _AVR_ATMEGA4808_H_INCLUDED - -/* Ungrouped common registers */ -#define CCP _SFR_MEM8(0x0034) /* Configuration Change Protection */ -#define RAMPZ _SFR_MEM8(0x003B) /* Extended Z-pointer Register */ -#define SPH _SFR_MEM8(0x003E) /* Stack Pointer High */ -#define SPL _SFR_MEM8(0x003D) /* Stack Pointer Low */ -#define SREG _SFR_MEM8(0x003F) /* Status Register */ - -#define GPIOR0 _SFR_MEM8(0x001C) /* General Purpose IO Register 0 */ -#define GPIOR1 _SFR_MEM8(0x001D) /* General Purpose IO Register 1 */ -#define GPIOR2 _SFR_MEM8(0x001E) /* General Purpose IO Register 2 */ -#define GPIOR3 _SFR_MEM8(0x001F) /* General Purpose IO Register 3 */ - -/* Deprecated */ -#define GPIO0 _SFR_MEM8(0x001C) /* General Purpose IO Register 0 */ -#define GPIO1 _SFR_MEM8(0x001D) /* General Purpose IO Register 1 */ -#define GPIO2 _SFR_MEM8(0x001E) /* General Purpose IO Register 2 */ -#define GPIO3 _SFR_MEM8(0x001F) /* General Purpose IO Register 3 */ - -/* C Language Only */ -#if !defined (__ASSEMBLER__) - -#include - -typedef volatile uint8_t register8_t; -typedef volatile uint16_t register16_t; -typedef volatile uint32_t register32_t; - - -#ifdef _WORDREGISTER -#undef _WORDREGISTER -#endif -#define _WORDREGISTER(regname) \ - __extension__ union \ - { \ - register16_t regname; \ - struct \ - { \ - register8_t regname ## L; \ - register8_t regname ## H; \ - }; \ - } - -#ifdef _DWORDREGISTER -#undef _DWORDREGISTER -#endif -#define _DWORDREGISTER(regname) \ - __extension__ union \ - { \ - register32_t regname; \ - struct \ - { \ - register8_t regname ## 0; \ - register8_t regname ## 1; \ - register8_t regname ## 2; \ - register8_t regname ## 3; \ - }; \ - } - - -/* -========================================================================== -IO Module Structures -========================================================================== -*/ - - -/* --------------------------------------------------------------------------- -AC - Analog Comparator --------------------------------------------------------------------------- -*/ - -/* Analog Comparator */ -typedef struct AC_struct -{ - register8_t CTRLA; /* Control A */ - register8_t reserved_0x01; - register8_t MUXCTRLA; /* Mux Control A */ - register8_t reserved_0x03; - register8_t DACREF; /* Referance scale control */ - register8_t reserved_0x05; - register8_t INTCTRL; /* Interrupt Control */ - register8_t STATUS; /* Status */ -} AC_t; - -/* Hysteresis Mode select */ -typedef enum AC_HYSMODE_enum -{ - AC_HYSMODE_OFF_gc = (0x00<<1), /* No hysteresis */ - AC_HYSMODE_10mV_gc = (0x01<<1), /* 10mV hysteresis */ - AC_HYSMODE_25mV_gc = (0x02<<1), /* 25mV hysteresis */ - AC_HYSMODE_50mV_gc = (0x03<<1), /* 50mV hysteresis */ -} AC_HYSMODE_t; - -/* Interrupt Mode select */ -typedef enum AC_INTMODE_enum -{ - AC_INTMODE_BOTHEDGE_gc = (0x00<<4), /* Any Edge */ - AC_INTMODE_NEGEDGE_gc = (0x02<<4), /* Negative Edge */ - AC_INTMODE_POSEDGE_gc = (0x03<<4), /* Positive Edge */ -} AC_INTMODE_t; - -/* Low Power Mode select */ -typedef enum AC_LPMODE_enum -{ - AC_LPMODE_DIS_gc = (0x00<<3), /* Low power mode disabled */ - AC_LPMODE_EN_gc = (0x01<<3), /* Low power mode enabled */ -} AC_LPMODE_t; - -/* Negative Input MUX Selection select */ -typedef enum AC_MUXNEG_enum -{ - AC_MUXNEG_PIN0_gc = (0x00<<0), /* Negative Pin 0 */ - AC_MUXNEG_PIN1_gc = (0x01<<0), /* Negative Pin 1 */ - AC_MUXNEG_PIN2_gc = (0x02<<0), /* Negative Pin 2 */ - AC_MUXNEG_DACREF_gc = (0x03<<0), /* DAC Voltage Reference */ -} AC_MUXNEG_t; - -/* Positive Input MUX Selection select */ -typedef enum AC_MUXPOS_enum -{ - AC_MUXPOS_PIN0_gc = (0x00<<3), /* Positive Pin 0 */ - AC_MUXPOS_PIN1_gc = (0x01<<3), /* Positive Pin 1 */ - AC_MUXPOS_PIN2_gc = (0x02<<3), /* Positive Pin 2 */ - AC_MUXPOS_PIN3_gc = (0x03<<3), /* Positive Pin 3 */ -} AC_MUXPOS_t; - -/* --------------------------------------------------------------------------- -ADC - Analog to Digital Converter --------------------------------------------------------------------------- -*/ - -/* Analog to Digital Converter */ -typedef struct ADC_struct -{ - register8_t CTRLA; /* Control A */ - register8_t CTRLB; /* Control B */ - register8_t CTRLC; /* Control C */ - register8_t CTRLD; /* Control D */ - register8_t CTRLE; /* Control E */ - register8_t SAMPCTRL; /* Sample Control */ - register8_t MUXPOS; /* Positive mux input */ - register8_t reserved_0x07; - register8_t COMMAND; /* Command */ - register8_t EVCTRL; /* Event Control */ - register8_t INTCTRL; /* Interrupt Control */ - register8_t INTFLAGS; /* Interrupt Flags */ - register8_t DBGCTRL; /* Debug Control */ - register8_t TEMP; /* Temporary Data */ - register8_t reserved_0x0E; - register8_t reserved_0x0F; - _WORDREGISTER(RES); /* ADC Accumulator Result */ - _WORDREGISTER(WINLT); /* Window comparator low threshold */ - _WORDREGISTER(WINHT); /* Window comparator high threshold */ - register8_t CALIB; /* Calibration */ - register8_t reserved_0x17; -} ADC_t; - -/* Automatic Sampling Delay Variation select */ -typedef enum ADC_ASDV_enum -{ - ADC_ASDV_ASVOFF_gc = (0x00<<4), /* The Automatic Sampling Delay Variation is disabled */ - ADC_ASDV_ASVON_gc = (0x01<<4), /* The Automatic Sampling Delay Variation is enabled */ -} ADC_ASDV_t; - -/* Duty Cycle select */ -typedef enum ADC_DUTYCYC_enum -{ - ADC_DUTYCYC_DUTY50_gc = (0x00<<0), /* 50% Duty cycle */ - ADC_DUTYCYC_DUTY25_gc = (0x01<<0), /* 25% Duty cycle */ -} ADC_DUTYCYC_t; - -/* Initial Delay Selection select */ -typedef enum ADC_INITDLY_enum -{ - ADC_INITDLY_DLY0_gc = (0x00<<5), /* Delay 0 CLK_ADC cycles */ - ADC_INITDLY_DLY16_gc = (0x01<<5), /* Delay 16 CLK_ADC cycles */ - ADC_INITDLY_DLY32_gc = (0x02<<5), /* Delay 32 CLK_ADC cycles */ - ADC_INITDLY_DLY64_gc = (0x03<<5), /* Delay 64 CLK_ADC cycles */ - ADC_INITDLY_DLY128_gc = (0x04<<5), /* Delay 128 CLK_ADC cycles */ - ADC_INITDLY_DLY256_gc = (0x05<<5), /* Delay 256 CLK_ADC cycles */ -} ADC_INITDLY_t; - -/* Analog Channel Selection Bits select */ -typedef enum ADC_MUXPOS_enum -{ - ADC_MUXPOS_AIN0_gc = (0x00<<0), /* ADC input pin 0 */ - ADC_MUXPOS_AIN1_gc = (0x01<<0), /* ADC input pin 1 */ - ADC_MUXPOS_DACREF_gc = (0x1C<<0), /* AC DAC Reference */ - ADC_MUXPOS_TEMPSENSE_gc = (0x1E<<0), /* Temperature sensor */ - ADC_MUXPOS_GND_gc = (0x1F<<0), /* 0V (GND) */ - ADC_MUXPOS_AIN2_gc = (0x02<<0), /* ADC input pin 2 */ - ADC_MUXPOS_AIN3_gc = (0x03<<0), /* ADC input pin 3 */ - ADC_MUXPOS_AIN4_gc = (0x04<<0), /* ADC input pin 4 */ - ADC_MUXPOS_AIN5_gc = (0x05<<0), /* ADC input pin 5 */ - ADC_MUXPOS_AIN6_gc = (0x06<<0), /* ADC input pin 6 */ - ADC_MUXPOS_AIN7_gc = (0x07<<0), /* ADC input pin 7 */ - ADC_MUXPOS_AIN8_gc = (0x08<<0), /* ADC input pin 8 */ - ADC_MUXPOS_AIN9_gc = (0x09<<0), /* ADC input pin 9 */ - ADC_MUXPOS_AIN10_gc = (0x0A<<0), /* ADC input pin 10 */ - ADC_MUXPOS_AIN11_gc = (0x0B<<0), /* ADC input pin 11 */ - ADC_MUXPOS_AIN12_gc = (0x0C<<0), /* ADC input pin 12 */ - ADC_MUXPOS_AIN13_gc = (0x0D<<0), /* ADC input pin 13 */ - ADC_MUXPOS_AIN14_gc = (0x0E<<0), /* ADC input pin 14 */ - ADC_MUXPOS_AIN15_gc = (0x0F<<0), /* ADC input pin 15 */ -} ADC_MUXPOS_t; - -/* Clock Pre-scaler select */ -typedef enum ADC_PRESC_enum -{ - ADC_PRESC_DIV2_gc = (0x00<<0), /* CLK_PER divided by 2 */ - ADC_PRESC_DIV4_gc = (0x01<<0), /* CLK_PER divided by 4 */ - ADC_PRESC_DIV8_gc = (0x02<<0), /* CLK_PER divided by 8 */ - ADC_PRESC_DIV16_gc = (0x03<<0), /* CLK_PER divided by 16 */ - ADC_PRESC_DIV32_gc = (0x04<<0), /* CLK_PER divided by 32 */ - ADC_PRESC_DIV64_gc = (0x05<<0), /* CLK_PER divided by 64 */ - ADC_PRESC_DIV128_gc = (0x06<<0), /* CLK_PER divided by 128 */ - ADC_PRESC_DIV256_gc = (0x07<<0), /* CLK_PER divided by 256 */ -} ADC_PRESC_t; - -/* Reference Selection select */ -typedef enum ADC_REFSEL_enum -{ - ADC_REFSEL_INTREF_gc = (0x00<<4), /* Internal reference */ - ADC_REFSEL_VDDREF_gc = (0x01<<4), /* VDD */ - ADC_REFSEL_VREFA_gc = (0x02<<4), /* External reference */ -} ADC_REFSEL_t; - -/* ADC Resolution select */ -typedef enum ADC_RESSEL_enum -{ - ADC_RESSEL_10BIT_gc = (0x00<<2), /* 10-bit mode */ - ADC_RESSEL_8BIT_gc = (0x01<<2), /* 8-bit mode */ -} ADC_RESSEL_t; - -/* Accumulation Samples select */ -typedef enum ADC_SAMPNUM_enum -{ - ADC_SAMPNUM_ACC1_gc = (0x00<<0), /* 1 ADC sample */ - ADC_SAMPNUM_ACC2_gc = (0x01<<0), /* Accumulate 2 samples */ - ADC_SAMPNUM_ACC4_gc = (0x02<<0), /* Accumulate 4 samples */ - ADC_SAMPNUM_ACC8_gc = (0x03<<0), /* Accumulate 8 samples */ - ADC_SAMPNUM_ACC16_gc = (0x04<<0), /* Accumulate 16 samples */ - ADC_SAMPNUM_ACC32_gc = (0x05<<0), /* Accumulate 32 samples */ - ADC_SAMPNUM_ACC64_gc = (0x06<<0), /* Accumulate 64 samples */ -} ADC_SAMPNUM_t; - -/* Window Comparator Mode select */ -typedef enum ADC_WINCM_enum -{ - ADC_WINCM_NONE_gc = (0x00<<0), /* No Window Comparison */ - ADC_WINCM_BELOW_gc = (0x01<<0), /* Below Window */ - ADC_WINCM_ABOVE_gc = (0x02<<0), /* Above Window */ - ADC_WINCM_INSIDE_gc = (0x03<<0), /* Inside Window */ - ADC_WINCM_OUTSIDE_gc = (0x04<<0), /* Outside Window */ -} ADC_WINCM_t; - -/* --------------------------------------------------------------------------- -BOD - Bod interface --------------------------------------------------------------------------- -*/ - -/* Bod interface */ -typedef struct BOD_struct -{ - register8_t CTRLA; /* Control A */ - register8_t CTRLB; /* Control B */ - register8_t reserved_0x02; - register8_t reserved_0x03; - register8_t reserved_0x04; - register8_t reserved_0x05; - register8_t reserved_0x06; - register8_t reserved_0x07; - register8_t VLMCTRLA; /* Voltage level monitor Control */ - register8_t INTCTRL; /* Voltage level monitor interrupt Control */ - register8_t INTFLAGS; /* Voltage level monitor interrupt Flags */ - register8_t STATUS; /* Voltage level monitor status */ - register8_t reserved_0x0C; - register8_t reserved_0x0D; - register8_t reserved_0x0E; - register8_t reserved_0x0F; -} BOD_t; - -/* Operation in active mode select */ -typedef enum BOD_ACTIVE_enum -{ - BOD_ACTIVE_DIS_gc = (0x00<<2), /* Disabled */ - BOD_ACTIVE_ENABLED_gc = (0x01<<2), /* Enabled */ - BOD_ACTIVE_SAMPLED_gc = (0x02<<2), /* Sampled */ - BOD_ACTIVE_ENWAKE_gc = (0x03<<2), /* Enabled with wake-up halted until BOD is ready */ -} BOD_ACTIVE_t; - -/* Bod level select */ -typedef enum BOD_LVL_enum -{ - BOD_LVL_BODLEVEL0_gc = (0x00<<0), /* 1.8 V */ - BOD_LVL_BODLEVEL1_gc = (0x01<<0), /* 2.1 V */ - BOD_LVL_BODLEVEL2_gc = (0x02<<0), /* 2.6 V */ - BOD_LVL_BODLEVEL3_gc = (0x03<<0), /* 2.9 V */ - BOD_LVL_BODLEVEL4_gc = (0x04<<0), /* 3.3 V */ - BOD_LVL_BODLEVEL5_gc = (0x05<<0), /* 3.7 V */ - BOD_LVL_BODLEVEL6_gc = (0x06<<0), /* 4.0 V */ - BOD_LVL_BODLEVEL7_gc = (0x07<<0), /* 4.2 V */ -} BOD_LVL_t; - -/* Sample frequency select */ -typedef enum BOD_SAMPFREQ_enum -{ - BOD_SAMPFREQ_1KHZ_gc = (0x00<<4), /* 1kHz sampling frequency */ - BOD_SAMPFREQ_125HZ_gc = (0x01<<4), /* 125kHz sampling frequency */ -} BOD_SAMPFREQ_t; - -/* Operation in sleep mode select */ -typedef enum BOD_SLEEP_enum -{ - BOD_SLEEP_DIS_gc = (0x00<<0), /* Disabled */ - BOD_SLEEP_ENABLED_gc = (0x01<<0), /* Enabled */ - BOD_SLEEP_SAMPLED_gc = (0x02<<0), /* Sampled */ -} BOD_SLEEP_t; - -/* Configuration select */ -typedef enum BOD_VLMCFG_enum -{ - BOD_VLMCFG_BELOW_gc = (0x00<<1), /* Interrupt when supply goes below VLM level */ - BOD_VLMCFG_ABOVE_gc = (0x01<<1), /* Interrupt when supply goes above VLM level */ - BOD_VLMCFG_CROSS_gc = (0x02<<1), /* Interrupt when supply crosses VLM level */ -} BOD_VLMCFG_t; - -/* voltage level monitor level select */ -typedef enum BOD_VLMLVL_enum -{ - BOD_VLMLVL_5ABOVE_gc = (0x00<<0), /* VLM threshold 5% above BOD level */ - BOD_VLMLVL_15ABOVE_gc = (0x01<<0), /* VLM threshold 15% above BOD level */ - BOD_VLMLVL_25ABOVE_gc = (0x02<<0), /* VLM threshold 25% above BOD level */ -} BOD_VLMLVL_t; - -/* --------------------------------------------------------------------------- -CCL - Configurable Custom Logic --------------------------------------------------------------------------- -*/ - -/* Configurable Custom Logic */ -typedef struct CCL_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t SEQCTRL0; /* Sequential Control 0 */ - register8_t reserved_0x02; - register8_t reserved_0x03; - register8_t reserved_0x04; - register8_t INTCTRL0; /* Interrupt Control 0 */ - register8_t reserved_0x06; - register8_t INTFLAGS; /* Interrupt Flags */ - register8_t LUT0CTRLA; /* LUT Control 0 A */ - register8_t LUT0CTRLB; /* LUT Control 0 B */ - register8_t LUT0CTRLC; /* LUT Control 0 C */ - register8_t TRUTH0; /* Truth 0 */ - register8_t LUT1CTRLA; /* LUT Control 1 A */ - register8_t LUT1CTRLB; /* LUT Control 1 B */ - register8_t LUT1CTRLC; /* LUT Control 1 C */ - register8_t TRUTH1; /* Truth 1 */ - register8_t LUT2CTRLA; /* LUT Control 2 A */ - register8_t LUT2CTRLB; /* LUT Control 2 B */ - register8_t LUT2CTRLC; /* LUT Control 2 C */ - register8_t TRUTH2; /* Truth 2 */ - register8_t LUT3CTRLA; /* LUT Control 3 A */ - register8_t LUT3CTRLB; /* LUT Control 3 B */ - register8_t LUT3CTRLC; /* LUT Control 3 C */ - register8_t TRUTH3; /* Truth 3 */ - register8_t reserved_0x18; - register8_t reserved_0x19; - register8_t reserved_0x1A; - register8_t reserved_0x1B; - register8_t reserved_0x1C; - register8_t reserved_0x1D; - register8_t reserved_0x1E; - register8_t reserved_0x1F; - register8_t reserved_0x20; - register8_t reserved_0x21; - register8_t reserved_0x22; - register8_t reserved_0x23; - register8_t reserved_0x24; - register8_t reserved_0x25; - register8_t reserved_0x26; - register8_t reserved_0x27; - register8_t reserved_0x28; - register8_t reserved_0x29; - register8_t reserved_0x2A; - register8_t reserved_0x2B; - register8_t reserved_0x2C; - register8_t reserved_0x2D; - register8_t reserved_0x2E; - register8_t reserved_0x2F; - register8_t reserved_0x30; - register8_t reserved_0x31; - register8_t reserved_0x32; - register8_t reserved_0x33; - register8_t reserved_0x34; - register8_t reserved_0x35; - register8_t reserved_0x36; - register8_t reserved_0x37; - register8_t reserved_0x38; - register8_t reserved_0x39; - register8_t reserved_0x3A; - register8_t reserved_0x3B; - register8_t reserved_0x3C; - register8_t reserved_0x3D; - register8_t reserved_0x3E; - register8_t reserved_0x3F; -} CCL_t; - -/* Clock Source Selection select */ -typedef enum CCL_CLKSRC_enum -{ - CCL_CLKSRC_CLKPER_gc = (0x00<<1), /* CLK_PER is clocking the LUT */ - CCL_CLKSRC_IN2_gc = (0x01<<1), /* IN[2] is clocking the LUT */ - CCL_CLKSRC_OSC20M_gc = (0x02<<1), /* 20MHz oscillator before prescaler is clocking the LUT */ - CCL_CLKSRC_OSCULP32K_gc = (0x03<<1), /* 32kHz oscillator is clocking the LUT */ - CCL_CLKSRC_OSCULP1K_gc = (0x04<<1), /* 32kHz oscillator after DIV32 is clocking the LUT */ -} CCL_CLKSRC_t; - -/* Edge Detection Enable select */ -typedef enum CCL_EDGEDET_enum -{ - CCL_EDGEDET_DIS_gc = (0x00<<7), /* Edge detector is disabled */ - CCL_EDGEDET_EN_gc = (0x01<<7), /* Edge detector is enabled */ -} CCL_EDGEDET_t; - -/* Filter Selection select */ -typedef enum CCL_FILTSEL_enum -{ - CCL_FILTSEL_DISABLE_gc = (0x00<<4), /* Filter disabled */ - CCL_FILTSEL_SYNCH_gc = (0x01<<4), /* Synchronizer enabled */ - CCL_FILTSEL_FILTER_gc = (0x02<<4), /* Filter enabled */ -} CCL_FILTSEL_t; - -/* LUT Input 0 Source Selection select */ -typedef enum CCL_INSEL0_enum -{ - CCL_INSEL0_MASK_gc = (0x00<<0), /* Masked input */ - CCL_INSEL0_FEEDBACK_gc = (0x01<<0), /* Feedback input source */ - CCL_INSEL0_LINK_gc = (0x02<<0), /* Linked LUT input source */ - CCL_INSEL0_EVENTA_gc = (0x03<<0), /* Event input source A */ - CCL_INSEL0_EVENTB_gc = (0x04<<0), /* Event input source B */ - CCL_INSEL0_IO_gc = (0x05<<0), /* IO pin LUTn-IN0 input source */ - CCL_INSEL0_AC0_gc = (0x06<<0), /* AC0 OUT input source */ - CCL_INSEL0_USART0_gc = (0x08<<0), /* USART0 TXD input source */ - CCL_INSEL0_SPI0_gc = (0x09<<0), /* SPI0 MOSI input source */ - CCL_INSEL0_TCA0_gc = (0x0A<<0), /* TCA0 WO0 input source */ - CCL_INSEL0_TCB0_gc = (0x0C<<0), /* TCB0 WO input source */ - CCL_INSEL0_TCD0_gc = (0x0D<<0), /* TCD0 WOA input source */ -} CCL_INSEL0_t; - -/* LUT Input 1 Source Selection select */ -typedef enum CCL_INSEL1_enum -{ - CCL_INSEL1_MASK_gc = (0x00<<4), /* Masked input */ - CCL_INSEL1_FEEDBACK_gc = (0x01<<4), /* Feedback input source */ - CCL_INSEL1_LINK_gc = (0x02<<4), /* Linked LUT input source */ - CCL_INSEL1_EVENTA_gc = (0x03<<4), /* Event input source A */ - CCL_INSEL1_EVENTB_gc = (0x04<<4), /* Event input source B */ - CCL_INSEL1_IO_gc = (0x05<<4), /* IO pin LUTn-N1 input source */ - CCL_INSEL1_AC0_gc = (0x06<<4), /* AC0 OUT input source */ - CCL_INSEL1_USART1_gc = (0x08<<4), /* USART1 TXD input source */ - CCL_INSEL1_SPI0_gc = (0x09<<4), /* SPI0 MOSI input source */ - CCL_INSEL1_TCA0_gc = (0x0A<<4), /* TCA0 WO1 input source */ - CCL_INSEL1_TCB1_gc = (0x0C<<4), /* TCB1 WO input source */ - CCL_INSEL1_TCD0_gc = (0x0D<<4), /* TCD0 WOB input soruce */ -} CCL_INSEL1_t; - -/* LUT Input 2 Source Selection select */ -typedef enum CCL_INSEL2_enum -{ - CCL_INSEL2_MASK_gc = (0x00<<0), /* Masked input */ - CCL_INSEL2_FEEDBACK_gc = (0x01<<0), /* Feedback input source */ - CCL_INSEL2_LINK_gc = (0x02<<0), /* Linked LUT input source */ - CCL_INSEL2_EVENTA_gc = (0x03<<0), /* Event input source A */ - CCL_INSEL2_EVENTB_gc = (0x04<<0), /* Event input source B */ - CCL_INSEL2_IO_gc = (0x05<<0), /* IO pin LUTn-IN2 input source */ - CCL_INSEL2_AC0_gc = (0x06<<0), /* AC0 OUT input source */ - CCL_INSEL2_USART2_gc = (0x08<<0), /* USART2 TXD input source */ - CCL_INSEL2_SPI0_gc = (0x09<<0), /* SPI0 SCK input source */ - CCL_INSEL2_TCA0_gc = (0x0A<<0), /* TCA0 WO2 input source */ - CCL_INSEL2_TCB2_gc = (0x0C<<0), /* TCB2 WO input source */ - CCL_INSEL2_TCD0_gc = (0x0D<<0), /* TCD0 WOC input source */ -} CCL_INSEL2_t; - -/* Interrupt Mode for LUT0 select */ -typedef enum CCL_INTMODE0_enum -{ - CCL_INTMODE0_BOTH_gc = (0x00<<0), /* Sense both edges */ - CCL_INTMODE0_FALLING_gc = (0x01<<0), /* Sense falling edge */ - CCL_INTMODE0_RISING_gc = (0x02<<0), /* Sense rising edge */ - CCL_INTMODE0_INTDISABLE_gc = (0x03<<0), /* Interrupt disabled */ -} CCL_INTMODE0_t; - -/* Interrupt Mode for LUT1 select */ -typedef enum CCL_INTMODE1_enum -{ - CCL_INTMODE1_BOTH_gc = (0x00<<2), /* Sense both edges */ - CCL_INTMODE1_FALLING_gc = (0x01<<2), /* Sense falling edge */ - CCL_INTMODE1_RISING_gc = (0x02<<2), /* Sense rising edge */ - CCL_INTMODE1_INTDISABLE_gc = (0x03<<2), /* Interrupt disabled */ -} CCL_INTMODE1_t; - -/* Interrupt Mode for LUT2 select */ -typedef enum CCL_INTMODE2_enum -{ - CCL_INTMODE2_BOTH_gc = (0x00<<4), /* Sense both edges */ - CCL_INTMODE2_FALLING_gc = (0x01<<4), /* Sense falling edge */ - CCL_INTMODE2_RISING_gc = (0x02<<4), /* Sense rising edge */ - CCL_INTMODE2_INTDISABLE_gc = (0x03<<4), /* Interrupt disabled */ -} CCL_INTMODE2_t; - -/* Interrupt Mode for LUT3 select */ -typedef enum CCL_INTMODE3_enum -{ - CCL_INTMODE3_BOTH_gc = (0x00<<6), /* Sense both edges */ - CCL_INTMODE3_FALLING_gc = (0x01<<6), /* Sense falling edge */ - CCL_INTMODE3_RISING_gc = (0x02<<6), /* Sense rising edge */ - CCL_INTMODE3_INTDISABLE_gc = (0x03<<6), /* Interrupt disabled */ -} CCL_INTMODE3_t; - -/* Sequential Selection select */ -typedef enum CCL_SEQSEL_enum -{ - CCL_SEQSEL_DISABLE_gc = (0x00<<0), /* Sequential logic disabled */ - CCL_SEQSEL_DFF_gc = (0x01<<0), /* D FlipFlop */ - CCL_SEQSEL_JK_gc = (0x02<<0), /* JK FlipFlop */ - CCL_SEQSEL_LATCH_gc = (0x03<<0), /* D Latch */ - CCL_SEQSEL_RS_gc = (0x04<<0), /* RS Latch */ -} CCL_SEQSEL_t; - -/* --------------------------------------------------------------------------- -CLKCTRL - Clock controller --------------------------------------------------------------------------- -*/ - -/* Clock controller */ -typedef struct CLKCTRL_struct -{ - register8_t MCLKCTRLA; /* MCLK Control A */ - register8_t MCLKCTRLB; /* MCLK Control B */ - register8_t MCLKLOCK; /* MCLK Lock */ - register8_t MCLKSTATUS; /* MCLK Status */ - register8_t reserved_0x04; - register8_t reserved_0x05; - register8_t reserved_0x06; - register8_t reserved_0x07; - register8_t reserved_0x08; - register8_t reserved_0x09; - register8_t reserved_0x0A; - register8_t reserved_0x0B; - register8_t reserved_0x0C; - register8_t reserved_0x0D; - register8_t reserved_0x0E; - register8_t reserved_0x0F; - register8_t OSC20MCTRLA; /* OSC20M Control A */ - register8_t OSC20MCALIBA; /* OSC20M Calibration A */ - register8_t OSC20MCALIBB; /* OSC20M Calibration B */ - register8_t reserved_0x13; - register8_t reserved_0x14; - register8_t reserved_0x15; - register8_t reserved_0x16; - register8_t reserved_0x17; - register8_t OSC32KCTRLA; /* OSC32K Control A */ - register8_t OSC32KCALIB; /* OSC32K Calibration */ - register8_t reserved_0x1A; - register8_t reserved_0x1B; - register8_t XOSC32KCTRLA; /* XOSC32K Control A */ - register8_t reserved_0x1D; - register8_t reserved_0x1E; - register8_t reserved_0x1F; -} CLKCTRL_t; - -/* clock select select */ -typedef enum CLKCTRL_CLKSEL_enum -{ - CLKCTRL_CLKSEL_OSC20M_gc = (0x00<<0), /* 20MHz oscillator */ - CLKCTRL_CLKSEL_OSCULP32K_gc = (0x01<<0), /* 32KHz oscillator */ - CLKCTRL_CLKSEL_XOSC32K_gc = (0x02<<0), /* 32.768kHz crystal oscillator */ - CLKCTRL_CLKSEL_EXTCLK_gc = (0x03<<0), /* External clock */ -} CLKCTRL_CLKSEL_t; - -/* Crystal startup time select */ -typedef enum CLKCTRL_CSUT_enum -{ - CLKCTRL_CSUT_1K_gc = (0x00<<4), /* 1k cycles */ - CLKCTRL_CSUT_16K_gc = (0x01<<4), /* 16k cycles */ - CLKCTRL_CSUT_32K_gc = (0x02<<4), /* 32k cycles */ - CLKCTRL_CSUT_64K_gc = (0x03<<4), /* 64k cycles */ -} CLKCTRL_CSUT_t; - -/* Prescaler division select */ -typedef enum CLKCTRL_PDIV_enum -{ - CLKCTRL_PDIV_2X_gc = (0x00<<1), /* 2X */ - CLKCTRL_PDIV_4X_gc = (0x01<<1), /* 4X */ - CLKCTRL_PDIV_8X_gc = (0x02<<1), /* 8X */ - CLKCTRL_PDIV_16X_gc = (0x03<<1), /* 16X */ - CLKCTRL_PDIV_32X_gc = (0x04<<1), /* 32X */ - CLKCTRL_PDIV_64X_gc = (0x05<<1), /* 64X */ - CLKCTRL_PDIV_6X_gc = (0x08<<1), /* 6X */ - CLKCTRL_PDIV_10X_gc = (0x09<<1), /* 10X */ - CLKCTRL_PDIV_12X_gc = (0x0A<<1), /* 12X */ - CLKCTRL_PDIV_24X_gc = (0x0B<<1), /* 24X */ - CLKCTRL_PDIV_48X_gc = (0x0C<<1), /* 48X */ -} CLKCTRL_PDIV_t; - -/* --------------------------------------------------------------------------- -CPU - CPU --------------------------------------------------------------------------- -*/ - -/* CCP signature select */ -typedef enum CCP_enum -{ - CCP_SPM_gc = (0x9D<<0), /* SPM Instruction Protection */ - CCP_IOREG_gc = (0xD8<<0), /* IO Register Protection */ -} CCP_t; - -/* --------------------------------------------------------------------------- -CPUINT - Interrupt Controller --------------------------------------------------------------------------- -*/ - -/* Interrupt Controller */ -typedef struct CPUINT_struct -{ - register8_t CTRLA; /* Control A */ - register8_t STATUS; /* Status */ - register8_t LVL0PRI; /* Interrupt Level 0 Priority */ - register8_t LVL1VEC; /* Interrupt Level 1 Priority Vector */ -} CPUINT_t; - - -/* --------------------------------------------------------------------------- -CRCSCAN - CRCSCAN --------------------------------------------------------------------------- -*/ - -/* CRCSCAN */ -typedef struct CRCSCAN_struct -{ - register8_t CTRLA; /* Control A */ - register8_t CTRLB; /* Control B */ - register8_t STATUS; /* Status */ - register8_t reserved_0x03; -} CRCSCAN_t; - -/* CRC Flash Access Mode select */ -typedef enum CRCSCAN_MODE_enum -{ - CRCSCAN_MODE_PRIORITY_gc = (0x00<<4), /* Priority to flash */ - CRCSCAN_MODE_RESERVED_gc = (0x01<<4), /* Reserved */ - CRCSCAN_MODE_BACKGROUND_gc = (0x02<<4), /* Lowest priority to flash */ - CRCSCAN_MODE_CONTINUOUS_gc = (0x03<<4), /* Continuous checks in background */ -} CRCSCAN_MODE_t; - -/* CRC Source select */ -typedef enum CRCSCAN_SRC_enum -{ - CRCSCAN_SRC_FLASH_gc = (0x00<<0), /* CRC on entire flash */ - CRCSCAN_SRC_APPLICATION_gc = (0x01<<0), /* CRC on boot and appl section of flash */ - CRCSCAN_SRC_BOOT_gc = (0x02<<0), /* CRC on boot section of flash */ -} CRCSCAN_SRC_t; - -/* --------------------------------------------------------------------------- -EVSYS - Event System --------------------------------------------------------------------------- -*/ - -/* Event System */ -typedef struct EVSYS_struct -{ - register8_t STROBE; /* Channel Strobe */ - register8_t reserved_0x01; - register8_t reserved_0x02; - register8_t reserved_0x03; - register8_t reserved_0x04; - register8_t reserved_0x05; - register8_t reserved_0x06; - register8_t reserved_0x07; - register8_t reserved_0x08; - register8_t reserved_0x09; - register8_t reserved_0x0A; - register8_t reserved_0x0B; - register8_t reserved_0x0C; - register8_t reserved_0x0D; - register8_t reserved_0x0E; - register8_t reserved_0x0F; - register8_t CHANNEL0; /* Multiplexer Channel 0 */ - register8_t CHANNEL1; /* Multiplexer Channel 1 */ - register8_t CHANNEL2; /* Multiplexer Channel 2 */ - register8_t CHANNEL3; /* Multiplexer Channel 3 */ - register8_t CHANNEL4; /* Multiplexer Channel 4 */ - register8_t CHANNEL5; /* Multiplexer Channel 5 */ - register8_t reserved_0x16; - register8_t reserved_0x17; - register8_t reserved_0x18; - register8_t reserved_0x19; - register8_t reserved_0x1A; - register8_t reserved_0x1B; - register8_t reserved_0x1C; - register8_t reserved_0x1D; - register8_t reserved_0x1E; - register8_t reserved_0x1F; - register8_t USERCCLLUT0A; /* User CCL LUT0 Event A */ - register8_t USERCCLLUT0B; /* User CCL LUT0 Event B */ - register8_t USERCCLLUT1A; /* User CCL LUT1 Event A */ - register8_t USERCCLLUT1B; /* User CCL LUT1 Event B */ - register8_t USERCCLLUT2A; /* User CCL LUT2 Event A */ - register8_t USERCCLLUT2B; /* User CCL LUT2 Event B */ - register8_t USERCCLLUT3A; /* User CCL LUT3 Event A */ - register8_t USERCCLLUT3B; /* User CCL LUT3 Event B */ - register8_t USERADC0; /* User ADC0 */ - register8_t USEREVOUTA; /* User EVOUT Port A */ - register8_t USEREVOUTB; /* User EVOUT Port B */ - register8_t USEREVOUTC; /* User EVOUT Port C */ - register8_t USEREVOUTD; /* User EVOUT Port D */ - register8_t USEREVOUTE; /* User EVOUT Port E */ - register8_t USEREVOUTF; /* User EVOUT Port F */ - register8_t USERUSART0; /* User USART0 */ - register8_t USERUSART1; /* User USART1 */ - register8_t USERUSART2; /* User USART2 */ - register8_t USERUSART3; /* User USART3 */ - register8_t USERTCA0; /* User TCA0 */ - register8_t USERTCB0; /* User TCB0 */ - register8_t USERTCB1; /* User TCB1 */ - register8_t USERTCB2; /* User TCB2 */ - register8_t USERTCB3; /* User TCB3 */ - register8_t reserved_0x38; - register8_t reserved_0x39; - register8_t reserved_0x3A; - register8_t reserved_0x3B; - register8_t reserved_0x3C; - register8_t reserved_0x3D; - register8_t reserved_0x3E; - register8_t reserved_0x3F; -} EVSYS_t; - -/* Channel selector select */ -typedef enum EVSYS_CHANNEL_enum -{ - EVSYS_CHANNEL_OFF_gc = (0x00<<0), /* Off */ - EVSYS_CHANNEL_CHANNEL0_gc = (0x01<<0), /* Connect user to event channel 0 */ - EVSYS_CHANNEL_CHANNEL1_gc = (0x02<<0), /* Connect user to event channel 1 */ - EVSYS_CHANNEL_CHANNEL2_gc = (0x03<<0), /* Connect user to event channel 2 */ - EVSYS_CHANNEL_CHANNEL3_gc = (0x04<<0), /* Connect user to event channel 3 */ - EVSYS_CHANNEL_CHANNEL4_gc = (0x05<<0), /* Connect user to event channel 4 */ - EVSYS_CHANNEL_CHANNEL5_gc = (0x06<<0), /* Connect user to event channel 5 */ -} EVSYS_CHANNEL_t; - -/* Generator selector select */ -typedef enum EVSYS_GENERATOR_enum -{ - EVSYS_GENERATOR_OFF_gc = (0x00<<0), /* Off */ - EVSYS_GENERATOR_UPDI_gc = (0x01<<0), /* Unified Program and Debug Interface */ - EVSYS_GENERATOR_CCL_LUT0_gc = (0x10<<0), /* Configurable Custom Logic LUT0 */ - EVSYS_GENERATOR_CCL_LUT1_gc = (0x11<<0), /* Configurable Custom Logic LUT1 */ - EVSYS_GENERATOR_CCL_LUT2_gc = (0x12<<0), /* Configurable Custom Logic LUT2 */ - EVSYS_GENERATOR_CCL_LUT3_gc = (0x13<<0), /* Configurable Custom Logic LUT3 */ - EVSYS_GENERATOR_OSC_TEST_gc = (0x02<<0), /* Oscillator test event */ - EVSYS_GENERATOR_AC0_OUT_gc = (0x20<<0), /* Analog Comparator 0 out */ - EVSYS_GENERATOR_ADC0_COMP_gc = (0x24<<0), /* ADC 0 Comparator Event */ - EVSYS_GENERATOR_PORT0_PIN0_gc = (0x40<<0), /* Port 0 Pin 0 */ - EVSYS_GENERATOR_PORT0_PIN1_gc = (0x41<<0), /* Port 0 Pin 1 */ - EVSYS_GENERATOR_PORT0_PIN2_gc = (0x42<<0), /* Port 0 Pin 2 */ - EVSYS_GENERATOR_PORT0_PIN3_gc = (0x43<<0), /* Port 0 Pin 3 */ - EVSYS_GENERATOR_PORT0_PIN4_gc = (0x44<<0), /* Port 0 Pin 4 */ - EVSYS_GENERATOR_PORT0_PIN5_gc = (0x45<<0), /* Port 0 Pin 5 */ - EVSYS_GENERATOR_PORT0_PIN6_gc = (0x46<<0), /* Port 0 Pin 6 */ - EVSYS_GENERATOR_PORT0_PIN7_gc = (0x47<<0), /* Port 0 Pin 7 */ - EVSYS_GENERATOR_PORT1_PIN0_gc = (0x48<<0), /* Port 1 Pin 0 */ - EVSYS_GENERATOR_PORT1_PIN1_gc = (0x49<<0), /* Port 1 Pin 1 */ - EVSYS_GENERATOR_PORT1_PIN2_gc = (0x4A<<0), /* Port 1 Pin 2 */ - EVSYS_GENERATOR_PORT1_PIN3_gc = (0x4B<<0), /* Port 1 Pin 3 */ - EVSYS_GENERATOR_PORT1_PIN4_gc = (0x4C<<0), /* Port 1 Pin 4 */ - EVSYS_GENERATOR_PORT1_PIN5_gc = (0x4D<<0), /* Port 1 Pin 5 */ - EVSYS_GENERATOR_PORT1_PIN6_gc = (0x4E<<0), /* Port 1 Pin 6 */ - EVSYS_GENERATOR_PORT1_PIN7_gc = (0x4F<<0), /* Port 1 Pin 7 */ - EVSYS_GENERATOR_RTC_OVF_gc = (0x06<<0), /* Real Time Counter overflow */ - EVSYS_GENERATOR_USART0_XCK_gc = (0x60<<0), /* USART 0 Xclock */ - EVSYS_GENERATOR_USART1_XCK_gc = (0x61<<0), /* USART 1 Xclock */ - EVSYS_GENERATOR_USART2_XCK_gc = (0x62<<0), /* USART 2 Xclock */ - EVSYS_GENERATOR_USART3_XCK_gc = (0x63<<0), /* USART 3 Xclock */ - EVSYS_GENERATOR_SPI0_SCK_gc = (0x68<<0), /* SPI 0 Sclock */ - EVSYS_GENERATOR_RTC_CMP_gc = (0x07<<0), /* Real Time Counter compare */ - EVSYS_GENERATOR_RTC_PIT0_gc = (0x08<<0), /* Periodic Interrupt Timer output 0 */ - EVSYS_GENERATOR_TCA0_OVF_gc = (0x80<<0), /* Timer/Counter A0 overflow */ - EVSYS_GENERATOR_TCA0_ERR_gc = (0x81<<0), /* Timer/Counter A0 error */ - EVSYS_GENERATOR_TCA0_CMP0_gc = (0x84<<0), /* Timer/Counter A0 compare 0 */ - EVSYS_GENERATOR_TCA0_CMP1_gc = (0x85<<0), /* Timer/Counter A0 compare 1 */ - EVSYS_GENERATOR_TCA0_CMP2_gc = (0x86<<0), /* Timer/Counter A0 compare 2 */ - EVSYS_GENERATOR_RTC_PIT1_gc = (0x09<<0), /* Periodic Interrupt Timer output 1 */ - EVSYS_GENERATOR_RTC_PIT2_gc = (0x0A<<0), /* Periodic Interrupt Timer output 2 */ - EVSYS_GENERATOR_TCB0_CMP0_gc = (0xA0<<0), /* Timer/Counter B0 compare 0 */ - EVSYS_GENERATOR_TCB1_CMP0_gc = (0xA2<<0), /* Timer/Counter B1 compare 0 */ - EVSYS_GENERATOR_TCB2_CMP0_gc = (0xA4<<0), /* Timer/Counter B2 compare 0 */ - EVSYS_GENERATOR_TCB3_CMP0_gc = (0xA6<<0), /* Timer/Counter B3 compare 0 */ - EVSYS_GENERATOR_RTC_PIT3_gc = (0x0B<<0), /* Periodic Interrupt Timer output 3 */ -} EVSYS_GENERATOR_t; - -/* Software event on channels select */ -typedef enum EVSYS_STROBE0_enum -{ - EVSYS_STROBE0_EV_STROBE_CH0_gc = (0x01<<0), /* */ - EVSYS_STROBE0_EV_STROBE_CH1_gc = (0x02<<0), /* */ - EVSYS_STROBE0_EV_STROBE_CH2_gc = (0x04<<0), /* */ - EVSYS_STROBE0_EV_STROBE_CH3_gc = (0x08<<0), /* */ - EVSYS_STROBE0_EV_STROBE_CH4_gc = (0x10<<0), /* */ - EVSYS_STROBE0_EV_STROBE_CH5_gc = (0x20<<0), /* */ - EVSYS_STROBE0_EV_STROBE_CH6_gc = (0x40<<0), /* */ - EVSYS_STROBE0_EV_STROBE_CH7_gc = (0x80<<0), /* */ -} EVSYS_STROBE0_t; - -/* --------------------------------------------------------------------------- -FUSE - Fuses --------------------------------------------------------------------------- -*/ - -/* Fuses */ -typedef struct FUSE_struct -{ - register8_t WDTCFG; /* Watchdog Configuration */ - register8_t BODCFG; /* BOD Configuration */ - register8_t OSCCFG; /* Oscillator Configuration */ - register8_t reserved_0x03; - register8_t TCD0CFG; /* TCD0 Configuration */ - register8_t SYSCFG0; /* System Configuration 0 */ - register8_t SYSCFG1; /* System Configuration 1 */ - register8_t APPEND; /* Application Code Section End */ - register8_t BOOTEND; /* Boot Section End */ - register8_t reserved_0x09; -} FUSE_t; - - -/* avr-libc typedef for avr/fuse.h */ -typedef FUSE_t NVM_FUSES_t; - -/* BOD Operation in Active Mode select */ -typedef enum ACTIVE_enum -{ - ACTIVE_DIS_gc = (0x00<<2), /* Disabled */ - ACTIVE_ENABLED_gc = (0x01<<2), /* Enabled */ - ACTIVE_SAMPLED_gc = (0x02<<2), /* Sampled */ - ACTIVE_ENWAKE_gc = (0x03<<2), /* Enabled with wake-up halted until BOD is ready */ -} ACTIVE_t; - -/* CRC Source select */ -typedef enum CRCSRC_enum -{ - CRCSRC_FLASH_gc = (0x00<<6), /* The CRC is performed on the entire Flash (boot, application code and application data section). */ - CRCSRC_BOOT_gc = (0x01<<6), /* The CRC is performed on the boot section of Flash */ - CRCSRC_BOOTAPP_gc = (0x02<<6), /* The CRC is performed on the boot and application code section of Flash */ - CRCSRC_NOCRC_gc = (0x03<<6), /* Disable CRC. */ -} CRCSRC_t; - -/* Frequency Select select */ -typedef enum FREQSEL_enum -{ - FREQSEL_16MHZ_gc = (0x01<<0), /* 16 MHz */ - FREQSEL_20MHZ_gc = (0x02<<0), /* 20 MHz */ -} FREQSEL_t; - -/* BOD Level select */ -typedef enum LVL_enum -{ - LVL_BODLEVEL0_gc = (0x00<<5), /* 1.8 V */ - LVL_BODLEVEL1_gc = (0x01<<5), /* 2.1 V */ - LVL_BODLEVEL2_gc = (0x02<<5), /* 2.6 V */ - LVL_BODLEVEL3_gc = (0x03<<5), /* 2.9 V */ - LVL_BODLEVEL4_gc = (0x04<<5), /* 3.3 V */ - LVL_BODLEVEL5_gc = (0x05<<5), /* 3.7 V */ - LVL_BODLEVEL6_gc = (0x06<<5), /* 4.0 V */ - LVL_BODLEVEL7_gc = (0x07<<5), /* 4.2 V */ -} LVL_t; - -/* Watchdog Timeout Period select */ -typedef enum PERIOD_enum -{ - PERIOD_OFF_gc = (0x00<<0), /* Off */ - PERIOD_8CLK_gc = (0x01<<0), /* 8 cycles (8ms) */ - PERIOD_16CLK_gc = (0x02<<0), /* 16 cycles (16ms) */ - PERIOD_32CLK_gc = (0x03<<0), /* 32 cycles (32ms) */ - PERIOD_64CLK_gc = (0x04<<0), /* 64 cycles (64ms) */ - PERIOD_128CLK_gc = (0x05<<0), /* 128 cycles (0.128s) */ - PERIOD_256CLK_gc = (0x06<<0), /* 256 cycles (0.256s) */ - PERIOD_512CLK_gc = (0x07<<0), /* 512 cycles (0.512s) */ - PERIOD_1KCLK_gc = (0x08<<0), /* 1K cycles (1.0s) */ - PERIOD_2KCLK_gc = (0x09<<0), /* 2K cycles (2.0s) */ - PERIOD_4KCLK_gc = (0x0A<<0), /* 4K cycles (4.1s) */ - PERIOD_8KCLK_gc = (0x0B<<0), /* 8K cycles (8.2s) */ -} PERIOD_t; - -/* Reset Pin Configuration select */ -typedef enum RSTPINCFG_enum -{ - RSTPINCFG_GPIO_gc = (0x00<<2), /* GPIO mode */ - RSTPINCFG_UPDI_gc = (0x01<<2), /* UPDI mode */ - RSTPINCFG_RST_gc = (0x02<<2), /* Reset mode */ - RSTPINCFG_PDIRST_gc = (0x03<<2), /* PDI on PDI pad, reset on alternative reset pad */ -} RSTPINCFG_t; - -/* BOD Sample Frequency select */ -typedef enum SAMPFREQ_enum -{ - SAMPFREQ_1KHZ_gc = (0x00<<4), /* 1kHz sampling frequency */ - SAMPFREQ_125HZ_gc = (0x01<<4), /* 125kHz sampling frequency */ -} SAMPFREQ_t; - -/* BOD Operation in Sleep Mode select */ -typedef enum SLEEP_enum -{ - SLEEP_DIS_gc = (0x00<<0), /* Disabled */ - SLEEP_ENABLED_gc = (0x01<<0), /* Enabled */ - SLEEP_SAMPLED_gc = (0x02<<0), /* Sampled */ -} SLEEP_t; - -/* Startup Time select */ -typedef enum SUT_enum -{ - SUT_0MS_gc = (0x00<<0), /* 0 ms */ - SUT_1MS_gc = (0x01<<0), /* 1 ms */ - SUT_2MS_gc = (0x02<<0), /* 2 ms */ - SUT_4MS_gc = (0x03<<0), /* 4 ms */ - SUT_8MS_gc = (0x04<<0), /* 8 ms */ - SUT_16MS_gc = (0x05<<0), /* 16 ms */ - SUT_32MS_gc = (0x06<<0), /* 32 ms */ - SUT_64MS_gc = (0x07<<0), /* 64 ms */ -} SUT_t; - -/* Watchdog Window Timeout Period select */ -typedef enum WINDOW_enum -{ - WINDOW_OFF_gc = (0x00<<4), /* Off */ - WINDOW_8CLK_gc = (0x01<<4), /* 8 cycles (8ms) */ - WINDOW_16CLK_gc = (0x02<<4), /* 16 cycles (16ms) */ - WINDOW_32CLK_gc = (0x03<<4), /* 32 cycles (32ms) */ - WINDOW_64CLK_gc = (0x04<<4), /* 64 cycles (64ms) */ - WINDOW_128CLK_gc = (0x05<<4), /* 128 cycles (0.128s) */ - WINDOW_256CLK_gc = (0x06<<4), /* 256 cycles (0.256s) */ - WINDOW_512CLK_gc = (0x07<<4), /* 512 cycles (0.512s) */ - WINDOW_1KCLK_gc = (0x08<<4), /* 1K cycles (1.0s) */ - WINDOW_2KCLK_gc = (0x09<<4), /* 2K cycles (2.0s) */ - WINDOW_4KCLK_gc = (0x0A<<4), /* 4K cycles (4.1s) */ - WINDOW_8KCLK_gc = (0x0B<<4), /* 8K cycles (8.2s) */ -} WINDOW_t; - -/* --------------------------------------------------------------------------- -LOCKBIT - Lockbit --------------------------------------------------------------------------- -*/ - -/* Lockbit */ -typedef struct LOCKBIT_struct -{ - register8_t LOCKBIT; /* Lock Bits */ - register8_t reserved_0x01; -} LOCKBIT_t; - -/* Lock Bits select */ -typedef enum LB_enum -{ - LB_RWLOCK_gc = (0x3A<<0), /* Read and write lock */ - LB_NOLOCK_gc = (0xC5<<0), /* No locks */ -} LB_t; - -/* --------------------------------------------------------------------------- -NVMBIST - BIST in the NVMCTRL module --------------------------------------------------------------------------- -*/ - -/* BIST in the NVMCTRL module */ -typedef struct NVMBIST_struct -{ - register8_t CTRLA; /* Control A */ - register8_t ADDRPAT; /* Address pattern */ - register8_t DATAPAT; /* Data pattern */ - register8_t STATUS; /* Status */ - _WORDREGISTER(CNT); /* */ - _DWORDREGISTER(END); /* */ - register8_t reserved_0x0A; - register8_t reserved_0x0B; - register8_t reserved_0x0C; - register8_t reserved_0x0D; - register8_t reserved_0x0E; - register8_t reserved_0x0F; -} NVMBIST_t; - -/* Address mode select */ -typedef enum NVMBIST_AMODE_enum -{ - NVMBIST_AMODE_NORMAL_gc = (0x00<<4), /* No special address pattern */ - NVMBIST_AMODE_COMPLEMENT_gc = (0x04<<4), /* Post complement address */ -} NVMBIST_AMODE_t; - -/* Command select */ -typedef enum NVMBIST_CMD_enum -{ - NVMBIST_CMD_NOCMD_gc = (0x00<<0), /* No effect */ - NVMBIST_CMD_START_gc = (0x01<<0), /* Start BIST testing */ - NVMBIST_CMD_RESTART_gc = (0x02<<0), /* Re-start BIST testing */ - NVMBIST_CMD_BREAK_gc = (0x03<<0), /* Stop BIST and go to BREAK state */ -} NVMBIST_CMD_t; - -/* Data check pattern select */ -typedef enum NVMBIST_PATTERN_enum -{ - NVMBIST_PATTERN_ZEROES_gc = (0x00<<0), /* All flash programmed */ - NVMBIST_PATTERN_CHECK_gc = (0x01<<0), /* Physical checkerboard in flash */ - NVMBIST_PATTERN_INVCHECK_gc = (0x02<<0), /* Inverse physical checkerboard in flash */ - NVMBIST_PATTERN_ONES_gc = (0x03<<0), /* All flash unprogrammed */ -} NVMBIST_PATTERN_t; - -/* FSM State select */ -typedef enum NVMBIST_STATE_enum -{ - NVMBIST_STATE_IDLE_gc = (0x00<<0), /* Reset state */ - NVMBIST_STATE_BREAK_gc = (0x01<<0), /* Break command used */ - NVMBIST_STATE_FAILED0_gc = (0x04<<0), /* Test failed, data from last address */ - NVMBIST_STATE_FAILED1_gc = (0x05<<0), /* Test failed, data from address-1 */ - NVMBIST_STATE_FAILED2_gc = (0x06<<0), /* Test failed, data from address-2 */ - NVMBIST_STATE_SUCCESS_gc = (0x07<<0), /* Test success */ - NVMBIST_STATE_START0_gc = (0x08<<0), /* Startup, fetching first data */ - NVMBIST_STATE_START1_gc = (0x09<<0), /* Startup, fetching second data */ - NVMBIST_STATE_RESTART0_gc = (0x0A<<0), /* Re-start from BREAK or FAILED2 */ - NVMBIST_STATE_RESTART1_gc = (0x0B<<0), /* Re-start from FAILED1 */ - NVMBIST_STATE_RUNNING_gc = (0x0C<<0), /* Test running */ - NVMBIST_STATE_FINISH0_gc = (0x0E<<0), /* Check last word */ - NVMBIST_STATE_FINISH1_gc = (0x0F<<0), /* Count faults in last word */ -} NVMBIST_STATE_t; - -/* X address mode select */ -typedef enum NVMBIST_XMODE_enum -{ - NVMBIST_XMODE_STATIC_gc = (0x00<<0), /* X static */ - NVMBIST_XMODE_CARRY_gc = (0x01<<0), /* Carry/borrow from Y */ - NVMBIST_XMODE_INC_gc = (0x02<<0), /* X increment each cycle */ - NVMBIST_XMODE_DEC_gc = (0x03<<0), /* X decrement each cycle */ -} NVMBIST_XMODE_t; - -/* Y address mode select */ -typedef enum NVMBIST_YMODE_enum -{ - NVMBIST_YMODE_STATIC_gc = (0x00<<2), /* Y static */ - NVMBIST_YMODE_CARRY_gc = (0x01<<2), /* Carry/borrow from X */ - NVMBIST_YMODE_INC_gc = (0x02<<2), /* Y increment each cycle */ - NVMBIST_YMODE_DEC_gc = (0x03<<2), /* Y decrement each cycle */ -} NVMBIST_YMODE_t; - -/* --------------------------------------------------------------------------- -NVMCTRL - Non-volatile Memory Controller --------------------------------------------------------------------------- -*/ - -/* Non-volatile Memory Controller */ -typedef struct NVMCTRL_struct -{ - register8_t CTRLA; /* Control A */ - register8_t CTRLB; /* Control B */ - register8_t STATUS; /* Status */ - register8_t INTCTRL; /* Interrupt Control */ - register8_t INTFLAGS; /* Interrupt Flags */ - register8_t reserved_0x05; - _WORDREGISTER(DATA); /* Data */ - _WORDREGISTER(ADDR); /* Address */ - register8_t reserved_0x0A; - register8_t reserved_0x0B; - register8_t reserved_0x0C; - register8_t reserved_0x0D; - register8_t reserved_0x0E; - register8_t reserved_0x0F; -} NVMCTRL_t; - -/* Command select */ -typedef enum NVMCTRL_CMD_enum -{ - NVMCTRL_CMD_NONE_gc = (0x00<<0), /* No Command */ - NVMCTRL_CMD_PAGEWRITE_gc = (0x01<<0), /* Write page */ - NVMCTRL_CMD_PAGEERASE_gc = (0x02<<0), /* Erase page */ - NVMCTRL_CMD_PAGEERASEWRITE_gc = (0x03<<0), /* Erase and write page */ - NVMCTRL_CMD_PAGEBUFCLR_gc = (0x04<<0), /* Page buffer clear */ - NVMCTRL_CMD_CHIPERASE_gc = (0x05<<0), /* Chip erase */ - NVMCTRL_CMD_EEERASE_gc = (0x06<<0), /* EEPROM erase */ - NVMCTRL_CMD_FUSEWRITE_gc = (0x07<<0), /* Write fuse (PDI only) */ -} NVMCTRL_CMD_t; - -/* --------------------------------------------------------------------------- -PORT - I/O Ports --------------------------------------------------------------------------- -*/ - -/* I/O Ports */ -typedef struct PORT_struct -{ - register8_t DIR; /* Data Direction */ - register8_t DIRSET; /* Data Direction Set */ - register8_t DIRCLR; /* Data Direction Clear */ - register8_t DIRTGL; /* Data Direction Toggle */ - register8_t OUT; /* Output Value */ - register8_t OUTSET; /* Output Value Set */ - register8_t OUTCLR; /* Output Value Clear */ - register8_t OUTTGL; /* Output Value Toggle */ - register8_t IN; /* Input Value */ - register8_t INTFLAGS; /* Interrupt Flags */ - register8_t PORTCTRL; /* Port Control */ - register8_t reserved_0x0B; - register8_t reserved_0x0C; - register8_t reserved_0x0D; - register8_t reserved_0x0E; - register8_t reserved_0x0F; - register8_t PIN0CTRL; /* Pin 0 Control */ - register8_t PIN1CTRL; /* Pin 1 Control */ - register8_t PIN2CTRL; /* Pin 2 Control */ - register8_t PIN3CTRL; /* Pin 3 Control */ - register8_t PIN4CTRL; /* Pin 4 Control */ - register8_t PIN5CTRL; /* Pin 5 Control */ - register8_t PIN6CTRL; /* Pin 6 Control */ - register8_t PIN7CTRL; /* Pin 7 Control */ - register8_t reserved_0x18; - register8_t reserved_0x19; - register8_t reserved_0x1A; - register8_t reserved_0x1B; - register8_t reserved_0x1C; - register8_t reserved_0x1D; - register8_t reserved_0x1E; - register8_t reserved_0x1F; -} PORT_t; - -/* Input/Sense Configuration select */ -typedef enum PORT_ISC_enum -{ - PORT_ISC_INTDISABLE_gc = (0x00<<0), /* Interrupt disabled but input buffer enabled */ - PORT_ISC_BOTHEDGES_gc = (0x01<<0), /* Sense Both Edges */ - PORT_ISC_RISING_gc = (0x02<<0), /* Sense Rising Edge */ - PORT_ISC_FALLING_gc = (0x03<<0), /* Sense Falling Edge */ - PORT_ISC_INPUT_DISABLE_gc = (0x04<<0), /* Digital Input Buffer disabled */ - PORT_ISC_LEVEL_gc = (0x05<<0), /* Sense low Level */ -} PORT_ISC_t; - -/* --------------------------------------------------------------------------- -PORTMUX - Port Multiplexer --------------------------------------------------------------------------- -*/ - -/* Port Multiplexer */ -typedef struct PORTMUX_struct -{ - register8_t EVSYSROUTEA; /* Port Multiplexer EVSYS */ - register8_t CCLROUTEA; /* Port Multiplexer CCL */ - register8_t USARTROUTEA; /* Port Multiplexer USART register A */ - register8_t TWISPIROUTEA; /* Port Multiplexer TWI and SPI */ - register8_t TCAROUTEA; /* Port Multiplexer TCA */ - register8_t TCBROUTEA; /* Port Multiplexer TCB */ - register8_t reserved_0x06; - register8_t reserved_0x07; - register8_t reserved_0x08; - register8_t reserved_0x09; - register8_t reserved_0x0A; - register8_t reserved_0x0B; - register8_t reserved_0x0C; - register8_t reserved_0x0D; - register8_t reserved_0x0E; - register8_t reserved_0x0F; -} PORTMUX_t; - -/* Port Multiplexer SPI0 select */ -typedef enum PORTMUX_SPI0_enum -{ - PORTMUX_SPI0_DEFAULT_gc = (0x00<<0), /* SPI0 on PA[7:4] */ - PORTMUX_SPI0_ALT1_gc = (0x01<<0), /* SPI0 on PC[3:0] */ - PORTMUX_SPI0_ALT2_gc = (0x02<<0), /* SPI0 on PE[3:0] */ - PORTMUX_SPI0_NONE_gc = (0x03<<0), /* Not connected to any pins */ -} PORTMUX_SPI0_t; - -/* Port Multiplexer TCA0 select */ -typedef enum PORTMUX_TCA0_enum -{ - PORTMUX_TCA0_PORTA_gc = (0x00<<0), /* TCA0 pins on PA[5:0] */ - PORTMUX_TCA0_PORTB_gc = (0x01<<0), /* TCA0 pins on PB[5:0] */ - PORTMUX_TCA0_PORTC_gc = (0x02<<0), /* TCA0 pins on PC[5:0] */ - PORTMUX_TCA0_PORTD_gc = (0x03<<0), /* TCA0 pins on PD[5:0] */ - PORTMUX_TCA0_PORTE_gc = (0x04<<0), /* TCA0 pins on PE[5:0] */ - PORTMUX_TCA0_PORTF_gc = (0x05<<0), /* TCA0 pins on PF[5:0] */ -} PORTMUX_TCA0_t; - -/* Port Multiplexer TWI0 select */ -typedef enum PORTMUX_TWI0_enum -{ - PORTMUX_TWI0_DEFAULT_gc = (0x00<<4), /* SCL/SDA on PA[3:2], Slave mode on PC[3:2] in dual TWI mode */ - PORTMUX_TWI0_ALT1_gc = (0x01<<4), /* SCL/SDA on PA[3:2], Slave mode on PF[3:2] in dual TWI mode */ - PORTMUX_TWI0_ALT2_gc = (0x02<<4), /* SCL/SDA on PC[3:2], Slave mode on PF[3:2] in dual TWI mode */ - PORTMUX_TWI0_NONE_gc = (0x03<<4), /* Not connected to any pins */ -} PORTMUX_TWI0_t; - -/* Port Multiplexer USART0 select */ -typedef enum PORTMUX_USART0_enum -{ - PORTMUX_USART0_DEFAULT_gc = (0x00<<0), /* USART0 on PA[3:0] */ - PORTMUX_USART0_ALT1_gc = (0x01<<0), /* USART0 on PA[7:4] */ - PORTMUX_USART0_NONE_gc = (0x03<<0), /* Not connected to any pins */ -} PORTMUX_USART0_t; - -/* Port Multiplexer USART1 select */ -typedef enum PORTMUX_USART1_enum -{ - PORTMUX_USART1_DEFAULT_gc = (0x00<<2), /* USART1 on PC[3:0] */ - PORTMUX_USART1_ALT1_gc = (0x01<<2), /* USART1 on PC[7:4] */ - PORTMUX_USART1_NONE_gc = (0x03<<2), /* Not connected to any pins */ -} PORTMUX_USART1_t; - -/* Port Multiplexer USART2 select */ -typedef enum PORTMUX_USART2_enum -{ - PORTMUX_USART2_DEFAULT_gc = (0x00<<4), /* USART2 on PF[3:0] */ - PORTMUX_USART2_ALT1_gc = (0x01<<4), /* USART2 on PF[5:4] */ - PORTMUX_USART2_NONE_gc = (0x03<<4), /* Not connected to any pins */ -} PORTMUX_USART2_t; - -/* Port Multiplexer USART3 select */ -typedef enum PORTMUX_USART3_enum -{ - PORTMUX_USART3_DEFAULT_gc = (0x00<<6), /* USART3 on PB[3:0] */ - PORTMUX_USART3_ALT1_gc = (0x01<<6), /* USART3 on PB[5:4] */ - PORTMUX_USART3_NONE_gc = (0x03<<6), /* Not connected to any pins */ -} PORTMUX_USART3_t; - -/* --------------------------------------------------------------------------- -RSTCTRL - Reset controller --------------------------------------------------------------------------- -*/ - -/* Reset controller */ -typedef struct RSTCTRL_struct -{ - register8_t RSTFR; /* Reset Flags */ - register8_t SWRR; /* Software Reset */ - register8_t reserved_0x02; - register8_t reserved_0x03; -} RSTCTRL_t; - - -/* --------------------------------------------------------------------------- -RTC - Real-Time Counter --------------------------------------------------------------------------- -*/ - -/* Real-Time Counter */ -typedef struct RTC_struct -{ - register8_t CTRLA; /* Control A */ - register8_t STATUS; /* Status */ - register8_t INTCTRL; /* Interrupt Control */ - register8_t INTFLAGS; /* Interrupt Flags */ - register8_t TEMP; /* Temporary */ - register8_t DBGCTRL; /* Debug control */ - register8_t reserved_0x06; - register8_t CLKSEL; /* Clock Select */ - _WORDREGISTER(CNT); /* Counter */ - _WORDREGISTER(PER); /* Period */ - _WORDREGISTER(CMP); /* Compare */ - register8_t reserved_0x0E; - register8_t reserved_0x0F; - register8_t PITCTRLA; /* PIT Control A */ - register8_t PITSTATUS; /* PIT Status */ - register8_t PITINTCTRL; /* PIT Interrupt Control */ - register8_t PITINTFLAGS; /* PIT Interrupt Flags */ - register8_t reserved_0x14; - register8_t PITDBGCTRL; /* PIT Debug control */ - register8_t reserved_0x16; - register8_t reserved_0x17; - register8_t reserved_0x18; - register8_t reserved_0x19; - register8_t reserved_0x1A; - register8_t reserved_0x1B; - register8_t reserved_0x1C; - register8_t reserved_0x1D; - register8_t reserved_0x1E; - register8_t reserved_0x1F; -} RTC_t; - -/* Clock Select select */ -typedef enum RTC_CLKSEL_enum -{ - RTC_CLKSEL_INT32K_gc = (0x00<<0), /* Internal 32kHz OSC */ - RTC_CLKSEL_INT1K_gc = (0x01<<0), /* Internal 1kHz OSC */ - RTC_CLKSEL_TOSC32K_gc = (0x02<<0), /* 32KHz Crystal OSC */ - RTC_CLKSEL_EXTCLK_gc = (0x03<<0), /* External Clock */ -} RTC_CLKSEL_t; - -/* Period select */ -typedef enum RTC_PERIOD_enum -{ - RTC_PERIOD_OFF_gc = (0x00<<3), /* Off */ - RTC_PERIOD_CYC4_gc = (0x01<<3), /* RTC Clock Cycles 4 */ - RTC_PERIOD_CYC8_gc = (0x02<<3), /* RTC Clock Cycles 8 */ - RTC_PERIOD_CYC16_gc = (0x03<<3), /* RTC Clock Cycles 16 */ - RTC_PERIOD_CYC32_gc = (0x04<<3), /* RTC Clock Cycles 32 */ - RTC_PERIOD_CYC64_gc = (0x05<<3), /* RTC Clock Cycles 64 */ - RTC_PERIOD_CYC128_gc = (0x06<<3), /* RTC Clock Cycles 128 */ - RTC_PERIOD_CYC256_gc = (0x07<<3), /* RTC Clock Cycles 256 */ - RTC_PERIOD_CYC512_gc = (0x08<<3), /* RTC Clock Cycles 512 */ - RTC_PERIOD_CYC1024_gc = (0x09<<3), /* RTC Clock Cycles 1024 */ - RTC_PERIOD_CYC2048_gc = (0x0A<<3), /* RTC Clock Cycles 2048 */ - RTC_PERIOD_CYC4096_gc = (0x0B<<3), /* RTC Clock Cycles 4096 */ - RTC_PERIOD_CYC8192_gc = (0x0C<<3), /* RTC Clock Cycles 8192 */ - RTC_PERIOD_CYC16384_gc = (0x0D<<3), /* RTC Clock Cycles 16384 */ - RTC_PERIOD_CYC32768_gc = (0x0E<<3), /* RTC Clock Cycles 32768 */ -} RTC_PERIOD_t; - -/* Prescaling Factor select */ -typedef enum RTC_PRESCALER_enum -{ - RTC_PRESCALER_DIV1_gc = (0x00<<3), /* RTC Clock / 1 */ - RTC_PRESCALER_DIV2_gc = (0x01<<3), /* RTC Clock / 2 */ - RTC_PRESCALER_DIV4_gc = (0x02<<3), /* RTC Clock / 4 */ - RTC_PRESCALER_DIV8_gc = (0x03<<3), /* RTC Clock / 8 */ - RTC_PRESCALER_DIV16_gc = (0x04<<3), /* RTC Clock / 16 */ - RTC_PRESCALER_DIV32_gc = (0x05<<3), /* RTC Clock / 32 */ - RTC_PRESCALER_DIV64_gc = (0x06<<3), /* RTC Clock / 64 */ - RTC_PRESCALER_DIV128_gc = (0x07<<3), /* RTC Clock / 128 */ - RTC_PRESCALER_DIV256_gc = (0x08<<3), /* RTC Clock / 256 */ - RTC_PRESCALER_DIV512_gc = (0x09<<3), /* RTC Clock / 512 */ - RTC_PRESCALER_DIV1024_gc = (0x0A<<3), /* RTC Clock / 1024 */ - RTC_PRESCALER_DIV2048_gc = (0x0B<<3), /* RTC Clock / 2048 */ - RTC_PRESCALER_DIV4096_gc = (0x0C<<3), /* RTC Clock / 4096 */ - RTC_PRESCALER_DIV8192_gc = (0x0D<<3), /* RTC Clock / 8192 */ - RTC_PRESCALER_DIV16384_gc = (0x0E<<3), /* RTC Clock / 16384 */ - RTC_PRESCALER_DIV32768_gc = (0x0F<<3), /* RTC Clock / 32768 */ -} RTC_PRESCALER_t; - -/* --------------------------------------------------------------------------- -SIGROW - Signature row --------------------------------------------------------------------------- -*/ - -/* Signature row */ -typedef struct SIGROW_struct -{ - register8_t DEVICEID0; /* Device ID Byte 0 */ - register8_t DEVICEID1; /* Device ID Byte 1 */ - register8_t DEVICEID2; /* Device ID Byte 2 */ - register8_t SERNUM0; /* Serial Number Byte 0 */ - register8_t SERNUM1; /* Serial Number Byte 1 */ - register8_t SERNUM2; /* Serial Number Byte 2 */ - register8_t SERNUM3; /* Serial Number Byte 3 */ - register8_t SERNUM4; /* Serial Number Byte 4 */ - register8_t SERNUM5; /* Serial Number Byte 5 */ - register8_t SERNUM6; /* Serial Number Byte 6 */ - register8_t SERNUM7; /* Serial Number Byte 7 */ - register8_t SERNUM8; /* Serial Number Byte 8 */ - register8_t SERNUM9; /* Serial Number Byte 9 */ - register8_t reserved_0x0D; - register8_t reserved_0x0E; - register8_t reserved_0x0F; - register8_t reserved_0x10; - register8_t reserved_0x11; - register8_t reserved_0x12; - register8_t reserved_0x13; - register8_t OSCCAL32K; /* Oscillator Calibration for 32kHz ULP */ - register8_t reserved_0x15; - register8_t reserved_0x16; - register8_t reserved_0x17; - register8_t OSCCAL16M0; /* Oscillator Calibration 16 MHz Byte 0 */ - register8_t OSCCAL16M1; /* Oscillator Calibration 16 MHz Byte 1 */ - register8_t OSCCAL20M0; /* Oscillator Calibration 20 MHz Byte 0 */ - register8_t OSCCAL20M1; /* Oscillator Calibration 20 MHz Byte 1 */ - register8_t reserved_0x1C; - register8_t reserved_0x1D; - register8_t reserved_0x1E; - register8_t reserved_0x1F; - register8_t TEMPSENSE0; /* Temperature Sensor Calibration Byte 0 */ - register8_t TEMPSENSE1; /* Temperature Sensor Calibration Byte 1 */ - register8_t OSC16ERR3V; /* OSC16 error at 3V */ - register8_t OSC16ERR5V; /* OSC16 error at 5V */ - register8_t OSC20ERR3V; /* OSC20 error at 3V */ - register8_t OSC20ERR5V; /* OSC20 error at 5V */ - register8_t reserved_0x26; - register8_t reserved_0x27; - register8_t reserved_0x28; - register8_t reserved_0x29; - register8_t reserved_0x2A; - register8_t reserved_0x2B; - register8_t reserved_0x2C; - register8_t reserved_0x2D; - register8_t reserved_0x2E; - register8_t CHECKSUM1; /* CRC Checksum Byte 1 */ - register8_t reserved_0x30; - register8_t reserved_0x31; - register8_t reserved_0x32; - register8_t reserved_0x33; - register8_t reserved_0x34; - register8_t reserved_0x35; - register8_t reserved_0x36; - register8_t reserved_0x37; - register8_t reserved_0x38; - register8_t reserved_0x39; - register8_t reserved_0x3A; - register8_t reserved_0x3B; - register8_t reserved_0x3C; - register8_t reserved_0x3D; - register8_t reserved_0x3E; - register8_t reserved_0x3F; -} SIGROW_t; - - -/* --------------------------------------------------------------------------- -SLPCTRL - Sleep Controller --------------------------------------------------------------------------- -*/ - -/* Sleep Controller */ -typedef struct SLPCTRL_struct -{ - register8_t CTRLA; /* Control */ - register8_t reserved_0x01; -} SLPCTRL_t; - -/* Sleep mode select */ -typedef enum SLPCTRL_SMODE_enum -{ - SLPCTRL_SMODE_IDLE_gc = (0x00<<1), /* Idle mode */ - SLPCTRL_SMODE_STDBY_gc = (0x01<<1), /* Standby Mode */ - SLPCTRL_SMODE_PDOWN_gc = (0x02<<1), /* Power-down Mode */ -} SLPCTRL_SMODE_t; - -#define SLEEP_MODE_IDLE (0x00<<1) -#define SLEEP_MODE_STANDBY (0x01<<1) -#define SLEEP_MODE_PWR_DOWN (0x02<<1) -/* --------------------------------------------------------------------------- -SPI - Serial Peripheral Interface --------------------------------------------------------------------------- -*/ - -/* Serial Peripheral Interface */ -typedef struct SPI_struct -{ - register8_t CTRLA; /* Control A */ - register8_t CTRLB; /* Control B */ - register8_t INTCTRL; /* Interrupt Control */ - register8_t INTFLAGS; /* Interrupt Flags */ - register8_t DATA; /* Data */ - register8_t reserved_0x05; - register8_t reserved_0x06; - register8_t reserved_0x07; -} SPI_t; - -/* SPI Mode select */ -typedef enum SPI_MODE_enum -{ - SPI_MODE_0_gc = (0x00<<0), /* SPI Mode 0 */ - SPI_MODE_1_gc = (0x01<<0), /* SPI Mode 1 */ - SPI_MODE_2_gc = (0x02<<0), /* SPI Mode 2 */ - SPI_MODE_3_gc = (0x03<<0), /* SPI Mode 3 */ -} SPI_MODE_t; - -/* Prescaler select */ -typedef enum SPI_PRESC_enum -{ - SPI_PRESC_DIV4_gc = (0x00<<1), /* System Clock / 4 */ - SPI_PRESC_DIV16_gc = (0x01<<1), /* System Clock / 16 */ - SPI_PRESC_DIV64_gc = (0x02<<1), /* System Clock / 64 */ - SPI_PRESC_DIV128_gc = (0x03<<1), /* System Clock / 128 */ -} SPI_PRESC_t; - -/* --------------------------------------------------------------------------- -SYSCFG - System Configuration Registers --------------------------------------------------------------------------- -*/ - -/* System Configuration Registers */ -typedef struct SYSCFG_struct -{ - register8_t reserved_0x00; - register8_t REVID; /* Revision ID */ - register8_t EXTBRK; /* External Break */ - register8_t reserved_0x03; - register8_t reserved_0x04; - register8_t reserved_0x05; - register8_t reserved_0x06; - register8_t reserved_0x07; - register8_t reserved_0x08; - register8_t reserved_0x09; - register8_t reserved_0x0A; - register8_t reserved_0x0B; - register8_t reserved_0x0C; - register8_t reserved_0x0D; - register8_t reserved_0x0E; - register8_t reserved_0x0F; - register8_t reserved_0x10; - register8_t reserved_0x11; - register8_t reserved_0x12; - register8_t reserved_0x13; - register8_t reserved_0x14; - register8_t reserved_0x15; - register8_t reserved_0x16; - register8_t reserved_0x17; - register8_t OCDM; /* OCD Message Register */ - register8_t OCDMS; /* OCD Message Status */ - register8_t reserved_0x1A; - register8_t reserved_0x1B; - register8_t reserved_0x1C; - register8_t reserved_0x1D; - register8_t reserved_0x1E; - register8_t reserved_0x1F; -} SYSCFG_t; - - -/* --------------------------------------------------------------------------- -TCA - 16-bit Timer/Counter Type A --------------------------------------------------------------------------- -*/ - -/* 16-bit Timer/Counter Type A - Single Mode */ -typedef struct TCA_SINGLE_struct -{ - register8_t CTRLA; /* Control A */ - register8_t CTRLB; /* Control B */ - register8_t CTRLC; /* Control C */ - register8_t CTRLD; /* Control D */ - register8_t CTRLECLR; /* Control E Clear */ - register8_t CTRLESET; /* Control E Set */ - register8_t CTRLFCLR; /* Control F Clear */ - register8_t CTRLFSET; /* Control F Set */ - register8_t reserved_0x08; - register8_t EVCTRL; /* Event Control */ - register8_t INTCTRL; /* Interrupt Control */ - register8_t INTFLAGS; /* Interrupt Flags */ - register8_t reserved_0x0C; - register8_t reserved_0x0D; - register8_t DBGCTRL; /* Degbug Control */ - register8_t TEMP; /* Temporary data for 16-bit Access */ - register8_t reserved_0x10; - register8_t reserved_0x11; - register8_t reserved_0x12; - register8_t reserved_0x13; - register8_t reserved_0x14; - register8_t reserved_0x15; - register8_t reserved_0x16; - register8_t reserved_0x17; - register8_t reserved_0x18; - register8_t reserved_0x19; - register8_t reserved_0x1A; - register8_t reserved_0x1B; - register8_t reserved_0x1C; - register8_t reserved_0x1D; - register8_t reserved_0x1E; - register8_t reserved_0x1F; - _WORDREGISTER(CNT); /* Count */ - register8_t reserved_0x22; - register8_t reserved_0x23; - register8_t reserved_0x24; - register8_t reserved_0x25; - _WORDREGISTER(PER); /* Period */ - _WORDREGISTER(CMP0); /* Compare 0 */ - _WORDREGISTER(CMP1); /* Compare 1 */ - _WORDREGISTER(CMP2); /* Compare 2 */ - register8_t reserved_0x2E; - register8_t reserved_0x2F; - register8_t reserved_0x30; - register8_t reserved_0x31; - register8_t reserved_0x32; - register8_t reserved_0x33; - register8_t reserved_0x34; - register8_t reserved_0x35; - _WORDREGISTER(PERBUF); /* Period Buffer */ - _WORDREGISTER(CMP0BUF); /* Compare 0 Buffer */ - _WORDREGISTER(CMP1BUF); /* Compare 1 Buffer */ - _WORDREGISTER(CMP2BUF); /* Compare 2 Buffer */ - register8_t reserved_0x3E; - register8_t reserved_0x3F; -} TCA_SINGLE_t; - - -/* 16-bit Timer/Counter Type A - Split Mode */ -typedef struct TCA_SPLIT_struct -{ - register8_t CTRLA; /* Control A */ - register8_t CTRLB; /* Control B */ - register8_t CTRLC; /* Control C */ - register8_t CTRLD; /* Control D */ - register8_t CTRLECLR; /* Control E Clear */ - register8_t CTRLESET; /* Control E Set */ - register8_t reserved_0x06; - register8_t reserved_0x07; - register8_t reserved_0x08; - register8_t reserved_0x09; - register8_t INTCTRL; /* Interrupt Control */ - register8_t INTFLAGS; /* Interrupt Flags */ - register8_t reserved_0x0C; - register8_t reserved_0x0D; - register8_t DBGCTRL; /* Degbug Control */ - register8_t reserved_0x0F; - register8_t reserved_0x10; - register8_t reserved_0x11; - register8_t reserved_0x12; - register8_t reserved_0x13; - register8_t reserved_0x14; - register8_t reserved_0x15; - register8_t reserved_0x16; - register8_t reserved_0x17; - register8_t reserved_0x18; - register8_t reserved_0x19; - register8_t reserved_0x1A; - register8_t reserved_0x1B; - register8_t reserved_0x1C; - register8_t reserved_0x1D; - register8_t reserved_0x1E; - register8_t reserved_0x1F; - register8_t LCNT; /* Low Count */ - register8_t HCNT; /* High Count */ - register8_t reserved_0x22; - register8_t reserved_0x23; - register8_t reserved_0x24; - register8_t reserved_0x25; - register8_t LPER; /* Low Period */ - register8_t HPER; /* High Period */ - register8_t LCMP0; /* Low Compare */ - register8_t HCMP0; /* High Compare */ - register8_t LCMP1; /* Low Compare */ - register8_t HCMP1; /* High Compare */ - register8_t LCMP2; /* Low Compare */ - register8_t HCMP2; /* High Compare */ - register8_t reserved_0x2E; - register8_t reserved_0x2F; - register8_t reserved_0x30; - register8_t reserved_0x31; - register8_t reserved_0x32; - register8_t reserved_0x33; - register8_t reserved_0x34; - register8_t reserved_0x35; - register8_t reserved_0x36; - register8_t reserved_0x37; - register8_t reserved_0x38; - register8_t reserved_0x39; - register8_t reserved_0x3A; - register8_t reserved_0x3B; - register8_t reserved_0x3C; - register8_t reserved_0x3D; - register8_t reserved_0x3E; - register8_t reserved_0x3F; -} TCA_SPLIT_t; - - -/* 16-bit Timer/Counter Type A */ -typedef union TCA_union -{ - TCA_SINGLE_t SINGLE; /* 16-bit Timer/Counter Type A - Single Mode */ - TCA_SPLIT_t SPLIT; /* 16-bit Timer/Counter Type A - Split Mode */ -} TCA_t; - -/* Clock Selection select */ -typedef enum TCA_SINGLE_CLKSEL_enum -{ - TCA_SINGLE_CLKSEL_DIV1_gc = (0x00<<1), /* System Clock */ - TCA_SINGLE_CLKSEL_DIV2_gc = (0x01<<1), /* System Clock / 2 */ - TCA_SINGLE_CLKSEL_DIV4_gc = (0x02<<1), /* System Clock / 4 */ - TCA_SINGLE_CLKSEL_DIV8_gc = (0x03<<1), /* System Clock / 8 */ - TCA_SINGLE_CLKSEL_DIV16_gc = (0x04<<1), /* System Clock / 16 */ - TCA_SINGLE_CLKSEL_DIV64_gc = (0x05<<1), /* System Clock / 64 */ - TCA_SINGLE_CLKSEL_DIV256_gc = (0x06<<1), /* System Clock / 256 */ - TCA_SINGLE_CLKSEL_DIV1024_gc = (0x07<<1), /* System Clock / 1024 */ -} TCA_SINGLE_CLKSEL_t; - -/* Command select */ -typedef enum TCA_SINGLE_CMD_enum -{ - TCA_SINGLE_CMD_NONE_gc = (0x00<<2), /* No Command */ - TCA_SINGLE_CMD_UPDATE_gc = (0x01<<2), /* Force Update */ - TCA_SINGLE_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ - TCA_SINGLE_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ -} TCA_SINGLE_CMD_t; - -/* Direction select */ -typedef enum TCA_SINGLE_DIR_enum -{ - TCA_SINGLE_DIR_UP_gc = (0x00<<0), /* Count up */ - TCA_SINGLE_DIR_DOWN_gc = (0x01<<0), /* Count down */ -} TCA_SINGLE_DIR_t; - -/* Event Action select */ -typedef enum TCA_SINGLE_EVACT_enum -{ - TCA_SINGLE_EVACT_POSEDGE_gc = (0x00<<1), /* Count on positive edge event */ - TCA_SINGLE_EVACT_ANYEDGE_gc = (0x01<<1), /* Count on any edge event */ - TCA_SINGLE_EVACT_HIGHLVL_gc = (0x02<<1), /* Count on prescaled clock while event line is 1. */ - TCA_SINGLE_EVACT_UPDOWN_gc = (0x03<<1), /* Count on prescaled clock. Event controls count direction. Up-count when event line is 0, down-count when event line is 1. */ -} TCA_SINGLE_EVACT_t; - -/* Waveform generation mode select */ -typedef enum TCA_SINGLE_WGMODE_enum -{ - TCA_SINGLE_WGMODE_NORMAL_gc = (0x00<<0), /* Normal Mode */ - TCA_SINGLE_WGMODE_FRQ_gc = (0x01<<0), /* Frequency Generation Mode */ - TCA_SINGLE_WGMODE_SINGLESLOPE_gc = (0x03<<0), /* Single Slope PWM */ - TCA_SINGLE_WGMODE_DSTOP_gc = (0x05<<0), /* Dual Slope PWM, overflow on TOP */ - TCA_SINGLE_WGMODE_DSBOTH_gc = (0x06<<0), /* Dual Slope PWM, overflow on TOP and BOTTOM */ - TCA_SINGLE_WGMODE_DSBOTTOM_gc = (0x07<<0), /* Dual Slope PWM, overflow on BOTTOM */ -} TCA_SINGLE_WGMODE_t; - -/* Clock Selection select */ -typedef enum TCA_SPLIT_CLKSEL_enum -{ - TCA_SPLIT_CLKSEL_DIV1_gc = (0x00<<1), /* System Clock */ - TCA_SPLIT_CLKSEL_DIV2_gc = (0x01<<1), /* System Clock / 2 */ - TCA_SPLIT_CLKSEL_DIV4_gc = (0x02<<1), /* System Clock / 4 */ - TCA_SPLIT_CLKSEL_DIV8_gc = (0x03<<1), /* System Clock / 8 */ - TCA_SPLIT_CLKSEL_DIV16_gc = (0x04<<1), /* System Clock / 16 */ - TCA_SPLIT_CLKSEL_DIV64_gc = (0x05<<1), /* System Clock / 64 */ - TCA_SPLIT_CLKSEL_DIV256_gc = (0x06<<1), /* System Clock / 256 */ - TCA_SPLIT_CLKSEL_DIV1024_gc = (0x07<<1), /* System Clock / 1024 */ -} TCA_SPLIT_CLKSEL_t; - -/* Command select */ -typedef enum TCA_SPLIT_CMD_enum -{ - TCA_SPLIT_CMD_NONE_gc = (0x00<<2), /* No Command */ - TCA_SPLIT_CMD_UPDATE_gc = (0x01<<2), /* Force Update */ - TCA_SPLIT_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ - TCA_SPLIT_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ -} TCA_SPLIT_CMD_t; - -/* --------------------------------------------------------------------------- -TCB - 16-bit Timer Type B --------------------------------------------------------------------------- -*/ - -/* 16-bit Timer Type B */ -typedef struct TCB_struct -{ - register8_t CTRLA; /* Control A */ - register8_t CTRLB; /* Control Register B */ - register8_t reserved_0x02; - register8_t reserved_0x03; - register8_t EVCTRL; /* Event Control */ - register8_t INTCTRL; /* Interrupt Control */ - register8_t INTFLAGS; /* Interrupt Flags */ - register8_t STATUS; /* Status */ - register8_t DBGCTRL; /* Debug Control */ - register8_t TEMP; /* Temporary Value */ - _WORDREGISTER(CNT); /* Count */ - _WORDREGISTER(CCMP); /* Compare or Capture */ - register8_t reserved_0x0E; - register8_t reserved_0x0F; -} TCB_t; - -/* Clock Select select */ -typedef enum TCB_CLKSEL_enum -{ - TCB_CLKSEL_CLKDIV1_gc = (0x00<<1), /* CLK_PER (No Prescaling) */ - TCB_CLKSEL_CLKDIV2_gc = (0x01<<1), /* CLK_PER/2 (From Prescaler) */ - TCB_CLKSEL_CLKTCA_gc = (0x02<<1), /* Use Clock from TCA */ -} TCB_CLKSEL_t; - -/* Timer Mode select */ -typedef enum TCB_CNTMODE_enum -{ - TCB_CNTMODE_INT_gc = (0x00<<0), /* Periodic Interrupt */ - TCB_CNTMODE_TIMEOUT_gc = (0x01<<0), /* Periodic Timeout */ - TCB_CNTMODE_CAPT_gc = (0x02<<0), /* Input Capture Event */ - TCB_CNTMODE_FRQ_gc = (0x03<<0), /* Input Capture Frequency measurement */ - TCB_CNTMODE_PW_gc = (0x04<<0), /* Input Capture Pulse-Width measurement */ - TCB_CNTMODE_FRQPW_gc = (0x05<<0), /* Input Capture Frequency and Pulse-Width measurement */ - TCB_CNTMODE_SINGLE_gc = (0x06<<0), /* Single Shot */ - TCB_CNTMODE_PWM8_gc = (0x07<<0), /* 8-bit PWM */ -} TCB_CNTMODE_t; - -/* --------------------------------------------------------------------------- -TWI - Two-Wire Interface --------------------------------------------------------------------------- -*/ - -/* Two-Wire Interface */ -typedef struct TWI_struct -{ - register8_t CTRLA; /* Control A */ - register8_t BRIDGECTRL; /* Bridge Control */ - register8_t DBGCTRL; /* Debug Control Register */ - register8_t MCTRLA; /* Master Control A */ - register8_t MCTRLB; /* Master Control B */ - register8_t MSTATUS; /* Master Status */ - register8_t MBAUD; /* Master Baurd Rate Control */ - register8_t MADDR; /* Master Address */ - register8_t MDATA; /* Master Data */ - register8_t SCTRLA; /* Slave Control A */ - register8_t SCTRLB; /* Slave Control B */ - register8_t SSTATUS; /* Slave Status */ - register8_t SADDR; /* Slave Address */ - register8_t SDATA; /* Slave Data */ - register8_t SADDRMASK; /* Slave Address Mask */ - register8_t reserved_0x0F; -} TWI_t; - -/* Acknowledge Action select */ -typedef enum TWI_ACKACT_enum -{ - TWI_ACKACT_ACK_gc = (0x00<<2), /* Send ACK */ - TWI_ACKACT_NACK_gc = (0x01<<2), /* Send NACK */ -} TWI_ACKACT_t; - -/* Slave Address or Stop select */ -typedef enum TWI_AP_enum -{ - TWI_AP_STOP_gc = (0x00<<0), /* Stop condition generated APIF */ - TWI_AP_ADR_gc = (0x01<<0), /* Address detection generated APIF */ -} TWI_AP_t; - -/* Bus State select */ -typedef enum TWI_BUSSTATE_enum -{ - TWI_BUSSTATE_UNKNOWN_gc = (0x00<<0), /* Unknown Bus State */ - TWI_BUSSTATE_IDLE_gc = (0x01<<0), /* Bus is Idle */ - TWI_BUSSTATE_OWNER_gc = (0x02<<0), /* This Module Controls The Bus */ - TWI_BUSSTATE_BUSY_gc = (0x03<<0), /* The Bus is Busy */ -} TWI_BUSSTATE_t; - -/* Command select */ -typedef enum TWI_MCMD_enum -{ - TWI_MCMD_NOACT_gc = (0x00<<0), /* No Action */ - TWI_MCMD_REPSTART_gc = (0x01<<0), /* Issue Repeated Start Condition */ - TWI_MCMD_RECVTRANS_gc = (0x02<<0), /* Receive or Transmit Data, depending on DIR */ - TWI_MCMD_STOP_gc = (0x03<<0), /* Issue Stop Condition */ -} TWI_MCMD_t; - -/* Command select */ -typedef enum TWI_SCMD_enum -{ - TWI_SCMD_NOACT_gc = (0x00<<0), /* No Action */ - TWI_SCMD_COMPTRANS_gc = (0x02<<0), /* Used To Complete a Transaction */ - TWI_SCMD_RESPONSE_gc = (0x03<<0), /* Used in Response to Address/Data Interrupt */ -} TWI_SCMD_t; - -/* SDA Hold Time select */ -typedef enum TWI_SDAHOLD_enum -{ - TWI_SDAHOLD_OFF_gc = (0x00<<2), /* SDA hold time off */ - TWI_SDAHOLD_50NS_gc = (0x01<<2), /* Typical 50ns hold time */ - TWI_SDAHOLD_300NS_gc = (0x02<<2), /* Typical 300ns hold time */ - TWI_SDAHOLD_500NS_gc = (0x03<<2), /* Typical 500ns hold time */ -} TWI_SDAHOLD_t; - -/* SDA Setup Time select */ -typedef enum TWI_SDASETUP_enum -{ - TWI_SDASETUP_4CYC_gc = (0x00<<4), /* SDA setup time is 4 clock cycles */ - TWI_SDASETUP_8CYC_gc = (0x01<<4), /* SDA setup time is 8 clock cycles */ -} TWI_SDASETUP_t; - -/* Inactive Bus Timeout select */ -typedef enum TWI_TIMEOUT_enum -{ - TWI_TIMEOUT_DISABLED_gc = (0x00<<2), /* Bus Timeout Disabled */ - TWI_TIMEOUT_50US_gc = (0x01<<2), /* 50 Microseconds */ - TWI_TIMEOUT_100US_gc = (0x02<<2), /* 100 Microseconds */ - TWI_TIMEOUT_200US_gc = (0x03<<2), /* 200 Microseconds */ -} TWI_TIMEOUT_t; - -/* --------------------------------------------------------------------------- -USART - Universal Synchronous and Asynchronous Receiver and Transmitter --------------------------------------------------------------------------- -*/ - -/* Universal Synchronous and Asynchronous Receiver and Transmitter */ -typedef struct USART_struct -{ - register8_t RXDATAL; /* Receive Data Low Byte */ - register8_t RXDATAH; /* Receive Data High Byte */ - register8_t TXDATAL; /* Transmit Data Low Byte */ - register8_t TXDATAH; /* Transmit Data High Byte */ - register8_t STATUS; /* Status */ - register8_t CTRLA; /* Control A */ - register8_t CTRLB; /* Control B */ - register8_t CTRLC; /* Control C */ - _WORDREGISTER(BAUD); /* Baud Rate */ - register8_t CTRLD; /* Control D */ - register8_t DBGCTRL; /* Debug Control */ - register8_t EVCTRL; /* Event Control */ - register8_t TXPLCTRL; /* IRCOM Transmitter Pulse Length Control */ - register8_t RXPLCTRL; /* IRCOM Receiver Pulse Length Control */ - register8_t reserved_0x0F; -} USART_t; - -/* Character Size select */ -typedef enum USART_CHSIZE_enum -{ - USART_CHSIZE_5BIT_gc = (0x00<<0), /* Character size: 5 bit */ - USART_CHSIZE_6BIT_gc = (0x01<<0), /* Character size: 6 bit */ - USART_CHSIZE_7BIT_gc = (0x02<<0), /* Character size: 7 bit */ - USART_CHSIZE_8BIT_gc = (0x03<<0), /* Character size: 8 bit */ - USART_CHSIZE_9BITL_gc = (0x06<<0), /* Character size: 9 bit read low byte first */ - USART_CHSIZE_9BITH_gc = (0x07<<0), /* Character size: 9 bit read high byte first */ -} USART_CHSIZE_t; - -/* Communication Mode select */ -typedef enum USART_CMODE_enum -{ - USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6), /* Asynchronous Mode */ - USART_CMODE_SYNCHRONOUS_gc = (0x01<<6), /* Synchronous Mode */ - USART_CMODE_IRCOM_gc = (0x02<<6), /* Infrared Communication */ - USART_CMODE_MSPI_gc = (0x03<<6), /* Master SPI Mode */ -} USART_CMODE_t; - -/* Parity Mode select */ -typedef enum USART_PMODE_enum -{ - USART_PMODE_DISABLED_gc = (0x00<<4), /* No Parity */ - USART_PMODE_EVEN_gc = (0x02<<4), /* Even Parity */ - USART_PMODE_ODD_gc = (0x03<<4), /* Odd Parity */ -} USART_PMODE_t; - -/* RS485 Mode internal transmitter select */ -typedef enum USART_RS485_enum -{ - USART_RS485_OFF_gc = (0x00<<0), /* RS485 Mode disabled */ - USART_RS485_EXT_gc = (0x01<<0), /* RS485 Mode External drive */ - USART_RS485_INT_gc = (0x02<<0), /* RS485 Mode Internal drive */ -} USART_RS485_t; - -/* Receiver Mode select */ -typedef enum USART_RXMODE_enum -{ - USART_RXMODE_NORMAL_gc = (0x00<<1), /* Normal mode */ - USART_RXMODE_CLK2X_gc = (0x01<<1), /* CLK2x mode */ - USART_RXMODE_GENAUTO_gc = (0x02<<1), /* Generic autobaud mode */ - USART_RXMODE_LINAUTO_gc = (0x03<<1), /* LIN constrained autobaud mode */ -} USART_RXMODE_t; - -/* Stop Bit Mode select */ -typedef enum USART_SBMODE_enum -{ - USART_SBMODE_1BIT_gc = (0x00<<3), /* 1 stop bit */ - USART_SBMODE_2BIT_gc = (0x01<<3), /* 2 stop bits */ -} USART_SBMODE_t; - -/* --------------------------------------------------------------------------- -USERROW - User Row --------------------------------------------------------------------------- -*/ - -/* User Row */ -typedef struct USERROW_struct -{ - register8_t USERROW0; /* User Row Byte 0 */ - register8_t USERROW1; /* User Row Byte 1 */ - register8_t USERROW2; /* User Row Byte 2 */ - register8_t USERROW3; /* User Row Byte 3 */ - register8_t USERROW4; /* User Row Byte 4 */ - register8_t USERROW5; /* User Row Byte 5 */ - register8_t USERROW6; /* User Row Byte 6 */ - register8_t USERROW7; /* User Row Byte 7 */ - register8_t USERROW8; /* User Row Byte 8 */ - register8_t USERROW9; /* User Row Byte 9 */ - register8_t USERROW10; /* User Row Byte 10 */ - register8_t USERROW11; /* User Row Byte 11 */ - register8_t USERROW12; /* User Row Byte 12 */ - register8_t USERROW13; /* User Row Byte 13 */ - register8_t USERROW14; /* User Row Byte 14 */ - register8_t USERROW15; /* User Row Byte 15 */ - register8_t USERROW16; /* User Row Byte 16 */ - register8_t USERROW17; /* User Row Byte 17 */ - register8_t USERROW18; /* User Row Byte 18 */ - register8_t USERROW19; /* User Row Byte 19 */ - register8_t USERROW20; /* User Row Byte 20 */ - register8_t USERROW21; /* User Row Byte 21 */ - register8_t USERROW22; /* User Row Byte 22 */ - register8_t USERROW23; /* User Row Byte 23 */ - register8_t USERROW24; /* User Row Byte 24 */ - register8_t USERROW25; /* User Row Byte 25 */ - register8_t USERROW26; /* User Row Byte 26 */ - register8_t USERROW27; /* User Row Byte 27 */ - register8_t USERROW28; /* User Row Byte 28 */ - register8_t USERROW29; /* User Row Byte 29 */ - register8_t USERROW30; /* User Row Byte 30 */ - register8_t USERROW31; /* User Row Byte 31 */ - register8_t USERROW32; /* User Row Byte 32 */ - register8_t USERROW33; /* User Row Byte 33 */ - register8_t USERROW34; /* User Row Byte 34 */ - register8_t USERROW35; /* User Row Byte 35 */ - register8_t USERROW36; /* User Row Byte 36 */ - register8_t USERROW37; /* User Row Byte 37 */ - register8_t USERROW38; /* User Row Byte 38 */ - register8_t USERROW39; /* User Row Byte 39 */ - register8_t USERROW40; /* User Row Byte 40 */ - register8_t USERROW41; /* User Row Byte 41 */ - register8_t USERROW42; /* User Row Byte 42 */ - register8_t USERROW43; /* User Row Byte 43 */ - register8_t USERROW44; /* User Row Byte 44 */ - register8_t USERROW45; /* User Row Byte 45 */ - register8_t USERROW46; /* User Row Byte 46 */ - register8_t USERROW47; /* User Row Byte 47 */ - register8_t USERROW48; /* User Row Byte 48 */ - register8_t USERROW49; /* User Row Byte 49 */ - register8_t USERROW50; /* User Row Byte 50 */ - register8_t USERROW51; /* User Row Byte 51 */ - register8_t USERROW52; /* User Row Byte 52 */ - register8_t USERROW53; /* User Row Byte 53 */ - register8_t USERROW54; /* User Row Byte 54 */ - register8_t USERROW55; /* User Row Byte 55 */ - register8_t USERROW56; /* User Row Byte 56 */ - register8_t USERROW57; /* User Row Byte 57 */ - register8_t USERROW58; /* User Row Byte 58 */ - register8_t USERROW59; /* User Row Byte 59 */ - register8_t USERROW60; /* User Row Byte 60 */ - register8_t USERROW61; /* User Row Byte 61 */ - register8_t USERROW62; /* User Row Byte 62 */ - register8_t USERROW63; /* User Row Byte 63 */ -} USERROW_t; - - -/* --------------------------------------------------------------------------- -VPORT - Virtual Ports --------------------------------------------------------------------------- -*/ - -/* Virtual Ports */ -typedef struct VPORT_struct -{ - register8_t DIR; /* Data Direction */ - register8_t OUT; /* Output Value */ - register8_t IN; /* Input Value */ - register8_t INTFLAGS; /* Interrupt Flags */ -} VPORT_t; - - -/* --------------------------------------------------------------------------- -VREF - Voltage reference --------------------------------------------------------------------------- -*/ - -/* Voltage reference */ -typedef struct VREF_struct -{ - register8_t CTRLA; /* Control A */ - register8_t CTRLB; /* Control B */ -} VREF_t; - -/* AC0 reference select select */ -typedef enum VREF_AC0REFSEL_enum -{ - VREF_AC0REFSEL_0V55_gc = (0x00<<0), /* Voltage reference at 0.55V */ - VREF_AC0REFSEL_1V1_gc = (0x01<<0), /* Voltage reference at 1.1V */ - VREF_AC0REFSEL_2V5_gc = (0x02<<0), /* Voltage reference at 2.5V */ - VREF_AC0REFSEL_4V34_gc = (0x03<<0), /* Voltage reference at 4.34V */ - VREF_AC0REFSEL_1V5_gc = (0x04<<0), /* Voltage reference at 1.5V */ -} VREF_AC0REFSEL_t; - -/* ADC0 reference select select */ -typedef enum VREF_ADC0REFSEL_enum -{ - VREF_ADC0REFSEL_0V55_gc = (0x00<<4), /* Voltage reference at 0.55V */ - VREF_ADC0REFSEL_1V1_gc = (0x01<<4), /* Voltage reference at 1.1V */ - VREF_ADC0REFSEL_2V5_gc = (0x02<<4), /* Voltage reference at 2.5V */ - VREF_ADC0REFSEL_4V34_gc = (0x03<<4), /* Voltage reference at 4.34V */ - VREF_ADC0REFSEL_1V5_gc = (0x04<<4), /* Voltage reference at 1.5V */ -} VREF_ADC0REFSEL_t; - -/* --------------------------------------------------------------------------- -WDT - Watch-Dog Timer --------------------------------------------------------------------------- -*/ - -/* Watch-Dog Timer */ -typedef struct WDT_struct -{ - register8_t CTRLA; /* Control A */ - register8_t STATUS; /* Status */ -} WDT_t; - -/* Period select */ -typedef enum WDT_PERIOD_enum -{ - WDT_PERIOD_OFF_gc = (0x00<<0), /* Off */ - WDT_PERIOD_8CLK_gc = (0x01<<0), /* 8 cycles (8ms) */ - WDT_PERIOD_16CLK_gc = (0x02<<0), /* 16 cycles (16ms) */ - WDT_PERIOD_32CLK_gc = (0x03<<0), /* 32 cycles (32ms) */ - WDT_PERIOD_64CLK_gc = (0x04<<0), /* 64 cycles (64ms) */ - WDT_PERIOD_128CLK_gc = (0x05<<0), /* 128 cycles (0.128s) */ - WDT_PERIOD_256CLK_gc = (0x06<<0), /* 256 cycles (0.256s) */ - WDT_PERIOD_512CLK_gc = (0x07<<0), /* 512 cycles (0.512s) */ - WDT_PERIOD_1KCLK_gc = (0x08<<0), /* 1K cycles (1.0s) */ - WDT_PERIOD_2KCLK_gc = (0x09<<0), /* 2K cycles (2.0s) */ - WDT_PERIOD_4KCLK_gc = (0x0A<<0), /* 4K cycles (4.1s) */ - WDT_PERIOD_8KCLK_gc = (0x0B<<0), /* 8K cycles (8.2s) */ -} WDT_PERIOD_t; - -/* Window select */ -typedef enum WDT_WINDOW_enum -{ - WDT_WINDOW_OFF_gc = (0x00<<4), /* Off */ - WDT_WINDOW_8CLK_gc = (0x01<<4), /* 8 cycles (8ms) */ - WDT_WINDOW_16CLK_gc = (0x02<<4), /* 16 cycles (16ms) */ - WDT_WINDOW_32CLK_gc = (0x03<<4), /* 32 cycles (32ms) */ - WDT_WINDOW_64CLK_gc = (0x04<<4), /* 64 cycles (64ms) */ - WDT_WINDOW_128CLK_gc = (0x05<<4), /* 128 cycles (0.128s) */ - WDT_WINDOW_256CLK_gc = (0x06<<4), /* 256 cycles (0.256s) */ - WDT_WINDOW_512CLK_gc = (0x07<<4), /* 512 cycles (0.512s) */ - WDT_WINDOW_1KCLK_gc = (0x08<<4), /* 1K cycles (1.0s) */ - WDT_WINDOW_2KCLK_gc = (0x09<<4), /* 2K cycles (2.0s) */ - WDT_WINDOW_4KCLK_gc = (0x0A<<4), /* 4K cycles (4.1s) */ - WDT_WINDOW_8KCLK_gc = (0x0B<<4), /* 8K cycles (8.2s) */ -} WDT_WINDOW_t; -/* -========================================================================== -IO Module Instances. Mapped to memory. -========================================================================== -*/ - -#define VPORTA (*(VPORT_t *) 0x0000) /* Virtual Ports */ -#define VPORTB (*(VPORT_t *) 0x0004) /* Virtual Ports */ -#define VPORTC (*(VPORT_t *) 0x0008) /* Virtual Ports */ -#define VPORTD (*(VPORT_t *) 0x000C) /* Virtual Ports */ -#define VPORTE (*(VPORT_t *) 0x0010) /* Virtual Ports */ -#define VPORTF (*(VPORT_t *) 0x0014) /* Virtual Ports */ -#define RSTCTRL (*(RSTCTRL_t *) 0x0040) /* Reset controller */ -#define SLPCTRL (*(SLPCTRL_t *) 0x0050) /* Sleep Controller */ -#define CLKCTRL (*(CLKCTRL_t *) 0x0060) /* Clock controller */ -#define BOD (*(BOD_t *) 0x0080) /* Bod interface */ -#define VREF (*(VREF_t *) 0x00A0) /* Voltage reference */ -#define NVMBIST (*(NVMBIST_t *) 0x00C0) /* BIST in the NVMCTRL module */ -#define WDT (*(WDT_t *) 0x0100) /* Watch-Dog Timer */ -#define CPUINT (*(CPUINT_t *) 0x0110) /* Interrupt Controller */ -#define CRCSCAN (*(CRCSCAN_t *) 0x0120) /* CRCSCAN */ -#define RTC (*(RTC_t *) 0x0140) /* Real-Time Counter */ -#define EVSYS (*(EVSYS_t *) 0x0180) /* Event System */ -#define CCL (*(CCL_t *) 0x01C0) /* Configurable Custom Logic */ -#define PORTA (*(PORT_t *) 0x0400) /* I/O Ports */ -#define PORTB (*(PORT_t *) 0x0420) /* I/O Ports */ -#define PORTC (*(PORT_t *) 0x0440) /* I/O Ports */ -#define PORTD (*(PORT_t *) 0x0460) /* I/O Ports */ -#define PORTE (*(PORT_t *) 0x0480) /* I/O Ports */ -#define PORTF (*(PORT_t *) 0x04A0) /* I/O Ports */ -#define PORTMUX (*(PORTMUX_t *) 0x05E0) /* Port Multiplexer */ -#define ADC0 (*(ADC_t *) 0x0600) /* Analog to Digital Converter */ -#define AC0 (*(AC_t *) 0x0680) /* Analog Comparator */ -#define USART0 (*(USART_t *) 0x0800) /* Universal Synchronous and Asynchronous Receiver and Transmitter */ -#define USART1 (*(USART_t *) 0x0820) /* Universal Synchronous and Asynchronous Receiver and Transmitter */ -#define USART2 (*(USART_t *) 0x0840) /* Universal Synchronous and Asynchronous Receiver and Transmitter */ -#define TWI0 (*(TWI_t *) 0x08A0) /* Two-Wire Interface */ -#define SPI0 (*(SPI_t *) 0x08C0) /* Serial Peripheral Interface */ -#define TCA0 (*(TCA_t *) 0x0A00) /* 16-bit Timer/Counter Type A */ -#define TCB0 (*(TCB_t *) 0x0A80) /* 16-bit Timer Type B */ -#define TCB1 (*(TCB_t *) 0x0A90) /* 16-bit Timer Type B */ -#define TCB2 (*(TCB_t *) 0x0AA0) /* 16-bit Timer Type B */ -#define SYSCFG (*(SYSCFG_t *) 0x0F00) /* System Configuration Registers */ -#define NVMCTRL (*(NVMCTRL_t *) 0x1000) /* Non-volatile Memory Controller */ -#define SIGROW (*(SIGROW_t *) 0x1100) /* Signature row */ -#define FUSE (*(FUSE_t *) 0x1280) /* Fuses */ -#define LOCKBIT (*(LOCKBIT_t *) 0x128A) /* Lockbit */ -#define USERROW (*(USERROW_t *) 0x1300) /* User Row */ - -#endif /* !defined (__ASSEMBLER__) */ - - -/* ========== Flattened fully qualified IO register names ========== */ - - -/* VPORT (VPORTA) - Virtual Ports */ -#define VPORTA_DIR _SFR_MEM8(0x0000) -#define VPORTA_OUT _SFR_MEM8(0x0001) -#define VPORTA_IN _SFR_MEM8(0x0002) -#define VPORTA_INTFLAGS _SFR_MEM8(0x0003) - - -/* VPORT (VPORTB) - Virtual Ports */ -#define VPORTB_DIR _SFR_MEM8(0x0004) -#define VPORTB_OUT _SFR_MEM8(0x0005) -#define VPORTB_IN _SFR_MEM8(0x0006) -#define VPORTB_INTFLAGS _SFR_MEM8(0x0007) - - -/* VPORT (VPORTC) - Virtual Ports */ -#define VPORTC_DIR _SFR_MEM8(0x0008) -#define VPORTC_OUT _SFR_MEM8(0x0009) -#define VPORTC_IN _SFR_MEM8(0x000A) -#define VPORTC_INTFLAGS _SFR_MEM8(0x000B) - - -/* VPORT (VPORTD) - Virtual Ports */ -#define VPORTD_DIR _SFR_MEM8(0x000C) -#define VPORTD_OUT _SFR_MEM8(0x000D) -#define VPORTD_IN _SFR_MEM8(0x000E) -#define VPORTD_INTFLAGS _SFR_MEM8(0x000F) - - -/* VPORT (VPORTE) - Virtual Ports */ -#define VPORTE_DIR _SFR_MEM8(0x0010) -#define VPORTE_OUT _SFR_MEM8(0x0011) -#define VPORTE_IN _SFR_MEM8(0x0012) -#define VPORTE_INTFLAGS _SFR_MEM8(0x0013) - - -/* VPORT (VPORTF) - Virtual Ports */ -#define VPORTF_DIR _SFR_MEM8(0x0014) -#define VPORTF_OUT _SFR_MEM8(0x0015) -#define VPORTF_IN _SFR_MEM8(0x0016) -#define VPORTF_INTFLAGS _SFR_MEM8(0x0017) - - -/* GPIO - General Purpose IO */ -#define GPIO_GPIOR0 _SFR_MEM8(0x001C) -#define GPIO_GPIOR1 _SFR_MEM8(0x001D) -#define GPIO_GPIOR2 _SFR_MEM8(0x001E) -#define GPIO_GPIOR3 _SFR_MEM8(0x001F) - - -/* Deprecated */ -#define GPIO_GPIO0 _SFR_MEM8(0x001C) -#define GPIO_GPIO1 _SFR_MEM8(0x001D) -#define GPIO_GPIO2 _SFR_MEM8(0x001E) -#define GPIO_GPIO3 _SFR_MEM8(0x001F) - - -/* CPU - CPU */ -#define CPU_CCP _SFR_MEM8(0x0034) -#define CPU_RAMPZ _SFR_MEM8(0x003B) -#define CPU_SPL _SFR_MEM8(0x003D) -#define CPU_SPH _SFR_MEM8(0x003E) -#define CPU_SREG _SFR_MEM8(0x003F) - - -/* RSTCTRL - Reset controller */ -#define RSTCTRL_RSTFR _SFR_MEM8(0x0040) -#define RSTCTRL_SWRR _SFR_MEM8(0x0041) - - -/* SLPCTRL - Sleep Controller */ -#define SLPCTRL_CTRLA _SFR_MEM8(0x0050) - - -/* CLKCTRL - Clock controller */ -#define CLKCTRL_MCLKCTRLA _SFR_MEM8(0x0060) -#define CLKCTRL_MCLKCTRLB _SFR_MEM8(0x0061) -#define CLKCTRL_MCLKLOCK _SFR_MEM8(0x0062) -#define CLKCTRL_MCLKSTATUS _SFR_MEM8(0x0063) -#define CLKCTRL_OSC20MCTRLA _SFR_MEM8(0x0070) -#define CLKCTRL_OSC20MCALIBA _SFR_MEM8(0x0071) -#define CLKCTRL_OSC20MCALIBB _SFR_MEM8(0x0072) -#define CLKCTRL_OSC32KCTRLA _SFR_MEM8(0x0078) -#define CLKCTRL_OSC32KCALIB _SFR_MEM8(0x0079) -#define CLKCTRL_XOSC32KCTRLA _SFR_MEM8(0x007C) - - -/* BOD - Bod interface */ -#define BOD_CTRLA _SFR_MEM8(0x0080) -#define BOD_CTRLB _SFR_MEM8(0x0081) -#define BOD_VLMCTRLA _SFR_MEM8(0x0088) -#define BOD_INTCTRL _SFR_MEM8(0x0089) -#define BOD_INTFLAGS _SFR_MEM8(0x008A) -#define BOD_STATUS _SFR_MEM8(0x008B) - - -/* VREF - Voltage reference */ -#define VREF_CTRLA _SFR_MEM8(0x00A0) -#define VREF_CTRLB _SFR_MEM8(0x00A1) - - -/* NVMBIST - BIST in the NVMCTRL module */ -#define NVMBIST_CTRLA _SFR_MEM8(0x00C0) -#define NVMBIST_ADDRPAT _SFR_MEM8(0x00C1) -#define NVMBIST_DATAPAT _SFR_MEM8(0x00C2) -#define NVMBIST_STATUS _SFR_MEM8(0x00C3) -#define NVMBIST_CNT _SFR_MEM16(0x00C4) -#define NVMBIST_CNTL _SFR_MEM8(0x00C4) -#define NVMBIST_CNTH _SFR_MEM8(0x00C5) -#define NVMBIST_END _SFR_MEM32(0x00C6) -#define NVMBIST_END0 _SFR_MEM8(0x00C6) -#define NVMBIST_END1 _SFR_MEM8(0x00C7) -#define NVMBIST_END2 _SFR_MEM8(0x00C8) -#define NVMBIST_END3 _SFR_MEM8(0x00C9) - - -/* WDT - Watch-Dog Timer */ -#define WDT_CTRLA _SFR_MEM8(0x0100) -#define WDT_STATUS _SFR_MEM8(0x0101) - - -/* CPUINT - Interrupt Controller */ -#define CPUINT_CTRLA _SFR_MEM8(0x0110) -#define CPUINT_STATUS _SFR_MEM8(0x0111) -#define CPUINT_LVL0PRI _SFR_MEM8(0x0112) -#define CPUINT_LVL1VEC _SFR_MEM8(0x0113) - - -/* CRCSCAN - CRCSCAN */ -#define CRCSCAN_CTRLA _SFR_MEM8(0x0120) -#define CRCSCAN_CTRLB _SFR_MEM8(0x0121) -#define CRCSCAN_STATUS _SFR_MEM8(0x0122) - - -/* RTC - Real-Time Counter */ -#define RTC_CTRLA _SFR_MEM8(0x0140) -#define RTC_STATUS _SFR_MEM8(0x0141) -#define RTC_INTCTRL _SFR_MEM8(0x0142) -#define RTC_INTFLAGS _SFR_MEM8(0x0143) -#define RTC_TEMP _SFR_MEM8(0x0144) -#define RTC_DBGCTRL _SFR_MEM8(0x0145) -#define RTC_CLKSEL _SFR_MEM8(0x0147) -#define RTC_CNT _SFR_MEM16(0x0148) -#define RTC_CNTL _SFR_MEM8(0x0148) -#define RTC_CNTH _SFR_MEM8(0x0149) -#define RTC_PER _SFR_MEM16(0x014A) -#define RTC_PERL _SFR_MEM8(0x014A) -#define RTC_PERH _SFR_MEM8(0x014B) -#define RTC_CMP _SFR_MEM16(0x014C) -#define RTC_CMPL _SFR_MEM8(0x014C) -#define RTC_CMPH _SFR_MEM8(0x014D) -#define RTC_PITCTRLA _SFR_MEM8(0x0150) -#define RTC_PITSTATUS _SFR_MEM8(0x0151) -#define RTC_PITINTCTRL _SFR_MEM8(0x0152) -#define RTC_PITINTFLAGS _SFR_MEM8(0x0153) -#define RTC_PITDBGCTRL _SFR_MEM8(0x0155) - - -/* EVSYS - Event System */ -#define EVSYS_STROBE _SFR_MEM8(0x0180) -#define EVSYS_CHANNEL0 _SFR_MEM8(0x0190) -#define EVSYS_CHANNEL1 _SFR_MEM8(0x0191) -#define EVSYS_CHANNEL2 _SFR_MEM8(0x0192) -#define EVSYS_CHANNEL3 _SFR_MEM8(0x0193) -#define EVSYS_CHANNEL4 _SFR_MEM8(0x0194) -#define EVSYS_CHANNEL5 _SFR_MEM8(0x0195) -#define EVSYS_USERCCLLUT0A _SFR_MEM8(0x01A0) -#define EVSYS_USERCCLLUT0B _SFR_MEM8(0x01A1) -#define EVSYS_USERCCLLUT1A _SFR_MEM8(0x01A2) -#define EVSYS_USERCCLLUT1B _SFR_MEM8(0x01A3) -#define EVSYS_USERCCLLUT2A _SFR_MEM8(0x01A4) -#define EVSYS_USERCCLLUT2B _SFR_MEM8(0x01A5) -#define EVSYS_USERCCLLUT3A _SFR_MEM8(0x01A6) -#define EVSYS_USERCCLLUT3B _SFR_MEM8(0x01A7) -#define EVSYS_USERADC0 _SFR_MEM8(0x01A8) -#define EVSYS_USEREVOUTA _SFR_MEM8(0x01A9) -#define EVSYS_USEREVOUTB _SFR_MEM8(0x01AA) -#define EVSYS_USEREVOUTC _SFR_MEM8(0x01AB) -#define EVSYS_USEREVOUTD _SFR_MEM8(0x01AC) -#define EVSYS_USEREVOUTE _SFR_MEM8(0x01AD) -#define EVSYS_USEREVOUTF _SFR_MEM8(0x01AE) -#define EVSYS_USERUSART0 _SFR_MEM8(0x01AF) -#define EVSYS_USERUSART1 _SFR_MEM8(0x01B0) -#define EVSYS_USERUSART2 _SFR_MEM8(0x01B1) -#define EVSYS_USERUSART3 _SFR_MEM8(0x01B2) -#define EVSYS_USERTCA0 _SFR_MEM8(0x01B3) -#define EVSYS_USERTCB0 _SFR_MEM8(0x01B4) -#define EVSYS_USERTCB1 _SFR_MEM8(0x01B5) -#define EVSYS_USERTCB2 _SFR_MEM8(0x01B6) -#define EVSYS_USERTCB3 _SFR_MEM8(0x01B7) - - -/* CCL - Configurable Custom Logic */ -#define CCL_CTRLA _SFR_MEM8(0x01C0) -#define CCL_SEQCTRL0 _SFR_MEM8(0x01C1) -#define CCL_INTCTRL0 _SFR_MEM8(0x01C5) -#define CCL_INTFLAGS _SFR_MEM8(0x01C7) -#define CCL_LUT0CTRLA _SFR_MEM8(0x01C8) -#define CCL_LUT0CTRLB _SFR_MEM8(0x01C9) -#define CCL_LUT0CTRLC _SFR_MEM8(0x01CA) -#define CCL_TRUTH0 _SFR_MEM8(0x01CB) -#define CCL_LUT1CTRLA _SFR_MEM8(0x01CC) -#define CCL_LUT1CTRLB _SFR_MEM8(0x01CD) -#define CCL_LUT1CTRLC _SFR_MEM8(0x01CE) -#define CCL_TRUTH1 _SFR_MEM8(0x01CF) -#define CCL_LUT2CTRLA _SFR_MEM8(0x01D0) -#define CCL_LUT2CTRLB _SFR_MEM8(0x01D1) -#define CCL_LUT2CTRLC _SFR_MEM8(0x01D2) -#define CCL_TRUTH2 _SFR_MEM8(0x01D3) -#define CCL_LUT3CTRLA _SFR_MEM8(0x01D4) -#define CCL_LUT3CTRLB _SFR_MEM8(0x01D5) -#define CCL_LUT3CTRLC _SFR_MEM8(0x01D6) -#define CCL_TRUTH3 _SFR_MEM8(0x01D7) - - -/* PORT (PORTA) - I/O Ports */ -#define PORTA_DIR _SFR_MEM8(0x0400) -#define PORTA_DIRSET _SFR_MEM8(0x0401) -#define PORTA_DIRCLR _SFR_MEM8(0x0402) -#define PORTA_DIRTGL _SFR_MEM8(0x0403) -#define PORTA_OUT _SFR_MEM8(0x0404) -#define PORTA_OUTSET _SFR_MEM8(0x0405) -#define PORTA_OUTCLR _SFR_MEM8(0x0406) -#define PORTA_OUTTGL _SFR_MEM8(0x0407) -#define PORTA_IN _SFR_MEM8(0x0408) -#define PORTA_INTFLAGS _SFR_MEM8(0x0409) -#define PORTA_PORTCTRL _SFR_MEM8(0x040A) -#define PORTA_PIN0CTRL _SFR_MEM8(0x0410) -#define PORTA_PIN1CTRL _SFR_MEM8(0x0411) -#define PORTA_PIN2CTRL _SFR_MEM8(0x0412) -#define PORTA_PIN3CTRL _SFR_MEM8(0x0413) -#define PORTA_PIN4CTRL _SFR_MEM8(0x0414) -#define PORTA_PIN5CTRL _SFR_MEM8(0x0415) -#define PORTA_PIN6CTRL _SFR_MEM8(0x0416) -#define PORTA_PIN7CTRL _SFR_MEM8(0x0417) - - -/* PORT (PORTB) - I/O Ports */ -#define PORTB_DIR _SFR_MEM8(0x0420) -#define PORTB_DIRSET _SFR_MEM8(0x0421) -#define PORTB_DIRCLR _SFR_MEM8(0x0422) -#define PORTB_DIRTGL _SFR_MEM8(0x0423) -#define PORTB_OUT _SFR_MEM8(0x0424) -#define PORTB_OUTSET _SFR_MEM8(0x0425) -#define PORTB_OUTCLR _SFR_MEM8(0x0426) -#define PORTB_OUTTGL _SFR_MEM8(0x0427) -#define PORTB_IN _SFR_MEM8(0x0428) -#define PORTB_INTFLAGS _SFR_MEM8(0x0429) -#define PORTB_PORTCTRL _SFR_MEM8(0x042A) -#define PORTB_PIN0CTRL _SFR_MEM8(0x0430) -#define PORTB_PIN1CTRL _SFR_MEM8(0x0431) -#define PORTB_PIN2CTRL _SFR_MEM8(0x0432) -#define PORTB_PIN3CTRL _SFR_MEM8(0x0433) -#define PORTB_PIN4CTRL _SFR_MEM8(0x0434) -#define PORTB_PIN5CTRL _SFR_MEM8(0x0435) -#define PORTB_PIN6CTRL _SFR_MEM8(0x0436) -#define PORTB_PIN7CTRL _SFR_MEM8(0x0437) - - -/* PORT (PORTC) - I/O Ports */ -#define PORTC_DIR _SFR_MEM8(0x0440) -#define PORTC_DIRSET _SFR_MEM8(0x0441) -#define PORTC_DIRCLR _SFR_MEM8(0x0442) -#define PORTC_DIRTGL _SFR_MEM8(0x0443) -#define PORTC_OUT _SFR_MEM8(0x0444) -#define PORTC_OUTSET _SFR_MEM8(0x0445) -#define PORTC_OUTCLR _SFR_MEM8(0x0446) -#define PORTC_OUTTGL _SFR_MEM8(0x0447) -#define PORTC_IN _SFR_MEM8(0x0448) -#define PORTC_INTFLAGS _SFR_MEM8(0x0449) -#define PORTC_PORTCTRL _SFR_MEM8(0x044A) -#define PORTC_PIN0CTRL _SFR_MEM8(0x0450) -#define PORTC_PIN1CTRL _SFR_MEM8(0x0451) -#define PORTC_PIN2CTRL _SFR_MEM8(0x0452) -#define PORTC_PIN3CTRL _SFR_MEM8(0x0453) -#define PORTC_PIN4CTRL _SFR_MEM8(0x0454) -#define PORTC_PIN5CTRL _SFR_MEM8(0x0455) -#define PORTC_PIN6CTRL _SFR_MEM8(0x0456) -#define PORTC_PIN7CTRL _SFR_MEM8(0x0457) - - -/* PORT (PORTD) - I/O Ports */ -#define PORTD_DIR _SFR_MEM8(0x0460) -#define PORTD_DIRSET _SFR_MEM8(0x0461) -#define PORTD_DIRCLR _SFR_MEM8(0x0462) -#define PORTD_DIRTGL _SFR_MEM8(0x0463) -#define PORTD_OUT _SFR_MEM8(0x0464) -#define PORTD_OUTSET _SFR_MEM8(0x0465) -#define PORTD_OUTCLR _SFR_MEM8(0x0466) -#define PORTD_OUTTGL _SFR_MEM8(0x0467) -#define PORTD_IN _SFR_MEM8(0x0468) -#define PORTD_INTFLAGS _SFR_MEM8(0x0469) -#define PORTD_PORTCTRL _SFR_MEM8(0x046A) -#define PORTD_PIN0CTRL _SFR_MEM8(0x0470) -#define PORTD_PIN1CTRL _SFR_MEM8(0x0471) -#define PORTD_PIN2CTRL _SFR_MEM8(0x0472) -#define PORTD_PIN3CTRL _SFR_MEM8(0x0473) -#define PORTD_PIN4CTRL _SFR_MEM8(0x0474) -#define PORTD_PIN5CTRL _SFR_MEM8(0x0475) -#define PORTD_PIN6CTRL _SFR_MEM8(0x0476) -#define PORTD_PIN7CTRL _SFR_MEM8(0x0477) - - -/* PORT (PORTE) - I/O Ports */ -#define PORTE_DIR _SFR_MEM8(0x0480) -#define PORTE_DIRSET _SFR_MEM8(0x0481) -#define PORTE_DIRCLR _SFR_MEM8(0x0482) -#define PORTE_DIRTGL _SFR_MEM8(0x0483) -#define PORTE_OUT _SFR_MEM8(0x0484) -#define PORTE_OUTSET _SFR_MEM8(0x0485) -#define PORTE_OUTCLR _SFR_MEM8(0x0486) -#define PORTE_OUTTGL _SFR_MEM8(0x0487) -#define PORTE_IN _SFR_MEM8(0x0488) -#define PORTE_INTFLAGS _SFR_MEM8(0x0489) -#define PORTE_PORTCTRL _SFR_MEM8(0x048A) -#define PORTE_PIN0CTRL _SFR_MEM8(0x0490) -#define PORTE_PIN1CTRL _SFR_MEM8(0x0491) -#define PORTE_PIN2CTRL _SFR_MEM8(0x0492) -#define PORTE_PIN3CTRL _SFR_MEM8(0x0493) -#define PORTE_PIN4CTRL _SFR_MEM8(0x0494) -#define PORTE_PIN5CTRL _SFR_MEM8(0x0495) -#define PORTE_PIN6CTRL _SFR_MEM8(0x0496) -#define PORTE_PIN7CTRL _SFR_MEM8(0x0497) - - -/* PORT (PORTF) - I/O Ports */ -#define PORTF_DIR _SFR_MEM8(0x04A0) -#define PORTF_DIRSET _SFR_MEM8(0x04A1) -#define PORTF_DIRCLR _SFR_MEM8(0x04A2) -#define PORTF_DIRTGL _SFR_MEM8(0x04A3) -#define PORTF_OUT _SFR_MEM8(0x04A4) -#define PORTF_OUTSET _SFR_MEM8(0x04A5) -#define PORTF_OUTCLR _SFR_MEM8(0x04A6) -#define PORTF_OUTTGL _SFR_MEM8(0x04A7) -#define PORTF_IN _SFR_MEM8(0x04A8) -#define PORTF_INTFLAGS _SFR_MEM8(0x04A9) -#define PORTF_PORTCTRL _SFR_MEM8(0x04AA) -#define PORTF_PIN0CTRL _SFR_MEM8(0x04B0) -#define PORTF_PIN1CTRL _SFR_MEM8(0x04B1) -#define PORTF_PIN2CTRL _SFR_MEM8(0x04B2) -#define PORTF_PIN3CTRL _SFR_MEM8(0x04B3) -#define PORTF_PIN4CTRL _SFR_MEM8(0x04B4) -#define PORTF_PIN5CTRL _SFR_MEM8(0x04B5) -#define PORTF_PIN6CTRL _SFR_MEM8(0x04B6) -#define PORTF_PIN7CTRL _SFR_MEM8(0x04B7) - - -/* PORTMUX - Port Multiplexer */ -#define PORTMUX_EVSYSROUTEA _SFR_MEM8(0x05E0) -#define PORTMUX_CCLROUTEA _SFR_MEM8(0x05E1) -#define PORTMUX_USARTROUTEA _SFR_MEM8(0x05E2) -#define PORTMUX_TWISPIROUTEA _SFR_MEM8(0x05E3) -#define PORTMUX_TCAROUTEA _SFR_MEM8(0x05E4) -#define PORTMUX_TCBROUTEA _SFR_MEM8(0x05E5) - - -/* ADC (ADC0) - Analog to Digital Converter */ -#define ADC0_CTRLA _SFR_MEM8(0x0600) -#define ADC0_CTRLB _SFR_MEM8(0x0601) -#define ADC0_CTRLC _SFR_MEM8(0x0602) -#define ADC0_CTRLD _SFR_MEM8(0x0603) -#define ADC0_CTRLE _SFR_MEM8(0x0604) -#define ADC0_SAMPCTRL _SFR_MEM8(0x0605) -#define ADC0_MUXPOS _SFR_MEM8(0x0606) -#define ADC0_COMMAND _SFR_MEM8(0x0608) -#define ADC0_EVCTRL _SFR_MEM8(0x0609) -#define ADC0_INTCTRL _SFR_MEM8(0x060A) -#define ADC0_INTFLAGS _SFR_MEM8(0x060B) -#define ADC0_DBGCTRL _SFR_MEM8(0x060C) -#define ADC0_TEMP _SFR_MEM8(0x060D) -#define ADC0_RES _SFR_MEM16(0x0610) -#define ADC0_RESL _SFR_MEM8(0x0610) -#define ADC0_RESH _SFR_MEM8(0x0611) -#define ADC0_WINLT _SFR_MEM16(0x0612) -#define ADC0_WINLTL _SFR_MEM8(0x0612) -#define ADC0_WINLTH _SFR_MEM8(0x0613) -#define ADC0_WINHT _SFR_MEM16(0x0614) -#define ADC0_WINHTL _SFR_MEM8(0x0614) -#define ADC0_WINHTH _SFR_MEM8(0x0615) -#define ADC0_CALIB _SFR_MEM8(0x0616) - - -/* AC (AC0) - Analog Comparator */ -#define AC0_CTRLA _SFR_MEM8(0x0680) -#define AC0_MUXCTRLA _SFR_MEM8(0x0682) -#define AC0_DACREF _SFR_MEM8(0x0684) -#define AC0_INTCTRL _SFR_MEM8(0x0686) -#define AC0_STATUS _SFR_MEM8(0x0687) - - -/* USART (USART0) - Universal Synchronous and Asynchronous Receiver and Transmitter */ -#define USART0_RXDATAL _SFR_MEM8(0x0800) -#define USART0_RXDATAH _SFR_MEM8(0x0801) -#define USART0_TXDATAL _SFR_MEM8(0x0802) -#define USART0_TXDATAH _SFR_MEM8(0x0803) -#define USART0_STATUS _SFR_MEM8(0x0804) -#define USART0_CTRLA _SFR_MEM8(0x0805) -#define USART0_CTRLB _SFR_MEM8(0x0806) -#define USART0_CTRLC _SFR_MEM8(0x0807) -#define USART0_BAUD _SFR_MEM16(0x0808) -#define USART0_BAUDL _SFR_MEM8(0x0808) -#define USART0_BAUDH _SFR_MEM8(0x0809) -#define USART0_CTRLD _SFR_MEM8(0x080A) -#define USART0_DBGCTRL _SFR_MEM8(0x080B) -#define USART0_EVCTRL _SFR_MEM8(0x080C) -#define USART0_TXPLCTRL _SFR_MEM8(0x080D) -#define USART0_RXPLCTRL _SFR_MEM8(0x080E) - - -/* USART (USART1) - Universal Synchronous and Asynchronous Receiver and Transmitter */ -#define USART1_RXDATAL _SFR_MEM8(0x0820) -#define USART1_RXDATAH _SFR_MEM8(0x0821) -#define USART1_TXDATAL _SFR_MEM8(0x0822) -#define USART1_TXDATAH _SFR_MEM8(0x0823) -#define USART1_STATUS _SFR_MEM8(0x0824) -#define USART1_CTRLA _SFR_MEM8(0x0825) -#define USART1_CTRLB _SFR_MEM8(0x0826) -#define USART1_CTRLC _SFR_MEM8(0x0827) -#define USART1_BAUD _SFR_MEM16(0x0828) -#define USART1_BAUDL _SFR_MEM8(0x0828) -#define USART1_BAUDH _SFR_MEM8(0x0829) -#define USART1_CTRLD _SFR_MEM8(0x082A) -#define USART1_DBGCTRL _SFR_MEM8(0x082B) -#define USART1_EVCTRL _SFR_MEM8(0x082C) -#define USART1_TXPLCTRL _SFR_MEM8(0x082D) -#define USART1_RXPLCTRL _SFR_MEM8(0x082E) - - -/* USART (USART2) - Universal Synchronous and Asynchronous Receiver and Transmitter */ -#define USART2_RXDATAL _SFR_MEM8(0x0840) -#define USART2_RXDATAH _SFR_MEM8(0x0841) -#define USART2_TXDATAL _SFR_MEM8(0x0842) -#define USART2_TXDATAH _SFR_MEM8(0x0843) -#define USART2_STATUS _SFR_MEM8(0x0844) -#define USART2_CTRLA _SFR_MEM8(0x0845) -#define USART2_CTRLB _SFR_MEM8(0x0846) -#define USART2_CTRLC _SFR_MEM8(0x0847) -#define USART2_BAUD _SFR_MEM16(0x0848) -#define USART2_BAUDL _SFR_MEM8(0x0848) -#define USART2_BAUDH _SFR_MEM8(0x0849) -#define USART2_CTRLD _SFR_MEM8(0x084A) -#define USART2_DBGCTRL _SFR_MEM8(0x084B) -#define USART2_EVCTRL _SFR_MEM8(0x084C) -#define USART2_TXPLCTRL _SFR_MEM8(0x084D) -#define USART2_RXPLCTRL _SFR_MEM8(0x084E) - - -/* TWI (TWI0) - Two-Wire Interface */ -#define TWI0_CTRLA _SFR_MEM8(0x08A0) -#define TWI0_BRIDGECTRL _SFR_MEM8(0x08A1) -#define TWI0_DBGCTRL _SFR_MEM8(0x08A2) -#define TWI0_MCTRLA _SFR_MEM8(0x08A3) -#define TWI0_MCTRLB _SFR_MEM8(0x08A4) -#define TWI0_MSTATUS _SFR_MEM8(0x08A5) -#define TWI0_MBAUD _SFR_MEM8(0x08A6) -#define TWI0_MADDR _SFR_MEM8(0x08A7) -#define TWI0_MDATA _SFR_MEM8(0x08A8) -#define TWI0_SCTRLA _SFR_MEM8(0x08A9) -#define TWI0_SCTRLB _SFR_MEM8(0x08AA) -#define TWI0_SSTATUS _SFR_MEM8(0x08AB) -#define TWI0_SADDR _SFR_MEM8(0x08AC) -#define TWI0_SDATA _SFR_MEM8(0x08AD) -#define TWI0_SADDRMASK _SFR_MEM8(0x08AE) - - -/* SPI (SPI0) - Serial Peripheral Interface */ -#define SPI0_CTRLA _SFR_MEM8(0x08C0) -#define SPI0_CTRLB _SFR_MEM8(0x08C1) -#define SPI0_INTCTRL _SFR_MEM8(0x08C2) -#define SPI0_INTFLAGS _SFR_MEM8(0x08C3) -#define SPI0_DATA _SFR_MEM8(0x08C4) - - -/* TCA (TCA0) - 16-bit Timer/Counter Type A */ -#define TCA0_SINGLE_CTRLA _SFR_MEM8(0x0A00) -#define TCA0_SINGLE_CTRLB _SFR_MEM8(0x0A01) -#define TCA0_SINGLE_CTRLC _SFR_MEM8(0x0A02) -#define TCA0_SINGLE_CTRLD _SFR_MEM8(0x0A03) -#define TCA0_SINGLE_CTRLECLR _SFR_MEM8(0x0A04) -#define TCA0_SINGLE_CTRLESET _SFR_MEM8(0x0A05) -#define TCA0_SINGLE_CTRLFCLR _SFR_MEM8(0x0A06) -#define TCA0_SINGLE_CTRLFSET _SFR_MEM8(0x0A07) -#define TCA0_SINGLE_EVCTRL _SFR_MEM8(0x0A09) -#define TCA0_SINGLE_INTCTRL _SFR_MEM8(0x0A0A) -#define TCA0_SINGLE_INTFLAGS _SFR_MEM8(0x0A0B) -#define TCA0_SINGLE_DBGCTRL _SFR_MEM8(0x0A0E) -#define TCA0_SINGLE_TEMP _SFR_MEM8(0x0A0F) -#define TCA0_SINGLE_CNT _SFR_MEM16(0x0A20) -#define TCA0_SINGLE_PER _SFR_MEM16(0x0A26) -#define TCA0_SINGLE_CMP0 _SFR_MEM16(0x0A28) -#define TCA0_SINGLE_CMP1 _SFR_MEM16(0x0A2A) -#define TCA0_SINGLE_CMP2 _SFR_MEM16(0x0A2C) -#define TCA0_SINGLE_PERBUF _SFR_MEM16(0x0A36) -#define TCA0_SINGLE_CMP0BUF _SFR_MEM16(0x0A38) -#define TCA0_SINGLE_CMP1BUF _SFR_MEM16(0x0A3A) -#define TCA0_SINGLE_CMP2BUF _SFR_MEM16(0x0A3C) - - -#define TCA0_SPLIT_CTRLA _SFR_MEM8(0x0A00) -#define TCA0_SPLIT_CTRLB _SFR_MEM8(0x0A01) -#define TCA0_SPLIT_CTRLC _SFR_MEM8(0x0A02) -#define TCA0_SPLIT_CTRLD _SFR_MEM8(0x0A03) -#define TCA0_SPLIT_CTRLECLR _SFR_MEM8(0x0A04) -#define TCA0_SPLIT_CTRLESET _SFR_MEM8(0x0A05) -#define TCA0_SPLIT_INTCTRL _SFR_MEM8(0x0A0A) -#define TCA0_SPLIT_INTFLAGS _SFR_MEM8(0x0A0B) -#define TCA0_SPLIT_DBGCTRL _SFR_MEM8(0x0A0E) -#define TCA0_SPLIT_LCNT _SFR_MEM8(0x0A20) -#define TCA0_SPLIT_HCNT _SFR_MEM8(0x0A21) -#define TCA0_SPLIT_LPER _SFR_MEM8(0x0A26) -#define TCA0_SPLIT_HPER _SFR_MEM8(0x0A27) -#define TCA0_SPLIT_LCMP0 _SFR_MEM8(0x0A28) -#define TCA0_SPLIT_HCMP0 _SFR_MEM8(0x0A29) -#define TCA0_SPLIT_LCMP1 _SFR_MEM8(0x0A2A) -#define TCA0_SPLIT_HCMP1 _SFR_MEM8(0x0A2B) -#define TCA0_SPLIT_LCMP2 _SFR_MEM8(0x0A2C) -#define TCA0_SPLIT_HCMP2 _SFR_MEM8(0x0A2D) - - - - -/* TCB (TCB0) - 16-bit Timer Type B */ -#define TCB0_CTRLA _SFR_MEM8(0x0A80) -#define TCB0_CTRLB _SFR_MEM8(0x0A81) -#define TCB0_EVCTRL _SFR_MEM8(0x0A84) -#define TCB0_INTCTRL _SFR_MEM8(0x0A85) -#define TCB0_INTFLAGS _SFR_MEM8(0x0A86) -#define TCB0_STATUS _SFR_MEM8(0x0A87) -#define TCB0_DBGCTRL _SFR_MEM8(0x0A88) -#define TCB0_TEMP _SFR_MEM8(0x0A89) -#define TCB0_CNT _SFR_MEM16(0x0A8A) -#define TCB0_CNTL _SFR_MEM8(0x0A8A) -#define TCB0_CNTH _SFR_MEM8(0x0A8B) -#define TCB0_CCMP _SFR_MEM16(0x0A8C) -#define TCB0_CCMPL _SFR_MEM8(0x0A8C) -#define TCB0_CCMPH _SFR_MEM8(0x0A8D) - - -/* TCB (TCB1) - 16-bit Timer Type B */ -#define TCB1_CTRLA _SFR_MEM8(0x0A90) -#define TCB1_CTRLB _SFR_MEM8(0x0A91) -#define TCB1_EVCTRL _SFR_MEM8(0x0A94) -#define TCB1_INTCTRL _SFR_MEM8(0x0A95) -#define TCB1_INTFLAGS _SFR_MEM8(0x0A96) -#define TCB1_STATUS _SFR_MEM8(0x0A97) -#define TCB1_DBGCTRL _SFR_MEM8(0x0A98) -#define TCB1_TEMP _SFR_MEM8(0x0A99) -#define TCB1_CNT _SFR_MEM16(0x0A9A) -#define TCB1_CNTL _SFR_MEM8(0x0A9A) -#define TCB1_CNTH _SFR_MEM8(0x0A9B) -#define TCB1_CCMP _SFR_MEM16(0x0A9C) -#define TCB1_CCMPL _SFR_MEM8(0x0A9C) -#define TCB1_CCMPH _SFR_MEM8(0x0A9D) - - -/* TCB (TCB2) - 16-bit Timer Type B */ -#define TCB2_CTRLA _SFR_MEM8(0x0AA0) -#define TCB2_CTRLB _SFR_MEM8(0x0AA1) -#define TCB2_EVCTRL _SFR_MEM8(0x0AA4) -#define TCB2_INTCTRL _SFR_MEM8(0x0AA5) -#define TCB2_INTFLAGS _SFR_MEM8(0x0AA6) -#define TCB2_STATUS _SFR_MEM8(0x0AA7) -#define TCB2_DBGCTRL _SFR_MEM8(0x0AA8) -#define TCB2_TEMP _SFR_MEM8(0x0AA9) -#define TCB2_CNT _SFR_MEM16(0x0AAA) -#define TCB2_CNTL _SFR_MEM8(0x0AAA) -#define TCB2_CNTH _SFR_MEM8(0x0AAB) -#define TCB2_CCMP _SFR_MEM16(0x0AAC) -#define TCB2_CCMPL _SFR_MEM8(0x0AAC) -#define TCB2_CCMPH _SFR_MEM8(0x0AAD) - - -/* SYSCFG - System Configuration Registers */ -#define SYSCFG_REVID _SFR_MEM8(0x0F01) -#define SYSCFG_EXTBRK _SFR_MEM8(0x0F02) -#define SYSCFG_OCDM _SFR_MEM8(0x0F18) -#define SYSCFG_OCDMS _SFR_MEM8(0x0F19) - - -/* NVMCTRL - Non-volatile Memory Controller */ -#define NVMCTRL_CTRLA _SFR_MEM8(0x1000) -#define NVMCTRL_CTRLB _SFR_MEM8(0x1001) -#define NVMCTRL_STATUS _SFR_MEM8(0x1002) -#define NVMCTRL_INTCTRL _SFR_MEM8(0x1003) -#define NVMCTRL_INTFLAGS _SFR_MEM8(0x1004) -#define NVMCTRL_DATA _SFR_MEM16(0x1006) -#define NVMCTRL_DATAL _SFR_MEM8(0x1006) -#define NVMCTRL_DATAH _SFR_MEM8(0x1007) -#define NVMCTRL_ADDR _SFR_MEM16(0x1008) -#define NVMCTRL_ADDRL _SFR_MEM8(0x1008) -#define NVMCTRL_ADDRH _SFR_MEM8(0x1009) - - -/* SIGROW - Signature row */ -#define SIGROW_DEVICEID0 _SFR_MEM8(0x1100) -#define SIGROW_DEVICEID1 _SFR_MEM8(0x1101) -#define SIGROW_DEVICEID2 _SFR_MEM8(0x1102) -#define SIGROW_SERNUM0 _SFR_MEM8(0x1103) -#define SIGROW_SERNUM1 _SFR_MEM8(0x1104) -#define SIGROW_SERNUM2 _SFR_MEM8(0x1105) -#define SIGROW_SERNUM3 _SFR_MEM8(0x1106) -#define SIGROW_SERNUM4 _SFR_MEM8(0x1107) -#define SIGROW_SERNUM5 _SFR_MEM8(0x1108) -#define SIGROW_SERNUM6 _SFR_MEM8(0x1109) -#define SIGROW_SERNUM7 _SFR_MEM8(0x110A) -#define SIGROW_SERNUM8 _SFR_MEM8(0x110B) -#define SIGROW_SERNUM9 _SFR_MEM8(0x110C) -#define SIGROW_OSCCAL32K _SFR_MEM8(0x1114) -#define SIGROW_OSCCAL16M0 _SFR_MEM8(0x1118) -#define SIGROW_OSCCAL16M1 _SFR_MEM8(0x1119) -#define SIGROW_OSCCAL20M0 _SFR_MEM8(0x111A) -#define SIGROW_OSCCAL20M1 _SFR_MEM8(0x111B) -#define SIGROW_TEMPSENSE0 _SFR_MEM8(0x1120) -#define SIGROW_TEMPSENSE1 _SFR_MEM8(0x1121) -#define SIGROW_OSC16ERR3V _SFR_MEM8(0x1122) -#define SIGROW_OSC16ERR5V _SFR_MEM8(0x1123) -#define SIGROW_OSC20ERR3V _SFR_MEM8(0x1124) -#define SIGROW_OSC20ERR5V _SFR_MEM8(0x1125) -#define SIGROW_CHECKSUM1 _SFR_MEM8(0x112F) - - -/* FUSE - Fuses */ -#define FUSE_WDTCFG _SFR_MEM8(0x1280) -#define FUSE_BODCFG _SFR_MEM8(0x1281) -#define FUSE_OSCCFG _SFR_MEM8(0x1282) -#define FUSE_TCD0CFG _SFR_MEM8(0x1284) -#define FUSE_SYSCFG0 _SFR_MEM8(0x1285) -#define FUSE_SYSCFG1 _SFR_MEM8(0x1286) -#define FUSE_APPEND _SFR_MEM8(0x1287) -#define FUSE_BOOTEND _SFR_MEM8(0x1288) - - -/* LOCKBIT - Lockbit */ -#define LOCKBIT_LOCKBIT _SFR_MEM8(0x128A) - - -/* USERROW - User Row */ -#define USERROW_USERROW0 _SFR_MEM8(0x1300) -#define USERROW_USERROW1 _SFR_MEM8(0x1301) -#define USERROW_USERROW2 _SFR_MEM8(0x1302) -#define USERROW_USERROW3 _SFR_MEM8(0x1303) -#define USERROW_USERROW4 _SFR_MEM8(0x1304) -#define USERROW_USERROW5 _SFR_MEM8(0x1305) -#define USERROW_USERROW6 _SFR_MEM8(0x1306) -#define USERROW_USERROW7 _SFR_MEM8(0x1307) -#define USERROW_USERROW8 _SFR_MEM8(0x1308) -#define USERROW_USERROW9 _SFR_MEM8(0x1309) -#define USERROW_USERROW10 _SFR_MEM8(0x130A) -#define USERROW_USERROW11 _SFR_MEM8(0x130B) -#define USERROW_USERROW12 _SFR_MEM8(0x130C) -#define USERROW_USERROW13 _SFR_MEM8(0x130D) -#define USERROW_USERROW14 _SFR_MEM8(0x130E) -#define USERROW_USERROW15 _SFR_MEM8(0x130F) -#define USERROW_USERROW16 _SFR_MEM8(0x1310) -#define USERROW_USERROW17 _SFR_MEM8(0x1311) -#define USERROW_USERROW18 _SFR_MEM8(0x1312) -#define USERROW_USERROW19 _SFR_MEM8(0x1313) -#define USERROW_USERROW20 _SFR_MEM8(0x1314) -#define USERROW_USERROW21 _SFR_MEM8(0x1315) -#define USERROW_USERROW22 _SFR_MEM8(0x1316) -#define USERROW_USERROW23 _SFR_MEM8(0x1317) -#define USERROW_USERROW24 _SFR_MEM8(0x1318) -#define USERROW_USERROW25 _SFR_MEM8(0x1319) -#define USERROW_USERROW26 _SFR_MEM8(0x131A) -#define USERROW_USERROW27 _SFR_MEM8(0x131B) -#define USERROW_USERROW28 _SFR_MEM8(0x131C) -#define USERROW_USERROW29 _SFR_MEM8(0x131D) -#define USERROW_USERROW30 _SFR_MEM8(0x131E) -#define USERROW_USERROW31 _SFR_MEM8(0x131F) -#define USERROW_USERROW32 _SFR_MEM8(0x1320) -#define USERROW_USERROW33 _SFR_MEM8(0x1321) -#define USERROW_USERROW34 _SFR_MEM8(0x1322) -#define USERROW_USERROW35 _SFR_MEM8(0x1323) -#define USERROW_USERROW36 _SFR_MEM8(0x1324) -#define USERROW_USERROW37 _SFR_MEM8(0x1325) -#define USERROW_USERROW38 _SFR_MEM8(0x1326) -#define USERROW_USERROW39 _SFR_MEM8(0x1327) -#define USERROW_USERROW40 _SFR_MEM8(0x1328) -#define USERROW_USERROW41 _SFR_MEM8(0x1329) -#define USERROW_USERROW42 _SFR_MEM8(0x132A) -#define USERROW_USERROW43 _SFR_MEM8(0x132B) -#define USERROW_USERROW44 _SFR_MEM8(0x132C) -#define USERROW_USERROW45 _SFR_MEM8(0x132D) -#define USERROW_USERROW46 _SFR_MEM8(0x132E) -#define USERROW_USERROW47 _SFR_MEM8(0x132F) -#define USERROW_USERROW48 _SFR_MEM8(0x1330) -#define USERROW_USERROW49 _SFR_MEM8(0x1331) -#define USERROW_USERROW50 _SFR_MEM8(0x1332) -#define USERROW_USERROW51 _SFR_MEM8(0x1333) -#define USERROW_USERROW52 _SFR_MEM8(0x1334) -#define USERROW_USERROW53 _SFR_MEM8(0x1335) -#define USERROW_USERROW54 _SFR_MEM8(0x1336) -#define USERROW_USERROW55 _SFR_MEM8(0x1337) -#define USERROW_USERROW56 _SFR_MEM8(0x1338) -#define USERROW_USERROW57 _SFR_MEM8(0x1339) -#define USERROW_USERROW58 _SFR_MEM8(0x133A) -#define USERROW_USERROW59 _SFR_MEM8(0x133B) -#define USERROW_USERROW60 _SFR_MEM8(0x133C) -#define USERROW_USERROW61 _SFR_MEM8(0x133D) -#define USERROW_USERROW62 _SFR_MEM8(0x133E) -#define USERROW_USERROW63 _SFR_MEM8(0x133F) - - - -/*================== Bitfield Definitions ================== */ - -/* AC - Analog Comparator */ -/* AC.CTRLA bit masks and bit positions */ -#define AC_ENABLE_bm 0x01 /* Enable bit mask. */ -#define AC_ENABLE_bp 0 /* Enable bit position. */ -#define AC_HYSMODE_gm 0x06 /* Hysteresis Mode group mask. */ -#define AC_HYSMODE_gp 1 /* Hysteresis Mode group position. */ -#define AC_HYSMODE0_bm (1<<1) /* Hysteresis Mode bit 0 mask. */ -#define AC_HYSMODE0_bp 1 /* Hysteresis Mode bit 0 position. */ -#define AC_HYSMODE1_bm (1<<2) /* Hysteresis Mode bit 1 mask. */ -#define AC_HYSMODE1_bp 2 /* Hysteresis Mode bit 1 position. */ -#define AC_LPMODE_bm 0x08 /* Low Power Mode bit mask. */ -#define AC_LPMODE_bp 3 /* Low Power Mode bit position. */ -#define AC_INTMODE_gm 0x30 /* Interrupt Mode group mask. */ -#define AC_INTMODE_gp 4 /* Interrupt Mode group position. */ -#define AC_INTMODE0_bm (1<<4) /* Interrupt Mode bit 0 mask. */ -#define AC_INTMODE0_bp 4 /* Interrupt Mode bit 0 position. */ -#define AC_INTMODE1_bm (1<<5) /* Interrupt Mode bit 1 mask. */ -#define AC_INTMODE1_bp 5 /* Interrupt Mode bit 1 position. */ -#define AC_OUTEN_bm 0x40 /* Output Buffer Enable bit mask. */ -#define AC_OUTEN_bp 6 /* Output Buffer Enable bit position. */ -#define AC_RUNSTDBY_bm 0x80 /* Run in Standby Mode bit mask. */ -#define AC_RUNSTDBY_bp 7 /* Run in Standby Mode bit position. */ - -/* AC.MUXCTRLA bit masks and bit positions */ -#define AC_MUXNEG_gm 0x03 /* Negative Input MUX Selection group mask. */ -#define AC_MUXNEG_gp 0 /* Negative Input MUX Selection group position. */ -#define AC_MUXNEG0_bm (1<<0) /* Negative Input MUX Selection bit 0 mask. */ -#define AC_MUXNEG0_bp 0 /* Negative Input MUX Selection bit 0 position. */ -#define AC_MUXNEG1_bm (1<<1) /* Negative Input MUX Selection bit 1 mask. */ -#define AC_MUXNEG1_bp 1 /* Negative Input MUX Selection bit 1 position. */ -#define AC_MUXPOS_gm 0x18 /* Positive Input MUX Selection group mask. */ -#define AC_MUXPOS_gp 3 /* Positive Input MUX Selection group position. */ -#define AC_MUXPOS0_bm (1<<3) /* Positive Input MUX Selection bit 0 mask. */ -#define AC_MUXPOS0_bp 3 /* Positive Input MUX Selection bit 0 position. */ -#define AC_MUXPOS1_bm (1<<4) /* Positive Input MUX Selection bit 1 mask. */ -#define AC_MUXPOS1_bp 4 /* Positive Input MUX Selection bit 1 position. */ -#define AC_INVERT_bm 0x80 /* Invert AC Output bit mask. */ -#define AC_INVERT_bp 7 /* Invert AC Output bit position. */ - -/* AC.DACREF bit masks and bit positions */ -#define AC_DATA_gm 0xFF /* DAC voltage reference group mask. */ -#define AC_DATA_gp 0 /* DAC voltage reference group position. */ -#define AC_DATA0_bm (1<<0) /* DAC voltage reference bit 0 mask. */ -#define AC_DATA0_bp 0 /* DAC voltage reference bit 0 position. */ -#define AC_DATA1_bm (1<<1) /* DAC voltage reference bit 1 mask. */ -#define AC_DATA1_bp 1 /* DAC voltage reference bit 1 position. */ -#define AC_DATA2_bm (1<<2) /* DAC voltage reference bit 2 mask. */ -#define AC_DATA2_bp 2 /* DAC voltage reference bit 2 position. */ -#define AC_DATA3_bm (1<<3) /* DAC voltage reference bit 3 mask. */ -#define AC_DATA3_bp 3 /* DAC voltage reference bit 3 position. */ -#define AC_DATA4_bm (1<<4) /* DAC voltage reference bit 4 mask. */ -#define AC_DATA4_bp 4 /* DAC voltage reference bit 4 position. */ -#define AC_DATA5_bm (1<<5) /* DAC voltage reference bit 5 mask. */ -#define AC_DATA5_bp 5 /* DAC voltage reference bit 5 position. */ -#define AC_DATA6_bm (1<<6) /* DAC voltage reference bit 6 mask. */ -#define AC_DATA6_bp 6 /* DAC voltage reference bit 6 position. */ -#define AC_DATA7_bm (1<<7) /* DAC voltage reference bit 7 mask. */ -#define AC_DATA7_bp 7 /* DAC voltage reference bit 7 position. */ - -/* AC.INTCTRL bit masks and bit positions */ -#define AC_CMP_bm 0x01 /* Analog Comparator 0 Interrupt Enable bit mask. */ -#define AC_CMP_bp 0 /* Analog Comparator 0 Interrupt Enable bit position. */ - -/* AC.STATUS bit masks and bit positions */ -/* AC_CMP is already defined. */ -#define AC_STATE_bm 0x10 /* Analog Comparator State bit mask. */ -#define AC_STATE_bp 4 /* Analog Comparator State bit position. */ - -/* ADC - Analog to Digital Converter */ -/* ADC.CTRLA bit masks and bit positions */ -#define ADC_ENABLE_bm 0x01 /* ADC Enable bit mask. */ -#define ADC_ENABLE_bp 0 /* ADC Enable bit position. */ -#define ADC_FREERUN_bm 0x02 /* ADC Freerun mode bit mask. */ -#define ADC_FREERUN_bp 1 /* ADC Freerun mode bit position. */ -#define ADC_RESSEL_bm 0x04 /* ADC Resolution bit mask. */ -#define ADC_RESSEL_bp 2 /* ADC Resolution bit position. */ -#define ADC_RUNSTBY_bm 0x80 /* Run standby mode bit mask. */ -#define ADC_RUNSTBY_bp 7 /* Run standby mode bit position. */ - -/* ADC.CTRLB bit masks and bit positions */ -#define ADC_SAMPNUM_gm 0x07 /* Accumulation Samples group mask. */ -#define ADC_SAMPNUM_gp 0 /* Accumulation Samples group position. */ -#define ADC_SAMPNUM0_bm (1<<0) /* Accumulation Samples bit 0 mask. */ -#define ADC_SAMPNUM0_bp 0 /* Accumulation Samples bit 0 position. */ -#define ADC_SAMPNUM1_bm (1<<1) /* Accumulation Samples bit 1 mask. */ -#define ADC_SAMPNUM1_bp 1 /* Accumulation Samples bit 1 position. */ -#define ADC_SAMPNUM2_bm (1<<2) /* Accumulation Samples bit 2 mask. */ -#define ADC_SAMPNUM2_bp 2 /* Accumulation Samples bit 2 position. */ - -/* ADC.CTRLC bit masks and bit positions */ -#define ADC_PRESC_gm 0x07 /* Clock Pre-scaler group mask. */ -#define ADC_PRESC_gp 0 /* Clock Pre-scaler group position. */ -#define ADC_PRESC0_bm (1<<0) /* Clock Pre-scaler bit 0 mask. */ -#define ADC_PRESC0_bp 0 /* Clock Pre-scaler bit 0 position. */ -#define ADC_PRESC1_bm (1<<1) /* Clock Pre-scaler bit 1 mask. */ -#define ADC_PRESC1_bp 1 /* Clock Pre-scaler bit 1 position. */ -#define ADC_PRESC2_bm (1<<2) /* Clock Pre-scaler bit 2 mask. */ -#define ADC_PRESC2_bp 2 /* Clock Pre-scaler bit 2 position. */ -#define ADC_REFSEL_gm 0x30 /* Reference Selection group mask. */ -#define ADC_REFSEL_gp 4 /* Reference Selection group position. */ -#define ADC_REFSEL0_bm (1<<4) /* Reference Selection bit 0 mask. */ -#define ADC_REFSEL0_bp 4 /* Reference Selection bit 0 position. */ -#define ADC_REFSEL1_bm (1<<5) /* Reference Selection bit 1 mask. */ -#define ADC_REFSEL1_bp 5 /* Reference Selection bit 1 position. */ -#define ADC_SAMPCAP_bm 0x40 /* Sample Capacitance Selection bit mask. */ -#define ADC_SAMPCAP_bp 6 /* Sample Capacitance Selection bit position. */ - -/* ADC.CTRLD bit masks and bit positions */ -#define ADC_SAMPDLY_gm 0x0F /* Sampling Delay Selection group mask. */ -#define ADC_SAMPDLY_gp 0 /* Sampling Delay Selection group position. */ -#define ADC_SAMPDLY0_bm (1<<0) /* Sampling Delay Selection bit 0 mask. */ -#define ADC_SAMPDLY0_bp 0 /* Sampling Delay Selection bit 0 position. */ -#define ADC_SAMPDLY1_bm (1<<1) /* Sampling Delay Selection bit 1 mask. */ -#define ADC_SAMPDLY1_bp 1 /* Sampling Delay Selection bit 1 position. */ -#define ADC_SAMPDLY2_bm (1<<2) /* Sampling Delay Selection bit 2 mask. */ -#define ADC_SAMPDLY2_bp 2 /* Sampling Delay Selection bit 2 position. */ -#define ADC_SAMPDLY3_bm (1<<3) /* Sampling Delay Selection bit 3 mask. */ -#define ADC_SAMPDLY3_bp 3 /* Sampling Delay Selection bit 3 position. */ -#define ADC_ASDV_bm 0x10 /* Automatic Sampling Delay Variation bit mask. */ -#define ADC_ASDV_bp 4 /* Automatic Sampling Delay Variation bit position. */ -#define ADC_INITDLY_gm 0xE0 /* Initial Delay Selection group mask. */ -#define ADC_INITDLY_gp 5 /* Initial Delay Selection group position. */ -#define ADC_INITDLY0_bm (1<<5) /* Initial Delay Selection bit 0 mask. */ -#define ADC_INITDLY0_bp 5 /* Initial Delay Selection bit 0 position. */ -#define ADC_INITDLY1_bm (1<<6) /* Initial Delay Selection bit 1 mask. */ -#define ADC_INITDLY1_bp 6 /* Initial Delay Selection bit 1 position. */ -#define ADC_INITDLY2_bm (1<<7) /* Initial Delay Selection bit 2 mask. */ -#define ADC_INITDLY2_bp 7 /* Initial Delay Selection bit 2 position. */ - -/* ADC.CTRLE bit masks and bit positions */ -#define ADC_WINCM_gm 0x07 /* Window Comparator Mode group mask. */ -#define ADC_WINCM_gp 0 /* Window Comparator Mode group position. */ -#define ADC_WINCM0_bm (1<<0) /* Window Comparator Mode bit 0 mask. */ -#define ADC_WINCM0_bp 0 /* Window Comparator Mode bit 0 position. */ -#define ADC_WINCM1_bm (1<<1) /* Window Comparator Mode bit 1 mask. */ -#define ADC_WINCM1_bp 1 /* Window Comparator Mode bit 1 position. */ -#define ADC_WINCM2_bm (1<<2) /* Window Comparator Mode bit 2 mask. */ -#define ADC_WINCM2_bp 2 /* Window Comparator Mode bit 2 position. */ - -/* ADC.SAMPCTRL bit masks and bit positions */ -#define ADC_SAMPLEN_gm 0x1F /* Sample lenght group mask. */ -#define ADC_SAMPLEN_gp 0 /* Sample lenght group position. */ -#define ADC_SAMPLEN0_bm (1<<0) /* Sample lenght bit 0 mask. */ -#define ADC_SAMPLEN0_bp 0 /* Sample lenght bit 0 position. */ -#define ADC_SAMPLEN1_bm (1<<1) /* Sample lenght bit 1 mask. */ -#define ADC_SAMPLEN1_bp 1 /* Sample lenght bit 1 position. */ -#define ADC_SAMPLEN2_bm (1<<2) /* Sample lenght bit 2 mask. */ -#define ADC_SAMPLEN2_bp 2 /* Sample lenght bit 2 position. */ -#define ADC_SAMPLEN3_bm (1<<3) /* Sample lenght bit 3 mask. */ -#define ADC_SAMPLEN3_bp 3 /* Sample lenght bit 3 position. */ -#define ADC_SAMPLEN4_bm (1<<4) /* Sample lenght bit 4 mask. */ -#define ADC_SAMPLEN4_bp 4 /* Sample lenght bit 4 position. */ - -/* ADC.MUXPOS bit masks and bit positions */ -#define ADC_MUXPOS_gm 0x1F /* Analog Channel Selection Bits group mask. */ -#define ADC_MUXPOS_gp 0 /* Analog Channel Selection Bits group position. */ -#define ADC_MUXPOS0_bm (1<<0) /* Analog Channel Selection Bits bit 0 mask. */ -#define ADC_MUXPOS0_bp 0 /* Analog Channel Selection Bits bit 0 position. */ -#define ADC_MUXPOS1_bm (1<<1) /* Analog Channel Selection Bits bit 1 mask. */ -#define ADC_MUXPOS1_bp 1 /* Analog Channel Selection Bits bit 1 position. */ -#define ADC_MUXPOS2_bm (1<<2) /* Analog Channel Selection Bits bit 2 mask. */ -#define ADC_MUXPOS2_bp 2 /* Analog Channel Selection Bits bit 2 position. */ -#define ADC_MUXPOS3_bm (1<<3) /* Analog Channel Selection Bits bit 3 mask. */ -#define ADC_MUXPOS3_bp 3 /* Analog Channel Selection Bits bit 3 position. */ -#define ADC_MUXPOS4_bm (1<<4) /* Analog Channel Selection Bits bit 4 mask. */ -#define ADC_MUXPOS4_bp 4 /* Analog Channel Selection Bits bit 4 position. */ - -/* ADC.COMMAND bit masks and bit positions */ -#define ADC_STCONV_bm 0x01 /* Start Conversion Operation bit mask. */ -#define ADC_STCONV_bp 0 /* Start Conversion Operation bit position. */ - -/* ADC.EVCTRL bit masks and bit positions */ -#define ADC_STARTEI_bm 0x01 /* Start Event Input Enable bit mask. */ -#define ADC_STARTEI_bp 0 /* Start Event Input Enable bit position. */ - -/* ADC.INTCTRL bit masks and bit positions */ -#define ADC_RESRDY_bm 0x01 /* Result Ready Interrupt Enable bit mask. */ -#define ADC_RESRDY_bp 0 /* Result Ready Interrupt Enable bit position. */ -#define ADC_WCMP_bm 0x02 /* Window Comparator Interrupt Enable bit mask. */ -#define ADC_WCMP_bp 1 /* Window Comparator Interrupt Enable bit position. */ - -/* ADC.INTFLAGS bit masks and bit positions */ -/* ADC_RESRDY is already defined. */ -/* ADC_WCMP is already defined. */ - -/* ADC.DBGCTRL bit masks and bit positions */ -#define ADC_DBGRUN_bm 0x01 /* Debug run bit mask. */ -#define ADC_DBGRUN_bp 0 /* Debug run bit position. */ - -/* ADC.TEMP bit masks and bit positions */ -#define ADC_TEMP_gm 0xFF /* Temporary group mask. */ -#define ADC_TEMP_gp 0 /* Temporary group position. */ -#define ADC_TEMP0_bm (1<<0) /* Temporary bit 0 mask. */ -#define ADC_TEMP0_bp 0 /* Temporary bit 0 position. */ -#define ADC_TEMP1_bm (1<<1) /* Temporary bit 1 mask. */ -#define ADC_TEMP1_bp 1 /* Temporary bit 1 position. */ -#define ADC_TEMP2_bm (1<<2) /* Temporary bit 2 mask. */ -#define ADC_TEMP2_bp 2 /* Temporary bit 2 position. */ -#define ADC_TEMP3_bm (1<<3) /* Temporary bit 3 mask. */ -#define ADC_TEMP3_bp 3 /* Temporary bit 3 position. */ -#define ADC_TEMP4_bm (1<<4) /* Temporary bit 4 mask. */ -#define ADC_TEMP4_bp 4 /* Temporary bit 4 position. */ -#define ADC_TEMP5_bm (1<<5) /* Temporary bit 5 mask. */ -#define ADC_TEMP5_bp 5 /* Temporary bit 5 position. */ -#define ADC_TEMP6_bm (1<<6) /* Temporary bit 6 mask. */ -#define ADC_TEMP6_bp 6 /* Temporary bit 6 position. */ -#define ADC_TEMP7_bm (1<<7) /* Temporary bit 7 mask. */ -#define ADC_TEMP7_bp 7 /* Temporary bit 7 position. */ - - - - -/* ADC.CALIB bit masks and bit positions */ -#define ADC_DUTYCYC_bm 0x01 /* Duty Cycle bit mask. */ -#define ADC_DUTYCYC_bp 0 /* Duty Cycle bit position. */ - -/* BOD - Bod interface */ -/* BOD.CTRLA bit masks and bit positions */ -#define BOD_SLEEP_gm 0x03 /* Operation in sleep mode group mask. */ -#define BOD_SLEEP_gp 0 /* Operation in sleep mode group position. */ -#define BOD_SLEEP0_bm (1<<0) /* Operation in sleep mode bit 0 mask. */ -#define BOD_SLEEP0_bp 0 /* Operation in sleep mode bit 0 position. */ -#define BOD_SLEEP1_bm (1<<1) /* Operation in sleep mode bit 1 mask. */ -#define BOD_SLEEP1_bp 1 /* Operation in sleep mode bit 1 position. */ -#define BOD_ACTIVE_gm 0x0C /* Operation in active mode group mask. */ -#define BOD_ACTIVE_gp 2 /* Operation in active mode group position. */ -#define BOD_ACTIVE0_bm (1<<2) /* Operation in active mode bit 0 mask. */ -#define BOD_ACTIVE0_bp 2 /* Operation in active mode bit 0 position. */ -#define BOD_ACTIVE1_bm (1<<3) /* Operation in active mode bit 1 mask. */ -#define BOD_ACTIVE1_bp 3 /* Operation in active mode bit 1 position. */ -#define BOD_SAMPFREQ_bm 0x10 /* Sample frequency bit mask. */ -#define BOD_SAMPFREQ_bp 4 /* Sample frequency bit position. */ - -/* BOD.CTRLB bit masks and bit positions */ -#define BOD_LVL_gm 0x07 /* Bod level group mask. */ -#define BOD_LVL_gp 0 /* Bod level group position. */ -#define BOD_LVL0_bm (1<<0) /* Bod level bit 0 mask. */ -#define BOD_LVL0_bp 0 /* Bod level bit 0 position. */ -#define BOD_LVL1_bm (1<<1) /* Bod level bit 1 mask. */ -#define BOD_LVL1_bp 1 /* Bod level bit 1 position. */ -#define BOD_LVL2_bm (1<<2) /* Bod level bit 2 mask. */ -#define BOD_LVL2_bp 2 /* Bod level bit 2 position. */ - -/* BOD.VLMCTRLA bit masks and bit positions */ -#define BOD_VLMLVL_gm 0x03 /* voltage level monitor level group mask. */ -#define BOD_VLMLVL_gp 0 /* voltage level monitor level group position. */ -#define BOD_VLMLVL0_bm (1<<0) /* voltage level monitor level bit 0 mask. */ -#define BOD_VLMLVL0_bp 0 /* voltage level monitor level bit 0 position. */ -#define BOD_VLMLVL1_bm (1<<1) /* voltage level monitor level bit 1 mask. */ -#define BOD_VLMLVL1_bp 1 /* voltage level monitor level bit 1 position. */ - -/* BOD.INTCTRL bit masks and bit positions */ -#define BOD_VLMIE_bm 0x01 /* voltage level monitor interrrupt enable bit mask. */ -#define BOD_VLMIE_bp 0 /* voltage level monitor interrrupt enable bit position. */ -#define BOD_VLMCFG_gm 0x06 /* Configuration group mask. */ -#define BOD_VLMCFG_gp 1 /* Configuration group position. */ -#define BOD_VLMCFG0_bm (1<<1) /* Configuration bit 0 mask. */ -#define BOD_VLMCFG0_bp 1 /* Configuration bit 0 position. */ -#define BOD_VLMCFG1_bm (1<<2) /* Configuration bit 1 mask. */ -#define BOD_VLMCFG1_bp 2 /* Configuration bit 1 position. */ - -/* BOD.INTFLAGS bit masks and bit positions */ -#define BOD_VLMIF_bm 0x01 /* Voltage level monitor interrupt flag bit mask. */ -#define BOD_VLMIF_bp 0 /* Voltage level monitor interrupt flag bit position. */ - -/* BOD.STATUS bit masks and bit positions */ -#define BOD_VLMS_bm 0x01 /* Voltage level monitor status bit mask. */ -#define BOD_VLMS_bp 0 /* Voltage level monitor status bit position. */ - -/* CCL - Configurable Custom Logic */ -/* CCL.CTRLA bit masks and bit positions */ -#define CCL_ENABLE_bm 0x01 /* Enable bit mask. */ -#define CCL_ENABLE_bp 0 /* Enable bit position. */ -#define CCL_RUNSTDBY_bm 0x40 /* Run in Standby bit mask. */ -#define CCL_RUNSTDBY_bp 6 /* Run in Standby bit position. */ - -/* CCL.SEQCTRL0 bit masks and bit positions */ -#define CCL_SEQSEL_gm 0x07 /* Sequential Selection group mask. */ -#define CCL_SEQSEL_gp 0 /* Sequential Selection group position. */ -#define CCL_SEQSEL0_bm (1<<0) /* Sequential Selection bit 0 mask. */ -#define CCL_SEQSEL0_bp 0 /* Sequential Selection bit 0 position. */ -#define CCL_SEQSEL1_bm (1<<1) /* Sequential Selection bit 1 mask. */ -#define CCL_SEQSEL1_bp 1 /* Sequential Selection bit 1 position. */ -#define CCL_SEQSEL2_bm (1<<2) /* Sequential Selection bit 2 mask. */ -#define CCL_SEQSEL2_bp 2 /* Sequential Selection bit 2 position. */ - -/* CCL.INTCTRL0 bit masks and bit positions */ -#define CCL_INTMODE0_gm 0x03 /* Interrupt Mode for LUT0 group mask. */ -#define CCL_INTMODE0_gp 0 /* Interrupt Mode for LUT0 group position. */ -#define CCL_INTMODE00_bm (1<<0) /* Interrupt Mode for LUT0 bit 0 mask. */ -#define CCL_INTMODE00_bp 0 /* Interrupt Mode for LUT0 bit 0 position. */ -#define CCL_INTMODE01_bm (1<<1) /* Interrupt Mode for LUT0 bit 1 mask. */ -#define CCL_INTMODE01_bp 1 /* Interrupt Mode for LUT0 bit 1 position. */ -#define CCL_INTMODE1_gm 0x0C /* Interrupt Mode for LUT1 group mask. */ -#define CCL_INTMODE1_gp 2 /* Interrupt Mode for LUT1 group position. */ -#define CCL_INTMODE10_bm (1<<2) /* Interrupt Mode for LUT1 bit 0 mask. */ -#define CCL_INTMODE10_bp 2 /* Interrupt Mode for LUT1 bit 0 position. */ -#define CCL_INTMODE11_bm (1<<3) /* Interrupt Mode for LUT1 bit 1 mask. */ -#define CCL_INTMODE11_bp 3 /* Interrupt Mode for LUT1 bit 1 position. */ -#define CCL_INTMODE2_gm 0x30 /* Interrupt Mode for LUT2 group mask. */ -#define CCL_INTMODE2_gp 4 /* Interrupt Mode for LUT2 group position. */ -#define CCL_INTMODE20_bm (1<<4) /* Interrupt Mode for LUT2 bit 0 mask. */ -#define CCL_INTMODE20_bp 4 /* Interrupt Mode for LUT2 bit 0 position. */ -#define CCL_INTMODE21_bm (1<<5) /* Interrupt Mode for LUT2 bit 1 mask. */ -#define CCL_INTMODE21_bp 5 /* Interrupt Mode for LUT2 bit 1 position. */ -#define CCL_INTMODE3_gm 0xC0 /* Interrupt Mode for LUT3 group mask. */ -#define CCL_INTMODE3_gp 6 /* Interrupt Mode for LUT3 group position. */ -#define CCL_INTMODE30_bm (1<<6) /* Interrupt Mode for LUT3 bit 0 mask. */ -#define CCL_INTMODE30_bp 6 /* Interrupt Mode for LUT3 bit 0 position. */ -#define CCL_INTMODE31_bm (1<<7) /* Interrupt Mode for LUT3 bit 1 mask. */ -#define CCL_INTMODE31_bp 7 /* Interrupt Mode for LUT3 bit 1 position. */ - -/* CCL.INTFLAGS bit masks and bit positions */ -#define CCL_INT_gm 0x0F /* Interrupt Flags group mask. */ -#define CCL_INT_gp 0 /* Interrupt Flags group position. */ -#define CCL_INT0_bm (1<<0) /* Interrupt Flags bit 0 mask. */ -#define CCL_INT0_bp 0 /* Interrupt Flags bit 0 position. */ -#define CCL_INT1_bm (1<<1) /* Interrupt Flags bit 1 mask. */ -#define CCL_INT1_bp 1 /* Interrupt Flags bit 1 position. */ -#define CCL_INT2_bm (1<<2) /* Interrupt Flags bit 2 mask. */ -#define CCL_INT2_bp 2 /* Interrupt Flags bit 2 position. */ -#define CCL_INT3_bm (1<<3) /* Interrupt Flags bit 3 mask. */ -#define CCL_INT3_bp 3 /* Interrupt Flags bit 3 position. */ - -/* CCL.LUT0CTRLA bit masks and bit positions */ -/* CCL_ENABLE is already defined. */ -#define CCL_CLKSRC_gm 0x0E /* Clock Source Selection group mask. */ -#define CCL_CLKSRC_gp 1 /* Clock Source Selection group position. */ -#define CCL_CLKSRC0_bm (1<<1) /* Clock Source Selection bit 0 mask. */ -#define CCL_CLKSRC0_bp 1 /* Clock Source Selection bit 0 position. */ -#define CCL_CLKSRC1_bm (1<<2) /* Clock Source Selection bit 1 mask. */ -#define CCL_CLKSRC1_bp 2 /* Clock Source Selection bit 1 position. */ -#define CCL_CLKSRC2_bm (1<<3) /* Clock Source Selection bit 2 mask. */ -#define CCL_CLKSRC2_bp 3 /* Clock Source Selection bit 2 position. */ -#define CCL_FILTSEL_gm 0x30 /* Filter Selection group mask. */ -#define CCL_FILTSEL_gp 4 /* Filter Selection group position. */ -#define CCL_FILTSEL0_bm (1<<4) /* Filter Selection bit 0 mask. */ -#define CCL_FILTSEL0_bp 4 /* Filter Selection bit 0 position. */ -#define CCL_FILTSEL1_bm (1<<5) /* Filter Selection bit 1 mask. */ -#define CCL_FILTSEL1_bp 5 /* Filter Selection bit 1 position. */ -#define CCL_OUTEN_bm 0x40 /* Output Enable bit mask. */ -#define CCL_OUTEN_bp 6 /* Output Enable bit position. */ -#define CCL_EDGEDET_bm 0x80 /* Edge Detection Enable bit mask. */ -#define CCL_EDGEDET_bp 7 /* Edge Detection Enable bit position. */ - -/* CCL.LUT0CTRLB bit masks and bit positions */ -#define CCL_INSEL0_gm 0x0F /* LUT Input 0 Source Selection group mask. */ -#define CCL_INSEL0_gp 0 /* LUT Input 0 Source Selection group position. */ -#define CCL_INSEL00_bm (1<<0) /* LUT Input 0 Source Selection bit 0 mask. */ -#define CCL_INSEL00_bp 0 /* LUT Input 0 Source Selection bit 0 position. */ -#define CCL_INSEL01_bm (1<<1) /* LUT Input 0 Source Selection bit 1 mask. */ -#define CCL_INSEL01_bp 1 /* LUT Input 0 Source Selection bit 1 position. */ -#define CCL_INSEL02_bm (1<<2) /* LUT Input 0 Source Selection bit 2 mask. */ -#define CCL_INSEL02_bp 2 /* LUT Input 0 Source Selection bit 2 position. */ -#define CCL_INSEL03_bm (1<<3) /* LUT Input 0 Source Selection bit 3 mask. */ -#define CCL_INSEL03_bp 3 /* LUT Input 0 Source Selection bit 3 position. */ -#define CCL_INSEL1_gm 0xF0 /* LUT Input 1 Source Selection group mask. */ -#define CCL_INSEL1_gp 4 /* LUT Input 1 Source Selection group position. */ -#define CCL_INSEL10_bm (1<<4) /* LUT Input 1 Source Selection bit 0 mask. */ -#define CCL_INSEL10_bp 4 /* LUT Input 1 Source Selection bit 0 position. */ -#define CCL_INSEL11_bm (1<<5) /* LUT Input 1 Source Selection bit 1 mask. */ -#define CCL_INSEL11_bp 5 /* LUT Input 1 Source Selection bit 1 position. */ -#define CCL_INSEL12_bm (1<<6) /* LUT Input 1 Source Selection bit 2 mask. */ -#define CCL_INSEL12_bp 6 /* LUT Input 1 Source Selection bit 2 position. */ -#define CCL_INSEL13_bm (1<<7) /* LUT Input 1 Source Selection bit 3 mask. */ -#define CCL_INSEL13_bp 7 /* LUT Input 1 Source Selection bit 3 position. */ - -/* CCL.LUT0CTRLC bit masks and bit positions */ -#define CCL_INSEL2_gm 0x0F /* LUT Input 2 Source Selection group mask. */ -#define CCL_INSEL2_gp 0 /* LUT Input 2 Source Selection group position. */ -#define CCL_INSEL20_bm (1<<0) /* LUT Input 2 Source Selection bit 0 mask. */ -#define CCL_INSEL20_bp 0 /* LUT Input 2 Source Selection bit 0 position. */ -#define CCL_INSEL21_bm (1<<1) /* LUT Input 2 Source Selection bit 1 mask. */ -#define CCL_INSEL21_bp 1 /* LUT Input 2 Source Selection bit 1 position. */ -#define CCL_INSEL22_bm (1<<2) /* LUT Input 2 Source Selection bit 2 mask. */ -#define CCL_INSEL22_bp 2 /* LUT Input 2 Source Selection bit 2 position. */ -#define CCL_INSEL23_bm (1<<3) /* LUT Input 2 Source Selection bit 3 mask. */ -#define CCL_INSEL23_bp 3 /* LUT Input 2 Source Selection bit 3 position. */ - - -/* CCL.LUT1CTRLA bit masks and bit positions */ -/* CCL_ENABLE is already defined. */ -/* CCL_CLKSRC is already defined. */ -/* CCL_FILTSEL is already defined. */ -/* CCL_OUTEN is already defined. */ -/* CCL_EDGEDET is already defined. */ - -/* CCL.LUT1CTRLB bit masks and bit positions */ -/* CCL_INSEL0 is already defined. */ -/* CCL_INSEL1 is already defined. */ - -/* CCL.LUT1CTRLC bit masks and bit positions */ -/* CCL_INSEL2 is already defined. */ - - -/* CCL.LUT2CTRLA bit masks and bit positions */ -/* CCL_ENABLE is already defined. */ -/* CCL_CLKSRC is already defined. */ -/* CCL_FILTSEL is already defined. */ -/* CCL_OUTEN is already defined. */ -/* CCL_EDGEDET is already defined. */ - -/* CCL.LUT2CTRLB bit masks and bit positions */ -/* CCL_INSEL0 is already defined. */ -/* CCL_INSEL1 is already defined. */ - -/* CCL.LUT2CTRLC bit masks and bit positions */ -/* CCL_INSEL2 is already defined. */ - - -/* CCL.LUT3CTRLA bit masks and bit positions */ -/* CCL_ENABLE is already defined. */ -/* CCL_CLKSRC is already defined. */ -/* CCL_FILTSEL is already defined. */ -/* CCL_OUTEN is already defined. */ -/* CCL_EDGEDET is already defined. */ - -/* CCL.LUT3CTRLB bit masks and bit positions */ -/* CCL_INSEL0 is already defined. */ -/* CCL_INSEL1 is already defined. */ - -/* CCL.LUT3CTRLC bit masks and bit positions */ -/* CCL_INSEL2 is already defined. */ - - -/* CLKCTRL - Clock controller */ -/* CLKCTRL.MCLKCTRLA bit masks and bit positions */ -#define CLKCTRL_CLKSEL_gm 0x03 /* clock select group mask. */ -#define CLKCTRL_CLKSEL_gp 0 /* clock select group position. */ -#define CLKCTRL_CLKSEL0_bm (1<<0) /* clock select bit 0 mask. */ -#define CLKCTRL_CLKSEL0_bp 0 /* clock select bit 0 position. */ -#define CLKCTRL_CLKSEL1_bm (1<<1) /* clock select bit 1 mask. */ -#define CLKCTRL_CLKSEL1_bp 1 /* clock select bit 1 position. */ -#define CLKCTRL_CLKOUT_bm 0x80 /* System clock out bit mask. */ -#define CLKCTRL_CLKOUT_bp 7 /* System clock out bit position. */ - -/* CLKCTRL.MCLKCTRLB bit masks and bit positions */ -#define CLKCTRL_PEN_bm 0x01 /* Prescaler enable bit mask. */ -#define CLKCTRL_PEN_bp 0 /* Prescaler enable bit position. */ -#define CLKCTRL_PDIV_gm 0x1E /* Prescaler division group mask. */ -#define CLKCTRL_PDIV_gp 1 /* Prescaler division group position. */ -#define CLKCTRL_PDIV0_bm (1<<1) /* Prescaler division bit 0 mask. */ -#define CLKCTRL_PDIV0_bp 1 /* Prescaler division bit 0 position. */ -#define CLKCTRL_PDIV1_bm (1<<2) /* Prescaler division bit 1 mask. */ -#define CLKCTRL_PDIV1_bp 2 /* Prescaler division bit 1 position. */ -#define CLKCTRL_PDIV2_bm (1<<3) /* Prescaler division bit 2 mask. */ -#define CLKCTRL_PDIV2_bp 3 /* Prescaler division bit 2 position. */ -#define CLKCTRL_PDIV3_bm (1<<4) /* Prescaler division bit 3 mask. */ -#define CLKCTRL_PDIV3_bp 4 /* Prescaler division bit 3 position. */ - -/* CLKCTRL.MCLKLOCK bit masks and bit positions */ -#define CLKCTRL_LOCKEN_bm 0x01 /* lock ebable bit mask. */ -#define CLKCTRL_LOCKEN_bp 0 /* lock ebable bit position. */ - -/* CLKCTRL.MCLKSTATUS bit masks and bit positions */ -#define CLKCTRL_SOSC_bm 0x01 /* System Oscillator changing bit mask. */ -#define CLKCTRL_SOSC_bp 0 /* System Oscillator changing bit position. */ -#define CLKCTRL_OSC20MS_bm 0x10 /* 20MHz oscillator status bit mask. */ -#define CLKCTRL_OSC20MS_bp 4 /* 20MHz oscillator status bit position. */ -#define CLKCTRL_OSC32KS_bm 0x20 /* 32KHz oscillator status bit mask. */ -#define CLKCTRL_OSC32KS_bp 5 /* 32KHz oscillator status bit position. */ -#define CLKCTRL_XOSC32KS_bm 0x40 /* 32.768 kHz Crystal Oscillator status bit mask. */ -#define CLKCTRL_XOSC32KS_bp 6 /* 32.768 kHz Crystal Oscillator status bit position. */ -#define CLKCTRL_EXTS_bm 0x80 /* External Clock status bit mask. */ -#define CLKCTRL_EXTS_bp 7 /* External Clock status bit position. */ - -/* CLKCTRL.OSC20MCTRLA bit masks and bit positions */ -#define CLKCTRL_RUNSTDBY_bm 0x02 /* Run standby bit mask. */ -#define CLKCTRL_RUNSTDBY_bp 1 /* Run standby bit position. */ - -/* CLKCTRL.OSC20MCALIBA bit masks and bit positions */ -#define CLKCTRL_CAL20M_gm 0x7F /* Calibration group mask. */ -#define CLKCTRL_CAL20M_gp 0 /* Calibration group position. */ -#define CLKCTRL_CAL20M0_bm (1<<0) /* Calibration bit 0 mask. */ -#define CLKCTRL_CAL20M0_bp 0 /* Calibration bit 0 position. */ -#define CLKCTRL_CAL20M1_bm (1<<1) /* Calibration bit 1 mask. */ -#define CLKCTRL_CAL20M1_bp 1 /* Calibration bit 1 position. */ -#define CLKCTRL_CAL20M2_bm (1<<2) /* Calibration bit 2 mask. */ -#define CLKCTRL_CAL20M2_bp 2 /* Calibration bit 2 position. */ -#define CLKCTRL_CAL20M3_bm (1<<3) /* Calibration bit 3 mask. */ -#define CLKCTRL_CAL20M3_bp 3 /* Calibration bit 3 position. */ -#define CLKCTRL_CAL20M4_bm (1<<4) /* Calibration bit 4 mask. */ -#define CLKCTRL_CAL20M4_bp 4 /* Calibration bit 4 position. */ -#define CLKCTRL_CAL20M5_bm (1<<5) /* Calibration bit 5 mask. */ -#define CLKCTRL_CAL20M5_bp 5 /* Calibration bit 5 position. */ -#define CLKCTRL_CAL20M6_bm (1<<6) /* Calibration bit 6 mask. */ -#define CLKCTRL_CAL20M6_bp 6 /* Calibration bit 6 position. */ -#define CLKCTRL_CALSEL20M_bm 0x80 /* Calibration freq select bit mask. */ -#define CLKCTRL_CALSEL20M_bp 7 /* Calibration freq select bit position. */ - -/* CLKCTRL.OSC20MCALIBB bit masks and bit positions */ -#define CLKCTRL_TEMPCAL20M_gm 0x0F /* Oscillator temperature coefficient group mask. */ -#define CLKCTRL_TEMPCAL20M_gp 0 /* Oscillator temperature coefficient group position. */ -#define CLKCTRL_TEMPCAL20M0_bm (1<<0) /* Oscillator temperature coefficient bit 0 mask. */ -#define CLKCTRL_TEMPCAL20M0_bp 0 /* Oscillator temperature coefficient bit 0 position. */ -#define CLKCTRL_TEMPCAL20M1_bm (1<<1) /* Oscillator temperature coefficient bit 1 mask. */ -#define CLKCTRL_TEMPCAL20M1_bp 1 /* Oscillator temperature coefficient bit 1 position. */ -#define CLKCTRL_TEMPCAL20M2_bm (1<<2) /* Oscillator temperature coefficient bit 2 mask. */ -#define CLKCTRL_TEMPCAL20M2_bp 2 /* Oscillator temperature coefficient bit 2 position. */ -#define CLKCTRL_TEMPCAL20M3_bm (1<<3) /* Oscillator temperature coefficient bit 3 mask. */ -#define CLKCTRL_TEMPCAL20M3_bp 3 /* Oscillator temperature coefficient bit 3 position. */ -#define CLKCTRL_LOCK_bm 0x80 /* Lock bit mask. */ -#define CLKCTRL_LOCK_bp 7 /* Lock bit position. */ - -/* CLKCTRL.OSC32KCTRLA bit masks and bit positions */ -/* CLKCTRL_RUNSTDBY is already defined. */ - -/* CLKCTRL.OSC32KCALIB bit masks and bit positions */ -#define CLKCTRL_CAL32K_gm 0x3F /* Calibration group mask. */ -#define CLKCTRL_CAL32K_gp 0 /* Calibration group position. */ -#define CLKCTRL_CAL32K0_bm (1<<0) /* Calibration bit 0 mask. */ -#define CLKCTRL_CAL32K0_bp 0 /* Calibration bit 0 position. */ -#define CLKCTRL_CAL32K1_bm (1<<1) /* Calibration bit 1 mask. */ -#define CLKCTRL_CAL32K1_bp 1 /* Calibration bit 1 position. */ -#define CLKCTRL_CAL32K2_bm (1<<2) /* Calibration bit 2 mask. */ -#define CLKCTRL_CAL32K2_bp 2 /* Calibration bit 2 position. */ -#define CLKCTRL_CAL32K3_bm (1<<3) /* Calibration bit 3 mask. */ -#define CLKCTRL_CAL32K3_bp 3 /* Calibration bit 3 position. */ -#define CLKCTRL_CAL32K4_bm (1<<4) /* Calibration bit 4 mask. */ -#define CLKCTRL_CAL32K4_bp 4 /* Calibration bit 4 position. */ -#define CLKCTRL_CAL32K5_bm (1<<5) /* Calibration bit 5 mask. */ -#define CLKCTRL_CAL32K5_bp 5 /* Calibration bit 5 position. */ - -/* CLKCTRL.XOSC32KCTRLA bit masks and bit positions */ -#define CLKCTRL_ENABLE_bm 0x01 /* Enable bit mask. */ -#define CLKCTRL_ENABLE_bp 0 /* Enable bit position. */ -/* CLKCTRL_RUNSTDBY is already defined. */ -#define CLKCTRL_SEL_bm 0x04 /* Select bit mask. */ -#define CLKCTRL_SEL_bp 2 /* Select bit position. */ -#define CLKCTRL_CSUT_gm 0x30 /* Crystal startup time group mask. */ -#define CLKCTRL_CSUT_gp 4 /* Crystal startup time group position. */ -#define CLKCTRL_CSUT0_bm (1<<4) /* Crystal startup time bit 0 mask. */ -#define CLKCTRL_CSUT0_bp 4 /* Crystal startup time bit 0 position. */ -#define CLKCTRL_CSUT1_bm (1<<5) /* Crystal startup time bit 1 mask. */ -#define CLKCTRL_CSUT1_bp 5 /* Crystal startup time bit 1 position. */ - -/* CPU - CPU */ -/* CPU.CCP bit masks and bit positions */ -#define CPU_CCP_gm 0xFF /* CCP signature group mask. */ -#define CPU_CCP_gp 0 /* CCP signature group position. */ -#define CPU_CCP0_bm (1<<0) /* CCP signature bit 0 mask. */ -#define CPU_CCP0_bp 0 /* CCP signature bit 0 position. */ -#define CPU_CCP1_bm (1<<1) /* CCP signature bit 1 mask. */ -#define CPU_CCP1_bp 1 /* CCP signature bit 1 position. */ -#define CPU_CCP2_bm (1<<2) /* CCP signature bit 2 mask. */ -#define CPU_CCP2_bp 2 /* CCP signature bit 2 position. */ -#define CPU_CCP3_bm (1<<3) /* CCP signature bit 3 mask. */ -#define CPU_CCP3_bp 3 /* CCP signature bit 3 position. */ -#define CPU_CCP4_bm (1<<4) /* CCP signature bit 4 mask. */ -#define CPU_CCP4_bp 4 /* CCP signature bit 4 position. */ -#define CPU_CCP5_bm (1<<5) /* CCP signature bit 5 mask. */ -#define CPU_CCP5_bp 5 /* CCP signature bit 5 position. */ -#define CPU_CCP6_bm (1<<6) /* CCP signature bit 6 mask. */ -#define CPU_CCP6_bp 6 /* CCP signature bit 6 position. */ -#define CPU_CCP7_bm (1<<7) /* CCP signature bit 7 mask. */ -#define CPU_CCP7_bp 7 /* CCP signature bit 7 position. */ - - - - -/* CPU.SREG bit masks and bit positions */ -#define CPU_C_bm 0x01 /* Carry Flag bit mask. */ -#define CPU_C_bp 0 /* Carry Flag bit position. */ -#define CPU_Z_bm 0x02 /* Zero Flag bit mask. */ -#define CPU_Z_bp 1 /* Zero Flag bit position. */ -#define CPU_N_bm 0x04 /* Negative Flag bit mask. */ -#define CPU_N_bp 2 /* Negative Flag bit position. */ -#define CPU_V_bm 0x08 /* Two's Complement Overflow Flag bit mask. */ -#define CPU_V_bp 3 /* Two's Complement Overflow Flag bit position. */ -#define CPU_S_bm 0x10 /* N Exclusive Or V Flag bit mask. */ -#define CPU_S_bp 4 /* N Exclusive Or V Flag bit position. */ -#define CPU_H_bm 0x20 /* Half Carry Flag bit mask. */ -#define CPU_H_bp 5 /* Half Carry Flag bit position. */ -#define CPU_T_bm 0x40 /* Transfer Bit bit mask. */ -#define CPU_T_bp 6 /* Transfer Bit bit position. */ -#define CPU_I_bm 0x80 /* Global Interrupt Enable Flag bit mask. */ -#define CPU_I_bp 7 /* Global Interrupt Enable Flag bit position. */ - -/* CPUINT - Interrupt Controller */ -/* CPUINT.CTRLA bit masks and bit positions */ -#define CPUINT_LVL0RR_bm 0x01 /* Round-robin Scheduling Enable bit mask. */ -#define CPUINT_LVL0RR_bp 0 /* Round-robin Scheduling Enable bit position. */ -#define CPUINT_CVT_bm 0x20 /* Compact Vector Table bit mask. */ -#define CPUINT_CVT_bp 5 /* Compact Vector Table bit position. */ -#define CPUINT_IVSEL_bm 0x40 /* Interrupt Vector Select bit mask. */ -#define CPUINT_IVSEL_bp 6 /* Interrupt Vector Select bit position. */ - -/* CPUINT.STATUS bit masks and bit positions */ -#define CPUINT_LVL0EX_bm 0x01 /* Level 0 Interrupt Executing bit mask. */ -#define CPUINT_LVL0EX_bp 0 /* Level 0 Interrupt Executing bit position. */ -#define CPUINT_LVL1EX_bm 0x02 /* Level 1 Interrupt Executing bit mask. */ -#define CPUINT_LVL1EX_bp 1 /* Level 1 Interrupt Executing bit position. */ -#define CPUINT_NMIEX_bm 0x80 /* Non-maskable Interrupt Executing bit mask. */ -#define CPUINT_NMIEX_bp 7 /* Non-maskable Interrupt Executing bit position. */ - -/* CPUINT.LVL0PRI bit masks and bit positions */ -#define CPUINT_LVL0PRI_gm 0xFF /* Interrupt Level Priority group mask. */ -#define CPUINT_LVL0PRI_gp 0 /* Interrupt Level Priority group position. */ -#define CPUINT_LVL0PRI0_bm (1<<0) /* Interrupt Level Priority bit 0 mask. */ -#define CPUINT_LVL0PRI0_bp 0 /* Interrupt Level Priority bit 0 position. */ -#define CPUINT_LVL0PRI1_bm (1<<1) /* Interrupt Level Priority bit 1 mask. */ -#define CPUINT_LVL0PRI1_bp 1 /* Interrupt Level Priority bit 1 position. */ -#define CPUINT_LVL0PRI2_bm (1<<2) /* Interrupt Level Priority bit 2 mask. */ -#define CPUINT_LVL0PRI2_bp 2 /* Interrupt Level Priority bit 2 position. */ -#define CPUINT_LVL0PRI3_bm (1<<3) /* Interrupt Level Priority bit 3 mask. */ -#define CPUINT_LVL0PRI3_bp 3 /* Interrupt Level Priority bit 3 position. */ -#define CPUINT_LVL0PRI4_bm (1<<4) /* Interrupt Level Priority bit 4 mask. */ -#define CPUINT_LVL0PRI4_bp 4 /* Interrupt Level Priority bit 4 position. */ -#define CPUINT_LVL0PRI5_bm (1<<5) /* Interrupt Level Priority bit 5 mask. */ -#define CPUINT_LVL0PRI5_bp 5 /* Interrupt Level Priority bit 5 position. */ -#define CPUINT_LVL0PRI6_bm (1<<6) /* Interrupt Level Priority bit 6 mask. */ -#define CPUINT_LVL0PRI6_bp 6 /* Interrupt Level Priority bit 6 position. */ -#define CPUINT_LVL0PRI7_bm (1<<7) /* Interrupt Level Priority bit 7 mask. */ -#define CPUINT_LVL0PRI7_bp 7 /* Interrupt Level Priority bit 7 position. */ - -/* CPUINT.LVL1VEC bit masks and bit positions */ -#define CPUINT_LVL1VEC_gm 0xFF /* Interrupt Vector with High Priority group mask. */ -#define CPUINT_LVL1VEC_gp 0 /* Interrupt Vector with High Priority group position. */ -#define CPUINT_LVL1VEC0_bm (1<<0) /* Interrupt Vector with High Priority bit 0 mask. */ -#define CPUINT_LVL1VEC0_bp 0 /* Interrupt Vector with High Priority bit 0 position. */ -#define CPUINT_LVL1VEC1_bm (1<<1) /* Interrupt Vector with High Priority bit 1 mask. */ -#define CPUINT_LVL1VEC1_bp 1 /* Interrupt Vector with High Priority bit 1 position. */ -#define CPUINT_LVL1VEC2_bm (1<<2) /* Interrupt Vector with High Priority bit 2 mask. */ -#define CPUINT_LVL1VEC2_bp 2 /* Interrupt Vector with High Priority bit 2 position. */ -#define CPUINT_LVL1VEC3_bm (1<<3) /* Interrupt Vector with High Priority bit 3 mask. */ -#define CPUINT_LVL1VEC3_bp 3 /* Interrupt Vector with High Priority bit 3 position. */ -#define CPUINT_LVL1VEC4_bm (1<<4) /* Interrupt Vector with High Priority bit 4 mask. */ -#define CPUINT_LVL1VEC4_bp 4 /* Interrupt Vector with High Priority bit 4 position. */ -#define CPUINT_LVL1VEC5_bm (1<<5) /* Interrupt Vector with High Priority bit 5 mask. */ -#define CPUINT_LVL1VEC5_bp 5 /* Interrupt Vector with High Priority bit 5 position. */ -#define CPUINT_LVL1VEC6_bm (1<<6) /* Interrupt Vector with High Priority bit 6 mask. */ -#define CPUINT_LVL1VEC6_bp 6 /* Interrupt Vector with High Priority bit 6 position. */ -#define CPUINT_LVL1VEC7_bm (1<<7) /* Interrupt Vector with High Priority bit 7 mask. */ -#define CPUINT_LVL1VEC7_bp 7 /* Interrupt Vector with High Priority bit 7 position. */ - -/* CRCSCAN - CRCSCAN */ -/* CRCSCAN.CTRLA bit masks and bit positions */ -#define CRCSCAN_ENABLE_bm 0x01 /* Enable CRC scan bit mask. */ -#define CRCSCAN_ENABLE_bp 0 /* Enable CRC scan bit position. */ -#define CRCSCAN_NMIEN_bm 0x02 /* Enable NMI Trigger bit mask. */ -#define CRCSCAN_NMIEN_bp 1 /* Enable NMI Trigger bit position. */ -#define CRCSCAN_RESET_bm 0x80 /* Reset CRC scan bit mask. */ -#define CRCSCAN_RESET_bp 7 /* Reset CRC scan bit position. */ - -/* CRCSCAN.CTRLB bit masks and bit positions */ -#define CRCSCAN_SRC_gm 0x03 /* CRC Source group mask. */ -#define CRCSCAN_SRC_gp 0 /* CRC Source group position. */ -#define CRCSCAN_SRC0_bm (1<<0) /* CRC Source bit 0 mask. */ -#define CRCSCAN_SRC0_bp 0 /* CRC Source bit 0 position. */ -#define CRCSCAN_SRC1_bm (1<<1) /* CRC Source bit 1 mask. */ -#define CRCSCAN_SRC1_bp 1 /* CRC Source bit 1 position. */ -#define CRCSCAN_MODE_gm 0x30 /* CRC Flash Access Mode group mask. */ -#define CRCSCAN_MODE_gp 4 /* CRC Flash Access Mode group position. */ -#define CRCSCAN_MODE0_bm (1<<4) /* CRC Flash Access Mode bit 0 mask. */ -#define CRCSCAN_MODE0_bp 4 /* CRC Flash Access Mode bit 0 position. */ -#define CRCSCAN_MODE1_bm (1<<5) /* CRC Flash Access Mode bit 1 mask. */ -#define CRCSCAN_MODE1_bp 5 /* CRC Flash Access Mode bit 1 position. */ - -/* CRCSCAN.STATUS bit masks and bit positions */ -#define CRCSCAN_BUSY_bm 0x01 /* CRC Busy bit mask. */ -#define CRCSCAN_BUSY_bp 0 /* CRC Busy bit position. */ -#define CRCSCAN_OK_bm 0x02 /* CRC Ok bit mask. */ -#define CRCSCAN_OK_bp 1 /* CRC Ok bit position. */ - -/* EVSYS - Event System */ -/* EVSYS.STROBE bit masks and bit positions */ -#define EVSYS_STROBE0_gm 0xFF /* Software event on channels group mask. */ -#define EVSYS_STROBE0_gp 0 /* Software event on channels group position. */ -#define EVSYS_STROBE00_bm (1<<0) /* Software event on channels bit 0 mask. */ -#define EVSYS_STROBE00_bp 0 /* Software event on channels bit 0 position. */ -#define EVSYS_STROBE01_bm (1<<1) /* Software event on channels bit 1 mask. */ -#define EVSYS_STROBE01_bp 1 /* Software event on channels bit 1 position. */ -#define EVSYS_STROBE02_bm (1<<2) /* Software event on channels bit 2 mask. */ -#define EVSYS_STROBE02_bp 2 /* Software event on channels bit 2 position. */ -#define EVSYS_STROBE03_bm (1<<3) /* Software event on channels bit 3 mask. */ -#define EVSYS_STROBE03_bp 3 /* Software event on channels bit 3 position. */ -#define EVSYS_STROBE04_bm (1<<4) /* Software event on channels bit 4 mask. */ -#define EVSYS_STROBE04_bp 4 /* Software event on channels bit 4 position. */ -#define EVSYS_STROBE05_bm (1<<5) /* Software event on channels bit 5 mask. */ -#define EVSYS_STROBE05_bp 5 /* Software event on channels bit 5 position. */ -#define EVSYS_STROBE06_bm (1<<6) /* Software event on channels bit 6 mask. */ -#define EVSYS_STROBE06_bp 6 /* Software event on channels bit 6 position. */ -#define EVSYS_STROBE07_bm (1<<7) /* Software event on channels bit 7 mask. */ -#define EVSYS_STROBE07_bp 7 /* Software event on channels bit 7 position. */ - -/* EVSYS.CHANNEL0 bit masks and bit positions */ -#define EVSYS_GENERATOR_gm 0xFF /* Generator selector group mask. */ -#define EVSYS_GENERATOR_gp 0 /* Generator selector group position. */ -#define EVSYS_GENERATOR0_bm (1<<0) /* Generator selector bit 0 mask. */ -#define EVSYS_GENERATOR0_bp 0 /* Generator selector bit 0 position. */ -#define EVSYS_GENERATOR1_bm (1<<1) /* Generator selector bit 1 mask. */ -#define EVSYS_GENERATOR1_bp 1 /* Generator selector bit 1 position. */ -#define EVSYS_GENERATOR2_bm (1<<2) /* Generator selector bit 2 mask. */ -#define EVSYS_GENERATOR2_bp 2 /* Generator selector bit 2 position. */ -#define EVSYS_GENERATOR3_bm (1<<3) /* Generator selector bit 3 mask. */ -#define EVSYS_GENERATOR3_bp 3 /* Generator selector bit 3 position. */ -#define EVSYS_GENERATOR4_bm (1<<4) /* Generator selector bit 4 mask. */ -#define EVSYS_GENERATOR4_bp 4 /* Generator selector bit 4 position. */ -#define EVSYS_GENERATOR5_bm (1<<5) /* Generator selector bit 5 mask. */ -#define EVSYS_GENERATOR5_bp 5 /* Generator selector bit 5 position. */ -#define EVSYS_GENERATOR6_bm (1<<6) /* Generator selector bit 6 mask. */ -#define EVSYS_GENERATOR6_bp 6 /* Generator selector bit 6 position. */ -#define EVSYS_GENERATOR7_bm (1<<7) /* Generator selector bit 7 mask. */ -#define EVSYS_GENERATOR7_bp 7 /* Generator selector bit 7 position. */ - -/* EVSYS.CHANNEL1 bit masks and bit positions */ -/* EVSYS_GENERATOR is already defined. */ - -/* EVSYS.CHANNEL2 bit masks and bit positions */ -/* EVSYS_GENERATOR is already defined. */ - -/* EVSYS.CHANNEL3 bit masks and bit positions */ -/* EVSYS_GENERATOR is already defined. */ - -/* EVSYS.CHANNEL4 bit masks and bit positions */ -/* EVSYS_GENERATOR is already defined. */ - -/* EVSYS.CHANNEL5 bit masks and bit positions */ -/* EVSYS_GENERATOR is already defined. */ - -/* EVSYS.USERCCLLUT0A bit masks and bit positions */ -#define EVSYS_CHANNEL_gm 0xFF /* Channel selector group mask. */ -#define EVSYS_CHANNEL_gp 0 /* Channel selector group position. */ -#define EVSYS_CHANNEL0_bm (1<<0) /* Channel selector bit 0 mask. */ -#define EVSYS_CHANNEL0_bp 0 /* Channel selector bit 0 position. */ -#define EVSYS_CHANNEL1_bm (1<<1) /* Channel selector bit 1 mask. */ -#define EVSYS_CHANNEL1_bp 1 /* Channel selector bit 1 position. */ -#define EVSYS_CHANNEL2_bm (1<<2) /* Channel selector bit 2 mask. */ -#define EVSYS_CHANNEL2_bp 2 /* Channel selector bit 2 position. */ -#define EVSYS_CHANNEL3_bm (1<<3) /* Channel selector bit 3 mask. */ -#define EVSYS_CHANNEL3_bp 3 /* Channel selector bit 3 position. */ -#define EVSYS_CHANNEL4_bm (1<<4) /* Channel selector bit 4 mask. */ -#define EVSYS_CHANNEL4_bp 4 /* Channel selector bit 4 position. */ -#define EVSYS_CHANNEL5_bm (1<<5) /* Channel selector bit 5 mask. */ -#define EVSYS_CHANNEL5_bp 5 /* Channel selector bit 5 position. */ -#define EVSYS_CHANNEL6_bm (1<<6) /* Channel selector bit 6 mask. */ -#define EVSYS_CHANNEL6_bp 6 /* Channel selector bit 6 position. */ -#define EVSYS_CHANNEL7_bm (1<<7) /* Channel selector bit 7 mask. */ -#define EVSYS_CHANNEL7_bp 7 /* Channel selector bit 7 position. */ - -/* EVSYS.USERCCLLUT0B bit masks and bit positions */ -/* EVSYS_CHANNEL is already defined. */ - -/* EVSYS.USERCCLLUT1A bit masks and bit positions */ -/* EVSYS_CHANNEL is already defined. */ - -/* EVSYS.USERCCLLUT1B bit masks and bit positions */ -/* EVSYS_CHANNEL is already defined. */ - -/* EVSYS.USERCCLLUT2A bit masks and bit positions */ -/* EVSYS_CHANNEL is already defined. */ - -/* EVSYS.USERCCLLUT2B bit masks and bit positions */ -/* EVSYS_CHANNEL is already defined. */ - -/* EVSYS.USERCCLLUT3A bit masks and bit positions */ -/* EVSYS_CHANNEL is already defined. */ - -/* EVSYS.USERCCLLUT3B bit masks and bit positions */ -/* EVSYS_CHANNEL is already defined. */ - -/* EVSYS.USERADC0 bit masks and bit positions */ -/* EVSYS_CHANNEL is already defined. */ - -/* EVSYS.USEREVOUTA bit masks and bit positions */ -/* EVSYS_CHANNEL is already defined. */ - -/* EVSYS.USEREVOUTB bit masks and bit positions */ -/* EVSYS_CHANNEL is already defined. */ - -/* EVSYS.USEREVOUTC bit masks and bit positions */ -/* EVSYS_CHANNEL is already defined. */ - -/* EVSYS.USEREVOUTD bit masks and bit positions */ -/* EVSYS_CHANNEL is already defined. */ - -/* EVSYS.USEREVOUTE bit masks and bit positions */ -/* EVSYS_CHANNEL is already defined. */ - -/* EVSYS.USEREVOUTF bit masks and bit positions */ -/* EVSYS_CHANNEL is already defined. */ - -/* EVSYS.USERUSART0 bit masks and bit positions */ -/* EVSYS_CHANNEL is already defined. */ - -/* EVSYS.USERUSART1 bit masks and bit positions */ -/* EVSYS_CHANNEL is already defined. */ - -/* EVSYS.USERUSART2 bit masks and bit positions */ -/* EVSYS_CHANNEL is already defined. */ - -/* EVSYS.USERUSART3 bit masks and bit positions */ -/* EVSYS_CHANNEL is already defined. */ - -/* EVSYS.USERTCA0 bit masks and bit positions */ -/* EVSYS_CHANNEL is already defined. */ - -/* EVSYS.USERTCB0 bit masks and bit positions */ -/* EVSYS_CHANNEL is already defined. */ - -/* EVSYS.USERTCB1 bit masks and bit positions */ -/* EVSYS_CHANNEL is already defined. */ - -/* EVSYS.USERTCB2 bit masks and bit positions */ -/* EVSYS_CHANNEL is already defined. */ - -/* EVSYS.USERTCB3 bit masks and bit positions */ -/* EVSYS_CHANNEL is already defined. */ - -/* FUSE - Fuses */ -/* FUSE.WDTCFG bit masks and bit positions */ -#define FUSE_PERIOD_gm 0x0F /* Watchdog Timeout Period group mask. */ -#define FUSE_PERIOD_gp 0 /* Watchdog Timeout Period group position. */ -#define FUSE_PERIOD0_bm (1<<0) /* Watchdog Timeout Period bit 0 mask. */ -#define FUSE_PERIOD0_bp 0 /* Watchdog Timeout Period bit 0 position. */ -#define FUSE_PERIOD1_bm (1<<1) /* Watchdog Timeout Period bit 1 mask. */ -#define FUSE_PERIOD1_bp 1 /* Watchdog Timeout Period bit 1 position. */ -#define FUSE_PERIOD2_bm (1<<2) /* Watchdog Timeout Period bit 2 mask. */ -#define FUSE_PERIOD2_bp 2 /* Watchdog Timeout Period bit 2 position. */ -#define FUSE_PERIOD3_bm (1<<3) /* Watchdog Timeout Period bit 3 mask. */ -#define FUSE_PERIOD3_bp 3 /* Watchdog Timeout Period bit 3 position. */ -#define FUSE_WINDOW_gm 0xF0 /* Watchdog Window Timeout Period group mask. */ -#define FUSE_WINDOW_gp 4 /* Watchdog Window Timeout Period group position. */ -#define FUSE_WINDOW0_bm (1<<4) /* Watchdog Window Timeout Period bit 0 mask. */ -#define FUSE_WINDOW0_bp 4 /* Watchdog Window Timeout Period bit 0 position. */ -#define FUSE_WINDOW1_bm (1<<5) /* Watchdog Window Timeout Period bit 1 mask. */ -#define FUSE_WINDOW1_bp 5 /* Watchdog Window Timeout Period bit 1 position. */ -#define FUSE_WINDOW2_bm (1<<6) /* Watchdog Window Timeout Period bit 2 mask. */ -#define FUSE_WINDOW2_bp 6 /* Watchdog Window Timeout Period bit 2 position. */ -#define FUSE_WINDOW3_bm (1<<7) /* Watchdog Window Timeout Period bit 3 mask. */ -#define FUSE_WINDOW3_bp 7 /* Watchdog Window Timeout Period bit 3 position. */ - -/* FUSE.BODCFG bit masks and bit positions */ -#define FUSE_SLEEP_gm 0x03 /* BOD Operation in Sleep Mode group mask. */ -#define FUSE_SLEEP_gp 0 /* BOD Operation in Sleep Mode group position. */ -#define FUSE_SLEEP0_bm (1<<0) /* BOD Operation in Sleep Mode bit 0 mask. */ -#define FUSE_SLEEP0_bp 0 /* BOD Operation in Sleep Mode bit 0 position. */ -#define FUSE_SLEEP1_bm (1<<1) /* BOD Operation in Sleep Mode bit 1 mask. */ -#define FUSE_SLEEP1_bp 1 /* BOD Operation in Sleep Mode bit 1 position. */ -#define FUSE_ACTIVE_gm 0x0C /* BOD Operation in Active Mode group mask. */ -#define FUSE_ACTIVE_gp 2 /* BOD Operation in Active Mode group position. */ -#define FUSE_ACTIVE0_bm (1<<2) /* BOD Operation in Active Mode bit 0 mask. */ -#define FUSE_ACTIVE0_bp 2 /* BOD Operation in Active Mode bit 0 position. */ -#define FUSE_ACTIVE1_bm (1<<3) /* BOD Operation in Active Mode bit 1 mask. */ -#define FUSE_ACTIVE1_bp 3 /* BOD Operation in Active Mode bit 1 position. */ -#define FUSE_SAMPFREQ_bm 0x10 /* BOD Sample Frequency bit mask. */ -#define FUSE_SAMPFREQ_bp 4 /* BOD Sample Frequency bit position. */ -#define FUSE_LVL_gm 0xE0 /* BOD Level group mask. */ -#define FUSE_LVL_gp 5 /* BOD Level group position. */ -#define FUSE_LVL0_bm (1<<5) /* BOD Level bit 0 mask. */ -#define FUSE_LVL0_bp 5 /* BOD Level bit 0 position. */ -#define FUSE_LVL1_bm (1<<6) /* BOD Level bit 1 mask. */ -#define FUSE_LVL1_bp 6 /* BOD Level bit 1 position. */ -#define FUSE_LVL2_bm (1<<7) /* BOD Level bit 2 mask. */ -#define FUSE_LVL2_bp 7 /* BOD Level bit 2 position. */ - -/* FUSE.OSCCFG bit masks and bit positions */ -#define FUSE_FREQSEL_gm 0x03 /* Frequency Select group mask. */ -#define FUSE_FREQSEL_gp 0 /* Frequency Select group position. */ -#define FUSE_FREQSEL0_bm (1<<0) /* Frequency Select bit 0 mask. */ -#define FUSE_FREQSEL0_bp 0 /* Frequency Select bit 0 position. */ -#define FUSE_FREQSEL1_bm (1<<1) /* Frequency Select bit 1 mask. */ -#define FUSE_FREQSEL1_bp 1 /* Frequency Select bit 1 position. */ -#define FUSE_OSCLOCK_bm 0x80 /* Oscillator Lock bit mask. */ -#define FUSE_OSCLOCK_bp 7 /* Oscillator Lock bit position. */ - -/* FUSE.TCD0CFG bit masks and bit positions */ -#define FUSE_CMPA_bm 0x01 /* Compare A Default Output Value bit mask. */ -#define FUSE_CMPA_bp 0 /* Compare A Default Output Value bit position. */ -#define FUSE_CMPB_bm 0x02 /* Compare B Default Output Value bit mask. */ -#define FUSE_CMPB_bp 1 /* Compare B Default Output Value bit position. */ -#define FUSE_CMPC_bm 0x04 /* Compare C Default Output Value bit mask. */ -#define FUSE_CMPC_bp 2 /* Compare C Default Output Value bit position. */ -#define FUSE_CMPD_bm 0x08 /* Compare D Default Output Value bit mask. */ -#define FUSE_CMPD_bp 3 /* Compare D Default Output Value bit position. */ -#define FUSE_CMPAEN_bm 0x10 /* Compare A Output Enable bit mask. */ -#define FUSE_CMPAEN_bp 4 /* Compare A Output Enable bit position. */ -#define FUSE_CMPBEN_bm 0x20 /* Compare B Output Enable bit mask. */ -#define FUSE_CMPBEN_bp 5 /* Compare B Output Enable bit position. */ -#define FUSE_CMPCEN_bm 0x40 /* Compare C Output Enable bit mask. */ -#define FUSE_CMPCEN_bp 6 /* Compare C Output Enable bit position. */ -#define FUSE_CMPDEN_bm 0x80 /* Compare D Output Enable bit mask. */ -#define FUSE_CMPDEN_bp 7 /* Compare D Output Enable bit position. */ - -/* FUSE.SYSCFG0 bit masks and bit positions */ -#define FUSE_EESAVE_bm 0x01 /* EEPROM Save bit mask. */ -#define FUSE_EESAVE_bp 0 /* EEPROM Save bit position. */ -#define FUSE_RSTPINCFG_gm 0x0C /* Reset Pin Configuration group mask. */ -#define FUSE_RSTPINCFG_gp 2 /* Reset Pin Configuration group position. */ -#define FUSE_RSTPINCFG0_bm (1<<2) /* Reset Pin Configuration bit 0 mask. */ -#define FUSE_RSTPINCFG0_bp 2 /* Reset Pin Configuration bit 0 position. */ -#define FUSE_RSTPINCFG1_bm (1<<3) /* Reset Pin Configuration bit 1 mask. */ -#define FUSE_RSTPINCFG1_bp 3 /* Reset Pin Configuration bit 1 position. */ -#define FUSE_CRCSRC_gm 0xC0 /* CRC Source group mask. */ -#define FUSE_CRCSRC_gp 6 /* CRC Source group position. */ -#define FUSE_CRCSRC0_bm (1<<6) /* CRC Source bit 0 mask. */ -#define FUSE_CRCSRC0_bp 6 /* CRC Source bit 0 position. */ -#define FUSE_CRCSRC1_bm (1<<7) /* CRC Source bit 1 mask. */ -#define FUSE_CRCSRC1_bp 7 /* CRC Source bit 1 position. */ - -/* FUSE.SYSCFG1 bit masks and bit positions */ -#define FUSE_SUT_gm 0x07 /* Startup Time group mask. */ -#define FUSE_SUT_gp 0 /* Startup Time group position. */ -#define FUSE_SUT0_bm (1<<0) /* Startup Time bit 0 mask. */ -#define FUSE_SUT0_bp 0 /* Startup Time bit 0 position. */ -#define FUSE_SUT1_bm (1<<1) /* Startup Time bit 1 mask. */ -#define FUSE_SUT1_bp 1 /* Startup Time bit 1 position. */ -#define FUSE_SUT2_bm (1<<2) /* Startup Time bit 2 mask. */ -#define FUSE_SUT2_bp 2 /* Startup Time bit 2 position. */ - - - - - - - -/* LOCKBIT - Lockbit */ -/* LOCKBIT.LOCKBIT bit masks and bit positions */ -#define LOCKBIT_LB_gm 0xFF /* Lock Bits group mask. */ -#define LOCKBIT_LB_gp 0 /* Lock Bits group position. */ -#define LOCKBIT_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ -#define LOCKBIT_LB0_bp 0 /* Lock Bits bit 0 position. */ -#define LOCKBIT_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ -#define LOCKBIT_LB1_bp 1 /* Lock Bits bit 1 position. */ -#define LOCKBIT_LB2_bm (1<<2) /* Lock Bits bit 2 mask. */ -#define LOCKBIT_LB2_bp 2 /* Lock Bits bit 2 position. */ -#define LOCKBIT_LB3_bm (1<<3) /* Lock Bits bit 3 mask. */ -#define LOCKBIT_LB3_bp 3 /* Lock Bits bit 3 position. */ -#define LOCKBIT_LB4_bm (1<<4) /* Lock Bits bit 4 mask. */ -#define LOCKBIT_LB4_bp 4 /* Lock Bits bit 4 position. */ -#define LOCKBIT_LB5_bm (1<<5) /* Lock Bits bit 5 mask. */ -#define LOCKBIT_LB5_bp 5 /* Lock Bits bit 5 position. */ -#define LOCKBIT_LB6_bm (1<<6) /* Lock Bits bit 6 mask. */ -#define LOCKBIT_LB6_bp 6 /* Lock Bits bit 6 position. */ -#define LOCKBIT_LB7_bm (1<<7) /* Lock Bits bit 7 mask. */ -#define LOCKBIT_LB7_bp 7 /* Lock Bits bit 7 position. */ - -/* NVMBIST - BIST in the NVMCTRL module */ -/* NVMBIST.CTRLA bit masks and bit positions */ -#define NVMBIST_CMD_gm 0x07 /* Command group mask. */ -#define NVMBIST_CMD_gp 0 /* Command group position. */ -#define NVMBIST_CMD0_bm (1<<0) /* Command bit 0 mask. */ -#define NVMBIST_CMD0_bp 0 /* Command bit 0 position. */ -#define NVMBIST_CMD1_bm (1<<1) /* Command bit 1 mask. */ -#define NVMBIST_CMD1_bp 1 /* Command bit 1 position. */ -#define NVMBIST_CMD2_bm (1<<2) /* Command bit 2 mask. */ -#define NVMBIST_CMD2_bp 2 /* Command bit 2 position. */ -#define NVMBIST_SAF_bm 0x08 /* Stop at fault bit mask. */ -#define NVMBIST_SAF_bp 3 /* Stop at fault bit position. */ - -/* NVMBIST.ADDRPAT bit masks and bit positions */ -#define NVMBIST_XMODE_gm 0x03 /* X address mode group mask. */ -#define NVMBIST_XMODE_gp 0 /* X address mode group position. */ -#define NVMBIST_XMODE0_bm (1<<0) /* X address mode bit 0 mask. */ -#define NVMBIST_XMODE0_bp 0 /* X address mode bit 0 position. */ -#define NVMBIST_XMODE1_bm (1<<1) /* X address mode bit 1 mask. */ -#define NVMBIST_XMODE1_bp 1 /* X address mode bit 1 position. */ -#define NVMBIST_YMODE_gm 0x0C /* Y address mode group mask. */ -#define NVMBIST_YMODE_gp 2 /* Y address mode group position. */ -#define NVMBIST_YMODE0_bm (1<<2) /* Y address mode bit 0 mask. */ -#define NVMBIST_YMODE0_bp 2 /* Y address mode bit 0 position. */ -#define NVMBIST_YMODE1_bm (1<<3) /* Y address mode bit 1 mask. */ -#define NVMBIST_YMODE1_bp 3 /* Y address mode bit 1 position. */ -#define NVMBIST_AMODE_gm 0x70 /* Address mode group mask. */ -#define NVMBIST_AMODE_gp 4 /* Address mode group position. */ -#define NVMBIST_AMODE0_bm (1<<4) /* Address mode bit 0 mask. */ -#define NVMBIST_AMODE0_bp 4 /* Address mode bit 0 position. */ -#define NVMBIST_AMODE1_bm (1<<5) /* Address mode bit 1 mask. */ -#define NVMBIST_AMODE1_bp 5 /* Address mode bit 1 position. */ -#define NVMBIST_AMODE2_bm (1<<6) /* Address mode bit 2 mask. */ -#define NVMBIST_AMODE2_bp 6 /* Address mode bit 2 position. */ - -/* NVMBIST.DATAPAT bit masks and bit positions */ -#define NVMBIST_PATTERN_gm 0x03 /* Data check pattern group mask. */ -#define NVMBIST_PATTERN_gp 0 /* Data check pattern group position. */ -#define NVMBIST_PATTERN0_bm (1<<0) /* Data check pattern bit 0 mask. */ -#define NVMBIST_PATTERN0_bp 0 /* Data check pattern bit 0 position. */ -#define NVMBIST_PATTERN1_bm (1<<1) /* Data check pattern bit 1 mask. */ -#define NVMBIST_PATTERN1_bp 1 /* Data check pattern bit 1 position. */ - -/* NVMBIST.STATUS bit masks and bit positions */ -#define NVMBIST_STATE_gm 0x0F /* FSM State group mask. */ -#define NVMBIST_STATE_gp 0 /* FSM State group position. */ -#define NVMBIST_STATE0_bm (1<<0) /* FSM State bit 0 mask. */ -#define NVMBIST_STATE0_bp 0 /* FSM State bit 0 position. */ -#define NVMBIST_STATE1_bm (1<<1) /* FSM State bit 1 mask. */ -#define NVMBIST_STATE1_bp 1 /* FSM State bit 1 position. */ -#define NVMBIST_STATE2_bm (1<<2) /* FSM State bit 2 mask. */ -#define NVMBIST_STATE2_bp 2 /* FSM State bit 2 position. */ -#define NVMBIST_STATE3_bm (1<<3) /* FSM State bit 3 mask. */ -#define NVMBIST_STATE3_bp 3 /* FSM State bit 3 position. */ - -/* NVMBIST.CNT bit masks and bit positions */ -#define NVMBIST_CNT_gm 0x7FF /* Faults counter group mask. */ -#define NVMBIST_CNT_gp 0 /* Faults counter group position. */ -#define NVMBIST_CNT0_bm (1<<0) /* Faults counter bit 0 mask. */ -#define NVMBIST_CNT0_bp 0 /* Faults counter bit 0 position. */ -#define NVMBIST_CNT1_bm (1<<1) /* Faults counter bit 1 mask. */ -#define NVMBIST_CNT1_bp 1 /* Faults counter bit 1 position. */ -#define NVMBIST_CNT2_bm (1<<2) /* Faults counter bit 2 mask. */ -#define NVMBIST_CNT2_bp 2 /* Faults counter bit 2 position. */ -#define NVMBIST_CNT3_bm (1<<3) /* Faults counter bit 3 mask. */ -#define NVMBIST_CNT3_bp 3 /* Faults counter bit 3 position. */ -#define NVMBIST_CNT4_bm (1<<4) /* Faults counter bit 4 mask. */ -#define NVMBIST_CNT4_bp 4 /* Faults counter bit 4 position. */ -#define NVMBIST_CNT5_bm (1<<5) /* Faults counter bit 5 mask. */ -#define NVMBIST_CNT5_bp 5 /* Faults counter bit 5 position. */ -#define NVMBIST_CNT6_bm (1<<6) /* Faults counter bit 6 mask. */ -#define NVMBIST_CNT6_bp 6 /* Faults counter bit 6 position. */ -#define NVMBIST_CNT7_bm (1<<7) /* Faults counter bit 7 mask. */ -#define NVMBIST_CNT7_bp 7 /* Faults counter bit 7 position. */ -#define NVMBIST_CNT8_bm (1<<8) /* Faults counter bit 8 mask. */ -#define NVMBIST_CNT8_bp 8 /* Faults counter bit 8 position. */ -#define NVMBIST_CNT9_bm (1<<9) /* Faults counter bit 9 mask. */ -#define NVMBIST_CNT9_bp 9 /* Faults counter bit 9 position. */ -#define NVMBIST_CNT10_bm (1<<10) /* Faults counter bit 10 mask. */ -#define NVMBIST_CNT10_bp 10 /* Faults counter bit 10 position. */ - -/* NVMBIST.END bit masks and bit positions */ -#define NVMBIST_END_gm 0xFFFFFF /* group mask. */ -#define NVMBIST_END_gp 0 /* group position. */ -#define NVMBIST_END0_bm (1<<0) /* bit 0 mask. */ -#define NVMBIST_END0_bp 0 /* bit 0 position. */ -#define NVMBIST_END1_bm (1<<1) /* bit 1 mask. */ -#define NVMBIST_END1_bp 1 /* bit 1 position. */ -#define NVMBIST_END2_bm (1<<2) /* bit 2 mask. */ -#define NVMBIST_END2_bp 2 /* bit 2 position. */ -#define NVMBIST_END3_bm (1<<3) /* bit 3 mask. */ -#define NVMBIST_END3_bp 3 /* bit 3 position. */ -#define NVMBIST_END4_bm (1<<4) /* bit 4 mask. */ -#define NVMBIST_END4_bp 4 /* bit 4 position. */ -#define NVMBIST_END5_bm (1<<5) /* bit 5 mask. */ -#define NVMBIST_END5_bp 5 /* bit 5 position. */ -#define NVMBIST_END6_bm (1<<6) /* bit 6 mask. */ -#define NVMBIST_END6_bp 6 /* bit 6 position. */ -#define NVMBIST_END7_bm (1<<7) /* bit 7 mask. */ -#define NVMBIST_END7_bp 7 /* bit 7 position. */ -#define NVMBIST_END8_bm (1<<8) /* bit 8 mask. */ -#define NVMBIST_END8_bp 8 /* bit 8 position. */ -#define NVMBIST_END9_bm (1<<9) /* bit 9 mask. */ -#define NVMBIST_END9_bp 9 /* bit 9 position. */ -#define NVMBIST_END10_bm (1<<10) /* bit 10 mask. */ -#define NVMBIST_END10_bp 10 /* bit 10 position. */ -#define NVMBIST_END11_bm (1<<11) /* bit 11 mask. */ -#define NVMBIST_END11_bp 11 /* bit 11 position. */ -#define NVMBIST_END12_bm (1<<12) /* bit 12 mask. */ -#define NVMBIST_END12_bp 12 /* bit 12 position. */ -#define NVMBIST_END13_bm (1<<13) /* bit 13 mask. */ -#define NVMBIST_END13_bp 13 /* bit 13 position. */ -#define NVMBIST_END14_bm (1<<14) /* bit 14 mask. */ -#define NVMBIST_END14_bp 14 /* bit 14 position. */ -#define NVMBIST_END15_bm (1<<15) /* bit 15 mask. */ -#define NVMBIST_END15_bp 15 /* bit 15 position. */ -#define NVMBIST_END16_bm (1<<16) /* bit 16 mask. */ -#define NVMBIST_END16_bp 16 /* bit 16 position. */ -#define NVMBIST_END17_bm (1<<17) /* bit 17 mask. */ -#define NVMBIST_END17_bp 17 /* bit 17 position. */ -#define NVMBIST_END18_bm (1<<18) /* bit 18 mask. */ -#define NVMBIST_END18_bp 18 /* bit 18 position. */ -#define NVMBIST_END19_bm (1<<19) /* bit 19 mask. */ -#define NVMBIST_END19_bp 19 /* bit 19 position. */ -#define NVMBIST_END20_bm (1<<20) /* bit 20 mask. */ -#define NVMBIST_END20_bp 20 /* bit 20 position. */ -#define NVMBIST_END21_bm (1<<21) /* bit 21 mask. */ -#define NVMBIST_END21_bp 21 /* bit 21 position. */ -#define NVMBIST_END22_bm (1<<22) /* bit 22 mask. */ -#define NVMBIST_END22_bp 22 /* bit 22 position. */ -#define NVMBIST_END23_bm (1<<23) /* bit 23 mask. */ -#define NVMBIST_END23_bp 23 /* bit 23 position. */ - -/* NVMCTRL - Non-volatile Memory Controller */ -/* NVMCTRL.CTRLA bit masks and bit positions */ -#define NVMCTRL_CMD_gm 0x07 /* Command group mask. */ -#define NVMCTRL_CMD_gp 0 /* Command group position. */ -#define NVMCTRL_CMD0_bm (1<<0) /* Command bit 0 mask. */ -#define NVMCTRL_CMD0_bp 0 /* Command bit 0 position. */ -#define NVMCTRL_CMD1_bm (1<<1) /* Command bit 1 mask. */ -#define NVMCTRL_CMD1_bp 1 /* Command bit 1 position. */ -#define NVMCTRL_CMD2_bm (1<<2) /* Command bit 2 mask. */ -#define NVMCTRL_CMD2_bp 2 /* Command bit 2 position. */ - -/* NVMCTRL.CTRLB bit masks and bit positions */ -#define NVMCTRL_APCWP_bm 0x01 /* Application code write protect bit mask. */ -#define NVMCTRL_APCWP_bp 0 /* Application code write protect bit position. */ -#define NVMCTRL_BOOTLOCK_bm 0x02 /* Boot Lock bit mask. */ -#define NVMCTRL_BOOTLOCK_bp 1 /* Boot Lock bit position. */ - -/* NVMCTRL.STATUS bit masks and bit positions */ -#define NVMCTRL_FBUSY_bm 0x01 /* Flash busy bit mask. */ -#define NVMCTRL_FBUSY_bp 0 /* Flash busy bit position. */ -#define NVMCTRL_EEBUSY_bm 0x02 /* EEPROM busy bit mask. */ -#define NVMCTRL_EEBUSY_bp 1 /* EEPROM busy bit position. */ -#define NVMCTRL_WRERROR_bm 0x04 /* Write error bit mask. */ -#define NVMCTRL_WRERROR_bp 2 /* Write error bit position. */ - -/* NVMCTRL.INTCTRL bit masks and bit positions */ -#define NVMCTRL_EEREADY_bm 0x01 /* EEPROM Ready bit mask. */ -#define NVMCTRL_EEREADY_bp 0 /* EEPROM Ready bit position. */ - -/* NVMCTRL.INTFLAGS bit masks and bit positions */ -/* NVMCTRL_EEREADY is already defined. */ - - - - - - - - - - - - -/* PORT - I/O Ports */ -/* PORT.INTFLAGS bit masks and bit positions */ -#define PORT_INT_gm 0xFF /* Pin Interrupt group mask. */ -#define PORT_INT_gp 0 /* Pin Interrupt group position. */ -#define PORT_INT0_bm (1<<0) /* Pin Interrupt bit 0 mask. */ -#define PORT_INT0_bp 0 /* Pin Interrupt bit 0 position. */ -#define PORT_INT1_bm (1<<1) /* Pin Interrupt bit 1 mask. */ -#define PORT_INT1_bp 1 /* Pin Interrupt bit 1 position. */ -#define PORT_INT2_bm (1<<2) /* Pin Interrupt bit 2 mask. */ -#define PORT_INT2_bp 2 /* Pin Interrupt bit 2 position. */ -#define PORT_INT3_bm (1<<3) /* Pin Interrupt bit 3 mask. */ -#define PORT_INT3_bp 3 /* Pin Interrupt bit 3 position. */ -#define PORT_INT4_bm (1<<4) /* Pin Interrupt bit 4 mask. */ -#define PORT_INT4_bp 4 /* Pin Interrupt bit 4 position. */ -#define PORT_INT5_bm (1<<5) /* Pin Interrupt bit 5 mask. */ -#define PORT_INT5_bp 5 /* Pin Interrupt bit 5 position. */ -#define PORT_INT6_bm (1<<6) /* Pin Interrupt bit 6 mask. */ -#define PORT_INT6_bp 6 /* Pin Interrupt bit 6 position. */ -#define PORT_INT7_bm (1<<7) /* Pin Interrupt bit 7 mask. */ -#define PORT_INT7_bp 7 /* Pin Interrupt bit 7 position. */ - -/* PORT.PORTCTRL bit masks and bit positions */ -#define PORT_SRL_bm 0x01 /* Slew Rate Limit Enable bit mask. */ -#define PORT_SRL_bp 0 /* Slew Rate Limit Enable bit position. */ - -/* PORT.PIN0CTRL bit masks and bit positions */ -#define PORT_ISC_gm 0x07 /* Input/Sense Configuration group mask. */ -#define PORT_ISC_gp 0 /* Input/Sense Configuration group position. */ -#define PORT_ISC0_bm (1<<0) /* Input/Sense Configuration bit 0 mask. */ -#define PORT_ISC0_bp 0 /* Input/Sense Configuration bit 0 position. */ -#define PORT_ISC1_bm (1<<1) /* Input/Sense Configuration bit 1 mask. */ -#define PORT_ISC1_bp 1 /* Input/Sense Configuration bit 1 position. */ -#define PORT_ISC2_bm (1<<2) /* Input/Sense Configuration bit 2 mask. */ -#define PORT_ISC2_bp 2 /* Input/Sense Configuration bit 2 position. */ -#define PORT_PULLUPEN_bm 0x08 /* Pullup enable bit mask. */ -#define PORT_PULLUPEN_bp 3 /* Pullup enable bit position. */ -#define PORT_INVEN_bm 0x80 /* Inverted I/O Enable bit mask. */ -#define PORT_INVEN_bp 7 /* Inverted I/O Enable bit position. */ - -/* PORT.PIN1CTRL bit masks and bit positions */ -/* PORT_ISC is already defined. */ -/* PORT_PULLUPEN is already defined. */ -/* PORT_INVEN is already defined. */ - -/* PORT.PIN2CTRL bit masks and bit positions */ -/* PORT_ISC is already defined. */ -/* PORT_PULLUPEN is already defined. */ -/* PORT_INVEN is already defined. */ - -/* PORT.PIN3CTRL bit masks and bit positions */ -/* PORT_ISC is already defined. */ -/* PORT_PULLUPEN is already defined. */ -/* PORT_INVEN is already defined. */ - -/* PORT.PIN4CTRL bit masks and bit positions */ -/* PORT_ISC is already defined. */ -/* PORT_PULLUPEN is already defined. */ -/* PORT_INVEN is already defined. */ - -/* PORT.PIN5CTRL bit masks and bit positions */ -/* PORT_ISC is already defined. */ -/* PORT_PULLUPEN is already defined. */ -/* PORT_INVEN is already defined. */ - -/* PORT.PIN6CTRL bit masks and bit positions */ -/* PORT_ISC is already defined. */ -/* PORT_PULLUPEN is already defined. */ -/* PORT_INVEN is already defined. */ - -/* PORT.PIN7CTRL bit masks and bit positions */ -/* PORT_ISC is already defined. */ -/* PORT_PULLUPEN is already defined. */ -/* PORT_INVEN is already defined. */ - -/* PORTMUX - Port Multiplexer */ -/* PORTMUX.EVSYSROUTEA bit masks and bit positions */ -#define PORTMUX_EVOUT0_bm 0x01 /* Event Output 0 bit mask. */ -#define PORTMUX_EVOUT0_bp 0 /* Event Output 0 bit position. */ -#define PORTMUX_EVOUT1_bm 0x02 /* Event Output 1 bit mask. */ -#define PORTMUX_EVOUT1_bp 1 /* Event Output 1 bit position. */ -#define PORTMUX_EVOUT2_bm 0x04 /* Event Output 2 bit mask. */ -#define PORTMUX_EVOUT2_bp 2 /* Event Output 2 bit position. */ -#define PORTMUX_EVOUT3_bm 0x08 /* Event Output 3 bit mask. */ -#define PORTMUX_EVOUT3_bp 3 /* Event Output 3 bit position. */ -#define PORTMUX_EVOUT4_bm 0x10 /* Event Output 4 bit mask. */ -#define PORTMUX_EVOUT4_bp 4 /* Event Output 4 bit position. */ -#define PORTMUX_EVOUT5_bm 0x20 /* Event Output 5 bit mask. */ -#define PORTMUX_EVOUT5_bp 5 /* Event Output 5 bit position. */ - -/* PORTMUX.CCLROUTEA bit masks and bit positions */ -#define PORTMUX_LUT0_bm 0x01 /* CCL LUT0 bit mask. */ -#define PORTMUX_LUT0_bp 0 /* CCL LUT0 bit position. */ -#define PORTMUX_LUT1_bm 0x02 /* CCL LUT1 bit mask. */ -#define PORTMUX_LUT1_bp 1 /* CCL LUT1 bit position. */ -#define PORTMUX_LUT2_bm 0x04 /* CCL LUT2 bit mask. */ -#define PORTMUX_LUT2_bp 2 /* CCL LUT2 bit position. */ -#define PORTMUX_LUT3_bm 0x08 /* CCL LUT3 bit mask. */ -#define PORTMUX_LUT3_bp 3 /* CCL LUT3 bit position. */ - -/* PORTMUX.USARTROUTEA bit masks and bit positions */ -#define PORTMUX_USART0_gm 0x03 /* Port Multiplexer USART0 group mask. */ -#define PORTMUX_USART0_gp 0 /* Port Multiplexer USART0 group position. */ -#define PORTMUX_USART00_bm (1<<0) /* Port Multiplexer USART0 bit 0 mask. */ -#define PORTMUX_USART00_bp 0 /* Port Multiplexer USART0 bit 0 position. */ -#define PORTMUX_USART01_bm (1<<1) /* Port Multiplexer USART0 bit 1 mask. */ -#define PORTMUX_USART01_bp 1 /* Port Multiplexer USART0 bit 1 position. */ -#define PORTMUX_USART1_gm 0x0C /* Port Multiplexer USART1 group mask. */ -#define PORTMUX_USART1_gp 2 /* Port Multiplexer USART1 group position. */ -#define PORTMUX_USART10_bm (1<<2) /* Port Multiplexer USART1 bit 0 mask. */ -#define PORTMUX_USART10_bp 2 /* Port Multiplexer USART1 bit 0 position. */ -#define PORTMUX_USART11_bm (1<<3) /* Port Multiplexer USART1 bit 1 mask. */ -#define PORTMUX_USART11_bp 3 /* Port Multiplexer USART1 bit 1 position. */ -#define PORTMUX_USART2_gm 0x30 /* Port Multiplexer USART2 group mask. */ -#define PORTMUX_USART2_gp 4 /* Port Multiplexer USART2 group position. */ -#define PORTMUX_USART20_bm (1<<4) /* Port Multiplexer USART2 bit 0 mask. */ -#define PORTMUX_USART20_bp 4 /* Port Multiplexer USART2 bit 0 position. */ -#define PORTMUX_USART21_bm (1<<5) /* Port Multiplexer USART2 bit 1 mask. */ -#define PORTMUX_USART21_bp 5 /* Port Multiplexer USART2 bit 1 position. */ -#define PORTMUX_USART3_gm 0xC0 /* Port Multiplexer USART3 group mask. */ -#define PORTMUX_USART3_gp 6 /* Port Multiplexer USART3 group position. */ -#define PORTMUX_USART30_bm (1<<6) /* Port Multiplexer USART3 bit 0 mask. */ -#define PORTMUX_USART30_bp 6 /* Port Multiplexer USART3 bit 0 position. */ -#define PORTMUX_USART31_bm (1<<7) /* Port Multiplexer USART3 bit 1 mask. */ -#define PORTMUX_USART31_bp 7 /* Port Multiplexer USART3 bit 1 position. */ - -/* PORTMUX.TWISPIROUTEA bit masks and bit positions */ -#define PORTMUX_SPI0_gm 0x03 /* Port Multiplexer SPI0 group mask. */ -#define PORTMUX_SPI0_gp 0 /* Port Multiplexer SPI0 group position. */ -#define PORTMUX_SPI00_bm (1<<0) /* Port Multiplexer SPI0 bit 0 mask. */ -#define PORTMUX_SPI00_bp 0 /* Port Multiplexer SPI0 bit 0 position. */ -#define PORTMUX_SPI01_bm (1<<1) /* Port Multiplexer SPI0 bit 1 mask. */ -#define PORTMUX_SPI01_bp 1 /* Port Multiplexer SPI0 bit 1 position. */ -#define PORTMUX_TWI0_gm 0x30 /* Port Multiplexer TWI0 group mask. */ -#define PORTMUX_TWI0_gp 4 /* Port Multiplexer TWI0 group position. */ -#define PORTMUX_TWI00_bm (1<<4) /* Port Multiplexer TWI0 bit 0 mask. */ -#define PORTMUX_TWI00_bp 4 /* Port Multiplexer TWI0 bit 0 position. */ -#define PORTMUX_TWI01_bm (1<<5) /* Port Multiplexer TWI0 bit 1 mask. */ -#define PORTMUX_TWI01_bp 5 /* Port Multiplexer TWI0 bit 1 position. */ - -/* PORTMUX.TCAROUTEA bit masks and bit positions */ -#define PORTMUX_TCA0_gm 0x07 /* Port Multiplexer TCA0 group mask. */ -#define PORTMUX_TCA0_gp 0 /* Port Multiplexer TCA0 group position. */ -#define PORTMUX_TCA00_bm (1<<0) /* Port Multiplexer TCA0 bit 0 mask. */ -#define PORTMUX_TCA00_bp 0 /* Port Multiplexer TCA0 bit 0 position. */ -#define PORTMUX_TCA01_bm (1<<1) /* Port Multiplexer TCA0 bit 1 mask. */ -#define PORTMUX_TCA01_bp 1 /* Port Multiplexer TCA0 bit 1 position. */ -#define PORTMUX_TCA02_bm (1<<2) /* Port Multiplexer TCA0 bit 2 mask. */ -#define PORTMUX_TCA02_bp 2 /* Port Multiplexer TCA0 bit 2 position. */ - -/* PORTMUX.TCBROUTEA bit masks and bit positions */ -#define PORTMUX_TCB0_bm 0x01 /* Port Multiplexer TCB0 bit mask. */ -#define PORTMUX_TCB0_bp 0 /* Port Multiplexer TCB0 bit position. */ -#define PORTMUX_TCB1_bm 0x02 /* Port Multiplexer TCB1 bit mask. */ -#define PORTMUX_TCB1_bp 1 /* Port Multiplexer TCB1 bit position. */ -#define PORTMUX_TCB2_bm 0x04 /* Port Multiplexer TCB2 bit mask. */ -#define PORTMUX_TCB2_bp 2 /* Port Multiplexer TCB2 bit position. */ -#define PORTMUX_TCB3_bm 0x08 /* Port Multiplexer TCB3 bit mask. */ -#define PORTMUX_TCB3_bp 3 /* Port Multiplexer TCB3 bit position. */ - -/* RSTCTRL - Reset controller */ -/* RSTCTRL.RSTFR bit masks and bit positions */ -#define RSTCTRL_PORF_bm 0x01 /* Power on Reset flag bit mask. */ -#define RSTCTRL_PORF_bp 0 /* Power on Reset flag bit position. */ -#define RSTCTRL_BORF_bm 0x02 /* Brown out detector Reset flag bit mask. */ -#define RSTCTRL_BORF_bp 1 /* Brown out detector Reset flag bit position. */ -#define RSTCTRL_EXTRF_bm 0x04 /* External Reset flag bit mask. */ -#define RSTCTRL_EXTRF_bp 2 /* External Reset flag bit position. */ -#define RSTCTRL_WDRF_bm 0x08 /* Watch dog Reset flag bit mask. */ -#define RSTCTRL_WDRF_bp 3 /* Watch dog Reset flag bit position. */ -#define RSTCTRL_SWRF_bm 0x10 /* Software Reset flag bit mask. */ -#define RSTCTRL_SWRF_bp 4 /* Software Reset flag bit position. */ -#define RSTCTRL_UPDIRF_bm 0x20 /* UPDI Reset flag bit mask. */ -#define RSTCTRL_UPDIRF_bp 5 /* UPDI Reset flag bit position. */ - -/* RSTCTRL.SWRR bit masks and bit positions */ -#define RSTCTRL_SWRE_bm 0x01 /* Software reset enable bit mask. */ -#define RSTCTRL_SWRE_bp 0 /* Software reset enable bit position. */ - -/* RTC - Real-Time Counter */ -/* RTC.CTRLA bit masks and bit positions */ -#define RTC_RTCEN_bm 0x01 /* Enable bit mask. */ -#define RTC_RTCEN_bp 0 /* Enable bit position. */ -#define RTC_PRESCALER_gm 0x78 /* Prescaling Factor group mask. */ -#define RTC_PRESCALER_gp 3 /* Prescaling Factor group position. */ -#define RTC_PRESCALER0_bm (1<<3) /* Prescaling Factor bit 0 mask. */ -#define RTC_PRESCALER0_bp 3 /* Prescaling Factor bit 0 position. */ -#define RTC_PRESCALER1_bm (1<<4) /* Prescaling Factor bit 1 mask. */ -#define RTC_PRESCALER1_bp 4 /* Prescaling Factor bit 1 position. */ -#define RTC_PRESCALER2_bm (1<<5) /* Prescaling Factor bit 2 mask. */ -#define RTC_PRESCALER2_bp 5 /* Prescaling Factor bit 2 position. */ -#define RTC_PRESCALER3_bm (1<<6) /* Prescaling Factor bit 3 mask. */ -#define RTC_PRESCALER3_bp 6 /* Prescaling Factor bit 3 position. */ -#define RTC_RUNSTDBY_bm 0x80 /* Run In Standby bit mask. */ -#define RTC_RUNSTDBY_bp 7 /* Run In Standby bit position. */ - -/* RTC.STATUS bit masks and bit positions */ -#define RTC_CTRLABUSY_bm 0x01 /* CTRLA Synchronization Busy Flag bit mask. */ -#define RTC_CTRLABUSY_bp 0 /* CTRLA Synchronization Busy Flag bit position. */ -#define RTC_CNTBUSY_bm 0x02 /* Count Synchronization Busy Flag bit mask. */ -#define RTC_CNTBUSY_bp 1 /* Count Synchronization Busy Flag bit position. */ -#define RTC_PERBUSY_bm 0x04 /* Period Synchronization Busy Flag bit mask. */ -#define RTC_PERBUSY_bp 2 /* Period Synchronization Busy Flag bit position. */ -#define RTC_CMPBUSY_bm 0x08 /* Comparator Synchronization Busy Flag bit mask. */ -#define RTC_CMPBUSY_bp 3 /* Comparator Synchronization Busy Flag bit position. */ - -/* RTC.INTCTRL bit masks and bit positions */ -#define RTC_OVF_bm 0x01 /* Overflow Interrupt enable bit mask. */ -#define RTC_OVF_bp 0 /* Overflow Interrupt enable bit position. */ -#define RTC_CMP_bm 0x02 /* Compare Match Interrupt enable bit mask. */ -#define RTC_CMP_bp 1 /* Compare Match Interrupt enable bit position. */ - -/* RTC.INTFLAGS bit masks and bit positions */ -/* RTC_OVF is already defined. */ -/* RTC_CMP is already defined. */ - - -/* RTC.DBGCTRL bit masks and bit positions */ -#define RTC_DBGRUN_bm 0x01 /* Run in debug bit mask. */ -#define RTC_DBGRUN_bp 0 /* Run in debug bit position. */ - -/* RTC.CLKSEL bit masks and bit positions */ -#define RTC_CLKSEL_gm 0x03 /* Clock Select group mask. */ -#define RTC_CLKSEL_gp 0 /* Clock Select group position. */ -#define RTC_CLKSEL0_bm (1<<0) /* Clock Select bit 0 mask. */ -#define RTC_CLKSEL0_bp 0 /* Clock Select bit 0 position. */ -#define RTC_CLKSEL1_bm (1<<1) /* Clock Select bit 1 mask. */ -#define RTC_CLKSEL1_bp 1 /* Clock Select bit 1 position. */ - - - - -/* RTC.PITCTRLA bit masks and bit positions */ -#define RTC_PITEN_bm 0x01 /* Enable bit mask. */ -#define RTC_PITEN_bp 0 /* Enable bit position. */ -#define RTC_PERIOD_gm 0x78 /* Period group mask. */ -#define RTC_PERIOD_gp 3 /* Period group position. */ -#define RTC_PERIOD0_bm (1<<3) /* Period bit 0 mask. */ -#define RTC_PERIOD0_bp 3 /* Period bit 0 position. */ -#define RTC_PERIOD1_bm (1<<4) /* Period bit 1 mask. */ -#define RTC_PERIOD1_bp 4 /* Period bit 1 position. */ -#define RTC_PERIOD2_bm (1<<5) /* Period bit 2 mask. */ -#define RTC_PERIOD2_bp 5 /* Period bit 2 position. */ -#define RTC_PERIOD3_bm (1<<6) /* Period bit 3 mask. */ -#define RTC_PERIOD3_bp 6 /* Period bit 3 position. */ - -/* RTC.PITSTATUS bit masks and bit positions */ -#define RTC_CTRLBUSY_bm 0x01 /* CTRLA Synchronization Busy Flag bit mask. */ -#define RTC_CTRLBUSY_bp 0 /* CTRLA Synchronization Busy Flag bit position. */ - -/* RTC.PITINTCTRL bit masks and bit positions */ -#define RTC_PI_bm 0x01 /* Periodic Interrupt bit mask. */ -#define RTC_PI_bp 0 /* Periodic Interrupt bit position. */ - -/* RTC.PITINTFLAGS bit masks and bit positions */ -/* RTC_PI is already defined. */ - -/* RTC.PITDBGCTRL bit masks and bit positions */ -/* RTC_DBGRUN is already defined. */ - - - - - - - - - - - - - - - - - - - - - - - - - - -/* SLPCTRL - Sleep Controller */ -/* SLPCTRL.CTRLA bit masks and bit positions */ -#define SLPCTRL_SEN_bm 0x01 /* Sleep enable bit mask. */ -#define SLPCTRL_SEN_bp 0 /* Sleep enable bit position. */ -#define SLPCTRL_SMODE_gm 0x06 /* Sleep mode group mask. */ -#define SLPCTRL_SMODE_gp 1 /* Sleep mode group position. */ -#define SLPCTRL_SMODE0_bm (1<<1) /* Sleep mode bit 0 mask. */ -#define SLPCTRL_SMODE0_bp 1 /* Sleep mode bit 0 position. */ -#define SLPCTRL_SMODE1_bm (1<<2) /* Sleep mode bit 1 mask. */ -#define SLPCTRL_SMODE1_bp 2 /* Sleep mode bit 1 position. */ - -/* SPI - Serial Peripheral Interface */ -/* SPI.CTRLA bit masks and bit positions */ -#define SPI_ENABLE_bm 0x01 /* Enable Module bit mask. */ -#define SPI_ENABLE_bp 0 /* Enable Module bit position. */ -#define SPI_PRESC_gm 0x06 /* Prescaler group mask. */ -#define SPI_PRESC_gp 1 /* Prescaler group position. */ -#define SPI_PRESC0_bm (1<<1) /* Prescaler bit 0 mask. */ -#define SPI_PRESC0_bp 1 /* Prescaler bit 0 position. */ -#define SPI_PRESC1_bm (1<<2) /* Prescaler bit 1 mask. */ -#define SPI_PRESC1_bp 2 /* Prescaler bit 1 position. */ -#define SPI_CLK2X_bm 0x10 /* Enable Double Speed bit mask. */ -#define SPI_CLK2X_bp 4 /* Enable Double Speed bit position. */ -#define SPI_MASTER_bm 0x20 /* Master Operation Enable bit mask. */ -#define SPI_MASTER_bp 5 /* Master Operation Enable bit position. */ -#define SPI_DORD_bm 0x40 /* Data Order Setting bit mask. */ -#define SPI_DORD_bp 6 /* Data Order Setting bit position. */ - -/* SPI.CTRLB bit masks and bit positions */ -#define SPI_MODE_gm 0x03 /* SPI Mode group mask. */ -#define SPI_MODE_gp 0 /* SPI Mode group position. */ -#define SPI_MODE0_bm (1<<0) /* SPI Mode bit 0 mask. */ -#define SPI_MODE0_bp 0 /* SPI Mode bit 0 position. */ -#define SPI_MODE1_bm (1<<1) /* SPI Mode bit 1 mask. */ -#define SPI_MODE1_bp 1 /* SPI Mode bit 1 position. */ -#define SPI_SSD_bm 0x04 /* Slave Select Disable bit mask. */ -#define SPI_SSD_bp 2 /* Slave Select Disable bit position. */ -#define SPI_BUFWR_bm 0x40 /* Buffer Write Mode bit mask. */ -#define SPI_BUFWR_bp 6 /* Buffer Write Mode bit position. */ -#define SPI_BUFEN_bm 0x80 /* Buffer Mode Enable bit mask. */ -#define SPI_BUFEN_bp 7 /* Buffer Mode Enable bit position. */ - -/* SPI.INTCTRL bit masks and bit positions */ -#define SPI_IE_bm 0x01 /* Interrupt Enable bit mask. */ -#define SPI_IE_bp 0 /* Interrupt Enable bit position. */ -#define SPI_SSIE_bm 0x10 /* Slave Select Trigger Interrupt Enable bit mask. */ -#define SPI_SSIE_bp 4 /* Slave Select Trigger Interrupt Enable bit position. */ -#define SPI_DREIE_bm 0x20 /* Data Register Empty Interrupt Enable bit mask. */ -#define SPI_DREIE_bp 5 /* Data Register Empty Interrupt Enable bit position. */ -#define SPI_TXCIE_bm 0x40 /* Transfer Complete Interrupt Enable bit mask. */ -#define SPI_TXCIE_bp 6 /* Transfer Complete Interrupt Enable bit position. */ -#define SPI_RXCIE_bm 0x80 /* Receive Complete Interrupt Enable bit mask. */ -#define SPI_RXCIE_bp 7 /* Receive Complete Interrupt Enable bit position. */ - -/* SPI.INTFLAGS bit masks and bit positions */ -#define SPI_BUFOVF_bm 0x01 /* Buffer Overflow bit mask. */ -#define SPI_BUFOVF_bp 0 /* Buffer Overflow bit position. */ -#define SPI_SSIF_bm 0x10 /* Slave Select Trigger Interrupt Flag bit mask. */ -#define SPI_SSIF_bp 4 /* Slave Select Trigger Interrupt Flag bit position. */ -#define SPI_DREIF_bm 0x20 /* Data Register Empty Interrupt Flag bit mask. */ -#define SPI_DREIF_bp 5 /* Data Register Empty Interrupt Flag bit position. */ -#define SPI_TXCIF_bm 0x40 /* Transfer Complete Interrupt Flag bit mask. */ -#define SPI_TXCIF_bp 6 /* Transfer Complete Interrupt Flag bit position. */ -#define SPI_WRCOL_bm 0x40 /* Write Collision bit mask. */ -#define SPI_WRCOL_bp 6 /* Write Collision bit position. */ -#define SPI_RXCIF_bm 0x80 /* Receive Complete Interrupt Flag bit mask. */ -#define SPI_RXCIF_bp 7 /* Receive Complete Interrupt Flag bit position. */ -#define SPI_IF_bm 0x80 /* Interrupt Flag bit mask. */ -#define SPI_IF_bp 7 /* Interrupt Flag bit position. */ - - - -/* SYSCFG - System Configuration Registers */ -/* SYSCFG.EXTBRK bit masks and bit positions */ -#define SYSCFG_ENEXTBRK_bm 0x01 /* External break enable bit mask. */ -#define SYSCFG_ENEXTBRK_bp 0 /* External break enable bit position. */ - - -/* SYSCFG.OCDMS bit masks and bit positions */ -#define SYSCFG_OCDMR_bm 0x01 /* OCD Message Read bit mask. */ -#define SYSCFG_OCDMR_bp 0 /* OCD Message Read bit position. */ - -/* TCA - 16-bit Timer/Counter Type A */ -/* TCA_SINGLE.CTRLA bit masks and bit positions */ -#define TCA_SINGLE_ENABLE_bm 0x01 /* Module Enable bit mask. */ -#define TCA_SINGLE_ENABLE_bp 0 /* Module Enable bit position. */ -#define TCA_SINGLE_CLKSEL_gm 0x0E /* Clock Selection group mask. */ -#define TCA_SINGLE_CLKSEL_gp 1 /* Clock Selection group position. */ -#define TCA_SINGLE_CLKSEL0_bm (1<<1) /* Clock Selection bit 0 mask. */ -#define TCA_SINGLE_CLKSEL0_bp 1 /* Clock Selection bit 0 position. */ -#define TCA_SINGLE_CLKSEL1_bm (1<<2) /* Clock Selection bit 1 mask. */ -#define TCA_SINGLE_CLKSEL1_bp 2 /* Clock Selection bit 1 position. */ -#define TCA_SINGLE_CLKSEL2_bm (1<<3) /* Clock Selection bit 2 mask. */ -#define TCA_SINGLE_CLKSEL2_bp 3 /* Clock Selection bit 2 position. */ - -/* TCA_SINGLE.CTRLB bit masks and bit positions */ -#define TCA_SINGLE_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ -#define TCA_SINGLE_WGMODE_gp 0 /* Waveform generation mode group position. */ -#define TCA_SINGLE_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ -#define TCA_SINGLE_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ -#define TCA_SINGLE_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ -#define TCA_SINGLE_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ -#define TCA_SINGLE_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ -#define TCA_SINGLE_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ -#define TCA_SINGLE_ALUPD_bm 0x08 /* Auto Lock Update bit mask. */ -#define TCA_SINGLE_ALUPD_bp 3 /* Auto Lock Update bit position. */ -#define TCA_SINGLE_CMP0EN_bm 0x10 /* Compare 0 Enable bit mask. */ -#define TCA_SINGLE_CMP0EN_bp 4 /* Compare 0 Enable bit position. */ -#define TCA_SINGLE_CMP1EN_bm 0x20 /* Compare 1 Enable bit mask. */ -#define TCA_SINGLE_CMP1EN_bp 5 /* Compare 1 Enable bit position. */ -#define TCA_SINGLE_CMP2EN_bm 0x40 /* Compare 2 Enable bit mask. */ -#define TCA_SINGLE_CMP2EN_bp 6 /* Compare 2 Enable bit position. */ - -/* TCA_SINGLE.CTRLC bit masks and bit positions */ -#define TCA_SINGLE_CMP0OV_bm 0x01 /* Compare 0 Waveform Output Value bit mask. */ -#define TCA_SINGLE_CMP0OV_bp 0 /* Compare 0 Waveform Output Value bit position. */ -#define TCA_SINGLE_CMP1OV_bm 0x02 /* Compare 1 Waveform Output Value bit mask. */ -#define TCA_SINGLE_CMP1OV_bp 1 /* Compare 1 Waveform Output Value bit position. */ -#define TCA_SINGLE_CMP2OV_bm 0x04 /* Compare 2 Waveform Output Value bit mask. */ -#define TCA_SINGLE_CMP2OV_bp 2 /* Compare 2 Waveform Output Value bit position. */ - -/* TCA_SINGLE.CTRLD bit masks and bit positions */ -#define TCA_SINGLE_SPLITM_bm 0x01 /* Split Mode Enable bit mask. */ -#define TCA_SINGLE_SPLITM_bp 0 /* Split Mode Enable bit position. */ - -/* TCA_SINGLE.CTRLECLR bit masks and bit positions */ -#define TCA_SINGLE_DIR_bm 0x01 /* Direction bit mask. */ -#define TCA_SINGLE_DIR_bp 0 /* Direction bit position. */ -#define TCA_SINGLE_LUPD_bm 0x02 /* Lock Update bit mask. */ -#define TCA_SINGLE_LUPD_bp 1 /* Lock Update bit position. */ -#define TCA_SINGLE_CMD_gm 0x0C /* Command group mask. */ -#define TCA_SINGLE_CMD_gp 2 /* Command group position. */ -#define TCA_SINGLE_CMD0_bm (1<<2) /* Command bit 0 mask. */ -#define TCA_SINGLE_CMD0_bp 2 /* Command bit 0 position. */ -#define TCA_SINGLE_CMD1_bm (1<<3) /* Command bit 1 mask. */ -#define TCA_SINGLE_CMD1_bp 3 /* Command bit 1 position. */ - -/* TCA_SINGLE.CTRLESET bit masks and bit positions */ -/* TCA_SINGLE_DIR is already defined. */ -/* TCA_SINGLE_LUPD is already defined. */ -/* TCA_SINGLE_CMD is already defined. */ - -/* TCA_SINGLE.CTRLFCLR bit masks and bit positions */ -#define TCA_SINGLE_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ -#define TCA_SINGLE_PERBV_bp 0 /* Period Buffer Valid bit position. */ -#define TCA_SINGLE_CMP0BV_bm 0x02 /* Compare 0 Buffer Valid bit mask. */ -#define TCA_SINGLE_CMP0BV_bp 1 /* Compare 0 Buffer Valid bit position. */ -#define TCA_SINGLE_CMP1BV_bm 0x04 /* Compare 1 Buffer Valid bit mask. */ -#define TCA_SINGLE_CMP1BV_bp 2 /* Compare 1 Buffer Valid bit position. */ -#define TCA_SINGLE_CMP2BV_bm 0x08 /* Compare 2 Buffer Valid bit mask. */ -#define TCA_SINGLE_CMP2BV_bp 3 /* Compare 2 Buffer Valid bit position. */ - -/* TCA_SINGLE.CTRLFSET bit masks and bit positions */ -/* TCA_SINGLE_PERBV is already defined. */ -/* TCA_SINGLE_CMP0BV is already defined. */ -/* TCA_SINGLE_CMP1BV is already defined. */ -/* TCA_SINGLE_CMP2BV is already defined. */ - -/* TCA_SINGLE.EVCTRL bit masks and bit positions */ -#define TCA_SINGLE_CNTEI_bm 0x01 /* Count on Event Input bit mask. */ -#define TCA_SINGLE_CNTEI_bp 0 /* Count on Event Input bit position. */ -#define TCA_SINGLE_EVACT_gm 0x06 /* Event Action group mask. */ -#define TCA_SINGLE_EVACT_gp 1 /* Event Action group position. */ -#define TCA_SINGLE_EVACT0_bm (1<<1) /* Event Action bit 0 mask. */ -#define TCA_SINGLE_EVACT0_bp 1 /* Event Action bit 0 position. */ -#define TCA_SINGLE_EVACT1_bm (1<<2) /* Event Action bit 1 mask. */ -#define TCA_SINGLE_EVACT1_bp 2 /* Event Action bit 1 position. */ - -/* TCA_SINGLE.INTCTRL bit masks and bit positions */ -#define TCA_SINGLE_OVF_bm 0x01 /* Overflow Interrupt bit mask. */ -#define TCA_SINGLE_OVF_bp 0 /* Overflow Interrupt bit position. */ -#define TCA_SINGLE_CMP0_bm 0x10 /* Compare 0 Interrupt bit mask. */ -#define TCA_SINGLE_CMP0_bp 4 /* Compare 0 Interrupt bit position. */ -#define TCA_SINGLE_CMP1_bm 0x20 /* Compare 1 Interrupt bit mask. */ -#define TCA_SINGLE_CMP1_bp 5 /* Compare 1 Interrupt bit position. */ -#define TCA_SINGLE_CMP2_bm 0x40 /* Compare 2 Interrupt bit mask. */ -#define TCA_SINGLE_CMP2_bp 6 /* Compare 2 Interrupt bit position. */ - -/* TCA_SINGLE.INTFLAGS bit masks and bit positions */ -/* TCA_SINGLE_OVF is already defined. */ -/* TCA_SINGLE_CMP0 is already defined. */ -/* TCA_SINGLE_CMP1 is already defined. */ -/* TCA_SINGLE_CMP2 is already defined. */ - -/* TCA_SINGLE.DBGCTRL bit masks and bit positions */ -#define TCA_SINGLE_DBGRUN_bm 0x01 /* Debug Run bit mask. */ -#define TCA_SINGLE_DBGRUN_bp 0 /* Debug Run bit position. */ - - - - - - - - - - - -/* TCA_SPLIT.CTRLA bit masks and bit positions */ -#define TCA_SPLIT_ENABLE_bm 0x01 /* Module Enable bit mask. */ -#define TCA_SPLIT_ENABLE_bp 0 /* Module Enable bit position. */ -#define TCA_SPLIT_CLKSEL_gm 0x0E /* Clock Selection group mask. */ -#define TCA_SPLIT_CLKSEL_gp 1 /* Clock Selection group position. */ -#define TCA_SPLIT_CLKSEL0_bm (1<<1) /* Clock Selection bit 0 mask. */ -#define TCA_SPLIT_CLKSEL0_bp 1 /* Clock Selection bit 0 position. */ -#define TCA_SPLIT_CLKSEL1_bm (1<<2) /* Clock Selection bit 1 mask. */ -#define TCA_SPLIT_CLKSEL1_bp 2 /* Clock Selection bit 1 position. */ -#define TCA_SPLIT_CLKSEL2_bm (1<<3) /* Clock Selection bit 2 mask. */ -#define TCA_SPLIT_CLKSEL2_bp 3 /* Clock Selection bit 2 position. */ - -/* TCA_SPLIT.CTRLB bit masks and bit positions */ -#define TCA_SPLIT_LCMP0EN_bm 0x01 /* Low Compare 0 Enable bit mask. */ -#define TCA_SPLIT_LCMP0EN_bp 0 /* Low Compare 0 Enable bit position. */ -#define TCA_SPLIT_LCMP1EN_bm 0x02 /* Low Compare 1 Enable bit mask. */ -#define TCA_SPLIT_LCMP1EN_bp 1 /* Low Compare 1 Enable bit position. */ -#define TCA_SPLIT_LCMP2EN_bm 0x04 /* Low Compare 2 Enable bit mask. */ -#define TCA_SPLIT_LCMP2EN_bp 2 /* Low Compare 2 Enable bit position. */ -#define TCA_SPLIT_HCMP0EN_bm 0x10 /* High Compare 0 Enable bit mask. */ -#define TCA_SPLIT_HCMP0EN_bp 4 /* High Compare 0 Enable bit position. */ -#define TCA_SPLIT_HCMP1EN_bm 0x20 /* High Compare 1 Enable bit mask. */ -#define TCA_SPLIT_HCMP1EN_bp 5 /* High Compare 1 Enable bit position. */ -#define TCA_SPLIT_HCMP2EN_bm 0x40 /* High Compare 2 Enable bit mask. */ -#define TCA_SPLIT_HCMP2EN_bp 6 /* High Compare 2 Enable bit position. */ - -/* TCA_SPLIT.CTRLC bit masks and bit positions */ -#define TCA_SPLIT_LCMP0OV_bm 0x01 /* Low Compare 0 Output Value bit mask. */ -#define TCA_SPLIT_LCMP0OV_bp 0 /* Low Compare 0 Output Value bit position. */ -#define TCA_SPLIT_LCMP1OV_bm 0x02 /* Low Compare 1 Output Value bit mask. */ -#define TCA_SPLIT_LCMP1OV_bp 1 /* Low Compare 1 Output Value bit position. */ -#define TCA_SPLIT_LCMP2OV_bm 0x04 /* Low Compare 2 Output Value bit mask. */ -#define TCA_SPLIT_LCMP2OV_bp 2 /* Low Compare 2 Output Value bit position. */ -#define TCA_SPLIT_HCMP0OV_bm 0x10 /* High Compare 0 Output Value bit mask. */ -#define TCA_SPLIT_HCMP0OV_bp 4 /* High Compare 0 Output Value bit position. */ -#define TCA_SPLIT_HCMP1OV_bm 0x20 /* High Compare 1 Output Value bit mask. */ -#define TCA_SPLIT_HCMP1OV_bp 5 /* High Compare 1 Output Value bit position. */ -#define TCA_SPLIT_HCMP2OV_bm 0x40 /* High Compare 2 Output Value bit mask. */ -#define TCA_SPLIT_HCMP2OV_bp 6 /* High Compare 2 Output Value bit position. */ - -/* TCA_SPLIT.CTRLD bit masks and bit positions */ -#define TCA_SPLIT_SPLITM_bm 0x01 /* Split Mode Enable bit mask. */ -#define TCA_SPLIT_SPLITM_bp 0 /* Split Mode Enable bit position. */ - -/* TCA_SPLIT.CTRLECLR bit masks and bit positions */ -#define TCA_SPLIT_CMD_gm 0x0C /* Command group mask. */ -#define TCA_SPLIT_CMD_gp 2 /* Command group position. */ -#define TCA_SPLIT_CMD0_bm (1<<2) /* Command bit 0 mask. */ -#define TCA_SPLIT_CMD0_bp 2 /* Command bit 0 position. */ -#define TCA_SPLIT_CMD1_bm (1<<3) /* Command bit 1 mask. */ -#define TCA_SPLIT_CMD1_bp 3 /* Command bit 1 position. */ - -/* TCA_SPLIT.CTRLESET bit masks and bit positions */ -/* TCA_SPLIT_CMD is already defined. */ - -/* TCA_SPLIT.INTCTRL bit masks and bit positions */ -#define TCA_SPLIT_LUNF_bm 0x01 /* Low Underflow Interrupt Enable bit mask. */ -#define TCA_SPLIT_LUNF_bp 0 /* Low Underflow Interrupt Enable bit position. */ -#define TCA_SPLIT_HUNF_bm 0x02 /* High Underflow Interrupt Enable bit mask. */ -#define TCA_SPLIT_HUNF_bp 1 /* High Underflow Interrupt Enable bit position. */ -#define TCA_SPLIT_LCMP0_bm 0x10 /* Low Compare 0 Interrupt Enable bit mask. */ -#define TCA_SPLIT_LCMP0_bp 4 /* Low Compare 0 Interrupt Enable bit position. */ -#define TCA_SPLIT_LCMP1_bm 0x20 /* Low Compare 1 Interrupt Enable bit mask. */ -#define TCA_SPLIT_LCMP1_bp 5 /* Low Compare 1 Interrupt Enable bit position. */ -#define TCA_SPLIT_LCMP2_bm 0x40 /* Low Compare 2 Interrupt Enable bit mask. */ -#define TCA_SPLIT_LCMP2_bp 6 /* Low Compare 2 Interrupt Enable bit position. */ - -/* TCA_SPLIT.INTFLAGS bit masks and bit positions */ -/* TCA_SPLIT_LUNF is already defined. */ -/* TCA_SPLIT_HUNF is already defined. */ -/* TCA_SPLIT_LCMP0 is already defined. */ -/* TCA_SPLIT_LCMP1 is already defined. */ -/* TCA_SPLIT_LCMP2 is already defined. */ - -/* TCA_SPLIT.DBGCTRL bit masks and bit positions */ -#define TCA_SPLIT_DBGRUN_bm 0x01 /* Debug Run bit mask. */ -#define TCA_SPLIT_DBGRUN_bp 0 /* Debug Run bit position. */ - - - - - - - - - - - -/* TCB - 16-bit Timer Type B */ -/* TCB.CTRLA bit masks and bit positions */ -#define TCB_ENABLE_bm 0x01 /* Enable bit mask. */ -#define TCB_ENABLE_bp 0 /* Enable bit position. */ -#define TCB_CLKSEL_gm 0x06 /* Clock Select group mask. */ -#define TCB_CLKSEL_gp 1 /* Clock Select group position. */ -#define TCB_CLKSEL0_bm (1<<1) /* Clock Select bit 0 mask. */ -#define TCB_CLKSEL0_bp 1 /* Clock Select bit 0 position. */ -#define TCB_CLKSEL1_bm (1<<2) /* Clock Select bit 1 mask. */ -#define TCB_CLKSEL1_bp 2 /* Clock Select bit 1 position. */ -#define TCB_SYNCUPD_bm 0x10 /* Synchronize Update bit mask. */ -#define TCB_SYNCUPD_bp 4 /* Synchronize Update bit position. */ -#define TCB_RUNSTDBY_bm 0x40 /* Run Standby bit mask. */ -#define TCB_RUNSTDBY_bp 6 /* Run Standby bit position. */ - -/* TCB.CTRLB bit masks and bit positions */ -#define TCB_CNTMODE_gm 0x07 /* Timer Mode group mask. */ -#define TCB_CNTMODE_gp 0 /* Timer Mode group position. */ -#define TCB_CNTMODE0_bm (1<<0) /* Timer Mode bit 0 mask. */ -#define TCB_CNTMODE0_bp 0 /* Timer Mode bit 0 position. */ -#define TCB_CNTMODE1_bm (1<<1) /* Timer Mode bit 1 mask. */ -#define TCB_CNTMODE1_bp 1 /* Timer Mode bit 1 position. */ -#define TCB_CNTMODE2_bm (1<<2) /* Timer Mode bit 2 mask. */ -#define TCB_CNTMODE2_bp 2 /* Timer Mode bit 2 position. */ -#define TCB_CCMPEN_bm 0x10 /* Pin Output Enable bit mask. */ -#define TCB_CCMPEN_bp 4 /* Pin Output Enable bit position. */ -#define TCB_CCMPINIT_bm 0x20 /* Pin Initial State bit mask. */ -#define TCB_CCMPINIT_bp 5 /* Pin Initial State bit position. */ -#define TCB_ASYNC_bm 0x40 /* Asynchronous Enable bit mask. */ -#define TCB_ASYNC_bp 6 /* Asynchronous Enable bit position. */ - -/* TCB.EVCTRL bit masks and bit positions */ -#define TCB_CAPTEI_bm 0x01 /* Event Input Enable bit mask. */ -#define TCB_CAPTEI_bp 0 /* Event Input Enable bit position. */ -#define TCB_EDGE_bm 0x10 /* Event Edge bit mask. */ -#define TCB_EDGE_bp 4 /* Event Edge bit position. */ -#define TCB_FILTER_bm 0x40 /* Input Capture Noise Cancellation Filter bit mask. */ -#define TCB_FILTER_bp 6 /* Input Capture Noise Cancellation Filter bit position. */ - -/* TCB.INTCTRL bit masks and bit positions */ -#define TCB_CAPT_bm 0x01 /* Capture or Timeout bit mask. */ -#define TCB_CAPT_bp 0 /* Capture or Timeout bit position. */ - -/* TCB.INTFLAGS bit masks and bit positions */ -/* TCB_CAPT is already defined. */ - -/* TCB.STATUS bit masks and bit positions */ -#define TCB_RUN_bm 0x01 /* Run bit mask. */ -#define TCB_RUN_bp 0 /* Run bit position. */ - -/* TCB.DBGCTRL bit masks and bit positions */ -#define TCB_DBGRUN_bm 0x01 /* Debug Run bit mask. */ -#define TCB_DBGRUN_bp 0 /* Debug Run bit position. */ - - - - -/* TWI - Two-Wire Interface */ -/* TWI.CTRLA bit masks and bit positions */ -#define TWI_FMPEN_bm 0x02 /* FM Plus Enable bit mask. */ -#define TWI_FMPEN_bp 1 /* FM Plus Enable bit position. */ -#define TWI_SDAHOLD_gm 0x0C /* SDA Hold Time group mask. */ -#define TWI_SDAHOLD_gp 2 /* SDA Hold Time group position. */ -#define TWI_SDAHOLD0_bm (1<<2) /* SDA Hold Time bit 0 mask. */ -#define TWI_SDAHOLD0_bp 2 /* SDA Hold Time bit 0 position. */ -#define TWI_SDAHOLD1_bm (1<<3) /* SDA Hold Time bit 1 mask. */ -#define TWI_SDAHOLD1_bp 3 /* SDA Hold Time bit 1 position. */ -#define TWI_SDASETUP_bm 0x10 /* SDA Setup Time bit mask. */ -#define TWI_SDASETUP_bp 4 /* SDA Setup Time bit position. */ - -/* TWI.BRIDGECTRL bit masks and bit positions */ -#define TWI_ENABLE_bm 0x01 /* Bridge Enable bit mask. */ -#define TWI_ENABLE_bp 0 /* Bridge Enable bit position. */ -/* TWI_FMPEN is already defined. */ -/* TWI_SDAHOLD is already defined. */ - -/* TWI.DBGCTRL bit masks and bit positions */ -#define TWI_DBGRUN_bm 0x01 /* Debug Run bit mask. */ -#define TWI_DBGRUN_bp 0 /* Debug Run bit position. */ - -/* TWI.MCTRLA bit masks and bit positions */ -/* TWI_ENABLE is already defined. */ -#define TWI_SMEN_bm 0x02 /* Smart Mode Enable bit mask. */ -#define TWI_SMEN_bp 1 /* Smart Mode Enable bit position. */ -#define TWI_TIMEOUT_gm 0x0C /* Inactive Bus Timeout group mask. */ -#define TWI_TIMEOUT_gp 2 /* Inactive Bus Timeout group position. */ -#define TWI_TIMEOUT0_bm (1<<2) /* Inactive Bus Timeout bit 0 mask. */ -#define TWI_TIMEOUT0_bp 2 /* Inactive Bus Timeout bit 0 position. */ -#define TWI_TIMEOUT1_bm (1<<3) /* Inactive Bus Timeout bit 1 mask. */ -#define TWI_TIMEOUT1_bp 3 /* Inactive Bus Timeout bit 1 position. */ -#define TWI_QCEN_bm 0x10 /* Quick Command Enable bit mask. */ -#define TWI_QCEN_bp 4 /* Quick Command Enable bit position. */ -#define TWI_WIEN_bm 0x40 /* Write Interrupt Enable bit mask. */ -#define TWI_WIEN_bp 6 /* Write Interrupt Enable bit position. */ -#define TWI_RIEN_bm 0x80 /* Read Interrupt Enable bit mask. */ -#define TWI_RIEN_bp 7 /* Read Interrupt Enable bit position. */ - -/* TWI.MCTRLB bit masks and bit positions */ -#define TWI_MCMD_gm 0x03 /* Command group mask. */ -#define TWI_MCMD_gp 0 /* Command group position. */ -#define TWI_MCMD0_bm (1<<0) /* Command bit 0 mask. */ -#define TWI_MCMD0_bp 0 /* Command bit 0 position. */ -#define TWI_MCMD1_bm (1<<1) /* Command bit 1 mask. */ -#define TWI_MCMD1_bp 1 /* Command bit 1 position. */ -#define TWI_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ -#define TWI_ACKACT_bp 2 /* Acknowledge Action bit position. */ -#define TWI_FLUSH_bm 0x08 /* Flush bit mask. */ -#define TWI_FLUSH_bp 3 /* Flush bit position. */ - -/* TWI.MSTATUS bit masks and bit positions */ -#define TWI_BUSSTATE_gm 0x03 /* Bus State group mask. */ -#define TWI_BUSSTATE_gp 0 /* Bus State group position. */ -#define TWI_BUSSTATE0_bm (1<<0) /* Bus State bit 0 mask. */ -#define TWI_BUSSTATE0_bp 0 /* Bus State bit 0 position. */ -#define TWI_BUSSTATE1_bm (1<<1) /* Bus State bit 1 mask. */ -#define TWI_BUSSTATE1_bp 1 /* Bus State bit 1 position. */ -#define TWI_BUSERR_bm 0x04 /* Bus Error bit mask. */ -#define TWI_BUSERR_bp 2 /* Bus Error bit position. */ -#define TWI_ARBLOST_bm 0x08 /* Arbitration Lost bit mask. */ -#define TWI_ARBLOST_bp 3 /* Arbitration Lost bit position. */ -#define TWI_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ -#define TWI_RXACK_bp 4 /* Received Acknowledge bit position. */ -#define TWI_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ -#define TWI_CLKHOLD_bp 5 /* Clock Hold bit position. */ -#define TWI_WIF_bm 0x40 /* Write Interrupt Flag bit mask. */ -#define TWI_WIF_bp 6 /* Write Interrupt Flag bit position. */ -#define TWI_RIF_bm 0x80 /* Read Interrupt Flag bit mask. */ -#define TWI_RIF_bp 7 /* Read Interrupt Flag bit position. */ - - - - -/* TWI.SCTRLA bit masks and bit positions */ -/* TWI_ENABLE is already defined. */ -/* TWI_SMEN is already defined. */ -#define TWI_PMEN_bm 0x04 /* Promiscuous Mode Enable bit mask. */ -#define TWI_PMEN_bp 2 /* Promiscuous Mode Enable bit position. */ -#define TWI_PIEN_bm 0x20 /* Stop Interrupt Enable bit mask. */ -#define TWI_PIEN_bp 5 /* Stop Interrupt Enable bit position. */ -#define TWI_APIEN_bm 0x40 /* Address/Stop Interrupt Enable bit mask. */ -#define TWI_APIEN_bp 6 /* Address/Stop Interrupt Enable bit position. */ -#define TWI_DIEN_bm 0x80 /* Data Interrupt Enable bit mask. */ -#define TWI_DIEN_bp 7 /* Data Interrupt Enable bit position. */ - -/* TWI.SCTRLB bit masks and bit positions */ -#define TWI_SCMD_gm 0x03 /* Command group mask. */ -#define TWI_SCMD_gp 0 /* Command group position. */ -#define TWI_SCMD0_bm (1<<0) /* Command bit 0 mask. */ -#define TWI_SCMD0_bp 0 /* Command bit 0 position. */ -#define TWI_SCMD1_bm (1<<1) /* Command bit 1 mask. */ -#define TWI_SCMD1_bp 1 /* Command bit 1 position. */ -/* TWI_ACKACT is already defined. */ - -/* TWI.SSTATUS bit masks and bit positions */ -#define TWI_AP_bm 0x01 /* Slave Address or Stop bit mask. */ -#define TWI_AP_bp 0 /* Slave Address or Stop bit position. */ -#define TWI_DIR_bm 0x02 /* Read/Write Direction bit mask. */ -#define TWI_DIR_bp 1 /* Read/Write Direction bit position. */ -/* TWI_BUSERR is already defined. */ -#define TWI_COLL_bm 0x08 /* Collision bit mask. */ -#define TWI_COLL_bp 3 /* Collision bit position. */ -/* TWI_RXACK is already defined. */ -/* TWI_CLKHOLD is already defined. */ -#define TWI_APIF_bm 0x40 /* Address/Stop Interrupt Flag bit mask. */ -#define TWI_APIF_bp 6 /* Address/Stop Interrupt Flag bit position. */ -#define TWI_DIF_bm 0x80 /* Data Interrupt Flag bit mask. */ -#define TWI_DIF_bp 7 /* Data Interrupt Flag bit position. */ - - - -/* TWI.SADDRMASK bit masks and bit positions */ -#define TWI_ADDREN_bm 0x01 /* Address Enable bit mask. */ -#define TWI_ADDREN_bp 0 /* Address Enable bit position. */ -#define TWI_ADDRMASK_gm 0xFE /* Address Mask group mask. */ -#define TWI_ADDRMASK_gp 1 /* Address Mask group position. */ -#define TWI_ADDRMASK0_bm (1<<1) /* Address Mask bit 0 mask. */ -#define TWI_ADDRMASK0_bp 1 /* Address Mask bit 0 position. */ -#define TWI_ADDRMASK1_bm (1<<2) /* Address Mask bit 1 mask. */ -#define TWI_ADDRMASK1_bp 2 /* Address Mask bit 1 position. */ -#define TWI_ADDRMASK2_bm (1<<3) /* Address Mask bit 2 mask. */ -#define TWI_ADDRMASK2_bp 3 /* Address Mask bit 2 position. */ -#define TWI_ADDRMASK3_bm (1<<4) /* Address Mask bit 3 mask. */ -#define TWI_ADDRMASK3_bp 4 /* Address Mask bit 3 position. */ -#define TWI_ADDRMASK4_bm (1<<5) /* Address Mask bit 4 mask. */ -#define TWI_ADDRMASK4_bp 5 /* Address Mask bit 4 position. */ -#define TWI_ADDRMASK5_bm (1<<6) /* Address Mask bit 5 mask. */ -#define TWI_ADDRMASK5_bp 6 /* Address Mask bit 5 position. */ -#define TWI_ADDRMASK6_bm (1<<7) /* Address Mask bit 6 mask. */ -#define TWI_ADDRMASK6_bp 7 /* Address Mask bit 6 position. */ - -/* USART - Universal Synchronous and Asynchronous Receiver and Transmitter */ -/* USART.RXDATAL bit masks and bit positions */ -#define USART_DATA_gm 0xFF /* RX Data group mask. */ -#define USART_DATA_gp 0 /* RX Data group position. */ -#define USART_DATA0_bm (1<<0) /* RX Data bit 0 mask. */ -#define USART_DATA0_bp 0 /* RX Data bit 0 position. */ -#define USART_DATA1_bm (1<<1) /* RX Data bit 1 mask. */ -#define USART_DATA1_bp 1 /* RX Data bit 1 position. */ -#define USART_DATA2_bm (1<<2) /* RX Data bit 2 mask. */ -#define USART_DATA2_bp 2 /* RX Data bit 2 position. */ -#define USART_DATA3_bm (1<<3) /* RX Data bit 3 mask. */ -#define USART_DATA3_bp 3 /* RX Data bit 3 position. */ -#define USART_DATA4_bm (1<<4) /* RX Data bit 4 mask. */ -#define USART_DATA4_bp 4 /* RX Data bit 4 position. */ -#define USART_DATA5_bm (1<<5) /* RX Data bit 5 mask. */ -#define USART_DATA5_bp 5 /* RX Data bit 5 position. */ -#define USART_DATA6_bm (1<<6) /* RX Data bit 6 mask. */ -#define USART_DATA6_bp 6 /* RX Data bit 6 position. */ -#define USART_DATA7_bm (1<<7) /* RX Data bit 7 mask. */ -#define USART_DATA7_bp 7 /* RX Data bit 7 position. */ - -/* USART.RXDATAH bit masks and bit positions */ -#define USART_DATA8_bm 0x01 /* Receiver Data Register bit mask. */ -#define USART_DATA8_bp 0 /* Receiver Data Register bit position. */ -#define USART_PERR_bm 0x02 /* Parity Error bit mask. */ -#define USART_PERR_bp 1 /* Parity Error bit position. */ -#define USART_FERR_bm 0x04 /* Frame Error bit mask. */ -#define USART_FERR_bp 2 /* Frame Error bit position. */ -#define USART_BUFOVF_bm 0x40 /* Buffer Overflow bit mask. */ -#define USART_BUFOVF_bp 6 /* Buffer Overflow bit position. */ -#define USART_RXCIF_bm 0x80 /* Receive Complete Interrupt Flag bit mask. */ -#define USART_RXCIF_bp 7 /* Receive Complete Interrupt Flag bit position. */ - -/* USART.TXDATAL bit masks and bit positions */ -/* USART_DATA is already defined. */ - -/* USART.TXDATAH bit masks and bit positions */ -/* USART_DATA8 is already defined. */ - -/* USART.STATUS bit masks and bit positions */ -#define USART_WFB_bm 0x01 /* Wait For Break bit mask. */ -#define USART_WFB_bp 0 /* Wait For Break bit position. */ -#define USART_BDF_bm 0x02 /* Break Detected Flag bit mask. */ -#define USART_BDF_bp 1 /* Break Detected Flag bit position. */ -#define USART_ISFIF_bm 0x08 /* Inconsistent Sync Field Interrupt Flag bit mask. */ -#define USART_ISFIF_bp 3 /* Inconsistent Sync Field Interrupt Flag bit position. */ -#define USART_RXSIF_bm 0x10 /* Receive Start Interrupt bit mask. */ -#define USART_RXSIF_bp 4 /* Receive Start Interrupt bit position. */ -#define USART_DREIF_bm 0x20 /* Data Register Empty Flag bit mask. */ -#define USART_DREIF_bp 5 /* Data Register Empty Flag bit position. */ -#define USART_TXCIF_bm 0x40 /* Transmit Interrupt Flag bit mask. */ -#define USART_TXCIF_bp 6 /* Transmit Interrupt Flag bit position. */ -/* USART_RXCIF is already defined. */ - -/* USART.CTRLA bit masks and bit positions */ -#define USART_RS485_gm 0x03 /* RS485 Mode internal transmitter group mask. */ -#define USART_RS485_gp 0 /* RS485 Mode internal transmitter group position. */ -#define USART_RS4850_bm (1<<0) /* RS485 Mode internal transmitter bit 0 mask. */ -#define USART_RS4850_bp 0 /* RS485 Mode internal transmitter bit 0 position. */ -#define USART_RS4851_bm (1<<1) /* RS485 Mode internal transmitter bit 1 mask. */ -#define USART_RS4851_bp 1 /* RS485 Mode internal transmitter bit 1 position. */ -#define USART_ABEIE_bm 0x04 /* Auto-baud Error Interrupt Enable bit mask. */ -#define USART_ABEIE_bp 2 /* Auto-baud Error Interrupt Enable bit position. */ -#define USART_LBME_bm 0x08 /* Loop-back Mode Enable bit mask. */ -#define USART_LBME_bp 3 /* Loop-back Mode Enable bit position. */ -#define USART_RXSIE_bm 0x10 /* Receiver Start Frame Interrupt Enable bit mask. */ -#define USART_RXSIE_bp 4 /* Receiver Start Frame Interrupt Enable bit position. */ -#define USART_DREIE_bm 0x20 /* Data Register Empty Interrupt Enable bit mask. */ -#define USART_DREIE_bp 5 /* Data Register Empty Interrupt Enable bit position. */ -#define USART_TXCIE_bm 0x40 /* Transmit Complete Interrupt Enable bit mask. */ -#define USART_TXCIE_bp 6 /* Transmit Complete Interrupt Enable bit position. */ -#define USART_RXCIE_bm 0x80 /* Receive Complete Interrupt Enable bit mask. */ -#define USART_RXCIE_bp 7 /* Receive Complete Interrupt Enable bit position. */ - -/* USART.CTRLB bit masks and bit positions */ -#define USART_MPCM_bm 0x01 /* Multi-processor Communication Mode bit mask. */ -#define USART_MPCM_bp 0 /* Multi-processor Communication Mode bit position. */ -#define USART_RXMODE_gm 0x06 /* Receiver Mode group mask. */ -#define USART_RXMODE_gp 1 /* Receiver Mode group position. */ -#define USART_RXMODE0_bm (1<<1) /* Receiver Mode bit 0 mask. */ -#define USART_RXMODE0_bp 1 /* Receiver Mode bit 0 position. */ -#define USART_RXMODE1_bm (1<<2) /* Receiver Mode bit 1 mask. */ -#define USART_RXMODE1_bp 2 /* Receiver Mode bit 1 position. */ -#define USART_ODME_bm 0x08 /* Open Drain Mode Enable bit mask. */ -#define USART_ODME_bp 3 /* Open Drain Mode Enable bit position. */ -#define USART_SFDEN_bm 0x10 /* Start Frame Detection Enable bit mask. */ -#define USART_SFDEN_bp 4 /* Start Frame Detection Enable bit position. */ -#define USART_TXEN_bm 0x40 /* Transmitter Enable bit mask. */ -#define USART_TXEN_bp 6 /* Transmitter Enable bit position. */ -#define USART_RXEN_bm 0x80 /* Reciever enable bit mask. */ -#define USART_RXEN_bp 7 /* Reciever enable bit position. */ - -/* USART.CTRLC bit masks and bit positions */ -#define USART_UCPHA_bm 0x02 /* SPI Master Mode, Clock Phase bit mask. */ -#define USART_UCPHA_bp 1 /* SPI Master Mode, Clock Phase bit position. */ -#define USART_UDORD_bm 0x04 /* SPI Master Mode, Data Order bit mask. */ -#define USART_UDORD_bp 2 /* SPI Master Mode, Data Order bit position. */ -#define USART_CHSIZE_gm 0x07 /* Character Size group mask. */ -#define USART_CHSIZE_gp 0 /* Character Size group position. */ -#define USART_CHSIZE0_bm (1<<0) /* Character Size bit 0 mask. */ -#define USART_CHSIZE0_bp 0 /* Character Size bit 0 position. */ -#define USART_CHSIZE1_bm (1<<1) /* Character Size bit 1 mask. */ -#define USART_CHSIZE1_bp 1 /* Character Size bit 1 position. */ -#define USART_CHSIZE2_bm (1<<2) /* Character Size bit 2 mask. */ -#define USART_CHSIZE2_bp 2 /* Character Size bit 2 position. */ -#define USART_SBMODE_bm 0x08 /* Stop Bit Mode bit mask. */ -#define USART_SBMODE_bp 3 /* Stop Bit Mode bit position. */ -#define USART_PMODE_gm 0x30 /* Parity Mode group mask. */ -#define USART_PMODE_gp 4 /* Parity Mode group position. */ -#define USART_PMODE0_bm (1<<4) /* Parity Mode bit 0 mask. */ -#define USART_PMODE0_bp 4 /* Parity Mode bit 0 position. */ -#define USART_PMODE1_bm (1<<5) /* Parity Mode bit 1 mask. */ -#define USART_PMODE1_bp 5 /* Parity Mode bit 1 position. */ -#define USART_CMODE_gm 0xC0 /* Communication Mode group mask. */ -#define USART_CMODE_gp 6 /* Communication Mode group position. */ -#define USART_CMODE0_bm (1<<6) /* Communication Mode bit 0 mask. */ -#define USART_CMODE0_bp 6 /* Communication Mode bit 0 position. */ -#define USART_CMODE1_bm (1<<7) /* Communication Mode bit 1 mask. */ -#define USART_CMODE1_bp 7 /* Communication Mode bit 1 position. */ - - - -/* USART.DBGCTRL bit masks and bit positions */ -#define USART_DBGRUN_bm 0x01 /* Debug Run bit mask. */ -#define USART_DBGRUN_bp 0 /* Debug Run bit position. */ -#define USART_ABMBP_bm 0x80 /* Autobaud majority voter bypass bit mask. */ -#define USART_ABMBP_bp 7 /* Autobaud majority voter bypass bit position. */ - -/* USART.EVCTRL bit masks and bit positions */ -#define USART_IREI_bm 0x01 /* IrDA Event Input Enable bit mask. */ -#define USART_IREI_bp 0 /* IrDA Event Input Enable bit position. */ - -/* USART.TXPLCTRL bit masks and bit positions */ -#define USART_TXPL_gm 0xFF /* Transmit pulse length group mask. */ -#define USART_TXPL_gp 0 /* Transmit pulse length group position. */ -#define USART_TXPL0_bm (1<<0) /* Transmit pulse length bit 0 mask. */ -#define USART_TXPL0_bp 0 /* Transmit pulse length bit 0 position. */ -#define USART_TXPL1_bm (1<<1) /* Transmit pulse length bit 1 mask. */ -#define USART_TXPL1_bp 1 /* Transmit pulse length bit 1 position. */ -#define USART_TXPL2_bm (1<<2) /* Transmit pulse length bit 2 mask. */ -#define USART_TXPL2_bp 2 /* Transmit pulse length bit 2 position. */ -#define USART_TXPL3_bm (1<<3) /* Transmit pulse length bit 3 mask. */ -#define USART_TXPL3_bp 3 /* Transmit pulse length bit 3 position. */ -#define USART_TXPL4_bm (1<<4) /* Transmit pulse length bit 4 mask. */ -#define USART_TXPL4_bp 4 /* Transmit pulse length bit 4 position. */ -#define USART_TXPL5_bm (1<<5) /* Transmit pulse length bit 5 mask. */ -#define USART_TXPL5_bp 5 /* Transmit pulse length bit 5 position. */ -#define USART_TXPL6_bm (1<<6) /* Transmit pulse length bit 6 mask. */ -#define USART_TXPL6_bp 6 /* Transmit pulse length bit 6 position. */ -#define USART_TXPL7_bm (1<<7) /* Transmit pulse length bit 7 mask. */ -#define USART_TXPL7_bp 7 /* Transmit pulse length bit 7 position. */ - -/* USART.RXPLCTRL bit masks and bit positions */ -#define USART_RXPL_gm 0x7F /* Receiver Pulse Lenght group mask. */ -#define USART_RXPL_gp 0 /* Receiver Pulse Lenght group position. */ -#define USART_RXPL0_bm (1<<0) /* Receiver Pulse Lenght bit 0 mask. */ -#define USART_RXPL0_bp 0 /* Receiver Pulse Lenght bit 0 position. */ -#define USART_RXPL1_bm (1<<1) /* Receiver Pulse Lenght bit 1 mask. */ -#define USART_RXPL1_bp 1 /* Receiver Pulse Lenght bit 1 position. */ -#define USART_RXPL2_bm (1<<2) /* Receiver Pulse Lenght bit 2 mask. */ -#define USART_RXPL2_bp 2 /* Receiver Pulse Lenght bit 2 position. */ -#define USART_RXPL3_bm (1<<3) /* Receiver Pulse Lenght bit 3 mask. */ -#define USART_RXPL3_bp 3 /* Receiver Pulse Lenght bit 3 position. */ -#define USART_RXPL4_bm (1<<4) /* Receiver Pulse Lenght bit 4 mask. */ -#define USART_RXPL4_bp 4 /* Receiver Pulse Lenght bit 4 position. */ -#define USART_RXPL5_bm (1<<5) /* Receiver Pulse Lenght bit 5 mask. */ -#define USART_RXPL5_bp 5 /* Receiver Pulse Lenght bit 5 position. */ -#define USART_RXPL6_bm (1<<6) /* Receiver Pulse Lenght bit 6 mask. */ -#define USART_RXPL6_bp 6 /* Receiver Pulse Lenght bit 6 position. */ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -/* VPORT - Virtual Ports */ -/* VPORT.INTFLAGS bit masks and bit positions */ -#define VPORT_INT_gm 0xFF /* Pin Interrupt group mask. */ -#define VPORT_INT_gp 0 /* Pin Interrupt group position. */ -#define VPORT_INT0_bm (1<<0) /* Pin Interrupt bit 0 mask. */ -#define VPORT_INT0_bp 0 /* Pin Interrupt bit 0 position. */ -#define VPORT_INT1_bm (1<<1) /* Pin Interrupt bit 1 mask. */ -#define VPORT_INT1_bp 1 /* Pin Interrupt bit 1 position. */ -#define VPORT_INT2_bm (1<<2) /* Pin Interrupt bit 2 mask. */ -#define VPORT_INT2_bp 2 /* Pin Interrupt bit 2 position. */ -#define VPORT_INT3_bm (1<<3) /* Pin Interrupt bit 3 mask. */ -#define VPORT_INT3_bp 3 /* Pin Interrupt bit 3 position. */ -#define VPORT_INT4_bm (1<<4) /* Pin Interrupt bit 4 mask. */ -#define VPORT_INT4_bp 4 /* Pin Interrupt bit 4 position. */ -#define VPORT_INT5_bm (1<<5) /* Pin Interrupt bit 5 mask. */ -#define VPORT_INT5_bp 5 /* Pin Interrupt bit 5 position. */ -#define VPORT_INT6_bm (1<<6) /* Pin Interrupt bit 6 mask. */ -#define VPORT_INT6_bp 6 /* Pin Interrupt bit 6 position. */ -#define VPORT_INT7_bm (1<<7) /* Pin Interrupt bit 7 mask. */ -#define VPORT_INT7_bp 7 /* Pin Interrupt bit 7 position. */ - -/* VREF - Voltage reference */ -/* VREF.CTRLA bit masks and bit positions */ -#define VREF_AC0REFSEL_gm 0x07 /* AC0 reference select group mask. */ -#define VREF_AC0REFSEL_gp 0 /* AC0 reference select group position. */ -#define VREF_AC0REFSEL0_bm (1<<0) /* AC0 reference select bit 0 mask. */ -#define VREF_AC0REFSEL0_bp 0 /* AC0 reference select bit 0 position. */ -#define VREF_AC0REFSEL1_bm (1<<1) /* AC0 reference select bit 1 mask. */ -#define VREF_AC0REFSEL1_bp 1 /* AC0 reference select bit 1 position. */ -#define VREF_AC0REFSEL2_bm (1<<2) /* AC0 reference select bit 2 mask. */ -#define VREF_AC0REFSEL2_bp 2 /* AC0 reference select bit 2 position. */ -#define VREF_ADC0REFSEL_gm 0x70 /* ADC0 reference select group mask. */ -#define VREF_ADC0REFSEL_gp 4 /* ADC0 reference select group position. */ -#define VREF_ADC0REFSEL0_bm (1<<4) /* ADC0 reference select bit 0 mask. */ -#define VREF_ADC0REFSEL0_bp 4 /* ADC0 reference select bit 0 position. */ -#define VREF_ADC0REFSEL1_bm (1<<5) /* ADC0 reference select bit 1 mask. */ -#define VREF_ADC0REFSEL1_bp 5 /* ADC0 reference select bit 1 position. */ -#define VREF_ADC0REFSEL2_bm (1<<6) /* ADC0 reference select bit 2 mask. */ -#define VREF_ADC0REFSEL2_bp 6 /* ADC0 reference select bit 2 position. */ - -/* VREF.CTRLB bit masks and bit positions */ -#define VREF_AC0REFEN_bm 0x01 /* AC0 DACREF reference enable bit mask. */ -#define VREF_AC0REFEN_bp 0 /* AC0 DACREF reference enable bit position. */ -#define VREF_ADC0REFEN_bm 0x02 /* ADC0 reference enable bit mask. */ -#define VREF_ADC0REFEN_bp 1 /* ADC0 reference enable bit position. */ -#define VREF_NVMREFEN_bm 0x04 /* NVM reference enable bit mask. */ -#define VREF_NVMREFEN_bp 2 /* NVM reference enable bit position. */ - -/* WDT - Watch-Dog Timer */ -/* WDT.CTRLA bit masks and bit positions */ -#define WDT_PERIOD_gm 0x0F /* Period group mask. */ -#define WDT_PERIOD_gp 0 /* Period group position. */ -#define WDT_PERIOD0_bm (1<<0) /* Period bit 0 mask. */ -#define WDT_PERIOD0_bp 0 /* Period bit 0 position. */ -#define WDT_PERIOD1_bm (1<<1) /* Period bit 1 mask. */ -#define WDT_PERIOD1_bp 1 /* Period bit 1 position. */ -#define WDT_PERIOD2_bm (1<<2) /* Period bit 2 mask. */ -#define WDT_PERIOD2_bp 2 /* Period bit 2 position. */ -#define WDT_PERIOD3_bm (1<<3) /* Period bit 3 mask. */ -#define WDT_PERIOD3_bp 3 /* Period bit 3 position. */ -#define WDT_WINDOW_gm 0xF0 /* Window group mask. */ -#define WDT_WINDOW_gp 4 /* Window group position. */ -#define WDT_WINDOW0_bm (1<<4) /* Window bit 0 mask. */ -#define WDT_WINDOW0_bp 4 /* Window bit 0 position. */ -#define WDT_WINDOW1_bm (1<<5) /* Window bit 1 mask. */ -#define WDT_WINDOW1_bp 5 /* Window bit 1 position. */ -#define WDT_WINDOW2_bm (1<<6) /* Window bit 2 mask. */ -#define WDT_WINDOW2_bp 6 /* Window bit 2 position. */ -#define WDT_WINDOW3_bm (1<<7) /* Window bit 3 mask. */ -#define WDT_WINDOW3_bp 7 /* Window bit 3 position. */ - -/* WDT.STATUS bit masks and bit positions */ -#define WDT_SYNCBUSY_bm 0x01 /* Syncronization busy bit mask. */ -#define WDT_SYNCBUSY_bp 0 /* Syncronization busy bit position. */ -#define WDT_LOCK_bm 0x80 /* Lock enable bit mask. */ -#define WDT_LOCK_bp 7 /* Lock enable bit position. */ - - - -// Generic Port Pins - -#define PIN0_bm 0x01 -#define PIN0_bp 0 -#define PIN1_bm 0x02 -#define PIN1_bp 1 -#define PIN2_bm 0x04 -#define PIN2_bp 2 -#define PIN3_bm 0x08 -#define PIN3_bp 3 -#define PIN4_bm 0x10 -#define PIN4_bp 4 -#define PIN5_bm 0x20 -#define PIN5_bp 5 -#define PIN6_bm 0x40 -#define PIN6_bp 6 -#define PIN7_bm 0x80 -#define PIN7_bp 7 - -/* ========== Interrupt Vector Definitions ========== */ -/* Vector 0 is the reset vector */ - -/* CRCSCAN interrupt vectors */ -#define CRCSCAN_NMI_vect_num 1 -#define CRCSCAN_NMI_vect _VECTOR(1) /* */ - -/* BOD interrupt vectors */ -#define BOD_VLM_vect_num 2 -#define BOD_VLM_vect _VECTOR(2) /* */ - -/* RTC interrupt vectors */ -#define RTC_CNT_vect_num 3 -#define RTC_CNT_vect _VECTOR(3) /* */ -#define RTC_PIT_vect_num 4 -#define RTC_PIT_vect _VECTOR(4) /* */ - -/* CCL interrupt vectors */ -#define CCL_CCL_vect_num 5 -#define CCL_CCL_vect _VECTOR(5) /* */ - -/* PORTA interrupt vectors */ -#define PORTA_PORT_vect_num 6 -#define PORTA_PORT_vect _VECTOR(6) /* */ - -/* TCA0 interrupt vectors */ -#define TCA0_OVF_vect_num 7 -#define TCA0_OVF_vect _VECTOR(7) /* */ -#define TCA0_LUNF_vect_num 7 -#define TCA0_LUNF_vect _VECTOR(7) /* */ -#define TCA0_HUNF_vect_num 8 -#define TCA0_HUNF_vect _VECTOR(8) /* */ -#define TCA0_LCMP0_vect_num 9 -#define TCA0_LCMP0_vect _VECTOR(9) /* */ -#define TCA0_CMP0_vect_num 9 -#define TCA0_CMP0_vect _VECTOR(9) /* */ -#define TCA0_LCMP1_vect_num 10 -#define TCA0_LCMP1_vect _VECTOR(10) /* */ -#define TCA0_CMP1_vect_num 10 -#define TCA0_CMP1_vect _VECTOR(10) /* */ -#define TCA0_CMP2_vect_num 11 -#define TCA0_CMP2_vect _VECTOR(11) /* */ -#define TCA0_LCMP2_vect_num 11 -#define TCA0_LCMP2_vect _VECTOR(11) /* */ - -/* TCB0 interrupt vectors */ -#define TCB0_INT_vect_num 12 -#define TCB0_INT_vect _VECTOR(12) /* */ - -/* TCB1 interrupt vectors */ -#define TCB1_INT_vect_num 13 -#define TCB1_INT_vect _VECTOR(13) /* */ - -/* TWI0 interrupt vectors */ -#define TWI0_TWIS_vect_num 14 -#define TWI0_TWIS_vect _VECTOR(14) /* */ -#define TWI0_TWIM_vect_num 15 -#define TWI0_TWIM_vect _VECTOR(15) /* */ - -/* SPI0 interrupt vectors */ -#define SPI0_INT_vect_num 16 -#define SPI0_INT_vect _VECTOR(16) /* */ - -/* USART0 interrupt vectors */ -#define USART0_RXC_vect_num 17 -#define USART0_RXC_vect _VECTOR(17) /* */ -#define USART0_DRE_vect_num 18 -#define USART0_DRE_vect _VECTOR(18) /* */ -#define USART0_TXC_vect_num 19 -#define USART0_TXC_vect _VECTOR(19) /* */ - -/* PORTD interrupt vectors */ -#define PORTD_PORT_vect_num 20 -#define PORTD_PORT_vect _VECTOR(20) /* */ - -/* AC0 interrupt vectors */ -#define AC0_AC_vect_num 21 -#define AC0_AC_vect _VECTOR(21) /* */ - -/* ADC0 interrupt vectors */ -#define ADC0_RESRDY_vect_num 22 -#define ADC0_RESRDY_vect _VECTOR(22) /* */ -#define ADC0_WCOMP_vect_num 23 -#define ADC0_WCOMP_vect _VECTOR(23) /* */ - -/* PORTC interrupt vectors */ -#define PORTC_PORT_vect_num 24 -#define PORTC_PORT_vect _VECTOR(24) /* */ - -/* TCB2 interrupt vectors */ -#define TCB2_INT_vect_num 25 -#define TCB2_INT_vect _VECTOR(25) /* */ - -/* USART1 interrupt vectors */ -#define USART1_RXC_vect_num 26 -#define USART1_RXC_vect _VECTOR(26) /* */ -#define USART1_DRE_vect_num 27 -#define USART1_DRE_vect _VECTOR(27) /* */ -#define USART1_TXC_vect_num 28 -#define USART1_TXC_vect _VECTOR(28) /* */ - -/* PORTF interrupt vectors */ -#define PORTF_PORT_vect_num 29 -#define PORTF_PORT_vect _VECTOR(29) /* */ - -/* NVMCTRL interrupt vectors */ -#define NVMCTRL_EE_vect_num 30 -#define NVMCTRL_EE_vect _VECTOR(30) /* */ - -/* USART2 interrupt vectors */ -#define USART2_RXC_vect_num 31 -#define USART2_RXC_vect _VECTOR(31) /* */ -#define USART2_DRE_vect_num 32 -#define USART2_DRE_vect _VECTOR(32) /* */ -#define USART2_TXC_vect_num 33 -#define USART2_TXC_vect _VECTOR(33) /* */ - -/* PORTB interrupt vectors */ -#define PORTB_PORT_vect_num 34 -#define PORTB_PORT_vect _VECTOR(34) /* */ - -/* PORTE interrupt vectors */ -#define PORTE_PORT_vect_num 35 -#define PORTE_PORT_vect _VECTOR(35) /* */ - -#define _VECTOR_SIZE 4 /* Size of individual vector. */ -#define _VECTORS_SIZE (36 * _VECTOR_SIZE) - - -/* ========== Constants ========== */ - -#define DATAMEM_START (0x0000) -#define DATAMEM_SIZE (49152) -#define DATAMEM_END (DATAMEM_START + DATAMEM_SIZE - 1) - -#define EEPROM_START (0x1400) -#define EEPROM_SIZE (256) -#define EEPROM_PAGE_SIZE (64) -#define EEPROM_END (EEPROM_START + EEPROM_SIZE - 1) - -/* Added MAPPED_EEPROM segment names for avr-libc */ -#define MAPPED_EEPROM_START (EEPROM_START) -#define MAPPED_EEPROM_SIZE (EEPROM_SIZE) -#define MAPPED_EEPROM_PAGE_SIZE (EEPROM_PAGE_SIZE) -#define MAPPED_EEPROM_END (MAPPED_EEPROM_START + MAPPED_EEPROM_SIZE - 1) - -#define FUSES_START (0x1280) -#define FUSES_SIZE (10) -#define FUSES_PAGE_SIZE (64) -#define FUSES_END (FUSES_START + FUSES_SIZE - 1) - -#define INTERNAL_SRAM_START (0x2800) -#define INTERNAL_SRAM_SIZE (6144) -#define INTERNAL_SRAM_PAGE_SIZE (0) -#define INTERNAL_SRAM_END (INTERNAL_SRAM_START + INTERNAL_SRAM_SIZE - 1) - -#define IO_START (0x0000) -#define IO_SIZE (4352) -#define IO_PAGE_SIZE (0) -#define IO_END (IO_START + IO_SIZE - 1) - -#define LOCKBITS_START (0x128A) -#define LOCKBITS_SIZE (1) -#define LOCKBITS_PAGE_SIZE (64) -#define LOCKBITS_END (LOCKBITS_START + LOCKBITS_SIZE - 1) - -#define MAPPED_PROGMEM_START (0x4000) -#define MAPPED_PROGMEM_SIZE (49152) -#define MAPPED_PROGMEM_PAGE_SIZE (128) -#define MAPPED_PROGMEM_END (MAPPED_PROGMEM_START + MAPPED_PROGMEM_SIZE - 1) - -#define PROD_SIGNATURES_START (0x1103) -#define PROD_SIGNATURES_SIZE (125) -#define PROD_SIGNATURES_PAGE_SIZE (128) -#define PROD_SIGNATURES_END (PROD_SIGNATURES_START + PROD_SIGNATURES_SIZE - 1) - -#define SIGNATURES_START (0x1100) -#define SIGNATURES_SIZE (3) -#define SIGNATURES_PAGE_SIZE (128) -#define SIGNATURES_END (SIGNATURES_START + SIGNATURES_SIZE - 1) - -#define USER_SIGNATURES_START (0x1300) -#define USER_SIGNATURES_SIZE (64) -#define USER_SIGNATURES_PAGE_SIZE (64) -#define USER_SIGNATURES_END (USER_SIGNATURES_START + USER_SIGNATURES_SIZE - 1) - -#define PROGMEM_START (0x0000) -#define PROGMEM_SIZE (49152) -#define PROGMEM_END (PROGMEM_START + PROGMEM_SIZE - 1) - -#define PROGMEM_START (0x0000) -#define PROGMEM_SIZE (49152) -#define PROGMEM_PAGE_SIZE (128) -#define PROGMEM_END (PROGMEM_START + PROGMEM_SIZE - 1) - -#define FLASHSTART PROGMEM_START -#define FLASHEND PROGMEM_END -#define RAMSTART INTERNAL_SRAM_START -#define RAMSIZE INTERNAL_SRAM_SIZE -#define RAMEND INTERNAL_SRAM_END -#define E2END EEPROM_END -#define E2PAGESIZE EEPROM_PAGE_SIZE - - -/* ========== Fuses ========== */ -#define FUSE_MEMORY_SIZE 9 - -/* Fuse Byte 0 Reserved */ - -/* Fuse Byte 1 Reserved */ - -/* Fuse Byte 2 Reserved */ - -/* Fuse Byte 3 Reserved */ - -/* Fuse Byte 4 Reserved */ - -/* Fuse Byte 5 Reserved */ - -/* Fuse Byte 6 Reserved */ - -/* Fuse Byte 7 */ - -/* Fuse Byte 8 */ -#define FUSE_SLEEP0 (unsigned char)~_BV(0) /* BOD Operation in Sleep Mode Bit 0 */ -#define FUSE_SLEEP1 (unsigned char)~_BV(1) /* BOD Operation in Sleep Mode Bit 1 */ -#define FUSE_ACTIVE0 (unsigned char)~_BV(2) /* BOD Operation in Active Mode Bit 0 */ -#define FUSE_ACTIVE1 (unsigned char)~_BV(3) /* BOD Operation in Active Mode Bit 1 */ -#define FUSE_SAMPFREQ (unsigned char)~_BV(4) /* BOD Sample Frequency */ -#define FUSE_LVL0 (unsigned char)~_BV(5) /* BOD Level Bit 0 */ -#define FUSE_LVL1 (unsigned char)~_BV(6) /* BOD Level Bit 1 */ -#define FUSE_LVL2 (unsigned char)~_BV(7) /* BOD Level Bit 2 */ - -/* Fuse Byte 9 */ - -/* Fuse Byte 10 */ -#define FUSE_FREQSEL0 (unsigned char)~_BV(0) /* Frequency Select Bit 0 */ -#define FUSE_FREQSEL1 (unsigned char)~_BV(1) /* Frequency Select Bit 1 */ -#define FUSE_OSCLOCK (unsigned char)~_BV(7) /* Oscillator Lock */ - -/* Fuse Byte 11 */ -#define FUSE_EESAVE (unsigned char)~_BV(0) /* EEPROM Save */ -#define FUSE_RSTPINCFG0 (unsigned char)~_BV(2) /* Reset Pin Configuration Bit 0 */ -#define FUSE_RSTPINCFG1 (unsigned char)~_BV(3) /* Reset Pin Configuration Bit 1 */ -#define FUSE_CRCSRC0 (unsigned char)~_BV(6) /* CRC Source Bit 0 */ -#define FUSE_CRCSRC1 (unsigned char)~_BV(7) /* CRC Source Bit 1 */ - -/* Fuse Byte 12 */ -#define FUSE_SUT0 (unsigned char)~_BV(0) /* Startup Time Bit 0 */ -#define FUSE_SUT1 (unsigned char)~_BV(1) /* Startup Time Bit 1 */ -#define FUSE_SUT2 (unsigned char)~_BV(2) /* Startup Time Bit 2 */ - -/* Fuse Byte 13 */ -#define FUSE_CMPA (unsigned char)~_BV(0) /* Compare A Default Output Value */ -#define FUSE_CMPB (unsigned char)~_BV(1) /* Compare B Default Output Value */ -#define FUSE_CMPC (unsigned char)~_BV(2) /* Compare C Default Output Value */ -#define FUSE_CMPD (unsigned char)~_BV(3) /* Compare D Default Output Value */ -#define FUSE_CMPAEN (unsigned char)~_BV(4) /* Compare A Output Enable */ -#define FUSE_CMPBEN (unsigned char)~_BV(5) /* Compare B Output Enable */ -#define FUSE_CMPCEN (unsigned char)~_BV(6) /* Compare C Output Enable */ -#define FUSE_CMPDEN (unsigned char)~_BV(7) /* Compare D Output Enable */ - -/* Fuse Byte 14 */ -#define FUSE_PERIOD0 (unsigned char)~_BV(0) /* Watchdog Timeout Period Bit 0 */ -#define FUSE_PERIOD1 (unsigned char)~_BV(1) /* Watchdog Timeout Period Bit 1 */ -#define FUSE_PERIOD2 (unsigned char)~_BV(2) /* Watchdog Timeout Period Bit 2 */ -#define FUSE_PERIOD3 (unsigned char)~_BV(3) /* Watchdog Timeout Period Bit 3 */ -#define FUSE_WINDOW0 (unsigned char)~_BV(4) /* Watchdog Window Timeout Period Bit 0 */ -#define FUSE_WINDOW1 (unsigned char)~_BV(5) /* Watchdog Window Timeout Period Bit 1 */ -#define FUSE_WINDOW2 (unsigned char)~_BV(6) /* Watchdog Window Timeout Period Bit 2 */ -#define FUSE_WINDOW3 (unsigned char)~_BV(7) /* Watchdog Window Timeout Period Bit 3 */ - -/* ========== Lock Bits ========== */ -#define __LOCK_BITS_EXIST - -/* ========== Signature ========== */ -#define SIGNATURE_0 0x1E -#define SIGNATURE_1 0x96 -#define SIGNATURE_2 0x50 - - -#endif /* #ifdef _AVR_ATMEGA4808_H_INCLUDED */ - diff --git a/arduino/hardware/tools/avr/avr/include/avr/iom4809.h b/arduino/hardware/tools/avr/avr/include/avr/iom4809.h deleted file mode 100644 index f8eb4d4..0000000 --- a/arduino/hardware/tools/avr/avr/include/avr/iom4809.h +++ /dev/null @@ -1,5473 +0,0 @@ -/***************************************************************************** - * - * Copyright (C) 2017 Atmel Corporation, a wholly owned subsidiary of Microchip Technology Inc. - * All rights reserved. - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - ****************************************************************************/ - - -#ifndef _AVR_IO_H_ -# error "Include instead of this file." -#endif - -#ifndef _AVR_IOXXX_H_ -# define _AVR_IOXXX_H_ "iom4809.h" -#else -# error "Attempt to include more than one file." -#endif - -#ifndef _AVR_ATMEGA4809_H_INCLUDED -#define _AVR_ATMEGA4809_H_INCLUDED - -/* Ungrouped common registers */ -#define CCP _SFR_MEM8(0x0034) /* Configuration Change Protection */ -#define RAMPZ _SFR_MEM8(0x003B) /* Extended Z-pointer Register */ -#define SPH _SFR_MEM8(0x003E) /* Stack Pointer High */ -#define SPL _SFR_MEM8(0x003D) /* Stack Pointer Low */ -#define SREG _SFR_MEM8(0x003F) /* Status Register */ - -#define GPIOR0 _SFR_MEM8(0x001C) /* General Purpose IO Register 0 */ -#define GPIOR1 _SFR_MEM8(0x001D) /* General Purpose IO Register 1 */ -#define GPIOR2 _SFR_MEM8(0x001E) /* General Purpose IO Register 2 */ -#define GPIOR3 _SFR_MEM8(0x001F) /* General Purpose IO Register 3 */ - -/* Deprecated */ -#define GPIO0 _SFR_MEM8(0x001C) /* General Purpose IO Register 0 */ -#define GPIO1 _SFR_MEM8(0x001D) /* General Purpose IO Register 1 */ -#define GPIO2 _SFR_MEM8(0x001E) /* General Purpose IO Register 2 */ -#define GPIO3 _SFR_MEM8(0x001F) /* General Purpose IO Register 3 */ - -/* C Language Only */ -#if !defined (__ASSEMBLER__) - -#include - -typedef volatile uint8_t register8_t; -typedef volatile uint16_t register16_t; -typedef volatile uint32_t register32_t; - - -#ifdef _WORDREGISTER -#undef _WORDREGISTER -#endif -#define _WORDREGISTER(regname) \ - __extension__ union \ - { \ - register16_t regname; \ - struct \ - { \ - register8_t regname ## L; \ - register8_t regname ## H; \ - }; \ - } - -#ifdef _DWORDREGISTER -#undef _DWORDREGISTER -#endif -#define _DWORDREGISTER(regname) \ - __extension__ union \ - { \ - register32_t regname; \ - struct \ - { \ - register8_t regname ## 0; \ - register8_t regname ## 1; \ - register8_t regname ## 2; \ - register8_t regname ## 3; \ - }; \ - } - - -/* -========================================================================== -IO Module Structures -========================================================================== -*/ - - -/* --------------------------------------------------------------------------- -AC - Analog Comparator --------------------------------------------------------------------------- -*/ - -/* Analog Comparator */ -typedef struct AC_struct -{ - register8_t CTRLA; /* Control A */ - register8_t reserved_0x01; - register8_t MUXCTRLA; /* Mux Control A */ - register8_t reserved_0x03; - register8_t DACREF; /* Referance scale control */ - register8_t reserved_0x05; - register8_t INTCTRL; /* Interrupt Control */ - register8_t STATUS; /* Status */ -} AC_t; - -/* Hysteresis Mode select */ -typedef enum AC_HYSMODE_enum -{ - AC_HYSMODE_OFF_gc = (0x00<<1), /* No hysteresis */ - AC_HYSMODE_10mV_gc = (0x01<<1), /* 10mV hysteresis */ - AC_HYSMODE_25mV_gc = (0x02<<1), /* 25mV hysteresis */ - AC_HYSMODE_50mV_gc = (0x03<<1), /* 50mV hysteresis */ -} AC_HYSMODE_t; - -/* Interrupt Mode select */ -typedef enum AC_INTMODE_enum -{ - AC_INTMODE_BOTHEDGE_gc = (0x00<<4), /* Any Edge */ - AC_INTMODE_NEGEDGE_gc = (0x02<<4), /* Negative Edge */ - AC_INTMODE_POSEDGE_gc = (0x03<<4), /* Positive Edge */ -} AC_INTMODE_t; - -/* Low Power Mode select */ -typedef enum AC_LPMODE_enum -{ - AC_LPMODE_DIS_gc = (0x00<<3), /* Low power mode disabled */ - AC_LPMODE_EN_gc = (0x01<<3), /* Low power mode enabled */ -} AC_LPMODE_t; - -/* Negative Input MUX Selection select */ -typedef enum AC_MUXNEG_enum -{ - AC_MUXNEG_PIN0_gc = (0x00<<0), /* Negative Pin 0 */ - AC_MUXNEG_PIN1_gc = (0x01<<0), /* Negative Pin 1 */ - AC_MUXNEG_PIN2_gc = (0x02<<0), /* Negative Pin 2 */ - AC_MUXNEG_DACREF_gc = (0x03<<0), /* DAC Voltage Reference */ -} AC_MUXNEG_t; - -/* Positive Input MUX Selection select */ -typedef enum AC_MUXPOS_enum -{ - AC_MUXPOS_PIN0_gc = (0x00<<3), /* Positive Pin 0 */ - AC_MUXPOS_PIN1_gc = (0x01<<3), /* Positive Pin 1 */ - AC_MUXPOS_PIN2_gc = (0x02<<3), /* Positive Pin 2 */ - AC_MUXPOS_PIN3_gc = (0x03<<3), /* Positive Pin 3 */ -} AC_MUXPOS_t; - -/* --------------------------------------------------------------------------- -ADC - Analog to Digital Converter --------------------------------------------------------------------------- -*/ - -/* Analog to Digital Converter */ -typedef struct ADC_struct -{ - register8_t CTRLA; /* Control A */ - register8_t CTRLB; /* Control B */ - register8_t CTRLC; /* Control C */ - register8_t CTRLD; /* Control D */ - register8_t CTRLE; /* Control E */ - register8_t SAMPCTRL; /* Sample Control */ - register8_t MUXPOS; /* Positive mux input */ - register8_t reserved_0x07; - register8_t COMMAND; /* Command */ - register8_t EVCTRL; /* Event Control */ - register8_t INTCTRL; /* Interrupt Control */ - register8_t INTFLAGS; /* Interrupt Flags */ - register8_t DBGCTRL; /* Debug Control */ - register8_t TEMP; /* Temporary Data */ - register8_t reserved_0x0E; - register8_t reserved_0x0F; - _WORDREGISTER(RES); /* ADC Accumulator Result */ - _WORDREGISTER(WINLT); /* Window comparator low threshold */ - _WORDREGISTER(WINHT); /* Window comparator high threshold */ - register8_t CALIB; /* Calibration */ - register8_t reserved_0x17; -} ADC_t; - -/* Automatic Sampling Delay Variation select */ -typedef enum ADC_ASDV_enum -{ - ADC_ASDV_ASVOFF_gc = (0x00<<4), /* The Automatic Sampling Delay Variation is disabled */ - ADC_ASDV_ASVON_gc = (0x01<<4), /* The Automatic Sampling Delay Variation is enabled */ -} ADC_ASDV_t; - -/* Duty Cycle select */ -typedef enum ADC_DUTYCYC_enum -{ - ADC_DUTYCYC_DUTY50_gc = (0x00<<0), /* 50% Duty cycle */ - ADC_DUTYCYC_DUTY25_gc = (0x01<<0), /* 25% Duty cycle */ -} ADC_DUTYCYC_t; - -/* Initial Delay Selection select */ -typedef enum ADC_INITDLY_enum -{ - ADC_INITDLY_DLY0_gc = (0x00<<5), /* Delay 0 CLK_ADC cycles */ - ADC_INITDLY_DLY16_gc = (0x01<<5), /* Delay 16 CLK_ADC cycles */ - ADC_INITDLY_DLY32_gc = (0x02<<5), /* Delay 32 CLK_ADC cycles */ - ADC_INITDLY_DLY64_gc = (0x03<<5), /* Delay 64 CLK_ADC cycles */ - ADC_INITDLY_DLY128_gc = (0x04<<5), /* Delay 128 CLK_ADC cycles */ - ADC_INITDLY_DLY256_gc = (0x05<<5), /* Delay 256 CLK_ADC cycles */ -} ADC_INITDLY_t; - -/* Analog Channel Selection Bits select */ -typedef enum ADC_MUXPOS_enum -{ - ADC_MUXPOS_AIN0_gc = (0x00<<0), /* ADC input pin 0 */ - ADC_MUXPOS_AIN1_gc = (0x01<<0), /* ADC input pin 1 */ - ADC_MUXPOS_DACREF_gc = (0x1C<<0), /* AC DAC Reference */ - ADC_MUXPOS_TEMPSENSE_gc = (0x1E<<0), /* Temperature sensor */ - ADC_MUXPOS_GND_gc = (0x1F<<0), /* 0V (GND) */ - ADC_MUXPOS_AIN2_gc = (0x02<<0), /* ADC input pin 2 */ - ADC_MUXPOS_AIN3_gc = (0x03<<0), /* ADC input pin 3 */ - ADC_MUXPOS_AIN4_gc = (0x04<<0), /* ADC input pin 4 */ - ADC_MUXPOS_AIN5_gc = (0x05<<0), /* ADC input pin 5 */ - ADC_MUXPOS_AIN6_gc = (0x06<<0), /* ADC input pin 6 */ - ADC_MUXPOS_AIN7_gc = (0x07<<0), /* ADC input pin 7 */ - ADC_MUXPOS_AIN8_gc = (0x08<<0), /* ADC input pin 8 */ - ADC_MUXPOS_AIN9_gc = (0x09<<0), /* ADC input pin 9 */ - ADC_MUXPOS_AIN10_gc = (0x0A<<0), /* ADC input pin 10 */ - ADC_MUXPOS_AIN11_gc = (0x0B<<0), /* ADC input pin 11 */ - ADC_MUXPOS_AIN12_gc = (0x0C<<0), /* ADC input pin 12 */ - ADC_MUXPOS_AIN13_gc = (0x0D<<0), /* ADC input pin 13 */ - ADC_MUXPOS_AIN14_gc = (0x0E<<0), /* ADC input pin 14 */ - ADC_MUXPOS_AIN15_gc = (0x0F<<0), /* ADC input pin 15 */ -} ADC_MUXPOS_t; - -/* Clock Pre-scaler select */ -typedef enum ADC_PRESC_enum -{ - ADC_PRESC_DIV2_gc = (0x00<<0), /* CLK_PER divided by 2 */ - ADC_PRESC_DIV4_gc = (0x01<<0), /* CLK_PER divided by 4 */ - ADC_PRESC_DIV8_gc = (0x02<<0), /* CLK_PER divided by 8 */ - ADC_PRESC_DIV16_gc = (0x03<<0), /* CLK_PER divided by 16 */ - ADC_PRESC_DIV32_gc = (0x04<<0), /* CLK_PER divided by 32 */ - ADC_PRESC_DIV64_gc = (0x05<<0), /* CLK_PER divided by 64 */ - ADC_PRESC_DIV128_gc = (0x06<<0), /* CLK_PER divided by 128 */ - ADC_PRESC_DIV256_gc = (0x07<<0), /* CLK_PER divided by 256 */ -} ADC_PRESC_t; - -/* Reference Selection select */ -typedef enum ADC_REFSEL_enum -{ - ADC_REFSEL_INTREF_gc = (0x00<<4), /* Internal reference */ - ADC_REFSEL_VDDREF_gc = (0x01<<4), /* VDD */ - ADC_REFSEL_VREFA_gc = (0x02<<4), /* External reference */ -} ADC_REFSEL_t; - -/* ADC Resolution select */ -typedef enum ADC_RESSEL_enum -{ - ADC_RESSEL_10BIT_gc = (0x00<<2), /* 10-bit mode */ - ADC_RESSEL_8BIT_gc = (0x01<<2), /* 8-bit mode */ -} ADC_RESSEL_t; - -/* Accumulation Samples select */ -typedef enum ADC_SAMPNUM_enum -{ - ADC_SAMPNUM_ACC1_gc = (0x00<<0), /* 1 ADC sample */ - ADC_SAMPNUM_ACC2_gc = (0x01<<0), /* Accumulate 2 samples */ - ADC_SAMPNUM_ACC4_gc = (0x02<<0), /* Accumulate 4 samples */ - ADC_SAMPNUM_ACC8_gc = (0x03<<0), /* Accumulate 8 samples */ - ADC_SAMPNUM_ACC16_gc = (0x04<<0), /* Accumulate 16 samples */ - ADC_SAMPNUM_ACC32_gc = (0x05<<0), /* Accumulate 32 samples */ - ADC_SAMPNUM_ACC64_gc = (0x06<<0), /* Accumulate 64 samples */ -} ADC_SAMPNUM_t; - -/* Window Comparator Mode select */ -typedef enum ADC_WINCM_enum -{ - ADC_WINCM_NONE_gc = (0x00<<0), /* No Window Comparison */ - ADC_WINCM_BELOW_gc = (0x01<<0), /* Below Window */ - ADC_WINCM_ABOVE_gc = (0x02<<0), /* Above Window */ - ADC_WINCM_INSIDE_gc = (0x03<<0), /* Inside Window */ - ADC_WINCM_OUTSIDE_gc = (0x04<<0), /* Outside Window */ -} ADC_WINCM_t; - -/* --------------------------------------------------------------------------- -BOD - Bod interface --------------------------------------------------------------------------- -*/ - -/* Bod interface */ -typedef struct BOD_struct -{ - register8_t CTRLA; /* Control A */ - register8_t CTRLB; /* Control B */ - register8_t reserved_0x02; - register8_t reserved_0x03; - register8_t reserved_0x04; - register8_t reserved_0x05; - register8_t reserved_0x06; - register8_t reserved_0x07; - register8_t VLMCTRLA; /* Voltage level monitor Control */ - register8_t INTCTRL; /* Voltage level monitor interrupt Control */ - register8_t INTFLAGS; /* Voltage level monitor interrupt Flags */ - register8_t STATUS; /* Voltage level monitor status */ - register8_t reserved_0x0C; - register8_t reserved_0x0D; - register8_t reserved_0x0E; - register8_t reserved_0x0F; -} BOD_t; - -/* Operation in active mode select */ -typedef enum BOD_ACTIVE_enum -{ - BOD_ACTIVE_DIS_gc = (0x00<<2), /* Disabled */ - BOD_ACTIVE_ENABLED_gc = (0x01<<2), /* Enabled */ - BOD_ACTIVE_SAMPLED_gc = (0x02<<2), /* Sampled */ - BOD_ACTIVE_ENWAKE_gc = (0x03<<2), /* Enabled with wake-up halted until BOD is ready */ -} BOD_ACTIVE_t; - -/* Bod level select */ -typedef enum BOD_LVL_enum -{ - BOD_LVL_BODLEVEL0_gc = (0x00<<0), /* 1.8 V */ - BOD_LVL_BODLEVEL1_gc = (0x01<<0), /* 2.1 V */ - BOD_LVL_BODLEVEL2_gc = (0x02<<0), /* 2.6 V */ - BOD_LVL_BODLEVEL3_gc = (0x03<<0), /* 2.9 V */ - BOD_LVL_BODLEVEL4_gc = (0x04<<0), /* 3.3 V */ - BOD_LVL_BODLEVEL5_gc = (0x05<<0), /* 3.7 V */ - BOD_LVL_BODLEVEL6_gc = (0x06<<0), /* 4.0 V */ - BOD_LVL_BODLEVEL7_gc = (0x07<<0), /* 4.2 V */ -} BOD_LVL_t; - -/* Sample frequency select */ -typedef enum BOD_SAMPFREQ_enum -{ - BOD_SAMPFREQ_1KHZ_gc = (0x00<<4), /* 1kHz sampling frequency */ - BOD_SAMPFREQ_125HZ_gc = (0x01<<4), /* 125kHz sampling frequency */ -} BOD_SAMPFREQ_t; - -/* Operation in sleep mode select */ -typedef enum BOD_SLEEP_enum -{ - BOD_SLEEP_DIS_gc = (0x00<<0), /* Disabled */ - BOD_SLEEP_ENABLED_gc = (0x01<<0), /* Enabled */ - BOD_SLEEP_SAMPLED_gc = (0x02<<0), /* Sampled */ -} BOD_SLEEP_t; - -/* Configuration select */ -typedef enum BOD_VLMCFG_enum -{ - BOD_VLMCFG_BELOW_gc = (0x00<<1), /* Interrupt when supply goes below VLM level */ - BOD_VLMCFG_ABOVE_gc = (0x01<<1), /* Interrupt when supply goes above VLM level */ - BOD_VLMCFG_CROSS_gc = (0x02<<1), /* Interrupt when supply crosses VLM level */ -} BOD_VLMCFG_t; - -/* voltage level monitor level select */ -typedef enum BOD_VLMLVL_enum -{ - BOD_VLMLVL_5ABOVE_gc = (0x00<<0), /* VLM threshold 5% above BOD level */ - BOD_VLMLVL_15ABOVE_gc = (0x01<<0), /* VLM threshold 15% above BOD level */ - BOD_VLMLVL_25ABOVE_gc = (0x02<<0), /* VLM threshold 25% above BOD level */ -} BOD_VLMLVL_t; - -/* --------------------------------------------------------------------------- -CCL - Configurable Custom Logic --------------------------------------------------------------------------- -*/ - -/* Configurable Custom Logic */ -typedef struct CCL_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t SEQCTRL0; /* Sequential Control 0 */ - register8_t reserved_0x02; - register8_t reserved_0x03; - register8_t reserved_0x04; - register8_t INTCTRL0; /* Interrupt Control 0 */ - register8_t reserved_0x06; - register8_t INTFLAGS; /* Interrupt Flags */ - register8_t LUT0CTRLA; /* LUT Control 0 A */ - register8_t LUT0CTRLB; /* LUT Control 0 B */ - register8_t LUT0CTRLC; /* LUT Control 0 C */ - register8_t TRUTH0; /* Truth 0 */ - register8_t LUT1CTRLA; /* LUT Control 1 A */ - register8_t LUT1CTRLB; /* LUT Control 1 B */ - register8_t LUT1CTRLC; /* LUT Control 1 C */ - register8_t TRUTH1; /* Truth 1 */ - register8_t LUT2CTRLA; /* LUT Control 2 A */ - register8_t LUT2CTRLB; /* LUT Control 2 B */ - register8_t LUT2CTRLC; /* LUT Control 2 C */ - register8_t TRUTH2; /* Truth 2 */ - register8_t LUT3CTRLA; /* LUT Control 3 A */ - register8_t LUT3CTRLB; /* LUT Control 3 B */ - register8_t LUT3CTRLC; /* LUT Control 3 C */ - register8_t TRUTH3; /* Truth 3 */ - register8_t reserved_0x18; - register8_t reserved_0x19; - register8_t reserved_0x1A; - register8_t reserved_0x1B; - register8_t reserved_0x1C; - register8_t reserved_0x1D; - register8_t reserved_0x1E; - register8_t reserved_0x1F; - register8_t reserved_0x20; - register8_t reserved_0x21; - register8_t reserved_0x22; - register8_t reserved_0x23; - register8_t reserved_0x24; - register8_t reserved_0x25; - register8_t reserved_0x26; - register8_t reserved_0x27; - register8_t reserved_0x28; - register8_t reserved_0x29; - register8_t reserved_0x2A; - register8_t reserved_0x2B; - register8_t reserved_0x2C; - register8_t reserved_0x2D; - register8_t reserved_0x2E; - register8_t reserved_0x2F; - register8_t reserved_0x30; - register8_t reserved_0x31; - register8_t reserved_0x32; - register8_t reserved_0x33; - register8_t reserved_0x34; - register8_t reserved_0x35; - register8_t reserved_0x36; - register8_t reserved_0x37; - register8_t reserved_0x38; - register8_t reserved_0x39; - register8_t reserved_0x3A; - register8_t reserved_0x3B; - register8_t reserved_0x3C; - register8_t reserved_0x3D; - register8_t reserved_0x3E; - register8_t reserved_0x3F; -} CCL_t; - -/* Clock Source Selection select */ -typedef enum CCL_CLKSRC_enum -{ - CCL_CLKSRC_CLKPER_gc = (0x00<<1), /* CLK_PER is clocking the LUT */ - CCL_CLKSRC_IN2_gc = (0x01<<1), /* IN[2] is clocking the LUT */ - CCL_CLKSRC_OSC20M_gc = (0x02<<1), /* 20MHz oscillator before prescaler is clocking the LUT */ - CCL_CLKSRC_OSCULP32K_gc = (0x03<<1), /* 32kHz oscillator is clocking the LUT */ - CCL_CLKSRC_OSCULP1K_gc = (0x04<<1), /* 32kHz oscillator after DIV32 is clocking the LUT */ -} CCL_CLKSRC_t; - -/* Edge Detection Enable select */ -typedef enum CCL_EDGEDET_enum -{ - CCL_EDGEDET_DIS_gc = (0x00<<7), /* Edge detector is disabled */ - CCL_EDGEDET_EN_gc = (0x01<<7), /* Edge detector is enabled */ -} CCL_EDGEDET_t; - -/* Filter Selection select */ -typedef enum CCL_FILTSEL_enum -{ - CCL_FILTSEL_DISABLE_gc = (0x00<<4), /* Filter disabled */ - CCL_FILTSEL_SYNCH_gc = (0x01<<4), /* Synchronizer enabled */ - CCL_FILTSEL_FILTER_gc = (0x02<<4), /* Filter enabled */ -} CCL_FILTSEL_t; - -/* LUT Input 0 Source Selection select */ -typedef enum CCL_INSEL0_enum -{ - CCL_INSEL0_MASK_gc = (0x00<<0), /* Masked input */ - CCL_INSEL0_FEEDBACK_gc = (0x01<<0), /* Feedback input source */ - CCL_INSEL0_LINK_gc = (0x02<<0), /* Linked LUT input source */ - CCL_INSEL0_EVENTA_gc = (0x03<<0), /* Event input source A */ - CCL_INSEL0_EVENTB_gc = (0x04<<0), /* Event input source B */ - CCL_INSEL0_IO_gc = (0x05<<0), /* IO pin LUTn-IN0 input source */ - CCL_INSEL0_AC0_gc = (0x06<<0), /* AC0 OUT input source */ - CCL_INSEL0_USART0_gc = (0x08<<0), /* USART0 TXD input source */ - CCL_INSEL0_SPI0_gc = (0x09<<0), /* SPI0 MOSI input source */ - CCL_INSEL0_TCA0_gc = (0x0A<<0), /* TCA0 WO0 input source */ - CCL_INSEL0_TCB0_gc = (0x0C<<0), /* TCB0 WO input source */ - CCL_INSEL0_TCD0_gc = (0x0D<<0), /* TCD0 WOA input source */ -} CCL_INSEL0_t; - -/* LUT Input 1 Source Selection select */ -typedef enum CCL_INSEL1_enum -{ - CCL_INSEL1_MASK_gc = (0x00<<4), /* Masked input */ - CCL_INSEL1_FEEDBACK_gc = (0x01<<4), /* Feedback input source */ - CCL_INSEL1_LINK_gc = (0x02<<4), /* Linked LUT input source */ - CCL_INSEL1_EVENTA_gc = (0x03<<4), /* Event input source A */ - CCL_INSEL1_EVENTB_gc = (0x04<<4), /* Event input source B */ - CCL_INSEL1_IO_gc = (0x05<<4), /* IO pin LUTn-N1 input source */ - CCL_INSEL1_AC0_gc = (0x06<<4), /* AC0 OUT input source */ - CCL_INSEL1_USART1_gc = (0x08<<4), /* USART1 TXD input source */ - CCL_INSEL1_SPI0_gc = (0x09<<4), /* SPI0 MOSI input source */ - CCL_INSEL1_TCA0_gc = (0x0A<<4), /* TCA0 WO1 input source */ - CCL_INSEL1_TCB1_gc = (0x0C<<4), /* TCB1 WO input source */ - CCL_INSEL1_TCD0_gc = (0x0D<<4), /* TCD0 WOB input soruce */ -} CCL_INSEL1_t; - -/* LUT Input 2 Source Selection select */ -typedef enum CCL_INSEL2_enum -{ - CCL_INSEL2_MASK_gc = (0x00<<0), /* Masked input */ - CCL_INSEL2_FEEDBACK_gc = (0x01<<0), /* Feedback input source */ - CCL_INSEL2_LINK_gc = (0x02<<0), /* Linked LUT input source */ - CCL_INSEL2_EVENTA_gc = (0x03<<0), /* Event input source A */ - CCL_INSEL2_EVENTB_gc = (0x04<<0), /* Event input source B */ - CCL_INSEL2_IO_gc = (0x05<<0), /* IO pin LUTn-IN2 input source */ - CCL_INSEL2_AC0_gc = (0x06<<0), /* AC0 OUT input source */ - CCL_INSEL2_USART2_gc = (0x08<<0), /* USART2 TXD input source */ - CCL_INSEL2_SPI0_gc = (0x09<<0), /* SPI0 SCK input source */ - CCL_INSEL2_TCA0_gc = (0x0A<<0), /* TCA0 WO2 input source */ - CCL_INSEL2_TCB2_gc = (0x0C<<0), /* TCB2 WO input source */ - CCL_INSEL2_TCD0_gc = (0x0D<<0), /* TCD0 WOC input source */ -} CCL_INSEL2_t; - -/* Interrupt Mode for LUT0 select */ -typedef enum CCL_INTMODE0_enum -{ - CCL_INTMODE0_BOTH_gc = (0x00<<0), /* Sense both edges */ - CCL_INTMODE0_FALLING_gc = (0x01<<0), /* Sense falling edge */ - CCL_INTMODE0_RISING_gc = (0x02<<0), /* Sense rising edge */ - CCL_INTMODE0_INTDISABLE_gc = (0x03<<0), /* Interrupt disabled */ -} CCL_INTMODE0_t; - -/* Interrupt Mode for LUT1 select */ -typedef enum CCL_INTMODE1_enum -{ - CCL_INTMODE1_BOTH_gc = (0x00<<2), /* Sense both edges */ - CCL_INTMODE1_FALLING_gc = (0x01<<2), /* Sense falling edge */ - CCL_INTMODE1_RISING_gc = (0x02<<2), /* Sense rising edge */ - CCL_INTMODE1_INTDISABLE_gc = (0x03<<2), /* Interrupt disabled */ -} CCL_INTMODE1_t; - -/* Interrupt Mode for LUT2 select */ -typedef enum CCL_INTMODE2_enum -{ - CCL_INTMODE2_BOTH_gc = (0x00<<4), /* Sense both edges */ - CCL_INTMODE2_FALLING_gc = (0x01<<4), /* Sense falling edge */ - CCL_INTMODE2_RISING_gc = (0x02<<4), /* Sense rising edge */ - CCL_INTMODE2_INTDISABLE_gc = (0x03<<4), /* Interrupt disabled */ -} CCL_INTMODE2_t; - -/* Interrupt Mode for LUT3 select */ -typedef enum CCL_INTMODE3_enum -{ - CCL_INTMODE3_BOTH_gc = (0x00<<6), /* Sense both edges */ - CCL_INTMODE3_FALLING_gc = (0x01<<6), /* Sense falling edge */ - CCL_INTMODE3_RISING_gc = (0x02<<6), /* Sense rising edge */ - CCL_INTMODE3_INTDISABLE_gc = (0x03<<6), /* Interrupt disabled */ -} CCL_INTMODE3_t; - -/* Sequential Selection select */ -typedef enum CCL_SEQSEL_enum -{ - CCL_SEQSEL_DISABLE_gc = (0x00<<0), /* Sequential logic disabled */ - CCL_SEQSEL_DFF_gc = (0x01<<0), /* D FlipFlop */ - CCL_SEQSEL_JK_gc = (0x02<<0), /* JK FlipFlop */ - CCL_SEQSEL_LATCH_gc = (0x03<<0), /* D Latch */ - CCL_SEQSEL_RS_gc = (0x04<<0), /* RS Latch */ -} CCL_SEQSEL_t; - -/* --------------------------------------------------------------------------- -CLKCTRL - Clock controller --------------------------------------------------------------------------- -*/ - -/* Clock controller */ -typedef struct CLKCTRL_struct -{ - register8_t MCLKCTRLA; /* MCLK Control A */ - register8_t MCLKCTRLB; /* MCLK Control B */ - register8_t MCLKLOCK; /* MCLK Lock */ - register8_t MCLKSTATUS; /* MCLK Status */ - register8_t reserved_0x04; - register8_t reserved_0x05; - register8_t reserved_0x06; - register8_t reserved_0x07; - register8_t reserved_0x08; - register8_t reserved_0x09; - register8_t reserved_0x0A; - register8_t reserved_0x0B; - register8_t reserved_0x0C; - register8_t reserved_0x0D; - register8_t reserved_0x0E; - register8_t reserved_0x0F; - register8_t OSC20MCTRLA; /* OSC20M Control A */ - register8_t OSC20MCALIBA; /* OSC20M Calibration A */ - register8_t OSC20MCALIBB; /* OSC20M Calibration B */ - register8_t reserved_0x13; - register8_t reserved_0x14; - register8_t reserved_0x15; - register8_t reserved_0x16; - register8_t reserved_0x17; - register8_t OSC32KCTRLA; /* OSC32K Control A */ - register8_t OSC32KCALIB; /* OSC32K Calibration */ - register8_t reserved_0x1A; - register8_t reserved_0x1B; - register8_t XOSC32KCTRLA; /* XOSC32K Control A */ - register8_t reserved_0x1D; - register8_t reserved_0x1E; - register8_t reserved_0x1F; -} CLKCTRL_t; - -/* clock select select */ -typedef enum CLKCTRL_CLKSEL_enum -{ - CLKCTRL_CLKSEL_OSC20M_gc = (0x00<<0), /* 20MHz oscillator */ - CLKCTRL_CLKSEL_OSCULP32K_gc = (0x01<<0), /* 32KHz oscillator */ - CLKCTRL_CLKSEL_XOSC32K_gc = (0x02<<0), /* 32.768kHz crystal oscillator */ - CLKCTRL_CLKSEL_EXTCLK_gc = (0x03<<0), /* External clock */ -} CLKCTRL_CLKSEL_t; - -/* Crystal startup time select */ -typedef enum CLKCTRL_CSUT_enum -{ - CLKCTRL_CSUT_1K_gc = (0x00<<4), /* 1k cycles */ - CLKCTRL_CSUT_16K_gc = (0x01<<4), /* 16k cycles */ - CLKCTRL_CSUT_32K_gc = (0x02<<4), /* 32k cycles */ - CLKCTRL_CSUT_64K_gc = (0x03<<4), /* 64k cycles */ -} CLKCTRL_CSUT_t; - -/* Prescaler division select */ -typedef enum CLKCTRL_PDIV_enum -{ - CLKCTRL_PDIV_2X_gc = (0x00<<1), /* 2X */ - CLKCTRL_PDIV_4X_gc = (0x01<<1), /* 4X */ - CLKCTRL_PDIV_8X_gc = (0x02<<1), /* 8X */ - CLKCTRL_PDIV_16X_gc = (0x03<<1), /* 16X */ - CLKCTRL_PDIV_32X_gc = (0x04<<1), /* 32X */ - CLKCTRL_PDIV_64X_gc = (0x05<<1), /* 64X */ - CLKCTRL_PDIV_6X_gc = (0x08<<1), /* 6X */ - CLKCTRL_PDIV_10X_gc = (0x09<<1), /* 10X */ - CLKCTRL_PDIV_12X_gc = (0x0A<<1), /* 12X */ - CLKCTRL_PDIV_24X_gc = (0x0B<<1), /* 24X */ - CLKCTRL_PDIV_48X_gc = (0x0C<<1), /* 48X */ -} CLKCTRL_PDIV_t; - -/* --------------------------------------------------------------------------- -CPU - CPU --------------------------------------------------------------------------- -*/ - -/* CCP signature select */ -typedef enum CCP_enum -{ - CCP_SPM_gc = (0x9D<<0), /* SPM Instruction Protection */ - CCP_IOREG_gc = (0xD8<<0), /* IO Register Protection */ -} CCP_t; - -/* --------------------------------------------------------------------------- -CPUINT - Interrupt Controller --------------------------------------------------------------------------- -*/ - -/* Interrupt Controller */ -typedef struct CPUINT_struct -{ - register8_t CTRLA; /* Control A */ - register8_t STATUS; /* Status */ - register8_t LVL0PRI; /* Interrupt Level 0 Priority */ - register8_t LVL1VEC; /* Interrupt Level 1 Priority Vector */ -} CPUINT_t; - - -/* --------------------------------------------------------------------------- -CRCSCAN - CRCSCAN --------------------------------------------------------------------------- -*/ - -/* CRCSCAN */ -typedef struct CRCSCAN_struct -{ - register8_t CTRLA; /* Control A */ - register8_t CTRLB; /* Control B */ - register8_t STATUS; /* Status */ - register8_t reserved_0x03; -} CRCSCAN_t; - -/* CRC Flash Access Mode select */ -typedef enum CRCSCAN_MODE_enum -{ - CRCSCAN_MODE_PRIORITY_gc = (0x00<<4), /* Priority to flash */ - CRCSCAN_MODE_RESERVED_gc = (0x01<<4), /* Reserved */ - CRCSCAN_MODE_BACKGROUND_gc = (0x02<<4), /* Lowest priority to flash */ - CRCSCAN_MODE_CONTINUOUS_gc = (0x03<<4), /* Continuous checks in background */ -} CRCSCAN_MODE_t; - -/* CRC Source select */ -typedef enum CRCSCAN_SRC_enum -{ - CRCSCAN_SRC_FLASH_gc = (0x00<<0), /* CRC on entire flash */ - CRCSCAN_SRC_APPLICATION_gc = (0x01<<0), /* CRC on boot and appl section of flash */ - CRCSCAN_SRC_BOOT_gc = (0x02<<0), /* CRC on boot section of flash */ -} CRCSCAN_SRC_t; - -/* --------------------------------------------------------------------------- -EVSYS - Event System --------------------------------------------------------------------------- -*/ - -/* Event System */ -typedef struct EVSYS_struct -{ - register8_t STROBE; /* Channel Strobe */ - register8_t reserved_0x01; - register8_t reserved_0x02; - register8_t reserved_0x03; - register8_t reserved_0x04; - register8_t reserved_0x05; - register8_t reserved_0x06; - register8_t reserved_0x07; - register8_t reserved_0x08; - register8_t reserved_0x09; - register8_t reserved_0x0A; - register8_t reserved_0x0B; - register8_t reserved_0x0C; - register8_t reserved_0x0D; - register8_t reserved_0x0E; - register8_t reserved_0x0F; - register8_t CHANNEL0; /* Multiplexer Channel 0 */ - register8_t CHANNEL1; /* Multiplexer Channel 1 */ - register8_t CHANNEL2; /* Multiplexer Channel 2 */ - register8_t CHANNEL3; /* Multiplexer Channel 3 */ - register8_t CHANNEL4; /* Multiplexer Channel 4 */ - register8_t CHANNEL5; /* Multiplexer Channel 5 */ - register8_t CHANNEL6; /* Multiplexer Channel 6 */ - register8_t CHANNEL7; /* Multiplexer Channel 7 */ - register8_t reserved_0x18; - register8_t reserved_0x19; - register8_t reserved_0x1A; - register8_t reserved_0x1B; - register8_t reserved_0x1C; - register8_t reserved_0x1D; - register8_t reserved_0x1E; - register8_t reserved_0x1F; - register8_t USERCCLLUT0A; /* User CCL LUT0 Event A */ - register8_t USERCCLLUT0B; /* User CCL LUT0 Event B */ - register8_t USERCCLLUT1A; /* User CCL LUT1 Event A */ - register8_t USERCCLLUT1B; /* User CCL LUT1 Event B */ - register8_t USERCCLLUT2A; /* User CCL LUT2 Event A */ - register8_t USERCCLLUT2B; /* User CCL LUT2 Event B */ - register8_t USERCCLLUT3A; /* User CCL LUT3 Event A */ - register8_t USERCCLLUT3B; /* User CCL LUT3 Event B */ - register8_t USERADC0; /* User ADC0 */ - register8_t USEREVOUTA; /* User EVOUT Port A */ - register8_t USEREVOUTB; /* User EVOUT Port B */ - register8_t USEREVOUTC; /* User EVOUT Port C */ - register8_t USEREVOUTD; /* User EVOUT Port D */ - register8_t USEREVOUTE; /* User EVOUT Port E */ - register8_t USEREVOUTF; /* User EVOUT Port F */ - register8_t USERUSART0; /* User USART0 */ - register8_t USERUSART1; /* User USART1 */ - register8_t USERUSART2; /* User USART2 */ - register8_t USERUSART3; /* User USART3 */ - register8_t USERTCA0; /* User TCA0 */ - register8_t USERTCB0; /* User TCB0 */ - register8_t USERTCB1; /* User TCB1 */ - register8_t USERTCB2; /* User TCB2 */ - register8_t USERTCB3; /* User TCB3 */ - register8_t reserved_0x38; - register8_t reserved_0x39; - register8_t reserved_0x3A; - register8_t reserved_0x3B; - register8_t reserved_0x3C; - register8_t reserved_0x3D; - register8_t reserved_0x3E; - register8_t reserved_0x3F; -} EVSYS_t; - -/* Channel selector select */ -typedef enum EVSYS_CHANNEL_enum -{ - EVSYS_CHANNEL_OFF_gc = (0x00<<0), /* Off */ - EVSYS_CHANNEL_CHANNEL0_gc = (0x01<<0), /* Connect user to event channel 0 */ - EVSYS_CHANNEL_CHANNEL1_gc = (0x02<<0), /* Connect user to event channel 1 */ - EVSYS_CHANNEL_CHANNEL2_gc = (0x03<<0), /* Connect user to event channel 2 */ - EVSYS_CHANNEL_CHANNEL3_gc = (0x04<<0), /* Connect user to event channel 3 */ - EVSYS_CHANNEL_CHANNEL4_gc = (0x05<<0), /* Connect user to event channel 4 */ - EVSYS_CHANNEL_CHANNEL5_gc = (0x06<<0), /* Connect user to event channel 5 */ - EVSYS_CHANNEL_CHANNEL6_gc = (0x07<<0), /* Connect user to event channel 6 */ - EVSYS_CHANNEL_CHANNEL7_gc = (0x08<<0), /* Connect user to event channel 7 */ -} EVSYS_CHANNEL_t; - -/* Generator selector select */ -typedef enum EVSYS_GENERATOR_enum -{ - EVSYS_GENERATOR_OFF_gc = (0x00<<0), /* Off */ - EVSYS_GENERATOR_UPDI_gc = (0x01<<0), /* Unified Program and Debug Interface */ - EVSYS_GENERATOR_CCL_LUT0_gc = (0x10<<0), /* Configurable Custom Logic LUT0 */ - EVSYS_GENERATOR_CCL_LUT1_gc = (0x11<<0), /* Configurable Custom Logic LUT1 */ - EVSYS_GENERATOR_CCL_LUT2_gc = (0x12<<0), /* Configurable Custom Logic LUT2 */ - EVSYS_GENERATOR_CCL_LUT3_gc = (0x13<<0), /* Configurable Custom Logic LUT3 */ - EVSYS_GENERATOR_OSC_TEST_gc = (0x02<<0), /* Oscillator test event */ - EVSYS_GENERATOR_AC0_OUT_gc = (0x20<<0), /* Analog Comparator 0 out */ - EVSYS_GENERATOR_ADC0_COMP_gc = (0x24<<0), /* ADC 0 Comparator Event */ - EVSYS_GENERATOR_PORT0_PIN0_gc = (0x40<<0), /* Port 0 Pin 0 */ - EVSYS_GENERATOR_PORT0_PIN1_gc = (0x41<<0), /* Port 0 Pin 1 */ - EVSYS_GENERATOR_PORT0_PIN2_gc = (0x42<<0), /* Port 0 Pin 2 */ - EVSYS_GENERATOR_PORT0_PIN3_gc = (0x43<<0), /* Port 0 Pin 3 */ - EVSYS_GENERATOR_PORT0_PIN4_gc = (0x44<<0), /* Port 0 Pin 4 */ - EVSYS_GENERATOR_PORT0_PIN5_gc = (0x45<<0), /* Port 0 Pin 5 */ - EVSYS_GENERATOR_PORT0_PIN6_gc = (0x46<<0), /* Port 0 Pin 6 */ - EVSYS_GENERATOR_PORT0_PIN7_gc = (0x47<<0), /* Port 0 Pin 7 */ - EVSYS_GENERATOR_PORT1_PIN0_gc = (0x48<<0), /* Port 1 Pin 0 */ - EVSYS_GENERATOR_PORT1_PIN1_gc = (0x49<<0), /* Port 1 Pin 1 */ - EVSYS_GENERATOR_PORT1_PIN2_gc = (0x4A<<0), /* Port 1 Pin 2 */ - EVSYS_GENERATOR_PORT1_PIN3_gc = (0x4B<<0), /* Port 1 Pin 3 */ - EVSYS_GENERATOR_PORT1_PIN4_gc = (0x4C<<0), /* Port 1 Pin 4 */ - EVSYS_GENERATOR_PORT1_PIN5_gc = (0x4D<<0), /* Port 1 Pin 5 */ - EVSYS_GENERATOR_PORT1_PIN6_gc = (0x4E<<0), /* Port 1 Pin 6 */ - EVSYS_GENERATOR_PORT1_PIN7_gc = (0x4F<<0), /* Port 1 Pin 7 */ - EVSYS_GENERATOR_RTC_OVF_gc = (0x06<<0), /* Real Time Counter overflow */ - EVSYS_GENERATOR_USART0_XCK_gc = (0x60<<0), /* USART 0 Xclock */ - EVSYS_GENERATOR_USART1_XCK_gc = (0x61<<0), /* USART 1 Xclock */ - EVSYS_GENERATOR_USART2_XCK_gc = (0x62<<0), /* USART 2 Xclock */ - EVSYS_GENERATOR_USART3_XCK_gc = (0x63<<0), /* USART 3 Xclock */ - EVSYS_GENERATOR_SPI0_SCK_gc = (0x68<<0), /* SPI 0 Sclock */ - EVSYS_GENERATOR_RTC_CMP_gc = (0x07<<0), /* Real Time Counter compare */ - EVSYS_GENERATOR_RTC_PIT0_gc = (0x08<<0), /* Periodic Interrupt Timer output 0 */ - EVSYS_GENERATOR_TCA0_OVF_gc = (0x80<<0), /* Timer/Counter A0 overflow */ - EVSYS_GENERATOR_TCA0_ERR_gc = (0x81<<0), /* Timer/Counter A0 error */ - EVSYS_GENERATOR_TCA0_CMP0_gc = (0x84<<0), /* Timer/Counter A0 compare 0 */ - EVSYS_GENERATOR_TCA0_CMP1_gc = (0x85<<0), /* Timer/Counter A0 compare 1 */ - EVSYS_GENERATOR_TCA0_CMP2_gc = (0x86<<0), /* Timer/Counter A0 compare 2 */ - EVSYS_GENERATOR_RTC_PIT1_gc = (0x09<<0), /* Periodic Interrupt Timer output 1 */ - EVSYS_GENERATOR_RTC_PIT2_gc = (0x0A<<0), /* Periodic Interrupt Timer output 2 */ - EVSYS_GENERATOR_TCB0_CMP0_gc = (0xA0<<0), /* Timer/Counter B0 compare 0 */ - EVSYS_GENERATOR_TCB1_CMP0_gc = (0xA2<<0), /* Timer/Counter B1 compare 0 */ - EVSYS_GENERATOR_TCB2_CMP0_gc = (0xA4<<0), /* Timer/Counter B2 compare 0 */ - EVSYS_GENERATOR_TCB3_CMP0_gc = (0xA6<<0), /* Timer/Counter B3 compare 0 */ - EVSYS_GENERATOR_RTC_PIT3_gc = (0x0B<<0), /* Periodic Interrupt Timer output 3 */ -} EVSYS_GENERATOR_t; - -/* Software event on channels select */ -typedef enum EVSYS_STROBE0_enum -{ - EVSYS_STROBE0_EV_STROBE_CH0_gc = (0x01<<0), /* */ - EVSYS_STROBE0_EV_STROBE_CH1_gc = (0x02<<0), /* */ - EVSYS_STROBE0_EV_STROBE_CH2_gc = (0x04<<0), /* */ - EVSYS_STROBE0_EV_STROBE_CH3_gc = (0x08<<0), /* */ - EVSYS_STROBE0_EV_STROBE_CH4_gc = (0x10<<0), /* */ - EVSYS_STROBE0_EV_STROBE_CH5_gc = (0x20<<0), /* */ - EVSYS_STROBE0_EV_STROBE_CH6_gc = (0x40<<0), /* */ - EVSYS_STROBE0_EV_STROBE_CH7_gc = (0x80<<0), /* */ -} EVSYS_STROBE0_t; - -/* --------------------------------------------------------------------------- -FUSE - Fuses --------------------------------------------------------------------------- -*/ - -/* Fuses */ -typedef struct FUSE_struct -{ - register8_t WDTCFG; /* Watchdog Configuration */ - register8_t BODCFG; /* BOD Configuration */ - register8_t OSCCFG; /* Oscillator Configuration */ - register8_t reserved_0x03; - register8_t TCD0CFG; /* TCD0 Configuration */ - register8_t SYSCFG0; /* System Configuration 0 */ - register8_t SYSCFG1; /* System Configuration 1 */ - register8_t APPEND; /* Application Code Section End */ - register8_t BOOTEND; /* Boot Section End */ - register8_t reserved_0x09; -} FUSE_t; - - -/* avr-libc typedef for avr/fuse.h */ -typedef FUSE_t NVM_FUSES_t; - -/* BOD Operation in Active Mode select */ -typedef enum ACTIVE_enum -{ - ACTIVE_DIS_gc = (0x00<<2), /* Disabled */ - ACTIVE_ENABLED_gc = (0x01<<2), /* Enabled */ - ACTIVE_SAMPLED_gc = (0x02<<2), /* Sampled */ - ACTIVE_ENWAKE_gc = (0x03<<2), /* Enabled with wake-up halted until BOD is ready */ -} ACTIVE_t; - -/* CRC Source select */ -typedef enum CRCSRC_enum -{ - CRCSRC_FLASH_gc = (0x00<<6), /* The CRC is performed on the entire Flash (boot, application code and application data section). */ - CRCSRC_BOOT_gc = (0x01<<6), /* The CRC is performed on the boot section of Flash */ - CRCSRC_BOOTAPP_gc = (0x02<<6), /* The CRC is performed on the boot and application code section of Flash */ - CRCSRC_NOCRC_gc = (0x03<<6), /* Disable CRC. */ -} CRCSRC_t; - -/* Frequency Select select */ -typedef enum FREQSEL_enum -{ - FREQSEL_16MHZ_gc = (0x01<<0), /* 16 MHz */ - FREQSEL_20MHZ_gc = (0x02<<0), /* 20 MHz */ -} FREQSEL_t; - -/* BOD Level select */ -typedef enum LVL_enum -{ - LVL_BODLEVEL0_gc = (0x00<<5), /* 1.8 V */ - LVL_BODLEVEL1_gc = (0x01<<5), /* 2.1 V */ - LVL_BODLEVEL2_gc = (0x02<<5), /* 2.6 V */ - LVL_BODLEVEL3_gc = (0x03<<5), /* 2.9 V */ - LVL_BODLEVEL4_gc = (0x04<<5), /* 3.3 V */ - LVL_BODLEVEL5_gc = (0x05<<5), /* 3.7 V */ - LVL_BODLEVEL6_gc = (0x06<<5), /* 4.0 V */ - LVL_BODLEVEL7_gc = (0x07<<5), /* 4.2 V */ -} LVL_t; - -/* Watchdog Timeout Period select */ -typedef enum PERIOD_enum -{ - PERIOD_OFF_gc = (0x00<<0), /* Off */ - PERIOD_8CLK_gc = (0x01<<0), /* 8 cycles (8ms) */ - PERIOD_16CLK_gc = (0x02<<0), /* 16 cycles (16ms) */ - PERIOD_32CLK_gc = (0x03<<0), /* 32 cycles (32ms) */ - PERIOD_64CLK_gc = (0x04<<0), /* 64 cycles (64ms) */ - PERIOD_128CLK_gc = (0x05<<0), /* 128 cycles (0.128s) */ - PERIOD_256CLK_gc = (0x06<<0), /* 256 cycles (0.256s) */ - PERIOD_512CLK_gc = (0x07<<0), /* 512 cycles (0.512s) */ - PERIOD_1KCLK_gc = (0x08<<0), /* 1K cycles (1.0s) */ - PERIOD_2KCLK_gc = (0x09<<0), /* 2K cycles (2.0s) */ - PERIOD_4KCLK_gc = (0x0A<<0), /* 4K cycles (4.1s) */ - PERIOD_8KCLK_gc = (0x0B<<0), /* 8K cycles (8.2s) */ -} PERIOD_t; - -/* Reset Pin Configuration select */ -typedef enum RSTPINCFG_enum -{ - RSTPINCFG_GPIO_gc = (0x00<<2), /* GPIO mode */ - RSTPINCFG_UPDI_gc = (0x01<<2), /* UPDI mode */ - RSTPINCFG_RST_gc = (0x02<<2), /* Reset mode */ - RSTPINCFG_PDIRST_gc = (0x03<<2), /* PDI on PDI pad, reset on alternative reset pad */ -} RSTPINCFG_t; - -/* BOD Sample Frequency select */ -typedef enum SAMPFREQ_enum -{ - SAMPFREQ_1KHZ_gc = (0x00<<4), /* 1kHz sampling frequency */ - SAMPFREQ_125HZ_gc = (0x01<<4), /* 125kHz sampling frequency */ -} SAMPFREQ_t; - -/* BOD Operation in Sleep Mode select */ -typedef enum SLEEP_enum -{ - SLEEP_DIS_gc = (0x00<<0), /* Disabled */ - SLEEP_ENABLED_gc = (0x01<<0), /* Enabled */ - SLEEP_SAMPLED_gc = (0x02<<0), /* Sampled */ -} SLEEP_t; - -/* Startup Time select */ -typedef enum SUT_enum -{ - SUT_0MS_gc = (0x00<<0), /* 0 ms */ - SUT_1MS_gc = (0x01<<0), /* 1 ms */ - SUT_2MS_gc = (0x02<<0), /* 2 ms */ - SUT_4MS_gc = (0x03<<0), /* 4 ms */ - SUT_8MS_gc = (0x04<<0), /* 8 ms */ - SUT_16MS_gc = (0x05<<0), /* 16 ms */ - SUT_32MS_gc = (0x06<<0), /* 32 ms */ - SUT_64MS_gc = (0x07<<0), /* 64 ms */ -} SUT_t; - -/* Watchdog Window Timeout Period select */ -typedef enum WINDOW_enum -{ - WINDOW_OFF_gc = (0x00<<4), /* Off */ - WINDOW_8CLK_gc = (0x01<<4), /* 8 cycles (8ms) */ - WINDOW_16CLK_gc = (0x02<<4), /* 16 cycles (16ms) */ - WINDOW_32CLK_gc = (0x03<<4), /* 32 cycles (32ms) */ - WINDOW_64CLK_gc = (0x04<<4), /* 64 cycles (64ms) */ - WINDOW_128CLK_gc = (0x05<<4), /* 128 cycles (0.128s) */ - WINDOW_256CLK_gc = (0x06<<4), /* 256 cycles (0.256s) */ - WINDOW_512CLK_gc = (0x07<<4), /* 512 cycles (0.512s) */ - WINDOW_1KCLK_gc = (0x08<<4), /* 1K cycles (1.0s) */ - WINDOW_2KCLK_gc = (0x09<<4), /* 2K cycles (2.0s) */ - WINDOW_4KCLK_gc = (0x0A<<4), /* 4K cycles (4.1s) */ - WINDOW_8KCLK_gc = (0x0B<<4), /* 8K cycles (8.2s) */ -} WINDOW_t; - -/* --------------------------------------------------------------------------- -LOCKBIT - Lockbit --------------------------------------------------------------------------- -*/ - -/* Lockbit */ -typedef struct LOCKBIT_struct -{ - register8_t LOCKBIT; /* Lock Bits */ - register8_t reserved_0x01; -} LOCKBIT_t; - -/* Lock Bits select */ -typedef enum LB_enum -{ - LB_RWLOCK_gc = (0x3A<<0), /* Read and write lock */ - LB_NOLOCK_gc = (0xC5<<0), /* No locks */ -} LB_t; - -/* --------------------------------------------------------------------------- -NVMBIST - BIST in the NVMCTRL module --------------------------------------------------------------------------- -*/ - -/* BIST in the NVMCTRL module */ -typedef struct NVMBIST_struct -{ - register8_t CTRLA; /* Control A */ - register8_t ADDRPAT; /* Address pattern */ - register8_t DATAPAT; /* Data pattern */ - register8_t STATUS; /* Status */ - _WORDREGISTER(CNT); /* */ - _DWORDREGISTER(END); /* */ - register8_t reserved_0x0A; - register8_t reserved_0x0B; - register8_t reserved_0x0C; - register8_t reserved_0x0D; - register8_t reserved_0x0E; - register8_t reserved_0x0F; -} NVMBIST_t; - -/* Address mode select */ -typedef enum NVMBIST_AMODE_enum -{ - NVMBIST_AMODE_NORMAL_gc = (0x00<<4), /* No special address pattern */ - NVMBIST_AMODE_COMPLEMENT_gc = (0x04<<4), /* Post complement address */ -} NVMBIST_AMODE_t; - -/* Command select */ -typedef enum NVMBIST_CMD_enum -{ - NVMBIST_CMD_NOCMD_gc = (0x00<<0), /* No effect */ - NVMBIST_CMD_START_gc = (0x01<<0), /* Start BIST testing */ - NVMBIST_CMD_RESTART_gc = (0x02<<0), /* Re-start BIST testing */ - NVMBIST_CMD_BREAK_gc = (0x03<<0), /* Stop BIST and go to BREAK state */ -} NVMBIST_CMD_t; - -/* Data check pattern select */ -typedef enum NVMBIST_PATTERN_enum -{ - NVMBIST_PATTERN_ZEROES_gc = (0x00<<0), /* All flash programmed */ - NVMBIST_PATTERN_CHECK_gc = (0x01<<0), /* Physical checkerboard in flash */ - NVMBIST_PATTERN_INVCHECK_gc = (0x02<<0), /* Inverse physical checkerboard in flash */ - NVMBIST_PATTERN_ONES_gc = (0x03<<0), /* All flash unprogrammed */ -} NVMBIST_PATTERN_t; - -/* FSM State select */ -typedef enum NVMBIST_STATE_enum -{ - NVMBIST_STATE_IDLE_gc = (0x00<<0), /* Reset state */ - NVMBIST_STATE_BREAK_gc = (0x01<<0), /* Break command used */ - NVMBIST_STATE_FAILED0_gc = (0x04<<0), /* Test failed, data from last address */ - NVMBIST_STATE_FAILED1_gc = (0x05<<0), /* Test failed, data from address-1 */ - NVMBIST_STATE_FAILED2_gc = (0x06<<0), /* Test failed, data from address-2 */ - NVMBIST_STATE_SUCCESS_gc = (0x07<<0), /* Test success */ - NVMBIST_STATE_START0_gc = (0x08<<0), /* Startup, fetching first data */ - NVMBIST_STATE_START1_gc = (0x09<<0), /* Startup, fetching second data */ - NVMBIST_STATE_RESTART0_gc = (0x0A<<0), /* Re-start from BREAK or FAILED2 */ - NVMBIST_STATE_RESTART1_gc = (0x0B<<0), /* Re-start from FAILED1 */ - NVMBIST_STATE_RUNNING_gc = (0x0C<<0), /* Test running */ - NVMBIST_STATE_FINISH0_gc = (0x0E<<0), /* Check last word */ - NVMBIST_STATE_FINISH1_gc = (0x0F<<0), /* Count faults in last word */ -} NVMBIST_STATE_t; - -/* X address mode select */ -typedef enum NVMBIST_XMODE_enum -{ - NVMBIST_XMODE_STATIC_gc = (0x00<<0), /* X static */ - NVMBIST_XMODE_CARRY_gc = (0x01<<0), /* Carry/borrow from Y */ - NVMBIST_XMODE_INC_gc = (0x02<<0), /* X increment each cycle */ - NVMBIST_XMODE_DEC_gc = (0x03<<0), /* X decrement each cycle */ -} NVMBIST_XMODE_t; - -/* Y address mode select */ -typedef enum NVMBIST_YMODE_enum -{ - NVMBIST_YMODE_STATIC_gc = (0x00<<2), /* Y static */ - NVMBIST_YMODE_CARRY_gc = (0x01<<2), /* Carry/borrow from X */ - NVMBIST_YMODE_INC_gc = (0x02<<2), /* Y increment each cycle */ - NVMBIST_YMODE_DEC_gc = (0x03<<2), /* Y decrement each cycle */ -} NVMBIST_YMODE_t; - -/* --------------------------------------------------------------------------- -NVMCTRL - Non-volatile Memory Controller --------------------------------------------------------------------------- -*/ - -/* Non-volatile Memory Controller */ -typedef struct NVMCTRL_struct -{ - register8_t CTRLA; /* Control A */ - register8_t CTRLB; /* Control B */ - register8_t STATUS; /* Status */ - register8_t INTCTRL; /* Interrupt Control */ - register8_t INTFLAGS; /* Interrupt Flags */ - register8_t reserved_0x05; - _WORDREGISTER(DATA); /* Data */ - _WORDREGISTER(ADDR); /* Address */ - register8_t reserved_0x0A; - register8_t reserved_0x0B; - register8_t reserved_0x0C; - register8_t reserved_0x0D; - register8_t reserved_0x0E; - register8_t reserved_0x0F; -} NVMCTRL_t; - -/* Command select */ -typedef enum NVMCTRL_CMD_enum -{ - NVMCTRL_CMD_NONE_gc = (0x00<<0), /* No Command */ - NVMCTRL_CMD_PAGEWRITE_gc = (0x01<<0), /* Write page */ - NVMCTRL_CMD_PAGEERASE_gc = (0x02<<0), /* Erase page */ - NVMCTRL_CMD_PAGEERASEWRITE_gc = (0x03<<0), /* Erase and write page */ - NVMCTRL_CMD_PAGEBUFCLR_gc = (0x04<<0), /* Page buffer clear */ - NVMCTRL_CMD_CHIPERASE_gc = (0x05<<0), /* Chip erase */ - NVMCTRL_CMD_EEERASE_gc = (0x06<<0), /* EEPROM erase */ - NVMCTRL_CMD_FUSEWRITE_gc = (0x07<<0), /* Write fuse (PDI only) */ -} NVMCTRL_CMD_t; - -/* --------------------------------------------------------------------------- -PORT - I/O Ports --------------------------------------------------------------------------- -*/ - -/* I/O Ports */ -typedef struct PORT_struct -{ - register8_t DIR; /* Data Direction */ - register8_t DIRSET; /* Data Direction Set */ - register8_t DIRCLR; /* Data Direction Clear */ - register8_t DIRTGL; /* Data Direction Toggle */ - register8_t OUT; /* Output Value */ - register8_t OUTSET; /* Output Value Set */ - register8_t OUTCLR; /* Output Value Clear */ - register8_t OUTTGL; /* Output Value Toggle */ - register8_t IN; /* Input Value */ - register8_t INTFLAGS; /* Interrupt Flags */ - register8_t PORTCTRL; /* Port Control */ - register8_t reserved_0x0B; - register8_t reserved_0x0C; - register8_t reserved_0x0D; - register8_t reserved_0x0E; - register8_t reserved_0x0F; - register8_t PIN0CTRL; /* Pin 0 Control */ - register8_t PIN1CTRL; /* Pin 1 Control */ - register8_t PIN2CTRL; /* Pin 2 Control */ - register8_t PIN3CTRL; /* Pin 3 Control */ - register8_t PIN4CTRL; /* Pin 4 Control */ - register8_t PIN5CTRL; /* Pin 5 Control */ - register8_t PIN6CTRL; /* Pin 6 Control */ - register8_t PIN7CTRL; /* Pin 7 Control */ - register8_t reserved_0x18; - register8_t reserved_0x19; - register8_t reserved_0x1A; - register8_t reserved_0x1B; - register8_t reserved_0x1C; - register8_t reserved_0x1D; - register8_t reserved_0x1E; - register8_t reserved_0x1F; -} PORT_t; - -/* Input/Sense Configuration select */ -typedef enum PORT_ISC_enum -{ - PORT_ISC_INTDISABLE_gc = (0x00<<0), /* Interrupt disabled but input buffer enabled */ - PORT_ISC_BOTHEDGES_gc = (0x01<<0), /* Sense Both Edges */ - PORT_ISC_RISING_gc = (0x02<<0), /* Sense Rising Edge */ - PORT_ISC_FALLING_gc = (0x03<<0), /* Sense Falling Edge */ - PORT_ISC_INPUT_DISABLE_gc = (0x04<<0), /* Digital Input Buffer disabled */ - PORT_ISC_LEVEL_gc = (0x05<<0), /* Sense low Level */ -} PORT_ISC_t; - -/* --------------------------------------------------------------------------- -PORTMUX - Port Multiplexer --------------------------------------------------------------------------- -*/ - -/* Port Multiplexer */ -typedef struct PORTMUX_struct -{ - register8_t EVSYSROUTEA; /* Port Multiplexer EVSYS */ - register8_t CCLROUTEA; /* Port Multiplexer CCL */ - register8_t USARTROUTEA; /* Port Multiplexer USART register A */ - register8_t TWISPIROUTEA; /* Port Multiplexer TWI and SPI */ - register8_t TCAROUTEA; /* Port Multiplexer TCA */ - register8_t TCBROUTEA; /* Port Multiplexer TCB */ - register8_t reserved_0x06; - register8_t reserved_0x07; - register8_t reserved_0x08; - register8_t reserved_0x09; - register8_t reserved_0x0A; - register8_t reserved_0x0B; - register8_t reserved_0x0C; - register8_t reserved_0x0D; - register8_t reserved_0x0E; - register8_t reserved_0x0F; -} PORTMUX_t; - -/* Port Multiplexer SPI0 select */ -typedef enum PORTMUX_SPI0_enum -{ - PORTMUX_SPI0_DEFAULT_gc = (0x00<<0), /* SPI0 on PA[7:4] */ - PORTMUX_SPI0_ALT1_gc = (0x01<<0), /* SPI0 on PC[3:0] */ - PORTMUX_SPI0_ALT2_gc = (0x02<<0), /* SPI0 on PE[3:0] */ - PORTMUX_SPI0_NONE_gc = (0x03<<0), /* Not connected to any pins */ -} PORTMUX_SPI0_t; - -/* Port Multiplexer TCA0 select */ -typedef enum PORTMUX_TCA0_enum -{ - PORTMUX_TCA0_PORTA_gc = (0x00<<0), /* TCA0 pins on PA[5:0] */ - PORTMUX_TCA0_PORTB_gc = (0x01<<0), /* TCA0 pins on PB[5:0] */ - PORTMUX_TCA0_PORTC_gc = (0x02<<0), /* TCA0 pins on PC[5:0] */ - PORTMUX_TCA0_PORTD_gc = (0x03<<0), /* TCA0 pins on PD[5:0] */ - PORTMUX_TCA0_PORTE_gc = (0x04<<0), /* TCA0 pins on PE[5:0] */ - PORTMUX_TCA0_PORTF_gc = (0x05<<0), /* TCA0 pins on PF[5:0] */ -} PORTMUX_TCA0_t; - -/* Port Multiplexer TWI0 select */ -typedef enum PORTMUX_TWI0_enum -{ - PORTMUX_TWI0_DEFAULT_gc = (0x00<<4), /* SCL/SDA on PA[3:2], Slave mode on PC[3:2] in dual TWI mode */ - PORTMUX_TWI0_ALT1_gc = (0x01<<4), /* SCL/SDA on PA[3:2], Slave mode on PF[3:2] in dual TWI mode */ - PORTMUX_TWI0_ALT2_gc = (0x02<<4), /* SCL/SDA on PC[3:2], Slave mode on PF[3:2] in dual TWI mode */ - PORTMUX_TWI0_NONE_gc = (0x03<<4), /* Not connected to any pins */ -} PORTMUX_TWI0_t; - -/* Port Multiplexer USART0 select */ -typedef enum PORTMUX_USART0_enum -{ - PORTMUX_USART0_DEFAULT_gc = (0x00<<0), /* USART0 on PA[3:0] */ - PORTMUX_USART0_ALT1_gc = (0x01<<0), /* USART0 on PA[7:4] */ - PORTMUX_USART0_NONE_gc = (0x03<<0), /* Not connected to any pins */ -} PORTMUX_USART0_t; - -/* Port Multiplexer USART1 select */ -typedef enum PORTMUX_USART1_enum -{ - PORTMUX_USART1_DEFAULT_gc = (0x00<<2), /* USART1 on PC[3:0] */ - PORTMUX_USART1_ALT1_gc = (0x01<<2), /* USART1 on PC[7:4] */ - PORTMUX_USART1_NONE_gc = (0x03<<2), /* Not connected to any pins */ -} PORTMUX_USART1_t; - -/* Port Multiplexer USART2 select */ -typedef enum PORTMUX_USART2_enum -{ - PORTMUX_USART2_DEFAULT_gc = (0x00<<4), /* USART2 on PF[3:0] */ - PORTMUX_USART2_ALT1_gc = (0x01<<4), /* USART2 on PF[5:4] */ - PORTMUX_USART2_NONE_gc = (0x03<<4), /* Not connected to any pins */ -} PORTMUX_USART2_t; - -/* Port Multiplexer USART3 select */ -typedef enum PORTMUX_USART3_enum -{ - PORTMUX_USART3_DEFAULT_gc = (0x00<<6), /* USART3 on PB[3:0] */ - PORTMUX_USART3_ALT1_gc = (0x01<<6), /* USART3 on PB[5:4] */ - PORTMUX_USART3_NONE_gc = (0x03<<6), /* Not connected to any pins */ -} PORTMUX_USART3_t; - -/* --------------------------------------------------------------------------- -RSTCTRL - Reset controller --------------------------------------------------------------------------- -*/ - -/* Reset controller */ -typedef struct RSTCTRL_struct -{ - register8_t RSTFR; /* Reset Flags */ - register8_t SWRR; /* Software Reset */ - register8_t reserved_0x02; - register8_t reserved_0x03; -} RSTCTRL_t; - - -/* --------------------------------------------------------------------------- -RTC - Real-Time Counter --------------------------------------------------------------------------- -*/ - -/* Real-Time Counter */ -typedef struct RTC_struct -{ - register8_t CTRLA; /* Control A */ - register8_t STATUS; /* Status */ - register8_t INTCTRL; /* Interrupt Control */ - register8_t INTFLAGS; /* Interrupt Flags */ - register8_t TEMP; /* Temporary */ - register8_t DBGCTRL; /* Debug control */ - register8_t reserved_0x06; - register8_t CLKSEL; /* Clock Select */ - _WORDREGISTER(CNT); /* Counter */ - _WORDREGISTER(PER); /* Period */ - _WORDREGISTER(CMP); /* Compare */ - register8_t reserved_0x0E; - register8_t reserved_0x0F; - register8_t PITCTRLA; /* PIT Control A */ - register8_t PITSTATUS; /* PIT Status */ - register8_t PITINTCTRL; /* PIT Interrupt Control */ - register8_t PITINTFLAGS; /* PIT Interrupt Flags */ - register8_t reserved_0x14; - register8_t PITDBGCTRL; /* PIT Debug control */ - register8_t reserved_0x16; - register8_t reserved_0x17; - register8_t reserved_0x18; - register8_t reserved_0x19; - register8_t reserved_0x1A; - register8_t reserved_0x1B; - register8_t reserved_0x1C; - register8_t reserved_0x1D; - register8_t reserved_0x1E; - register8_t reserved_0x1F; -} RTC_t; - -/* Clock Select select */ -typedef enum RTC_CLKSEL_enum -{ - RTC_CLKSEL_INT32K_gc = (0x00<<0), /* Internal 32kHz OSC */ - RTC_CLKSEL_INT1K_gc = (0x01<<0), /* Internal 1kHz OSC */ - RTC_CLKSEL_TOSC32K_gc = (0x02<<0), /* 32KHz Crystal OSC */ - RTC_CLKSEL_EXTCLK_gc = (0x03<<0), /* External Clock */ -} RTC_CLKSEL_t; - -/* Period select */ -typedef enum RTC_PERIOD_enum -{ - RTC_PERIOD_OFF_gc = (0x00<<3), /* Off */ - RTC_PERIOD_CYC4_gc = (0x01<<3), /* RTC Clock Cycles 4 */ - RTC_PERIOD_CYC8_gc = (0x02<<3), /* RTC Clock Cycles 8 */ - RTC_PERIOD_CYC16_gc = (0x03<<3), /* RTC Clock Cycles 16 */ - RTC_PERIOD_CYC32_gc = (0x04<<3), /* RTC Clock Cycles 32 */ - RTC_PERIOD_CYC64_gc = (0x05<<3), /* RTC Clock Cycles 64 */ - RTC_PERIOD_CYC128_gc = (0x06<<3), /* RTC Clock Cycles 128 */ - RTC_PERIOD_CYC256_gc = (0x07<<3), /* RTC Clock Cycles 256 */ - RTC_PERIOD_CYC512_gc = (0x08<<3), /* RTC Clock Cycles 512 */ - RTC_PERIOD_CYC1024_gc = (0x09<<3), /* RTC Clock Cycles 1024 */ - RTC_PERIOD_CYC2048_gc = (0x0A<<3), /* RTC Clock Cycles 2048 */ - RTC_PERIOD_CYC4096_gc = (0x0B<<3), /* RTC Clock Cycles 4096 */ - RTC_PERIOD_CYC8192_gc = (0x0C<<3), /* RTC Clock Cycles 8192 */ - RTC_PERIOD_CYC16384_gc = (0x0D<<3), /* RTC Clock Cycles 16384 */ - RTC_PERIOD_CYC32768_gc = (0x0E<<3), /* RTC Clock Cycles 32768 */ -} RTC_PERIOD_t; - -/* Prescaling Factor select */ -typedef enum RTC_PRESCALER_enum -{ - RTC_PRESCALER_DIV1_gc = (0x00<<3), /* RTC Clock / 1 */ - RTC_PRESCALER_DIV2_gc = (0x01<<3), /* RTC Clock / 2 */ - RTC_PRESCALER_DIV4_gc = (0x02<<3), /* RTC Clock / 4 */ - RTC_PRESCALER_DIV8_gc = (0x03<<3), /* RTC Clock / 8 */ - RTC_PRESCALER_DIV16_gc = (0x04<<3), /* RTC Clock / 16 */ - RTC_PRESCALER_DIV32_gc = (0x05<<3), /* RTC Clock / 32 */ - RTC_PRESCALER_DIV64_gc = (0x06<<3), /* RTC Clock / 64 */ - RTC_PRESCALER_DIV128_gc = (0x07<<3), /* RTC Clock / 128 */ - RTC_PRESCALER_DIV256_gc = (0x08<<3), /* RTC Clock / 256 */ - RTC_PRESCALER_DIV512_gc = (0x09<<3), /* RTC Clock / 512 */ - RTC_PRESCALER_DIV1024_gc = (0x0A<<3), /* RTC Clock / 1024 */ - RTC_PRESCALER_DIV2048_gc = (0x0B<<3), /* RTC Clock / 2048 */ - RTC_PRESCALER_DIV4096_gc = (0x0C<<3), /* RTC Clock / 4096 */ - RTC_PRESCALER_DIV8192_gc = (0x0D<<3), /* RTC Clock / 8192 */ - RTC_PRESCALER_DIV16384_gc = (0x0E<<3), /* RTC Clock / 16384 */ - RTC_PRESCALER_DIV32768_gc = (0x0F<<3), /* RTC Clock / 32768 */ -} RTC_PRESCALER_t; - -/* --------------------------------------------------------------------------- -SIGROW - Signature row --------------------------------------------------------------------------- -*/ - -/* Signature row */ -typedef struct SIGROW_struct -{ - register8_t DEVICEID0; /* Device ID Byte 0 */ - register8_t DEVICEID1; /* Device ID Byte 1 */ - register8_t DEVICEID2; /* Device ID Byte 2 */ - register8_t SERNUM0; /* Serial Number Byte 0 */ - register8_t SERNUM1; /* Serial Number Byte 1 */ - register8_t SERNUM2; /* Serial Number Byte 2 */ - register8_t SERNUM3; /* Serial Number Byte 3 */ - register8_t SERNUM4; /* Serial Number Byte 4 */ - register8_t SERNUM5; /* Serial Number Byte 5 */ - register8_t SERNUM6; /* Serial Number Byte 6 */ - register8_t SERNUM7; /* Serial Number Byte 7 */ - register8_t SERNUM8; /* Serial Number Byte 8 */ - register8_t SERNUM9; /* Serial Number Byte 9 */ - register8_t reserved_0x0D; - register8_t reserved_0x0E; - register8_t reserved_0x0F; - register8_t reserved_0x10; - register8_t reserved_0x11; - register8_t reserved_0x12; - register8_t reserved_0x13; - register8_t OSCCAL32K; /* Oscillator Calibration for 32kHz ULP */ - register8_t reserved_0x15; - register8_t reserved_0x16; - register8_t reserved_0x17; - register8_t OSCCAL16M0; /* Oscillator Calibration 16 MHz Byte 0 */ - register8_t OSCCAL16M1; /* Oscillator Calibration 16 MHz Byte 1 */ - register8_t OSCCAL20M0; /* Oscillator Calibration 20 MHz Byte 0 */ - register8_t OSCCAL20M1; /* Oscillator Calibration 20 MHz Byte 1 */ - register8_t reserved_0x1C; - register8_t reserved_0x1D; - register8_t reserved_0x1E; - register8_t reserved_0x1F; - register8_t TEMPSENSE0; /* Temperature Sensor Calibration Byte 0 */ - register8_t TEMPSENSE1; /* Temperature Sensor Calibration Byte 1 */ - register8_t OSC16ERR3V; /* OSC16 error at 3V */ - register8_t OSC16ERR5V; /* OSC16 error at 5V */ - register8_t OSC20ERR3V; /* OSC20 error at 3V */ - register8_t OSC20ERR5V; /* OSC20 error at 5V */ - register8_t reserved_0x26; - register8_t reserved_0x27; - register8_t reserved_0x28; - register8_t reserved_0x29; - register8_t reserved_0x2A; - register8_t reserved_0x2B; - register8_t reserved_0x2C; - register8_t reserved_0x2D; - register8_t reserved_0x2E; - register8_t CHECKSUM1; /* CRC Checksum Byte 1 */ - register8_t reserved_0x30; - register8_t reserved_0x31; - register8_t reserved_0x32; - register8_t reserved_0x33; - register8_t reserved_0x34; - register8_t reserved_0x35; - register8_t reserved_0x36; - register8_t reserved_0x37; - register8_t reserved_0x38; - register8_t reserved_0x39; - register8_t reserved_0x3A; - register8_t reserved_0x3B; - register8_t reserved_0x3C; - register8_t reserved_0x3D; - register8_t reserved_0x3E; - register8_t reserved_0x3F; -} SIGROW_t; - - -/* --------------------------------------------------------------------------- -SLPCTRL - Sleep Controller --------------------------------------------------------------------------- -*/ - -/* Sleep Controller */ -typedef struct SLPCTRL_struct -{ - register8_t CTRLA; /* Control */ - register8_t reserved_0x01; -} SLPCTRL_t; - -/* Sleep mode select */ -typedef enum SLPCTRL_SMODE_enum -{ - SLPCTRL_SMODE_IDLE_gc = (0x00<<1), /* Idle mode */ - SLPCTRL_SMODE_STDBY_gc = (0x01<<1), /* Standby Mode */ - SLPCTRL_SMODE_PDOWN_gc = (0x02<<1), /* Power-down Mode */ -} SLPCTRL_SMODE_t; - -#define SLEEP_MODE_IDLE (0x00<<1) -#define SLEEP_MODE_STANDBY (0x01<<1) -#define SLEEP_MODE_PWR_DOWN (0x02<<1) -/* --------------------------------------------------------------------------- -SPI - Serial Peripheral Interface --------------------------------------------------------------------------- -*/ - -/* Serial Peripheral Interface */ -typedef struct SPI_struct -{ - register8_t CTRLA; /* Control A */ - register8_t CTRLB; /* Control B */ - register8_t INTCTRL; /* Interrupt Control */ - register8_t INTFLAGS; /* Interrupt Flags */ - register8_t DATA; /* Data */ - register8_t reserved_0x05; - register8_t reserved_0x06; - register8_t reserved_0x07; -} SPI_t; - -/* SPI Mode select */ -typedef enum SPI_MODE_enum -{ - SPI_MODE_0_gc = (0x00<<0), /* SPI Mode 0 */ - SPI_MODE_1_gc = (0x01<<0), /* SPI Mode 1 */ - SPI_MODE_2_gc = (0x02<<0), /* SPI Mode 2 */ - SPI_MODE_3_gc = (0x03<<0), /* SPI Mode 3 */ -} SPI_MODE_t; - -/* Prescaler select */ -typedef enum SPI_PRESC_enum -{ - SPI_PRESC_DIV4_gc = (0x00<<1), /* System Clock / 4 */ - SPI_PRESC_DIV16_gc = (0x01<<1), /* System Clock / 16 */ - SPI_PRESC_DIV64_gc = (0x02<<1), /* System Clock / 64 */ - SPI_PRESC_DIV128_gc = (0x03<<1), /* System Clock / 128 */ -} SPI_PRESC_t; - -/* --------------------------------------------------------------------------- -SYSCFG - System Configuration Registers --------------------------------------------------------------------------- -*/ - -/* System Configuration Registers */ -typedef struct SYSCFG_struct -{ - register8_t reserved_0x00; - register8_t REVID; /* Revision ID */ - register8_t EXTBRK; /* External Break */ - register8_t reserved_0x03; - register8_t reserved_0x04; - register8_t reserved_0x05; - register8_t reserved_0x06; - register8_t reserved_0x07; - register8_t reserved_0x08; - register8_t reserved_0x09; - register8_t reserved_0x0A; - register8_t reserved_0x0B; - register8_t reserved_0x0C; - register8_t reserved_0x0D; - register8_t reserved_0x0E; - register8_t reserved_0x0F; - register8_t reserved_0x10; - register8_t reserved_0x11; - register8_t reserved_0x12; - register8_t reserved_0x13; - register8_t reserved_0x14; - register8_t reserved_0x15; - register8_t reserved_0x16; - register8_t reserved_0x17; - register8_t OCDM; /* OCD Message Register */ - register8_t OCDMS; /* OCD Message Status */ - register8_t reserved_0x1A; - register8_t reserved_0x1B; - register8_t reserved_0x1C; - register8_t reserved_0x1D; - register8_t reserved_0x1E; - register8_t reserved_0x1F; -} SYSCFG_t; - - -/* --------------------------------------------------------------------------- -TCA - 16-bit Timer/Counter Type A --------------------------------------------------------------------------- -*/ - -/* 16-bit Timer/Counter Type A - Single Mode */ -typedef struct TCA_SINGLE_struct -{ - register8_t CTRLA; /* Control A */ - register8_t CTRLB; /* Control B */ - register8_t CTRLC; /* Control C */ - register8_t CTRLD; /* Control D */ - register8_t CTRLECLR; /* Control E Clear */ - register8_t CTRLESET; /* Control E Set */ - register8_t CTRLFCLR; /* Control F Clear */ - register8_t CTRLFSET; /* Control F Set */ - register8_t reserved_0x08; - register8_t EVCTRL; /* Event Control */ - register8_t INTCTRL; /* Interrupt Control */ - register8_t INTFLAGS; /* Interrupt Flags */ - register8_t reserved_0x0C; - register8_t reserved_0x0D; - register8_t DBGCTRL; /* Degbug Control */ - register8_t TEMP; /* Temporary data for 16-bit Access */ - register8_t reserved_0x10; - register8_t reserved_0x11; - register8_t reserved_0x12; - register8_t reserved_0x13; - register8_t reserved_0x14; - register8_t reserved_0x15; - register8_t reserved_0x16; - register8_t reserved_0x17; - register8_t reserved_0x18; - register8_t reserved_0x19; - register8_t reserved_0x1A; - register8_t reserved_0x1B; - register8_t reserved_0x1C; - register8_t reserved_0x1D; - register8_t reserved_0x1E; - register8_t reserved_0x1F; - _WORDREGISTER(CNT); /* Count */ - register8_t reserved_0x22; - register8_t reserved_0x23; - register8_t reserved_0x24; - register8_t reserved_0x25; - _WORDREGISTER(PER); /* Period */ - _WORDREGISTER(CMP0); /* Compare 0 */ - _WORDREGISTER(CMP1); /* Compare 1 */ - _WORDREGISTER(CMP2); /* Compare 2 */ - register8_t reserved_0x2E; - register8_t reserved_0x2F; - register8_t reserved_0x30; - register8_t reserved_0x31; - register8_t reserved_0x32; - register8_t reserved_0x33; - register8_t reserved_0x34; - register8_t reserved_0x35; - _WORDREGISTER(PERBUF); /* Period Buffer */ - _WORDREGISTER(CMP0BUF); /* Compare 0 Buffer */ - _WORDREGISTER(CMP1BUF); /* Compare 1 Buffer */ - _WORDREGISTER(CMP2BUF); /* Compare 2 Buffer */ - register8_t reserved_0x3E; - register8_t reserved_0x3F; -} TCA_SINGLE_t; - - -/* 16-bit Timer/Counter Type A - Split Mode */ -typedef struct TCA_SPLIT_struct -{ - register8_t CTRLA; /* Control A */ - register8_t CTRLB; /* Control B */ - register8_t CTRLC; /* Control C */ - register8_t CTRLD; /* Control D */ - register8_t CTRLECLR; /* Control E Clear */ - register8_t CTRLESET; /* Control E Set */ - register8_t reserved_0x06; - register8_t reserved_0x07; - register8_t reserved_0x08; - register8_t reserved_0x09; - register8_t INTCTRL; /* Interrupt Control */ - register8_t INTFLAGS; /* Interrupt Flags */ - register8_t reserved_0x0C; - register8_t reserved_0x0D; - register8_t DBGCTRL; /* Degbug Control */ - register8_t reserved_0x0F; - register8_t reserved_0x10; - register8_t reserved_0x11; - register8_t reserved_0x12; - register8_t reserved_0x13; - register8_t reserved_0x14; - register8_t reserved_0x15; - register8_t reserved_0x16; - register8_t reserved_0x17; - register8_t reserved_0x18; - register8_t reserved_0x19; - register8_t reserved_0x1A; - register8_t reserved_0x1B; - register8_t reserved_0x1C; - register8_t reserved_0x1D; - register8_t reserved_0x1E; - register8_t reserved_0x1F; - register8_t LCNT; /* Low Count */ - register8_t HCNT; /* High Count */ - register8_t reserved_0x22; - register8_t reserved_0x23; - register8_t reserved_0x24; - register8_t reserved_0x25; - register8_t LPER; /* Low Period */ - register8_t HPER; /* High Period */ - register8_t LCMP0; /* Low Compare */ - register8_t HCMP0; /* High Compare */ - register8_t LCMP1; /* Low Compare */ - register8_t HCMP1; /* High Compare */ - register8_t LCMP2; /* Low Compare */ - register8_t HCMP2; /* High Compare */ - register8_t reserved_0x2E; - register8_t reserved_0x2F; - register8_t reserved_0x30; - register8_t reserved_0x31; - register8_t reserved_0x32; - register8_t reserved_0x33; - register8_t reserved_0x34; - register8_t reserved_0x35; - register8_t reserved_0x36; - register8_t reserved_0x37; - register8_t reserved_0x38; - register8_t reserved_0x39; - register8_t reserved_0x3A; - register8_t reserved_0x3B; - register8_t reserved_0x3C; - register8_t reserved_0x3D; - register8_t reserved_0x3E; - register8_t reserved_0x3F; -} TCA_SPLIT_t; - - -/* 16-bit Timer/Counter Type A */ -typedef union TCA_union -{ - TCA_SINGLE_t SINGLE; /* 16-bit Timer/Counter Type A - Single Mode */ - TCA_SPLIT_t SPLIT; /* 16-bit Timer/Counter Type A - Split Mode */ -} TCA_t; - -/* Clock Selection select */ -typedef enum TCA_SINGLE_CLKSEL_enum -{ - TCA_SINGLE_CLKSEL_DIV1_gc = (0x00<<1), /* System Clock */ - TCA_SINGLE_CLKSEL_DIV2_gc = (0x01<<1), /* System Clock / 2 */ - TCA_SINGLE_CLKSEL_DIV4_gc = (0x02<<1), /* System Clock / 4 */ - TCA_SINGLE_CLKSEL_DIV8_gc = (0x03<<1), /* System Clock / 8 */ - TCA_SINGLE_CLKSEL_DIV16_gc = (0x04<<1), /* System Clock / 16 */ - TCA_SINGLE_CLKSEL_DIV64_gc = (0x05<<1), /* System Clock / 64 */ - TCA_SINGLE_CLKSEL_DIV256_gc = (0x06<<1), /* System Clock / 256 */ - TCA_SINGLE_CLKSEL_DIV1024_gc = (0x07<<1), /* System Clock / 1024 */ -} TCA_SINGLE_CLKSEL_t; - -/* Command select */ -typedef enum TCA_SINGLE_CMD_enum -{ - TCA_SINGLE_CMD_NONE_gc = (0x00<<2), /* No Command */ - TCA_SINGLE_CMD_UPDATE_gc = (0x01<<2), /* Force Update */ - TCA_SINGLE_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ - TCA_SINGLE_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ -} TCA_SINGLE_CMD_t; - -/* Direction select */ -typedef enum TCA_SINGLE_DIR_enum -{ - TCA_SINGLE_DIR_UP_gc = (0x00<<0), /* Count up */ - TCA_SINGLE_DIR_DOWN_gc = (0x01<<0), /* Count down */ -} TCA_SINGLE_DIR_t; - -/* Event Action select */ -typedef enum TCA_SINGLE_EVACT_enum -{ - TCA_SINGLE_EVACT_POSEDGE_gc = (0x00<<1), /* Count on positive edge event */ - TCA_SINGLE_EVACT_ANYEDGE_gc = (0x01<<1), /* Count on any edge event */ - TCA_SINGLE_EVACT_HIGHLVL_gc = (0x02<<1), /* Count on prescaled clock while event line is 1. */ - TCA_SINGLE_EVACT_UPDOWN_gc = (0x03<<1), /* Count on prescaled clock. Event controls count direction. Up-count when event line is 0, down-count when event line is 1. */ -} TCA_SINGLE_EVACT_t; - -/* Waveform generation mode select */ -typedef enum TCA_SINGLE_WGMODE_enum -{ - TCA_SINGLE_WGMODE_NORMAL_gc = (0x00<<0), /* Normal Mode */ - TCA_SINGLE_WGMODE_FRQ_gc = (0x01<<0), /* Frequency Generation Mode */ - TCA_SINGLE_WGMODE_SINGLESLOPE_gc = (0x03<<0), /* Single Slope PWM */ - TCA_SINGLE_WGMODE_DSTOP_gc = (0x05<<0), /* Dual Slope PWM, overflow on TOP */ - TCA_SINGLE_WGMODE_DSBOTH_gc = (0x06<<0), /* Dual Slope PWM, overflow on TOP and BOTTOM */ - TCA_SINGLE_WGMODE_DSBOTTOM_gc = (0x07<<0), /* Dual Slope PWM, overflow on BOTTOM */ -} TCA_SINGLE_WGMODE_t; - -/* Clock Selection select */ -typedef enum TCA_SPLIT_CLKSEL_enum -{ - TCA_SPLIT_CLKSEL_DIV1_gc = (0x00<<1), /* System Clock */ - TCA_SPLIT_CLKSEL_DIV2_gc = (0x01<<1), /* System Clock / 2 */ - TCA_SPLIT_CLKSEL_DIV4_gc = (0x02<<1), /* System Clock / 4 */ - TCA_SPLIT_CLKSEL_DIV8_gc = (0x03<<1), /* System Clock / 8 */ - TCA_SPLIT_CLKSEL_DIV16_gc = (0x04<<1), /* System Clock / 16 */ - TCA_SPLIT_CLKSEL_DIV64_gc = (0x05<<1), /* System Clock / 64 */ - TCA_SPLIT_CLKSEL_DIV256_gc = (0x06<<1), /* System Clock / 256 */ - TCA_SPLIT_CLKSEL_DIV1024_gc = (0x07<<1), /* System Clock / 1024 */ -} TCA_SPLIT_CLKSEL_t; - -/* Command select */ -typedef enum TCA_SPLIT_CMD_enum -{ - TCA_SPLIT_CMD_NONE_gc = (0x00<<2), /* No Command */ - TCA_SPLIT_CMD_UPDATE_gc = (0x01<<2), /* Force Update */ - TCA_SPLIT_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ - TCA_SPLIT_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ -} TCA_SPLIT_CMD_t; - -/* --------------------------------------------------------------------------- -TCB - 16-bit Timer Type B --------------------------------------------------------------------------- -*/ - -/* 16-bit Timer Type B */ -typedef struct TCB_struct -{ - register8_t CTRLA; /* Control A */ - register8_t CTRLB; /* Control Register B */ - register8_t reserved_0x02; - register8_t reserved_0x03; - register8_t EVCTRL; /* Event Control */ - register8_t INTCTRL; /* Interrupt Control */ - register8_t INTFLAGS; /* Interrupt Flags */ - register8_t STATUS; /* Status */ - register8_t DBGCTRL; /* Debug Control */ - register8_t TEMP; /* Temporary Value */ - _WORDREGISTER(CNT); /* Count */ - _WORDREGISTER(CCMP); /* Compare or Capture */ - register8_t reserved_0x0E; - register8_t reserved_0x0F; -} TCB_t; - -/* Clock Select select */ -typedef enum TCB_CLKSEL_enum -{ - TCB_CLKSEL_CLKDIV1_gc = (0x00<<1), /* CLK_PER (No Prescaling) */ - TCB_CLKSEL_CLKDIV2_gc = (0x01<<1), /* CLK_PER/2 (From Prescaler) */ - TCB_CLKSEL_CLKTCA_gc = (0x02<<1), /* Use Clock from TCA */ -} TCB_CLKSEL_t; - -/* Timer Mode select */ -typedef enum TCB_CNTMODE_enum -{ - TCB_CNTMODE_INT_gc = (0x00<<0), /* Periodic Interrupt */ - TCB_CNTMODE_TIMEOUT_gc = (0x01<<0), /* Periodic Timeout */ - TCB_CNTMODE_CAPT_gc = (0x02<<0), /* Input Capture Event */ - TCB_CNTMODE_FRQ_gc = (0x03<<0), /* Input Capture Frequency measurement */ - TCB_CNTMODE_PW_gc = (0x04<<0), /* Input Capture Pulse-Width measurement */ - TCB_CNTMODE_FRQPW_gc = (0x05<<0), /* Input Capture Frequency and Pulse-Width measurement */ - TCB_CNTMODE_SINGLE_gc = (0x06<<0), /* Single Shot */ - TCB_CNTMODE_PWM8_gc = (0x07<<0), /* 8-bit PWM */ -} TCB_CNTMODE_t; - -/* --------------------------------------------------------------------------- -TWI - Two-Wire Interface --------------------------------------------------------------------------- -*/ - -/* Two-Wire Interface */ -typedef struct TWI_struct -{ - register8_t CTRLA; /* Control A */ - register8_t BRIDGECTRL; /* Bridge Control */ - register8_t DBGCTRL; /* Debug Control Register */ - register8_t MCTRLA; /* Master Control A */ - register8_t MCTRLB; /* Master Control B */ - register8_t MSTATUS; /* Master Status */ - register8_t MBAUD; /* Master Baurd Rate Control */ - register8_t MADDR; /* Master Address */ - register8_t MDATA; /* Master Data */ - register8_t SCTRLA; /* Slave Control A */ - register8_t SCTRLB; /* Slave Control B */ - register8_t SSTATUS; /* Slave Status */ - register8_t SADDR; /* Slave Address */ - register8_t SDATA; /* Slave Data */ - register8_t SADDRMASK; /* Slave Address Mask */ - register8_t reserved_0x0F; -} TWI_t; - -/* Acknowledge Action select */ -typedef enum TWI_ACKACT_enum -{ - TWI_ACKACT_ACK_gc = (0x00<<2), /* Send ACK */ - TWI_ACKACT_NACK_gc = (0x01<<2), /* Send NACK */ -} TWI_ACKACT_t; - -/* Slave Address or Stop select */ -typedef enum TWI_AP_enum -{ - TWI_AP_STOP_gc = (0x00<<0), /* Stop condition generated APIF */ - TWI_AP_ADR_gc = (0x01<<0), /* Address detection generated APIF */ -} TWI_AP_t; - -/* Bus State select */ -typedef enum TWI_BUSSTATE_enum -{ - TWI_BUSSTATE_UNKNOWN_gc = (0x00<<0), /* Unknown Bus State */ - TWI_BUSSTATE_IDLE_gc = (0x01<<0), /* Bus is Idle */ - TWI_BUSSTATE_OWNER_gc = (0x02<<0), /* This Module Controls The Bus */ - TWI_BUSSTATE_BUSY_gc = (0x03<<0), /* The Bus is Busy */ -} TWI_BUSSTATE_t; - -/* Command select */ -typedef enum TWI_MCMD_enum -{ - TWI_MCMD_NOACT_gc = (0x00<<0), /* No Action */ - TWI_MCMD_REPSTART_gc = (0x01<<0), /* Issue Repeated Start Condition */ - TWI_MCMD_RECVTRANS_gc = (0x02<<0), /* Receive or Transmit Data, depending on DIR */ - TWI_MCMD_STOP_gc = (0x03<<0), /* Issue Stop Condition */ -} TWI_MCMD_t; - -/* Command select */ -typedef enum TWI_SCMD_enum -{ - TWI_SCMD_NOACT_gc = (0x00<<0), /* No Action */ - TWI_SCMD_COMPTRANS_gc = (0x02<<0), /* Used To Complete a Transaction */ - TWI_SCMD_RESPONSE_gc = (0x03<<0), /* Used in Response to Address/Data Interrupt */ -} TWI_SCMD_t; - -/* SDA Hold Time select */ -typedef enum TWI_SDAHOLD_enum -{ - TWI_SDAHOLD_OFF_gc = (0x00<<2), /* SDA hold time off */ - TWI_SDAHOLD_50NS_gc = (0x01<<2), /* Typical 50ns hold time */ - TWI_SDAHOLD_300NS_gc = (0x02<<2), /* Typical 300ns hold time */ - TWI_SDAHOLD_500NS_gc = (0x03<<2), /* Typical 500ns hold time */ -} TWI_SDAHOLD_t; - -/* SDA Setup Time select */ -typedef enum TWI_SDASETUP_enum -{ - TWI_SDASETUP_4CYC_gc = (0x00<<4), /* SDA setup time is 4 clock cycles */ - TWI_SDASETUP_8CYC_gc = (0x01<<4), /* SDA setup time is 8 clock cycles */ -} TWI_SDASETUP_t; - -/* Inactive Bus Timeout select */ -typedef enum TWI_TIMEOUT_enum -{ - TWI_TIMEOUT_DISABLED_gc = (0x00<<2), /* Bus Timeout Disabled */ - TWI_TIMEOUT_50US_gc = (0x01<<2), /* 50 Microseconds */ - TWI_TIMEOUT_100US_gc = (0x02<<2), /* 100 Microseconds */ - TWI_TIMEOUT_200US_gc = (0x03<<2), /* 200 Microseconds */ -} TWI_TIMEOUT_t; - -/* --------------------------------------------------------------------------- -USART - Universal Synchronous and Asynchronous Receiver and Transmitter --------------------------------------------------------------------------- -*/ - -/* Universal Synchronous and Asynchronous Receiver and Transmitter */ -typedef struct USART_struct -{ - register8_t RXDATAL; /* Receive Data Low Byte */ - register8_t RXDATAH; /* Receive Data High Byte */ - register8_t TXDATAL; /* Transmit Data Low Byte */ - register8_t TXDATAH; /* Transmit Data High Byte */ - register8_t STATUS; /* Status */ - register8_t CTRLA; /* Control A */ - register8_t CTRLB; /* Control B */ - register8_t CTRLC; /* Control C */ - _WORDREGISTER(BAUD); /* Baud Rate */ - register8_t CTRLD; /* Control D */ - register8_t DBGCTRL; /* Debug Control */ - register8_t EVCTRL; /* Event Control */ - register8_t TXPLCTRL; /* IRCOM Transmitter Pulse Length Control */ - register8_t RXPLCTRL; /* IRCOM Receiver Pulse Length Control */ - register8_t reserved_0x0F; -} USART_t; - -/* Character Size select */ -typedef enum USART_CHSIZE_enum -{ - USART_CHSIZE_5BIT_gc = (0x00<<0), /* Character size: 5 bit */ - USART_CHSIZE_6BIT_gc = (0x01<<0), /* Character size: 6 bit */ - USART_CHSIZE_7BIT_gc = (0x02<<0), /* Character size: 7 bit */ - USART_CHSIZE_8BIT_gc = (0x03<<0), /* Character size: 8 bit */ - USART_CHSIZE_9BITL_gc = (0x06<<0), /* Character size: 9 bit read low byte first */ - USART_CHSIZE_9BITH_gc = (0x07<<0), /* Character size: 9 bit read high byte first */ -} USART_CHSIZE_t; - -/* Communication Mode select */ -typedef enum USART_CMODE_enum -{ - USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6), /* Asynchronous Mode */ - USART_CMODE_SYNCHRONOUS_gc = (0x01<<6), /* Synchronous Mode */ - USART_CMODE_IRCOM_gc = (0x02<<6), /* Infrared Communication */ - USART_CMODE_MSPI_gc = (0x03<<6), /* Master SPI Mode */ -} USART_CMODE_t; - -/* Parity Mode select */ -typedef enum USART_PMODE_enum -{ - USART_PMODE_DISABLED_gc = (0x00<<4), /* No Parity */ - USART_PMODE_EVEN_gc = (0x02<<4), /* Even Parity */ - USART_PMODE_ODD_gc = (0x03<<4), /* Odd Parity */ -} USART_PMODE_t; - -/* RS485 Mode internal transmitter select */ -typedef enum USART_RS485_enum -{ - USART_RS485_OFF_gc = (0x00<<0), /* RS485 Mode disabled */ - USART_RS485_EXT_gc = (0x01<<0), /* RS485 Mode External drive */ - USART_RS485_INT_gc = (0x02<<0), /* RS485 Mode Internal drive */ -} USART_RS485_t; - -/* Receiver Mode select */ -typedef enum USART_RXMODE_enum -{ - USART_RXMODE_NORMAL_gc = (0x00<<1), /* Normal mode */ - USART_RXMODE_CLK2X_gc = (0x01<<1), /* CLK2x mode */ - USART_RXMODE_GENAUTO_gc = (0x02<<1), /* Generic autobaud mode */ - USART_RXMODE_LINAUTO_gc = (0x03<<1), /* LIN constrained autobaud mode */ -} USART_RXMODE_t; - -/* Stop Bit Mode select */ -typedef enum USART_SBMODE_enum -{ - USART_SBMODE_1BIT_gc = (0x00<<3), /* 1 stop bit */ - USART_SBMODE_2BIT_gc = (0x01<<3), /* 2 stop bits */ -} USART_SBMODE_t; - -/* --------------------------------------------------------------------------- -USERROW - User Row --------------------------------------------------------------------------- -*/ - -/* User Row */ -typedef struct USERROW_struct -{ - register8_t USERROW0; /* User Row Byte 0 */ - register8_t USERROW1; /* User Row Byte 1 */ - register8_t USERROW2; /* User Row Byte 2 */ - register8_t USERROW3; /* User Row Byte 3 */ - register8_t USERROW4; /* User Row Byte 4 */ - register8_t USERROW5; /* User Row Byte 5 */ - register8_t USERROW6; /* User Row Byte 6 */ - register8_t USERROW7; /* User Row Byte 7 */ - register8_t USERROW8; /* User Row Byte 8 */ - register8_t USERROW9; /* User Row Byte 9 */ - register8_t USERROW10; /* User Row Byte 10 */ - register8_t USERROW11; /* User Row Byte 11 */ - register8_t USERROW12; /* User Row Byte 12 */ - register8_t USERROW13; /* User Row Byte 13 */ - register8_t USERROW14; /* User Row Byte 14 */ - register8_t USERROW15; /* User Row Byte 15 */ - register8_t USERROW16; /* User Row Byte 16 */ - register8_t USERROW17; /* User Row Byte 17 */ - register8_t USERROW18; /* User Row Byte 18 */ - register8_t USERROW19; /* User Row Byte 19 */ - register8_t USERROW20; /* User Row Byte 20 */ - register8_t USERROW21; /* User Row Byte 21 */ - register8_t USERROW22; /* User Row Byte 22 */ - register8_t USERROW23; /* User Row Byte 23 */ - register8_t USERROW24; /* User Row Byte 24 */ - register8_t USERROW25; /* User Row Byte 25 */ - register8_t USERROW26; /* User Row Byte 26 */ - register8_t USERROW27; /* User Row Byte 27 */ - register8_t USERROW28; /* User Row Byte 28 */ - register8_t USERROW29; /* User Row Byte 29 */ - register8_t USERROW30; /* User Row Byte 30 */ - register8_t USERROW31; /* User Row Byte 31 */ - register8_t USERROW32; /* User Row Byte 32 */ - register8_t USERROW33; /* User Row Byte 33 */ - register8_t USERROW34; /* User Row Byte 34 */ - register8_t USERROW35; /* User Row Byte 35 */ - register8_t USERROW36; /* User Row Byte 36 */ - register8_t USERROW37; /* User Row Byte 37 */ - register8_t USERROW38; /* User Row Byte 38 */ - register8_t USERROW39; /* User Row Byte 39 */ - register8_t USERROW40; /* User Row Byte 40 */ - register8_t USERROW41; /* User Row Byte 41 */ - register8_t USERROW42; /* User Row Byte 42 */ - register8_t USERROW43; /* User Row Byte 43 */ - register8_t USERROW44; /* User Row Byte 44 */ - register8_t USERROW45; /* User Row Byte 45 */ - register8_t USERROW46; /* User Row Byte 46 */ - register8_t USERROW47; /* User Row Byte 47 */ - register8_t USERROW48; /* User Row Byte 48 */ - register8_t USERROW49; /* User Row Byte 49 */ - register8_t USERROW50; /* User Row Byte 50 */ - register8_t USERROW51; /* User Row Byte 51 */ - register8_t USERROW52; /* User Row Byte 52 */ - register8_t USERROW53; /* User Row Byte 53 */ - register8_t USERROW54; /* User Row Byte 54 */ - register8_t USERROW55; /* User Row Byte 55 */ - register8_t USERROW56; /* User Row Byte 56 */ - register8_t USERROW57; /* User Row Byte 57 */ - register8_t USERROW58; /* User Row Byte 58 */ - register8_t USERROW59; /* User Row Byte 59 */ - register8_t USERROW60; /* User Row Byte 60 */ - register8_t USERROW61; /* User Row Byte 61 */ - register8_t USERROW62; /* User Row Byte 62 */ - register8_t USERROW63; /* User Row Byte 63 */ -} USERROW_t; - - -/* --------------------------------------------------------------------------- -VPORT - Virtual Ports --------------------------------------------------------------------------- -*/ - -/* Virtual Ports */ -typedef struct VPORT_struct -{ - register8_t DIR; /* Data Direction */ - register8_t OUT; /* Output Value */ - register8_t IN; /* Input Value */ - register8_t INTFLAGS; /* Interrupt Flags */ -} VPORT_t; - - -/* --------------------------------------------------------------------------- -VREF - Voltage reference --------------------------------------------------------------------------- -*/ - -/* Voltage reference */ -typedef struct VREF_struct -{ - register8_t CTRLA; /* Control A */ - register8_t CTRLB; /* Control B */ -} VREF_t; - -/* AC0 reference select select */ -typedef enum VREF_AC0REFSEL_enum -{ - VREF_AC0REFSEL_0V55_gc = (0x00<<0), /* Voltage reference at 0.55V */ - VREF_AC0REFSEL_1V1_gc = (0x01<<0), /* Voltage reference at 1.1V */ - VREF_AC0REFSEL_2V5_gc = (0x02<<0), /* Voltage reference at 2.5V */ - VREF_AC0REFSEL_4V34_gc = (0x03<<0), /* Voltage reference at 4.34V */ - VREF_AC0REFSEL_1V5_gc = (0x04<<0), /* Voltage reference at 1.5V */ -} VREF_AC0REFSEL_t; - -/* ADC0 reference select select */ -typedef enum VREF_ADC0REFSEL_enum -{ - VREF_ADC0REFSEL_0V55_gc = (0x00<<4), /* Voltage reference at 0.55V */ - VREF_ADC0REFSEL_1V1_gc = (0x01<<4), /* Voltage reference at 1.1V */ - VREF_ADC0REFSEL_2V5_gc = (0x02<<4), /* Voltage reference at 2.5V */ - VREF_ADC0REFSEL_4V34_gc = (0x03<<4), /* Voltage reference at 4.34V */ - VREF_ADC0REFSEL_1V5_gc = (0x04<<4), /* Voltage reference at 1.5V */ -} VREF_ADC0REFSEL_t; - -/* --------------------------------------------------------------------------- -WDT - Watch-Dog Timer --------------------------------------------------------------------------- -*/ - -/* Watch-Dog Timer */ -typedef struct WDT_struct -{ - register8_t CTRLA; /* Control A */ - register8_t STATUS; /* Status */ -} WDT_t; - -/* Period select */ -typedef enum WDT_PERIOD_enum -{ - WDT_PERIOD_OFF_gc = (0x00<<0), /* Off */ - WDT_PERIOD_8CLK_gc = (0x01<<0), /* 8 cycles (8ms) */ - WDT_PERIOD_16CLK_gc = (0x02<<0), /* 16 cycles (16ms) */ - WDT_PERIOD_32CLK_gc = (0x03<<0), /* 32 cycles (32ms) */ - WDT_PERIOD_64CLK_gc = (0x04<<0), /* 64 cycles (64ms) */ - WDT_PERIOD_128CLK_gc = (0x05<<0), /* 128 cycles (0.128s) */ - WDT_PERIOD_256CLK_gc = (0x06<<0), /* 256 cycles (0.256s) */ - WDT_PERIOD_512CLK_gc = (0x07<<0), /* 512 cycles (0.512s) */ - WDT_PERIOD_1KCLK_gc = (0x08<<0), /* 1K cycles (1.0s) */ - WDT_PERIOD_2KCLK_gc = (0x09<<0), /* 2K cycles (2.0s) */ - WDT_PERIOD_4KCLK_gc = (0x0A<<0), /* 4K cycles (4.1s) */ - WDT_PERIOD_8KCLK_gc = (0x0B<<0), /* 8K cycles (8.2s) */ -} WDT_PERIOD_t; - -/* Window select */ -typedef enum WDT_WINDOW_enum -{ - WDT_WINDOW_OFF_gc = (0x00<<4), /* Off */ - WDT_WINDOW_8CLK_gc = (0x01<<4), /* 8 cycles (8ms) */ - WDT_WINDOW_16CLK_gc = (0x02<<4), /* 16 cycles (16ms) */ - WDT_WINDOW_32CLK_gc = (0x03<<4), /* 32 cycles (32ms) */ - WDT_WINDOW_64CLK_gc = (0x04<<4), /* 64 cycles (64ms) */ - WDT_WINDOW_128CLK_gc = (0x05<<4), /* 128 cycles (0.128s) */ - WDT_WINDOW_256CLK_gc = (0x06<<4), /* 256 cycles (0.256s) */ - WDT_WINDOW_512CLK_gc = (0x07<<4), /* 512 cycles (0.512s) */ - WDT_WINDOW_1KCLK_gc = (0x08<<4), /* 1K cycles (1.0s) */ - WDT_WINDOW_2KCLK_gc = (0x09<<4), /* 2K cycles (2.0s) */ - WDT_WINDOW_4KCLK_gc = (0x0A<<4), /* 4K cycles (4.1s) */ - WDT_WINDOW_8KCLK_gc = (0x0B<<4), /* 8K cycles (8.2s) */ -} WDT_WINDOW_t; -/* -========================================================================== -IO Module Instances. Mapped to memory. -========================================================================== -*/ - -#define VPORTA (*(VPORT_t *) 0x0000) /* Virtual Ports */ -#define VPORTB (*(VPORT_t *) 0x0004) /* Virtual Ports */ -#define VPORTC (*(VPORT_t *) 0x0008) /* Virtual Ports */ -#define VPORTD (*(VPORT_t *) 0x000C) /* Virtual Ports */ -#define VPORTE (*(VPORT_t *) 0x0010) /* Virtual Ports */ -#define VPORTF (*(VPORT_t *) 0x0014) /* Virtual Ports */ -#define RSTCTRL (*(RSTCTRL_t *) 0x0040) /* Reset controller */ -#define SLPCTRL (*(SLPCTRL_t *) 0x0050) /* Sleep Controller */ -#define CLKCTRL (*(CLKCTRL_t *) 0x0060) /* Clock controller */ -#define BOD (*(BOD_t *) 0x0080) /* Bod interface */ -#define VREF (*(VREF_t *) 0x00A0) /* Voltage reference */ -#define NVMBIST (*(NVMBIST_t *) 0x00C0) /* BIST in the NVMCTRL module */ -#define WDT (*(WDT_t *) 0x0100) /* Watch-Dog Timer */ -#define CPUINT (*(CPUINT_t *) 0x0110) /* Interrupt Controller */ -#define CRCSCAN (*(CRCSCAN_t *) 0x0120) /* CRCSCAN */ -#define RTC (*(RTC_t *) 0x0140) /* Real-Time Counter */ -#define EVSYS (*(EVSYS_t *) 0x0180) /* Event System */ -#define CCL (*(CCL_t *) 0x01C0) /* Configurable Custom Logic */ -#define PORTA (*(PORT_t *) 0x0400) /* I/O Ports */ -#define PORTB (*(PORT_t *) 0x0420) /* I/O Ports */ -#define PORTC (*(PORT_t *) 0x0440) /* I/O Ports */ -#define PORTD (*(PORT_t *) 0x0460) /* I/O Ports */ -#define PORTE (*(PORT_t *) 0x0480) /* I/O Ports */ -#define PORTF (*(PORT_t *) 0x04A0) /* I/O Ports */ -#define PORTMUX (*(PORTMUX_t *) 0x05E0) /* Port Multiplexer */ -#define ADC0 (*(ADC_t *) 0x0600) /* Analog to Digital Converter */ -#define AC0 (*(AC_t *) 0x0680) /* Analog Comparator */ -#define USART0 (*(USART_t *) 0x0800) /* Universal Synchronous and Asynchronous Receiver and Transmitter */ -#define USART1 (*(USART_t *) 0x0820) /* Universal Synchronous and Asynchronous Receiver and Transmitter */ -#define USART2 (*(USART_t *) 0x0840) /* Universal Synchronous and Asynchronous Receiver and Transmitter */ -#define USART3 (*(USART_t *) 0x0860) /* Universal Synchronous and Asynchronous Receiver and Transmitter */ -#define TWI0 (*(TWI_t *) 0x08A0) /* Two-Wire Interface */ -#define SPI0 (*(SPI_t *) 0x08C0) /* Serial Peripheral Interface */ -#define TCA0 (*(TCA_t *) 0x0A00) /* 16-bit Timer/Counter Type A */ -#define TCB0 (*(TCB_t *) 0x0A80) /* 16-bit Timer Type B */ -#define TCB1 (*(TCB_t *) 0x0A90) /* 16-bit Timer Type B */ -#define TCB2 (*(TCB_t *) 0x0AA0) /* 16-bit Timer Type B */ -#define TCB3 (*(TCB_t *) 0x0AB0) /* 16-bit Timer Type B */ -#define SYSCFG (*(SYSCFG_t *) 0x0F00) /* System Configuration Registers */ -#define NVMCTRL (*(NVMCTRL_t *) 0x1000) /* Non-volatile Memory Controller */ -#define SIGROW (*(SIGROW_t *) 0x1100) /* Signature row */ -#define FUSE (*(FUSE_t *) 0x1280) /* Fuses */ -#define LOCKBIT (*(LOCKBIT_t *) 0x128A) /* Lockbit */ -#define USERROW (*(USERROW_t *) 0x1300) /* User Row */ - -#endif /* !defined (__ASSEMBLER__) */ - - -/* ========== Flattened fully qualified IO register names ========== */ - - -/* VPORT (VPORTA) - Virtual Ports */ -#define VPORTA_DIR _SFR_MEM8(0x0000) -#define VPORTA_OUT _SFR_MEM8(0x0001) -#define VPORTA_IN _SFR_MEM8(0x0002) -#define VPORTA_INTFLAGS _SFR_MEM8(0x0003) - - -/* VPORT (VPORTB) - Virtual Ports */ -#define VPORTB_DIR _SFR_MEM8(0x0004) -#define VPORTB_OUT _SFR_MEM8(0x0005) -#define VPORTB_IN _SFR_MEM8(0x0006) -#define VPORTB_INTFLAGS _SFR_MEM8(0x0007) - - -/* VPORT (VPORTC) - Virtual Ports */ -#define VPORTC_DIR _SFR_MEM8(0x0008) -#define VPORTC_OUT _SFR_MEM8(0x0009) -#define VPORTC_IN _SFR_MEM8(0x000A) -#define VPORTC_INTFLAGS _SFR_MEM8(0x000B) - - -/* VPORT (VPORTD) - Virtual Ports */ -#define VPORTD_DIR _SFR_MEM8(0x000C) -#define VPORTD_OUT _SFR_MEM8(0x000D) -#define VPORTD_IN _SFR_MEM8(0x000E) -#define VPORTD_INTFLAGS _SFR_MEM8(0x000F) - - -/* VPORT (VPORTE) - Virtual Ports */ -#define VPORTE_DIR _SFR_MEM8(0x0010) -#define VPORTE_OUT _SFR_MEM8(0x0011) -#define VPORTE_IN _SFR_MEM8(0x0012) -#define VPORTE_INTFLAGS _SFR_MEM8(0x0013) - - -/* VPORT (VPORTF) - Virtual Ports */ -#define VPORTF_DIR _SFR_MEM8(0x0014) -#define VPORTF_OUT _SFR_MEM8(0x0015) -#define VPORTF_IN _SFR_MEM8(0x0016) -#define VPORTF_INTFLAGS _SFR_MEM8(0x0017) - - -/* GPIO - General Purpose IO */ -#define GPIO_GPIOR0 _SFR_MEM8(0x001C) -#define GPIO_GPIOR1 _SFR_MEM8(0x001D) -#define GPIO_GPIOR2 _SFR_MEM8(0x001E) -#define GPIO_GPIOR3 _SFR_MEM8(0x001F) - - -/* Deprecated */ -#define GPIO_GPIO0 _SFR_MEM8(0x001C) -#define GPIO_GPIO1 _SFR_MEM8(0x001D) -#define GPIO_GPIO2 _SFR_MEM8(0x001E) -#define GPIO_GPIO3 _SFR_MEM8(0x001F) - - -/* CPU - CPU */ -#define CPU_CCP _SFR_MEM8(0x0034) -#define CPU_RAMPZ _SFR_MEM8(0x003B) -#define CPU_SPL _SFR_MEM8(0x003D) -#define CPU_SPH _SFR_MEM8(0x003E) -#define CPU_SREG _SFR_MEM8(0x003F) - - -/* RSTCTRL - Reset controller */ -#define RSTCTRL_RSTFR _SFR_MEM8(0x0040) -#define RSTCTRL_SWRR _SFR_MEM8(0x0041) - - -/* SLPCTRL - Sleep Controller */ -#define SLPCTRL_CTRLA _SFR_MEM8(0x0050) - - -/* CLKCTRL - Clock controller */ -#define CLKCTRL_MCLKCTRLA _SFR_MEM8(0x0060) -#define CLKCTRL_MCLKCTRLB _SFR_MEM8(0x0061) -#define CLKCTRL_MCLKLOCK _SFR_MEM8(0x0062) -#define CLKCTRL_MCLKSTATUS _SFR_MEM8(0x0063) -#define CLKCTRL_OSC20MCTRLA _SFR_MEM8(0x0070) -#define CLKCTRL_OSC20MCALIBA _SFR_MEM8(0x0071) -#define CLKCTRL_OSC20MCALIBB _SFR_MEM8(0x0072) -#define CLKCTRL_OSC32KCTRLA _SFR_MEM8(0x0078) -#define CLKCTRL_OSC32KCALIB _SFR_MEM8(0x0079) -#define CLKCTRL_XOSC32KCTRLA _SFR_MEM8(0x007C) - - -/* BOD - Bod interface */ -#define BOD_CTRLA _SFR_MEM8(0x0080) -#define BOD_CTRLB _SFR_MEM8(0x0081) -#define BOD_VLMCTRLA _SFR_MEM8(0x0088) -#define BOD_INTCTRL _SFR_MEM8(0x0089) -#define BOD_INTFLAGS _SFR_MEM8(0x008A) -#define BOD_STATUS _SFR_MEM8(0x008B) - - -/* VREF - Voltage reference */ -#define VREF_CTRLA _SFR_MEM8(0x00A0) -#define VREF_CTRLB _SFR_MEM8(0x00A1) - - -/* NVMBIST - BIST in the NVMCTRL module */ -#define NVMBIST_CTRLA _SFR_MEM8(0x00C0) -#define NVMBIST_ADDRPAT _SFR_MEM8(0x00C1) -#define NVMBIST_DATAPAT _SFR_MEM8(0x00C2) -#define NVMBIST_STATUS _SFR_MEM8(0x00C3) -#define NVMBIST_CNT _SFR_MEM16(0x00C4) -#define NVMBIST_CNTL _SFR_MEM8(0x00C4) -#define NVMBIST_CNTH _SFR_MEM8(0x00C5) -#define NVMBIST_END _SFR_MEM32(0x00C6) -#define NVMBIST_END0 _SFR_MEM8(0x00C6) -#define NVMBIST_END1 _SFR_MEM8(0x00C7) -#define NVMBIST_END2 _SFR_MEM8(0x00C8) -#define NVMBIST_END3 _SFR_MEM8(0x00C9) - - -/* WDT - Watch-Dog Timer */ -#define WDT_CTRLA _SFR_MEM8(0x0100) -#define WDT_STATUS _SFR_MEM8(0x0101) - - -/* CPUINT - Interrupt Controller */ -#define CPUINT_CTRLA _SFR_MEM8(0x0110) -#define CPUINT_STATUS _SFR_MEM8(0x0111) -#define CPUINT_LVL0PRI _SFR_MEM8(0x0112) -#define CPUINT_LVL1VEC _SFR_MEM8(0x0113) - - -/* CRCSCAN - CRCSCAN */ -#define CRCSCAN_CTRLA _SFR_MEM8(0x0120) -#define CRCSCAN_CTRLB _SFR_MEM8(0x0121) -#define CRCSCAN_STATUS _SFR_MEM8(0x0122) - - -/* RTC - Real-Time Counter */ -#define RTC_CTRLA _SFR_MEM8(0x0140) -#define RTC_STATUS _SFR_MEM8(0x0141) -#define RTC_INTCTRL _SFR_MEM8(0x0142) -#define RTC_INTFLAGS _SFR_MEM8(0x0143) -#define RTC_TEMP _SFR_MEM8(0x0144) -#define RTC_DBGCTRL _SFR_MEM8(0x0145) -#define RTC_CLKSEL _SFR_MEM8(0x0147) -#define RTC_CNT _SFR_MEM16(0x0148) -#define RTC_CNTL _SFR_MEM8(0x0148) -#define RTC_CNTH _SFR_MEM8(0x0149) -#define RTC_PER _SFR_MEM16(0x014A) -#define RTC_PERL _SFR_MEM8(0x014A) -#define RTC_PERH _SFR_MEM8(0x014B) -#define RTC_CMP _SFR_MEM16(0x014C) -#define RTC_CMPL _SFR_MEM8(0x014C) -#define RTC_CMPH _SFR_MEM8(0x014D) -#define RTC_PITCTRLA _SFR_MEM8(0x0150) -#define RTC_PITSTATUS _SFR_MEM8(0x0151) -#define RTC_PITINTCTRL _SFR_MEM8(0x0152) -#define RTC_PITINTFLAGS _SFR_MEM8(0x0153) -#define RTC_PITDBGCTRL _SFR_MEM8(0x0155) - - -/* EVSYS - Event System */ -#define EVSYS_STROBE _SFR_MEM8(0x0180) -#define EVSYS_CHANNEL0 _SFR_MEM8(0x0190) -#define EVSYS_CHANNEL1 _SFR_MEM8(0x0191) -#define EVSYS_CHANNEL2 _SFR_MEM8(0x0192) -#define EVSYS_CHANNEL3 _SFR_MEM8(0x0193) -#define EVSYS_CHANNEL4 _SFR_MEM8(0x0194) -#define EVSYS_CHANNEL5 _SFR_MEM8(0x0195) -#define EVSYS_CHANNEL6 _SFR_MEM8(0x0196) -#define EVSYS_CHANNEL7 _SFR_MEM8(0x0197) -#define EVSYS_USERCCLLUT0A _SFR_MEM8(0x01A0) -#define EVSYS_USERCCLLUT0B _SFR_MEM8(0x01A1) -#define EVSYS_USERCCLLUT1A _SFR_MEM8(0x01A2) -#define EVSYS_USERCCLLUT1B _SFR_MEM8(0x01A3) -#define EVSYS_USERCCLLUT2A _SFR_MEM8(0x01A4) -#define EVSYS_USERCCLLUT2B _SFR_MEM8(0x01A5) -#define EVSYS_USERCCLLUT3A _SFR_MEM8(0x01A6) -#define EVSYS_USERCCLLUT3B _SFR_MEM8(0x01A7) -#define EVSYS_USERADC0 _SFR_MEM8(0x01A8) -#define EVSYS_USEREVOUTA _SFR_MEM8(0x01A9) -#define EVSYS_USEREVOUTB _SFR_MEM8(0x01AA) -#define EVSYS_USEREVOUTC _SFR_MEM8(0x01AB) -#define EVSYS_USEREVOUTD _SFR_MEM8(0x01AC) -#define EVSYS_USEREVOUTE _SFR_MEM8(0x01AD) -#define EVSYS_USEREVOUTF _SFR_MEM8(0x01AE) -#define EVSYS_USERUSART0 _SFR_MEM8(0x01AF) -#define EVSYS_USERUSART1 _SFR_MEM8(0x01B0) -#define EVSYS_USERUSART2 _SFR_MEM8(0x01B1) -#define EVSYS_USERUSART3 _SFR_MEM8(0x01B2) -#define EVSYS_USERTCA0 _SFR_MEM8(0x01B3) -#define EVSYS_USERTCB0 _SFR_MEM8(0x01B4) -#define EVSYS_USERTCB1 _SFR_MEM8(0x01B5) -#define EVSYS_USERTCB2 _SFR_MEM8(0x01B6) -#define EVSYS_USERTCB3 _SFR_MEM8(0x01B7) - - -/* CCL - Configurable Custom Logic */ -#define CCL_CTRLA _SFR_MEM8(0x01C0) -#define CCL_SEQCTRL0 _SFR_MEM8(0x01C1) -#define CCL_INTCTRL0 _SFR_MEM8(0x01C5) -#define CCL_INTFLAGS _SFR_MEM8(0x01C7) -#define CCL_LUT0CTRLA _SFR_MEM8(0x01C8) -#define CCL_LUT0CTRLB _SFR_MEM8(0x01C9) -#define CCL_LUT0CTRLC _SFR_MEM8(0x01CA) -#define CCL_TRUTH0 _SFR_MEM8(0x01CB) -#define CCL_LUT1CTRLA _SFR_MEM8(0x01CC) -#define CCL_LUT1CTRLB _SFR_MEM8(0x01CD) -#define CCL_LUT1CTRLC _SFR_MEM8(0x01CE) -#define CCL_TRUTH1 _SFR_MEM8(0x01CF) -#define CCL_LUT2CTRLA _SFR_MEM8(0x01D0) -#define CCL_LUT2CTRLB _SFR_MEM8(0x01D1) -#define CCL_LUT2CTRLC _SFR_MEM8(0x01D2) -#define CCL_TRUTH2 _SFR_MEM8(0x01D3) -#define CCL_LUT3CTRLA _SFR_MEM8(0x01D4) -#define CCL_LUT3CTRLB _SFR_MEM8(0x01D5) -#define CCL_LUT3CTRLC _SFR_MEM8(0x01D6) -#define CCL_TRUTH3 _SFR_MEM8(0x01D7) - - -/* PORT (PORTA) - I/O Ports */ -#define PORTA_DIR _SFR_MEM8(0x0400) -#define PORTA_DIRSET _SFR_MEM8(0x0401) -#define PORTA_DIRCLR _SFR_MEM8(0x0402) -#define PORTA_DIRTGL _SFR_MEM8(0x0403) -#define PORTA_OUT _SFR_MEM8(0x0404) -#define PORTA_OUTSET _SFR_MEM8(0x0405) -#define PORTA_OUTCLR _SFR_MEM8(0x0406) -#define PORTA_OUTTGL _SFR_MEM8(0x0407) -#define PORTA_IN _SFR_MEM8(0x0408) -#define PORTA_INTFLAGS _SFR_MEM8(0x0409) -#define PORTA_PORTCTRL _SFR_MEM8(0x040A) -#define PORTA_PIN0CTRL _SFR_MEM8(0x0410) -#define PORTA_PIN1CTRL _SFR_MEM8(0x0411) -#define PORTA_PIN2CTRL _SFR_MEM8(0x0412) -#define PORTA_PIN3CTRL _SFR_MEM8(0x0413) -#define PORTA_PIN4CTRL _SFR_MEM8(0x0414) -#define PORTA_PIN5CTRL _SFR_MEM8(0x0415) -#define PORTA_PIN6CTRL _SFR_MEM8(0x0416) -#define PORTA_PIN7CTRL _SFR_MEM8(0x0417) - - -/* PORT (PORTB) - I/O Ports */ -#define PORTB_DIR _SFR_MEM8(0x0420) -#define PORTB_DIRSET _SFR_MEM8(0x0421) -#define PORTB_DIRCLR _SFR_MEM8(0x0422) -#define PORTB_DIRTGL _SFR_MEM8(0x0423) -#define PORTB_OUT _SFR_MEM8(0x0424) -#define PORTB_OUTSET _SFR_MEM8(0x0425) -#define PORTB_OUTCLR _SFR_MEM8(0x0426) -#define PORTB_OUTTGL _SFR_MEM8(0x0427) -#define PORTB_IN _SFR_MEM8(0x0428) -#define PORTB_INTFLAGS _SFR_MEM8(0x0429) -#define PORTB_PORTCTRL _SFR_MEM8(0x042A) -#define PORTB_PIN0CTRL _SFR_MEM8(0x0430) -#define PORTB_PIN1CTRL _SFR_MEM8(0x0431) -#define PORTB_PIN2CTRL _SFR_MEM8(0x0432) -#define PORTB_PIN3CTRL _SFR_MEM8(0x0433) -#define PORTB_PIN4CTRL _SFR_MEM8(0x0434) -#define PORTB_PIN5CTRL _SFR_MEM8(0x0435) -#define PORTB_PIN6CTRL _SFR_MEM8(0x0436) -#define PORTB_PIN7CTRL _SFR_MEM8(0x0437) - - -/* PORT (PORTC) - I/O Ports */ -#define PORTC_DIR _SFR_MEM8(0x0440) -#define PORTC_DIRSET _SFR_MEM8(0x0441) -#define PORTC_DIRCLR _SFR_MEM8(0x0442) -#define PORTC_DIRTGL _SFR_MEM8(0x0443) -#define PORTC_OUT _SFR_MEM8(0x0444) -#define PORTC_OUTSET _SFR_MEM8(0x0445) -#define PORTC_OUTCLR _SFR_MEM8(0x0446) -#define PORTC_OUTTGL _SFR_MEM8(0x0447) -#define PORTC_IN _SFR_MEM8(0x0448) -#define PORTC_INTFLAGS _SFR_MEM8(0x0449) -#define PORTC_PORTCTRL _SFR_MEM8(0x044A) -#define PORTC_PIN0CTRL _SFR_MEM8(0x0450) -#define PORTC_PIN1CTRL _SFR_MEM8(0x0451) -#define PORTC_PIN2CTRL _SFR_MEM8(0x0452) -#define PORTC_PIN3CTRL _SFR_MEM8(0x0453) -#define PORTC_PIN4CTRL _SFR_MEM8(0x0454) -#define PORTC_PIN5CTRL _SFR_MEM8(0x0455) -#define PORTC_PIN6CTRL _SFR_MEM8(0x0456) -#define PORTC_PIN7CTRL _SFR_MEM8(0x0457) - - -/* PORT (PORTD) - I/O Ports */ -#define PORTD_DIR _SFR_MEM8(0x0460) -#define PORTD_DIRSET _SFR_MEM8(0x0461) -#define PORTD_DIRCLR _SFR_MEM8(0x0462) -#define PORTD_DIRTGL _SFR_MEM8(0x0463) -#define PORTD_OUT _SFR_MEM8(0x0464) -#define PORTD_OUTSET _SFR_MEM8(0x0465) -#define PORTD_OUTCLR _SFR_MEM8(0x0466) -#define PORTD_OUTTGL _SFR_MEM8(0x0467) -#define PORTD_IN _SFR_MEM8(0x0468) -#define PORTD_INTFLAGS _SFR_MEM8(0x0469) -#define PORTD_PORTCTRL _SFR_MEM8(0x046A) -#define PORTD_PIN0CTRL _SFR_MEM8(0x0470) -#define PORTD_PIN1CTRL _SFR_MEM8(0x0471) -#define PORTD_PIN2CTRL _SFR_MEM8(0x0472) -#define PORTD_PIN3CTRL _SFR_MEM8(0x0473) -#define PORTD_PIN4CTRL _SFR_MEM8(0x0474) -#define PORTD_PIN5CTRL _SFR_MEM8(0x0475) -#define PORTD_PIN6CTRL _SFR_MEM8(0x0476) -#define PORTD_PIN7CTRL _SFR_MEM8(0x0477) - - -/* PORT (PORTE) - I/O Ports */ -#define PORTE_DIR _SFR_MEM8(0x0480) -#define PORTE_DIRSET _SFR_MEM8(0x0481) -#define PORTE_DIRCLR _SFR_MEM8(0x0482) -#define PORTE_DIRTGL _SFR_MEM8(0x0483) -#define PORTE_OUT _SFR_MEM8(0x0484) -#define PORTE_OUTSET _SFR_MEM8(0x0485) -#define PORTE_OUTCLR _SFR_MEM8(0x0486) -#define PORTE_OUTTGL _SFR_MEM8(0x0487) -#define PORTE_IN _SFR_MEM8(0x0488) -#define PORTE_INTFLAGS _SFR_MEM8(0x0489) -#define PORTE_PORTCTRL _SFR_MEM8(0x048A) -#define PORTE_PIN0CTRL _SFR_MEM8(0x0490) -#define PORTE_PIN1CTRL _SFR_MEM8(0x0491) -#define PORTE_PIN2CTRL _SFR_MEM8(0x0492) -#define PORTE_PIN3CTRL _SFR_MEM8(0x0493) -#define PORTE_PIN4CTRL _SFR_MEM8(0x0494) -#define PORTE_PIN5CTRL _SFR_MEM8(0x0495) -#define PORTE_PIN6CTRL _SFR_MEM8(0x0496) -#define PORTE_PIN7CTRL _SFR_MEM8(0x0497) - - -/* PORT (PORTF) - I/O Ports */ -#define PORTF_DIR _SFR_MEM8(0x04A0) -#define PORTF_DIRSET _SFR_MEM8(0x04A1) -#define PORTF_DIRCLR _SFR_MEM8(0x04A2) -#define PORTF_DIRTGL _SFR_MEM8(0x04A3) -#define PORTF_OUT _SFR_MEM8(0x04A4) -#define PORTF_OUTSET _SFR_MEM8(0x04A5) -#define PORTF_OUTCLR _SFR_MEM8(0x04A6) -#define PORTF_OUTTGL _SFR_MEM8(0x04A7) -#define PORTF_IN _SFR_MEM8(0x04A8) -#define PORTF_INTFLAGS _SFR_MEM8(0x04A9) -#define PORTF_PORTCTRL _SFR_MEM8(0x04AA) -#define PORTF_PIN0CTRL _SFR_MEM8(0x04B0) -#define PORTF_PIN1CTRL _SFR_MEM8(0x04B1) -#define PORTF_PIN2CTRL _SFR_MEM8(0x04B2) -#define PORTF_PIN3CTRL _SFR_MEM8(0x04B3) -#define PORTF_PIN4CTRL _SFR_MEM8(0x04B4) -#define PORTF_PIN5CTRL _SFR_MEM8(0x04B5) -#define PORTF_PIN6CTRL _SFR_MEM8(0x04B6) -#define PORTF_PIN7CTRL _SFR_MEM8(0x04B7) - - -/* PORTMUX - Port Multiplexer */ -#define PORTMUX_EVSYSROUTEA _SFR_MEM8(0x05E0) -#define PORTMUX_CCLROUTEA _SFR_MEM8(0x05E1) -#define PORTMUX_USARTROUTEA _SFR_MEM8(0x05E2) -#define PORTMUX_TWISPIROUTEA _SFR_MEM8(0x05E3) -#define PORTMUX_TCAROUTEA _SFR_MEM8(0x05E4) -#define PORTMUX_TCBROUTEA _SFR_MEM8(0x05E5) - - -/* ADC (ADC0) - Analog to Digital Converter */ -#define ADC0_CTRLA _SFR_MEM8(0x0600) -#define ADC0_CTRLB _SFR_MEM8(0x0601) -#define ADC0_CTRLC _SFR_MEM8(0x0602) -#define ADC0_CTRLD _SFR_MEM8(0x0603) -#define ADC0_CTRLE _SFR_MEM8(0x0604) -#define ADC0_SAMPCTRL _SFR_MEM8(0x0605) -#define ADC0_MUXPOS _SFR_MEM8(0x0606) -#define ADC0_COMMAND _SFR_MEM8(0x0608) -#define ADC0_EVCTRL _SFR_MEM8(0x0609) -#define ADC0_INTCTRL _SFR_MEM8(0x060A) -#define ADC0_INTFLAGS _SFR_MEM8(0x060B) -#define ADC0_DBGCTRL _SFR_MEM8(0x060C) -#define ADC0_TEMP _SFR_MEM8(0x060D) -#define ADC0_RES _SFR_MEM16(0x0610) -#define ADC0_RESL _SFR_MEM8(0x0610) -#define ADC0_RESH _SFR_MEM8(0x0611) -#define ADC0_WINLT _SFR_MEM16(0x0612) -#define ADC0_WINLTL _SFR_MEM8(0x0612) -#define ADC0_WINLTH _SFR_MEM8(0x0613) -#define ADC0_WINHT _SFR_MEM16(0x0614) -#define ADC0_WINHTL _SFR_MEM8(0x0614) -#define ADC0_WINHTH _SFR_MEM8(0x0615) -#define ADC0_CALIB _SFR_MEM8(0x0616) - - -/* AC (AC0) - Analog Comparator */ -#define AC0_CTRLA _SFR_MEM8(0x0680) -#define AC0_MUXCTRLA _SFR_MEM8(0x0682) -#define AC0_DACREF _SFR_MEM8(0x0684) -#define AC0_INTCTRL _SFR_MEM8(0x0686) -#define AC0_STATUS _SFR_MEM8(0x0687) - - -/* USART (USART0) - Universal Synchronous and Asynchronous Receiver and Transmitter */ -#define USART0_RXDATAL _SFR_MEM8(0x0800) -#define USART0_RXDATAH _SFR_MEM8(0x0801) -#define USART0_TXDATAL _SFR_MEM8(0x0802) -#define USART0_TXDATAH _SFR_MEM8(0x0803) -#define USART0_STATUS _SFR_MEM8(0x0804) -#define USART0_CTRLA _SFR_MEM8(0x0805) -#define USART0_CTRLB _SFR_MEM8(0x0806) -#define USART0_CTRLC _SFR_MEM8(0x0807) -#define USART0_BAUD _SFR_MEM16(0x0808) -#define USART0_BAUDL _SFR_MEM8(0x0808) -#define USART0_BAUDH _SFR_MEM8(0x0809) -#define USART0_CTRLD _SFR_MEM8(0x080A) -#define USART0_DBGCTRL _SFR_MEM8(0x080B) -#define USART0_EVCTRL _SFR_MEM8(0x080C) -#define USART0_TXPLCTRL _SFR_MEM8(0x080D) -#define USART0_RXPLCTRL _SFR_MEM8(0x080E) - - -/* USART (USART1) - Universal Synchronous and Asynchronous Receiver and Transmitter */ -#define USART1_RXDATAL _SFR_MEM8(0x0820) -#define USART1_RXDATAH _SFR_MEM8(0x0821) -#define USART1_TXDATAL _SFR_MEM8(0x0822) -#define USART1_TXDATAH _SFR_MEM8(0x0823) -#define USART1_STATUS _SFR_MEM8(0x0824) -#define USART1_CTRLA _SFR_MEM8(0x0825) -#define USART1_CTRLB _SFR_MEM8(0x0826) -#define USART1_CTRLC _SFR_MEM8(0x0827) -#define USART1_BAUD _SFR_MEM16(0x0828) -#define USART1_BAUDL _SFR_MEM8(0x0828) -#define USART1_BAUDH _SFR_MEM8(0x0829) -#define USART1_CTRLD _SFR_MEM8(0x082A) -#define USART1_DBGCTRL _SFR_MEM8(0x082B) -#define USART1_EVCTRL _SFR_MEM8(0x082C) -#define USART1_TXPLCTRL _SFR_MEM8(0x082D) -#define USART1_RXPLCTRL _SFR_MEM8(0x082E) - - -/* USART (USART2) - Universal Synchronous and Asynchronous Receiver and Transmitter */ -#define USART2_RXDATAL _SFR_MEM8(0x0840) -#define USART2_RXDATAH _SFR_MEM8(0x0841) -#define USART2_TXDATAL _SFR_MEM8(0x0842) -#define USART2_TXDATAH _SFR_MEM8(0x0843) -#define USART2_STATUS _SFR_MEM8(0x0844) -#define USART2_CTRLA _SFR_MEM8(0x0845) -#define USART2_CTRLB _SFR_MEM8(0x0846) -#define USART2_CTRLC _SFR_MEM8(0x0847) -#define USART2_BAUD _SFR_MEM16(0x0848) -#define USART2_BAUDL _SFR_MEM8(0x0848) -#define USART2_BAUDH _SFR_MEM8(0x0849) -#define USART2_CTRLD _SFR_MEM8(0x084A) -#define USART2_DBGCTRL _SFR_MEM8(0x084B) -#define USART2_EVCTRL _SFR_MEM8(0x084C) -#define USART2_TXPLCTRL _SFR_MEM8(0x084D) -#define USART2_RXPLCTRL _SFR_MEM8(0x084E) - - -/* USART (USART3) - Universal Synchronous and Asynchronous Receiver and Transmitter */ -#define USART3_RXDATAL _SFR_MEM8(0x0860) -#define USART3_RXDATAH _SFR_MEM8(0x0861) -#define USART3_TXDATAL _SFR_MEM8(0x0862) -#define USART3_TXDATAH _SFR_MEM8(0x0863) -#define USART3_STATUS _SFR_MEM8(0x0864) -#define USART3_CTRLA _SFR_MEM8(0x0865) -#define USART3_CTRLB _SFR_MEM8(0x0866) -#define USART3_CTRLC _SFR_MEM8(0x0867) -#define USART3_BAUD _SFR_MEM16(0x0868) -#define USART3_BAUDL _SFR_MEM8(0x0868) -#define USART3_BAUDH _SFR_MEM8(0x0869) -#define USART3_CTRLD _SFR_MEM8(0x086A) -#define USART3_DBGCTRL _SFR_MEM8(0x086B) -#define USART3_EVCTRL _SFR_MEM8(0x086C) -#define USART3_TXPLCTRL _SFR_MEM8(0x086D) -#define USART3_RXPLCTRL _SFR_MEM8(0x086E) - - -/* TWI (TWI0) - Two-Wire Interface */ -#define TWI0_CTRLA _SFR_MEM8(0x08A0) -#define TWI0_BRIDGECTRL _SFR_MEM8(0x08A1) -#define TWI0_DBGCTRL _SFR_MEM8(0x08A2) -#define TWI0_MCTRLA _SFR_MEM8(0x08A3) -#define TWI0_MCTRLB _SFR_MEM8(0x08A4) -#define TWI0_MSTATUS _SFR_MEM8(0x08A5) -#define TWI0_MBAUD _SFR_MEM8(0x08A6) -#define TWI0_MADDR _SFR_MEM8(0x08A7) -#define TWI0_MDATA _SFR_MEM8(0x08A8) -#define TWI0_SCTRLA _SFR_MEM8(0x08A9) -#define TWI0_SCTRLB _SFR_MEM8(0x08AA) -#define TWI0_SSTATUS _SFR_MEM8(0x08AB) -#define TWI0_SADDR _SFR_MEM8(0x08AC) -#define TWI0_SDATA _SFR_MEM8(0x08AD) -#define TWI0_SADDRMASK _SFR_MEM8(0x08AE) - - -/* SPI (SPI0) - Serial Peripheral Interface */ -#define SPI0_CTRLA _SFR_MEM8(0x08C0) -#define SPI0_CTRLB _SFR_MEM8(0x08C1) -#define SPI0_INTCTRL _SFR_MEM8(0x08C2) -#define SPI0_INTFLAGS _SFR_MEM8(0x08C3) -#define SPI0_DATA _SFR_MEM8(0x08C4) - - -/* TCA (TCA0) - 16-bit Timer/Counter Type A */ -#define TCA0_SINGLE_CTRLA _SFR_MEM8(0x0A00) -#define TCA0_SINGLE_CTRLB _SFR_MEM8(0x0A01) -#define TCA0_SINGLE_CTRLC _SFR_MEM8(0x0A02) -#define TCA0_SINGLE_CTRLD _SFR_MEM8(0x0A03) -#define TCA0_SINGLE_CTRLECLR _SFR_MEM8(0x0A04) -#define TCA0_SINGLE_CTRLESET _SFR_MEM8(0x0A05) -#define TCA0_SINGLE_CTRLFCLR _SFR_MEM8(0x0A06) -#define TCA0_SINGLE_CTRLFSET _SFR_MEM8(0x0A07) -#define TCA0_SINGLE_EVCTRL _SFR_MEM8(0x0A09) -#define TCA0_SINGLE_INTCTRL _SFR_MEM8(0x0A0A) -#define TCA0_SINGLE_INTFLAGS _SFR_MEM8(0x0A0B) -#define TCA0_SINGLE_DBGCTRL _SFR_MEM8(0x0A0E) -#define TCA0_SINGLE_TEMP _SFR_MEM8(0x0A0F) -#define TCA0_SINGLE_CNT _SFR_MEM16(0x0A20) -#define TCA0_SINGLE_PER _SFR_MEM16(0x0A26) -#define TCA0_SINGLE_CMP0 _SFR_MEM16(0x0A28) -#define TCA0_SINGLE_CMP1 _SFR_MEM16(0x0A2A) -#define TCA0_SINGLE_CMP2 _SFR_MEM16(0x0A2C) -#define TCA0_SINGLE_PERBUF _SFR_MEM16(0x0A36) -#define TCA0_SINGLE_CMP0BUF _SFR_MEM16(0x0A38) -#define TCA0_SINGLE_CMP1BUF _SFR_MEM16(0x0A3A) -#define TCA0_SINGLE_CMP2BUF _SFR_MEM16(0x0A3C) - - -#define TCA0_SPLIT_CTRLA _SFR_MEM8(0x0A00) -#define TCA0_SPLIT_CTRLB _SFR_MEM8(0x0A01) -#define TCA0_SPLIT_CTRLC _SFR_MEM8(0x0A02) -#define TCA0_SPLIT_CTRLD _SFR_MEM8(0x0A03) -#define TCA0_SPLIT_CTRLECLR _SFR_MEM8(0x0A04) -#define TCA0_SPLIT_CTRLESET _SFR_MEM8(0x0A05) -#define TCA0_SPLIT_INTCTRL _SFR_MEM8(0x0A0A) -#define TCA0_SPLIT_INTFLAGS _SFR_MEM8(0x0A0B) -#define TCA0_SPLIT_DBGCTRL _SFR_MEM8(0x0A0E) -#define TCA0_SPLIT_LCNT _SFR_MEM8(0x0A20) -#define TCA0_SPLIT_HCNT _SFR_MEM8(0x0A21) -#define TCA0_SPLIT_LPER _SFR_MEM8(0x0A26) -#define TCA0_SPLIT_HPER _SFR_MEM8(0x0A27) -#define TCA0_SPLIT_LCMP0 _SFR_MEM8(0x0A28) -#define TCA0_SPLIT_HCMP0 _SFR_MEM8(0x0A29) -#define TCA0_SPLIT_LCMP1 _SFR_MEM8(0x0A2A) -#define TCA0_SPLIT_HCMP1 _SFR_MEM8(0x0A2B) -#define TCA0_SPLIT_LCMP2 _SFR_MEM8(0x0A2C) -#define TCA0_SPLIT_HCMP2 _SFR_MEM8(0x0A2D) - - - - -/* TCB (TCB0) - 16-bit Timer Type B */ -#define TCB0_CTRLA _SFR_MEM8(0x0A80) -#define TCB0_CTRLB _SFR_MEM8(0x0A81) -#define TCB0_EVCTRL _SFR_MEM8(0x0A84) -#define TCB0_INTCTRL _SFR_MEM8(0x0A85) -#define TCB0_INTFLAGS _SFR_MEM8(0x0A86) -#define TCB0_STATUS _SFR_MEM8(0x0A87) -#define TCB0_DBGCTRL _SFR_MEM8(0x0A88) -#define TCB0_TEMP _SFR_MEM8(0x0A89) -#define TCB0_CNT _SFR_MEM16(0x0A8A) -#define TCB0_CNTL _SFR_MEM8(0x0A8A) -#define TCB0_CNTH _SFR_MEM8(0x0A8B) -#define TCB0_CCMP _SFR_MEM16(0x0A8C) -#define TCB0_CCMPL _SFR_MEM8(0x0A8C) -#define TCB0_CCMPH _SFR_MEM8(0x0A8D) - - -/* TCB (TCB1) - 16-bit Timer Type B */ -#define TCB1_CTRLA _SFR_MEM8(0x0A90) -#define TCB1_CTRLB _SFR_MEM8(0x0A91) -#define TCB1_EVCTRL _SFR_MEM8(0x0A94) -#define TCB1_INTCTRL _SFR_MEM8(0x0A95) -#define TCB1_INTFLAGS _SFR_MEM8(0x0A96) -#define TCB1_STATUS _SFR_MEM8(0x0A97) -#define TCB1_DBGCTRL _SFR_MEM8(0x0A98) -#define TCB1_TEMP _SFR_MEM8(0x0A99) -#define TCB1_CNT _SFR_MEM16(0x0A9A) -#define TCB1_CNTL _SFR_MEM8(0x0A9A) -#define TCB1_CNTH _SFR_MEM8(0x0A9B) -#define TCB1_CCMP _SFR_MEM16(0x0A9C) -#define TCB1_CCMPL _SFR_MEM8(0x0A9C) -#define TCB1_CCMPH _SFR_MEM8(0x0A9D) - - -/* TCB (TCB2) - 16-bit Timer Type B */ -#define TCB2_CTRLA _SFR_MEM8(0x0AA0) -#define TCB2_CTRLB _SFR_MEM8(0x0AA1) -#define TCB2_EVCTRL _SFR_MEM8(0x0AA4) -#define TCB2_INTCTRL _SFR_MEM8(0x0AA5) -#define TCB2_INTFLAGS _SFR_MEM8(0x0AA6) -#define TCB2_STATUS _SFR_MEM8(0x0AA7) -#define TCB2_DBGCTRL _SFR_MEM8(0x0AA8) -#define TCB2_TEMP _SFR_MEM8(0x0AA9) -#define TCB2_CNT _SFR_MEM16(0x0AAA) -#define TCB2_CNTL _SFR_MEM8(0x0AAA) -#define TCB2_CNTH _SFR_MEM8(0x0AAB) -#define TCB2_CCMP _SFR_MEM16(0x0AAC) -#define TCB2_CCMPL _SFR_MEM8(0x0AAC) -#define TCB2_CCMPH _SFR_MEM8(0x0AAD) - - -/* TCB (TCB3) - 16-bit Timer Type B */ -#define TCB3_CTRLA _SFR_MEM8(0x0AB0) -#define TCB3_CTRLB _SFR_MEM8(0x0AB1) -#define TCB3_EVCTRL _SFR_MEM8(0x0AB4) -#define TCB3_INTCTRL _SFR_MEM8(0x0AB5) -#define TCB3_INTFLAGS _SFR_MEM8(0x0AB6) -#define TCB3_STATUS _SFR_MEM8(0x0AB7) -#define TCB3_DBGCTRL _SFR_MEM8(0x0AB8) -#define TCB3_TEMP _SFR_MEM8(0x0AB9) -#define TCB3_CNT _SFR_MEM16(0x0ABA) -#define TCB3_CNTL _SFR_MEM8(0x0ABA) -#define TCB3_CNTH _SFR_MEM8(0x0ABB) -#define TCB3_CCMP _SFR_MEM16(0x0ABC) -#define TCB3_CCMPL _SFR_MEM8(0x0ABC) -#define TCB3_CCMPH _SFR_MEM8(0x0ABD) - - -/* SYSCFG - System Configuration Registers */ -#define SYSCFG_REVID _SFR_MEM8(0x0F01) -#define SYSCFG_EXTBRK _SFR_MEM8(0x0F02) -#define SYSCFG_OCDM _SFR_MEM8(0x0F18) -#define SYSCFG_OCDMS _SFR_MEM8(0x0F19) - - -/* NVMCTRL - Non-volatile Memory Controller */ -#define NVMCTRL_CTRLA _SFR_MEM8(0x1000) -#define NVMCTRL_CTRLB _SFR_MEM8(0x1001) -#define NVMCTRL_STATUS _SFR_MEM8(0x1002) -#define NVMCTRL_INTCTRL _SFR_MEM8(0x1003) -#define NVMCTRL_INTFLAGS _SFR_MEM8(0x1004) -#define NVMCTRL_DATA _SFR_MEM16(0x1006) -#define NVMCTRL_DATAL _SFR_MEM8(0x1006) -#define NVMCTRL_DATAH _SFR_MEM8(0x1007) -#define NVMCTRL_ADDR _SFR_MEM16(0x1008) -#define NVMCTRL_ADDRL _SFR_MEM8(0x1008) -#define NVMCTRL_ADDRH _SFR_MEM8(0x1009) - - -/* SIGROW - Signature row */ -#define SIGROW_DEVICEID0 _SFR_MEM8(0x1100) -#define SIGROW_DEVICEID1 _SFR_MEM8(0x1101) -#define SIGROW_DEVICEID2 _SFR_MEM8(0x1102) -#define SIGROW_SERNUM0 _SFR_MEM8(0x1103) -#define SIGROW_SERNUM1 _SFR_MEM8(0x1104) -#define SIGROW_SERNUM2 _SFR_MEM8(0x1105) -#define SIGROW_SERNUM3 _SFR_MEM8(0x1106) -#define SIGROW_SERNUM4 _SFR_MEM8(0x1107) -#define SIGROW_SERNUM5 _SFR_MEM8(0x1108) -#define SIGROW_SERNUM6 _SFR_MEM8(0x1109) -#define SIGROW_SERNUM7 _SFR_MEM8(0x110A) -#define SIGROW_SERNUM8 _SFR_MEM8(0x110B) -#define SIGROW_SERNUM9 _SFR_MEM8(0x110C) -#define SIGROW_OSCCAL32K _SFR_MEM8(0x1114) -#define SIGROW_OSCCAL16M0 _SFR_MEM8(0x1118) -#define SIGROW_OSCCAL16M1 _SFR_MEM8(0x1119) -#define SIGROW_OSCCAL20M0 _SFR_MEM8(0x111A) -#define SIGROW_OSCCAL20M1 _SFR_MEM8(0x111B) -#define SIGROW_TEMPSENSE0 _SFR_MEM8(0x1120) -#define SIGROW_TEMPSENSE1 _SFR_MEM8(0x1121) -#define SIGROW_OSC16ERR3V _SFR_MEM8(0x1122) -#define SIGROW_OSC16ERR5V _SFR_MEM8(0x1123) -#define SIGROW_OSC20ERR3V _SFR_MEM8(0x1124) -#define SIGROW_OSC20ERR5V _SFR_MEM8(0x1125) -#define SIGROW_CHECKSUM1 _SFR_MEM8(0x112F) - - -/* FUSE - Fuses */ -#define FUSE_WDTCFG _SFR_MEM8(0x1280) -#define FUSE_BODCFG _SFR_MEM8(0x1281) -#define FUSE_OSCCFG _SFR_MEM8(0x1282) -#define FUSE_TCD0CFG _SFR_MEM8(0x1284) -#define FUSE_SYSCFG0 _SFR_MEM8(0x1285) -#define FUSE_SYSCFG1 _SFR_MEM8(0x1286) -#define FUSE_APPEND _SFR_MEM8(0x1287) -#define FUSE_BOOTEND _SFR_MEM8(0x1288) - - -/* LOCKBIT - Lockbit */ -#define LOCKBIT_LOCKBIT _SFR_MEM8(0x128A) - - -/* USERROW - User Row */ -#define USERROW_USERROW0 _SFR_MEM8(0x1300) -#define USERROW_USERROW1 _SFR_MEM8(0x1301) -#define USERROW_USERROW2 _SFR_MEM8(0x1302) -#define USERROW_USERROW3 _SFR_MEM8(0x1303) -#define USERROW_USERROW4 _SFR_MEM8(0x1304) -#define USERROW_USERROW5 _SFR_MEM8(0x1305) -#define USERROW_USERROW6 _SFR_MEM8(0x1306) -#define USERROW_USERROW7 _SFR_MEM8(0x1307) -#define USERROW_USERROW8 _SFR_MEM8(0x1308) -#define USERROW_USERROW9 _SFR_MEM8(0x1309) -#define USERROW_USERROW10 _SFR_MEM8(0x130A) -#define USERROW_USERROW11 _SFR_MEM8(0x130B) -#define USERROW_USERROW12 _SFR_MEM8(0x130C) -#define USERROW_USERROW13 _SFR_MEM8(0x130D) -#define USERROW_USERROW14 _SFR_MEM8(0x130E) -#define USERROW_USERROW15 _SFR_MEM8(0x130F) -#define USERROW_USERROW16 _SFR_MEM8(0x1310) -#define USERROW_USERROW17 _SFR_MEM8(0x1311) -#define USERROW_USERROW18 _SFR_MEM8(0x1312) -#define USERROW_USERROW19 _SFR_MEM8(0x1313) -#define USERROW_USERROW20 _SFR_MEM8(0x1314) -#define USERROW_USERROW21 _SFR_MEM8(0x1315) -#define USERROW_USERROW22 _SFR_MEM8(0x1316) -#define USERROW_USERROW23 _SFR_MEM8(0x1317) -#define USERROW_USERROW24 _SFR_MEM8(0x1318) -#define USERROW_USERROW25 _SFR_MEM8(0x1319) -#define USERROW_USERROW26 _SFR_MEM8(0x131A) -#define USERROW_USERROW27 _SFR_MEM8(0x131B) -#define USERROW_USERROW28 _SFR_MEM8(0x131C) -#define USERROW_USERROW29 _SFR_MEM8(0x131D) -#define USERROW_USERROW30 _SFR_MEM8(0x131E) -#define USERROW_USERROW31 _SFR_MEM8(0x131F) -#define USERROW_USERROW32 _SFR_MEM8(0x1320) -#define USERROW_USERROW33 _SFR_MEM8(0x1321) -#define USERROW_USERROW34 _SFR_MEM8(0x1322) -#define USERROW_USERROW35 _SFR_MEM8(0x1323) -#define USERROW_USERROW36 _SFR_MEM8(0x1324) -#define USERROW_USERROW37 _SFR_MEM8(0x1325) -#define USERROW_USERROW38 _SFR_MEM8(0x1326) -#define USERROW_USERROW39 _SFR_MEM8(0x1327) -#define USERROW_USERROW40 _SFR_MEM8(0x1328) -#define USERROW_USERROW41 _SFR_MEM8(0x1329) -#define USERROW_USERROW42 _SFR_MEM8(0x132A) -#define USERROW_USERROW43 _SFR_MEM8(0x132B) -#define USERROW_USERROW44 _SFR_MEM8(0x132C) -#define USERROW_USERROW45 _SFR_MEM8(0x132D) -#define USERROW_USERROW46 _SFR_MEM8(0x132E) -#define USERROW_USERROW47 _SFR_MEM8(0x132F) -#define USERROW_USERROW48 _SFR_MEM8(0x1330) -#define USERROW_USERROW49 _SFR_MEM8(0x1331) -#define USERROW_USERROW50 _SFR_MEM8(0x1332) -#define USERROW_USERROW51 _SFR_MEM8(0x1333) -#define USERROW_USERROW52 _SFR_MEM8(0x1334) -#define USERROW_USERROW53 _SFR_MEM8(0x1335) -#define USERROW_USERROW54 _SFR_MEM8(0x1336) -#define USERROW_USERROW55 _SFR_MEM8(0x1337) -#define USERROW_USERROW56 _SFR_MEM8(0x1338) -#define USERROW_USERROW57 _SFR_MEM8(0x1339) -#define USERROW_USERROW58 _SFR_MEM8(0x133A) -#define USERROW_USERROW59 _SFR_MEM8(0x133B) -#define USERROW_USERROW60 _SFR_MEM8(0x133C) -#define USERROW_USERROW61 _SFR_MEM8(0x133D) -#define USERROW_USERROW62 _SFR_MEM8(0x133E) -#define USERROW_USERROW63 _SFR_MEM8(0x133F) - - - -/*================== Bitfield Definitions ================== */ - -/* AC - Analog Comparator */ -/* AC.CTRLA bit masks and bit positions */ -#define AC_ENABLE_bm 0x01 /* Enable bit mask. */ -#define AC_ENABLE_bp 0 /* Enable bit position. */ -#define AC_HYSMODE_gm 0x06 /* Hysteresis Mode group mask. */ -#define AC_HYSMODE_gp 1 /* Hysteresis Mode group position. */ -#define AC_HYSMODE0_bm (1<<1) /* Hysteresis Mode bit 0 mask. */ -#define AC_HYSMODE0_bp 1 /* Hysteresis Mode bit 0 position. */ -#define AC_HYSMODE1_bm (1<<2) /* Hysteresis Mode bit 1 mask. */ -#define AC_HYSMODE1_bp 2 /* Hysteresis Mode bit 1 position. */ -#define AC_LPMODE_bm 0x08 /* Low Power Mode bit mask. */ -#define AC_LPMODE_bp 3 /* Low Power Mode bit position. */ -#define AC_INTMODE_gm 0x30 /* Interrupt Mode group mask. */ -#define AC_INTMODE_gp 4 /* Interrupt Mode group position. */ -#define AC_INTMODE0_bm (1<<4) /* Interrupt Mode bit 0 mask. */ -#define AC_INTMODE0_bp 4 /* Interrupt Mode bit 0 position. */ -#define AC_INTMODE1_bm (1<<5) /* Interrupt Mode bit 1 mask. */ -#define AC_INTMODE1_bp 5 /* Interrupt Mode bit 1 position. */ -#define AC_OUTEN_bm 0x40 /* Output Buffer Enable bit mask. */ -#define AC_OUTEN_bp 6 /* Output Buffer Enable bit position. */ -#define AC_RUNSTDBY_bm 0x80 /* Run in Standby Mode bit mask. */ -#define AC_RUNSTDBY_bp 7 /* Run in Standby Mode bit position. */ - -/* AC.MUXCTRLA bit masks and bit positions */ -#define AC_MUXNEG_gm 0x03 /* Negative Input MUX Selection group mask. */ -#define AC_MUXNEG_gp 0 /* Negative Input MUX Selection group position. */ -#define AC_MUXNEG0_bm (1<<0) /* Negative Input MUX Selection bit 0 mask. */ -#define AC_MUXNEG0_bp 0 /* Negative Input MUX Selection bit 0 position. */ -#define AC_MUXNEG1_bm (1<<1) /* Negative Input MUX Selection bit 1 mask. */ -#define AC_MUXNEG1_bp 1 /* Negative Input MUX Selection bit 1 position. */ -#define AC_MUXPOS_gm 0x18 /* Positive Input MUX Selection group mask. */ -#define AC_MUXPOS_gp 3 /* Positive Input MUX Selection group position. */ -#define AC_MUXPOS0_bm (1<<3) /* Positive Input MUX Selection bit 0 mask. */ -#define AC_MUXPOS0_bp 3 /* Positive Input MUX Selection bit 0 position. */ -#define AC_MUXPOS1_bm (1<<4) /* Positive Input MUX Selection bit 1 mask. */ -#define AC_MUXPOS1_bp 4 /* Positive Input MUX Selection bit 1 position. */ -#define AC_INVERT_bm 0x80 /* Invert AC Output bit mask. */ -#define AC_INVERT_bp 7 /* Invert AC Output bit position. */ - -/* AC.DACREF bit masks and bit positions */ -#define AC_DATA_gm 0xFF /* DAC voltage reference group mask. */ -#define AC_DATA_gp 0 /* DAC voltage reference group position. */ -#define AC_DATA0_bm (1<<0) /* DAC voltage reference bit 0 mask. */ -#define AC_DATA0_bp 0 /* DAC voltage reference bit 0 position. */ -#define AC_DATA1_bm (1<<1) /* DAC voltage reference bit 1 mask. */ -#define AC_DATA1_bp 1 /* DAC voltage reference bit 1 position. */ -#define AC_DATA2_bm (1<<2) /* DAC voltage reference bit 2 mask. */ -#define AC_DATA2_bp 2 /* DAC voltage reference bit 2 position. */ -#define AC_DATA3_bm (1<<3) /* DAC voltage reference bit 3 mask. */ -#define AC_DATA3_bp 3 /* DAC voltage reference bit 3 position. */ -#define AC_DATA4_bm (1<<4) /* DAC voltage reference bit 4 mask. */ -#define AC_DATA4_bp 4 /* DAC voltage reference bit 4 position. */ -#define AC_DATA5_bm (1<<5) /* DAC voltage reference bit 5 mask. */ -#define AC_DATA5_bp 5 /* DAC voltage reference bit 5 position. */ -#define AC_DATA6_bm (1<<6) /* DAC voltage reference bit 6 mask. */ -#define AC_DATA6_bp 6 /* DAC voltage reference bit 6 position. */ -#define AC_DATA7_bm (1<<7) /* DAC voltage reference bit 7 mask. */ -#define AC_DATA7_bp 7 /* DAC voltage reference bit 7 position. */ - -/* AC.INTCTRL bit masks and bit positions */ -#define AC_CMP_bm 0x01 /* Analog Comparator 0 Interrupt Enable bit mask. */ -#define AC_CMP_bp 0 /* Analog Comparator 0 Interrupt Enable bit position. */ - -/* AC.STATUS bit masks and bit positions */ -/* AC_CMP is already defined. */ -#define AC_STATE_bm 0x10 /* Analog Comparator State bit mask. */ -#define AC_STATE_bp 4 /* Analog Comparator State bit position. */ - -/* ADC - Analog to Digital Converter */ -/* ADC.CTRLA bit masks and bit positions */ -#define ADC_ENABLE_bm 0x01 /* ADC Enable bit mask. */ -#define ADC_ENABLE_bp 0 /* ADC Enable bit position. */ -#define ADC_FREERUN_bm 0x02 /* ADC Freerun mode bit mask. */ -#define ADC_FREERUN_bp 1 /* ADC Freerun mode bit position. */ -#define ADC_RESSEL_bm 0x04 /* ADC Resolution bit mask. */ -#define ADC_RESSEL_bp 2 /* ADC Resolution bit position. */ -#define ADC_RUNSTBY_bm 0x80 /* Run standby mode bit mask. */ -#define ADC_RUNSTBY_bp 7 /* Run standby mode bit position. */ - -/* ADC.CTRLB bit masks and bit positions */ -#define ADC_SAMPNUM_gm 0x07 /* Accumulation Samples group mask. */ -#define ADC_SAMPNUM_gp 0 /* Accumulation Samples group position. */ -#define ADC_SAMPNUM0_bm (1<<0) /* Accumulation Samples bit 0 mask. */ -#define ADC_SAMPNUM0_bp 0 /* Accumulation Samples bit 0 position. */ -#define ADC_SAMPNUM1_bm (1<<1) /* Accumulation Samples bit 1 mask. */ -#define ADC_SAMPNUM1_bp 1 /* Accumulation Samples bit 1 position. */ -#define ADC_SAMPNUM2_bm (1<<2) /* Accumulation Samples bit 2 mask. */ -#define ADC_SAMPNUM2_bp 2 /* Accumulation Samples bit 2 position. */ - -/* ADC.CTRLC bit masks and bit positions */ -#define ADC_PRESC_gm 0x07 /* Clock Pre-scaler group mask. */ -#define ADC_PRESC_gp 0 /* Clock Pre-scaler group position. */ -#define ADC_PRESC0_bm (1<<0) /* Clock Pre-scaler bit 0 mask. */ -#define ADC_PRESC0_bp 0 /* Clock Pre-scaler bit 0 position. */ -#define ADC_PRESC1_bm (1<<1) /* Clock Pre-scaler bit 1 mask. */ -#define ADC_PRESC1_bp 1 /* Clock Pre-scaler bit 1 position. */ -#define ADC_PRESC2_bm (1<<2) /* Clock Pre-scaler bit 2 mask. */ -#define ADC_PRESC2_bp 2 /* Clock Pre-scaler bit 2 position. */ -#define ADC_REFSEL_gm 0x30 /* Reference Selection group mask. */ -#define ADC_REFSEL_gp 4 /* Reference Selection group position. */ -#define ADC_REFSEL0_bm (1<<4) /* Reference Selection bit 0 mask. */ -#define ADC_REFSEL0_bp 4 /* Reference Selection bit 0 position. */ -#define ADC_REFSEL1_bm (1<<5) /* Reference Selection bit 1 mask. */ -#define ADC_REFSEL1_bp 5 /* Reference Selection bit 1 position. */ -#define ADC_SAMPCAP_bm 0x40 /* Sample Capacitance Selection bit mask. */ -#define ADC_SAMPCAP_bp 6 /* Sample Capacitance Selection bit position. */ - -/* ADC.CTRLD bit masks and bit positions */ -#define ADC_SAMPDLY_gm 0x0F /* Sampling Delay Selection group mask. */ -#define ADC_SAMPDLY_gp 0 /* Sampling Delay Selection group position. */ -#define ADC_SAMPDLY0_bm (1<<0) /* Sampling Delay Selection bit 0 mask. */ -#define ADC_SAMPDLY0_bp 0 /* Sampling Delay Selection bit 0 position. */ -#define ADC_SAMPDLY1_bm (1<<1) /* Sampling Delay Selection bit 1 mask. */ -#define ADC_SAMPDLY1_bp 1 /* Sampling Delay Selection bit 1 position. */ -#define ADC_SAMPDLY2_bm (1<<2) /* Sampling Delay Selection bit 2 mask. */ -#define ADC_SAMPDLY2_bp 2 /* Sampling Delay Selection bit 2 position. */ -#define ADC_SAMPDLY3_bm (1<<3) /* Sampling Delay Selection bit 3 mask. */ -#define ADC_SAMPDLY3_bp 3 /* Sampling Delay Selection bit 3 position. */ -#define ADC_ASDV_bm 0x10 /* Automatic Sampling Delay Variation bit mask. */ -#define ADC_ASDV_bp 4 /* Automatic Sampling Delay Variation bit position. */ -#define ADC_INITDLY_gm 0xE0 /* Initial Delay Selection group mask. */ -#define ADC_INITDLY_gp 5 /* Initial Delay Selection group position. */ -#define ADC_INITDLY0_bm (1<<5) /* Initial Delay Selection bit 0 mask. */ -#define ADC_INITDLY0_bp 5 /* Initial Delay Selection bit 0 position. */ -#define ADC_INITDLY1_bm (1<<6) /* Initial Delay Selection bit 1 mask. */ -#define ADC_INITDLY1_bp 6 /* Initial Delay Selection bit 1 position. */ -#define ADC_INITDLY2_bm (1<<7) /* Initial Delay Selection bit 2 mask. */ -#define ADC_INITDLY2_bp 7 /* Initial Delay Selection bit 2 position. */ - -/* ADC.CTRLE bit masks and bit positions */ -#define ADC_WINCM_gm 0x07 /* Window Comparator Mode group mask. */ -#define ADC_WINCM_gp 0 /* Window Comparator Mode group position. */ -#define ADC_WINCM0_bm (1<<0) /* Window Comparator Mode bit 0 mask. */ -#define ADC_WINCM0_bp 0 /* Window Comparator Mode bit 0 position. */ -#define ADC_WINCM1_bm (1<<1) /* Window Comparator Mode bit 1 mask. */ -#define ADC_WINCM1_bp 1 /* Window Comparator Mode bit 1 position. */ -#define ADC_WINCM2_bm (1<<2) /* Window Comparator Mode bit 2 mask. */ -#define ADC_WINCM2_bp 2 /* Window Comparator Mode bit 2 position. */ - -/* ADC.SAMPCTRL bit masks and bit positions */ -#define ADC_SAMPLEN_gm 0x1F /* Sample lenght group mask. */ -#define ADC_SAMPLEN_gp 0 /* Sample lenght group position. */ -#define ADC_SAMPLEN0_bm (1<<0) /* Sample lenght bit 0 mask. */ -#define ADC_SAMPLEN0_bp 0 /* Sample lenght bit 0 position. */ -#define ADC_SAMPLEN1_bm (1<<1) /* Sample lenght bit 1 mask. */ -#define ADC_SAMPLEN1_bp 1 /* Sample lenght bit 1 position. */ -#define ADC_SAMPLEN2_bm (1<<2) /* Sample lenght bit 2 mask. */ -#define ADC_SAMPLEN2_bp 2 /* Sample lenght bit 2 position. */ -#define ADC_SAMPLEN3_bm (1<<3) /* Sample lenght bit 3 mask. */ -#define ADC_SAMPLEN3_bp 3 /* Sample lenght bit 3 position. */ -#define ADC_SAMPLEN4_bm (1<<4) /* Sample lenght bit 4 mask. */ -#define ADC_SAMPLEN4_bp 4 /* Sample lenght bit 4 position. */ - -/* ADC.MUXPOS bit masks and bit positions */ -#define ADC_MUXPOS_gm 0x1F /* Analog Channel Selection Bits group mask. */ -#define ADC_MUXPOS_gp 0 /* Analog Channel Selection Bits group position. */ -#define ADC_MUXPOS0_bm (1<<0) /* Analog Channel Selection Bits bit 0 mask. */ -#define ADC_MUXPOS0_bp 0 /* Analog Channel Selection Bits bit 0 position. */ -#define ADC_MUXPOS1_bm (1<<1) /* Analog Channel Selection Bits bit 1 mask. */ -#define ADC_MUXPOS1_bp 1 /* Analog Channel Selection Bits bit 1 position. */ -#define ADC_MUXPOS2_bm (1<<2) /* Analog Channel Selection Bits bit 2 mask. */ -#define ADC_MUXPOS2_bp 2 /* Analog Channel Selection Bits bit 2 position. */ -#define ADC_MUXPOS3_bm (1<<3) /* Analog Channel Selection Bits bit 3 mask. */ -#define ADC_MUXPOS3_bp 3 /* Analog Channel Selection Bits bit 3 position. */ -#define ADC_MUXPOS4_bm (1<<4) /* Analog Channel Selection Bits bit 4 mask. */ -#define ADC_MUXPOS4_bp 4 /* Analog Channel Selection Bits bit 4 position. */ - -/* ADC.COMMAND bit masks and bit positions */ -#define ADC_STCONV_bm 0x01 /* Start Conversion Operation bit mask. */ -#define ADC_STCONV_bp 0 /* Start Conversion Operation bit position. */ - -/* ADC.EVCTRL bit masks and bit positions */ -#define ADC_STARTEI_bm 0x01 /* Start Event Input Enable bit mask. */ -#define ADC_STARTEI_bp 0 /* Start Event Input Enable bit position. */ - -/* ADC.INTCTRL bit masks and bit positions */ -#define ADC_RESRDY_bm 0x01 /* Result Ready Interrupt Enable bit mask. */ -#define ADC_RESRDY_bp 0 /* Result Ready Interrupt Enable bit position. */ -#define ADC_WCMP_bm 0x02 /* Window Comparator Interrupt Enable bit mask. */ -#define ADC_WCMP_bp 1 /* Window Comparator Interrupt Enable bit position. */ - -/* ADC.INTFLAGS bit masks and bit positions */ -/* ADC_RESRDY is already defined. */ -/* ADC_WCMP is already defined. */ - -/* ADC.DBGCTRL bit masks and bit positions */ -#define ADC_DBGRUN_bm 0x01 /* Debug run bit mask. */ -#define ADC_DBGRUN_bp 0 /* Debug run bit position. */ - -/* ADC.TEMP bit masks and bit positions */ -#define ADC_TEMP_gm 0xFF /* Temporary group mask. */ -#define ADC_TEMP_gp 0 /* Temporary group position. */ -#define ADC_TEMP0_bm (1<<0) /* Temporary bit 0 mask. */ -#define ADC_TEMP0_bp 0 /* Temporary bit 0 position. */ -#define ADC_TEMP1_bm (1<<1) /* Temporary bit 1 mask. */ -#define ADC_TEMP1_bp 1 /* Temporary bit 1 position. */ -#define ADC_TEMP2_bm (1<<2) /* Temporary bit 2 mask. */ -#define ADC_TEMP2_bp 2 /* Temporary bit 2 position. */ -#define ADC_TEMP3_bm (1<<3) /* Temporary bit 3 mask. */ -#define ADC_TEMP3_bp 3 /* Temporary bit 3 position. */ -#define ADC_TEMP4_bm (1<<4) /* Temporary bit 4 mask. */ -#define ADC_TEMP4_bp 4 /* Temporary bit 4 position. */ -#define ADC_TEMP5_bm (1<<5) /* Temporary bit 5 mask. */ -#define ADC_TEMP5_bp 5 /* Temporary bit 5 position. */ -#define ADC_TEMP6_bm (1<<6) /* Temporary bit 6 mask. */ -#define ADC_TEMP6_bp 6 /* Temporary bit 6 position. */ -#define ADC_TEMP7_bm (1<<7) /* Temporary bit 7 mask. */ -#define ADC_TEMP7_bp 7 /* Temporary bit 7 position. */ - - - - -/* ADC.CALIB bit masks and bit positions */ -#define ADC_DUTYCYC_bm 0x01 /* Duty Cycle bit mask. */ -#define ADC_DUTYCYC_bp 0 /* Duty Cycle bit position. */ - -/* BOD - Bod interface */ -/* BOD.CTRLA bit masks and bit positions */ -#define BOD_SLEEP_gm 0x03 /* Operation in sleep mode group mask. */ -#define BOD_SLEEP_gp 0 /* Operation in sleep mode group position. */ -#define BOD_SLEEP0_bm (1<<0) /* Operation in sleep mode bit 0 mask. */ -#define BOD_SLEEP0_bp 0 /* Operation in sleep mode bit 0 position. */ -#define BOD_SLEEP1_bm (1<<1) /* Operation in sleep mode bit 1 mask. */ -#define BOD_SLEEP1_bp 1 /* Operation in sleep mode bit 1 position. */ -#define BOD_ACTIVE_gm 0x0C /* Operation in active mode group mask. */ -#define BOD_ACTIVE_gp 2 /* Operation in active mode group position. */ -#define BOD_ACTIVE0_bm (1<<2) /* Operation in active mode bit 0 mask. */ -#define BOD_ACTIVE0_bp 2 /* Operation in active mode bit 0 position. */ -#define BOD_ACTIVE1_bm (1<<3) /* Operation in active mode bit 1 mask. */ -#define BOD_ACTIVE1_bp 3 /* Operation in active mode bit 1 position. */ -#define BOD_SAMPFREQ_bm 0x10 /* Sample frequency bit mask. */ -#define BOD_SAMPFREQ_bp 4 /* Sample frequency bit position. */ - -/* BOD.CTRLB bit masks and bit positions */ -#define BOD_LVL_gm 0x07 /* Bod level group mask. */ -#define BOD_LVL_gp 0 /* Bod level group position. */ -#define BOD_LVL0_bm (1<<0) /* Bod level bit 0 mask. */ -#define BOD_LVL0_bp 0 /* Bod level bit 0 position. */ -#define BOD_LVL1_bm (1<<1) /* Bod level bit 1 mask. */ -#define BOD_LVL1_bp 1 /* Bod level bit 1 position. */ -#define BOD_LVL2_bm (1<<2) /* Bod level bit 2 mask. */ -#define BOD_LVL2_bp 2 /* Bod level bit 2 position. */ - -/* BOD.VLMCTRLA bit masks and bit positions */ -#define BOD_VLMLVL_gm 0x03 /* voltage level monitor level group mask. */ -#define BOD_VLMLVL_gp 0 /* voltage level monitor level group position. */ -#define BOD_VLMLVL0_bm (1<<0) /* voltage level monitor level bit 0 mask. */ -#define BOD_VLMLVL0_bp 0 /* voltage level monitor level bit 0 position. */ -#define BOD_VLMLVL1_bm (1<<1) /* voltage level monitor level bit 1 mask. */ -#define BOD_VLMLVL1_bp 1 /* voltage level monitor level bit 1 position. */ - -/* BOD.INTCTRL bit masks and bit positions */ -#define BOD_VLMIE_bm 0x01 /* voltage level monitor interrrupt enable bit mask. */ -#define BOD_VLMIE_bp 0 /* voltage level monitor interrrupt enable bit position. */ -#define BOD_VLMCFG_gm 0x06 /* Configuration group mask. */ -#define BOD_VLMCFG_gp 1 /* Configuration group position. */ -#define BOD_VLMCFG0_bm (1<<1) /* Configuration bit 0 mask. */ -#define BOD_VLMCFG0_bp 1 /* Configuration bit 0 position. */ -#define BOD_VLMCFG1_bm (1<<2) /* Configuration bit 1 mask. */ -#define BOD_VLMCFG1_bp 2 /* Configuration bit 1 position. */ - -/* BOD.INTFLAGS bit masks and bit positions */ -#define BOD_VLMIF_bm 0x01 /* Voltage level monitor interrupt flag bit mask. */ -#define BOD_VLMIF_bp 0 /* Voltage level monitor interrupt flag bit position. */ - -/* BOD.STATUS bit masks and bit positions */ -#define BOD_VLMS_bm 0x01 /* Voltage level monitor status bit mask. */ -#define BOD_VLMS_bp 0 /* Voltage level monitor status bit position. */ - -/* CCL - Configurable Custom Logic */ -/* CCL.CTRLA bit masks and bit positions */ -#define CCL_ENABLE_bm 0x01 /* Enable bit mask. */ -#define CCL_ENABLE_bp 0 /* Enable bit position. */ -#define CCL_RUNSTDBY_bm 0x40 /* Run in Standby bit mask. */ -#define CCL_RUNSTDBY_bp 6 /* Run in Standby bit position. */ - -/* CCL.SEQCTRL0 bit masks and bit positions */ -#define CCL_SEQSEL_gm 0x07 /* Sequential Selection group mask. */ -#define CCL_SEQSEL_gp 0 /* Sequential Selection group position. */ -#define CCL_SEQSEL0_bm (1<<0) /* Sequential Selection bit 0 mask. */ -#define CCL_SEQSEL0_bp 0 /* Sequential Selection bit 0 position. */ -#define CCL_SEQSEL1_bm (1<<1) /* Sequential Selection bit 1 mask. */ -#define CCL_SEQSEL1_bp 1 /* Sequential Selection bit 1 position. */ -#define CCL_SEQSEL2_bm (1<<2) /* Sequential Selection bit 2 mask. */ -#define CCL_SEQSEL2_bp 2 /* Sequential Selection bit 2 position. */ - -/* CCL.INTCTRL0 bit masks and bit positions */ -#define CCL_INTMODE0_gm 0x03 /* Interrupt Mode for LUT0 group mask. */ -#define CCL_INTMODE0_gp 0 /* Interrupt Mode for LUT0 group position. */ -#define CCL_INTMODE00_bm (1<<0) /* Interrupt Mode for LUT0 bit 0 mask. */ -#define CCL_INTMODE00_bp 0 /* Interrupt Mode for LUT0 bit 0 position. */ -#define CCL_INTMODE01_bm (1<<1) /* Interrupt Mode for LUT0 bit 1 mask. */ -#define CCL_INTMODE01_bp 1 /* Interrupt Mode for LUT0 bit 1 position. */ -#define CCL_INTMODE1_gm 0x0C /* Interrupt Mode for LUT1 group mask. */ -#define CCL_INTMODE1_gp 2 /* Interrupt Mode for LUT1 group position. */ -#define CCL_INTMODE10_bm (1<<2) /* Interrupt Mode for LUT1 bit 0 mask. */ -#define CCL_INTMODE10_bp 2 /* Interrupt Mode for LUT1 bit 0 position. */ -#define CCL_INTMODE11_bm (1<<3) /* Interrupt Mode for LUT1 bit 1 mask. */ -#define CCL_INTMODE11_bp 3 /* Interrupt Mode for LUT1 bit 1 position. */ -#define CCL_INTMODE2_gm 0x30 /* Interrupt Mode for LUT2 group mask. */ -#define CCL_INTMODE2_gp 4 /* Interrupt Mode for LUT2 group position. */ -#define CCL_INTMODE20_bm (1<<4) /* Interrupt Mode for LUT2 bit 0 mask. */ -#define CCL_INTMODE20_bp 4 /* Interrupt Mode for LUT2 bit 0 position. */ -#define CCL_INTMODE21_bm (1<<5) /* Interrupt Mode for LUT2 bit 1 mask. */ -#define CCL_INTMODE21_bp 5 /* Interrupt Mode for LUT2 bit 1 position. */ -#define CCL_INTMODE3_gm 0xC0 /* Interrupt Mode for LUT3 group mask. */ -#define CCL_INTMODE3_gp 6 /* Interrupt Mode for LUT3 group position. */ -#define CCL_INTMODE30_bm (1<<6) /* Interrupt Mode for LUT3 bit 0 mask. */ -#define CCL_INTMODE30_bp 6 /* Interrupt Mode for LUT3 bit 0 position. */ -#define CCL_INTMODE31_bm (1<<7) /* Interrupt Mode for LUT3 bit 1 mask. */ -#define CCL_INTMODE31_bp 7 /* Interrupt Mode for LUT3 bit 1 position. */ - -/* CCL.INTFLAGS bit masks and bit positions */ -#define CCL_INT_gm 0x0F /* Interrupt Flags group mask. */ -#define CCL_INT_gp 0 /* Interrupt Flags group position. */ -#define CCL_INT0_bm (1<<0) /* Interrupt Flags bit 0 mask. */ -#define CCL_INT0_bp 0 /* Interrupt Flags bit 0 position. */ -#define CCL_INT1_bm (1<<1) /* Interrupt Flags bit 1 mask. */ -#define CCL_INT1_bp 1 /* Interrupt Flags bit 1 position. */ -#define CCL_INT2_bm (1<<2) /* Interrupt Flags bit 2 mask. */ -#define CCL_INT2_bp 2 /* Interrupt Flags bit 2 position. */ -#define CCL_INT3_bm (1<<3) /* Interrupt Flags bit 3 mask. */ -#define CCL_INT3_bp 3 /* Interrupt Flags bit 3 position. */ - -/* CCL.LUT0CTRLA bit masks and bit positions */ -/* CCL_ENABLE is already defined. */ -#define CCL_CLKSRC_gm 0x0E /* Clock Source Selection group mask. */ -#define CCL_CLKSRC_gp 1 /* Clock Source Selection group position. */ -#define CCL_CLKSRC0_bm (1<<1) /* Clock Source Selection bit 0 mask. */ -#define CCL_CLKSRC0_bp 1 /* Clock Source Selection bit 0 position. */ -#define CCL_CLKSRC1_bm (1<<2) /* Clock Source Selection bit 1 mask. */ -#define CCL_CLKSRC1_bp 2 /* Clock Source Selection bit 1 position. */ -#define CCL_CLKSRC2_bm (1<<3) /* Clock Source Selection bit 2 mask. */ -#define CCL_CLKSRC2_bp 3 /* Clock Source Selection bit 2 position. */ -#define CCL_FILTSEL_gm 0x30 /* Filter Selection group mask. */ -#define CCL_FILTSEL_gp 4 /* Filter Selection group position. */ -#define CCL_FILTSEL0_bm (1<<4) /* Filter Selection bit 0 mask. */ -#define CCL_FILTSEL0_bp 4 /* Filter Selection bit 0 position. */ -#define CCL_FILTSEL1_bm (1<<5) /* Filter Selection bit 1 mask. */ -#define CCL_FILTSEL1_bp 5 /* Filter Selection bit 1 position. */ -#define CCL_OUTEN_bm 0x40 /* Output Enable bit mask. */ -#define CCL_OUTEN_bp 6 /* Output Enable bit position. */ -#define CCL_EDGEDET_bm 0x80 /* Edge Detection Enable bit mask. */ -#define CCL_EDGEDET_bp 7 /* Edge Detection Enable bit position. */ - -/* CCL.LUT0CTRLB bit masks and bit positions */ -#define CCL_INSEL0_gm 0x0F /* LUT Input 0 Source Selection group mask. */ -#define CCL_INSEL0_gp 0 /* LUT Input 0 Source Selection group position. */ -#define CCL_INSEL00_bm (1<<0) /* LUT Input 0 Source Selection bit 0 mask. */ -#define CCL_INSEL00_bp 0 /* LUT Input 0 Source Selection bit 0 position. */ -#define CCL_INSEL01_bm (1<<1) /* LUT Input 0 Source Selection bit 1 mask. */ -#define CCL_INSEL01_bp 1 /* LUT Input 0 Source Selection bit 1 position. */ -#define CCL_INSEL02_bm (1<<2) /* LUT Input 0 Source Selection bit 2 mask. */ -#define CCL_INSEL02_bp 2 /* LUT Input 0 Source Selection bit 2 position. */ -#define CCL_INSEL03_bm (1<<3) /* LUT Input 0 Source Selection bit 3 mask. */ -#define CCL_INSEL03_bp 3 /* LUT Input 0 Source Selection bit 3 position. */ -#define CCL_INSEL1_gm 0xF0 /* LUT Input 1 Source Selection group mask. */ -#define CCL_INSEL1_gp 4 /* LUT Input 1 Source Selection group position. */ -#define CCL_INSEL10_bm (1<<4) /* LUT Input 1 Source Selection bit 0 mask. */ -#define CCL_INSEL10_bp 4 /* LUT Input 1 Source Selection bit 0 position. */ -#define CCL_INSEL11_bm (1<<5) /* LUT Input 1 Source Selection bit 1 mask. */ -#define CCL_INSEL11_bp 5 /* LUT Input 1 Source Selection bit 1 position. */ -#define CCL_INSEL12_bm (1<<6) /* LUT Input 1 Source Selection bit 2 mask. */ -#define CCL_INSEL12_bp 6 /* LUT Input 1 Source Selection bit 2 position. */ -#define CCL_INSEL13_bm (1<<7) /* LUT Input 1 Source Selection bit 3 mask. */ -#define CCL_INSEL13_bp 7 /* LUT Input 1 Source Selection bit 3 position. */ - -/* CCL.LUT0CTRLC bit masks and bit positions */ -#define CCL_INSEL2_gm 0x0F /* LUT Input 2 Source Selection group mask. */ -#define CCL_INSEL2_gp 0 /* LUT Input 2 Source Selection group position. */ -#define CCL_INSEL20_bm (1<<0) /* LUT Input 2 Source Selection bit 0 mask. */ -#define CCL_INSEL20_bp 0 /* LUT Input 2 Source Selection bit 0 position. */ -#define CCL_INSEL21_bm (1<<1) /* LUT Input 2 Source Selection bit 1 mask. */ -#define CCL_INSEL21_bp 1 /* LUT Input 2 Source Selection bit 1 position. */ -#define CCL_INSEL22_bm (1<<2) /* LUT Input 2 Source Selection bit 2 mask. */ -#define CCL_INSEL22_bp 2 /* LUT Input 2 Source Selection bit 2 position. */ -#define CCL_INSEL23_bm (1<<3) /* LUT Input 2 Source Selection bit 3 mask. */ -#define CCL_INSEL23_bp 3 /* LUT Input 2 Source Selection bit 3 position. */ - - -/* CCL.LUT1CTRLA bit masks and bit positions */ -/* CCL_ENABLE is already defined. */ -/* CCL_CLKSRC is already defined. */ -/* CCL_FILTSEL is already defined. */ -/* CCL_OUTEN is already defined. */ -/* CCL_EDGEDET is already defined. */ - -/* CCL.LUT1CTRLB bit masks and bit positions */ -/* CCL_INSEL0 is already defined. */ -/* CCL_INSEL1 is already defined. */ - -/* CCL.LUT1CTRLC bit masks and bit positions */ -/* CCL_INSEL2 is already defined. */ - - -/* CCL.LUT2CTRLA bit masks and bit positions */ -/* CCL_ENABLE is already defined. */ -/* CCL_CLKSRC is already defined. */ -/* CCL_FILTSEL is already defined. */ -/* CCL_OUTEN is already defined. */ -/* CCL_EDGEDET is already defined. */ - -/* CCL.LUT2CTRLB bit masks and bit positions */ -/* CCL_INSEL0 is already defined. */ -/* CCL_INSEL1 is already defined. */ - -/* CCL.LUT2CTRLC bit masks and bit positions */ -/* CCL_INSEL2 is already defined. */ - - -/* CCL.LUT3CTRLA bit masks and bit positions */ -/* CCL_ENABLE is already defined. */ -/* CCL_CLKSRC is already defined. */ -/* CCL_FILTSEL is already defined. */ -/* CCL_OUTEN is already defined. */ -/* CCL_EDGEDET is already defined. */ - -/* CCL.LUT3CTRLB bit masks and bit positions */ -/* CCL_INSEL0 is already defined. */ -/* CCL_INSEL1 is already defined. */ - -/* CCL.LUT3CTRLC bit masks and bit positions */ -/* CCL_INSEL2 is already defined. */ - - -/* CLKCTRL - Clock controller */ -/* CLKCTRL.MCLKCTRLA bit masks and bit positions */ -#define CLKCTRL_CLKSEL_gm 0x03 /* clock select group mask. */ -#define CLKCTRL_CLKSEL_gp 0 /* clock select group position. */ -#define CLKCTRL_CLKSEL0_bm (1<<0) /* clock select bit 0 mask. */ -#define CLKCTRL_CLKSEL0_bp 0 /* clock select bit 0 position. */ -#define CLKCTRL_CLKSEL1_bm (1<<1) /* clock select bit 1 mask. */ -#define CLKCTRL_CLKSEL1_bp 1 /* clock select bit 1 position. */ -#define CLKCTRL_CLKOUT_bm 0x80 /* System clock out bit mask. */ -#define CLKCTRL_CLKOUT_bp 7 /* System clock out bit position. */ - -/* CLKCTRL.MCLKCTRLB bit masks and bit positions */ -#define CLKCTRL_PEN_bm 0x01 /* Prescaler enable bit mask. */ -#define CLKCTRL_PEN_bp 0 /* Prescaler enable bit position. */ -#define CLKCTRL_PDIV_gm 0x1E /* Prescaler division group mask. */ -#define CLKCTRL_PDIV_gp 1 /* Prescaler division group position. */ -#define CLKCTRL_PDIV0_bm (1<<1) /* Prescaler division bit 0 mask. */ -#define CLKCTRL_PDIV0_bp 1 /* Prescaler division bit 0 position. */ -#define CLKCTRL_PDIV1_bm (1<<2) /* Prescaler division bit 1 mask. */ -#define CLKCTRL_PDIV1_bp 2 /* Prescaler division bit 1 position. */ -#define CLKCTRL_PDIV2_bm (1<<3) /* Prescaler division bit 2 mask. */ -#define CLKCTRL_PDIV2_bp 3 /* Prescaler division bit 2 position. */ -#define CLKCTRL_PDIV3_bm (1<<4) /* Prescaler division bit 3 mask. */ -#define CLKCTRL_PDIV3_bp 4 /* Prescaler division bit 3 position. */ - -/* CLKCTRL.MCLKLOCK bit masks and bit positions */ -#define CLKCTRL_LOCKEN_bm 0x01 /* lock ebable bit mask. */ -#define CLKCTRL_LOCKEN_bp 0 /* lock ebable bit position. */ - -/* CLKCTRL.MCLKSTATUS bit masks and bit positions */ -#define CLKCTRL_SOSC_bm 0x01 /* System Oscillator changing bit mask. */ -#define CLKCTRL_SOSC_bp 0 /* System Oscillator changing bit position. */ -#define CLKCTRL_OSC20MS_bm 0x10 /* 20MHz oscillator status bit mask. */ -#define CLKCTRL_OSC20MS_bp 4 /* 20MHz oscillator status bit position. */ -#define CLKCTRL_OSC32KS_bm 0x20 /* 32KHz oscillator status bit mask. */ -#define CLKCTRL_OSC32KS_bp 5 /* 32KHz oscillator status bit position. */ -#define CLKCTRL_XOSC32KS_bm 0x40 /* 32.768 kHz Crystal Oscillator status bit mask. */ -#define CLKCTRL_XOSC32KS_bp 6 /* 32.768 kHz Crystal Oscillator status bit position. */ -#define CLKCTRL_EXTS_bm 0x80 /* External Clock status bit mask. */ -#define CLKCTRL_EXTS_bp 7 /* External Clock status bit position. */ - -/* CLKCTRL.OSC20MCTRLA bit masks and bit positions */ -#define CLKCTRL_RUNSTDBY_bm 0x02 /* Run standby bit mask. */ -#define CLKCTRL_RUNSTDBY_bp 1 /* Run standby bit position. */ - -/* CLKCTRL.OSC20MCALIBA bit masks and bit positions */ -#define CLKCTRL_CAL20M_gm 0x7F /* Calibration group mask. */ -#define CLKCTRL_CAL20M_gp 0 /* Calibration group position. */ -#define CLKCTRL_CAL20M0_bm (1<<0) /* Calibration bit 0 mask. */ -#define CLKCTRL_CAL20M0_bp 0 /* Calibration bit 0 position. */ -#define CLKCTRL_CAL20M1_bm (1<<1) /* Calibration bit 1 mask. */ -#define CLKCTRL_CAL20M1_bp 1 /* Calibration bit 1 position. */ -#define CLKCTRL_CAL20M2_bm (1<<2) /* Calibration bit 2 mask. */ -#define CLKCTRL_CAL20M2_bp 2 /* Calibration bit 2 position. */ -#define CLKCTRL_CAL20M3_bm (1<<3) /* Calibration bit 3 mask. */ -#define CLKCTRL_CAL20M3_bp 3 /* Calibration bit 3 position. */ -#define CLKCTRL_CAL20M4_bm (1<<4) /* Calibration bit 4 mask. */ -#define CLKCTRL_CAL20M4_bp 4 /* Calibration bit 4 position. */ -#define CLKCTRL_CAL20M5_bm (1<<5) /* Calibration bit 5 mask. */ -#define CLKCTRL_CAL20M5_bp 5 /* Calibration bit 5 position. */ -#define CLKCTRL_CAL20M6_bm (1<<6) /* Calibration bit 6 mask. */ -#define CLKCTRL_CAL20M6_bp 6 /* Calibration bit 6 position. */ -#define CLKCTRL_CALSEL20M_bm 0x80 /* Calibration freq select bit mask. */ -#define CLKCTRL_CALSEL20M_bp 7 /* Calibration freq select bit position. */ - -/* CLKCTRL.OSC20MCALIBB bit masks and bit positions */ -#define CLKCTRL_TEMPCAL20M_gm 0x0F /* Oscillator temperature coefficient group mask. */ -#define CLKCTRL_TEMPCAL20M_gp 0 /* Oscillator temperature coefficient group position. */ -#define CLKCTRL_TEMPCAL20M0_bm (1<<0) /* Oscillator temperature coefficient bit 0 mask. */ -#define CLKCTRL_TEMPCAL20M0_bp 0 /* Oscillator temperature coefficient bit 0 position. */ -#define CLKCTRL_TEMPCAL20M1_bm (1<<1) /* Oscillator temperature coefficient bit 1 mask. */ -#define CLKCTRL_TEMPCAL20M1_bp 1 /* Oscillator temperature coefficient bit 1 position. */ -#define CLKCTRL_TEMPCAL20M2_bm (1<<2) /* Oscillator temperature coefficient bit 2 mask. */ -#define CLKCTRL_TEMPCAL20M2_bp 2 /* Oscillator temperature coefficient bit 2 position. */ -#define CLKCTRL_TEMPCAL20M3_bm (1<<3) /* Oscillator temperature coefficient bit 3 mask. */ -#define CLKCTRL_TEMPCAL20M3_bp 3 /* Oscillator temperature coefficient bit 3 position. */ -#define CLKCTRL_LOCK_bm 0x80 /* Lock bit mask. */ -#define CLKCTRL_LOCK_bp 7 /* Lock bit position. */ - -/* CLKCTRL.OSC32KCTRLA bit masks and bit positions */ -/* CLKCTRL_RUNSTDBY is already defined. */ - -/* CLKCTRL.OSC32KCALIB bit masks and bit positions */ -#define CLKCTRL_CAL32K_gm 0x3F /* Calibration group mask. */ -#define CLKCTRL_CAL32K_gp 0 /* Calibration group position. */ -#define CLKCTRL_CAL32K0_bm (1<<0) /* Calibration bit 0 mask. */ -#define CLKCTRL_CAL32K0_bp 0 /* Calibration bit 0 position. */ -#define CLKCTRL_CAL32K1_bm (1<<1) /* Calibration bit 1 mask. */ -#define CLKCTRL_CAL32K1_bp 1 /* Calibration bit 1 position. */ -#define CLKCTRL_CAL32K2_bm (1<<2) /* Calibration bit 2 mask. */ -#define CLKCTRL_CAL32K2_bp 2 /* Calibration bit 2 position. */ -#define CLKCTRL_CAL32K3_bm (1<<3) /* Calibration bit 3 mask. */ -#define CLKCTRL_CAL32K3_bp 3 /* Calibration bit 3 position. */ -#define CLKCTRL_CAL32K4_bm (1<<4) /* Calibration bit 4 mask. */ -#define CLKCTRL_CAL32K4_bp 4 /* Calibration bit 4 position. */ -#define CLKCTRL_CAL32K5_bm (1<<5) /* Calibration bit 5 mask. */ -#define CLKCTRL_CAL32K5_bp 5 /* Calibration bit 5 position. */ - -/* CLKCTRL.XOSC32KCTRLA bit masks and bit positions */ -#define CLKCTRL_ENABLE_bm 0x01 /* Enable bit mask. */ -#define CLKCTRL_ENABLE_bp 0 /* Enable bit position. */ -/* CLKCTRL_RUNSTDBY is already defined. */ -#define CLKCTRL_SEL_bm 0x04 /* Select bit mask. */ -#define CLKCTRL_SEL_bp 2 /* Select bit position. */ -#define CLKCTRL_CSUT_gm 0x30 /* Crystal startup time group mask. */ -#define CLKCTRL_CSUT_gp 4 /* Crystal startup time group position. */ -#define CLKCTRL_CSUT0_bm (1<<4) /* Crystal startup time bit 0 mask. */ -#define CLKCTRL_CSUT0_bp 4 /* Crystal startup time bit 0 position. */ -#define CLKCTRL_CSUT1_bm (1<<5) /* Crystal startup time bit 1 mask. */ -#define CLKCTRL_CSUT1_bp 5 /* Crystal startup time bit 1 position. */ - -/* CPU - CPU */ -/* CPU.CCP bit masks and bit positions */ -#define CPU_CCP_gm 0xFF /* CCP signature group mask. */ -#define CPU_CCP_gp 0 /* CCP signature group position. */ -#define CPU_CCP0_bm (1<<0) /* CCP signature bit 0 mask. */ -#define CPU_CCP0_bp 0 /* CCP signature bit 0 position. */ -#define CPU_CCP1_bm (1<<1) /* CCP signature bit 1 mask. */ -#define CPU_CCP1_bp 1 /* CCP signature bit 1 position. */ -#define CPU_CCP2_bm (1<<2) /* CCP signature bit 2 mask. */ -#define CPU_CCP2_bp 2 /* CCP signature bit 2 position. */ -#define CPU_CCP3_bm (1<<3) /* CCP signature bit 3 mask. */ -#define CPU_CCP3_bp 3 /* CCP signature bit 3 position. */ -#define CPU_CCP4_bm (1<<4) /* CCP signature bit 4 mask. */ -#define CPU_CCP4_bp 4 /* CCP signature bit 4 position. */ -#define CPU_CCP5_bm (1<<5) /* CCP signature bit 5 mask. */ -#define CPU_CCP5_bp 5 /* CCP signature bit 5 position. */ -#define CPU_CCP6_bm (1<<6) /* CCP signature bit 6 mask. */ -#define CPU_CCP6_bp 6 /* CCP signature bit 6 position. */ -#define CPU_CCP7_bm (1<<7) /* CCP signature bit 7 mask. */ -#define CPU_CCP7_bp 7 /* CCP signature bit 7 position. */ - - - - -/* CPU.SREG bit masks and bit positions */ -#define CPU_C_bm 0x01 /* Carry Flag bit mask. */ -#define CPU_C_bp 0 /* Carry Flag bit position. */ -#define CPU_Z_bm 0x02 /* Zero Flag bit mask. */ -#define CPU_Z_bp 1 /* Zero Flag bit position. */ -#define CPU_N_bm 0x04 /* Negative Flag bit mask. */ -#define CPU_N_bp 2 /* Negative Flag bit position. */ -#define CPU_V_bm 0x08 /* Two's Complement Overflow Flag bit mask. */ -#define CPU_V_bp 3 /* Two's Complement Overflow Flag bit position. */ -#define CPU_S_bm 0x10 /* N Exclusive Or V Flag bit mask. */ -#define CPU_S_bp 4 /* N Exclusive Or V Flag bit position. */ -#define CPU_H_bm 0x20 /* Half Carry Flag bit mask. */ -#define CPU_H_bp 5 /* Half Carry Flag bit position. */ -#define CPU_T_bm 0x40 /* Transfer Bit bit mask. */ -#define CPU_T_bp 6 /* Transfer Bit bit position. */ -#define CPU_I_bm 0x80 /* Global Interrupt Enable Flag bit mask. */ -#define CPU_I_bp 7 /* Global Interrupt Enable Flag bit position. */ - -/* CPUINT - Interrupt Controller */ -/* CPUINT.CTRLA bit masks and bit positions */ -#define CPUINT_LVL0RR_bm 0x01 /* Round-robin Scheduling Enable bit mask. */ -#define CPUINT_LVL0RR_bp 0 /* Round-robin Scheduling Enable bit position. */ -#define CPUINT_CVT_bm 0x20 /* Compact Vector Table bit mask. */ -#define CPUINT_CVT_bp 5 /* Compact Vector Table bit position. */ -#define CPUINT_IVSEL_bm 0x40 /* Interrupt Vector Select bit mask. */ -#define CPUINT_IVSEL_bp 6 /* Interrupt Vector Select bit position. */ - -/* CPUINT.STATUS bit masks and bit positions */ -#define CPUINT_LVL0EX_bm 0x01 /* Level 0 Interrupt Executing bit mask. */ -#define CPUINT_LVL0EX_bp 0 /* Level 0 Interrupt Executing bit position. */ -#define CPUINT_LVL1EX_bm 0x02 /* Level 1 Interrupt Executing bit mask. */ -#define CPUINT_LVL1EX_bp 1 /* Level 1 Interrupt Executing bit position. */ -#define CPUINT_NMIEX_bm 0x80 /* Non-maskable Interrupt Executing bit mask. */ -#define CPUINT_NMIEX_bp 7 /* Non-maskable Interrupt Executing bit position. */ - -/* CPUINT.LVL0PRI bit masks and bit positions */ -#define CPUINT_LVL0PRI_gm 0xFF /* Interrupt Level Priority group mask. */ -#define CPUINT_LVL0PRI_gp 0 /* Interrupt Level Priority group position. */ -#define CPUINT_LVL0PRI0_bm (1<<0) /* Interrupt Level Priority bit 0 mask. */ -#define CPUINT_LVL0PRI0_bp 0 /* Interrupt Level Priority bit 0 position. */ -#define CPUINT_LVL0PRI1_bm (1<<1) /* Interrupt Level Priority bit 1 mask. */ -#define CPUINT_LVL0PRI1_bp 1 /* Interrupt Level Priority bit 1 position. */ -#define CPUINT_LVL0PRI2_bm (1<<2) /* Interrupt Level Priority bit 2 mask. */ -#define CPUINT_LVL0PRI2_bp 2 /* Interrupt Level Priority bit 2 position. */ -#define CPUINT_LVL0PRI3_bm (1<<3) /* Interrupt Level Priority bit 3 mask. */ -#define CPUINT_LVL0PRI3_bp 3 /* Interrupt Level Priority bit 3 position. */ -#define CPUINT_LVL0PRI4_bm (1<<4) /* Interrupt Level Priority bit 4 mask. */ -#define CPUINT_LVL0PRI4_bp 4 /* Interrupt Level Priority bit 4 position. */ -#define CPUINT_LVL0PRI5_bm (1<<5) /* Interrupt Level Priority bit 5 mask. */ -#define CPUINT_LVL0PRI5_bp 5 /* Interrupt Level Priority bit 5 position. */ -#define CPUINT_LVL0PRI6_bm (1<<6) /* Interrupt Level Priority bit 6 mask. */ -#define CPUINT_LVL0PRI6_bp 6 /* Interrupt Level Priority bit 6 position. */ -#define CPUINT_LVL0PRI7_bm (1<<7) /* Interrupt Level Priority bit 7 mask. */ -#define CPUINT_LVL0PRI7_bp 7 /* Interrupt Level Priority bit 7 position. */ - -/* CPUINT.LVL1VEC bit masks and bit positions */ -#define CPUINT_LVL1VEC_gm 0xFF /* Interrupt Vector with High Priority group mask. */ -#define CPUINT_LVL1VEC_gp 0 /* Interrupt Vector with High Priority group position. */ -#define CPUINT_LVL1VEC0_bm (1<<0) /* Interrupt Vector with High Priority bit 0 mask. */ -#define CPUINT_LVL1VEC0_bp 0 /* Interrupt Vector with High Priority bit 0 position. */ -#define CPUINT_LVL1VEC1_bm (1<<1) /* Interrupt Vector with High Priority bit 1 mask. */ -#define CPUINT_LVL1VEC1_bp 1 /* Interrupt Vector with High Priority bit 1 position. */ -#define CPUINT_LVL1VEC2_bm (1<<2) /* Interrupt Vector with High Priority bit 2 mask. */ -#define CPUINT_LVL1VEC2_bp 2 /* Interrupt Vector with High Priority bit 2 position. */ -#define CPUINT_LVL1VEC3_bm (1<<3) /* Interrupt Vector with High Priority bit 3 mask. */ -#define CPUINT_LVL1VEC3_bp 3 /* Interrupt Vector with High Priority bit 3 position. */ -#define CPUINT_LVL1VEC4_bm (1<<4) /* Interrupt Vector with High Priority bit 4 mask. */ -#define CPUINT_LVL1VEC4_bp 4 /* Interrupt Vector with High Priority bit 4 position. */ -#define CPUINT_LVL1VEC5_bm (1<<5) /* Interrupt Vector with High Priority bit 5 mask. */ -#define CPUINT_LVL1VEC5_bp 5 /* Interrupt Vector with High Priority bit 5 position. */ -#define CPUINT_LVL1VEC6_bm (1<<6) /* Interrupt Vector with High Priority bit 6 mask. */ -#define CPUINT_LVL1VEC6_bp 6 /* Interrupt Vector with High Priority bit 6 position. */ -#define CPUINT_LVL1VEC7_bm (1<<7) /* Interrupt Vector with High Priority bit 7 mask. */ -#define CPUINT_LVL1VEC7_bp 7 /* Interrupt Vector with High Priority bit 7 position. */ - -/* CRCSCAN - CRCSCAN */ -/* CRCSCAN.CTRLA bit masks and bit positions */ -#define CRCSCAN_ENABLE_bm 0x01 /* Enable CRC scan bit mask. */ -#define CRCSCAN_ENABLE_bp 0 /* Enable CRC scan bit position. */ -#define CRCSCAN_NMIEN_bm 0x02 /* Enable NMI Trigger bit mask. */ -#define CRCSCAN_NMIEN_bp 1 /* Enable NMI Trigger bit position. */ -#define CRCSCAN_RESET_bm 0x80 /* Reset CRC scan bit mask. */ -#define CRCSCAN_RESET_bp 7 /* Reset CRC scan bit position. */ - -/* CRCSCAN.CTRLB bit masks and bit positions */ -#define CRCSCAN_SRC_gm 0x03 /* CRC Source group mask. */ -#define CRCSCAN_SRC_gp 0 /* CRC Source group position. */ -#define CRCSCAN_SRC0_bm (1<<0) /* CRC Source bit 0 mask. */ -#define CRCSCAN_SRC0_bp 0 /* CRC Source bit 0 position. */ -#define CRCSCAN_SRC1_bm (1<<1) /* CRC Source bit 1 mask. */ -#define CRCSCAN_SRC1_bp 1 /* CRC Source bit 1 position. */ -#define CRCSCAN_MODE_gm 0x30 /* CRC Flash Access Mode group mask. */ -#define CRCSCAN_MODE_gp 4 /* CRC Flash Access Mode group position. */ -#define CRCSCAN_MODE0_bm (1<<4) /* CRC Flash Access Mode bit 0 mask. */ -#define CRCSCAN_MODE0_bp 4 /* CRC Flash Access Mode bit 0 position. */ -#define CRCSCAN_MODE1_bm (1<<5) /* CRC Flash Access Mode bit 1 mask. */ -#define CRCSCAN_MODE1_bp 5 /* CRC Flash Access Mode bit 1 position. */ - -/* CRCSCAN.STATUS bit masks and bit positions */ -#define CRCSCAN_BUSY_bm 0x01 /* CRC Busy bit mask. */ -#define CRCSCAN_BUSY_bp 0 /* CRC Busy bit position. */ -#define CRCSCAN_OK_bm 0x02 /* CRC Ok bit mask. */ -#define CRCSCAN_OK_bp 1 /* CRC Ok bit position. */ - -/* EVSYS - Event System */ -/* EVSYS.STROBE bit masks and bit positions */ -#define EVSYS_STROBE0_gm 0xFF /* Software event on channels group mask. */ -#define EVSYS_STROBE0_gp 0 /* Software event on channels group position. */ -#define EVSYS_STROBE00_bm (1<<0) /* Software event on channels bit 0 mask. */ -#define EVSYS_STROBE00_bp 0 /* Software event on channels bit 0 position. */ -#define EVSYS_STROBE01_bm (1<<1) /* Software event on channels bit 1 mask. */ -#define EVSYS_STROBE01_bp 1 /* Software event on channels bit 1 position. */ -#define EVSYS_STROBE02_bm (1<<2) /* Software event on channels bit 2 mask. */ -#define EVSYS_STROBE02_bp 2 /* Software event on channels bit 2 position. */ -#define EVSYS_STROBE03_bm (1<<3) /* Software event on channels bit 3 mask. */ -#define EVSYS_STROBE03_bp 3 /* Software event on channels bit 3 position. */ -#define EVSYS_STROBE04_bm (1<<4) /* Software event on channels bit 4 mask. */ -#define EVSYS_STROBE04_bp 4 /* Software event on channels bit 4 position. */ -#define EVSYS_STROBE05_bm (1<<5) /* Software event on channels bit 5 mask. */ -#define EVSYS_STROBE05_bp 5 /* Software event on channels bit 5 position. */ -#define EVSYS_STROBE06_bm (1<<6) /* Software event on channels bit 6 mask. */ -#define EVSYS_STROBE06_bp 6 /* Software event on channels bit 6 position. */ -#define EVSYS_STROBE07_bm (1<<7) /* Software event on channels bit 7 mask. */ -#define EVSYS_STROBE07_bp 7 /* Software event on channels bit 7 position. */ - -/* EVSYS.CHANNEL0 bit masks and bit positions */ -#define EVSYS_GENERATOR_gm 0xFF /* Generator selector group mask. */ -#define EVSYS_GENERATOR_gp 0 /* Generator selector group position. */ -#define EVSYS_GENERATOR0_bm (1<<0) /* Generator selector bit 0 mask. */ -#define EVSYS_GENERATOR0_bp 0 /* Generator selector bit 0 position. */ -#define EVSYS_GENERATOR1_bm (1<<1) /* Generator selector bit 1 mask. */ -#define EVSYS_GENERATOR1_bp 1 /* Generator selector bit 1 position. */ -#define EVSYS_GENERATOR2_bm (1<<2) /* Generator selector bit 2 mask. */ -#define EVSYS_GENERATOR2_bp 2 /* Generator selector bit 2 position. */ -#define EVSYS_GENERATOR3_bm (1<<3) /* Generator selector bit 3 mask. */ -#define EVSYS_GENERATOR3_bp 3 /* Generator selector bit 3 position. */ -#define EVSYS_GENERATOR4_bm (1<<4) /* Generator selector bit 4 mask. */ -#define EVSYS_GENERATOR4_bp 4 /* Generator selector bit 4 position. */ -#define EVSYS_GENERATOR5_bm (1<<5) /* Generator selector bit 5 mask. */ -#define EVSYS_GENERATOR5_bp 5 /* Generator selector bit 5 position. */ -#define EVSYS_GENERATOR6_bm (1<<6) /* Generator selector bit 6 mask. */ -#define EVSYS_GENERATOR6_bp 6 /* Generator selector bit 6 position. */ -#define EVSYS_GENERATOR7_bm (1<<7) /* Generator selector bit 7 mask. */ -#define EVSYS_GENERATOR7_bp 7 /* Generator selector bit 7 position. */ - -/* EVSYS.CHANNEL1 bit masks and bit positions */ -/* EVSYS_GENERATOR is already defined. */ - -/* EVSYS.CHANNEL2 bit masks and bit positions */ -/* EVSYS_GENERATOR is already defined. */ - -/* EVSYS.CHANNEL3 bit masks and bit positions */ -/* EVSYS_GENERATOR is already defined. */ - -/* EVSYS.CHANNEL4 bit masks and bit positions */ -/* EVSYS_GENERATOR is already defined. */ - -/* EVSYS.CHANNEL5 bit masks and bit positions */ -/* EVSYS_GENERATOR is already defined. */ - -/* EVSYS.CHANNEL6 bit masks and bit positions */ -/* EVSYS_GENERATOR is already defined. */ - -/* EVSYS.CHANNEL7 bit masks and bit positions */ -/* EVSYS_GENERATOR is already defined. */ - -/* EVSYS.USERCCLLUT0A bit masks and bit positions */ -#define EVSYS_CHANNEL_gm 0xFF /* Channel selector group mask. */ -#define EVSYS_CHANNEL_gp 0 /* Channel selector group position. */ -#define EVSYS_CHANNEL0_bm (1<<0) /* Channel selector bit 0 mask. */ -#define EVSYS_CHANNEL0_bp 0 /* Channel selector bit 0 position. */ -#define EVSYS_CHANNEL1_bm (1<<1) /* Channel selector bit 1 mask. */ -#define EVSYS_CHANNEL1_bp 1 /* Channel selector bit 1 position. */ -#define EVSYS_CHANNEL2_bm (1<<2) /* Channel selector bit 2 mask. */ -#define EVSYS_CHANNEL2_bp 2 /* Channel selector bit 2 position. */ -#define EVSYS_CHANNEL3_bm (1<<3) /* Channel selector bit 3 mask. */ -#define EVSYS_CHANNEL3_bp 3 /* Channel selector bit 3 position. */ -#define EVSYS_CHANNEL4_bm (1<<4) /* Channel selector bit 4 mask. */ -#define EVSYS_CHANNEL4_bp 4 /* Channel selector bit 4 position. */ -#define EVSYS_CHANNEL5_bm (1<<5) /* Channel selector bit 5 mask. */ -#define EVSYS_CHANNEL5_bp 5 /* Channel selector bit 5 position. */ -#define EVSYS_CHANNEL6_bm (1<<6) /* Channel selector bit 6 mask. */ -#define EVSYS_CHANNEL6_bp 6 /* Channel selector bit 6 position. */ -#define EVSYS_CHANNEL7_bm (1<<7) /* Channel selector bit 7 mask. */ -#define EVSYS_CHANNEL7_bp 7 /* Channel selector bit 7 position. */ - -/* EVSYS.USERCCLLUT0B bit masks and bit positions */ -/* EVSYS_CHANNEL is already defined. */ - -/* EVSYS.USERCCLLUT1A bit masks and bit positions */ -/* EVSYS_CHANNEL is already defined. */ - -/* EVSYS.USERCCLLUT1B bit masks and bit positions */ -/* EVSYS_CHANNEL is already defined. */ - -/* EVSYS.USERCCLLUT2A bit masks and bit positions */ -/* EVSYS_CHANNEL is already defined. */ - -/* EVSYS.USERCCLLUT2B bit masks and bit positions */ -/* EVSYS_CHANNEL is already defined. */ - -/* EVSYS.USERCCLLUT3A bit masks and bit positions */ -/* EVSYS_CHANNEL is already defined. */ - -/* EVSYS.USERCCLLUT3B bit masks and bit positions */ -/* EVSYS_CHANNEL is already defined. */ - -/* EVSYS.USERADC0 bit masks and bit positions */ -/* EVSYS_CHANNEL is already defined. */ - -/* EVSYS.USEREVOUTA bit masks and bit positions */ -/* EVSYS_CHANNEL is already defined. */ - -/* EVSYS.USEREVOUTB bit masks and bit positions */ -/* EVSYS_CHANNEL is already defined. */ - -/* EVSYS.USEREVOUTC bit masks and bit positions */ -/* EVSYS_CHANNEL is already defined. */ - -/* EVSYS.USEREVOUTD bit masks and bit positions */ -/* EVSYS_CHANNEL is already defined. */ - -/* EVSYS.USEREVOUTE bit masks and bit positions */ -/* EVSYS_CHANNEL is already defined. */ - -/* EVSYS.USEREVOUTF bit masks and bit positions */ -/* EVSYS_CHANNEL is already defined. */ - -/* EVSYS.USERUSART0 bit masks and bit positions */ -/* EVSYS_CHANNEL is already defined. */ - -/* EVSYS.USERUSART1 bit masks and bit positions */ -/* EVSYS_CHANNEL is already defined. */ - -/* EVSYS.USERUSART2 bit masks and bit positions */ -/* EVSYS_CHANNEL is already defined. */ - -/* EVSYS.USERUSART3 bit masks and bit positions */ -/* EVSYS_CHANNEL is already defined. */ - -/* EVSYS.USERTCA0 bit masks and bit positions */ -/* EVSYS_CHANNEL is already defined. */ - -/* EVSYS.USERTCB0 bit masks and bit positions */ -/* EVSYS_CHANNEL is already defined. */ - -/* EVSYS.USERTCB1 bit masks and bit positions */ -/* EVSYS_CHANNEL is already defined. */ - -/* EVSYS.USERTCB2 bit masks and bit positions */ -/* EVSYS_CHANNEL is already defined. */ - -/* EVSYS.USERTCB3 bit masks and bit positions */ -/* EVSYS_CHANNEL is already defined. */ - -/* FUSE - Fuses */ -/* FUSE.WDTCFG bit masks and bit positions */ -#define FUSE_PERIOD_gm 0x0F /* Watchdog Timeout Period group mask. */ -#define FUSE_PERIOD_gp 0 /* Watchdog Timeout Period group position. */ -#define FUSE_PERIOD0_bm (1<<0) /* Watchdog Timeout Period bit 0 mask. */ -#define FUSE_PERIOD0_bp 0 /* Watchdog Timeout Period bit 0 position. */ -#define FUSE_PERIOD1_bm (1<<1) /* Watchdog Timeout Period bit 1 mask. */ -#define FUSE_PERIOD1_bp 1 /* Watchdog Timeout Period bit 1 position. */ -#define FUSE_PERIOD2_bm (1<<2) /* Watchdog Timeout Period bit 2 mask. */ -#define FUSE_PERIOD2_bp 2 /* Watchdog Timeout Period bit 2 position. */ -#define FUSE_PERIOD3_bm (1<<3) /* Watchdog Timeout Period bit 3 mask. */ -#define FUSE_PERIOD3_bp 3 /* Watchdog Timeout Period bit 3 position. */ -#define FUSE_WINDOW_gm 0xF0 /* Watchdog Window Timeout Period group mask. */ -#define FUSE_WINDOW_gp 4 /* Watchdog Window Timeout Period group position. */ -#define FUSE_WINDOW0_bm (1<<4) /* Watchdog Window Timeout Period bit 0 mask. */ -#define FUSE_WINDOW0_bp 4 /* Watchdog Window Timeout Period bit 0 position. */ -#define FUSE_WINDOW1_bm (1<<5) /* Watchdog Window Timeout Period bit 1 mask. */ -#define FUSE_WINDOW1_bp 5 /* Watchdog Window Timeout Period bit 1 position. */ -#define FUSE_WINDOW2_bm (1<<6) /* Watchdog Window Timeout Period bit 2 mask. */ -#define FUSE_WINDOW2_bp 6 /* Watchdog Window Timeout Period bit 2 position. */ -#define FUSE_WINDOW3_bm (1<<7) /* Watchdog Window Timeout Period bit 3 mask. */ -#define FUSE_WINDOW3_bp 7 /* Watchdog Window Timeout Period bit 3 position. */ - -/* FUSE.BODCFG bit masks and bit positions */ -#define FUSE_SLEEP_gm 0x03 /* BOD Operation in Sleep Mode group mask. */ -#define FUSE_SLEEP_gp 0 /* BOD Operation in Sleep Mode group position. */ -#define FUSE_SLEEP0_bm (1<<0) /* BOD Operation in Sleep Mode bit 0 mask. */ -#define FUSE_SLEEP0_bp 0 /* BOD Operation in Sleep Mode bit 0 position. */ -#define FUSE_SLEEP1_bm (1<<1) /* BOD Operation in Sleep Mode bit 1 mask. */ -#define FUSE_SLEEP1_bp 1 /* BOD Operation in Sleep Mode bit 1 position. */ -#define FUSE_ACTIVE_gm 0x0C /* BOD Operation in Active Mode group mask. */ -#define FUSE_ACTIVE_gp 2 /* BOD Operation in Active Mode group position. */ -#define FUSE_ACTIVE0_bm (1<<2) /* BOD Operation in Active Mode bit 0 mask. */ -#define FUSE_ACTIVE0_bp 2 /* BOD Operation in Active Mode bit 0 position. */ -#define FUSE_ACTIVE1_bm (1<<3) /* BOD Operation in Active Mode bit 1 mask. */ -#define FUSE_ACTIVE1_bp 3 /* BOD Operation in Active Mode bit 1 position. */ -#define FUSE_SAMPFREQ_bm 0x10 /* BOD Sample Frequency bit mask. */ -#define FUSE_SAMPFREQ_bp 4 /* BOD Sample Frequency bit position. */ -#define FUSE_LVL_gm 0xE0 /* BOD Level group mask. */ -#define FUSE_LVL_gp 5 /* BOD Level group position. */ -#define FUSE_LVL0_bm (1<<5) /* BOD Level bit 0 mask. */ -#define FUSE_LVL0_bp 5 /* BOD Level bit 0 position. */ -#define FUSE_LVL1_bm (1<<6) /* BOD Level bit 1 mask. */ -#define FUSE_LVL1_bp 6 /* BOD Level bit 1 position. */ -#define FUSE_LVL2_bm (1<<7) /* BOD Level bit 2 mask. */ -#define FUSE_LVL2_bp 7 /* BOD Level bit 2 position. */ - -/* FUSE.OSCCFG bit masks and bit positions */ -#define FUSE_FREQSEL_gm 0x03 /* Frequency Select group mask. */ -#define FUSE_FREQSEL_gp 0 /* Frequency Select group position. */ -#define FUSE_FREQSEL0_bm (1<<0) /* Frequency Select bit 0 mask. */ -#define FUSE_FREQSEL0_bp 0 /* Frequency Select bit 0 position. */ -#define FUSE_FREQSEL1_bm (1<<1) /* Frequency Select bit 1 mask. */ -#define FUSE_FREQSEL1_bp 1 /* Frequency Select bit 1 position. */ -#define FUSE_OSCLOCK_bm 0x80 /* Oscillator Lock bit mask. */ -#define FUSE_OSCLOCK_bp 7 /* Oscillator Lock bit position. */ - -/* FUSE.TCD0CFG bit masks and bit positions */ -#define FUSE_CMPA_bm 0x01 /* Compare A Default Output Value bit mask. */ -#define FUSE_CMPA_bp 0 /* Compare A Default Output Value bit position. */ -#define FUSE_CMPB_bm 0x02 /* Compare B Default Output Value bit mask. */ -#define FUSE_CMPB_bp 1 /* Compare B Default Output Value bit position. */ -#define FUSE_CMPC_bm 0x04 /* Compare C Default Output Value bit mask. */ -#define FUSE_CMPC_bp 2 /* Compare C Default Output Value bit position. */ -#define FUSE_CMPD_bm 0x08 /* Compare D Default Output Value bit mask. */ -#define FUSE_CMPD_bp 3 /* Compare D Default Output Value bit position. */ -#define FUSE_CMPAEN_bm 0x10 /* Compare A Output Enable bit mask. */ -#define FUSE_CMPAEN_bp 4 /* Compare A Output Enable bit position. */ -#define FUSE_CMPBEN_bm 0x20 /* Compare B Output Enable bit mask. */ -#define FUSE_CMPBEN_bp 5 /* Compare B Output Enable bit position. */ -#define FUSE_CMPCEN_bm 0x40 /* Compare C Output Enable bit mask. */ -#define FUSE_CMPCEN_bp 6 /* Compare C Output Enable bit position. */ -#define FUSE_CMPDEN_bm 0x80 /* Compare D Output Enable bit mask. */ -#define FUSE_CMPDEN_bp 7 /* Compare D Output Enable bit position. */ - -/* FUSE.SYSCFG0 bit masks and bit positions */ -#define FUSE_EESAVE_bm 0x01 /* EEPROM Save bit mask. */ -#define FUSE_EESAVE_bp 0 /* EEPROM Save bit position. */ -#define FUSE_RSTPINCFG_gm 0x0C /* Reset Pin Configuration group mask. */ -#define FUSE_RSTPINCFG_gp 2 /* Reset Pin Configuration group position. */ -#define FUSE_RSTPINCFG0_bm (1<<2) /* Reset Pin Configuration bit 0 mask. */ -#define FUSE_RSTPINCFG0_bp 2 /* Reset Pin Configuration bit 0 position. */ -#define FUSE_RSTPINCFG1_bm (1<<3) /* Reset Pin Configuration bit 1 mask. */ -#define FUSE_RSTPINCFG1_bp 3 /* Reset Pin Configuration bit 1 position. */ -#define FUSE_CRCSRC_gm 0xC0 /* CRC Source group mask. */ -#define FUSE_CRCSRC_gp 6 /* CRC Source group position. */ -#define FUSE_CRCSRC0_bm (1<<6) /* CRC Source bit 0 mask. */ -#define FUSE_CRCSRC0_bp 6 /* CRC Source bit 0 position. */ -#define FUSE_CRCSRC1_bm (1<<7) /* CRC Source bit 1 mask. */ -#define FUSE_CRCSRC1_bp 7 /* CRC Source bit 1 position. */ - -/* FUSE.SYSCFG1 bit masks and bit positions */ -#define FUSE_SUT_gm 0x07 /* Startup Time group mask. */ -#define FUSE_SUT_gp 0 /* Startup Time group position. */ -#define FUSE_SUT0_bm (1<<0) /* Startup Time bit 0 mask. */ -#define FUSE_SUT0_bp 0 /* Startup Time bit 0 position. */ -#define FUSE_SUT1_bm (1<<1) /* Startup Time bit 1 mask. */ -#define FUSE_SUT1_bp 1 /* Startup Time bit 1 position. */ -#define FUSE_SUT2_bm (1<<2) /* Startup Time bit 2 mask. */ -#define FUSE_SUT2_bp 2 /* Startup Time bit 2 position. */ - - - - - - - -/* LOCKBIT - Lockbit */ -/* LOCKBIT.LOCKBIT bit masks and bit positions */ -#define LOCKBIT_LB_gm 0xFF /* Lock Bits group mask. */ -#define LOCKBIT_LB_gp 0 /* Lock Bits group position. */ -#define LOCKBIT_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ -#define LOCKBIT_LB0_bp 0 /* Lock Bits bit 0 position. */ -#define LOCKBIT_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ -#define LOCKBIT_LB1_bp 1 /* Lock Bits bit 1 position. */ -#define LOCKBIT_LB2_bm (1<<2) /* Lock Bits bit 2 mask. */ -#define LOCKBIT_LB2_bp 2 /* Lock Bits bit 2 position. */ -#define LOCKBIT_LB3_bm (1<<3) /* Lock Bits bit 3 mask. */ -#define LOCKBIT_LB3_bp 3 /* Lock Bits bit 3 position. */ -#define LOCKBIT_LB4_bm (1<<4) /* Lock Bits bit 4 mask. */ -#define LOCKBIT_LB4_bp 4 /* Lock Bits bit 4 position. */ -#define LOCKBIT_LB5_bm (1<<5) /* Lock Bits bit 5 mask. */ -#define LOCKBIT_LB5_bp 5 /* Lock Bits bit 5 position. */ -#define LOCKBIT_LB6_bm (1<<6) /* Lock Bits bit 6 mask. */ -#define LOCKBIT_LB6_bp 6 /* Lock Bits bit 6 position. */ -#define LOCKBIT_LB7_bm (1<<7) /* Lock Bits bit 7 mask. */ -#define LOCKBIT_LB7_bp 7 /* Lock Bits bit 7 position. */ - -/* NVMBIST - BIST in the NVMCTRL module */ -/* NVMBIST.CTRLA bit masks and bit positions */ -#define NVMBIST_CMD_gm 0x07 /* Command group mask. */ -#define NVMBIST_CMD_gp 0 /* Command group position. */ -#define NVMBIST_CMD0_bm (1<<0) /* Command bit 0 mask. */ -#define NVMBIST_CMD0_bp 0 /* Command bit 0 position. */ -#define NVMBIST_CMD1_bm (1<<1) /* Command bit 1 mask. */ -#define NVMBIST_CMD1_bp 1 /* Command bit 1 position. */ -#define NVMBIST_CMD2_bm (1<<2) /* Command bit 2 mask. */ -#define NVMBIST_CMD2_bp 2 /* Command bit 2 position. */ -#define NVMBIST_SAF_bm 0x08 /* Stop at fault bit mask. */ -#define NVMBIST_SAF_bp 3 /* Stop at fault bit position. */ - -/* NVMBIST.ADDRPAT bit masks and bit positions */ -#define NVMBIST_XMODE_gm 0x03 /* X address mode group mask. */ -#define NVMBIST_XMODE_gp 0 /* X address mode group position. */ -#define NVMBIST_XMODE0_bm (1<<0) /* X address mode bit 0 mask. */ -#define NVMBIST_XMODE0_bp 0 /* X address mode bit 0 position. */ -#define NVMBIST_XMODE1_bm (1<<1) /* X address mode bit 1 mask. */ -#define NVMBIST_XMODE1_bp 1 /* X address mode bit 1 position. */ -#define NVMBIST_YMODE_gm 0x0C /* Y address mode group mask. */ -#define NVMBIST_YMODE_gp 2 /* Y address mode group position. */ -#define NVMBIST_YMODE0_bm (1<<2) /* Y address mode bit 0 mask. */ -#define NVMBIST_YMODE0_bp 2 /* Y address mode bit 0 position. */ -#define NVMBIST_YMODE1_bm (1<<3) /* Y address mode bit 1 mask. */ -#define NVMBIST_YMODE1_bp 3 /* Y address mode bit 1 position. */ -#define NVMBIST_AMODE_gm 0x70 /* Address mode group mask. */ -#define NVMBIST_AMODE_gp 4 /* Address mode group position. */ -#define NVMBIST_AMODE0_bm (1<<4) /* Address mode bit 0 mask. */ -#define NVMBIST_AMODE0_bp 4 /* Address mode bit 0 position. */ -#define NVMBIST_AMODE1_bm (1<<5) /* Address mode bit 1 mask. */ -#define NVMBIST_AMODE1_bp 5 /* Address mode bit 1 position. */ -#define NVMBIST_AMODE2_bm (1<<6) /* Address mode bit 2 mask. */ -#define NVMBIST_AMODE2_bp 6 /* Address mode bit 2 position. */ - -/* NVMBIST.DATAPAT bit masks and bit positions */ -#define NVMBIST_PATTERN_gm 0x03 /* Data check pattern group mask. */ -#define NVMBIST_PATTERN_gp 0 /* Data check pattern group position. */ -#define NVMBIST_PATTERN0_bm (1<<0) /* Data check pattern bit 0 mask. */ -#define NVMBIST_PATTERN0_bp 0 /* Data check pattern bit 0 position. */ -#define NVMBIST_PATTERN1_bm (1<<1) /* Data check pattern bit 1 mask. */ -#define NVMBIST_PATTERN1_bp 1 /* Data check pattern bit 1 position. */ - -/* NVMBIST.STATUS bit masks and bit positions */ -#define NVMBIST_STATE_gm 0x0F /* FSM State group mask. */ -#define NVMBIST_STATE_gp 0 /* FSM State group position. */ -#define NVMBIST_STATE0_bm (1<<0) /* FSM State bit 0 mask. */ -#define NVMBIST_STATE0_bp 0 /* FSM State bit 0 position. */ -#define NVMBIST_STATE1_bm (1<<1) /* FSM State bit 1 mask. */ -#define NVMBIST_STATE1_bp 1 /* FSM State bit 1 position. */ -#define NVMBIST_STATE2_bm (1<<2) /* FSM State bit 2 mask. */ -#define NVMBIST_STATE2_bp 2 /* FSM State bit 2 position. */ -#define NVMBIST_STATE3_bm (1<<3) /* FSM State bit 3 mask. */ -#define NVMBIST_STATE3_bp 3 /* FSM State bit 3 position. */ - -/* NVMBIST.CNT bit masks and bit positions */ -#define NVMBIST_CNT_gm 0x7FF /* Faults counter group mask. */ -#define NVMBIST_CNT_gp 0 /* Faults counter group position. */ -#define NVMBIST_CNT0_bm (1<<0) /* Faults counter bit 0 mask. */ -#define NVMBIST_CNT0_bp 0 /* Faults counter bit 0 position. */ -#define NVMBIST_CNT1_bm (1<<1) /* Faults counter bit 1 mask. */ -#define NVMBIST_CNT1_bp 1 /* Faults counter bit 1 position. */ -#define NVMBIST_CNT2_bm (1<<2) /* Faults counter bit 2 mask. */ -#define NVMBIST_CNT2_bp 2 /* Faults counter bit 2 position. */ -#define NVMBIST_CNT3_bm (1<<3) /* Faults counter bit 3 mask. */ -#define NVMBIST_CNT3_bp 3 /* Faults counter bit 3 position. */ -#define NVMBIST_CNT4_bm (1<<4) /* Faults counter bit 4 mask. */ -#define NVMBIST_CNT4_bp 4 /* Faults counter bit 4 position. */ -#define NVMBIST_CNT5_bm (1<<5) /* Faults counter bit 5 mask. */ -#define NVMBIST_CNT5_bp 5 /* Faults counter bit 5 position. */ -#define NVMBIST_CNT6_bm (1<<6) /* Faults counter bit 6 mask. */ -#define NVMBIST_CNT6_bp 6 /* Faults counter bit 6 position. */ -#define NVMBIST_CNT7_bm (1<<7) /* Faults counter bit 7 mask. */ -#define NVMBIST_CNT7_bp 7 /* Faults counter bit 7 position. */ -#define NVMBIST_CNT8_bm (1<<8) /* Faults counter bit 8 mask. */ -#define NVMBIST_CNT8_bp 8 /* Faults counter bit 8 position. */ -#define NVMBIST_CNT9_bm (1<<9) /* Faults counter bit 9 mask. */ -#define NVMBIST_CNT9_bp 9 /* Faults counter bit 9 position. */ -#define NVMBIST_CNT10_bm (1<<10) /* Faults counter bit 10 mask. */ -#define NVMBIST_CNT10_bp 10 /* Faults counter bit 10 position. */ - -/* NVMBIST.END bit masks and bit positions */ -#define NVMBIST_END_gm 0xFFFFFF /* group mask. */ -#define NVMBIST_END_gp 0 /* group position. */ -#define NVMBIST_END0_bm (1<<0) /* bit 0 mask. */ -#define NVMBIST_END0_bp 0 /* bit 0 position. */ -#define NVMBIST_END1_bm (1<<1) /* bit 1 mask. */ -#define NVMBIST_END1_bp 1 /* bit 1 position. */ -#define NVMBIST_END2_bm (1<<2) /* bit 2 mask. */ -#define NVMBIST_END2_bp 2 /* bit 2 position. */ -#define NVMBIST_END3_bm (1<<3) /* bit 3 mask. */ -#define NVMBIST_END3_bp 3 /* bit 3 position. */ -#define NVMBIST_END4_bm (1<<4) /* bit 4 mask. */ -#define NVMBIST_END4_bp 4 /* bit 4 position. */ -#define NVMBIST_END5_bm (1<<5) /* bit 5 mask. */ -#define NVMBIST_END5_bp 5 /* bit 5 position. */ -#define NVMBIST_END6_bm (1<<6) /* bit 6 mask. */ -#define NVMBIST_END6_bp 6 /* bit 6 position. */ -#define NVMBIST_END7_bm (1<<7) /* bit 7 mask. */ -#define NVMBIST_END7_bp 7 /* bit 7 position. */ -#define NVMBIST_END8_bm (1<<8) /* bit 8 mask. */ -#define NVMBIST_END8_bp 8 /* bit 8 position. */ -#define NVMBIST_END9_bm (1<<9) /* bit 9 mask. */ -#define NVMBIST_END9_bp 9 /* bit 9 position. */ -#define NVMBIST_END10_bm (1<<10) /* bit 10 mask. */ -#define NVMBIST_END10_bp 10 /* bit 10 position. */ -#define NVMBIST_END11_bm (1<<11) /* bit 11 mask. */ -#define NVMBIST_END11_bp 11 /* bit 11 position. */ -#define NVMBIST_END12_bm (1<<12) /* bit 12 mask. */ -#define NVMBIST_END12_bp 12 /* bit 12 position. */ -#define NVMBIST_END13_bm (1<<13) /* bit 13 mask. */ -#define NVMBIST_END13_bp 13 /* bit 13 position. */ -#define NVMBIST_END14_bm (1<<14) /* bit 14 mask. */ -#define NVMBIST_END14_bp 14 /* bit 14 position. */ -#define NVMBIST_END15_bm (1<<15) /* bit 15 mask. */ -#define NVMBIST_END15_bp 15 /* bit 15 position. */ -#define NVMBIST_END16_bm (1<<16) /* bit 16 mask. */ -#define NVMBIST_END16_bp 16 /* bit 16 position. */ -#define NVMBIST_END17_bm (1<<17) /* bit 17 mask. */ -#define NVMBIST_END17_bp 17 /* bit 17 position. */ -#define NVMBIST_END18_bm (1<<18) /* bit 18 mask. */ -#define NVMBIST_END18_bp 18 /* bit 18 position. */ -#define NVMBIST_END19_bm (1<<19) /* bit 19 mask. */ -#define NVMBIST_END19_bp 19 /* bit 19 position. */ -#define NVMBIST_END20_bm (1<<20) /* bit 20 mask. */ -#define NVMBIST_END20_bp 20 /* bit 20 position. */ -#define NVMBIST_END21_bm (1<<21) /* bit 21 mask. */ -#define NVMBIST_END21_bp 21 /* bit 21 position. */ -#define NVMBIST_END22_bm (1<<22) /* bit 22 mask. */ -#define NVMBIST_END22_bp 22 /* bit 22 position. */ -#define NVMBIST_END23_bm (1<<23) /* bit 23 mask. */ -#define NVMBIST_END23_bp 23 /* bit 23 position. */ - -/* NVMCTRL - Non-volatile Memory Controller */ -/* NVMCTRL.CTRLA bit masks and bit positions */ -#define NVMCTRL_CMD_gm 0x07 /* Command group mask. */ -#define NVMCTRL_CMD_gp 0 /* Command group position. */ -#define NVMCTRL_CMD0_bm (1<<0) /* Command bit 0 mask. */ -#define NVMCTRL_CMD0_bp 0 /* Command bit 0 position. */ -#define NVMCTRL_CMD1_bm (1<<1) /* Command bit 1 mask. */ -#define NVMCTRL_CMD1_bp 1 /* Command bit 1 position. */ -#define NVMCTRL_CMD2_bm (1<<2) /* Command bit 2 mask. */ -#define NVMCTRL_CMD2_bp 2 /* Command bit 2 position. */ - -/* NVMCTRL.CTRLB bit masks and bit positions */ -#define NVMCTRL_APCWP_bm 0x01 /* Application code write protect bit mask. */ -#define NVMCTRL_APCWP_bp 0 /* Application code write protect bit position. */ -#define NVMCTRL_BOOTLOCK_bm 0x02 /* Boot Lock bit mask. */ -#define NVMCTRL_BOOTLOCK_bp 1 /* Boot Lock bit position. */ - -/* NVMCTRL.STATUS bit masks and bit positions */ -#define NVMCTRL_FBUSY_bm 0x01 /* Flash busy bit mask. */ -#define NVMCTRL_FBUSY_bp 0 /* Flash busy bit position. */ -#define NVMCTRL_EEBUSY_bm 0x02 /* EEPROM busy bit mask. */ -#define NVMCTRL_EEBUSY_bp 1 /* EEPROM busy bit position. */ -#define NVMCTRL_WRERROR_bm 0x04 /* Write error bit mask. */ -#define NVMCTRL_WRERROR_bp 2 /* Write error bit position. */ - -/* NVMCTRL.INTCTRL bit masks and bit positions */ -#define NVMCTRL_EEREADY_bm 0x01 /* EEPROM Ready bit mask. */ -#define NVMCTRL_EEREADY_bp 0 /* EEPROM Ready bit position. */ - -/* NVMCTRL.INTFLAGS bit masks and bit positions */ -/* NVMCTRL_EEREADY is already defined. */ - - - - - - - - - - - - -/* PORT - I/O Ports */ -/* PORT.INTFLAGS bit masks and bit positions */ -#define PORT_INT_gm 0xFF /* Pin Interrupt group mask. */ -#define PORT_INT_gp 0 /* Pin Interrupt group position. */ -#define PORT_INT0_bm (1<<0) /* Pin Interrupt bit 0 mask. */ -#define PORT_INT0_bp 0 /* Pin Interrupt bit 0 position. */ -#define PORT_INT1_bm (1<<1) /* Pin Interrupt bit 1 mask. */ -#define PORT_INT1_bp 1 /* Pin Interrupt bit 1 position. */ -#define PORT_INT2_bm (1<<2) /* Pin Interrupt bit 2 mask. */ -#define PORT_INT2_bp 2 /* Pin Interrupt bit 2 position. */ -#define PORT_INT3_bm (1<<3) /* Pin Interrupt bit 3 mask. */ -#define PORT_INT3_bp 3 /* Pin Interrupt bit 3 position. */ -#define PORT_INT4_bm (1<<4) /* Pin Interrupt bit 4 mask. */ -#define PORT_INT4_bp 4 /* Pin Interrupt bit 4 position. */ -#define PORT_INT5_bm (1<<5) /* Pin Interrupt bit 5 mask. */ -#define PORT_INT5_bp 5 /* Pin Interrupt bit 5 position. */ -#define PORT_INT6_bm (1<<6) /* Pin Interrupt bit 6 mask. */ -#define PORT_INT6_bp 6 /* Pin Interrupt bit 6 position. */ -#define PORT_INT7_bm (1<<7) /* Pin Interrupt bit 7 mask. */ -#define PORT_INT7_bp 7 /* Pin Interrupt bit 7 position. */ - -/* PORT.PORTCTRL bit masks and bit positions */ -#define PORT_SRL_bm 0x01 /* Slew Rate Limit Enable bit mask. */ -#define PORT_SRL_bp 0 /* Slew Rate Limit Enable bit position. */ - -/* PORT.PIN0CTRL bit masks and bit positions */ -#define PORT_ISC_gm 0x07 /* Input/Sense Configuration group mask. */ -#define PORT_ISC_gp 0 /* Input/Sense Configuration group position. */ -#define PORT_ISC0_bm (1<<0) /* Input/Sense Configuration bit 0 mask. */ -#define PORT_ISC0_bp 0 /* Input/Sense Configuration bit 0 position. */ -#define PORT_ISC1_bm (1<<1) /* Input/Sense Configuration bit 1 mask. */ -#define PORT_ISC1_bp 1 /* Input/Sense Configuration bit 1 position. */ -#define PORT_ISC2_bm (1<<2) /* Input/Sense Configuration bit 2 mask. */ -#define PORT_ISC2_bp 2 /* Input/Sense Configuration bit 2 position. */ -#define PORT_PULLUPEN_bm 0x08 /* Pullup enable bit mask. */ -#define PORT_PULLUPEN_bp 3 /* Pullup enable bit position. */ -#define PORT_INVEN_bm 0x80 /* Inverted I/O Enable bit mask. */ -#define PORT_INVEN_bp 7 /* Inverted I/O Enable bit position. */ - -/* PORT.PIN1CTRL bit masks and bit positions */ -/* PORT_ISC is already defined. */ -/* PORT_PULLUPEN is already defined. */ -/* PORT_INVEN is already defined. */ - -/* PORT.PIN2CTRL bit masks and bit positions */ -/* PORT_ISC is already defined. */ -/* PORT_PULLUPEN is already defined. */ -/* PORT_INVEN is already defined. */ - -/* PORT.PIN3CTRL bit masks and bit positions */ -/* PORT_ISC is already defined. */ -/* PORT_PULLUPEN is already defined. */ -/* PORT_INVEN is already defined. */ - -/* PORT.PIN4CTRL bit masks and bit positions */ -/* PORT_ISC is already defined. */ -/* PORT_PULLUPEN is already defined. */ -/* PORT_INVEN is already defined. */ - -/* PORT.PIN5CTRL bit masks and bit positions */ -/* PORT_ISC is already defined. */ -/* PORT_PULLUPEN is already defined. */ -/* PORT_INVEN is already defined. */ - -/* PORT.PIN6CTRL bit masks and bit positions */ -/* PORT_ISC is already defined. */ -/* PORT_PULLUPEN is already defined. */ -/* PORT_INVEN is already defined. */ - -/* PORT.PIN7CTRL bit masks and bit positions */ -/* PORT_ISC is already defined. */ -/* PORT_PULLUPEN is already defined. */ -/* PORT_INVEN is already defined. */ - -/* PORTMUX - Port Multiplexer */ -/* PORTMUX.EVSYSROUTEA bit masks and bit positions */ -#define PORTMUX_EVOUT0_bm 0x01 /* Event Output 0 bit mask. */ -#define PORTMUX_EVOUT0_bp 0 /* Event Output 0 bit position. */ -#define PORTMUX_EVOUT1_bm 0x02 /* Event Output 1 bit mask. */ -#define PORTMUX_EVOUT1_bp 1 /* Event Output 1 bit position. */ -#define PORTMUX_EVOUT2_bm 0x04 /* Event Output 2 bit mask. */ -#define PORTMUX_EVOUT2_bp 2 /* Event Output 2 bit position. */ -#define PORTMUX_EVOUT3_bm 0x08 /* Event Output 3 bit mask. */ -#define PORTMUX_EVOUT3_bp 3 /* Event Output 3 bit position. */ -#define PORTMUX_EVOUT4_bm 0x10 /* Event Output 4 bit mask. */ -#define PORTMUX_EVOUT4_bp 4 /* Event Output 4 bit position. */ -#define PORTMUX_EVOUT5_bm 0x20 /* Event Output 5 bit mask. */ -#define PORTMUX_EVOUT5_bp 5 /* Event Output 5 bit position. */ - -/* PORTMUX.CCLROUTEA bit masks and bit positions */ -#define PORTMUX_LUT0_bm 0x01 /* CCL LUT0 bit mask. */ -#define PORTMUX_LUT0_bp 0 /* CCL LUT0 bit position. */ -#define PORTMUX_LUT1_bm 0x02 /* CCL LUT1 bit mask. */ -#define PORTMUX_LUT1_bp 1 /* CCL LUT1 bit position. */ -#define PORTMUX_LUT2_bm 0x04 /* CCL LUT2 bit mask. */ -#define PORTMUX_LUT2_bp 2 /* CCL LUT2 bit position. */ -#define PORTMUX_LUT3_bm 0x08 /* CCL LUT3 bit mask. */ -#define PORTMUX_LUT3_bp 3 /* CCL LUT3 bit position. */ - -/* PORTMUX.USARTROUTEA bit masks and bit positions */ -#define PORTMUX_USART0_gm 0x03 /* Port Multiplexer USART0 group mask. */ -#define PORTMUX_USART0_gp 0 /* Port Multiplexer USART0 group position. */ -#define PORTMUX_USART00_bm (1<<0) /* Port Multiplexer USART0 bit 0 mask. */ -#define PORTMUX_USART00_bp 0 /* Port Multiplexer USART0 bit 0 position. */ -#define PORTMUX_USART01_bm (1<<1) /* Port Multiplexer USART0 bit 1 mask. */ -#define PORTMUX_USART01_bp 1 /* Port Multiplexer USART0 bit 1 position. */ -#define PORTMUX_USART1_gm 0x0C /* Port Multiplexer USART1 group mask. */ -#define PORTMUX_USART1_gp 2 /* Port Multiplexer USART1 group position. */ -#define PORTMUX_USART10_bm (1<<2) /* Port Multiplexer USART1 bit 0 mask. */ -#define PORTMUX_USART10_bp 2 /* Port Multiplexer USART1 bit 0 position. */ -#define PORTMUX_USART11_bm (1<<3) /* Port Multiplexer USART1 bit 1 mask. */ -#define PORTMUX_USART11_bp 3 /* Port Multiplexer USART1 bit 1 position. */ -#define PORTMUX_USART2_gm 0x30 /* Port Multiplexer USART2 group mask. */ -#define PORTMUX_USART2_gp 4 /* Port Multiplexer USART2 group position. */ -#define PORTMUX_USART20_bm (1<<4) /* Port Multiplexer USART2 bit 0 mask. */ -#define PORTMUX_USART20_bp 4 /* Port Multiplexer USART2 bit 0 position. */ -#define PORTMUX_USART21_bm (1<<5) /* Port Multiplexer USART2 bit 1 mask. */ -#define PORTMUX_USART21_bp 5 /* Port Multiplexer USART2 bit 1 position. */ -#define PORTMUX_USART3_gm 0xC0 /* Port Multiplexer USART3 group mask. */ -#define PORTMUX_USART3_gp 6 /* Port Multiplexer USART3 group position. */ -#define PORTMUX_USART30_bm (1<<6) /* Port Multiplexer USART3 bit 0 mask. */ -#define PORTMUX_USART30_bp 6 /* Port Multiplexer USART3 bit 0 position. */ -#define PORTMUX_USART31_bm (1<<7) /* Port Multiplexer USART3 bit 1 mask. */ -#define PORTMUX_USART31_bp 7 /* Port Multiplexer USART3 bit 1 position. */ - -/* PORTMUX.TWISPIROUTEA bit masks and bit positions */ -#define PORTMUX_SPI0_gm 0x03 /* Port Multiplexer SPI0 group mask. */ -#define PORTMUX_SPI0_gp 0 /* Port Multiplexer SPI0 group position. */ -#define PORTMUX_SPI00_bm (1<<0) /* Port Multiplexer SPI0 bit 0 mask. */ -#define PORTMUX_SPI00_bp 0 /* Port Multiplexer SPI0 bit 0 position. */ -#define PORTMUX_SPI01_bm (1<<1) /* Port Multiplexer SPI0 bit 1 mask. */ -#define PORTMUX_SPI01_bp 1 /* Port Multiplexer SPI0 bit 1 position. */ -#define PORTMUX_TWI0_gm 0x30 /* Port Multiplexer TWI0 group mask. */ -#define PORTMUX_TWI0_gp 4 /* Port Multiplexer TWI0 group position. */ -#define PORTMUX_TWI00_bm (1<<4) /* Port Multiplexer TWI0 bit 0 mask. */ -#define PORTMUX_TWI00_bp 4 /* Port Multiplexer TWI0 bit 0 position. */ -#define PORTMUX_TWI01_bm (1<<5) /* Port Multiplexer TWI0 bit 1 mask. */ -#define PORTMUX_TWI01_bp 5 /* Port Multiplexer TWI0 bit 1 position. */ - -/* PORTMUX.TCAROUTEA bit masks and bit positions */ -#define PORTMUX_TCA0_gm 0x07 /* Port Multiplexer TCA0 group mask. */ -#define PORTMUX_TCA0_gp 0 /* Port Multiplexer TCA0 group position. */ -#define PORTMUX_TCA00_bm (1<<0) /* Port Multiplexer TCA0 bit 0 mask. */ -#define PORTMUX_TCA00_bp 0 /* Port Multiplexer TCA0 bit 0 position. */ -#define PORTMUX_TCA01_bm (1<<1) /* Port Multiplexer TCA0 bit 1 mask. */ -#define PORTMUX_TCA01_bp 1 /* Port Multiplexer TCA0 bit 1 position. */ -#define PORTMUX_TCA02_bm (1<<2) /* Port Multiplexer TCA0 bit 2 mask. */ -#define PORTMUX_TCA02_bp 2 /* Port Multiplexer TCA0 bit 2 position. */ - -/* PORTMUX.TCBROUTEA bit masks and bit positions */ -#define PORTMUX_TCB0_bm 0x01 /* Port Multiplexer TCB0 bit mask. */ -#define PORTMUX_TCB0_bp 0 /* Port Multiplexer TCB0 bit position. */ -#define PORTMUX_TCB1_bm 0x02 /* Port Multiplexer TCB1 bit mask. */ -#define PORTMUX_TCB1_bp 1 /* Port Multiplexer TCB1 bit position. */ -#define PORTMUX_TCB2_bm 0x04 /* Port Multiplexer TCB2 bit mask. */ -#define PORTMUX_TCB2_bp 2 /* Port Multiplexer TCB2 bit position. */ -#define PORTMUX_TCB3_bm 0x08 /* Port Multiplexer TCB3 bit mask. */ -#define PORTMUX_TCB3_bp 3 /* Port Multiplexer TCB3 bit position. */ - -/* RSTCTRL - Reset controller */ -/* RSTCTRL.RSTFR bit masks and bit positions */ -#define RSTCTRL_PORF_bm 0x01 /* Power on Reset flag bit mask. */ -#define RSTCTRL_PORF_bp 0 /* Power on Reset flag bit position. */ -#define RSTCTRL_BORF_bm 0x02 /* Brown out detector Reset flag bit mask. */ -#define RSTCTRL_BORF_bp 1 /* Brown out detector Reset flag bit position. */ -#define RSTCTRL_EXTRF_bm 0x04 /* External Reset flag bit mask. */ -#define RSTCTRL_EXTRF_bp 2 /* External Reset flag bit position. */ -#define RSTCTRL_WDRF_bm 0x08 /* Watch dog Reset flag bit mask. */ -#define RSTCTRL_WDRF_bp 3 /* Watch dog Reset flag bit position. */ -#define RSTCTRL_SWRF_bm 0x10 /* Software Reset flag bit mask. */ -#define RSTCTRL_SWRF_bp 4 /* Software Reset flag bit position. */ -#define RSTCTRL_UPDIRF_bm 0x20 /* UPDI Reset flag bit mask. */ -#define RSTCTRL_UPDIRF_bp 5 /* UPDI Reset flag bit position. */ - -/* RSTCTRL.SWRR bit masks and bit positions */ -#define RSTCTRL_SWRE_bm 0x01 /* Software reset enable bit mask. */ -#define RSTCTRL_SWRE_bp 0 /* Software reset enable bit position. */ - -/* RTC - Real-Time Counter */ -/* RTC.CTRLA bit masks and bit positions */ -#define RTC_RTCEN_bm 0x01 /* Enable bit mask. */ -#define RTC_RTCEN_bp 0 /* Enable bit position. */ -#define RTC_PRESCALER_gm 0x78 /* Prescaling Factor group mask. */ -#define RTC_PRESCALER_gp 3 /* Prescaling Factor group position. */ -#define RTC_PRESCALER0_bm (1<<3) /* Prescaling Factor bit 0 mask. */ -#define RTC_PRESCALER0_bp 3 /* Prescaling Factor bit 0 position. */ -#define RTC_PRESCALER1_bm (1<<4) /* Prescaling Factor bit 1 mask. */ -#define RTC_PRESCALER1_bp 4 /* Prescaling Factor bit 1 position. */ -#define RTC_PRESCALER2_bm (1<<5) /* Prescaling Factor bit 2 mask. */ -#define RTC_PRESCALER2_bp 5 /* Prescaling Factor bit 2 position. */ -#define RTC_PRESCALER3_bm (1<<6) /* Prescaling Factor bit 3 mask. */ -#define RTC_PRESCALER3_bp 6 /* Prescaling Factor bit 3 position. */ -#define RTC_RUNSTDBY_bm 0x80 /* Run In Standby bit mask. */ -#define RTC_RUNSTDBY_bp 7 /* Run In Standby bit position. */ - -/* RTC.STATUS bit masks and bit positions */ -#define RTC_CTRLABUSY_bm 0x01 /* CTRLA Synchronization Busy Flag bit mask. */ -#define RTC_CTRLABUSY_bp 0 /* CTRLA Synchronization Busy Flag bit position. */ -#define RTC_CNTBUSY_bm 0x02 /* Count Synchronization Busy Flag bit mask. */ -#define RTC_CNTBUSY_bp 1 /* Count Synchronization Busy Flag bit position. */ -#define RTC_PERBUSY_bm 0x04 /* Period Synchronization Busy Flag bit mask. */ -#define RTC_PERBUSY_bp 2 /* Period Synchronization Busy Flag bit position. */ -#define RTC_CMPBUSY_bm 0x08 /* Comparator Synchronization Busy Flag bit mask. */ -#define RTC_CMPBUSY_bp 3 /* Comparator Synchronization Busy Flag bit position. */ - -/* RTC.INTCTRL bit masks and bit positions */ -#define RTC_OVF_bm 0x01 /* Overflow Interrupt enable bit mask. */ -#define RTC_OVF_bp 0 /* Overflow Interrupt enable bit position. */ -#define RTC_CMP_bm 0x02 /* Compare Match Interrupt enable bit mask. */ -#define RTC_CMP_bp 1 /* Compare Match Interrupt enable bit position. */ - -/* RTC.INTFLAGS bit masks and bit positions */ -/* RTC_OVF is already defined. */ -/* RTC_CMP is already defined. */ - - -/* RTC.DBGCTRL bit masks and bit positions */ -#define RTC_DBGRUN_bm 0x01 /* Run in debug bit mask. */ -#define RTC_DBGRUN_bp 0 /* Run in debug bit position. */ - -/* RTC.CLKSEL bit masks and bit positions */ -#define RTC_CLKSEL_gm 0x03 /* Clock Select group mask. */ -#define RTC_CLKSEL_gp 0 /* Clock Select group position. */ -#define RTC_CLKSEL0_bm (1<<0) /* Clock Select bit 0 mask. */ -#define RTC_CLKSEL0_bp 0 /* Clock Select bit 0 position. */ -#define RTC_CLKSEL1_bm (1<<1) /* Clock Select bit 1 mask. */ -#define RTC_CLKSEL1_bp 1 /* Clock Select bit 1 position. */ - - - - -/* RTC.PITCTRLA bit masks and bit positions */ -#define RTC_PITEN_bm 0x01 /* Enable bit mask. */ -#define RTC_PITEN_bp 0 /* Enable bit position. */ -#define RTC_PERIOD_gm 0x78 /* Period group mask. */ -#define RTC_PERIOD_gp 3 /* Period group position. */ -#define RTC_PERIOD0_bm (1<<3) /* Period bit 0 mask. */ -#define RTC_PERIOD0_bp 3 /* Period bit 0 position. */ -#define RTC_PERIOD1_bm (1<<4) /* Period bit 1 mask. */ -#define RTC_PERIOD1_bp 4 /* Period bit 1 position. */ -#define RTC_PERIOD2_bm (1<<5) /* Period bit 2 mask. */ -#define RTC_PERIOD2_bp 5 /* Period bit 2 position. */ -#define RTC_PERIOD3_bm (1<<6) /* Period bit 3 mask. */ -#define RTC_PERIOD3_bp 6 /* Period bit 3 position. */ - -/* RTC.PITSTATUS bit masks and bit positions */ -#define RTC_CTRLBUSY_bm 0x01 /* CTRLA Synchronization Busy Flag bit mask. */ -#define RTC_CTRLBUSY_bp 0 /* CTRLA Synchronization Busy Flag bit position. */ - -/* RTC.PITINTCTRL bit masks and bit positions */ -#define RTC_PI_bm 0x01 /* Periodic Interrupt bit mask. */ -#define RTC_PI_bp 0 /* Periodic Interrupt bit position. */ - -/* RTC.PITINTFLAGS bit masks and bit positions */ -/* RTC_PI is already defined. */ - -/* RTC.PITDBGCTRL bit masks and bit positions */ -/* RTC_DBGRUN is already defined. */ - - - - - - - - - - - - - - - - - - - - - - - - - - -/* SLPCTRL - Sleep Controller */ -/* SLPCTRL.CTRLA bit masks and bit positions */ -#define SLPCTRL_SEN_bm 0x01 /* Sleep enable bit mask. */ -#define SLPCTRL_SEN_bp 0 /* Sleep enable bit position. */ -#define SLPCTRL_SMODE_gm 0x06 /* Sleep mode group mask. */ -#define SLPCTRL_SMODE_gp 1 /* Sleep mode group position. */ -#define SLPCTRL_SMODE0_bm (1<<1) /* Sleep mode bit 0 mask. */ -#define SLPCTRL_SMODE0_bp 1 /* Sleep mode bit 0 position. */ -#define SLPCTRL_SMODE1_bm (1<<2) /* Sleep mode bit 1 mask. */ -#define SLPCTRL_SMODE1_bp 2 /* Sleep mode bit 1 position. */ - -/* SPI - Serial Peripheral Interface */ -/* SPI.CTRLA bit masks and bit positions */ -#define SPI_ENABLE_bm 0x01 /* Enable Module bit mask. */ -#define SPI_ENABLE_bp 0 /* Enable Module bit position. */ -#define SPI_PRESC_gm 0x06 /* Prescaler group mask. */ -#define SPI_PRESC_gp 1 /* Prescaler group position. */ -#define SPI_PRESC0_bm (1<<1) /* Prescaler bit 0 mask. */ -#define SPI_PRESC0_bp 1 /* Prescaler bit 0 position. */ -#define SPI_PRESC1_bm (1<<2) /* Prescaler bit 1 mask. */ -#define SPI_PRESC1_bp 2 /* Prescaler bit 1 position. */ -#define SPI_CLK2X_bm 0x10 /* Enable Double Speed bit mask. */ -#define SPI_CLK2X_bp 4 /* Enable Double Speed bit position. */ -#define SPI_MASTER_bm 0x20 /* Master Operation Enable bit mask. */ -#define SPI_MASTER_bp 5 /* Master Operation Enable bit position. */ -#define SPI_DORD_bm 0x40 /* Data Order Setting bit mask. */ -#define SPI_DORD_bp 6 /* Data Order Setting bit position. */ - -/* SPI.CTRLB bit masks and bit positions */ -#define SPI_MODE_gm 0x03 /* SPI Mode group mask. */ -#define SPI_MODE_gp 0 /* SPI Mode group position. */ -#define SPI_MODE0_bm (1<<0) /* SPI Mode bit 0 mask. */ -#define SPI_MODE0_bp 0 /* SPI Mode bit 0 position. */ -#define SPI_MODE1_bm (1<<1) /* SPI Mode bit 1 mask. */ -#define SPI_MODE1_bp 1 /* SPI Mode bit 1 position. */ -#define SPI_SSD_bm 0x04 /* Slave Select Disable bit mask. */ -#define SPI_SSD_bp 2 /* Slave Select Disable bit position. */ -#define SPI_BUFWR_bm 0x40 /* Buffer Write Mode bit mask. */ -#define SPI_BUFWR_bp 6 /* Buffer Write Mode bit position. */ -#define SPI_BUFEN_bm 0x80 /* Buffer Mode Enable bit mask. */ -#define SPI_BUFEN_bp 7 /* Buffer Mode Enable bit position. */ - -/* SPI.INTCTRL bit masks and bit positions */ -#define SPI_IE_bm 0x01 /* Interrupt Enable bit mask. */ -#define SPI_IE_bp 0 /* Interrupt Enable bit position. */ -#define SPI_SSIE_bm 0x10 /* Slave Select Trigger Interrupt Enable bit mask. */ -#define SPI_SSIE_bp 4 /* Slave Select Trigger Interrupt Enable bit position. */ -#define SPI_DREIE_bm 0x20 /* Data Register Empty Interrupt Enable bit mask. */ -#define SPI_DREIE_bp 5 /* Data Register Empty Interrupt Enable bit position. */ -#define SPI_TXCIE_bm 0x40 /* Transfer Complete Interrupt Enable bit mask. */ -#define SPI_TXCIE_bp 6 /* Transfer Complete Interrupt Enable bit position. */ -#define SPI_RXCIE_bm 0x80 /* Receive Complete Interrupt Enable bit mask. */ -#define SPI_RXCIE_bp 7 /* Receive Complete Interrupt Enable bit position. */ - -/* SPI.INTFLAGS bit masks and bit positions */ -#define SPI_BUFOVF_bm 0x01 /* Buffer Overflow bit mask. */ -#define SPI_BUFOVF_bp 0 /* Buffer Overflow bit position. */ -#define SPI_SSIF_bm 0x10 /* Slave Select Trigger Interrupt Flag bit mask. */ -#define SPI_SSIF_bp 4 /* Slave Select Trigger Interrupt Flag bit position. */ -#define SPI_DREIF_bm 0x20 /* Data Register Empty Interrupt Flag bit mask. */ -#define SPI_DREIF_bp 5 /* Data Register Empty Interrupt Flag bit position. */ -#define SPI_TXCIF_bm 0x40 /* Transfer Complete Interrupt Flag bit mask. */ -#define SPI_TXCIF_bp 6 /* Transfer Complete Interrupt Flag bit position. */ -#define SPI_WRCOL_bm 0x40 /* Write Collision bit mask. */ -#define SPI_WRCOL_bp 6 /* Write Collision bit position. */ -#define SPI_RXCIF_bm 0x80 /* Receive Complete Interrupt Flag bit mask. */ -#define SPI_RXCIF_bp 7 /* Receive Complete Interrupt Flag bit position. */ -#define SPI_IF_bm 0x80 /* Interrupt Flag bit mask. */ -#define SPI_IF_bp 7 /* Interrupt Flag bit position. */ - - - -/* SYSCFG - System Configuration Registers */ -/* SYSCFG.EXTBRK bit masks and bit positions */ -#define SYSCFG_ENEXTBRK_bm 0x01 /* External break enable bit mask. */ -#define SYSCFG_ENEXTBRK_bp 0 /* External break enable bit position. */ - - -/* SYSCFG.OCDMS bit masks and bit positions */ -#define SYSCFG_OCDMR_bm 0x01 /* OCD Message Read bit mask. */ -#define SYSCFG_OCDMR_bp 0 /* OCD Message Read bit position. */ - -/* TCA - 16-bit Timer/Counter Type A */ -/* TCA_SINGLE.CTRLA bit masks and bit positions */ -#define TCA_SINGLE_ENABLE_bm 0x01 /* Module Enable bit mask. */ -#define TCA_SINGLE_ENABLE_bp 0 /* Module Enable bit position. */ -#define TCA_SINGLE_CLKSEL_gm 0x0E /* Clock Selection group mask. */ -#define TCA_SINGLE_CLKSEL_gp 1 /* Clock Selection group position. */ -#define TCA_SINGLE_CLKSEL0_bm (1<<1) /* Clock Selection bit 0 mask. */ -#define TCA_SINGLE_CLKSEL0_bp 1 /* Clock Selection bit 0 position. */ -#define TCA_SINGLE_CLKSEL1_bm (1<<2) /* Clock Selection bit 1 mask. */ -#define TCA_SINGLE_CLKSEL1_bp 2 /* Clock Selection bit 1 position. */ -#define TCA_SINGLE_CLKSEL2_bm (1<<3) /* Clock Selection bit 2 mask. */ -#define TCA_SINGLE_CLKSEL2_bp 3 /* Clock Selection bit 2 position. */ - -/* TCA_SINGLE.CTRLB bit masks and bit positions */ -#define TCA_SINGLE_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ -#define TCA_SINGLE_WGMODE_gp 0 /* Waveform generation mode group position. */ -#define TCA_SINGLE_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ -#define TCA_SINGLE_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ -#define TCA_SINGLE_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ -#define TCA_SINGLE_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ -#define TCA_SINGLE_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ -#define TCA_SINGLE_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ -#define TCA_SINGLE_ALUPD_bm 0x08 /* Auto Lock Update bit mask. */ -#define TCA_SINGLE_ALUPD_bp 3 /* Auto Lock Update bit position. */ -#define TCA_SINGLE_CMP0EN_bm 0x10 /* Compare 0 Enable bit mask. */ -#define TCA_SINGLE_CMP0EN_bp 4 /* Compare 0 Enable bit position. */ -#define TCA_SINGLE_CMP1EN_bm 0x20 /* Compare 1 Enable bit mask. */ -#define TCA_SINGLE_CMP1EN_bp 5 /* Compare 1 Enable bit position. */ -#define TCA_SINGLE_CMP2EN_bm 0x40 /* Compare 2 Enable bit mask. */ -#define TCA_SINGLE_CMP2EN_bp 6 /* Compare 2 Enable bit position. */ - -/* TCA_SINGLE.CTRLC bit masks and bit positions */ -#define TCA_SINGLE_CMP0OV_bm 0x01 /* Compare 0 Waveform Output Value bit mask. */ -#define TCA_SINGLE_CMP0OV_bp 0 /* Compare 0 Waveform Output Value bit position. */ -#define TCA_SINGLE_CMP1OV_bm 0x02 /* Compare 1 Waveform Output Value bit mask. */ -#define TCA_SINGLE_CMP1OV_bp 1 /* Compare 1 Waveform Output Value bit position. */ -#define TCA_SINGLE_CMP2OV_bm 0x04 /* Compare 2 Waveform Output Value bit mask. */ -#define TCA_SINGLE_CMP2OV_bp 2 /* Compare 2 Waveform Output Value bit position. */ - -/* TCA_SINGLE.CTRLD bit masks and bit positions */ -#define TCA_SINGLE_SPLITM_bm 0x01 /* Split Mode Enable bit mask. */ -#define TCA_SINGLE_SPLITM_bp 0 /* Split Mode Enable bit position. */ - -/* TCA_SINGLE.CTRLECLR bit masks and bit positions */ -#define TCA_SINGLE_DIR_bm 0x01 /* Direction bit mask. */ -#define TCA_SINGLE_DIR_bp 0 /* Direction bit position. */ -#define TCA_SINGLE_LUPD_bm 0x02 /* Lock Update bit mask. */ -#define TCA_SINGLE_LUPD_bp 1 /* Lock Update bit position. */ -#define TCA_SINGLE_CMD_gm 0x0C /* Command group mask. */ -#define TCA_SINGLE_CMD_gp 2 /* Command group position. */ -#define TCA_SINGLE_CMD0_bm (1<<2) /* Command bit 0 mask. */ -#define TCA_SINGLE_CMD0_bp 2 /* Command bit 0 position. */ -#define TCA_SINGLE_CMD1_bm (1<<3) /* Command bit 1 mask. */ -#define TCA_SINGLE_CMD1_bp 3 /* Command bit 1 position. */ - -/* TCA_SINGLE.CTRLESET bit masks and bit positions */ -/* TCA_SINGLE_DIR is already defined. */ -/* TCA_SINGLE_LUPD is already defined. */ -/* TCA_SINGLE_CMD is already defined. */ - -/* TCA_SINGLE.CTRLFCLR bit masks and bit positions */ -#define TCA_SINGLE_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ -#define TCA_SINGLE_PERBV_bp 0 /* Period Buffer Valid bit position. */ -#define TCA_SINGLE_CMP0BV_bm 0x02 /* Compare 0 Buffer Valid bit mask. */ -#define TCA_SINGLE_CMP0BV_bp 1 /* Compare 0 Buffer Valid bit position. */ -#define TCA_SINGLE_CMP1BV_bm 0x04 /* Compare 1 Buffer Valid bit mask. */ -#define TCA_SINGLE_CMP1BV_bp 2 /* Compare 1 Buffer Valid bit position. */ -#define TCA_SINGLE_CMP2BV_bm 0x08 /* Compare 2 Buffer Valid bit mask. */ -#define TCA_SINGLE_CMP2BV_bp 3 /* Compare 2 Buffer Valid bit position. */ - -/* TCA_SINGLE.CTRLFSET bit masks and bit positions */ -/* TCA_SINGLE_PERBV is already defined. */ -/* TCA_SINGLE_CMP0BV is already defined. */ -/* TCA_SINGLE_CMP1BV is already defined. */ -/* TCA_SINGLE_CMP2BV is already defined. */ - -/* TCA_SINGLE.EVCTRL bit masks and bit positions */ -#define TCA_SINGLE_CNTEI_bm 0x01 /* Count on Event Input bit mask. */ -#define TCA_SINGLE_CNTEI_bp 0 /* Count on Event Input bit position. */ -#define TCA_SINGLE_EVACT_gm 0x06 /* Event Action group mask. */ -#define TCA_SINGLE_EVACT_gp 1 /* Event Action group position. */ -#define TCA_SINGLE_EVACT0_bm (1<<1) /* Event Action bit 0 mask. */ -#define TCA_SINGLE_EVACT0_bp 1 /* Event Action bit 0 position. */ -#define TCA_SINGLE_EVACT1_bm (1<<2) /* Event Action bit 1 mask. */ -#define TCA_SINGLE_EVACT1_bp 2 /* Event Action bit 1 position. */ - -/* TCA_SINGLE.INTCTRL bit masks and bit positions */ -#define TCA_SINGLE_OVF_bm 0x01 /* Overflow Interrupt bit mask. */ -#define TCA_SINGLE_OVF_bp 0 /* Overflow Interrupt bit position. */ -#define TCA_SINGLE_CMP0_bm 0x10 /* Compare 0 Interrupt bit mask. */ -#define TCA_SINGLE_CMP0_bp 4 /* Compare 0 Interrupt bit position. */ -#define TCA_SINGLE_CMP1_bm 0x20 /* Compare 1 Interrupt bit mask. */ -#define TCA_SINGLE_CMP1_bp 5 /* Compare 1 Interrupt bit position. */ -#define TCA_SINGLE_CMP2_bm 0x40 /* Compare 2 Interrupt bit mask. */ -#define TCA_SINGLE_CMP2_bp 6 /* Compare 2 Interrupt bit position. */ - -/* TCA_SINGLE.INTFLAGS bit masks and bit positions */ -/* TCA_SINGLE_OVF is already defined. */ -/* TCA_SINGLE_CMP0 is already defined. */ -/* TCA_SINGLE_CMP1 is already defined. */ -/* TCA_SINGLE_CMP2 is already defined. */ - -/* TCA_SINGLE.DBGCTRL bit masks and bit positions */ -#define TCA_SINGLE_DBGRUN_bm 0x01 /* Debug Run bit mask. */ -#define TCA_SINGLE_DBGRUN_bp 0 /* Debug Run bit position. */ - - - - - - - - - - - -/* TCA_SPLIT.CTRLA bit masks and bit positions */ -#define TCA_SPLIT_ENABLE_bm 0x01 /* Module Enable bit mask. */ -#define TCA_SPLIT_ENABLE_bp 0 /* Module Enable bit position. */ -#define TCA_SPLIT_CLKSEL_gm 0x0E /* Clock Selection group mask. */ -#define TCA_SPLIT_CLKSEL_gp 1 /* Clock Selection group position. */ -#define TCA_SPLIT_CLKSEL0_bm (1<<1) /* Clock Selection bit 0 mask. */ -#define TCA_SPLIT_CLKSEL0_bp 1 /* Clock Selection bit 0 position. */ -#define TCA_SPLIT_CLKSEL1_bm (1<<2) /* Clock Selection bit 1 mask. */ -#define TCA_SPLIT_CLKSEL1_bp 2 /* Clock Selection bit 1 position. */ -#define TCA_SPLIT_CLKSEL2_bm (1<<3) /* Clock Selection bit 2 mask. */ -#define TCA_SPLIT_CLKSEL2_bp 3 /* Clock Selection bit 2 position. */ - -/* TCA_SPLIT.CTRLB bit masks and bit positions */ -#define TCA_SPLIT_LCMP0EN_bm 0x01 /* Low Compare 0 Enable bit mask. */ -#define TCA_SPLIT_LCMP0EN_bp 0 /* Low Compare 0 Enable bit position. */ -#define TCA_SPLIT_LCMP1EN_bm 0x02 /* Low Compare 1 Enable bit mask. */ -#define TCA_SPLIT_LCMP1EN_bp 1 /* Low Compare 1 Enable bit position. */ -#define TCA_SPLIT_LCMP2EN_bm 0x04 /* Low Compare 2 Enable bit mask. */ -#define TCA_SPLIT_LCMP2EN_bp 2 /* Low Compare 2 Enable bit position. */ -#define TCA_SPLIT_HCMP0EN_bm 0x10 /* High Compare 0 Enable bit mask. */ -#define TCA_SPLIT_HCMP0EN_bp 4 /* High Compare 0 Enable bit position. */ -#define TCA_SPLIT_HCMP1EN_bm 0x20 /* High Compare 1 Enable bit mask. */ -#define TCA_SPLIT_HCMP1EN_bp 5 /* High Compare 1 Enable bit position. */ -#define TCA_SPLIT_HCMP2EN_bm 0x40 /* High Compare 2 Enable bit mask. */ -#define TCA_SPLIT_HCMP2EN_bp 6 /* High Compare 2 Enable bit position. */ - -/* TCA_SPLIT.CTRLC bit masks and bit positions */ -#define TCA_SPLIT_LCMP0OV_bm 0x01 /* Low Compare 0 Output Value bit mask. */ -#define TCA_SPLIT_LCMP0OV_bp 0 /* Low Compare 0 Output Value bit position. */ -#define TCA_SPLIT_LCMP1OV_bm 0x02 /* Low Compare 1 Output Value bit mask. */ -#define TCA_SPLIT_LCMP1OV_bp 1 /* Low Compare 1 Output Value bit position. */ -#define TCA_SPLIT_LCMP2OV_bm 0x04 /* Low Compare 2 Output Value bit mask. */ -#define TCA_SPLIT_LCMP2OV_bp 2 /* Low Compare 2 Output Value bit position. */ -#define TCA_SPLIT_HCMP0OV_bm 0x10 /* High Compare 0 Output Value bit mask. */ -#define TCA_SPLIT_HCMP0OV_bp 4 /* High Compare 0 Output Value bit position. */ -#define TCA_SPLIT_HCMP1OV_bm 0x20 /* High Compare 1 Output Value bit mask. */ -#define TCA_SPLIT_HCMP1OV_bp 5 /* High Compare 1 Output Value bit position. */ -#define TCA_SPLIT_HCMP2OV_bm 0x40 /* High Compare 2 Output Value bit mask. */ -#define TCA_SPLIT_HCMP2OV_bp 6 /* High Compare 2 Output Value bit position. */ - -/* TCA_SPLIT.CTRLD bit masks and bit positions */ -#define TCA_SPLIT_SPLITM_bm 0x01 /* Split Mode Enable bit mask. */ -#define TCA_SPLIT_SPLITM_bp 0 /* Split Mode Enable bit position. */ - -/* TCA_SPLIT.CTRLECLR bit masks and bit positions */ -#define TCA_SPLIT_CMD_gm 0x0C /* Command group mask. */ -#define TCA_SPLIT_CMD_gp 2 /* Command group position. */ -#define TCA_SPLIT_CMD0_bm (1<<2) /* Command bit 0 mask. */ -#define TCA_SPLIT_CMD0_bp 2 /* Command bit 0 position. */ -#define TCA_SPLIT_CMD1_bm (1<<3) /* Command bit 1 mask. */ -#define TCA_SPLIT_CMD1_bp 3 /* Command bit 1 position. */ - -/* TCA_SPLIT.CTRLESET bit masks and bit positions */ -/* TCA_SPLIT_CMD is already defined. */ - -/* TCA_SPLIT.INTCTRL bit masks and bit positions */ -#define TCA_SPLIT_LUNF_bm 0x01 /* Low Underflow Interrupt Enable bit mask. */ -#define TCA_SPLIT_LUNF_bp 0 /* Low Underflow Interrupt Enable bit position. */ -#define TCA_SPLIT_HUNF_bm 0x02 /* High Underflow Interrupt Enable bit mask. */ -#define TCA_SPLIT_HUNF_bp 1 /* High Underflow Interrupt Enable bit position. */ -#define TCA_SPLIT_LCMP0_bm 0x10 /* Low Compare 0 Interrupt Enable bit mask. */ -#define TCA_SPLIT_LCMP0_bp 4 /* Low Compare 0 Interrupt Enable bit position. */ -#define TCA_SPLIT_LCMP1_bm 0x20 /* Low Compare 1 Interrupt Enable bit mask. */ -#define TCA_SPLIT_LCMP1_bp 5 /* Low Compare 1 Interrupt Enable bit position. */ -#define TCA_SPLIT_LCMP2_bm 0x40 /* Low Compare 2 Interrupt Enable bit mask. */ -#define TCA_SPLIT_LCMP2_bp 6 /* Low Compare 2 Interrupt Enable bit position. */ - -/* TCA_SPLIT.INTFLAGS bit masks and bit positions */ -/* TCA_SPLIT_LUNF is already defined. */ -/* TCA_SPLIT_HUNF is already defined. */ -/* TCA_SPLIT_LCMP0 is already defined. */ -/* TCA_SPLIT_LCMP1 is already defined. */ -/* TCA_SPLIT_LCMP2 is already defined. */ - -/* TCA_SPLIT.DBGCTRL bit masks and bit positions */ -#define TCA_SPLIT_DBGRUN_bm 0x01 /* Debug Run bit mask. */ -#define TCA_SPLIT_DBGRUN_bp 0 /* Debug Run bit position. */ - - - - - - - - - - - -/* TCB - 16-bit Timer Type B */ -/* TCB.CTRLA bit masks and bit positions */ -#define TCB_ENABLE_bm 0x01 /* Enable bit mask. */ -#define TCB_ENABLE_bp 0 /* Enable bit position. */ -#define TCB_CLKSEL_gm 0x06 /* Clock Select group mask. */ -#define TCB_CLKSEL_gp 1 /* Clock Select group position. */ -#define TCB_CLKSEL0_bm (1<<1) /* Clock Select bit 0 mask. */ -#define TCB_CLKSEL0_bp 1 /* Clock Select bit 0 position. */ -#define TCB_CLKSEL1_bm (1<<2) /* Clock Select bit 1 mask. */ -#define TCB_CLKSEL1_bp 2 /* Clock Select bit 1 position. */ -#define TCB_SYNCUPD_bm 0x10 /* Synchronize Update bit mask. */ -#define TCB_SYNCUPD_bp 4 /* Synchronize Update bit position. */ -#define TCB_RUNSTDBY_bm 0x40 /* Run Standby bit mask. */ -#define TCB_RUNSTDBY_bp 6 /* Run Standby bit position. */ - -/* TCB.CTRLB bit masks and bit positions */ -#define TCB_CNTMODE_gm 0x07 /* Timer Mode group mask. */ -#define TCB_CNTMODE_gp 0 /* Timer Mode group position. */ -#define TCB_CNTMODE0_bm (1<<0) /* Timer Mode bit 0 mask. */ -#define TCB_CNTMODE0_bp 0 /* Timer Mode bit 0 position. */ -#define TCB_CNTMODE1_bm (1<<1) /* Timer Mode bit 1 mask. */ -#define TCB_CNTMODE1_bp 1 /* Timer Mode bit 1 position. */ -#define TCB_CNTMODE2_bm (1<<2) /* Timer Mode bit 2 mask. */ -#define TCB_CNTMODE2_bp 2 /* Timer Mode bit 2 position. */ -#define TCB_CCMPEN_bm 0x10 /* Pin Output Enable bit mask. */ -#define TCB_CCMPEN_bp 4 /* Pin Output Enable bit position. */ -#define TCB_CCMPINIT_bm 0x20 /* Pin Initial State bit mask. */ -#define TCB_CCMPINIT_bp 5 /* Pin Initial State bit position. */ -#define TCB_ASYNC_bm 0x40 /* Asynchronous Enable bit mask. */ -#define TCB_ASYNC_bp 6 /* Asynchronous Enable bit position. */ - -/* TCB.EVCTRL bit masks and bit positions */ -#define TCB_CAPTEI_bm 0x01 /* Event Input Enable bit mask. */ -#define TCB_CAPTEI_bp 0 /* Event Input Enable bit position. */ -#define TCB_EDGE_bm 0x10 /* Event Edge bit mask. */ -#define TCB_EDGE_bp 4 /* Event Edge bit position. */ -#define TCB_FILTER_bm 0x40 /* Input Capture Noise Cancellation Filter bit mask. */ -#define TCB_FILTER_bp 6 /* Input Capture Noise Cancellation Filter bit position. */ - -/* TCB.INTCTRL bit masks and bit positions */ -#define TCB_CAPT_bm 0x01 /* Capture or Timeout bit mask. */ -#define TCB_CAPT_bp 0 /* Capture or Timeout bit position. */ - -/* TCB.INTFLAGS bit masks and bit positions */ -/* TCB_CAPT is already defined. */ - -/* TCB.STATUS bit masks and bit positions */ -#define TCB_RUN_bm 0x01 /* Run bit mask. */ -#define TCB_RUN_bp 0 /* Run bit position. */ - -/* TCB.DBGCTRL bit masks and bit positions */ -#define TCB_DBGRUN_bm 0x01 /* Debug Run bit mask. */ -#define TCB_DBGRUN_bp 0 /* Debug Run bit position. */ - - - - -/* TWI - Two-Wire Interface */ -/* TWI.CTRLA bit masks and bit positions */ -#define TWI_FMPEN_bm 0x02 /* FM Plus Enable bit mask. */ -#define TWI_FMPEN_bp 1 /* FM Plus Enable bit position. */ -#define TWI_SDAHOLD_gm 0x0C /* SDA Hold Time group mask. */ -#define TWI_SDAHOLD_gp 2 /* SDA Hold Time group position. */ -#define TWI_SDAHOLD0_bm (1<<2) /* SDA Hold Time bit 0 mask. */ -#define TWI_SDAHOLD0_bp 2 /* SDA Hold Time bit 0 position. */ -#define TWI_SDAHOLD1_bm (1<<3) /* SDA Hold Time bit 1 mask. */ -#define TWI_SDAHOLD1_bp 3 /* SDA Hold Time bit 1 position. */ -#define TWI_SDASETUP_bm 0x10 /* SDA Setup Time bit mask. */ -#define TWI_SDASETUP_bp 4 /* SDA Setup Time bit position. */ - -/* TWI.BRIDGECTRL bit masks and bit positions */ -#define TWI_ENABLE_bm 0x01 /* Bridge Enable bit mask. */ -#define TWI_ENABLE_bp 0 /* Bridge Enable bit position. */ -/* TWI_FMPEN is already defined. */ -/* TWI_SDAHOLD is already defined. */ - -/* TWI.DBGCTRL bit masks and bit positions */ -#define TWI_DBGRUN_bm 0x01 /* Debug Run bit mask. */ -#define TWI_DBGRUN_bp 0 /* Debug Run bit position. */ - -/* TWI.MCTRLA bit masks and bit positions */ -/* TWI_ENABLE is already defined. */ -#define TWI_SMEN_bm 0x02 /* Smart Mode Enable bit mask. */ -#define TWI_SMEN_bp 1 /* Smart Mode Enable bit position. */ -#define TWI_TIMEOUT_gm 0x0C /* Inactive Bus Timeout group mask. */ -#define TWI_TIMEOUT_gp 2 /* Inactive Bus Timeout group position. */ -#define TWI_TIMEOUT0_bm (1<<2) /* Inactive Bus Timeout bit 0 mask. */ -#define TWI_TIMEOUT0_bp 2 /* Inactive Bus Timeout bit 0 position. */ -#define TWI_TIMEOUT1_bm (1<<3) /* Inactive Bus Timeout bit 1 mask. */ -#define TWI_TIMEOUT1_bp 3 /* Inactive Bus Timeout bit 1 position. */ -#define TWI_QCEN_bm 0x10 /* Quick Command Enable bit mask. */ -#define TWI_QCEN_bp 4 /* Quick Command Enable bit position. */ -#define TWI_WIEN_bm 0x40 /* Write Interrupt Enable bit mask. */ -#define TWI_WIEN_bp 6 /* Write Interrupt Enable bit position. */ -#define TWI_RIEN_bm 0x80 /* Read Interrupt Enable bit mask. */ -#define TWI_RIEN_bp 7 /* Read Interrupt Enable bit position. */ - -/* TWI.MCTRLB bit masks and bit positions */ -#define TWI_MCMD_gm 0x03 /* Command group mask. */ -#define TWI_MCMD_gp 0 /* Command group position. */ -#define TWI_MCMD0_bm (1<<0) /* Command bit 0 mask. */ -#define TWI_MCMD0_bp 0 /* Command bit 0 position. */ -#define TWI_MCMD1_bm (1<<1) /* Command bit 1 mask. */ -#define TWI_MCMD1_bp 1 /* Command bit 1 position. */ -#define TWI_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ -#define TWI_ACKACT_bp 2 /* Acknowledge Action bit position. */ -#define TWI_FLUSH_bm 0x08 /* Flush bit mask. */ -#define TWI_FLUSH_bp 3 /* Flush bit position. */ - -/* TWI.MSTATUS bit masks and bit positions */ -#define TWI_BUSSTATE_gm 0x03 /* Bus State group mask. */ -#define TWI_BUSSTATE_gp 0 /* Bus State group position. */ -#define TWI_BUSSTATE0_bm (1<<0) /* Bus State bit 0 mask. */ -#define TWI_BUSSTATE0_bp 0 /* Bus State bit 0 position. */ -#define TWI_BUSSTATE1_bm (1<<1) /* Bus State bit 1 mask. */ -#define TWI_BUSSTATE1_bp 1 /* Bus State bit 1 position. */ -#define TWI_BUSERR_bm 0x04 /* Bus Error bit mask. */ -#define TWI_BUSERR_bp 2 /* Bus Error bit position. */ -#define TWI_ARBLOST_bm 0x08 /* Arbitration Lost bit mask. */ -#define TWI_ARBLOST_bp 3 /* Arbitration Lost bit position. */ -#define TWI_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ -#define TWI_RXACK_bp 4 /* Received Acknowledge bit position. */ -#define TWI_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ -#define TWI_CLKHOLD_bp 5 /* Clock Hold bit position. */ -#define TWI_WIF_bm 0x40 /* Write Interrupt Flag bit mask. */ -#define TWI_WIF_bp 6 /* Write Interrupt Flag bit position. */ -#define TWI_RIF_bm 0x80 /* Read Interrupt Flag bit mask. */ -#define TWI_RIF_bp 7 /* Read Interrupt Flag bit position. */ - - - - -/* TWI.SCTRLA bit masks and bit positions */ -/* TWI_ENABLE is already defined. */ -/* TWI_SMEN is already defined. */ -#define TWI_PMEN_bm 0x04 /* Promiscuous Mode Enable bit mask. */ -#define TWI_PMEN_bp 2 /* Promiscuous Mode Enable bit position. */ -#define TWI_PIEN_bm 0x20 /* Stop Interrupt Enable bit mask. */ -#define TWI_PIEN_bp 5 /* Stop Interrupt Enable bit position. */ -#define TWI_APIEN_bm 0x40 /* Address/Stop Interrupt Enable bit mask. */ -#define TWI_APIEN_bp 6 /* Address/Stop Interrupt Enable bit position. */ -#define TWI_DIEN_bm 0x80 /* Data Interrupt Enable bit mask. */ -#define TWI_DIEN_bp 7 /* Data Interrupt Enable bit position. */ - -/* TWI.SCTRLB bit masks and bit positions */ -#define TWI_SCMD_gm 0x03 /* Command group mask. */ -#define TWI_SCMD_gp 0 /* Command group position. */ -#define TWI_SCMD0_bm (1<<0) /* Command bit 0 mask. */ -#define TWI_SCMD0_bp 0 /* Command bit 0 position. */ -#define TWI_SCMD1_bm (1<<1) /* Command bit 1 mask. */ -#define TWI_SCMD1_bp 1 /* Command bit 1 position. */ -/* TWI_ACKACT is already defined. */ - -/* TWI.SSTATUS bit masks and bit positions */ -#define TWI_AP_bm 0x01 /* Slave Address or Stop bit mask. */ -#define TWI_AP_bp 0 /* Slave Address or Stop bit position. */ -#define TWI_DIR_bm 0x02 /* Read/Write Direction bit mask. */ -#define TWI_DIR_bp 1 /* Read/Write Direction bit position. */ -/* TWI_BUSERR is already defined. */ -#define TWI_COLL_bm 0x08 /* Collision bit mask. */ -#define TWI_COLL_bp 3 /* Collision bit position. */ -/* TWI_RXACK is already defined. */ -/* TWI_CLKHOLD is already defined. */ -#define TWI_APIF_bm 0x40 /* Address/Stop Interrupt Flag bit mask. */ -#define TWI_APIF_bp 6 /* Address/Stop Interrupt Flag bit position. */ -#define TWI_DIF_bm 0x80 /* Data Interrupt Flag bit mask. */ -#define TWI_DIF_bp 7 /* Data Interrupt Flag bit position. */ - - - -/* TWI.SADDRMASK bit masks and bit positions */ -#define TWI_ADDREN_bm 0x01 /* Address Enable bit mask. */ -#define TWI_ADDREN_bp 0 /* Address Enable bit position. */ -#define TWI_ADDRMASK_gm 0xFE /* Address Mask group mask. */ -#define TWI_ADDRMASK_gp 1 /* Address Mask group position. */ -#define TWI_ADDRMASK0_bm (1<<1) /* Address Mask bit 0 mask. */ -#define TWI_ADDRMASK0_bp 1 /* Address Mask bit 0 position. */ -#define TWI_ADDRMASK1_bm (1<<2) /* Address Mask bit 1 mask. */ -#define TWI_ADDRMASK1_bp 2 /* Address Mask bit 1 position. */ -#define TWI_ADDRMASK2_bm (1<<3) /* Address Mask bit 2 mask. */ -#define TWI_ADDRMASK2_bp 3 /* Address Mask bit 2 position. */ -#define TWI_ADDRMASK3_bm (1<<4) /* Address Mask bit 3 mask. */ -#define TWI_ADDRMASK3_bp 4 /* Address Mask bit 3 position. */ -#define TWI_ADDRMASK4_bm (1<<5) /* Address Mask bit 4 mask. */ -#define TWI_ADDRMASK4_bp 5 /* Address Mask bit 4 position. */ -#define TWI_ADDRMASK5_bm (1<<6) /* Address Mask bit 5 mask. */ -#define TWI_ADDRMASK5_bp 6 /* Address Mask bit 5 position. */ -#define TWI_ADDRMASK6_bm (1<<7) /* Address Mask bit 6 mask. */ -#define TWI_ADDRMASK6_bp 7 /* Address Mask bit 6 position. */ - -/* USART - Universal Synchronous and Asynchronous Receiver and Transmitter */ -/* USART.RXDATAL bit masks and bit positions */ -#define USART_DATA_gm 0xFF /* RX Data group mask. */ -#define USART_DATA_gp 0 /* RX Data group position. */ -#define USART_DATA0_bm (1<<0) /* RX Data bit 0 mask. */ -#define USART_DATA0_bp 0 /* RX Data bit 0 position. */ -#define USART_DATA1_bm (1<<1) /* RX Data bit 1 mask. */ -#define USART_DATA1_bp 1 /* RX Data bit 1 position. */ -#define USART_DATA2_bm (1<<2) /* RX Data bit 2 mask. */ -#define USART_DATA2_bp 2 /* RX Data bit 2 position. */ -#define USART_DATA3_bm (1<<3) /* RX Data bit 3 mask. */ -#define USART_DATA3_bp 3 /* RX Data bit 3 position. */ -#define USART_DATA4_bm (1<<4) /* RX Data bit 4 mask. */ -#define USART_DATA4_bp 4 /* RX Data bit 4 position. */ -#define USART_DATA5_bm (1<<5) /* RX Data bit 5 mask. */ -#define USART_DATA5_bp 5 /* RX Data bit 5 position. */ -#define USART_DATA6_bm (1<<6) /* RX Data bit 6 mask. */ -#define USART_DATA6_bp 6 /* RX Data bit 6 position. */ -#define USART_DATA7_bm (1<<7) /* RX Data bit 7 mask. */ -#define USART_DATA7_bp 7 /* RX Data bit 7 position. */ - -/* USART.RXDATAH bit masks and bit positions */ -#define USART_DATA8_bm 0x01 /* Receiver Data Register bit mask. */ -#define USART_DATA8_bp 0 /* Receiver Data Register bit position. */ -#define USART_PERR_bm 0x02 /* Parity Error bit mask. */ -#define USART_PERR_bp 1 /* Parity Error bit position. */ -#define USART_FERR_bm 0x04 /* Frame Error bit mask. */ -#define USART_FERR_bp 2 /* Frame Error bit position. */ -#define USART_BUFOVF_bm 0x40 /* Buffer Overflow bit mask. */ -#define USART_BUFOVF_bp 6 /* Buffer Overflow bit position. */ -#define USART_RXCIF_bm 0x80 /* Receive Complete Interrupt Flag bit mask. */ -#define USART_RXCIF_bp 7 /* Receive Complete Interrupt Flag bit position. */ - -/* USART.TXDATAL bit masks and bit positions */ -/* USART_DATA is already defined. */ - -/* USART.TXDATAH bit masks and bit positions */ -/* USART_DATA8 is already defined. */ - -/* USART.STATUS bit masks and bit positions */ -#define USART_WFB_bm 0x01 /* Wait For Break bit mask. */ -#define USART_WFB_bp 0 /* Wait For Break bit position. */ -#define USART_BDF_bm 0x02 /* Break Detected Flag bit mask. */ -#define USART_BDF_bp 1 /* Break Detected Flag bit position. */ -#define USART_ISFIF_bm 0x08 /* Inconsistent Sync Field Interrupt Flag bit mask. */ -#define USART_ISFIF_bp 3 /* Inconsistent Sync Field Interrupt Flag bit position. */ -#define USART_RXSIF_bm 0x10 /* Receive Start Interrupt bit mask. */ -#define USART_RXSIF_bp 4 /* Receive Start Interrupt bit position. */ -#define USART_DREIF_bm 0x20 /* Data Register Empty Flag bit mask. */ -#define USART_DREIF_bp 5 /* Data Register Empty Flag bit position. */ -#define USART_TXCIF_bm 0x40 /* Transmit Interrupt Flag bit mask. */ -#define USART_TXCIF_bp 6 /* Transmit Interrupt Flag bit position. */ -/* USART_RXCIF is already defined. */ - -/* USART.CTRLA bit masks and bit positions */ -#define USART_RS485_gm 0x03 /* RS485 Mode internal transmitter group mask. */ -#define USART_RS485_gp 0 /* RS485 Mode internal transmitter group position. */ -#define USART_RS4850_bm (1<<0) /* RS485 Mode internal transmitter bit 0 mask. */ -#define USART_RS4850_bp 0 /* RS485 Mode internal transmitter bit 0 position. */ -#define USART_RS4851_bm (1<<1) /* RS485 Mode internal transmitter bit 1 mask. */ -#define USART_RS4851_bp 1 /* RS485 Mode internal transmitter bit 1 position. */ -#define USART_ABEIE_bm 0x04 /* Auto-baud Error Interrupt Enable bit mask. */ -#define USART_ABEIE_bp 2 /* Auto-baud Error Interrupt Enable bit position. */ -#define USART_LBME_bm 0x08 /* Loop-back Mode Enable bit mask. */ -#define USART_LBME_bp 3 /* Loop-back Mode Enable bit position. */ -#define USART_RXSIE_bm 0x10 /* Receiver Start Frame Interrupt Enable bit mask. */ -#define USART_RXSIE_bp 4 /* Receiver Start Frame Interrupt Enable bit position. */ -#define USART_DREIE_bm 0x20 /* Data Register Empty Interrupt Enable bit mask. */ -#define USART_DREIE_bp 5 /* Data Register Empty Interrupt Enable bit position. */ -#define USART_TXCIE_bm 0x40 /* Transmit Complete Interrupt Enable bit mask. */ -#define USART_TXCIE_bp 6 /* Transmit Complete Interrupt Enable bit position. */ -#define USART_RXCIE_bm 0x80 /* Receive Complete Interrupt Enable bit mask. */ -#define USART_RXCIE_bp 7 /* Receive Complete Interrupt Enable bit position. */ - -/* USART.CTRLB bit masks and bit positions */ -#define USART_MPCM_bm 0x01 /* Multi-processor Communication Mode bit mask. */ -#define USART_MPCM_bp 0 /* Multi-processor Communication Mode bit position. */ -#define USART_RXMODE_gm 0x06 /* Receiver Mode group mask. */ -#define USART_RXMODE_gp 1 /* Receiver Mode group position. */ -#define USART_RXMODE0_bm (1<<1) /* Receiver Mode bit 0 mask. */ -#define USART_RXMODE0_bp 1 /* Receiver Mode bit 0 position. */ -#define USART_RXMODE1_bm (1<<2) /* Receiver Mode bit 1 mask. */ -#define USART_RXMODE1_bp 2 /* Receiver Mode bit 1 position. */ -#define USART_ODME_bm 0x08 /* Open Drain Mode Enable bit mask. */ -#define USART_ODME_bp 3 /* Open Drain Mode Enable bit position. */ -#define USART_SFDEN_bm 0x10 /* Start Frame Detection Enable bit mask. */ -#define USART_SFDEN_bp 4 /* Start Frame Detection Enable bit position. */ -#define USART_TXEN_bm 0x40 /* Transmitter Enable bit mask. */ -#define USART_TXEN_bp 6 /* Transmitter Enable bit position. */ -#define USART_RXEN_bm 0x80 /* Reciever enable bit mask. */ -#define USART_RXEN_bp 7 /* Reciever enable bit position. */ - -/* USART.CTRLC bit masks and bit positions */ -#define USART_UCPHA_bm 0x02 /* SPI Master Mode, Clock Phase bit mask. */ -#define USART_UCPHA_bp 1 /* SPI Master Mode, Clock Phase bit position. */ -#define USART_UDORD_bm 0x04 /* SPI Master Mode, Data Order bit mask. */ -#define USART_UDORD_bp 2 /* SPI Master Mode, Data Order bit position. */ -#define USART_CHSIZE_gm 0x07 /* Character Size group mask. */ -#define USART_CHSIZE_gp 0 /* Character Size group position. */ -#define USART_CHSIZE0_bm (1<<0) /* Character Size bit 0 mask. */ -#define USART_CHSIZE0_bp 0 /* Character Size bit 0 position. */ -#define USART_CHSIZE1_bm (1<<1) /* Character Size bit 1 mask. */ -#define USART_CHSIZE1_bp 1 /* Character Size bit 1 position. */ -#define USART_CHSIZE2_bm (1<<2) /* Character Size bit 2 mask. */ -#define USART_CHSIZE2_bp 2 /* Character Size bit 2 position. */ -#define USART_SBMODE_bm 0x08 /* Stop Bit Mode bit mask. */ -#define USART_SBMODE_bp 3 /* Stop Bit Mode bit position. */ -#define USART_PMODE_gm 0x30 /* Parity Mode group mask. */ -#define USART_PMODE_gp 4 /* Parity Mode group position. */ -#define USART_PMODE0_bm (1<<4) /* Parity Mode bit 0 mask. */ -#define USART_PMODE0_bp 4 /* Parity Mode bit 0 position. */ -#define USART_PMODE1_bm (1<<5) /* Parity Mode bit 1 mask. */ -#define USART_PMODE1_bp 5 /* Parity Mode bit 1 position. */ -#define USART_CMODE_gm 0xC0 /* Communication Mode group mask. */ -#define USART_CMODE_gp 6 /* Communication Mode group position. */ -#define USART_CMODE0_bm (1<<6) /* Communication Mode bit 0 mask. */ -#define USART_CMODE0_bp 6 /* Communication Mode bit 0 position. */ -#define USART_CMODE1_bm (1<<7) /* Communication Mode bit 1 mask. */ -#define USART_CMODE1_bp 7 /* Communication Mode bit 1 position. */ - - - -/* USART.DBGCTRL bit masks and bit positions */ -#define USART_DBGRUN_bm 0x01 /* Debug Run bit mask. */ -#define USART_DBGRUN_bp 0 /* Debug Run bit position. */ -#define USART_ABMBP_bm 0x80 /* Autobaud majority voter bypass bit mask. */ -#define USART_ABMBP_bp 7 /* Autobaud majority voter bypass bit position. */ - -/* USART.EVCTRL bit masks and bit positions */ -#define USART_IREI_bm 0x01 /* IrDA Event Input Enable bit mask. */ -#define USART_IREI_bp 0 /* IrDA Event Input Enable bit position. */ - -/* USART.TXPLCTRL bit masks and bit positions */ -#define USART_TXPL_gm 0xFF /* Transmit pulse length group mask. */ -#define USART_TXPL_gp 0 /* Transmit pulse length group position. */ -#define USART_TXPL0_bm (1<<0) /* Transmit pulse length bit 0 mask. */ -#define USART_TXPL0_bp 0 /* Transmit pulse length bit 0 position. */ -#define USART_TXPL1_bm (1<<1) /* Transmit pulse length bit 1 mask. */ -#define USART_TXPL1_bp 1 /* Transmit pulse length bit 1 position. */ -#define USART_TXPL2_bm (1<<2) /* Transmit pulse length bit 2 mask. */ -#define USART_TXPL2_bp 2 /* Transmit pulse length bit 2 position. */ -#define USART_TXPL3_bm (1<<3) /* Transmit pulse length bit 3 mask. */ -#define USART_TXPL3_bp 3 /* Transmit pulse length bit 3 position. */ -#define USART_TXPL4_bm (1<<4) /* Transmit pulse length bit 4 mask. */ -#define USART_TXPL4_bp 4 /* Transmit pulse length bit 4 position. */ -#define USART_TXPL5_bm (1<<5) /* Transmit pulse length bit 5 mask. */ -#define USART_TXPL5_bp 5 /* Transmit pulse length bit 5 position. */ -#define USART_TXPL6_bm (1<<6) /* Transmit pulse length bit 6 mask. */ -#define USART_TXPL6_bp 6 /* Transmit pulse length bit 6 position. */ -#define USART_TXPL7_bm (1<<7) /* Transmit pulse length bit 7 mask. */ -#define USART_TXPL7_bp 7 /* Transmit pulse length bit 7 position. */ - -/* USART.RXPLCTRL bit masks and bit positions */ -#define USART_RXPL_gm 0x7F /* Receiver Pulse Lenght group mask. */ -#define USART_RXPL_gp 0 /* Receiver Pulse Lenght group position. */ -#define USART_RXPL0_bm (1<<0) /* Receiver Pulse Lenght bit 0 mask. */ -#define USART_RXPL0_bp 0 /* Receiver Pulse Lenght bit 0 position. */ -#define USART_RXPL1_bm (1<<1) /* Receiver Pulse Lenght bit 1 mask. */ -#define USART_RXPL1_bp 1 /* Receiver Pulse Lenght bit 1 position. */ -#define USART_RXPL2_bm (1<<2) /* Receiver Pulse Lenght bit 2 mask. */ -#define USART_RXPL2_bp 2 /* Receiver Pulse Lenght bit 2 position. */ -#define USART_RXPL3_bm (1<<3) /* Receiver Pulse Lenght bit 3 mask. */ -#define USART_RXPL3_bp 3 /* Receiver Pulse Lenght bit 3 position. */ -#define USART_RXPL4_bm (1<<4) /* Receiver Pulse Lenght bit 4 mask. */ -#define USART_RXPL4_bp 4 /* Receiver Pulse Lenght bit 4 position. */ -#define USART_RXPL5_bm (1<<5) /* Receiver Pulse Lenght bit 5 mask. */ -#define USART_RXPL5_bp 5 /* Receiver Pulse Lenght bit 5 position. */ -#define USART_RXPL6_bm (1<<6) /* Receiver Pulse Lenght bit 6 mask. */ -#define USART_RXPL6_bp 6 /* Receiver Pulse Lenght bit 6 position. */ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -/* VPORT - Virtual Ports */ -/* VPORT.INTFLAGS bit masks and bit positions */ -#define VPORT_INT_gm 0xFF /* Pin Interrupt group mask. */ -#define VPORT_INT_gp 0 /* Pin Interrupt group position. */ -#define VPORT_INT0_bm (1<<0) /* Pin Interrupt bit 0 mask. */ -#define VPORT_INT0_bp 0 /* Pin Interrupt bit 0 position. */ -#define VPORT_INT1_bm (1<<1) /* Pin Interrupt bit 1 mask. */ -#define VPORT_INT1_bp 1 /* Pin Interrupt bit 1 position. */ -#define VPORT_INT2_bm (1<<2) /* Pin Interrupt bit 2 mask. */ -#define VPORT_INT2_bp 2 /* Pin Interrupt bit 2 position. */ -#define VPORT_INT3_bm (1<<3) /* Pin Interrupt bit 3 mask. */ -#define VPORT_INT3_bp 3 /* Pin Interrupt bit 3 position. */ -#define VPORT_INT4_bm (1<<4) /* Pin Interrupt bit 4 mask. */ -#define VPORT_INT4_bp 4 /* Pin Interrupt bit 4 position. */ -#define VPORT_INT5_bm (1<<5) /* Pin Interrupt bit 5 mask. */ -#define VPORT_INT5_bp 5 /* Pin Interrupt bit 5 position. */ -#define VPORT_INT6_bm (1<<6) /* Pin Interrupt bit 6 mask. */ -#define VPORT_INT6_bp 6 /* Pin Interrupt bit 6 position. */ -#define VPORT_INT7_bm (1<<7) /* Pin Interrupt bit 7 mask. */ -#define VPORT_INT7_bp 7 /* Pin Interrupt bit 7 position. */ - -/* VREF - Voltage reference */ -/* VREF.CTRLA bit masks and bit positions */ -#define VREF_AC0REFSEL_gm 0x07 /* AC0 reference select group mask. */ -#define VREF_AC0REFSEL_gp 0 /* AC0 reference select group position. */ -#define VREF_AC0REFSEL0_bm (1<<0) /* AC0 reference select bit 0 mask. */ -#define VREF_AC0REFSEL0_bp 0 /* AC0 reference select bit 0 position. */ -#define VREF_AC0REFSEL1_bm (1<<1) /* AC0 reference select bit 1 mask. */ -#define VREF_AC0REFSEL1_bp 1 /* AC0 reference select bit 1 position. */ -#define VREF_AC0REFSEL2_bm (1<<2) /* AC0 reference select bit 2 mask. */ -#define VREF_AC0REFSEL2_bp 2 /* AC0 reference select bit 2 position. */ -#define VREF_ADC0REFSEL_gm 0x70 /* ADC0 reference select group mask. */ -#define VREF_ADC0REFSEL_gp 4 /* ADC0 reference select group position. */ -#define VREF_ADC0REFSEL0_bm (1<<4) /* ADC0 reference select bit 0 mask. */ -#define VREF_ADC0REFSEL0_bp 4 /* ADC0 reference select bit 0 position. */ -#define VREF_ADC0REFSEL1_bm (1<<5) /* ADC0 reference select bit 1 mask. */ -#define VREF_ADC0REFSEL1_bp 5 /* ADC0 reference select bit 1 position. */ -#define VREF_ADC0REFSEL2_bm (1<<6) /* ADC0 reference select bit 2 mask. */ -#define VREF_ADC0REFSEL2_bp 6 /* ADC0 reference select bit 2 position. */ - -/* VREF.CTRLB bit masks and bit positions */ -#define VREF_AC0REFEN_bm 0x01 /* AC0 DACREF reference enable bit mask. */ -#define VREF_AC0REFEN_bp 0 /* AC0 DACREF reference enable bit position. */ -#define VREF_ADC0REFEN_bm 0x02 /* ADC0 reference enable bit mask. */ -#define VREF_ADC0REFEN_bp 1 /* ADC0 reference enable bit position. */ -#define VREF_NVMREFEN_bm 0x04 /* NVM reference enable bit mask. */ -#define VREF_NVMREFEN_bp 2 /* NVM reference enable bit position. */ - -/* WDT - Watch-Dog Timer */ -/* WDT.CTRLA bit masks and bit positions */ -#define WDT_PERIOD_gm 0x0F /* Period group mask. */ -#define WDT_PERIOD_gp 0 /* Period group position. */ -#define WDT_PERIOD0_bm (1<<0) /* Period bit 0 mask. */ -#define WDT_PERIOD0_bp 0 /* Period bit 0 position. */ -#define WDT_PERIOD1_bm (1<<1) /* Period bit 1 mask. */ -#define WDT_PERIOD1_bp 1 /* Period bit 1 position. */ -#define WDT_PERIOD2_bm (1<<2) /* Period bit 2 mask. */ -#define WDT_PERIOD2_bp 2 /* Period bit 2 position. */ -#define WDT_PERIOD3_bm (1<<3) /* Period bit 3 mask. */ -#define WDT_PERIOD3_bp 3 /* Period bit 3 position. */ -#define WDT_WINDOW_gm 0xF0 /* Window group mask. */ -#define WDT_WINDOW_gp 4 /* Window group position. */ -#define WDT_WINDOW0_bm (1<<4) /* Window bit 0 mask. */ -#define WDT_WINDOW0_bp 4 /* Window bit 0 position. */ -#define WDT_WINDOW1_bm (1<<5) /* Window bit 1 mask. */ -#define WDT_WINDOW1_bp 5 /* Window bit 1 position. */ -#define WDT_WINDOW2_bm (1<<6) /* Window bit 2 mask. */ -#define WDT_WINDOW2_bp 6 /* Window bit 2 position. */ -#define WDT_WINDOW3_bm (1<<7) /* Window bit 3 mask. */ -#define WDT_WINDOW3_bp 7 /* Window bit 3 position. */ - -/* WDT.STATUS bit masks and bit positions */ -#define WDT_SYNCBUSY_bm 0x01 /* Syncronization busy bit mask. */ -#define WDT_SYNCBUSY_bp 0 /* Syncronization busy bit position. */ -#define WDT_LOCK_bm 0x80 /* Lock enable bit mask. */ -#define WDT_LOCK_bp 7 /* Lock enable bit position. */ - - - -// Generic Port Pins - -#define PIN0_bm 0x01 -#define PIN0_bp 0 -#define PIN1_bm 0x02 -#define PIN1_bp 1 -#define PIN2_bm 0x04 -#define PIN2_bp 2 -#define PIN3_bm 0x08 -#define PIN3_bp 3 -#define PIN4_bm 0x10 -#define PIN4_bp 4 -#define PIN5_bm 0x20 -#define PIN5_bp 5 -#define PIN6_bm 0x40 -#define PIN6_bp 6 -#define PIN7_bm 0x80 -#define PIN7_bp 7 - -/* ========== Interrupt Vector Definitions ========== */ -/* Vector 0 is the reset vector */ - -/* CRCSCAN interrupt vectors */ -#define CRCSCAN_NMI_vect_num 1 -#define CRCSCAN_NMI_vect _VECTOR(1) /* */ - -/* BOD interrupt vectors */ -#define BOD_VLM_vect_num 2 -#define BOD_VLM_vect _VECTOR(2) /* */ - -/* RTC interrupt vectors */ -#define RTC_CNT_vect_num 3 -#define RTC_CNT_vect _VECTOR(3) /* */ -#define RTC_PIT_vect_num 4 -#define RTC_PIT_vect _VECTOR(4) /* */ - -/* CCL interrupt vectors */ -#define CCL_CCL_vect_num 5 -#define CCL_CCL_vect _VECTOR(5) /* */ - -/* PORTA interrupt vectors */ -#define PORTA_PORT_vect_num 6 -#define PORTA_PORT_vect _VECTOR(6) /* */ - -/* TCA0 interrupt vectors */ -#define TCA0_LUNF_vect_num 7 -#define TCA0_LUNF_vect _VECTOR(7) /* */ -#define TCA0_OVF_vect_num 7 -#define TCA0_OVF_vect _VECTOR(7) /* */ -#define TCA0_HUNF_vect_num 8 -#define TCA0_HUNF_vect _VECTOR(8) /* */ -#define TCA0_LCMP0_vect_num 9 -#define TCA0_LCMP0_vect _VECTOR(9) /* */ -#define TCA0_CMP0_vect_num 9 -#define TCA0_CMP0_vect _VECTOR(9) /* */ -#define TCA0_CMP1_vect_num 10 -#define TCA0_CMP1_vect _VECTOR(10) /* */ -#define TCA0_LCMP1_vect_num 10 -#define TCA0_LCMP1_vect _VECTOR(10) /* */ -#define TCA0_CMP2_vect_num 11 -#define TCA0_CMP2_vect _VECTOR(11) /* */ -#define TCA0_LCMP2_vect_num 11 -#define TCA0_LCMP2_vect _VECTOR(11) /* */ - -/* TCB0 interrupt vectors */ -#define TCB0_INT_vect_num 12 -#define TCB0_INT_vect _VECTOR(12) /* */ - -/* TCB1 interrupt vectors */ -#define TCB1_INT_vect_num 13 -#define TCB1_INT_vect _VECTOR(13) /* */ - -/* TWI0 interrupt vectors */ -#define TWI0_TWIS_vect_num 14 -#define TWI0_TWIS_vect _VECTOR(14) /* */ -#define TWI0_TWIM_vect_num 15 -#define TWI0_TWIM_vect _VECTOR(15) /* */ - -/* SPI0 interrupt vectors */ -#define SPI0_INT_vect_num 16 -#define SPI0_INT_vect _VECTOR(16) /* */ - -/* USART0 interrupt vectors */ -#define USART0_RXC_vect_num 17 -#define USART0_RXC_vect _VECTOR(17) /* */ -#define USART0_DRE_vect_num 18 -#define USART0_DRE_vect _VECTOR(18) /* */ -#define USART0_TXC_vect_num 19 -#define USART0_TXC_vect _VECTOR(19) /* */ - -/* PORTD interrupt vectors */ -#define PORTD_PORT_vect_num 20 -#define PORTD_PORT_vect _VECTOR(20) /* */ - -/* AC0 interrupt vectors */ -#define AC0_AC_vect_num 21 -#define AC0_AC_vect _VECTOR(21) /* */ - -/* ADC0 interrupt vectors */ -#define ADC0_RESRDY_vect_num 22 -#define ADC0_RESRDY_vect _VECTOR(22) /* */ -#define ADC0_WCOMP_vect_num 23 -#define ADC0_WCOMP_vect _VECTOR(23) /* */ - -/* PORTC interrupt vectors */ -#define PORTC_PORT_vect_num 24 -#define PORTC_PORT_vect _VECTOR(24) /* */ - -/* TCB2 interrupt vectors */ -#define TCB2_INT_vect_num 25 -#define TCB2_INT_vect _VECTOR(25) /* */ - -/* USART1 interrupt vectors */ -#define USART1_RXC_vect_num 26 -#define USART1_RXC_vect _VECTOR(26) /* */ -#define USART1_DRE_vect_num 27 -#define USART1_DRE_vect _VECTOR(27) /* */ -#define USART1_TXC_vect_num 28 -#define USART1_TXC_vect _VECTOR(28) /* */ - -/* PORTF interrupt vectors */ -#define PORTF_PORT_vect_num 29 -#define PORTF_PORT_vect _VECTOR(29) /* */ - -/* NVMCTRL interrupt vectors */ -#define NVMCTRL_EE_vect_num 30 -#define NVMCTRL_EE_vect _VECTOR(30) /* */ - -/* USART2 interrupt vectors */ -#define USART2_RXC_vect_num 31 -#define USART2_RXC_vect _VECTOR(31) /* */ -#define USART2_DRE_vect_num 32 -#define USART2_DRE_vect _VECTOR(32) /* */ -#define USART2_TXC_vect_num 33 -#define USART2_TXC_vect _VECTOR(33) /* */ - -/* PORTB interrupt vectors */ -#define PORTB_PORT_vect_num 34 -#define PORTB_PORT_vect _VECTOR(34) /* */ - -/* PORTE interrupt vectors */ -#define PORTE_PORT_vect_num 35 -#define PORTE_PORT_vect _VECTOR(35) /* */ - -/* TCB3 interrupt vectors */ -#define TCB3_INT_vect_num 36 -#define TCB3_INT_vect _VECTOR(36) /* */ - -/* USART3 interrupt vectors */ -#define USART3_RXC_vect_num 37 -#define USART3_RXC_vect _VECTOR(37) /* */ -#define USART3_DRE_vect_num 38 -#define USART3_DRE_vect _VECTOR(38) /* */ -#define USART3_TXC_vect_num 39 -#define USART3_TXC_vect _VECTOR(39) /* */ - -#define _VECTOR_SIZE 4 /* Size of individual vector. */ -#define _VECTORS_SIZE (40 * _VECTOR_SIZE) - - -/* ========== Constants ========== */ - -#define DATAMEM_START (0x0000) -#define DATAMEM_SIZE (49152) -#define DATAMEM_END (DATAMEM_START + DATAMEM_SIZE - 1) - -#define EEPROM_START (0x1400) -#define EEPROM_SIZE (256) -#define EEPROM_PAGE_SIZE (64) -#define EEPROM_END (EEPROM_START + EEPROM_SIZE - 1) - -/* Added MAPPED_EEPROM segment names for avr-libc */ -#define MAPPED_EEPROM_START (EEPROM_START) -#define MAPPED_EEPROM_SIZE (EEPROM_SIZE) -#define MAPPED_EEPROM_PAGE_SIZE (EEPROM_PAGE_SIZE) -#define MAPPED_EEPROM_END (MAPPED_EEPROM_START + MAPPED_EEPROM_SIZE - 1) - -#define FUSES_START (0x1280) -#define FUSES_SIZE (10) -#define FUSES_PAGE_SIZE (64) -#define FUSES_END (FUSES_START + FUSES_SIZE - 1) - -#define INTERNAL_SRAM_START (0x2800) -#define INTERNAL_SRAM_SIZE (6144) -#define INTERNAL_SRAM_PAGE_SIZE (0) -#define INTERNAL_SRAM_END (INTERNAL_SRAM_START + INTERNAL_SRAM_SIZE - 1) - -#define IO_START (0x0000) -#define IO_SIZE (4352) -#define IO_PAGE_SIZE (0) -#define IO_END (IO_START + IO_SIZE - 1) - -#define LOCKBITS_START (0x128A) -#define LOCKBITS_SIZE (1) -#define LOCKBITS_PAGE_SIZE (64) -#define LOCKBITS_END (LOCKBITS_START + LOCKBITS_SIZE - 1) - -#define MAPPED_PROGMEM_START (0x4000) -#define MAPPED_PROGMEM_SIZE (49152) -#define MAPPED_PROGMEM_PAGE_SIZE (128) -#define MAPPED_PROGMEM_END (MAPPED_PROGMEM_START + MAPPED_PROGMEM_SIZE - 1) - -#define PROD_SIGNATURES_START (0x1103) -#define PROD_SIGNATURES_SIZE (125) -#define PROD_SIGNATURES_PAGE_SIZE (128) -#define PROD_SIGNATURES_END (PROD_SIGNATURES_START + PROD_SIGNATURES_SIZE - 1) - -#define SIGNATURES_START (0x1100) -#define SIGNATURES_SIZE (3) -#define SIGNATURES_PAGE_SIZE (128) -#define SIGNATURES_END (SIGNATURES_START + SIGNATURES_SIZE - 1) - -#define USER_SIGNATURES_START (0x1300) -#define USER_SIGNATURES_SIZE (64) -#define USER_SIGNATURES_PAGE_SIZE (64) -#define USER_SIGNATURES_END (USER_SIGNATURES_START + USER_SIGNATURES_SIZE - 1) - -#define PROGMEM_START (0x0000) -#define PROGMEM_SIZE (49152) -#define PROGMEM_END (PROGMEM_START + PROGMEM_SIZE - 1) - -#define PROGMEM_START (0x0000) -#define PROGMEM_SIZE (49152) -#define PROGMEM_PAGE_SIZE (128) -#define PROGMEM_END (PROGMEM_START + PROGMEM_SIZE - 1) - -#define FLASHSTART PROGMEM_START -#define FLASHEND PROGMEM_END -#define RAMSTART INTERNAL_SRAM_START -#define RAMSIZE INTERNAL_SRAM_SIZE -#define RAMEND INTERNAL_SRAM_END -#define E2END EEPROM_END -#define E2PAGESIZE EEPROM_PAGE_SIZE - - -/* ========== Fuses ========== */ -#define FUSE_MEMORY_SIZE 9 - -/* Fuse Byte 0 Reserved */ - -/* Fuse Byte 1 Reserved */ - -/* Fuse Byte 2 Reserved */ - -/* Fuse Byte 3 Reserved */ - -/* Fuse Byte 4 Reserved */ - -/* Fuse Byte 5 Reserved */ - -/* Fuse Byte 6 Reserved */ - -/* Fuse Byte 7 */ - -/* Fuse Byte 8 */ -#define FUSE_SLEEP0 (unsigned char)~_BV(0) /* BOD Operation in Sleep Mode Bit 0 */ -#define FUSE_SLEEP1 (unsigned char)~_BV(1) /* BOD Operation in Sleep Mode Bit 1 */ -#define FUSE_ACTIVE0 (unsigned char)~_BV(2) /* BOD Operation in Active Mode Bit 0 */ -#define FUSE_ACTIVE1 (unsigned char)~_BV(3) /* BOD Operation in Active Mode Bit 1 */ -#define FUSE_SAMPFREQ (unsigned char)~_BV(4) /* BOD Sample Frequency */ -#define FUSE_LVL0 (unsigned char)~_BV(5) /* BOD Level Bit 0 */ -#define FUSE_LVL1 (unsigned char)~_BV(6) /* BOD Level Bit 1 */ -#define FUSE_LVL2 (unsigned char)~_BV(7) /* BOD Level Bit 2 */ - -/* Fuse Byte 9 */ - -/* Fuse Byte 10 */ -#define FUSE_FREQSEL0 (unsigned char)~_BV(0) /* Frequency Select Bit 0 */ -#define FUSE_FREQSEL1 (unsigned char)~_BV(1) /* Frequency Select Bit 1 */ -#define FUSE_OSCLOCK (unsigned char)~_BV(7) /* Oscillator Lock */ - -/* Fuse Byte 11 */ -#define FUSE_EESAVE (unsigned char)~_BV(0) /* EEPROM Save */ -#define FUSE_RSTPINCFG0 (unsigned char)~_BV(2) /* Reset Pin Configuration Bit 0 */ -#define FUSE_RSTPINCFG1 (unsigned char)~_BV(3) /* Reset Pin Configuration Bit 1 */ -#define FUSE_CRCSRC0 (unsigned char)~_BV(6) /* CRC Source Bit 0 */ -#define FUSE_CRCSRC1 (unsigned char)~_BV(7) /* CRC Source Bit 1 */ - -/* Fuse Byte 12 */ -#define FUSE_SUT0 (unsigned char)~_BV(0) /* Startup Time Bit 0 */ -#define FUSE_SUT1 (unsigned char)~_BV(1) /* Startup Time Bit 1 */ -#define FUSE_SUT2 (unsigned char)~_BV(2) /* Startup Time Bit 2 */ - -/* Fuse Byte 13 */ -#define FUSE_CMPA (unsigned char)~_BV(0) /* Compare A Default Output Value */ -#define FUSE_CMPB (unsigned char)~_BV(1) /* Compare B Default Output Value */ -#define FUSE_CMPC (unsigned char)~_BV(2) /* Compare C Default Output Value */ -#define FUSE_CMPD (unsigned char)~_BV(3) /* Compare D Default Output Value */ -#define FUSE_CMPAEN (unsigned char)~_BV(4) /* Compare A Output Enable */ -#define FUSE_CMPBEN (unsigned char)~_BV(5) /* Compare B Output Enable */ -#define FUSE_CMPCEN (unsigned char)~_BV(6) /* Compare C Output Enable */ -#define FUSE_CMPDEN (unsigned char)~_BV(7) /* Compare D Output Enable */ - -/* Fuse Byte 14 */ -#define FUSE_PERIOD0 (unsigned char)~_BV(0) /* Watchdog Timeout Period Bit 0 */ -#define FUSE_PERIOD1 (unsigned char)~_BV(1) /* Watchdog Timeout Period Bit 1 */ -#define FUSE_PERIOD2 (unsigned char)~_BV(2) /* Watchdog Timeout Period Bit 2 */ -#define FUSE_PERIOD3 (unsigned char)~_BV(3) /* Watchdog Timeout Period Bit 3 */ -#define FUSE_WINDOW0 (unsigned char)~_BV(4) /* Watchdog Window Timeout Period Bit 0 */ -#define FUSE_WINDOW1 (unsigned char)~_BV(5) /* Watchdog Window Timeout Period Bit 1 */ -#define FUSE_WINDOW2 (unsigned char)~_BV(6) /* Watchdog Window Timeout Period Bit 2 */ -#define FUSE_WINDOW3 (unsigned char)~_BV(7) /* Watchdog Window Timeout Period Bit 3 */ - -/* ========== Lock Bits ========== */ -#define __LOCK_BITS_EXIST - -/* ========== Signature ========== */ -#define SIGNATURE_0 0x1E -#define SIGNATURE_1 0x96 -#define SIGNATURE_2 0x51 - - -#endif /* #ifdef _AVR_ATMEGA4809_H_INCLUDED */ - diff --git a/arduino/hardware/tools/avr/avr/include/avr/iom48a.h b/arduino/hardware/tools/avr/avr/include/avr/iom48a.h deleted file mode 100644 index 8992147..0000000 --- a/arduino/hardware/tools/avr/avr/include/avr/iom48a.h +++ /dev/null @@ -1,35 +0,0 @@ -/***************************************************************************** - * - * Copyright (C) 2011 Atmel Corporation - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * - * * Neither the name of the copyright holders nor the names of - * contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - ****************************************************************************/ - -#include "iom48.h" -#define SLEEP_MODE_EXT_STANDBY (0x07<<1) diff --git a/arduino/hardware/tools/avr/avr/include/avr/iom48p.h b/arduino/hardware/tools/avr/avr/include/avr/iom48p.h deleted file mode 100644 index 57a0702..0000000 --- a/arduino/hardware/tools/avr/avr/include/avr/iom48p.h +++ /dev/null @@ -1,936 +0,0 @@ -/* Copyright (c) 2007 Atmel Corporation - All rights reserved. - - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - * Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - * Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in - the documentation and/or other materials provided with the - distribution. - - * Neither the name of the copyright holders nor the names of - contributors may be used to endorse or promote products derived - from this software without specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. -*/ - -/* $Id: iom48p.h 2225 2011-03-02 16:27:26Z arcanum $ */ - -/* avr/iom48p.h - definitions for ATmega48P. */ - -/* This file should only be included from , never directly. */ - -#ifndef _AVR_IO_H_ -# error "Include instead of this file." -#endif - -#ifndef _AVR_IOXXX_H_ -# define _AVR_IOXXX_H_ "iom48p.h" -#else -# error "Attempt to include more than one file." -#endif - - -#ifndef _AVR_IOM48P_H_ -#define _AVR_IOM48P_H_ 1 - -/* Registers and associated bit numbers */ - -#define PINB _SFR_IO8(0x03) -#define PINB0 0 -#define PINB1 1 -#define PINB2 2 -#define PINB3 3 -#define PINB4 4 -#define PINB5 5 -#define PINB6 6 -#define PINB7 7 - -#define DDRB _SFR_IO8(0x04) -#define DDB0 0 -#define DDB1 1 -#define DDB2 2 -#define DDB3 3 -#define DDB4 4 -#define DDB5 5 -#define DDB6 6 -#define DDB7 7 - -#define PORTB _SFR_IO8(0x05) -#define PORTB0 0 -#define PORTB1 1 -#define PORTB2 2 -#define PORTB3 3 -#define PORTB4 4 -#define PORTB5 5 -#define PORTB6 6 -#define PORTB7 7 - -#define PINC _SFR_IO8(0x06) -#define PINC0 0 -#define PINC1 1 -#define PINC2 2 -#define PINC3 3 -#define PINC4 4 -#define PINC5 5 -#define PINC6 6 - -#define DDRC _SFR_IO8(0x07) -#define DDC0 0 -#define DDC1 1 -#define DDC2 2 -#define DDC3 3 -#define DDC4 4 -#define DDC5 5 -#define DDC6 6 - -#define PORTC _SFR_IO8(0x08) -#define PORTC0 0 -#define PORTC1 1 -#define PORTC2 2 -#define PORTC3 3 -#define PORTC4 4 -#define PORTC5 5 -#define PORTC6 6 - -#define PIND _SFR_IO8(0x09) -#define PIND0 0 -#define PIND1 1 -#define PIND2 2 -#define PIND3 3 -#define PIND4 4 -#define PIND5 5 -#define PIND6 6 -#define PIND7 7 - -#define DDRD _SFR_IO8(0x0A) -#define DDD0 0 -#define DDD1 1 -#define DDD2 2 -#define DDD3 3 -#define DDD4 4 -#define DDD5 5 -#define DDD6 6 -#define DDD7 7 - -#define PORTD _SFR_IO8(0x0B) -#define PORTD0 0 -#define PORTD1 1 -#define PORTD2 2 -#define PORTD3 3 -#define PORTD4 4 -#define PORTD5 5 -#define PORTD6 6 -#define PORTD7 7 - -#define TIFR0 _SFR_IO8(0x15) -#define TOV0 0 -#define OCF0A 1 -#define OCF0B 2 - -#define TIFR1 _SFR_IO8(0x16) -#define TOV1 0 -#define OCF1A 1 -#define OCF1B 2 -#define ICF1 5 - -#define TIFR2 _SFR_IO8(0x17) -#define TOV2 0 -#define OCF2A 1 -#define OCF2B 2 - -#define PCIFR _SFR_IO8(0x1B) -#define PCIF0 0 -#define PCIF1 1 -#define PCIF2 2 - -#define EIFR _SFR_IO8(0x1C) -#define INTF0 0 -#define INTF1 1 - -#define EIMSK _SFR_IO8(0x1D) -#define INT0 0 -#define INT1 1 - -#define GPIOR0 _SFR_IO8(0x1E) -#define GPIOR00 0 -#define GPIOR01 1 -#define GPIOR02 2 -#define GPIOR03 3 -#define GPIOR04 4 -#define GPIOR05 5 -#define GPIOR06 6 -#define GPIOR07 7 - -#define EECR _SFR_IO8(0x1F) -#define EERE 0 -#define EEPE 1 -#define EEMPE 2 -#define EERIE 3 -#define EEPM0 4 -#define EEPM1 5 - -#define EEDR _SFR_IO8(0x20) -#define EEDR0 0 -#define EEDR1 1 -#define EEDR2 2 -#define EEDR3 3 -#define EEDR4 4 -#define EEDR5 5 -#define EEDR6 6 -#define EEDR7 7 - -#define EEARL _SFR_IO8(0x21) -#define EEAR0 0 -#define EEAR1 1 -#define EEAR2 2 -#define EEAR3 3 -#define EEAR4 4 -#define EEAR5 5 -#define EEAR6 6 -#define EEAR7 7 - -/* Only valid for ATmega88P-168P-328P */ -/* EEARH _SFR_IO8(0x22) */ - -#define EEPROM_REG_LOCATIONS 1F2021 - -#define GTCCR _SFR_IO8(0x23) -#define PSRSYNC 0 -#define PSRASY 1 -#define TSM 7 - -#define TCCR0A _SFR_IO8(0x24) -#define WGM00 0 -#define WGM01 1 -#define COM0B0 4 -#define COM0B1 5 -#define COM0A0 6 -#define COM0A1 7 - -#define TCCR0B _SFR_IO8(0x25) -#define CS00 0 -#define CS01 1 -#define CS02 2 -#define WGM02 3 -#define FOC0B 6 -#define FOC0A 7 - -#define TCNT0 _SFR_IO8(0x26) -#define TCNT0_0 0 -#define TCNT0_1 1 -#define TCNT0_2 2 -#define TCNT0_3 3 -#define TCNT0_4 4 -#define TCNT0_5 5 -#define TCNT0_6 6 -#define TCNT0_7 7 - -#define OCR0A _SFR_IO8(0x27) -#define OCR0A_0 0 -#define OCR0A_1 1 -#define OCR0A_2 2 -#define OCR0A_3 3 -#define OCR0A_4 4 -#define OCR0A_5 5 -#define OCR0A_6 6 -#define OCR0A_7 7 - -#define OCR0B _SFR_IO8(0x28) -#define OCR0B_0 0 -#define OCR0B_1 1 -#define OCR0B_2 2 -#define OCR0B_3 3 -#define OCR0B_4 4 -#define OCR0B_5 5 -#define OCR0B_6 6 -#define OCR0B_7 7 - -#define GPIOR1 _SFR_IO8(0x2A) -#define GPIOR10 0 -#define GPIOR11 1 -#define GPIOR12 2 -#define GPIOR13 3 -#define GPIOR14 4 -#define GPIOR15 5 -#define GPIOR16 6 -#define GPIOR17 7 - -#define GPIOR2 _SFR_IO8(0x2B) -#define GPIOR20 0 -#define GPIOR21 1 -#define GPIOR22 2 -#define GPIOR23 3 -#define GPIOR24 4 -#define GPIOR25 5 -#define GPIOR26 6 -#define GPIOR27 7 - -#define SPCR _SFR_IO8(0x2C) -#define SPR0 0 -#define SPR1 1 -#define CPHA 2 -#define CPOL 3 -#define MSTR 4 -#define DORD 5 -#define SPE 6 -#define SPIE 7 - -#define SPSR _SFR_IO8(0x2D) -#define SPI2X 0 -#define WCOL 6 -#define SPIF 7 - -#define SPDR _SFR_IO8(0x2E) -#define SPDR0 0 -#define SPDR1 1 -#define SPDR2 2 -#define SPDR3 3 -#define SPDR4 4 -#define SPDR5 5 -#define SPDR6 6 -#define SPDR7 7 - -#define ACSR _SFR_IO8(0x30) -#define ACIS0 0 -#define ACIS1 1 -#define ACIC 2 -#define ACIE 3 -#define ACI 4 -#define ACO 5 -#define ACBG 6 -#define ACD 7 - -#define SMCR _SFR_IO8(0x33) -#define SE 0 -#define SM0 1 -#define SM1 2 -#define SM2 3 - -#define MCUSR _SFR_IO8(0x34) -#define PORF 0 -#define EXTRF 1 -#define BORF 2 -#define WDRF 3 - -#define MCUCR _SFR_IO8(0x35) -#define PUD 4 -#define BODSE 5 -#define BODS 6 - -#define SPMCSR _SFR_IO8(0x37) -#define SELFPRGEN 0 -#define SPMEN 0 -#define PGERS 1 -#define PGWRT 2 -#define BLBSET 3 -#define RWWSRE 4 -#define SIGRD 5 -#define RWWSB 6 -#define SPMIE 7 - -#define WDTCSR _SFR_MEM8(0x60) -#define WDP0 0 -#define WDP1 1 -#define WDP2 2 -#define WDE 3 -#define WDCE 4 -#define WDP3 5 -#define WDIE 6 -#define WDIF 7 - -#define CLKPR _SFR_MEM8(0x61) -#define CLKPS0 0 -#define CLKPS1 1 -#define CLKPS2 2 -#define CLKPS3 3 -#define CLKPCE 7 - -#define PRR _SFR_MEM8(0x64) -#define PRADC 0 -#define PRUSART0 1 -#define PRSPI 2 -#define PRTIM1 3 -#define PRTIM0 5 -#define PRTIM2 6 -#define PRTWI 7 - -#define __AVR_HAVE_PRR ((1< instead of this file." -#endif - -#ifndef _AVR_IOXXX_H_ -# define _AVR_IOXXX_H_ "iom48pa.h" -#else -# error "Attempt to include more than one file." -#endif - -/* Registers and associated bit numbers */ - -#define PINB _SFR_IO8(0x03) -#define PINB7 7 -#define PINB6 6 -#define PINB5 5 -#define PINB4 4 -#define PINB3 3 -#define PINB2 2 -#define PINB1 1 -#define PINB0 0 - -#define DDRB _SFR_IO8(0x04) -#define DDRB7 7 -// Inserted "DDB7" from "DDRB7" due to compatibility -#define DDB7 7 -#define DDRB6 6 -// Inserted "DDB6" from "DDRB6" due to compatibility -#define DDB6 6 -#define DDRB5 5 -// Inserted "DDB5" from "DDRB5" due to compatibility -#define DDB5 5 -#define DDRB4 4 -// Inserted "DDB4" from "DDRB4" due to compatibility -#define DDB4 4 -#define DDRB3 3 -// Inserted "DDB3" from "DDRB3" due to compatibility -#define DDB3 3 -#define DDRB2 2 -// Inserted "DDB2" from "DDRB2" due to compatibility -#define DDB2 2 -#define DDRB1 1 -// Inserted "DDB1" from "DDRB1" due to compatibility -#define DDB1 1 -#define DDRB0 0 -// Inserted "DDB0" from "DDRB0" due to compatibility -#define DDB0 0 - -#define PORTB _SFR_IO8(0x05) -#define PORTB7 7 -#define PORTB6 6 -#define PORTB5 5 -#define PORTB4 4 -#define PORTB3 3 -#define PORTB2 2 -#define PORTB1 1 -#define PORTB0 0 - -#define PINC _SFR_IO8(0x06) -#define PINC6 6 -#define PINC5 5 -#define PINC4 4 -#define PINC3 3 -#define PINC2 2 -#define PINC1 1 -#define PINC0 0 - -#define DDRC _SFR_IO8(0x07) -#define DDRC6 6 -// Inserted "DDC6" from "DDRC6" due to compatibility -#define DDC6 6 -#define DDRC5 5 -// Inserted "DDC5" from "DDRC5" due to compatibility -#define DDC5 5 -#define DDRC4 4 -// Inserted "DDC4" from "DDRC4" due to compatibility -#define DDC4 4 -#define DDRC3 3 -// Inserted "DDC3" from "DDRC3" due to compatibility -#define DDC3 3 -#define DDRC2 2 -// Inserted "DDC2" from "DDRC2" due to compatibility -#define DDC2 2 -#define DDRC1 1 -// Inserted "DDC1" from "DDRC1" due to compatibility -#define DDC1 1 -#define DDRC0 0 -// Inserted "DDC0" from "DDRC0" due to compatibility -#define DDC0 0 - -#define PORTC _SFR_IO8(0x08) -#define PORTC6 6 -#define PORTC5 5 -#define PORTC4 4 -#define PORTC3 3 -#define PORTC2 2 -#define PORTC1 1 -#define PORTC0 0 - -#define PIND _SFR_IO8(0x09) -#define PIND7 7 -#define PIND6 6 -#define PIND5 5 -#define PIND4 4 -#define PIND3 3 -#define PIND2 2 -#define PIND1 1 -#define PIND0 0 - -#define DDRD _SFR_IO8(0x0A) -#define DDRD7 7 -// Inserted "DDD7" from "DDRD7" due to compatibility -#define DDD7 7 -#define DDRD6 6 -// Inserted "DDD6" from "DDRD6" due to compatibility -#define DDD6 6 -#define DDRD5 5 -// Inserted "DDD5" from "DDRD5" due to compatibility -#define DDD5 5 -#define DDRD4 4 -// Inserted "DDD4" from "DDRD4" due to compatibility -#define DDD4 4 -#define DDRD3 3 -// Inserted "DDD3" from "DDRD3" due to compatibility -#define DDD3 3 -#define DDRD2 2 -// Inserted "DDD2" from "DDRD2" due to compatibility -#define DDD2 2 -#define DDRD1 1 -// Inserted "DDD1" from "DDRD1" due to compatibility -#define DDD1 1 -#define DDRD0 0 -// Inserted "DDD0" from "DDRD0" due to compatibility -#define DDD0 0 - -#define PORTD _SFR_IO8(0x0B) -#define PORTD7 7 -#define PORTD6 6 -#define PORTD5 5 -#define PORTD4 4 -#define PORTD3 3 -#define PORTD2 2 -#define PORTD1 1 -#define PORTD0 0 - -/* Reserved [0x0C..0x14] */ - -#define TIFR0 _SFR_IO8(0x15) -#define TOV0 0 -#define OCF0A 1 -#define OCF0B 2 - -#define TIFR1 _SFR_IO8(0x16) -#define TOV1 0 -#define OCF1A 1 -#define OCF1B 2 -#define ICF1 5 - -#define TIFR2 _SFR_IO8(0x17) -#define TOV2 0 -#define OCF2A 1 -#define OCF2B 2 - -/* Reserved [0x18..0x1A] */ - -#define PCIFR _SFR_IO8(0x1B) -#define PCIF0 0 -#define PCIF1 1 -#define PCIF2 2 - -#define EIFR _SFR_IO8(0x1C) -#define INTF0 0 -#define INTF1 1 - -#define EIMSK _SFR_IO8(0x1D) -#define INT0 0 -#define INT1 1 - -#define GPIOR0 _SFR_IO8(0x1E) - -#define EECR _SFR_IO8(0x1F) -#define EERE 0 -#define EEPE 1 -#define EEMPE 2 -#define EERIE 3 -#define EEPM0 4 -#define EEPM1 5 - -#define EEDR _SFR_IO8(0x20) - -#define EEARL _SFR_IO8(0x21) - -#define EEARH _SFR_IO8(0x22) -#define EEAR8 0 -#define EEAR9 1 - -#define GTCCR _SFR_IO8(0x23) -#define PSRSYNC 0 -#define TSM 7 -#define PSRASY 1 - -#define TCCR0A _SFR_IO8(0x24) -#define WGM00 0 -#define WGM01 1 -#define COM0B0 4 -#define COM0B1 5 -#define COM0A0 6 -#define COM0A1 7 - -#define TCCR0B _SFR_IO8(0x25) -#define CS00 0 -#define CS01 1 -#define CS02 2 -#define WGM02 3 -#define FOC0B 6 -#define FOC0A 7 - -#define TCNT0 _SFR_IO8(0x26) - -#define OCR0A _SFR_IO8(0x27) - -#define OCR0B _SFR_IO8(0x28) - -/* Reserved [0x29] */ - -#define GPIOR1 _SFR_IO8(0x2A) - -#define GPIOR2 _SFR_IO8(0x2B) - -#define SPCR _SFR_IO8(0x2C) -#define SPR0 0 -#define SPR1 1 -#define CPHA 2 -#define CPOL 3 -#define MSTR 4 -#define DORD 5 -#define SPE 6 -#define SPIE 7 - -#define SPSR _SFR_IO8(0x2D) -#define SPI2X 0 -#define WCOL 6 -#define SPIF 7 - -#define SPDR _SFR_IO8(0x2E) - -/* Reserved [0x2F] */ - -#define ACSR _SFR_IO8(0x30) -#define ACIS0 0 -#define ACIS1 1 -#define ACIC 2 -#define ACIE 3 -#define ACI 4 -#define ACO 5 -#define ACBG 6 -#define ACD 7 - -/* Reserved [0x31..0x32] */ - -#define SMCR _SFR_IO8(0x33) -#define SE 0 -#define SM0 1 -#define SM1 2 -#define SM2 3 - -#define MCUSR _SFR_IO8(0x34) -#define PORF 0 -#define EXTRF 1 -#define BORF 2 -#define WDRF 3 - -#define MCUCR _SFR_IO8(0x35) -#define IVCE 0 -#define IVSEL 1 -#define PUD 4 -#define BODSE 5 -#define BODS 6 - -/* Reserved [0x36] */ - -#define SPMCSR _SFR_IO8(0x37) -#define SPMEN 0 -#define PGERS 1 -#define PGWRT 2 -#define BLBSET 3 -#define RWWSRE 4 -#define SIGRD 5 -#define RWWSB 6 -#define SPMIE 7 - -/* Reserved [0x38..0x3C] */ - -/* SP [0x3D..0x3E] */ - -/* SREG [0x3F] */ - -#define WDTCSR _SFR_MEM8(0x60) -#define WDE 3 -#define WDCE 4 -#define WDP0 0 -#define WDP1 1 -#define WDP2 2 -#define WDP3 5 -#define WDIE 6 -#define WDIF 7 - -#define CLKPR _SFR_MEM8(0x61) -#define CLKPS0 0 -#define CLKPS1 1 -#define CLKPS2 2 -#define CLKPS3 3 -#define CLKPCE 7 - -/* Reserved [0x62..0x63] */ - -#define PRR _SFR_MEM8(0x64) -#define PRADC 0 -#define PRUSART0 1 -#define PRSPI 2 -#define PRTIM1 3 -#define PRTIM0 5 -#define PRTIM2 6 -#define PRTWI 7 - -#define __AVR_HAVE_PRR ((1< instead of this file." -#endif - -#ifndef _AVR_IOXXX_H_ -# define _AVR_IOXXX_H_ "iom48pb.h" -#else -# error "Attempt to include more than one file." -#endif - -/* Registers and associated bit numbers */ - -#define PINB _SFR_IO8(0x03) -#define PINB7 7 -#define PINB6 6 -#define PINB5 5 -#define PINB4 4 -#define PINB3 3 -#define PINB2 2 -#define PINB1 1 -#define PINB0 0 - -#define DDRB _SFR_IO8(0x04) -#define DDRB7 7 -// Inserted "DDB7" from "DDRB7" due to compatibility -#define DDB7 7 -#define DDRB6 6 -// Inserted "DDB6" from "DDRB6" due to compatibility -#define DDB6 6 -#define DDRB5 5 -// Inserted "DDB5" from "DDRB5" due to compatibility -#define DDB5 5 -#define DDRB4 4 -// Inserted "DDB4" from "DDRB4" due to compatibility -#define DDB4 4 -#define DDRB3 3 -// Inserted "DDB3" from "DDRB3" due to compatibility -#define DDB3 3 -#define DDRB2 2 -// Inserted "DDB2" from "DDRB2" due to compatibility -#define DDB2 2 -#define DDRB1 1 -// Inserted "DDB1" from "DDRB1" due to compatibility -#define DDB1 1 -#define DDRB0 0 -// Inserted "DDB0" from "DDRB0" due to compatibility -#define DDB0 0 - -#define PORTB _SFR_IO8(0x05) -#define PORTB7 7 -#define PORTB6 6 -#define PORTB5 5 -#define PORTB4 4 -#define PORTB3 3 -#define PORTB2 2 -#define PORTB1 1 -#define PORTB0 0 - -#define PINC _SFR_IO8(0x06) -#define PINC6 6 -#define PINC5 5 -#define PINC4 4 -#define PINC3 3 -#define PINC2 2 -#define PINC1 1 -#define PINC0 0 - -#define DDRC _SFR_IO8(0x07) -#define DDRC6 6 -// Inserted "DDC6" from "DDRC6" due to compatibility -#define DDC6 6 -#define DDRC5 5 -// Inserted "DDC5" from "DDRC5" due to compatibility -#define DDC5 5 -#define DDRC4 4 -// Inserted "DDC4" from "DDRC4" due to compatibility -#define DDC4 4 -#define DDRC3 3 -// Inserted "DDC3" from "DDRC3" due to compatibility -#define DDC3 3 -#define DDRC2 2 -// Inserted "DDC2" from "DDRC2" due to compatibility -#define DDC2 2 -#define DDRC1 1 -// Inserted "DDC1" from "DDRC1" due to compatibility -#define DDC1 1 -#define DDRC0 0 -// Inserted "DDC0" from "DDRC0" due to compatibility -#define DDC0 0 - -#define PORTC _SFR_IO8(0x08) -#define PORTC6 6 -#define PORTC5 5 -#define PORTC4 4 -#define PORTC3 3 -#define PORTC2 2 -#define PORTC1 1 -#define PORTC0 0 - -#define PIND _SFR_IO8(0x09) -#define PIND7 7 -#define PIND6 6 -#define PIND5 5 -#define PIND4 4 -#define PIND3 3 -#define PIND2 2 -#define PIND1 1 -#define PIND0 0 - -#define DDRD _SFR_IO8(0x0A) -#define DDRD7 7 -// Inserted "DDD7" from "DDRD7" due to compatibility -#define DDD7 7 -#define DDRD6 6 -// Inserted "DDD6" from "DDRD6" due to compatibility -#define DDD6 6 -#define DDRD5 5 -// Inserted "DDD5" from "DDRD5" due to compatibility -#define DDD5 5 -#define DDRD4 4 -// Inserted "DDD4" from "DDRD4" due to compatibility -#define DDD4 4 -#define DDRD3 3 -// Inserted "DDD3" from "DDRD3" due to compatibility -#define DDD3 3 -#define DDRD2 2 -// Inserted "DDD2" from "DDRD2" due to compatibility -#define DDD2 2 -#define DDRD1 1 -// Inserted "DDD1" from "DDRD1" due to compatibility -#define DDD1 1 -#define DDRD0 0 -// Inserted "DDD0" from "DDRD0" due to compatibility -#define DDD0 0 - -#define PORTD _SFR_IO8(0x0B) -#define PORTD7 7 -#define PORTD6 6 -#define PORTD5 5 -#define PORTD4 4 -#define PORTD3 3 -#define PORTD2 2 -#define PORTD1 1 -#define PORTD0 0 - -#define PINE _SFR_IO8(0x0C) -#define PINE3 3 -#define PINE2 2 -#define PINE1 1 -#define PINE0 0 - -#define DDRE _SFR_IO8(0x0D) -#define DDRE3 3 -// Inserted "DDE3" from "DDRE3" due to compatibility -#define DDE3 3 -#define DDRE2 2 -// Inserted "DDE2" from "DDRE2" due to compatibility -#define DDE2 2 -#define DDRE1 1 -// Inserted "DDE1" from "DDRE1" due to compatibility -#define DDE1 1 -#define DDRE0 0 -// Inserted "DDE0" from "DDRE0" due to compatibility -#define DDE0 0 - -#define PORTE _SFR_IO8(0x0E) -#define PORTE3 3 -#define PORTE2 2 -#define PORTE1 1 -#define PORTE0 0 - -#define ACSRB _SFR_IO8(0x0F) -#define ACOE 0 - -/* Reserved [0x10..0x14] */ - -#define TIFR0 _SFR_IO8(0x15) -#define TOV0 0 -#define OCF0A 1 -#define OCF0B 2 - -#define TIFR1 _SFR_IO8(0x16) -#define TOV1 0 -#define OCF1A 1 -#define OCF1B 2 -#define ICF1 5 - -#define TIFR2 _SFR_IO8(0x17) -#define TOV2 0 -#define OCF2A 1 -#define OCF2B 2 - -/* Reserved [0x18..0x1A] */ - -#define PCIFR _SFR_IO8(0x1B) -#define PCIF0 0 -#define PCIF1 1 -#define PCIF2 2 - -#define EIFR _SFR_IO8(0x1C) -#define INTF0 0 -#define INTF1 1 - -#define EIMSK _SFR_IO8(0x1D) -#define INT0 0 -#define INT1 1 - -#define GPIOR0 _SFR_IO8(0x1E) - -#define EECR _SFR_IO8(0x1F) -#define EERE 0 -#define EEPE 1 -#define EEMPE 2 -#define EERIE 3 -#define EEPM0 4 -#define EEPM1 5 - -#define EEDR _SFR_IO8(0x20) - -#define EEARL _SFR_IO8(0x21) - -/* Reserved [0x22] */ - -#define GTCCR _SFR_IO8(0x23) -#define PSRSYNC 0 -#define TSM 7 -#define PSRASY 1 - -#define TCCR0A _SFR_IO8(0x24) -#define WGM00 0 -#define WGM01 1 -#define COM0B0 4 -#define COM0B1 5 -#define COM0A0 6 -#define COM0A1 7 - -#define TCCR0B _SFR_IO8(0x25) -#define CS00 0 -#define CS01 1 -#define CS02 2 -#define WGM02 3 -#define FOC0B 6 -#define FOC0A 7 - -#define TCNT0 _SFR_IO8(0x26) - -#define OCR0A _SFR_IO8(0x27) - -#define OCR0B _SFR_IO8(0x28) - -/* Reserved [0x29] */ - -#define GPIOR1 _SFR_IO8(0x2A) - -#define GPIOR2 _SFR_IO8(0x2B) - -#define SPCR _SFR_IO8(0x2C) -#define SPR0 0 -#define SPR1 1 -#define CPHA 2 -#define CPOL 3 -#define MSTR 4 -#define DORD 5 -#define SPE 6 -#define SPIE 7 - -#define SPSR _SFR_IO8(0x2D) -#define SPI2X 0 -#define WCOL 6 -#define SPIF 7 - -#define SPDR _SFR_IO8(0x2E) - -/* Reserved [0x2F] */ - -#define ACSR _SFR_IO8(0x30) -#define ACIS0 0 -#define ACIS1 1 -#define ACIC 2 -#define ACIE 3 -#define ACI 4 -#define ACO 5 -#define ACBG 6 -#define ACD 7 - -/* Reserved [0x31..0x32] */ - -#define SMCR _SFR_IO8(0x33) -#define SE 0 -#define SM0 1 -#define SM1 2 -#define SM2 3 - -#define MCUSR _SFR_IO8(0x34) -#define PORF 0 -#define EXTRF 1 -#define BORF 2 -#define WDRF 3 - -#define MCUCR _SFR_IO8(0x35) -#define PUD 4 -#define BODSE 5 -#define BODS 6 - -/* Reserved [0x36] */ - -#define SPMCSR _SFR_IO8(0x37) -#define SELFPRGEN 0 -#define PGERS 1 -#define PGWRT 2 -#define BLBSET 3 -#define RWWSRE 4 -#define RWWSB 6 -#define SPMIE 7 - -/* Reserved [0x38..0x3C] */ - -/* SP [0x3D..0x3E] */ - -/* SREG [0x3F] */ - -#define WDTCSR _SFR_MEM8(0x60) -#define WDE 3 -#define WDCE 4 -#define WDP0 0 -#define WDP1 1 -#define WDP2 2 -#define WDP3 5 -#define WDIE 6 -#define WDIF 7 - -#define CLKPR _SFR_MEM8(0x61) -#define CLKPS0 0 -#define CLKPS1 1 -#define CLKPS2 2 -#define CLKPS3 3 -#define CLKPCE 7 - -/* Reserved [0x62..0x63] */ - -#define PRR _SFR_MEM8(0x64) -#define PRADC 0 -#define PRUSART0 1 -#define PRSPI 2 -#define PRTIM1 3 -#define PRTIM0 5 -#define PRTIM2 6 -#define PRTWI 7 - -#define __AVR_HAVE_PRR ((1<, never directly. */ - -#ifndef _AVR_IO_H_ -# error "Include instead of this file." -#endif - -#ifndef _AVR_IOXXX_H_ -# define _AVR_IOXXX_H_ "iom64.h" -#else -# error "Attempt to include more than one file." -#endif - -/* I/O registers */ - -/* Input Pins, Port F */ -#define PINF _SFR_IO8(0x00) - -/* Input Pins, Port E */ -#define PINE _SFR_IO8(0x01) - -/* Data Direction Register, Port E */ -#define DDRE _SFR_IO8(0x02) - -/* Data Register, Port E */ -#define PORTE _SFR_IO8(0x03) - -/* ADC Data Register */ -#define ADCW _SFR_IO16(0x04) /* for backwards compatibility */ -#ifndef __ASSEMBLER__ -#define ADC _SFR_IO16(0x04) -#endif -#define ADCL _SFR_IO8(0x04) -#define ADCH _SFR_IO8(0x05) - -/* ADC Control and Status Register A */ -#define ADCSR _SFR_IO8(0x06) /* for backwards compatibility */ -#define ADCSRA _SFR_IO8(0x06) - -/* ADC Multiplexer select */ -#define ADMUX _SFR_IO8(0x07) - -/* Analog Comparator Control and Status Register */ -#define ACSR _SFR_IO8(0x08) - -/* USART0 Baud Rate Register Low */ -#define UBRR0L _SFR_IO8(0x09) - -/* USART0 Control and Status Register B */ -#define UCSR0B _SFR_IO8(0x0A) - -/* USART0 Control and Status Register A */ -#define UCSR0A _SFR_IO8(0x0B) - -/* USART0 I/O Data Register */ -#define UDR0 _SFR_IO8(0x0C) - -/* SPI Control Register */ -#define SPCR _SFR_IO8(0x0D) - -/* SPI Status Register */ -#define SPSR _SFR_IO8(0x0E) - -/* SPI I/O Data Register */ -#define SPDR _SFR_IO8(0x0F) - -/* Input Pins, Port D */ -#define PIND _SFR_IO8(0x10) - -/* Data Direction Register, Port D */ -#define DDRD _SFR_IO8(0x11) - -/* Data Register, Port D */ -#define PORTD _SFR_IO8(0x12) - -/* Input Pins, Port C */ -#define PINC _SFR_IO8(0x13) - -/* Data Direction Register, Port C */ -#define DDRC _SFR_IO8(0x14) - -/* Data Register, Port C */ -#define PORTC _SFR_IO8(0x15) - -/* Input Pins, Port B */ -#define PINB _SFR_IO8(0x16) - -/* Data Direction Register, Port B */ -#define DDRB _SFR_IO8(0x17) - -/* Data Register, Port B */ -#define PORTB _SFR_IO8(0x18) - -/* Input Pins, Port A */ -#define PINA _SFR_IO8(0x19) - -/* Data Direction Register, Port A */ -#define DDRA _SFR_IO8(0x1A) - -/* Data Register, Port A */ -#define PORTA _SFR_IO8(0x1B) - -/* EEPROM Control Register */ -#define EECR _SFR_IO8(0x1C) - -/* EEPROM Data Register */ -#define EEDR _SFR_IO8(0x1D) - -/* EEPROM Address Register */ -#define EEAR _SFR_IO16(0x1E) -#define EEARL _SFR_IO8(0x1E) -#define EEARH _SFR_IO8(0x1F) - -/* Special Function I/O Register */ -#define SFIOR _SFR_IO8(0x20) - -/* Watchdog Timer Control Register */ -#define WDTCR _SFR_IO8(0x21) - -/* On-chip Debug Register */ -#define OCDR _SFR_IO8(0x22) - -/* Timer2 Output Compare Register */ -#define OCR2 _SFR_IO8(0x23) - -/* Timer/Counter 2 */ -#define TCNT2 _SFR_IO8(0x24) - -/* Timer/Counter 2 Control register */ -#define TCCR2 _SFR_IO8(0x25) - -/* T/C 1 Input Capture Register */ -#define ICR1 _SFR_IO16(0x26) -#define ICR1L _SFR_IO8(0x26) -#define ICR1H _SFR_IO8(0x27) - -/* Timer/Counter1 Output Compare Register B */ -#define OCR1B _SFR_IO16(0x28) -#define OCR1BL _SFR_IO8(0x28) -#define OCR1BH _SFR_IO8(0x29) - -/* Timer/Counter1 Output Compare Register A */ -#define OCR1A _SFR_IO16(0x2A) -#define OCR1AL _SFR_IO8(0x2A) -#define OCR1AH _SFR_IO8(0x2B) - -/* Timer/Counter 1 */ -#define TCNT1 _SFR_IO16(0x2C) -#define TCNT1L _SFR_IO8(0x2C) -#define TCNT1H _SFR_IO8(0x2D) - -/* Timer/Counter 1 Control and Status Register */ -#define TCCR1B _SFR_IO8(0x2E) - -/* Timer/Counter 1 Control Register */ -#define TCCR1A _SFR_IO8(0x2F) - -/* Timer/Counter 0 Asynchronous Control & Status Register */ -#define ASSR _SFR_IO8(0x30) - -/* Output Compare Register 0 */ -#define OCR0 _SFR_IO8(0x31) - -/* Timer/Counter 0 */ -#define TCNT0 _SFR_IO8(0x32) - -/* Timer/Counter 0 Control Register */ -#define TCCR0 _SFR_IO8(0x33) - -/* MCU Status Register */ -#define MCUSR _SFR_IO8(0x34) /* for backwards compatibility */ -#define MCUCSR _SFR_IO8(0x34) - -/* MCU general Control Register */ -#define MCUCR _SFR_IO8(0x35) - -/* Timer/Counter Interrupt Flag Register */ -#define TIFR _SFR_IO8(0x36) - -/* Timer/Counter Interrupt MaSK register */ -#define TIMSK _SFR_IO8(0x37) - -/* External Interrupt Flag Register */ -#define EIFR _SFR_IO8(0x38) - -/* External Interrupt MaSK register */ -#define EIMSK _SFR_IO8(0x39) - -/* External Interrupt Control Register B */ -#define EICRB _SFR_IO8(0x3A) - -/* XDIV Divide control register */ -#define XDIV _SFR_IO8(0x3C) - -/* 0x3D..0x3E SP */ - -/* 0x3F SREG */ - -/* Extended I/O registers */ - -/* Data Direction Register, Port F */ -#define DDRF _SFR_MEM8(0x61) - -/* Data Register, Port F */ -#define PORTF _SFR_MEM8(0x62) - -/* Input Pins, Port G */ -#define PING _SFR_MEM8(0x63) - -/* Data Direction Register, Port G */ -#define DDRG _SFR_MEM8(0x64) - -/* Data Register, Port G */ -#define PORTG _SFR_MEM8(0x65) - -/* Store Program Memory Control and Status Register */ -#define SPMCR _SFR_MEM8(0x68) -#define SPMCSR _SFR_MEM8(0x68) /* for backwards compatibility with m128*/ - -/* External Interrupt Control Register A */ -#define EICRA _SFR_MEM8(0x6A) - -/* External Memory Control Register B */ -#define XMCRB _SFR_MEM8(0x6C) - -/* External Memory Control Register A */ -#define XMCRA _SFR_MEM8(0x6D) - -/* Oscillator Calibration Register */ -#define OSCCAL _SFR_MEM8(0x6F) - -/* 2-wire Serial Interface Bit Rate Register */ -#define TWBR _SFR_MEM8(0x70) - -/* 2-wire Serial Interface Status Register */ -#define TWSR _SFR_MEM8(0x71) - -/* 2-wire Serial Interface Address Register */ -#define TWAR _SFR_MEM8(0x72) - -/* 2-wire Serial Interface Data Register */ -#define TWDR _SFR_MEM8(0x73) - -/* 2-wire Serial Interface Control Register */ -#define TWCR _SFR_MEM8(0x74) - -/* Time Counter 1 Output Compare Register C */ -#define OCR1C _SFR_MEM16(0x78) -#define OCR1CL _SFR_MEM8(0x78) -#define OCR1CH _SFR_MEM8(0x79) - -/* Timer/Counter 1 Control Register C */ -#define TCCR1C _SFR_MEM8(0x7A) - -/* Extended Timer Interrupt Flag Register */ -#define ETIFR _SFR_MEM8(0x7C) - -/* Extended Timer Interrupt Mask Register */ -#define ETIMSK _SFR_MEM8(0x7D) - -/* Timer/Counter 3 Input Capture Register */ -#define ICR3 _SFR_MEM16(0x80) -#define ICR3L _SFR_MEM8(0x80) -#define ICR3H _SFR_MEM8(0x81) - -/* Timer/Counter 3 Output Compare Register C */ -#define OCR3C _SFR_MEM16(0x82) -#define OCR3CL _SFR_MEM8(0x82) -#define OCR3CH _SFR_MEM8(0x83) - -/* Timer/Counter 3 Output Compare Register B */ -#define OCR3B _SFR_MEM16(0x84) -#define OCR3BL _SFR_MEM8(0x84) -#define OCR3BH _SFR_MEM8(0x85) - -/* Timer/Counter 3 Output Compare Register A */ -#define OCR3A _SFR_MEM16(0x86) -#define OCR3AL _SFR_MEM8(0x86) -#define OCR3AH _SFR_MEM8(0x87) - -/* Timer/Counter 3 Counter Register */ -#define TCNT3 _SFR_MEM16(0x88) -#define TCNT3L _SFR_MEM8(0x88) -#define TCNT3H _SFR_MEM8(0x89) - -/* Timer/Counter 3 Control Register B */ -#define TCCR3B _SFR_MEM8(0x8A) - -/* Timer/Counter 3 Control Register A */ -#define TCCR3A _SFR_MEM8(0x8B) - -/* Timer/Counter 3 Control Register C */ -#define TCCR3C _SFR_MEM8(0x8C) - -/* ADC Control and Status Register B */ -#define ADCSRB _SFR_MEM8(0x8E) - -/* USART0 Baud Rate Register High */ -#define UBRR0H _SFR_MEM8(0x90) - -/* USART0 Control and Status Register C */ -#define UCSR0C _SFR_MEM8(0x95) - -/* USART1 Baud Rate Register High */ -#define UBRR1H _SFR_MEM8(0x98) - -/* USART1 Baud Rate Register Low*/ -#define UBRR1L _SFR_MEM8(0x99) - -/* USART1 Control and Status Register B */ -#define UCSR1B _SFR_MEM8(0x9A) - -/* USART1 Control and Status Register A */ -#define UCSR1A _SFR_MEM8(0x9B) - -/* USART1 I/O Data Register */ -#define UDR1 _SFR_MEM8(0x9C) - -/* USART1 Control and Status Register C */ -#define UCSR1C _SFR_MEM8(0x9D) - -/* Interrupt vectors */ - -/* External Interrupt Request 0 */ -#define INT0_vect_num 1 -#define INT0_vect _VECTOR(1) -#define SIG_INTERRUPT0 _VECTOR(1) - -/* External Interrupt Request 1 */ -#define INT1_vect_num 2 -#define INT1_vect _VECTOR(2) -#define SIG_INTERRUPT1 _VECTOR(2) - -/* External Interrupt Request 2 */ -#define INT2_vect_num 3 -#define INT2_vect _VECTOR(3) -#define SIG_INTERRUPT2 _VECTOR(3) - -/* External Interrupt Request 3 */ -#define INT3_vect_num 4 -#define INT3_vect _VECTOR(4) -#define SIG_INTERRUPT3 _VECTOR(4) - -/* External Interrupt Request 4 */ -#define INT4_vect_num 5 -#define INT4_vect _VECTOR(5) -#define SIG_INTERRUPT4 _VECTOR(5) - -/* External Interrupt Request 5 */ -#define INT5_vect_num 6 -#define INT5_vect _VECTOR(6) -#define SIG_INTERRUPT5 _VECTOR(6) - -/* External Interrupt Request 6 */ -#define INT6_vect_num 7 -#define INT6_vect _VECTOR(7) -#define SIG_INTERRUPT6 _VECTOR(7) - -/* External Interrupt Request 7 */ -#define INT7_vect_num 8 -#define INT7_vect _VECTOR(8) -#define SIG_INTERRUPT7 _VECTOR(8) - -/* Timer/Counter2 Compare Match */ -#define TIMER2_COMP_vect_num 9 -#define TIMER2_COMP_vect _VECTOR(9) -#define SIG_OUTPUT_COMPARE2 _VECTOR(9) - -/* Timer/Counter2 Overflow */ -#define TIMER2_OVF_vect_num 10 -#define TIMER2_OVF_vect _VECTOR(10) -#define SIG_OVERFLOW2 _VECTOR(10) - -/* Timer/Counter1 Capture Event */ -#define TIMER1_CAPT_vect_num 11 -#define TIMER1_CAPT_vect _VECTOR(11) -#define SIG_INPUT_CAPTURE1 _VECTOR(11) - -/* Timer/Counter1 Compare Match A */ -#define TIMER1_COMPA_vect_num 12 -#define TIMER1_COMPA_vect _VECTOR(12) -#define SIG_OUTPUT_COMPARE1A _VECTOR(12) - -/* Timer/Counter Compare Match B */ -#define TIMER1_COMPB_vect_num 13 -#define TIMER1_COMPB_vect _VECTOR(13) -#define SIG_OUTPUT_COMPARE1B _VECTOR(13) - -/* Timer/Counter1 Overflow */ -#define TIMER1_OVF_vect_num 14 -#define TIMER1_OVF_vect _VECTOR(14) -#define SIG_OVERFLOW1 _VECTOR(14) - -/* Timer/Counter0 Compare Match */ -#define TIMER0_COMP_vect_num 15 -#define TIMER0_COMP_vect _VECTOR(15) -#define SIG_OUTPUT_COMPARE0 _VECTOR(15) - -/* Timer/Counter0 Overflow */ -#define TIMER0_OVF_vect_num 16 -#define TIMER0_OVF_vect _VECTOR(16) -#define SIG_OVERFLOW0 _VECTOR(16) - -/* SPI Serial Transfer Complete */ -#define SPI_STC_vect_num 17 -#define SPI_STC_vect _VECTOR(17) -#define SIG_SPI _VECTOR(17) - -/* USART0, Rx Complete */ -#define USART0_RX_vect_num 18 -#define USART0_RX_vect _VECTOR(18) -#define SIG_UART0_RECV _VECTOR(18) - -/* USART0 Data Register Empty */ -#define USART0_UDRE_vect_num 19 -#define USART0_UDRE_vect _VECTOR(19) -#define SIG_UART0_DATA _VECTOR(19) - -/* USART0, Tx Complete */ -#define USART0_TX_vect_num 20 -#define USART0_TX_vect _VECTOR(20) -#define SIG_UART0_TRANS _VECTOR(20) - -/* ADC Conversion Complete */ -#define ADC_vect_num 21 -#define ADC_vect _VECTOR(21) -#define SIG_ADC _VECTOR(21) - -/* EEPROM Ready */ -#define EE_READY_vect_num 22 -#define EE_READY_vect _VECTOR(22) -#define SIG_EEPROM_READY _VECTOR(22) - -/* Analog Comparator */ -#define ANALOG_COMP_vect_num 23 -#define ANALOG_COMP_vect _VECTOR(23) -#define SIG_COMPARATOR _VECTOR(23) - -/* Timer/Counter1 Compare Match C */ -#define TIMER1_COMPC_vect_num 24 -#define TIMER1_COMPC_vect _VECTOR(24) -#define SIG_OUTPUT_COMPARE1C _VECTOR(24) - -/* Timer/Counter3 Capture Event */ -#define TIMER3_CAPT_vect_num 25 -#define TIMER3_CAPT_vect _VECTOR(25) -#define SIG_INPUT_CAPTURE3 _VECTOR(25) - -/* Timer/Counter3 Compare Match A */ -#define TIMER3_COMPA_vect_num 26 -#define TIMER3_COMPA_vect _VECTOR(26) -#define SIG_OUTPUT_COMPARE3A _VECTOR(26) - -/* Timer/Counter3 Compare Match B */ -#define TIMER3_COMPB_vect_num 27 -#define TIMER3_COMPB_vect _VECTOR(27) -#define SIG_OUTPUT_COMPARE3B _VECTOR(27) - -/* Timer/Counter3 Compare Match C */ -#define TIMER3_COMPC_vect_num 28 -#define TIMER3_COMPC_vect _VECTOR(28) -#define SIG_OUTPUT_COMPARE3C _VECTOR(28) - -/* Timer/Counter3 Overflow */ -#define TIMER3_OVF_vect_num 29 -#define TIMER3_OVF_vect _VECTOR(29) -#define SIG_OVERFLOW3 _VECTOR(29) - -/* USART1, Rx Complete */ -#define USART1_RX_vect_num 30 -#define USART1_RX_vect _VECTOR(30) -#define SIG_UART1_RECV _VECTOR(30) - -/* USART1, Data Register Empty */ -#define USART1_UDRE_vect_num 31 -#define USART1_UDRE_vect _VECTOR(31) -#define SIG_UART1_DATA _VECTOR(31) - -/* USART1, Tx Complete */ -#define USART1_TX_vect_num 32 -#define USART1_TX_vect _VECTOR(32) -#define SIG_UART1_TRANS _VECTOR(32) - -/* 2-wire Serial Interface */ -#define TWI_vect_num 33 -#define TWI_vect _VECTOR(33) -#define SIG_2WIRE_SERIAL _VECTOR(33) - -/* Store Program Memory Read */ -#define SPM_READY_vect_num 34 -#define SPM_READY_vect _VECTOR(34) -#define SIG_SPM_READY _VECTOR(34) - -#define _VECTORS_SIZE 140 - -/* - The Register Bit names are represented by their bit number (0-7). -*/ - -/* 2-wire Control Register - TWCR */ -#define TWINT 7 -#define TWEA 6 -#define TWSTA 5 -#define TWSTO 4 -#define TWWC 3 -#define TWEN 2 -#define TWIE 0 - -/* 2-wire Address Register - TWAR */ -#define TWA6 7 -#define TWA5 6 -#define TWA4 5 -#define TWA3 4 -#define TWA2 3 -#define TWA1 2 -#define TWA0 1 -#define TWGCE 0 - -/* 2-wire Status Register - TWSR */ -#define TWS7 7 -#define TWS6 6 -#define TWS5 5 -#define TWS4 4 -#define TWS3 3 -#define TWPS1 1 -#define TWPS0 0 - -/* External Memory Control Register A - XMCRA */ -#define SRL2 6 -#define SRL1 5 -#define SRL0 4 -#define SRW01 3 -#define SRW00 2 -#define SRW11 1 - -/* External Memory Control Register B - XMCRA */ -#define XMBK 7 -#define XMM2 2 -#define XMM1 1 -#define XMM0 0 - -/* XDIV Divide control register - XDIV */ -#define XDIVEN 7 -#define XDIV6 6 -#define XDIV5 5 -#define XDIV4 4 -#define XDIV3 3 -#define XDIV2 2 -#define XDIV1 1 -#define XDIV0 0 - -/* External Interrupt Control Register A - EICRA */ -#define ISC31 7 -#define ISC30 6 -#define ISC21 5 -#define ISC20 4 -#define ISC11 3 -#define ISC10 2 -#define ISC01 1 -#define ISC00 0 - -/* External Interrupt Control Register B - EICRB */ -#define ISC71 7 -#define ISC70 6 -#define ISC61 5 -#define ISC60 4 -#define ISC51 3 -#define ISC50 2 -#define ISC41 1 -#define ISC40 0 - -/* Store Program Memory Control Register - SPMCSR, SPMCR */ -#define SPMIE 7 -#define RWWSB 6 -#define RWWSRE 4 -#define BLBSET 3 -#define PGWRT 2 -#define PGERS 1 -#define SPMEN 0 - -/* External Interrupt MaSK register - EIMSK */ -#define INT7 7 -#define INT6 6 -#define INT5 5 -#define INT4 4 -#define INT3 3 -#define INT2 2 -#define INT1 1 -#define INT0 0 - -/* External Interrupt Flag Register - EIFR */ -#define INTF7 7 -#define INTF6 6 -#define INTF5 5 -#define INTF4 4 -#define INTF3 3 -#define INTF2 2 -#define INTF1 1 -#define INTF0 0 - -/* Timer/Counter Interrupt MaSK register - TIMSK */ -#define OCIE2 7 -#define TOIE2 6 -#define TICIE1 5 -#define OCIE1A 4 -#define OCIE1B 3 -#define TOIE1 2 -#define OCIE0 1 -#define TOIE0 0 - -/* Timer/Counter Interrupt Flag Register - TIFR */ -#define OCF2 7 -#define TOV2 6 -#define ICF1 5 -#define OCF1A 4 -#define OCF1B 3 -#define TOV1 2 -#define OCF0 1 -#define TOV0 0 - -/* Extended Timer Interrupt MaSK register - ETIMSK */ -#define TICIE3 5 -#define OCIE3A 4 -#define OCIE3B 3 -#define TOIE3 2 -#define OCIE3C 1 -#define OCIE1C 0 - -/* Extended Timer Interrupt Flag Register - ETIFR */ -#define ICF3 5 -#define OCF3A 4 -#define OCF3B 3 -#define TOV3 2 -#define OCF3C 1 -#define OCF1C 0 - -/* MCU Control Register - MCUCR */ -#define SRE 7 -#define SRW10 6 -#define SE 5 -#define SM1 4 -#define SM0 3 -#define SM2 2 -#define IVSEL 1 -#define IVCE 0 - -/* MCU Control And Status Register - MCUCSR */ -#define JTD 7 -#define JTRF 4 -#define WDRF 3 -#define BORF 2 -#define EXTRF 1 -#define PORF 0 - -/* Timer/Counter Control Register (generic) */ -#define FOC 7 -#define WGM0 6 -#define COM1 5 -#define COM0 4 -#define WGM1 3 -#define CS2 2 -#define CS1 1 -#define CS0 0 - -/* Timer/Counter 0 Control Register - TCCR0 */ -#define FOC0 7 -#define WGM00 6 -#define COM01 5 -#define COM00 4 -#define WGM01 3 -#define CS02 2 -#define CS01 1 -#define CS00 0 - -/* Timer/Counter 2 Control Register - TCCR2 */ -#define FOC2 7 -#define WGM20 6 -#define COM21 5 -#define COM20 4 -#define WGM21 3 -#define CS22 2 -#define CS21 1 -#define CS20 0 - -/* Timer/Counter 0 Asynchronous Control & Status Register - ASSR */ -#define AS0 3 -#define TCN0UB 2 -#define OCR0UB 1 -#define TCR0UB 0 - -/* Timer/Counter Control Register A (generic) */ -#define COMA1 7 -#define COMA0 6 -#define COMB1 5 -#define COMB0 4 -#define COMC1 3 -#define COMC0 2 -#define WGMA1 1 -#define WGMA0 0 - -/* Timer/Counter 1 Control and Status Register A - TCCR1A */ -#define COM1A1 7 -#define COM1A0 6 -#define COM1B1 5 -#define COM1B0 4 -#define COM1C1 3 -#define COM1C0 2 -#define WGM11 1 -#define WGM10 0 - -/* Timer/Counter 3 Control and Status Register A - TCCR3A */ -#define COM3A1 7 -#define COM3A0 6 -#define COM3B1 5 -#define COM3B0 4 -#define COM3C1 3 -#define COM3C0 2 -#define WGM31 1 -#define WGM30 0 - -/* Timer/Counter Control and Status Register B (generic) */ -#define ICNC 7 -#define ICES 6 -#define WGMB3 4 -#define WGMB2 3 -#define CSB2 2 -#define CSB1 1 -#define CSB0 0 - -/* Timer/Counter 1 Control and Status Register B - TCCR1B */ -#define ICNC1 7 -#define ICES1 6 -#define WGM13 4 -#define WGM12 3 -#define CS12 2 -#define CS11 1 -#define CS10 0 - -/* Timer/Counter 3 Control and Status Register B - TCCR3B */ -#define ICNC3 7 -#define ICES3 6 -#define WGM33 4 -#define WGM32 3 -#define CS32 2 -#define CS31 1 -#define CS30 0 - -/* Timer/Counter Control Register C (generic) */ -#define FOCA 7 -#define FOCB 6 -#define FOCC 5 - -/* Timer/Counter 3 Control Register C - TCCR3C */ -#define FOC3A 7 -#define FOC3B 6 -#define FOC3C 5 - -/* Timer/Counter 1 Control Register C - TCCR1C */ -#define FOC1A 7 -#define FOC1B 6 -#define FOC1C 5 - -/* On-chip Debug Register - OCDR */ -#define IDRD 7 -#define OCDR7 7 -#define OCDR6 6 -#define OCDR5 5 -#define OCDR4 4 -#define OCDR3 3 -#define OCDR2 2 -#define OCDR1 1 -#define OCDR0 0 - -/* Watchdog Timer Control Register - WDTCR */ -#define WDCE 4 -#define WDE 3 -#define WDP2 2 -#define WDP1 1 -#define WDP0 0 - -/* - The ADHSM bit has been removed from all documentation, - as being not needed at all since the comparator has proven - to be fast enough even without feeding it more power. -*/ - -/* Special Function I/O Register - SFIOR */ -#define TSM 7 -#define ACME 3 -#define PUD 2 -#define PSR0 1 -#define PSR321 0 - -/* Port Data Register (generic) */ -#define PORT7 7 -#define PORT6 6 -#define PORT5 5 -#define PORT4 4 -#define PORT3 3 -#define PORT2 2 -#define PORT1 1 -#define PORT0 0 - -/* Port Data Direction Register (generic) */ -#define DD7 7 -#define DD6 6 -#define DD5 5 -#define DD4 4 -#define DD3 3 -#define DD2 2 -#define DD1 1 -#define DD0 0 - -/* Port Input Pins (generic) */ -#define PIN7 7 -#define PIN6 6 -#define PIN5 5 -#define PIN4 4 -#define PIN3 3 -#define PIN2 2 -#define PIN1 1 -#define PIN0 0 - -/* SPI Status Register - SPSR */ -#define SPIF 7 -#define WCOL 6 -#define SPI2X 0 - -/* SPI Control Register - SPCR */ -#define SPIE 7 -#define SPE 6 -#define DORD 5 -#define MSTR 4 -#define CPOL 3 -#define CPHA 2 -#define SPR1 1 -#define SPR0 0 - -/* USART Register C (generic) */ -#define UMSEL 6 -#define UPM1 5 -#define UPM0 4 -#define USBS 3 -#define UCSZ1 2 -#define UCSZ0 1 -#define UCPOL 0 - -/* USART1 Register C - UCSR1C */ -#define UMSEL1 6 -#define UPM11 5 -#define UPM10 4 -#define USBS1 3 -#define UCSZ11 2 -#define UCSZ10 1 -#define UCPOL1 0 - -/* USART0 Register C - UCSR0C */ -#define UMSEL0 6 -#define UPM01 5 -#define UPM00 4 -#define USBS0 3 -#define UCSZ01 2 -#define UCSZ00 1 -#define UCPOL0 0 - -/* USART Status Register A (generic) */ -#define RXC 7 -#define TXC 6 -#define UDRE 5 -#define FE 4 -#define DOR 3 -#define UPE 2 -#define U2X 1 -#define MPCM 0 - -/* USART1 Status Register A - UCSR1A */ -#define RXC1 7 -#define TXC1 6 -#define UDRE1 5 -#define FE1 4 -#define DOR1 3 -#define UPE1 2 -#define U2X1 1 -#define MPCM1 0 - -/* USART0 Status Register A - UCSR0A */ -#define RXC0 7 -#define TXC0 6 -#define UDRE0 5 -#define FE0 4 -#define DOR0 3 -#define UPE0 2 -#define U2X0 1 -#define MPCM0 0 - -/* USART Control Register B (generic) */ -#define RXCIE 7 -#define TXCIE 6 -#define UDRIE 5 -#define RXEN 4 -#define TXEN 3 -#define UCSZ 2 -#define UCSZ2 2 /* new name in datasheet (2467E-AVR-05/02) */ -#define RXB8 1 -#define TXB8 0 - -/* USART1 Control Register B - UCSR1B */ -#define RXCIE1 7 -#define TXCIE1 6 -#define UDRIE1 5 -#define RXEN1 4 -#define TXEN1 3 -#define UCSZ12 2 -#define RXB81 1 -#define TXB81 0 - -/* USART0 Control Register B - UCSR0B */ -#define RXCIE0 7 -#define TXCIE0 6 -#define UDRIE0 5 -#define RXEN0 4 -#define TXEN0 3 -#define UCSZ02 2 -#define RXB80 1 -#define TXB80 0 - -/* Analog Comparator Control and Status Register - ACSR */ -#define ACD 7 -#define ACBG 6 -#define ACO 5 -#define ACI 4 -#define ACIE 3 -#define ACIC 2 -#define ACIS1 1 -#define ACIS0 0 - -/* ADC Control and Status Register B - ADCSRB */ -#define ADTS2 2 -#define ADTS1 1 -#define ADTS0 0 - -/* ADC Control and status Register A - ADCSRA */ -#define ADEN 7 -#define ADSC 6 -#define ADATE 5 -#define ADIF 4 -#define ADIE 3 -#define ADPS2 2 -#define ADPS1 1 -#define ADPS0 0 - -/* ADC Multiplexer select - ADMUX */ -#define REFS1 7 -#define REFS0 6 -#define ADLAR 5 -#define MUX4 4 -#define MUX3 3 -#define MUX2 2 -#define MUX1 1 -#define MUX0 0 - -/* Port A Data Register - PORTA */ -#define PA7 7 -#define PA6 6 -#define PA5 5 -#define PA4 4 -#define PA3 3 -#define PA2 2 -#define PA1 1 -#define PA0 0 - -/* Port A Data Direction Register - DDRA */ -#define DDA7 7 -#define DDA6 6 -#define DDA5 5 -#define DDA4 4 -#define DDA3 3 -#define DDA2 2 -#define DDA1 1 -#define DDA0 0 - -/* Port A Input Pins - PINA */ -#define PINA7 7 -#define PINA6 6 -#define PINA5 5 -#define PINA4 4 -#define PINA3 3 -#define PINA2 2 -#define PINA1 1 -#define PINA0 0 - -/* Port B Data Register - PORTB */ -#define PB7 7 -#define PB6 6 -#define PB5 5 -#define PB4 4 -#define PB3 3 -#define PB2 2 -#define PB1 1 -#define PB0 0 - -/* Port B Data Direction Register - DDRB */ -#define DDB7 7 -#define DDB6 6 -#define DDB5 5 -#define DDB4 4 -#define DDB3 3 -#define DDB2 2 -#define DDB1 1 -#define DDB0 0 - -/* Port B Input Pins - PINB */ -#define PINB7 7 -#define PINB6 6 -#define PINB5 5 -#define PINB4 4 -#define PINB3 3 -#define PINB2 2 -#define PINB1 1 -#define PINB0 0 - -/* Port C Data Register - PORTC */ -#define PC7 7 -#define PC6 6 -#define PC5 5 -#define PC4 4 -#define PC3 3 -#define PC2 2 -#define PC1 1 -#define PC0 0 - -/* Port C Data Direction Register - DDRC */ -#define DDC7 7 -#define DDC6 6 -#define DDC5 5 -#define DDC4 4 -#define DDC3 3 -#define DDC2 2 -#define DDC1 1 -#define DDC0 0 - -/* Port C Input Pins - PINC */ -#define PINC7 7 -#define PINC6 6 -#define PINC5 5 -#define PINC4 4 -#define PINC3 3 -#define PINC2 2 -#define PINC1 1 -#define PINC0 0 - -/* Port D Data Register - PORTD */ -#define PD7 7 -#define PD6 6 -#define PD5 5 -#define PD4 4 -#define PD3 3 -#define PD2 2 -#define PD1 1 -#define PD0 0 - -/* Port D Data Direction Register - DDRD */ -#define DDD7 7 -#define DDD6 6 -#define DDD5 5 -#define DDD4 4 -#define DDD3 3 -#define DDD2 2 -#define DDD1 1 -#define DDD0 0 - -/* Port D Input Pins - PIND */ -#define PIND7 7 -#define PIND6 6 -#define PIND5 5 -#define PIND4 4 -#define PIND3 3 -#define PIND2 2 -#define PIND1 1 -#define PIND0 0 - -/* Port E Data Register - PORTE */ -#define PE7 7 -#define PE6 6 -#define PE5 5 -#define PE4 4 -#define PE3 3 -#define PE2 2 -#define PE1 1 -#define PE0 0 - -/* Port E Data Direction Register - DDRE */ -#define DDE7 7 -#define DDE6 6 -#define DDE5 5 -#define DDE4 4 -#define DDE3 3 -#define DDE2 2 -#define DDE1 1 -#define DDE0 0 - -/* Port E Input Pins - PINE */ -#define PINE7 7 -#define PINE6 6 -#define PINE5 5 -#define PINE4 4 -#define PINE3 3 -#define PINE2 2 -#define PINE1 1 -#define PINE0 0 - -/* Port F Data Register - PORTF */ -#define PF7 7 -#define PF6 6 -#define PF5 5 -#define PF4 4 -#define PF3 3 -#define PF2 2 -#define PF1 1 -#define PF0 0 - -/* Port F Data Direction Register - DDRF */ -#define DDF7 7 -#define DDF6 6 -#define DDF5 5 -#define DDF4 4 -#define DDF3 3 -#define DDF2 2 -#define DDF1 1 -#define DDF0 0 - -/* Port F Input Pins - PINF */ -#define PINF7 7 -#define PINF6 6 -#define PINF5 5 -#define PINF4 4 -#define PINF3 3 -#define PINF2 2 -#define PINF1 1 -#define PINF0 0 - -/* Port G Data Register - PORTG */ -#define PG4 4 -#define PG3 3 -#define PG2 2 -#define PG1 1 -#define PG0 0 - -/* Port G Data Direction Register - DDRG */ -#define DDG4 4 -#define DDG3 3 -#define DDG2 2 -#define DDG1 1 -#define DDG0 0 - -/* Port G Input Pins - PING */ -#define PING4 4 -#define PING3 3 -#define PING2 2 -#define PING1 1 -#define PING0 0 - -/* EEPROM Control Register */ -#define EERIE 3 -#define EEMWE 2 -#define EEWE 1 -#define EERE 0 - -/* Constants */ -#define SPM_PAGESIZE 256 -#define RAMSTART 0x100 -#define RAMEND 0x10FF /* Last On-Chip SRAM Location */ -#define XRAMEND 0xFFFF -#define E2END 0x07FF -#define E2PAGESIZE 8 -#define FLASHEND 0xFFFF - - -/* Fuses */ - -#define FUSE_MEMORY_SIZE 3 - -/* Low Fuse Byte */ -#define FUSE_CKSEL0 (unsigned char)~_BV(0) -#define FUSE_CKSEL1 (unsigned char)~_BV(1) -#define FUSE_CKSEL2 (unsigned char)~_BV(2) -#define FUSE_CKSEL3 (unsigned char)~_BV(3) -#define FUSE_SUT0 (unsigned char)~_BV(4) -#define FUSE_SUT1 (unsigned char)~_BV(5) -#define FUSE_BODEN (unsigned char)~_BV(6) -#define FUSE_BODLEVEL (unsigned char)~_BV(7) -#define LFUSE_DEFAULT (FUSE_CKSEL1 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0) - -/* High Fuse Byte */ -#define FUSE_BOOTRST (unsigned char)~_BV(0) -#define FUSE_BOOTSZ0 (unsigned char)~_BV(1) -#define FUSE_BOOTSZ1 (unsigned char)~_BV(2) -#define FUSE_EESAVE (unsigned char)~_BV(3) -#define FUSE_CKOPT (unsigned char)~_BV(4) -#define FUSE_SPIEN (unsigned char)~_BV(5) -#define FUSE_JTAGEN (unsigned char)~_BV(6) -#define FUSE_OCDEN (unsigned char)~_BV(7) -#define HFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_SPIEN & FUSE_JTAGEN) - -/* Extended Fuse Byte */ -#define FUSE_WDTON (unsigned char)~_BV(0) -#define FUSE_M103C (unsigned char)~_BV(1) -#define EFUSE_DEFAULT (FUSE_M103C) - - -/* Lock Bits */ -#define __LOCK_BITS_EXIST -#define __BOOT_LOCK_BITS_0_EXIST -#define __BOOT_LOCK_BITS_1_EXIST - - -/* Signature */ -#define SIGNATURE_0 0x1E -#define SIGNATURE_1 0x96 -#define SIGNATURE_2 0x02 - - -/* Deprecated items */ -#if !defined(__AVR_LIBC_DEPRECATED_ENABLE__) - -#pragma GCC system_header - -#pragma GCC poison SIG_INTERRUPT0 -#pragma GCC poison SIG_INTERRUPT1 -#pragma GCC poison SIG_INTERRUPT2 -#pragma GCC poison SIG_INTERRUPT3 -#pragma GCC poison SIG_INTERRUPT4 -#pragma GCC poison SIG_INTERRUPT5 -#pragma GCC poison SIG_INTERRUPT6 -#pragma GCC poison SIG_INTERRUPT7 -#pragma GCC poison SIG_OUTPUT_COMPARE2 -#pragma GCC poison SIG_OVERFLOW2 -#pragma GCC poison SIG_INPUT_CAPTURE1 -#pragma GCC poison SIG_OUTPUT_COMPARE1A -#pragma GCC poison SIG_OUTPUT_COMPARE1B -#pragma GCC poison SIG_OVERFLOW1 -#pragma GCC poison SIG_OUTPUT_COMPARE0 -#pragma GCC poison SIG_OVERFLOW0 -#pragma GCC poison SIG_SPI -#pragma GCC poison SIG_UART0_RECV -#pragma GCC poison SIG_UART0_DATA -#pragma GCC poison SIG_UART0_TRANS -#pragma GCC poison SIG_ADC -#pragma GCC poison SIG_EEPROM_READY -#pragma GCC poison SIG_COMPARATOR -#pragma GCC poison SIG_OUTPUT_COMPARE1C -#pragma GCC poison SIG_INPUT_CAPTURE3 -#pragma GCC poison SIG_OUTPUT_COMPARE3A -#pragma GCC poison SIG_OUTPUT_COMPARE3B -#pragma GCC poison SIG_OUTPUT_COMPARE3C -#pragma GCC poison SIG_OVERFLOW3 -#pragma GCC poison SIG_UART1_RECV -#pragma GCC poison SIG_UART1_DATA -#pragma GCC poison SIG_UART1_TRANS -#pragma GCC poison SIG_2WIRE_SERIAL -#pragma GCC poison SIG_SPM_READY - -#endif /* !defined(__AVR_LIBC_DEPRECATED_ENABLE__) */ - -#define SLEEP_MODE_IDLE (0x00<<2) -#define SLEEP_MODE_ADC (0x02<<2) -#define SLEEP_MODE_PWR_DOWN (0x04<<2) -#define SLEEP_MODE_PWR_SAVE (0x06<<2) -#define SLEEP_MODE_STANDBY (0x05<<2) -#define SLEEP_MODE_EXT_STANDBY (0x07<<2) - -#endif /* _AVR_IOM64_H_ */ diff --git a/arduino/hardware/tools/avr/avr/include/avr/iom640.h b/arduino/hardware/tools/avr/avr/include/avr/iom640.h deleted file mode 100644 index 92574e8..0000000 --- a/arduino/hardware/tools/avr/avr/include/avr/iom640.h +++ /dev/null @@ -1,101 +0,0 @@ -/* Copyright (c) 2005 Anatoly Sokolov - All rights reserved. - - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - * Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - * Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in - the documentation and/or other materials provided with the - distribution. - - * Neither the name of the copyright holders nor the names of - contributors may be used to endorse or promote products derived - from this software without specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. */ - -/* $Id: iom640.h 2102 2010-03-16 22:52:39Z joerg_wunsch $ */ - -/* avr/iom640.h - definitions for ATmega640 */ - -#ifndef _AVR_IOM640_H_ -#define _AVR_IOM640_H_ 1 - -#include - -/* Constants */ -#define SPM_PAGESIZE 256 -#define RAMSTART 0x200 -#define RAMEND 0x21FF -#define XRAMEND 0xFFFF -#define E2END 0xFFF -#define E2PAGESIZE 8 -#define FLASHEND 0xFFFF - - -/* Fuses */ - -#define FUSE_MEMORY_SIZE 3 - -/* Low Fuse Byte */ -#define FUSE_CKSEL0 (unsigned char)~_BV(0) -#define FUSE_CKSEL1 (unsigned char)~_BV(1) -#define FUSE_CKSEL2 (unsigned char)~_BV(2) -#define FUSE_CKSEL3 (unsigned char)~_BV(3) -#define FUSE_SUT0 (unsigned char)~_BV(4) -#define FUSE_SUT1 (unsigned char)~_BV(5) -#define FUSE_CKOUT (unsigned char)~_BV(6) -#define FUSE_CKDIV8 (unsigned char)~_BV(7) -#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8) - -/* High Fuse Byte */ -#define FUSE_BOOTRST (unsigned char)~_BV(0) -#define FUSE_BOOTSZ0 (unsigned char)~_BV(1) -#define FUSE_BOOTSZ1 (unsigned char)~_BV(2) -#define FUSE_EESAVE (unsigned char)~_BV(3) -#define FUSE_WDTON (unsigned char)~_BV(4) -#define FUSE_SPIEN (unsigned char)~_BV(5) -#define FUSE_JTAGEN (unsigned char)~_BV(6) -#define FUSE_OCDEN (unsigned char)~_BV(7) -#define HFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_SPIEN & FUSE_JTAGEN) - -/* Extended Fuse Byte */ -#define FUSE_BODLEVEL0 (unsigned char)~_BV(0) -#define FUSE_BODLEVEL1 (unsigned char)~_BV(1) -#define FUSE_BODLEVEL2 (unsigned char)~_BV(2) -#define EFUSE_DEFAULT (0xFF) - - -/* Lock Bits */ -#define __LOCK_BITS_EXIST -#define __BOOT_LOCK_BITS_0_EXIST -#define __BOOT_LOCK_BITS_1_EXIST - - -/* Signature */ -#define SIGNATURE_0 0x1E -#define SIGNATURE_1 0x96 -#define SIGNATURE_2 0x08 - -#define SLEEP_MODE_IDLE (0x00<<1) -#define SLEEP_MODE_ADC (0x01<<1) -#define SLEEP_MODE_PWR_DOWN (0x02<<1) -#define SLEEP_MODE_PWR_SAVE (0x03<<1) -#define SLEEP_MODE_STANDBY (0x06<<1) -#define SLEEP_MODE_EXT_STANDBY (0x07<<1) - -#endif /* _AVR_IOM640_H_ */ diff --git a/arduino/hardware/tools/avr/avr/include/avr/iom644.h b/arduino/hardware/tools/avr/avr/include/avr/iom644.h deleted file mode 100644 index c8dba84..0000000 --- a/arduino/hardware/tools/avr/avr/include/avr/iom644.h +++ /dev/null @@ -1,101 +0,0 @@ -/* Copyright (c) 2005 Anatoly Sokolov - All rights reserved. - - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - * Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - * Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in - the documentation and/or other materials provided with the - distribution. - - * Neither the name of the copyright holders nor the names of - contributors may be used to endorse or promote products derived - from this software without specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. */ - -/* avr/iom644.h - definitions for ATmega644 */ - -/* $Id: iom644.h 2115 2010-04-05 23:19:53Z arcanum $ */ - -#ifndef _AVR_IOM644_H_ -#define _AVR_IOM644_H_ 1 - -#include - -/* Constants */ -#define SPM_PAGESIZE 256 -#define RAMSTART (0x100) -#define RAMEND 0x10FF -#define XRAMEND RAMEND -#define E2END 0x7FF -#define E2PAGESIZE 8 -#define FLASHEND 0xFFFF - - -/* Fuses */ - -#define FUSE_MEMORY_SIZE 3 - -/* Low Fuse Byte */ -#define FUSE_CKSEL0 (unsigned char)~_BV(0) -#define FUSE_CKSEL1 (unsigned char)~_BV(1) -#define FUSE_CKSEL2 (unsigned char)~_BV(2) -#define FUSE_CKSEL3 (unsigned char)~_BV(3) -#define FUSE_SUT0 (unsigned char)~_BV(4) -#define FUSE_SUT1 (unsigned char)~_BV(5) -#define FUSE_CKOUT (unsigned char)~_BV(6) -#define FUSE_CKDIV8 (unsigned char)~_BV(7) -#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_SUT1 & FUSE_CKDIV8) - -/* High Fuse Byte */ -#define FUSE_BOOTRST (unsigned char)~_BV(0) -#define FUSE_BOOTSZ0 (unsigned char)~_BV(1) -#define FUSE_BOOTSZ1 (unsigned char)~_BV(2) -#define FUSE_EESAVE (unsigned char)~_BV(3) -#define FUSE_WDTON (unsigned char)~_BV(4) -#define FUSE_SPIEN (unsigned char)~_BV(5) -#define FUSE_JTAGEN (unsigned char)~_BV(6) -#define FUSE_OCDEN (unsigned char)~_BV(7) -#define HFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_SPIEN & FUSE_JTAGEN) - -/* Extended Fuse Byte */ -#define FUSE_BODLEVEL0 (unsigned char)~_BV(0) -#define FUSE_BODLEVEL1 (unsigned char)~_BV(1) -#define FUSE_BODLEVEL2 (unsigned char)~_BV(2) -#define EFUSE_DEFAULT (0xFF) - - -/* Lock Bits */ -#define __LOCK_BITS_EXIST -#define __BOOT_LOCK_BITS_0_EXIST -#define __BOOT_LOCK_BITS_1_EXIST - - -/* Signature */ -#define SIGNATURE_0 0x1E -#define SIGNATURE_1 0x96 -#define SIGNATURE_2 0x09 - -#define SLEEP_MODE_IDLE (0x00<<1) -#define SLEEP_MODE_ADC (0x01<<1) -#define SLEEP_MODE_PWR_DOWN (0x02<<1) -#define SLEEP_MODE_PWR_SAVE (0x03<<1) -#define SLEEP_MODE_STANDBY (0x06<<1) -#define SLEEP_MODE_EXT_STANDBY (0x07<<1) - -#endif /* _AVR_IOM644_H_ */ diff --git a/arduino/hardware/tools/avr/avr/include/avr/iom644a.h b/arduino/hardware/tools/avr/avr/include/avr/iom644a.h deleted file mode 100644 index 49d4e3b..0000000 --- a/arduino/hardware/tools/avr/avr/include/avr/iom644a.h +++ /dev/null @@ -1,34 +0,0 @@ -/***************************************************************************** - * - * Copyright (C) 2011 Atmel Corporation - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * - * * Neither the name of the copyright holders nor the names of - * contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - ****************************************************************************/ - -#include "iom644.h" diff --git a/arduino/hardware/tools/avr/avr/include/avr/iom644p.h b/arduino/hardware/tools/avr/avr/include/avr/iom644p.h deleted file mode 100644 index e0e6094..0000000 --- a/arduino/hardware/tools/avr/avr/include/avr/iom644p.h +++ /dev/null @@ -1,101 +0,0 @@ -/* Copyright (c) 2005 Anatoly Sokolov - All rights reserved. - - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - * Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - * Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in - the documentation and/or other materials provided with the - distribution. - - * Neither the name of the copyright holders nor the names of - contributors may be used to endorse or promote products derived - from this software without specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. */ - -/* avr/iom644p.h - definitions for ATmega644P */ - -/* $Id: iom644p.h 2115 2010-04-05 23:19:53Z arcanum $ */ - -#ifndef _AVR_IOM644P_H_ -#define _AVR_IOM644P_H_ 1 - -#include - -/* Constants */ -#define SPM_PAGESIZE 256 -#define RAMSTART (0x100) -#define RAMEND 0x10FF -#define XRAMEND RAMEND -#define E2END 0x7FF -#define E2PAGESIZE 8 -#define FLASHEND 0xFFFF - - -/* Fuses */ - -#define FUSE_MEMORY_SIZE 3 - -/* Low Fuse Byte */ -#define FUSE_CKSEL0 (unsigned char)~_BV(0) -#define FUSE_CKSEL1 (unsigned char)~_BV(1) -#define FUSE_CKSEL2 (unsigned char)~_BV(2) -#define FUSE_CKSEL3 (unsigned char)~_BV(3) -#define FUSE_SUT0 (unsigned char)~_BV(4) -#define FUSE_SUT1 (unsigned char)~_BV(5) -#define FUSE_CKOUT (unsigned char)~_BV(6) -#define FUSE_CKDIV8 (unsigned char)~_BV(7) -#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_SUT1 & FUSE_CKDIV8) - -/* High Fuse Byte */ -#define FUSE_BOOTRST (unsigned char)~_BV(0) -#define FUSE_BOOTSZ0 (unsigned char)~_BV(1) -#define FUSE_BOOTSZ1 (unsigned char)~_BV(2) -#define FUSE_EESAVE (unsigned char)~_BV(3) -#define FUSE_WDTON (unsigned char)~_BV(4) -#define FUSE_SPIEN (unsigned char)~_BV(5) -#define FUSE_JTAGEN (unsigned char)~_BV(6) -#define FUSE_OCDEN (unsigned char)~_BV(7) -#define HFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_SPIEN & FUSE_JTAGEN) - -/* Extended Fuse Byte */ -#define FUSE_BODLEVEL0 (unsigned char)~_BV(0) -#define FUSE_BODLEVEL1 (unsigned char)~_BV(1) -#define FUSE_BODLEVEL2 (unsigned char)~_BV(2) -#define EFUSE_DEFAULT (0xFF) - - -/* Lock Bits */ -#define __LOCK_BITS_EXIST -#define __BOOT_LOCK_BITS_0_EXIST -#define __BOOT_LOCK_BITS_1_EXIST - - -/* Signature */ -#define SIGNATURE_0 0x1E -#define SIGNATURE_1 0x96 -#define SIGNATURE_2 0x0A - -#define SLEEP_MODE_IDLE (0x00<<1) -#define SLEEP_MODE_ADC (0x01<<1) -#define SLEEP_MODE_PWR_DOWN (0x02<<1) -#define SLEEP_MODE_PWR_SAVE (0x03<<1) -#define SLEEP_MODE_STANDBY (0x06<<1) -#define SLEEP_MODE_EXT_STANDBY (0x07<<1) - -#endif /* _AVR_IOM644P_H_ */ diff --git a/arduino/hardware/tools/avr/avr/include/avr/iom644pa.h b/arduino/hardware/tools/avr/avr/include/avr/iom644pa.h deleted file mode 100644 index 5c3f3a8..0000000 --- a/arduino/hardware/tools/avr/avr/include/avr/iom644pa.h +++ /dev/null @@ -1,1387 +0,0 @@ -/* Copyright (c) 2009 Atmel Corporation - All rights reserved. - - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - * Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - * Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in - the documentation and/or other materials provided with the - distribution. - - * Neither the name of the copyright holders nor the names of - contributors may be used to endorse or promote products derived - from this software without specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. */ - -/* $Id: iom644pa.h 2035 2009-11-02 02:44:17Z arcanum $ */ - -/* avr/iom644PA.h - definitions for ATmega644PA */ - -/* This file should only be included from , never directly. */ - -#ifndef _AVR_IO_H_ -# error "Include instead of this file." -#endif - -#ifndef _AVR_IOXXX_H_ -# define _AVR_IOXXX_H_ "iom644PA.h" -#else -# error "Attempt to include more than one file." -#endif - - -#ifndef _AVR_ATmega644PA_H_ -#define _AVR_ATmega644PA_H_ 1 - - -/* Registers and associated bit numbers. */ - -#define PINA _SFR_IO8(0x00) -#define PINA0 0 -#define PINA1 1 -#define PINA2 2 -#define PINA3 3 -#define PINA4 4 -#define PINA5 5 -#define PINA6 6 -#define PINA7 7 - -#define DDRA _SFR_IO8(0x01) -#define DDA0 0 -#define DDA1 1 -#define DDA2 2 -#define DDA3 3 -#define DDA4 4 -#define DDA5 5 -#define DDA6 6 -#define DDA7 7 - -#define PORTA _SFR_IO8(0x02) -#define PORTA0 0 -#define PORTA1 1 -#define PORTA2 2 -#define PORTA3 3 -#define PORTA4 4 -#define PORTA5 5 -#define PORTA6 6 -#define PORTA7 7 - -#define PINB _SFR_IO8(0x03) -#define PINB0 0 -#define PINB1 1 -#define PINB2 2 -#define PINB3 3 -#define PINB4 4 -#define PINB5 5 -#define PINB6 6 -#define PINB7 7 - -#define DDRB _SFR_IO8(0x04) -#define DDB0 0 -#define DDB1 1 -#define DDB2 2 -#define DDB3 3 -#define DDB4 4 -#define DDB5 5 -#define DDB6 6 -#define DDB7 7 - -#define PORTB _SFR_IO8(0x05) -#define PORTB0 0 -#define PORTB1 1 -#define PORTB2 2 -#define PORTB3 3 -#define PORTB4 4 -#define PORTB5 5 -#define PORTB6 6 -#define PORTB7 7 - -#define PINC _SFR_IO8(0x06) -#define PINC0 0 -#define PINC1 1 -#define PINC2 2 -#define PINC3 3 -#define PINC4 4 -#define PINC5 5 -#define PINC6 6 -#define PINC7 7 - -#define DDRC _SFR_IO8(0x07) -#define DDC0 0 -#define DDC1 1 -#define DDC2 2 -#define DDC3 3 -#define DDC4 4 -#define DDC5 5 -#define DDC6 6 -#define DDC7 7 - -#define PORTC _SFR_IO8(0x08) -#define PORTC0 0 -#define PORTC1 1 -#define PORTC2 2 -#define PORTC3 3 -#define PORTC4 4 -#define PORTC5 5 -#define PORTC6 6 -#define PORTC7 7 - -#define PIND _SFR_IO8(0x09) -#define PIND0 0 -#define PIND1 1 -#define PIND2 2 -#define PIND3 3 -#define PIND4 4 -#define PIND5 5 -#define PIND6 6 -#define PIND7 7 - -#define DDRD _SFR_IO8(0x0A) -#define DDD0 0 -#define DDD1 1 -#define DDD2 2 -#define DDD3 3 -#define DDD4 4 -#define DDD5 5 -#define DDD6 6 -#define DDD7 7 - -#define PORTD _SFR_IO8(0x0B) -#define PORTD0 0 -#define PORTD1 1 -#define PORTD2 2 -#define PORTD3 3 -#define PORTD4 4 -#define PORTD5 5 -#define PORTD6 6 -#define PORTD7 7 - -#define TIFR0 _SFR_IO8(0x15) -#define TOV0 0 -#define OCF0A 1 -#define OCF0B 2 - -#define TIFR1 _SFR_IO8(0x16) -#define TOV1 0 -#define OCF1A 1 -#define OCF1B 2 -#define ICF1 5 - -#define TIFR2 _SFR_IO8(0x17) -#define TOV2 0 -#define OCF2A 1 -#define OCF2B 2 - -#define PCIFR _SFR_IO8(0x1B) -#define PCIF0 0 -#define PCIF1 1 -#define PCIF2 2 -#define PCIF3 3 - -#define EIFR _SFR_IO8(0x1C) -#define INTF0 0 -#define INTF1 1 -#define INTF2 2 - -#define EIMSK _SFR_IO8(0x1D) -#define INT0 0 -#define INT1 1 -#define INT2 2 - -#define GPIOR0 _SFR_IO8(0x1E) -#define GPIOR00 0 -#define GPIOR01 1 -#define GPIOR02 2 -#define GPIOR03 3 -#define GPIOR04 4 -#define GPIOR05 5 -#define GPIOR06 6 -#define GPIOR07 7 - -#define EECR _SFR_IO8(0x1F) -#define EERE 0 -#define EEPE 1 -#define EEMPE 2 -#define EERIE 3 -#define EEPM0 4 -#define EEPM1 5 - -#define EEDR _SFR_IO8(0x20) -#define EEDR0 0 -#define EEDR1 1 -#define EEDR2 2 -#define EEDR3 3 -#define EEDR4 4 -#define EEDR5 5 -#define EEDR6 6 -#define EEDR7 7 - -#define EEAR _SFR_IO16(0x21) - -#define EEARL _SFR_IO8(0x21) -#define EEAR0 0 -#define EEAR1 1 -#define EEAR2 2 -#define EEAR3 3 -#define EEAR4 4 -#define EEAR5 5 -#define EEAR6 6 -#define EEAR7 7 - -#define EEARH _SFR_IO8(0x22) -#define EEAR8 0 -#define EEAR9 1 -#define EEAR10 2 -#define EEAR11 3 - -#define GTCCR _SFR_IO8(0x23) -#define PSRSYNC 0 -#define PSRASY 1 -#define TSM 7 - -#define TCCR0A _SFR_IO8(0x24) -#define WGM00 0 -#define WGM01 1 -#define COM0B0 4 -#define COM0B1 5 -#define COM0A0 6 -#define COM0A1 7 - -#define TCCR0B _SFR_IO8(0x25) -#define CS00 0 -#define CS01 1 -#define CS02 2 -#define WGM02 3 -#define FOC0B 6 -#define FOC0A 7 - -#define TCNT0 _SFR_IO8(0x26) -#define TCNT0_0 0 -#define TCNT0_1 1 -#define TCNT0_2 2 -#define TCNT0_3 3 -#define TCNT0_4 4 -#define TCNT0_5 5 -#define TCNT0_6 6 -#define TCNT0_7 7 - -#define OCR0A _SFR_IO8(0x27) -#define OCR0A_0 0 -#define OCR0A_1 1 -#define OCR0A_2 2 -#define OCR0A_3 3 -#define OCR0A_4 4 -#define OCR0A_5 5 -#define OCR0A_6 6 -#define OCR0A_7 7 - -#define OCR0B _SFR_IO8(0x28) -#define OCR0B_0 0 -#define OCR0B_1 1 -#define OCR0B_2 2 -#define OCR0B_3 3 -#define OCR0B_4 4 -#define OCR0B_5 5 -#define OCR0B_6 6 -#define OCR0B_7 7 - -#define GPIOR1 _SFR_IO8(0x2A) -#define GPIOR10 0 -#define GPIOR11 1 -#define GPIOR12 2 -#define GPIOR13 3 -#define GPIOR14 4 -#define GPIOR15 5 -#define GPIOR16 6 -#define GPIOR17 7 - -#define GPIOR2 _SFR_IO8(0x2B) -#define GPIOR20 0 -#define GPIOR21 1 -#define GPIOR22 2 -#define GPIOR23 3 -#define GPIOR24 4 -#define GPIOR25 5 -#define GPIOR26 6 -#define GPIOR27 7 - -#define SPCR _SFR_IO8(0x2C) -#define SPR0 0 -#define SPR1 1 -#define CPHA 2 -#define CPOL 3 -#define MSTR 4 -#define DORD 5 -#define SPE 6 -#define SPIE 7 - -#define SPSR _SFR_IO8(0x2D) -#define SPI2X 0 -#define WCOL 6 -#define SPIF 7 - -#define SPDR _SFR_IO8(0x2E) -#define SPDR0 0 -#define SPDR1 1 -#define SPDR2 2 -#define SPDR3 3 -#define SPDR4 4 -#define SPDR5 5 -#define SPDR6 6 -#define SPDR7 7 - -#define ACSR _SFR_IO8(0x30) -#define ACIS0 0 -#define ACIS1 1 -#define ACIC 2 -#define ACIE 3 -#define ACI 4 -#define ACO 5 -#define ACBG 6 -#define ACD 7 - -#define OCDR _SFR_IO8(0x31) -#define OCDR0 0 -#define OCDR1 1 -#define OCDR2 2 -#define OCDR3 3 -#define OCDR4 4 -#define OCDR5 5 -#define OCDR6 6 -#define OCDR7 7 - -#define SMCR _SFR_IO8(0x33) -#define SE 0 -#define SM0 1 -#define SM1 2 -#define SM2 3 - -#define MCUSR _SFR_IO8(0x34) -#define PORF 0 -#define EXTRF 1 -#define BORF 2 -#define WDRF 3 -#define JTRF 4 - -#define MCUCR _SFR_IO8(0x35) -#define IVCE 0 -#define IVSEL 1 -#define PUD 4 -#define BODSE 5 -#define BODS 6 -#define JTD 7 - -#define SPMCSR _SFR_IO8(0x37) -#define SPMEN 0 -#define PGERS 1 -#define PGWRT 2 -#define BLBSET 3 -#define RWWSRE 4 -#define SIGRD 5 -#define RWWSB 6 -#define SPMIE 7 - -#define WDTCSR _SFR_MEM8(0x60) -#define WDP0 0 -#define WDP1 1 -#define WDP2 2 -#define WDE 3 -#define WDCE 4 -#define WDP3 5 -#define WDIE 6 -#define WDIF 7 - -#define CLKPR _SFR_MEM8(0x61) -#define CLKPS0 0 -#define CLKPS1 1 -#define CLKPS2 2 -#define CLKPS3 3 -#define CLKPCE 7 - -#define PRR0 _SFR_MEM8(0x64) -#define PRADC 0 -#define PRUSART0 1 -#define PRSPI 2 -#define PRTIM1 3 -#define PRUSART1 4 -#define PRTIM0 5 -#define PRTIM2 6 -#define PRTWI 7 - -#define __AVR_HAVE_PRR0 ((1< instead of this file." -#endif - -#ifndef _AVR_IOXXX_H_ -# define _AVR_IOXXX_H_ "iom644rfr2.h" -#else -# error "Attempt to include more than one file." -#endif - -/* Registers and associated bit numbers */ - -#define PINA _SFR_IO8(0x00) -#define PINA7 7 -#define PINA6 6 -#define PINA5 5 -#define PINA4 4 -#define PINA3 3 -#define PINA2 2 -#define PINA1 1 -#define PINA0 0 - -#define DDRA _SFR_IO8(0x01) -#define DDRA7 7 -// Inserted "DDA7" from "DDRA7" due to compatibility -#define DDA7 7 -#define DDRA6 6 -// Inserted "DDA6" from "DDRA6" due to compatibility -#define DDA6 6 -#define DDRA5 5 -// Inserted "DDA5" from "DDRA5" due to compatibility -#define DDA5 5 -#define DDRA4 4 -// Inserted "DDA4" from "DDRA4" due to compatibility -#define DDA4 4 -#define DDRA3 3 -// Inserted "DDA3" from "DDRA3" due to compatibility -#define DDA3 3 -#define DDRA2 2 -// Inserted "DDA2" from "DDRA2" due to compatibility -#define DDA2 2 -#define DDRA1 1 -// Inserted "DDA1" from "DDRA1" due to compatibility -#define DDA1 1 -#define DDRA0 0 -// Inserted "DDA0" from "DDRA0" due to compatibility -#define DDA0 0 - -#define PORTA _SFR_IO8(0x02) -#define PORTA7 7 -#define PORTA6 6 -#define PORTA5 5 -#define PORTA4 4 -#define PORTA3 3 -#define PORTA2 2 -#define PORTA1 1 -#define PORTA0 0 - -#define PINB _SFR_IO8(0x03) -#define PINB7 7 -#define PINB6 6 -#define PINB5 5 -#define PINB4 4 -#define PINB3 3 -#define PINB2 2 -#define PINB1 1 -#define PINB0 0 - -#define DDRB _SFR_IO8(0x04) -#define DDRB7 7 -// Inserted "DDB7" from "DDRB7" due to compatibility -#define DDB7 7 -#define DDRB6 6 -// Inserted "DDB6" from "DDRB6" due to compatibility -#define DDB6 6 -#define DDRB5 5 -// Inserted "DDB5" from "DDRB5" due to compatibility -#define DDB5 5 -#define DDRB4 4 -// Inserted "DDB4" from "DDRB4" due to compatibility -#define DDB4 4 -#define DDRB3 3 -// Inserted "DDB3" from "DDRB3" due to compatibility -#define DDB3 3 -#define DDRB2 2 -// Inserted "DDB2" from "DDRB2" due to compatibility -#define DDB2 2 -#define DDRB1 1 -// Inserted "DDB1" from "DDRB1" due to compatibility -#define DDB1 1 -#define DDRB0 0 -// Inserted "DDB0" from "DDRB0" due to compatibility -#define DDB0 0 - -#define PORTB _SFR_IO8(0x05) -#define PORTB7 7 -#define PORTB6 6 -#define PORTB5 5 -#define PORTB4 4 -#define PORTB3 3 -#define PORTB2 2 -#define PORTB1 1 -#define PORTB0 0 - -#define PINC _SFR_IO8(0x06) -#define PINC7 7 -#define PINC6 6 -#define PINC5 5 -#define PINC4 4 -#define PINC3 3 -#define PINC2 2 -#define PINC1 1 -#define PINC0 0 - -#define DDRC _SFR_IO8(0x07) -#define DDRC7 7 -// Inserted "DDC7" from "DDRC7" due to compatibility -#define DDC7 7 -#define DDRC6 6 -// Inserted "DDC6" from "DDRC6" due to compatibility -#define DDC6 6 -#define DDRC5 5 -// Inserted "DDC5" from "DDRC5" due to compatibility -#define DDC5 5 -#define DDRC4 4 -// Inserted "DDC4" from "DDRC4" due to compatibility -#define DDC4 4 -#define DDRC3 3 -// Inserted "DDC3" from "DDRC3" due to compatibility -#define DDC3 3 -#define DDRC2 2 -// Inserted "DDC2" from "DDRC2" due to compatibility -#define DDC2 2 -#define DDRC1 1 -// Inserted "DDC1" from "DDRC1" due to compatibility -#define DDC1 1 -#define DDRC0 0 -// Inserted "DDC0" from "DDRC0" due to compatibility -#define DDC0 0 - -#define PORTC _SFR_IO8(0x08) -#define PORTC7 7 -#define PORTC6 6 -#define PORTC5 5 -#define PORTC4 4 -#define PORTC3 3 -#define PORTC2 2 -#define PORTC1 1 -#define PORTC0 0 - -#define PIND _SFR_IO8(0x09) -#define PIND7 7 -#define PIND6 6 -#define PIND5 5 -#define PIND4 4 -#define PIND3 3 -#define PIND2 2 -#define PIND1 1 -#define PIND0 0 - -#define DDRD _SFR_IO8(0x0A) -#define DDRD7 7 -// Inserted "DDD7" from "DDRD7" due to compatibility -#define DDD7 7 -#define DDRD6 6 -// Inserted "DDD6" from "DDRD6" due to compatibility -#define DDD6 6 -#define DDRD5 5 -// Inserted "DDD5" from "DDRD5" due to compatibility -#define DDD5 5 -#define DDRD4 4 -// Inserted "DDD4" from "DDRD4" due to compatibility -#define DDD4 4 -#define DDRD3 3 -// Inserted "DDD3" from "DDRD3" due to compatibility -#define DDD3 3 -#define DDRD2 2 -// Inserted "DDD2" from "DDRD2" due to compatibility -#define DDD2 2 -#define DDRD1 1 -// Inserted "DDD1" from "DDRD1" due to compatibility -#define DDD1 1 -#define DDRD0 0 -// Inserted "DDD0" from "DDRD0" due to compatibility -#define DDD0 0 - -#define PORTD _SFR_IO8(0x0B) -#define PORTD7 7 -#define PORTD6 6 -#define PORTD5 5 -#define PORTD4 4 -#define PORTD3 3 -#define PORTD2 2 -#define PORTD1 1 -#define PORTD0 0 - -#define PINE _SFR_IO8(0x0C) -#define PINE7 7 -#define PINE6 6 -#define PINE5 5 -#define PINE4 4 -#define PINE3 3 -#define PINE2 2 -#define PINE1 1 -#define PINE0 0 - -#define DDRE _SFR_IO8(0x0D) -#define DDRE7 7 -// Inserted "DDE7" from "DDRE7" due to compatibility -#define DDE7 7 -#define DDRE6 6 -// Inserted "DDE6" from "DDRE6" due to compatibility -#define DDE6 6 -#define DDRE5 5 -// Inserted "DDE5" from "DDRE5" due to compatibility -#define DDE5 5 -#define DDRE4 4 -// Inserted "DDE4" from "DDRE4" due to compatibility -#define DDE4 4 -#define DDRE3 3 -// Inserted "DDE3" from "DDRE3" due to compatibility -#define DDE3 3 -#define DDRE2 2 -// Inserted "DDE2" from "DDRE2" due to compatibility -#define DDE2 2 -#define DDRE1 1 -// Inserted "DDE1" from "DDRE1" due to compatibility -#define DDE1 1 -#define DDRE0 0 -// Inserted "DDE0" from "DDRE0" due to compatibility -#define DDE0 0 - -#define PORTE _SFR_IO8(0x0E) -#define PORTE7 7 -#define PORTE6 6 -#define PORTE5 5 -#define PORTE4 4 -#define PORTE3 3 -#define PORTE2 2 -#define PORTE1 1 -#define PORTE0 0 - -#define PINF _SFR_IO8(0x0F) -#define PINF7 7 -#define PINF6 6 -#define PINF5 5 -#define PINF4 4 -#define PINF3 3 -#define PINF2 2 -#define PINF1 1 -#define PINF0 0 - -#define DDRF _SFR_IO8(0x10) -#define DDRF7 7 -// Inserted "DDF7" from "DDRF7" due to compatibility -#define DDF7 7 -#define DDRF6 6 -// Inserted "DDF6" from "DDRF6" due to compatibility -#define DDF6 6 -#define DDRF5 5 -// Inserted "DDF5" from "DDRF5" due to compatibility -#define DDF5 5 -#define DDRF4 4 -// Inserted "DDF4" from "DDRF4" due to compatibility -#define DDF4 4 -#define DDRF3 3 -// Inserted "DDF3" from "DDRF3" due to compatibility -#define DDF3 3 -#define DDRF2 2 -// Inserted "DDF2" from "DDRF2" due to compatibility -#define DDF2 2 -#define DDRF1 1 -// Inserted "DDF1" from "DDRF1" due to compatibility -#define DDF1 1 -#define DDRF0 0 -// Inserted "DDF0" from "DDRF0" due to compatibility -#define DDF0 0 - -#define PORTF _SFR_IO8(0x11) -#define PORTF7 7 -#define PORTF6 6 -#define PORTF5 5 -#define PORTF4 4 -#define PORTF3 3 -#define PORTF2 2 -#define PORTF1 1 -#define PORTF0 0 - -#define PING _SFR_IO8(0x12) -#define PING7 7 -#define PING6 6 -#define PING5 5 -#define PING4 4 -#define PING3 3 -#define PING2 2 -#define PING1 1 -#define PING0 0 - -#define DDRG _SFR_IO8(0x13) -#define DDRG7 7 -// Inserted "DDG7" from "DDRG7" due to compatibility -#define DDG7 7 -#define DDRG6 6 -// Inserted "DDG6" from "DDRG6" due to compatibility -#define DDG6 6 -#define DDRG5 5 -// Inserted "DDG5" from "DDRG5" due to compatibility -#define DDG5 5 -#define DDRG4 4 -// Inserted "DDG4" from "DDRG4" due to compatibility -#define DDG4 4 -#define DDRG3 3 -// Inserted "DDG3" from "DDRG3" due to compatibility -#define DDG3 3 -#define DDRG2 2 -// Inserted "DDG2" from "DDRG2" due to compatibility -#define DDG2 2 -#define DDRG1 1 -// Inserted "DDG1" from "DDRG1" due to compatibility -#define DDG1 1 -#define DDRG0 0 -// Inserted "DDG0" from "DDRG0" due to compatibility -#define DDG0 0 - -#define PORTG _SFR_IO8(0x14) -#define PORTG7 7 -#define PORTG6 6 -#define PORTG5 5 -#define PORTG4 4 -#define PORTG3 3 -#define PORTG2 2 -#define PORTG1 1 -#define PORTG0 0 - -#define TIFR0 _SFR_IO8(0x15) -#define TOV0 0 -#define OCF0A 1 -#define OCF0B 2 -#define Res0 3 -#define Res1 4 -#define Res2 5 -#define Res3 6 -#define Res4 7 - -#define TIFR1 _SFR_IO8(0x16) -#define TOV1 0 -#define OCF1A 1 -#define OCF1B 2 -#define OCF1C 3 -#define ICF1 5 - -#define TIFR2 _SFR_IO8(0x17) -#define TOV2 0 -#define OCF2A 1 -#define OCF2B 2 - -#define TIFR3 _SFR_IO8(0x18) -#define TOV3 0 -#define OCF3A 1 -#define OCF3B 2 -#define OCF3C 3 -#define ICF3 5 - -#define TIFR4 _SFR_IO8(0x19) -#define TOV4 0 -#define OCF4A 1 -#define OCF4B 2 -#define OCF4C 3 -#define ICF4 5 - -#define TIFR5 _SFR_IO8(0x1A) -#define TOV5 0 -#define OCF5A 1 -#define OCF5B 2 -#define OCF5C 3 -#define ICF5 5 - -#define PCIFR _SFR_IO8(0x1B) -#define PCIF0 0 -#define PCIF1 1 -#define PCIF2 2 - -#define EIFR _SFR_IO8(0x1C) -#define INTF0 0 -#define INTF1 1 -#define INTF2 2 -#define INTF3 3 -#define INTF4 4 -#define INTF5 5 -#define INTF6 6 -#define INTF7 7 - -#define EIMSK _SFR_IO8(0x1D) -#define INT0 0 -#define INT1 1 -#define INT2 2 -#define INT3 3 -#define INT4 4 -#define INT5 5 -#define INT6 6 -#define INT7 7 - -#define GPIOR0 _SFR_IO8(0x1E) -#define GPIOR00 0 -#define GPIOR01 1 -#define GPIOR02 2 -#define GPIOR03 3 -#define GPIOR04 4 -#define GPIOR05 5 -#define GPIOR06 6 -#define GPIOR07 7 - -#define EECR _SFR_IO8(0x1F) -#define EERE 0 -#define EEPE 1 -#define EEMPE 2 -#define EERIE 3 -#define EEPM0 4 -#define EEPM1 5 - -#define EEDR _SFR_IO8(0x20) - -/* Combine EEARL and EEARH */ -#define EEAR _SFR_IO16(0x21) - -#define EEARL _SFR_IO8(0x21) -#define EEARH _SFR_IO8(0x22) - -#define GTCCR _SFR_IO8(0x23) -#define PSRSYNC 0 -#define PSRASY 1 -#define TSM 7 - -#define TCCR0A _SFR_IO8(0x24) -#define WGM00 0 -#define WGM01 1 -#define COM0B0 4 -#define COM0B1 5 -#define COM0A0 6 -#define COM0A1 7 - -#define TCCR0B _SFR_IO8(0x25) -#define CS00 0 -#define CS01 1 -#define CS02 2 -#define WGM02 3 -#define FOC0B 6 -#define FOC0A 7 - -#define TCNT0 _SFR_IO8(0x26) - -#define OCR0A _SFR_IO8(0x27) - -#define OCR0B _SFR_IO8(0x28) - -/* Reserved [0x29] */ - -#define GPIOR1 _SFR_IO8(0x2A) -#define GPIOR10 0 -#define GPIOR11 1 -#define GPIOR12 2 -#define GPIOR13 3 -#define GPIOR14 4 -#define GPIOR15 5 -#define GPIOR16 6 -#define GPIOR17 7 - -#define GPIOR2 _SFR_IO8(0x2B) -#define GPIOR20 0 -#define GPIOR21 1 -#define GPIOR22 2 -#define GPIOR23 3 -#define GPIOR24 4 -#define GPIOR25 5 -#define GPIOR26 6 -#define GPIOR27 7 - -#define SPCR _SFR_IO8(0x2C) -#define SPR0 0 -#define SPR1 1 -#define CPHA 2 -#define CPOL 3 -#define MSTR 4 -#define DORD 5 -#define SPE 6 -#define SPIE 7 - -#define SPSR _SFR_IO8(0x2D) -#define SPI2X 0 -#define WCOL 6 -#define SPIF 7 - -#define SPDR _SFR_IO8(0x2E) - -/* Reserved [0x2F] */ - -#define ACSR _SFR_IO8(0x30) -#define ACIS0 0 -#define ACIS1 1 -#define ACIC 2 -#define ACIE 3 -#define ACI 4 -#define ACO 5 -#define ACBG 6 -#define ACD 7 - -#define OCDR _SFR_IO8(0x31) -#define OCDR0 0 -#define OCDR1 1 -#define OCDR2 2 -#define OCDR3 3 -#define OCDR4 4 -#define OCDR5 5 -#define OCDR6 6 -#define OCDR7 7 - -/* Reserved [0x32] */ - -#define SMCR _SFR_IO8(0x33) -#define SE 0 -#define SM0 1 -#define SM1 2 -#define SM2 3 - -#define MCUSR _SFR_IO8(0x34) -#define JTRF 4 -#define PORF 0 -#define EXTRF 1 -#define BORF 2 -#define WDRF 3 - -#define MCUCR _SFR_IO8(0x35) -#define JTD 7 -#define IVCE 0 -#define IVSEL 1 -#define PUD 4 - -/* Reserved [0x36] */ - -#define SPMCSR _SFR_IO8(0x37) -#define SPMEN 0 -#define PGERS 1 -#define PGWRT 2 -#define BLBSET 3 -#define RWWSRE 4 -#define SIGRD 5 -#define RWWSB 6 -#define SPMIE 7 - -/* Reserved [0x38..0x3C] */ - -/* SP [0x3D..0x3E] */ - -/* SREG [0x3F] */ - -#define WDTCSR _SFR_MEM8(0x60) -#define WDE 3 -#define WDCE 4 -#define WDP0 0 -#define WDP1 1 -#define WDP2 2 -#define WDP3 5 -#define WDIE 6 -#define WDIF 7 - -#define CLKPR _SFR_MEM8(0x61) -#define CLKPS0 0 -#define CLKPS1 1 -#define CLKPS2 2 -#define CLKPS3 3 -#define CLKPCE 7 - -/* Reserved [0x62] */ - -#define PRR2 _SFR_MEM8(0x63) -#define PRRAM0 0 -#define PRRAM1 1 -#define PRRAM2 2 -#define PRRAM3 3 - -#define __AVR_HAVE_PRR2 ((1<, never directly. */ - -#ifndef _AVR_IO_H_ -# error "Include instead of this file." -#endif - -#ifndef _AVR_IOXXX_H_ -# define _AVR_IOXXX_H_ "iom645.h" -#else -# error "Attempt to include more than one file." -#endif - -/* Registers and associated bit numbers */ - -#define PINA _SFR_IO8(0x00) -#define PINA7 7 -#define PINA6 6 -#define PINA5 5 -#define PINA4 4 -#define PINA3 3 -#define PINA2 2 -#define PINA1 1 -#define PINA0 0 - -#define DDRA _SFR_IO8(0x01) -#define DDA7 7 -#define DDA6 6 -#define DDA5 5 -#define DDA4 4 -#define DDA3 3 -#define DDA2 2 -#define DDA1 1 -#define DDA0 0 - -#define PORTA _SFR_IO8(0x02) -#define PA7 7 -#define PA6 6 -#define PA5 5 -#define PA4 4 -#define PA3 3 -#define PA2 2 -#define PA1 1 -#define PA0 0 - -#define PINB _SFR_IO8(0x03) -#define PINB7 7 -#define PINB6 6 -#define PINB5 5 -#define PINB4 4 -#define PINB3 3 -#define PINB2 2 -#define PINB1 1 -#define PINB0 0 - -#define DDRB _SFR_IO8(0x04) -#define DDB7 7 -#define DDB6 6 -#define DDB5 5 -#define DDB4 4 -#define DDB3 3 -#define DDB2 2 -#define DDB1 1 -#define DDB0 0 - -#define PORTB _SFR_IO8(0x05) -#define PB7 7 -#define PB6 6 -#define PB5 5 -#define PB4 4 -#define PB3 3 -#define PB2 2 -#define PB1 1 -#define PB0 0 - -#define PINC _SFR_IO8(0x06) -#define PINC7 7 -#define PINC6 6 -#define PINC5 5 -#define PINC4 4 -#define PINC3 3 -#define PINC2 2 -#define PINC1 1 -#define PINC0 0 - -#define DDRC _SFR_IO8(0x07) -#define DDC7 7 -#define DDC6 6 -#define DDC5 5 -#define DDC4 4 -#define DDC3 3 -#define DDC2 2 -#define DDC1 1 -#define DDC0 0 - -#define PORTC _SFR_IO8(0x08) -#define PC7 7 -#define PC6 6 -#define PC5 5 -#define PC4 4 -#define PC3 3 -#define PC2 2 -#define PC1 1 -#define PC0 0 - -#define PIND _SFR_IO8(0x09) -#define PIND7 7 -#define PIND6 6 -#define PIND5 5 -#define PIND4 4 -#define PIND3 3 -#define PIND2 2 -#define PIND1 1 -#define PIND0 0 - -#define DDRD _SFR_IO8(0x0A) -#define DDD7 7 -#define DDD6 6 -#define DDD5 5 -#define DDD4 4 -#define DDD3 3 -#define DDD2 2 -#define DDD1 1 -#define DDD0 0 - -#define PORTD _SFR_IO8(0x0B) -#define PD7 7 -#define PD6 6 -#define PD5 5 -#define PD4 4 -#define PD3 3 -#define PD2 2 -#define PD1 1 -#define PD0 0 - -#define PINE _SFR_IO8(0x0C) -#define PINE7 7 -#define PINE6 6 -#define PINE5 5 -#define PINE4 4 -#define PINE3 3 -#define PINE2 2 -#define PINE1 1 -#define PINE0 0 - -#define DDRE _SFR_IO8(0x0D) -#define DDE7 7 -#define DDE6 6 -#define DDE5 5 -#define DDE4 4 -#define DDE3 3 -#define DDE2 2 -#define DDE1 1 -#define DDE0 0 - -#define PORTE _SFR_IO8(0x0E) -#define PE7 7 -#define PE6 6 -#define PE5 5 -#define PE4 4 -#define PE3 3 -#define PE2 2 -#define PE1 1 -#define PE0 0 - -#define PINF _SFR_IO8(0x0F) -#define PINF7 7 -#define PINF6 6 -#define PINF5 5 -#define PINF4 4 -#define PINF3 3 -#define PINF2 2 -#define PINF1 1 -#define PINF0 0 - -#define DDRF _SFR_IO8(0x10) -#define DDF7 7 -#define DDF6 6 -#define DDF5 5 -#define DDF4 4 -#define DDF3 3 -#define DDF2 2 -#define DDF1 1 -#define DDF0 0 - -#define PORTF _SFR_IO8(0x11) -#define PF7 7 -#define PF6 6 -#define PF5 5 -#define PF4 4 -#define PF3 3 -#define PF2 2 -#define PF1 1 -#define PF0 0 - -#define PING _SFR_IO8(0x12) -#define PING5 5 -#define PING4 4 -#define PING3 3 -#define PING2 2 -#define PING1 1 -#define PING0 0 - -#define DDRG _SFR_IO8(0x13) -#define DDG4 4 -#define DDG3 3 -#define DDG2 2 -#define DDG1 1 -#define DDG0 0 - -#define PORTG _SFR_IO8(0x14) -#define PG4 4 -#define PG3 3 -#define PG2 2 -#define PG1 1 -#define PG0 0 - -#define TIFR0 _SFR_IO8(0x15) -#define TOV0 0 -#define OCF0A 1 - -#define TIFR1 _SFR_IO8(0x16) -#define TOV1 0 -#define OCF1A 1 -#define OCF1B 2 -#define ICF1 5 - -#define TIFR2 _SFR_IO8(0x17) -#define TOV2 0 -#define OCF2A 1 - -/* Reserved [0x18..0x1B] */ - -#define EIFR _SFR_IO8(0x1C) -#define INTF0 0 -#define PCIF0 4 -#define PCIF1 5 - -#define EIMSK _SFR_IO8(0x1D) -#define INT0 0 -#define PCIE0 4 -#define PCIE1 5 - -#define GPIOR0 _SFR_IO8(0x1E) - -#define EECR _SFR_IO8(0x1F) -#define EERE 0 -#define EEWE 1 -#define EEMWE 2 -#define EERIE 3 - -#define EEDR _SFR_IO8(0X20) - -/* Combine EEARL and EEARH */ -#define EEAR _SFR_IO16(0x21) -#define EEARL _SFR_IO8(0x21) -#define EEARH _SFR_IO8(0X22) - -/* 6-char sequence denoting where to find the EEPROM registers in memory space. - Adresses denoted in hex syntax with uppercase letters. Used by the EEPROM - subroutines. - First two letters: EECR address. - Second two letters: EEDR address. - Last two letters: EEAR address. */ -#define __EEPROM_REG_LOCATIONS__ 1F2021 - -#define GTCCR _SFR_IO8(0x23) -#define PSR10 0 -#define PSR2 1 -#define TSM 7 - -#define TCCR0A _SFR_IO8(0x24) -#define CS00 0 -#define CS01 1 -#define CS02 2 -#define WGM01 3 -#define COM0A0 4 -#define COM0A1 5 -#define WGM00 6 -#define FOC0A 7 - -/* Reserved [0x25] */ - -#define TCNT0 _SFR_IO8(0X26) - -#define OCR0A _SFR_IO8(0X27) - -/* Reserved [0x28..0x29] */ - -#define GPIOR1 _SFR_IO8(0x2A) - -#define GPIOR2 _SFR_IO8(0x2B) - -#define SPCR _SFR_IO8(0x2C) -#define SPR0 0 -#define SPR1 1 -#define CPHA 2 -#define CPOL 3 -#define MSTR 4 -#define DORD 5 -#define SPE 6 -#define SPIE 7 - -#define SPSR _SFR_IO8(0x2D) -#define SPI2X 0 -#define WCOL 6 -#define SPIF 7 - -#define SPDR _SFR_IO8(0X2E) - -/* Reserved [0x2F] */ - -#define ACSR _SFR_IO8(0x30) -#define ACIS0 0 -#define ACIS1 1 -#define ACIC 2 -#define ACIE 3 -#define ACI 4 -#define ACO 5 -#define ACBG 6 -#define ACD 7 - -#define OCDR _SFR_IO8(0x31) -#define OCDR0 0 -#define OCDR1 1 -#define OCDR2 2 -#define OCDR3 3 -#define OCDR4 4 -#define OCDR5 5 -#define OCDR6 6 -#define OCDR7 7 -#define IDRD 7 - -/* Reserved [0x32] */ - -#define SMCR _SFR_IO8(0x33) -#define SE 0 -#define SM0 1 -#define SM1 2 -#define SM2 3 - -#define MCUSR _SFR_IO8(0x34) -#define PORF 0 -#define EXTRF 1 -#define BORF 2 -#define WDRF 3 -#define JTRF 4 - -#define MCUCR _SFR_IO8(0X35) -#define IVCE 0 -#define IVSEL 1 -#define PUD 4 -#define JTD 7 - -/* Reserved [0x36] */ - -#define SPMCSR _SFR_IO8(0x37) -#define SPMEN 0 -#define PGERS 1 -#define PGWRT 2 -#define BLBSET 3 -#define RWWSRE 4 -#define RWWSB 6 -#define SPMIE 7 - -/* Reserved [0x38..0x3C] */ - -/* SP [0x3D..0x3E] */ -/* SREG [0x3F] */ - -#define WDTCR _SFR_MEM8(0x60) -#define WDP0 0 -#define WDP1 1 -#define WDP2 2 -#define WDE 3 -#define WDCE 4 - -#define CLKPR _SFR_MEM8(0x61) -#define CLKPS0 0 -#define CLKPS1 1 -#define CLKPS2 2 -#define CLKPS3 3 -#define CLKPCE 7 - -/* Reserved [0x62..0x63] */ - -#define PRR _SFR_MEM8(0x64) -#define PRADC 0 -#define PRUSART0 1 -#define PRSPI 2 -#define PRTIM1 3 - -#define __AVR_HAVE_PRR ((1<, never directly. */ - -#ifndef _AVR_IO_H_ -# error "Include instead of this file." -#endif - -#ifndef _AVR_IOXXX_H_ -# define _AVR_IOXXX_H_ "iom6450.h" -#else -# error "Attempt to include more than one file." -#endif - -/* Registers and associated bit numbers */ - -#define PINA _SFR_IO8(0x00) -#define PINA7 7 -#define PINA6 6 -#define PINA5 5 -#define PINA4 4 -#define PINA3 3 -#define PINA2 2 -#define PINA1 1 -#define PINA0 0 - -#define DDRA _SFR_IO8(0x01) -#define DDA7 7 -#define DDA6 6 -#define DDA5 5 -#define DDA4 4 -#define DDA3 3 -#define DDA2 2 -#define DDA1 1 -#define DDA0 0 - -#define PORTA _SFR_IO8(0x02) -#define PA7 7 -#define PA6 6 -#define PA5 5 -#define PA4 4 -#define PA3 3 -#define PA2 2 -#define PA1 1 -#define PA0 0 - -#define PINB _SFR_IO8(0x03) -#define PINB7 7 -#define PINB6 6 -#define PINB5 5 -#define PINB4 4 -#define PINB3 3 -#define PINB2 2 -#define PINB1 1 -#define PINB0 0 - -#define DDRB _SFR_IO8(0x04) -#define DDB7 7 -#define DDB6 6 -#define DDB5 5 -#define DDB4 4 -#define DDB3 3 -#define DDB2 2 -#define DDB1 1 -#define DDB0 0 - -#define PORTB _SFR_IO8(0x05) -#define PB7 7 -#define PB6 6 -#define PB5 5 -#define PB4 4 -#define PB3 3 -#define PB2 2 -#define PB1 1 -#define PB0 0 - -#define PINC _SFR_IO8(0x06) -#define PINC7 7 -#define PINC6 6 -#define PINC5 5 -#define PINC4 4 -#define PINC3 3 -#define PINC2 2 -#define PINC1 1 -#define PINC0 0 - -#define DDRC _SFR_IO8(0x07) -#define DDC7 7 -#define DDC6 6 -#define DDC5 5 -#define DDC4 4 -#define DDC3 3 -#define DDC2 2 -#define DDC1 1 -#define DDC0 0 - -#define PORTC _SFR_IO8(0x08) -#define PC7 7 -#define PC6 6 -#define PC5 5 -#define PC4 4 -#define PC3 3 -#define PC2 2 -#define PC1 1 -#define PC0 0 - -#define PIND _SFR_IO8(0x09) -#define PIND7 7 -#define PIND6 6 -#define PIND5 5 -#define PIND4 4 -#define PIND3 3 -#define PIND2 2 -#define PIND1 1 -#define PIND0 0 - -#define DDRD _SFR_IO8(0x0A) -#define DDD7 7 -#define DDD6 6 -#define DDD5 5 -#define DDD4 4 -#define DDD3 3 -#define DDD2 2 -#define DDD1 1 -#define DDD0 0 - -#define PORTD _SFR_IO8(0x0B) -#define PD7 7 -#define PD6 6 -#define PD5 5 -#define PD4 4 -#define PD3 3 -#define PD2 2 -#define PD1 1 -#define PD0 0 - -#define PINE _SFR_IO8(0x0C) -#define PINE7 7 -#define PINE6 6 -#define PINE5 5 -#define PINE4 4 -#define PINE3 3 -#define PINE2 2 -#define PINE1 1 -#define PINE0 0 - -#define DDRE _SFR_IO8(0x0D) -#define DDE7 7 -#define DDE6 6 -#define DDE5 5 -#define DDE4 4 -#define DDE3 3 -#define DDE2 2 -#define DDE1 1 -#define DDE0 0 - -#define PORTE _SFR_IO8(0x0E) -#define PE7 7 -#define PE6 6 -#define PE5 5 -#define PE4 4 -#define PE3 3 -#define PE2 2 -#define PE1 1 -#define PE0 0 - -#define PINF _SFR_IO8(0x0F) -#define PINF7 7 -#define PINF6 6 -#define PINF5 5 -#define PINF4 4 -#define PINF3 3 -#define PINF2 2 -#define PINF1 1 -#define PINF0 0 - -#define DDRF _SFR_IO8(0x10) -#define DDF7 7 -#define DDF6 6 -#define DDF5 5 -#define DDF4 4 -#define DDF3 3 -#define DDF2 2 -#define DDF1 1 -#define DDF0 0 - -#define PORTF _SFR_IO8(0x11) -#define PF7 7 -#define PF6 6 -#define PF5 5 -#define PF4 4 -#define PF3 3 -#define PF2 2 -#define PF1 1 -#define PF0 0 - -#define PING _SFR_IO8(0x12) -#define PING5 5 -#define PING4 4 -#define PING3 3 -#define PING2 2 -#define PING1 1 -#define PING0 0 - -#define DDRG _SFR_IO8(0x13) -#define DDG4 4 -#define DDG3 3 -#define DDG2 2 -#define DDG1 1 -#define DDG0 0 - -#define PORTG _SFR_IO8(0x14) -#define PG4 4 -#define PG3 3 -#define PG2 2 -#define PG1 1 -#define PG0 0 - -#define TIFR0 _SFR_IO8(0x15) -#define TOV0 0 -#define OCF0A 1 - -#define TIFR1 _SFR_IO8(0x16) -#define TOV1 0 -#define OCF1A 1 -#define OCF1B 2 -#define ICF1 5 - -#define TIFR2 _SFR_IO8(0x17) -#define TOV2 0 -#define OCF2A 1 - -/* Reserved [0x18..0x1B] */ - -#define EIFR _SFR_IO8(0x1C) -#define INTF0 0 -#define PCIF0 4 -#define PCIF1 5 -#define PCIF2 6 -#define PCIF3 7 - -#define EIMSK _SFR_IO8(0x1D) -#define INT0 0 -#define PCIE0 4 -#define PCIE1 5 -#define PCIE2 6 -#define PCIE3 7 - -#define GPIOR0 _SFR_IO8(0x1E) - -#define EECR _SFR_IO8(0x1F) -#define EERE 0 -#define EEWE 1 -#define EEMWE 2 -#define EERIE 3 - -#define EEDR _SFR_IO8(0X20) - -/* Combine EEARL and EEARH */ -#define EEAR _SFR_IO16(0x21) -#define EEARL _SFR_IO8(0x21) -#define EEARH _SFR_IO8(0X22) - -/* 6-char sequence denoting where to find the EEPROM registers in memory space. - Adresses denoted in hex syntax with uppercase letters. Used by the EEPROM - subroutines. - First two letters: EECR address. - Second two letters: EEDR address. - Last two letters: EEAR address. */ -#define __EEPROM_REG_LOCATIONS__ 1F2021 - -#define GTCCR _SFR_IO8(0x23) -#define PSR10 0 -#define PSR2 1 -#define TSM 7 - -#define TCCR0A _SFR_IO8(0x24) -#define CS00 0 -#define CS01 1 -#define CS02 2 -#define WGM01 3 -#define COM0A0 4 -#define COM0A1 5 -#define WGM00 6 -#define FOC0A 7 - -/* Reserved [0x25] */ - -#define TCNT0 _SFR_IO8(0X26) - -#define OCR0A _SFR_IO8(0X27) - -/* Reserved [0x28..0x29] */ - -#define GPIOR1 _SFR_IO8(0x2A) - -#define GPIOR2 _SFR_IO8(0x2B) - -#define SPCR _SFR_IO8(0x2C) -#define SPR0 0 -#define SPR1 1 -#define CPHA 2 -#define CPOL 3 -#define MSTR 4 -#define DORD 5 -#define SPE 6 -#define SPIE 7 - -#define SPSR _SFR_IO8(0x2D) -#define SPI2X 0 -#define WCOL 6 -#define SPIF 7 - -#define SPDR _SFR_IO8(0X2E) - -/* Reserved [0x2F] */ - -#define ACSR _SFR_IO8(0x30) -#define ACIS0 0 -#define ACIS1 1 -#define ACIC 2 -#define ACIE 3 -#define ACI 4 -#define ACO 5 -#define ACBG 6 -#define ACD 7 - -#define OCDR _SFR_IO8(0x31) -#define OCDR0 0 -#define OCDR1 1 -#define OCDR2 2 -#define OCDR3 3 -#define OCDR4 4 -#define OCDR5 5 -#define OCDR6 6 -#define OCDR7 7 -#define IDRD 7 - -/* Reserved [0x32] */ - -#define SMCR _SFR_IO8(0x33) -#define SE 0 -#define SM0 1 -#define SM1 2 -#define SM2 3 - -#define MCUSR _SFR_IO8(0x34) -#define PORF 0 -#define EXTRF 1 -#define BORF 2 -#define WDRF 3 -#define JTRF 4 - -#define MCUCR _SFR_IO8(0X35) -#define IVCE 0 -#define IVSEL 1 -#define PUD 4 -#define JTD 7 - -/* Reserved [0x36] */ - -#define SPMCSR _SFR_IO8(0x37) -#define SPMEN 0 -#define PGERS 1 -#define PGWRT 2 -#define BLBSET 3 -#define RWWSRE 4 -#define RWWSB 6 -#define SPMIE 7 - -/* Reserved [0x38..0x3C] */ - -/* SP [0x3D..0x3E] */ -/* SREG [0x3F] */ - -#define WDTCR _SFR_MEM8(0x60) -#define WDP0 0 -#define WDP1 1 -#define WDP2 2 -#define WDE 3 -#define WDCE 4 - -#define CLKPR _SFR_MEM8(0x61) -#define CLKPS0 0 -#define CLKPS1 1 -#define CLKPS2 2 -#define CLKPS3 3 -#define CLKPCE 7 - -/* Reserved [0x62..0x63] */ - -#define PRR _SFR_MEM8(0x64) -#define PRADC 0 -#define PRUSART0 1 -#define PRSPI 2 -#define PRTIM1 3 - -#define __AVR_HAVE_PRR ((1<, never directly. */ - -#ifndef _AVR_IO_H_ -# error "Include instead of this file." -#endif - -#ifndef _AVR_IOXXX_H_ -# define _AVR_IOXXX_H_ "iom649.h" -#else -# error "Attempt to include more than one file." -#endif - -/* Registers and associated bit numbers */ - -#define PINA _SFR_IO8(0x00) -#define PINA7 7 -#define PINA6 6 -#define PINA5 5 -#define PINA4 4 -#define PINA3 3 -#define PINA2 2 -#define PINA1 1 -#define PINA0 0 - -#define DDRA _SFR_IO8(0x01) -#define DDA7 7 -#define DDA6 6 -#define DDA5 5 -#define DDA4 4 -#define DDA3 3 -#define DDA2 2 -#define DDA1 1 -#define DDA0 0 - -#define PORTA _SFR_IO8(0x02) -#define PA7 7 -#define PA6 6 -#define PA5 5 -#define PA4 4 -#define PA3 3 -#define PA2 2 -#define PA1 1 -#define PA0 0 - -#define PINB _SFR_IO8(0x03) -#define PINB7 7 -#define PINB6 6 -#define PINB5 5 -#define PINB4 4 -#define PINB3 3 -#define PINB2 2 -#define PINB1 1 -#define PINB0 0 - -#define DDRB _SFR_IO8(0x04) -#define DDB7 7 -#define DDB6 6 -#define DDB5 5 -#define DDB4 4 -#define DDB3 3 -#define DDB2 2 -#define DDB1 1 -#define DDB0 0 - -#define PORTB _SFR_IO8(0x05) -#define PB7 7 -#define PB6 6 -#define PB5 5 -#define PB4 4 -#define PB3 3 -#define PB2 2 -#define PB1 1 -#define PB0 0 - -#define PINC _SFR_IO8(0x06) -#define PINC7 7 -#define PINC6 6 -#define PINC5 5 -#define PINC4 4 -#define PINC3 3 -#define PINC2 2 -#define PINC1 1 -#define PINC0 0 - -#define DDRC _SFR_IO8(0x07) -#define DDC7 7 -#define DDC6 6 -#define DDC5 5 -#define DDC4 4 -#define DDC3 3 -#define DDC2 2 -#define DDC1 1 -#define DDC0 0 - -#define PORTC _SFR_IO8(0x08) -#define PC7 7 -#define PC6 6 -#define PC5 5 -#define PC4 4 -#define PC3 3 -#define PC2 2 -#define PC1 1 -#define PC0 0 - -#define PIND _SFR_IO8(0x09) -#define PIND7 7 -#define PIND6 6 -#define PIND5 5 -#define PIND4 4 -#define PIND3 3 -#define PIND2 2 -#define PIND1 1 -#define PIND0 0 - -#define DDRD _SFR_IO8(0x0A) -#define DDD7 7 -#define DDD6 6 -#define DDD5 5 -#define DDD4 4 -#define DDD3 3 -#define DDD2 2 -#define DDD1 1 -#define DDD0 0 - -#define PORTD _SFR_IO8(0x0B) -#define PD7 7 -#define PD6 6 -#define PD5 5 -#define PD4 4 -#define PD3 3 -#define PD2 2 -#define PD1 1 -#define PD0 0 - -#define PINE _SFR_IO8(0x0C) -#define PINE7 7 -#define PINE6 6 -#define PINE5 5 -#define PINE4 4 -#define PINE3 3 -#define PINE2 2 -#define PINE1 1 -#define PINE0 0 - -#define DDRE _SFR_IO8(0x0D) -#define DDE7 7 -#define DDE6 6 -#define DDE5 5 -#define DDE4 4 -#define DDE3 3 -#define DDE2 2 -#define DDE1 1 -#define DDE0 0 - -#define PORTE _SFR_IO8(0x0E) -#define PE7 7 -#define PE6 6 -#define PE5 5 -#define PE4 4 -#define PE3 3 -#define PE2 2 -#define PE1 1 -#define PE0 0 - -#define PINF _SFR_IO8(0x0F) -#define PINF7 7 -#define PINF6 6 -#define PINF5 5 -#define PINF4 4 -#define PINF3 3 -#define PINF2 2 -#define PINF1 1 -#define PINF0 0 - -#define DDRF _SFR_IO8(0x10) -#define DDF7 7 -#define DDF6 6 -#define DDF5 5 -#define DDF4 4 -#define DDF3 3 -#define DDF2 2 -#define DDF1 1 -#define DDF0 0 - -#define PORTF _SFR_IO8(0x11) -#define PF7 7 -#define PF6 6 -#define PF5 5 -#define PF4 4 -#define PF3 3 -#define PF2 2 -#define PF1 1 -#define PF0 0 - -#define PING _SFR_IO8(0x12) -#define PING5 5 -#define PING4 4 -#define PING3 3 -#define PING2 2 -#define PING1 1 -#define PING0 0 - -#define DDRG _SFR_IO8(0x13) -#define DDG4 4 -#define DDG3 3 -#define DDG2 2 -#define DDG1 1 -#define DDG0 0 - -#define PORTG _SFR_IO8(0x14) -#define PG4 4 -#define PG3 3 -#define PG2 2 -#define PG1 1 -#define PG0 0 - -#define TIFR0 _SFR_IO8(0x15) -#define TOV0 0 -#define OCF0A 1 - -#define TIFR1 _SFR_IO8(0x16) -#define TOV1 0 -#define OCF1A 1 -#define OCF1B 2 -#define ICF1 5 - -#define TIFR2 _SFR_IO8(0x17) -#define TOV2 0 -#define OCF2A 1 - -/* Reserved [0x18..0x1B] */ - -#define EIFR _SFR_IO8(0x1C) -#define INTF0 0 -#define PCIF0 4 -#define PCIF1 5 - -#define EIMSK _SFR_IO8(0x1D) -#define INT0 0 -#define PCIE0 4 -#define PCIE1 5 - -#define GPIOR0 _SFR_IO8(0x1E) - -#define EECR _SFR_IO8(0x1F) -#define EERIE 3 -#define EEMWE 2 -#define EEWE 1 -#define EERE 0 - -#define EEDR _SFR_IO8(0X20) - -/* Combine EEARL and EEARH */ -#define EEAR _SFR_IO16(0x21) -#define EEARL _SFR_IO8(0x21) -#define EEARH _SFR_IO8(0X22) - -/* 6-char sequence denoting where to find the EEPROM registers in memory space. - Adresses denoted in hex syntax with uppercase letters. Used by the EEPROM - subroutines. - First two letters: EECR address. - Second two letters: EEDR address. - Last two letters: EEAR address. */ -#define __EEPROM_REG_LOCATIONS__ 1F2021 - -#define GTCCR _SFR_IO8(0x23) -#define PSR10 0 -#define PSR2 1 -#define TSM 7 - -#define TCCR0A _SFR_IO8(0x24) -#define CS00 0 -#define CS01 1 -#define CS02 2 -#define WGM01 3 -#define COM0A0 4 -#define COM0A1 5 -#define WGM00 6 -#define FOC0A 7 - -/* Reserved [0x25] */ - -#define TCNT0 _SFR_IO8(0X26) - -#define OCR0A _SFR_IO8(0X27) - -/* Reserved [0x28..0x29] */ - -#define GPIOR1 _SFR_IO8(0x2A) - -#define GPIOR2 _SFR_IO8(0x2B) - -#define SPCR _SFR_IO8(0x2C) -#define SPR0 0 -#define SPR1 1 -#define CPHA 2 -#define CPOL 3 -#define MSTR 4 -#define DORD 5 -#define SPE 6 -#define SPIE 7 - -#define SPSR _SFR_IO8(0x2D) -#define SPI2X 0 -#define WCOL 6 -#define SPIF 7 - -#define SPDR _SFR_IO8(0X2E) - -/* Reserved [0x2F] */ - -#define ACSR _SFR_IO8(0x30) -#define ACIS0 0 -#define ACIS1 1 -#define ACIC 2 -#define ACIE 3 -#define ACI 4 -#define ACO 5 -#define ACBG 6 -#define ACD 7 - -#define OCDR _SFR_IO8(0x31) -#define OCDR0 0 -#define OCDR1 1 -#define OCDR2 2 -#define OCDR3 3 -#define OCDR4 4 -#define OCDR5 5 -#define OCDR6 6 -#define OCDR7 7 -#define IDRD 7 - -/* Reserved [0x32] */ - -#define SMCR _SFR_IO8(0x33) -#define SE 0 -#define SM0 1 -#define SM1 2 -#define SM2 3 - -#define MCUSR _SFR_IO8(0x34) -#define PORF 0 -#define EXTRF 1 -#define BORF 2 -#define WDRF 3 -#define JTRF 4 - -#define MCUCR _SFR_IO8(0X35) -#define IVCE 0 -#define IVSEL 1 -#define PUD 4 -#define JTD 7 - -/* Reserved [0x36] */ - -#define SPMCSR _SFR_IO8(0x37) -#define SPMEN 0 -#define PGERS 1 -#define PGWRT 2 -#define BLBSET 3 -#define RWWSRE 4 -#define RWWSB 6 -#define SPMIE 7 - -/* Reserved [0x38..0x3C] */ - -/* SP [0x3D..0x3E] */ -/* SREG [0x3F] */ - -#define WDTCR _SFR_MEM8(0x60) -#define WDP0 0 -#define WDP1 1 -#define WDP2 2 -#define WDE 3 -#define WDCE 4 - -#define CLKPR _SFR_MEM8(0x61) -#define CLKPS0 0 -#define CLKPS1 1 -#define CLKPS2 2 -#define CLKPS3 3 -#define CLKPCE 7 - -/* Reserved [0x62..0x63] */ - -#define PRR _SFR_MEM8(0x64) -#define PRADC 0 -#define PRUSART0 1 -#define PRSPI 2 -#define PRTIM1 3 -#define PRLCD 4 - -#define __AVR_HAVE_PRR ((1<, never directly. */ - -#ifndef _AVR_IO_H_ -# error "Include instead of this file." -#endif - -#ifndef _AVR_IOXXX_H_ -# define _AVR_IOXXX_H_ "iom6490.h" -#else -# error "Attempt to include more than one file." -#endif - -/* Registers and associated bit numbers */ - -#define PINA _SFR_IO8(0x00) -#define PINA7 7 -#define PINA6 6 -#define PINA5 5 -#define PINA4 4 -#define PINA3 3 -#define PINA2 2 -#define PINA1 1 -#define PINA0 0 - -#define DDRA _SFR_IO8(0x01) -#define DDA7 7 -#define DDA6 6 -#define DDA5 5 -#define DDA4 4 -#define DDA3 3 -#define DDA2 2 -#define DDA1 1 -#define DDA0 0 - -#define PORTA _SFR_IO8(0x02) -#define PA7 7 -#define PA6 6 -#define PA5 5 -#define PA4 4 -#define PA3 3 -#define PA2 2 -#define PA1 1 -#define PA0 0 - -#define PINB _SFR_IO8(0x03) -#define PINB7 7 -#define PINB6 6 -#define PINB5 5 -#define PINB4 4 -#define PINB3 3 -#define PINB2 2 -#define PINB1 1 -#define PINB0 0 - -#define DDRB _SFR_IO8(0x04) -#define DDB7 7 -#define DDB6 6 -#define DDB5 5 -#define DDB4 4 -#define DDB3 3 -#define DDB2 2 -#define DDB1 1 -#define DDB0 0 - -#define PORTB _SFR_IO8(0x05) -#define PB7 7 -#define PB6 6 -#define PB5 5 -#define PB4 4 -#define PB3 3 -#define PB2 2 -#define PB1 1 -#define PB0 0 - -#define PINC _SFR_IO8(0x06) -#define PINC7 7 -#define PINC6 6 -#define PINC5 5 -#define PINC4 4 -#define PINC3 3 -#define PINC2 2 -#define PINC1 1 -#define PINC0 0 - -#define DDRC _SFR_IO8(0x07) -#define DDC7 7 -#define DDC6 6 -#define DDC5 5 -#define DDC4 4 -#define DDC3 3 -#define DDC2 2 -#define DDC1 1 -#define DDC0 0 - -#define PORTC _SFR_IO8(0x08) -#define PC7 7 -#define PC6 6 -#define PC5 5 -#define PC4 4 -#define PC3 3 -#define PC2 2 -#define PC1 1 -#define PC0 0 - -#define PIND _SFR_IO8(0x09) -#define PIND7 7 -#define PIND6 6 -#define PIND5 5 -#define PIND4 4 -#define PIND3 3 -#define PIND2 2 -#define PIND1 1 -#define PIND0 0 - -#define DDRD _SFR_IO8(0x0A) -#define DDD7 7 -#define DDD6 6 -#define DDD5 5 -#define DDD4 4 -#define DDD3 3 -#define DDD2 2 -#define DDD1 1 -#define DDD0 0 - -#define PORTD _SFR_IO8(0x0B) -#define PD7 7 -#define PD6 6 -#define PD5 5 -#define PD4 4 -#define PD3 3 -#define PD2 2 -#define PD1 1 -#define PD0 0 - -#define PINE _SFR_IO8(0x0C) -#define PINE7 7 -#define PINE6 6 -#define PINE5 5 -#define PINE4 4 -#define PINE3 3 -#define PINE2 2 -#define PINE1 1 -#define PINE0 0 - -#define DDRE _SFR_IO8(0x0D) -#define DDE7 7 -#define DDE6 6 -#define DDE5 5 -#define DDE4 4 -#define DDE3 3 -#define DDE2 2 -#define DDE1 1 -#define DDE0 0 - -#define PORTE _SFR_IO8(0x0E) -#define PE7 7 -#define PE6 6 -#define PE5 5 -#define PE4 4 -#define PE3 3 -#define PE2 2 -#define PE1 1 -#define PE0 0 - -#define PINF _SFR_IO8(0x0F) -#define PINF7 7 -#define PINF6 6 -#define PINF5 5 -#define PINF4 4 -#define PINF3 3 -#define PINF2 2 -#define PINF1 1 -#define PINF0 0 - -#define DDRF _SFR_IO8(0x10) -#define DDF7 7 -#define DDF6 6 -#define DDF5 5 -#define DDF4 4 -#define DDF3 3 -#define DDF2 2 -#define DDF1 1 -#define DDF0 0 - -#define PORTF _SFR_IO8(0x11) -#define PF7 7 -#define PF6 6 -#define PF5 5 -#define PF4 4 -#define PF3 3 -#define PF2 2 -#define PF1 1 -#define PF0 0 - -#define PING _SFR_IO8(0x12) -#define PING5 5 -#define PING4 4 -#define PING3 3 -#define PING2 2 -#define PING1 1 -#define PING0 0 - -#define DDRG _SFR_IO8(0x13) -#define DDG4 4 -#define DDG3 3 -#define DDG2 2 -#define DDG1 1 -#define DDG0 0 - -#define PORTG _SFR_IO8(0x14) -#define PG4 4 -#define PG3 3 -#define PG2 2 -#define PG1 1 -#define PG0 0 - -#define TIFR0 _SFR_IO8(0x15) -#define TOV0 0 -#define OCF0A 1 - -#define TIFR1 _SFR_IO8(0x16) -#define TOV1 0 -#define OCF1A 1 -#define OCF1B 2 -#define ICF1 5 - -#define TIFR2 _SFR_IO8(0x17) -#define TOV2 0 -#define OCF2A 1 - -/* Reserved [0x18..0x1B] */ - -#define EIFR _SFR_IO8(0x1C) -#define INTF0 0 -#define PCIF0 4 -#define PCIF1 5 -#define PCIF2 6 -#define PCIF3 7 - -#define EIMSK _SFR_IO8(0x1D) -#define INT0 0 -#define PCIE0 4 -#define PCIE1 5 -#define PCIE2 6 -#define PCIE3 7 - -#define GPIOR0 _SFR_IO8(0x1E) - -#define EECR _SFR_IO8(0x1F) -#define EERIE 3 -#define EEMWE 2 -#define EEWE 1 -#define EERE 0 - -#define EEDR _SFR_IO8(0X20) - -/* Combine EEARL and EEARH */ -#define EEAR _SFR_IO16(0x21) -#define EEARL _SFR_IO8(0x21) -#define EEARH _SFR_IO8(0X22) - -/* 6-char sequence denoting where to find the EEPROM registers in memory space. - Adresses denoted in hex syntax with uppercase letters. Used by the EEPROM - subroutines. - First two letters: EECR address. - Second two letters: EEDR address. - Last two letters: EEAR address. */ -#define __EEPROM_REG_LOCATIONS__ 1F2021 - -#define GTCCR _SFR_IO8(0x23) -#define PSR10 0 -#define PSR2 1 -#define TSM 7 - -#define TCCR0A _SFR_IO8(0x24) -#define CS00 0 -#define CS01 1 -#define CS02 2 -#define WGM01 3 -#define COM0A0 4 -#define COM0A1 5 -#define WGM00 6 -#define FOC0A 7 - -/* Reserved [0x25] */ - -#define TCNT0 _SFR_IO8(0X26) - -#define OCR0A _SFR_IO8(0X27) - -/* Reserved [0x28..0x29] */ - -#define GPIOR1 _SFR_IO8(0x2A) - -#define GPIOR2 _SFR_IO8(0x2B) - -#define SPCR _SFR_IO8(0x2C) -#define SPR0 0 -#define SPR1 1 -#define CPHA 2 -#define CPOL 3 -#define MSTR 4 -#define DORD 5 -#define SPE 6 -#define SPIE 7 - -#define SPSR _SFR_IO8(0x2D) -#define SPI2X 0 -#define WCOL 6 -#define SPIF 7 - -#define SPDR _SFR_IO8(0X2E) - -/* Reserved [0x2F] */ - -#define ACSR _SFR_IO8(0x30) -#define ACIS0 0 -#define ACIS1 1 -#define ACIC 2 -#define ACIE 3 -#define ACI 4 -#define ACO 5 -#define ACBG 6 -#define ACD 7 - -#define OCDR _SFR_IO8(0x31) -#define OCDR0 0 -#define OCDR1 1 -#define OCDR2 2 -#define OCDR3 3 -#define OCDR4 4 -#define OCDR5 5 -#define OCDR6 6 -#define OCDR7 7 -#define IDRD 7 - -/* Reserved [0x32] */ - -#define SMCR _SFR_IO8(0x33) -#define SE 0 -#define SM0 1 -#define SM1 2 -#define SM2 3 - -#define MCUSR _SFR_IO8(0x34) -#define PORF 0 -#define EXTRF 1 -#define BORF 2 -#define WDRF 3 -#define JTRF 4 - -#define MCUCR _SFR_IO8(0X35) -#define IVCE 0 -#define IVSEL 1 -#define PUD 4 -#define JTD 7 - -/* Reserved [0x36] */ - -#define SPMCSR _SFR_IO8(0x37) -#define SPMEN 0 -#define PGERS 1 -#define PGWRT 2 -#define BLBSET 3 -#define RWWSRE 4 -#define RWWSB 6 -#define SPMIE 7 - -/* Reserved [0x38..0x3C] */ - -/* SP [0x3D..0x3E] */ -/* SREG [0x3F] */ - -#define WDTCR _SFR_MEM8(0x60) -#define WDP0 0 -#define WDP1 1 -#define WDP2 2 -#define WDE 3 -#define WDCE 4 - -#define CLKPR _SFR_MEM8(0x61) -#define CLKPS0 0 -#define CLKPS1 1 -#define CLKPS2 2 -#define CLKPS3 3 -#define CLKPCE 7 - -/* Reserved [0x62..0x63] */ - -#define PRR _SFR_MEM8(0x64) -#define PRADC 0 -#define PRUSART0 1 -#define PRSPI 2 -#define PRTIM1 3 -#define PRLCD 4 - -#define __AVR_HAVE_PRR ((1<, never directly. */ - -#ifndef _AVR_IO_H_ -# error "Include instead of this file." -#endif - -#ifndef _AVR_IOXXX_H_ -# define _AVR_IOXXX_H_ "iom649p.h" -#else -# error "Attempt to include more than one file." -#endif - - -#ifndef _AVR_ATmega649_H_ -#define _AVR_ATmega649_H_ 1 - - -/* Registers and associated bit numbers. */ - -#define PINA _SFR_IO8(0x00) -#define PINA0 0 -#define PINA1 1 -#define PINA2 2 -#define PINA3 3 -#define PINA4 4 -#define PINA5 5 -#define PINA6 6 -#define PINA7 7 - -#define DDRA _SFR_IO8(0x01) -#define DDA0 0 -#define DDA1 1 -#define DDA2 2 -#define DDA3 3 -#define DDA4 4 -#define DDA5 5 -#define DDA6 6 -#define DDA7 7 - -#define PORTA _SFR_IO8(0x02) -#define PORTA0 0 -#define PORTA1 1 -#define PORTA2 2 -#define PORTA3 3 -#define PORTA4 4 -#define PORTA5 5 -#define PORTA6 6 -#define PORTA7 7 - -#define PINB _SFR_IO8(0x03) -#define PINB0 0 -#define PINB1 1 -#define PINB2 2 -#define PINB3 3 -#define PINB4 4 -#define PINB5 5 -#define PINB6 6 -#define PINB7 7 - -#define DDRB _SFR_IO8(0x04) -#define DDB0 0 -#define DDB1 1 -#define DDB2 2 -#define DDB3 3 -#define DDB4 4 -#define DDB5 5 -#define DDB6 6 -#define DDB7 7 - -#define PORTB _SFR_IO8(0x05) -#define PORTB0 0 -#define PORTB1 1 -#define PORTB2 2 -#define PORTB3 3 -#define PORTB4 4 -#define PORTB5 5 -#define PORTB6 6 -#define PORTB7 7 - -#define PINC _SFR_IO8(0x06) -#define PINC0 0 -#define PINC1 1 -#define PINC2 2 -#define PINC3 3 -#define PINC4 4 -#define PINC5 5 -#define PINC6 6 -#define PINC7 7 - -#define DDRC _SFR_IO8(0x07) -#define DDC0 0 -#define DDC1 1 -#define DDC2 2 -#define DDC3 3 -#define DDC4 4 -#define DDC5 5 -#define DDC6 6 -#define DDC7 7 - -#define PORTC _SFR_IO8(0x08) -#define PORTC0 0 -#define PORTC1 1 -#define PORTC2 2 -#define PORTC3 3 -#define PORTC4 4 -#define PORTC5 5 -#define PORTC6 6 -#define PORTC7 7 - -#define PIND _SFR_IO8(0x09) -#define PIND0 0 -#define PIND1 1 -#define PIND2 2 -#define PIND3 3 -#define PIND4 4 -#define PIND5 5 -#define PIND6 6 -#define PIND7 7 - -#define DDRD _SFR_IO8(0x0A) -#define DDD0 0 -#define DDD1 1 -#define DDD2 2 -#define DDD3 3 -#define DDD4 4 -#define DDD5 5 -#define DDD6 6 -#define DDD7 7 - -#define PORTD _SFR_IO8(0x0B) -#define PORTD0 0 -#define PORTD1 1 -#define PORTD2 2 -#define PORTD3 3 -#define PORTD4 4 -#define PORTD5 5 -#define PORTD6 6 -#define PORTD7 7 - -#define PINE _SFR_IO8(0x0C) -#define PINE0 0 -#define PINE1 1 -#define PINE2 2 -#define PINE3 3 -#define PINE4 4 -#define PINE5 5 -#define PINE6 6 -#define PINE7 7 - -#define DDRE _SFR_IO8(0x0D) -#define DDE0 0 -#define DDE1 1 -#define DDE2 2 -#define DDE3 3 -#define DDE4 4 -#define DDE5 5 -#define DDE6 6 -#define DDE7 7 - -#define PORTE _SFR_IO8(0x0E) -#define PORTE0 0 -#define PORTE1 1 -#define PORTE2 2 -#define PORTE3 3 -#define PORTE4 4 -#define PORTE5 5 -#define PORTE6 6 -#define PORTE7 7 - -#define PINF _SFR_IO8(0x0F) -#define PINF0 0 -#define PINF1 1 -#define PINF2 2 -#define PINF3 3 -#define PINF4 4 -#define PINF5 5 -#define PINF6 6 -#define PINF7 7 - -#define DDRF _SFR_IO8(0x10) -#define DDF0 0 -#define DDF1 1 -#define DDF2 2 -#define DDF3 3 -#define DDF4 4 -#define DDF5 5 -#define DDF6 6 -#define DDF7 7 - -#define PORTF _SFR_IO8(0x11) -#define PORTF0 0 -#define PORTF1 1 -#define PORTF2 2 -#define PORTF3 3 -#define PORTF4 4 -#define PORTF5 5 -#define PORTF6 6 -#define PORTF7 7 - -#define PING _SFR_IO8(0x12) -#define PING0 0 -#define PING1 1 -#define PING2 2 -#define PING3 3 -#define PING4 4 -#define PING5 5 - -#define DDRG _SFR_IO8(0x13) -#define DDG0 0 -#define DDG1 1 -#define DDG2 2 -#define DDG3 3 -#define DDG4 4 - -#define PORTG _SFR_IO8(0x14) -#define PORTG0 0 -#define PORTG1 1 -#define PORTG2 2 -#define PORTG3 3 -#define PORTG4 4 - -#define TIFR0 _SFR_IO8(0x15) -#define TOV0 0 -#define OCF0A 1 - -#define TIFR1 _SFR_IO8(0x16) -#define TOV1 0 -#define OCF1A 1 -#define OCF1B 2 -#define ICF1 5 - -#define TIFR2 _SFR_IO8(0x17) -#define TOV2 0 -#define OCF2A 1 - -#define EIFR _SFR_IO8(0x1C) -#define INTF0 0 -#define PCIF0 4 -#define PCIF1 5 -#define PCIF2 6 -#define PCIF3 7 - -#define EIMSK _SFR_IO8(0x1D) -#define INT0 0 -#define PCIE0 4 -#define PCIE1 5 -#define PCIE2 6 -#define PCIE3 7 - -#define GPIOR0 _SFR_IO8(0x1E) -#define GPIOR00 0 -#define GPIOR01 1 -#define GPIOR02 2 -#define GPIOR03 3 -#define GPIOR04 4 -#define GPIOR05 5 -#define GPIOR06 6 -#define GPIOR07 7 - -#define EECR _SFR_IO8(0x1F) -#define EERE 0 -#define EEWE 1 -#define EEMWE 2 -#define EERIE 3 - -#define EEDR _SFR_IO8(0x20) -#define EEDR0 0 -#define EEDR1 1 -#define EEDR2 2 -#define EEDR3 3 -#define EEDR4 4 -#define EEDR5 5 -#define EEDR6 6 -#define EEDR7 7 - -#define EEAR _SFR_IO16(0x21) - -#define EEARL _SFR_IO8(0x21) -#define EEARL0 0 -#define EEARL1 1 -#define EEARL2 2 -#define EEARL3 3 -#define EEARL4 4 -#define EEARL5 5 -#define EEARL6 6 -#define EEARL7 7 - -#define EEARH _SFR_IO8(0x22) -#define EEAR8 0 -#define EEAR9 1 -#define EEAR10 2 - -#define GTCCR _SFR_IO8(0x23) -#define PSR310 0 -#define PSR2 1 -#define TSM 7 - -#define TCCR0A _SFR_IO8(0x24) -#define CS00 0 -#define CS01 1 -#define CS02 2 -#define WGM01 3 -#define COM0A0 4 -#define COM0A1 5 -#define WGM00 6 -#define FOC0A 7 - -#define TCNT0 _SFR_IO8(0x26) -#define TCNT0_0 0 -#define TCNT0_1 1 -#define TCNT0_2 2 -#define TCNT0_3 3 -#define TCNT0_4 4 -#define TCNT0_5 5 -#define TCNT0_6 6 -#define TCNT0_7 7 - -#define OCR0A _SFR_IO8(0x27) -#define OCR0A0 0 -#define OCR0A1 1 -#define OCR0A2 2 -#define OCR0A3 3 -#define OCR0A4 4 -#define OCR0A5 5 -#define OCR0A6 6 -#define OCR0A7 7 - -#define GPIOR1 _SFR_IO8(0x2A) -#define GPIOR10 0 -#define GPIOR11 1 -#define GPIOR12 2 -#define GPIOR13 3 -#define GPIOR14 4 -#define GPIOR15 5 -#define GPIOR16 6 -#define GPIOR17 7 - -#define GPIOR2 _SFR_IO8(0x2B) -#define GPIOR20 0 -#define GPIOR21 1 -#define GPIOR22 2 -#define GPIOR23 3 -#define GPIOR24 4 -#define GPIOR25 5 -#define GPIOR26 6 -#define GPIOR27 7 - -#define SPCR _SFR_IO8(0x2C) -#define SPR0 0 -#define SPR1 1 -#define CPHA 2 -#define CPOL 3 -#define MSTR 4 -#define DORD 5 -#define SPE 6 -#define SPIE 7 - -#define SPSR _SFR_IO8(0x2D) -#define SPI2X 0 -#define WCOL 6 -#define SPIF 7 - -#define SPDR _SFR_IO8(0x2E) -#define SPDR0 0 -#define SPDR1 1 -#define SPDR2 2 -#define SPDR3 3 -#define SPDR4 4 -#define SPDR5 5 -#define SPDR6 6 -#define SPDR7 7 - -#define ACSR _SFR_IO8(0x30) -#define ACIS0 0 -#define ACIS1 1 -#define ACIC 2 -#define ACIE 3 -#define ACI 4 -#define ACO 5 -#define ACBG 6 -#define ACD 7 - -#define OCDR _SFR_IO8(0x31) -#define OCDR0 0 -#define OCDR1 1 -#define OCDR2 2 -#define OCDR3 3 -#define OCDR4 4 -#define OCDR5 5 -#define OCDR6 6 -#define OCDR7 7 - -#define SMCR _SFR_IO8(0x33) -#define SE 0 -#define SM0 1 -#define SM1 2 -#define SM2 3 - -#define MCUSR _SFR_IO8(0x34) -#define PORF 0 -#define EXTRF 1 -#define BORF 2 -#define WDRF 3 -#define JTRF 4 - -#define MCUCR _SFR_IO8(0x35) -#define IVCE 0 -#define IVSEL 1 -#define PUD 4 -#define JTD 7 - -#define SPMCSR _SFR_IO8(0x37) -#define SPMEN 0 -#define PGERS 1 -#define PGWRT 2 -#define BLBSET 3 -#define RWWSRE 4 -#define RWWSB 6 -#define SPMIE 7 - -#define WDTCR _SFR_MEM8(0x60) -#define WDP0 0 -#define WDP1 1 -#define WDP2 2 -#define WDE 3 -#define WDCE 4 - -#define CLKPR _SFR_MEM8(0x61) -#define CLKPS0 0 -#define CLKPS1 1 -#define CLKPS2 2 -#define CLKPS3 3 -#define CLKPCE 7 - -#define PRR _SFR_MEM8(0x64) -#define PRADC 0 -#define PRUSART0 1 -#define PRSPI 2 -#define PRTIM1 3 -#define PRLCD 4 - -#define __AVR_HAVE_PRR ((1< instead of this file." -#endif - -#ifndef _AVR_IOXXX_H_ -# define _AVR_IOXXX_H_ "iom64a.h" -#else -# error "Attempt to include more than one file." -#endif - -/* Registers and associated bit numbers */ - -#define PINF _SFR_IO8(0x00) -#define PINF7 7 -#define PINF6 6 -#define PINF5 5 -#define PINF4 4 -#define PINF3 3 -#define PINF2 2 -#define PINF1 1 -#define PINF0 0 - -#define PINE _SFR_IO8(0x01) -#define PINE7 7 -#define PINE6 6 -#define PINE5 5 -#define PINE4 4 -#define PINE3 3 -#define PINE2 2 -#define PINE1 1 -#define PINE0 0 - -#define DDRE _SFR_IO8(0x02) -#define DDRE7 7 -// Inserted "DDE7" from "DDRE7" due to compatibility -#define DDE7 7 -#define DDRE6 6 -// Inserted "DDE6" from "DDRE6" due to compatibility -#define DDE6 6 -#define DDRE5 5 -// Inserted "DDE5" from "DDRE5" due to compatibility -#define DDE5 5 -#define DDRE4 4 -// Inserted "DDE4" from "DDRE4" due to compatibility -#define DDE4 4 -#define DDRE3 3 -// Inserted "DDE3" from "DDRE3" due to compatibility -#define DDE3 3 -#define DDRE2 2 -// Inserted "DDE2" from "DDRE2" due to compatibility -#define DDE2 2 -#define DDRE1 1 -// Inserted "DDE1" from "DDRE1" due to compatibility -#define DDE1 1 -#define DDRE0 0 -// Inserted "DDE0" from "DDRE0" due to compatibility -#define DDE0 0 - -#define PORTE _SFR_IO8(0x03) -#define PORTE7 7 -#define PORTE6 6 -#define PORTE5 5 -#define PORTE4 4 -#define PORTE3 3 -#define PORTE2 2 -#define PORTE1 1 -#define PORTE0 0 - -/* Combine ADCL and ADCH */ -#ifndef __ASSEMBLER__ -#define ADC _SFR_IO16(0x04) -#endif -#define ADCW _SFR_IO16(0x04) - -#define ADCL _SFR_IO8(0x04) -#define ADCH _SFR_IO8(0x05) - -#define ADCSRA _SFR_IO8(0x06) -#define ADPS0 0 -#define ADPS1 1 -#define ADPS2 2 -#define ADIE 3 -#define ADIF 4 -#define ADATE 5 -#define ADSC 6 -#define ADEN 7 - -#define ADMUX _SFR_IO8(0x07) -#define MUX0 0 -#define MUX1 1 -#define MUX2 2 -#define MUX3 3 -#define MUX4 4 -#define ADLAR 5 -#define REFS0 6 -#define REFS1 7 - -#define ACSR _SFR_IO8(0x08) -#define ACIS0 0 -#define ACIS1 1 -#define ACIC 2 -#define ACIE 3 -#define ACI 4 -#define ACO 5 -#define ACBG 6 -#define ACD 7 - -#define UBRR0L _SFR_IO8(0x09) - -#define UCSR0B _SFR_IO8(0x0A) -#define TXB80 0 -#define RXB80 1 -#define UCSZ02 2 -#define TXEN0 3 -#define RXEN0 4 -#define UDRIE0 5 -#define TXCIE0 6 -#define RXCIE0 7 - -#define UCSR0A _SFR_IO8(0x0B) -#define MPCM0 0 -#define U2X0 1 -#define UPE0 2 -#define DOR0 3 -#define FE0 4 -#define UDRE0 5 -#define TXC0 6 -#define RXC0 7 - -#define UDR0 _SFR_IO8(0x0C) - -#define SPCR _SFR_IO8(0x0D) -#define SPR0 0 -#define SPR1 1 -#define CPHA 2 -#define CPOL 3 -#define MSTR 4 -#define DORD 5 -#define SPE 6 -#define SPIE 7 - -#define SPSR _SFR_IO8(0x0E) -#define SPI2X 0 -#define WCOL 6 -#define SPIF 7 - -#define SPDR _SFR_IO8(0x0F) - -#define PIND _SFR_IO8(0x10) -#define PIND7 7 -#define PIND6 6 -#define PIND5 5 -#define PIND4 4 -#define PIND3 3 -#define PIND2 2 -#define PIND1 1 -#define PIND0 0 - -#define DDRD _SFR_IO8(0x11) -#define DDRD7 7 -// Inserted "DDD7" from "DDRD7" due to compatibility -#define DDD7 7 -#define DDRD6 6 -// Inserted "DDD6" from "DDRD6" due to compatibility -#define DDD6 6 -#define DDRD5 5 -// Inserted "DDD5" from "DDRD5" due to compatibility -#define DDD5 5 -#define DDRD4 4 -// Inserted "DDD4" from "DDRD4" due to compatibility -#define DDD4 4 -#define DDRD3 3 -// Inserted "DDD3" from "DDRD3" due to compatibility -#define DDD3 3 -#define DDRD2 2 -// Inserted "DDD2" from "DDRD2" due to compatibility -#define DDD2 2 -#define DDRD1 1 -// Inserted "DDD1" from "DDRD1" due to compatibility -#define DDD1 1 -#define DDRD0 0 -// Inserted "DDD0" from "DDRD0" due to compatibility -#define DDD0 0 - -#define PORTD _SFR_IO8(0x12) -#define PORTD7 7 -#define PORTD6 6 -#define PORTD5 5 -#define PORTD4 4 -#define PORTD3 3 -#define PORTD2 2 -#define PORTD1 1 -#define PORTD0 0 - -#define PINC _SFR_IO8(0x13) -#define PINC7 7 -#define PINC6 6 -#define PINC5 5 -#define PINC4 4 -#define PINC3 3 -#define PINC2 2 -#define PINC1 1 -#define PINC0 0 - -#define DDRC _SFR_IO8(0x14) -#define DDRC7 7 -// Inserted "DDC7" from "DDRC7" due to compatibility -#define DDC7 7 -#define DDRC6 6 -// Inserted "DDC6" from "DDRC6" due to compatibility -#define DDC6 6 -#define DDRC5 5 -// Inserted "DDC5" from "DDRC5" due to compatibility -#define DDC5 5 -#define DDRC4 4 -// Inserted "DDC4" from "DDRC4" due to compatibility -#define DDC4 4 -#define DDRC3 3 -// Inserted "DDC3" from "DDRC3" due to compatibility -#define DDC3 3 -#define DDRC2 2 -// Inserted "DDC2" from "DDRC2" due to compatibility -#define DDC2 2 -#define DDRC1 1 -// Inserted "DDC1" from "DDRC1" due to compatibility -#define DDC1 1 -#define DDRC0 0 -// Inserted "DDC0" from "DDRC0" due to compatibility -#define DDC0 0 - -#define PORTC _SFR_IO8(0x15) -#define PORTC7 7 -#define PORTC6 6 -#define PORTC5 5 -#define PORTC4 4 -#define PORTC3 3 -#define PORTC2 2 -#define PORTC1 1 -#define PORTC0 0 - -#define PINB _SFR_IO8(0x16) -#define PINB7 7 -#define PINB6 6 -#define PINB5 5 -#define PINB4 4 -#define PINB3 3 -#define PINB2 2 -#define PINB1 1 -#define PINB0 0 - -#define DDRB _SFR_IO8(0x17) -#define DDRB7 7 -// Inserted "DDB7" from "DDRB7" due to compatibility -#define DDB7 7 -#define DDRB6 6 -// Inserted "DDB6" from "DDRB6" due to compatibility -#define DDB6 6 -#define DDRB5 5 -// Inserted "DDB5" from "DDRB5" due to compatibility -#define DDB5 5 -#define DDRB4 4 -// Inserted "DDB4" from "DDRB4" due to compatibility -#define DDB4 4 -#define DDRB3 3 -// Inserted "DDB3" from "DDRB3" due to compatibility -#define DDB3 3 -#define DDRB2 2 -// Inserted "DDB2" from "DDRB2" due to compatibility -#define DDB2 2 -#define DDRB1 1 -// Inserted "DDB1" from "DDRB1" due to compatibility -#define DDB1 1 -#define DDRB0 0 -// Inserted "DDB0" from "DDRB0" due to compatibility -#define DDB0 0 - -#define PORTB _SFR_IO8(0x18) -#define PORTB7 7 -#define PORTB6 6 -#define PORTB5 5 -#define PORTB4 4 -#define PORTB3 3 -#define PORTB2 2 -#define PORTB1 1 -#define PORTB0 0 - -#define PINA _SFR_IO8(0x19) -#define PINA7 7 -#define PINA6 6 -#define PINA5 5 -#define PINA4 4 -#define PINA3 3 -#define PINA2 2 -#define PINA1 1 -#define PINA0 0 - -#define DDRA _SFR_IO8(0x1A) -#define DDRA7 7 -// Inserted "DDA7" from "DDRA7" due to compatibility -#define DDA7 7 -#define DDRA6 6 -// Inserted "DDA6" from "DDRA6" due to compatibility -#define DDA6 6 -#define DDRA5 5 -// Inserted "DDA5" from "DDRA5" due to compatibility -#define DDA5 5 -#define DDRA4 4 -// Inserted "DDA4" from "DDRA4" due to compatibility -#define DDA4 4 -#define DDRA3 3 -// Inserted "DDA3" from "DDRA3" due to compatibility -#define DDA3 3 -#define DDRA2 2 -// Inserted "DDA2" from "DDRA2" due to compatibility -#define DDA2 2 -#define DDRA1 1 -// Inserted "DDA1" from "DDRA1" due to compatibility -#define DDA1 1 -#define DDRA0 0 -// Inserted "DDA0" from "DDRA0" due to compatibility -#define DDA0 0 - -#define PORTA _SFR_IO8(0x1B) -#define PORTA7 7 -#define PORTA6 6 -#define PORTA5 5 -#define PORTA4 4 -#define PORTA3 3 -#define PORTA2 2 -#define PORTA1 1 -#define PORTA0 0 - -#define EECR _SFR_IO8(0x1C) -#define EERE 0 -#define EEWE 1 -#define EEMWE 2 -#define EERIE 3 - -#define EEDR _SFR_IO8(0x1D) - -/* Combine EEARL and EEARH */ -#define EEAR _SFR_IO16(0x1E) - -#define EEARL _SFR_IO8(0x1E) -#define EEARH _SFR_IO8(0x1F) - -#define SFIOR _SFR_IO8(0x20) -#define ACME 3 -#define PSR321 0 -#define PSR0 1 -#define PUD 2 -#define TSM 7 - -#define WDTCR _SFR_IO8(0x21) -#define WDP0 0 -#define WDP1 1 -#define WDP2 2 -#define WDE 3 -#define WDCE 4 - -#define OCDR _SFR_IO8(0x22) -#define OCDR0 0 -#define OCDR1 1 -#define OCDR2 2 -#define OCDR3 3 -#define OCDR4 4 -#define OCDR5 5 -#define OCDR6 6 -#define OCDR7 7 - -#define OCR2 _SFR_IO8(0x23) - -#define TCNT2 _SFR_IO8(0x24) - -#define TCCR2 _SFR_IO8(0x25) -#define CS20 0 -#define CS21 1 -#define CS22 2 -#define WGM21 3 -#define COM20 4 -#define COM21 5 -#define WGM20 6 -#define FOC2 7 - -/* Combine ICR1L and ICR1H */ -#define ICR1 _SFR_IO16(0x26) - -#define ICR1L _SFR_IO8(0x26) -#define ICR1H _SFR_IO8(0x27) - -/* Combine OCR1BL and OCR1BH */ -#define OCR1B _SFR_IO16(0x28) - -#define OCR1BL _SFR_IO8(0x28) -#define OCR1BH _SFR_IO8(0x29) - -/* Combine OCR1AL and OCR1AH */ -#define OCR1A _SFR_IO16(0x2A) - -#define OCR1AL _SFR_IO8(0x2A) -#define OCR1AH _SFR_IO8(0x2B) - -/* Combine TCNT1L and TCNT1H */ -#define TCNT1 _SFR_IO16(0x2C) - -#define TCNT1L _SFR_IO8(0x2C) -#define TCNT1H _SFR_IO8(0x2D) - -#define TCCR1B _SFR_IO8(0x2E) -#define CS10 0 -#define CS11 1 -#define CS12 2 -#define WGM12 3 -#define WGM13 4 -#define ICES1 6 -#define ICNC1 7 - -#define TCCR1A _SFR_IO8(0x2F) -#define WGM10 0 -#define WGM11 1 -#define COM1C0 2 -#define COM1C1 3 -#define COM1B0 4 -#define COM1B1 5 -#define COM1A0 6 -#define COM1A1 7 - -#define ASSR _SFR_IO8(0x30) -#define TCR0UB 0 -#define OCR0UB 1 -#define TCN0UB 2 -#define AS0 3 - -#define OCR0 _SFR_IO8(0x31) - -#define TCNT0 _SFR_IO8(0x32) - -#define TCCR0 _SFR_IO8(0x33) -#define CS00 0 -#define CS01 1 -#define CS02 2 -#define WGM01 3 -#define COM00 4 -#define COM01 5 -#define WGM00 6 -#define FOC0 7 - -#define MCUCSR _SFR_IO8(0x34) -#define PORF 0 -#define EXTRF 1 -#define BORF 2 -#define WDRF 3 -#define JTRF 4 -#define JTD 7 - -#define MCUCR _SFR_IO8(0x35) -#define IVCE 0 -#define IVSEL 1 -#define SM2 2 -#define SM0 3 -#define SM1 4 -#define SE 5 -#define SRW10 6 -#define SRE 7 - -#define TIFR _SFR_IO8(0x36) -#define TOV0 0 -#define OCF0 1 -#define TOV1 2 -#define OCF1B 3 -#define OCF1A 4 -#define ICF1 5 -#define TOV2 6 -#define OCF2 7 - -#define TIMSK _SFR_IO8(0x37) -#define TOIE0 0 -#define OCIE0 1 -#define TOIE1 2 -#define OCIE1B 3 -#define OCIE1A 4 -#define TICIE1 5 -#define TOIE2 6 -#define OCIE2 7 - -#define EIFR _SFR_IO8(0x38) -#define INTF0 0 -#define INTF1 1 -#define INTF2 2 -#define INTF3 3 -#define INTF4 4 -#define INTF5 5 -#define INTF6 6 -#define INTF7 7 - -#define EIMSK _SFR_IO8(0x39) -#define INT0 0 -#define INT1 1 -#define INT2 2 -#define INT3 3 -#define INT4 4 -#define INT5 5 -#define INT6 6 -#define INT7 7 - -#define EICRB _SFR_IO8(0x3A) -#define ISC40 0 -#define ISC41 1 -#define ISC50 2 -#define ISC51 3 -#define ISC60 4 -#define ISC61 5 -#define ISC70 6 -#define ISC71 7 - -/* Reserved [0x3B] */ - -#define XDIV _SFR_IO8(0x3C) -#define XDIV0 0 -#define XDIV1 1 -#define XDIV2 2 -#define XDIV3 3 -#define XDIV4 4 -#define XDIV5 5 -#define XDIV6 6 -#define XDIVEN 7 - -/* SP [0x3D..0x3E] */ - -/* SREG [0x3F] */ - -/* Reserved [0x40..0x60] */ - -#define DDRF _SFR_MEM8(0x61) -#define DDRF7 7 -// Inserted "DDF7" from "DDRF7" due to compatibility -#define DDF7 7 -#define DDRF6 6 -// Inserted "DDF6" from "DDRF6" due to compatibility -#define DDF6 6 -#define DDRF5 5 -// Inserted "DDF5" from "DDRF5" due to compatibility -#define DDF5 5 -#define DDRF4 4 -// Inserted "DDF4" from "DDRF4" due to compatibility -#define DDF4 4 -#define DDRF3 3 -// Inserted "DDF3" from "DDRF3" due to compatibility -#define DDF3 3 -#define DDRF2 2 -// Inserted "DDF2" from "DDRF2" due to compatibility -#define DDF2 2 -#define DDRF1 1 -// Inserted "DDF1" from "DDRF1" due to compatibility -#define DDF1 1 -#define DDRF0 0 -// Inserted "DDF0" from "DDRF0" due to compatibility -#define DDF0 0 - -#define PORTF _SFR_MEM8(0x62) -#define PORTF7 7 -#define PORTF6 6 -#define PORTF5 5 -#define PORTF4 4 -#define PORTF3 3 -#define PORTF2 2 -#define PORTF1 1 -#define PORTF0 0 - -#define PING _SFR_MEM8(0x63) -#define PING4 4 -#define PING3 3 -#define PING2 2 -#define PING1 1 -#define PING0 0 - -#define DDRG _SFR_MEM8(0x64) -#define DDRG4 4 -// Inserted "DDG4" from "DDRG4" due to compatibility -#define DDG4 4 -#define DDRG3 3 -// Inserted "DDG3" from "DDRG3" due to compatibility -#define DDG3 3 -#define DDRG2 2 -// Inserted "DDG2" from "DDRG2" due to compatibility -#define DDG2 2 -#define DDRG1 1 -// Inserted "DDG1" from "DDRG1" due to compatibility -#define DDG1 1 -#define DDRG0 0 -// Inserted "DDG0" from "DDRG0" due to compatibility -#define DDG0 0 - -#define PORTG _SFR_MEM8(0x65) -#define PORTG4 4 -#define PORTG3 3 -#define PORTG2 2 -#define PORTG1 1 -#define PORTG0 0 - -/* Reserved [0x66..0x67] */ - -#define SPMCSR _SFR_MEM8(0x68) -#define SPMEN 0 -#define PGERS 1 -#define PGWRT 2 -#define BLBSET 3 -#define RWWSRE 4 -#define RWWSB 6 -#define SPMIE 7 - -/* Reserved [0x69] */ - -#define EICRA _SFR_MEM8(0x6A) -#define ISC00 0 -#define ISC01 1 -#define ISC10 2 -#define ISC11 3 -#define ISC20 4 -#define ISC21 5 -#define ISC30 6 -#define ISC31 7 - -/* Reserved [0x6B] */ - -#define XMCRB _SFR_MEM8(0x6C) -#define XMM0 0 -#define XMM1 1 -#define XMM2 2 -#define XMBK 7 - -#define XMCRA _SFR_MEM8(0x6D) -#define SRW11 1 -#define SRW00 2 -#define SRW01 3 -#define SRL0 4 -#define SRL1 5 -#define SRL2 6 - -/* Reserved [0x6E] */ - -#define OSCCAL _SFR_MEM8(0x6F) -#define OSCCAL0 0 -#define OSCCAL1 1 -#define OSCCAL2 2 -#define OSCCAL3 3 -#define OSCCAL4 4 -#define OSCCAL5 5 -#define OSCCAL6 6 -#define OSCCAL7 7 - -#define TWBR _SFR_MEM8(0x70) - -#define TWSR _SFR_MEM8(0x71) -#define TWPS0 0 -#define TWPS1 1 -#define TWS3 3 -#define TWS4 4 -#define TWS5 5 -#define TWS6 6 -#define TWS7 7 - -#define TWAR _SFR_MEM8(0x72) -#define TWGCE 0 -#define TWA0 1 -#define TWA1 2 -#define TWA2 3 -#define TWA3 4 -#define TWA4 5 -#define TWA5 6 -#define TWA6 7 - -#define TWDR _SFR_MEM8(0x73) - -#define TWCR _SFR_MEM8(0x74) -#define TWIE 0 -#define TWEN 2 -#define TWWC 3 -#define TWSTO 4 -#define TWSTA 5 -#define TWEA 6 -#define TWINT 7 - -/* Reserved [0x75..0x77] */ - -/* Combine OCR1CL and OCR1CH */ -#define OCR1C _SFR_MEM16(0x78) - -#define OCR1CL _SFR_MEM8(0x78) -#define OCR1CH _SFR_MEM8(0x79) - -#define TCCR1C _SFR_MEM8(0x7A) -#define FOC1C 5 -#define FOC1B 6 -#define FOC1A 7 - -/* Reserved [0x7B] */ - -#define ETIFR _SFR_MEM8(0x7C) -#define OCF1C 0 -#define OCF3C 1 -#define TOV3 2 -#define OCF3B 3 -#define OCF3A 4 -#define ICF3 5 - -#define ETIMSK _SFR_MEM8(0x7D) -#define OCIE1C 0 -#define OCIE3C 1 -#define TOIE3 2 -#define OCIE3B 3 -#define OCIE3A 4 -#define TICIE3 5 - -/* Reserved [0x7E..0x7F] */ - -/* Combine ICR3L and ICR3H */ -#define ICR3 _SFR_MEM16(0x80) - -#define ICR3L _SFR_MEM8(0x80) -#define ICR3H _SFR_MEM8(0x81) - -/* Combine OCR3CL and OCR3CH */ -#define OCR3C _SFR_MEM16(0x82) - -#define OCR3CL _SFR_MEM8(0x82) -#define OCR3CH _SFR_MEM8(0x83) - -/* Combine OCR3BL and OCR3BH */ -#define OCR3B _SFR_MEM16(0x84) - -#define OCR3BL _SFR_MEM8(0x84) -#define OCR3BH _SFR_MEM8(0x85) - -/* Combine OCR3AL and OCR3AH */ -#define OCR3A _SFR_MEM16(0x86) - -#define OCR3AL _SFR_MEM8(0x86) -#define OCR3AH _SFR_MEM8(0x87) - -/* Combine TCNT3L and TCNT3H */ -#define TCNT3 _SFR_MEM16(0x88) - -#define TCNT3L _SFR_MEM8(0x88) -#define TCNT3H _SFR_MEM8(0x89) - -#define TCCR3B _SFR_MEM8(0x8A) -#define CS30 0 -#define CS31 1 -#define CS32 2 -#define WGM32 3 -#define WGM33 4 -#define ICES3 6 -#define ICNC3 7 - -#define TCCR3A _SFR_MEM8(0x8B) -#define WGM30 0 -#define WGM31 1 -#define COM3C0 2 -#define COM3C1 3 -#define COM3B0 4 -#define COM3B1 5 -#define COM3A0 6 -#define COM3A1 7 - -#define TCCR3C _SFR_MEM8(0x8C) -#define FOC3C 5 -#define FOC3B 6 -#define FOC3A 7 - -/* Reserved [0x8D] */ - -#define ADCSRB _SFR_MEM8(0x8E) -#define ADTS0 0 -#define ADTS1 1 -#define ADTS2 2 - -/* Reserved [0x8F] */ - -#define UBRR0H _SFR_MEM8(0x90) - -/* Reserved [0x91..0x94] */ - -#define UCSR0C _SFR_MEM8(0x95) -#define UCPOL0 0 -#define UCSZ00 1 -#define UCSZ01 2 -#define USBS0 3 -#define UPM00 4 -#define UPM01 5 -#define UMSEL0 6 - -/* Reserved [0x96..0x97] */ - -#define UBRR1H _SFR_MEM8(0x98) - -#define UBRR1L _SFR_MEM8(0x99) - -#define UCSR1B _SFR_MEM8(0x9A) -#define TXB81 0 -#define RXB81 1 -#define UCSZ12 2 -#define TXEN1 3 -#define RXEN1 4 -#define UDRIE1 5 -#define TXCIE1 6 -#define RXCIE1 7 - -#define UCSR1A _SFR_MEM8(0x9B) -#define MPCM1 0 -#define U2X1 1 -#define UPE1 2 -#define DOR1 3 -#define FE1 4 -#define UDRE1 5 -#define TXC1 6 -#define RXC1 7 - -#define UDR1 _SFR_MEM8(0x9C) - -#define UCSR1C _SFR_MEM8(0x9D) -#define UCPOL1 0 -#define UCSZ10 1 -#define UCSZ11 2 -#define USBS1 3 -#define UPM10 4 -#define UPM11 5 -#define UMSEL1 6 - - - -/* Values and associated defines */ - - -#define SLEEP_MODE_IDLE (0x00<<2) -#define SLEEP_MODE_ADC (0x02<<2) -#define SLEEP_MODE_PWR_DOWN (0x04<<2) -#define SLEEP_MODE_PWR_SAVE (0x06<<2) -#define SLEEP_MODE_STANDBY (0x05<<2) -#define SLEEP_MODE_EXT_STANDBY (0x07<<2) - -/* Interrupt vectors */ -/* Vector 0 is the reset vector */ -/* External Interrupt Request 0 */ -#define INT0_vect _VECTOR(1) -#define INT0_vect_num 1 - -/* External Interrupt Request 1 */ -#define INT1_vect _VECTOR(2) -#define INT1_vect_num 2 - -/* External Interrupt Request 2 */ -#define INT2_vect _VECTOR(3) -#define INT2_vect_num 3 - -/* External Interrupt Request 3 */ -#define INT3_vect _VECTOR(4) -#define INT3_vect_num 4 - -/* External Interrupt Request 4 */ -#define INT4_vect _VECTOR(5) -#define INT4_vect_num 5 - -/* External Interrupt Request 5 */ -#define INT5_vect _VECTOR(6) -#define INT5_vect_num 6 - -/* External Interrupt Request 6 */ -#define INT6_vect _VECTOR(7) -#define INT6_vect_num 7 - -/* External Interrupt Request 7 */ -#define INT7_vect _VECTOR(8) -#define INT7_vect_num 8 - -/* Timer/Counter2 Compare Match */ -#define TIMER2_COMP_vect _VECTOR(9) -#define TIMER2_COMP_vect_num 9 - -/* Timer/Counter2 Overflow */ -#define TIMER2_OVF_vect _VECTOR(10) -#define TIMER2_OVF_vect_num 10 - -/* Timer/Counter1 Capture Event */ -#define TIMER1_CAPT_vect _VECTOR(11) -#define TIMER1_CAPT_vect_num 11 - -/* Timer/Counter1 Compare Match A */ -#define TIMER1_COMPA_vect _VECTOR(12) -#define TIMER1_COMPA_vect_num 12 - -/* Timer/Counter Compare Match B */ -#define TIMER1_COMPB_vect _VECTOR(13) -#define TIMER1_COMPB_vect_num 13 - -/* Timer/Counter1 Overflow */ -#define TIMER1_OVF_vect _VECTOR(14) -#define TIMER1_OVF_vect_num 14 - -/* Timer/Counter0 Compare Match */ -#define TIMER0_COMP_vect _VECTOR(15) -#define TIMER0_COMP_vect_num 15 - -/* Timer/Counter0 Overflow */ -#define TIMER0_OVF_vect _VECTOR(16) -#define TIMER0_OVF_vect_num 16 - -/* SPI Serial Transfer Complete */ -#define SPI_STC_vect _VECTOR(17) -#define SPI_STC_vect_num 17 - -/* USART0, Rx Complete */ -#define USART0_RX_vect _VECTOR(18) -#define USART0_RX_vect_num 18 - -/* USART0 Data Register Empty */ -#define USART0_UDRE_vect _VECTOR(19) -#define USART0_UDRE_vect_num 19 - -/* USART0, Tx Complete */ -#define USART0_TX_vect _VECTOR(20) -#define USART0_TX_vect_num 20 - -/* ADC Conversion Complete */ -#define ADC_vect _VECTOR(21) -#define ADC_vect_num 21 - -/* EEPROM Ready */ -#define EE_READY_vect _VECTOR(22) -#define EE_READY_vect_num 22 - -/* Analog Comparator */ -#define ANALOG_COMP_vect _VECTOR(23) -#define ANALOG_COMP_vect_num 23 - -/* Timer/Counter1 Compare Match C */ -#define TIMER1_COMPC_vect _VECTOR(24) -#define TIMER1_COMPC_vect_num 24 - -/* Timer/Counter3 Capture Event */ -#define TIMER3_CAPT_vect _VECTOR(25) -#define TIMER3_CAPT_vect_num 25 - -/* Timer/Counter3 Compare Match A */ -#define TIMER3_COMPA_vect _VECTOR(26) -#define TIMER3_COMPA_vect_num 26 - -/* Timer/Counter3 Compare Match B */ -#define TIMER3_COMPB_vect _VECTOR(27) -#define TIMER3_COMPB_vect_num 27 - -/* Timer/Counter3 Compare Match C */ -#define TIMER3_COMPC_vect _VECTOR(28) -#define TIMER3_COMPC_vect_num 28 - -/* Timer/Counter3 Overflow */ -#define TIMER3_OVF_vect _VECTOR(29) -#define TIMER3_OVF_vect_num 29 - -/* USART1, Rx Complete */ -#define USART1_RX_vect _VECTOR(30) -#define USART1_RX_vect_num 30 - -/* USART1, Data Register Empty */ -#define USART1_UDRE_vect _VECTOR(31) -#define USART1_UDRE_vect_num 31 - -/* USART1, Tx Complete */ -#define USART1_TX_vect _VECTOR(32) -#define USART1_TX_vect_num 32 - -/* 2-wire Serial Interface */ -#define TWI_vect _VECTOR(33) -#define TWI_vect_num 33 - -/* Store Program Memory Read */ -#define SPM_READY_vect _VECTOR(34) -#define SPM_READY_vect_num 34 - -#define _VECTORS_SIZE 140 - - -/* Constants */ - -#define SPM_PAGESIZE 256 -#define FLASHSTART 0x0000 -#define FLASHEND 0xFFFF -#define RAMSTART 0x0100 -#define RAMSIZE 4096 -#define RAMEND 0x10FF -#define E2START 0 -#define E2SIZE 2048 -#define E2PAGESIZE 8 -#define E2END 0x07FF -#define XRAMEND RAMEND - - -/* Fuses */ - -#define FUSE_MEMORY_SIZE 3 - -/* Low Fuse Byte */ -#define FUSE_SUT_CKSEL0 (unsigned char)~_BV(0) -#define FUSE_SUT_CKSEL1 (unsigned char)~_BV(1) -#define FUSE_SUT_CKSEL2 (unsigned char)~_BV(2) -#define FUSE_SUT_CKSEL3 (unsigned char)~_BV(3) -#define FUSE_SUT_CKSEL4 (unsigned char)~_BV(4) -#define FUSE_SUT_CKSEL5 (unsigned char)~_BV(5) -#define FUSE_BODEN (unsigned char)~_BV(6) -#define FUSE_BODLEVEL (unsigned char)~_BV(7) -#define LFUSE_DEFAULT (FUSE_SUT_CKSEL1 & FUSE_SUT_CKSEL2 & FUSE_SUT_CKSEL3 & FUSE_SUT_CKSEL4) - - -/* High Fuse Byte */ -#define FUSE_BOOTRST (unsigned char)~_BV(0) -#define FUSE_BOOTSZ0 (unsigned char)~_BV(1) -#define FUSE_BOOTSZ1 (unsigned char)~_BV(2) -#define FUSE_EESAVE (unsigned char)~_BV(3) -#define FUSE_CKOPT (unsigned char)~_BV(4) -#define FUSE_SPIEN (unsigned char)~_BV(5) -#define FUSE_JTAGEN (unsigned char)~_BV(6) -#define FUSE_OCDEN (unsigned char)~_BV(7) -#define HFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_SPIEN & FUSE_JTAGEN) - - -/* Extended Fuse Byte */ -#define FUSE_WDTON (unsigned char)~_BV(0) -#define FUSE_CompMode (unsigned char)~_BV(1) -#define EFUSE_DEFAULT (FUSE_CompMode) - - - -/* Lock Bits */ -#define __LOCK_BITS_EXIST -#define __BOOT_LOCK_BITS_0_EXIST -#define __BOOT_LOCK_BITS_1_EXIST - - -/* Signature */ -#define SIGNATURE_0 0x1E -#define SIGNATURE_1 0x96 -#define SIGNATURE_2 0x02 - - -#endif /* #ifdef _AVR_ATMEGA64A_H_INCLUDED */ - diff --git a/arduino/hardware/tools/avr/avr/include/avr/iom64c1.h b/arduino/hardware/tools/avr/avr/include/avr/iom64c1.h deleted file mode 100644 index c685341..0000000 --- a/arduino/hardware/tools/avr/avr/include/avr/iom64c1.h +++ /dev/null @@ -1,1321 +0,0 @@ -/* Copyright (c) 2009 Atmel Corporation - All rights reserved. - - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - * Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - * Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in - the documentation and/or other materials provided with the - distribution. - - * Neither the name of the copyright holders nor the names of - contributors may be used to endorse or promote products derived - from this software without specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. */ - -/* $Id: iom64c1.h 2183 2010-09-21 05:37:46Z aboyapati $ */ - -/* avr/iom64c1.h - definitions for ATmega64C1 */ - -/* This file should only be included from , never directly. */ - -#ifndef _AVR_IO_H_ -# error "Include instead of this file." -#endif - -#ifndef _AVR_IOXXX_H_ -# define _AVR_IOXXX_H_ "iom64c1.h" -#else -# error "Attempt to include more than one file." -#endif - - -#ifndef _AVR_ATmega64C1_H_ -#define _AVR_ATmega64C1_H_ 1 - - -/* Registers and associated bit numbers. */ - -#define PINB _SFR_IO8(0x03) -#define PINB0 0 -#define PINB1 1 -#define PINB2 2 -#define PINB3 3 -#define PINB4 4 -#define PINB5 5 -#define PINB6 6 -#define PINB7 7 - -#define DDRB _SFR_IO8(0x04) -#define DDB0 0 -#define DDB1 1 -#define DDB2 2 -#define DDB3 3 -#define DDB4 4 -#define DDB5 5 -#define DDB6 6 -#define DDB7 7 - -#define PORTB _SFR_IO8(0x05) -#define PORTB0 0 -#define PORTB1 1 -#define PORTB2 2 -#define PORTB3 3 -#define PORTB4 4 -#define PORTB5 5 -#define PORTB6 6 -#define PORTB7 7 - -#define PINC _SFR_IO8(0x06) -#define PINC0 0 -#define PINC1 1 -#define PINC2 2 -#define PINC3 3 -#define PINC4 4 -#define PINC5 5 -#define PINC6 6 -#define PINC7 7 - -#define DDRC _SFR_IO8(0x07) -#define DDC0 0 -#define DDC1 1 -#define DDC2 2 -#define DDC3 3 -#define DDC4 4 -#define DDC5 5 -#define DDC6 6 -#define DDC7 7 - -#define PORTC _SFR_IO8(0x08) -#define PORTC0 0 -#define PORTC1 1 -#define PORTC2 2 -#define PORTC3 3 -#define PORTC4 4 -#define PORTC5 5 -#define PORTC6 6 -#define PORTC7 7 - -#define PIND _SFR_IO8(0x09) -#define PIND0 0 -#define PIND1 1 -#define PIND2 2 -#define PIND3 3 -#define PIND4 4 -#define PIND5 5 -#define PIND6 6 -#define PIND7 7 - -#define DDRD _SFR_IO8(0x0A) -#define DDD0 0 -#define DDD1 1 -#define DDD2 2 -#define DDD3 3 -#define DDD4 4 -#define DDD5 5 -#define DDD6 6 -#define DDD7 7 - -#define PORTD _SFR_IO8(0x0B) -#define PORTD0 0 -#define PORTD1 1 -#define PORTD2 2 -#define PORTD3 3 -#define PORTD4 4 -#define PORTD5 5 -#define PORTD6 6 -#define PORTD7 7 - -#define PINE _SFR_IO8(0x0C) -#define PINE0 0 -#define PINE1 1 -#define PINE2 2 - -#define DDRE _SFR_IO8(0x0D) -#define DDE0 0 -#define DDE1 1 -#define DDE2 2 - -#define PORTE _SFR_IO8(0x0E) -#define PORTE0 0 -#define PORTE1 1 -#define PORTE2 2 - -#define TIFR0 _SFR_IO8(0x15) -#define TOV0 0 -#define OCF0A 1 -#define OCF0B 2 - -#define TIFR1 _SFR_IO8(0x16) -#define TOV1 0 -#define OCF1A 1 -#define OCF1B 2 -#define ICF1 5 - -#define GPIOR1 _SFR_IO8(0x19) -#define GPIOR10 0 -#define GPIOR11 1 -#define GPIOR12 2 -#define GPIOR13 3 -#define GPIOR14 4 -#define GPIOR15 5 -#define GPIOR16 6 -#define GPIOR17 7 - -#define GPIOR2 _SFR_IO8(0x1A) -#define GPIOR20 0 -#define GPIOR21 1 -#define GPIOR22 2 -#define GPIOR23 3 -#define GPIOR24 4 -#define GPIOR25 5 -#define GPIOR26 6 -#define GPIOR27 7 - -#define PCIFR _SFR_IO8(0x1B) -#define PCIF0 0 -#define PCIF1 1 -#define PCIF2 2 -#define PCIF3 3 - -#define EIFR _SFR_IO8(0x1C) -#define INTF0 0 -#define INTF1 1 -#define INTF2 2 -#define INTF3 3 - -#define EIMSK _SFR_IO8(0x1D) -#define INT0 0 -#define INT1 1 -#define INT2 2 -#define INT3 3 - -#define GPIOR0 _SFR_IO8(0x1E) -#define GPIOR00 0 -#define GPIOR01 1 -#define GPIOR02 2 -#define GPIOR03 3 -#define GPIOR04 4 -#define GPIOR05 5 -#define GPIOR06 6 -#define GPIOR07 7 - -#define EECR _SFR_IO8(0x1F) -#define EERE 0 -#define EEWE 1 -#define EEMWE 2 -#define EERIE 3 -#define EEPM0 4 -#define EEPM1 5 - -#define EEDR _SFR_IO8(0x20) -#define EEDR0 0 -#define EEDR1 1 -#define EEDR2 2 -#define EEDR3 3 -#define EEDR4 4 -#define EEDR5 5 -#define EEDR6 6 -#define EEDR7 7 - -#define EEAR _SFR_IO16(0x21) - -#define EEARL _SFR_IO8(0x21) -#define EEAR0 0 -#define EEAR1 1 -#define EEAR2 2 -#define EEAR3 3 -#define EEAR4 4 -#define EEAR5 5 -#define EEAR6 6 -#define EEAR7 7 - -#define EEARH _SFR_IO8(0x22) -#define EEAR8 0 -#define EEAR9 1 -#define EEAR10 2 - -#define GTCCR _SFR_IO8(0x23) -#define PSR10 0 -#define PSRSYNC 0 -#define ICPSEL1 6 -#define TSM 7 - -#define TCCR0A _SFR_IO8(0x24) -#define WGM00 0 -#define WGM01 1 -#define COM0B0 4 -#define COM0B1 5 -#define COM0A0 6 -#define COM0A1 7 - -#define TCCR0B _SFR_IO8(0x25) -#define CS00 0 -#define CS01 1 -#define CS02 2 -#define WGM02 3 -#define FOC0B 6 -#define FOC0A 7 - -#define TCNT0 _SFR_IO8(0x26) -#define TCNT0_0 0 -#define TCNT0_1 1 -#define TCNT0_2 2 -#define TCNT0_3 3 -#define TCNT0_4 4 -#define TCNT0_5 5 -#define TCNT0_6 6 -#define TCNT0_7 7 - -#define OCR0A _SFR_IO8(0x27) -#define OCR0A_0 0 -#define OCR0A_1 1 -#define OCR0A_2 2 -#define OCR0A_3 3 -#define OCR0A_4 4 -#define OCR0A_5 5 -#define OCR0A_6 6 -#define OCR0A_7 7 - -#define OCR0B _SFR_IO8(0x28) -#define OCR0B_0 0 -#define OCR0B_1 1 -#define OCR0B_2 2 -#define OCR0B_3 3 -#define OCR0B_4 4 -#define OCR0B_5 5 -#define OCR0B_6 6 -#define OCR0B_7 7 - -#define PLLCSR _SFR_IO8(0x29) -#define PLOCK 0 -#define PLLE 1 -#define PLLF 2 - -#define SPCR _SFR_IO8(0x2C) -#define SPR0 0 -#define SPR1 1 -#define CPHA 2 -#define CPOL 3 -#define MSTR 4 -#define DORD 5 -#define SPE 6 -#define SPIE 7 - -#define SPSR _SFR_IO8(0x2D) -#define SPI2X 0 -#define WCOL 6 -#define SPIF 7 - -#define SPDR _SFR_IO8(0x2E) -#define SPDR0 0 -#define SPDR1 1 -#define SPDR2 2 -#define SPDR3 3 -#define SPDR4 4 -#define SPDR5 5 -#define SPDR6 6 -#define SPDR7 7 - -#define ACSR _SFR_IO8(0x30) -#define AC0O 0 -#define AC1O 1 -#define AC2O 2 -#define AC3O 3 -#define AC0IF 4 -#define AC1IF 5 -#define AC2IF 6 -#define AC3IF 7 - -#define DWDR _SFR_IO8(0x31) - -#define SMCR _SFR_IO8(0x33) -#define SE 0 -#define SM0 1 -#define SM1 2 -#define SM2 3 - -#define MCUSR _SFR_IO8(0x34) -#define PORF 0 -#define EXTRF 1 -#define BORF 2 -#define WDRF 3 - -#define MCUCR _SFR_IO8(0x35) -#define IVCE 0 -#define IVSEL 1 -#define PUD 4 -#define SPIPS 7 - -#define SPMCSR _SFR_IO8(0x37) -#define SPMEN 0 -#define PGERS 1 -#define PGWRT 2 -#define BLBSET 3 -#define RWWSRE 4 -#define SIGRD 5 -#define RWWSB 6 -#define SPMIE 7 - -#define WDTCSR _SFR_MEM8(0x60) -#define WDP0 0 -#define WDP1 1 -#define WDP2 2 -#define WDE 3 -#define WDCE 4 -#define WDP3 5 -#define WDIE 6 -#define WDIF 7 - -#define CLKPR _SFR_MEM8(0x61) -#define CLKPS0 0 -#define CLKPS1 1 -#define CLKPS2 2 -#define CLKPS3 3 -#define CLKPCE 7 - -#define PRR _SFR_MEM8(0x64) -#define PRADC 0 -#define PRLIN 1 -#define PRSPI 2 -#define PRTIM0 3 -#define PRTIM1 4 -#define PRPSC 5 -#define PRCAN 6 - -#define __AVR_HAVE_PRR ((1<, never directly. */ - -#ifndef _AVR_IO_H_ -# error "Include instead of this file." -#endif - -#ifndef _AVR_IOXXX_H_ -# define _AVR_IOXXX_H_ "iom64hve.h" -#else -# error "Attempt to include more than one file." -#endif - - -#ifndef _AVR_ATmega64HVE_H_ -#define _AVR_ATmega64HVE_H_ 1 - - -/* Registers and associated bit numbers. */ - -#define PINA _SFR_IO8(0x00) -#define PINA0 0 -#define PINA1 1 - -#define DDRA _SFR_IO8(0x01) -#define DDA0 0 -#define DDA1 1 - -#define PORTA _SFR_IO8(0x02) -#define PORTA0 0 -#define PORTA1 1 - -#define PINB _SFR_IO8(0x03) -#define PINB0 0 -#define PINB1 1 -#define PINB2 2 -#define PINB3 3 -#define PINB4 4 -#define PINB5 5 -#define PINB6 6 -#define PINB7 7 - -#define DDRB _SFR_IO8(0x04) -#define DDB0 0 -#define DDB1 1 -#define DDB2 2 -#define DDB3 3 -#define DDB4 4 -#define DDB5 5 -#define DDB6 6 -#define DDB7 7 - -#define PORTB _SFR_IO8(0x05) -#define PORTB0 0 -#define PORTB1 1 -#define PORTB2 2 -#define PORTB3 3 -#define PORTB4 4 -#define PORTB5 5 -#define PORTB6 6 -#define PORTB7 7 - -#define TIFR0 _SFR_IO8(0x15) -#define TOV0 0 -#define OCF0A 1 -#define OCF0B 2 -#define ICF0 3 - -#define TIFR1 _SFR_IO8(0x16) -#define TOV1 0 -#define OCF1A 1 -#define OCF1B 2 -#define ICF1 3 - -#define PCIFR _SFR_IO8(0x1B) -#define PCIF0 0 -#define PCIF1 1 - -#define EIFR _SFR_IO8(0x1C) -#define INTF0 0 - -#define EIMSK _SFR_IO8(0x1D) -#define INT0 0 - -#define GPIOR0 _SFR_IO8(0x1E) -#define GPIOR00 0 -#define GPIOR01 1 -#define GPIOR02 2 -#define GPIOR03 3 -#define GPIOR04 4 -#define GPIOR05 5 -#define GPIOR06 6 -#define GPIOR07 7 - -#define EECR _SFR_IO8(0x1F) -#define EERE 0 -#define EEPE 1 -#define EEMPE 2 -#define EERIE 3 -#define EEPM0 4 -#define EEPM1 5 - -#define EEDR _SFR_IO8(0x20) -#define EEDR0 0 -#define EEDR1 1 -#define EEDR2 2 -#define EEDR3 3 -#define EEDR4 4 -#define EEDR5 5 -#define EEDR6 6 -#define EEDR7 7 - -#define EEAR _SFR_IO16(0x21) - -#define EEARL _SFR_IO8(0x21) -#define EEAR0 0 -#define EEAR1 1 -#define EEAR2 2 -#define EEAR3 3 -#define EEAR4 4 -#define EEAR5 5 -#define EEAR6 6 -#define EEAR7 7 - -#define EEARH _SFR_IO8(0x22) -#define EEAR8 0 -#define EEAR9 1 - -#define GTCCR _SFR_IO8(0x23) -#define PSRSYNC 0 -#define TSM 7 - -#define TCCR0A _SFR_IO8(0x24) -#define WGM00 0 -#define ICS0 3 -#define ICES0 4 -#define ICNC0 5 -#define ICEN0 6 -#define TCW0 7 - -#define TCCR0B _SFR_IO8(0x25) -#define CS00 0 -#define CS01 1 -#define CS02 2 - -#define TCNT0 _SFR_IO16(0x26) - -#define TCNT0L _SFR_IO8(0x26) -#define TCNT0L0 0 -#define TCNT0L1 1 -#define TCNT0L2 2 -#define TCNT0L3 3 -#define TCNT0L4 4 -#define TCNT0L5 5 -#define TCNT0L6 6 -#define TCNT0L7 7 - -#define TCNT0H _SFR_IO8(0x27) -#define TCNT0H0 0 -#define TCNT0H1 1 -#define TCNT0H2 2 -#define TCNT0H3 3 -#define TCNT0H4 4 -#define TCNT0H5 5 -#define TCNT0H6 6 -#define TCNT0H7 7 - -#define OCR0A _SFR_IO8(0x28) -#define OCR0A0 0 -#define OCR0A1 1 -#define OCR0A2 2 -#define OCR0A3 3 -#define OCR0A4 4 -#define OCR0A5 5 -#define OCR0A6 6 -#define OCR0A7 7 - -#define OCR0B _SFR_IO8(0x29) -#define OCR0B0 0 -#define OCR0B1 1 -#define OCR0B2 2 -#define OCR0B3 3 -#define OCR0B4 4 -#define OCR0B5 5 -#define OCR0B6 6 -#define OCR0B7 7 - -#define GPIOR1 _SFR_IO8(0x2A) -#define GPIOR10 0 -#define GPIOR11 1 -#define GPIOR12 2 -#define GPIOR13 3 -#define GPIOR14 4 -#define GPIOR15 5 -#define GPIOR16 6 -#define GPIOR17 7 - -#define GPIOR2 _SFR_IO8(0x2B) -#define GPIOR20 0 -#define GPIOR21 1 -#define GPIOR22 2 -#define GPIOR23 3 -#define GPIOR24 4 -#define GPIOR25 5 -#define GPIOR26 6 -#define GPIOR27 7 - -#define SPCR _SFR_IO8(0x2C) -#define SPR0 0 -#define SPR1 1 -#define CPHA 2 -#define CPOL 3 -#define MSTR 4 -#define DORD 5 -#define SPE 6 -#define SPIE 7 - -#define SPSR _SFR_IO8(0x2D) -#define SPI2X 0 -#define WCOL 6 -#define SPIF 7 - -#define SPDR _SFR_IO8(0x2E) -#define SPDR0 0 -#define SPDR1 1 -#define SPDR2 2 -#define SPDR3 3 -#define SPDR4 4 -#define SPDR5 5 -#define SPDR6 6 -#define SPDR7 7 - -#define TCCR0C _SFR_IO8(0x2F) - -#define OCDR _SFR_IO8(0x31) - -#define SMCR _SFR_IO8(0x33) -#define SE 0 -#define SM0 1 -#define SM1 2 -#define SM2 3 - -#define MCUSR _SFR_IO8(0x34) -#define PORF 0 -#define EXTRF 1 -#define BODRF 2 -#define WDRF 3 -#define OCDRF 4 - -#define MCUCR _SFR_IO8(0x35) -#define IVCE 0 -#define IVSEL 1 -#define PUD 4 -#define CKOE 5 - -#define SPMCSR _SFR_IO8(0x37) -#define SPMEN 0 -#define PGERS 1 -#define PGWRT 2 -#define LBSET 3 -#define RWWSRE 4 -#define SIGRD 5 -#define RWWSB 6 -#define SPMIE 7 - -#define WDTCSR _SFR_MEM8(0x60) -#define WDP0 0 -#define WDP1 1 -#define WDP2 2 -#define WDE 3 -#define WDCE 4 -#define WDP3 5 -#define WDIE 6 -#define WDIF 7 - -#define CLKPR _SFR_MEM8(0x61) -#define CLKPS0 0 -#define CLKPS1 1 -#define CLKPCE 7 - -#define WUTCSR _SFR_MEM8(0x62) -#define WUTP0 0 -#define WUTP1 1 -#define WUTP2 2 -#define WUTE 3 -#define WUTR 4 -#define WUTIE 6 -#define WUTIF 7 - -#define WDTCLR _SFR_MEM8(0x63) -#define WDCLE 0 -#define WDCL0 1 -#define WDCL1 2 - -#define PRR0 _SFR_MEM8(0x64) -#define PRTIM0 0 -#define PRTIM1 1 -#define PRSPI 2 -#define PRLIN 3 - -#define __AVR_HAVE_PRR0 ((1< instead of this file." -#endif - -#ifndef _AVR_IOXXX_H_ -# define _AVR_IOXXX_H_ "iom64hve2.h" -#else -# error "Attempt to include more than one file." -#endif - -/* Registers and associated bit numbers */ - -#define PINA _SFR_IO8(0x00) -#define PINA1 1 -#define PINA0 0 - -#define DDRA _SFR_IO8(0x01) -#define DDRA1 1 -// Inserted "DDA1" from "DDRA1" due to compatibility -#define DDA1 1 -#define DDRA0 0 -// Inserted "DDA0" from "DDRA0" due to compatibility -#define DDA0 0 - -#define PORTA _SFR_IO8(0x02) -#define PORTA1 1 -#define PORTA0 0 - -#define PINB _SFR_IO8(0x03) -#define PINB7 7 -#define PINB6 6 -#define PINB5 5 -#define PINB4 4 -#define PINB3 3 -#define PINB2 2 -#define PINB1 1 -#define PINB0 0 - -#define DDRB _SFR_IO8(0x04) -#define DDRB7 7 -// Inserted "DDB7" from "DDRB7" due to compatibility -#define DDB7 7 -#define DDRB6 6 -// Inserted "DDB6" from "DDRB6" due to compatibility -#define DDB6 6 -#define DDRB5 5 -// Inserted "DDB5" from "DDRB5" due to compatibility -#define DDB5 5 -#define DDRB4 4 -// Inserted "DDB4" from "DDRB4" due to compatibility -#define DDB4 4 -#define DDRB3 3 -// Inserted "DDB3" from "DDRB3" due to compatibility -#define DDB3 3 -#define DDRB2 2 -// Inserted "DDB2" from "DDRB2" due to compatibility -#define DDB2 2 -#define DDRB1 1 -// Inserted "DDB1" from "DDRB1" due to compatibility -#define DDB1 1 -#define DDRB0 0 -// Inserted "DDB0" from "DDRB0" due to compatibility -#define DDB0 0 - -#define PORTB _SFR_IO8(0x05) -#define PORTB7 7 -#define PORTB6 6 -#define PORTB5 5 -#define PORTB4 4 -#define PORTB3 3 -#define PORTB2 2 -#define PORTB1 1 -#define PORTB0 0 - -/* Reserved [0x06..0x14] */ - -#define TIFR0 _SFR_IO8(0x15) -#define TOV0 0 -#define OCF0A 1 -#define OCF0B 2 -#define ICF0 3 - -#define TIFR1 _SFR_IO8(0x16) -#define TOV1 0 -#define OCF1A 1 -#define OCF1B 2 -#define ICF1 3 - -/* Reserved [0x17..0x1A] */ - -#define PCIFR _SFR_IO8(0x1B) -#define PCIF0 0 -#define PCIF1 1 - -#define EIFR _SFR_IO8(0x1C) -#define INTF0 0 - -#define EIMSK _SFR_IO8(0x1D) -#define INT0 0 - -#define GPIOR0 _SFR_IO8(0x1E) - -#define EECR _SFR_IO8(0x1F) -#define EERE 0 -#define EEPE 1 -#define EEMPE 2 -#define EERIE 3 -#define EEPM0 4 -#define EEPM1 5 - -#define EEDR _SFR_IO8(0x20) - -/* Combine EEARL and EEARH */ -#define EEAR _SFR_IO16(0x21) - -#define EEARL _SFR_IO8(0x21) -#define EEARH _SFR_IO8(0x22) - -#define GTCCR _SFR_IO8(0x23) -#define PSRSYNC 0 -#define TSM 7 - -#define TCCR0A _SFR_IO8(0x24) -#define WGM00 0 -#define ICS0 3 -#define ICES0 4 -#define ICNC0 5 -#define ICEN0 6 -#define TCW0 7 - -#define TCCR0B _SFR_IO8(0x25) -#define CS00 0 -#define CS01 1 -#define CS02 2 - -/* Combine TCNT0L and TCNT0H */ -#define TCNT0 _SFR_IO16(0x26) - -#define TCNT0L _SFR_IO8(0x26) -#define TCNT0H _SFR_IO8(0x27) - -#define OCR0A _SFR_IO8(0x28) - -#define OCR0B _SFR_IO8(0x29) - -#define GPIOR1 _SFR_IO8(0x2A) - -#define GPIOR2 _SFR_IO8(0x2B) - -#define SPCR _SFR_IO8(0x2C) -#define SPR0 0 -#define SPR1 1 -#define CPHA 2 -#define CPOL 3 -#define MSTR 4 -#define DORD 5 -#define SPE 6 -#define SPIE 7 - -#define SPSR _SFR_IO8(0x2D) -#define SPI2X 0 -#define WCOL 6 -#define SPIF 7 - -#define SPDR _SFR_IO8(0x2E) - -/* Reserved [0x2F..0x32] */ - -#define SMCR _SFR_IO8(0x33) -#define SE 0 -#define SM0 1 -#define SM1 2 -#define SM2 3 - -#define MCUSR _SFR_IO8(0x34) -#define PORF 0 -#define EXTRF 1 -#define BODRF 2 -#define WDRF 3 -#define OCDRF 4 - -#define MCUCR _SFR_IO8(0x35) -#define IVCE 0 -#define IVSEL 1 -#define PUD 4 -#define CKOE 5 - -/* Reserved [0x36] */ - -#define SPMCSR _SFR_IO8(0x37) -#define SPMEN 0 -#define PGERS 1 -#define PGWRT 2 -#define LBSET 3 -#define RWWSRE 4 -#define SIGRD 5 -#define RWWSB 6 -#define SPMIE 7 - -/* Reserved [0x38..0x3C] */ - -/* SP [0x3D..0x3E] */ - -/* SREG [0x3F] */ - -#define WDTCSR _SFR_MEM8(0x60) -#define WDE 3 -#define WDCE 4 -#define WDP0 0 -#define WDP1 1 -#define WDP2 2 -#define WDP3 5 -#define WDIE 6 -#define WDIF 7 - -#define CLKPR _SFR_MEM8(0x61) -#define CLKPS0 0 -#define CLKPS1 1 -#define CLKPCE 7 - -#define WUTCSR _SFR_MEM8(0x62) -#define WUTP0 0 -#define WUTP1 1 -#define WUTP2 2 -#define WUTE 3 -#define WUTR 4 -#define WUTIE 6 -#define WUTIF 7 - -#define WDTCLR _SFR_MEM8(0x63) -#define WDCLE 0 -#define WDCL0 1 -#define WDCL1 2 - -#define PRR0 _SFR_MEM8(0x64) -#define PRTIM0 0 -#define PRTIM1 1 -#define PRSPI 2 -#define PRLIN 3 - -#define __AVR_HAVE_PRR0 ((1<, never directly. */ - -#ifndef _AVR_IO_H_ -# error "Include instead of this file." -#endif - -#ifndef _AVR_IOXXX_H_ -# define _AVR_IOXXX_H_ "iom64m1.h" -#else -# error "Attempt to include more than one file." -#endif - - -#ifndef _AVR_ATmega64M1_H_ -#define _AVR_ATmega64M1_H_ 1 - - -/* Registers and associated bit numbers. */ - -#define PINB _SFR_IO8(0x03) -#define PINB0 0 -#define PINB1 1 -#define PINB2 2 -#define PINB3 3 -#define PINB4 4 -#define PINB5 5 -#define PINB6 6 -#define PINB7 7 - -#define DDRB _SFR_IO8(0x04) -#define DDB0 0 -#define DDB1 1 -#define DDB2 2 -#define DDB3 3 -#define DDB4 4 -#define DDB5 5 -#define DDB6 6 -#define DDB7 7 - -#define PORTB _SFR_IO8(0x05) -#define PORTB0 0 -#define PORTB1 1 -#define PORTB2 2 -#define PORTB3 3 -#define PORTB4 4 -#define PORTB5 5 -#define PORTB6 6 -#define PORTB7 7 - -#define PINC _SFR_IO8(0x06) -#define PINC0 0 -#define PINC1 1 -#define PINC2 2 -#define PINC3 3 -#define PINC4 4 -#define PINC5 5 -#define PINC6 6 -#define PINC7 7 - -#define DDRC _SFR_IO8(0x07) -#define DDC0 0 -#define DDC1 1 -#define DDC2 2 -#define DDC3 3 -#define DDC4 4 -#define DDC5 5 -#define DDC6 6 -#define DDC7 7 - -#define PORTC _SFR_IO8(0x08) -#define PORTC0 0 -#define PORTC1 1 -#define PORTC2 2 -#define PORTC3 3 -#define PORTC4 4 -#define PORTC5 5 -#define PORTC6 6 -#define PORTC7 7 - -#define PIND _SFR_IO8(0x09) -#define PIND0 0 -#define PIND1 1 -#define PIND2 2 -#define PIND3 3 -#define PIND4 4 -#define PIND5 5 -#define PIND6 6 -#define PIND7 7 - -#define DDRD _SFR_IO8(0x0A) -#define DDD0 0 -#define DDD1 1 -#define DDD2 2 -#define DDD3 3 -#define DDD4 4 -#define DDD5 5 -#define DDD6 6 -#define DDD7 7 - -#define PORTD _SFR_IO8(0x0B) -#define PORTD0 0 -#define PORTD1 1 -#define PORTD2 2 -#define PORTD3 3 -#define PORTD4 4 -#define PORTD5 5 -#define PORTD6 6 -#define PORTD7 7 - -#define PINE _SFR_IO8(0x0C) -#define PINE0 0 -#define PINE1 1 -#define PINE2 2 - -#define DDRE _SFR_IO8(0x0D) -#define DDE0 0 -#define DDE1 1 -#define DDE2 2 - -#define PORTE _SFR_IO8(0x0E) -#define PORTE0 0 -#define PORTE1 1 -#define PORTE2 2 - -#define TIFR0 _SFR_IO8(0x15) -#define TOV0 0 -#define OCF0A 1 -#define OCF0B 2 - -#define TIFR1 _SFR_IO8(0x16) -#define TOV1 0 -#define OCF1A 1 -#define OCF1B 2 -#define ICF1 5 - -#define GPIOR1 _SFR_IO8(0x19) -#define GPIOR10 0 -#define GPIOR11 1 -#define GPIOR12 2 -#define GPIOR13 3 -#define GPIOR14 4 -#define GPIOR15 5 -#define GPIOR16 6 -#define GPIOR17 7 - -#define GPIOR2 _SFR_IO8(0x1A) -#define GPIOR20 0 -#define GPIOR21 1 -#define GPIOR22 2 -#define GPIOR23 3 -#define GPIOR24 4 -#define GPIOR25 5 -#define GPIOR26 6 -#define GPIOR27 7 - -#define PCIFR _SFR_IO8(0x1B) -#define PCIF0 0 -#define PCIF1 1 -#define PCIF2 2 -#define PCIF3 3 - -#define EIFR _SFR_IO8(0x1C) -#define INTF0 0 -#define INTF1 1 -#define INTF2 2 -#define INTF3 3 - -#define EIMSK _SFR_IO8(0x1D) -#define INT0 0 -#define INT1 1 -#define INT2 2 -#define INT3 3 - -#define GPIOR0 _SFR_IO8(0x1E) -#define GPIOR00 0 -#define GPIOR01 1 -#define GPIOR02 2 -#define GPIOR03 3 -#define GPIOR04 4 -#define GPIOR05 5 -#define GPIOR06 6 -#define GPIOR07 7 - -#define EECR _SFR_IO8(0x1F) -#define EERE 0 -#define EEWE 1 -#define EEMWE 2 -#define EERIE 3 -#define EEPM0 4 -#define EEPM1 5 - -#define EEDR _SFR_IO8(0x20) -#define EEDR0 0 -#define EEDR1 1 -#define EEDR2 2 -#define EEDR3 3 -#define EEDR4 4 -#define EEDR5 5 -#define EEDR6 6 -#define EEDR7 7 - -#define EEAR _SFR_IO16(0x21) - -#define EEARL _SFR_IO8(0x21) -#define EEAR0 0 -#define EEAR1 1 -#define EEAR2 2 -#define EEAR3 3 -#define EEAR4 4 -#define EEAR5 5 -#define EEAR6 6 -#define EEAR7 7 - -#define EEARH _SFR_IO8(0x22) -#define EEAR8 0 -#define EEAR9 1 -#define EEAR10 2 - -#define GTCCR _SFR_IO8(0x23) -#define PSR10 0 -#define PSRSYNC 0 -#define ICPSEL1 6 -#define TSM 7 - -#define TCCR0A _SFR_IO8(0x24) -#define WGM00 0 -#define WGM01 1 -#define COM0B0 4 -#define COM0B1 5 -#define COM0A0 6 -#define COM0A1 7 - -#define TCCR0B _SFR_IO8(0x25) -#define CS00 0 -#define CS01 1 -#define CS02 2 -#define WGM02 3 -#define FOC0B 6 -#define FOC0A 7 - -#define TCNT0 _SFR_IO8(0x26) -#define TCNT0_0 0 -#define TCNT0_1 1 -#define TCNT0_2 2 -#define TCNT0_3 3 -#define TCNT0_4 4 -#define TCNT0_5 5 -#define TCNT0_6 6 -#define TCNT0_7 7 - -#define OCR0A _SFR_IO8(0x27) -#define OCR0A_0 0 -#define OCR0A_1 1 -#define OCR0A_2 2 -#define OCR0A_3 3 -#define OCR0A_4 4 -#define OCR0A_5 5 -#define OCR0A_6 6 -#define OCR0A_7 7 - -#define OCR0B _SFR_IO8(0x28) -#define OCR0B_0 0 -#define OCR0B_1 1 -#define OCR0B_2 2 -#define OCR0B_3 3 -#define OCR0B_4 4 -#define OCR0B_5 5 -#define OCR0B_6 6 -#define OCR0B_7 7 - -#define PLLCSR _SFR_IO8(0x29) -#define PLOCK 0 -#define PLLE 1 -#define PLLF 2 - -#define SPCR _SFR_IO8(0x2C) -#define SPR0 0 -#define SPR1 1 -#define CPHA 2 -#define CPOL 3 -#define MSTR 4 -#define DORD 5 -#define SPE 6 -#define SPIE 7 - -#define SPSR _SFR_IO8(0x2D) -#define SPI2X 0 -#define WCOL 6 -#define SPIF 7 - -#define SPDR _SFR_IO8(0x2E) -#define SPDR0 0 -#define SPDR1 1 -#define SPDR2 2 -#define SPDR3 3 -#define SPDR4 4 -#define SPDR5 5 -#define SPDR6 6 -#define SPDR7 7 - -#define ACSR _SFR_IO8(0x30) -#define AC0O 0 -#define AC1O 1 -#define AC2O 2 -#define AC3O 3 -#define AC0IF 4 -#define AC1IF 5 -#define AC2IF 6 -#define AC3IF 7 - -#define DWDR _SFR_IO8(0x31) - -#define SMCR _SFR_IO8(0x33) -#define SE 0 -#define SM0 1 -#define SM1 2 -#define SM2 3 - -#define MCUSR _SFR_IO8(0x34) -#define PORF 0 -#define EXTRF 1 -#define BORF 2 -#define WDRF 3 - -#define MCUCR _SFR_IO8(0x35) -#define IVCE 0 -#define IVSEL 1 -#define PUD 4 -#define SPIPS 7 - -#define SPMCSR _SFR_IO8(0x37) -#define SPMEN 0 -#define PGERS 1 -#define PGWRT 2 -#define BLBSET 3 -#define RWWSRE 4 -#define SIGRD 5 -#define RWWSB 6 -#define SPMIE 7 - -#define WDTCSR _SFR_MEM8(0x60) -#define WDP0 0 -#define WDP1 1 -#define WDP2 2 -#define WDE 3 -#define WDCE 4 -#define WDP3 5 -#define WDIE 6 -#define WDIF 7 - -#define CLKPR _SFR_MEM8(0x61) -#define CLKPS0 0 -#define CLKPS1 1 -#define CLKPS2 2 -#define CLKPS3 3 -#define CLKPCE 7 - -#define PRR _SFR_MEM8(0x64) -#define PRADC 0 -#define PRLIN 1 -#define PRSPI 2 -#define PRTIM0 3 -#define PRTIM1 4 -#define PRPSC 5 -#define PRCAN 6 - -#define __AVR_HAVE_PRR ((1< instead of this file." -#endif - -#ifndef _AVR_IOXXX_H_ -# define _AVR_IOXXX_H_ "iom64rfr2.h" -#else -# error "Attempt to include more than one file." -#endif - -/* Registers and associated bit numbers */ - -#define PINA _SFR_IO8(0x00) -#define PINA7 7 -#define PINA6 6 -#define PINA5 5 -#define PINA4 4 -#define PINA3 3 -#define PINA2 2 -#define PINA1 1 -#define PINA0 0 - -#define DDRA _SFR_IO8(0x01) -#define DDRA7 7 -// Inserted "DDA7" from "DDRA7" due to compatibility -#define DDA7 7 -#define DDRA6 6 -// Inserted "DDA6" from "DDRA6" due to compatibility -#define DDA6 6 -#define DDRA5 5 -// Inserted "DDA5" from "DDRA5" due to compatibility -#define DDA5 5 -#define DDRA4 4 -// Inserted "DDA4" from "DDRA4" due to compatibility -#define DDA4 4 -#define DDRA3 3 -// Inserted "DDA3" from "DDRA3" due to compatibility -#define DDA3 3 -#define DDRA2 2 -// Inserted "DDA2" from "DDRA2" due to compatibility -#define DDA2 2 -#define DDRA1 1 -// Inserted "DDA1" from "DDRA1" due to compatibility -#define DDA1 1 -#define DDRA0 0 -// Inserted "DDA0" from "DDRA0" due to compatibility -#define DDA0 0 - -#define PORTA _SFR_IO8(0x02) -#define PORTA7 7 -#define PORTA6 6 -#define PORTA5 5 -#define PORTA4 4 -#define PORTA3 3 -#define PORTA2 2 -#define PORTA1 1 -#define PORTA0 0 - -#define PINB _SFR_IO8(0x03) -#define PINB7 7 -#define PINB6 6 -#define PINB5 5 -#define PINB4 4 -#define PINB3 3 -#define PINB2 2 -#define PINB1 1 -#define PINB0 0 - -#define DDRB _SFR_IO8(0x04) -#define DDRB7 7 -// Inserted "DDB7" from "DDRB7" due to compatibility -#define DDB7 7 -#define DDRB6 6 -// Inserted "DDB6" from "DDRB6" due to compatibility -#define DDB6 6 -#define DDRB5 5 -// Inserted "DDB5" from "DDRB5" due to compatibility -#define DDB5 5 -#define DDRB4 4 -// Inserted "DDB4" from "DDRB4" due to compatibility -#define DDB4 4 -#define DDRB3 3 -// Inserted "DDB3" from "DDRB3" due to compatibility -#define DDB3 3 -#define DDRB2 2 -// Inserted "DDB2" from "DDRB2" due to compatibility -#define DDB2 2 -#define DDRB1 1 -// Inserted "DDB1" from "DDRB1" due to compatibility -#define DDB1 1 -#define DDRB0 0 -// Inserted "DDB0" from "DDRB0" due to compatibility -#define DDB0 0 - -#define PORTB _SFR_IO8(0x05) -#define PORTB7 7 -#define PORTB6 6 -#define PORTB5 5 -#define PORTB4 4 -#define PORTB3 3 -#define PORTB2 2 -#define PORTB1 1 -#define PORTB0 0 - -#define PINC _SFR_IO8(0x06) -#define PINC7 7 -#define PINC6 6 -#define PINC5 5 -#define PINC4 4 -#define PINC3 3 -#define PINC2 2 -#define PINC1 1 -#define PINC0 0 - -#define DDRC _SFR_IO8(0x07) -#define DDRC7 7 -// Inserted "DDC7" from "DDRC7" due to compatibility -#define DDC7 7 -#define DDRC6 6 -// Inserted "DDC6" from "DDRC6" due to compatibility -#define DDC6 6 -#define DDRC5 5 -// Inserted "DDC5" from "DDRC5" due to compatibility -#define DDC5 5 -#define DDRC4 4 -// Inserted "DDC4" from "DDRC4" due to compatibility -#define DDC4 4 -#define DDRC3 3 -// Inserted "DDC3" from "DDRC3" due to compatibility -#define DDC3 3 -#define DDRC2 2 -// Inserted "DDC2" from "DDRC2" due to compatibility -#define DDC2 2 -#define DDRC1 1 -// Inserted "DDC1" from "DDRC1" due to compatibility -#define DDC1 1 -#define DDRC0 0 -// Inserted "DDC0" from "DDRC0" due to compatibility -#define DDC0 0 - -#define PORTC _SFR_IO8(0x08) -#define PORTC7 7 -#define PORTC6 6 -#define PORTC5 5 -#define PORTC4 4 -#define PORTC3 3 -#define PORTC2 2 -#define PORTC1 1 -#define PORTC0 0 - -#define PIND _SFR_IO8(0x09) -#define PIND7 7 -#define PIND6 6 -#define PIND5 5 -#define PIND4 4 -#define PIND3 3 -#define PIND2 2 -#define PIND1 1 -#define PIND0 0 - -#define DDRD _SFR_IO8(0x0A) -#define DDRD7 7 -// Inserted "DDD7" from "DDRD7" due to compatibility -#define DDD7 7 -#define DDRD6 6 -// Inserted "DDD6" from "DDRD6" due to compatibility -#define DDD6 6 -#define DDRD5 5 -// Inserted "DDD5" from "DDRD5" due to compatibility -#define DDD5 5 -#define DDRD4 4 -// Inserted "DDD4" from "DDRD4" due to compatibility -#define DDD4 4 -#define DDRD3 3 -// Inserted "DDD3" from "DDRD3" due to compatibility -#define DDD3 3 -#define DDRD2 2 -// Inserted "DDD2" from "DDRD2" due to compatibility -#define DDD2 2 -#define DDRD1 1 -// Inserted "DDD1" from "DDRD1" due to compatibility -#define DDD1 1 -#define DDRD0 0 -// Inserted "DDD0" from "DDRD0" due to compatibility -#define DDD0 0 - -#define PORTD _SFR_IO8(0x0B) -#define PORTD7 7 -#define PORTD6 6 -#define PORTD5 5 -#define PORTD4 4 -#define PORTD3 3 -#define PORTD2 2 -#define PORTD1 1 -#define PORTD0 0 - -#define PINE _SFR_IO8(0x0C) -#define PINE7 7 -#define PINE6 6 -#define PINE5 5 -#define PINE4 4 -#define PINE3 3 -#define PINE2 2 -#define PINE1 1 -#define PINE0 0 - -#define DDRE _SFR_IO8(0x0D) -#define DDRE7 7 -// Inserted "DDE7" from "DDRE7" due to compatibility -#define DDE7 7 -#define DDRE6 6 -// Inserted "DDE6" from "DDRE6" due to compatibility -#define DDE6 6 -#define DDRE5 5 -// Inserted "DDE5" from "DDRE5" due to compatibility -#define DDE5 5 -#define DDRE4 4 -// Inserted "DDE4" from "DDRE4" due to compatibility -#define DDE4 4 -#define DDRE3 3 -// Inserted "DDE3" from "DDRE3" due to compatibility -#define DDE3 3 -#define DDRE2 2 -// Inserted "DDE2" from "DDRE2" due to compatibility -#define DDE2 2 -#define DDRE1 1 -// Inserted "DDE1" from "DDRE1" due to compatibility -#define DDE1 1 -#define DDRE0 0 -// Inserted "DDE0" from "DDRE0" due to compatibility -#define DDE0 0 - -#define PORTE _SFR_IO8(0x0E) -#define PORTE7 7 -#define PORTE6 6 -#define PORTE5 5 -#define PORTE4 4 -#define PORTE3 3 -#define PORTE2 2 -#define PORTE1 1 -#define PORTE0 0 - -#define PINF _SFR_IO8(0x0F) -#define PINF7 7 -#define PINF6 6 -#define PINF5 5 -#define PINF4 4 -#define PINF3 3 -#define PINF2 2 -#define PINF1 1 -#define PINF0 0 - -#define DDRF _SFR_IO8(0x10) -#define DDRF7 7 -// Inserted "DDF7" from "DDRF7" due to compatibility -#define DDF7 7 -#define DDRF6 6 -// Inserted "DDF6" from "DDRF6" due to compatibility -#define DDF6 6 -#define DDRF5 5 -// Inserted "DDF5" from "DDRF5" due to compatibility -#define DDF5 5 -#define DDRF4 4 -// Inserted "DDF4" from "DDRF4" due to compatibility -#define DDF4 4 -#define DDRF3 3 -// Inserted "DDF3" from "DDRF3" due to compatibility -#define DDF3 3 -#define DDRF2 2 -// Inserted "DDF2" from "DDRF2" due to compatibility -#define DDF2 2 -#define DDRF1 1 -// Inserted "DDF1" from "DDRF1" due to compatibility -#define DDF1 1 -#define DDRF0 0 -// Inserted "DDF0" from "DDRF0" due to compatibility -#define DDF0 0 - -#define PORTF _SFR_IO8(0x11) -#define PORTF7 7 -#define PORTF6 6 -#define PORTF5 5 -#define PORTF4 4 -#define PORTF3 3 -#define PORTF2 2 -#define PORTF1 1 -#define PORTF0 0 - -#define PING _SFR_IO8(0x12) -#define PING7 7 -#define PING6 6 -#define PING5 5 -#define PING4 4 -#define PING3 3 -#define PING2 2 -#define PING1 1 -#define PING0 0 - -#define DDRG _SFR_IO8(0x13) -#define DDRG7 7 -// Inserted "DDG7" from "DDRG7" due to compatibility -#define DDG7 7 -#define DDRG6 6 -// Inserted "DDG6" from "DDRG6" due to compatibility -#define DDG6 6 -#define DDRG5 5 -// Inserted "DDG5" from "DDRG5" due to compatibility -#define DDG5 5 -#define DDRG4 4 -// Inserted "DDG4" from "DDRG4" due to compatibility -#define DDG4 4 -#define DDRG3 3 -// Inserted "DDG3" from "DDRG3" due to compatibility -#define DDG3 3 -#define DDRG2 2 -// Inserted "DDG2" from "DDRG2" due to compatibility -#define DDG2 2 -#define DDRG1 1 -// Inserted "DDG1" from "DDRG1" due to compatibility -#define DDG1 1 -#define DDRG0 0 -// Inserted "DDG0" from "DDRG0" due to compatibility -#define DDG0 0 - -#define PORTG _SFR_IO8(0x14) -#define PORTG7 7 -#define PORTG6 6 -#define PORTG5 5 -#define PORTG4 4 -#define PORTG3 3 -#define PORTG2 2 -#define PORTG1 1 -#define PORTG0 0 - -#define TIFR0 _SFR_IO8(0x15) -#define TOV0 0 -#define OCF0A 1 -#define OCF0B 2 -#define Res0 3 -#define Res1 4 -#define Res2 5 -#define Res3 6 -#define Res4 7 - -#define TIFR1 _SFR_IO8(0x16) -#define TOV1 0 -#define OCF1A 1 -#define OCF1B 2 -#define OCF1C 3 -#define ICF1 5 - -#define TIFR2 _SFR_IO8(0x17) -#define TOV2 0 -#define OCF2A 1 -#define OCF2B 2 - -#define TIFR3 _SFR_IO8(0x18) -#define TOV3 0 -#define OCF3A 1 -#define OCF3B 2 -#define OCF3C 3 -#define ICF3 5 - -#define TIFR4 _SFR_IO8(0x19) -#define TOV4 0 -#define OCF4A 1 -#define OCF4B 2 -#define OCF4C 3 -#define ICF4 5 - -#define TIFR5 _SFR_IO8(0x1A) -#define TOV5 0 -#define OCF5A 1 -#define OCF5B 2 -#define OCF5C 3 -#define ICF5 5 - -#define PCIFR _SFR_IO8(0x1B) -#define PCIF0 0 -#define PCIF1 1 -#define PCIF2 2 - -#define EIFR _SFR_IO8(0x1C) -#define INTF0 0 -#define INTF1 1 -#define INTF2 2 -#define INTF3 3 -#define INTF4 4 -#define INTF5 5 -#define INTF6 6 -#define INTF7 7 - -#define EIMSK _SFR_IO8(0x1D) -#define INT0 0 -#define INT1 1 -#define INT2 2 -#define INT3 3 -#define INT4 4 -#define INT5 5 -#define INT6 6 -#define INT7 7 - -#define GPIOR0 _SFR_IO8(0x1E) -#define GPIOR00 0 -#define GPIOR01 1 -#define GPIOR02 2 -#define GPIOR03 3 -#define GPIOR04 4 -#define GPIOR05 5 -#define GPIOR06 6 -#define GPIOR07 7 - -#define EECR _SFR_IO8(0x1F) -#define EERE 0 -#define EEPE 1 -#define EEMPE 2 -#define EERIE 3 -#define EEPM0 4 -#define EEPM1 5 - -#define EEDR _SFR_IO8(0x20) - -/* Combine EEARL and EEARH */ -#define EEAR _SFR_IO16(0x21) - -#define EEARL _SFR_IO8(0x21) -#define EEARH _SFR_IO8(0x22) - -#define GTCCR _SFR_IO8(0x23) -#define PSRSYNC 0 -#define PSRASY 1 -#define TSM 7 - -#define TCCR0A _SFR_IO8(0x24) -#define WGM00 0 -#define WGM01 1 -#define COM0B0 4 -#define COM0B1 5 -#define COM0A0 6 -#define COM0A1 7 - -#define TCCR0B _SFR_IO8(0x25) -#define CS00 0 -#define CS01 1 -#define CS02 2 -#define WGM02 3 -#define FOC0B 6 -#define FOC0A 7 - -#define TCNT0 _SFR_IO8(0x26) - -#define OCR0A _SFR_IO8(0x27) - -#define OCR0B _SFR_IO8(0x28) - -/* Reserved [0x29] */ - -#define GPIOR1 _SFR_IO8(0x2A) -#define GPIOR10 0 -#define GPIOR11 1 -#define GPIOR12 2 -#define GPIOR13 3 -#define GPIOR14 4 -#define GPIOR15 5 -#define GPIOR16 6 -#define GPIOR17 7 - -#define GPIOR2 _SFR_IO8(0x2B) -#define GPIOR20 0 -#define GPIOR21 1 -#define GPIOR22 2 -#define GPIOR23 3 -#define GPIOR24 4 -#define GPIOR25 5 -#define GPIOR26 6 -#define GPIOR27 7 - -#define SPCR _SFR_IO8(0x2C) -#define SPR0 0 -#define SPR1 1 -#define CPHA 2 -#define CPOL 3 -#define MSTR 4 -#define DORD 5 -#define SPE 6 -#define SPIE 7 - -#define SPSR _SFR_IO8(0x2D) -#define SPI2X 0 -#define WCOL 6 -#define SPIF 7 - -#define SPDR _SFR_IO8(0x2E) - -/* Reserved [0x2F] */ - -#define ACSR _SFR_IO8(0x30) -#define ACIS0 0 -#define ACIS1 1 -#define ACIC 2 -#define ACIE 3 -#define ACI 4 -#define ACO 5 -#define ACBG 6 -#define ACD 7 - -#define OCDR _SFR_IO8(0x31) -#define OCDR0 0 -#define OCDR1 1 -#define OCDR2 2 -#define OCDR3 3 -#define OCDR4 4 -#define OCDR5 5 -#define OCDR6 6 -#define OCDR7 7 - -/* Reserved [0x32] */ - -#define SMCR _SFR_IO8(0x33) -#define SE 0 -#define SM0 1 -#define SM1 2 -#define SM2 3 - -#define MCUSR _SFR_IO8(0x34) -#define JTRF 4 -#define PORF 0 -#define EXTRF 1 -#define BORF 2 -#define WDRF 3 - -#define MCUCR _SFR_IO8(0x35) -#define JTD 7 -#define IVCE 0 -#define IVSEL 1 -#define PUD 4 - -/* Reserved [0x36] */ - -#define SPMCSR _SFR_IO8(0x37) -#define SPMEN 0 -#define PGERS 1 -#define PGWRT 2 -#define BLBSET 3 -#define RWWSRE 4 -#define SIGRD 5 -#define RWWSB 6 -#define SPMIE 7 - -/* Reserved [0x38..0x3C] */ - -/* SP [0x3D..0x3E] */ - -/* SREG [0x3F] */ - -#define WDTCSR _SFR_MEM8(0x60) -#define WDE 3 -#define WDCE 4 -#define WDP0 0 -#define WDP1 1 -#define WDP2 2 -#define WDP3 5 -#define WDIE 6 -#define WDIF 7 - -#define CLKPR _SFR_MEM8(0x61) -#define CLKPS0 0 -#define CLKPS1 1 -#define CLKPS2 2 -#define CLKPS3 3 -#define CLKPCE 7 - -/* Reserved [0x62] */ - -#define PRR2 _SFR_MEM8(0x63) -#define PRRAM0 0 -#define PRRAM1 1 -#define PRRAM2 2 -#define PRRAM3 3 - -#define __AVR_HAVE_PRR2 ((1<, never directly. */ - -#ifndef _AVR_IO_H_ -# error "Include instead of this file." -#endif - -#ifndef _AVR_IOXXX_H_ -# define _AVR_IOXXX_H_ "iom8.h" -#else -# error "Attempt to include more than one file." -#endif - -/* I/O registers */ - -/* TWI stands for "Two Wire Interface" or "TWI Was I2C(tm)" */ -#define TWBR _SFR_IO8(0x00) -#define TWSR _SFR_IO8(0x01) -#define TWAR _SFR_IO8(0x02) -#define TWDR _SFR_IO8(0x03) - -/* ADC */ -#define ADCW _SFR_IO16(0x04) -#ifndef __ASSEMBLER__ -#define ADC _SFR_IO16(0x04) -#endif -#define ADCL _SFR_IO8(0x04) -#define ADCH _SFR_IO8(0x05) -#define ADCSR _SFR_IO8(0x06) -#define ADCSRA _SFR_IO8(0x06) /* Changed in 2486H-AVR-09/02 */ -#define ADMUX _SFR_IO8(0x07) - -/* analog comparator */ -#define ACSR _SFR_IO8(0x08) - -/* USART */ -#define UBRRL _SFR_IO8(0x09) -#define UCSRB _SFR_IO8(0x0A) -#define UCSRA _SFR_IO8(0x0B) -#define UDR _SFR_IO8(0x0C) - -/* SPI */ -#define SPCR _SFR_IO8(0x0D) -#define SPSR _SFR_IO8(0x0E) -#define SPDR _SFR_IO8(0x0F) - -/* Port D */ -#define PIND _SFR_IO8(0x10) -#define DDRD _SFR_IO8(0x11) -#define PORTD _SFR_IO8(0x12) - -/* Port C */ -#define PINC _SFR_IO8(0x13) -#define DDRC _SFR_IO8(0x14) -#define PORTC _SFR_IO8(0x15) - -/* Port B */ -#define PINB _SFR_IO8(0x16) -#define DDRB _SFR_IO8(0x17) -#define PORTB _SFR_IO8(0x18) - -/* EEPROM Control Register */ -#define EECR _SFR_IO8(0x1C) - -/* EEPROM Data Register */ -#define EEDR _SFR_IO8(0x1D) - -/* EEPROM Address Register */ -#define EEAR _SFR_IO16(0x1E) -#define EEARL _SFR_IO8(0x1E) -#define EEARH _SFR_IO8(0x1F) - -#define UCSRC _SFR_IO8(0x20) -#define UBRRH _SFR_IO8(0x20) - -#define WDTCR _SFR_IO8(0x21) -#define ASSR _SFR_IO8(0x22) - -/* Timer 2 */ -#define OCR2 _SFR_IO8(0x23) -#define TCNT2 _SFR_IO8(0x24) -#define TCCR2 _SFR_IO8(0x25) - -/* Timer 1 */ -#define ICR1 _SFR_IO16(0x26) -#define ICR1L _SFR_IO8(0x26) -#define ICR1H _SFR_IO8(0x27) -#define OCR1B _SFR_IO16(0x28) -#define OCR1BL _SFR_IO8(0x28) -#define OCR1BH _SFR_IO8(0x29) -#define OCR1A _SFR_IO16(0x2A) -#define OCR1AL _SFR_IO8(0x2A) -#define OCR1AH _SFR_IO8(0x2B) -#define TCNT1 _SFR_IO16(0x2C) -#define TCNT1L _SFR_IO8(0x2C) -#define TCNT1H _SFR_IO8(0x2D) -#define TCCR1B _SFR_IO8(0x2E) -#define TCCR1A _SFR_IO8(0x2F) - -#define SFIOR _SFR_IO8(0x30) - -#define OSCCAL _SFR_IO8(0x31) - -/* Timer 0 */ -#define TCNT0 _SFR_IO8(0x32) -#define TCCR0 _SFR_IO8(0x33) - -#define MCUCSR _SFR_IO8(0x34) -#define MCUSR _SFR_IO8(0x34) /* Defined as an alias for MCUCSR. */ - -#define MCUCR _SFR_IO8(0x35) - -#define TWCR _SFR_IO8(0x36) - -#define SPMCR _SFR_IO8(0x37) - -#define TIFR _SFR_IO8(0x38) -#define TIMSK _SFR_IO8(0x39) - -#define GIFR _SFR_IO8(0x3A) -#define GIMSK _SFR_IO8(0x3B) -#define GICR _SFR_IO8(0x3B) /* Changed in 2486H-AVR-09/02 */ - -/* 0x3C reserved (OCR0?) */ - -/* 0x3D..0x3E SP */ - -/* 0x3F SREG */ - -/* Interrupt vectors */ - -/* External Interrupt Request 0 */ -#define INT0_vect_num 1 -#define INT0_vect _VECTOR(1) -#define SIG_INTERRUPT0 _VECTOR(1) - -/* External Interrupt Request 1 */ -#define INT1_vect_num 2 -#define INT1_vect _VECTOR(2) -#define SIG_INTERRUPT1 _VECTOR(2) - -/* Timer/Counter2 Compare Match */ -#define TIMER2_COMP_vect_num 3 -#define TIMER2_COMP_vect _VECTOR(3) -#define SIG_OUTPUT_COMPARE2 _VECTOR(3) - -/* Timer/Counter2 Overflow */ -#define TIMER2_OVF_vect_num 4 -#define TIMER2_OVF_vect _VECTOR(4) -#define SIG_OVERFLOW2 _VECTOR(4) - -/* Timer/Counter1 Capture Event */ -#define TIMER1_CAPT_vect_num 5 -#define TIMER1_CAPT_vect _VECTOR(5) -#define SIG_INPUT_CAPTURE1 _VECTOR(5) - -/* Timer/Counter1 Compare Match A */ -#define TIMER1_COMPA_vect_num 6 -#define TIMER1_COMPA_vect _VECTOR(6) -#define SIG_OUTPUT_COMPARE1A _VECTOR(6) - -/* Timer/Counter1 Compare Match B */ -#define TIMER1_COMPB_vect_num 7 -#define TIMER1_COMPB_vect _VECTOR(7) -#define SIG_OUTPUT_COMPARE1B _VECTOR(7) - -/* Timer/Counter1 Overflow */ -#define TIMER1_OVF_vect_num 8 -#define TIMER1_OVF_vect _VECTOR(8) -#define SIG_OVERFLOW1 _VECTOR(8) - -/* Timer/Counter0 Overflow */ -#define TIMER0_OVF_vect_num 9 -#define TIMER0_OVF_vect _VECTOR(9) -#define SIG_OVERFLOW0 _VECTOR(9) - -/* Serial Transfer Complete */ -#define SPI_STC_vect_num 10 -#define SPI_STC_vect _VECTOR(10) -#define SIG_SPI _VECTOR(10) - -/* USART, Rx Complete */ -#define USART_RXC_vect_num 11 -#define USART_RXC_vect _VECTOR(11) -#define SIG_UART_RECV _VECTOR(11) - -/* USART Data Register Empty */ -#define USART_UDRE_vect_num 12 -#define USART_UDRE_vect _VECTOR(12) -#define SIG_UART_DATA _VECTOR(12) - -/* USART, Tx Complete */ -#define USART_TXC_vect_num 13 -#define USART_TXC_vect _VECTOR(13) -#define SIG_UART_TRANS _VECTOR(13) - -/* ADC Conversion Complete */ -#define ADC_vect_num 14 -#define ADC_vect _VECTOR(14) -#define SIG_ADC _VECTOR(14) - -/* EEPROM Ready */ -#define EE_RDY_vect_num 15 -#define EE_RDY_vect _VECTOR(15) -#define SIG_EEPROM_READY _VECTOR(15) - -/* Analog Comparator */ -#define ANA_COMP_vect_num 16 -#define ANA_COMP_vect _VECTOR(16) -#define SIG_COMPARATOR _VECTOR(16) - -/* 2-wire Serial Interface */ -#define TWI_vect_num 17 -#define TWI_vect _VECTOR(17) -#define SIG_2WIRE_SERIAL _VECTOR(17) - -/* Store Program Memory Ready */ -#define SPM_RDY_vect_num 18 -#define SPM_RDY_vect _VECTOR(18) -#define SIG_SPM_READY _VECTOR(18) - -#define _VECTORS_SIZE 38 - -/* Bit numbers */ - -/* GIMSK / GICR */ -#define INT1 7 -#define INT0 6 -#define IVSEL 1 -#define IVCE 0 - -/* GIFR */ -#define INTF1 7 -#define INTF0 6 - -/* TIMSK */ -#define OCIE2 7 -#define TOIE2 6 -#define TICIE1 5 -#define OCIE1A 4 -#define OCIE1B 3 -#define TOIE1 2 -/* bit 1 reserved (OCIE0?) */ -#define TOIE0 0 - -/* TIFR */ -#define OCF2 7 -#define TOV2 6 -#define ICF1 5 -#define OCF1A 4 -#define OCF1B 3 -#define TOV1 2 -/* bit 1 reserved (OCF0?) */ -#define TOV0 0 - -/* SPMCR */ -#define SPMIE 7 -#define RWWSB 6 -/* bit 5 reserved */ -#define RWWSRE 4 -#define BLBSET 3 -#define PGWRT 2 -#define PGERS 1 -#define SPMEN 0 - -/* TWCR */ -#define TWINT 7 -#define TWEA 6 -#define TWSTA 5 -#define TWSTO 4 -#define TWWC 3 -#define TWEN 2 -/* bit 1 reserved (TWI_TST?) */ -#define TWIE 0 - -/* TWAR */ -#define TWA6 7 -#define TWA5 6 -#define TWA4 5 -#define TWA3 4 -#define TWA2 3 -#define TWA1 2 -#define TWA0 1 -#define TWGCE 0 - -/* TWSR */ -#define TWS7 7 -#define TWS6 6 -#define TWS5 5 -#define TWS4 4 -#define TWS3 3 -/* bit 2 reserved */ -#define TWPS1 1 -#define TWPS0 0 - -/* MCUCR */ -#define SE 7 -#define SM2 6 -#define SM1 5 -#define SM0 4 -#define ISC11 3 -#define ISC10 2 -#define ISC01 1 -#define ISC00 0 - -/* MCUCSR */ -/* bits 7-4 reserved */ -#define WDRF 3 -#define BORF 2 -#define EXTRF 1 -#define PORF 0 - -/* - The ADHSM bit has been removed from all documentation, - as being not needed at all since the comparator has proven - to be fast enough even without feeding it more power. -*/ - -/* SFIOR */ -/* bits 7-5 reserved */ -#define ACME 3 -#define PUD 2 -#define PSR2 1 -#define PSR10 0 - -/* TCCR0 */ -/* bits 7-3 reserved */ -#define CS02 2 -#define CS01 1 -#define CS00 0 - -/* TCCR2 */ -#define FOC2 7 -#define WGM20 6 -#define COM21 5 -#define COM20 4 -#define WGM21 3 -#define CS22 2 -#define CS21 1 -#define CS20 0 - -/* ASSR */ -/* bits 7-4 reserved */ -#define AS2 3 -#define TCN2UB 2 -#define OCR2UB 1 -#define TCR2UB 0 - -/* TCCR1A */ -#define COM1A1 7 -#define COM1A0 6 -#define COM1B1 5 -#define COM1B0 4 -#define FOC1A 3 -#define FOC1B 2 -#define WGM11 1 -#define WGM10 0 - -/* TCCR1B */ -#define ICNC1 7 -#define ICES1 6 -/* bit 5 reserved */ -#define WGM13 4 -#define WGM12 3 -#define CS12 2 -#define CS11 1 -#define CS10 0 - -/* WDTCR */ -/* bits 7-5 reserved */ -#define WDCE 4 -#define WDE 3 -#define WDP2 2 -#define WDP1 1 -#define WDP0 0 - -/* UBRRH */ -#define URSEL 7 - -/* UCSRC */ -#define URSEL 7 -#define UMSEL 6 -#define UPM1 5 -#define UPM0 4 -#define USBS 3 -#define UCSZ1 2 -#define UCSZ0 1 -#define UCPOL 0 - -/* PORTB */ -#define PB7 7 -#define PB6 6 -#define PB5 5 -#define PB4 4 -#define PB3 3 -#define PB2 2 -#define PB1 1 -#define PB0 0 - -/* DDRB */ -#define DDB7 7 -#define DDB6 6 -#define DDB5 5 -#define DDB4 4 -#define DDB3 3 -#define DDB2 2 -#define DDB1 1 -#define DDB0 0 - -/* PINB */ -#define PINB7 7 -#define PINB6 6 -#define PINB5 5 -#define PINB4 4 -#define PINB3 3 -#define PINB2 2 -#define PINB1 1 -#define PINB0 0 - -/* PORTC */ -#define PC6 6 -#define PC5 5 -#define PC4 4 -#define PC3 3 -#define PC2 2 -#define PC1 1 -#define PC0 0 - -/* DDRC */ -#define DDC6 6 -#define DDC5 5 -#define DDC4 4 -#define DDC3 3 -#define DDC2 2 -#define DDC1 1 -#define DDC0 0 - -/* PINC */ -#define PINC6 6 -#define PINC5 5 -#define PINC4 4 -#define PINC3 3 -#define PINC2 2 -#define PINC1 1 -#define PINC0 0 - -/* PORTD */ -#define PD7 7 -#define PD6 6 -#define PD5 5 -#define PD4 4 -#define PD3 3 -#define PD2 2 -#define PD1 1 -#define PD0 0 - -/* DDRD */ -#define DDD7 7 -#define DDD6 6 -#define DDD5 5 -#define DDD4 4 -#define DDD3 3 -#define DDD2 2 -#define DDD1 1 -#define DDD0 0 - -/* PIND */ -#define PIND7 7 -#define PIND6 6 -#define PIND5 5 -#define PIND4 4 -#define PIND3 3 -#define PIND2 2 -#define PIND1 1 -#define PIND0 0 - -/* SPSR */ -#define SPIF 7 -#define WCOL 6 -#define SPI2X 0 - -/* SPCR */ -#define SPIE 7 -#define SPE 6 -#define DORD 5 -#define MSTR 4 -#define CPOL 3 -#define CPHA 2 -#define SPR1 1 -#define SPR0 0 - -/* UCSRA */ -#define RXC 7 -#define TXC 6 -#define UDRE 5 -#define FE 4 -#define DOR 3 -#define PE 2 -#define U2X 1 -#define MPCM 0 - -/* UCSRB */ -#define RXCIE 7 -#define TXCIE 6 -#define UDRIE 5 -#define RXEN 4 -#define TXEN 3 -#define UCSZ2 2 -#define RXB8 1 -#define TXB8 0 - -/* ACSR */ -#define ACD 7 -#define ACBG 6 -#define ACO 5 -#define ACI 4 -#define ACIE 3 -#define ACIC 2 -#define ACIS1 1 -#define ACIS0 0 - -/* ADCSR / ADCSRA */ -#define ADEN 7 -#define ADSC 6 -#define ADFR 5 -#define ADIF 4 -#define ADIE 3 -#define ADPS2 2 -#define ADPS1 1 -#define ADPS0 0 - -/* ADMUX */ -#define REFS1 7 -#define REFS0 6 -#define ADLAR 5 -/* bit 4 reserved */ -#define MUX3 3 -#define MUX2 2 -#define MUX1 1 -#define MUX0 0 - -/* EEPROM Control Register */ -#define EERIE 3 -#define EEMWE 2 -#define EEWE 1 -#define EERE 0 - -/* Constants */ -#define SPM_PAGESIZE 64 -#define RAMSTART (0x60) -#define RAMEND 0x45F -#define XRAMEND RAMEND -#define E2END 0x1FF -#define E2PAGESIZE 4 -#define FLASHEND 0x1FFF - - -/* Fuses */ - -#define FUSE_MEMORY_SIZE 2 - -/* Low Fuse Byte */ -#define FUSE_CKSEL0 (unsigned char)~_BV(0) -#define FUSE_CKSEL1 (unsigned char)~_BV(1) -#define FUSE_CKSEL2 (unsigned char)~_BV(2) -#define FUSE_CKSEL3 (unsigned char)~_BV(3) -#define FUSE_SUT0 (unsigned char)~_BV(4) -#define FUSE_SUT1 (unsigned char)~_BV(5) -#define FUSE_BODEN (unsigned char)~_BV(6) -#define FUSE_BODLEVEL (unsigned char)~_BV(7) -#define LFUSE_DEFAULT (FUSE_SUT0 & FUSE_CKSEL3 & FUSE_CKSEL2 & FUSE_CKSEL1) - -/* High Fuse Byte */ -#define FUSE_BOOTRST (unsigned char)~_BV(0) -#define FUSE_BOOTSZ0 (unsigned char)~_BV(1) -#define FUSE_BOOTSZ1 (unsigned char)~_BV(2) -#define FUSE_EESAVE (unsigned char)~_BV(3) -#define FUSE_CKOPT (unsigned char)~_BV(4) -#define FUSE_SPIEN (unsigned char)~_BV(5) -#define FUSE_WDTON (unsigned char)~_BV(6) -#define FUSE_RSTDISBL (unsigned char)~_BV(7) -#define HFUSE_DEFAULT (FUSE_SPIEN & FUSE_BOOTSZ1 & FUSE_BOOTSZ0) - - -/* Lock Bits */ -#define __LOCK_BITS_EXIST -#define __BOOT_LOCK_BITS_0_EXIST -#define __BOOT_LOCK_BITS_1_EXIST - - -/* Signature */ -#define SIGNATURE_0 0x1E -#define SIGNATURE_1 0x93 -#define SIGNATURE_2 0x07 - - -/* Deprecated items */ -#if !defined(__AVR_LIBC_DEPRECATED_ENABLE__) - -#pragma GCC system_header - -#pragma GCC poison SIG_INTERRUPT0 -#pragma GCC poison SIG_INTERRUPT1 -#pragma GCC poison SIG_OUTPUT_COMPARE2 -#pragma GCC poison SIG_OVERFLOW2 -#pragma GCC poison SIG_INPUT_CAPTURE1 -#pragma GCC poison SIG_OUTPUT_COMPARE1A -#pragma GCC poison SIG_OUTPUT_COMPARE1B -#pragma GCC poison SIG_OVERFLOW1 -#pragma GCC poison SIG_OVERFLOW0 -#pragma GCC poison SIG_SPI -#pragma GCC poison SIG_UART_RECV -#pragma GCC poison SIG_UART_DATA -#pragma GCC poison SIG_UART_TRANS -#pragma GCC poison SIG_ADC -#pragma GCC poison SIG_EEPROM_READY -#pragma GCC poison SIG_COMPARATOR -#pragma GCC poison SIG_2WIRE_SERIAL -#pragma GCC poison SIG_SPM_READY - -#endif /* !defined(__AVR_LIBC_DEPRECATED_ENABLE__) */ - -#define SLEEP_MODE_IDLE (0x00<<4) -#define SLEEP_MODE_ADC (0x01<<4) -#define SLEEP_MODE_PWR_DOWN (0x02<<4) -#define SLEEP_MODE_PWR_SAVE (0x03<<4) -#define SLEEP_MODE_STANDBY (0x06<<4) - -#endif /* _AVR_IOM8_H_ */ diff --git a/arduino/hardware/tools/avr/avr/include/avr/iom8515.h b/arduino/hardware/tools/avr/avr/include/avr/iom8515.h deleted file mode 100644 index c49dc83..0000000 --- a/arduino/hardware/tools/avr/avr/include/avr/iom8515.h +++ /dev/null @@ -1,687 +0,0 @@ -/* Copyright (c) 2002, Steinar Haugen - All rights reserved. - - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - * Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - * Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in - the documentation and/or other materials provided with the - distribution. - - * Neither the name of the copyright holders nor the names of - contributors may be used to endorse or promote products derived - from this software without specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. */ - -/* $Id: iom8515.h 2235 2011-03-17 04:13:14Z arcanum $ */ - -/* avr/iom8515.h - definitions for ATmega8515 */ - -#ifndef _AVR_IOM8515_H_ -#define _AVR_IOM8515_H_ 1 - -/* This file should only be included from , never directly. */ - -#ifndef _AVR_IO_H_ -# error "Include instead of this file." -#endif - -#ifndef _AVR_IOXXX_H_ -# define _AVR_IOXXX_H_ "iom8515.h" -#else -# error "Attempt to include more than one file." -#endif - -/* I/O registers */ - -/* Oscillator Calibration Register */ -#define OSCCAL _SFR_IO8(0x04) - -/* Input Pins, Port E */ -#define PINE _SFR_IO8(0x05) - -/* Data Direction Register, Port E */ -#define DDRE _SFR_IO8(0x06) - -/* Data Register, Port E */ -#define PORTE _SFR_IO8(0x07) - -/* Analog Comparator Control and Status Register */ -#define ACSR _SFR_IO8(0x08) - -/* USART Baud Rate Register */ -#define UBRRL _SFR_IO8(0x09) - -/* USART Control and Status Register B */ -#define UCSRB _SFR_IO8(0x0A) - -/* USART Control and Status Register A */ -#define UCSRA _SFR_IO8(0x0B) - -/* USART I/O Data Register */ -#define UDR _SFR_IO8(0x0C) - -/* SPI Control Register */ -#define SPCR _SFR_IO8(0x0D) - -/* SPI Status Register */ -#define SPSR _SFR_IO8(0x0E) - -/* SPI I/O Data Register */ -#define SPDR _SFR_IO8(0x0F) - -/* Input Pins, Port D */ -#define PIND _SFR_IO8(0x10) - -/* Data Direction Register, Port D */ -#define DDRD _SFR_IO8(0x11) - -/* Data Register, Port D */ -#define PORTD _SFR_IO8(0x12) - -/* Input Pins, Port C */ -#define PINC _SFR_IO8(0x13) - -/* Data Direction Register, Port C */ -#define DDRC _SFR_IO8(0x14) - -/* Data Register, Port C */ -#define PORTC _SFR_IO8(0x15) - -/* Input Pins, Port B */ -#define PINB _SFR_IO8(0x16) - -/* Data Direction Register, Port B */ -#define DDRB _SFR_IO8(0x17) - -/* Data Register, Port B */ -#define PORTB _SFR_IO8(0x18) - -/* Input Pins, Port A */ -#define PINA _SFR_IO8(0x19) - -/* Data Direction Register, Port A */ -#define DDRA _SFR_IO8(0x1A) - -/* Data Register, Port A */ -#define PORTA _SFR_IO8(0x1B) - -/* EEPROM Control Register */ -#define EECR _SFR_IO8(0x1C) - -/* EEPROM Data Register */ -#define EEDR _SFR_IO8(0x1D) - -/* EEPROM Address Register */ -#define EEAR _SFR_IO16(0x1E) -#define EEARL _SFR_IO8(0x1E) -#define EEARH _SFR_IO8(0x1F) - -/* USART Baud Rate Register HI */ -/* USART Control and Status Register C */ -#define UBRRH _SFR_IO8(0x20) -#define UCSRC UBRRH - -/* Watchdog Timer Control Register */ -#define WDTCR _SFR_IO8(0x21) - -/* T/C 1 Input Capture Register */ -#define ICR1 _SFR_IO16(0x24) -#define ICR1L _SFR_IO8(0x24) -#define ICR1H _SFR_IO8(0x25) - -/* Timer/Counter1 Output Compare Register B */ -#define OCR1B _SFR_IO16(0x28) -#define OCR1BL _SFR_IO8(0x28) -#define OCR1BH _SFR_IO8(0x29) - -/* Timer/Counter1 Output Compare Register A */ -#define OCR1A _SFR_IO16(0x2A) -#define OCR1AL _SFR_IO8(0x2A) -#define OCR1AH _SFR_IO8(0x2B) - -/* Timer/Counter 1 */ -#define TCNT1 _SFR_IO16(0x2C) -#define TCNT1L _SFR_IO8(0x2C) -#define TCNT1H _SFR_IO8(0x2D) - -/* Timer/Counter 1 Control and Status Register */ -#define TCCR1B _SFR_IO8(0x2E) - -/* Timer/Counter 1 Control Register */ -#define TCCR1A _SFR_IO8(0x2F) - -/* Special Function IO Register */ -#define SFIOR _SFR_IO8(0x30) - -/* Timer/Counter 0 Output Compare Register */ -#define OCR0 _SFR_IO8(0x31) - -/* Timer/Counter 0 */ -#define TCNT0 _SFR_IO8(0x32) - -/* Timer/Counter 0 Control Register */ -#define TCCR0 _SFR_IO8(0x33) - -/* MCU Control and Status Register */ -#define MCUCSR _SFR_IO8(0x34) - -/* MCU Control Register */ -#define MCUCR _SFR_IO8(0x35) - -/* Extended MCU Control Register */ -#define EMCUCR _SFR_IO8(0x36) - -/* Store Program Memory Control Register */ -#define SPMCR _SFR_IO8(0x37) - -/* Timer/Counter Interrupt Flag register */ -#define TIFR _SFR_IO8(0x38) - -/* Timer/Counter Interrupt MaSK register */ -#define TIMSK _SFR_IO8(0x39) - -/* General Interrupt Flag Register */ -#define GIFR _SFR_IO8(0x3A) - -/* General Interrupt Control Register */ -#define GICR _SFR_IO8(0x3B) - -/* 0x3D..0x3E SP */ - -/* 0x3F SREG */ - -/* Interrupt vectors */ - -/* External Interrupt Request 0 */ -#define INT0_vect_num 1 -#define INT0_vect _VECTOR(1) -#define SIG_INTERRUPT0 _VECTOR(1) - -/* External Interrupt Request 1 */ -#define INT1_vect_num 2 -#define INT1_vect _VECTOR(2) -#define SIG_INTERRUPT1 _VECTOR(2) - -/* Timer/Counter1 Capture Event */ -#define TIMER1_CAPT_vect_num 3 -#define TIMER1_CAPT_vect _VECTOR(3) -#define SIG_INPUT_CAPTURE1 _VECTOR(3) - -/* Timer/Counter1 Compare Match A */ -#define TIMER1_COMPA_vect_num 4 -#define TIMER1_COMPA_vect _VECTOR(4) -#define SIG_OUTPUT_COMPARE1A _VECTOR(4) - -/* Timer/Counter1 Compare MatchB */ -#define TIMER1_COMPB_vect_num 5 -#define TIMER1_COMPB_vect _VECTOR(5) -#define SIG_OUTPUT_COMPARE1B _VECTOR(5) - -/* Timer/Counter1 Overflow */ -#define TIMER1_OVF_vect_num 6 -#define TIMER1_OVF_vect _VECTOR(6) -#define SIG_OVERFLOW1 _VECTOR(6) - -/* Timer/Counter0 Overflow */ -#define TIMER0_OVF_vect_num 7 -#define TIMER0_OVF_vect _VECTOR(7) -#define SIG_OVERFLOW0 _VECTOR(7) - -/* Serial Transfer Complete */ -#define SPI_STC_vect_num 8 -#define SPI_STC_vect _VECTOR(8) -#define SIG_SPI _VECTOR(8) - -/* UART, Rx Complete */ -#define USART_RX_vect_num 9 -#define USART_RX_vect _VECTOR(9) -#define UART_RX_vect _VECTOR(9) /* For compatability only */ -#define SIG_UART_RECV _VECTOR(9) /* For compatability only */ - -/* UART Data Register Empty */ -#define USART_UDRE_vect_num 10 -#define USART_UDRE_vect _VECTOR(10) -#define UART_UDRE_vect _VECTOR(10) /* For compatability only */ -#define SIG_UART_DATA _VECTOR(10) /* For compatability only */ - -/* UART, Tx Complete */ -#define USART_TX_vect_num 11 -#define USART_TX_vect _VECTOR(11) -#define UART_TX_vect _VECTOR(11) /* For compatability only */ -#define SIG_UART_TRANS _VECTOR(11) /* For compatability only */ - -/* Analog Comparator */ -#define ANA_COMP_vect_num 12 -#define ANA_COMP_vect _VECTOR(12) -#define SIG_COMPARATOR _VECTOR(12) - -/* External Interrupt Request 2 */ -#define INT2_vect_num 13 -#define INT2_vect _VECTOR(13) -#define SIG_INTERRUPT2 _VECTOR(13) - -/* Timer 0 Compare Match */ -#define TIMER0_COMP_vect_num 14 -#define TIMER0_COMP_vect _VECTOR(14) -#define SIG_OUTPUT_COMPARE0 _VECTOR(14) - -/* EEPROM Ready */ -#define EE_RDY_vect_num 15 -#define EE_RDY_vect _VECTOR(15) -#define SIG_EEPROM_READY _VECTOR(15) - -/* Store Program Memory Ready */ -#define SPM_RDY_vect_num 16 -#define SPM_RDY_vect _VECTOR(16) -#define SIG_SPM_READY _VECTOR(16) - -#define _VECTORS_SIZE 34 - -/* - The Register Bit names are represented by their bit number (0-7). -*/ - -/* General Interrupt Control Register */ -#define INT1 7 -#define INT0 6 -#define INT2 5 -#define IVSEL 1 -#define IVCE 0 - -/* General Interrupt Flag Register */ -#define INTF1 7 -#define INTF0 6 -#define INTF2 5 - -/* Timer/Counter Interrupt MaSK Register */ -#define TOIE1 7 -#define OCIE1A 6 -#define OCIE1B 5 -#define TICIE1 3 -#define TOIE0 1 -#define OCIE0 0 - -/* Timer/Counter Interrupt Flag Register */ -#define TOV1 7 -#define OCF1A 6 -#define OCF1B 5 -#define ICF1 3 -#define TOV0 1 -#define OCF0 0 - -/* Store Program Memory Control Register */ -#define SPMIE 7 -#define RWWSB 6 -#define RWWSRE 4 -#define BLBSET 3 -#define PGWRT 2 -#define PGERS 1 -#define SPMEN 0 - -/* Extended MCU Control Register */ -#define SM0 7 -#define SRL2 6 -#define SRL1 5 -#define SRL0 4 -#define SRW01 3 -#define SRW00 2 -#define SRW11 1 -#define ISC2 0 - -/* MCU Control Register */ -#define SRE 7 -#define SRW10 6 -#define SE 5 -#define SM1 4 -#define ISC11 3 -#define ISC10 2 -#define ISC01 1 -#define ISC00 0 - -/* MCU Control and Status Register */ -#define SM2 5 -#define WDRF 3 -#define BORF 2 -#define EXTRF 1 -#define PORF 0 - -/* Timer/Counter 0 Control Register */ -#define FOC0 7 -#define WGM00 6 -#define COM01 5 -#define COM00 4 -#define WGM01 3 -#define CS02 2 -#define CS01 1 -#define CS00 0 - -/* Special Function IO Register */ -#define XMBK 6 -#define XMM2 5 -#define XMM1 4 -#define XMM0 3 -#define PUD 2 -#define PSR10 0 - -/* Timer/Counter 1 Control Register */ -#define COM1A1 7 -#define COM1A0 6 -#define COM1B1 5 -#define COM1B0 4 -#define FOC1A 3 -#define FOC1B 2 -#define WGM11 1 -#define WGM10 0 - -/* Timer/Counter 1 Control and Status Register */ -#define ICNC1 7 -#define ICES1 6 -#define WGM13 4 -#define WGM12 3 -#define CS12 2 -#define CS11 1 -#define CS10 0 - -/* Watchdog Timer Control Register */ -#define WDCE 4 -#define WDE 3 -#define WDP2 2 -#define WDP1 1 -#define WDP0 0 - -/* USART Control and Status Register C */ -#define URSEL 7 -#define UMSEL 6 -#define UPM1 5 -#define UPM0 4 -#define USBS 3 -#define UCSZ1 2 -#define UCSZ0 1 -#define UCPOL 0 - -/* Data Register, Port A */ -#define PA7 7 -#define PA6 6 -#define PA5 5 -#define PA4 4 -#define PA3 3 -#define PA2 2 -#define PA1 1 -#define PA0 0 - -/* Data Direction Register, Port A */ -#define DDA7 7 -#define DDA6 6 -#define DDA5 5 -#define DDA4 4 -#define DDA3 3 -#define DDA2 2 -#define DDA1 1 -#define DDA0 0 - -/* Input Pins, Port A */ -#define PINA7 7 -#define PINA6 6 -#define PINA5 5 -#define PINA4 4 -#define PINA3 3 -#define PINA2 2 -#define PINA1 1 -#define PINA0 0 - -/* Data Register, Port B */ -#define PB7 7 -#define PB6 6 -#define PB5 5 -#define PB4 4 -#define PB3 3 -#define PB2 2 -#define PB1 1 -#define PB0 0 - -/* Data Direction Register, Port B */ -#define DDB7 7 -#define DDB6 6 -#define DDB5 5 -#define DDB4 4 -#define DDB3 3 -#define DDB2 2 -#define DDB1 1 -#define DDB0 0 - -/* Input Pins, Port B */ -#define PINB7 7 -#define PINB6 6 -#define PINB5 5 -#define PINB4 4 -#define PINB3 3 -#define PINB2 2 -#define PINB1 1 -#define PINB0 0 - -/* Data Register, Port C */ -#define PC7 7 -#define PC6 6 -#define PC5 5 -#define PC4 4 -#define PC3 3 -#define PC2 2 -#define PC1 1 -#define PC0 0 - -/* Data Direction Register, Port C */ -#define DDC7 7 -#define DDC6 6 -#define DDC5 5 -#define DDC4 4 -#define DDC3 3 -#define DDC2 2 -#define DDC1 1 -#define DDC0 0 - -/* Input Pins, Port C */ -#define PINC7 7 -#define PINC6 6 -#define PINC5 5 -#define PINC4 4 -#define PINC3 3 -#define PINC2 2 -#define PINC1 1 -#define PINC0 0 - -/* Data Register, Port D */ -#define PD7 7 -#define PD6 6 -#define PD5 5 -#define PD4 4 -#define PD3 3 -#define PD2 2 -#define PD1 1 -#define PD0 0 - -/* Data Direction Register, Port D */ -#define DDD7 7 -#define DDD6 6 -#define DDD5 5 -#define DDD4 4 -#define DDD3 3 -#define DDD2 2 -#define DDD1 1 -#define DDD0 0 - -/* Input Pins, Port D */ -#define PIND7 7 -#define PIND6 6 -#define PIND5 5 -#define PIND4 4 -#define PIND3 3 -#define PIND2 2 -#define PIND1 1 -#define PIND0 0 - -/* SPI Status Register */ -#define SPIF 7 -#define WCOL 6 -#define SPI2X 0 - -/* SPI Control Register */ -#define SPIE 7 -#define SPE 6 -#define DORD 5 -#define MSTR 4 -#define CPOL 3 -#define CPHA 2 -#define SPR1 1 -#define SPR0 0 - -/* USART Control and Status Register A */ -#define RXC 7 -#define TXC 6 -#define UDRE 5 -#define FE 4 -#define DOR 3 -#define PE 2 -#define U2X 1 -#define MPCM 0 - -/* USART Control and Status Register B */ -#define RXCIE 7 -#define TXCIE 6 -#define UDRIE 5 -#define RXEN 4 -#define TXEN 3 -#define UCSZ2 2 -#define RXB8 1 -#define TXB8 0 - -/* Analog Comparator Control and Status Register */ -#define ACD 7 -#define ACBG 6 -#define ACO 5 -#define ACI 4 -#define ACIE 3 -#define ACIC 2 -#define ACIS1 1 -#define ACIS0 0 - -/* Data Register, Port E */ -#define PE2 2 -#define PE1 1 -#define PE0 0 - -/* Data Direction Register, Port E */ -#define DDE2 2 -#define DDE1 1 -#define DDE0 0 - -/* Input Pins, Port E */ -#define PINE2 2 -#define PINE1 1 -#define PINE0 0 - -/* EEPROM Control Register */ -#define EERIE 3 -#define EEMWE 2 -#define EEWE 1 -#define EERE 0 - -/* Constants */ -#define SPM_PAGESIZE 64 -#define RAMSTART (0x60) -#define RAMEND 0x25F /* Last On-Chip SRAM Location */ -#define XRAMEND 0xFFFF -#define E2END 0x1FF -#define E2PAGESIZE 4 -#define FLASHEND 0x1FFF - - -/* Fuses */ - -#define FUSE_MEMORY_SIZE 2 - -/* Low Fuse Byte */ -#define FUSE_CKSEL0 (unsigned char)~_BV(0) -#define FUSE_CKSEL1 (unsigned char)~_BV(1) -#define FUSE_CKSEL2 (unsigned char)~_BV(2) -#define FUSE_CKSEL3 (unsigned char)~_BV(3) -#define FUSE_SUT0 (unsigned char)~_BV(4) -#define FUSE_SUT1 (unsigned char)~_BV(5) -#define FUSE_BODEN (unsigned char)~_BV(6) -#define FUSE_BODLEVEL (unsigned char)~_BV(7) -#define LFUSE_DEFAULT (FUSE_CKSEL1 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0) - -/* High Fuse Byte */ -#define FUSE_BOOTRST (unsigned char)~_BV(0) -#define FUSE_BOOTSZ0 (unsigned char)~_BV(1) -#define FUSE_BOOTSZ1 (unsigned char)~_BV(2) -#define FUSE_EESAVE (unsigned char)~_BV(3) -#define FUSE_CKOPT (unsigned char)~_BV(4) -#define FUSE_SPIEN (unsigned char)~_BV(5) -#define FUSE_WDTON (unsigned char)~_BV(6) -#define FUSE_S8515C (unsigned char)~_BV(7) -#define HFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_SPIEN) - - -/* Lock Bits */ -#define __LOCK_BITS_EXIST -#define __BOOT_LOCK_BITS_0_EXIST -#define __BOOT_LOCK_BITS_1_EXIST - - -/* Signature */ -#define SIGNATURE_0 0x1E -#define SIGNATURE_1 0x93 -#define SIGNATURE_2 0x06 - - -/* Deprecated items */ -#if !defined(__AVR_LIBC_DEPRECATED_ENABLE__) - -#pragma GCC system_header - -#pragma GCC poison SIG_INTERRUPT0 -#pragma GCC poison SIG_INTERRUPT1 -#pragma GCC poison SIG_INPUT_CAPTURE1 -#pragma GCC poison SIG_OUTPUT_COMPARE1A -#pragma GCC poison SIG_OUTPUT_COMPARE1B -#pragma GCC poison SIG_OVERFLOW1 -#pragma GCC poison SIG_OVERFLOW0 -#pragma GCC poison SIG_SPI -#pragma GCC poison UART_RX_vect -#pragma GCC poison SIG_UART_RECV -#pragma GCC poison UART_UDRE_vect -#pragma GCC poison SIG_UART_DATA -#pragma GCC poison UART_TX_vect -#pragma GCC poison SIG_UART_TRANS -#pragma GCC poison SIG_COMPARATOR -#pragma GCC poison SIG_INTERRUPT2 -#pragma GCC poison SIG_OUTPUT_COMPARE0 -#pragma GCC poison SIG_EEPROM_READY -#pragma GCC poison SIG_SPM_READY - -#endif /* !defined(__AVR_LIBC_DEPRECATED_ENABLE__) */ - -#define SLEEP_MODE_IDLE 0 -#define SLEEP_MODE_PWR_DOWN 1 -#define SLEEP_MODE_PWR_SAVE 2 -#define SLEEP_MODE_ADC 3 -#define SLEEP_MODE_STANDBY 4 -#define SLEEP_MODE_EXT_STANDBY 5 - -#endif /* _AVR_IOM8515_H_ */ diff --git a/arduino/hardware/tools/avr/avr/include/avr/iom8535.h b/arduino/hardware/tools/avr/avr/include/avr/iom8535.h deleted file mode 100644 index 8cfa744..0000000 --- a/arduino/hardware/tools/avr/avr/include/avr/iom8535.h +++ /dev/null @@ -1,772 +0,0 @@ -/* Copyright (c) 2002, Steinar Haugen - All rights reserved. - - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - * Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - * Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in - the documentation and/or other materials provided with the - distribution. - - * Neither the name of the copyright holders nor the names of - contributors may be used to endorse or promote products derived - from this software without specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. */ - -/* $Id: iom8535.h 2235 2011-03-17 04:13:14Z arcanum $ */ - -/* avr/iom8535.h - definitions for ATmega8535 */ - -#ifndef _AVR_IOM8535_H_ -#define _AVR_IOM8535_H_ 1 - -/* This file should only be included from , never directly. */ - -#ifndef _AVR_IO_H_ -# error "Include instead of this file." -#endif - -#ifndef _AVR_IOXXX_H_ -# define _AVR_IOXXX_H_ "iom8535.h" -#else -# error "Attempt to include more than one file." -#endif - -/* I/O registers */ - -/* TWI stands for "Two Wire Interface" or "TWI Was I2C(tm)" */ -#define TWBR _SFR_IO8(0x00) -#define TWSR _SFR_IO8(0x01) -#define TWAR _SFR_IO8(0x02) -#define TWDR _SFR_IO8(0x03) - -/* ADC Data register */ -#ifndef __ASSEMBLER__ -#define ADC _SFR_IO16(0x04) -#endif -#define ADCW _SFR_IO16(0x04) -#define ADCL _SFR_IO8(0x04) -#define ADCH _SFR_IO8(0x05) - -/* ADC Control and Status Register */ -#define ADCSRA _SFR_IO8(0x06) - -/* ADC MUX */ -#define ADMUX _SFR_IO8(0x07) - -/* Analog Comparator Control and Status Register */ -#define ACSR _SFR_IO8(0x08) - -/* USART Baud Rate Register */ -#define UBRRL _SFR_IO8(0x09) - -/* USART Control and Status Register B */ -#define UCSRB _SFR_IO8(0x0A) - -/* USART Control and Status Register A */ -#define UCSRA _SFR_IO8(0x0B) - -/* USART I/O Data Register */ -#define UDR _SFR_IO8(0x0C) - -/* SPI Control Register */ -#define SPCR _SFR_IO8(0x0D) - -/* SPI Status Register */ -#define SPSR _SFR_IO8(0x0E) - -/* SPI I/O Data Register */ -#define SPDR _SFR_IO8(0x0F) - -/* Input Pins, Port D */ -#define PIND _SFR_IO8(0x10) - -/* Data Direction Register, Port D */ -#define DDRD _SFR_IO8(0x11) - -/* Data Register, Port D */ -#define PORTD _SFR_IO8(0x12) - -/* Input Pins, Port C */ -#define PINC _SFR_IO8(0x13) - -/* Data Direction Register, Port C */ -#define DDRC _SFR_IO8(0x14) - -/* Data Register, Port C */ -#define PORTC _SFR_IO8(0x15) - -/* Input Pins, Port B */ -#define PINB _SFR_IO8(0x16) - -/* Data Direction Register, Port B */ -#define DDRB _SFR_IO8(0x17) - -/* Data Register, Port B */ -#define PORTB _SFR_IO8(0x18) - -/* Input Pins, Port A */ -#define PINA _SFR_IO8(0x19) - -/* Data Direction Register, Port A */ -#define DDRA _SFR_IO8(0x1A) - -/* Data Register, Port A */ -#define PORTA _SFR_IO8(0x1B) - -/* EEPROM Control Register */ -#define EECR _SFR_IO8(0x1C) - -/* EEPROM Data Register */ -#define EEDR _SFR_IO8(0x1D) - -/* EEPROM Address Register */ -#define EEAR _SFR_IO16(0x1E) -#define EEARL _SFR_IO8(0x1E) -#define EEARH _SFR_IO8(0x1F) - -/* USART Baud Rate Register HI */ -/* USART Control and Status Register C */ -#define UBRRH _SFR_IO8(0x20) -#define UCSRC UBRRH - -/* Watchdog Timer Control Register */ -#define WDTCR _SFR_IO8(0x21) - -/* Asynchronous mode Status Register */ -#define ASSR _SFR_IO8(0x22) - -/* Timer/Counter2 Output Compare Register */ -#define OCR2 _SFR_IO8(0x23) - -/* Timer/Counter 2 */ -#define TCNT2 _SFR_IO8(0x24) - -/* Timer/Counter 2 Control Register */ -#define TCCR2 _SFR_IO8(0x25) - -/* T/C 1 Input Capture Register */ -#define ICR1 _SFR_IO16(0x26) -#define ICR1L _SFR_IO8(0x26) -#define ICR1H _SFR_IO8(0x27) - -/* Timer/Counter1 Output Compare Register B */ -#define OCR1B _SFR_IO16(0x28) -#define OCR1BL _SFR_IO8(0x28) -#define OCR1BH _SFR_IO8(0x29) - -/* Timer/Counter1 Output Compare Register A */ -#define OCR1A _SFR_IO16(0x2A) -#define OCR1AL _SFR_IO8(0x2A) -#define OCR1AH _SFR_IO8(0x2B) - -/* Timer/Counter 1 */ -#define TCNT1 _SFR_IO16(0x2C) -#define TCNT1L _SFR_IO8(0x2C) -#define TCNT1H _SFR_IO8(0x2D) - -/* Timer/Counter 1 Control and Status Register */ -#define TCCR1B _SFR_IO8(0x2E) - -/* Timer/Counter 1 Control Register */ -#define TCCR1A _SFR_IO8(0x2F) - -/* Special Function IO Register */ -#define SFIOR _SFR_IO8(0x30) - -/* Oscillator Calibration Register */ -#define OSCCAL _SFR_IO8(0x31) - -/* Timer/Counter 0 */ -#define TCNT0 _SFR_IO8(0x32) - -/* Timer/Counter 0 Control Register */ -#define TCCR0 _SFR_IO8(0x33) - -/* MCU Control and Status Register */ -#define MCUCSR _SFR_IO8(0x34) - -/* MCU Control Register */ -#define MCUCR _SFR_IO8(0x35) - -/* TWI Control Register */ -#define TWCR _SFR_IO8(0x36) - -/* Store Program Memory Control Register */ -#define SPMCR _SFR_IO8(0x37) - -/* Timer/Counter Interrupt Flag register */ -#define TIFR _SFR_IO8(0x38) - -/* Timer/Counter Interrupt MaSK register */ -#define TIMSK _SFR_IO8(0x39) - -/* General Interrupt Flag Register */ -#define GIFR _SFR_IO8(0x3A) - -/* General Interrupt MaSK register */ -#define GICR _SFR_IO8(0x3B) - -/* Timer/Counter 0 Output Compare Register */ -#define OCR0 _SFR_IO8(0x3C) - -/* 0x3D..0x3E SP */ - -/* 0x3F SREG */ - -/* Interrupt vectors */ - -/* External Interrupt 0 */ -#define INT0_vect_num 1 -#define INT0_vect _VECTOR(1) -#define SIG_INTERRUPT0 _VECTOR(1) - -/* External Interrupt 1 */ -#define INT1_vect_num 2 -#define INT1_vect _VECTOR(2) -#define SIG_INTERRUPT1 _VECTOR(2) - -/* Timer/Counter2 Compare Match */ -#define TIMER2_COMP_vect_num 3 -#define TIMER2_COMP_vect _VECTOR(3) -#define SIG_OUTPUT_COMPARE2 _VECTOR(3) - -/* Timer/Counter2 Overflow */ -#define TIMER2_OVF_vect_num 4 -#define TIMER2_OVF_vect _VECTOR(4) -#define SIG_OVERFLOW2 _VECTOR(4) - -/* Timer/Counter1 Capture Event */ -#define TIMER1_CAPT_vect_num 5 -#define TIMER1_CAPT_vect _VECTOR(5) -#define SIG_INPUT_CAPTURE1 _VECTOR(5) - -/* Timer/Counter1 Compare Match A */ -#define TIMER1_COMPA_vect_num 6 -#define TIMER1_COMPA_vect _VECTOR(6) -#define SIG_OUTPUT_COMPARE1A _VECTOR(6) - -/* Timer/Counter1 Compare Match B */ -#define TIMER1_COMPB_vect_num 7 -#define TIMER1_COMPB_vect _VECTOR(7) -#define SIG_OUTPUT_COMPARE1B _VECTOR(7) - -/* Timer/Counter1 Overflow */ -#define TIMER1_OVF_vect_num 8 -#define TIMER1_OVF_vect _VECTOR(8) -#define SIG_OVERFLOW1 _VECTOR(8) - -/* Timer/Counter0 Overflow */ -#define TIMER0_OVF_vect_num 9 -#define TIMER0_OVF_vect _VECTOR(9) -#define SIG_OVERFLOW0 _VECTOR(9) - -/* SPI Serial Transfer Complete */ -#define SPI_STC_vect_num 10 -#define SPI_STC_vect _VECTOR(10) -#define SIG_SPI _VECTOR(10) - -/* USART, RX Complete */ -#define USART_RX_vect_num 11 -#define USART_RX_vect _VECTOR(11) -#define SIG_UART_RECV _VECTOR(11) - -/* USART Data Register Empty */ -#define USART_UDRE_vect_num 12 -#define USART_UDRE_vect _VECTOR(12) -#define SIG_UART_DATA _VECTOR(12) - -/* USART, TX Complete */ -#define USART_TX_vect_num 13 -#define USART_TX_vect _VECTOR(13) -#define SIG_UART_TRANS _VECTOR(13) - -/* ADC Conversion Complete */ -#define ADC_vect_num 14 -#define ADC_vect _VECTOR(14) -#define SIG_ADC _VECTOR(14) - -/* EEPROM Ready */ -#define EE_RDY_vect_num 15 -#define EE_RDY_vect _VECTOR(15) -#define SIG_EEPROM_READY _VECTOR(15) - -/* Analog Comparator */ -#define ANA_COMP_vect_num 16 -#define ANA_COMP_vect _VECTOR(16) -#define SIG_COMPARATOR _VECTOR(16) - -/* Two-wire Serial Interface */ -#define TWI_vect_num 17 -#define TWI_vect _VECTOR(17) -#define SIG_2WIRE_SERIAL _VECTOR(17) - -/* External Interrupt Request 2 */ -#define INT2_vect_num 18 -#define INT2_vect _VECTOR(18) -#define SIG_INTERRUPT2 _VECTOR(18) - -/* TimerCounter0 Compare Match */ -#define TIMER0_COMP_vect_num 19 -#define TIMER0_COMP_vect _VECTOR(19) -#define SIG_OUTPUT_COMPARE0 _VECTOR(19) - -/* Store Program Memory Read */ -#define SPM_RDY_vect_num 20 -#define SPM_RDY_vect _VECTOR(20) -#define SIG_SPM_READY _VECTOR(20) - -#define _VECTORS_SIZE 42 - -/* - The Register Bit names are represented by their bit number (0-7). -*/ - -/* General Interrupt Control Register */ -#define INT1 7 -#define INT0 6 -#define INT2 5 -#define IVSEL 1 -#define IVCE 0 - -/* General Interrupt Flag Register */ -#define INTF1 7 -#define INTF0 6 -#define INTF2 5 - -/* Timer/Counter Interrupt MaSK register */ -#define OCIE2 7 -#define TOIE2 6 -#define TICIE1 5 -#define OCIE1A 4 -#define OCIE1B 3 -#define TOIE1 2 -#define OCIE0 1 -#define TOIE0 0 - -/* Timer/Counter Interrupt Flag register */ -#define OCF2 7 -#define TOV2 6 -#define ICF1 5 -#define OCF1A 4 -#define OCF1B 3 -#define TOV1 2 -#define OCF0 1 -#define TOV0 0 - -/* Store Program Memory Control Register */ -#define SPMIE 7 -#define RWWSB 6 -#define RWWSRE 4 -#define BLBSET 3 -#define PGWRT 2 -#define PGERS 1 -#define SPMEN 0 - -/* TWI Control Register */ -#define TWINT 7 -#define TWEA 6 -#define TWSTA 5 -#define TWSTO 4 -#define TWWC 3 -#define TWEN 2 -#define TWIE 0 - -/* MCU Control Register */ -#define SM2 7 -#define SE 6 -#define SM1 5 -#define SM0 4 -#define ISC11 3 -#define ISC10 2 -#define ISC01 1 -#define ISC00 0 - -/* MCU Control and Status Register */ -#define ISC2 6 -#define WDRF 3 -#define BORF 2 -#define EXTRF 1 -#define PORF 0 - -/* Timer/Counter 0 Control Register */ -#define FOC0 7 -#define WGM00 6 -#define COM01 5 -#define COM00 4 -#define WGM01 3 -#define CS02 2 -#define CS01 1 -#define CS00 0 - -/* - The ADHSM bit has been removed from all documentation, - as being not needed at all since the comparator has proven - to be fast enough even without feeding it more power. -*/ - -/* Special Function IO Register */ -#define ADTS2 7 -#define ADTS1 6 -#define ADTS0 5 -#define ACME 3 -#define PUD 2 -#define PSR2 1 -#define PSR10 0 - -/* Timer/Counter 1 Control Register */ -#define COM1A1 7 -#define COM1A0 6 -#define COM1B1 5 -#define COM1B0 4 -#define FOC1A 3 -#define FOC1B 2 -#define WGM11 1 -#define WGM10 0 - -/* Timer/Counter 1 Control and Status Register */ -#define ICNC1 7 -#define ICES1 6 -#define WGM13 4 -#define WGM12 3 -#define CS12 2 -#define CS11 1 -#define CS10 0 - -/* Timer/Counter 2 Control Register */ -#define FOC2 7 -#define WGM20 6 -#define COM21 5 -#define COM20 4 -#define WGM21 3 -#define CS22 2 -#define CS21 1 -#define CS20 0 - -/* Asynchronous mode Status Register */ -#define AS2 3 -#define TCN2UB 2 -#define OCR2UB 1 -#define TCR2UB 0 - -/* Watchdog Timer Control Register */ -#define WDCE 4 -#define WDE 3 -#define WDP2 2 -#define WDP1 1 -#define WDP0 0 - -/* USART Control and Status Register C */ -#define URSEL 7 -#define UMSEL 6 -#define UPM1 5 -#define UPM0 4 -#define USBS 3 -#define UCSZ1 2 -#define UCSZ0 1 -#define UCPOL 0 - -/* Data Register, Port A */ -#define PA7 7 -#define PA6 6 -#define PA5 5 -#define PA4 4 -#define PA3 3 -#define PA2 2 -#define PA1 1 -#define PA0 0 - -/* Data Direction Register, Port A */ -#define DDA7 7 -#define DDA6 6 -#define DDA5 5 -#define DDA4 4 -#define DDA3 3 -#define DDA2 2 -#define DDA1 1 -#define DDA0 0 - -/* Input Pins, Port A */ -#define PINA7 7 -#define PINA6 6 -#define PINA5 5 -#define PINA4 4 -#define PINA3 3 -#define PINA2 2 -#define PINA1 1 -#define PINA0 0 - -/* Data Register, Port B */ -#define PB7 7 -#define PB6 6 -#define PB5 5 -#define PB4 4 -#define PB3 3 -#define PB2 2 -#define PB1 1 -#define PB0 0 - -/* Data Direction Register, Port B */ -#define DDB7 7 -#define DDB6 6 -#define DDB5 5 -#define DDB4 4 -#define DDB3 3 -#define DDB2 2 -#define DDB1 1 -#define DDB0 0 - -/* Input Pins, Port B */ -#define PINB7 7 -#define PINB6 6 -#define PINB5 5 -#define PINB4 4 -#define PINB3 3 -#define PINB2 2 -#define PINB1 1 -#define PINB0 0 - -/* Data Register, Port C */ -#define PC7 7 -#define PC6 6 -#define PC5 5 -#define PC4 4 -#define PC3 3 -#define PC2 2 -#define PC1 1 -#define PC0 0 - -/* Data Direction Register, Port C */ -#define DDC7 7 -#define DDC6 6 -#define DDC5 5 -#define DDC4 4 -#define DDC3 3 -#define DDC2 2 -#define DDC1 1 -#define DDC0 0 - -/* Input Pins, Port C */ -#define PINC7 7 -#define PINC6 6 -#define PINC5 5 -#define PINC4 4 -#define PINC3 3 -#define PINC2 2 -#define PINC1 1 -#define PINC0 0 - -/* Data Register, Port D */ -#define PD7 7 -#define PD6 6 -#define PD5 5 -#define PD4 4 -#define PD3 3 -#define PD2 2 -#define PD1 1 -#define PD0 0 - -/* Data Direction Register, Port D */ -#define DDD7 7 -#define DDD6 6 -#define DDD5 5 -#define DDD4 4 -#define DDD3 3 -#define DDD2 2 -#define DDD1 1 -#define DDD0 0 - -/* Input Pins, Port D */ -#define PIND7 7 -#define PIND6 6 -#define PIND5 5 -#define PIND4 4 -#define PIND3 3 -#define PIND2 2 -#define PIND1 1 -#define PIND0 0 - -/* SPI Status Register */ -#define SPIF 7 -#define WCOL 6 -#define SPI2X 0 - -/* SPI Control Register */ -#define SPIE 7 -#define SPE 6 -#define DORD 5 -#define MSTR 4 -#define CPOL 3 -#define CPHA 2 -#define SPR1 1 -#define SPR0 0 - -/* USART Control and Status Register A */ -#define RXC 7 -#define TXC 6 -#define UDRE 5 -#define FE 4 -#define DOR 3 -#define PE 2 -#define U2X 1 -#define MPCM 0 - -/* USART Control and Status Register B */ -#define RXCIE 7 -#define TXCIE 6 -#define UDRIE 5 -#define RXEN 4 -#define TXEN 3 -#define UCSZ2 2 -#define RXB8 1 -#define TXB8 0 - -/* Analog Comparator Control and Status Register */ -#define ACD 7 -#define ACBG 6 -#define ACO 5 -#define ACI 4 -#define ACIE 3 -#define ACIC 2 -#define ACIS1 1 -#define ACIS0 0 - -/* ADC Multiplexer Selection Register */ -#define REFS1 7 -#define REFS0 6 -#define ADLAR 5 -#define MUX4 4 -#define MUX3 3 -#define MUX2 2 -#define MUX1 1 -#define MUX0 0 - -/* ADC Control and Status Register */ -#define ADEN 7 -#define ADSC 6 -#define ADATE 5 -#define ADIF 4 -#define ADIE 3 -#define ADPS2 2 -#define ADPS1 1 -#define ADPS0 0 - -/* TWI (Slave) Address Register */ -#define TWGCE 0 - -/* TWI Status Register */ -#define TWS7 7 -#define TWS6 6 -#define TWS5 5 -#define TWS4 4 -#define TWS3 3 -#define TWPS1 1 -#define TWPS0 0 - -/* EEPROM Control Register */ -#define EERIE 3 -#define EEMWE 2 -#define EEWE 1 -#define EERE 0 - -/* Constants */ -#define SPM_PAGESIZE 64 -#define RAMSTART (0x60) -#define RAMEND 0x25F /* Last On-Chip SRAM Location */ -#define XRAMEND RAMEND -#define E2END 0x1FF -#define E2PAGESIZE 4 -#define FLASHEND 0x1FFF - - -/* Fuses */ - -#define FUSE_MEMORY_SIZE 2 - -/* Low Fuse Byte */ -#define FUSE_CKSEL0 (unsigned char)~_BV(0) -#define FUSE_CKSEL1 (unsigned char)~_BV(1) -#define FUSE_CKSEL2 (unsigned char)~_BV(2) -#define FUSE_CKSEL3 (unsigned char)~_BV(3) -#define FUSE_SUT0 (unsigned char)~_BV(4) -#define FUSE_SUT1 (unsigned char)~_BV(5) -#define FUSE_BODEN (unsigned char)~_BV(6) -#define FUSE_BODLEVEL (unsigned char)~_BV(7) -#define LFUSE_DEFAULT (FUSE_CKSEL1 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_SUT1) - -/* High Fuse Byte */ -#define FUSE_BOOTRST (unsigned char)~_BV(0) -#define FUSE_BOOTSZ0 (unsigned char)~_BV(1) -#define FUSE_BOOTSZ1 (unsigned char)~_BV(2) -#define FUSE_EESAVE (unsigned char)~_BV(3) -#define FUSE_CKOPT (unsigned char)~_BV(4) -#define FUSE_SPIEN (unsigned char)~_BV(5) -#define FUSE_WDTON (unsigned char)~_BV(6) -#define FUSE_S8535C (unsigned char)~_BV(7) -#define HFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_SPIEN) - - -/* Lock Bits */ -#define __LOCK_BITS_EXIST -#define __BOOT_LOCK_BITS_0_EXIST -#define __BOOT_LOCK_BITS_1_EXIST - - -/* Signature */ -#define SIGNATURE_0 0x1E -#define SIGNATURE_1 0x93 -#define SIGNATURE_2 0x08 - - -/* Deprecated items */ -#if !defined(__AVR_LIBC_DEPRECATED_ENABLE__) - -#pragma GCC system_header - -#pragma GCC poison SIG_INTERRUPT0 -#pragma GCC poison SIG_INTERRUPT1 -#pragma GCC poison SIG_OUTPUT_COMPARE2 -#pragma GCC poison SIG_OVERFLOW2 -#pragma GCC poison SIG_INPUT_CAPTURE1 -#pragma GCC poison SIG_OUTPUT_COMPARE1A -#pragma GCC poison SIG_OUTPUT_COMPARE1B -#pragma GCC poison SIG_OVERFLOW1 -#pragma GCC poison SIG_OVERFLOW0 -#pragma GCC poison SIG_SPI -#pragma GCC poison SIG_UART_RECV -#pragma GCC poison SIG_UART_DATA -#pragma GCC poison SIG_UART_TRANS -#pragma GCC poison SIG_ADC -#pragma GCC poison SIG_EEPROM_READY -#pragma GCC poison SIG_COMPARATOR -#pragma GCC poison SIG_2WIRE_SERIAL -#pragma GCC poison SIG_INTERRUPT2 -#pragma GCC poison SIG_OUTPUT_COMPARE0 -#pragma GCC poison SIG_SPM_READY - -#endif /* !defined(__AVR_LIBC_DEPRECATED_ENABLE__) */ - - -#define SLEEP_MODE_IDLE (0x00<<4) -#define SLEEP_MODE_ADC (0x01<<4) -#define SLEEP_MODE_PWR_DOWN (0x02<<4) -#define SLEEP_MODE_PWR_SAVE (0x03<<4) -#define SLEEP_MODE_STANDBY (0x0A<<4) -#define SLEEP_MODE_EXT_STANDBY (0x0B<<4) - -#endif /* _AVR_IOM8535_H_ */ diff --git a/arduino/hardware/tools/avr/avr/include/avr/iom88.h b/arduino/hardware/tools/avr/avr/include/avr/iom88.h deleted file mode 100644 index ece11b2..0000000 --- a/arduino/hardware/tools/avr/avr/include/avr/iom88.h +++ /dev/null @@ -1,97 +0,0 @@ -/* Copyright (c) 2004, Theodore A. Roth - All rights reserved. - - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - * Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - * Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in - the documentation and/or other materials provided with the - distribution. - - * Neither the name of the copyright holders nor the names of - contributors may be used to endorse or promote products derived - from this software without specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. */ - -/* $Id: iom88.h 2115 2010-04-05 23:19:53Z arcanum $ */ - -#ifndef _AVR_IOM88_H_ -#define _AVR_IOM88_H_ 1 - -#include - -/* Constants */ -#define SPM_PAGESIZE 64 -#define RAMSTART (0x100) -#define RAMEND 0x4FF -#define XRAMEND RAMEND -#define E2END 0x1FF -#define E2PAGESIZE 4 -#define FLASHEND 0x1FFF - - -/* Fuses */ -#define FUSE_MEMORY_SIZE 3 - -/* Low Fuse Byte */ -#define FUSE_CKSEL0 (unsigned char)~_BV(0) /* Select Clock Source */ -#define FUSE_CKSEL1 (unsigned char)~_BV(1) /* Select Clock Source */ -#define FUSE_CKSEL2 (unsigned char)~_BV(2) /* Select Clock Source */ -#define FUSE_CKSEL3 (unsigned char)~_BV(3) /* Select Clock Source */ -#define FUSE_SUT0 (unsigned char)~_BV(4) /* Select start-up time */ -#define FUSE_SUT1 (unsigned char)~_BV(5) /* Select start-up time */ -#define FUSE_CKOUT (unsigned char)~_BV(6) /* Clock output */ -#define FUSE_CKDIV8 (unsigned char)~_BV(7) /* Divide clock by 8 */ -#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8) - -/* High Fuse Byte */ -#define FUSE_BODLEVEL0 (unsigned char)~_BV(0) /* Brown-out Detector trigger level */ -#define FUSE_BODLEVEL1 (unsigned char)~_BV(1) /* Brown-out Detector trigger level */ -#define FUSE_BODLEVEL2 (unsigned char)~_BV(2) /* Brown-out Detector trigger level */ -#define FUSE_EESAVE (unsigned char)~_BV(3) /* EEPROM memory is preserved through chip erase */ -#define FUSE_WDTON (unsigned char)~_BV(4) /* Watchdog Timer Always On */ -#define FUSE_SPIEN (unsigned char)~_BV(5) /* Enable Serial programming and Data Downloading */ -#define FUSE_DWEN (unsigned char)~_BV(6) /* debugWIRE Enable */ -#define FUSE_RSTDISBL (unsigned char)~_BV(7) /* External reset disable */ -#define HFUSE_DEFAULT (FUSE_SPIEN) - -/* Extended Fuse Byte */ -#define FUSE_BOOTRST (unsigned char)~_BV(0) -#define FUSE_BOOTSZ0 (unsigned char)~_BV(1) -#define FUSE_BOOTSZ1 (unsigned char)~_BV(2) -#define EFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1) - - -/* Lock Bits */ -#define __LOCK_BITS_EXIST -#define __BOOT_LOCK_BITS_0_EXIST -#define __BOOT_LOCK_BITS_1_EXIST - - -/* Signature */ -#define SIGNATURE_0 0x1E -#define SIGNATURE_1 0x93 -#define SIGNATURE_2 0x0A - -#define SLEEP_MODE_IDLE (0x00<<1) -#define SLEEP_MODE_ADC (0x01<<1) -#define SLEEP_MODE_PWR_DOWN (0x02<<1) -#define SLEEP_MODE_PWR_SAVE (0x03<<1) -#define SLEEP_MODE_STANDBY (0x06<<1) - -#endif /* _AVR_IOM88_H_ */ diff --git a/arduino/hardware/tools/avr/avr/include/avr/iom88a.h b/arduino/hardware/tools/avr/avr/include/avr/iom88a.h deleted file mode 100644 index d01dbf4..0000000 --- a/arduino/hardware/tools/avr/avr/include/avr/iom88a.h +++ /dev/null @@ -1,35 +0,0 @@ -/***************************************************************************** - * - * Copyright (C) 2011 Atmel Corporation - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * - * * Neither the name of the copyright holders nor the names of - * contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - ****************************************************************************/ - -#include "iom88.h" -#define SLEEP_MODE_EXT_STANDBY (0x07<<1) diff --git a/arduino/hardware/tools/avr/avr/include/avr/iom88p.h b/arduino/hardware/tools/avr/avr/include/avr/iom88p.h deleted file mode 100644 index 39fab86..0000000 --- a/arduino/hardware/tools/avr/avr/include/avr/iom88p.h +++ /dev/null @@ -1,941 +0,0 @@ -/* Copyright (c) 2007 Atmel Corporation - All rights reserved. - - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - * Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - * Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in - the documentation and/or other materials provided with the - distribution. - - * Neither the name of the copyright holders nor the names of - contributors may be used to endorse or promote products derived - from this software without specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. -*/ - -/* $Id: iom88p.h 2225 2011-03-02 16:27:26Z arcanum $ */ - -/* avr/iom88p.h - definitions for ATmega88P. */ - -/* This file should only be included from , never directly. */ - -#ifndef _AVR_IO_H_ -# error "Include instead of this file." -#endif - -#ifndef _AVR_IOXXX_H_ -# define _AVR_IOXXX_H_ "iom88p.h" -#else -# error "Attempt to include more than one file." -#endif - - -#ifndef _AVR_IOM88P_H_ -#define _AVR_IOM88P_H_ 1 - -/* Registers and associated bit numbers */ - -#define PINB _SFR_IO8(0x03) -#define PINB0 0 -#define PINB1 1 -#define PINB2 2 -#define PINB3 3 -#define PINB4 4 -#define PINB5 5 -#define PINB6 6 -#define PINB7 7 - -#define DDRB _SFR_IO8(0x04) -#define DDB0 0 -#define DDB1 1 -#define DDB2 2 -#define DDB3 3 -#define DDB4 4 -#define DDB5 5 -#define DDB6 6 -#define DDB7 7 - -#define PORTB _SFR_IO8(0x05) -#define PORTB0 0 -#define PORTB1 1 -#define PORTB2 2 -#define PORTB3 3 -#define PORTB4 4 -#define PORTB5 5 -#define PORTB6 6 -#define PORTB7 7 - -#define PINC _SFR_IO8(0x06) -#define PINC0 0 -#define PINC1 1 -#define PINC2 2 -#define PINC3 3 -#define PINC4 4 -#define PINC5 5 -#define PINC6 6 - -#define DDRC _SFR_IO8(0x07) -#define DDC0 0 -#define DDC1 1 -#define DDC2 2 -#define DDC3 3 -#define DDC4 4 -#define DDC5 5 -#define DDC6 6 - -#define PORTC _SFR_IO8(0x08) -#define PORTC0 0 -#define PORTC1 1 -#define PORTC2 2 -#define PORTC3 3 -#define PORTC4 4 -#define PORTC5 5 -#define PORTC6 6 - -#define PIND _SFR_IO8(0x09) -#define PIND0 0 -#define PIND1 1 -#define PIND2 2 -#define PIND3 3 -#define PIND4 4 -#define PIND5 5 -#define PIND6 6 -#define PIND7 7 - -#define DDRD _SFR_IO8(0x0A) -#define DDD0 0 -#define DDD1 1 -#define DDD2 2 -#define DDD3 3 -#define DDD4 4 -#define DDD5 5 -#define DDD6 6 -#define DDD7 7 - -#define PORTD _SFR_IO8(0x0B) -#define PORTD0 0 -#define PORTD1 1 -#define PORTD2 2 -#define PORTD3 3 -#define PORTD4 4 -#define PORTD5 5 -#define PORTD6 6 -#define PORTD7 7 - -#define TIFR0 _SFR_IO8(0x15) -#define TOV0 0 -#define OCF0A 1 -#define OCF0B 2 - -#define TIFR1 _SFR_IO8(0x16) -#define TOV1 0 -#define OCF1A 1 -#define OCF1B 2 -#define ICF1 5 - -#define TIFR2 _SFR_IO8(0x17) -#define TOV2 0 -#define OCF2A 1 -#define OCF2B 2 - -#define PCIFR _SFR_IO8(0x1B) -#define PCIF0 0 -#define PCIF1 1 -#define PCIF2 2 - -#define EIFR _SFR_IO8(0x1C) -#define INTF0 0 -#define INTF1 1 - -#define EIMSK _SFR_IO8(0x1D) -#define INT0 0 -#define INT1 1 - -#define GPIOR0 _SFR_IO8(0x1E) -#define GPIOR00 0 -#define GPIOR01 1 -#define GPIOR02 2 -#define GPIOR03 3 -#define GPIOR04 4 -#define GPIOR05 5 -#define GPIOR06 6 -#define GPIOR07 7 - -#define EECR _SFR_IO8(0x1F) -#define EERE 0 -#define EEPE 1 -#define EEMPE 2 -#define EERIE 3 -#define EEPM0 4 -#define EEPM1 5 - -#define EEDR _SFR_IO8(0x20) -#define EEDR0 0 -#define EEDR1 1 -#define EEDR2 2 -#define EEDR3 3 -#define EEDR4 4 -#define EEDR5 5 -#define EEDR6 6 -#define EEDR7 7 - -#define EEAR _SFR_IO16(0x21) - -#define EEARL _SFR_IO8(0x21) -#define EEAR0 0 -#define EEAR1 1 -#define EEAR2 2 -#define EEAR3 3 -#define EEAR4 4 -#define EEAR5 5 -#define EEAR6 6 -#define EEAR7 7 - -#define EEARH _SFR_IO8(0x22) -#define EEAR8 0 - -#define EEPROM_REG_LOCATIONS 1F2021 - -#define GTCCR _SFR_IO8(0x23) -#define PSRSYNC 0 -#define PSRASY 1 -#define TSM 7 - -#define TCCR0A _SFR_IO8(0x24) -#define WGM00 0 -#define WGM01 1 -#define COM0B0 4 -#define COM0B1 5 -#define COM0A0 6 -#define COM0A1 7 - -#define TCCR0B _SFR_IO8(0x25) -#define CS00 0 -#define CS01 1 -#define CS02 2 -#define WGM02 3 -#define FOC0B 6 -#define FOC0A 7 - -#define TCNT0 _SFR_IO8(0x26) -#define TCNT0_0 0 -#define TCNT0_1 1 -#define TCNT0_2 2 -#define TCNT0_3 3 -#define TCNT0_4 4 -#define TCNT0_5 5 -#define TCNT0_6 6 -#define TCNT0_7 7 - -#define OCR0A _SFR_IO8(0x27) -#define OCR0A_0 0 -#define OCR0A_1 1 -#define OCR0A_2 2 -#define OCR0A_3 3 -#define OCR0A_4 4 -#define OCR0A_5 5 -#define OCR0A_6 6 -#define OCR0A_7 7 - -#define OCR0B _SFR_IO8(0x28) -#define OCR0B_0 0 -#define OCR0B_1 1 -#define OCR0B_2 2 -#define OCR0B_3 3 -#define OCR0B_4 4 -#define OCR0B_5 5 -#define OCR0B_6 6 -#define OCR0B_7 7 - -#define GPIOR1 _SFR_IO8(0x2A) -#define GPIOR10 0 -#define GPIOR11 1 -#define GPIOR12 2 -#define GPIOR13 3 -#define GPIOR14 4 -#define GPIOR15 5 -#define GPIOR16 6 -#define GPIOR17 7 - -#define GPIOR2 _SFR_IO8(0x2B) -#define GPIOR20 0 -#define GPIOR21 1 -#define GPIOR22 2 -#define GPIOR23 3 -#define GPIOR24 4 -#define GPIOR25 5 -#define GPIOR26 6 -#define GPIOR27 7 - -#define SPCR _SFR_IO8(0x2C) -#define SPR0 0 -#define SPR1 1 -#define CPHA 2 -#define CPOL 3 -#define MSTR 4 -#define DORD 5 -#define SPE 6 -#define SPIE 7 - -#define SPSR _SFR_IO8(0x2D) -#define SPI2X 0 -#define WCOL 6 -#define SPIF 7 - -#define SPDR _SFR_IO8(0x2E) -#define SPDR0 0 -#define SPDR1 1 -#define SPDR2 2 -#define SPDR3 3 -#define SPDR4 4 -#define SPDR5 5 -#define SPDR6 6 -#define SPDR7 7 - -#define ACSR _SFR_IO8(0x30) -#define ACIS0 0 -#define ACIS1 1 -#define ACIC 2 -#define ACIE 3 -#define ACI 4 -#define ACO 5 -#define ACBG 6 -#define ACD 7 - -#define SMCR _SFR_IO8(0x33) -#define SE 0 -#define SM0 1 -#define SM1 2 -#define SM2 3 - -#define MCUSR _SFR_IO8(0x34) -#define PORF 0 -#define EXTRF 1 -#define BORF 2 -#define WDRF 3 - -#define MCUCR _SFR_IO8(0x35) -#define IVCE 0 -#define IVSEL 1 -#define PUD 4 -#define BODSE 5 -#define BODS 6 - -#define SPMCSR _SFR_IO8(0x37) -#define SELFPRGEN 0 -#define SPMEN 0 -#define PGERS 1 -#define PGWRT 2 -#define BLBSET 3 -#define RWWSRE 4 -#define SIGRD 5 -#define RWWSB 6 -#define SPMIE 7 - -#define WDTCSR _SFR_MEM8(0x60) -#define WDP0 0 -#define WDP1 1 -#define WDP2 2 -#define WDE 3 -#define WDCE 4 -#define WDP3 5 -#define WDIE 6 -#define WDIF 7 - -#define CLKPR _SFR_MEM8(0x61) -#define CLKPS0 0 -#define CLKPS1 1 -#define CLKPS2 2 -#define CLKPS3 3 -#define CLKPCE 7 - -#define PRR _SFR_MEM8(0x64) -#define PRADC 0 -#define PRUSART0 1 -#define PRSPI 2 -#define PRTIM1 3 -#define PRTIM0 5 -#define PRTIM2 6 -#define PRTWI 7 - -#define __AVR_HAVE_PRR ((1<, never directly. */ - -#ifndef _AVR_IO_H_ -# error "Include instead of this file." -#endif - -#ifndef _AVR_IOXXX_H_ -# define _AVR_IOXXX_H_ "iom88pa.h" -#else -# error "Attempt to include more than one file." -#endif - - -#ifndef _AVR_ATmega88PA_H_ -#define _AVR_ATmega88PA_H_ 1 - - -/* Registers and associated bit numbers. */ - -#define PINB _SFR_IO8(0x03) -#define PINB0 0 -#define PINB1 1 -#define PINB2 2 -#define PINB3 3 -#define PINB4 4 -#define PINB5 5 -#define PINB6 6 -#define PINB7 7 - -#define DDRB _SFR_IO8(0x04) -#define DDB0 0 -#define DDB1 1 -#define DDB2 2 -#define DDB3 3 -#define DDB4 4 -#define DDB5 5 -#define DDB6 6 -#define DDB7 7 - -#define PORTB _SFR_IO8(0x05) -#define PORTB0 0 -#define PORTB1 1 -#define PORTB2 2 -#define PORTB3 3 -#define PORTB4 4 -#define PORTB5 5 -#define PORTB6 6 -#define PORTB7 7 - -#define PINC _SFR_IO8(0x06) -#define PINC0 0 -#define PINC1 1 -#define PINC2 2 -#define PINC3 3 -#define PINC4 4 -#define PINC5 5 -#define PINC6 6 - -#define DDRC _SFR_IO8(0x07) -#define DDC0 0 -#define DDC1 1 -#define DDC2 2 -#define DDC3 3 -#define DDC4 4 -#define DDC5 5 -#define DDC6 6 - -#define PORTC _SFR_IO8(0x08) -#define PORTC0 0 -#define PORTC1 1 -#define PORTC2 2 -#define PORTC3 3 -#define PORTC4 4 -#define PORTC5 5 -#define PORTC6 6 - -#define PIND _SFR_IO8(0x09) -#define PIND0 0 -#define PIND1 1 -#define PIND2 2 -#define PIND3 3 -#define PIND4 4 -#define PIND5 5 -#define PIND6 6 -#define PIND7 7 - -#define DDRD _SFR_IO8(0x0A) -#define DDD0 0 -#define DDD1 1 -#define DDD2 2 -#define DDD3 3 -#define DDD4 4 -#define DDD5 5 -#define DDD6 6 -#define DDD7 7 - -#define PORTD _SFR_IO8(0x0B) -#define PORTD0 0 -#define PORTD1 1 -#define PORTD2 2 -#define PORTD3 3 -#define PORTD4 4 -#define PORTD5 5 -#define PORTD6 6 -#define PORTD7 7 - -#define TIFR0 _SFR_IO8(0x15) -#define TOV0 0 -#define OCF0A 1 -#define OCF0B 2 - -#define TIFR1 _SFR_IO8(0x16) -#define TOV1 0 -#define OCF1A 1 -#define OCF1B 2 -#define ICF1 5 - -#define TIFR2 _SFR_IO8(0x17) -#define TOV2 0 -#define OCF2A 1 -#define OCF2B 2 - -#define PCIFR _SFR_IO8(0x1B) -#define PCIF0 0 -#define PCIF1 1 -#define PCIF2 2 - -#define EIFR _SFR_IO8(0x1C) -#define INTF0 0 -#define INTF1 1 - -#define EIMSK _SFR_IO8(0x1D) -#define INT0 0 -#define INT1 1 - -#define GPIOR0 _SFR_IO8(0x1E) -#define GPIOR00 0 -#define GPIOR01 1 -#define GPIOR02 2 -#define GPIOR03 3 -#define GPIOR04 4 -#define GPIOR05 5 -#define GPIOR06 6 -#define GPIOR07 7 - -#define EECR _SFR_IO8(0x1F) -#define EERE 0 -#define EEPE 1 -#define EEMPE 2 -#define EERIE 3 -#define EEPM0 4 -#define EEPM1 5 - -#define EEDR _SFR_IO8(0x20) -#define EEDR0 0 -#define EEDR1 1 -#define EEDR2 2 -#define EEDR3 3 -#define EEDR4 4 -#define EEDR5 5 -#define EEDR6 6 -#define EEDR7 7 - -#define EEAR _SFR_IO16(0x21) - -#define EEARL _SFR_IO8(0x21) -#define EEAR0 0 -#define EEAR1 1 -#define EEAR2 2 -#define EEAR3 3 -#define EEAR4 4 -#define EEAR5 5 -#define EEAR6 6 -#define EEAR7 7 - -#define EEARH _SFR_IO8(0x22) -#define EEAR8 0 - -#define GTCCR _SFR_IO8(0x23) -#define PSRSYNC 0 -#define PSRASY 1 -#define TSM 7 - -#define TCCR0A _SFR_IO8(0x24) -#define WGM00 0 -#define WGM01 1 -#define COM0B0 4 -#define COM0B1 5 -#define COM0A0 6 -#define COM0A1 7 - -#define TCCR0B _SFR_IO8(0x25) -#define CS00 0 -#define CS01 1 -#define CS02 2 -#define WGM02 3 -#define FOC0B 6 -#define FOC0A 7 - -#define TCNT0 _SFR_IO8(0x26) -#define TCNT0_0 0 -#define TCNT0_1 1 -#define TCNT0_2 2 -#define TCNT0_3 3 -#define TCNT0_4 4 -#define TCNT0_5 5 -#define TCNT0_6 6 -#define TCNT0_7 7 - -#define OCR0A _SFR_IO8(0x27) -#define OCR0A_0 0 -#define OCR0A_1 1 -#define OCR0A_2 2 -#define OCR0A_3 3 -#define OCR0A_4 4 -#define OCR0A_5 5 -#define OCR0A_6 6 -#define OCR0A_7 7 - -#define OCR0B _SFR_IO8(0x28) -#define OCR0B_0 0 -#define OCR0B_1 1 -#define OCR0B_2 2 -#define OCR0B_3 3 -#define OCR0B_4 4 -#define OCR0B_5 5 -#define OCR0B_6 6 -#define OCR0B_7 7 - -#define GPIOR1 _SFR_IO8(0x2A) -#define GPIOR10 0 -#define GPIOR11 1 -#define GPIOR12 2 -#define GPIOR13 3 -#define GPIOR14 4 -#define GPIOR15 5 -#define GPIOR16 6 -#define GPIOR17 7 - -#define GPIOR2 _SFR_IO8(0x2B) -#define GPIOR20 0 -#define GPIOR21 1 -#define GPIOR22 2 -#define GPIOR23 3 -#define GPIOR24 4 -#define GPIOR25 5 -#define GPIOR26 6 -#define GPIOR27 7 - -#define SPCR _SFR_IO8(0x2C) -#define SPR0 0 -#define SPR1 1 -#define CPHA 2 -#define CPOL 3 -#define MSTR 4 -#define DORD 5 -#define SPE 6 -#define SPIE 7 - -#define SPSR _SFR_IO8(0x2D) -#define SPI2X 0 -#define WCOL 6 -#define SPIF 7 - -#define SPDR _SFR_IO8(0x2E) -#define SPDR0 0 -#define SPDR1 1 -#define SPDR2 2 -#define SPDR3 3 -#define SPDR4 4 -#define SPDR5 5 -#define SPDR6 6 -#define SPDR7 7 - -#define ACSR _SFR_IO8(0x30) -#define ACIS0 0 -#define ACIS1 1 -#define ACIC 2 -#define ACIE 3 -#define ACI 4 -#define ACO 5 -#define ACBG 6 -#define ACD 7 - -#define SMCR _SFR_IO8(0x33) -#define SE 0 -#define SM0 1 -#define SM1 2 -#define SM2 3 - -#define MCUSR _SFR_IO8(0x34) -#define PORF 0 -#define EXTRF 1 -#define BORF 2 -#define WDRF 3 - -#define MCUCR _SFR_IO8(0x35) -#define IVCE 0 -#define IVSEL 1 -#define PUD 4 -#define BODSE 5 -#define BODS 6 - -#define SPMCSR _SFR_IO8(0x37) -#define SELFPRGEN 0 -#define SPMEN 0 -#define PGERS 1 -#define PGWRT 2 -#define BLBSET 3 -#define RWWSRE 4 -#define SIGRD 5 -#define RWWSB 6 -#define SPMIE 7 - -#define WDTCSR _SFR_MEM8(0x60) -#define WDP0 0 -#define WDP1 1 -#define WDP2 2 -#define WDE 3 -#define WDCE 4 -#define WDP3 5 -#define WDIE 6 -#define WDIF 7 - -#define CLKPR _SFR_MEM8(0x61) -#define CLKPS0 0 -#define CLKPS1 1 -#define CLKPS2 2 -#define CLKPS3 3 -#define CLKPCE 7 - -#define PRR _SFR_MEM8(0x64) -#define PRADC 0 -#define PRUSART0 1 -#define PRSPI 2 -#define PRTIM1 3 -#define PRTIM0 5 -#define PRTIM2 6 -#define PRTWI 7 - -#define __AVR_HAVE_PRR ((1< instead of this file." -#endif - -#ifndef _AVR_IOXXX_H_ -# define _AVR_IOXXX_H_ "iom88pb.h" -#else -# error "Attempt to include more than one file." -#endif - -/* Registers and associated bit numbers */ - -#define PINB _SFR_IO8(0x03) -#define PINB7 7 -#define PINB6 6 -#define PINB5 5 -#define PINB4 4 -#define PINB3 3 -#define PINB2 2 -#define PINB1 1 -#define PINB0 0 - -#define DDRB _SFR_IO8(0x04) -#define DDRB7 7 -// Inserted "DDB7" from "DDRB7" due to compatibility -#define DDB7 7 -#define DDRB6 6 -// Inserted "DDB6" from "DDRB6" due to compatibility -#define DDB6 6 -#define DDRB5 5 -// Inserted "DDB5" from "DDRB5" due to compatibility -#define DDB5 5 -#define DDRB4 4 -// Inserted "DDB4" from "DDRB4" due to compatibility -#define DDB4 4 -#define DDRB3 3 -// Inserted "DDB3" from "DDRB3" due to compatibility -#define DDB3 3 -#define DDRB2 2 -// Inserted "DDB2" from "DDRB2" due to compatibility -#define DDB2 2 -#define DDRB1 1 -// Inserted "DDB1" from "DDRB1" due to compatibility -#define DDB1 1 -#define DDRB0 0 -// Inserted "DDB0" from "DDRB0" due to compatibility -#define DDB0 0 - -#define PORTB _SFR_IO8(0x05) -#define PORTB7 7 -#define PORTB6 6 -#define PORTB5 5 -#define PORTB4 4 -#define PORTB3 3 -#define PORTB2 2 -#define PORTB1 1 -#define PORTB0 0 - -#define PINC _SFR_IO8(0x06) -#define PINC6 6 -#define PINC5 5 -#define PINC4 4 -#define PINC3 3 -#define PINC2 2 -#define PINC1 1 -#define PINC0 0 - -#define DDRC _SFR_IO8(0x07) -#define DDRC6 6 -// Inserted "DDC6" from "DDRC6" due to compatibility -#define DDC6 6 -#define DDRC5 5 -// Inserted "DDC5" from "DDRC5" due to compatibility -#define DDC5 5 -#define DDRC4 4 -// Inserted "DDC4" from "DDRC4" due to compatibility -#define DDC4 4 -#define DDRC3 3 -// Inserted "DDC3" from "DDRC3" due to compatibility -#define DDC3 3 -#define DDRC2 2 -// Inserted "DDC2" from "DDRC2" due to compatibility -#define DDC2 2 -#define DDRC1 1 -// Inserted "DDC1" from "DDRC1" due to compatibility -#define DDC1 1 -#define DDRC0 0 -// Inserted "DDC0" from "DDRC0" due to compatibility -#define DDC0 0 - -#define PORTC _SFR_IO8(0x08) -#define PORTC6 6 -#define PORTC5 5 -#define PORTC4 4 -#define PORTC3 3 -#define PORTC2 2 -#define PORTC1 1 -#define PORTC0 0 - -#define PIND _SFR_IO8(0x09) -#define PIND7 7 -#define PIND6 6 -#define PIND5 5 -#define PIND4 4 -#define PIND3 3 -#define PIND2 2 -#define PIND1 1 -#define PIND0 0 - -#define DDRD _SFR_IO8(0x0A) -#define DDRD7 7 -// Inserted "DDD7" from "DDRD7" due to compatibility -#define DDD7 7 -#define DDRD6 6 -// Inserted "DDD6" from "DDRD6" due to compatibility -#define DDD6 6 -#define DDRD5 5 -// Inserted "DDD5" from "DDRD5" due to compatibility -#define DDD5 5 -#define DDRD4 4 -// Inserted "DDD4" from "DDRD4" due to compatibility -#define DDD4 4 -#define DDRD3 3 -// Inserted "DDD3" from "DDRD3" due to compatibility -#define DDD3 3 -#define DDRD2 2 -// Inserted "DDD2" from "DDRD2" due to compatibility -#define DDD2 2 -#define DDRD1 1 -// Inserted "DDD1" from "DDRD1" due to compatibility -#define DDD1 1 -#define DDRD0 0 -// Inserted "DDD0" from "DDRD0" due to compatibility -#define DDD0 0 - -#define PORTD _SFR_IO8(0x0B) -#define PORTD7 7 -#define PORTD6 6 -#define PORTD5 5 -#define PORTD4 4 -#define PORTD3 3 -#define PORTD2 2 -#define PORTD1 1 -#define PORTD0 0 - -#define PINE _SFR_IO8(0x0C) -#define PINE3 3 -#define PINE2 2 -#define PINE1 1 -#define PINE0 0 - -#define DDRE _SFR_IO8(0x0D) -#define DDRE3 3 -// Inserted "DDE3" from "DDRE3" due to compatibility -#define DDE3 3 -#define DDRE2 2 -// Inserted "DDE2" from "DDRE2" due to compatibility -#define DDE2 2 -#define DDRE1 1 -// Inserted "DDE1" from "DDRE1" due to compatibility -#define DDE1 1 -#define DDRE0 0 -// Inserted "DDE0" from "DDRE0" due to compatibility -#define DDE0 0 - -#define PORTE _SFR_IO8(0x0E) -#define PORTE3 3 -#define PORTE2 2 -#define PORTE1 1 -#define PORTE0 0 - -#define ACSRB _SFR_IO8(0x0F) -#define ACOE 0 - -/* Reserved [0x10..0x14] */ - -#define TIFR0 _SFR_IO8(0x15) -#define TOV0 0 -#define OCF0A 1 -#define OCF0B 2 - -#define TIFR1 _SFR_IO8(0x16) -#define TOV1 0 -#define OCF1A 1 -#define OCF1B 2 -#define ICF1 5 - -#define TIFR2 _SFR_IO8(0x17) -#define TOV2 0 -#define OCF2A 1 -#define OCF2B 2 - -/* Reserved [0x18..0x1A] */ - -#define PCIFR _SFR_IO8(0x1B) -#define PCIF0 0 -#define PCIF1 1 -#define PCIF2 2 - -#define EIFR _SFR_IO8(0x1C) -#define INTF0 0 -#define INTF1 1 - -#define EIMSK _SFR_IO8(0x1D) -#define INT0 0 -#define INT1 1 - -#define GPIOR0 _SFR_IO8(0x1E) - -#define EECR _SFR_IO8(0x1F) -#define EERE 0 -#define EEPE 1 -#define EEMPE 2 -#define EERIE 3 -#define EEPM0 4 -#define EEPM1 5 - -#define EEDR _SFR_IO8(0x20) - -/* Combine EEARL and EEARH */ -#define EEAR _SFR_IO16(0x21) - -#define EEARL _SFR_IO8(0x21) -#define EEARH _SFR_IO8(0x22) - -#define GTCCR _SFR_IO8(0x23) -#define PSRSYNC 0 -#define TSM 7 -#define PSRASY 1 - -#define TCCR0A _SFR_IO8(0x24) -#define WGM00 0 -#define WGM01 1 -#define COM0B0 4 -#define COM0B1 5 -#define COM0A0 6 -#define COM0A1 7 - -#define TCCR0B _SFR_IO8(0x25) -#define CS00 0 -#define CS01 1 -#define CS02 2 -#define WGM02 3 -#define FOC0B 6 -#define FOC0A 7 - -#define TCNT0 _SFR_IO8(0x26) - -#define OCR0A _SFR_IO8(0x27) - -#define OCR0B _SFR_IO8(0x28) - -/* Reserved [0x29] */ - -#define GPIOR1 _SFR_IO8(0x2A) - -#define GPIOR2 _SFR_IO8(0x2B) - -#define SPCR _SFR_IO8(0x2C) -#define SPR0 0 -#define SPR1 1 -#define CPHA 2 -#define CPOL 3 -#define MSTR 4 -#define DORD 5 -#define SPE 6 -#define SPIE 7 - -#define SPSR _SFR_IO8(0x2D) -#define SPI2X 0 -#define WCOL 6 -#define SPIF 7 - -#define SPDR _SFR_IO8(0x2E) - -/* Reserved [0x2F] */ - -#define ACSR _SFR_IO8(0x30) -#define ACIS0 0 -#define ACIS1 1 -#define ACIC 2 -#define ACIE 3 -#define ACI 4 -#define ACO 5 -#define ACBG 6 -#define ACD 7 - -/* Reserved [0x31..0x32] */ - -#define SMCR _SFR_IO8(0x33) -#define SE 0 -#define SM0 1 -#define SM1 2 -#define SM2 3 - -#define MCUSR _SFR_IO8(0x34) -#define PORF 0 -#define EXTRF 1 -#define BORF 2 -#define WDRF 3 - -#define MCUCR _SFR_IO8(0x35) -#define IVCE 0 -#define IVSEL 1 -#define PUD 4 -#define BODSE 5 -#define BODS 6 - -/* Reserved [0x36] */ - -#define SPMCSR _SFR_IO8(0x37) -#define SPMEN 0 -#define PGERS 1 -#define PGWRT 2 -#define BLBSET 3 -#define RWWSRE 4 -#define SIGRD 5 -#define RWWSB 6 -#define SPMIE 7 - -/* Reserved [0x38..0x3C] */ - -/* SP [0x3D..0x3E] */ - -/* SREG [0x3F] */ - -#define WDTCSR _SFR_MEM8(0x60) -#define WDE 3 -#define WDCE 4 -#define WDP0 0 -#define WDP1 1 -#define WDP2 2 -#define WDP3 5 -#define WDIE 6 -#define WDIF 7 - -#define CLKPR _SFR_MEM8(0x61) -#define CLKPS0 0 -#define CLKPS1 1 -#define CLKPS2 2 -#define CLKPS3 3 -#define CLKPCE 7 - -/* Reserved [0x62..0x63] */ - -#define PRR _SFR_MEM8(0x64) -#define PRADC 0 -#define PRUSART0 1 -#define PRSPI 2 -#define PRTIM1 3 -#define PRTIM0 5 -#define PRTIM2 6 -#define PRTWI 7 - -#define __AVR_HAVE_PRR ((1< instead of this file." -#endif - -#ifndef _AVR_IOXXX_H_ -# define _AVR_IOXXX_H_ "iom8a.h" -#else -# error "Attempt to include more than one file." -#endif - -/* Registers and associated bit numbers */ - -#define TWBR _SFR_IO8(0x00) - -#define TWSR _SFR_IO8(0x01) -#define TWPS0 0 -#define TWPS1 1 -#define TWS3 3 -#define TWS4 4 -#define TWS5 5 -#define TWS6 6 -#define TWS7 7 - -#define TWAR _SFR_IO8(0x02) -#define TWGCE 0 -#define TWA0 1 -#define TWA1 2 -#define TWA2 3 -#define TWA3 4 -#define TWA4 5 -#define TWA5 6 -#define TWA6 7 - -#define TWDR _SFR_IO8(0x03) - -/* Combine ADCL and ADCH */ -#ifndef __ASSEMBLER__ -#define ADC _SFR_IO16(0x04) -#endif -#define ADCW _SFR_IO16(0x04) - -#define ADCL _SFR_IO8(0x04) -#define ADCH _SFR_IO8(0x05) - -#define ADCSRA _SFR_IO8(0x06) -#define ADPS0 0 -#define ADPS1 1 -#define ADPS2 2 -#define ADIE 3 -#define ADIF 4 -#define ADFR 5 -#define ADSC 6 -#define ADEN 7 - -#define ADMUX _SFR_IO8(0x07) -#define MUX0 0 -#define MUX1 1 -#define MUX2 2 -#define MUX3 3 -#define ADLAR 5 -#define REFS0 6 -#define REFS1 7 - -#define ACSR _SFR_IO8(0x08) -#define ACIS0 0 -#define ACIS1 1 -#define ACIC 2 -#define ACIE 3 -#define ACI 4 -#define ACO 5 -#define ACBG 6 -#define ACD 7 - -#define UBRRL _SFR_IO8(0x09) - -#define UCSRB _SFR_IO8(0x0A) -#define TXB8 0 -#define RXB8 1 -#define UCSZ2 2 -#define TXEN 3 -#define RXEN 4 -#define UDRIE 5 -#define TXCIE 6 -#define RXCIE 7 - -#define UCSRA _SFR_IO8(0x0B) -#define MPCM 0 -#define U2X 1 -#define UPE 2 -#define DOR 3 -#define FE 4 -#define UDRE 5 -#define TXC 6 -#define RXC 7 - -#define UDR _SFR_IO8(0x0C) - -#define SPCR _SFR_IO8(0x0D) -#define SPR0 0 -#define SPR1 1 -#define CPHA 2 -#define CPOL 3 -#define MSTR 4 -#define DORD 5 -#define SPE 6 -#define SPIE 7 - -#define SPSR _SFR_IO8(0x0E) -#define SPI2X 0 -#define WCOL 6 -#define SPIF 7 - -#define SPDR _SFR_IO8(0x0F) - -#define PIND _SFR_IO8(0x10) -#define PIND7 7 -#define PIND6 6 -#define PIND5 5 -#define PIND4 4 -#define PIND3 3 -#define PIND2 2 -#define PIND1 1 -#define PIND0 0 - -#define DDRD _SFR_IO8(0x11) -#define DDRD7 7 -// Inserted "DDD7" from "DDRD7" due to compatibility -#define DDD7 7 -#define DDRD6 6 -// Inserted "DDD6" from "DDRD6" due to compatibility -#define DDD6 6 -#define DDRD5 5 -// Inserted "DDD5" from "DDRD5" due to compatibility -#define DDD5 5 -#define DDRD4 4 -// Inserted "DDD4" from "DDRD4" due to compatibility -#define DDD4 4 -#define DDRD3 3 -// Inserted "DDD3" from "DDRD3" due to compatibility -#define DDD3 3 -#define DDRD2 2 -// Inserted "DDD2" from "DDRD2" due to compatibility -#define DDD2 2 -#define DDRD1 1 -// Inserted "DDD1" from "DDRD1" due to compatibility -#define DDD1 1 -#define DDRD0 0 -// Inserted "DDD0" from "DDRD0" due to compatibility -#define DDD0 0 - -#define PORTD _SFR_IO8(0x12) -#define PORTD7 7 -#define PORTD6 6 -#define PORTD5 5 -#define PORTD4 4 -#define PORTD3 3 -#define PORTD2 2 -#define PORTD1 1 -#define PORTD0 0 - -#define PINC _SFR_IO8(0x13) -#define PINC6 6 -#define PINC5 5 -#define PINC4 4 -#define PINC3 3 -#define PINC2 2 -#define PINC1 1 -#define PINC0 0 - -#define DDRC _SFR_IO8(0x14) -#define DDRC6 6 -// Inserted "DDC6" from "DDRC6" due to compatibility -#define DDC6 6 -#define DDRC5 5 -// Inserted "DDC5" from "DDRC5" due to compatibility -#define DDC5 5 -#define DDRC4 4 -// Inserted "DDC4" from "DDRC4" due to compatibility -#define DDC4 4 -#define DDRC3 3 -// Inserted "DDC3" from "DDRC3" due to compatibility -#define DDC3 3 -#define DDRC2 2 -// Inserted "DDC2" from "DDRC2" due to compatibility -#define DDC2 2 -#define DDRC1 1 -// Inserted "DDC1" from "DDRC1" due to compatibility -#define DDC1 1 -#define DDRC0 0 -// Inserted "DDC0" from "DDRC0" due to compatibility -#define DDC0 0 - -#define PORTC _SFR_IO8(0x15) -#define PORTC6 6 -#define PORTC5 5 -#define PORTC4 4 -#define PORTC3 3 -#define PORTC2 2 -#define PORTC1 1 -#define PORTC0 0 - -#define PINB _SFR_IO8(0x16) -#define PINB7 7 -#define PINB6 6 -#define PINB5 5 -#define PINB4 4 -#define PINB3 3 -#define PINB2 2 -#define PINB1 1 -#define PINB0 0 - -#define DDRB _SFR_IO8(0x17) -#define DDRB7 7 -// Inserted "DDB7" from "DDRB7" due to compatibility -#define DDB7 7 -#define DDRB6 6 -// Inserted "DDB6" from "DDRB6" due to compatibility -#define DDB6 6 -#define DDRB5 5 -// Inserted "DDB5" from "DDRB5" due to compatibility -#define DDB5 5 -#define DDRB4 4 -// Inserted "DDB4" from "DDRB4" due to compatibility -#define DDB4 4 -#define DDRB3 3 -// Inserted "DDB3" from "DDRB3" due to compatibility -#define DDB3 3 -#define DDRB2 2 -// Inserted "DDB2" from "DDRB2" due to compatibility -#define DDB2 2 -#define DDRB1 1 -// Inserted "DDB1" from "DDRB1" due to compatibility -#define DDB1 1 -#define DDRB0 0 -// Inserted "DDB0" from "DDRB0" due to compatibility -#define DDB0 0 - -#define PORTB _SFR_IO8(0x18) -#define PORTB7 7 -#define PORTB6 6 -#define PORTB5 5 -#define PORTB4 4 -#define PORTB3 3 -#define PORTB2 2 -#define PORTB1 1 -#define PORTB0 0 - -/* Reserved [0x19..0x1B] */ - -#define EECR _SFR_IO8(0x1C) -#define EERE 0 -#define EEWE 1 -#define EEMWE 2 -#define EERIE 3 - -#define EEDR _SFR_IO8(0x1D) - -/* Combine EEARL and EEARH */ -#define EEAR _SFR_IO16(0x1E) - -#define EEARL _SFR_IO8(0x1E) -#define EEARH _SFR_IO8(0x1F) - -#define UCSRC _SFR_IO8(0x20) -#define UCPOL 0 -#define UCSZ0 1 -#define UCSZ1 2 -#define USBS 3 -#define UPM0 4 -#define UPM1 5 -#define UMSEL 6 -#define URSEL 7 - -#define UBRRH _SFR_IO8(0x20) - -#define WDTCR _SFR_IO8(0x21) -#define WDP0 0 -#define WDP1 1 -#define WDP2 2 -#define WDE 3 -#define WDCE 4 - -#define ASSR _SFR_IO8(0x22) -#define TCR2UB 0 -#define OCR2UB 1 -#define TCN2UB 2 -#define AS2 3 - -#define OCR2 _SFR_IO8(0x23) - -#define TCNT2 _SFR_IO8(0x24) - -#define TCCR2 _SFR_IO8(0x25) -#define CS20 0 -#define CS21 1 -#define CS22 2 -#define WGM21 3 -#define COM20 4 -#define COM21 5 -#define WGM20 6 -#define FOC2 7 - -/* Combine ICR1L and ICR1H */ -#define ICR1 _SFR_IO16(0x26) - -#define ICR1L _SFR_IO8(0x26) -#define ICR1H _SFR_IO8(0x27) - -/* Combine OCR1BL and OCR1BH */ -#define OCR1B _SFR_IO16(0x28) - -#define OCR1BL _SFR_IO8(0x28) -#define OCR1BH _SFR_IO8(0x29) - -/* Combine OCR1AL and OCR1AH */ -#define OCR1A _SFR_IO16(0x2A) - -#define OCR1AL _SFR_IO8(0x2A) -#define OCR1AH _SFR_IO8(0x2B) - -/* Combine TCNT1L and TCNT1H */ -#define TCNT1 _SFR_IO16(0x2C) - -#define TCNT1L _SFR_IO8(0x2C) -#define TCNT1H _SFR_IO8(0x2D) - -#define TCCR1B _SFR_IO8(0x2E) -#define CS10 0 -#define CS11 1 -#define CS12 2 -#define WGM12 3 -#define WGM13 4 -#define ICES1 6 -#define ICNC1 7 - -#define TCCR1A _SFR_IO8(0x2F) -#define WGM10 0 -#define WGM11 1 -#define FOC1B 2 -#define FOC1A 3 -#define COM1B0 4 -#define COM1B1 5 -#define COM1A0 6 -#define COM1A1 7 - -#define SFIOR _SFR_IO8(0x30) -#define ACME 3 -#define PSR2 1 -#define PSR10 0 -#define PUD 2 -#define ADHSM 4 - -#define OSCCAL _SFR_IO8(0x31) -#define OSCCAL0 0 -#define OSCCAL1 1 -#define OSCCAL2 2 -#define OSCCAL3 3 -#define OSCCAL4 4 -#define OSCCAL5 5 -#define OSCCAL6 6 -#define OSCCAL7 7 - -#define TCNT0 _SFR_IO8(0x32) - -#define TCCR0 _SFR_IO8(0x33) -#define CS00 0 -#define CS01 1 -#define CS02 2 - -#define MCUCSR _SFR_IO8(0x34) -#define PORF 0 -#define EXTRF 1 -#define BORF 2 -#define WDRF 3 - -#define MCUCR _SFR_IO8(0x35) -#define ISC00 0 -#define ISC01 1 -#define ISC10 2 -#define ISC11 3 -#define SM0 4 -#define SM1 5 -#define SM2 6 -#define SE 7 - -#define TWCR _SFR_IO8(0x36) -#define TWIE 0 -#define TWEN 2 -#define TWWC 3 -#define TWSTO 4 -#define TWSTA 5 -#define TWEA 6 -#define TWINT 7 - -#define SPMCR _SFR_IO8(0x37) -#define SPMEN 0 -#define PGERS 1 -#define PGWRT 2 -#define BLBSET 3 -#define RWWSRE 4 -#define RWWSB 6 -#define SPMIE 7 - -#define TIFR _SFR_IO8(0x38) -#define TOV0 0 -#define TOV1 2 -#define OCF1B 3 -#define OCF1A 4 -#define ICF1 5 -#define TOV2 6 -#define OCF2 7 - -#define TIMSK _SFR_IO8(0x39) -#define TOIE0 0 -#define TOIE1 2 -#define OCIE1B 3 -#define OCIE1A 4 -#define TICIE1 5 -#define TOIE2 6 -#define OCIE2 7 - -#define GIFR _SFR_IO8(0x3A) -#define INTF0 6 -#define INTF1 7 - -#define GICR _SFR_IO8(0x3B) -#define IVCE 0 -#define IVSEL 1 -#define INT0 6 -#define INT1 7 - -/* Reserved [0x3C] */ - -/* SP [0x3D..0x3E] */ - -/* SREG [0x3F] */ - - - -/* Values and associated defines */ - - -#define SLEEP_MODE_IDLE (0x00<<4) -#define SLEEP_MODE_ADC (0x01<<4) -#define SLEEP_MODE_PWR_DOWN (0x02<<4) -#define SLEEP_MODE_PWR_SAVE (0x03<<4) -#define SLEEP_MODE_STANDBY (0x06<<4) - -/* Interrupt vectors */ -/* Vector 0 is the reset vector */ -/* External Interrupt Request 0 */ -#define INT0_vect _VECTOR(1) -#define INT0_vect_num 1 - -/* External Interrupt Request 1 */ -#define INT1_vect _VECTOR(2) -#define INT1_vect_num 2 - -/* Timer/Counter2 Compare Match */ -#define TIMER2_COMP_vect _VECTOR(3) -#define TIMER2_COMP_vect_num 3 - -/* Timer/Counter2 Overflow */ -#define TIMER2_OVF_vect _VECTOR(4) -#define TIMER2_OVF_vect_num 4 - -/* Timer/Counter1 Capture Event */ -#define TIMER1_CAPT_vect _VECTOR(5) -#define TIMER1_CAPT_vect_num 5 - -/* Timer/Counter1 Compare Match A */ -#define TIMER1_COMPA_vect _VECTOR(6) -#define TIMER1_COMPA_vect_num 6 - -/* Timer/Counter1 Compare Match B */ -#define TIMER1_COMPB_vect _VECTOR(7) -#define TIMER1_COMPB_vect_num 7 - -/* Timer/Counter1 Overflow */ -#define TIMER1_OVF_vect _VECTOR(8) -#define TIMER1_OVF_vect_num 8 - -/* Timer/Counter0 Overflow */ -#define TIMER0_OVF_vect _VECTOR(9) -#define TIMER0_OVF_vect_num 9 - -/* Serial Transfer Complete */ -#define SPI_STC_vect _VECTOR(10) -#define SPI_STC_vect_num 10 - -/* USART, Rx Complete */ -#define USART_RXC_vect _VECTOR(11) -#define USART_RXC_vect_num 11 - -/* USART Data Register Empty */ -#define USART_UDRE_vect _VECTOR(12) -#define USART_UDRE_vect_num 12 - -/* USART, Tx Complete */ -#define USART_TXC_vect _VECTOR(13) -#define USART_TXC_vect_num 13 - -/* ADC Conversion Complete */ -#define ADC_vect _VECTOR(14) -#define ADC_vect_num 14 - -/* EEPROM Ready */ -#define EE_RDY_vect _VECTOR(15) -#define EE_RDY_vect_num 15 - -/* Analog Comparator */ -#define ANA_COMP_vect _VECTOR(16) -#define ANA_COMP_vect_num 16 - -/* 2-wire Serial Interface */ -#define TWI_vect _VECTOR(17) -#define TWI_vect_num 17 - -/* Store Program Memory Ready */ -#define SPM_RDY_vect _VECTOR(18) -#define SPM_RDY_vect_num 18 - -#define _VECTORS_SIZE 38 - - -/* Constants */ - -#define SPM_PAGESIZE 64 -#define FLASHSTART 0x0000 -#define FLASHEND 0x1FFF -#define RAMSTART 0x0060 -#define RAMSIZE 1024 -#define RAMEND 0x045F -#define E2START 0 -#define E2SIZE 512 -#define E2PAGESIZE 4 -#define E2END 0x01FF -#define XRAMEND RAMEND - - -/* Fuses */ - -#define FUSE_MEMORY_SIZE 2 - -/* Low Fuse Byte */ -#define FUSE_SUT_CKSEL0 (unsigned char)~_BV(0) -#define FUSE_SUT_CKSEL1 (unsigned char)~_BV(1) -#define FUSE_SUT_CKSEL2 (unsigned char)~_BV(2) -#define FUSE_SUT_CKSEL3 (unsigned char)~_BV(3) -#define FUSE_SUT_CKSEL4 (unsigned char)~_BV(4) -#define FUSE_SUT_CKSEL5 (unsigned char)~_BV(5) -#define FUSE_BODEN (unsigned char)~_BV(6) -#define FUSE_BODLEVEL (unsigned char)~_BV(7) -#define LFUSE_DEFAULT (FUSE_SUT_CKSEL1 & FUSE_SUT_CKSEL2 & FUSE_SUT_CKSEL3 & FUSE_SUT_CKSEL4) - - -/* High Fuse Byte */ -#define FUSE_BOOTRST (unsigned char)~_BV(0) -#define FUSE_BOOTSZ0 (unsigned char)~_BV(1) -#define FUSE_BOOTSZ1 (unsigned char)~_BV(2) -#define FUSE_EESAVE (unsigned char)~_BV(3) -#define FUSE_CKOPT (unsigned char)~_BV(4) -#define FUSE_SPIEN (unsigned char)~_BV(5) -#define FUSE_WTDON (unsigned char)~_BV(6) -#define FUSE_RSTDISBL (unsigned char)~_BV(7) -#define HFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_SPIEN) - - - -/* Lock Bits */ -#define __LOCK_BITS_EXIST -#define __BOOT_LOCK_BITS_0_EXIST -#define __BOOT_LOCK_BITS_1_EXIST - - -/* Signature */ -#define SIGNATURE_0 0x1E -#define SIGNATURE_1 0x93 -#define SIGNATURE_2 0x07 - - -#endif /* #ifdef _AVR_ATMEGA8A_H_INCLUDED */ - diff --git a/arduino/hardware/tools/avr/avr/include/avr/iom8hva.h b/arduino/hardware/tools/avr/avr/include/avr/iom8hva.h deleted file mode 100644 index f900c58..0000000 --- a/arduino/hardware/tools/avr/avr/include/avr/iom8hva.h +++ /dev/null @@ -1,76 +0,0 @@ -/* Copyright (c) 2007, Anatoly Sokolov - All rights reserved. - - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - * Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - * Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in - the documentation and/or other materials provided with the - distribution. - - * Neither the name of the copyright holders nor the names of - contributors may be used to endorse or promote products derived - from this software without specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. */ - -/* $Id: iom8hva.h 2102 2010-03-16 22:52:39Z joerg_wunsch $ */ - -/* iom8hva.h - definitions for ATmega8HVA. */ - -#ifndef _AVR_IOM8HVA_H_ -#define _AVR_IOM8HVA_H_ 1 - -#include - -/* Constants */ -#define SPM_PAGESIZE 128 -#define RAMSTART 0x100 -#define RAMEND 0x2FF -#define XRAMEND RAMEND -#define E2END 0xFF -#define E2PAGESIZE 4 -#define FLASHEND 0x1FFF - - -/* Fuses */ - -#define FUSE_MEMORY_SIZE 1 - -/* Low Fuse Byte */ -#define FUSE_SUT0 (unsigned char)~_BV(0) -#define FUSE_SUT1 (unsigned char)~_BV(1) -#define FUSE_SUT2 (unsigned char)~_BV(2) -#define FUSE_SELFPRGEN (unsigned char)~_BV(3) -#define FUSE_DWEN (unsigned char)~_BV(4) -#define FUSE_SPIEN (unsigned char)~_BV(5) -#define FUSE_EESAVE (unsigned char)~_BV(6) -#define FUSE_WDTON (unsigned char)~_BV(7) -#define FUSE_DEFAULT (FUSE_SPIEN) - - -/* Lock Bits */ -#define __LOCK_BITS_EXIST - - -#define SLEEP_MODE_IDLE (0x00<<1) -#define SLEEP_MODE_ADC (0x01<<1) -#define SLEEP_MODE_PWR_SAVE (0x03<<1) -#define SLEEP_MODE_PWR_OFF (0x04<<1) - -#endif /* _AVR_IOM8HVA_H_ */ - diff --git a/arduino/hardware/tools/avr/avr/include/avr/iom8u2.h b/arduino/hardware/tools/avr/avr/include/avr/iom8u2.h deleted file mode 100644 index fa4c43a..0000000 --- a/arduino/hardware/tools/avr/avr/include/avr/iom8u2.h +++ /dev/null @@ -1,997 +0,0 @@ -/* Copyright (c) 2009 Atmel Corporation - All rights reserved. - - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - * Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - * Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in - the documentation and/or other materials provided with the - distribution. - - * Neither the name of the copyright holders nor the names of - contributors may be used to endorse or promote products derived - from this software without specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. */ - -/* $Id: iom8u2.h 2245 2011-05-12 22:42:21Z arcanum $ */ - -/* avr/iom8u2.h - definitions for ATmega8U2 */ - -/* This file should only be included from , never directly. */ - -#ifndef _AVR_IO_H_ -# error "Include instead of this file." -#endif - -#ifndef _AVR_IOXXX_H_ -# define _AVR_IOXXX_H_ "iom8u2.h" -#else -# error "Attempt to include more than one file." -#endif - - -#ifndef _AVR_ATmega8U2_H_ -#define _AVR_ATmega8U2_H_ 1 - - -/* Registers and associated bit numbers. */ - -#define PINB _SFR_IO8(0x03) -#define PINB0 0 -#define PINB1 1 -#define PINB2 2 -#define PINB3 3 -#define PINB4 4 -#define PINB5 5 -#define PINB6 6 -#define PINB7 7 - -#define DDRB _SFR_IO8(0x04) -#define DDB0 0 -#define DDB1 1 -#define DDB2 2 -#define DDB3 3 -#define DDB4 4 -#define DDB5 5 -#define DDB6 6 -#define DDB7 7 - -#define PORTB _SFR_IO8(0x05) -#define PORTB0 0 -#define PORTB1 1 -#define PORTB2 2 -#define PORTB3 3 -#define PORTB4 4 -#define PORTB5 5 -#define PORTB6 6 -#define PORTB7 7 - -#define PINC _SFR_IO8(0x06) -#define PINC0 0 -#define PINC1 1 -#define PINC2 2 -#define PINC4 4 -#define PINC5 5 -#define PINC6 6 -#define PINC7 7 - -#define DDRC _SFR_IO8(0x07) -#define DDC0 0 -#define DDC1 1 -#define DDC2 2 -#define DDC4 4 -#define DDC5 5 -#define DDC6 6 -#define DDC7 7 - -#define PORTC _SFR_IO8(0x08) -#define PORTC0 0 -#define PORTC1 1 -#define PORTC2 2 -#define PORTC4 4 -#define PORTC5 5 -#define PORTC6 6 -#define PORTC7 7 - -#define PIND _SFR_IO8(0x09) -#define PIND0 0 -#define PIND1 1 -#define PIND2 2 -#define PIND3 3 -#define PIND4 4 -#define PIND5 5 -#define PIND6 6 -#define PIND7 7 - -#define DDRD _SFR_IO8(0x0A) -#define DDD0 0 -#define DDD1 1 -#define DDD2 2 -#define DDD3 3 -#define DDD4 4 -#define DDD5 5 -#define DDD6 6 -#define DDD7 7 - -#define PORTD _SFR_IO8(0x0B) -#define PORTD0 0 -#define PORTD1 1 -#define PORTD2 2 -#define PORTD3 3 -#define PORTD4 4 -#define PORTD5 5 -#define PORTD6 6 -#define PORTD7 7 - -#define TIFR0 _SFR_IO8(0x15) -#define TOV0 0 -#define OCF0A 1 -#define OCF0B 2 - -#define TIFR1 _SFR_IO8(0x16) -#define TOV1 0 -#define OCF1A 1 -#define OCF1B 2 -#define OCF1C 3 -#define ICF1 5 - -#define PCIFR _SFR_IO8(0x1B) -#define PCIF0 0 -#define PCIF1 1 - -#define EIFR _SFR_IO8(0x1C) -#define INTF0 0 -#define INTF1 1 -#define INTF2 2 -#define INTF3 3 -#define INTF4 4 -#define INTF5 5 -#define INTF6 6 -#define INTF7 7 - -#define EIMSK _SFR_IO8(0x1D) -#define INT0 0 -#define INT1 1 -#define INT2 2 -#define INT3 3 -#define INT4 4 -#define INT5 5 -#define INT6 6 -#define INT7 7 - -#define GPIOR0 _SFR_IO8(0x1E) -#define GPIOR00 0 -#define GPIOR01 1 -#define GPIOR02 2 -#define GPIOR03 3 -#define GPIOR04 4 -#define GPIOR05 5 -#define GPIOR06 6 -#define GPIOR07 7 - -#define EECR _SFR_IO8(0x1F) -#define EERE 0 -#define EEPE 1 -#define EEMPE 2 -#define EERIE 3 -#define EEPM0 4 -#define EEPM1 5 - -#define EEDR _SFR_IO8(0x20) -#define EEDR0 0 -#define EEDR1 1 -#define EEDR2 2 -#define EEDR3 3 -#define EEDR4 4 -#define EEDR5 5 -#define EEDR6 6 -#define EEDR7 7 - -#define EEAR _SFR_IO16(0x21) - -#define EEARL _SFR_IO8(0x21) -#define EEAR0 0 -#define EEAR1 1 -#define EEAR2 2 -#define EEAR3 3 -#define EEAR4 4 -#define EEAR5 5 -#define EEAR6 6 -#define EEAR7 7 - -#define EEARH _SFR_IO8(0x22) -#define EEAR8 0 -#define EEAR9 1 -#define EEAR10 2 -#define EEAR11 3 - -#define GTCCR _SFR_IO8(0x23) -#define PSRSYNC 0 -#define TSM 7 - -#define TCCR0A _SFR_IO8(0x24) -#define WGM00 0 -#define WGM01 1 -#define COM0B0 4 -#define COM0B1 5 -#define COM0A0 6 -#define COM0A1 7 - -#define TCCR0B _SFR_IO8(0x25) -#define CS00 0 -#define CS01 1 -#define CS02 2 -#define WGM02 3 -#define FOC0B 6 -#define FOC0A 7 - -#define TCNT0 _SFR_IO8(0x26) -#define TCNT0_0 0 -#define TCNT0_1 1 -#define TCNT0_2 2 -#define TCNT0_3 3 -#define TCNT0_4 4 -#define TCNT0_5 5 -#define TCNT0_6 6 -#define TCNT0_7 7 - -#define OCR0A _SFR_IO8(0x27) -#define OCR0A_0 0 -#define OCR0A_1 1 -#define OCR0A_2 2 -#define OCR0A_3 3 -#define OCR0A_4 4 -#define OCR0A_5 5 -#define OCR0A_6 6 -#define OCR0A_7 7 - -#define OCR0B _SFR_IO8(0x28) -#define OCR0B_0 0 -#define OCR0B_1 1 -#define OCR0B_2 2 -#define OCR0B_3 3 -#define OCR0B_4 4 -#define OCR0B_5 5 -#define OCR0B_6 6 -#define OCR0B_7 7 - -#define PLLCSR _SFR_IO8(0x29) -#define PLOCK 0 -#define PLLE 1 -#define PLLP0 2 -#define PLLP1 3 -#define PLLP2 4 - -#define GPIOR1 _SFR_IO8(0x2A) -#define GPIOR10 0 -#define GPIOR11 1 -#define GPIOR12 2 -#define GPIOR13 3 -#define GPIOR14 4 -#define GPIOR15 5 -#define GPIOR16 6 -#define GPIOR17 7 - -#define GPIOR2 _SFR_IO8(0x2B) -#define GPIOR20 0 -#define GPIOR21 1 -#define GPIOR22 2 -#define GPIOR23 3 -#define GPIOR24 4 -#define GPIOR25 5 -#define GPIOR26 6 -#define GPIOR27 7 - -#define SPCR _SFR_IO8(0x2C) -#define SPR0 0 -#define SPR1 1 -#define CPHA 2 -#define CPOL 3 -#define MSTR 4 -#define DORD 5 -#define SPE 6 -#define SPIE 7 - -#define SPSR _SFR_IO8(0x2D) -#define SPI2X 0 -#define WCOL 6 -#define SPIF 7 - -#define SPDR _SFR_IO8(0x2E) -#define SPDR0 0 -#define SPDR1 1 -#define SPDR2 2 -#define SPDR3 3 -#define SPDR4 4 -#define SPDR5 5 -#define SPDR6 6 -#define SPDR7 7 - -#define ACSR _SFR_IO8(0x30) -#define ACIS0 0 -#define ACIS1 1 -#define ACIC 2 -#define ACIE 3 -#define ACI 4 -#define ACO 5 -#define ACBG 6 -#define ACD 7 - -#define DWDR _SFR_IO8(0x31) -#define DWDR0 0 -#define DWDR1 1 -#define DWDR2 2 -#define DWDR3 3 -#define DWDR4 4 -#define DWDR5 5 -#define DWDR6 6 -#define DWDR7 7 - -#define SMCR _SFR_IO8(0x33) -#define SE 0 -#define SM0 1 -#define SM1 2 -#define SM2 3 - -#define MCUSR _SFR_IO8(0x34) -#define PORF 0 -#define EXTRF 1 -#define BORF 2 -#define WDRF 3 -#define USBRF 5 - -#define MCUCR _SFR_IO8(0x35) -#define IVCE 0 -#define IVSEL 1 -#define PUD 4 - -#define SPMCSR _SFR_IO8(0x37) -#define SPMEN 0 -#define PGERS 1 -#define PGWRT 2 -#define BLBSET 3 -#define RWWSRE 4 -#define SIGRD 5 -#define RWWSB 6 -#define SPMIE 7 - -#define EIND _SFR_IO8(0x3C) -#define EIND0 0 - -#define WDTCSR _SFR_MEM8(0x60) -#define WDP0 0 -#define WDP1 1 -#define WDP2 2 -#define WDE 3 -#define WDCE 4 -#define WDP3 5 -#define WDIE 6 -#define WDIF 7 - -#define CLKPR _SFR_MEM8(0x61) -#define CLKPS0 0 -#define CLKPS1 1 -#define CLKPS2 2 -#define CLKPS3 3 -#define CLKPCE 7 - -#define WDTCKD _SFR_MEM8(0x62) -#define WCLKD0 0 -#define WCLKD1 1 -#define WDEWIE 2 -#define WDEWIF 3 - -#define REGCR _SFR_MEM8(0x63) -#define REGDIS 0 - -#define PRR0 _SFR_MEM8(0x64) -#define PRSPI 2 -#define PRTIM1 3 -#define PRTIM0 5 - -#define __AVR_HAVE_PRR0 ((1<, never directly. */ - -#ifndef _AVR_IO_H_ -# error "Include instead of this file." -#endif - -#ifndef _AVR_IOXXX_H_ -# define _AVR_IOXXX_H_ "iomx8.h" -#else -# error "Attempt to include more than one file." -#endif - -/* I/O registers */ - -/* Port B */ - -#define PINB _SFR_IO8 (0x03) -/* PINB */ -#define PINB7 7 -#define PINB6 6 -#define PINB5 5 -#define PINB4 4 -#define PINB3 3 -#define PINB2 2 -#define PINB1 1 -#define PINB0 0 - -#define DDRB _SFR_IO8 (0x04) -/* DDRB */ -#define DDB7 7 -#define DDB6 6 -#define DDB5 5 -#define DDB4 4 -#define DDB3 3 -#define DDB2 2 -#define DDB1 1 -#define DDB0 0 - -#define PORTB _SFR_IO8 (0x05) -/* PORTB */ -#define PB7 7 -#define PB6 6 -#define PB5 5 -#define PB4 4 -#define PB3 3 -#define PB2 2 -#define PB1 1 -#define PB0 0 - -/* Port C */ - -#define PINC _SFR_IO8 (0x06) -/* PINC */ -#define PINC6 6 -#define PINC5 5 -#define PINC4 4 -#define PINC3 3 -#define PINC2 2 -#define PINC1 1 -#define PINC0 0 - -#define DDRC _SFR_IO8 (0x07) -/* DDRC */ -#define DDC6 6 -#define DDC5 5 -#define DDC4 4 -#define DDC3 3 -#define DDC2 2 -#define DDC1 1 -#define DDC0 0 - -#define PORTC _SFR_IO8 (0x08) -/* PORTC */ -#define PC6 6 -#define PC5 5 -#define PC4 4 -#define PC3 3 -#define PC2 2 -#define PC1 1 -#define PC0 0 - -/* Port D */ - -#define PIND _SFR_IO8 (0x09) -/* PIND */ -#define PIND7 7 -#define PIND6 6 -#define PIND5 5 -#define PIND4 4 -#define PIND3 3 -#define PIND2 2 -#define PIND1 1 -#define PIND0 0 - -#define DDRD _SFR_IO8 (0x0A) -/* DDRD */ -#define DDD7 7 -#define DDD6 6 -#define DDD5 5 -#define DDD4 4 -#define DDD3 3 -#define DDD2 2 -#define DDD1 1 -#define DDD0 0 - -#define PORTD _SFR_IO8 (0x0B) -/* PORTD */ -#define PD7 7 -#define PD6 6 -#define PD5 5 -#define PD4 4 -#define PD3 3 -#define PD2 2 -#define PD1 1 -#define PD0 0 - -#define TIFR0 _SFR_IO8 (0x15) -/* TIFR0 */ -#define OCF0B 2 -#define OCF0A 1 -#define TOV0 0 - -#define TIFR1 _SFR_IO8 (0x16) -/* TIFR1 */ -#define ICF1 5 -#define OCF1B 2 -#define OCF1A 1 -#define TOV1 0 - -#define TIFR2 _SFR_IO8 (0x17) -/* TIFR2 */ -#define OCF2B 2 -#define OCF2A 1 -#define TOV2 0 - -#define PCIFR _SFR_IO8 (0x1B) -/* PCIFR */ -#define PCIF2 2 -#define PCIF1 1 -#define PCIF0 0 - -#define EIFR _SFR_IO8 (0x1C) -/* EIFR */ -#define INTF1 1 -#define INTF0 0 - -#define EIMSK _SFR_IO8 (0x1D) -/* EIMSK */ -#define INT1 1 -#define INT0 0 - -#define GPIOR0 _SFR_IO8 (0x1E) - -#define EECR _SFR_IO8(0x1F) -/* EECT - EEPROM Control Register */ -#define EEPM1 5 -#define EEPM0 4 -#define EERIE 3 -#define EEMPE 2 -#define EEPE 1 -#define EERE 0 - -#define EEDR _SFR_IO8(0X20) - -/* Combine EEARL and EEARH */ -#define EEAR _SFR_IO16(0x21) -#define EEARL _SFR_IO8(0x21) -#define EEARH _SFR_IO8(0X22) -/* -Even though EEARH is not used by the mega48, the EEAR8 bit in the register -must be written to 0, according to the datasheet, hence the EEARH register -must be defined for the mega48. -*/ -/* 6-char sequence denoting where to find the EEPROM registers in memory space. - Adresses denoted in hex syntax with uppercase letters. Used by the EEPROM - subroutines. - First two letters: EECR address. - Second two letters: EEDR address. - Last two letters: EEAR address. */ -#define __EEPROM_REG_LOCATIONS__ 1F2021 - - -#define GTCCR _SFR_IO8 (0x23) -/* GTCCR */ -#define TSM 7 -#define PSRASY 1 -#define PSRSYNC 0 - -#define TCCR0A _SFR_IO8 (0x24) -/* TCCR0A */ -#define COM0A1 7 -#define COM0A0 6 -#define COM0B1 5 -#define COM0B0 4 -#define WGM01 1 -#define WGM00 0 - -#define TCCR0B _SFR_IO8 (0x25) -/* TCCR0A */ -#define FOC0A 7 -#define FOC0B 6 -#define WGM02 3 -#define CS02 2 -#define CS01 1 -#define CS00 0 - -#define TCNT0 _SFR_IO8 (0x26) -#define OCR0A _SFR_IO8 (0x27) -#define OCR0B _SFR_IO8 (0x28) - -#define GPIOR1 _SFR_IO8 (0x2A) -#define GPIOR2 _SFR_IO8 (0x2B) - -#define SPCR _SFR_IO8 (0x2C) -/* SPCR */ -#define SPIE 7 -#define SPE 6 -#define DORD 5 -#define MSTR 4 -#define CPOL 3 -#define CPHA 2 -#define SPR1 1 -#define SPR0 0 - -#define SPSR _SFR_IO8 (0x2D) -/* SPSR */ -#define SPIF 7 -#define WCOL 6 -#define SPI2X 0 - -#define SPDR _SFR_IO8 (0x2E) - -#define ACSR _SFR_IO8 (0x30) -/* ACSR */ -#define ACD 7 -#define ACBG 6 -#define ACO 5 -#define ACI 4 -#define ACIE 3 -#define ACIC 2 -#define ACIS1 1 -#define ACIS0 0 - -#define MONDR _SFR_IO8 (0x31) - -#define SMCR _SFR_IO8 (0x33) -/* SMCR */ -#define SM2 3 -#define SM1 2 -#define SM0 1 -#define SE 0 - -#define MCUSR _SFR_IO8 (0x34) -/* MCUSR */ -#define WDRF 3 -#define BORF 2 -#define EXTRF 1 -#define PORF 0 - -#define MCUCR _SFR_IO8 (0x35) -/* MCUCR */ -#define PUD 4 -#if defined (__AVR_ATmega88__) || defined (__AVR_ATmega168__) || defined (__AVR_ATmega48A__) || defined(__AVR_ATmega48PA__) -#define IVSEL 1 -#define IVCE 0 -#endif - -#define SPMCSR _SFR_IO8 (0x37) -/* SPMCSR */ -#define SPMIE 7 -#if defined (__AVR_ATmega88__) || defined (__AVR_ATmega168__) || (__AVR_ATmega88P__) || defined (__AVR_ATmega168P__) || (__AVR_ATmega88A__) || defined (__AVR_ATmega168A__) || (__AVR_ATmega88PA__) || defined (__AVR_ATmega168PA__) -# define RWWSB 6 -# define RWWSRE 4 -#endif -#if defined(__AVR_ATmega48A) || defined(__AVR_ATmega48PA) || defined(__AVR_ATmega88A) || defined(__AVR_ATmega88PA) || defined(__AVR_ATmega168A) || defined(__AVR_ATmega168PA) - #define SIGRD 5 -#endif -#define BLBSET 3 -#define PGWRT 2 -#define PGERS 1 -#define SELFPRGEN 0 -#define SPMEN 0 - -/* 0x3D..0x3E SP [defined in ] */ -/* 0x3F SREG [defined in ] */ - -#define WDTCSR _SFR_MEM8 (0x60) -/* WDTCSR */ -#define WDIF 7 -#define WDIE 6 -#define WDP3 5 -#define WDCE 4 -#define WDE 3 -#define WDP2 2 -#define WDP1 1 -#define WDP0 0 - -#define CLKPR _SFR_MEM8 (0x61) -/* CLKPR */ -#define CLKPCE 7 -#define CLKPS3 3 -#define CLKPS2 2 -#define CLKPS1 1 -#define CLKPS0 0 - -#define PRR _SFR_MEM8 (0x64) -/* PRR */ -#define PRTWI 7 -#define PRTIM2 6 -#define PRTIM0 5 -#define PRTIM1 3 -#define PRSPI 2 -#define PRUSART0 1 -#define PRADC 0 - -#define __AVR_HAVE_PRR ((1<, never directly. */ - -#ifndef _AVR_IO_H_ -# error "Include instead of this file." -#endif - -#ifndef _AVR_IOXXX_H_ -# define _AVR_IOXXX_H_ "iomxx0_1.h" -#else -# error "Attempt to include more than one file." -#endif - -#if defined(__AVR_ATmega640__) || defined(__AVR_ATmega1280__) || defined(__AVR_ATmega2560__) -# define __ATmegaxx0__ -#elif defined(__AVR_ATmega1281__) || defined(__AVR_ATmega2561__) -# define __ATmegaxx1__ -#endif - -/* Registers and associated bit numbers */ - -#define PINA _SFR_IO8(0X00) -#define PINA7 7 -#define PINA6 6 -#define PINA5 5 -#define PINA4 4 -#define PINA3 3 -#define PINA2 2 -#define PINA1 1 -#define PINA0 0 - -#define DDRA _SFR_IO8(0X01) -#define DDA7 7 -#define DDA6 6 -#define DDA5 5 -#define DDA4 4 -#define DDA3 3 -#define DDA2 2 -#define DDA1 1 -#define DDA0 0 - -#define PORTA _SFR_IO8(0X02) -#define PA7 7 -#define PA6 6 -#define PA5 5 -#define PA4 4 -#define PA3 3 -#define PA2 2 -#define PA1 1 -#define PA0 0 - -#define PINB _SFR_IO8(0X03) -#define PINB7 7 -#define PINB6 6 -#define PINB5 5 -#define PINB4 4 -#define PINB3 3 -#define PINB2 2 -#define PINB1 1 -#define PINB0 0 - -#define DDRB _SFR_IO8(0x04) -#define DDB7 7 -#define DDB6 6 -#define DDB5 5 -#define DDB4 4 -#define DDB3 3 -#define DDB2 2 -#define DDB1 1 -#define DDB0 0 - -#define PORTB _SFR_IO8(0x05) -#define PB7 7 -#define PB6 6 -#define PB5 5 -#define PB4 4 -#define PB3 3 -#define PB2 2 -#define PB1 1 -#define PB0 0 - -#define PINC _SFR_IO8(0x06) -#define PINC7 7 -#define PINC6 6 -#define PINC5 5 -#define PINC4 4 -#define PINC3 3 -#define PINC2 2 -#define PINC1 1 -#define PINC0 0 - -#define DDRC _SFR_IO8(0x07) -#define DDC7 7 -#define DDC6 6 -#define DDC5 5 -#define DDC4 4 -#define DDC3 3 -#define DDC2 2 -#define DDC1 1 -#define DDC0 0 - -#define PORTC _SFR_IO8(0x08) -#define PC7 7 -#define PC6 6 -#define PC5 5 -#define PC4 4 -#define PC3 3 -#define PC2 2 -#define PC1 1 -#define PC0 0 - -#define PIND _SFR_IO8(0x09) -#define PIND7 7 -#define PIND6 6 -#define PIND5 5 -#define PIND4 4 -#define PIND3 3 -#define PIND2 2 -#define PIND1 1 -#define PIND0 0 - -#define DDRD _SFR_IO8(0x0A) -#define DDD7 7 -#define DDD6 6 -#define DDD5 5 -#define DDD4 4 -#define DDD3 3 -#define DDD2 2 -#define DDD1 1 -#define DDD0 0 - -#define PORTD _SFR_IO8(0x0B) -#define PD7 7 -#define PD6 6 -#define PD5 5 -#define PD4 4 -#define PD3 3 -#define PD2 2 -#define PD1 1 -#define PD0 0 - -#define PINE _SFR_IO8(0x0C) -#define PINE7 7 -#define PINE6 6 -#define PINE5 5 -#define PINE4 4 -#define PINE3 3 -#define PINE2 2 -#define PINE1 1 -#define PINE0 0 - -#define DDRE _SFR_IO8(0x0D) -#define DDE7 7 -#define DDE6 6 -#define DDE5 5 -#define DDE4 4 -#define DDE3 3 -#define DDE2 2 -#define DDE1 1 -#define DDE0 0 - -#define PORTE _SFR_IO8(0x0E) -#define PE7 7 -#define PE6 6 -#define PE5 5 -#define PE4 4 -#define PE3 3 -#define PE2 2 -#define PE1 1 -#define PE0 0 - -#define PINF _SFR_IO8(0x0F) -#define PINF7 7 -#define PINF6 6 -#define PINF5 5 -#define PINF4 4 -#define PINF3 3 -#define PINF2 2 -#define PINF1 1 -#define PINF0 0 - -#define DDRF _SFR_IO8(0x10) -#define DDF7 7 -#define DDF6 6 -#define DDF5 5 -#define DDF4 4 -#define DDF3 3 -#define DDF2 2 -#define DDF1 1 -#define DDF0 0 - -#define PORTF _SFR_IO8(0x11) -#define PF7 7 -#define PF6 6 -#define PF5 5 -#define PF4 4 -#define PF3 3 -#define PF2 2 -#define PF1 1 -#define PF0 0 - -#define PING _SFR_IO8(0x12) -#define PING5 5 -#define PING4 4 -#define PING3 3 -#define PING2 2 -#define PING1 1 -#define PING0 0 - -#define DDRG _SFR_IO8(0x13) -#define DDG5 5 -#define DDG4 4 -#define DDG3 3 -#define DDG2 2 -#define DDG1 1 -#define DDG0 0 - -#define PORTG _SFR_IO8(0x14) -#define PG5 5 -#define PG4 4 -#define PG3 3 -#define PG2 2 -#define PG1 1 -#define PG0 0 - -#define TIFR0 _SFR_IO8(0x15) -#define OCF0B 2 -#define OCF0A 1 -#define TOV0 0 - -#define TIFR1 _SFR_IO8(0x16) -#define ICF1 5 -#define OCF1C 3 -#define OCF1B 2 -#define OCF1A 1 -#define TOV1 0 - -#define TIFR2 _SFR_IO8(0x17) -#define OCF2B 2 -#define OCF2A 1 -#define TOV2 0 - -#define TIFR3 _SFR_IO8(0x18) -#define ICF3 5 -#define OCF3C 3 -#define OCF3B 2 -#define OCF3A 1 -#define TOV3 0 - -#define TIFR4 _SFR_IO8(0x19) -#define ICF4 5 -#define OCF4C 3 -#define OCF4B 2 -#define OCF4A 1 -#define TOV4 0 - -#define TIFR5 _SFR_IO8(0x1A) -#define ICF5 5 -#define OCF5C 3 -#define OCF5B 2 -#define OCF5A 1 -#define TOV5 0 - -#define PCIFR _SFR_IO8(0x1B) -#if defined(__ATmegaxx0__) -# define PCIF2 2 -#endif /* __ATmegaxx0__ */ -#define PCIF1 1 -#define PCIF0 0 - -#define EIFR _SFR_IO8(0x1C) -#define INTF7 7 -#define INTF6 6 -#define INTF5 5 -#define INTF4 4 -#define INTF3 3 -#define INTF2 2 -#define INTF1 1 -#define INTF0 0 - -#define EIMSK _SFR_IO8(0x1D) -#define INT7 7 -#define INT6 6 -#define INT5 5 -#define INT4 4 -#define INT3 3 -#define INT2 2 -#define INT1 1 -#define INT0 0 - -#define GPIOR0 _SFR_IO8(0x1E) - -#define EECR _SFR_IO8(0x1F) -#define EEPM1 5 -#define EEPM0 4 -#define EERIE 3 -#define EEMPE 2 -#define EEPE 1 -#define EERE 0 - -#define EEDR _SFR_IO8(0X20) - -/* Combine EEARL and EEARH */ -#define EEAR _SFR_IO16(0x21) - -#define EEARL _SFR_IO8(0x21) -#define EEARH _SFR_IO8(0X22) - -/* 6-char sequence denoting where to find the EEPROM registers in memory space. - Adresses denoted in hex syntax with uppercase letters. Used by the EEPROM - subroutines. - First two letters: EECR address. - Second two letters: EEDR address. - Last two letters: EEAR address. */ -#define __EEPROM_REG_LOCATIONS__ 1F2021 - -#define GTCCR _SFR_IO8(0x23) -#define TSM 7 -#define PSRASY 1 -#define PSRSYNC 0 - -#define TCCR0A _SFR_IO8(0x24) -#define COM0A1 7 -#define COM0A0 6 -#define COM0B1 5 -#define COM0B0 4 -#define WGM01 1 -#define WGM00 0 - -#define TCCR0B _SFR_IO8(0x25) -#define FOC0A 7 -#define FOC0B 6 -#define WGM02 3 -#define CS02 2 -#define CS01 1 -#define CS00 0 - -#define TCNT0 _SFR_IO8(0X26) - -#define OCR0A _SFR_IO8(0X27) - -#define OCR0B _SFR_IO8(0X28) - -/* Reserved [0x29] */ - -#define GPIOR1 _SFR_IO8(0x2A) - -#define GPIOR2 _SFR_IO8(0x2B) - -#define SPCR _SFR_IO8(0x2C) -#define SPIE 7 -#define SPE 6 -#define DORD 5 -#define MSTR 4 -#define CPOL 3 -#define CPHA 2 -#define SPR1 1 -#define SPR0 0 - -#define SPSR _SFR_IO8(0x2D) -#define SPIF 7 -#define WCOL 6 -#define SPI2X 0 - -#define SPDR _SFR_IO8(0X2E) - -/* Reserved [0x2F] */ - -#define ACSR _SFR_IO8(0x30) -#define ACD 7 -#define ACBG 6 -#define ACO 5 -#define ACI 4 -#define ACIE 3 -#define ACIC 2 -#define ACIS1 1 -#define ACIS0 0 - -#define MONDR _SFR_IO8(0x31) -#define OCDR _SFR_IO8(0x31) -#define IDRD 7 -#define OCDR7 7 -#define OCDR6 6 -#define OCDR5 5 -#define OCDR4 4 -#define OCDR3 3 -#define OCDR2 2 -#define OCDR1 1 -#define OCDR0 0 - -/* Reserved [0x32] */ - -#define SMCR _SFR_IO8(0x33) -#define SM2 3 -#define SM1 2 -#define SM0 1 -#define SE 0 - -#define MCUSR _SFR_IO8(0x34) -#define JTRF 4 -#define WDRF 3 -#define BORF 2 -#define EXTRF 1 -#define PORF 0 - -#define MCUCR _SFR_IO8(0X35) -#define JTD 7 -#define PUD 4 -#define IVSEL 1 -#define IVCE 0 - -/* Reserved [0x36] */ - -#define SPMCSR _SFR_IO8(0x37) -#define SPMIE 7 -#define RWWSB 6 -#define SIGRD 5 -#define RWWSRE 4 -#define BLBSET 3 -#define PGWRT 2 -#define PGERS 1 -#define SPMEN 0 - -/* Reserved [0x38..0x3A] */ - -#define RAMPZ _SFR_IO8(0X3B) -#define RAMPZ0 0 - -#define EIND _SFR_IO8(0X3C) -#define EIND0 0 - -/* SP [0x3D..0x3E] */ -/* SREG [0x3F] */ - -#define WDTCSR _SFR_MEM8(0x60) -#define WDIF 7 -#define WDIE 6 -#define WDP3 5 -#define WDCE 4 -#define WDE 3 -#define WDP2 2 -#define WDP1 1 -#define WDP0 0 - -#define CLKPR _SFR_MEM8(0x61) -#define CLKPCE 7 -#define CLKPS3 3 -#define CLKPS2 2 -#define CLKPS1 1 -#define CLKPS0 0 - -/* Reserved [0x62..0x63] */ - -#define PRR0 _SFR_MEM8(0x64) -#define PRTWI 7 -#define PRTIM2 6 -#define PRTIM0 5 -#define PRTIM1 3 -#define PRSPI 2 -#define PRUSART0 1 -#define PRADC 0 - -#define __AVR_HAVE_PRR0 ((1<, never directly. */ - -#ifndef _AVR_IO_H_ -# error "Include instead of this file." -#endif - -#ifndef _AVR_IOXXX_H_ -# define _AVR_IOXXX_H_ "iom164.h" -#else -# error "Attempt to include more than one file." -#endif - -/* Registers and associated bit numbers */ - -#define PINA _SFR_IO8(0X00) -#define PINA7 7 -#define PINA6 6 -#define PINA5 5 -#define PINA4 4 -#define PINA3 3 -#define PINA2 2 -#define PINA1 1 -#define PINA0 0 - -#define DDRA _SFR_IO8(0X01) -#define DDA7 7 -#define DDA6 6 -#define DDA5 5 -#define DDA4 4 -#define DDA3 3 -#define DDA2 2 -#define DDA1 1 -#define DDA0 0 - -#define PORTA _SFR_IO8(0X02) -#define PA7 7 -#define PA6 6 -#define PA5 5 -#define PA4 4 -#define PA3 3 -#define PA2 2 -#define PA1 1 -#define PA0 0 - -#define PINB _SFR_IO8(0X03) -#define PINB7 7 -#define PINB6 6 -#define PINB5 5 -#define PINB4 4 -#define PINB3 3 -#define PINB2 2 -#define PINB1 1 -#define PINB0 0 - -#define DDRB _SFR_IO8(0x04) -#define DDB7 7 -#define DDB6 6 -#define DDB5 5 -#define DDB4 4 -#define DDB3 3 -#define DDB2 2 -#define DDB1 1 -#define DDB0 0 - -#define PORTB _SFR_IO8(0x05) -#define PB7 7 -#define PB6 6 -#define PB5 5 -#define PB4 4 -#define PB3 3 -#define PB2 2 -#define PB1 1 -#define PB0 0 - -#define PINC _SFR_IO8(0x06) -#define PINC7 7 -#define PINC6 6 -#define PINC5 5 -#define PINC4 4 -#define PINC3 3 -#define PINC2 2 -#define PINC1 1 -#define PINC0 0 - -#define DDRC _SFR_IO8(0x07) -#define DDC7 7 -#define DDC6 6 -#define DDC5 5 -#define DDC4 4 -#define DDC3 3 -#define DDC2 2 -#define DDC1 1 -#define DDC0 0 - -#define PORTC _SFR_IO8(0x08) -#define PC7 7 -#define PC6 6 -#define PC5 5 -#define PC4 4 -#define PC3 3 -#define PC2 2 -#define PC1 1 -#define PC0 0 - -#define PIND _SFR_IO8(0x09) -#define PIND7 7 -#define PIND6 6 -#define PIND5 5 -#define PIND4 4 -#define PIND3 3 -#define PIND2 2 -#define PIND1 1 -#define PIND0 0 - -#define DDRD _SFR_IO8(0x0A) -#define DDD7 7 -#define DDD6 6 -#define DDD5 5 -#define DDD4 4 -#define DDD3 3 -#define DDD2 2 -#define DDD1 1 -#define DDD0 0 - -#define PORTD _SFR_IO8(0x0B) -#define PD7 7 -#define PD6 6 -#define PD5 5 -#define PD4 4 -#define PD3 3 -#define PD2 2 -#define PD1 1 -#define PD0 0 - -/* Reserved [0x0C..0x14] */ - -#define TIFR0 _SFR_IO8(0x15) -#define OCF0B 2 -#define OCF0A 1 -#define TOV0 0 - -#define TIFR1 _SFR_IO8(0x16) -#define ICF1 5 -#define OCF1B 2 -#define OCF1A 1 -#define TOV1 0 - -#define TIFR2 _SFR_IO8(0x17) -#define OCF2B 2 -#define OCF2A 1 -#define TOV2 0 - -/* Reserved [0x18..0x1A] */ - -#define PCIFR _SFR_IO8(0x1B) -#define PCIF3 3 -#define PCIF2 2 -#define PCIF1 1 -#define PCIF0 0 - -#define EIFR _SFR_IO8(0x1C) -#define INTF2 2 -#define INTF1 1 -#define INTF0 0 - -#define EIMSK _SFR_IO8(0x1D) -#define INT2 2 -#define INT1 1 -#define INT0 0 - -#define GPIOR0 _SFR_IO8(0x1E) - -#define EECR _SFR_IO8(0x1F) -/* EECR - EEPROM Control Register */ -#define EEPM1 5 -#define EEPM0 4 -#define EERIE 3 -#define EEMPE 2 -#define EEPE 1 -#define EERE 0 - -#define EEDR _SFR_IO8(0X20) - -/* Combine EEARL and EEARH */ -#define EEAR _SFR_IO16(0x21) -#define EEARL _SFR_IO8(0x21) -#define EEARH _SFR_IO8(0X22) - -/* 6-char sequence denoting where to find the EEPROM registers in memory space. - Adresses denoted in hex syntax with uppercase letters. Used by the EEPROM - subroutines. - First two letters: EECR address. - Second two letters: EEDR address. - Last two letters: EEAR address. */ -#define __EEPROM_REG_LOCATIONS__ 1F2021 - -#define GTCCR _SFR_IO8(0x23) -#define TSM 7 -#define PSRASY 1 -#define PSRSYNC 0 - -#define TCCR0A _SFR_IO8(0x24) -#define COM0A1 7 -#define COM0A0 6 -#define COM0B1 5 -#define COM0B0 4 -#define WGM01 1 -#define WGM00 0 - -#define TCCR0B _SFR_IO8(0x25) -#define FOC0A 7 -#define FOC0B 6 -#define WGM02 3 -#define CS02 2 -#define CS01 1 -#define CS00 0 - -#define TCNT0 _SFR_IO8(0X26) - -#define OCR0A _SFR_IO8(0X27) - -#define OCR0B _SFR_IO8(0X28) - -/* Reserved [0x29] */ - -#define GPIOR1 _SFR_IO8(0x2A) - -#define GPIOR2 _SFR_IO8(0x2B) - -#define SPCR _SFR_IO8(0x2C) -#define SPIE 7 -#define SPE 6 -#define DORD 5 -#define MSTR 4 -#define CPOL 3 -#define CPHA 2 -#define SPR1 1 -#define SPR0 0 - -#define SPSR _SFR_IO8(0x2D) -#define SPIF 7 -#define WCOL 6 -#define SPI2X 0 - -#define SPDR _SFR_IO8(0x2E) - -/* Reserved [0x2F] */ - -#define ACSR _SFR_IO8(0x30) -#define ACD 7 -#define ACBG 6 -#define ACO 5 -#define ACI 4 -#define ACIE 3 -#define ACIC 2 -#define ACIS1 1 -#define ACIS0 0 - -#define MONDR _SFR_IO8(0x31) -#define OCDR _SFR_IO8(0x31) -#define IDRD 7 -#define OCDR7 7 -#define OCDR6 6 -#define OCDR5 5 -#define OCDR4 4 -#define OCDR3 3 -#define OCDR2 2 -#define OCDR1 1 -#define OCDR0 0 - -/* Reserved [0x32] */ - -#define SMCR _SFR_IO8(0x33) -#define SM2 3 -#define SM1 2 -#define SM0 1 -#define SE 0 - -#define MCUSR _SFR_IO8(0x34) -#define JTRF 4 -#define WDRF 3 -#define BORF 2 -#define EXTRF 1 -#define PORF 0 - -#define MCUCR _SFR_IO8(0X35) -#define JTD 7 -#if !defined(__AVR_ATmega644__) -#define BODS 6 -#define BODSE 5 -#endif -#define PUD 4 -#define IVSEL 1 -#define IVCE 0 - -/* Reserved [0x36] */ - -#define SPMCSR _SFR_IO8(0x37) -#define SPMIE 7 -#define RWWSB 6 -#define SIGRD 5 -#define RWWSRE 4 -#define BLBSET 3 -#define PGWRT 2 -#define PGERS 1 -#define SPMEN 0 - -/* Reserved [0x38..0x3C] */ - -/* SP [0x3D..0x3E] */ -/* SREG [0x3F] */ - -#define WDTCSR _SFR_MEM8(0x60) -#define WDIF 7 -#define WDIE 6 -#define WDP3 5 -#define WDCE 4 -#define WDE 3 -#define WDP2 2 -#define WDP1 1 -#define WDP0 0 - -#define CLKPR _SFR_MEM8(0x61) -#define CLKPCE 7 -#define CLKPS3 3 -#define CLKPS2 2 -#define CLKPS1 1 -#define CLKPS0 0 - -/* Reserved [0x62..0x63] */ - -#define PRR _SFR_MEM8(0x64) /* Datasheets: ATmega164P/324P/644P 8011D�AVR�02/07 - and ATmega644 2593L�AVR�02/07. */ -#define PRR0 _SFR_MEM8(0x64) /* AVR Studio 4.13, build 524. */ -#define PRTWI 7 -#define PRTIM2 6 -#define PRTIM0 5 -#if !defined(__AVR_ATmega644__) -# define PRUSART1 4 -#endif -#define PRTIM1 3 -#define PRSPI 2 -#define PRUSART0 1 -#define PRADC 0 - -#if !defined(__AVR_ATmega644__) -#define __AVR_HAVE_PRR0 ((1<, never directly. */ - -#ifndef _AVR_IO_H_ -# error "Include instead of this file." -#endif - -#ifndef _AVR_IOXXX_H_ -# define _AVR_IOXXX_H_ "iomxxhva.h" -#else -# error "Attempt to include more than one file." -#endif - -/* Registers and associated bit numbers */ - -#define PINA _SFR_IO8(0X00) -#define PINA1 1 -#define PINA0 0 - -#define DDRA _SFR_IO8(0x01) -#define DDA1 1 -#define DDA0 0 - -#define PORTA _SFR_IO8(0x02) -#define PA1 1 -#define PA0 0 - -#define PINB _SFR_IO8(0X03) -#define PINB3 3 -#define PINB2 2 -#define PINB1 1 -#define PINB0 0 - -#define DDRB _SFR_IO8(0x04) -#define DDB3 3 -#define DDB2 2 -#define DDB1 1 -#define DDB0 0 - -#define PORTB _SFR_IO8(0x05) -#define PB3 3 -#define PB2 2 -#define PB1 1 -#define PB0 0 - -#define PINC _SFR_IO8(0x06) -#define PINC0 0 - -/* Reserved [0x7] */ - -#define PORTC _SFR_IO8(0x08) -#define PC0 0 - -/* Reserved [0x9..0x14] */ - -#define TIFR0 _SFR_IO8(0x15) -#define ICF0 3 -#define OCF0B 2 -#define OCF0A 1 -#define TOV0 0 - -#define TIFR1 _SFR_IO8(0x16) -#define ICF1 3 -#define OCF1B 2 -#define OCF1A 1 -#define TOV1 0 - -#define OSICSR _SFR_IO8(0x17) -#define OSISEL0 4 -#define OSIST 1 -#define OSIEN 0 - -/* Reserved [0x18..0x1B] */ - -#define EIFR _SFR_IO8(0x1C) -#define INTF2 2 -#define INTF1 1 -#define INTF0 0 - -#define EIMSK _SFR_IO8(0x1D) -#define INT2 2 -#define INT1 1 -#define INT0 0 - -#define GPIOR0 _SFR_IO8(0x1E) - -#define EECR _SFR_IO8(0x1F) -#define EEPM1 5 -#define EEPM0 4 -#define EERIE 3 -#define EEMPE 2 -#define EEPE 1 -#define EERE 0 - -#define EEDR _SFR_IO8(0x20) - -#define EEAR _SFR_IO8(0x21) -#define EEARL _SFR_IO8(0x21) - -/* 6-char sequence denoting where to find the EEPROM registers in memory space. - Adresses denoted in hex syntax with uppercase letters. Used by the EEPROM - subroutines. - First two letters: EECR address. - Second two letters: EEDR address. - Last two letters: EEAR address. */ -#define __EEPROM_REG_LOCATIONS__ 1F2021 - -/* Reserved [0x22] */ - -#define GTCCR _SFR_IO8(0x23) -#define TSM 7 -#define PSRSYNC 0 - -#define TCCR0A _SFR_IO8(0x24) -#define TCW0 7 -#define ICEN0 6 -#define ICNC0 5 -#define ICES0 4 -#define ICS0 3 -#define WGM00 0 - -#define TCCR0B _SFR_IO8(0x25) -#define CS02 2 -#define CS01 1 -#define CS00 0 - -#define TCNT0 _SFR_IO16(0X26) -#define TCNT0L _SFR_IO8(0X26) -#define TCNT0H _SFR_IO8(0X27) - -#define OCR0A _SFR_IO8(0x28) - -#define OCR0B _SFR_IO8(0X29) - -#define GPIOR1 _SFR_IO8(0x2A) - -#define GPIOR2 _SFR_IO8(0x2B) - -#define SPCR _SFR_IO8(0x2C) -#define SPIE 7 -#define SPE 6 -#define DORD 5 -#define MSTR 4 -#define CPOL 3 -#define CPHA 2 -#define SPR1 1 -#define SPR0 0 - -#define SPSR _SFR_IO8(0x2D) -#define SPIF 7 -#define WCOL 6 -#define SPI2X 0 - -#define SPDR _SFR_IO8(0x2E) - -/* Reserved [0x2F..0x30] */ - -#define DWDR _SFR_IO8(0x31) -#define IDRD 7 - -/* Reserved [0x32] */ - -#define SMCR _SFR_IO8(0x33) -#define SM2 3 -#define SM1 2 -#define SM0 1 -#define SE 0 - -#define MCUSR _SFR_IO8(0x34) -#define OCDRF 4 -#define WDRF 3 -#define BORF 2 -#define EXTRF 1 -#define PORF 0 - -#define MCUCR _SFR_IO8(0x35) -#define CKOE 5 -#define PUD 4 - -/* Reserved [0x36] */ - -#define SPMCSR _SFR_IO8(0x37) -#define SIGRD 5 -#define CTPB 4 -#define RFLB 3 -#define PGWRT 2 -#define PGERS 1 -#define SPMEN 0 - -/* Reserved [0x38..0x3C] */ - -/* SP [0x3D..0x3E] */ -/* SREG [0x3F] */ - -#define WDTCSR _SFR_MEM8(0x60) -#define WDIF 7 -#define WDIE 6 -#define WDP3 5 -#define WDCE 4 -#define WDE 3 -#define WDP2 2 -#define WDP1 1 -#define WDP0 0 - -#define CLKPR _SFR_MEM8(0x61) -#define CLKPCE 7 -#define CLKPS1 1 -#define CLKPS0 0 - -/* Reserved [0x62..0x63] */ - -#define PRR0 _SFR_MEM8(0x64) -#define PRVRM 5 -#define PRSPI 3 -#define PRTIM1 2 -#define PRTIM0 1 -#define PRVADC 0 - -#define __AVR_HAVE_PRR0 ((1<, never directly. */ - -#ifndef _AVR_IO_H_ -# error "Include instead of this file." -#endif - -#ifndef _AVR_IOXXX_H_ -# define _AVR_IOXXX_H_ "iotn10.h" -#else -# error "Attempt to include more than one file." -#endif - - -#ifndef _AVR_ATtiny10_H_ -#define _AVR_ATtiny10_H_ 1 - - -/* Registers and associated bit numbers. */ - -#define PINB _SFR_IO8(0x00) -#define PINB0 0 -#define PINB1 1 -#define PINB2 2 -#define PINB3 3 - -#define DDRB _SFR_IO8(0x01) -#define DDB0 0 -#define DDB1 1 -#define DDB2 2 -#define DDB3 3 - -#define PORTB _SFR_IO8(0x02) -#define PORTB0 0 -#define PORTB1 1 -#define PORTB2 2 -#define PORTB3 3 - -#define PUEB _SFR_IO8(0x03) -#define PUEB0 0 -#define PUEB1 1 -#define PUEB2 2 -#define PUEB3 3 - -#define PORTCR _SFR_IO8(0x0C) -#define BBMB 1 - -#define PCMSK _SFR_IO8(0x10) -#define PCINT0 0 -#define PCINT1 1 -#define PCINT2 2 -#define PCINT3 3 - -#define PCIFR _SFR_IO8(0x11) -#define PCIF0 0 - -#define PCICR _SFR_IO8(0x12) -#define PCIE0 0 - -#define EIMSK _SFR_IO8(0x13) -#define INT0 0 - -#define EIFR _SFR_IO8(0x14) -#define INTF0 0 - -#define EICRA _SFR_IO8(0x15) -#define ISC00 0 -#define ISC01 1 - -#define DIDR0 _SFR_IO8(0x17) -#define ADC0D 0 -#define AIN0D 0 -#define ADC1D 1 -#define AIN1D 1 -#define ADC2D 2 -#define ADC3D 3 - -#define ADCL _SFR_IO8(0x19) -#define ADC0 0 -#define ADC1 1 -#define ADC2 2 -#define ADC3 3 -#define ADC4 4 -#define ADC5 5 -#define ADC6 6 -#define ADC7 7 - -#define ADMUX _SFR_IO8(0x1B) -#define MUX0 0 -#define MUX1 1 - -#define ADCSRB _SFR_IO8(0x1C) -#define ADTS0 0 -#define ADTS1 1 -#define ADTS2 2 - -#define ADCSRA _SFR_IO8(0x1D) -#define ADPS0 0 -#define ADPS1 1 -#define ADPS2 2 -#define ADIE 3 -#define ADIF 4 -#define ADATE 5 -#define ADSC 6 -#define ADEN 7 - -#define ACSR _SFR_IO8(0x1F) -#define ACIS0 0 -#define ACIS1 1 -#define ACIC 2 -#define ACIE 3 -#define ACI 4 -#define ACO 5 -#define ACD 7 - -#define ICR0 _SFR_IO16(0x22) - -#define ICR0L _SFR_IO8(0x22) -#define ICR0_0 0 -#define ICR0_1 1 -#define ICR0_2 2 -#define ICR0_3 3 -#define ICR0_4 4 -#define ICR0_5 5 -#define ICR0_6 6 -#define ICR0_7 7 - -#define ICR0H _SFR_IO8(0x23) -#define ICR0_8 0 -#define ICR0_9 1 -#define ICR0_10 2 -#define ICR0_11 3 -#define ICR0_12 4 -#define ICR0_13 5 -#define ICR0_14 6 -#define ICR0_15 7 - -#define OCR0B _SFR_IO16(0x24) - -#define OCR0BL _SFR_IO8(0x24) -#define OCR0B0 0 -#define OCR0B1 1 -#define OCR0B2 2 -#define OCR0B3 3 -#define OCR0B4 4 -#define OCR0B5 5 -#define OCR0B6 6 -#define OCR0B7 7 - -#define OCR0BH _SFR_IO8(0x25) -#define OCR0B8 0 -#define OCR0B9 1 -#define OCR0B10 2 -#define OCR0B11 3 -#define OCR0B12 4 -#define OCR0B13 5 -#define OCR0B14 6 -#define OCR0B15 7 - -#define OCR0A _SFR_IO16(0x26) - -#define OCR0AL _SFR_IO8(0x26) -#define OCR0A0 0 -#define OCR0A1 1 -#define OCR0A2 2 -#define OCR0A3 3 -#define OCR0A4 4 -#define OCR0A5 5 -#define OCR0A6 6 -#define OCR0A7 7 - -#define OCR0AH _SFR_IO8(0x27) -#define OCR0A8 0 -#define OCR0A9 1 -#define OCR0A10 2 -#define OCR0A11 3 -#define OCR0A12 4 -#define OCR0A13 5 -#define OCR0A14 6 -#define OCR0A15 7 - -#define TCNT0 _SFR_IO16(0x28) - -#define TCNT0L _SFR_IO8(0x28) -#define TCNT0_0 0 -#define TCNT0_1 1 -#define TCNT0_2 2 -#define TCNT0_3 3 -#define TCNT0_4 4 -#define TCNT0_5 5 -#define TCNT0_6 6 -#define TCNT0_7 7 - -#define TCNT0H _SFR_IO8(0x29) -#define TCNT0_8 0 -#define TCNT0_9 1 -#define TCNT0_10 2 -#define TCNT0_11 3 -#define TCNT0_12 4 -#define TCNT0_13 5 -#define TCNT0_14 6 -#define TCNT0_15 7 - -#define TIFR0 _SFR_IO8(0x2A) -#define TOV0 0 -#define OCF0A 1 -#define OCF0B 2 -#define ICF0 5 - -#define TIMSK0 _SFR_IO8(0x2B) -#define TOIE0 0 -#define OCIE0A 1 -#define OCIE0B 2 -#define ICIE0 5 - -#define TCCR0C _SFR_IO8(0x2C) -#define FOC0B 6 -#define FOC0A 7 - -#define TCCR0B _SFR_IO8(0x2D) -#define CS00 0 -#define CS01 1 -#define CS02 2 -#define WGM02 3 -#define WGM03 4 -#define ICES0 6 -#define ICNC0 7 - -#define TCCR0A _SFR_IO8(0x2E) -#define WGM00 0 -#define WGM01 1 -#define COM0B0 4 -#define COM0B1 5 -#define COM0A0 6 -#define COM0A1 7 - -#define GTCCR _SFR_IO8(0x2F) -#define PSR 0 -#define TSM 7 - -#define WDTCSR _SFR_IO8(0x31) -#define WDP0 0 -#define WDP1 1 -#define WDP2 2 -#define WDE 3 -#define WDP3 5 -#define WDIE 6 -#define WDIF 7 - -#define NVMCSR _SFR_IO8(0x32) -#define NVMBSY 7 - -#define NVMCMD _SFR_IO8(0x33) -#define NVMCMD0 0 -#define NVMCMD1 1 -#define NVMCMD2 2 -#define NVMCMD3 3 -#define NVMCMD4 4 -#define NVMCMD5 5 - -#define VLMCSR _SFR_IO8(0x34) -#define VLM0 0 -#define VLM1 1 -#define VLM2 2 -#define VLMIE 6 -#define VLMF 7 - -#define PRR _SFR_IO8(0x35) -#define PRTIM0 0 -#define PRADC 1 - -#define __AVR_HAVE_PRR ((1<, never directly. */ - -#ifndef _AVR_IO_H_ -# error "Include instead of this file." -#endif - -#ifndef _AVR_IOXXX_H_ -# define _AVR_IOXXX_H_ "iotn11.h" -#else -# error "Attempt to include more than one file." -#endif - -#ifndef __ASSEMBLER__ -# warning "MCU not supported by the C compiler" -#endif - -/* I/O registers */ - -/* 0x00..0x07 reserved */ - -/* Analog Comparator Control and Status Register */ -#define ACSR _SFR_IO8(0x08) - -/* 0x09..0x15 reserved */ - -/* Input Pins, Port B */ -#define PINB _SFR_IO8(0x16) - -/* Data Direction Register, Port B */ -#define DDRB _SFR_IO8(0x17) - -/* Data Register, Port B */ -#define PORTB _SFR_IO8(0x18) - -/* 0x19..0x20 reserved */ - -/* Watchdog Timer Control Register */ -#define WDTCR _SFR_IO8(0x21) - -/* 0x22..0x31 reserved */ - -/* Timer/Counter0 (8-bit) */ -#define TCNT0 _SFR_IO8(0x32) - -/* Timer/Counter0 Control Register */ -#define TCCR0 _SFR_IO8(0x33) - -/* MCU general Status Register */ -#define MCUSR _SFR_IO8(0x34) - -/* MCU general Control Register */ -#define MCUCR _SFR_IO8(0x35) - -/* 0x36..0x37 reserved */ - -/* Timer/Counter Interrupt Flag Register */ -#define TIFR _SFR_IO8(0x38) - -/* Timer/Counter Interrupt MaSK Register */ -#define TIMSK _SFR_IO8(0x39) - -/* General Interrupt Flag Register */ -#define GIFR _SFR_IO8(0x3A) - -/* General Interrupt MaSK register */ -#define GIMSK _SFR_IO8(0x3B) - -/* 0x3C..0x3E reserved */ - -/* 0x3F SREG */ - -/* Interrupt vectors */ - -/* External Interrupt 0 */ -#define INT0_vect_num 1 -#define INT0_vect _VECTOR(1) -#define SIG_INTERRUPT0 _VECTOR(1) - -/* External Interrupt Request 0 */ -#define IO_PINS_vect_num 2 -#define IO_PINS_vect _VECTOR(2) -#define SIG_PIN _VECTOR(2) -#define SIG_PIN_CHANGE _VECTOR(2) - -/* Timer/Counter0 Overflow */ -#define TIMER0_OVF_vect_num 3 -#define TIMER0_OVF_vect _VECTOR(3) -#define SIG_OVERFLOW0 _VECTOR(3) - -/* Analog Comparator */ -#define ANA_COMP_vect_num 4 -#define ANA_COMP_vect _VECTOR(4) -#define SIG_COMPARATOR _VECTOR(4) - -#define _VECTORS_SIZE 10 - -/* Bit numbers */ - -/* GIMSK */ -#define INT0 6 -#define PCIE 5 - -/* GIFR */ -#define INTF0 6 -#define PCIF 5 - -/* TIMSK */ -#define TOIE0 1 - -/* TIFR */ -#define TOV0 1 - -/* MCUCR */ -#define SE 5 -#define SM 4 -#define ISC01 1 -#define ISC00 0 - -/* TCCR0 */ -#define CS02 2 -#define CS01 1 -#define CS00 0 - -/* WDTCR */ -#define WDTOE 4 -#define WDE 3 -#define WDP2 2 -#define WDP1 1 -#define WDP0 0 - -/* - PB5 = RESET# - PB4 = XTAL2 - PB3 = XTAL1 - PB2 = T0 - PB1 = INT0 / AIN1 - PB0 = AIN0 - */ - -/* PORTB */ -#define PB4 4 -#define PB3 3 -#define PB2 2 -#define PB1 1 -#define PB0 0 - -/* DDRB */ -#define DDB4 4 -#define DDB3 3 -#define DDB2 2 -#define DDB1 1 -#define DDB0 0 - -/* PINB */ -#define PINB5 5 -#define PINB4 4 -#define PINB3 3 -#define PINB2 2 -#define PINB1 1 -#define PINB0 0 - -/* ACSR */ -#define ACD 7 -#define ACO 5 -#define ACI 4 -#define ACIE 3 -#define ACIS1 1 -#define ACIS0 0 - -#define RAMSTART 0x60 -/* Last memory addresses */ -#define RAMEND 0x1F -#define XRAMEND 0x0 -#define E2END 0x0 -#define E2PAGESIZE 2 -#define FLASHEND 0x3FF - - -/* Fuses */ - -#define FUSE_MEMORY_SIZE 1 - -/* Low Fuse Byte */ -#define FUSE_CKSEL0 (unsigned char)~_BV(0) -#define FUSE_CKSEL1 (unsigned char)~_BV(1) -#define FUSE_CKSEL2 (unsigned char)~_BV(2) -#define FUSE_RSTDISBL (unsigned char)~_BV(3) -#define FUSE_FSTRT (unsigned char)~_BV(4) -#define FUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL1) - - -/* Lock Bits */ -#define __LOCK_BITS_EXIST - - -/* Signature */ -#define SIGNATURE_0 0x1E -#define SIGNATURE_1 0x90 -#define SIGNATURE_2 0x04 - - -/* Deprecated items */ -#if !defined(__AVR_LIBC_DEPRECATED_ENABLE__) - -#pragma GCC system_header - -#pragma GCC poison SIG_INTERRUPT0 -#pragma GCC poison SIG_PIN -#pragma GCC poison SIG_PIN_CHANGE -#pragma GCC poison SIG_OVERFLOW0 -#pragma GCC poison SIG_COMPARATOR - -#endif /* !defined(__AVR_LIBC_DEPRECATED_ENABLE__) */ - -#define SLEEP_MODE_IDLE (0x00<<4) -#define SLEEP_MODE_PWR_DOWN (0x01<<4) - -#endif /* _AVR_IOTN11_H_ */ diff --git a/arduino/hardware/tools/avr/avr/include/avr/iotn12.h b/arduino/hardware/tools/avr/avr/include/avr/iotn12.h deleted file mode 100644 index cba6c3e..0000000 --- a/arduino/hardware/tools/avr/avr/include/avr/iotn12.h +++ /dev/null @@ -1,288 +0,0 @@ -/* Copyright (c) 2002,2005 Marek Michalkiewicz - All rights reserved. - - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - * Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - * Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in - the documentation and/or other materials provided with the - distribution. - - * Neither the name of the copyright holders nor the names of - contributors may be used to endorse or promote products derived - from this software without specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. */ - -/* $Id: iotn12.h 2236 2011-03-17 21:53:39Z arcanum $ */ - -/* avr/iotn12.h - definitions for ATtiny12 */ - -#ifndef _AVR_IOTN12_H_ -#define _AVR_IOTN12_H_ 1 - -/* This file should only be included from , never directly. */ - -#ifndef _AVR_IO_H_ -# error "Include instead of this file." -#endif - -#ifndef _AVR_IOXXX_H_ -# define _AVR_IOXXX_H_ "iotn12.h" -#else -# error "Attempt to include more than one file." -#endif - -#ifndef __ASSEMBLER__ -# warning "MCU not supported by the C compiler" -#endif - -/* I/O registers */ - -/* 0x00..0x07 reserved */ - -/* Analog Comparator Control and Status Register */ -#define ACSR _SFR_IO8(0x08) - -/* 0x09..0x15 reserved */ - -/* Input Pins, Port B */ -#define PINB _SFR_IO8(0x16) - -/* Data Direction Register, Port B */ -#define DDRB _SFR_IO8(0x17) - -/* Data Register, Port B */ -#define PORTB _SFR_IO8(0x18) - -/* 0x19..0x1B reserved */ - -/* EEPROM Control Register */ -#define EECR _SFR_IO8(0x1C) - -/* EEPROM Data Register */ -#define EEDR _SFR_IO8(0x1D) - -/* EEPROM Address Register */ -#define EEAR _SFR_IO8(0x1E) -#define EEARL _SFR_IO8(0x1E) - -/* 0x1F..0x20 reserved */ - -/* Watchdog Timer Control Register */ -#define WDTCR _SFR_IO8(0x21) - -/* 0x22..0x30 reserved */ - -/* Oscillator Calibration Register */ -#define OSCCAL _SFR_IO8(0x31) - -/* Timer/Counter0 (8-bit) */ -#define TCNT0 _SFR_IO8(0x32) - -/* Timer/Counter0 Control Register */ -#define TCCR0 _SFR_IO8(0x33) - -/* MCU general Status Register */ -#define MCUSR _SFR_IO8(0x34) - -/* MCU general Control Register */ -#define MCUCR _SFR_IO8(0x35) - -/* 0x36..0x37 reserved */ - -/* Timer/Counter Interrupt Flag Register */ -#define TIFR _SFR_IO8(0x38) - -/* Timer/Counter Interrupt MaSK Register */ -#define TIMSK _SFR_IO8(0x39) - -/* General Interrupt Flag Register */ -#define GIFR _SFR_IO8(0x3A) - -/* General Interrupt MaSK register */ -#define GIMSK _SFR_IO8(0x3B) - -/* 0x3C..0x3E reserved */ - -/* 0x3F SREG */ - -/* Interrupt vectors */ - -/* External Interrupt 0 */ -#define INT0_vect_num 1 -#define INT0_vect _VECTOR(1) -#define SIG_INTERRUPT0 _VECTOR(1) - -/* External Interrupt Request 0 */ -#define IO_PINS_vect_num 2 -#define IO_PINS_vect _VECTOR(2) -#define SIG_PIN _VECTOR(2) -#define SIG_PIN_CHANGE _VECTOR(2) - -/* Timer/Counter0 Overflow */ -#define TIMER0_OVF_vect_num 3 -#define TIMER0_OVF_vect _VECTOR(3) -#define SIG_OVERFLOW0 _VECTOR(3) - -/* EEPROM Ready */ -#define EE_RDY_vect_num 4 -#define EE_RDY_vect _VECTOR(4) -#define SIG_EEPROM_READY _VECTOR(4) - -/* Analog Comparator */ -#define ANA_COMP_vect_num 5 -#define ANA_COMP_vect _VECTOR(5) -#define SIG_COMPARATOR _VECTOR(5) - -#define _VECTORS_SIZE 12 - -/* Bit numbers */ - -/* GIMSK */ -#define INT0 6 -#define PCIE 5 - -/* GIFR */ -#define INTF0 6 -#define PCIF 5 - -/* TIMSK */ -#define TOIE0 1 - -/* TIFR */ -#define TOV0 1 - -/* MCUCR */ -#define PUD 6 -#define SE 5 -#define SM 4 -#define ISC01 1 -#define ISC00 0 - -/* TCCR0 */ -#define CS02 2 -#define CS01 1 -#define CS00 0 - -/* WDTCR */ -#define WDTOE 4 -#define WDE 3 -#define WDP2 2 -#define WDP1 1 -#define WDP0 0 - -/* - PB5 = RESET# - PB4 = XTAL2 - PB3 = XTAL1 - PB2 = T0 / SCK - PB1 = INT0 / AIN1 / MISO - PB0 = AIN0 / MOSI - */ - -/* PORTB */ -#define PB4 4 -#define PB3 3 -#define PB2 2 -#define PB1 1 -#define PB0 0 - -/* DDRB */ -#define DDB5 5 -#define DDB4 4 -#define DDB3 3 -#define DDB2 2 -#define DDB1 1 -#define DDB0 0 - -/* PINB */ -#define PINB5 5 -#define PINB4 4 -#define PINB3 3 -#define PINB2 2 -#define PINB1 1 -#define PINB0 0 - -/* ACSR */ -#define ACD 7 -#define AINBG 6 -#define ACO 5 -#define ACI 4 -#define ACIE 3 -#define ACIS1 1 -#define ACIS0 0 - -/* EEPROM Control Register */ -#define EERIE 3 -#define EEMWE 2 -#define EEWE 1 -#define EERE 0 - -#define RAMSTART 0x60 -/* Last memory addresses */ -#define RAMEND 0x1F -#define XRAMEND 0x0 -#define E2END 0x3F -#define E2PAGESIZE 2 -#define FLASHEND 0x3FF - - -/* Fuses */ - -#define FUSE_MEMORY_SIZE 1 - -/* Low Fuse Byte */ -#define FUSE_CKSEL0 (unsigned char)~_BV(0) -#define FUSE_CKSEL1 (unsigned char)~_BV(1) -#define FUSE_CKSEL2 (unsigned char)~_BV(2) -#define FUSE_CKSEL3 (unsigned char)~_BV(3) -#define FUSE_RSTDISBL (unsigned char)~_BV(4) -#define FUSE_SPIEN (unsigned char)~_BV(5) -#define FUSE_BODEN (unsigned char)~_BV(6) -#define FUSE_BODLEVEL (unsigned char)~_BV(7) -#define FUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SPIEN & FUSE_BODLEVEL) - - -/* Lock Bits */ -#define __LOCK_BITS_EXIST - - -/* Signature */ -#define SIGNATURE_0 0x1E -#define SIGNATURE_1 0x90 -#define SIGNATURE_2 0x05 - - -/* Deprecated items */ -#if !defined(__AVR_LIBC_DEPRECATED_ENABLE__) - -#pragma GCC system_header - -#pragma GCC poison SIG_INTERRUPT0 -#pragma GCC poison SIG_PIN -#pragma GCC poison SIG_PIN_CHANGE -#pragma GCC poison SIG_OVERFLOW0 -#pragma GCC poison SIG_EEPROM_READY -#pragma GCC poison SIG_COMPARATOR - -#endif /* !defined(__AVR_LIBC_DEPRECATED_ENABLE__) */ - -#define SLEEP_MODE_IDLE (0x00<<4) -#define SLEEP_MODE_PWR_DOWN (0x01<<4) - -#endif /* _AVR_IOTN12_H_ */ diff --git a/arduino/hardware/tools/avr/avr/include/avr/iotn13.h b/arduino/hardware/tools/avr/avr/include/avr/iotn13.h deleted file mode 100644 index 4e57500..0000000 --- a/arduino/hardware/tools/avr/avr/include/avr/iotn13.h +++ /dev/null @@ -1,395 +0,0 @@ -/* Copyright (c) 2004, Theodore A. Roth - All rights reserved. - - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - * Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - * Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in - the documentation and/or other materials provided with the - distribution. - - * Neither the name of the copyright holders nor the names of - contributors may be used to endorse or promote products derived - from this software without specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. */ - -/* $Id: iotn13.h 2236 2011-03-17 21:53:39Z arcanum $ */ - -/* avr/iotn13.h - definitions for ATtiny13 */ - -/* Verified 5/20/04 by Bruce Graham */ - -#ifndef _AVR_IOTN13_H_ -#define _AVR_IOTN13_H_ 1 - -/* This file should only be included from , never directly. */ - -#ifndef _AVR_IO_H_ -# error "Include instead of this file." -#endif - -#ifndef _AVR_IOXXX_H_ -# define _AVR_IOXXX_H_ "iotn13.h" -#else -# error "Attempt to include more than one file." -#endif - -/* I/O registers and bit names */ - -/* ADC Control and Status Register B */ -#define ADCSRB _SFR_IO8(0x03) -# define ACME 6 -# define ADTS2 2 -# define ADTS1 1 -# define ADTS0 0 - -/* ADC Data Register */ -#ifndef __ASSEMBLER__ -#define ADC _SFR_IO16 (0x04) -#endif -#define ADCW _SFR_IO16 (0x04) -#define ADCL _SFR_IO8(0x04) -#define ADCH _SFR_IO8(0x05) - -/* ADC Control and Status Register A */ -#define ADCSRA _SFR_IO8(0x06) -# define ADEN 7 -# define ADSC 6 -# define ADATE 5 -# define ADIF 4 -# define ADIE 3 -# define ADPS2 2 -# define ADPS1 1 -# define ADPS0 0 - -/* ADC Multiplex Selection Register */ -#define ADMUX _SFR_IO8(0x07) -# define REFS0 6 -# define ADLAR 5 -# define MUX1 1 -# define MUX0 0 - -/* Analog Comparator Control and Status Register */ -#define ACSR _SFR_IO8(0x08) -# define ACD 7 -# define ACBG 6 -# define ACO 5 -# define ACI 4 -# define ACIE 3 -# define ACIS1 1 -# define ACIS0 0 - -/* Digital Input Disable Register 0 */ -#define DIDR0 _SFR_IO8(0x14) -# define ADC0D 5 -# define ADC2D 4 -# define ADC3D 3 -# define ADC1D 2 -# define AIN1D 1 -# define AIN0D 0 - -/* PIN Change Mask Register */ -#define PCMSK _SFR_IO8(0x15) -# define PCINT5 5 -# define PCINT4 4 -# define PCINT3 3 -# define PCINT2 2 -# define PCINT1 1 -# define PCINT0 0 - -/* Port B Pin Utilization [2535D-AVR-04/04] - - PORTB5 = PCINT5/RESET#/ADC0/dW - - PORTB4 = PCINT4/ADC2 - - PORTB3 = PCINT3/CLKI/ADC3 - - PORTB2 = SCK/ADC1/T0/PCINT2 - - PORTB1 = MISO/AIN1/OC0B/INT0/PCINT1 - - PORTB0 = MOSI/AIN0/OC0A/PCINT0 */ - -/* Input Pins, Port B */ -#define PINB _SFR_IO8(0x16) -# define PINB5 5 -# define PINB4 4 -# define PINB3 3 -# define PINB2 2 -# define PINB1 1 -# define PINB0 0 - -/* Data Direction Register, Port B */ -#define DDRB _SFR_IO8(0x17) -# define DDB5 5 -# define DDB4 4 -# define DDB3 3 -# define DDB2 2 -# define DDB1 1 -# define DDB0 0 - -/* Data Register, Port B */ -#define PORTB _SFR_IO8(0x18) -# define PB5 5 -# define PB4 4 -# define PB3 3 -# define PB2 2 -# define PB1 1 -# define PB0 0 - -/* ATtiny EEPROM Control Register EECR */ -#define EECR _SFR_IO8(0x1C) -#define EEPM1 5 -#define EEPM0 4 -#define EERIE 3 -#define EEMPE 2 -#define EEPE 1 -#define EERE 0 - -/* EEPROM Data Register */ -#define EEDR _SFR_IO8(0x1D) - -/* The EEPROM Address Register EEAR[6:0] */ -#define EEAR _SFR_IO8(0x1E) -#define EEARL _SFR_IO8(0x1E) - -/* Watchdog Timer Control Register */ -#define WDTCR _SFR_IO8(0x21) -# define WDTIF 7 -# define WDTIE 6 -# define WDP3 5 -# define WDCE 4 -# define WDE 3 -# define WDP2 2 -# define WDP1 1 -# define WDP0 0 - -/* Clock Prescale Register */ -#define CLKPR _SFR_IO8(0x26) -# define CLKPCE 7 -# define CLKPS3 3 -# define CLKPS2 2 -# define CLKPS1 1 -# define CLKPS0 0 - -/* General Timer/Counter Control Register */ -#define GTCCR _SFR_IO8(0x28) -# define TSM 7 -# define PSR10 0 - -/* Output Compare 0 Register B */ -#define OCR0B _SFR_IO8(0x29) - -/* debugWIRE Data Register */ -#define DWDR _SFR_IO8(0x2e) - -/* Timer/Counter 0 Control Register A */ -#define TCCR0A _SFR_IO8(0x2f) -# define COM0A1 7 -# define COM0A0 6 -# define COM0B1 5 -# define COM0B0 4 -# define WGM01 1 -# define WGM00 0 - -/* Oscillator Calibration Register */ -#define OSCCAL _SFR_IO8(0x31) - -/* Timer/Counter0 (8-bit) */ -#define TCNT0 _SFR_IO8(0x32) - -/* Timer/Counter 0 Control Register B */ -#define TCCR0B _SFR_IO8(0x33) -# define FOC0A 7 -# define FOC0B 6 -# define WGM02 3 -# define CS02 2 -# define CS01 1 -# define CS00 0 - -/* MCU General Status Register */ -#define MCUSR _SFR_IO8(0x34) -# define WDRF 3 -# define BORF 2 -# define EXTRF 1 -# define PORF 0 - -/* MCU General Control Register */ -#define MCUCR _SFR_IO8(0x35) -# define PUD 6 -# define SE 5 -# define SM1 4 -# define SM0 3 -# define ISC01 1 -# define ISC00 0 - -/* Output Compare 0 REgister A */ -#define OCR0A _SFR_IO8(0x36) - -/* Store Program Memory Control and Status Register */ -#define SPMCSR _SFR_IO8(0x37) -# define CTPB 4 -# define RFLB 3 -# define PGWRT 2 -# define PGERS 1 -# define SPMEN 0 -# define SELFPRGEN 0 - -/* Timer/Counter 0 Interrupt Flag Register */ -#define TIFR0 _SFR_IO8(0x38) -# define OCF0B 3 -# define OCF0A 2 -# define TOV0 1 - -/* Timer/Counter 0 Interrupt MaSK Register */ -#define TIMSK0 _SFR_IO8(0x39) -# define OCIE0B 3 -# define OCIE0A 2 -# define TOIE0 1 - -/* General Interrupt Flag Register */ -#define GIFR _SFR_IO8(0x3a) -# define INTF0 6 -# define PCIF 5 - -/* General Interrupt MaSK register */ -#define GIMSK _SFR_IO8(0x3b) -# define INT0 6 -# define PCIE 5 - -/* SPL and SREG are defined in */ - -/* From the datasheet: - 1 0x0000 RESET External Pin, Power-on Reset, Brown-out Reset, Watchdog Reset - 2 0x0001 INT0 External Interrupt Request 0 - 3 0x0002 PCINT0 Pin Change Interrupt Request 0 - 4 0x0003 TIM0_OVF Timer/Counter Overflow - 5 0x0004 EE_RDY EEPROM Ready - 6 0x0005 ANA_COMP Analog Comparator - 7 0x0006 TIM0_COMPA Timer/Counter Compare Match A - 8 0x0007 TIM0_COMPB Timer/Counter Compare Match B - 9 0x0008 WDT Watchdog Time-out - 10 0x0009 ADC ADC Conversion Complete */ - -/* External Interrupt 0 */ -#define INT0_vect_num 1 -#define INT0_vect _VECTOR(1) -#define SIG_INTERRUPT0 _VECTOR(1) - -/* External Interrupt Request 0 */ -#define PCINT0_vect_num 2 -#define PCINT0_vect _VECTOR(2) -#define SIG_PIN_CHANGE0 _VECTOR(2) - -/* Timer/Counter0 Overflow */ -#define TIM0_OVF_vect_num 3 -#define TIM0_OVF_vect _VECTOR(3) -#define SIG_OVERFLOW0 _VECTOR(3) - -/* EEPROM Ready */ -#define EE_RDY_vect_num 4 -#define EE_RDY_vect _VECTOR(4) -#define SIG_EEPROM_READY _VECTOR(4) - -/* Analog Comparator */ -#define ANA_COMP_vect_num 5 -#define ANA_COMP_vect _VECTOR(5) -#define SIG_COMPARATOR _VECTOR(5) - -/* Timer/Counter Compare Match A */ -#define TIM0_COMPA_vect_num 6 -#define TIM0_COMPA_vect _VECTOR(6) -#define SIG_OUTPUT_COMPARE0A _VECTOR(6) - -/* Timer/Counter Compare Match B */ -#define TIM0_COMPB_vect_num 7 -#define TIM0_COMPB_vect _VECTOR(7) -#define SIG_OUTPUT_COMPARE0B _VECTOR(7) - -/* Watchdog Time-out */ -#define WDT_vect_num 8 -#define WDT_vect _VECTOR(8) -#define SIG_WATCHDOG_TIMEOUT _VECTOR(8) - -/* ADC Conversion Complete */ -#define ADC_vect_num 9 -#define ADC_vect _VECTOR(9) -#define SIG_ADC _VECTOR(9) - -#define _VECTORS_SIZE 20 - -#define SPM_PAGESIZE 32 -#define RAMSTART (0x60) -#define RAMEND 0x9F -#define XRAMEND RAMEND -#define E2END 0x3F -#define E2PAGESIZE 4 -#define FLASHEND 0x3FF - - -/* Fuses */ - -#define FUSE_MEMORY_SIZE 2 - -/* Low Fuse Byte */ -#define FUSE_CKSEL0 (unsigned char)~_BV(0) -#define FUSE_CKSEL1 (unsigned char)~_BV(1) -#define FUSE_SUT0 (unsigned char)~_BV(2) -#define FUSE_SUT1 (unsigned char)~_BV(3) -#define FUSE_CKDIV8 (unsigned char)~_BV(4) -#define FUSE_WDTON (unsigned char)~_BV(5) -#define FUSE_EESAVE (unsigned char)~_BV(6) -#define FUSE_SPIEN (unsigned char)~_BV(7) -#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_SUT0 & FUSE_CKDIV8 & FUSE_SPIEN) - -/* High Fuse Byte */ -#define FUSE_RSTDISBL (unsigned char)~_BV(0) -#define FUSE_BODLEVEL0 (unsigned char)~_BV(1) -#define FUSE_BODLEVEL1 (unsigned char)~_BV(2) -#define FUSE_DWEN (unsigned char)~_BV(3) -#define FUSE_SPMEN (unsigned char)~_BV(4) -#define HFUSE_DEFAULT (0xFF) - - -/* Lock Bits */ -#define __LOCK_BITS_EXIST - - -/* Signature */ -#define SIGNATURE_0 0x1E -#define SIGNATURE_1 0x90 -#define SIGNATURE_2 0x07 - - -/* Deprecated items */ -#if !defined(__AVR_LIBC_DEPRECATED_ENABLE__) - -#pragma GCC system_header - -#pragma GCC poison SIG_INTERRUPT0 -#pragma GCC poison SIG_PIN_CHANGE0 -#pragma GCC poison SIG_OVERFLOW0 -#pragma GCC poison SIG_EEPROM_READY -#pragma GCC poison SIG_COMPARATOR -#pragma GCC poison SIG_OUTPUT_COMPARE0A -#pragma GCC poison SIG_OUTPUT_COMPARE0B -#pragma GCC poison SIG_WATCHDOG_TIMEOUT -#pragma GCC poison SIG_ADC - -#endif /* !defined(__AVR_LIBC_DEPRECATED_ENABLE__) */ - -#define SLEEP_MODE_IDLE (0x00<<3) -#define SLEEP_MODE_ADC (0x01<<3) -#define SLEEP_MODE_PWR_DOWN (0x02<<3) - -#endif /* _AVR_IOTN13_H_*/ diff --git a/arduino/hardware/tools/avr/avr/include/avr/iotn13a.h b/arduino/hardware/tools/avr/avr/include/avr/iotn13a.h deleted file mode 100644 index cb9db8f..0000000 --- a/arduino/hardware/tools/avr/avr/include/avr/iotn13a.h +++ /dev/null @@ -1,394 +0,0 @@ -/* Copyright (c) 2008 Atmel Corporation - All rights reserved. - - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - * Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - * Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in - the documentation and/or other materials provided with the - distribution. - - * Neither the name of the copyright holders nor the names of - contributors may be used to endorse or promote products derived - from this software without specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. */ - -/* $Id: iotn13a.h 1955 2009-04-28 08:51:16Z arcanum $ */ - -/* avr/iotn13a.h - definitions for ATtiny13 */ - -/* This file should only be included from , never directly. */ - -#ifndef _AVR_IO_H_ -# error "Include instead of this file." -#endif - -#ifndef _AVR_IOXXX_H_ -# define _AVR_IOXXX_H_ "iotn13a.h" -#else -# error "Attempt to include more than one file." -#endif - - -#ifndef _AVR_ATTINY13A_H_ -#define _AVR_ATTINY13A_H_ 1 - - -/* Registers and associated bit numbers. */ - -#define ADCSRB _SFR_IO8(0x03) -#define ADTS0 0 -#define ADTS1 1 -#define ADTS2 2 -#define ACME 6 - -#ifndef __ASSEMBLER__ -#define ADC _SFR_IO16(0x04) -#endif -#define ADCW _SFR_IO16(0x04) - -#define ADCL _SFR_IO8(0x04) -#define ADCL0 0 -#define ADCL1 1 -#define ADCL2 2 -#define ADCL3 3 -#define ADCL4 4 -#define ADCL5 5 -#define ADCL6 6 -#define ADCL7 7 - -#define ADCH _SFR_IO8(0x05) -#define ADCH0 0 -#define ADCH1 1 -#define ADCH2 2 -#define ADCH3 3 -#define ADCH4 4 -#define ADCH5 5 -#define ADCH6 6 -#define ADCH7 7 - -#define ADCSRA _SFR_IO8(0x06) -#define ADPS0 0 -#define ADPS1 1 -#define ADPS2 2 -#define ADIE 3 -#define ADIF 4 -#define ADATE 5 -#define ADSC 6 -#define ADEN 7 - -#define ADMUX _SFR_IO8(0x07) -#define MUX0 0 -#define MUX1 1 -#define ADLAR 5 -#define REFS0 6 - -#define ACSR _SFR_IO8(0x08) -#define ACIS0 0 -#define ACIS1 1 -#define ACIE 3 -#define ACI 4 -#define ACO 5 -#define ACBG 6 -#define ACD 7 - -#define DIDR0 _SFR_IO8(0x14) -#define AIN0D 0 -#define AIN1D 1 -#define ADC1D 2 -#define ADC3D 3 -#define ADC2D 4 -#define ADC0D 5 - -#define PCMSK _SFR_IO8(0x15) -#define PCINT0 0 -#define PCINT1 1 -#define PCINT2 2 -#define PCINT3 3 -#define PCINT4 4 -#define PCINT5 5 - -#define PINB _SFR_IO8(0x16) -#define PINB0 0 -#define PINB1 1 -#define PINB2 2 -#define PINB3 3 -#define PINB4 4 -#define PINB5 5 - -#define DDRB _SFR_IO8(0x17) -#define DDB0 0 -#define DDB1 1 -#define DDB2 2 -#define DDB3 3 -#define DDB4 4 -#define DDB5 5 - -#define PORTB _SFR_IO8(0x18) -#define PORTB0 0 -#define PORTB1 1 -#define PORTB2 2 -#define PORTB3 3 -#define PORTB4 4 -#define PORTB5 5 - -#define EECR _SFR_IO8(0x1C) -#define EERE 0 -#define EEWE 1 -#define EEPE EEWE -#define EEMWE 2 -#define EEMPE EEMWE -#define EERIE 3 -#define EEPM0 4 -#define EEPM1 5 - -#define EEDR _SFR_IO8(0x1D) -#define EEDR0 0 -#define EEDR1 1 -#define EEDR2 2 -#define EEDR3 3 -#define EEDR4 4 -#define EEDR5 5 -#define EEDR6 6 -#define EEDR7 7 - -#define EEARL _SFR_IO8(0x1E) - -#define EEAR _SFR_IO8(0x1E) -#define EEAR0 0 -#define EEAR1 1 -#define EEAR2 2 -#define EEAR3 3 -#define EEAR4 4 -#define EEAR5 5 - -#define WDTCR _SFR_IO8(0x21) -#define WDP0 0 -#define WDP1 1 -#define WDP2 2 -#define WDE 3 -#define WDCE 4 -#define WDP3 5 -#define WDTIE 6 -#define WDTIF 7 - -#define PRR _SFR_IO8(0x25) -#define PRADC 0 -#define PRTIM0 1 - -#define __AVR_HAVE_PRR ((1<, never directly. */ - -#ifndef _AVR_IO_H_ -# error "Include instead of this file." -#endif - -#ifndef _AVR_IOXXX_H_ -# define _AVR_IOXXX_H_ "iotn15.h" -#else -# error "Attempt to include more than one file." -#endif - -#ifndef __ASSEMBLER__ -# warning "MCU not supported by the C compiler" -#endif - -/* I/O registers */ - -/* 0x00..0x03 reserved */ - -#ifndef __ASSEMBLER__ -#define ADC _SFR_IO16 (0x04) -#endif -#define ADCW _SFR_IO16(0x04) -#define ADCL _SFR_IO8(0x04) -#define ADCH _SFR_IO8(0x05) -#define ADCSR _SFR_IO8(0x06) -#define ADMUX _SFR_IO8(0x07) - -/* Analog Comparator Control and Status Register */ -#define ACSR _SFR_IO8(0x08) - -/* 0x09..0x15 reserved */ - -/* Input Pins, Port B */ -#define PINB _SFR_IO8(0x16) - -/* Data Direction Register, Port B */ -#define DDRB _SFR_IO8(0x17) - -/* Data Register, Port B */ -#define PORTB _SFR_IO8(0x18) - -/* 0x19..0x1B reserved */ - -/* EEPROM Control Register */ -#define EECR _SFR_IO8(0x1C) - -/* EEPROM Data Register */ -#define EEDR _SFR_IO8(0x1D) - -/* EEPROM Address Register */ -#define EEAR _SFR_IO8(0x1E) -#define EEARL _SFR_IO8(0x1E) - -/* 0x1F..0x20 reserved */ - -/* Watchdog Timer Control Register */ -#define WDTCR _SFR_IO8(0x21) - -/* 0x22..0x2B reserved */ -#define SFIOR _SFR_IO8(0x2C) - -#define OCR1B _SFR_IO8(0x2D) -#define OCR1A _SFR_IO8(0x2E) -#define TCNT1 _SFR_IO8(0x2F) -#define TCCR1 _SFR_IO8(0x30) - -/* Oscillator Calibration Register */ -#define OSCCAL _SFR_IO8(0x31) - -/* Timer/Counter0 (8-bit) */ -#define TCNT0 _SFR_IO8(0x32) - -/* Timer/Counter0 Control Register */ -#define TCCR0 _SFR_IO8(0x33) - -/* MCU general Status Register */ -#define MCUSR _SFR_IO8(0x34) - -/* MCU general Control Register */ -#define MCUCR _SFR_IO8(0x35) - -/* 0x36..0x37 reserved */ - -/* Timer/Counter Interrupt Flag Register */ -#define TIFR _SFR_IO8(0x38) - -/* Timer/Counter Interrupt MaSK Register */ -#define TIMSK _SFR_IO8(0x39) - -/* General Interrupt Flag Register */ -#define GIFR _SFR_IO8(0x3A) - -/* General Interrupt MaSK register */ -#define GIMSK _SFR_IO8(0x3B) - -/* 0x3C..0x3E reserved */ - -/* 0x3F SREG */ - -/* Interrupt vectors */ - -/* External Interrupt 0 */ -#define INT0_vect_num 1 -#define INT0_vect _VECTOR(1) -#define SIG_INTERRUPT0 _VECTOR(1) - -/* External Interrupt Request 0 */ -#define IO_PINS_vect_num 2 -#define IO_PINS_vect _VECTOR(2) -#define SIG_PIN _VECTOR(2) -#define SIG_PIN_CHANGE _VECTOR(2) - -/* Timer/Counter1 Compare Match */ -#define TIMER1_COMP_vect_num 3 -#define TIMER1_COMP_vect _VECTOR(3) -#define SIG_OUTPUT_COMPARE1A _VECTOR(3) - -/* Timer/Counter1 Overflow */ -#define TIMER1_OVF_vect_num 4 -#define TIMER1_OVF_vect _VECTOR(4) -#define SIG_OVERFLOW1 _VECTOR(4) - -/* Timer/Counter0 Overflow */ -#define TIMER0_OVF_vect_num 5 -#define TIMER0_OVF_vect _VECTOR(5) -#define SIG_OVERFLOW0 _VECTOR(5) - -/* EEPROM Ready */ -#define EE_RDY_vect_num 6 -#define EE_RDY_vect _VECTOR(6) -#define SIG_EEPROM_READY _VECTOR(6) - -/* Analog Comparator */ -#define ANA_COMP_vect_num 7 -#define ANA_COMP_vect _VECTOR(7) -#define SIG_COMPARATOR _VECTOR(7) - -/* ADC Conversion Ready */ -#define ADC_vect_num 8 -#define ADC_vect _VECTOR(8) -#define SIG_ADC _VECTOR(8) - -#define _VECTORS_SIZE 18 - -/* Bit numbers */ - -/* GIMSK */ -#define INT0 6 -#define PCIE 5 - -/* GIFR */ -#define INTF0 6 -#define PCIF 5 - -/* TIMSK */ -#define OCIE1 6 -#define TOIE1 2 -#define TOIE0 1 - -/* TIFR */ -#define OCF1 6 -#define TOV1 2 -#define TOV0 1 - -/* MCUCR */ -#define PUD 6 -#define SE 5 -#define SM1 4 -#define SM0 3 -#define ISC01 1 -#define ISC00 0 - -/* MCUSR */ -#define WDRF 3 -#define BORF 2 -#define EXTRF 1 -#define PORF 0 - -/* TCCR0 */ -#define CS02 2 -#define CS01 1 -#define CS00 0 - -/* TCCR1 */ -#define CTC1 7 -#define PWM1 6 -#define COM1A1 5 -#define COM1A0 4 -#define CS13 3 -#define CS12 2 -#define CS11 1 -#define CS10 0 - -/* SFIOR */ -#define FOC1A 2 -#define PSR1 1 -#define PSR0 0 - -/* WDTCR */ -#define WDTOE 4 -#define WDE 3 -#define WDP2 2 -#define WDP1 1 -#define WDP0 0 - -/* - PB5 = RESET# / ADC0 - PB4 = ADC3 - PB3 = ADC2 - PB2 = SCK / ADC1 / T0 / INT0 - PB1 = MISO / AIN1 / OCP - PB0 = MOSI / AIN0 / AREF - */ - -/* PORTB */ -#define PB4 4 -#define PB3 3 -#define PB2 2 -#define PB1 1 -#define PB0 0 - -/* DDRB */ -#define DDB4 4 -#define DDB3 3 -#define DDB2 2 -#define DDB1 1 -#define DDB0 0 - -/* PINB */ -#define PINB5 5 -#define PINB4 4 -#define PINB3 3 -#define PINB2 2 -#define PINB1 1 -#define PINB0 0 - -/* ACSR */ -#define ACD 7 -#define GREF 6 -#define ACO 5 -#define ACI 4 -#define ACIE 3 -#define ACIS1 1 -#define ACIS0 0 - -/* ADMUX */ -#define REFS1 7 -#define REFS0 6 -#define ADLAR 5 -#define MUX2 2 -#define MUX1 1 -#define MUX0 0 - -/* ADCSR */ -#define ADEN 7 -#define ADSC 6 -#define ADFR 5 -#define ADIF 4 -#define ADIE 3 -#define ADPS2 2 -#define ADPS1 1 -#define ADPS0 0 - -/* EEPROM Control Register */ -#define EERIE 3 -#define EEMWE 2 -#define EEWE 1 -#define EERE 0 - -#define RAMSTART 0x60 -/* Last memory addresses */ -#define RAMEND 0x1F -#define XRAMEND 0x0 -#define E2END 0x3F -#define E2PAGESIZE 2 -#define FLASHEND 0x3FF - - -/* Fuses */ - -#define FUSE_MEMORY_SIZE 1 - -/* Fuse Byte */ -#define FUSE_CKSEL0 (unsigned char)~_BV(0) -#define FUSE_CKSEL1 (unsigned char)~_BV(1) -#define FUSE_RSTDISBL (unsigned char)~_BV(4) -#define FUSE_SPIEN (unsigned char)~_BV(5) -#define FUSE_BODEN (unsigned char)~_BV(6) -#define FUSE_BODLEVEL (unsigned char)~_BV(7) -#define FUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL1 & FUSE_SPIEN) - - -/* Lock Bits */ -#define __LOCK_BITS_EXIST - - -/* Signature */ -#define SIGNATURE_0 0x1E -#define SIGNATURE_1 0x90 -#define SIGNATURE_2 0x06 - - -/* Deprecated items */ -#if !defined(__AVR_LIBC_DEPRECATED_ENABLE__) - -#pragma GCC system_header - -#pragma GCC poison SIG_INTERRUPT0 -#pragma GCC poison SIG_PIN -#pragma GCC poison SIG_PIN_CHANGE -#pragma GCC poison SIG_OUTPUT_COMPARE1A -#pragma GCC poison SIG_OVERFLOW1 -#pragma GCC poison SIG_OVERFLOW0 -#pragma GCC poison SIG_EEPROM_READY -#pragma GCC poison SIG_COMPARATOR -#pragma GCC poison SIG_ADC - -#endif /* !defined(__AVR_LIBC_DEPRECATED_ENABLE__) */ - -#define SLEEP_MODE_IDLE (0x00<<3) -#define SLEEP_MODE_ADC (0x01<<3) -#define SLEEP_MODE_PWR_DOWN (0x02<<3) - -#endif /* _AVR_IOTN15_H_ */ diff --git a/arduino/hardware/tools/avr/avr/include/avr/iotn1634.h b/arduino/hardware/tools/avr/avr/include/avr/iotn1634.h deleted file mode 100644 index b0ca5b5..0000000 --- a/arduino/hardware/tools/avr/avr/include/avr/iotn1634.h +++ /dev/null @@ -1,914 +0,0 @@ -/***************************************************************************** - * - * Copyright (C) 2015 Atmel Corporation - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * - * * Neither the name of the copyright holders nor the names of - * contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - ****************************************************************************/ - - -#ifndef _AVR_ATTINY1634_H_INCLUDED -#define _AVR_ATTINY1634_H_INCLUDED - - -#ifndef _AVR_IO_H_ -# error "Include instead of this file." -#endif - -#ifndef _AVR_IOXXX_H_ -# define _AVR_IOXXX_H_ "iotn1634.h" -#else -# error "Attempt to include more than one file." -#endif - -/* Registers and associated bit numbers */ - -/* Combine ADCL and ADCH */ -#ifndef __ASSEMBLER__ -#define ADC _SFR_IO16(0x00) -#endif -#define ADCW _SFR_IO16(0x00) - -#define ADCL _SFR_IO8(0x00) -#define ADCH _SFR_IO8(0x01) - -#define ADCSRB _SFR_IO8(0x02) -#define ADTS0 0 -#define ADTS1 1 -#define ADTS2 2 -#define ADLAR 3 -#define VDPD 6 -#define VDEN 7 - -#define ADCSRA _SFR_IO8(0x03) -#define ADPS0 0 -#define ADPS1 1 -#define ADPS2 2 -#define ADIE 3 -#define ADIF 4 -#define ADATE 5 -#define ADSC 6 -#define ADEN 7 - -#define ADMUX _SFR_IO8(0x04) -#define MUX0 0 -#define MUX1 1 -#define MUX2 2 -#define MUX3 3 -#define ADC0EN 4 -#define REFEN 5 -#define REFS0 6 -#define REFS1 7 - -#define ACSRB _SFR_IO8(0x05) -#define ACIRS0 0 -#define ACIRS1 1 -#define ACME 2 -#define ACCE 3 -#define ACLP 5 -#define HLEV 6 -#define HSEL 7 - -#define ACSRA _SFR_IO8(0x06) -#define ACIS0 0 -#define ACIS1 1 -#define ACIC 2 -#define ACIE 3 -#define ACI 4 -#define ACO 5 -#define ACBG 6 -#define ACD 7 - -#define PINC _SFR_IO8(0x07) -#define PINC5 5 -#define PINC4 4 -#define PINC3 3 -#define PINC2 2 -#define PINC1 1 -#define PINC0 0 - -#define DDRC _SFR_IO8(0x08) -#define DDRC5 5 -// Inserted "DDC5" from "DDRC5" due to compatibility -#define DDC5 5 -#define DDRC4 4 -// Inserted "DDC4" from "DDRC4" due to compatibility -#define DDC4 4 -#define DDRC3 3 -// Inserted "DDC3" from "DDRC3" due to compatibility -#define DDC3 3 -#define DDRC2 2 -// Inserted "DDC2" from "DDRC2" due to compatibility -#define DDC2 2 -#define DDRC1 1 -// Inserted "DDC1" from "DDRC1" due to compatibility -#define DDC1 1 -#define DDRC0 0 -// Inserted "DDC0" from "DDRC0" due to compatibility -#define DDC0 0 - -#define PORTC _SFR_IO8(0x09) -#define PORTC5 5 -#define PORTC4 4 -#define PORTC3 3 -#define PORTC2 2 -#define PORTC1 1 -#define PORTC0 0 - -#define PUEC _SFR_IO8(0x0A) -#define PUEC0 0 -#define PUEC1 1 -#define PUEC2 2 -#define PUEC3 3 -#define PUEC4 4 -#define PUEC5 5 - -#define PINB _SFR_IO8(0x0B) -#define PINB3 3 -#define PINB2 2 -#define PINB1 1 -#define PINB0 0 - -#define DDRB _SFR_IO8(0x0C) -#define DDRB3 3 -// Inserted "DDB3" from "DDRB3" due to compatibility -#define DDB3 3 -#define DDRB2 2 -// Inserted "DDB2" from "DDRB2" due to compatibility -#define DDB2 2 -#define DDRB1 1 -// Inserted "DDB1" from "DDRB1" due to compatibility -#define DDB1 1 -#define DDRB0 0 -// Inserted "DDB0" from "DDRB0" due to compatibility -#define DDB0 0 - -#define PORTB _SFR_IO8(0x0D) -#define PORTB3 3 -#define PORTB2 2 -#define PORTB1 1 -#define PORTB0 0 - -#define PUEB _SFR_IO8(0x0E) -#define PUEB0 0 -#define PUEB1 1 -#define PUEB2 2 -#define PUEB3 3 - -#define PINA _SFR_IO8(0x0F) -#define PINA7 7 -#define PINA6 6 -#define PINA5 5 -#define PINA4 4 -#define PINA3 3 -#define PINA2 2 -#define PINA1 1 -#define PINA0 0 - -#define DDRA _SFR_IO8(0x10) -#define DDRA7 7 -// Inserted "DDA7" from "DDRA7" due to compatibility -#define DDA7 7 -#define DDRA6 6 -// Inserted "DDA6" from "DDRA6" due to compatibility -#define DDA6 6 -#define DDRA5 5 -// Inserted "DDA5" from "DDRA5" due to compatibility -#define DDA5 5 -#define DDRA4 4 -// Inserted "DDA4" from "DDRA4" due to compatibility -#define DDA4 4 -#define DDRA3 3 -// Inserted "DDA3" from "DDRA3" due to compatibility -#define DDA3 3 -#define DDRA2 2 -// Inserted "DDA2" from "DDRA2" due to compatibility -#define DDA2 2 -#define DDRA1 1 -// Inserted "DDA1" from "DDRA1" due to compatibility -#define DDA1 1 -#define DDRA0 0 -// Inserted "DDA0" from "DDRA0" due to compatibility -#define DDA0 0 - -#define PORTA _SFR_IO8(0x11) -#define PORTA7 7 -#define PORTA6 6 -#define PORTA5 5 -#define PORTA4 4 -#define PORTA3 3 -#define PORTA2 2 -#define PORTA1 1 -#define PORTA0 0 - -#define PUEA _SFR_IO8(0x12) -#define PUEA0 0 -#define PUEA1 1 -#define PUEA2 2 -#define PUEA3 3 -#define PUEA4 4 -#define PUEA5 5 -#define PUEA6 6 -#define PUEA7 7 - -#define PORTCR _SFR_IO8(0x13) -#define BBMB 1 -#define BBMC 2 -#define BBMA 0 - -#define GPIOR0 _SFR_IO8(0x14) - -#define GPIOR1 _SFR_IO8(0x15) - -#define GPIOR2 _SFR_IO8(0x16) - -#define OCR0B _SFR_IO8(0x17) - -#define OCR0A _SFR_IO8(0x18) - -#define TCNT0 _SFR_IO8(0x19) - -#define TCCR0B _SFR_IO8(0x1A) -#define CS00 0 -#define CS01 1 -#define CS02 2 -#define WGM02 3 -#define FOC0B 6 -#define FOC0A 7 - -#define TCCR0A _SFR_IO8(0x1B) -#define WGM00 0 -#define WGM01 1 -#define COM0B0 4 -#define COM0B1 5 -#define COM0A0 6 -#define COM0A1 7 - -#define EECR _SFR_IO8(0x1C) -#define EERE 0 -#define EEPE 1 -#define EEMPE 2 -#define EERIE 3 -#define EEPM0 4 -#define EEPM1 5 - -#define EEDR _SFR_IO8(0x1D) - -/* Combine EEARL and EEARH */ -#define EEAR _SFR_IO16(0x1E) - -#define EEARL _SFR_IO8(0x1E) -#define EEARH _SFR_IO8(0x1F) - -#define UDR0 _SFR_IO8(0x20) - -/* Combine UBRR0L and UBRR0H */ -#define UBRR0 _SFR_IO16(0x21) - -#define UBRR0L _SFR_IO8(0x21) -#define UBRR0H _SFR_IO8(0x22) - -#define UCSR0D _SFR_IO8(0x23) -#define SFDE0 5 -#define RXS0 6 -#define RXSIE0 7 - -#define UCSR0C _SFR_IO8(0x24) -#define UCPOL0 0 -#define UCSZ00 1 -#define UCSZ01 2 -#define USBS0 3 -#define UPM00 4 -#define UPM01 5 -#define UMSEL00 6 -#define UMSEL01 7 - -#define UCSR0B _SFR_IO8(0x25) -#define TXB80 0 -#define RXB80 1 -#define UCSZ02 2 -#define TXEN0 3 -#define RXEN0 4 -#define UDRIE0 5 -#define TXCIE0 6 -#define RXCIE0 7 - -#define UCSR0A _SFR_IO8(0x26) -#define MPCM0 0 -#define U2X0 1 -#define UPE0 2 -#define DOR0 3 -#define FE0 4 -#define UDRE0 5 -#define TXC0 6 -#define RXC0 7 - -#define PCMSK0 _SFR_IO8(0x27) -#define PCINT0 0 -#define PCINT1 1 -#define PCINT2 2 -#define PCINT3 3 -#define PCINT4 4 -#define PCINT5 5 -#define PCINT6 6 -#define PCINT7 7 - -#define PCMSK1 _SFR_IO8(0x28) -#define PCINT8 0 -#define PCINT9 1 -#define PCINT10 2 -#define PCINT11 3 - -#define PCMSK2 _SFR_IO8(0x29) -#define PCINT12 0 -#define PCINT13 1 -#define PCINT14 2 -#define PCINT15 3 -#define PCINT16 4 -#define PCINT17 5 - -#define USICR _SFR_IO8(0x2A) -#define USITC 0 -#define USICLK 1 -#define USICS0 2 -#define USICS1 3 -#define USIWM0 4 -#define USIWM1 5 -#define USIOIE 6 -#define USISIE 7 - -#define USISR _SFR_IO8(0x2B) -#define USICNT0 0 -#define USICNT1 1 -#define USICNT2 2 -#define USICNT3 3 -#define USIDC 4 -#define USIPF 5 -#define USIOIF 6 -#define USISIF 7 - -#define USIDR _SFR_IO8(0x2C) - -#define USIBR _SFR_IO8(0x2D) - -/* Reserved [0x2E] */ - -#define CCP _SFR_IO8(0x2F) - -#define WDTCSR _SFR_IO8(0x30) -#define WDE 3 -#define WDP0 0 -#define WDP1 1 -#define WDP2 2 -#define WDP3 5 -#define WDIE 6 -#define WDIF 7 - -/* Reserved [0x31] */ - -#define CLKSR _SFR_IO8(0x32) -#define CKSEL0 0 -#define CKSEL1 1 -#define CKSEL2 2 -#define CKSEL3 3 -#define SUT 4 -#define CKOUT_IO 5 -#define CSTR 6 -#define OSCRDY 7 - -#define CLKPR _SFR_IO8(0x33) -#define CLKPS0 0 -#define CLKPS1 1 -#define CLKPS2 2 -#define CLKPS3 3 - -#define PRR _SFR_IO8(0x34) -#define PRADC 0 -#define PRUSART0 1 -#define PRUSART1 2 -#define PRUSI 3 -#define PRTIM0 4 -#define PRTIM1 5 -#define PRTWI 6 - -#define __AVR_HAVE_PRR ((1<, never directly. */ - -#ifndef _AVR_IO_H_ -# error "Include instead of this file." -#endif - -#ifndef _AVR_IOXXX_H_ -# define _AVR_IOXXX_H_ "iotn167.h" -#else -# error "Attempt to include more than one file." -#endif - - -#ifndef _AVR_IOTN167_H_ -#define _AVR_IOTN167_H_ 1 - - -/* Registers and associated bit numbers */ - -#define PINA _SFR_IO8(0x00) -#define PINA0 0 -#define PINA1 1 -#define PINA2 2 -#define PINA3 3 -#define PINA4 4 -#define PINA5 5 -#define PINA6 6 -#define PINA7 7 - -#define DDRA _SFR_IO8(0x01) -#define DDA0 0 -#define DDA1 1 -#define DDA2 2 -#define DDA3 3 -#define DDA4 4 -#define DDA5 5 -#define DDA6 6 -#define DDA7 7 - -#define PORTA _SFR_IO8(0x02) -#define PORTA0 0 -#define PORTA1 1 -#define PORTA2 2 -#define PORTA3 3 -#define PORTA4 4 -#define PORTA5 5 -#define PORTA6 6 -#define PORTA7 7 - -#define PINB _SFR_IO8(0x03) -#define PINB0 0 -#define PINB1 1 -#define PINB2 2 -#define PINB3 3 -#define PINB4 4 -#define PINB5 5 -#define PINB6 6 -#define PINB7 7 - -#define DDRB _SFR_IO8(0x04) -#define DDB0 0 -#define DDB1 1 -#define DDB2 2 -#define DDB3 3 -#define DDB4 4 -#define DDB5 5 -#define DDB6 6 -#define DDB7 7 - -#define PORTB _SFR_IO8(0x05) -#define PORTB0 0 -#define PORTB1 1 -#define PORTB2 2 -#define PORTB3 3 -#define PORTB4 4 -#define PORTB5 5 -#define PORTB6 6 -#define PORTB7 7 - -#define PORTCR _SFR_IO8(0x12) -#define PUDA 0 -#define PUDB 1 -#define BBMA 4 -#define BBMB 5 - -#define TIFR0 _SFR_IO8(0x15) -#define TOV0 0 -#define OCF0A 1 - -#define TIFR1 _SFR_IO8(0x16) -#define TOV1 0 -#define OCF1A 1 -#define OCF1B 2 -#define ICF1 5 - -#define PCIFR _SFR_IO8(0x1B) -#define PCIF0 0 -#define PCIF1 1 - -#define EIFR _SFR_IO8(0x1C) -#define INTF0 0 -#define INTF1 1 - -#define EIMSK _SFR_IO8(0x1D) -#define INT0 0 -#define INT1 1 - -#define GPIOR0 _SFR_IO8(0x1E) -#define GPIOR00 0 -#define GPIOR01 1 -#define GPIOR02 2 -#define GPIOR03 3 -#define GPIOR04 4 -#define GPIOR05 5 -#define GPIOR06 6 -#define GPIOR07 7 - -#define EECR _SFR_IO8(0x1F) -#define EERE 0 -#define EEPE 1 -#define EEMPE 2 -#define EERIE 3 -#define EEPM0 4 -#define EEPM1 5 - -#define EEDR _SFR_IO8(0x20) -#define EEDR0 0 -#define EEDR1 1 -#define EEDR2 2 -#define EEDR3 3 -#define EEDR4 4 -#define EEDR5 5 -#define EEDR6 6 -#define EEDR7 7 - -#define EEAR _SFR_IO16(0x21) - -#define EEARL _SFR_IO8(0x21) -#define EEAR0 0 -#define EEAR1 1 -#define EEAR2 2 -#define EEAR3 3 -#define EEAR4 4 -#define EEAR5 5 -#define EEAR6 6 -#define EEAR7 7 - -#define EEARH _SFR_IO8(0x22) -#define EEAR8 0 - -#define GTCCR _SFR_IO8(0x23) -#define PSR1 0 -#define PSR0 1 -#define TSM 7 - -#define TCCR0A _SFR_IO8(0x25) -#define WGM00 0 -#define WGM01 1 -#define COM0A0 6 -#define COM0A1 7 - -#define TCCR0B _SFR_IO8(0x26) -#define CS00 0 -#define CS01 1 -#define CS02 2 -#define FOC0A 7 - -#define TCNT0 _SFR_IO8(0x27) -#define TCNT00 0 -#define TCNT01 1 -#define TCNT02 2 -#define TCNT03 3 -#define TCNT04 4 -#define TCNT05 5 -#define TCNT06 6 -#define TCNT07 7 - -#define OCR0A _SFR_IO8(0x28) -#define OCR00 0 -#define OCR01 1 -#define OCR02 2 -#define OCR03 3 -#define OCR04 4 -#define OCR05 5 -#define OCR06 6 -#define OCR07 7 - -#define GPIOR1 _SFR_IO8(0x2A) -#define GPIOR10 0 -#define GPIOR11 1 -#define GPIOR12 2 -#define GPIOR13 3 -#define GPIOR14 4 -#define GPIOR15 5 -#define GPIOR16 6 -#define GPIOR17 7 - -#define GPIOR2 _SFR_IO8(0x2B) -#define GPIOR20 0 -#define GPIOR21 1 -#define GPIOR22 2 -#define GPIOR23 3 -#define GPIOR24 4 -#define GPIOR25 5 -#define GPIOR26 6 -#define GPIOR27 7 - -#define SPCR _SFR_IO8(0x2C) -#define SPR0 0 -#define SPR1 1 -#define CPHA 2 -#define CPOL 3 -#define MSTR 4 -#define DORD 5 -#define SPE 6 -#define SPIE 7 - -#define SPSR _SFR_IO8(0x2D) -#define SPI2X 0 -#define WCOL 6 -#define SPIF 7 - -#define SPDR _SFR_IO8(0x2E) -#define SPDR0 0 -#define SPDR1 1 -#define SPDR2 2 -#define SPDR3 3 -#define SPDR4 4 -#define SPDR5 5 -#define SPDR6 6 -#define SPDR7 7 - -#define ACSR _SFR_IO8(0x30) -#define ACIS0 0 -#define ACIS1 1 -#define ACIC 2 -#define ACIE 3 -#define ACI 4 -#define ACO 5 -#define ACIRS 6 -#define ACD 7 - -#define DWDR _SFR_IO8(0x31) -#define DWDR0 0 -#define DWDR1 1 -#define DWDR2 2 -#define DWDR3 3 -#define DWDR4 4 -#define DWDR5 5 -#define DWDR6 6 -#define DWDR7 7 - -#define SMCR _SFR_IO8(0x33) -#define SE 0 -#define SM0 1 -#define SM1 2 - -#define MCUSR _SFR_IO8(0x34) -#define PORF 0 -#define EXTRF 1 -#define BORF 2 -#define WDRF 3 - -#define MCUCR _SFR_IO8(0x35) -#define PUD 4 -#define BODSE 5 -#define BODS 6 - -#define SPMCSR _SFR_IO8(0x37) -#define SPMEN 0 -#define PGERS 1 -#define PGWRT 2 -#define RFLB 3 -#define CTPB 4 -#define SIGRD 5 -#define RWWSB 6 - -#define WDTCR _SFR_MEM8(0x60) -#define WDP0 0 -#define WDP1 1 -#define WDP2 2 -#define WDE 3 -#define WDCE 4 -#define WDP3 5 -#define WDIE 6 -#define WDIF 7 - -#define CLKPR _SFR_MEM8(0x61) -#define CLKPS0 0 -#define CLKPS1 1 -#define CLKPS2 2 -#define CLKPS3 3 -#define CLKPCE 7 - -#define CLKCSR _SFR_MEM8(0x62) -#define CLKC0 0 -#define CLKC1 1 -#define CLKC2 2 -#define CLKC3 3 -#define CLKRDY 4 -#define CLKCCE 7 - -#define CLKSELR _SFR_MEM8(0x63) -#define CSEL0 0 -#define CSEL1 1 -#define CSEL2 2 -#define CSEL3 3 -#define CSUT0 4 -#define CSUT1 5 -#define COUT 6 - -#define PRR _SFR_MEM8(0x64) -#define PRADC 0 -#define PRUSI 1 -#define PRTIM0 2 -#define PRTIM1 3 -#define PRSPI 4 -#define PRLIN 5 - -#define __AVR_HAVE_PRR ((1<, never directly. */ - -#ifndef _AVR_IO_H_ -# error "Include instead of this file." -#endif - -#ifndef _AVR_IOXXX_H_ -# define _AVR_IOXXX_H_ "iotn20.h" -#else -# error "Attempt to include more than one file." -#endif - - -#ifndef _AVR_ATtiny20_H_ -#define _AVR_ATtiny20_H_ 1 - - -/* Registers and associated bit numbers. */ - -#define PINA _SFR_IO8(0x00) -#define PINA0 0 -#define PINA1 1 -#define PINA2 2 -#define PINA3 3 -#define PINA4 4 -#define PINA5 5 -#define PINA6 6 -#define PINA7 7 - -#define DDRA _SFR_IO8(0x01) -#define DDA0 0 -#define DDA1 1 -#define DDA2 2 -#define DDA3 3 -#define DDA4 4 -#define DDA5 5 -#define DDA6 6 -#define DDA7 7 - -#define PORTA _SFR_IO8(0x02) -#define PORTA0 0 -#define PORTA1 1 -#define PORTA2 2 -#define PORTA3 3 -#define PORTA4 4 -#define PORTA5 5 -#define PORTA6 6 -#define PORTA7 7 - -#define PUEA _SFR_IO8(0x03) -#define PUEA0 0 -#define PUEA1 1 -#define PUEA2 2 -#define PUEA3 3 -#define PUEA4 4 -#define PUEA5 5 -#define PUEA6 6 -#define PUEA7 7 - -#define PINB _SFR_IO8(0x04) -#define PINB0 0 -#define PINB1 1 -#define PINB2 2 -#define PINB3 3 - -#define DDRB _SFR_IO8(0x05) -#define DDB0 0 -#define DDB1 1 -#define DDB2 2 -#define DDB3 3 - -#define PORTB _SFR_IO8(0x06) -#define PORTB0 0 -#define PORTB1 1 -#define PORTB2 2 -#define PORTB3 3 - -#define PUEB _SFR_IO8(0x07) -#define PUEB0 0 -#define PUEB1 1 -#define PUEB2 2 -#define PUEB3 3 - -#define PORTCR _SFR_IO8(0x08) -#define BBMA 0 -#define BBMB 1 - -#define PCMSK0 _SFR_IO8(0x09) -#define PCINT0 0 -#define PCINT1 1 -#define PCINT2 2 -#define PCINT3 3 -#define PCINT4 4 -#define PCINT5 5 -#define PCINT6 6 -#define PCINT7 7 - -#define PCMSK1 _SFR_IO8(0x0A) -#define PCINT8 0 -#define PCINT9 1 -#define PCINT10 2 -#define PCINT11 3 - -#define GIFR _SFR_IO8(0x0B) -#define INTF0 0 -#define PCIF0 4 -#define PCIF1 5 - -#define GIMSK _SFR_IO8(0x0C) -#define INT0 0 -#define PCIE0 4 -#define PCIE1 5 - -#define DIDR0 _SFR_IO8(0x0D) -#define ADC0D 0 -#define ADC1D 1 -#define ADC2D 2 -#define ADC3D 3 -#define ADC4D 4 -#define ADC5D 5 -#define ADC6D 6 -#define ADC7D 7 - -#ifndef __ASSEMBLER__ -#define ADC _SFR_IO16(0x0E) -#endif -#define ADCW _SFR_IO16(0x0E) - -#define ADCL _SFR_IO8(0x0E) -#define ADCL0 0 -#define ADCL1 1 -#define ADCL2 2 -#define ADCL3 3 -#define ADCL4 4 -#define ADCL5 5 -#define ADCL6 6 -#define ADCL7 7 - -#define ADCH _SFR_IO8(0x0F) -#define ADCH0 0 -#define ADCH1 1 -#define ADCH2 2 -#define ADCH3 3 -#define ADCH4 4 -#define ADCH5 5 -#define ADCH6 6 -#define ADCH7 7 - -#define ADMUX _SFR_IO8(0x10) -#define MUX0 0 -#define MUX1 1 -#define MUX2 2 -#define MUX3 3 -#define REFS 6 - -#define ADCSRB _SFR_IO8(0x11) -#define ADTS0 0 -#define ADTS1 1 -#define ADTS2 2 -#define ADLAR 3 - -#define ADCSRA _SFR_IO8(0x12) -#define ADPS0 0 -#define ADPS1 1 -#define ADPS2 2 -#define ADIE 3 -#define ADIF 4 -#define ADATE 5 -#define ADSC 6 -#define ADEN 7 - -#define ACSRB _SFR_IO8(0x13) -#define ACME 2 -#define HLEV 6 -#define HSEL 7 - -#define ACSRA _SFR_IO8(0x14) -#define ACIS0 0 -#define ACIS1 1 -#define ACIC 2 -#define ACIE 3 -#define ACI 4 -#define ACO 5 -#define ACBG 6 -#define ACD 7 - -#define OCR0B _SFR_IO8(0x15) -#define OCR0B_0 0 -#define OCR0B_1 1 -#define OCR0B_2 2 -#define OCR0B_3 3 -#define OCR0B_4 4 -#define OCR0B_5 5 -#define OCR0B_6 6 -#define OCR0B_7 7 - -#define OCR0A _SFR_IO8(0x16) -#define OCR0_0 0 -#define OCR0_1 1 -#define OCR0_2 2 -#define OCR0_3 3 -#define OCR0_4 4 -#define OCR0_5 5 -#define OCR0_6 6 -#define OCR0_7 7 - -#define TCNT0 _SFR_IO8(0x17) -#define TCNT0_0 0 -#define TCNT0_1 1 -#define TCNT0_2 2 -#define TCNT0_3 3 -#define TCNT0_4 4 -#define TCNT0_5 5 -#define TCNT0_6 6 -#define TCNT0_7 7 - -#define TCCR0B _SFR_IO8(0x18) -#define CS00 0 -#define CS01 1 -#define CS02 2 -#define WGM02 3 -#define FOC0B 6 -#define FOC0A 7 - -#define TCCR0A _SFR_IO8(0x19) -#define WGM00 0 -#define WGM01 1 -#define COM0B0 4 -#define COM0B1 5 -#define COM0A0 6 -#define COM0A1 7 - -#define ICR1 _SFR_IO16(0x1A) - -#define ICR1L _SFR_IO8(0x1A) -#define ICR1_0 0 -#define ICR1_1 1 -#define ICR1_2 2 -#define ICR1_3 3 -#define ICR1_4 4 -#define ICR1_5 5 -#define ICR1_6 6 -#define ICR1_7 7 - -#define ICR1H _SFR_IO8(0x1B) -#define ICR1_8 0 -#define ICR1_9 1 -#define ICR1_10 2 -#define ICR1_11 3 -#define ICR1_12 4 -#define ICR1_13 5 -#define ICR1_14 6 -#define ICR1_15 7 - -#define OCR1B _SFR_IO16(0x1C) - -#define OCR1BL _SFR_IO8(0x1C) -#define OCR1B0 0 -#define OCR1B1 1 -#define OCR1B2 2 -#define OCR1B3 3 -#define OCR1B4 4 -#define OCR1B5 5 -#define OCR1B6 6 -#define OCR1B7 7 - -#define OCR1BH _SFR_IO8(0x1D) -#define OCR1B8 0 -#define OCR1B9 1 -#define OCR1B10 2 -#define OCR1B11 3 -#define OCR1B12 4 -#define OCR1B13 5 -#define OCR1B14 6 -#define OCR1B15 7 - -#define OCR1A _SFR_IO16(0x1E) - -#define OCR1AL _SFR_IO8(0x1E) -#define OCR1A0 0 -#define OCR1A1 1 -#define OCR1A2 2 -#define OCR1A3 3 -#define OCR1A4 4 -#define OCR1A5 5 -#define OCR1A6 6 -#define OCR1A7 7 - -#define OCR1AH _SFR_IO8(0x1F) -#define OCR1A8 0 -#define OCR1A9 1 -#define OCR1A10 2 -#define OCR1A11 3 -#define OCR1A12 4 -#define OCR1A13 5 -#define OCR1A14 6 -#define OCR1A15 7 - -#define TCNT1 _SFR_IO16(0x20) - -#define TCNT1L _SFR_IO8(0x20) -#define TCNT1_0 0 -#define TCNT1_1 1 -#define TCNT1_2 2 -#define TCNT1_3 3 -#define TCNT1_4 4 -#define TCNT1_5 5 -#define TCNT1_6 6 -#define TCNT1_7 7 - -#define TCNT1H _SFR_IO8(0x21) -#define TCNT1_8 0 -#define TCNT1_9 1 -#define TCNT1_10 2 -#define TCNT1_11 3 -#define TCNT1_12 4 -#define TCNT1_13 5 -#define TCNT1_14 6 -#define TCNT1_15 7 - -#define TCCR1C _SFR_IO8(0x22) -#define FOC1B 6 -#define FOC1A 7 - -#define TCCR1B _SFR_IO8(0x23) -#define CS10 0 -#define CS11 1 -#define CS12 2 -#define WGM12 3 -#define WGM13 4 -#define ICES1 6 -#define ICNC1 7 - -#define TCCR1A _SFR_IO8(0x24) -#define WGM10 0 -#define WGM11 1 -#define COM1B0 4 -#define COM1B1 5 -#define COM1A0 6 -#define COM1A1 7 - -#define TIFR _SFR_IO8(0x25) -#define TOV0 0 -#define OCF0A 1 -#define OCF0B 2 -#define TOV1 3 -#define OCF1A 4 -#define OCF1B 5 -#define ICF1 7 - -#define TIMSK _SFR_IO8(0x26) -#define TOIE0 0 -#define OCIE0A 1 -#define OCIE0B 2 -#define TOIE1 3 -#define OCIE1A 4 -#define OCIE1B 5 -#define ICIE1 7 - -#define GTCCR _SFR_IO8(0x27) -#define PSR 0 -#define TSM 7 - -#define TWSD _SFR_IO8(0x28) -#define TWSD0 0 -#define TWSD1 1 -#define TWSD2 2 -#define TWSD3 3 -#define TWSD4 4 -#define TWSD5 5 -#define TWSD6 6 -#define TWSD7 7 - -#define TWSAM _SFR_IO8(0x29) -#define TWAE 0 -#define TWSAM1 1 -#define TWSAM2 2 -#define TWSAM3 3 -#define TWSAM4 4 -#define TWSAM5 5 -#define TWSAM6 6 -#define TWSAM7 7 - -#define TWSA _SFR_IO8(0x2A) -#define TWSA0 0 -#define TWSA1 1 -#define TWSA2 2 -#define TWSA3 3 -#define TWSA4 4 -#define TWSA5 5 -#define TWSA6 6 -#define TWSA7 7 - -#define TWSSRA _SFR_IO8(0x2B) -#define TWAS 0 -#define TWDIR 1 -#define TWBE 2 -#define TWC 3 -#define TWRA 4 -#define TWCH 5 -#define TWASIF 6 -#define TWDIF 7 - -#define TWSCRB _SFR_IO8(0x2C) -#define TWCMD0 0 -#define TWCMD1 1 -#define TWAA 2 - -#define TWSCRA _SFR_IO8(0x2D) -#define TWSME 0 -#define TWPME 1 -#define TWSIE 2 -#define TWEN 3 -#define TWASIE 4 -#define TWDIE 5 -#define TWSHE 7 - -#define SPDR _SFR_IO8(0x2E) -#define SPDR0 0 -#define SPDR1 1 -#define SPDR2 2 -#define SPDR3 3 -#define SPDR4 4 -#define SPDR5 5 -#define SPDR6 6 -#define SPDR7 7 - -#define SPSR _SFR_IO8(0x2F) -#define SPI2X 0 -#define WCOL 6 -#define SPIF 7 - -#define SPCR _SFR_IO8(0x30) -#define SPR0 0 -#define SPR1 1 -#define CPHA 2 -#define CPOL 3 -#define MSTR 4 -#define DORD 5 -#define SPE 6 -#define SPIE 7 - -#define WDTCSR _SFR_IO8(0x31) -#define WDP0 0 -#define WDP1 1 -#define WDP2 2 -#define WDE 3 -#define WDP3 5 -#define WDIE 6 -#define WDIF 7 - -#define NVMCSR _SFR_IO8(0x32) -#define NVMBSY 7 - -#define NVMCMD _SFR_IO8(0x33) -#define NVMCMD0 0 -#define NVMCMD1 1 -#define NVMCMD2 2 -#define NVMCMD3 3 -#define NVMCMD4 4 -#define NVMCMD5 5 - -#define QTCSR _SFR_IO8(0x34) - -#define PRR _SFR_IO8(0x35) -#define PRADC 0 -#define PRTIM0 1 -#define PRTIM1 2 -#define PRSPI 3 -#define PRTWI 4 - -#define __AVR_HAVE_PRR ((1<, never directly. */ - -#ifndef _AVR_IO_H_ -# error "Include instead of this file." -#endif - -#ifndef _AVR_IOXXX_H_ -# define _AVR_IOXXX_H_ "iotn22.h" -#else -# error "Attempt to include more than one file." -#endif - -/* I/O registers */ - -/* Input Pins, Port B */ -#define PINB _SFR_IO8(0x16) - -/* Data Direction Register, Port B */ -#define DDRB _SFR_IO8(0x17) - -/* Data Register, Port B */ -#define PORTB _SFR_IO8(0x18) - -/* EEPROM Control Register */ -#define EECR _SFR_IO8(0x1C) - -/* EEPROM Data Register */ -#define EEDR _SFR_IO8(0x1D) - -/* EEPROM Address Register */ -#define EEAR _SFR_IO8(0x1E) -#define EEARL _SFR_IO8(0x1E) - -/* Watchdog Timer Control Register */ -#define WDTCR _SFR_IO8(0x21) - -/* Timer/Counter 0 */ -#define TCNT0 _SFR_IO8(0x32) - -/* Timer/Counter 0 Control Register */ -#define TCCR0 _SFR_IO8(0x33) - -/* MCU Status Register */ -#define MCUSR _SFR_IO8(0x34) - -/* MCU general Control Register */ -#define MCUCR _SFR_IO8(0x35) - -/* Timer/Counter Interrupt Flag register */ -#define TIFR _SFR_IO8(0x38) - -/* Timer/Counter Interrupt MaSK register */ -#define TIMSK _SFR_IO8(0x39) - -/* General Interrupt Flag register */ -#define GIFR _SFR_IO8(0x3A) - -/* General Interrupt MaSK register */ -#define GIMSK _SFR_IO8(0x3B) - -/* 0x3D SP */ - -/* 0x3F SREG */ - -/* Interrupt vectors */ - -/* External Interrupt 0 */ -#define INT0_vect_num 1 -#define INT0_vect _VECTOR(1) -#define SIG_INTERRUPT0 _VECTOR(1) - -/* Timer/Counter0 Overflow */ -#define TIMER0_OVF0_vect_num 2 -#define TIMER0_OVF0_vect _VECTOR(2) -#define SIG_OVERFLOW0 _VECTOR(2) - -#define _VECTORS_SIZE 6 - -/* - The Register Bit names are represented by their bit number (0-7). - */ - -/* General Interrupt MaSK register */ -#define INT0 6 -#define INTF0 6 - -/* General Interrupt Flag Register */ -#define TOIE0 1 -#define TOV0 1 - -/* MCU general Control Register */ -#define SE 5 -#define SM 4 -#define ISC01 1 -#define ISC00 0 - -/* Timer/Counter 0 Control Register */ -#define CS02 2 -#define CS01 1 -#define CS00 0 - -/* Watchdog Timer Control Register */ -#define WDTOE 4 -#define WDE 3 -#define WDP2 2 -#define WDP1 1 -#define WDP0 0 - -/* - PB2 = SCK/T0 - PB1 = MISO/INT0 - PB0 = MOSI - */ - -/* Data Register, Port B */ -#define PB4 4 -#define PB3 3 -#define PB2 2 -#define PB1 1 -#define PB0 0 - -/* Data Direction Register, Port B */ -#define DDB4 4 -#define DDB3 3 -#define DDB2 2 -#define DDB1 1 -#define DDB0 0 - -/* Input Pins, Port B */ -#define PINB4 4 -#define PINB3 3 -#define PINB2 2 -#define PINB1 1 -#define PINB0 0 - -/* EEPROM Control Register */ -#define EERIE 3 -#define EEMWE 2 -#define EEWE 1 -#define EERE 0 - -/* Constants */ -#define RAMSTART 0x60 -#define RAMEND 0xDF -#define XRAMEND RAMEND -#define E2END 0x7F -#define E2PAGESIZE 0 -#define FLASHEND 0x07FF - - -/* Fuses */ - -#define FUSE_MEMORY_SIZE 1 - -/* Fuse Byte */ -#define FUSE_CKSEL (unsigned char)~_BV(0) -#define FUSE_SPIEN (unsigned char)~_BV(5) -#define FUSE_DEFAULT (FUSE_SPIEN) - - -/* Lock Bits */ -#define __LOCK_BITS_EXIST - - -/* Signature */ -#define SIGNATURE_0 0x1E -#define SIGNATURE_1 0x91 -#define SIGNATURE_2 0x06 - - -/* Deprecated items */ -#if !defined(__AVR_LIBC_DEPRECATED_ENABLE__) - -#pragma GCC system_header - -#pragma GCC poison SIG_INTERRUPT0 -#pragma GCC poison SIG_OVERFLOW0 - -#endif /* !defined(__AVR_LIBC_DEPRECATED_ENABLE__) */ - -#define SLEEP_MODE_IDLE (0x00<<4) -#define SLEEP_MODE_PWR_DOWN (0x01<<4) - -#endif /* _AVR_IOTN22_H_ */ diff --git a/arduino/hardware/tools/avr/avr/include/avr/iotn2313.h b/arduino/hardware/tools/avr/avr/include/avr/iotn2313.h deleted file mode 100644 index 570caf4..0000000 --- a/arduino/hardware/tools/avr/avr/include/avr/iotn2313.h +++ /dev/null @@ -1,702 +0,0 @@ -/* Copyright (c) 2004, 2005, 2006 Bob Paddock - All rights reserved. - - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - * Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - * Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in - the documentation and/or other materials provided with the - distribution. - - * Neither the name of the copyright holders nor the names of - contributors may be used to endorse or promote products derived - from this software without specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. */ - -/* $Id: iotn2313.h 2236 2011-03-17 21:53:39Z arcanum $ */ - -/* iotn2313.h derived from io2313.h by Bob Paddock. - - The changes between the AT90S2313 and the ATtiny2313 are extensive. - - Atmel has renamed several registers, and bits. See Atmel application note - AVR091, as well as the errata at the end of the current ATtiny2313 data - sheet. Some of the names have changed more than once during the sampling - period of the ATtiny2313. - - Where there is no conflict the new and old names are both supported. - - In the case of a new feature in a register, only the new name is used. - This intentionally breaks old code, so that there are no silent bugs. The - source code must be updated to the new name in this case. - - The hardware interrupt vector table has changed from that of the AT90S2313. - - ATtiny2313 programs in page mode rather than the byte mode of the - AT90S2313. Beware of programming the ATtiny2313 as a AT90S2313 device, - when programming the Flash. - - ATtiny2313 has Signature Bytes: 0x1E 0x91 0x0A. - - Changes and/or additions are noted by "ATtiny" in the comments below. */ - -/* avr/iotn2313.h - definitions for ATtiny2313 */ - -#ifndef _AVR_IOTN2313_H_ -#define _AVR_IOTN2313_H_ 1 - -/* This file should only be included from , never directly. */ - -#ifndef _AVR_IO_H_ -# error "Include instead of this file." -#endif - -#ifndef _AVR_IOXXX_H_ -# define _AVR_IOXXX_H_ "iotn2313.h" -#else -# error "Attempt to include more than one file." -#endif - -/* I/O registers */ - -/* - * The Register Bit names are represented by their bit number (0-7). - * Example: PORTB |= _BV(PORTB7); Set MSB of PORTB. - */ - -/* 0x00 Reserved */ - -/* ATtiny Digital Input Disable Register DIDR */ -#define DIDR _SFR_IO8(0x01) - -#define AIN1D 1 -#define AIN0D 0 - -/* ATtiny USART Baud Rate Register High UBBRH[11:8] */ -#define UBRRH _SFR_IO8(0x02) - -/* ATtiny USART Control and Status Register C UCSRC */ -#define UCSRC _SFR_IO8(0x03) - -#define UMSEL 6 -#define UPM1 5 -#define UPM0 4 -#define USBS 3 -#define UCSZ1 2 -#define UCSZ0 1 -#define UCPOL 0 - -/* 0x04 -> 0x07 Reserved */ - -/* ATtiny Analog Comparator Control and Status Register ACSR */ -#define ACSR _SFR_IO8(0x08) - -#define ACD 7 -#define ACBG 6 -#define ACO 5 -#define ACI 4 -#define ACIE 3 -#define ACIC 2 -#define ACIS1 1 -#define ACIS0 0 - -/* USART Baud Rate Register Low UBBRL[7:0] */ -#define UBRRL _SFR_IO8(0x09) - -/* ATtiny USART Control Register UCSRB */ -#define UCSRB _SFR_IO8(0x0A) - -#define RXCIE 7 -#define TXCIE 6 -#define UDRIE 5 -#define RXEN 4 -#define TXEN 3 -#define UCSZ2 2 -#define RXB8 1 -#define TXB8 0 - -/* ATtiny USART Status Register UCSRA */ -#define UCSRA _SFR_IO8(0x0B) - -#define RXC 7 -#define TXC 6 -#define UDRE 5 -#define FE 4 -#define DOR 3 -#define UPE 2 -#define U2X 1 -#define MPCM 0 - -/* USART I/O Data Register UBR or RXB[7:0], TXB[7:0] */ -#define UDR _SFR_IO8(0x0C) -#define RXB _SFR_IO8(0x0C) -#define TXB _SFR_IO8(0x0C) - -/* ATtiny USI Control Register USICR */ -#define USICR _SFR_IO8(0x0D) - -#define USISIE 7 -#define USIOIE 6 -#define USIWM1 5 -#define USIWM0 4 -#define USICS1 3 -#define USICS0 2 -#define USICLK 1 -#define USITC 0 - -/* ATtiny USI Status Register USISR */ -#define USISR _SFR_IO8(0x0E) - -#define USISIF 7 -#define USIOIF 6 -#define USIPF 5 -#define USIDC 4 -#define USICNT3 3 -#define USICNT2 2 -#define USICNT1 1 -#define USICNT0 0 - -/* ATtiny USI Data Register USIDR[7:0] */ -#define USIDR _SFR_IO8(0x0F) - -/* Input Pins, Port D PIND[6:0] */ -#define PIND _SFR_IO8(0x10) - -#define PIND6 6 -#define PIND5 5 -#define PIND4 4 -#define PIND3 3 -#define PIND2 2 -#define PIND1 1 -#define PIND0 0 - -/* Data Direction Register, Port D DDRD[6:0] */ -#define DDRD _SFR_IO8(0x11) - -#define DDD6 6 -#define DDD5 5 -#define DDD4 4 -#define DDD3 3 -#define DDD2 2 -#define DDD1 1 -#define DDD0 0 - -/* Data Register, Port D PORTD[6:0] */ -#define PORTD _SFR_IO8(0x12) - -#define PD6 6 -#define PD5 5 -#define PD4 4 -#define PD3 3 -#define PD2 2 -#define PD1 1 -#define PD0 0 - -/* ATtiny General Purpose I/O Register Zero GPIOR0[7:0] */ -#define GPIOR0 _SFR_IO8(0x13) - -/* ATtiny General Purpose I/O Register One GPIOR1[7:0] */ -#define GPIOR1 _SFR_IO8(0x14) - -/* ATtiny General Purpose I/O Register Two One GPIOR2[7:0] */ -#define GPIOR2 _SFR_IO8(0x15) - -/* Input Pins, Port B PORTB[7:0] */ -#define PINB _SFR_IO8(0x16) - -#define PINB7 7 -#define PINB6 6 -#define PINB5 5 -#define PINB4 4 -#define PINB3 3 -#define PINB2 2 -#define PINB1 1 -#define PINB0 0 - -/* Data Direction Register, Port B PORTB[7:0] */ -#define DDRB _SFR_IO8(0x17) - -#define DDB7 7 -#define DDB6 6 -#define DDB5 5 -#define DDB4 4 -#define DDB3 3 -#define DDB2 2 -#define DDB1 1 -#define DDB0 0 - -/* Data Register, Port B PORTB[7:0] */ -#define PORTB _SFR_IO8(0x18) - -#define PB7 7 -#define PB6 6 -#define PB5 5 -#define PB4 4 -#define PB3 3 -#define PB2 2 -#define PB1 1 -#define PB0 0 - -/* Port A Input Pins Address PINA[2:0] */ -#define PINA _SFR_IO8(0x19) - -#define PINA2 2 -#define PINA1 1 -#define PINA0 0 - -/* Port A Data Direction Register DDRA[2:0] */ -#define DDRA _SFR_IO8(0x1A) - -#define DDRA2 2 -#define DDRA1 1 -#define DDRA0 0 - -/* Port A Data Register PORTA[2:0] */ -#define PORTA _SFR_IO8(0x1B) - -#define PA2 2 -#define PA1 1 -#define PA0 0 - -/* ATtiny EEPROM Control Register EECR */ -#define EECR _SFR_IO8(0x1C) -#define EEPM1 5 -#define EEPM0 4 -#define EERIE 3 -#define EEMPE 2 -#define EEPE 1 -#define EERE 0 - -/* EEPROM Data Register */ -#define EEDR _SFR_IO8(0x1D) - -/* The EEPROM Address Register EEAR[6:0] */ -#define EEAR _SFR_IO8(0x1E) -#define EEARL _SFR_IO8(0x1E) -#define EEAR6 6 -#define EEAR5 5 -#define EEAR4 4 -#define EEAR3 3 -#define EEAR2 2 -#define EEAR1 1 -#define EEAR0 0 - -/* 0x1F Reserved */ - -/* ATtiny Pin Change Mask Register PCMSK PCINT[7:0] */ -#define PCMSK _SFR_IO8(0x20) - -#define PCINT7 7 -#define PCINT6 6 -#define PCINT5 5 -#define PCINT4 4 -#define PCINT3 3 -#define PCINT2 2 -#define PCINT1 1 -#define PCINT0 0 - -/* ATtiny Watchdog Timer Control Register WDTCSR */ -#define WDTCSR _SFR_IO8(0x21) - -#define WDIF 7 -#define WDIE 6 -#define WDP3 5 -#define WDCE 4 -#define WDE 3 -#define WDP2 2 -#define WDP1 1 -#define WDP0 0 - -/* ATtiny Timer/Counter1 Control Register C TCCR1C */ -#define TCCR1C _SFR_IO8(0x22) - -#define FOC1A 7 -#define FOC1B 6 - -/* General Timer/Counter Control Register GTCCR */ -#define GTCCR _SFR_IO8(0x23) - -#define PSR10 0 - -/* T/C 1 Input Capture Register ICR1[15:0] */ -#define ICR1 _SFR_IO16(0x24) -#define ICR1L _SFR_IO8(0x24) -#define ICR1H _SFR_IO8(0x25) - -/* ATtiny Clock Prescale Register */ -#define CLKPR _SFR_IO8(0x26) - -#define CLKPCE 7 -#define CLKPS3 3 -#define CLKPS2 2 -#define CLKPS1 1 -#define CLKPS0 0 - -/* 0x27 Reserved */ - -/* ATtiny Output Compare Register 1 B OCR1B[15:0] */ -#define OCR1B _SFR_IO16(0x28) -#define OCR1BL _SFR_IO8(0x28) -#define OCR1BH _SFR_IO8(0x29) - -/* Output Compare Register 1 OCR1A[15:0] */ -#define OCR1 _SFR_IO16(0x2A) -#define OCR1L _SFR_IO8(0x2A) -#define OCR1H _SFR_IO8(0x2B) -#define OCR1A _SFR_IO16(0x2A) -#define OCR1AL _SFR_IO8(0x2A) -#define OCR1AH _SFR_IO8(0x2B) - -/* Timer/Counter 1 TCNT1[15:0] */ -#define TCNT1 _SFR_IO16(0x2C) -#define TCNT1L _SFR_IO8(0x2C) -#define TCNT1H _SFR_IO8(0x2D) - -/* ATtiny Timer/Counter 1 Control and Status Register TCCR1B */ -#define TCCR1B _SFR_IO8(0x2E) - -#define ICNC1 7 -#define ICES1 6 -#define WGM13 4 -#define WGM12 3 /* Was CTC1 in AT90S2313 */ -#define CS12 2 -#define CS11 1 -#define CS10 0 - -/* ATtiny Timer/Counter 1 Control Register TCCR1A */ -#define TCCR1A _SFR_IO8(0x2F) - -#define COM1A1 7 -#define COM1A0 6 -#define COM1B1 5 -#define COM1B0 4 -#define WGM11 1 /* Was PWM11 in AT90S2313 */ -#define WGM10 0 /* Was PWM10 in AT90S2313 */ - -/* ATtiny Timer/Counter Control Register A TCCR0A */ -#define TCCR0A _SFR_IO8(0x30) - -#define COM0A1 7 -#define COM0A0 6 -#define COM0B1 5 -#define COM0B0 4 -#define WGM01 1 -#define WGM00 0 - -/* ATtiny Oscillator Calibration Register OSCCAL[6:0] */ -#define OSCCAL _SFR_IO8(0x31) - -#define CAL6 6 -#define CAL5 5 -#define CAL4 4 -#define CAL3 3 -#define CAL2 2 -#define CAL1 1 -#define CAL0 0 - -/* Timer/Counter 0 TCNT0[7:0] */ -#define TCNT0 _SFR_IO8(0x32) - -/* ATtiny Timer/Counter 0 Control Register TCCR0B */ -#define TCCR0B _SFR_IO8(0x33) - -#define FOC0A 7 -#define FOC0B 6 -#define WGM02 3 -#define CS02 2 -#define CS01 1 -#define CS00 0 - -/* ATtiny MCU Status Register MCUSR */ -#define MCUSR _SFR_IO8(0x34) - -#define WDRF 3 -#define BORF 2 -#define EXTRF 1 -#define PORF 0 - -/* ATtiny MCU general Control Register MCUCR */ -#define MCUCR _SFR_IO8(0x35) - -#define PUD 7 -#define SM1 6 -#define SE 5 -#define SM0 4 /* Some preliminary ATtiny2313 data sheets incorrectly refer - to this bit as SMD; was SM in AT90S2313. */ -#define ISC11 3 -#define ISC10 2 -#define ISC01 1 -#define ISC00 0 - -/* ATtiny Output Compare Register A OCR0A[7:0] */ -#define OCR0A _SFR_IO8(0x36) - -/* ATtiny Store Program Memory Control and Status Register SPMCSR */ -#define SPMCSR _SFR_IO8(0x37) - -#define CTPB 4 -#define RFLB 3 -#define PGWRT 2 -#define PGERS 1 -#define SPMEN 0 /* The name is used in ATtiny2313.xml file. */ -#define SELFPRGEN 0 /* The name is used in datasheet. */ -#define SELFPRGE 0 /* The name is left for compatibility. */ - -/* ATtiny Timer/Counter Interrupt Flag register TIFR */ -#define TIFR _SFR_IO8(0x38) - -#define TOV1 7 -#define OCF1A 6 -#define OCF1B 5 -#define ICF1 3 -#define OCF0B 2 -#define TOV0 1 -#define OCF0A 0 - -/* ATtiny Timer/Counter Interrupt MaSK register TIMSK */ -#define TIMSK _SFR_IO8(0x39) - -#define TOIE1 7 -#define OCIE1A 6 -#define OCIE1B 5 -#define ICIE1 3 -#define OCIE0B 2 -#define TOIE0 1 -#define OCIE0A 0 - -/* ATtiny External Interrupt Flag Register EIFR, was GIFR */ -#define EIFR _SFR_IO8(0x3A) - -#define INTF1 7 -#define INTF0 6 -#define PCIF 5 - -/* ATtiny General Interrupt MaSK register GIMSK */ -#define GIMSK _SFR_IO8(0x3B) - -#define INT1 7 -#define INT0 6 -#define PCIE 5 - -/* ATtiny Output Compare Register B OCR0B[7:0] */ -#define OCR0B _SFR_IO8(0x3C) - -/* Interrupt vectors: */ - -/* External Interrupt Request 0 */ -#define INT0_vect_num 1 -#define INT0_vect _VECTOR(1) -#define SIG_INTERRUPT0 _VECTOR(1) -#define SIG_INT0 _VECTOR(1) - -/* External Interrupt Request 1 */ -#define INT1_vect_num 2 -#define INT1_vect _VECTOR(2) -#define SIG_INTERRUPT1 _VECTOR(2) -#define SIG_INT1 _VECTOR(2) - -/* Timer/Counter1 Capture Event */ -#define TIMER1_CAPT_vect_num 3 -#define TIMER1_CAPT_vect _VECTOR(3) -#define SIG_INPUT_CAPTURE1 _VECTOR(3) -#define SIG_TIMER1_CAPT _VECTOR(3) - -/* Timer/Counter1 Compare Match A */ -#define TIMER1_COMPA_vect_num 4 -#define TIMER1_COMPA_vect _VECTOR(4) -#define SIG_OUTPUT_COMPARE1A _VECTOR(4) -#define SIG_TIMER1_COMPA _VECTOR(4) - -/* Timer/Counter1 Overflow */ -#define TIMER1_OVF_vect_num 5 -#define TIMER1_OVF_vect _VECTOR(5) -#define SIG_OVERFLOW1 _VECTOR(5) -#define SIG_TIMER1_OVF _VECTOR(5) - -/* Timer/Counter0 Overflow */ -#define TIMER0_OVF_vect_num 6 -#define TIMER0_OVF_vect _VECTOR(6) -#define SIG_OVERFLOW0 _VECTOR(6) -#define SIG_TIMER0_OVF _VECTOR(6) - -/* USART, Rx Complete */ -#define USART_RX_vect_num 7 -#define USART_RX_vect _VECTOR(7) -#define SIG_USART0_RECV _VECTOR(7) -#define SIG_USART0_RX _VECTOR(7) - -/* USART Data Register Empty */ -#define USART_UDRE_vect_num 8 -#define USART_UDRE_vect _VECTOR(8) -#define SIG_USART0_DATA _VECTOR(8) -#define SIG_USART0_UDRE _VECTOR(8) - -/* USART, Tx Complete */ -#define USART_TX_vect_num 9 -#define USART_TX_vect _VECTOR(9) -#define SIG_USART0_TRANS _VECTOR(9) -#define SIG_USART0_TX _VECTOR(9) - -/* Analog Comparator */ -#define ANA_COMP_vect_num 10 -#define ANA_COMP_vect _VECTOR(10) -#define SIG_COMPARATOR _VECTOR(10) -#define SIG_ANALOG_COMP _VECTOR(10) - -#define PCINT_vect_num 11 -#define PCINT_vect _VECTOR(11) -#define SIG_PIN_CHANGE _VECTOR(11) -#define SIG_PCINT _VECTOR(11) - -#define TIMER1_COMPB_vect_num 12 -#define TIMER1_COMPB_vect _VECTOR(12) -#define SIG_OUTPUT_COMPARE1B _VECTOR(12) -#define SIG_TIMER1_COMPB _VECTOR(12) - -#define TIMER0_COMPA_vect_num 13 -#define TIMER0_COMPA_vect _VECTOR(13) -#define SIG_OUTPUT_COMPARE0A _VECTOR(13) -#define SIG_TIMER0_COMPA _VECTOR(13) - -#define TIMER0_COMPB_vect_num 14 -#define TIMER0_COMPB_vect _VECTOR(14) -#define SIG_OUTPUT_COMPARE0B _VECTOR(14) -#define SIG_TIMER0_COMPB _VECTOR(14) - -/* USI Start Condition */ -#define USI_START_vect_num 15 -#define USI_START_vect _VECTOR(15) -#define SIG_USI_START _VECTOR(15) - -/* USI Overflow */ -#define USI_OVERFLOW_vect_num 16 -#define USI_OVERFLOW_vect _VECTOR(16) -#define SIG_USI_OVERFLOW _VECTOR(16) - -#define EEPROM_READY_vect_num 17 -#define EEPROM_READY_vect _VECTOR(17) -#define SIG_EEPROM_READY _VECTOR(17) -#define SIG_EE_READY _VECTOR(17) - -/* Watchdog Timer Overflow */ -#define WDT_OVERFLOW_vect_num 18 -#define WDT_OVERFLOW_vect _VECTOR(18) -#define SIG_WATCHDOG_TIMEOUT _VECTOR(18) -#define SIG_WDT_OVERFLOW _VECTOR(18) - -/* 38 = (18*2)+2: Number of vectors times two, plus the reset vector */ -#define _VECTORS_SIZE 38 - -/* Constants */ -#define SPM_PAGESIZE 32 -#define RAMSTART (0x60) -#define RAMEND 0xDF -#define XRAMEND RAMEND -#define E2END 0x7F -#define E2PAGESIZE 4 -#define FLASHEND 0x07FF - - -/* Fuses */ -#define FUSE_MEMORY_SIZE 3 - -/* Low Fuse Byte */ -#define FUSE_CKSEL0 (unsigned char)~_BV(0) -#define FUSE_CKSEL1 (unsigned char)~_BV(1) -#define FUSE_CKSEL2 (unsigned char)~_BV(2) -#define FUSE_CKSEL3 (unsigned char)~_BV(3) -#define FUSE_SUT0 (unsigned char)~_BV(4) -#define FUSE_SUT1 (unsigned char)~_BV(5) -#define FUSE_CKOUT (unsigned char)~_BV(6) -#define FUSE_CKDIV8 (unsigned char)~_BV(7) -#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL1 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8) - -/* High Fuse Byte */ -#define FUSE_RSTDISBL (unsigned char)~_BV(0) -#define FUSE_BODLEVEL0 (unsigned char)~_BV(1) -#define FUSE_BODLEVEL1 (unsigned char)~_BV(2) -#define FUSE_BODLEVEL2 (unsigned char)~_BV(3) -#define FUSE_WDTON (unsigned char)~_BV(4) -#define FUSE_SPIEN (unsigned char)~_BV(5) -#define FUSE_EESAVE (unsigned char)~_BV(6) -#define FUSE_DWEN (unsigned char)~_BV(7) -#define HFUSE_DEFAULT (FUSE_SPIEN) - -/* Extended Fuse Byte */ -#define FUSE_SELFPRGEN (unsigned char)~_BV(0) -#define EFUSE_DEFAULT (0xFF) - - -/* Lock Bits */ -#define __LOCK_BITS_EXIST - - -/* Signature */ -#define SIGNATURE_0 0x1E -#define SIGNATURE_1 0x91 -#define SIGNATURE_2 0x0A - - -/* Deprecated items */ -#if !defined(__AVR_LIBC_DEPRECATED_ENABLE__) - -#pragma GCC system_header - -#pragma GCC poison SIG_INTERRUPT0 -#pragma GCC poison SIG_INT0 -#pragma GCC poison SIG_INTERRUPT1 -#pragma GCC poison SIG_INT1 -#pragma GCC poison SIG_INPUT_CAPTURE1 -#pragma GCC poison SIG_TIMER1_CAPT -#pragma GCC poison SIG_OUTPUT_COMPARE1A -#pragma GCC poison SIG_TIMER1_COMPA -#pragma GCC poison SIG_OVERFLOW1 -#pragma GCC poison SIG_TIMER1_OVF -#pragma GCC poison SIG_OVERFLOW0 -#pragma GCC poison SIG_TIMER0_OVF -#pragma GCC poison SIG_USART0_RECV -#pragma GCC poison SIG_USART0_RX -#pragma GCC poison SIG_USART0_DATA -#pragma GCC poison SIG_USART0_UDRE -#pragma GCC poison SIG_USART0_TRANS -#pragma GCC poison SIG_USART0_TX -#pragma GCC poison SIG_COMPARATOR -#pragma GCC poison SIG_ANALOG_COMP -#pragma GCC poison SIG_PIN_CHANGE -#pragma GCC poison SIG_PCINT -#pragma GCC poison SIG_OUTPUT_COMPARE1B -#pragma GCC poison SIG_TIMER1_COMPB -#pragma GCC poison SIG_OUTPUT_COMPARE0A -#pragma GCC poison SIG_TIMER0_COMPA -#pragma GCC poison SIG_OUTPUT_COMPARE0B -#pragma GCC poison SIG_TIMER0_COMPB -#pragma GCC poison SIG_USI_START -#pragma GCC poison SIG_USI_OVERFLOW -#pragma GCC poison SIG_EEPROM_READY -#pragma GCC poison SIG_EE_READY -#pragma GCC poison SIG_WATCHDOG_TIMEOUT -#pragma GCC poison SIG_WDT_OVERFLOW - -#endif /* !defined(__AVR_LIBC_DEPRECATED_ENABLE__) */ - - -#define SLEEP_MODE_IDLE (0x00<<4) -#define SLEEP_MODE_STANDBY (0x04<<4) -#define SLEEP_MODE_PWR_DOWN (0x05<<4) - -#endif /* _AVR_IOTN2313_H_ */ diff --git a/arduino/hardware/tools/avr/avr/include/avr/iotn2313a.h b/arduino/hardware/tools/avr/avr/include/avr/iotn2313a.h deleted file mode 100644 index ea991cf..0000000 --- a/arduino/hardware/tools/avr/avr/include/avr/iotn2313a.h +++ /dev/null @@ -1,812 +0,0 @@ -/* Copyright (c) 2009 Atmel Corporation - All rights reserved. - - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - * Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - * Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in - the documentation and/or other materials provided with the - distribution. - - * Neither the name of the copyright holders nor the names of - contributors may be used to endorse or promote products derived - from this software without specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. */ - -/* $Id: iotn2313a.h 2412 2014-03-20 11:21:20Z pitchumani $ */ - -/* avr/iotn2313a.h - definitions for ATtiny2313A */ - -/* This file should only be included from , never directly. */ - -#ifndef _AVR_IO_H_ -# error "Include instead of this file." -#endif - -#ifndef _AVR_IOXXX_H_ -# define _AVR_IOXXX_H_ "iotn2313a.h" -#else -# error "Attempt to include more than one file." -#endif - - -#ifndef _AVR_ATtiny2313A_H_ -#define _AVR_ATtiny2313A_H_ 1 - - -/* Registers and associated bit numbers. */ - -#define USIBR _SFR_IO8(0x000) -#define USIBR0 0 -#define USIBR1 1 -#define USIBR2 2 -#define USIBR3 3 -#define USIBR4 4 -#define USIBR5 5 -#define USIBR6 6 -#define USIBR7 7 - -#define DIDR _SFR_IO8(0x001) -#define AIN0D 0 -#define AIN1D 1 - -#define UBRRH _SFR_IO8(0x002) -#define UBRR8 0 -#define UBRR9 1 -#define UBRR10 2 -#define UBRR11 3 - -#define UCSRC _SFR_IO8(0x003) -#define UCPOL 0 -#define UCSZ0 1 -#define UCSZ1 2 -#define USBS 3 -#define UPM0 4 -#define UPM1 5 -#define UMSEL0 6 -#define UMSEL1 7 - -/* When in MSPIM mode */ -#define UCPHA 1 -#define UDORD 2 - -#define PCMSK1 _SFR_IO8(0x004) -#define PCINT8 0 -#define PCINT9 1 -#define PCINT10 2 - -#define PCMSK2 _SFR_IO8(0x005) -#define PCINT11 0 -#define PCINT12 1 -#define PCINT13 2 -#define PCINT14 3 -#define PCINT15 4 -#define PCINT16 5 -#define PCINT17 6 - -#define PRR _SFR_IO8(0x006) -#define PRUSART 0 -#define PRUSI 1 -#define PRTIM0 2 -#define PRTIM1 3 - -#define __AVR_HAVE_PRR ((1< - -#define SPM_PAGESIZE 32 -#define RAMSTART (0x60) -#define RAMEND 0xDF -#define XRAMEND RAMEND -#define E2END 0x7F -#define E2PAGESIZE 4 -#define FLASHEND 0x7FF - - -/* Fuses */ - -#define FUSE_MEMORY_SIZE 3 - -/* Low Fuse Byte */ -#define FUSE_CKSEL0 (unsigned char)~_BV(0) -#define FUSE_CKSEL1 (unsigned char)~_BV(1) -#define FUSE_CKSEL2 (unsigned char)~_BV(2) -#define FUSE_CKSEL3 (unsigned char)~_BV(3) -#define FUSE_SUT0 (unsigned char)~_BV(4) -#define FUSE_SUT1 (unsigned char)~_BV(5) -#define FUSE_CKOUT (unsigned char)~_BV(6) -#define FUSE_CKDIV8 (unsigned char)~_BV(7) -#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8) - -/* High Fuse Byte */ -#define FUSE_BODLEVEL0 (unsigned char)~_BV(0) -#define FUSE_BODLEVEL1 (unsigned char)~_BV(1) -#define FUSE_BODLEVEL2 (unsigned char)~_BV(2) -#define FUSE_EESAVE (unsigned char)~_BV(3) -#define FUSE_WDTON (unsigned char)~_BV(4) -#define FUSE_SPIEN (unsigned char)~_BV(5) -#define FUSE_DWEN (unsigned char)~_BV(6) -#define FUSE_RSTDISBL (unsigned char)~_BV(7) -#define HFUSE_DEFAULT (FUSE_SPIEN) - -/* Extended Fuse Byte */ -#define FUSE_SELFPRGEN (unsigned char)~_BV(0) -#define EFUSE_DEFAULT (0xFF) - - -/* Lock Bits */ -#define __LOCK_BITS_EXIST - - -/* Signature */ -#define SIGNATURE_0 0x1E -#define SIGNATURE_1 0x91 -#define SIGNATURE_2 0x0B - -#define SLEEP_MODE_IDLE (0x00<<3) -#define SLEEP_MODE_ADC (0x01<<3) -#define SLEEP_MODE_PWR_DOWN (0x02<<3) -#define SLEEP_MODE_STANDBY (0x03<<3) - -#endif /* _AVR_IOTN24_H_ */ diff --git a/arduino/hardware/tools/avr/avr/include/avr/iotn24a.h b/arduino/hardware/tools/avr/avr/include/avr/iotn24a.h deleted file mode 100644 index 35d5277..0000000 --- a/arduino/hardware/tools/avr/avr/include/avr/iotn24a.h +++ /dev/null @@ -1,846 +0,0 @@ -/* Copyright (c) 2009 Atmel Corporation - All rights reserved. - - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - * Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - * Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in - the documentation and/or other materials provided with the - distribution. - - * Neither the name of the copyright holders nor the names of - contributors may be used to endorse or promote products derived - from this software without specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. */ - -/* $Id: iotn24a.h 2414 2014-03-21 16:04:00Z pitchumani $ */ - -/* avr/iotn24a.h - definitions for ATtiny24A */ - -/* This file should only be included from , never directly. */ - -#ifndef _AVR_IO_H_ -# error "Include instead of this file." -#endif - -#ifndef _AVR_IOXXX_H_ -# define _AVR_IOXXX_H_ "iotn24a.h" -#else -# error "Attempt to include more than one file." -#endif - - -#ifndef _AVR_ATtiny24A_H_ -#define _AVR_ATtiny24A_H_ 1 - - -/* Registers and associated bit numbers. */ - -#define PRR _SFR_IO8(0x00) -#define PRADC 0 -#define PRUSI 1 -#define PRTIM0 2 -#define PRTIM1 3 - -#define __AVR_HAVE_PRR ((1< - -#define SPM_PAGESIZE 32 -#define RAMSTART (0x60) -#define RAMEND 0xDF -#define XRAMEND RAMEND -#define E2END 0x7F -#define E2PAGESIZE 4 -#define FLASHEND 0x7FF - - -/* Fuses */ - -#define FUSE_MEMORY_SIZE 3 - -/* Low Fuse Byte */ -#define FUSE_CKSEL0 (unsigned char)~_BV(0) -#define FUSE_CKSEL1 (unsigned char)~_BV(1) -#define FUSE_CKSEL2 (unsigned char)~_BV(2) -#define FUSE_CKSEL3 (unsigned char)~_BV(3) -#define FUSE_SUT0 (unsigned char)~_BV(4) -#define FUSE_SUT1 (unsigned char)~_BV(5) -#define FUSE_CKOUT (unsigned char)~_BV(6) -#define FUSE_CKDIV8 (unsigned char)~_BV(7) -#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8) - -/* High Fuse Byte */ -#define FUSE_BODLEVEL0 (unsigned char)~_BV(0) -#define FUSE_BODLEVEL1 (unsigned char)~_BV(1) -#define FUSE_BODLEVEL2 (unsigned char)~_BV(2) -#define FUSE_EESAVE (unsigned char)~_BV(3) -#define FUSE_WDTON (unsigned char)~_BV(4) -#define FUSE_SPIEN (unsigned char)~_BV(5) -#define FUSE_DWEN (unsigned char)~_BV(6) -#define FUSE_RSTDISBL (unsigned char)~_BV(7) -#define HFUSE_DEFAULT (FUSE_SPIEN) - -/* Extended Fuse Byte */ -#define FUSE_SELFPRGEN (unsigned char)~_BV(0) -#define EFUSE_DEFAULT (0xFF) - - -/* Lock Bits */ -#define __LOCK_BITS_EXIST - - -/* Signature */ -#define SIGNATURE_0 0x1E -#define SIGNATURE_1 0x91 -#define SIGNATURE_2 0x08 - -#define SLEEP_MODE_IDLE (0x00<<3) -#define SLEEP_MODE_ADC (0x01<<3) -#define SLEEP_MODE_PWR_DOWN (0x02<<3) - -#endif /* _AVR_IOTN25_H_ */ diff --git a/arduino/hardware/tools/avr/avr/include/avr/iotn26.h b/arduino/hardware/tools/avr/avr/include/avr/iotn26.h deleted file mode 100644 index e0d81a3..0000000 --- a/arduino/hardware/tools/avr/avr/include/avr/iotn26.h +++ /dev/null @@ -1,422 +0,0 @@ -/* Copyright (c) 2004,2005 Eric B. Weddington - All rights reserved. - - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - * Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - * Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in - the documentation and/or other materials provided with the - distribution. - - * Neither the name of the copyright holders nor the names of - contributors may be used to endorse or promote products derived - from this software without specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. */ - -/* $Id: iotn26.h 2236 2011-03-17 21:53:39Z arcanum $ */ - -/* avr/iotn26.h - definitions for ATtiny26 */ - -/* This file should only be included from , never directly. */ - -#ifndef _AVR_IO_H_ -# error "Include instead of this file." -#endif - -#ifndef _AVR_IOXXX_H_ -# define _AVR_IOXXX_H_ "iotn26.h" -#else -# error "Attempt to include more than one file." -#endif - -#ifndef _AVR_IOTN26_H_ -#define _AVR_IOTN26_H_ 1 - -/* Registers and associated bit numbers */ - -/* Reserved [0x00..0x03] */ - -#define ADCW _SFR_IO16(0x04) -#ifndef __ASSEMBLER__ -#define ADC _SFR_IO16(0x04) -#endif - -#define ADCL _SFR_IO8(0x04) -#define ADCH _SFR_IO8(0x05) - -#define ADCSR _SFR_IO8(0x06) -#define ADPS0 0 -#define ADPS1 1 -#define ADPS2 2 -#define ADIE 3 -#define ADIF 4 -#define ADFR 5 -#define ADSC 6 -#define ADEN 7 - -#define ADMUX _SFR_IO8(0x07) -#define MUX0 0 -#define MUX1 1 -#define MUX2 2 -#define MUX3 3 -#define MUX4 4 -#define ADLAR 5 -#define REFS0 6 -#define REFS1 7 - -#define ACSR _SFR_IO8(0x08) -#define ACIS0 0 -#define ACIS1 1 -#define ACME 2 -#define ACIE 3 -#define ACI 4 -#define ACO 5 -#define ACBG 6 -#define ACD 7 - -/* Reserved [0x09..0x0C] */ - -#define USICR _SFR_IO8(0x0D) -#define USITC 0 -#define USICLK 1 -#define USICS0 2 -#define USICS1 3 -#define USIWM0 4 -#define USIWM1 5 -#define USIOIE 6 -#define USISIE 7 - -#define USISR _SFR_IO8(0x0E) -#define USICNT0 0 -#define USICNT1 1 -#define USICNT2 2 -#define USICNT3 3 -#define USIDC 4 -#define USIPF 5 -#define USIOIF 6 -#define USISIF 7 - -#define USIDR _SFR_IO8(0x0F) - -/* Reserved [0x10..0x15] */ - - -#define PINB _SFR_IO8(0x16) -#define PINB0 0 -#define PINB1 1 -#define PINB2 2 -#define PINB3 3 -#define PINB4 4 -#define PINB5 5 -#define PINB6 6 -#define PINB7 7 - -#define DDRB _SFR_IO8(0x17) -#define DDB0 0 -#define DDB1 1 -#define DDB2 2 -#define DDB3 3 -#define DDB4 4 -#define DDB5 5 -#define DDB6 6 -#define DDB7 7 - -#define PORTB _SFR_IO8(0x18) -#define PB0 0 -#define PB1 1 -#define PB2 2 -#define PB3 3 -#define PB4 4 -#define PB5 5 -#define PB6 6 -#define PB7 7 - -#define PINA _SFR_IO8(0x19) -#define PINA0 0 -#define PINA1 1 -#define PINA2 2 -#define PINA3 3 -#define PINA4 4 -#define PINA5 5 -#define PINA6 6 -#define PINA7 7 - -#define DDRA _SFR_IO8(0x1A) -#define DDA0 0 -#define DDA1 1 -#define DDA2 2 -#define DDA3 3 -#define DDA4 4 -#define DDA5 5 -#define DDA6 6 -#define DDA7 7 - -#define PORTA _SFR_IO8(0x1B) -#define PA0 0 -#define PA1 1 -#define PA2 2 -#define PA3 3 -#define PA4 4 -#define PA5 5 -#define PA6 6 -#define PA7 7 - -/* EEPROM Control Register */ -#define EECR _SFR_IO8(0x1C) -#define EERE 0 -#define EEWE 1 -#define EEMWE 2 -#define EERIE 3 - -/* EEPROM Data Register */ -#define EEDR _SFR_IO8(0x1D) - -/* EEPROM Address Register */ -#define EEAR _SFR_IO8(0x1E) -#define EEARL _SFR_IO8(0x1E) - -/* Reserved [0x1F..0x20] */ - -#define WDTCR _SFR_IO8(0x21) -#define WDP0 0 -#define WDP1 1 -#define WDP2 2 -#define WDE 3 -#define WDCE 4 - -/* Reserved [0x22..0x28] */ - -#define PLLCSR _SFR_IO8(0x29) -#define PLOCK 0 -#define PLLE 1 -#define PCKE 2 - -/* Reserved [0x2A] */ - -#define OCR1C _SFR_IO8(0x2B) - -#define OCR1B _SFR_IO8(0x2C) - -#define OCR1A _SFR_IO8(0x2D) - -#define TCNT1 _SFR_IO8(0x2E) - -#define TCCR1B _SFR_IO8(0x2F) -#define CS10 0 -#define CS11 1 -#define CS12 2 -#define CS13 3 -#define PSR1 6 -#define CTC1 7 - -#define TCCR1A _SFR_IO8(0x30) -#define PWM1B 0 -#define PWM1A 1 -#define FOC1B 2 -#define FOC1A 3 -#define COM1B0 4 -#define COM1B1 5 -#define COM1A0 6 -#define COM1A1 7 - -#define OSCCAL _SFR_IO8(0x31) - -#define TCNT0 _SFR_IO8(0x32) - -#define TCCR0 _SFR_IO8(0x33) -#define CS00 0 -#define CS01 1 -#define CS02 2 -#define PSR0 3 - -#define MCUSR _SFR_IO8(0x34) -#define PORF 0 -#define EXTRF 1 -#define BORF 2 -#define WDRF 3 - -#define MCUCR _SFR_IO8(0x35) -#define ISC00 0 -#define ISC01 1 -#define SM0 3 -#define SM1 4 -#define SE 5 -#define PUD 6 - -/* Reserved [0x36..0x37] */ - -#define TIFR _SFR_IO8(0x38) -#define TOV0 1 -#define TOV1 2 -#define OCF1B 5 -#define OCF1A 6 - -#define TIMSK _SFR_IO8(0x39) -#define TOIE0 1 -#define TOIE1 2 -#define OCIE1B 5 -#define OCIE1A 6 - -#define GIFR _SFR_IO8(0x3A) -#define PCIF 5 -#define INTF0 6 - -#define GIMSK _SFR_IO8(0x3B) -#define PCIE0 4 -#define PCIE1 5 -#define INT0 6 - -/* Reserved [0x3C] */ - -/* SP [0x3D] */ - -/* Reserved [0x3E] */ - -/* SREG [0x3F] */ - - -/* Interrupt vectors */ -/* Interrupt vector 0 is the reset vector. */ -/* External Interrupt 0 */ -#define INT0_vect_num 1 -#define INT0_vect _VECTOR(1) -#define SIG_INTERRUPT0 _VECTOR(1) - -/* External Interrupt Request 0 */ -#define IO_PINS_vect_num 2 -#define IO_PINS_vect _VECTOR(2) -#define SIG_PIN_CHANGE _VECTOR(2) - -/* Timer/Counter1 Compare Match 1A */ -#define TIMER1_CMPA_vect_num 3 -#define TIMER1_CMPA_vect _VECTOR(3) -#define SIG_OUTPUT_COMPARE1A _VECTOR(3) - -/* Timer/Counter1 Compare Match 1B */ -#define TIMER1_CMPB_vect_num 4 -#define TIMER1_CMPB_vect _VECTOR(4) -#define SIG_OUTPUT_COMPARE1B _VECTOR(4) - -/* Timer/Counter1 Overflow */ -#define TIMER1_OVF1_vect_num 5 -#define TIMER1_OVF1_vect _VECTOR(5) -#define SIG_OVERFLOW1 _VECTOR(5) - -/* Timer/Counter0 Overflow */ -#define TIMER0_OVF0_vect_num 6 -#define TIMER0_OVF0_vect _VECTOR(6) -#define SIG_OVERFLOW0 _VECTOR(6) - -/* USI Start */ -#define USI_STRT_vect_num 7 -#define USI_STRT_vect _VECTOR(7) -#define SIG_USI_START _VECTOR(7) - -/* USI Overflow */ -#define USI_OVF_vect_num 8 -#define USI_OVF_vect _VECTOR(8) -#define SIG_USI_OVERFLOW _VECTOR(8) - -/* EEPROM Ready */ -#define EE_RDY_vect_num 9 -#define EE_RDY_vect _VECTOR(9) -#define SIG_EEPROM_READY _VECTOR(9) - -/* Analog Comparator */ -#define ANA_COMP_vect_num 10 -#define ANA_COMP_vect _VECTOR(10) -#define SIG_ANA_COMP _VECTOR(10) -#define SIG_COMPARATOR _VECTOR(10) - -/* ADC Conversion Complete */ -#define ADC_vect_num 11 -#define ADC_vect _VECTOR(11) -#define SIG_ADC _VECTOR(11) - -#define _VECTORS_SIZE 24 - - -/* Constants */ -#define RAMSTART 0x60 -#define RAMEND 0xDF -#define XRAMEND RAMEND -#define E2END 0x7F -#define E2PAGESIZE 4 -#define FLASHEND 0x07FF - - -/* Fuses */ - -#define FUSE_MEMORY_SIZE 2 - -/* Low Fuse Byte */ -#define FUSE_CKSEL0 (unsigned char)~_BV(0) -#define FUSE_CKSEL1 (unsigned char)~_BV(1) -#define FUSE_CKSEL2 (unsigned char)~_BV(2) -#define FUSE_CKSEL3 (unsigned char)~_BV(3) -#define FUSE_SUT0 (unsigned char)~_BV(4) -#define FUSE_SUT1 (unsigned char)~_BV(5) -#define FUSE_CKOPT (unsigned char)~_BV(6) -#define FUSE_PLLCK (unsigned char)~_BV(7) -#define LFUSE_DEFAULT (FUSE_CKSEL1 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0) - -/* High Fuse Byte */ -#define FUSE_BODEN (unsigned char)~_BV(0) -#define FUSE_BODLEVEL (unsigned char)~_BV(1) -#define FUSE_EESAVE (unsigned char)~_BV(2) -#define FUSE_SPIEN (unsigned char)~_BV(3) -#define FUSE_RSTDISBL (unsigned char)~_BV(4) -#define HFUSE_DEFAULT (FUSE_SPIEN) - - -/* Lock Bits */ -#define __LOCK_BITS_EXIST - - -/* Signature */ -#define SIGNATURE_0 0x1E -#define SIGNATURE_1 0x91 -#define SIGNATURE_2 0x09 - - -/* Deprecated items */ -#if !defined(__AVR_LIBC_DEPRECATED_ENABLE__) - -#pragma GCC system_header - -#pragma GCC poison SIG_INTERRUPT0 -#pragma GCC poison SIG_PIN_CHANGE -#pragma GCC poison SIG_OUTPUT_COMPARE1A -#pragma GCC poison SIG_OUTPUT_COMPARE1B -#pragma GCC poison SIG_OVERFLOW1 -#pragma GCC poison SIG_OVERFLOW0 -#pragma GCC poison SIG_USI_START -#pragma GCC poison SIG_USI_OVERFLOW -#pragma GCC poison SIG_EEPROM_READY -#pragma GCC poison SIG_ANA_COMP -#pragma GCC poison SIG_COMPARATOR -#pragma GCC poison SIG_ADC - -#endif /* !defined(__AVR_LIBC_DEPRECATED_ENABLE__) */ - -#define SLEEP_MODE_IDLE (0x00<<3) -#define SLEEP_MODE_ADC (0x01<<3) -#define SLEEP_MODE_PWR_DOWN (0x02<<3) -#define SLEEP_MODE_STANDBY (0x03<<3) - -#endif /* _AVR_IOTN26_H_ */ diff --git a/arduino/hardware/tools/avr/avr/include/avr/iotn261.h b/arduino/hardware/tools/avr/avr/include/avr/iotn261.h deleted file mode 100644 index 0bce89d..0000000 --- a/arduino/hardware/tools/avr/avr/include/avr/iotn261.h +++ /dev/null @@ -1,93 +0,0 @@ -/* Copyright (c) 2006, Anatoly Sokolov - All rights reserved. - - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - * Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - * Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in - the documentation and/or other materials provided with the - distribution. - - * Neither the name of the copyright holders nor the names of - contributors may be used to endorse or promote products derived - from this software without specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. */ - -/* $Id: iotn261.h 2115 2010-04-05 23:19:53Z arcanum $ */ - -/* avr/iotn261.h - definitions for ATtiny261 */ - -#ifndef _AVR_IOTN261_H_ -#define _AVR_IOTN261_H_ 1 - -#include - -#define SPM_PAGESIZE 32 -#define RAMSTART (0x60) -#define RAMEND 0xDF -#define XRAMEND RAMEND -#define E2END 0x7F -#define E2PAGESIZE 4 -#define FLASHEND 0x7FF - -/* Fuses */ - -#define FUSE_MEMORY_SIZE 3 - -/* Low Fuse Byte */ -#define FUSE_CKSEL0 (unsigned char)~_BV(0) -#define FUSE_CKSEL1 (unsigned char)~_BV(1) -#define FUSE_CKSEL2 (unsigned char)~_BV(2) -#define FUSE_CKSEL3 (unsigned char)~_BV(3) -#define FUSE_SUT0 (unsigned char)~_BV(4) -#define FUSE_SUT1 (unsigned char)~_BV(5) -#define FUSE_CKOUT (unsigned char)~_BV(6) -#define FUSE_CKDIV8 (unsigned char)~_BV(7) -#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8) - -/* High Fuse Byte */ -#define FUSE_BODLEVEL0 (unsigned char)~_BV(0) -#define FUSE_BODLEVEL1 (unsigned char)~_BV(1) -#define FUSE_BODLEVEL2 (unsigned char)~_BV(2) -#define FUSE_EESAVE (unsigned char)~_BV(3) -#define FUSE_WDTON (unsigned char)~_BV(4) -#define FUSE_SPIEN (unsigned char)~_BV(5) -#define FUSE_DWEN (unsigned char)~_BV(6) -#define FUSE_RSTDISBL (unsigned char)~_BV(7) -#define HFUSE_DEFAULT (FUSE_SPIEN) - -/* Extended Fuse Byte */ -#define FUSE_SELFPRGEN (unsigned char)~_BV(0) -#define EFUSE_DEFAULT (0xFF) - - -/* Lock Bits */ -#define __LOCK_BITS_EXIST - - -/* Signature */ -#define SIGNATURE_0 0x1E -#define SIGNATURE_1 0x91 -#define SIGNATURE_2 0x0C - -#define SLEEP_MODE_IDLE (0x00<<3) -#define SLEEP_MODE_ADC (0x01<<3) -#define SLEEP_MODE_PWR_DOWN (0x02<<3) -#define SLEEP_MODE_STANDBY (0x03<<3) - -#endif /* _AVR_IOTN261_H_ */ diff --git a/arduino/hardware/tools/avr/avr/include/avr/iotn261a.h b/arduino/hardware/tools/avr/avr/include/avr/iotn261a.h deleted file mode 100644 index f4a7fa0..0000000 --- a/arduino/hardware/tools/avr/avr/include/avr/iotn261a.h +++ /dev/null @@ -1,987 +0,0 @@ -/* Copyright (c) 2009 Atmel Corporation - All rights reserved. - - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - * Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - * Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in - the documentation and/or other materials provided with the - distribution. - - * Neither the name of the copyright holders nor the names of - contributors may be used to endorse or promote products derived - from this software without specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. */ - -/* $Id: iotn261a.h 2063 2009-11-18 22:06:28Z arcanum $ */ - -/* avr/iotn261a.h - definitions for ATtiny261A */ - -/* This file should only be included from , never directly. */ - -#ifndef _AVR_IO_H_ -# error "Include instead of this file." -#endif - -#ifndef _AVR_IOXXX_H_ -# define _AVR_IOXXX_H_ "iotn261a.h" -#else -# error "Attempt to include more than one file." -#endif - - -#ifndef _AVR_ATtiny261A_H_ -#define _AVR_ATtiny261A_H_ 1 - - -/* Registers and associated bit numbers. */ - -#define TCCR1E _SFR_IO8(0x00) -#define OC1OE0 0 -#define OC1OE1 1 -#define OC1OE2 2 -#define OC1OE3 3 -#define OC1OE4 4 -#define OC1OE5 5 - -#define DIDR0 _SFR_IO8(0x01) -#define ADC0D 0 -#define ADC1D 1 -#define ADC2D 2 -#define AREFD 3 -#define ADC3D 4 -#define ADC4D 5 -#define ADC5D 6 -#define ADC6D 7 - -#define DIDR1 _SFR_IO8(0x02) -#define ADC7D 4 -#define ADC8D 5 -#define ADC9D 6 -#define ADC10D 7 - -#define ADCSRB _SFR_IO8(0x03) -#define ADTS0 0 -#define ADTS1 1 -#define ADTS2 2 -#define MUX5 3 -#define REFS2 4 -#define IPR 5 -#define GSEL 6 -#define BIN 7 - -#ifndef __ASSEMBLER__ -#define ADC _SFR_IO16(0x04) -#endif -#define ADCW _SFR_IO16(0x04) - -#define ADCL _SFR_IO8(0x04) -#define ADCL0 0 -#define ADCL1 1 -#define ADCL2 2 -#define ADCL3 3 -#define ADCL4 4 -#define ADCL5 5 -#define ADCL6 6 -#define ADCL7 7 - -#define ADCH _SFR_IO8(0x05) -#define ADCH0 0 -#define ADCH1 1 -#define ADCH2 2 -#define ADCH3 3 -#define ADCH4 4 -#define ADCH5 5 -#define ADCH6 6 -#define ADCH7 7 - -#define ADCSRA _SFR_IO8(0x06) -#define ADPS0 0 -#define ADPS1 1 -#define ADPS2 2 -#define ADIE 3 -#define ADIF 4 -#define ADATE 5 -#define ADSC 6 -#define ADEN 7 - -#define ADMUX _SFR_IO8(0x07) -#define MUX0 0 -#define MUX1 1 -#define MUX2 2 -#define MUX3 3 -#define MUX4 4 -#define ADLAR 5 -#define REFS0 6 -#define REFS1 7 - -#define ACSRA _SFR_IO8(0x08) -#define ACIS0 0 -#define ACIS1 1 -#define ACME 2 -#define ACIE 3 -#define ACI 4 -#define ACO 5 -#define ACBG 6 -#define ACD 7 - -#define ACSRB _SFR_IO8(0x09) -#define ACM0 0 -#define ACM1 1 -#define ACM2 2 -#define HLEV 6 -#define HSEL 7 - -#define GPIOR0 _SFR_IO8(0x0A) -#define GPIOR00 0 -#define GPIOR01 1 -#define GPIOR02 2 -#define GPIOR03 3 -#define GPIOR04 4 -#define GPIOR05 5 -#define GPIOR06 6 -#define GPIOR07 7 - -#define GPIOR1 _SFR_IO8(0x0B) -#define GPIOR10 0 -#define GPIOR11 1 -#define GPIOR12 2 -#define GPIOR13 3 -#define GPIOR14 4 -#define GPIOR15 5 -#define GPIOR16 6 -#define GPIOR17 7 - -#define GPIOR2 _SFR_IO8(0x0C) -#define GPIOR20 0 -#define GPIOR21 1 -#define GPIOR22 2 -#define GPIOR23 3 -#define GPIOR24 4 -#define GPIOR25 5 -#define GPIOR26 6 -#define GPIOR27 7 - -#define USICR _SFR_IO8(0x0D) -#define USITC 0 -#define USICLK 1 -#define USICS0 2 -#define USICS1 3 -#define USIWM0 4 -#define USIWM1 5 -#define USIOIE 6 -#define USISIE 7 - -#define USISR _SFR_IO8(0x0E) -#define USICNT0 0 -#define USICNT1 1 -#define USICNT2 2 -#define USICNT3 3 -#define USIDC 4 -#define USIPF 5 -#define USIOIF 6 -#define USISIF 7 - -#define USIDR _SFR_IO8(0x0F) -#define USIDR0 0 -#define USIDR1 1 -#define USIDR2 2 -#define USIDR3 3 -#define USIDR4 4 -#define USIDR5 5 -#define USIDR6 6 -#define USIDR7 7 - -#define USIBR _SFR_IO8(0x10) -#define USIBR0 0 -#define USIBR1 1 -#define USIBR2 2 -#define USIBR3 3 -#define USIBR4 4 -#define USIBR5 5 -#define USIBR6 6 -#define USIBR7 7 - -#define USIPP _SFR_IO8(0x11) -#define USIPOS 0 - -#define OCR0B _SFR_IO8(0x12) -#define OCR0B_0 0 -#define OCR0B_1 1 -#define OCR0B_2 2 -#define OCR0B_3 3 -#define OCR0B_4 4 -#define OCR0B_5 5 -#define OCR0B_6 6 -#define OCR0B_7 7 - -#define OCR0A _SFR_IO8(0x13) -#define OCR0A_0 0 -#define OCR0A_1 1 -#define OCR0A_2 2 -#define OCR0A_3 3 -#define OCR0A_4 4 -#define OCR0A_5 5 -#define OCR0A_6 6 -#define OCR0A_7 7 - -#define TCNT0H _SFR_IO8(0x14) -#define TCNT0H_0 0 -#define TCNT0H_1 1 -#define TCNT0H_2 2 -#define TCNT0H_3 3 -#define TCNT0H_4 4 -#define TCNT0H_5 5 -#define TCNT0H_6 6 -#define TCNT0H_7 7 - -#define TCCR0A _SFR_IO8(0x15) -#define WGM00 0 -#define ACIC0 3 -#define ICES0 4 -#define ICNC0 5 -#define ICEN0 6 -#define TCW0 7 - -#define PINB _SFR_IO8(0x16) -#define PINB0 0 -#define PINB1 1 -#define PINB2 2 -#define PINB3 3 -#define PINB4 4 -#define PINB5 5 -#define PINB6 6 -#define PINB7 7 - -#define DDRB _SFR_IO8(0x17) -#define DDB0 0 -#define DDB1 1 -#define DDB2 2 -#define DDB3 3 -#define DDB4 4 -#define DDB5 5 -#define DDB6 6 -#define DDB7 7 - -#define PORTB _SFR_IO8(0x18) -#define PORTB0 0 -#define PORTB1 1 -#define PORTB2 2 -#define PORTB3 3 -#define PORTB4 4 -#define PORTB5 5 -#define PORTB6 6 -#define PORTB7 7 - -#define PINA _SFR_IO8(0x19) -#define PINA0 0 -#define PINA1 1 -#define PINA2 2 -#define PINA3 3 -#define PINA4 4 -#define PINA5 5 -#define PINA6 6 -#define PINA7 7 - -#define DDRA _SFR_IO8(0x1A) -#define DDA0 0 -#define DDA1 1 -#define DDA2 2 -#define DDA3 3 -#define DDA4 4 -#define DDA5 5 -#define DDA6 6 -#define DDA7 7 - -#define PORTA _SFR_IO8(0x1B) -#define PORTA0 0 -#define PORTA1 1 -#define PORTA2 2 -#define PORTA3 3 -#define PORTA4 4 -#define PORTA5 5 -#define PORTA6 6 -#define PORTA7 7 - -#define EECR _SFR_IO8(0x1C) -#define EERE 0 -#define EEPE 1 -#define EEMPE 2 -#define EERIE 3 -#define EEPM0 4 -#define EEPM1 5 - -#define EEDR _SFR_IO8(0x1D) -#define EEDR0 0 -#define EEDR1 1 -#define EEDR2 2 -#define EEDR3 3 -#define EEDR4 4 -#define EEDR5 5 -#define EEDR6 6 -#define EEDR7 7 - -#define EEAR _SFR_IO16(0x1E) - -#define EEARL _SFR_IO8(0x1E) -#define EEAR0 0 -#define EEAR1 1 -#define EEAR2 2 -#define EEAR3 3 -#define EEAR4 4 -#define EEAR5 5 -#define EEAR6 6 -#define EEAR7 7 - -#define EEARH _SFR_IO8(0x1F) -#define EEAR8 0 - -#define DWDR _SFR_IO8(0x20) -#define DWDR0 0 -#define DWDR1 1 -#define DWDR2 2 -#define DWDR3 3 -#define DWDR4 4 -#define DWDR5 5 -#define DWDR6 6 -#define DWDR7 7 - -#define WDTCR _SFR_IO8(0x21) -#define WDP0 0 -#define WDP1 1 -#define WDP2 2 -#define WDE 3 -#define WDCE 4 -#define WDP3 5 -#define WDIE 6 -#define WDIF 7 - -#define PCMSK1 _SFR_IO8(0x22) -#define PCINT8 0 -#define PCINT9 1 -#define PCINT10 2 -#define PCINT11 3 -#define PCINT12 4 -#define PCINT13 5 -#define PCINT14 6 -#define PCINT15 7 - -#define PCMSK0 _SFR_IO8(0x23) -#define PCINT0 0 -#define PCINT1 1 -#define PCINT2 2 -#define PCINT3 3 -#define PCINT4 4 -#define PCINT5 5 -#define PCINT6 6 -#define PCINT7 7 - -#define DT1 _SFR_IO8(0x24) -#define DT1L0 0 -#define DT1L1 1 -#define DT1L2 2 -#define DT1L3 3 -#define DT1H0 4 -#define DT1H1 5 -#define DT1H2 6 -#define DT1H3 7 - -#define TC1H _SFR_IO8(0x25) -#define TC18 0 -#define TC19 1 - -#define TCCR1D _SFR_IO8(0x26) -#define WGM10 0 -#define WGM11 1 -#define FPF1 2 -#define FPAC1 3 -#define FPES1 4 -#define FPNC1 5 -#define FPEN1 6 -#define FPIE1 7 - -#define TCCR1C _SFR_IO8(0x27) -#define PWM1D 0 -#define FOC1D 1 -#define COM1D0 2 -#define COM1D1 3 -#define COM1B0S 4 -#define COM1B1S 5 -#define COM1A0S 6 -#define COM1A1S 7 - -#define CLKPR _SFR_IO8(0x28) -#define CLKPS0 0 -#define CLKPS1 1 -#define CLKPS2 2 -#define CLKPS3 3 -#define CLKPCE 7 - -#define PLLCSR _SFR_IO8(0x29) -#define PLOCK 0 -#define PLLE 1 -#define PCKE 2 -#define LSM 7 - -#define OCR1D _SFR_IO8(0x2A) -#define OCR1D0 0 -#define OCR1D1 1 -#define OCR1D2 2 -#define OCR1D3 3 -#define OCR1D4 4 -#define OCR1D5 5 -#define OCR1D6 6 -#define OCR1D7 7 - -#define OCR1C _SFR_IO8(0x2B) -#define OCR1C0 0 -#define OCR1C1 1 -#define OCR1C2 2 -#define OCR1C3 3 -#define OCR1C4 4 -#define OCR1C5 5 -#define OCR1C6 6 -#define OCR1C7 7 - -#define OCR1B _SFR_IO8(0x2C) -#define OCR1B0 0 -#define OCR1B1 1 -#define OCR1B2 2 -#define OCR1B3 3 -#define OCR1B4 4 -#define OCR1B5 5 -#define OCR1B6 6 -#define OCR1B7 7 - -#define OCR1A _SFR_IO8(0x2D) -#define OCR1A0 0 -#define OCR1A1 1 -#define OCR1A2 2 -#define OCR1A3 3 -#define OCR1A4 4 -#define OCR1A5 5 -#define OCR1A6 6 -#define OCR1A7 7 - -#define TCNT1 _SFR_IO8(0x2E) -#define TC1H_0 0 -#define TC1H_1 1 -#define TC1H_2 2 -#define TC1H_3 3 -#define TC1H_4 4 -#define TC1H_5 5 -#define TC1H_6 6 -#define TC1H_7 7 - -#define TCCR1B _SFR_IO8(0x2F) -#define CS10 0 -#define CS11 1 -#define CS12 2 -#define CS13 3 -#define DTPS10 4 -#define DTPS11 5 -#define PSR1 6 - -#define TCCR1A _SFR_IO8(0x30) -#define PWM1B 0 -#define PWM1A 1 -#define FOC1B 2 -#define FOC1A 3 -#define COM1B0 4 -#define COM1B1 5 -#define COM1A0 6 -#define COM1A1 7 - -#define OSCCAL _SFR_IO8(0x31) -#define CAL0 0 -#define CAL1 1 -#define CAL2 2 -#define CAL3 3 -#define CAL4 4 -#define CAL5 5 -#define CAL6 6 -#define CAL7 7 - -#define TCNT0L _SFR_IO8(0x32) -#define TCNT0L_0 0 -#define TCNT0L_1 1 -#define TCNT0L_2 2 -#define TCNT0L_3 3 -#define TCNT0L_4 4 -#define TCNT0L_5 5 -#define TCNT0L_6 6 -#define TCNT0L_7 7 - -#define TCCR0B _SFR_IO8(0x33) -#define CS00 0 -#define CS01 1 -#define CS02 2 -#define PSR0 3 -#define TSM 4 - -#define MCUSR _SFR_IO8(0x34) -#define PORF 0 -#define EXTRF 1 -#define BORF 2 -#define WDRF 3 - -#define MCUCR _SFR_IO8(0x35) -#define ISC00 0 -#define ISC01 1 -#define BODSE 2 -#define SM0 3 -#define SM1 4 -#define SE 5 -#define PUD 6 -#define BODS 7 - -#define PRR _SFR_IO8(0x36) -#define PRADC 0 -#define PRUSI 1 -#define PRTIM0 2 -#define PRTIM1 3 - -#define __AVR_HAVE_PRR ((1<, never directly. */ - -#ifndef _AVR_IO_H_ -# error "Include instead of this file." -#endif - -#ifndef _AVR_IOXXX_H_ -# define _AVR_IOXXX_H_ "iotn28.h" -#else -# error "Attempt to include more than one file." -#endif - -#ifndef __ASSEMBLER__ -# warning "MCU not supported by the C compiler" -#endif - -/* I/O registers */ - -#define OSCCAL _SFR_IO8(0x00) - -#define WDTCR _SFR_IO8(0x01) - -#define MODCR _SFR_IO8(0x02) - -#define TCNT0 _SFR_IO8(0x03) -#define TCCR0 _SFR_IO8(0x04) - -#define IFR _SFR_IO8(0x05) -#define ICR _SFR_IO8(0x06) - -#define MCUCS _SFR_IO8(0x07) - -#define ACSR _SFR_IO8(0x08) - -/* 0x09..0x0F reserved */ - -#define PIND _SFR_IO8(0x10) -#define DDRD _SFR_IO8(0x11) -#define PORTD _SFR_IO8(0x12) - -/* 0x13..0x15 reserved */ - -#define PINB _SFR_IO8(0x16) - -/* 0x17..0x18 reserved */ - -#define PINA _SFR_IO8(0x19) -#define PACR _SFR_IO8(0x1A) -#define PORTA _SFR_IO8(0x1B) - -/* 0x1C..0x3E reserved */ - -/* 0x3F SREG */ - -/* Interrupt vectors */ - -/* External Interrupt 0 */ -#define INT0_vect_num 1 -#define INT0_vect _VECTOR(1) -#define SIG_INTERRUPT0 _VECTOR(1) - -/* External Interrupt 1 */ -#define INT1_vect_num 2 -#define INT1_vect _VECTOR(2) -#define SIG_INTERRUPT1 _VECTOR(2) - -/* Low-level Input on Port B */ -#define LOWLEVEL_IO_PINS_vect_num 3 -#define LOWLEVEL_IO_PINS_vect _VECTOR(3) -#define SIG_PIN _VECTOR(3) - -/* Timer/Counter0 Overflow */ -#define TIMER0_OVF_vect_num 4 -#define TIMER0_OVF_vect _VECTOR(4) -#define SIG_OVERFLOW0 _VECTOR(4) - -/* Analog Comparator */ -#define ANA_COMP_vect_num 5 -#define ANA_COMP_vect _VECTOR(5) -#define SIG_COMPARATOR _VECTOR(5) - -#define _VECTORS_SIZE 12 - - -/* Bit numbers */ - -/* ICR */ -#define INT1 7 -#define INT0 6 -#define LLIE 5 -#define TOIE0 4 -#define ISC11 3 -#define ISC10 2 -#define ISC01 1 -#define ISC00 - -/* IFR */ -#define INTF1 7 -#define INTF0 6 -#define TOV0 4 - -/* MCUCS */ -#define PLUPB 7 -#define SE 5 -#define SM 4 -#define WDRF 3 -#define EXTRF 1 -#define PORF 0 - -/* TCCR0 */ -#define FOV0 7 -#define OOM01 4 -#define OOM00 3 -#define CS02 2 -#define CS01 1 -#define CS00 0 - -/* MODCR */ -#define ONTIM4 7 -#define ONTIM3 6 -#define ONTIM2 5 -#define ONTIM1 4 -#define ONTIM0 3 -#define MCONF2 2 -#define MCONF1 1 -#define MCONF0 0 - -/* WDTCR */ -#define WDTOE 4 -#define WDE 3 -#define WDP2 2 -#define WDP1 1 -#define WDP0 0 - -/* - PA2 = IR - */ - -/* PORTA */ -#define PA3 3 -#define PA2 2 -#define PA1 1 -#define PA0 0 - -/* PACR */ -#define DDA3 3 -#define PA2HC 2 -#define DDA1 1 -#define DDA0 0 - -/* PINA */ -#define PINA3 3 -#define PINA1 1 -#define PINA0 0 - -/* - PB4 = INT1 - PB3 = INT0 - PB2 = T0 - PB1 = AIN1 - PB0 = AIN0 - */ - -/* PINB */ -#define PINB7 7 -#define PINB6 6 -#define PINB5 5 -#define PINB4 4 -#define PINB3 3 -#define PINB2 2 -#define PINB1 1 -#define PINB0 0 - -/* PORTD */ -#define PD7 7 -#define PD6 6 -#define PD5 5 -#define PD4 4 -#define PD3 3 -#define PD2 2 -#define PD1 1 -#define PD0 0 - -/* DDRD */ -#define DDD7 7 -#define DDD6 6 -#define DDD5 5 -#define DDD4 4 -#define DDD3 3 -#define DDD2 2 -#define DDD1 1 -#define DDD0 0 - -/* PIND */ -#define PIND7 7 -#define PIND6 6 -#define PIND5 5 -#define PIND4 4 -#define PIND3 3 -#define PIND2 2 -#define PIND1 1 -#define PIND0 0 - -/* ACSR */ -#define ACD 7 -#define ACO 5 -#define ACI 4 -#define ACIE 3 -#define ACIS1 1 -#define ACIS0 0 - -#define RAMSTART 0x60 -/* Last memory addresses */ -#define RAMEND 0x1F -#define XRAMEND 0x0 -#define E2END 0x0 -#define E2PAGESIZE 0 -#define FLASHEND 0x7FF - - -/* Fuses */ - -#define FUSE_MEMORY_SIZE 1 - -/* Fuse Byte */ -#define FUSE_CKSEL0 (unsigned char)~_BV(0) -#define FUSE_CKSEL1 (unsigned char)~_BV(1) -#define FUSE_CKSEL2 (unsigned char)~_BV(2) -#define FUSE_CKSEL3 (unsigned char)~_BV(3) -#define FUSE_INTCAP (unsigned char)~_BV(4) -#define FUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3) - - -/* Lock Bits */ -#define __LOCK_BITS_EXIST - - -/* Signature */ -#define SIGNATURE_0 0x1E -#define SIGNATURE_1 0x91 -#define SIGNATURE_2 0x07 - - -/* Deprecated items */ -#if !defined(__AVR_LIBC_DEPRECATED_ENABLE__) - -#pragma GCC system_header - -#pragma GCC poison SIG_INTERRUPT0 -#pragma GCC poison SIG_INTERRUPT1 -#pragma GCC poison SIG_PIN -#pragma GCC poison SIG_OVERFLOW0 -#pragma GCC poison SIG_COMPARATOR - -#endif /* !defined(__AVR_LIBC_DEPRECATED_ENABLE__) */ - -#define SLEEP_MODE_IDLE (0x00<<4) -#define SLEEP_MODE_PWR_DOWN (0x01<<4) - -#endif /* _AVR_IOTN28_H_ */ diff --git a/arduino/hardware/tools/avr/avr/include/avr/iotn4.h b/arduino/hardware/tools/avr/avr/include/avr/iotn4.h deleted file mode 100644 index 6e2c880..0000000 --- a/arduino/hardware/tools/avr/avr/include/avr/iotn4.h +++ /dev/null @@ -1,477 +0,0 @@ -/* Copyright (c) 2009 Atmel Corporation - All rights reserved. - - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - * Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - * Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in - the documentation and/or other materials provided with the - distribution. - - * Neither the name of the copyright holders nor the names of - contributors may be used to endorse or promote products derived - from this software without specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. */ - -/* $Id: iotn4.h 2063 2009-11-18 22:06:28Z arcanum $ */ - -/* avr/iotn4.h - definitions for ATtiny4 */ - -/* This file should only be included from , never directly. */ - -#ifndef _AVR_IO_H_ -# error "Include instead of this file." -#endif - -#ifndef _AVR_IOXXX_H_ -# define _AVR_IOXXX_H_ "iotn4.h" -#else -# error "Attempt to include more than one file." -#endif - - -#ifndef _AVR_ATtiny4_H_ -#define _AVR_ATtiny4_H_ 1 - - -/* Registers and associated bit numbers. */ - -#define PINB _SFR_IO8(0x00) -#define PINB0 0 -#define PINB1 1 -#define PINB2 2 -#define PINB3 3 - -#define DDRB _SFR_IO8(0x01) -#define DDB0 0 -#define DDB1 1 -#define DDB2 2 -#define DDB3 3 - -#define PORTB _SFR_IO8(0x02) -#define PORTB0 0 -#define PORTB1 1 -#define PORTB2 2 -#define PORTB3 3 - -#define PUEB _SFR_IO8(0x03) -#define PUEB0 0 -#define PUEB1 1 -#define PUEB2 2 -#define PUEB3 3 - -#define PORTCR _SFR_IO8(0x0C) -#define BBMB 1 - -#define PCMSK _SFR_IO8(0x10) -#define PCINT0 0 -#define PCINT1 1 -#define PCINT2 2 -#define PCINT3 3 - -#define PCIFR _SFR_IO8(0x11) -#define PCIF0 0 - -#define PCICR _SFR_IO8(0x12) -#define PCIE0 0 - -#define EIMSK _SFR_IO8(0x13) -#define INT0 0 - -#define EIFR _SFR_IO8(0x14) -#define INTF0 0 - -#define EICRA _SFR_IO8(0x15) -#define ISC00 0 -#define ISC01 1 - -#define DIDR0 _SFR_IO8(0x17) -#define AIN0D 0 -#define AIN1D 1 - -#define ACSR _SFR_IO8(0x1F) -#define ACIS0 0 -#define ACIS1 1 -#define ACIC 2 -#define ACIE 3 -#define ACI 4 -#define ACO 5 -#define ACD 7 - -#define ICR0 _SFR_IO16(0x22) - -#define ICR0L _SFR_IO8(0x22) -#define ICR0_0 0 -#define ICR0_1 1 -#define ICR0_2 2 -#define ICR0_3 3 -#define ICR0_4 4 -#define ICR0_5 5 -#define ICR0_6 6 -#define ICR0_7 7 - -#define ICR0H _SFR_IO8(0x23) -#define ICR0_8 0 -#define ICR0_9 1 -#define ICR0_10 2 -#define ICR0_11 3 -#define ICR0_12 4 -#define ICR0_13 5 -#define ICR0_14 6 -#define ICR0_15 7 - -#define OCR0B _SFR_IO16(0x24) - -#define OCR0BL _SFR_IO8(0x24) -#define OCR0B0 0 -#define OCR0B1 1 -#define OCR0B2 2 -#define OCR0B3 3 -#define OCR0B4 4 -#define OCR0B5 5 -#define OCR0B6 6 -#define OCR0B7 7 - -#define OCR0BH _SFR_IO8(0x25) -#define OCR0B8 0 -#define OCR0B9 1 -#define OCR0B10 2 -#define OCR0B11 3 -#define OCR0B12 4 -#define OCR0B13 5 -#define OCR0B14 6 -#define OCR0B15 7 - -#define OCR0A _SFR_IO16(0x26) - -#define OCR0AL _SFR_IO8(0x26) -#define OCR0A0 0 -#define OCR0A1 1 -#define OCR0A2 2 -#define OCR0A3 3 -#define OCR0A4 4 -#define OCR0A5 5 -#define OCR0A6 6 -#define OCR0A7 7 - -#define OCR0AH _SFR_IO8(0x27) -#define OCR0A8 0 -#define OCR0A9 1 -#define OCR0A10 2 -#define OCR0A11 3 -#define OCR0A12 4 -#define OCR0A13 5 -#define OCR0A14 6 -#define OCR0A15 7 - -#define TCNT0 _SFR_IO16(0x28) - -#define TCNT0L _SFR_IO8(0x28) -#define TCNT0_0 0 -#define TCNT0_1 1 -#define TCNT0_2 2 -#define TCNT0_3 3 -#define TCNT0_4 4 -#define TCNT0_5 5 -#define TCNT0_6 6 -#define TCNT0_7 7 - -#define TCNT0H _SFR_IO8(0x29) -#define TCNT0_8 0 -#define TCNT0_9 1 -#define TCNT0_10 2 -#define TCNT0_11 3 -#define TCNT0_12 4 -#define TCNT0_13 5 -#define TCNT0_14 6 -#define TCNT0_15 7 - -#define TIFR0 _SFR_IO8(0x2A) -#define TOV0 0 -#define OCF0A 1 -#define OCF0B 2 -#define ICF0 5 - -#define TIMSK0 _SFR_IO8(0x2B) -#define TOIE0 0 -#define OCIE0A 1 -#define OCIE0B 2 -#define ICIE0 5 - -#define TCCR0C _SFR_IO8(0x2C) -#define FOC0B 6 -#define FOC0A 7 - -#define TCCR0B _SFR_IO8(0x2D) -#define CS00 0 -#define CS01 1 -#define CS02 2 -#define WGM02 3 -#define WGM03 4 -#define ICES0 6 -#define ICNC0 7 - -#define TCCR0A _SFR_IO8(0x2E) -#define WGM00 0 -#define WGM01 1 -#define COM0B0 4 -#define COM0B1 5 -#define COM0A0 6 -#define COM0A1 7 - -#define GTCCR _SFR_IO8(0x2F) -#define PSR 0 -#define TSM 7 - -#define WDTCSR _SFR_IO8(0x31) -#define WDP0 0 -#define WDP1 1 -#define WDP2 2 -#define WDE 3 -#define WDP3 5 -#define WDIE 6 -#define WDIF 7 - -#define NVMCSR _SFR_IO8(0x32) -#define NVMBSY 7 - -#define NVMCMD _SFR_IO8(0x33) -#define NVMCMD0 0 -#define NVMCMD1 1 -#define NVMCMD2 2 -#define NVMCMD3 3 -#define NVMCMD4 4 -#define NVMCMD5 5 - -#define VLMCSR _SFR_IO8(0x34) -#define VLM0 0 -#define VLM1 1 -#define VLM2 2 -#define VLMIE 6 -#define VLMF 7 - -#define PRR _SFR_IO8(0x35) -#define PRTIM0 0 -#define PRADC 1 - -#define __AVR_HAVE_PRR ((1<, never directly. */ - -#ifndef _AVR_IO_H_ -# error "Include instead of this file." -#endif - -#ifndef _AVR_IOXXX_H_ -# define _AVR_IOXXX_H_ "iotn40.h" -#else -# error "Attempt to include more than one file." -#endif - - -#ifndef _AVR_ATtiny40_H_ -#define _AVR_ATtiny40_H_ 1 - - -/* Registers and associated bit numbers. */ - -#define PINA _SFR_IO8(0x00) -#define PINA0 0 -#define PINA1 1 -#define PINA2 2 -#define PINA3 3 -#define PINA4 4 -#define PINA5 5 -#define PINA6 6 -#define PINA7 7 - -#define DDRA _SFR_IO8(0x01) -#define DDA0 0 -#define DDA1 1 -#define DDA2 2 -#define DDA3 3 -#define DDA4 4 -#define DDA5 5 -#define DDA6 6 -#define DDA7 7 - -#define PORTA _SFR_IO8(0x02) -#define PORTA0 0 -#define PORTA1 1 -#define PORTA2 2 -#define PORTA3 3 -#define PORTA4 4 -#define PORTA5 5 -#define PORTA6 6 -#define PORTA7 7 - -#define PUEA _SFR_IO8(0x03) -#define PUEA0 0 -#define PUEA1 1 -#define PUEA2 2 -#define PUEA3 3 -#define PUEA4 4 -#define PUEA5 5 -#define PUEA6 6 -#define PUEA7 7 - -#define PINB _SFR_IO8(0x04) -#define PINB0 0 -#define PINB1 1 -#define PINB2 2 -#define PINB3 3 - -#define DDRB _SFR_IO8(0x05) -#define DDB0 0 -#define DDB1 1 -#define DDB2 2 -#define DDB3 3 - -#define PORTB _SFR_IO8(0x06) -#define PORTB0 0 -#define PORTB1 1 -#define PORTB2 2 -#define PORTB3 3 - -#define PUEB _SFR_IO8(0x07) -#define PUEB0 0 -#define PUEB1 1 -#define PUEB2 2 -#define PUEB3 3 - -#define PORTCR _SFR_IO8(0x08) -#define BBMA 0 -#define BBMB 1 -#define BBMC 2 -#define ADC8D 4 -#define ADC9D 5 -#define ADC10D 6 -#define ADC11D 7 - -#define PCMSK0 _SFR_IO8(0x09) -#define PCINT0 0 -#define PCINT1 1 -#define PCINT2 2 -#define PCINT3 3 -#define PCINT4 4 -#define PCINT5 5 -#define PCINT6 6 -#define PCINT7 7 - -#define PCMSK1 _SFR_IO8(0x0A) -#define PCINT8 0 -#define PCINT9 1 -#define PCINT10 2 -#define PCINT11 3 - -#define GIFR _SFR_IO8(0x0B) -#define INTF0 0 -#define PCIF0 4 -#define PCIF1 5 -#define PCIF2 6 - -#define GIMSK _SFR_IO8(0x0C) -#define INT0 0 -#define PCIE0 4 -#define PCIE1 5 -#define PCIE2 6 - -#define DIDR0 _SFR_IO8(0x0D) -#define ADC0D 0 -#define ADC1D 1 -#define ADC2D 2 -#define ADC3D 3 -#define ADC4D 4 -#define ADC5D 5 -#define ADC6D 6 -#define ADC7D 7 - -#ifndef __ASSEMBLER__ -#define ADC _SFR_IO16(0x0E) -#endif -#define ADCW _SFR_IO16(0x0E) - -#define ADCL _SFR_IO8(0x0E) -#define ADCL0 0 -#define ADCL1 1 -#define ADCL2 2 -#define ADCL3 3 -#define ADCL4 4 -#define ADCL5 5 -#define ADCL6 6 -#define ADCL7 7 - -#define ADCH _SFR_IO8(0x0F) -#define ADCH0 0 -#define ADCH1 1 -#define ADCH2 2 -#define ADCH3 3 -#define ADCH4 4 -#define ADCH5 5 -#define ADCH6 6 -#define ADCH7 7 - -#define ADMUX _SFR_IO8(0x10) -#define MUX0 0 -#define MUX1 1 -#define MUX2 2 -#define MUX3 3 -#define REFS 6 - -#define ADCSRB _SFR_IO8(0x11) -#define ADTS0 0 -#define ADTS1 1 -#define ADTS2 2 -#define ADLAR 3 - -#define ADCSRA _SFR_IO8(0x12) -#define ADPS0 0 -#define ADPS1 1 -#define ADPS2 2 -#define ADIE 3 -#define ADIF 4 -#define ADATE 5 -#define ADSC 6 -#define ADEN 7 - -#define ACSRB _SFR_IO8(0x13) -#define ACME 2 -#define HLEV 6 -#define HSEL 7 - -#define ACSRA _SFR_IO8(0x14) -#define ACIS0 0 -#define ACIS1 1 -#define ACIC 2 -#define ACIE 3 -#define ACI 4 -#define ACO 5 -#define ACBG 6 -#define ACD 7 - -#define OCR0B _SFR_IO8(0x15) -#define OCR0B_0 0 -#define OCR0B_1 1 -#define OCR0B_2 2 -#define OCR0B_3 3 -#define OCR0B_4 4 -#define OCR0B_5 5 -#define OCR0B_6 6 -#define OCR0B_7 7 - -#define OCR0A _SFR_IO8(0x16) -#define OCR0_0 0 -#define OCR0_1 1 -#define OCR0_2 2 -#define OCR0_3 3 -#define OCR0_4 4 -#define OCR0_5 5 -#define OCR0_6 6 -#define OCR0_7 7 - -#define TCNT0 _SFR_IO8(0x17) -#define TCNT0_0 0 -#define TCNT0_1 1 -#define TCNT0_2 2 -#define TCNT0_3 3 -#define TCNT0_4 4 -#define TCNT0_5 5 -#define TCNT0_6 6 -#define TCNT0_7 7 - -#define TCCR0B _SFR_IO8(0x18) -#define CS00 0 -#define CS01 1 -#define CS02 2 -#define WGM02 3 -#define PSR 4 -#define TSM 5 -#define FOC0B 6 -#define FOC0A 7 - -#define TCCR0A _SFR_IO8(0x19) -#define WGM00 0 -#define WGM01 1 -#define COM0B0 4 -#define COM0B1 5 -#define COM0A0 6 -#define COM0A1 7 - -#define PCMSK2 _SFR_IO8(0x1A) -#define PCINT12 0 -#define PCINT13 1 -#define PCINT14 2 -#define PCINT15 3 -#define PCINT16 4 -#define PCINT17 5 - -#define PINC _SFR_IO8(0x1B) -#define PINC0 0 -#define PINC1 1 -#define PINC2 2 -#define PINC3 3 -#define PINC4 4 -#define PINC5 5 - -#define DDRC _SFR_IO8(0x1C) -#define DDC0 0 -#define DDC1 1 -#define DDC2 2 -#define DDC3 3 -#define DDC4 4 -#define DDC5 5 - -#define PORTC _SFR_IO8(0x1D) -#define PORTC0 0 -#define PORTC1 1 -#define PORTC2 2 -#define PORTC3 3 -#define PORTC4 4 -#define PORTC5 5 - -#define PUEC _SFR_IO8(0x1E) -#define PUEC0 0 -#define PUEC1 1 -#define PUEC2 2 -#define PUEC3 3 -#define PUEC4 4 -#define PUEC5 5 - -#define RAMDR _SFR_IO8(0x1F) -#define RAMDR0 0 -#define RAMDR1 1 -#define RAMDR2 2 -#define RAMDR3 3 -#define RAMDR4 4 -#define RAMDR5 5 -#define RAMDR6 6 -#define RAMDR7 7 - -#define RAMAR _SFR_IO8(0x20) -#define RAMAR0 0 -#define RAMAR1 1 -#define RAMAR2 2 -#define RAMAR3 3 -#define RAMAR4 4 -#define RAMAR5 5 -#define RAMAR6 6 -#define RAMAR7 7 - -#define OCR1B _SFR_IO8(0x21) -#define OCR1B0 0 -#define OCR1B1 1 -#define OCR1B2 2 -#define OCR1B3 3 -#define OCR1B4 4 -#define OCR1B5 5 -#define OCR1B6 6 -#define OCR1B7 7 - -#define OCR1A _SFR_IO8(0x22) -#define OCR1A0 0 -#define OCR1A1 1 -#define OCR1A2 2 -#define OCR1A3 3 -#define OCR1A4 4 -#define OCR1A5 5 -#define OCR1A6 6 -#define OCR1A7 7 - -#define TCNT1L _SFR_IO8(0x23) -#define TCNT1_0 0 -#define TCNT1_1 1 -#define TCNT1_2 2 -#define TCNT1_3 3 -#define TCNT1_4 4 -#define TCNT1_5 5 -#define TCNT1_6 6 -#define TCNT1_7 7 - -#define TCCR1A _SFR_IO8(0x24) -#define CS10 0 -#define CS11 1 -#define CS12 2 -#define CTC1 3 -#define ICES1 4 -#define ICNC1 5 -#define ICEN1 6 -#define TCW1 7 - -#define TIFR _SFR_IO8(0x25) -#define TOV0 0 -#define OCF0A 1 -#define OCF0B 2 -#define TOV1 3 -#define OCF1A 4 -#define OCF1B 5 -#define ICF1 7 - -#define TIMSK _SFR_IO8(0x26) -#define TOIE0 0 -#define OCIE0A 1 -#define OCIE0B 2 -#define TOIE1 3 -#define OCIE1A 4 -#define OCIE1B 5 -#define ICIE1 7 - -#define TCNT1H _SFR_IO8(0x27) -#define TCNT1_8 0 -#define TCNT1_9 1 -#define TCNT1_10 2 -#define TCNT1_11 3 -#define TCNT1_12 4 -#define TCNT1_13 5 -#define TCNT1_14 6 -#define TCNT1_15 7 - -#define TWSD _SFR_IO8(0x28) -#define TWSD0 0 -#define TWSD1 1 -#define TWSD2 2 -#define TWSD3 3 -#define TWSD4 4 -#define TWSD5 5 -#define TWSD6 6 -#define TWSD7 7 - -#define TWSAM _SFR_IO8(0x29) -#define TWAE 0 -#define TWSAM1 1 -#define TWSAM2 2 -#define TWSAM3 3 -#define TWSAM4 4 -#define TWSAM5 5 -#define TWSAM6 6 -#define TWSAM7 7 - -#define TWSA _SFR_IO8(0x2A) -#define TWSA0 0 -#define TWSA1 1 -#define TWSA2 2 -#define TWSA3 3 -#define TWSA4 4 -#define TWSA5 5 -#define TWSA6 6 -#define TWSA7 7 - -#define TWSSRA _SFR_IO8(0x2B) -#define TWAS 0 -#define TWDIR 1 -#define TWBE 2 -#define TWC 3 -#define TWRA 4 -#define TWCH 5 -#define TWASIF 6 -#define TWDIF 7 - -#define TWSCRB _SFR_IO8(0x2C) -#define TWCMD0 0 -#define TWCMD1 1 -#define TWAA 2 - -#define TWSCRA _SFR_IO8(0x2D) -#define TWSME 0 -#define TWPME 1 -#define TWSIE 2 -#define TWEN 3 -#define TWASIE 4 -#define TWDIE 5 -#define TWSHE 7 - -#define SPDR _SFR_IO8(0x2E) - -#define SPSR _SFR_IO8(0x2F) - -#define SPCR _SFR_IO8(0x30) - -#define WDTCSR _SFR_IO8(0x31) -#define WDP0 0 -#define WDP1 1 -#define WDP2 2 -#define WDE 3 -#define WDP3 5 -#define WDIE 6 -#define WDIF 7 - -#define NVMCSR _SFR_IO8(0x32) -#define NVMBSY 7 - -#define NVMCMD _SFR_IO8(0x33) -#define NVMCMD0 0 -#define NVMCMD1 1 -#define NVMCMD2 2 -#define NVMCMD3 3 -#define NVMCMD4 4 -#define NVMCMD5 5 - -#define QTCSR _SFR_IO8(0x34) - -#define PRR _SFR_IO8(0x35) -#define PRADC 0 -#define PRTIM0 1 -#define PRTIM1 2 -#define PRSPI 3 -#define PRTWI 4 - -#define __AVR_HAVE_PRR ((1<, never directly. */ - -#ifndef _AVR_IO_H_ -# error "Include instead of this file." -#endif - -#ifndef _AVR_IOXXX_H_ -# define _AVR_IOXXX_H_ "iotn4313.h" -#else -# error "Attempt to include more than one file." -#endif - - -#ifndef _AVR_ATtiny4313_H_ -#define _AVR_ATtiny4313_H_ 1 - - -/* Registers and associated bit numbers. */ - -#define USIBR _SFR_IO8(0x000) -#define USIBR0 0 -#define USIBR1 1 -#define USIBR2 2 -#define USIBR3 3 -#define USIBR4 4 -#define USIBR5 5 -#define USIBR6 6 -#define USIBR7 7 - -#define DIDR _SFR_IO8(0x001) -#define AIN0D 0 -#define AIN1D 1 - -#define UBRRH _SFR_IO8(0x002) -#define UBRR8 0 -#define UBRR9 1 -#define UBRR10 2 -#define UBRR11 3 - -#define UCSRC _SFR_IO8(0x003) -#define UCPOL 0 -#define UCSZ0 1 -#define UCSZ1 2 -#define USBS 3 -#define UPM0 4 -#define UPM1 5 -#define UMSEL0 6 -#define UMSEL1 7 - -/* When in MSPIM mode */ -#define UCPHA 1 -#define UDORD 2 - -#define PCMSK1 _SFR_IO8(0x004) -#define PCINT8 0 -#define PCINT9 1 -#define PCINT10 2 - -#define PCMSK2 _SFR_IO8(0x005) -#define PCINT11 0 -#define PCINT12 1 -#define PCINT13 2 -#define PCINT14 3 -#define PCINT15 4 -#define PCINT16 5 -#define PCINT17 6 - -#define PRR _SFR_IO8(0x006) -#define PRUSART 0 -#define PRUSI 1 -#define PRTIM0 2 -#define PRTIM1 3 - -#define __AVR_HAVE_PRR ((1<, never directly. */ - -#ifndef _AVR_IO_H_ -# error "Include instead of this file." -#endif - -#ifndef _AVR_IOXXX_H_ -# define _AVR_IOXXX_H_ "iotn43u.h" -#else -# error "Attempt to include more than one file." -#endif - - -#ifndef _AVR_IOTN43U_H_ -#define _AVR_IOTN43U_H_ 1 - -/* Registers and associated bit numbers */ - -#define PRR _SFR_IO8(0x00) -#define PRADC 0 -#define PRUSI 1 -#define PRTIM0 2 -#define PRTIM1 3 - -#define __AVR_HAVE_PRR ((1< - -/* Constants */ -#define SPM_PAGESIZE 64 -#define RAMSTART (0x60) -#define RAMEND 0x15F -#define XRAMEND RAMEND -#define E2END 0xFF -#define E2PAGESIZE 4 -#define FLASHEND 0xFFF - - -/* Fuses */ -#define FUSE_MEMORY_SIZE 3 - -/* Low Fuse Byte */ -#define FUSE_CKSEL0 (unsigned char)~_BV(0) -#define FUSE_CKSEL1 (unsigned char)~_BV(1) -#define FUSE_CKSEL2 (unsigned char)~_BV(2) -#define FUSE_CKSEL3 (unsigned char)~_BV(3) -#define FUSE_SUT0 (unsigned char)~_BV(4) -#define FUSE_SUT1 (unsigned char)~_BV(5) -#define FUSE_CKOUT (unsigned char)~_BV(6) -#define FUSE_CKDIV8 (unsigned char)~_BV(7) -#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8) - -/* High Fuse Byte */ -#define FUSE_BODLEVEL0 (unsigned char)~_BV(0) -#define FUSE_BODLEVEL1 (unsigned char)~_BV(1) -#define FUSE_BODLEVEL2 (unsigned char)~_BV(2) -#define FUSE_EESAVE (unsigned char)~_BV(3) -#define FUSE_WDTON (unsigned char)~_BV(4) -#define FUSE_SPIEN (unsigned char)~_BV(5) -#define FUSE_DWEN (unsigned char)~_BV(6) -#define FUSE_RSTDISBL (unsigned char)~_BV(7) -#define HFUSE_DEFAULT (FUSE_SPIEN) - -/* Extended Fuse Byte */ -#define FUSE_SELFPRGEN (unsigned char)~_BV(0) -#define EFUSE_DEFAULT (0xFF) - - -/* Lock Bits */ -#define __LOCK_BITS_EXIST - - -/* Signature */ -#define SIGNATURE_0 0x1E -#define SIGNATURE_1 0x92 -#define SIGNATURE_2 0x07 - -#define SLEEP_MODE_IDLE (0x00<<3) -#define SLEEP_MODE_ADC (0x01<<3) -#define SLEEP_MODE_PWR_DOWN (0x02<<3) -#define SLEEP_MODE_STANDBY (0x03<<3) - -#endif /* _AVR_IOTN44_H_ */ diff --git a/arduino/hardware/tools/avr/avr/include/avr/iotn441.h b/arduino/hardware/tools/avr/avr/include/avr/iotn441.h deleted file mode 100644 index b1471ca..0000000 --- a/arduino/hardware/tools/avr/avr/include/avr/iotn441.h +++ /dev/null @@ -1,903 +0,0 @@ -/***************************************************************************** - * - * Copyright (C) 2015 Atmel Corporation - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * - * * Neither the name of the copyright holders nor the names of - * contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - ****************************************************************************/ - - -#ifndef _AVR_ATTINY441_H_INCLUDED -#define _AVR_ATTINY441_H_INCLUDED - - -#ifndef _AVR_IO_H_ -# error "Include instead of this file." -#endif - -#ifndef _AVR_IOXXX_H_ -# define _AVR_IOXXX_H_ "iotn441.h" -#else -# error "Attempt to include more than one file." -#endif - -/* Registers and associated bit numbers */ - -#define ADCSRB _SFR_IO8(0x04) -#define ADTS0 0 -#define ADTS1 1 -#define ADTS2 2 -#define ADLAR 3 - -#define ADCSRA _SFR_IO8(0x05) -#define ADPS0 0 -#define ADPS1 1 -#define ADPS2 2 -#define ADIE 3 -#define ADIF 4 -#define ADATE 5 -#define ADSC 6 -#define ADEN 7 - -/* Combine ADCL and ADCH */ -#ifndef __ASSEMBLER__ -#define ADC _SFR_IO16(0x06) -#endif -#define ADCW _SFR_IO16(0x06) - -#define ADCL _SFR_IO8(0x06) -#define ADCH _SFR_IO8(0x07) - -#define ADMUXB _SFR_IO8(0x08) -#define GSEL0 0 -#define GSEL1 1 -#define REFS0 5 -#define REFS1 6 -#define REFS2 7 - -#define ADMUXA _SFR_IO8(0x09) -#define MUX0 0 -#define MUX1 1 -#define MUX2 2 -#define MUX3 3 -#define MUX4 4 -#define MUX5 5 - -#define ACSR0A _SFR_IO8(0x0A) -#define ACIS00 0 -#define ACIS01 1 -#define ACIC0 2 -#define ACIE0 3 -#define ACI0 4 -#define ACO0 5 -#define ACPMUX2 6 -#define ACD0 7 - -#define ACSR0B _SFR_IO8(0x0B) -#define ACPMUX0 0 -#define ACPMUX1 1 -#define ACNMUX0 2 -#define ACNMUX1 3 -#define ACOE0 4 -#define HLEV0 6 -#define HSEL0 7 - -#define ACSR1A _SFR_IO8(0x0C) -#define ACIS10 0 -#define ACIS11 1 -#define ACIC1 2 -#define ACIE1 3 -#define ACI1 4 -#define ACO1 5 -#define ACBG1 6 -#define ACD1 7 - -#define ACSR1B _SFR_IO8(0x0D) -#define ACME1 2 -#define ACOE1 4 -#define HLEV1 6 -#define HSEL1 7 - -#define TIFR1 _SFR_IO8(0x0E) -#define TOV1 0 -#define OCF1A 1 -#define OCF1B 2 -#define ICF1 5 - -#define TIMSK1 _SFR_IO8(0x0F) -#define TOIE1 0 -#define OCIE1A 1 -#define OCIE1B 2 -#define ICIE1 5 - -#define TIFR2 _SFR_IO8(0x10) -#define TOV2 0 -#define OCF2A 1 -#define OCF2B 2 -#define ICF2 5 - -#define TIMSK2 _SFR_IO8(0x11) -#define TOIE2 0 -#define OCIE2A 1 -#define OCIE2B 2 -#define ICIE2 5 - -#define PCMSK0 _SFR_IO8(0x12) -#define PCINT0 0 -#define PCINT1 1 -#define PCINT2 2 -#define PCINT3 3 -#define PCINT4 4 -#define PCINT5 5 -#define PCINT6 6 -#define PCINT7 7 - -#define GPIOR0 _SFR_IO8(0x13) - -#define GPIOR1 _SFR_IO8(0x14) - -#define GPIOR2 _SFR_IO8(0x15) - -#define PINB _SFR_IO8(0x16) -#define PINB3 3 -#define PINB2 2 -#define PINB1 1 -#define PINB0 0 - -#define DDRB _SFR_IO8(0x17) -#define DDRB3 3 -// Inserted "DDB3" from "DDRB3" due to compatibility -#define DDB3 3 -#define DDRB2 2 -// Inserted "DDB2" from "DDRB2" due to compatibility -#define DDB2 2 -#define DDRB1 1 -// Inserted "DDB1" from "DDRB1" due to compatibility -#define DDB1 1 -#define DDRB0 0 -// Inserted "DDB0" from "DDRB0" due to compatibility -#define DDB0 0 - -#define PORTB _SFR_IO8(0x18) -#define PORTB3 3 -#define PORTB2 2 -#define PORTB1 1 -#define PORTB0 0 - -#define PINA _SFR_IO8(0x19) -#define PINA7 7 -#define PINA6 6 -#define PINA5 5 -#define PINA4 4 -#define PINA3 3 -#define PINA2 2 -#define PINA1 1 -#define PINA0 0 - -#define DDRA _SFR_IO8(0x1A) -#define DDRA7 7 -// Inserted "DDA7" from "DDRA7" due to compatibility -#define DDA7 7 -#define DDRA6 6 -// Inserted "DDA6" from "DDRA6" due to compatibility -#define DDA6 6 -#define DDRA5 5 -// Inserted "DDA5" from "DDRA5" due to compatibility -#define DDA5 5 -#define DDRA4 4 -// Inserted "DDA4" from "DDRA4" due to compatibility -#define DDA4 4 -#define DDRA3 3 -// Inserted "DDA3" from "DDRA3" due to compatibility -#define DDA3 3 -#define DDRA2 2 -// Inserted "DDA2" from "DDRA2" due to compatibility -#define DDA2 2 -#define DDRA1 1 -// Inserted "DDA1" from "DDRA1" due to compatibility -#define DDA1 1 -#define DDRA0 0 -// Inserted "DDA0" from "DDRA0" due to compatibility -#define DDA0 0 - -#define PORTA _SFR_IO8(0x1B) -#define PORTA7 7 -#define PORTA6 6 -#define PORTA5 5 -#define PORTA4 4 -#define PORTA3 3 -#define PORTA2 2 -#define PORTA1 1 -#define PORTA0 0 - -#define EECR _SFR_IO8(0x1C) -#define EERE 0 -#define EEPE 1 -#define EEMPE 2 -#define EERIE 3 -#define EEPM0 4 -#define EEPM1 5 - -#define EEDR _SFR_IO8(0x1D) - -/* Combine EEARL and EEARH */ -#define EEAR _SFR_IO16(0x1E) - -#define EEARL _SFR_IO8(0x1E) -#define EEARH _SFR_IO8(0x1F) - -#define PCMSK1 _SFR_IO8(0x20) -#define PCINT8 0 -#define PCINT9 1 -#define PCINT10 2 -#define PCINT11 3 - -#define WDTCSR _SFR_IO8(0x21) -#define WDE 3 -#define WDP0 0 -#define WDP1 1 -#define WDP2 2 -#define WDP3 5 -#define WDIE 6 -#define WDIF 7 - -#define TCCR1C _SFR_IO8(0x22) -#define FOC1B 6 -#define FOC1A 7 - -#define GTCCR _SFR_IO8(0x23) -#define PSR 0 -#define TSM 7 - -/* Combine ICR1L and ICR1H */ -#define ICR1 _SFR_IO16(0x24) - -#define ICR1L _SFR_IO8(0x24) -#define ICR1H _SFR_IO8(0x25) - -/* Reserved [0x26..0x27] */ - -/* Combine OCR1BL and OCR1BH */ -#define OCR1B _SFR_IO16(0x28) - -#define OCR1BL _SFR_IO8(0x28) -#define OCR1BH _SFR_IO8(0x29) - -/* Combine OCR1AL and OCR1AH */ -#define OCR1A _SFR_IO16(0x2A) - -#define OCR1AL _SFR_IO8(0x2A) -#define OCR1AH _SFR_IO8(0x2B) - -/* Combine TCNT1L and TCNT1H */ -#define TCNT1 _SFR_IO16(0x2C) - -#define TCNT1L _SFR_IO8(0x2C) -#define TCNT1H _SFR_IO8(0x2D) - -#define TCCR1B _SFR_IO8(0x2E) -#define CS10 0 -#define CS11 1 -#define CS12 2 -#define WGM12 3 -#define WGM13 4 -#define ICES1 6 -#define ICNC1 7 - -#define TCCR1A _SFR_IO8(0x2F) -#define WGM10 0 -#define WGM11 1 -#define COM1B0 4 -#define COM1B1 5 -#define COM1A0 6 -#define COM1A1 7 - -#define TCCR0A _SFR_IO8(0x30) -#define WGM00 0 -#define WGM01 1 -#define COM0B0 4 -#define COM0B1 5 -#define COM0A0 6 -#define COM0A1 7 - -/* Reserved [0x31] */ - -#define TCNT0 _SFR_IO8(0x32) - -#define TCCR0B _SFR_IO8(0x33) -#define CS00 0 -#define CS01 1 -#define CS02 2 -#define WGM02 3 -#define FOC0B 6 -#define FOC0A 7 - -#define MCUSR _SFR_IO8(0x34) -#define PORF 0 -#define EXTRF 1 -#define BORF 2 -#define WDRF 3 - -#define MCUCR _SFR_IO8(0x35) -#define ISC00 0 -#define ISC01 1 -#define SM0 3 -#define SM1 4 -#define SE 5 - -#define OCR0A _SFR_IO8(0x36) - -#define SPMCSR _SFR_IO8(0x37) -#define SPMEN 0 -#define PGERS 1 -#define PGWRT 2 -#define RFLB 3 -#define CTPB 4 -#define RSIG 5 - -#define TIFR0 _SFR_IO8(0x38) -#define TOV0 0 -#define OCF0A 1 -#define OCF0B 2 - -#define TIMSK0 _SFR_IO8(0x39) -#define TOIE0 0 -#define OCIE0A 1 -#define OCIE0B 2 - -#define GIFR _SFR_IO8(0x3A) -#define PCIF0 4 -#define PCIF1 5 -#define INTF0 6 - -#define GIMSK _SFR_IO8(0x3B) -#define PCIE0 4 -#define PCIE1 5 -#define INT0 6 - -#define OCR0B _SFR_IO8(0x3C) - -/* SP [0x3D..0x3E] */ - -/* SREG [0x3F] */ - -#define DIDR0 _SFR_MEM8(0x60) -#define ADC0D 0 -#define ADC1D 1 -#define ADC2D 2 -#define ADC3D 3 -#define ADC4D 4 -#define ADC5D 5 -#define ADC6D 6 -#define ADC7D 7 - -#define DIDR1 _SFR_MEM8(0x61) -#define ADC11D 0 -#define ADC10D 1 -#define ADC8D 2 -#define ADC9D 3 - -#define PUEB _SFR_MEM8(0x62) - -#define PUEA _SFR_MEM8(0x63) - -#define PORTCR _SFR_MEM8(0x64) -#define BBMB 1 -#define BBMA 0 - -#define REMAP _SFR_MEM8(0x65) -#define U0MAP 0 -#define SPIMAP 1 - -#define TOCPMCOE _SFR_MEM8(0x66) -#define TOCC0OE 0 -#define TOCC1OE 1 -#define TOCC2OE 2 -#define TOCC3OE 3 -#define TOCC4OE 4 -#define TOCC5OE 5 -#define TOCC6OE 6 -#define TOCC7OE 7 - -#define TOCPMSA0 _SFR_MEM8(0x67) -#define TOCC0S0 0 -#define TOCC0S1 1 -#define TOCC1S0 2 -#define TOCC1S1 3 -#define TOCC2S0 4 -#define TOCC2S1 5 -#define TOCC3S0 6 -#define TOCC3S1 7 - -#define TOCPMSA1 _SFR_MEM8(0x68) -#define TOCC4S0 0 -#define TOCC4S1 1 -#define TOCC5S0 2 -#define TOCC5S1 3 -#define TOCC6S0 4 -#define TOCC6S1 5 -#define TOCC7S0 6 -#define TOCC7S1 7 - -/* Reserved [0x69] */ - -#define PHDE _SFR_MEM8(0x6A) -#define PHDEA0 0 -#define PHDEA1 1 - -/* Reserved [0x6B..0x6F] */ - -#define PRR _SFR_MEM8(0x70) -#define PRADC 0 -#define PRTIM0 1 -#define PRTIM1 2 -#define PRTIM2 3 -#define PRSPI 4 -#define PRUSART0 5 -#define PRUSART1 6 -#define PRTWI 7 - -#define __AVR_HAVE_PRR ((1<, never directly. */ - -#ifndef _AVR_IO_H_ -# error "Include instead of this file." -#endif - -#ifndef _AVR_IOXXX_H_ -# define _AVR_IOXXX_H_ "iotn44a.h" -#else -# error "Attempt to include more than one file." -#endif - - -#ifndef _AVR_ATtiny44A_H_ -#define _AVR_ATtiny44A_H_ 1 - - -/* Registers and associated bit numbers. */ - -#define PRR _SFR_IO8(0x00) -#define PRADC 0 -#define PRUSI 1 -#define PRTIM0 2 -#define PRTIM1 3 - -#define __AVR_HAVE_PRR ((1< - -/* Constants */ -#define SPM_PAGESIZE 64 -#define RAMSTART (0x60) -#define RAMEND 0x15F -#define XRAMEND RAMEND -#define E2END 0xFF -#define E2PAGESIZE 4 -#define FLASHEND 0xFFF - - -/* Fuses */ -#define FUSE_MEMORY_SIZE 3 - -/* Low Fuse Byte */ -#define FUSE_CKSEL0 (unsigned char)~_BV(0) -#define FUSE_CKSEL1 (unsigned char)~_BV(1) -#define FUSE_CKSEL2 (unsigned char)~_BV(2) -#define FUSE_CKSEL3 (unsigned char)~_BV(3) -#define FUSE_SUT0 (unsigned char)~_BV(4) -#define FUSE_SUT1 (unsigned char)~_BV(5) -#define FUSE_CKOUT (unsigned char)~_BV(6) -#define FUSE_CKDIV8 (unsigned char)~_BV(7) -#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8) - -/* High Fuse Byte */ -#define FUSE_BODLEVEL0 (unsigned char)~_BV(0) -#define FUSE_BODLEVEL1 (unsigned char)~_BV(1) -#define FUSE_BODLEVEL2 (unsigned char)~_BV(2) -#define FUSE_EESAVE (unsigned char)~_BV(3) -#define FUSE_WDTON (unsigned char)~_BV(4) -#define FUSE_SPIEN (unsigned char)~_BV(5) -#define FUSE_DWEN (unsigned char)~_BV(6) -#define FUSE_RSTDISBL (unsigned char)~_BV(7) -#define HFUSE_DEFAULT (FUSE_SPIEN) - -/* Extended Fuse Byte */ -#define FUSE_SELFPRGEN (unsigned char)~_BV(0) -#define EFUSE_DEFAULT (0xFF) - - -/* Lock Bits */ -#define __LOCK_BITS_EXIST - - -/* Signature */ -#define SIGNATURE_0 0x1E -#define SIGNATURE_1 0x92 -#define SIGNATURE_2 0x06 - -#define SLEEP_MODE_IDLE (0x00<<3) -#define SLEEP_MODE_ADC (0x01<<3) -#define SLEEP_MODE_PWR_DOWN (0x02<<3) - -#endif /* _AVR_IOTN45_H_ */ diff --git a/arduino/hardware/tools/avr/avr/include/avr/iotn461.h b/arduino/hardware/tools/avr/avr/include/avr/iotn461.h deleted file mode 100644 index eef716f..0000000 --- a/arduino/hardware/tools/avr/avr/include/avr/iotn461.h +++ /dev/null @@ -1,94 +0,0 @@ -/* Copyright (c) 2006, Anatoly Sokolov - All rights reserved. - - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - * Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - * Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in - the documentation and/or other materials provided with the - distribution. - - * Neither the name of the copyright holders nor the names of - contributors may be used to endorse or promote products derived - from this software without specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. */ - -/* $Id: iotn461.h 2115 2010-04-05 23:19:53Z arcanum $ */ - -/* avr/iotn461.h - definitions for ATtiny461 */ - -#ifndef _AVR_IOTN461_H_ -#define _AVR_IOTN461_H_ 1 - -#include - -/* Constants */ -#define SPM_PAGESIZE 64 -#define RAMSTART (0x60) -#define RAMEND 0x15F -#define XRAMEND RAMEND -#define E2END 0xFF -#define E2PAGESIZE 4 -#define FLASHEND 0xFFF - - -/* Fuses */ -#define FUSE_MEMORY_SIZE 3 - -/* Low Fuse Byte */ -#define FUSE_CKSEL0 (unsigned char)~_BV(0) -#define FUSE_CKSEL1 (unsigned char)~_BV(1) -#define FUSE_CKSEL2 (unsigned char)~_BV(2) -#define FUSE_CKSEL3 (unsigned char)~_BV(3) -#define FUSE_SUT0 (unsigned char)~_BV(4) -#define FUSE_SUT1 (unsigned char)~_BV(5) -#define FUSE_CKOUT (unsigned char)~_BV(6) -#define FUSE_CKDIV8 (unsigned char)~_BV(7) -#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8) - -/* High Fuse Byte */ -#define FUSE_BODLEVEL0 (unsigned char)~_BV(0) -#define FUSE_BODLEVEL1 (unsigned char)~_BV(1) -#define FUSE_BODLEVEL2 (unsigned char)~_BV(2) -#define FUSE_EESAVE (unsigned char)~_BV(3) -#define FUSE_WDTON (unsigned char)~_BV(4) -#define FUSE_SPIEN (unsigned char)~_BV(5) -#define FUSE_DWEN (unsigned char)~_BV(6) -#define FUSE_RSTDISBL (unsigned char)~_BV(7) -#define HFUSE_DEFAULT (FUSE_SPIEN) - -/* Extended Fuse Byte */ -#define FUSE_SELFPRGEN (unsigned char)~_BV(0) -#define EFUSE_DEFAULT (0xFF) - - -/* Lock Bits */ -#define __LOCK_BITS_EXIST - - -/* Signature */ -#define SIGNATURE_0 0x1E -#define SIGNATURE_1 0x92 -#define SIGNATURE_2 0x08 - -#define SLEEP_MODE_IDLE (0x00<<3) -#define SLEEP_MODE_ADC (0x01<<3) -#define SLEEP_MODE_PWR_DOWN (0x02<<3) -#define SLEEP_MODE_STANDBY (0x03<<3) - -#endif /* _AVR_IOTN461_H_ */ diff --git a/arduino/hardware/tools/avr/avr/include/avr/iotn461a.h b/arduino/hardware/tools/avr/avr/include/avr/iotn461a.h deleted file mode 100644 index 809e23b..0000000 --- a/arduino/hardware/tools/avr/avr/include/avr/iotn461a.h +++ /dev/null @@ -1,987 +0,0 @@ -/* Copyright (c) 2009 Atmel Corporation - All rights reserved. - - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - * Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - * Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in - the documentation and/or other materials provided with the - distribution. - - * Neither the name of the copyright holders nor the names of - contributors may be used to endorse or promote products derived - from this software without specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. */ - -/* $Id: iotn461a.h 2063 2009-11-18 22:06:28Z arcanum $ */ - -/* avr/iotn461a.h - definitions for ATtiny461A */ - -/* This file should only be included from , never directly. */ - -#ifndef _AVR_IO_H_ -# error "Include instead of this file." -#endif - -#ifndef _AVR_IOXXX_H_ -# define _AVR_IOXXX_H_ "iotn461a.h" -#else -# error "Attempt to include more than one file." -#endif - - -#ifndef _AVR_ATtiny461A_H_ -#define _AVR_ATtiny461A_H_ 1 - - -/* Registers and associated bit numbers. */ - -#define TCCR1E _SFR_IO8(0x00) -#define OC1OE0 0 -#define OC1OE1 1 -#define OC1OE2 2 -#define OC1OE3 3 -#define OC1OE4 4 -#define OC1OE5 5 - -#define DIDR0 _SFR_IO8(0x01) -#define ADC0D 0 -#define ADC1D 1 -#define ADC2D 2 -#define AREFD 3 -#define ADC3D 4 -#define ADC4D 5 -#define ADC5D 6 -#define ADC6D 7 - -#define DIDR1 _SFR_IO8(0x02) -#define ADC7D 4 -#define ADC8D 5 -#define ADC9D 6 -#define ADC10D 7 - -#define ADCSRB _SFR_IO8(0x03) -#define ADTS0 0 -#define ADTS1 1 -#define ADTS2 2 -#define MUX5 3 -#define REFS2 4 -#define IPR 5 -#define GSEL 6 -#define BIN 7 - -#ifndef __ASSEMBLER__ -#define ADC _SFR_IO16(0x04) -#endif -#define ADCW _SFR_IO16(0x04) - -#define ADCL _SFR_IO8(0x04) -#define ADCL0 0 -#define ADCL1 1 -#define ADCL2 2 -#define ADCL3 3 -#define ADCL4 4 -#define ADCL5 5 -#define ADCL6 6 -#define ADCL7 7 - -#define ADCH _SFR_IO8(0x05) -#define ADCH0 0 -#define ADCH1 1 -#define ADCH2 2 -#define ADCH3 3 -#define ADCH4 4 -#define ADCH5 5 -#define ADCH6 6 -#define ADCH7 7 - -#define ADCSRA _SFR_IO8(0x06) -#define ADPS0 0 -#define ADPS1 1 -#define ADPS2 2 -#define ADIE 3 -#define ADIF 4 -#define ADATE 5 -#define ADSC 6 -#define ADEN 7 - -#define ADMUX _SFR_IO8(0x07) -#define MUX0 0 -#define MUX1 1 -#define MUX2 2 -#define MUX3 3 -#define MUX4 4 -#define ADLAR 5 -#define REFS0 6 -#define REFS1 7 - -#define ACSRA _SFR_IO8(0x08) -#define ACIS0 0 -#define ACIS1 1 -#define ACME 2 -#define ACIE 3 -#define ACI 4 -#define ACO 5 -#define ACBG 6 -#define ACD 7 - -#define ACSRB _SFR_IO8(0x09) -#define ACM0 0 -#define ACM1 1 -#define ACM2 2 -#define HLEV 6 -#define HSEL 7 - -#define GPIOR0 _SFR_IO8(0x0A) -#define GPIOR00 0 -#define GPIOR01 1 -#define GPIOR02 2 -#define GPIOR03 3 -#define GPIOR04 4 -#define GPIOR05 5 -#define GPIOR06 6 -#define GPIOR07 7 - -#define GPIOR1 _SFR_IO8(0x0B) -#define GPIOR10 0 -#define GPIOR11 1 -#define GPIOR12 2 -#define GPIOR13 3 -#define GPIOR14 4 -#define GPIOR15 5 -#define GPIOR16 6 -#define GPIOR17 7 - -#define GPIOR2 _SFR_IO8(0x0C) -#define GPIOR20 0 -#define GPIOR21 1 -#define GPIOR22 2 -#define GPIOR23 3 -#define GPIOR24 4 -#define GPIOR25 5 -#define GPIOR26 6 -#define GPIOR27 7 - -#define USICR _SFR_IO8(0x0D) -#define USITC 0 -#define USICLK 1 -#define USICS0 2 -#define USICS1 3 -#define USIWM0 4 -#define USIWM1 5 -#define USIOIE 6 -#define USISIE 7 - -#define USISR _SFR_IO8(0x0E) -#define USICNT0 0 -#define USICNT1 1 -#define USICNT2 2 -#define USICNT3 3 -#define USIDC 4 -#define USIPF 5 -#define USIOIF 6 -#define USISIF 7 - -#define USIDR _SFR_IO8(0x0F) -#define USIDR0 0 -#define USIDR1 1 -#define USIDR2 2 -#define USIDR3 3 -#define USIDR4 4 -#define USIDR5 5 -#define USIDR6 6 -#define USIDR7 7 - -#define USIBR _SFR_IO8(0x10) -#define USIBR0 0 -#define USIBR1 1 -#define USIBR2 2 -#define USIBR3 3 -#define USIBR4 4 -#define USIBR5 5 -#define USIBR6 6 -#define USIBR7 7 - -#define USIPP _SFR_IO8(0x11) -#define USIPOS 0 - -#define OCR0B _SFR_IO8(0x12) -#define OCR0B_0 0 -#define OCR0B_1 1 -#define OCR0B_2 2 -#define OCR0B_3 3 -#define OCR0B_4 4 -#define OCR0B_5 5 -#define OCR0B_6 6 -#define OCR0B_7 7 - -#define OCR0A _SFR_IO8(0x13) -#define OCR0A_0 0 -#define OCR0A_1 1 -#define OCR0A_2 2 -#define OCR0A_3 3 -#define OCR0A_4 4 -#define OCR0A_5 5 -#define OCR0A_6 6 -#define OCR0A_7 7 - -#define TCNT0H _SFR_IO8(0x14) -#define TCNT0H_0 0 -#define TCNT0H_1 1 -#define TCNT0H_2 2 -#define TCNT0H_3 3 -#define TCNT0H_4 4 -#define TCNT0H_5 5 -#define TCNT0H_6 6 -#define TCNT0H_7 7 - -#define TCCR0A _SFR_IO8(0x15) -#define WGM00 0 -#define ACIC0 3 -#define ICES0 4 -#define ICNC0 5 -#define ICEN0 6 -#define TCW0 7 - -#define PINB _SFR_IO8(0x16) -#define PINB0 0 -#define PINB1 1 -#define PINB2 2 -#define PINB3 3 -#define PINB4 4 -#define PINB5 5 -#define PINB6 6 -#define PINB7 7 - -#define DDRB _SFR_IO8(0x17) -#define DDB0 0 -#define DDB1 1 -#define DDB2 2 -#define DDB3 3 -#define DDB4 4 -#define DDB5 5 -#define DDB6 6 -#define DDB7 7 - -#define PORTB _SFR_IO8(0x18) -#define PORTB0 0 -#define PORTB1 1 -#define PORTB2 2 -#define PORTB3 3 -#define PORTB4 4 -#define PORTB5 5 -#define PORTB6 6 -#define PORTB7 7 - -#define PINA _SFR_IO8(0x19) -#define PINA0 0 -#define PINA1 1 -#define PINA2 2 -#define PINA3 3 -#define PINA4 4 -#define PINA5 5 -#define PINA6 6 -#define PINA7 7 - -#define DDRA _SFR_IO8(0x1A) -#define DDA0 0 -#define DDA1 1 -#define DDA2 2 -#define DDA3 3 -#define DDA4 4 -#define DDA5 5 -#define DDA6 6 -#define DDA7 7 - -#define PORTA _SFR_IO8(0x1B) -#define PORTA0 0 -#define PORTA1 1 -#define PORTA2 2 -#define PORTA3 3 -#define PORTA4 4 -#define PORTA5 5 -#define PORTA6 6 -#define PORTA7 7 - -#define EECR _SFR_IO8(0x1C) -#define EERE 0 -#define EEPE 1 -#define EEMPE 2 -#define EERIE 3 -#define EEPM0 4 -#define EEPM1 5 - -#define EEDR _SFR_IO8(0x1D) -#define EEDR0 0 -#define EEDR1 1 -#define EEDR2 2 -#define EEDR3 3 -#define EEDR4 4 -#define EEDR5 5 -#define EEDR6 6 -#define EEDR7 7 - -#define EEAR _SFR_IO16(0x1E) - -#define EEARL _SFR_IO8(0x1E) -#define EEAR0 0 -#define EEAR1 1 -#define EEAR2 2 -#define EEAR3 3 -#define EEAR4 4 -#define EEAR5 5 -#define EEAR6 6 -#define EEAR7 7 - -#define EEARH _SFR_IO8(0x1F) -#define EEAR8 0 - -#define DWDR _SFR_IO8(0x20) -#define DWDR0 0 -#define DWDR1 1 -#define DWDR2 2 -#define DWDR3 3 -#define DWDR4 4 -#define DWDR5 5 -#define DWDR6 6 -#define DWDR7 7 - -#define WDTCR _SFR_IO8(0x21) -#define WDP0 0 -#define WDP1 1 -#define WDP2 2 -#define WDE 3 -#define WDCE 4 -#define WDP3 5 -#define WDIE 6 -#define WDIF 7 - -#define PCMSK1 _SFR_IO8(0x22) -#define PCINT8 0 -#define PCINT9 1 -#define PCINT10 2 -#define PCINT11 3 -#define PCINT12 4 -#define PCINT13 5 -#define PCINT14 6 -#define PCINT15 7 - -#define PCMSK0 _SFR_IO8(0x23) -#define PCINT0 0 -#define PCINT1 1 -#define PCINT2 2 -#define PCINT3 3 -#define PCINT4 4 -#define PCINT5 5 -#define PCINT6 6 -#define PCINT7 7 - -#define DT1 _SFR_IO8(0x24) -#define DT1L0 0 -#define DT1L1 1 -#define DT1L2 2 -#define DT1L3 3 -#define DT1H0 4 -#define DT1H1 5 -#define DT1H2 6 -#define DT1H3 7 - -#define TC1H _SFR_IO8(0x25) -#define TC18 0 -#define TC19 1 - -#define TCCR1D _SFR_IO8(0x26) -#define WGM10 0 -#define WGM11 1 -#define FPF1 2 -#define FPAC1 3 -#define FPES1 4 -#define FPNC1 5 -#define FPEN1 6 -#define FPIE1 7 - -#define TCCR1C _SFR_IO8(0x27) -#define PWM1D 0 -#define FOC1D 1 -#define COM1D0 2 -#define COM1D1 3 -#define COM1B0S 4 -#define COM1B1S 5 -#define COM1A0S 6 -#define COM1A1S 7 - -#define CLKPR _SFR_IO8(0x28) -#define CLKPS0 0 -#define CLKPS1 1 -#define CLKPS2 2 -#define CLKPS3 3 -#define CLKPCE 7 - -#define PLLCSR _SFR_IO8(0x29) -#define PLOCK 0 -#define PLLE 1 -#define PCKE 2 -#define LSM 7 - -#define OCR1D _SFR_IO8(0x2A) -#define OCR1D0 0 -#define OCR1D1 1 -#define OCR1D2 2 -#define OCR1D3 3 -#define OCR1D4 4 -#define OCR1D5 5 -#define OCR1D6 6 -#define OCR1D7 7 - -#define OCR1C _SFR_IO8(0x2B) -#define OCR1C0 0 -#define OCR1C1 1 -#define OCR1C2 2 -#define OCR1C3 3 -#define OCR1C4 4 -#define OCR1C5 5 -#define OCR1C6 6 -#define OCR1C7 7 - -#define OCR1B _SFR_IO8(0x2C) -#define OCR1B0 0 -#define OCR1B1 1 -#define OCR1B2 2 -#define OCR1B3 3 -#define OCR1B4 4 -#define OCR1B5 5 -#define OCR1B6 6 -#define OCR1B7 7 - -#define OCR1A _SFR_IO8(0x2D) -#define OCR1A0 0 -#define OCR1A1 1 -#define OCR1A2 2 -#define OCR1A3 3 -#define OCR1A4 4 -#define OCR1A5 5 -#define OCR1A6 6 -#define OCR1A7 7 - -#define TCNT1 _SFR_IO8(0x2E) -#define TC1H_0 0 -#define TC1H_1 1 -#define TC1H_2 2 -#define TC1H_3 3 -#define TC1H_4 4 -#define TC1H_5 5 -#define TC1H_6 6 -#define TC1H_7 7 - -#define TCCR1B _SFR_IO8(0x2F) -#define CS10 0 -#define CS11 1 -#define CS12 2 -#define CS13 3 -#define DTPS10 4 -#define DTPS11 5 -#define PSR1 6 - -#define TCCR1A _SFR_IO8(0x30) -#define PWM1B 0 -#define PWM1A 1 -#define FOC1B 2 -#define FOC1A 3 -#define COM1B0 4 -#define COM1B1 5 -#define COM1A0 6 -#define COM1A1 7 - -#define OSCCAL _SFR_IO8(0x31) -#define CAL0 0 -#define CAL1 1 -#define CAL2 2 -#define CAL3 3 -#define CAL4 4 -#define CAL5 5 -#define CAL6 6 -#define CAL7 7 - -#define TCNT0L _SFR_IO8(0x32) -#define TCNT0L_0 0 -#define TCNT0L_1 1 -#define TCNT0L_2 2 -#define TCNT0L_3 3 -#define TCNT0L_4 4 -#define TCNT0L_5 5 -#define TCNT0L_6 6 -#define TCNT0L_7 7 - -#define TCCR0B _SFR_IO8(0x33) -#define CS00 0 -#define CS01 1 -#define CS02 2 -#define PSR0 3 -#define TSM 4 - -#define MCUSR _SFR_IO8(0x34) -#define PORF 0 -#define EXTRF 1 -#define BORF 2 -#define WDRF 3 - -#define MCUCR _SFR_IO8(0x35) -#define ISC00 0 -#define ISC01 1 -#define BODSE 2 -#define SM0 3 -#define SM1 4 -#define SE 5 -#define PUD 6 -#define BODS 7 - -#define PRR _SFR_IO8(0x36) -#define PRADC 0 -#define PRUSI 1 -#define PRTIM0 2 -#define PRTIM1 3 - -#define __AVR_HAVE_PRR ((1<, never directly. */ - -#ifndef _AVR_IO_H_ -# error "Include instead of this file." -#endif - -#ifndef _AVR_IOXXX_H_ -# define _AVR_IOXXX_H_ "iotn48.h" -#else -# error "Attempt to include more than one file." -#endif - - -#ifndef _AVR_IOTN48_H_ -#define _AVR_IOTN48_H_ 1 - -/* Registers and associated bit numbers */ - -#define PINB _SFR_IO8(0x03) -#define PINB0 0 -#define PINB1 1 -#define PINB2 2 -#define PINB3 3 -#define PINB4 4 -#define PINB5 5 -#define PINB6 6 -#define PINB7 7 - -#define DDRB _SFR_IO8(0x04) -#define DDB0 0 -#define DDB1 1 -#define DDB2 2 -#define DDB3 3 -#define DDB4 4 -#define DDB5 5 -#define DDB6 6 -#define DDB7 7 - -#define PORTB _SFR_IO8(0x05) -#define PORTB0 0 -#define PORTB1 1 -#define PORTB2 2 -#define PORTB3 3 -#define PORTB4 4 -#define PORTB5 5 -#define PORTB6 6 -#define PORTB7 7 - -#define PINC _SFR_IO8(0x06) -#define PINC0 0 -#define PINC1 1 -#define PINC2 2 -#define PINC3 3 -#define PINC4 4 -#define PINC5 5 -#define PINC6 6 -#define PINC7 7 - -#define DDRC _SFR_IO8(0x07) -#define DDC0 0 -#define DDC1 1 -#define DDC2 2 -#define DDC3 3 -#define DDC4 4 -#define DDC5 5 -#define DDC6 6 -#define DDC7 7 - -#define PORTC _SFR_IO8(0x08) -#define PORTC0 0 -#define PORTC1 1 -#define PORTC2 2 -#define PORTC3 3 -#define PORTC4 4 -#define PORTC5 5 -#define PORTC6 6 -#define PORTC7 7 - -#define PIND _SFR_IO8(0x09) -#define PIND0 0 -#define PIND1 1 -#define PIND2 2 -#define PIND3 3 -#define PIND4 4 -#define PIND5 5 -#define PIND6 6 -#define PIND7 7 - -#define DDRD _SFR_IO8(0x0A) -#define DDD0 0 -#define DDD1 1 -#define DDD2 2 -#define DDD3 3 -#define DDD4 4 -#define DDD5 5 -#define DDD6 6 -#define DDD7 7 - -#define PORTD _SFR_IO8(0x0B) -#define PORTD0 0 -#define PORTD1 1 -#define PORTD2 2 -#define PORTD3 3 -#define PORTD4 4 -#define PORTD5 5 -#define PORTD6 6 -#define PORTD7 7 - -#define PINA _SFR_IO8(0x0C) -#define PINA0 0 -#define PINA1 1 -#define PINA2 2 -#define PINA3 3 - -#define DDRA _SFR_IO8(0x0D) -#define DDA0 0 -#define DDA1 1 -#define DDA2 2 -#define DDA3 3 - -#define PORTA _SFR_IO8(0x0E) -#define PORTA0 0 -#define PORTA1 1 -#define PORTA2 2 -#define PORTA3 3 - -#define PORTCR _SFR_IO8(0x12) -#define PUDA 0 -#define PUDB 1 -#define PUDC 2 -#define PUDD 3 -#define BBMA 4 -#define BBMB 5 -#define BBMC 6 -#define BBMD 7 - -#define TIFR0 _SFR_IO8(0x15) -#define TOV0 0 -#define OCF0A 1 -#define OCF0B 2 - -#define TIFR1 _SFR_IO8(0x16) -#define TOV1 0 -#define OCF1A 1 -#define OCF1B 2 -#define ICF1 5 - -#define PCIFR _SFR_IO8(0x1B) -#define PCIF0 0 -#define PCIF1 1 -#define PCIF2 2 -#define PCIF3 3 - -#define EIFR _SFR_IO8(0x1C) -#define INTF0 0 -#define INTF1 1 - -#define EIMSK _SFR_IO8(0x1D) -#define INT0 0 -#define INT1 1 - -#define GPIOR0 _SFR_IO8(0x1E) -#define GPIOR00 0 -#define GPIOR01 1 -#define GPIOR02 2 -#define GPIOR03 3 -#define GPIOR04 4 -#define GPIOR05 5 -#define GPIOR06 6 -#define GPIOR07 7 - -#define EECR _SFR_IO8(0x1F) -#define EERE 0 -#define EEPE 1 -#define EEMPE 2 -#define EERIE 3 -#define EEPM0 4 -#define EEPM1 5 - -#define EEDR _SFR_IO8(0x20) -#define EEDR0 0 -#define EEDR1 1 -#define EEDR2 2 -#define EEDR3 3 -#define EEDR4 4 -#define EEDR5 5 -#define EEDR6 6 -#define EEDR7 7 - -#define EEARL _SFR_IO8(0x21) -#define EEAR0 0 -#define EEAR1 1 -#define EEAR2 2 -#define EEAR3 3 -#define EEAR4 4 -#define EEAR5 5 -#define EEAR6 6 -#define EEAR7 7 - -#define GTCCR _SFR_IO8(0x23) -#define PSRSYNC 0 -#define TSM 7 - -#define TCCR0A _SFR_IO8(0x25) -#define CS00 0 -#define CS01 1 -#define CS02 2 -#define CTC0 3 - -#define TCNT0 _SFR_IO8(0x26) -#define TCNT0_0 0 -#define TCNT0_1 1 -#define TCNT0_2 2 -#define TCNT0_3 3 -#define TCNT0_4 4 -#define TCNT0_5 5 -#define TCNT0_6 6 -#define TCNT0_7 7 - -#define OCR0A _SFR_IO8(0x27) -#define OCR0A_0 0 -#define OCR0A_1 1 -#define OCR0A_2 2 -#define OCR0A_3 3 -#define OCR0A_4 4 -#define OCR0A_5 5 -#define OCR0A_6 6 -#define OCR0A_7 7 - -#define OCR0B _SFR_IO8(0x28) -#define OCR0B_0 0 -#define OCR0B_1 1 -#define OCR0B_2 2 -#define OCR0B_3 3 -#define OCR0B_4 4 -#define OCR0B_5 5 -#define OCR0B_6 6 -#define OCR0B_7 7 - -#define GPIOR1 _SFR_IO8(0x2A) -#define GPIOR10 0 -#define GPIOR11 1 -#define GPIOR12 2 -#define GPIOR13 3 -#define GPIOR14 4 -#define GPIOR15 5 -#define GPIOR16 6 -#define GPIOR17 7 - -#define GPIOR2 _SFR_IO8(0x2B) -#define GPIOR20 0 -#define GPIOR21 1 -#define GPIOR22 2 -#define GPIOR23 3 -#define GPIOR24 4 -#define GPIOR25 5 -#define GPIOR26 6 -#define GPIOR27 7 - -#define SPCR _SFR_IO8(0x2C) -#define SPR0 0 -#define SPR1 1 -#define CPHA 2 -#define CPOL 3 -#define MSTR 4 -#define DORD 5 -#define SPE 6 -#define SPIE 7 - -#define SPSR _SFR_IO8(0x2D) -#define SPI2X 0 -#define WCOL 6 -#define SPIF 7 - -#define SPDR _SFR_IO8(0x2E) -#define SPDR0 0 -#define SPDR1 1 -#define SPDR2 2 -#define SPDR3 3 -#define SPDR4 4 -#define SPDR5 5 -#define SPDR6 6 -#define SPDR7 7 - -#define ACSR _SFR_IO8(0x30) -#define ACIS0 0 -#define ACIS1 1 -#define ACIC 2 -#define ACIE 3 -#define ACI 4 -#define ACO 5 -#define ACBG 6 -#define ACD 7 - -#define SMCR _SFR_IO8(0x33) -#define SE 0 -#define SM0 1 -#define SM1 2 - -#define MCUSR _SFR_IO8(0x34) -#define PORF 0 -#define EXTRF 1 -#define BORF 2 -#define WDRF 3 - -#define MCUCR _SFR_IO8(0x35) -#define PUD 4 -#define BODSE 5 -#define BODS 6 - -#define SPMCSR _SFR_IO8(0x37) -#define SELFPRGEN 0 -#define PGERS 1 -#define PGWRT 2 -#define RFLB 3 -#define CTPB 4 -#define RWWSB 6 - -#define WDTCSR _SFR_MEM8(0x60) -#define WDP0 0 -#define WDP1 1 -#define WDP2 2 -#define WDE 3 -#define WDCE 4 -#define WDP3 5 -#define WDIE 6 -#define WDIF 7 - -#define CLKPR _SFR_MEM8(0x61) -#define CLKPS0 0 -#define CLKPS1 1 -#define CLKPS2 2 -#define CLKPS3 3 -#define CLKPCE 7 - -#define PRR _SFR_MEM8(0x64) -#define PRADC 0 -#define PRSPI 2 -#define PRTIM1 3 -#define PRTIM0 5 -#define PRTWI 7 - -#define __AVR_HAVE_PRR ((1<, never directly. */ - -#ifndef _AVR_IO_H_ -# error "Include instead of this file." -#endif - -#ifndef _AVR_IOXXX_H_ -# define _AVR_IOXXX_H_ "iotn5.h" -#else -# error "Attempt to include more than one file." -#endif - - -#ifndef _AVR_ATtiny5_H_ -#define _AVR_ATtiny5_H_ 1 - - -/* Registers and associated bit numbers. */ - -#define PINB _SFR_IO8(0x00) -#define PINB0 0 -#define PINB1 1 -#define PINB2 2 -#define PINB3 3 - -#define DDRB _SFR_IO8(0x01) -#define DDB0 0 -#define DDB1 1 -#define DDB2 2 -#define DDB3 3 - -#define PORTB _SFR_IO8(0x02) -#define PORTB0 0 -#define PORTB1 1 -#define PORTB2 2 -#define PORTB3 3 - -#define PUEB _SFR_IO8(0x03) -#define PUEB0 0 -#define PUEB1 1 -#define PUEB2 2 -#define PUEB3 3 - -#define PORTCR _SFR_IO8(0x0C) -#define BBMB 1 - -#define PCMSK _SFR_IO8(0x10) -#define PCINT0 0 -#define PCINT1 1 -#define PCINT2 2 -#define PCINT3 3 - -#define PCIFR _SFR_IO8(0x11) -#define PCIF0 0 - -#define PCICR _SFR_IO8(0x12) -#define PCIE0 0 - -#define EIMSK _SFR_IO8(0x13) -#define INT0 0 - -#define EIFR _SFR_IO8(0x14) -#define INTF0 0 - -#define EICRA _SFR_IO8(0x15) -#define ISC00 0 -#define ISC01 1 - -#define DIDR0 _SFR_IO8(0x17) -#define ADC0D 0 -#define AIN0D 0 -#define ADC1D 1 -#define AIN1D 1 -#define ADC2D 2 -#define ADC3D 3 - -#define ADCL _SFR_IO8(0x19) -#define ADC0 0 -#define ADC1 1 -#define ADC2 2 -#define ADC3 3 -#define ADC4 4 -#define ADC5 5 -#define ADC6 6 -#define ADC7 7 - -#define ADMUX _SFR_IO8(0x1B) -#define MUX0 0 -#define MUX1 1 - -#define ADCSRB _SFR_IO8(0x1C) -#define ADTS0 0 -#define ADTS1 1 -#define ADTS2 2 - -#define ADCSRA _SFR_IO8(0x1D) -#define ADPS0 0 -#define ADPS1 1 -#define ADPS2 2 -#define ADIE 3 -#define ADIF 4 -#define ADATE 5 -#define ADSC 6 -#define ADEN 7 - -#define ACSR _SFR_IO8(0x1F) -#define ACIS0 0 -#define ACIS1 1 -#define ACIC 2 -#define ACIE 3 -#define ACI 4 -#define ACO 5 -#define ACD 7 - -#define ICR0 _SFR_IO16(0x22) - -#define ICR0L _SFR_IO8(0x22) -#define ICR0_0 0 -#define ICR0_1 1 -#define ICR0_2 2 -#define ICR0_3 3 -#define ICR0_4 4 -#define ICR0_5 5 -#define ICR0_6 6 -#define ICR0_7 7 - -#define ICR0H _SFR_IO8(0x23) -#define ICR0_8 0 -#define ICR0_9 1 -#define ICR0_10 2 -#define ICR0_11 3 -#define ICR0_12 4 -#define ICR0_13 5 -#define ICR0_14 6 -#define ICR0_15 7 - -#define OCR0B _SFR_IO16(0x24) - -#define OCR0BL _SFR_IO8(0x24) -#define OCR0B0 0 -#define OCR0B1 1 -#define OCR0B2 2 -#define OCR0B3 3 -#define OCR0B4 4 -#define OCR0B5 5 -#define OCR0B6 6 -#define OCR0B7 7 - -#define OCR0BH _SFR_IO8(0x25) -#define OCR0B8 0 -#define OCR0B9 1 -#define OCR0B10 2 -#define OCR0B11 3 -#define OCR0B12 4 -#define OCR0B13 5 -#define OCR0B14 6 -#define OCR0B15 7 - -#define OCR0A _SFR_IO16(0x26) - -#define OCR0AL _SFR_IO8(0x26) -#define OCR0A0 0 -#define OCR0A1 1 -#define OCR0A2 2 -#define OCR0A3 3 -#define OCR0A4 4 -#define OCR0A5 5 -#define OCR0A6 6 -#define OCR0A7 7 - -#define OCR0AH _SFR_IO8(0x27) -#define OCR0A8 0 -#define OCR0A9 1 -#define OCR0A10 2 -#define OCR0A11 3 -#define OCR0A12 4 -#define OCR0A13 5 -#define OCR0A14 6 -#define OCR0A15 7 - -#define TCNT0 _SFR_IO16(0x28) - -#define TCNT0L _SFR_IO8(0x28) -#define TCNT0_0 0 -#define TCNT0_1 1 -#define TCNT0_2 2 -#define TCNT0_3 3 -#define TCNT0_4 4 -#define TCNT0_5 5 -#define TCNT0_6 6 -#define TCNT0_7 7 - -#define TCNT0H _SFR_IO8(0x29) -#define TCNT0_8 0 -#define TCNT0_9 1 -#define TCNT0_10 2 -#define TCNT0_11 3 -#define TCNT0_12 4 -#define TCNT0_13 5 -#define TCNT0_14 6 -#define TCNT0_15 7 - -#define TIFR0 _SFR_IO8(0x2A) -#define TOV0 0 -#define OCF0A 1 -#define OCF0B 2 -#define ICF0 5 - -#define TIMSK0 _SFR_IO8(0x2B) -#define TOIE0 0 -#define OCIE0A 1 -#define OCIE0B 2 -#define ICIE0 5 - -#define TCCR0C _SFR_IO8(0x2C) -#define FOC0B 6 -#define FOC0A 7 - -#define TCCR0B _SFR_IO8(0x2D) -#define CS00 0 -#define CS01 1 -#define CS02 2 -#define WGM02 3 -#define WGM03 4 -#define ICES0 6 -#define ICNC0 7 - -#define TCCR0A _SFR_IO8(0x2E) -#define WGM00 0 -#define WGM01 1 -#define COM0B0 4 -#define COM0B1 5 -#define COM0A0 6 -#define COM0A1 7 - -#define GTCCR _SFR_IO8(0x2F) -#define PSR 0 -#define TSM 7 - -#define WDTCSR _SFR_IO8(0x31) -#define WDP0 0 -#define WDP1 1 -#define WDP2 2 -#define WDE 3 -#define WDP3 5 -#define WDIE 6 -#define WDIF 7 - -#define NVMCSR _SFR_IO8(0x32) -#define NVMBSY 7 - -#define NVMCMD _SFR_IO8(0x33) -#define NVMCMD0 0 -#define NVMCMD1 1 -#define NVMCMD2 2 -#define NVMCMD3 3 -#define NVMCMD4 4 -#define NVMCMD5 5 - -#define VLMCSR _SFR_IO8(0x34) -#define VLM0 0 -#define VLM1 1 -#define VLM2 2 -#define VLMIE 6 -#define VLMF 7 - -#define PRR _SFR_IO8(0x35) -#define PRTIM0 0 -#define PRADC 1 - -#define __AVR_HAVE_PRR ((1< instead of this file." -#endif - -#ifndef _AVR_IOXXX_H_ -# define _AVR_IOXXX_H_ "iotn828.h" -#else -# error "Attempt to include more than one file." -#endif - -/* Registers and associated bit numbers */ - -#define PINA _SFR_IO8(0x00) -#define PINA7 7 -#define PINA6 6 -#define PINA5 5 -#define PINA4 4 -#define PINA3 3 -#define PINA2 2 -#define PINA1 1 -#define PINA0 0 - -#define DDRA _SFR_IO8(0x01) -#define DDRA7 7 -// Inserted "DDA7" from "DDRA7" due to compatibility -#define DDA7 7 -#define DDRA6 6 -// Inserted "DDA6" from "DDRA6" due to compatibility -#define DDA6 6 -#define DDRA5 5 -// Inserted "DDA5" from "DDRA5" due to compatibility -#define DDA5 5 -#define DDRA4 4 -// Inserted "DDA4" from "DDRA4" due to compatibility -#define DDA4 4 -#define DDRA3 3 -// Inserted "DDA3" from "DDRA3" due to compatibility -#define DDA3 3 -#define DDRA2 2 -// Inserted "DDA2" from "DDRA2" due to compatibility -#define DDA2 2 -#define DDRA1 1 -// Inserted "DDA1" from "DDRA1" due to compatibility -#define DDA1 1 -#define DDRA0 0 -// Inserted "DDA0" from "DDRA0" due to compatibility -#define DDA0 0 - -#define PORTA _SFR_IO8(0x02) -#define PORTA7 7 -#define PORTA6 6 -#define PORTA5 5 -#define PORTA4 4 -#define PORTA3 3 -#define PORTA2 2 -#define PORTA1 1 -#define PORTA0 0 - -#define PUEA _SFR_IO8(0x03) - -#define PINB _SFR_IO8(0x04) -#define PINB7 7 -#define PINB6 6 -#define PINB5 5 -#define PINB4 4 -#define PINB3 3 -#define PINB2 2 -#define PINB1 1 -#define PINB0 0 - -#define DDRB _SFR_IO8(0x05) -#define DDRB7 7 -// Inserted "DDB7" from "DDRB7" due to compatibility -#define DDB7 7 -#define DDRB6 6 -// Inserted "DDB6" from "DDRB6" due to compatibility -#define DDB6 6 -#define DDRB5 5 -// Inserted "DDB5" from "DDRB5" due to compatibility -#define DDB5 5 -#define DDRB4 4 -// Inserted "DDB4" from "DDRB4" due to compatibility -#define DDB4 4 -#define DDRB3 3 -// Inserted "DDB3" from "DDRB3" due to compatibility -#define DDB3 3 -#define DDRB2 2 -// Inserted "DDB2" from "DDRB2" due to compatibility -#define DDB2 2 -#define DDRB1 1 -// Inserted "DDB1" from "DDRB1" due to compatibility -#define DDB1 1 -#define DDRB0 0 -// Inserted "DDB0" from "DDRB0" due to compatibility -#define DDB0 0 - -#define PORTB _SFR_IO8(0x06) -#define PORTB7 7 -#define PORTB6 6 -#define PORTB5 5 -#define PORTB4 4 -#define PORTB3 3 -#define PORTB2 2 -#define PORTB1 1 -#define PORTB0 0 - -#define PUEB _SFR_IO8(0x07) - -#define PINC _SFR_IO8(0x08) -#define PINC7 7 -#define PINC6 6 -#define PINC5 5 -#define PINC4 4 -#define PINC3 3 -#define PINC2 2 -#define PINC1 1 -#define PINC0 0 - -#define DDRC _SFR_IO8(0x09) -#define DDRC7 7 -// Inserted "DDC7" from "DDRC7" due to compatibility -#define DDC7 7 -#define DDRC6 6 -// Inserted "DDC6" from "DDRC6" due to compatibility -#define DDC6 6 -#define DDRC5 5 -// Inserted "DDC5" from "DDRC5" due to compatibility -#define DDC5 5 -#define DDRC4 4 -// Inserted "DDC4" from "DDRC4" due to compatibility -#define DDC4 4 -#define DDRC3 3 -// Inserted "DDC3" from "DDRC3" due to compatibility -#define DDC3 3 -#define DDRC2 2 -// Inserted "DDC2" from "DDRC2" due to compatibility -#define DDC2 2 -#define DDRC1 1 -// Inserted "DDC1" from "DDRC1" due to compatibility -#define DDC1 1 -#define DDRC0 0 -// Inserted "DDC0" from "DDRC0" due to compatibility -#define DDC0 0 - -#define PORTC _SFR_IO8(0x0A) -#define PORTC7 7 -#define PORTC6 6 -#define PORTC5 5 -#define PORTC4 4 -#define PORTC3 3 -#define PORTC2 2 -#define PORTC1 1 -#define PORTC0 0 - -#define PUEC _SFR_IO8(0x0B) - -#define PIND _SFR_IO8(0x0C) -#define PIND3 3 -#define PIND2 2 -#define PIND1 1 -#define PIND0 0 - -#define DDRD _SFR_IO8(0x0D) -#define DDRD3 3 -// Inserted "DDD3" from "DDRD3" due to compatibility -#define DDD3 3 -#define DDRD2 2 -// Inserted "DDD2" from "DDRD2" due to compatibility -#define DDD2 2 -#define DDRD1 1 -// Inserted "DDD1" from "DDRD1" due to compatibility -#define DDD1 1 -#define DDRD0 0 -// Inserted "DDD0" from "DDRD0" due to compatibility -#define DDD0 0 - -#define PORTD _SFR_IO8(0x0E) -#define PORTD3 3 -#define PORTD2 2 -#define PORTD1 1 -#define PORTD0 0 - -#define PUED _SFR_IO8(0x0F) - -/* Reserved [0x10..0x13] */ - -#define PHDE _SFR_IO8(0x14) -#define PHDEC 2 - -#define TIFR0 _SFR_IO8(0x15) -#define TOV0 0 -#define OCF0A 1 -#define OCF0B 2 - -#define TIFR1 _SFR_IO8(0x16) -#define TOV1 0 -#define OCF1A 1 -#define OCF1B 2 -#define ICF1 5 - -/* Reserved [0x17..0x1A] */ - -#define PCIFR _SFR_IO8(0x1B) -#define PCIF0 0 -#define PCIF1 1 -#define PCIF2 2 -#define PCIF3 3 - -#define EIFR _SFR_IO8(0x1C) -#define INTF0 0 -#define INTF1 1 - -#define EIMSK _SFR_IO8(0x1D) -#define INT0 0 -#define INT1 1 - -#define GPIOR0 _SFR_IO8(0x1E) - -#define EECR _SFR_IO8(0x1F) -#define EERE 0 -#define EEPE 1 -#define EEMPE 2 -#define EERIE 3 -#define EEPM0 4 -#define EEPM1 5 - -#define EEDR _SFR_IO8(0x20) - -#define EEAR _SFR_IO8(0x21) - -/* Reserved [0x22] */ - -#define GTCCR _SFR_IO8(0x23) -#define PSRSYNC 0 -#define TSM 7 - -#define TCCR0A _SFR_IO8(0x24) -#define WGM00 0 -#define WGM01 1 -#define COM0B0 4 -#define COM0B1 5 -#define COM0A0 6 -#define COM0A1 7 - -#define TCCR0B _SFR_IO8(0x25) -#define CS00 0 -#define CS01 1 -#define CS02 2 -#define WGM02 3 -#define FOC0B 6 -#define FOC0A 7 - -#define TCNT0 _SFR_IO8(0x26) - -#define OCR0A _SFR_IO8(0x27) - -#define OCR0B _SFR_IO8(0x28) - -/* Reserved [0x29] */ - -#define GPIOR1 _SFR_IO8(0x2A) - -#define GPIOR2 _SFR_IO8(0x2B) - -#define SPCR _SFR_IO8(0x2C) -#define SPR0 0 -#define SPR1 1 -#define CPHA 2 -#define CPOL 3 -#define MSTR 4 -#define DORD 5 -#define SPE 6 -#define SPIE 7 - -#define SPSR _SFR_IO8(0x2D) -#define SPI2X 0 -#define WCOL 6 -#define SPIF 7 - -#define SPDR _SFR_IO8(0x2E) - -#define ACSRB _SFR_IO8(0x2F) -#define ACPMUX0 0 -#define ACPMUX1 1 -#define ACNMUX0 2 -#define ACNMUX1 3 -#define HLEV 6 -#define HSEL 7 - -#define ACSRA _SFR_IO8(0x30) -#define ACIS0 0 -#define ACIS1 1 -#define ACIC 2 -#define ACIE 3 -#define ACI 4 -#define ACO 5 -#define ACPMUX2 6 -#define ACD 7 - -/* Reserved [0x31..0x32] */ - -#define SMCR _SFR_IO8(0x33) -#define SE 0 -#define SM0 1 -#define SM1 2 - -#define MCUSR _SFR_IO8(0x34) -#define PORF 0 -#define EXTRF 1 -#define BORF 2 -#define WDRF 3 - -#define MCUCR _SFR_IO8(0x35) -#define IVSEL 1 - -#define CCP _SFR_IO8(0x36) - -#define SPMCSR _SFR_IO8(0x37) -#define SPMEN 0 -#define PGERS 1 -#define PGWRT 2 -#define RWFLB 3 -#define RWWSRE 4 -#define RSIG 5 -#define RWWSB 6 -#define SPMIE 7 - -/* Reserved [0x38..0x3C] */ - -/* SP [0x3D..0x3E] */ - -/* SREG [0x3F] */ - -#define WDTCSR _SFR_MEM8(0x60) -#define WDE 3 -#define WDP0 0 -#define WDP1 1 -#define WDP2 2 -#define WDP3 5 -#define WDIE 6 -#define WDIF 7 - -#define CLKPR _SFR_MEM8(0x61) -#define CLKPS0 0 -#define CLKPS1 1 -#define CLKPS2 2 -#define CLKPS3 3 - -/* Reserved [0x62..0x63] */ - -#define PRR _SFR_MEM8(0x64) -#define PRADC 0 -#define PRUSART0 1 -#define PRSPI 2 -#define PRTIM1 3 -#define PRTIM0 5 -#define PRTWI 7 - -#define __AVR_HAVE_PRR ((1< - -/* Constants */ -#define SPM_PAGESIZE 64 -#define RAMSTART (0x60) -#define RAMEND 0x25F -#define XRAMEND RAMEND -#define E2END 0x1FF -#define E2PAGESIZE 4 -#define FLASHEND 0x1FFF - - -/* Fuses */ -#define FUSE_MEMORY_SIZE 3 - -/* Low Fuse Byte */ -#define FUSE_CKSEL0 (unsigned char)~_BV(0) -#define FUSE_CKSEL1 (unsigned char)~_BV(1) -#define FUSE_CKSEL2 (unsigned char)~_BV(2) -#define FUSE_CKSEL3 (unsigned char)~_BV(3) -#define FUSE_SUT0 (unsigned char)~_BV(4) -#define FUSE_SUT1 (unsigned char)~_BV(5) -#define FUSE_CKOUT (unsigned char)~_BV(6) -#define FUSE_CKDIV8 (unsigned char)~_BV(7) -#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8) - -/* High Fuse Byte */ -#define FUSE_BODLEVEL0 (unsigned char)~_BV(0) -#define FUSE_BODLEVEL1 (unsigned char)~_BV(1) -#define FUSE_BODLEVEL2 (unsigned char)~_BV(2) -#define FUSE_EESAVE (unsigned char)~_BV(3) -#define FUSE_WDTON (unsigned char)~_BV(4) -#define FUSE_SPIEN (unsigned char)~_BV(5) -#define FUSE_DWEN (unsigned char)~_BV(6) -#define FUSE_RSTDISBL (unsigned char)~_BV(7) -#define HFUSE_DEFAULT (FUSE_SPIEN) - -/* Extended Fuse Byte */ -#define FUSE_SELFPRGEN (unsigned char)~_BV(0) -#define EFUSE_DEFAULT (0xFF) - - -/* Lock Bits */ -#define __LOCK_BITS_EXIST - - -/* Signature */ -#define SIGNATURE_0 0x1E -#define SIGNATURE_1 0x93 -#define SIGNATURE_2 0x0C - -#define SLEEP_MODE_IDLE (0x00<<3) -#define SLEEP_MODE_ADC (0x01<<3) -#define SLEEP_MODE_PWR_DOWN (0x02<<3) -#define SLEEP_MODE_STANDBY (0x03<<3) - -#endif /* _AVR_IOTN84_H_ */ diff --git a/arduino/hardware/tools/avr/avr/include/avr/iotn841.h b/arduino/hardware/tools/avr/avr/include/avr/iotn841.h deleted file mode 100644 index f8d9823..0000000 --- a/arduino/hardware/tools/avr/avr/include/avr/iotn841.h +++ /dev/null @@ -1,903 +0,0 @@ -/***************************************************************************** - * - * Copyright (C) 2015 Atmel Corporation - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * - * * Neither the name of the copyright holders nor the names of - * contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - ****************************************************************************/ - - -#ifndef _AVR_ATTINY841_H_INCLUDED -#define _AVR_ATTINY841_H_INCLUDED - - -#ifndef _AVR_IO_H_ -# error "Include instead of this file." -#endif - -#ifndef _AVR_IOXXX_H_ -# define _AVR_IOXXX_H_ "iotn841.h" -#else -# error "Attempt to include more than one file." -#endif - -/* Registers and associated bit numbers */ - -#define ADCSRB _SFR_IO8(0x04) -#define ADTS0 0 -#define ADTS1 1 -#define ADTS2 2 -#define ADLAR 3 - -#define ADCSRA _SFR_IO8(0x05) -#define ADPS0 0 -#define ADPS1 1 -#define ADPS2 2 -#define ADIE 3 -#define ADIF 4 -#define ADATE 5 -#define ADSC 6 -#define ADEN 7 - -/* Combine ADCL and ADCH */ -#ifndef __ASSEMBLER__ -#define ADC _SFR_IO16(0x06) -#endif -#define ADCW _SFR_IO16(0x06) - -#define ADCL _SFR_IO8(0x06) -#define ADCH _SFR_IO8(0x07) - -#define ADMUXB _SFR_IO8(0x08) -#define GSEL0 0 -#define GSEL1 1 -#define REFS0 5 -#define REFS1 6 -#define REFS2 7 - -#define ADMUXA _SFR_IO8(0x09) -#define MUX0 0 -#define MUX1 1 -#define MUX2 2 -#define MUX3 3 -#define MUX4 4 -#define MUX5 5 - -#define ACSR0A _SFR_IO8(0x0A) -#define ACIS00 0 -#define ACIS01 1 -#define ACIC0 2 -#define ACIE0 3 -#define ACI0 4 -#define ACO0 5 -#define ACPMUX2 6 -#define ACD0 7 - -#define ACSR0B _SFR_IO8(0x0B) -#define ACPMUX0 0 -#define ACPMUX1 1 -#define ACNMUX0 2 -#define ACNMUX1 3 -#define ACOE0 4 -#define HLEV0 6 -#define HSEL0 7 - -#define ACSR1A _SFR_IO8(0x0C) -#define ACIS10 0 -#define ACIS11 1 -#define ACIC1 2 -#define ACIE1 3 -#define ACI1 4 -#define ACO1 5 -#define ACBG1 6 -#define ACD1 7 - -#define ACSR1B _SFR_IO8(0x0D) -#define ACME1 2 -#define ACOE1 4 -#define HLEV1 6 -#define HSEL1 7 - -#define TIFR1 _SFR_IO8(0x0E) -#define TOV1 0 -#define OCF1A 1 -#define OCF1B 2 -#define ICF1 5 - -#define TIMSK1 _SFR_IO8(0x0F) -#define TOIE1 0 -#define OCIE1A 1 -#define OCIE1B 2 -#define ICIE1 5 - -#define TIFR2 _SFR_IO8(0x10) -#define TOV2 0 -#define OCF2A 1 -#define OCF2B 2 -#define ICF2 5 - -#define TIMSK2 _SFR_IO8(0x11) -#define TOIE2 0 -#define OCIE2A 1 -#define OCIE2B 2 -#define ICIE2 5 - -#define PCMSK0 _SFR_IO8(0x12) -#define PCINT0 0 -#define PCINT1 1 -#define PCINT2 2 -#define PCINT3 3 -#define PCINT4 4 -#define PCINT5 5 -#define PCINT6 6 -#define PCINT7 7 - -#define GPIOR0 _SFR_IO8(0x13) - -#define GPIOR1 _SFR_IO8(0x14) - -#define GPIOR2 _SFR_IO8(0x15) - -#define PINB _SFR_IO8(0x16) -#define PINB3 3 -#define PINB2 2 -#define PINB1 1 -#define PINB0 0 - -#define DDRB _SFR_IO8(0x17) -#define DDRB3 3 -// Inserted "DDB3" from "DDRB3" due to compatibility -#define DDB3 3 -#define DDRB2 2 -// Inserted "DDB2" from "DDRB2" due to compatibility -#define DDB2 2 -#define DDRB1 1 -// Inserted "DDB1" from "DDRB1" due to compatibility -#define DDB1 1 -#define DDRB0 0 -// Inserted "DDB0" from "DDRB0" due to compatibility -#define DDB0 0 - -#define PORTB _SFR_IO8(0x18) -#define PORTB3 3 -#define PORTB2 2 -#define PORTB1 1 -#define PORTB0 0 - -#define PINA _SFR_IO8(0x19) -#define PINA7 7 -#define PINA6 6 -#define PINA5 5 -#define PINA4 4 -#define PINA3 3 -#define PINA2 2 -#define PINA1 1 -#define PINA0 0 - -#define DDRA _SFR_IO8(0x1A) -#define DDRA7 7 -// Inserted "DDA7" from "DDRA7" due to compatibility -#define DDA7 7 -#define DDRA6 6 -// Inserted "DDA6" from "DDRA6" due to compatibility -#define DDA6 6 -#define DDRA5 5 -// Inserted "DDA5" from "DDRA5" due to compatibility -#define DDA5 5 -#define DDRA4 4 -// Inserted "DDA4" from "DDRA4" due to compatibility -#define DDA4 4 -#define DDRA3 3 -// Inserted "DDA3" from "DDRA3" due to compatibility -#define DDA3 3 -#define DDRA2 2 -// Inserted "DDA2" from "DDRA2" due to compatibility -#define DDA2 2 -#define DDRA1 1 -// Inserted "DDA1" from "DDRA1" due to compatibility -#define DDA1 1 -#define DDRA0 0 -// Inserted "DDA0" from "DDRA0" due to compatibility -#define DDA0 0 - -#define PORTA _SFR_IO8(0x1B) -#define PORTA7 7 -#define PORTA6 6 -#define PORTA5 5 -#define PORTA4 4 -#define PORTA3 3 -#define PORTA2 2 -#define PORTA1 1 -#define PORTA0 0 - -#define EECR _SFR_IO8(0x1C) -#define EERE 0 -#define EEPE 1 -#define EEMPE 2 -#define EERIE 3 -#define EEPM0 4 -#define EEPM1 5 - -#define EEDR _SFR_IO8(0x1D) - -/* Combine EEARL and EEARH */ -#define EEAR _SFR_IO16(0x1E) - -#define EEARL _SFR_IO8(0x1E) -#define EEARH _SFR_IO8(0x1F) - -#define PCMSK1 _SFR_IO8(0x20) -#define PCINT8 0 -#define PCINT9 1 -#define PCINT10 2 -#define PCINT11 3 - -#define WDTCSR _SFR_IO8(0x21) -#define WDE 3 -#define WDP0 0 -#define WDP1 1 -#define WDP2 2 -#define WDP3 5 -#define WDIE 6 -#define WDIF 7 - -#define TCCR1C _SFR_IO8(0x22) -#define FOC1B 6 -#define FOC1A 7 - -#define GTCCR _SFR_IO8(0x23) -#define PSR 0 -#define TSM 7 - -/* Combine ICR1L and ICR1H */ -#define ICR1 _SFR_IO16(0x24) - -#define ICR1L _SFR_IO8(0x24) -#define ICR1H _SFR_IO8(0x25) - -/* Reserved [0x26..0x27] */ - -/* Combine OCR1BL and OCR1BH */ -#define OCR1B _SFR_IO16(0x28) - -#define OCR1BL _SFR_IO8(0x28) -#define OCR1BH _SFR_IO8(0x29) - -/* Combine OCR1AL and OCR1AH */ -#define OCR1A _SFR_IO16(0x2A) - -#define OCR1AL _SFR_IO8(0x2A) -#define OCR1AH _SFR_IO8(0x2B) - -/* Combine TCNT1L and TCNT1H */ -#define TCNT1 _SFR_IO16(0x2C) - -#define TCNT1L _SFR_IO8(0x2C) -#define TCNT1H _SFR_IO8(0x2D) - -#define TCCR1B _SFR_IO8(0x2E) -#define CS10 0 -#define CS11 1 -#define CS12 2 -#define WGM12 3 -#define WGM13 4 -#define ICES1 6 -#define ICNC1 7 - -#define TCCR1A _SFR_IO8(0x2F) -#define WGM10 0 -#define WGM11 1 -#define COM1B0 4 -#define COM1B1 5 -#define COM1A0 6 -#define COM1A1 7 - -#define TCCR0A _SFR_IO8(0x30) -#define WGM00 0 -#define WGM01 1 -#define COM0B0 4 -#define COM0B1 5 -#define COM0A0 6 -#define COM0A1 7 - -/* Reserved [0x31] */ - -#define TCNT0 _SFR_IO8(0x32) - -#define TCCR0B _SFR_IO8(0x33) -#define CS00 0 -#define CS01 1 -#define CS02 2 -#define WGM02 3 -#define FOC0B 6 -#define FOC0A 7 - -#define MCUSR _SFR_IO8(0x34) -#define PORF 0 -#define EXTRF 1 -#define BORF 2 -#define WDRF 3 - -#define MCUCR _SFR_IO8(0x35) -#define ISC00 0 -#define ISC01 1 -#define SM0 3 -#define SM1 4 -#define SE 5 - -#define OCR0A _SFR_IO8(0x36) - -#define SPMCSR _SFR_IO8(0x37) -#define SPMEN 0 -#define PGERS 1 -#define PGWRT 2 -#define RFLB 3 -#define CTPB 4 -#define RSIG 5 - -#define TIFR0 _SFR_IO8(0x38) -#define TOV0 0 -#define OCF0A 1 -#define OCF0B 2 - -#define TIMSK0 _SFR_IO8(0x39) -#define TOIE0 0 -#define OCIE0A 1 -#define OCIE0B 2 - -#define GIFR _SFR_IO8(0x3A) -#define PCIF0 4 -#define PCIF1 5 -#define INTF0 6 - -#define GIMSK _SFR_IO8(0x3B) -#define PCIE0 4 -#define PCIE1 5 -#define INT0 6 - -#define OCR0B _SFR_IO8(0x3C) - -/* SP [0x3D..0x3E] */ - -/* SREG [0x3F] */ - -#define DIDR0 _SFR_MEM8(0x60) -#define ADC0D 0 -#define ADC1D 1 -#define ADC2D 2 -#define ADC3D 3 -#define ADC4D 4 -#define ADC5D 5 -#define ADC6D 6 -#define ADC7D 7 - -#define DIDR1 _SFR_MEM8(0x61) -#define ADC11D 0 -#define ADC10D 1 -#define ADC8D 2 -#define ADC9D 3 - -#define PUEB _SFR_MEM8(0x62) - -#define PUEA _SFR_MEM8(0x63) - -#define PORTCR _SFR_MEM8(0x64) -#define BBMB 1 -#define BBMA 0 - -#define REMAP _SFR_MEM8(0x65) -#define U0MAP 0 -#define SPIMAP 1 - -#define TOCPMCOE _SFR_MEM8(0x66) -#define TOCC0OE 0 -#define TOCC1OE 1 -#define TOCC2OE 2 -#define TOCC3OE 3 -#define TOCC4OE 4 -#define TOCC5OE 5 -#define TOCC6OE 6 -#define TOCC7OE 7 - -#define TOCPMSA0 _SFR_MEM8(0x67) -#define TOCC0S0 0 -#define TOCC0S1 1 -#define TOCC1S0 2 -#define TOCC1S1 3 -#define TOCC2S0 4 -#define TOCC2S1 5 -#define TOCC3S0 6 -#define TOCC3S1 7 - -#define TOCPMSA1 _SFR_MEM8(0x68) -#define TOCC4S0 0 -#define TOCC4S1 1 -#define TOCC5S0 2 -#define TOCC5S1 3 -#define TOCC6S0 4 -#define TOCC6S1 5 -#define TOCC7S0 6 -#define TOCC7S1 7 - -/* Reserved [0x69] */ - -#define PHDE _SFR_MEM8(0x6A) -#define PHDEA0 0 -#define PHDEA1 1 - -/* Reserved [0x6B..0x6F] */ - -#define PRR _SFR_MEM8(0x70) -#define PRADC 0 -#define PRTIM0 1 -#define PRTIM1 2 -#define PRTIM2 3 -#define PRSPI 4 -#define PRUSART0 5 -#define PRUSART1 6 -#define PRTWI 7 - -#define __AVR_HAVE_PRR ((1<, never directly. */ - -#ifndef _AVR_IO_H_ -# error "Include instead of this file." -#endif - -#ifndef _AVR_IOXXX_H_ -# define _AVR_IOXXX_H_ "iotn84a.h" -#else -# error "Attempt to include more than one file." -#endif - - -#ifndef _AVR_ATtiny84A_H_ -#define _AVR_ATtiny84A_H_ 1 - - -/* Registers and associated bit numbers. */ - -#define PRR _SFR_IO8(0x00) -#define PRADC 0 -#define PRUSI 1 -#define PRTIM0 2 -#define PRTIM1 3 - -#define __AVR_HAVE_PRR ((1< - -/* Constants */ -#define SPM_PAGESIZE 64 -#define RAMSTART (0x60) -#define RAMEND 0x25F -#define XRAMEND RAMEND -#define E2END 0x1FF -#define E2PAGESIZE 4 -#define FLASHEND 0x1FFF - - -/* Fuses */ -#define FUSE_MEMORY_SIZE 3 - -/* Low Fuse Byte */ -#define FUSE_CKSEL0 (unsigned char)~_BV(0) -#define FUSE_CKSEL1 (unsigned char)~_BV(1) -#define FUSE_CKSEL2 (unsigned char)~_BV(2) -#define FUSE_CKSEL3 (unsigned char)~_BV(3) -#define FUSE_SUT0 (unsigned char)~_BV(4) -#define FUSE_SUT1 (unsigned char)~_BV(5) -#define FUSE_CKOUT (unsigned char)~_BV(6) -#define FUSE_CKDIV8 (unsigned char)~_BV(7) -#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8) - -/* High Fuse Byte */ -#define FUSE_BODLEVEL0 (unsigned char)~_BV(0) -#define FUSE_BODLEVEL1 (unsigned char)~_BV(1) -#define FUSE_BODLEVEL2 (unsigned char)~_BV(2) -#define FUSE_EESAVE (unsigned char)~_BV(3) -#define FUSE_WDTON (unsigned char)~_BV(4) -#define FUSE_SPIEN (unsigned char)~_BV(5) -#define FUSE_DWEN (unsigned char)~_BV(6) -#define FUSE_RSTDISBL (unsigned char)~_BV(7) -#define HFUSE_DEFAULT (FUSE_SPIEN) - -/* Extended Fuse Byte */ -#define FUSE_SELFPRGEN (unsigned char)~_BV(0) -#define EFUSE_DEFAULT (0xFF) - - -/* Lock Bits */ -#define __LOCK_BITS_EXIST - - -/* Signature */ -#define SIGNATURE_0 0x1E -#define SIGNATURE_1 0x93 -#define SIGNATURE_2 0x0B - -#define SLEEP_MODE_IDLE (0x00<<3) -#define SLEEP_MODE_ADC (0x01<<3) -#define SLEEP_MODE_PWR_DOWN (0x02<<3) - -#endif /* _AVR_IOTN85_H_ */ diff --git a/arduino/hardware/tools/avr/avr/include/avr/iotn861.h b/arduino/hardware/tools/avr/avr/include/avr/iotn861.h deleted file mode 100644 index 16f1cf0..0000000 --- a/arduino/hardware/tools/avr/avr/include/avr/iotn861.h +++ /dev/null @@ -1,94 +0,0 @@ -/* Copyright (c) 2006, Anatoly Sokolov - All rights reserved. - - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - * Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - * Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in - the documentation and/or other materials provided with the - distribution. - - * Neither the name of the copyright holders nor the names of - contributors may be used to endorse or promote products derived - from this software without specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. */ - -/* $Id: iotn861.h 2115 2010-04-05 23:19:53Z arcanum $ */ - -/* avr/iotn861.h - definitions for ATtiny861 */ - -#ifndef _AVR_IOTN861_H_ -#define _AVR_IOTN861_H_ 1 - -#include - -/* Constants */ -#define SPM_PAGESIZE 64 -#define RAMSTART (0x60) -#define RAMEND 0x25F -#define XRAMEND RAMEND -#define E2END 0x1FF -#define E2PAGESIZE 4 -#define FLASHEND 0x1FFF - - -/* Fuses */ -#define FUSE_MEMORY_SIZE 3 - -/* Low Fuse Byte */ -#define FUSE_CKSEL0 (unsigned char)~_BV(0) -#define FUSE_CKSEL1 (unsigned char)~_BV(1) -#define FUSE_CKSEL2 (unsigned char)~_BV(2) -#define FUSE_CKSEL3 (unsigned char)~_BV(3) -#define FUSE_SUT0 (unsigned char)~_BV(4) -#define FUSE_SUT1 (unsigned char)~_BV(5) -#define FUSE_CKOUT (unsigned char)~_BV(6) -#define FUSE_CKDIV8 (unsigned char)~_BV(7) -#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8) - -/* High Fuse Byte */ -#define FUSE_BODLEVEL0 (unsigned char)~_BV(0) -#define FUSE_BODLEVEL1 (unsigned char)~_BV(1) -#define FUSE_BODLEVEL2 (unsigned char)~_BV(2) -#define FUSE_EESAVE (unsigned char)~_BV(3) -#define FUSE_WDTON (unsigned char)~_BV(4) -#define FUSE_SPIEN (unsigned char)~_BV(5) -#define FUSE_DWEN (unsigned char)~_BV(6) -#define FUSE_RSTDISBL (unsigned char)~_BV(7) -#define HFUSE_DEFAULT (FUSE_SPIEN) - -/* Extended Fuse Byte */ -#define FUSE_SELFPRGEN (unsigned char)~_BV(0) -#define EFUSE_DEFAULT (0xFF) - - -/* Lock Bits */ -#define __LOCK_BITS_EXIST - - -/* Signature */ -#define SIGNATURE_0 0x1E -#define SIGNATURE_1 0x93 -#define SIGNATURE_2 0x0D - -#define SLEEP_MODE_IDLE (0x00<<3) -#define SLEEP_MODE_ADC (0x01<<3) -#define SLEEP_MODE_PWR_DOWN (0x02<<3) -#define SLEEP_MODE_STANDBY (0x03<<3) - -#endif /* _AVR_IOTN861_H_ */ diff --git a/arduino/hardware/tools/avr/avr/include/avr/iotn861a.h b/arduino/hardware/tools/avr/avr/include/avr/iotn861a.h deleted file mode 100644 index efa691e..0000000 --- a/arduino/hardware/tools/avr/avr/include/avr/iotn861a.h +++ /dev/null @@ -1,988 +0,0 @@ -/* Copyright (c) 2009 Atmel Corporation - All rights reserved. - - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - * Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - * Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in - the documentation and/or other materials provided with the - distribution. - - * Neither the name of the copyright holders nor the names of - contributors may be used to endorse or promote products derived - from this software without specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. */ - -/* $Id: iotn861a.h 2063 2009-11-18 22:06:28Z arcanum $ */ - -/* avr/iotn861a.h - definitions for ATtiny861A */ - -/* This file should only be included from , never directly. */ - -#ifndef _AVR_IO_H_ -# error "Include instead of this file." -#endif - -#ifndef _AVR_IOXXX_H_ -# define _AVR_IOXXX_H_ "iotn861a.h" -#else -# error "Attempt to include more than one file." -#endif - - -#ifndef _AVR_ATtiny861A_H_ -#define _AVR_ATtiny861A_H_ 1 - - -/* Registers and associated bit numbers. */ - -#define TCCR1E _SFR_IO8(0x00) -#define OC1OE0 0 -#define OC1OE1 1 -#define OC1OE2 2 -#define OC1OE3 3 -#define OC1OE4 4 -#define OC1OE5 5 - -#define DIDR0 _SFR_IO8(0x01) -#define ADC0D 0 -#define ADC1D 1 -#define ADC2D 2 -#define AREFD 3 -#define ADC3D 4 -#define ADC4D 5 -#define ADC5D 6 -#define ADC6D 7 - -#define DIDR1 _SFR_IO8(0x02) -#define ADC7D 4 -#define ADC8D 5 -#define ADC9D 6 -#define ADC10D 7 - -#define ADCSRB _SFR_IO8(0x03) -#define ADTS0 0 -#define ADTS1 1 -#define ADTS2 2 -#define MUX5 3 -#define REFS2 4 -#define IPR 5 -#define GSEL 6 -#define BIN 7 - -#ifndef __ASSEMBLER__ -#define ADC _SFR_IO16(0x04) -#endif -#define ADCW _SFR_IO16(0x04) - -#define ADCL _SFR_IO8(0x04) -#define ADCL0 0 -#define ADCL1 1 -#define ADCL2 2 -#define ADCL3 3 -#define ADCL4 4 -#define ADCL5 5 -#define ADCL6 6 -#define ADCL7 7 - -#define ADCH _SFR_IO8(0x05) -#define ADCH0 0 -#define ADCH1 1 -#define ADCH2 2 -#define ADCH3 3 -#define ADCH4 4 -#define ADCH5 5 -#define ADCH6 6 -#define ADCH7 7 - -#define ADCSRA _SFR_IO8(0x06) -#define ADPS0 0 -#define ADPS1 1 -#define ADPS2 2 -#define ADIE 3 -#define ADIF 4 -#define ADATE 5 -#define ADSC 6 -#define ADEN 7 - -#define ADMUX _SFR_IO8(0x07) -#define MUX0 0 -#define MUX1 1 -#define MUX2 2 -#define MUX3 3 -#define MUX4 4 -#define ADLAR 5 -#define REFS0 6 -#define REFS1 7 - -#define ACSRA _SFR_IO8(0x08) -#define ACIS0 0 -#define ACIS1 1 -#define ACME 2 -#define ACIE 3 -#define ACI 4 -#define ACO 5 -#define ACBG 6 -#define ACD 7 - -#define ACSRB _SFR_IO8(0x09) -#define ACM0 0 -#define ACM1 1 -#define ACM2 2 -#define HLEV 6 -#define HSEL 7 - -#define GPIOR0 _SFR_IO8(0x0A) -#define GPIOR00 0 -#define GPIOR01 1 -#define GPIOR02 2 -#define GPIOR03 3 -#define GPIOR04 4 -#define GPIOR05 5 -#define GPIOR06 6 -#define GPIOR07 7 - -#define GPIOR1 _SFR_IO8(0x0B) -#define GPIOR10 0 -#define GPIOR11 1 -#define GPIOR12 2 -#define GPIOR13 3 -#define GPIOR14 4 -#define GPIOR15 5 -#define GPIOR16 6 -#define GPIOR17 7 - -#define GPIOR2 _SFR_IO8(0x0C) -#define GPIOR20 0 -#define GPIOR21 1 -#define GPIOR22 2 -#define GPIOR23 3 -#define GPIOR24 4 -#define GPIOR25 5 -#define GPIOR26 6 -#define GPIOR27 7 - -#define USICR _SFR_IO8(0x0D) -#define USITC 0 -#define USICLK 1 -#define USICS0 2 -#define USICS1 3 -#define USIWM0 4 -#define USIWM1 5 -#define USIOIE 6 -#define USISIE 7 - -#define USISR _SFR_IO8(0x0E) -#define USICNT0 0 -#define USICNT1 1 -#define USICNT2 2 -#define USICNT3 3 -#define USIDC 4 -#define USIPF 5 -#define USIOIF 6 -#define USISIF 7 - -#define USIDR _SFR_IO8(0x0F) -#define USIDR0 0 -#define USIDR1 1 -#define USIDR2 2 -#define USIDR3 3 -#define USIDR4 4 -#define USIDR5 5 -#define USIDR6 6 -#define USIDR7 7 - -#define USIBR _SFR_IO8(0x10) -#define USIBR0 0 -#define USIBR1 1 -#define USIBR2 2 -#define USIBR3 3 -#define USIBR4 4 -#define USIBR5 5 -#define USIBR6 6 -#define USIBR7 7 - -#define USIPP _SFR_IO8(0x11) -#define USIPOS 0 - -#define OCR0B _SFR_IO8(0x12) -#define OCR0B_0 0 -#define OCR0B_1 1 -#define OCR0B_2 2 -#define OCR0B_3 3 -#define OCR0B_4 4 -#define OCR0B_5 5 -#define OCR0B_6 6 -#define OCR0B_7 7 - -#define OCR0A _SFR_IO8(0x13) -#define OCR0A_0 0 -#define OCR0A_1 1 -#define OCR0A_2 2 -#define OCR0A_3 3 -#define OCR0A_4 4 -#define OCR0A_5 5 -#define OCR0A_6 6 -#define OCR0A_7 7 - -#define TCNT0H _SFR_IO8(0x14) -#define TCNT0H_0 0 -#define TCNT0H_1 1 -#define TCNT0H_2 2 -#define TCNT0H_3 3 -#define TCNT0H_4 4 -#define TCNT0H_5 5 -#define TCNT0H_6 6 -#define TCNT0H_7 7 - -#define TCCR0A _SFR_IO8(0x15) -#define WGM00 0 -#define ACIC0 3 -#define ICES0 4 -#define ICNC0 5 -#define ICEN0 6 -#define TCW0 7 - -#define PINB _SFR_IO8(0x16) -#define PINB0 0 -#define PINB1 1 -#define PINB2 2 -#define PINB3 3 -#define PINB4 4 -#define PINB5 5 -#define PINB6 6 -#define PINB7 7 - -#define DDRB _SFR_IO8(0x17) -#define DDB0 0 -#define DDB1 1 -#define DDB2 2 -#define DDB3 3 -#define DDB4 4 -#define DDB5 5 -#define DDB6 6 -#define DDB7 7 - -#define PORTB _SFR_IO8(0x18) -#define PORTB0 0 -#define PORTB1 1 -#define PORTB2 2 -#define PORTB3 3 -#define PORTB4 4 -#define PORTB5 5 -#define PORTB6 6 -#define PORTB7 7 - -#define PINA _SFR_IO8(0x19) -#define PINA0 0 -#define PINA1 1 -#define PINA2 2 -#define PINA3 3 -#define PINA4 4 -#define PINA5 5 -#define PINA6 6 -#define PINA7 7 - -#define DDRA _SFR_IO8(0x1A) -#define DDA0 0 -#define DDA1 1 -#define DDA2 2 -#define DDA3 3 -#define DDA4 4 -#define DDA5 5 -#define DDA6 6 -#define DDA7 7 - -#define PORTA _SFR_IO8(0x1B) -#define PORTA0 0 -#define PORTA1 1 -#define PORTA2 2 -#define PORTA3 3 -#define PORTA4 4 -#define PORTA5 5 -#define PORTA6 6 -#define PORTA7 7 - -#define EECR _SFR_IO8(0x1C) -#define EERE 0 -#define EEPE 1 -#define EEMPE 2 -#define EERIE 3 -#define EEPM0 4 -#define EEPM1 5 - -#define EEDR _SFR_IO8(0x1D) -#define EEDR0 0 -#define EEDR1 1 -#define EEDR2 2 -#define EEDR3 3 -#define EEDR4 4 -#define EEDR5 5 -#define EEDR6 6 -#define EEDR7 7 - -#define EEAR _SFR_IO16(0x1E) - -#define EEARL _SFR_IO8(0x1E) -#define EEAR0 0 -#define EEAR1 1 -#define EEAR2 2 -#define EEAR3 3 -#define EEAR4 4 -#define EEAR5 5 -#define EEAR6 6 -#define EEAR7 7 - -#define EEARH _SFR_IO8(0x1F) -#define EEAR8 0 - -#define DWDR _SFR_IO8(0x20) -#define DWDR0 0 -#define DWDR1 1 -#define DWDR2 2 -#define DWDR3 3 -#define DWDR4 4 -#define DWDR5 5 -#define DWDR6 6 -#define DWDR7 7 - -#define WDTCR _SFR_IO8(0x21) -#define WDP0 0 -#define WDP1 1 -#define WDP2 2 -#define WDE 3 -#define WDCE 4 -#define WDP3 5 -#define WDIE 6 -#define WDIF 7 - -#define PCMSK1 _SFR_IO8(0x22) -#define PCINT8 0 -#define PCINT9 1 -#define PCINT10 2 -#define PCINT11 3 -#define PCINT12 4 -#define PCINT13 5 -#define PCINT14 6 -#define PCINT15 7 - -#define PCMSK0 _SFR_IO8(0x23) -#define PCINT0 0 -#define PCINT1 1 -#define PCINT2 2 -#define PCINT3 3 -#define PCINT4 4 -#define PCINT5 5 -#define PCINT6 6 -#define PCINT7 7 - -#define DT1 _SFR_IO8(0x24) -#define DT1L0 0 -#define DT1L1 1 -#define DT1L2 2 -#define DT1L3 3 -#define DT1H0 4 -#define DT1H1 5 -#define DT1H2 6 -#define DT1H3 7 - -#define TC1H _SFR_IO8(0x25) -#define TC18 0 -#define TC19 1 - -#define TCCR1D _SFR_IO8(0x26) -#define WGM10 0 -#define WGM11 1 -#define FPF1 2 -#define FPAC1 3 -#define FPES1 4 -#define FPNC1 5 -#define FPEN1 6 -#define FPIE1 7 - -#define TCCR1C _SFR_IO8(0x27) -#define PWM1D 0 -#define FOC1D 1 -#define COM1D0 2 -#define COM1D1 3 -#define COM1B0S 4 -#define COM1B1S 5 -#define COM1A0S 6 -#define COM1A1S 7 - -#define CLKPR _SFR_IO8(0x28) -#define CLKPS0 0 -#define CLKPS1 1 -#define CLKPS2 2 -#define CLKPS3 3 -#define CLKPCE 7 - -#define PLLCSR _SFR_IO8(0x29) -#define PLOCK 0 -#define PLLE 1 -#define PCKE 2 -#define LSM 7 - -#define OCR1D _SFR_IO8(0x2A) -#define OCR1D0 0 -#define OCR1D1 1 -#define OCR1D2 2 -#define OCR1D3 3 -#define OCR1D4 4 -#define OCR1D5 5 -#define OCR1D6 6 -#define OCR1D7 7 - -#define OCR1C _SFR_IO8(0x2B) -#define OCR1C0 0 -#define OCR1C1 1 -#define OCR1C2 2 -#define OCR1C3 3 -#define OCR1C4 4 -#define OCR1C5 5 -#define OCR1C6 6 -#define OCR1C7 7 - -#define OCR1B _SFR_IO8(0x2C) -#define OCR1B0 0 -#define OCR1B1 1 -#define OCR1B2 2 -#define OCR1B3 3 -#define OCR1B4 4 -#define OCR1B5 5 -#define OCR1B6 6 -#define OCR1B7 7 - -#define OCR1A _SFR_IO8(0x2D) -#define OCR1A0 0 -#define OCR1A1 1 -#define OCR1A2 2 -#define OCR1A3 3 -#define OCR1A4 4 -#define OCR1A5 5 -#define OCR1A6 6 -#define OCR1A7 7 - -#define TCNT1 _SFR_IO8(0x2E) -#define TC1H_0 0 -#define TC1H_1 1 -#define TC1H_2 2 -#define TC1H_3 3 -#define TC1H_4 4 -#define TC1H_5 5 -#define TC1H_6 6 -#define TC1H_7 7 - -#define TCCR1B _SFR_IO8(0x2F) -#define CS10 0 -#define CS11 1 -#define CS12 2 -#define CS13 3 -#define DTPS10 4 -#define DTPS11 5 -#define PSR1 6 -#define PWM1X 7 - -#define TCCR1A _SFR_IO8(0x30) -#define PWM1B 0 -#define PWM1A 1 -#define FOC1B 2 -#define FOC1A 3 -#define COM1B0 4 -#define COM1B1 5 -#define COM1A0 6 -#define COM1A1 7 - -#define OSCCAL _SFR_IO8(0x31) -#define CAL0 0 -#define CAL1 1 -#define CAL2 2 -#define CAL3 3 -#define CAL4 4 -#define CAL5 5 -#define CAL6 6 -#define CAL7 7 - -#define TCNT0L _SFR_IO8(0x32) -#define TCNT0L_0 0 -#define TCNT0L_1 1 -#define TCNT0L_2 2 -#define TCNT0L_3 3 -#define TCNT0L_4 4 -#define TCNT0L_5 5 -#define TCNT0L_6 6 -#define TCNT0L_7 7 - -#define TCCR0B _SFR_IO8(0x33) -#define CS00 0 -#define CS01 1 -#define CS02 2 -#define PSR0 3 -#define TSM 4 - -#define MCUSR _SFR_IO8(0x34) -#define PORF 0 -#define EXTRF 1 -#define BORF 2 -#define WDRF 3 - -#define MCUCR _SFR_IO8(0x35) -#define ISC00 0 -#define ISC01 1 -#define BODSE 2 -#define SM0 3 -#define SM1 4 -#define SE 5 -#define PUD 6 -#define BODS 7 - -#define PRR _SFR_IO8(0x36) -#define PRADC 0 -#define PRUSI 1 -#define PRTIM0 2 -#define PRTIM1 3 - -#define __AVR_HAVE_PRR ((1<, never directly. */ - -#ifndef _AVR_IO_H_ -# error "Include instead of this file." -#endif - -#ifndef _AVR_IOXXX_H_ -# define _AVR_IOXXX_H_ "iotn87.h" -#else -# error "Attempt to include more than one file." -#endif - - -#ifndef _AVR_ATtiny87_H_ -#define _AVR_ATtiny87_H_ 1 - - -/* Registers and associated bit numbers. */ - -#define PINA _SFR_IO8(0x00) -#define PINA0 0 -#define PINA1 1 -#define PINA2 2 -#define PINA3 3 -#define PINA4 4 -#define PINA5 5 -#define PINA6 6 -#define PINA7 7 - -#define DDRA _SFR_IO8(0x01) -#define DDA0 0 -#define DDA1 1 -#define DDA2 2 -#define DDA3 3 -#define DDA4 4 -#define DDA5 5 -#define DDA6 6 -#define DDA7 7 - -#define PORTA _SFR_IO8(0x02) -#define PORTA0 0 -#define PORTA1 1 -#define PORTA2 2 -#define PORTA3 3 -#define PORTA4 4 -#define PORTA5 5 -#define PORTA6 6 -#define PORTA7 7 - -#define PINB _SFR_IO8(0x03) -#define PINB0 0 -#define PINB1 1 -#define PINB2 2 -#define PINB3 3 -#define PINB4 4 -#define PINB5 5 -#define PINB6 6 -#define PINB7 7 - -#define DDRB _SFR_IO8(0x04) -#define DDB0 0 -#define DDB1 1 -#define DDB2 2 -#define DDB3 3 -#define DDB4 4 -#define DDB5 5 -#define DDB6 6 -#define DDB7 7 - -#define PORTB _SFR_IO8(0x05) -#define PORTB0 0 -#define PORTB1 1 -#define PORTB2 2 -#define PORTB3 3 -#define PORTB4 4 -#define PORTB5 5 -#define PORTB6 6 -#define PORTB7 7 - -#define PORTCR _SFR_IO8(0x12) -#define PUDA 0 -#define PUDB 2 -#define BBMA 4 -#define BBMB 5 - -#define TIFR0 _SFR_IO8(0x15) -#define TOV0 0 -#define OCF0A 1 - -#define TIFR1 _SFR_IO8(0x16) -#define TOV1 0 -#define OCF1A 1 -#define OCF1B 2 -#define ICF1 5 - -#define PCIFR _SFR_IO8(0x1B) -#define PCIF0 0 -#define PCIF1 1 - -#define EIFR _SFR_IO8(0x1C) -#define INTF0 0 -#define INTF1 1 - -#define EIMSK _SFR_IO8(0x1D) -#define INT0 0 -#define INT1 1 - -#define GPIOR0 _SFR_IO8(0x1E) -#define GPIOR00 0 -#define GPIOR01 1 -#define GPIOR02 2 -#define GPIOR03 3 -#define GPIOR04 4 -#define GPIOR05 5 -#define GPIOR06 6 -#define GPIOR07 7 - -#define EECR _SFR_IO8(0x1F) -#define EERE 0 -#define EEPE 1 -#define EEMPE 2 -#define EERIE 3 -#define EEPM0 4 -#define EEPM1 5 - -#define EEDR _SFR_IO8(0x20) -#define EEDR0 0 -#define EEDR1 1 -#define EEDR2 2 -#define EEDR3 3 -#define EEDR4 4 -#define EEDR5 5 -#define EEDR6 6 -#define EEDR7 7 - -#define EEAR _SFR_IO16(0x21) - -#define EEARL _SFR_IO8(0x21) -#define EEAR0 0 -#define EEAR1 1 -#define EEAR2 2 -#define EEAR3 3 -#define EEAR4 4 -#define EEAR5 5 -#define EEAR6 6 -#define EEAR7 7 - -#define EEARH _SFR_IO8(0x22) -#define EEAR8 0 - -#define GTCCR _SFR_IO8(0x23) -#define PSR1 0 -#define PSR0 1 -#define TSM 7 - -#define TCCR0A _SFR_IO8(0x25) -#define WGM00 0 -#define WGM01 1 -#define COM0A0 6 -#define COM0A1 7 - -#define TCCR0B _SFR_IO8(0x26) -#define CS00 0 -#define CS01 1 -#define CS02 2 -#define FOC0A 7 - -#define TCNT0 _SFR_IO8(0x27) -#define TCNT00 0 -#define TCNT01 1 -#define TCNT02 2 -#define TCNT03 3 -#define TCNT04 4 -#define TCNT05 5 -#define TCNT06 6 -#define TCNT07 7 - -#define OCR0A _SFR_IO8(0x28) -#define OCR00 0 -#define OCR01 1 -#define OCR02 2 -#define OCR03 3 -#define OCR04 4 -#define OCR05 5 -#define OCR06 6 -#define OCR07 7 - -#define GPIOR1 _SFR_IO8(0x2A) -#define GPIOR10 0 -#define GPIOR11 1 -#define GPIOR12 2 -#define GPIOR13 3 -#define GPIOR14 4 -#define GPIOR15 5 -#define GPIOR16 6 -#define GPIOR17 7 - -#define GPIOR2 _SFR_IO8(0x2B) -#define GPIOR20 0 -#define GPIOR21 1 -#define GPIOR22 2 -#define GPIOR23 3 -#define GPIOR24 4 -#define GPIOR25 5 -#define GPIOR26 6 -#define GPIOR27 7 - -#define SPCR _SFR_IO8(0x2C) -#define SPR0 0 -#define SPR1 1 -#define CPHA 2 -#define CPOL 3 -#define MSTR 4 -#define DORD 5 -#define SPE 6 -#define SPIE 7 - -#define SPSR _SFR_IO8(0x2D) -#define SPI2X 0 -#define WCOL 6 -#define SPIF 7 - -#define SPDR _SFR_IO8(0x2E) -#define SPDR0 0 -#define SPDR1 1 -#define SPDR2 2 -#define SPDR3 3 -#define SPDR4 4 -#define SPDR5 5 -#define SPDR6 6 -#define SPDR7 7 - -#define ACSR _SFR_IO8(0x30) -#define ACIS0 0 -#define ACIS1 1 -#define ACIC 2 -#define ACIE 3 -#define ACI 4 -#define ACO 5 -#define ACIRS 6 -#define ACD 7 - -#define DWDR _SFR_IO8(0x31) -#define DWDR0 0 -#define DWDR1 1 -#define DWDR2 2 -#define DWDR3 3 -#define DWDR4 4 -#define DWDR5 5 -#define DWDR6 6 -#define DWDR7 7 - -#define SMCR _SFR_IO8(0x33) -#define SE 0 -#define SM0 1 -#define SM1 2 - -#define MCUSR _SFR_IO8(0x34) -#define PORF 0 -#define EXTRF 1 -#define BORF 2 -#define WDRF 3 - -#define MCUCR _SFR_IO8(0x35) -#define PUD 4 -#define BODSE 5 -#define BODS 6 - -#define SPMCSR _SFR_IO8(0x37) -#define SPMEN 0 -#define PGERS 1 -#define PGWRT 2 -#define RFLB 3 -#define CTPB 4 -#define SIGRD 5 -#define RWWSB 6 - -#define WDTCR _SFR_MEM8(0x60) -#define WDP0 0 -#define WDP1 1 -#define WDP2 2 -#define WDE 3 -#define WDCE 4 -#define WDP3 5 -#define WDIE 6 -#define WDIF 7 - -#define CLKPR _SFR_MEM8(0x61) -#define CLKPS0 0 -#define CLKPS1 1 -#define CLKPS2 2 -#define CLKPS3 3 -#define CLKPCE 7 - -#define CLKCSR _SFR_MEM8(0x62) -#define CLKC0 0 -#define CLKC1 1 -#define CLKC2 2 -#define CLKC3 3 -#define CLKRDY 4 -#define CLKCCE 7 - -#define CLKSELR _SFR_MEM8(0x63) -#define CSEL0 0 -#define CSEL1 1 -#define CSEL2 2 -#define CSEL3 3 -#define CSUT0 4 -#define CSUT1 5 -#define COUT 6 - -#define PRR _SFR_MEM8(0x64) -#define PRADC 0 -#define PRUSI 1 -#define PRTIM0 2 -#define PRTIM1 3 -#define PRSPI 4 -#define PRLIN 5 - -#define __AVR_HAVE_PRR ((1<, never directly. */ - -#ifndef _AVR_IO_H_ -# error "Include instead of this file." -#endif - -#ifndef _AVR_IOXXX_H_ -# define _AVR_IOXXX_H_ "iotn88.h" -#else -# error "Attempt to include more than one file." -#endif - - -#ifndef _AVR_IOTN88_H_ -#define _AVR_IOTN88_H_ 1 - -/* Registers and associated bit numbers */ - -#define PINB _SFR_IO8(0x03) -#define PINB0 0 -#define PINB1 1 -#define PINB2 2 -#define PINB3 3 -#define PINB4 4 -#define PINB5 5 -#define PINB6 6 -#define PINB7 7 - -#define DDRB _SFR_IO8(0x04) -#define DDB0 0 -#define DDB1 1 -#define DDB2 2 -#define DDB3 3 -#define DDB4 4 -#define DDB5 5 -#define DDB6 6 -#define DDB7 7 - -#define PORTB _SFR_IO8(0x05) -#define PORTB0 0 -#define PORTB1 1 -#define PORTB2 2 -#define PORTB3 3 -#define PORTB4 4 -#define PORTB5 5 -#define PORTB6 6 -#define PORTB7 7 - -#define PINC _SFR_IO8(0x06) -#define PINC0 0 -#define PINC1 1 -#define PINC2 2 -#define PINC3 3 -#define PINC4 4 -#define PINC5 5 -#define PINC6 6 -#define PINC7 7 - -#define DDRC _SFR_IO8(0x07) -#define DDC0 0 -#define DDC1 1 -#define DDC2 2 -#define DDC3 3 -#define DDC4 4 -#define DDC5 5 -#define DDC6 6 -#define DDC7 7 - -#define PORTC _SFR_IO8(0x08) -#define PORTC0 0 -#define PORTC1 1 -#define PORTC2 2 -#define PORTC3 3 -#define PORTC4 4 -#define PORTC5 5 -#define PORTC6 6 -#define PORTC7 7 - -#define PIND _SFR_IO8(0x09) -#define PIND0 0 -#define PIND1 1 -#define PIND2 2 -#define PIND3 3 -#define PIND4 4 -#define PIND5 5 -#define PIND6 6 -#define PIND7 7 - -#define DDRD _SFR_IO8(0x0A) -#define DDD0 0 -#define DDD1 1 -#define DDD2 2 -#define DDD3 3 -#define DDD4 4 -#define DDD5 5 -#define DDD6 6 -#define DDD7 7 - -#define PORTD _SFR_IO8(0x0B) -#define PORTD0 0 -#define PORTD1 1 -#define PORTD2 2 -#define PORTD3 3 -#define PORTD4 4 -#define PORTD5 5 -#define PORTD6 6 -#define PORTD7 7 - -#define PINA _SFR_IO8(0x0C) -#define PINA0 0 -#define PINA1 1 -#define PINA2 2 -#define PINA3 3 - -#define DDRA _SFR_IO8(0x0D) -#define DDA0 0 -#define DDA1 1 -#define DDA2 2 -#define DDA3 3 - -#define PORTA _SFR_IO8(0x0E) -#define PORTA0 0 -#define PORTA1 1 -#define PORTA2 2 -#define PORTA3 3 - -#define PORTCR _SFR_IO8(0x12) -#define PUDA 0 -#define PUDB 1 -#define PUDC 2 -#define PUDD 3 -#define BBMA 4 -#define BBMB 5 -#define BBMC 6 -#define BBMD 7 - -#define TIFR0 _SFR_IO8(0x15) -#define TOV0 0 -#define OCF0A 1 -#define OCF0B 2 - -#define TIFR1 _SFR_IO8(0x16) -#define TOV1 0 -#define OCF1A 1 -#define OCF1B 2 -#define ICF1 5 - -#define PCIFR _SFR_IO8(0x1B) -#define PCIF0 0 -#define PCIF1 1 -#define PCIF2 2 -#define PCIF3 3 - -#define EIFR _SFR_IO8(0x1C) -#define INTF0 0 -#define INTF1 1 - -#define EIMSK _SFR_IO8(0x1D) -#define INT0 0 -#define INT1 1 - -#define GPIOR0 _SFR_IO8(0x1E) -#define GPIOR00 0 -#define GPIOR01 1 -#define GPIOR02 2 -#define GPIOR03 3 -#define GPIOR04 4 -#define GPIOR05 5 -#define GPIOR06 6 -#define GPIOR07 7 - -#define EECR _SFR_IO8(0x1F) -#define EERE 0 -#define EEPE 1 -#define EEMPE 2 -#define EERIE 3 -#define EEPM0 4 -#define EEPM1 5 - -#define EEDR _SFR_IO8(0x20) -#define EEDR0 0 -#define EEDR1 1 -#define EEDR2 2 -#define EEDR3 3 -#define EEDR4 4 -#define EEDR5 5 -#define EEDR6 6 -#define EEDR7 7 - -#define EEARL _SFR_IO8(0x21) -#define EEAR0 0 -#define EEAR1 1 -#define EEAR2 2 -#define EEAR3 3 -#define EEAR4 4 -#define EEAR5 5 -#define EEAR6 6 -#define EEAR7 7 - -#define GTCCR _SFR_IO8(0x23) -#define PSRSYNC 0 -#define TSM 7 - -#define TCCR0A _SFR_IO8(0x25) -#define CS00 0 -#define CS01 1 -#define CS02 2 -#define CTC0 3 - -#define TCNT0 _SFR_IO8(0x26) -#define TCNT0_0 0 -#define TCNT0_1 1 -#define TCNT0_2 2 -#define TCNT0_3 3 -#define TCNT0_4 4 -#define TCNT0_5 5 -#define TCNT0_6 6 -#define TCNT0_7 7 - -#define OCR0A _SFR_IO8(0x27) -#define OCR0A_0 0 -#define OCR0A_1 1 -#define OCR0A_2 2 -#define OCR0A_3 3 -#define OCR0A_4 4 -#define OCR0A_5 5 -#define OCR0A_6 6 -#define OCR0A_7 7 - -#define OCR0B _SFR_IO8(0x28) -#define OCR0B_0 0 -#define OCR0B_1 1 -#define OCR0B_2 2 -#define OCR0B_3 3 -#define OCR0B_4 4 -#define OCR0B_5 5 -#define OCR0B_6 6 -#define OCR0B_7 7 - -#define GPIOR1 _SFR_IO8(0x2A) -#define GPIOR10 0 -#define GPIOR11 1 -#define GPIOR12 2 -#define GPIOR13 3 -#define GPIOR14 4 -#define GPIOR15 5 -#define GPIOR16 6 -#define GPIOR17 7 - -#define GPIOR2 _SFR_IO8(0x2B) -#define GPIOR20 0 -#define GPIOR21 1 -#define GPIOR22 2 -#define GPIOR23 3 -#define GPIOR24 4 -#define GPIOR25 5 -#define GPIOR26 6 -#define GPIOR27 7 - -#define SPCR _SFR_IO8(0x2C) -#define SPR0 0 -#define SPR1 1 -#define CPHA 2 -#define CPOL 3 -#define MSTR 4 -#define DORD 5 -#define SPE 6 -#define SPIE 7 - -#define SPSR _SFR_IO8(0x2D) -#define SPI2X 0 -#define WCOL 6 -#define SPIF 7 - -#define SPDR _SFR_IO8(0x2E) -#define SPDR0 0 -#define SPDR1 1 -#define SPDR2 2 -#define SPDR3 3 -#define SPDR4 4 -#define SPDR5 5 -#define SPDR6 6 -#define SPDR7 7 - -#define ACSR _SFR_IO8(0x30) -#define ACIS0 0 -#define ACIS1 1 -#define ACIC 2 -#define ACIE 3 -#define ACI 4 -#define ACO 5 -#define ACBG 6 -#define ACD 7 - -#define SMCR _SFR_IO8(0x33) -#define SE 0 -#define SM0 1 -#define SM1 2 - -#define MCUSR _SFR_IO8(0x34) -#define PORF 0 -#define EXTRF 1 -#define BORF 2 -#define WDRF 3 - -#define MCUCR _SFR_IO8(0x35) -#define PUD 4 -#define BODSE 5 -#define BODS 6 - -#define SPMCSR _SFR_IO8(0x37) -#define SELFPRGEN 0 -#define PGERS 1 -#define PGWRT 2 -#define RFLB 3 -#define CTPB 4 -#define RWWSB 6 - -#define WDTCSR _SFR_MEM8(0x60) -#define WDP0 0 -#define WDP1 1 -#define WDP2 2 -#define WDE 3 -#define WDCE 4 -#define WDP3 5 -#define WDIE 6 -#define WDIF 7 - -#define CLKPR _SFR_MEM8(0x61) -#define CLKPS0 0 -#define CLKPS1 1 -#define CLKPS2 2 -#define CLKPS3 3 -#define CLKPCE 7 - -#define PRR _SFR_MEM8(0x64) -#define PRADC 0 -#define PRSPI 2 -#define PRTIM1 3 -#define PRTIM0 5 -#define PRTWI 7 - -#define __AVR_HAVE_PRR ((1<, never directly. */ - -#ifndef _AVR_IO_H_ -# error "Include instead of this file." -#endif - -#ifndef _AVR_IOXXX_H_ -# define _AVR_IOXXX_H_ "iotn9.h" -#else -# error "Attempt to include more than one file." -#endif - - -#ifndef _AVR_ATtiny9_H_ -#define _AVR_ATtiny9_H_ 1 - - -/* Registers and associated bit numbers. */ - -#define PINB _SFR_IO8(0x00) -#define PINB0 0 -#define PINB1 1 -#define PINB2 2 -#define PINB3 3 - -#define DDRB _SFR_IO8(0x01) -#define DDB0 0 -#define DDB1 1 -#define DDB2 2 -#define DDB3 3 - -#define PORTB _SFR_IO8(0x02) -#define PORTB0 0 -#define PORTB1 1 -#define PORTB2 2 -#define PORTB3 3 - -#define PUEB _SFR_IO8(0x03) -#define PUEB0 0 -#define PUEB1 1 -#define PUEB2 2 -#define PUEB3 3 - -#define PORTCR _SFR_IO8(0x0C) -#define BBMB 1 - -#define PCMSK _SFR_IO8(0x10) -#define PCINT0 0 -#define PCINT1 1 -#define PCINT2 2 -#define PCINT3 3 - -#define PCIFR _SFR_IO8(0x11) -#define PCIF0 0 - -#define PCICR _SFR_IO8(0x12) -#define PCIE0 0 - -#define EIMSK _SFR_IO8(0x13) -#define INT0 0 - -#define EIFR _SFR_IO8(0x14) -#define INTF0 0 - -#define EICRA _SFR_IO8(0x15) -#define ISC00 0 -#define ISC01 1 - -#define DIDR0 _SFR_IO8(0x17) -#define AIN0D 0 -#define AIN1D 1 - -#define ACSR _SFR_IO8(0x1F) -#define ACIS0 0 -#define ACIS1 1 -#define ACIC 2 -#define ACIE 3 -#define ACI 4 -#define ACO 5 -#define ACD 7 - -#define ICR0 _SFR_IO16(0x22) - -#define ICR0L _SFR_IO8(0x22) -#define ICR0_0 0 -#define ICR0_1 1 -#define ICR0_2 2 -#define ICR0_3 3 -#define ICR0_4 4 -#define ICR0_5 5 -#define ICR0_6 6 -#define ICR0_7 7 - -#define ICR0H _SFR_IO8(0x23) -#define ICR0_8 0 -#define ICR0_9 1 -#define ICR0_10 2 -#define ICR0_11 3 -#define ICR0_12 4 -#define ICR0_13 5 -#define ICR0_14 6 -#define ICR0_15 7 - -#define OCR0B _SFR_IO16(0x24) - -#define OCR0BL _SFR_IO8(0x24) -#define OCR0B0 0 -#define OCR0B1 1 -#define OCR0B2 2 -#define OCR0B3 3 -#define OCR0B4 4 -#define OCR0B5 5 -#define OCR0B6 6 -#define OCR0B7 7 - -#define OCR0BH _SFR_IO8(0x25) -#define OCR0B8 0 -#define OCR0B9 1 -#define OCR0B10 2 -#define OCR0B11 3 -#define OCR0B12 4 -#define OCR0B13 5 -#define OCR0B14 6 -#define OCR0B15 7 - -#define OCR0A _SFR_IO16(0x26) - -#define OCR0AL _SFR_IO8(0x26) -#define OCR0A0 0 -#define OCR0A1 1 -#define OCR0A2 2 -#define OCR0A3 3 -#define OCR0A4 4 -#define OCR0A5 5 -#define OCR0A6 6 -#define OCR0A7 7 - -#define OCR0AH _SFR_IO8(0x27) -#define OCR0A8 0 -#define OCR0A9 1 -#define OCR0A10 2 -#define OCR0A11 3 -#define OCR0A12 4 -#define OCR0A13 5 -#define OCR0A14 6 -#define OCR0A15 7 - -#define TCNT0 _SFR_IO16(0x28) - -#define TCNT0L _SFR_IO8(0x28) -#define TCNT0_0 0 -#define TCNT0_1 1 -#define TCNT0_2 2 -#define TCNT0_3 3 -#define TCNT0_4 4 -#define TCNT0_5 5 -#define TCNT0_6 6 -#define TCNT0_7 7 - -#define TCNT0H _SFR_IO8(0x29) -#define TCNT0_8 0 -#define TCNT0_9 1 -#define TCNT0_10 2 -#define TCNT0_11 3 -#define TCNT0_12 4 -#define TCNT0_13 5 -#define TCNT0_14 6 -#define TCNT0_15 7 - -#define TIFR0 _SFR_IO8(0x2A) -#define TOV0 0 -#define OCF0A 1 -#define OCF0B 2 -#define ICF0 5 - -#define TIMSK0 _SFR_IO8(0x2B) -#define TOIE0 0 -#define OCIE0A 1 -#define OCIE0B 2 -#define ICIE0 5 - -#define TCCR0C _SFR_IO8(0x2C) -#define FOC0B 6 -#define FOC0A 7 - -#define TCCR0B _SFR_IO8(0x2D) -#define CS00 0 -#define CS01 1 -#define CS02 2 -#define WGM02 3 -#define WGM03 4 -#define ICES0 6 -#define ICNC0 7 - -#define TCCR0A _SFR_IO8(0x2E) -#define WGM00 0 -#define WGM01 1 -#define COM0B0 4 -#define COM0B1 5 -#define COM0A0 6 -#define COM0A1 7 - -#define GTCCR _SFR_IO8(0x2F) -#define PSR 0 -#define TSM 7 - -#define WDTCSR _SFR_IO8(0x31) -#define WDP0 0 -#define WDP1 1 -#define WDP2 2 -#define WDE 3 -#define WDP3 5 -#define WDIE 6 -#define WDIF 7 - -#define NVMCSR _SFR_IO8(0x32) -#define NVMBSY 7 - -#define NVMCMD _SFR_IO8(0x33) -#define NVMCMD0 0 -#define NVMCMD1 1 -#define NVMCMD2 2 -#define NVMCMD3 3 -#define NVMCMD4 4 -#define NVMCMD5 5 - -#define VLMCSR _SFR_IO8(0x34) -#define VLM0 0 -#define VLM1 1 -#define VLM2 2 -#define VLMIE 6 -#define VLMF 7 - -#define PRR _SFR_IO8(0x35) -#define PRTIM0 0 -#define PRADC 1 - -#define __AVR_HAVE_PRR ((1<, never directly. */ - -#ifndef _AVR_IO_H_ -# error "Include instead of this file." -#endif - -#ifndef _AVR_IOXXX_H_ -# define _AVR_IOXXX_H_ "iotnx4.h" -#else -# error "Attempt to include more than one file." -#endif - -/* I/O registers */ - -#define PRR _SFR_IO8 (0x00) -#define PRTIM1 3 -#define PRTIM0 2 -#define PRUSI 1 -#define PRADC 0 - -#define __AVR_HAVE_PRR ((1<] */ -/* 0x3F SREG [defined in ] */ - -///--- - -/* Interrupt vectors */ -/* Interrupt vector 0 is the reset vector. */ -/* External Interrupt Request 0 */ -#define INT0_vect_num 1 -#define INT0_vect _VECTOR(1) -#define EXT_INT0_vect_num 1 -#define EXT_INT0_vect _VECTOR(1) -#define SIG_INTERRUPT0 _VECTOR(1) - -/* Pin Change Interrupt Request 0 */ -#define PCINT0_vect_num 2 -#define PCINT0_vect _VECTOR(2) -#define SIG_PIN_CHANGE0 _VECTOR(2) - -/* Pin Change Interrupt Request 1 */ -#define PCINT1_vect_num 3 -#define PCINT1_vect _VECTOR(3) -#define SIG_PIN_CHANGE1 _VECTOR(3) - -/* Watchdog Time-out */ -#define WDT_vect_num 4 -#define WDT_vect _VECTOR(4) -#define WATCHDOG_vect_num 4 -#define WATCHDOG_vect _VECTOR(4) -#define SIG_WATCHDOG_TIMEOUT _VECTOR(4) - -/* Timer/Counter1 Capture Event */ -#define TIMER1_CAPT_vect_num 5 -#define TIMER1_CAPT_vect _VECTOR(5) -#define TIM1_CAPT_vect_num 5 -#define TIM1_CAPT_vect _VECTOR(5) -#define SIG_INPUT_CAPTURE1 _VECTOR(5) - -/* Timer/Counter1 Compare Match A */ -#define TIM1_COMPA_vect_num 6 -#define TIM1_COMPA_vect _VECTOR(6) -#define SIG_OUTPUT_COMPARE1A _VECTOR(6) - -/* Timer/Counter1 Compare Match B */ -#define TIM1_COMPB_vect_num 7 -#define TIM1_COMPB_vect _VECTOR(7) -#define SIG_OUTPUT_COMPARE1B _VECTOR(7) - -/* Timer/Counter1 Overflow */ -#define TIM1_OVF_vect_num 8 -#define TIM1_OVF_vect _VECTOR(8) -#define SIG_OVERFLOW1 _VECTOR(8) - -/* Timer/Counter0 Compare Match A */ -#define TIM0_COMPA_vect_num 9 -#define TIM0_COMPA_vect _VECTOR(9) -#define SIG_OUTPUT_COMPARE0A _VECTOR(9) - -/* Timer/Counter0 Compare Match B */ -#define TIM0_COMPB_vect_num 10 -#define TIM0_COMPB_vect _VECTOR(10) -#define SIG_OUTPUT_COMPARE0B _VECTOR(10) - -/* Timer/Counter0 Overflow */ -#define TIM0_OVF_vect_num 11 -#define TIM0_OVF_vect _VECTOR(11) -#define SIG_OVERFLOW0 _VECTOR(11) - -/* Analog Comparator */ -#define ANA_COMP_vect_num 12 -#define ANA_COMP_vect _VECTOR(12) -#define SIG_COMPARATOR _VECTOR(12) - -/* ADC Conversion Complete */ -#define ADC_vect_num 13 -#define ADC_vect _VECTOR(13) -#define SIG_ADC _VECTOR(13) - -/* EEPROM Ready */ -#define EE_RDY_vect_num 14 -#define EE_RDY_vect _VECTOR(14) -#define SIG_EEPROM_READY _VECTOR(14) - -/* USI START */ -#define USI_START_vect_num 15 -#define USI_START_vect _VECTOR(15) -#define USI_STR_vect_num 15 -#define USI_STR_vect _VECTOR(15) -#define SIG_USI_START _VECTOR(15) - -/* USI Overflow */ -#define USI_OVF_vect_num 16 -#define USI_OVF_vect _VECTOR(16) -#define SIG_USI_OVERFLOW _VECTOR(16) - -#define _VECTORS_SIZE 34 - -#endif /* _AVR_IOTNX4_H_ */ diff --git a/arduino/hardware/tools/avr/avr/include/avr/iotnx5.h b/arduino/hardware/tools/avr/avr/include/avr/iotnx5.h deleted file mode 100644 index 4ad9052..0000000 --- a/arduino/hardware/tools/avr/avr/include/avr/iotnx5.h +++ /dev/null @@ -1,442 +0,0 @@ -/* Copyright (c) 2005,2007 Anatoly Sokolov - All rights reserved. - - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - * Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - * Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in - the documentation and/or other materials provided with the - distribution. - - * Neither the name of the copyright holders nor the names of - contributors may be used to endorse or promote products derived - from this software without specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. */ - -/* $Id: iotnx5.h 2269 2011-12-29 08:07:25Z joerg_wunsch $ */ - -/* avr/iotnx5.h - definitions for ATtiny25, ATtiny45 and ATtiny85 */ - -#ifndef _AVR_IOTNX5_H_ -#define _AVR_IOTNX5_H_ 1 - -/* This file should only be included from , never directly. */ - -#ifndef _AVR_IO_H_ -# error "Include instead of this file." -#endif - -#ifndef _AVR_IOXXX_H_ -# define _AVR_IOXXX_H_ "iotnx5.h" -#else -# error "Attempt to include more than one file." -#endif - -/* I/O registers */ - -/* Reserved [0x00..0x02] */ - -#define ADCSRB _SFR_IO8 (0x03) -#define BIN 7 -#define ACME 6 -#define IPR 5 -#define ADTS2 2 -#define ADTS1 1 -#define ADTS0 0 - -#ifndef __ASSEMBLER__ -#define ADC _SFR_IO16(0x04) -#endif -#define ADCW _SFR_IO16(0x04) -#define ADCL _SFR_IO8(0x04) -#define ADCH _SFR_IO8(0x05) - -#define ADCSRA _SFR_IO8 (0x06) -#define ADEN 7 -#define ADSC 6 -#define ADATE 5 -#define ADIF 4 -#define ADIE 3 -#define ADPS2 2 -#define ADPS1 1 -#define ADPS0 0 - -#define ADMUX _SFR_IO8(0x07) -#define REFS1 7 -#define REFS0 6 -#define ADLAR 5 -#define REFS2 4 -#define MUX3 3 -#define MUX2 2 -#define MUX1 1 -#define MUX0 0 - -#define ACSR _SFR_IO8(0x08) -#define ACD 7 -#define ACBG 6 -#define ACO 5 -#define ACI 4 -#define ACIE 3 -#define ACIS1 1 -#define ACIS0 0 - -/* Reserved [0x09..0x0C] */ - -#define USICR _SFR_IO8(0x0D) -#define USISIE 7 -#define USIOIE 6 -#define USIWM1 5 -#define USIWM0 4 -#define USICS1 3 -#define USICS0 2 -#define USICLK 1 -#define USITC 0 - -#define USISR _SFR_IO8(0x0E) -#define USISIF 7 -#define USIOIF 6 -#define USIPF 5 -#define USIDC 4 -#define USICNT3 3 -#define USICNT2 2 -#define USICNT1 1 -#define USICNT0 0 - -#define USIDR _SFR_IO8(0x0F) -#define USIBR _SFR_IO8(0x10) - -#define GPIOR0 _SFR_IO8(0x11) -#define GPIOR1 _SFR_IO8(0x12) -#define GPIOR2 _SFR_IO8(0x13) - -#define DIDR0 _SFR_IO8(0x14) -#define ADC0D 5 -#define ADC2D 4 -#define ADC3D 3 -#define ADC1D 2 -#define AIN1D 1 -#define AIN0D 0 - -#define PCMSK _SFR_IO8(0x15) -#define PCINT5 5 -#define PCINT4 4 -#define PCINT3 3 -#define PCINT2 2 -#define PCINT1 1 -#define PCINT0 0 - -#define PINB _SFR_IO8(0x16) -#define PINB5 5 -#define PINB4 4 -#define PINB3 3 -#define PINB2 2 -#define PINB1 1 -#define PINB0 0 - -#define DDRB _SFR_IO8(0x17) -#define DDB5 5 -#define DDB4 4 -#define DDB3 3 -#define DDB2 2 -#define DDB1 1 -#define DDB0 0 - -#define PORTB _SFR_IO8(0x18) -#define PB5 5 -#define PB4 4 -#define PB3 3 -#define PB2 2 -#define PB1 1 -#define PB0 0 - -/* Reserved [0x19..0x1B] */ - -/* EEPROM Control Register EECR */ -#define EECR _SFR_IO8(0x1C) -#define EEPM1 5 -#define EEPM0 4 -#define EERIE 3 -#define EEMPE 2 -#define EEPE 1 -#define EERE 0 - -/* EEPROM Data Register */ -#define EEDR _SFR_IO8(0x1D) - -/* EEPROM Address Register */ -#define EEAR _SFR_IO16(0x1E) -#define EEARL _SFR_IO8(0x1E) -#define EEARH _SFR_IO8(0x1F) - -#define PRR _SFR_IO8(0x20) -#define PRTIM1 3 -#define PRTIM0 2 -#define PRUSI 1 -#define PRADC 0 - -#define __AVR_HAVE_PRR ((1<] */ -/* 0x3F SREG [defined in ] */ - -///--- - -/* Interrupt vectors */ -/* Interrupt vector 0 is the reset vector. */ -/* External Interrupt 0 */ -#define INT0_vect_num 1 -#define INT0_vect _VECTOR(1) -#define SIG_INTERRUPT0 _VECTOR(1) - -/* Pin change Interrupt Request 0 */ -#define PCINT0_vect_num 2 -#define PCINT0_vect _VECTOR(2) -#define SIG_PIN_CHANGE _VECTOR(2) - -/* Timer/Counter1 Compare Match 1A */ -#define TIM1_COMPA_vect_num 3 -#define TIM1_COMPA_vect _VECTOR(3) -#define TIMER1_COMPA_vect_num 3 -#define TIMER1_COMPA_vect _VECTOR(3) -#define SIG_OUTPUT_COMPARE1A _VECTOR(3) - -/* Timer/Counter1 Overflow */ -#define TIM1_OVF_vect_num 4 -#define TIM1_OVF_vect _VECTOR(4) -#define TIMER1_OVF_vect_num 4 -#define TIMER1_OVF_vect _VECTOR(4) -#define SIG_OVERFLOW1 _VECTOR(4) - -/* Timer/Counter0 Overflow */ -#define TIM0_OVF_vect_num 5 -#define TIM0_OVF_vect _VECTOR(5) -#define TIMER0_OVF_vect_num 5 -#define TIMER0_OVF_vect _VECTOR(5) -#define SIG_OVERFLOW0 _VECTOR(5) - -/* EEPROM Ready */ -#define EE_RDY_vect_num 6 -#define EE_RDY_vect _VECTOR(6) -#define SIG_EEPROM_READY _VECTOR(6) - -/* Analog comparator */ -#define ANA_COMP_vect_num 7 -#define ANA_COMP_vect _VECTOR(7) -#define SIG_COMPARATOR _VECTOR(7) - -/* ADC Conversion ready */ -#define ADC_vect_num 8 -#define ADC_vect _VECTOR(8) -#define SIG_ADC _VECTOR(8) - -/* Timer/Counter1 Compare Match B */ -#define TIM1_COMPB_vect_num 9 -#define TIM1_COMPB_vect _VECTOR(9) -#define TIMER1_COMPB_vect_num 9 -#define TIMER1_COMPB_vect _VECTOR(9) -#define SIG_OUTPUT_COMPARE1B _VECTOR(9) - -/* Timer/Counter0 Compare Match A */ -#define TIM0_COMPA_vect_num 10 -#define TIM0_COMPA_vect _VECTOR(10) -#define TIMER0_COMPA_vect_num 10 -#define TIMER0_COMPA_vect _VECTOR(10) -#define SIG_OUTPUT_COMPARE0A _VECTOR(10) - -/* Timer/Counter0 Compare Match B */ -#define TIM0_COMPB_vect_num 11 -#define TIM0_COMPB_vect _VECTOR(11) -#define TIMER0_COMPB_vect_num 11 -#define TIMER0_COMPB_vect _VECTOR(11) -#define SIG_OUTPUT_COMPARE0B _VECTOR(11) - -/* Watchdog Time-out */ -#define WDT_vect_num 12 -#define WDT_vect _VECTOR(12) -#define SIG_WATCHDOG_TIMEOUT _VECTOR(12) - -/* USI START */ -#define USI_START_vect_num 13 -#define USI_START_vect _VECTOR(13) -#define SIG_USI_START _VECTOR(13) - -/* USI Overflow */ -#define USI_OVF_vect_num 14 -#define USI_OVF_vect _VECTOR(14) -#define SIG_USI_OVERFLOW _VECTOR(14) - -#define _VECTORS_SIZE 30 - -#endif /* _AVR_IOTNX5_H_ */ diff --git a/arduino/hardware/tools/avr/avr/include/avr/iotnx61.h b/arduino/hardware/tools/avr/avr/include/avr/iotnx61.h deleted file mode 100644 index 3e811c1..0000000 --- a/arduino/hardware/tools/avr/avr/include/avr/iotnx61.h +++ /dev/null @@ -1,541 +0,0 @@ -/* Copyright (c) 2006, 2007 Anatoly Sokolov - All rights reserved. - - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - * Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - * Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in - the documentation and/or other materials provided with the - distribution. - - * Neither the name of the copyright holders nor the names of - contributors may be used to endorse or promote products derived - from this software without specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. */ - -/* $Id: iotnx61.h 2247 2011-05-23 19:39:56Z joerg_wunsch $ */ - -/* avr/iotnx61.h - definitions for ATtiny261, ATtiny461 and ATtiny861 */ - -/* This file should only be included from , never directly. */ - -#ifndef _AVR_IO_H_ -# error "Include instead of this file." -#endif - -#ifndef _AVR_IOXXX_H_ -# define _AVR_IOXXX_H_ "iotnx61.h" -#else -# error "Attempt to include more than one file." -#endif - -#ifndef _AVR_IOTNx61_H_ -#define _AVR_IOTNx61_H_ 1 - -/* Registers and associated bit numbers */ - -#define TCCR1E _SFR_IO8(0x00) -#define OC1OE0 0 -#define OC1OE1 1 -#define OC1OE2 2 -#define OC1OE3 3 -#define OC1OE4 4 -#define OC1OE5 5 - -#define DIDR0 _SFR_IO8(0x01) -#define ADC0D 0 -#define ADC1D 1 -#define ADC2D 2 -#define AREFD 3 -#define ADC3D 4 -#define ADC4D 5 -#define ADC5D 6 -#define ADC6D 7 - -#define DIDR1 _SFR_IO8(0x02) -#define ADC7D 4 -#define ADC8D 5 -#define ADC9D 6 -#define ADC10D 7 - -#define ADCSRB _SFR_IO8(0x03) -#define ADTS0 0 -#define ADTS1 1 -#define ADTS2 2 -#define MUX5 3 -#define REFS2 4 -#define IRP 5 -#define GSEL 6 -#define BIN 7 - -#define ADCW _SFR_IO16(0x04) -#ifndef __ASSEMBLER__ -#define ADC _SFR_IO16(0x04) -#endif - -#define ADCL _SFR_IO8(0x04) -#define ADCH _SFR_IO8(0x05) - -#define ADCSRA _SFR_IO8(0x06) -#define ADPS0 0 -#define ADPS1 1 -#define ADPS2 2 -#define ADIE 3 -#define ADIF 4 -#define ADATE 5 -#define ADSC 6 -#define ADEN 7 - -#define ADMUX _SFR_IO8(0x07) -#define MUX0 0 -#define MUX1 1 -#define MUX2 2 -#define MUX3 3 -#define MUX4 4 -#define ADLAR 5 -#define REFS0 6 -#define REFS1 7 - -#define ACSRA _SFR_IO8(0x08) -#define ACIS0 0 -#define ACIS1 1 -#define ACME 2 -#define ACIE 3 -#define ACI 4 -#define ACO 5 -#define ACBG 6 -#define ACD 7 - -#define ACSRB _SFR_IO8(0x09) -#define ACM0 0 -#define ACM1 1 -#define ACM2 2 -#define HLEV 6 -#define HSEL 7 - -#define GPIOR0 _SFR_IO8(0x0A) - -#define GPIOR1 _SFR_IO8(0x0B) - -#define GPIOR2 _SFR_IO8(0x0C) - -#define USICR _SFR_IO8(0x0D) -#define USITC 0 -#define USICLK 1 -#define USICS0 2 -#define USICS1 3 -#define USIWM0 4 -#define USIWM1 5 -#define USIOIE 6 -#define USISIE 7 - -#define USISR _SFR_IO8(0x0E) -#define USICNT0 0 -#define USICNT1 1 -#define USICNT2 2 -#define USICNT3 3 -#define USIDC 4 -#define USIPF 5 -#define USIOIF 6 -#define USISIF 7 - -#define USIDR _SFR_IO8(0x0F) - -#define USIBR _SFR_IO8(0x10) - -#define USIPP _SFR_IO8(0x11) -#define USIPOS 0 - -#define OCR0B _SFR_IO8(0x12) - -#define OCR0A _SFR_IO8(0x13) - -#define TCNT0H _SFR_IO8(0x14) - -#define TCCR0A _SFR_IO8(0x15) -#define WGM00 0 /* up to at least datasheet rev. B */ -#define CTC0 0 /* newer revisions; change not mentioned - * in revision history */ -#define ACIC0 3 -#define ICES0 4 -#define ICNC0 5 -#define ICEN0 6 -#define TCW0 7 - -#define PINB _SFR_IO8(0x16) -#define PINB0 0 -#define PINB1 1 -#define PINB2 2 -#define PINB3 3 -#define PINB4 4 -#define PINB5 5 -#define PINB6 6 -#define PINB7 7 - -#define DDRB _SFR_IO8(0x17) -#define DDB0 0 -#define DDB1 1 -#define DDB2 2 -#define DDB3 3 -#define DDB4 4 -#define DDB5 5 -#define DDB6 6 -#define DDB7 7 - -#define PORTB _SFR_IO8(0x18) -#define PB0 0 -#define PB1 1 -#define PB2 2 -#define PB3 3 -#define PB4 4 -#define PB5 5 -#define PB6 6 -#define PB7 7 - -#define PINA _SFR_IO8(0x19) -#define PINA0 0 -#define PINA1 1 -#define PINA2 2 -#define PINA3 3 -#define PINA4 4 -#define PINA5 5 -#define PINA6 6 -#define PINA7 7 - -#define DDRA _SFR_IO8(0x1A) -#define DDA0 0 -#define DDA1 1 -#define DDA2 2 -#define DDA3 3 -#define DDA4 4 -#define DDA5 5 -#define DDA6 6 -#define DDA7 7 - -#define PORTA _SFR_IO8(0x1B) -#define PA0 0 -#define PA1 1 -#define PA2 2 -#define PA3 3 -#define PA4 4 -#define PA5 5 -#define PA6 6 -#define PA7 7 - -/* EEPROM Control Register */ -#define EECR _SFR_IO8(0x1C) -#define EERE 0 -#define EEPE 1 -#define EEMPE 2 -#define EERIE 3 -#define EEPM0 4 -#define EEPM1 5 - -/* EEPROM Data Register */ -#define EEDR _SFR_IO8(0x1D) - -/* EEPROM Address Register */ -#define EEAR _SFR_IO16(0x1E) -#define EEARL _SFR_IO8(0x1E) -#define EEARH _SFR_IO8(0x1F) - -#define DWDR _SFR_IO8(0x20) - -#define WDTCR _SFR_IO8(0x21) -#define WDP0 0 -#define WDP1 1 -#define WDP2 2 -#define WDE 3 -#define WDCE 4 -#define WDP3 5 -#define WDIE 6 -#define WDIF 7 - -#define PCMSK1 _SFR_IO8(0x22) -#define PCINT8 0 -#define PCINT9 1 -#define PCINT10 2 -#define PCINT11 3 -#define PCINT12 4 -#define PCINT13 5 -#define PCINT14 6 -#define PCINT15 7 - -#define PCMSK0 _SFR_IO8(0x23) -#define PCINT0 0 -#define PCINT1 1 -#define PCINT2 2 -#define PCINT3 3 -#define PCINT4 4 -#define PCINT5 5 -#define PCINT6 6 -#define PCINT7 7 - -#define DT1 _SFR_IO8(0x24) -#define DT1L0 0 -#define DT1L1 1 -#define DT1L2 2 -#define DT1L3 3 -#define DT1H0 4 -#define DT1H1 5 -#define DT1H2 6 -#define DT1H3 7 - -#define TC1H _SFR_IO8(0x25) -#define TC18 0 -#define TC19 1 - -#define TCCR1D _SFR_IO8(0x26) -#define WGM10 0 -#define WGM11 1 -#define FPF1 2 -#define FPAC1 3 -#define FPES1 4 -#define FPNC1 5 -#define FPEN1 6 -#define FPIE1 7 - -#define TCCR1C _SFR_IO8(0x27) -#define PWM1D 0 -#define FOC1D 1 -#define COM1D0 2 -#define COM1D1 3 -#define COM1B0S 4 -#define COM1B1S 5 -#define COM1A0S 6 -#define COM1A1S 7 - -#define CLKPR _SFR_IO8(0x28) -#define CLKPS0 0 -#define CLKPS1 1 -#define CLKPS2 2 -#define CLKPS3 3 -#define CLKPCE 7 - -#define PLLCSR _SFR_IO8(0x29) -#define PLOCK 0 -#define PLLE 1 -#define PCKE 2 -#define LSM 7 - -#define OCR1D _SFR_IO8(0x2A) - -#define OCR1C _SFR_IO8(0x2B) - -#define OCR1B _SFR_IO8(0x2C) - -#define OCR1A _SFR_IO8(0x2D) - -#define TCNT1 _SFR_IO8(0x2E) - -#define TCCR1B _SFR_IO8(0x2F) -#define CS10 0 -#define CS11 1 -#define CS12 2 -#define CS13 3 -#define DTPS10 4 -#define DTPS11 5 -#define PSR1 6 -#define PWM1X 7 - -#define TCCR1A _SFR_IO8(0x30) -#define PWM1B 0 -#define PWM1A 1 -#define FOC1B 2 -#define FOC1A 3 -#define COM1B0 4 -#define COM1B1 5 -#define COM1A0 6 -#define COM1A1 7 - -#define OSCCAL _SFR_IO8(0x31) - -#define TCNT0L _SFR_IO8(0x32) - -#define TCCR0B _SFR_IO8(0x33) -#define CS00 0 -#define CS01 1 -#define CS02 2 -#define PSR0 3 -#define TSM 4 - -#define MCUSR _SFR_IO8(0x34) -#define PORF 0 -#define EXTRF 1 -#define BORF 2 -#define WDRF 3 - -#define MCUCR _SFR_IO8(0x35) -#define ISC00 0 -#define ISC01 1 -#define SM0 3 -#define SM1 4 -#define SE 5 -#define PUD 6 - -#define PRR _SFR_IO8(0x36) -#define PRADC 0 -#define PRUSI 1 -#define PRTIM0 2 -#define PRTIM1 3 - -#define __AVR_HAVE_PRR ((1<] */ -/* 0x3F SREG [defined in ] */ - - -/* Interrupt vectors */ -/* Interrupt vector 0 is the reset vector. */ -/* External Interrupt 0 */ -#define INT0_vect_num 1 -#define INT0_vect _VECTOR(1) -#define SIG_INTERRUPT0 _VECTOR(1) - -/* Pin Change Interrupt */ -#define PCINT_vect_num 2 -#define PCINT_vect _VECTOR(2) -#define SIG_PIN_CHANGE _VECTOR(2) - -/* Timer/Counter1 Compare Match 1A */ -#define TIMER1_COMPA_vect_num 3 -#define TIMER1_COMPA_vect _VECTOR(3) -#define SIG_OUTPUT_COMPARE1A _VECTOR(3) - -/* Timer/Counter1 Compare Match 1B */ -#define TIMER1_COMPB_vect_num 4 -#define TIMER1_COMPB_vect _VECTOR(4) -#define SIG_OUTPUT_COMPARE1B _VECTOR(4) - -/* Timer/Counter1 Overflow */ -#define TIMER1_OVF_vect_num 5 -#define TIMER1_OVF_vect _VECTOR(5) -#define SIG_OVERFLOW1 _VECTOR(5) - -/* Timer/Counter0 Overflow */ -#define TIMER0_OVF_vect_num 6 -#define TIMER0_OVF_vect _VECTOR(6) -#define SIG_OVERFLOW0 _VECTOR(6) - -/* USI Start */ -#define USI_START_vect_num 7 -#define USI_START_vect _VECTOR(7) -#define SIG_USI_START _VECTOR(7) - -/* USI Overflow */ -#define USI_OVF_vect_num 8 -#define USI_OVF_vect _VECTOR(8) -#define SIG_USI_OVERFLOW _VECTOR(8) - -/* EEPROM Ready */ -#define EE_RDY_vect_num 9 -#define EE_RDY_vect _VECTOR(9) -#define SIG_EEPROM_READY _VECTOR(9) - -/* Analog Comparator */ -#define ANA_COMP_vect_num 10 -#define ANA_COMP_vect _VECTOR(10) -#define SIG_ANA_COMP _VECTOR(10) -#define SIG_COMPARATOR _VECTOR(10) - -/* ADC Conversion Complete */ -#define ADC_vect_num 11 -#define ADC_vect _VECTOR(11) -#define SIG_ADC _VECTOR(11) - -/* Watchdog Time-Out */ -#define WDT_vect_num 12 -#define WDT_vect _VECTOR(12) -#define SIG_WDT _VECTOR(12) - -/* External Interrupt 1 */ -#define INT1_vect_num 13 -#define INT1_vect _VECTOR(13) -#define SIG_INTERRUPT1 _VECTOR(13) - -/* Timer/Counter0 Compare Match A */ -#define TIMER0_COMPA_vect_num 14 -#define TIMER0_COMPA_vect _VECTOR(14) -#define SIG_OUTPUT_COMPARE0A _VECTOR(14) - -/* Timer/Counter0 Compare Match B */ -#define TIMER0_COMPB_vect_num 15 -#define TIMER0_COMPB_vect _VECTOR(15) -#define SIG_OUTPUT_COMPARE0B _VECTOR(15) - -/* ADC Conversion Complete */ -#define TIMER0_CAPT_vect_num 16 -#define TIMER0_CAPT_vect _VECTOR(16) -#define SIG_INPUT_CAPTURE0 _VECTOR(16) - -/* Timer/Counter1 Compare Match D */ -#define TIMER1_COMPD_vect_num 17 -#define TIMER1_COMPD_vect _VECTOR(17) -#define SIG_OUTPUT_COMPARE0D _VECTOR(17) - -/* Timer/Counter1 Fault Protection */ -#define FAULT_PROTECTION_vect_num 18 -#define FAULT_PROTECTION_vect _VECTOR(18) - -#define _VECTORS_SIZE 38 - -#endif /* _AVR_IOTNx61_H_ */ diff --git a/arduino/hardware/tools/avr/avr/include/avr/iousb1286.h b/arduino/hardware/tools/avr/avr/include/avr/iousb1286.h deleted file mode 100644 index b67e5b3..0000000 --- a/arduino/hardware/tools/avr/avr/include/avr/iousb1286.h +++ /dev/null @@ -1,101 +0,0 @@ -/* Copyright (c) 2006 Anatoly Sokolov - All rights reserved. - - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - * Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - * Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in - the documentation and/or other materials provided with the - distribution. - - * Neither the name of the copyright holders nor the names of - contributors may be used to endorse or promote products derived - from this software without specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. */ - -/* $Id: iousb1286.h 2102 2010-03-16 22:52:39Z joerg_wunsch $ */ - -/* avr/iousb1286.h - definitions for AT90USB1286 */ - -#ifndef _AVR_AT90USB1286_H_ -#define _AVR_AT90USB1286_H_ 1 - -#include - -/* Constants */ -#define SPM_PAGESIZE 256 -#define RAMSTART 0x100 -#define RAMEND 0x20FF -#define XRAMEND 0xFFFF -#define E2END 0xFFF -#define E2PAGESIZE 8 -#define FLASHEND 0x1FFFF - - -/* Fuses */ -#define FUSE_MEMORY_SIZE 3 - -/* Low Fuse Byte */ -#define FUSE_CKSEL0 (unsigned char)~_BV(0) -#define FUSE_CKSEL1 (unsigned char)~_BV(1) -#define FUSE_CKSEL2 (unsigned char)~_BV(2) -#define FUSE_CKSEL3 (unsigned char)~_BV(3) -#define FUSE_SUT0 (unsigned char)~_BV(4) -#define FUSE_SUT1 (unsigned char)~_BV(5) -#define FUSE_CKOUT (unsigned char)~_BV(6) -#define FUSE_CKDIV8 (unsigned char)~_BV(7) -#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8) - -/* High Fuse Byte */ -#define FUSE_BOOTRST (unsigned char)~_BV(0) -#define FUSE_BOOTSZ0 (unsigned char)~_BV(1) -#define FUSE_BOOTSZ1 (unsigned char)~_BV(2) -#define FUSE_EESAVE (unsigned char)~_BV(3) -#define FUSE_WDTON (unsigned char)~_BV(4) -#define FUSE_SPIEN (unsigned char)~_BV(5) -#define FUSE_JTAGEN (unsigned char)~_BV(6) -#define FUSE_OCDEN (unsigned char)~_BV(7) -#define HFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_SPIEN & FUSE_JTAGEN) - -/* Extended Fuse Byte */ -#define FUSE_BODLEVEL0 (unsigned char)~_BV(0) -#define FUSE_BODLEVEL1 (unsigned char)~_BV(1) -#define FUSE_BODLEVEL2 (unsigned char)~_BV(2) -#define FUSE_HWBE (unsigned char)~_BV(3) -#define EFUSE_DEFAULT (FUSE_BODLEVEL2 & FUSE_HWBE) - - -/* Lock Bits */ -#define __LOCK_BITS_EXIST -#define __BOOT_LOCK_BITS_0_EXIST -#define __BOOT_LOCK_BITS_1_EXIST - - -/* Signature */ -#define SIGNATURE_0 0x1E -#define SIGNATURE_1 0x97 -#define SIGNATURE_2 0x82 - -#define SLEEP_MODE_IDLE (0x00<<1) -#define SLEEP_MODE_ADC (0x01<<1) -#define SLEEP_MODE_PWR_DOWN (0x02<<1) -#define SLEEP_MODE_PWR_SAVE (0x03<<1) -#define SLEEP_MODE_STANDBY (0x06<<1) -#define SLEEP_MODE_EXT_STANDBY (0x07<<1) - -#endif /* _AVR_AT90USB1286_H_ */ diff --git a/arduino/hardware/tools/avr/avr/include/avr/iousb1287.h b/arduino/hardware/tools/avr/avr/include/avr/iousb1287.h deleted file mode 100644 index 076d478..0000000 --- a/arduino/hardware/tools/avr/avr/include/avr/iousb1287.h +++ /dev/null @@ -1,101 +0,0 @@ -/* Copyright (c) 2006 Anatoly Sokolov - All rights reserved. - - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - * Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - * Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in - the documentation and/or other materials provided with the - distribution. - - * Neither the name of the copyright holders nor the names of - contributors may be used to endorse or promote products derived - from this software without specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. */ - -/* $Id: iousb1287.h 2102 2010-03-16 22:52:39Z joerg_wunsch $ */ - -/* avr/iousb1287.h - definitions for AT90USB1287 */ - -#ifndef _AVR_AT90USB1287_H_ -#define _AVR_AT90USB1287_H_ 1 - -#include - -/* Constants */ -#define SPM_PAGESIZE 256 -#define RAMSTART 0x100 -#define RAMEND 0x20FF -#define XRAMEND 0xFFFF -#define E2END 0xFFF -#define E2PAGESIZE 8 -#define FLASHEND 0x1FFFF - - -/* Fuses */ -#define FUSE_MEMORY_SIZE 3 - -/* Low Fuse Byte */ -#define FUSE_CKSEL0 (unsigned char)~_BV(0) -#define FUSE_CKSEL1 (unsigned char)~_BV(1) -#define FUSE_CKSEL2 (unsigned char)~_BV(2) -#define FUSE_CKSEL3 (unsigned char)~_BV(3) -#define FUSE_SUT0 (unsigned char)~_BV(4) -#define FUSE_SUT1 (unsigned char)~_BV(5) -#define FUSE_CKOUT (unsigned char)~_BV(6) -#define FUSE_CKDIV8 (unsigned char)~_BV(7) -#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8) - -/* High Fuse Byte */ -#define FUSE_BOOTRST (unsigned char)~_BV(0) -#define FUSE_BOOTSZ0 (unsigned char)~_BV(1) -#define FUSE_BOOTSZ1 (unsigned char)~_BV(2) -#define FUSE_EESAVE (unsigned char)~_BV(3) -#define FUSE_WDTON (unsigned char)~_BV(4) -#define FUSE_SPIEN (unsigned char)~_BV(5) -#define FUSE_JTAGEN (unsigned char)~_BV(6) -#define FUSE_OCDEN (unsigned char)~_BV(7) -#define HFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_SPIEN & FUSE_JTAGEN) - -/* Extended Fuse Byte */ -#define FUSE_BODLEVEL0 (unsigned char)~_BV(0) -#define FUSE_BODLEVEL1 (unsigned char)~_BV(1) -#define FUSE_BODLEVEL2 (unsigned char)~_BV(2) -#define FUSE_HWBE (unsigned char)~_BV(3) -#define EFUSE_DEFAULT (FUSE_BODLEVEL2 & FUSE_HWBE) - - -/* Lock Bits */ -#define __LOCK_BITS_EXIST -#define __BOOT_LOCK_BITS_0_EXIST -#define __BOOT_LOCK_BITS_1_EXIST - - -/* Signature */ -#define SIGNATURE_0 0x1E -#define SIGNATURE_1 0x97 -#define SIGNATURE_2 0x82 - -#define SLEEP_MODE_IDLE (0x00<<1) -#define SLEEP_MODE_ADC (0x01<<1) -#define SLEEP_MODE_PWR_DOWN (0x02<<1) -#define SLEEP_MODE_PWR_SAVE (0x03<<1) -#define SLEEP_MODE_STANDBY (0x06<<1) -#define SLEEP_MODE_EXT_STANDBY (0x07<<1) - -#endif /* _AVR_AT90USB1287_H_ */ diff --git a/arduino/hardware/tools/avr/avr/include/avr/iousb162.h b/arduino/hardware/tools/avr/avr/include/avr/iousb162.h deleted file mode 100644 index 5c02eb2..0000000 --- a/arduino/hardware/tools/avr/avr/include/avr/iousb162.h +++ /dev/null @@ -1,101 +0,0 @@ -/* Copyright (c) 2007 Anatoly Sokolov - Copyright (c) 2010 Atmel Corporation - All rights reserved. - - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - * Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - * Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in - the documentation and/or other materials provided with the - distribution. - - * Neither the name of the copyright holders nor the names of - contributors may be used to endorse or promote products derived - from this software without specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. */ - -/* $Id: iousb162.h 2102 2010-03-16 22:52:39Z joerg_wunsch $ */ - -/* avr/iousb162.h - definitions for AT90USB162 */ - -#ifndef _AVR_AT90USB162_H_ -#define _AVR_AT90USB162_H_ 1 - -#include - -/* Constants */ -#define SPM_PAGESIZE 128 -#define RAMSTART 0x100 -#define RAMEND 0x2FF -#define XRAMEND RAMEND -#define E2END 0x1FF -#define E2PAGESIZE 4 -#define FLASHEND 0x3FFF - - -/* Fuses */ -#define FUSE_MEMORY_SIZE 3 - -/* Low Fuse Byte */ -#define FUSE_CKSEL0 (unsigned char)~_BV(0) -#define FUSE_CKSEL1 (unsigned char)~_BV(1) -#define FUSE_CKSEL2 (unsigned char)~_BV(2) -#define FUSE_CKSEL3 (unsigned char)~_BV(3) -#define FUSE_SUT0 (unsigned char)~_BV(4) -#define FUSE_SUT1 (unsigned char)~_BV(5) -#define FUSE_CKOUT (unsigned char)~_BV(6) -#define FUSE_CKDIV8 (unsigned char)~_BV(7) -#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_SUT1 & FUSE_CKDIV8) - -/* High Fuse Byte */ -#define FUSE_BOOTRST (unsigned char)~_BV(0) -#define FUSE_BOOTSZ0 (unsigned char)~_BV(1) -#define FUSE_BOOTSZ1 (unsigned char)~_BV(2) -#define FUSE_EESAVE (unsigned char)~_BV(3) -#define FUSE_WDTON (unsigned char)~_BV(4) -#define FUSE_SPIEN (unsigned char)~_BV(5) -#define FUSE_RSTDSBL (unsigned char)~_BV(6) -#define FUSE_DWEN (unsigned char)~_BV(7) -#define HFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_SPIEN) - -/* Extended Fuse Byte */ -#define FUSE_BODLEVEL0 (unsigned char)~_BV(0) -#define FUSE_BODLEVEL1 (unsigned char)~_BV(1) -#define FUSE_BODLEVEL2 (unsigned char)~_BV(2) -#define FUSE_HWBE (unsigned char)~_BV(3) -#define EFUSE_DEFAULT (FUSE_BODLEVEL0 & FUSE_BODLEVEL1 & FUSE_HWBE) - - -/* Lock Bits */ -#define __LOCK_BITS_EXIST -#define __BOOT_LOCK_BITS_0_EXIST -#define __BOOT_LOCK_BITS_1_EXIST - - -/* Signature */ -#define SIGNATURE_0 0x1E -#define SIGNATURE_1 0x94 -#define SIGNATURE_2 0x82 - -#define SLEEP_MODE_IDLE (0x00<<1) -#define SLEEP_MODE_PWR_DOWN (0x02<<1) -#define SLEEP_MODE_PWR_SAVE (0x03<<1) -#define SLEEP_MODE_STANDBY (0x06<<1) -#define SLEEP_MODE_EXT_STANDBY (0x07<<1) - -#endif /* _AVR_AT90USB162_H_ */ diff --git a/arduino/hardware/tools/avr/avr/include/avr/iousb646.h b/arduino/hardware/tools/avr/avr/include/avr/iousb646.h deleted file mode 100644 index ce9fcb5..0000000 --- a/arduino/hardware/tools/avr/avr/include/avr/iousb646.h +++ /dev/null @@ -1,102 +0,0 @@ -/* Copyright (c) 2006 Anatoly Sokolov - Copyright (c) 2010 Atmel Corporation - All rights reserved. - - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - * Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - * Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in - the documentation and/or other materials provided with the - distribution. - - * Neither the name of the copyright holders nor the names of - contributors may be used to endorse or promote products derived - from this software without specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. */ - -/* $Id: iousb646.h 2102 2010-03-16 22:52:39Z joerg_wunsch $ */ - -/* avr/iousb646.h - definitions for AT90USB646 */ - -#ifndef _AVR_AT90USB646_H_ -#define _AVR_AT90USB646_H_ 1 - -#include - -/* Constants */ -#define SPM_PAGESIZE 256 -#define RAMSTART 0x100 -#define RAMEND 0x10FF -#define XRAMEND 0xFFFF -#define E2END 0x7FF -#define E2PAGESIZE 8 -#define FLASHEND 0xFFFF - - -/* Fuses */ -#define FUSE_MEMORY_SIZE 3 - -/* Low Fuse Byte */ -#define FUSE_CKSEL0 (unsigned char)~_BV(0) -#define FUSE_CKSEL1 (unsigned char)~_BV(1) -#define FUSE_CKSEL2 (unsigned char)~_BV(2) -#define FUSE_CKSEL3 (unsigned char)~_BV(3) -#define FUSE_SUT0 (unsigned char)~_BV(4) -#define FUSE_SUT1 (unsigned char)~_BV(5) -#define FUSE_CKOUT (unsigned char)~_BV(6) -#define FUSE_CKDIV8 (unsigned char)~_BV(7) -#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8) - -/* High Fuse Byte */ -#define FUSE_BOOTRST (unsigned char)~_BV(0) -#define FUSE_BOOTSZ0 (unsigned char)~_BV(1) -#define FUSE_BOOTSZ1 (unsigned char)~_BV(2) -#define FUSE_EESAVE (unsigned char)~_BV(3) -#define FUSE_WDTON (unsigned char)~_BV(4) -#define FUSE_SPIEN (unsigned char)~_BV(5) -#define FUSE_JTAGEN (unsigned char)~_BV(6) -#define FUSE_OCDEN (unsigned char)~_BV(7) -#define HFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_SPIEN & FUSE_JTAGEN) - -/* Extended Fuse Byte */ -#define FUSE_BODLEVEL0 (unsigned char)~_BV(0) -#define FUSE_BODLEVEL1 (unsigned char)~_BV(1) -#define FUSE_BODLEVEL2 (unsigned char)~_BV(2) -#define FUSE_HWBE (unsigned char)~_BV(3) -#define EFUSE_DEFAULT (FUSE_BODLEVEL2 & FUSE_HWBE) - - -/* Lock Bits */ -#define __LOCK_BITS_EXIST -#define __BOOT_LOCK_BITS_0_EXIST -#define __BOOT_LOCK_BITS_1_EXIST - - -/* Signature */ -#define SIGNATURE_0 0x1E -#define SIGNATURE_1 0x96 -#define SIGNATURE_2 0x82 - -#define SLEEP_MODE_IDLE (0x00<<1) -#define SLEEP_MODE_ADC (0x01<<1) -#define SLEEP_MODE_PWR_DOWN (0x02<<1) -#define SLEEP_MODE_PWR_SAVE (0x03<<1) -#define SLEEP_MODE_STANDBY (0x06<<1) -#define SLEEP_MODE_EXT_STANDBY (0x07<<1) - -#endif /* _AVR_AT90USB646_H_ */ diff --git a/arduino/hardware/tools/avr/avr/include/avr/iousb647.h b/arduino/hardware/tools/avr/avr/include/avr/iousb647.h deleted file mode 100644 index 638fd35..0000000 --- a/arduino/hardware/tools/avr/avr/include/avr/iousb647.h +++ /dev/null @@ -1,102 +0,0 @@ -/* Copyright (c) 2006 Anatoly Sokolov - Copyright (c) 2010 Atmel Corporation - All rights reserved. - - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - * Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - * Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in - the documentation and/or other materials provided with the - distribution. - - * Neither the name of the copyright holders nor the names of - contributors may be used to endorse or promote products derived - from this software without specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. */ - -/* $Id: iousb647.h 2102 2010-03-16 22:52:39Z joerg_wunsch $ */ - -/* avr/iousb647.h - definitions for AT90USB647 */ - -#ifndef _AVR_AT90USB647_H_ -#define _AVR_AT90USB647_H_ 1 - -#include - -/* Constants */ -#define SPM_PAGESIZE 256 -#define RAMSTART 0x100 -#define RAMEND 0x10FF -#define XRAMEND 0xFFFF -#define E2END 0x7FF -#define E2PAGESIZE 8 -#define FLASHEND 0xFFFF - - -/* Fuses */ -#define FUSE_MEMORY_SIZE 3 - -/* Low Fuse Byte */ -#define FUSE_CKSEL0 (unsigned char)~_BV(0) -#define FUSE_CKSEL1 (unsigned char)~_BV(1) -#define FUSE_CKSEL2 (unsigned char)~_BV(2) -#define FUSE_CKSEL3 (unsigned char)~_BV(3) -#define FUSE_SUT0 (unsigned char)~_BV(4) -#define FUSE_SUT1 (unsigned char)~_BV(5) -#define FUSE_CKOUT (unsigned char)~_BV(6) -#define FUSE_CKDIV8 (unsigned char)~_BV(7) -#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8) - -/* High Fuse Byte */ -#define FUSE_BOOTRST (unsigned char)~_BV(0) -#define FUSE_BOOTSZ0 (unsigned char)~_BV(1) -#define FUSE_BOOTSZ1 (unsigned char)~_BV(2) -#define FUSE_EESAVE (unsigned char)~_BV(3) -#define FUSE_WDTON (unsigned char)~_BV(4) -#define FUSE_SPIEN (unsigned char)~_BV(5) -#define FUSE_JTAGEN (unsigned char)~_BV(6) -#define FUSE_OCDEN (unsigned char)~_BV(7) -#define HFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_SPIEN & FUSE_JTAGEN) - -/* Extended Fuse Byte */ -#define FUSE_BODLEVEL0 (unsigned char)~_BV(0) -#define FUSE_BODLEVEL1 (unsigned char)~_BV(1) -#define FUSE_BODLEVEL2 (unsigned char)~_BV(2) -#define FUSE_HWBE (unsigned char)~_BV(3) -#define EFUSE_DEFAULT (FUSE_BODLEVEL2 & FUSE_HWBE) - - -/* Lock Bits */ -#define __LOCK_BITS_EXIST -#define __BOOT_LOCK_BITS_0_EXIST -#define __BOOT_LOCK_BITS_1_EXIST - - -/* Signature */ -#define SIGNATURE_0 0x1E -#define SIGNATURE_1 0x96 -#define SIGNATURE_2 0x82 - -#define SLEEP_MODE_IDLE (0x00<<1) -#define SLEEP_MODE_ADC (0x01<<1) -#define SLEEP_MODE_PWR_DOWN (0x02<<1) -#define SLEEP_MODE_PWR_SAVE (0x03<<1) -#define SLEEP_MODE_STANDBY (0x06<<1) -#define SLEEP_MODE_EXT_STANDBY (0x07<<1) - -#endif /* _AVR_AT90USB647_H_ */ diff --git a/arduino/hardware/tools/avr/avr/include/avr/iousb82.h b/arduino/hardware/tools/avr/avr/include/avr/iousb82.h deleted file mode 100644 index 8f8e8ec..0000000 --- a/arduino/hardware/tools/avr/avr/include/avr/iousb82.h +++ /dev/null @@ -1,95 +0,0 @@ -/* Copyright (c) 2007 Anatoly Sokolov - Copyright (c) 2010 Atmel Corporation - All rights reserved. - - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - * Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - * Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in - the documentation and/or other materials provided with the - distribution. - - * Neither the name of the copyright holders nor the names of - contributors may be used to endorse or promote products derived - from this software without specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. */ - -/* $Id: iousb82.h 2102 2010-03-16 22:52:39Z joerg_wunsch $ */ - -/* avr/iousb82.h - definitions for AT90USB82 */ - -#ifndef _AVR_AT90USB82_H_ -#define _AVR_AT90USB82_H_ 1 - -#include - -/* Constants */ -#define SPM_PAGESIZE 128 -#define RAMSTART 0x100 -#define RAMEND 0x2FF -#define XRAMEND RAMEND -#define E2END 0x1FF -#define E2PAGESIZE 4 -#define FLASHEND 0x1FFF - - -/* Fuses */ -#define FUSE_MEMORY_SIZE 3 - -/* Low Fuse Byte */ -#define FUSE_CKSEL0 (unsigned char)~_BV(0) -#define FUSE_CKSEL1 (unsigned char)~_BV(1) -#define FUSE_CKSEL2 (unsigned char)~_BV(2) -#define FUSE_CKSEL3 (unsigned char)~_BV(3) -#define FUSE_SUT0 (unsigned char)~_BV(4) -#define FUSE_SUT1 (unsigned char)~_BV(5) -#define FUSE_CKOUT (unsigned char)~_BV(6) -#define FUSE_CKDIV8 (unsigned char)~_BV(7) -#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_SUT1 & FUSE_CKDIV8) - -/* High Fuse Byte */ -#define FUSE_BOOTRST (unsigned char)~_BV(0) -#define FUSE_BOOTSZ0 (unsigned char)~_BV(1) -#define FUSE_BOOTSZ1 (unsigned char)~_BV(2) -#define FUSE_EESAVE (unsigned char)~_BV(3) -#define FUSE_WDTON (unsigned char)~_BV(4) -#define FUSE_SPIEN (unsigned char)~_BV(5) -#define FUSE_RSTDSBL (unsigned char)~_BV(6) -#define FUSE_DWEN (unsigned char)~_BV(7) -#define HFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_SPIEN) - -/* Extended Fuse Byte */ -#define FUSE_BODLEVEL0 (unsigned char)~_BV(0) -#define FUSE_BODLEVEL1 (unsigned char)~_BV(1) -#define FUSE_BODLEVEL2 (unsigned char)~_BV(2) -#define FUSE_HWBE (unsigned char)~_BV(3) -#define EFUSE_DEFAULT (FUSE_BODLEVEL0 & FUSE_BODLEVEL1 & FUSE_HWBE) - - -/* Lock Bits */ -#define __LOCK_BITS_EXIST -#define __BOOT_LOCK_BITS_0_EXIST -#define __BOOT_LOCK_BITS_1_EXIST - -#define SLEEP_MODE_IDLE (0x00<<1) -#define SLEEP_MODE_PWR_DOWN (0x02<<1) -#define SLEEP_MODE_PWR_SAVE (0x03<<1) -#define SLEEP_MODE_STANDBY (0x06<<1) -#define SLEEP_MODE_EXT_STANDBY (0x07<<1) - -#endif /* _AVR_AT90USB82_H_ */ diff --git a/arduino/hardware/tools/avr/avr/include/avr/iousbxx2.h b/arduino/hardware/tools/avr/avr/include/avr/iousbxx2.h deleted file mode 100644 index 2f0e391..0000000 --- a/arduino/hardware/tools/avr/avr/include/avr/iousbxx2.h +++ /dev/null @@ -1,807 +0,0 @@ -/* Copyright (c) 2007 Anatoly Sokolov - All rights reserved. - - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - * Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - * Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in - the documentation and/or other materials provided with the - distribution. - - * Neither the name of the copyright holders nor the names of - contributors may be used to endorse or promote products derived - from this software without specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. */ - -/* $Id: iousbxx2.h 2246 2011-05-14 20:02:02Z joerg_wunsch $ */ - -/* iousbxx2.h - definitions for AT90USB82 and AT90USB162. */ - -#ifndef _AVR_IOUSBXX2_H_ -#define _AVR_IOUSBXX2_H_ 1 - -/* This file should only be included from , never directly. */ - -#ifndef _AVR_IO_H_ -# error "Include instead of this file." -#endif - -#ifndef _AVR_IOXXX_H_ -# define _AVR_IOXXX_H_ "iousbxx2.h" -#else -# error "Attempt to include more than one file." -#endif - -/* Registers and associated bit numbers */ - -/* Reserved [0x00..0x02] */ - -#define PINB _SFR_IO8(0X03) -#define PINB7 7 -#define PINB6 6 -#define PINB5 5 -#define PINB4 4 -#define PINB3 3 -#define PINB2 2 -#define PINB1 1 -#define PINB0 0 - -#define DDRB _SFR_IO8(0x04) -#define DDB7 7 -#define DDB6 6 -#define DDB5 5 -#define DDB4 4 -#define DDB3 3 -#define DDB2 2 -#define DDB1 1 -#define DDB0 0 - -#define PORTB _SFR_IO8(0x05) -#define PB7 7 -#define PB6 6 -#define PB5 5 -#define PB4 4 -#define PB3 3 -#define PB2 2 -#define PB1 1 -#define PB0 0 - -#define PINC _SFR_IO8(0x06) -#define PINC7 7 -#define PINC6 6 -#define PINC5 5 -#define PINC4 4 -#define PINC2 2 -#define PINC1 1 -#define PINC0 0 - -#define DDRC _SFR_IO8(0x07) -#define DDC7 7 -#define DDC6 6 -#define DDC5 5 -#define DDC4 4 -#define DDC2 2 -#define DDC1 1 -#define DDC0 0 - -#define PORTC _SFR_IO8(0x08) -#define PC7 7 -#define PC6 6 -#define PC5 5 -#define PC4 4 -#define PC2 2 -#define PC1 1 -#define PC0 0 - -#define PIND _SFR_IO8(0x09) -#define PIND7 7 -#define PIND6 6 -#define PIND5 5 -#define PIND4 4 -#define PIND3 3 -#define PIND2 2 -#define PIND1 1 -#define PIND0 0 - -#define DDRD _SFR_IO8(0x0A) -#define DDD7 7 -#define DDD6 6 -#define DDD5 5 -#define DDD4 4 -#define DDD3 3 -#define DDD2 2 -#define DDD1 1 -#define DDD0 0 - -#define PORTD _SFR_IO8(0x0B) -#define PD7 7 -#define PD6 6 -#define PD5 5 -#define PD4 4 -#define PD3 3 -#define PD2 2 -#define PD1 1 -#define PD0 0 - -/* Reserved [0xC..0x14] */ - -#define TIFR0 _SFR_IO8(0x15) -#define OCF0B 2 -#define OCF0A 1 -#define TOV0 0 - -#define TIFR1 _SFR_IO8(0x16) -#define ICF1 5 -#define OCF1C 3 -#define OCF1B 2 -#define OCF1A 1 -#define TOV1 0 - -/* Reserved [0x17..0x1A] */ - -#define PCIFR _SFR_IO8(0x1B) -#define PCIF1 1 -#define PCIF0 0 - -#define EIFR _SFR_IO8(0x1C) -#define INTF7 7 -#define INTF6 6 -#define INTF5 5 -#define INTF4 4 -#define INTF3 3 -#define INTF2 2 -#define INTF1 1 -#define INTF0 0 - -#define EIMSK _SFR_IO8(0x1D) -#define INT7 7 -#define INT6 6 -#define INT5 5 -#define INT4 4 -#define INT3 3 -#define INT2 2 -#define INT1 1 -#define INT0 0 - -#define GPIOR0 _SFR_IO8(0x1E) - -#define EECR _SFR_IO8(0x1F) -#define EEPM1 5 -#define EEPM0 4 -#define EERIE 3 -#define EEMPE 2 -#define EEPE 1 -#define EERE 0 - -#define EEDR _SFR_IO8(0x20) - -#define EEAR _SFR_IO16(0x21) -#define EEARL _SFR_IO8(0x21) -#define EEARH _SFR_IO8(0x22) - -/* 6-char sequence denoting where to find the EEPROM registers in memory space. - Adresses denoted in hex syntax with uppercase letters. Used by the EEPROM - subroutines. - First two letters: EECR address. - Second two letters: EEDR address. - Last two letters: EEAR address. */ -#define __EEPROM_REG_LOCATIONS__ 1F2021 - -#define GTCCR _SFR_IO8(0x23) -#define TSM 7 -#define PSRASY 1 -#define PSRSYNC 0 - -#define TCCR0A _SFR_IO8(0x24) -#define COM0A1 7 -#define COM0A0 6 -#define COM0B1 5 -#define COM0B0 4 -#define WGM01 1 -#define WGM00 0 - -#define TCCR0B _SFR_IO8(0x25) -#define FOC0A 7 -#define FOC0B 6 -#define WGM02 3 -#define CS02 2 -#define CS01 1 -#define CS00 0 - -#define TCNT0 _SFR_IO8(0X26) - -#define OCR0A _SFR_IO8(0x27) - -#define OCR0B _SFR_IO8(0X28) - -#define PLLCSR _SFR_IO8(0x29) -#define PLLP2 4 -#define PLLP1 3 -#define PLLP0 2 -#define PLLE 1 -#define PLOCK 0 - -#define GPIOR1 _SFR_IO8(0x2A) - -#define GPIOR2 _SFR_IO8(0x2B) - -#define SPCR _SFR_IO8(0x2C) -#define SPIE 7 -#define SPE 6 -#define DORD 5 -#define MSTR 4 -#define CPOL 3 -#define CPHA 2 -#define SPR1 1 -#define SPR0 0 - -#define SPSR _SFR_IO8(0x2D) -#define SPIF 7 -#define WCOL 6 -#define SPI2X 0 - -#define SPDR _SFR_IO8(0x2E) - -/* Reserved [0x2F] */ - -#define ACSR _SFR_IO8(0x30) -#define ACD 7 -#define ACBG 6 -#define ACO 5 -#define ACI 4 -#define ACIE 3 -#define ACIC 2 -#define ACIS1 1 -#define ACIS0 0 - -#define DWDR _SFR_IO8(0x31) -#define IDRD 7 - -/* Reserved [0x32] */ - -#define SMCR _SFR_IO8(0x33) -#define SM2 3 -#define SM1 2 -#define SM0 1 -#define SE 0 - -#define MCUSR _SFR_IO8(0x34) -#define USBRF 5 -#define WDRF 3 -#define BORF 2 -#define EXTRF 1 -#define PORF 0 - -#define MCUCR _SFR_IO8(0x35) -#define PUD 4 -#define IVSEL 1 -#define IVCE 0 - -/* Reserved [0x36] */ - -#define SPMCSR _SFR_IO8(0x37) -#define SPMIE 7 -#define RWWSB 6 -#define SIGRD 5 -#define RWWSRE 4 -#define BLBSET 3 -#define PGWRT 2 -#define PGERS 1 -#define SPMEN 0 - -/* Reserved [0x38..0x3C] */ - -/* SP [0x3D..0x3E] */ -/* SREG [0x3F] */ - -#define WDTCSR _SFR_MEM8(0x60) -#define WDIF 7 -#define WDIE 6 -#define WDP3 5 -#define WDCE 4 -#define WDE 3 -#define WDP2 2 -#define WDP1 1 -#define WDP0 0 - -#define CLKPR _SFR_MEM8(0x61) -#define CLKPCE 7 -#define CLKPS3 3 -#define CLKPS2 2 -#define CLKPS1 1 -#define CLKPS0 0 - -#define WDTCKD _SFR_MEM8(0x62) -#define WDEWIF 3 -#define WDEWIE 2 -#define WCLKD1 1 -#define WCLKD0 0 - -#define REGCR _SFR_MEM8(0x63) -#define REGDIS 0 - -#define PRR0 _SFR_MEM8(0x64) -#define PRTIM0 5 -#define PRTIM1 3 -#define PRSPI 2 - -#define __AVR_HAVE_PRR0 ((1<, never directly. */ - -#ifndef _AVR_IO_H_ -# error "Include instead of this file." -#endif - -#ifndef _AVR_IOXXX_H_ -# define _AVR_IOXXX_H_ "iousbxx6_7.h" -#else -# error "Attempt to include more than one file." -#endif - -#if defined(__AVR_AT90USB646__) || defined(__AVR_AT90USB1286__) -# define __AT90USBxx6__ 1 -#elif defined(__AVR_AT90USB647__) || defined(__AVR_AT90USB1287__) -# define __AT90USBxx7__ 1 -#endif - -/* Registers and associated bit numbers */ - -#define PINA _SFR_IO8(0X00) -#define PINA7 7 -#define PINA6 6 -#define PINA5 5 -#define PINA4 4 -#define PINA3 3 -#define PINA2 2 -#define PINA1 1 -#define PINA0 0 - -#define DDRA _SFR_IO8(0X01) -#define DDA7 7 -#define DDA6 6 -#define DDA5 5 -#define DDA4 4 -#define DDA3 3 -#define DDA2 2 -#define DDA1 1 -#define DDA0 0 - -#define PORTA _SFR_IO8(0X02) -#define PA7 7 -#define PA6 6 -#define PA5 5 -#define PA4 4 -#define PA3 3 -#define PA2 2 -#define PA1 1 -#define PA0 0 - -#define PINB _SFR_IO8(0X03) -#define PINB7 7 -#define PINB6 6 -#define PINB5 5 -#define PINB4 4 -#define PINB3 3 -#define PINB2 2 -#define PINB1 1 -#define PINB0 0 - -#define DDRB _SFR_IO8(0x04) -#define DDB7 7 -#define DDB6 6 -#define DDB5 5 -#define DDB4 4 -#define DDB3 3 -#define DDB2 2 -#define DDB1 1 -#define DDB0 0 - -#define PORTB _SFR_IO8(0x05) -#define PB7 7 -#define PB6 6 -#define PB5 5 -#define PB4 4 -#define PB3 3 -#define PB2 2 -#define PB1 1 -#define PB0 0 - -#define PINC _SFR_IO8(0x06) -#define PINC7 7 -#define PINC6 6 -#define PINC5 5 -#define PINC4 4 -#define PINC3 3 -#define PINC2 2 -#define PINC1 1 -#define PINC0 0 - -#define DDRC _SFR_IO8(0x07) -#define DDC7 7 -#define DDC6 6 -#define DDC5 5 -#define DDC4 4 -#define DDC3 3 -#define DDC2 2 -#define DDC1 1 -#define DDC0 0 - -#define PORTC _SFR_IO8(0x08) -#define PC7 7 -#define PC6 6 -#define PC5 5 -#define PC4 4 -#define PC3 3 -#define PC2 2 -#define PC1 1 -#define PC0 0 - -#define PIND _SFR_IO8(0x09) -#define PIND7 7 -#define PIND6 6 -#define PIND5 5 -#define PIND4 4 -#define PIND3 3 -#define PIND2 2 -#define PIND1 1 -#define PIND0 0 - -#define DDRD _SFR_IO8(0x0A) -#define DDD7 7 -#define DDD6 6 -#define DDD5 5 -#define DDD4 4 -#define DDD3 3 -#define DDD2 2 -#define DDD1 1 -#define DDD0 0 - -#define PORTD _SFR_IO8(0x0B) -#define PD7 7 -#define PD6 6 -#define PD5 5 -#define PD4 4 -#define PD3 3 -#define PD2 2 -#define PD1 1 -#define PD0 0 - -#define PINE _SFR_IO8(0x0C) -#define PINE7 7 -#define PINE6 6 -#define PINE5 5 -#define PINE4 4 -#define PINE3 3 -#define PINE2 2 -#define PINE1 1 -#define PINE0 0 - -#define DDRE _SFR_IO8(0x0D) -#define DDE7 7 -#define DDE6 6 -#define DDE5 5 -#define DDE4 4 -#define DDE3 3 -#define DDE2 2 -#define DDE1 1 -#define DDE0 0 - -#define PORTE _SFR_IO8(0x0E) -#define PE7 7 -#define PE6 6 -#define PE5 5 -#define PE4 4 -#define PE3 3 -#define PE2 2 -#define PE1 1 -#define PE0 0 - -#define PINF _SFR_IO8(0x0F) -#define PINF7 7 -#define PINF6 6 -#define PINF5 5 -#define PINF4 4 -#define PINF3 3 -#define PINF2 2 -#define PINF1 1 -#define PINF0 0 - -#define DDRF _SFR_IO8(0x10) -#define DDF7 7 -#define DDF6 6 -#define DDF5 5 -#define DDF4 4 -#define DDF3 3 -#define DDF2 2 -#define DDF1 1 -#define DDF0 0 - -#define PORTF _SFR_IO8(0x11) -#define PF7 7 -#define PF6 6 -#define PF5 5 -#define PF4 4 -#define PF3 3 -#define PF2 2 -#define PF1 1 -#define PF0 0 - -/* Reserved [0x12..0x14] */ - -#define TIFR0 _SFR_IO8(0x15) -#define OCF0B 2 -#define OCF0A 1 -#define TOV0 0 - -#define TIFR1 _SFR_IO8(0x16) -#define ICF1 5 -#define OCF1C 3 -#define OCF1B 2 -#define OCF1A 1 -#define TOV1 0 - -#define TIFR2 _SFR_IO8(0x17) -#define OCF2B 2 -#define OCF2A 1 -#define TOV2 0 - -#define TIFR3 _SFR_IO8(0x18) -#define ICF3 5 -#define OCF3C 3 -#define OCF3B 2 -#define OCF3A 1 -#define TOV3 0 - -/* Reserved [0x19..0x1A] */ - -#define PCIFR _SFR_IO8(0x1B) -#define PCIF0 0 - -#define EIFR _SFR_IO8(0x1C) -#define INTF7 7 -#define INTF6 6 -#define INTF5 5 -#define INTF4 4 -#define INTF3 3 -#define INTF2 2 -#define INTF1 1 -#define INTF0 0 - -#define EIMSK _SFR_IO8(0x1D) -#define INT7 7 -#define INT6 6 -#define INT5 5 -#define INT4 4 -#define INT3 3 -#define INT2 2 -#define INT1 1 -#define INT0 0 - -#define GPIOR0 _SFR_IO8(0x1E) - -#define EECR _SFR_IO8(0x1F) -#define EEPM1 5 -#define EEPM0 4 -#define EERIE 3 -#define EEMPE 2 -#define EEPE 1 -#define EERE 0 - -#define EEDR _SFR_IO8(0x20) - -#define EEAR _SFR_IO16(0x21) -#define EEARL _SFR_IO8(0x21) -#define EEARH _SFR_IO8(0x22) - -/* 6-char sequence denoting where to find the EEPROM registers in memory space. - Adresses denoted in hex syntax with uppercase letters. Used by the EEPROM - subroutines. - First two letters: EECR address. - Second two letters: EEDR address. - Last two letters: EEAR address. */ -#define __EEPROM_REG_LOCATIONS__ 1F2021 - -#define GTCCR _SFR_IO8(0x23) -#define TSM 7 -#define PSRASY 1 -#define PSRSYNC 0 - -#define TCCR0A _SFR_IO8(0x24) -#define COM0A1 7 -#define COM0A0 6 -#define COM0B1 5 -#define COM0B0 4 -#define WGM01 1 -#define WGM00 0 - -#define TCCR0B _SFR_IO8(0x25) -#define FOC0A 7 -#define FOC0B 6 -#define WGM02 3 -#define CS02 2 -#define CS01 1 -#define CS00 0 - -#define TCNT0 _SFR_IO8(0X26) - -#define OCR0A _SFR_IO8(0x27) - -#define OCR0B _SFR_IO8(0X28) - -#define PLLCSR _SFR_IO8(0x29) -#define PLLP2 4 -#define PLLP1 3 -#define PLLP0 2 -#define PLLE 1 -#define PLOCK 0 - -#define GPIOR1 _SFR_IO8(0x2A) - -#define GPIOR2 _SFR_IO8(0x2B) - -#define SPCR _SFR_IO8(0x2C) -#define SPIE 7 -#define SPE 6 -#define DORD 5 -#define MSTR 4 -#define CPOL 3 -#define CPHA 2 -#define SPR1 1 -#define SPR0 0 - -#define SPSR _SFR_IO8(0x2D) -#define SPIF 7 -#define WCOL 6 -#define SPI2X 0 - -#define SPDR _SFR_IO8(0x2E) - -/* Reserved [0x2F] */ - -#define ACSR _SFR_IO8(0x30) -#define ACD 7 -#define ACBG 6 -#define ACO 5 -#define ACI 4 -#define ACIE 3 -#define ACIC 2 -#define ACIS1 1 -#define ACIS0 0 - -#define MONDR _SFR_IO8(0x31) -#define OCDR _SFR_IO8(0x31) -#define IDRD 7 -#define OCDR7 7 -#define OCDR6 6 -#define OCDR5 5 -#define OCDR4 4 -#define OCDR3 3 -#define OCDR2 2 -#define OCDR1 1 -#define OCDR0 0 - -/* Reserved [0x32] */ - -#define SMCR _SFR_IO8(0x33) -#define SM2 3 -#define SM1 2 -#define SM0 1 -#define SE 0 - -#define MCUSR _SFR_IO8(0x34) -#define JTRF 4 -#define WDRF 3 -#define BORF 2 -#define EXTRF 1 -#define PORF 0 - -#define MCUCR _SFR_IO8(0x35) -#define JTD 7 -#define PUD 4 -#define IVSEL 1 -#define IVCE 0 - -/* Reserved [0x36] */ - -#define SPMCSR _SFR_IO8(0x37) -#define SPMIE 7 -#define RWWSB 6 -#define SIGRD 5 -#define RWWSRE 4 -#define BLBSET 3 -#define PGWRT 2 -#define PGERS 1 -#define SPMEN 0 - -/* Reserved [0x38..0x3A] */ - -#if defined(__AVR_AT90USB1286__) || defined(__AVR_AT90USB1287__) -#define RAMPZ _SFR_IO8(0x3B) -#endif - -/* Reserved [0x3C] */ - -/* SP [0x3D..0x3E] */ -/* SREG [0x3F] */ - -#define WDTCSR _SFR_MEM8(0x60) -#define WDIF 7 -#define WDIE 6 -#define WDP3 5 -#define WDCE 4 -#define WDE 3 -#define WDP2 2 -#define WDP1 1 -#define WDP0 0 - -#define CLKPR _SFR_MEM8(0x61) -#define CLKPCE 7 -#define CLKPS3 3 -#define CLKPS2 2 -#define CLKPS1 1 -#define CLKPS0 0 - -/* Reserved [0x62..0x63] */ - -#define PRR0 _SFR_MEM8(0x64) -#define PRTWI 7 -#define PRTIM2 6 -#define PRTIM0 5 -#define PRTIM1 3 -#define PRSPI 2 -#define PRADC 0 - -#define __AVR_HAVE_PRR0 ((1<, never directly. */ - -#ifndef _AVR_IO_H_ -# error "Include instead of this file." -#endif - -#ifndef _AVR_IOXXX_H_ -# define _AVR_IOXXX_H_ "iox128a1.h" -#else -# error "Attempt to include more than one file." -#endif - - -#ifndef _AVR_ATxmega128A1_H_ -#define _AVR_ATxmega128A1_H_ 1 - - -/* Ungrouped common registers */ -#define GPIOR0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ -#define GPIOR1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ -#define GPIOR2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ -#define GPIOR3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ -#define GPIOR4 _SFR_MEM8(0x0004) /* General Purpose IO Register 4 */ -#define GPIOR5 _SFR_MEM8(0x0005) /* General Purpose IO Register 5 */ -#define GPIOR6 _SFR_MEM8(0x0006) /* General Purpose IO Register 6 */ -#define GPIOR7 _SFR_MEM8(0x0007) /* General Purpose IO Register 7 */ -#define GPIOR8 _SFR_MEM8(0x0008) /* General Purpose IO Register 8 */ -#define GPIOR9 _SFR_MEM8(0x0009) /* General Purpose IO Register 9 */ -#define GPIORA _SFR_MEM8(0x000A) /* General Purpose IO Register 10 */ -#define GPIORB _SFR_MEM8(0x000B) /* General Purpose IO Register 11 */ -#define GPIORC _SFR_MEM8(0x000C) /* General Purpose IO Register 12 */ -#define GPIORD _SFR_MEM8(0x000D) /* General Purpose IO Register 13 */ -#define GPIORE _SFR_MEM8(0x000E) /* General Purpose IO Register 14 */ -#define GPIORF _SFR_MEM8(0x000F) /* General Purpose IO Register 15 */ - -/* Deprecated */ -#define GPIO0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ -#define GPIO1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ -#define GPIO2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ -#define GPIO3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ -#define GPIO4 _SFR_MEM8(0x0004) /* General Purpose IO Register 4 */ -#define GPIO5 _SFR_MEM8(0x0005) /* General Purpose IO Register 5 */ -#define GPIO6 _SFR_MEM8(0x0006) /* General Purpose IO Register 6 */ -#define GPIO7 _SFR_MEM8(0x0007) /* General Purpose IO Register 7 */ -#define GPIO8 _SFR_MEM8(0x0008) /* General Purpose IO Register 8 */ -#define GPIO9 _SFR_MEM8(0x0009) /* General Purpose IO Register 9 */ -#define GPIOA _SFR_MEM8(0x000A) /* General Purpose IO Register 10 */ -#define GPIOB _SFR_MEM8(0x000B) /* General Purpose IO Register 11 */ -#define GPIOC _SFR_MEM8(0x000C) /* General Purpose IO Register 12 */ -#define GPIOD _SFR_MEM8(0x000D) /* General Purpose IO Register 13 */ -#define GPIOE _SFR_MEM8(0x000E) /* General Purpose IO Register 14 */ -#define GPIOF _SFR_MEM8(0x000F) /* General Purpose IO Register 15 */ - -#define CCP _SFR_MEM8(0x0034) /* Configuration Change Protection */ -#define RAMPD _SFR_MEM8(0x0038) /* Ramp D */ -#define RAMPX _SFR_MEM8(0x0039) /* Ramp X */ -#define RAMPY _SFR_MEM8(0x003A) /* Ramp Y */ -#define RAMPZ _SFR_MEM8(0x003B) /* Ramp Z */ -#define EIND _SFR_MEM8(0x003C) /* Extended Indirect Jump */ -#define SPL _SFR_MEM8(0x003D) /* Stack Pointer Low */ -#define SPH _SFR_MEM8(0x003E) /* Stack Pointer High */ -#define SREG _SFR_MEM8(0x003F) /* Status Register */ - - -/* C Language Only */ -#if !defined (__ASSEMBLER__) - -#include - -typedef volatile uint8_t register8_t; -typedef volatile uint16_t register16_t; -typedef volatile uint32_t register32_t; - - -#ifdef _WORDREGISTER -#undef _WORDREGISTER -#endif -#define _WORDREGISTER(regname) \ - __extension__ union \ - { \ - register16_t regname; \ - struct \ - { \ - register8_t regname ## L; \ - register8_t regname ## H; \ - }; \ - } - -#ifdef _DWORDREGISTER -#undef _DWORDREGISTER -#endif -#define _DWORDREGISTER(regname) \ - __extension__ union \ - { \ - register32_t regname; \ - struct \ - { \ - register8_t regname ## 0; \ - register8_t regname ## 1; \ - register8_t regname ## 2; \ - register8_t regname ## 3; \ - }; \ - } - - -/* -========================================================================== -IO Module Structures -========================================================================== -*/ - - -/* --------------------------------------------------------------------------- -XOCD - On-Chip Debug System --------------------------------------------------------------------------- -*/ - -/* On-Chip Debug System */ -typedef struct OCD_struct -{ - register8_t OCDR0; /* OCD Register 0 */ - register8_t OCDR1; /* OCD Register 1 */ -} OCD_t; - - -/* CCP signatures */ -typedef enum CCP_enum -{ - CCP_SPM_gc = (0x9D<<0), /* SPM Instruction Protection */ - CCP_IOREG_gc = (0xD8<<0), /* IO Register Protection */ -} CCP_t; - - -/* --------------------------------------------------------------------------- -CLK - Clock System --------------------------------------------------------------------------- -*/ - -/* Clock System */ -typedef struct CLK_struct -{ - register8_t CTRL; /* Control Register */ - register8_t PSCTRL; /* Prescaler Control Register */ - register8_t LOCK; /* Lock register */ - register8_t RTCCTRL; /* RTC Control Register */ -} CLK_t; - -/* --------------------------------------------------------------------------- -CLK - Clock System --------------------------------------------------------------------------- -*/ - -/* Power Reduction */ -typedef struct PR_struct -{ - register8_t PRGEN; /* General Power Reduction */ - register8_t PRPA; /* Power Reduction Port A */ - register8_t PRPB; /* Power Reduction Port B */ - register8_t PRPC; /* Power Reduction Port C */ - register8_t PRPD; /* Power Reduction Port D */ - register8_t PRPE; /* Power Reduction Port E */ - register8_t PRPF; /* Power Reduction Port F */ -} PR_t; - -/* System Clock Selection */ -typedef enum CLK_SCLKSEL_enum -{ - CLK_SCLKSEL_RC2M_gc = (0x00<<0), /* Internal 2MHz RC Oscillator */ - CLK_SCLKSEL_RC32M_gc = (0x01<<0), /* Internal 32MHz RC Oscillator */ - CLK_SCLKSEL_RC32K_gc = (0x02<<0), /* Internal 32kHz RC Oscillator */ - CLK_SCLKSEL_XOSC_gc = (0x03<<0), /* External Crystal Oscillator or Clock */ - CLK_SCLKSEL_PLL_gc = (0x04<<0), /* Phase Locked Loop */ -} CLK_SCLKSEL_t; - -/* Prescaler A Division Factor */ -typedef enum CLK_PSADIV_enum -{ - CLK_PSADIV_1_gc = (0x00<<2), /* Divide by 1 */ - CLK_PSADIV_2_gc = (0x01<<2), /* Divide by 2 */ - CLK_PSADIV_4_gc = (0x03<<2), /* Divide by 4 */ - CLK_PSADIV_8_gc = (0x05<<2), /* Divide by 8 */ - CLK_PSADIV_16_gc = (0x07<<2), /* Divide by 16 */ - CLK_PSADIV_32_gc = (0x09<<2), /* Divide by 32 */ - CLK_PSADIV_64_gc = (0x0B<<2), /* Divide by 64 */ - CLK_PSADIV_128_gc = (0x0D<<2), /* Divide by 128 */ - CLK_PSADIV_256_gc = (0x0F<<2), /* Divide by 256 */ - CLK_PSADIV_512_gc = (0x11<<2), /* Divide by 512 */ -} CLK_PSADIV_t; - -/* Prescaler B and C Division Factor */ -typedef enum CLK_PSBCDIV_enum -{ - CLK_PSBCDIV_1_1_gc = (0x00<<0), /* Divide B by 1 and C by 1 */ - CLK_PSBCDIV_1_2_gc = (0x01<<0), /* Divide B by 1 and C by 2 */ - CLK_PSBCDIV_4_1_gc = (0x02<<0), /* Divide B by 4 and C by 1 */ - CLK_PSBCDIV_2_2_gc = (0x03<<0), /* Divide B by 2 and C by 2 */ -} CLK_PSBCDIV_t; - -/* RTC Clock Source */ -typedef enum CLK_RTCSRC_enum -{ - CLK_RTCSRC_ULP_gc = (0x00<<1), /* 1kHz from internal 32kHz ULP */ - CLK_RTCSRC_TOSC_gc = (0x01<<1), /* 1kHz from 32kHz crystal oscillator on TOSC */ - CLK_RTCSRC_RCOSC_gc = (0x02<<1), /* 1kHz from internal 32kHz RC oscillator */ - CLK_RTCSRC_TOSC32_gc = (0x05<<1), /* 32kHz from 32kHz crystal oscillator on TOSC */ -} CLK_RTCSRC_t; - - -/* --------------------------------------------------------------------------- -SLEEP - Sleep Controller --------------------------------------------------------------------------- -*/ - -/* Sleep Controller */ -typedef struct SLEEP_struct -{ - register8_t CTRL; /* Control Register */ -} SLEEP_t; - -/* Sleep Mode */ -typedef enum SLEEP_SMODE_enum -{ - SLEEP_SMODE_IDLE_gc = (0x00<<1), /* Idle mode */ - SLEEP_SMODE_PDOWN_gc = (0x02<<1), /* Power-down Mode */ - SLEEP_SMODE_PSAVE_gc = (0x03<<1), /* Power-save Mode */ - SLEEP_SMODE_STDBY_gc = (0x06<<1), /* Standby Mode */ - SLEEP_SMODE_ESTDBY_gc = (0x07<<1), /* Extended Standby Mode */ -} SLEEP_SMODE_t; - - -#define SLEEP_MODE_IDLE (0x00<<1) -#define SLEEP_MODE_PWR_DOWN (0x02<<1) -#define SLEEP_MODE_PWR_SAVE (0x03<<1) -#define SLEEP_MODE_STANDBY (0x06<<1) -#define SLEEP_MODE_EXT_STANDBY (0x07<<1) - - -/* --------------------------------------------------------------------------- -OSC - Oscillator --------------------------------------------------------------------------- -*/ - -/* Oscillator */ -typedef struct OSC_struct -{ - register8_t CTRL; /* Control Register */ - register8_t STATUS; /* Status Register */ - register8_t XOSCCTRL; /* External Oscillator Control Register */ - register8_t XOSCFAIL; /* External Oscillator Failure Detection Register */ - register8_t RC32KCAL; /* 32kHz Internal Oscillator Calibration Register */ - register8_t PLLCTRL; /* PLL Control REgister */ - register8_t DFLLCTRL; /* DFLL Control Register */ -} OSC_t; - -/* Oscillator Frequency Range */ -typedef enum OSC_FRQRANGE_enum -{ - OSC_FRQRANGE_04TO2_gc = (0x00<<6), /* 0.4 - 2 MHz */ - OSC_FRQRANGE_2TO9_gc = (0x01<<6), /* 2 - 9 MHz */ - OSC_FRQRANGE_9TO12_gc = (0x02<<6), /* 9 - 12 MHz */ - OSC_FRQRANGE_12TO16_gc = (0x03<<6), /* 12 - 16 MHz */ -} OSC_FRQRANGE_t; - -/* External Oscillator Selection and Startup Time */ -typedef enum OSC_XOSCSEL_enum -{ - OSC_XOSCSEL_EXTCLK_gc = (0x00<<0), /* External Clock - 6 CLK */ - OSC_XOSCSEL_32KHz_gc = (0x02<<0), /* 32kHz TOSC - 32K CLK */ - OSC_XOSCSEL_XTAL_256CLK_gc = (0x03<<0), /* 0.4-16MHz XTAL - 256 CLK */ - OSC_XOSCSEL_XTAL_1KCLK_gc = (0x07<<0), /* 0.4-16MHz XTAL - 1K CLK */ - OSC_XOSCSEL_XTAL_16KCLK_gc = (0x0B<<0), /* 0.4-16MHz XTAL - 16K CLK */ -} OSC_XOSCSEL_t; - -/* PLL Clock Source */ -typedef enum OSC_PLLSRC_enum -{ - OSC_PLLSRC_RC2M_gc = (0x00<<6), /* Internal 2MHz RC Oscillator */ - OSC_PLLSRC_RC32M_gc = (0x02<<6), /* Internal 32MHz RC Oscillator */ - OSC_PLLSRC_XOSC_gc = (0x03<<6), /* External Oscillator */ -} OSC_PLLSRC_t; - - -/* --------------------------------------------------------------------------- -DFLL - DFLL --------------------------------------------------------------------------- -*/ - -/* DFLL */ -typedef struct DFLL_struct -{ - register8_t CTRL; /* Control Register */ - register8_t reserved_0x01; - register8_t CALA; /* Calibration Register A */ - register8_t CALB; /* Calibration Register B */ - register8_t COMP0; /* Oscillator Compare Register 0 */ - register8_t COMP1; /* Oscillator Compare Register 1 */ - register8_t COMP2; /* Oscillator Compare Register 2 */ - register8_t reserved_0x07; -} DFLL_t; - - -/* --------------------------------------------------------------------------- -RST - Reset --------------------------------------------------------------------------- -*/ - -/* Reset */ -typedef struct RST_struct -{ - register8_t STATUS; /* Status Register */ - register8_t CTRL; /* Control Register */ -} RST_t; - - -/* --------------------------------------------------------------------------- -WDT - Watch-Dog Timer --------------------------------------------------------------------------- -*/ - -/* Watch-Dog Timer */ -typedef struct WDT_struct -{ - register8_t CTRL; /* Control */ - register8_t WINCTRL; /* Windowed Mode Control */ - register8_t STATUS; /* Status */ -} WDT_t; - -/* Period setting */ -typedef enum WDT_PER_enum -{ - WDT_PER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ - WDT_PER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ - WDT_PER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ - WDT_PER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ - WDT_PER_128CLK_gc = (0x04<<2), /* 128 cycles (0.125s @ 3.3V) */ - WDT_PER_256CLK_gc = (0x05<<2), /* 256 cycles (0.25s @ 3.3V) */ - WDT_PER_512CLK_gc = (0x06<<2), /* 512 cycles (0.5s @ 3.3V) */ - WDT_PER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ - WDT_PER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ - WDT_PER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ - WDT_PER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ -} WDT_PER_t; - -/* Closed window period */ -typedef enum WDT_WPER_enum -{ - WDT_WPER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ - WDT_WPER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ - WDT_WPER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ - WDT_WPER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ - WDT_WPER_128CLK_gc = (0x04<<2), /* 128 cycles (0.125s @ 3.3V) */ - WDT_WPER_256CLK_gc = (0x05<<2), /* 256 cycles (0.25s @ 3.3V) */ - WDT_WPER_512CLK_gc = (0x06<<2), /* 512 cycles (0.5s @ 3.3V) */ - WDT_WPER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ - WDT_WPER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ - WDT_WPER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ - WDT_WPER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ -} WDT_WPER_t; - - -/* --------------------------------------------------------------------------- -MCU - MCU Control --------------------------------------------------------------------------- -*/ - -/* MCU Control */ -typedef struct MCU_struct -{ - register8_t DEVID0; /* Device ID byte 0 */ - register8_t DEVID1; /* Device ID byte 1 */ - register8_t DEVID2; /* Device ID byte 2 */ - register8_t REVID; /* Revision ID */ - register8_t JTAGUID; /* JTAG User ID */ - register8_t reserved_0x05; - register8_t MCUCR; /* MCU Control */ - register8_t reserved_0x07; - register8_t EVSYSLOCK; /* Event System Lock */ - register8_t AWEXLOCK; /* AWEX Lock */ - register8_t reserved_0x0A; - register8_t reserved_0x0B; -} MCU_t; - - -/* --------------------------------------------------------------------------- -PMIC - Programmable Multi-level Interrupt Controller --------------------------------------------------------------------------- -*/ - -/* Programmable Multi-level Interrupt Controller */ -typedef struct PMIC_struct -{ - register8_t STATUS; /* Status Register */ - register8_t INTPRI; /* Interrupt Priority */ - register8_t CTRL; /* Control Register */ -} PMIC_t; - - -/* --------------------------------------------------------------------------- -DMA - DMA Controller --------------------------------------------------------------------------- -*/ - -/* DMA Channel */ -typedef struct DMA_CH_struct -{ - register8_t CTRLA; /* Channel Control */ - register8_t CTRLB; /* Channel Control */ - register8_t ADDRCTRL; /* Address Control */ - register8_t TRIGSRC; /* Channel Trigger Source */ - _WORDREGISTER(TRFCNT); /* Channel Block Transfer Count */ - register8_t REPCNT; /* Channel Repeat Count */ - register8_t reserved_0x07; - register8_t SRCADDR0; /* Channel Source Address 0 */ - register8_t SRCADDR1; /* Channel Source Address 1 */ - register8_t SRCADDR2; /* Channel Source Address 2 */ - register8_t reserved_0x0B; - register8_t DESTADDR0; /* Channel Destination Address 0 */ - register8_t DESTADDR1; /* Channel Destination Address 1 */ - register8_t DESTADDR2; /* Channel Destination Address 2 */ - register8_t reserved_0x0F; -} DMA_CH_t; - -/* --------------------------------------------------------------------------- -DMA - DMA Controller --------------------------------------------------------------------------- -*/ - -/* DMA Controller */ -typedef struct DMA_struct -{ - register8_t CTRL; /* Control */ - register8_t reserved_0x01; - register8_t reserved_0x02; - register8_t INTFLAGS; /* Transfer Interrupt Status */ - register8_t STATUS; /* Status */ - register8_t reserved_0x05; - _WORDREGISTER(TEMP); /* Temporary Register For 16/24-bit Access */ - register8_t reserved_0x08; - register8_t reserved_0x09; - register8_t reserved_0x0A; - register8_t reserved_0x0B; - register8_t reserved_0x0C; - register8_t reserved_0x0D; - register8_t reserved_0x0E; - register8_t reserved_0x0F; - DMA_CH_t CH0; /* DMA Channel 0 */ - DMA_CH_t CH1; /* DMA Channel 1 */ - DMA_CH_t CH2; /* DMA Channel 2 */ - DMA_CH_t CH3; /* DMA Channel 3 */ -} DMA_t; - -/* Burst mode */ -typedef enum DMA_CH_BURSTLEN_enum -{ - DMA_CH_BURSTLEN_1BYTE_gc = (0x00<<0), /* 1-byte burst mode */ - DMA_CH_BURSTLEN_2BYTE_gc = (0x01<<0), /* 2-byte burst mode */ - DMA_CH_BURSTLEN_4BYTE_gc = (0x02<<0), /* 4-byte burst mode */ - DMA_CH_BURSTLEN_8BYTE_gc = (0x03<<0), /* 8-byte burst mode */ -} DMA_CH_BURSTLEN_t; - -/* Source address reload mode */ -typedef enum DMA_CH_SRCRELOAD_enum -{ - DMA_CH_SRCRELOAD_NONE_gc = (0x00<<6), /* No reload */ - DMA_CH_SRCRELOAD_BLOCK_gc = (0x01<<6), /* Reload at end of block */ - DMA_CH_SRCRELOAD_BURST_gc = (0x02<<6), /* Reload at end of burst */ - DMA_CH_SRCRELOAD_TRANSACTION_gc = (0x03<<6), /* Reload at end of transaction */ -} DMA_CH_SRCRELOAD_t; - -/* Source addressing mode */ -typedef enum DMA_CH_SRCDIR_enum -{ - DMA_CH_SRCDIR_FIXED_gc = (0x00<<4), /* Fixed */ - DMA_CH_SRCDIR_INC_gc = (0x01<<4), /* Increment */ - DMA_CH_SRCDIR_DEC_gc = (0x02<<4), /* Decrement */ -} DMA_CH_SRCDIR_t; - -/* Destination adress reload mode */ -typedef enum DMA_CH_DESTRELOAD_enum -{ - DMA_CH_DESTRELOAD_NONE_gc = (0x00<<2), /* No reload */ - DMA_CH_DESTRELOAD_BLOCK_gc = (0x01<<2), /* Reload at end of block */ - DMA_CH_DESTRELOAD_BURST_gc = (0x02<<2), /* Reload at end of burst */ - DMA_CH_DESTRELOAD_TRANSACTION_gc = (0x03<<2), /* Reload at end of transaction */ -} DMA_CH_DESTRELOAD_t; - -/* Destination adressing mode */ -typedef enum DMA_CH_DESTDIR_enum -{ - DMA_CH_DESTDIR_FIXED_gc = (0x00<<0), /* Fixed */ - DMA_CH_DESTDIR_INC_gc = (0x01<<0), /* Increment */ - DMA_CH_DESTDIR_DEC_gc = (0x02<<0), /* Decrement */ -} DMA_CH_DESTDIR_t; - -/* Transfer trigger source */ -typedef enum DMA_CH_TRIGSRC_enum -{ - DMA_CH_TRIGSRC_OFF_gc = (0x00<<0), /* Off software triggers only */ - DMA_CH_TRIGSRC_EVSYS_CH0_gc = (0x01<<0), /* Event System Channel 0 */ - DMA_CH_TRIGSRC_EVSYS_CH1_gc = (0x02<<0), /* Event System Channel 1 */ - DMA_CH_TRIGSRC_EVSYS_CH2_gc = (0x03<<0), /* Event System Channel 2 */ - DMA_CH_TRIGSRC_ADCA_CH0_gc = (0x10<<0), /* ADCA Channel 0 */ - DMA_CH_TRIGSRC_ADCA_CH1_gc = (0x11<<0), /* ADCA Channel 1 */ - DMA_CH_TRIGSRC_ADCA_CH2_gc = (0x12<<0), /* ADCA Channel 2 */ - DMA_CH_TRIGSRC_ADCA_CH3_gc = (0x13<<0), /* ADCA Channel 3 */ - DMA_CH_TRIGSRC_ADCA_CH4_gc = (0x14<<0), /* ADCA Channel 0,1,2,3 combined */ - DMA_CH_TRIGSRC_DACA_CH0_gc = (0x15<<0), /* DACA Channel 0 */ - DMA_CH_TRIGSRC_DACA_CH1_gc = (0x16<<0), /* DACA Channel 1 */ - DMA_CH_TRIGSRC_ADCB_CH0_gc = (0x20<<0), /* ADCB Channel 0 */ - DMA_CH_TRIGSRC_ADCB_CH1_gc = (0x21<<0), /* ADCB Channel 1 */ - DMA_CH_TRIGSRC_ADCB_CH2_gc = (0x22<<0), /* ADCB Channel 2 */ - DMA_CH_TRIGSRC_ADCB_CH3_gc = (0x23<<0), /* ADCB Channel 3 */ - DMA_CH_TRIGSRC_ADCB_CH4_gc = (0x24<<0), /* ADCB Channel 0,1,2,3 combined */ - DMA_CH_TRIGSRC_DACB_CH0_gc = (0x25<<0), /* DACB Channel 0 */ - DMA_CH_TRIGSRC_DACB_CH1_gc = (0x26<<0), /* DACB Channel 1 */ - DMA_CH_TRIGSRC_TCC0_OVF_gc = (0x40<<0), /* Timer/Counter C0 Overflow */ - DMA_CH_TRIGSRC_TCC0_ERR_gc = (0x41<<0), /* Timer/Counter C0 Error */ - DMA_CH_TRIGSRC_TCC0_CCA_gc = (0x42<<0), /* Timer/Counter C0 Compare or Capture A */ - DMA_CH_TRIGSRC_TCC0_CCB_gc = (0x43<<0), /* Timer/Counter C0 Compare or Capture B */ - DMA_CH_TRIGSRC_TCC0_CCC_gc = (0x44<<0), /* Timer/Counter C0 Compare or Capture C */ - DMA_CH_TRIGSRC_TCC0_CCD_gc = (0x45<<0), /* Timer/Counter C0 Compare or Capture D */ - DMA_CH_TRIGSRC_TCC1_OVF_gc = (0x46<<0), /* Timer/Counter C1 Overflow */ - DMA_CH_TRIGSRC_TCC1_ERR_gc = (0x47<<0), /* Timer/Counter C1 Error */ - DMA_CH_TRIGSRC_TCC1_CCA_gc = (0x48<<0), /* Timer/Counter C1 Compare or Capture A */ - DMA_CH_TRIGSRC_TCC1_CCB_gc = (0x49<<0), /* Timer/Counter C1 Compare or Capture B */ - DMA_CH_TRIGSRC_SPIC_gc = (0x4A<<0), /* SPI C Transfer Complete */ - DMA_CH_TRIGSRC_USARTC0_RXC_gc = (0x4B<<0), /* USART C0 Receive Complete */ - DMA_CH_TRIGSRC_USARTC0_DRE_gc = (0x4C<<0), /* USART C0 Data Register Empty */ - DMA_CH_TRIGSRC_USARTC1_RXC_gc = (0x4E<<0), /* USART C1 Receive Complete */ - DMA_CH_TRIGSRC_USARTC1_DRE_gc = (0x4F<<0), /* USART C1 Data Register Empty */ - DMA_CH_TRIGSRC_TCD0_OVF_gc = (0x60<<0), /* Timer/Counter D0 Overflow */ - DMA_CH_TRIGSRC_TCD0_ERR_gc = (0x61<<0), /* Timer/Counter D0 Error */ - DMA_CH_TRIGSRC_TCD0_CCA_gc = (0x62<<0), /* Timer/Counter D0 Compare or Capture A */ - DMA_CH_TRIGSRC_TCD0_CCB_gc = (0x63<<0), /* Timer/Counter D0 Compare or Capture B */ - DMA_CH_TRIGSRC_TCD0_CCC_gc = (0x64<<0), /* Timer/Counter D0 Compare or Capture C */ - DMA_CH_TRIGSRC_TCD0_CCD_gc = (0x65<<0), /* Timer/Counter D0 Compare or Capture D */ - DMA_CH_TRIGSRC_TCD1_OVF_gc = (0x66<<0), /* Timer/Counter D1 Overflow */ - DMA_CH_TRIGSRC_TCD1_ERR_gc = (0x67<<0), /* Timer/Counter D1 Error */ - DMA_CH_TRIGSRC_TCD1_CCA_gc = (0x68<<0), /* Timer/Counter D1 Compare or Capture A */ - DMA_CH_TRIGSRC_TCD1_CCB_gc = (0x69<<0), /* Timer/Counter D1 Compare or Capture B */ - DMA_CH_TRIGSRC_SPID_gc = (0x6A<<0), /* SPI D Transfer Complete */ - DMA_CH_TRIGSRC_USARTD0_RXC_gc = (0x6B<<0), /* USART D0 Receive Complete */ - DMA_CH_TRIGSRC_USARTD0_DRE_gc = (0x6C<<0), /* USART D0 Data Register Empty */ - DMA_CH_TRIGSRC_USARTD1_RXC_gc = (0x6E<<0), /* USART D1 Receive Complete */ - DMA_CH_TRIGSRC_USARTD1_DRE_gc = (0x6F<<0), /* USART D1 Data Register Empty */ - DMA_CH_TRIGSRC_TCE0_OVF_gc = (0x80<<0), /* Timer/Counter E0 Overflow */ - DMA_CH_TRIGSRC_TCE0_ERR_gc = (0x81<<0), /* Timer/Counter E0 Error */ - DMA_CH_TRIGSRC_TCE0_CCA_gc = (0x82<<0), /* Timer/Counter E0 Compare or Capture A */ - DMA_CH_TRIGSRC_TCE0_CCB_gc = (0x83<<0), /* Timer/Counter E0 Compare or Capture B */ - DMA_CH_TRIGSRC_TCE0_CCC_gc = (0x84<<0), /* Timer/Counter E0 Compare or Capture C */ - DMA_CH_TRIGSRC_TCE0_CCD_gc = (0x85<<0), /* Timer/Counter E0 Compare or Capture D */ - DMA_CH_TRIGSRC_TCE1_OVF_gc = (0x86<<0), /* Timer/Counter E1 Overflow */ - DMA_CH_TRIGSRC_TCE1_ERR_gc = (0x87<<0), /* Timer/Counter E1 Error */ - DMA_CH_TRIGSRC_TCE1_CCA_gc = (0x88<<0), /* Timer/Counter E1 Compare or Capture A */ - DMA_CH_TRIGSRC_TCE1_CCB_gc = (0x89<<0), /* Timer/Counter E1 Compare or Capture B */ - DMA_CH_TRIGSRC_SPIE_gc = (0x8A<<0), /* SPI E Transfer Complete */ - DMA_CH_TRIGSRC_USARTE0_RXC_gc = (0x8B<<0), /* USART E0 Receive Complete */ - DMA_CH_TRIGSRC_USARTE0_DRE_gc = (0x8C<<0), /* USART E0 Data Register Empty */ - DMA_CH_TRIGSRC_USARTE1_RXC_gc = (0x8E<<0), /* USART E1 Receive Complete */ - DMA_CH_TRIGSRC_USARTE1_DRE_gc = (0x8F<<0), /* USART E1 Data Register Empty */ - DMA_CH_TRIGSRC_TCF0_OVF_gc = (0xA0<<0), /* Timer/Counter F0 Overflow */ - DMA_CH_TRIGSRC_TCF0_ERR_gc = (0xA1<<0), /* Timer/Counter F0 Error */ - DMA_CH_TRIGSRC_TCF0_CCA_gc = (0xA2<<0), /* Timer/Counter F0 Compare or Capture A */ - DMA_CH_TRIGSRC_TCF0_CCB_gc = (0xA3<<0), /* Timer/Counter F0 Compare or Capture B */ - DMA_CH_TRIGSRC_TCF0_CCC_gc = (0xA4<<0), /* Timer/Counter F0 Compare or Capture C */ - DMA_CH_TRIGSRC_TCF0_CCD_gc = (0xA5<<0), /* Timer/Counter F0 Compare or Capture D */ - DMA_CH_TRIGSRC_TCF1_OVF_gc = (0xA6<<0), /* Timer/Counter F1 Overflow */ - DMA_CH_TRIGSRC_TCF1_ERR_gc = (0xA7<<0), /* Timer/Counter F1 Error */ - DMA_CH_TRIGSRC_TCF1_CCA_gc = (0xA8<<0), /* Timer/Counter F1 Compare or Capture A */ - DMA_CH_TRIGSRC_TCF1_CCB_gc = (0xA9<<0), /* Timer/Counter F1 Compare or Capture B */ - DMA_CH_TRIGSRC_SPIF_gc = (0xAA<<0), /* SPI F Transfer Complete */ - DMA_CH_TRIGSRC_USARTF0_RXC_gc = (0xAB<<0), /* USART F0 Receive Complete */ - DMA_CH_TRIGSRC_USARTF0_DRE_gc = (0xAC<<0), /* USART F0 Data Register Empty */ - DMA_CH_TRIGSRC_USARTF1_RXC_gc = (0xAE<<0), /* USART F1 Receive Complete */ - DMA_CH_TRIGSRC_USARTF1_DRE_gc = (0xAF<<0), /* USART F1 Data Register Empty */ -} DMA_CH_TRIGSRC_t; - -/* Double buffering mode */ -typedef enum DMA_DBUFMODE_enum -{ - DMA_DBUFMODE_DISABLED_gc = (0x00<<2), /* Double buffering disabled */ - DMA_DBUFMODE_CH01_gc = (0x01<<2), /* Double buffering enabled on channel 0/1 */ - DMA_DBUFMODE_CH23_gc = (0x02<<2), /* Double buffering enabled on channel 2/3 */ - DMA_DBUFMODE_CH01CH23_gc = (0x03<<2), /* Double buffering enabled on ch. 0/1 and ch. 2/3 */ -} DMA_DBUFMODE_t; - -/* Priority mode */ -typedef enum DMA_PRIMODE_enum -{ - DMA_PRIMODE_RR0123_gc = (0x00<<0), /* Round Robin */ - DMA_PRIMODE_CH0RR123_gc = (0x01<<0), /* Channel 0 > Round Robin on channel 1/2/3 */ - DMA_PRIMODE_CH01RR23_gc = (0x02<<0), /* Channel 0 > channel 1 > Round Robin on channel 2/3 */ - DMA_PRIMODE_CH0123_gc = (0x03<<0), /* Channel 0 > channel 1 > channel 2 > channel 3 */ -} DMA_PRIMODE_t; - -/* Interrupt level */ -typedef enum DMA_CH_ERRINTLVL_enum -{ - DMA_CH_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ - DMA_CH_ERRINTLVL_LO_gc = (0x01<<2), /* Low level */ - DMA_CH_ERRINTLVL_MED_gc = (0x02<<2), /* Medium level */ - DMA_CH_ERRINTLVL_HI_gc = (0x03<<2), /* High level */ -} DMA_CH_ERRINTLVL_t; - -/* Interrupt level */ -typedef enum DMA_CH_TRNINTLVL_enum -{ - DMA_CH_TRNINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ - DMA_CH_TRNINTLVL_LO_gc = (0x01<<0), /* Low level */ - DMA_CH_TRNINTLVL_MED_gc = (0x02<<0), /* Medium level */ - DMA_CH_TRNINTLVL_HI_gc = (0x03<<0), /* High level */ -} DMA_CH_TRNINTLVL_t; - - -/* --------------------------------------------------------------------------- -EVSYS - Event System --------------------------------------------------------------------------- -*/ - -/* Event System */ -typedef struct EVSYS_struct -{ - register8_t CH0MUX; /* Event Channel 0 Multiplexer */ - register8_t CH1MUX; /* Event Channel 1 Multiplexer */ - register8_t CH2MUX; /* Event Channel 2 Multiplexer */ - register8_t CH3MUX; /* Event Channel 3 Multiplexer */ - register8_t CH4MUX; /* Event Channel 4 Multiplexer */ - register8_t CH5MUX; /* Event Channel 5 Multiplexer */ - register8_t CH6MUX; /* Event Channel 6 Multiplexer */ - register8_t CH7MUX; /* Event Channel 7 Multiplexer */ - register8_t CH0CTRL; /* Channel 0 Control Register */ - register8_t CH1CTRL; /* Channel 1 Control Register */ - register8_t CH2CTRL; /* Channel 2 Control Register */ - register8_t CH3CTRL; /* Channel 3 Control Register */ - register8_t CH4CTRL; /* Channel 4 Control Register */ - register8_t CH5CTRL; /* Channel 5 Control Register */ - register8_t CH6CTRL; /* Channel 6 Control Register */ - register8_t CH7CTRL; /* Channel 7 Control Register */ - register8_t STROBE; /* Event Strobe */ - register8_t DATA; /* Event Data */ -} EVSYS_t; - -/* Quadrature Decoder Index Recognition Mode */ -typedef enum EVSYS_QDIRM_enum -{ - EVSYS_QDIRM_00_gc = (0x00<<5), /* QDPH0 = 0, QDPH90 = 0 */ - EVSYS_QDIRM_01_gc = (0x01<<5), /* QDPH0 = 0, QDPH90 = 1 */ - EVSYS_QDIRM_10_gc = (0x02<<5), /* QDPH0 = 1, QDPH90 = 0 */ - EVSYS_QDIRM_11_gc = (0x03<<5), /* QDPH0 = 1, QDPH90 = 1 */ -} EVSYS_QDIRM_t; - -/* Digital filter coefficient */ -typedef enum EVSYS_DIGFILT_enum -{ - EVSYS_DIGFILT_1SAMPLE_gc = (0x00<<0), /* 1 SAMPLE */ - EVSYS_DIGFILT_2SAMPLES_gc = (0x01<<0), /* 2 SAMPLES */ - EVSYS_DIGFILT_3SAMPLES_gc = (0x02<<0), /* 3 SAMPLES */ - EVSYS_DIGFILT_4SAMPLES_gc = (0x03<<0), /* 4 SAMPLES */ - EVSYS_DIGFILT_5SAMPLES_gc = (0x04<<0), /* 5 SAMPLES */ - EVSYS_DIGFILT_6SAMPLES_gc = (0x05<<0), /* 6 SAMPLES */ - EVSYS_DIGFILT_7SAMPLES_gc = (0x06<<0), /* 7 SAMPLES */ - EVSYS_DIGFILT_8SAMPLES_gc = (0x07<<0), /* 8 SAMPLES */ -} EVSYS_DIGFILT_t; - -/* Event Channel multiplexer input selection */ -typedef enum EVSYS_CHMUX_enum -{ - EVSYS_CHMUX_OFF_gc = (0x00<<0), /* Off */ - EVSYS_CHMUX_RTC_OVF_gc = (0x08<<0), /* RTC Overflow */ - EVSYS_CHMUX_RTC_CMP_gc = (0x09<<0), /* RTC Compare Match */ - EVSYS_CHMUX_ACA_CH0_gc = (0x10<<0), /* Analog Comparator A Channel 0 */ - EVSYS_CHMUX_ACA_CH1_gc = (0x11<<0), /* Analog Comparator A Channel 1 */ - EVSYS_CHMUX_ACA_WIN_gc = (0x12<<0), /* Analog Comparator A Window */ - EVSYS_CHMUX_ACB_CH0_gc = (0x13<<0), /* Analog Comparator B Channel 0 */ - EVSYS_CHMUX_ACB_CH1_gc = (0x14<<0), /* Analog Comparator B Channel 1 */ - EVSYS_CHMUX_ACB_WIN_gc = (0x15<<0), /* Analog Comparator B Window */ - EVSYS_CHMUX_ADCA_CH0_gc = (0x20<<0), /* ADC A Channel 0 */ - EVSYS_CHMUX_ADCA_CH1_gc = (0x21<<0), /* ADC A Channel 1 */ - EVSYS_CHMUX_ADCA_CH2_gc = (0x22<<0), /* ADC A Channel 2 */ - EVSYS_CHMUX_ADCA_CH3_gc = (0x23<<0), /* ADC A Channel 3 */ - EVSYS_CHMUX_ADCB_CH0_gc = (0x24<<0), /* ADC B Channel 0 */ - EVSYS_CHMUX_ADCB_CH1_gc = (0x25<<0), /* ADC B Channel 1 */ - EVSYS_CHMUX_ADCB_CH2_gc = (0x26<<0), /* ADC B Channel 2 */ - EVSYS_CHMUX_ADCB_CH3_gc = (0x27<<0), /* ADC B Channel 3 */ - EVSYS_CHMUX_PORTA_PIN0_gc = (0x50<<0), /* Port A, Pin0 */ - EVSYS_CHMUX_PORTA_PIN1_gc = (0x51<<0), /* Port A, Pin1 */ - EVSYS_CHMUX_PORTA_PIN2_gc = (0x52<<0), /* Port A, Pin2 */ - EVSYS_CHMUX_PORTA_PIN3_gc = (0x53<<0), /* Port A, Pin3 */ - EVSYS_CHMUX_PORTA_PIN4_gc = (0x54<<0), /* Port A, Pin4 */ - EVSYS_CHMUX_PORTA_PIN5_gc = (0x55<<0), /* Port A, Pin5 */ - EVSYS_CHMUX_PORTA_PIN6_gc = (0x56<<0), /* Port A, Pin6 */ - EVSYS_CHMUX_PORTA_PIN7_gc = (0x57<<0), /* Port A, Pin7 */ - EVSYS_CHMUX_PORTB_PIN0_gc = (0x58<<0), /* Port B, Pin0 */ - EVSYS_CHMUX_PORTB_PIN1_gc = (0x59<<0), /* Port B, Pin1 */ - EVSYS_CHMUX_PORTB_PIN2_gc = (0x5A<<0), /* Port B, Pin2 */ - EVSYS_CHMUX_PORTB_PIN3_gc = (0x5B<<0), /* Port B, Pin3 */ - EVSYS_CHMUX_PORTB_PIN4_gc = (0x5C<<0), /* Port B, Pin4 */ - EVSYS_CHMUX_PORTB_PIN5_gc = (0x5D<<0), /* Port B, Pin5 */ - EVSYS_CHMUX_PORTB_PIN6_gc = (0x5E<<0), /* Port B, Pin6 */ - EVSYS_CHMUX_PORTB_PIN7_gc = (0x5F<<0), /* Port B, Pin7 */ - EVSYS_CHMUX_PORTC_PIN0_gc = (0x60<<0), /* Port C, Pin0 */ - EVSYS_CHMUX_PORTC_PIN1_gc = (0x61<<0), /* Port C, Pin1 */ - EVSYS_CHMUX_PORTC_PIN2_gc = (0x62<<0), /* Port C, Pin2 */ - EVSYS_CHMUX_PORTC_PIN3_gc = (0x63<<0), /* Port C, Pin3 */ - EVSYS_CHMUX_PORTC_PIN4_gc = (0x64<<0), /* Port C, Pin4 */ - EVSYS_CHMUX_PORTC_PIN5_gc = (0x65<<0), /* Port C, Pin5 */ - EVSYS_CHMUX_PORTC_PIN6_gc = (0x66<<0), /* Port C, Pin6 */ - EVSYS_CHMUX_PORTC_PIN7_gc = (0x67<<0), /* Port C, Pin7 */ - EVSYS_CHMUX_PORTD_PIN0_gc = (0x68<<0), /* Port D, Pin0 */ - EVSYS_CHMUX_PORTD_PIN1_gc = (0x69<<0), /* Port D, Pin1 */ - EVSYS_CHMUX_PORTD_PIN2_gc = (0x6A<<0), /* Port D, Pin2 */ - EVSYS_CHMUX_PORTD_PIN3_gc = (0x6B<<0), /* Port D, Pin3 */ - EVSYS_CHMUX_PORTD_PIN4_gc = (0x6C<<0), /* Port D, Pin4 */ - EVSYS_CHMUX_PORTD_PIN5_gc = (0x6D<<0), /* Port D, Pin5 */ - EVSYS_CHMUX_PORTD_PIN6_gc = (0x6E<<0), /* Port D, Pin6 */ - EVSYS_CHMUX_PORTD_PIN7_gc = (0x6F<<0), /* Port D, Pin7 */ - EVSYS_CHMUX_PORTE_PIN0_gc = (0x70<<0), /* Port E, Pin0 */ - EVSYS_CHMUX_PORTE_PIN1_gc = (0x71<<0), /* Port E, Pin1 */ - EVSYS_CHMUX_PORTE_PIN2_gc = (0x72<<0), /* Port E, Pin2 */ - EVSYS_CHMUX_PORTE_PIN3_gc = (0x73<<0), /* Port E, Pin3 */ - EVSYS_CHMUX_PORTE_PIN4_gc = (0x74<<0), /* Port E, Pin4 */ - EVSYS_CHMUX_PORTE_PIN5_gc = (0x75<<0), /* Port E, Pin5 */ - EVSYS_CHMUX_PORTE_PIN6_gc = (0x76<<0), /* Port E, Pin6 */ - EVSYS_CHMUX_PORTE_PIN7_gc = (0x77<<0), /* Port E, Pin7 */ - EVSYS_CHMUX_PORTF_PIN0_gc = (0x78<<0), /* Port F, Pin0 */ - EVSYS_CHMUX_PORTF_PIN1_gc = (0x79<<0), /* Port F, Pin1 */ - EVSYS_CHMUX_PORTF_PIN2_gc = (0x7A<<0), /* Port F, Pin2 */ - EVSYS_CHMUX_PORTF_PIN3_gc = (0x7B<<0), /* Port F, Pin3 */ - EVSYS_CHMUX_PORTF_PIN4_gc = (0x7C<<0), /* Port F, Pin4 */ - EVSYS_CHMUX_PORTF_PIN5_gc = (0x7D<<0), /* Port F, Pin5 */ - EVSYS_CHMUX_PORTF_PIN6_gc = (0x7E<<0), /* Port F, Pin6 */ - EVSYS_CHMUX_PORTF_PIN7_gc = (0x7F<<0), /* Port F, Pin7 */ - EVSYS_CHMUX_PRESCALER_1_gc = (0x80<<0), /* Prescaler, divide by 1 */ - EVSYS_CHMUX_PRESCALER_2_gc = (0x81<<0), /* Prescaler, divide by 2 */ - EVSYS_CHMUX_PRESCALER_4_gc = (0x82<<0), /* Prescaler, divide by 4 */ - EVSYS_CHMUX_PRESCALER_8_gc = (0x83<<0), /* Prescaler, divide by 8 */ - EVSYS_CHMUX_PRESCALER_16_gc = (0x84<<0), /* Prescaler, divide by 16 */ - EVSYS_CHMUX_PRESCALER_32_gc = (0x85<<0), /* Prescaler, divide by 32 */ - EVSYS_CHMUX_PRESCALER_64_gc = (0x86<<0), /* Prescaler, divide by 64 */ - EVSYS_CHMUX_PRESCALER_128_gc = (0x87<<0), /* Prescaler, divide by 128 */ - EVSYS_CHMUX_PRESCALER_256_gc = (0x88<<0), /* Prescaler, divide by 256 */ - EVSYS_CHMUX_PRESCALER_512_gc = (0x89<<0), /* Prescaler, divide by 512 */ - EVSYS_CHMUX_PRESCALER_1024_gc = (0x8A<<0), /* Prescaler, divide by 1024 */ - EVSYS_CHMUX_PRESCALER_2048_gc = (0x8B<<0), /* Prescaler, divide by 2048 */ - EVSYS_CHMUX_PRESCALER_4096_gc = (0x8C<<0), /* Prescaler, divide by 4096 */ - EVSYS_CHMUX_PRESCALER_8192_gc = (0x8D<<0), /* Prescaler, divide by 8192 */ - EVSYS_CHMUX_PRESCALER_16384_gc = (0x8E<<0), /* Prescaler, divide by 16384 */ - EVSYS_CHMUX_PRESCALER_32768_gc = (0x8F<<0), /* Prescaler, divide by 32768 */ - EVSYS_CHMUX_TCC0_OVF_gc = (0xC0<<0), /* Timer/Counter C0 Overflow */ - EVSYS_CHMUX_TCC0_ERR_gc = (0xC1<<0), /* Timer/Counter C0 Error */ - EVSYS_CHMUX_TCC0_CCA_gc = (0xC4<<0), /* Timer/Counter C0 Compare or Capture A */ - EVSYS_CHMUX_TCC0_CCB_gc = (0xC5<<0), /* Timer/Counter C0 Compare or Capture B */ - EVSYS_CHMUX_TCC0_CCC_gc = (0xC6<<0), /* Timer/Counter C0 Compare or Capture C */ - EVSYS_CHMUX_TCC0_CCD_gc = (0xC7<<0), /* Timer/Counter C0 Compare or Capture D */ - EVSYS_CHMUX_TCC1_OVF_gc = (0xC8<<0), /* Timer/Counter C1 Overflow */ - EVSYS_CHMUX_TCC1_ERR_gc = (0xC9<<0), /* Timer/Counter C1 Error */ - EVSYS_CHMUX_TCC1_CCA_gc = (0xCC<<0), /* Timer/Counter C1 Compare or Capture A */ - EVSYS_CHMUX_TCC1_CCB_gc = (0xCD<<0), /* Timer/Counter C1 Compare or Capture B */ - EVSYS_CHMUX_TCD0_OVF_gc = (0xD0<<0), /* Timer/Counter D0 Overflow */ - EVSYS_CHMUX_TCD0_ERR_gc = (0xD1<<0), /* Timer/Counter D0 Error */ - EVSYS_CHMUX_TCD0_CCA_gc = (0xD4<<0), /* Timer/Counter D0 Compare or Capture A */ - EVSYS_CHMUX_TCD0_CCB_gc = (0xD5<<0), /* Timer/Counter D0 Compare or Capture B */ - EVSYS_CHMUX_TCD0_CCC_gc = (0xD6<<0), /* Timer/Counter D0 Compare or Capture C */ - EVSYS_CHMUX_TCD0_CCD_gc = (0xD7<<0), /* Timer/Counter D0 Compare or Capture D */ - EVSYS_CHMUX_TCD1_OVF_gc = (0xD8<<0), /* Timer/Counter D1 Overflow */ - EVSYS_CHMUX_TCD1_ERR_gc = (0xD9<<0), /* Timer/Counter D1 Error */ - EVSYS_CHMUX_TCD1_CCA_gc = (0xDC<<0), /* Timer/Counter D1 Compare or Capture A */ - EVSYS_CHMUX_TCD1_CCB_gc = (0xDD<<0), /* Timer/Counter D1 Compare or Capture B */ - EVSYS_CHMUX_TCE0_OVF_gc = (0xE0<<0), /* Timer/Counter E0 Overflow */ - EVSYS_CHMUX_TCE0_ERR_gc = (0xE1<<0), /* Timer/Counter E0 Error */ - EVSYS_CHMUX_TCE0_CCA_gc = (0xE4<<0), /* Timer/Counter E0 Compare or Capture A */ - EVSYS_CHMUX_TCE0_CCB_gc = (0xE5<<0), /* Timer/Counter E0 Compare or Capture B */ - EVSYS_CHMUX_TCE0_CCC_gc = (0xE6<<0), /* Timer/Counter E0 Compare or Capture C */ - EVSYS_CHMUX_TCE0_CCD_gc = (0xE7<<0), /* Timer/Counter E0 Compare or Capture D */ - EVSYS_CHMUX_TCE1_OVF_gc = (0xE8<<0), /* Timer/Counter E1 Overflow */ - EVSYS_CHMUX_TCE1_ERR_gc = (0xE9<<0), /* Timer/Counter E1 Error */ - EVSYS_CHMUX_TCE1_CCA_gc = (0xEC<<0), /* Timer/Counter E1 Compare or Capture A */ - EVSYS_CHMUX_TCE1_CCB_gc = (0xED<<0), /* Timer/Counter E1 Compare or Capture B */ - EVSYS_CHMUX_TCF0_OVF_gc = (0xF0<<0), /* Timer/Counter F0 Overflow */ - EVSYS_CHMUX_TCF0_ERR_gc = (0xF1<<0), /* Timer/Counter F0 Error */ - EVSYS_CHMUX_TCF0_CCA_gc = (0xF4<<0), /* Timer/Counter F0 Compare or Capture A */ - EVSYS_CHMUX_TCF0_CCB_gc = (0xF5<<0), /* Timer/Counter F0 Compare or Capture B */ - EVSYS_CHMUX_TCF0_CCC_gc = (0xF6<<0), /* Timer/Counter F0 Compare or Capture C */ - EVSYS_CHMUX_TCF0_CCD_gc = (0xF7<<0), /* Timer/Counter F0 Compare or Capture D */ - EVSYS_CHMUX_TCF1_OVF_gc = (0xF8<<0), /* Timer/Counter F1 Overflow */ - EVSYS_CHMUX_TCF1_ERR_gc = (0xF9<<0), /* Timer/Counter F1 Error */ - EVSYS_CHMUX_TCF1_CCA_gc = (0xFC<<0), /* Timer/Counter F1 Compare or Capture A */ - EVSYS_CHMUX_TCF1_CCB_gc = (0xFD<<0), /* Timer/Counter F1 Compare or Capture B */ -} EVSYS_CHMUX_t; - - -/* --------------------------------------------------------------------------- -NVM - Non Volatile Memory Controller --------------------------------------------------------------------------- -*/ - -/* Non-volatile Memory Controller */ -typedef struct NVM_struct -{ - register8_t ADDR0; /* Address Register 0 */ - register8_t ADDR1; /* Address Register 1 */ - register8_t ADDR2; /* Address Register 2 */ - register8_t reserved_0x03; - register8_t DATA0; /* Data Register 0 */ - register8_t DATA1; /* Data Register 1 */ - register8_t DATA2; /* Data Register 2 */ - register8_t reserved_0x07; - register8_t reserved_0x08; - register8_t reserved_0x09; - register8_t CMD; /* Command */ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t INTCTRL; /* Interrupt Control */ - register8_t reserved_0x0E; - register8_t STATUS; /* Status */ - register8_t LOCK_BITS; /* Lock Bits */ -} NVM_t; - -/* --------------------------------------------------------------------------- -NVM - Non Volatile Memory Controller --------------------------------------------------------------------------- -*/ - -/* Lock Bits */ -typedef struct NVM_LOCKBITS_struct -{ - register8_t LOCKBITS; /* Lock Bits */ -} NVM_LOCKBITS_t; - -/* --------------------------------------------------------------------------- -NVM - Non Volatile Memory Controller --------------------------------------------------------------------------- -*/ - -/* Fuses */ -typedef struct NVM_FUSES_struct -{ - register8_t FUSEBYTE0; /* JTAG User ID */ - register8_t FUSEBYTE1; /* Watchdog Configuration */ - register8_t FUSEBYTE2; /* Reset Configuration */ - register8_t reserved_0x03; - register8_t FUSEBYTE4; /* Start-up Configuration */ - register8_t FUSEBYTE5; /* EESAVE and BOD Level */ -} NVM_FUSES_t; - -/* --------------------------------------------------------------------------- -NVM - Non Volatile Memory Controller --------------------------------------------------------------------------- -*/ - -/* Production Signatures */ -typedef struct NVM_PROD_SIGNATURES_struct -{ - register8_t RCOSC2M; /* RCOSC 2MHz Calibration Value */ - register8_t reserved_0x01; - register8_t RCOSC32K; /* RCOSC 32kHz Calibration Value */ - register8_t RCOSC32M; /* RCOSC 32MHz Calibration Value */ - register8_t reserved_0x04; - register8_t reserved_0x05; - register8_t reserved_0x06; - register8_t reserved_0x07; - register8_t LOTNUM0; /* Lot Number Byte 0, ASCII */ - register8_t LOTNUM1; /* Lot Number Byte 1, ASCII */ - register8_t LOTNUM2; /* Lot Number Byte 2, ASCII */ - register8_t LOTNUM3; /* Lot Number Byte 3, ASCII */ - register8_t LOTNUM4; /* Lot Number Byte 4, ASCII */ - register8_t LOTNUM5; /* Lot Number Byte 5, ASCII */ - register8_t reserved_0x0E; - register8_t reserved_0x0F; - register8_t WAFNUM; /* Wafer Number */ - register8_t reserved_0x11; - register8_t COORDX0; /* Wafer Coordinate X Byte 0 */ - register8_t COORDX1; /* Wafer Coordinate X Byte 1 */ - register8_t COORDY0; /* Wafer Coordinate Y Byte 0 */ - register8_t COORDY1; /* Wafer Coordinate Y Byte 1 */ - register8_t reserved_0x16; - register8_t reserved_0x17; - register8_t reserved_0x18; - register8_t reserved_0x19; - register8_t reserved_0x1A; - register8_t reserved_0x1B; - register8_t reserved_0x1C; - register8_t reserved_0x1D; - register8_t reserved_0x1E; - register8_t reserved_0x1F; - register8_t ADCACAL0; /* ADCA Calibration Byte 0 */ - register8_t ADCACAL1; /* ADCA Calibration Byte 1 */ - register8_t reserved_0x22; - register8_t reserved_0x23; - register8_t ADCBCAL0; /* ADCB Calibration Byte 0 */ - register8_t ADCBCAL1; /* ADCB Calibration Byte 1 */ - register8_t reserved_0x26; - register8_t reserved_0x27; - register8_t reserved_0x28; - register8_t reserved_0x29; - register8_t reserved_0x2A; - register8_t reserved_0x2B; - register8_t reserved_0x2C; - register8_t reserved_0x2D; - register8_t TEMPSENSE0; /* Temperature Sensor Calibration Byte 0 */ - register8_t TEMPSENSE1; /* Temperature Sensor Calibration Byte 0 */ - register8_t DACAOFFCAL; /* DACA Calibration Byte 0 */ - register8_t DACAGAINCAL; /* DACA Calibration Byte 1 */ - register8_t DACBOFFCAL; /* DACB Calibration Byte 0 */ - register8_t DACBGAINCAL; /* DACB Calibration Byte 1 */ - register8_t reserved_0x34; - register8_t reserved_0x35; - register8_t reserved_0x36; - register8_t reserved_0x37; - register8_t reserved_0x38; - register8_t reserved_0x39; - register8_t reserved_0x3A; - register8_t reserved_0x3B; - register8_t reserved_0x3C; - register8_t reserved_0x3D; - register8_t reserved_0x3E; -} NVM_PROD_SIGNATURES_t; - -/* NVM Command */ -typedef enum NVM_CMD_enum -{ - NVM_CMD_NO_OPERATION_gc = (0x00<<0), /* Noop/Ordinary LPM */ - NVM_CMD_READ_CALIB_ROW_gc = (0x02<<0), /* Read calibration row */ - NVM_CMD_READ_USER_SIG_ROW_gc = (0x01<<0), /* Read user signature row */ - NVM_CMD_READ_EEPROM_gc = (0x06<<0), /* Read EEPROM */ - NVM_CMD_READ_FUSES_gc = (0x07<<0), /* Read fuse byte */ - NVM_CMD_WRITE_LOCK_BITS_gc = (0x08<<0), /* Write lock bits */ - NVM_CMD_ERASE_USER_SIG_ROW_gc = (0x18<<0), /* Erase user signature row */ - NVM_CMD_WRITE_USER_SIG_ROW_gc = (0x1A<<0), /* Write user signature row */ - NVM_CMD_ERASE_APP_gc = (0x20<<0), /* Erase Application Section */ - NVM_CMD_ERASE_APP_PAGE_gc = (0x22<<0), /* Erase Application Section page */ - NVM_CMD_LOAD_FLASH_BUFFER_gc = (0x23<<0), /* Load Flash page buffer */ - NVM_CMD_WRITE_APP_PAGE_gc = (0x24<<0), /* Write Application Section page */ - NVM_CMD_ERASE_WRITE_APP_PAGE_gc = (0x25<<0), /* Erase-and-write Application Section page */ - NVM_CMD_ERASE_FLASH_BUFFER_gc = (0x26<<0), /* Erase/flush Flash page buffer */ - NVM_CMD_ERASE_BOOT_PAGE_gc = (0x2A<<0), /* Erase Boot Section page */ - NVM_CMD_WRITE_BOOT_PAGE_gc = (0x2C<<0), /* Write Boot Section page */ - NVM_CMD_ERASE_WRITE_BOOT_PAGE_gc = (0x2D<<0), /* Erase-and-write Boot Section page */ - NVM_CMD_ERASE_EEPROM_gc = (0x30<<0), /* Erase EEPROM */ - NVM_CMD_ERASE_EEPROM_PAGE_gc = (0x32<<0), /* Erase EEPROM page */ - NVM_CMD_LOAD_EEPROM_BUFFER_gc = (0x33<<0), /* Load EEPROM page buffer */ - NVM_CMD_WRITE_EEPROM_PAGE_gc = (0x34<<0), /* Write EEPROM page */ - NVM_CMD_ERASE_WRITE_EEPROM_PAGE_gc = (0x35<<0), /* Erase-and-write EEPROM page */ - NVM_CMD_ERASE_EEPROM_BUFFER_gc = (0x36<<0), /* Erase/flush EEPROM page buffer */ - NVM_CMD_APP_CRC_gc = (0x38<<0), /* Generate Application section CRC */ - NVM_CMD_BOOT_CRC_gc = (0x39<<0), /* Generate Boot Section CRC */ - NVM_CMD_FLASH_RANGE_CRC_gc = (0x3A<<0), /* Generate Flash Range CRC */ -} NVM_CMD_t; - -/* SPM ready interrupt level */ -typedef enum NVM_SPMLVL_enum -{ - NVM_SPMLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ - NVM_SPMLVL_LO_gc = (0x01<<2), /* Low level */ - NVM_SPMLVL_MED_gc = (0x02<<2), /* Medium level */ - NVM_SPMLVL_HI_gc = (0x03<<2), /* High level */ -} NVM_SPMLVL_t; - -/* EEPROM ready interrupt level */ -typedef enum NVM_EELVL_enum -{ - NVM_EELVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ - NVM_EELVL_LO_gc = (0x01<<0), /* Low level */ - NVM_EELVL_MED_gc = (0x02<<0), /* Medium level */ - NVM_EELVL_HI_gc = (0x03<<0), /* High level */ -} NVM_EELVL_t; - -/* Boot lock bits - boot setcion */ -typedef enum NVM_BLBB_enum -{ - NVM_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ - NVM_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ - NVM_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ - NVM_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ -} NVM_BLBB_t; - -/* Boot lock bits - application section */ -typedef enum NVM_BLBA_enum -{ - NVM_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ - NVM_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ - NVM_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ - NVM_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ -} NVM_BLBA_t; - -/* Boot lock bits - application table section */ -typedef enum NVM_BLBAT_enum -{ - NVM_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ - NVM_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ - NVM_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ - NVM_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ -} NVM_BLBAT_t; - -/* Lock bits */ -typedef enum NVM_LB_enum -{ - NVM_LB_NOLOCK_gc = (0x03<<0), /* No locks */ - NVM_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ - NVM_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ -} NVM_LB_t; - -/* Boot Loader Section Reset Vector */ -typedef enum BOOTRST_enum -{ - BOOTRST_BOOTLDR_gc = (0x00<<6), /* Boot Loader Reset */ - BOOTRST_APPLICATION_gc = (0x01<<6), /* Application Reset */ -} BOOTRST_t; - -/* BOD operation */ -typedef enum BOD_enum -{ - BOD_INSAMPLEDMODE_gc = (0x01<<2), /* BOD enabled in sampled mode */ - BOD_CONTINOUSLY_gc = (0x02<<2), /* BOD enabled continuously */ - BOD_DISABLED_gc = (0x03<<2), /* BOD Disabled */ -} BOD_t; - -/* Watchdog (Window) Timeout Period */ -typedef enum WD_enum -{ - WD_8CLK_gc = (0x00<<4), /* 8 cycles (8ms @ 3.3V) */ - WD_16CLK_gc = (0x01<<4), /* 16 cycles (16ms @ 3.3V) */ - WD_32CLK_gc = (0x02<<4), /* 32 cycles (32ms @ 3.3V) */ - WD_64CLK_gc = (0x03<<4), /* 64 cycles (64ms @ 3.3V) */ - WD_128CLK_gc = (0x04<<4), /* 128 cycles (0.125s @ 3.3V) */ - WD_256CLK_gc = (0x05<<4), /* 256 cycles (0.25s @ 3.3V) */ - WD_512CLK_gc = (0x06<<4), /* 512 cycles (0.5s @ 3.3V) */ - WD_1KCLK_gc = (0x07<<4), /* 1K cycles (1s @ 3.3V) */ - WD_2KCLK_gc = (0x08<<4), /* 2K cycles (2s @ 3.3V) */ - WD_4KCLK_gc = (0x09<<4), /* 4K cycles (4s @ 3.3V) */ - WD_8KCLK_gc = (0x0A<<4), /* 8K cycles (8s @ 3.3V) */ -} WD_t; - -/* Start-up Time */ -typedef enum SUT_enum -{ - SUT_0MS_gc = (0x03<<2), /* 0 ms */ - SUT_4MS_gc = (0x01<<2), /* 4 ms */ - SUT_64MS_gc = (0x00<<2), /* 64 ms */ -} SUT_t; - -/* Brown Out Detection Voltage Level */ -typedef enum BODLVL_enum -{ - BODLVL_1V6_gc = (0x07<<0), /* 1.6 V */ - BODLVL_1V9_gc = (0x06<<0), /* 1.8 V */ - BODLVL_2V1_gc = (0x05<<0), /* 2.0 V */ - BODLVL_2V4_gc = (0x04<<0), /* 2.2 V */ - BODLVL_2V6_gc = (0x03<<0), /* 2.4 V */ - BODLVL_2V9_gc = (0x02<<0), /* 2.7 V */ - BODLVL_3V2_gc = (0x01<<0), /* 2.9 V */ -} BODLVL_t; - - -/* --------------------------------------------------------------------------- -AC - Analog Comparator --------------------------------------------------------------------------- -*/ - -/* Analog Comparator */ -typedef struct AC_struct -{ - register8_t AC0CTRL; /* Comparator 0 Control */ - register8_t AC1CTRL; /* Comparator 1 Control */ - register8_t AC0MUXCTRL; /* Comparator 0 MUX Control */ - register8_t AC1MUXCTRL; /* Comparator 1 MUX Control */ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t WINCTRL; /* Window Mode Control */ - register8_t STATUS; /* Status */ -} AC_t; - -/* Interrupt mode */ -typedef enum AC_INTMODE_enum -{ - AC_INTMODE_BOTHEDGES_gc = (0x00<<6), /* Interrupt on both edges */ - AC_INTMODE_FALLING_gc = (0x02<<6), /* Interrupt on falling edge */ - AC_INTMODE_RISING_gc = (0x03<<6), /* Interrupt on rising edge */ -} AC_INTMODE_t; - -/* Interrupt level */ -typedef enum AC_INTLVL_enum -{ - AC_INTLVL_OFF_gc = (0x00<<4), /* Interrupt disabled */ - AC_INTLVL_LO_gc = (0x01<<4), /* Low level */ - AC_INTLVL_MED_gc = (0x02<<4), /* Medium level */ - AC_INTLVL_HI_gc = (0x03<<4), /* High level */ -} AC_INTLVL_t; - -/* Hysteresis mode selection */ -typedef enum AC_HYSMODE_enum -{ - AC_HYSMODE_NO_gc = (0x00<<1), /* No hysteresis */ - AC_HYSMODE_SMALL_gc = (0x01<<1), /* Small hysteresis */ - AC_HYSMODE_LARGE_gc = (0x02<<1), /* Large hysteresis */ -} AC_HYSMODE_t; - -/* Positive input multiplexer selection */ -typedef enum AC_MUXPOS_enum -{ - AC_MUXPOS_PIN0_gc = (0x00<<3), /* Pin 0 */ - AC_MUXPOS_PIN1_gc = (0x01<<3), /* Pin 1 */ - AC_MUXPOS_PIN2_gc = (0x02<<3), /* Pin 2 */ - AC_MUXPOS_PIN3_gc = (0x03<<3), /* Pin 3 */ - AC_MUXPOS_PIN4_gc = (0x04<<3), /* Pin 4 */ - AC_MUXPOS_PIN5_gc = (0x05<<3), /* Pin 5 */ - AC_MUXPOS_PIN6_gc = (0x06<<3), /* Pin 6 */ - AC_MUXPOS_DAC_gc = (0x07<<3), /* DAC output */ -} AC_MUXPOS_t; - -/* Negative input multiplexer selection */ -typedef enum AC_MUXNEG_enum -{ - AC_MUXNEG_PIN0_gc = (0x00<<0), /* Pin 0 */ - AC_MUXNEG_PIN1_gc = (0x01<<0), /* Pin 1 */ - AC_MUXNEG_PIN3_gc = (0x02<<0), /* Pin 3 */ - AC_MUXNEG_PIN5_gc = (0x03<<0), /* Pin 5 */ - AC_MUXNEG_PIN7_gc = (0x04<<0), /* Pin 7 */ - AC_MUXNEG_DAC_gc = (0x05<<0), /* DAC output */ - AC_MUXNEG_BANDGAP_gc = (0x06<<0), /* Bandgap Reference */ - AC_MUXNEG_SCALER_gc = (0x07<<0), /* Internal voltage scaler */ -} AC_MUXNEG_t; - -/* Windows interrupt mode */ -typedef enum AC_WINTMODE_enum -{ - AC_WINTMODE_ABOVE_gc = (0x00<<2), /* Interrupt on above window */ - AC_WINTMODE_INSIDE_gc = (0x01<<2), /* Interrupt on inside window */ - AC_WINTMODE_BELOW_gc = (0x02<<2), /* Interrupt on below window */ - AC_WINTMODE_OUTSIDE_gc = (0x03<<2), /* Interrupt on outside window */ -} AC_WINTMODE_t; - -/* Window interrupt level */ -typedef enum AC_WINTLVL_enum -{ - AC_WINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ - AC_WINTLVL_LO_gc = (0x01<<0), /* Low priority */ - AC_WINTLVL_MED_gc = (0x02<<0), /* Medium priority */ - AC_WINTLVL_HI_gc = (0x03<<0), /* High priority */ -} AC_WINTLVL_t; - -/* Window mode state */ -typedef enum AC_WSTATE_enum -{ - AC_WSTATE_ABOVE_gc = (0x00<<6), /* Signal above window */ - AC_WSTATE_INSIDE_gc = (0x01<<6), /* Signal inside window */ - AC_WSTATE_BELOW_gc = (0x02<<6), /* Signal below window */ -} AC_WSTATE_t; - - -/* --------------------------------------------------------------------------- -ADC - Analog/Digital Converter --------------------------------------------------------------------------- -*/ - -/* ADC Channel */ -typedef struct ADC_CH_struct -{ - register8_t CTRL; /* Control Register */ - register8_t MUXCTRL; /* MUX Control */ - register8_t INTCTRL; /* Channel Interrupt Control */ - register8_t INTFLAGS; /* Interrupt Flags */ - _WORDREGISTER(RES); /* Channel Result */ - register8_t reserved_0x6; - register8_t reserved_0x7; -} ADC_CH_t; - -/* --------------------------------------------------------------------------- -ADC - Analog/Digital Converter --------------------------------------------------------------------------- -*/ - -/* Analog-to-Digital Converter */ -typedef struct ADC_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t REFCTRL; /* Reference Control */ - register8_t EVCTRL; /* Event Control */ - register8_t PRESCALER; /* Clock Prescaler */ - register8_t reserved_0x05; - register8_t INTFLAGS; /* Interrupt Flags */ - register8_t reserved_0x07; - register8_t reserved_0x08; - register8_t reserved_0x09; - register8_t reserved_0x0A; - register8_t reserved_0x0B; - _WORDREGISTER(CAL); /* Calibration Value */ - register8_t reserved_0x0E; - register8_t reserved_0x0F; - _WORDREGISTER(CH0RES); /* Channel 0 Result */ - _WORDREGISTER(CH1RES); /* Channel 1 Result */ - _WORDREGISTER(CH2RES); /* Channel 2 Result */ - _WORDREGISTER(CH3RES); /* Channel 3 Result */ - _WORDREGISTER(CMP); /* Compare Value */ - register8_t reserved_0x1A; - register8_t reserved_0x1B; - register8_t reserved_0x1C; - register8_t reserved_0x1D; - register8_t reserved_0x1E; - register8_t reserved_0x1F; - ADC_CH_t CH0; /* ADC Channel 0 */ - ADC_CH_t CH1; /* ADC Channel 1 */ - ADC_CH_t CH2; /* ADC Channel 2 */ - ADC_CH_t CH3; /* ADC Channel 3 */ -} ADC_t; - -/* Positive input multiplexer selection */ -typedef enum ADC_CH_MUXPOS_enum -{ - ADC_CH_MUXPOS_PIN0_gc = (0x00<<3), /* Input pin 0 */ - ADC_CH_MUXPOS_PIN1_gc = (0x01<<3), /* Input pin 1 */ - ADC_CH_MUXPOS_PIN2_gc = (0x02<<3), /* Input pin 2 */ - ADC_CH_MUXPOS_PIN3_gc = (0x03<<3), /* Input pin 3 */ - ADC_CH_MUXPOS_PIN4_gc = (0x04<<3), /* Input pin 4 */ - ADC_CH_MUXPOS_PIN5_gc = (0x05<<3), /* Input pin 5 */ - ADC_CH_MUXPOS_PIN6_gc = (0x06<<3), /* Input pin 6 */ - ADC_CH_MUXPOS_PIN7_gc = (0x07<<3), /* Input pin 7 */ -} ADC_CH_MUXPOS_t; - -/* Internal input multiplexer selections */ -typedef enum ADC_CH_MUXINT_enum -{ - ADC_CH_MUXINT_TEMP_gc = (0x00<<3), /* Temperature Reference */ - ADC_CH_MUXINT_BANDGAP_gc = (0x01<<3), /* Bandgap Reference */ - ADC_CH_MUXINT_SCALEDVCC_gc = (0x02<<3), /* 1/10 scaled VCC */ - ADC_CH_MUXINT_DAC_gc = (0x03<<3), /* DAC output */ -} ADC_CH_MUXINT_t; - -/* Negative input multiplexer selection */ -typedef enum ADC_CH_MUXNEG_enum -{ - ADC_CH_MUXNEG_PIN0_gc = (0x00<<0), /* Input pin 0 */ - ADC_CH_MUXNEG_PIN1_gc = (0x01<<0), /* Input pin 1 */ - ADC_CH_MUXNEG_PIN2_gc = (0x02<<0), /* Input pin 2 */ - ADC_CH_MUXNEG_PIN3_gc = (0x03<<0), /* Input pin 3 */ - ADC_CH_MUXNEG_PIN4_gc = (0x04<<0), /* Input pin 4 */ - ADC_CH_MUXNEG_PIN5_gc = (0x05<<0), /* Input pin 5 */ - ADC_CH_MUXNEG_PIN6_gc = (0x06<<0), /* Input pin 6 */ - ADC_CH_MUXNEG_PIN7_gc = (0x07<<0), /* Input pin 7 */ -} ADC_CH_MUXNEG_t; - -/* Input mode */ -typedef enum ADC_CH_INPUTMODE_enum -{ - ADC_CH_INPUTMODE_INTERNAL_gc = (0x00<<0), /* Internal inputs, no gain */ - ADC_CH_INPUTMODE_SINGLEENDED_gc = (0x01<<0), /* Single-ended input, no gain */ - ADC_CH_INPUTMODE_DIFF_gc = (0x02<<0), /* Differential input, no gain */ - ADC_CH_INPUTMODE_DIFFWGAIN_gc = (0x03<<0), /* Differential input, with gain */ -} ADC_CH_INPUTMODE_t; - -/* Gain factor */ -typedef enum ADC_CH_GAIN_enum -{ - ADC_CH_GAIN_1X_gc = (0x00<<2), /* 1x gain */ - ADC_CH_GAIN_2X_gc = (0x01<<2), /* 2x gain */ - ADC_CH_GAIN_4X_gc = (0x02<<2), /* 4x gain */ - ADC_CH_GAIN_8X_gc = (0x03<<2), /* 8x gain */ - ADC_CH_GAIN_16X_gc = (0x04<<2), /* 16x gain */ - ADC_CH_GAIN_32X_gc = (0x05<<2), /* 32x gain */ - ADC_CH_GAIN_64X_gc = (0x06<<2), /* 64x gain */ -} ADC_CH_GAIN_t; - -/* Conversion result resolution */ -typedef enum ADC_RESOLUTION_enum -{ - ADC_RESOLUTION_12BIT_gc = (0x00<<1), /* 12-bit right-adjusted result */ - ADC_RESOLUTION_8BIT_gc = (0x02<<1), /* 8-bit right-adjusted result */ - ADC_RESOLUTION_LEFT12BIT_gc = (0x03<<1), /* 12-bit left-adjusted result */ -} ADC_RESOLUTION_t; - -/* Voltage reference selection */ -typedef enum ADC_REFSEL_enum -{ - ADC_REFSEL_INT1V_gc = (0x00<<4), /* Internal 1V */ - ADC_REFSEL_VCC_gc = (0x01<<4), /* Internal VCC / 1.6V */ - ADC_REFSEL_AREFA_gc = (0x02<<4), /* External reference on PORT A */ - ADC_REFSEL_AREFB_gc = (0x03<<4), /* External reference on PORT B */ -} ADC_REFSEL_t; - -/* Channel sweep selection */ -typedef enum ADC_SWEEP_enum -{ - ADC_SWEEP_0_gc = (0x00<<6), /* ADC Channel 0 */ - ADC_SWEEP_01_gc = (0x01<<6), /* ADC Channel 0,1 */ - ADC_SWEEP_012_gc = (0x02<<6), /* ADC Channel 0,1,2 */ - ADC_SWEEP_0123_gc = (0x03<<6), /* ADC Channel 0,1,2,3 */ -} ADC_SWEEP_t; - -/* Event channel input selection */ -typedef enum ADC_EVSEL_enum -{ - ADC_EVSEL_0123_gc = (0x00<<3), /* Event Channel 0,1,2,3 */ - ADC_EVSEL_1234_gc = (0x01<<3), /* Event Channel 1,2,3,4 */ - ADC_EVSEL_2345_gc = (0x02<<3), /* Event Channel 2,3,4,5 */ - ADC_EVSEL_3456_gc = (0x03<<3), /* Event Channel 3,4,5,6 */ - ADC_EVSEL_4567_gc = (0x04<<3), /* Event Channel 4,5,6,7 */ - ADC_EVSEL_567_gc = (0x05<<3), /* Event Channel 5,6,7 */ - ADC_EVSEL_67_gc = (0x06<<3), /* Event Channel 6,7 */ - ADC_EVSEL_7_gc = (0x07<<3), /* Event Channel 7 */ -} ADC_EVSEL_t; - -/* Event action selection */ -typedef enum ADC_EVACT_enum -{ - ADC_EVACT_NONE_gc = (0x00<<0), /* No event action */ - ADC_EVACT_CH0_gc = (0x01<<0), /* First event triggers channel 0 */ - ADC_EVACT_CH01_gc = (0x02<<0), /* First two events trigger channel 0,1 */ - ADC_EVACT_CH012_gc = (0x03<<0), /* First three events trigger channel 0,1,2 */ - ADC_EVACT_CH0123_gc = (0x04<<0), /* Events trigger channel 0,1,2,3 */ - ADC_EVACT_SWEEP_gc = (0x05<<0), /* First event triggers sweep */ - ADC_EVACT_SYNCHSWEEP_gc = (0x06<<0), /* First event triggers synchronized sweep */ -} ADC_EVACT_t; - -/* Interupt mode */ -typedef enum ADC_CH_INTMODE_enum -{ - ADC_CH_INTMODE_COMPLETE_gc = (0x00<<2), /* Interrupt on conversion complete */ - ADC_CH_INTMODE_BELOW_gc = (0x01<<2), /* Interrupt on result below compare value */ - ADC_CH_INTMODE_ABOVE_gc = (0x03<<2), /* Interrupt on result above compare value */ -} ADC_CH_INTMODE_t; - -/* Interrupt level */ -typedef enum ADC_CH_INTLVL_enum -{ - ADC_CH_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ - ADC_CH_INTLVL_LO_gc = (0x01<<0), /* Low level */ - ADC_CH_INTLVL_MED_gc = (0x02<<0), /* Medium level */ - ADC_CH_INTLVL_HI_gc = (0x03<<0), /* High level */ -} ADC_CH_INTLVL_t; - -/* DMA request selection */ -typedef enum ADC_DMASEL_enum -{ - ADC_DMASEL_OFF_gc = (0x00<<6), /* Combined DMA request OFF */ - ADC_DMASEL_CH01_gc = (0x01<<6), /* ADC Channel 0 or 1 */ - ADC_DMASEL_CH012_gc = (0x02<<6), /* ADC Channel 0 or 1 or 2 */ - ADC_DMASEL_CH0123_gc = (0x03<<6), /* ADC Channel 0 or 1 or 2 or 3 */ -} ADC_DMASEL_t; - -/* Clock prescaler */ -typedef enum ADC_PRESCALER_enum -{ - ADC_PRESCALER_DIV4_gc = (0x00<<0), /* Divide clock by 4 */ - ADC_PRESCALER_DIV8_gc = (0x01<<0), /* Divide clock by 8 */ - ADC_PRESCALER_DIV16_gc = (0x02<<0), /* Divide clock by 16 */ - ADC_PRESCALER_DIV32_gc = (0x03<<0), /* Divide clock by 32 */ - ADC_PRESCALER_DIV64_gc = (0x04<<0), /* Divide clock by 64 */ - ADC_PRESCALER_DIV128_gc = (0x05<<0), /* Divide clock by 128 */ - ADC_PRESCALER_DIV256_gc = (0x06<<0), /* Divide clock by 256 */ - ADC_PRESCALER_DIV512_gc = (0x07<<0), /* Divide clock by 512 */ -} ADC_PRESCALER_t; - - -/* --------------------------------------------------------------------------- -DAC - Digital/Analog Converter --------------------------------------------------------------------------- -*/ - -/* Digital-to-Analog Converter */ -typedef struct DAC_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t CTRLC; /* Control Register C */ - register8_t EVCTRL; /* Event Input Control */ - register8_t TIMCTRL; /* Timing Control */ - register8_t STATUS; /* Status */ - register8_t reserved_0x06; - register8_t reserved_0x07; - register8_t GAINCAL; /* Gain Calibration */ - register8_t OFFSETCAL; /* Offset Calibration */ - register8_t reserved_0x0A; - register8_t reserved_0x0B; - register8_t reserved_0x0C; - register8_t reserved_0x0D; - register8_t reserved_0x0E; - register8_t reserved_0x0F; - register8_t reserved_0x10; - register8_t reserved_0x11; - register8_t reserved_0x12; - register8_t reserved_0x13; - register8_t reserved_0x14; - register8_t reserved_0x15; - register8_t reserved_0x16; - register8_t reserved_0x17; - _WORDREGISTER(CH0DATA); /* Channel 0 Data */ - _WORDREGISTER(CH1DATA); /* Channel 1 Data */ -} DAC_t; - -/* Output channel selection */ -typedef enum DAC_CHSEL_enum -{ - DAC_CHSEL_SINGLE_gc = (0x00<<5), /* Single channel operation (Channel A only) */ - DAC_CHSEL_DUAL_gc = (0x02<<5), /* Dual channel operation (S/H on both channels) */ -} DAC_CHSEL_t; - -/* Reference voltage selection */ -typedef enum DAC_REFSEL_enum -{ - DAC_REFSEL_INT1V_gc = (0x00<<3), /* Internal 1V */ - DAC_REFSEL_AVCC_gc = (0x01<<3), /* Analog supply voltage */ - DAC_REFSEL_AREFA_gc = (0x02<<3), /* External reference on AREF on PORTA */ - DAC_REFSEL_AREFB_gc = (0x03<<3), /* External reference on AREF on PORTB */ -} DAC_REFSEL_t; - -/* Event channel selection */ -typedef enum DAC_EVSEL_enum -{ - DAC_EVSEL_0_gc = (0x00<<0), /* Event Channel 0 */ - DAC_EVSEL_1_gc = (0x01<<0), /* Event Channel 1 */ - DAC_EVSEL_2_gc = (0x02<<0), /* Event Channel 2 */ - DAC_EVSEL_3_gc = (0x03<<0), /* Event Channel 3 */ - DAC_EVSEL_4_gc = (0x04<<0), /* Event Channel 4 */ - DAC_EVSEL_5_gc = (0x05<<0), /* Event Channel 5 */ - DAC_EVSEL_6_gc = (0x06<<0), /* Event Channel 6 */ - DAC_EVSEL_7_gc = (0x07<<0), /* Event Channel 7 */ -} DAC_EVSEL_t; - -/* Conversion interval */ -typedef enum DAC_CONINTVAL_enum -{ - DAC_CONINTVAL_1CLK_gc = (0x00<<4), /* 1 CLK / 2 CLK in S/H mode */ - DAC_CONINTVAL_2CLK_gc = (0x01<<4), /* 2 CLK / 3 CLK in S/H mode */ - DAC_CONINTVAL_4CLK_gc = (0x02<<4), /* 4 CLK / 6 CLK in S/H mode */ - DAC_CONINTVAL_8CLK_gc = (0x03<<4), /* 8 CLK / 12 CLK in S/H mode */ - DAC_CONINTVAL_16CLK_gc = (0x04<<4), /* 16 CLK / 24 CLK in S/H mode */ - DAC_CONINTVAL_32CLK_gc = (0x05<<4), /* 32 CLK / 48 CLK in S/H mode */ - DAC_CONINTVAL_64CLK_gc = (0x06<<4), /* 64 CLK / 96 CLK in S/H mode */ - DAC_CONINTVAL_128CLK_gc = (0x07<<4), /* 128 CLK / 192 CLK in S/H mode */ -} DAC_CONINTVAL_t; - -/* Refresh rate */ -typedef enum DAC_REFRESH_enum -{ - DAC_REFRESH_16CLK_gc = (0x00<<0), /* 16 CLK */ - DAC_REFRESH_32CLK_gc = (0x01<<0), /* 32 CLK */ - DAC_REFRESH_64CLK_gc = (0x02<<0), /* 64 CLK */ - DAC_REFRESH_128CLK_gc = (0x03<<0), /* 128 CLK */ - DAC_REFRESH_256CLK_gc = (0x04<<0), /* 256 CLK */ - DAC_REFRESH_512CLK_gc = (0x05<<0), /* 512 CLK */ - DAC_REFRESH_1024CLK_gc = (0x06<<0), /* 1024 CLK */ - DAC_REFRESH_2048CLK_gc = (0x07<<0), /* 2048 CLK */ - DAC_REFRESH_4096CLK_gc = (0x08<<0), /* 4096 CLK */ - DAC_REFRESH_8192CLK_gc = (0x09<<0), /* 8192 CLK */ - DAC_REFRESH_16384CLK_gc = (0x0A<<0), /* 16384 CLK */ - DAC_REFRESH_32768CLK_gc = (0x0B<<0), /* 32768 CLK */ - DAC_REFRESH_65536CLK_gc = (0x0C<<0), /* 65536 CLK */ - DAC_REFRESH_OFF_gc = (0x0F<<0), /* Auto refresh OFF */ -} DAC_REFRESH_t; - - -/* --------------------------------------------------------------------------- -RTC - Real-Time Clounter --------------------------------------------------------------------------- -*/ - -/* Real-Time Counter */ -typedef struct RTC_struct -{ - register8_t CTRL; /* Control Register */ - register8_t STATUS; /* Status Register */ - register8_t INTCTRL; /* Interrupt Control Register */ - register8_t INTFLAGS; /* Interrupt Flags */ - register8_t TEMP; /* Temporary register */ - register8_t reserved_0x05; - register8_t reserved_0x06; - register8_t reserved_0x07; - _WORDREGISTER(CNT); /* Count Register */ - _WORDREGISTER(PER); /* Period Register */ - _WORDREGISTER(COMP); /* Compare Register */ -} RTC_t; - -/* Prescaler Factor */ -typedef enum RTC_PRESCALER_enum -{ - RTC_PRESCALER_OFF_gc = (0x00<<0), /* RTC Off */ - RTC_PRESCALER_DIV1_gc = (0x01<<0), /* RTC Clock */ - RTC_PRESCALER_DIV2_gc = (0x02<<0), /* RTC Clock / 2 */ - RTC_PRESCALER_DIV8_gc = (0x03<<0), /* RTC Clock / 8 */ - RTC_PRESCALER_DIV16_gc = (0x04<<0), /* RTC Clock / 16 */ - RTC_PRESCALER_DIV64_gc = (0x05<<0), /* RTC Clock / 64 */ - RTC_PRESCALER_DIV256_gc = (0x06<<0), /* RTC Clock / 256 */ - RTC_PRESCALER_DIV1024_gc = (0x07<<0), /* RTC Clock / 1024 */ -} RTC_PRESCALER_t; - -/* Compare Interrupt level */ -typedef enum RTC_COMPINTLVL_enum -{ - RTC_COMPINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ - RTC_COMPINTLVL_LO_gc = (0x01<<2), /* Low Level */ - RTC_COMPINTLVL_MED_gc = (0x02<<2), /* Medium Level */ - RTC_COMPINTLVL_HI_gc = (0x03<<2), /* High Level */ -} RTC_COMPINTLVL_t; - -/* Overflow Interrupt level */ -typedef enum RTC_OVFINTLVL_enum -{ - RTC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - RTC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ - RTC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ - RTC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ -} RTC_OVFINTLVL_t; - - -/* --------------------------------------------------------------------------- -EBI - External Bus Interface --------------------------------------------------------------------------- -*/ - -/* EBI Chip Select Module */ -typedef struct EBI_CS_struct -{ - register8_t CTRLA; /* Chip Select Control Register A */ - register8_t CTRLB; /* Chip Select Control Register B */ - _WORDREGISTER(BASEADDR); /* Chip Select Base Address */ -} EBI_CS_t; - -/* --------------------------------------------------------------------------- -EBI - External Bus Interface --------------------------------------------------------------------------- -*/ - -/* External Bus Interface */ -typedef struct EBI_struct -{ - register8_t CTRL; /* Control */ - register8_t SDRAMCTRLA; /* SDRAM Control Register A */ - register8_t reserved_0x02; - register8_t reserved_0x03; - _WORDREGISTER(REFRESH); /* SDRAM Refresh Period */ - _WORDREGISTER(INITDLY); /* SDRAM Initialization Delay */ - register8_t SDRAMCTRLB; /* SDRAM Control Register B */ - register8_t SDRAMCTRLC; /* SDRAM Control Register C */ - register8_t reserved_0x0A; - register8_t reserved_0x0B; - register8_t reserved_0x0C; - register8_t reserved_0x0D; - register8_t reserved_0x0E; - register8_t reserved_0x0F; - EBI_CS_t CS0; /* Chip Select 0 */ - EBI_CS_t CS1; /* Chip Select 1 */ - EBI_CS_t CS2; /* Chip Select 2 */ - EBI_CS_t CS3; /* Chip Select 3 */ -} EBI_t; - -/* Chip Select adress space */ -typedef enum EBI_CS_ASIZE_enum -{ - EBI_CS_ASIZE_256B_gc = (0x00<<2), /* 256 bytes */ - EBI_CS_ASIZE_512B_gc = (0x01<<2), /* 512 bytes */ - EBI_CS_ASIZE_1KB_gc = (0x02<<2), /* 1K bytes */ - EBI_CS_ASIZE_2KB_gc = (0x03<<2), /* 2K bytes */ - EBI_CS_ASIZE_4KB_gc = (0x04<<2), /* 4K bytes */ - EBI_CS_ASIZE_8KB_gc = (0x05<<2), /* 8K bytes */ - EBI_CS_ASIZE_16KB_gc = (0x06<<2), /* 16K bytes */ - EBI_CS_ASIZE_32KB_gc = (0x07<<2), /* 32K bytes */ - EBI_CS_ASIZE_64KB_gc = (0x08<<2), /* 64K bytes */ - EBI_CS_ASIZE_128KB_gc = (0x09<<2), /* 128K bytes */ - EBI_CS_ASIZE_256KB_gc = (0x0A<<2), /* 256K bytes */ - EBI_CS_ASIZE_512KB_gc = (0x0B<<2), /* 512K bytes */ - EBI_CS_ASIZE_1MB_gc = (0x0C<<2), /* 1M bytes */ - EBI_CS_ASIZE_2MB_gc = (0x0D<<2), /* 2M bytes */ - EBI_CS_ASIZE_4MB_gc = (0x0E<<2), /* 4M bytes */ - EBI_CS_ASIZE_8MB_gc = (0x0F<<2), /* 8M bytes */ - EBI_CS_ASIZE_16M_gc = (0x10<<2), /* 16M bytes */ -} EBI_CS_ASIZE_t; - -/* */ -typedef enum EBI_CS_SRWS_enum -{ - EBI_CS_SRWS_0CLK_gc = (0x00<<0), /* 0 cycles */ - EBI_CS_SRWS_1CLK_gc = (0x01<<0), /* 1 cycle */ - EBI_CS_SRWS_2CLK_gc = (0x02<<0), /* 2 cycles */ - EBI_CS_SRWS_3CLK_gc = (0x03<<0), /* 3 cycles */ - EBI_CS_SRWS_4CLK_gc = (0x04<<0), /* 4 cycles */ - EBI_CS_SRWS_5CLK_gc = (0x05<<0), /* 5 cycle */ - EBI_CS_SRWS_6CLK_gc = (0x06<<0), /* 6 cycles */ - EBI_CS_SRWS_7CLK_gc = (0x07<<0), /* 7 cycles */ -} EBI_CS_SRWS_t; - -/* Chip Select address mode */ -typedef enum EBI_CS_MODE_enum -{ - EBI_CS_MODE_DISABLED_gc = (0x00<<0), /* Chip Select Disabled */ - EBI_CS_MODE_SRAM_gc = (0x01<<0), /* Chip Select in SRAM mode */ - EBI_CS_MODE_LPC_gc = (0x02<<0), /* Chip Select in SRAM LPC mode */ - EBI_CS_MODE_SDRAM_gc = (0x03<<0), /* Chip Select in SDRAM mode */ -} EBI_CS_MODE_t; - -/* Chip Select SDRAM mode */ -typedef enum EBI_CS_SDMODE_enum -{ - EBI_CS_SDMODE_NORMAL_gc = (0x00<<0), /* Normal mode */ - EBI_CS_SDMODE_LOAD_gc = (0x01<<0), /* Load Mode Register command mode */ -} EBI_CS_SDMODE_t; - -/* */ -typedef enum EBI_SDDATAW_enum -{ - EBI_SDDATAW_4BIT_gc = (0x00<<6), /* 4-bit data bus */ - EBI_SDDATAW_8BIT_gc = (0x01<<6), /* 8-bit data bus */ -} EBI_SDDATAW_t; - -/* */ -typedef enum EBI_LPCMODE_enum -{ - EBI_LPCMODE_ALE1_gc = (0x00<<4), /* Data muxed with addr byte 0 */ - EBI_LPCMODE_ALE12_gc = (0x02<<4), /* Data muxed with addr byte 0 and 1 */ -} EBI_LPCMODE_t; - -/* */ -typedef enum EBI_SRMODE_enum -{ - EBI_SRMODE_ALE1_gc = (0x00<<2), /* Addr byte 0 muxed with 1 */ - EBI_SRMODE_ALE2_gc = (0x01<<2), /* Addr byte 0 muxed with 2 */ - EBI_SRMODE_ALE12_gc = (0x02<<2), /* Addr byte 0 muxed with 1 and 2 */ - EBI_SRMODE_NOALE_gc = (0x03<<2), /* No addr muxing */ -} EBI_SRMODE_t; - -/* */ -typedef enum EBI_IFMODE_enum -{ - EBI_IFMODE_DISABLED_gc = (0x00<<0), /* EBI Disabled */ - EBI_IFMODE_3PORT_gc = (0x01<<0), /* 3-port mode */ - EBI_IFMODE_4PORT_gc = (0x02<<0), /* 4-port mode */ - EBI_IFMODE_2PORT_gc = (0x03<<0), /* 2-port mode */ -} EBI_IFMODE_t; - -/* */ -typedef enum EBI_SDCOL_enum -{ - EBI_SDCOL_8BIT_gc = (0x00<<0), /* 8 column bits */ - EBI_SDCOL_9BIT_gc = (0x01<<0), /* 9 column bits */ - EBI_SDCOL_10BIT_gc = (0x02<<0), /* 10 column bits */ - EBI_SDCOL_11BIT_gc = (0x03<<0), /* 11 column bits */ -} EBI_SDCOL_t; - -/* */ -typedef enum EBI_MRDLY_enum -{ - EBI_MRDLY_0CLK_gc = (0x00<<6), /* 0 cycles */ - EBI_MRDLY_1CLK_gc = (0x01<<6), /* 1 cycle */ - EBI_MRDLY_2CLK_gc = (0x02<<6), /* 2 cycles */ - EBI_MRDLY_3CLK_gc = (0x03<<6), /* 3 cycles */ -} EBI_MRDLY_t; - -/* */ -typedef enum EBI_ROWCYCDLY_enum -{ - EBI_ROWCYCDLY_0CLK_gc = (0x00<<3), /* 0 cycles */ - EBI_ROWCYCDLY_1CLK_gc = (0x01<<3), /* 1 cycle */ - EBI_ROWCYCDLY_2CLK_gc = (0x02<<3), /* 2 cycles */ - EBI_ROWCYCDLY_3CLK_gc = (0x03<<3), /* 3 cycles */ - EBI_ROWCYCDLY_4CLK_gc = (0x04<<3), /* 4 cycles */ - EBI_ROWCYCDLY_5CLK_gc = (0x05<<3), /* 5 cycle */ - EBI_ROWCYCDLY_6CLK_gc = (0x06<<3), /* 6 cycles */ - EBI_ROWCYCDLY_7CLK_gc = (0x07<<3), /* 7 cycles */ -} EBI_ROWCYCDLY_t; - -/* */ -typedef enum EBI_RPDLY_enum -{ - EBI_RPDLY_0CLK_gc = (0x00<<0), /* 0 cycles */ - EBI_RPDLY_1CLK_gc = (0x01<<0), /* 1 cycle */ - EBI_RPDLY_2CLK_gc = (0x02<<0), /* 2 cycles */ - EBI_RPDLY_3CLK_gc = (0x03<<0), /* 3 cycles */ - EBI_RPDLY_4CLK_gc = (0x04<<0), /* 4 cycles */ - EBI_RPDLY_5CLK_gc = (0x05<<0), /* 5 cycle */ - EBI_RPDLY_6CLK_gc = (0x06<<0), /* 6 cycles */ - EBI_RPDLY_7CLK_gc = (0x07<<0), /* 7 cycles */ -} EBI_RPDLY_t; - -/* */ -typedef enum EBI_WRDLY_enum -{ - EBI_WRDLY_0CLK_gc = (0x00<<6), /* 0 cycles */ - EBI_WRDLY_1CLK_gc = (0x01<<6), /* 1 cycle */ - EBI_WRDLY_2CLK_gc = (0x02<<6), /* 2 cycles */ - EBI_WRDLY_3CLK_gc = (0x03<<6), /* 3 cycles */ -} EBI_WRDLY_t; - -/* */ -typedef enum EBI_ESRDLY_enum -{ - EBI_ESRDLY_0CLK_gc = (0x00<<3), /* 0 cycles */ - EBI_ESRDLY_1CLK_gc = (0x01<<3), /* 1 cycle */ - EBI_ESRDLY_2CLK_gc = (0x02<<3), /* 2 cycles */ - EBI_ESRDLY_3CLK_gc = (0x03<<3), /* 3 cycles */ - EBI_ESRDLY_4CLK_gc = (0x04<<3), /* 4 cycles */ - EBI_ESRDLY_5CLK_gc = (0x05<<3), /* 5 cycle */ - EBI_ESRDLY_6CLK_gc = (0x06<<3), /* 6 cycles */ - EBI_ESRDLY_7CLK_gc = (0x07<<3), /* 7 cycles */ -} EBI_ESRDLY_t; - -/* */ -typedef enum EBI_ROWCOLDLY_enum -{ - EBI_ROWCOLDLY_0CLK_gc = (0x00<<0), /* 0 cycles */ - EBI_ROWCOLDLY_1CLK_gc = (0x01<<0), /* 1 cycle */ - EBI_ROWCOLDLY_2CLK_gc = (0x02<<0), /* 2 cycles */ - EBI_ROWCOLDLY_3CLK_gc = (0x03<<0), /* 3 cycles */ - EBI_ROWCOLDLY_4CLK_gc = (0x04<<0), /* 4 cycles */ - EBI_ROWCOLDLY_5CLK_gc = (0x05<<0), /* 5 cycle */ - EBI_ROWCOLDLY_6CLK_gc = (0x06<<0), /* 6 cycles */ - EBI_ROWCOLDLY_7CLK_gc = (0x07<<0), /* 7 cycles */ -} EBI_ROWCOLDLY_t; - - -/* --------------------------------------------------------------------------- -TWI - Two-Wire Interface --------------------------------------------------------------------------- -*/ - -/* */ -typedef struct TWI_MASTER_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t CTRLC; /* Control Register C */ - register8_t STATUS; /* Status Register */ - register8_t BAUD; /* Baurd Rate Control Register */ - register8_t ADDR; /* Address Register */ - register8_t DATA; /* Data Register */ -} TWI_MASTER_t; - -/* --------------------------------------------------------------------------- -TWI - Two-Wire Interface --------------------------------------------------------------------------- -*/ - -/* */ -typedef struct TWI_SLAVE_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t STATUS; /* Status Register */ - register8_t ADDR; /* Address Register */ - register8_t DATA; /* Data Register */ - register8_t ADDRMASK; /* Address Mask Register */ -} TWI_SLAVE_t; - -/* --------------------------------------------------------------------------- -TWI - Two-Wire Interface --------------------------------------------------------------------------- -*/ - -/* Two-Wire Interface */ -typedef struct TWI_struct -{ - register8_t CTRL; /* TWI Common Control Register */ - TWI_MASTER_t MASTER; /* TWI master module */ - TWI_SLAVE_t SLAVE; /* TWI slave module */ -} TWI_t; - -/* Master Interrupt Level */ -typedef enum TWI_MASTER_INTLVL_enum -{ - TWI_MASTER_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ - TWI_MASTER_INTLVL_LO_gc = (0x01<<6), /* Low Level */ - TWI_MASTER_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ - TWI_MASTER_INTLVL_HI_gc = (0x03<<6), /* High Level */ -} TWI_MASTER_INTLVL_t; - -/* Inactive Timeout */ -typedef enum TWI_MASTER_TIMEOUT_enum -{ - TWI_MASTER_TIMEOUT_DISABLED_gc = (0x00<<2), /* Bus Timeout Disabled */ - TWI_MASTER_TIMEOUT_50US_gc = (0x01<<2), /* 50 Microseconds */ - TWI_MASTER_TIMEOUT_100US_gc = (0x02<<2), /* 100 Microseconds */ - TWI_MASTER_TIMEOUT_200US_gc = (0x03<<2), /* 200 Microseconds */ -} TWI_MASTER_TIMEOUT_t; - -/* Master Command */ -typedef enum TWI_MASTER_CMD_enum -{ - TWI_MASTER_CMD_NOACT_gc = (0x00<<0), /* No Action */ - TWI_MASTER_CMD_REPSTART_gc = (0x01<<0), /* Issue Repeated Start Condition */ - TWI_MASTER_CMD_RECVTRANS_gc = (0x02<<0), /* Receive or Transmit Data */ - TWI_MASTER_CMD_STOP_gc = (0x03<<0), /* Issue Stop Condition */ -} TWI_MASTER_CMD_t; - -/* Master Bus State */ -typedef enum TWI_MASTER_BUSSTATE_enum -{ - TWI_MASTER_BUSSTATE_UNKNOWN_gc = (0x00<<0), /* Unknown Bus State */ - TWI_MASTER_BUSSTATE_IDLE_gc = (0x01<<0), /* Bus is Idle */ - TWI_MASTER_BUSSTATE_OWNER_gc = (0x02<<0), /* This Module Controls The Bus */ - TWI_MASTER_BUSSTATE_BUSY_gc = (0x03<<0), /* The Bus is Busy */ -} TWI_MASTER_BUSSTATE_t; - -/* Slave Interrupt Level */ -typedef enum TWI_SLAVE_INTLVL_enum -{ - TWI_SLAVE_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ - TWI_SLAVE_INTLVL_LO_gc = (0x01<<6), /* Low Level */ - TWI_SLAVE_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ - TWI_SLAVE_INTLVL_HI_gc = (0x03<<6), /* High Level */ -} TWI_SLAVE_INTLVL_t; - -/* Slave Command */ -typedef enum TWI_SLAVE_CMD_enum -{ - TWI_SLAVE_CMD_NOACT_gc = (0x00<<0), /* No Action */ - TWI_SLAVE_CMD_COMPTRANS_gc = (0x02<<0), /* Used To Complete a Transaction */ - TWI_SLAVE_CMD_RESPONSE_gc = (0x03<<0), /* Used in Response to Address/Data Interrupt */ -} TWI_SLAVE_CMD_t; - - -/* --------------------------------------------------------------------------- -PORT - Port Configuration --------------------------------------------------------------------------- -*/ - -/* I/O port Configuration */ -typedef struct PORTCFG_struct -{ - register8_t MPCMASK; /* Multi-pin Configuration Mask */ - register8_t reserved_0x01; - register8_t VPCTRLA; /* Virtual Port Control Register A */ - register8_t VPCTRLB; /* Virtual Port Control Register B */ - register8_t CLKEVOUT; /* Clock and Event Out Register */ -} PORTCFG_t; - -/* --------------------------------------------------------------------------- -PORT - Port Configuration --------------------------------------------------------------------------- -*/ - -/* Virtual Port */ -typedef struct VPORT_struct -{ - register8_t DIR; /* I/O Port Data Direction */ - register8_t OUT; /* I/O Port Output */ - register8_t IN; /* I/O Port Input */ - register8_t INTFLAGS; /* Interrupt Flag Register */ -} VPORT_t; - -/* --------------------------------------------------------------------------- -PORT - Port Configuration --------------------------------------------------------------------------- -*/ - -/* I/O Ports */ -typedef struct PORT_struct -{ - register8_t DIR; /* I/O Port Data Direction */ - register8_t DIRSET; /* I/O Port Data Direction Set */ - register8_t DIRCLR; /* I/O Port Data Direction Clear */ - register8_t DIRTGL; /* I/O Port Data Direction Toggle */ - register8_t OUT; /* I/O Port Output */ - register8_t OUTSET; /* I/O Port Output Set */ - register8_t OUTCLR; /* I/O Port Output Clear */ - register8_t OUTTGL; /* I/O Port Output Toggle */ - register8_t IN; /* I/O port Input */ - register8_t INTCTRL; /* Interrupt Control Register */ - register8_t INT0MASK; /* Port Interrupt 0 Mask */ - register8_t INT1MASK; /* Port Interrupt 1 Mask */ - register8_t INTFLAGS; /* Interrupt Flag Register */ - register8_t reserved_0x0D; - register8_t reserved_0x0E; - register8_t reserved_0x0F; - register8_t PIN0CTRL; /* Pin 0 Control Register */ - register8_t PIN1CTRL; /* Pin 1 Control Register */ - register8_t PIN2CTRL; /* Pin 2 Control Register */ - register8_t PIN3CTRL; /* Pin 3 Control Register */ - register8_t PIN4CTRL; /* Pin 4 Control Register */ - register8_t PIN5CTRL; /* Pin 5 Control Register */ - register8_t PIN6CTRL; /* Pin 6 Control Register */ - register8_t PIN7CTRL; /* Pin 7 Control Register */ -} PORT_t; - -/* Virtual Port 0 Mapping */ -typedef enum PORTCFG_VP0MAP_enum -{ - PORTCFG_VP0MAP_PORTA_gc = (0x00<<0), /* Mapped To PORTA */ - PORTCFG_VP0MAP_PORTB_gc = (0x01<<0), /* Mapped To PORTB */ - PORTCFG_VP0MAP_PORTC_gc = (0x02<<0), /* Mapped To PORTC */ - PORTCFG_VP0MAP_PORTD_gc = (0x03<<0), /* Mapped To PORTD */ - PORTCFG_VP0MAP_PORTE_gc = (0x04<<0), /* Mapped To PORTE */ - PORTCFG_VP0MAP_PORTF_gc = (0x05<<0), /* Mapped To PORTF */ - PORTCFG_VP0MAP_PORTG_gc = (0x06<<0), /* Mapped To PORTG */ - PORTCFG_VP0MAP_PORTH_gc = (0x07<<0), /* Mapped To PORTH */ - PORTCFG_VP0MAP_PORTJ_gc = (0x08<<0), /* Mapped To PORTJ */ - PORTCFG_VP0MAP_PORTK_gc = (0x09<<0), /* Mapped To PORTK */ - PORTCFG_VP0MAP_PORTL_gc = (0x0A<<0), /* Mapped To PORTL */ - PORTCFG_VP0MAP_PORTM_gc = (0x0B<<0), /* Mapped To PORTM */ - PORTCFG_VP0MAP_PORTN_gc = (0x0C<<0), /* Mapped To PORTN */ - PORTCFG_VP0MAP_PORTP_gc = (0x0D<<0), /* Mapped To PORTP */ - PORTCFG_VP0MAP_PORTQ_gc = (0x0E<<0), /* Mapped To PORTQ */ - PORTCFG_VP0MAP_PORTR_gc = (0x0F<<0), /* Mapped To PORTR */ -} PORTCFG_VP0MAP_t; - -/* Virtual Port 1 Mapping */ -typedef enum PORTCFG_VP1MAP_enum -{ - PORTCFG_VP1MAP_PORTA_gc = (0x00<<4), /* Mapped To PORTA */ - PORTCFG_VP1MAP_PORTB_gc = (0x01<<4), /* Mapped To PORTB */ - PORTCFG_VP1MAP_PORTC_gc = (0x02<<4), /* Mapped To PORTC */ - PORTCFG_VP1MAP_PORTD_gc = (0x03<<4), /* Mapped To PORTD */ - PORTCFG_VP1MAP_PORTE_gc = (0x04<<4), /* Mapped To PORTE */ - PORTCFG_VP1MAP_PORTF_gc = (0x05<<4), /* Mapped To PORTF */ - PORTCFG_VP1MAP_PORTG_gc = (0x06<<4), /* Mapped To PORTG */ - PORTCFG_VP1MAP_PORTH_gc = (0x07<<4), /* Mapped To PORTH */ - PORTCFG_VP1MAP_PORTJ_gc = (0x08<<4), /* Mapped To PORTJ */ - PORTCFG_VP1MAP_PORTK_gc = (0x09<<4), /* Mapped To PORTK */ - PORTCFG_VP1MAP_PORTL_gc = (0x0A<<4), /* Mapped To PORTL */ - PORTCFG_VP1MAP_PORTM_gc = (0x0B<<4), /* Mapped To PORTM */ - PORTCFG_VP1MAP_PORTN_gc = (0x0C<<4), /* Mapped To PORTN */ - PORTCFG_VP1MAP_PORTP_gc = (0x0D<<4), /* Mapped To PORTP */ - PORTCFG_VP1MAP_PORTQ_gc = (0x0E<<4), /* Mapped To PORTQ */ - PORTCFG_VP1MAP_PORTR_gc = (0x0F<<4), /* Mapped To PORTR */ -} PORTCFG_VP1MAP_t; - -/* Virtual Port 2 Mapping */ -typedef enum PORTCFG_VP2MAP_enum -{ - PORTCFG_VP2MAP_PORTA_gc = (0x00<<0), /* Mapped To PORTA */ - PORTCFG_VP2MAP_PORTB_gc = (0x01<<0), /* Mapped To PORTB */ - PORTCFG_VP2MAP_PORTC_gc = (0x02<<0), /* Mapped To PORTC */ - PORTCFG_VP2MAP_PORTD_gc = (0x03<<0), /* Mapped To PORTD */ - PORTCFG_VP2MAP_PORTE_gc = (0x04<<0), /* Mapped To PORTE */ - PORTCFG_VP2MAP_PORTF_gc = (0x05<<0), /* Mapped To PORTF */ - PORTCFG_VP2MAP_PORTG_gc = (0x06<<0), /* Mapped To PORTG */ - PORTCFG_VP2MAP_PORTH_gc = (0x07<<0), /* Mapped To PORTH */ - PORTCFG_VP2MAP_PORTJ_gc = (0x08<<0), /* Mapped To PORTJ */ - PORTCFG_VP2MAP_PORTK_gc = (0x09<<0), /* Mapped To PORTK */ - PORTCFG_VP2MAP_PORTL_gc = (0x0A<<0), /* Mapped To PORTL */ - PORTCFG_VP2MAP_PORTM_gc = (0x0B<<0), /* Mapped To PORTM */ - PORTCFG_VP2MAP_PORTN_gc = (0x0C<<0), /* Mapped To PORTN */ - PORTCFG_VP2MAP_PORTP_gc = (0x0D<<0), /* Mapped To PORTP */ - PORTCFG_VP2MAP_PORTQ_gc = (0x0E<<0), /* Mapped To PORTQ */ - PORTCFG_VP2MAP_PORTR_gc = (0x0F<<0), /* Mapped To PORTR */ -} PORTCFG_VP2MAP_t; - -/* Virtual Port 3 Mapping */ -typedef enum PORTCFG_VP3MAP_enum -{ - PORTCFG_VP3MAP_PORTA_gc = (0x00<<4), /* Mapped To PORTA */ - PORTCFG_VP3MAP_PORTB_gc = (0x01<<4), /* Mapped To PORTB */ - PORTCFG_VP3MAP_PORTC_gc = (0x02<<4), /* Mapped To PORTC */ - PORTCFG_VP3MAP_PORTD_gc = (0x03<<4), /* Mapped To PORTD */ - PORTCFG_VP3MAP_PORTE_gc = (0x04<<4), /* Mapped To PORTE */ - PORTCFG_VP3MAP_PORTF_gc = (0x05<<4), /* Mapped To PORTF */ - PORTCFG_VP3MAP_PORTG_gc = (0x06<<4), /* Mapped To PORTG */ - PORTCFG_VP3MAP_PORTH_gc = (0x07<<4), /* Mapped To PORTH */ - PORTCFG_VP3MAP_PORTJ_gc = (0x08<<4), /* Mapped To PORTJ */ - PORTCFG_VP3MAP_PORTK_gc = (0x09<<4), /* Mapped To PORTK */ - PORTCFG_VP3MAP_PORTL_gc = (0x0A<<4), /* Mapped To PORTL */ - PORTCFG_VP3MAP_PORTM_gc = (0x0B<<4), /* Mapped To PORTM */ - PORTCFG_VP3MAP_PORTN_gc = (0x0C<<4), /* Mapped To PORTN */ - PORTCFG_VP3MAP_PORTP_gc = (0x0D<<4), /* Mapped To PORTP */ - PORTCFG_VP3MAP_PORTQ_gc = (0x0E<<4), /* Mapped To PORTQ */ - PORTCFG_VP3MAP_PORTR_gc = (0x0F<<4), /* Mapped To PORTR */ -} PORTCFG_VP3MAP_t; - -/* Clock Output Port */ -typedef enum PORTCFG_CLKOUT_enum -{ - PORTCFG_CLKOUT_OFF_gc = (0x00<<0), /* Clock Output Disabled */ - PORTCFG_CLKOUT_PC7_gc = (0x01<<0), /* Clock Output on Port C pin 7 */ - PORTCFG_CLKOUT_PD7_gc = (0x02<<0), /* Clock Output on Port D pin 7 */ - PORTCFG_CLKOUT_PE7_gc = (0x03<<0), /* Clock Output on Port E pin 7 */ -} PORTCFG_CLKOUT_t; - -/* Event Output Port */ -typedef enum PORTCFG_EVOUT_enum -{ - PORTCFG_EVOUT_OFF_gc = (0x00<<4), /* Event Output Disabled */ - PORTCFG_EVOUT_PC7_gc = (0x01<<4), /* Event Channel 7 Output on Port C pin 7 */ - PORTCFG_EVOUT_PD7_gc = (0x02<<4), /* Event Channel 7 Output on Port D pin 7 */ - PORTCFG_EVOUT_PE7_gc = (0x03<<4), /* Event Channel 7 Output on Port E pin 7 */ -} PORTCFG_EVOUT_t; - -/* Port Interrupt 0 Level */ -typedef enum PORT_INT0LVL_enum -{ - PORT_INT0LVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - PORT_INT0LVL_LO_gc = (0x01<<0), /* Low Level */ - PORT_INT0LVL_MED_gc = (0x02<<0), /* Medium Level */ - PORT_INT0LVL_HI_gc = (0x03<<0), /* High Level */ -} PORT_INT0LVL_t; - -/* Port Interrupt 1 Level */ -typedef enum PORT_INT1LVL_enum -{ - PORT_INT1LVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ - PORT_INT1LVL_LO_gc = (0x01<<2), /* Low Level */ - PORT_INT1LVL_MED_gc = (0x02<<2), /* Medium Level */ - PORT_INT1LVL_HI_gc = (0x03<<2), /* High Level */ -} PORT_INT1LVL_t; - -/* Output/Pull Configuration */ -typedef enum PORT_OPC_enum -{ - PORT_OPC_TOTEM_gc = (0x00<<3), /* Totempole */ - PORT_OPC_BUSKEEPER_gc = (0x01<<3), /* Totempole w/ Bus keeper on Input and Output */ - PORT_OPC_PULLDOWN_gc = (0x02<<3), /* Totempole w/ Pull-down on Input */ - PORT_OPC_PULLUP_gc = (0x03<<3), /* Totempole w/ Pull-up on Input */ - PORT_OPC_WIREDOR_gc = (0x04<<3), /* Wired OR */ - PORT_OPC_WIREDAND_gc = (0x05<<3), /* Wired AND */ - PORT_OPC_WIREDORPULL_gc = (0x06<<3), /* Wired OR w/ Pull-down */ - PORT_OPC_WIREDANDPULL_gc = (0x07<<3), /* Wired AND w/ Pull-up */ -} PORT_OPC_t; - -/* Input/Sense Configuration */ -typedef enum PORT_ISC_enum -{ - PORT_ISC_BOTHEDGES_gc = (0x00<<0), /* Sense Both Edges */ - PORT_ISC_RISING_gc = (0x01<<0), /* Sense Rising Edge */ - PORT_ISC_FALLING_gc = (0x02<<0), /* Sense Falling Edge */ - PORT_ISC_LEVEL_gc = (0x03<<0), /* Sense Level (Transparent For Events) */ - PORT_ISC_INPUT_DISABLE_gc = (0x07<<0), /* Disable Digital Input Buffer */ -} PORT_ISC_t; - - -/* --------------------------------------------------------------------------- -TC - 16-bit Timer/Counter With PWM --------------------------------------------------------------------------- -*/ - -/* 16-bit Timer/Counter 0 */ -typedef struct TC0_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t CTRLC; /* Control register C */ - register8_t CTRLD; /* Control Register D */ - register8_t CTRLE; /* Control Register E */ - register8_t reserved_0x05; - register8_t INTCTRLA; /* Interrupt Control Register A */ - register8_t INTCTRLB; /* Interrupt Control Register B */ - register8_t CTRLFCLR; /* Control Register F Clear */ - register8_t CTRLFSET; /* Control Register F Set */ - register8_t CTRLGCLR; /* Control Register G Clear */ - register8_t CTRLGSET; /* Control Register G Set */ - register8_t INTFLAGS; /* Interrupt Flag Register */ - register8_t reserved_0x0D; - register8_t reserved_0x0E; - register8_t TEMP; /* Temporary Register For 16-bit Access */ - register8_t reserved_0x10; - register8_t reserved_0x11; - register8_t reserved_0x12; - register8_t reserved_0x13; - register8_t reserved_0x14; - register8_t reserved_0x15; - register8_t reserved_0x16; - register8_t reserved_0x17; - register8_t reserved_0x18; - register8_t reserved_0x19; - register8_t reserved_0x1A; - register8_t reserved_0x1B; - register8_t reserved_0x1C; - register8_t reserved_0x1D; - register8_t reserved_0x1E; - register8_t reserved_0x1F; - _WORDREGISTER(CNT); /* Count */ - register8_t reserved_0x22; - register8_t reserved_0x23; - register8_t reserved_0x24; - register8_t reserved_0x25; - _WORDREGISTER(PER); /* Period */ - _WORDREGISTER(CCA); /* Compare or Capture A */ - _WORDREGISTER(CCB); /* Compare or Capture B */ - _WORDREGISTER(CCC); /* Compare or Capture C */ - _WORDREGISTER(CCD); /* Compare or Capture D */ - register8_t reserved_0x30; - register8_t reserved_0x31; - register8_t reserved_0x32; - register8_t reserved_0x33; - register8_t reserved_0x34; - register8_t reserved_0x35; - _WORDREGISTER(PERBUF); /* Period Buffer */ - _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ - _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ - _WORDREGISTER(CCCBUF); /* Compare Or Capture C Buffer */ - _WORDREGISTER(CCDBUF); /* Compare Or Capture D Buffer */ -} TC0_t; - -/* --------------------------------------------------------------------------- -TC - 16-bit Timer/Counter With PWM --------------------------------------------------------------------------- -*/ - -/* 16-bit Timer/Counter 1 */ -typedef struct TC1_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t CTRLC; /* Control register C */ - register8_t CTRLD; /* Control Register D */ - register8_t CTRLE; /* Control Register E */ - register8_t reserved_0x05; - register8_t INTCTRLA; /* Interrupt Control Register A */ - register8_t INTCTRLB; /* Interrupt Control Register B */ - register8_t CTRLFCLR; /* Control Register F Clear */ - register8_t CTRLFSET; /* Control Register F Set */ - register8_t CTRLGCLR; /* Control Register G Clear */ - register8_t CTRLGSET; /* Control Register G Set */ - register8_t INTFLAGS; /* Interrupt Flag Register */ - register8_t reserved_0x0D; - register8_t reserved_0x0E; - register8_t TEMP; /* Temporary Register For 16-bit Access */ - register8_t reserved_0x10; - register8_t reserved_0x11; - register8_t reserved_0x12; - register8_t reserved_0x13; - register8_t reserved_0x14; - register8_t reserved_0x15; - register8_t reserved_0x16; - register8_t reserved_0x17; - register8_t reserved_0x18; - register8_t reserved_0x19; - register8_t reserved_0x1A; - register8_t reserved_0x1B; - register8_t reserved_0x1C; - register8_t reserved_0x1D; - register8_t reserved_0x1E; - register8_t reserved_0x1F; - _WORDREGISTER(CNT); /* Count */ - register8_t reserved_0x22; - register8_t reserved_0x23; - register8_t reserved_0x24; - register8_t reserved_0x25; - _WORDREGISTER(PER); /* Period */ - _WORDREGISTER(CCA); /* Compare or Capture A */ - _WORDREGISTER(CCB); /* Compare or Capture B */ - register8_t reserved_0x2C; - register8_t reserved_0x2D; - register8_t reserved_0x2E; - register8_t reserved_0x2F; - register8_t reserved_0x30; - register8_t reserved_0x31; - register8_t reserved_0x32; - register8_t reserved_0x33; - register8_t reserved_0x34; - register8_t reserved_0x35; - _WORDREGISTER(PERBUF); /* Period Buffer */ - _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ - _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ -} TC1_t; - -/* --------------------------------------------------------------------------- -TC - 16-bit Timer/Counter With PWM --------------------------------------------------------------------------- -*/ - -/* Advanced Waveform Extension */ -typedef struct AWEX_struct -{ - register8_t CTRL; /* Control Register */ - register8_t reserved_0x01; - register8_t FDEMASK; /* Fault Detection Event Mask */ - register8_t FDCTRL; /* Fault Detection Control Register */ - register8_t STATUS; /* Status Register */ - register8_t reserved_0x05; - register8_t DTBOTH; /* Dead Time Both Sides */ - register8_t DTBOTHBUF; /* Dead Time Both Sides Buffer */ - register8_t DTLS; /* Dead Time Low Side */ - register8_t DTHS; /* Dead Time High Side */ - register8_t DTLSBUF; /* Dead Time Low Side Buffer */ - register8_t DTHSBUF; /* Dead Time High Side Buffer */ - register8_t OUTOVEN; /* Output Override Enable */ -} AWEX_t; - -/* --------------------------------------------------------------------------- -TC - 16-bit Timer/Counter With PWM --------------------------------------------------------------------------- -*/ - -/* High-Resolution Extension */ -typedef struct HIRES_struct -{ - register8_t CTRLA; /* Control Register A */ -} HIRES_t; - -/* Clock Selection */ -typedef enum TC_CLKSEL_enum -{ - TC_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */ - TC_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */ - TC_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */ - TC_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */ - TC_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */ - TC_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */ - TC_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */ - TC_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */ - TC_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */ - TC_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */ - TC_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */ - TC_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */ - TC_CLKSEL_EVCH4_gc = (0x0C<<0), /* Event Channel 4 */ - TC_CLKSEL_EVCH5_gc = (0x0D<<0), /* Event Channel 5 */ - TC_CLKSEL_EVCH6_gc = (0x0E<<0), /* Event Channel 6 */ - TC_CLKSEL_EVCH7_gc = (0x0F<<0), /* Event Channel 7 */ -} TC_CLKSEL_t; - -/* Waveform Generation Mode */ -typedef enum TC_WGMODE_enum -{ - TC_WGMODE_NORMAL_gc = (0x00<<0), /* Normal Mode */ - TC_WGMODE_FRQ_gc = (0x01<<0), /* Frequency Generation Mode */ - TC_WGMODE_SS_gc = (0x03<<0), /* Single Slope */ - TC_WGMODE_DS_T_gc = (0x05<<0), /* Dual Slope, Update on TOP */ - TC_WGMODE_DS_TB_gc = (0x06<<0), /* Dual Slope, Update on TOP and BOTTOM */ - TC_WGMODE_DS_B_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */ -} TC_WGMODE_t; - -/* Event Action */ -typedef enum TC_EVACT_enum -{ - TC_EVACT_OFF_gc = (0x00<<5), /* No Event Action */ - TC_EVACT_CAPT_gc = (0x01<<5), /* Input Capture */ - TC_EVACT_UPDOWN_gc = (0x02<<5), /* Externally Controlled Up/Down Count */ - TC_EVACT_QDEC_gc = (0x03<<5), /* Quadrature Decode */ - TC_EVACT_RESTART_gc = (0x04<<5), /* Restart */ - TC_EVACT_FRQ_gc = (0x05<<5), /* Frequency Capture */ - TC_EVACT_PW_gc = (0x06<<5), /* Pulse-width Capture */ -} TC_EVACT_t; - -/* Event Selection */ -typedef enum TC_EVSEL_enum -{ - TC_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ - TC_EVSEL_CH0_gc = (0x08<<0), /* Event Channel 0 */ - TC_EVSEL_CH1_gc = (0x09<<0), /* Event Channel 1 */ - TC_EVSEL_CH2_gc = (0x0A<<0), /* Event Channel 2 */ - TC_EVSEL_CH3_gc = (0x0B<<0), /* Event Channel 3 */ - TC_EVSEL_CH4_gc = (0x0C<<0), /* Event Channel 4 */ - TC_EVSEL_CH5_gc = (0x0D<<0), /* Event Channel 5 */ - TC_EVSEL_CH6_gc = (0x0E<<0), /* Event Channel 6 */ - TC_EVSEL_CH7_gc = (0x0F<<0), /* Event Channel 7 */ -} TC_EVSEL_t; - -/* Error Interrupt Level */ -typedef enum TC_ERRINTLVL_enum -{ - TC_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ - TC_ERRINTLVL_LO_gc = (0x01<<2), /* Low Level */ - TC_ERRINTLVL_MED_gc = (0x02<<2), /* Medium Level */ - TC_ERRINTLVL_HI_gc = (0x03<<2), /* High Level */ -} TC_ERRINTLVL_t; - -/* Overflow Interrupt Level */ -typedef enum TC_OVFINTLVL_enum -{ - TC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - TC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ - TC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ - TC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ -} TC_OVFINTLVL_t; - -/* Compare or Capture D Interrupt Level */ -typedef enum TC_CCDINTLVL_enum -{ - TC_CCDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ - TC_CCDINTLVL_LO_gc = (0x01<<6), /* Low Level */ - TC_CCDINTLVL_MED_gc = (0x02<<6), /* Medium Level */ - TC_CCDINTLVL_HI_gc = (0x03<<6), /* High Level */ -} TC_CCDINTLVL_t; - -/* Compare or Capture C Interrupt Level */ -typedef enum TC_CCCINTLVL_enum -{ - TC_CCCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ - TC_CCCINTLVL_LO_gc = (0x01<<4), /* Low Level */ - TC_CCCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ - TC_CCCINTLVL_HI_gc = (0x03<<4), /* High Level */ -} TC_CCCINTLVL_t; - -/* Compare or Capture B Interrupt Level */ -typedef enum TC_CCBINTLVL_enum -{ - TC_CCBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ - TC_CCBINTLVL_LO_gc = (0x01<<2), /* Low Level */ - TC_CCBINTLVL_MED_gc = (0x02<<2), /* Medium Level */ - TC_CCBINTLVL_HI_gc = (0x03<<2), /* High Level */ -} TC_CCBINTLVL_t; - -/* Compare or Capture A Interrupt Level */ -typedef enum TC_CCAINTLVL_enum -{ - TC_CCAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - TC_CCAINTLVL_LO_gc = (0x01<<0), /* Low Level */ - TC_CCAINTLVL_MED_gc = (0x02<<0), /* Medium Level */ - TC_CCAINTLVL_HI_gc = (0x03<<0), /* High Level */ -} TC_CCAINTLVL_t; - -/* Timer/Counter Command */ -typedef enum TC_CMD_enum -{ - TC_CMD_NONE_gc = (0x00<<2), /* No Command */ - TC_CMD_UPDATE_gc = (0x01<<2), /* Force Update */ - TC_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ - TC_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ -} TC_CMD_t; - -/* Fault Detect Action */ -typedef enum AWEX_FDACT_enum -{ - AWEX_FDACT_NONE_gc = (0x00<<0), /* No Fault Protection */ - AWEX_FDACT_CLEAROE_gc = (0x01<<0), /* Clear Output Enable Bits */ - AWEX_FDACT_CLEARDIR_gc = (0x03<<0), /* Clear I/O Port Direction Bits */ -} AWEX_FDACT_t; - -/* High Resolution Enable */ -typedef enum HIRES_HREN_enum -{ - HIRES_HREN_NONE_gc = (0x00<<0), /* No Fault Protection */ - HIRES_HREN_TC0_gc = (0x01<<0), /* Enable High Resolution on Timer/Counter 0 */ - HIRES_HREN_TC1_gc = (0x02<<0), /* Enable High Resolution on Timer/Counter 1 */ - HIRES_HREN_BOTH_gc = (0x03<<0), /* Enable High Resolution both Timer/Counters */ -} HIRES_HREN_t; - - -/* --------------------------------------------------------------------------- -USART - Universal Asynchronous Receiver-Transmitter --------------------------------------------------------------------------- -*/ - -/* Universal Synchronous/Asynchronous Receiver/Transmitter */ -typedef struct USART_struct -{ - register8_t DATA; /* Data Register */ - register8_t STATUS; /* Status Register */ - register8_t reserved_0x02; - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t CTRLC; /* Control Register C */ - register8_t BAUDCTRLA; /* Baud Rate Control Register A */ - register8_t BAUDCTRLB; /* Baud Rate Control Register B */ -} USART_t; - -/* Receive Complete Interrupt level */ -typedef enum USART_RXCINTLVL_enum -{ - USART_RXCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ - USART_RXCINTLVL_LO_gc = (0x01<<4), /* Low Level */ - USART_RXCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ - USART_RXCINTLVL_HI_gc = (0x03<<4), /* High Level */ -} USART_RXCINTLVL_t; - -/* Transmit Complete Interrupt level */ -typedef enum USART_TXCINTLVL_enum -{ - USART_TXCINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ - USART_TXCINTLVL_LO_gc = (0x01<<2), /* Low Level */ - USART_TXCINTLVL_MED_gc = (0x02<<2), /* Medium Level */ - USART_TXCINTLVL_HI_gc = (0x03<<2), /* High Level */ -} USART_TXCINTLVL_t; - -/* Data Register Empty Interrupt level */ -typedef enum USART_DREINTLVL_enum -{ - USART_DREINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - USART_DREINTLVL_LO_gc = (0x01<<0), /* Low Level */ - USART_DREINTLVL_MED_gc = (0x02<<0), /* Medium Level */ - USART_DREINTLVL_HI_gc = (0x03<<0), /* High Level */ -} USART_DREINTLVL_t; - -/* Character Size */ -typedef enum USART_CHSIZE_enum -{ - USART_CHSIZE_5BIT_gc = (0x00<<0), /* Character size: 5 bit */ - USART_CHSIZE_6BIT_gc = (0x01<<0), /* Character size: 6 bit */ - USART_CHSIZE_7BIT_gc = (0x02<<0), /* Character size: 7 bit */ - USART_CHSIZE_8BIT_gc = (0x03<<0), /* Character size: 8 bit */ - USART_CHSIZE_9BIT_gc = (0x07<<0), /* Character size: 9 bit */ -} USART_CHSIZE_t; - -/* Communication Mode */ -typedef enum USART_CMODE_enum -{ - USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6), /* Asynchronous Mode */ - USART_CMODE_SYNCHRONOUS_gc = (0x01<<6), /* Synchronous Mode */ - USART_CMODE_IRDA_gc = (0x02<<6), /* IrDA Mode */ - USART_CMODE_MSPI_gc = (0x03<<6), /* Master SPI Mode */ -} USART_CMODE_t; - -/* Parity Mode */ -typedef enum USART_PMODE_enum -{ - USART_PMODE_DISABLED_gc = (0x00<<4), /* No Parity */ - USART_PMODE_EVEN_gc = (0x02<<4), /* Even Parity */ - USART_PMODE_ODD_gc = (0x03<<4), /* Odd Parity */ -} USART_PMODE_t; - - -/* --------------------------------------------------------------------------- -SPI - Serial Peripheral Interface --------------------------------------------------------------------------- -*/ - -/* Serial Peripheral Interface */ -typedef struct SPI_struct -{ - register8_t CTRL; /* Control Register */ - register8_t INTCTRL; /* Interrupt Control Register */ - register8_t STATUS; /* Status Register */ - register8_t DATA; /* Data Register */ -} SPI_t; - -/* SPI Mode */ -typedef enum SPI_MODE_enum -{ - SPI_MODE_0_gc = (0x00<<2), /* SPI Mode 0 */ - SPI_MODE_1_gc = (0x01<<2), /* SPI Mode 1 */ - SPI_MODE_2_gc = (0x02<<2), /* SPI Mode 2 */ - SPI_MODE_3_gc = (0x03<<2), /* SPI Mode 3 */ -} SPI_MODE_t; - -/* Prescaler setting */ -typedef enum SPI_PRESCALER_enum -{ - SPI_PRESCALER_DIV4_gc = (0x00<<0), /* System Clock / 4 */ - SPI_PRESCALER_DIV16_gc = (0x01<<0), /* System Clock / 16 */ - SPI_PRESCALER_DIV64_gc = (0x02<<0), /* System Clock / 64 */ - SPI_PRESCALER_DIV128_gc = (0x03<<0), /* System Clock / 128 */ -} SPI_PRESCALER_t; - -/* Interrupt level */ -typedef enum SPI_INTLVL_enum -{ - SPI_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - SPI_INTLVL_LO_gc = (0x01<<0), /* Low Level */ - SPI_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ - SPI_INTLVL_HI_gc = (0x03<<0), /* High Level */ -} SPI_INTLVL_t; - - -/* --------------------------------------------------------------------------- -IRCOM - IR Communication Module --------------------------------------------------------------------------- -*/ - -/* IR Communication Module */ -typedef struct IRCOM_struct -{ - register8_t CTRL; /* Control Register */ - register8_t TXPLCTRL; /* IrDA Transmitter Pulse Length Control Register */ - register8_t RXPLCTRL; /* IrDA Receiver Pulse Length Control Register */ -} IRCOM_t; - -/* Event channel selection */ -typedef enum IRDA_EVSEL_enum -{ - IRDA_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ - IRDA_EVSEL_0_gc = (0x08<<0), /* Event Channel 0 */ - IRDA_EVSEL_1_gc = (0x09<<0), /* Event Channel 1 */ - IRDA_EVSEL_2_gc = (0x0A<<0), /* Event Channel 2 */ - IRDA_EVSEL_3_gc = (0x0B<<0), /* Event Channel 3 */ - IRDA_EVSEL_4_gc = (0x0C<<0), /* Event Channel 4 */ - IRDA_EVSEL_5_gc = (0x0D<<0), /* Event Channel 5 */ - IRDA_EVSEL_6_gc = (0x0E<<0), /* Event Channel 6 */ - IRDA_EVSEL_7_gc = (0x0F<<0), /* Event Channel 7 */ -} IRDA_EVSEL_t; - - -/* --------------------------------------------------------------------------- -AES - AES Module --------------------------------------------------------------------------- -*/ - -/* AES Module */ -typedef struct AES_struct -{ - register8_t CTRL; /* AES Control Register */ - register8_t STATUS; /* AES Status Register */ - register8_t STATE; /* AES State Register */ - register8_t KEY; /* AES Key Register */ - register8_t INTCTRL; /* AES Interrupt Control Register */ -} AES_t; - -/* Interrupt level */ -typedef enum AES_INTLVL_enum -{ - AES_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - AES_INTLVL_LO_gc = (0x01<<0), /* Low Level */ - AES_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ - AES_INTLVL_HI_gc = (0x03<<0), /* High Level */ -} AES_INTLVL_t; - - - -/* -========================================================================== -IO Module Instances. Mapped to memory. -========================================================================== -*/ - -#define VPORT0 (*(VPORT_t *) 0x0010) /* Virtual Port 0 */ -#define VPORT1 (*(VPORT_t *) 0x0014) /* Virtual Port 1 */ -#define VPORT2 (*(VPORT_t *) 0x0018) /* Virtual Port 2 */ -#define VPORT3 (*(VPORT_t *) 0x001C) /* Virtual Port 3 */ -#define OCD (*(OCD_t *) 0x002E) /* On-Chip Debug System */ -#define CLK (*(CLK_t *) 0x0040) /* Clock System */ -#define SLEEP (*(SLEEP_t *) 0x0048) /* Sleep Controller */ -#define OSC (*(OSC_t *) 0x0050) /* Oscillator Control */ -#define DFLLRC32M (*(DFLL_t *) 0x0060) /* DFLL for 32MHz RC Oscillator */ -#define DFLLRC2M (*(DFLL_t *) 0x0068) /* DFLL for 2MHz RC Oscillator */ -#define PR (*(PR_t *) 0x0070) /* Power Reduction */ -#define RST (*(RST_t *) 0x0078) /* Reset Controller */ -#define WDT (*(WDT_t *) 0x0080) /* Watch-Dog Timer */ -#define MCU (*(MCU_t *) 0x0090) /* MCU Control */ -#define PMIC (*(PMIC_t *) 0x00A0) /* Programmable Interrupt Controller */ -#define PORTCFG (*(PORTCFG_t *) 0x00B0) /* Port Configuration */ -#define AES (*(AES_t *) 0x00C0) /* AES Crypto Module */ -#define DMA (*(DMA_t *) 0x0100) /* DMA Controller */ -#define EVSYS (*(EVSYS_t *) 0x0180) /* Event System */ -#define NVM (*(NVM_t *) 0x01C0) /* Non Volatile Memory Controller */ -#define ADCA (*(ADC_t *) 0x0200) /* Analog to Digital Converter A */ -#define ADCB (*(ADC_t *) 0x0240) /* Analog to Digital Converter B */ -#define DACA (*(DAC_t *) 0x0300) /* Digital to Analog Converter A */ -#define DACB (*(DAC_t *) 0x0320) /* Digital to Analog Converter B */ -#define ACA (*(AC_t *) 0x0380) /* Analog Comparator A */ -#define ACB (*(AC_t *) 0x0390) /* Analog Comparator B */ -#define RTC (*(RTC_t *) 0x0400) /* Real-Time Counter */ -#define EBI (*(EBI_t *) 0x0440) /* External Bus Interface */ -#define TWIC (*(TWI_t *) 0x0480) /* Two-Wire Interface C */ -#define TWID (*(TWI_t *) 0x0490) /* Two-Wire Interface D */ -#define TWIE (*(TWI_t *) 0x04A0) /* Two-Wire Interface E */ -#define TWIF (*(TWI_t *) 0x04B0) /* Two-Wire Interface F */ -#define PORTA (*(PORT_t *) 0x0600) /* Port A */ -#define PORTB (*(PORT_t *) 0x0620) /* Port B */ -#define PORTC (*(PORT_t *) 0x0640) /* Port C */ -#define PORTD (*(PORT_t *) 0x0660) /* Port D */ -#define PORTE (*(PORT_t *) 0x0680) /* Port E */ -#define PORTF (*(PORT_t *) 0x06A0) /* Port F */ -#define PORTH (*(PORT_t *) 0x06E0) /* Port H */ -#define PORTJ (*(PORT_t *) 0x0700) /* Port J */ -#define PORTK (*(PORT_t *) 0x0720) /* Port K */ -#define PORTQ (*(PORT_t *) 0x07C0) /* Port Q */ -#define PORTR (*(PORT_t *) 0x07E0) /* Port R */ -#define TCC0 (*(TC0_t *) 0x0800) /* Timer/Counter C0 */ -#define TCC1 (*(TC1_t *) 0x0840) /* Timer/Counter C1 */ -#define AWEXC (*(AWEX_t *) 0x0880) /* Advanced Waveform Extension C */ -#define HIRESC (*(HIRES_t *) 0x0890) /* High-Resolution Extension C */ -#define USARTC0 (*(USART_t *) 0x08A0) /* Universal Asynchronous Receiver-Transmitter C0 */ -#define USARTC1 (*(USART_t *) 0x08B0) /* Universal Asynchronous Receiver-Transmitter C1 */ -#define SPIC (*(SPI_t *) 0x08C0) /* Serial Peripheral Interface C */ -#define IRCOM (*(IRCOM_t *) 0x08F8) /* IR Communication Module */ -#define TCD0 (*(TC0_t *) 0x0900) /* Timer/Counter D0 */ -#define TCD1 (*(TC1_t *) 0x0940) /* Timer/Counter D1 */ -#define HIRESD (*(HIRES_t *) 0x0990) /* High-Resolution Extension D */ -#define USARTD0 (*(USART_t *) 0x09A0) /* Universal Asynchronous Receiver-Transmitter D0 */ -#define USARTD1 (*(USART_t *) 0x09B0) /* Universal Asynchronous Receiver-Transmitter D1 */ -#define SPID (*(SPI_t *) 0x09C0) /* Serial Peripheral Interface D */ -#define TCE0 (*(TC0_t *) 0x0A00) /* Timer/Counter E0 */ -#define TCE1 (*(TC1_t *) 0x0A40) /* Timer/Counter E1 */ -#define AWEXE (*(AWEX_t *) 0x0A80) /* Advanced Waveform Extension E */ -#define HIRESE (*(HIRES_t *) 0x0A90) /* High-Resolution Extension E */ -#define USARTE0 (*(USART_t *) 0x0AA0) /* Universal Asynchronous Receiver-Transmitter E0 */ -#define USARTE1 (*(USART_t *) 0x0AB0) /* Universal Asynchronous Receiver-Transmitter E1 */ -#define SPIE (*(SPI_t *) 0x0AC0) /* Serial Peripheral Interface E */ -#define TCF0 (*(TC0_t *) 0x0B00) /* Timer/Counter F0 */ -#define TCF1 (*(TC1_t *) 0x0B40) /* Timer/Counter F1 */ -#define HIRESF (*(HIRES_t *) 0x0B90) /* High-Resolution Extension F */ -#define USARTF0 (*(USART_t *) 0x0BA0) /* Universal Asynchronous Receiver-Transmitter F0 */ -#define USARTF1 (*(USART_t *) 0x0BB0) /* Universal Asynchronous Receiver-Transmitter F1 */ -#define SPIF (*(SPI_t *) 0x0BC0) /* Serial Peripheral Interface F */ - - -#endif /* !defined (__ASSEMBLER__) */ - - -/* ========== Flattened fully qualified IO register names ========== */ - -/* GPIO - General Purpose IO Registers */ -#define GPIO_GPIOR0 _SFR_MEM8(0x0000) -#define GPIO_GPIOR1 _SFR_MEM8(0x0001) -#define GPIO_GPIOR2 _SFR_MEM8(0x0002) -#define GPIO_GPIOR3 _SFR_MEM8(0x0003) -#define GPIO_GPIOR4 _SFR_MEM8(0x0004) -#define GPIO_GPIOR5 _SFR_MEM8(0x0005) -#define GPIO_GPIOR6 _SFR_MEM8(0x0006) -#define GPIO_GPIOR7 _SFR_MEM8(0x0007) -#define GPIO_GPIOR8 _SFR_MEM8(0x0008) -#define GPIO_GPIOR9 _SFR_MEM8(0x0009) -#define GPIO_GPIORA _SFR_MEM8(0x000A) -#define GPIO_GPIORB _SFR_MEM8(0x000B) -#define GPIO_GPIORC _SFR_MEM8(0x000C) -#define GPIO_GPIORD _SFR_MEM8(0x000D) -#define GPIO_GPIORE _SFR_MEM8(0x000E) -#define GPIO_GPIORF _SFR_MEM8(0x000F) - -/* Deprecated */ -#define GPIO_GPIO0 _SFR_MEM8(0x0000) -#define GPIO_GPIO1 _SFR_MEM8(0x0001) -#define GPIO_GPIO2 _SFR_MEM8(0x0002) -#define GPIO_GPIO3 _SFR_MEM8(0x0003) -#define GPIO_GPIO4 _SFR_MEM8(0x0004) -#define GPIO_GPIO5 _SFR_MEM8(0x0005) -#define GPIO_GPIO6 _SFR_MEM8(0x0006) -#define GPIO_GPIO7 _SFR_MEM8(0x0007) -#define GPIO_GPIO8 _SFR_MEM8(0x0008) -#define GPIO_GPIO9 _SFR_MEM8(0x0009) -#define GPIO_GPIOA _SFR_MEM8(0x000A) -#define GPIO_GPIOB _SFR_MEM8(0x000B) -#define GPIO_GPIOC _SFR_MEM8(0x000C) -#define GPIO_GPIOD _SFR_MEM8(0x000D) -#define GPIO_GPIOE _SFR_MEM8(0x000E) -#define GPIO_GPIOF _SFR_MEM8(0x000F) - -/* VPORT0 - Virtual Port 0 */ -#define VPORT0_DIR _SFR_MEM8(0x0010) -#define VPORT0_OUT _SFR_MEM8(0x0011) -#define VPORT0_IN _SFR_MEM8(0x0012) -#define VPORT0_INTFLAGS _SFR_MEM8(0x0013) - -/* VPORT1 - Virtual Port 1 */ -#define VPORT1_DIR _SFR_MEM8(0x0014) -#define VPORT1_OUT _SFR_MEM8(0x0015) -#define VPORT1_IN _SFR_MEM8(0x0016) -#define VPORT1_INTFLAGS _SFR_MEM8(0x0017) - -/* VPORT2 - Virtual Port 2 */ -#define VPORT2_DIR _SFR_MEM8(0x0018) -#define VPORT2_OUT _SFR_MEM8(0x0019) -#define VPORT2_IN _SFR_MEM8(0x001A) -#define VPORT2_INTFLAGS _SFR_MEM8(0x001B) - -/* VPORT3 - Virtual Port 3 */ -#define VPORT3_DIR _SFR_MEM8(0x001C) -#define VPORT3_OUT _SFR_MEM8(0x001D) -#define VPORT3_IN _SFR_MEM8(0x001E) -#define VPORT3_INTFLAGS _SFR_MEM8(0x001F) - -/* OCD - On-Chip Debug System */ -#define OCD_OCDR0 _SFR_MEM8(0x002E) -#define OCD_OCDR1 _SFR_MEM8(0x002F) - -/* CPU - CPU Registers */ -#define CPU_CCP _SFR_MEM8(0x0034) -#define CPU_RAMPD _SFR_MEM8(0x0038) -#define CPU_RAMPX _SFR_MEM8(0x0039) -#define CPU_RAMPY _SFR_MEM8(0x003A) -#define CPU_RAMPZ _SFR_MEM8(0x003B) -#define CPU_EIND _SFR_MEM8(0x003C) -#define CPU_SPL _SFR_MEM8(0x003D) -#define CPU_SPH _SFR_MEM8(0x003E) -#define CPU_SREG _SFR_MEM8(0x003F) - -/* CLK - Clock System */ -#define CLK_CTRL _SFR_MEM8(0x0040) -#define CLK_PSCTRL _SFR_MEM8(0x0041) -#define CLK_LOCK _SFR_MEM8(0x0042) -#define CLK_RTCCTRL _SFR_MEM8(0x0043) - -/* SLEEP - Sleep Controller */ -#define SLEEP_CTRL _SFR_MEM8(0x0048) - -/* OSC - Oscillator Control */ -#define OSC_CTRL _SFR_MEM8(0x0050) -#define OSC_STATUS _SFR_MEM8(0x0051) -#define OSC_XOSCCTRL _SFR_MEM8(0x0052) -#define OSC_XOSCFAIL _SFR_MEM8(0x0053) -#define OSC_RC32KCAL _SFR_MEM8(0x0054) -#define OSC_PLLCTRL _SFR_MEM8(0x0055) -#define OSC_DFLLCTRL _SFR_MEM8(0x0056) - -/* DFLLRC32M - DFLL for 32MHz RC Oscillator */ -#define DFLLRC32M_CTRL _SFR_MEM8(0x0060) -#define DFLLRC32M_CALA _SFR_MEM8(0x0062) -#define DFLLRC32M_CALB _SFR_MEM8(0x0063) -#define DFLLRC32M_COMP0 _SFR_MEM8(0x0064) -#define DFLLRC32M_COMP1 _SFR_MEM8(0x0065) -#define DFLLRC32M_COMP2 _SFR_MEM8(0x0066) - -/* DFLLRC2M - DFLL for 2MHz RC Oscillator */ -#define DFLLRC2M_CTRL _SFR_MEM8(0x0068) -#define DFLLRC2M_CALA _SFR_MEM8(0x006A) -#define DFLLRC2M_CALB _SFR_MEM8(0x006B) -#define DFLLRC2M_COMP0 _SFR_MEM8(0x006C) -#define DFLLRC2M_COMP1 _SFR_MEM8(0x006D) -#define DFLLRC2M_COMP2 _SFR_MEM8(0x006E) - -/* PR - Power Reduction */ -#define PR_PRGEN _SFR_MEM8(0x0070) -#define PR_PRPA _SFR_MEM8(0x0071) -#define PR_PRPB _SFR_MEM8(0x0072) -#define PR_PRPC _SFR_MEM8(0x0073) -#define PR_PRPD _SFR_MEM8(0x0074) -#define PR_PRPE _SFR_MEM8(0x0075) -#define PR_PRPF _SFR_MEM8(0x0076) - -/* RST - Reset Controller */ -#define RST_STATUS _SFR_MEM8(0x0078) -#define RST_CTRL _SFR_MEM8(0x0079) - -/* WDT - Watch-Dog Timer */ -#define WDT_CTRL _SFR_MEM8(0x0080) -#define WDT_WINCTRL _SFR_MEM8(0x0081) -#define WDT_STATUS _SFR_MEM8(0x0082) - -/* MCU - MCU Control */ -#define MCU_DEVID0 _SFR_MEM8(0x0090) -#define MCU_DEVID1 _SFR_MEM8(0x0091) -#define MCU_DEVID2 _SFR_MEM8(0x0092) -#define MCU_REVID _SFR_MEM8(0x0093) -#define MCU_JTAGUID _SFR_MEM8(0x0094) -#define MCU_MCUCR _SFR_MEM8(0x0096) -#define MCU_EVSYSLOCK _SFR_MEM8(0x0098) -#define MCU_AWEXLOCK _SFR_MEM8(0x0099) - -/* PMIC - Programmable Interrupt Controller */ -#define PMIC_STATUS _SFR_MEM8(0x00A0) -#define PMIC_INTPRI _SFR_MEM8(0x00A1) -#define PMIC_CTRL _SFR_MEM8(0x00A2) - -/* PORTCFG - Port Configuration */ -#define PORTCFG_MPCMASK _SFR_MEM8(0x00B0) -#define PORTCFG_VPCTRLA _SFR_MEM8(0x00B2) -#define PORTCFG_VPCTRLB _SFR_MEM8(0x00B3) -#define PORTCFG_CLKEVOUT _SFR_MEM8(0x00B4) - -/* AES - AES Crypto Module */ -#define AES_CTRL _SFR_MEM8(0x00C0) -#define AES_STATUS _SFR_MEM8(0x00C1) -#define AES_STATE _SFR_MEM8(0x00C2) -#define AES_KEY _SFR_MEM8(0x00C3) -#define AES_INTCTRL _SFR_MEM8(0x00C4) - -/* DMA - DMA Controller */ -#define DMA_CTRL _SFR_MEM8(0x0100) -#define DMA_INTFLAGS _SFR_MEM8(0x0103) -#define DMA_STATUS _SFR_MEM8(0x0104) -#define DMA_TEMP _SFR_MEM16(0x0106) -#define DMA_CH0_CTRLA _SFR_MEM8(0x0110) -#define DMA_CH0_CTRLB _SFR_MEM8(0x0111) -#define DMA_CH0_ADDRCTRL _SFR_MEM8(0x0112) -#define DMA_CH0_TRIGSRC _SFR_MEM8(0x0113) -#define DMA_CH0_TRFCNT _SFR_MEM16(0x0114) -#define DMA_CH0_REPCNT _SFR_MEM8(0x0116) -#define DMA_CH0_SRCADDR0 _SFR_MEM8(0x0118) -#define DMA_CH0_SRCADDR1 _SFR_MEM8(0x0119) -#define DMA_CH0_SRCADDR2 _SFR_MEM8(0x011A) -#define DMA_CH0_DESTADDR0 _SFR_MEM8(0x011C) -#define DMA_CH0_DESTADDR1 _SFR_MEM8(0x011D) -#define DMA_CH0_DESTADDR2 _SFR_MEM8(0x011E) -#define DMA_CH1_CTRLA _SFR_MEM8(0x0120) -#define DMA_CH1_CTRLB _SFR_MEM8(0x0121) -#define DMA_CH1_ADDRCTRL _SFR_MEM8(0x0122) -#define DMA_CH1_TRIGSRC _SFR_MEM8(0x0123) -#define DMA_CH1_TRFCNT _SFR_MEM16(0x0124) -#define DMA_CH1_REPCNT _SFR_MEM8(0x0126) -#define DMA_CH1_SRCADDR0 _SFR_MEM8(0x0128) -#define DMA_CH1_SRCADDR1 _SFR_MEM8(0x0129) -#define DMA_CH1_SRCADDR2 _SFR_MEM8(0x012A) -#define DMA_CH1_DESTADDR0 _SFR_MEM8(0x012C) -#define DMA_CH1_DESTADDR1 _SFR_MEM8(0x012D) -#define DMA_CH1_DESTADDR2 _SFR_MEM8(0x012E) -#define DMA_CH2_CTRLA _SFR_MEM8(0x0130) -#define DMA_CH2_CTRLB _SFR_MEM8(0x0131) -#define DMA_CH2_ADDRCTRL _SFR_MEM8(0x0132) -#define DMA_CH2_TRIGSRC _SFR_MEM8(0x0133) -#define DMA_CH2_TRFCNT _SFR_MEM16(0x0134) -#define DMA_CH2_REPCNT _SFR_MEM8(0x0136) -#define DMA_CH2_SRCADDR0 _SFR_MEM8(0x0138) -#define DMA_CH2_SRCADDR1 _SFR_MEM8(0x0139) -#define DMA_CH2_SRCADDR2 _SFR_MEM8(0x013A) -#define DMA_CH2_DESTADDR0 _SFR_MEM8(0x013C) -#define DMA_CH2_DESTADDR1 _SFR_MEM8(0x013D) -#define DMA_CH2_DESTADDR2 _SFR_MEM8(0x013E) -#define DMA_CH3_CTRLA _SFR_MEM8(0x0140) -#define DMA_CH3_CTRLB _SFR_MEM8(0x0141) -#define DMA_CH3_ADDRCTRL _SFR_MEM8(0x0142) -#define DMA_CH3_TRIGSRC _SFR_MEM8(0x0143) -#define DMA_CH3_TRFCNT _SFR_MEM16(0x0144) -#define DMA_CH3_REPCNT _SFR_MEM8(0x0146) -#define DMA_CH3_SRCADDR0 _SFR_MEM8(0x0148) -#define DMA_CH3_SRCADDR1 _SFR_MEM8(0x0149) -#define DMA_CH3_SRCADDR2 _SFR_MEM8(0x014A) -#define DMA_CH3_DESTADDR0 _SFR_MEM8(0x014C) -#define DMA_CH3_DESTADDR1 _SFR_MEM8(0x014D) -#define DMA_CH3_DESTADDR2 _SFR_MEM8(0x014E) - -/* EVSYS - Event System */ -#define EVSYS_CH0MUX _SFR_MEM8(0x0180) -#define EVSYS_CH1MUX _SFR_MEM8(0x0181) -#define EVSYS_CH2MUX _SFR_MEM8(0x0182) -#define EVSYS_CH3MUX _SFR_MEM8(0x0183) -#define EVSYS_CH4MUX _SFR_MEM8(0x0184) -#define EVSYS_CH5MUX _SFR_MEM8(0x0185) -#define EVSYS_CH6MUX _SFR_MEM8(0x0186) -#define EVSYS_CH7MUX _SFR_MEM8(0x0187) -#define EVSYS_CH0CTRL _SFR_MEM8(0x0188) -#define EVSYS_CH1CTRL _SFR_MEM8(0x0189) -#define EVSYS_CH2CTRL _SFR_MEM8(0x018A) -#define EVSYS_CH3CTRL _SFR_MEM8(0x018B) -#define EVSYS_CH4CTRL _SFR_MEM8(0x018C) -#define EVSYS_CH5CTRL _SFR_MEM8(0x018D) -#define EVSYS_CH6CTRL _SFR_MEM8(0x018E) -#define EVSYS_CH7CTRL _SFR_MEM8(0x018F) -#define EVSYS_STROBE _SFR_MEM8(0x0190) -#define EVSYS_DATA _SFR_MEM8(0x0191) - -/* NVM - Non Volatile Memory Controller */ -#define NVM_ADDR0 _SFR_MEM8(0x01C0) -#define NVM_ADDR1 _SFR_MEM8(0x01C1) -#define NVM_ADDR2 _SFR_MEM8(0x01C2) -#define NVM_DATA0 _SFR_MEM8(0x01C4) -#define NVM_DATA1 _SFR_MEM8(0x01C5) -#define NVM_DATA2 _SFR_MEM8(0x01C6) -#define NVM_CMD _SFR_MEM8(0x01CA) -#define NVM_CTRLA _SFR_MEM8(0x01CB) -#define NVM_CTRLB _SFR_MEM8(0x01CC) -#define NVM_INTCTRL _SFR_MEM8(0x01CD) -#define NVM_STATUS _SFR_MEM8(0x01CF) -#define NVM_LOCKBITS _SFR_MEM8(0x01D0) - -/* ADCA - Analog to Digital Converter A */ -#define ADCA_CTRLA _SFR_MEM8(0x0200) -#define ADCA_CTRLB _SFR_MEM8(0x0201) -#define ADCA_REFCTRL _SFR_MEM8(0x0202) -#define ADCA_EVCTRL _SFR_MEM8(0x0203) -#define ADCA_PRESCALER _SFR_MEM8(0x0204) -#define ADCA_INTFLAGS _SFR_MEM8(0x0206) -#define ADCA_CAL _SFR_MEM16(0x020C) -#define ADCA_CH0RES _SFR_MEM16(0x0210) -#define ADCA_CH1RES _SFR_MEM16(0x0212) -#define ADCA_CH2RES _SFR_MEM16(0x0214) -#define ADCA_CH3RES _SFR_MEM16(0x0216) -#define ADCA_CMP _SFR_MEM16(0x0218) -#define ADCA_CH0_CTRL _SFR_MEM8(0x0220) -#define ADCA_CH0_MUXCTRL _SFR_MEM8(0x0221) -#define ADCA_CH0_INTCTRL _SFR_MEM8(0x0222) -#define ADCA_CH0_INTFLAGS _SFR_MEM8(0x0223) -#define ADCA_CH0_RES _SFR_MEM16(0x0224) -#define ADCA_CH1_CTRL _SFR_MEM8(0x0228) -#define ADCA_CH1_MUXCTRL _SFR_MEM8(0x0229) -#define ADCA_CH1_INTCTRL _SFR_MEM8(0x022A) -#define ADCA_CH1_INTFLAGS _SFR_MEM8(0x022B) -#define ADCA_CH1_RES _SFR_MEM16(0x022C) -#define ADCA_CH2_CTRL _SFR_MEM8(0x0230) -#define ADCA_CH2_MUXCTRL _SFR_MEM8(0x0231) -#define ADCA_CH2_INTCTRL _SFR_MEM8(0x0232) -#define ADCA_CH2_INTFLAGS _SFR_MEM8(0x0233) -#define ADCA_CH2_RES _SFR_MEM16(0x0234) -#define ADCA_CH3_CTRL _SFR_MEM8(0x0238) -#define ADCA_CH3_MUXCTRL _SFR_MEM8(0x0239) -#define ADCA_CH3_INTCTRL _SFR_MEM8(0x023A) -#define ADCA_CH3_INTFLAGS _SFR_MEM8(0x023B) -#define ADCA_CH3_RES _SFR_MEM16(0x023C) - -/* ADCB - Analog to Digital Converter B */ -#define ADCB_CTRLA _SFR_MEM8(0x0240) -#define ADCB_CTRLB _SFR_MEM8(0x0241) -#define ADCB_REFCTRL _SFR_MEM8(0x0242) -#define ADCB_EVCTRL _SFR_MEM8(0x0243) -#define ADCB_PRESCALER _SFR_MEM8(0x0244) -#define ADCB_INTFLAGS _SFR_MEM8(0x0246) -#define ADCB_CAL _SFR_MEM16(0x024C) -#define ADCB_CH0RES _SFR_MEM16(0x0250) -#define ADCB_CH1RES _SFR_MEM16(0x0252) -#define ADCB_CH2RES _SFR_MEM16(0x0254) -#define ADCB_CH3RES _SFR_MEM16(0x0256) -#define ADCB_CMP _SFR_MEM16(0x0258) -#define ADCB_CH0_CTRL _SFR_MEM8(0x0260) -#define ADCB_CH0_MUXCTRL _SFR_MEM8(0x0261) -#define ADCB_CH0_INTCTRL _SFR_MEM8(0x0262) -#define ADCB_CH0_INTFLAGS _SFR_MEM8(0x0263) -#define ADCB_CH0_RES _SFR_MEM16(0x0264) -#define ADCB_CH1_CTRL _SFR_MEM8(0x0268) -#define ADCB_CH1_MUXCTRL _SFR_MEM8(0x0269) -#define ADCB_CH1_INTCTRL _SFR_MEM8(0x026A) -#define ADCB_CH1_INTFLAGS _SFR_MEM8(0x026B) -#define ADCB_CH1_RES _SFR_MEM16(0x026C) -#define ADCB_CH2_CTRL _SFR_MEM8(0x0270) -#define ADCB_CH2_MUXCTRL _SFR_MEM8(0x0271) -#define ADCB_CH2_INTCTRL _SFR_MEM8(0x0272) -#define ADCB_CH2_INTFLAGS _SFR_MEM8(0x0273) -#define ADCB_CH2_RES _SFR_MEM16(0x0274) -#define ADCB_CH3_CTRL _SFR_MEM8(0x0278) -#define ADCB_CH3_MUXCTRL _SFR_MEM8(0x0279) -#define ADCB_CH3_INTCTRL _SFR_MEM8(0x027A) -#define ADCB_CH3_INTFLAGS _SFR_MEM8(0x027B) -#define ADCB_CH3_RES _SFR_MEM16(0x027C) - -/* DACA - Digital to Analog Converter A */ -#define DACA_CTRLA _SFR_MEM8(0x0300) -#define DACA_CTRLB _SFR_MEM8(0x0301) -#define DACA_CTRLC _SFR_MEM8(0x0302) -#define DACA_EVCTRL _SFR_MEM8(0x0303) -#define DACA_TIMCTRL _SFR_MEM8(0x0304) -#define DACA_STATUS _SFR_MEM8(0x0305) -#define DACA_GAINCAL _SFR_MEM8(0x0308) -#define DACA_OFFSETCAL _SFR_MEM8(0x0309) -#define DACA_CH0DATA _SFR_MEM16(0x0318) -#define DACA_CH1DATA _SFR_MEM16(0x031A) - -/* DACB - Digital to Analog Converter B */ -#define DACB_CTRLA _SFR_MEM8(0x0320) -#define DACB_CTRLB _SFR_MEM8(0x0321) -#define DACB_CTRLC _SFR_MEM8(0x0322) -#define DACB_EVCTRL _SFR_MEM8(0x0323) -#define DACB_TIMCTRL _SFR_MEM8(0x0324) -#define DACB_STATUS _SFR_MEM8(0x0325) -#define DACB_GAINCAL _SFR_MEM8(0x0328) -#define DACB_OFFSETCAL _SFR_MEM8(0x0329) -#define DACB_CH0DATA _SFR_MEM16(0x0338) -#define DACB_CH1DATA _SFR_MEM16(0x033A) - -/* ACA - Analog Comparator A */ -#define ACA_AC0CTRL _SFR_MEM8(0x0380) -#define ACA_AC1CTRL _SFR_MEM8(0x0381) -#define ACA_AC0MUXCTRL _SFR_MEM8(0x0382) -#define ACA_AC1MUXCTRL _SFR_MEM8(0x0383) -#define ACA_CTRLA _SFR_MEM8(0x0384) -#define ACA_CTRLB _SFR_MEM8(0x0385) -#define ACA_WINCTRL _SFR_MEM8(0x0386) -#define ACA_STATUS _SFR_MEM8(0x0387) - -/* ACB - Analog Comparator B */ -#define ACB_AC0CTRL _SFR_MEM8(0x0390) -#define ACB_AC1CTRL _SFR_MEM8(0x0391) -#define ACB_AC0MUXCTRL _SFR_MEM8(0x0392) -#define ACB_AC1MUXCTRL _SFR_MEM8(0x0393) -#define ACB_CTRLA _SFR_MEM8(0x0394) -#define ACB_CTRLB _SFR_MEM8(0x0395) -#define ACB_WINCTRL _SFR_MEM8(0x0396) -#define ACB_STATUS _SFR_MEM8(0x0397) - -/* RTC - Real-Time Counter */ -#define RTC_CTRL _SFR_MEM8(0x0400) -#define RTC_STATUS _SFR_MEM8(0x0401) -#define RTC_INTCTRL _SFR_MEM8(0x0402) -#define RTC_INTFLAGS _SFR_MEM8(0x0403) -#define RTC_TEMP _SFR_MEM8(0x0404) -#define RTC_CNT _SFR_MEM16(0x0408) -#define RTC_PER _SFR_MEM16(0x040A) -#define RTC_COMP _SFR_MEM16(0x040C) - -/* EBI - External Bus Interface */ -#define EBI_CTRL _SFR_MEM8(0x0440) -#define EBI_SDRAMCTRLA _SFR_MEM8(0x0441) -#define EBI_REFRESH _SFR_MEM16(0x0444) -#define EBI_INITDLY _SFR_MEM16(0x0446) -#define EBI_SDRAMCTRLB _SFR_MEM8(0x0448) -#define EBI_SDRAMCTRLC _SFR_MEM8(0x0449) -#define EBI_CS0_CTRLA _SFR_MEM8(0x0450) -#define EBI_CS0_CTRLB _SFR_MEM8(0x0451) -#define EBI_CS0_BASEADDR _SFR_MEM16(0x0452) -#define EBI_CS1_CTRLA _SFR_MEM8(0x0454) -#define EBI_CS1_CTRLB _SFR_MEM8(0x0455) -#define EBI_CS1_BASEADDR _SFR_MEM16(0x0456) -#define EBI_CS2_CTRLA _SFR_MEM8(0x0458) -#define EBI_CS2_CTRLB _SFR_MEM8(0x0459) -#define EBI_CS2_BASEADDR _SFR_MEM16(0x045A) -#define EBI_CS3_CTRLA _SFR_MEM8(0x045C) -#define EBI_CS3_CTRLB _SFR_MEM8(0x045D) -#define EBI_CS3_BASEADDR _SFR_MEM16(0x045E) - -/* TWIC - Two-Wire Interface C */ -#define TWIC_CTRL _SFR_MEM8(0x0480) -#define TWIC_MASTER_CTRLA _SFR_MEM8(0x0481) -#define TWIC_MASTER_CTRLB _SFR_MEM8(0x0482) -#define TWIC_MASTER_CTRLC _SFR_MEM8(0x0483) -#define TWIC_MASTER_STATUS _SFR_MEM8(0x0484) -#define TWIC_MASTER_BAUD _SFR_MEM8(0x0485) -#define TWIC_MASTER_ADDR _SFR_MEM8(0x0486) -#define TWIC_MASTER_DATA _SFR_MEM8(0x0487) -#define TWIC_SLAVE_CTRLA _SFR_MEM8(0x0488) -#define TWIC_SLAVE_CTRLB _SFR_MEM8(0x0489) -#define TWIC_SLAVE_STATUS _SFR_MEM8(0x048A) -#define TWIC_SLAVE_ADDR _SFR_MEM8(0x048B) -#define TWIC_SLAVE_DATA _SFR_MEM8(0x048C) -#define TWIC_SLAVE_ADDRMASK _SFR_MEM8(0x048D) - -/* TWID - Two-Wire Interface D */ -#define TWID_CTRL _SFR_MEM8(0x0490) -#define TWID_MASTER_CTRLA _SFR_MEM8(0x0491) -#define TWID_MASTER_CTRLB _SFR_MEM8(0x0492) -#define TWID_MASTER_CTRLC _SFR_MEM8(0x0493) -#define TWID_MASTER_STATUS _SFR_MEM8(0x0494) -#define TWID_MASTER_BAUD _SFR_MEM8(0x0495) -#define TWID_MASTER_ADDR _SFR_MEM8(0x0496) -#define TWID_MASTER_DATA _SFR_MEM8(0x0497) -#define TWID_SLAVE_CTRLA _SFR_MEM8(0x0498) -#define TWID_SLAVE_CTRLB _SFR_MEM8(0x0499) -#define TWID_SLAVE_STATUS _SFR_MEM8(0x049A) -#define TWID_SLAVE_ADDR _SFR_MEM8(0x049B) -#define TWID_SLAVE_DATA _SFR_MEM8(0x049C) -#define TWID_SLAVE_ADDRMASK _SFR_MEM8(0x049D) - -/* TWIE - Two-Wire Interface E */ -#define TWIE_CTRL _SFR_MEM8(0x04A0) -#define TWIE_MASTER_CTRLA _SFR_MEM8(0x04A1) -#define TWIE_MASTER_CTRLB _SFR_MEM8(0x04A2) -#define TWIE_MASTER_CTRLC _SFR_MEM8(0x04A3) -#define TWIE_MASTER_STATUS _SFR_MEM8(0x04A4) -#define TWIE_MASTER_BAUD _SFR_MEM8(0x04A5) -#define TWIE_MASTER_ADDR _SFR_MEM8(0x04A6) -#define TWIE_MASTER_DATA _SFR_MEM8(0x04A7) -#define TWIE_SLAVE_CTRLA _SFR_MEM8(0x04A8) -#define TWIE_SLAVE_CTRLB _SFR_MEM8(0x04A9) -#define TWIE_SLAVE_STATUS _SFR_MEM8(0x04AA) -#define TWIE_SLAVE_ADDR _SFR_MEM8(0x04AB) -#define TWIE_SLAVE_DATA _SFR_MEM8(0x04AC) -#define TWIE_SLAVE_ADDRMASK _SFR_MEM8(0x04AD) - -/* TWIF - Two-Wire Interface F */ -#define TWIF_CTRL _SFR_MEM8(0x04B0) -#define TWIF_MASTER_CTRLA _SFR_MEM8(0x04B1) -#define TWIF_MASTER_CTRLB _SFR_MEM8(0x04B2) -#define TWIF_MASTER_CTRLC _SFR_MEM8(0x04B3) -#define TWIF_MASTER_STATUS _SFR_MEM8(0x04B4) -#define TWIF_MASTER_BAUD _SFR_MEM8(0x04B5) -#define TWIF_MASTER_ADDR _SFR_MEM8(0x04B6) -#define TWIF_MASTER_DATA _SFR_MEM8(0x04B7) -#define TWIF_SLAVE_CTRLA _SFR_MEM8(0x04B8) -#define TWIF_SLAVE_CTRLB _SFR_MEM8(0x04B9) -#define TWIF_SLAVE_STATUS _SFR_MEM8(0x04BA) -#define TWIF_SLAVE_ADDR _SFR_MEM8(0x04BB) -#define TWIF_SLAVE_DATA _SFR_MEM8(0x04BC) -#define TWIF_SLAVE_ADDRMASK _SFR_MEM8(0x04BD) - -/* PORTA - Port A */ -#define PORTA_DIR _SFR_MEM8(0x0600) -#define PORTA_DIRSET _SFR_MEM8(0x0601) -#define PORTA_DIRCLR _SFR_MEM8(0x0602) -#define PORTA_DIRTGL _SFR_MEM8(0x0603) -#define PORTA_OUT _SFR_MEM8(0x0604) -#define PORTA_OUTSET _SFR_MEM8(0x0605) -#define PORTA_OUTCLR _SFR_MEM8(0x0606) -#define PORTA_OUTTGL _SFR_MEM8(0x0607) -#define PORTA_IN _SFR_MEM8(0x0608) -#define PORTA_INTCTRL _SFR_MEM8(0x0609) -#define PORTA_INT0MASK _SFR_MEM8(0x060A) -#define PORTA_INT1MASK _SFR_MEM8(0x060B) -#define PORTA_INTFLAGS _SFR_MEM8(0x060C) -#define PORTA_PIN0CTRL _SFR_MEM8(0x0610) -#define PORTA_PIN1CTRL _SFR_MEM8(0x0611) -#define PORTA_PIN2CTRL _SFR_MEM8(0x0612) -#define PORTA_PIN3CTRL _SFR_MEM8(0x0613) -#define PORTA_PIN4CTRL _SFR_MEM8(0x0614) -#define PORTA_PIN5CTRL _SFR_MEM8(0x0615) -#define PORTA_PIN6CTRL _SFR_MEM8(0x0616) -#define PORTA_PIN7CTRL _SFR_MEM8(0x0617) - -/* PORTB - Port B */ -#define PORTB_DIR _SFR_MEM8(0x0620) -#define PORTB_DIRSET _SFR_MEM8(0x0621) -#define PORTB_DIRCLR _SFR_MEM8(0x0622) -#define PORTB_DIRTGL _SFR_MEM8(0x0623) -#define PORTB_OUT _SFR_MEM8(0x0624) -#define PORTB_OUTSET _SFR_MEM8(0x0625) -#define PORTB_OUTCLR _SFR_MEM8(0x0626) -#define PORTB_OUTTGL _SFR_MEM8(0x0627) -#define PORTB_IN _SFR_MEM8(0x0628) -#define PORTB_INTCTRL _SFR_MEM8(0x0629) -#define PORTB_INT0MASK _SFR_MEM8(0x062A) -#define PORTB_INT1MASK _SFR_MEM8(0x062B) -#define PORTB_INTFLAGS _SFR_MEM8(0x062C) -#define PORTB_PIN0CTRL _SFR_MEM8(0x0630) -#define PORTB_PIN1CTRL _SFR_MEM8(0x0631) -#define PORTB_PIN2CTRL _SFR_MEM8(0x0632) -#define PORTB_PIN3CTRL _SFR_MEM8(0x0633) -#define PORTB_PIN4CTRL _SFR_MEM8(0x0634) -#define PORTB_PIN5CTRL _SFR_MEM8(0x0635) -#define PORTB_PIN6CTRL _SFR_MEM8(0x0636) -#define PORTB_PIN7CTRL _SFR_MEM8(0x0637) - -/* PORTC - Port C */ -#define PORTC_DIR _SFR_MEM8(0x0640) -#define PORTC_DIRSET _SFR_MEM8(0x0641) -#define PORTC_DIRCLR _SFR_MEM8(0x0642) -#define PORTC_DIRTGL _SFR_MEM8(0x0643) -#define PORTC_OUT _SFR_MEM8(0x0644) -#define PORTC_OUTSET _SFR_MEM8(0x0645) -#define PORTC_OUTCLR _SFR_MEM8(0x0646) -#define PORTC_OUTTGL _SFR_MEM8(0x0647) -#define PORTC_IN _SFR_MEM8(0x0648) -#define PORTC_INTCTRL _SFR_MEM8(0x0649) -#define PORTC_INT0MASK _SFR_MEM8(0x064A) -#define PORTC_INT1MASK _SFR_MEM8(0x064B) -#define PORTC_INTFLAGS _SFR_MEM8(0x064C) -#define PORTC_PIN0CTRL _SFR_MEM8(0x0650) -#define PORTC_PIN1CTRL _SFR_MEM8(0x0651) -#define PORTC_PIN2CTRL _SFR_MEM8(0x0652) -#define PORTC_PIN3CTRL _SFR_MEM8(0x0653) -#define PORTC_PIN4CTRL _SFR_MEM8(0x0654) -#define PORTC_PIN5CTRL _SFR_MEM8(0x0655) -#define PORTC_PIN6CTRL _SFR_MEM8(0x0656) -#define PORTC_PIN7CTRL _SFR_MEM8(0x0657) - -/* PORTD - Port D */ -#define PORTD_DIR _SFR_MEM8(0x0660) -#define PORTD_DIRSET _SFR_MEM8(0x0661) -#define PORTD_DIRCLR _SFR_MEM8(0x0662) -#define PORTD_DIRTGL _SFR_MEM8(0x0663) -#define PORTD_OUT _SFR_MEM8(0x0664) -#define PORTD_OUTSET _SFR_MEM8(0x0665) -#define PORTD_OUTCLR _SFR_MEM8(0x0666) -#define PORTD_OUTTGL _SFR_MEM8(0x0667) -#define PORTD_IN _SFR_MEM8(0x0668) -#define PORTD_INTCTRL _SFR_MEM8(0x0669) -#define PORTD_INT0MASK _SFR_MEM8(0x066A) -#define PORTD_INT1MASK _SFR_MEM8(0x066B) -#define PORTD_INTFLAGS _SFR_MEM8(0x066C) -#define PORTD_PIN0CTRL _SFR_MEM8(0x0670) -#define PORTD_PIN1CTRL _SFR_MEM8(0x0671) -#define PORTD_PIN2CTRL _SFR_MEM8(0x0672) -#define PORTD_PIN3CTRL _SFR_MEM8(0x0673) -#define PORTD_PIN4CTRL _SFR_MEM8(0x0674) -#define PORTD_PIN5CTRL _SFR_MEM8(0x0675) -#define PORTD_PIN6CTRL _SFR_MEM8(0x0676) -#define PORTD_PIN7CTRL _SFR_MEM8(0x0677) - -/* PORTE - Port E */ -#define PORTE_DIR _SFR_MEM8(0x0680) -#define PORTE_DIRSET _SFR_MEM8(0x0681) -#define PORTE_DIRCLR _SFR_MEM8(0x0682) -#define PORTE_DIRTGL _SFR_MEM8(0x0683) -#define PORTE_OUT _SFR_MEM8(0x0684) -#define PORTE_OUTSET _SFR_MEM8(0x0685) -#define PORTE_OUTCLR _SFR_MEM8(0x0686) -#define PORTE_OUTTGL _SFR_MEM8(0x0687) -#define PORTE_IN _SFR_MEM8(0x0688) -#define PORTE_INTCTRL _SFR_MEM8(0x0689) -#define PORTE_INT0MASK _SFR_MEM8(0x068A) -#define PORTE_INT1MASK _SFR_MEM8(0x068B) -#define PORTE_INTFLAGS _SFR_MEM8(0x068C) -#define PORTE_PIN0CTRL _SFR_MEM8(0x0690) -#define PORTE_PIN1CTRL _SFR_MEM8(0x0691) -#define PORTE_PIN2CTRL _SFR_MEM8(0x0692) -#define PORTE_PIN3CTRL _SFR_MEM8(0x0693) -#define PORTE_PIN4CTRL _SFR_MEM8(0x0694) -#define PORTE_PIN5CTRL _SFR_MEM8(0x0695) -#define PORTE_PIN6CTRL _SFR_MEM8(0x0696) -#define PORTE_PIN7CTRL _SFR_MEM8(0x0697) - -/* PORTF - Port F */ -#define PORTF_DIR _SFR_MEM8(0x06A0) -#define PORTF_DIRSET _SFR_MEM8(0x06A1) -#define PORTF_DIRCLR _SFR_MEM8(0x06A2) -#define PORTF_DIRTGL _SFR_MEM8(0x06A3) -#define PORTF_OUT _SFR_MEM8(0x06A4) -#define PORTF_OUTSET _SFR_MEM8(0x06A5) -#define PORTF_OUTCLR _SFR_MEM8(0x06A6) -#define PORTF_OUTTGL _SFR_MEM8(0x06A7) -#define PORTF_IN _SFR_MEM8(0x06A8) -#define PORTF_INTCTRL _SFR_MEM8(0x06A9) -#define PORTF_INT0MASK _SFR_MEM8(0x06AA) -#define PORTF_INT1MASK _SFR_MEM8(0x06AB) -#define PORTF_INTFLAGS _SFR_MEM8(0x06AC) -#define PORTF_PIN0CTRL _SFR_MEM8(0x06B0) -#define PORTF_PIN1CTRL _SFR_MEM8(0x06B1) -#define PORTF_PIN2CTRL _SFR_MEM8(0x06B2) -#define PORTF_PIN3CTRL _SFR_MEM8(0x06B3) -#define PORTF_PIN4CTRL _SFR_MEM8(0x06B4) -#define PORTF_PIN5CTRL _SFR_MEM8(0x06B5) -#define PORTF_PIN6CTRL _SFR_MEM8(0x06B6) -#define PORTF_PIN7CTRL _SFR_MEM8(0x06B7) - -/* PORTH - Port H */ -#define PORTH_DIR _SFR_MEM8(0x06E0) -#define PORTH_DIRSET _SFR_MEM8(0x06E1) -#define PORTH_DIRCLR _SFR_MEM8(0x06E2) -#define PORTH_DIRTGL _SFR_MEM8(0x06E3) -#define PORTH_OUT _SFR_MEM8(0x06E4) -#define PORTH_OUTSET _SFR_MEM8(0x06E5) -#define PORTH_OUTCLR _SFR_MEM8(0x06E6) -#define PORTH_OUTTGL _SFR_MEM8(0x06E7) -#define PORTH_IN _SFR_MEM8(0x06E8) -#define PORTH_INTCTRL _SFR_MEM8(0x06E9) -#define PORTH_INT0MASK _SFR_MEM8(0x06EA) -#define PORTH_INT1MASK _SFR_MEM8(0x06EB) -#define PORTH_INTFLAGS _SFR_MEM8(0x06EC) -#define PORTH_PIN0CTRL _SFR_MEM8(0x06F0) -#define PORTH_PIN1CTRL _SFR_MEM8(0x06F1) -#define PORTH_PIN2CTRL _SFR_MEM8(0x06F2) -#define PORTH_PIN3CTRL _SFR_MEM8(0x06F3) -#define PORTH_PIN4CTRL _SFR_MEM8(0x06F4) -#define PORTH_PIN5CTRL _SFR_MEM8(0x06F5) -#define PORTH_PIN6CTRL _SFR_MEM8(0x06F6) -#define PORTH_PIN7CTRL _SFR_MEM8(0x06F7) - -/* PORTJ - Port J */ -#define PORTJ_DIR _SFR_MEM8(0x0700) -#define PORTJ_DIRSET _SFR_MEM8(0x0701) -#define PORTJ_DIRCLR _SFR_MEM8(0x0702) -#define PORTJ_DIRTGL _SFR_MEM8(0x0703) -#define PORTJ_OUT _SFR_MEM8(0x0704) -#define PORTJ_OUTSET _SFR_MEM8(0x0705) -#define PORTJ_OUTCLR _SFR_MEM8(0x0706) -#define PORTJ_OUTTGL _SFR_MEM8(0x0707) -#define PORTJ_IN _SFR_MEM8(0x0708) -#define PORTJ_INTCTRL _SFR_MEM8(0x0709) -#define PORTJ_INT0MASK _SFR_MEM8(0x070A) -#define PORTJ_INT1MASK _SFR_MEM8(0x070B) -#define PORTJ_INTFLAGS _SFR_MEM8(0x070C) -#define PORTJ_PIN0CTRL _SFR_MEM8(0x0710) -#define PORTJ_PIN1CTRL _SFR_MEM8(0x0711) -#define PORTJ_PIN2CTRL _SFR_MEM8(0x0712) -#define PORTJ_PIN3CTRL _SFR_MEM8(0x0713) -#define PORTJ_PIN4CTRL _SFR_MEM8(0x0714) -#define PORTJ_PIN5CTRL _SFR_MEM8(0x0715) -#define PORTJ_PIN6CTRL _SFR_MEM8(0x0716) -#define PORTJ_PIN7CTRL _SFR_MEM8(0x0717) - -/* PORTK - Port K */ -#define PORTK_DIR _SFR_MEM8(0x0720) -#define PORTK_DIRSET _SFR_MEM8(0x0721) -#define PORTK_DIRCLR _SFR_MEM8(0x0722) -#define PORTK_DIRTGL _SFR_MEM8(0x0723) -#define PORTK_OUT _SFR_MEM8(0x0724) -#define PORTK_OUTSET _SFR_MEM8(0x0725) -#define PORTK_OUTCLR _SFR_MEM8(0x0726) -#define PORTK_OUTTGL _SFR_MEM8(0x0727) -#define PORTK_IN _SFR_MEM8(0x0728) -#define PORTK_INTCTRL _SFR_MEM8(0x0729) -#define PORTK_INT0MASK _SFR_MEM8(0x072A) -#define PORTK_INT1MASK _SFR_MEM8(0x072B) -#define PORTK_INTFLAGS _SFR_MEM8(0x072C) -#define PORTK_PIN0CTRL _SFR_MEM8(0x0730) -#define PORTK_PIN1CTRL _SFR_MEM8(0x0731) -#define PORTK_PIN2CTRL _SFR_MEM8(0x0732) -#define PORTK_PIN3CTRL _SFR_MEM8(0x0733) -#define PORTK_PIN4CTRL _SFR_MEM8(0x0734) -#define PORTK_PIN5CTRL _SFR_MEM8(0x0735) -#define PORTK_PIN6CTRL _SFR_MEM8(0x0736) -#define PORTK_PIN7CTRL _SFR_MEM8(0x0737) - -/* PORTQ - Port Q */ -#define PORTQ_DIR _SFR_MEM8(0x07C0) -#define PORTQ_DIRSET _SFR_MEM8(0x07C1) -#define PORTQ_DIRCLR _SFR_MEM8(0x07C2) -#define PORTQ_DIRTGL _SFR_MEM8(0x07C3) -#define PORTQ_OUT _SFR_MEM8(0x07C4) -#define PORTQ_OUTSET _SFR_MEM8(0x07C5) -#define PORTQ_OUTCLR _SFR_MEM8(0x07C6) -#define PORTQ_OUTTGL _SFR_MEM8(0x07C7) -#define PORTQ_IN _SFR_MEM8(0x07C8) -#define PORTQ_INTCTRL _SFR_MEM8(0x07C9) -#define PORTQ_INT0MASK _SFR_MEM8(0x07CA) -#define PORTQ_INT1MASK _SFR_MEM8(0x07CB) -#define PORTQ_INTFLAGS _SFR_MEM8(0x07CC) -#define PORTQ_PIN0CTRL _SFR_MEM8(0x07D0) -#define PORTQ_PIN1CTRL _SFR_MEM8(0x07D1) -#define PORTQ_PIN2CTRL _SFR_MEM8(0x07D2) -#define PORTQ_PIN3CTRL _SFR_MEM8(0x07D3) -#define PORTQ_PIN4CTRL _SFR_MEM8(0x07D4) -#define PORTQ_PIN5CTRL _SFR_MEM8(0x07D5) -#define PORTQ_PIN6CTRL _SFR_MEM8(0x07D6) -#define PORTQ_PIN7CTRL _SFR_MEM8(0x07D7) - -/* PORTR - Port R */ -#define PORTR_DIR _SFR_MEM8(0x07E0) -#define PORTR_DIRSET _SFR_MEM8(0x07E1) -#define PORTR_DIRCLR _SFR_MEM8(0x07E2) -#define PORTR_DIRTGL _SFR_MEM8(0x07E3) -#define PORTR_OUT _SFR_MEM8(0x07E4) -#define PORTR_OUTSET _SFR_MEM8(0x07E5) -#define PORTR_OUTCLR _SFR_MEM8(0x07E6) -#define PORTR_OUTTGL _SFR_MEM8(0x07E7) -#define PORTR_IN _SFR_MEM8(0x07E8) -#define PORTR_INTCTRL _SFR_MEM8(0x07E9) -#define PORTR_INT0MASK _SFR_MEM8(0x07EA) -#define PORTR_INT1MASK _SFR_MEM8(0x07EB) -#define PORTR_INTFLAGS _SFR_MEM8(0x07EC) -#define PORTR_PIN0CTRL _SFR_MEM8(0x07F0) -#define PORTR_PIN1CTRL _SFR_MEM8(0x07F1) -#define PORTR_PIN2CTRL _SFR_MEM8(0x07F2) -#define PORTR_PIN3CTRL _SFR_MEM8(0x07F3) -#define PORTR_PIN4CTRL _SFR_MEM8(0x07F4) -#define PORTR_PIN5CTRL _SFR_MEM8(0x07F5) -#define PORTR_PIN6CTRL _SFR_MEM8(0x07F6) -#define PORTR_PIN7CTRL _SFR_MEM8(0x07F7) - -/* TCC0 - Timer/Counter C0 */ -#define TCC0_CTRLA _SFR_MEM8(0x0800) -#define TCC0_CTRLB _SFR_MEM8(0x0801) -#define TCC0_CTRLC _SFR_MEM8(0x0802) -#define TCC0_CTRLD _SFR_MEM8(0x0803) -#define TCC0_CTRLE _SFR_MEM8(0x0804) -#define TCC0_INTCTRLA _SFR_MEM8(0x0806) -#define TCC0_INTCTRLB _SFR_MEM8(0x0807) -#define TCC0_CTRLFCLR _SFR_MEM8(0x0808) -#define TCC0_CTRLFSET _SFR_MEM8(0x0809) -#define TCC0_CTRLGCLR _SFR_MEM8(0x080A) -#define TCC0_CTRLGSET _SFR_MEM8(0x080B) -#define TCC0_INTFLAGS _SFR_MEM8(0x080C) -#define TCC0_TEMP _SFR_MEM8(0x080F) -#define TCC0_CNT _SFR_MEM16(0x0820) -#define TCC0_PER _SFR_MEM16(0x0826) -#define TCC0_CCA _SFR_MEM16(0x0828) -#define TCC0_CCB _SFR_MEM16(0x082A) -#define TCC0_CCC _SFR_MEM16(0x082C) -#define TCC0_CCD _SFR_MEM16(0x082E) -#define TCC0_PERBUF _SFR_MEM16(0x0836) -#define TCC0_CCABUF _SFR_MEM16(0x0838) -#define TCC0_CCBBUF _SFR_MEM16(0x083A) -#define TCC0_CCCBUF _SFR_MEM16(0x083C) -#define TCC0_CCDBUF _SFR_MEM16(0x083E) - -/* TCC1 - Timer/Counter C1 */ -#define TCC1_CTRLA _SFR_MEM8(0x0840) -#define TCC1_CTRLB _SFR_MEM8(0x0841) -#define TCC1_CTRLC _SFR_MEM8(0x0842) -#define TCC1_CTRLD _SFR_MEM8(0x0843) -#define TCC1_CTRLE _SFR_MEM8(0x0844) -#define TCC1_INTCTRLA _SFR_MEM8(0x0846) -#define TCC1_INTCTRLB _SFR_MEM8(0x0847) -#define TCC1_CTRLFCLR _SFR_MEM8(0x0848) -#define TCC1_CTRLFSET _SFR_MEM8(0x0849) -#define TCC1_CTRLGCLR _SFR_MEM8(0x084A) -#define TCC1_CTRLGSET _SFR_MEM8(0x084B) -#define TCC1_INTFLAGS _SFR_MEM8(0x084C) -#define TCC1_TEMP _SFR_MEM8(0x084F) -#define TCC1_CNT _SFR_MEM16(0x0860) -#define TCC1_PER _SFR_MEM16(0x0866) -#define TCC1_CCA _SFR_MEM16(0x0868) -#define TCC1_CCB _SFR_MEM16(0x086A) -#define TCC1_PERBUF _SFR_MEM16(0x0876) -#define TCC1_CCABUF _SFR_MEM16(0x0878) -#define TCC1_CCBBUF _SFR_MEM16(0x087A) - -/* AWEXC - Advanced Waveform Extension C */ -#define AWEXC_CTRL _SFR_MEM8(0x0880) -#define AWEXC_FDEMASK _SFR_MEM8(0x0882) -#define AWEXC_FDCTRL _SFR_MEM8(0x0883) -#define AWEXC_STATUS _SFR_MEM8(0x0884) -#define AWEXC_DTBOTH _SFR_MEM8(0x0886) -#define AWEXC_DTBOTHBUF _SFR_MEM8(0x0887) -#define AWEXC_DTLS _SFR_MEM8(0x0888) -#define AWEXC_DTHS _SFR_MEM8(0x0889) -#define AWEXC_DTLSBUF _SFR_MEM8(0x088A) -#define AWEXC_DTHSBUF _SFR_MEM8(0x088B) -#define AWEXC_OUTOVEN _SFR_MEM8(0x088C) - -/* HIRESC - High-Resolution Extension C */ -#define HIRESC_CTRLA _SFR_MEM8(0x0890) - -/* USARTC0 - Universal Asynchronous Receiver-Transmitter C0 */ -#define USARTC0_DATA _SFR_MEM8(0x08A0) -#define USARTC0_STATUS _SFR_MEM8(0x08A1) -#define USARTC0_CTRLA _SFR_MEM8(0x08A3) -#define USARTC0_CTRLB _SFR_MEM8(0x08A4) -#define USARTC0_CTRLC _SFR_MEM8(0x08A5) -#define USARTC0_BAUDCTRLA _SFR_MEM8(0x08A6) -#define USARTC0_BAUDCTRLB _SFR_MEM8(0x08A7) - -/* USARTC1 - Universal Asynchronous Receiver-Transmitter C1 */ -#define USARTC1_DATA _SFR_MEM8(0x08B0) -#define USARTC1_STATUS _SFR_MEM8(0x08B1) -#define USARTC1_CTRLA _SFR_MEM8(0x08B3) -#define USARTC1_CTRLB _SFR_MEM8(0x08B4) -#define USARTC1_CTRLC _SFR_MEM8(0x08B5) -#define USARTC1_BAUDCTRLA _SFR_MEM8(0x08B6) -#define USARTC1_BAUDCTRLB _SFR_MEM8(0x08B7) - -/* SPIC - Serial Peripheral Interface C */ -#define SPIC_CTRL _SFR_MEM8(0x08C0) -#define SPIC_INTCTRL _SFR_MEM8(0x08C1) -#define SPIC_STATUS _SFR_MEM8(0x08C2) -#define SPIC_DATA _SFR_MEM8(0x08C3) - -/* IRCOM - IR Communication Module */ -#define IRCOM_CTRL _SFR_MEM8(0x08F8) -#define IRCOM_TXPLCTRL _SFR_MEM8(0x08F9) -#define IRCOM_RXPLCTRL _SFR_MEM8(0x08FA) - -/* TCD0 - Timer/Counter D0 */ -#define TCD0_CTRLA _SFR_MEM8(0x0900) -#define TCD0_CTRLB _SFR_MEM8(0x0901) -#define TCD0_CTRLC _SFR_MEM8(0x0902) -#define TCD0_CTRLD _SFR_MEM8(0x0903) -#define TCD0_CTRLE _SFR_MEM8(0x0904) -#define TCD0_INTCTRLA _SFR_MEM8(0x0906) -#define TCD0_INTCTRLB _SFR_MEM8(0x0907) -#define TCD0_CTRLFCLR _SFR_MEM8(0x0908) -#define TCD0_CTRLFSET _SFR_MEM8(0x0909) -#define TCD0_CTRLGCLR _SFR_MEM8(0x090A) -#define TCD0_CTRLGSET _SFR_MEM8(0x090B) -#define TCD0_INTFLAGS _SFR_MEM8(0x090C) -#define TCD0_TEMP _SFR_MEM8(0x090F) -#define TCD0_CNT _SFR_MEM16(0x0920) -#define TCD0_PER _SFR_MEM16(0x0926) -#define TCD0_CCA _SFR_MEM16(0x0928) -#define TCD0_CCB _SFR_MEM16(0x092A) -#define TCD0_CCC _SFR_MEM16(0x092C) -#define TCD0_CCD _SFR_MEM16(0x092E) -#define TCD0_PERBUF _SFR_MEM16(0x0936) -#define TCD0_CCABUF _SFR_MEM16(0x0938) -#define TCD0_CCBBUF _SFR_MEM16(0x093A) -#define TCD0_CCCBUF _SFR_MEM16(0x093C) -#define TCD0_CCDBUF _SFR_MEM16(0x093E) - -/* TCD1 - Timer/Counter D1 */ -#define TCD1_CTRLA _SFR_MEM8(0x0940) -#define TCD1_CTRLB _SFR_MEM8(0x0941) -#define TCD1_CTRLC _SFR_MEM8(0x0942) -#define TCD1_CTRLD _SFR_MEM8(0x0943) -#define TCD1_CTRLE _SFR_MEM8(0x0944) -#define TCD1_INTCTRLA _SFR_MEM8(0x0946) -#define TCD1_INTCTRLB _SFR_MEM8(0x0947) -#define TCD1_CTRLFCLR _SFR_MEM8(0x0948) -#define TCD1_CTRLFSET _SFR_MEM8(0x0949) -#define TCD1_CTRLGCLR _SFR_MEM8(0x094A) -#define TCD1_CTRLGSET _SFR_MEM8(0x094B) -#define TCD1_INTFLAGS _SFR_MEM8(0x094C) -#define TCD1_TEMP _SFR_MEM8(0x094F) -#define TCD1_CNT _SFR_MEM16(0x0960) -#define TCD1_PER _SFR_MEM16(0x0966) -#define TCD1_CCA _SFR_MEM16(0x0968) -#define TCD1_CCB _SFR_MEM16(0x096A) -#define TCD1_PERBUF _SFR_MEM16(0x0976) -#define TCD1_CCABUF _SFR_MEM16(0x0978) -#define TCD1_CCBBUF _SFR_MEM16(0x097A) - -/* HIRESD - High-Resolution Extension D */ -#define HIRESD_CTRLA _SFR_MEM8(0x0990) - -/* USARTD0 - Universal Asynchronous Receiver-Transmitter D0 */ -#define USARTD0_DATA _SFR_MEM8(0x09A0) -#define USARTD0_STATUS _SFR_MEM8(0x09A1) -#define USARTD0_CTRLA _SFR_MEM8(0x09A3) -#define USARTD0_CTRLB _SFR_MEM8(0x09A4) -#define USARTD0_CTRLC _SFR_MEM8(0x09A5) -#define USARTD0_BAUDCTRLA _SFR_MEM8(0x09A6) -#define USARTD0_BAUDCTRLB _SFR_MEM8(0x09A7) - -/* USARTD1 - Universal Asynchronous Receiver-Transmitter D1 */ -#define USARTD1_DATA _SFR_MEM8(0x09B0) -#define USARTD1_STATUS _SFR_MEM8(0x09B1) -#define USARTD1_CTRLA _SFR_MEM8(0x09B3) -#define USARTD1_CTRLB _SFR_MEM8(0x09B4) -#define USARTD1_CTRLC _SFR_MEM8(0x09B5) -#define USARTD1_BAUDCTRLA _SFR_MEM8(0x09B6) -#define USARTD1_BAUDCTRLB _SFR_MEM8(0x09B7) - -/* SPID - Serial Peripheral Interface D */ -#define SPID_CTRL _SFR_MEM8(0x09C0) -#define SPID_INTCTRL _SFR_MEM8(0x09C1) -#define SPID_STATUS _SFR_MEM8(0x09C2) -#define SPID_DATA _SFR_MEM8(0x09C3) - -/* TCE0 - Timer/Counter E0 */ -#define TCE0_CTRLA _SFR_MEM8(0x0A00) -#define TCE0_CTRLB _SFR_MEM8(0x0A01) -#define TCE0_CTRLC _SFR_MEM8(0x0A02) -#define TCE0_CTRLD _SFR_MEM8(0x0A03) -#define TCE0_CTRLE _SFR_MEM8(0x0A04) -#define TCE0_INTCTRLA _SFR_MEM8(0x0A06) -#define TCE0_INTCTRLB _SFR_MEM8(0x0A07) -#define TCE0_CTRLFCLR _SFR_MEM8(0x0A08) -#define TCE0_CTRLFSET _SFR_MEM8(0x0A09) -#define TCE0_CTRLGCLR _SFR_MEM8(0x0A0A) -#define TCE0_CTRLGSET _SFR_MEM8(0x0A0B) -#define TCE0_INTFLAGS _SFR_MEM8(0x0A0C) -#define TCE0_TEMP _SFR_MEM8(0x0A0F) -#define TCE0_CNT _SFR_MEM16(0x0A20) -#define TCE0_PER _SFR_MEM16(0x0A26) -#define TCE0_CCA _SFR_MEM16(0x0A28) -#define TCE0_CCB _SFR_MEM16(0x0A2A) -#define TCE0_CCC _SFR_MEM16(0x0A2C) -#define TCE0_CCD _SFR_MEM16(0x0A2E) -#define TCE0_PERBUF _SFR_MEM16(0x0A36) -#define TCE0_CCABUF _SFR_MEM16(0x0A38) -#define TCE0_CCBBUF _SFR_MEM16(0x0A3A) -#define TCE0_CCCBUF _SFR_MEM16(0x0A3C) -#define TCE0_CCDBUF _SFR_MEM16(0x0A3E) - -/* TCE1 - Timer/Counter E1 */ -#define TCE1_CTRLA _SFR_MEM8(0x0A40) -#define TCE1_CTRLB _SFR_MEM8(0x0A41) -#define TCE1_CTRLC _SFR_MEM8(0x0A42) -#define TCE1_CTRLD _SFR_MEM8(0x0A43) -#define TCE1_CTRLE _SFR_MEM8(0x0A44) -#define TCE1_INTCTRLA _SFR_MEM8(0x0A46) -#define TCE1_INTCTRLB _SFR_MEM8(0x0A47) -#define TCE1_CTRLFCLR _SFR_MEM8(0x0A48) -#define TCE1_CTRLFSET _SFR_MEM8(0x0A49) -#define TCE1_CTRLGCLR _SFR_MEM8(0x0A4A) -#define TCE1_CTRLGSET _SFR_MEM8(0x0A4B) -#define TCE1_INTFLAGS _SFR_MEM8(0x0A4C) -#define TCE1_TEMP _SFR_MEM8(0x0A4F) -#define TCE1_CNT _SFR_MEM16(0x0A60) -#define TCE1_PER _SFR_MEM16(0x0A66) -#define TCE1_CCA _SFR_MEM16(0x0A68) -#define TCE1_CCB _SFR_MEM16(0x0A6A) -#define TCE1_PERBUF _SFR_MEM16(0x0A76) -#define TCE1_CCABUF _SFR_MEM16(0x0A78) -#define TCE1_CCBBUF _SFR_MEM16(0x0A7A) - -/* AWEXE - Advanced Waveform Extension E */ -#define AWEXE_CTRL _SFR_MEM8(0x0A80) -#define AWEXE_FDEMASK _SFR_MEM8(0x0A82) -#define AWEXE_FDCTRL _SFR_MEM8(0x0A83) -#define AWEXE_STATUS _SFR_MEM8(0x0A84) -#define AWEXE_DTBOTH _SFR_MEM8(0x0A86) -#define AWEXE_DTBOTHBUF _SFR_MEM8(0x0A87) -#define AWEXE_DTLS _SFR_MEM8(0x0A88) -#define AWEXE_DTHS _SFR_MEM8(0x0A89) -#define AWEXE_DTLSBUF _SFR_MEM8(0x0A8A) -#define AWEXE_DTHSBUF _SFR_MEM8(0x0A8B) -#define AWEXE_OUTOVEN _SFR_MEM8(0x0A8C) - -/* HIRESE - High-Resolution Extension E */ -#define HIRESE_CTRLA _SFR_MEM8(0x0A90) - -/* USARTE0 - Universal Asynchronous Receiver-Transmitter E0 */ -#define USARTE0_DATA _SFR_MEM8(0x0AA0) -#define USARTE0_STATUS _SFR_MEM8(0x0AA1) -#define USARTE0_CTRLA _SFR_MEM8(0x0AA3) -#define USARTE0_CTRLB _SFR_MEM8(0x0AA4) -#define USARTE0_CTRLC _SFR_MEM8(0x0AA5) -#define USARTE0_BAUDCTRLA _SFR_MEM8(0x0AA6) -#define USARTE0_BAUDCTRLB _SFR_MEM8(0x0AA7) - -/* USARTE1 - Universal Asynchronous Receiver-Transmitter E1 */ -#define USARTE1_DATA _SFR_MEM8(0x0AB0) -#define USARTE1_STATUS _SFR_MEM8(0x0AB1) -#define USARTE1_CTRLA _SFR_MEM8(0x0AB3) -#define USARTE1_CTRLB _SFR_MEM8(0x0AB4) -#define USARTE1_CTRLC _SFR_MEM8(0x0AB5) -#define USARTE1_BAUDCTRLA _SFR_MEM8(0x0AB6) -#define USARTE1_BAUDCTRLB _SFR_MEM8(0x0AB7) - -/* SPIE - Serial Peripheral Interface E */ -#define SPIE_CTRL _SFR_MEM8(0x0AC0) -#define SPIE_INTCTRL _SFR_MEM8(0x0AC1) -#define SPIE_STATUS _SFR_MEM8(0x0AC2) -#define SPIE_DATA _SFR_MEM8(0x0AC3) - -/* TCF0 - Timer/Counter F0 */ -#define TCF0_CTRLA _SFR_MEM8(0x0B00) -#define TCF0_CTRLB _SFR_MEM8(0x0B01) -#define TCF0_CTRLC _SFR_MEM8(0x0B02) -#define TCF0_CTRLD _SFR_MEM8(0x0B03) -#define TCF0_CTRLE _SFR_MEM8(0x0B04) -#define TCF0_INTCTRLA _SFR_MEM8(0x0B06) -#define TCF0_INTCTRLB _SFR_MEM8(0x0B07) -#define TCF0_CTRLFCLR _SFR_MEM8(0x0B08) -#define TCF0_CTRLFSET _SFR_MEM8(0x0B09) -#define TCF0_CTRLGCLR _SFR_MEM8(0x0B0A) -#define TCF0_CTRLGSET _SFR_MEM8(0x0B0B) -#define TCF0_INTFLAGS _SFR_MEM8(0x0B0C) -#define TCF0_TEMP _SFR_MEM8(0x0B0F) -#define TCF0_CNT _SFR_MEM16(0x0B20) -#define TCF0_PER _SFR_MEM16(0x0B26) -#define TCF0_CCA _SFR_MEM16(0x0B28) -#define TCF0_CCB _SFR_MEM16(0x0B2A) -#define TCF0_CCC _SFR_MEM16(0x0B2C) -#define TCF0_CCD _SFR_MEM16(0x0B2E) -#define TCF0_PERBUF _SFR_MEM16(0x0B36) -#define TCF0_CCABUF _SFR_MEM16(0x0B38) -#define TCF0_CCBBUF _SFR_MEM16(0x0B3A) -#define TCF0_CCCBUF _SFR_MEM16(0x0B3C) -#define TCF0_CCDBUF _SFR_MEM16(0x0B3E) - -/* TCF1 - Timer/Counter F1 */ -#define TCF1_CTRLA _SFR_MEM8(0x0B40) -#define TCF1_CTRLB _SFR_MEM8(0x0B41) -#define TCF1_CTRLC _SFR_MEM8(0x0B42) -#define TCF1_CTRLD _SFR_MEM8(0x0B43) -#define TCF1_CTRLE _SFR_MEM8(0x0B44) -#define TCF1_INTCTRLA _SFR_MEM8(0x0B46) -#define TCF1_INTCTRLB _SFR_MEM8(0x0B47) -#define TCF1_CTRLFCLR _SFR_MEM8(0x0B48) -#define TCF1_CTRLFSET _SFR_MEM8(0x0B49) -#define TCF1_CTRLGCLR _SFR_MEM8(0x0B4A) -#define TCF1_CTRLGSET _SFR_MEM8(0x0B4B) -#define TCF1_INTFLAGS _SFR_MEM8(0x0B4C) -#define TCF1_TEMP _SFR_MEM8(0x0B4F) -#define TCF1_CNT _SFR_MEM16(0x0B60) -#define TCF1_PER _SFR_MEM16(0x0B66) -#define TCF1_CCA _SFR_MEM16(0x0B68) -#define TCF1_CCB _SFR_MEM16(0x0B6A) -#define TCF1_PERBUF _SFR_MEM16(0x0B76) -#define TCF1_CCABUF _SFR_MEM16(0x0B78) -#define TCF1_CCBBUF _SFR_MEM16(0x0B7A) - -/* HIRESF - High-Resolution Extension F */ -#define HIRESF_CTRLA _SFR_MEM8(0x0B90) - -/* USARTF0 - Universal Asynchronous Receiver-Transmitter F0 */ -#define USARTF0_DATA _SFR_MEM8(0x0BA0) -#define USARTF0_STATUS _SFR_MEM8(0x0BA1) -#define USARTF0_CTRLA _SFR_MEM8(0x0BA3) -#define USARTF0_CTRLB _SFR_MEM8(0x0BA4) -#define USARTF0_CTRLC _SFR_MEM8(0x0BA5) -#define USARTF0_BAUDCTRLA _SFR_MEM8(0x0BA6) -#define USARTF0_BAUDCTRLB _SFR_MEM8(0x0BA7) - -/* USARTF1 - Universal Asynchronous Receiver-Transmitter F1 */ -#define USARTF1_DATA _SFR_MEM8(0x0BB0) -#define USARTF1_STATUS _SFR_MEM8(0x0BB1) -#define USARTF1_CTRLA _SFR_MEM8(0x0BB3) -#define USARTF1_CTRLB _SFR_MEM8(0x0BB4) -#define USARTF1_CTRLC _SFR_MEM8(0x0BB5) -#define USARTF1_BAUDCTRLA _SFR_MEM8(0x0BB6) -#define USARTF1_BAUDCTRLB _SFR_MEM8(0x0BB7) - -/* SPIF - Serial Peripheral Interface F */ -#define SPIF_CTRL _SFR_MEM8(0x0BC0) -#define SPIF_INTCTRL _SFR_MEM8(0x0BC1) -#define SPIF_STATUS _SFR_MEM8(0x0BC2) -#define SPIF_DATA _SFR_MEM8(0x0BC3) - - - -/*================== Bitfield Definitions ================== */ - -/* XOCD - On-Chip Debug System */ -/* OCD.OCDR1 bit masks and bit positions */ -#define OCD_OCDRD_bm 0x01 /* OCDR Dirty bit mask. */ -#define OCD_OCDRD_bp 0 /* OCDR Dirty bit position. */ - - -/* CPU - CPU */ -/* CPU.CCP bit masks and bit positions */ -#define CPU_CCP_gm 0xFF /* CCP signature group mask. */ -#define CPU_CCP_gp 0 /* CCP signature group position. */ -#define CPU_CCP0_bm (1<<0) /* CCP signature bit 0 mask. */ -#define CPU_CCP0_bp 0 /* CCP signature bit 0 position. */ -#define CPU_CCP1_bm (1<<1) /* CCP signature bit 1 mask. */ -#define CPU_CCP1_bp 1 /* CCP signature bit 1 position. */ -#define CPU_CCP2_bm (1<<2) /* CCP signature bit 2 mask. */ -#define CPU_CCP2_bp 2 /* CCP signature bit 2 position. */ -#define CPU_CCP3_bm (1<<3) /* CCP signature bit 3 mask. */ -#define CPU_CCP3_bp 3 /* CCP signature bit 3 position. */ -#define CPU_CCP4_bm (1<<4) /* CCP signature bit 4 mask. */ -#define CPU_CCP4_bp 4 /* CCP signature bit 4 position. */ -#define CPU_CCP5_bm (1<<5) /* CCP signature bit 5 mask. */ -#define CPU_CCP5_bp 5 /* CCP signature bit 5 position. */ -#define CPU_CCP6_bm (1<<6) /* CCP signature bit 6 mask. */ -#define CPU_CCP6_bp 6 /* CCP signature bit 6 position. */ -#define CPU_CCP7_bm (1<<7) /* CCP signature bit 7 mask. */ -#define CPU_CCP7_bp 7 /* CCP signature bit 7 position. */ - - -/* CPU.SREG bit masks and bit positions */ -#define CPU_I_bm 0x80 /* Global Interrupt Enable Flag bit mask. */ -#define CPU_I_bp 7 /* Global Interrupt Enable Flag bit position. */ - -#define CPU_T_bm 0x40 /* Transfer Bit bit mask. */ -#define CPU_T_bp 6 /* Transfer Bit bit position. */ - -#define CPU_H_bm 0x20 /* Half Carry Flag bit mask. */ -#define CPU_H_bp 5 /* Half Carry Flag bit position. */ - -#define CPU_S_bm 0x10 /* N Exclusive Or V Flag bit mask. */ -#define CPU_S_bp 4 /* N Exclusive Or V Flag bit position. */ - -#define CPU_V_bm 0x08 /* Two's Complement Overflow Flag bit mask. */ -#define CPU_V_bp 3 /* Two's Complement Overflow Flag bit position. */ - -#define CPU_N_bm 0x04 /* Negative Flag bit mask. */ -#define CPU_N_bp 2 /* Negative Flag bit position. */ - -#define CPU_Z_bm 0x02 /* Zero Flag bit mask. */ -#define CPU_Z_bp 1 /* Zero Flag bit position. */ - -#define CPU_C_bm 0x01 /* Carry Flag bit mask. */ -#define CPU_C_bp 0 /* Carry Flag bit position. */ - - -/* CLK - Clock System */ -/* CLK.CTRL bit masks and bit positions */ -#define CLK_SCLKSEL_gm 0x07 /* System Clock Selection group mask. */ -#define CLK_SCLKSEL_gp 0 /* System Clock Selection group position. */ -#define CLK_SCLKSEL0_bm (1<<0) /* System Clock Selection bit 0 mask. */ -#define CLK_SCLKSEL0_bp 0 /* System Clock Selection bit 0 position. */ -#define CLK_SCLKSEL1_bm (1<<1) /* System Clock Selection bit 1 mask. */ -#define CLK_SCLKSEL1_bp 1 /* System Clock Selection bit 1 position. */ -#define CLK_SCLKSEL2_bm (1<<2) /* System Clock Selection bit 2 mask. */ -#define CLK_SCLKSEL2_bp 2 /* System Clock Selection bit 2 position. */ - - -/* CLK.PSCTRL bit masks and bit positions */ -#define CLK_PSADIV_gm 0x7C /* Prescaler A Division Factor group mask. */ -#define CLK_PSADIV_gp 2 /* Prescaler A Division Factor group position. */ -#define CLK_PSADIV0_bm (1<<2) /* Prescaler A Division Factor bit 0 mask. */ -#define CLK_PSADIV0_bp 2 /* Prescaler A Division Factor bit 0 position. */ -#define CLK_PSADIV1_bm (1<<3) /* Prescaler A Division Factor bit 1 mask. */ -#define CLK_PSADIV1_bp 3 /* Prescaler A Division Factor bit 1 position. */ -#define CLK_PSADIV2_bm (1<<4) /* Prescaler A Division Factor bit 2 mask. */ -#define CLK_PSADIV2_bp 4 /* Prescaler A Division Factor bit 2 position. */ -#define CLK_PSADIV3_bm (1<<5) /* Prescaler A Division Factor bit 3 mask. */ -#define CLK_PSADIV3_bp 5 /* Prescaler A Division Factor bit 3 position. */ -#define CLK_PSADIV4_bm (1<<6) /* Prescaler A Division Factor bit 4 mask. */ -#define CLK_PSADIV4_bp 6 /* Prescaler A Division Factor bit 4 position. */ - -#define CLK_PSBCDIV_gm 0x03 /* Prescaler B and C Division factor group mask. */ -#define CLK_PSBCDIV_gp 0 /* Prescaler B and C Division factor group position. */ -#define CLK_PSBCDIV0_bm (1<<0) /* Prescaler B and C Division factor bit 0 mask. */ -#define CLK_PSBCDIV0_bp 0 /* Prescaler B and C Division factor bit 0 position. */ -#define CLK_PSBCDIV1_bm (1<<1) /* Prescaler B and C Division factor bit 1 mask. */ -#define CLK_PSBCDIV1_bp 1 /* Prescaler B and C Division factor bit 1 position. */ - - -/* CLK.LOCK bit masks and bit positions */ -#define CLK_LOCK_bm 0x01 /* Clock System Lock bit mask. */ -#define CLK_LOCK_bp 0 /* Clock System Lock bit position. */ - - -/* CLK.RTCCTRL bit masks and bit positions */ -#define CLK_RTCSRC_gm 0x0E /* Clock Source group mask. */ -#define CLK_RTCSRC_gp 1 /* Clock Source group position. */ -#define CLK_RTCSRC0_bm (1<<1) /* Clock Source bit 0 mask. */ -#define CLK_RTCSRC0_bp 1 /* Clock Source bit 0 position. */ -#define CLK_RTCSRC1_bm (1<<2) /* Clock Source bit 1 mask. */ -#define CLK_RTCSRC1_bp 2 /* Clock Source bit 1 position. */ -#define CLK_RTCSRC2_bm (1<<3) /* Clock Source bit 2 mask. */ -#define CLK_RTCSRC2_bp 3 /* Clock Source bit 2 position. */ - -#define CLK_RTCEN_bm 0x01 /* RTC Clock Source Enable bit mask. */ -#define CLK_RTCEN_bp 0 /* RTC Clock Source Enable bit position. */ - - -/* PR.PRGEN bit masks and bit positions */ -#define PR_AES_bm 0x10 /* AES bit mask. */ -#define PR_AES_bp 4 /* AES bit position. */ - -#define PR_EBI_bm 0x08 /* External Bus Interface bit mask. */ -#define PR_EBI_bp 3 /* External Bus Interface bit position. */ - -#define PR_RTC_bm 0x04 /* Real-time Counter bit mask. */ -#define PR_RTC_bp 2 /* Real-time Counter bit position. */ - -#define PR_EVSYS_bm 0x02 /* Event System bit mask. */ -#define PR_EVSYS_bp 1 /* Event System bit position. */ - -#define PR_DMA_bm 0x01 /* DMA-Controller bit mask. */ -#define PR_DMA_bp 0 /* DMA-Controller bit position. */ - - -/* PR.PRPA bit masks and bit positions */ -#define PR_DAC_bm 0x04 /* Port A DAC bit mask. */ -#define PR_DAC_bp 2 /* Port A DAC bit position. */ - -#define PR_ADC_bm 0x02 /* Port A ADC bit mask. */ -#define PR_ADC_bp 1 /* Port A ADC bit position. */ - -#define PR_AC_bm 0x01 /* Port A Analog Comparator bit mask. */ -#define PR_AC_bp 0 /* Port A Analog Comparator bit position. */ - - -/* PR.PRPB bit masks and bit positions */ -/* PR_DAC_bm Predefined. */ -/* PR_DAC_bp Predefined. */ - -/* PR_ADC_bm Predefined. */ -/* PR_ADC_bp Predefined. */ - -/* PR_AC_bm Predefined. */ -/* PR_AC_bp Predefined. */ - - -/* PR.PRPC bit masks and bit positions */ -#define PR_TWI_bm 0x40 /* Port C Two-wire Interface bit mask. */ -#define PR_TWI_bp 6 /* Port C Two-wire Interface bit position. */ - -#define PR_USART1_bm 0x20 /* Port C USART1 bit mask. */ -#define PR_USART1_bp 5 /* Port C USART1 bit position. */ - -#define PR_USART0_bm 0x10 /* Port C USART0 bit mask. */ -#define PR_USART0_bp 4 /* Port C USART0 bit position. */ - -#define PR_SPI_bm 0x08 /* Port C SPI bit mask. */ -#define PR_SPI_bp 3 /* Port C SPI bit position. */ - -#define PR_HIRES_bm 0x04 /* Port C AWEX bit mask. */ -#define PR_HIRES_bp 2 /* Port C AWEX bit position. */ - -#define PR_TC1_bm 0x02 /* Port C Timer/Counter1 bit mask. */ -#define PR_TC1_bp 1 /* Port C Timer/Counter1 bit position. */ - -#define PR_TC0_bm 0x01 /* Port C Timer/Counter0 bit mask. */ -#define PR_TC0_bp 0 /* Port C Timer/Counter0 bit position. */ - - -/* PR.PRPD bit masks and bit positions */ -/* PR_TWI_bm Predefined. */ -/* PR_TWI_bp Predefined. */ - -/* PR_USART1_bm Predefined. */ -/* PR_USART1_bp Predefined. */ - -/* PR_USART0_bm Predefined. */ -/* PR_USART0_bp Predefined. */ - -/* PR_SPI_bm Predefined. */ -/* PR_SPI_bp Predefined. */ - -/* PR_HIRES_bm Predefined. */ -/* PR_HIRES_bp Predefined. */ - -/* PR_TC1_bm Predefined. */ -/* PR_TC1_bp Predefined. */ - -/* PR_TC0_bm Predefined. */ -/* PR_TC0_bp Predefined. */ - - -/* PR.PRPE bit masks and bit positions */ -/* PR_TWI_bm Predefined. */ -/* PR_TWI_bp Predefined. */ - -/* PR_USART1_bm Predefined. */ -/* PR_USART1_bp Predefined. */ - -/* PR_USART0_bm Predefined. */ -/* PR_USART0_bp Predefined. */ - -/* PR_SPI_bm Predefined. */ -/* PR_SPI_bp Predefined. */ - -/* PR_HIRES_bm Predefined. */ -/* PR_HIRES_bp Predefined. */ - -/* PR_TC1_bm Predefined. */ -/* PR_TC1_bp Predefined. */ - -/* PR_TC0_bm Predefined. */ -/* PR_TC0_bp Predefined. */ - - -/* PR.PRPF bit masks and bit positions */ -/* PR_TWI_bm Predefined. */ -/* PR_TWI_bp Predefined. */ - -/* PR_USART1_bm Predefined. */ -/* PR_USART1_bp Predefined. */ - -/* PR_USART0_bm Predefined. */ -/* PR_USART0_bp Predefined. */ - -/* PR_SPI_bm Predefined. */ -/* PR_SPI_bp Predefined. */ - -/* PR_HIRES_bm Predefined. */ -/* PR_HIRES_bp Predefined. */ - -/* PR_TC1_bm Predefined. */ -/* PR_TC1_bp Predefined. */ - -/* PR_TC0_bm Predefined. */ -/* PR_TC0_bp Predefined. */ - - -/* SLEEP - Sleep Controller */ -/* SLEEP.CTRL bit masks and bit positions */ -#define SLEEP_SMODE_gm 0x0E /* Sleep Mode group mask. */ -#define SLEEP_SMODE_gp 1 /* Sleep Mode group position. */ -#define SLEEP_SMODE0_bm (1<<1) /* Sleep Mode bit 0 mask. */ -#define SLEEP_SMODE0_bp 1 /* Sleep Mode bit 0 position. */ -#define SLEEP_SMODE1_bm (1<<2) /* Sleep Mode bit 1 mask. */ -#define SLEEP_SMODE1_bp 2 /* Sleep Mode bit 1 position. */ -#define SLEEP_SMODE2_bm (1<<3) /* Sleep Mode bit 2 mask. */ -#define SLEEP_SMODE2_bp 3 /* Sleep Mode bit 2 position. */ - -#define SLEEP_SEN_bm 0x01 /* Sleep Enable bit mask. */ -#define SLEEP_SEN_bp 0 /* Sleep Enable bit position. */ - - -/* OSC - Oscillator */ -/* OSC.CTRL bit masks and bit positions */ -#define OSC_PLLEN_bm 0x10 /* PLL Enable bit mask. */ -#define OSC_PLLEN_bp 4 /* PLL Enable bit position. */ - -#define OSC_XOSCEN_bm 0x08 /* External Oscillator Enable bit mask. */ -#define OSC_XOSCEN_bp 3 /* External Oscillator Enable bit position. */ - -#define OSC_RC32KEN_bm 0x04 /* Internal 32kHz RC Oscillator Enable bit mask. */ -#define OSC_RC32KEN_bp 2 /* Internal 32kHz RC Oscillator Enable bit position. */ - -#define OSC_RC32MEN_bm 0x02 /* Internal 32MHz RC Oscillator Enable bit mask. */ -#define OSC_RC32MEN_bp 1 /* Internal 32MHz RC Oscillator Enable bit position. */ - -#define OSC_RC2MEN_bm 0x01 /* Internal 2MHz RC Oscillator Enable bit mask. */ -#define OSC_RC2MEN_bp 0 /* Internal 2MHz RC Oscillator Enable bit position. */ - - -/* OSC.STATUS bit masks and bit positions */ -#define OSC_PLLRDY_bm 0x10 /* PLL Ready bit mask. */ -#define OSC_PLLRDY_bp 4 /* PLL Ready bit position. */ - -#define OSC_XOSCRDY_bm 0x08 /* External Oscillator Ready bit mask. */ -#define OSC_XOSCRDY_bp 3 /* External Oscillator Ready bit position. */ - -#define OSC_RC32KRDY_bm 0x04 /* Internal 32kHz RC Oscillator Ready bit mask. */ -#define OSC_RC32KRDY_bp 2 /* Internal 32kHz RC Oscillator Ready bit position. */ - -#define OSC_RC32MRDY_bm 0x02 /* Internal 32MHz RC Oscillator Ready bit mask. */ -#define OSC_RC32MRDY_bp 1 /* Internal 32MHz RC Oscillator Ready bit position. */ - -#define OSC_RC2MRDY_bm 0x01 /* Internal 2MHz RC Oscillator Ready bit mask. */ -#define OSC_RC2MRDY_bp 0 /* Internal 2MHz RC Oscillator Ready bit position. */ - - -/* OSC.XOSCCTRL bit masks and bit positions */ -#define OSC_FRQRANGE_gm 0xC0 /* Frequency Range group mask. */ -#define OSC_FRQRANGE_gp 6 /* Frequency Range group position. */ -#define OSC_FRQRANGE0_bm (1<<6) /* Frequency Range bit 0 mask. */ -#define OSC_FRQRANGE0_bp 6 /* Frequency Range bit 0 position. */ -#define OSC_FRQRANGE1_bm (1<<7) /* Frequency Range bit 1 mask. */ -#define OSC_FRQRANGE1_bp 7 /* Frequency Range bit 1 position. */ - -#define OSC_X32KLPM_bm 0x20 /* 32kHz XTAL OSC Low-power Mode bit mask. */ -#define OSC_X32KLPM_bp 5 /* 32kHz XTAL OSC Low-power Mode bit position. */ - -#define OSC_XOSCSEL_gm 0x0F /* External Oscillator Selection and Startup Time group mask. */ -#define OSC_XOSCSEL_gp 0 /* External Oscillator Selection and Startup Time group position. */ -#define OSC_XOSCSEL0_bm (1<<0) /* External Oscillator Selection and Startup Time bit 0 mask. */ -#define OSC_XOSCSEL0_bp 0 /* External Oscillator Selection and Startup Time bit 0 position. */ -#define OSC_XOSCSEL1_bm (1<<1) /* External Oscillator Selection and Startup Time bit 1 mask. */ -#define OSC_XOSCSEL1_bp 1 /* External Oscillator Selection and Startup Time bit 1 position. */ -#define OSC_XOSCSEL2_bm (1<<2) /* External Oscillator Selection and Startup Time bit 2 mask. */ -#define OSC_XOSCSEL2_bp 2 /* External Oscillator Selection and Startup Time bit 2 position. */ -#define OSC_XOSCSEL3_bm (1<<3) /* External Oscillator Selection and Startup Time bit 3 mask. */ -#define OSC_XOSCSEL3_bp 3 /* External Oscillator Selection and Startup Time bit 3 position. */ - - -/* OSC.XOSCFAIL bit masks and bit positions */ -#define OSC_XOSCFDIF_bm 0x02 /* Failure Detection Interrupt Flag bit mask. */ -#define OSC_XOSCFDIF_bp 1 /* Failure Detection Interrupt Flag bit position. */ - -#define OSC_XOSCFDEN_bm 0x01 /* Failure Detection Enable bit mask. */ -#define OSC_XOSCFDEN_bp 0 /* Failure Detection Enable bit position. */ - - -/* OSC.PLLCTRL bit masks and bit positions */ -#define OSC_PLLSRC_gm 0xC0 /* Clock Source group mask. */ -#define OSC_PLLSRC_gp 6 /* Clock Source group position. */ -#define OSC_PLLSRC0_bm (1<<6) /* Clock Source bit 0 mask. */ -#define OSC_PLLSRC0_bp 6 /* Clock Source bit 0 position. */ -#define OSC_PLLSRC1_bm (1<<7) /* Clock Source bit 1 mask. */ -#define OSC_PLLSRC1_bp 7 /* Clock Source bit 1 position. */ - -#define OSC_PLLFAC_gm 0x1F /* Multiplication Factor group mask. */ -#define OSC_PLLFAC_gp 0 /* Multiplication Factor group position. */ -#define OSC_PLLFAC0_bm (1<<0) /* Multiplication Factor bit 0 mask. */ -#define OSC_PLLFAC0_bp 0 /* Multiplication Factor bit 0 position. */ -#define OSC_PLLFAC1_bm (1<<1) /* Multiplication Factor bit 1 mask. */ -#define OSC_PLLFAC1_bp 1 /* Multiplication Factor bit 1 position. */ -#define OSC_PLLFAC2_bm (1<<2) /* Multiplication Factor bit 2 mask. */ -#define OSC_PLLFAC2_bp 2 /* Multiplication Factor bit 2 position. */ -#define OSC_PLLFAC3_bm (1<<3) /* Multiplication Factor bit 3 mask. */ -#define OSC_PLLFAC3_bp 3 /* Multiplication Factor bit 3 position. */ -#define OSC_PLLFAC4_bm (1<<4) /* Multiplication Factor bit 4 mask. */ -#define OSC_PLLFAC4_bp 4 /* Multiplication Factor bit 4 position. */ - - -/* OSC.DFLLCTRL bit masks and bit positions */ -#define OSC_RC32MCREF_bm 0x02 /* 32MHz Calibration Reference bit mask. */ -#define OSC_RC32MCREF_bp 1 /* 32MHz Calibration Reference bit position. */ - -#define OSC_RC2MCREF_bm 0x01 /* 2MHz Calibration Reference bit mask. */ -#define OSC_RC2MCREF_bp 0 /* 2MHz Calibration Reference bit position. */ - - -/* DFLL - DFLL */ -/* DFLL.CTRL bit masks and bit positions */ -#define DFLL_ENABLE_bm 0x01 /* DFLL Enable bit mask. */ -#define DFLL_ENABLE_bp 0 /* DFLL Enable bit position. */ - - -/* DFLL.CALA bit masks and bit positions */ -#define DFLL_CALL_gm 0x7F /* DFLL Calibration bits [6:0] group mask. */ -#define DFLL_CALL_gp 0 /* DFLL Calibration bits [6:0] group position. */ -#define DFLL_CALL0_bm (1<<0) /* DFLL Calibration bits [6:0] bit 0 mask. */ -#define DFLL_CALL0_bp 0 /* DFLL Calibration bits [6:0] bit 0 position. */ -#define DFLL_CALL1_bm (1<<1) /* DFLL Calibration bits [6:0] bit 1 mask. */ -#define DFLL_CALL1_bp 1 /* DFLL Calibration bits [6:0] bit 1 position. */ -#define DFLL_CALL2_bm (1<<2) /* DFLL Calibration bits [6:0] bit 2 mask. */ -#define DFLL_CALL2_bp 2 /* DFLL Calibration bits [6:0] bit 2 position. */ -#define DFLL_CALL3_bm (1<<3) /* DFLL Calibration bits [6:0] bit 3 mask. */ -#define DFLL_CALL3_bp 3 /* DFLL Calibration bits [6:0] bit 3 position. */ -#define DFLL_CALL4_bm (1<<4) /* DFLL Calibration bits [6:0] bit 4 mask. */ -#define DFLL_CALL4_bp 4 /* DFLL Calibration bits [6:0] bit 4 position. */ -#define DFLL_CALL5_bm (1<<5) /* DFLL Calibration bits [6:0] bit 5 mask. */ -#define DFLL_CALL5_bp 5 /* DFLL Calibration bits [6:0] bit 5 position. */ -#define DFLL_CALL6_bm (1<<6) /* DFLL Calibration bits [6:0] bit 6 mask. */ -#define DFLL_CALL6_bp 6 /* DFLL Calibration bits [6:0] bit 6 position. */ - - -/* DFLL.CALB bit masks and bit positions */ -#define DFLL_CALH_gm 0x3F /* DFLL Calibration bits [12:7] group mask. */ -#define DFLL_CALH_gp 0 /* DFLL Calibration bits [12:7] group position. */ -#define DFLL_CALH0_bm (1<<0) /* DFLL Calibration bits [12:7] bit 0 mask. */ -#define DFLL_CALH0_bp 0 /* DFLL Calibration bits [12:7] bit 0 position. */ -#define DFLL_CALH1_bm (1<<1) /* DFLL Calibration bits [12:7] bit 1 mask. */ -#define DFLL_CALH1_bp 1 /* DFLL Calibration bits [12:7] bit 1 position. */ -#define DFLL_CALH2_bm (1<<2) /* DFLL Calibration bits [12:7] bit 2 mask. */ -#define DFLL_CALH2_bp 2 /* DFLL Calibration bits [12:7] bit 2 position. */ -#define DFLL_CALH3_bm (1<<3) /* DFLL Calibration bits [12:7] bit 3 mask. */ -#define DFLL_CALH3_bp 3 /* DFLL Calibration bits [12:7] bit 3 position. */ -#define DFLL_CALH4_bm (1<<4) /* DFLL Calibration bits [12:7] bit 4 mask. */ -#define DFLL_CALH4_bp 4 /* DFLL Calibration bits [12:7] bit 4 position. */ -#define DFLL_CALH5_bm (1<<5) /* DFLL Calibration bits [12:7] bit 5 mask. */ -#define DFLL_CALH5_bp 5 /* DFLL Calibration bits [12:7] bit 5 position. */ - - -/* RST - Reset */ -/* RST.STATUS bit masks and bit positions */ -#define RST_SDRF_bm 0x40 /* Spike Detection Reset Flag bit mask. */ -#define RST_SDRF_bp 6 /* Spike Detection Reset Flag bit position. */ - -#define RST_SRF_bm 0x20 /* Software Reset Flag bit mask. */ -#define RST_SRF_bp 5 /* Software Reset Flag bit position. */ - -#define RST_PDIRF_bm 0x10 /* Programming and Debug Interface Interface Reset Flag bit mask. */ -#define RST_PDIRF_bp 4 /* Programming and Debug Interface Interface Reset Flag bit position. */ - -#define RST_WDRF_bm 0x08 /* Watchdog Reset Flag bit mask. */ -#define RST_WDRF_bp 3 /* Watchdog Reset Flag bit position. */ - -#define RST_BORF_bm 0x04 /* Brown-out Reset Flag bit mask. */ -#define RST_BORF_bp 2 /* Brown-out Reset Flag bit position. */ - -#define RST_EXTRF_bm 0x02 /* External Reset Flag bit mask. */ -#define RST_EXTRF_bp 1 /* External Reset Flag bit position. */ - -#define RST_PORF_bm 0x01 /* Power-on Reset Flag bit mask. */ -#define RST_PORF_bp 0 /* Power-on Reset Flag bit position. */ - - -/* RST.CTRL bit masks and bit positions */ -#define RST_SWRST_bm 0x01 /* Software Reset bit mask. */ -#define RST_SWRST_bp 0 /* Software Reset bit position. */ - - -/* WDT - Watch-Dog Timer */ -/* WDT.CTRL bit masks and bit positions */ -#define WDT_PER_gm 0x3C /* Period group mask. */ -#define WDT_PER_gp 2 /* Period group position. */ -#define WDT_PER0_bm (1<<2) /* Period bit 0 mask. */ -#define WDT_PER0_bp 2 /* Period bit 0 position. */ -#define WDT_PER1_bm (1<<3) /* Period bit 1 mask. */ -#define WDT_PER1_bp 3 /* Period bit 1 position. */ -#define WDT_PER2_bm (1<<4) /* Period bit 2 mask. */ -#define WDT_PER2_bp 4 /* Period bit 2 position. */ -#define WDT_PER3_bm (1<<5) /* Period bit 3 mask. */ -#define WDT_PER3_bp 5 /* Period bit 3 position. */ - -#define WDT_ENABLE_bm 0x02 /* Enable bit mask. */ -#define WDT_ENABLE_bp 1 /* Enable bit position. */ - -#define WDT_CEN_bm 0x01 /* Change Enable bit mask. */ -#define WDT_CEN_bp 0 /* Change Enable bit position. */ - - -/* WDT.WINCTRL bit masks and bit positions */ -#define WDT_WPER_gm 0x3C /* Windowed Mode Period group mask. */ -#define WDT_WPER_gp 2 /* Windowed Mode Period group position. */ -#define WDT_WPER0_bm (1<<2) /* Windowed Mode Period bit 0 mask. */ -#define WDT_WPER0_bp 2 /* Windowed Mode Period bit 0 position. */ -#define WDT_WPER1_bm (1<<3) /* Windowed Mode Period bit 1 mask. */ -#define WDT_WPER1_bp 3 /* Windowed Mode Period bit 1 position. */ -#define WDT_WPER2_bm (1<<4) /* Windowed Mode Period bit 2 mask. */ -#define WDT_WPER2_bp 4 /* Windowed Mode Period bit 2 position. */ -#define WDT_WPER3_bm (1<<5) /* Windowed Mode Period bit 3 mask. */ -#define WDT_WPER3_bp 5 /* Windowed Mode Period bit 3 position. */ - -#define WDT_WEN_bm 0x02 /* Windowed Mode Enable bit mask. */ -#define WDT_WEN_bp 1 /* Windowed Mode Enable bit position. */ - -#define WDT_WCEN_bm 0x01 /* Windowed Mode Change Enable bit mask. */ -#define WDT_WCEN_bp 0 /* Windowed Mode Change Enable bit position. */ - - -/* WDT.STATUS bit masks and bit positions */ -#define WDT_SYNCBUSY_bm 0x01 /* Syncronization busy bit mask. */ -#define WDT_SYNCBUSY_bp 0 /* Syncronization busy bit position. */ - - -/* MCU - MCU Control */ -/* MCU.MCUCR bit masks and bit positions */ -#define MCU_JTAGD_bm 0x01 /* JTAG Disable bit mask. */ -#define MCU_JTAGD_bp 0 /* JTAG Disable bit position. */ - - -/* MCU.EVSYSLOCK bit masks and bit positions */ -#define MCU_EVSYS1LOCK_bm 0x10 /* Event Channel 4-7 Lock bit mask. */ -#define MCU_EVSYS1LOCK_bp 4 /* Event Channel 4-7 Lock bit position. */ - -#define MCU_EVSYS0LOCK_bm 0x01 /* Event Channel 0-3 Lock bit mask. */ -#define MCU_EVSYS0LOCK_bp 0 /* Event Channel 0-3 Lock bit position. */ - - -/* MCU.AWEXLOCK bit masks and bit positions */ -#define MCU_AWEXELOCK_bm 0x04 /* AWeX on T/C E0 Lock bit mask. */ -#define MCU_AWEXELOCK_bp 2 /* AWeX on T/C E0 Lock bit position. */ - -#define MCU_AWEXCLOCK_bm 0x01 /* AWeX on T/C C0 Lock bit mask. */ -#define MCU_AWEXCLOCK_bp 0 /* AWeX on T/C C0 Lock bit position. */ - - -/* PMIC - Programmable Multi-level Interrupt Controller */ -/* PMIC.STATUS bit masks and bit positions */ -#define PMIC_NMIEX_bm 0x80 /* Non-maskable Interrupt Executing bit mask. */ -#define PMIC_NMIEX_bp 7 /* Non-maskable Interrupt Executing bit position. */ - -#define PMIC_HILVLEX_bm 0x04 /* High Level Interrupt Executing bit mask. */ -#define PMIC_HILVLEX_bp 2 /* High Level Interrupt Executing bit position. */ - -#define PMIC_MEDLVLEX_bm 0x02 /* Medium Level Interrupt Executing bit mask. */ -#define PMIC_MEDLVLEX_bp 1 /* Medium Level Interrupt Executing bit position. */ - -#define PMIC_LOLVLEX_bm 0x01 /* Low Level Interrupt Executing bit mask. */ -#define PMIC_LOLVLEX_bp 0 /* Low Level Interrupt Executing bit position. */ - - -/* PMIC.CTRL bit masks and bit positions */ -#define PMIC_RREN_bm 0x80 /* Round-Robin Priority Enable bit mask. */ -#define PMIC_RREN_bp 7 /* Round-Robin Priority Enable bit position. */ - -#define PMIC_IVSEL_bm 0x40 /* Interrupt Vector Select bit mask. */ -#define PMIC_IVSEL_bp 6 /* Interrupt Vector Select bit position. */ - -#define PMIC_HILVLEN_bm 0x04 /* High Level Enable bit mask. */ -#define PMIC_HILVLEN_bp 2 /* High Level Enable bit position. */ - -#define PMIC_MEDLVLEN_bm 0x02 /* Medium Level Enable bit mask. */ -#define PMIC_MEDLVLEN_bp 1 /* Medium Level Enable bit position. */ - -#define PMIC_LOLVLEN_bm 0x01 /* Low Level Enable bit mask. */ -#define PMIC_LOLVLEN_bp 0 /* Low Level Enable bit position. */ - - -/* DMA - DMA Controller */ -/* DMA_CH.CTRLA bit masks and bit positions */ -#define DMA_CH_ENABLE_bm 0x80 /* Channel Enable bit mask. */ -#define DMA_CH_ENABLE_bp 7 /* Channel Enable bit position. */ - -#define DMA_CH_RESET_bm 0x40 /* Channel Software Reset bit mask. */ -#define DMA_CH_RESET_bp 6 /* Channel Software Reset bit position. */ - -#define DMA_CH_REPEAT_bm 0x20 /* Channel Repeat Mode bit mask. */ -#define DMA_CH_REPEAT_bp 5 /* Channel Repeat Mode bit position. */ - -#define DMA_CH_TRFREQ_bm 0x10 /* Channel Transfer Request bit mask. */ -#define DMA_CH_TRFREQ_bp 4 /* Channel Transfer Request bit position. */ - -#define DMA_CH_SINGLE_bm 0x04 /* Channel Single Shot Data Transfer bit mask. */ -#define DMA_CH_SINGLE_bp 2 /* Channel Single Shot Data Transfer bit position. */ - -#define DMA_CH_BURSTLEN_gm 0x03 /* Channel Transfer Mode group mask. */ -#define DMA_CH_BURSTLEN_gp 0 /* Channel Transfer Mode group position. */ -#define DMA_CH_BURSTLEN0_bm (1<<0) /* Channel Transfer Mode bit 0 mask. */ -#define DMA_CH_BURSTLEN0_bp 0 /* Channel Transfer Mode bit 0 position. */ -#define DMA_CH_BURSTLEN1_bm (1<<1) /* Channel Transfer Mode bit 1 mask. */ -#define DMA_CH_BURSTLEN1_bp 1 /* Channel Transfer Mode bit 1 position. */ - - -/* DMA_CH.CTRLB bit masks and bit positions */ -#define DMA_CH_CHBUSY_bm 0x80 /* Block Transfer Busy bit mask. */ -#define DMA_CH_CHBUSY_bp 7 /* Block Transfer Busy bit position. */ - -#define DMA_CH_CHPEND_bm 0x40 /* Block Transfer Pending bit mask. */ -#define DMA_CH_CHPEND_bp 6 /* Block Transfer Pending bit position. */ - -#define DMA_CH_ERRIF_bm 0x20 /* Block Transfer Error Interrupt Flag bit mask. */ -#define DMA_CH_ERRIF_bp 5 /* Block Transfer Error Interrupt Flag bit position. */ - -#define DMA_CH_TRNIF_bm 0x10 /* Transaction Complete Interrup Flag bit mask. */ -#define DMA_CH_TRNIF_bp 4 /* Transaction Complete Interrup Flag bit position. */ - -#define DMA_CH_ERRINTLVL_gm 0x0C /* Transfer Error Interrupt Level group mask. */ -#define DMA_CH_ERRINTLVL_gp 2 /* Transfer Error Interrupt Level group position. */ -#define DMA_CH_ERRINTLVL0_bm (1<<2) /* Transfer Error Interrupt Level bit 0 mask. */ -#define DMA_CH_ERRINTLVL0_bp 2 /* Transfer Error Interrupt Level bit 0 position. */ -#define DMA_CH_ERRINTLVL1_bm (1<<3) /* Transfer Error Interrupt Level bit 1 mask. */ -#define DMA_CH_ERRINTLVL1_bp 3 /* Transfer Error Interrupt Level bit 1 position. */ - -#define DMA_CH_TRNINTLVL_gm 0x03 /* Transaction Complete Interrupt Level group mask. */ -#define DMA_CH_TRNINTLVL_gp 0 /* Transaction Complete Interrupt Level group position. */ -#define DMA_CH_TRNINTLVL0_bm (1<<0) /* Transaction Complete Interrupt Level bit 0 mask. */ -#define DMA_CH_TRNINTLVL0_bp 0 /* Transaction Complete Interrupt Level bit 0 position. */ -#define DMA_CH_TRNINTLVL1_bm (1<<1) /* Transaction Complete Interrupt Level bit 1 mask. */ -#define DMA_CH_TRNINTLVL1_bp 1 /* Transaction Complete Interrupt Level bit 1 position. */ - - -/* DMA_CH.ADDRCTRL bit masks and bit positions */ -#define DMA_CH_SRCRELOAD_gm 0xC0 /* Channel Source Address Reload group mask. */ -#define DMA_CH_SRCRELOAD_gp 6 /* Channel Source Address Reload group position. */ -#define DMA_CH_SRCRELOAD0_bm (1<<6) /* Channel Source Address Reload bit 0 mask. */ -#define DMA_CH_SRCRELOAD0_bp 6 /* Channel Source Address Reload bit 0 position. */ -#define DMA_CH_SRCRELOAD1_bm (1<<7) /* Channel Source Address Reload bit 1 mask. */ -#define DMA_CH_SRCRELOAD1_bp 7 /* Channel Source Address Reload bit 1 position. */ - -#define DMA_CH_SRCDIR_gm 0x30 /* Channel Source Address Mode group mask. */ -#define DMA_CH_SRCDIR_gp 4 /* Channel Source Address Mode group position. */ -#define DMA_CH_SRCDIR0_bm (1<<4) /* Channel Source Address Mode bit 0 mask. */ -#define DMA_CH_SRCDIR0_bp 4 /* Channel Source Address Mode bit 0 position. */ -#define DMA_CH_SRCDIR1_bm (1<<5) /* Channel Source Address Mode bit 1 mask. */ -#define DMA_CH_SRCDIR1_bp 5 /* Channel Source Address Mode bit 1 position. */ - -#define DMA_CH_DESTRELOAD_gm 0x0C /* Channel Destination Address Reload group mask. */ -#define DMA_CH_DESTRELOAD_gp 2 /* Channel Destination Address Reload group position. */ -#define DMA_CH_DESTRELOAD0_bm (1<<2) /* Channel Destination Address Reload bit 0 mask. */ -#define DMA_CH_DESTRELOAD0_bp 2 /* Channel Destination Address Reload bit 0 position. */ -#define DMA_CH_DESTRELOAD1_bm (1<<3) /* Channel Destination Address Reload bit 1 mask. */ -#define DMA_CH_DESTRELOAD1_bp 3 /* Channel Destination Address Reload bit 1 position. */ - -#define DMA_CH_DESTDIR_gm 0x03 /* Channel Destination Address Mode group mask. */ -#define DMA_CH_DESTDIR_gp 0 /* Channel Destination Address Mode group position. */ -#define DMA_CH_DESTDIR0_bm (1<<0) /* Channel Destination Address Mode bit 0 mask. */ -#define DMA_CH_DESTDIR0_bp 0 /* Channel Destination Address Mode bit 0 position. */ -#define DMA_CH_DESTDIR1_bm (1<<1) /* Channel Destination Address Mode bit 1 mask. */ -#define DMA_CH_DESTDIR1_bp 1 /* Channel Destination Address Mode bit 1 position. */ - - -/* DMA_CH.TRIGSRC bit masks and bit positions */ -#define DMA_CH_TRIGSRC_gm 0xFF /* Channel Trigger Source group mask. */ -#define DMA_CH_TRIGSRC_gp 0 /* Channel Trigger Source group position. */ -#define DMA_CH_TRIGSRC0_bm (1<<0) /* Channel Trigger Source bit 0 mask. */ -#define DMA_CH_TRIGSRC0_bp 0 /* Channel Trigger Source bit 0 position. */ -#define DMA_CH_TRIGSRC1_bm (1<<1) /* Channel Trigger Source bit 1 mask. */ -#define DMA_CH_TRIGSRC1_bp 1 /* Channel Trigger Source bit 1 position. */ -#define DMA_CH_TRIGSRC2_bm (1<<2) /* Channel Trigger Source bit 2 mask. */ -#define DMA_CH_TRIGSRC2_bp 2 /* Channel Trigger Source bit 2 position. */ -#define DMA_CH_TRIGSRC3_bm (1<<3) /* Channel Trigger Source bit 3 mask. */ -#define DMA_CH_TRIGSRC3_bp 3 /* Channel Trigger Source bit 3 position. */ -#define DMA_CH_TRIGSRC4_bm (1<<4) /* Channel Trigger Source bit 4 mask. */ -#define DMA_CH_TRIGSRC4_bp 4 /* Channel Trigger Source bit 4 position. */ -#define DMA_CH_TRIGSRC5_bm (1<<5) /* Channel Trigger Source bit 5 mask. */ -#define DMA_CH_TRIGSRC5_bp 5 /* Channel Trigger Source bit 5 position. */ -#define DMA_CH_TRIGSRC6_bm (1<<6) /* Channel Trigger Source bit 6 mask. */ -#define DMA_CH_TRIGSRC6_bp 6 /* Channel Trigger Source bit 6 position. */ -#define DMA_CH_TRIGSRC7_bm (1<<7) /* Channel Trigger Source bit 7 mask. */ -#define DMA_CH_TRIGSRC7_bp 7 /* Channel Trigger Source bit 7 position. */ - - -/* DMA.CTRL bit masks and bit positions */ -#define DMA_ENABLE_bm 0x80 /* Enable bit mask. */ -#define DMA_ENABLE_bp 7 /* Enable bit position. */ - -#define DMA_RESET_bm 0x40 /* Software Reset bit mask. */ -#define DMA_RESET_bp 6 /* Software Reset bit position. */ - -#define DMA_DBUFMODE_gm 0x0C /* Double Buffering Mode group mask. */ -#define DMA_DBUFMODE_gp 2 /* Double Buffering Mode group position. */ -#define DMA_DBUFMODE0_bm (1<<2) /* Double Buffering Mode bit 0 mask. */ -#define DMA_DBUFMODE0_bp 2 /* Double Buffering Mode bit 0 position. */ -#define DMA_DBUFMODE1_bm (1<<3) /* Double Buffering Mode bit 1 mask. */ -#define DMA_DBUFMODE1_bp 3 /* Double Buffering Mode bit 1 position. */ - -#define DMA_PRIMODE_gm 0x03 /* Channel Priority Mode group mask. */ -#define DMA_PRIMODE_gp 0 /* Channel Priority Mode group position. */ -#define DMA_PRIMODE0_bm (1<<0) /* Channel Priority Mode bit 0 mask. */ -#define DMA_PRIMODE0_bp 0 /* Channel Priority Mode bit 0 position. */ -#define DMA_PRIMODE1_bm (1<<1) /* Channel Priority Mode bit 1 mask. */ -#define DMA_PRIMODE1_bp 1 /* Channel Priority Mode bit 1 position. */ - - -/* DMA.INTFLAGS bit masks and bit positions */ -#define DMA_CH3ERRIF_bm 0x80 /* Channel 3 Block Transfer Error Interrupt Flag bit mask. */ -#define DMA_CH3ERRIF_bp 7 /* Channel 3 Block Transfer Error Interrupt Flag bit position. */ - -#define DMA_CH2ERRIF_bm 0x40 /* Channel 2 Block Transfer Error Interrupt Flag bit mask. */ -#define DMA_CH2ERRIF_bp 6 /* Channel 2 Block Transfer Error Interrupt Flag bit position. */ - -#define DMA_CH1ERRIF_bm 0x20 /* Channel 1 Block Transfer Error Interrupt Flag bit mask. */ -#define DMA_CH1ERRIF_bp 5 /* Channel 1 Block Transfer Error Interrupt Flag bit position. */ - -#define DMA_CH0ERRIF_bm 0x10 /* Channel 0 Block Transfer Error Interrupt Flag bit mask. */ -#define DMA_CH0ERRIF_bp 4 /* Channel 0 Block Transfer Error Interrupt Flag bit position. */ - -#define DMA_CH3TRNIF_bm 0x08 /* Channel 3 Transaction Complete Interrupt Flag bit mask. */ -#define DMA_CH3TRNIF_bp 3 /* Channel 3 Transaction Complete Interrupt Flag bit position. */ - -#define DMA_CH2TRNIF_bm 0x04 /* Channel 2 Transaction Complete Interrupt Flag bit mask. */ -#define DMA_CH2TRNIF_bp 2 /* Channel 2 Transaction Complete Interrupt Flag bit position. */ - -#define DMA_CH1TRNIF_bm 0x02 /* Channel 1 Transaction Complete Interrupt Flag bit mask. */ -#define DMA_CH1TRNIF_bp 1 /* Channel 1 Transaction Complete Interrupt Flag bit position. */ - -#define DMA_CH0TRNIF_bm 0x01 /* Channel 0 Transaction Complete Interrupt Flag bit mask. */ -#define DMA_CH0TRNIF_bp 0 /* Channel 0 Transaction Complete Interrupt Flag bit position. */ - - -/* DMA.STATUS bit masks and bit positions */ -#define DMA_CH3BUSY_bm 0x80 /* Channel 3 Block Transfer Busy bit mask. */ -#define DMA_CH3BUSY_bp 7 /* Channel 3 Block Transfer Busy bit position. */ - -#define DMA_CH2BUSY_bm 0x40 /* Channel 2 Block Transfer Busy bit mask. */ -#define DMA_CH2BUSY_bp 6 /* Channel 2 Block Transfer Busy bit position. */ - -#define DMA_CH1BUSY_bm 0x20 /* Channel 1 Block Transfer Busy bit mask. */ -#define DMA_CH1BUSY_bp 5 /* Channel 1 Block Transfer Busy bit position. */ - -#define DMA_CH0BUSY_bm 0x10 /* Channel 0 Block Transfer Busy bit mask. */ -#define DMA_CH0BUSY_bp 4 /* Channel 0 Block Transfer Busy bit position. */ - -#define DMA_CH3PEND_bm 0x08 /* Channel 3 Block Transfer Pending bit mask. */ -#define DMA_CH3PEND_bp 3 /* Channel 3 Block Transfer Pending bit position. */ - -#define DMA_CH2PEND_bm 0x04 /* Channel 2 Block Transfer Pending bit mask. */ -#define DMA_CH2PEND_bp 2 /* Channel 2 Block Transfer Pending bit position. */ - -#define DMA_CH1PEND_bm 0x02 /* Channel 1 Block Transfer Pending bit mask. */ -#define DMA_CH1PEND_bp 1 /* Channel 1 Block Transfer Pending bit position. */ - -#define DMA_CH0PEND_bm 0x01 /* Channel 0 Block Transfer Pending bit mask. */ -#define DMA_CH0PEND_bp 0 /* Channel 0 Block Transfer Pending bit position. */ - - -/* EVSYS - Event System */ -/* EVSYS.CH0MUX bit masks and bit positions */ -#define EVSYS_CHMUX_gm 0xFF /* Event Channel 0 Multiplexer group mask. */ -#define EVSYS_CHMUX_gp 0 /* Event Channel 0 Multiplexer group position. */ -#define EVSYS_CHMUX0_bm (1<<0) /* Event Channel 0 Multiplexer bit 0 mask. */ -#define EVSYS_CHMUX0_bp 0 /* Event Channel 0 Multiplexer bit 0 position. */ -#define EVSYS_CHMUX1_bm (1<<1) /* Event Channel 0 Multiplexer bit 1 mask. */ -#define EVSYS_CHMUX1_bp 1 /* Event Channel 0 Multiplexer bit 1 position. */ -#define EVSYS_CHMUX2_bm (1<<2) /* Event Channel 0 Multiplexer bit 2 mask. */ -#define EVSYS_CHMUX2_bp 2 /* Event Channel 0 Multiplexer bit 2 position. */ -#define EVSYS_CHMUX3_bm (1<<3) /* Event Channel 0 Multiplexer bit 3 mask. */ -#define EVSYS_CHMUX3_bp 3 /* Event Channel 0 Multiplexer bit 3 position. */ -#define EVSYS_CHMUX4_bm (1<<4) /* Event Channel 0 Multiplexer bit 4 mask. */ -#define EVSYS_CHMUX4_bp 4 /* Event Channel 0 Multiplexer bit 4 position. */ -#define EVSYS_CHMUX5_bm (1<<5) /* Event Channel 0 Multiplexer bit 5 mask. */ -#define EVSYS_CHMUX5_bp 5 /* Event Channel 0 Multiplexer bit 5 position. */ -#define EVSYS_CHMUX6_bm (1<<6) /* Event Channel 0 Multiplexer bit 6 mask. */ -#define EVSYS_CHMUX6_bp 6 /* Event Channel 0 Multiplexer bit 6 position. */ -#define EVSYS_CHMUX7_bm (1<<7) /* Event Channel 0 Multiplexer bit 7 mask. */ -#define EVSYS_CHMUX7_bp 7 /* Event Channel 0 Multiplexer bit 7 position. */ - - -/* EVSYS.CH1MUX bit masks and bit positions */ -/* EVSYS_CHMUX_gm Predefined. */ -/* EVSYS_CHMUX_gp Predefined. */ -/* EVSYS_CHMUX0_bm Predefined. */ -/* EVSYS_CHMUX0_bp Predefined. */ -/* EVSYS_CHMUX1_bm Predefined. */ -/* EVSYS_CHMUX1_bp Predefined. */ -/* EVSYS_CHMUX2_bm Predefined. */ -/* EVSYS_CHMUX2_bp Predefined. */ -/* EVSYS_CHMUX3_bm Predefined. */ -/* EVSYS_CHMUX3_bp Predefined. */ -/* EVSYS_CHMUX4_bm Predefined. */ -/* EVSYS_CHMUX4_bp Predefined. */ -/* EVSYS_CHMUX5_bm Predefined. */ -/* EVSYS_CHMUX5_bp Predefined. */ -/* EVSYS_CHMUX6_bm Predefined. */ -/* EVSYS_CHMUX6_bp Predefined. */ -/* EVSYS_CHMUX7_bm Predefined. */ -/* EVSYS_CHMUX7_bp Predefined. */ - - -/* EVSYS.CH2MUX bit masks and bit positions */ -/* EVSYS_CHMUX_gm Predefined. */ -/* EVSYS_CHMUX_gp Predefined. */ -/* EVSYS_CHMUX0_bm Predefined. */ -/* EVSYS_CHMUX0_bp Predefined. */ -/* EVSYS_CHMUX1_bm Predefined. */ -/* EVSYS_CHMUX1_bp Predefined. */ -/* EVSYS_CHMUX2_bm Predefined. */ -/* EVSYS_CHMUX2_bp Predefined. */ -/* EVSYS_CHMUX3_bm Predefined. */ -/* EVSYS_CHMUX3_bp Predefined. */ -/* EVSYS_CHMUX4_bm Predefined. */ -/* EVSYS_CHMUX4_bp Predefined. */ -/* EVSYS_CHMUX5_bm Predefined. */ -/* EVSYS_CHMUX5_bp Predefined. */ -/* EVSYS_CHMUX6_bm Predefined. */ -/* EVSYS_CHMUX6_bp Predefined. */ -/* EVSYS_CHMUX7_bm Predefined. */ -/* EVSYS_CHMUX7_bp Predefined. */ - - -/* EVSYS.CH3MUX bit masks and bit positions */ -/* EVSYS_CHMUX_gm Predefined. */ -/* EVSYS_CHMUX_gp Predefined. */ -/* EVSYS_CHMUX0_bm Predefined. */ -/* EVSYS_CHMUX0_bp Predefined. */ -/* EVSYS_CHMUX1_bm Predefined. */ -/* EVSYS_CHMUX1_bp Predefined. */ -/* EVSYS_CHMUX2_bm Predefined. */ -/* EVSYS_CHMUX2_bp Predefined. */ -/* EVSYS_CHMUX3_bm Predefined. */ -/* EVSYS_CHMUX3_bp Predefined. */ -/* EVSYS_CHMUX4_bm Predefined. */ -/* EVSYS_CHMUX4_bp Predefined. */ -/* EVSYS_CHMUX5_bm Predefined. */ -/* EVSYS_CHMUX5_bp Predefined. */ -/* EVSYS_CHMUX6_bm Predefined. */ -/* EVSYS_CHMUX6_bp Predefined. */ -/* EVSYS_CHMUX7_bm Predefined. */ -/* EVSYS_CHMUX7_bp Predefined. */ - - -/* EVSYS.CH4MUX bit masks and bit positions */ -/* EVSYS_CHMUX_gm Predefined. */ -/* EVSYS_CHMUX_gp Predefined. */ -/* EVSYS_CHMUX0_bm Predefined. */ -/* EVSYS_CHMUX0_bp Predefined. */ -/* EVSYS_CHMUX1_bm Predefined. */ -/* EVSYS_CHMUX1_bp Predefined. */ -/* EVSYS_CHMUX2_bm Predefined. */ -/* EVSYS_CHMUX2_bp Predefined. */ -/* EVSYS_CHMUX3_bm Predefined. */ -/* EVSYS_CHMUX3_bp Predefined. */ -/* EVSYS_CHMUX4_bm Predefined. */ -/* EVSYS_CHMUX4_bp Predefined. */ -/* EVSYS_CHMUX5_bm Predefined. */ -/* EVSYS_CHMUX5_bp Predefined. */ -/* EVSYS_CHMUX6_bm Predefined. */ -/* EVSYS_CHMUX6_bp Predefined. */ -/* EVSYS_CHMUX7_bm Predefined. */ -/* EVSYS_CHMUX7_bp Predefined. */ - - -/* EVSYS.CH5MUX bit masks and bit positions */ -/* EVSYS_CHMUX_gm Predefined. */ -/* EVSYS_CHMUX_gp Predefined. */ -/* EVSYS_CHMUX0_bm Predefined. */ -/* EVSYS_CHMUX0_bp Predefined. */ -/* EVSYS_CHMUX1_bm Predefined. */ -/* EVSYS_CHMUX1_bp Predefined. */ -/* EVSYS_CHMUX2_bm Predefined. */ -/* EVSYS_CHMUX2_bp Predefined. */ -/* EVSYS_CHMUX3_bm Predefined. */ -/* EVSYS_CHMUX3_bp Predefined. */ -/* EVSYS_CHMUX4_bm Predefined. */ -/* EVSYS_CHMUX4_bp Predefined. */ -/* EVSYS_CHMUX5_bm Predefined. */ -/* EVSYS_CHMUX5_bp Predefined. */ -/* EVSYS_CHMUX6_bm Predefined. */ -/* EVSYS_CHMUX6_bp Predefined. */ -/* EVSYS_CHMUX7_bm Predefined. */ -/* EVSYS_CHMUX7_bp Predefined. */ - - -/* EVSYS.CH6MUX bit masks and bit positions */ -/* EVSYS_CHMUX_gm Predefined. */ -/* EVSYS_CHMUX_gp Predefined. */ -/* EVSYS_CHMUX0_bm Predefined. */ -/* EVSYS_CHMUX0_bp Predefined. */ -/* EVSYS_CHMUX1_bm Predefined. */ -/* EVSYS_CHMUX1_bp Predefined. */ -/* EVSYS_CHMUX2_bm Predefined. */ -/* EVSYS_CHMUX2_bp Predefined. */ -/* EVSYS_CHMUX3_bm Predefined. */ -/* EVSYS_CHMUX3_bp Predefined. */ -/* EVSYS_CHMUX4_bm Predefined. */ -/* EVSYS_CHMUX4_bp Predefined. */ -/* EVSYS_CHMUX5_bm Predefined. */ -/* EVSYS_CHMUX5_bp Predefined. */ -/* EVSYS_CHMUX6_bm Predefined. */ -/* EVSYS_CHMUX6_bp Predefined. */ -/* EVSYS_CHMUX7_bm Predefined. */ -/* EVSYS_CHMUX7_bp Predefined. */ - - -/* EVSYS.CH7MUX bit masks and bit positions */ -/* EVSYS_CHMUX_gm Predefined. */ -/* EVSYS_CHMUX_gp Predefined. */ -/* EVSYS_CHMUX0_bm Predefined. */ -/* EVSYS_CHMUX0_bp Predefined. */ -/* EVSYS_CHMUX1_bm Predefined. */ -/* EVSYS_CHMUX1_bp Predefined. */ -/* EVSYS_CHMUX2_bm Predefined. */ -/* EVSYS_CHMUX2_bp Predefined. */ -/* EVSYS_CHMUX3_bm Predefined. */ -/* EVSYS_CHMUX3_bp Predefined. */ -/* EVSYS_CHMUX4_bm Predefined. */ -/* EVSYS_CHMUX4_bp Predefined. */ -/* EVSYS_CHMUX5_bm Predefined. */ -/* EVSYS_CHMUX5_bp Predefined. */ -/* EVSYS_CHMUX6_bm Predefined. */ -/* EVSYS_CHMUX6_bp Predefined. */ -/* EVSYS_CHMUX7_bm Predefined. */ -/* EVSYS_CHMUX7_bp Predefined. */ - - -/* EVSYS.CH0CTRL bit masks and bit positions */ -#define EVSYS_QDIRM_gm 0x60 /* Quadrature Decoder Index Recognition Mode group mask. */ -#define EVSYS_QDIRM_gp 5 /* Quadrature Decoder Index Recognition Mode group position. */ -#define EVSYS_QDIRM0_bm (1<<5) /* Quadrature Decoder Index Recognition Mode bit 0 mask. */ -#define EVSYS_QDIRM0_bp 5 /* Quadrature Decoder Index Recognition Mode bit 0 position. */ -#define EVSYS_QDIRM1_bm (1<<6) /* Quadrature Decoder Index Recognition Mode bit 1 mask. */ -#define EVSYS_QDIRM1_bp 6 /* Quadrature Decoder Index Recognition Mode bit 1 position. */ - -#define EVSYS_QDIEN_bm 0x10 /* Quadrature Decoder Index Enable bit mask. */ -#define EVSYS_QDIEN_bp 4 /* Quadrature Decoder Index Enable bit position. */ - -#define EVSYS_QDEN_bm 0x08 /* Quadrature Decoder Enable bit mask. */ -#define EVSYS_QDEN_bp 3 /* Quadrature Decoder Enable bit position. */ - -#define EVSYS_DIGFILT_gm 0x07 /* Digital Filter group mask. */ -#define EVSYS_DIGFILT_gp 0 /* Digital Filter group position. */ -#define EVSYS_DIGFILT0_bm (1<<0) /* Digital Filter bit 0 mask. */ -#define EVSYS_DIGFILT0_bp 0 /* Digital Filter bit 0 position. */ -#define EVSYS_DIGFILT1_bm (1<<1) /* Digital Filter bit 1 mask. */ -#define EVSYS_DIGFILT1_bp 1 /* Digital Filter bit 1 position. */ -#define EVSYS_DIGFILT2_bm (1<<2) /* Digital Filter bit 2 mask. */ -#define EVSYS_DIGFILT2_bp 2 /* Digital Filter bit 2 position. */ - - -/* EVSYS.CH1CTRL bit masks and bit positions */ -/* EVSYS_DIGFILT_gm Predefined. */ -/* EVSYS_DIGFILT_gp Predefined. */ -/* EVSYS_DIGFILT0_bm Predefined. */ -/* EVSYS_DIGFILT0_bp Predefined. */ -/* EVSYS_DIGFILT1_bm Predefined. */ -/* EVSYS_DIGFILT1_bp Predefined. */ -/* EVSYS_DIGFILT2_bm Predefined. */ -/* EVSYS_DIGFILT2_bp Predefined. */ - - -/* EVSYS.CH2CTRL bit masks and bit positions */ -/* EVSYS_QDIRM_gm Predefined. */ -/* EVSYS_QDIRM_gp Predefined. */ -/* EVSYS_QDIRM0_bm Predefined. */ -/* EVSYS_QDIRM0_bp Predefined. */ -/* EVSYS_QDIRM1_bm Predefined. */ -/* EVSYS_QDIRM1_bp Predefined. */ - -/* EVSYS_QDIEN_bm Predefined. */ -/* EVSYS_QDIEN_bp Predefined. */ - -/* EVSYS_QDEN_bm Predefined. */ -/* EVSYS_QDEN_bp Predefined. */ - -/* EVSYS_DIGFILT_gm Predefined. */ -/* EVSYS_DIGFILT_gp Predefined. */ -/* EVSYS_DIGFILT0_bm Predefined. */ -/* EVSYS_DIGFILT0_bp Predefined. */ -/* EVSYS_DIGFILT1_bm Predefined. */ -/* EVSYS_DIGFILT1_bp Predefined. */ -/* EVSYS_DIGFILT2_bm Predefined. */ -/* EVSYS_DIGFILT2_bp Predefined. */ - - -/* EVSYS.CH3CTRL bit masks and bit positions */ -/* EVSYS_DIGFILT_gm Predefined. */ -/* EVSYS_DIGFILT_gp Predefined. */ -/* EVSYS_DIGFILT0_bm Predefined. */ -/* EVSYS_DIGFILT0_bp Predefined. */ -/* EVSYS_DIGFILT1_bm Predefined. */ -/* EVSYS_DIGFILT1_bp Predefined. */ -/* EVSYS_DIGFILT2_bm Predefined. */ -/* EVSYS_DIGFILT2_bp Predefined. */ - - -/* EVSYS.CH4CTRL bit masks and bit positions */ -/* EVSYS_QDIRM_gm Predefined. */ -/* EVSYS_QDIRM_gp Predefined. */ -/* EVSYS_QDIRM0_bm Predefined. */ -/* EVSYS_QDIRM0_bp Predefined. */ -/* EVSYS_QDIRM1_bm Predefined. */ -/* EVSYS_QDIRM1_bp Predefined. */ - -/* EVSYS_QDIEN_bm Predefined. */ -/* EVSYS_QDIEN_bp Predefined. */ - -/* EVSYS_QDEN_bm Predefined. */ -/* EVSYS_QDEN_bp Predefined. */ - -/* EVSYS_DIGFILT_gm Predefined. */ -/* EVSYS_DIGFILT_gp Predefined. */ -/* EVSYS_DIGFILT0_bm Predefined. */ -/* EVSYS_DIGFILT0_bp Predefined. */ -/* EVSYS_DIGFILT1_bm Predefined. */ -/* EVSYS_DIGFILT1_bp Predefined. */ -/* EVSYS_DIGFILT2_bm Predefined. */ -/* EVSYS_DIGFILT2_bp Predefined. */ - - -/* EVSYS.CH5CTRL bit masks and bit positions */ -/* EVSYS_DIGFILT_gm Predefined. */ -/* EVSYS_DIGFILT_gp Predefined. */ -/* EVSYS_DIGFILT0_bm Predefined. */ -/* EVSYS_DIGFILT0_bp Predefined. */ -/* EVSYS_DIGFILT1_bm Predefined. */ -/* EVSYS_DIGFILT1_bp Predefined. */ -/* EVSYS_DIGFILT2_bm Predefined. */ -/* EVSYS_DIGFILT2_bp Predefined. */ - - -/* EVSYS.CH6CTRL bit masks and bit positions */ -/* EVSYS_DIGFILT_gm Predefined. */ -/* EVSYS_DIGFILT_gp Predefined. */ -/* EVSYS_DIGFILT0_bm Predefined. */ -/* EVSYS_DIGFILT0_bp Predefined. */ -/* EVSYS_DIGFILT1_bm Predefined. */ -/* EVSYS_DIGFILT1_bp Predefined. */ -/* EVSYS_DIGFILT2_bm Predefined. */ -/* EVSYS_DIGFILT2_bp Predefined. */ - - -/* EVSYS.CH7CTRL bit masks and bit positions */ -/* EVSYS_DIGFILT_gm Predefined. */ -/* EVSYS_DIGFILT_gp Predefined. */ -/* EVSYS_DIGFILT0_bm Predefined. */ -/* EVSYS_DIGFILT0_bp Predefined. */ -/* EVSYS_DIGFILT1_bm Predefined. */ -/* EVSYS_DIGFILT1_bp Predefined. */ -/* EVSYS_DIGFILT2_bm Predefined. */ -/* EVSYS_DIGFILT2_bp Predefined. */ - - -/* NVM - Non Volatile Memory Controller */ -/* NVM.CMD bit masks and bit positions */ -#define NVM_CMD_gm 0xFF /* Command group mask. */ -#define NVM_CMD_gp 0 /* Command group position. */ -#define NVM_CMD0_bm (1<<0) /* Command bit 0 mask. */ -#define NVM_CMD0_bp 0 /* Command bit 0 position. */ -#define NVM_CMD1_bm (1<<1) /* Command bit 1 mask. */ -#define NVM_CMD1_bp 1 /* Command bit 1 position. */ -#define NVM_CMD2_bm (1<<2) /* Command bit 2 mask. */ -#define NVM_CMD2_bp 2 /* Command bit 2 position. */ -#define NVM_CMD3_bm (1<<3) /* Command bit 3 mask. */ -#define NVM_CMD3_bp 3 /* Command bit 3 position. */ -#define NVM_CMD4_bm (1<<4) /* Command bit 4 mask. */ -#define NVM_CMD4_bp 4 /* Command bit 4 position. */ -#define NVM_CMD5_bm (1<<5) /* Command bit 5 mask. */ -#define NVM_CMD5_bp 5 /* Command bit 5 position. */ -#define NVM_CMD6_bm (1<<6) /* Command bit 6 mask. */ -#define NVM_CMD6_bp 6 /* Command bit 6 position. */ -#define NVM_CMD7_bm (1<<7) /* Command bit 7 mask. */ -#define NVM_CMD7_bp 7 /* Command bit 7 position. */ - - -/* NVM.CTRLA bit masks and bit positions */ -#define NVM_CMDEX_bm 0x01 /* Command Execute bit mask. */ -#define NVM_CMDEX_bp 0 /* Command Execute bit position. */ - - -/* NVM.CTRLB bit masks and bit positions */ -#define NVM_EEMAPEN_bm 0x08 /* EEPROM Mapping Enable bit mask. */ -#define NVM_EEMAPEN_bp 3 /* EEPROM Mapping Enable bit position. */ - -#define NVM_FPRM_bm 0x04 /* Flash Power Reduction Enable bit mask. */ -#define NVM_FPRM_bp 2 /* Flash Power Reduction Enable bit position. */ - -#define NVM_EPRM_bm 0x02 /* EEPROM Power Reduction Enable bit mask. */ -#define NVM_EPRM_bp 1 /* EEPROM Power Reduction Enable bit position. */ - -#define NVM_SPMLOCK_bm 0x01 /* SPM Lock bit mask. */ -#define NVM_SPMLOCK_bp 0 /* SPM Lock bit position. */ - - -/* NVM.INTCTRL bit masks and bit positions */ -#define NVM_SPMLVL_gm 0x0C /* SPM Interrupt Level group mask. */ -#define NVM_SPMLVL_gp 2 /* SPM Interrupt Level group position. */ -#define NVM_SPMLVL0_bm (1<<2) /* SPM Interrupt Level bit 0 mask. */ -#define NVM_SPMLVL0_bp 2 /* SPM Interrupt Level bit 0 position. */ -#define NVM_SPMLVL1_bm (1<<3) /* SPM Interrupt Level bit 1 mask. */ -#define NVM_SPMLVL1_bp 3 /* SPM Interrupt Level bit 1 position. */ - -#define NVM_EELVL_gm 0x03 /* EEPROM Interrupt Level group mask. */ -#define NVM_EELVL_gp 0 /* EEPROM Interrupt Level group position. */ -#define NVM_EELVL0_bm (1<<0) /* EEPROM Interrupt Level bit 0 mask. */ -#define NVM_EELVL0_bp 0 /* EEPROM Interrupt Level bit 0 position. */ -#define NVM_EELVL1_bm (1<<1) /* EEPROM Interrupt Level bit 1 mask. */ -#define NVM_EELVL1_bp 1 /* EEPROM Interrupt Level bit 1 position. */ - - -/* NVM.STATUS bit masks and bit positions */ -#define NVM_NVMBUSY_bm 0x80 /* Non-volatile Memory Busy bit mask. */ -#define NVM_NVMBUSY_bp 7 /* Non-volatile Memory Busy bit position. */ - -#define NVM_FBUSY_bm 0x40 /* Flash Memory Busy bit mask. */ -#define NVM_FBUSY_bp 6 /* Flash Memory Busy bit position. */ - -#define NVM_EELOAD_bm 0x02 /* EEPROM Page Buffer Active Loading bit mask. */ -#define NVM_EELOAD_bp 1 /* EEPROM Page Buffer Active Loading bit position. */ - -#define NVM_FLOAD_bm 0x01 /* Flash Page Buffer Active Loading bit mask. */ -#define NVM_FLOAD_bp 0 /* Flash Page Buffer Active Loading bit position. */ - - -/* NVM.LOCKBITS bit masks and bit positions */ -#define NVM_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ -#define NVM_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ -#define NVM_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ -#define NVM_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ -#define NVM_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ -#define NVM_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ - -#define NVM_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ -#define NVM_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ -#define NVM_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ -#define NVM_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ -#define NVM_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ -#define NVM_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ - -#define NVM_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ -#define NVM_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ -#define NVM_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ -#define NVM_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ -#define NVM_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ -#define NVM_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ - -#define NVM_LB_gm 0x03 /* Lock Bits group mask. */ -#define NVM_LB_gp 0 /* Lock Bits group position. */ -#define NVM_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ -#define NVM_LB0_bp 0 /* Lock Bits bit 0 position. */ -#define NVM_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ -#define NVM_LB1_bp 1 /* Lock Bits bit 1 position. */ - - -/* NVM_LOCKBITS.LOCKBITS bit masks and bit positions */ -#define NVM_LOCKBITS_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ -#define NVM_LOCKBITS_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ -#define NVM_LOCKBITS_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ -#define NVM_LOCKBITS_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ -#define NVM_LOCKBITS_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ -#define NVM_LOCKBITS_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ - -#define NVM_LOCKBITS_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ -#define NVM_LOCKBITS_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ -#define NVM_LOCKBITS_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ -#define NVM_LOCKBITS_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ -#define NVM_LOCKBITS_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ -#define NVM_LOCKBITS_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ - -#define NVM_LOCKBITS_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ -#define NVM_LOCKBITS_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ -#define NVM_LOCKBITS_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ -#define NVM_LOCKBITS_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ -#define NVM_LOCKBITS_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ -#define NVM_LOCKBITS_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ - -#define NVM_LOCKBITS_LB_gm 0x03 /* Lock Bits group mask. */ -#define NVM_LOCKBITS_LB_gp 0 /* Lock Bits group position. */ -#define NVM_LOCKBITS_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ -#define NVM_LOCKBITS_LB0_bp 0 /* Lock Bits bit 0 position. */ -#define NVM_LOCKBITS_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ -#define NVM_LOCKBITS_LB1_bp 1 /* Lock Bits bit 1 position. */ - - -/* NVM_FUSES.FUSEBYTE0 bit masks and bit positions */ -#define NVM_FUSES_JTAGUSERID_gm 0xFF /* JTAG User ID group mask. */ -#define NVM_FUSES_JTAGUSERID_gp 0 /* JTAG User ID group position. */ -#define NVM_FUSES_JTAGUSERID0_bm (1<<0) /* JTAG User ID bit 0 mask. */ -#define NVM_FUSES_JTAGUSERID0_bp 0 /* JTAG User ID bit 0 position. */ -#define NVM_FUSES_JTAGUSERID1_bm (1<<1) /* JTAG User ID bit 1 mask. */ -#define NVM_FUSES_JTAGUSERID1_bp 1 /* JTAG User ID bit 1 position. */ -#define NVM_FUSES_JTAGUSERID2_bm (1<<2) /* JTAG User ID bit 2 mask. */ -#define NVM_FUSES_JTAGUSERID2_bp 2 /* JTAG User ID bit 2 position. */ -#define NVM_FUSES_JTAGUSERID3_bm (1<<3) /* JTAG User ID bit 3 mask. */ -#define NVM_FUSES_JTAGUSERID3_bp 3 /* JTAG User ID bit 3 position. */ -#define NVM_FUSES_JTAGUSERID4_bm (1<<4) /* JTAG User ID bit 4 mask. */ -#define NVM_FUSES_JTAGUSERID4_bp 4 /* JTAG User ID bit 4 position. */ -#define NVM_FUSES_JTAGUSERID5_bm (1<<5) /* JTAG User ID bit 5 mask. */ -#define NVM_FUSES_JTAGUSERID5_bp 5 /* JTAG User ID bit 5 position. */ -#define NVM_FUSES_JTAGUSERID6_bm (1<<6) /* JTAG User ID bit 6 mask. */ -#define NVM_FUSES_JTAGUSERID6_bp 6 /* JTAG User ID bit 6 position. */ -#define NVM_FUSES_JTAGUSERID7_bm (1<<7) /* JTAG User ID bit 7 mask. */ -#define NVM_FUSES_JTAGUSERID7_bp 7 /* JTAG User ID bit 7 position. */ - - -/* NVM_FUSES.FUSEBYTE1 bit masks and bit positions */ -#define NVM_FUSES_WDWP_gm 0xF0 /* Watchdog Window Timeout Period group mask. */ -#define NVM_FUSES_WDWP_gp 4 /* Watchdog Window Timeout Period group position. */ -#define NVM_FUSES_WDWP0_bm (1<<4) /* Watchdog Window Timeout Period bit 0 mask. */ -#define NVM_FUSES_WDWP0_bp 4 /* Watchdog Window Timeout Period bit 0 position. */ -#define NVM_FUSES_WDWP1_bm (1<<5) /* Watchdog Window Timeout Period bit 1 mask. */ -#define NVM_FUSES_WDWP1_bp 5 /* Watchdog Window Timeout Period bit 1 position. */ -#define NVM_FUSES_WDWP2_bm (1<<6) /* Watchdog Window Timeout Period bit 2 mask. */ -#define NVM_FUSES_WDWP2_bp 6 /* Watchdog Window Timeout Period bit 2 position. */ -#define NVM_FUSES_WDWP3_bm (1<<7) /* Watchdog Window Timeout Period bit 3 mask. */ -#define NVM_FUSES_WDWP3_bp 7 /* Watchdog Window Timeout Period bit 3 position. */ - -#define NVM_FUSES_WDP_gm 0x0F /* Watchdog Timeout Period group mask. */ -#define NVM_FUSES_WDP_gp 0 /* Watchdog Timeout Period group position. */ -#define NVM_FUSES_WDP0_bm (1<<0) /* Watchdog Timeout Period bit 0 mask. */ -#define NVM_FUSES_WDP0_bp 0 /* Watchdog Timeout Period bit 0 position. */ -#define NVM_FUSES_WDP1_bm (1<<1) /* Watchdog Timeout Period bit 1 mask. */ -#define NVM_FUSES_WDP1_bp 1 /* Watchdog Timeout Period bit 1 position. */ -#define NVM_FUSES_WDP2_bm (1<<2) /* Watchdog Timeout Period bit 2 mask. */ -#define NVM_FUSES_WDP2_bp 2 /* Watchdog Timeout Period bit 2 position. */ -#define NVM_FUSES_WDP3_bm (1<<3) /* Watchdog Timeout Period bit 3 mask. */ -#define NVM_FUSES_WDP3_bp 3 /* Watchdog Timeout Period bit 3 position. */ - - -/* NVM_FUSES.FUSEBYTE2 bit masks and bit positions */ -#define NVM_FUSES_DVSDON_bm 0x80 /* Spike Detector Enable bit mask. */ -#define NVM_FUSES_DVSDON_bp 7 /* Spike Detector Enable bit position. */ - -#define NVM_FUSES_BOOTRST_bm 0x40 /* Boot Loader Section Reset Vector bit mask. */ -#define NVM_FUSES_BOOTRST_bp 6 /* Boot Loader Section Reset Vector bit position. */ - -#define NVM_FUSES_BODACT_gm 0x0C /* BOD Operation in Active Mode group mask. */ -#define NVM_FUSES_BODACT_gp 2 /* BOD Operation in Active Mode group position. */ -#define NVM_FUSES_BODACT0_bm (1<<2) /* BOD Operation in Active Mode bit 0 mask. */ -#define NVM_FUSES_BODACT0_bp 2 /* BOD Operation in Active Mode bit 0 position. */ -#define NVM_FUSES_BODACT1_bm (1<<3) /* BOD Operation in Active Mode bit 1 mask. */ -#define NVM_FUSES_BODACT1_bp 3 /* BOD Operation in Active Mode bit 1 position. */ - -#define NVM_FUSES_BODPD_gm 0x03 /* BOD Operation in Power-Down Mode group mask. */ -#define NVM_FUSES_BODPD_gp 0 /* BOD Operation in Power-Down Mode group position. */ -#define NVM_FUSES_BODPD0_bm (1<<0) /* BOD Operation in Power-Down Mode bit 0 mask. */ -#define NVM_FUSES_BODPD0_bp 0 /* BOD Operation in Power-Down Mode bit 0 position. */ -#define NVM_FUSES_BODPD1_bm (1<<1) /* BOD Operation in Power-Down Mode bit 1 mask. */ -#define NVM_FUSES_BODPD1_bp 1 /* BOD Operation in Power-Down Mode bit 1 position. */ - - -/* NVM_FUSES.FUSEBYTE4 bit masks and bit positions */ -#define NVM_FUSES_SUT_gm 0x0C /* Start-up Time group mask. */ -#define NVM_FUSES_SUT_gp 2 /* Start-up Time group position. */ -#define NVM_FUSES_SUT0_bm (1<<2) /* Start-up Time bit 0 mask. */ -#define NVM_FUSES_SUT0_bp 2 /* Start-up Time bit 0 position. */ -#define NVM_FUSES_SUT1_bm (1<<3) /* Start-up Time bit 1 mask. */ -#define NVM_FUSES_SUT1_bp 3 /* Start-up Time bit 1 position. */ - -#define NVM_FUSES_WDLOCK_bm 0x02 /* Watchdog Timer Lock bit mask. */ -#define NVM_FUSES_WDLOCK_bp 1 /* Watchdog Timer Lock bit position. */ - -#define NVM_FUSES_JTAGEN_bm 0x01 /* JTAG Interface Enable bit mask. */ -#define NVM_FUSES_JTAGEN_bp 0 /* JTAG Interface Enable bit position. */ - - -/* NVM_FUSES.FUSEBYTE5 bit masks and bit positions */ -#define NVM_FUSES_EESAVE_bm 0x08 /* Preserve EEPROM Through Chip Erase bit mask. */ -#define NVM_FUSES_EESAVE_bp 3 /* Preserve EEPROM Through Chip Erase bit position. */ - -#define NVM_FUSES_BODLVL_gm 0x07 /* Brown Out Detection Voltage Level group mask. */ -#define NVM_FUSES_BODLVL_gp 0 /* Brown Out Detection Voltage Level group position. */ -#define NVM_FUSES_BODLVL0_bm (1<<0) /* Brown Out Detection Voltage Level bit 0 mask. */ -#define NVM_FUSES_BODLVL0_bp 0 /* Brown Out Detection Voltage Level bit 0 position. */ -#define NVM_FUSES_BODLVL1_bm (1<<1) /* Brown Out Detection Voltage Level bit 1 mask. */ -#define NVM_FUSES_BODLVL1_bp 1 /* Brown Out Detection Voltage Level bit 1 position. */ -#define NVM_FUSES_BODLVL2_bm (1<<2) /* Brown Out Detection Voltage Level bit 2 mask. */ -#define NVM_FUSES_BODLVL2_bp 2 /* Brown Out Detection Voltage Level bit 2 position. */ - - -/* AC - Analog Comparator */ -/* AC.AC0CTRL bit masks and bit positions */ -#define AC_INTMODE_gm 0xC0 /* Interrupt Mode group mask. */ -#define AC_INTMODE_gp 6 /* Interrupt Mode group position. */ -#define AC_INTMODE0_bm (1<<6) /* Interrupt Mode bit 0 mask. */ -#define AC_INTMODE0_bp 6 /* Interrupt Mode bit 0 position. */ -#define AC_INTMODE1_bm (1<<7) /* Interrupt Mode bit 1 mask. */ -#define AC_INTMODE1_bp 7 /* Interrupt Mode bit 1 position. */ - -#define AC_INTLVL_gm 0x30 /* Interrupt Level group mask. */ -#define AC_INTLVL_gp 4 /* Interrupt Level group position. */ -#define AC_INTLVL0_bm (1<<4) /* Interrupt Level bit 0 mask. */ -#define AC_INTLVL0_bp 4 /* Interrupt Level bit 0 position. */ -#define AC_INTLVL1_bm (1<<5) /* Interrupt Level bit 1 mask. */ -#define AC_INTLVL1_bp 5 /* Interrupt Level bit 1 position. */ - -#define AC_HSMODE_bm 0x08 /* High-speed Mode bit mask. */ -#define AC_HSMODE_bp 3 /* High-speed Mode bit position. */ - -#define AC_HYSMODE_gm 0x06 /* Hysteresis Mode group mask. */ -#define AC_HYSMODE_gp 1 /* Hysteresis Mode group position. */ -#define AC_HYSMODE0_bm (1<<1) /* Hysteresis Mode bit 0 mask. */ -#define AC_HYSMODE0_bp 1 /* Hysteresis Mode bit 0 position. */ -#define AC_HYSMODE1_bm (1<<2) /* Hysteresis Mode bit 1 mask. */ -#define AC_HYSMODE1_bp 2 /* Hysteresis Mode bit 1 position. */ - -#define AC_ENABLE_bm 0x01 /* Enable bit mask. */ -#define AC_ENABLE_bp 0 /* Enable bit position. */ - - -/* AC.AC1CTRL bit masks and bit positions */ -/* AC_INTMODE_gm Predefined. */ -/* AC_INTMODE_gp Predefined. */ -/* AC_INTMODE0_bm Predefined. */ -/* AC_INTMODE0_bp Predefined. */ -/* AC_INTMODE1_bm Predefined. */ -/* AC_INTMODE1_bp Predefined. */ - -/* AC_INTLVL_gm Predefined. */ -/* AC_INTLVL_gp Predefined. */ -/* AC_INTLVL0_bm Predefined. */ -/* AC_INTLVL0_bp Predefined. */ -/* AC_INTLVL1_bm Predefined. */ -/* AC_INTLVL1_bp Predefined. */ - -/* AC_HSMODE_bm Predefined. */ -/* AC_HSMODE_bp Predefined. */ - -/* AC_HYSMODE_gm Predefined. */ -/* AC_HYSMODE_gp Predefined. */ -/* AC_HYSMODE0_bm Predefined. */ -/* AC_HYSMODE0_bp Predefined. */ -/* AC_HYSMODE1_bm Predefined. */ -/* AC_HYSMODE1_bp Predefined. */ - -/* AC_ENABLE_bm Predefined. */ -/* AC_ENABLE_bp Predefined. */ - - -/* AC.AC0MUXCTRL bit masks and bit positions */ -#define AC_MUXPOS_gm 0x38 /* MUX Positive Input group mask. */ -#define AC_MUXPOS_gp 3 /* MUX Positive Input group position. */ -#define AC_MUXPOS0_bm (1<<3) /* MUX Positive Input bit 0 mask. */ -#define AC_MUXPOS0_bp 3 /* MUX Positive Input bit 0 position. */ -#define AC_MUXPOS1_bm (1<<4) /* MUX Positive Input bit 1 mask. */ -#define AC_MUXPOS1_bp 4 /* MUX Positive Input bit 1 position. */ -#define AC_MUXPOS2_bm (1<<5) /* MUX Positive Input bit 2 mask. */ -#define AC_MUXPOS2_bp 5 /* MUX Positive Input bit 2 position. */ - -#define AC_MUXNEG_gm 0x07 /* MUX Negative Input group mask. */ -#define AC_MUXNEG_gp 0 /* MUX Negative Input group position. */ -#define AC_MUXNEG0_bm (1<<0) /* MUX Negative Input bit 0 mask. */ -#define AC_MUXNEG0_bp 0 /* MUX Negative Input bit 0 position. */ -#define AC_MUXNEG1_bm (1<<1) /* MUX Negative Input bit 1 mask. */ -#define AC_MUXNEG1_bp 1 /* MUX Negative Input bit 1 position. */ -#define AC_MUXNEG2_bm (1<<2) /* MUX Negative Input bit 2 mask. */ -#define AC_MUXNEG2_bp 2 /* MUX Negative Input bit 2 position. */ - - -/* AC.AC1MUXCTRL bit masks and bit positions */ -/* AC_MUXPOS_gm Predefined. */ -/* AC_MUXPOS_gp Predefined. */ -/* AC_MUXPOS0_bm Predefined. */ -/* AC_MUXPOS0_bp Predefined. */ -/* AC_MUXPOS1_bm Predefined. */ -/* AC_MUXPOS1_bp Predefined. */ -/* AC_MUXPOS2_bm Predefined. */ -/* AC_MUXPOS2_bp Predefined. */ - -/* AC_MUXNEG_gm Predefined. */ -/* AC_MUXNEG_gp Predefined. */ -/* AC_MUXNEG0_bm Predefined. */ -/* AC_MUXNEG0_bp Predefined. */ -/* AC_MUXNEG1_bm Predefined. */ -/* AC_MUXNEG1_bp Predefined. */ -/* AC_MUXNEG2_bm Predefined. */ -/* AC_MUXNEG2_bp Predefined. */ - - -/* AC.CTRLA bit masks and bit positions */ -#define AC_AC0OUT_bm 0x01 /* Comparator 0 Output Enable bit mask. */ -#define AC_AC0OUT_bp 0 /* Comparator 0 Output Enable bit position. */ - - -/* AC.CTRLB bit masks and bit positions */ -#define AC_SCALEFAC_gm 0x3F /* VCC Voltage Scaler Factor group mask. */ -#define AC_SCALEFAC_gp 0 /* VCC Voltage Scaler Factor group position. */ -#define AC_SCALEFAC0_bm (1<<0) /* VCC Voltage Scaler Factor bit 0 mask. */ -#define AC_SCALEFAC0_bp 0 /* VCC Voltage Scaler Factor bit 0 position. */ -#define AC_SCALEFAC1_bm (1<<1) /* VCC Voltage Scaler Factor bit 1 mask. */ -#define AC_SCALEFAC1_bp 1 /* VCC Voltage Scaler Factor bit 1 position. */ -#define AC_SCALEFAC2_bm (1<<2) /* VCC Voltage Scaler Factor bit 2 mask. */ -#define AC_SCALEFAC2_bp 2 /* VCC Voltage Scaler Factor bit 2 position. */ -#define AC_SCALEFAC3_bm (1<<3) /* VCC Voltage Scaler Factor bit 3 mask. */ -#define AC_SCALEFAC3_bp 3 /* VCC Voltage Scaler Factor bit 3 position. */ -#define AC_SCALEFAC4_bm (1<<4) /* VCC Voltage Scaler Factor bit 4 mask. */ -#define AC_SCALEFAC4_bp 4 /* VCC Voltage Scaler Factor bit 4 position. */ -#define AC_SCALEFAC5_bm (1<<5) /* VCC Voltage Scaler Factor bit 5 mask. */ -#define AC_SCALEFAC5_bp 5 /* VCC Voltage Scaler Factor bit 5 position. */ - - -/* AC.WINCTRL bit masks and bit positions */ -#define AC_WEN_bm 0x10 /* Window Mode Enable bit mask. */ -#define AC_WEN_bp 4 /* Window Mode Enable bit position. */ - -#define AC_WINTMODE_gm 0x0C /* Window Interrupt Mode group mask. */ -#define AC_WINTMODE_gp 2 /* Window Interrupt Mode group position. */ -#define AC_WINTMODE0_bm (1<<2) /* Window Interrupt Mode bit 0 mask. */ -#define AC_WINTMODE0_bp 2 /* Window Interrupt Mode bit 0 position. */ -#define AC_WINTMODE1_bm (1<<3) /* Window Interrupt Mode bit 1 mask. */ -#define AC_WINTMODE1_bp 3 /* Window Interrupt Mode bit 1 position. */ - -#define AC_WINTLVL_gm 0x03 /* Window Interrupt Level group mask. */ -#define AC_WINTLVL_gp 0 /* Window Interrupt Level group position. */ -#define AC_WINTLVL0_bm (1<<0) /* Window Interrupt Level bit 0 mask. */ -#define AC_WINTLVL0_bp 0 /* Window Interrupt Level bit 0 position. */ -#define AC_WINTLVL1_bm (1<<1) /* Window Interrupt Level bit 1 mask. */ -#define AC_WINTLVL1_bp 1 /* Window Interrupt Level bit 1 position. */ - - -/* AC.STATUS bit masks and bit positions */ -#define AC_WSTATE_gm 0xC0 /* Window Mode State group mask. */ -#define AC_WSTATE_gp 6 /* Window Mode State group position. */ -#define AC_WSTATE0_bm (1<<6) /* Window Mode State bit 0 mask. */ -#define AC_WSTATE0_bp 6 /* Window Mode State bit 0 position. */ -#define AC_WSTATE1_bm (1<<7) /* Window Mode State bit 1 mask. */ -#define AC_WSTATE1_bp 7 /* Window Mode State bit 1 position. */ - -#define AC_AC1STATE_bm 0x20 /* Comparator 1 State bit mask. */ -#define AC_AC1STATE_bp 5 /* Comparator 1 State bit position. */ - -#define AC_AC0STATE_bm 0x10 /* Comparator 0 State bit mask. */ -#define AC_AC0STATE_bp 4 /* Comparator 0 State bit position. */ - -#define AC_WIF_bm 0x04 /* Window Mode Interrupt Flag bit mask. */ -#define AC_WIF_bp 2 /* Window Mode Interrupt Flag bit position. */ - -#define AC_AC1IF_bm 0x02 /* Comparator 1 Interrupt Flag bit mask. */ -#define AC_AC1IF_bp 1 /* Comparator 1 Interrupt Flag bit position. */ - -#define AC_AC0IF_bm 0x01 /* Comparator 0 Interrupt Flag bit mask. */ -#define AC_AC0IF_bp 0 /* Comparator 0 Interrupt Flag bit position. */ - - -/* ADC - Analog/Digital Converter */ -/* ADC_CH.CTRL bit masks and bit positions */ -#define ADC_CH_START_bm 0x80 /* Channel Start Conversion bit mask. */ -#define ADC_CH_START_bp 7 /* Channel Start Conversion bit position. */ - -#define ADC_CH_GAINFAC_gm 0x1C /* Gain Factor group mask. */ -#define ADC_CH_GAINFAC_gp 2 /* Gain Factor group position. */ -#define ADC_CH_GAINFAC0_bm (1<<2) /* Gain Factor bit 0 mask. */ -#define ADC_CH_GAINFAC0_bp 2 /* Gain Factor bit 0 position. */ -#define ADC_CH_GAINFAC1_bm (1<<3) /* Gain Factor bit 1 mask. */ -#define ADC_CH_GAINFAC1_bp 3 /* Gain Factor bit 1 position. */ -#define ADC_CH_GAINFAC2_bm (1<<4) /* Gain Factor bit 2 mask. */ -#define ADC_CH_GAINFAC2_bp 4 /* Gain Factor bit 2 position. */ - -#define ADC_CH_INPUTMODE_gm 0x03 /* Input Mode Select group mask. */ -#define ADC_CH_INPUTMODE_gp 0 /* Input Mode Select group position. */ -#define ADC_CH_INPUTMODE0_bm (1<<0) /* Input Mode Select bit 0 mask. */ -#define ADC_CH_INPUTMODE0_bp 0 /* Input Mode Select bit 0 position. */ -#define ADC_CH_INPUTMODE1_bm (1<<1) /* Input Mode Select bit 1 mask. */ -#define ADC_CH_INPUTMODE1_bp 1 /* Input Mode Select bit 1 position. */ - - -/* ADC_CH.MUXCTRL bit masks and bit positions */ -#define ADC_CH_MUXPOS_gm 0x78 /* Positive Input Select group mask. */ -#define ADC_CH_MUXPOS_gp 3 /* Positive Input Select group position. */ -#define ADC_CH_MUXPOS0_bm (1<<3) /* Positive Input Select bit 0 mask. */ -#define ADC_CH_MUXPOS0_bp 3 /* Positive Input Select bit 0 position. */ -#define ADC_CH_MUXPOS1_bm (1<<4) /* Positive Input Select bit 1 mask. */ -#define ADC_CH_MUXPOS1_bp 4 /* Positive Input Select bit 1 position. */ -#define ADC_CH_MUXPOS2_bm (1<<5) /* Positive Input Select bit 2 mask. */ -#define ADC_CH_MUXPOS2_bp 5 /* Positive Input Select bit 2 position. */ -#define ADC_CH_MUXPOS3_bm (1<<6) /* Positive Input Select bit 3 mask. */ -#define ADC_CH_MUXPOS3_bp 6 /* Positive Input Select bit 3 position. */ - -#define ADC_CH_MUXINT_gm 0x78 /* Internal Input Select group mask. */ -#define ADC_CH_MUXINT_gp 3 /* Internal Input Select group position. */ -#define ADC_CH_MUXINT0_bm (1<<3) /* Internal Input Select bit 0 mask. */ -#define ADC_CH_MUXINT0_bp 3 /* Internal Input Select bit 0 position. */ -#define ADC_CH_MUXINT1_bm (1<<4) /* Internal Input Select bit 1 mask. */ -#define ADC_CH_MUXINT1_bp 4 /* Internal Input Select bit 1 position. */ -#define ADC_CH_MUXINT2_bm (1<<5) /* Internal Input Select bit 2 mask. */ -#define ADC_CH_MUXINT2_bp 5 /* Internal Input Select bit 2 position. */ -#define ADC_CH_MUXINT3_bm (1<<6) /* Internal Input Select bit 3 mask. */ -#define ADC_CH_MUXINT3_bp 6 /* Internal Input Select bit 3 position. */ - -#define ADC_CH_MUXNEG_gm 0x03 /* Negative Input Select group mask. */ -#define ADC_CH_MUXNEG_gp 0 /* Negative Input Select group position. */ -#define ADC_CH_MUXNEG0_bm (1<<0) /* Negative Input Select bit 0 mask. */ -#define ADC_CH_MUXNEG0_bp 0 /* Negative Input Select bit 0 position. */ -#define ADC_CH_MUXNEG1_bm (1<<1) /* Negative Input Select bit 1 mask. */ -#define ADC_CH_MUXNEG1_bp 1 /* Negative Input Select bit 1 position. */ - - -/* ADC_CH.INTCTRL bit masks and bit positions */ -#define ADC_CH_INTMODE_gm 0x0C /* Interrupt Mode group mask. */ -#define ADC_CH_INTMODE_gp 2 /* Interrupt Mode group position. */ -#define ADC_CH_INTMODE0_bm (1<<2) /* Interrupt Mode bit 0 mask. */ -#define ADC_CH_INTMODE0_bp 2 /* Interrupt Mode bit 0 position. */ -#define ADC_CH_INTMODE1_bm (1<<3) /* Interrupt Mode bit 1 mask. */ -#define ADC_CH_INTMODE1_bp 3 /* Interrupt Mode bit 1 position. */ - -#define ADC_CH_INTLVL_gm 0x03 /* Interrupt Level group mask. */ -#define ADC_CH_INTLVL_gp 0 /* Interrupt Level group position. */ -#define ADC_CH_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */ -#define ADC_CH_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */ -#define ADC_CH_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ -#define ADC_CH_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */ - - -/* ADC_CH.INTFLAGS bit masks and bit positions */ -#define ADC_CH_CHIF_bm 0x01 /* Channel Interrupt Flag bit mask. */ -#define ADC_CH_CHIF_bp 0 /* Channel Interrupt Flag bit position. */ - - -/* ADC.CTRLA bit masks and bit positions */ -#define ADC_DMASEL_gm 0xC0 /* DMA Selection group mask. */ -#define ADC_DMASEL_gp 6 /* DMA Selection group position. */ -#define ADC_DMASEL0_bm (1<<6) /* DMA Selection bit 0 mask. */ -#define ADC_DMASEL0_bp 6 /* DMA Selection bit 0 position. */ -#define ADC_DMASEL1_bm (1<<7) /* DMA Selection bit 1 mask. */ -#define ADC_DMASEL1_bp 7 /* DMA Selection bit 1 position. */ - -#define ADC_CH3START_bm 0x20 /* Channel 3 Start Conversion bit mask. */ -#define ADC_CH3START_bp 5 /* Channel 3 Start Conversion bit position. */ - -#define ADC_CH2START_bm 0x10 /* Channel 2 Start Conversion bit mask. */ -#define ADC_CH2START_bp 4 /* Channel 2 Start Conversion bit position. */ - -#define ADC_CH1START_bm 0x08 /* Channel 1 Start Conversion bit mask. */ -#define ADC_CH1START_bp 3 /* Channel 1 Start Conversion bit position. */ - -#define ADC_CH0START_bm 0x04 /* Channel 0 Start Conversion bit mask. */ -#define ADC_CH0START_bp 2 /* Channel 0 Start Conversion bit position. */ - -#define ADC_FLUSH_bm 0x02 /* Flush Pipeline bit mask. */ -#define ADC_FLUSH_bp 1 /* Flush Pipeline bit position. */ - -#define ADC_ENABLE_bm 0x01 /* Enable ADC bit mask. */ -#define ADC_ENABLE_bp 0 /* Enable ADC bit position. */ - - -/* ADC.CTRLB bit masks and bit positions */ -#define ADC_CONMODE_bm 0x10 /* Conversion Mode bit mask. */ -#define ADC_CONMODE_bp 4 /* Conversion Mode bit position. */ - -#define ADC_FREERUN_bm 0x08 /* Free Running Mode Enable bit mask. */ -#define ADC_FREERUN_bp 3 /* Free Running Mode Enable bit position. */ - -#define ADC_RESOLUTION_gm 0x06 /* Result Resolution group mask. */ -#define ADC_RESOLUTION_gp 1 /* Result Resolution group position. */ -#define ADC_RESOLUTION0_bm (1<<1) /* Result Resolution bit 0 mask. */ -#define ADC_RESOLUTION0_bp 1 /* Result Resolution bit 0 position. */ -#define ADC_RESOLUTION1_bm (1<<2) /* Result Resolution bit 1 mask. */ -#define ADC_RESOLUTION1_bp 2 /* Result Resolution bit 1 position. */ - - -/* ADC.REFCTRL bit masks and bit positions */ -#define ADC_REFSEL_gm 0x30 /* Reference Selection group mask. */ -#define ADC_REFSEL_gp 4 /* Reference Selection group position. */ -#define ADC_REFSEL0_bm (1<<4) /* Reference Selection bit 0 mask. */ -#define ADC_REFSEL0_bp 4 /* Reference Selection bit 0 position. */ -#define ADC_REFSEL1_bm (1<<5) /* Reference Selection bit 1 mask. */ -#define ADC_REFSEL1_bp 5 /* Reference Selection bit 1 position. */ - -#define ADC_BANDGAP_bm 0x02 /* Bandgap enable bit mask. */ -#define ADC_BANDGAP_bp 1 /* Bandgap enable bit position. */ - -#define ADC_TEMPREF_bm 0x01 /* Temperature Reference Enable bit mask. */ -#define ADC_TEMPREF_bp 0 /* Temperature Reference Enable bit position. */ - - -/* ADC.EVCTRL bit masks and bit positions */ -#define ADC_SWEEP_gm 0xC0 /* Channel Sweep Selection group mask. */ -#define ADC_SWEEP_gp 6 /* Channel Sweep Selection group position. */ -#define ADC_SWEEP0_bm (1<<6) /* Channel Sweep Selection bit 0 mask. */ -#define ADC_SWEEP0_bp 6 /* Channel Sweep Selection bit 0 position. */ -#define ADC_SWEEP1_bm (1<<7) /* Channel Sweep Selection bit 1 mask. */ -#define ADC_SWEEP1_bp 7 /* Channel Sweep Selection bit 1 position. */ - -#define ADC_EVSEL_gm 0x38 /* Event Input Select group mask. */ -#define ADC_EVSEL_gp 3 /* Event Input Select group position. */ -#define ADC_EVSEL0_bm (1<<3) /* Event Input Select bit 0 mask. */ -#define ADC_EVSEL0_bp 3 /* Event Input Select bit 0 position. */ -#define ADC_EVSEL1_bm (1<<4) /* Event Input Select bit 1 mask. */ -#define ADC_EVSEL1_bp 4 /* Event Input Select bit 1 position. */ -#define ADC_EVSEL2_bm (1<<5) /* Event Input Select bit 2 mask. */ -#define ADC_EVSEL2_bp 5 /* Event Input Select bit 2 position. */ - -#define ADC_EVACT_gm 0x07 /* Event Action Select group mask. */ -#define ADC_EVACT_gp 0 /* Event Action Select group position. */ -#define ADC_EVACT0_bm (1<<0) /* Event Action Select bit 0 mask. */ -#define ADC_EVACT0_bp 0 /* Event Action Select bit 0 position. */ -#define ADC_EVACT1_bm (1<<1) /* Event Action Select bit 1 mask. */ -#define ADC_EVACT1_bp 1 /* Event Action Select bit 1 position. */ -#define ADC_EVACT2_bm (1<<2) /* Event Action Select bit 2 mask. */ -#define ADC_EVACT2_bp 2 /* Event Action Select bit 2 position. */ - - -/* ADC.PRESCALER bit masks and bit positions */ -#define ADC_PRESCALER_gm 0x07 /* Clock Prescaler Selection group mask. */ -#define ADC_PRESCALER_gp 0 /* Clock Prescaler Selection group position. */ -#define ADC_PRESCALER0_bm (1<<0) /* Clock Prescaler Selection bit 0 mask. */ -#define ADC_PRESCALER0_bp 0 /* Clock Prescaler Selection bit 0 position. */ -#define ADC_PRESCALER1_bm (1<<1) /* Clock Prescaler Selection bit 1 mask. */ -#define ADC_PRESCALER1_bp 1 /* Clock Prescaler Selection bit 1 position. */ -#define ADC_PRESCALER2_bm (1<<2) /* Clock Prescaler Selection bit 2 mask. */ -#define ADC_PRESCALER2_bp 2 /* Clock Prescaler Selection bit 2 position. */ - - -/* ADC.INTFLAGS bit masks and bit positions */ -#define ADC_CH3IF_bm 0x08 /* Channel 3 Interrupt Flag bit mask. */ -#define ADC_CH3IF_bp 3 /* Channel 3 Interrupt Flag bit position. */ - -#define ADC_CH2IF_bm 0x04 /* Channel 2 Interrupt Flag bit mask. */ -#define ADC_CH2IF_bp 2 /* Channel 2 Interrupt Flag bit position. */ - -#define ADC_CH1IF_bm 0x02 /* Channel 1 Interrupt Flag bit mask. */ -#define ADC_CH1IF_bp 1 /* Channel 1 Interrupt Flag bit position. */ - -#define ADC_CH0IF_bm 0x01 /* Channel 0 Interrupt Flag bit mask. */ -#define ADC_CH0IF_bp 0 /* Channel 0 Interrupt Flag bit position. */ - - -/* DAC - Digital/Analog Converter */ -/* DAC.CTRLA bit masks and bit positions */ -#define DAC_IDOEN_bm 0x10 /* Internal Output Enable bit mask. */ -#define DAC_IDOEN_bp 4 /* Internal Output Enable bit position. */ - -#define DAC_CH1EN_bm 0x08 /* Channel 1 Output Enable bit mask. */ -#define DAC_CH1EN_bp 3 /* Channel 1 Output Enable bit position. */ - -#define DAC_CH0EN_bm 0x04 /* Channel 0 Output Enable bit mask. */ -#define DAC_CH0EN_bp 2 /* Channel 0 Output Enable bit position. */ - -#define DAC_LPMODE_bm 0x02 /* Low Power Mode bit mask. */ -#define DAC_LPMODE_bp 1 /* Low Power Mode bit position. */ - -#define DAC_ENABLE_bm 0x01 /* Enable bit mask. */ -#define DAC_ENABLE_bp 0 /* Enable bit position. */ - - -/* DAC.CTRLB bit masks and bit positions */ -#define DAC_CHSEL_gm 0x60 /* Channel Select group mask. */ -#define DAC_CHSEL_gp 5 /* Channel Select group position. */ -#define DAC_CHSEL0_bm (1<<5) /* Channel Select bit 0 mask. */ -#define DAC_CHSEL0_bp 5 /* Channel Select bit 0 position. */ -#define DAC_CHSEL1_bm (1<<6) /* Channel Select bit 1 mask. */ -#define DAC_CHSEL1_bp 6 /* Channel Select bit 1 position. */ - -#define DAC_CH1TRIG_bm 0x02 /* Channel 1 Event Trig Enable bit mask. */ -#define DAC_CH1TRIG_bp 1 /* Channel 1 Event Trig Enable bit position. */ - -#define DAC_CH0TRIG_bm 0x01 /* Channel 0 Event Trig Enable bit mask. */ -#define DAC_CH0TRIG_bp 0 /* Channel 0 Event Trig Enable bit position. */ - - -/* DAC.CTRLC bit masks and bit positions */ -#define DAC_REFSEL_gm 0x18 /* Reference Select group mask. */ -#define DAC_REFSEL_gp 3 /* Reference Select group position. */ -#define DAC_REFSEL0_bm (1<<3) /* Reference Select bit 0 mask. */ -#define DAC_REFSEL0_bp 3 /* Reference Select bit 0 position. */ -#define DAC_REFSEL1_bm (1<<4) /* Reference Select bit 1 mask. */ -#define DAC_REFSEL1_bp 4 /* Reference Select bit 1 position. */ - -#define DAC_LEFTADJ_bm 0x01 /* Left-adjust Result bit mask. */ -#define DAC_LEFTADJ_bp 0 /* Left-adjust Result bit position. */ - - -/* DAC.EVCTRL bit masks and bit positions */ -#define DAC_EVSEL_gm 0x07 /* Event Input Selection group mask. */ -#define DAC_EVSEL_gp 0 /* Event Input Selection group position. */ -#define DAC_EVSEL0_bm (1<<0) /* Event Input Selection bit 0 mask. */ -#define DAC_EVSEL0_bp 0 /* Event Input Selection bit 0 position. */ -#define DAC_EVSEL1_bm (1<<1) /* Event Input Selection bit 1 mask. */ -#define DAC_EVSEL1_bp 1 /* Event Input Selection bit 1 position. */ -#define DAC_EVSEL2_bm (1<<2) /* Event Input Selection bit 2 mask. */ -#define DAC_EVSEL2_bp 2 /* Event Input Selection bit 2 position. */ - - -/* DAC.TIMCTRL bit masks and bit positions */ -#define DAC_CONINTVAL_gm 0x70 /* Conversion Intercal group mask. */ -#define DAC_CONINTVAL_gp 4 /* Conversion Intercal group position. */ -#define DAC_CONINTVAL0_bm (1<<4) /* Conversion Intercal bit 0 mask. */ -#define DAC_CONINTVAL0_bp 4 /* Conversion Intercal bit 0 position. */ -#define DAC_CONINTVAL1_bm (1<<5) /* Conversion Intercal bit 1 mask. */ -#define DAC_CONINTVAL1_bp 5 /* Conversion Intercal bit 1 position. */ -#define DAC_CONINTVAL2_bm (1<<6) /* Conversion Intercal bit 2 mask. */ -#define DAC_CONINTVAL2_bp 6 /* Conversion Intercal bit 2 position. */ - -#define DAC_REFRESH_gm 0x0F /* Refresh Timing Control group mask. */ -#define DAC_REFRESH_gp 0 /* Refresh Timing Control group position. */ -#define DAC_REFRESH0_bm (1<<0) /* Refresh Timing Control bit 0 mask. */ -#define DAC_REFRESH0_bp 0 /* Refresh Timing Control bit 0 position. */ -#define DAC_REFRESH1_bm (1<<1) /* Refresh Timing Control bit 1 mask. */ -#define DAC_REFRESH1_bp 1 /* Refresh Timing Control bit 1 position. */ -#define DAC_REFRESH2_bm (1<<2) /* Refresh Timing Control bit 2 mask. */ -#define DAC_REFRESH2_bp 2 /* Refresh Timing Control bit 2 position. */ -#define DAC_REFRESH3_bm (1<<3) /* Refresh Timing Control bit 3 mask. */ -#define DAC_REFRESH3_bp 3 /* Refresh Timing Control bit 3 position. */ - - -/* DAC.STATUS bit masks and bit positions */ -#define DAC_CH1DRE_bm 0x02 /* Channel 1 Data Register Empty bit mask. */ -#define DAC_CH1DRE_bp 1 /* Channel 1 Data Register Empty bit position. */ - -#define DAC_CH0DRE_bm 0x01 /* Channel 0 Data Register Empty bit mask. */ -#define DAC_CH0DRE_bp 0 /* Channel 0 Data Register Empty bit position. */ - - -/* RTC - Real-Time Clounter */ -/* RTC.CTRL bit masks and bit positions */ -#define RTC_PRESCALER_gm 0x07 /* Prescaling Factor group mask. */ -#define RTC_PRESCALER_gp 0 /* Prescaling Factor group position. */ -#define RTC_PRESCALER0_bm (1<<0) /* Prescaling Factor bit 0 mask. */ -#define RTC_PRESCALER0_bp 0 /* Prescaling Factor bit 0 position. */ -#define RTC_PRESCALER1_bm (1<<1) /* Prescaling Factor bit 1 mask. */ -#define RTC_PRESCALER1_bp 1 /* Prescaling Factor bit 1 position. */ -#define RTC_PRESCALER2_bm (1<<2) /* Prescaling Factor bit 2 mask. */ -#define RTC_PRESCALER2_bp 2 /* Prescaling Factor bit 2 position. */ - - -/* RTC.STATUS bit masks and bit positions */ -#define RTC_SYNCBUSY_bm 0x01 /* Synchronization Busy Flag bit mask. */ -#define RTC_SYNCBUSY_bp 0 /* Synchronization Busy Flag bit position. */ - - -/* RTC.INTCTRL bit masks and bit positions */ -#define RTC_COMPINTLVL_gm 0x0C /* Compare Match Interrupt Level group mask. */ -#define RTC_COMPINTLVL_gp 2 /* Compare Match Interrupt Level group position. */ -#define RTC_COMPINTLVL0_bm (1<<2) /* Compare Match Interrupt Level bit 0 mask. */ -#define RTC_COMPINTLVL0_bp 2 /* Compare Match Interrupt Level bit 0 position. */ -#define RTC_COMPINTLVL1_bm (1<<3) /* Compare Match Interrupt Level bit 1 mask. */ -#define RTC_COMPINTLVL1_bp 3 /* Compare Match Interrupt Level bit 1 position. */ - -#define RTC_OVFINTLVL_gm 0x03 /* Overflow Interrupt Level group mask. */ -#define RTC_OVFINTLVL_gp 0 /* Overflow Interrupt Level group position. */ -#define RTC_OVFINTLVL0_bm (1<<0) /* Overflow Interrupt Level bit 0 mask. */ -#define RTC_OVFINTLVL0_bp 0 /* Overflow Interrupt Level bit 0 position. */ -#define RTC_OVFINTLVL1_bm (1<<1) /* Overflow Interrupt Level bit 1 mask. */ -#define RTC_OVFINTLVL1_bp 1 /* Overflow Interrupt Level bit 1 position. */ - - -/* RTC.INTFLAGS bit masks and bit positions */ -#define RTC_COMPIF_bm 0x02 /* Compare Match Interrupt Flag bit mask. */ -#define RTC_COMPIF_bp 1 /* Compare Match Interrupt Flag bit position. */ - -#define RTC_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ -#define RTC_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ - - -/* EBI - External Bus Interface */ -/* EBI_CS.CTRLA bit masks and bit positions */ -#define EBI_CS_ASIZE_gm 0x7C /* Address Size group mask. */ -#define EBI_CS_ASIZE_gp 2 /* Address Size group position. */ -#define EBI_CS_ASIZE0_bm (1<<2) /* Address Size bit 0 mask. */ -#define EBI_CS_ASIZE0_bp 2 /* Address Size bit 0 position. */ -#define EBI_CS_ASIZE1_bm (1<<3) /* Address Size bit 1 mask. */ -#define EBI_CS_ASIZE1_bp 3 /* Address Size bit 1 position. */ -#define EBI_CS_ASIZE2_bm (1<<4) /* Address Size bit 2 mask. */ -#define EBI_CS_ASIZE2_bp 4 /* Address Size bit 2 position. */ -#define EBI_CS_ASIZE3_bm (1<<5) /* Address Size bit 3 mask. */ -#define EBI_CS_ASIZE3_bp 5 /* Address Size bit 3 position. */ -#define EBI_CS_ASIZE4_bm (1<<6) /* Address Size bit 4 mask. */ -#define EBI_CS_ASIZE4_bp 6 /* Address Size bit 4 position. */ - -#define EBI_CS_MODE_gm 0x03 /* Memory Mode group mask. */ -#define EBI_CS_MODE_gp 0 /* Memory Mode group position. */ -#define EBI_CS_MODE0_bm (1<<0) /* Memory Mode bit 0 mask. */ -#define EBI_CS_MODE0_bp 0 /* Memory Mode bit 0 position. */ -#define EBI_CS_MODE1_bm (1<<1) /* Memory Mode bit 1 mask. */ -#define EBI_CS_MODE1_bp 1 /* Memory Mode bit 1 position. */ - - -/* EBI_CS.CTRLB bit masks and bit positions */ -#define EBI_CS_SRWS_gm 0x07 /* SRAM Wait State Cycles group mask. */ -#define EBI_CS_SRWS_gp 0 /* SRAM Wait State Cycles group position. */ -#define EBI_CS_SRWS0_bm (1<<0) /* SRAM Wait State Cycles bit 0 mask. */ -#define EBI_CS_SRWS0_bp 0 /* SRAM Wait State Cycles bit 0 position. */ -#define EBI_CS_SRWS1_bm (1<<1) /* SRAM Wait State Cycles bit 1 mask. */ -#define EBI_CS_SRWS1_bp 1 /* SRAM Wait State Cycles bit 1 position. */ -#define EBI_CS_SRWS2_bm (1<<2) /* SRAM Wait State Cycles bit 2 mask. */ -#define EBI_CS_SRWS2_bp 2 /* SRAM Wait State Cycles bit 2 position. */ - -#define EBI_CS_SDINITDONE_bm 0x80 /* SDRAM Initialization Done bit mask. */ -#define EBI_CS_SDINITDONE_bp 7 /* SDRAM Initialization Done bit position. */ - -#define EBI_CS_SDSREN_bm 0x04 /* SDRAM Self-refresh Enable bit mask. */ -#define EBI_CS_SDSREN_bp 2 /* SDRAM Self-refresh Enable bit position. */ - -#define EBI_CS_SDMODE_gm 0x03 /* SDRAM Mode group mask. */ -#define EBI_CS_SDMODE_gp 0 /* SDRAM Mode group position. */ -#define EBI_CS_SDMODE0_bm (1<<0) /* SDRAM Mode bit 0 mask. */ -#define EBI_CS_SDMODE0_bp 0 /* SDRAM Mode bit 0 position. */ -#define EBI_CS_SDMODE1_bm (1<<1) /* SDRAM Mode bit 1 mask. */ -#define EBI_CS_SDMODE1_bp 1 /* SDRAM Mode bit 1 position. */ - - -/* EBI.CTRL bit masks and bit positions */ -#define EBI_SDDATAW_gm 0xC0 /* SDRAM Data Width Setting group mask. */ -#define EBI_SDDATAW_gp 6 /* SDRAM Data Width Setting group position. */ -#define EBI_SDDATAW0_bm (1<<6) /* SDRAM Data Width Setting bit 0 mask. */ -#define EBI_SDDATAW0_bp 6 /* SDRAM Data Width Setting bit 0 position. */ -#define EBI_SDDATAW1_bm (1<<7) /* SDRAM Data Width Setting bit 1 mask. */ -#define EBI_SDDATAW1_bp 7 /* SDRAM Data Width Setting bit 1 position. */ - -#define EBI_LPCMODE_gm 0x30 /* SRAM LPC Mode group mask. */ -#define EBI_LPCMODE_gp 4 /* SRAM LPC Mode group position. */ -#define EBI_LPCMODE0_bm (1<<4) /* SRAM LPC Mode bit 0 mask. */ -#define EBI_LPCMODE0_bp 4 /* SRAM LPC Mode bit 0 position. */ -#define EBI_LPCMODE1_bm (1<<5) /* SRAM LPC Mode bit 1 mask. */ -#define EBI_LPCMODE1_bp 5 /* SRAM LPC Mode bit 1 position. */ - -#define EBI_SRMODE_gm 0x0C /* SRAM Mode group mask. */ -#define EBI_SRMODE_gp 2 /* SRAM Mode group position. */ -#define EBI_SRMODE0_bm (1<<2) /* SRAM Mode bit 0 mask. */ -#define EBI_SRMODE0_bp 2 /* SRAM Mode bit 0 position. */ -#define EBI_SRMODE1_bm (1<<3) /* SRAM Mode bit 1 mask. */ -#define EBI_SRMODE1_bp 3 /* SRAM Mode bit 1 position. */ - -#define EBI_IFMODE_gm 0x03 /* Interface Mode group mask. */ -#define EBI_IFMODE_gp 0 /* Interface Mode group position. */ -#define EBI_IFMODE0_bm (1<<0) /* Interface Mode bit 0 mask. */ -#define EBI_IFMODE0_bp 0 /* Interface Mode bit 0 position. */ -#define EBI_IFMODE1_bm (1<<1) /* Interface Mode bit 1 mask. */ -#define EBI_IFMODE1_bp 1 /* Interface Mode bit 1 position. */ - - -/* EBI.SDRAMCTRLA bit masks and bit positions */ -#define EBI_SDCAS_bm 0x08 /* SDRAM CAS Latency Setting bit mask. */ -#define EBI_SDCAS_bp 3 /* SDRAM CAS Latency Setting bit position. */ - -#define EBI_SDROW_bm 0x04 /* SDRAM ROW Bits Setting bit mask. */ -#define EBI_SDROW_bp 2 /* SDRAM ROW Bits Setting bit position. */ - -#define EBI_SDCOL_gm 0x03 /* SDRAM Column Bits Setting group mask. */ -#define EBI_SDCOL_gp 0 /* SDRAM Column Bits Setting group position. */ -#define EBI_SDCOL0_bm (1<<0) /* SDRAM Column Bits Setting bit 0 mask. */ -#define EBI_SDCOL0_bp 0 /* SDRAM Column Bits Setting bit 0 position. */ -#define EBI_SDCOL1_bm (1<<1) /* SDRAM Column Bits Setting bit 1 mask. */ -#define EBI_SDCOL1_bp 1 /* SDRAM Column Bits Setting bit 1 position. */ - - -/* EBI.SDRAMCTRLB bit masks and bit positions */ -#define EBI_MRDLY_gm 0xC0 /* SDRAM Mode Register Delay group mask. */ -#define EBI_MRDLY_gp 6 /* SDRAM Mode Register Delay group position. */ -#define EBI_MRDLY0_bm (1<<6) /* SDRAM Mode Register Delay bit 0 mask. */ -#define EBI_MRDLY0_bp 6 /* SDRAM Mode Register Delay bit 0 position. */ -#define EBI_MRDLY1_bm (1<<7) /* SDRAM Mode Register Delay bit 1 mask. */ -#define EBI_MRDLY1_bp 7 /* SDRAM Mode Register Delay bit 1 position. */ - -#define EBI_ROWCYCDLY_gm 0x38 /* SDRAM Row Cycle Delay group mask. */ -#define EBI_ROWCYCDLY_gp 3 /* SDRAM Row Cycle Delay group position. */ -#define EBI_ROWCYCDLY0_bm (1<<3) /* SDRAM Row Cycle Delay bit 0 mask. */ -#define EBI_ROWCYCDLY0_bp 3 /* SDRAM Row Cycle Delay bit 0 position. */ -#define EBI_ROWCYCDLY1_bm (1<<4) /* SDRAM Row Cycle Delay bit 1 mask. */ -#define EBI_ROWCYCDLY1_bp 4 /* SDRAM Row Cycle Delay bit 1 position. */ -#define EBI_ROWCYCDLY2_bm (1<<5) /* SDRAM Row Cycle Delay bit 2 mask. */ -#define EBI_ROWCYCDLY2_bp 5 /* SDRAM Row Cycle Delay bit 2 position. */ - -#define EBI_RPDLY_gm 0x07 /* SDRAM Row-to-Precharge Delay group mask. */ -#define EBI_RPDLY_gp 0 /* SDRAM Row-to-Precharge Delay group position. */ -#define EBI_RPDLY0_bm (1<<0) /* SDRAM Row-to-Precharge Delay bit 0 mask. */ -#define EBI_RPDLY0_bp 0 /* SDRAM Row-to-Precharge Delay bit 0 position. */ -#define EBI_RPDLY1_bm (1<<1) /* SDRAM Row-to-Precharge Delay bit 1 mask. */ -#define EBI_RPDLY1_bp 1 /* SDRAM Row-to-Precharge Delay bit 1 position. */ -#define EBI_RPDLY2_bm (1<<2) /* SDRAM Row-to-Precharge Delay bit 2 mask. */ -#define EBI_RPDLY2_bp 2 /* SDRAM Row-to-Precharge Delay bit 2 position. */ - - -/* EBI.SDRAMCTRLC bit masks and bit positions */ -#define EBI_WRDLY_gm 0xC0 /* SDRAM Write Recovery Delay group mask. */ -#define EBI_WRDLY_gp 6 /* SDRAM Write Recovery Delay group position. */ -#define EBI_WRDLY0_bm (1<<6) /* SDRAM Write Recovery Delay bit 0 mask. */ -#define EBI_WRDLY0_bp 6 /* SDRAM Write Recovery Delay bit 0 position. */ -#define EBI_WRDLY1_bm (1<<7) /* SDRAM Write Recovery Delay bit 1 mask. */ -#define EBI_WRDLY1_bp 7 /* SDRAM Write Recovery Delay bit 1 position. */ - -#define EBI_ESRDLY_gm 0x38 /* SDRAM Exit-Self-refresh-to-Active Delay group mask. */ -#define EBI_ESRDLY_gp 3 /* SDRAM Exit-Self-refresh-to-Active Delay group position. */ -#define EBI_ESRDLY0_bm (1<<3) /* SDRAM Exit-Self-refresh-to-Active Delay bit 0 mask. */ -#define EBI_ESRDLY0_bp 3 /* SDRAM Exit-Self-refresh-to-Active Delay bit 0 position. */ -#define EBI_ESRDLY1_bm (1<<4) /* SDRAM Exit-Self-refresh-to-Active Delay bit 1 mask. */ -#define EBI_ESRDLY1_bp 4 /* SDRAM Exit-Self-refresh-to-Active Delay bit 1 position. */ -#define EBI_ESRDLY2_bm (1<<5) /* SDRAM Exit-Self-refresh-to-Active Delay bit 2 mask. */ -#define EBI_ESRDLY2_bp 5 /* SDRAM Exit-Self-refresh-to-Active Delay bit 2 position. */ - -#define EBI_ROWCOLDLY_gm 0x07 /* SDRAM Row-to-Column Delay group mask. */ -#define EBI_ROWCOLDLY_gp 0 /* SDRAM Row-to-Column Delay group position. */ -#define EBI_ROWCOLDLY0_bm (1<<0) /* SDRAM Row-to-Column Delay bit 0 mask. */ -#define EBI_ROWCOLDLY0_bp 0 /* SDRAM Row-to-Column Delay bit 0 position. */ -#define EBI_ROWCOLDLY1_bm (1<<1) /* SDRAM Row-to-Column Delay bit 1 mask. */ -#define EBI_ROWCOLDLY1_bp 1 /* SDRAM Row-to-Column Delay bit 1 position. */ -#define EBI_ROWCOLDLY2_bm (1<<2) /* SDRAM Row-to-Column Delay bit 2 mask. */ -#define EBI_ROWCOLDLY2_bp 2 /* SDRAM Row-to-Column Delay bit 2 position. */ - - -/* TWI - Two-Wire Interface */ -/* TWI_MASTER.CTRLA bit masks and bit positions */ -#define TWI_MASTER_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ -#define TWI_MASTER_INTLVL_gp 6 /* Interrupt Level group position. */ -#define TWI_MASTER_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ -#define TWI_MASTER_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ -#define TWI_MASTER_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ -#define TWI_MASTER_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ - -#define TWI_MASTER_RIEN_bm 0x20 /* Read Interrupt Enable bit mask. */ -#define TWI_MASTER_RIEN_bp 5 /* Read Interrupt Enable bit position. */ - -#define TWI_MASTER_WIEN_bm 0x10 /* Write Interrupt Enable bit mask. */ -#define TWI_MASTER_WIEN_bp 4 /* Write Interrupt Enable bit position. */ - -#define TWI_MASTER_ENABLE_bm 0x08 /* Enable TWI Master bit mask. */ -#define TWI_MASTER_ENABLE_bp 3 /* Enable TWI Master bit position. */ - - -/* TWI_MASTER.CTRLB bit masks and bit positions */ -#define TWI_MASTER_TIMEOUT_gm 0x0C /* Inactive Bus Timeout group mask. */ -#define TWI_MASTER_TIMEOUT_gp 2 /* Inactive Bus Timeout group position. */ -#define TWI_MASTER_TIMEOUT0_bm (1<<2) /* Inactive Bus Timeout bit 0 mask. */ -#define TWI_MASTER_TIMEOUT0_bp 2 /* Inactive Bus Timeout bit 0 position. */ -#define TWI_MASTER_TIMEOUT1_bm (1<<3) /* Inactive Bus Timeout bit 1 mask. */ -#define TWI_MASTER_TIMEOUT1_bp 3 /* Inactive Bus Timeout bit 1 position. */ - -#define TWI_MASTER_QCEN_bm 0x02 /* Quick Command Enable bit mask. */ -#define TWI_MASTER_QCEN_bp 1 /* Quick Command Enable bit position. */ - -#define TWI_MASTER_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ -#define TWI_MASTER_SMEN_bp 0 /* Smart Mode Enable bit position. */ - - -/* TWI_MASTER.CTRLC bit masks and bit positions */ -#define TWI_MASTER_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ -#define TWI_MASTER_ACKACT_bp 2 /* Acknowledge Action bit position. */ - -#define TWI_MASTER_CMD_gm 0x03 /* Command group mask. */ -#define TWI_MASTER_CMD_gp 0 /* Command group position. */ -#define TWI_MASTER_CMD0_bm (1<<0) /* Command bit 0 mask. */ -#define TWI_MASTER_CMD0_bp 0 /* Command bit 0 position. */ -#define TWI_MASTER_CMD1_bm (1<<1) /* Command bit 1 mask. */ -#define TWI_MASTER_CMD1_bp 1 /* Command bit 1 position. */ - - -/* TWI_MASTER.STATUS bit masks and bit positions */ -#define TWI_MASTER_RIF_bm 0x80 /* Read Interrupt Flag bit mask. */ -#define TWI_MASTER_RIF_bp 7 /* Read Interrupt Flag bit position. */ - -#define TWI_MASTER_WIF_bm 0x40 /* Write Interrupt Flag bit mask. */ -#define TWI_MASTER_WIF_bp 6 /* Write Interrupt Flag bit position. */ - -#define TWI_MASTER_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ -#define TWI_MASTER_CLKHOLD_bp 5 /* Clock Hold bit position. */ - -#define TWI_MASTER_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ -#define TWI_MASTER_RXACK_bp 4 /* Received Acknowledge bit position. */ - -#define TWI_MASTER_ARBLOST_bm 0x08 /* Arbitration Lost bit mask. */ -#define TWI_MASTER_ARBLOST_bp 3 /* Arbitration Lost bit position. */ - -#define TWI_MASTER_BUSERR_bm 0x04 /* Bus Error bit mask. */ -#define TWI_MASTER_BUSERR_bp 2 /* Bus Error bit position. */ - -#define TWI_MASTER_BUSSTATE_gm 0x03 /* Bus State group mask. */ -#define TWI_MASTER_BUSSTATE_gp 0 /* Bus State group position. */ -#define TWI_MASTER_BUSSTATE0_bm (1<<0) /* Bus State bit 0 mask. */ -#define TWI_MASTER_BUSSTATE0_bp 0 /* Bus State bit 0 position. */ -#define TWI_MASTER_BUSSTATE1_bm (1<<1) /* Bus State bit 1 mask. */ -#define TWI_MASTER_BUSSTATE1_bp 1 /* Bus State bit 1 position. */ - - -/* TWI_SLAVE.CTRLA bit masks and bit positions */ -#define TWI_SLAVE_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ -#define TWI_SLAVE_INTLVL_gp 6 /* Interrupt Level group position. */ -#define TWI_SLAVE_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ -#define TWI_SLAVE_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ -#define TWI_SLAVE_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ -#define TWI_SLAVE_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ - -#define TWI_SLAVE_DIEN_bm 0x20 /* Data Interrupt Enable bit mask. */ -#define TWI_SLAVE_DIEN_bp 5 /* Data Interrupt Enable bit position. */ - -#define TWI_SLAVE_APIEN_bm 0x10 /* Address/Stop Interrupt Enable bit mask. */ -#define TWI_SLAVE_APIEN_bp 4 /* Address/Stop Interrupt Enable bit position. */ - -#define TWI_SLAVE_ENABLE_bm 0x08 /* Enable TWI Slave bit mask. */ -#define TWI_SLAVE_ENABLE_bp 3 /* Enable TWI Slave bit position. */ - -#define TWI_SLAVE_PIEN_bm 0x04 /* Stop Interrupt Enable bit mask. */ -#define TWI_SLAVE_PIEN_bp 2 /* Stop Interrupt Enable bit position. */ - -#define TWI_SLAVE_PMEN_bm 0x02 /* Promiscuous Mode Enable bit mask. */ -#define TWI_SLAVE_PMEN_bp 1 /* Promiscuous Mode Enable bit position. */ - -#define TWI_SLAVE_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ -#define TWI_SLAVE_SMEN_bp 0 /* Smart Mode Enable bit position. */ - - -/* TWI_SLAVE.CTRLB bit masks and bit positions */ -#define TWI_SLAVE_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ -#define TWI_SLAVE_ACKACT_bp 2 /* Acknowledge Action bit position. */ - -#define TWI_SLAVE_CMD_gm 0x03 /* Command group mask. */ -#define TWI_SLAVE_CMD_gp 0 /* Command group position. */ -#define TWI_SLAVE_CMD0_bm (1<<0) /* Command bit 0 mask. */ -#define TWI_SLAVE_CMD0_bp 0 /* Command bit 0 position. */ -#define TWI_SLAVE_CMD1_bm (1<<1) /* Command bit 1 mask. */ -#define TWI_SLAVE_CMD1_bp 1 /* Command bit 1 position. */ - - -/* TWI_SLAVE.STATUS bit masks and bit positions */ -#define TWI_SLAVE_DIF_bm 0x80 /* Data Interrupt Flag bit mask. */ -#define TWI_SLAVE_DIF_bp 7 /* Data Interrupt Flag bit position. */ - -#define TWI_SLAVE_APIF_bm 0x40 /* Address/Stop Interrupt Flag bit mask. */ -#define TWI_SLAVE_APIF_bp 6 /* Address/Stop Interrupt Flag bit position. */ - -#define TWI_SLAVE_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ -#define TWI_SLAVE_CLKHOLD_bp 5 /* Clock Hold bit position. */ - -#define TWI_SLAVE_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ -#define TWI_SLAVE_RXACK_bp 4 /* Received Acknowledge bit position. */ - -#define TWI_SLAVE_COLL_bm 0x08 /* Collision bit mask. */ -#define TWI_SLAVE_COLL_bp 3 /* Collision bit position. */ - -#define TWI_SLAVE_BUSERR_bm 0x04 /* Bus Error bit mask. */ -#define TWI_SLAVE_BUSERR_bp 2 /* Bus Error bit position. */ - -#define TWI_SLAVE_DIR_bm 0x02 /* Read/Write Direction bit mask. */ -#define TWI_SLAVE_DIR_bp 1 /* Read/Write Direction bit position. */ - -#define TWI_SLAVE_AP_bm 0x01 /* Slave Address or Stop bit mask. */ -#define TWI_SLAVE_AP_bp 0 /* Slave Address or Stop bit position. */ - - -/* TWI_SLAVE.ADDRMASK bit masks and bit positions */ -#define TWI_SLAVE_ADDRMASK_gm 0xFE /* Address Mask group mask. */ -#define TWI_SLAVE_ADDRMASK_gp 1 /* Address Mask group position. */ -#define TWI_SLAVE_ADDRMASK0_bm (1<<1) /* Address Mask bit 0 mask. */ -#define TWI_SLAVE_ADDRMASK0_bp 1 /* Address Mask bit 0 position. */ -#define TWI_SLAVE_ADDRMASK1_bm (1<<2) /* Address Mask bit 1 mask. */ -#define TWI_SLAVE_ADDRMASK1_bp 2 /* Address Mask bit 1 position. */ -#define TWI_SLAVE_ADDRMASK2_bm (1<<3) /* Address Mask bit 2 mask. */ -#define TWI_SLAVE_ADDRMASK2_bp 3 /* Address Mask bit 2 position. */ -#define TWI_SLAVE_ADDRMASK3_bm (1<<4) /* Address Mask bit 3 mask. */ -#define TWI_SLAVE_ADDRMASK3_bp 4 /* Address Mask bit 3 position. */ -#define TWI_SLAVE_ADDRMASK4_bm (1<<5) /* Address Mask bit 4 mask. */ -#define TWI_SLAVE_ADDRMASK4_bp 5 /* Address Mask bit 4 position. */ -#define TWI_SLAVE_ADDRMASK5_bm (1<<6) /* Address Mask bit 5 mask. */ -#define TWI_SLAVE_ADDRMASK5_bp 6 /* Address Mask bit 5 position. */ -#define TWI_SLAVE_ADDRMASK6_bm (1<<7) /* Address Mask bit 6 mask. */ -#define TWI_SLAVE_ADDRMASK6_bp 7 /* Address Mask bit 6 position. */ - -#define TWI_SLAVE_ADDREN_bm 0x01 /* Address Enable bit mask. */ -#define TWI_SLAVE_ADDREN_bp 0 /* Address Enable bit position. */ - - -/* TWI.CTRL bit masks and bit positions */ -#define TWI_SDAHOLD_bm 0x02 /* SDA Hold Time Enable bit mask. */ -#define TWI_SDAHOLD_bp 1 /* SDA Hold Time Enable bit position. */ - -#define TWI_EDIEN_bm 0x01 /* External Driver Interface Enable bit mask. */ -#define TWI_EDIEN_bp 0 /* External Driver Interface Enable bit position. */ - - -/* PORT - Port Configuration */ -/* PORTCFG.VPCTRLA bit masks and bit positions */ -#define PORTCFG_VP1MAP_gm 0xF0 /* Virtual Port 1 Mapping group mask. */ -#define PORTCFG_VP1MAP_gp 4 /* Virtual Port 1 Mapping group position. */ -#define PORTCFG_VP1MAP0_bm (1<<4) /* Virtual Port 1 Mapping bit 0 mask. */ -#define PORTCFG_VP1MAP0_bp 4 /* Virtual Port 1 Mapping bit 0 position. */ -#define PORTCFG_VP1MAP1_bm (1<<5) /* Virtual Port 1 Mapping bit 1 mask. */ -#define PORTCFG_VP1MAP1_bp 5 /* Virtual Port 1 Mapping bit 1 position. */ -#define PORTCFG_VP1MAP2_bm (1<<6) /* Virtual Port 1 Mapping bit 2 mask. */ -#define PORTCFG_VP1MAP2_bp 6 /* Virtual Port 1 Mapping bit 2 position. */ -#define PORTCFG_VP1MAP3_bm (1<<7) /* Virtual Port 1 Mapping bit 3 mask. */ -#define PORTCFG_VP1MAP3_bp 7 /* Virtual Port 1 Mapping bit 3 position. */ - -#define PORTCFG_VP0MAP_gm 0x0F /* Virtual Port 0 Mapping group mask. */ -#define PORTCFG_VP0MAP_gp 0 /* Virtual Port 0 Mapping group position. */ -#define PORTCFG_VP0MAP0_bm (1<<0) /* Virtual Port 0 Mapping bit 0 mask. */ -#define PORTCFG_VP0MAP0_bp 0 /* Virtual Port 0 Mapping bit 0 position. */ -#define PORTCFG_VP0MAP1_bm (1<<1) /* Virtual Port 0 Mapping bit 1 mask. */ -#define PORTCFG_VP0MAP1_bp 1 /* Virtual Port 0 Mapping bit 1 position. */ -#define PORTCFG_VP0MAP2_bm (1<<2) /* Virtual Port 0 Mapping bit 2 mask. */ -#define PORTCFG_VP0MAP2_bp 2 /* Virtual Port 0 Mapping bit 2 position. */ -#define PORTCFG_VP0MAP3_bm (1<<3) /* Virtual Port 0 Mapping bit 3 mask. */ -#define PORTCFG_VP0MAP3_bp 3 /* Virtual Port 0 Mapping bit 3 position. */ - - -/* PORTCFG.VPCTRLB bit masks and bit positions */ -#define PORTCFG_VP3MAP_gm 0xF0 /* Virtual Port 3 Mapping group mask. */ -#define PORTCFG_VP3MAP_gp 4 /* Virtual Port 3 Mapping group position. */ -#define PORTCFG_VP3MAP0_bm (1<<4) /* Virtual Port 3 Mapping bit 0 mask. */ -#define PORTCFG_VP3MAP0_bp 4 /* Virtual Port 3 Mapping bit 0 position. */ -#define PORTCFG_VP3MAP1_bm (1<<5) /* Virtual Port 3 Mapping bit 1 mask. */ -#define PORTCFG_VP3MAP1_bp 5 /* Virtual Port 3 Mapping bit 1 position. */ -#define PORTCFG_VP3MAP2_bm (1<<6) /* Virtual Port 3 Mapping bit 2 mask. */ -#define PORTCFG_VP3MAP2_bp 6 /* Virtual Port 3 Mapping bit 2 position. */ -#define PORTCFG_VP3MAP3_bm (1<<7) /* Virtual Port 3 Mapping bit 3 mask. */ -#define PORTCFG_VP3MAP3_bp 7 /* Virtual Port 3 Mapping bit 3 position. */ - -#define PORTCFG_VP2MAP_gm 0x0F /* Virtual Port 2 Mapping group mask. */ -#define PORTCFG_VP2MAP_gp 0 /* Virtual Port 2 Mapping group position. */ -#define PORTCFG_VP2MAP0_bm (1<<0) /* Virtual Port 2 Mapping bit 0 mask. */ -#define PORTCFG_VP2MAP0_bp 0 /* Virtual Port 2 Mapping bit 0 position. */ -#define PORTCFG_VP2MAP1_bm (1<<1) /* Virtual Port 2 Mapping bit 1 mask. */ -#define PORTCFG_VP2MAP1_bp 1 /* Virtual Port 2 Mapping bit 1 position. */ -#define PORTCFG_VP2MAP2_bm (1<<2) /* Virtual Port 2 Mapping bit 2 mask. */ -#define PORTCFG_VP2MAP2_bp 2 /* Virtual Port 2 Mapping bit 2 position. */ -#define PORTCFG_VP2MAP3_bm (1<<3) /* Virtual Port 2 Mapping bit 3 mask. */ -#define PORTCFG_VP2MAP3_bp 3 /* Virtual Port 2 Mapping bit 3 position. */ - - -/* PORTCFG.CLKEVOUT bit masks and bit positions */ -#define PORTCFG_CLKOUT_gm 0x03 /* Clock Output Port group mask. */ -#define PORTCFG_CLKOUT_gp 0 /* Clock Output Port group position. */ -#define PORTCFG_CLKOUT0_bm (1<<0) /* Clock Output Port bit 0 mask. */ -#define PORTCFG_CLKOUT0_bp 0 /* Clock Output Port bit 0 position. */ -#define PORTCFG_CLKOUT1_bm (1<<1) /* Clock Output Port bit 1 mask. */ -#define PORTCFG_CLKOUT1_bp 1 /* Clock Output Port bit 1 position. */ - -#define PORTCFG_EVOUT_gm 0x30 /* Event Output Port group mask. */ -#define PORTCFG_EVOUT_gp 4 /* Event Output Port group position. */ -#define PORTCFG_EVOUT0_bm (1<<4) /* Event Output Port bit 0 mask. */ -#define PORTCFG_EVOUT0_bp 4 /* Event Output Port bit 0 position. */ -#define PORTCFG_EVOUT1_bm (1<<5) /* Event Output Port bit 1 mask. */ -#define PORTCFG_EVOUT1_bp 5 /* Event Output Port bit 1 position. */ - - -/* VPORT.INTFLAGS bit masks and bit positions */ -#define VPORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ -#define VPORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ - -#define VPORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ -#define VPORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ - - -/* PORT.INTCTRL bit masks and bit positions */ -#define PORT_INT1LVL_gm 0x0C /* Port Interrupt 1 Level group mask. */ -#define PORT_INT1LVL_gp 2 /* Port Interrupt 1 Level group position. */ -#define PORT_INT1LVL0_bm (1<<2) /* Port Interrupt 1 Level bit 0 mask. */ -#define PORT_INT1LVL0_bp 2 /* Port Interrupt 1 Level bit 0 position. */ -#define PORT_INT1LVL1_bm (1<<3) /* Port Interrupt 1 Level bit 1 mask. */ -#define PORT_INT1LVL1_bp 3 /* Port Interrupt 1 Level bit 1 position. */ - -#define PORT_INT0LVL_gm 0x03 /* Port Interrupt 0 Level group mask. */ -#define PORT_INT0LVL_gp 0 /* Port Interrupt 0 Level group position. */ -#define PORT_INT0LVL0_bm (1<<0) /* Port Interrupt 0 Level bit 0 mask. */ -#define PORT_INT0LVL0_bp 0 /* Port Interrupt 0 Level bit 0 position. */ -#define PORT_INT0LVL1_bm (1<<1) /* Port Interrupt 0 Level bit 1 mask. */ -#define PORT_INT0LVL1_bp 1 /* Port Interrupt 0 Level bit 1 position. */ - - -/* PORT.INTFLAGS bit masks and bit positions */ -#define PORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ -#define PORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ - -#define PORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ -#define PORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ - - -/* PORT.PIN0CTRL bit masks and bit positions */ -#define PORT_SRLEN_bm 0x80 /* Slew Rate Enable bit mask. */ -#define PORT_SRLEN_bp 7 /* Slew Rate Enable bit position. */ - -#define PORT_INVEN_bm 0x40 /* Inverted I/O Enable bit mask. */ -#define PORT_INVEN_bp 6 /* Inverted I/O Enable bit position. */ - -#define PORT_OPC_gm 0x38 /* Output/Pull Configuration group mask. */ -#define PORT_OPC_gp 3 /* Output/Pull Configuration group position. */ -#define PORT_OPC0_bm (1<<3) /* Output/Pull Configuration bit 0 mask. */ -#define PORT_OPC0_bp 3 /* Output/Pull Configuration bit 0 position. */ -#define PORT_OPC1_bm (1<<4) /* Output/Pull Configuration bit 1 mask. */ -#define PORT_OPC1_bp 4 /* Output/Pull Configuration bit 1 position. */ -#define PORT_OPC2_bm (1<<5) /* Output/Pull Configuration bit 2 mask. */ -#define PORT_OPC2_bp 5 /* Output/Pull Configuration bit 2 position. */ - -#define PORT_ISC_gm 0x07 /* Input/Sense Configuration group mask. */ -#define PORT_ISC_gp 0 /* Input/Sense Configuration group position. */ -#define PORT_ISC0_bm (1<<0) /* Input/Sense Configuration bit 0 mask. */ -#define PORT_ISC0_bp 0 /* Input/Sense Configuration bit 0 position. */ -#define PORT_ISC1_bm (1<<1) /* Input/Sense Configuration bit 1 mask. */ -#define PORT_ISC1_bp 1 /* Input/Sense Configuration bit 1 position. */ -#define PORT_ISC2_bm (1<<2) /* Input/Sense Configuration bit 2 mask. */ -#define PORT_ISC2_bp 2 /* Input/Sense Configuration bit 2 position. */ - - -/* PORT.PIN1CTRL bit masks and bit positions */ -/* PORT_SRLEN_bm Predefined. */ -/* PORT_SRLEN_bp Predefined. */ - -/* PORT_INVEN_bm Predefined. */ -/* PORT_INVEN_bp Predefined. */ - -/* PORT_OPC_gm Predefined. */ -/* PORT_OPC_gp Predefined. */ -/* PORT_OPC0_bm Predefined. */ -/* PORT_OPC0_bp Predefined. */ -/* PORT_OPC1_bm Predefined. */ -/* PORT_OPC1_bp Predefined. */ -/* PORT_OPC2_bm Predefined. */ -/* PORT_OPC2_bp Predefined. */ - -/* PORT_ISC_gm Predefined. */ -/* PORT_ISC_gp Predefined. */ -/* PORT_ISC0_bm Predefined. */ -/* PORT_ISC0_bp Predefined. */ -/* PORT_ISC1_bm Predefined. */ -/* PORT_ISC1_bp Predefined. */ -/* PORT_ISC2_bm Predefined. */ -/* PORT_ISC2_bp Predefined. */ - - -/* PORT.PIN2CTRL bit masks and bit positions */ -/* PORT_SRLEN_bm Predefined. */ -/* PORT_SRLEN_bp Predefined. */ - -/* PORT_INVEN_bm Predefined. */ -/* PORT_INVEN_bp Predefined. */ - -/* PORT_OPC_gm Predefined. */ -/* PORT_OPC_gp Predefined. */ -/* PORT_OPC0_bm Predefined. */ -/* PORT_OPC0_bp Predefined. */ -/* PORT_OPC1_bm Predefined. */ -/* PORT_OPC1_bp Predefined. */ -/* PORT_OPC2_bm Predefined. */ -/* PORT_OPC2_bp Predefined. */ - -/* PORT_ISC_gm Predefined. */ -/* PORT_ISC_gp Predefined. */ -/* PORT_ISC0_bm Predefined. */ -/* PORT_ISC0_bp Predefined. */ -/* PORT_ISC1_bm Predefined. */ -/* PORT_ISC1_bp Predefined. */ -/* PORT_ISC2_bm Predefined. */ -/* PORT_ISC2_bp Predefined. */ - - -/* PORT.PIN3CTRL bit masks and bit positions */ -/* PORT_SRLEN_bm Predefined. */ -/* PORT_SRLEN_bp Predefined. */ - -/* PORT_INVEN_bm Predefined. */ -/* PORT_INVEN_bp Predefined. */ - -/* PORT_OPC_gm Predefined. */ -/* PORT_OPC_gp Predefined. */ -/* PORT_OPC0_bm Predefined. */ -/* PORT_OPC0_bp Predefined. */ -/* PORT_OPC1_bm Predefined. */ -/* PORT_OPC1_bp Predefined. */ -/* PORT_OPC2_bm Predefined. */ -/* PORT_OPC2_bp Predefined. */ - -/* PORT_ISC_gm Predefined. */ -/* PORT_ISC_gp Predefined. */ -/* PORT_ISC0_bm Predefined. */ -/* PORT_ISC0_bp Predefined. */ -/* PORT_ISC1_bm Predefined. */ -/* PORT_ISC1_bp Predefined. */ -/* PORT_ISC2_bm Predefined. */ -/* PORT_ISC2_bp Predefined. */ - - -/* PORT.PIN4CTRL bit masks and bit positions */ -/* PORT_SRLEN_bm Predefined. */ -/* PORT_SRLEN_bp Predefined. */ - -/* PORT_INVEN_bm Predefined. */ -/* PORT_INVEN_bp Predefined. */ - -/* PORT_OPC_gm Predefined. */ -/* PORT_OPC_gp Predefined. */ -/* PORT_OPC0_bm Predefined. */ -/* PORT_OPC0_bp Predefined. */ -/* PORT_OPC1_bm Predefined. */ -/* PORT_OPC1_bp Predefined. */ -/* PORT_OPC2_bm Predefined. */ -/* PORT_OPC2_bp Predefined. */ - -/* PORT_ISC_gm Predefined. */ -/* PORT_ISC_gp Predefined. */ -/* PORT_ISC0_bm Predefined. */ -/* PORT_ISC0_bp Predefined. */ -/* PORT_ISC1_bm Predefined. */ -/* PORT_ISC1_bp Predefined. */ -/* PORT_ISC2_bm Predefined. */ -/* PORT_ISC2_bp Predefined. */ - - -/* PORT.PIN5CTRL bit masks and bit positions */ -/* PORT_SRLEN_bm Predefined. */ -/* PORT_SRLEN_bp Predefined. */ - -/* PORT_INVEN_bm Predefined. */ -/* PORT_INVEN_bp Predefined. */ - -/* PORT_OPC_gm Predefined. */ -/* PORT_OPC_gp Predefined. */ -/* PORT_OPC0_bm Predefined. */ -/* PORT_OPC0_bp Predefined. */ -/* PORT_OPC1_bm Predefined. */ -/* PORT_OPC1_bp Predefined. */ -/* PORT_OPC2_bm Predefined. */ -/* PORT_OPC2_bp Predefined. */ - -/* PORT_ISC_gm Predefined. */ -/* PORT_ISC_gp Predefined. */ -/* PORT_ISC0_bm Predefined. */ -/* PORT_ISC0_bp Predefined. */ -/* PORT_ISC1_bm Predefined. */ -/* PORT_ISC1_bp Predefined. */ -/* PORT_ISC2_bm Predefined. */ -/* PORT_ISC2_bp Predefined. */ - - -/* PORT.PIN6CTRL bit masks and bit positions */ -/* PORT_SRLEN_bm Predefined. */ -/* PORT_SRLEN_bp Predefined. */ - -/* PORT_INVEN_bm Predefined. */ -/* PORT_INVEN_bp Predefined. */ - -/* PORT_OPC_gm Predefined. */ -/* PORT_OPC_gp Predefined. */ -/* PORT_OPC0_bm Predefined. */ -/* PORT_OPC0_bp Predefined. */ -/* PORT_OPC1_bm Predefined. */ -/* PORT_OPC1_bp Predefined. */ -/* PORT_OPC2_bm Predefined. */ -/* PORT_OPC2_bp Predefined. */ - -/* PORT_ISC_gm Predefined. */ -/* PORT_ISC_gp Predefined. */ -/* PORT_ISC0_bm Predefined. */ -/* PORT_ISC0_bp Predefined. */ -/* PORT_ISC1_bm Predefined. */ -/* PORT_ISC1_bp Predefined. */ -/* PORT_ISC2_bm Predefined. */ -/* PORT_ISC2_bp Predefined. */ - - -/* PORT.PIN7CTRL bit masks and bit positions */ -/* PORT_SRLEN_bm Predefined. */ -/* PORT_SRLEN_bp Predefined. */ - -/* PORT_INVEN_bm Predefined. */ -/* PORT_INVEN_bp Predefined. */ - -/* PORT_OPC_gm Predefined. */ -/* PORT_OPC_gp Predefined. */ -/* PORT_OPC0_bm Predefined. */ -/* PORT_OPC0_bp Predefined. */ -/* PORT_OPC1_bm Predefined. */ -/* PORT_OPC1_bp Predefined. */ -/* PORT_OPC2_bm Predefined. */ -/* PORT_OPC2_bp Predefined. */ - -/* PORT_ISC_gm Predefined. */ -/* PORT_ISC_gp Predefined. */ -/* PORT_ISC0_bm Predefined. */ -/* PORT_ISC0_bp Predefined. */ -/* PORT_ISC1_bm Predefined. */ -/* PORT_ISC1_bp Predefined. */ -/* PORT_ISC2_bm Predefined. */ -/* PORT_ISC2_bp Predefined. */ - - -/* TC - 16-bit Timer/Counter With PWM */ -/* TC0.CTRLA bit masks and bit positions */ -#define TC0_CLKSEL_gm 0x0F /* Clock Selection group mask. */ -#define TC0_CLKSEL_gp 0 /* Clock Selection group position. */ -#define TC0_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ -#define TC0_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ -#define TC0_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ -#define TC0_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ -#define TC0_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ -#define TC0_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ -#define TC0_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ -#define TC0_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ - - -/* TC0.CTRLB bit masks and bit positions */ -#define TC0_CCDEN_bm 0x80 /* Compare or Capture D Enable bit mask. */ -#define TC0_CCDEN_bp 7 /* Compare or Capture D Enable bit position. */ - -#define TC0_CCCEN_bm 0x40 /* Compare or Capture C Enable bit mask. */ -#define TC0_CCCEN_bp 6 /* Compare or Capture C Enable bit position. */ - -#define TC0_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ -#define TC0_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ - -#define TC0_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ -#define TC0_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ - -#define TC0_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ -#define TC0_WGMODE_gp 0 /* Waveform generation mode group position. */ -#define TC0_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ -#define TC0_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ -#define TC0_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ -#define TC0_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ -#define TC0_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ -#define TC0_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ - - -/* TC0.CTRLC bit masks and bit positions */ -#define TC0_CMPD_bm 0x08 /* Compare D Output Value bit mask. */ -#define TC0_CMPD_bp 3 /* Compare D Output Value bit position. */ - -#define TC0_CMPC_bm 0x04 /* Compare C Output Value bit mask. */ -#define TC0_CMPC_bp 2 /* Compare C Output Value bit position. */ - -#define TC0_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ -#define TC0_CMPB_bp 1 /* Compare B Output Value bit position. */ - -#define TC0_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ -#define TC0_CMPA_bp 0 /* Compare A Output Value bit position. */ - - -/* TC0.CTRLD bit masks and bit positions */ -#define TC0_EVACT_gm 0xE0 /* Event Action group mask. */ -#define TC0_EVACT_gp 5 /* Event Action group position. */ -#define TC0_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ -#define TC0_EVACT0_bp 5 /* Event Action bit 0 position. */ -#define TC0_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ -#define TC0_EVACT1_bp 6 /* Event Action bit 1 position. */ -#define TC0_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ -#define TC0_EVACT2_bp 7 /* Event Action bit 2 position. */ - -#define TC0_EVDLY_bm 0x10 /* Event Delay bit mask. */ -#define TC0_EVDLY_bp 4 /* Event Delay bit position. */ - -#define TC0_EVSEL_gm 0x0F /* Event Source Select group mask. */ -#define TC0_EVSEL_gp 0 /* Event Source Select group position. */ -#define TC0_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ -#define TC0_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ -#define TC0_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ -#define TC0_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ -#define TC0_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ -#define TC0_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ -#define TC0_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ -#define TC0_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ - - -/* TC0.CTRLE bit masks and bit positions */ -#define TC0_DTHM_bm 0x02 /* Dead Time Hold Mode bit mask. */ -#define TC0_DTHM_bp 1 /* Dead Time Hold Mode bit position. */ - -#define TC0_BYTEM_bm 0x01 /* Byte Mode bit mask. */ -#define TC0_BYTEM_bp 0 /* Byte Mode bit position. */ - - -/* TC0.INTCTRLA bit masks and bit positions */ -#define TC0_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ -#define TC0_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ -#define TC0_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ -#define TC0_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ -#define TC0_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ -#define TC0_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ - -#define TC0_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ -#define TC0_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ -#define TC0_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ -#define TC0_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ -#define TC0_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ -#define TC0_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ - - -/* TC0.INTCTRLB bit masks and bit positions */ -#define TC0_CCDINTLVL_gm 0xC0 /* Compare or Capture D Interrupt Level group mask. */ -#define TC0_CCDINTLVL_gp 6 /* Compare or Capture D Interrupt Level group position. */ -#define TC0_CCDINTLVL0_bm (1<<6) /* Compare or Capture D Interrupt Level bit 0 mask. */ -#define TC0_CCDINTLVL0_bp 6 /* Compare or Capture D Interrupt Level bit 0 position. */ -#define TC0_CCDINTLVL1_bm (1<<7) /* Compare or Capture D Interrupt Level bit 1 mask. */ -#define TC0_CCDINTLVL1_bp 7 /* Compare or Capture D Interrupt Level bit 1 position. */ - -#define TC0_CCCINTLVL_gm 0x30 /* Compare or Capture C Interrupt Level group mask. */ -#define TC0_CCCINTLVL_gp 4 /* Compare or Capture C Interrupt Level group position. */ -#define TC0_CCCINTLVL0_bm (1<<4) /* Compare or Capture C Interrupt Level bit 0 mask. */ -#define TC0_CCCINTLVL0_bp 4 /* Compare or Capture C Interrupt Level bit 0 position. */ -#define TC0_CCCINTLVL1_bm (1<<5) /* Compare or Capture C Interrupt Level bit 1 mask. */ -#define TC0_CCCINTLVL1_bp 5 /* Compare or Capture C Interrupt Level bit 1 position. */ - -#define TC0_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ -#define TC0_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ -#define TC0_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ -#define TC0_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ -#define TC0_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ -#define TC0_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ - -#define TC0_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ -#define TC0_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ -#define TC0_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ -#define TC0_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ -#define TC0_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ -#define TC0_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ - - -/* TC0.CTRLFCLR bit masks and bit positions */ -#define TC0_CMD_gm 0x0C /* Command group mask. */ -#define TC0_CMD_gp 2 /* Command group position. */ -#define TC0_CMD0_bm (1<<2) /* Command bit 0 mask. */ -#define TC0_CMD0_bp 2 /* Command bit 0 position. */ -#define TC0_CMD1_bm (1<<3) /* Command bit 1 mask. */ -#define TC0_CMD1_bp 3 /* Command bit 1 position. */ - -#define TC0_LUPD_bm 0x02 /* Lock Update bit mask. */ -#define TC0_LUPD_bp 1 /* Lock Update bit position. */ - -#define TC0_DIR_bm 0x01 /* Direction bit mask. */ -#define TC0_DIR_bp 0 /* Direction bit position. */ - - -/* TC0.CTRLFSET bit masks and bit positions */ -/* TC0_CMD_gm Predefined. */ -/* TC0_CMD_gp Predefined. */ -/* TC0_CMD0_bm Predefined. */ -/* TC0_CMD0_bp Predefined. */ -/* TC0_CMD1_bm Predefined. */ -/* TC0_CMD1_bp Predefined. */ - -/* TC0_LUPD_bm Predefined. */ -/* TC0_LUPD_bp Predefined. */ - -/* TC0_DIR_bm Predefined. */ -/* TC0_DIR_bp Predefined. */ - - -/* TC0.CTRLGCLR bit masks and bit positions */ -#define TC0_CCDBV_bm 0x10 /* Compare or Capture D Buffer Valid bit mask. */ -#define TC0_CCDBV_bp 4 /* Compare or Capture D Buffer Valid bit position. */ - -#define TC0_CCCBV_bm 0x08 /* Compare or Capture C Buffer Valid bit mask. */ -#define TC0_CCCBV_bp 3 /* Compare or Capture C Buffer Valid bit position. */ - -#define TC0_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ -#define TC0_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ - -#define TC0_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ -#define TC0_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ - -#define TC0_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ -#define TC0_PERBV_bp 0 /* Period Buffer Valid bit position. */ - - -/* TC0.CTRLGSET bit masks and bit positions */ -/* TC0_CCDBV_bm Predefined. */ -/* TC0_CCDBV_bp Predefined. */ - -/* TC0_CCCBV_bm Predefined. */ -/* TC0_CCCBV_bp Predefined. */ - -/* TC0_CCBBV_bm Predefined. */ -/* TC0_CCBBV_bp Predefined. */ - -/* TC0_CCABV_bm Predefined. */ -/* TC0_CCABV_bp Predefined. */ - -/* TC0_PERBV_bm Predefined. */ -/* TC0_PERBV_bp Predefined. */ - - -/* TC0.INTFLAGS bit masks and bit positions */ -#define TC0_CCDIF_bm 0x80 /* Compare or Capture D Interrupt Flag bit mask. */ -#define TC0_CCDIF_bp 7 /* Compare or Capture D Interrupt Flag bit position. */ - -#define TC0_CCCIF_bm 0x40 /* Compare or Capture C Interrupt Flag bit mask. */ -#define TC0_CCCIF_bp 6 /* Compare or Capture C Interrupt Flag bit position. */ - -#define TC0_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ -#define TC0_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ - -#define TC0_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ -#define TC0_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ - -#define TC0_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ -#define TC0_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ - -#define TC0_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ -#define TC0_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ - - -/* TC1.CTRLA bit masks and bit positions */ -#define TC1_CLKSEL_gm 0x0F /* Clock Selection group mask. */ -#define TC1_CLKSEL_gp 0 /* Clock Selection group position. */ -#define TC1_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ -#define TC1_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ -#define TC1_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ -#define TC1_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ -#define TC1_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ -#define TC1_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ -#define TC1_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ -#define TC1_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ - - -/* TC1.CTRLB bit masks and bit positions */ -#define TC1_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ -#define TC1_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ - -#define TC1_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ -#define TC1_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ - -#define TC1_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ -#define TC1_WGMODE_gp 0 /* Waveform generation mode group position. */ -#define TC1_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ -#define TC1_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ -#define TC1_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ -#define TC1_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ -#define TC1_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ -#define TC1_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ - - -/* TC1.CTRLC bit masks and bit positions */ -#define TC1_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ -#define TC1_CMPB_bp 1 /* Compare B Output Value bit position. */ - -#define TC1_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ -#define TC1_CMPA_bp 0 /* Compare A Output Value bit position. */ - - -/* TC1.CTRLD bit masks and bit positions */ -#define TC1_EVACT_gm 0xE0 /* Event Action group mask. */ -#define TC1_EVACT_gp 5 /* Event Action group position. */ -#define TC1_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ -#define TC1_EVACT0_bp 5 /* Event Action bit 0 position. */ -#define TC1_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ -#define TC1_EVACT1_bp 6 /* Event Action bit 1 position. */ -#define TC1_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ -#define TC1_EVACT2_bp 7 /* Event Action bit 2 position. */ - -#define TC1_EVDLY_bm 0x10 /* Event Delay bit mask. */ -#define TC1_EVDLY_bp 4 /* Event Delay bit position. */ - -#define TC1_EVSEL_gm 0x0F /* Event Source Select group mask. */ -#define TC1_EVSEL_gp 0 /* Event Source Select group position. */ -#define TC1_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ -#define TC1_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ -#define TC1_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ -#define TC1_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ -#define TC1_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ -#define TC1_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ -#define TC1_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ -#define TC1_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ - - -/* TC1.CTRLE bit masks and bit positions */ -#define TC1_DTHM_bm 0x02 /* Dead Time Hold Mode bit mask. */ -#define TC1_DTHM_bp 1 /* Dead Time Hold Mode bit position. */ - -#define TC1_BYTEM_bm 0x01 /* Byte Mode bit mask. */ -#define TC1_BYTEM_bp 0 /* Byte Mode bit position. */ - - -/* TC1.INTCTRLA bit masks and bit positions */ -#define TC1_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ -#define TC1_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ -#define TC1_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ -#define TC1_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ -#define TC1_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ -#define TC1_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ - -#define TC1_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ -#define TC1_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ -#define TC1_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ -#define TC1_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ -#define TC1_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ -#define TC1_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ - - -/* TC1.INTCTRLB bit masks and bit positions */ -#define TC1_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ -#define TC1_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ -#define TC1_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ -#define TC1_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ -#define TC1_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ -#define TC1_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ - -#define TC1_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ -#define TC1_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ -#define TC1_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ -#define TC1_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ -#define TC1_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ -#define TC1_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ - - -/* TC1.CTRLFCLR bit masks and bit positions */ -#define TC1_CMD_gm 0x0C /* Command group mask. */ -#define TC1_CMD_gp 2 /* Command group position. */ -#define TC1_CMD0_bm (1<<2) /* Command bit 0 mask. */ -#define TC1_CMD0_bp 2 /* Command bit 0 position. */ -#define TC1_CMD1_bm (1<<3) /* Command bit 1 mask. */ -#define TC1_CMD1_bp 3 /* Command bit 1 position. */ - -#define TC1_LUPD_bm 0x02 /* Lock Update bit mask. */ -#define TC1_LUPD_bp 1 /* Lock Update bit position. */ - -#define TC1_DIR_bm 0x01 /* Direction bit mask. */ -#define TC1_DIR_bp 0 /* Direction bit position. */ - - -/* TC1.CTRLFSET bit masks and bit positions */ -/* TC1_CMD_gm Predefined. */ -/* TC1_CMD_gp Predefined. */ -/* TC1_CMD0_bm Predefined. */ -/* TC1_CMD0_bp Predefined. */ -/* TC1_CMD1_bm Predefined. */ -/* TC1_CMD1_bp Predefined. */ - -/* TC1_LUPD_bm Predefined. */ -/* TC1_LUPD_bp Predefined. */ - -/* TC1_DIR_bm Predefined. */ -/* TC1_DIR_bp Predefined. */ - - -/* TC1.CTRLGCLR bit masks and bit positions */ -#define TC1_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ -#define TC1_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ - -#define TC1_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ -#define TC1_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ - -#define TC1_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ -#define TC1_PERBV_bp 0 /* Period Buffer Valid bit position. */ - - -/* TC1.CTRLGSET bit masks and bit positions */ -/* TC1_CCBBV_bm Predefined. */ -/* TC1_CCBBV_bp Predefined. */ - -/* TC1_CCABV_bm Predefined. */ -/* TC1_CCABV_bp Predefined. */ - -/* TC1_PERBV_bm Predefined. */ -/* TC1_PERBV_bp Predefined. */ - - -/* TC1.INTFLAGS bit masks and bit positions */ -#define TC1_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ -#define TC1_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ - -#define TC1_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ -#define TC1_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ - -#define TC1_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ -#define TC1_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ - -#define TC1_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ -#define TC1_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ - - -/* AWEX.CTRL bit masks and bit positions */ -#define AWEX_PGM_bm 0x20 /* Pattern Generation Mode bit mask. */ -#define AWEX_PGM_bp 5 /* Pattern Generation Mode bit position. */ - -#define AWEX_CWCM_bm 0x10 /* Common Waveform Channel Mode bit mask. */ -#define AWEX_CWCM_bp 4 /* Common Waveform Channel Mode bit position. */ - -#define AWEX_DTICCDEN_bm 0x08 /* Dead Time Insertion Compare Channel D Enable bit mask. */ -#define AWEX_DTICCDEN_bp 3 /* Dead Time Insertion Compare Channel D Enable bit position. */ - -#define AWEX_DTICCCEN_bm 0x04 /* Dead Time Insertion Compare Channel C Enable bit mask. */ -#define AWEX_DTICCCEN_bp 2 /* Dead Time Insertion Compare Channel C Enable bit position. */ - -#define AWEX_DTICCBEN_bm 0x02 /* Dead Time Insertion Compare Channel B Enable bit mask. */ -#define AWEX_DTICCBEN_bp 1 /* Dead Time Insertion Compare Channel B Enable bit position. */ - -#define AWEX_DTICCAEN_bm 0x01 /* Dead Time Insertion Compare Channel A Enable bit mask. */ -#define AWEX_DTICCAEN_bp 0 /* Dead Time Insertion Compare Channel A Enable bit position. */ - - -/* AWEX.FDCTRL bit masks and bit positions */ -#define AWEX_FDDBD_bm 0x10 /* Fault Detect on Disable Break Disable bit mask. */ -#define AWEX_FDDBD_bp 4 /* Fault Detect on Disable Break Disable bit position. */ - -#define AWEX_FDMODE_bm 0x04 /* Fault Detect Mode bit mask. */ -#define AWEX_FDMODE_bp 2 /* Fault Detect Mode bit position. */ - -#define AWEX_FDACT_gm 0x03 /* Fault Detect Action group mask. */ -#define AWEX_FDACT_gp 0 /* Fault Detect Action group position. */ -#define AWEX_FDACT0_bm (1<<0) /* Fault Detect Action bit 0 mask. */ -#define AWEX_FDACT0_bp 0 /* Fault Detect Action bit 0 position. */ -#define AWEX_FDACT1_bm (1<<1) /* Fault Detect Action bit 1 mask. */ -#define AWEX_FDACT1_bp 1 /* Fault Detect Action bit 1 position. */ - - -/* AWEX.STATUS bit masks and bit positions */ -#define AWEX_FDF_bm 0x04 /* Fault Detect Flag bit mask. */ -#define AWEX_FDF_bp 2 /* Fault Detect Flag bit position. */ - -#define AWEX_DTHSBUFV_bm 0x02 /* Dead Time High Side Buffer Valid bit mask. */ -#define AWEX_DTHSBUFV_bp 1 /* Dead Time High Side Buffer Valid bit position. */ - -#define AWEX_DTLSBUFV_bm 0x01 /* Dead Time Low Side Buffer Valid bit mask. */ -#define AWEX_DTLSBUFV_bp 0 /* Dead Time Low Side Buffer Valid bit position. */ - - -/* HIRES.CTRLA bit masks and bit positions */ -#define HIRES_HREN_gm 0x03 /* High Resolution Enable group mask. */ -#define HIRES_HREN_gp 0 /* High Resolution Enable group position. */ -#define HIRES_HREN0_bm (1<<0) /* High Resolution Enable bit 0 mask. */ -#define HIRES_HREN0_bp 0 /* High Resolution Enable bit 0 position. */ -#define HIRES_HREN1_bm (1<<1) /* High Resolution Enable bit 1 mask. */ -#define HIRES_HREN1_bp 1 /* High Resolution Enable bit 1 position. */ - - -/* USART - Universal Asynchronous Receiver-Transmitter */ -/* USART.STATUS bit masks and bit positions */ -#define USART_RXCIF_bm 0x80 /* Receive Interrupt Flag bit mask. */ -#define USART_RXCIF_bp 7 /* Receive Interrupt Flag bit position. */ - -#define USART_TXCIF_bm 0x40 /* Transmit Interrupt Flag bit mask. */ -#define USART_TXCIF_bp 6 /* Transmit Interrupt Flag bit position. */ - -#define USART_DREIF_bm 0x20 /* Data Register Empty Flag bit mask. */ -#define USART_DREIF_bp 5 /* Data Register Empty Flag bit position. */ - -#define USART_FERR_bm 0x10 /* Frame Error bit mask. */ -#define USART_FERR_bp 4 /* Frame Error bit position. */ - -#define USART_BUFOVF_bm 0x08 /* Buffer Overflow bit mask. */ -#define USART_BUFOVF_bp 3 /* Buffer Overflow bit position. */ - -#define USART_PERR_bm 0x04 /* Parity Error bit mask. */ -#define USART_PERR_bp 2 /* Parity Error bit position. */ - -#define USART_RXB8_bm 0x01 /* Receive Bit 8 bit mask. */ -#define USART_RXB8_bp 0 /* Receive Bit 8 bit position. */ - - -/* USART.CTRLA bit masks and bit positions */ -#define USART_RXCINTLVL_gm 0x30 /* Receive Interrupt Level group mask. */ -#define USART_RXCINTLVL_gp 4 /* Receive Interrupt Level group position. */ -#define USART_RXCINTLVL0_bm (1<<4) /* Receive Interrupt Level bit 0 mask. */ -#define USART_RXCINTLVL0_bp 4 /* Receive Interrupt Level bit 0 position. */ -#define USART_RXCINTLVL1_bm (1<<5) /* Receive Interrupt Level bit 1 mask. */ -#define USART_RXCINTLVL1_bp 5 /* Receive Interrupt Level bit 1 position. */ - -#define USART_TXCINTLVL_gm 0x0C /* Transmit Interrupt Level group mask. */ -#define USART_TXCINTLVL_gp 2 /* Transmit Interrupt Level group position. */ -#define USART_TXCINTLVL0_bm (1<<2) /* Transmit Interrupt Level bit 0 mask. */ -#define USART_TXCINTLVL0_bp 2 /* Transmit Interrupt Level bit 0 position. */ -#define USART_TXCINTLVL1_bm (1<<3) /* Transmit Interrupt Level bit 1 mask. */ -#define USART_TXCINTLVL1_bp 3 /* Transmit Interrupt Level bit 1 position. */ - -#define USART_DREINTLVL_gm 0x03 /* Data Register Empty Interrupt Level group mask. */ -#define USART_DREINTLVL_gp 0 /* Data Register Empty Interrupt Level group position. */ -#define USART_DREINTLVL0_bm (1<<0) /* Data Register Empty Interrupt Level bit 0 mask. */ -#define USART_DREINTLVL0_bp 0 /* Data Register Empty Interrupt Level bit 0 position. */ -#define USART_DREINTLVL1_bm (1<<1) /* Data Register Empty Interrupt Level bit 1 mask. */ -#define USART_DREINTLVL1_bp 1 /* Data Register Empty Interrupt Level bit 1 position. */ - - -/* USART.CTRLB bit masks and bit positions */ -#define USART_RXEN_bm 0x10 /* Receiver Enable bit mask. */ -#define USART_RXEN_bp 4 /* Receiver Enable bit position. */ - -#define USART_TXEN_bm 0x08 /* Transmitter Enable bit mask. */ -#define USART_TXEN_bp 3 /* Transmitter Enable bit position. */ - -#define USART_CLK2X_bm 0x04 /* Double transmission speed bit mask. */ -#define USART_CLK2X_bp 2 /* Double transmission speed bit position. */ - -#define USART_MPCM_bm 0x02 /* Multi-processor Communication Mode bit mask. */ -#define USART_MPCM_bp 1 /* Multi-processor Communication Mode bit position. */ - -#define USART_TXB8_bm 0x01 /* Transmit bit 8 bit mask. */ -#define USART_TXB8_bp 0 /* Transmit bit 8 bit position. */ - - -/* USART.CTRLC bit masks and bit positions */ -#define USART_CMODE_gm 0xC0 /* Communication Mode group mask. */ -#define USART_CMODE_gp 6 /* Communication Mode group position. */ -#define USART_CMODE0_bm (1<<6) /* Communication Mode bit 0 mask. */ -#define USART_CMODE0_bp 6 /* Communication Mode bit 0 position. */ -#define USART_CMODE1_bm (1<<7) /* Communication Mode bit 1 mask. */ -#define USART_CMODE1_bp 7 /* Communication Mode bit 1 position. */ - -#define USART_PMODE_gm 0x30 /* Parity Mode group mask. */ -#define USART_PMODE_gp 4 /* Parity Mode group position. */ -#define USART_PMODE0_bm (1<<4) /* Parity Mode bit 0 mask. */ -#define USART_PMODE0_bp 4 /* Parity Mode bit 0 position. */ -#define USART_PMODE1_bm (1<<5) /* Parity Mode bit 1 mask. */ -#define USART_PMODE1_bp 5 /* Parity Mode bit 1 position. */ - -#define USART_SBMODE_bm 0x08 /* Stop Bit Mode bit mask. */ -#define USART_SBMODE_bp 3 /* Stop Bit Mode bit position. */ - -#define USART_CHSIZE_gm 0x07 /* Character Size group mask. */ -#define USART_CHSIZE_gp 0 /* Character Size group position. */ -#define USART_CHSIZE0_bm (1<<0) /* Character Size bit 0 mask. */ -#define USART_CHSIZE0_bp 0 /* Character Size bit 0 position. */ -#define USART_CHSIZE1_bm (1<<1) /* Character Size bit 1 mask. */ -#define USART_CHSIZE1_bp 1 /* Character Size bit 1 position. */ -#define USART_CHSIZE2_bm (1<<2) /* Character Size bit 2 mask. */ -#define USART_CHSIZE2_bp 2 /* Character Size bit 2 position. */ - - -/* USART.BAUDCTRLA bit masks and bit positions */ -#define USART_BSEL_gm 0xFF /* Baud Rate Selection Bits [7:0] group mask. */ -#define USART_BSEL_gp 0 /* Baud Rate Selection Bits [7:0] group position. */ -#define USART_BSEL0_bm (1<<0) /* Baud Rate Selection Bits [7:0] bit 0 mask. */ -#define USART_BSEL0_bp 0 /* Baud Rate Selection Bits [7:0] bit 0 position. */ -#define USART_BSEL1_bm (1<<1) /* Baud Rate Selection Bits [7:0] bit 1 mask. */ -#define USART_BSEL1_bp 1 /* Baud Rate Selection Bits [7:0] bit 1 position. */ -#define USART_BSEL2_bm (1<<2) /* Baud Rate Selection Bits [7:0] bit 2 mask. */ -#define USART_BSEL2_bp 2 /* Baud Rate Selection Bits [7:0] bit 2 position. */ -#define USART_BSEL3_bm (1<<3) /* Baud Rate Selection Bits [7:0] bit 3 mask. */ -#define USART_BSEL3_bp 3 /* Baud Rate Selection Bits [7:0] bit 3 position. */ -#define USART_BSEL4_bm (1<<4) /* Baud Rate Selection Bits [7:0] bit 4 mask. */ -#define USART_BSEL4_bp 4 /* Baud Rate Selection Bits [7:0] bit 4 position. */ -#define USART_BSEL5_bm (1<<5) /* Baud Rate Selection Bits [7:0] bit 5 mask. */ -#define USART_BSEL5_bp 5 /* Baud Rate Selection Bits [7:0] bit 5 position. */ -#define USART_BSEL6_bm (1<<6) /* Baud Rate Selection Bits [7:0] bit 6 mask. */ -#define USART_BSEL6_bp 6 /* Baud Rate Selection Bits [7:0] bit 6 position. */ -#define USART_BSEL7_bm (1<<7) /* Baud Rate Selection Bits [7:0] bit 7 mask. */ -#define USART_BSEL7_bp 7 /* Baud Rate Selection Bits [7:0] bit 7 position. */ - - -/* USART.BAUDCTRLB bit masks and bit positions */ -#define USART_BSCALE_gm 0xF0 /* Baud Rate Scale group mask. */ -#define USART_BSCALE_gp 4 /* Baud Rate Scale group position. */ -#define USART_BSCALE0_bm (1<<4) /* Baud Rate Scale bit 0 mask. */ -#define USART_BSCALE0_bp 4 /* Baud Rate Scale bit 0 position. */ -#define USART_BSCALE1_bm (1<<5) /* Baud Rate Scale bit 1 mask. */ -#define USART_BSCALE1_bp 5 /* Baud Rate Scale bit 1 position. */ -#define USART_BSCALE2_bm (1<<6) /* Baud Rate Scale bit 2 mask. */ -#define USART_BSCALE2_bp 6 /* Baud Rate Scale bit 2 position. */ -#define USART_BSCALE3_bm (1<<7) /* Baud Rate Scale bit 3 mask. */ -#define USART_BSCALE3_bp 7 /* Baud Rate Scale bit 3 position. */ - -/* USART_BSEL_gm Predefined. */ -/* USART_BSEL_gp Predefined. */ -/* USART_BSEL0_bm Predefined. */ -/* USART_BSEL0_bp Predefined. */ -/* USART_BSEL1_bm Predefined. */ -/* USART_BSEL1_bp Predefined. */ -/* USART_BSEL2_bm Predefined. */ -/* USART_BSEL2_bp Predefined. */ -/* USART_BSEL3_bm Predefined. */ -/* USART_BSEL3_bp Predefined. */ - - -/* SPI - Serial Peripheral Interface */ -/* SPI.CTRL bit masks and bit positions */ -#define SPI_CLK2X_bm 0x80 /* Enable Double Speed bit mask. */ -#define SPI_CLK2X_bp 7 /* Enable Double Speed bit position. */ - -#define SPI_ENABLE_bm 0x40 /* Enable Module bit mask. */ -#define SPI_ENABLE_bp 6 /* Enable Module bit position. */ - -#define SPI_DORD_bm 0x20 /* Data Order Setting bit mask. */ -#define SPI_DORD_bp 5 /* Data Order Setting bit position. */ - -#define SPI_MASTER_bm 0x10 /* Master Operation Enable bit mask. */ -#define SPI_MASTER_bp 4 /* Master Operation Enable bit position. */ - -#define SPI_MODE_gm 0x0C /* SPI Mode group mask. */ -#define SPI_MODE_gp 2 /* SPI Mode group position. */ -#define SPI_MODE0_bm (1<<2) /* SPI Mode bit 0 mask. */ -#define SPI_MODE0_bp 2 /* SPI Mode bit 0 position. */ -#define SPI_MODE1_bm (1<<3) /* SPI Mode bit 1 mask. */ -#define SPI_MODE1_bp 3 /* SPI Mode bit 1 position. */ - -#define SPI_PRESCALER_gm 0x03 /* Prescaler group mask. */ -#define SPI_PRESCALER_gp 0 /* Prescaler group position. */ -#define SPI_PRESCALER0_bm (1<<0) /* Prescaler bit 0 mask. */ -#define SPI_PRESCALER0_bp 0 /* Prescaler bit 0 position. */ -#define SPI_PRESCALER1_bm (1<<1) /* Prescaler bit 1 mask. */ -#define SPI_PRESCALER1_bp 1 /* Prescaler bit 1 position. */ - - -/* SPI.INTCTRL bit masks and bit positions */ -#define SPI_INTLVL_gm 0x03 /* Interrupt level group mask. */ -#define SPI_INTLVL_gp 0 /* Interrupt level group position. */ -#define SPI_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */ -#define SPI_INTLVL0_bp 0 /* Interrupt level bit 0 position. */ -#define SPI_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */ -#define SPI_INTLVL1_bp 1 /* Interrupt level bit 1 position. */ - - -/* SPI.STATUS bit masks and bit positions */ -#define SPI_IF_bm 0x80 /* Interrupt Flag bit mask. */ -#define SPI_IF_bp 7 /* Interrupt Flag bit position. */ - -#define SPI_WRCOL_bm 0x40 /* Write Collision bit mask. */ -#define SPI_WRCOL_bp 6 /* Write Collision bit position. */ - - -/* IRCOM - IR Communication Module */ -/* IRCOM.CTRL bit masks and bit positions */ -#define IRCOM_EVSEL_gm 0x0F /* Event Channel Select group mask. */ -#define IRCOM_EVSEL_gp 0 /* Event Channel Select group position. */ -#define IRCOM_EVSEL0_bm (1<<0) /* Event Channel Select bit 0 mask. */ -#define IRCOM_EVSEL0_bp 0 /* Event Channel Select bit 0 position. */ -#define IRCOM_EVSEL1_bm (1<<1) /* Event Channel Select bit 1 mask. */ -#define IRCOM_EVSEL1_bp 1 /* Event Channel Select bit 1 position. */ -#define IRCOM_EVSEL2_bm (1<<2) /* Event Channel Select bit 2 mask. */ -#define IRCOM_EVSEL2_bp 2 /* Event Channel Select bit 2 position. */ -#define IRCOM_EVSEL3_bm (1<<3) /* Event Channel Select bit 3 mask. */ -#define IRCOM_EVSEL3_bp 3 /* Event Channel Select bit 3 position. */ - - -/* AES - AES Module */ -/* AES.CTRL bit masks and bit positions */ -#define AES_START_bm 0x80 /* Start/Run bit mask. */ -#define AES_START_bp 7 /* Start/Run bit position. */ - -#define AES_AUTO_bm 0x40 /* Auto Start Trigger bit mask. */ -#define AES_AUTO_bp 6 /* Auto Start Trigger bit position. */ - -#define AES_RESET_bm 0x20 /* AES Software Reset bit mask. */ -#define AES_RESET_bp 5 /* AES Software Reset bit position. */ - -#define AES_DECRYPT_bm 0x10 /* Decryption / Direction bit mask. */ -#define AES_DECRYPT_bp 4 /* Decryption / Direction bit position. */ - -#define AES_XOR_bm 0x04 /* State XOR Load Enable bit mask. */ -#define AES_XOR_bp 2 /* State XOR Load Enable bit position. */ - - -/* AES.STATUS bit masks and bit positions */ -#define AES_ERROR_bm 0x80 /* AES Error bit mask. */ -#define AES_ERROR_bp 7 /* AES Error bit position. */ - -#define AES_SRIF_bm 0x01 /* State Ready Interrupt Flag bit mask. */ -#define AES_SRIF_bp 0 /* State Ready Interrupt Flag bit position. */ - - -/* AES.INTCTRL bit masks and bit positions */ -#define AES_INTLVL_gm 0x03 /* Interrupt level group mask. */ -#define AES_INTLVL_gp 0 /* Interrupt level group position. */ -#define AES_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */ -#define AES_INTLVL0_bp 0 /* Interrupt level bit 0 position. */ -#define AES_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */ -#define AES_INTLVL1_bp 1 /* Interrupt level bit 1 position. */ - - - -// Generic Port Pins - -#define PIN0_bm 0x01 -#define PIN0_bp 0 -#define PIN1_bm 0x02 -#define PIN1_bp 1 -#define PIN2_bm 0x04 -#define PIN2_bp 2 -#define PIN3_bm 0x08 -#define PIN3_bp 3 -#define PIN4_bm 0x10 -#define PIN4_bp 4 -#define PIN5_bm 0x20 -#define PIN5_bp 5 -#define PIN6_bm 0x40 -#define PIN6_bp 6 -#define PIN7_bm 0x80 -#define PIN7_bp 7 - - -/* ========== Interrupt Vector Definitions ========== */ -/* Vector 0 is the reset vector */ - -/* OSC interrupt vectors */ -#define OSC_XOSCF_vect_num 1 -#define OSC_XOSCF_vect _VECTOR(1) /* External Oscillator Failure Interrupt (NMI) */ - -/* PORTC interrupt vectors */ -#define PORTC_INT0_vect_num 2 -#define PORTC_INT0_vect _VECTOR(2) /* External Interrupt 0 */ -#define PORTC_INT1_vect_num 3 -#define PORTC_INT1_vect _VECTOR(3) /* External Interrupt 1 */ - -/* PORTR interrupt vectors */ -#define PORTR_INT0_vect_num 4 -#define PORTR_INT0_vect _VECTOR(4) /* External Interrupt 0 */ -#define PORTR_INT1_vect_num 5 -#define PORTR_INT1_vect _VECTOR(5) /* External Interrupt 1 */ - -/* DMA interrupt vectors */ -#define DMA_CH0_vect_num 6 -#define DMA_CH0_vect _VECTOR(6) /* Channel 0 Interrupt */ -#define DMA_CH1_vect_num 7 -#define DMA_CH1_vect _VECTOR(7) /* Channel 1 Interrupt */ -#define DMA_CH2_vect_num 8 -#define DMA_CH2_vect _VECTOR(8) /* Channel 2 Interrupt */ -#define DMA_CH3_vect_num 9 -#define DMA_CH3_vect _VECTOR(9) /* Channel 3 Interrupt */ - -/* RTC interrupt vectors */ -#define RTC_OVF_vect_num 10 -#define RTC_OVF_vect _VECTOR(10) /* Overflow Interrupt */ -#define RTC_COMP_vect_num 11 -#define RTC_COMP_vect _VECTOR(11) /* Compare Interrupt */ - -/* TWIC interrupt vectors */ -#define TWIC_TWIS_vect_num 12 -#define TWIC_TWIS_vect _VECTOR(12) /* TWI Slave Interrupt */ -#define TWIC_TWIM_vect_num 13 -#define TWIC_TWIM_vect _VECTOR(13) /* TWI Master Interrupt */ - -/* TCC0 interrupt vectors */ -#define TCC0_OVF_vect_num 14 -#define TCC0_OVF_vect _VECTOR(14) /* Overflow Interrupt */ -#define TCC0_ERR_vect_num 15 -#define TCC0_ERR_vect _VECTOR(15) /* Error Interrupt */ -#define TCC0_CCA_vect_num 16 -#define TCC0_CCA_vect _VECTOR(16) /* Compare or Capture A Interrupt */ -#define TCC0_CCB_vect_num 17 -#define TCC0_CCB_vect _VECTOR(17) /* Compare or Capture B Interrupt */ -#define TCC0_CCC_vect_num 18 -#define TCC0_CCC_vect _VECTOR(18) /* Compare or Capture C Interrupt */ -#define TCC0_CCD_vect_num 19 -#define TCC0_CCD_vect _VECTOR(19) /* Compare or Capture D Interrupt */ - -/* TCC1 interrupt vectors */ -#define TCC1_OVF_vect_num 20 -#define TCC1_OVF_vect _VECTOR(20) /* Overflow Interrupt */ -#define TCC1_ERR_vect_num 21 -#define TCC1_ERR_vect _VECTOR(21) /* Error Interrupt */ -#define TCC1_CCA_vect_num 22 -#define TCC1_CCA_vect _VECTOR(22) /* Compare or Capture A Interrupt */ -#define TCC1_CCB_vect_num 23 -#define TCC1_CCB_vect _VECTOR(23) /* Compare or Capture B Interrupt */ - -/* SPIC interrupt vectors */ -#define SPIC_INT_vect_num 24 -#define SPIC_INT_vect _VECTOR(24) /* SPI Interrupt */ - -/* USARTC0 interrupt vectors */ -#define USARTC0_RXC_vect_num 25 -#define USARTC0_RXC_vect _VECTOR(25) /* Reception Complete Interrupt */ -#define USARTC0_DRE_vect_num 26 -#define USARTC0_DRE_vect _VECTOR(26) /* Data Register Empty Interrupt */ -#define USARTC0_TXC_vect_num 27 -#define USARTC0_TXC_vect _VECTOR(27) /* Transmission Complete Interrupt */ - -/* USARTC1 interrupt vectors */ -#define USARTC1_RXC_vect_num 28 -#define USARTC1_RXC_vect _VECTOR(28) /* Reception Complete Interrupt */ -#define USARTC1_DRE_vect_num 29 -#define USARTC1_DRE_vect _VECTOR(29) /* Data Register Empty Interrupt */ -#define USARTC1_TXC_vect_num 30 -#define USARTC1_TXC_vect _VECTOR(30) /* Transmission Complete Interrupt */ - -/* AES interrupt vectors */ -#define AES_INT_vect_num 31 -#define AES_INT_vect _VECTOR(31) /* AES Interrupt */ - -/* NVM interrupt vectors */ -#define NVM_EE_vect_num 32 -#define NVM_EE_vect _VECTOR(32) /* EE Interrupt */ -#define NVM_SPM_vect_num 33 -#define NVM_SPM_vect _VECTOR(33) /* SPM Interrupt */ - -/* PORTB interrupt vectors */ -#define PORTB_INT0_vect_num 34 -#define PORTB_INT0_vect _VECTOR(34) /* External Interrupt 0 */ -#define PORTB_INT1_vect_num 35 -#define PORTB_INT1_vect _VECTOR(35) /* External Interrupt 1 */ - -/* ACB interrupt vectors */ -#define ACB_AC0_vect_num 36 -#define ACB_AC0_vect _VECTOR(36) /* AC0 Interrupt */ -#define ACB_AC1_vect_num 37 -#define ACB_AC1_vect _VECTOR(37) /* AC1 Interrupt */ -#define ACB_ACW_vect_num 38 -#define ACB_ACW_vect _VECTOR(38) /* ACW Window Mode Interrupt */ - -/* ADCB interrupt vectors */ -#define ADCB_CH0_vect_num 39 -#define ADCB_CH0_vect _VECTOR(39) /* Interrupt 0 */ -#define ADCB_CH1_vect_num 40 -#define ADCB_CH1_vect _VECTOR(40) /* Interrupt 1 */ -#define ADCB_CH2_vect_num 41 -#define ADCB_CH2_vect _VECTOR(41) /* Interrupt 2 */ -#define ADCB_CH3_vect_num 42 -#define ADCB_CH3_vect _VECTOR(42) /* Interrupt 3 */ - -/* PORTE interrupt vectors */ -#define PORTE_INT0_vect_num 43 -#define PORTE_INT0_vect _VECTOR(43) /* External Interrupt 0 */ -#define PORTE_INT1_vect_num 44 -#define PORTE_INT1_vect _VECTOR(44) /* External Interrupt 1 */ - -/* TWIE interrupt vectors */ -#define TWIE_TWIS_vect_num 45 -#define TWIE_TWIS_vect _VECTOR(45) /* TWI Slave Interrupt */ -#define TWIE_TWIM_vect_num 46 -#define TWIE_TWIM_vect _VECTOR(46) /* TWI Master Interrupt */ - -/* TCE0 interrupt vectors */ -#define TCE0_OVF_vect_num 47 -#define TCE0_OVF_vect _VECTOR(47) /* Overflow Interrupt */ -#define TCE0_ERR_vect_num 48 -#define TCE0_ERR_vect _VECTOR(48) /* Error Interrupt */ -#define TCE0_CCA_vect_num 49 -#define TCE0_CCA_vect _VECTOR(49) /* Compare or Capture A Interrupt */ -#define TCE0_CCB_vect_num 50 -#define TCE0_CCB_vect _VECTOR(50) /* Compare or Capture B Interrupt */ -#define TCE0_CCC_vect_num 51 -#define TCE0_CCC_vect _VECTOR(51) /* Compare or Capture C Interrupt */ -#define TCE0_CCD_vect_num 52 -#define TCE0_CCD_vect _VECTOR(52) /* Compare or Capture D Interrupt */ - -/* TCE1 interrupt vectors */ -#define TCE1_OVF_vect_num 53 -#define TCE1_OVF_vect _VECTOR(53) /* Overflow Interrupt */ -#define TCE1_ERR_vect_num 54 -#define TCE1_ERR_vect _VECTOR(54) /* Error Interrupt */ -#define TCE1_CCA_vect_num 55 -#define TCE1_CCA_vect _VECTOR(55) /* Compare or Capture A Interrupt */ -#define TCE1_CCB_vect_num 56 -#define TCE1_CCB_vect _VECTOR(56) /* Compare or Capture B Interrupt */ - -/* SPIE interrupt vectors */ -#define SPIE_INT_vect_num 57 -#define SPIE_INT_vect _VECTOR(57) /* SPI Interrupt */ - -/* USARTE0 interrupt vectors */ -#define USARTE0_RXC_vect_num 58 -#define USARTE0_RXC_vect _VECTOR(58) /* Reception Complete Interrupt */ -#define USARTE0_DRE_vect_num 59 -#define USARTE0_DRE_vect _VECTOR(59) /* Data Register Empty Interrupt */ -#define USARTE0_TXC_vect_num 60 -#define USARTE0_TXC_vect _VECTOR(60) /* Transmission Complete Interrupt */ - -/* USARTE1 interrupt vectors */ -#define USARTE1_RXC_vect_num 61 -#define USARTE1_RXC_vect _VECTOR(61) /* Reception Complete Interrupt */ -#define USARTE1_DRE_vect_num 62 -#define USARTE1_DRE_vect _VECTOR(62) /* Data Register Empty Interrupt */ -#define USARTE1_TXC_vect_num 63 -#define USARTE1_TXC_vect _VECTOR(63) /* Transmission Complete Interrupt */ - -/* PORTD interrupt vectors */ -#define PORTD_INT0_vect_num 64 -#define PORTD_INT0_vect _VECTOR(64) /* External Interrupt 0 */ -#define PORTD_INT1_vect_num 65 -#define PORTD_INT1_vect _VECTOR(65) /* External Interrupt 1 */ - -/* PORTA interrupt vectors */ -#define PORTA_INT0_vect_num 66 -#define PORTA_INT0_vect _VECTOR(66) /* External Interrupt 0 */ -#define PORTA_INT1_vect_num 67 -#define PORTA_INT1_vect _VECTOR(67) /* External Interrupt 1 */ - -/* ACA interrupt vectors */ -#define ACA_AC0_vect_num 68 -#define ACA_AC0_vect _VECTOR(68) /* AC0 Interrupt */ -#define ACA_AC1_vect_num 69 -#define ACA_AC1_vect _VECTOR(69) /* AC1 Interrupt */ -#define ACA_ACW_vect_num 70 -#define ACA_ACW_vect _VECTOR(70) /* ACW Window Mode Interrupt */ - -/* ADCA interrupt vectors */ -#define ADCA_CH0_vect_num 71 -#define ADCA_CH0_vect _VECTOR(71) /* Interrupt 0 */ -#define ADCA_CH1_vect_num 72 -#define ADCA_CH1_vect _VECTOR(72) /* Interrupt 1 */ -#define ADCA_CH2_vect_num 73 -#define ADCA_CH2_vect _VECTOR(73) /* Interrupt 2 */ -#define ADCA_CH3_vect_num 74 -#define ADCA_CH3_vect _VECTOR(74) /* Interrupt 3 */ - -/* TWID interrupt vectors */ -#define TWID_TWIS_vect_num 75 -#define TWID_TWIS_vect _VECTOR(75) /* TWI Slave Interrupt */ -#define TWID_TWIM_vect_num 76 -#define TWID_TWIM_vect _VECTOR(76) /* TWI Master Interrupt */ - -/* TCD0 interrupt vectors */ -#define TCD0_OVF_vect_num 77 -#define TCD0_OVF_vect _VECTOR(77) /* Overflow Interrupt */ -#define TCD0_ERR_vect_num 78 -#define TCD0_ERR_vect _VECTOR(78) /* Error Interrupt */ -#define TCD0_CCA_vect_num 79 -#define TCD0_CCA_vect _VECTOR(79) /* Compare or Capture A Interrupt */ -#define TCD0_CCB_vect_num 80 -#define TCD0_CCB_vect _VECTOR(80) /* Compare or Capture B Interrupt */ -#define TCD0_CCC_vect_num 81 -#define TCD0_CCC_vect _VECTOR(81) /* Compare or Capture C Interrupt */ -#define TCD0_CCD_vect_num 82 -#define TCD0_CCD_vect _VECTOR(82) /* Compare or Capture D Interrupt */ - -/* TCD1 interrupt vectors */ -#define TCD1_OVF_vect_num 83 -#define TCD1_OVF_vect _VECTOR(83) /* Overflow Interrupt */ -#define TCD1_ERR_vect_num 84 -#define TCD1_ERR_vect _VECTOR(84) /* Error Interrupt */ -#define TCD1_CCA_vect_num 85 -#define TCD1_CCA_vect _VECTOR(85) /* Compare or Capture A Interrupt */ -#define TCD1_CCB_vect_num 86 -#define TCD1_CCB_vect _VECTOR(86) /* Compare or Capture B Interrupt */ - -/* SPID interrupt vectors */ -#define SPID_INT_vect_num 87 -#define SPID_INT_vect _VECTOR(87) /* SPI Interrupt */ - -/* USARTD0 interrupt vectors */ -#define USARTD0_RXC_vect_num 88 -#define USARTD0_RXC_vect _VECTOR(88) /* Reception Complete Interrupt */ -#define USARTD0_DRE_vect_num 89 -#define USARTD0_DRE_vect _VECTOR(89) /* Data Register Empty Interrupt */ -#define USARTD0_TXC_vect_num 90 -#define USARTD0_TXC_vect _VECTOR(90) /* Transmission Complete Interrupt */ - -/* USARTD1 interrupt vectors */ -#define USARTD1_RXC_vect_num 91 -#define USARTD1_RXC_vect _VECTOR(91) /* Reception Complete Interrupt */ -#define USARTD1_DRE_vect_num 92 -#define USARTD1_DRE_vect _VECTOR(92) /* Data Register Empty Interrupt */ -#define USARTD1_TXC_vect_num 93 -#define USARTD1_TXC_vect _VECTOR(93) /* Transmission Complete Interrupt */ - -/* PORTQ interrupt vectors */ -#define PORTQ_INT0_vect_num 94 -#define PORTQ_INT0_vect _VECTOR(94) /* External Interrupt 0 */ -#define PORTQ_INT1_vect_num 95 -#define PORTQ_INT1_vect _VECTOR(95) /* External Interrupt 1 */ - -/* PORTH interrupt vectors */ -#define PORTH_INT0_vect_num 96 -#define PORTH_INT0_vect _VECTOR(96) /* External Interrupt 0 */ -#define PORTH_INT1_vect_num 97 -#define PORTH_INT1_vect _VECTOR(97) /* External Interrupt 1 */ - -/* PORTJ interrupt vectors */ -#define PORTJ_INT0_vect_num 98 -#define PORTJ_INT0_vect _VECTOR(98) /* External Interrupt 0 */ -#define PORTJ_INT1_vect_num 99 -#define PORTJ_INT1_vect _VECTOR(99) /* External Interrupt 1 */ - -/* PORTK interrupt vectors */ -#define PORTK_INT0_vect_num 100 -#define PORTK_INT0_vect _VECTOR(100) /* External Interrupt 0 */ -#define PORTK_INT1_vect_num 101 -#define PORTK_INT1_vect _VECTOR(101) /* External Interrupt 1 */ - -/* PORTF interrupt vectors */ -#define PORTF_INT0_vect_num 104 -#define PORTF_INT0_vect _VECTOR(104) /* External Interrupt 0 */ -#define PORTF_INT1_vect_num 105 -#define PORTF_INT1_vect _VECTOR(105) /* External Interrupt 1 */ - -/* TWIF interrupt vectors */ -#define TWIF_TWIS_vect_num 106 -#define TWIF_TWIS_vect _VECTOR(106) /* TWI Slave Interrupt */ -#define TWIF_TWIM_vect_num 107 -#define TWIF_TWIM_vect _VECTOR(107) /* TWI Master Interrupt */ - -/* TCF0 interrupt vectors */ -#define TCF0_OVF_vect_num 108 -#define TCF0_OVF_vect _VECTOR(108) /* Overflow Interrupt */ -#define TCF0_ERR_vect_num 109 -#define TCF0_ERR_vect _VECTOR(109) /* Error Interrupt */ -#define TCF0_CCA_vect_num 110 -#define TCF0_CCA_vect _VECTOR(110) /* Compare or Capture A Interrupt */ -#define TCF0_CCB_vect_num 111 -#define TCF0_CCB_vect _VECTOR(111) /* Compare or Capture B Interrupt */ -#define TCF0_CCC_vect_num 112 -#define TCF0_CCC_vect _VECTOR(112) /* Compare or Capture C Interrupt */ -#define TCF0_CCD_vect_num 113 -#define TCF0_CCD_vect _VECTOR(113) /* Compare or Capture D Interrupt */ - -/* TCF1 interrupt vectors */ -#define TCF1_OVF_vect_num 114 -#define TCF1_OVF_vect _VECTOR(114) /* Overflow Interrupt */ -#define TCF1_ERR_vect_num 115 -#define TCF1_ERR_vect _VECTOR(115) /* Error Interrupt */ -#define TCF1_CCA_vect_num 116 -#define TCF1_CCA_vect _VECTOR(116) /* Compare or Capture A Interrupt */ -#define TCF1_CCB_vect_num 117 -#define TCF1_CCB_vect _VECTOR(117) /* Compare or Capture B Interrupt */ - -/* SPIF interrupt vectors */ -#define SPIF_INT_vect_num 118 -#define SPIF_INT_vect _VECTOR(118) /* SPI Interrupt */ - -/* USARTF0 interrupt vectors */ -#define USARTF0_RXC_vect_num 119 -#define USARTF0_RXC_vect _VECTOR(119) /* Reception Complete Interrupt */ -#define USARTF0_DRE_vect_num 120 -#define USARTF0_DRE_vect _VECTOR(120) /* Data Register Empty Interrupt */ -#define USARTF0_TXC_vect_num 121 -#define USARTF0_TXC_vect _VECTOR(121) /* Transmission Complete Interrupt */ - -/* USARTF1 interrupt vectors */ -#define USARTF1_RXC_vect_num 122 -#define USARTF1_RXC_vect _VECTOR(122) /* Reception Complete Interrupt */ -#define USARTF1_DRE_vect_num 123 -#define USARTF1_DRE_vect _VECTOR(123) /* Data Register Empty Interrupt */ -#define USARTF1_TXC_vect_num 124 -#define USARTF1_TXC_vect _VECTOR(124) /* Transmission Complete Interrupt */ - - -#define _VECTOR_SIZE 4 /* Size of individual vector. */ -#define _VECTORS_SIZE (125 * _VECTOR_SIZE) - - -/* ========== Constants ========== */ - -#define PROGMEM_START (0x0000) -#define PROGMEM_SIZE (139264) -#define PROGMEM_PAGE_SIZE (512) -#define PROGMEM_END (PROGMEM_START + PROGMEM_SIZE - 1) - -#define APP_SECTION_START (0x0000) -#define APP_SECTION_SIZE (131072) -#define APP_SECTION_PAGE_SIZE (512) -#define APP_SECTION_END (APP_SECTION_START + APP_SECTION_SIZE - 1) - -#define APPTABLE_SECTION_START (0x1E000) -#define APPTABLE_SECTION_SIZE (8192) -#define APPTABLE_SECTION_PAGE_SIZE (512) -#define APPTABLE_SECTION_END (APPTABLE_SECTION_START + APPTABLE_SECTION_SIZE - 1) - -#define BOOT_SECTION_START (0x20000) -#define BOOT_SECTION_SIZE (8192) -#define BOOT_SECTION_PAGE_SIZE (512) -#define BOOT_SECTION_END (BOOT_SECTION_START + BOOT_SECTION_SIZE - 1) - -#define DATAMEM_START (0x0000) -#define DATAMEM_SIZE (16777216) -#define DATAMEM_PAGE_SIZE (0) -#define DATAMEM_END (DATAMEM_START + DATAMEM_SIZE - 1) - -#define IO_START (0x0000) -#define IO_SIZE (4096) -#define IO_PAGE_SIZE (0) -#define IO_END (IO_START + IO_SIZE - 1) - -#define MAPPED_EEPROM_START (0x1000) -#define MAPPED_EEPROM_SIZE (2048) -#define MAPPED_EEPROM_PAGE_SIZE (0) -#define MAPPED_EEPROM_END (MAPPED_EEPROM_START + MAPPED_EEPROM_SIZE - 1) - -#define INTERNAL_SRAM_START (0x2000) -#define INTERNAL_SRAM_SIZE (8192) -#define INTERNAL_SRAM_PAGE_SIZE (0) -#define INTERNAL_SRAM_END (INTERNAL_SRAM_START + INTERNAL_SRAM_SIZE - 1) - -#define EXTERNAL_SRAM_START (0x4000) -#define EXTERNAL_SRAM_SIZE (16760832) -#define EXTERNAL_SRAM_PAGE_SIZE (0) -#define EXTERNAL_SRAM_END (EXTERNAL_SRAM_START + EXTERNAL_SRAM_SIZE - 1) - -#define EEPROM_START (0x0000) -#define EEPROM_SIZE (2048) -#define EEPROM_PAGE_SIZE (32) -#define EEPROM_END (EEPROM_START + EEPROM_SIZE - 1) - -#define FUSE_START (0x0000) -#define FUSE_SIZE (6) -#define FUSE_PAGE_SIZE (0) -#define FUSE_END (FUSE_START + FUSE_SIZE - 1) - -#define LOCKBIT_START (0x0000) -#define LOCKBIT_SIZE (1) -#define LOCKBIT_PAGE_SIZE (0) -#define LOCKBIT_END (LOCKBIT_START + LOCKBIT_SIZE - 1) - -#define SIGNATURES_START (0x0000) -#define SIGNATURES_SIZE (3) -#define SIGNATURES_PAGE_SIZE (0) -#define SIGNATURES_END (SIGNATURES_START + SIGNATURES_SIZE - 1) - -#define USER_SIGNATURES_START (0x0000) -#define USER_SIGNATURES_SIZE (512) -#define USER_SIGNATURES_PAGE_SIZE (0) -#define USER_SIGNATURES_END (USER_SIGNATURES_START + USER_SIGNATURES_SIZE - 1) - -#define PROD_SIGNATURES_START (0x0000) -#define PROD_SIGNATURES_SIZE (52) -#define PROD_SIGNATURES_PAGE_SIZE (0) -#define PROD_SIGNATURES_END (PROD_SIGNATURES_START + PROD_SIGNATURES_SIZE - 1) - -#define FLASHEND PROGMEM_END -#define SPM_PAGESIZE PROGMEM_PAGE_SIZE -#define RAMSTART INTERNAL_SRAM_START -#define RAMSIZE INTERNAL_SRAM_SIZE -#define RAMEND INTERNAL_SRAM_END -#define XRAMSTART EXTERNAL_SRAM_START -#define XRAMSIZE EXTERNAL_SRAM_SIZE -#define XRAMEND EXTERNAL_SRAM_END -#define E2END EEPROM_END -#define E2PAGESIZE EEPROM_PAGE_SIZE - - -/* ========== Fuses ========== */ -#define FUSE_MEMORY_SIZE 6 - -/* Fuse Byte 0 */ -#define FUSE_JTAGUSERID0 (unsigned char)~_BV(0) /* JTAG User ID Bit 0 */ -#define FUSE_JTAGUSERID1 (unsigned char)~_BV(1) /* JTAG User ID Bit 1 */ -#define FUSE_JTAGUSERID2 (unsigned char)~_BV(2) /* JTAG User ID Bit 2 */ -#define FUSE_JTAGUSERID3 (unsigned char)~_BV(3) /* JTAG User ID Bit 3 */ -#define FUSE_JTAGUSERID4 (unsigned char)~_BV(4) /* JTAG User ID Bit 4 */ -#define FUSE_JTAGUSERID5 (unsigned char)~_BV(5) /* JTAG User ID Bit 5 */ -#define FUSE_JTAGUSERID6 (unsigned char)~_BV(6) /* JTAG User ID Bit 6 */ -#define FUSE_JTAGUSERID7 (unsigned char)~_BV(7) /* JTAG User ID Bit 7 */ -#define FUSE0_DEFAULT (0xFF) - -/* Fuse Byte 1 */ -#define FUSE_WDP0 (unsigned char)~_BV(0) /* Watchdog Timeout Period Bit 0 */ -#define FUSE_WDP1 (unsigned char)~_BV(1) /* Watchdog Timeout Period Bit 1 */ -#define FUSE_WDP2 (unsigned char)~_BV(2) /* Watchdog Timeout Period Bit 2 */ -#define FUSE_WDP3 (unsigned char)~_BV(3) /* Watchdog Timeout Period Bit 3 */ -#define FUSE_WDWP0 (unsigned char)~_BV(4) /* Watchdog Window Timeout Period Bit 0 */ -#define FUSE_WDWP1 (unsigned char)~_BV(5) /* Watchdog Window Timeout Period Bit 1 */ -#define FUSE_WDWP2 (unsigned char)~_BV(6) /* Watchdog Window Timeout Period Bit 2 */ -#define FUSE_WDWP3 (unsigned char)~_BV(7) /* Watchdog Window Timeout Period Bit 3 */ -#define FUSE1_DEFAULT (0xFF) - -/* Fuse Byte 2 */ -#define FUSE_BODPD0 (unsigned char)~_BV(0) /* BOD Operation in Power-Down Mode Bit 0 */ -#define FUSE_BODPD1 (unsigned char)~_BV(1) /* BOD Operation in Power-Down Mode Bit 1 */ -#define FUSE_BODACT0 (unsigned char)~_BV(2) /* BOD Operation in Active Mode Bit 0 */ -#define FUSE_BODACT1 (unsigned char)~_BV(3) /* BOD Operation in Active Mode Bit 1 */ -#define FUSE_BOOTRST (unsigned char)~_BV(6) /* Boot Loader Section Reset Vector */ -#define FUSE_DVSDON (unsigned char)~_BV(7) /* Spike Detector Enable */ -#define FUSE2_DEFAULT (0xFF) - -/* Fuse Byte 3 Reserved */ - -/* Fuse Byte 4 */ -#define FUSE_JTAGEN (unsigned char)~_BV(0) /* JTAG Interface Enable */ -#define FUSE_WDLOCK (unsigned char)~_BV(1) /* Watchdog Timer Lock */ -#define FUSE_SUT0 (unsigned char)~_BV(2) /* Start-up Time Bit 0 */ -#define FUSE_SUT1 (unsigned char)~_BV(3) /* Start-up Time Bit 1 */ -#define FUSE4_DEFAULT (0xFF) - -/* Fuse Byte 5 */ -#define FUSE_BODLVL0 (unsigned char)~_BV(0) /* Brown Out Detection Voltage Level Bit 0 */ -#define FUSE_BODLVL1 (unsigned char)~_BV(1) /* Brown Out Detection Voltage Level Bit 1 */ -#define FUSE_BODLVL2 (unsigned char)~_BV(2) /* Brown Out Detection Voltage Level Bit 2 */ -#define FUSE_EESAVE (unsigned char)~_BV(3) /* Preserve EEPROM Through Chip Erase */ -#define FUSE5_DEFAULT (0xFF) - - -/* ========== Lock Bits ========== */ -#define __LOCK_BITS_EXIST -#define __BOOT_LOCK_APPLICATION_TABLE_BITS_EXIST -#define __BOOT_LOCK_APPLICATION_BITS_EXIST -#define __BOOT_LOCK_BOOT_BITS_EXIST - - -/* ========== Signature ========== */ -#define SIGNATURE_0 0x1E -#define SIGNATURE_1 0x97 -#define SIGNATURE_2 0x4C - -/* ========== Power Reduction Condition Definitions ========== */ - -/* PR.PRGEN */ -#define __AVR_HAVE_PRGEN (PR_AES_bm|PR_EBI_bm|PR_RTC_bm|PR_EVSYS_bm|PR_DMA_bm) -#define __AVR_HAVE_PRGEN_AES -#define __AVR_HAVE_PRGEN_EBI -#define __AVR_HAVE_PRGEN_RTC -#define __AVR_HAVE_PRGEN_EVSYS -#define __AVR_HAVE_PRGEN_DMA - -/* PR.PRPA */ -#define __AVR_HAVE_PRPA (PR_DAC_bm|PR_ADC_bm|PR_AC_bm) -#define __AVR_HAVE_PRPA_DAC -#define __AVR_HAVE_PRPA_ADC -#define __AVR_HAVE_PRPA_AC - -/* PR.PRPB */ -#define __AVR_HAVE_PRPB (PR_DAC_bm|PR_ADC_bm|PR_AC_bm) -#define __AVR_HAVE_PRPB_DAC -#define __AVR_HAVE_PRPB_ADC -#define __AVR_HAVE_PRPB_AC - -/* PR.PRPC */ -#define __AVR_HAVE_PRPC (PR_TWI_bm|PR_USART1_bm|PR_USART0_bm|PR_SPI_bm|PR_HIRES_bm|PR_TC1_bm|PR_TC0_bm) -#define __AVR_HAVE_PRPC_TWI -#define __AVR_HAVE_PRPC_USART1 -#define __AVR_HAVE_PRPC_USART0 -#define __AVR_HAVE_PRPC_SPI -#define __AVR_HAVE_PRPC_HIRES -#define __AVR_HAVE_PRPC_TC1 -#define __AVR_HAVE_PRPC_TC0 - -/* PR.PRPD */ -#define __AVR_HAVE_PRPD (PR_TWI_bm|PR_USART1_bm|PR_USART0_bm|PR_SPI_bm|PR_HIRES_bm|PR_TC1_bm|PR_TC0_bm) -#define __AVR_HAVE_PRPD_TWI -#define __AVR_HAVE_PRPD_USART1 -#define __AVR_HAVE_PRPD_USART0 -#define __AVR_HAVE_PRPD_SPI -#define __AVR_HAVE_PRPD_HIRES -#define __AVR_HAVE_PRPD_TC1 -#define __AVR_HAVE_PRPD_TC0 - -/* PR.PRPE */ -#define __AVR_HAVE_PRPE (PR_TWI_bm|PR_USART1_bm|PR_USART0_bm|PR_SPI_bm|PR_HIRES_bm|PR_TC1_bm|PR_TC0_bm) -#define __AVR_HAVE_PRPE_TWI -#define __AVR_HAVE_PRPE_USART1 -#define __AVR_HAVE_PRPE_USART0 -#define __AVR_HAVE_PRPE_SPI -#define __AVR_HAVE_PRPE_HIRES -#define __AVR_HAVE_PRPE_TC1 -#define __AVR_HAVE_PRPE_TC0 - -/* PR.PRPF */ -#define __AVR_HAVE_PRPF (PR_TWI_bm|PR_USART1_bm|PR_USART0_bm|PR_SPI_bm|PR_HIRES_bm|PR_TC1_bm|PR_TC0_bm) -#define __AVR_HAVE_PRPF_TWI -#define __AVR_HAVE_PRPF_USART1 -#define __AVR_HAVE_PRPF_USART0 -#define __AVR_HAVE_PRPF_SPI -#define __AVR_HAVE_PRPF_HIRES -#define __AVR_HAVE_PRPF_TC1 -#define __AVR_HAVE_PRPF_TC0 - - -#endif /* _AVR_ATxmega128A1_H_ */ - diff --git a/arduino/hardware/tools/avr/avr/include/avr/iox128a1u.h b/arduino/hardware/tools/avr/avr/include/avr/iox128a1u.h deleted file mode 100644 index 72f0ce8..0000000 --- a/arduino/hardware/tools/avr/avr/include/avr/iox128a1u.h +++ /dev/null @@ -1,8305 +0,0 @@ -/***************************************************************************** - * - * Copyright (C) 2015 Atmel Corporation - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * - * * Neither the name of the copyright holders nor the names of - * contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - ****************************************************************************/ - - -#ifndef _AVR_IO_H_ -# error "Include instead of this file." -#endif - -#ifndef _AVR_IOXXX_H_ -# define _AVR_IOXXX_H_ "iox128a1u.h" -#else -# error "Attempt to include more than one file." -#endif - -#ifndef _AVR_ATXMEGA128A1U_H_INCLUDED -#define _AVR_ATXMEGA128A1U_H_INCLUDED - -/* Ungrouped common registers */ -#define GPIOR0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ -#define GPIOR1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ -#define GPIOR2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ -#define GPIOR3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ -#define GPIOR4 _SFR_MEM8(0x0004) /* General Purpose IO Register 4 */ -#define GPIOR5 _SFR_MEM8(0x0005) /* General Purpose IO Register 5 */ -#define GPIOR6 _SFR_MEM8(0x0006) /* General Purpose IO Register 6 */ -#define GPIOR7 _SFR_MEM8(0x0007) /* General Purpose IO Register 7 */ -#define GPIOR8 _SFR_MEM8(0x0008) /* General Purpose IO Register 8 */ -#define GPIOR9 _SFR_MEM8(0x0009) /* General Purpose IO Register 9 */ -#define GPIORA _SFR_MEM8(0x000A) /* General Purpose IO Register 10 */ -#define GPIORB _SFR_MEM8(0x000B) /* General Purpose IO Register 11 */ -#define GPIORC _SFR_MEM8(0x000C) /* General Purpose IO Register 12 */ -#define GPIORD _SFR_MEM8(0x000D) /* General Purpose IO Register 13 */ -#define GPIORE _SFR_MEM8(0x000E) /* General Purpose IO Register 14 */ -#define GPIORF _SFR_MEM8(0x000F) /* General Purpose IO Register 15 */ - -/* Deprecated */ -#define GPIO0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ -#define GPIO1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ -#define GPIO2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ -#define GPIO3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ -#define GPIO4 _SFR_MEM8(0x0004) /* General Purpose IO Register 4 */ -#define GPIO5 _SFR_MEM8(0x0005) /* General Purpose IO Register 5 */ -#define GPIO6 _SFR_MEM8(0x0006) /* General Purpose IO Register 6 */ -#define GPIO7 _SFR_MEM8(0x0007) /* General Purpose IO Register 7 */ -#define GPIO8 _SFR_MEM8(0x0008) /* General Purpose IO Register 8 */ -#define GPIO9 _SFR_MEM8(0x0009) /* General Purpose IO Register 9 */ -#define GPIOA _SFR_MEM8(0x000A) /* General Purpose IO Register 10 */ -#define GPIOB _SFR_MEM8(0x000B) /* General Purpose IO Register 11 */ -#define GPIOC _SFR_MEM8(0x000C) /* General Purpose IO Register 12 */ -#define GPIOD _SFR_MEM8(0x000D) /* General Purpose IO Register 13 */ -#define GPIOE _SFR_MEM8(0x000E) /* General Purpose IO Register 14 */ -#define GPIOF _SFR_MEM8(0x000F) /* General Purpose IO Register 15 */ - -#define CCP _SFR_MEM8(0x0034) /* Configuration Change Protection */ -#define RAMPD _SFR_MEM8(0x0038) /* Ramp D */ -#define RAMPX _SFR_MEM8(0x0039) /* Ramp X */ -#define RAMPY _SFR_MEM8(0x003A) /* Ramp Y */ -#define RAMPZ _SFR_MEM8(0x003B) /* Ramp Z */ -#define EIND _SFR_MEM8(0x003C) /* Extended Indirect Jump */ -#define SPL _SFR_MEM8(0x003D) /* Stack Pointer Low */ -#define SPH _SFR_MEM8(0x003E) /* Stack Pointer High */ -#define SREG _SFR_MEM8(0x003F) /* Status Register */ - -/* C Language Only */ -#if !defined (__ASSEMBLER__) - -#include - -typedef volatile uint8_t register8_t; -typedef volatile uint16_t register16_t; -typedef volatile uint32_t register32_t; - - -#ifdef _WORDREGISTER -#undef _WORDREGISTER -#endif -#define _WORDREGISTER(regname) \ - __extension__ union \ - { \ - register16_t regname; \ - struct \ - { \ - register8_t regname ## L; \ - register8_t regname ## H; \ - }; \ - } - -#ifdef _DWORDREGISTER -#undef _DWORDREGISTER -#endif -#define _DWORDREGISTER(regname) \ - __extension__ union \ - { \ - register32_t regname; \ - struct \ - { \ - register8_t regname ## 0; \ - register8_t regname ## 1; \ - register8_t regname ## 2; \ - register8_t regname ## 3; \ - }; \ - } - - -/* -========================================================================== -IO Module Structures -========================================================================== -*/ - - -/* --------------------------------------------------------------------------- -VPORT - Virtual Ports --------------------------------------------------------------------------- -*/ - -/* Virtual Port */ -typedef struct VPORT_struct -{ - register8_t DIR; /* I/O Port Data Direction */ - register8_t OUT; /* I/O Port Output */ - register8_t IN; /* I/O Port Input */ - register8_t INTFLAGS; /* Interrupt Flag Register */ -} VPORT_t; - - -/* --------------------------------------------------------------------------- -XOCD - On-Chip Debug System --------------------------------------------------------------------------- -*/ - -/* On-Chip Debug System */ -typedef struct OCD_struct -{ - register8_t OCDR0; /* OCD Register 0 */ - register8_t OCDR1; /* OCD Register 1 */ -} OCD_t; - - -/* --------------------------------------------------------------------------- -CPU - CPU --------------------------------------------------------------------------- -*/ - -/* CCP signatures */ -typedef enum CCP_enum -{ - CCP_SPM_gc = (0x9D<<0), /* SPM Instruction Protection */ - CCP_IOREG_gc = (0xD8<<0), /* IO Register Protection */ -} CCP_t; - - -/* --------------------------------------------------------------------------- -CLK - Clock System --------------------------------------------------------------------------- -*/ - -/* Clock System */ -typedef struct CLK_struct -{ - register8_t CTRL; /* Control Register */ - register8_t PSCTRL; /* Prescaler Control Register */ - register8_t LOCK; /* Lock register */ - register8_t RTCCTRL; /* RTC Control Register */ - register8_t USBCTRL; /* USB Control Register */ -} CLK_t; - - -/* Power Reduction */ -typedef struct PR_struct -{ - register8_t PRGEN; /* General Power Reduction */ - register8_t PRPA; /* Power Reduction Port A */ - register8_t PRPB; /* Power Reduction Port B */ - register8_t PRPC; /* Power Reduction Port C */ - register8_t PRPD; /* Power Reduction Port D */ - register8_t PRPE; /* Power Reduction Port E */ - register8_t PRPF; /* Power Reduction Port F */ -} PR_t; - -/* System Clock Selection */ -typedef enum CLK_SCLKSEL_enum -{ - CLK_SCLKSEL_RC2M_gc = (0x00<<0), /* Internal 2 MHz RC Oscillator */ - CLK_SCLKSEL_RC32M_gc = (0x01<<0), /* Internal 32 MHz RC Oscillator */ - CLK_SCLKSEL_RC32K_gc = (0x02<<0), /* Internal 32.768 kHz RC Oscillator */ - CLK_SCLKSEL_XOSC_gc = (0x03<<0), /* External Crystal Oscillator or Clock */ - CLK_SCLKSEL_PLL_gc = (0x04<<0), /* Phase Locked Loop */ -} CLK_SCLKSEL_t; - -/* Prescaler A Division Factor */ -typedef enum CLK_PSADIV_enum -{ - CLK_PSADIV_1_gc = (0x00<<2), /* Divide by 1 */ - CLK_PSADIV_2_gc = (0x01<<2), /* Divide by 2 */ - CLK_PSADIV_4_gc = (0x03<<2), /* Divide by 4 */ - CLK_PSADIV_8_gc = (0x05<<2), /* Divide by 8 */ - CLK_PSADIV_16_gc = (0x07<<2), /* Divide by 16 */ - CLK_PSADIV_32_gc = (0x09<<2), /* Divide by 32 */ - CLK_PSADIV_64_gc = (0x0B<<2), /* Divide by 64 */ - CLK_PSADIV_128_gc = (0x0D<<2), /* Divide by 128 */ - CLK_PSADIV_256_gc = (0x0F<<2), /* Divide by 256 */ - CLK_PSADIV_512_gc = (0x11<<2), /* Divide by 512 */ -} CLK_PSADIV_t; - -/* Prescaler B and C Division Factor */ -typedef enum CLK_PSBCDIV_enum -{ - CLK_PSBCDIV_1_1_gc = (0x00<<0), /* Divide B by 1 and C by 1 */ - CLK_PSBCDIV_1_2_gc = (0x01<<0), /* Divide B by 1 and C by 2 */ - CLK_PSBCDIV_4_1_gc = (0x02<<0), /* Divide B by 4 and C by 1 */ - CLK_PSBCDIV_2_2_gc = (0x03<<0), /* Divide B by 2 and C by 2 */ -} CLK_PSBCDIV_t; - -/* RTC Clock Source */ -typedef enum CLK_RTCSRC_enum -{ - CLK_RTCSRC_ULP_gc = (0x00<<1), /* 1.024 kHz from internal 32kHz ULP */ - CLK_RTCSRC_TOSC_gc = (0x01<<1), /* 1.024 kHz from 32.768 kHz crystal oscillator on TOSC */ - CLK_RTCSRC_RCOSC_gc = (0x02<<1), /* 1.024 kHz from internal 32.768 kHz RC oscillator */ - CLK_RTCSRC_TOSC32_gc = (0x05<<1), /* 32.768 kHz from 32.768 kHz crystal oscillator on TOSC */ - CLK_RTCSRC_RCOSC32_gc = (0x06<<1), /* 32.768 kHz from internal 32.768 kHz RC oscillator */ - CLK_RTCSRC_EXTCLK_gc = (0x07<<1), /* External Clock from TOSC1 */ -} CLK_RTCSRC_t; - -/* USB Prescaler Division Factor */ -typedef enum CLK_USBPSDIV_enum -{ - CLK_USBPSDIV_1_gc = (0x00<<3), /* Divide by 1 */ - CLK_USBPSDIV_2_gc = (0x01<<3), /* Divide by 2 */ - CLK_USBPSDIV_4_gc = (0x02<<3), /* Divide by 4 */ - CLK_USBPSDIV_8_gc = (0x03<<3), /* Divide by 8 */ - CLK_USBPSDIV_16_gc = (0x04<<3), /* Divide by 16 */ - CLK_USBPSDIV_32_gc = (0x05<<3), /* Divide by 32 */ -} CLK_USBPSDIV_t; - -/* USB Clock Source */ -typedef enum CLK_USBSRC_enum -{ - CLK_USBSRC_PLL_gc = (0x00<<1), /* PLL */ - CLK_USBSRC_RC32M_gc = (0x01<<1), /* Internal 32 MHz RC Oscillator */ -} CLK_USBSRC_t; - - -/* --------------------------------------------------------------------------- -SLEEP - Sleep Controller --------------------------------------------------------------------------- -*/ - -/* Sleep Controller */ -typedef struct SLEEP_struct -{ - register8_t CTRL; /* Control Register */ -} SLEEP_t; - -/* Sleep Mode */ -typedef enum SLEEP_SMODE_enum -{ - SLEEP_SMODE_IDLE_gc = (0x00<<1), /* Idle mode */ - SLEEP_SMODE_PDOWN_gc = (0x02<<1), /* Power-down Mode */ - SLEEP_SMODE_PSAVE_gc = (0x03<<1), /* Power-save Mode */ - SLEEP_SMODE_STDBY_gc = (0x06<<1), /* Standby Mode */ - SLEEP_SMODE_ESTDBY_gc = (0x07<<1), /* Extended Standby Mode */ -} SLEEP_SMODE_t; - - - -#define SLEEP_MODE_IDLE (0x00<<1) -#define SLEEP_MODE_PWR_DOWN (0x02<<1) -#define SLEEP_MODE_PWR_SAVE (0x03<<1) -#define SLEEP_MODE_STANDBY (0x06<<1) -#define SLEEP_MODE_EXT_STANDBY (0x07<<1) -/* --------------------------------------------------------------------------- -OSC - Oscillator --------------------------------------------------------------------------- -*/ - -/* Oscillator */ -typedef struct OSC_struct -{ - register8_t CTRL; /* Control Register */ - register8_t STATUS; /* Status Register */ - register8_t XOSCCTRL; /* External Oscillator Control Register */ - register8_t XOSCFAIL; /* Oscillator Failure Detection Register */ - register8_t RC32KCAL; /* 32.768 kHz Internal Oscillator Calibration Register */ - register8_t PLLCTRL; /* PLL Control Register */ - register8_t DFLLCTRL; /* DFLL Control Register */ -} OSC_t; - -/* Oscillator Frequency Range */ -typedef enum OSC_FRQRANGE_enum -{ - OSC_FRQRANGE_04TO2_gc = (0x00<<6), /* 0.4 - 2 MHz */ - OSC_FRQRANGE_2TO9_gc = (0x01<<6), /* 2 - 9 MHz */ - OSC_FRQRANGE_9TO12_gc = (0x02<<6), /* 9 - 12 MHz */ - OSC_FRQRANGE_12TO16_gc = (0x03<<6), /* 12 - 16 MHz */ -} OSC_FRQRANGE_t; - -/* External Oscillator Selection and Startup Time */ -typedef enum OSC_XOSCSEL_enum -{ - OSC_XOSCSEL_EXTCLK_gc = (0x00<<0), /* External Clock - 6 CLK */ - OSC_XOSCSEL_32KHz_gc = (0x02<<0), /* 32.768 kHz TOSC - 32K CLK */ - OSC_XOSCSEL_XTAL_256CLK_gc = (0x03<<0), /* 0.4-16 MHz XTAL - 256 CLK */ - OSC_XOSCSEL_XTAL_1KCLK_gc = (0x07<<0), /* 0.4-16 MHz XTAL - 1K CLK */ - OSC_XOSCSEL_XTAL_16KCLK_gc = (0x0B<<0), /* 0.4-16 MHz XTAL - 16K CLK */ -} OSC_XOSCSEL_t; - -/* PLL Clock Source */ -typedef enum OSC_PLLSRC_enum -{ - OSC_PLLSRC_RC2M_gc = (0x00<<6), /* Internal 2 MHz RC Oscillator */ - OSC_PLLSRC_RC32M_gc = (0x02<<6), /* Internal 32 MHz RC Oscillator */ - OSC_PLLSRC_XOSC_gc = (0x03<<6), /* External Oscillator */ -} OSC_PLLSRC_t; - -/* 2 MHz DFLL Calibration Reference */ -typedef enum OSC_RC2MCREF_enum -{ - OSC_RC2MCREF_RC32K_gc = (0x00<<0), /* Internal 32.768 kHz RC Oscillator */ - OSC_RC2MCREF_XOSC32K_gc = (0x01<<0), /* External 32.768 kHz Crystal Oscillator */ -} OSC_RC2MCREF_t; - -/* 32 MHz DFLL Calibration Reference */ -typedef enum OSC_RC32MCREF_enum -{ - OSC_RC32MCREF_RC32K_gc = (0x00<<1), /* Internal 32.768 kHz RC Oscillator */ - OSC_RC32MCREF_XOSC32K_gc = (0x01<<1), /* External 32.768 kHz Crystal Oscillator */ - OSC_RC32MCREF_USBSOF_gc = (0x02<<1), /* USB Start of Frame */ -} OSC_RC32MCREF_t; - - -/* --------------------------------------------------------------------------- -DFLL - DFLL --------------------------------------------------------------------------- -*/ - -/* DFLL */ -typedef struct DFLL_struct -{ - register8_t CTRL; /* Control Register */ - register8_t reserved_0x01; - register8_t CALA; /* Calibration Register A */ - register8_t CALB; /* Calibration Register B */ - register8_t COMP0; /* Oscillator Compare Register 0 */ - register8_t COMP1; /* Oscillator Compare Register 1 */ - register8_t COMP2; /* Oscillator Compare Register 2 */ - register8_t reserved_0x07; -} DFLL_t; - - -/* --------------------------------------------------------------------------- -RST - Reset --------------------------------------------------------------------------- -*/ - -/* Reset */ -typedef struct RST_struct -{ - register8_t STATUS; /* Status Register */ - register8_t CTRL; /* Control Register */ -} RST_t; - - -/* --------------------------------------------------------------------------- -WDT - Watch-Dog Timer --------------------------------------------------------------------------- -*/ - -/* Watch-Dog Timer */ -typedef struct WDT_struct -{ - register8_t CTRL; /* Control */ - register8_t WINCTRL; /* Windowed Mode Control */ - register8_t STATUS; /* Status */ -} WDT_t; - -/* Period setting */ -typedef enum WDT_PER_enum -{ - WDT_PER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ - WDT_PER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ - WDT_PER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ - WDT_PER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ - WDT_PER_128CLK_gc = (0x04<<2), /* 128 cycles (0.128s @ 3.3V) */ - WDT_PER_256CLK_gc = (0x05<<2), /* 256 cycles (0.256s @ 3.3V) */ - WDT_PER_512CLK_gc = (0x06<<2), /* 512 cycles (0.512s @ 3.3V) */ - WDT_PER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ - WDT_PER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ - WDT_PER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ - WDT_PER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ -} WDT_PER_t; - -/* Closed window period */ -typedef enum WDT_WPER_enum -{ - WDT_WPER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ - WDT_WPER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ - WDT_WPER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ - WDT_WPER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ - WDT_WPER_128CLK_gc = (0x04<<2), /* 128 cycles (0.128s @ 3.3V) */ - WDT_WPER_256CLK_gc = (0x05<<2), /* 256 cycles (0.256s @ 3.3V) */ - WDT_WPER_512CLK_gc = (0x06<<2), /* 512 cycles (0.512s @ 3.3V) */ - WDT_WPER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ - WDT_WPER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ - WDT_WPER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ - WDT_WPER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ -} WDT_WPER_t; - - -/* --------------------------------------------------------------------------- -MCU - MCU Control --------------------------------------------------------------------------- -*/ - -/* MCU Control */ -typedef struct MCU_struct -{ - register8_t DEVID0; /* Device ID byte 0 */ - register8_t DEVID1; /* Device ID byte 1 */ - register8_t DEVID2; /* Device ID byte 2 */ - register8_t REVID; /* Revision ID */ - register8_t JTAGUID; /* JTAG User ID */ - register8_t reserved_0x05; - register8_t MCUCR; /* MCU Control */ - register8_t ANAINIT; /* Analog Startup Delay */ - register8_t EVSYSLOCK; /* Event System Lock */ - register8_t AWEXLOCK; /* AWEX Lock */ - register8_t reserved_0x0A; - register8_t reserved_0x0B; -} MCU_t; - - -/* --------------------------------------------------------------------------- -PMIC - Programmable Multi-level Interrupt Controller --------------------------------------------------------------------------- -*/ - -/* Programmable Multi-level Interrupt Controller */ -typedef struct PMIC_struct -{ - register8_t STATUS; /* Status Register */ - register8_t INTPRI; /* Interrupt Priority */ - register8_t CTRL; /* Control Register */ - register8_t reserved_0x03; - register8_t reserved_0x04; - register8_t reserved_0x05; - register8_t reserved_0x06; - register8_t reserved_0x07; - register8_t reserved_0x08; - register8_t reserved_0x09; - register8_t reserved_0x0A; - register8_t reserved_0x0B; - register8_t reserved_0x0C; - register8_t reserved_0x0D; - register8_t reserved_0x0E; - register8_t reserved_0x0F; -} PMIC_t; - - -/* --------------------------------------------------------------------------- -PORTCFG - Port Configuration --------------------------------------------------------------------------- -*/ - -/* I/O port Configuration */ -typedef struct PORTCFG_struct -{ - register8_t MPCMASK; /* Multi-pin Configuration Mask */ - register8_t reserved_0x01; - register8_t VPCTRLA; /* Virtual Port Control Register A */ - register8_t VPCTRLB; /* Virtual Port Control Register B */ - register8_t CLKEVOUT; /* Clock and Event Out Register */ - register8_t EBIOUT; /* EBI Output register */ - register8_t EVOUTSEL; /* Event Output Select */ -} PORTCFG_t; - -/* Virtual Port Mapping */ -typedef enum PORTCFG_VP02MAP_enum -{ - PORTCFG_VP02MAP_PORTA_gc = (0x00<<0), /* Mapped To PORTA */ - PORTCFG_VP02MAP_PORTB_gc = (0x01<<0), /* Mapped To PORTB */ - PORTCFG_VP02MAP_PORTC_gc = (0x02<<0), /* Mapped To PORTC */ - PORTCFG_VP02MAP_PORTD_gc = (0x03<<0), /* Mapped To PORTD */ - PORTCFG_VP02MAP_PORTE_gc = (0x04<<0), /* Mapped To PORTE */ - PORTCFG_VP02MAP_PORTF_gc = (0x05<<0), /* Mapped To PORTF */ - PORTCFG_VP02MAP_PORTG_gc = (0x06<<0), /* Mapped To PORTG */ - PORTCFG_VP02MAP_PORTH_gc = (0x07<<0), /* Mapped To PORTH */ - PORTCFG_VP02MAP_PORTJ_gc = (0x08<<0), /* Mapped To PORTJ */ - PORTCFG_VP02MAP_PORTK_gc = (0x09<<0), /* Mapped To PORTK */ - PORTCFG_VP02MAP_PORTL_gc = (0x0A<<0), /* Mapped To PORTL */ - PORTCFG_VP02MAP_PORTM_gc = (0x0B<<0), /* Mapped To PORTM */ - PORTCFG_VP02MAP_PORTN_gc = (0x0C<<0), /* Mapped To PORTN */ - PORTCFG_VP02MAP_PORTP_gc = (0x0D<<0), /* Mapped To PORTP */ - PORTCFG_VP02MAP_PORTQ_gc = (0x0E<<0), /* Mapped To PORTQ */ - PORTCFG_VP02MAP_PORTR_gc = (0x0F<<0), /* Mapped To PORTR */ -} PORTCFG_VP02MAP_t; - -/* Virtual Port Mapping */ -typedef enum PORTCFG_VP13MAP_enum -{ - PORTCFG_VP13MAP_PORTA_gc = (0x00<<4), /* Mapped To PORTA */ - PORTCFG_VP13MAP_PORTB_gc = (0x01<<4), /* Mapped To PORTB */ - PORTCFG_VP13MAP_PORTC_gc = (0x02<<4), /* Mapped To PORTC */ - PORTCFG_VP13MAP_PORTD_gc = (0x03<<4), /* Mapped To PORTD */ - PORTCFG_VP13MAP_PORTE_gc = (0x04<<4), /* Mapped To PORTE */ - PORTCFG_VP13MAP_PORTF_gc = (0x05<<4), /* Mapped To PORTF */ - PORTCFG_VP13MAP_PORTG_gc = (0x06<<4), /* Mapped To PORTG */ - PORTCFG_VP13MAP_PORTH_gc = (0x07<<4), /* Mapped To PORTH */ - PORTCFG_VP13MAP_PORTJ_gc = (0x08<<4), /* Mapped To PORTJ */ - PORTCFG_VP13MAP_PORTK_gc = (0x09<<4), /* Mapped To PORTK */ - PORTCFG_VP13MAP_PORTL_gc = (0x0A<<4), /* Mapped To PORTL */ - PORTCFG_VP13MAP_PORTM_gc = (0x0B<<4), /* Mapped To PORTM */ - PORTCFG_VP13MAP_PORTN_gc = (0x0C<<4), /* Mapped To PORTN */ - PORTCFG_VP13MAP_PORTP_gc = (0x0D<<4), /* Mapped To PORTP */ - PORTCFG_VP13MAP_PORTQ_gc = (0x0E<<4), /* Mapped To PORTQ */ - PORTCFG_VP13MAP_PORTR_gc = (0x0F<<4), /* Mapped To PORTR */ -} PORTCFG_VP13MAP_t; - -/* System Clock Output Port */ -typedef enum PORTCFG_CLKOUT_enum -{ - PORTCFG_CLKOUT_OFF_gc = (0x00<<0), /* System Clock Output Disabled */ - PORTCFG_CLKOUT_PC7_gc = (0x01<<0), /* System Clock Output on Port C pin 7 */ - PORTCFG_CLKOUT_PD7_gc = (0x02<<0), /* System Clock Output on Port D pin 7 */ - PORTCFG_CLKOUT_PE7_gc = (0x03<<0), /* System Clock Output on Port E pin 7 */ -} PORTCFG_CLKOUT_t; - -/* Peripheral Clock Output Select */ -typedef enum PORTCFG_CLKOUTSEL_enum -{ - PORTCFG_CLKOUTSEL_CLK1X_gc = (0x00<<2), /* 1x Peripheral Clock Output to pin */ - PORTCFG_CLKOUTSEL_CLK2X_gc = (0x01<<2), /* 2x Peripheral Clock Output to pin */ - PORTCFG_CLKOUTSEL_CLK4X_gc = (0x02<<2), /* 4x Peripheral Clock Output to pin */ -} PORTCFG_CLKOUTSEL_t; - -/* Event Output Port */ -typedef enum PORTCFG_EVOUT_enum -{ - PORTCFG_EVOUT_OFF_gc = (0x00<<4), /* Event Output Disabled */ - PORTCFG_EVOUT_PC7_gc = (0x01<<4), /* Event Channel 7 Output on Port C pin 7 */ - PORTCFG_EVOUT_PD7_gc = (0x02<<4), /* Event Channel 7 Output on Port D pin 7 */ - PORTCFG_EVOUT_PE7_gc = (0x03<<4), /* Event Channel 7 Output on Port E pin 7 */ -} PORTCFG_EVOUT_t; - -/* Clock and Event Output Port */ -typedef enum PORTCFG_CLKEVPIN_enum -{ - PORTCFG_CLKEVPIN_PIN7_gc = (0x00<<7), /* Clock and Event Ouput on PIN 7 */ - PORTCFG_CLKEVPIN_PIN4_gc = (0x01<<7), /* Clock and Event Ouput on PIN 4 */ -} PORTCFG_CLKEVPIN_t; - -/* EBI Address Output Port */ -typedef enum PORTCFG_EBIADROUT_enum -{ - PORTCFG_EBIADROUT_PF_gc = (0x00<<2), /* EBI port 3 address output on PORTF pins 0 to 7 */ - PORTCFG_EBIADROUT_PE_gc = (0x01<<2), /* EBI port 3 address output on PORTE pins 0 to 7 */ - PORTCFG_EBIADROUT_PFH_gc = (0x02<<2), /* EBI port 3 address output on PORTF pins 4 to 7 */ - PORTCFG_EBIADROUT_PEH_gc = (0x03<<2), /* EBI port 3 address output on PORTE pins 4 to 7 */ -} PORTCFG_EBIADROUT_t; - -/* EBI Chip Select Output Port */ -typedef enum PORTCFG_EBICSOUT_enum -{ - PORTCFG_EBICSOUT_PH_gc = (0x00<<0), /* EBI chip select output to PORTH pin 4 to 7 */ - PORTCFG_EBICSOUT_PL_gc = (0x01<<0), /* EBI chip select output to PORTL pin 4 to 7 */ - PORTCFG_EBICSOUT_PF_gc = (0x02<<0), /* EBI chip select output to PORTF pin 4 to 7 */ - PORTCFG_EBICSOUT_PE_gc = (0x03<<0), /* EBI chip select output to PORTE pin 4 to 7 */ -} PORTCFG_EBICSOUT_t; - -/* Event Output Select */ -typedef enum PORTCFG_EVOUTSEL_enum -{ - PORTCFG_EVOUTSEL_0_gc = (0x00<<0), /* Event Channel 0 output to pin */ - PORTCFG_EVOUTSEL_1_gc = (0x01<<0), /* Event Channel 1 output to pin */ - PORTCFG_EVOUTSEL_2_gc = (0x02<<0), /* Event Channel 2 output to pin */ - PORTCFG_EVOUTSEL_3_gc = (0x03<<0), /* Event Channel 3 output to pin */ - PORTCFG_EVOUTSEL_4_gc = (0x04<<0), /* Event Channel 4 output to pin */ - PORTCFG_EVOUTSEL_5_gc = (0x05<<0), /* Event Channel 5 output to pin */ - PORTCFG_EVOUTSEL_6_gc = (0x06<<0), /* Event Channel 6 output to pin */ - PORTCFG_EVOUTSEL_7_gc = (0x07<<0), /* Event Channel 7 output to pin */ -} PORTCFG_EVOUTSEL_t; - - -/* --------------------------------------------------------------------------- -AES - AES Module --------------------------------------------------------------------------- -*/ - -/* AES Module */ -typedef struct AES_struct -{ - register8_t CTRL; /* AES Control Register */ - register8_t STATUS; /* AES Status Register */ - register8_t STATE; /* AES State Register */ - register8_t KEY; /* AES Key Register */ - register8_t INTCTRL; /* AES Interrupt Control Register */ -} AES_t; - -/* Interrupt level */ -typedef enum AES_INTLVL_enum -{ - AES_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - AES_INTLVL_LO_gc = (0x01<<0), /* Low Level */ - AES_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ - AES_INTLVL_HI_gc = (0x03<<0), /* High Level */ -} AES_INTLVL_t; - - -/* --------------------------------------------------------------------------- -CRC - Cyclic Redundancy Checker --------------------------------------------------------------------------- -*/ - -/* Cyclic Redundancy Checker */ -typedef struct CRC_struct -{ - register8_t CTRL; /* Control Register */ - register8_t STATUS; /* Status Register */ - register8_t reserved_0x02; - register8_t DATAIN; /* Data Input */ - register8_t CHECKSUM0; /* Checksum byte 0 */ - register8_t CHECKSUM1; /* Checksum byte 1 */ - register8_t CHECKSUM2; /* Checksum byte 2 */ - register8_t CHECKSUM3; /* Checksum byte 3 */ -} CRC_t; - -/* Reset */ -typedef enum CRC_RESET_enum -{ - CRC_RESET_NO_gc = (0x00<<6), /* No Reset */ - CRC_RESET_RESET0_gc = (0x02<<6), /* Reset CRC with CHECKSUM to all zeros */ - CRC_RESET_RESET1_gc = (0x03<<6), /* Reset CRC with CHECKSUM to all ones */ -} CRC_RESET_t; - -/* Input Source */ -typedef enum CRC_SOURCE_enum -{ - CRC_SOURCE_DISABLE_gc = (0x00<<0), /* Disabled */ - CRC_SOURCE_IO_gc = (0x01<<0), /* I/O Interface */ - CRC_SOURCE_FLASH_gc = (0x02<<0), /* Flash */ - CRC_SOURCE_DMAC0_gc = (0x04<<0), /* DMAC Channel 0 */ - CRC_SOURCE_DMAC1_gc = (0x05<<0), /* DMAC Channel 1 */ - CRC_SOURCE_DMAC2_gc = (0x06<<0), /* DMAC Channel 2 */ - CRC_SOURCE_DMAC3_gc = (0x07<<0), /* DMAC Channel 3 */ -} CRC_SOURCE_t; - - -/* --------------------------------------------------------------------------- -DMA - DMA Controller --------------------------------------------------------------------------- -*/ - -/* DMA Channel */ -typedef struct DMA_CH_struct -{ - register8_t CTRLA; /* Channel Control */ - register8_t CTRLB; /* Channel Control */ - register8_t ADDRCTRL; /* Address Control */ - register8_t TRIGSRC; /* Channel Trigger Source */ - _WORDREGISTER(TRFCNT); /* Channel Block Transfer Count */ - register8_t REPCNT; /* Channel Repeat Count */ - register8_t reserved_0x07; - register8_t SRCADDR0; /* Channel Source Address 0 */ - register8_t SRCADDR1; /* Channel Source Address 1 */ - register8_t SRCADDR2; /* Channel Source Address 2 */ - register8_t reserved_0x0B; - register8_t DESTADDR0; /* Channel Destination Address 0 */ - register8_t DESTADDR1; /* Channel Destination Address 1 */ - register8_t DESTADDR2; /* Channel Destination Address 2 */ - register8_t reserved_0x0F; -} DMA_CH_t; - - -/* DMA Controller */ -typedef struct DMA_struct -{ - register8_t CTRL; /* Control */ - register8_t reserved_0x01; - register8_t reserved_0x02; - register8_t INTFLAGS; /* Transfer Interrupt Status */ - register8_t STATUS; /* Status */ - register8_t reserved_0x05; - _WORDREGISTER(TEMP); /* Temporary Register For 16/24-bit Access */ - register8_t reserved_0x08; - register8_t reserved_0x09; - register8_t reserved_0x0A; - register8_t reserved_0x0B; - register8_t reserved_0x0C; - register8_t reserved_0x0D; - register8_t reserved_0x0E; - register8_t reserved_0x0F; - DMA_CH_t CH0; /* DMA Channel 0 */ - DMA_CH_t CH1; /* DMA Channel 1 */ - DMA_CH_t CH2; /* DMA Channel 2 */ - DMA_CH_t CH3; /* DMA Channel 3 */ -} DMA_t; - -/* Burst mode */ -typedef enum DMA_CH_BURSTLEN_enum -{ - DMA_CH_BURSTLEN_1BYTE_gc = (0x00<<0), /* 1-byte burst mode */ - DMA_CH_BURSTLEN_2BYTE_gc = (0x01<<0), /* 2-byte burst mode */ - DMA_CH_BURSTLEN_4BYTE_gc = (0x02<<0), /* 4-byte burst mode */ - DMA_CH_BURSTLEN_8BYTE_gc = (0x03<<0), /* 8-byte burst mode */ -} DMA_CH_BURSTLEN_t; - -/* Source address reload mode */ -typedef enum DMA_CH_SRCRELOAD_enum -{ - DMA_CH_SRCRELOAD_NONE_gc = (0x00<<6), /* No reload */ - DMA_CH_SRCRELOAD_BLOCK_gc = (0x01<<6), /* Reload at end of block */ - DMA_CH_SRCRELOAD_BURST_gc = (0x02<<6), /* Reload at end of burst */ - DMA_CH_SRCRELOAD_TRANSACTION_gc = (0x03<<6), /* Reload at end of transaction */ -} DMA_CH_SRCRELOAD_t; - -/* Source addressing mode */ -typedef enum DMA_CH_SRCDIR_enum -{ - DMA_CH_SRCDIR_FIXED_gc = (0x00<<4), /* Fixed */ - DMA_CH_SRCDIR_INC_gc = (0x01<<4), /* Increment */ - DMA_CH_SRCDIR_DEC_gc = (0x02<<4), /* Decrement */ -} DMA_CH_SRCDIR_t; - -/* Destination adress reload mode */ -typedef enum DMA_CH_DESTRELOAD_enum -{ - DMA_CH_DESTRELOAD_NONE_gc = (0x00<<2), /* No reload */ - DMA_CH_DESTRELOAD_BLOCK_gc = (0x01<<2), /* Reload at end of block */ - DMA_CH_DESTRELOAD_BURST_gc = (0x02<<2), /* Reload at end of burst */ - DMA_CH_DESTRELOAD_TRANSACTION_gc = (0x03<<2), /* Reload at end of transaction */ -} DMA_CH_DESTRELOAD_t; - -/* Destination adressing mode */ -typedef enum DMA_CH_DESTDIR_enum -{ - DMA_CH_DESTDIR_FIXED_gc = (0x00<<0), /* Fixed */ - DMA_CH_DESTDIR_INC_gc = (0x01<<0), /* Increment */ - DMA_CH_DESTDIR_DEC_gc = (0x02<<0), /* Decrement */ -} DMA_CH_DESTDIR_t; - -/* Transfer trigger source */ -typedef enum DMA_CH_TRIGSRC_enum -{ - DMA_CH_TRIGSRC_OFF_gc = (0x00<<0), /* Off software triggers only */ - DMA_CH_TRIGSRC_EVSYS_CH0_gc = (0x01<<0), /* Event System Channel 0 */ - DMA_CH_TRIGSRC_EVSYS_CH1_gc = (0x02<<0), /* Event System Channel 1 */ - DMA_CH_TRIGSRC_EVSYS_CH2_gc = (0x03<<0), /* Event System Channel 2 */ - DMA_CH_TRIGSRC_ADCA_CH0_gc = (0x10<<0), /* ADCA Channel 0 */ - DMA_CH_TRIGSRC_ADCA_CH1_gc = (0x11<<0), /* ADCA Channel 1 */ - DMA_CH_TRIGSRC_ADCA_CH2_gc = (0x12<<0), /* ADCA Channel 2 */ - DMA_CH_TRIGSRC_ADCA_CH3_gc = (0x13<<0), /* ADCA Channel 3 */ - DMA_CH_TRIGSRC_ADCA_CH4_gc = (0x14<<0), /* ADCA Channel 0,1,2,3 combined */ - DMA_CH_TRIGSRC_DACA_CH0_gc = (0x15<<0), /* DACA Channel 0 */ - DMA_CH_TRIGSRC_DACA_CH1_gc = (0x16<<0), /* DACA Channel 1 */ - DMA_CH_TRIGSRC_ADCB_CH0_gc = (0x20<<0), /* ADCB Channel 0 */ - DMA_CH_TRIGSRC_ADCB_CH1_gc = (0x21<<0), /* ADCB Channel 1 */ - DMA_CH_TRIGSRC_ADCB_CH2_gc = (0x22<<0), /* ADCB Channel 2 */ - DMA_CH_TRIGSRC_ADCB_CH3_gc = (0x23<<0), /* ADCB Channel 3 */ - DMA_CH_TRIGSRC_ADCB_CH4_gc = (0x24<<0), /* ADCB Channel 0,1,2,3 combined */ - DMA_CH_TRIGSRC_DACB_CH0_gc = (0x25<<0), /* DACB Channel 0 */ - DMA_CH_TRIGSRC_DACB_CH1_gc = (0x26<<0), /* DACB Channel 1 */ - DMA_CH_TRIGSRC_TCC0_OVF_gc = (0x40<<0), /* Timer/Counter C0 Overflow */ - DMA_CH_TRIGSRC_TCC0_ERR_gc = (0x41<<0), /* Timer/Counter C0 Error */ - DMA_CH_TRIGSRC_TCC0_CCA_gc = (0x42<<0), /* Timer/Counter C0 Compare or Capture A */ - DMA_CH_TRIGSRC_TCC0_CCB_gc = (0x43<<0), /* Timer/Counter C0 Compare or Capture B */ - DMA_CH_TRIGSRC_TCC0_CCC_gc = (0x44<<0), /* Timer/Counter C0 Compare or Capture C */ - DMA_CH_TRIGSRC_TCC0_CCD_gc = (0x45<<0), /* Timer/Counter C0 Compare or Capture D */ - DMA_CH_TRIGSRC_TCC1_OVF_gc = (0x46<<0), /* Timer/Counter C1 Overflow */ - DMA_CH_TRIGSRC_TCC1_ERR_gc = (0x47<<0), /* Timer/Counter C1 Error */ - DMA_CH_TRIGSRC_TCC1_CCA_gc = (0x48<<0), /* Timer/Counter C1 Compare or Capture A */ - DMA_CH_TRIGSRC_TCC1_CCB_gc = (0x49<<0), /* Timer/Counter C1 Compare or Capture B */ - DMA_CH_TRIGSRC_SPIC_gc = (0x4A<<0), /* SPI C Transfer Complete */ - DMA_CH_TRIGSRC_USARTC0_RXC_gc = (0x4B<<0), /* USART C0 Receive Complete */ - DMA_CH_TRIGSRC_USARTC0_DRE_gc = (0x4C<<0), /* USART C0 Data Register Empty */ - DMA_CH_TRIGSRC_USARTC1_RXC_gc = (0x4E<<0), /* USART C1 Receive Complete */ - DMA_CH_TRIGSRC_USARTC1_DRE_gc = (0x4F<<0), /* USART C1 Data Register Empty */ - DMA_CH_TRIGSRC_TCD0_OVF_gc = (0x60<<0), /* Timer/Counter D0 Overflow */ - DMA_CH_TRIGSRC_TCD0_ERR_gc = (0x61<<0), /* Timer/Counter D0 Error */ - DMA_CH_TRIGSRC_TCD0_CCA_gc = (0x62<<0), /* Timer/Counter D0 Compare or Capture A */ - DMA_CH_TRIGSRC_TCD0_CCB_gc = (0x63<<0), /* Timer/Counter D0 Compare or Capture B */ - DMA_CH_TRIGSRC_TCD0_CCC_gc = (0x64<<0), /* Timer/Counter D0 Compare or Capture C */ - DMA_CH_TRIGSRC_TCD0_CCD_gc = (0x65<<0), /* Timer/Counter D0 Compare or Capture D */ - DMA_CH_TRIGSRC_TCD1_OVF_gc = (0x66<<0), /* Timer/Counter D1 Overflow */ - DMA_CH_TRIGSRC_TCD1_ERR_gc = (0x67<<0), /* Timer/Counter D1 Error */ - DMA_CH_TRIGSRC_TCD1_CCA_gc = (0x68<<0), /* Timer/Counter D1 Compare or Capture A */ - DMA_CH_TRIGSRC_TCD1_CCB_gc = (0x69<<0), /* Timer/Counter D1 Compare or Capture B */ - DMA_CH_TRIGSRC_SPID_gc = (0x6A<<0), /* SPI D Transfer Complete */ - DMA_CH_TRIGSRC_USARTD0_RXC_gc = (0x6B<<0), /* USART D0 Receive Complete */ - DMA_CH_TRIGSRC_USARTD0_DRE_gc = (0x6C<<0), /* USART D0 Data Register Empty */ - DMA_CH_TRIGSRC_USARTD1_RXC_gc = (0x6E<<0), /* USART D1 Receive Complete */ - DMA_CH_TRIGSRC_USARTD1_DRE_gc = (0x6F<<0), /* USART D1 Data Register Empty */ - DMA_CH_TRIGSRC_TCE0_OVF_gc = (0x80<<0), /* Timer/Counter E0 Overflow */ - DMA_CH_TRIGSRC_TCE0_ERR_gc = (0x81<<0), /* Timer/Counter E0 Error */ - DMA_CH_TRIGSRC_TCE0_CCA_gc = (0x82<<0), /* Timer/Counter E0 Compare or Capture A */ - DMA_CH_TRIGSRC_TCE0_CCB_gc = (0x83<<0), /* Timer/Counter E0 Compare or Capture B */ - DMA_CH_TRIGSRC_TCE0_CCC_gc = (0x84<<0), /* Timer/Counter E0 Compare or Capture C */ - DMA_CH_TRIGSRC_TCE0_CCD_gc = (0x85<<0), /* Timer/Counter E0 Compare or Capture D */ - DMA_CH_TRIGSRC_TCE1_OVF_gc = (0x86<<0), /* Timer/Counter E1 Overflow */ - DMA_CH_TRIGSRC_TCE1_ERR_gc = (0x87<<0), /* Timer/Counter E1 Error */ - DMA_CH_TRIGSRC_TCE1_CCA_gc = (0x88<<0), /* Timer/Counter E1 Compare or Capture A */ - DMA_CH_TRIGSRC_TCE1_CCB_gc = (0x89<<0), /* Timer/Counter E1 Compare or Capture B */ - DMA_CH_TRIGSRC_SPIE_gc = (0x8A<<0), /* SPI E Transfer Complete */ - DMA_CH_TRIGSRC_USARTE0_RXC_gc = (0x8B<<0), /* USART E0 Receive Complete */ - DMA_CH_TRIGSRC_USARTE0_DRE_gc = (0x8C<<0), /* USART E0 Data Register Empty */ - DMA_CH_TRIGSRC_USARTE1_RXC_gc = (0x8E<<0), /* USART E1 Receive Complete */ - DMA_CH_TRIGSRC_USARTE1_DRE_gc = (0x8F<<0), /* USART E1 Data Register Empty */ - DMA_CH_TRIGSRC_TCF0_OVF_gc = (0xA0<<0), /* Timer/Counter F0 Overflow */ - DMA_CH_TRIGSRC_TCF0_ERR_gc = (0xA1<<0), /* Timer/Counter F0 Error */ - DMA_CH_TRIGSRC_TCF0_CCA_gc = (0xA2<<0), /* Timer/Counter F0 Compare or Capture A */ - DMA_CH_TRIGSRC_TCF0_CCB_gc = (0xA3<<0), /* Timer/Counter F0 Compare or Capture B */ - DMA_CH_TRIGSRC_TCF0_CCC_gc = (0xA4<<0), /* Timer/Counter F0 Compare or Capture C */ - DMA_CH_TRIGSRC_TCF0_CCD_gc = (0xA5<<0), /* Timer/Counter F0 Compare or Capture D */ - DMA_CH_TRIGSRC_TCF1_OVF_gc = (0xA6<<0), /* Timer/Counter F1 Overflow */ - DMA_CH_TRIGSRC_TCF1_ERR_gc = (0xA7<<0), /* Timer/Counter F1 Error */ - DMA_CH_TRIGSRC_TCF1_CCA_gc = (0xA8<<0), /* Timer/Counter F1 Compare or Capture A */ - DMA_CH_TRIGSRC_TCF1_CCB_gc = (0xA9<<0), /* Timer/Counter F1 Compare or Capture B */ - DMA_CH_TRIGSRC_SPIF_gc = (0xAA<<0), /* SPI F Transfer Complete */ - DMA_CH_TRIGSRC_USARTF0_RXC_gc = (0xAB<<0), /* USART F0 Receive Complete */ - DMA_CH_TRIGSRC_USARTF0_DRE_gc = (0xAC<<0), /* USART F0 Data Register Empty */ - DMA_CH_TRIGSRC_USARTF1_RXC_gc = (0xAE<<0), /* USART F1 Receive Complete */ - DMA_CH_TRIGSRC_USARTF1_DRE_gc = (0xAF<<0), /* USART F1 Data Register Empty */ -} DMA_CH_TRIGSRC_t; - -/* Double buffering mode */ -typedef enum DMA_DBUFMODE_enum -{ - DMA_DBUFMODE_DISABLED_gc = (0x00<<2), /* Double buffering disabled */ - DMA_DBUFMODE_CH01_gc = (0x01<<2), /* Double buffering enabled on channel 0/1 */ - DMA_DBUFMODE_CH23_gc = (0x02<<2), /* Double buffering enabled on channel 2/3 */ - DMA_DBUFMODE_CH01CH23_gc = (0x03<<2), /* Double buffering enabled on ch. 0/1 and ch. 2/3 */ -} DMA_DBUFMODE_t; - -/* Priority mode */ -typedef enum DMA_PRIMODE_enum -{ - DMA_PRIMODE_RR0123_gc = (0x00<<0), /* Round Robin */ - DMA_PRIMODE_CH0RR123_gc = (0x01<<0), /* Channel 0 > Round Robin on channel 1/2/3 */ - DMA_PRIMODE_CH01RR23_gc = (0x02<<0), /* Channel 0 > channel 1 > Round Robin on channel 2/3 */ - DMA_PRIMODE_CH0123_gc = (0x03<<0), /* Channel 0 > channel 1 > channel 2 > channel 3 */ -} DMA_PRIMODE_t; - -/* Interrupt level */ -typedef enum DMA_CH_ERRINTLVL_enum -{ - DMA_CH_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ - DMA_CH_ERRINTLVL_LO_gc = (0x01<<2), /* Low level */ - DMA_CH_ERRINTLVL_MED_gc = (0x02<<2), /* Medium level */ - DMA_CH_ERRINTLVL_HI_gc = (0x03<<2), /* High level */ -} DMA_CH_ERRINTLVL_t; - -/* Interrupt level */ -typedef enum DMA_CH_TRNINTLVL_enum -{ - DMA_CH_TRNINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ - DMA_CH_TRNINTLVL_LO_gc = (0x01<<0), /* Low level */ - DMA_CH_TRNINTLVL_MED_gc = (0x02<<0), /* Medium level */ - DMA_CH_TRNINTLVL_HI_gc = (0x03<<0), /* High level */ -} DMA_CH_TRNINTLVL_t; - - -/* --------------------------------------------------------------------------- -EVSYS - Event System --------------------------------------------------------------------------- -*/ - -/* Event System */ -typedef struct EVSYS_struct -{ - register8_t CH0MUX; /* Event Channel 0 Multiplexer */ - register8_t CH1MUX; /* Event Channel 1 Multiplexer */ - register8_t CH2MUX; /* Event Channel 2 Multiplexer */ - register8_t CH3MUX; /* Event Channel 3 Multiplexer */ - register8_t CH4MUX; /* Event Channel 4 Multiplexer */ - register8_t CH5MUX; /* Event Channel 5 Multiplexer */ - register8_t CH6MUX; /* Event Channel 6 Multiplexer */ - register8_t CH7MUX; /* Event Channel 7 Multiplexer */ - register8_t CH0CTRL; /* Channel 0 Control Register */ - register8_t CH1CTRL; /* Channel 1 Control Register */ - register8_t CH2CTRL; /* Channel 2 Control Register */ - register8_t CH3CTRL; /* Channel 3 Control Register */ - register8_t CH4CTRL; /* Channel 4 Control Register */ - register8_t CH5CTRL; /* Channel 5 Control Register */ - register8_t CH6CTRL; /* Channel 6 Control Register */ - register8_t CH7CTRL; /* Channel 7 Control Register */ - register8_t STROBE; /* Event Strobe */ - register8_t DATA; /* Event Data */ -} EVSYS_t; - -/* Quadrature Decoder Index Recognition Mode */ -typedef enum EVSYS_QDIRM_enum -{ - EVSYS_QDIRM_00_gc = (0x00<<5), /* QDPH0 = 0, QDPH90 = 0 */ - EVSYS_QDIRM_01_gc = (0x01<<5), /* QDPH0 = 0, QDPH90 = 1 */ - EVSYS_QDIRM_10_gc = (0x02<<5), /* QDPH0 = 1, QDPH90 = 0 */ - EVSYS_QDIRM_11_gc = (0x03<<5), /* QDPH0 = 1, QDPH90 = 1 */ -} EVSYS_QDIRM_t; - -/* Digital filter coefficient */ -typedef enum EVSYS_DIGFILT_enum -{ - EVSYS_DIGFILT_1SAMPLE_gc = (0x00<<0), /* 1 SAMPLE */ - EVSYS_DIGFILT_2SAMPLES_gc = (0x01<<0), /* 2 SAMPLES */ - EVSYS_DIGFILT_3SAMPLES_gc = (0x02<<0), /* 3 SAMPLES */ - EVSYS_DIGFILT_4SAMPLES_gc = (0x03<<0), /* 4 SAMPLES */ - EVSYS_DIGFILT_5SAMPLES_gc = (0x04<<0), /* 5 SAMPLES */ - EVSYS_DIGFILT_6SAMPLES_gc = (0x05<<0), /* 6 SAMPLES */ - EVSYS_DIGFILT_7SAMPLES_gc = (0x06<<0), /* 7 SAMPLES */ - EVSYS_DIGFILT_8SAMPLES_gc = (0x07<<0), /* 8 SAMPLES */ -} EVSYS_DIGFILT_t; - -/* Event Channel multiplexer input selection */ -typedef enum EVSYS_CHMUX_enum -{ - EVSYS_CHMUX_OFF_gc = (0x00<<0), /* Off */ - EVSYS_CHMUX_RTC_OVF_gc = (0x08<<0), /* RTC Overflow */ - EVSYS_CHMUX_RTC_CMP_gc = (0x09<<0), /* RTC Compare Match */ - EVSYS_CHMUX_USB_gc = (0x0A<<0), /* USB Setup, SOF, CRC error and UNF/OVF */ - EVSYS_CHMUX_ACA_CH0_gc = (0x10<<0), /* Analog Comparator A Channel 0 */ - EVSYS_CHMUX_ACA_CH1_gc = (0x11<<0), /* Analog Comparator A Channel 1 */ - EVSYS_CHMUX_ACA_WIN_gc = (0x12<<0), /* Analog Comparator A Window */ - EVSYS_CHMUX_ACB_CH0_gc = (0x13<<0), /* Analog Comparator B Channel 0 */ - EVSYS_CHMUX_ACB_CH1_gc = (0x14<<0), /* Analog Comparator B Channel 1 */ - EVSYS_CHMUX_ACB_WIN_gc = (0x15<<0), /* Analog Comparator B Window */ - EVSYS_CHMUX_ADCA_CH0_gc = (0x20<<0), /* ADC A Channel 0 */ - EVSYS_CHMUX_ADCA_CH1_gc = (0x21<<0), /* ADC A Channel 1 */ - EVSYS_CHMUX_ADCA_CH2_gc = (0x22<<0), /* ADC A Channel 2 */ - EVSYS_CHMUX_ADCA_CH3_gc = (0x23<<0), /* ADC A Channel 3 */ - EVSYS_CHMUX_ADCB_CH0_gc = (0x24<<0), /* ADC B Channel 0 */ - EVSYS_CHMUX_ADCB_CH1_gc = (0x25<<0), /* ADC B Channel 1 */ - EVSYS_CHMUX_ADCB_CH2_gc = (0x26<<0), /* ADC B Channel 2 */ - EVSYS_CHMUX_ADCB_CH3_gc = (0x27<<0), /* ADC B Channel 3 */ - EVSYS_CHMUX_PORTA_PIN0_gc = (0x50<<0), /* Port A, Pin0 */ - EVSYS_CHMUX_PORTA_PIN1_gc = (0x51<<0), /* Port A, Pin1 */ - EVSYS_CHMUX_PORTA_PIN2_gc = (0x52<<0), /* Port A, Pin2 */ - EVSYS_CHMUX_PORTA_PIN3_gc = (0x53<<0), /* Port A, Pin3 */ - EVSYS_CHMUX_PORTA_PIN4_gc = (0x54<<0), /* Port A, Pin4 */ - EVSYS_CHMUX_PORTA_PIN5_gc = (0x55<<0), /* Port A, Pin5 */ - EVSYS_CHMUX_PORTA_PIN6_gc = (0x56<<0), /* Port A, Pin6 */ - EVSYS_CHMUX_PORTA_PIN7_gc = (0x57<<0), /* Port A, Pin7 */ - EVSYS_CHMUX_PORTB_PIN0_gc = (0x58<<0), /* Port B, Pin0 */ - EVSYS_CHMUX_PORTB_PIN1_gc = (0x59<<0), /* Port B, Pin1 */ - EVSYS_CHMUX_PORTB_PIN2_gc = (0x5A<<0), /* Port B, Pin2 */ - EVSYS_CHMUX_PORTB_PIN3_gc = (0x5B<<0), /* Port B, Pin3 */ - EVSYS_CHMUX_PORTB_PIN4_gc = (0x5C<<0), /* Port B, Pin4 */ - EVSYS_CHMUX_PORTB_PIN5_gc = (0x5D<<0), /* Port B, Pin5 */ - EVSYS_CHMUX_PORTB_PIN6_gc = (0x5E<<0), /* Port B, Pin6 */ - EVSYS_CHMUX_PORTB_PIN7_gc = (0x5F<<0), /* Port B, Pin7 */ - EVSYS_CHMUX_PORTC_PIN0_gc = (0x60<<0), /* Port C, Pin0 */ - EVSYS_CHMUX_PORTC_PIN1_gc = (0x61<<0), /* Port C, Pin1 */ - EVSYS_CHMUX_PORTC_PIN2_gc = (0x62<<0), /* Port C, Pin2 */ - EVSYS_CHMUX_PORTC_PIN3_gc = (0x63<<0), /* Port C, Pin3 */ - EVSYS_CHMUX_PORTC_PIN4_gc = (0x64<<0), /* Port C, Pin4 */ - EVSYS_CHMUX_PORTC_PIN5_gc = (0x65<<0), /* Port C, Pin5 */ - EVSYS_CHMUX_PORTC_PIN6_gc = (0x66<<0), /* Port C, Pin6 */ - EVSYS_CHMUX_PORTC_PIN7_gc = (0x67<<0), /* Port C, Pin7 */ - EVSYS_CHMUX_PORTD_PIN0_gc = (0x68<<0), /* Port D, Pin0 */ - EVSYS_CHMUX_PORTD_PIN1_gc = (0x69<<0), /* Port D, Pin1 */ - EVSYS_CHMUX_PORTD_PIN2_gc = (0x6A<<0), /* Port D, Pin2 */ - EVSYS_CHMUX_PORTD_PIN3_gc = (0x6B<<0), /* Port D, Pin3 */ - EVSYS_CHMUX_PORTD_PIN4_gc = (0x6C<<0), /* Port D, Pin4 */ - EVSYS_CHMUX_PORTD_PIN5_gc = (0x6D<<0), /* Port D, Pin5 */ - EVSYS_CHMUX_PORTD_PIN6_gc = (0x6E<<0), /* Port D, Pin6 */ - EVSYS_CHMUX_PORTD_PIN7_gc = (0x6F<<0), /* Port D, Pin7 */ - EVSYS_CHMUX_PORTE_PIN0_gc = (0x70<<0), /* Port E, Pin0 */ - EVSYS_CHMUX_PORTE_PIN1_gc = (0x71<<0), /* Port E, Pin1 */ - EVSYS_CHMUX_PORTE_PIN2_gc = (0x72<<0), /* Port E, Pin2 */ - EVSYS_CHMUX_PORTE_PIN3_gc = (0x73<<0), /* Port E, Pin3 */ - EVSYS_CHMUX_PORTE_PIN4_gc = (0x74<<0), /* Port E, Pin4 */ - EVSYS_CHMUX_PORTE_PIN5_gc = (0x75<<0), /* Port E, Pin5 */ - EVSYS_CHMUX_PORTE_PIN6_gc = (0x76<<0), /* Port E, Pin6 */ - EVSYS_CHMUX_PORTE_PIN7_gc = (0x77<<0), /* Port E, Pin7 */ - EVSYS_CHMUX_PORTF_PIN0_gc = (0x78<<0), /* Port F, Pin0 */ - EVSYS_CHMUX_PORTF_PIN1_gc = (0x79<<0), /* Port F, Pin1 */ - EVSYS_CHMUX_PORTF_PIN2_gc = (0x7A<<0), /* Port F, Pin2 */ - EVSYS_CHMUX_PORTF_PIN3_gc = (0x7B<<0), /* Port F, Pin3 */ - EVSYS_CHMUX_PORTF_PIN4_gc = (0x7C<<0), /* Port F, Pin4 */ - EVSYS_CHMUX_PORTF_PIN5_gc = (0x7D<<0), /* Port F, Pin5 */ - EVSYS_CHMUX_PORTF_PIN6_gc = (0x7E<<0), /* Port F, Pin6 */ - EVSYS_CHMUX_PORTF_PIN7_gc = (0x7F<<0), /* Port F, Pin7 */ - EVSYS_CHMUX_PRESCALER_1_gc = (0x80<<0), /* Prescaler, divide by 1 */ - EVSYS_CHMUX_PRESCALER_2_gc = (0x81<<0), /* Prescaler, divide by 2 */ - EVSYS_CHMUX_PRESCALER_4_gc = (0x82<<0), /* Prescaler, divide by 4 */ - EVSYS_CHMUX_PRESCALER_8_gc = (0x83<<0), /* Prescaler, divide by 8 */ - EVSYS_CHMUX_PRESCALER_16_gc = (0x84<<0), /* Prescaler, divide by 16 */ - EVSYS_CHMUX_PRESCALER_32_gc = (0x85<<0), /* Prescaler, divide by 32 */ - EVSYS_CHMUX_PRESCALER_64_gc = (0x86<<0), /* Prescaler, divide by 64 */ - EVSYS_CHMUX_PRESCALER_128_gc = (0x87<<0), /* Prescaler, divide by 128 */ - EVSYS_CHMUX_PRESCALER_256_gc = (0x88<<0), /* Prescaler, divide by 256 */ - EVSYS_CHMUX_PRESCALER_512_gc = (0x89<<0), /* Prescaler, divide by 512 */ - EVSYS_CHMUX_PRESCALER_1024_gc = (0x8A<<0), /* Prescaler, divide by 1024 */ - EVSYS_CHMUX_PRESCALER_2048_gc = (0x8B<<0), /* Prescaler, divide by 2048 */ - EVSYS_CHMUX_PRESCALER_4096_gc = (0x8C<<0), /* Prescaler, divide by 4096 */ - EVSYS_CHMUX_PRESCALER_8192_gc = (0x8D<<0), /* Prescaler, divide by 8192 */ - EVSYS_CHMUX_PRESCALER_16384_gc = (0x8E<<0), /* Prescaler, divide by 16384 */ - EVSYS_CHMUX_PRESCALER_32768_gc = (0x8F<<0), /* Prescaler, divide by 32768 */ - EVSYS_CHMUX_TCC0_OVF_gc = (0xC0<<0), /* Timer/Counter C0 Overflow */ - EVSYS_CHMUX_TCC0_ERR_gc = (0xC1<<0), /* Timer/Counter C0 Error */ - EVSYS_CHMUX_TCC0_CCA_gc = (0xC4<<0), /* Timer/Counter C0 Compare or Capture A */ - EVSYS_CHMUX_TCC0_CCB_gc = (0xC5<<0), /* Timer/Counter C0 Compare or Capture B */ - EVSYS_CHMUX_TCC0_CCC_gc = (0xC6<<0), /* Timer/Counter C0 Compare or Capture C */ - EVSYS_CHMUX_TCC0_CCD_gc = (0xC7<<0), /* Timer/Counter C0 Compare or Capture D */ - EVSYS_CHMUX_TCC1_OVF_gc = (0xC8<<0), /* Timer/Counter C1 Overflow */ - EVSYS_CHMUX_TCC1_ERR_gc = (0xC9<<0), /* Timer/Counter C1 Error */ - EVSYS_CHMUX_TCC1_CCA_gc = (0xCC<<0), /* Timer/Counter C1 Compare or Capture A */ - EVSYS_CHMUX_TCC1_CCB_gc = (0xCD<<0), /* Timer/Counter C1 Compare or Capture B */ - EVSYS_CHMUX_TCD0_OVF_gc = (0xD0<<0), /* Timer/Counter D0 Overflow */ - EVSYS_CHMUX_TCD0_ERR_gc = (0xD1<<0), /* Timer/Counter D0 Error */ - EVSYS_CHMUX_TCD0_CCA_gc = (0xD4<<0), /* Timer/Counter D0 Compare or Capture A */ - EVSYS_CHMUX_TCD0_CCB_gc = (0xD5<<0), /* Timer/Counter D0 Compare or Capture B */ - EVSYS_CHMUX_TCD0_CCC_gc = (0xD6<<0), /* Timer/Counter D0 Compare or Capture C */ - EVSYS_CHMUX_TCD0_CCD_gc = (0xD7<<0), /* Timer/Counter D0 Compare or Capture D */ - EVSYS_CHMUX_TCD1_OVF_gc = (0xD8<<0), /* Timer/Counter D1 Overflow */ - EVSYS_CHMUX_TCD1_ERR_gc = (0xD9<<0), /* Timer/Counter D1 Error */ - EVSYS_CHMUX_TCD1_CCA_gc = (0xDC<<0), /* Timer/Counter D1 Compare or Capture A */ - EVSYS_CHMUX_TCD1_CCB_gc = (0xDD<<0), /* Timer/Counter D1 Compare or Capture B */ - EVSYS_CHMUX_TCE0_OVF_gc = (0xE0<<0), /* Timer/Counter E0 Overflow */ - EVSYS_CHMUX_TCE0_ERR_gc = (0xE1<<0), /* Timer/Counter E0 Error */ - EVSYS_CHMUX_TCE0_CCA_gc = (0xE4<<0), /* Timer/Counter E0 Compare or Capture A */ - EVSYS_CHMUX_TCE0_CCB_gc = (0xE5<<0), /* Timer/Counter E0 Compare or Capture B */ - EVSYS_CHMUX_TCE0_CCC_gc = (0xE6<<0), /* Timer/Counter E0 Compare or Capture C */ - EVSYS_CHMUX_TCE0_CCD_gc = (0xE7<<0), /* Timer/Counter E0 Compare or Capture D */ - EVSYS_CHMUX_TCE1_OVF_gc = (0xE8<<0), /* Timer/Counter E1 Overflow */ - EVSYS_CHMUX_TCE1_ERR_gc = (0xE9<<0), /* Timer/Counter E1 Error */ - EVSYS_CHMUX_TCE1_CCA_gc = (0xEC<<0), /* Timer/Counter E1 Compare or Capture A */ - EVSYS_CHMUX_TCE1_CCB_gc = (0xED<<0), /* Timer/Counter E1 Compare or Capture B */ - EVSYS_CHMUX_TCF0_OVF_gc = (0xF0<<0), /* Timer/Counter F0 Overflow */ - EVSYS_CHMUX_TCF0_ERR_gc = (0xF1<<0), /* Timer/Counter F0 Error */ - EVSYS_CHMUX_TCF0_CCA_gc = (0xF4<<0), /* Timer/Counter F0 Compare or Capture A */ - EVSYS_CHMUX_TCF0_CCB_gc = (0xF5<<0), /* Timer/Counter F0 Compare or Capture B */ - EVSYS_CHMUX_TCF0_CCC_gc = (0xF6<<0), /* Timer/Counter F0 Compare or Capture C */ - EVSYS_CHMUX_TCF0_CCD_gc = (0xF7<<0), /* Timer/Counter F0 Compare or Capture D */ - EVSYS_CHMUX_TCF1_OVF_gc = (0xF8<<0), /* Timer/Counter F1 Overflow */ - EVSYS_CHMUX_TCF1_ERR_gc = (0xF9<<0), /* Timer/Counter F1 Error */ - EVSYS_CHMUX_TCF1_CCA_gc = (0xFC<<0), /* Timer/Counter F1 Compare or Capture A */ - EVSYS_CHMUX_TCF1_CCB_gc = (0xFD<<0), /* Timer/Counter F1 Compare or Capture B */ -} EVSYS_CHMUX_t; - - -/* --------------------------------------------------------------------------- -NVM - Non Volatile Memory Controller --------------------------------------------------------------------------- -*/ - -/* Non-volatile Memory Controller */ -typedef struct NVM_struct -{ - register8_t ADDR0; /* Address Register 0 */ - register8_t ADDR1; /* Address Register 1 */ - register8_t ADDR2; /* Address Register 2 */ - register8_t reserved_0x03; - register8_t DATA0; /* Data Register 0 */ - register8_t DATA1; /* Data Register 1 */ - register8_t DATA2; /* Data Register 2 */ - register8_t reserved_0x07; - register8_t reserved_0x08; - register8_t reserved_0x09; - register8_t CMD; /* Command */ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t INTCTRL; /* Interrupt Control */ - register8_t reserved_0x0E; - register8_t STATUS; /* Status */ - register8_t LOCK_BITS; /* Lock Bits (Changed from LOCKBITS to avoid avr-libc collision) */ -} NVM_t; - -/* NVM Command */ -typedef enum NVM_CMD_enum -{ - NVM_CMD_NO_OPERATION_gc = (0x00<<0), /* Noop/Ordinary LPM */ - NVM_CMD_READ_USER_SIG_ROW_gc = (0x01<<0), /* Read user signature row */ - NVM_CMD_READ_CALIB_ROW_gc = (0x02<<0), /* Read calibration row */ - NVM_CMD_READ_EEPROM_gc = (0x06<<0), /* Read EEPROM */ - NVM_CMD_READ_FUSES_gc = (0x07<<0), /* Read fuse byte */ - NVM_CMD_WRITE_LOCK_BITS_gc = (0x08<<0), /* Write lock bits */ - NVM_CMD_ERASE_USER_SIG_ROW_gc = (0x18<<0), /* Erase user signature row */ - NVM_CMD_WRITE_USER_SIG_ROW_gc = (0x1A<<0), /* Write user signature row */ - NVM_CMD_ERASE_APP_gc = (0x20<<0), /* Erase Application Section */ - NVM_CMD_ERASE_APP_PAGE_gc = (0x22<<0), /* Erase Application Section page */ - NVM_CMD_LOAD_FLASH_BUFFER_gc = (0x23<<0), /* Load Flash page buffer */ - NVM_CMD_WRITE_APP_PAGE_gc = (0x24<<0), /* Write Application Section page */ - NVM_CMD_ERASE_WRITE_APP_PAGE_gc = (0x25<<0), /* Erase-and-write Application Section page */ - NVM_CMD_ERASE_FLASH_BUFFER_gc = (0x26<<0), /* Erase/flush Flash page buffer */ - NVM_CMD_ERASE_BOOT_PAGE_gc = (0x2A<<0), /* Erase Boot Section page */ - NVM_CMD_ERASE_FLASH_PAGE_gc = (0x2B<<0), /* Erase Flash Page */ - NVM_CMD_WRITE_BOOT_PAGE_gc = (0x2C<<0), /* Write Boot Section page */ - NVM_CMD_ERASE_WRITE_BOOT_PAGE_gc = (0x2D<<0), /* Erase-and-write Boot Section page */ - NVM_CMD_WRITE_FLASH_PAGE_gc = (0x2E<<0), /* Write Flash Page */ - NVM_CMD_ERASE_WRITE_FLASH_PAGE_gc = (0x2F<<0), /* Erase-and-write Flash Page */ - NVM_CMD_ERASE_EEPROM_gc = (0x30<<0), /* Erase EEPROM */ - NVM_CMD_ERASE_EEPROM_PAGE_gc = (0x32<<0), /* Erase EEPROM page */ - NVM_CMD_LOAD_EEPROM_BUFFER_gc = (0x33<<0), /* Load EEPROM page buffer */ - NVM_CMD_WRITE_EEPROM_PAGE_gc = (0x34<<0), /* Write EEPROM page */ - NVM_CMD_ERASE_WRITE_EEPROM_PAGE_gc = (0x35<<0), /* Erase-and-write EEPROM page */ - NVM_CMD_ERASE_EEPROM_BUFFER_gc = (0x36<<0), /* Erase/flush EEPROM page buffer */ - NVM_CMD_APP_CRC_gc = (0x38<<0), /* Application section CRC */ - NVM_CMD_BOOT_CRC_gc = (0x39<<0), /* Boot Section CRC */ - NVM_CMD_FLASH_RANGE_CRC_gc = (0x3A<<0), /* Flash Range CRC */ - NVM_CMD_CHIP_ERASE_gc = (0x40<<0), /* Erase Chip */ - NVM_CMD_READ_NVM_gc = (0x43<<0), /* Read NVM */ - NVM_CMD_WRITE_FUSE_gc = (0x4C<<0), /* Write Fuse byte */ - NVM_CMD_ERASE_BOOT_gc = (0x68<<0), /* Erase Boot Section */ - NVM_CMD_FLASH_CRC_gc = (0x78<<0), /* Flash CRC */ -} NVM_CMD_t; - -/* SPM ready interrupt level */ -typedef enum NVM_SPMLVL_enum -{ - NVM_SPMLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ - NVM_SPMLVL_LO_gc = (0x01<<2), /* Low level */ - NVM_SPMLVL_MED_gc = (0x02<<2), /* Medium level */ - NVM_SPMLVL_HI_gc = (0x03<<2), /* High level */ -} NVM_SPMLVL_t; - -/* EEPROM ready interrupt level */ -typedef enum NVM_EELVL_enum -{ - NVM_EELVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ - NVM_EELVL_LO_gc = (0x01<<0), /* Low level */ - NVM_EELVL_MED_gc = (0x02<<0), /* Medium level */ - NVM_EELVL_HI_gc = (0x03<<0), /* High level */ -} NVM_EELVL_t; - -/* Boot lock bits - boot setcion */ -typedef enum NVM_BLBB_enum -{ - NVM_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ - NVM_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ - NVM_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ - NVM_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ -} NVM_BLBB_t; - -/* Boot lock bits - application section */ -typedef enum NVM_BLBA_enum -{ - NVM_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ - NVM_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ - NVM_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ - NVM_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ -} NVM_BLBA_t; - -/* Boot lock bits - application table section */ -typedef enum NVM_BLBAT_enum -{ - NVM_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ - NVM_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ - NVM_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ - NVM_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ -} NVM_BLBAT_t; - -/* Lock bits */ -typedef enum NVM_LB_enum -{ - NVM_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ - NVM_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ - NVM_LB_NOLOCK_gc = (0x03<<0), /* No locks */ -} NVM_LB_t; - - -/* --------------------------------------------------------------------------- -ADC - Analog/Digital Converter --------------------------------------------------------------------------- -*/ - -/* ADC Channel */ -typedef struct ADC_CH_struct -{ - register8_t CTRL; /* Control Register */ - register8_t MUXCTRL; /* MUX Control */ - register8_t INTCTRL; /* Channel Interrupt Control Register */ - register8_t INTFLAGS; /* Interrupt Flags */ - _WORDREGISTER(RES); /* Channel Result */ - register8_t SCAN; /* Input Channel Scan */ - register8_t reserved_0x07; -} ADC_CH_t; - - -/* Analog-to-Digital Converter */ -typedef struct ADC_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t REFCTRL; /* Reference Control */ - register8_t EVCTRL; /* Event Control */ - register8_t PRESCALER; /* Clock Prescaler */ - register8_t reserved_0x05; - register8_t INTFLAGS; /* Interrupt Flags */ - register8_t TEMP; /* Temporary Register */ - register8_t reserved_0x08; - register8_t reserved_0x09; - register8_t reserved_0x0A; - register8_t reserved_0x0B; - _WORDREGISTER(CAL); /* Calibration Value */ - register8_t reserved_0x0E; - register8_t reserved_0x0F; - _WORDREGISTER(CH0RES); /* Channel 0 Result */ - _WORDREGISTER(CH1RES); /* Channel 1 Result */ - _WORDREGISTER(CH2RES); /* Channel 2 Result */ - _WORDREGISTER(CH3RES); /* Channel 3 Result */ - _WORDREGISTER(CMP); /* Compare Value */ - register8_t reserved_0x1A; - register8_t reserved_0x1B; - register8_t reserved_0x1C; - register8_t reserved_0x1D; - register8_t reserved_0x1E; - register8_t reserved_0x1F; - ADC_CH_t CH0; /* ADC Channel 0 */ - ADC_CH_t CH1; /* ADC Channel 1 */ - ADC_CH_t CH2; /* ADC Channel 2 */ - ADC_CH_t CH3; /* ADC Channel 3 */ -} ADC_t; - -/* Positive input multiplexer selection */ -typedef enum ADC_CH_MUXPOS_enum -{ - ADC_CH_MUXPOS_PIN0_gc = (0x00<<3), /* Input pin 0 */ - ADC_CH_MUXPOS_PIN1_gc = (0x01<<3), /* Input pin 1 */ - ADC_CH_MUXPOS_PIN2_gc = (0x02<<3), /* Input pin 2 */ - ADC_CH_MUXPOS_PIN3_gc = (0x03<<3), /* Input pin 3 */ - ADC_CH_MUXPOS_PIN4_gc = (0x04<<3), /* Input pin 4 */ - ADC_CH_MUXPOS_PIN5_gc = (0x05<<3), /* Input pin 5 */ - ADC_CH_MUXPOS_PIN6_gc = (0x06<<3), /* Input pin 6 */ - ADC_CH_MUXPOS_PIN7_gc = (0x07<<3), /* Input pin 7 */ - ADC_CH_MUXPOS_PIN8_gc = (0x08<<3), /* Input pin 8 */ - ADC_CH_MUXPOS_PIN9_gc = (0x09<<3), /* Input pin 9 */ - ADC_CH_MUXPOS_PIN10_gc = (0x0A<<3), /* Input pin 10 */ - ADC_CH_MUXPOS_PIN11_gc = (0x0B<<3), /* Input pin 11 */ - ADC_CH_MUXPOS_PIN12_gc = (0x0C<<3), /* Input pin 12 */ - ADC_CH_MUXPOS_PIN13_gc = (0x0D<<3), /* Input pin 13 */ - ADC_CH_MUXPOS_PIN14_gc = (0x0E<<3), /* Input pin 14 */ - ADC_CH_MUXPOS_PIN15_gc = (0x0F<<3), /* Input pin 15 */ -} ADC_CH_MUXPOS_t; - -/* Internal input multiplexer selections */ -typedef enum ADC_CH_MUXINT_enum -{ - ADC_CH_MUXINT_TEMP_gc = (0x00<<3), /* Temperature Reference */ - ADC_CH_MUXINT_BANDGAP_gc = (0x01<<3), /* Bandgap Reference */ - ADC_CH_MUXINT_SCALEDVCC_gc = (0x02<<3), /* 1/10 scaled VCC */ - ADC_CH_MUXINT_DAC_gc = (0x03<<3), /* DAC output */ -} ADC_CH_MUXINT_t; - -/* Negative input multiplexer selection */ -typedef enum ADC_CH_MUXNEG_enum -{ - ADC_CH_MUXNEG_PIN0_gc = (0x00<<0), /* Input pin 0 (Input Mode = 2) */ - ADC_CH_MUXNEG_PIN1_gc = (0x01<<0), /* Input pin 1 (Input Mode = 2) */ - ADC_CH_MUXNEG_PIN2_gc = (0x02<<0), /* Input pin 2 (Input Mode = 2) */ - ADC_CH_MUXNEG_PIN3_gc = (0x03<<0), /* Input pin 3 (Input Mode = 2) */ - ADC_CH_MUXNEG_PIN4_gc = (0x00<<0), /* Input pin 4 (Input Mode = 3) */ - ADC_CH_MUXNEG_PIN5_gc = (0x01<<0), /* Input pin 5 (Input Mode = 3) */ - ADC_CH_MUXNEG_PIN6_gc = (0x02<<0), /* Input pin 6 (Input Mode = 3) */ - ADC_CH_MUXNEG_PIN7_gc = (0x03<<0), /* Input pin 7 (Input Mode = 3) */ - ADC_CH_MUXNEG_GND_MODE3_gc = (0x05<<0), /* PAD Ground (Input Mode = 2) */ - ADC_CH_MUXNEG_INTGND_MODE3_gc = (0x07<<0), /* Internal Ground (Input Mode = 2) */ - ADC_CH_MUXNEG_INTGND_MODE4_gc = (0x04<<0), /* Internal Ground (Input Mode = 3) */ - ADC_CH_MUXNEG_GND_MODE4_gc = (0x07<<0), /* PAD Ground (Input Mode = 3) */ -} ADC_CH_MUXNEG_t; - -/* Input mode */ -typedef enum ADC_CH_INPUTMODE_enum -{ - ADC_CH_INPUTMODE_INTERNAL_gc = (0x00<<0), /* Internal inputs, no gain */ - ADC_CH_INPUTMODE_SINGLEENDED_gc = (0x01<<0), /* Single-ended input, no gain */ - ADC_CH_INPUTMODE_DIFF_gc = (0x02<<0), /* Differential input, no gain */ - ADC_CH_INPUTMODE_DIFFWGAIN_gc = (0x03<<0), /* Differential input, with gain */ -} ADC_CH_INPUTMODE_t; - -/* Gain factor */ -typedef enum ADC_CH_GAIN_enum -{ - ADC_CH_GAIN_1X_gc = (0x00<<2), /* 1x gain */ - ADC_CH_GAIN_2X_gc = (0x01<<2), /* 2x gain */ - ADC_CH_GAIN_4X_gc = (0x02<<2), /* 4x gain */ - ADC_CH_GAIN_8X_gc = (0x03<<2), /* 8x gain */ - ADC_CH_GAIN_16X_gc = (0x04<<2), /* 16x gain */ - ADC_CH_GAIN_32X_gc = (0x05<<2), /* 32x gain */ - ADC_CH_GAIN_64X_gc = (0x06<<2), /* 64x gain */ - ADC_CH_GAIN_DIV2_gc = (0x07<<2), /* x/2 gain */ -} ADC_CH_GAIN_t; - -/* Conversion result resolution */ -typedef enum ADC_RESOLUTION_enum -{ - ADC_RESOLUTION_12BIT_gc = (0x00<<1), /* 12-bit right-adjusted result */ - ADC_RESOLUTION_8BIT_gc = (0x02<<1), /* 8-bit right-adjusted result */ - ADC_RESOLUTION_LEFT12BIT_gc = (0x03<<1), /* 12-bit left-adjusted result */ -} ADC_RESOLUTION_t; - -/* Current Limitation Mode */ -typedef enum ADC_CURRLIMIT_enum -{ - ADC_CURRLIMIT_NO_gc = (0x00<<5), /* No limit */ - ADC_CURRLIMIT_LOW_gc = (0x01<<5), /* Low current limit, max. sampling rate 1.5MSPS */ - ADC_CURRLIMIT_MED_gc = (0x02<<5), /* Medium current limit, max. sampling rate 1MSPS */ - ADC_CURRLIMIT_HIGH_gc = (0x03<<5), /* High current limit, max. sampling rate 0.5MSPS */ -} ADC_CURRLIMIT_t; - -/* Voltage reference selection */ -typedef enum ADC_REFSEL_enum -{ - ADC_REFSEL_INT1V_gc = (0x00<<4), /* Internal 1V */ - ADC_REFSEL_INTVCC_gc = (0x01<<4), /* Internal VCC / 1.6 */ - ADC_REFSEL_AREFA_gc = (0x02<<4), /* External reference on PORT A */ - ADC_REFSEL_AREFB_gc = (0x03<<4), /* External reference on PORT B */ - ADC_REFSEL_INTVCC2_gc = (0x04<<4), /* Internal VCC / 2 */ -} ADC_REFSEL_t; - -/* Channel sweep selection */ -typedef enum ADC_SWEEP_enum -{ - ADC_SWEEP_0_gc = (0x00<<6), /* ADC Channel 0 */ - ADC_SWEEP_01_gc = (0x01<<6), /* ADC Channel 0,1 */ - ADC_SWEEP_012_gc = (0x02<<6), /* ADC Channel 0,1,2 */ - ADC_SWEEP_0123_gc = (0x03<<6), /* ADC Channel 0,1,2,3 */ -} ADC_SWEEP_t; - -/* Event channel input selection */ -typedef enum ADC_EVSEL_enum -{ - ADC_EVSEL_0123_gc = (0x00<<3), /* Event Channel 0,1,2,3 */ - ADC_EVSEL_1234_gc = (0x01<<3), /* Event Channel 1,2,3,4 */ - ADC_EVSEL_2345_gc = (0x02<<3), /* Event Channel 2,3,4,5 */ - ADC_EVSEL_3456_gc = (0x03<<3), /* Event Channel 3,4,5,6 */ - ADC_EVSEL_4567_gc = (0x04<<3), /* Event Channel 4,5,6,7 */ - ADC_EVSEL_567_gc = (0x05<<3), /* Event Channel 5,6,7 */ - ADC_EVSEL_67_gc = (0x06<<3), /* Event Channel 6,7 */ - ADC_EVSEL_7_gc = (0x07<<3), /* Event Channel 7 */ -} ADC_EVSEL_t; - -/* Event action selection */ -typedef enum ADC_EVACT_enum -{ - ADC_EVACT_NONE_gc = (0x00<<0), /* No event action */ - ADC_EVACT_CH0_gc = (0x01<<0), /* First event triggers channel 0 */ - ADC_EVACT_CH01_gc = (0x02<<0), /* First two events trigger channel 0,1 */ - ADC_EVACT_CH012_gc = (0x03<<0), /* First three events trigger channel 0,1,2 */ - ADC_EVACT_CH0123_gc = (0x04<<0), /* Events trigger channel 0,1,2,3 */ - ADC_EVACT_SWEEP_gc = (0x05<<0), /* First event triggers sweep */ - ADC_EVACT_SYNCSWEEP_gc = (0x06<<0), /* The ADC is flushed and restarted for accurate timing */ -} ADC_EVACT_t; - -/* Interupt mode */ -typedef enum ADC_CH_INTMODE_enum -{ - ADC_CH_INTMODE_COMPLETE_gc = (0x00<<2), /* Interrupt on conversion complete */ - ADC_CH_INTMODE_BELOW_gc = (0x01<<2), /* Interrupt on result below compare value */ - ADC_CH_INTMODE_ABOVE_gc = (0x03<<2), /* Interrupt on result above compare value */ -} ADC_CH_INTMODE_t; - -/* Interrupt level */ -typedef enum ADC_CH_INTLVL_enum -{ - ADC_CH_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ - ADC_CH_INTLVL_LO_gc = (0x01<<0), /* Low level */ - ADC_CH_INTLVL_MED_gc = (0x02<<0), /* Medium level */ - ADC_CH_INTLVL_HI_gc = (0x03<<0), /* High level */ -} ADC_CH_INTLVL_t; - -/* DMA request selection */ -typedef enum ADC_DMASEL_enum -{ - ADC_DMASEL_OFF_gc = (0x00<<6), /* Combined DMA request OFF */ - ADC_DMASEL_CH01_gc = (0x01<<6), /* ADC Channel 0 or 1 */ - ADC_DMASEL_CH012_gc = (0x02<<6), /* ADC Channel 0 or 1 or 2 */ - ADC_DMASEL_CH0123_gc = (0x03<<6), /* ADC Channel 0 or 1 or 2 or 3 */ -} ADC_DMASEL_t; - -/* Clock prescaler */ -typedef enum ADC_PRESCALER_enum -{ - ADC_PRESCALER_DIV4_gc = (0x00<<0), /* Divide clock by 4 */ - ADC_PRESCALER_DIV8_gc = (0x01<<0), /* Divide clock by 8 */ - ADC_PRESCALER_DIV16_gc = (0x02<<0), /* Divide clock by 16 */ - ADC_PRESCALER_DIV32_gc = (0x03<<0), /* Divide clock by 32 */ - ADC_PRESCALER_DIV64_gc = (0x04<<0), /* Divide clock by 64 */ - ADC_PRESCALER_DIV128_gc = (0x05<<0), /* Divide clock by 128 */ - ADC_PRESCALER_DIV256_gc = (0x06<<0), /* Divide clock by 256 */ - ADC_PRESCALER_DIV512_gc = (0x07<<0), /* Divide clock by 512 */ -} ADC_PRESCALER_t; - - -/* --------------------------------------------------------------------------- -DAC - Digital/Analog Converter --------------------------------------------------------------------------- -*/ - -/* Digital-to-Analog Converter */ -typedef struct DAC_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t CTRLC; /* Control Register C */ - register8_t EVCTRL; /* Event Input Control */ - register8_t reserved_0x04; - register8_t STATUS; /* Status */ - register8_t reserved_0x06; - register8_t reserved_0x07; - register8_t CH0GAINCAL; /* Gain Calibration */ - register8_t CH0OFFSETCAL; /* Offset Calibration */ - register8_t CH1GAINCAL; /* Gain Calibration */ - register8_t CH1OFFSETCAL; /* Offset Calibration */ - register8_t reserved_0x0C; - register8_t reserved_0x0D; - register8_t reserved_0x0E; - register8_t reserved_0x0F; - register8_t reserved_0x10; - register8_t reserved_0x11; - register8_t reserved_0x12; - register8_t reserved_0x13; - register8_t reserved_0x14; - register8_t reserved_0x15; - register8_t reserved_0x16; - register8_t reserved_0x17; - _WORDREGISTER(CH0DATA); /* Channel 0 Data */ - _WORDREGISTER(CH1DATA); /* Channel 1 Data */ -} DAC_t; - -/* Output channel selection */ -typedef enum DAC_CHSEL_enum -{ - DAC_CHSEL_SINGLE_gc = (0x00<<5), /* Single channel operation (Channel 0 only) */ - DAC_CHSEL_SINGLE1_gc = (0x01<<5), /* Single channel operation (Channel 1 only) */ - DAC_CHSEL_DUAL_gc = (0x02<<5), /* Dual channel operation (Channel 0 and channel 1) */ -} DAC_CHSEL_t; - -/* Reference voltage selection */ -typedef enum DAC_REFSEL_enum -{ - DAC_REFSEL_INT1V_gc = (0x00<<3), /* Internal 1V */ - DAC_REFSEL_AVCC_gc = (0x01<<3), /* Analog supply voltage */ - DAC_REFSEL_AREFA_gc = (0x02<<3), /* External reference on AREF on PORTA */ - DAC_REFSEL_AREFB_gc = (0x03<<3), /* External reference on AREF on PORTB */ -} DAC_REFSEL_t; - -/* Event channel selection */ -typedef enum DAC_EVSEL_enum -{ - DAC_EVSEL_0_gc = (0x00<<0), /* Event Channel 0 */ - DAC_EVSEL_1_gc = (0x01<<0), /* Event Channel 1 */ - DAC_EVSEL_2_gc = (0x02<<0), /* Event Channel 2 */ - DAC_EVSEL_3_gc = (0x03<<0), /* Event Channel 3 */ - DAC_EVSEL_4_gc = (0x04<<0), /* Event Channel 4 */ - DAC_EVSEL_5_gc = (0x05<<0), /* Event Channel 5 */ - DAC_EVSEL_6_gc = (0x06<<0), /* Event Channel 6 */ - DAC_EVSEL_7_gc = (0x07<<0), /* Event Channel 7 */ -} DAC_EVSEL_t; - - -/* --------------------------------------------------------------------------- -AC - Analog Comparator --------------------------------------------------------------------------- -*/ - -/* Analog Comparator */ -typedef struct AC_struct -{ - register8_t AC0CTRL; /* Analog Comparator 0 Control */ - register8_t AC1CTRL; /* Analog Comparator 1 Control */ - register8_t AC0MUXCTRL; /* Analog Comparator 0 MUX Control */ - register8_t AC1MUXCTRL; /* Analog Comparator 1 MUX Control */ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t WINCTRL; /* Window Mode Control */ - register8_t STATUS; /* Status */ -} AC_t; - -/* Interrupt mode */ -typedef enum AC_INTMODE_enum -{ - AC_INTMODE_BOTHEDGES_gc = (0x00<<6), /* Interrupt on both edges */ - AC_INTMODE_FALLING_gc = (0x02<<6), /* Interrupt on falling edge */ - AC_INTMODE_RISING_gc = (0x03<<6), /* Interrupt on rising edge */ -} AC_INTMODE_t; - -/* Interrupt level */ -typedef enum AC_INTLVL_enum -{ - AC_INTLVL_OFF_gc = (0x00<<4), /* Interrupt disabled */ - AC_INTLVL_LO_gc = (0x01<<4), /* Low level */ - AC_INTLVL_MED_gc = (0x02<<4), /* Medium level */ - AC_INTLVL_HI_gc = (0x03<<4), /* High level */ -} AC_INTLVL_t; - -/* Hysteresis mode selection */ -typedef enum AC_HYSMODE_enum -{ - AC_HYSMODE_NO_gc = (0x00<<1), /* No hysteresis */ - AC_HYSMODE_SMALL_gc = (0x01<<1), /* Small hysteresis */ - AC_HYSMODE_LARGE_gc = (0x02<<1), /* Large hysteresis */ -} AC_HYSMODE_t; - -/* Positive input multiplexer selection */ -typedef enum AC_MUXPOS_enum -{ - AC_MUXPOS_PIN0_gc = (0x00<<3), /* Pin 0 */ - AC_MUXPOS_PIN1_gc = (0x01<<3), /* Pin 1 */ - AC_MUXPOS_PIN2_gc = (0x02<<3), /* Pin 2 */ - AC_MUXPOS_PIN3_gc = (0x03<<3), /* Pin 3 */ - AC_MUXPOS_PIN4_gc = (0x04<<3), /* Pin 4 */ - AC_MUXPOS_PIN5_gc = (0x05<<3), /* Pin 5 */ - AC_MUXPOS_PIN6_gc = (0x06<<3), /* Pin 6 */ - AC_MUXPOS_DAC_gc = (0x07<<3), /* DAC output */ -} AC_MUXPOS_t; - -/* Negative input multiplexer selection */ -typedef enum AC_MUXNEG_enum -{ - AC_MUXNEG_PIN0_gc = (0x00<<0), /* Pin 0 */ - AC_MUXNEG_PIN1_gc = (0x01<<0), /* Pin 1 */ - AC_MUXNEG_PIN3_gc = (0x02<<0), /* Pin 3 */ - AC_MUXNEG_PIN5_gc = (0x03<<0), /* Pin 5 */ - AC_MUXNEG_PIN7_gc = (0x04<<0), /* Pin 7 */ - AC_MUXNEG_DAC_gc = (0x05<<0), /* DAC output */ - AC_MUXNEG_BANDGAP_gc = (0x06<<0), /* Bandgap Reference */ - AC_MUXNEG_SCALER_gc = (0x07<<0), /* Internal voltage scaler */ -} AC_MUXNEG_t; - -/* Windows interrupt mode */ -typedef enum AC_WINTMODE_enum -{ - AC_WINTMODE_ABOVE_gc = (0x00<<2), /* Interrupt on above window */ - AC_WINTMODE_INSIDE_gc = (0x01<<2), /* Interrupt on inside window */ - AC_WINTMODE_BELOW_gc = (0x02<<2), /* Interrupt on below window */ - AC_WINTMODE_OUTSIDE_gc = (0x03<<2), /* Interrupt on outside window */ -} AC_WINTMODE_t; - -/* Window interrupt level */ -typedef enum AC_WINTLVL_enum -{ - AC_WINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ - AC_WINTLVL_LO_gc = (0x01<<0), /* Low priority */ - AC_WINTLVL_MED_gc = (0x02<<0), /* Medium priority */ - AC_WINTLVL_HI_gc = (0x03<<0), /* High priority */ -} AC_WINTLVL_t; - -/* Window mode state */ -typedef enum AC_WSTATE_enum -{ - AC_WSTATE_ABOVE_gc = (0x00<<6), /* Signal above window */ - AC_WSTATE_INSIDE_gc = (0x01<<6), /* Signal inside window */ - AC_WSTATE_BELOW_gc = (0x02<<6), /* Signal below window */ -} AC_WSTATE_t; - - -/* --------------------------------------------------------------------------- -RTC - Real-Time Counter --------------------------------------------------------------------------- -*/ - -/* Real-Time Counter */ -typedef struct RTC_struct -{ - register8_t CTRL; /* Control Register */ - register8_t STATUS; /* Status Register */ - register8_t INTCTRL; /* Interrupt Control Register */ - register8_t INTFLAGS; /* Interrupt Flags */ - register8_t TEMP; /* Temporary register */ - register8_t reserved_0x05; - register8_t reserved_0x06; - register8_t reserved_0x07; - _WORDREGISTER(CNT); /* Count Register */ - _WORDREGISTER(PER); /* Period Register */ - _WORDREGISTER(COMP); /* Compare Register */ -} RTC_t; - -/* Prescaler Factor */ -typedef enum RTC_PRESCALER_enum -{ - RTC_PRESCALER_OFF_gc = (0x00<<0), /* RTC Off */ - RTC_PRESCALER_DIV1_gc = (0x01<<0), /* RTC Clock */ - RTC_PRESCALER_DIV2_gc = (0x02<<0), /* RTC Clock / 2 */ - RTC_PRESCALER_DIV8_gc = (0x03<<0), /* RTC Clock / 8 */ - RTC_PRESCALER_DIV16_gc = (0x04<<0), /* RTC Clock / 16 */ - RTC_PRESCALER_DIV64_gc = (0x05<<0), /* RTC Clock / 64 */ - RTC_PRESCALER_DIV256_gc = (0x06<<0), /* RTC Clock / 256 */ - RTC_PRESCALER_DIV1024_gc = (0x07<<0), /* RTC Clock / 1024 */ -} RTC_PRESCALER_t; - -/* Compare Interrupt level */ -typedef enum RTC_COMPINTLVL_enum -{ - RTC_COMPINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ - RTC_COMPINTLVL_LO_gc = (0x01<<2), /* Low Level */ - RTC_COMPINTLVL_MED_gc = (0x02<<2), /* Medium Level */ - RTC_COMPINTLVL_HI_gc = (0x03<<2), /* High Level */ -} RTC_COMPINTLVL_t; - -/* Overflow Interrupt level */ -typedef enum RTC_OVFINTLVL_enum -{ - RTC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - RTC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ - RTC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ - RTC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ -} RTC_OVFINTLVL_t; - - -/* --------------------------------------------------------------------------- -EBI - External Bus Interface --------------------------------------------------------------------------- -*/ - -/* EBI Chip Select Module */ -typedef struct EBI_CS_struct -{ - register8_t CTRLA; /* Chip Select Control Register A */ - register8_t CTRLB; /* Chip Select Control Register B */ - _WORDREGISTER(BASEADDR); /* Chip Select Base Address */ -} EBI_CS_t; - - -/* External Bus Interface */ -typedef struct EBI_struct -{ - register8_t CTRL; /* Control */ - register8_t SDRAMCTRLA; /* SDRAM Control Register A */ - register8_t reserved_0x02; - register8_t reserved_0x03; - _WORDREGISTER(REFRESH); /* SDRAM Refresh Period */ - _WORDREGISTER(INITDLY); /* SDRAM Initialization Delay */ - register8_t SDRAMCTRLB; /* SDRAM Control Register B */ - register8_t SDRAMCTRLC; /* SDRAM Control Register C */ - register8_t reserved_0x0A; - register8_t reserved_0x0B; - register8_t reserved_0x0C; - register8_t reserved_0x0D; - register8_t reserved_0x0E; - register8_t reserved_0x0F; - EBI_CS_t CS0; /* Chip Select 0 */ - EBI_CS_t CS1; /* Chip Select 1 */ - EBI_CS_t CS2; /* Chip Select 2 */ - EBI_CS_t CS3; /* Chip Select 3 */ -} EBI_t; - -/* Chip Select adress space */ -typedef enum EBI_CS_ASPACE_enum -{ - EBI_CS_ASPACE_256B_gc = (0x00<<2), /* 256 bytes */ - EBI_CS_ASPACE_512B_gc = (0x01<<2), /* 512 bytes */ - EBI_CS_ASPACE_1KB_gc = (0x02<<2), /* 1K bytes */ - EBI_CS_ASPACE_2KB_gc = (0x03<<2), /* 2K bytes */ - EBI_CS_ASPACE_4KB_gc = (0x04<<2), /* 4K bytes */ - EBI_CS_ASPACE_8KB_gc = (0x05<<2), /* 8K bytes */ - EBI_CS_ASPACE_16KB_gc = (0x06<<2), /* 16K bytes */ - EBI_CS_ASPACE_32KB_gc = (0x07<<2), /* 32K bytes */ - EBI_CS_ASPACE_64KB_gc = (0x08<<2), /* 64K bytes */ - EBI_CS_ASPACE_128KB_gc = (0x09<<2), /* 128K bytes */ - EBI_CS_ASPACE_256KB_gc = (0x0A<<2), /* 256K bytes */ - EBI_CS_ASPACE_512KB_gc = (0x0B<<2), /* 512K bytes */ - EBI_CS_ASPACE_1MB_gc = (0x0C<<2), /* 1M bytes */ - EBI_CS_ASPACE_2MB_gc = (0x0D<<2), /* 2M bytes */ - EBI_CS_ASPACE_4MB_gc = (0x0E<<2), /* 4M bytes */ - EBI_CS_ASPACE_8MB_gc = (0x0F<<2), /* 8M bytes */ - EBI_CS_ASPACE_16M_gc = (0x10<<2), /* 16M bytes */ -} EBI_CS_ASPACE_t; - -/* SRAM Wait State Selection */ -typedef enum EBI_CS_SRWS_enum -{ - EBI_CS_SRWS_0CLK_gc = (0x00<<0), /* 0 cycles */ - EBI_CS_SRWS_1CLK_gc = (0x01<<0), /* 1 cycle */ - EBI_CS_SRWS_2CLK_gc = (0x02<<0), /* 2 cycles */ - EBI_CS_SRWS_3CLK_gc = (0x03<<0), /* 3 cycles */ - EBI_CS_SRWS_4CLK_gc = (0x04<<0), /* 4 cycles */ - EBI_CS_SRWS_5CLK_gc = (0x05<<0), /* 5 cycles */ - EBI_CS_SRWS_6CLK_gc = (0x06<<0), /* 6 cycles */ - EBI_CS_SRWS_7CLK_gc = (0x07<<0), /* 7 cycles */ -} EBI_CS_SRWS_t; - -/* Chip Select address mode */ -typedef enum EBI_CS_MODE_enum -{ - EBI_CS_MODE_DISABLED_gc = (0x00<<0), /* Chip Select Disabled */ - EBI_CS_MODE_SRAM_gc = (0x01<<0), /* Chip Select in SRAM mode */ - EBI_CS_MODE_LPC_gc = (0x02<<0), /* Chip Select in SRAM LPC mode */ - EBI_CS_MODE_SDRAM_gc = (0x03<<0), /* Chip Select in SDRAM mode */ -} EBI_CS_MODE_t; - -/* Chip Select SDRAM mode */ -typedef enum EBI_CS_SDMODE_enum -{ - EBI_CS_SDMODE_NORMAL_gc = (0x00<<0), /* Normal mode */ - EBI_CS_SDMODE_LOAD_gc = (0x01<<0), /* Load Mode Register command mode */ -} EBI_CS_SDMODE_t; - -/* */ -typedef enum EBI_SDDATAW_enum -{ - EBI_SDDATAW_4BIT_gc = (0x00<<6), /* 4-bit data bus */ - EBI_SDDATAW_8BIT_gc = (0x01<<6), /* 8-bit data bus */ -} EBI_SDDATAW_t; - -/* */ -typedef enum EBI_LPCMODE_enum -{ - EBI_LPCMODE_ALE1_gc = (0x00<<4), /* Data muxed with addr byte 0 */ - EBI_LPCMODE_ALE12_gc = (0x02<<4), /* Data muxed with addr byte 0 and 1 */ -} EBI_LPCMODE_t; - -/* */ -typedef enum EBI_SRMODE_enum -{ - EBI_SRMODE_ALE1_gc = (0x00<<2), /* Addr byte 0 muxed with 1 */ - EBI_SRMODE_ALE2_gc = (0x01<<2), /* Addr byte 0 muxed with 2 */ - EBI_SRMODE_ALE12_gc = (0x02<<2), /* Addr byte 0 muxed with 1 and 2 */ - EBI_SRMODE_NOALE_gc = (0x03<<2), /* No addr muxing */ -} EBI_SRMODE_t; - -/* */ -typedef enum EBI_IFMODE_enum -{ - EBI_IFMODE_DISABLED_gc = (0x00<<0), /* EBI Disabled */ - EBI_IFMODE_3PORT_gc = (0x01<<0), /* 3-port mode */ - EBI_IFMODE_4PORT_gc = (0x02<<0), /* 4-port mode */ - EBI_IFMODE_2PORT_gc = (0x03<<0), /* 2-port mode */ -} EBI_IFMODE_t; - -/* */ -typedef enum EBI_SDCOL_enum -{ - EBI_SDCOL_8BIT_gc = (0x00<<0), /* 8 column bits */ - EBI_SDCOL_9BIT_gc = (0x01<<0), /* 9 column bits */ - EBI_SDCOL_10BIT_gc = (0x02<<0), /* 10 column bits */ - EBI_SDCOL_11BIT_gc = (0x03<<0), /* 11 column bits */ -} EBI_SDCOL_t; - -/* SDRAM Load Mode to Active delay */ -typedef enum EBI_MRDLY_enum -{ - EBI_MRDLY_0CLK_gc = (0x00<<6), /* 0 cycles */ - EBI_MRDLY_1CLK_gc = (0x01<<6), /* 1 cycle */ - EBI_MRDLY_2CLK_gc = (0x02<<6), /* 2 cycles */ - EBI_MRDLY_3CLK_gc = (0x03<<6), /* 3 cycles */ -} EBI_MRDLY_t; - -/* SDRAM Row Cycle Delay */ -typedef enum EBI_ROWCYCDLY_enum -{ - EBI_ROWCYCDLY_0CLK_gc = (0x00<<3), /* 0 cycles */ - EBI_ROWCYCDLY_1CLK_gc = (0x01<<3), /* 1 cycle */ - EBI_ROWCYCDLY_2CLK_gc = (0x02<<3), /* 2 cycles */ - EBI_ROWCYCDLY_3CLK_gc = (0x03<<3), /* 3 cycles */ - EBI_ROWCYCDLY_4CLK_gc = (0x04<<3), /* 4 cycles */ - EBI_ROWCYCDLY_5CLK_gc = (0x05<<3), /* 5 cycles */ - EBI_ROWCYCDLY_6CLK_gc = (0x06<<3), /* 6 cycles */ - EBI_ROWCYCDLY_7CLK_gc = (0x07<<3), /* 7 cycles */ -} EBI_ROWCYCDLY_t; - -/* SDRAM Row to Precharge Delay */ -typedef enum EBI_RPDLY_enum -{ - EBI_RPDLY_0CLK_gc = (0x00<<0), /* 0 cycles */ - EBI_RPDLY_1CLK_gc = (0x01<<0), /* 1 cycle */ - EBI_RPDLY_2CLK_gc = (0x02<<0), /* 2 cycles */ - EBI_RPDLY_3CLK_gc = (0x03<<0), /* 3 cycles */ - EBI_RPDLY_4CLK_gc = (0x04<<0), /* 4 cycles */ - EBI_RPDLY_5CLK_gc = (0x05<<0), /* 5 cycles */ - EBI_RPDLY_6CLK_gc = (0x06<<0), /* 6 cycles */ - EBI_RPDLY_7CLK_gc = (0x07<<0), /* 7 cycles */ -} EBI_RPDLY_t; - -/* SDRAM Write Recovery Delay */ -typedef enum EBI_WRDLY_enum -{ - EBI_WRDLY_0CLK_gc = (0x00<<6), /* 0 cycles */ - EBI_WRDLY_1CLK_gc = (0x01<<6), /* 1 cycle */ - EBI_WRDLY_2CLK_gc = (0x02<<6), /* 2 cycles */ - EBI_WRDLY_3CLK_gc = (0x03<<6), /* 3 cycles */ -} EBI_WRDLY_t; - -/* SDRAM Exit Self Refresh to Active Delay */ -typedef enum EBI_ESRDLY_enum -{ - EBI_ESRDLY_0CLK_gc = (0x00<<3), /* 0 cycles */ - EBI_ESRDLY_1CLK_gc = (0x01<<3), /* 1 cycle */ - EBI_ESRDLY_2CLK_gc = (0x02<<3), /* 2 cycles */ - EBI_ESRDLY_3CLK_gc = (0x03<<3), /* 3 cycles */ - EBI_ESRDLY_4CLK_gc = (0x04<<3), /* 4 cycles */ - EBI_ESRDLY_5CLK_gc = (0x05<<3), /* 5 cycles */ - EBI_ESRDLY_6CLK_gc = (0x06<<3), /* 6 cycles */ - EBI_ESRDLY_7CLK_gc = (0x07<<3), /* 7 cycles */ -} EBI_ESRDLY_t; - -/* SDRAM Row to Column Delay */ -typedef enum EBI_ROWCOLDLY_enum -{ - EBI_ROWCOLDLY_0CLK_gc = (0x00<<0), /* 0 cycles */ - EBI_ROWCOLDLY_1CLK_gc = (0x01<<0), /* 1 cycle */ - EBI_ROWCOLDLY_2CLK_gc = (0x02<<0), /* 2 cycles */ - EBI_ROWCOLDLY_3CLK_gc = (0x03<<0), /* 3 cycles */ - EBI_ROWCOLDLY_4CLK_gc = (0x04<<0), /* 4 cycles */ - EBI_ROWCOLDLY_5CLK_gc = (0x05<<0), /* 5 cycles */ - EBI_ROWCOLDLY_6CLK_gc = (0x06<<0), /* 6 cycles */ - EBI_ROWCOLDLY_7CLK_gc = (0x07<<0), /* 7 cycles */ -} EBI_ROWCOLDLY_t; - - -/* --------------------------------------------------------------------------- -TWI - Two-Wire Interface --------------------------------------------------------------------------- -*/ - -/* */ -typedef struct TWI_MASTER_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t CTRLC; /* Control Register C */ - register8_t STATUS; /* Status Register */ - register8_t BAUD; /* Baurd Rate Control Register */ - register8_t ADDR; /* Address Register */ - register8_t DATA; /* Data Register */ -} TWI_MASTER_t; - - -/* */ -typedef struct TWI_SLAVE_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t STATUS; /* Status Register */ - register8_t ADDR; /* Address Register */ - register8_t DATA; /* Data Register */ - register8_t ADDRMASK; /* Address Mask Register */ -} TWI_SLAVE_t; - - -/* Two-Wire Interface */ -typedef struct TWI_struct -{ - register8_t CTRL; /* TWI Common Control Register */ - TWI_MASTER_t MASTER; /* TWI master module */ - TWI_SLAVE_t SLAVE; /* TWI slave module */ -} TWI_t; - -/* Master Interrupt Level */ -typedef enum TWI_MASTER_INTLVL_enum -{ - TWI_MASTER_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ - TWI_MASTER_INTLVL_LO_gc = (0x01<<6), /* Low Level */ - TWI_MASTER_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ - TWI_MASTER_INTLVL_HI_gc = (0x03<<6), /* High Level */ -} TWI_MASTER_INTLVL_t; - -/* Inactive Timeout */ -typedef enum TWI_MASTER_TIMEOUT_enum -{ - TWI_MASTER_TIMEOUT_DISABLED_gc = (0x00<<2), /* Bus Timeout Disabled */ - TWI_MASTER_TIMEOUT_50US_gc = (0x01<<2), /* 50 Microseconds */ - TWI_MASTER_TIMEOUT_100US_gc = (0x02<<2), /* 100 Microseconds */ - TWI_MASTER_TIMEOUT_200US_gc = (0x03<<2), /* 200 Microseconds */ -} TWI_MASTER_TIMEOUT_t; - -/* Master Command */ -typedef enum TWI_MASTER_CMD_enum -{ - TWI_MASTER_CMD_NOACT_gc = (0x00<<0), /* No Action */ - TWI_MASTER_CMD_REPSTART_gc = (0x01<<0), /* Issue Repeated Start Condition */ - TWI_MASTER_CMD_RECVTRANS_gc = (0x02<<0), /* Receive or Transmit Data */ - TWI_MASTER_CMD_STOP_gc = (0x03<<0), /* Issue Stop Condition */ -} TWI_MASTER_CMD_t; - -/* Master Bus State */ -typedef enum TWI_MASTER_BUSSTATE_enum -{ - TWI_MASTER_BUSSTATE_UNKNOWN_gc = (0x00<<0), /* Unknown Bus State */ - TWI_MASTER_BUSSTATE_IDLE_gc = (0x01<<0), /* Bus is Idle */ - TWI_MASTER_BUSSTATE_OWNER_gc = (0x02<<0), /* This Module Controls The Bus */ - TWI_MASTER_BUSSTATE_BUSY_gc = (0x03<<0), /* The Bus is Busy */ -} TWI_MASTER_BUSSTATE_t; - -/* Slave Interrupt Level */ -typedef enum TWI_SLAVE_INTLVL_enum -{ - TWI_SLAVE_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ - TWI_SLAVE_INTLVL_LO_gc = (0x01<<6), /* Low Level */ - TWI_SLAVE_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ - TWI_SLAVE_INTLVL_HI_gc = (0x03<<6), /* High Level */ -} TWI_SLAVE_INTLVL_t; - -/* Slave Command */ -typedef enum TWI_SLAVE_CMD_enum -{ - TWI_SLAVE_CMD_NOACT_gc = (0x00<<0), /* No Action */ - TWI_SLAVE_CMD_COMPTRANS_gc = (0x02<<0), /* Used To Complete a Transaction */ - TWI_SLAVE_CMD_RESPONSE_gc = (0x03<<0), /* Used in Response to Address/Data Interrupt */ -} TWI_SLAVE_CMD_t; - -/* SDA hold time */ -typedef enum SDA_HOLD_TIME_enum -{ - SDA_HOLD_TIME_OFF_gc = (0x00<<1), /* SDA hold time off */ - SDA_HOLD_TIME_50NS_gc = (0x01<<1), /* Typical 50ns hold time */ - SDA_HOLD_TIME_300NS_gc = (0x02<<1), /* Typical 300ns hold time */ - SDA_HOLD_TIME_400NS_gc = (0x03<<1), /* Typical 400ns hold time */ -} SDA_HOLD_TIME_t; - - -/* --------------------------------------------------------------------------- -USB - USB --------------------------------------------------------------------------- -*/ - -/* USB Endpoint */ -typedef struct USB_EP_struct -{ - register8_t STATUS; /* Endpoint Status */ - register8_t CTRL; /* Endpoint Control */ - _WORDREGISTER(CNT); /* USB Endpoint Counter */ - _WORDREGISTER(DATAPTR); /* Data Pointer */ - _WORDREGISTER(AUXDATA); /* Auxiliary Data */ -} USB_EP_t; - - -/* Universal Serial Bus */ -typedef struct USB_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t STATUS; /* Status Register */ - register8_t ADDR; /* Address Register */ - register8_t FIFOWP; /* FIFO Write Pointer Register */ - register8_t FIFORP; /* FIFO Read Pointer Register */ - _WORDREGISTER(EPPTR); /* Endpoint Configuration Table Pointer */ - register8_t INTCTRLA; /* Interrupt Control Register A */ - register8_t INTCTRLB; /* Interrupt Control Register B */ - register8_t INTFLAGSACLR; /* Clear Interrupt Flag Register A */ - register8_t INTFLAGSASET; /* Set Interrupt Flag Register A */ - register8_t INTFLAGSBCLR; /* Clear Interrupt Flag Register B */ - register8_t INTFLAGSBSET; /* Set Interrupt Flag Register B */ - register8_t reserved_0x0E; - register8_t reserved_0x0F; - register8_t reserved_0x10; - register8_t reserved_0x11; - register8_t reserved_0x12; - register8_t reserved_0x13; - register8_t reserved_0x14; - register8_t reserved_0x15; - register8_t reserved_0x16; - register8_t reserved_0x17; - register8_t reserved_0x18; - register8_t reserved_0x19; - register8_t reserved_0x1A; - register8_t reserved_0x1B; - register8_t reserved_0x1C; - register8_t reserved_0x1D; - register8_t reserved_0x1E; - register8_t reserved_0x1F; - register8_t reserved_0x20; - register8_t reserved_0x21; - register8_t reserved_0x22; - register8_t reserved_0x23; - register8_t reserved_0x24; - register8_t reserved_0x25; - register8_t reserved_0x26; - register8_t reserved_0x27; - register8_t reserved_0x28; - register8_t reserved_0x29; - register8_t reserved_0x2A; - register8_t reserved_0x2B; - register8_t reserved_0x2C; - register8_t reserved_0x2D; - register8_t reserved_0x2E; - register8_t reserved_0x2F; - register8_t reserved_0x30; - register8_t reserved_0x31; - register8_t reserved_0x32; - register8_t reserved_0x33; - register8_t reserved_0x34; - register8_t reserved_0x35; - register8_t reserved_0x36; - register8_t reserved_0x37; - register8_t reserved_0x38; - register8_t reserved_0x39; - register8_t CAL0; /* Calibration Byte 0 */ - register8_t CAL1; /* Calibration Byte 1 */ -} USB_t; - - -/* USB Endpoint Table */ -typedef struct USB_EP_TABLE_struct -{ - USB_EP_t EP0OUT; /* Endpoint 0 */ - USB_EP_t EP0IN; /* Endpoint 0 */ - USB_EP_t EP1OUT; /* Endpoint 1 */ - USB_EP_t EP1IN; /* Endpoint 1 */ - USB_EP_t EP2OUT; /* Endpoint 2 */ - USB_EP_t EP2IN; /* Endpoint 2 */ - USB_EP_t EP3OUT; /* Endpoint 3 */ - USB_EP_t EP3IN; /* Endpoint 3 */ - USB_EP_t EP4OUT; /* Endpoint 4 */ - USB_EP_t EP4IN; /* Endpoint 4 */ - USB_EP_t EP5OUT; /* Endpoint 5 */ - USB_EP_t EP5IN; /* Endpoint 5 */ - USB_EP_t EP6OUT; /* Endpoint 6 */ - USB_EP_t EP6IN; /* Endpoint 6 */ - USB_EP_t EP7OUT; /* Endpoint 7 */ - USB_EP_t EP7IN; /* Endpoint 7 */ - USB_EP_t EP8OUT; /* Endpoint 8 */ - USB_EP_t EP8IN; /* Endpoint 8 */ - USB_EP_t EP9OUT; /* Endpoint 9 */ - USB_EP_t EP9IN; /* Endpoint 9 */ - USB_EP_t EP10OUT; /* Endpoint 10 */ - USB_EP_t EP10IN; /* Endpoint 10 */ - USB_EP_t EP11OUT; /* Endpoint 11 */ - USB_EP_t EP11IN; /* Endpoint 11 */ - USB_EP_t EP12OUT; /* Endpoint 12 */ - USB_EP_t EP12IN; /* Endpoint 12 */ - USB_EP_t EP13OUT; /* Endpoint 13 */ - USB_EP_t EP13IN; /* Endpoint 13 */ - USB_EP_t EP14OUT; /* Endpoint 14 */ - USB_EP_t EP14IN; /* Endpoint 14 */ - USB_EP_t EP15OUT; /* Endpoint 15 */ - USB_EP_t EP15IN; /* Endpoint 15 */ - register8_t reserved_0x100; - register8_t reserved_0x101; - register8_t reserved_0x102; - register8_t reserved_0x103; - register8_t reserved_0x104; - register8_t reserved_0x105; - register8_t reserved_0x106; - register8_t reserved_0x107; - register8_t reserved_0x108; - register8_t reserved_0x109; - register8_t reserved_0x10A; - register8_t reserved_0x10B; - register8_t reserved_0x10C; - register8_t reserved_0x10D; - register8_t reserved_0x10E; - register8_t reserved_0x10F; - register8_t FRAMENUML; /* Frame Number Low Byte */ - register8_t FRAMENUMH; /* Frame Number High Byte */ -} USB_EP_TABLE_t; - -/* Interrupt level */ -typedef enum USB_INTLVL_enum -{ - USB_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ - USB_INTLVL_LO_gc = (0x01<<0), /* Low level */ - USB_INTLVL_MED_gc = (0x02<<0), /* Medium level */ - USB_INTLVL_HI_gc = (0x03<<0), /* High level */ -} USB_INTLVL_t; - -/* USB Endpoint Type */ -typedef enum USB_EP_TYPE_enum -{ - USB_EP_TYPE_DISABLE_gc = (0x00<<6), /* Endpoint Disabled */ - USB_EP_TYPE_CONTROL_gc = (0x01<<6), /* Control */ - USB_EP_TYPE_BULK_gc = (0x02<<6), /* Bulk/Interrupt */ - USB_EP_TYPE_ISOCHRONOUS_gc = (0x03<<6), /* Isochronous */ -} USB_EP_TYPE_t; - -/* USB Endpoint Buffersize */ -typedef enum USB_EP_BUFSIZE_enum -{ - USB_EP_BUFSIZE_8_gc = (0x00<<0), /* 8 bytes buffer size */ - USB_EP_BUFSIZE_16_gc = (0x01<<0), /* 16 bytes buffer size */ - USB_EP_BUFSIZE_32_gc = (0x02<<0), /* 32 bytes buffer size */ - USB_EP_BUFSIZE_64_gc = (0x03<<0), /* 64 bytes buffer size */ - USB_EP_BUFSIZE_128_gc = (0x04<<0), /* 128 bytes buffer size */ - USB_EP_BUFSIZE_256_gc = (0x05<<0), /* 256 bytes buffer size */ - USB_EP_BUFSIZE_512_gc = (0x06<<0), /* 512 bytes buffer size */ - USB_EP_BUFSIZE_1023_gc = (0x07<<0), /* 1023 bytes buffer size */ -} USB_EP_BUFSIZE_t; - - -/* --------------------------------------------------------------------------- -PORT - I/O Port Configuration --------------------------------------------------------------------------- -*/ - -/* I/O Ports */ -typedef struct PORT_struct -{ - register8_t DIR; /* I/O Port Data Direction */ - register8_t DIRSET; /* I/O Port Data Direction Set */ - register8_t DIRCLR; /* I/O Port Data Direction Clear */ - register8_t DIRTGL; /* I/O Port Data Direction Toggle */ - register8_t OUT; /* I/O Port Output */ - register8_t OUTSET; /* I/O Port Output Set */ - register8_t OUTCLR; /* I/O Port Output Clear */ - register8_t OUTTGL; /* I/O Port Output Toggle */ - register8_t IN; /* I/O port Input */ - register8_t INTCTRL; /* Interrupt Control Register */ - register8_t INT0MASK; /* Port Interrupt 0 Mask */ - register8_t INT1MASK; /* Port Interrupt 1 Mask */ - register8_t INTFLAGS; /* Interrupt Flag Register */ - register8_t reserved_0x0D; - register8_t REMAP; /* I/O Port Pin Remap Register */ - register8_t reserved_0x0F; - register8_t PIN0CTRL; /* Pin 0 Control Register */ - register8_t PIN1CTRL; /* Pin 1 Control Register */ - register8_t PIN2CTRL; /* Pin 2 Control Register */ - register8_t PIN3CTRL; /* Pin 3 Control Register */ - register8_t PIN4CTRL; /* Pin 4 Control Register */ - register8_t PIN5CTRL; /* Pin 5 Control Register */ - register8_t PIN6CTRL; /* Pin 6 Control Register */ - register8_t PIN7CTRL; /* Pin 7 Control Register */ -} PORT_t; - -/* Port Interrupt 0 Level */ -typedef enum PORT_INT0LVL_enum -{ - PORT_INT0LVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - PORT_INT0LVL_LO_gc = (0x01<<0), /* Low Level */ - PORT_INT0LVL_MED_gc = (0x02<<0), /* Medium Level */ - PORT_INT0LVL_HI_gc = (0x03<<0), /* High Level */ -} PORT_INT0LVL_t; - -/* Port Interrupt 1 Level */ -typedef enum PORT_INT1LVL_enum -{ - PORT_INT1LVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ - PORT_INT1LVL_LO_gc = (0x01<<2), /* Low Level */ - PORT_INT1LVL_MED_gc = (0x02<<2), /* Medium Level */ - PORT_INT1LVL_HI_gc = (0x03<<2), /* High Level */ -} PORT_INT1LVL_t; - -/* Output/Pull Configuration */ -typedef enum PORT_OPC_enum -{ - PORT_OPC_TOTEM_gc = (0x00<<3), /* Totempole */ - PORT_OPC_BUSKEEPER_gc = (0x01<<3), /* Totempole w/ Bus keeper on Input and Output */ - PORT_OPC_PULLDOWN_gc = (0x02<<3), /* Totempole w/ Pull-down on Input */ - PORT_OPC_PULLUP_gc = (0x03<<3), /* Totempole w/ Pull-up on Input */ - PORT_OPC_WIREDOR_gc = (0x04<<3), /* Wired OR */ - PORT_OPC_WIREDAND_gc = (0x05<<3), /* Wired AND */ - PORT_OPC_WIREDORPULL_gc = (0x06<<3), /* Wired OR w/ Pull-down */ - PORT_OPC_WIREDANDPULL_gc = (0x07<<3), /* Wired AND w/ Pull-up */ -} PORT_OPC_t; - -/* Input/Sense Configuration */ -typedef enum PORT_ISC_enum -{ - PORT_ISC_BOTHEDGES_gc = (0x00<<0), /* Sense Both Edges */ - PORT_ISC_RISING_gc = (0x01<<0), /* Sense Rising Edge */ - PORT_ISC_FALLING_gc = (0x02<<0), /* Sense Falling Edge */ - PORT_ISC_LEVEL_gc = (0x03<<0), /* Sense Level (Transparent For Events) */ - PORT_ISC_INPUT_DISABLE_gc = (0x07<<0), /* Disable Digital Input Buffer */ -} PORT_ISC_t; - - -/* --------------------------------------------------------------------------- -TC - 16-bit Timer/Counter With PWM --------------------------------------------------------------------------- -*/ - -/* 16-bit Timer/Counter 0 */ -typedef struct TC0_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t CTRLC; /* Control register C */ - register8_t CTRLD; /* Control Register D */ - register8_t CTRLE; /* Control Register E */ - register8_t reserved_0x05; - register8_t INTCTRLA; /* Interrupt Control Register A */ - register8_t INTCTRLB; /* Interrupt Control Register B */ - register8_t CTRLFCLR; /* Control Register F Clear */ - register8_t CTRLFSET; /* Control Register F Set */ - register8_t CTRLGCLR; /* Control Register G Clear */ - register8_t CTRLGSET; /* Control Register G Set */ - register8_t INTFLAGS; /* Interrupt Flag Register */ - register8_t reserved_0x0D; - register8_t reserved_0x0E; - register8_t TEMP; /* Temporary Register For 16-bit Access */ - register8_t reserved_0x10; - register8_t reserved_0x11; - register8_t reserved_0x12; - register8_t reserved_0x13; - register8_t reserved_0x14; - register8_t reserved_0x15; - register8_t reserved_0x16; - register8_t reserved_0x17; - register8_t reserved_0x18; - register8_t reserved_0x19; - register8_t reserved_0x1A; - register8_t reserved_0x1B; - register8_t reserved_0x1C; - register8_t reserved_0x1D; - register8_t reserved_0x1E; - register8_t reserved_0x1F; - _WORDREGISTER(CNT); /* Count */ - register8_t reserved_0x22; - register8_t reserved_0x23; - register8_t reserved_0x24; - register8_t reserved_0x25; - _WORDREGISTER(PER); /* Period */ - _WORDREGISTER(CCA); /* Compare or Capture A */ - _WORDREGISTER(CCB); /* Compare or Capture B */ - _WORDREGISTER(CCC); /* Compare or Capture C */ - _WORDREGISTER(CCD); /* Compare or Capture D */ - register8_t reserved_0x30; - register8_t reserved_0x31; - register8_t reserved_0x32; - register8_t reserved_0x33; - register8_t reserved_0x34; - register8_t reserved_0x35; - _WORDREGISTER(PERBUF); /* Period Buffer */ - _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ - _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ - _WORDREGISTER(CCCBUF); /* Compare Or Capture C Buffer */ - _WORDREGISTER(CCDBUF); /* Compare Or Capture D Buffer */ -} TC0_t; - - -/* 16-bit Timer/Counter 1 */ -typedef struct TC1_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t CTRLC; /* Control register C */ - register8_t CTRLD; /* Control Register D */ - register8_t CTRLE; /* Control Register E */ - register8_t reserved_0x05; - register8_t INTCTRLA; /* Interrupt Control Register A */ - register8_t INTCTRLB; /* Interrupt Control Register B */ - register8_t CTRLFCLR; /* Control Register F Clear */ - register8_t CTRLFSET; /* Control Register F Set */ - register8_t CTRLGCLR; /* Control Register G Clear */ - register8_t CTRLGSET; /* Control Register G Set */ - register8_t INTFLAGS; /* Interrupt Flag Register */ - register8_t reserved_0x0D; - register8_t reserved_0x0E; - register8_t TEMP; /* Temporary Register For 16-bit Access */ - register8_t reserved_0x10; - register8_t reserved_0x11; - register8_t reserved_0x12; - register8_t reserved_0x13; - register8_t reserved_0x14; - register8_t reserved_0x15; - register8_t reserved_0x16; - register8_t reserved_0x17; - register8_t reserved_0x18; - register8_t reserved_0x19; - register8_t reserved_0x1A; - register8_t reserved_0x1B; - register8_t reserved_0x1C; - register8_t reserved_0x1D; - register8_t reserved_0x1E; - register8_t reserved_0x1F; - _WORDREGISTER(CNT); /* Count */ - register8_t reserved_0x22; - register8_t reserved_0x23; - register8_t reserved_0x24; - register8_t reserved_0x25; - _WORDREGISTER(PER); /* Period */ - _WORDREGISTER(CCA); /* Compare or Capture A */ - _WORDREGISTER(CCB); /* Compare or Capture B */ - register8_t reserved_0x2C; - register8_t reserved_0x2D; - register8_t reserved_0x2E; - register8_t reserved_0x2F; - register8_t reserved_0x30; - register8_t reserved_0x31; - register8_t reserved_0x32; - register8_t reserved_0x33; - register8_t reserved_0x34; - register8_t reserved_0x35; - _WORDREGISTER(PERBUF); /* Period Buffer */ - _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ - _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ -} TC1_t; - -/* Clock Selection */ -typedef enum TC_CLKSEL_enum -{ - TC_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */ - TC_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */ - TC_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */ - TC_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */ - TC_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */ - TC_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */ - TC_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */ - TC_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */ - TC_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */ - TC_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */ - TC_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */ - TC_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */ - TC_CLKSEL_EVCH4_gc = (0x0C<<0), /* Event Channel 4 */ - TC_CLKSEL_EVCH5_gc = (0x0D<<0), /* Event Channel 5 */ - TC_CLKSEL_EVCH6_gc = (0x0E<<0), /* Event Channel 6 */ - TC_CLKSEL_EVCH7_gc = (0x0F<<0), /* Event Channel 7 */ -} TC_CLKSEL_t; - -/* Waveform Generation Mode */ -typedef enum TC_WGMODE_enum -{ - TC_WGMODE_NORMAL_gc = (0x00<<0), /* Normal Mode */ - TC_WGMODE_FRQ_gc = (0x01<<0), /* Frequency Generation Mode */ - TC_WGMODE_SINGLESLOPE_gc = (0x03<<0), /* Single Slope */ - TC_WGMODE_SS_gc = (0x03<<0), /* Single Slope */ - TC_WGMODE_DSTOP_gc = (0x05<<0), /* Dual Slope, Update on TOP */ - TC_WGMODE_DS_T_gc = (0x05<<0), /* Dual Slope, Update on TOP */ - TC_WGMODE_DSBOTH_gc = (0x06<<0), /* Dual Slope, Update on both TOP and BOTTOM */ - TC_WGMODE_DS_TB_gc = (0x06<<0), /* Dual Slope, Update on both TOP and BOTTOM */ - TC_WGMODE_DSBOTTOM_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */ - TC_WGMODE_DS_B_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */ -} TC_WGMODE_t; - -/* Byte Mode */ -typedef enum TC_BYTEM_enum -{ - TC_BYTEM_NORMAL_gc = (0x00<<0), /* 16-bit mode */ - TC_BYTEM_BYTEMODE_gc = (0x01<<0), /* Timer/Counter operating in byte mode only */ - TC_BYTEM_SPLITMODE_gc = (0x02<<0), /* Timer/Counter split into two 8-bit Counters (TC2) */ -} TC_BYTEM_t; - -/* Event Action */ -typedef enum TC_EVACT_enum -{ - TC_EVACT_OFF_gc = (0x00<<5), /* No Event Action */ - TC_EVACT_CAPT_gc = (0x01<<5), /* Input Capture */ - TC_EVACT_UPDOWN_gc = (0x02<<5), /* Externally Controlled Up/Down Count */ - TC_EVACT_QDEC_gc = (0x03<<5), /* Quadrature Decode */ - TC_EVACT_RESTART_gc = (0x04<<5), /* Restart */ - TC_EVACT_FRQ_gc = (0x05<<5), /* Frequency Capture */ - TC_EVACT_PW_gc = (0x06<<5), /* Pulse-width Capture */ -} TC_EVACT_t; - -/* Event Selection */ -typedef enum TC_EVSEL_enum -{ - TC_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ - TC_EVSEL_CH0_gc = (0x08<<0), /* Event Channel 0 */ - TC_EVSEL_CH1_gc = (0x09<<0), /* Event Channel 1 */ - TC_EVSEL_CH2_gc = (0x0A<<0), /* Event Channel 2 */ - TC_EVSEL_CH3_gc = (0x0B<<0), /* Event Channel 3 */ - TC_EVSEL_CH4_gc = (0x0C<<0), /* Event Channel 4 */ - TC_EVSEL_CH5_gc = (0x0D<<0), /* Event Channel 5 */ - TC_EVSEL_CH6_gc = (0x0E<<0), /* Event Channel 6 */ - TC_EVSEL_CH7_gc = (0x0F<<0), /* Event Channel 7 */ -} TC_EVSEL_t; - -/* Error Interrupt Level */ -typedef enum TC_ERRINTLVL_enum -{ - TC_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ - TC_ERRINTLVL_LO_gc = (0x01<<2), /* Low Level */ - TC_ERRINTLVL_MED_gc = (0x02<<2), /* Medium Level */ - TC_ERRINTLVL_HI_gc = (0x03<<2), /* High Level */ -} TC_ERRINTLVL_t; - -/* Overflow Interrupt Level */ -typedef enum TC_OVFINTLVL_enum -{ - TC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - TC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ - TC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ - TC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ -} TC_OVFINTLVL_t; - -/* Compare or Capture D Interrupt Level */ -typedef enum TC_CCDINTLVL_enum -{ - TC_CCDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ - TC_CCDINTLVL_LO_gc = (0x01<<6), /* Low Level */ - TC_CCDINTLVL_MED_gc = (0x02<<6), /* Medium Level */ - TC_CCDINTLVL_HI_gc = (0x03<<6), /* High Level */ -} TC_CCDINTLVL_t; - -/* Compare or Capture C Interrupt Level */ -typedef enum TC_CCCINTLVL_enum -{ - TC_CCCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ - TC_CCCINTLVL_LO_gc = (0x01<<4), /* Low Level */ - TC_CCCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ - TC_CCCINTLVL_HI_gc = (0x03<<4), /* High Level */ -} TC_CCCINTLVL_t; - -/* Compare or Capture B Interrupt Level */ -typedef enum TC_CCBINTLVL_enum -{ - TC_CCBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ - TC_CCBINTLVL_LO_gc = (0x01<<2), /* Low Level */ - TC_CCBINTLVL_MED_gc = (0x02<<2), /* Medium Level */ - TC_CCBINTLVL_HI_gc = (0x03<<2), /* High Level */ -} TC_CCBINTLVL_t; - -/* Compare or Capture A Interrupt Level */ -typedef enum TC_CCAINTLVL_enum -{ - TC_CCAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - TC_CCAINTLVL_LO_gc = (0x01<<0), /* Low Level */ - TC_CCAINTLVL_MED_gc = (0x02<<0), /* Medium Level */ - TC_CCAINTLVL_HI_gc = (0x03<<0), /* High Level */ -} TC_CCAINTLVL_t; - -/* Timer/Counter Command */ -typedef enum TC_CMD_enum -{ - TC_CMD_NONE_gc = (0x00<<2), /* No Command */ - TC_CMD_UPDATE_gc = (0x01<<2), /* Force Update */ - TC_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ - TC_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ -} TC_CMD_t; - - -/* --------------------------------------------------------------------------- -TC2 - 16-bit Timer/Counter type 2 --------------------------------------------------------------------------- -*/ - -/* 16-bit Timer/Counter type 2 */ -typedef struct TC2_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t CTRLC; /* Control register C */ - register8_t reserved_0x03; - register8_t CTRLE; /* Control Register E */ - register8_t reserved_0x05; - register8_t INTCTRLA; /* Interrupt Control Register A */ - register8_t INTCTRLB; /* Interrupt Control Register B */ - register8_t reserved_0x08; - register8_t CTRLF; /* Control Register F */ - register8_t reserved_0x0A; - register8_t reserved_0x0B; - register8_t INTFLAGS; /* Interrupt Flag Register */ - register8_t reserved_0x0D; - register8_t reserved_0x0E; - register8_t reserved_0x0F; - register8_t reserved_0x10; - register8_t reserved_0x11; - register8_t reserved_0x12; - register8_t reserved_0x13; - register8_t reserved_0x14; - register8_t reserved_0x15; - register8_t reserved_0x16; - register8_t reserved_0x17; - register8_t reserved_0x18; - register8_t reserved_0x19; - register8_t reserved_0x1A; - register8_t reserved_0x1B; - register8_t reserved_0x1C; - register8_t reserved_0x1D; - register8_t reserved_0x1E; - register8_t reserved_0x1F; - register8_t LCNT; /* Low Byte Count */ - register8_t HCNT; /* High Byte Count */ - register8_t reserved_0x22; - register8_t reserved_0x23; - register8_t reserved_0x24; - register8_t reserved_0x25; - register8_t LPER; /* Low Byte Period */ - register8_t HPER; /* High Byte Period */ - register8_t LCMPA; /* Low Byte Compare A */ - register8_t HCMPA; /* High Byte Compare A */ - register8_t LCMPB; /* Low Byte Compare B */ - register8_t HCMPB; /* High Byte Compare B */ - register8_t LCMPC; /* Low Byte Compare C */ - register8_t HCMPC; /* High Byte Compare C */ - register8_t LCMPD; /* Low Byte Compare D */ - register8_t HCMPD; /* High Byte Compare D */ -} TC2_t; - -/* Clock Selection */ -typedef enum TC2_CLKSEL_enum -{ - TC2_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */ - TC2_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */ - TC2_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */ - TC2_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */ - TC2_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */ - TC2_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */ - TC2_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */ - TC2_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */ - TC2_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */ - TC2_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */ - TC2_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */ - TC2_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */ - TC2_CLKSEL_EVCH4_gc = (0x0C<<0), /* Event Channel 4 */ - TC2_CLKSEL_EVCH5_gc = (0x0D<<0), /* Event Channel 5 */ - TC2_CLKSEL_EVCH6_gc = (0x0E<<0), /* Event Channel 6 */ - TC2_CLKSEL_EVCH7_gc = (0x0F<<0), /* Event Channel 7 */ -} TC2_CLKSEL_t; - -/* Byte Mode */ -typedef enum TC2_BYTEM_enum -{ - TC2_BYTEM_NORMAL_gc = (0x00<<0), /* 16-bit mode */ - TC2_BYTEM_BYTEMODE_gc = (0x01<<0), /* Timer/Counter operating in byte mode only (TC2) */ - TC2_BYTEM_SPLITMODE_gc = (0x02<<0), /* Timer/Counter split into two 8-bit Counters */ -} TC2_BYTEM_t; - -/* High Byte Underflow Interrupt Level */ -typedef enum TC2_HUNFINTLVL_enum -{ - TC2_HUNFINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ - TC2_HUNFINTLVL_LO_gc = (0x01<<2), /* Low Level */ - TC2_HUNFINTLVL_MED_gc = (0x02<<2), /* Medium Level */ - TC2_HUNFINTLVL_HI_gc = (0x03<<2), /* High Level */ -} TC2_HUNFINTLVL_t; - -/* Low Byte Underflow Interrupt Level */ -typedef enum TC2_LUNFINTLVL_enum -{ - TC2_LUNFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - TC2_LUNFINTLVL_LO_gc = (0x01<<0), /* Low Level */ - TC2_LUNFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ - TC2_LUNFINTLVL_HI_gc = (0x03<<0), /* High Level */ -} TC2_LUNFINTLVL_t; - -/* Low Byte Compare D Interrupt Level */ -typedef enum TC2_LCMPDINTLVL_enum -{ - TC2_LCMPDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ - TC2_LCMPDINTLVL_LO_gc = (0x01<<6), /* Low Level */ - TC2_LCMPDINTLVL_MED_gc = (0x02<<6), /* Medium Level */ - TC2_LCMPDINTLVL_HI_gc = (0x03<<6), /* High Level */ -} TC2_LCMPDINTLVL_t; - -/* Low Byte Compare C Interrupt Level */ -typedef enum TC2_LCMPCINTLVL_enum -{ - TC2_LCMPCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ - TC2_LCMPCINTLVL_LO_gc = (0x01<<4), /* Low Level */ - TC2_LCMPCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ - TC2_LCMPCINTLVL_HI_gc = (0x03<<4), /* High Level */ -} TC2_LCMPCINTLVL_t; - -/* Low Byte Compare B Interrupt Level */ -typedef enum TC2_LCMPBINTLVL_enum -{ - TC2_LCMPBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ - TC2_LCMPBINTLVL_LO_gc = (0x01<<2), /* Low Level */ - TC2_LCMPBINTLVL_MED_gc = (0x02<<2), /* Medium Level */ - TC2_LCMPBINTLVL_HI_gc = (0x03<<2), /* High Level */ -} TC2_LCMPBINTLVL_t; - -/* Low Byte Compare A Interrupt Level */ -typedef enum TC2_LCMPAINTLVL_enum -{ - TC2_LCMPAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - TC2_LCMPAINTLVL_LO_gc = (0x01<<0), /* Low Level */ - TC2_LCMPAINTLVL_MED_gc = (0x02<<0), /* Medium Level */ - TC2_LCMPAINTLVL_HI_gc = (0x03<<0), /* High Level */ -} TC2_LCMPAINTLVL_t; - -/* Timer/Counter Command */ -typedef enum TC2_CMD_enum -{ - TC2_CMD_NONE_gc = (0x00<<2), /* No Command */ - TC2_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ - TC2_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ -} TC2_CMD_t; - -/* Timer/Counter Command */ -typedef enum TC2_CMDEN_enum -{ - TC2_CMDEN_LOW_gc = (0x01<<0), /* Low Byte Timer/Counter */ - TC2_CMDEN_HIGH_gc = (0x02<<0), /* High Byte Timer/Counter */ - TC2_CMDEN_BOTH_gc = (0x03<<0), /* Both Low Byte and High Byte Timer/Counters */ -} TC2_CMDEN_t; - - -/* --------------------------------------------------------------------------- -AWEX - Timer/Counter Advanced Waveform Extension --------------------------------------------------------------------------- -*/ - -/* Advanced Waveform Extension */ -typedef struct AWEX_struct -{ - register8_t CTRL; /* Control Register */ - register8_t reserved_0x01; - register8_t FDEMASK; /* Fault Detection Event Mask */ - register8_t FDCTRL; /* Fault Detection Control Register */ - register8_t STATUS; /* Status Register */ - register8_t STATUSSET; /* Status Set Register */ - register8_t DTBOTH; /* Dead Time Both Sides */ - register8_t DTBOTHBUF; /* Dead Time Both Sides Buffer */ - register8_t DTLS; /* Dead Time Low Side */ - register8_t DTHS; /* Dead Time High Side */ - register8_t DTLSBUF; /* Dead Time Low Side Buffer */ - register8_t DTHSBUF; /* Dead Time High Side Buffer */ - register8_t OUTOVEN; /* Output Override Enable */ -} AWEX_t; - -/* Fault Detect Action */ -typedef enum AWEX_FDACT_enum -{ - AWEX_FDACT_NONE_gc = (0x00<<0), /* No Fault Protection */ - AWEX_FDACT_CLEAROE_gc = (0x01<<0), /* Clear Output Enable Bits */ - AWEX_FDACT_CLEARDIR_gc = (0x03<<0), /* Clear I/O Port Direction Bits */ -} AWEX_FDACT_t; - - -/* --------------------------------------------------------------------------- -HIRES - Timer/Counter High-Resolution Extension --------------------------------------------------------------------------- -*/ - -/* High-Resolution Extension */ -typedef struct HIRES_struct -{ - register8_t CTRLA; /* Control Register */ -} HIRES_t; - -/* High Resolution Enable */ -typedef enum HIRES_HREN_enum -{ - HIRES_HREN_NONE_gc = (0x00<<0), /* No Fault Protection */ - HIRES_HREN_TC0_gc = (0x01<<0), /* Enable High Resolution on Timer/Counter 0 */ - HIRES_HREN_TC1_gc = (0x02<<0), /* Enable High Resolution on Timer/Counter 1 */ - HIRES_HREN_BOTH_gc = (0x03<<0), /* Enable High Resolution both Timer/Counters */ -} HIRES_HREN_t; - - -/* --------------------------------------------------------------------------- -USART - Universal Asynchronous Receiver-Transmitter --------------------------------------------------------------------------- -*/ - -/* Universal Synchronous/Asynchronous Receiver/Transmitter */ -typedef struct USART_struct -{ - register8_t DATA; /* Data Register */ - register8_t STATUS; /* Status Register */ - register8_t reserved_0x02; - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t CTRLC; /* Control Register C */ - register8_t BAUDCTRLA; /* Baud Rate Control Register A */ - register8_t BAUDCTRLB; /* Baud Rate Control Register B */ -} USART_t; - -/* Receive Complete Interrupt level */ -typedef enum USART_RXCINTLVL_enum -{ - USART_RXCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ - USART_RXCINTLVL_LO_gc = (0x01<<4), /* Low Level */ - USART_RXCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ - USART_RXCINTLVL_HI_gc = (0x03<<4), /* High Level */ -} USART_RXCINTLVL_t; - -/* Transmit Complete Interrupt level */ -typedef enum USART_TXCINTLVL_enum -{ - USART_TXCINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ - USART_TXCINTLVL_LO_gc = (0x01<<2), /* Low Level */ - USART_TXCINTLVL_MED_gc = (0x02<<2), /* Medium Level */ - USART_TXCINTLVL_HI_gc = (0x03<<2), /* High Level */ -} USART_TXCINTLVL_t; - -/* Data Register Empty Interrupt level */ -typedef enum USART_DREINTLVL_enum -{ - USART_DREINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - USART_DREINTLVL_LO_gc = (0x01<<0), /* Low Level */ - USART_DREINTLVL_MED_gc = (0x02<<0), /* Medium Level */ - USART_DREINTLVL_HI_gc = (0x03<<0), /* High Level */ -} USART_DREINTLVL_t; - -/* Character Size */ -typedef enum USART_CHSIZE_enum -{ - USART_CHSIZE_5BIT_gc = (0x00<<0), /* Character size: 5 bit */ - USART_CHSIZE_6BIT_gc = (0x01<<0), /* Character size: 6 bit */ - USART_CHSIZE_7BIT_gc = (0x02<<0), /* Character size: 7 bit */ - USART_CHSIZE_8BIT_gc = (0x03<<0), /* Character size: 8 bit */ - USART_CHSIZE_9BIT_gc = (0x07<<0), /* Character size: 9 bit */ -} USART_CHSIZE_t; - -/* Communication Mode */ -typedef enum USART_CMODE_enum -{ - USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6), /* Asynchronous Mode */ - USART_CMODE_SYNCHRONOUS_gc = (0x01<<6), /* Synchronous Mode */ - USART_CMODE_IRDA_gc = (0x02<<6), /* IrDA Mode */ - USART_CMODE_MSPI_gc = (0x03<<6), /* Master SPI Mode */ -} USART_CMODE_t; - -/* Parity Mode */ -typedef enum USART_PMODE_enum -{ - USART_PMODE_DISABLED_gc = (0x00<<4), /* No Parity */ - USART_PMODE_EVEN_gc = (0x02<<4), /* Even Parity */ - USART_PMODE_ODD_gc = (0x03<<4), /* Odd Parity */ -} USART_PMODE_t; - - -/* --------------------------------------------------------------------------- -SPI - Serial Peripheral Interface --------------------------------------------------------------------------- -*/ - -/* Serial Peripheral Interface */ -typedef struct SPI_struct -{ - register8_t CTRL; /* Control Register */ - register8_t INTCTRL; /* Interrupt Control Register */ - register8_t STATUS; /* Status Register */ - register8_t DATA; /* Data Register */ -} SPI_t; - -/* SPI Mode */ -typedef enum SPI_MODE_enum -{ - SPI_MODE_0_gc = (0x00<<2), /* SPI Mode 0 */ - SPI_MODE_1_gc = (0x01<<2), /* SPI Mode 1 */ - SPI_MODE_2_gc = (0x02<<2), /* SPI Mode 2 */ - SPI_MODE_3_gc = (0x03<<2), /* SPI Mode 3 */ -} SPI_MODE_t; - -/* Prescaler setting */ -typedef enum SPI_PRESCALER_enum -{ - SPI_PRESCALER_DIV4_gc = (0x00<<0), /* System Clock / 4 */ - SPI_PRESCALER_DIV16_gc = (0x01<<0), /* System Clock / 16 */ - SPI_PRESCALER_DIV64_gc = (0x02<<0), /* System Clock / 64 */ - SPI_PRESCALER_DIV128_gc = (0x03<<0), /* System Clock / 128 */ -} SPI_PRESCALER_t; - -/* Interrupt level */ -typedef enum SPI_INTLVL_enum -{ - SPI_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - SPI_INTLVL_LO_gc = (0x01<<0), /* Low Level */ - SPI_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ - SPI_INTLVL_HI_gc = (0x03<<0), /* High Level */ -} SPI_INTLVL_t; - - -/* --------------------------------------------------------------------------- -IRCOM - IR Communication Module --------------------------------------------------------------------------- -*/ - -/* IR Communication Module */ -typedef struct IRCOM_struct -{ - register8_t CTRL; /* Control Register */ - register8_t TXPLCTRL; /* IrDA Transmitter Pulse Length Control Register */ - register8_t RXPLCTRL; /* IrDA Receiver Pulse Length Control Register */ -} IRCOM_t; - -/* Event channel selection */ -typedef enum IRDA_EVSEL_enum -{ - IRDA_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ - IRDA_EVSEL_0_gc = (0x08<<0), /* Event Channel 0 */ - IRDA_EVSEL_1_gc = (0x09<<0), /* Event Channel 1 */ - IRDA_EVSEL_2_gc = (0x0A<<0), /* Event Channel 2 */ - IRDA_EVSEL_3_gc = (0x0B<<0), /* Event Channel 3 */ - IRDA_EVSEL_4_gc = (0x0C<<0), /* Event Channel 4 */ - IRDA_EVSEL_5_gc = (0x0D<<0), /* Event Channel 5 */ - IRDA_EVSEL_6_gc = (0x0E<<0), /* Event Channel 6 */ - IRDA_EVSEL_7_gc = (0x0F<<0), /* Event Channel 7 */ -} IRDA_EVSEL_t; - - -/* --------------------------------------------------------------------------- -FUSE - Fuses and Lockbits --------------------------------------------------------------------------- -*/ - -/* Fuses */ -typedef struct NVM_FUSES_struct -{ - register8_t FUSEBYTE0; /* JTAG User ID */ - register8_t FUSEBYTE1; /* Watchdog Configuration */ - register8_t FUSEBYTE2; /* Reset Configuration */ - register8_t reserved_0x03; - register8_t FUSEBYTE4; /* Start-up Configuration */ - register8_t FUSEBYTE5; /* EESAVE and BOD Level */ -} NVM_FUSES_t; - -/* Boot Loader Section Reset Vector */ -typedef enum BOOTRST_enum -{ - BOOTRST_BOOTLDR_gc = (0x00<<6), /* Boot Loader Reset */ - BOOTRST_APPLICATION_gc = (0x01<<6), /* Application Reset */ -} BOOTRST_t; - -/* Timer Oscillator pin location */ -typedef enum TOSCSEL_enum -{ - TOSCSEL_ALTERNATE_gc = (0x00<<5), /* TOSC1 / TOSC2 on separate pins */ - TOSCSEL_XTAL_gc = (0x01<<5), /* TOSC1 / TOSC2 shared with XTAL1 / XTAL2 */ -} TOSCSEL_t; - -/* BOD operation */ -typedef enum BOD_enum -{ - BOD_SAMPLED_gc = (0x01<<0), /* BOD enabled in sampled mode */ - BOD_CONTINUOUS_gc = (0x02<<0), /* BOD enabled continuously */ - BOD_DISABLED_gc = (0x03<<0), /* BOD Disabled */ -} BOD_t; - -/* BOD operation */ -typedef enum BODACT_enum -{ - BODACT_SAMPLED_gc = (0x01<<4), /* BOD enabled in sampled mode */ - BODACT_CONTINUOUS_gc = (0x02<<4), /* BOD enabled continuously */ - BODACT_DISABLED_gc = (0x03<<4), /* BOD Disabled */ -} BODACT_t; - -/* Watchdog (Window) Timeout Period */ -typedef enum WD_enum -{ - WD_8CLK_gc = (0x00<<4), /* 8 cycles (8ms @ 3.3V) */ - WD_16CLK_gc = (0x01<<4), /* 16 cycles (16ms @ 3.3V) */ - WD_32CLK_gc = (0x02<<4), /* 32 cycles (32ms @ 3.3V) */ - WD_64CLK_gc = (0x03<<4), /* 64 cycles (64ms @ 3.3V) */ - WD_128CLK_gc = (0x04<<4), /* 128 cycles (0.125s @ 3.3V) */ - WD_256CLK_gc = (0x05<<4), /* 256 cycles (0.25s @ 3.3V) */ - WD_512CLK_gc = (0x06<<4), /* 512 cycles (0.5s @ 3.3V) */ - WD_1KCLK_gc = (0x07<<4), /* 1K cycles (1s @ 3.3V) */ - WD_2KCLK_gc = (0x08<<4), /* 2K cycles (2s @ 3.3V) */ - WD_4KCLK_gc = (0x09<<4), /* 4K cycles (4s @ 3.3V) */ - WD_8KCLK_gc = (0x0A<<4), /* 8K cycles (8s @ 3.3V) */ -} WD_t; - -/* Watchdog (Window) Timeout Period */ -typedef enum WDP_enum -{ - WDP_8CLK_gc = (0x00<<0), /* 8 cycles (8ms @ 3.3V) */ - WDP_16CLK_gc = (0x01<<0), /* 16 cycles (16ms @ 3.3V) */ - WDP_32CLK_gc = (0x02<<0), /* 32 cycles (32ms @ 3.3V) */ - WDP_64CLK_gc = (0x03<<0), /* 64 cycles (64ms @ 3.3V) */ - WDP_128CLK_gc = (0x04<<0), /* 128 cycles (0.125s @ 3.3V) */ - WDP_256CLK_gc = (0x05<<0), /* 256 cycles (0.25s @ 3.3V) */ - WDP_512CLK_gc = (0x06<<0), /* 512 cycles (0.5s @ 3.3V) */ - WDP_1KCLK_gc = (0x07<<0), /* 1K cycles (1s @ 3.3V) */ - WDP_2KCLK_gc = (0x08<<0), /* 2K cycles (2s @ 3.3V) */ - WDP_4KCLK_gc = (0x09<<0), /* 4K cycles (4s @ 3.3V) */ - WDP_8KCLK_gc = (0x0A<<0), /* 8K cycles (8s @ 3.3V) */ -} WDP_t; - -/* Start-up Time */ -typedef enum SUT_enum -{ - SUT_0MS_gc = (0x03<<2), /* 0 ms */ - SUT_4MS_gc = (0x01<<2), /* 4 ms */ - SUT_64MS_gc = (0x00<<2), /* 64 ms */ -} SUT_t; - -/* Brownout Detection Voltage Level */ -typedef enum BODLVL_enum -{ - BODLVL_1V6_gc = (0x07<<0), /* 1.6 V */ - BODLVL_1V8_gc = (0x06<<0), /* 1.8 V */ - BODLVL_2V0_gc = (0x05<<0), /* 2.0 V */ - BODLVL_2V2_gc = (0x04<<0), /* 2.2 V */ - BODLVL_2V4_gc = (0x03<<0), /* 2.4 V */ - BODLVL_2V6_gc = (0x02<<0), /* 2.6 V */ - BODLVL_2V8_gc = (0x01<<0), /* 2.8 V */ - BODLVL_3V0_gc = (0x00<<0), /* 3.0 V */ -} BODLVL_t; - - -/* --------------------------------------------------------------------------- -LOCKBIT - Fuses and Lockbits --------------------------------------------------------------------------- -*/ - -/* Lock Bits */ -typedef struct NVM_LOCKBITS_struct -{ - register8_t LOCK_BITS; /* Lock Bits (Changed from LOCKBITS to avoid avr-libc collision) */ -} NVM_LOCKBITS_t; - -/* Boot lock bits - boot setcion */ -typedef enum FUSE_BLBB_enum -{ - FUSE_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ - FUSE_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ - FUSE_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ - FUSE_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ -} FUSE_BLBB_t; - -/* Boot lock bits - application section */ -typedef enum FUSE_BLBA_enum -{ - FUSE_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ - FUSE_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ - FUSE_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ - FUSE_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ -} FUSE_BLBA_t; - -/* Boot lock bits - application table section */ -typedef enum FUSE_BLBAT_enum -{ - FUSE_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ - FUSE_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ - FUSE_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ - FUSE_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ -} FUSE_BLBAT_t; - -/* Lock bits */ -typedef enum FUSE_LB_enum -{ - FUSE_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ - FUSE_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ - FUSE_LB_NOLOCK_gc = (0x03<<0), /* No locks */ -} FUSE_LB_t; - - -/* --------------------------------------------------------------------------- -SIGROW - Signature Row --------------------------------------------------------------------------- -*/ - -/* Production Signatures */ -typedef struct NVM_PROD_SIGNATURES_struct -{ - register8_t RCOSC2M; /* RCOSC 2 MHz Calibration Value B */ - register8_t RCOSC2MA; /* RCOSC 2 MHz Calibration Value A */ - register8_t RCOSC32K; /* RCOSC 32.768 kHz Calibration Value */ - register8_t RCOSC32M; /* RCOSC 32 MHz Calibration Value B */ - register8_t RCOSC32MA; /* RCOSC 32 MHz Calibration Value A */ - register8_t reserved_0x05; - register8_t reserved_0x06; - register8_t reserved_0x07; - register8_t LOTNUM0; /* Lot Number Byte 0, ASCII */ - register8_t LOTNUM1; /* Lot Number Byte 1, ASCII */ - register8_t LOTNUM2; /* Lot Number Byte 2, ASCII */ - register8_t LOTNUM3; /* Lot Number Byte 3, ASCII */ - register8_t LOTNUM4; /* Lot Number Byte 4, ASCII */ - register8_t LOTNUM5; /* Lot Number Byte 5, ASCII */ - register8_t reserved_0x0E; - register8_t reserved_0x0F; - register8_t WAFNUM; /* Wafer Number */ - register8_t reserved_0x11; - register8_t COORDX0; /* Wafer Coordinate X Byte 0 */ - register8_t COORDX1; /* Wafer Coordinate X Byte 1 */ - register8_t COORDY0; /* Wafer Coordinate Y Byte 0 */ - register8_t COORDY1; /* Wafer Coordinate Y Byte 1 */ - register8_t reserved_0x16; - register8_t reserved_0x17; - register8_t reserved_0x18; - register8_t reserved_0x19; - register8_t USBCAL0; /* USB Calibration Byte 0 */ - register8_t USBCAL1; /* USB Calibration Byte 1 */ - register8_t USBRCOSC; /* USB RCOSC Calibration Value B */ - register8_t USBRCOSCA; /* USB RCOSC Calibration Value A */ - register8_t reserved_0x1E; - register8_t reserved_0x1F; - register8_t ADCACAL0; /* ADCA Calibration Byte 0 */ - register8_t ADCACAL1; /* ADCA Calibration Byte 1 */ - register8_t reserved_0x22; - register8_t reserved_0x23; - register8_t ADCBCAL0; /* ADCB Calibration Byte 0 */ - register8_t ADCBCAL1; /* ADCB Calibration Byte 1 */ - register8_t reserved_0x26; - register8_t reserved_0x27; - register8_t reserved_0x28; - register8_t reserved_0x29; - register8_t reserved_0x2A; - register8_t reserved_0x2B; - register8_t reserved_0x2C; - register8_t reserved_0x2D; - register8_t TEMPSENSE0; /* Temperature Sensor Calibration Byte 0 */ - register8_t TEMPSENSE1; /* Temperature Sensor Calibration Byte 1 */ - register8_t DACA0OFFCAL; /* DACA0 Calibration Byte 0 */ - register8_t DACA0GAINCAL; /* DACA0 Calibration Byte 1 */ - register8_t DACB0OFFCAL; /* DACB0 Calibration Byte 0 */ - register8_t DACB0GAINCAL; /* DACB0 Calibration Byte 1 */ - register8_t DACA1OFFCAL; /* DACA1 Calibration Byte 0 */ - register8_t DACA1GAINCAL; /* DACA1 Calibration Byte 1 */ - register8_t DACB1OFFCAL; /* DACB1 Calibration Byte 0 */ - register8_t DACB1GAINCAL; /* DACB1 Calibration Byte 1 */ - register8_t reserved_0x38; - register8_t reserved_0x39; - register8_t reserved_0x3A; - register8_t reserved_0x3B; - register8_t reserved_0x3C; - register8_t reserved_0x3D; - register8_t reserved_0x3E; - register8_t reserved_0x3F; - register8_t reserved_0x40; - register8_t reserved_0x41; - register8_t reserved_0x42; - register8_t reserved_0x43; - register8_t reserved_0x44; - register8_t reserved_0x45; - register8_t reserved_0x46; - register8_t reserved_0x47; -} NVM_PROD_SIGNATURES_t; - -/* -========================================================================== -IO Module Instances. Mapped to memory. -========================================================================== -*/ - -#define VPORT0 (*(VPORT_t *) 0x0010) /* Virtual Port */ -#define VPORT1 (*(VPORT_t *) 0x0014) /* Virtual Port */ -#define VPORT2 (*(VPORT_t *) 0x0018) /* Virtual Port */ -#define VPORT3 (*(VPORT_t *) 0x001C) /* Virtual Port */ -#define OCD (*(OCD_t *) 0x002E) /* On-Chip Debug System */ -#define CLK (*(CLK_t *) 0x0040) /* Clock System */ -#define SLEEP (*(SLEEP_t *) 0x0048) /* Sleep Controller */ -#define OSC (*(OSC_t *) 0x0050) /* Oscillator */ -#define DFLLRC32M (*(DFLL_t *) 0x0060) /* DFLL */ -#define DFLLRC2M (*(DFLL_t *) 0x0068) /* DFLL */ -#define PR (*(PR_t *) 0x0070) /* Power Reduction */ -#define RST (*(RST_t *) 0x0078) /* Reset */ -#define WDT (*(WDT_t *) 0x0080) /* Watch-Dog Timer */ -#define MCU (*(MCU_t *) 0x0090) /* MCU Control */ -#define PMIC (*(PMIC_t *) 0x00A0) /* Programmable Multi-level Interrupt Controller */ -#define PORTCFG (*(PORTCFG_t *) 0x00B0) /* I/O port Configuration */ -#define AES (*(AES_t *) 0x00C0) /* AES Module */ -#define CRC (*(CRC_t *) 0x00D0) /* Cyclic Redundancy Checker */ -#define DMA (*(DMA_t *) 0x0100) /* DMA Controller */ -#define EVSYS (*(EVSYS_t *) 0x0180) /* Event System */ -#define NVM (*(NVM_t *) 0x01C0) /* Non-volatile Memory Controller */ -#define ADCA (*(ADC_t *) 0x0200) /* Analog-to-Digital Converter */ -#define ADCB (*(ADC_t *) 0x0240) /* Analog-to-Digital Converter */ -#define DACA (*(DAC_t *) 0x0300) /* Digital-to-Analog Converter */ -#define DACB (*(DAC_t *) 0x0320) /* Digital-to-Analog Converter */ -#define ACA (*(AC_t *) 0x0380) /* Analog Comparator */ -#define ACB (*(AC_t *) 0x0390) /* Analog Comparator */ -#define RTC (*(RTC_t *) 0x0400) /* Real-Time Counter */ -#define EBI (*(EBI_t *) 0x0440) /* External Bus Interface */ -#define TWIC (*(TWI_t *) 0x0480) /* Two-Wire Interface */ -#define TWID (*(TWI_t *) 0x0490) /* Two-Wire Interface */ -#define TWIE (*(TWI_t *) 0x04A0) /* Two-Wire Interface */ -#define TWIF (*(TWI_t *) 0x04B0) /* Two-Wire Interface */ -#define USB (*(USB_t *) 0x04C0) /* Universal Serial Bus */ -#define PORTA (*(PORT_t *) 0x0600) /* I/O Ports */ -#define PORTB (*(PORT_t *) 0x0620) /* I/O Ports */ -#define PORTC (*(PORT_t *) 0x0640) /* I/O Ports */ -#define PORTD (*(PORT_t *) 0x0660) /* I/O Ports */ -#define PORTE (*(PORT_t *) 0x0680) /* I/O Ports */ -#define PORTF (*(PORT_t *) 0x06A0) /* I/O Ports */ -#define PORTH (*(PORT_t *) 0x06E0) /* I/O Ports */ -#define PORTJ (*(PORT_t *) 0x0700) /* I/O Ports */ -#define PORTK (*(PORT_t *) 0x0720) /* I/O Ports */ -#define PORTQ (*(PORT_t *) 0x07C0) /* I/O Ports */ -#define PORTR (*(PORT_t *) 0x07E0) /* I/O Ports */ -#define TCC0 (*(TC0_t *) 0x0800) /* 16-bit Timer/Counter 0 */ -#define TCC2 (*(TC2_t *) 0x0800) /* 16-bit Timer/Counter type 2 */ -#define TCC1 (*(TC1_t *) 0x0840) /* 16-bit Timer/Counter 1 */ -#define AWEXC (*(AWEX_t *) 0x0880) /* Advanced Waveform Extension */ -#define HIRESC (*(HIRES_t *) 0x0890) /* High-Resolution Extension */ -#define USARTC0 (*(USART_t *) 0x08A0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ -#define USARTC1 (*(USART_t *) 0x08B0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ -#define SPIC (*(SPI_t *) 0x08C0) /* Serial Peripheral Interface */ -#define IRCOM (*(IRCOM_t *) 0x08F8) /* IR Communication Module */ -#define TCD0 (*(TC0_t *) 0x0900) /* 16-bit Timer/Counter 0 */ -#define TCD2 (*(TC2_t *) 0x0900) /* 16-bit Timer/Counter type 2 */ -#define TCD1 (*(TC1_t *) 0x0940) /* 16-bit Timer/Counter 1 */ -#define HIRESD (*(HIRES_t *) 0x0990) /* High-Resolution Extension */ -#define USARTD0 (*(USART_t *) 0x09A0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ -#define USARTD1 (*(USART_t *) 0x09B0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ -#define SPID (*(SPI_t *) 0x09C0) /* Serial Peripheral Interface */ -#define TCE0 (*(TC0_t *) 0x0A00) /* 16-bit Timer/Counter 0 */ -#define TCE2 (*(TC2_t *) 0x0A00) /* 16-bit Timer/Counter type 2 */ -#define TCE1 (*(TC1_t *) 0x0A40) /* 16-bit Timer/Counter 1 */ -#define AWEXE (*(AWEX_t *) 0x0A80) /* Advanced Waveform Extension */ -#define HIRESE (*(HIRES_t *) 0x0A90) /* High-Resolution Extension */ -#define USARTE0 (*(USART_t *) 0x0AA0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ -#define USARTE1 (*(USART_t *) 0x0AB0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ -#define SPIE (*(SPI_t *) 0x0AC0) /* Serial Peripheral Interface */ -#define TCF0 (*(TC0_t *) 0x0B00) /* 16-bit Timer/Counter 0 */ -#define TCF2 (*(TC2_t *) 0x0B00) /* 16-bit Timer/Counter type 2 */ -#define TCF1 (*(TC1_t *) 0x0B40) /* 16-bit Timer/Counter 1 */ -#define HIRESF (*(HIRES_t *) 0x0B90) /* High-Resolution Extension */ -#define USARTF0 (*(USART_t *) 0x0BA0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ -#define USARTF1 (*(USART_t *) 0x0BB0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ -#define SPIF (*(SPI_t *) 0x0BC0) /* Serial Peripheral Interface */ - - -#endif /* !defined (__ASSEMBLER__) */ - - -/* ========== Flattened fully qualified IO register names ========== */ - -/* GPIO - General Purpose IO Registers */ -#define GPIO_GPIOR0 _SFR_MEM8(0x0000) -#define GPIO_GPIOR1 _SFR_MEM8(0x0001) -#define GPIO_GPIOR2 _SFR_MEM8(0x0002) -#define GPIO_GPIOR3 _SFR_MEM8(0x0003) -#define GPIO_GPIOR4 _SFR_MEM8(0x0004) -#define GPIO_GPIOR5 _SFR_MEM8(0x0005) -#define GPIO_GPIOR6 _SFR_MEM8(0x0006) -#define GPIO_GPIOR7 _SFR_MEM8(0x0007) -#define GPIO_GPIOR8 _SFR_MEM8(0x0008) -#define GPIO_GPIOR9 _SFR_MEM8(0x0009) -#define GPIO_GPIORA _SFR_MEM8(0x000A) -#define GPIO_GPIORB _SFR_MEM8(0x000B) -#define GPIO_GPIORC _SFR_MEM8(0x000C) -#define GPIO_GPIORD _SFR_MEM8(0x000D) -#define GPIO_GPIORE _SFR_MEM8(0x000E) -#define GPIO_GPIORF _SFR_MEM8(0x000F) - -/* Deprecated */ -#define GPIO_GPIO0 _SFR_MEM8(0x0000) -#define GPIO_GPIO1 _SFR_MEM8(0x0001) -#define GPIO_GPIO2 _SFR_MEM8(0x0002) -#define GPIO_GPIO3 _SFR_MEM8(0x0003) -#define GPIO_GPIO4 _SFR_MEM8(0x0004) -#define GPIO_GPIO5 _SFR_MEM8(0x0005) -#define GPIO_GPIO6 _SFR_MEM8(0x0006) -#define GPIO_GPIO7 _SFR_MEM8(0x0007) -#define GPIO_GPIO8 _SFR_MEM8(0x0008) -#define GPIO_GPIO9 _SFR_MEM8(0x0009) -#define GPIO_GPIOA _SFR_MEM8(0x000A) -#define GPIO_GPIOB _SFR_MEM8(0x000B) -#define GPIO_GPIOC _SFR_MEM8(0x000C) -#define GPIO_GPIOD _SFR_MEM8(0x000D) -#define GPIO_GPIOE _SFR_MEM8(0x000E) -#define GPIO_GPIOF _SFR_MEM8(0x000F) - -/* NVM_FUSES - Fuses */ -#define FUSE_FUSEBYTE0 _SFR_MEM8(0x0000) -#define FUSE_FUSEBYTE1 _SFR_MEM8(0x0001) -#define FUSE_FUSEBYTE2 _SFR_MEM8(0x0002) -#define FUSE_FUSEBYTE4 _SFR_MEM8(0x0004) -#define FUSE_FUSEBYTE5 _SFR_MEM8(0x0005) - -/* NVM_LOCKBITS - Lock Bits */ -#define LOCKBIT_LOCKBITS _SFR_MEM8(0x0000) - -/* NVM_PROD_SIGNATURES - Production Signatures */ -#define PRODSIGNATURES_RCOSC2M _SFR_MEM8(0x0000) -#define PRODSIGNATURES_RCOSC2MA _SFR_MEM8(0x0001) -#define PRODSIGNATURES_RCOSC32K _SFR_MEM8(0x0002) -#define PRODSIGNATURES_RCOSC32M _SFR_MEM8(0x0003) -#define PRODSIGNATURES_RCOSC32MA _SFR_MEM8(0x0004) -#define PRODSIGNATURES_LOTNUM0 _SFR_MEM8(0x0008) -#define PRODSIGNATURES_LOTNUM1 _SFR_MEM8(0x0009) -#define PRODSIGNATURES_LOTNUM2 _SFR_MEM8(0x000A) -#define PRODSIGNATURES_LOTNUM3 _SFR_MEM8(0x000B) -#define PRODSIGNATURES_LOTNUM4 _SFR_MEM8(0x000C) -#define PRODSIGNATURES_LOTNUM5 _SFR_MEM8(0x000D) -#define PRODSIGNATURES_WAFNUM _SFR_MEM8(0x0010) -#define PRODSIGNATURES_COORDX0 _SFR_MEM8(0x0012) -#define PRODSIGNATURES_COORDX1 _SFR_MEM8(0x0013) -#define PRODSIGNATURES_COORDY0 _SFR_MEM8(0x0014) -#define PRODSIGNATURES_COORDY1 _SFR_MEM8(0x0015) -#define PRODSIGNATURES_USBCAL0 _SFR_MEM8(0x001A) -#define PRODSIGNATURES_USBCAL1 _SFR_MEM8(0x001B) -#define PRODSIGNATURES_USBRCOSC _SFR_MEM8(0x001C) -#define PRODSIGNATURES_USBRCOSCA _SFR_MEM8(0x001D) -#define PRODSIGNATURES_ADCACAL0 _SFR_MEM8(0x0020) -#define PRODSIGNATURES_ADCACAL1 _SFR_MEM8(0x0021) -#define PRODSIGNATURES_ADCBCAL0 _SFR_MEM8(0x0024) -#define PRODSIGNATURES_ADCBCAL1 _SFR_MEM8(0x0025) -#define PRODSIGNATURES_TEMPSENSE0 _SFR_MEM8(0x002E) -#define PRODSIGNATURES_TEMPSENSE1 _SFR_MEM8(0x002F) -#define PRODSIGNATURES_DACA0OFFCAL _SFR_MEM8(0x0030) -#define PRODSIGNATURES_DACA0GAINCAL _SFR_MEM8(0x0031) -#define PRODSIGNATURES_DACB0OFFCAL _SFR_MEM8(0x0032) -#define PRODSIGNATURES_DACB0GAINCAL _SFR_MEM8(0x0033) -#define PRODSIGNATURES_DACA1OFFCAL _SFR_MEM8(0x0034) -#define PRODSIGNATURES_DACA1GAINCAL _SFR_MEM8(0x0035) -#define PRODSIGNATURES_DACB1OFFCAL _SFR_MEM8(0x0036) -#define PRODSIGNATURES_DACB1GAINCAL _SFR_MEM8(0x0037) - -/* VPORT - Virtual Port */ -#define VPORT0_DIR _SFR_MEM8(0x0010) -#define VPORT0_OUT _SFR_MEM8(0x0011) -#define VPORT0_IN _SFR_MEM8(0x0012) -#define VPORT0_INTFLAGS _SFR_MEM8(0x0013) - -/* VPORT - Virtual Port */ -#define VPORT1_DIR _SFR_MEM8(0x0014) -#define VPORT1_OUT _SFR_MEM8(0x0015) -#define VPORT1_IN _SFR_MEM8(0x0016) -#define VPORT1_INTFLAGS _SFR_MEM8(0x0017) - -/* VPORT - Virtual Port */ -#define VPORT2_DIR _SFR_MEM8(0x0018) -#define VPORT2_OUT _SFR_MEM8(0x0019) -#define VPORT2_IN _SFR_MEM8(0x001A) -#define VPORT2_INTFLAGS _SFR_MEM8(0x001B) - -/* VPORT - Virtual Port */ -#define VPORT3_DIR _SFR_MEM8(0x001C) -#define VPORT3_OUT _SFR_MEM8(0x001D) -#define VPORT3_IN _SFR_MEM8(0x001E) -#define VPORT3_INTFLAGS _SFR_MEM8(0x001F) - -/* OCD - On-Chip Debug System */ -#define OCD_OCDR0 _SFR_MEM8(0x002E) -#define OCD_OCDR1 _SFR_MEM8(0x002F) - -/* CPU - CPU registers */ -#define CPU_CCP _SFR_MEM8(0x0034) -#define CPU_RAMPD _SFR_MEM8(0x0038) -#define CPU_RAMPX _SFR_MEM8(0x0039) -#define CPU_RAMPY _SFR_MEM8(0x003A) -#define CPU_RAMPZ _SFR_MEM8(0x003B) -#define CPU_EIND _SFR_MEM8(0x003C) -#define CPU_SPL _SFR_MEM8(0x003D) -#define CPU_SPH _SFR_MEM8(0x003E) -#define CPU_SREG _SFR_MEM8(0x003F) - -/* CLK - Clock System */ -#define CLK_CTRL _SFR_MEM8(0x0040) -#define CLK_PSCTRL _SFR_MEM8(0x0041) -#define CLK_LOCK _SFR_MEM8(0x0042) -#define CLK_RTCCTRL _SFR_MEM8(0x0043) -#define CLK_USBCTRL _SFR_MEM8(0x0044) - -/* SLEEP - Sleep Controller */ -#define SLEEP_CTRL _SFR_MEM8(0x0048) - -/* OSC - Oscillator */ -#define OSC_CTRL _SFR_MEM8(0x0050) -#define OSC_STATUS _SFR_MEM8(0x0051) -#define OSC_XOSCCTRL _SFR_MEM8(0x0052) -#define OSC_XOSCFAIL _SFR_MEM8(0x0053) -#define OSC_RC32KCAL _SFR_MEM8(0x0054) -#define OSC_PLLCTRL _SFR_MEM8(0x0055) -#define OSC_DFLLCTRL _SFR_MEM8(0x0056) - -/* DFLL - DFLL */ -#define DFLLRC32M_CTRL _SFR_MEM8(0x0060) -#define DFLLRC32M_CALA _SFR_MEM8(0x0062) -#define DFLLRC32M_CALB _SFR_MEM8(0x0063) -#define DFLLRC32M_COMP0 _SFR_MEM8(0x0064) -#define DFLLRC32M_COMP1 _SFR_MEM8(0x0065) -#define DFLLRC32M_COMP2 _SFR_MEM8(0x0066) - -/* DFLL - DFLL */ -#define DFLLRC2M_CTRL _SFR_MEM8(0x0068) -#define DFLLRC2M_CALA _SFR_MEM8(0x006A) -#define DFLLRC2M_CALB _SFR_MEM8(0x006B) -#define DFLLRC2M_COMP0 _SFR_MEM8(0x006C) -#define DFLLRC2M_COMP1 _SFR_MEM8(0x006D) -#define DFLLRC2M_COMP2 _SFR_MEM8(0x006E) - -/* PR - Power Reduction */ -#define PR_PRGEN _SFR_MEM8(0x0070) -#define PR_PRPA _SFR_MEM8(0x0071) -#define PR_PRPB _SFR_MEM8(0x0072) -#define PR_PRPC _SFR_MEM8(0x0073) -#define PR_PRPD _SFR_MEM8(0x0074) -#define PR_PRPE _SFR_MEM8(0x0075) -#define PR_PRPF _SFR_MEM8(0x0076) - -/* RST - Reset */ -#define RST_STATUS _SFR_MEM8(0x0078) -#define RST_CTRL _SFR_MEM8(0x0079) - -/* WDT - Watch-Dog Timer */ -#define WDT_CTRL _SFR_MEM8(0x0080) -#define WDT_WINCTRL _SFR_MEM8(0x0081) -#define WDT_STATUS _SFR_MEM8(0x0082) - -/* MCU - MCU Control */ -#define MCU_DEVID0 _SFR_MEM8(0x0090) -#define MCU_DEVID1 _SFR_MEM8(0x0091) -#define MCU_DEVID2 _SFR_MEM8(0x0092) -#define MCU_REVID _SFR_MEM8(0x0093) -#define MCU_JTAGUID _SFR_MEM8(0x0094) -#define MCU_MCUCR _SFR_MEM8(0x0096) -#define MCU_ANAINIT _SFR_MEM8(0x0097) -#define MCU_EVSYSLOCK _SFR_MEM8(0x0098) -#define MCU_AWEXLOCK _SFR_MEM8(0x0099) - -/* PMIC - Programmable Multi-level Interrupt Controller */ -#define PMIC_STATUS _SFR_MEM8(0x00A0) -#define PMIC_INTPRI _SFR_MEM8(0x00A1) -#define PMIC_CTRL _SFR_MEM8(0x00A2) - -/* PORTCFG - I/O port Configuration */ -#define PORTCFG_MPCMASK _SFR_MEM8(0x00B0) -#define PORTCFG_VPCTRLA _SFR_MEM8(0x00B2) -#define PORTCFG_VPCTRLB _SFR_MEM8(0x00B3) -#define PORTCFG_CLKEVOUT _SFR_MEM8(0x00B4) -#define PORTCFG_EBIOUT _SFR_MEM8(0x00B5) -#define PORTCFG_EVOUTSEL _SFR_MEM8(0x00B6) - -/* AES - AES Module */ -#define AES_CTRL _SFR_MEM8(0x00C0) -#define AES_STATUS _SFR_MEM8(0x00C1) -#define AES_STATE _SFR_MEM8(0x00C2) -#define AES_KEY _SFR_MEM8(0x00C3) -#define AES_INTCTRL _SFR_MEM8(0x00C4) - -/* CRC - Cyclic Redundancy Checker */ -#define CRC_CTRL _SFR_MEM8(0x00D0) -#define CRC_STATUS _SFR_MEM8(0x00D1) -#define CRC_DATAIN _SFR_MEM8(0x00D3) -#define CRC_CHECKSUM0 _SFR_MEM8(0x00D4) -#define CRC_CHECKSUM1 _SFR_MEM8(0x00D5) -#define CRC_CHECKSUM2 _SFR_MEM8(0x00D6) -#define CRC_CHECKSUM3 _SFR_MEM8(0x00D7) - -/* DMA - DMA Controller */ -#define DMA_CTRL _SFR_MEM8(0x0100) -#define DMA_INTFLAGS _SFR_MEM8(0x0103) -#define DMA_STATUS _SFR_MEM8(0x0104) -#define DMA_TEMP _SFR_MEM16(0x0106) -#define DMA_CH0_CTRLA _SFR_MEM8(0x0110) -#define DMA_CH0_CTRLB _SFR_MEM8(0x0111) -#define DMA_CH0_ADDRCTRL _SFR_MEM8(0x0112) -#define DMA_CH0_TRIGSRC _SFR_MEM8(0x0113) -#define DMA_CH0_TRFCNT _SFR_MEM16(0x0114) -#define DMA_CH0_REPCNT _SFR_MEM8(0x0116) -#define DMA_CH0_SRCADDR0 _SFR_MEM8(0x0118) -#define DMA_CH0_SRCADDR1 _SFR_MEM8(0x0119) -#define DMA_CH0_SRCADDR2 _SFR_MEM8(0x011A) -#define DMA_CH0_DESTADDR0 _SFR_MEM8(0x011C) -#define DMA_CH0_DESTADDR1 _SFR_MEM8(0x011D) -#define DMA_CH0_DESTADDR2 _SFR_MEM8(0x011E) -#define DMA_CH1_CTRLA _SFR_MEM8(0x0120) -#define DMA_CH1_CTRLB _SFR_MEM8(0x0121) -#define DMA_CH1_ADDRCTRL _SFR_MEM8(0x0122) -#define DMA_CH1_TRIGSRC _SFR_MEM8(0x0123) -#define DMA_CH1_TRFCNT _SFR_MEM16(0x0124) -#define DMA_CH1_REPCNT _SFR_MEM8(0x0126) -#define DMA_CH1_SRCADDR0 _SFR_MEM8(0x0128) -#define DMA_CH1_SRCADDR1 _SFR_MEM8(0x0129) -#define DMA_CH1_SRCADDR2 _SFR_MEM8(0x012A) -#define DMA_CH1_DESTADDR0 _SFR_MEM8(0x012C) -#define DMA_CH1_DESTADDR1 _SFR_MEM8(0x012D) -#define DMA_CH1_DESTADDR2 _SFR_MEM8(0x012E) -#define DMA_CH2_CTRLA _SFR_MEM8(0x0130) -#define DMA_CH2_CTRLB _SFR_MEM8(0x0131) -#define DMA_CH2_ADDRCTRL _SFR_MEM8(0x0132) -#define DMA_CH2_TRIGSRC _SFR_MEM8(0x0133) -#define DMA_CH2_TRFCNT _SFR_MEM16(0x0134) -#define DMA_CH2_REPCNT _SFR_MEM8(0x0136) -#define DMA_CH2_SRCADDR0 _SFR_MEM8(0x0138) -#define DMA_CH2_SRCADDR1 _SFR_MEM8(0x0139) -#define DMA_CH2_SRCADDR2 _SFR_MEM8(0x013A) -#define DMA_CH2_DESTADDR0 _SFR_MEM8(0x013C) -#define DMA_CH2_DESTADDR1 _SFR_MEM8(0x013D) -#define DMA_CH2_DESTADDR2 _SFR_MEM8(0x013E) -#define DMA_CH3_CTRLA _SFR_MEM8(0x0140) -#define DMA_CH3_CTRLB _SFR_MEM8(0x0141) -#define DMA_CH3_ADDRCTRL _SFR_MEM8(0x0142) -#define DMA_CH3_TRIGSRC _SFR_MEM8(0x0143) -#define DMA_CH3_TRFCNT _SFR_MEM16(0x0144) -#define DMA_CH3_REPCNT _SFR_MEM8(0x0146) -#define DMA_CH3_SRCADDR0 _SFR_MEM8(0x0148) -#define DMA_CH3_SRCADDR1 _SFR_MEM8(0x0149) -#define DMA_CH3_SRCADDR2 _SFR_MEM8(0x014A) -#define DMA_CH3_DESTADDR0 _SFR_MEM8(0x014C) -#define DMA_CH3_DESTADDR1 _SFR_MEM8(0x014D) -#define DMA_CH3_DESTADDR2 _SFR_MEM8(0x014E) - -/* EVSYS - Event System */ -#define EVSYS_CH0MUX _SFR_MEM8(0x0180) -#define EVSYS_CH1MUX _SFR_MEM8(0x0181) -#define EVSYS_CH2MUX _SFR_MEM8(0x0182) -#define EVSYS_CH3MUX _SFR_MEM8(0x0183) -#define EVSYS_CH4MUX _SFR_MEM8(0x0184) -#define EVSYS_CH5MUX _SFR_MEM8(0x0185) -#define EVSYS_CH6MUX _SFR_MEM8(0x0186) -#define EVSYS_CH7MUX _SFR_MEM8(0x0187) -#define EVSYS_CH0CTRL _SFR_MEM8(0x0188) -#define EVSYS_CH1CTRL _SFR_MEM8(0x0189) -#define EVSYS_CH2CTRL _SFR_MEM8(0x018A) -#define EVSYS_CH3CTRL _SFR_MEM8(0x018B) -#define EVSYS_CH4CTRL _SFR_MEM8(0x018C) -#define EVSYS_CH5CTRL _SFR_MEM8(0x018D) -#define EVSYS_CH6CTRL _SFR_MEM8(0x018E) -#define EVSYS_CH7CTRL _SFR_MEM8(0x018F) -#define EVSYS_STROBE _SFR_MEM8(0x0190) -#define EVSYS_DATA _SFR_MEM8(0x0191) - -/* NVM - Non-volatile Memory Controller */ -#define NVM_ADDR0 _SFR_MEM8(0x01C0) -#define NVM_ADDR1 _SFR_MEM8(0x01C1) -#define NVM_ADDR2 _SFR_MEM8(0x01C2) -#define NVM_DATA0 _SFR_MEM8(0x01C4) -#define NVM_DATA1 _SFR_MEM8(0x01C5) -#define NVM_DATA2 _SFR_MEM8(0x01C6) -#define NVM_CMD _SFR_MEM8(0x01CA) -#define NVM_CTRLA _SFR_MEM8(0x01CB) -#define NVM_CTRLB _SFR_MEM8(0x01CC) -#define NVM_INTCTRL _SFR_MEM8(0x01CD) -#define NVM_STATUS _SFR_MEM8(0x01CF) -#define NVM_LOCKBITS _SFR_MEM8(0x01D0) - -/* ADC - Analog-to-Digital Converter */ -#define ADCA_CTRLA _SFR_MEM8(0x0200) -#define ADCA_CTRLB _SFR_MEM8(0x0201) -#define ADCA_REFCTRL _SFR_MEM8(0x0202) -#define ADCA_EVCTRL _SFR_MEM8(0x0203) -#define ADCA_PRESCALER _SFR_MEM8(0x0204) -#define ADCA_INTFLAGS _SFR_MEM8(0x0206) -#define ADCA_TEMP _SFR_MEM8(0x0207) -#define ADCA_CAL _SFR_MEM16(0x020C) -#define ADCA_CH0RES _SFR_MEM16(0x0210) -#define ADCA_CH1RES _SFR_MEM16(0x0212) -#define ADCA_CH2RES _SFR_MEM16(0x0214) -#define ADCA_CH3RES _SFR_MEM16(0x0216) -#define ADCA_CMP _SFR_MEM16(0x0218) -#define ADCA_CH0_CTRL _SFR_MEM8(0x0220) -#define ADCA_CH0_MUXCTRL _SFR_MEM8(0x0221) -#define ADCA_CH0_INTCTRL _SFR_MEM8(0x0222) -#define ADCA_CH0_INTFLAGS _SFR_MEM8(0x0223) -#define ADCA_CH0_RES _SFR_MEM16(0x0224) -#define ADCA_CH0_SCAN _SFR_MEM8(0x0226) -#define ADCA_CH1_CTRL _SFR_MEM8(0x0228) -#define ADCA_CH1_MUXCTRL _SFR_MEM8(0x0229) -#define ADCA_CH1_INTCTRL _SFR_MEM8(0x022A) -#define ADCA_CH1_INTFLAGS _SFR_MEM8(0x022B) -#define ADCA_CH1_RES _SFR_MEM16(0x022C) -#define ADCA_CH1_SCAN _SFR_MEM8(0x022E) -#define ADCA_CH2_CTRL _SFR_MEM8(0x0230) -#define ADCA_CH2_MUXCTRL _SFR_MEM8(0x0231) -#define ADCA_CH2_INTCTRL _SFR_MEM8(0x0232) -#define ADCA_CH2_INTFLAGS _SFR_MEM8(0x0233) -#define ADCA_CH2_RES _SFR_MEM16(0x0234) -#define ADCA_CH2_SCAN _SFR_MEM8(0x0236) -#define ADCA_CH3_CTRL _SFR_MEM8(0x0238) -#define ADCA_CH3_MUXCTRL _SFR_MEM8(0x0239) -#define ADCA_CH3_INTCTRL _SFR_MEM8(0x023A) -#define ADCA_CH3_INTFLAGS _SFR_MEM8(0x023B) -#define ADCA_CH3_RES _SFR_MEM16(0x023C) -#define ADCA_CH3_SCAN _SFR_MEM8(0x023E) - -/* ADC - Analog-to-Digital Converter */ -#define ADCB_CTRLA _SFR_MEM8(0x0240) -#define ADCB_CTRLB _SFR_MEM8(0x0241) -#define ADCB_REFCTRL _SFR_MEM8(0x0242) -#define ADCB_EVCTRL _SFR_MEM8(0x0243) -#define ADCB_PRESCALER _SFR_MEM8(0x0244) -#define ADCB_INTFLAGS _SFR_MEM8(0x0246) -#define ADCB_TEMP _SFR_MEM8(0x0247) -#define ADCB_CAL _SFR_MEM16(0x024C) -#define ADCB_CH0RES _SFR_MEM16(0x0250) -#define ADCB_CH1RES _SFR_MEM16(0x0252) -#define ADCB_CH2RES _SFR_MEM16(0x0254) -#define ADCB_CH3RES _SFR_MEM16(0x0256) -#define ADCB_CMP _SFR_MEM16(0x0258) -#define ADCB_CH0_CTRL _SFR_MEM8(0x0260) -#define ADCB_CH0_MUXCTRL _SFR_MEM8(0x0261) -#define ADCB_CH0_INTCTRL _SFR_MEM8(0x0262) -#define ADCB_CH0_INTFLAGS _SFR_MEM8(0x0263) -#define ADCB_CH0_RES _SFR_MEM16(0x0264) -#define ADCB_CH0_SCAN _SFR_MEM8(0x0266) -#define ADCB_CH1_CTRL _SFR_MEM8(0x0268) -#define ADCB_CH1_MUXCTRL _SFR_MEM8(0x0269) -#define ADCB_CH1_INTCTRL _SFR_MEM8(0x026A) -#define ADCB_CH1_INTFLAGS _SFR_MEM8(0x026B) -#define ADCB_CH1_RES _SFR_MEM16(0x026C) -#define ADCB_CH1_SCAN _SFR_MEM8(0x026E) -#define ADCB_CH2_CTRL _SFR_MEM8(0x0270) -#define ADCB_CH2_MUXCTRL _SFR_MEM8(0x0271) -#define ADCB_CH2_INTCTRL _SFR_MEM8(0x0272) -#define ADCB_CH2_INTFLAGS _SFR_MEM8(0x0273) -#define ADCB_CH2_RES _SFR_MEM16(0x0274) -#define ADCB_CH2_SCAN _SFR_MEM8(0x0276) -#define ADCB_CH3_CTRL _SFR_MEM8(0x0278) -#define ADCB_CH3_MUXCTRL _SFR_MEM8(0x0279) -#define ADCB_CH3_INTCTRL _SFR_MEM8(0x027A) -#define ADCB_CH3_INTFLAGS _SFR_MEM8(0x027B) -#define ADCB_CH3_RES _SFR_MEM16(0x027C) -#define ADCB_CH3_SCAN _SFR_MEM8(0x027E) - -/* DAC - Digital-to-Analog Converter */ -#define DACA_CTRLA _SFR_MEM8(0x0300) -#define DACA_CTRLB _SFR_MEM8(0x0301) -#define DACA_CTRLC _SFR_MEM8(0x0302) -#define DACA_EVCTRL _SFR_MEM8(0x0303) -#define DACA_STATUS _SFR_MEM8(0x0305) -#define DACA_CH0GAINCAL _SFR_MEM8(0x0308) -#define DACA_CH0OFFSETCAL _SFR_MEM8(0x0309) -#define DACA_CH1GAINCAL _SFR_MEM8(0x030A) -#define DACA_CH1OFFSETCAL _SFR_MEM8(0x030B) -#define DACA_CH0DATA _SFR_MEM16(0x0318) -#define DACA_CH1DATA _SFR_MEM16(0x031A) - -/* DAC - Digital-to-Analog Converter */ -#define DACB_CTRLA _SFR_MEM8(0x0320) -#define DACB_CTRLB _SFR_MEM8(0x0321) -#define DACB_CTRLC _SFR_MEM8(0x0322) -#define DACB_EVCTRL _SFR_MEM8(0x0323) -#define DACB_STATUS _SFR_MEM8(0x0325) -#define DACB_CH0GAINCAL _SFR_MEM8(0x0328) -#define DACB_CH0OFFSETCAL _SFR_MEM8(0x0329) -#define DACB_CH1GAINCAL _SFR_MEM8(0x032A) -#define DACB_CH1OFFSETCAL _SFR_MEM8(0x032B) -#define DACB_CH0DATA _SFR_MEM16(0x0338) -#define DACB_CH1DATA _SFR_MEM16(0x033A) - -/* AC - Analog Comparator */ -#define ACA_AC0CTRL _SFR_MEM8(0x0380) -#define ACA_AC1CTRL _SFR_MEM8(0x0381) -#define ACA_AC0MUXCTRL _SFR_MEM8(0x0382) -#define ACA_AC1MUXCTRL _SFR_MEM8(0x0383) -#define ACA_CTRLA _SFR_MEM8(0x0384) -#define ACA_CTRLB _SFR_MEM8(0x0385) -#define ACA_WINCTRL _SFR_MEM8(0x0386) -#define ACA_STATUS _SFR_MEM8(0x0387) - -/* AC - Analog Comparator */ -#define ACB_AC0CTRL _SFR_MEM8(0x0390) -#define ACB_AC1CTRL _SFR_MEM8(0x0391) -#define ACB_AC0MUXCTRL _SFR_MEM8(0x0392) -#define ACB_AC1MUXCTRL _SFR_MEM8(0x0393) -#define ACB_CTRLA _SFR_MEM8(0x0394) -#define ACB_CTRLB _SFR_MEM8(0x0395) -#define ACB_WINCTRL _SFR_MEM8(0x0396) -#define ACB_STATUS _SFR_MEM8(0x0397) - -/* RTC - Real-Time Counter */ -#define RTC_CTRL _SFR_MEM8(0x0400) -#define RTC_STATUS _SFR_MEM8(0x0401) -#define RTC_INTCTRL _SFR_MEM8(0x0402) -#define RTC_INTFLAGS _SFR_MEM8(0x0403) -#define RTC_TEMP _SFR_MEM8(0x0404) -#define RTC_CNT _SFR_MEM16(0x0408) -#define RTC_PER _SFR_MEM16(0x040A) -#define RTC_COMP _SFR_MEM16(0x040C) - -/* EBI - External Bus Interface */ -#define EBI_CTRL _SFR_MEM8(0x0440) -#define EBI_SDRAMCTRLA _SFR_MEM8(0x0441) -#define EBI_REFRESH _SFR_MEM16(0x0444) -#define EBI_INITDLY _SFR_MEM16(0x0446) -#define EBI_SDRAMCTRLB _SFR_MEM8(0x0448) -#define EBI_SDRAMCTRLC _SFR_MEM8(0x0449) -#define EBI_CS0_CTRLA _SFR_MEM8(0x0450) -#define EBI_CS0_CTRLB _SFR_MEM8(0x0451) -#define EBI_CS0_BASEADDR _SFR_MEM16(0x0452) -#define EBI_CS1_CTRLA _SFR_MEM8(0x0454) -#define EBI_CS1_CTRLB _SFR_MEM8(0x0455) -#define EBI_CS1_BASEADDR _SFR_MEM16(0x0456) -#define EBI_CS2_CTRLA _SFR_MEM8(0x0458) -#define EBI_CS2_CTRLB _SFR_MEM8(0x0459) -#define EBI_CS2_BASEADDR _SFR_MEM16(0x045A) -#define EBI_CS3_CTRLA _SFR_MEM8(0x045C) -#define EBI_CS3_CTRLB _SFR_MEM8(0x045D) -#define EBI_CS3_BASEADDR _SFR_MEM16(0x045E) - -/* TWI - Two-Wire Interface */ -#define TWIC_CTRL _SFR_MEM8(0x0480) -#define TWIC_MASTER_CTRLA _SFR_MEM8(0x0481) -#define TWIC_MASTER_CTRLB _SFR_MEM8(0x0482) -#define TWIC_MASTER_CTRLC _SFR_MEM8(0x0483) -#define TWIC_MASTER_STATUS _SFR_MEM8(0x0484) -#define TWIC_MASTER_BAUD _SFR_MEM8(0x0485) -#define TWIC_MASTER_ADDR _SFR_MEM8(0x0486) -#define TWIC_MASTER_DATA _SFR_MEM8(0x0487) -#define TWIC_SLAVE_CTRLA _SFR_MEM8(0x0488) -#define TWIC_SLAVE_CTRLB _SFR_MEM8(0x0489) -#define TWIC_SLAVE_STATUS _SFR_MEM8(0x048A) -#define TWIC_SLAVE_ADDR _SFR_MEM8(0x048B) -#define TWIC_SLAVE_DATA _SFR_MEM8(0x048C) -#define TWIC_SLAVE_ADDRMASK _SFR_MEM8(0x048D) - -/* TWI - Two-Wire Interface */ -#define TWID_CTRL _SFR_MEM8(0x0490) -#define TWID_MASTER_CTRLA _SFR_MEM8(0x0491) -#define TWID_MASTER_CTRLB _SFR_MEM8(0x0492) -#define TWID_MASTER_CTRLC _SFR_MEM8(0x0493) -#define TWID_MASTER_STATUS _SFR_MEM8(0x0494) -#define TWID_MASTER_BAUD _SFR_MEM8(0x0495) -#define TWID_MASTER_ADDR _SFR_MEM8(0x0496) -#define TWID_MASTER_DATA _SFR_MEM8(0x0497) -#define TWID_SLAVE_CTRLA _SFR_MEM8(0x0498) -#define TWID_SLAVE_CTRLB _SFR_MEM8(0x0499) -#define TWID_SLAVE_STATUS _SFR_MEM8(0x049A) -#define TWID_SLAVE_ADDR _SFR_MEM8(0x049B) -#define TWID_SLAVE_DATA _SFR_MEM8(0x049C) -#define TWID_SLAVE_ADDRMASK _SFR_MEM8(0x049D) - -/* TWI - Two-Wire Interface */ -#define TWIE_CTRL _SFR_MEM8(0x04A0) -#define TWIE_MASTER_CTRLA _SFR_MEM8(0x04A1) -#define TWIE_MASTER_CTRLB _SFR_MEM8(0x04A2) -#define TWIE_MASTER_CTRLC _SFR_MEM8(0x04A3) -#define TWIE_MASTER_STATUS _SFR_MEM8(0x04A4) -#define TWIE_MASTER_BAUD _SFR_MEM8(0x04A5) -#define TWIE_MASTER_ADDR _SFR_MEM8(0x04A6) -#define TWIE_MASTER_DATA _SFR_MEM8(0x04A7) -#define TWIE_SLAVE_CTRLA _SFR_MEM8(0x04A8) -#define TWIE_SLAVE_CTRLB _SFR_MEM8(0x04A9) -#define TWIE_SLAVE_STATUS _SFR_MEM8(0x04AA) -#define TWIE_SLAVE_ADDR _SFR_MEM8(0x04AB) -#define TWIE_SLAVE_DATA _SFR_MEM8(0x04AC) -#define TWIE_SLAVE_ADDRMASK _SFR_MEM8(0x04AD) - -/* TWI - Two-Wire Interface */ -#define TWIF_CTRL _SFR_MEM8(0x04B0) -#define TWIF_MASTER_CTRLA _SFR_MEM8(0x04B1) -#define TWIF_MASTER_CTRLB _SFR_MEM8(0x04B2) -#define TWIF_MASTER_CTRLC _SFR_MEM8(0x04B3) -#define TWIF_MASTER_STATUS _SFR_MEM8(0x04B4) -#define TWIF_MASTER_BAUD _SFR_MEM8(0x04B5) -#define TWIF_MASTER_ADDR _SFR_MEM8(0x04B6) -#define TWIF_MASTER_DATA _SFR_MEM8(0x04B7) -#define TWIF_SLAVE_CTRLA _SFR_MEM8(0x04B8) -#define TWIF_SLAVE_CTRLB _SFR_MEM8(0x04B9) -#define TWIF_SLAVE_STATUS _SFR_MEM8(0x04BA) -#define TWIF_SLAVE_ADDR _SFR_MEM8(0x04BB) -#define TWIF_SLAVE_DATA _SFR_MEM8(0x04BC) -#define TWIF_SLAVE_ADDRMASK _SFR_MEM8(0x04BD) - -/* USB - Universal Serial Bus */ -#define USB_CTRLA _SFR_MEM8(0x04C0) -#define USB_CTRLB _SFR_MEM8(0x04C1) -#define USB_STATUS _SFR_MEM8(0x04C2) -#define USB_ADDR _SFR_MEM8(0x04C3) -#define USB_FIFOWP _SFR_MEM8(0x04C4) -#define USB_FIFORP _SFR_MEM8(0x04C5) -#define USB_EPPTR _SFR_MEM16(0x04C6) -#define USB_INTCTRLA _SFR_MEM8(0x04C8) -#define USB_INTCTRLB _SFR_MEM8(0x04C9) -#define USB_INTFLAGSACLR _SFR_MEM8(0x04CA) -#define USB_INTFLAGSASET _SFR_MEM8(0x04CB) -#define USB_INTFLAGSBCLR _SFR_MEM8(0x04CC) -#define USB_INTFLAGSBSET _SFR_MEM8(0x04CD) -#define USB_CAL0 _SFR_MEM8(0x04FA) -#define USB_CAL1 _SFR_MEM8(0x04FB) - -/* PORT - I/O Ports */ -#define PORTA_DIR _SFR_MEM8(0x0600) -#define PORTA_DIRSET _SFR_MEM8(0x0601) -#define PORTA_DIRCLR _SFR_MEM8(0x0602) -#define PORTA_DIRTGL _SFR_MEM8(0x0603) -#define PORTA_OUT _SFR_MEM8(0x0604) -#define PORTA_OUTSET _SFR_MEM8(0x0605) -#define PORTA_OUTCLR _SFR_MEM8(0x0606) -#define PORTA_OUTTGL _SFR_MEM8(0x0607) -#define PORTA_IN _SFR_MEM8(0x0608) -#define PORTA_INTCTRL _SFR_MEM8(0x0609) -#define PORTA_INT0MASK _SFR_MEM8(0x060A) -#define PORTA_INT1MASK _SFR_MEM8(0x060B) -#define PORTA_INTFLAGS _SFR_MEM8(0x060C) -#define PORTA_REMAP _SFR_MEM8(0x060E) -#define PORTA_PIN0CTRL _SFR_MEM8(0x0610) -#define PORTA_PIN1CTRL _SFR_MEM8(0x0611) -#define PORTA_PIN2CTRL _SFR_MEM8(0x0612) -#define PORTA_PIN3CTRL _SFR_MEM8(0x0613) -#define PORTA_PIN4CTRL _SFR_MEM8(0x0614) -#define PORTA_PIN5CTRL _SFR_MEM8(0x0615) -#define PORTA_PIN6CTRL _SFR_MEM8(0x0616) -#define PORTA_PIN7CTRL _SFR_MEM8(0x0617) - -/* PORT - I/O Ports */ -#define PORTB_DIR _SFR_MEM8(0x0620) -#define PORTB_DIRSET _SFR_MEM8(0x0621) -#define PORTB_DIRCLR _SFR_MEM8(0x0622) -#define PORTB_DIRTGL _SFR_MEM8(0x0623) -#define PORTB_OUT _SFR_MEM8(0x0624) -#define PORTB_OUTSET _SFR_MEM8(0x0625) -#define PORTB_OUTCLR _SFR_MEM8(0x0626) -#define PORTB_OUTTGL _SFR_MEM8(0x0627) -#define PORTB_IN _SFR_MEM8(0x0628) -#define PORTB_INTCTRL _SFR_MEM8(0x0629) -#define PORTB_INT0MASK _SFR_MEM8(0x062A) -#define PORTB_INT1MASK _SFR_MEM8(0x062B) -#define PORTB_INTFLAGS _SFR_MEM8(0x062C) -#define PORTB_REMAP _SFR_MEM8(0x062E) -#define PORTB_PIN0CTRL _SFR_MEM8(0x0630) -#define PORTB_PIN1CTRL _SFR_MEM8(0x0631) -#define PORTB_PIN2CTRL _SFR_MEM8(0x0632) -#define PORTB_PIN3CTRL _SFR_MEM8(0x0633) -#define PORTB_PIN4CTRL _SFR_MEM8(0x0634) -#define PORTB_PIN5CTRL _SFR_MEM8(0x0635) -#define PORTB_PIN6CTRL _SFR_MEM8(0x0636) -#define PORTB_PIN7CTRL _SFR_MEM8(0x0637) - -/* PORT - I/O Ports */ -#define PORTC_DIR _SFR_MEM8(0x0640) -#define PORTC_DIRSET _SFR_MEM8(0x0641) -#define PORTC_DIRCLR _SFR_MEM8(0x0642) -#define PORTC_DIRTGL _SFR_MEM8(0x0643) -#define PORTC_OUT _SFR_MEM8(0x0644) -#define PORTC_OUTSET _SFR_MEM8(0x0645) -#define PORTC_OUTCLR _SFR_MEM8(0x0646) -#define PORTC_OUTTGL _SFR_MEM8(0x0647) -#define PORTC_IN _SFR_MEM8(0x0648) -#define PORTC_INTCTRL _SFR_MEM8(0x0649) -#define PORTC_INT0MASK _SFR_MEM8(0x064A) -#define PORTC_INT1MASK _SFR_MEM8(0x064B) -#define PORTC_INTFLAGS _SFR_MEM8(0x064C) -#define PORTC_REMAP _SFR_MEM8(0x064E) -#define PORTC_PIN0CTRL _SFR_MEM8(0x0650) -#define PORTC_PIN1CTRL _SFR_MEM8(0x0651) -#define PORTC_PIN2CTRL _SFR_MEM8(0x0652) -#define PORTC_PIN3CTRL _SFR_MEM8(0x0653) -#define PORTC_PIN4CTRL _SFR_MEM8(0x0654) -#define PORTC_PIN5CTRL _SFR_MEM8(0x0655) -#define PORTC_PIN6CTRL _SFR_MEM8(0x0656) -#define PORTC_PIN7CTRL _SFR_MEM8(0x0657) - -/* PORT - I/O Ports */ -#define PORTD_DIR _SFR_MEM8(0x0660) -#define PORTD_DIRSET _SFR_MEM8(0x0661) -#define PORTD_DIRCLR _SFR_MEM8(0x0662) -#define PORTD_DIRTGL _SFR_MEM8(0x0663) -#define PORTD_OUT _SFR_MEM8(0x0664) -#define PORTD_OUTSET _SFR_MEM8(0x0665) -#define PORTD_OUTCLR _SFR_MEM8(0x0666) -#define PORTD_OUTTGL _SFR_MEM8(0x0667) -#define PORTD_IN _SFR_MEM8(0x0668) -#define PORTD_INTCTRL _SFR_MEM8(0x0669) -#define PORTD_INT0MASK _SFR_MEM8(0x066A) -#define PORTD_INT1MASK _SFR_MEM8(0x066B) -#define PORTD_INTFLAGS _SFR_MEM8(0x066C) -#define PORTD_REMAP _SFR_MEM8(0x066E) -#define PORTD_PIN0CTRL _SFR_MEM8(0x0670) -#define PORTD_PIN1CTRL _SFR_MEM8(0x0671) -#define PORTD_PIN2CTRL _SFR_MEM8(0x0672) -#define PORTD_PIN3CTRL _SFR_MEM8(0x0673) -#define PORTD_PIN4CTRL _SFR_MEM8(0x0674) -#define PORTD_PIN5CTRL _SFR_MEM8(0x0675) -#define PORTD_PIN6CTRL _SFR_MEM8(0x0676) -#define PORTD_PIN7CTRL _SFR_MEM8(0x0677) - -/* PORT - I/O Ports */ -#define PORTE_DIR _SFR_MEM8(0x0680) -#define PORTE_DIRSET _SFR_MEM8(0x0681) -#define PORTE_DIRCLR _SFR_MEM8(0x0682) -#define PORTE_DIRTGL _SFR_MEM8(0x0683) -#define PORTE_OUT _SFR_MEM8(0x0684) -#define PORTE_OUTSET _SFR_MEM8(0x0685) -#define PORTE_OUTCLR _SFR_MEM8(0x0686) -#define PORTE_OUTTGL _SFR_MEM8(0x0687) -#define PORTE_IN _SFR_MEM8(0x0688) -#define PORTE_INTCTRL _SFR_MEM8(0x0689) -#define PORTE_INT0MASK _SFR_MEM8(0x068A) -#define PORTE_INT1MASK _SFR_MEM8(0x068B) -#define PORTE_INTFLAGS _SFR_MEM8(0x068C) -#define PORTE_REMAP _SFR_MEM8(0x068E) -#define PORTE_PIN0CTRL _SFR_MEM8(0x0690) -#define PORTE_PIN1CTRL _SFR_MEM8(0x0691) -#define PORTE_PIN2CTRL _SFR_MEM8(0x0692) -#define PORTE_PIN3CTRL _SFR_MEM8(0x0693) -#define PORTE_PIN4CTRL _SFR_MEM8(0x0694) -#define PORTE_PIN5CTRL _SFR_MEM8(0x0695) -#define PORTE_PIN6CTRL _SFR_MEM8(0x0696) -#define PORTE_PIN7CTRL _SFR_MEM8(0x0697) - -/* PORT - I/O Ports */ -#define PORTF_DIR _SFR_MEM8(0x06A0) -#define PORTF_DIRSET _SFR_MEM8(0x06A1) -#define PORTF_DIRCLR _SFR_MEM8(0x06A2) -#define PORTF_DIRTGL _SFR_MEM8(0x06A3) -#define PORTF_OUT _SFR_MEM8(0x06A4) -#define PORTF_OUTSET _SFR_MEM8(0x06A5) -#define PORTF_OUTCLR _SFR_MEM8(0x06A6) -#define PORTF_OUTTGL _SFR_MEM8(0x06A7) -#define PORTF_IN _SFR_MEM8(0x06A8) -#define PORTF_INTCTRL _SFR_MEM8(0x06A9) -#define PORTF_INT0MASK _SFR_MEM8(0x06AA) -#define PORTF_INT1MASK _SFR_MEM8(0x06AB) -#define PORTF_INTFLAGS _SFR_MEM8(0x06AC) -#define PORTF_REMAP _SFR_MEM8(0x06AE) -#define PORTF_PIN0CTRL _SFR_MEM8(0x06B0) -#define PORTF_PIN1CTRL _SFR_MEM8(0x06B1) -#define PORTF_PIN2CTRL _SFR_MEM8(0x06B2) -#define PORTF_PIN3CTRL _SFR_MEM8(0x06B3) -#define PORTF_PIN4CTRL _SFR_MEM8(0x06B4) -#define PORTF_PIN5CTRL _SFR_MEM8(0x06B5) -#define PORTF_PIN6CTRL _SFR_MEM8(0x06B6) -#define PORTF_PIN7CTRL _SFR_MEM8(0x06B7) - -/* PORT - I/O Ports */ -#define PORTH_DIR _SFR_MEM8(0x06E0) -#define PORTH_DIRSET _SFR_MEM8(0x06E1) -#define PORTH_DIRCLR _SFR_MEM8(0x06E2) -#define PORTH_DIRTGL _SFR_MEM8(0x06E3) -#define PORTH_OUT _SFR_MEM8(0x06E4) -#define PORTH_OUTSET _SFR_MEM8(0x06E5) -#define PORTH_OUTCLR _SFR_MEM8(0x06E6) -#define PORTH_OUTTGL _SFR_MEM8(0x06E7) -#define PORTH_IN _SFR_MEM8(0x06E8) -#define PORTH_INTCTRL _SFR_MEM8(0x06E9) -#define PORTH_INT0MASK _SFR_MEM8(0x06EA) -#define PORTH_INT1MASK _SFR_MEM8(0x06EB) -#define PORTH_INTFLAGS _SFR_MEM8(0x06EC) -#define PORTH_REMAP _SFR_MEM8(0x06EE) -#define PORTH_PIN0CTRL _SFR_MEM8(0x06F0) -#define PORTH_PIN1CTRL _SFR_MEM8(0x06F1) -#define PORTH_PIN2CTRL _SFR_MEM8(0x06F2) -#define PORTH_PIN3CTRL _SFR_MEM8(0x06F3) -#define PORTH_PIN4CTRL _SFR_MEM8(0x06F4) -#define PORTH_PIN5CTRL _SFR_MEM8(0x06F5) -#define PORTH_PIN6CTRL _SFR_MEM8(0x06F6) -#define PORTH_PIN7CTRL _SFR_MEM8(0x06F7) - -/* PORT - I/O Ports */ -#define PORTJ_DIR _SFR_MEM8(0x0700) -#define PORTJ_DIRSET _SFR_MEM8(0x0701) -#define PORTJ_DIRCLR _SFR_MEM8(0x0702) -#define PORTJ_DIRTGL _SFR_MEM8(0x0703) -#define PORTJ_OUT _SFR_MEM8(0x0704) -#define PORTJ_OUTSET _SFR_MEM8(0x0705) -#define PORTJ_OUTCLR _SFR_MEM8(0x0706) -#define PORTJ_OUTTGL _SFR_MEM8(0x0707) -#define PORTJ_IN _SFR_MEM8(0x0708) -#define PORTJ_INTCTRL _SFR_MEM8(0x0709) -#define PORTJ_INT0MASK _SFR_MEM8(0x070A) -#define PORTJ_INT1MASK _SFR_MEM8(0x070B) -#define PORTJ_INTFLAGS _SFR_MEM8(0x070C) -#define PORTJ_REMAP _SFR_MEM8(0x070E) -#define PORTJ_PIN0CTRL _SFR_MEM8(0x0710) -#define PORTJ_PIN1CTRL _SFR_MEM8(0x0711) -#define PORTJ_PIN2CTRL _SFR_MEM8(0x0712) -#define PORTJ_PIN3CTRL _SFR_MEM8(0x0713) -#define PORTJ_PIN4CTRL _SFR_MEM8(0x0714) -#define PORTJ_PIN5CTRL _SFR_MEM8(0x0715) -#define PORTJ_PIN6CTRL _SFR_MEM8(0x0716) -#define PORTJ_PIN7CTRL _SFR_MEM8(0x0717) - -/* PORT - I/O Ports */ -#define PORTK_DIR _SFR_MEM8(0x0720) -#define PORTK_DIRSET _SFR_MEM8(0x0721) -#define PORTK_DIRCLR _SFR_MEM8(0x0722) -#define PORTK_DIRTGL _SFR_MEM8(0x0723) -#define PORTK_OUT _SFR_MEM8(0x0724) -#define PORTK_OUTSET _SFR_MEM8(0x0725) -#define PORTK_OUTCLR _SFR_MEM8(0x0726) -#define PORTK_OUTTGL _SFR_MEM8(0x0727) -#define PORTK_IN _SFR_MEM8(0x0728) -#define PORTK_INTCTRL _SFR_MEM8(0x0729) -#define PORTK_INT0MASK _SFR_MEM8(0x072A) -#define PORTK_INT1MASK _SFR_MEM8(0x072B) -#define PORTK_INTFLAGS _SFR_MEM8(0x072C) -#define PORTK_REMAP _SFR_MEM8(0x072E) -#define PORTK_PIN0CTRL _SFR_MEM8(0x0730) -#define PORTK_PIN1CTRL _SFR_MEM8(0x0731) -#define PORTK_PIN2CTRL _SFR_MEM8(0x0732) -#define PORTK_PIN3CTRL _SFR_MEM8(0x0733) -#define PORTK_PIN4CTRL _SFR_MEM8(0x0734) -#define PORTK_PIN5CTRL _SFR_MEM8(0x0735) -#define PORTK_PIN6CTRL _SFR_MEM8(0x0736) -#define PORTK_PIN7CTRL _SFR_MEM8(0x0737) - -/* PORT - I/O Ports */ -#define PORTQ_DIR _SFR_MEM8(0x07C0) -#define PORTQ_DIRSET _SFR_MEM8(0x07C1) -#define PORTQ_DIRCLR _SFR_MEM8(0x07C2) -#define PORTQ_DIRTGL _SFR_MEM8(0x07C3) -#define PORTQ_OUT _SFR_MEM8(0x07C4) -#define PORTQ_OUTSET _SFR_MEM8(0x07C5) -#define PORTQ_OUTCLR _SFR_MEM8(0x07C6) -#define PORTQ_OUTTGL _SFR_MEM8(0x07C7) -#define PORTQ_IN _SFR_MEM8(0x07C8) -#define PORTQ_INTCTRL _SFR_MEM8(0x07C9) -#define PORTQ_INT0MASK _SFR_MEM8(0x07CA) -#define PORTQ_INT1MASK _SFR_MEM8(0x07CB) -#define PORTQ_INTFLAGS _SFR_MEM8(0x07CC) -#define PORTQ_REMAP _SFR_MEM8(0x07CE) -#define PORTQ_PIN0CTRL _SFR_MEM8(0x07D0) -#define PORTQ_PIN1CTRL _SFR_MEM8(0x07D1) -#define PORTQ_PIN2CTRL _SFR_MEM8(0x07D2) -#define PORTQ_PIN3CTRL _SFR_MEM8(0x07D3) -#define PORTQ_PIN4CTRL _SFR_MEM8(0x07D4) -#define PORTQ_PIN5CTRL _SFR_MEM8(0x07D5) -#define PORTQ_PIN6CTRL _SFR_MEM8(0x07D6) -#define PORTQ_PIN7CTRL _SFR_MEM8(0x07D7) - -/* PORT - I/O Ports */ -#define PORTR_DIR _SFR_MEM8(0x07E0) -#define PORTR_DIRSET _SFR_MEM8(0x07E1) -#define PORTR_DIRCLR _SFR_MEM8(0x07E2) -#define PORTR_DIRTGL _SFR_MEM8(0x07E3) -#define PORTR_OUT _SFR_MEM8(0x07E4) -#define PORTR_OUTSET _SFR_MEM8(0x07E5) -#define PORTR_OUTCLR _SFR_MEM8(0x07E6) -#define PORTR_OUTTGL _SFR_MEM8(0x07E7) -#define PORTR_IN _SFR_MEM8(0x07E8) -#define PORTR_INTCTRL _SFR_MEM8(0x07E9) -#define PORTR_INT0MASK _SFR_MEM8(0x07EA) -#define PORTR_INT1MASK _SFR_MEM8(0x07EB) -#define PORTR_INTFLAGS _SFR_MEM8(0x07EC) -#define PORTR_REMAP _SFR_MEM8(0x07EE) -#define PORTR_PIN0CTRL _SFR_MEM8(0x07F0) -#define PORTR_PIN1CTRL _SFR_MEM8(0x07F1) -#define PORTR_PIN2CTRL _SFR_MEM8(0x07F2) -#define PORTR_PIN3CTRL _SFR_MEM8(0x07F3) -#define PORTR_PIN4CTRL _SFR_MEM8(0x07F4) -#define PORTR_PIN5CTRL _SFR_MEM8(0x07F5) -#define PORTR_PIN6CTRL _SFR_MEM8(0x07F6) -#define PORTR_PIN7CTRL _SFR_MEM8(0x07F7) - -/* TC0 - 16-bit Timer/Counter 0 */ -#define TCC0_CTRLA _SFR_MEM8(0x0800) -#define TCC0_CTRLB _SFR_MEM8(0x0801) -#define TCC0_CTRLC _SFR_MEM8(0x0802) -#define TCC0_CTRLD _SFR_MEM8(0x0803) -#define TCC0_CTRLE _SFR_MEM8(0x0804) -#define TCC0_INTCTRLA _SFR_MEM8(0x0806) -#define TCC0_INTCTRLB _SFR_MEM8(0x0807) -#define TCC0_CTRLFCLR _SFR_MEM8(0x0808) -#define TCC0_CTRLFSET _SFR_MEM8(0x0809) -#define TCC0_CTRLGCLR _SFR_MEM8(0x080A) -#define TCC0_CTRLGSET _SFR_MEM8(0x080B) -#define TCC0_INTFLAGS _SFR_MEM8(0x080C) -#define TCC0_TEMP _SFR_MEM8(0x080F) -#define TCC0_CNT _SFR_MEM16(0x0820) -#define TCC0_PER _SFR_MEM16(0x0826) -#define TCC0_CCA _SFR_MEM16(0x0828) -#define TCC0_CCB _SFR_MEM16(0x082A) -#define TCC0_CCC _SFR_MEM16(0x082C) -#define TCC0_CCD _SFR_MEM16(0x082E) -#define TCC0_PERBUF _SFR_MEM16(0x0836) -#define TCC0_CCABUF _SFR_MEM16(0x0838) -#define TCC0_CCBBUF _SFR_MEM16(0x083A) -#define TCC0_CCCBUF _SFR_MEM16(0x083C) -#define TCC0_CCDBUF _SFR_MEM16(0x083E) - -/* TC2 - 16-bit Timer/Counter type 2 */ -#define TCC2_CTRLA _SFR_MEM8(0x0800) -#define TCC2_CTRLB _SFR_MEM8(0x0801) -#define TCC2_CTRLC _SFR_MEM8(0x0802) -#define TCC2_CTRLE _SFR_MEM8(0x0804) -#define TCC2_INTCTRLA _SFR_MEM8(0x0806) -#define TCC2_INTCTRLB _SFR_MEM8(0x0807) -#define TCC2_CTRLF _SFR_MEM8(0x0809) -#define TCC2_INTFLAGS _SFR_MEM8(0x080C) -#define TCC2_LCNT _SFR_MEM8(0x0820) -#define TCC2_HCNT _SFR_MEM8(0x0821) -#define TCC2_LPER _SFR_MEM8(0x0826) -#define TCC2_HPER _SFR_MEM8(0x0827) -#define TCC2_LCMPA _SFR_MEM8(0x0828) -#define TCC2_HCMPA _SFR_MEM8(0x0829) -#define TCC2_LCMPB _SFR_MEM8(0x082A) -#define TCC2_HCMPB _SFR_MEM8(0x082B) -#define TCC2_LCMPC _SFR_MEM8(0x082C) -#define TCC2_HCMPC _SFR_MEM8(0x082D) -#define TCC2_LCMPD _SFR_MEM8(0x082E) -#define TCC2_HCMPD _SFR_MEM8(0x082F) - -/* TC1 - 16-bit Timer/Counter 1 */ -#define TCC1_CTRLA _SFR_MEM8(0x0840) -#define TCC1_CTRLB _SFR_MEM8(0x0841) -#define TCC1_CTRLC _SFR_MEM8(0x0842) -#define TCC1_CTRLD _SFR_MEM8(0x0843) -#define TCC1_CTRLE _SFR_MEM8(0x0844) -#define TCC1_INTCTRLA _SFR_MEM8(0x0846) -#define TCC1_INTCTRLB _SFR_MEM8(0x0847) -#define TCC1_CTRLFCLR _SFR_MEM8(0x0848) -#define TCC1_CTRLFSET _SFR_MEM8(0x0849) -#define TCC1_CTRLGCLR _SFR_MEM8(0x084A) -#define TCC1_CTRLGSET _SFR_MEM8(0x084B) -#define TCC1_INTFLAGS _SFR_MEM8(0x084C) -#define TCC1_TEMP _SFR_MEM8(0x084F) -#define TCC1_CNT _SFR_MEM16(0x0860) -#define TCC1_PER _SFR_MEM16(0x0866) -#define TCC1_CCA _SFR_MEM16(0x0868) -#define TCC1_CCB _SFR_MEM16(0x086A) -#define TCC1_PERBUF _SFR_MEM16(0x0876) -#define TCC1_CCABUF _SFR_MEM16(0x0878) -#define TCC1_CCBBUF _SFR_MEM16(0x087A) - -/* AWEX - Advanced Waveform Extension */ -#define AWEXC_CTRL _SFR_MEM8(0x0880) -#define AWEXC_FDEMASK _SFR_MEM8(0x0882) -#define AWEXC_FDCTRL _SFR_MEM8(0x0883) -#define AWEXC_STATUS _SFR_MEM8(0x0884) -#define AWEXC_STATUSSET _SFR_MEM8(0x0885) -#define AWEXC_DTBOTH _SFR_MEM8(0x0886) -#define AWEXC_DTBOTHBUF _SFR_MEM8(0x0887) -#define AWEXC_DTLS _SFR_MEM8(0x0888) -#define AWEXC_DTHS _SFR_MEM8(0x0889) -#define AWEXC_DTLSBUF _SFR_MEM8(0x088A) -#define AWEXC_DTHSBUF _SFR_MEM8(0x088B) -#define AWEXC_OUTOVEN _SFR_MEM8(0x088C) - -/* HIRES - High-Resolution Extension */ -#define HIRESC_CTRLA _SFR_MEM8(0x0890) - -/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ -#define USARTC0_DATA _SFR_MEM8(0x08A0) -#define USARTC0_STATUS _SFR_MEM8(0x08A1) -#define USARTC0_CTRLA _SFR_MEM8(0x08A3) -#define USARTC0_CTRLB _SFR_MEM8(0x08A4) -#define USARTC0_CTRLC _SFR_MEM8(0x08A5) -#define USARTC0_BAUDCTRLA _SFR_MEM8(0x08A6) -#define USARTC0_BAUDCTRLB _SFR_MEM8(0x08A7) - -/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ -#define USARTC1_DATA _SFR_MEM8(0x08B0) -#define USARTC1_STATUS _SFR_MEM8(0x08B1) -#define USARTC1_CTRLA _SFR_MEM8(0x08B3) -#define USARTC1_CTRLB _SFR_MEM8(0x08B4) -#define USARTC1_CTRLC _SFR_MEM8(0x08B5) -#define USARTC1_BAUDCTRLA _SFR_MEM8(0x08B6) -#define USARTC1_BAUDCTRLB _SFR_MEM8(0x08B7) - -/* SPI - Serial Peripheral Interface */ -#define SPIC_CTRL _SFR_MEM8(0x08C0) -#define SPIC_INTCTRL _SFR_MEM8(0x08C1) -#define SPIC_STATUS _SFR_MEM8(0x08C2) -#define SPIC_DATA _SFR_MEM8(0x08C3) - -/* IRCOM - IR Communication Module */ -#define IRCOM_CTRL _SFR_MEM8(0x08F8) -#define IRCOM_TXPLCTRL _SFR_MEM8(0x08F9) -#define IRCOM_RXPLCTRL _SFR_MEM8(0x08FA) - -/* TC0 - 16-bit Timer/Counter 0 */ -#define TCD0_CTRLA _SFR_MEM8(0x0900) -#define TCD0_CTRLB _SFR_MEM8(0x0901) -#define TCD0_CTRLC _SFR_MEM8(0x0902) -#define TCD0_CTRLD _SFR_MEM8(0x0903) -#define TCD0_CTRLE _SFR_MEM8(0x0904) -#define TCD0_INTCTRLA _SFR_MEM8(0x0906) -#define TCD0_INTCTRLB _SFR_MEM8(0x0907) -#define TCD0_CTRLFCLR _SFR_MEM8(0x0908) -#define TCD0_CTRLFSET _SFR_MEM8(0x0909) -#define TCD0_CTRLGCLR _SFR_MEM8(0x090A) -#define TCD0_CTRLGSET _SFR_MEM8(0x090B) -#define TCD0_INTFLAGS _SFR_MEM8(0x090C) -#define TCD0_TEMP _SFR_MEM8(0x090F) -#define TCD0_CNT _SFR_MEM16(0x0920) -#define TCD0_PER _SFR_MEM16(0x0926) -#define TCD0_CCA _SFR_MEM16(0x0928) -#define TCD0_CCB _SFR_MEM16(0x092A) -#define TCD0_CCC _SFR_MEM16(0x092C) -#define TCD0_CCD _SFR_MEM16(0x092E) -#define TCD0_PERBUF _SFR_MEM16(0x0936) -#define TCD0_CCABUF _SFR_MEM16(0x0938) -#define TCD0_CCBBUF _SFR_MEM16(0x093A) -#define TCD0_CCCBUF _SFR_MEM16(0x093C) -#define TCD0_CCDBUF _SFR_MEM16(0x093E) - -/* TC2 - 16-bit Timer/Counter type 2 */ -#define TCD2_CTRLA _SFR_MEM8(0x0900) -#define TCD2_CTRLB _SFR_MEM8(0x0901) -#define TCD2_CTRLC _SFR_MEM8(0x0902) -#define TCD2_CTRLE _SFR_MEM8(0x0904) -#define TCD2_INTCTRLA _SFR_MEM8(0x0906) -#define TCD2_INTCTRLB _SFR_MEM8(0x0907) -#define TCD2_CTRLF _SFR_MEM8(0x0909) -#define TCD2_INTFLAGS _SFR_MEM8(0x090C) -#define TCD2_LCNT _SFR_MEM8(0x0920) -#define TCD2_HCNT _SFR_MEM8(0x0921) -#define TCD2_LPER _SFR_MEM8(0x0926) -#define TCD2_HPER _SFR_MEM8(0x0927) -#define TCD2_LCMPA _SFR_MEM8(0x0928) -#define TCD2_HCMPA _SFR_MEM8(0x0929) -#define TCD2_LCMPB _SFR_MEM8(0x092A) -#define TCD2_HCMPB _SFR_MEM8(0x092B) -#define TCD2_LCMPC _SFR_MEM8(0x092C) -#define TCD2_HCMPC _SFR_MEM8(0x092D) -#define TCD2_LCMPD _SFR_MEM8(0x092E) -#define TCD2_HCMPD _SFR_MEM8(0x092F) - -/* TC1 - 16-bit Timer/Counter 1 */ -#define TCD1_CTRLA _SFR_MEM8(0x0940) -#define TCD1_CTRLB _SFR_MEM8(0x0941) -#define TCD1_CTRLC _SFR_MEM8(0x0942) -#define TCD1_CTRLD _SFR_MEM8(0x0943) -#define TCD1_CTRLE _SFR_MEM8(0x0944) -#define TCD1_INTCTRLA _SFR_MEM8(0x0946) -#define TCD1_INTCTRLB _SFR_MEM8(0x0947) -#define TCD1_CTRLFCLR _SFR_MEM8(0x0948) -#define TCD1_CTRLFSET _SFR_MEM8(0x0949) -#define TCD1_CTRLGCLR _SFR_MEM8(0x094A) -#define TCD1_CTRLGSET _SFR_MEM8(0x094B) -#define TCD1_INTFLAGS _SFR_MEM8(0x094C) -#define TCD1_TEMP _SFR_MEM8(0x094F) -#define TCD1_CNT _SFR_MEM16(0x0960) -#define TCD1_PER _SFR_MEM16(0x0966) -#define TCD1_CCA _SFR_MEM16(0x0968) -#define TCD1_CCB _SFR_MEM16(0x096A) -#define TCD1_PERBUF _SFR_MEM16(0x0976) -#define TCD1_CCABUF _SFR_MEM16(0x0978) -#define TCD1_CCBBUF _SFR_MEM16(0x097A) - -/* HIRES - High-Resolution Extension */ -#define HIRESD_CTRLA _SFR_MEM8(0x0990) - -/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ -#define USARTD0_DATA _SFR_MEM8(0x09A0) -#define USARTD0_STATUS _SFR_MEM8(0x09A1) -#define USARTD0_CTRLA _SFR_MEM8(0x09A3) -#define USARTD0_CTRLB _SFR_MEM8(0x09A4) -#define USARTD0_CTRLC _SFR_MEM8(0x09A5) -#define USARTD0_BAUDCTRLA _SFR_MEM8(0x09A6) -#define USARTD0_BAUDCTRLB _SFR_MEM8(0x09A7) - -/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ -#define USARTD1_DATA _SFR_MEM8(0x09B0) -#define USARTD1_STATUS _SFR_MEM8(0x09B1) -#define USARTD1_CTRLA _SFR_MEM8(0x09B3) -#define USARTD1_CTRLB _SFR_MEM8(0x09B4) -#define USARTD1_CTRLC _SFR_MEM8(0x09B5) -#define USARTD1_BAUDCTRLA _SFR_MEM8(0x09B6) -#define USARTD1_BAUDCTRLB _SFR_MEM8(0x09B7) - -/* SPI - Serial Peripheral Interface */ -#define SPID_CTRL _SFR_MEM8(0x09C0) -#define SPID_INTCTRL _SFR_MEM8(0x09C1) -#define SPID_STATUS _SFR_MEM8(0x09C2) -#define SPID_DATA _SFR_MEM8(0x09C3) - -/* TC0 - 16-bit Timer/Counter 0 */ -#define TCE0_CTRLA _SFR_MEM8(0x0A00) -#define TCE0_CTRLB _SFR_MEM8(0x0A01) -#define TCE0_CTRLC _SFR_MEM8(0x0A02) -#define TCE0_CTRLD _SFR_MEM8(0x0A03) -#define TCE0_CTRLE _SFR_MEM8(0x0A04) -#define TCE0_INTCTRLA _SFR_MEM8(0x0A06) -#define TCE0_INTCTRLB _SFR_MEM8(0x0A07) -#define TCE0_CTRLFCLR _SFR_MEM8(0x0A08) -#define TCE0_CTRLFSET _SFR_MEM8(0x0A09) -#define TCE0_CTRLGCLR _SFR_MEM8(0x0A0A) -#define TCE0_CTRLGSET _SFR_MEM8(0x0A0B) -#define TCE0_INTFLAGS _SFR_MEM8(0x0A0C) -#define TCE0_TEMP _SFR_MEM8(0x0A0F) -#define TCE0_CNT _SFR_MEM16(0x0A20) -#define TCE0_PER _SFR_MEM16(0x0A26) -#define TCE0_CCA _SFR_MEM16(0x0A28) -#define TCE0_CCB _SFR_MEM16(0x0A2A) -#define TCE0_CCC _SFR_MEM16(0x0A2C) -#define TCE0_CCD _SFR_MEM16(0x0A2E) -#define TCE0_PERBUF _SFR_MEM16(0x0A36) -#define TCE0_CCABUF _SFR_MEM16(0x0A38) -#define TCE0_CCBBUF _SFR_MEM16(0x0A3A) -#define TCE0_CCCBUF _SFR_MEM16(0x0A3C) -#define TCE0_CCDBUF _SFR_MEM16(0x0A3E) - -/* TC2 - 16-bit Timer/Counter type 2 */ -#define TCE2_CTRLA _SFR_MEM8(0x0A00) -#define TCE2_CTRLB _SFR_MEM8(0x0A01) -#define TCE2_CTRLC _SFR_MEM8(0x0A02) -#define TCE2_CTRLE _SFR_MEM8(0x0A04) -#define TCE2_INTCTRLA _SFR_MEM8(0x0A06) -#define TCE2_INTCTRLB _SFR_MEM8(0x0A07) -#define TCE2_CTRLF _SFR_MEM8(0x0A09) -#define TCE2_INTFLAGS _SFR_MEM8(0x0A0C) -#define TCE2_LCNT _SFR_MEM8(0x0A20) -#define TCE2_HCNT _SFR_MEM8(0x0A21) -#define TCE2_LPER _SFR_MEM8(0x0A26) -#define TCE2_HPER _SFR_MEM8(0x0A27) -#define TCE2_LCMPA _SFR_MEM8(0x0A28) -#define TCE2_HCMPA _SFR_MEM8(0x0A29) -#define TCE2_LCMPB _SFR_MEM8(0x0A2A) -#define TCE2_HCMPB _SFR_MEM8(0x0A2B) -#define TCE2_LCMPC _SFR_MEM8(0x0A2C) -#define TCE2_HCMPC _SFR_MEM8(0x0A2D) -#define TCE2_LCMPD _SFR_MEM8(0x0A2E) -#define TCE2_HCMPD _SFR_MEM8(0x0A2F) - -/* TC1 - 16-bit Timer/Counter 1 */ -#define TCE1_CTRLA _SFR_MEM8(0x0A40) -#define TCE1_CTRLB _SFR_MEM8(0x0A41) -#define TCE1_CTRLC _SFR_MEM8(0x0A42) -#define TCE1_CTRLD _SFR_MEM8(0x0A43) -#define TCE1_CTRLE _SFR_MEM8(0x0A44) -#define TCE1_INTCTRLA _SFR_MEM8(0x0A46) -#define TCE1_INTCTRLB _SFR_MEM8(0x0A47) -#define TCE1_CTRLFCLR _SFR_MEM8(0x0A48) -#define TCE1_CTRLFSET _SFR_MEM8(0x0A49) -#define TCE1_CTRLGCLR _SFR_MEM8(0x0A4A) -#define TCE1_CTRLGSET _SFR_MEM8(0x0A4B) -#define TCE1_INTFLAGS _SFR_MEM8(0x0A4C) -#define TCE1_TEMP _SFR_MEM8(0x0A4F) -#define TCE1_CNT _SFR_MEM16(0x0A60) -#define TCE1_PER _SFR_MEM16(0x0A66) -#define TCE1_CCA _SFR_MEM16(0x0A68) -#define TCE1_CCB _SFR_MEM16(0x0A6A) -#define TCE1_PERBUF _SFR_MEM16(0x0A76) -#define TCE1_CCABUF _SFR_MEM16(0x0A78) -#define TCE1_CCBBUF _SFR_MEM16(0x0A7A) - -/* AWEX - Advanced Waveform Extension */ -#define AWEXE_CTRL _SFR_MEM8(0x0A80) -#define AWEXE_FDEMASK _SFR_MEM8(0x0A82) -#define AWEXE_FDCTRL _SFR_MEM8(0x0A83) -#define AWEXE_STATUS _SFR_MEM8(0x0A84) -#define AWEXE_STATUSSET _SFR_MEM8(0x0A85) -#define AWEXE_DTBOTH _SFR_MEM8(0x0A86) -#define AWEXE_DTBOTHBUF _SFR_MEM8(0x0A87) -#define AWEXE_DTLS _SFR_MEM8(0x0A88) -#define AWEXE_DTHS _SFR_MEM8(0x0A89) -#define AWEXE_DTLSBUF _SFR_MEM8(0x0A8A) -#define AWEXE_DTHSBUF _SFR_MEM8(0x0A8B) -#define AWEXE_OUTOVEN _SFR_MEM8(0x0A8C) - -/* HIRES - High-Resolution Extension */ -#define HIRESE_CTRLA _SFR_MEM8(0x0A90) - -/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ -#define USARTE0_DATA _SFR_MEM8(0x0AA0) -#define USARTE0_STATUS _SFR_MEM8(0x0AA1) -#define USARTE0_CTRLA _SFR_MEM8(0x0AA3) -#define USARTE0_CTRLB _SFR_MEM8(0x0AA4) -#define USARTE0_CTRLC _SFR_MEM8(0x0AA5) -#define USARTE0_BAUDCTRLA _SFR_MEM8(0x0AA6) -#define USARTE0_BAUDCTRLB _SFR_MEM8(0x0AA7) - -/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ -#define USARTE1_DATA _SFR_MEM8(0x0AB0) -#define USARTE1_STATUS _SFR_MEM8(0x0AB1) -#define USARTE1_CTRLA _SFR_MEM8(0x0AB3) -#define USARTE1_CTRLB _SFR_MEM8(0x0AB4) -#define USARTE1_CTRLC _SFR_MEM8(0x0AB5) -#define USARTE1_BAUDCTRLA _SFR_MEM8(0x0AB6) -#define USARTE1_BAUDCTRLB _SFR_MEM8(0x0AB7) - -/* SPI - Serial Peripheral Interface */ -#define SPIE_CTRL _SFR_MEM8(0x0AC0) -#define SPIE_INTCTRL _SFR_MEM8(0x0AC1) -#define SPIE_STATUS _SFR_MEM8(0x0AC2) -#define SPIE_DATA _SFR_MEM8(0x0AC3) - -/* TC0 - 16-bit Timer/Counter 0 */ -#define TCF0_CTRLA _SFR_MEM8(0x0B00) -#define TCF0_CTRLB _SFR_MEM8(0x0B01) -#define TCF0_CTRLC _SFR_MEM8(0x0B02) -#define TCF0_CTRLD _SFR_MEM8(0x0B03) -#define TCF0_CTRLE _SFR_MEM8(0x0B04) -#define TCF0_INTCTRLA _SFR_MEM8(0x0B06) -#define TCF0_INTCTRLB _SFR_MEM8(0x0B07) -#define TCF0_CTRLFCLR _SFR_MEM8(0x0B08) -#define TCF0_CTRLFSET _SFR_MEM8(0x0B09) -#define TCF0_CTRLGCLR _SFR_MEM8(0x0B0A) -#define TCF0_CTRLGSET _SFR_MEM8(0x0B0B) -#define TCF0_INTFLAGS _SFR_MEM8(0x0B0C) -#define TCF0_TEMP _SFR_MEM8(0x0B0F) -#define TCF0_CNT _SFR_MEM16(0x0B20) -#define TCF0_PER _SFR_MEM16(0x0B26) -#define TCF0_CCA _SFR_MEM16(0x0B28) -#define TCF0_CCB _SFR_MEM16(0x0B2A) -#define TCF0_CCC _SFR_MEM16(0x0B2C) -#define TCF0_CCD _SFR_MEM16(0x0B2E) -#define TCF0_PERBUF _SFR_MEM16(0x0B36) -#define TCF0_CCABUF _SFR_MEM16(0x0B38) -#define TCF0_CCBBUF _SFR_MEM16(0x0B3A) -#define TCF0_CCCBUF _SFR_MEM16(0x0B3C) -#define TCF0_CCDBUF _SFR_MEM16(0x0B3E) - -/* TC2 - 16-bit Timer/Counter type 2 */ -#define TCF2_CTRLA _SFR_MEM8(0x0B00) -#define TCF2_CTRLB _SFR_MEM8(0x0B01) -#define TCF2_CTRLC _SFR_MEM8(0x0B02) -#define TCF2_CTRLE _SFR_MEM8(0x0B04) -#define TCF2_INTCTRLA _SFR_MEM8(0x0B06) -#define TCF2_INTCTRLB _SFR_MEM8(0x0B07) -#define TCF2_CTRLF _SFR_MEM8(0x0B09) -#define TCF2_INTFLAGS _SFR_MEM8(0x0B0C) -#define TCF2_LCNT _SFR_MEM8(0x0B20) -#define TCF2_HCNT _SFR_MEM8(0x0B21) -#define TCF2_LPER _SFR_MEM8(0x0B26) -#define TCF2_HPER _SFR_MEM8(0x0B27) -#define TCF2_LCMPA _SFR_MEM8(0x0B28) -#define TCF2_HCMPA _SFR_MEM8(0x0B29) -#define TCF2_LCMPB _SFR_MEM8(0x0B2A) -#define TCF2_HCMPB _SFR_MEM8(0x0B2B) -#define TCF2_LCMPC _SFR_MEM8(0x0B2C) -#define TCF2_HCMPC _SFR_MEM8(0x0B2D) -#define TCF2_LCMPD _SFR_MEM8(0x0B2E) -#define TCF2_HCMPD _SFR_MEM8(0x0B2F) - -/* TC1 - 16-bit Timer/Counter 1 */ -#define TCF1_CTRLA _SFR_MEM8(0x0B40) -#define TCF1_CTRLB _SFR_MEM8(0x0B41) -#define TCF1_CTRLC _SFR_MEM8(0x0B42) -#define TCF1_CTRLD _SFR_MEM8(0x0B43) -#define TCF1_CTRLE _SFR_MEM8(0x0B44) -#define TCF1_INTCTRLA _SFR_MEM8(0x0B46) -#define TCF1_INTCTRLB _SFR_MEM8(0x0B47) -#define TCF1_CTRLFCLR _SFR_MEM8(0x0B48) -#define TCF1_CTRLFSET _SFR_MEM8(0x0B49) -#define TCF1_CTRLGCLR _SFR_MEM8(0x0B4A) -#define TCF1_CTRLGSET _SFR_MEM8(0x0B4B) -#define TCF1_INTFLAGS _SFR_MEM8(0x0B4C) -#define TCF1_TEMP _SFR_MEM8(0x0B4F) -#define TCF1_CNT _SFR_MEM16(0x0B60) -#define TCF1_PER _SFR_MEM16(0x0B66) -#define TCF1_CCA _SFR_MEM16(0x0B68) -#define TCF1_CCB _SFR_MEM16(0x0B6A) -#define TCF1_PERBUF _SFR_MEM16(0x0B76) -#define TCF1_CCABUF _SFR_MEM16(0x0B78) -#define TCF1_CCBBUF _SFR_MEM16(0x0B7A) - -/* HIRES - High-Resolution Extension */ -#define HIRESF_CTRLA _SFR_MEM8(0x0B90) - -/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ -#define USARTF0_DATA _SFR_MEM8(0x0BA0) -#define USARTF0_STATUS _SFR_MEM8(0x0BA1) -#define USARTF0_CTRLA _SFR_MEM8(0x0BA3) -#define USARTF0_CTRLB _SFR_MEM8(0x0BA4) -#define USARTF0_CTRLC _SFR_MEM8(0x0BA5) -#define USARTF0_BAUDCTRLA _SFR_MEM8(0x0BA6) -#define USARTF0_BAUDCTRLB _SFR_MEM8(0x0BA7) - -/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ -#define USARTF1_DATA _SFR_MEM8(0x0BB0) -#define USARTF1_STATUS _SFR_MEM8(0x0BB1) -#define USARTF1_CTRLA _SFR_MEM8(0x0BB3) -#define USARTF1_CTRLB _SFR_MEM8(0x0BB4) -#define USARTF1_CTRLC _SFR_MEM8(0x0BB5) -#define USARTF1_BAUDCTRLA _SFR_MEM8(0x0BB6) -#define USARTF1_BAUDCTRLB _SFR_MEM8(0x0BB7) - -/* SPI - Serial Peripheral Interface */ -#define SPIF_CTRL _SFR_MEM8(0x0BC0) -#define SPIF_INTCTRL _SFR_MEM8(0x0BC1) -#define SPIF_STATUS _SFR_MEM8(0x0BC2) -#define SPIF_DATA _SFR_MEM8(0x0BC3) - - - -/*================== Bitfield Definitions ================== */ - -/* VPORT - Virtual Ports */ -/* VPORT.INTFLAGS bit masks and bit positions */ -#define VPORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ -#define VPORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ - -#define VPORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ -#define VPORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ - -/* XOCD - On-Chip Debug System */ -/* OCD.OCDR0 bit masks and bit positions */ -#define OCD_OCDRD_gm 0xFF /* OCDR Dirty group mask. */ -#define OCD_OCDRD_gp 0 /* OCDR Dirty group position. */ -#define OCD_OCDRD0_bm (1<<0) /* OCDR Dirty bit 0 mask. */ -#define OCD_OCDRD0_bp 0 /* OCDR Dirty bit 0 position. */ -#define OCD_OCDRD1_bm (1<<1) /* OCDR Dirty bit 1 mask. */ -#define OCD_OCDRD1_bp 1 /* OCDR Dirty bit 1 position. */ -#define OCD_OCDRD2_bm (1<<2) /* OCDR Dirty bit 2 mask. */ -#define OCD_OCDRD2_bp 2 /* OCDR Dirty bit 2 position. */ -#define OCD_OCDRD3_bm (1<<3) /* OCDR Dirty bit 3 mask. */ -#define OCD_OCDRD3_bp 3 /* OCDR Dirty bit 3 position. */ -#define OCD_OCDRD4_bm (1<<4) /* OCDR Dirty bit 4 mask. */ -#define OCD_OCDRD4_bp 4 /* OCDR Dirty bit 4 position. */ -#define OCD_OCDRD5_bm (1<<5) /* OCDR Dirty bit 5 mask. */ -#define OCD_OCDRD5_bp 5 /* OCDR Dirty bit 5 position. */ -#define OCD_OCDRD6_bm (1<<6) /* OCDR Dirty bit 6 mask. */ -#define OCD_OCDRD6_bp 6 /* OCDR Dirty bit 6 position. */ -#define OCD_OCDRD7_bm (1<<7) /* OCDR Dirty bit 7 mask. */ -#define OCD_OCDRD7_bp 7 /* OCDR Dirty bit 7 position. */ - -/* OCD.OCDR1 bit masks and bit positions */ -/* OCD_OCDRD Predefined. */ -/* OCD_OCDRD Predefined. */ - -/* CPU - CPU */ -/* CPU.CCP bit masks and bit positions */ -#define CPU_CCP_gm 0xFF /* CCP signature group mask. */ -#define CPU_CCP_gp 0 /* CCP signature group position. */ -#define CPU_CCP0_bm (1<<0) /* CCP signature bit 0 mask. */ -#define CPU_CCP0_bp 0 /* CCP signature bit 0 position. */ -#define CPU_CCP1_bm (1<<1) /* CCP signature bit 1 mask. */ -#define CPU_CCP1_bp 1 /* CCP signature bit 1 position. */ -#define CPU_CCP2_bm (1<<2) /* CCP signature bit 2 mask. */ -#define CPU_CCP2_bp 2 /* CCP signature bit 2 position. */ -#define CPU_CCP3_bm (1<<3) /* CCP signature bit 3 mask. */ -#define CPU_CCP3_bp 3 /* CCP signature bit 3 position. */ -#define CPU_CCP4_bm (1<<4) /* CCP signature bit 4 mask. */ -#define CPU_CCP4_bp 4 /* CCP signature bit 4 position. */ -#define CPU_CCP5_bm (1<<5) /* CCP signature bit 5 mask. */ -#define CPU_CCP5_bp 5 /* CCP signature bit 5 position. */ -#define CPU_CCP6_bm (1<<6) /* CCP signature bit 6 mask. */ -#define CPU_CCP6_bp 6 /* CCP signature bit 6 position. */ -#define CPU_CCP7_bm (1<<7) /* CCP signature bit 7 mask. */ -#define CPU_CCP7_bp 7 /* CCP signature bit 7 position. */ - -/* CPU.SREG bit masks and bit positions */ -#define CPU_I_bm 0x80 /* Global Interrupt Enable Flag bit mask. */ -#define CPU_I_bp 7 /* Global Interrupt Enable Flag bit position. */ - -#define CPU_T_bm 0x40 /* Transfer Bit bit mask. */ -#define CPU_T_bp 6 /* Transfer Bit bit position. */ - -#define CPU_H_bm 0x20 /* Half Carry Flag bit mask. */ -#define CPU_H_bp 5 /* Half Carry Flag bit position. */ - -#define CPU_S_bm 0x10 /* N Exclusive Or V Flag bit mask. */ -#define CPU_S_bp 4 /* N Exclusive Or V Flag bit position. */ - -#define CPU_V_bm 0x08 /* Two's Complement Overflow Flag bit mask. */ -#define CPU_V_bp 3 /* Two's Complement Overflow Flag bit position. */ - -#define CPU_N_bm 0x04 /* Negative Flag bit mask. */ -#define CPU_N_bp 2 /* Negative Flag bit position. */ - -#define CPU_Z_bm 0x02 /* Zero Flag bit mask. */ -#define CPU_Z_bp 1 /* Zero Flag bit position. */ - -#define CPU_C_bm 0x01 /* Carry Flag bit mask. */ -#define CPU_C_bp 0 /* Carry Flag bit position. */ - -/* CLK - Clock System */ -/* CLK.CTRL bit masks and bit positions */ -#define CLK_SCLKSEL_gm 0x07 /* System Clock Selection group mask. */ -#define CLK_SCLKSEL_gp 0 /* System Clock Selection group position. */ -#define CLK_SCLKSEL0_bm (1<<0) /* System Clock Selection bit 0 mask. */ -#define CLK_SCLKSEL0_bp 0 /* System Clock Selection bit 0 position. */ -#define CLK_SCLKSEL1_bm (1<<1) /* System Clock Selection bit 1 mask. */ -#define CLK_SCLKSEL1_bp 1 /* System Clock Selection bit 1 position. */ -#define CLK_SCLKSEL2_bm (1<<2) /* System Clock Selection bit 2 mask. */ -#define CLK_SCLKSEL2_bp 2 /* System Clock Selection bit 2 position. */ - -/* CLK.PSCTRL bit masks and bit positions */ -#define CLK_PSADIV_gm 0x7C /* Prescaler A Division Factor group mask. */ -#define CLK_PSADIV_gp 2 /* Prescaler A Division Factor group position. */ -#define CLK_PSADIV0_bm (1<<2) /* Prescaler A Division Factor bit 0 mask. */ -#define CLK_PSADIV0_bp 2 /* Prescaler A Division Factor bit 0 position. */ -#define CLK_PSADIV1_bm (1<<3) /* Prescaler A Division Factor bit 1 mask. */ -#define CLK_PSADIV1_bp 3 /* Prescaler A Division Factor bit 1 position. */ -#define CLK_PSADIV2_bm (1<<4) /* Prescaler A Division Factor bit 2 mask. */ -#define CLK_PSADIV2_bp 4 /* Prescaler A Division Factor bit 2 position. */ -#define CLK_PSADIV3_bm (1<<5) /* Prescaler A Division Factor bit 3 mask. */ -#define CLK_PSADIV3_bp 5 /* Prescaler A Division Factor bit 3 position. */ -#define CLK_PSADIV4_bm (1<<6) /* Prescaler A Division Factor bit 4 mask. */ -#define CLK_PSADIV4_bp 6 /* Prescaler A Division Factor bit 4 position. */ - -#define CLK_PSBCDIV_gm 0x03 /* Prescaler B and C Division factor group mask. */ -#define CLK_PSBCDIV_gp 0 /* Prescaler B and C Division factor group position. */ -#define CLK_PSBCDIV0_bm (1<<0) /* Prescaler B and C Division factor bit 0 mask. */ -#define CLK_PSBCDIV0_bp 0 /* Prescaler B and C Division factor bit 0 position. */ -#define CLK_PSBCDIV1_bm (1<<1) /* Prescaler B and C Division factor bit 1 mask. */ -#define CLK_PSBCDIV1_bp 1 /* Prescaler B and C Division factor bit 1 position. */ - -/* CLK.LOCK bit masks and bit positions */ -#define CLK_LOCK_bm 0x01 /* Clock System Lock bit mask. */ -#define CLK_LOCK_bp 0 /* Clock System Lock bit position. */ - -/* CLK.RTCCTRL bit masks and bit positions */ -#define CLK_RTCSRC_gm 0x0E /* Clock Source group mask. */ -#define CLK_RTCSRC_gp 1 /* Clock Source group position. */ -#define CLK_RTCSRC0_bm (1<<1) /* Clock Source bit 0 mask. */ -#define CLK_RTCSRC0_bp 1 /* Clock Source bit 0 position. */ -#define CLK_RTCSRC1_bm (1<<2) /* Clock Source bit 1 mask. */ -#define CLK_RTCSRC1_bp 2 /* Clock Source bit 1 position. */ -#define CLK_RTCSRC2_bm (1<<3) /* Clock Source bit 2 mask. */ -#define CLK_RTCSRC2_bp 3 /* Clock Source bit 2 position. */ - -#define CLK_RTCEN_bm 0x01 /* Clock Source Enable bit mask. */ -#define CLK_RTCEN_bp 0 /* Clock Source Enable bit position. */ - -/* CLK.USBCTRL bit masks and bit positions */ -#define CLK_USBPSDIV_gm 0x38 /* Prescaler Division Factor group mask. */ -#define CLK_USBPSDIV_gp 3 /* Prescaler Division Factor group position. */ -#define CLK_USBPSDIV0_bm (1<<3) /* Prescaler Division Factor bit 0 mask. */ -#define CLK_USBPSDIV0_bp 3 /* Prescaler Division Factor bit 0 position. */ -#define CLK_USBPSDIV1_bm (1<<4) /* Prescaler Division Factor bit 1 mask. */ -#define CLK_USBPSDIV1_bp 4 /* Prescaler Division Factor bit 1 position. */ -#define CLK_USBPSDIV2_bm (1<<5) /* Prescaler Division Factor bit 2 mask. */ -#define CLK_USBPSDIV2_bp 5 /* Prescaler Division Factor bit 2 position. */ - -#define CLK_USBSRC_gm 0x06 /* Clock Source group mask. */ -#define CLK_USBSRC_gp 1 /* Clock Source group position. */ -#define CLK_USBSRC0_bm (1<<1) /* Clock Source bit 0 mask. */ -#define CLK_USBSRC0_bp 1 /* Clock Source bit 0 position. */ -#define CLK_USBSRC1_bm (1<<2) /* Clock Source bit 1 mask. */ -#define CLK_USBSRC1_bp 2 /* Clock Source bit 1 position. */ - -#define CLK_USBSEN_bm 0x01 /* Clock Source Enable bit mask. */ -#define CLK_USBSEN_bp 0 /* Clock Source Enable bit position. */ - -/* PR.PRGEN bit masks and bit positions */ -#define PR_USB_bm 0x40 /* USB bit mask. */ -#define PR_USB_bp 6 /* USB bit position. */ - -#define PR_AES_bm 0x10 /* AES bit mask. */ -#define PR_AES_bp 4 /* AES bit position. */ - -#define PR_EBI_bm 0x08 /* External Bus Interface bit mask. */ -#define PR_EBI_bp 3 /* External Bus Interface bit position. */ - -#define PR_RTC_bm 0x04 /* Real-time Counter bit mask. */ -#define PR_RTC_bp 2 /* Real-time Counter bit position. */ - -#define PR_EVSYS_bm 0x02 /* Event System bit mask. */ -#define PR_EVSYS_bp 1 /* Event System bit position. */ - -#define PR_DMA_bm 0x01 /* DMA-Controller bit mask. */ -#define PR_DMA_bp 0 /* DMA-Controller bit position. */ - -/* PR.PRPA bit masks and bit positions */ -#define PR_DAC_bm 0x04 /* Port A DAC bit mask. */ -#define PR_DAC_bp 2 /* Port A DAC bit position. */ - -#define PR_ADC_bm 0x02 /* Port A ADC bit mask. */ -#define PR_ADC_bp 1 /* Port A ADC bit position. */ - -#define PR_AC_bm 0x01 /* Port A Analog Comparator bit mask. */ -#define PR_AC_bp 0 /* Port A Analog Comparator bit position. */ - -/* PR.PRPB bit masks and bit positions */ -/* PR_DAC Predefined. */ -/* PR_DAC Predefined. */ - -/* PR_ADC Predefined. */ -/* PR_ADC Predefined. */ - -/* PR_AC Predefined. */ -/* PR_AC Predefined. */ - -/* PR.PRPC bit masks and bit positions */ -#define PR_TWI_bm 0x40 /* Port C Two-wire Interface bit mask. */ -#define PR_TWI_bp 6 /* Port C Two-wire Interface bit position. */ - -#define PR_USART1_bm 0x20 /* Port C USART1 bit mask. */ -#define PR_USART1_bp 5 /* Port C USART1 bit position. */ - -#define PR_USART0_bm 0x10 /* Port C USART0 bit mask. */ -#define PR_USART0_bp 4 /* Port C USART0 bit position. */ - -#define PR_SPI_bm 0x08 /* Port C SPI bit mask. */ -#define PR_SPI_bp 3 /* Port C SPI bit position. */ - -#define PR_HIRES_bm 0x04 /* Port C AWEX bit mask. */ -#define PR_HIRES_bp 2 /* Port C AWEX bit position. */ - -#define PR_TC1_bm 0x02 /* Port C Timer/Counter1 bit mask. */ -#define PR_TC1_bp 1 /* Port C Timer/Counter1 bit position. */ - -#define PR_TC0_bm 0x01 /* Port C Timer/Counter0 bit mask. */ -#define PR_TC0_bp 0 /* Port C Timer/Counter0 bit position. */ - -/* PR.PRPD bit masks and bit positions */ -/* PR_TWI Predefined. */ -/* PR_TWI Predefined. */ - -/* PR_USART1 Predefined. */ -/* PR_USART1 Predefined. */ - -/* PR_USART0 Predefined. */ -/* PR_USART0 Predefined. */ - -/* PR_SPI Predefined. */ -/* PR_SPI Predefined. */ - -/* PR_HIRES Predefined. */ -/* PR_HIRES Predefined. */ - -/* PR_TC1 Predefined. */ -/* PR_TC1 Predefined. */ - -/* PR_TC0 Predefined. */ -/* PR_TC0 Predefined. */ - -/* PR.PRPE bit masks and bit positions */ -/* PR_TWI Predefined. */ -/* PR_TWI Predefined. */ - -/* PR_USART1 Predefined. */ -/* PR_USART1 Predefined. */ - -/* PR_USART0 Predefined. */ -/* PR_USART0 Predefined. */ - -/* PR_SPI Predefined. */ -/* PR_SPI Predefined. */ - -/* PR_HIRES Predefined. */ -/* PR_HIRES Predefined. */ - -/* PR_TC1 Predefined. */ -/* PR_TC1 Predefined. */ - -/* PR_TC0 Predefined. */ -/* PR_TC0 Predefined. */ - -/* PR.PRPF bit masks and bit positions */ -/* PR_TWI Predefined. */ -/* PR_TWI Predefined. */ - -/* PR_USART1 Predefined. */ -/* PR_USART1 Predefined. */ - -/* PR_USART0 Predefined. */ -/* PR_USART0 Predefined. */ - -/* PR_SPI Predefined. */ -/* PR_SPI Predefined. */ - -/* PR_HIRES Predefined. */ -/* PR_HIRES Predefined. */ - -/* PR_TC1 Predefined. */ -/* PR_TC1 Predefined. */ - -/* PR_TC0 Predefined. */ -/* PR_TC0 Predefined. */ - -/* SLEEP - Sleep Controller */ -/* SLEEP.CTRL bit masks and bit positions */ -#define SLEEP_SMODE_gm 0x0E /* Sleep Mode group mask. */ -#define SLEEP_SMODE_gp 1 /* Sleep Mode group position. */ -#define SLEEP_SMODE0_bm (1<<1) /* Sleep Mode bit 0 mask. */ -#define SLEEP_SMODE0_bp 1 /* Sleep Mode bit 0 position. */ -#define SLEEP_SMODE1_bm (1<<2) /* Sleep Mode bit 1 mask. */ -#define SLEEP_SMODE1_bp 2 /* Sleep Mode bit 1 position. */ -#define SLEEP_SMODE2_bm (1<<3) /* Sleep Mode bit 2 mask. */ -#define SLEEP_SMODE2_bp 3 /* Sleep Mode bit 2 position. */ - -#define SLEEP_SEN_bm 0x01 /* Sleep Enable bit mask. */ -#define SLEEP_SEN_bp 0 /* Sleep Enable bit position. */ - -/* OSC - Oscillator */ -/* OSC.CTRL bit masks and bit positions */ -#define OSC_PLLEN_bm 0x10 /* PLL Enable bit mask. */ -#define OSC_PLLEN_bp 4 /* PLL Enable bit position. */ - -#define OSC_XOSCEN_bm 0x08 /* External Oscillator Enable bit mask. */ -#define OSC_XOSCEN_bp 3 /* External Oscillator Enable bit position. */ - -#define OSC_RC32KEN_bm 0x04 /* Internal 32.768 kHz RC Oscillator Enable bit mask. */ -#define OSC_RC32KEN_bp 2 /* Internal 32.768 kHz RC Oscillator Enable bit position. */ - -#define OSC_RC32MEN_bm 0x02 /* Internal 32 MHz RC Oscillator Enable bit mask. */ -#define OSC_RC32MEN_bp 1 /* Internal 32 MHz RC Oscillator Enable bit position. */ - -#define OSC_RC2MEN_bm 0x01 /* Internal 2 MHz RC Oscillator Enable bit mask. */ -#define OSC_RC2MEN_bp 0 /* Internal 2 MHz RC Oscillator Enable bit position. */ - -/* OSC.STATUS bit masks and bit positions */ -#define OSC_PLLRDY_bm 0x10 /* PLL Ready bit mask. */ -#define OSC_PLLRDY_bp 4 /* PLL Ready bit position. */ - -#define OSC_XOSCRDY_bm 0x08 /* External Oscillator Ready bit mask. */ -#define OSC_XOSCRDY_bp 3 /* External Oscillator Ready bit position. */ - -#define OSC_RC32KRDY_bm 0x04 /* Internal 32.768 kHz RC Oscillator Ready bit mask. */ -#define OSC_RC32KRDY_bp 2 /* Internal 32.768 kHz RC Oscillator Ready bit position. */ - -#define OSC_RC32MRDY_bm 0x02 /* Internal 32 MHz RC Oscillator Ready bit mask. */ -#define OSC_RC32MRDY_bp 1 /* Internal 32 MHz RC Oscillator Ready bit position. */ - -#define OSC_RC2MRDY_bm 0x01 /* Internal 2 MHz RC Oscillator Ready bit mask. */ -#define OSC_RC2MRDY_bp 0 /* Internal 2 MHz RC Oscillator Ready bit position. */ - -/* OSC.XOSCCTRL bit masks and bit positions */ -#define OSC_FRQRANGE_gm 0xC0 /* Frequency Range group mask. */ -#define OSC_FRQRANGE_gp 6 /* Frequency Range group position. */ -#define OSC_FRQRANGE0_bm (1<<6) /* Frequency Range bit 0 mask. */ -#define OSC_FRQRANGE0_bp 6 /* Frequency Range bit 0 position. */ -#define OSC_FRQRANGE1_bm (1<<7) /* Frequency Range bit 1 mask. */ -#define OSC_FRQRANGE1_bp 7 /* Frequency Range bit 1 position. */ - -#define OSC_X32KLPM_bm 0x20 /* 32.768 kHz XTAL OSC Low-power Mode bit mask. */ -#define OSC_X32KLPM_bp 5 /* 32.768 kHz XTAL OSC Low-power Mode bit position. */ - -#define OSC_XOSCPWR_bm 0x10 /* 16 MHz Crystal Oscillator High Power mode bit mask. */ -#define OSC_XOSCPWR_bp 4 /* 16 MHz Crystal Oscillator High Power mode bit position. */ - -#define OSC_XOSCSEL_gm 0x0F /* External Oscillator Selection and Startup Time group mask. */ -#define OSC_XOSCSEL_gp 0 /* External Oscillator Selection and Startup Time group position. */ -#define OSC_XOSCSEL0_bm (1<<0) /* External Oscillator Selection and Startup Time bit 0 mask. */ -#define OSC_XOSCSEL0_bp 0 /* External Oscillator Selection and Startup Time bit 0 position. */ -#define OSC_XOSCSEL1_bm (1<<1) /* External Oscillator Selection and Startup Time bit 1 mask. */ -#define OSC_XOSCSEL1_bp 1 /* External Oscillator Selection and Startup Time bit 1 position. */ -#define OSC_XOSCSEL2_bm (1<<2) /* External Oscillator Selection and Startup Time bit 2 mask. */ -#define OSC_XOSCSEL2_bp 2 /* External Oscillator Selection and Startup Time bit 2 position. */ -#define OSC_XOSCSEL3_bm (1<<3) /* External Oscillator Selection and Startup Time bit 3 mask. */ -#define OSC_XOSCSEL3_bp 3 /* External Oscillator Selection and Startup Time bit 3 position. */ - -/* OSC.XOSCFAIL bit masks and bit positions */ -#define OSC_PLLFDIF_bm 0x08 /* PLL Failure Detection Interrupt Flag bit mask. */ -#define OSC_PLLFDIF_bp 3 /* PLL Failure Detection Interrupt Flag bit position. */ - -#define OSC_PLLFDEN_bm 0x04 /* PLL Failure Detection Enable bit mask. */ -#define OSC_PLLFDEN_bp 2 /* PLL Failure Detection Enable bit position. */ - -#define OSC_XOSCFDIF_bm 0x02 /* XOSC Failure Detection Interrupt Flag bit mask. */ -#define OSC_XOSCFDIF_bp 1 /* XOSC Failure Detection Interrupt Flag bit position. */ - -#define OSC_XOSCFDEN_bm 0x01 /* XOSC Failure Detection Enable bit mask. */ -#define OSC_XOSCFDEN_bp 0 /* XOSC Failure Detection Enable bit position. */ - -/* OSC.PLLCTRL bit masks and bit positions */ -#define OSC_PLLSRC_gm 0xC0 /* Clock Source group mask. */ -#define OSC_PLLSRC_gp 6 /* Clock Source group position. */ -#define OSC_PLLSRC0_bm (1<<6) /* Clock Source bit 0 mask. */ -#define OSC_PLLSRC0_bp 6 /* Clock Source bit 0 position. */ -#define OSC_PLLSRC1_bm (1<<7) /* Clock Source bit 1 mask. */ -#define OSC_PLLSRC1_bp 7 /* Clock Source bit 1 position. */ - -#define OSC_PLLDIV_bm 0x20 /* Divide by 2 bit mask. */ -#define OSC_PLLDIV_bp 5 /* Divide by 2 bit position. */ - -#define OSC_PLLFAC_gm 0x1F /* Multiplication Factor group mask. */ -#define OSC_PLLFAC_gp 0 /* Multiplication Factor group position. */ -#define OSC_PLLFAC0_bm (1<<0) /* Multiplication Factor bit 0 mask. */ -#define OSC_PLLFAC0_bp 0 /* Multiplication Factor bit 0 position. */ -#define OSC_PLLFAC1_bm (1<<1) /* Multiplication Factor bit 1 mask. */ -#define OSC_PLLFAC1_bp 1 /* Multiplication Factor bit 1 position. */ -#define OSC_PLLFAC2_bm (1<<2) /* Multiplication Factor bit 2 mask. */ -#define OSC_PLLFAC2_bp 2 /* Multiplication Factor bit 2 position. */ -#define OSC_PLLFAC3_bm (1<<3) /* Multiplication Factor bit 3 mask. */ -#define OSC_PLLFAC3_bp 3 /* Multiplication Factor bit 3 position. */ -#define OSC_PLLFAC4_bm (1<<4) /* Multiplication Factor bit 4 mask. */ -#define OSC_PLLFAC4_bp 4 /* Multiplication Factor bit 4 position. */ - -/* OSC.DFLLCTRL bit masks and bit positions */ -#define OSC_RC32MCREF_gm 0x06 /* 32 MHz DFLL Calibration Reference group mask. */ -#define OSC_RC32MCREF_gp 1 /* 32 MHz DFLL Calibration Reference group position. */ -#define OSC_RC32MCREF0_bm (1<<1) /* 32 MHz DFLL Calibration Reference bit 0 mask. */ -#define OSC_RC32MCREF0_bp 1 /* 32 MHz DFLL Calibration Reference bit 0 position. */ -#define OSC_RC32MCREF1_bm (1<<2) /* 32 MHz DFLL Calibration Reference bit 1 mask. */ -#define OSC_RC32MCREF1_bp 2 /* 32 MHz DFLL Calibration Reference bit 1 position. */ - -#define OSC_RC2MCREF_bm 0x01 /* 2 MHz DFLL Calibration Reference bit mask. */ -#define OSC_RC2MCREF_bp 0 /* 2 MHz DFLL Calibration Reference bit position. */ - -/* DFLL - DFLL */ -/* DFLL.CTRL bit masks and bit positions */ -#define DFLL_ENABLE_bm 0x01 /* DFLL Enable bit mask. */ -#define DFLL_ENABLE_bp 0 /* DFLL Enable bit position. */ - -/* DFLL.CALA bit masks and bit positions */ -#define DFLL_CALL_gm 0x7F /* DFLL Calibration Value A group mask. */ -#define DFLL_CALL_gp 0 /* DFLL Calibration Value A group position. */ -#define DFLL_CALL0_bm (1<<0) /* DFLL Calibration Value A bit 0 mask. */ -#define DFLL_CALL0_bp 0 /* DFLL Calibration Value A bit 0 position. */ -#define DFLL_CALL1_bm (1<<1) /* DFLL Calibration Value A bit 1 mask. */ -#define DFLL_CALL1_bp 1 /* DFLL Calibration Value A bit 1 position. */ -#define DFLL_CALL2_bm (1<<2) /* DFLL Calibration Value A bit 2 mask. */ -#define DFLL_CALL2_bp 2 /* DFLL Calibration Value A bit 2 position. */ -#define DFLL_CALL3_bm (1<<3) /* DFLL Calibration Value A bit 3 mask. */ -#define DFLL_CALL3_bp 3 /* DFLL Calibration Value A bit 3 position. */ -#define DFLL_CALL4_bm (1<<4) /* DFLL Calibration Value A bit 4 mask. */ -#define DFLL_CALL4_bp 4 /* DFLL Calibration Value A bit 4 position. */ -#define DFLL_CALL5_bm (1<<5) /* DFLL Calibration Value A bit 5 mask. */ -#define DFLL_CALL5_bp 5 /* DFLL Calibration Value A bit 5 position. */ -#define DFLL_CALL6_bm (1<<6) /* DFLL Calibration Value A bit 6 mask. */ -#define DFLL_CALL6_bp 6 /* DFLL Calibration Value A bit 6 position. */ - -/* DFLL.CALB bit masks and bit positions */ -#define DFLL_CALH_gm 0x3F /* DFLL Calibration Value B group mask. */ -#define DFLL_CALH_gp 0 /* DFLL Calibration Value B group position. */ -#define DFLL_CALH0_bm (1<<0) /* DFLL Calibration Value B bit 0 mask. */ -#define DFLL_CALH0_bp 0 /* DFLL Calibration Value B bit 0 position. */ -#define DFLL_CALH1_bm (1<<1) /* DFLL Calibration Value B bit 1 mask. */ -#define DFLL_CALH1_bp 1 /* DFLL Calibration Value B bit 1 position. */ -#define DFLL_CALH2_bm (1<<2) /* DFLL Calibration Value B bit 2 mask. */ -#define DFLL_CALH2_bp 2 /* DFLL Calibration Value B bit 2 position. */ -#define DFLL_CALH3_bm (1<<3) /* DFLL Calibration Value B bit 3 mask. */ -#define DFLL_CALH3_bp 3 /* DFLL Calibration Value B bit 3 position. */ -#define DFLL_CALH4_bm (1<<4) /* DFLL Calibration Value B bit 4 mask. */ -#define DFLL_CALH4_bp 4 /* DFLL Calibration Value B bit 4 position. */ -#define DFLL_CALH5_bm (1<<5) /* DFLL Calibration Value B bit 5 mask. */ -#define DFLL_CALH5_bp 5 /* DFLL Calibration Value B bit 5 position. */ - -/* RST - Reset */ -/* RST.STATUS bit masks and bit positions */ -#define RST_SDRF_bm 0x40 /* Spike Detection Reset Flag bit mask. */ -#define RST_SDRF_bp 6 /* Spike Detection Reset Flag bit position. */ - -#define RST_SRF_bm 0x20 /* Software Reset Flag bit mask. */ -#define RST_SRF_bp 5 /* Software Reset Flag bit position. */ - -#define RST_PDIRF_bm 0x10 /* Programming and Debug Interface Interface Reset Flag bit mask. */ -#define RST_PDIRF_bp 4 /* Programming and Debug Interface Interface Reset Flag bit position. */ - -#define RST_WDRF_bm 0x08 /* Watchdog Reset Flag bit mask. */ -#define RST_WDRF_bp 3 /* Watchdog Reset Flag bit position. */ - -#define RST_BORF_bm 0x04 /* Brown-out Reset Flag bit mask. */ -#define RST_BORF_bp 2 /* Brown-out Reset Flag bit position. */ - -#define RST_EXTRF_bm 0x02 /* External Reset Flag bit mask. */ -#define RST_EXTRF_bp 1 /* External Reset Flag bit position. */ - -#define RST_PORF_bm 0x01 /* Power-on Reset Flag bit mask. */ -#define RST_PORF_bp 0 /* Power-on Reset Flag bit position. */ - -/* RST.CTRL bit masks and bit positions */ -#define RST_SWRST_bm 0x01 /* Software Reset bit mask. */ -#define RST_SWRST_bp 0 /* Software Reset bit position. */ - -/* WDT - Watch-Dog Timer */ -/* WDT.CTRL bit masks and bit positions */ -#define WDT_PER_gm 0x3C /* Period group mask. */ -#define WDT_PER_gp 2 /* Period group position. */ -#define WDT_PER0_bm (1<<2) /* Period bit 0 mask. */ -#define WDT_PER0_bp 2 /* Period bit 0 position. */ -#define WDT_PER1_bm (1<<3) /* Period bit 1 mask. */ -#define WDT_PER1_bp 3 /* Period bit 1 position. */ -#define WDT_PER2_bm (1<<4) /* Period bit 2 mask. */ -#define WDT_PER2_bp 4 /* Period bit 2 position. */ -#define WDT_PER3_bm (1<<5) /* Period bit 3 mask. */ -#define WDT_PER3_bp 5 /* Period bit 3 position. */ - -#define WDT_ENABLE_bm 0x02 /* Enable bit mask. */ -#define WDT_ENABLE_bp 1 /* Enable bit position. */ - -#define WDT_CEN_bm 0x01 /* Change Enable bit mask. */ -#define WDT_CEN_bp 0 /* Change Enable bit position. */ - -/* WDT.WINCTRL bit masks and bit positions */ -#define WDT_WPER_gm 0x3C /* Windowed Mode Period group mask. */ -#define WDT_WPER_gp 2 /* Windowed Mode Period group position. */ -#define WDT_WPER0_bm (1<<2) /* Windowed Mode Period bit 0 mask. */ -#define WDT_WPER0_bp 2 /* Windowed Mode Period bit 0 position. */ -#define WDT_WPER1_bm (1<<3) /* Windowed Mode Period bit 1 mask. */ -#define WDT_WPER1_bp 3 /* Windowed Mode Period bit 1 position. */ -#define WDT_WPER2_bm (1<<4) /* Windowed Mode Period bit 2 mask. */ -#define WDT_WPER2_bp 4 /* Windowed Mode Period bit 2 position. */ -#define WDT_WPER3_bm (1<<5) /* Windowed Mode Period bit 3 mask. */ -#define WDT_WPER3_bp 5 /* Windowed Mode Period bit 3 position. */ - -#define WDT_WEN_bm 0x02 /* Windowed Mode Enable bit mask. */ -#define WDT_WEN_bp 1 /* Windowed Mode Enable bit position. */ - -#define WDT_WCEN_bm 0x01 /* Windowed Mode Change Enable bit mask. */ -#define WDT_WCEN_bp 0 /* Windowed Mode Change Enable bit position. */ - -/* WDT.STATUS bit masks and bit positions */ -#define WDT_SYNCBUSY_bm 0x01 /* Syncronization busy bit mask. */ -#define WDT_SYNCBUSY_bp 0 /* Syncronization busy bit position. */ - -/* MCU - MCU Control */ -/* MCU.MCUCR bit masks and bit positions */ -#define MCU_JTAGD_bm 0x01 /* JTAG Disable bit mask. */ -#define MCU_JTAGD_bp 0 /* JTAG Disable bit position. */ - -/* MCU.ANAINIT bit masks and bit positions */ -#define MCU_STARTUPDLYB_gm 0x0C /* Analog startup delay Port B group mask. */ -#define MCU_STARTUPDLYB_gp 2 /* Analog startup delay Port B group position. */ -#define MCU_STARTUPDLYB0_bm (1<<2) /* Analog startup delay Port B bit 0 mask. */ -#define MCU_STARTUPDLYB0_bp 2 /* Analog startup delay Port B bit 0 position. */ -#define MCU_STARTUPDLYB1_bm (1<<3) /* Analog startup delay Port B bit 1 mask. */ -#define MCU_STARTUPDLYB1_bp 3 /* Analog startup delay Port B bit 1 position. */ - -#define MCU_STARTUPDLYA_gm 0x03 /* Analog startup delay Port A group mask. */ -#define MCU_STARTUPDLYA_gp 0 /* Analog startup delay Port A group position. */ -#define MCU_STARTUPDLYA0_bm (1<<0) /* Analog startup delay Port A bit 0 mask. */ -#define MCU_STARTUPDLYA0_bp 0 /* Analog startup delay Port A bit 0 position. */ -#define MCU_STARTUPDLYA1_bm (1<<1) /* Analog startup delay Port A bit 1 mask. */ -#define MCU_STARTUPDLYA1_bp 1 /* Analog startup delay Port A bit 1 position. */ - -/* MCU.EVSYSLOCK bit masks and bit positions */ -#define MCU_EVSYS1LOCK_bm 0x10 /* Event Channel 4-7 Lock bit mask. */ -#define MCU_EVSYS1LOCK_bp 4 /* Event Channel 4-7 Lock bit position. */ - -#define MCU_EVSYS0LOCK_bm 0x01 /* Event Channel 0-3 Lock bit mask. */ -#define MCU_EVSYS0LOCK_bp 0 /* Event Channel 0-3 Lock bit position. */ - -/* MCU.AWEXLOCK bit masks and bit positions */ -#define MCU_AWEXFLOCK_bm 0x08 /* AWeX on T/C F0 Lock bit mask. */ -#define MCU_AWEXFLOCK_bp 3 /* AWeX on T/C F0 Lock bit position. */ - -#define MCU_AWEXELOCK_bm 0x04 /* AWeX on T/C E0 Lock bit mask. */ -#define MCU_AWEXELOCK_bp 2 /* AWeX on T/C E0 Lock bit position. */ - -#define MCU_AWEXDLOCK_bm 0x02 /* AWeX on T/C D0 Lock bit mask. */ -#define MCU_AWEXDLOCK_bp 1 /* AWeX on T/C D0 Lock bit position. */ - -#define MCU_AWEXCLOCK_bm 0x01 /* AWeX on T/C C0 Lock bit mask. */ -#define MCU_AWEXCLOCK_bp 0 /* AWeX on T/C C0 Lock bit position. */ - -/* PMIC - Programmable Multi-level Interrupt Controller */ -/* PMIC.STATUS bit masks and bit positions */ -#define PMIC_NMIEX_bm 0x80 /* Non-maskable Interrupt Executing bit mask. */ -#define PMIC_NMIEX_bp 7 /* Non-maskable Interrupt Executing bit position. */ - -#define PMIC_HILVLEX_bm 0x04 /* High Level Interrupt Executing bit mask. */ -#define PMIC_HILVLEX_bp 2 /* High Level Interrupt Executing bit position. */ - -#define PMIC_MEDLVLEX_bm 0x02 /* Medium Level Interrupt Executing bit mask. */ -#define PMIC_MEDLVLEX_bp 1 /* Medium Level Interrupt Executing bit position. */ - -#define PMIC_LOLVLEX_bm 0x01 /* Low Level Interrupt Executing bit mask. */ -#define PMIC_LOLVLEX_bp 0 /* Low Level Interrupt Executing bit position. */ - -/* PMIC.INTPRI bit masks and bit positions */ -#define PMIC_INTPRI_gm 0xFF /* Interrupt Priority group mask. */ -#define PMIC_INTPRI_gp 0 /* Interrupt Priority group position. */ -#define PMIC_INTPRI0_bm (1<<0) /* Interrupt Priority bit 0 mask. */ -#define PMIC_INTPRI0_bp 0 /* Interrupt Priority bit 0 position. */ -#define PMIC_INTPRI1_bm (1<<1) /* Interrupt Priority bit 1 mask. */ -#define PMIC_INTPRI1_bp 1 /* Interrupt Priority bit 1 position. */ -#define PMIC_INTPRI2_bm (1<<2) /* Interrupt Priority bit 2 mask. */ -#define PMIC_INTPRI2_bp 2 /* Interrupt Priority bit 2 position. */ -#define PMIC_INTPRI3_bm (1<<3) /* Interrupt Priority bit 3 mask. */ -#define PMIC_INTPRI3_bp 3 /* Interrupt Priority bit 3 position. */ -#define PMIC_INTPRI4_bm (1<<4) /* Interrupt Priority bit 4 mask. */ -#define PMIC_INTPRI4_bp 4 /* Interrupt Priority bit 4 position. */ -#define PMIC_INTPRI5_bm (1<<5) /* Interrupt Priority bit 5 mask. */ -#define PMIC_INTPRI5_bp 5 /* Interrupt Priority bit 5 position. */ -#define PMIC_INTPRI6_bm (1<<6) /* Interrupt Priority bit 6 mask. */ -#define PMIC_INTPRI6_bp 6 /* Interrupt Priority bit 6 position. */ -#define PMIC_INTPRI7_bm (1<<7) /* Interrupt Priority bit 7 mask. */ -#define PMIC_INTPRI7_bp 7 /* Interrupt Priority bit 7 position. */ - -/* PMIC.CTRL bit masks and bit positions */ -#define PMIC_RREN_bm 0x80 /* Round-Robin Priority Enable bit mask. */ -#define PMIC_RREN_bp 7 /* Round-Robin Priority Enable bit position. */ - -#define PMIC_IVSEL_bm 0x40 /* Interrupt Vector Select bit mask. */ -#define PMIC_IVSEL_bp 6 /* Interrupt Vector Select bit position. */ - -#define PMIC_HILVLEN_bm 0x04 /* High Level Enable bit mask. */ -#define PMIC_HILVLEN_bp 2 /* High Level Enable bit position. */ - -#define PMIC_MEDLVLEN_bm 0x02 /* Medium Level Enable bit mask. */ -#define PMIC_MEDLVLEN_bp 1 /* Medium Level Enable bit position. */ - -#define PMIC_LOLVLEN_bm 0x01 /* Low Level Enable bit mask. */ -#define PMIC_LOLVLEN_bp 0 /* Low Level Enable bit position. */ - -/* PORTCFG - Port Configuration */ -/* PORTCFG.VPCTRLA bit masks and bit positions */ -#define PORTCFG_VP1MAP_gm 0xF0 /* Virtual Port 1 Mapping group mask. */ -#define PORTCFG_VP1MAP_gp 4 /* Virtual Port 1 Mapping group position. */ -#define PORTCFG_VP1MAP0_bm (1<<4) /* Virtual Port 1 Mapping bit 0 mask. */ -#define PORTCFG_VP1MAP0_bp 4 /* Virtual Port 1 Mapping bit 0 position. */ -#define PORTCFG_VP1MAP1_bm (1<<5) /* Virtual Port 1 Mapping bit 1 mask. */ -#define PORTCFG_VP1MAP1_bp 5 /* Virtual Port 1 Mapping bit 1 position. */ -#define PORTCFG_VP1MAP2_bm (1<<6) /* Virtual Port 1 Mapping bit 2 mask. */ -#define PORTCFG_VP1MAP2_bp 6 /* Virtual Port 1 Mapping bit 2 position. */ -#define PORTCFG_VP1MAP3_bm (1<<7) /* Virtual Port 1 Mapping bit 3 mask. */ -#define PORTCFG_VP1MAP3_bp 7 /* Virtual Port 1 Mapping bit 3 position. */ - -#define PORTCFG_VP0MAP_gm 0x0F /* Virtual Port 0 Mapping group mask. */ -#define PORTCFG_VP0MAP_gp 0 /* Virtual Port 0 Mapping group position. */ -#define PORTCFG_VP0MAP0_bm (1<<0) /* Virtual Port 0 Mapping bit 0 mask. */ -#define PORTCFG_VP0MAP0_bp 0 /* Virtual Port 0 Mapping bit 0 position. */ -#define PORTCFG_VP0MAP1_bm (1<<1) /* Virtual Port 0 Mapping bit 1 mask. */ -#define PORTCFG_VP0MAP1_bp 1 /* Virtual Port 0 Mapping bit 1 position. */ -#define PORTCFG_VP0MAP2_bm (1<<2) /* Virtual Port 0 Mapping bit 2 mask. */ -#define PORTCFG_VP0MAP2_bp 2 /* Virtual Port 0 Mapping bit 2 position. */ -#define PORTCFG_VP0MAP3_bm (1<<3) /* Virtual Port 0 Mapping bit 3 mask. */ -#define PORTCFG_VP0MAP3_bp 3 /* Virtual Port 0 Mapping bit 3 position. */ - -/* PORTCFG.VPCTRLB bit masks and bit positions */ -#define PORTCFG_VP3MAP_gm 0xF0 /* Virtual Port 3 Mapping group mask. */ -#define PORTCFG_VP3MAP_gp 4 /* Virtual Port 3 Mapping group position. */ -#define PORTCFG_VP3MAP0_bm (1<<4) /* Virtual Port 3 Mapping bit 0 mask. */ -#define PORTCFG_VP3MAP0_bp 4 /* Virtual Port 3 Mapping bit 0 position. */ -#define PORTCFG_VP3MAP1_bm (1<<5) /* Virtual Port 3 Mapping bit 1 mask. */ -#define PORTCFG_VP3MAP1_bp 5 /* Virtual Port 3 Mapping bit 1 position. */ -#define PORTCFG_VP3MAP2_bm (1<<6) /* Virtual Port 3 Mapping bit 2 mask. */ -#define PORTCFG_VP3MAP2_bp 6 /* Virtual Port 3 Mapping bit 2 position. */ -#define PORTCFG_VP3MAP3_bm (1<<7) /* Virtual Port 3 Mapping bit 3 mask. */ -#define PORTCFG_VP3MAP3_bp 7 /* Virtual Port 3 Mapping bit 3 position. */ - -#define PORTCFG_VP2MAP_gm 0x0F /* Virtual Port 2 Mapping group mask. */ -#define PORTCFG_VP2MAP_gp 0 /* Virtual Port 2 Mapping group position. */ -#define PORTCFG_VP2MAP0_bm (1<<0) /* Virtual Port 2 Mapping bit 0 mask. */ -#define PORTCFG_VP2MAP0_bp 0 /* Virtual Port 2 Mapping bit 0 position. */ -#define PORTCFG_VP2MAP1_bm (1<<1) /* Virtual Port 2 Mapping bit 1 mask. */ -#define PORTCFG_VP2MAP1_bp 1 /* Virtual Port 2 Mapping bit 1 position. */ -#define PORTCFG_VP2MAP2_bm (1<<2) /* Virtual Port 2 Mapping bit 2 mask. */ -#define PORTCFG_VP2MAP2_bp 2 /* Virtual Port 2 Mapping bit 2 position. */ -#define PORTCFG_VP2MAP3_bm (1<<3) /* Virtual Port 2 Mapping bit 3 mask. */ -#define PORTCFG_VP2MAP3_bp 3 /* Virtual Port 2 Mapping bit 3 position. */ - -/* PORTCFG.CLKEVOUT bit masks and bit positions */ -#define PORTCFG_CLKOUT_gm 0x03 /* Peripheral Clock Output Port group mask. */ -#define PORTCFG_CLKOUT_gp 0 /* Peripheral Clock Output Port group position. */ -#define PORTCFG_CLKOUT0_bm (1<<0) /* Peripheral Clock Output Port bit 0 mask. */ -#define PORTCFG_CLKOUT0_bp 0 /* Peripheral Clock Output Port bit 0 position. */ -#define PORTCFG_CLKOUT1_bm (1<<1) /* Peripheral Clock Output Port bit 1 mask. */ -#define PORTCFG_CLKOUT1_bp 1 /* Peripheral Clock Output Port bit 1 position. */ - -#define PORTCFG_CLKOUTSEL_gm 0x0C /* Peripheral Clock Output Select group mask. */ -#define PORTCFG_CLKOUTSEL_gp 2 /* Peripheral Clock Output Select group position. */ -#define PORTCFG_CLKOUTSEL0_bm (1<<2) /* Peripheral Clock Output Select bit 0 mask. */ -#define PORTCFG_CLKOUTSEL0_bp 2 /* Peripheral Clock Output Select bit 0 position. */ -#define PORTCFG_CLKOUTSEL1_bm (1<<3) /* Peripheral Clock Output Select bit 1 mask. */ -#define PORTCFG_CLKOUTSEL1_bp 3 /* Peripheral Clock Output Select bit 1 position. */ - -#define PORTCFG_EVOUT_gm 0x30 /* Event Output Port group mask. */ -#define PORTCFG_EVOUT_gp 4 /* Event Output Port group position. */ -#define PORTCFG_EVOUT0_bm (1<<4) /* Event Output Port bit 0 mask. */ -#define PORTCFG_EVOUT0_bp 4 /* Event Output Port bit 0 position. */ -#define PORTCFG_EVOUT1_bm (1<<5) /* Event Output Port bit 1 mask. */ -#define PORTCFG_EVOUT1_bp 5 /* Event Output Port bit 1 position. */ - -#define PORTCFG_RTCOUT_bm 0x40 /* RTC Clock Output bit mask. */ -#define PORTCFG_RTCOUT_bp 6 /* RTC Clock Output bit position. */ - -#define PORTCFG_CLKEVPIN_bm 0x80 /* Peripheral Clock and Event Output pin Select bit mask. */ -#define PORTCFG_CLKEVPIN_bp 7 /* Peripheral Clock and Event Output pin Select bit position. */ - -/* PORTCFG.EBIOUT bit masks and bit positions */ -#define PORTCFG_EBICSOUT_gm 0x03 /* EBI Chip Select Output group mask. */ -#define PORTCFG_EBICSOUT_gp 0 /* EBI Chip Select Output group position. */ -#define PORTCFG_EBICSOUT0_bm (1<<0) /* EBI Chip Select Output bit 0 mask. */ -#define PORTCFG_EBICSOUT0_bp 0 /* EBI Chip Select Output bit 0 position. */ -#define PORTCFG_EBICSOUT1_bm (1<<1) /* EBI Chip Select Output bit 1 mask. */ -#define PORTCFG_EBICSOUT1_bp 1 /* EBI Chip Select Output bit 1 position. */ - -#define PORTCFG_EBIADROUT_gm 0x0C /* EBI Address Output group mask. */ -#define PORTCFG_EBIADROUT_gp 2 /* EBI Address Output group position. */ -#define PORTCFG_EBIADROUT0_bm (1<<2) /* EBI Address Output bit 0 mask. */ -#define PORTCFG_EBIADROUT0_bp 2 /* EBI Address Output bit 0 position. */ -#define PORTCFG_EBIADROUT1_bm (1<<3) /* EBI Address Output bit 1 mask. */ -#define PORTCFG_EBIADROUT1_bp 3 /* EBI Address Output bit 1 position. */ - -/* PORTCFG.EVOUTSEL bit masks and bit positions */ -#define PORTCFG_EVOUTSEL_gm 0x07 /* Event Output Select group mask. */ -#define PORTCFG_EVOUTSEL_gp 0 /* Event Output Select group position. */ -#define PORTCFG_EVOUTSEL0_bm (1<<0) /* Event Output Select bit 0 mask. */ -#define PORTCFG_EVOUTSEL0_bp 0 /* Event Output Select bit 0 position. */ -#define PORTCFG_EVOUTSEL1_bm (1<<1) /* Event Output Select bit 1 mask. */ -#define PORTCFG_EVOUTSEL1_bp 1 /* Event Output Select bit 1 position. */ -#define PORTCFG_EVOUTSEL2_bm (1<<2) /* Event Output Select bit 2 mask. */ -#define PORTCFG_EVOUTSEL2_bp 2 /* Event Output Select bit 2 position. */ - -/* AES - AES Module */ -/* AES.CTRL bit masks and bit positions */ -#define AES_START_bm 0x80 /* Start/Run bit mask. */ -#define AES_START_bp 7 /* Start/Run bit position. */ - -#define AES_AUTO_bm 0x40 /* Auto Start Trigger bit mask. */ -#define AES_AUTO_bp 6 /* Auto Start Trigger bit position. */ - -#define AES_RESET_bm 0x20 /* AES Software Reset bit mask. */ -#define AES_RESET_bp 5 /* AES Software Reset bit position. */ - -#define AES_DECRYPT_bm 0x10 /* Decryption / Direction bit mask. */ -#define AES_DECRYPT_bp 4 /* Decryption / Direction bit position. */ - -#define AES_XOR_bm 0x04 /* State XOR Load Enable bit mask. */ -#define AES_XOR_bp 2 /* State XOR Load Enable bit position. */ - -/* AES.STATUS bit masks and bit positions */ -#define AES_ERROR_bm 0x80 /* AES Error bit mask. */ -#define AES_ERROR_bp 7 /* AES Error bit position. */ - -#define AES_SRIF_bm 0x01 /* State Ready Interrupt Flag bit mask. */ -#define AES_SRIF_bp 0 /* State Ready Interrupt Flag bit position. */ - -/* AES.INTCTRL bit masks and bit positions */ -#define AES_INTLVL_gm 0x03 /* Interrupt level group mask. */ -#define AES_INTLVL_gp 0 /* Interrupt level group position. */ -#define AES_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */ -#define AES_INTLVL0_bp 0 /* Interrupt level bit 0 position. */ -#define AES_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */ -#define AES_INTLVL1_bp 1 /* Interrupt level bit 1 position. */ - -/* CRC - Cyclic Redundancy Checker */ -/* CRC.CTRL bit masks and bit positions */ -#define CRC_RESET_gm 0xC0 /* Reset group mask. */ -#define CRC_RESET_gp 6 /* Reset group position. */ -#define CRC_RESET0_bm (1<<6) /* Reset bit 0 mask. */ -#define CRC_RESET0_bp 6 /* Reset bit 0 position. */ -#define CRC_RESET1_bm (1<<7) /* Reset bit 1 mask. */ -#define CRC_RESET1_bp 7 /* Reset bit 1 position. */ - -#define CRC_CRC32_bm 0x20 /* CRC Mode bit mask. */ -#define CRC_CRC32_bp 5 /* CRC Mode bit position. */ - -#define CRC_SOURCE_gm 0x0F /* Input Source group mask. */ -#define CRC_SOURCE_gp 0 /* Input Source group position. */ -#define CRC_SOURCE0_bm (1<<0) /* Input Source bit 0 mask. */ -#define CRC_SOURCE0_bp 0 /* Input Source bit 0 position. */ -#define CRC_SOURCE1_bm (1<<1) /* Input Source bit 1 mask. */ -#define CRC_SOURCE1_bp 1 /* Input Source bit 1 position. */ -#define CRC_SOURCE2_bm (1<<2) /* Input Source bit 2 mask. */ -#define CRC_SOURCE2_bp 2 /* Input Source bit 2 position. */ -#define CRC_SOURCE3_bm (1<<3) /* Input Source bit 3 mask. */ -#define CRC_SOURCE3_bp 3 /* Input Source bit 3 position. */ - -/* CRC.STATUS bit masks and bit positions */ -#define CRC_ZERO_bm 0x02 /* Zero detection bit mask. */ -#define CRC_ZERO_bp 1 /* Zero detection bit position. */ - -#define CRC_BUSY_bm 0x01 /* Busy bit mask. */ -#define CRC_BUSY_bp 0 /* Busy bit position. */ - -/* DMA - DMA Controller */ -/* DMA_CH.CTRLA bit masks and bit positions */ -#define DMA_CH_ENABLE_bm 0x80 /* Channel Enable bit mask. */ -#define DMA_CH_ENABLE_bp 7 /* Channel Enable bit position. */ - -#define DMA_CH_RESET_bm 0x40 /* Channel Software Reset bit mask. */ -#define DMA_CH_RESET_bp 6 /* Channel Software Reset bit position. */ - -#define DMA_CH_REPEAT_bm 0x20 /* Channel Repeat Mode bit mask. */ -#define DMA_CH_REPEAT_bp 5 /* Channel Repeat Mode bit position. */ - -#define DMA_CH_TRFREQ_bm 0x10 /* Channel Transfer Request bit mask. */ -#define DMA_CH_TRFREQ_bp 4 /* Channel Transfer Request bit position. */ - -#define DMA_CH_SINGLE_bm 0x04 /* Channel Single Shot Data Transfer bit mask. */ -#define DMA_CH_SINGLE_bp 2 /* Channel Single Shot Data Transfer bit position. */ - -#define DMA_CH_BURSTLEN_gm 0x03 /* Channel Transfer Mode group mask. */ -#define DMA_CH_BURSTLEN_gp 0 /* Channel Transfer Mode group position. */ -#define DMA_CH_BURSTLEN0_bm (1<<0) /* Channel Transfer Mode bit 0 mask. */ -#define DMA_CH_BURSTLEN0_bp 0 /* Channel Transfer Mode bit 0 position. */ -#define DMA_CH_BURSTLEN1_bm (1<<1) /* Channel Transfer Mode bit 1 mask. */ -#define DMA_CH_BURSTLEN1_bp 1 /* Channel Transfer Mode bit 1 position. */ - -/* DMA_CH.CTRLB bit masks and bit positions */ -#define DMA_CH_CHBUSY_bm 0x80 /* Block Transfer Busy bit mask. */ -#define DMA_CH_CHBUSY_bp 7 /* Block Transfer Busy bit position. */ - -#define DMA_CH_CHPEND_bm 0x40 /* Block Transfer Pending bit mask. */ -#define DMA_CH_CHPEND_bp 6 /* Block Transfer Pending bit position. */ - -#define DMA_CH_ERRIF_bm 0x20 /* Block Transfer Error Interrupt Flag bit mask. */ -#define DMA_CH_ERRIF_bp 5 /* Block Transfer Error Interrupt Flag bit position. */ - -#define DMA_CH_TRNIF_bm 0x10 /* Transaction Complete Interrup Flag bit mask. */ -#define DMA_CH_TRNIF_bp 4 /* Transaction Complete Interrup Flag bit position. */ - -#define DMA_CH_ERRINTLVL_gm 0x0C /* Transfer Error Interrupt Level group mask. */ -#define DMA_CH_ERRINTLVL_gp 2 /* Transfer Error Interrupt Level group position. */ -#define DMA_CH_ERRINTLVL0_bm (1<<2) /* Transfer Error Interrupt Level bit 0 mask. */ -#define DMA_CH_ERRINTLVL0_bp 2 /* Transfer Error Interrupt Level bit 0 position. */ -#define DMA_CH_ERRINTLVL1_bm (1<<3) /* Transfer Error Interrupt Level bit 1 mask. */ -#define DMA_CH_ERRINTLVL1_bp 3 /* Transfer Error Interrupt Level bit 1 position. */ - -#define DMA_CH_TRNINTLVL_gm 0x03 /* Transaction Complete Interrupt Level group mask. */ -#define DMA_CH_TRNINTLVL_gp 0 /* Transaction Complete Interrupt Level group position. */ -#define DMA_CH_TRNINTLVL0_bm (1<<0) /* Transaction Complete Interrupt Level bit 0 mask. */ -#define DMA_CH_TRNINTLVL0_bp 0 /* Transaction Complete Interrupt Level bit 0 position. */ -#define DMA_CH_TRNINTLVL1_bm (1<<1) /* Transaction Complete Interrupt Level bit 1 mask. */ -#define DMA_CH_TRNINTLVL1_bp 1 /* Transaction Complete Interrupt Level bit 1 position. */ - -/* DMA_CH.ADDRCTRL bit masks and bit positions */ -#define DMA_CH_SRCRELOAD_gm 0xC0 /* Channel Source Address Reload group mask. */ -#define DMA_CH_SRCRELOAD_gp 6 /* Channel Source Address Reload group position. */ -#define DMA_CH_SRCRELOAD0_bm (1<<6) /* Channel Source Address Reload bit 0 mask. */ -#define DMA_CH_SRCRELOAD0_bp 6 /* Channel Source Address Reload bit 0 position. */ -#define DMA_CH_SRCRELOAD1_bm (1<<7) /* Channel Source Address Reload bit 1 mask. */ -#define DMA_CH_SRCRELOAD1_bp 7 /* Channel Source Address Reload bit 1 position. */ - -#define DMA_CH_SRCDIR_gm 0x30 /* Channel Source Address Mode group mask. */ -#define DMA_CH_SRCDIR_gp 4 /* Channel Source Address Mode group position. */ -#define DMA_CH_SRCDIR0_bm (1<<4) /* Channel Source Address Mode bit 0 mask. */ -#define DMA_CH_SRCDIR0_bp 4 /* Channel Source Address Mode bit 0 position. */ -#define DMA_CH_SRCDIR1_bm (1<<5) /* Channel Source Address Mode bit 1 mask. */ -#define DMA_CH_SRCDIR1_bp 5 /* Channel Source Address Mode bit 1 position. */ - -#define DMA_CH_DESTRELOAD_gm 0x0C /* Channel Destination Address Reload group mask. */ -#define DMA_CH_DESTRELOAD_gp 2 /* Channel Destination Address Reload group position. */ -#define DMA_CH_DESTRELOAD0_bm (1<<2) /* Channel Destination Address Reload bit 0 mask. */ -#define DMA_CH_DESTRELOAD0_bp 2 /* Channel Destination Address Reload bit 0 position. */ -#define DMA_CH_DESTRELOAD1_bm (1<<3) /* Channel Destination Address Reload bit 1 mask. */ -#define DMA_CH_DESTRELOAD1_bp 3 /* Channel Destination Address Reload bit 1 position. */ - -#define DMA_CH_DESTDIR_gm 0x03 /* Channel Destination Address Mode group mask. */ -#define DMA_CH_DESTDIR_gp 0 /* Channel Destination Address Mode group position. */ -#define DMA_CH_DESTDIR0_bm (1<<0) /* Channel Destination Address Mode bit 0 mask. */ -#define DMA_CH_DESTDIR0_bp 0 /* Channel Destination Address Mode bit 0 position. */ -#define DMA_CH_DESTDIR1_bm (1<<1) /* Channel Destination Address Mode bit 1 mask. */ -#define DMA_CH_DESTDIR1_bp 1 /* Channel Destination Address Mode bit 1 position. */ - -/* DMA_CH.TRIGSRC bit masks and bit positions */ -#define DMA_CH_TRIGSRC_gm 0xFF /* Channel Trigger Source group mask. */ -#define DMA_CH_TRIGSRC_gp 0 /* Channel Trigger Source group position. */ -#define DMA_CH_TRIGSRC0_bm (1<<0) /* Channel Trigger Source bit 0 mask. */ -#define DMA_CH_TRIGSRC0_bp 0 /* Channel Trigger Source bit 0 position. */ -#define DMA_CH_TRIGSRC1_bm (1<<1) /* Channel Trigger Source bit 1 mask. */ -#define DMA_CH_TRIGSRC1_bp 1 /* Channel Trigger Source bit 1 position. */ -#define DMA_CH_TRIGSRC2_bm (1<<2) /* Channel Trigger Source bit 2 mask. */ -#define DMA_CH_TRIGSRC2_bp 2 /* Channel Trigger Source bit 2 position. */ -#define DMA_CH_TRIGSRC3_bm (1<<3) /* Channel Trigger Source bit 3 mask. */ -#define DMA_CH_TRIGSRC3_bp 3 /* Channel Trigger Source bit 3 position. */ -#define DMA_CH_TRIGSRC4_bm (1<<4) /* Channel Trigger Source bit 4 mask. */ -#define DMA_CH_TRIGSRC4_bp 4 /* Channel Trigger Source bit 4 position. */ -#define DMA_CH_TRIGSRC5_bm (1<<5) /* Channel Trigger Source bit 5 mask. */ -#define DMA_CH_TRIGSRC5_bp 5 /* Channel Trigger Source bit 5 position. */ -#define DMA_CH_TRIGSRC6_bm (1<<6) /* Channel Trigger Source bit 6 mask. */ -#define DMA_CH_TRIGSRC6_bp 6 /* Channel Trigger Source bit 6 position. */ -#define DMA_CH_TRIGSRC7_bm (1<<7) /* Channel Trigger Source bit 7 mask. */ -#define DMA_CH_TRIGSRC7_bp 7 /* Channel Trigger Source bit 7 position. */ - -/* DMA.CTRL bit masks and bit positions */ -#define DMA_ENABLE_bm 0x80 /* Enable bit mask. */ -#define DMA_ENABLE_bp 7 /* Enable bit position. */ - -#define DMA_RESET_bm 0x40 /* Software Reset bit mask. */ -#define DMA_RESET_bp 6 /* Software Reset bit position. */ - -#define DMA_DBUFMODE_gm 0x0C /* Double Buffering Mode group mask. */ -#define DMA_DBUFMODE_gp 2 /* Double Buffering Mode group position. */ -#define DMA_DBUFMODE0_bm (1<<2) /* Double Buffering Mode bit 0 mask. */ -#define DMA_DBUFMODE0_bp 2 /* Double Buffering Mode bit 0 position. */ -#define DMA_DBUFMODE1_bm (1<<3) /* Double Buffering Mode bit 1 mask. */ -#define DMA_DBUFMODE1_bp 3 /* Double Buffering Mode bit 1 position. */ - -#define DMA_PRIMODE_gm 0x03 /* Channel Priority Mode group mask. */ -#define DMA_PRIMODE_gp 0 /* Channel Priority Mode group position. */ -#define DMA_PRIMODE0_bm (1<<0) /* Channel Priority Mode bit 0 mask. */ -#define DMA_PRIMODE0_bp 0 /* Channel Priority Mode bit 0 position. */ -#define DMA_PRIMODE1_bm (1<<1) /* Channel Priority Mode bit 1 mask. */ -#define DMA_PRIMODE1_bp 1 /* Channel Priority Mode bit 1 position. */ - -/* DMA.INTFLAGS bit masks and bit positions */ -#define DMA_CH3ERRIF_bm 0x80 /* Channel 3 Block Transfer Error Interrupt Flag bit mask. */ -#define DMA_CH3ERRIF_bp 7 /* Channel 3 Block Transfer Error Interrupt Flag bit position. */ - -#define DMA_CH2ERRIF_bm 0x40 /* Channel 2 Block Transfer Error Interrupt Flag bit mask. */ -#define DMA_CH2ERRIF_bp 6 /* Channel 2 Block Transfer Error Interrupt Flag bit position. */ - -#define DMA_CH1ERRIF_bm 0x20 /* Channel 1 Block Transfer Error Interrupt Flag bit mask. */ -#define DMA_CH1ERRIF_bp 5 /* Channel 1 Block Transfer Error Interrupt Flag bit position. */ - -#define DMA_CH0ERRIF_bm 0x10 /* Channel 0 Block Transfer Error Interrupt Flag bit mask. */ -#define DMA_CH0ERRIF_bp 4 /* Channel 0 Block Transfer Error Interrupt Flag bit position. */ - -#define DMA_CH3TRNIF_bm 0x08 /* Channel 3 Transaction Complete Interrupt Flag bit mask. */ -#define DMA_CH3TRNIF_bp 3 /* Channel 3 Transaction Complete Interrupt Flag bit position. */ - -#define DMA_CH2TRNIF_bm 0x04 /* Channel 2 Transaction Complete Interrupt Flag bit mask. */ -#define DMA_CH2TRNIF_bp 2 /* Channel 2 Transaction Complete Interrupt Flag bit position. */ - -#define DMA_CH1TRNIF_bm 0x02 /* Channel 1 Transaction Complete Interrupt Flag bit mask. */ -#define DMA_CH1TRNIF_bp 1 /* Channel 1 Transaction Complete Interrupt Flag bit position. */ - -#define DMA_CH0TRNIF_bm 0x01 /* Channel 0 Transaction Complete Interrupt Flag bit mask. */ -#define DMA_CH0TRNIF_bp 0 /* Channel 0 Transaction Complete Interrupt Flag bit position. */ - -/* DMA.STATUS bit masks and bit positions */ -#define DMA_CH3BUSY_bm 0x80 /* Channel 3 Block Transfer Busy bit mask. */ -#define DMA_CH3BUSY_bp 7 /* Channel 3 Block Transfer Busy bit position. */ - -#define DMA_CH2BUSY_bm 0x40 /* Channel 2 Block Transfer Busy bit mask. */ -#define DMA_CH2BUSY_bp 6 /* Channel 2 Block Transfer Busy bit position. */ - -#define DMA_CH1BUSY_bm 0x20 /* Channel 1 Block Transfer Busy bit mask. */ -#define DMA_CH1BUSY_bp 5 /* Channel 1 Block Transfer Busy bit position. */ - -#define DMA_CH0BUSY_bm 0x10 /* Channel 0 Block Transfer Busy bit mask. */ -#define DMA_CH0BUSY_bp 4 /* Channel 0 Block Transfer Busy bit position. */ - -#define DMA_CH3PEND_bm 0x08 /* Channel 3 Block Transfer Pending bit mask. */ -#define DMA_CH3PEND_bp 3 /* Channel 3 Block Transfer Pending bit position. */ - -#define DMA_CH2PEND_bm 0x04 /* Channel 2 Block Transfer Pending bit mask. */ -#define DMA_CH2PEND_bp 2 /* Channel 2 Block Transfer Pending bit position. */ - -#define DMA_CH1PEND_bm 0x02 /* Channel 1 Block Transfer Pending bit mask. */ -#define DMA_CH1PEND_bp 1 /* Channel 1 Block Transfer Pending bit position. */ - -#define DMA_CH0PEND_bm 0x01 /* Channel 0 Block Transfer Pending bit mask. */ -#define DMA_CH0PEND_bp 0 /* Channel 0 Block Transfer Pending bit position. */ - -/* EVSYS - Event System */ -/* EVSYS.CH0MUX bit masks and bit positions */ -#define EVSYS_CHMUX_gm 0xFF /* Event Channel 0 Multiplexer group mask. */ -#define EVSYS_CHMUX_gp 0 /* Event Channel 0 Multiplexer group position. */ -#define EVSYS_CHMUX0_bm (1<<0) /* Event Channel 0 Multiplexer bit 0 mask. */ -#define EVSYS_CHMUX0_bp 0 /* Event Channel 0 Multiplexer bit 0 position. */ -#define EVSYS_CHMUX1_bm (1<<1) /* Event Channel 0 Multiplexer bit 1 mask. */ -#define EVSYS_CHMUX1_bp 1 /* Event Channel 0 Multiplexer bit 1 position. */ -#define EVSYS_CHMUX2_bm (1<<2) /* Event Channel 0 Multiplexer bit 2 mask. */ -#define EVSYS_CHMUX2_bp 2 /* Event Channel 0 Multiplexer bit 2 position. */ -#define EVSYS_CHMUX3_bm (1<<3) /* Event Channel 0 Multiplexer bit 3 mask. */ -#define EVSYS_CHMUX3_bp 3 /* Event Channel 0 Multiplexer bit 3 position. */ -#define EVSYS_CHMUX4_bm (1<<4) /* Event Channel 0 Multiplexer bit 4 mask. */ -#define EVSYS_CHMUX4_bp 4 /* Event Channel 0 Multiplexer bit 4 position. */ -#define EVSYS_CHMUX5_bm (1<<5) /* Event Channel 0 Multiplexer bit 5 mask. */ -#define EVSYS_CHMUX5_bp 5 /* Event Channel 0 Multiplexer bit 5 position. */ -#define EVSYS_CHMUX6_bm (1<<6) /* Event Channel 0 Multiplexer bit 6 mask. */ -#define EVSYS_CHMUX6_bp 6 /* Event Channel 0 Multiplexer bit 6 position. */ -#define EVSYS_CHMUX7_bm (1<<7) /* Event Channel 0 Multiplexer bit 7 mask. */ -#define EVSYS_CHMUX7_bp 7 /* Event Channel 0 Multiplexer bit 7 position. */ - -/* EVSYS.CH1MUX bit masks and bit positions */ -/* EVSYS_CHMUX Predefined. */ -/* EVSYS_CHMUX Predefined. */ - -/* EVSYS.CH2MUX bit masks and bit positions */ -/* EVSYS_CHMUX Predefined. */ -/* EVSYS_CHMUX Predefined. */ - -/* EVSYS.CH3MUX bit masks and bit positions */ -/* EVSYS_CHMUX Predefined. */ -/* EVSYS_CHMUX Predefined. */ - -/* EVSYS.CH4MUX bit masks and bit positions */ -/* EVSYS_CHMUX Predefined. */ -/* EVSYS_CHMUX Predefined. */ - -/* EVSYS.CH5MUX bit masks and bit positions */ -/* EVSYS_CHMUX Predefined. */ -/* EVSYS_CHMUX Predefined. */ - -/* EVSYS.CH6MUX bit masks and bit positions */ -/* EVSYS_CHMUX Predefined. */ -/* EVSYS_CHMUX Predefined. */ - -/* EVSYS.CH7MUX bit masks and bit positions */ -/* EVSYS_CHMUX Predefined. */ -/* EVSYS_CHMUX Predefined. */ - -/* EVSYS.CH0CTRL bit masks and bit positions */ -#define EVSYS_QDIRM_gm 0x60 /* Quadrature Decoder Index Recognition Mode group mask. */ -#define EVSYS_QDIRM_gp 5 /* Quadrature Decoder Index Recognition Mode group position. */ -#define EVSYS_QDIRM0_bm (1<<5) /* Quadrature Decoder Index Recognition Mode bit 0 mask. */ -#define EVSYS_QDIRM0_bp 5 /* Quadrature Decoder Index Recognition Mode bit 0 position. */ -#define EVSYS_QDIRM1_bm (1<<6) /* Quadrature Decoder Index Recognition Mode bit 1 mask. */ -#define EVSYS_QDIRM1_bp 6 /* Quadrature Decoder Index Recognition Mode bit 1 position. */ - -#define EVSYS_QDIEN_bm 0x10 /* Quadrature Decoder Index Enable bit mask. */ -#define EVSYS_QDIEN_bp 4 /* Quadrature Decoder Index Enable bit position. */ - -#define EVSYS_QDEN_bm 0x08 /* Quadrature Decoder Enable bit mask. */ -#define EVSYS_QDEN_bp 3 /* Quadrature Decoder Enable bit position. */ - -#define EVSYS_DIGFILT_gm 0x07 /* Digital Filter group mask. */ -#define EVSYS_DIGFILT_gp 0 /* Digital Filter group position. */ -#define EVSYS_DIGFILT0_bm (1<<0) /* Digital Filter bit 0 mask. */ -#define EVSYS_DIGFILT0_bp 0 /* Digital Filter bit 0 position. */ -#define EVSYS_DIGFILT1_bm (1<<1) /* Digital Filter bit 1 mask. */ -#define EVSYS_DIGFILT1_bp 1 /* Digital Filter bit 1 position. */ -#define EVSYS_DIGFILT2_bm (1<<2) /* Digital Filter bit 2 mask. */ -#define EVSYS_DIGFILT2_bp 2 /* Digital Filter bit 2 position. */ - -/* EVSYS.CH1CTRL bit masks and bit positions */ -/* EVSYS_DIGFILT Predefined. */ -/* EVSYS_DIGFILT Predefined. */ - -/* EVSYS.CH2CTRL bit masks and bit positions */ -/* EVSYS_QDIRM Predefined. */ -/* EVSYS_QDIRM Predefined. */ - -/* EVSYS_QDIEN Predefined. */ -/* EVSYS_QDIEN Predefined. */ - -/* EVSYS_QDEN Predefined. */ -/* EVSYS_QDEN Predefined. */ - -/* EVSYS_DIGFILT Predefined. */ -/* EVSYS_DIGFILT Predefined. */ - -/* EVSYS.CH3CTRL bit masks and bit positions */ -/* EVSYS_DIGFILT Predefined. */ -/* EVSYS_DIGFILT Predefined. */ - -/* EVSYS.CH4CTRL bit masks and bit positions */ -/* EVSYS_QDIRM Predefined. */ -/* EVSYS_QDIRM Predefined. */ - -/* EVSYS_QDIEN Predefined. */ -/* EVSYS_QDIEN Predefined. */ - -/* EVSYS_QDEN Predefined. */ -/* EVSYS_QDEN Predefined. */ - -/* EVSYS_DIGFILT Predefined. */ -/* EVSYS_DIGFILT Predefined. */ - -/* EVSYS.CH5CTRL bit masks and bit positions */ -/* EVSYS_DIGFILT Predefined. */ -/* EVSYS_DIGFILT Predefined. */ - -/* EVSYS.CH6CTRL bit masks and bit positions */ -/* EVSYS_DIGFILT Predefined. */ -/* EVSYS_DIGFILT Predefined. */ - -/* EVSYS.CH7CTRL bit masks and bit positions */ -/* EVSYS_DIGFILT Predefined. */ -/* EVSYS_DIGFILT Predefined. */ - -/* NVM - Non Volatile Memory Controller */ -/* NVM.CMD bit masks and bit positions */ -#define NVM_CMD_gm 0x7F /* Command group mask. */ -#define NVM_CMD_gp 0 /* Command group position. */ -#define NVM_CMD0_bm (1<<0) /* Command bit 0 mask. */ -#define NVM_CMD0_bp 0 /* Command bit 0 position. */ -#define NVM_CMD1_bm (1<<1) /* Command bit 1 mask. */ -#define NVM_CMD1_bp 1 /* Command bit 1 position. */ -#define NVM_CMD2_bm (1<<2) /* Command bit 2 mask. */ -#define NVM_CMD2_bp 2 /* Command bit 2 position. */ -#define NVM_CMD3_bm (1<<3) /* Command bit 3 mask. */ -#define NVM_CMD3_bp 3 /* Command bit 3 position. */ -#define NVM_CMD4_bm (1<<4) /* Command bit 4 mask. */ -#define NVM_CMD4_bp 4 /* Command bit 4 position. */ -#define NVM_CMD5_bm (1<<5) /* Command bit 5 mask. */ -#define NVM_CMD5_bp 5 /* Command bit 5 position. */ -#define NVM_CMD6_bm (1<<6) /* Command bit 6 mask. */ -#define NVM_CMD6_bp 6 /* Command bit 6 position. */ - -/* NVM.CTRLA bit masks and bit positions */ -#define NVM_CMDEX_bm 0x01 /* Command Execute bit mask. */ -#define NVM_CMDEX_bp 0 /* Command Execute bit position. */ - -/* NVM.CTRLB bit masks and bit positions */ -#define NVM_EEMAPEN_bm 0x08 /* EEPROM Mapping Enable bit mask. */ -#define NVM_EEMAPEN_bp 3 /* EEPROM Mapping Enable bit position. */ - -#define NVM_FPRM_bm 0x04 /* Flash Power Reduction Enable bit mask. */ -#define NVM_FPRM_bp 2 /* Flash Power Reduction Enable bit position. */ - -#define NVM_EPRM_bm 0x02 /* EEPROM Power Reduction Enable bit mask. */ -#define NVM_EPRM_bp 1 /* EEPROM Power Reduction Enable bit position. */ - -#define NVM_SPMLOCK_bm 0x01 /* SPM Lock bit mask. */ -#define NVM_SPMLOCK_bp 0 /* SPM Lock bit position. */ - -/* NVM.INTCTRL bit masks and bit positions */ -#define NVM_SPMLVL_gm 0x0C /* SPM Interrupt Level group mask. */ -#define NVM_SPMLVL_gp 2 /* SPM Interrupt Level group position. */ -#define NVM_SPMLVL0_bm (1<<2) /* SPM Interrupt Level bit 0 mask. */ -#define NVM_SPMLVL0_bp 2 /* SPM Interrupt Level bit 0 position. */ -#define NVM_SPMLVL1_bm (1<<3) /* SPM Interrupt Level bit 1 mask. */ -#define NVM_SPMLVL1_bp 3 /* SPM Interrupt Level bit 1 position. */ - -#define NVM_EELVL_gm 0x03 /* EEPROM Interrupt Level group mask. */ -#define NVM_EELVL_gp 0 /* EEPROM Interrupt Level group position. */ -#define NVM_EELVL0_bm (1<<0) /* EEPROM Interrupt Level bit 0 mask. */ -#define NVM_EELVL0_bp 0 /* EEPROM Interrupt Level bit 0 position. */ -#define NVM_EELVL1_bm (1<<1) /* EEPROM Interrupt Level bit 1 mask. */ -#define NVM_EELVL1_bp 1 /* EEPROM Interrupt Level bit 1 position. */ - -/* NVM.STATUS bit masks and bit positions */ -#define NVM_NVMBUSY_bm 0x80 /* Non-volatile Memory Busy bit mask. */ -#define NVM_NVMBUSY_bp 7 /* Non-volatile Memory Busy bit position. */ - -#define NVM_FBUSY_bm 0x40 /* Flash Memory Busy bit mask. */ -#define NVM_FBUSY_bp 6 /* Flash Memory Busy bit position. */ - -#define NVM_EELOAD_bm 0x02 /* EEPROM Page Buffer Active Loading bit mask. */ -#define NVM_EELOAD_bp 1 /* EEPROM Page Buffer Active Loading bit position. */ - -#define NVM_FLOAD_bm 0x01 /* Flash Page Buffer Active Loading bit mask. */ -#define NVM_FLOAD_bp 0 /* Flash Page Buffer Active Loading bit position. */ - -/* NVM.LOCKBITS bit masks and bit positions */ -#define NVM_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ -#define NVM_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ -#define NVM_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ -#define NVM_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ -#define NVM_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ -#define NVM_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ - -#define NVM_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ -#define NVM_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ -#define NVM_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ -#define NVM_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ -#define NVM_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ -#define NVM_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ - -#define NVM_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ -#define NVM_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ -#define NVM_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ -#define NVM_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ -#define NVM_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ -#define NVM_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ - -#define NVM_LB_gm 0x03 /* Lock Bits group mask. */ -#define NVM_LB_gp 0 /* Lock Bits group position. */ -#define NVM_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ -#define NVM_LB0_bp 0 /* Lock Bits bit 0 position. */ -#define NVM_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ -#define NVM_LB1_bp 1 /* Lock Bits bit 1 position. */ - -/* ADC - Analog/Digital Converter */ -/* ADC_CH.CTRL bit masks and bit positions */ -#define ADC_CH_START_bm 0x80 /* Channel Start Conversion bit mask. */ -#define ADC_CH_START_bp 7 /* Channel Start Conversion bit position. */ - -#define ADC_CH_GAIN_gm 0x1C /* Gain Factor group mask. */ -#define ADC_CH_GAIN_gp 2 /* Gain Factor group position. */ -#define ADC_CH_GAIN0_bm (1<<2) /* Gain Factor bit 0 mask. */ -#define ADC_CH_GAIN0_bp 2 /* Gain Factor bit 0 position. */ -#define ADC_CH_GAIN1_bm (1<<3) /* Gain Factor bit 1 mask. */ -#define ADC_CH_GAIN1_bp 3 /* Gain Factor bit 1 position. */ -#define ADC_CH_GAIN2_bm (1<<4) /* Gain Factor bit 2 mask. */ -#define ADC_CH_GAIN2_bp 4 /* Gain Factor bit 2 position. */ - -#define ADC_CH_INPUTMODE_gm 0x03 /* Input Mode Select group mask. */ -#define ADC_CH_INPUTMODE_gp 0 /* Input Mode Select group position. */ -#define ADC_CH_INPUTMODE0_bm (1<<0) /* Input Mode Select bit 0 mask. */ -#define ADC_CH_INPUTMODE0_bp 0 /* Input Mode Select bit 0 position. */ -#define ADC_CH_INPUTMODE1_bm (1<<1) /* Input Mode Select bit 1 mask. */ -#define ADC_CH_INPUTMODE1_bp 1 /* Input Mode Select bit 1 position. */ - -/* ADC_CH.MUXCTRL bit masks and bit positions */ -#define ADC_CH_MUXPOS_gm 0x78 /* MUX selection on Positive ADC input group mask. */ -#define ADC_CH_MUXPOS_gp 3 /* MUX selection on Positive ADC input group position. */ -#define ADC_CH_MUXPOS0_bm (1<<3) /* MUX selection on Positive ADC input bit 0 mask. */ -#define ADC_CH_MUXPOS0_bp 3 /* MUX selection on Positive ADC input bit 0 position. */ -#define ADC_CH_MUXPOS1_bm (1<<4) /* MUX selection on Positive ADC input bit 1 mask. */ -#define ADC_CH_MUXPOS1_bp 4 /* MUX selection on Positive ADC input bit 1 position. */ -#define ADC_CH_MUXPOS2_bm (1<<5) /* MUX selection on Positive ADC input bit 2 mask. */ -#define ADC_CH_MUXPOS2_bp 5 /* MUX selection on Positive ADC input bit 2 position. */ -#define ADC_CH_MUXPOS3_bm (1<<6) /* MUX selection on Positive ADC input bit 3 mask. */ -#define ADC_CH_MUXPOS3_bp 6 /* MUX selection on Positive ADC input bit 3 position. */ - -#define ADC_CH_MUXINT_gm 0x78 /* MUX selection on Internal ADC input group mask. */ -#define ADC_CH_MUXINT_gp 3 /* MUX selection on Internal ADC input group position. */ -#define ADC_CH_MUXINT0_bm (1<<3) /* MUX selection on Internal ADC input bit 0 mask. */ -#define ADC_CH_MUXINT0_bp 3 /* MUX selection on Internal ADC input bit 0 position. */ -#define ADC_CH_MUXINT1_bm (1<<4) /* MUX selection on Internal ADC input bit 1 mask. */ -#define ADC_CH_MUXINT1_bp 4 /* MUX selection on Internal ADC input bit 1 position. */ -#define ADC_CH_MUXINT2_bm (1<<5) /* MUX selection on Internal ADC input bit 2 mask. */ -#define ADC_CH_MUXINT2_bp 5 /* MUX selection on Internal ADC input bit 2 position. */ -#define ADC_CH_MUXINT3_bm (1<<6) /* MUX selection on Internal ADC input bit 3 mask. */ -#define ADC_CH_MUXINT3_bp 6 /* MUX selection on Internal ADC input bit 3 position. */ - -#define ADC_CH_MUXNEG_gm 0x07 /* MUX selection on Negative ADC input group mask. */ -#define ADC_CH_MUXNEG_gp 0 /* MUX selection on Negative ADC input group position. */ -#define ADC_CH_MUXNEG0_bm (1<<0) /* MUX selection on Negative ADC input bit 0 mask. */ -#define ADC_CH_MUXNEG0_bp 0 /* MUX selection on Negative ADC input bit 0 position. */ -#define ADC_CH_MUXNEG1_bm (1<<1) /* MUX selection on Negative ADC input bit 1 mask. */ -#define ADC_CH_MUXNEG1_bp 1 /* MUX selection on Negative ADC input bit 1 position. */ -#define ADC_CH_MUXNEG2_bm (1<<2) /* MUX selection on Negative ADC input bit 2 mask. */ -#define ADC_CH_MUXNEG2_bp 2 /* MUX selection on Negative ADC input bit 2 position. */ - -/* ADC_CH.INTCTRL bit masks and bit positions */ -#define ADC_CH_INTMODE_gm 0x0C /* Interrupt Mode group mask. */ -#define ADC_CH_INTMODE_gp 2 /* Interrupt Mode group position. */ -#define ADC_CH_INTMODE0_bm (1<<2) /* Interrupt Mode bit 0 mask. */ -#define ADC_CH_INTMODE0_bp 2 /* Interrupt Mode bit 0 position. */ -#define ADC_CH_INTMODE1_bm (1<<3) /* Interrupt Mode bit 1 mask. */ -#define ADC_CH_INTMODE1_bp 3 /* Interrupt Mode bit 1 position. */ - -#define ADC_CH_INTLVL_gm 0x03 /* Interrupt Level group mask. */ -#define ADC_CH_INTLVL_gp 0 /* Interrupt Level group position. */ -#define ADC_CH_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */ -#define ADC_CH_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */ -#define ADC_CH_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ -#define ADC_CH_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */ - -/* ADC_CH.INTFLAGS bit masks and bit positions */ -#define ADC_CH_CHIF_bm 0x01 /* Channel Interrupt Flag bit mask. */ -#define ADC_CH_CHIF_bp 0 /* Channel Interrupt Flag bit position. */ - -/* ADC_CH.SCAN bit masks and bit positions */ -#define ADC_CH_OFFSET_gm 0xF0 /* Positive MUX setting offset group mask. */ -#define ADC_CH_OFFSET_gp 4 /* Positive MUX setting offset group position. */ -#define ADC_CH_OFFSET0_bm (1<<4) /* Positive MUX setting offset bit 0 mask. */ -#define ADC_CH_OFFSET0_bp 4 /* Positive MUX setting offset bit 0 position. */ -#define ADC_CH_OFFSET1_bm (1<<5) /* Positive MUX setting offset bit 1 mask. */ -#define ADC_CH_OFFSET1_bp 5 /* Positive MUX setting offset bit 1 position. */ -#define ADC_CH_OFFSET2_bm (1<<6) /* Positive MUX setting offset bit 2 mask. */ -#define ADC_CH_OFFSET2_bp 6 /* Positive MUX setting offset bit 2 position. */ -#define ADC_CH_OFFSET3_bm (1<<7) /* Positive MUX setting offset bit 3 mask. */ -#define ADC_CH_OFFSET3_bp 7 /* Positive MUX setting offset bit 3 position. */ - -#define ADC_CH_SCANNUM_gm 0x0F /* Number of Channels included in scan group mask. */ -#define ADC_CH_SCANNUM_gp 0 /* Number of Channels included in scan group position. */ -#define ADC_CH_SCANNUM0_bm (1<<0) /* Number of Channels included in scan bit 0 mask. */ -#define ADC_CH_SCANNUM0_bp 0 /* Number of Channels included in scan bit 0 position. */ -#define ADC_CH_SCANNUM1_bm (1<<1) /* Number of Channels included in scan bit 1 mask. */ -#define ADC_CH_SCANNUM1_bp 1 /* Number of Channels included in scan bit 1 position. */ -#define ADC_CH_SCANNUM2_bm (1<<2) /* Number of Channels included in scan bit 2 mask. */ -#define ADC_CH_SCANNUM2_bp 2 /* Number of Channels included in scan bit 2 position. */ -#define ADC_CH_SCANNUM3_bm (1<<3) /* Number of Channels included in scan bit 3 mask. */ -#define ADC_CH_SCANNUM3_bp 3 /* Number of Channels included in scan bit 3 position. */ - -/* ADC.CTRLA bit masks and bit positions */ -#define ADC_DMASEL_gm 0xC0 /* DMA Selection group mask. */ -#define ADC_DMASEL_gp 6 /* DMA Selection group position. */ -#define ADC_DMASEL0_bm (1<<6) /* DMA Selection bit 0 mask. */ -#define ADC_DMASEL0_bp 6 /* DMA Selection bit 0 position. */ -#define ADC_DMASEL1_bm (1<<7) /* DMA Selection bit 1 mask. */ -#define ADC_DMASEL1_bp 7 /* DMA Selection bit 1 position. */ - -#define ADC_CH3START_bm 0x20 /* Channel 3 Start Conversion bit mask. */ -#define ADC_CH3START_bp 5 /* Channel 3 Start Conversion bit position. */ - -#define ADC_CH2START_bm 0x10 /* Channel 2 Start Conversion bit mask. */ -#define ADC_CH2START_bp 4 /* Channel 2 Start Conversion bit position. */ - -#define ADC_CH1START_bm 0x08 /* Channel 1 Start Conversion bit mask. */ -#define ADC_CH1START_bp 3 /* Channel 1 Start Conversion bit position. */ - -#define ADC_CH0START_bm 0x04 /* Channel 0 Start Conversion bit mask. */ -#define ADC_CH0START_bp 2 /* Channel 0 Start Conversion bit position. */ - -#define ADC_FLUSH_bm 0x02 /* Flush Pipeline bit mask. */ -#define ADC_FLUSH_bp 1 /* Flush Pipeline bit position. */ - -#define ADC_ENABLE_bm 0x01 /* Enable ADC bit mask. */ -#define ADC_ENABLE_bp 0 /* Enable ADC bit position. */ - -/* ADC.CTRLB bit masks and bit positions */ -#define ADC_IMPMODE_bm 0x80 /* Gain Stage Impedance Mode bit mask. */ -#define ADC_IMPMODE_bp 7 /* Gain Stage Impedance Mode bit position. */ - -#define ADC_CURRLIMIT_gm 0x60 /* Current Limitation group mask. */ -#define ADC_CURRLIMIT_gp 5 /* Current Limitation group position. */ -#define ADC_CURRLIMIT0_bm (1<<5) /* Current Limitation bit 0 mask. */ -#define ADC_CURRLIMIT0_bp 5 /* Current Limitation bit 0 position. */ -#define ADC_CURRLIMIT1_bm (1<<6) /* Current Limitation bit 1 mask. */ -#define ADC_CURRLIMIT1_bp 6 /* Current Limitation bit 1 position. */ - -#define ADC_CONMODE_bm 0x10 /* Conversion Mode bit mask. */ -#define ADC_CONMODE_bp 4 /* Conversion Mode bit position. */ - -#define ADC_FREERUN_bm 0x08 /* Free Running Mode Enable bit mask. */ -#define ADC_FREERUN_bp 3 /* Free Running Mode Enable bit position. */ - -#define ADC_RESOLUTION_gm 0x06 /* Result Resolution group mask. */ -#define ADC_RESOLUTION_gp 1 /* Result Resolution group position. */ -#define ADC_RESOLUTION0_bm (1<<1) /* Result Resolution bit 0 mask. */ -#define ADC_RESOLUTION0_bp 1 /* Result Resolution bit 0 position. */ -#define ADC_RESOLUTION1_bm (1<<2) /* Result Resolution bit 1 mask. */ -#define ADC_RESOLUTION1_bp 2 /* Result Resolution bit 1 position. */ - -/* ADC.REFCTRL bit masks and bit positions */ -#define ADC_REFSEL_gm 0x70 /* Reference Selection group mask. */ -#define ADC_REFSEL_gp 4 /* Reference Selection group position. */ -#define ADC_REFSEL0_bm (1<<4) /* Reference Selection bit 0 mask. */ -#define ADC_REFSEL0_bp 4 /* Reference Selection bit 0 position. */ -#define ADC_REFSEL1_bm (1<<5) /* Reference Selection bit 1 mask. */ -#define ADC_REFSEL1_bp 5 /* Reference Selection bit 1 position. */ -#define ADC_REFSEL2_bm (1<<6) /* Reference Selection bit 2 mask. */ -#define ADC_REFSEL2_bp 6 /* Reference Selection bit 2 position. */ - -#define ADC_BANDGAP_bm 0x02 /* Bandgap enable bit mask. */ -#define ADC_BANDGAP_bp 1 /* Bandgap enable bit position. */ - -#define ADC_TEMPREF_bm 0x01 /* Temperature Reference Enable bit mask. */ -#define ADC_TEMPREF_bp 0 /* Temperature Reference Enable bit position. */ - -/* ADC.EVCTRL bit masks and bit positions */ -#define ADC_SWEEP_gm 0xC0 /* Channel Sweep Selection group mask. */ -#define ADC_SWEEP_gp 6 /* Channel Sweep Selection group position. */ -#define ADC_SWEEP0_bm (1<<6) /* Channel Sweep Selection bit 0 mask. */ -#define ADC_SWEEP0_bp 6 /* Channel Sweep Selection bit 0 position. */ -#define ADC_SWEEP1_bm (1<<7) /* Channel Sweep Selection bit 1 mask. */ -#define ADC_SWEEP1_bp 7 /* Channel Sweep Selection bit 1 position. */ - -#define ADC_EVSEL_gm 0x38 /* Event Input Select group mask. */ -#define ADC_EVSEL_gp 3 /* Event Input Select group position. */ -#define ADC_EVSEL0_bm (1<<3) /* Event Input Select bit 0 mask. */ -#define ADC_EVSEL0_bp 3 /* Event Input Select bit 0 position. */ -#define ADC_EVSEL1_bm (1<<4) /* Event Input Select bit 1 mask. */ -#define ADC_EVSEL1_bp 4 /* Event Input Select bit 1 position. */ -#define ADC_EVSEL2_bm (1<<5) /* Event Input Select bit 2 mask. */ -#define ADC_EVSEL2_bp 5 /* Event Input Select bit 2 position. */ - -#define ADC_EVACT_gm 0x07 /* Event Action Select group mask. */ -#define ADC_EVACT_gp 0 /* Event Action Select group position. */ -#define ADC_EVACT0_bm (1<<0) /* Event Action Select bit 0 mask. */ -#define ADC_EVACT0_bp 0 /* Event Action Select bit 0 position. */ -#define ADC_EVACT1_bm (1<<1) /* Event Action Select bit 1 mask. */ -#define ADC_EVACT1_bp 1 /* Event Action Select bit 1 position. */ -#define ADC_EVACT2_bm (1<<2) /* Event Action Select bit 2 mask. */ -#define ADC_EVACT2_bp 2 /* Event Action Select bit 2 position. */ - -/* ADC.PRESCALER bit masks and bit positions */ -#define ADC_PRESCALER_gm 0x07 /* Clock Prescaler Selection group mask. */ -#define ADC_PRESCALER_gp 0 /* Clock Prescaler Selection group position. */ -#define ADC_PRESCALER0_bm (1<<0) /* Clock Prescaler Selection bit 0 mask. */ -#define ADC_PRESCALER0_bp 0 /* Clock Prescaler Selection bit 0 position. */ -#define ADC_PRESCALER1_bm (1<<1) /* Clock Prescaler Selection bit 1 mask. */ -#define ADC_PRESCALER1_bp 1 /* Clock Prescaler Selection bit 1 position. */ -#define ADC_PRESCALER2_bm (1<<2) /* Clock Prescaler Selection bit 2 mask. */ -#define ADC_PRESCALER2_bp 2 /* Clock Prescaler Selection bit 2 position. */ - -/* ADC.INTFLAGS bit masks and bit positions */ -#define ADC_CH3IF_bm 0x08 /* Channel 3 Interrupt Flag bit mask. */ -#define ADC_CH3IF_bp 3 /* Channel 3 Interrupt Flag bit position. */ - -#define ADC_CH2IF_bm 0x04 /* Channel 2 Interrupt Flag bit mask. */ -#define ADC_CH2IF_bp 2 /* Channel 2 Interrupt Flag bit position. */ - -#define ADC_CH1IF_bm 0x02 /* Channel 1 Interrupt Flag bit mask. */ -#define ADC_CH1IF_bp 1 /* Channel 1 Interrupt Flag bit position. */ - -#define ADC_CH0IF_bm 0x01 /* Channel 0 Interrupt Flag bit mask. */ -#define ADC_CH0IF_bp 0 /* Channel 0 Interrupt Flag bit position. */ - -/* DAC - Digital/Analog Converter */ -/* DAC.CTRLA bit masks and bit positions */ -#define DAC_IDOEN_bm 0x10 /* Internal Output Enable bit mask. */ -#define DAC_IDOEN_bp 4 /* Internal Output Enable bit position. */ - -#define DAC_CH1EN_bm 0x08 /* Channel 1 Output Enable bit mask. */ -#define DAC_CH1EN_bp 3 /* Channel 1 Output Enable bit position. */ - -#define DAC_CH0EN_bm 0x04 /* Channel 0 Output Enable bit mask. */ -#define DAC_CH0EN_bp 2 /* Channel 0 Output Enable bit position. */ - -#define DAC_LPMODE_bm 0x02 /* Low Power Mode bit mask. */ -#define DAC_LPMODE_bp 1 /* Low Power Mode bit position. */ - -#define DAC_ENABLE_bm 0x01 /* Enable bit mask. */ -#define DAC_ENABLE_bp 0 /* Enable bit position. */ - -/* DAC.CTRLB bit masks and bit positions */ -#define DAC_CHSEL_gm 0x60 /* Channel Select group mask. */ -#define DAC_CHSEL_gp 5 /* Channel Select group position. */ -#define DAC_CHSEL0_bm (1<<5) /* Channel Select bit 0 mask. */ -#define DAC_CHSEL0_bp 5 /* Channel Select bit 0 position. */ -#define DAC_CHSEL1_bm (1<<6) /* Channel Select bit 1 mask. */ -#define DAC_CHSEL1_bp 6 /* Channel Select bit 1 position. */ - -#define DAC_CH1TRIG_bm 0x02 /* Channel 1 Event Trig Enable bit mask. */ -#define DAC_CH1TRIG_bp 1 /* Channel 1 Event Trig Enable bit position. */ - -#define DAC_CH0TRIG_bm 0x01 /* Channel 0 Event Trig Enable bit mask. */ -#define DAC_CH0TRIG_bp 0 /* Channel 0 Event Trig Enable bit position. */ - -/* DAC.CTRLC bit masks and bit positions */ -#define DAC_REFSEL_gm 0x18 /* Reference Select group mask. */ -#define DAC_REFSEL_gp 3 /* Reference Select group position. */ -#define DAC_REFSEL0_bm (1<<3) /* Reference Select bit 0 mask. */ -#define DAC_REFSEL0_bp 3 /* Reference Select bit 0 position. */ -#define DAC_REFSEL1_bm (1<<4) /* Reference Select bit 1 mask. */ -#define DAC_REFSEL1_bp 4 /* Reference Select bit 1 position. */ - -#define DAC_LEFTADJ_bm 0x01 /* Left-adjust Result bit mask. */ -#define DAC_LEFTADJ_bp 0 /* Left-adjust Result bit position. */ - -/* DAC.EVCTRL bit masks and bit positions */ -#define DAC_EVSPLIT_bm 0x08 /* Separate Event Channel Input for Channel 1 bit mask. */ -#define DAC_EVSPLIT_bp 3 /* Separate Event Channel Input for Channel 1 bit position. */ - -#define DAC_EVSEL_gm 0x07 /* Event Input Selection group mask. */ -#define DAC_EVSEL_gp 0 /* Event Input Selection group position. */ -#define DAC_EVSEL0_bm (1<<0) /* Event Input Selection bit 0 mask. */ -#define DAC_EVSEL0_bp 0 /* Event Input Selection bit 0 position. */ -#define DAC_EVSEL1_bm (1<<1) /* Event Input Selection bit 1 mask. */ -#define DAC_EVSEL1_bp 1 /* Event Input Selection bit 1 position. */ -#define DAC_EVSEL2_bm (1<<2) /* Event Input Selection bit 2 mask. */ -#define DAC_EVSEL2_bp 2 /* Event Input Selection bit 2 position. */ - -/* DAC.STATUS bit masks and bit positions */ -#define DAC_CH1DRE_bm 0x02 /* Channel 1 Data Register Empty bit mask. */ -#define DAC_CH1DRE_bp 1 /* Channel 1 Data Register Empty bit position. */ - -#define DAC_CH0DRE_bm 0x01 /* Channel 0 Data Register Empty bit mask. */ -#define DAC_CH0DRE_bp 0 /* Channel 0 Data Register Empty bit position. */ - -/* DAC.CH0GAINCAL bit masks and bit positions */ -#define DAC_CH0GAINCAL_gm 0x7F /* Gain Calibration group mask. */ -#define DAC_CH0GAINCAL_gp 0 /* Gain Calibration group position. */ -#define DAC_CH0GAINCAL0_bm (1<<0) /* Gain Calibration bit 0 mask. */ -#define DAC_CH0GAINCAL0_bp 0 /* Gain Calibration bit 0 position. */ -#define DAC_CH0GAINCAL1_bm (1<<1) /* Gain Calibration bit 1 mask. */ -#define DAC_CH0GAINCAL1_bp 1 /* Gain Calibration bit 1 position. */ -#define DAC_CH0GAINCAL2_bm (1<<2) /* Gain Calibration bit 2 mask. */ -#define DAC_CH0GAINCAL2_bp 2 /* Gain Calibration bit 2 position. */ -#define DAC_CH0GAINCAL3_bm (1<<3) /* Gain Calibration bit 3 mask. */ -#define DAC_CH0GAINCAL3_bp 3 /* Gain Calibration bit 3 position. */ -#define DAC_CH0GAINCAL4_bm (1<<4) /* Gain Calibration bit 4 mask. */ -#define DAC_CH0GAINCAL4_bp 4 /* Gain Calibration bit 4 position. */ -#define DAC_CH0GAINCAL5_bm (1<<5) /* Gain Calibration bit 5 mask. */ -#define DAC_CH0GAINCAL5_bp 5 /* Gain Calibration bit 5 position. */ -#define DAC_CH0GAINCAL6_bm (1<<6) /* Gain Calibration bit 6 mask. */ -#define DAC_CH0GAINCAL6_bp 6 /* Gain Calibration bit 6 position. */ - -/* DAC.CH0OFFSETCAL bit masks and bit positions */ -#define DAC_CH0OFFSETCAL_gm 0x7F /* Offset Calibration group mask. */ -#define DAC_CH0OFFSETCAL_gp 0 /* Offset Calibration group position. */ -#define DAC_CH0OFFSETCAL0_bm (1<<0) /* Offset Calibration bit 0 mask. */ -#define DAC_CH0OFFSETCAL0_bp 0 /* Offset Calibration bit 0 position. */ -#define DAC_CH0OFFSETCAL1_bm (1<<1) /* Offset Calibration bit 1 mask. */ -#define DAC_CH0OFFSETCAL1_bp 1 /* Offset Calibration bit 1 position. */ -#define DAC_CH0OFFSETCAL2_bm (1<<2) /* Offset Calibration bit 2 mask. */ -#define DAC_CH0OFFSETCAL2_bp 2 /* Offset Calibration bit 2 position. */ -#define DAC_CH0OFFSETCAL3_bm (1<<3) /* Offset Calibration bit 3 mask. */ -#define DAC_CH0OFFSETCAL3_bp 3 /* Offset Calibration bit 3 position. */ -#define DAC_CH0OFFSETCAL4_bm (1<<4) /* Offset Calibration bit 4 mask. */ -#define DAC_CH0OFFSETCAL4_bp 4 /* Offset Calibration bit 4 position. */ -#define DAC_CH0OFFSETCAL5_bm (1<<5) /* Offset Calibration bit 5 mask. */ -#define DAC_CH0OFFSETCAL5_bp 5 /* Offset Calibration bit 5 position. */ -#define DAC_CH0OFFSETCAL6_bm (1<<6) /* Offset Calibration bit 6 mask. */ -#define DAC_CH0OFFSETCAL6_bp 6 /* Offset Calibration bit 6 position. */ - -/* DAC.CH1GAINCAL bit masks and bit positions */ -#define DAC_CH1GAINCAL_gm 0x7F /* Gain Calibration group mask. */ -#define DAC_CH1GAINCAL_gp 0 /* Gain Calibration group position. */ -#define DAC_CH1GAINCAL0_bm (1<<0) /* Gain Calibration bit 0 mask. */ -#define DAC_CH1GAINCAL0_bp 0 /* Gain Calibration bit 0 position. */ -#define DAC_CH1GAINCAL1_bm (1<<1) /* Gain Calibration bit 1 mask. */ -#define DAC_CH1GAINCAL1_bp 1 /* Gain Calibration bit 1 position. */ -#define DAC_CH1GAINCAL2_bm (1<<2) /* Gain Calibration bit 2 mask. */ -#define DAC_CH1GAINCAL2_bp 2 /* Gain Calibration bit 2 position. */ -#define DAC_CH1GAINCAL3_bm (1<<3) /* Gain Calibration bit 3 mask. */ -#define DAC_CH1GAINCAL3_bp 3 /* Gain Calibration bit 3 position. */ -#define DAC_CH1GAINCAL4_bm (1<<4) /* Gain Calibration bit 4 mask. */ -#define DAC_CH1GAINCAL4_bp 4 /* Gain Calibration bit 4 position. */ -#define DAC_CH1GAINCAL5_bm (1<<5) /* Gain Calibration bit 5 mask. */ -#define DAC_CH1GAINCAL5_bp 5 /* Gain Calibration bit 5 position. */ -#define DAC_CH1GAINCAL6_bm (1<<6) /* Gain Calibration bit 6 mask. */ -#define DAC_CH1GAINCAL6_bp 6 /* Gain Calibration bit 6 position. */ - -/* DAC.CH1OFFSETCAL bit masks and bit positions */ -#define DAC_CH1OFFSETCAL_gm 0x7F /* Offset Calibration group mask. */ -#define DAC_CH1OFFSETCAL_gp 0 /* Offset Calibration group position. */ -#define DAC_CH1OFFSETCAL0_bm (1<<0) /* Offset Calibration bit 0 mask. */ -#define DAC_CH1OFFSETCAL0_bp 0 /* Offset Calibration bit 0 position. */ -#define DAC_CH1OFFSETCAL1_bm (1<<1) /* Offset Calibration bit 1 mask. */ -#define DAC_CH1OFFSETCAL1_bp 1 /* Offset Calibration bit 1 position. */ -#define DAC_CH1OFFSETCAL2_bm (1<<2) /* Offset Calibration bit 2 mask. */ -#define DAC_CH1OFFSETCAL2_bp 2 /* Offset Calibration bit 2 position. */ -#define DAC_CH1OFFSETCAL3_bm (1<<3) /* Offset Calibration bit 3 mask. */ -#define DAC_CH1OFFSETCAL3_bp 3 /* Offset Calibration bit 3 position. */ -#define DAC_CH1OFFSETCAL4_bm (1<<4) /* Offset Calibration bit 4 mask. */ -#define DAC_CH1OFFSETCAL4_bp 4 /* Offset Calibration bit 4 position. */ -#define DAC_CH1OFFSETCAL5_bm (1<<5) /* Offset Calibration bit 5 mask. */ -#define DAC_CH1OFFSETCAL5_bp 5 /* Offset Calibration bit 5 position. */ -#define DAC_CH1OFFSETCAL6_bm (1<<6) /* Offset Calibration bit 6 mask. */ -#define DAC_CH1OFFSETCAL6_bp 6 /* Offset Calibration bit 6 position. */ - -/* AC - Analog Comparator */ -/* AC.AC0CTRL bit masks and bit positions */ -#define AC_INTMODE_gm 0xC0 /* Interrupt Mode group mask. */ -#define AC_INTMODE_gp 6 /* Interrupt Mode group position. */ -#define AC_INTMODE0_bm (1<<6) /* Interrupt Mode bit 0 mask. */ -#define AC_INTMODE0_bp 6 /* Interrupt Mode bit 0 position. */ -#define AC_INTMODE1_bm (1<<7) /* Interrupt Mode bit 1 mask. */ -#define AC_INTMODE1_bp 7 /* Interrupt Mode bit 1 position. */ - -#define AC_INTLVL_gm 0x30 /* Interrupt Level group mask. */ -#define AC_INTLVL_gp 4 /* Interrupt Level group position. */ -#define AC_INTLVL0_bm (1<<4) /* Interrupt Level bit 0 mask. */ -#define AC_INTLVL0_bp 4 /* Interrupt Level bit 0 position. */ -#define AC_INTLVL1_bm (1<<5) /* Interrupt Level bit 1 mask. */ -#define AC_INTLVL1_bp 5 /* Interrupt Level bit 1 position. */ - -#define AC_HSMODE_bm 0x08 /* High-speed Mode bit mask. */ -#define AC_HSMODE_bp 3 /* High-speed Mode bit position. */ - -#define AC_HYSMODE_gm 0x06 /* Hysteresis Mode group mask. */ -#define AC_HYSMODE_gp 1 /* Hysteresis Mode group position. */ -#define AC_HYSMODE0_bm (1<<1) /* Hysteresis Mode bit 0 mask. */ -#define AC_HYSMODE0_bp 1 /* Hysteresis Mode bit 0 position. */ -#define AC_HYSMODE1_bm (1<<2) /* Hysteresis Mode bit 1 mask. */ -#define AC_HYSMODE1_bp 2 /* Hysteresis Mode bit 1 position. */ - -#define AC_ENABLE_bm 0x01 /* Enable bit mask. */ -#define AC_ENABLE_bp 0 /* Enable bit position. */ - -/* AC.AC1CTRL bit masks and bit positions */ -/* AC_INTMODE Predefined. */ -/* AC_INTMODE Predefined. */ - -/* AC_INTLVL Predefined. */ -/* AC_INTLVL Predefined. */ - -/* AC_HSMODE Predefined. */ -/* AC_HSMODE Predefined. */ - -/* AC_HYSMODE Predefined. */ -/* AC_HYSMODE Predefined. */ - -/* AC_ENABLE Predefined. */ -/* AC_ENABLE Predefined. */ - -/* AC.AC0MUXCTRL bit masks and bit positions */ -#define AC_MUXPOS_gm 0x38 /* MUX Positive Input group mask. */ -#define AC_MUXPOS_gp 3 /* MUX Positive Input group position. */ -#define AC_MUXPOS0_bm (1<<3) /* MUX Positive Input bit 0 mask. */ -#define AC_MUXPOS0_bp 3 /* MUX Positive Input bit 0 position. */ -#define AC_MUXPOS1_bm (1<<4) /* MUX Positive Input bit 1 mask. */ -#define AC_MUXPOS1_bp 4 /* MUX Positive Input bit 1 position. */ -#define AC_MUXPOS2_bm (1<<5) /* MUX Positive Input bit 2 mask. */ -#define AC_MUXPOS2_bp 5 /* MUX Positive Input bit 2 position. */ - -#define AC_MUXNEG_gm 0x07 /* MUX Negative Input group mask. */ -#define AC_MUXNEG_gp 0 /* MUX Negative Input group position. */ -#define AC_MUXNEG0_bm (1<<0) /* MUX Negative Input bit 0 mask. */ -#define AC_MUXNEG0_bp 0 /* MUX Negative Input bit 0 position. */ -#define AC_MUXNEG1_bm (1<<1) /* MUX Negative Input bit 1 mask. */ -#define AC_MUXNEG1_bp 1 /* MUX Negative Input bit 1 position. */ -#define AC_MUXNEG2_bm (1<<2) /* MUX Negative Input bit 2 mask. */ -#define AC_MUXNEG2_bp 2 /* MUX Negative Input bit 2 position. */ - -/* AC.AC1MUXCTRL bit masks and bit positions */ -/* AC_MUXPOS Predefined. */ -/* AC_MUXPOS Predefined. */ - -/* AC_MUXNEG Predefined. */ -/* AC_MUXNEG Predefined. */ - -/* AC.CTRLA bit masks and bit positions */ -#define AC_AC1OUT_bm 0x02 /* Analog Comparator 1 Output Enable bit mask. */ -#define AC_AC1OUT_bp 1 /* Analog Comparator 1 Output Enable bit position. */ - -#define AC_AC0OUT_bm 0x01 /* Analog Comparator 0 Output Enable bit mask. */ -#define AC_AC0OUT_bp 0 /* Analog Comparator 0 Output Enable bit position. */ - -/* AC.CTRLB bit masks and bit positions */ -#define AC_SCALEFAC_gm 0x3F /* VCC Voltage Scaler Factor group mask. */ -#define AC_SCALEFAC_gp 0 /* VCC Voltage Scaler Factor group position. */ -#define AC_SCALEFAC0_bm (1<<0) /* VCC Voltage Scaler Factor bit 0 mask. */ -#define AC_SCALEFAC0_bp 0 /* VCC Voltage Scaler Factor bit 0 position. */ -#define AC_SCALEFAC1_bm (1<<1) /* VCC Voltage Scaler Factor bit 1 mask. */ -#define AC_SCALEFAC1_bp 1 /* VCC Voltage Scaler Factor bit 1 position. */ -#define AC_SCALEFAC2_bm (1<<2) /* VCC Voltage Scaler Factor bit 2 mask. */ -#define AC_SCALEFAC2_bp 2 /* VCC Voltage Scaler Factor bit 2 position. */ -#define AC_SCALEFAC3_bm (1<<3) /* VCC Voltage Scaler Factor bit 3 mask. */ -#define AC_SCALEFAC3_bp 3 /* VCC Voltage Scaler Factor bit 3 position. */ -#define AC_SCALEFAC4_bm (1<<4) /* VCC Voltage Scaler Factor bit 4 mask. */ -#define AC_SCALEFAC4_bp 4 /* VCC Voltage Scaler Factor bit 4 position. */ -#define AC_SCALEFAC5_bm (1<<5) /* VCC Voltage Scaler Factor bit 5 mask. */ -#define AC_SCALEFAC5_bp 5 /* VCC Voltage Scaler Factor bit 5 position. */ - -/* AC.WINCTRL bit masks and bit positions */ -#define AC_WEN_bm 0x10 /* Window Mode Enable bit mask. */ -#define AC_WEN_bp 4 /* Window Mode Enable bit position. */ - -#define AC_WINTMODE_gm 0x0C /* Window Interrupt Mode group mask. */ -#define AC_WINTMODE_gp 2 /* Window Interrupt Mode group position. */ -#define AC_WINTMODE0_bm (1<<2) /* Window Interrupt Mode bit 0 mask. */ -#define AC_WINTMODE0_bp 2 /* Window Interrupt Mode bit 0 position. */ -#define AC_WINTMODE1_bm (1<<3) /* Window Interrupt Mode bit 1 mask. */ -#define AC_WINTMODE1_bp 3 /* Window Interrupt Mode bit 1 position. */ - -#define AC_WINTLVL_gm 0x03 /* Window Interrupt Level group mask. */ -#define AC_WINTLVL_gp 0 /* Window Interrupt Level group position. */ -#define AC_WINTLVL0_bm (1<<0) /* Window Interrupt Level bit 0 mask. */ -#define AC_WINTLVL0_bp 0 /* Window Interrupt Level bit 0 position. */ -#define AC_WINTLVL1_bm (1<<1) /* Window Interrupt Level bit 1 mask. */ -#define AC_WINTLVL1_bp 1 /* Window Interrupt Level bit 1 position. */ - -/* AC.STATUS bit masks and bit positions */ -#define AC_WSTATE_gm 0xC0 /* Window Mode State group mask. */ -#define AC_WSTATE_gp 6 /* Window Mode State group position. */ -#define AC_WSTATE0_bm (1<<6) /* Window Mode State bit 0 mask. */ -#define AC_WSTATE0_bp 6 /* Window Mode State bit 0 position. */ -#define AC_WSTATE1_bm (1<<7) /* Window Mode State bit 1 mask. */ -#define AC_WSTATE1_bp 7 /* Window Mode State bit 1 position. */ - -#define AC_AC1STATE_bm 0x20 /* Analog Comparator 1 State bit mask. */ -#define AC_AC1STATE_bp 5 /* Analog Comparator 1 State bit position. */ - -#define AC_AC0STATE_bm 0x10 /* Analog Comparator 0 State bit mask. */ -#define AC_AC0STATE_bp 4 /* Analog Comparator 0 State bit position. */ - -#define AC_WIF_bm 0x04 /* Window Mode Interrupt Flag bit mask. */ -#define AC_WIF_bp 2 /* Window Mode Interrupt Flag bit position. */ - -#define AC_AC1IF_bm 0x02 /* Analog Comparator 1 Interrupt Flag bit mask. */ -#define AC_AC1IF_bp 1 /* Analog Comparator 1 Interrupt Flag bit position. */ - -#define AC_AC0IF_bm 0x01 /* Analog Comparator 0 Interrupt Flag bit mask. */ -#define AC_AC0IF_bp 0 /* Analog Comparator 0 Interrupt Flag bit position. */ - -/* RTC - Real-Time Counter */ -/* RTC.CTRL bit masks and bit positions */ -#define RTC_PRESCALER_gm 0x07 /* Prescaling Factor group mask. */ -#define RTC_PRESCALER_gp 0 /* Prescaling Factor group position. */ -#define RTC_PRESCALER0_bm (1<<0) /* Prescaling Factor bit 0 mask. */ -#define RTC_PRESCALER0_bp 0 /* Prescaling Factor bit 0 position. */ -#define RTC_PRESCALER1_bm (1<<1) /* Prescaling Factor bit 1 mask. */ -#define RTC_PRESCALER1_bp 1 /* Prescaling Factor bit 1 position. */ -#define RTC_PRESCALER2_bm (1<<2) /* Prescaling Factor bit 2 mask. */ -#define RTC_PRESCALER2_bp 2 /* Prescaling Factor bit 2 position. */ - -/* RTC.STATUS bit masks and bit positions */ -#define RTC_SYNCBUSY_bm 0x01 /* Synchronization Busy Flag bit mask. */ -#define RTC_SYNCBUSY_bp 0 /* Synchronization Busy Flag bit position. */ - -/* RTC.INTCTRL bit masks and bit positions */ -#define RTC_COMPINTLVL_gm 0x0C /* Compare Match Interrupt Level group mask. */ -#define RTC_COMPINTLVL_gp 2 /* Compare Match Interrupt Level group position. */ -#define RTC_COMPINTLVL0_bm (1<<2) /* Compare Match Interrupt Level bit 0 mask. */ -#define RTC_COMPINTLVL0_bp 2 /* Compare Match Interrupt Level bit 0 position. */ -#define RTC_COMPINTLVL1_bm (1<<3) /* Compare Match Interrupt Level bit 1 mask. */ -#define RTC_COMPINTLVL1_bp 3 /* Compare Match Interrupt Level bit 1 position. */ - -#define RTC_OVFINTLVL_gm 0x03 /* Overflow Interrupt Level group mask. */ -#define RTC_OVFINTLVL_gp 0 /* Overflow Interrupt Level group position. */ -#define RTC_OVFINTLVL0_bm (1<<0) /* Overflow Interrupt Level bit 0 mask. */ -#define RTC_OVFINTLVL0_bp 0 /* Overflow Interrupt Level bit 0 position. */ -#define RTC_OVFINTLVL1_bm (1<<1) /* Overflow Interrupt Level bit 1 mask. */ -#define RTC_OVFINTLVL1_bp 1 /* Overflow Interrupt Level bit 1 position. */ - -/* RTC.INTFLAGS bit masks and bit positions */ -#define RTC_COMPIF_bm 0x02 /* Compare Match Interrupt Flag bit mask. */ -#define RTC_COMPIF_bp 1 /* Compare Match Interrupt Flag bit position. */ - -#define RTC_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ -#define RTC_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ - -/* EBI - External Bus Interface */ -/* EBI_CS.CTRLA bit masks and bit positions */ -#define EBI_CS_ASPACE_gm 0x7C /* Address Space group mask. */ -#define EBI_CS_ASPACE_gp 2 /* Address Space group position. */ -#define EBI_CS_ASPACE0_bm (1<<2) /* Address Space bit 0 mask. */ -#define EBI_CS_ASPACE0_bp 2 /* Address Space bit 0 position. */ -#define EBI_CS_ASPACE1_bm (1<<3) /* Address Space bit 1 mask. */ -#define EBI_CS_ASPACE1_bp 3 /* Address Space bit 1 position. */ -#define EBI_CS_ASPACE2_bm (1<<4) /* Address Space bit 2 mask. */ -#define EBI_CS_ASPACE2_bp 4 /* Address Space bit 2 position. */ -#define EBI_CS_ASPACE3_bm (1<<5) /* Address Space bit 3 mask. */ -#define EBI_CS_ASPACE3_bp 5 /* Address Space bit 3 position. */ -#define EBI_CS_ASPACE4_bm (1<<6) /* Address Space bit 4 mask. */ -#define EBI_CS_ASPACE4_bp 6 /* Address Space bit 4 position. */ - -#define EBI_CS_MODE_gm 0x03 /* Memory Mode group mask. */ -#define EBI_CS_MODE_gp 0 /* Memory Mode group position. */ -#define EBI_CS_MODE0_bm (1<<0) /* Memory Mode bit 0 mask. */ -#define EBI_CS_MODE0_bp 0 /* Memory Mode bit 0 position. */ -#define EBI_CS_MODE1_bm (1<<1) /* Memory Mode bit 1 mask. */ -#define EBI_CS_MODE1_bp 1 /* Memory Mode bit 1 position. */ - -/* EBI_CS.CTRLB bit masks and bit positions */ -#define EBI_CS_SRWS_gm 0x07 /* SRAM Wait State Cycles group mask. */ -#define EBI_CS_SRWS_gp 0 /* SRAM Wait State Cycles group position. */ -#define EBI_CS_SRWS0_bm (1<<0) /* SRAM Wait State Cycles bit 0 mask. */ -#define EBI_CS_SRWS0_bp 0 /* SRAM Wait State Cycles bit 0 position. */ -#define EBI_CS_SRWS1_bm (1<<1) /* SRAM Wait State Cycles bit 1 mask. */ -#define EBI_CS_SRWS1_bp 1 /* SRAM Wait State Cycles bit 1 position. */ -#define EBI_CS_SRWS2_bm (1<<2) /* SRAM Wait State Cycles bit 2 mask. */ -#define EBI_CS_SRWS2_bp 2 /* SRAM Wait State Cycles bit 2 position. */ - -#define EBI_CS_SDINITDONE_bm 0x80 /* SDRAM Initialization Done bit mask. */ -#define EBI_CS_SDINITDONE_bp 7 /* SDRAM Initialization Done bit position. */ - -#define EBI_CS_SDSREN_bm 0x04 /* SDRAM Self-refresh Enable bit mask. */ -#define EBI_CS_SDSREN_bp 2 /* SDRAM Self-refresh Enable bit position. */ - -#define EBI_CS_SDMODE_gm 0x03 /* SDRAM Mode group mask. */ -#define EBI_CS_SDMODE_gp 0 /* SDRAM Mode group position. */ -#define EBI_CS_SDMODE0_bm (1<<0) /* SDRAM Mode bit 0 mask. */ -#define EBI_CS_SDMODE0_bp 0 /* SDRAM Mode bit 0 position. */ -#define EBI_CS_SDMODE1_bm (1<<1) /* SDRAM Mode bit 1 mask. */ -#define EBI_CS_SDMODE1_bp 1 /* SDRAM Mode bit 1 position. */ - -/* EBI.CTRL bit masks and bit positions */ -#define EBI_SDDATAW_gm 0xC0 /* SDRAM Data Width Setting group mask. */ -#define EBI_SDDATAW_gp 6 /* SDRAM Data Width Setting group position. */ -#define EBI_SDDATAW0_bm (1<<6) /* SDRAM Data Width Setting bit 0 mask. */ -#define EBI_SDDATAW0_bp 6 /* SDRAM Data Width Setting bit 0 position. */ -#define EBI_SDDATAW1_bm (1<<7) /* SDRAM Data Width Setting bit 1 mask. */ -#define EBI_SDDATAW1_bp 7 /* SDRAM Data Width Setting bit 1 position. */ - -#define EBI_LPCMODE_gm 0x30 /* SRAM LPC Mode group mask. */ -#define EBI_LPCMODE_gp 4 /* SRAM LPC Mode group position. */ -#define EBI_LPCMODE0_bm (1<<4) /* SRAM LPC Mode bit 0 mask. */ -#define EBI_LPCMODE0_bp 4 /* SRAM LPC Mode bit 0 position. */ -#define EBI_LPCMODE1_bm (1<<5) /* SRAM LPC Mode bit 1 mask. */ -#define EBI_LPCMODE1_bp 5 /* SRAM LPC Mode bit 1 position. */ - -#define EBI_SRMODE_gm 0x0C /* SRAM Mode group mask. */ -#define EBI_SRMODE_gp 2 /* SRAM Mode group position. */ -#define EBI_SRMODE0_bm (1<<2) /* SRAM Mode bit 0 mask. */ -#define EBI_SRMODE0_bp 2 /* SRAM Mode bit 0 position. */ -#define EBI_SRMODE1_bm (1<<3) /* SRAM Mode bit 1 mask. */ -#define EBI_SRMODE1_bp 3 /* SRAM Mode bit 1 position. */ - -#define EBI_IFMODE_gm 0x03 /* Interface Mode group mask. */ -#define EBI_IFMODE_gp 0 /* Interface Mode group position. */ -#define EBI_IFMODE0_bm (1<<0) /* Interface Mode bit 0 mask. */ -#define EBI_IFMODE0_bp 0 /* Interface Mode bit 0 position. */ -#define EBI_IFMODE1_bm (1<<1) /* Interface Mode bit 1 mask. */ -#define EBI_IFMODE1_bp 1 /* Interface Mode bit 1 position. */ - -/* EBI.SDRAMCTRLA bit masks and bit positions */ -#define EBI_SDCAS_bm 0x08 /* SDRAM CAS Latency Setting bit mask. */ -#define EBI_SDCAS_bp 3 /* SDRAM CAS Latency Setting bit position. */ - -#define EBI_SDROW_bm 0x04 /* SDRAM ROW Bits Setting bit mask. */ -#define EBI_SDROW_bp 2 /* SDRAM ROW Bits Setting bit position. */ - -#define EBI_SDCOL_gm 0x03 /* SDRAM Column Bits Setting group mask. */ -#define EBI_SDCOL_gp 0 /* SDRAM Column Bits Setting group position. */ -#define EBI_SDCOL0_bm (1<<0) /* SDRAM Column Bits Setting bit 0 mask. */ -#define EBI_SDCOL0_bp 0 /* SDRAM Column Bits Setting bit 0 position. */ -#define EBI_SDCOL1_bm (1<<1) /* SDRAM Column Bits Setting bit 1 mask. */ -#define EBI_SDCOL1_bp 1 /* SDRAM Column Bits Setting bit 1 position. */ - -/* EBI.SDRAMCTRLB bit masks and bit positions */ -#define EBI_MRDLY_gm 0xC0 /* SDRAM Mode Register Delay group mask. */ -#define EBI_MRDLY_gp 6 /* SDRAM Mode Register Delay group position. */ -#define EBI_MRDLY0_bm (1<<6) /* SDRAM Mode Register Delay bit 0 mask. */ -#define EBI_MRDLY0_bp 6 /* SDRAM Mode Register Delay bit 0 position. */ -#define EBI_MRDLY1_bm (1<<7) /* SDRAM Mode Register Delay bit 1 mask. */ -#define EBI_MRDLY1_bp 7 /* SDRAM Mode Register Delay bit 1 position. */ - -#define EBI_ROWCYCDLY_gm 0x38 /* SDRAM Row Cycle Delay group mask. */ -#define EBI_ROWCYCDLY_gp 3 /* SDRAM Row Cycle Delay group position. */ -#define EBI_ROWCYCDLY0_bm (1<<3) /* SDRAM Row Cycle Delay bit 0 mask. */ -#define EBI_ROWCYCDLY0_bp 3 /* SDRAM Row Cycle Delay bit 0 position. */ -#define EBI_ROWCYCDLY1_bm (1<<4) /* SDRAM Row Cycle Delay bit 1 mask. */ -#define EBI_ROWCYCDLY1_bp 4 /* SDRAM Row Cycle Delay bit 1 position. */ -#define EBI_ROWCYCDLY2_bm (1<<5) /* SDRAM Row Cycle Delay bit 2 mask. */ -#define EBI_ROWCYCDLY2_bp 5 /* SDRAM Row Cycle Delay bit 2 position. */ - -#define EBI_RPDLY_gm 0x07 /* SDRAM Row-to-Precharge Delay group mask. */ -#define EBI_RPDLY_gp 0 /* SDRAM Row-to-Precharge Delay group position. */ -#define EBI_RPDLY0_bm (1<<0) /* SDRAM Row-to-Precharge Delay bit 0 mask. */ -#define EBI_RPDLY0_bp 0 /* SDRAM Row-to-Precharge Delay bit 0 position. */ -#define EBI_RPDLY1_bm (1<<1) /* SDRAM Row-to-Precharge Delay bit 1 mask. */ -#define EBI_RPDLY1_bp 1 /* SDRAM Row-to-Precharge Delay bit 1 position. */ -#define EBI_RPDLY2_bm (1<<2) /* SDRAM Row-to-Precharge Delay bit 2 mask. */ -#define EBI_RPDLY2_bp 2 /* SDRAM Row-to-Precharge Delay bit 2 position. */ - -/* EBI.SDRAMCTRLC bit masks and bit positions */ -#define EBI_WRDLY_gm 0xC0 /* SDRAM Write Recovery Delay group mask. */ -#define EBI_WRDLY_gp 6 /* SDRAM Write Recovery Delay group position. */ -#define EBI_WRDLY0_bm (1<<6) /* SDRAM Write Recovery Delay bit 0 mask. */ -#define EBI_WRDLY0_bp 6 /* SDRAM Write Recovery Delay bit 0 position. */ -#define EBI_WRDLY1_bm (1<<7) /* SDRAM Write Recovery Delay bit 1 mask. */ -#define EBI_WRDLY1_bp 7 /* SDRAM Write Recovery Delay bit 1 position. */ - -#define EBI_ESRDLY_gm 0x38 /* SDRAM Exit-Self-refresh-to-Active Delay group mask. */ -#define EBI_ESRDLY_gp 3 /* SDRAM Exit-Self-refresh-to-Active Delay group position. */ -#define EBI_ESRDLY0_bm (1<<3) /* SDRAM Exit-Self-refresh-to-Active Delay bit 0 mask. */ -#define EBI_ESRDLY0_bp 3 /* SDRAM Exit-Self-refresh-to-Active Delay bit 0 position. */ -#define EBI_ESRDLY1_bm (1<<4) /* SDRAM Exit-Self-refresh-to-Active Delay bit 1 mask. */ -#define EBI_ESRDLY1_bp 4 /* SDRAM Exit-Self-refresh-to-Active Delay bit 1 position. */ -#define EBI_ESRDLY2_bm (1<<5) /* SDRAM Exit-Self-refresh-to-Active Delay bit 2 mask. */ -#define EBI_ESRDLY2_bp 5 /* SDRAM Exit-Self-refresh-to-Active Delay bit 2 position. */ - -#define EBI_ROWCOLDLY_gm 0x07 /* SDRAM Row-to-Column Delay group mask. */ -#define EBI_ROWCOLDLY_gp 0 /* SDRAM Row-to-Column Delay group position. */ -#define EBI_ROWCOLDLY0_bm (1<<0) /* SDRAM Row-to-Column Delay bit 0 mask. */ -#define EBI_ROWCOLDLY0_bp 0 /* SDRAM Row-to-Column Delay bit 0 position. */ -#define EBI_ROWCOLDLY1_bm (1<<1) /* SDRAM Row-to-Column Delay bit 1 mask. */ -#define EBI_ROWCOLDLY1_bp 1 /* SDRAM Row-to-Column Delay bit 1 position. */ -#define EBI_ROWCOLDLY2_bm (1<<2) /* SDRAM Row-to-Column Delay bit 2 mask. */ -#define EBI_ROWCOLDLY2_bp 2 /* SDRAM Row-to-Column Delay bit 2 position. */ - -/* TWI - Two-Wire Interface */ -/* TWI_MASTER.CTRLA bit masks and bit positions */ -#define TWI_MASTER_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ -#define TWI_MASTER_INTLVL_gp 6 /* Interrupt Level group position. */ -#define TWI_MASTER_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ -#define TWI_MASTER_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ -#define TWI_MASTER_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ -#define TWI_MASTER_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ - -#define TWI_MASTER_RIEN_bm 0x20 /* Read Interrupt Enable bit mask. */ -#define TWI_MASTER_RIEN_bp 5 /* Read Interrupt Enable bit position. */ - -#define TWI_MASTER_WIEN_bm 0x10 /* Write Interrupt Enable bit mask. */ -#define TWI_MASTER_WIEN_bp 4 /* Write Interrupt Enable bit position. */ - -#define TWI_MASTER_ENABLE_bm 0x08 /* Enable TWI Master bit mask. */ -#define TWI_MASTER_ENABLE_bp 3 /* Enable TWI Master bit position. */ - -/* TWI_MASTER.CTRLB bit masks and bit positions */ -#define TWI_MASTER_TIMEOUT_gm 0x0C /* Inactive Bus Tisdahmeout group mask. */ -#define TWI_MASTER_TIMEOUT_gp 2 /* Inactive Bus Tisdahmeout group position. */ -#define TWI_MASTER_TIMEOUT0_bm (1<<2) /* Inactive Bus Tisdahmeout bit 0 mask. */ -#define TWI_MASTER_TIMEOUT0_bp 2 /* Inactive Bus Tisdahmeout bit 0 position. */ -#define TWI_MASTER_TIMEOUT1_bm (1<<3) /* Inactive Bus Tisdahmeout bit 1 mask. */ -#define TWI_MASTER_TIMEOUT1_bp 3 /* Inactive Bus Tisdahmeout bit 1 position. */ - -#define TWI_MASTER_QCEN_bm 0x02 /* Quick Command Enable bit mask. */ -#define TWI_MASTER_QCEN_bp 1 /* Quick Command Enable bit position. */ - -#define TWI_MASTER_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ -#define TWI_MASTER_SMEN_bp 0 /* Smart Mode Enable bit position. */ - -/* TWI_MASTER.CTRLC bit masks and bit positions */ -#define TWI_MASTER_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ -#define TWI_MASTER_ACKACT_bp 2 /* Acknowledge Action bit position. */ - -#define TWI_MASTER_CMD_gm 0x03 /* Command group mask. */ -#define TWI_MASTER_CMD_gp 0 /* Command group position. */ -#define TWI_MASTER_CMD0_bm (1<<0) /* Command bit 0 mask. */ -#define TWI_MASTER_CMD0_bp 0 /* Command bit 0 position. */ -#define TWI_MASTER_CMD1_bm (1<<1) /* Command bit 1 mask. */ -#define TWI_MASTER_CMD1_bp 1 /* Command bit 1 position. */ - -/* TWI_MASTER.STATUS bit masks and bit positions */ -#define TWI_MASTER_RIF_bm 0x80 /* Read Interrupt Flag bit mask. */ -#define TWI_MASTER_RIF_bp 7 /* Read Interrupt Flag bit position. */ - -#define TWI_MASTER_WIF_bm 0x40 /* Write Interrupt Flag bit mask. */ -#define TWI_MASTER_WIF_bp 6 /* Write Interrupt Flag bit position. */ - -#define TWI_MASTER_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ -#define TWI_MASTER_CLKHOLD_bp 5 /* Clock Hold bit position. */ - -#define TWI_MASTER_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ -#define TWI_MASTER_RXACK_bp 4 /* Received Acknowledge bit position. */ - -#define TWI_MASTER_ARBLOST_bm 0x08 /* Arbitration Lost bit mask. */ -#define TWI_MASTER_ARBLOST_bp 3 /* Arbitration Lost bit position. */ - -#define TWI_MASTER_BUSERR_bm 0x04 /* Bus Error bit mask. */ -#define TWI_MASTER_BUSERR_bp 2 /* Bus Error bit position. */ - -#define TWI_MASTER_BUSSTATE_gm 0x03 /* Bus State group mask. */ -#define TWI_MASTER_BUSSTATE_gp 0 /* Bus State group position. */ -#define TWI_MASTER_BUSSTATE0_bm (1<<0) /* Bus State bit 0 mask. */ -#define TWI_MASTER_BUSSTATE0_bp 0 /* Bus State bit 0 position. */ -#define TWI_MASTER_BUSSTATE1_bm (1<<1) /* Bus State bit 1 mask. */ -#define TWI_MASTER_BUSSTATE1_bp 1 /* Bus State bit 1 position. */ - -/* TWI_SLAVE.CTRLA bit masks and bit positions */ -#define TWI_SLAVE_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ -#define TWI_SLAVE_INTLVL_gp 6 /* Interrupt Level group position. */ -#define TWI_SLAVE_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ -#define TWI_SLAVE_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ -#define TWI_SLAVE_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ -#define TWI_SLAVE_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ - -#define TWI_SLAVE_DIEN_bm 0x20 /* Data Interrupt Enable bit mask. */ -#define TWI_SLAVE_DIEN_bp 5 /* Data Interrupt Enable bit position. */ - -#define TWI_SLAVE_APIEN_bm 0x10 /* Address/Stop Interrupt Enable bit mask. */ -#define TWI_SLAVE_APIEN_bp 4 /* Address/Stop Interrupt Enable bit position. */ - -#define TWI_SLAVE_ENABLE_bm 0x08 /* Enable TWI Slave bit mask. */ -#define TWI_SLAVE_ENABLE_bp 3 /* Enable TWI Slave bit position. */ - -#define TWI_SLAVE_PIEN_bm 0x04 /* Stop Interrupt Enable bit mask. */ -#define TWI_SLAVE_PIEN_bp 2 /* Stop Interrupt Enable bit position. */ - -#define TWI_SLAVE_PMEN_bm 0x02 /* Promiscuous Mode Enable bit mask. */ -#define TWI_SLAVE_PMEN_bp 1 /* Promiscuous Mode Enable bit position. */ - -#define TWI_SLAVE_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ -#define TWI_SLAVE_SMEN_bp 0 /* Smart Mode Enable bit position. */ - -/* TWI_SLAVE.CTRLB bit masks and bit positions */ -#define TWI_SLAVE_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ -#define TWI_SLAVE_ACKACT_bp 2 /* Acknowledge Action bit position. */ - -#define TWI_SLAVE_CMD_gm 0x03 /* Command group mask. */ -#define TWI_SLAVE_CMD_gp 0 /* Command group position. */ -#define TWI_SLAVE_CMD0_bm (1<<0) /* Command bit 0 mask. */ -#define TWI_SLAVE_CMD0_bp 0 /* Command bit 0 position. */ -#define TWI_SLAVE_CMD1_bm (1<<1) /* Command bit 1 mask. */ -#define TWI_SLAVE_CMD1_bp 1 /* Command bit 1 position. */ - -/* TWI_SLAVE.STATUS bit masks and bit positions */ -#define TWI_SLAVE_DIF_bm 0x80 /* Data Interrupt Flag bit mask. */ -#define TWI_SLAVE_DIF_bp 7 /* Data Interrupt Flag bit position. */ - -#define TWI_SLAVE_APIF_bm 0x40 /* Address/Stop Interrupt Flag bit mask. */ -#define TWI_SLAVE_APIF_bp 6 /* Address/Stop Interrupt Flag bit position. */ - -#define TWI_SLAVE_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ -#define TWI_SLAVE_CLKHOLD_bp 5 /* Clock Hold bit position. */ - -#define TWI_SLAVE_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ -#define TWI_SLAVE_RXACK_bp 4 /* Received Acknowledge bit position. */ - -#define TWI_SLAVE_COLL_bm 0x08 /* Collision bit mask. */ -#define TWI_SLAVE_COLL_bp 3 /* Collision bit position. */ - -#define TWI_SLAVE_BUSERR_bm 0x04 /* Bus Error bit mask. */ -#define TWI_SLAVE_BUSERR_bp 2 /* Bus Error bit position. */ - -#define TWI_SLAVE_DIR_bm 0x02 /* Read/Write Direction bit mask. */ -#define TWI_SLAVE_DIR_bp 1 /* Read/Write Direction bit position. */ - -#define TWI_SLAVE_AP_bm 0x01 /* Slave Address or Stop bit mask. */ -#define TWI_SLAVE_AP_bp 0 /* Slave Address or Stop bit position. */ - -/* TWI_SLAVE.ADDRMASK bit masks and bit positions */ -#define TWI_SLAVE_ADDRMASK_gm 0xFE /* Address Mask group mask. */ -#define TWI_SLAVE_ADDRMASK_gp 1 /* Address Mask group position. */ -#define TWI_SLAVE_ADDRMASK0_bm (1<<1) /* Address Mask bit 0 mask. */ -#define TWI_SLAVE_ADDRMASK0_bp 1 /* Address Mask bit 0 position. */ -#define TWI_SLAVE_ADDRMASK1_bm (1<<2) /* Address Mask bit 1 mask. */ -#define TWI_SLAVE_ADDRMASK1_bp 2 /* Address Mask bit 1 position. */ -#define TWI_SLAVE_ADDRMASK2_bm (1<<3) /* Address Mask bit 2 mask. */ -#define TWI_SLAVE_ADDRMASK2_bp 3 /* Address Mask bit 2 position. */ -#define TWI_SLAVE_ADDRMASK3_bm (1<<4) /* Address Mask bit 3 mask. */ -#define TWI_SLAVE_ADDRMASK3_bp 4 /* Address Mask bit 3 position. */ -#define TWI_SLAVE_ADDRMASK4_bm (1<<5) /* Address Mask bit 4 mask. */ -#define TWI_SLAVE_ADDRMASK4_bp 5 /* Address Mask bit 4 position. */ -#define TWI_SLAVE_ADDRMASK5_bm (1<<6) /* Address Mask bit 5 mask. */ -#define TWI_SLAVE_ADDRMASK5_bp 6 /* Address Mask bit 5 position. */ -#define TWI_SLAVE_ADDRMASK6_bm (1<<7) /* Address Mask bit 6 mask. */ -#define TWI_SLAVE_ADDRMASK6_bp 7 /* Address Mask bit 6 position. */ - -#define TWI_SLAVE_ADDREN_bm 0x01 /* Address Enable bit mask. */ -#define TWI_SLAVE_ADDREN_bp 0 /* Address Enable bit position. */ - -/* TWI.CTRL bit masks and bit positions */ -#define TWI_SDAHOLD_gm 0x06 /* SDA Hold Time Enable group mask. */ -#define TWI_SDAHOLD_gp 1 /* SDA Hold Time Enable group position. */ -#define TWI_SDAHOLD0_bm (1<<1) /* SDA Hold Time Enable bit 0 mask. */ -#define TWI_SDAHOLD0_bp 1 /* SDA Hold Time Enable bit 0 position. */ -#define TWI_SDAHOLD1_bm (1<<2) /* SDA Hold Time Enable bit 1 mask. */ -#define TWI_SDAHOLD1_bp 2 /* SDA Hold Time Enable bit 1 position. */ - -#define TWI_EDIEN_bm 0x01 /* External Driver Interface Enable bit mask. */ -#define TWI_EDIEN_bp 0 /* External Driver Interface Enable bit position. */ - -/* USB - USB */ -/* USB_EP.STATUS bit masks and bit positions */ -#define USB_EP_STALLF_bm 0x80 /* Endpoint Stall Flag bit mask. */ -#define USB_EP_STALLF_bp 7 /* Endpoint Stall Flag bit position. */ - -#define USB_EP_CRC_bm 0x80 /* CRC Error Flag bit mask. */ -#define USB_EP_CRC_bp 7 /* CRC Error Flag bit position. */ - -#define USB_EP_UNF_bm 0x40 /* Underflow Enpoint FLag bit mask. */ -#define USB_EP_UNF_bp 6 /* Underflow Enpoint FLag bit position. */ - -#define USB_EP_OVF_bm 0x40 /* Overflow Enpoint Flag for Output Endpoints bit mask. */ -#define USB_EP_OVF_bp 6 /* Overflow Enpoint Flag for Output Endpoints bit position. */ - -#define USB_EP_TRNCOMPL0_bm 0x20 /* Transaction Complete 0 Flag bit mask. */ -#define USB_EP_TRNCOMPL0_bp 5 /* Transaction Complete 0 Flag bit position. */ - -#define USB_EP_TRNCOMPL1_bm 0x10 /* Transaction Complete 1 Flag bit mask. */ -#define USB_EP_TRNCOMPL1_bp 4 /* Transaction Complete 1 Flag bit position. */ - -#define USB_EP_SETUP_bm 0x10 /* SETUP Transaction Complete Flag bit mask. */ -#define USB_EP_SETUP_bp 4 /* SETUP Transaction Complete Flag bit position. */ - -#define USB_EP_BANK_bm 0x08 /* Bank Select bit mask. */ -#define USB_EP_BANK_bp 3 /* Bank Select bit position. */ - -#define USB_EP_BUSNACK1_bm 0x04 /* Data Buffer 1 Not Acknowledge bit mask. */ -#define USB_EP_BUSNACK1_bp 2 /* Data Buffer 1 Not Acknowledge bit position. */ - -#define USB_EP_BUSNACK0_bm 0x02 /* Data Buffer 0 Not Acknowledge bit mask. */ -#define USB_EP_BUSNACK0_bp 1 /* Data Buffer 0 Not Acknowledge bit position. */ - -#define USB_EP_TOGGLE_bm 0x01 /* Data Toggle bit mask. */ -#define USB_EP_TOGGLE_bp 0 /* Data Toggle bit position. */ - -/* USB_EP.CTRL bit masks and bit positions */ -#define USB_EP_TYPE_gm 0xC0 /* Endpoint Type group mask. */ -#define USB_EP_TYPE_gp 6 /* Endpoint Type group position. */ -#define USB_EP_TYPE0_bm (1<<6) /* Endpoint Type bit 0 mask. */ -#define USB_EP_TYPE0_bp 6 /* Endpoint Type bit 0 position. */ -#define USB_EP_TYPE1_bm (1<<7) /* Endpoint Type bit 1 mask. */ -#define USB_EP_TYPE1_bp 7 /* Endpoint Type bit 1 position. */ - -#define USB_EP_MULTIPKT_bm 0x20 /* Multi Packet Transfer Enable bit mask. */ -#define USB_EP_MULTIPKT_bp 5 /* Multi Packet Transfer Enable bit position. */ - -#define USB_EP_PINGPONG_bm 0x10 /* Ping-Pong Enable bit mask. */ -#define USB_EP_PINGPONG_bp 4 /* Ping-Pong Enable bit position. */ - -#define USB_EP_INTDSBL_bm 0x08 /* Interrupt Disable bit mask. */ -#define USB_EP_INTDSBL_bp 3 /* Interrupt Disable bit position. */ - -#define USB_EP_STALL_bm 0x04 /* Data Stall bit mask. */ -#define USB_EP_STALL_bp 2 /* Data Stall bit position. */ - -#define USB_EP_BUFSIZE_gm 0x07 /* Data Buffer Size group mask. */ -#define USB_EP_BUFSIZE_gp 0 /* Data Buffer Size group position. */ -#define USB_EP_BUFSIZE0_bm (1<<0) /* Data Buffer Size bit 0 mask. */ -#define USB_EP_BUFSIZE0_bp 0 /* Data Buffer Size bit 0 position. */ -#define USB_EP_BUFSIZE1_bm (1<<1) /* Data Buffer Size bit 1 mask. */ -#define USB_EP_BUFSIZE1_bp 1 /* Data Buffer Size bit 1 position. */ -#define USB_EP_BUFSIZE2_bm (1<<2) /* Data Buffer Size bit 2 mask. */ -#define USB_EP_BUFSIZE2_bp 2 /* Data Buffer Size bit 2 position. */ - -/* USB_EP.CNT bit masks and bit positions */ -#define USB_EP_ZLP_bm 0x8000 /* Zero Length Packet bit mask. */ -#define USB_EP_ZLP_bp 15 /* Zero Length Packet bit position. */ - -/* USB.CTRLA bit masks and bit positions */ -#define USB_ENABLE_bm 0x80 /* USB Enable bit mask. */ -#define USB_ENABLE_bp 7 /* USB Enable bit position. */ - -#define USB_SPEED_bm 0x40 /* Speed Select bit mask. */ -#define USB_SPEED_bp 6 /* Speed Select bit position. */ - -#define USB_FIFOEN_bm 0x20 /* USB FIFO Enable bit mask. */ -#define USB_FIFOEN_bp 5 /* USB FIFO Enable bit position. */ - -#define USB_STFRNUM_bm 0x10 /* Store Frame Number Enable bit mask. */ -#define USB_STFRNUM_bp 4 /* Store Frame Number Enable bit position. */ - -#define USB_MAXEP_gm 0x0F /* Maximum Endpoint Addresses group mask. */ -#define USB_MAXEP_gp 0 /* Maximum Endpoint Addresses group position. */ -#define USB_MAXEP0_bm (1<<0) /* Maximum Endpoint Addresses bit 0 mask. */ -#define USB_MAXEP0_bp 0 /* Maximum Endpoint Addresses bit 0 position. */ -#define USB_MAXEP1_bm (1<<1) /* Maximum Endpoint Addresses bit 1 mask. */ -#define USB_MAXEP1_bp 1 /* Maximum Endpoint Addresses bit 1 position. */ -#define USB_MAXEP2_bm (1<<2) /* Maximum Endpoint Addresses bit 2 mask. */ -#define USB_MAXEP2_bp 2 /* Maximum Endpoint Addresses bit 2 position. */ -#define USB_MAXEP3_bm (1<<3) /* Maximum Endpoint Addresses bit 3 mask. */ -#define USB_MAXEP3_bp 3 /* Maximum Endpoint Addresses bit 3 position. */ - -/* USB.CTRLB bit masks and bit positions */ -#define USB_PULLRST_bm 0x10 /* Pull during Reset bit mask. */ -#define USB_PULLRST_bp 4 /* Pull during Reset bit position. */ - -#define USB_RWAKEUP_bm 0x04 /* Remote Wake-up bit mask. */ -#define USB_RWAKEUP_bp 2 /* Remote Wake-up bit position. */ - -#define USB_GNACK_bm 0x02 /* Global NACK bit mask. */ -#define USB_GNACK_bp 1 /* Global NACK bit position. */ - -#define USB_ATTACH_bm 0x01 /* Attach bit mask. */ -#define USB_ATTACH_bp 0 /* Attach bit position. */ - -/* USB.STATUS bit masks and bit positions */ -#define USB_URESUME_bm 0x08 /* Upstream Resume bit mask. */ -#define USB_URESUME_bp 3 /* Upstream Resume bit position. */ - -#define USB_RESUME_bm 0x04 /* Resume bit mask. */ -#define USB_RESUME_bp 2 /* Resume bit position. */ - -#define USB_SUSPEND_bm 0x02 /* Bus Suspended bit mask. */ -#define USB_SUSPEND_bp 1 /* Bus Suspended bit position. */ - -#define USB_BUSRST_bm 0x01 /* Bus Reset bit mask. */ -#define USB_BUSRST_bp 0 /* Bus Reset bit position. */ - -/* USB.ADDR bit masks and bit positions */ -#define USB_ADDR_gm 0x7F /* Device Address group mask. */ -#define USB_ADDR_gp 0 /* Device Address group position. */ -#define USB_ADDR0_bm (1<<0) /* Device Address bit 0 mask. */ -#define USB_ADDR0_bp 0 /* Device Address bit 0 position. */ -#define USB_ADDR1_bm (1<<1) /* Device Address bit 1 mask. */ -#define USB_ADDR1_bp 1 /* Device Address bit 1 position. */ -#define USB_ADDR2_bm (1<<2) /* Device Address bit 2 mask. */ -#define USB_ADDR2_bp 2 /* Device Address bit 2 position. */ -#define USB_ADDR3_bm (1<<3) /* Device Address bit 3 mask. */ -#define USB_ADDR3_bp 3 /* Device Address bit 3 position. */ -#define USB_ADDR4_bm (1<<4) /* Device Address bit 4 mask. */ -#define USB_ADDR4_bp 4 /* Device Address bit 4 position. */ -#define USB_ADDR5_bm (1<<5) /* Device Address bit 5 mask. */ -#define USB_ADDR5_bp 5 /* Device Address bit 5 position. */ -#define USB_ADDR6_bm (1<<6) /* Device Address bit 6 mask. */ -#define USB_ADDR6_bp 6 /* Device Address bit 6 position. */ - -/* USB.FIFOWP bit masks and bit positions */ -#define USB_FIFOWP_gm 0x1F /* FIFO Write Pointer group mask. */ -#define USB_FIFOWP_gp 0 /* FIFO Write Pointer group position. */ -#define USB_FIFOWP0_bm (1<<0) /* FIFO Write Pointer bit 0 mask. */ -#define USB_FIFOWP0_bp 0 /* FIFO Write Pointer bit 0 position. */ -#define USB_FIFOWP1_bm (1<<1) /* FIFO Write Pointer bit 1 mask. */ -#define USB_FIFOWP1_bp 1 /* FIFO Write Pointer bit 1 position. */ -#define USB_FIFOWP2_bm (1<<2) /* FIFO Write Pointer bit 2 mask. */ -#define USB_FIFOWP2_bp 2 /* FIFO Write Pointer bit 2 position. */ -#define USB_FIFOWP3_bm (1<<3) /* FIFO Write Pointer bit 3 mask. */ -#define USB_FIFOWP3_bp 3 /* FIFO Write Pointer bit 3 position. */ -#define USB_FIFOWP4_bm (1<<4) /* FIFO Write Pointer bit 4 mask. */ -#define USB_FIFOWP4_bp 4 /* FIFO Write Pointer bit 4 position. */ - -/* USB.FIFORP bit masks and bit positions */ -#define USB_FIFORP_gm 0x1F /* FIFO Read Pointer group mask. */ -#define USB_FIFORP_gp 0 /* FIFO Read Pointer group position. */ -#define USB_FIFORP0_bm (1<<0) /* FIFO Read Pointer bit 0 mask. */ -#define USB_FIFORP0_bp 0 /* FIFO Read Pointer bit 0 position. */ -#define USB_FIFORP1_bm (1<<1) /* FIFO Read Pointer bit 1 mask. */ -#define USB_FIFORP1_bp 1 /* FIFO Read Pointer bit 1 position. */ -#define USB_FIFORP2_bm (1<<2) /* FIFO Read Pointer bit 2 mask. */ -#define USB_FIFORP2_bp 2 /* FIFO Read Pointer bit 2 position. */ -#define USB_FIFORP3_bm (1<<3) /* FIFO Read Pointer bit 3 mask. */ -#define USB_FIFORP3_bp 3 /* FIFO Read Pointer bit 3 position. */ -#define USB_FIFORP4_bm (1<<4) /* FIFO Read Pointer bit 4 mask. */ -#define USB_FIFORP4_bp 4 /* FIFO Read Pointer bit 4 position. */ - -/* USB.INTCTRLA bit masks and bit positions */ -#define USB_SOFIE_bm 0x80 /* Start Of Frame Interrupt Enable bit mask. */ -#define USB_SOFIE_bp 7 /* Start Of Frame Interrupt Enable bit position. */ - -#define USB_BUSEVIE_bm 0x40 /* Bus Event Interrupt Enable bit mask. */ -#define USB_BUSEVIE_bp 6 /* Bus Event Interrupt Enable bit position. */ - -#define USB_BUSERRIE_bm 0x20 /* Bus Error Interrupt Enable bit mask. */ -#define USB_BUSERRIE_bp 5 /* Bus Error Interrupt Enable bit position. */ - -#define USB_STALLIE_bm 0x10 /* STALL Interrupt Enable bit mask. */ -#define USB_STALLIE_bp 4 /* STALL Interrupt Enable bit position. */ - -#define USB_INTLVL_gm 0x03 /* Interrupt Level group mask. */ -#define USB_INTLVL_gp 0 /* Interrupt Level group position. */ -#define USB_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */ -#define USB_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */ -#define USB_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ -#define USB_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */ - -/* USB.INTCTRLB bit masks and bit positions */ -#define USB_TRNIE_bm 0x02 /* Transaction Complete Interrupt Enable bit mask. */ -#define USB_TRNIE_bp 1 /* Transaction Complete Interrupt Enable bit position. */ - -#define USB_SETUPIE_bm 0x01 /* SETUP Transaction Complete Interrupt Enable bit mask. */ -#define USB_SETUPIE_bp 0 /* SETUP Transaction Complete Interrupt Enable bit position. */ - -/* USB.INTFLAGSACLR bit masks and bit positions */ -#define USB_SOFIF_bm 0x80 /* Start Of Frame Interrupt Flag bit mask. */ -#define USB_SOFIF_bp 7 /* Start Of Frame Interrupt Flag bit position. */ - -#define USB_SUSPENDIF_bm 0x40 /* Suspend Interrupt Flag bit mask. */ -#define USB_SUSPENDIF_bp 6 /* Suspend Interrupt Flag bit position. */ - -#define USB_RESUMEIF_bm 0x20 /* Resume Interrupt Flag bit mask. */ -#define USB_RESUMEIF_bp 5 /* Resume Interrupt Flag bit position. */ - -#define USB_RSTIF_bm 0x10 /* Reset Interrupt Flag bit mask. */ -#define USB_RSTIF_bp 4 /* Reset Interrupt Flag bit position. */ - -#define USB_CRCIF_bm 0x08 /* Isochronous CRC Error Interrupt Flag bit mask. */ -#define USB_CRCIF_bp 3 /* Isochronous CRC Error Interrupt Flag bit position. */ - -#define USB_UNFIF_bm 0x04 /* Underflow Interrupt Flag bit mask. */ -#define USB_UNFIF_bp 2 /* Underflow Interrupt Flag bit position. */ - -#define USB_OVFIF_bm 0x02 /* Overflow Interrupt Flag bit mask. */ -#define USB_OVFIF_bp 1 /* Overflow Interrupt Flag bit position. */ - -#define USB_STALLIF_bm 0x01 /* STALL Interrupt Flag bit mask. */ -#define USB_STALLIF_bp 0 /* STALL Interrupt Flag bit position. */ - -/* USB.INTFLAGSASET bit masks and bit positions */ -/* USB_SOFIF Predefined. */ -/* USB_SOFIF Predefined. */ - -/* USB_SUSPENDIF Predefined. */ -/* USB_SUSPENDIF Predefined. */ - -/* USB_RESUMEIF Predefined. */ -/* USB_RESUMEIF Predefined. */ - -/* USB_RSTIF Predefined. */ -/* USB_RSTIF Predefined. */ - -/* USB_CRCIF Predefined. */ -/* USB_CRCIF Predefined. */ - -/* USB_UNFIF Predefined. */ -/* USB_UNFIF Predefined. */ - -/* USB_OVFIF Predefined. */ -/* USB_OVFIF Predefined. */ - -/* USB_STALLIF Predefined. */ -/* USB_STALLIF Predefined. */ - -/* USB.INTFLAGSBCLR bit masks and bit positions */ -#define USB_TRNIF_bm 0x02 /* Transaction Complete Interrupt Flag bit mask. */ -#define USB_TRNIF_bp 1 /* Transaction Complete Interrupt Flag bit position. */ - -#define USB_SETUPIF_bm 0x01 /* SETUP Transaction Complete Interrupt Flag bit mask. */ -#define USB_SETUPIF_bp 0 /* SETUP Transaction Complete Interrupt Flag bit position. */ - -/* USB.INTFLAGSBSET bit masks and bit positions */ -/* USB_TRNIF Predefined. */ -/* USB_TRNIF Predefined. */ - -/* USB_SETUPIF Predefined. */ -/* USB_SETUPIF Predefined. */ - -/* PORT - I/O Port Configuration */ -/* PORT.INTCTRL bit masks and bit positions */ -#define PORT_INT1LVL_gm 0x0C /* Port Interrupt 1 Level group mask. */ -#define PORT_INT1LVL_gp 2 /* Port Interrupt 1 Level group position. */ -#define PORT_INT1LVL0_bm (1<<2) /* Port Interrupt 1 Level bit 0 mask. */ -#define PORT_INT1LVL0_bp 2 /* Port Interrupt 1 Level bit 0 position. */ -#define PORT_INT1LVL1_bm (1<<3) /* Port Interrupt 1 Level bit 1 mask. */ -#define PORT_INT1LVL1_bp 3 /* Port Interrupt 1 Level bit 1 position. */ - -#define PORT_INT0LVL_gm 0x03 /* Port Interrupt 0 Level group mask. */ -#define PORT_INT0LVL_gp 0 /* Port Interrupt 0 Level group position. */ -#define PORT_INT0LVL0_bm (1<<0) /* Port Interrupt 0 Level bit 0 mask. */ -#define PORT_INT0LVL0_bp 0 /* Port Interrupt 0 Level bit 0 position. */ -#define PORT_INT0LVL1_bm (1<<1) /* Port Interrupt 0 Level bit 1 mask. */ -#define PORT_INT0LVL1_bp 1 /* Port Interrupt 0 Level bit 1 position. */ - -/* PORT.INTFLAGS bit masks and bit positions */ -#define PORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ -#define PORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ - -#define PORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ -#define PORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ - -/* PORT.REMAP bit masks and bit positions */ -#define PORT_SPI_bm 0x20 /* SPI bit mask. */ -#define PORT_SPI_bp 5 /* SPI bit position. */ - -#define PORT_USART0_bm 0x10 /* USART0 bit mask. */ -#define PORT_USART0_bp 4 /* USART0 bit position. */ - -#define PORT_TC0D_bm 0x08 /* Timer/Counter 0 Output Compare D bit mask. */ -#define PORT_TC0D_bp 3 /* Timer/Counter 0 Output Compare D bit position. */ - -#define PORT_TC0C_bm 0x04 /* Timer/Counter 0 Output Compare C bit mask. */ -#define PORT_TC0C_bp 2 /* Timer/Counter 0 Output Compare C bit position. */ - -#define PORT_TC0B_bm 0x02 /* Timer/Counter 0 Output Compare B bit mask. */ -#define PORT_TC0B_bp 1 /* Timer/Counter 0 Output Compare B bit position. */ - -#define PORT_TC0A_bm 0x01 /* Timer/Counter 0 Output Compare A bit mask. */ -#define PORT_TC0A_bp 0 /* Timer/Counter 0 Output Compare A bit position. */ - -/* PORT.PIN0CTRL bit masks and bit positions */ -#define PORT_SRLEN_bm 0x80 /* Slew Rate Enable bit mask. */ -#define PORT_SRLEN_bp 7 /* Slew Rate Enable bit position. */ - -#define PORT_INVEN_bm 0x40 /* Inverted I/O Enable bit mask. */ -#define PORT_INVEN_bp 6 /* Inverted I/O Enable bit position. */ - -#define PORT_OPC_gm 0x38 /* Output/Pull Configuration group mask. */ -#define PORT_OPC_gp 3 /* Output/Pull Configuration group position. */ -#define PORT_OPC0_bm (1<<3) /* Output/Pull Configuration bit 0 mask. */ -#define PORT_OPC0_bp 3 /* Output/Pull Configuration bit 0 position. */ -#define PORT_OPC1_bm (1<<4) /* Output/Pull Configuration bit 1 mask. */ -#define PORT_OPC1_bp 4 /* Output/Pull Configuration bit 1 position. */ -#define PORT_OPC2_bm (1<<5) /* Output/Pull Configuration bit 2 mask. */ -#define PORT_OPC2_bp 5 /* Output/Pull Configuration bit 2 position. */ - -#define PORT_ISC_gm 0x07 /* Input/Sense Configuration group mask. */ -#define PORT_ISC_gp 0 /* Input/Sense Configuration group position. */ -#define PORT_ISC0_bm (1<<0) /* Input/Sense Configuration bit 0 mask. */ -#define PORT_ISC0_bp 0 /* Input/Sense Configuration bit 0 position. */ -#define PORT_ISC1_bm (1<<1) /* Input/Sense Configuration bit 1 mask. */ -#define PORT_ISC1_bp 1 /* Input/Sense Configuration bit 1 position. */ -#define PORT_ISC2_bm (1<<2) /* Input/Sense Configuration bit 2 mask. */ -#define PORT_ISC2_bp 2 /* Input/Sense Configuration bit 2 position. */ - -/* PORT.PIN1CTRL bit masks and bit positions */ -/* PORT_SRLEN Predefined. */ -/* PORT_SRLEN Predefined. */ - -/* PORT_INVEN Predefined. */ -/* PORT_INVEN Predefined. */ - -/* PORT_OPC Predefined. */ -/* PORT_OPC Predefined. */ - -/* PORT_ISC Predefined. */ -/* PORT_ISC Predefined. */ - -/* PORT.PIN2CTRL bit masks and bit positions */ -/* PORT_SRLEN Predefined. */ -/* PORT_SRLEN Predefined. */ - -/* PORT_INVEN Predefined. */ -/* PORT_INVEN Predefined. */ - -/* PORT_OPC Predefined. */ -/* PORT_OPC Predefined. */ - -/* PORT_ISC Predefined. */ -/* PORT_ISC Predefined. */ - -/* PORT.PIN3CTRL bit masks and bit positions */ -/* PORT_SRLEN Predefined. */ -/* PORT_SRLEN Predefined. */ - -/* PORT_INVEN Predefined. */ -/* PORT_INVEN Predefined. */ - -/* PORT_OPC Predefined. */ -/* PORT_OPC Predefined. */ - -/* PORT_ISC Predefined. */ -/* PORT_ISC Predefined. */ - -/* PORT.PIN4CTRL bit masks and bit positions */ -/* PORT_SRLEN Predefined. */ -/* PORT_SRLEN Predefined. */ - -/* PORT_INVEN Predefined. */ -/* PORT_INVEN Predefined. */ - -/* PORT_OPC Predefined. */ -/* PORT_OPC Predefined. */ - -/* PORT_ISC Predefined. */ -/* PORT_ISC Predefined. */ - -/* PORT.PIN5CTRL bit masks and bit positions */ -/* PORT_SRLEN Predefined. */ -/* PORT_SRLEN Predefined. */ - -/* PORT_INVEN Predefined. */ -/* PORT_INVEN Predefined. */ - -/* PORT_OPC Predefined. */ -/* PORT_OPC Predefined. */ - -/* PORT_ISC Predefined. */ -/* PORT_ISC Predefined. */ - -/* PORT.PIN6CTRL bit masks and bit positions */ -/* PORT_SRLEN Predefined. */ -/* PORT_SRLEN Predefined. */ - -/* PORT_INVEN Predefined. */ -/* PORT_INVEN Predefined. */ - -/* PORT_OPC Predefined. */ -/* PORT_OPC Predefined. */ - -/* PORT_ISC Predefined. */ -/* PORT_ISC Predefined. */ - -/* PORT.PIN7CTRL bit masks and bit positions */ -/* PORT_SRLEN Predefined. */ -/* PORT_SRLEN Predefined. */ - -/* PORT_INVEN Predefined. */ -/* PORT_INVEN Predefined. */ - -/* PORT_OPC Predefined. */ -/* PORT_OPC Predefined. */ - -/* PORT_ISC Predefined. */ -/* PORT_ISC Predefined. */ - -/* TC - 16-bit Timer/Counter With PWM */ -/* TC0.CTRLA bit masks and bit positions */ -#define TC0_CLKSEL_gm 0x0F /* Clock Selection group mask. */ -#define TC0_CLKSEL_gp 0 /* Clock Selection group position. */ -#define TC0_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ -#define TC0_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ -#define TC0_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ -#define TC0_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ -#define TC0_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ -#define TC0_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ -#define TC0_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ -#define TC0_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ - -/* TC0.CTRLB bit masks and bit positions */ -#define TC0_CCDEN_bm 0x80 /* Compare or Capture D Enable bit mask. */ -#define TC0_CCDEN_bp 7 /* Compare or Capture D Enable bit position. */ - -#define TC0_CCCEN_bm 0x40 /* Compare or Capture C Enable bit mask. */ -#define TC0_CCCEN_bp 6 /* Compare or Capture C Enable bit position. */ - -#define TC0_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ -#define TC0_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ - -#define TC0_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ -#define TC0_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ - -#define TC0_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ -#define TC0_WGMODE_gp 0 /* Waveform generation mode group position. */ -#define TC0_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ -#define TC0_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ -#define TC0_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ -#define TC0_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ -#define TC0_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ -#define TC0_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ - -/* TC0.CTRLC bit masks and bit positions */ -#define TC0_CMPD_bm 0x08 /* Compare D Output Value bit mask. */ -#define TC0_CMPD_bp 3 /* Compare D Output Value bit position. */ - -#define TC0_CMPC_bm 0x04 /* Compare C Output Value bit mask. */ -#define TC0_CMPC_bp 2 /* Compare C Output Value bit position. */ - -#define TC0_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ -#define TC0_CMPB_bp 1 /* Compare B Output Value bit position. */ - -#define TC0_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ -#define TC0_CMPA_bp 0 /* Compare A Output Value bit position. */ - -/* TC0.CTRLD bit masks and bit positions */ -#define TC0_EVACT_gm 0xE0 /* Event Action group mask. */ -#define TC0_EVACT_gp 5 /* Event Action group position. */ -#define TC0_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ -#define TC0_EVACT0_bp 5 /* Event Action bit 0 position. */ -#define TC0_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ -#define TC0_EVACT1_bp 6 /* Event Action bit 1 position. */ -#define TC0_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ -#define TC0_EVACT2_bp 7 /* Event Action bit 2 position. */ - -#define TC0_EVDLY_bm 0x10 /* Event Delay bit mask. */ -#define TC0_EVDLY_bp 4 /* Event Delay bit position. */ - -#define TC0_EVSEL_gm 0x0F /* Event Source Select group mask. */ -#define TC0_EVSEL_gp 0 /* Event Source Select group position. */ -#define TC0_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ -#define TC0_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ -#define TC0_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ -#define TC0_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ -#define TC0_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ -#define TC0_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ -#define TC0_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ -#define TC0_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ - -/* TC0.CTRLE bit masks and bit positions */ -#define TC0_BYTEM_gm 0x03 /* Byte Mode group mask. */ -#define TC0_BYTEM_gp 0 /* Byte Mode group position. */ -#define TC0_BYTEM0_bm (1<<0) /* Byte Mode bit 0 mask. */ -#define TC0_BYTEM0_bp 0 /* Byte Mode bit 0 position. */ -#define TC0_BYTEM1_bm (1<<1) /* Byte Mode bit 1 mask. */ -#define TC0_BYTEM1_bp 1 /* Byte Mode bit 1 position. */ - -/* TC0.INTCTRLA bit masks and bit positions */ -#define TC0_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ -#define TC0_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ -#define TC0_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ -#define TC0_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ -#define TC0_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ -#define TC0_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ - -#define TC0_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ -#define TC0_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ -#define TC0_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ -#define TC0_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ -#define TC0_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ -#define TC0_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ - -/* TC0.INTCTRLB bit masks and bit positions */ -#define TC0_CCDINTLVL_gm 0xC0 /* Compare or Capture D Interrupt Level group mask. */ -#define TC0_CCDINTLVL_gp 6 /* Compare or Capture D Interrupt Level group position. */ -#define TC0_CCDINTLVL0_bm (1<<6) /* Compare or Capture D Interrupt Level bit 0 mask. */ -#define TC0_CCDINTLVL0_bp 6 /* Compare or Capture D Interrupt Level bit 0 position. */ -#define TC0_CCDINTLVL1_bm (1<<7) /* Compare or Capture D Interrupt Level bit 1 mask. */ -#define TC0_CCDINTLVL1_bp 7 /* Compare or Capture D Interrupt Level bit 1 position. */ - -#define TC0_CCCINTLVL_gm 0x30 /* Compare or Capture C Interrupt Level group mask. */ -#define TC0_CCCINTLVL_gp 4 /* Compare or Capture C Interrupt Level group position. */ -#define TC0_CCCINTLVL0_bm (1<<4) /* Compare or Capture C Interrupt Level bit 0 mask. */ -#define TC0_CCCINTLVL0_bp 4 /* Compare or Capture C Interrupt Level bit 0 position. */ -#define TC0_CCCINTLVL1_bm (1<<5) /* Compare or Capture C Interrupt Level bit 1 mask. */ -#define TC0_CCCINTLVL1_bp 5 /* Compare or Capture C Interrupt Level bit 1 position. */ - -#define TC0_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ -#define TC0_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ -#define TC0_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ -#define TC0_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ -#define TC0_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ -#define TC0_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ - -#define TC0_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ -#define TC0_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ -#define TC0_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ -#define TC0_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ -#define TC0_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ -#define TC0_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ - -/* TC0.CTRLFCLR bit masks and bit positions */ -#define TC0_CMD_gm 0x0C /* Command group mask. */ -#define TC0_CMD_gp 2 /* Command group position. */ -#define TC0_CMD0_bm (1<<2) /* Command bit 0 mask. */ -#define TC0_CMD0_bp 2 /* Command bit 0 position. */ -#define TC0_CMD1_bm (1<<3) /* Command bit 1 mask. */ -#define TC0_CMD1_bp 3 /* Command bit 1 position. */ - -#define TC0_LUPD_bm 0x02 /* Lock Update bit mask. */ -#define TC0_LUPD_bp 1 /* Lock Update bit position. */ - -#define TC0_DIR_bm 0x01 /* Direction bit mask. */ -#define TC0_DIR_bp 0 /* Direction bit position. */ - -/* TC0.CTRLFSET bit masks and bit positions */ -/* TC0_CMD Predefined. */ -/* TC0_CMD Predefined. */ - -/* TC0_LUPD Predefined. */ -/* TC0_LUPD Predefined. */ - -/* TC0_DIR Predefined. */ -/* TC0_DIR Predefined. */ - -/* TC0.CTRLGCLR bit masks and bit positions */ -#define TC0_CCDBV_bm 0x10 /* Compare or Capture D Buffer Valid bit mask. */ -#define TC0_CCDBV_bp 4 /* Compare or Capture D Buffer Valid bit position. */ - -#define TC0_CCCBV_bm 0x08 /* Compare or Capture C Buffer Valid bit mask. */ -#define TC0_CCCBV_bp 3 /* Compare or Capture C Buffer Valid bit position. */ - -#define TC0_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ -#define TC0_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ - -#define TC0_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ -#define TC0_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ - -#define TC0_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ -#define TC0_PERBV_bp 0 /* Period Buffer Valid bit position. */ - -/* TC0.CTRLGSET bit masks and bit positions */ -/* TC0_CCDBV Predefined. */ -/* TC0_CCDBV Predefined. */ - -/* TC0_CCCBV Predefined. */ -/* TC0_CCCBV Predefined. */ - -/* TC0_CCBBV Predefined. */ -/* TC0_CCBBV Predefined. */ - -/* TC0_CCABV Predefined. */ -/* TC0_CCABV Predefined. */ - -/* TC0_PERBV Predefined. */ -/* TC0_PERBV Predefined. */ - -/* TC0.INTFLAGS bit masks and bit positions */ -#define TC0_CCDIF_bm 0x80 /* Compare or Capture D Interrupt Flag bit mask. */ -#define TC0_CCDIF_bp 7 /* Compare or Capture D Interrupt Flag bit position. */ - -#define TC0_CCCIF_bm 0x40 /* Compare or Capture C Interrupt Flag bit mask. */ -#define TC0_CCCIF_bp 6 /* Compare or Capture C Interrupt Flag bit position. */ - -#define TC0_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ -#define TC0_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ - -#define TC0_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ -#define TC0_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ - -#define TC0_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ -#define TC0_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ - -#define TC0_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ -#define TC0_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ - -/* TC1.CTRLA bit masks and bit positions */ -#define TC1_CLKSEL_gm 0x0F /* Clock Selection group mask. */ -#define TC1_CLKSEL_gp 0 /* Clock Selection group position. */ -#define TC1_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ -#define TC1_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ -#define TC1_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ -#define TC1_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ -#define TC1_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ -#define TC1_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ -#define TC1_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ -#define TC1_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ - -/* TC1.CTRLB bit masks and bit positions */ -#define TC1_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ -#define TC1_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ - -#define TC1_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ -#define TC1_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ - -#define TC1_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ -#define TC1_WGMODE_gp 0 /* Waveform generation mode group position. */ -#define TC1_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ -#define TC1_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ -#define TC1_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ -#define TC1_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ -#define TC1_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ -#define TC1_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ - -/* TC1.CTRLC bit masks and bit positions */ -#define TC1_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ -#define TC1_CMPB_bp 1 /* Compare B Output Value bit position. */ - -#define TC1_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ -#define TC1_CMPA_bp 0 /* Compare A Output Value bit position. */ - -/* TC1.CTRLD bit masks and bit positions */ -#define TC1_EVACT_gm 0xE0 /* Event Action group mask. */ -#define TC1_EVACT_gp 5 /* Event Action group position. */ -#define TC1_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ -#define TC1_EVACT0_bp 5 /* Event Action bit 0 position. */ -#define TC1_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ -#define TC1_EVACT1_bp 6 /* Event Action bit 1 position. */ -#define TC1_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ -#define TC1_EVACT2_bp 7 /* Event Action bit 2 position. */ - -#define TC1_EVDLY_bm 0x10 /* Event Delay bit mask. */ -#define TC1_EVDLY_bp 4 /* Event Delay bit position. */ - -#define TC1_EVSEL_gm 0x0F /* Event Source Select group mask. */ -#define TC1_EVSEL_gp 0 /* Event Source Select group position. */ -#define TC1_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ -#define TC1_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ -#define TC1_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ -#define TC1_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ -#define TC1_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ -#define TC1_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ -#define TC1_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ -#define TC1_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ - -/* TC1.CTRLE bit masks and bit positions */ -#define TC1_BYTEM_bm 0x01 /* Byte Mode bit mask. */ -#define TC1_BYTEM_bp 0 /* Byte Mode bit position. */ - -/* TC1.INTCTRLA bit masks and bit positions */ -#define TC1_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ -#define TC1_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ -#define TC1_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ -#define TC1_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ -#define TC1_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ -#define TC1_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ - -#define TC1_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ -#define TC1_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ -#define TC1_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ -#define TC1_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ -#define TC1_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ -#define TC1_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ - -/* TC1.INTCTRLB bit masks and bit positions */ -#define TC1_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ -#define TC1_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ -#define TC1_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ -#define TC1_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ -#define TC1_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ -#define TC1_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ - -#define TC1_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ -#define TC1_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ -#define TC1_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ -#define TC1_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ -#define TC1_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ -#define TC1_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ - -/* TC1.CTRLFCLR bit masks and bit positions */ -#define TC1_CMD_gm 0x0C /* Command group mask. */ -#define TC1_CMD_gp 2 /* Command group position. */ -#define TC1_CMD0_bm (1<<2) /* Command bit 0 mask. */ -#define TC1_CMD0_bp 2 /* Command bit 0 position. */ -#define TC1_CMD1_bm (1<<3) /* Command bit 1 mask. */ -#define TC1_CMD1_bp 3 /* Command bit 1 position. */ - -#define TC1_LUPD_bm 0x02 /* Lock Update bit mask. */ -#define TC1_LUPD_bp 1 /* Lock Update bit position. */ - -#define TC1_DIR_bm 0x01 /* Direction bit mask. */ -#define TC1_DIR_bp 0 /* Direction bit position. */ - -/* TC1.CTRLFSET bit masks and bit positions */ -/* TC1_CMD Predefined. */ -/* TC1_CMD Predefined. */ - -/* TC1_LUPD Predefined. */ -/* TC1_LUPD Predefined. */ - -/* TC1_DIR Predefined. */ -/* TC1_DIR Predefined. */ - -/* TC1.CTRLGCLR bit masks and bit positions */ -#define TC1_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ -#define TC1_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ - -#define TC1_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ -#define TC1_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ - -#define TC1_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ -#define TC1_PERBV_bp 0 /* Period Buffer Valid bit position. */ - -/* TC1.CTRLGSET bit masks and bit positions */ -/* TC1_CCBBV Predefined. */ -/* TC1_CCBBV Predefined. */ - -/* TC1_CCABV Predefined. */ -/* TC1_CCABV Predefined. */ - -/* TC1_PERBV Predefined. */ -/* TC1_PERBV Predefined. */ - -/* TC1.INTFLAGS bit masks and bit positions */ -#define TC1_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ -#define TC1_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ - -#define TC1_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ -#define TC1_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ - -#define TC1_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ -#define TC1_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ - -#define TC1_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ -#define TC1_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ - -/* TC2 - 16-bit Timer/Counter type 2 */ -/* TC2.CTRLA bit masks and bit positions */ -#define TC2_CLKSEL_gm 0x0F /* Clock Selection group mask. */ -#define TC2_CLKSEL_gp 0 /* Clock Selection group position. */ -#define TC2_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ -#define TC2_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ -#define TC2_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ -#define TC2_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ -#define TC2_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ -#define TC2_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ -#define TC2_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ -#define TC2_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ - -/* TC2.CTRLB bit masks and bit positions */ -#define TC2_HCMPDEN_bm 0x80 /* High Byte Compare D Enable bit mask. */ -#define TC2_HCMPDEN_bp 7 /* High Byte Compare D Enable bit position. */ - -#define TC2_HCMPCEN_bm 0x40 /* High Byte Compare C Enable bit mask. */ -#define TC2_HCMPCEN_bp 6 /* High Byte Compare C Enable bit position. */ - -#define TC2_HCMPBEN_bm 0x20 /* High Byte Compare B Enable bit mask. */ -#define TC2_HCMPBEN_bp 5 /* High Byte Compare B Enable bit position. */ - -#define TC2_HCMPAEN_bm 0x10 /* High Byte Compare A Enable bit mask. */ -#define TC2_HCMPAEN_bp 4 /* High Byte Compare A Enable bit position. */ - -#define TC2_LCMPDEN_bm 0x08 /* Low Byte Compare D Enable bit mask. */ -#define TC2_LCMPDEN_bp 3 /* Low Byte Compare D Enable bit position. */ - -#define TC2_LCMPCEN_bm 0x04 /* Low Byte Compare C Enable bit mask. */ -#define TC2_LCMPCEN_bp 2 /* Low Byte Compare C Enable bit position. */ - -#define TC2_LCMPBEN_bm 0x02 /* Low Byte Compare B Enable bit mask. */ -#define TC2_LCMPBEN_bp 1 /* Low Byte Compare B Enable bit position. */ - -#define TC2_LCMPAEN_bm 0x01 /* Low Byte Compare A Enable bit mask. */ -#define TC2_LCMPAEN_bp 0 /* Low Byte Compare A Enable bit position. */ - -/* TC2.CTRLC bit masks and bit positions */ -#define TC2_HCMPD_bm 0x80 /* High Byte Compare D Output Value bit mask. */ -#define TC2_HCMPD_bp 7 /* High Byte Compare D Output Value bit position. */ - -#define TC2_HCMPC_bm 0x40 /* High Byte Compare C Output Value bit mask. */ -#define TC2_HCMPC_bp 6 /* High Byte Compare C Output Value bit position. */ - -#define TC2_HCMPB_bm 0x20 /* High Byte Compare B Output Value bit mask. */ -#define TC2_HCMPB_bp 5 /* High Byte Compare B Output Value bit position. */ - -#define TC2_HCMPA_bm 0x10 /* High Byte Compare A Output Value bit mask. */ -#define TC2_HCMPA_bp 4 /* High Byte Compare A Output Value bit position. */ - -#define TC2_LCMPD_bm 0x08 /* Low Byte Compare D Output Value bit mask. */ -#define TC2_LCMPD_bp 3 /* Low Byte Compare D Output Value bit position. */ - -#define TC2_LCMPC_bm 0x04 /* Low Byte Compare C Output Value bit mask. */ -#define TC2_LCMPC_bp 2 /* Low Byte Compare C Output Value bit position. */ - -#define TC2_LCMPB_bm 0x02 /* Low Byte Compare B Output Value bit mask. */ -#define TC2_LCMPB_bp 1 /* Low Byte Compare B Output Value bit position. */ - -#define TC2_LCMPA_bm 0x01 /* Low Byte Compare A Output Value bit mask. */ -#define TC2_LCMPA_bp 0 /* Low Byte Compare A Output Value bit position. */ - -/* TC2.CTRLE bit masks and bit positions */ -#define TC2_BYTEM_gm 0x03 /* Byte Mode group mask. */ -#define TC2_BYTEM_gp 0 /* Byte Mode group position. */ -#define TC2_BYTEM0_bm (1<<0) /* Byte Mode bit 0 mask. */ -#define TC2_BYTEM0_bp 0 /* Byte Mode bit 0 position. */ -#define TC2_BYTEM1_bm (1<<1) /* Byte Mode bit 1 mask. */ -#define TC2_BYTEM1_bp 1 /* Byte Mode bit 1 position. */ - -/* TC2.INTCTRLA bit masks and bit positions */ -#define TC2_HUNFINTLVL_gm 0x0C /* High Byte Underflow Interrupt Level group mask. */ -#define TC2_HUNFINTLVL_gp 2 /* High Byte Underflow Interrupt Level group position. */ -#define TC2_HUNFINTLVL0_bm (1<<2) /* High Byte Underflow Interrupt Level bit 0 mask. */ -#define TC2_HUNFINTLVL0_bp 2 /* High Byte Underflow Interrupt Level bit 0 position. */ -#define TC2_HUNFINTLVL1_bm (1<<3) /* High Byte Underflow Interrupt Level bit 1 mask. */ -#define TC2_HUNFINTLVL1_bp 3 /* High Byte Underflow Interrupt Level bit 1 position. */ - -#define TC2_LUNFINTLVL_gm 0x03 /* Low Byte Underflow interrupt level group mask. */ -#define TC2_LUNFINTLVL_gp 0 /* Low Byte Underflow interrupt level group position. */ -#define TC2_LUNFINTLVL0_bm (1<<0) /* Low Byte Underflow interrupt level bit 0 mask. */ -#define TC2_LUNFINTLVL0_bp 0 /* Low Byte Underflow interrupt level bit 0 position. */ -#define TC2_LUNFINTLVL1_bm (1<<1) /* Low Byte Underflow interrupt level bit 1 mask. */ -#define TC2_LUNFINTLVL1_bp 1 /* Low Byte Underflow interrupt level bit 1 position. */ - -/* TC2.INTCTRLB bit masks and bit positions */ -#define TC2_LCMPDINTLVL_gm 0xC0 /* Low Byte Compare D Interrupt Level group mask. */ -#define TC2_LCMPDINTLVL_gp 6 /* Low Byte Compare D Interrupt Level group position. */ -#define TC2_LCMPDINTLVL0_bm (1<<6) /* Low Byte Compare D Interrupt Level bit 0 mask. */ -#define TC2_LCMPDINTLVL0_bp 6 /* Low Byte Compare D Interrupt Level bit 0 position. */ -#define TC2_LCMPDINTLVL1_bm (1<<7) /* Low Byte Compare D Interrupt Level bit 1 mask. */ -#define TC2_LCMPDINTLVL1_bp 7 /* Low Byte Compare D Interrupt Level bit 1 position. */ - -#define TC2_LCMPCINTLVL_gm 0x30 /* Low Byte Compare C Interrupt Level group mask. */ -#define TC2_LCMPCINTLVL_gp 4 /* Low Byte Compare C Interrupt Level group position. */ -#define TC2_LCMPCINTLVL0_bm (1<<4) /* Low Byte Compare C Interrupt Level bit 0 mask. */ -#define TC2_LCMPCINTLVL0_bp 4 /* Low Byte Compare C Interrupt Level bit 0 position. */ -#define TC2_LCMPCINTLVL1_bm (1<<5) /* Low Byte Compare C Interrupt Level bit 1 mask. */ -#define TC2_LCMPCINTLVL1_bp 5 /* Low Byte Compare C Interrupt Level bit 1 position. */ - -#define TC2_LCMPBINTLVL_gm 0x0C /* Low Byte Compare B Interrupt Level group mask. */ -#define TC2_LCMPBINTLVL_gp 2 /* Low Byte Compare B Interrupt Level group position. */ -#define TC2_LCMPBINTLVL0_bm (1<<2) /* Low Byte Compare B Interrupt Level bit 0 mask. */ -#define TC2_LCMPBINTLVL0_bp 2 /* Low Byte Compare B Interrupt Level bit 0 position. */ -#define TC2_LCMPBINTLVL1_bm (1<<3) /* Low Byte Compare B Interrupt Level bit 1 mask. */ -#define TC2_LCMPBINTLVL1_bp 3 /* Low Byte Compare B Interrupt Level bit 1 position. */ - -#define TC2_LCMPAINTLVL_gm 0x03 /* Low Byte Compare A Interrupt Level group mask. */ -#define TC2_LCMPAINTLVL_gp 0 /* Low Byte Compare A Interrupt Level group position. */ -#define TC2_LCMPAINTLVL0_bm (1<<0) /* Low Byte Compare A Interrupt Level bit 0 mask. */ -#define TC2_LCMPAINTLVL0_bp 0 /* Low Byte Compare A Interrupt Level bit 0 position. */ -#define TC2_LCMPAINTLVL1_bm (1<<1) /* Low Byte Compare A Interrupt Level bit 1 mask. */ -#define TC2_LCMPAINTLVL1_bp 1 /* Low Byte Compare A Interrupt Level bit 1 position. */ - -/* TC2.CTRLF bit masks and bit positions */ -#define TC2_CMD_gm 0x0C /* Command group mask. */ -#define TC2_CMD_gp 2 /* Command group position. */ -#define TC2_CMD0_bm (1<<2) /* Command bit 0 mask. */ -#define TC2_CMD0_bp 2 /* Command bit 0 position. */ -#define TC2_CMD1_bm (1<<3) /* Command bit 1 mask. */ -#define TC2_CMD1_bp 3 /* Command bit 1 position. */ - -#define TC2_CMDEN_gm 0x03 /* Command Enable group mask. */ -#define TC2_CMDEN_gp 0 /* Command Enable group position. */ -#define TC2_CMDEN0_bm (1<<0) /* Command Enable bit 0 mask. */ -#define TC2_CMDEN0_bp 0 /* Command Enable bit 0 position. */ -#define TC2_CMDEN1_bm (1<<1) /* Command Enable bit 1 mask. */ -#define TC2_CMDEN1_bp 1 /* Command Enable bit 1 position. */ - -/* TC2.INTFLAGS bit masks and bit positions */ -#define TC2_LCMPDIF_bm 0x80 /* Low Byte Compare D Interrupt Flag bit mask. */ -#define TC2_LCMPDIF_bp 7 /* Low Byte Compare D Interrupt Flag bit position. */ - -#define TC2_LCMPCIF_bm 0x40 /* Low Byte Compare C Interrupt Flag bit mask. */ -#define TC2_LCMPCIF_bp 6 /* Low Byte Compare C Interrupt Flag bit position. */ - -#define TC2_LCMPBIF_bm 0x20 /* Low Byte Compare B Interrupt Flag bit mask. */ -#define TC2_LCMPBIF_bp 5 /* Low Byte Compare B Interrupt Flag bit position. */ - -#define TC2_LCMPAIF_bm 0x10 /* Low Byte Compare A Interrupt Flag bit mask. */ -#define TC2_LCMPAIF_bp 4 /* Low Byte Compare A Interrupt Flag bit position. */ - -#define TC2_HUNFIF_bm 0x02 /* High Byte Underflow Interrupt Flag bit mask. */ -#define TC2_HUNFIF_bp 1 /* High Byte Underflow Interrupt Flag bit position. */ - -#define TC2_LUNFIF_bm 0x01 /* Low Byte Underflow Interrupt Flag bit mask. */ -#define TC2_LUNFIF_bp 0 /* Low Byte Underflow Interrupt Flag bit position. */ - -/* AWEX - Timer/Counter Advanced Waveform Extension */ -/* AWEX.CTRL bit masks and bit positions */ -#define AWEX_PGM_bm 0x20 /* Pattern Generation Mode bit mask. */ -#define AWEX_PGM_bp 5 /* Pattern Generation Mode bit position. */ - -#define AWEX_CWCM_bm 0x10 /* Common Waveform Channel Mode bit mask. */ -#define AWEX_CWCM_bp 4 /* Common Waveform Channel Mode bit position. */ - -#define AWEX_DTICCDEN_bm 0x08 /* Dead Time Insertion Compare Channel D Enable bit mask. */ -#define AWEX_DTICCDEN_bp 3 /* Dead Time Insertion Compare Channel D Enable bit position. */ - -#define AWEX_DTICCCEN_bm 0x04 /* Dead Time Insertion Compare Channel C Enable bit mask. */ -#define AWEX_DTICCCEN_bp 2 /* Dead Time Insertion Compare Channel C Enable bit position. */ - -#define AWEX_DTICCBEN_bm 0x02 /* Dead Time Insertion Compare Channel B Enable bit mask. */ -#define AWEX_DTICCBEN_bp 1 /* Dead Time Insertion Compare Channel B Enable bit position. */ - -#define AWEX_DTICCAEN_bm 0x01 /* Dead Time Insertion Compare Channel A Enable bit mask. */ -#define AWEX_DTICCAEN_bp 0 /* Dead Time Insertion Compare Channel A Enable bit position. */ - -/* AWEX.FDCTRL bit masks and bit positions */ -#define AWEX_FDDBD_bm 0x10 /* Fault Detect on Disable Break Disable bit mask. */ -#define AWEX_FDDBD_bp 4 /* Fault Detect on Disable Break Disable bit position. */ - -#define AWEX_FDMODE_bm 0x04 /* Fault Detect Mode bit mask. */ -#define AWEX_FDMODE_bp 2 /* Fault Detect Mode bit position. */ - -#define AWEX_FDACT_gm 0x03 /* Fault Detect Action group mask. */ -#define AWEX_FDACT_gp 0 /* Fault Detect Action group position. */ -#define AWEX_FDACT0_bm (1<<0) /* Fault Detect Action bit 0 mask. */ -#define AWEX_FDACT0_bp 0 /* Fault Detect Action bit 0 position. */ -#define AWEX_FDACT1_bm (1<<1) /* Fault Detect Action bit 1 mask. */ -#define AWEX_FDACT1_bp 1 /* Fault Detect Action bit 1 position. */ - -/* AWEX.STATUS bit masks and bit positions */ -#define AWEX_FDF_bm 0x04 /* Fault Detect Flag bit mask. */ -#define AWEX_FDF_bp 2 /* Fault Detect Flag bit position. */ - -#define AWEX_DTHSBUFV_bm 0x02 /* Dead Time High Side Buffer Valid bit mask. */ -#define AWEX_DTHSBUFV_bp 1 /* Dead Time High Side Buffer Valid bit position. */ - -#define AWEX_DTLSBUFV_bm 0x01 /* Dead Time Low Side Buffer Valid bit mask. */ -#define AWEX_DTLSBUFV_bp 0 /* Dead Time Low Side Buffer Valid bit position. */ - -/* AWEX.STATUSSET bit masks and bit positions */ -/* AWEX_FDF Predefined. */ -/* AWEX_FDF Predefined. */ - -/* AWEX_DTHSBUFV Predefined. */ -/* AWEX_DTHSBUFV Predefined. */ - -/* AWEX_DTLSBUFV Predefined. */ -/* AWEX_DTLSBUFV Predefined. */ - -/* HIRES - Timer/Counter High-Resolution Extension */ -/* HIRES.CTRLA bit masks and bit positions */ -#define HIRES_HREN_gm 0x03 /* High Resolution Enable group mask. */ -#define HIRES_HREN_gp 0 /* High Resolution Enable group position. */ -#define HIRES_HREN0_bm (1<<0) /* High Resolution Enable bit 0 mask. */ -#define HIRES_HREN0_bp 0 /* High Resolution Enable bit 0 position. */ -#define HIRES_HREN1_bm (1<<1) /* High Resolution Enable bit 1 mask. */ -#define HIRES_HREN1_bp 1 /* High Resolution Enable bit 1 position. */ - -/* USART - Universal Asynchronous Receiver-Transmitter */ -/* USART.STATUS bit masks and bit positions */ -#define USART_RXCIF_bm 0x80 /* Receive Interrupt Flag bit mask. */ -#define USART_RXCIF_bp 7 /* Receive Interrupt Flag bit position. */ - -#define USART_TXCIF_bm 0x40 /* Transmit Interrupt Flag bit mask. */ -#define USART_TXCIF_bp 6 /* Transmit Interrupt Flag bit position. */ - -#define USART_DREIF_bm 0x20 /* Data Register Empty Flag bit mask. */ -#define USART_DREIF_bp 5 /* Data Register Empty Flag bit position. */ - -#define USART_FERR_bm 0x10 /* Frame Error bit mask. */ -#define USART_FERR_bp 4 /* Frame Error bit position. */ - -#define USART_BUFOVF_bm 0x08 /* Buffer Overflow bit mask. */ -#define USART_BUFOVF_bp 3 /* Buffer Overflow bit position. */ - -#define USART_PERR_bm 0x04 /* Parity Error bit mask. */ -#define USART_PERR_bp 2 /* Parity Error bit position. */ - -#define USART_RXB8_bm 0x01 /* Receive Bit 8 bit mask. */ -#define USART_RXB8_bp 0 /* Receive Bit 8 bit position. */ - -/* USART.CTRLA bit masks and bit positions */ -#define USART_RXCINTLVL_gm 0x30 /* Receive Interrupt Level group mask. */ -#define USART_RXCINTLVL_gp 4 /* Receive Interrupt Level group position. */ -#define USART_RXCINTLVL0_bm (1<<4) /* Receive Interrupt Level bit 0 mask. */ -#define USART_RXCINTLVL0_bp 4 /* Receive Interrupt Level bit 0 position. */ -#define USART_RXCINTLVL1_bm (1<<5) /* Receive Interrupt Level bit 1 mask. */ -#define USART_RXCINTLVL1_bp 5 /* Receive Interrupt Level bit 1 position. */ - -#define USART_TXCINTLVL_gm 0x0C /* Transmit Interrupt Level group mask. */ -#define USART_TXCINTLVL_gp 2 /* Transmit Interrupt Level group position. */ -#define USART_TXCINTLVL0_bm (1<<2) /* Transmit Interrupt Level bit 0 mask. */ -#define USART_TXCINTLVL0_bp 2 /* Transmit Interrupt Level bit 0 position. */ -#define USART_TXCINTLVL1_bm (1<<3) /* Transmit Interrupt Level bit 1 mask. */ -#define USART_TXCINTLVL1_bp 3 /* Transmit Interrupt Level bit 1 position. */ - -#define USART_DREINTLVL_gm 0x03 /* Data Register Empty Interrupt Level group mask. */ -#define USART_DREINTLVL_gp 0 /* Data Register Empty Interrupt Level group position. */ -#define USART_DREINTLVL0_bm (1<<0) /* Data Register Empty Interrupt Level bit 0 mask. */ -#define USART_DREINTLVL0_bp 0 /* Data Register Empty Interrupt Level bit 0 position. */ -#define USART_DREINTLVL1_bm (1<<1) /* Data Register Empty Interrupt Level bit 1 mask. */ -#define USART_DREINTLVL1_bp 1 /* Data Register Empty Interrupt Level bit 1 position. */ - -/* USART.CTRLB bit masks and bit positions */ -#define USART_RXEN_bm 0x10 /* Receiver Enable bit mask. */ -#define USART_RXEN_bp 4 /* Receiver Enable bit position. */ - -#define USART_TXEN_bm 0x08 /* Transmitter Enable bit mask. */ -#define USART_TXEN_bp 3 /* Transmitter Enable bit position. */ - -#define USART_CLK2X_bm 0x04 /* Double transmission speed bit mask. */ -#define USART_CLK2X_bp 2 /* Double transmission speed bit position. */ - -#define USART_MPCM_bm 0x02 /* Multi-processor Communication Mode bit mask. */ -#define USART_MPCM_bp 1 /* Multi-processor Communication Mode bit position. */ - -#define USART_TXB8_bm 0x01 /* Transmit bit 8 bit mask. */ -#define USART_TXB8_bp 0 /* Transmit bit 8 bit position. */ - -/* USART.CTRLC bit masks and bit positions */ -#define USART_CMODE_gm 0xC0 /* Communication Mode group mask. */ -#define USART_CMODE_gp 6 /* Communication Mode group position. */ -#define USART_CMODE0_bm (1<<6) /* Communication Mode bit 0 mask. */ -#define USART_CMODE0_bp 6 /* Communication Mode bit 0 position. */ -#define USART_CMODE1_bm (1<<7) /* Communication Mode bit 1 mask. */ -#define USART_CMODE1_bp 7 /* Communication Mode bit 1 position. */ - -#define USART_PMODE_gm 0x30 /* Parity Mode group mask. */ -#define USART_PMODE_gp 4 /* Parity Mode group position. */ -#define USART_PMODE0_bm (1<<4) /* Parity Mode bit 0 mask. */ -#define USART_PMODE0_bp 4 /* Parity Mode bit 0 position. */ -#define USART_PMODE1_bm (1<<5) /* Parity Mode bit 1 mask. */ -#define USART_PMODE1_bp 5 /* Parity Mode bit 1 position. */ - -#define USART_SBMODE_bm 0x08 /* Stop Bit Mode bit mask. */ -#define USART_SBMODE_bp 3 /* Stop Bit Mode bit position. */ - -#define USART_CHSIZE_gm 0x07 /* Character Size group mask. */ -#define USART_CHSIZE_gp 0 /* Character Size group position. */ -#define USART_CHSIZE0_bm (1<<0) /* Character Size bit 0 mask. */ -#define USART_CHSIZE0_bp 0 /* Character Size bit 0 position. */ -#define USART_CHSIZE1_bm (1<<1) /* Character Size bit 1 mask. */ -#define USART_CHSIZE1_bp 1 /* Character Size bit 1 position. */ -#define USART_CHSIZE2_bm (1<<2) /* Character Size bit 2 mask. */ -#define USART_CHSIZE2_bp 2 /* Character Size bit 2 position. */ - -/* USART.BAUDCTRLA bit masks and bit positions */ -#define USART_BSEL_gm 0xFF /* Baud Rate Selection Bits [7:0] group mask. */ -#define USART_BSEL_gp 0 /* Baud Rate Selection Bits [7:0] group position. */ -#define USART_BSEL0_bm (1<<0) /* Baud Rate Selection Bits [7:0] bit 0 mask. */ -#define USART_BSEL0_bp 0 /* Baud Rate Selection Bits [7:0] bit 0 position. */ -#define USART_BSEL1_bm (1<<1) /* Baud Rate Selection Bits [7:0] bit 1 mask. */ -#define USART_BSEL1_bp 1 /* Baud Rate Selection Bits [7:0] bit 1 position. */ -#define USART_BSEL2_bm (1<<2) /* Baud Rate Selection Bits [7:0] bit 2 mask. */ -#define USART_BSEL2_bp 2 /* Baud Rate Selection Bits [7:0] bit 2 position. */ -#define USART_BSEL3_bm (1<<3) /* Baud Rate Selection Bits [7:0] bit 3 mask. */ -#define USART_BSEL3_bp 3 /* Baud Rate Selection Bits [7:0] bit 3 position. */ -#define USART_BSEL4_bm (1<<4) /* Baud Rate Selection Bits [7:0] bit 4 mask. */ -#define USART_BSEL4_bp 4 /* Baud Rate Selection Bits [7:0] bit 4 position. */ -#define USART_BSEL5_bm (1<<5) /* Baud Rate Selection Bits [7:0] bit 5 mask. */ -#define USART_BSEL5_bp 5 /* Baud Rate Selection Bits [7:0] bit 5 position. */ -#define USART_BSEL6_bm (1<<6) /* Baud Rate Selection Bits [7:0] bit 6 mask. */ -#define USART_BSEL6_bp 6 /* Baud Rate Selection Bits [7:0] bit 6 position. */ -#define USART_BSEL7_bm (1<<7) /* Baud Rate Selection Bits [7:0] bit 7 mask. */ -#define USART_BSEL7_bp 7 /* Baud Rate Selection Bits [7:0] bit 7 position. */ - -/* USART.BAUDCTRLB bit masks and bit positions */ -#define USART_BSCALE_gm 0xF0 /* Baud Rate Scale group mask. */ -#define USART_BSCALE_gp 4 /* Baud Rate Scale group position. */ -#define USART_BSCALE0_bm (1<<4) /* Baud Rate Scale bit 0 mask. */ -#define USART_BSCALE0_bp 4 /* Baud Rate Scale bit 0 position. */ -#define USART_BSCALE1_bm (1<<5) /* Baud Rate Scale bit 1 mask. */ -#define USART_BSCALE1_bp 5 /* Baud Rate Scale bit 1 position. */ -#define USART_BSCALE2_bm (1<<6) /* Baud Rate Scale bit 2 mask. */ -#define USART_BSCALE2_bp 6 /* Baud Rate Scale bit 2 position. */ -#define USART_BSCALE3_bm (1<<7) /* Baud Rate Scale bit 3 mask. */ -#define USART_BSCALE3_bp 7 /* Baud Rate Scale bit 3 position. */ - -/* USART_BSEL Predefined. */ -/* USART_BSEL Predefined. */ - -/* SPI - Serial Peripheral Interface */ -/* SPI.CTRL bit masks and bit positions */ -#define SPI_CLK2X_bm 0x80 /* Enable Double Speed bit mask. */ -#define SPI_CLK2X_bp 7 /* Enable Double Speed bit position. */ - -#define SPI_ENABLE_bm 0x40 /* Enable Module bit mask. */ -#define SPI_ENABLE_bp 6 /* Enable Module bit position. */ - -#define SPI_DORD_bm 0x20 /* Data Order Setting bit mask. */ -#define SPI_DORD_bp 5 /* Data Order Setting bit position. */ - -#define SPI_MASTER_bm 0x10 /* Master Operation Enable bit mask. */ -#define SPI_MASTER_bp 4 /* Master Operation Enable bit position. */ - -#define SPI_MODE_gm 0x0C /* SPI Mode group mask. */ -#define SPI_MODE_gp 2 /* SPI Mode group position. */ -#define SPI_MODE0_bm (1<<2) /* SPI Mode bit 0 mask. */ -#define SPI_MODE0_bp 2 /* SPI Mode bit 0 position. */ -#define SPI_MODE1_bm (1<<3) /* SPI Mode bit 1 mask. */ -#define SPI_MODE1_bp 3 /* SPI Mode bit 1 position. */ - -#define SPI_PRESCALER_gm 0x03 /* Prescaler group mask. */ -#define SPI_PRESCALER_gp 0 /* Prescaler group position. */ -#define SPI_PRESCALER0_bm (1<<0) /* Prescaler bit 0 mask. */ -#define SPI_PRESCALER0_bp 0 /* Prescaler bit 0 position. */ -#define SPI_PRESCALER1_bm (1<<1) /* Prescaler bit 1 mask. */ -#define SPI_PRESCALER1_bp 1 /* Prescaler bit 1 position. */ - -/* SPI.INTCTRL bit masks and bit positions */ -#define SPI_INTLVL_gm 0x03 /* Interrupt level group mask. */ -#define SPI_INTLVL_gp 0 /* Interrupt level group position. */ -#define SPI_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */ -#define SPI_INTLVL0_bp 0 /* Interrupt level bit 0 position. */ -#define SPI_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */ -#define SPI_INTLVL1_bp 1 /* Interrupt level bit 1 position. */ - -/* SPI.STATUS bit masks and bit positions */ -#define SPI_IF_bm 0x80 /* Interrupt Flag bit mask. */ -#define SPI_IF_bp 7 /* Interrupt Flag bit position. */ - -#define SPI_WRCOL_bm 0x40 /* Write Collision bit mask. */ -#define SPI_WRCOL_bp 6 /* Write Collision bit position. */ - -/* IRCOM - IR Communication Module */ -/* IRCOM.CTRL bit masks and bit positions */ -#define IRCOM_EVSEL_gm 0x0F /* Event Channel Select group mask. */ -#define IRCOM_EVSEL_gp 0 /* Event Channel Select group position. */ -#define IRCOM_EVSEL0_bm (1<<0) /* Event Channel Select bit 0 mask. */ -#define IRCOM_EVSEL0_bp 0 /* Event Channel Select bit 0 position. */ -#define IRCOM_EVSEL1_bm (1<<1) /* Event Channel Select bit 1 mask. */ -#define IRCOM_EVSEL1_bp 1 /* Event Channel Select bit 1 position. */ -#define IRCOM_EVSEL2_bm (1<<2) /* Event Channel Select bit 2 mask. */ -#define IRCOM_EVSEL2_bp 2 /* Event Channel Select bit 2 position. */ -#define IRCOM_EVSEL3_bm (1<<3) /* Event Channel Select bit 3 mask. */ -#define IRCOM_EVSEL3_bp 3 /* Event Channel Select bit 3 position. */ - -/* FUSE - Fuses and Lockbits */ -/* NVM_FUSES.FUSEBYTE0 bit masks and bit positions */ -#define NVM_FUSES_JTAGUSERID_gm 0xFF /* JTAG User ID group mask. */ -#define NVM_FUSES_JTAGUSERID_gp 0 /* JTAG User ID group position. */ -#define NVM_FUSES_JTAGUSERID0_bm (1<<0) /* JTAG User ID bit 0 mask. */ -#define NVM_FUSES_JTAGUSERID0_bp 0 /* JTAG User ID bit 0 position. */ -#define NVM_FUSES_JTAGUSERID1_bm (1<<1) /* JTAG User ID bit 1 mask. */ -#define NVM_FUSES_JTAGUSERID1_bp 1 /* JTAG User ID bit 1 position. */ -#define NVM_FUSES_JTAGUSERID2_bm (1<<2) /* JTAG User ID bit 2 mask. */ -#define NVM_FUSES_JTAGUSERID2_bp 2 /* JTAG User ID bit 2 position. */ -#define NVM_FUSES_JTAGUSERID3_bm (1<<3) /* JTAG User ID bit 3 mask. */ -#define NVM_FUSES_JTAGUSERID3_bp 3 /* JTAG User ID bit 3 position. */ -#define NVM_FUSES_JTAGUSERID4_bm (1<<4) /* JTAG User ID bit 4 mask. */ -#define NVM_FUSES_JTAGUSERID4_bp 4 /* JTAG User ID bit 4 position. */ -#define NVM_FUSES_JTAGUSERID5_bm (1<<5) /* JTAG User ID bit 5 mask. */ -#define NVM_FUSES_JTAGUSERID5_bp 5 /* JTAG User ID bit 5 position. */ -#define NVM_FUSES_JTAGUSERID6_bm (1<<6) /* JTAG User ID bit 6 mask. */ -#define NVM_FUSES_JTAGUSERID6_bp 6 /* JTAG User ID bit 6 position. */ -#define NVM_FUSES_JTAGUSERID7_bm (1<<7) /* JTAG User ID bit 7 mask. */ -#define NVM_FUSES_JTAGUSERID7_bp 7 /* JTAG User ID bit 7 position. */ - -/* NVM_FUSES.FUSEBYTE1 bit masks and bit positions */ -#define NVM_FUSES_WDWP_gm 0xF0 /* Watchdog Window Timeout Period group mask. */ -#define NVM_FUSES_WDWP_gp 4 /* Watchdog Window Timeout Period group position. */ -#define NVM_FUSES_WDWP0_bm (1<<4) /* Watchdog Window Timeout Period bit 0 mask. */ -#define NVM_FUSES_WDWP0_bp 4 /* Watchdog Window Timeout Period bit 0 position. */ -#define NVM_FUSES_WDWP1_bm (1<<5) /* Watchdog Window Timeout Period bit 1 mask. */ -#define NVM_FUSES_WDWP1_bp 5 /* Watchdog Window Timeout Period bit 1 position. */ -#define NVM_FUSES_WDWP2_bm (1<<6) /* Watchdog Window Timeout Period bit 2 mask. */ -#define NVM_FUSES_WDWP2_bp 6 /* Watchdog Window Timeout Period bit 2 position. */ -#define NVM_FUSES_WDWP3_bm (1<<7) /* Watchdog Window Timeout Period bit 3 mask. */ -#define NVM_FUSES_WDWP3_bp 7 /* Watchdog Window Timeout Period bit 3 position. */ - -#define NVM_FUSES_WDP_gm 0x0F /* Watchdog Timeout Period group mask. */ -#define NVM_FUSES_WDP_gp 0 /* Watchdog Timeout Period group position. */ -#define NVM_FUSES_WDP0_bm (1<<0) /* Watchdog Timeout Period bit 0 mask. */ -#define NVM_FUSES_WDP0_bp 0 /* Watchdog Timeout Period bit 0 position. */ -#define NVM_FUSES_WDP1_bm (1<<1) /* Watchdog Timeout Period bit 1 mask. */ -#define NVM_FUSES_WDP1_bp 1 /* Watchdog Timeout Period bit 1 position. */ -#define NVM_FUSES_WDP2_bm (1<<2) /* Watchdog Timeout Period bit 2 mask. */ -#define NVM_FUSES_WDP2_bp 2 /* Watchdog Timeout Period bit 2 position. */ -#define NVM_FUSES_WDP3_bm (1<<3) /* Watchdog Timeout Period bit 3 mask. */ -#define NVM_FUSES_WDP3_bp 3 /* Watchdog Timeout Period bit 3 position. */ - -/* NVM_FUSES.FUSEBYTE2 bit masks and bit positions */ -#define NVM_FUSES_BOOTRST_bm 0x40 /* Boot Loader Section Reset Vector bit mask. */ -#define NVM_FUSES_BOOTRST_bp 6 /* Boot Loader Section Reset Vector bit position. */ - -#define NVM_FUSES_TOSCSEL_bm 0x20 /* Timer Oscillator pin location bit mask. */ -#define NVM_FUSES_TOSCSEL_bp 5 /* Timer Oscillator pin location bit position. */ - -#define NVM_FUSES_BODPD_gm 0x03 /* BOD Operation in Power-Down Mode group mask. */ -#define NVM_FUSES_BODPD_gp 0 /* BOD Operation in Power-Down Mode group position. */ -#define NVM_FUSES_BODPD0_bm (1<<0) /* BOD Operation in Power-Down Mode bit 0 mask. */ -#define NVM_FUSES_BODPD0_bp 0 /* BOD Operation in Power-Down Mode bit 0 position. */ -#define NVM_FUSES_BODPD1_bm (1<<1) /* BOD Operation in Power-Down Mode bit 1 mask. */ -#define NVM_FUSES_BODPD1_bp 1 /* BOD Operation in Power-Down Mode bit 1 position. */ - -/* NVM_FUSES.FUSEBYTE4 bit masks and bit positions */ -#define NVM_FUSES_RSTDISBL_bm 0x10 /* External Reset Disable bit mask. */ -#define NVM_FUSES_RSTDISBL_bp 4 /* External Reset Disable bit position. */ - -#define NVM_FUSES_SUT_gm 0x0C /* Start-up Time group mask. */ -#define NVM_FUSES_SUT_gp 2 /* Start-up Time group position. */ -#define NVM_FUSES_SUT0_bm (1<<2) /* Start-up Time bit 0 mask. */ -#define NVM_FUSES_SUT0_bp 2 /* Start-up Time bit 0 position. */ -#define NVM_FUSES_SUT1_bm (1<<3) /* Start-up Time bit 1 mask. */ -#define NVM_FUSES_SUT1_bp 3 /* Start-up Time bit 1 position. */ - -#define NVM_FUSES_WDLOCK_bm 0x02 /* Watchdog Timer Lock bit mask. */ -#define NVM_FUSES_WDLOCK_bp 1 /* Watchdog Timer Lock bit position. */ - -#define NVM_FUSES_JTAGEN_bm 0x01 /* JTAG Interface Enable bit mask. */ -#define NVM_FUSES_JTAGEN_bp 0 /* JTAG Interface Enable bit position. */ - -/* NVM_FUSES.FUSEBYTE5 bit masks and bit positions */ -#define NVM_FUSES_BODACT_gm 0x30 /* BOD Operation in Active Mode group mask. */ -#define NVM_FUSES_BODACT_gp 4 /* BOD Operation in Active Mode group position. */ -#define NVM_FUSES_BODACT0_bm (1<<4) /* BOD Operation in Active Mode bit 0 mask. */ -#define NVM_FUSES_BODACT0_bp 4 /* BOD Operation in Active Mode bit 0 position. */ -#define NVM_FUSES_BODACT1_bm (1<<5) /* BOD Operation in Active Mode bit 1 mask. */ -#define NVM_FUSES_BODACT1_bp 5 /* BOD Operation in Active Mode bit 1 position. */ - -#define NVM_FUSES_EESAVE_bm 0x08 /* Preserve EEPROM Through Chip Erase bit mask. */ -#define NVM_FUSES_EESAVE_bp 3 /* Preserve EEPROM Through Chip Erase bit position. */ - -#define NVM_FUSES_BODLVL_gm 0x07 /* Brownout Detection Voltage Level group mask. */ -#define NVM_FUSES_BODLVL_gp 0 /* Brownout Detection Voltage Level group position. */ -#define NVM_FUSES_BODLVL0_bm (1<<0) /* Brownout Detection Voltage Level bit 0 mask. */ -#define NVM_FUSES_BODLVL0_bp 0 /* Brownout Detection Voltage Level bit 0 position. */ -#define NVM_FUSES_BODLVL1_bm (1<<1) /* Brownout Detection Voltage Level bit 1 mask. */ -#define NVM_FUSES_BODLVL1_bp 1 /* Brownout Detection Voltage Level bit 1 position. */ -#define NVM_FUSES_BODLVL2_bm (1<<2) /* Brownout Detection Voltage Level bit 2 mask. */ -#define NVM_FUSES_BODLVL2_bp 2 /* Brownout Detection Voltage Level bit 2 position. */ - -/* LOCKBIT - Fuses and Lockbits */ -/* NVM_LOCKBITS.LOCKBITS bit masks and bit positions */ -#define NVM_LOCKBITS_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ -#define NVM_LOCKBITS_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ -#define NVM_LOCKBITS_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ -#define NVM_LOCKBITS_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ -#define NVM_LOCKBITS_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ -#define NVM_LOCKBITS_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ - -#define NVM_LOCKBITS_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ -#define NVM_LOCKBITS_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ -#define NVM_LOCKBITS_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ -#define NVM_LOCKBITS_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ -#define NVM_LOCKBITS_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ -#define NVM_LOCKBITS_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ - -#define NVM_LOCKBITS_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ -#define NVM_LOCKBITS_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ -#define NVM_LOCKBITS_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ -#define NVM_LOCKBITS_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ -#define NVM_LOCKBITS_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ -#define NVM_LOCKBITS_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ - -#define NVM_LOCKBITS_LB_gm 0x03 /* Lock Bits group mask. */ -#define NVM_LOCKBITS_LB_gp 0 /* Lock Bits group position. */ -#define NVM_LOCKBITS_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ -#define NVM_LOCKBITS_LB0_bp 0 /* Lock Bits bit 0 position. */ -#define NVM_LOCKBITS_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ -#define NVM_LOCKBITS_LB1_bp 1 /* Lock Bits bit 1 position. */ - - - -// Generic Port Pins - -#define PIN0_bm 0x01 -#define PIN0_bp 0 -#define PIN1_bm 0x02 -#define PIN1_bp 1 -#define PIN2_bm 0x04 -#define PIN2_bp 2 -#define PIN3_bm 0x08 -#define PIN3_bp 3 -#define PIN4_bm 0x10 -#define PIN4_bp 4 -#define PIN5_bm 0x20 -#define PIN5_bp 5 -#define PIN6_bm 0x40 -#define PIN6_bp 6 -#define PIN7_bm 0x80 -#define PIN7_bp 7 - -/* ========== Interrupt Vector Definitions ========== */ -/* Vector 0 is the reset vector */ - -/* OSC interrupt vectors */ -#define OSC_OSCF_vect_num 1 -#define OSC_OSCF_vect _VECTOR(1) /* Oscillator Failure Interrupt (NMI) */ - -/* PORTC interrupt vectors */ -#define PORTC_INT0_vect_num 2 -#define PORTC_INT0_vect _VECTOR(2) /* External Interrupt 0 */ -#define PORTC_INT1_vect_num 3 -#define PORTC_INT1_vect _VECTOR(3) /* External Interrupt 1 */ - -/* PORTR interrupt vectors */ -#define PORTR_INT0_vect_num 4 -#define PORTR_INT0_vect _VECTOR(4) /* External Interrupt 0 */ -#define PORTR_INT1_vect_num 5 -#define PORTR_INT1_vect _VECTOR(5) /* External Interrupt 1 */ - -/* DMA interrupt vectors */ -#define DMA_CH0_vect_num 6 -#define DMA_CH0_vect _VECTOR(6) /* Channel 0 Interrupt */ -#define DMA_CH1_vect_num 7 -#define DMA_CH1_vect _VECTOR(7) /* Channel 1 Interrupt */ -#define DMA_CH2_vect_num 8 -#define DMA_CH2_vect _VECTOR(8) /* Channel 2 Interrupt */ -#define DMA_CH3_vect_num 9 -#define DMA_CH3_vect _VECTOR(9) /* Channel 3 Interrupt */ - -/* RTC interrupt vectors */ -#define RTC_OVF_vect_num 10 -#define RTC_OVF_vect _VECTOR(10) /* Overflow Interrupt */ -#define RTC_COMP_vect_num 11 -#define RTC_COMP_vect _VECTOR(11) /* Compare Interrupt */ - -/* TWIC interrupt vectors */ -#define TWIC_TWIS_vect_num 12 -#define TWIC_TWIS_vect _VECTOR(12) /* TWI Slave Interrupt */ -#define TWIC_TWIM_vect_num 13 -#define TWIC_TWIM_vect _VECTOR(13) /* TWI Master Interrupt */ - -/* TCC0 interrupt vectors */ -#define TCC0_OVF_vect_num 14 -#define TCC0_OVF_vect _VECTOR(14) /* Overflow Interrupt */ - -/* TCC2 interrupt vectors */ -#define TCC2_LUNF_vect_num 14 -#define TCC2_LUNF_vect _VECTOR(14) /* Low Byte Underflow Interrupt */ - -/* TCC0 interrupt vectors */ -#define TCC0_ERR_vect_num 15 -#define TCC0_ERR_vect _VECTOR(15) /* Error Interrupt */ - -/* TCC2 interrupt vectors */ -#define TCC2_HUNF_vect_num 15 -#define TCC2_HUNF_vect _VECTOR(15) /* High Byte Underflow Interrupt */ - -/* TCC0 interrupt vectors */ -#define TCC0_CCA_vect_num 16 -#define TCC0_CCA_vect _VECTOR(16) /* Compare or Capture A Interrupt */ - -/* TCC2 interrupt vectors */ -#define TCC2_LCMPA_vect_num 16 -#define TCC2_LCMPA_vect _VECTOR(16) /* Low Byte Compare A Interrupt */ - -/* TCC0 interrupt vectors */ -#define TCC0_CCB_vect_num 17 -#define TCC0_CCB_vect _VECTOR(17) /* Compare or Capture B Interrupt */ - -/* TCC2 interrupt vectors */ -#define TCC2_LCMPB_vect_num 17 -#define TCC2_LCMPB_vect _VECTOR(17) /* Low Byte Compare B Interrupt */ - -/* TCC0 interrupt vectors */ -#define TCC0_CCC_vect_num 18 -#define TCC0_CCC_vect _VECTOR(18) /* Compare or Capture C Interrupt */ - -/* TCC2 interrupt vectors */ -#define TCC2_LCMPC_vect_num 18 -#define TCC2_LCMPC_vect _VECTOR(18) /* Low Byte Compare C Interrupt */ - -/* TCC0 interrupt vectors */ -#define TCC0_CCD_vect_num 19 -#define TCC0_CCD_vect _VECTOR(19) /* Compare or Capture D Interrupt */ - -/* TCC2 interrupt vectors */ -#define TCC2_LCMPD_vect_num 19 -#define TCC2_LCMPD_vect _VECTOR(19) /* Low Byte Compare D Interrupt */ - -/* TCC1 interrupt vectors */ -#define TCC1_OVF_vect_num 20 -#define TCC1_OVF_vect _VECTOR(20) /* Overflow Interrupt */ -#define TCC1_ERR_vect_num 21 -#define TCC1_ERR_vect _VECTOR(21) /* Error Interrupt */ -#define TCC1_CCA_vect_num 22 -#define TCC1_CCA_vect _VECTOR(22) /* Compare or Capture A Interrupt */ -#define TCC1_CCB_vect_num 23 -#define TCC1_CCB_vect _VECTOR(23) /* Compare or Capture B Interrupt */ - -/* SPIC interrupt vectors */ -#define SPIC_INT_vect_num 24 -#define SPIC_INT_vect _VECTOR(24) /* SPI Interrupt */ - -/* USARTC0 interrupt vectors */ -#define USARTC0_RXC_vect_num 25 -#define USARTC0_RXC_vect _VECTOR(25) /* Reception Complete Interrupt */ -#define USARTC0_DRE_vect_num 26 -#define USARTC0_DRE_vect _VECTOR(26) /* Data Register Empty Interrupt */ -#define USARTC0_TXC_vect_num 27 -#define USARTC0_TXC_vect _VECTOR(27) /* Transmission Complete Interrupt */ - -/* USARTC1 interrupt vectors */ -#define USARTC1_RXC_vect_num 28 -#define USARTC1_RXC_vect _VECTOR(28) /* Reception Complete Interrupt */ -#define USARTC1_DRE_vect_num 29 -#define USARTC1_DRE_vect _VECTOR(29) /* Data Register Empty Interrupt */ -#define USARTC1_TXC_vect_num 30 -#define USARTC1_TXC_vect _VECTOR(30) /* Transmission Complete Interrupt */ - -/* AES interrupt vectors */ -#define AES_INT_vect_num 31 -#define AES_INT_vect _VECTOR(31) /* AES Interrupt */ - -/* NVM interrupt vectors */ -#define NVM_EE_vect_num 32 -#define NVM_EE_vect _VECTOR(32) /* EE Interrupt */ -#define NVM_SPM_vect_num 33 -#define NVM_SPM_vect _VECTOR(33) /* SPM Interrupt */ - -/* PORTB interrupt vectors */ -#define PORTB_INT0_vect_num 34 -#define PORTB_INT0_vect _VECTOR(34) /* External Interrupt 0 */ -#define PORTB_INT1_vect_num 35 -#define PORTB_INT1_vect _VECTOR(35) /* External Interrupt 1 */ - -/* ACB interrupt vectors */ -#define ACB_AC0_vect_num 36 -#define ACB_AC0_vect _VECTOR(36) /* AC0 Interrupt */ -#define ACB_AC1_vect_num 37 -#define ACB_AC1_vect _VECTOR(37) /* AC1 Interrupt */ -#define ACB_ACW_vect_num 38 -#define ACB_ACW_vect _VECTOR(38) /* ACW Window Mode Interrupt */ - -/* ADCB interrupt vectors */ -#define ADCB_CH0_vect_num 39 -#define ADCB_CH0_vect _VECTOR(39) /* Interrupt 0 */ -#define ADCB_CH1_vect_num 40 -#define ADCB_CH1_vect _VECTOR(40) /* Interrupt 1 */ -#define ADCB_CH2_vect_num 41 -#define ADCB_CH2_vect _VECTOR(41) /* Interrupt 2 */ -#define ADCB_CH3_vect_num 42 -#define ADCB_CH3_vect _VECTOR(42) /* Interrupt 3 */ - -/* PORTE interrupt vectors */ -#define PORTE_INT0_vect_num 43 -#define PORTE_INT0_vect _VECTOR(43) /* External Interrupt 0 */ -#define PORTE_INT1_vect_num 44 -#define PORTE_INT1_vect _VECTOR(44) /* External Interrupt 1 */ - -/* TWIE interrupt vectors */ -#define TWIE_TWIS_vect_num 45 -#define TWIE_TWIS_vect _VECTOR(45) /* TWI Slave Interrupt */ -#define TWIE_TWIM_vect_num 46 -#define TWIE_TWIM_vect _VECTOR(46) /* TWI Master Interrupt */ - -/* TCE0 interrupt vectors */ -#define TCE0_OVF_vect_num 47 -#define TCE0_OVF_vect _VECTOR(47) /* Overflow Interrupt */ - -/* TCE2 interrupt vectors */ -#define TCE2_LUNF_vect_num 47 -#define TCE2_LUNF_vect _VECTOR(47) /* Low Byte Underflow Interrupt */ - -/* TCE0 interrupt vectors */ -#define TCE0_ERR_vect_num 48 -#define TCE0_ERR_vect _VECTOR(48) /* Error Interrupt */ - -/* TCE2 interrupt vectors */ -#define TCE2_HUNF_vect_num 48 -#define TCE2_HUNF_vect _VECTOR(48) /* High Byte Underflow Interrupt */ - -/* TCE0 interrupt vectors */ -#define TCE0_CCA_vect_num 49 -#define TCE0_CCA_vect _VECTOR(49) /* Compare or Capture A Interrupt */ - -/* TCE2 interrupt vectors */ -#define TCE2_LCMPA_vect_num 49 -#define TCE2_LCMPA_vect _VECTOR(49) /* Low Byte Compare A Interrupt */ - -/* TCE0 interrupt vectors */ -#define TCE0_CCB_vect_num 50 -#define TCE0_CCB_vect _VECTOR(50) /* Compare or Capture B Interrupt */ - -/* TCE2 interrupt vectors */ -#define TCE2_LCMPB_vect_num 50 -#define TCE2_LCMPB_vect _VECTOR(50) /* Low Byte Compare B Interrupt */ - -/* TCE0 interrupt vectors */ -#define TCE0_CCC_vect_num 51 -#define TCE0_CCC_vect _VECTOR(51) /* Compare or Capture C Interrupt */ - -/* TCE2 interrupt vectors */ -#define TCE2_LCMPC_vect_num 51 -#define TCE2_LCMPC_vect _VECTOR(51) /* Low Byte Compare C Interrupt */ - -/* TCE0 interrupt vectors */ -#define TCE0_CCD_vect_num 52 -#define TCE0_CCD_vect _VECTOR(52) /* Compare or Capture D Interrupt */ - -/* TCE2 interrupt vectors */ -#define TCE2_LCMPD_vect_num 52 -#define TCE2_LCMPD_vect _VECTOR(52) /* Low Byte Compare D Interrupt */ - -/* TCE1 interrupt vectors */ -#define TCE1_OVF_vect_num 53 -#define TCE1_OVF_vect _VECTOR(53) /* Overflow Interrupt */ -#define TCE1_ERR_vect_num 54 -#define TCE1_ERR_vect _VECTOR(54) /* Error Interrupt */ -#define TCE1_CCA_vect_num 55 -#define TCE1_CCA_vect _VECTOR(55) /* Compare or Capture A Interrupt */ -#define TCE1_CCB_vect_num 56 -#define TCE1_CCB_vect _VECTOR(56) /* Compare or Capture B Interrupt */ - -/* SPIE interrupt vectors */ -#define SPIE_INT_vect_num 57 -#define SPIE_INT_vect _VECTOR(57) /* SPI Interrupt */ - -/* USARTE0 interrupt vectors */ -#define USARTE0_RXC_vect_num 58 -#define USARTE0_RXC_vect _VECTOR(58) /* Reception Complete Interrupt */ -#define USARTE0_DRE_vect_num 59 -#define USARTE0_DRE_vect _VECTOR(59) /* Data Register Empty Interrupt */ -#define USARTE0_TXC_vect_num 60 -#define USARTE0_TXC_vect _VECTOR(60) /* Transmission Complete Interrupt */ - -/* USARTE1 interrupt vectors */ -#define USARTE1_RXC_vect_num 61 -#define USARTE1_RXC_vect _VECTOR(61) /* Reception Complete Interrupt */ -#define USARTE1_DRE_vect_num 62 -#define USARTE1_DRE_vect _VECTOR(62) /* Data Register Empty Interrupt */ -#define USARTE1_TXC_vect_num 63 -#define USARTE1_TXC_vect _VECTOR(63) /* Transmission Complete Interrupt */ - -/* PORTD interrupt vectors */ -#define PORTD_INT0_vect_num 64 -#define PORTD_INT0_vect _VECTOR(64) /* External Interrupt 0 */ -#define PORTD_INT1_vect_num 65 -#define PORTD_INT1_vect _VECTOR(65) /* External Interrupt 1 */ - -/* PORTA interrupt vectors */ -#define PORTA_INT0_vect_num 66 -#define PORTA_INT0_vect _VECTOR(66) /* External Interrupt 0 */ -#define PORTA_INT1_vect_num 67 -#define PORTA_INT1_vect _VECTOR(67) /* External Interrupt 1 */ - -/* ACA interrupt vectors */ -#define ACA_AC0_vect_num 68 -#define ACA_AC0_vect _VECTOR(68) /* AC0 Interrupt */ -#define ACA_AC1_vect_num 69 -#define ACA_AC1_vect _VECTOR(69) /* AC1 Interrupt */ -#define ACA_ACW_vect_num 70 -#define ACA_ACW_vect _VECTOR(70) /* ACW Window Mode Interrupt */ - -/* ADCA interrupt vectors */ -#define ADCA_CH0_vect_num 71 -#define ADCA_CH0_vect _VECTOR(71) /* Interrupt 0 */ -#define ADCA_CH1_vect_num 72 -#define ADCA_CH1_vect _VECTOR(72) /* Interrupt 1 */ -#define ADCA_CH2_vect_num 73 -#define ADCA_CH2_vect _VECTOR(73) /* Interrupt 2 */ -#define ADCA_CH3_vect_num 74 -#define ADCA_CH3_vect _VECTOR(74) /* Interrupt 3 */ - -/* TWID interrupt vectors */ -#define TWID_TWIS_vect_num 75 -#define TWID_TWIS_vect _VECTOR(75) /* TWI Slave Interrupt */ -#define TWID_TWIM_vect_num 76 -#define TWID_TWIM_vect _VECTOR(76) /* TWI Master Interrupt */ - -/* TCD0 interrupt vectors */ -#define TCD0_OVF_vect_num 77 -#define TCD0_OVF_vect _VECTOR(77) /* Overflow Interrupt */ - -/* TCD2 interrupt vectors */ -#define TCD2_LUNF_vect_num 77 -#define TCD2_LUNF_vect _VECTOR(77) /* Low Byte Underflow Interrupt */ - -/* TCD0 interrupt vectors */ -#define TCD0_ERR_vect_num 78 -#define TCD0_ERR_vect _VECTOR(78) /* Error Interrupt */ - -/* TCD2 interrupt vectors */ -#define TCD2_HUNF_vect_num 78 -#define TCD2_HUNF_vect _VECTOR(78) /* High Byte Underflow Interrupt */ - -/* TCD0 interrupt vectors */ -#define TCD0_CCA_vect_num 79 -#define TCD0_CCA_vect _VECTOR(79) /* Compare or Capture A Interrupt */ - -/* TCD2 interrupt vectors */ -#define TCD2_LCMPA_vect_num 79 -#define TCD2_LCMPA_vect _VECTOR(79) /* Low Byte Compare A Interrupt */ - -/* TCD0 interrupt vectors */ -#define TCD0_CCB_vect_num 80 -#define TCD0_CCB_vect _VECTOR(80) /* Compare or Capture B Interrupt */ - -/* TCD2 interrupt vectors */ -#define TCD2_LCMPB_vect_num 80 -#define TCD2_LCMPB_vect _VECTOR(80) /* Low Byte Compare B Interrupt */ - -/* TCD0 interrupt vectors */ -#define TCD0_CCC_vect_num 81 -#define TCD0_CCC_vect _VECTOR(81) /* Compare or Capture C Interrupt */ - -/* TCD2 interrupt vectors */ -#define TCD2_LCMPC_vect_num 81 -#define TCD2_LCMPC_vect _VECTOR(81) /* Low Byte Compare C Interrupt */ - -/* TCD0 interrupt vectors */ -#define TCD0_CCD_vect_num 82 -#define TCD0_CCD_vect _VECTOR(82) /* Compare or Capture D Interrupt */ - -/* TCD2 interrupt vectors */ -#define TCD2_LCMPD_vect_num 82 -#define TCD2_LCMPD_vect _VECTOR(82) /* Low Byte Compare D Interrupt */ - -/* TCD1 interrupt vectors */ -#define TCD1_OVF_vect_num 83 -#define TCD1_OVF_vect _VECTOR(83) /* Overflow Interrupt */ -#define TCD1_ERR_vect_num 84 -#define TCD1_ERR_vect _VECTOR(84) /* Error Interrupt */ -#define TCD1_CCA_vect_num 85 -#define TCD1_CCA_vect _VECTOR(85) /* Compare or Capture A Interrupt */ -#define TCD1_CCB_vect_num 86 -#define TCD1_CCB_vect _VECTOR(86) /* Compare or Capture B Interrupt */ - -/* SPID interrupt vectors */ -#define SPID_INT_vect_num 87 -#define SPID_INT_vect _VECTOR(87) /* SPI Interrupt */ - -/* USARTD0 interrupt vectors */ -#define USARTD0_RXC_vect_num 88 -#define USARTD0_RXC_vect _VECTOR(88) /* Reception Complete Interrupt */ -#define USARTD0_DRE_vect_num 89 -#define USARTD0_DRE_vect _VECTOR(89) /* Data Register Empty Interrupt */ -#define USARTD0_TXC_vect_num 90 -#define USARTD0_TXC_vect _VECTOR(90) /* Transmission Complete Interrupt */ - -/* USARTD1 interrupt vectors */ -#define USARTD1_RXC_vect_num 91 -#define USARTD1_RXC_vect _VECTOR(91) /* Reception Complete Interrupt */ -#define USARTD1_DRE_vect_num 92 -#define USARTD1_DRE_vect _VECTOR(92) /* Data Register Empty Interrupt */ -#define USARTD1_TXC_vect_num 93 -#define USARTD1_TXC_vect _VECTOR(93) /* Transmission Complete Interrupt */ - -/* PORTQ interrupt vectors */ -#define PORTQ_INT0_vect_num 94 -#define PORTQ_INT0_vect _VECTOR(94) /* External Interrupt 0 */ -#define PORTQ_INT1_vect_num 95 -#define PORTQ_INT1_vect _VECTOR(95) /* External Interrupt 1 */ - -/* PORTH interrupt vectors */ -#define PORTH_INT0_vect_num 96 -#define PORTH_INT0_vect _VECTOR(96) /* External Interrupt 0 */ -#define PORTH_INT1_vect_num 97 -#define PORTH_INT1_vect _VECTOR(97) /* External Interrupt 1 */ - -/* PORTJ interrupt vectors */ -#define PORTJ_INT0_vect_num 98 -#define PORTJ_INT0_vect _VECTOR(98) /* External Interrupt 0 */ -#define PORTJ_INT1_vect_num 99 -#define PORTJ_INT1_vect _VECTOR(99) /* External Interrupt 1 */ - -/* PORTK interrupt vectors */ -#define PORTK_INT0_vect_num 100 -#define PORTK_INT0_vect _VECTOR(100) /* External Interrupt 0 */ -#define PORTK_INT1_vect_num 101 -#define PORTK_INT1_vect _VECTOR(101) /* External Interrupt 1 */ - -/* PORTF interrupt vectors */ -#define PORTF_INT0_vect_num 104 -#define PORTF_INT0_vect _VECTOR(104) /* External Interrupt 0 */ -#define PORTF_INT1_vect_num 105 -#define PORTF_INT1_vect _VECTOR(105) /* External Interrupt 1 */ - -/* TWIF interrupt vectors */ -#define TWIF_TWIS_vect_num 106 -#define TWIF_TWIS_vect _VECTOR(106) /* TWI Slave Interrupt */ -#define TWIF_TWIM_vect_num 107 -#define TWIF_TWIM_vect _VECTOR(107) /* TWI Master Interrupt */ - -/* TCF0 interrupt vectors */ -#define TCF0_OVF_vect_num 108 -#define TCF0_OVF_vect _VECTOR(108) /* Overflow Interrupt */ - -/* TCF2 interrupt vectors */ -#define TCF2_LUNF_vect_num 108 -#define TCF2_LUNF_vect _VECTOR(108) /* Low Byte Underflow Interrupt */ - -/* TCF0 interrupt vectors */ -#define TCF0_ERR_vect_num 109 -#define TCF0_ERR_vect _VECTOR(109) /* Error Interrupt */ - -/* TCF2 interrupt vectors */ -#define TCF2_HUNF_vect_num 109 -#define TCF2_HUNF_vect _VECTOR(109) /* High Byte Underflow Interrupt */ - -/* TCF0 interrupt vectors */ -#define TCF0_CCA_vect_num 110 -#define TCF0_CCA_vect _VECTOR(110) /* Compare or Capture A Interrupt */ - -/* TCF2 interrupt vectors */ -#define TCF2_LCMPA_vect_num 110 -#define TCF2_LCMPA_vect _VECTOR(110) /* Low Byte Compare A Interrupt */ - -/* TCF0 interrupt vectors */ -#define TCF0_CCB_vect_num 111 -#define TCF0_CCB_vect _VECTOR(111) /* Compare or Capture B Interrupt */ - -/* TCF2 interrupt vectors */ -#define TCF2_LCMPB_vect_num 111 -#define TCF2_LCMPB_vect _VECTOR(111) /* Low Byte Compare B Interrupt */ - -/* TCF0 interrupt vectors */ -#define TCF0_CCC_vect_num 112 -#define TCF0_CCC_vect _VECTOR(112) /* Compare or Capture C Interrupt */ - -/* TCF2 interrupt vectors */ -#define TCF2_LCMPC_vect_num 112 -#define TCF2_LCMPC_vect _VECTOR(112) /* Low Byte Compare C Interrupt */ - -/* TCF0 interrupt vectors */ -#define TCF0_CCD_vect_num 113 -#define TCF0_CCD_vect _VECTOR(113) /* Compare or Capture D Interrupt */ - -/* TCF2 interrupt vectors */ -#define TCF2_LCMPD_vect_num 113 -#define TCF2_LCMPD_vect _VECTOR(113) /* Low Byte Compare D Interrupt */ - -/* TCF1 interrupt vectors */ -#define TCF1_OVF_vect_num 114 -#define TCF1_OVF_vect _VECTOR(114) /* Overflow Interrupt */ -#define TCF1_ERR_vect_num 115 -#define TCF1_ERR_vect _VECTOR(115) /* Error Interrupt */ -#define TCF1_CCA_vect_num 116 -#define TCF1_CCA_vect _VECTOR(116) /* Compare or Capture A Interrupt */ -#define TCF1_CCB_vect_num 117 -#define TCF1_CCB_vect _VECTOR(117) /* Compare or Capture B Interrupt */ - -/* SPIF interrupt vectors */ -#define SPIF_INT_vect_num 118 -#define SPIF_INT_vect _VECTOR(118) /* SPI Interrupt */ - -/* USARTF0 interrupt vectors */ -#define USARTF0_RXC_vect_num 119 -#define USARTF0_RXC_vect _VECTOR(119) /* Reception Complete Interrupt */ -#define USARTF0_DRE_vect_num 120 -#define USARTF0_DRE_vect _VECTOR(120) /* Data Register Empty Interrupt */ -#define USARTF0_TXC_vect_num 121 -#define USARTF0_TXC_vect _VECTOR(121) /* Transmission Complete Interrupt */ - -/* USARTF1 interrupt vectors */ -#define USARTF1_RXC_vect_num 122 -#define USARTF1_RXC_vect _VECTOR(122) /* Reception Complete Interrupt */ -#define USARTF1_DRE_vect_num 123 -#define USARTF1_DRE_vect _VECTOR(123) /* Data Register Empty Interrupt */ -#define USARTF1_TXC_vect_num 124 -#define USARTF1_TXC_vect _VECTOR(124) /* Transmission Complete Interrupt */ - -/* USB interrupt vectors */ -#define USB_BUSEVENT_vect_num 125 -#define USB_BUSEVENT_vect _VECTOR(125) /* SOF, suspend, resume, reset bus event interrupts, crc, underflow, overflow and stall error interrupts */ -#define USB_TRNCOMPL_vect_num 126 -#define USB_TRNCOMPL_vect _VECTOR(126) /* Transaction complete interrupt */ - -#define _VECTOR_SIZE 4 /* Size of individual vector. */ -#define _VECTORS_SIZE (127 * _VECTOR_SIZE) - - -/* ========== Constants ========== */ - -#define PROGMEM_START (0x0000) -#define PROGMEM_SIZE (139264) -#define PROGMEM_END (PROGMEM_START + PROGMEM_SIZE - 1) - -#define APP_SECTION_START (0x0000) -#define APP_SECTION_SIZE (131072) -#define APP_SECTION_PAGE_SIZE (512) -#define APP_SECTION_END (APP_SECTION_START + APP_SECTION_SIZE - 1) - -#define APPTABLE_SECTION_START (0x1E000) -#define APPTABLE_SECTION_SIZE (8192) -#define APPTABLE_SECTION_PAGE_SIZE (512) -#define APPTABLE_SECTION_END (APPTABLE_SECTION_START + APPTABLE_SECTION_SIZE - 1) - -#define BOOT_SECTION_START (0x20000) -#define BOOT_SECTION_SIZE (8192) -#define BOOT_SECTION_PAGE_SIZE (512) -#define BOOT_SECTION_END (BOOT_SECTION_START + BOOT_SECTION_SIZE - 1) - -#define DATAMEM_START (0x0000) -#define DATAMEM_SIZE (16777216) -#define DATAMEM_END (DATAMEM_START + DATAMEM_SIZE - 1) - -#define IO_START (0x0000) -#define IO_SIZE (4096) -#define IO_PAGE_SIZE (0) -#define IO_END (IO_START + IO_SIZE - 1) - -#define MAPPED_EEPROM_START (0x1000) -#define MAPPED_EEPROM_SIZE (2048) -#define MAPPED_EEPROM_PAGE_SIZE (0) -#define MAPPED_EEPROM_END (MAPPED_EEPROM_START + MAPPED_EEPROM_SIZE - 1) - -#define INTERNAL_SRAM_START (0x2000) -#define INTERNAL_SRAM_SIZE (8192) -#define INTERNAL_SRAM_PAGE_SIZE (0) -#define INTERNAL_SRAM_END (INTERNAL_SRAM_START + INTERNAL_SRAM_SIZE - 1) - -#define EEPROM_START (0x0000) -#define EEPROM_SIZE (2048) -#define EEPROM_PAGE_SIZE (32) -#define EEPROM_END (EEPROM_START + EEPROM_SIZE - 1) - -#define SIGNATURES_START (0x0000) -#define SIGNATURES_SIZE (3) -#define SIGNATURES_PAGE_SIZE (0) -#define SIGNATURES_END (SIGNATURES_START + SIGNATURES_SIZE - 1) - -#define FUSES_START (0x0000) -#define FUSES_SIZE (6) -#define FUSES_PAGE_SIZE (0) -#define FUSES_END (FUSES_START + FUSES_SIZE - 1) - -#define LOCKBITS_START (0x0000) -#define LOCKBITS_SIZE (1) -#define LOCKBITS_PAGE_SIZE (0) -#define LOCKBITS_END (LOCKBITS_START + LOCKBITS_SIZE - 1) - -#define USER_SIGNATURES_START (0x0000) -#define USER_SIGNATURES_SIZE (512) -#define USER_SIGNATURES_PAGE_SIZE (512) -#define USER_SIGNATURES_END (USER_SIGNATURES_START + USER_SIGNATURES_SIZE - 1) - -#define PROD_SIGNATURES_START (0x0000) -#define PROD_SIGNATURES_SIZE (64) -#define PROD_SIGNATURES_PAGE_SIZE (512) -#define PROD_SIGNATURES_END (PROD_SIGNATURES_START + PROD_SIGNATURES_SIZE - 1) - -#define FLASHSTART PROGMEM_START -#define FLASHEND PROGMEM_END -#define SPM_PAGESIZE 512 -#define RAMSTART INTERNAL_SRAM_START -#define RAMSIZE INTERNAL_SRAM_SIZE -#define RAMEND INTERNAL_SRAM_END -#define E2END EEPROM_END -#define E2PAGESIZE EEPROM_PAGE_SIZE - - -/* ========== Fuses ========== */ -#define FUSE_MEMORY_SIZE 6 - -/* Fuse Byte 0 */ -#define FUSE_JTAGUSERID0 (unsigned char)~_BV(0) /* JTAG User ID Bit 0 */ -#define FUSE_JTAGUSERID1 (unsigned char)~_BV(1) /* JTAG User ID Bit 1 */ -#define FUSE_JTAGUSERID2 (unsigned char)~_BV(2) /* JTAG User ID Bit 2 */ -#define FUSE_JTAGUSERID3 (unsigned char)~_BV(3) /* JTAG User ID Bit 3 */ -#define FUSE_JTAGUSERID4 (unsigned char)~_BV(4) /* JTAG User ID Bit 4 */ -#define FUSE_JTAGUSERID5 (unsigned char)~_BV(5) /* JTAG User ID Bit 5 */ -#define FUSE_JTAGUSERID6 (unsigned char)~_BV(6) /* JTAG User ID Bit 6 */ -#define FUSE_JTAGUSERID7 (unsigned char)~_BV(7) /* JTAG User ID Bit 7 */ -#define FUSE0_DEFAULT (0xFF) - -/* Fuse Byte 1 */ -#define FUSE_WDP0 (unsigned char)~_BV(0) /* Watchdog Timeout Period Bit 0 */ -#define FUSE_WDP1 (unsigned char)~_BV(1) /* Watchdog Timeout Period Bit 1 */ -#define FUSE_WDP2 (unsigned char)~_BV(2) /* Watchdog Timeout Period Bit 2 */ -#define FUSE_WDP3 (unsigned char)~_BV(3) /* Watchdog Timeout Period Bit 3 */ -#define FUSE_WDWP0 (unsigned char)~_BV(4) /* Watchdog Window Timeout Period Bit 0 */ -#define FUSE_WDWP1 (unsigned char)~_BV(5) /* Watchdog Window Timeout Period Bit 1 */ -#define FUSE_WDWP2 (unsigned char)~_BV(6) /* Watchdog Window Timeout Period Bit 2 */ -#define FUSE_WDWP3 (unsigned char)~_BV(7) /* Watchdog Window Timeout Period Bit 3 */ -#define FUSE1_DEFAULT (0xFF) - -/* Fuse Byte 2 */ -#define FUSE_BODPD0 (unsigned char)~_BV(0) /* BOD Operation in Power-Down Mode Bit 0 */ -#define FUSE_BODPD1 (unsigned char)~_BV(1) /* BOD Operation in Power-Down Mode Bit 1 */ -#define FUSE_TOSCSEL (unsigned char)~_BV(5) /* Timer Oscillator pin location */ -#define FUSE_BOOTRST (unsigned char)~_BV(6) /* Boot Loader Section Reset Vector */ -#define FUSE2_DEFAULT (0xFF) - -/* Fuse Byte 3 Reserved */ - -/* Fuse Byte 4 */ -#define FUSE_JTAGEN (unsigned char)~_BV(0) /* JTAG Interface Enable */ -#define FUSE_WDLOCK (unsigned char)~_BV(1) /* Watchdog Timer Lock */ -#define FUSE_SUT0 (unsigned char)~_BV(2) /* Start-up Time Bit 0 */ -#define FUSE_SUT1 (unsigned char)~_BV(3) /* Start-up Time Bit 1 */ -#define FUSE_RSTDISBL (unsigned char)~_BV(4) /* External Reset Disable */ -#define FUSE4_DEFAULT (0xFF) - -/* Fuse Byte 5 */ -#define FUSE_BODLVL0 (unsigned char)~_BV(0) /* Brownout Detection Voltage Level Bit 0 */ -#define FUSE_BODLVL1 (unsigned char)~_BV(1) /* Brownout Detection Voltage Level Bit 1 */ -#define FUSE_BODLVL2 (unsigned char)~_BV(2) /* Brownout Detection Voltage Level Bit 2 */ -#define FUSE_EESAVE (unsigned char)~_BV(3) /* Preserve EEPROM Through Chip Erase */ -#define FUSE_BODACT0 (unsigned char)~_BV(4) /* BOD Operation in Active Mode Bit 0 */ -#define FUSE_BODACT1 (unsigned char)~_BV(5) /* BOD Operation in Active Mode Bit 1 */ -#define FUSE5_DEFAULT (0xFF) - -/* ========== Lock Bits ========== */ -#define __LOCK_BITS_EXIST -#define __BOOT_LOCK_APPLICATION_TABLE_BITS_EXIST -#define __BOOT_LOCK_APPLICATION_BITS_EXIST -#define __BOOT_LOCK_BOOT_BITS_EXIST - -/* ========== Signature ========== */ -#define SIGNATURE_0 0x1E -#define SIGNATURE_1 0x97 -#define SIGNATURE_2 0x4C - -/* ========== Power Reduction Condition Definitions ========== */ - -/* PR.PRGEN */ -#define __AVR_HAVE_PRGEN (PR_USB_bm|PR_AES_bm|PR_EBI_bm|PR_RTC_bm|PR_EVSYS_bm|PR_DMA_bm) -#define __AVR_HAVE_PRGEN_USB -#define __AVR_HAVE_PRGEN_AES -#define __AVR_HAVE_PRGEN_EBI -#define __AVR_HAVE_PRGEN_RTC -#define __AVR_HAVE_PRGEN_EVSYS -#define __AVR_HAVE_PRGEN_DMA - -/* PR.PRPA */ -#define __AVR_HAVE_PRPA (PR_DAC_bm|PR_ADC_bm|PR_AC_bm) -#define __AVR_HAVE_PRPA_DAC -#define __AVR_HAVE_PRPA_ADC -#define __AVR_HAVE_PRPA_AC - -/* PR.PRPB */ -#define __AVR_HAVE_PRPB (PR_DAC_bm|PR_ADC_bm|PR_AC_bm) -#define __AVR_HAVE_PRPB_DAC -#define __AVR_HAVE_PRPB_ADC -#define __AVR_HAVE_PRPB_AC - -/* PR.PRPC */ -#define __AVR_HAVE_PRPC (PR_TWI_bm|PR_USART1_bm|PR_USART0_bm|PR_SPI_bm|PR_HIRES_bm|PR_TC1_bm|PR_TC0_bm) -#define __AVR_HAVE_PRPC_TWI -#define __AVR_HAVE_PRPC_USART1 -#define __AVR_HAVE_PRPC_USART0 -#define __AVR_HAVE_PRPC_SPI -#define __AVR_HAVE_PRPC_HIRES -#define __AVR_HAVE_PRPC_TC1 -#define __AVR_HAVE_PRPC_TC0 - -/* PR.PRPD */ -#define __AVR_HAVE_PRPD (PR_TWI_bm|PR_USART1_bm|PR_USART0_bm|PR_SPI_bm|PR_HIRES_bm|PR_TC1_bm|PR_TC0_bm) -#define __AVR_HAVE_PRPD_TWI -#define __AVR_HAVE_PRPD_USART1 -#define __AVR_HAVE_PRPD_USART0 -#define __AVR_HAVE_PRPD_SPI -#define __AVR_HAVE_PRPD_HIRES -#define __AVR_HAVE_PRPD_TC1 -#define __AVR_HAVE_PRPD_TC0 - -/* PR.PRPE */ -#define __AVR_HAVE_PRPE (PR_TWI_bm|PR_USART1_bm|PR_USART0_bm|PR_SPI_bm|PR_HIRES_bm|PR_TC1_bm|PR_TC0_bm) -#define __AVR_HAVE_PRPE_TWI -#define __AVR_HAVE_PRPE_USART1 -#define __AVR_HAVE_PRPE_USART0 -#define __AVR_HAVE_PRPE_SPI -#define __AVR_HAVE_PRPE_HIRES -#define __AVR_HAVE_PRPE_TC1 -#define __AVR_HAVE_PRPE_TC0 - -/* PR.PRPF */ -#define __AVR_HAVE_PRPF (PR_TWI_bm|PR_USART1_bm|PR_USART0_bm|PR_SPI_bm|PR_HIRES_bm|PR_TC1_bm|PR_TC0_bm) -#define __AVR_HAVE_PRPF_TWI -#define __AVR_HAVE_PRPF_USART1 -#define __AVR_HAVE_PRPF_USART0 -#define __AVR_HAVE_PRPF_SPI -#define __AVR_HAVE_PRPF_HIRES -#define __AVR_HAVE_PRPF_TC1 -#define __AVR_HAVE_PRPF_TC0 - - -#endif /* #ifdef _AVR_ATXMEGA128A1U_H_INCLUDED */ - diff --git a/arduino/hardware/tools/avr/avr/include/avr/iox128a3.h b/arduino/hardware/tools/avr/avr/include/avr/iox128a3.h deleted file mode 100644 index 14723b3..0000000 --- a/arduino/hardware/tools/avr/avr/include/avr/iox128a3.h +++ /dev/null @@ -1,6987 +0,0 @@ -/* Copyright (c) 2009-2010 Atmel Corporation - All rights reserved. - - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - * Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - * Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in - the documentation and/or other materials provided with the - distribution. - - * Neither the name of the copyright holders nor the names of - contributors may be used to endorse or promote products derived - from this software without specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. */ - -/* $Id: iox128a3.h 2200 2010-12-14 04:24:24Z arcanum $ */ - -/* avr/iox128a3.h - definitions for ATxmega128A3 */ - -/* This file should only be included from , never directly. */ - -#ifndef _AVR_IO_H_ -# error "Include instead of this file." -#endif - -#ifndef _AVR_IOXXX_H_ -# define _AVR_IOXXX_H_ "iox128a3.h" -#else -# error "Attempt to include more than one file." -#endif - - -#ifndef _AVR_ATxmega128A3_H_ -#define _AVR_ATxmega128A3_H_ 1 - - -/* Ungrouped common registers */ -#define GPIOR0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ -#define GPIOR1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ -#define GPIOR2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ -#define GPIOR3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ -#define GPIOR4 _SFR_MEM8(0x0004) /* General Purpose IO Register 4 */ -#define GPIOR5 _SFR_MEM8(0x0005) /* General Purpose IO Register 5 */ -#define GPIOR6 _SFR_MEM8(0x0006) /* General Purpose IO Register 6 */ -#define GPIOR7 _SFR_MEM8(0x0007) /* General Purpose IO Register 7 */ -#define GPIOR8 _SFR_MEM8(0x0008) /* General Purpose IO Register 8 */ -#define GPIOR9 _SFR_MEM8(0x0009) /* General Purpose IO Register 9 */ -#define GPIORA _SFR_MEM8(0x000A) /* General Purpose IO Register 10 */ -#define GPIORB _SFR_MEM8(0x000B) /* General Purpose IO Register 11 */ -#define GPIORC _SFR_MEM8(0x000C) /* General Purpose IO Register 12 */ -#define GPIORD _SFR_MEM8(0x000D) /* General Purpose IO Register 13 */ -#define GPIORE _SFR_MEM8(0x000E) /* General Purpose IO Register 14 */ -#define GPIORF _SFR_MEM8(0x000F) /* General Purpose IO Register 15 */ - -/* Deprecated */ -#define GPIO0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ -#define GPIO1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ -#define GPIO2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ -#define GPIO3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ -#define GPIO4 _SFR_MEM8(0x0004) /* General Purpose IO Register 4 */ -#define GPIO5 _SFR_MEM8(0x0005) /* General Purpose IO Register 5 */ -#define GPIO6 _SFR_MEM8(0x0006) /* General Purpose IO Register 6 */ -#define GPIO7 _SFR_MEM8(0x0007) /* General Purpose IO Register 7 */ -#define GPIO8 _SFR_MEM8(0x0008) /* General Purpose IO Register 8 */ -#define GPIO9 _SFR_MEM8(0x0009) /* General Purpose IO Register 9 */ -#define GPIOA _SFR_MEM8(0x000A) /* General Purpose IO Register 10 */ -#define GPIOB _SFR_MEM8(0x000B) /* General Purpose IO Register 11 */ -#define GPIOC _SFR_MEM8(0x000C) /* General Purpose IO Register 12 */ -#define GPIOD _SFR_MEM8(0x000D) /* General Purpose IO Register 13 */ -#define GPIOE _SFR_MEM8(0x000E) /* General Purpose IO Register 14 */ -#define GPIOF _SFR_MEM8(0x000F) /* General Purpose IO Register 15 */ - -#define CCP _SFR_MEM8(0x0034) /* Configuration Change Protection */ -#define RAMPD _SFR_MEM8(0x0038) /* Ramp D */ -#define RAMPX _SFR_MEM8(0x0039) /* Ramp X */ -#define RAMPY _SFR_MEM8(0x003A) /* Ramp Y */ -#define RAMPZ _SFR_MEM8(0x003B) /* Ramp Z */ -#define EIND _SFR_MEM8(0x003C) /* Extended Indirect Jump */ -#define SPL _SFR_MEM8(0x003D) /* Stack Pointer Low */ -#define SPH _SFR_MEM8(0x003E) /* Stack Pointer High */ -#define SREG _SFR_MEM8(0x003F) /* Status Register */ - - -/* C Language Only */ -#if !defined (__ASSEMBLER__) - -#include - -typedef volatile uint8_t register8_t; -typedef volatile uint16_t register16_t; -typedef volatile uint32_t register32_t; - - -#ifdef _WORDREGISTER -#undef _WORDREGISTER -#endif -#define _WORDREGISTER(regname) \ - __extension__ union \ - { \ - register16_t regname; \ - struct \ - { \ - register8_t regname ## L; \ - register8_t regname ## H; \ - }; \ - } - -#ifdef _DWORDREGISTER -#undef _DWORDREGISTER -#endif -#define _DWORDREGISTER(regname) \ - __extension__ union \ - { \ - register32_t regname; \ - struct \ - { \ - register8_t regname ## 0; \ - register8_t regname ## 1; \ - register8_t regname ## 2; \ - register8_t regname ## 3; \ - }; \ - } - - -/* -========================================================================== -IO Module Structures -========================================================================== -*/ - - -/* --------------------------------------------------------------------------- -XOCD - On-Chip Debug System --------------------------------------------------------------------------- -*/ - -/* On-Chip Debug System */ -typedef struct OCD_struct -{ - register8_t OCDR0; /* OCD Register 0 */ - register8_t OCDR1; /* OCD Register 1 */ -} OCD_t; - - -/* CCP signatures */ -typedef enum CCP_enum -{ - CCP_SPM_gc = (0x9D<<0), /* SPM Instruction Protection */ - CCP_IOREG_gc = (0xD8<<0), /* IO Register Protection */ -} CCP_t; - - -/* --------------------------------------------------------------------------- -CLK - Clock System --------------------------------------------------------------------------- -*/ - -/* Clock System */ -typedef struct CLK_struct -{ - register8_t CTRL; /* Control Register */ - register8_t PSCTRL; /* Prescaler Control Register */ - register8_t LOCK; /* Lock register */ - register8_t RTCCTRL; /* RTC Control Register */ -} CLK_t; - -/* --------------------------------------------------------------------------- -CLK - Clock System --------------------------------------------------------------------------- -*/ - -/* Power Reduction */ -typedef struct PR_struct -{ - register8_t PRGEN; /* General Power Reduction */ - register8_t PRPA; /* Power Reduction Port A */ - register8_t PRPB; /* Power Reduction Port B */ - register8_t PRPC; /* Power Reduction Port C */ - register8_t PRPD; /* Power Reduction Port D */ - register8_t PRPE; /* Power Reduction Port E */ - register8_t PRPF; /* Power Reduction Port F */ -} PR_t; - -/* System Clock Selection */ -typedef enum CLK_SCLKSEL_enum -{ - CLK_SCLKSEL_RC2M_gc = (0x00<<0), /* Internal 2MHz RC Oscillator */ - CLK_SCLKSEL_RC32M_gc = (0x01<<0), /* Internal 32MHz RC Oscillator */ - CLK_SCLKSEL_RC32K_gc = (0x02<<0), /* Internal 32kHz RC Oscillator */ - CLK_SCLKSEL_XOSC_gc = (0x03<<0), /* External Crystal Oscillator or Clock */ - CLK_SCLKSEL_PLL_gc = (0x04<<0), /* Phase Locked Loop */ -} CLK_SCLKSEL_t; - -/* Prescaler A Division Factor */ -typedef enum CLK_PSADIV_enum -{ - CLK_PSADIV_1_gc = (0x00<<2), /* Divide by 1 */ - CLK_PSADIV_2_gc = (0x01<<2), /* Divide by 2 */ - CLK_PSADIV_4_gc = (0x03<<2), /* Divide by 4 */ - CLK_PSADIV_8_gc = (0x05<<2), /* Divide by 8 */ - CLK_PSADIV_16_gc = (0x07<<2), /* Divide by 16 */ - CLK_PSADIV_32_gc = (0x09<<2), /* Divide by 32 */ - CLK_PSADIV_64_gc = (0x0B<<2), /* Divide by 64 */ - CLK_PSADIV_128_gc = (0x0D<<2), /* Divide by 128 */ - CLK_PSADIV_256_gc = (0x0F<<2), /* Divide by 256 */ - CLK_PSADIV_512_gc = (0x11<<2), /* Divide by 512 */ -} CLK_PSADIV_t; - -/* Prescaler B and C Division Factor */ -typedef enum CLK_PSBCDIV_enum -{ - CLK_PSBCDIV_1_1_gc = (0x00<<0), /* Divide B by 1 and C by 1 */ - CLK_PSBCDIV_1_2_gc = (0x01<<0), /* Divide B by 1 and C by 2 */ - CLK_PSBCDIV_4_1_gc = (0x02<<0), /* Divide B by 4 and C by 1 */ - CLK_PSBCDIV_2_2_gc = (0x03<<0), /* Divide B by 2 and C by 2 */ -} CLK_PSBCDIV_t; - -/* RTC Clock Source */ -typedef enum CLK_RTCSRC_enum -{ - CLK_RTCSRC_ULP_gc = (0x00<<1), /* 1kHz from internal 32kHz ULP */ - CLK_RTCSRC_TOSC_gc = (0x01<<1), /* 1kHz from 32kHz crystal oscillator on TOSC */ - CLK_RTCSRC_RCOSC_gc = (0x02<<1), /* 1kHz from internal 32kHz RC oscillator */ - CLK_RTCSRC_TOSC32_gc = (0x05<<1), /* 32kHz from 32kHz crystal oscillator on TOSC */ -} CLK_RTCSRC_t; - - -/* --------------------------------------------------------------------------- -SLEEP - Sleep Controller --------------------------------------------------------------------------- -*/ - -/* Sleep Controller */ -typedef struct SLEEP_struct -{ - register8_t CTRL; /* Control Register */ -} SLEEP_t; - -/* Sleep Mode */ -typedef enum SLEEP_SMODE_enum -{ - SLEEP_SMODE_IDLE_gc = (0x00<<1), /* Idle mode */ - SLEEP_SMODE_PDOWN_gc = (0x02<<1), /* Power-down Mode */ - SLEEP_SMODE_PSAVE_gc = (0x03<<1), /* Power-save Mode */ - SLEEP_SMODE_STDBY_gc = (0x06<<1), /* Standby Mode */ - SLEEP_SMODE_ESTDBY_gc = (0x07<<1), /* Extended Standby Mode */ -} SLEEP_SMODE_t; - - -#define SLEEP_MODE_IDLE (0x00<<1) -#define SLEEP_MODE_PWR_DOWN (0x02<<1) -#define SLEEP_MODE_PWR_SAVE (0x03<<1) -#define SLEEP_MODE_STANDBY (0x06<<1) -#define SLEEP_MODE_EXT_STANDBY (0x07<<1) - - -/* --------------------------------------------------------------------------- -OSC - Oscillator --------------------------------------------------------------------------- -*/ - -/* Oscillator */ -typedef struct OSC_struct -{ - register8_t CTRL; /* Control Register */ - register8_t STATUS; /* Status Register */ - register8_t XOSCCTRL; /* External Oscillator Control Register */ - register8_t XOSCFAIL; /* External Oscillator Failure Detection Register */ - register8_t RC32KCAL; /* 32kHz Internal Oscillator Calibration Register */ - register8_t PLLCTRL; /* PLL Control REgister */ - register8_t DFLLCTRL; /* DFLL Control Register */ -} OSC_t; - -/* Oscillator Frequency Range */ -typedef enum OSC_FRQRANGE_enum -{ - OSC_FRQRANGE_04TO2_gc = (0x00<<6), /* 0.4 - 2 MHz */ - OSC_FRQRANGE_2TO9_gc = (0x01<<6), /* 2 - 9 MHz */ - OSC_FRQRANGE_9TO12_gc = (0x02<<6), /* 9 - 12 MHz */ - OSC_FRQRANGE_12TO16_gc = (0x03<<6), /* 12 - 16 MHz */ -} OSC_FRQRANGE_t; - -/* External Oscillator Selection and Startup Time */ -typedef enum OSC_XOSCSEL_enum -{ - OSC_XOSCSEL_EXTCLK_gc = (0x00<<0), /* External Clock - 6 CLK */ - OSC_XOSCSEL_32KHz_gc = (0x02<<0), /* 32kHz TOSC - 32K CLK */ - OSC_XOSCSEL_XTAL_256CLK_gc = (0x03<<0), /* 0.4-16MHz XTAL - 256 CLK */ - OSC_XOSCSEL_XTAL_1KCLK_gc = (0x07<<0), /* 0.4-16MHz XTAL - 1K CLK */ - OSC_XOSCSEL_XTAL_16KCLK_gc = (0x0B<<0), /* 0.4-16MHz XTAL - 16K CLK */ -} OSC_XOSCSEL_t; - -/* PLL Clock Source */ -typedef enum OSC_PLLSRC_enum -{ - OSC_PLLSRC_RC2M_gc = (0x00<<6), /* Internal 2MHz RC Oscillator */ - OSC_PLLSRC_RC32M_gc = (0x02<<6), /* Internal 32MHz RC Oscillator */ - OSC_PLLSRC_XOSC_gc = (0x03<<6), /* External Oscillator */ -} OSC_PLLSRC_t; - - -/* --------------------------------------------------------------------------- -DFLL - DFLL --------------------------------------------------------------------------- -*/ - -/* DFLL */ -typedef struct DFLL_struct -{ - register8_t CTRL; /* Control Register */ - register8_t reserved_0x01; - register8_t CALA; /* Calibration Register A */ - register8_t CALB; /* Calibration Register B */ - register8_t COMP0; /* Oscillator Compare Register 0 */ - register8_t COMP1; /* Oscillator Compare Register 1 */ - register8_t COMP2; /* Oscillator Compare Register 2 */ - register8_t reserved_0x07; -} DFLL_t; - - -/* --------------------------------------------------------------------------- -RST - Reset --------------------------------------------------------------------------- -*/ - -/* Reset */ -typedef struct RST_struct -{ - register8_t STATUS; /* Status Register */ - register8_t CTRL; /* Control Register */ -} RST_t; - - -/* --------------------------------------------------------------------------- -WDT - Watch-Dog Timer --------------------------------------------------------------------------- -*/ - -/* Watch-Dog Timer */ -typedef struct WDT_struct -{ - register8_t CTRL; /* Control */ - register8_t WINCTRL; /* Windowed Mode Control */ - register8_t STATUS; /* Status */ -} WDT_t; - -/* Period setting */ -typedef enum WDT_PER_enum -{ - WDT_PER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ - WDT_PER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ - WDT_PER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ - WDT_PER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ - WDT_PER_128CLK_gc = (0x04<<2), /* 128 cycles (0.125s @ 3.3V) */ - WDT_PER_256CLK_gc = (0x05<<2), /* 256 cycles (0.25s @ 3.3V) */ - WDT_PER_512CLK_gc = (0x06<<2), /* 512 cycles (0.5s @ 3.3V) */ - WDT_PER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ - WDT_PER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ - WDT_PER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ - WDT_PER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ -} WDT_PER_t; - -/* Closed window period */ -typedef enum WDT_WPER_enum -{ - WDT_WPER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ - WDT_WPER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ - WDT_WPER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ - WDT_WPER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ - WDT_WPER_128CLK_gc = (0x04<<2), /* 128 cycles (0.125s @ 3.3V) */ - WDT_WPER_256CLK_gc = (0x05<<2), /* 256 cycles (0.25s @ 3.3V) */ - WDT_WPER_512CLK_gc = (0x06<<2), /* 512 cycles (0.5s @ 3.3V) */ - WDT_WPER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ - WDT_WPER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ - WDT_WPER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ - WDT_WPER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ -} WDT_WPER_t; - - -/* --------------------------------------------------------------------------- -MCU - MCU Control --------------------------------------------------------------------------- -*/ - -/* MCU Control */ -typedef struct MCU_struct -{ - register8_t DEVID0; /* Device ID byte 0 */ - register8_t DEVID1; /* Device ID byte 1 */ - register8_t DEVID2; /* Device ID byte 2 */ - register8_t REVID; /* Revision ID */ - register8_t JTAGUID; /* JTAG User ID */ - register8_t reserved_0x05; - register8_t MCUCR; /* MCU Control */ - register8_t reserved_0x07; - register8_t EVSYSLOCK; /* Event System Lock */ - register8_t AWEXLOCK; /* AWEX Lock */ - register8_t reserved_0x0A; - register8_t reserved_0x0B; -} MCU_t; - - -/* --------------------------------------------------------------------------- -PMIC - Programmable Multi-level Interrupt Controller --------------------------------------------------------------------------- -*/ - -/* Programmable Multi-level Interrupt Controller */ -typedef struct PMIC_struct -{ - register8_t STATUS; /* Status Register */ - register8_t INTPRI; /* Interrupt Priority */ - register8_t CTRL; /* Control Register */ -} PMIC_t; - - -/* --------------------------------------------------------------------------- -DMA - DMA Controller --------------------------------------------------------------------------- -*/ - -/* DMA Channel */ -typedef struct DMA_CH_struct -{ - register8_t CTRLA; /* Channel Control */ - register8_t CTRLB; /* Channel Control */ - register8_t ADDRCTRL; /* Address Control */ - register8_t TRIGSRC; /* Channel Trigger Source */ - _WORDREGISTER(TRFCNT); /* Channel Block Transfer Count */ - register8_t REPCNT; /* Channel Repeat Count */ - register8_t reserved_0x07; - register8_t SRCADDR0; /* Channel Source Address 0 */ - register8_t SRCADDR1; /* Channel Source Address 1 */ - register8_t SRCADDR2; /* Channel Source Address 2 */ - register8_t reserved_0x0B; - register8_t DESTADDR0; /* Channel Destination Address 0 */ - register8_t DESTADDR1; /* Channel Destination Address 1 */ - register8_t DESTADDR2; /* Channel Destination Address 2 */ - register8_t reserved_0x0F; -} DMA_CH_t; - -/* --------------------------------------------------------------------------- -DMA - DMA Controller --------------------------------------------------------------------------- -*/ - -/* DMA Controller */ -typedef struct DMA_struct -{ - register8_t CTRL; /* Control */ - register8_t reserved_0x01; - register8_t reserved_0x02; - register8_t INTFLAGS; /* Transfer Interrupt Status */ - register8_t STATUS; /* Status */ - register8_t reserved_0x05; - _WORDREGISTER(TEMP); /* Temporary Register For 16/24-bit Access */ - register8_t reserved_0x08; - register8_t reserved_0x09; - register8_t reserved_0x0A; - register8_t reserved_0x0B; - register8_t reserved_0x0C; - register8_t reserved_0x0D; - register8_t reserved_0x0E; - register8_t reserved_0x0F; - DMA_CH_t CH0; /* DMA Channel 0 */ - DMA_CH_t CH1; /* DMA Channel 1 */ - DMA_CH_t CH2; /* DMA Channel 2 */ - DMA_CH_t CH3; /* DMA Channel 3 */ -} DMA_t; - -/* Burst mode */ -typedef enum DMA_CH_BURSTLEN_enum -{ - DMA_CH_BURSTLEN_1BYTE_gc = (0x00<<0), /* 1-byte burst mode */ - DMA_CH_BURSTLEN_2BYTE_gc = (0x01<<0), /* 2-byte burst mode */ - DMA_CH_BURSTLEN_4BYTE_gc = (0x02<<0), /* 4-byte burst mode */ - DMA_CH_BURSTLEN_8BYTE_gc = (0x03<<0), /* 8-byte burst mode */ -} DMA_CH_BURSTLEN_t; - -/* Source address reload mode */ -typedef enum DMA_CH_SRCRELOAD_enum -{ - DMA_CH_SRCRELOAD_NONE_gc = (0x00<<6), /* No reload */ - DMA_CH_SRCRELOAD_BLOCK_gc = (0x01<<6), /* Reload at end of block */ - DMA_CH_SRCRELOAD_BURST_gc = (0x02<<6), /* Reload at end of burst */ - DMA_CH_SRCRELOAD_TRANSACTION_gc = (0x03<<6), /* Reload at end of transaction */ -} DMA_CH_SRCRELOAD_t; - -/* Source addressing mode */ -typedef enum DMA_CH_SRCDIR_enum -{ - DMA_CH_SRCDIR_FIXED_gc = (0x00<<4), /* Fixed */ - DMA_CH_SRCDIR_INC_gc = (0x01<<4), /* Increment */ - DMA_CH_SRCDIR_DEC_gc = (0x02<<4), /* Decrement */ -} DMA_CH_SRCDIR_t; - -/* Destination adress reload mode */ -typedef enum DMA_CH_DESTRELOAD_enum -{ - DMA_CH_DESTRELOAD_NONE_gc = (0x00<<2), /* No reload */ - DMA_CH_DESTRELOAD_BLOCK_gc = (0x01<<2), /* Reload at end of block */ - DMA_CH_DESTRELOAD_BURST_gc = (0x02<<2), /* Reload at end of burst */ - DMA_CH_DESTRELOAD_TRANSACTION_gc = (0x03<<2), /* Reload at end of transaction */ -} DMA_CH_DESTRELOAD_t; - -/* Destination adressing mode */ -typedef enum DMA_CH_DESTDIR_enum -{ - DMA_CH_DESTDIR_FIXED_gc = (0x00<<0), /* Fixed */ - DMA_CH_DESTDIR_INC_gc = (0x01<<0), /* Increment */ - DMA_CH_DESTDIR_DEC_gc = (0x02<<0), /* Decrement */ -} DMA_CH_DESTDIR_t; - -/* Transfer trigger source */ -typedef enum DMA_CH_TRIGSRC_enum -{ - DMA_CH_TRIGSRC_OFF_gc = (0x00<<0), /* Off software triggers only */ - DMA_CH_TRIGSRC_EVSYS_CH0_gc = (0x01<<0), /* Event System Channel 0 */ - DMA_CH_TRIGSRC_EVSYS_CH1_gc = (0x02<<0), /* Event System Channel 1 */ - DMA_CH_TRIGSRC_EVSYS_CH2_gc = (0x03<<0), /* Event System Channel 2 */ - DMA_CH_TRIGSRC_ADCA_CH0_gc = (0x10<<0), /* ADCA Channel 0 */ - DMA_CH_TRIGSRC_ADCA_CH1_gc = (0x11<<0), /* ADCA Channel 1 */ - DMA_CH_TRIGSRC_ADCA_CH2_gc = (0x12<<0), /* ADCA Channel 2 */ - DMA_CH_TRIGSRC_ADCA_CH3_gc = (0x13<<0), /* ADCA Channel 3 */ - DMA_CH_TRIGSRC_ADCA_CH4_gc = (0x14<<0), /* ADCA Channel 0,1,2,3 combined */ - DMA_CH_TRIGSRC_DACA_CH0_gc = (0x15<<0), /* DACA Channel 0 */ - DMA_CH_TRIGSRC_DACA_CH1_gc = (0x16<<0), /* DACA Channel 1 */ - DMA_CH_TRIGSRC_ADCB_CH0_gc = (0x20<<0), /* ADCB Channel 0 */ - DMA_CH_TRIGSRC_ADCB_CH1_gc = (0x21<<0), /* ADCB Channel 1 */ - DMA_CH_TRIGSRC_ADCB_CH2_gc = (0x22<<0), /* ADCB Channel 2 */ - DMA_CH_TRIGSRC_ADCB_CH3_gc = (0x23<<0), /* ADCB Channel 3 */ - DMA_CH_TRIGSRC_ADCB_CH4_gc = (0x24<<0), /* ADCB Channel 0,1,2,3 combined */ - DMA_CH_TRIGSRC_DACB_CH0_gc = (0x25<<0), /* DACB Channel 0 */ - DMA_CH_TRIGSRC_DACB_CH1_gc = (0x26<<0), /* DACB Channel 1 */ - DMA_CH_TRIGSRC_TCC0_OVF_gc = (0x40<<0), /* Timer/Counter C0 Overflow */ - DMA_CH_TRIGSRC_TCC0_ERR_gc = (0x41<<0), /* Timer/Counter C0 Error */ - DMA_CH_TRIGSRC_TCC0_CCA_gc = (0x42<<0), /* Timer/Counter C0 Compare or Capture A */ - DMA_CH_TRIGSRC_TCC0_CCB_gc = (0x43<<0), /* Timer/Counter C0 Compare or Capture B */ - DMA_CH_TRIGSRC_TCC0_CCC_gc = (0x44<<0), /* Timer/Counter C0 Compare or Capture C */ - DMA_CH_TRIGSRC_TCC0_CCD_gc = (0x45<<0), /* Timer/Counter C0 Compare or Capture D */ - DMA_CH_TRIGSRC_TCC1_OVF_gc = (0x46<<0), /* Timer/Counter C1 Overflow */ - DMA_CH_TRIGSRC_TCC1_ERR_gc = (0x47<<0), /* Timer/Counter C1 Error */ - DMA_CH_TRIGSRC_TCC1_CCA_gc = (0x48<<0), /* Timer/Counter C1 Compare or Capture A */ - DMA_CH_TRIGSRC_TCC1_CCB_gc = (0x49<<0), /* Timer/Counter C1 Compare or Capture B */ - DMA_CH_TRIGSRC_SPIC_gc = (0x4A<<0), /* SPI C Transfer Complete */ - DMA_CH_TRIGSRC_USARTC0_RXC_gc = (0x4B<<0), /* USART C0 Receive Complete */ - DMA_CH_TRIGSRC_USARTC0_DRE_gc = (0x4C<<0), /* USART C0 Data Register Empty */ - DMA_CH_TRIGSRC_USARTC1_RXC_gc = (0x4E<<0), /* USART C1 Receive Complete */ - DMA_CH_TRIGSRC_USARTC1_DRE_gc = (0x4F<<0), /* USART C1 Data Register Empty */ - DMA_CH_TRIGSRC_TCD0_OVF_gc = (0x60<<0), /* Timer/Counter D0 Overflow */ - DMA_CH_TRIGSRC_TCD0_ERR_gc = (0x61<<0), /* Timer/Counter D0 Error */ - DMA_CH_TRIGSRC_TCD0_CCA_gc = (0x62<<0), /* Timer/Counter D0 Compare or Capture A */ - DMA_CH_TRIGSRC_TCD0_CCB_gc = (0x63<<0), /* Timer/Counter D0 Compare or Capture B */ - DMA_CH_TRIGSRC_TCD0_CCC_gc = (0x64<<0), /* Timer/Counter D0 Compare or Capture C */ - DMA_CH_TRIGSRC_TCD0_CCD_gc = (0x65<<0), /* Timer/Counter D0 Compare or Capture D */ - DMA_CH_TRIGSRC_TCD1_OVF_gc = (0x66<<0), /* Timer/Counter D1 Overflow */ - DMA_CH_TRIGSRC_TCD1_ERR_gc = (0x67<<0), /* Timer/Counter D1 Error */ - DMA_CH_TRIGSRC_TCD1_CCA_gc = (0x68<<0), /* Timer/Counter D1 Compare or Capture A */ - DMA_CH_TRIGSRC_TCD1_CCB_gc = (0x69<<0), /* Timer/Counter D1 Compare or Capture B */ - DMA_CH_TRIGSRC_SPID_gc = (0x6A<<0), /* SPI D Transfer Complete */ - DMA_CH_TRIGSRC_USARTD0_RXC_gc = (0x6B<<0), /* USART D0 Receive Complete */ - DMA_CH_TRIGSRC_USARTD0_DRE_gc = (0x6C<<0), /* USART D0 Data Register Empty */ - DMA_CH_TRIGSRC_USARTD1_RXC_gc = (0x6E<<0), /* USART D1 Receive Complete */ - DMA_CH_TRIGSRC_USARTD1_DRE_gc = (0x6F<<0), /* USART D1 Data Register Empty */ - DMA_CH_TRIGSRC_TCE0_OVF_gc = (0x80<<0), /* Timer/Counter E0 Overflow */ - DMA_CH_TRIGSRC_TCE0_ERR_gc = (0x81<<0), /* Timer/Counter E0 Error */ - DMA_CH_TRIGSRC_TCE0_CCA_gc = (0x82<<0), /* Timer/Counter E0 Compare or Capture A */ - DMA_CH_TRIGSRC_TCE0_CCB_gc = (0x83<<0), /* Timer/Counter E0 Compare or Capture B */ - DMA_CH_TRIGSRC_TCE0_CCC_gc = (0x84<<0), /* Timer/Counter E0 Compare or Capture C */ - DMA_CH_TRIGSRC_TCE0_CCD_gc = (0x85<<0), /* Timer/Counter E0 Compare or Capture D */ - DMA_CH_TRIGSRC_TCE1_OVF_gc = (0x86<<0), /* Timer/Counter E1 Overflow */ - DMA_CH_TRIGSRC_TCE1_ERR_gc = (0x87<<0), /* Timer/Counter E1 Error */ - DMA_CH_TRIGSRC_TCE1_CCA_gc = (0x88<<0), /* Timer/Counter E1 Compare or Capture A */ - DMA_CH_TRIGSRC_TCE1_CCB_gc = (0x89<<0), /* Timer/Counter E1 Compare or Capture B */ - DMA_CH_TRIGSRC_SPIE_gc = (0x8A<<0), /* SPI E Transfer Complete */ - DMA_CH_TRIGSRC_USARTE0_RXC_gc = (0x8B<<0), /* USART E0 Receive Complete */ - DMA_CH_TRIGSRC_USARTE0_DRE_gc = (0x8C<<0), /* USART E0 Data Register Empty */ - DMA_CH_TRIGSRC_USARTE1_RXC_gc = (0x8E<<0), /* USART E1 Receive Complete */ - DMA_CH_TRIGSRC_USARTE1_DRE_gc = (0x8F<<0), /* USART E1 Data Register Empty */ - DMA_CH_TRIGSRC_TCF0_OVF_gc = (0xA0<<0), /* Timer/Counter F0 Overflow */ - DMA_CH_TRIGSRC_TCF0_ERR_gc = (0xA1<<0), /* Timer/Counter F0 Error */ - DMA_CH_TRIGSRC_TCF0_CCA_gc = (0xA2<<0), /* Timer/Counter F0 Compare or Capture A */ - DMA_CH_TRIGSRC_TCF0_CCB_gc = (0xA3<<0), /* Timer/Counter F0 Compare or Capture B */ - DMA_CH_TRIGSRC_TCF0_CCC_gc = (0xA4<<0), /* Timer/Counter F0 Compare or Capture C */ - DMA_CH_TRIGSRC_TCF0_CCD_gc = (0xA5<<0), /* Timer/Counter F0 Compare or Capture D */ - DMA_CH_TRIGSRC_TCF1_OVF_gc = (0xA6<<0), /* Timer/Counter F1 Overflow */ - DMA_CH_TRIGSRC_TCF1_ERR_gc = (0xA7<<0), /* Timer/Counter F1 Error */ - DMA_CH_TRIGSRC_TCF1_CCA_gc = (0xA8<<0), /* Timer/Counter F1 Compare or Capture A */ - DMA_CH_TRIGSRC_TCF1_CCB_gc = (0xA9<<0), /* Timer/Counter F1 Compare or Capture B */ - DMA_CH_TRIGSRC_SPIF_gc = (0xAA<<0), /* SPI F Transfer Complete */ - DMA_CH_TRIGSRC_USARTF0_RXC_gc = (0xAB<<0), /* USART F0 Receive Complete */ - DMA_CH_TRIGSRC_USARTF0_DRE_gc = (0xAC<<0), /* USART F0 Data Register Empty */ - DMA_CH_TRIGSRC_USARTF1_RXC_gc = (0xAE<<0), /* USART F1 Receive Complete */ - DMA_CH_TRIGSRC_USARTF1_DRE_gc = (0xAF<<0), /* USART F1 Data Register Empty */ -} DMA_CH_TRIGSRC_t; - -/* Double buffering mode */ -typedef enum DMA_DBUFMODE_enum -{ - DMA_DBUFMODE_DISABLED_gc = (0x00<<2), /* Double buffering disabled */ - DMA_DBUFMODE_CH01_gc = (0x01<<2), /* Double buffering enabled on channel 0/1 */ - DMA_DBUFMODE_CH23_gc = (0x02<<2), /* Double buffering enabled on channel 2/3 */ - DMA_DBUFMODE_CH01CH23_gc = (0x03<<2), /* Double buffering enabled on ch. 0/1 and ch. 2/3 */ -} DMA_DBUFMODE_t; - -/* Priority mode */ -typedef enum DMA_PRIMODE_enum -{ - DMA_PRIMODE_RR0123_gc = (0x00<<0), /* Round Robin */ - DMA_PRIMODE_CH0RR123_gc = (0x01<<0), /* Channel 0 > Round Robin on channel 1/2/3 */ - DMA_PRIMODE_CH01RR23_gc = (0x02<<0), /* Channel 0 > channel 1 > Round Robin on channel 2/3 */ - DMA_PRIMODE_CH0123_gc = (0x03<<0), /* Channel 0 > channel 1 > channel 2 > channel 3 */ -} DMA_PRIMODE_t; - -/* Interrupt level */ -typedef enum DMA_CH_ERRINTLVL_enum -{ - DMA_CH_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ - DMA_CH_ERRINTLVL_LO_gc = (0x01<<2), /* Low level */ - DMA_CH_ERRINTLVL_MED_gc = (0x02<<2), /* Medium level */ - DMA_CH_ERRINTLVL_HI_gc = (0x03<<2), /* High level */ -} DMA_CH_ERRINTLVL_t; - -/* Interrupt level */ -typedef enum DMA_CH_TRNINTLVL_enum -{ - DMA_CH_TRNINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ - DMA_CH_TRNINTLVL_LO_gc = (0x01<<0), /* Low level */ - DMA_CH_TRNINTLVL_MED_gc = (0x02<<0), /* Medium level */ - DMA_CH_TRNINTLVL_HI_gc = (0x03<<0), /* High level */ -} DMA_CH_TRNINTLVL_t; - - -/* --------------------------------------------------------------------------- -EVSYS - Event System --------------------------------------------------------------------------- -*/ - -/* Event System */ -typedef struct EVSYS_struct -{ - register8_t CH0MUX; /* Event Channel 0 Multiplexer */ - register8_t CH1MUX; /* Event Channel 1 Multiplexer */ - register8_t CH2MUX; /* Event Channel 2 Multiplexer */ - register8_t CH3MUX; /* Event Channel 3 Multiplexer */ - register8_t CH4MUX; /* Event Channel 4 Multiplexer */ - register8_t CH5MUX; /* Event Channel 5 Multiplexer */ - register8_t CH6MUX; /* Event Channel 6 Multiplexer */ - register8_t CH7MUX; /* Event Channel 7 Multiplexer */ - register8_t CH0CTRL; /* Channel 0 Control Register */ - register8_t CH1CTRL; /* Channel 1 Control Register */ - register8_t CH2CTRL; /* Channel 2 Control Register */ - register8_t CH3CTRL; /* Channel 3 Control Register */ - register8_t CH4CTRL; /* Channel 4 Control Register */ - register8_t CH5CTRL; /* Channel 5 Control Register */ - register8_t CH6CTRL; /* Channel 6 Control Register */ - register8_t CH7CTRL; /* Channel 7 Control Register */ - register8_t STROBE; /* Event Strobe */ - register8_t DATA; /* Event Data */ -} EVSYS_t; - -/* Quadrature Decoder Index Recognition Mode */ -typedef enum EVSYS_QDIRM_enum -{ - EVSYS_QDIRM_00_gc = (0x00<<5), /* QDPH0 = 0, QDPH90 = 0 */ - EVSYS_QDIRM_01_gc = (0x01<<5), /* QDPH0 = 0, QDPH90 = 1 */ - EVSYS_QDIRM_10_gc = (0x02<<5), /* QDPH0 = 1, QDPH90 = 0 */ - EVSYS_QDIRM_11_gc = (0x03<<5), /* QDPH0 = 1, QDPH90 = 1 */ -} EVSYS_QDIRM_t; - -/* Digital filter coefficient */ -typedef enum EVSYS_DIGFILT_enum -{ - EVSYS_DIGFILT_1SAMPLE_gc = (0x00<<0), /* 1 SAMPLE */ - EVSYS_DIGFILT_2SAMPLES_gc = (0x01<<0), /* 2 SAMPLES */ - EVSYS_DIGFILT_3SAMPLES_gc = (0x02<<0), /* 3 SAMPLES */ - EVSYS_DIGFILT_4SAMPLES_gc = (0x03<<0), /* 4 SAMPLES */ - EVSYS_DIGFILT_5SAMPLES_gc = (0x04<<0), /* 5 SAMPLES */ - EVSYS_DIGFILT_6SAMPLES_gc = (0x05<<0), /* 6 SAMPLES */ - EVSYS_DIGFILT_7SAMPLES_gc = (0x06<<0), /* 7 SAMPLES */ - EVSYS_DIGFILT_8SAMPLES_gc = (0x07<<0), /* 8 SAMPLES */ -} EVSYS_DIGFILT_t; - -/* Event Channel multiplexer input selection */ -typedef enum EVSYS_CHMUX_enum -{ - EVSYS_CHMUX_OFF_gc = (0x00<<0), /* Off */ - EVSYS_CHMUX_RTC_OVF_gc = (0x08<<0), /* RTC Overflow */ - EVSYS_CHMUX_RTC_CMP_gc = (0x09<<0), /* RTC Compare Match */ - EVSYS_CHMUX_ACA_CH0_gc = (0x10<<0), /* Analog Comparator A Channel 0 */ - EVSYS_CHMUX_ACA_CH1_gc = (0x11<<0), /* Analog Comparator A Channel 1 */ - EVSYS_CHMUX_ACA_WIN_gc = (0x12<<0), /* Analog Comparator A Window */ - EVSYS_CHMUX_ACB_CH0_gc = (0x13<<0), /* Analog Comparator B Channel 0 */ - EVSYS_CHMUX_ACB_CH1_gc = (0x14<<0), /* Analog Comparator B Channel 1 */ - EVSYS_CHMUX_ACB_WIN_gc = (0x15<<0), /* Analog Comparator B Window */ - EVSYS_CHMUX_ADCA_CH0_gc = (0x20<<0), /* ADC A Channel 0 */ - EVSYS_CHMUX_ADCA_CH1_gc = (0x21<<0), /* ADC A Channel 1 */ - EVSYS_CHMUX_ADCA_CH2_gc = (0x22<<0), /* ADC A Channel 2 */ - EVSYS_CHMUX_ADCA_CH3_gc = (0x23<<0), /* ADC A Channel 3 */ - EVSYS_CHMUX_ADCB_CH0_gc = (0x24<<0), /* ADC B Channel 0 */ - EVSYS_CHMUX_ADCB_CH1_gc = (0x25<<0), /* ADC B Channel 1 */ - EVSYS_CHMUX_ADCB_CH2_gc = (0x26<<0), /* ADC B Channel 2 */ - EVSYS_CHMUX_ADCB_CH3_gc = (0x27<<0), /* ADC B Channel 3 */ - EVSYS_CHMUX_PORTA_PIN0_gc = (0x50<<0), /* Port A, Pin0 */ - EVSYS_CHMUX_PORTA_PIN1_gc = (0x51<<0), /* Port A, Pin1 */ - EVSYS_CHMUX_PORTA_PIN2_gc = (0x52<<0), /* Port A, Pin2 */ - EVSYS_CHMUX_PORTA_PIN3_gc = (0x53<<0), /* Port A, Pin3 */ - EVSYS_CHMUX_PORTA_PIN4_gc = (0x54<<0), /* Port A, Pin4 */ - EVSYS_CHMUX_PORTA_PIN5_gc = (0x55<<0), /* Port A, Pin5 */ - EVSYS_CHMUX_PORTA_PIN6_gc = (0x56<<0), /* Port A, Pin6 */ - EVSYS_CHMUX_PORTA_PIN7_gc = (0x57<<0), /* Port A, Pin7 */ - EVSYS_CHMUX_PORTB_PIN0_gc = (0x58<<0), /* Port B, Pin0 */ - EVSYS_CHMUX_PORTB_PIN1_gc = (0x59<<0), /* Port B, Pin1 */ - EVSYS_CHMUX_PORTB_PIN2_gc = (0x5A<<0), /* Port B, Pin2 */ - EVSYS_CHMUX_PORTB_PIN3_gc = (0x5B<<0), /* Port B, Pin3 */ - EVSYS_CHMUX_PORTB_PIN4_gc = (0x5C<<0), /* Port B, Pin4 */ - EVSYS_CHMUX_PORTB_PIN5_gc = (0x5D<<0), /* Port B, Pin5 */ - EVSYS_CHMUX_PORTB_PIN6_gc = (0x5E<<0), /* Port B, Pin6 */ - EVSYS_CHMUX_PORTB_PIN7_gc = (0x5F<<0), /* Port B, Pin7 */ - EVSYS_CHMUX_PORTC_PIN0_gc = (0x60<<0), /* Port C, Pin0 */ - EVSYS_CHMUX_PORTC_PIN1_gc = (0x61<<0), /* Port C, Pin1 */ - EVSYS_CHMUX_PORTC_PIN2_gc = (0x62<<0), /* Port C, Pin2 */ - EVSYS_CHMUX_PORTC_PIN3_gc = (0x63<<0), /* Port C, Pin3 */ - EVSYS_CHMUX_PORTC_PIN4_gc = (0x64<<0), /* Port C, Pin4 */ - EVSYS_CHMUX_PORTC_PIN5_gc = (0x65<<0), /* Port C, Pin5 */ - EVSYS_CHMUX_PORTC_PIN6_gc = (0x66<<0), /* Port C, Pin6 */ - EVSYS_CHMUX_PORTC_PIN7_gc = (0x67<<0), /* Port C, Pin7 */ - EVSYS_CHMUX_PORTD_PIN0_gc = (0x68<<0), /* Port D, Pin0 */ - EVSYS_CHMUX_PORTD_PIN1_gc = (0x69<<0), /* Port D, Pin1 */ - EVSYS_CHMUX_PORTD_PIN2_gc = (0x6A<<0), /* Port D, Pin2 */ - EVSYS_CHMUX_PORTD_PIN3_gc = (0x6B<<0), /* Port D, Pin3 */ - EVSYS_CHMUX_PORTD_PIN4_gc = (0x6C<<0), /* Port D, Pin4 */ - EVSYS_CHMUX_PORTD_PIN5_gc = (0x6D<<0), /* Port D, Pin5 */ - EVSYS_CHMUX_PORTD_PIN6_gc = (0x6E<<0), /* Port D, Pin6 */ - EVSYS_CHMUX_PORTD_PIN7_gc = (0x6F<<0), /* Port D, Pin7 */ - EVSYS_CHMUX_PORTE_PIN0_gc = (0x70<<0), /* Port E, Pin0 */ - EVSYS_CHMUX_PORTE_PIN1_gc = (0x71<<0), /* Port E, Pin1 */ - EVSYS_CHMUX_PORTE_PIN2_gc = (0x72<<0), /* Port E, Pin2 */ - EVSYS_CHMUX_PORTE_PIN3_gc = (0x73<<0), /* Port E, Pin3 */ - EVSYS_CHMUX_PORTE_PIN4_gc = (0x74<<0), /* Port E, Pin4 */ - EVSYS_CHMUX_PORTE_PIN5_gc = (0x75<<0), /* Port E, Pin5 */ - EVSYS_CHMUX_PORTE_PIN6_gc = (0x76<<0), /* Port E, Pin6 */ - EVSYS_CHMUX_PORTE_PIN7_gc = (0x77<<0), /* Port E, Pin7 */ - EVSYS_CHMUX_PORTF_PIN0_gc = (0x78<<0), /* Port F, Pin0 */ - EVSYS_CHMUX_PORTF_PIN1_gc = (0x79<<0), /* Port F, Pin1 */ - EVSYS_CHMUX_PORTF_PIN2_gc = (0x7A<<0), /* Port F, Pin2 */ - EVSYS_CHMUX_PORTF_PIN3_gc = (0x7B<<0), /* Port F, Pin3 */ - EVSYS_CHMUX_PORTF_PIN4_gc = (0x7C<<0), /* Port F, Pin4 */ - EVSYS_CHMUX_PORTF_PIN5_gc = (0x7D<<0), /* Port F, Pin5 */ - EVSYS_CHMUX_PORTF_PIN6_gc = (0x7E<<0), /* Port F, Pin6 */ - EVSYS_CHMUX_PORTF_PIN7_gc = (0x7F<<0), /* Port F, Pin7 */ - EVSYS_CHMUX_PRESCALER_1_gc = (0x80<<0), /* Prescaler, divide by 1 */ - EVSYS_CHMUX_PRESCALER_2_gc = (0x81<<0), /* Prescaler, divide by 2 */ - EVSYS_CHMUX_PRESCALER_4_gc = (0x82<<0), /* Prescaler, divide by 4 */ - EVSYS_CHMUX_PRESCALER_8_gc = (0x83<<0), /* Prescaler, divide by 8 */ - EVSYS_CHMUX_PRESCALER_16_gc = (0x84<<0), /* Prescaler, divide by 16 */ - EVSYS_CHMUX_PRESCALER_32_gc = (0x85<<0), /* Prescaler, divide by 32 */ - EVSYS_CHMUX_PRESCALER_64_gc = (0x86<<0), /* Prescaler, divide by 64 */ - EVSYS_CHMUX_PRESCALER_128_gc = (0x87<<0), /* Prescaler, divide by 128 */ - EVSYS_CHMUX_PRESCALER_256_gc = (0x88<<0), /* Prescaler, divide by 256 */ - EVSYS_CHMUX_PRESCALER_512_gc = (0x89<<0), /* Prescaler, divide by 512 */ - EVSYS_CHMUX_PRESCALER_1024_gc = (0x8A<<0), /* Prescaler, divide by 1024 */ - EVSYS_CHMUX_PRESCALER_2048_gc = (0x8B<<0), /* Prescaler, divide by 2048 */ - EVSYS_CHMUX_PRESCALER_4096_gc = (0x8C<<0), /* Prescaler, divide by 4096 */ - EVSYS_CHMUX_PRESCALER_8192_gc = (0x8D<<0), /* Prescaler, divide by 8192 */ - EVSYS_CHMUX_PRESCALER_16384_gc = (0x8E<<0), /* Prescaler, divide by 16384 */ - EVSYS_CHMUX_PRESCALER_32768_gc = (0x8F<<0), /* Prescaler, divide by 32768 */ - EVSYS_CHMUX_TCC0_OVF_gc = (0xC0<<0), /* Timer/Counter C0 Overflow */ - EVSYS_CHMUX_TCC0_ERR_gc = (0xC1<<0), /* Timer/Counter C0 Error */ - EVSYS_CHMUX_TCC0_CCA_gc = (0xC4<<0), /* Timer/Counter C0 Compare or Capture A */ - EVSYS_CHMUX_TCC0_CCB_gc = (0xC5<<0), /* Timer/Counter C0 Compare or Capture B */ - EVSYS_CHMUX_TCC0_CCC_gc = (0xC6<<0), /* Timer/Counter C0 Compare or Capture C */ - EVSYS_CHMUX_TCC0_CCD_gc = (0xC7<<0), /* Timer/Counter C0 Compare or Capture D */ - EVSYS_CHMUX_TCC1_OVF_gc = (0xC8<<0), /* Timer/Counter C1 Overflow */ - EVSYS_CHMUX_TCC1_ERR_gc = (0xC9<<0), /* Timer/Counter C1 Error */ - EVSYS_CHMUX_TCC1_CCA_gc = (0xCC<<0), /* Timer/Counter C1 Compare or Capture A */ - EVSYS_CHMUX_TCC1_CCB_gc = (0xCD<<0), /* Timer/Counter C1 Compare or Capture B */ - EVSYS_CHMUX_TCD0_OVF_gc = (0xD0<<0), /* Timer/Counter D0 Overflow */ - EVSYS_CHMUX_TCD0_ERR_gc = (0xD1<<0), /* Timer/Counter D0 Error */ - EVSYS_CHMUX_TCD0_CCA_gc = (0xD4<<0), /* Timer/Counter D0 Compare or Capture A */ - EVSYS_CHMUX_TCD0_CCB_gc = (0xD5<<0), /* Timer/Counter D0 Compare or Capture B */ - EVSYS_CHMUX_TCD0_CCC_gc = (0xD6<<0), /* Timer/Counter D0 Compare or Capture C */ - EVSYS_CHMUX_TCD0_CCD_gc = (0xD7<<0), /* Timer/Counter D0 Compare or Capture D */ - EVSYS_CHMUX_TCD1_OVF_gc = (0xD8<<0), /* Timer/Counter D1 Overflow */ - EVSYS_CHMUX_TCD1_ERR_gc = (0xD9<<0), /* Timer/Counter D1 Error */ - EVSYS_CHMUX_TCD1_CCA_gc = (0xDC<<0), /* Timer/Counter D1 Compare or Capture A */ - EVSYS_CHMUX_TCD1_CCB_gc = (0xDD<<0), /* Timer/Counter D1 Compare or Capture B */ - EVSYS_CHMUX_TCE0_OVF_gc = (0xE0<<0), /* Timer/Counter E0 Overflow */ - EVSYS_CHMUX_TCE0_ERR_gc = (0xE1<<0), /* Timer/Counter E0 Error */ - EVSYS_CHMUX_TCE0_CCA_gc = (0xE4<<0), /* Timer/Counter E0 Compare or Capture A */ - EVSYS_CHMUX_TCE0_CCB_gc = (0xE5<<0), /* Timer/Counter E0 Compare or Capture B */ - EVSYS_CHMUX_TCE0_CCC_gc = (0xE6<<0), /* Timer/Counter E0 Compare or Capture C */ - EVSYS_CHMUX_TCE0_CCD_gc = (0xE7<<0), /* Timer/Counter E0 Compare or Capture D */ - EVSYS_CHMUX_TCE1_OVF_gc = (0xE8<<0), /* Timer/Counter E1 Overflow */ - EVSYS_CHMUX_TCE1_ERR_gc = (0xE9<<0), /* Timer/Counter E1 Error */ - EVSYS_CHMUX_TCE1_CCA_gc = (0xEC<<0), /* Timer/Counter E1 Compare or Capture A */ - EVSYS_CHMUX_TCE1_CCB_gc = (0xED<<0), /* Timer/Counter E1 Compare or Capture B */ - EVSYS_CHMUX_TCF0_OVF_gc = (0xF0<<0), /* Timer/Counter F0 Overflow */ - EVSYS_CHMUX_TCF0_ERR_gc = (0xF1<<0), /* Timer/Counter F0 Error */ - EVSYS_CHMUX_TCF0_CCA_gc = (0xF4<<0), /* Timer/Counter F0 Compare or Capture A */ - EVSYS_CHMUX_TCF0_CCB_gc = (0xF5<<0), /* Timer/Counter F0 Compare or Capture B */ - EVSYS_CHMUX_TCF0_CCC_gc = (0xF6<<0), /* Timer/Counter F0 Compare or Capture C */ - EVSYS_CHMUX_TCF0_CCD_gc = (0xF7<<0), /* Timer/Counter F0 Compare or Capture D */ - EVSYS_CHMUX_TCF1_OVF_gc = (0xF8<<0), /* Timer/Counter F1 Overflow */ - EVSYS_CHMUX_TCF1_ERR_gc = (0xF9<<0), /* Timer/Counter F1 Error */ - EVSYS_CHMUX_TCF1_CCA_gc = (0xFC<<0), /* Timer/Counter F1 Compare or Capture A */ - EVSYS_CHMUX_TCF1_CCB_gc = (0xFD<<0), /* Timer/Counter F1 Compare or Capture B */ -} EVSYS_CHMUX_t; - - -/* --------------------------------------------------------------------------- -NVM - Non Volatile Memory Controller --------------------------------------------------------------------------- -*/ - -/* Non-volatile Memory Controller */ -typedef struct NVM_struct -{ - register8_t ADDR0; /* Address Register 0 */ - register8_t ADDR1; /* Address Register 1 */ - register8_t ADDR2; /* Address Register 2 */ - register8_t reserved_0x03; - register8_t DATA0; /* Data Register 0 */ - register8_t DATA1; /* Data Register 1 */ - register8_t DATA2; /* Data Register 2 */ - register8_t reserved_0x07; - register8_t reserved_0x08; - register8_t reserved_0x09; - register8_t CMD; /* Command */ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t INTCTRL; /* Interrupt Control */ - register8_t reserved_0x0E; - register8_t STATUS; /* Status */ - register8_t LOCK_BITS; /* Lock Bits */ -} NVM_t; - -/* --------------------------------------------------------------------------- -NVM - Non Volatile Memory Controller --------------------------------------------------------------------------- -*/ - -/* Lock Bits */ -typedef struct NVM_LOCKBITS_struct -{ - register8_t LOCKBITS; /* Lock Bits */ -} NVM_LOCKBITS_t; - -/* --------------------------------------------------------------------------- -NVM - Non Volatile Memory Controller --------------------------------------------------------------------------- -*/ - -/* Fuses */ -typedef struct NVM_FUSES_struct -{ - register8_t FUSEBYTE0; /* JTAG User ID */ - register8_t FUSEBYTE1; /* Watchdog Configuration */ - register8_t FUSEBYTE2; /* Reset Configuration */ - register8_t reserved_0x03; - register8_t FUSEBYTE4; /* Start-up Configuration */ - register8_t FUSEBYTE5; /* EESAVE and BOD Level */ -} NVM_FUSES_t; - -/* --------------------------------------------------------------------------- -NVM - Non Volatile Memory Controller --------------------------------------------------------------------------- -*/ - -/* Production Signatures */ -typedef struct NVM_PROD_SIGNATURES_struct -{ - register8_t RCOSC2M; /* RCOSC 2MHz Calibration Value */ - register8_t reserved_0x01; - register8_t RCOSC32K; /* RCOSC 32kHz Calibration Value */ - register8_t RCOSC32M; /* RCOSC 32MHz Calibration Value */ - register8_t reserved_0x04; - register8_t reserved_0x05; - register8_t reserved_0x06; - register8_t reserved_0x07; - register8_t LOTNUM0; /* Lot Number Byte 0, ASCII */ - register8_t LOTNUM1; /* Lot Number Byte 1, ASCII */ - register8_t LOTNUM2; /* Lot Number Byte 2, ASCII */ - register8_t LOTNUM3; /* Lot Number Byte 3, ASCII */ - register8_t LOTNUM4; /* Lot Number Byte 4, ASCII */ - register8_t LOTNUM5; /* Lot Number Byte 5, ASCII */ - register8_t reserved_0x0E; - register8_t reserved_0x0F; - register8_t WAFNUM; /* Wafer Number */ - register8_t reserved_0x11; - register8_t COORDX0; /* Wafer Coordinate X Byte 0 */ - register8_t COORDX1; /* Wafer Coordinate X Byte 1 */ - register8_t COORDY0; /* Wafer Coordinate Y Byte 0 */ - register8_t COORDY1; /* Wafer Coordinate Y Byte 1 */ - register8_t reserved_0x16; - register8_t reserved_0x17; - register8_t reserved_0x18; - register8_t reserved_0x19; - register8_t reserved_0x1A; - register8_t reserved_0x1B; - register8_t reserved_0x1C; - register8_t reserved_0x1D; - register8_t reserved_0x1E; - register8_t reserved_0x1F; - register8_t ADCACAL0; /* ADCA Calibration Byte 0 */ - register8_t ADCACAL1; /* ADCA Calibration Byte 1 */ - register8_t reserved_0x22; - register8_t reserved_0x23; - register8_t ADCBCAL0; /* ADCB Calibration Byte 0 */ - register8_t ADCBCAL1; /* ADCB Calibration Byte 1 */ - register8_t reserved_0x26; - register8_t reserved_0x27; - register8_t reserved_0x28; - register8_t reserved_0x29; - register8_t reserved_0x2A; - register8_t reserved_0x2B; - register8_t reserved_0x2C; - register8_t reserved_0x2D; - register8_t TEMPSENSE0; /* Temperature Sensor Calibration Byte 0 */ - register8_t TEMPSENSE1; /* Temperature Sensor Calibration Byte 0 */ - register8_t DACAOFFCAL; /* DACA Calibration Byte 0 */ - register8_t DACAGAINCAL; /* DACA Calibration Byte 1 */ - register8_t DACBOFFCAL; /* DACB Calibration Byte 0 */ - register8_t DACBGAINCAL; /* DACB Calibration Byte 1 */ - register8_t reserved_0x34; - register8_t reserved_0x35; - register8_t reserved_0x36; - register8_t reserved_0x37; - register8_t reserved_0x38; - register8_t reserved_0x39; - register8_t reserved_0x3A; - register8_t reserved_0x3B; - register8_t reserved_0x3C; - register8_t reserved_0x3D; - register8_t reserved_0x3E; -} NVM_PROD_SIGNATURES_t; - -/* NVM Command */ -typedef enum NVM_CMD_enum -{ - NVM_CMD_NO_OPERATION_gc = (0x00<<0), /* Noop/Ordinary LPM */ - NVM_CMD_READ_CALIB_ROW_gc = (0x02<<0), /* Read calibration row */ - NVM_CMD_READ_USER_SIG_ROW_gc = (0x01<<0), /* Read user signature row */ - NVM_CMD_READ_EEPROM_gc = (0x06<<0), /* Read EEPROM */ - NVM_CMD_READ_FUSES_gc = (0x07<<0), /* Read fuse byte */ - NVM_CMD_WRITE_LOCK_BITS_gc = (0x08<<0), /* Write lock bits */ - NVM_CMD_ERASE_USER_SIG_ROW_gc = (0x18<<0), /* Erase user signature row */ - NVM_CMD_WRITE_USER_SIG_ROW_gc = (0x1A<<0), /* Write user signature row */ - NVM_CMD_ERASE_APP_gc = (0x20<<0), /* Erase Application Section */ - NVM_CMD_ERASE_APP_PAGE_gc = (0x22<<0), /* Erase Application Section page */ - NVM_CMD_LOAD_FLASH_BUFFER_gc = (0x23<<0), /* Load Flash page buffer */ - NVM_CMD_WRITE_APP_PAGE_gc = (0x24<<0), /* Write Application Section page */ - NVM_CMD_ERASE_WRITE_APP_PAGE_gc = (0x25<<0), /* Erase-and-write Application Section page */ - NVM_CMD_ERASE_FLASH_BUFFER_gc = (0x26<<0), /* Erase/flush Flash page buffer */ - NVM_CMD_ERASE_BOOT_PAGE_gc = (0x2A<<0), /* Erase Boot Section page */ - NVM_CMD_WRITE_BOOT_PAGE_gc = (0x2C<<0), /* Write Boot Section page */ - NVM_CMD_ERASE_WRITE_BOOT_PAGE_gc = (0x2D<<0), /* Erase-and-write Boot Section page */ - NVM_CMD_ERASE_EEPROM_gc = (0x30<<0), /* Erase EEPROM */ - NVM_CMD_ERASE_EEPROM_PAGE_gc = (0x32<<0), /* Erase EEPROM page */ - NVM_CMD_LOAD_EEPROM_BUFFER_gc = (0x33<<0), /* Load EEPROM page buffer */ - NVM_CMD_WRITE_EEPROM_PAGE_gc = (0x34<<0), /* Write EEPROM page */ - NVM_CMD_ERASE_WRITE_EEPROM_PAGE_gc = (0x35<<0), /* Erase-and-write EEPROM page */ - NVM_CMD_ERASE_EEPROM_BUFFER_gc = (0x36<<0), /* Erase/flush EEPROM page buffer */ - NVM_CMD_APP_CRC_gc = (0x38<<0), /* Generate Application section CRC */ - NVM_CMD_BOOT_CRC_gc = (0x39<<0), /* Generate Boot Section CRC */ - NVM_CMD_FLASH_RANGE_CRC_gc = (0x3A<<0), /* Generate Flash Range CRC */ -} NVM_CMD_t; - -/* SPM ready interrupt level */ -typedef enum NVM_SPMLVL_enum -{ - NVM_SPMLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ - NVM_SPMLVL_LO_gc = (0x01<<2), /* Low level */ - NVM_SPMLVL_MED_gc = (0x02<<2), /* Medium level */ - NVM_SPMLVL_HI_gc = (0x03<<2), /* High level */ -} NVM_SPMLVL_t; - -/* EEPROM ready interrupt level */ -typedef enum NVM_EELVL_enum -{ - NVM_EELVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ - NVM_EELVL_LO_gc = (0x01<<0), /* Low level */ - NVM_EELVL_MED_gc = (0x02<<0), /* Medium level */ - NVM_EELVL_HI_gc = (0x03<<0), /* High level */ -} NVM_EELVL_t; - -/* Boot lock bits - boot setcion */ -typedef enum NVM_BLBB_enum -{ - NVM_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ - NVM_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ - NVM_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ - NVM_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ -} NVM_BLBB_t; - -/* Boot lock bits - application section */ -typedef enum NVM_BLBA_enum -{ - NVM_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ - NVM_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ - NVM_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ - NVM_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ -} NVM_BLBA_t; - -/* Boot lock bits - application table section */ -typedef enum NVM_BLBAT_enum -{ - NVM_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ - NVM_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ - NVM_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ - NVM_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ -} NVM_BLBAT_t; - -/* Lock bits */ -typedef enum NVM_LB_enum -{ - NVM_LB_NOLOCK_gc = (0x03<<0), /* No locks */ - NVM_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ - NVM_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ -} NVM_LB_t; - -/* Boot Loader Section Reset Vector */ -typedef enum BOOTRST_enum -{ - BOOTRST_BOOTLDR_gc = (0x00<<6), /* Boot Loader Reset */ - BOOTRST_APPLICATION_gc = (0x01<<6), /* Application Reset */ -} BOOTRST_t; - -/* BOD operation */ -typedef enum BOD_enum -{ - BOD_INSAMPLEDMODE_gc = (0x01<<0), /* BOD enabled in sampled mode */ - BOD_CONTINOUSLY_gc = (0x02<<0), /* BOD enabled continuously */ - BOD_DISABLED_gc = (0x03<<0), /* BOD Disabled */ -} BOD_t; - -/* Watchdog (Window) Timeout Period */ -typedef enum WD_enum -{ - WD_8CLK_gc = (0x00<<4), /* 8 cycles (8ms @ 3.3V) */ - WD_16CLK_gc = (0x01<<4), /* 16 cycles (16ms @ 3.3V) */ - WD_32CLK_gc = (0x02<<4), /* 32 cycles (32ms @ 3.3V) */ - WD_64CLK_gc = (0x03<<4), /* 64 cycles (64ms @ 3.3V) */ - WD_128CLK_gc = (0x04<<4), /* 128 cycles (0.125s @ 3.3V) */ - WD_256CLK_gc = (0x05<<4), /* 256 cycles (0.25s @ 3.3V) */ - WD_512CLK_gc = (0x06<<4), /* 512 cycles (0.5s @ 3.3V) */ - WD_1KCLK_gc = (0x07<<4), /* 1K cycles (1s @ 3.3V) */ - WD_2KCLK_gc = (0x08<<4), /* 2K cycles (2s @ 3.3V) */ - WD_4KCLK_gc = (0x09<<4), /* 4K cycles (4s @ 3.3V) */ - WD_8KCLK_gc = (0x0A<<4), /* 8K cycles (8s @ 3.3V) */ -} WD_t; - -/* Start-up Time */ -typedef enum SUT_enum -{ - SUT_0MS_gc = (0x03<<2), /* 0 ms */ - SUT_4MS_gc = (0x01<<2), /* 4 ms */ - SUT_64MS_gc = (0x00<<2), /* 64 ms */ -} SUT_t; - -/* Brown Out Detection Voltage Level */ -typedef enum BODLVL_enum -{ - BODLVL_1V6_gc = (0x07<<0), /* 1.6 V */ - BODLVL_1V9_gc = (0x06<<0), /* 1.8 V */ - BODLVL_2V1_gc = (0x05<<0), /* 2.0 V */ - BODLVL_2V4_gc = (0x04<<0), /* 2.2 V */ - BODLVL_2V6_gc = (0x03<<0), /* 2.4 V */ - BODLVL_2V9_gc = (0x02<<0), /* 2.7 V */ - BODLVL_3V2_gc = (0x01<<0), /* 2.9 V */ -} BODLVL_t; - - -/* --------------------------------------------------------------------------- -AC - Analog Comparator --------------------------------------------------------------------------- -*/ - -/* Analog Comparator */ -typedef struct AC_struct -{ - register8_t AC0CTRL; /* Comparator 0 Control */ - register8_t AC1CTRL; /* Comparator 1 Control */ - register8_t AC0MUXCTRL; /* Comparator 0 MUX Control */ - register8_t AC1MUXCTRL; /* Comparator 1 MUX Control */ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t WINCTRL; /* Window Mode Control */ - register8_t STATUS; /* Status */ -} AC_t; - -/* Interrupt mode */ -typedef enum AC_INTMODE_enum -{ - AC_INTMODE_BOTHEDGES_gc = (0x00<<6), /* Interrupt on both edges */ - AC_INTMODE_FALLING_gc = (0x02<<6), /* Interrupt on falling edge */ - AC_INTMODE_RISING_gc = (0x03<<6), /* Interrupt on rising edge */ -} AC_INTMODE_t; - -/* Interrupt level */ -typedef enum AC_INTLVL_enum -{ - AC_INTLVL_OFF_gc = (0x00<<4), /* Interrupt disabled */ - AC_INTLVL_LO_gc = (0x01<<4), /* Low level */ - AC_INTLVL_MED_gc = (0x02<<4), /* Medium level */ - AC_INTLVL_HI_gc = (0x03<<4), /* High level */ -} AC_INTLVL_t; - -/* Hysteresis mode selection */ -typedef enum AC_HYSMODE_enum -{ - AC_HYSMODE_NO_gc = (0x00<<1), /* No hysteresis */ - AC_HYSMODE_SMALL_gc = (0x01<<1), /* Small hysteresis */ - AC_HYSMODE_LARGE_gc = (0x02<<1), /* Large hysteresis */ -} AC_HYSMODE_t; - -/* Positive input multiplexer selection */ -typedef enum AC_MUXPOS_enum -{ - AC_MUXPOS_PIN0_gc = (0x00<<3), /* Pin 0 */ - AC_MUXPOS_PIN1_gc = (0x01<<3), /* Pin 1 */ - AC_MUXPOS_PIN2_gc = (0x02<<3), /* Pin 2 */ - AC_MUXPOS_PIN3_gc = (0x03<<3), /* Pin 3 */ - AC_MUXPOS_PIN4_gc = (0x04<<3), /* Pin 4 */ - AC_MUXPOS_PIN5_gc = (0x05<<3), /* Pin 5 */ - AC_MUXPOS_PIN6_gc = (0x06<<3), /* Pin 6 */ - AC_MUXPOS_DAC_gc = (0x07<<3), /* DAC output */ -} AC_MUXPOS_t; - -/* Negative input multiplexer selection */ -typedef enum AC_MUXNEG_enum -{ - AC_MUXNEG_PIN0_gc = (0x00<<0), /* Pin 0 */ - AC_MUXNEG_PIN1_gc = (0x01<<0), /* Pin 1 */ - AC_MUXNEG_PIN3_gc = (0x02<<0), /* Pin 3 */ - AC_MUXNEG_PIN5_gc = (0x03<<0), /* Pin 5 */ - AC_MUXNEG_PIN7_gc = (0x04<<0), /* Pin 7 */ - AC_MUXNEG_DAC_gc = (0x05<<0), /* DAC output */ - AC_MUXNEG_BANDGAP_gc = (0x06<<0), /* Bandgap Reference */ - AC_MUXNEG_SCALER_gc = (0x07<<0), /* Internal voltage scaler */ -} AC_MUXNEG_t; - -/* Windows interrupt mode */ -typedef enum AC_WINTMODE_enum -{ - AC_WINTMODE_ABOVE_gc = (0x00<<2), /* Interrupt on above window */ - AC_WINTMODE_INSIDE_gc = (0x01<<2), /* Interrupt on inside window */ - AC_WINTMODE_BELOW_gc = (0x02<<2), /* Interrupt on below window */ - AC_WINTMODE_OUTSIDE_gc = (0x03<<2), /* Interrupt on outside window */ -} AC_WINTMODE_t; - -/* Window interrupt level */ -typedef enum AC_WINTLVL_enum -{ - AC_WINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ - AC_WINTLVL_LO_gc = (0x01<<0), /* Low priority */ - AC_WINTLVL_MED_gc = (0x02<<0), /* Medium priority */ - AC_WINTLVL_HI_gc = (0x03<<0), /* High priority */ -} AC_WINTLVL_t; - -/* Window mode state */ -typedef enum AC_WSTATE_enum -{ - AC_WSTATE_ABOVE_gc = (0x00<<6), /* Signal above window */ - AC_WSTATE_INSIDE_gc = (0x01<<6), /* Signal inside window */ - AC_WSTATE_BELOW_gc = (0x02<<6), /* Signal below window */ -} AC_WSTATE_t; - - -/* --------------------------------------------------------------------------- -ADC - Analog/Digital Converter --------------------------------------------------------------------------- -*/ - -/* ADC Channel */ -typedef struct ADC_CH_struct -{ - register8_t CTRL; /* Control Register */ - register8_t MUXCTRL; /* MUX Control */ - register8_t INTCTRL; /* Channel Interrupt Control */ - register8_t INTFLAGS; /* Interrupt Flags */ - _WORDREGISTER(RES); /* Channel Result */ - register8_t reserved_0x6; - register8_t reserved_0x7; -} ADC_CH_t; - -/* --------------------------------------------------------------------------- -ADC - Analog/Digital Converter --------------------------------------------------------------------------- -*/ - -/* Analog-to-Digital Converter */ -typedef struct ADC_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t REFCTRL; /* Reference Control */ - register8_t EVCTRL; /* Event Control */ - register8_t PRESCALER; /* Clock Prescaler */ - register8_t reserved_0x05; - register8_t INTFLAGS; /* Interrupt Flags */ - register8_t reserved_0x07; - register8_t reserved_0x08; - register8_t reserved_0x09; - register8_t reserved_0x0A; - register8_t reserved_0x0B; - _WORDREGISTER(CAL); /* Calibration Value */ - register8_t reserved_0x0E; - register8_t reserved_0x0F; - _WORDREGISTER(CH0RES); /* Channel 0 Result */ - _WORDREGISTER(CH1RES); /* Channel 1 Result */ - _WORDREGISTER(CH2RES); /* Channel 2 Result */ - _WORDREGISTER(CH3RES); /* Channel 3 Result */ - _WORDREGISTER(CMP); /* Compare Value */ - register8_t reserved_0x1A; - register8_t reserved_0x1B; - register8_t reserved_0x1C; - register8_t reserved_0x1D; - register8_t reserved_0x1E; - register8_t reserved_0x1F; - ADC_CH_t CH0; /* ADC Channel 0 */ - ADC_CH_t CH1; /* ADC Channel 1 */ - ADC_CH_t CH2; /* ADC Channel 2 */ - ADC_CH_t CH3; /* ADC Channel 3 */ -} ADC_t; - -/* Positive input multiplexer selection */ -typedef enum ADC_CH_MUXPOS_enum -{ - ADC_CH_MUXPOS_PIN0_gc = (0x00<<3), /* Input pin 0 */ - ADC_CH_MUXPOS_PIN1_gc = (0x01<<3), /* Input pin 1 */ - ADC_CH_MUXPOS_PIN2_gc = (0x02<<3), /* Input pin 2 */ - ADC_CH_MUXPOS_PIN3_gc = (0x03<<3), /* Input pin 3 */ - ADC_CH_MUXPOS_PIN4_gc = (0x04<<3), /* Input pin 4 */ - ADC_CH_MUXPOS_PIN5_gc = (0x05<<3), /* Input pin 5 */ - ADC_CH_MUXPOS_PIN6_gc = (0x06<<3), /* Input pin 6 */ - ADC_CH_MUXPOS_PIN7_gc = (0x07<<3), /* Input pin 7 */ -} ADC_CH_MUXPOS_t; - -/* Internal input multiplexer selections */ -typedef enum ADC_CH_MUXINT_enum -{ - ADC_CH_MUXINT_TEMP_gc = (0x00<<3), /* Temperature Reference */ - ADC_CH_MUXINT_BANDGAP_gc = (0x01<<3), /* Bandgap Reference */ - ADC_CH_MUXINT_SCALEDVCC_gc = (0x02<<3), /* 1/10 scaled VCC */ - ADC_CH_MUXINT_DAC_gc = (0x03<<3), /* DAC output */ -} ADC_CH_MUXINT_t; - -/* Negative input multiplexer selection */ -typedef enum ADC_CH_MUXNEG_enum -{ - ADC_CH_MUXNEG_PIN0_gc = (0x00<<0), /* Input pin 0 */ - ADC_CH_MUXNEG_PIN1_gc = (0x01<<0), /* Input pin 1 */ - ADC_CH_MUXNEG_PIN2_gc = (0x02<<0), /* Input pin 2 */ - ADC_CH_MUXNEG_PIN3_gc = (0x03<<0), /* Input pin 3 */ - ADC_CH_MUXNEG_PIN4_gc = (0x04<<0), /* Input pin 4 */ - ADC_CH_MUXNEG_PIN5_gc = (0x05<<0), /* Input pin 5 */ - ADC_CH_MUXNEG_PIN6_gc = (0x06<<0), /* Input pin 6 */ - ADC_CH_MUXNEG_PIN7_gc = (0x07<<0), /* Input pin 7 */ -} ADC_CH_MUXNEG_t; - -/* Input mode */ -typedef enum ADC_CH_INPUTMODE_enum -{ - ADC_CH_INPUTMODE_INTERNAL_gc = (0x00<<0), /* Internal inputs, no gain */ - ADC_CH_INPUTMODE_SINGLEENDED_gc = (0x01<<0), /* Single-ended input, no gain */ - ADC_CH_INPUTMODE_DIFF_gc = (0x02<<0), /* Differential input, no gain */ - ADC_CH_INPUTMODE_DIFFWGAIN_gc = (0x03<<0), /* Differential input, with gain */ -} ADC_CH_INPUTMODE_t; - -/* Gain factor */ -typedef enum ADC_CH_GAIN_enum -{ - ADC_CH_GAIN_1X_gc = (0x00<<2), /* 1x gain */ - ADC_CH_GAIN_2X_gc = (0x01<<2), /* 2x gain */ - ADC_CH_GAIN_4X_gc = (0x02<<2), /* 4x gain */ - ADC_CH_GAIN_8X_gc = (0x03<<2), /* 8x gain */ - ADC_CH_GAIN_16X_gc = (0x04<<2), /* 16x gain */ - ADC_CH_GAIN_32X_gc = (0x05<<2), /* 32x gain */ - ADC_CH_GAIN_64X_gc = (0x06<<2), /* 64x gain */ -} ADC_CH_GAIN_t; - -/* Conversion result resolution */ -typedef enum ADC_RESOLUTION_enum -{ - ADC_RESOLUTION_12BIT_gc = (0x00<<1), /* 12-bit right-adjusted result */ - ADC_RESOLUTION_8BIT_gc = (0x02<<1), /* 8-bit right-adjusted result */ - ADC_RESOLUTION_LEFT12BIT_gc = (0x03<<1), /* 12-bit left-adjusted result */ -} ADC_RESOLUTION_t; - -/* Voltage reference selection */ -typedef enum ADC_REFSEL_enum -{ - ADC_REFSEL_INT1V_gc = (0x00<<4), /* Internal 1V */ - ADC_REFSEL_VCC_gc = (0x01<<4), /* Internal VCC / 1.6V */ - ADC_REFSEL_AREFA_gc = (0x02<<4), /* External reference on PORT A */ - ADC_REFSEL_AREFB_gc = (0x03<<4), /* External reference on PORT B */ -} ADC_REFSEL_t; - -/* Channel sweep selection */ -typedef enum ADC_SWEEP_enum -{ - ADC_SWEEP_0_gc = (0x00<<6), /* ADC Channel 0 */ - ADC_SWEEP_01_gc = (0x01<<6), /* ADC Channel 0,1 */ - ADC_SWEEP_012_gc = (0x02<<6), /* ADC Channel 0,1,2 */ - ADC_SWEEP_0123_gc = (0x03<<6), /* ADC Channel 0,1,2,3 */ -} ADC_SWEEP_t; - -/* Event channel input selection */ -typedef enum ADC_EVSEL_enum -{ - ADC_EVSEL_0123_gc = (0x00<<3), /* Event Channel 0,1,2,3 */ - ADC_EVSEL_1234_gc = (0x01<<3), /* Event Channel 1,2,3,4 */ - ADC_EVSEL_2345_gc = (0x02<<3), /* Event Channel 2,3,4,5 */ - ADC_EVSEL_3456_gc = (0x03<<3), /* Event Channel 3,4,5,6 */ - ADC_EVSEL_4567_gc = (0x04<<3), /* Event Channel 4,5,6,7 */ - ADC_EVSEL_567_gc = (0x05<<3), /* Event Channel 5,6,7 */ - ADC_EVSEL_67_gc = (0x06<<3), /* Event Channel 6,7 */ - ADC_EVSEL_7_gc = (0x07<<3), /* Event Channel 7 */ -} ADC_EVSEL_t; - -/* Event action selection */ -typedef enum ADC_EVACT_enum -{ - ADC_EVACT_NONE_gc = (0x00<<0), /* No event action */ - ADC_EVACT_CH0_gc = (0x01<<0), /* First event triggers channel 0 */ - ADC_EVACT_CH01_gc = (0x02<<0), /* First two events trigger channel 0,1 */ - ADC_EVACT_CH012_gc = (0x03<<0), /* First three events trigger channel 0,1,2 */ - ADC_EVACT_CH0123_gc = (0x04<<0), /* Events trigger channel 0,1,2,3 */ - ADC_EVACT_SWEEP_gc = (0x05<<0), /* First event triggers sweep */ - ADC_EVACT_SYNCHSWEEP_gc = (0x06<<0), /* First event triggers synchronized sweep */ -} ADC_EVACT_t; - -/* Interupt mode */ -typedef enum ADC_CH_INTMODE_enum -{ - ADC_CH_INTMODE_COMPLETE_gc = (0x00<<2), /* Interrupt on conversion complete */ - ADC_CH_INTMODE_BELOW_gc = (0x01<<2), /* Interrupt on result below compare value */ - ADC_CH_INTMODE_ABOVE_gc = (0x03<<2), /* Interrupt on result above compare value */ -} ADC_CH_INTMODE_t; - -/* Interrupt level */ -typedef enum ADC_CH_INTLVL_enum -{ - ADC_CH_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ - ADC_CH_INTLVL_LO_gc = (0x01<<0), /* Low level */ - ADC_CH_INTLVL_MED_gc = (0x02<<0), /* Medium level */ - ADC_CH_INTLVL_HI_gc = (0x03<<0), /* High level */ -} ADC_CH_INTLVL_t; - -/* DMA request selection */ -typedef enum ADC_DMASEL_enum -{ - ADC_DMASEL_OFF_gc = (0x00<<6), /* Combined DMA request OFF */ - ADC_DMASEL_CH01_gc = (0x01<<6), /* ADC Channel 0 or 1 */ - ADC_DMASEL_CH012_gc = (0x02<<6), /* ADC Channel 0 or 1 or 2 */ - ADC_DMASEL_CH0123_gc = (0x03<<6), /* ADC Channel 0 or 1 or 2 or 3 */ -} ADC_DMASEL_t; - -/* Clock prescaler */ -typedef enum ADC_PRESCALER_enum -{ - ADC_PRESCALER_DIV4_gc = (0x00<<0), /* Divide clock by 4 */ - ADC_PRESCALER_DIV8_gc = (0x01<<0), /* Divide clock by 8 */ - ADC_PRESCALER_DIV16_gc = (0x02<<0), /* Divide clock by 16 */ - ADC_PRESCALER_DIV32_gc = (0x03<<0), /* Divide clock by 32 */ - ADC_PRESCALER_DIV64_gc = (0x04<<0), /* Divide clock by 64 */ - ADC_PRESCALER_DIV128_gc = (0x05<<0), /* Divide clock by 128 */ - ADC_PRESCALER_DIV256_gc = (0x06<<0), /* Divide clock by 256 */ - ADC_PRESCALER_DIV512_gc = (0x07<<0), /* Divide clock by 512 */ -} ADC_PRESCALER_t; - - -/* --------------------------------------------------------------------------- -DAC - Digital/Analog Converter --------------------------------------------------------------------------- -*/ - -/* Digital-to-Analog Converter */ -typedef struct DAC_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t CTRLC; /* Control Register C */ - register8_t EVCTRL; /* Event Input Control */ - register8_t TIMCTRL; /* Timing Control */ - register8_t STATUS; /* Status */ - register8_t reserved_0x06; - register8_t reserved_0x07; - register8_t GAINCAL; /* Gain Calibration */ - register8_t OFFSETCAL; /* Offset Calibration */ - register8_t reserved_0x0A; - register8_t reserved_0x0B; - register8_t reserved_0x0C; - register8_t reserved_0x0D; - register8_t reserved_0x0E; - register8_t reserved_0x0F; - register8_t reserved_0x10; - register8_t reserved_0x11; - register8_t reserved_0x12; - register8_t reserved_0x13; - register8_t reserved_0x14; - register8_t reserved_0x15; - register8_t reserved_0x16; - register8_t reserved_0x17; - _WORDREGISTER(CH0DATA); /* Channel 0 Data */ - _WORDREGISTER(CH1DATA); /* Channel 1 Data */ -} DAC_t; - -/* Output channel selection */ -typedef enum DAC_CHSEL_enum -{ - DAC_CHSEL_SINGLE_gc = (0x00<<5), /* Single channel operation (Channel A only) */ - DAC_CHSEL_DUAL_gc = (0x02<<5), /* Dual channel operation (S/H on both channels) */ -} DAC_CHSEL_t; - -/* Reference voltage selection */ -typedef enum DAC_REFSEL_enum -{ - DAC_REFSEL_INT1V_gc = (0x00<<3), /* Internal 1V */ - DAC_REFSEL_AVCC_gc = (0x01<<3), /* Analog supply voltage */ - DAC_REFSEL_AREFA_gc = (0x02<<3), /* External reference on AREF on PORTA */ - DAC_REFSEL_AREFB_gc = (0x03<<3), /* External reference on AREF on PORTB */ -} DAC_REFSEL_t; - -/* Event channel selection */ -typedef enum DAC_EVSEL_enum -{ - DAC_EVSEL_0_gc = (0x00<<0), /* Event Channel 0 */ - DAC_EVSEL_1_gc = (0x01<<0), /* Event Channel 1 */ - DAC_EVSEL_2_gc = (0x02<<0), /* Event Channel 2 */ - DAC_EVSEL_3_gc = (0x03<<0), /* Event Channel 3 */ - DAC_EVSEL_4_gc = (0x04<<0), /* Event Channel 4 */ - DAC_EVSEL_5_gc = (0x05<<0), /* Event Channel 5 */ - DAC_EVSEL_6_gc = (0x06<<0), /* Event Channel 6 */ - DAC_EVSEL_7_gc = (0x07<<0), /* Event Channel 7 */ -} DAC_EVSEL_t; - -/* Conversion interval */ -typedef enum DAC_CONINTVAL_enum -{ - DAC_CONINTVAL_1CLK_gc = (0x00<<4), /* 1 CLK / 2 CLK in S/H mode */ - DAC_CONINTVAL_2CLK_gc = (0x01<<4), /* 2 CLK / 3 CLK in S/H mode */ - DAC_CONINTVAL_4CLK_gc = (0x02<<4), /* 4 CLK / 6 CLK in S/H mode */ - DAC_CONINTVAL_8CLK_gc = (0x03<<4), /* 8 CLK / 12 CLK in S/H mode */ - DAC_CONINTVAL_16CLK_gc = (0x04<<4), /* 16 CLK / 24 CLK in S/H mode */ - DAC_CONINTVAL_32CLK_gc = (0x05<<4), /* 32 CLK / 48 CLK in S/H mode */ - DAC_CONINTVAL_64CLK_gc = (0x06<<4), /* 64 CLK / 96 CLK in S/H mode */ - DAC_CONINTVAL_128CLK_gc = (0x07<<4), /* 128 CLK / 192 CLK in S/H mode */ -} DAC_CONINTVAL_t; - -/* Refresh rate */ -typedef enum DAC_REFRESH_enum -{ - DAC_REFRESH_16CLK_gc = (0x00<<0), /* 16 CLK */ - DAC_REFRESH_32CLK_gc = (0x01<<0), /* 32 CLK */ - DAC_REFRESH_64CLK_gc = (0x02<<0), /* 64 CLK */ - DAC_REFRESH_128CLK_gc = (0x03<<0), /* 128 CLK */ - DAC_REFRESH_256CLK_gc = (0x04<<0), /* 256 CLK */ - DAC_REFRESH_512CLK_gc = (0x05<<0), /* 512 CLK */ - DAC_REFRESH_1024CLK_gc = (0x06<<0), /* 1024 CLK */ - DAC_REFRESH_2048CLK_gc = (0x07<<0), /* 2048 CLK */ - DAC_REFRESH_4096CLK_gc = (0x08<<0), /* 4096 CLK */ - DAC_REFRESH_8192CLK_gc = (0x09<<0), /* 8192 CLK */ - DAC_REFRESH_16384CLK_gc = (0x0A<<0), /* 16384 CLK */ - DAC_REFRESH_32768CLK_gc = (0x0B<<0), /* 32768 CLK */ - DAC_REFRESH_65536CLK_gc = (0x0C<<0), /* 65536 CLK */ - DAC_REFRESH_OFF_gc = (0x0F<<0), /* Auto refresh OFF */ -} DAC_REFRESH_t; - - -/* --------------------------------------------------------------------------- -RTC - Real-Time Clounter --------------------------------------------------------------------------- -*/ - -/* Real-Time Counter */ -typedef struct RTC_struct -{ - register8_t CTRL; /* Control Register */ - register8_t STATUS; /* Status Register */ - register8_t INTCTRL; /* Interrupt Control Register */ - register8_t INTFLAGS; /* Interrupt Flags */ - register8_t TEMP; /* Temporary register */ - register8_t reserved_0x05; - register8_t reserved_0x06; - register8_t reserved_0x07; - _WORDREGISTER(CNT); /* Count Register */ - _WORDREGISTER(PER); /* Period Register */ - _WORDREGISTER(COMP); /* Compare Register */ -} RTC_t; - -/* Prescaler Factor */ -typedef enum RTC_PRESCALER_enum -{ - RTC_PRESCALER_OFF_gc = (0x00<<0), /* RTC Off */ - RTC_PRESCALER_DIV1_gc = (0x01<<0), /* RTC Clock */ - RTC_PRESCALER_DIV2_gc = (0x02<<0), /* RTC Clock / 2 */ - RTC_PRESCALER_DIV8_gc = (0x03<<0), /* RTC Clock / 8 */ - RTC_PRESCALER_DIV16_gc = (0x04<<0), /* RTC Clock / 16 */ - RTC_PRESCALER_DIV64_gc = (0x05<<0), /* RTC Clock / 64 */ - RTC_PRESCALER_DIV256_gc = (0x06<<0), /* RTC Clock / 256 */ - RTC_PRESCALER_DIV1024_gc = (0x07<<0), /* RTC Clock / 1024 */ -} RTC_PRESCALER_t; - -/* Compare Interrupt level */ -typedef enum RTC_COMPINTLVL_enum -{ - RTC_COMPINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ - RTC_COMPINTLVL_LO_gc = (0x01<<2), /* Low Level */ - RTC_COMPINTLVL_MED_gc = (0x02<<2), /* Medium Level */ - RTC_COMPINTLVL_HI_gc = (0x03<<2), /* High Level */ -} RTC_COMPINTLVL_t; - -/* Overflow Interrupt level */ -typedef enum RTC_OVFINTLVL_enum -{ - RTC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - RTC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ - RTC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ - RTC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ -} RTC_OVFINTLVL_t; - - -/* --------------------------------------------------------------------------- -EBI - External Bus Interface --------------------------------------------------------------------------- -*/ - -/* EBI Chip Select Module */ -typedef struct EBI_CS_struct -{ - register8_t CTRLA; /* Chip Select Control Register A */ - register8_t CTRLB; /* Chip Select Control Register B */ - _WORDREGISTER(BASEADDR); /* Chip Select Base Address */ -} EBI_CS_t; - -/* --------------------------------------------------------------------------- -EBI - External Bus Interface --------------------------------------------------------------------------- -*/ - -/* External Bus Interface */ -typedef struct EBI_struct -{ - register8_t CTRL; /* Control */ - register8_t SDRAMCTRLA; /* SDRAM Control Register A */ - register8_t reserved_0x02; - register8_t reserved_0x03; - _WORDREGISTER(REFRESH); /* SDRAM Refresh Period */ - _WORDREGISTER(INITDLY); /* SDRAM Initialization Delay */ - register8_t SDRAMCTRLB; /* SDRAM Control Register B */ - register8_t SDRAMCTRLC; /* SDRAM Control Register C */ - register8_t reserved_0x0A; - register8_t reserved_0x0B; - register8_t reserved_0x0C; - register8_t reserved_0x0D; - register8_t reserved_0x0E; - register8_t reserved_0x0F; - EBI_CS_t CS0; /* Chip Select 0 */ - EBI_CS_t CS1; /* Chip Select 1 */ - EBI_CS_t CS2; /* Chip Select 2 */ - EBI_CS_t CS3; /* Chip Select 3 */ -} EBI_t; - -/* Chip Select adress space */ -typedef enum EBI_CS_ASIZE_enum -{ - EBI_CS_ASIZE_256B_gc = (0x00<<2), /* 256 bytes */ - EBI_CS_ASIZE_512B_gc = (0x01<<2), /* 512 bytes */ - EBI_CS_ASIZE_1KB_gc = (0x02<<2), /* 1K bytes */ - EBI_CS_ASIZE_2KB_gc = (0x03<<2), /* 2K bytes */ - EBI_CS_ASIZE_4KB_gc = (0x04<<2), /* 4K bytes */ - EBI_CS_ASIZE_8KB_gc = (0x05<<2), /* 8K bytes */ - EBI_CS_ASIZE_16KB_gc = (0x06<<2), /* 16K bytes */ - EBI_CS_ASIZE_32KB_gc = (0x07<<2), /* 32K bytes */ - EBI_CS_ASIZE_64KB_gc = (0x08<<2), /* 64K bytes */ - EBI_CS_ASIZE_128KB_gc = (0x09<<2), /* 128K bytes */ - EBI_CS_ASIZE_256KB_gc = (0x0A<<2), /* 256K bytes */ - EBI_CS_ASIZE_512KB_gc = (0x0B<<2), /* 512K bytes */ - EBI_CS_ASIZE_1MB_gc = (0x0C<<2), /* 1M bytes */ - EBI_CS_ASIZE_2MB_gc = (0x0D<<2), /* 2M bytes */ - EBI_CS_ASIZE_4MB_gc = (0x0E<<2), /* 4M bytes */ - EBI_CS_ASIZE_8MB_gc = (0x0F<<2), /* 8M bytes */ - EBI_CS_ASIZE_16M_gc = (0x10<<2), /* 16M bytes */ -} EBI_CS_ASIZE_t; - -/* */ -typedef enum EBI_CS_SRWS_enum -{ - EBI_CS_SRWS_0CLK_gc = (0x00<<0), /* 0 cycles */ - EBI_CS_SRWS_1CLK_gc = (0x01<<0), /* 1 cycle */ - EBI_CS_SRWS_2CLK_gc = (0x02<<0), /* 2 cycles */ - EBI_CS_SRWS_3CLK_gc = (0x03<<0), /* 3 cycles */ - EBI_CS_SRWS_4CLK_gc = (0x04<<0), /* 4 cycles */ - EBI_CS_SRWS_5CLK_gc = (0x05<<0), /* 5 cycle */ - EBI_CS_SRWS_6CLK_gc = (0x06<<0), /* 6 cycles */ - EBI_CS_SRWS_7CLK_gc = (0x07<<0), /* 7 cycles */ -} EBI_CS_SRWS_t; - -/* Chip Select address mode */ -typedef enum EBI_CS_MODE_enum -{ - EBI_CS_MODE_DISABLED_gc = (0x00<<0), /* Chip Select Disabled */ - EBI_CS_MODE_SRAM_gc = (0x01<<0), /* Chip Select in SRAM mode */ - EBI_CS_MODE_LPC_gc = (0x02<<0), /* Chip Select in SRAM LPC mode */ - EBI_CS_MODE_SDRAM_gc = (0x03<<0), /* Chip Select in SDRAM mode */ -} EBI_CS_MODE_t; - -/* Chip Select SDRAM mode */ -typedef enum EBI_CS_SDMODE_enum -{ - EBI_CS_SDMODE_NORMAL_gc = (0x00<<0), /* Normal mode */ - EBI_CS_SDMODE_LOAD_gc = (0x01<<0), /* Load Mode Register command mode */ -} EBI_CS_SDMODE_t; - -/* */ -typedef enum EBI_SDDATAW_enum -{ - EBI_SDDATAW_4BIT_gc = (0x00<<6), /* 4-bit data bus */ - EBI_SDDATAW_8BIT_gc = (0x01<<6), /* 8-bit data bus */ -} EBI_SDDATAW_t; - -/* */ -typedef enum EBI_LPCMODE_enum -{ - EBI_LPCMODE_ALE1_gc = (0x00<<4), /* Data muxed with addr byte 0 */ - EBI_LPCMODE_ALE12_gc = (0x02<<4), /* Data muxed with addr byte 0 and 1 */ -} EBI_LPCMODE_t; - -/* */ -typedef enum EBI_SRMODE_enum -{ - EBI_SRMODE_ALE1_gc = (0x00<<2), /* Addr byte 0 muxed with 1 */ - EBI_SRMODE_ALE2_gc = (0x01<<2), /* Addr byte 0 muxed with 2 */ - EBI_SRMODE_ALE12_gc = (0x02<<2), /* Addr byte 0 muxed with 1 and 2 */ - EBI_SRMODE_NOALE_gc = (0x03<<2), /* No addr muxing */ -} EBI_SRMODE_t; - -/* */ -typedef enum EBI_IFMODE_enum -{ - EBI_IFMODE_DISABLED_gc = (0x00<<0), /* EBI Disabled */ - EBI_IFMODE_3PORT_gc = (0x01<<0), /* 3-port mode */ - EBI_IFMODE_4PORT_gc = (0x02<<0), /* 4-port mode */ - EBI_IFMODE_2PORT_gc = (0x03<<0), /* 2-port mode */ -} EBI_IFMODE_t; - -/* */ -typedef enum EBI_SDCOL_enum -{ - EBI_SDCOL_8BIT_gc = (0x00<<0), /* 8 column bits */ - EBI_SDCOL_9BIT_gc = (0x01<<0), /* 9 column bits */ - EBI_SDCOL_10BIT_gc = (0x02<<0), /* 10 column bits */ - EBI_SDCOL_11BIT_gc = (0x03<<0), /* 11 column bits */ -} EBI_SDCOL_t; - -/* */ -typedef enum EBI_MRDLY_enum -{ - EBI_MRDLY_0CLK_gc = (0x00<<6), /* 0 cycles */ - EBI_MRDLY_1CLK_gc = (0x01<<6), /* 1 cycle */ - EBI_MRDLY_2CLK_gc = (0x02<<6), /* 2 cycles */ - EBI_MRDLY_3CLK_gc = (0x03<<6), /* 3 cycles */ -} EBI_MRDLY_t; - -/* */ -typedef enum EBI_ROWCYCDLY_enum -{ - EBI_ROWCYCDLY_0CLK_gc = (0x00<<3), /* 0 cycles */ - EBI_ROWCYCDLY_1CLK_gc = (0x01<<3), /* 1 cycle */ - EBI_ROWCYCDLY_2CLK_gc = (0x02<<3), /* 2 cycles */ - EBI_ROWCYCDLY_3CLK_gc = (0x03<<3), /* 3 cycles */ - EBI_ROWCYCDLY_4CLK_gc = (0x04<<3), /* 4 cycles */ - EBI_ROWCYCDLY_5CLK_gc = (0x05<<3), /* 5 cycle */ - EBI_ROWCYCDLY_6CLK_gc = (0x06<<3), /* 6 cycles */ - EBI_ROWCYCDLY_7CLK_gc = (0x07<<3), /* 7 cycles */ -} EBI_ROWCYCDLY_t; - -/* */ -typedef enum EBI_RPDLY_enum -{ - EBI_RPDLY_0CLK_gc = (0x00<<0), /* 0 cycles */ - EBI_RPDLY_1CLK_gc = (0x01<<0), /* 1 cycle */ - EBI_RPDLY_2CLK_gc = (0x02<<0), /* 2 cycles */ - EBI_RPDLY_3CLK_gc = (0x03<<0), /* 3 cycles */ - EBI_RPDLY_4CLK_gc = (0x04<<0), /* 4 cycles */ - EBI_RPDLY_5CLK_gc = (0x05<<0), /* 5 cycle */ - EBI_RPDLY_6CLK_gc = (0x06<<0), /* 6 cycles */ - EBI_RPDLY_7CLK_gc = (0x07<<0), /* 7 cycles */ -} EBI_RPDLY_t; - -/* */ -typedef enum EBI_WRDLY_enum -{ - EBI_WRDLY_0CLK_gc = (0x00<<6), /* 0 cycles */ - EBI_WRDLY_1CLK_gc = (0x01<<6), /* 1 cycle */ - EBI_WRDLY_2CLK_gc = (0x02<<6), /* 2 cycles */ - EBI_WRDLY_3CLK_gc = (0x03<<6), /* 3 cycles */ -} EBI_WRDLY_t; - -/* */ -typedef enum EBI_ESRDLY_enum -{ - EBI_ESRDLY_0CLK_gc = (0x00<<3), /* 0 cycles */ - EBI_ESRDLY_1CLK_gc = (0x01<<3), /* 1 cycle */ - EBI_ESRDLY_2CLK_gc = (0x02<<3), /* 2 cycles */ - EBI_ESRDLY_3CLK_gc = (0x03<<3), /* 3 cycles */ - EBI_ESRDLY_4CLK_gc = (0x04<<3), /* 4 cycles */ - EBI_ESRDLY_5CLK_gc = (0x05<<3), /* 5 cycle */ - EBI_ESRDLY_6CLK_gc = (0x06<<3), /* 6 cycles */ - EBI_ESRDLY_7CLK_gc = (0x07<<3), /* 7 cycles */ -} EBI_ESRDLY_t; - -/* */ -typedef enum EBI_ROWCOLDLY_enum -{ - EBI_ROWCOLDLY_0CLK_gc = (0x00<<0), /* 0 cycles */ - EBI_ROWCOLDLY_1CLK_gc = (0x01<<0), /* 1 cycle */ - EBI_ROWCOLDLY_2CLK_gc = (0x02<<0), /* 2 cycles */ - EBI_ROWCOLDLY_3CLK_gc = (0x03<<0), /* 3 cycles */ - EBI_ROWCOLDLY_4CLK_gc = (0x04<<0), /* 4 cycles */ - EBI_ROWCOLDLY_5CLK_gc = (0x05<<0), /* 5 cycle */ - EBI_ROWCOLDLY_6CLK_gc = (0x06<<0), /* 6 cycles */ - EBI_ROWCOLDLY_7CLK_gc = (0x07<<0), /* 7 cycles */ -} EBI_ROWCOLDLY_t; - - -/* --------------------------------------------------------------------------- -TWI - Two-Wire Interface --------------------------------------------------------------------------- -*/ - -/* */ -typedef struct TWI_MASTER_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t CTRLC; /* Control Register C */ - register8_t STATUS; /* Status Register */ - register8_t BAUD; /* Baurd Rate Control Register */ - register8_t ADDR; /* Address Register */ - register8_t DATA; /* Data Register */ -} TWI_MASTER_t; - -/* --------------------------------------------------------------------------- -TWI - Two-Wire Interface --------------------------------------------------------------------------- -*/ - -/* */ -typedef struct TWI_SLAVE_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t STATUS; /* Status Register */ - register8_t ADDR; /* Address Register */ - register8_t DATA; /* Data Register */ - register8_t ADDRMASK; /* Address Mask Register */ -} TWI_SLAVE_t; - -/* --------------------------------------------------------------------------- -TWI - Two-Wire Interface --------------------------------------------------------------------------- -*/ - -/* Two-Wire Interface */ -typedef struct TWI_struct -{ - register8_t CTRL; /* TWI Common Control Register */ - TWI_MASTER_t MASTER; /* TWI master module */ - TWI_SLAVE_t SLAVE; /* TWI slave module */ -} TWI_t; - -/* Master Interrupt Level */ -typedef enum TWI_MASTER_INTLVL_enum -{ - TWI_MASTER_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ - TWI_MASTER_INTLVL_LO_gc = (0x01<<6), /* Low Level */ - TWI_MASTER_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ - TWI_MASTER_INTLVL_HI_gc = (0x03<<6), /* High Level */ -} TWI_MASTER_INTLVL_t; - -/* Inactive Timeout */ -typedef enum TWI_MASTER_TIMEOUT_enum -{ - TWI_MASTER_TIMEOUT_DISABLED_gc = (0x00<<2), /* Bus Timeout Disabled */ - TWI_MASTER_TIMEOUT_50US_gc = (0x01<<2), /* 50 Microseconds */ - TWI_MASTER_TIMEOUT_100US_gc = (0x02<<2), /* 100 Microseconds */ - TWI_MASTER_TIMEOUT_200US_gc = (0x03<<2), /* 200 Microseconds */ -} TWI_MASTER_TIMEOUT_t; - -/* Master Command */ -typedef enum TWI_MASTER_CMD_enum -{ - TWI_MASTER_CMD_NOACT_gc = (0x00<<0), /* No Action */ - TWI_MASTER_CMD_REPSTART_gc = (0x01<<0), /* Issue Repeated Start Condition */ - TWI_MASTER_CMD_RECVTRANS_gc = (0x02<<0), /* Receive or Transmit Data */ - TWI_MASTER_CMD_STOP_gc = (0x03<<0), /* Issue Stop Condition */ -} TWI_MASTER_CMD_t; - -/* Master Bus State */ -typedef enum TWI_MASTER_BUSSTATE_enum -{ - TWI_MASTER_BUSSTATE_UNKNOWN_gc = (0x00<<0), /* Unknown Bus State */ - TWI_MASTER_BUSSTATE_IDLE_gc = (0x01<<0), /* Bus is Idle */ - TWI_MASTER_BUSSTATE_OWNER_gc = (0x02<<0), /* This Module Controls The Bus */ - TWI_MASTER_BUSSTATE_BUSY_gc = (0x03<<0), /* The Bus is Busy */ -} TWI_MASTER_BUSSTATE_t; - -/* Slave Interrupt Level */ -typedef enum TWI_SLAVE_INTLVL_enum -{ - TWI_SLAVE_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ - TWI_SLAVE_INTLVL_LO_gc = (0x01<<6), /* Low Level */ - TWI_SLAVE_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ - TWI_SLAVE_INTLVL_HI_gc = (0x03<<6), /* High Level */ -} TWI_SLAVE_INTLVL_t; - -/* Slave Command */ -typedef enum TWI_SLAVE_CMD_enum -{ - TWI_SLAVE_CMD_NOACT_gc = (0x00<<0), /* No Action */ - TWI_SLAVE_CMD_COMPTRANS_gc = (0x02<<0), /* Used To Complete a Transaction */ - TWI_SLAVE_CMD_RESPONSE_gc = (0x03<<0), /* Used in Response to Address/Data Interrupt */ -} TWI_SLAVE_CMD_t; - - -/* --------------------------------------------------------------------------- -PORT - Port Configuration --------------------------------------------------------------------------- -*/ - -/* I/O port Configuration */ -typedef struct PORTCFG_struct -{ - register8_t MPCMASK; /* Multi-pin Configuration Mask */ - register8_t reserved_0x01; - register8_t VPCTRLA; /* Virtual Port Control Register A */ - register8_t VPCTRLB; /* Virtual Port Control Register B */ - register8_t CLKEVOUT; /* Clock and Event Out Register */ -} PORTCFG_t; - -/* --------------------------------------------------------------------------- -PORT - Port Configuration --------------------------------------------------------------------------- -*/ - -/* Virtual Port */ -typedef struct VPORT_struct -{ - register8_t DIR; /* I/O Port Data Direction */ - register8_t OUT; /* I/O Port Output */ - register8_t IN; /* I/O Port Input */ - register8_t INTFLAGS; /* Interrupt Flag Register */ -} VPORT_t; - -/* --------------------------------------------------------------------------- -PORT - Port Configuration --------------------------------------------------------------------------- -*/ - -/* I/O Ports */ -typedef struct PORT_struct -{ - register8_t DIR; /* I/O Port Data Direction */ - register8_t DIRSET; /* I/O Port Data Direction Set */ - register8_t DIRCLR; /* I/O Port Data Direction Clear */ - register8_t DIRTGL; /* I/O Port Data Direction Toggle */ - register8_t OUT; /* I/O Port Output */ - register8_t OUTSET; /* I/O Port Output Set */ - register8_t OUTCLR; /* I/O Port Output Clear */ - register8_t OUTTGL; /* I/O Port Output Toggle */ - register8_t IN; /* I/O port Input */ - register8_t INTCTRL; /* Interrupt Control Register */ - register8_t INT0MASK; /* Port Interrupt 0 Mask */ - register8_t INT1MASK; /* Port Interrupt 1 Mask */ - register8_t INTFLAGS; /* Interrupt Flag Register */ - register8_t reserved_0x0D; - register8_t reserved_0x0E; - register8_t reserved_0x0F; - register8_t PIN0CTRL; /* Pin 0 Control Register */ - register8_t PIN1CTRL; /* Pin 1 Control Register */ - register8_t PIN2CTRL; /* Pin 2 Control Register */ - register8_t PIN3CTRL; /* Pin 3 Control Register */ - register8_t PIN4CTRL; /* Pin 4 Control Register */ - register8_t PIN5CTRL; /* Pin 5 Control Register */ - register8_t PIN6CTRL; /* Pin 6 Control Register */ - register8_t PIN7CTRL; /* Pin 7 Control Register */ -} PORT_t; - -/* Virtual Port 0 Mapping */ -typedef enum PORTCFG_VP0MAP_enum -{ - PORTCFG_VP0MAP_PORTA_gc = (0x00<<0), /* Mapped To PORTA */ - PORTCFG_VP0MAP_PORTB_gc = (0x01<<0), /* Mapped To PORTB */ - PORTCFG_VP0MAP_PORTC_gc = (0x02<<0), /* Mapped To PORTC */ - PORTCFG_VP0MAP_PORTD_gc = (0x03<<0), /* Mapped To PORTD */ - PORTCFG_VP0MAP_PORTE_gc = (0x04<<0), /* Mapped To PORTE */ - PORTCFG_VP0MAP_PORTF_gc = (0x05<<0), /* Mapped To PORTF */ - PORTCFG_VP0MAP_PORTG_gc = (0x06<<0), /* Mapped To PORTG */ - PORTCFG_VP0MAP_PORTH_gc = (0x07<<0), /* Mapped To PORTH */ - PORTCFG_VP0MAP_PORTJ_gc = (0x08<<0), /* Mapped To PORTJ */ - PORTCFG_VP0MAP_PORTK_gc = (0x09<<0), /* Mapped To PORTK */ - PORTCFG_VP0MAP_PORTL_gc = (0x0A<<0), /* Mapped To PORTL */ - PORTCFG_VP0MAP_PORTM_gc = (0x0B<<0), /* Mapped To PORTM */ - PORTCFG_VP0MAP_PORTN_gc = (0x0C<<0), /* Mapped To PORTN */ - PORTCFG_VP0MAP_PORTP_gc = (0x0D<<0), /* Mapped To PORTP */ - PORTCFG_VP0MAP_PORTQ_gc = (0x0E<<0), /* Mapped To PORTQ */ - PORTCFG_VP0MAP_PORTR_gc = (0x0F<<0), /* Mapped To PORTR */ -} PORTCFG_VP0MAP_t; - -/* Virtual Port 1 Mapping */ -typedef enum PORTCFG_VP1MAP_enum -{ - PORTCFG_VP1MAP_PORTA_gc = (0x00<<4), /* Mapped To PORTA */ - PORTCFG_VP1MAP_PORTB_gc = (0x01<<4), /* Mapped To PORTB */ - PORTCFG_VP1MAP_PORTC_gc = (0x02<<4), /* Mapped To PORTC */ - PORTCFG_VP1MAP_PORTD_gc = (0x03<<4), /* Mapped To PORTD */ - PORTCFG_VP1MAP_PORTE_gc = (0x04<<4), /* Mapped To PORTE */ - PORTCFG_VP1MAP_PORTF_gc = (0x05<<4), /* Mapped To PORTF */ - PORTCFG_VP1MAP_PORTG_gc = (0x06<<4), /* Mapped To PORTG */ - PORTCFG_VP1MAP_PORTH_gc = (0x07<<4), /* Mapped To PORTH */ - PORTCFG_VP1MAP_PORTJ_gc = (0x08<<4), /* Mapped To PORTJ */ - PORTCFG_VP1MAP_PORTK_gc = (0x09<<4), /* Mapped To PORTK */ - PORTCFG_VP1MAP_PORTL_gc = (0x0A<<4), /* Mapped To PORTL */ - PORTCFG_VP1MAP_PORTM_gc = (0x0B<<4), /* Mapped To PORTM */ - PORTCFG_VP1MAP_PORTN_gc = (0x0C<<4), /* Mapped To PORTN */ - PORTCFG_VP1MAP_PORTP_gc = (0x0D<<4), /* Mapped To PORTP */ - PORTCFG_VP1MAP_PORTQ_gc = (0x0E<<4), /* Mapped To PORTQ */ - PORTCFG_VP1MAP_PORTR_gc = (0x0F<<4), /* Mapped To PORTR */ -} PORTCFG_VP1MAP_t; - -/* Virtual Port 2 Mapping */ -typedef enum PORTCFG_VP2MAP_enum -{ - PORTCFG_VP2MAP_PORTA_gc = (0x00<<0), /* Mapped To PORTA */ - PORTCFG_VP2MAP_PORTB_gc = (0x01<<0), /* Mapped To PORTB */ - PORTCFG_VP2MAP_PORTC_gc = (0x02<<0), /* Mapped To PORTC */ - PORTCFG_VP2MAP_PORTD_gc = (0x03<<0), /* Mapped To PORTD */ - PORTCFG_VP2MAP_PORTE_gc = (0x04<<0), /* Mapped To PORTE */ - PORTCFG_VP2MAP_PORTF_gc = (0x05<<0), /* Mapped To PORTF */ - PORTCFG_VP2MAP_PORTG_gc = (0x06<<0), /* Mapped To PORTG */ - PORTCFG_VP2MAP_PORTH_gc = (0x07<<0), /* Mapped To PORTH */ - PORTCFG_VP2MAP_PORTJ_gc = (0x08<<0), /* Mapped To PORTJ */ - PORTCFG_VP2MAP_PORTK_gc = (0x09<<0), /* Mapped To PORTK */ - PORTCFG_VP2MAP_PORTL_gc = (0x0A<<0), /* Mapped To PORTL */ - PORTCFG_VP2MAP_PORTM_gc = (0x0B<<0), /* Mapped To PORTM */ - PORTCFG_VP2MAP_PORTN_gc = (0x0C<<0), /* Mapped To PORTN */ - PORTCFG_VP2MAP_PORTP_gc = (0x0D<<0), /* Mapped To PORTP */ - PORTCFG_VP2MAP_PORTQ_gc = (0x0E<<0), /* Mapped To PORTQ */ - PORTCFG_VP2MAP_PORTR_gc = (0x0F<<0), /* Mapped To PORTR */ -} PORTCFG_VP2MAP_t; - -/* Virtual Port 3 Mapping */ -typedef enum PORTCFG_VP3MAP_enum -{ - PORTCFG_VP3MAP_PORTA_gc = (0x00<<4), /* Mapped To PORTA */ - PORTCFG_VP3MAP_PORTB_gc = (0x01<<4), /* Mapped To PORTB */ - PORTCFG_VP3MAP_PORTC_gc = (0x02<<4), /* Mapped To PORTC */ - PORTCFG_VP3MAP_PORTD_gc = (0x03<<4), /* Mapped To PORTD */ - PORTCFG_VP3MAP_PORTE_gc = (0x04<<4), /* Mapped To PORTE */ - PORTCFG_VP3MAP_PORTF_gc = (0x05<<4), /* Mapped To PORTF */ - PORTCFG_VP3MAP_PORTG_gc = (0x06<<4), /* Mapped To PORTG */ - PORTCFG_VP3MAP_PORTH_gc = (0x07<<4), /* Mapped To PORTH */ - PORTCFG_VP3MAP_PORTJ_gc = (0x08<<4), /* Mapped To PORTJ */ - PORTCFG_VP3MAP_PORTK_gc = (0x09<<4), /* Mapped To PORTK */ - PORTCFG_VP3MAP_PORTL_gc = (0x0A<<4), /* Mapped To PORTL */ - PORTCFG_VP3MAP_PORTM_gc = (0x0B<<4), /* Mapped To PORTM */ - PORTCFG_VP3MAP_PORTN_gc = (0x0C<<4), /* Mapped To PORTN */ - PORTCFG_VP3MAP_PORTP_gc = (0x0D<<4), /* Mapped To PORTP */ - PORTCFG_VP3MAP_PORTQ_gc = (0x0E<<4), /* Mapped To PORTQ */ - PORTCFG_VP3MAP_PORTR_gc = (0x0F<<4), /* Mapped To PORTR */ -} PORTCFG_VP3MAP_t; - -/* Clock Output Port */ -typedef enum PORTCFG_CLKOUT_enum -{ - PORTCFG_CLKOUT_OFF_gc = (0x00<<0), /* Clock Output Disabled */ - PORTCFG_CLKOUT_PC7_gc = (0x01<<0), /* Clock Output on Port C pin 7 */ - PORTCFG_CLKOUT_PD7_gc = (0x02<<0), /* Clock Output on Port D pin 7 */ - PORTCFG_CLKOUT_PE7_gc = (0x03<<0), /* Clock Output on Port E pin 7 */ -} PORTCFG_CLKOUT_t; - -/* Event Output Port */ -typedef enum PORTCFG_EVOUT_enum -{ - PORTCFG_EVOUT_OFF_gc = (0x00<<4), /* Event Output Disabled */ - PORTCFG_EVOUT_PC7_gc = (0x01<<4), /* Event Channel 7 Output on Port C pin 7 */ - PORTCFG_EVOUT_PD7_gc = (0x02<<4), /* Event Channel 7 Output on Port D pin 7 */ - PORTCFG_EVOUT_PE7_gc = (0x03<<4), /* Event Channel 7 Output on Port E pin 7 */ -} PORTCFG_EVOUT_t; - -/* Port Interrupt 0 Level */ -typedef enum PORT_INT0LVL_enum -{ - PORT_INT0LVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - PORT_INT0LVL_LO_gc = (0x01<<0), /* Low Level */ - PORT_INT0LVL_MED_gc = (0x02<<0), /* Medium Level */ - PORT_INT0LVL_HI_gc = (0x03<<0), /* High Level */ -} PORT_INT0LVL_t; - -/* Port Interrupt 1 Level */ -typedef enum PORT_INT1LVL_enum -{ - PORT_INT1LVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ - PORT_INT1LVL_LO_gc = (0x01<<2), /* Low Level */ - PORT_INT1LVL_MED_gc = (0x02<<2), /* Medium Level */ - PORT_INT1LVL_HI_gc = (0x03<<2), /* High Level */ -} PORT_INT1LVL_t; - -/* Output/Pull Configuration */ -typedef enum PORT_OPC_enum -{ - PORT_OPC_TOTEM_gc = (0x00<<3), /* Totempole */ - PORT_OPC_BUSKEEPER_gc = (0x01<<3), /* Totempole w/ Bus keeper on Input and Output */ - PORT_OPC_PULLDOWN_gc = (0x02<<3), /* Totempole w/ Pull-down on Input */ - PORT_OPC_PULLUP_gc = (0x03<<3), /* Totempole w/ Pull-up on Input */ - PORT_OPC_WIREDOR_gc = (0x04<<3), /* Wired OR */ - PORT_OPC_WIREDAND_gc = (0x05<<3), /* Wired AND */ - PORT_OPC_WIREDORPULL_gc = (0x06<<3), /* Wired OR w/ Pull-down */ - PORT_OPC_WIREDANDPULL_gc = (0x07<<3), /* Wired AND w/ Pull-up */ -} PORT_OPC_t; - -/* Input/Sense Configuration */ -typedef enum PORT_ISC_enum -{ - PORT_ISC_BOTHEDGES_gc = (0x00<<0), /* Sense Both Edges */ - PORT_ISC_RISING_gc = (0x01<<0), /* Sense Rising Edge */ - PORT_ISC_FALLING_gc = (0x02<<0), /* Sense Falling Edge */ - PORT_ISC_LEVEL_gc = (0x03<<0), /* Sense Level (Transparent For Events) */ - PORT_ISC_INPUT_DISABLE_gc = (0x07<<0), /* Disable Digital Input Buffer */ -} PORT_ISC_t; - - -/* --------------------------------------------------------------------------- -TC - 16-bit Timer/Counter With PWM --------------------------------------------------------------------------- -*/ - -/* 16-bit Timer/Counter 0 */ -typedef struct TC0_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t CTRLC; /* Control register C */ - register8_t CTRLD; /* Control Register D */ - register8_t CTRLE; /* Control Register E */ - register8_t reserved_0x05; - register8_t INTCTRLA; /* Interrupt Control Register A */ - register8_t INTCTRLB; /* Interrupt Control Register B */ - register8_t CTRLFCLR; /* Control Register F Clear */ - register8_t CTRLFSET; /* Control Register F Set */ - register8_t CTRLGCLR; /* Control Register G Clear */ - register8_t CTRLGSET; /* Control Register G Set */ - register8_t INTFLAGS; /* Interrupt Flag Register */ - register8_t reserved_0x0D; - register8_t reserved_0x0E; - register8_t TEMP; /* Temporary Register For 16-bit Access */ - register8_t reserved_0x10; - register8_t reserved_0x11; - register8_t reserved_0x12; - register8_t reserved_0x13; - register8_t reserved_0x14; - register8_t reserved_0x15; - register8_t reserved_0x16; - register8_t reserved_0x17; - register8_t reserved_0x18; - register8_t reserved_0x19; - register8_t reserved_0x1A; - register8_t reserved_0x1B; - register8_t reserved_0x1C; - register8_t reserved_0x1D; - register8_t reserved_0x1E; - register8_t reserved_0x1F; - _WORDREGISTER(CNT); /* Count */ - register8_t reserved_0x22; - register8_t reserved_0x23; - register8_t reserved_0x24; - register8_t reserved_0x25; - _WORDREGISTER(PER); /* Period */ - _WORDREGISTER(CCA); /* Compare or Capture A */ - _WORDREGISTER(CCB); /* Compare or Capture B */ - _WORDREGISTER(CCC); /* Compare or Capture C */ - _WORDREGISTER(CCD); /* Compare or Capture D */ - register8_t reserved_0x30; - register8_t reserved_0x31; - register8_t reserved_0x32; - register8_t reserved_0x33; - register8_t reserved_0x34; - register8_t reserved_0x35; - _WORDREGISTER(PERBUF); /* Period Buffer */ - _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ - _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ - _WORDREGISTER(CCCBUF); /* Compare Or Capture C Buffer */ - _WORDREGISTER(CCDBUF); /* Compare Or Capture D Buffer */ -} TC0_t; - -/* --------------------------------------------------------------------------- -TC - 16-bit Timer/Counter With PWM --------------------------------------------------------------------------- -*/ - -/* 16-bit Timer/Counter 1 */ -typedef struct TC1_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t CTRLC; /* Control register C */ - register8_t CTRLD; /* Control Register D */ - register8_t CTRLE; /* Control Register E */ - register8_t reserved_0x05; - register8_t INTCTRLA; /* Interrupt Control Register A */ - register8_t INTCTRLB; /* Interrupt Control Register B */ - register8_t CTRLFCLR; /* Control Register F Clear */ - register8_t CTRLFSET; /* Control Register F Set */ - register8_t CTRLGCLR; /* Control Register G Clear */ - register8_t CTRLGSET; /* Control Register G Set */ - register8_t INTFLAGS; /* Interrupt Flag Register */ - register8_t reserved_0x0D; - register8_t reserved_0x0E; - register8_t TEMP; /* Temporary Register For 16-bit Access */ - register8_t reserved_0x10; - register8_t reserved_0x11; - register8_t reserved_0x12; - register8_t reserved_0x13; - register8_t reserved_0x14; - register8_t reserved_0x15; - register8_t reserved_0x16; - register8_t reserved_0x17; - register8_t reserved_0x18; - register8_t reserved_0x19; - register8_t reserved_0x1A; - register8_t reserved_0x1B; - register8_t reserved_0x1C; - register8_t reserved_0x1D; - register8_t reserved_0x1E; - register8_t reserved_0x1F; - _WORDREGISTER(CNT); /* Count */ - register8_t reserved_0x22; - register8_t reserved_0x23; - register8_t reserved_0x24; - register8_t reserved_0x25; - _WORDREGISTER(PER); /* Period */ - _WORDREGISTER(CCA); /* Compare or Capture A */ - _WORDREGISTER(CCB); /* Compare or Capture B */ - register8_t reserved_0x2C; - register8_t reserved_0x2D; - register8_t reserved_0x2E; - register8_t reserved_0x2F; - register8_t reserved_0x30; - register8_t reserved_0x31; - register8_t reserved_0x32; - register8_t reserved_0x33; - register8_t reserved_0x34; - register8_t reserved_0x35; - _WORDREGISTER(PERBUF); /* Period Buffer */ - _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ - _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ -} TC1_t; - -/* --------------------------------------------------------------------------- -TC - 16-bit Timer/Counter With PWM --------------------------------------------------------------------------- -*/ - -/* Advanced Waveform Extension */ -typedef struct AWEX_struct -{ - register8_t CTRL; /* Control Register */ - register8_t reserved_0x01; - register8_t FDEMASK; /* Fault Detection Event Mask */ - register8_t FDCTRL; /* Fault Detection Control Register */ - register8_t STATUS; /* Status Register */ - register8_t reserved_0x05; - register8_t DTBOTH; /* Dead Time Both Sides */ - register8_t DTBOTHBUF; /* Dead Time Both Sides Buffer */ - register8_t DTLS; /* Dead Time Low Side */ - register8_t DTHS; /* Dead Time High Side */ - register8_t DTLSBUF; /* Dead Time Low Side Buffer */ - register8_t DTHSBUF; /* Dead Time High Side Buffer */ - register8_t OUTOVEN; /* Output Override Enable */ -} AWEX_t; - -/* --------------------------------------------------------------------------- -TC - 16-bit Timer/Counter With PWM --------------------------------------------------------------------------- -*/ - -/* High-Resolution Extension */ -typedef struct HIRES_struct -{ - register8_t CTRLA; /* Control Register */ -} HIRES_t; - -/* Clock Selection */ -typedef enum TC_CLKSEL_enum -{ - TC_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */ - TC_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */ - TC_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */ - TC_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */ - TC_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */ - TC_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */ - TC_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */ - TC_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */ - TC_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */ - TC_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */ - TC_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */ - TC_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */ - TC_CLKSEL_EVCH4_gc = (0x0C<<0), /* Event Channel 4 */ - TC_CLKSEL_EVCH5_gc = (0x0D<<0), /* Event Channel 5 */ - TC_CLKSEL_EVCH6_gc = (0x0E<<0), /* Event Channel 6 */ - TC_CLKSEL_EVCH7_gc = (0x0F<<0), /* Event Channel 7 */ -} TC_CLKSEL_t; - -/* Waveform Generation Mode */ -typedef enum TC_WGMODE_enum -{ - TC_WGMODE_NORMAL_gc = (0x00<<0), /* Normal Mode */ - TC_WGMODE_FRQ_gc = (0x01<<0), /* Frequency Generation Mode */ - TC_WGMODE_SS_gc = (0x03<<0), /* Single Slope */ - TC_WGMODE_DS_T_gc = (0x05<<0), /* Dual Slope, Update on TOP */ - TC_WGMODE_DS_TB_gc = (0x06<<0), /* Dual Slope, Update on TOP and BOTTOM */ - TC_WGMODE_DS_B_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */ -} TC_WGMODE_t; - -/* Event Action */ -typedef enum TC_EVACT_enum -{ - TC_EVACT_OFF_gc = (0x00<<5), /* No Event Action */ - TC_EVACT_CAPT_gc = (0x01<<5), /* Input Capture */ - TC_EVACT_UPDOWN_gc = (0x02<<5), /* Externally Controlled Up/Down Count */ - TC_EVACT_QDEC_gc = (0x03<<5), /* Quadrature Decode */ - TC_EVACT_RESTART_gc = (0x04<<5), /* Restart */ - TC_EVACT_FRQ_gc = (0x05<<5), /* Frequency Capture */ - TC_EVACT_FRW_gc = (0x05<<5), /* Frequency Capture (typo in earlier header file) */ - TC_EVACT_PW_gc = (0x06<<5), /* Pulse-width Capture */ -} TC_EVACT_t; - -/* Event Selection */ -typedef enum TC_EVSEL_enum -{ - TC_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ - TC_EVSEL_CH0_gc = (0x08<<0), /* Event Channel 0 */ - TC_EVSEL_CH1_gc = (0x09<<0), /* Event Channel 1 */ - TC_EVSEL_CH2_gc = (0x0A<<0), /* Event Channel 2 */ - TC_EVSEL_CH3_gc = (0x0B<<0), /* Event Channel 3 */ - TC_EVSEL_CH4_gc = (0x0C<<0), /* Event Channel 4 */ - TC_EVSEL_CH5_gc = (0x0D<<0), /* Event Channel 5 */ - TC_EVSEL_CH6_gc = (0x0E<<0), /* Event Channel 6 */ - TC_EVSEL_CH7_gc = (0x0F<<0), /* Event Channel 7 */ -} TC_EVSEL_t; - -/* Error Interrupt Level */ -typedef enum TC_ERRINTLVL_enum -{ - TC_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ - TC_ERRINTLVL_LO_gc = (0x01<<2), /* Low Level */ - TC_ERRINTLVL_MED_gc = (0x02<<2), /* Medium Level */ - TC_ERRINTLVL_HI_gc = (0x03<<2), /* High Level */ -} TC_ERRINTLVL_t; - -/* Overflow Interrupt Level */ -typedef enum TC_OVFINTLVL_enum -{ - TC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - TC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ - TC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ - TC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ -} TC_OVFINTLVL_t; - -/* Compare or Capture D Interrupt Level */ -typedef enum TC_CCDINTLVL_enum -{ - TC_CCDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ - TC_CCDINTLVL_LO_gc = (0x01<<6), /* Low Level */ - TC_CCDINTLVL_MED_gc = (0x02<<6), /* Medium Level */ - TC_CCDINTLVL_HI_gc = (0x03<<6), /* High Level */ -} TC_CCDINTLVL_t; - -/* Compare or Capture C Interrupt Level */ -typedef enum TC_CCCINTLVL_enum -{ - TC_CCCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ - TC_CCCINTLVL_LO_gc = (0x01<<4), /* Low Level */ - TC_CCCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ - TC_CCCINTLVL_HI_gc = (0x03<<4), /* High Level */ -} TC_CCCINTLVL_t; - -/* Compare or Capture B Interrupt Level */ -typedef enum TC_CCBINTLVL_enum -{ - TC_CCBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ - TC_CCBINTLVL_LO_gc = (0x01<<2), /* Low Level */ - TC_CCBINTLVL_MED_gc = (0x02<<2), /* Medium Level */ - TC_CCBINTLVL_HI_gc = (0x03<<2), /* High Level */ -} TC_CCBINTLVL_t; - -/* Compare or Capture A Interrupt Level */ -typedef enum TC_CCAINTLVL_enum -{ - TC_CCAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - TC_CCAINTLVL_LO_gc = (0x01<<0), /* Low Level */ - TC_CCAINTLVL_MED_gc = (0x02<<0), /* Medium Level */ - TC_CCAINTLVL_HI_gc = (0x03<<0), /* High Level */ -} TC_CCAINTLVL_t; - -/* Timer/Counter Command */ -typedef enum TC_CMD_enum -{ - TC_CMD_NONE_gc = (0x00<<2), /* No Command */ - TC_CMD_UPDATE_gc = (0x01<<2), /* Force Update */ - TC_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ - TC_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ -} TC_CMD_t; - -/* Fault Detect Action */ -typedef enum AWEX_FDACT_enum -{ - AWEX_FDACT_NONE_gc = (0x00<<0), /* No Fault Protection */ - AWEX_FDACT_CLEAROE_gc = (0x01<<0), /* Clear Output Enable Bits */ - AWEX_FDACT_CLEARDIR_gc = (0x03<<0), /* Clear I/O Port Direction Bits */ -} AWEX_FDACT_t; - -/* High Resolution Enable */ -typedef enum HIRES_HREN_enum -{ - HIRES_HREN_NONE_gc = (0x00<<0), /* No Fault Protection */ - HIRES_HREN_TC0_gc = (0x01<<0), /* Enable High Resolution on Timer/Counter 0 */ - HIRES_HREN_TC1_gc = (0x02<<0), /* Enable High Resolution on Timer/Counter 1 */ - HIRES_HREN_BOTH_gc = (0x03<<0), /* Enable High Resolution both Timer/Counters */ -} HIRES_HREN_t; - - -/* --------------------------------------------------------------------------- -USART - Universal Asynchronous Receiver-Transmitter --------------------------------------------------------------------------- -*/ - -/* Universal Synchronous/Asynchronous Receiver/Transmitter */ -typedef struct USART_struct -{ - register8_t DATA; /* Data Register */ - register8_t STATUS; /* Status Register */ - register8_t reserved_0x02; - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t CTRLC; /* Control Register C */ - register8_t BAUDCTRLA; /* Baud Rate Control Register A */ - register8_t BAUDCTRLB; /* Baud Rate Control Register B */ -} USART_t; - -/* Receive Complete Interrupt level */ -typedef enum USART_RXCINTLVL_enum -{ - USART_RXCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ - USART_RXCINTLVL_LO_gc = (0x01<<4), /* Low Level */ - USART_RXCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ - USART_RXCINTLVL_HI_gc = (0x03<<4), /* High Level */ -} USART_RXCINTLVL_t; - -/* Transmit Complete Interrupt level */ -typedef enum USART_TXCINTLVL_enum -{ - USART_TXCINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ - USART_TXCINTLVL_LO_gc = (0x01<<2), /* Low Level */ - USART_TXCINTLVL_MED_gc = (0x02<<2), /* Medium Level */ - USART_TXCINTLVL_HI_gc = (0x03<<2), /* High Level */ -} USART_TXCINTLVL_t; - -/* Data Register Empty Interrupt level */ -typedef enum USART_DREINTLVL_enum -{ - USART_DREINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - USART_DREINTLVL_LO_gc = (0x01<<0), /* Low Level */ - USART_DREINTLVL_MED_gc = (0x02<<0), /* Medium Level */ - USART_DREINTLVL_HI_gc = (0x03<<0), /* High Level */ -} USART_DREINTLVL_t; - -/* Character Size */ -typedef enum USART_CHSIZE_enum -{ - USART_CHSIZE_5BIT_gc = (0x00<<0), /* Character size: 5 bit */ - USART_CHSIZE_6BIT_gc = (0x01<<0), /* Character size: 6 bit */ - USART_CHSIZE_7BIT_gc = (0x02<<0), /* Character size: 7 bit */ - USART_CHSIZE_8BIT_gc = (0x03<<0), /* Character size: 8 bit */ - USART_CHSIZE_9BIT_gc = (0x07<<0), /* Character size: 9 bit */ -} USART_CHSIZE_t; - -/* Communication Mode */ -typedef enum USART_CMODE_enum -{ - USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6), /* Asynchronous Mode */ - USART_CMODE_SYNCHRONOUS_gc = (0x01<<6), /* Synchronous Mode */ - USART_CMODE_IRDA_gc = (0x02<<6), /* IrDA Mode */ - USART_CMODE_MSPI_gc = (0x03<<6), /* Master SPI Mode */ -} USART_CMODE_t; - -/* Parity Mode */ -typedef enum USART_PMODE_enum -{ - USART_PMODE_DISABLED_gc = (0x00<<4), /* No Parity */ - USART_PMODE_EVEN_gc = (0x02<<4), /* Even Parity */ - USART_PMODE_ODD_gc = (0x03<<4), /* Odd Parity */ -} USART_PMODE_t; - - -/* --------------------------------------------------------------------------- -SPI - Serial Peripheral Interface --------------------------------------------------------------------------- -*/ - -/* Serial Peripheral Interface */ -typedef struct SPI_struct -{ - register8_t CTRL; /* Control Register */ - register8_t INTCTRL; /* Interrupt Control Register */ - register8_t STATUS; /* Status Register */ - register8_t DATA; /* Data Register */ -} SPI_t; - -/* SPI Mode */ -typedef enum SPI_MODE_enum -{ - SPI_MODE_0_gc = (0x00<<2), /* SPI Mode 0 */ - SPI_MODE_1_gc = (0x01<<2), /* SPI Mode 1 */ - SPI_MODE_2_gc = (0x02<<2), /* SPI Mode 2 */ - SPI_MODE_3_gc = (0x03<<2), /* SPI Mode 3 */ -} SPI_MODE_t; - -/* Prescaler setting */ -typedef enum SPI_PRESCALER_enum -{ - SPI_PRESCALER_DIV4_gc = (0x00<<0), /* System Clock / 4 */ - SPI_PRESCALER_DIV16_gc = (0x01<<0), /* System Clock / 16 */ - SPI_PRESCALER_DIV64_gc = (0x02<<0), /* System Clock / 64 */ - SPI_PRESCALER_DIV128_gc = (0x03<<0), /* System Clock / 128 */ -} SPI_PRESCALER_t; - -/* Interrupt level */ -typedef enum SPI_INTLVL_enum -{ - SPI_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - SPI_INTLVL_LO_gc = (0x01<<0), /* Low Level */ - SPI_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ - SPI_INTLVL_HI_gc = (0x03<<0), /* High Level */ -} SPI_INTLVL_t; - - -/* --------------------------------------------------------------------------- -IRCOM - IR Communication Module --------------------------------------------------------------------------- -*/ - -/* IR Communication Module */ -typedef struct IRCOM_struct -{ - register8_t CTRL; /* Control Register */ - register8_t TXPLCTRL; /* IrDA Transmitter Pulse Length Control Register */ - register8_t RXPLCTRL; /* IrDA Receiver Pulse Length Control Register */ -} IRCOM_t; - -/* Event channel selection */ -typedef enum IRDA_EVSEL_enum -{ - IRDA_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ - IRDA_EVSEL_0_gc = (0x08<<0), /* Event Channel 0 */ - IRDA_EVSEL_1_gc = (0x09<<0), /* Event Channel 1 */ - IRDA_EVSEL_2_gc = (0x0A<<0), /* Event Channel 2 */ - IRDA_EVSEL_3_gc = (0x0B<<0), /* Event Channel 3 */ - IRDA_EVSEL_4_gc = (0x0C<<0), /* Event Channel 4 */ - IRDA_EVSEL_5_gc = (0x0D<<0), /* Event Channel 5 */ - IRDA_EVSEL_6_gc = (0x0E<<0), /* Event Channel 6 */ - IRDA_EVSEL_7_gc = (0x0F<<0), /* Event Channel 7 */ -} IRDA_EVSEL_t; - - -/* --------------------------------------------------------------------------- -AES - AES Module --------------------------------------------------------------------------- -*/ - -/* AES Module */ -typedef struct AES_struct -{ - register8_t CTRL; /* AES Control Register */ - register8_t STATUS; /* AES Status Register */ - register8_t STATE; /* AES State Register */ - register8_t KEY; /* AES Key Register */ - register8_t INTCTRL; /* AES Interrupt Control Register */ -} AES_t; - -/* Interrupt level */ -typedef enum AES_INTLVL_enum -{ - AES_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - AES_INTLVL_LO_gc = (0x01<<0), /* Low Level */ - AES_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ - AES_INTLVL_HI_gc = (0x03<<0), /* High Level */ -} AES_INTLVL_t; - - - -/* -========================================================================== -IO Module Instances. Mapped to memory. -========================================================================== -*/ - -#define VPORT0 (*(VPORT_t *) 0x0010) /* Virtual Port 0 */ -#define VPORT1 (*(VPORT_t *) 0x0014) /* Virtual Port 1 */ -#define VPORT2 (*(VPORT_t *) 0x0018) /* Virtual Port 2 */ -#define VPORT3 (*(VPORT_t *) 0x001C) /* Virtual Port 3 */ -#define OCD (*(OCD_t *) 0x002E) /* On-Chip Debug System */ -#define CLK (*(CLK_t *) 0x0040) /* Clock System */ -#define SLEEP (*(SLEEP_t *) 0x0048) /* Sleep Controller */ -#define OSC (*(OSC_t *) 0x0050) /* Oscillator Control */ -#define DFLLRC32M (*(DFLL_t *) 0x0060) /* DFLL for 32MHz RC Oscillator */ -#define DFLLRC2M (*(DFLL_t *) 0x0068) /* DFLL for 2MHz RC Oscillator */ -#define PR (*(PR_t *) 0x0070) /* Power Reduction */ -#define RST (*(RST_t *) 0x0078) /* Reset Controller */ -#define WDT (*(WDT_t *) 0x0080) /* Watch-Dog Timer */ -#define MCU (*(MCU_t *) 0x0090) /* MCU Control */ -#define PMIC (*(PMIC_t *) 0x00A0) /* Programmable Interrupt Controller */ -#define PORTCFG (*(PORTCFG_t *) 0x00B0) /* Port Configuration */ -#define AES (*(AES_t *) 0x00C0) /* AES Crypto Module */ -#define DMA (*(DMA_t *) 0x0100) /* DMA Controller */ -#define EVSYS (*(EVSYS_t *) 0x0180) /* Event System */ -#define NVM (*(NVM_t *) 0x01C0) /* Non Volatile Memory Controller */ -#define ADCA (*(ADC_t *) 0x0200) /* Analog to Digital Converter A */ -#define ADCB (*(ADC_t *) 0x0240) /* Analog to Digital Converter B */ -#define DACB (*(DAC_t *) 0x0320) /* Digital to Analog Converter B */ -#define ACA (*(AC_t *) 0x0380) /* Analog Comparator A */ -#define ACB (*(AC_t *) 0x0390) /* Analog Comparator B */ -#define RTC (*(RTC_t *) 0x0400) /* Real-Time Counter */ -#define TWIC (*(TWI_t *) 0x0480) /* Two-Wire Interface C */ -#define TWIE (*(TWI_t *) 0x04A0) /* Two-Wire Interface E */ -#define PORTA (*(PORT_t *) 0x0600) /* Port A */ -#define PORTB (*(PORT_t *) 0x0620) /* Port B */ -#define PORTC (*(PORT_t *) 0x0640) /* Port C */ -#define PORTD (*(PORT_t *) 0x0660) /* Port D */ -#define PORTE (*(PORT_t *) 0x0680) /* Port E */ -#define PORTF (*(PORT_t *) 0x06A0) /* Port F */ -#define PORTR (*(PORT_t *) 0x07E0) /* Port R */ -#define TCC0 (*(TC0_t *) 0x0800) /* Timer/Counter C0 */ -#define TCC1 (*(TC1_t *) 0x0840) /* Timer/Counter C1 */ -#define AWEXC (*(AWEX_t *) 0x0880) /* Advanced Waveform Extension C */ -#define HIRESC (*(HIRES_t *) 0x0890) /* High-Resolution Extension C */ -#define USARTC0 (*(USART_t *) 0x08A0) /* Universal Asynchronous Receiver-Transmitter C0 */ -#define USARTC1 (*(USART_t *) 0x08B0) /* Universal Asynchronous Receiver-Transmitter C1 */ -#define SPIC (*(SPI_t *) 0x08C0) /* Serial Peripheral Interface C */ -#define IRCOM (*(IRCOM_t *) 0x08F8) /* IR Communication Module */ -#define TCD0 (*(TC0_t *) 0x0900) /* Timer/Counter D0 */ -#define TCD1 (*(TC1_t *) 0x0940) /* Timer/Counter D1 */ -#define HIRESD (*(HIRES_t *) 0x0990) /* High-Resolution Extension D */ -#define USARTD0 (*(USART_t *) 0x09A0) /* Universal Asynchronous Receiver-Transmitter D0 */ -#define USARTD1 (*(USART_t *) 0x09B0) /* Universal Asynchronous Receiver-Transmitter D1 */ -#define SPID (*(SPI_t *) 0x09C0) /* Serial Peripheral Interface D */ -#define TCE0 (*(TC0_t *) 0x0A00) /* Timer/Counter E0 */ -#define TCE1 (*(TC1_t *) 0x0A40) /* Timer/Counter E1 */ -#define AWEXE (*(AWEX_t *) 0x0A80) /* Advanced Waveform Extension E */ -#define HIRESE (*(HIRES_t *) 0x0A90) /* High-Resolution Extension E */ -#define USARTE0 (*(USART_t *) 0x0AA0) /* Universal Asynchronous Receiver-Transmitter E0 */ -#define USARTE1 (*(USART_t *) 0x0AB0) /* Universal Asynchronous Receiver-Transmitter E1 */ -#define SPIE (*(SPI_t *) 0x0AC0) /* Serial Peripheral Interface E */ -#define TCF0 (*(TC0_t *) 0x0B00) /* Timer/Counter F0 */ -#define HIRESF (*(HIRES_t *) 0x0B90) /* High-Resolution Extension F */ -#define USARTF0 (*(USART_t *) 0x0BA0) /* Universal Asynchronous Receiver-Transmitter F0 */ -#define USARTF1 (*(USART_t *) 0x0BB0) /* Universal Asynchronous Receiver-Transmitter F1 */ -#define SPIF (*(SPI_t *) 0x0BC0) /* Serial Peripheral Interface F */ - - -#endif /* !defined (__ASSEMBLER__) */ - - -/* ========== Flattened fully qualified IO register names ========== */ - -/* GPIO - General Purpose IO Registers */ -#define GPIO_GPIOR0 _SFR_MEM8(0x0000) -#define GPIO_GPIOR1 _SFR_MEM8(0x0001) -#define GPIO_GPIOR2 _SFR_MEM8(0x0002) -#define GPIO_GPIOR3 _SFR_MEM8(0x0003) -#define GPIO_GPIOR4 _SFR_MEM8(0x0004) -#define GPIO_GPIOR5 _SFR_MEM8(0x0005) -#define GPIO_GPIOR6 _SFR_MEM8(0x0006) -#define GPIO_GPIOR7 _SFR_MEM8(0x0007) -#define GPIO_GPIOR8 _SFR_MEM8(0x0008) -#define GPIO_GPIOR9 _SFR_MEM8(0x0009) -#define GPIO_GPIORA _SFR_MEM8(0x000A) -#define GPIO_GPIORB _SFR_MEM8(0x000B) -#define GPIO_GPIORC _SFR_MEM8(0x000C) -#define GPIO_GPIORD _SFR_MEM8(0x000D) -#define GPIO_GPIORE _SFR_MEM8(0x000E) -#define GPIO_GPIORF _SFR_MEM8(0x000F) - -/* Deprecated */ -#define GPIO_GPIO0 _SFR_MEM8(0x0000) -#define GPIO_GPIO1 _SFR_MEM8(0x0001) -#define GPIO_GPIO2 _SFR_MEM8(0x0002) -#define GPIO_GPIO3 _SFR_MEM8(0x0003) -#define GPIO_GPIO4 _SFR_MEM8(0x0004) -#define GPIO_GPIO5 _SFR_MEM8(0x0005) -#define GPIO_GPIO6 _SFR_MEM8(0x0006) -#define GPIO_GPIO7 _SFR_MEM8(0x0007) -#define GPIO_GPIO8 _SFR_MEM8(0x0008) -#define GPIO_GPIO9 _SFR_MEM8(0x0009) -#define GPIO_GPIOA _SFR_MEM8(0x000A) -#define GPIO_GPIOB _SFR_MEM8(0x000B) -#define GPIO_GPIOC _SFR_MEM8(0x000C) -#define GPIO_GPIOD _SFR_MEM8(0x000D) -#define GPIO_GPIOE _SFR_MEM8(0x000E) -#define GPIO_GPIOF _SFR_MEM8(0x000F) - -/* VPORT0 - Virtual Port 0 */ -#define VPORT0_DIR _SFR_MEM8(0x0010) -#define VPORT0_OUT _SFR_MEM8(0x0011) -#define VPORT0_IN _SFR_MEM8(0x0012) -#define VPORT0_INTFLAGS _SFR_MEM8(0x0013) - -/* VPORT1 - Virtual Port 1 */ -#define VPORT1_DIR _SFR_MEM8(0x0014) -#define VPORT1_OUT _SFR_MEM8(0x0015) -#define VPORT1_IN _SFR_MEM8(0x0016) -#define VPORT1_INTFLAGS _SFR_MEM8(0x0017) - -/* VPORT2 - Virtual Port 2 */ -#define VPORT2_DIR _SFR_MEM8(0x0018) -#define VPORT2_OUT _SFR_MEM8(0x0019) -#define VPORT2_IN _SFR_MEM8(0x001A) -#define VPORT2_INTFLAGS _SFR_MEM8(0x001B) - -/* VPORT3 - Virtual Port 3 */ -#define VPORT3_DIR _SFR_MEM8(0x001C) -#define VPORT3_OUT _SFR_MEM8(0x001D) -#define VPORT3_IN _SFR_MEM8(0x001E) -#define VPORT3_INTFLAGS _SFR_MEM8(0x001F) - -/* OCD - On-Chip Debug System */ -#define OCD_OCDR0 _SFR_MEM8(0x002E) -#define OCD_OCDR1 _SFR_MEM8(0x002F) - -/* CPU - CPU Registers */ -#define CPU_CCP _SFR_MEM8(0x0034) -#define CPU_RAMPD _SFR_MEM8(0x0038) -#define CPU_RAMPX _SFR_MEM8(0x0039) -#define CPU_RAMPY _SFR_MEM8(0x003A) -#define CPU_RAMPZ _SFR_MEM8(0x003B) -#define CPU_EIND _SFR_MEM8(0x003C) -#define CPU_SPL _SFR_MEM8(0x003D) -#define CPU_SPH _SFR_MEM8(0x003E) -#define CPU_SREG _SFR_MEM8(0x003F) - -/* CLK - Clock System */ -#define CLK_CTRL _SFR_MEM8(0x0040) -#define CLK_PSCTRL _SFR_MEM8(0x0041) -#define CLK_LOCK _SFR_MEM8(0x0042) -#define CLK_RTCCTRL _SFR_MEM8(0x0043) - -/* SLEEP - Sleep Controller */ -#define SLEEP_CTRL _SFR_MEM8(0x0048) - -/* OSC - Oscillator Control */ -#define OSC_CTRL _SFR_MEM8(0x0050) -#define OSC_STATUS _SFR_MEM8(0x0051) -#define OSC_XOSCCTRL _SFR_MEM8(0x0052) -#define OSC_XOSCFAIL _SFR_MEM8(0x0053) -#define OSC_RC32KCAL _SFR_MEM8(0x0054) -#define OSC_PLLCTRL _SFR_MEM8(0x0055) -#define OSC_DFLLCTRL _SFR_MEM8(0x0056) - -/* DFLLRC32M - DFLL for 32MHz RC Oscillator */ -#define DFLLRC32M_CTRL _SFR_MEM8(0x0060) -#define DFLLRC32M_CALA _SFR_MEM8(0x0062) -#define DFLLRC32M_CALB _SFR_MEM8(0x0063) -#define DFLLRC32M_COMP0 _SFR_MEM8(0x0064) -#define DFLLRC32M_COMP1 _SFR_MEM8(0x0065) -#define DFLLRC32M_COMP2 _SFR_MEM8(0x0066) - -/* DFLLRC2M - DFLL for 2MHz RC Oscillator */ -#define DFLLRC2M_CTRL _SFR_MEM8(0x0068) -#define DFLLRC2M_CALA _SFR_MEM8(0x006A) -#define DFLLRC2M_CALB _SFR_MEM8(0x006B) -#define DFLLRC2M_COMP0 _SFR_MEM8(0x006C) -#define DFLLRC2M_COMP1 _SFR_MEM8(0x006D) -#define DFLLRC2M_COMP2 _SFR_MEM8(0x006E) - -/* PR - Power Reduction */ -#define PR_PRGEN _SFR_MEM8(0x0070) -#define PR_PRPA _SFR_MEM8(0x0071) -#define PR_PRPB _SFR_MEM8(0x0072) -#define PR_PRPC _SFR_MEM8(0x0073) -#define PR_PRPD _SFR_MEM8(0x0074) -#define PR_PRPE _SFR_MEM8(0x0075) -#define PR_PRPF _SFR_MEM8(0x0076) - -/* RST - Reset Controller */ -#define RST_STATUS _SFR_MEM8(0x0078) -#define RST_CTRL _SFR_MEM8(0x0079) - -/* WDT - Watch-Dog Timer */ -#define WDT_CTRL _SFR_MEM8(0x0080) -#define WDT_WINCTRL _SFR_MEM8(0x0081) -#define WDT_STATUS _SFR_MEM8(0x0082) - -/* MCU - MCU Control */ -#define MCU_DEVID0 _SFR_MEM8(0x0090) -#define MCU_DEVID1 _SFR_MEM8(0x0091) -#define MCU_DEVID2 _SFR_MEM8(0x0092) -#define MCU_REVID _SFR_MEM8(0x0093) -#define MCU_JTAGUID _SFR_MEM8(0x0094) -#define MCU_MCUCR _SFR_MEM8(0x0096) -#define MCU_EVSYSLOCK _SFR_MEM8(0x0098) -#define MCU_AWEXLOCK _SFR_MEM8(0x0099) - -/* PMIC - Programmable Interrupt Controller */ -#define PMIC_STATUS _SFR_MEM8(0x00A0) -#define PMIC_INTPRI _SFR_MEM8(0x00A1) -#define PMIC_CTRL _SFR_MEM8(0x00A2) - -/* PORTCFG - Port Configuration */ -#define PORTCFG_MPCMASK _SFR_MEM8(0x00B0) -#define PORTCFG_VPCTRLA _SFR_MEM8(0x00B2) -#define PORTCFG_VPCTRLB _SFR_MEM8(0x00B3) -#define PORTCFG_CLKEVOUT _SFR_MEM8(0x00B4) - -/* AES - AES Crypto Module */ -#define AES_CTRL _SFR_MEM8(0x00C0) -#define AES_STATUS _SFR_MEM8(0x00C1) -#define AES_STATE _SFR_MEM8(0x00C2) -#define AES_KEY _SFR_MEM8(0x00C3) -#define AES_INTCTRL _SFR_MEM8(0x00C4) - -/* DMA - DMA Controller */ -#define DMA_CTRL _SFR_MEM8(0x0100) -#define DMA_INTFLAGS _SFR_MEM8(0x0103) -#define DMA_STATUS _SFR_MEM8(0x0104) -#define DMA_TEMP _SFR_MEM16(0x0106) -#define DMA_CH0_CTRLA _SFR_MEM8(0x0110) -#define DMA_CH0_CTRLB _SFR_MEM8(0x0111) -#define DMA_CH0_ADDRCTRL _SFR_MEM8(0x0112) -#define DMA_CH0_TRIGSRC _SFR_MEM8(0x0113) -#define DMA_CH0_TRFCNT _SFR_MEM16(0x0114) -#define DMA_CH0_REPCNT _SFR_MEM8(0x0116) -#define DMA_CH0_SRCADDR0 _SFR_MEM8(0x0118) -#define DMA_CH0_SRCADDR1 _SFR_MEM8(0x0119) -#define DMA_CH0_SRCADDR2 _SFR_MEM8(0x011A) -#define DMA_CH0_DESTADDR0 _SFR_MEM8(0x011C) -#define DMA_CH0_DESTADDR1 _SFR_MEM8(0x011D) -#define DMA_CH0_DESTADDR2 _SFR_MEM8(0x011E) -#define DMA_CH1_CTRLA _SFR_MEM8(0x0120) -#define DMA_CH1_CTRLB _SFR_MEM8(0x0121) -#define DMA_CH1_ADDRCTRL _SFR_MEM8(0x0122) -#define DMA_CH1_TRIGSRC _SFR_MEM8(0x0123) -#define DMA_CH1_TRFCNT _SFR_MEM16(0x0124) -#define DMA_CH1_REPCNT _SFR_MEM8(0x0126) -#define DMA_CH1_SRCADDR0 _SFR_MEM8(0x0128) -#define DMA_CH1_SRCADDR1 _SFR_MEM8(0x0129) -#define DMA_CH1_SRCADDR2 _SFR_MEM8(0x012A) -#define DMA_CH1_DESTADDR0 _SFR_MEM8(0x012C) -#define DMA_CH1_DESTADDR1 _SFR_MEM8(0x012D) -#define DMA_CH1_DESTADDR2 _SFR_MEM8(0x012E) -#define DMA_CH2_CTRLA _SFR_MEM8(0x0130) -#define DMA_CH2_CTRLB _SFR_MEM8(0x0131) -#define DMA_CH2_ADDRCTRL _SFR_MEM8(0x0132) -#define DMA_CH2_TRIGSRC _SFR_MEM8(0x0133) -#define DMA_CH2_TRFCNT _SFR_MEM16(0x0134) -#define DMA_CH2_REPCNT _SFR_MEM8(0x0136) -#define DMA_CH2_SRCADDR0 _SFR_MEM8(0x0138) -#define DMA_CH2_SRCADDR1 _SFR_MEM8(0x0139) -#define DMA_CH2_SRCADDR2 _SFR_MEM8(0x013A) -#define DMA_CH2_DESTADDR0 _SFR_MEM8(0x013C) -#define DMA_CH2_DESTADDR1 _SFR_MEM8(0x013D) -#define DMA_CH2_DESTADDR2 _SFR_MEM8(0x013E) -#define DMA_CH3_CTRLA _SFR_MEM8(0x0140) -#define DMA_CH3_CTRLB _SFR_MEM8(0x0141) -#define DMA_CH3_ADDRCTRL _SFR_MEM8(0x0142) -#define DMA_CH3_TRIGSRC _SFR_MEM8(0x0143) -#define DMA_CH3_TRFCNT _SFR_MEM16(0x0144) -#define DMA_CH3_REPCNT _SFR_MEM8(0x0146) -#define DMA_CH3_SRCADDR0 _SFR_MEM8(0x0148) -#define DMA_CH3_SRCADDR1 _SFR_MEM8(0x0149) -#define DMA_CH3_SRCADDR2 _SFR_MEM8(0x014A) -#define DMA_CH3_DESTADDR0 _SFR_MEM8(0x014C) -#define DMA_CH3_DESTADDR1 _SFR_MEM8(0x014D) -#define DMA_CH3_DESTADDR2 _SFR_MEM8(0x014E) - -/* EVSYS - Event System */ -#define EVSYS_CH0MUX _SFR_MEM8(0x0180) -#define EVSYS_CH1MUX _SFR_MEM8(0x0181) -#define EVSYS_CH2MUX _SFR_MEM8(0x0182) -#define EVSYS_CH3MUX _SFR_MEM8(0x0183) -#define EVSYS_CH4MUX _SFR_MEM8(0x0184) -#define EVSYS_CH5MUX _SFR_MEM8(0x0185) -#define EVSYS_CH6MUX _SFR_MEM8(0x0186) -#define EVSYS_CH7MUX _SFR_MEM8(0x0187) -#define EVSYS_CH0CTRL _SFR_MEM8(0x0188) -#define EVSYS_CH1CTRL _SFR_MEM8(0x0189) -#define EVSYS_CH2CTRL _SFR_MEM8(0x018A) -#define EVSYS_CH3CTRL _SFR_MEM8(0x018B) -#define EVSYS_CH4CTRL _SFR_MEM8(0x018C) -#define EVSYS_CH5CTRL _SFR_MEM8(0x018D) -#define EVSYS_CH6CTRL _SFR_MEM8(0x018E) -#define EVSYS_CH7CTRL _SFR_MEM8(0x018F) -#define EVSYS_STROBE _SFR_MEM8(0x0190) -#define EVSYS_DATA _SFR_MEM8(0x0191) - -/* NVM - Non Volatile Memory Controller */ -#define NVM_ADDR0 _SFR_MEM8(0x01C0) -#define NVM_ADDR1 _SFR_MEM8(0x01C1) -#define NVM_ADDR2 _SFR_MEM8(0x01C2) -#define NVM_DATA0 _SFR_MEM8(0x01C4) -#define NVM_DATA1 _SFR_MEM8(0x01C5) -#define NVM_DATA2 _SFR_MEM8(0x01C6) -#define NVM_CMD _SFR_MEM8(0x01CA) -#define NVM_CTRLA _SFR_MEM8(0x01CB) -#define NVM_CTRLB _SFR_MEM8(0x01CC) -#define NVM_INTCTRL _SFR_MEM8(0x01CD) -#define NVM_STATUS _SFR_MEM8(0x01CF) -#define NVM_LOCKBITS _SFR_MEM8(0x01D0) - -/* ADCA - Analog to Digital Converter A */ -#define ADCA_CTRLA _SFR_MEM8(0x0200) -#define ADCA_CTRLB _SFR_MEM8(0x0201) -#define ADCA_REFCTRL _SFR_MEM8(0x0202) -#define ADCA_EVCTRL _SFR_MEM8(0x0203) -#define ADCA_PRESCALER _SFR_MEM8(0x0204) -#define ADCA_INTFLAGS _SFR_MEM8(0x0206) -#define ADCA_CAL _SFR_MEM16(0x020C) -#define ADCA_CH0RES _SFR_MEM16(0x0210) -#define ADCA_CH1RES _SFR_MEM16(0x0212) -#define ADCA_CH2RES _SFR_MEM16(0x0214) -#define ADCA_CH3RES _SFR_MEM16(0x0216) -#define ADCA_CMP _SFR_MEM16(0x0218) -#define ADCA_CH0_CTRL _SFR_MEM8(0x0220) -#define ADCA_CH0_MUXCTRL _SFR_MEM8(0x0221) -#define ADCA_CH0_INTCTRL _SFR_MEM8(0x0222) -#define ADCA_CH0_INTFLAGS _SFR_MEM8(0x0223) -#define ADCA_CH0_RES _SFR_MEM16(0x0224) -#define ADCA_CH1_CTRL _SFR_MEM8(0x0228) -#define ADCA_CH1_MUXCTRL _SFR_MEM8(0x0229) -#define ADCA_CH1_INTCTRL _SFR_MEM8(0x022A) -#define ADCA_CH1_INTFLAGS _SFR_MEM8(0x022B) -#define ADCA_CH1_RES _SFR_MEM16(0x022C) -#define ADCA_CH2_CTRL _SFR_MEM8(0x0230) -#define ADCA_CH2_MUXCTRL _SFR_MEM8(0x0231) -#define ADCA_CH2_INTCTRL _SFR_MEM8(0x0232) -#define ADCA_CH2_INTFLAGS _SFR_MEM8(0x0233) -#define ADCA_CH2_RES _SFR_MEM16(0x0234) -#define ADCA_CH3_CTRL _SFR_MEM8(0x0238) -#define ADCA_CH3_MUXCTRL _SFR_MEM8(0x0239) -#define ADCA_CH3_INTCTRL _SFR_MEM8(0x023A) -#define ADCA_CH3_INTFLAGS _SFR_MEM8(0x023B) -#define ADCA_CH3_RES _SFR_MEM16(0x023C) - -/* ADCB - Analog to Digital Converter B */ -#define ADCB_CTRLA _SFR_MEM8(0x0240) -#define ADCB_CTRLB _SFR_MEM8(0x0241) -#define ADCB_REFCTRL _SFR_MEM8(0x0242) -#define ADCB_EVCTRL _SFR_MEM8(0x0243) -#define ADCB_PRESCALER _SFR_MEM8(0x0244) -#define ADCB_INTFLAGS _SFR_MEM8(0x0246) -#define ADCB_CAL _SFR_MEM16(0x024C) -#define ADCB_CH0RES _SFR_MEM16(0x0250) -#define ADCB_CH1RES _SFR_MEM16(0x0252) -#define ADCB_CH2RES _SFR_MEM16(0x0254) -#define ADCB_CH3RES _SFR_MEM16(0x0256) -#define ADCB_CMP _SFR_MEM16(0x0258) -#define ADCB_CH0_CTRL _SFR_MEM8(0x0260) -#define ADCB_CH0_MUXCTRL _SFR_MEM8(0x0261) -#define ADCB_CH0_INTCTRL _SFR_MEM8(0x0262) -#define ADCB_CH0_INTFLAGS _SFR_MEM8(0x0263) -#define ADCB_CH0_RES _SFR_MEM16(0x0264) -#define ADCB_CH1_CTRL _SFR_MEM8(0x0268) -#define ADCB_CH1_MUXCTRL _SFR_MEM8(0x0269) -#define ADCB_CH1_INTCTRL _SFR_MEM8(0x026A) -#define ADCB_CH1_INTFLAGS _SFR_MEM8(0x026B) -#define ADCB_CH1_RES _SFR_MEM16(0x026C) -#define ADCB_CH2_CTRL _SFR_MEM8(0x0270) -#define ADCB_CH2_MUXCTRL _SFR_MEM8(0x0271) -#define ADCB_CH2_INTCTRL _SFR_MEM8(0x0272) -#define ADCB_CH2_INTFLAGS _SFR_MEM8(0x0273) -#define ADCB_CH2_RES _SFR_MEM16(0x0274) -#define ADCB_CH3_CTRL _SFR_MEM8(0x0278) -#define ADCB_CH3_MUXCTRL _SFR_MEM8(0x0279) -#define ADCB_CH3_INTCTRL _SFR_MEM8(0x027A) -#define ADCB_CH3_INTFLAGS _SFR_MEM8(0x027B) -#define ADCB_CH3_RES _SFR_MEM16(0x027C) - -/* DACB - Digital to Analog Converter B */ -#define DACB_CTRLA _SFR_MEM8(0x0320) -#define DACB_CTRLB _SFR_MEM8(0x0321) -#define DACB_CTRLC _SFR_MEM8(0x0322) -#define DACB_EVCTRL _SFR_MEM8(0x0323) -#define DACB_TIMCTRL _SFR_MEM8(0x0324) -#define DACB_STATUS _SFR_MEM8(0x0325) -#define DACB_GAINCAL _SFR_MEM8(0x0328) -#define DACB_OFFSETCAL _SFR_MEM8(0x0329) -#define DACB_CH0DATA _SFR_MEM16(0x0338) -#define DACB_CH1DATA _SFR_MEM16(0x033A) - -/* ACA - Analog Comparator A */ -#define ACA_AC0CTRL _SFR_MEM8(0x0380) -#define ACA_AC1CTRL _SFR_MEM8(0x0381) -#define ACA_AC0MUXCTRL _SFR_MEM8(0x0382) -#define ACA_AC1MUXCTRL _SFR_MEM8(0x0383) -#define ACA_CTRLA _SFR_MEM8(0x0384) -#define ACA_CTRLB _SFR_MEM8(0x0385) -#define ACA_WINCTRL _SFR_MEM8(0x0386) -#define ACA_STATUS _SFR_MEM8(0x0387) - -/* ACB - Analog Comparator B */ -#define ACB_AC0CTRL _SFR_MEM8(0x0390) -#define ACB_AC1CTRL _SFR_MEM8(0x0391) -#define ACB_AC0MUXCTRL _SFR_MEM8(0x0392) -#define ACB_AC1MUXCTRL _SFR_MEM8(0x0393) -#define ACB_CTRLA _SFR_MEM8(0x0394) -#define ACB_CTRLB _SFR_MEM8(0x0395) -#define ACB_WINCTRL _SFR_MEM8(0x0396) -#define ACB_STATUS _SFR_MEM8(0x0397) - -/* RTC - Real-Time Counter */ -#define RTC_CTRL _SFR_MEM8(0x0400) -#define RTC_STATUS _SFR_MEM8(0x0401) -#define RTC_INTCTRL _SFR_MEM8(0x0402) -#define RTC_INTFLAGS _SFR_MEM8(0x0403) -#define RTC_TEMP _SFR_MEM8(0x0404) -#define RTC_CNT _SFR_MEM16(0x0408) -#define RTC_PER _SFR_MEM16(0x040A) -#define RTC_COMP _SFR_MEM16(0x040C) - -/* TWIC - Two-Wire Interface C */ -#define TWIC_CTRL _SFR_MEM8(0x0480) -#define TWIC_MASTER_CTRLA _SFR_MEM8(0x0481) -#define TWIC_MASTER_CTRLB _SFR_MEM8(0x0482) -#define TWIC_MASTER_CTRLC _SFR_MEM8(0x0483) -#define TWIC_MASTER_STATUS _SFR_MEM8(0x0484) -#define TWIC_MASTER_BAUD _SFR_MEM8(0x0485) -#define TWIC_MASTER_ADDR _SFR_MEM8(0x0486) -#define TWIC_MASTER_DATA _SFR_MEM8(0x0487) -#define TWIC_SLAVE_CTRLA _SFR_MEM8(0x0488) -#define TWIC_SLAVE_CTRLB _SFR_MEM8(0x0489) -#define TWIC_SLAVE_STATUS _SFR_MEM8(0x048A) -#define TWIC_SLAVE_ADDR _SFR_MEM8(0x048B) -#define TWIC_SLAVE_DATA _SFR_MEM8(0x048C) -#define TWIC_SLAVE_ADDRMASK _SFR_MEM8(0x048D) - -/* TWIE - Two-Wire Interface E */ -#define TWIE_CTRL _SFR_MEM8(0x04A0) -#define TWIE_MASTER_CTRLA _SFR_MEM8(0x04A1) -#define TWIE_MASTER_CTRLB _SFR_MEM8(0x04A2) -#define TWIE_MASTER_CTRLC _SFR_MEM8(0x04A3) -#define TWIE_MASTER_STATUS _SFR_MEM8(0x04A4) -#define TWIE_MASTER_BAUD _SFR_MEM8(0x04A5) -#define TWIE_MASTER_ADDR _SFR_MEM8(0x04A6) -#define TWIE_MASTER_DATA _SFR_MEM8(0x04A7) -#define TWIE_SLAVE_CTRLA _SFR_MEM8(0x04A8) -#define TWIE_SLAVE_CTRLB _SFR_MEM8(0x04A9) -#define TWIE_SLAVE_STATUS _SFR_MEM8(0x04AA) -#define TWIE_SLAVE_ADDR _SFR_MEM8(0x04AB) -#define TWIE_SLAVE_DATA _SFR_MEM8(0x04AC) -#define TWIE_SLAVE_ADDRMASK _SFR_MEM8(0x04AD) - -/* PORTA - Port A */ -#define PORTA_DIR _SFR_MEM8(0x0600) -#define PORTA_DIRSET _SFR_MEM8(0x0601) -#define PORTA_DIRCLR _SFR_MEM8(0x0602) -#define PORTA_DIRTGL _SFR_MEM8(0x0603) -#define PORTA_OUT _SFR_MEM8(0x0604) -#define PORTA_OUTSET _SFR_MEM8(0x0605) -#define PORTA_OUTCLR _SFR_MEM8(0x0606) -#define PORTA_OUTTGL _SFR_MEM8(0x0607) -#define PORTA_IN _SFR_MEM8(0x0608) -#define PORTA_INTCTRL _SFR_MEM8(0x0609) -#define PORTA_INT0MASK _SFR_MEM8(0x060A) -#define PORTA_INT1MASK _SFR_MEM8(0x060B) -#define PORTA_INTFLAGS _SFR_MEM8(0x060C) -#define PORTA_PIN0CTRL _SFR_MEM8(0x0610) -#define PORTA_PIN1CTRL _SFR_MEM8(0x0611) -#define PORTA_PIN2CTRL _SFR_MEM8(0x0612) -#define PORTA_PIN3CTRL _SFR_MEM8(0x0613) -#define PORTA_PIN4CTRL _SFR_MEM8(0x0614) -#define PORTA_PIN5CTRL _SFR_MEM8(0x0615) -#define PORTA_PIN6CTRL _SFR_MEM8(0x0616) -#define PORTA_PIN7CTRL _SFR_MEM8(0x0617) - -/* PORTB - Port B */ -#define PORTB_DIR _SFR_MEM8(0x0620) -#define PORTB_DIRSET _SFR_MEM8(0x0621) -#define PORTB_DIRCLR _SFR_MEM8(0x0622) -#define PORTB_DIRTGL _SFR_MEM8(0x0623) -#define PORTB_OUT _SFR_MEM8(0x0624) -#define PORTB_OUTSET _SFR_MEM8(0x0625) -#define PORTB_OUTCLR _SFR_MEM8(0x0626) -#define PORTB_OUTTGL _SFR_MEM8(0x0627) -#define PORTB_IN _SFR_MEM8(0x0628) -#define PORTB_INTCTRL _SFR_MEM8(0x0629) -#define PORTB_INT0MASK _SFR_MEM8(0x062A) -#define PORTB_INT1MASK _SFR_MEM8(0x062B) -#define PORTB_INTFLAGS _SFR_MEM8(0x062C) -#define PORTB_PIN0CTRL _SFR_MEM8(0x0630) -#define PORTB_PIN1CTRL _SFR_MEM8(0x0631) -#define PORTB_PIN2CTRL _SFR_MEM8(0x0632) -#define PORTB_PIN3CTRL _SFR_MEM8(0x0633) -#define PORTB_PIN4CTRL _SFR_MEM8(0x0634) -#define PORTB_PIN5CTRL _SFR_MEM8(0x0635) -#define PORTB_PIN6CTRL _SFR_MEM8(0x0636) -#define PORTB_PIN7CTRL _SFR_MEM8(0x0637) - -/* PORTC - Port C */ -#define PORTC_DIR _SFR_MEM8(0x0640) -#define PORTC_DIRSET _SFR_MEM8(0x0641) -#define PORTC_DIRCLR _SFR_MEM8(0x0642) -#define PORTC_DIRTGL _SFR_MEM8(0x0643) -#define PORTC_OUT _SFR_MEM8(0x0644) -#define PORTC_OUTSET _SFR_MEM8(0x0645) -#define PORTC_OUTCLR _SFR_MEM8(0x0646) -#define PORTC_OUTTGL _SFR_MEM8(0x0647) -#define PORTC_IN _SFR_MEM8(0x0648) -#define PORTC_INTCTRL _SFR_MEM8(0x0649) -#define PORTC_INT0MASK _SFR_MEM8(0x064A) -#define PORTC_INT1MASK _SFR_MEM8(0x064B) -#define PORTC_INTFLAGS _SFR_MEM8(0x064C) -#define PORTC_PIN0CTRL _SFR_MEM8(0x0650) -#define PORTC_PIN1CTRL _SFR_MEM8(0x0651) -#define PORTC_PIN2CTRL _SFR_MEM8(0x0652) -#define PORTC_PIN3CTRL _SFR_MEM8(0x0653) -#define PORTC_PIN4CTRL _SFR_MEM8(0x0654) -#define PORTC_PIN5CTRL _SFR_MEM8(0x0655) -#define PORTC_PIN6CTRL _SFR_MEM8(0x0656) -#define PORTC_PIN7CTRL _SFR_MEM8(0x0657) - -/* PORTD - Port D */ -#define PORTD_DIR _SFR_MEM8(0x0660) -#define PORTD_DIRSET _SFR_MEM8(0x0661) -#define PORTD_DIRCLR _SFR_MEM8(0x0662) -#define PORTD_DIRTGL _SFR_MEM8(0x0663) -#define PORTD_OUT _SFR_MEM8(0x0664) -#define PORTD_OUTSET _SFR_MEM8(0x0665) -#define PORTD_OUTCLR _SFR_MEM8(0x0666) -#define PORTD_OUTTGL _SFR_MEM8(0x0667) -#define PORTD_IN _SFR_MEM8(0x0668) -#define PORTD_INTCTRL _SFR_MEM8(0x0669) -#define PORTD_INT0MASK _SFR_MEM8(0x066A) -#define PORTD_INT1MASK _SFR_MEM8(0x066B) -#define PORTD_INTFLAGS _SFR_MEM8(0x066C) -#define PORTD_PIN0CTRL _SFR_MEM8(0x0670) -#define PORTD_PIN1CTRL _SFR_MEM8(0x0671) -#define PORTD_PIN2CTRL _SFR_MEM8(0x0672) -#define PORTD_PIN3CTRL _SFR_MEM8(0x0673) -#define PORTD_PIN4CTRL _SFR_MEM8(0x0674) -#define PORTD_PIN5CTRL _SFR_MEM8(0x0675) -#define PORTD_PIN6CTRL _SFR_MEM8(0x0676) -#define PORTD_PIN7CTRL _SFR_MEM8(0x0677) - -/* PORTE - Port E */ -#define PORTE_DIR _SFR_MEM8(0x0680) -#define PORTE_DIRSET _SFR_MEM8(0x0681) -#define PORTE_DIRCLR _SFR_MEM8(0x0682) -#define PORTE_DIRTGL _SFR_MEM8(0x0683) -#define PORTE_OUT _SFR_MEM8(0x0684) -#define PORTE_OUTSET _SFR_MEM8(0x0685) -#define PORTE_OUTCLR _SFR_MEM8(0x0686) -#define PORTE_OUTTGL _SFR_MEM8(0x0687) -#define PORTE_IN _SFR_MEM8(0x0688) -#define PORTE_INTCTRL _SFR_MEM8(0x0689) -#define PORTE_INT0MASK _SFR_MEM8(0x068A) -#define PORTE_INT1MASK _SFR_MEM8(0x068B) -#define PORTE_INTFLAGS _SFR_MEM8(0x068C) -#define PORTE_PIN0CTRL _SFR_MEM8(0x0690) -#define PORTE_PIN1CTRL _SFR_MEM8(0x0691) -#define PORTE_PIN2CTRL _SFR_MEM8(0x0692) -#define PORTE_PIN3CTRL _SFR_MEM8(0x0693) -#define PORTE_PIN4CTRL _SFR_MEM8(0x0694) -#define PORTE_PIN5CTRL _SFR_MEM8(0x0695) -#define PORTE_PIN6CTRL _SFR_MEM8(0x0696) -#define PORTE_PIN7CTRL _SFR_MEM8(0x0697) - -/* PORTF - Port F */ -#define PORTF_DIR _SFR_MEM8(0x06A0) -#define PORTF_DIRSET _SFR_MEM8(0x06A1) -#define PORTF_DIRCLR _SFR_MEM8(0x06A2) -#define PORTF_DIRTGL _SFR_MEM8(0x06A3) -#define PORTF_OUT _SFR_MEM8(0x06A4) -#define PORTF_OUTSET _SFR_MEM8(0x06A5) -#define PORTF_OUTCLR _SFR_MEM8(0x06A6) -#define PORTF_OUTTGL _SFR_MEM8(0x06A7) -#define PORTF_IN _SFR_MEM8(0x06A8) -#define PORTF_INTCTRL _SFR_MEM8(0x06A9) -#define PORTF_INT0MASK _SFR_MEM8(0x06AA) -#define PORTF_INT1MASK _SFR_MEM8(0x06AB) -#define PORTF_INTFLAGS _SFR_MEM8(0x06AC) -#define PORTF_PIN0CTRL _SFR_MEM8(0x06B0) -#define PORTF_PIN1CTRL _SFR_MEM8(0x06B1) -#define PORTF_PIN2CTRL _SFR_MEM8(0x06B2) -#define PORTF_PIN3CTRL _SFR_MEM8(0x06B3) -#define PORTF_PIN4CTRL _SFR_MEM8(0x06B4) -#define PORTF_PIN5CTRL _SFR_MEM8(0x06B5) -#define PORTF_PIN6CTRL _SFR_MEM8(0x06B6) -#define PORTF_PIN7CTRL _SFR_MEM8(0x06B7) - -/* PORTR - Port R */ -#define PORTR_DIR _SFR_MEM8(0x07E0) -#define PORTR_DIRSET _SFR_MEM8(0x07E1) -#define PORTR_DIRCLR _SFR_MEM8(0x07E2) -#define PORTR_DIRTGL _SFR_MEM8(0x07E3) -#define PORTR_OUT _SFR_MEM8(0x07E4) -#define PORTR_OUTSET _SFR_MEM8(0x07E5) -#define PORTR_OUTCLR _SFR_MEM8(0x07E6) -#define PORTR_OUTTGL _SFR_MEM8(0x07E7) -#define PORTR_IN _SFR_MEM8(0x07E8) -#define PORTR_INTCTRL _SFR_MEM8(0x07E9) -#define PORTR_INT0MASK _SFR_MEM8(0x07EA) -#define PORTR_INT1MASK _SFR_MEM8(0x07EB) -#define PORTR_INTFLAGS _SFR_MEM8(0x07EC) -#define PORTR_PIN0CTRL _SFR_MEM8(0x07F0) -#define PORTR_PIN1CTRL _SFR_MEM8(0x07F1) -#define PORTR_PIN2CTRL _SFR_MEM8(0x07F2) -#define PORTR_PIN3CTRL _SFR_MEM8(0x07F3) -#define PORTR_PIN4CTRL _SFR_MEM8(0x07F4) -#define PORTR_PIN5CTRL _SFR_MEM8(0x07F5) -#define PORTR_PIN6CTRL _SFR_MEM8(0x07F6) -#define PORTR_PIN7CTRL _SFR_MEM8(0x07F7) - -/* TCC0 - Timer/Counter C0 */ -#define TCC0_CTRLA _SFR_MEM8(0x0800) -#define TCC0_CTRLB _SFR_MEM8(0x0801) -#define TCC0_CTRLC _SFR_MEM8(0x0802) -#define TCC0_CTRLD _SFR_MEM8(0x0803) -#define TCC0_CTRLE _SFR_MEM8(0x0804) -#define TCC0_INTCTRLA _SFR_MEM8(0x0806) -#define TCC0_INTCTRLB _SFR_MEM8(0x0807) -#define TCC0_CTRLFCLR _SFR_MEM8(0x0808) -#define TCC0_CTRLFSET _SFR_MEM8(0x0809) -#define TCC0_CTRLGCLR _SFR_MEM8(0x080A) -#define TCC0_CTRLGSET _SFR_MEM8(0x080B) -#define TCC0_INTFLAGS _SFR_MEM8(0x080C) -#define TCC0_TEMP _SFR_MEM8(0x080F) -#define TCC0_CNT _SFR_MEM16(0x0820) -#define TCC0_PER _SFR_MEM16(0x0826) -#define TCC0_CCA _SFR_MEM16(0x0828) -#define TCC0_CCB _SFR_MEM16(0x082A) -#define TCC0_CCC _SFR_MEM16(0x082C) -#define TCC0_CCD _SFR_MEM16(0x082E) -#define TCC0_PERBUF _SFR_MEM16(0x0836) -#define TCC0_CCABUF _SFR_MEM16(0x0838) -#define TCC0_CCBBUF _SFR_MEM16(0x083A) -#define TCC0_CCCBUF _SFR_MEM16(0x083C) -#define TCC0_CCDBUF _SFR_MEM16(0x083E) - -/* TCC1 - Timer/Counter C1 */ -#define TCC1_CTRLA _SFR_MEM8(0x0840) -#define TCC1_CTRLB _SFR_MEM8(0x0841) -#define TCC1_CTRLC _SFR_MEM8(0x0842) -#define TCC1_CTRLD _SFR_MEM8(0x0843) -#define TCC1_CTRLE _SFR_MEM8(0x0844) -#define TCC1_INTCTRLA _SFR_MEM8(0x0846) -#define TCC1_INTCTRLB _SFR_MEM8(0x0847) -#define TCC1_CTRLFCLR _SFR_MEM8(0x0848) -#define TCC1_CTRLFSET _SFR_MEM8(0x0849) -#define TCC1_CTRLGCLR _SFR_MEM8(0x084A) -#define TCC1_CTRLGSET _SFR_MEM8(0x084B) -#define TCC1_INTFLAGS _SFR_MEM8(0x084C) -#define TCC1_TEMP _SFR_MEM8(0x084F) -#define TCC1_CNT _SFR_MEM16(0x0860) -#define TCC1_PER _SFR_MEM16(0x0866) -#define TCC1_CCA _SFR_MEM16(0x0868) -#define TCC1_CCB _SFR_MEM16(0x086A) -#define TCC1_PERBUF _SFR_MEM16(0x0876) -#define TCC1_CCABUF _SFR_MEM16(0x0878) -#define TCC1_CCBBUF _SFR_MEM16(0x087A) - -/* AWEXC - Advanced Waveform Extension C */ -#define AWEXC_CTRL _SFR_MEM8(0x0880) -#define AWEXC_FDEMASK _SFR_MEM8(0x0882) -#define AWEXC_FDCTRL _SFR_MEM8(0x0883) -#define AWEXC_STATUS _SFR_MEM8(0x0884) -#define AWEXC_DTBOTH _SFR_MEM8(0x0886) -#define AWEXC_DTBOTHBUF _SFR_MEM8(0x0887) -#define AWEXC_DTLS _SFR_MEM8(0x0888) -#define AWEXC_DTHS _SFR_MEM8(0x0889) -#define AWEXC_DTLSBUF _SFR_MEM8(0x088A) -#define AWEXC_DTHSBUF _SFR_MEM8(0x088B) -#define AWEXC_OUTOVEN _SFR_MEM8(0x088C) - -/* HIRESC - High-Resolution Extension C */ -#define HIRESC_CTRLA _SFR_MEM8(0x0890) - -/* USARTC0 - Universal Asynchronous Receiver-Transmitter C0 */ -#define USARTC0_DATA _SFR_MEM8(0x08A0) -#define USARTC0_STATUS _SFR_MEM8(0x08A1) -#define USARTC0_CTRLA _SFR_MEM8(0x08A3) -#define USARTC0_CTRLB _SFR_MEM8(0x08A4) -#define USARTC0_CTRLC _SFR_MEM8(0x08A5) -#define USARTC0_BAUDCTRLA _SFR_MEM8(0x08A6) -#define USARTC0_BAUDCTRLB _SFR_MEM8(0x08A7) - -/* USARTC1 - Universal Asynchronous Receiver-Transmitter C1 */ -#define USARTC1_DATA _SFR_MEM8(0x08B0) -#define USARTC1_STATUS _SFR_MEM8(0x08B1) -#define USARTC1_CTRLA _SFR_MEM8(0x08B3) -#define USARTC1_CTRLB _SFR_MEM8(0x08B4) -#define USARTC1_CTRLC _SFR_MEM8(0x08B5) -#define USARTC1_BAUDCTRLA _SFR_MEM8(0x08B6) -#define USARTC1_BAUDCTRLB _SFR_MEM8(0x08B7) - -/* SPIC - Serial Peripheral Interface C */ -#define SPIC_CTRL _SFR_MEM8(0x08C0) -#define SPIC_INTCTRL _SFR_MEM8(0x08C1) -#define SPIC_STATUS _SFR_MEM8(0x08C2) -#define SPIC_DATA _SFR_MEM8(0x08C3) - -/* IRCOM - IR Communication Module */ -#define IRCOM_CTRL _SFR_MEM8(0x08F8) -#define IRCOM_TXPLCTRL _SFR_MEM8(0x08F9) -#define IRCOM_RXPLCTRL _SFR_MEM8(0x08FA) - -/* TCD0 - Timer/Counter D0 */ -#define TCD0_CTRLA _SFR_MEM8(0x0900) -#define TCD0_CTRLB _SFR_MEM8(0x0901) -#define TCD0_CTRLC _SFR_MEM8(0x0902) -#define TCD0_CTRLD _SFR_MEM8(0x0903) -#define TCD0_CTRLE _SFR_MEM8(0x0904) -#define TCD0_INTCTRLA _SFR_MEM8(0x0906) -#define TCD0_INTCTRLB _SFR_MEM8(0x0907) -#define TCD0_CTRLFCLR _SFR_MEM8(0x0908) -#define TCD0_CTRLFSET _SFR_MEM8(0x0909) -#define TCD0_CTRLGCLR _SFR_MEM8(0x090A) -#define TCD0_CTRLGSET _SFR_MEM8(0x090B) -#define TCD0_INTFLAGS _SFR_MEM8(0x090C) -#define TCD0_TEMP _SFR_MEM8(0x090F) -#define TCD0_CNT _SFR_MEM16(0x0920) -#define TCD0_PER _SFR_MEM16(0x0926) -#define TCD0_CCA _SFR_MEM16(0x0928) -#define TCD0_CCB _SFR_MEM16(0x092A) -#define TCD0_CCC _SFR_MEM16(0x092C) -#define TCD0_CCD _SFR_MEM16(0x092E) -#define TCD0_PERBUF _SFR_MEM16(0x0936) -#define TCD0_CCABUF _SFR_MEM16(0x0938) -#define TCD0_CCBBUF _SFR_MEM16(0x093A) -#define TCD0_CCCBUF _SFR_MEM16(0x093C) -#define TCD0_CCDBUF _SFR_MEM16(0x093E) - -/* TCD1 - Timer/Counter D1 */ -#define TCD1_CTRLA _SFR_MEM8(0x0940) -#define TCD1_CTRLB _SFR_MEM8(0x0941) -#define TCD1_CTRLC _SFR_MEM8(0x0942) -#define TCD1_CTRLD _SFR_MEM8(0x0943) -#define TCD1_CTRLE _SFR_MEM8(0x0944) -#define TCD1_INTCTRLA _SFR_MEM8(0x0946) -#define TCD1_INTCTRLB _SFR_MEM8(0x0947) -#define TCD1_CTRLFCLR _SFR_MEM8(0x0948) -#define TCD1_CTRLFSET _SFR_MEM8(0x0949) -#define TCD1_CTRLGCLR _SFR_MEM8(0x094A) -#define TCD1_CTRLGSET _SFR_MEM8(0x094B) -#define TCD1_INTFLAGS _SFR_MEM8(0x094C) -#define TCD1_TEMP _SFR_MEM8(0x094F) -#define TCD1_CNT _SFR_MEM16(0x0960) -#define TCD1_PER _SFR_MEM16(0x0966) -#define TCD1_CCA _SFR_MEM16(0x0968) -#define TCD1_CCB _SFR_MEM16(0x096A) -#define TCD1_PERBUF _SFR_MEM16(0x0976) -#define TCD1_CCABUF _SFR_MEM16(0x0978) -#define TCD1_CCBBUF _SFR_MEM16(0x097A) - -/* HIRESD - High-Resolution Extension D */ -#define HIRESD_CTRLA _SFR_MEM8(0x0990) - -/* USARTD0 - Universal Asynchronous Receiver-Transmitter D0 */ -#define USARTD0_DATA _SFR_MEM8(0x09A0) -#define USARTD0_STATUS _SFR_MEM8(0x09A1) -#define USARTD0_CTRLA _SFR_MEM8(0x09A3) -#define USARTD0_CTRLB _SFR_MEM8(0x09A4) -#define USARTD0_CTRLC _SFR_MEM8(0x09A5) -#define USARTD0_BAUDCTRLA _SFR_MEM8(0x09A6) -#define USARTD0_BAUDCTRLB _SFR_MEM8(0x09A7) - -/* USARTD1 - Universal Asynchronous Receiver-Transmitter D1 */ -#define USARTD1_DATA _SFR_MEM8(0x09B0) -#define USARTD1_STATUS _SFR_MEM8(0x09B1) -#define USARTD1_CTRLA _SFR_MEM8(0x09B3) -#define USARTD1_CTRLB _SFR_MEM8(0x09B4) -#define USARTD1_CTRLC _SFR_MEM8(0x09B5) -#define USARTD1_BAUDCTRLA _SFR_MEM8(0x09B6) -#define USARTD1_BAUDCTRLB _SFR_MEM8(0x09B7) - -/* SPID - Serial Peripheral Interface D */ -#define SPID_CTRL _SFR_MEM8(0x09C0) -#define SPID_INTCTRL _SFR_MEM8(0x09C1) -#define SPID_STATUS _SFR_MEM8(0x09C2) -#define SPID_DATA _SFR_MEM8(0x09C3) - -/* TCE0 - Timer/Counter E0 */ -#define TCE0_CTRLA _SFR_MEM8(0x0A00) -#define TCE0_CTRLB _SFR_MEM8(0x0A01) -#define TCE0_CTRLC _SFR_MEM8(0x0A02) -#define TCE0_CTRLD _SFR_MEM8(0x0A03) -#define TCE0_CTRLE _SFR_MEM8(0x0A04) -#define TCE0_INTCTRLA _SFR_MEM8(0x0A06) -#define TCE0_INTCTRLB _SFR_MEM8(0x0A07) -#define TCE0_CTRLFCLR _SFR_MEM8(0x0A08) -#define TCE0_CTRLFSET _SFR_MEM8(0x0A09) -#define TCE0_CTRLGCLR _SFR_MEM8(0x0A0A) -#define TCE0_CTRLGSET _SFR_MEM8(0x0A0B) -#define TCE0_INTFLAGS _SFR_MEM8(0x0A0C) -#define TCE0_TEMP _SFR_MEM8(0x0A0F) -#define TCE0_CNT _SFR_MEM16(0x0A20) -#define TCE0_PER _SFR_MEM16(0x0A26) -#define TCE0_CCA _SFR_MEM16(0x0A28) -#define TCE0_CCB _SFR_MEM16(0x0A2A) -#define TCE0_CCC _SFR_MEM16(0x0A2C) -#define TCE0_CCD _SFR_MEM16(0x0A2E) -#define TCE0_PERBUF _SFR_MEM16(0x0A36) -#define TCE0_CCABUF _SFR_MEM16(0x0A38) -#define TCE0_CCBBUF _SFR_MEM16(0x0A3A) -#define TCE0_CCCBUF _SFR_MEM16(0x0A3C) -#define TCE0_CCDBUF _SFR_MEM16(0x0A3E) - -/* TCE1 - Timer/Counter E1 */ -#define TCE1_CTRLA _SFR_MEM8(0x0A40) -#define TCE1_CTRLB _SFR_MEM8(0x0A41) -#define TCE1_CTRLC _SFR_MEM8(0x0A42) -#define TCE1_CTRLD _SFR_MEM8(0x0A43) -#define TCE1_CTRLE _SFR_MEM8(0x0A44) -#define TCE1_INTCTRLA _SFR_MEM8(0x0A46) -#define TCE1_INTCTRLB _SFR_MEM8(0x0A47) -#define TCE1_CTRLFCLR _SFR_MEM8(0x0A48) -#define TCE1_CTRLFSET _SFR_MEM8(0x0A49) -#define TCE1_CTRLGCLR _SFR_MEM8(0x0A4A) -#define TCE1_CTRLGSET _SFR_MEM8(0x0A4B) -#define TCE1_INTFLAGS _SFR_MEM8(0x0A4C) -#define TCE1_TEMP _SFR_MEM8(0x0A4F) -#define TCE1_CNT _SFR_MEM16(0x0A60) -#define TCE1_PER _SFR_MEM16(0x0A66) -#define TCE1_CCA _SFR_MEM16(0x0A68) -#define TCE1_CCB _SFR_MEM16(0x0A6A) -#define TCE1_PERBUF _SFR_MEM16(0x0A76) -#define TCE1_CCABUF _SFR_MEM16(0x0A78) -#define TCE1_CCBBUF _SFR_MEM16(0x0A7A) - -/* AWEXE - Advanced Waveform Extension E */ -#define AWEXE_CTRL _SFR_MEM8(0x0A80) -#define AWEXE_FDEMASK _SFR_MEM8(0x0A82) -#define AWEXE_FDCTRL _SFR_MEM8(0x0A83) -#define AWEXE_STATUS _SFR_MEM8(0x0A84) -#define AWEXE_DTBOTH _SFR_MEM8(0x0A86) -#define AWEXE_DTBOTHBUF _SFR_MEM8(0x0A87) -#define AWEXE_DTLS _SFR_MEM8(0x0A88) -#define AWEXE_DTHS _SFR_MEM8(0x0A89) -#define AWEXE_DTLSBUF _SFR_MEM8(0x0A8A) -#define AWEXE_DTHSBUF _SFR_MEM8(0x0A8B) -#define AWEXE_OUTOVEN _SFR_MEM8(0x0A8C) - -/* HIRESE - High-Resolution Extension E */ -#define HIRESE_CTRLA _SFR_MEM8(0x0A90) - -/* USARTE0 - Universal Asynchronous Receiver-Transmitter E0 */ -#define USARTE0_DATA _SFR_MEM8(0x0AA0) -#define USARTE0_STATUS _SFR_MEM8(0x0AA1) -#define USARTE0_CTRLA _SFR_MEM8(0x0AA3) -#define USARTE0_CTRLB _SFR_MEM8(0x0AA4) -#define USARTE0_CTRLC _SFR_MEM8(0x0AA5) -#define USARTE0_BAUDCTRLA _SFR_MEM8(0x0AA6) -#define USARTE0_BAUDCTRLB _SFR_MEM8(0x0AA7) - -/* USARTE1 - Universal Asynchronous Receiver-Transmitter E1 */ -#define USARTE1_DATA _SFR_MEM8(0x0AB0) -#define USARTE1_STATUS _SFR_MEM8(0x0AB1) -#define USARTE1_CTRLA _SFR_MEM8(0x0AB3) -#define USARTE1_CTRLB _SFR_MEM8(0x0AB4) -#define USARTE1_CTRLC _SFR_MEM8(0x0AB5) -#define USARTE1_BAUDCTRLA _SFR_MEM8(0x0AB6) -#define USARTE1_BAUDCTRLB _SFR_MEM8(0x0AB7) - -/* SPIE - Serial Peripheral Interface E */ -#define SPIE_CTRL _SFR_MEM8(0x0AC0) -#define SPIE_INTCTRL _SFR_MEM8(0x0AC1) -#define SPIE_STATUS _SFR_MEM8(0x0AC2) -#define SPIE_DATA _SFR_MEM8(0x0AC3) - -/* TCF0 - Timer/Counter F0 */ -#define TCF0_CTRLA _SFR_MEM8(0x0B00) -#define TCF0_CTRLB _SFR_MEM8(0x0B01) -#define TCF0_CTRLC _SFR_MEM8(0x0B02) -#define TCF0_CTRLD _SFR_MEM8(0x0B03) -#define TCF0_CTRLE _SFR_MEM8(0x0B04) -#define TCF0_INTCTRLA _SFR_MEM8(0x0B06) -#define TCF0_INTCTRLB _SFR_MEM8(0x0B07) -#define TCF0_CTRLFCLR _SFR_MEM8(0x0B08) -#define TCF0_CTRLFSET _SFR_MEM8(0x0B09) -#define TCF0_CTRLGCLR _SFR_MEM8(0x0B0A) -#define TCF0_CTRLGSET _SFR_MEM8(0x0B0B) -#define TCF0_INTFLAGS _SFR_MEM8(0x0B0C) -#define TCF0_TEMP _SFR_MEM8(0x0B0F) -#define TCF0_CNT _SFR_MEM16(0x0B20) -#define TCF0_PER _SFR_MEM16(0x0B26) -#define TCF0_CCA _SFR_MEM16(0x0B28) -#define TCF0_CCB _SFR_MEM16(0x0B2A) -#define TCF0_CCC _SFR_MEM16(0x0B2C) -#define TCF0_CCD _SFR_MEM16(0x0B2E) -#define TCF0_PERBUF _SFR_MEM16(0x0B36) -#define TCF0_CCABUF _SFR_MEM16(0x0B38) -#define TCF0_CCBBUF _SFR_MEM16(0x0B3A) -#define TCF0_CCCBUF _SFR_MEM16(0x0B3C) -#define TCF0_CCDBUF _SFR_MEM16(0x0B3E) - -/* HIRESF - High-Resolution Extension F */ -#define HIRESF_CTRLA _SFR_MEM8(0x0B90) - -/* USARTF0 - Universal Asynchronous Receiver-Transmitter F0 */ -#define USARTF0_DATA _SFR_MEM8(0x0BA0) -#define USARTF0_STATUS _SFR_MEM8(0x0BA1) -#define USARTF0_CTRLA _SFR_MEM8(0x0BA3) -#define USARTF0_CTRLB _SFR_MEM8(0x0BA4) -#define USARTF0_CTRLC _SFR_MEM8(0x0BA5) -#define USARTF0_BAUDCTRLA _SFR_MEM8(0x0BA6) -#define USARTF0_BAUDCTRLB _SFR_MEM8(0x0BA7) - -/* USARTF1 - Universal Asynchronous Receiver-Transmitter F1 */ -#define USARTF1_DATA _SFR_MEM8(0x0BB0) -#define USARTF1_STATUS _SFR_MEM8(0x0BB1) -#define USARTF1_CTRLA _SFR_MEM8(0x0BB3) -#define USARTF1_CTRLB _SFR_MEM8(0x0BB4) -#define USARTF1_CTRLC _SFR_MEM8(0x0BB5) -#define USARTF1_BAUDCTRLA _SFR_MEM8(0x0BB6) -#define USARTF1_BAUDCTRLB _SFR_MEM8(0x0BB7) - -/* SPIF - Serial Peripheral Interface F */ -#define SPIF_CTRL _SFR_MEM8(0x0BC0) -#define SPIF_INTCTRL _SFR_MEM8(0x0BC1) -#define SPIF_STATUS _SFR_MEM8(0x0BC2) -#define SPIF_DATA _SFR_MEM8(0x0BC3) - - - -/*================== Bitfield Definitions ================== */ - -/* XOCD - On-Chip Debug System */ -/* OCD.OCDR1 bit masks and bit positions */ -#define OCD_OCDRD_bm 0x01 /* OCDR Dirty bit mask. */ -#define OCD_OCDRD_bp 0 /* OCDR Dirty bit position. */ - - -/* CPU - CPU */ -/* CPU.CCP bit masks and bit positions */ -#define CPU_CCP_gm 0xFF /* CCP signature group mask. */ -#define CPU_CCP_gp 0 /* CCP signature group position. */ -#define CPU_CCP0_bm (1<<0) /* CCP signature bit 0 mask. */ -#define CPU_CCP0_bp 0 /* CCP signature bit 0 position. */ -#define CPU_CCP1_bm (1<<1) /* CCP signature bit 1 mask. */ -#define CPU_CCP1_bp 1 /* CCP signature bit 1 position. */ -#define CPU_CCP2_bm (1<<2) /* CCP signature bit 2 mask. */ -#define CPU_CCP2_bp 2 /* CCP signature bit 2 position. */ -#define CPU_CCP3_bm (1<<3) /* CCP signature bit 3 mask. */ -#define CPU_CCP3_bp 3 /* CCP signature bit 3 position. */ -#define CPU_CCP4_bm (1<<4) /* CCP signature bit 4 mask. */ -#define CPU_CCP4_bp 4 /* CCP signature bit 4 position. */ -#define CPU_CCP5_bm (1<<5) /* CCP signature bit 5 mask. */ -#define CPU_CCP5_bp 5 /* CCP signature bit 5 position. */ -#define CPU_CCP6_bm (1<<6) /* CCP signature bit 6 mask. */ -#define CPU_CCP6_bp 6 /* CCP signature bit 6 position. */ -#define CPU_CCP7_bm (1<<7) /* CCP signature bit 7 mask. */ -#define CPU_CCP7_bp 7 /* CCP signature bit 7 position. */ - - -/* CPU.SREG bit masks and bit positions */ -#define CPU_I_bm 0x80 /* Global Interrupt Enable Flag bit mask. */ -#define CPU_I_bp 7 /* Global Interrupt Enable Flag bit position. */ - -#define CPU_T_bm 0x40 /* Transfer Bit bit mask. */ -#define CPU_T_bp 6 /* Transfer Bit bit position. */ - -#define CPU_H_bm 0x20 /* Half Carry Flag bit mask. */ -#define CPU_H_bp 5 /* Half Carry Flag bit position. */ - -#define CPU_S_bm 0x10 /* N Exclusive Or V Flag bit mask. */ -#define CPU_S_bp 4 /* N Exclusive Or V Flag bit position. */ - -#define CPU_V_bm 0x08 /* Two's Complement Overflow Flag bit mask. */ -#define CPU_V_bp 3 /* Two's Complement Overflow Flag bit position. */ - -#define CPU_N_bm 0x04 /* Negative Flag bit mask. */ -#define CPU_N_bp 2 /* Negative Flag bit position. */ - -#define CPU_Z_bm 0x02 /* Zero Flag bit mask. */ -#define CPU_Z_bp 1 /* Zero Flag bit position. */ - -#define CPU_C_bm 0x01 /* Carry Flag bit mask. */ -#define CPU_C_bp 0 /* Carry Flag bit position. */ - - -/* CLK - Clock System */ -/* CLK.CTRL bit masks and bit positions */ -#define CLK_SCLKSEL_gm 0x07 /* System Clock Selection group mask. */ -#define CLK_SCLKSEL_gp 0 /* System Clock Selection group position. */ -#define CLK_SCLKSEL0_bm (1<<0) /* System Clock Selection bit 0 mask. */ -#define CLK_SCLKSEL0_bp 0 /* System Clock Selection bit 0 position. */ -#define CLK_SCLKSEL1_bm (1<<1) /* System Clock Selection bit 1 mask. */ -#define CLK_SCLKSEL1_bp 1 /* System Clock Selection bit 1 position. */ -#define CLK_SCLKSEL2_bm (1<<2) /* System Clock Selection bit 2 mask. */ -#define CLK_SCLKSEL2_bp 2 /* System Clock Selection bit 2 position. */ - - -/* CLK.PSCTRL bit masks and bit positions */ -#define CLK_PSADIV_gm 0x7C /* Prescaler A Division Factor group mask. */ -#define CLK_PSADIV_gp 2 /* Prescaler A Division Factor group position. */ -#define CLK_PSADIV0_bm (1<<2) /* Prescaler A Division Factor bit 0 mask. */ -#define CLK_PSADIV0_bp 2 /* Prescaler A Division Factor bit 0 position. */ -#define CLK_PSADIV1_bm (1<<3) /* Prescaler A Division Factor bit 1 mask. */ -#define CLK_PSADIV1_bp 3 /* Prescaler A Division Factor bit 1 position. */ -#define CLK_PSADIV2_bm (1<<4) /* Prescaler A Division Factor bit 2 mask. */ -#define CLK_PSADIV2_bp 4 /* Prescaler A Division Factor bit 2 position. */ -#define CLK_PSADIV3_bm (1<<5) /* Prescaler A Division Factor bit 3 mask. */ -#define CLK_PSADIV3_bp 5 /* Prescaler A Division Factor bit 3 position. */ -#define CLK_PSADIV4_bm (1<<6) /* Prescaler A Division Factor bit 4 mask. */ -#define CLK_PSADIV4_bp 6 /* Prescaler A Division Factor bit 4 position. */ - -#define CLK_PSBCDIV_gm 0x03 /* Prescaler B and C Division factor group mask. */ -#define CLK_PSBCDIV_gp 0 /* Prescaler B and C Division factor group position. */ -#define CLK_PSBCDIV0_bm (1<<0) /* Prescaler B and C Division factor bit 0 mask. */ -#define CLK_PSBCDIV0_bp 0 /* Prescaler B and C Division factor bit 0 position. */ -#define CLK_PSBCDIV1_bm (1<<1) /* Prescaler B and C Division factor bit 1 mask. */ -#define CLK_PSBCDIV1_bp 1 /* Prescaler B and C Division factor bit 1 position. */ - - -/* CLK.LOCK bit masks and bit positions */ -#define CLK_LOCK_bm 0x01 /* Clock System Lock bit mask. */ -#define CLK_LOCK_bp 0 /* Clock System Lock bit position. */ - - -/* CLK.RTCCTRL bit masks and bit positions */ -#define CLK_RTCSRC_gm 0x0E /* Clock Source group mask. */ -#define CLK_RTCSRC_gp 1 /* Clock Source group position. */ -#define CLK_RTCSRC0_bm (1<<1) /* Clock Source bit 0 mask. */ -#define CLK_RTCSRC0_bp 1 /* Clock Source bit 0 position. */ -#define CLK_RTCSRC1_bm (1<<2) /* Clock Source bit 1 mask. */ -#define CLK_RTCSRC1_bp 2 /* Clock Source bit 1 position. */ -#define CLK_RTCSRC2_bm (1<<3) /* Clock Source bit 2 mask. */ -#define CLK_RTCSRC2_bp 3 /* Clock Source bit 2 position. */ - -#define CLK_RTCEN_bm 0x01 /* RTC Clock Source Enable bit mask. */ -#define CLK_RTCEN_bp 0 /* RTC Clock Source Enable bit position. */ - - -/* PR.PRGEN bit masks and bit positions */ -#define PR_AES_bm 0x10 /* AES bit mask. */ -#define PR_AES_bp 4 /* AES bit position. */ - -#define PR_EBI_bm 0x08 /* External Bus Interface bit mask. */ -#define PR_EBI_bp 3 /* External Bus Interface bit position. */ - -#define PR_RTC_bm 0x04 /* Real-time Counter bit mask. */ -#define PR_RTC_bp 2 /* Real-time Counter bit position. */ - -#define PR_EVSYS_bm 0x02 /* Event System bit mask. */ -#define PR_EVSYS_bp 1 /* Event System bit position. */ - -#define PR_DMA_bm 0x01 /* DMA-Controller bit mask. */ -#define PR_DMA_bp 0 /* DMA-Controller bit position. */ - - -/* PR.PRPA bit masks and bit positions */ -#define PR_DAC_bm 0x04 /* Port A DAC bit mask. */ -#define PR_DAC_bp 2 /* Port A DAC bit position. */ - -#define PR_ADC_bm 0x02 /* Port A ADC bit mask. */ -#define PR_ADC_bp 1 /* Port A ADC bit position. */ - -#define PR_AC_bm 0x01 /* Port A Analog Comparator bit mask. */ -#define PR_AC_bp 0 /* Port A Analog Comparator bit position. */ - - -/* PR.PRPB bit masks and bit positions */ -/* PR_DAC_bm Predefined. */ -/* PR_DAC_bp Predefined. */ - -/* PR_ADC_bm Predefined. */ -/* PR_ADC_bp Predefined. */ - -/* PR_AC_bm Predefined. */ -/* PR_AC_bp Predefined. */ - - -/* PR.PRPC bit masks and bit positions */ -#define PR_TWI_bm 0x40 /* Port C Two-wire Interface bit mask. */ -#define PR_TWI_bp 6 /* Port C Two-wire Interface bit position. */ - -#define PR_USART1_bm 0x20 /* Port C USART1 bit mask. */ -#define PR_USART1_bp 5 /* Port C USART1 bit position. */ - -#define PR_USART0_bm 0x10 /* Port C USART0 bit mask. */ -#define PR_USART0_bp 4 /* Port C USART0 bit position. */ - -#define PR_SPI_bm 0x08 /* Port C SPI bit mask. */ -#define PR_SPI_bp 3 /* Port C SPI bit position. */ - -#define PR_HIRES_bm 0x04 /* Port C AWEX bit mask. */ -#define PR_HIRES_bp 2 /* Port C AWEX bit position. */ - -#define PR_TC1_bm 0x02 /* Port C Timer/Counter1 bit mask. */ -#define PR_TC1_bp 1 /* Port C Timer/Counter1 bit position. */ - -#define PR_TC0_bm 0x01 /* Port C Timer/Counter0 bit mask. */ -#define PR_TC0_bp 0 /* Port C Timer/Counter0 bit position. */ - - -/* PR.PRPD bit masks and bit positions */ -/* PR_TWI_bm Predefined. */ -/* PR_TWI_bp Predefined. */ - -/* PR_USART1_bm Predefined. */ -/* PR_USART1_bp Predefined. */ - -/* PR_USART0_bm Predefined. */ -/* PR_USART0_bp Predefined. */ - -/* PR_SPI_bm Predefined. */ -/* PR_SPI_bp Predefined. */ - -/* PR_HIRES_bm Predefined. */ -/* PR_HIRES_bp Predefined. */ - -/* PR_TC1_bm Predefined. */ -/* PR_TC1_bp Predefined. */ - -/* PR_TC0_bm Predefined. */ -/* PR_TC0_bp Predefined. */ - - -/* PR.PRPE bit masks and bit positions */ -/* PR_TWI_bm Predefined. */ -/* PR_TWI_bp Predefined. */ - -/* PR_USART1_bm Predefined. */ -/* PR_USART1_bp Predefined. */ - -/* PR_USART0_bm Predefined. */ -/* PR_USART0_bp Predefined. */ - -/* PR_SPI_bm Predefined. */ -/* PR_SPI_bp Predefined. */ - -/* PR_HIRES_bm Predefined. */ -/* PR_HIRES_bp Predefined. */ - -/* PR_TC1_bm Predefined. */ -/* PR_TC1_bp Predefined. */ - -/* PR_TC0_bm Predefined. */ -/* PR_TC0_bp Predefined. */ - - -/* PR.PRPF bit masks and bit positions */ -/* PR_TWI_bm Predefined. */ -/* PR_TWI_bp Predefined. */ - -/* PR_USART1_bm Predefined. */ -/* PR_USART1_bp Predefined. */ - -/* PR_USART0_bm Predefined. */ -/* PR_USART0_bp Predefined. */ - -/* PR_SPI_bm Predefined. */ -/* PR_SPI_bp Predefined. */ - -/* PR_HIRES_bm Predefined. */ -/* PR_HIRES_bp Predefined. */ - -/* PR_TC1_bm Predefined. */ -/* PR_TC1_bp Predefined. */ - -/* PR_TC0_bm Predefined. */ -/* PR_TC0_bp Predefined. */ - - -/* SLEEP - Sleep Controller */ -/* SLEEP.CTRL bit masks and bit positions */ -#define SLEEP_SMODE_gm 0x0E /* Sleep Mode group mask. */ -#define SLEEP_SMODE_gp 1 /* Sleep Mode group position. */ -#define SLEEP_SMODE0_bm (1<<1) /* Sleep Mode bit 0 mask. */ -#define SLEEP_SMODE0_bp 1 /* Sleep Mode bit 0 position. */ -#define SLEEP_SMODE1_bm (1<<2) /* Sleep Mode bit 1 mask. */ -#define SLEEP_SMODE1_bp 2 /* Sleep Mode bit 1 position. */ -#define SLEEP_SMODE2_bm (1<<3) /* Sleep Mode bit 2 mask. */ -#define SLEEP_SMODE2_bp 3 /* Sleep Mode bit 2 position. */ - -#define SLEEP_SEN_bm 0x01 /* Sleep Enable bit mask. */ -#define SLEEP_SEN_bp 0 /* Sleep Enable bit position. */ - - -/* OSC - Oscillator */ -/* OSC.CTRL bit masks and bit positions */ -#define OSC_PLLEN_bm 0x10 /* PLL Enable bit mask. */ -#define OSC_PLLEN_bp 4 /* PLL Enable bit position. */ - -#define OSC_XOSCEN_bm 0x08 /* External Oscillator Enable bit mask. */ -#define OSC_XOSCEN_bp 3 /* External Oscillator Enable bit position. */ - -#define OSC_RC32KEN_bm 0x04 /* Internal 32kHz RC Oscillator Enable bit mask. */ -#define OSC_RC32KEN_bp 2 /* Internal 32kHz RC Oscillator Enable bit position. */ - -#define OSC_RC32MEN_bm 0x02 /* Internal 32MHz RC Oscillator Enable bit mask. */ -#define OSC_RC32MEN_bp 1 /* Internal 32MHz RC Oscillator Enable bit position. */ - -#define OSC_RC2MEN_bm 0x01 /* Internal 2MHz RC Oscillator Enable bit mask. */ -#define OSC_RC2MEN_bp 0 /* Internal 2MHz RC Oscillator Enable bit position. */ - - -/* OSC.STATUS bit masks and bit positions */ -#define OSC_PLLRDY_bm 0x10 /* PLL Ready bit mask. */ -#define OSC_PLLRDY_bp 4 /* PLL Ready bit position. */ - -#define OSC_XOSCRDY_bm 0x08 /* External Oscillator Ready bit mask. */ -#define OSC_XOSCRDY_bp 3 /* External Oscillator Ready bit position. */ - -#define OSC_RC32KRDY_bm 0x04 /* Internal 32kHz RC Oscillator Ready bit mask. */ -#define OSC_RC32KRDY_bp 2 /* Internal 32kHz RC Oscillator Ready bit position. */ - -#define OSC_RC32MRDY_bm 0x02 /* Internal 32MHz RC Oscillator Ready bit mask. */ -#define OSC_RC32MRDY_bp 1 /* Internal 32MHz RC Oscillator Ready bit position. */ - -#define OSC_RC2MRDY_bm 0x01 /* Internal 2MHz RC Oscillator Ready bit mask. */ -#define OSC_RC2MRDY_bp 0 /* Internal 2MHz RC Oscillator Ready bit position. */ - - -/* OSC.XOSCCTRL bit masks and bit positions */ -#define OSC_FRQRANGE_gm 0xC0 /* Frequency Range group mask. */ -#define OSC_FRQRANGE_gp 6 /* Frequency Range group position. */ -#define OSC_FRQRANGE0_bm (1<<6) /* Frequency Range bit 0 mask. */ -#define OSC_FRQRANGE0_bp 6 /* Frequency Range bit 0 position. */ -#define OSC_FRQRANGE1_bm (1<<7) /* Frequency Range bit 1 mask. */ -#define OSC_FRQRANGE1_bp 7 /* Frequency Range bit 1 position. */ - -#define OSC_X32KLPM_bm 0x20 /* 32kHz XTAL OSC Low-power Mode bit mask. */ -#define OSC_X32KLPM_bp 5 /* 32kHz XTAL OSC Low-power Mode bit position. */ - -#define OSC_XOSCSEL_gm 0x0F /* External Oscillator Selection and Startup Time group mask. */ -#define OSC_XOSCSEL_gp 0 /* External Oscillator Selection and Startup Time group position. */ -#define OSC_XOSCSEL0_bm (1<<0) /* External Oscillator Selection and Startup Time bit 0 mask. */ -#define OSC_XOSCSEL0_bp 0 /* External Oscillator Selection and Startup Time bit 0 position. */ -#define OSC_XOSCSEL1_bm (1<<1) /* External Oscillator Selection and Startup Time bit 1 mask. */ -#define OSC_XOSCSEL1_bp 1 /* External Oscillator Selection and Startup Time bit 1 position. */ -#define OSC_XOSCSEL2_bm (1<<2) /* External Oscillator Selection and Startup Time bit 2 mask. */ -#define OSC_XOSCSEL2_bp 2 /* External Oscillator Selection and Startup Time bit 2 position. */ -#define OSC_XOSCSEL3_bm (1<<3) /* External Oscillator Selection and Startup Time bit 3 mask. */ -#define OSC_XOSCSEL3_bp 3 /* External Oscillator Selection and Startup Time bit 3 position. */ - - -/* OSC.XOSCFAIL bit masks and bit positions */ -#define OSC_XOSCFDIF_bm 0x02 /* Failure Detection Interrupt Flag bit mask. */ -#define OSC_XOSCFDIF_bp 1 /* Failure Detection Interrupt Flag bit position. */ - -#define OSC_XOSCFDEN_bm 0x01 /* Failure Detection Enable bit mask. */ -#define OSC_XOSCFDEN_bp 0 /* Failure Detection Enable bit position. */ - - -/* OSC.PLLCTRL bit masks and bit positions */ -#define OSC_PLLSRC_gm 0xC0 /* Clock Source group mask. */ -#define OSC_PLLSRC_gp 6 /* Clock Source group position. */ -#define OSC_PLLSRC0_bm (1<<6) /* Clock Source bit 0 mask. */ -#define OSC_PLLSRC0_bp 6 /* Clock Source bit 0 position. */ -#define OSC_PLLSRC1_bm (1<<7) /* Clock Source bit 1 mask. */ -#define OSC_PLLSRC1_bp 7 /* Clock Source bit 1 position. */ - -#define OSC_PLLFAC_gm 0x1F /* Multiplication Factor group mask. */ -#define OSC_PLLFAC_gp 0 /* Multiplication Factor group position. */ -#define OSC_PLLFAC0_bm (1<<0) /* Multiplication Factor bit 0 mask. */ -#define OSC_PLLFAC0_bp 0 /* Multiplication Factor bit 0 position. */ -#define OSC_PLLFAC1_bm (1<<1) /* Multiplication Factor bit 1 mask. */ -#define OSC_PLLFAC1_bp 1 /* Multiplication Factor bit 1 position. */ -#define OSC_PLLFAC2_bm (1<<2) /* Multiplication Factor bit 2 mask. */ -#define OSC_PLLFAC2_bp 2 /* Multiplication Factor bit 2 position. */ -#define OSC_PLLFAC3_bm (1<<3) /* Multiplication Factor bit 3 mask. */ -#define OSC_PLLFAC3_bp 3 /* Multiplication Factor bit 3 position. */ -#define OSC_PLLFAC4_bm (1<<4) /* Multiplication Factor bit 4 mask. */ -#define OSC_PLLFAC4_bp 4 /* Multiplication Factor bit 4 position. */ - - -/* OSC.DFLLCTRL bit masks and bit positions */ -#define OSC_RC32MCREF_bm 0x02 /* 32MHz Calibration Reference bit mask. */ -#define OSC_RC32MCREF_bp 1 /* 32MHz Calibration Reference bit position. */ - -#define OSC_RC2MCREF_bm 0x01 /* 2MHz Calibration Reference bit mask. */ -#define OSC_RC2MCREF_bp 0 /* 2MHz Calibration Reference bit position. */ - - -/* DFLL - DFLL */ -/* DFLL.CTRL bit masks and bit positions */ -#define DFLL_ENABLE_bm 0x01 /* DFLL Enable bit mask. */ -#define DFLL_ENABLE_bp 0 /* DFLL Enable bit position. */ - - -/* DFLL.CALA bit masks and bit positions */ -#define DFLL_CALL_gm 0x7F /* DFLL Calibration bits [6:0] group mask. */ -#define DFLL_CALL_gp 0 /* DFLL Calibration bits [6:0] group position. */ -#define DFLL_CALL0_bm (1<<0) /* DFLL Calibration bits [6:0] bit 0 mask. */ -#define DFLL_CALL0_bp 0 /* DFLL Calibration bits [6:0] bit 0 position. */ -#define DFLL_CALL1_bm (1<<1) /* DFLL Calibration bits [6:0] bit 1 mask. */ -#define DFLL_CALL1_bp 1 /* DFLL Calibration bits [6:0] bit 1 position. */ -#define DFLL_CALL2_bm (1<<2) /* DFLL Calibration bits [6:0] bit 2 mask. */ -#define DFLL_CALL2_bp 2 /* DFLL Calibration bits [6:0] bit 2 position. */ -#define DFLL_CALL3_bm (1<<3) /* DFLL Calibration bits [6:0] bit 3 mask. */ -#define DFLL_CALL3_bp 3 /* DFLL Calibration bits [6:0] bit 3 position. */ -#define DFLL_CALL4_bm (1<<4) /* DFLL Calibration bits [6:0] bit 4 mask. */ -#define DFLL_CALL4_bp 4 /* DFLL Calibration bits [6:0] bit 4 position. */ -#define DFLL_CALL5_bm (1<<5) /* DFLL Calibration bits [6:0] bit 5 mask. */ -#define DFLL_CALL5_bp 5 /* DFLL Calibration bits [6:0] bit 5 position. */ -#define DFLL_CALL6_bm (1<<6) /* DFLL Calibration bits [6:0] bit 6 mask. */ -#define DFLL_CALL6_bp 6 /* DFLL Calibration bits [6:0] bit 6 position. */ - - -/* DFLL.CALB bit masks and bit positions */ -#define DFLL_CALH_gm 0x3F /* DFLL Calibration bits [12:7] group mask. */ -#define DFLL_CALH_gp 0 /* DFLL Calibration bits [12:7] group position. */ -#define DFLL_CALH0_bm (1<<0) /* DFLL Calibration bits [12:7] bit 0 mask. */ -#define DFLL_CALH0_bp 0 /* DFLL Calibration bits [12:7] bit 0 position. */ -#define DFLL_CALH1_bm (1<<1) /* DFLL Calibration bits [12:7] bit 1 mask. */ -#define DFLL_CALH1_bp 1 /* DFLL Calibration bits [12:7] bit 1 position. */ -#define DFLL_CALH2_bm (1<<2) /* DFLL Calibration bits [12:7] bit 2 mask. */ -#define DFLL_CALH2_bp 2 /* DFLL Calibration bits [12:7] bit 2 position. */ -#define DFLL_CALH3_bm (1<<3) /* DFLL Calibration bits [12:7] bit 3 mask. */ -#define DFLL_CALH3_bp 3 /* DFLL Calibration bits [12:7] bit 3 position. */ -#define DFLL_CALH4_bm (1<<4) /* DFLL Calibration bits [12:7] bit 4 mask. */ -#define DFLL_CALH4_bp 4 /* DFLL Calibration bits [12:7] bit 4 position. */ -#define DFLL_CALH5_bm (1<<5) /* DFLL Calibration bits [12:7] bit 5 mask. */ -#define DFLL_CALH5_bp 5 /* DFLL Calibration bits [12:7] bit 5 position. */ - - -/* RST - Reset */ -/* RST.STATUS bit masks and bit positions */ -#define RST_SDRF_bm 0x40 /* Spike Detection Reset Flag bit mask. */ -#define RST_SDRF_bp 6 /* Spike Detection Reset Flag bit position. */ - -#define RST_SRF_bm 0x20 /* Software Reset Flag bit mask. */ -#define RST_SRF_bp 5 /* Software Reset Flag bit position. */ - -#define RST_PDIRF_bm 0x10 /* Programming and Debug Interface Interface Reset Flag bit mask. */ -#define RST_PDIRF_bp 4 /* Programming and Debug Interface Interface Reset Flag bit position. */ - -#define RST_WDRF_bm 0x08 /* Watchdog Reset Flag bit mask. */ -#define RST_WDRF_bp 3 /* Watchdog Reset Flag bit position. */ - -#define RST_BORF_bm 0x04 /* Brown-out Reset Flag bit mask. */ -#define RST_BORF_bp 2 /* Brown-out Reset Flag bit position. */ - -#define RST_EXTRF_bm 0x02 /* External Reset Flag bit mask. */ -#define RST_EXTRF_bp 1 /* External Reset Flag bit position. */ - -#define RST_PORF_bm 0x01 /* Power-on Reset Flag bit mask. */ -#define RST_PORF_bp 0 /* Power-on Reset Flag bit position. */ - - -/* RST.CTRL bit masks and bit positions */ -#define RST_SWRST_bm 0x01 /* Software Reset bit mask. */ -#define RST_SWRST_bp 0 /* Software Reset bit position. */ - - -/* WDT - Watch-Dog Timer */ -/* WDT.CTRL bit masks and bit positions */ -#define WDT_PER_gm 0x3C /* Period group mask. */ -#define WDT_PER_gp 2 /* Period group position. */ -#define WDT_PER0_bm (1<<2) /* Period bit 0 mask. */ -#define WDT_PER0_bp 2 /* Period bit 0 position. */ -#define WDT_PER1_bm (1<<3) /* Period bit 1 mask. */ -#define WDT_PER1_bp 3 /* Period bit 1 position. */ -#define WDT_PER2_bm (1<<4) /* Period bit 2 mask. */ -#define WDT_PER2_bp 4 /* Period bit 2 position. */ -#define WDT_PER3_bm (1<<5) /* Period bit 3 mask. */ -#define WDT_PER3_bp 5 /* Period bit 3 position. */ - -#define WDT_ENABLE_bm 0x02 /* Enable bit mask. */ -#define WDT_ENABLE_bp 1 /* Enable bit position. */ - -#define WDT_CEN_bm 0x01 /* Change Enable bit mask. */ -#define WDT_CEN_bp 0 /* Change Enable bit position. */ - - -/* WDT.WINCTRL bit masks and bit positions */ -#define WDT_WPER_gm 0x3C /* Windowed Mode Period group mask. */ -#define WDT_WPER_gp 2 /* Windowed Mode Period group position. */ -#define WDT_WPER0_bm (1<<2) /* Windowed Mode Period bit 0 mask. */ -#define WDT_WPER0_bp 2 /* Windowed Mode Period bit 0 position. */ -#define WDT_WPER1_bm (1<<3) /* Windowed Mode Period bit 1 mask. */ -#define WDT_WPER1_bp 3 /* Windowed Mode Period bit 1 position. */ -#define WDT_WPER2_bm (1<<4) /* Windowed Mode Period bit 2 mask. */ -#define WDT_WPER2_bp 4 /* Windowed Mode Period bit 2 position. */ -#define WDT_WPER3_bm (1<<5) /* Windowed Mode Period bit 3 mask. */ -#define WDT_WPER3_bp 5 /* Windowed Mode Period bit 3 position. */ - -#define WDT_WEN_bm 0x02 /* Windowed Mode Enable bit mask. */ -#define WDT_WEN_bp 1 /* Windowed Mode Enable bit position. */ - -#define WDT_WCEN_bm 0x01 /* Windowed Mode Change Enable bit mask. */ -#define WDT_WCEN_bp 0 /* Windowed Mode Change Enable bit position. */ - - -/* WDT.STATUS bit masks and bit positions */ -#define WDT_SYNCBUSY_bm 0x01 /* Syncronization busy bit mask. */ -#define WDT_SYNCBUSY_bp 0 /* Syncronization busy bit position. */ - - -/* MCU - MCU Control */ -/* MCU.MCUCR bit masks and bit positions */ -#define MCU_JTAGD_bm 0x01 /* JTAG Disable bit mask. */ -#define MCU_JTAGD_bp 0 /* JTAG Disable bit position. */ - - -/* MCU.EVSYSLOCK bit masks and bit positions */ -#define MCU_EVSYS1LOCK_bm 0x10 /* Event Channel 4-7 Lock bit mask. */ -#define MCU_EVSYS1LOCK_bp 4 /* Event Channel 4-7 Lock bit position. */ - -#define MCU_EVSYS0LOCK_bm 0x01 /* Event Channel 0-3 Lock bit mask. */ -#define MCU_EVSYS0LOCK_bp 0 /* Event Channel 0-3 Lock bit position. */ - - -/* MCU.AWEXLOCK bit masks and bit positions */ -#define MCU_AWEXELOCK_bm 0x04 /* AWeX on T/C E0 Lock bit mask. */ -#define MCU_AWEXELOCK_bp 2 /* AWeX on T/C E0 Lock bit position. */ - -#define MCU_AWEXCLOCK_bm 0x01 /* AWeX on T/C C0 Lock bit mask. */ -#define MCU_AWEXCLOCK_bp 0 /* AWeX on T/C C0 Lock bit position. */ - - -/* PMIC - Programmable Multi-level Interrupt Controller */ -/* PMIC.STATUS bit masks and bit positions */ -#define PMIC_NMIEX_bm 0x80 /* Non-maskable Interrupt Executing bit mask. */ -#define PMIC_NMIEX_bp 7 /* Non-maskable Interrupt Executing bit position. */ - -#define PMIC_HILVLEX_bm 0x04 /* High Level Interrupt Executing bit mask. */ -#define PMIC_HILVLEX_bp 2 /* High Level Interrupt Executing bit position. */ - -#define PMIC_MEDLVLEX_bm 0x02 /* Medium Level Interrupt Executing bit mask. */ -#define PMIC_MEDLVLEX_bp 1 /* Medium Level Interrupt Executing bit position. */ - -#define PMIC_LOLVLEX_bm 0x01 /* Low Level Interrupt Executing bit mask. */ -#define PMIC_LOLVLEX_bp 0 /* Low Level Interrupt Executing bit position. */ - - -/* PMIC.CTRL bit masks and bit positions */ -#define PMIC_RREN_bm 0x80 /* Round-Robin Priority Enable bit mask. */ -#define PMIC_RREN_bp 7 /* Round-Robin Priority Enable bit position. */ - -#define PMIC_IVSEL_bm 0x40 /* Interrupt Vector Select bit mask. */ -#define PMIC_IVSEL_bp 6 /* Interrupt Vector Select bit position. */ - -#define PMIC_HILVLEN_bm 0x04 /* High Level Enable bit mask. */ -#define PMIC_HILVLEN_bp 2 /* High Level Enable bit position. */ - -#define PMIC_MEDLVLEN_bm 0x02 /* Medium Level Enable bit mask. */ -#define PMIC_MEDLVLEN_bp 1 /* Medium Level Enable bit position. */ - -#define PMIC_LOLVLEN_bm 0x01 /* Low Level Enable bit mask. */ -#define PMIC_LOLVLEN_bp 0 /* Low Level Enable bit position. */ - - -/* DMA - DMA Controller */ -/* DMA_CH.CTRLA bit masks and bit positions */ -#define DMA_CH_ENABLE_bm 0x80 /* Channel Enable bit mask. */ -#define DMA_CH_ENABLE_bp 7 /* Channel Enable bit position. */ - -#define DMA_CH_RESET_bm 0x40 /* Channel Software Reset bit mask. */ -#define DMA_CH_RESET_bp 6 /* Channel Software Reset bit position. */ - -#define DMA_CH_REPEAT_bm 0x20 /* Channel Repeat Mode bit mask. */ -#define DMA_CH_REPEAT_bp 5 /* Channel Repeat Mode bit position. */ - -#define DMA_CH_TRFREQ_bm 0x10 /* Channel Transfer Request bit mask. */ -#define DMA_CH_TRFREQ_bp 4 /* Channel Transfer Request bit position. */ - -#define DMA_CH_SINGLE_bm 0x04 /* Channel Single Shot Data Transfer bit mask. */ -#define DMA_CH_SINGLE_bp 2 /* Channel Single Shot Data Transfer bit position. */ - -#define DMA_CH_BURSTLEN_gm 0x03 /* Channel Transfer Mode group mask. */ -#define DMA_CH_BURSTLEN_gp 0 /* Channel Transfer Mode group position. */ -#define DMA_CH_BURSTLEN0_bm (1<<0) /* Channel Transfer Mode bit 0 mask. */ -#define DMA_CH_BURSTLEN0_bp 0 /* Channel Transfer Mode bit 0 position. */ -#define DMA_CH_BURSTLEN1_bm (1<<1) /* Channel Transfer Mode bit 1 mask. */ -#define DMA_CH_BURSTLEN1_bp 1 /* Channel Transfer Mode bit 1 position. */ - - -/* DMA_CH.CTRLB bit masks and bit positions */ -#define DMA_CH_CHBUSY_bm 0x80 /* Block Transfer Busy bit mask. */ -#define DMA_CH_CHBUSY_bp 7 /* Block Transfer Busy bit position. */ - -#define DMA_CH_CHPEND_bm 0x40 /* Block Transfer Pending bit mask. */ -#define DMA_CH_CHPEND_bp 6 /* Block Transfer Pending bit position. */ - -#define DMA_CH_ERRIF_bm 0x20 /* Block Transfer Error Interrupt Flag bit mask. */ -#define DMA_CH_ERRIF_bp 5 /* Block Transfer Error Interrupt Flag bit position. */ - -#define DMA_CH_TRNIF_bm 0x10 /* Transaction Complete Interrup Flag bit mask. */ -#define DMA_CH_TRNIF_bp 4 /* Transaction Complete Interrup Flag bit position. */ - -#define DMA_CH_ERRINTLVL_gm 0x0C /* Transfer Error Interrupt Level group mask. */ -#define DMA_CH_ERRINTLVL_gp 2 /* Transfer Error Interrupt Level group position. */ -#define DMA_CH_ERRINTLVL0_bm (1<<2) /* Transfer Error Interrupt Level bit 0 mask. */ -#define DMA_CH_ERRINTLVL0_bp 2 /* Transfer Error Interrupt Level bit 0 position. */ -#define DMA_CH_ERRINTLVL1_bm (1<<3) /* Transfer Error Interrupt Level bit 1 mask. */ -#define DMA_CH_ERRINTLVL1_bp 3 /* Transfer Error Interrupt Level bit 1 position. */ - -#define DMA_CH_TRNINTLVL_gm 0x03 /* Transaction Complete Interrupt Level group mask. */ -#define DMA_CH_TRNINTLVL_gp 0 /* Transaction Complete Interrupt Level group position. */ -#define DMA_CH_TRNINTLVL0_bm (1<<0) /* Transaction Complete Interrupt Level bit 0 mask. */ -#define DMA_CH_TRNINTLVL0_bp 0 /* Transaction Complete Interrupt Level bit 0 position. */ -#define DMA_CH_TRNINTLVL1_bm (1<<1) /* Transaction Complete Interrupt Level bit 1 mask. */ -#define DMA_CH_TRNINTLVL1_bp 1 /* Transaction Complete Interrupt Level bit 1 position. */ - - -/* DMA_CH.ADDRCTRL bit masks and bit positions */ -#define DMA_CH_SRCRELOAD_gm 0xC0 /* Channel Source Address Reload group mask. */ -#define DMA_CH_SRCRELOAD_gp 6 /* Channel Source Address Reload group position. */ -#define DMA_CH_SRCRELOAD0_bm (1<<6) /* Channel Source Address Reload bit 0 mask. */ -#define DMA_CH_SRCRELOAD0_bp 6 /* Channel Source Address Reload bit 0 position. */ -#define DMA_CH_SRCRELOAD1_bm (1<<7) /* Channel Source Address Reload bit 1 mask. */ -#define DMA_CH_SRCRELOAD1_bp 7 /* Channel Source Address Reload bit 1 position. */ - -#define DMA_CH_SRCDIR_gm 0x30 /* Channel Source Address Mode group mask. */ -#define DMA_CH_SRCDIR_gp 4 /* Channel Source Address Mode group position. */ -#define DMA_CH_SRCDIR0_bm (1<<4) /* Channel Source Address Mode bit 0 mask. */ -#define DMA_CH_SRCDIR0_bp 4 /* Channel Source Address Mode bit 0 position. */ -#define DMA_CH_SRCDIR1_bm (1<<5) /* Channel Source Address Mode bit 1 mask. */ -#define DMA_CH_SRCDIR1_bp 5 /* Channel Source Address Mode bit 1 position. */ - -#define DMA_CH_DESTRELOAD_gm 0x0C /* Channel Destination Address Reload group mask. */ -#define DMA_CH_DESTRELOAD_gp 2 /* Channel Destination Address Reload group position. */ -#define DMA_CH_DESTRELOAD0_bm (1<<2) /* Channel Destination Address Reload bit 0 mask. */ -#define DMA_CH_DESTRELOAD0_bp 2 /* Channel Destination Address Reload bit 0 position. */ -#define DMA_CH_DESTRELOAD1_bm (1<<3) /* Channel Destination Address Reload bit 1 mask. */ -#define DMA_CH_DESTRELOAD1_bp 3 /* Channel Destination Address Reload bit 1 position. */ - -#define DMA_CH_DESTDIR_gm 0x03 /* Channel Destination Address Mode group mask. */ -#define DMA_CH_DESTDIR_gp 0 /* Channel Destination Address Mode group position. */ -#define DMA_CH_DESTDIR0_bm (1<<0) /* Channel Destination Address Mode bit 0 mask. */ -#define DMA_CH_DESTDIR0_bp 0 /* Channel Destination Address Mode bit 0 position. */ -#define DMA_CH_DESTDIR1_bm (1<<1) /* Channel Destination Address Mode bit 1 mask. */ -#define DMA_CH_DESTDIR1_bp 1 /* Channel Destination Address Mode bit 1 position. */ - - -/* DMA_CH.TRIGSRC bit masks and bit positions */ -#define DMA_CH_TRIGSRC_gm 0xFF /* Channel Trigger Source group mask. */ -#define DMA_CH_TRIGSRC_gp 0 /* Channel Trigger Source group position. */ -#define DMA_CH_TRIGSRC0_bm (1<<0) /* Channel Trigger Source bit 0 mask. */ -#define DMA_CH_TRIGSRC0_bp 0 /* Channel Trigger Source bit 0 position. */ -#define DMA_CH_TRIGSRC1_bm (1<<1) /* Channel Trigger Source bit 1 mask. */ -#define DMA_CH_TRIGSRC1_bp 1 /* Channel Trigger Source bit 1 position. */ -#define DMA_CH_TRIGSRC2_bm (1<<2) /* Channel Trigger Source bit 2 mask. */ -#define DMA_CH_TRIGSRC2_bp 2 /* Channel Trigger Source bit 2 position. */ -#define DMA_CH_TRIGSRC3_bm (1<<3) /* Channel Trigger Source bit 3 mask. */ -#define DMA_CH_TRIGSRC3_bp 3 /* Channel Trigger Source bit 3 position. */ -#define DMA_CH_TRIGSRC4_bm (1<<4) /* Channel Trigger Source bit 4 mask. */ -#define DMA_CH_TRIGSRC4_bp 4 /* Channel Trigger Source bit 4 position. */ -#define DMA_CH_TRIGSRC5_bm (1<<5) /* Channel Trigger Source bit 5 mask. */ -#define DMA_CH_TRIGSRC5_bp 5 /* Channel Trigger Source bit 5 position. */ -#define DMA_CH_TRIGSRC6_bm (1<<6) /* Channel Trigger Source bit 6 mask. */ -#define DMA_CH_TRIGSRC6_bp 6 /* Channel Trigger Source bit 6 position. */ -#define DMA_CH_TRIGSRC7_bm (1<<7) /* Channel Trigger Source bit 7 mask. */ -#define DMA_CH_TRIGSRC7_bp 7 /* Channel Trigger Source bit 7 position. */ - - -/* DMA.CTRL bit masks and bit positions */ -#define DMA_ENABLE_bm 0x80 /* Enable bit mask. */ -#define DMA_ENABLE_bp 7 /* Enable bit position. */ - -#define DMA_RESET_bm 0x40 /* Software Reset bit mask. */ -#define DMA_RESET_bp 6 /* Software Reset bit position. */ - -#define DMA_DBUFMODE_gm 0x0C /* Double Buffering Mode group mask. */ -#define DMA_DBUFMODE_gp 2 /* Double Buffering Mode group position. */ -#define DMA_DBUFMODE0_bm (1<<2) /* Double Buffering Mode bit 0 mask. */ -#define DMA_DBUFMODE0_bp 2 /* Double Buffering Mode bit 0 position. */ -#define DMA_DBUFMODE1_bm (1<<3) /* Double Buffering Mode bit 1 mask. */ -#define DMA_DBUFMODE1_bp 3 /* Double Buffering Mode bit 1 position. */ - -#define DMA_PRIMODE_gm 0x03 /* Channel Priority Mode group mask. */ -#define DMA_PRIMODE_gp 0 /* Channel Priority Mode group position. */ -#define DMA_PRIMODE0_bm (1<<0) /* Channel Priority Mode bit 0 mask. */ -#define DMA_PRIMODE0_bp 0 /* Channel Priority Mode bit 0 position. */ -#define DMA_PRIMODE1_bm (1<<1) /* Channel Priority Mode bit 1 mask. */ -#define DMA_PRIMODE1_bp 1 /* Channel Priority Mode bit 1 position. */ - - -/* DMA.INTFLAGS bit masks and bit positions */ -#define DMA_CH3ERRIF_bm 0x80 /* Channel 3 Block Transfer Error Interrupt Flag bit mask. */ -#define DMA_CH3ERRIF_bp 7 /* Channel 3 Block Transfer Error Interrupt Flag bit position. */ - -#define DMA_CH2ERRIF_bm 0x40 /* Channel 2 Block Transfer Error Interrupt Flag bit mask. */ -#define DMA_CH2ERRIF_bp 6 /* Channel 2 Block Transfer Error Interrupt Flag bit position. */ - -#define DMA_CH1ERRIF_bm 0x20 /* Channel 1 Block Transfer Error Interrupt Flag bit mask. */ -#define DMA_CH1ERRIF_bp 5 /* Channel 1 Block Transfer Error Interrupt Flag bit position. */ - -#define DMA_CH0ERRIF_bm 0x10 /* Channel 0 Block Transfer Error Interrupt Flag bit mask. */ -#define DMA_CH0ERRIF_bp 4 /* Channel 0 Block Transfer Error Interrupt Flag bit position. */ - -#define DMA_CH3TRNIF_bm 0x08 /* Channel 3 Transaction Complete Interrupt Flag bit mask. */ -#define DMA_CH3TRNIF_bp 3 /* Channel 3 Transaction Complete Interrupt Flag bit position. */ - -#define DMA_CH2TRNIF_bm 0x04 /* Channel 2 Transaction Complete Interrupt Flag bit mask. */ -#define DMA_CH2TRNIF_bp 2 /* Channel 2 Transaction Complete Interrupt Flag bit position. */ - -#define DMA_CH1TRNIF_bm 0x02 /* Channel 1 Transaction Complete Interrupt Flag bit mask. */ -#define DMA_CH1TRNIF_bp 1 /* Channel 1 Transaction Complete Interrupt Flag bit position. */ - -#define DMA_CH0TRNIF_bm 0x01 /* Channel 0 Transaction Complete Interrupt Flag bit mask. */ -#define DMA_CH0TRNIF_bp 0 /* Channel 0 Transaction Complete Interrupt Flag bit position. */ - - -/* DMA.STATUS bit masks and bit positions */ -#define DMA_CH3BUSY_bm 0x80 /* Channel 3 Block Transfer Busy bit mask. */ -#define DMA_CH3BUSY_bp 7 /* Channel 3 Block Transfer Busy bit position. */ - -#define DMA_CH2BUSY_bm 0x40 /* Channel 2 Block Transfer Busy bit mask. */ -#define DMA_CH2BUSY_bp 6 /* Channel 2 Block Transfer Busy bit position. */ - -#define DMA_CH1BUSY_bm 0x20 /* Channel 1 Block Transfer Busy bit mask. */ -#define DMA_CH1BUSY_bp 5 /* Channel 1 Block Transfer Busy bit position. */ - -#define DMA_CH0BUSY_bm 0x10 /* Channel 0 Block Transfer Busy bit mask. */ -#define DMA_CH0BUSY_bp 4 /* Channel 0 Block Transfer Busy bit position. */ - -#define DMA_CH3PEND_bm 0x08 /* Channel 3 Block Transfer Pending bit mask. */ -#define DMA_CH3PEND_bp 3 /* Channel 3 Block Transfer Pending bit position. */ - -#define DMA_CH2PEND_bm 0x04 /* Channel 2 Block Transfer Pending bit mask. */ -#define DMA_CH2PEND_bp 2 /* Channel 2 Block Transfer Pending bit position. */ - -#define DMA_CH1PEND_bm 0x02 /* Channel 1 Block Transfer Pending bit mask. */ -#define DMA_CH1PEND_bp 1 /* Channel 1 Block Transfer Pending bit position. */ - -#define DMA_CH0PEND_bm 0x01 /* Channel 0 Block Transfer Pending bit mask. */ -#define DMA_CH0PEND_bp 0 /* Channel 0 Block Transfer Pending bit position. */ - - -/* EVSYS - Event System */ -/* EVSYS.CH0MUX bit masks and bit positions */ -#define EVSYS_CHMUX_gm 0xFF /* Event Channel 0 Multiplexer group mask. */ -#define EVSYS_CHMUX_gp 0 /* Event Channel 0 Multiplexer group position. */ -#define EVSYS_CHMUX0_bm (1<<0) /* Event Channel 0 Multiplexer bit 0 mask. */ -#define EVSYS_CHMUX0_bp 0 /* Event Channel 0 Multiplexer bit 0 position. */ -#define EVSYS_CHMUX1_bm (1<<1) /* Event Channel 0 Multiplexer bit 1 mask. */ -#define EVSYS_CHMUX1_bp 1 /* Event Channel 0 Multiplexer bit 1 position. */ -#define EVSYS_CHMUX2_bm (1<<2) /* Event Channel 0 Multiplexer bit 2 mask. */ -#define EVSYS_CHMUX2_bp 2 /* Event Channel 0 Multiplexer bit 2 position. */ -#define EVSYS_CHMUX3_bm (1<<3) /* Event Channel 0 Multiplexer bit 3 mask. */ -#define EVSYS_CHMUX3_bp 3 /* Event Channel 0 Multiplexer bit 3 position. */ -#define EVSYS_CHMUX4_bm (1<<4) /* Event Channel 0 Multiplexer bit 4 mask. */ -#define EVSYS_CHMUX4_bp 4 /* Event Channel 0 Multiplexer bit 4 position. */ -#define EVSYS_CHMUX5_bm (1<<5) /* Event Channel 0 Multiplexer bit 5 mask. */ -#define EVSYS_CHMUX5_bp 5 /* Event Channel 0 Multiplexer bit 5 position. */ -#define EVSYS_CHMUX6_bm (1<<6) /* Event Channel 0 Multiplexer bit 6 mask. */ -#define EVSYS_CHMUX6_bp 6 /* Event Channel 0 Multiplexer bit 6 position. */ -#define EVSYS_CHMUX7_bm (1<<7) /* Event Channel 0 Multiplexer bit 7 mask. */ -#define EVSYS_CHMUX7_bp 7 /* Event Channel 0 Multiplexer bit 7 position. */ - - -/* EVSYS.CH1MUX bit masks and bit positions */ -/* EVSYS_CHMUX_gm Predefined. */ -/* EVSYS_CHMUX_gp Predefined. */ -/* EVSYS_CHMUX0_bm Predefined. */ -/* EVSYS_CHMUX0_bp Predefined. */ -/* EVSYS_CHMUX1_bm Predefined. */ -/* EVSYS_CHMUX1_bp Predefined. */ -/* EVSYS_CHMUX2_bm Predefined. */ -/* EVSYS_CHMUX2_bp Predefined. */ -/* EVSYS_CHMUX3_bm Predefined. */ -/* EVSYS_CHMUX3_bp Predefined. */ -/* EVSYS_CHMUX4_bm Predefined. */ -/* EVSYS_CHMUX4_bp Predefined. */ -/* EVSYS_CHMUX5_bm Predefined. */ -/* EVSYS_CHMUX5_bp Predefined. */ -/* EVSYS_CHMUX6_bm Predefined. */ -/* EVSYS_CHMUX6_bp Predefined. */ -/* EVSYS_CHMUX7_bm Predefined. */ -/* EVSYS_CHMUX7_bp Predefined. */ - - -/* EVSYS.CH2MUX bit masks and bit positions */ -/* EVSYS_CHMUX_gm Predefined. */ -/* EVSYS_CHMUX_gp Predefined. */ -/* EVSYS_CHMUX0_bm Predefined. */ -/* EVSYS_CHMUX0_bp Predefined. */ -/* EVSYS_CHMUX1_bm Predefined. */ -/* EVSYS_CHMUX1_bp Predefined. */ -/* EVSYS_CHMUX2_bm Predefined. */ -/* EVSYS_CHMUX2_bp Predefined. */ -/* EVSYS_CHMUX3_bm Predefined. */ -/* EVSYS_CHMUX3_bp Predefined. */ -/* EVSYS_CHMUX4_bm Predefined. */ -/* EVSYS_CHMUX4_bp Predefined. */ -/* EVSYS_CHMUX5_bm Predefined. */ -/* EVSYS_CHMUX5_bp Predefined. */ -/* EVSYS_CHMUX6_bm Predefined. */ -/* EVSYS_CHMUX6_bp Predefined. */ -/* EVSYS_CHMUX7_bm Predefined. */ -/* EVSYS_CHMUX7_bp Predefined. */ - - -/* EVSYS.CH3MUX bit masks and bit positions */ -/* EVSYS_CHMUX_gm Predefined. */ -/* EVSYS_CHMUX_gp Predefined. */ -/* EVSYS_CHMUX0_bm Predefined. */ -/* EVSYS_CHMUX0_bp Predefined. */ -/* EVSYS_CHMUX1_bm Predefined. */ -/* EVSYS_CHMUX1_bp Predefined. */ -/* EVSYS_CHMUX2_bm Predefined. */ -/* EVSYS_CHMUX2_bp Predefined. */ -/* EVSYS_CHMUX3_bm Predefined. */ -/* EVSYS_CHMUX3_bp Predefined. */ -/* EVSYS_CHMUX4_bm Predefined. */ -/* EVSYS_CHMUX4_bp Predefined. */ -/* EVSYS_CHMUX5_bm Predefined. */ -/* EVSYS_CHMUX5_bp Predefined. */ -/* EVSYS_CHMUX6_bm Predefined. */ -/* EVSYS_CHMUX6_bp Predefined. */ -/* EVSYS_CHMUX7_bm Predefined. */ -/* EVSYS_CHMUX7_bp Predefined. */ - - -/* EVSYS.CH4MUX bit masks and bit positions */ -/* EVSYS_CHMUX_gm Predefined. */ -/* EVSYS_CHMUX_gp Predefined. */ -/* EVSYS_CHMUX0_bm Predefined. */ -/* EVSYS_CHMUX0_bp Predefined. */ -/* EVSYS_CHMUX1_bm Predefined. */ -/* EVSYS_CHMUX1_bp Predefined. */ -/* EVSYS_CHMUX2_bm Predefined. */ -/* EVSYS_CHMUX2_bp Predefined. */ -/* EVSYS_CHMUX3_bm Predefined. */ -/* EVSYS_CHMUX3_bp Predefined. */ -/* EVSYS_CHMUX4_bm Predefined. */ -/* EVSYS_CHMUX4_bp Predefined. */ -/* EVSYS_CHMUX5_bm Predefined. */ -/* EVSYS_CHMUX5_bp Predefined. */ -/* EVSYS_CHMUX6_bm Predefined. */ -/* EVSYS_CHMUX6_bp Predefined. */ -/* EVSYS_CHMUX7_bm Predefined. */ -/* EVSYS_CHMUX7_bp Predefined. */ - - -/* EVSYS.CH5MUX bit masks and bit positions */ -/* EVSYS_CHMUX_gm Predefined. */ -/* EVSYS_CHMUX_gp Predefined. */ -/* EVSYS_CHMUX0_bm Predefined. */ -/* EVSYS_CHMUX0_bp Predefined. */ -/* EVSYS_CHMUX1_bm Predefined. */ -/* EVSYS_CHMUX1_bp Predefined. */ -/* EVSYS_CHMUX2_bm Predefined. */ -/* EVSYS_CHMUX2_bp Predefined. */ -/* EVSYS_CHMUX3_bm Predefined. */ -/* EVSYS_CHMUX3_bp Predefined. */ -/* EVSYS_CHMUX4_bm Predefined. */ -/* EVSYS_CHMUX4_bp Predefined. */ -/* EVSYS_CHMUX5_bm Predefined. */ -/* EVSYS_CHMUX5_bp Predefined. */ -/* EVSYS_CHMUX6_bm Predefined. */ -/* EVSYS_CHMUX6_bp Predefined. */ -/* EVSYS_CHMUX7_bm Predefined. */ -/* EVSYS_CHMUX7_bp Predefined. */ - - -/* EVSYS.CH6MUX bit masks and bit positions */ -/* EVSYS_CHMUX_gm Predefined. */ -/* EVSYS_CHMUX_gp Predefined. */ -/* EVSYS_CHMUX0_bm Predefined. */ -/* EVSYS_CHMUX0_bp Predefined. */ -/* EVSYS_CHMUX1_bm Predefined. */ -/* EVSYS_CHMUX1_bp Predefined. */ -/* EVSYS_CHMUX2_bm Predefined. */ -/* EVSYS_CHMUX2_bp Predefined. */ -/* EVSYS_CHMUX3_bm Predefined. */ -/* EVSYS_CHMUX3_bp Predefined. */ -/* EVSYS_CHMUX4_bm Predefined. */ -/* EVSYS_CHMUX4_bp Predefined. */ -/* EVSYS_CHMUX5_bm Predefined. */ -/* EVSYS_CHMUX5_bp Predefined. */ -/* EVSYS_CHMUX6_bm Predefined. */ -/* EVSYS_CHMUX6_bp Predefined. */ -/* EVSYS_CHMUX7_bm Predefined. */ -/* EVSYS_CHMUX7_bp Predefined. */ - - -/* EVSYS.CH7MUX bit masks and bit positions */ -/* EVSYS_CHMUX_gm Predefined. */ -/* EVSYS_CHMUX_gp Predefined. */ -/* EVSYS_CHMUX0_bm Predefined. */ -/* EVSYS_CHMUX0_bp Predefined. */ -/* EVSYS_CHMUX1_bm Predefined. */ -/* EVSYS_CHMUX1_bp Predefined. */ -/* EVSYS_CHMUX2_bm Predefined. */ -/* EVSYS_CHMUX2_bp Predefined. */ -/* EVSYS_CHMUX3_bm Predefined. */ -/* EVSYS_CHMUX3_bp Predefined. */ -/* EVSYS_CHMUX4_bm Predefined. */ -/* EVSYS_CHMUX4_bp Predefined. */ -/* EVSYS_CHMUX5_bm Predefined. */ -/* EVSYS_CHMUX5_bp Predefined. */ -/* EVSYS_CHMUX6_bm Predefined. */ -/* EVSYS_CHMUX6_bp Predefined. */ -/* EVSYS_CHMUX7_bm Predefined. */ -/* EVSYS_CHMUX7_bp Predefined. */ - - -/* EVSYS.CH0CTRL bit masks and bit positions */ -#define EVSYS_QDIRM_gm 0x60 /* Quadrature Decoder Index Recognition Mode group mask. */ -#define EVSYS_QDIRM_gp 5 /* Quadrature Decoder Index Recognition Mode group position. */ -#define EVSYS_QDIRM0_bm (1<<5) /* Quadrature Decoder Index Recognition Mode bit 0 mask. */ -#define EVSYS_QDIRM0_bp 5 /* Quadrature Decoder Index Recognition Mode bit 0 position. */ -#define EVSYS_QDIRM1_bm (1<<6) /* Quadrature Decoder Index Recognition Mode bit 1 mask. */ -#define EVSYS_QDIRM1_bp 6 /* Quadrature Decoder Index Recognition Mode bit 1 position. */ - -#define EVSYS_QDIEN_bm 0x10 /* Quadrature Decoder Index Enable bit mask. */ -#define EVSYS_QDIEN_bp 4 /* Quadrature Decoder Index Enable bit position. */ - -#define EVSYS_QDEN_bm 0x08 /* Quadrature Decoder Enable bit mask. */ -#define EVSYS_QDEN_bp 3 /* Quadrature Decoder Enable bit position. */ - -#define EVSYS_DIGFILT_gm 0x07 /* Digital Filter group mask. */ -#define EVSYS_DIGFILT_gp 0 /* Digital Filter group position. */ -#define EVSYS_DIGFILT0_bm (1<<0) /* Digital Filter bit 0 mask. */ -#define EVSYS_DIGFILT0_bp 0 /* Digital Filter bit 0 position. */ -#define EVSYS_DIGFILT1_bm (1<<1) /* Digital Filter bit 1 mask. */ -#define EVSYS_DIGFILT1_bp 1 /* Digital Filter bit 1 position. */ -#define EVSYS_DIGFILT2_bm (1<<2) /* Digital Filter bit 2 mask. */ -#define EVSYS_DIGFILT2_bp 2 /* Digital Filter bit 2 position. */ - - -/* EVSYS.CH1CTRL bit masks and bit positions */ -/* EVSYS_DIGFILT_gm Predefined. */ -/* EVSYS_DIGFILT_gp Predefined. */ -/* EVSYS_DIGFILT0_bm Predefined. */ -/* EVSYS_DIGFILT0_bp Predefined. */ -/* EVSYS_DIGFILT1_bm Predefined. */ -/* EVSYS_DIGFILT1_bp Predefined. */ -/* EVSYS_DIGFILT2_bm Predefined. */ -/* EVSYS_DIGFILT2_bp Predefined. */ - - -/* EVSYS.CH2CTRL bit masks and bit positions */ -/* EVSYS_QDIRM_gm Predefined. */ -/* EVSYS_QDIRM_gp Predefined. */ -/* EVSYS_QDIRM0_bm Predefined. */ -/* EVSYS_QDIRM0_bp Predefined. */ -/* EVSYS_QDIRM1_bm Predefined. */ -/* EVSYS_QDIRM1_bp Predefined. */ - -/* EVSYS_QDIEN_bm Predefined. */ -/* EVSYS_QDIEN_bp Predefined. */ - -/* EVSYS_QDEN_bm Predefined. */ -/* EVSYS_QDEN_bp Predefined. */ - -/* EVSYS_DIGFILT_gm Predefined. */ -/* EVSYS_DIGFILT_gp Predefined. */ -/* EVSYS_DIGFILT0_bm Predefined. */ -/* EVSYS_DIGFILT0_bp Predefined. */ -/* EVSYS_DIGFILT1_bm Predefined. */ -/* EVSYS_DIGFILT1_bp Predefined. */ -/* EVSYS_DIGFILT2_bm Predefined. */ -/* EVSYS_DIGFILT2_bp Predefined. */ - - -/* EVSYS.CH3CTRL bit masks and bit positions */ -/* EVSYS_DIGFILT_gm Predefined. */ -/* EVSYS_DIGFILT_gp Predefined. */ -/* EVSYS_DIGFILT0_bm Predefined. */ -/* EVSYS_DIGFILT0_bp Predefined. */ -/* EVSYS_DIGFILT1_bm Predefined. */ -/* EVSYS_DIGFILT1_bp Predefined. */ -/* EVSYS_DIGFILT2_bm Predefined. */ -/* EVSYS_DIGFILT2_bp Predefined. */ - - -/* EVSYS.CH4CTRL bit masks and bit positions */ -/* EVSYS_QDIRM_gm Predefined. */ -/* EVSYS_QDIRM_gp Predefined. */ -/* EVSYS_QDIRM0_bm Predefined. */ -/* EVSYS_QDIRM0_bp Predefined. */ -/* EVSYS_QDIRM1_bm Predefined. */ -/* EVSYS_QDIRM1_bp Predefined. */ - -/* EVSYS_QDIEN_bm Predefined. */ -/* EVSYS_QDIEN_bp Predefined. */ - -/* EVSYS_QDEN_bm Predefined. */ -/* EVSYS_QDEN_bp Predefined. */ - -/* EVSYS_DIGFILT_gm Predefined. */ -/* EVSYS_DIGFILT_gp Predefined. */ -/* EVSYS_DIGFILT0_bm Predefined. */ -/* EVSYS_DIGFILT0_bp Predefined. */ -/* EVSYS_DIGFILT1_bm Predefined. */ -/* EVSYS_DIGFILT1_bp Predefined. */ -/* EVSYS_DIGFILT2_bm Predefined. */ -/* EVSYS_DIGFILT2_bp Predefined. */ - - -/* EVSYS.CH5CTRL bit masks and bit positions */ -/* EVSYS_DIGFILT_gm Predefined. */ -/* EVSYS_DIGFILT_gp Predefined. */ -/* EVSYS_DIGFILT0_bm Predefined. */ -/* EVSYS_DIGFILT0_bp Predefined. */ -/* EVSYS_DIGFILT1_bm Predefined. */ -/* EVSYS_DIGFILT1_bp Predefined. */ -/* EVSYS_DIGFILT2_bm Predefined. */ -/* EVSYS_DIGFILT2_bp Predefined. */ - - -/* EVSYS.CH6CTRL bit masks and bit positions */ -/* EVSYS_DIGFILT_gm Predefined. */ -/* EVSYS_DIGFILT_gp Predefined. */ -/* EVSYS_DIGFILT0_bm Predefined. */ -/* EVSYS_DIGFILT0_bp Predefined. */ -/* EVSYS_DIGFILT1_bm Predefined. */ -/* EVSYS_DIGFILT1_bp Predefined. */ -/* EVSYS_DIGFILT2_bm Predefined. */ -/* EVSYS_DIGFILT2_bp Predefined. */ - - -/* EVSYS.CH7CTRL bit masks and bit positions */ -/* EVSYS_DIGFILT_gm Predefined. */ -/* EVSYS_DIGFILT_gp Predefined. */ -/* EVSYS_DIGFILT0_bm Predefined. */ -/* EVSYS_DIGFILT0_bp Predefined. */ -/* EVSYS_DIGFILT1_bm Predefined. */ -/* EVSYS_DIGFILT1_bp Predefined. */ -/* EVSYS_DIGFILT2_bm Predefined. */ -/* EVSYS_DIGFILT2_bp Predefined. */ - - -/* NVM - Non Volatile Memory Controller */ -/* NVM.CMD bit masks and bit positions */ -#define NVM_CMD_gm 0xFF /* Command group mask. */ -#define NVM_CMD_gp 0 /* Command group position. */ -#define NVM_CMD0_bm (1<<0) /* Command bit 0 mask. */ -#define NVM_CMD0_bp 0 /* Command bit 0 position. */ -#define NVM_CMD1_bm (1<<1) /* Command bit 1 mask. */ -#define NVM_CMD1_bp 1 /* Command bit 1 position. */ -#define NVM_CMD2_bm (1<<2) /* Command bit 2 mask. */ -#define NVM_CMD2_bp 2 /* Command bit 2 position. */ -#define NVM_CMD3_bm (1<<3) /* Command bit 3 mask. */ -#define NVM_CMD3_bp 3 /* Command bit 3 position. */ -#define NVM_CMD4_bm (1<<4) /* Command bit 4 mask. */ -#define NVM_CMD4_bp 4 /* Command bit 4 position. */ -#define NVM_CMD5_bm (1<<5) /* Command bit 5 mask. */ -#define NVM_CMD5_bp 5 /* Command bit 5 position. */ -#define NVM_CMD6_bm (1<<6) /* Command bit 6 mask. */ -#define NVM_CMD6_bp 6 /* Command bit 6 position. */ -#define NVM_CMD7_bm (1<<7) /* Command bit 7 mask. */ -#define NVM_CMD7_bp 7 /* Command bit 7 position. */ - - -/* NVM.CTRLA bit masks and bit positions */ -#define NVM_CMDEX_bm 0x01 /* Command Execute bit mask. */ -#define NVM_CMDEX_bp 0 /* Command Execute bit position. */ - - -/* NVM.CTRLB bit masks and bit positions */ -#define NVM_EEMAPEN_bm 0x08 /* EEPROM Mapping Enable bit mask. */ -#define NVM_EEMAPEN_bp 3 /* EEPROM Mapping Enable bit position. */ - -#define NVM_FPRM_bm 0x04 /* Flash Power Reduction Enable bit mask. */ -#define NVM_FPRM_bp 2 /* Flash Power Reduction Enable bit position. */ - -#define NVM_EPRM_bm 0x02 /* EEPROM Power Reduction Enable bit mask. */ -#define NVM_EPRM_bp 1 /* EEPROM Power Reduction Enable bit position. */ - -#define NVM_SPMLOCK_bm 0x01 /* SPM Lock bit mask. */ -#define NVM_SPMLOCK_bp 0 /* SPM Lock bit position. */ - - -/* NVM.INTCTRL bit masks and bit positions */ -#define NVM_SPMLVL_gm 0x0C /* SPM Interrupt Level group mask. */ -#define NVM_SPMLVL_gp 2 /* SPM Interrupt Level group position. */ -#define NVM_SPMLVL0_bm (1<<2) /* SPM Interrupt Level bit 0 mask. */ -#define NVM_SPMLVL0_bp 2 /* SPM Interrupt Level bit 0 position. */ -#define NVM_SPMLVL1_bm (1<<3) /* SPM Interrupt Level bit 1 mask. */ -#define NVM_SPMLVL1_bp 3 /* SPM Interrupt Level bit 1 position. */ - -#define NVM_EELVL_gm 0x03 /* EEPROM Interrupt Level group mask. */ -#define NVM_EELVL_gp 0 /* EEPROM Interrupt Level group position. */ -#define NVM_EELVL0_bm (1<<0) /* EEPROM Interrupt Level bit 0 mask. */ -#define NVM_EELVL0_bp 0 /* EEPROM Interrupt Level bit 0 position. */ -#define NVM_EELVL1_bm (1<<1) /* EEPROM Interrupt Level bit 1 mask. */ -#define NVM_EELVL1_bp 1 /* EEPROM Interrupt Level bit 1 position. */ - - -/* NVM.STATUS bit masks and bit positions */ -#define NVM_NVMBUSY_bm 0x80 /* Non-volatile Memory Busy bit mask. */ -#define NVM_NVMBUSY_bp 7 /* Non-volatile Memory Busy bit position. */ - -#define NVM_FBUSY_bm 0x40 /* Flash Memory Busy bit mask. */ -#define NVM_FBUSY_bp 6 /* Flash Memory Busy bit position. */ - -#define NVM_EELOAD_bm 0x02 /* EEPROM Page Buffer Active Loading bit mask. */ -#define NVM_EELOAD_bp 1 /* EEPROM Page Buffer Active Loading bit position. */ - -#define NVM_FLOAD_bm 0x01 /* Flash Page Buffer Active Loading bit mask. */ -#define NVM_FLOAD_bp 0 /* Flash Page Buffer Active Loading bit position. */ - - -/* NVM.LOCKBITS bit masks and bit positions */ -#define NVM_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ -#define NVM_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ -#define NVM_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ -#define NVM_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ -#define NVM_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ -#define NVM_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ - -#define NVM_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ -#define NVM_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ -#define NVM_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ -#define NVM_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ -#define NVM_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ -#define NVM_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ - -#define NVM_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ -#define NVM_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ -#define NVM_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ -#define NVM_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ -#define NVM_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ -#define NVM_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ - -#define NVM_LB_gm 0x03 /* Lock Bits group mask. */ -#define NVM_LB_gp 0 /* Lock Bits group position. */ -#define NVM_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ -#define NVM_LB0_bp 0 /* Lock Bits bit 0 position. */ -#define NVM_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ -#define NVM_LB1_bp 1 /* Lock Bits bit 1 position. */ - - -/* NVM_LOCKBITS.LOCKBITS bit masks and bit positions */ -#define NVM_LOCKBITS_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ -#define NVM_LOCKBITS_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ -#define NVM_LOCKBITS_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ -#define NVM_LOCKBITS_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ -#define NVM_LOCKBITS_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ -#define NVM_LOCKBITS_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ - -#define NVM_LOCKBITS_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ -#define NVM_LOCKBITS_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ -#define NVM_LOCKBITS_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ -#define NVM_LOCKBITS_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ -#define NVM_LOCKBITS_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ -#define NVM_LOCKBITS_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ - -#define NVM_LOCKBITS_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ -#define NVM_LOCKBITS_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ -#define NVM_LOCKBITS_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ -#define NVM_LOCKBITS_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ -#define NVM_LOCKBITS_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ -#define NVM_LOCKBITS_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ - -#define NVM_LOCKBITS_LB_gm 0x03 /* Lock Bits group mask. */ -#define NVM_LOCKBITS_LB_gp 0 /* Lock Bits group position. */ -#define NVM_LOCKBITS_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ -#define NVM_LOCKBITS_LB0_bp 0 /* Lock Bits bit 0 position. */ -#define NVM_LOCKBITS_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ -#define NVM_LOCKBITS_LB1_bp 1 /* Lock Bits bit 1 position. */ - - -/* NVM_FUSES.FUSEBYTE0 bit masks and bit positions */ -#define NVM_FUSES_JTAGUSERID_gm 0xFF /* JTAG User ID group mask. */ -#define NVM_FUSES_JTAGUSERID_gp 0 /* JTAG User ID group position. */ -#define NVM_FUSES_JTAGUSERID0_bm (1<<0) /* JTAG User ID bit 0 mask. */ -#define NVM_FUSES_JTAGUSERID0_bp 0 /* JTAG User ID bit 0 position. */ -#define NVM_FUSES_JTAGUSERID1_bm (1<<1) /* JTAG User ID bit 1 mask. */ -#define NVM_FUSES_JTAGUSERID1_bp 1 /* JTAG User ID bit 1 position. */ -#define NVM_FUSES_JTAGUSERID2_bm (1<<2) /* JTAG User ID bit 2 mask. */ -#define NVM_FUSES_JTAGUSERID2_bp 2 /* JTAG User ID bit 2 position. */ -#define NVM_FUSES_JTAGUSERID3_bm (1<<3) /* JTAG User ID bit 3 mask. */ -#define NVM_FUSES_JTAGUSERID3_bp 3 /* JTAG User ID bit 3 position. */ -#define NVM_FUSES_JTAGUSERID4_bm (1<<4) /* JTAG User ID bit 4 mask. */ -#define NVM_FUSES_JTAGUSERID4_bp 4 /* JTAG User ID bit 4 position. */ -#define NVM_FUSES_JTAGUSERID5_bm (1<<5) /* JTAG User ID bit 5 mask. */ -#define NVM_FUSES_JTAGUSERID5_bp 5 /* JTAG User ID bit 5 position. */ -#define NVM_FUSES_JTAGUSERID6_bm (1<<6) /* JTAG User ID bit 6 mask. */ -#define NVM_FUSES_JTAGUSERID6_bp 6 /* JTAG User ID bit 6 position. */ -#define NVM_FUSES_JTAGUSERID7_bm (1<<7) /* JTAG User ID bit 7 mask. */ -#define NVM_FUSES_JTAGUSERID7_bp 7 /* JTAG User ID bit 7 position. */ - - -/* NVM_FUSES.FUSEBYTE1 bit masks and bit positions */ -#define NVM_FUSES_WDWP_gm 0xF0 /* Watchdog Window Timeout Period group mask. */ -#define NVM_FUSES_WDWP_gp 4 /* Watchdog Window Timeout Period group position. */ -#define NVM_FUSES_WDWP0_bm (1<<4) /* Watchdog Window Timeout Period bit 0 mask. */ -#define NVM_FUSES_WDWP0_bp 4 /* Watchdog Window Timeout Period bit 0 position. */ -#define NVM_FUSES_WDWP1_bm (1<<5) /* Watchdog Window Timeout Period bit 1 mask. */ -#define NVM_FUSES_WDWP1_bp 5 /* Watchdog Window Timeout Period bit 1 position. */ -#define NVM_FUSES_WDWP2_bm (1<<6) /* Watchdog Window Timeout Period bit 2 mask. */ -#define NVM_FUSES_WDWP2_bp 6 /* Watchdog Window Timeout Period bit 2 position. */ -#define NVM_FUSES_WDWP3_bm (1<<7) /* Watchdog Window Timeout Period bit 3 mask. */ -#define NVM_FUSES_WDWP3_bp 7 /* Watchdog Window Timeout Period bit 3 position. */ - -#define NVM_FUSES_WDP_gm 0x0F /* Watchdog Timeout Period group mask. */ -#define NVM_FUSES_WDP_gp 0 /* Watchdog Timeout Period group position. */ -#define NVM_FUSES_WDP0_bm (1<<0) /* Watchdog Timeout Period bit 0 mask. */ -#define NVM_FUSES_WDP0_bp 0 /* Watchdog Timeout Period bit 0 position. */ -#define NVM_FUSES_WDP1_bm (1<<1) /* Watchdog Timeout Period bit 1 mask. */ -#define NVM_FUSES_WDP1_bp 1 /* Watchdog Timeout Period bit 1 position. */ -#define NVM_FUSES_WDP2_bm (1<<2) /* Watchdog Timeout Period bit 2 mask. */ -#define NVM_FUSES_WDP2_bp 2 /* Watchdog Timeout Period bit 2 position. */ -#define NVM_FUSES_WDP3_bm (1<<3) /* Watchdog Timeout Period bit 3 mask. */ -#define NVM_FUSES_WDP3_bp 3 /* Watchdog Timeout Period bit 3 position. */ - - -/* NVM_FUSES.FUSEBYTE2 bit masks and bit positions */ -#define NVM_FUSES_DVSDON_bm 0x80 /* Spike Detector Enable bit mask. */ -#define NVM_FUSES_DVSDON_bp 7 /* Spike Detector Enable bit position. */ - -#define NVM_FUSES_BOOTRST_bm 0x40 /* Boot Loader Section Reset Vector bit mask. */ -#define NVM_FUSES_BOOTRST_bp 6 /* Boot Loader Section Reset Vector bit position. */ - -#define NVM_FUSES_BODPD_gm 0x03 /* BOD Operation in Power-Down Mode group mask. */ -#define NVM_FUSES_BODPD_gp 0 /* BOD Operation in Power-Down Mode group position. */ -#define NVM_FUSES_BODPD0_bm (1<<0) /* BOD Operation in Power-Down Mode bit 0 mask. */ -#define NVM_FUSES_BODPD0_bp 0 /* BOD Operation in Power-Down Mode bit 0 position. */ -#define NVM_FUSES_BODPD1_bm (1<<1) /* BOD Operation in Power-Down Mode bit 1 mask. */ -#define NVM_FUSES_BODPD1_bp 1 /* BOD Operation in Power-Down Mode bit 1 position. */ - - -/* NVM_FUSES.FUSEBYTE4 bit masks and bit positions */ -#define NVM_FUSES_SUT_gm 0x0C /* Start-up Time group mask. */ -#define NVM_FUSES_SUT_gp 2 /* Start-up Time group position. */ -#define NVM_FUSES_SUT0_bm (1<<2) /* Start-up Time bit 0 mask. */ -#define NVM_FUSES_SUT0_bp 2 /* Start-up Time bit 0 position. */ -#define NVM_FUSES_SUT1_bm (1<<3) /* Start-up Time bit 1 mask. */ -#define NVM_FUSES_SUT1_bp 3 /* Start-up Time bit 1 position. */ - -#define NVM_FUSES_WDLOCK_bm 0x02 /* Watchdog Timer Lock bit mask. */ -#define NVM_FUSES_WDLOCK_bp 1 /* Watchdog Timer Lock bit position. */ - -#define NVM_FUSES_JTAGEN_bm 0x01 /* JTAG Interface Enable bit mask. */ -#define NVM_FUSES_JTAGEN_bp 0 /* JTAG Interface Enable bit position. */ - - -/* NVM_FUSES.FUSEBYTE5 bit masks and bit positions */ -#define NVM_FUSES_BODACT_gm 0x30 /* BOD Operation in Active Mode group mask. */ -#define NVM_FUSES_BODACT_gp 4 /* BOD Operation in Active Mode group position. */ -#define NVM_FUSES_BODACT0_bm (1<<4) /* BOD Operation in Active Mode bit 0 mask. */ -#define NVM_FUSES_BODACT0_bp 4 /* BOD Operation in Active Mode bit 0 position. */ -#define NVM_FUSES_BODACT1_bm (1<<5) /* BOD Operation in Active Mode bit 1 mask. */ -#define NVM_FUSES_BODACT1_bp 5 /* BOD Operation in Active Mode bit 1 position. */ - -#define NVM_FUSES_EESAVE_bm 0x08 /* Preserve EEPROM Through Chip Erase bit mask. */ -#define NVM_FUSES_EESAVE_bp 3 /* Preserve EEPROM Through Chip Erase bit position. */ - -#define NVM_FUSES_BODLVL_gm 0x07 /* Brown Out Detection Voltage Level group mask. */ -#define NVM_FUSES_BODLVL_gp 0 /* Brown Out Detection Voltage Level group position. */ -#define NVM_FUSES_BODLVL0_bm (1<<0) /* Brown Out Detection Voltage Level bit 0 mask. */ -#define NVM_FUSES_BODLVL0_bp 0 /* Brown Out Detection Voltage Level bit 0 position. */ -#define NVM_FUSES_BODLVL1_bm (1<<1) /* Brown Out Detection Voltage Level bit 1 mask. */ -#define NVM_FUSES_BODLVL1_bp 1 /* Brown Out Detection Voltage Level bit 1 position. */ -#define NVM_FUSES_BODLVL2_bm (1<<2) /* Brown Out Detection Voltage Level bit 2 mask. */ -#define NVM_FUSES_BODLVL2_bp 2 /* Brown Out Detection Voltage Level bit 2 position. */ - - -/* AC - Analog Comparator */ -/* AC.AC0CTRL bit masks and bit positions */ -#define AC_INTMODE_gm 0xC0 /* Interrupt Mode group mask. */ -#define AC_INTMODE_gp 6 /* Interrupt Mode group position. */ -#define AC_INTMODE0_bm (1<<6) /* Interrupt Mode bit 0 mask. */ -#define AC_INTMODE0_bp 6 /* Interrupt Mode bit 0 position. */ -#define AC_INTMODE1_bm (1<<7) /* Interrupt Mode bit 1 mask. */ -#define AC_INTMODE1_bp 7 /* Interrupt Mode bit 1 position. */ - -#define AC_INTLVL_gm 0x30 /* Interrupt Level group mask. */ -#define AC_INTLVL_gp 4 /* Interrupt Level group position. */ -#define AC_INTLVL0_bm (1<<4) /* Interrupt Level bit 0 mask. */ -#define AC_INTLVL0_bp 4 /* Interrupt Level bit 0 position. */ -#define AC_INTLVL1_bm (1<<5) /* Interrupt Level bit 1 mask. */ -#define AC_INTLVL1_bp 5 /* Interrupt Level bit 1 position. */ - -#define AC_HSMODE_bm 0x08 /* High-speed Mode bit mask. */ -#define AC_HSMODE_bp 3 /* High-speed Mode bit position. */ - -#define AC_HYSMODE_gm 0x06 /* Hysteresis Mode group mask. */ -#define AC_HYSMODE_gp 1 /* Hysteresis Mode group position. */ -#define AC_HYSMODE0_bm (1<<1) /* Hysteresis Mode bit 0 mask. */ -#define AC_HYSMODE0_bp 1 /* Hysteresis Mode bit 0 position. */ -#define AC_HYSMODE1_bm (1<<2) /* Hysteresis Mode bit 1 mask. */ -#define AC_HYSMODE1_bp 2 /* Hysteresis Mode bit 1 position. */ - -#define AC_ENABLE_bm 0x01 /* Enable bit mask. */ -#define AC_ENABLE_bp 0 /* Enable bit position. */ - - -/* AC.AC1CTRL bit masks and bit positions */ -/* AC_INTMODE_gm Predefined. */ -/* AC_INTMODE_gp Predefined. */ -/* AC_INTMODE0_bm Predefined. */ -/* AC_INTMODE0_bp Predefined. */ -/* AC_INTMODE1_bm Predefined. */ -/* AC_INTMODE1_bp Predefined. */ - -/* AC_INTLVL_gm Predefined. */ -/* AC_INTLVL_gp Predefined. */ -/* AC_INTLVL0_bm Predefined. */ -/* AC_INTLVL0_bp Predefined. */ -/* AC_INTLVL1_bm Predefined. */ -/* AC_INTLVL1_bp Predefined. */ - -/* AC_HSMODE_bm Predefined. */ -/* AC_HSMODE_bp Predefined. */ - -/* AC_HYSMODE_gm Predefined. */ -/* AC_HYSMODE_gp Predefined. */ -/* AC_HYSMODE0_bm Predefined. */ -/* AC_HYSMODE0_bp Predefined. */ -/* AC_HYSMODE1_bm Predefined. */ -/* AC_HYSMODE1_bp Predefined. */ - -/* AC_ENABLE_bm Predefined. */ -/* AC_ENABLE_bp Predefined. */ - - -/* AC.AC0MUXCTRL bit masks and bit positions */ -#define AC_MUXPOS_gm 0x38 /* MUX Positive Input group mask. */ -#define AC_MUXPOS_gp 3 /* MUX Positive Input group position. */ -#define AC_MUXPOS0_bm (1<<3) /* MUX Positive Input bit 0 mask. */ -#define AC_MUXPOS0_bp 3 /* MUX Positive Input bit 0 position. */ -#define AC_MUXPOS1_bm (1<<4) /* MUX Positive Input bit 1 mask. */ -#define AC_MUXPOS1_bp 4 /* MUX Positive Input bit 1 position. */ -#define AC_MUXPOS2_bm (1<<5) /* MUX Positive Input bit 2 mask. */ -#define AC_MUXPOS2_bp 5 /* MUX Positive Input bit 2 position. */ - -#define AC_MUXNEG_gm 0x07 /* MUX Negative Input group mask. */ -#define AC_MUXNEG_gp 0 /* MUX Negative Input group position. */ -#define AC_MUXNEG0_bm (1<<0) /* MUX Negative Input bit 0 mask. */ -#define AC_MUXNEG0_bp 0 /* MUX Negative Input bit 0 position. */ -#define AC_MUXNEG1_bm (1<<1) /* MUX Negative Input bit 1 mask. */ -#define AC_MUXNEG1_bp 1 /* MUX Negative Input bit 1 position. */ -#define AC_MUXNEG2_bm (1<<2) /* MUX Negative Input bit 2 mask. */ -#define AC_MUXNEG2_bp 2 /* MUX Negative Input bit 2 position. */ - - -/* AC.AC1MUXCTRL bit masks and bit positions */ -/* AC_MUXPOS_gm Predefined. */ -/* AC_MUXPOS_gp Predefined. */ -/* AC_MUXPOS0_bm Predefined. */ -/* AC_MUXPOS0_bp Predefined. */ -/* AC_MUXPOS1_bm Predefined. */ -/* AC_MUXPOS1_bp Predefined. */ -/* AC_MUXPOS2_bm Predefined. */ -/* AC_MUXPOS2_bp Predefined. */ - -/* AC_MUXNEG_gm Predefined. */ -/* AC_MUXNEG_gp Predefined. */ -/* AC_MUXNEG0_bm Predefined. */ -/* AC_MUXNEG0_bp Predefined. */ -/* AC_MUXNEG1_bm Predefined. */ -/* AC_MUXNEG1_bp Predefined. */ -/* AC_MUXNEG2_bm Predefined. */ -/* AC_MUXNEG2_bp Predefined. */ - - -/* AC.CTRLA bit masks and bit positions */ -#define AC_AC0OUT_bm 0x01 /* Comparator 0 Output Enable bit mask. */ -#define AC_AC0OUT_bp 0 /* Comparator 0 Output Enable bit position. */ - - -/* AC.CTRLB bit masks and bit positions */ -#define AC_SCALEFAC_gm 0x3F /* VCC Voltage Scaler Factor group mask. */ -#define AC_SCALEFAC_gp 0 /* VCC Voltage Scaler Factor group position. */ -#define AC_SCALEFAC0_bm (1<<0) /* VCC Voltage Scaler Factor bit 0 mask. */ -#define AC_SCALEFAC0_bp 0 /* VCC Voltage Scaler Factor bit 0 position. */ -#define AC_SCALEFAC1_bm (1<<1) /* VCC Voltage Scaler Factor bit 1 mask. */ -#define AC_SCALEFAC1_bp 1 /* VCC Voltage Scaler Factor bit 1 position. */ -#define AC_SCALEFAC2_bm (1<<2) /* VCC Voltage Scaler Factor bit 2 mask. */ -#define AC_SCALEFAC2_bp 2 /* VCC Voltage Scaler Factor bit 2 position. */ -#define AC_SCALEFAC3_bm (1<<3) /* VCC Voltage Scaler Factor bit 3 mask. */ -#define AC_SCALEFAC3_bp 3 /* VCC Voltage Scaler Factor bit 3 position. */ -#define AC_SCALEFAC4_bm (1<<4) /* VCC Voltage Scaler Factor bit 4 mask. */ -#define AC_SCALEFAC4_bp 4 /* VCC Voltage Scaler Factor bit 4 position. */ -#define AC_SCALEFAC5_bm (1<<5) /* VCC Voltage Scaler Factor bit 5 mask. */ -#define AC_SCALEFAC5_bp 5 /* VCC Voltage Scaler Factor bit 5 position. */ - - -/* AC.WINCTRL bit masks and bit positions */ -#define AC_WEN_bm 0x10 /* Window Mode Enable bit mask. */ -#define AC_WEN_bp 4 /* Window Mode Enable bit position. */ - -#define AC_WINTMODE_gm 0x0C /* Window Interrupt Mode group mask. */ -#define AC_WINTMODE_gp 2 /* Window Interrupt Mode group position. */ -#define AC_WINTMODE0_bm (1<<2) /* Window Interrupt Mode bit 0 mask. */ -#define AC_WINTMODE0_bp 2 /* Window Interrupt Mode bit 0 position. */ -#define AC_WINTMODE1_bm (1<<3) /* Window Interrupt Mode bit 1 mask. */ -#define AC_WINTMODE1_bp 3 /* Window Interrupt Mode bit 1 position. */ - -#define AC_WINTLVL_gm 0x03 /* Window Interrupt Level group mask. */ -#define AC_WINTLVL_gp 0 /* Window Interrupt Level group position. */ -#define AC_WINTLVL0_bm (1<<0) /* Window Interrupt Level bit 0 mask. */ -#define AC_WINTLVL0_bp 0 /* Window Interrupt Level bit 0 position. */ -#define AC_WINTLVL1_bm (1<<1) /* Window Interrupt Level bit 1 mask. */ -#define AC_WINTLVL1_bp 1 /* Window Interrupt Level bit 1 position. */ - - -/* AC.STATUS bit masks and bit positions */ -#define AC_WSTATE_gm 0xC0 /* Window Mode State group mask. */ -#define AC_WSTATE_gp 6 /* Window Mode State group position. */ -#define AC_WSTATE0_bm (1<<6) /* Window Mode State bit 0 mask. */ -#define AC_WSTATE0_bp 6 /* Window Mode State bit 0 position. */ -#define AC_WSTATE1_bm (1<<7) /* Window Mode State bit 1 mask. */ -#define AC_WSTATE1_bp 7 /* Window Mode State bit 1 position. */ - -#define AC_AC1STATE_bm 0x20 /* Comparator 1 State bit mask. */ -#define AC_AC1STATE_bp 5 /* Comparator 1 State bit position. */ - -#define AC_AC0STATE_bm 0x10 /* Comparator 0 State bit mask. */ -#define AC_AC0STATE_bp 4 /* Comparator 0 State bit position. */ - -#define AC_WIF_bm 0x04 /* Window Mode Interrupt Flag bit mask. */ -#define AC_WIF_bp 2 /* Window Mode Interrupt Flag bit position. */ - -#define AC_AC1IF_bm 0x02 /* Comparator 1 Interrupt Flag bit mask. */ -#define AC_AC1IF_bp 1 /* Comparator 1 Interrupt Flag bit position. */ - -#define AC_AC0IF_bm 0x01 /* Comparator 0 Interrupt Flag bit mask. */ -#define AC_AC0IF_bp 0 /* Comparator 0 Interrupt Flag bit position. */ - - -/* ADC - Analog/Digital Converter */ -/* ADC_CH.CTRL bit masks and bit positions */ -#define ADC_CH_START_bm 0x80 /* Channel Start Conversion bit mask. */ -#define ADC_CH_START_bp 7 /* Channel Start Conversion bit position. */ - -#define ADC_CH_GAINFAC_gm 0x1C /* Gain Factor group mask. */ -#define ADC_CH_GAINFAC_gp 2 /* Gain Factor group position. */ -#define ADC_CH_GAINFAC0_bm (1<<2) /* Gain Factor bit 0 mask. */ -#define ADC_CH_GAINFAC0_bp 2 /* Gain Factor bit 0 position. */ -#define ADC_CH_GAINFAC1_bm (1<<3) /* Gain Factor bit 1 mask. */ -#define ADC_CH_GAINFAC1_bp 3 /* Gain Factor bit 1 position. */ -#define ADC_CH_GAINFAC2_bm (1<<4) /* Gain Factor bit 2 mask. */ -#define ADC_CH_GAINFAC2_bp 4 /* Gain Factor bit 2 position. */ - -#define ADC_CH_INPUTMODE_gm 0x03 /* Input Mode Select group mask. */ -#define ADC_CH_INPUTMODE_gp 0 /* Input Mode Select group position. */ -#define ADC_CH_INPUTMODE0_bm (1<<0) /* Input Mode Select bit 0 mask. */ -#define ADC_CH_INPUTMODE0_bp 0 /* Input Mode Select bit 0 position. */ -#define ADC_CH_INPUTMODE1_bm (1<<1) /* Input Mode Select bit 1 mask. */ -#define ADC_CH_INPUTMODE1_bp 1 /* Input Mode Select bit 1 position. */ - - -/* ADC_CH.MUXCTRL bit masks and bit positions */ -#define ADC_CH_MUXPOS_gm 0x78 /* Positive Input Select group mask. */ -#define ADC_CH_MUXPOS_gp 3 /* Positive Input Select group position. */ -#define ADC_CH_MUXPOS0_bm (1<<3) /* Positive Input Select bit 0 mask. */ -#define ADC_CH_MUXPOS0_bp 3 /* Positive Input Select bit 0 position. */ -#define ADC_CH_MUXPOS1_bm (1<<4) /* Positive Input Select bit 1 mask. */ -#define ADC_CH_MUXPOS1_bp 4 /* Positive Input Select bit 1 position. */ -#define ADC_CH_MUXPOS2_bm (1<<5) /* Positive Input Select bit 2 mask. */ -#define ADC_CH_MUXPOS2_bp 5 /* Positive Input Select bit 2 position. */ -#define ADC_CH_MUXPOS3_bm (1<<6) /* Positive Input Select bit 3 mask. */ -#define ADC_CH_MUXPOS3_bp 6 /* Positive Input Select bit 3 position. */ - -#define ADC_CH_MUXINT_gm 0x78 /* Internal Input Select group mask. */ -#define ADC_CH_MUXINT_gp 3 /* Internal Input Select group position. */ -#define ADC_CH_MUXINT0_bm (1<<3) /* Internal Input Select bit 0 mask. */ -#define ADC_CH_MUXINT0_bp 3 /* Internal Input Select bit 0 position. */ -#define ADC_CH_MUXINT1_bm (1<<4) /* Internal Input Select bit 1 mask. */ -#define ADC_CH_MUXINT1_bp 4 /* Internal Input Select bit 1 position. */ -#define ADC_CH_MUXINT2_bm (1<<5) /* Internal Input Select bit 2 mask. */ -#define ADC_CH_MUXINT2_bp 5 /* Internal Input Select bit 2 position. */ -#define ADC_CH_MUXINT3_bm (1<<6) /* Internal Input Select bit 3 mask. */ -#define ADC_CH_MUXINT3_bp 6 /* Internal Input Select bit 3 position. */ - -#define ADC_CH_MUXNEG_gm 0x03 /* Negative Input Select group mask. */ -#define ADC_CH_MUXNEG_gp 0 /* Negative Input Select group position. */ -#define ADC_CH_MUXNEG0_bm (1<<0) /* Negative Input Select bit 0 mask. */ -#define ADC_CH_MUXNEG0_bp 0 /* Negative Input Select bit 0 position. */ -#define ADC_CH_MUXNEG1_bm (1<<1) /* Negative Input Select bit 1 mask. */ -#define ADC_CH_MUXNEG1_bp 1 /* Negative Input Select bit 1 position. */ - - -/* ADC_CH.INTCTRL bit masks and bit positions */ -#define ADC_CH_INTMODE_gm 0x0C /* Interrupt Mode group mask. */ -#define ADC_CH_INTMODE_gp 2 /* Interrupt Mode group position. */ -#define ADC_CH_INTMODE0_bm (1<<2) /* Interrupt Mode bit 0 mask. */ -#define ADC_CH_INTMODE0_bp 2 /* Interrupt Mode bit 0 position. */ -#define ADC_CH_INTMODE1_bm (1<<3) /* Interrupt Mode bit 1 mask. */ -#define ADC_CH_INTMODE1_bp 3 /* Interrupt Mode bit 1 position. */ - -#define ADC_CH_INTLVL_gm 0x03 /* Interrupt Level group mask. */ -#define ADC_CH_INTLVL_gp 0 /* Interrupt Level group position. */ -#define ADC_CH_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */ -#define ADC_CH_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */ -#define ADC_CH_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ -#define ADC_CH_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */ - - -/* ADC_CH.INTFLAGS bit masks and bit positions */ -#define ADC_CH_CHIF_bm 0x01 /* Channel Interrupt Flag bit mask. */ -#define ADC_CH_CHIF_bp 0 /* Channel Interrupt Flag bit position. */ - - -/* ADC.CTRLA bit masks and bit positions */ -#define ADC_DMASEL_gm 0xC0 /* DMA Selection group mask. */ -#define ADC_DMASEL_gp 6 /* DMA Selection group position. */ -#define ADC_DMASEL0_bm (1<<6) /* DMA Selection bit 0 mask. */ -#define ADC_DMASEL0_bp 6 /* DMA Selection bit 0 position. */ -#define ADC_DMASEL1_bm (1<<7) /* DMA Selection bit 1 mask. */ -#define ADC_DMASEL1_bp 7 /* DMA Selection bit 1 position. */ - -#define ADC_CH3START_bm 0x20 /* Channel 3 Start Conversion bit mask. */ -#define ADC_CH3START_bp 5 /* Channel 3 Start Conversion bit position. */ - -#define ADC_CH2START_bm 0x10 /* Channel 2 Start Conversion bit mask. */ -#define ADC_CH2START_bp 4 /* Channel 2 Start Conversion bit position. */ - -#define ADC_CH1START_bm 0x08 /* Channel 1 Start Conversion bit mask. */ -#define ADC_CH1START_bp 3 /* Channel 1 Start Conversion bit position. */ - -#define ADC_CH0START_bm 0x04 /* Channel 0 Start Conversion bit mask. */ -#define ADC_CH0START_bp 2 /* Channel 0 Start Conversion bit position. */ - -#define ADC_FLUSH_bm 0x02 /* Flush Pipeline bit mask. */ -#define ADC_FLUSH_bp 1 /* Flush Pipeline bit position. */ - -#define ADC_ENABLE_bm 0x01 /* Enable ADC bit mask. */ -#define ADC_ENABLE_bp 0 /* Enable ADC bit position. */ - - -/* ADC.CTRLB bit masks and bit positions */ -#define ADC_CONMODE_bm 0x10 /* Conversion Mode bit mask. */ -#define ADC_CONMODE_bp 4 /* Conversion Mode bit position. */ - -#define ADC_FREERUN_bm 0x08 /* Free Running Mode Enable bit mask. */ -#define ADC_FREERUN_bp 3 /* Free Running Mode Enable bit position. */ - -#define ADC_RESOLUTION_gm 0x06 /* Result Resolution group mask. */ -#define ADC_RESOLUTION_gp 1 /* Result Resolution group position. */ -#define ADC_RESOLUTION0_bm (1<<1) /* Result Resolution bit 0 mask. */ -#define ADC_RESOLUTION0_bp 1 /* Result Resolution bit 0 position. */ -#define ADC_RESOLUTION1_bm (1<<2) /* Result Resolution bit 1 mask. */ -#define ADC_RESOLUTION1_bp 2 /* Result Resolution bit 1 position. */ - - -/* ADC.REFCTRL bit masks and bit positions */ -#define ADC_REFSEL_gm 0x30 /* Reference Selection group mask. */ -#define ADC_REFSEL_gp 4 /* Reference Selection group position. */ -#define ADC_REFSEL0_bm (1<<4) /* Reference Selection bit 0 mask. */ -#define ADC_REFSEL0_bp 4 /* Reference Selection bit 0 position. */ -#define ADC_REFSEL1_bm (1<<5) /* Reference Selection bit 1 mask. */ -#define ADC_REFSEL1_bp 5 /* Reference Selection bit 1 position. */ - -#define ADC_BANDGAP_bm 0x02 /* Bandgap enable bit mask. */ -#define ADC_BANDGAP_bp 1 /* Bandgap enable bit position. */ - -#define ADC_TEMPREF_bm 0x01 /* Temperature Reference Enable bit mask. */ -#define ADC_TEMPREF_bp 0 /* Temperature Reference Enable bit position. */ - - -/* ADC.EVCTRL bit masks and bit positions */ -#define ADC_SWEEP_gm 0xC0 /* Channel Sweep Selection group mask. */ -#define ADC_SWEEP_gp 6 /* Channel Sweep Selection group position. */ -#define ADC_SWEEP0_bm (1<<6) /* Channel Sweep Selection bit 0 mask. */ -#define ADC_SWEEP0_bp 6 /* Channel Sweep Selection bit 0 position. */ -#define ADC_SWEEP1_bm (1<<7) /* Channel Sweep Selection bit 1 mask. */ -#define ADC_SWEEP1_bp 7 /* Channel Sweep Selection bit 1 position. */ - -#define ADC_EVSEL_gm 0x38 /* Event Input Select group mask. */ -#define ADC_EVSEL_gp 3 /* Event Input Select group position. */ -#define ADC_EVSEL0_bm (1<<3) /* Event Input Select bit 0 mask. */ -#define ADC_EVSEL0_bp 3 /* Event Input Select bit 0 position. */ -#define ADC_EVSEL1_bm (1<<4) /* Event Input Select bit 1 mask. */ -#define ADC_EVSEL1_bp 4 /* Event Input Select bit 1 position. */ -#define ADC_EVSEL2_bm (1<<5) /* Event Input Select bit 2 mask. */ -#define ADC_EVSEL2_bp 5 /* Event Input Select bit 2 position. */ - -#define ADC_EVACT_gm 0x07 /* Event Action Select group mask. */ -#define ADC_EVACT_gp 0 /* Event Action Select group position. */ -#define ADC_EVACT0_bm (1<<0) /* Event Action Select bit 0 mask. */ -#define ADC_EVACT0_bp 0 /* Event Action Select bit 0 position. */ -#define ADC_EVACT1_bm (1<<1) /* Event Action Select bit 1 mask. */ -#define ADC_EVACT1_bp 1 /* Event Action Select bit 1 position. */ -#define ADC_EVACT2_bm (1<<2) /* Event Action Select bit 2 mask. */ -#define ADC_EVACT2_bp 2 /* Event Action Select bit 2 position. */ - - -/* ADC.PRESCALER bit masks and bit positions */ -#define ADC_PRESCALER_gm 0x07 /* Clock Prescaler Selection group mask. */ -#define ADC_PRESCALER_gp 0 /* Clock Prescaler Selection group position. */ -#define ADC_PRESCALER0_bm (1<<0) /* Clock Prescaler Selection bit 0 mask. */ -#define ADC_PRESCALER0_bp 0 /* Clock Prescaler Selection bit 0 position. */ -#define ADC_PRESCALER1_bm (1<<1) /* Clock Prescaler Selection bit 1 mask. */ -#define ADC_PRESCALER1_bp 1 /* Clock Prescaler Selection bit 1 position. */ -#define ADC_PRESCALER2_bm (1<<2) /* Clock Prescaler Selection bit 2 mask. */ -#define ADC_PRESCALER2_bp 2 /* Clock Prescaler Selection bit 2 position. */ - - -/* ADC.INTFLAGS bit masks and bit positions */ -#define ADC_CH3IF_bm 0x08 /* Channel 3 Interrupt Flag bit mask. */ -#define ADC_CH3IF_bp 3 /* Channel 3 Interrupt Flag bit position. */ - -#define ADC_CH2IF_bm 0x04 /* Channel 2 Interrupt Flag bit mask. */ -#define ADC_CH2IF_bp 2 /* Channel 2 Interrupt Flag bit position. */ - -#define ADC_CH1IF_bm 0x02 /* Channel 1 Interrupt Flag bit mask. */ -#define ADC_CH1IF_bp 1 /* Channel 1 Interrupt Flag bit position. */ - -#define ADC_CH0IF_bm 0x01 /* Channel 0 Interrupt Flag bit mask. */ -#define ADC_CH0IF_bp 0 /* Channel 0 Interrupt Flag bit position. */ - - -/* DAC - Digital/Analog Converter */ -/* DAC.CTRLA bit masks and bit positions */ -#define DAC_IDOEN_bm 0x10 /* Internal Output Enable bit mask. */ -#define DAC_IDOEN_bp 4 /* Internal Output Enable bit position. */ - -#define DAC_CH1EN_bm 0x08 /* Channel 1 Output Enable bit mask. */ -#define DAC_CH1EN_bp 3 /* Channel 1 Output Enable bit position. */ - -#define DAC_CH0EN_bm 0x04 /* Channel 0 Output Enable bit mask. */ -#define DAC_CH0EN_bp 2 /* Channel 0 Output Enable bit position. */ - -#define DAC_LPMODE_bm 0x02 /* Low Power Mode bit mask. */ -#define DAC_LPMODE_bp 1 /* Low Power Mode bit position. */ - -#define DAC_ENABLE_bm 0x01 /* Enable bit mask. */ -#define DAC_ENABLE_bp 0 /* Enable bit position. */ - - -/* DAC.CTRLB bit masks and bit positions */ -#define DAC_CHSEL_gm 0x60 /* Channel Select group mask. */ -#define DAC_CHSEL_gp 5 /* Channel Select group position. */ -#define DAC_CHSEL0_bm (1<<5) /* Channel Select bit 0 mask. */ -#define DAC_CHSEL0_bp 5 /* Channel Select bit 0 position. */ -#define DAC_CHSEL1_bm (1<<6) /* Channel Select bit 1 mask. */ -#define DAC_CHSEL1_bp 6 /* Channel Select bit 1 position. */ - -#define DAC_CH1TRIG_bm 0x02 /* Channel 1 Event Trig Enable bit mask. */ -#define DAC_CH1TRIG_bp 1 /* Channel 1 Event Trig Enable bit position. */ - -#define DAC_CH0TRIG_bm 0x01 /* Channel 0 Event Trig Enable bit mask. */ -#define DAC_CH0TRIG_bp 0 /* Channel 0 Event Trig Enable bit position. */ - - -/* DAC.CTRLC bit masks and bit positions */ -#define DAC_REFSEL_gm 0x18 /* Reference Select group mask. */ -#define DAC_REFSEL_gp 3 /* Reference Select group position. */ -#define DAC_REFSEL0_bm (1<<3) /* Reference Select bit 0 mask. */ -#define DAC_REFSEL0_bp 3 /* Reference Select bit 0 position. */ -#define DAC_REFSEL1_bm (1<<4) /* Reference Select bit 1 mask. */ -#define DAC_REFSEL1_bp 4 /* Reference Select bit 1 position. */ - -#define DAC_LEFTADJ_bm 0x01 /* Left-adjust Result bit mask. */ -#define DAC_LEFTADJ_bp 0 /* Left-adjust Result bit position. */ - - -/* DAC.EVCTRL bit masks and bit positions */ -#define DAC_EVSEL_gm 0x07 /* Event Input Selection group mask. */ -#define DAC_EVSEL_gp 0 /* Event Input Selection group position. */ -#define DAC_EVSEL0_bm (1<<0) /* Event Input Selection bit 0 mask. */ -#define DAC_EVSEL0_bp 0 /* Event Input Selection bit 0 position. */ -#define DAC_EVSEL1_bm (1<<1) /* Event Input Selection bit 1 mask. */ -#define DAC_EVSEL1_bp 1 /* Event Input Selection bit 1 position. */ -#define DAC_EVSEL2_bm (1<<2) /* Event Input Selection bit 2 mask. */ -#define DAC_EVSEL2_bp 2 /* Event Input Selection bit 2 position. */ - - -/* DAC.TIMCTRL bit masks and bit positions */ -#define DAC_CONINTVAL_gm 0x70 /* Conversion Intercal group mask. */ -#define DAC_CONINTVAL_gp 4 /* Conversion Intercal group position. */ -#define DAC_CONINTVAL0_bm (1<<4) /* Conversion Intercal bit 0 mask. */ -#define DAC_CONINTVAL0_bp 4 /* Conversion Intercal bit 0 position. */ -#define DAC_CONINTVAL1_bm (1<<5) /* Conversion Intercal bit 1 mask. */ -#define DAC_CONINTVAL1_bp 5 /* Conversion Intercal bit 1 position. */ -#define DAC_CONINTVAL2_bm (1<<6) /* Conversion Intercal bit 2 mask. */ -#define DAC_CONINTVAL2_bp 6 /* Conversion Intercal bit 2 position. */ - -#define DAC_REFRESH_gm 0x0F /* Refresh Timing Control group mask. */ -#define DAC_REFRESH_gp 0 /* Refresh Timing Control group position. */ -#define DAC_REFRESH0_bm (1<<0) /* Refresh Timing Control bit 0 mask. */ -#define DAC_REFRESH0_bp 0 /* Refresh Timing Control bit 0 position. */ -#define DAC_REFRESH1_bm (1<<1) /* Refresh Timing Control bit 1 mask. */ -#define DAC_REFRESH1_bp 1 /* Refresh Timing Control bit 1 position. */ -#define DAC_REFRESH2_bm (1<<2) /* Refresh Timing Control bit 2 mask. */ -#define DAC_REFRESH2_bp 2 /* Refresh Timing Control bit 2 position. */ -#define DAC_REFRESH3_bm (1<<3) /* Refresh Timing Control bit 3 mask. */ -#define DAC_REFRESH3_bp 3 /* Refresh Timing Control bit 3 position. */ - - -/* DAC.STATUS bit masks and bit positions */ -#define DAC_CH1DRE_bm 0x02 /* Channel 1 Data Register Empty bit mask. */ -#define DAC_CH1DRE_bp 1 /* Channel 1 Data Register Empty bit position. */ - -#define DAC_CH0DRE_bm 0x01 /* Channel 0 Data Register Empty bit mask. */ -#define DAC_CH0DRE_bp 0 /* Channel 0 Data Register Empty bit position. */ - - -/* RTC - Real-Time Clounter */ -/* RTC.CTRL bit masks and bit positions */ -#define RTC_PRESCALER_gm 0x07 /* Prescaling Factor group mask. */ -#define RTC_PRESCALER_gp 0 /* Prescaling Factor group position. */ -#define RTC_PRESCALER0_bm (1<<0) /* Prescaling Factor bit 0 mask. */ -#define RTC_PRESCALER0_bp 0 /* Prescaling Factor bit 0 position. */ -#define RTC_PRESCALER1_bm (1<<1) /* Prescaling Factor bit 1 mask. */ -#define RTC_PRESCALER1_bp 1 /* Prescaling Factor bit 1 position. */ -#define RTC_PRESCALER2_bm (1<<2) /* Prescaling Factor bit 2 mask. */ -#define RTC_PRESCALER2_bp 2 /* Prescaling Factor bit 2 position. */ - - -/* RTC.STATUS bit masks and bit positions */ -#define RTC_SYNCBUSY_bm 0x01 /* Synchronization Busy Flag bit mask. */ -#define RTC_SYNCBUSY_bp 0 /* Synchronization Busy Flag bit position. */ - - -/* RTC.INTCTRL bit masks and bit positions */ -#define RTC_COMPINTLVL_gm 0x0C /* Compare Match Interrupt Level group mask. */ -#define RTC_COMPINTLVL_gp 2 /* Compare Match Interrupt Level group position. */ -#define RTC_COMPINTLVL0_bm (1<<2) /* Compare Match Interrupt Level bit 0 mask. */ -#define RTC_COMPINTLVL0_bp 2 /* Compare Match Interrupt Level bit 0 position. */ -#define RTC_COMPINTLVL1_bm (1<<3) /* Compare Match Interrupt Level bit 1 mask. */ -#define RTC_COMPINTLVL1_bp 3 /* Compare Match Interrupt Level bit 1 position. */ - -#define RTC_OVFINTLVL_gm 0x03 /* Overflow Interrupt Level group mask. */ -#define RTC_OVFINTLVL_gp 0 /* Overflow Interrupt Level group position. */ -#define RTC_OVFINTLVL0_bm (1<<0) /* Overflow Interrupt Level bit 0 mask. */ -#define RTC_OVFINTLVL0_bp 0 /* Overflow Interrupt Level bit 0 position. */ -#define RTC_OVFINTLVL1_bm (1<<1) /* Overflow Interrupt Level bit 1 mask. */ -#define RTC_OVFINTLVL1_bp 1 /* Overflow Interrupt Level bit 1 position. */ - - -/* RTC.INTFLAGS bit masks and bit positions */ -#define RTC_COMPIF_bm 0x02 /* Compare Match Interrupt Flag bit mask. */ -#define RTC_COMPIF_bp 1 /* Compare Match Interrupt Flag bit position. */ - -#define RTC_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ -#define RTC_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ - - -/* EBI - External Bus Interface */ -/* EBI_CS.CTRLA bit masks and bit positions */ -#define EBI_CS_ASIZE_gm 0x7C /* Address Size group mask. */ -#define EBI_CS_ASIZE_gp 2 /* Address Size group position. */ -#define EBI_CS_ASIZE0_bm (1<<2) /* Address Size bit 0 mask. */ -#define EBI_CS_ASIZE0_bp 2 /* Address Size bit 0 position. */ -#define EBI_CS_ASIZE1_bm (1<<3) /* Address Size bit 1 mask. */ -#define EBI_CS_ASIZE1_bp 3 /* Address Size bit 1 position. */ -#define EBI_CS_ASIZE2_bm (1<<4) /* Address Size bit 2 mask. */ -#define EBI_CS_ASIZE2_bp 4 /* Address Size bit 2 position. */ -#define EBI_CS_ASIZE3_bm (1<<5) /* Address Size bit 3 mask. */ -#define EBI_CS_ASIZE3_bp 5 /* Address Size bit 3 position. */ -#define EBI_CS_ASIZE4_bm (1<<6) /* Address Size bit 4 mask. */ -#define EBI_CS_ASIZE4_bp 6 /* Address Size bit 4 position. */ - -#define EBI_CS_MODE_gm 0x03 /* Memory Mode group mask. */ -#define EBI_CS_MODE_gp 0 /* Memory Mode group position. */ -#define EBI_CS_MODE0_bm (1<<0) /* Memory Mode bit 0 mask. */ -#define EBI_CS_MODE0_bp 0 /* Memory Mode bit 0 position. */ -#define EBI_CS_MODE1_bm (1<<1) /* Memory Mode bit 1 mask. */ -#define EBI_CS_MODE1_bp 1 /* Memory Mode bit 1 position. */ - - -/* EBI_CS.CTRLB bit masks and bit positions */ -#define EBI_CS_SRWS_gm 0x07 /* SRAM Wait State Cycles group mask. */ -#define EBI_CS_SRWS_gp 0 /* SRAM Wait State Cycles group position. */ -#define EBI_CS_SRWS0_bm (1<<0) /* SRAM Wait State Cycles bit 0 mask. */ -#define EBI_CS_SRWS0_bp 0 /* SRAM Wait State Cycles bit 0 position. */ -#define EBI_CS_SRWS1_bm (1<<1) /* SRAM Wait State Cycles bit 1 mask. */ -#define EBI_CS_SRWS1_bp 1 /* SRAM Wait State Cycles bit 1 position. */ -#define EBI_CS_SRWS2_bm (1<<2) /* SRAM Wait State Cycles bit 2 mask. */ -#define EBI_CS_SRWS2_bp 2 /* SRAM Wait State Cycles bit 2 position. */ - -#define EBI_CS_SDINITDONE_bm 0x80 /* SDRAM Initialization Done bit mask. */ -#define EBI_CS_SDINITDONE_bp 7 /* SDRAM Initialization Done bit position. */ - -#define EBI_CS_SDSREN_bm 0x04 /* SDRAM Self-refresh Enable bit mask. */ -#define EBI_CS_SDSREN_bp 2 /* SDRAM Self-refresh Enable bit position. */ - -#define EBI_CS_SDMODE_gm 0x03 /* SDRAM Mode group mask. */ -#define EBI_CS_SDMODE_gp 0 /* SDRAM Mode group position. */ -#define EBI_CS_SDMODE0_bm (1<<0) /* SDRAM Mode bit 0 mask. */ -#define EBI_CS_SDMODE0_bp 0 /* SDRAM Mode bit 0 position. */ -#define EBI_CS_SDMODE1_bm (1<<1) /* SDRAM Mode bit 1 mask. */ -#define EBI_CS_SDMODE1_bp 1 /* SDRAM Mode bit 1 position. */ - - -/* EBI.CTRL bit masks and bit positions */ -#define EBI_SDDATAW_gm 0xC0 /* SDRAM Data Width Setting group mask. */ -#define EBI_SDDATAW_gp 6 /* SDRAM Data Width Setting group position. */ -#define EBI_SDDATAW0_bm (1<<6) /* SDRAM Data Width Setting bit 0 mask. */ -#define EBI_SDDATAW0_bp 6 /* SDRAM Data Width Setting bit 0 position. */ -#define EBI_SDDATAW1_bm (1<<7) /* SDRAM Data Width Setting bit 1 mask. */ -#define EBI_SDDATAW1_bp 7 /* SDRAM Data Width Setting bit 1 position. */ - -#define EBI_LPCMODE_gm 0x30 /* SRAM LPC Mode group mask. */ -#define EBI_LPCMODE_gp 4 /* SRAM LPC Mode group position. */ -#define EBI_LPCMODE0_bm (1<<4) /* SRAM LPC Mode bit 0 mask. */ -#define EBI_LPCMODE0_bp 4 /* SRAM LPC Mode bit 0 position. */ -#define EBI_LPCMODE1_bm (1<<5) /* SRAM LPC Mode bit 1 mask. */ -#define EBI_LPCMODE1_bp 5 /* SRAM LPC Mode bit 1 position. */ - -#define EBI_SRMODE_gm 0x0C /* SRAM Mode group mask. */ -#define EBI_SRMODE_gp 2 /* SRAM Mode group position. */ -#define EBI_SRMODE0_bm (1<<2) /* SRAM Mode bit 0 mask. */ -#define EBI_SRMODE0_bp 2 /* SRAM Mode bit 0 position. */ -#define EBI_SRMODE1_bm (1<<3) /* SRAM Mode bit 1 mask. */ -#define EBI_SRMODE1_bp 3 /* SRAM Mode bit 1 position. */ - -#define EBI_IFMODE_gm 0x03 /* Interface Mode group mask. */ -#define EBI_IFMODE_gp 0 /* Interface Mode group position. */ -#define EBI_IFMODE0_bm (1<<0) /* Interface Mode bit 0 mask. */ -#define EBI_IFMODE0_bp 0 /* Interface Mode bit 0 position. */ -#define EBI_IFMODE1_bm (1<<1) /* Interface Mode bit 1 mask. */ -#define EBI_IFMODE1_bp 1 /* Interface Mode bit 1 position. */ - - -/* EBI.SDRAMCTRLA bit masks and bit positions */ -#define EBI_SDCAS_bm 0x08 /* SDRAM CAS Latency Setting bit mask. */ -#define EBI_SDCAS_bp 3 /* SDRAM CAS Latency Setting bit position. */ - -#define EBI_SDROW_bm 0x04 /* SDRAM ROW Bits Setting bit mask. */ -#define EBI_SDROW_bp 2 /* SDRAM ROW Bits Setting bit position. */ - -#define EBI_SDCOL_gm 0x03 /* SDRAM Column Bits Setting group mask. */ -#define EBI_SDCOL_gp 0 /* SDRAM Column Bits Setting group position. */ -#define EBI_SDCOL0_bm (1<<0) /* SDRAM Column Bits Setting bit 0 mask. */ -#define EBI_SDCOL0_bp 0 /* SDRAM Column Bits Setting bit 0 position. */ -#define EBI_SDCOL1_bm (1<<1) /* SDRAM Column Bits Setting bit 1 mask. */ -#define EBI_SDCOL1_bp 1 /* SDRAM Column Bits Setting bit 1 position. */ - - -/* EBI.SDRAMCTRLB bit masks and bit positions */ -#define EBI_MRDLY_gm 0xC0 /* SDRAM Mode Register Delay group mask. */ -#define EBI_MRDLY_gp 6 /* SDRAM Mode Register Delay group position. */ -#define EBI_MRDLY0_bm (1<<6) /* SDRAM Mode Register Delay bit 0 mask. */ -#define EBI_MRDLY0_bp 6 /* SDRAM Mode Register Delay bit 0 position. */ -#define EBI_MRDLY1_bm (1<<7) /* SDRAM Mode Register Delay bit 1 mask. */ -#define EBI_MRDLY1_bp 7 /* SDRAM Mode Register Delay bit 1 position. */ - -#define EBI_ROWCYCDLY_gm 0x38 /* SDRAM Row Cycle Delay group mask. */ -#define EBI_ROWCYCDLY_gp 3 /* SDRAM Row Cycle Delay group position. */ -#define EBI_ROWCYCDLY0_bm (1<<3) /* SDRAM Row Cycle Delay bit 0 mask. */ -#define EBI_ROWCYCDLY0_bp 3 /* SDRAM Row Cycle Delay bit 0 position. */ -#define EBI_ROWCYCDLY1_bm (1<<4) /* SDRAM Row Cycle Delay bit 1 mask. */ -#define EBI_ROWCYCDLY1_bp 4 /* SDRAM Row Cycle Delay bit 1 position. */ -#define EBI_ROWCYCDLY2_bm (1<<5) /* SDRAM Row Cycle Delay bit 2 mask. */ -#define EBI_ROWCYCDLY2_bp 5 /* SDRAM Row Cycle Delay bit 2 position. */ - -#define EBI_RPDLY_gm 0x07 /* SDRAM Row-to-Precharge Delay group mask. */ -#define EBI_RPDLY_gp 0 /* SDRAM Row-to-Precharge Delay group position. */ -#define EBI_RPDLY0_bm (1<<0) /* SDRAM Row-to-Precharge Delay bit 0 mask. */ -#define EBI_RPDLY0_bp 0 /* SDRAM Row-to-Precharge Delay bit 0 position. */ -#define EBI_RPDLY1_bm (1<<1) /* SDRAM Row-to-Precharge Delay bit 1 mask. */ -#define EBI_RPDLY1_bp 1 /* SDRAM Row-to-Precharge Delay bit 1 position. */ -#define EBI_RPDLY2_bm (1<<2) /* SDRAM Row-to-Precharge Delay bit 2 mask. */ -#define EBI_RPDLY2_bp 2 /* SDRAM Row-to-Precharge Delay bit 2 position. */ - - -/* EBI.SDRAMCTRLC bit masks and bit positions */ -#define EBI_WRDLY_gm 0xC0 /* SDRAM Write Recovery Delay group mask. */ -#define EBI_WRDLY_gp 6 /* SDRAM Write Recovery Delay group position. */ -#define EBI_WRDLY0_bm (1<<6) /* SDRAM Write Recovery Delay bit 0 mask. */ -#define EBI_WRDLY0_bp 6 /* SDRAM Write Recovery Delay bit 0 position. */ -#define EBI_WRDLY1_bm (1<<7) /* SDRAM Write Recovery Delay bit 1 mask. */ -#define EBI_WRDLY1_bp 7 /* SDRAM Write Recovery Delay bit 1 position. */ - -#define EBI_ESRDLY_gm 0x38 /* SDRAM Exit-Self-refresh-to-Active Delay group mask. */ -#define EBI_ESRDLY_gp 3 /* SDRAM Exit-Self-refresh-to-Active Delay group position. */ -#define EBI_ESRDLY0_bm (1<<3) /* SDRAM Exit-Self-refresh-to-Active Delay bit 0 mask. */ -#define EBI_ESRDLY0_bp 3 /* SDRAM Exit-Self-refresh-to-Active Delay bit 0 position. */ -#define EBI_ESRDLY1_bm (1<<4) /* SDRAM Exit-Self-refresh-to-Active Delay bit 1 mask. */ -#define EBI_ESRDLY1_bp 4 /* SDRAM Exit-Self-refresh-to-Active Delay bit 1 position. */ -#define EBI_ESRDLY2_bm (1<<5) /* SDRAM Exit-Self-refresh-to-Active Delay bit 2 mask. */ -#define EBI_ESRDLY2_bp 5 /* SDRAM Exit-Self-refresh-to-Active Delay bit 2 position. */ - -#define EBI_ROWCOLDLY_gm 0x07 /* SDRAM Row-to-Column Delay group mask. */ -#define EBI_ROWCOLDLY_gp 0 /* SDRAM Row-to-Column Delay group position. */ -#define EBI_ROWCOLDLY0_bm (1<<0) /* SDRAM Row-to-Column Delay bit 0 mask. */ -#define EBI_ROWCOLDLY0_bp 0 /* SDRAM Row-to-Column Delay bit 0 position. */ -#define EBI_ROWCOLDLY1_bm (1<<1) /* SDRAM Row-to-Column Delay bit 1 mask. */ -#define EBI_ROWCOLDLY1_bp 1 /* SDRAM Row-to-Column Delay bit 1 position. */ -#define EBI_ROWCOLDLY2_bm (1<<2) /* SDRAM Row-to-Column Delay bit 2 mask. */ -#define EBI_ROWCOLDLY2_bp 2 /* SDRAM Row-to-Column Delay bit 2 position. */ - - -/* TWI - Two-Wire Interface */ -/* TWI_MASTER.CTRLA bit masks and bit positions */ -#define TWI_MASTER_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ -#define TWI_MASTER_INTLVL_gp 6 /* Interrupt Level group position. */ -#define TWI_MASTER_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ -#define TWI_MASTER_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ -#define TWI_MASTER_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ -#define TWI_MASTER_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ - -#define TWI_MASTER_RIEN_bm 0x20 /* Read Interrupt Enable bit mask. */ -#define TWI_MASTER_RIEN_bp 5 /* Read Interrupt Enable bit position. */ - -#define TWI_MASTER_WIEN_bm 0x10 /* Write Interrupt Enable bit mask. */ -#define TWI_MASTER_WIEN_bp 4 /* Write Interrupt Enable bit position. */ - -#define TWI_MASTER_ENABLE_bm 0x08 /* Enable TWI Master bit mask. */ -#define TWI_MASTER_ENABLE_bp 3 /* Enable TWI Master bit position. */ - - -/* TWI_MASTER.CTRLB bit masks and bit positions */ -#define TWI_MASTER_TIMEOUT_gm 0x0C /* Inactive Bus Timeout group mask. */ -#define TWI_MASTER_TIMEOUT_gp 2 /* Inactive Bus Timeout group position. */ -#define TWI_MASTER_TIMEOUT0_bm (1<<2) /* Inactive Bus Timeout bit 0 mask. */ -#define TWI_MASTER_TIMEOUT0_bp 2 /* Inactive Bus Timeout bit 0 position. */ -#define TWI_MASTER_TIMEOUT1_bm (1<<3) /* Inactive Bus Timeout bit 1 mask. */ -#define TWI_MASTER_TIMEOUT1_bp 3 /* Inactive Bus Timeout bit 1 position. */ - -#define TWI_MASTER_QCEN_bm 0x02 /* Quick Command Enable bit mask. */ -#define TWI_MASTER_QCEN_bp 1 /* Quick Command Enable bit position. */ - -#define TWI_MASTER_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ -#define TWI_MASTER_SMEN_bp 0 /* Smart Mode Enable bit position. */ - - -/* TWI_MASTER.CTRLC bit masks and bit positions */ -#define TWI_MASTER_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ -#define TWI_MASTER_ACKACT_bp 2 /* Acknowledge Action bit position. */ - -#define TWI_MASTER_CMD_gm 0x03 /* Command group mask. */ -#define TWI_MASTER_CMD_gp 0 /* Command group position. */ -#define TWI_MASTER_CMD0_bm (1<<0) /* Command bit 0 mask. */ -#define TWI_MASTER_CMD0_bp 0 /* Command bit 0 position. */ -#define TWI_MASTER_CMD1_bm (1<<1) /* Command bit 1 mask. */ -#define TWI_MASTER_CMD1_bp 1 /* Command bit 1 position. */ - - -/* TWI_MASTER.STATUS bit masks and bit positions */ -#define TWI_MASTER_RIF_bm 0x80 /* Read Interrupt Flag bit mask. */ -#define TWI_MASTER_RIF_bp 7 /* Read Interrupt Flag bit position. */ - -#define TWI_MASTER_WIF_bm 0x40 /* Write Interrupt Flag bit mask. */ -#define TWI_MASTER_WIF_bp 6 /* Write Interrupt Flag bit position. */ - -#define TWI_MASTER_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ -#define TWI_MASTER_CLKHOLD_bp 5 /* Clock Hold bit position. */ - -#define TWI_MASTER_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ -#define TWI_MASTER_RXACK_bp 4 /* Received Acknowledge bit position. */ - -#define TWI_MASTER_ARBLOST_bm 0x08 /* Arbitration Lost bit mask. */ -#define TWI_MASTER_ARBLOST_bp 3 /* Arbitration Lost bit position. */ - -#define TWI_MASTER_BUSERR_bm 0x04 /* Bus Error bit mask. */ -#define TWI_MASTER_BUSERR_bp 2 /* Bus Error bit position. */ - -#define TWI_MASTER_BUSSTATE_gm 0x03 /* Bus State group mask. */ -#define TWI_MASTER_BUSSTATE_gp 0 /* Bus State group position. */ -#define TWI_MASTER_BUSSTATE0_bm (1<<0) /* Bus State bit 0 mask. */ -#define TWI_MASTER_BUSSTATE0_bp 0 /* Bus State bit 0 position. */ -#define TWI_MASTER_BUSSTATE1_bm (1<<1) /* Bus State bit 1 mask. */ -#define TWI_MASTER_BUSSTATE1_bp 1 /* Bus State bit 1 position. */ - - -/* TWI_SLAVE.CTRLA bit masks and bit positions */ -#define TWI_SLAVE_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ -#define TWI_SLAVE_INTLVL_gp 6 /* Interrupt Level group position. */ -#define TWI_SLAVE_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ -#define TWI_SLAVE_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ -#define TWI_SLAVE_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ -#define TWI_SLAVE_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ - -#define TWI_SLAVE_DIEN_bm 0x20 /* Data Interrupt Enable bit mask. */ -#define TWI_SLAVE_DIEN_bp 5 /* Data Interrupt Enable bit position. */ - -#define TWI_SLAVE_APIEN_bm 0x10 /* Address/Stop Interrupt Enable bit mask. */ -#define TWI_SLAVE_APIEN_bp 4 /* Address/Stop Interrupt Enable bit position. */ - -#define TWI_SLAVE_ENABLE_bm 0x08 /* Enable TWI Slave bit mask. */ -#define TWI_SLAVE_ENABLE_bp 3 /* Enable TWI Slave bit position. */ - -#define TWI_SLAVE_PIEN_bm 0x04 /* Stop Interrupt Enable bit mask. */ -#define TWI_SLAVE_PIEN_bp 2 /* Stop Interrupt Enable bit position. */ - -#define TWI_SLAVE_PMEN_bm 0x02 /* Promiscuous Mode Enable bit mask. */ -#define TWI_SLAVE_PMEN_bp 1 /* Promiscuous Mode Enable bit position. */ - -#define TWI_SLAVE_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ -#define TWI_SLAVE_SMEN_bp 0 /* Smart Mode Enable bit position. */ - - -/* TWI_SLAVE.CTRLB bit masks and bit positions */ -#define TWI_SLAVE_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ -#define TWI_SLAVE_ACKACT_bp 2 /* Acknowledge Action bit position. */ - -#define TWI_SLAVE_CMD_gm 0x03 /* Command group mask. */ -#define TWI_SLAVE_CMD_gp 0 /* Command group position. */ -#define TWI_SLAVE_CMD0_bm (1<<0) /* Command bit 0 mask. */ -#define TWI_SLAVE_CMD0_bp 0 /* Command bit 0 position. */ -#define TWI_SLAVE_CMD1_bm (1<<1) /* Command bit 1 mask. */ -#define TWI_SLAVE_CMD1_bp 1 /* Command bit 1 position. */ - - -/* TWI_SLAVE.STATUS bit masks and bit positions */ -#define TWI_SLAVE_DIF_bm 0x80 /* Data Interrupt Flag bit mask. */ -#define TWI_SLAVE_DIF_bp 7 /* Data Interrupt Flag bit position. */ - -#define TWI_SLAVE_APIF_bm 0x40 /* Address/Stop Interrupt Flag bit mask. */ -#define TWI_SLAVE_APIF_bp 6 /* Address/Stop Interrupt Flag bit position. */ - -#define TWI_SLAVE_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ -#define TWI_SLAVE_CLKHOLD_bp 5 /* Clock Hold bit position. */ - -#define TWI_SLAVE_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ -#define TWI_SLAVE_RXACK_bp 4 /* Received Acknowledge bit position. */ - -#define TWI_SLAVE_COLL_bm 0x08 /* Collision bit mask. */ -#define TWI_SLAVE_COLL_bp 3 /* Collision bit position. */ - -#define TWI_SLAVE_BUSERR_bm 0x04 /* Bus Error bit mask. */ -#define TWI_SLAVE_BUSERR_bp 2 /* Bus Error bit position. */ - -#define TWI_SLAVE_DIR_bm 0x02 /* Read/Write Direction bit mask. */ -#define TWI_SLAVE_DIR_bp 1 /* Read/Write Direction bit position. */ - -#define TWI_SLAVE_AP_bm 0x01 /* Slave Address or Stop bit mask. */ -#define TWI_SLAVE_AP_bp 0 /* Slave Address or Stop bit position. */ - - -/* TWI_SLAVE.ADDRMASK bit masks and bit positions */ -#define TWI_SLAVE_ADDRMASK_gm 0xFE /* Address Mask group mask. */ -#define TWI_SLAVE_ADDRMASK_gp 1 /* Address Mask group position. */ -#define TWI_SLAVE_ADDRMASK0_bm (1<<1) /* Address Mask bit 0 mask. */ -#define TWI_SLAVE_ADDRMASK0_bp 1 /* Address Mask bit 0 position. */ -#define TWI_SLAVE_ADDRMASK1_bm (1<<2) /* Address Mask bit 1 mask. */ -#define TWI_SLAVE_ADDRMASK1_bp 2 /* Address Mask bit 1 position. */ -#define TWI_SLAVE_ADDRMASK2_bm (1<<3) /* Address Mask bit 2 mask. */ -#define TWI_SLAVE_ADDRMASK2_bp 3 /* Address Mask bit 2 position. */ -#define TWI_SLAVE_ADDRMASK3_bm (1<<4) /* Address Mask bit 3 mask. */ -#define TWI_SLAVE_ADDRMASK3_bp 4 /* Address Mask bit 3 position. */ -#define TWI_SLAVE_ADDRMASK4_bm (1<<5) /* Address Mask bit 4 mask. */ -#define TWI_SLAVE_ADDRMASK4_bp 5 /* Address Mask bit 4 position. */ -#define TWI_SLAVE_ADDRMASK5_bm (1<<6) /* Address Mask bit 5 mask. */ -#define TWI_SLAVE_ADDRMASK5_bp 6 /* Address Mask bit 5 position. */ -#define TWI_SLAVE_ADDRMASK6_bm (1<<7) /* Address Mask bit 6 mask. */ -#define TWI_SLAVE_ADDRMASK6_bp 7 /* Address Mask bit 6 position. */ - -#define TWI_SLAVE_ADDREN_bm 0x01 /* Address Enable bit mask. */ -#define TWI_SLAVE_ADDREN_bp 0 /* Address Enable bit position. */ - - -/* TWI.CTRL bit masks and bit positions */ -#define TWI_SDAHOLD_bm 0x02 /* SDA Hold Time Enable bit mask. */ -#define TWI_SDAHOLD_bp 1 /* SDA Hold Time Enable bit position. */ - -#define TWI_EDIEN_bm 0x01 /* External Driver Interface Enable bit mask. */ -#define TWI_EDIEN_bp 0 /* External Driver Interface Enable bit position. */ - - -/* PORT - Port Configuration */ -/* PORTCFG.VPCTRLA bit masks and bit positions */ -#define PORTCFG_VP1MAP_gm 0xF0 /* Virtual Port 1 Mapping group mask. */ -#define PORTCFG_VP1MAP_gp 4 /* Virtual Port 1 Mapping group position. */ -#define PORTCFG_VP1MAP0_bm (1<<4) /* Virtual Port 1 Mapping bit 0 mask. */ -#define PORTCFG_VP1MAP0_bp 4 /* Virtual Port 1 Mapping bit 0 position. */ -#define PORTCFG_VP1MAP1_bm (1<<5) /* Virtual Port 1 Mapping bit 1 mask. */ -#define PORTCFG_VP1MAP1_bp 5 /* Virtual Port 1 Mapping bit 1 position. */ -#define PORTCFG_VP1MAP2_bm (1<<6) /* Virtual Port 1 Mapping bit 2 mask. */ -#define PORTCFG_VP1MAP2_bp 6 /* Virtual Port 1 Mapping bit 2 position. */ -#define PORTCFG_VP1MAP3_bm (1<<7) /* Virtual Port 1 Mapping bit 3 mask. */ -#define PORTCFG_VP1MAP3_bp 7 /* Virtual Port 1 Mapping bit 3 position. */ - -#define PORTCFG_VP0MAP_gm 0x0F /* Virtual Port 0 Mapping group mask. */ -#define PORTCFG_VP0MAP_gp 0 /* Virtual Port 0 Mapping group position. */ -#define PORTCFG_VP0MAP0_bm (1<<0) /* Virtual Port 0 Mapping bit 0 mask. */ -#define PORTCFG_VP0MAP0_bp 0 /* Virtual Port 0 Mapping bit 0 position. */ -#define PORTCFG_VP0MAP1_bm (1<<1) /* Virtual Port 0 Mapping bit 1 mask. */ -#define PORTCFG_VP0MAP1_bp 1 /* Virtual Port 0 Mapping bit 1 position. */ -#define PORTCFG_VP0MAP2_bm (1<<2) /* Virtual Port 0 Mapping bit 2 mask. */ -#define PORTCFG_VP0MAP2_bp 2 /* Virtual Port 0 Mapping bit 2 position. */ -#define PORTCFG_VP0MAP3_bm (1<<3) /* Virtual Port 0 Mapping bit 3 mask. */ -#define PORTCFG_VP0MAP3_bp 3 /* Virtual Port 0 Mapping bit 3 position. */ - - -/* PORTCFG.VPCTRLB bit masks and bit positions */ -#define PORTCFG_VP3MAP_gm 0xF0 /* Virtual Port 3 Mapping group mask. */ -#define PORTCFG_VP3MAP_gp 4 /* Virtual Port 3 Mapping group position. */ -#define PORTCFG_VP3MAP0_bm (1<<4) /* Virtual Port 3 Mapping bit 0 mask. */ -#define PORTCFG_VP3MAP0_bp 4 /* Virtual Port 3 Mapping bit 0 position. */ -#define PORTCFG_VP3MAP1_bm (1<<5) /* Virtual Port 3 Mapping bit 1 mask. */ -#define PORTCFG_VP3MAP1_bp 5 /* Virtual Port 3 Mapping bit 1 position. */ -#define PORTCFG_VP3MAP2_bm (1<<6) /* Virtual Port 3 Mapping bit 2 mask. */ -#define PORTCFG_VP3MAP2_bp 6 /* Virtual Port 3 Mapping bit 2 position. */ -#define PORTCFG_VP3MAP3_bm (1<<7) /* Virtual Port 3 Mapping bit 3 mask. */ -#define PORTCFG_VP3MAP3_bp 7 /* Virtual Port 3 Mapping bit 3 position. */ - -#define PORTCFG_VP2MAP_gm 0x0F /* Virtual Port 2 Mapping group mask. */ -#define PORTCFG_VP2MAP_gp 0 /* Virtual Port 2 Mapping group position. */ -#define PORTCFG_VP2MAP0_bm (1<<0) /* Virtual Port 2 Mapping bit 0 mask. */ -#define PORTCFG_VP2MAP0_bp 0 /* Virtual Port 2 Mapping bit 0 position. */ -#define PORTCFG_VP2MAP1_bm (1<<1) /* Virtual Port 2 Mapping bit 1 mask. */ -#define PORTCFG_VP2MAP1_bp 1 /* Virtual Port 2 Mapping bit 1 position. */ -#define PORTCFG_VP2MAP2_bm (1<<2) /* Virtual Port 2 Mapping bit 2 mask. */ -#define PORTCFG_VP2MAP2_bp 2 /* Virtual Port 2 Mapping bit 2 position. */ -#define PORTCFG_VP2MAP3_bm (1<<3) /* Virtual Port 2 Mapping bit 3 mask. */ -#define PORTCFG_VP2MAP3_bp 3 /* Virtual Port 2 Mapping bit 3 position. */ - - -/* PORTCFG.CLKEVOUT bit masks and bit positions */ -#define PORTCFG_CLKOUT_gm 0x03 /* Clock Output Port group mask. */ -#define PORTCFG_CLKOUT_gp 0 /* Clock Output Port group position. */ -#define PORTCFG_CLKOUT0_bm (1<<0) /* Clock Output Port bit 0 mask. */ -#define PORTCFG_CLKOUT0_bp 0 /* Clock Output Port bit 0 position. */ -#define PORTCFG_CLKOUT1_bm (1<<1) /* Clock Output Port bit 1 mask. */ -#define PORTCFG_CLKOUT1_bp 1 /* Clock Output Port bit 1 position. */ - -#define PORTCFG_EVOUT_gm 0x30 /* Event Output Port group mask. */ -#define PORTCFG_EVOUT_gp 4 /* Event Output Port group position. */ -#define PORTCFG_EVOUT0_bm (1<<4) /* Event Output Port bit 0 mask. */ -#define PORTCFG_EVOUT0_bp 4 /* Event Output Port bit 0 position. */ -#define PORTCFG_EVOUT1_bm (1<<5) /* Event Output Port bit 1 mask. */ -#define PORTCFG_EVOUT1_bp 5 /* Event Output Port bit 1 position. */ - - -/* VPORT.INTFLAGS bit masks and bit positions */ -#define VPORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ -#define VPORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ - -#define VPORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ -#define VPORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ - - -/* PORT.INTCTRL bit masks and bit positions */ -#define PORT_INT1LVL_gm 0x0C /* Port Interrupt 1 Level group mask. */ -#define PORT_INT1LVL_gp 2 /* Port Interrupt 1 Level group position. */ -#define PORT_INT1LVL0_bm (1<<2) /* Port Interrupt 1 Level bit 0 mask. */ -#define PORT_INT1LVL0_bp 2 /* Port Interrupt 1 Level bit 0 position. */ -#define PORT_INT1LVL1_bm (1<<3) /* Port Interrupt 1 Level bit 1 mask. */ -#define PORT_INT1LVL1_bp 3 /* Port Interrupt 1 Level bit 1 position. */ - -#define PORT_INT0LVL_gm 0x03 /* Port Interrupt 0 Level group mask. */ -#define PORT_INT0LVL_gp 0 /* Port Interrupt 0 Level group position. */ -#define PORT_INT0LVL0_bm (1<<0) /* Port Interrupt 0 Level bit 0 mask. */ -#define PORT_INT0LVL0_bp 0 /* Port Interrupt 0 Level bit 0 position. */ -#define PORT_INT0LVL1_bm (1<<1) /* Port Interrupt 0 Level bit 1 mask. */ -#define PORT_INT0LVL1_bp 1 /* Port Interrupt 0 Level bit 1 position. */ - - -/* PORT.INTFLAGS bit masks and bit positions */ -#define PORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ -#define PORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ - -#define PORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ -#define PORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ - - -/* PORT.PIN0CTRL bit masks and bit positions */ -#define PORT_SRLEN_bm 0x80 /* Slew Rate Enable bit mask. */ -#define PORT_SRLEN_bp 7 /* Slew Rate Enable bit position. */ - -#define PORT_INVEN_bm 0x40 /* Inverted I/O Enable bit mask. */ -#define PORT_INVEN_bp 6 /* Inverted I/O Enable bit position. */ - -#define PORT_OPC_gm 0x38 /* Output/Pull Configuration group mask. */ -#define PORT_OPC_gp 3 /* Output/Pull Configuration group position. */ -#define PORT_OPC0_bm (1<<3) /* Output/Pull Configuration bit 0 mask. */ -#define PORT_OPC0_bp 3 /* Output/Pull Configuration bit 0 position. */ -#define PORT_OPC1_bm (1<<4) /* Output/Pull Configuration bit 1 mask. */ -#define PORT_OPC1_bp 4 /* Output/Pull Configuration bit 1 position. */ -#define PORT_OPC2_bm (1<<5) /* Output/Pull Configuration bit 2 mask. */ -#define PORT_OPC2_bp 5 /* Output/Pull Configuration bit 2 position. */ - -#define PORT_ISC_gm 0x07 /* Input/Sense Configuration group mask. */ -#define PORT_ISC_gp 0 /* Input/Sense Configuration group position. */ -#define PORT_ISC0_bm (1<<0) /* Input/Sense Configuration bit 0 mask. */ -#define PORT_ISC0_bp 0 /* Input/Sense Configuration bit 0 position. */ -#define PORT_ISC1_bm (1<<1) /* Input/Sense Configuration bit 1 mask. */ -#define PORT_ISC1_bp 1 /* Input/Sense Configuration bit 1 position. */ -#define PORT_ISC2_bm (1<<2) /* Input/Sense Configuration bit 2 mask. */ -#define PORT_ISC2_bp 2 /* Input/Sense Configuration bit 2 position. */ - - -/* PORT.PIN1CTRL bit masks and bit positions */ -/* PORT_SRLEN_bm Predefined. */ -/* PORT_SRLEN_bp Predefined. */ - -/* PORT_INVEN_bm Predefined. */ -/* PORT_INVEN_bp Predefined. */ - -/* PORT_OPC_gm Predefined. */ -/* PORT_OPC_gp Predefined. */ -/* PORT_OPC0_bm Predefined. */ -/* PORT_OPC0_bp Predefined. */ -/* PORT_OPC1_bm Predefined. */ -/* PORT_OPC1_bp Predefined. */ -/* PORT_OPC2_bm Predefined. */ -/* PORT_OPC2_bp Predefined. */ - -/* PORT_ISC_gm Predefined. */ -/* PORT_ISC_gp Predefined. */ -/* PORT_ISC0_bm Predefined. */ -/* PORT_ISC0_bp Predefined. */ -/* PORT_ISC1_bm Predefined. */ -/* PORT_ISC1_bp Predefined. */ -/* PORT_ISC2_bm Predefined. */ -/* PORT_ISC2_bp Predefined. */ - - -/* PORT.PIN2CTRL bit masks and bit positions */ -/* PORT_SRLEN_bm Predefined. */ -/* PORT_SRLEN_bp Predefined. */ - -/* PORT_INVEN_bm Predefined. */ -/* PORT_INVEN_bp Predefined. */ - -/* PORT_OPC_gm Predefined. */ -/* PORT_OPC_gp Predefined. */ -/* PORT_OPC0_bm Predefined. */ -/* PORT_OPC0_bp Predefined. */ -/* PORT_OPC1_bm Predefined. */ -/* PORT_OPC1_bp Predefined. */ -/* PORT_OPC2_bm Predefined. */ -/* PORT_OPC2_bp Predefined. */ - -/* PORT_ISC_gm Predefined. */ -/* PORT_ISC_gp Predefined. */ -/* PORT_ISC0_bm Predefined. */ -/* PORT_ISC0_bp Predefined. */ -/* PORT_ISC1_bm Predefined. */ -/* PORT_ISC1_bp Predefined. */ -/* PORT_ISC2_bm Predefined. */ -/* PORT_ISC2_bp Predefined. */ - - -/* PORT.PIN3CTRL bit masks and bit positions */ -/* PORT_SRLEN_bm Predefined. */ -/* PORT_SRLEN_bp Predefined. */ - -/* PORT_INVEN_bm Predefined. */ -/* PORT_INVEN_bp Predefined. */ - -/* PORT_OPC_gm Predefined. */ -/* PORT_OPC_gp Predefined. */ -/* PORT_OPC0_bm Predefined. */ -/* PORT_OPC0_bp Predefined. */ -/* PORT_OPC1_bm Predefined. */ -/* PORT_OPC1_bp Predefined. */ -/* PORT_OPC2_bm Predefined. */ -/* PORT_OPC2_bp Predefined. */ - -/* PORT_ISC_gm Predefined. */ -/* PORT_ISC_gp Predefined. */ -/* PORT_ISC0_bm Predefined. */ -/* PORT_ISC0_bp Predefined. */ -/* PORT_ISC1_bm Predefined. */ -/* PORT_ISC1_bp Predefined. */ -/* PORT_ISC2_bm Predefined. */ -/* PORT_ISC2_bp Predefined. */ - - -/* PORT.PIN4CTRL bit masks and bit positions */ -/* PORT_SRLEN_bm Predefined. */ -/* PORT_SRLEN_bp Predefined. */ - -/* PORT_INVEN_bm Predefined. */ -/* PORT_INVEN_bp Predefined. */ - -/* PORT_OPC_gm Predefined. */ -/* PORT_OPC_gp Predefined. */ -/* PORT_OPC0_bm Predefined. */ -/* PORT_OPC0_bp Predefined. */ -/* PORT_OPC1_bm Predefined. */ -/* PORT_OPC1_bp Predefined. */ -/* PORT_OPC2_bm Predefined. */ -/* PORT_OPC2_bp Predefined. */ - -/* PORT_ISC_gm Predefined. */ -/* PORT_ISC_gp Predefined. */ -/* PORT_ISC0_bm Predefined. */ -/* PORT_ISC0_bp Predefined. */ -/* PORT_ISC1_bm Predefined. */ -/* PORT_ISC1_bp Predefined. */ -/* PORT_ISC2_bm Predefined. */ -/* PORT_ISC2_bp Predefined. */ - - -/* PORT.PIN5CTRL bit masks and bit positions */ -/* PORT_SRLEN_bm Predefined. */ -/* PORT_SRLEN_bp Predefined. */ - -/* PORT_INVEN_bm Predefined. */ -/* PORT_INVEN_bp Predefined. */ - -/* PORT_OPC_gm Predefined. */ -/* PORT_OPC_gp Predefined. */ -/* PORT_OPC0_bm Predefined. */ -/* PORT_OPC0_bp Predefined. */ -/* PORT_OPC1_bm Predefined. */ -/* PORT_OPC1_bp Predefined. */ -/* PORT_OPC2_bm Predefined. */ -/* PORT_OPC2_bp Predefined. */ - -/* PORT_ISC_gm Predefined. */ -/* PORT_ISC_gp Predefined. */ -/* PORT_ISC0_bm Predefined. */ -/* PORT_ISC0_bp Predefined. */ -/* PORT_ISC1_bm Predefined. */ -/* PORT_ISC1_bp Predefined. */ -/* PORT_ISC2_bm Predefined. */ -/* PORT_ISC2_bp Predefined. */ - - -/* PORT.PIN6CTRL bit masks and bit positions */ -/* PORT_SRLEN_bm Predefined. */ -/* PORT_SRLEN_bp Predefined. */ - -/* PORT_INVEN_bm Predefined. */ -/* PORT_INVEN_bp Predefined. */ - -/* PORT_OPC_gm Predefined. */ -/* PORT_OPC_gp Predefined. */ -/* PORT_OPC0_bm Predefined. */ -/* PORT_OPC0_bp Predefined. */ -/* PORT_OPC1_bm Predefined. */ -/* PORT_OPC1_bp Predefined. */ -/* PORT_OPC2_bm Predefined. */ -/* PORT_OPC2_bp Predefined. */ - -/* PORT_ISC_gm Predefined. */ -/* PORT_ISC_gp Predefined. */ -/* PORT_ISC0_bm Predefined. */ -/* PORT_ISC0_bp Predefined. */ -/* PORT_ISC1_bm Predefined. */ -/* PORT_ISC1_bp Predefined. */ -/* PORT_ISC2_bm Predefined. */ -/* PORT_ISC2_bp Predefined. */ - - -/* PORT.PIN7CTRL bit masks and bit positions */ -/* PORT_SRLEN_bm Predefined. */ -/* PORT_SRLEN_bp Predefined. */ - -/* PORT_INVEN_bm Predefined. */ -/* PORT_INVEN_bp Predefined. */ - -/* PORT_OPC_gm Predefined. */ -/* PORT_OPC_gp Predefined. */ -/* PORT_OPC0_bm Predefined. */ -/* PORT_OPC0_bp Predefined. */ -/* PORT_OPC1_bm Predefined. */ -/* PORT_OPC1_bp Predefined. */ -/* PORT_OPC2_bm Predefined. */ -/* PORT_OPC2_bp Predefined. */ - -/* PORT_ISC_gm Predefined. */ -/* PORT_ISC_gp Predefined. */ -/* PORT_ISC0_bm Predefined. */ -/* PORT_ISC0_bp Predefined. */ -/* PORT_ISC1_bm Predefined. */ -/* PORT_ISC1_bp Predefined. */ -/* PORT_ISC2_bm Predefined. */ -/* PORT_ISC2_bp Predefined. */ - - -/* TC - 16-bit Timer/Counter With PWM */ -/* TC0.CTRLA bit masks and bit positions */ -#define TC0_CLKSEL_gm 0x0F /* Clock Selection group mask. */ -#define TC0_CLKSEL_gp 0 /* Clock Selection group position. */ -#define TC0_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ -#define TC0_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ -#define TC0_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ -#define TC0_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ -#define TC0_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ -#define TC0_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ -#define TC0_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ -#define TC0_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ - - -/* TC0.CTRLB bit masks and bit positions */ -#define TC0_CCDEN_bm 0x80 /* Compare or Capture D Enable bit mask. */ -#define TC0_CCDEN_bp 7 /* Compare or Capture D Enable bit position. */ - -#define TC0_CCCEN_bm 0x40 /* Compare or Capture C Enable bit mask. */ -#define TC0_CCCEN_bp 6 /* Compare or Capture C Enable bit position. */ - -#define TC0_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ -#define TC0_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ - -#define TC0_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ -#define TC0_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ - -#define TC0_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ -#define TC0_WGMODE_gp 0 /* Waveform generation mode group position. */ -#define TC0_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ -#define TC0_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ -#define TC0_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ -#define TC0_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ -#define TC0_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ -#define TC0_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ - - -/* TC0.CTRLC bit masks and bit positions */ -#define TC0_CMPD_bm 0x08 /* Compare D Output Value bit mask. */ -#define TC0_CMPD_bp 3 /* Compare D Output Value bit position. */ - -#define TC0_CMPC_bm 0x04 /* Compare C Output Value bit mask. */ -#define TC0_CMPC_bp 2 /* Compare C Output Value bit position. */ - -#define TC0_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ -#define TC0_CMPB_bp 1 /* Compare B Output Value bit position. */ - -#define TC0_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ -#define TC0_CMPA_bp 0 /* Compare A Output Value bit position. */ - - -/* TC0.CTRLD bit masks and bit positions */ -#define TC0_EVACT_gm 0xE0 /* Event Action group mask. */ -#define TC0_EVACT_gp 5 /* Event Action group position. */ -#define TC0_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ -#define TC0_EVACT0_bp 5 /* Event Action bit 0 position. */ -#define TC0_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ -#define TC0_EVACT1_bp 6 /* Event Action bit 1 position. */ -#define TC0_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ -#define TC0_EVACT2_bp 7 /* Event Action bit 2 position. */ - -#define TC0_EVDLY_bm 0x10 /* Event Delay bit mask. */ -#define TC0_EVDLY_bp 4 /* Event Delay bit position. */ - -#define TC0_EVSEL_gm 0x0F /* Event Source Select group mask. */ -#define TC0_EVSEL_gp 0 /* Event Source Select group position. */ -#define TC0_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ -#define TC0_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ -#define TC0_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ -#define TC0_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ -#define TC0_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ -#define TC0_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ -#define TC0_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ -#define TC0_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ - - -/* TC0.CTRLE bit masks and bit positions */ -#define TC0_DTHM_bm 0x02 /* Dead Time Hold Mode bit mask. */ -#define TC0_DTHM_bp 1 /* Dead Time Hold Mode bit position. */ - -#define TC0_BYTEM_bm 0x01 /* Byte Mode bit mask. */ -#define TC0_BYTEM_bp 0 /* Byte Mode bit position. */ - - -/* TC0.INTCTRLA bit masks and bit positions */ -#define TC0_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ -#define TC0_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ -#define TC0_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ -#define TC0_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ -#define TC0_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ -#define TC0_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ - -#define TC0_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ -#define TC0_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ -#define TC0_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ -#define TC0_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ -#define TC0_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ -#define TC0_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ - - -/* TC0.INTCTRLB bit masks and bit positions */ -#define TC0_CCDINTLVL_gm 0xC0 /* Compare or Capture D Interrupt Level group mask. */ -#define TC0_CCDINTLVL_gp 6 /* Compare or Capture D Interrupt Level group position. */ -#define TC0_CCDINTLVL0_bm (1<<6) /* Compare or Capture D Interrupt Level bit 0 mask. */ -#define TC0_CCDINTLVL0_bp 6 /* Compare or Capture D Interrupt Level bit 0 position. */ -#define TC0_CCDINTLVL1_bm (1<<7) /* Compare or Capture D Interrupt Level bit 1 mask. */ -#define TC0_CCDINTLVL1_bp 7 /* Compare or Capture D Interrupt Level bit 1 position. */ - -#define TC0_CCCINTLVL_gm 0x30 /* Compare or Capture C Interrupt Level group mask. */ -#define TC0_CCCINTLVL_gp 4 /* Compare or Capture C Interrupt Level group position. */ -#define TC0_CCCINTLVL0_bm (1<<4) /* Compare or Capture C Interrupt Level bit 0 mask. */ -#define TC0_CCCINTLVL0_bp 4 /* Compare or Capture C Interrupt Level bit 0 position. */ -#define TC0_CCCINTLVL1_bm (1<<5) /* Compare or Capture C Interrupt Level bit 1 mask. */ -#define TC0_CCCINTLVL1_bp 5 /* Compare or Capture C Interrupt Level bit 1 position. */ - -#define TC0_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ -#define TC0_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ -#define TC0_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ -#define TC0_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ -#define TC0_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ -#define TC0_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ - -#define TC0_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ -#define TC0_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ -#define TC0_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ -#define TC0_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ -#define TC0_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ -#define TC0_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ - - -/* TC0.CTRLFCLR bit masks and bit positions */ -#define TC0_CMD_gm 0x0C /* Command group mask. */ -#define TC0_CMD_gp 2 /* Command group position. */ -#define TC0_CMD0_bm (1<<2) /* Command bit 0 mask. */ -#define TC0_CMD0_bp 2 /* Command bit 0 position. */ -#define TC0_CMD1_bm (1<<3) /* Command bit 1 mask. */ -#define TC0_CMD1_bp 3 /* Command bit 1 position. */ - -#define TC0_LUPD_bm 0x02 /* Lock Update bit mask. */ -#define TC0_LUPD_bp 1 /* Lock Update bit position. */ - -#define TC0_DIR_bm 0x01 /* Direction bit mask. */ -#define TC0_DIR_bp 0 /* Direction bit position. */ - - -/* TC0.CTRLFSET bit masks and bit positions */ -/* TC0_CMD_gm Predefined. */ -/* TC0_CMD_gp Predefined. */ -/* TC0_CMD0_bm Predefined. */ -/* TC0_CMD0_bp Predefined. */ -/* TC0_CMD1_bm Predefined. */ -/* TC0_CMD1_bp Predefined. */ - -/* TC0_LUPD_bm Predefined. */ -/* TC0_LUPD_bp Predefined. */ - -/* TC0_DIR_bm Predefined. */ -/* TC0_DIR_bp Predefined. */ - - -/* TC0.CTRLGCLR bit masks and bit positions */ -#define TC0_CCDBV_bm 0x10 /* Compare or Capture D Buffer Valid bit mask. */ -#define TC0_CCDBV_bp 4 /* Compare or Capture D Buffer Valid bit position. */ - -#define TC0_CCCBV_bm 0x08 /* Compare or Capture C Buffer Valid bit mask. */ -#define TC0_CCCBV_bp 3 /* Compare or Capture C Buffer Valid bit position. */ - -#define TC0_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ -#define TC0_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ - -#define TC0_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ -#define TC0_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ - -#define TC0_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ -#define TC0_PERBV_bp 0 /* Period Buffer Valid bit position. */ - - -/* TC0.CTRLGSET bit masks and bit positions */ -/* TC0_CCDBV_bm Predefined. */ -/* TC0_CCDBV_bp Predefined. */ - -/* TC0_CCCBV_bm Predefined. */ -/* TC0_CCCBV_bp Predefined. */ - -/* TC0_CCBBV_bm Predefined. */ -/* TC0_CCBBV_bp Predefined. */ - -/* TC0_CCABV_bm Predefined. */ -/* TC0_CCABV_bp Predefined. */ - -/* TC0_PERBV_bm Predefined. */ -/* TC0_PERBV_bp Predefined. */ - - -/* TC0.INTFLAGS bit masks and bit positions */ -#define TC0_CCDIF_bm 0x80 /* Compare or Capture D Interrupt Flag bit mask. */ -#define TC0_CCDIF_bp 7 /* Compare or Capture D Interrupt Flag bit position. */ - -#define TC0_CCCIF_bm 0x40 /* Compare or Capture C Interrupt Flag bit mask. */ -#define TC0_CCCIF_bp 6 /* Compare or Capture C Interrupt Flag bit position. */ - -#define TC0_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ -#define TC0_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ - -#define TC0_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ -#define TC0_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ - -#define TC0_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ -#define TC0_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ - -#define TC0_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ -#define TC0_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ - - -/* TC1.CTRLA bit masks and bit positions */ -#define TC1_CLKSEL_gm 0x0F /* Clock Selection group mask. */ -#define TC1_CLKSEL_gp 0 /* Clock Selection group position. */ -#define TC1_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ -#define TC1_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ -#define TC1_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ -#define TC1_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ -#define TC1_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ -#define TC1_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ -#define TC1_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ -#define TC1_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ - - -/* TC1.CTRLB bit masks and bit positions */ -#define TC1_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ -#define TC1_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ - -#define TC1_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ -#define TC1_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ - -#define TC1_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ -#define TC1_WGMODE_gp 0 /* Waveform generation mode group position. */ -#define TC1_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ -#define TC1_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ -#define TC1_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ -#define TC1_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ -#define TC1_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ -#define TC1_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ - - -/* TC1.CTRLC bit masks and bit positions */ -#define TC1_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ -#define TC1_CMPB_bp 1 /* Compare B Output Value bit position. */ - -#define TC1_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ -#define TC1_CMPA_bp 0 /* Compare A Output Value bit position. */ - - -/* TC1.CTRLD bit masks and bit positions */ -#define TC1_EVACT_gm 0xE0 /* Event Action group mask. */ -#define TC1_EVACT_gp 5 /* Event Action group position. */ -#define TC1_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ -#define TC1_EVACT0_bp 5 /* Event Action bit 0 position. */ -#define TC1_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ -#define TC1_EVACT1_bp 6 /* Event Action bit 1 position. */ -#define TC1_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ -#define TC1_EVACT2_bp 7 /* Event Action bit 2 position. */ - -#define TC1_EVDLY_bm 0x10 /* Event Delay bit mask. */ -#define TC1_EVDLY_bp 4 /* Event Delay bit position. */ - -#define TC1_EVSEL_gm 0x0F /* Event Source Select group mask. */ -#define TC1_EVSEL_gp 0 /* Event Source Select group position. */ -#define TC1_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ -#define TC1_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ -#define TC1_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ -#define TC1_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ -#define TC1_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ -#define TC1_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ -#define TC1_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ -#define TC1_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ - - -/* TC1.CTRLE bit masks and bit positions */ -#define TC1_DTHM_bm 0x02 /* Dead Time Hold Mode bit mask. */ -#define TC1_DTHM_bp 1 /* Dead Time Hold Mode bit position. */ - -#define TC1_BYTEM_bm 0x01 /* Byte Mode bit mask. */ -#define TC1_BYTEM_bp 0 /* Byte Mode bit position. */ - - -/* TC1.INTCTRLA bit masks and bit positions */ -#define TC1_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ -#define TC1_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ -#define TC1_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ -#define TC1_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ -#define TC1_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ -#define TC1_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ - -#define TC1_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ -#define TC1_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ -#define TC1_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ -#define TC1_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ -#define TC1_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ -#define TC1_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ - - -/* TC1.INTCTRLB bit masks and bit positions */ -#define TC1_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ -#define TC1_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ -#define TC1_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ -#define TC1_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ -#define TC1_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ -#define TC1_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ - -#define TC1_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ -#define TC1_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ -#define TC1_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ -#define TC1_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ -#define TC1_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ -#define TC1_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ - - -/* TC1.CTRLFCLR bit masks and bit positions */ -#define TC1_CMD_gm 0x0C /* Command group mask. */ -#define TC1_CMD_gp 2 /* Command group position. */ -#define TC1_CMD0_bm (1<<2) /* Command bit 0 mask. */ -#define TC1_CMD0_bp 2 /* Command bit 0 position. */ -#define TC1_CMD1_bm (1<<3) /* Command bit 1 mask. */ -#define TC1_CMD1_bp 3 /* Command bit 1 position. */ - -#define TC1_LUPD_bm 0x02 /* Lock Update bit mask. */ -#define TC1_LUPD_bp 1 /* Lock Update bit position. */ - -#define TC1_DIR_bm 0x01 /* Direction bit mask. */ -#define TC1_DIR_bp 0 /* Direction bit position. */ - - -/* TC1.CTRLFSET bit masks and bit positions */ -/* TC1_CMD_gm Predefined. */ -/* TC1_CMD_gp Predefined. */ -/* TC1_CMD0_bm Predefined. */ -/* TC1_CMD0_bp Predefined. */ -/* TC1_CMD1_bm Predefined. */ -/* TC1_CMD1_bp Predefined. */ - -/* TC1_LUPD_bm Predefined. */ -/* TC1_LUPD_bp Predefined. */ - -/* TC1_DIR_bm Predefined. */ -/* TC1_DIR_bp Predefined. */ - - -/* TC1.CTRLGCLR bit masks and bit positions */ -#define TC1_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ -#define TC1_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ - -#define TC1_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ -#define TC1_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ - -#define TC1_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ -#define TC1_PERBV_bp 0 /* Period Buffer Valid bit position. */ - - -/* TC1.CTRLGSET bit masks and bit positions */ -/* TC1_CCBBV_bm Predefined. */ -/* TC1_CCBBV_bp Predefined. */ - -/* TC1_CCABV_bm Predefined. */ -/* TC1_CCABV_bp Predefined. */ - -/* TC1_PERBV_bm Predefined. */ -/* TC1_PERBV_bp Predefined. */ - - -/* TC1.INTFLAGS bit masks and bit positions */ -#define TC1_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ -#define TC1_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ - -#define TC1_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ -#define TC1_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ - -#define TC1_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ -#define TC1_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ - -#define TC1_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ -#define TC1_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ - - -/* AWEX.CTRL bit masks and bit positions */ -#define AWEX_PGM_bm 0x20 /* Pattern Generation Mode bit mask. */ -#define AWEX_PGM_bp 5 /* Pattern Generation Mode bit position. */ - -#define AWEX_CWCM_bm 0x10 /* Common Waveform Channel Mode bit mask. */ -#define AWEX_CWCM_bp 4 /* Common Waveform Channel Mode bit position. */ - -#define AWEX_DTICCDEN_bm 0x08 /* Dead Time Insertion Compare Channel D Enable bit mask. */ -#define AWEX_DTICCDEN_bp 3 /* Dead Time Insertion Compare Channel D Enable bit position. */ - -#define AWEX_DTICCCEN_bm 0x04 /* Dead Time Insertion Compare Channel C Enable bit mask. */ -#define AWEX_DTICCCEN_bp 2 /* Dead Time Insertion Compare Channel C Enable bit position. */ - -#define AWEX_DTICCBEN_bm 0x02 /* Dead Time Insertion Compare Channel B Enable bit mask. */ -#define AWEX_DTICCBEN_bp 1 /* Dead Time Insertion Compare Channel B Enable bit position. */ - -#define AWEX_DTICCAEN_bm 0x01 /* Dead Time Insertion Compare Channel A Enable bit mask. */ -#define AWEX_DTICCAEN_bp 0 /* Dead Time Insertion Compare Channel A Enable bit position. */ - - -/* AWEX.FDCTRL bit masks and bit positions */ -#define AWEX_FDDBD_bm 0x10 /* Fault Detect on Disable Break Disable bit mask. */ -#define AWEX_FDDBD_bp 4 /* Fault Detect on Disable Break Disable bit position. */ - -#define AWEX_FDMODE_bm 0x04 /* Fault Detect Mode bit mask. */ -#define AWEX_FDMODE_bp 2 /* Fault Detect Mode bit position. */ - -#define AWEX_FDACT_gm 0x03 /* Fault Detect Action group mask. */ -#define AWEX_FDACT_gp 0 /* Fault Detect Action group position. */ -#define AWEX_FDACT0_bm (1<<0) /* Fault Detect Action bit 0 mask. */ -#define AWEX_FDACT0_bp 0 /* Fault Detect Action bit 0 position. */ -#define AWEX_FDACT1_bm (1<<1) /* Fault Detect Action bit 1 mask. */ -#define AWEX_FDACT1_bp 1 /* Fault Detect Action bit 1 position. */ - - -/* AWEX.STATUS bit masks and bit positions */ -#define AWEX_FDF_bm 0x04 /* Fault Detect Flag bit mask. */ -#define AWEX_FDF_bp 2 /* Fault Detect Flag bit position. */ - -#define AWEX_DTHSBUFV_bm 0x02 /* Dead Time High Side Buffer Valid bit mask. */ -#define AWEX_DTHSBUFV_bp 1 /* Dead Time High Side Buffer Valid bit position. */ - -#define AWEX_DTLSBUFV_bm 0x01 /* Dead Time Low Side Buffer Valid bit mask. */ -#define AWEX_DTLSBUFV_bp 0 /* Dead Time Low Side Buffer Valid bit position. */ - - -/* HIRES.CTRL bit masks and bit positions */ -#define HIRES_HREN_gm 0x03 /* High Resolution Enable group mask. */ -#define HIRES_HREN_gp 0 /* High Resolution Enable group position. */ -#define HIRES_HREN0_bm (1<<0) /* High Resolution Enable bit 0 mask. */ -#define HIRES_HREN0_bp 0 /* High Resolution Enable bit 0 position. */ -#define HIRES_HREN1_bm (1<<1) /* High Resolution Enable bit 1 mask. */ -#define HIRES_HREN1_bp 1 /* High Resolution Enable bit 1 position. */ - - -/* USART - Universal Asynchronous Receiver-Transmitter */ -/* USART.STATUS bit masks and bit positions */ -#define USART_RXCIF_bm 0x80 /* Receive Interrupt Flag bit mask. */ -#define USART_RXCIF_bp 7 /* Receive Interrupt Flag bit position. */ - -#define USART_TXCIF_bm 0x40 /* Transmit Interrupt Flag bit mask. */ -#define USART_TXCIF_bp 6 /* Transmit Interrupt Flag bit position. */ - -#define USART_DREIF_bm 0x20 /* Data Register Empty Flag bit mask. */ -#define USART_DREIF_bp 5 /* Data Register Empty Flag bit position. */ - -#define USART_FERR_bm 0x10 /* Frame Error bit mask. */ -#define USART_FERR_bp 4 /* Frame Error bit position. */ - -#define USART_BUFOVF_bm 0x08 /* Buffer Overflow bit mask. */ -#define USART_BUFOVF_bp 3 /* Buffer Overflow bit position. */ - -#define USART_PERR_bm 0x04 /* Parity Error bit mask. */ -#define USART_PERR_bp 2 /* Parity Error bit position. */ - -#define USART_RXB8_bm 0x01 /* Receive Bit 8 bit mask. */ -#define USART_RXB8_bp 0 /* Receive Bit 8 bit position. */ - - -/* USART.CTRLA bit masks and bit positions */ -#define USART_RXCINTLVL_gm 0x30 /* Receive Interrupt Level group mask. */ -#define USART_RXCINTLVL_gp 4 /* Receive Interrupt Level group position. */ -#define USART_RXCINTLVL0_bm (1<<4) /* Receive Interrupt Level bit 0 mask. */ -#define USART_RXCINTLVL0_bp 4 /* Receive Interrupt Level bit 0 position. */ -#define USART_RXCINTLVL1_bm (1<<5) /* Receive Interrupt Level bit 1 mask. */ -#define USART_RXCINTLVL1_bp 5 /* Receive Interrupt Level bit 1 position. */ - -#define USART_TXCINTLVL_gm 0x0C /* Transmit Interrupt Level group mask. */ -#define USART_TXCINTLVL_gp 2 /* Transmit Interrupt Level group position. */ -#define USART_TXCINTLVL0_bm (1<<2) /* Transmit Interrupt Level bit 0 mask. */ -#define USART_TXCINTLVL0_bp 2 /* Transmit Interrupt Level bit 0 position. */ -#define USART_TXCINTLVL1_bm (1<<3) /* Transmit Interrupt Level bit 1 mask. */ -#define USART_TXCINTLVL1_bp 3 /* Transmit Interrupt Level bit 1 position. */ - -#define USART_DREINTLVL_gm 0x03 /* Data Register Empty Interrupt Level group mask. */ -#define USART_DREINTLVL_gp 0 /* Data Register Empty Interrupt Level group position. */ -#define USART_DREINTLVL0_bm (1<<0) /* Data Register Empty Interrupt Level bit 0 mask. */ -#define USART_DREINTLVL0_bp 0 /* Data Register Empty Interrupt Level bit 0 position. */ -#define USART_DREINTLVL1_bm (1<<1) /* Data Register Empty Interrupt Level bit 1 mask. */ -#define USART_DREINTLVL1_bp 1 /* Data Register Empty Interrupt Level bit 1 position. */ - - -/* USART.CTRLB bit masks and bit positions */ -#define USART_RXEN_bm 0x10 /* Receiver Enable bit mask. */ -#define USART_RXEN_bp 4 /* Receiver Enable bit position. */ - -#define USART_TXEN_bm 0x08 /* Transmitter Enable bit mask. */ -#define USART_TXEN_bp 3 /* Transmitter Enable bit position. */ - -#define USART_CLK2X_bm 0x04 /* Double transmission speed bit mask. */ -#define USART_CLK2X_bp 2 /* Double transmission speed bit position. */ - -#define USART_MPCM_bm 0x02 /* Multi-processor Communication Mode bit mask. */ -#define USART_MPCM_bp 1 /* Multi-processor Communication Mode bit position. */ - -#define USART_TXB8_bm 0x01 /* Transmit bit 8 bit mask. */ -#define USART_TXB8_bp 0 /* Transmit bit 8 bit position. */ - - -/* USART.CTRLC bit masks and bit positions */ -#define USART_CMODE_gm 0xC0 /* Communication Mode group mask. */ -#define USART_CMODE_gp 6 /* Communication Mode group position. */ -#define USART_CMODE0_bm (1<<6) /* Communication Mode bit 0 mask. */ -#define USART_CMODE0_bp 6 /* Communication Mode bit 0 position. */ -#define USART_CMODE1_bm (1<<7) /* Communication Mode bit 1 mask. */ -#define USART_CMODE1_bp 7 /* Communication Mode bit 1 position. */ - -#define USART_PMODE_gm 0x30 /* Parity Mode group mask. */ -#define USART_PMODE_gp 4 /* Parity Mode group position. */ -#define USART_PMODE0_bm (1<<4) /* Parity Mode bit 0 mask. */ -#define USART_PMODE0_bp 4 /* Parity Mode bit 0 position. */ -#define USART_PMODE1_bm (1<<5) /* Parity Mode bit 1 mask. */ -#define USART_PMODE1_bp 5 /* Parity Mode bit 1 position. */ - -#define USART_SBMODE_bm 0x08 /* Stop Bit Mode bit mask. */ -#define USART_SBMODE_bp 3 /* Stop Bit Mode bit position. */ - -#define USART_CHSIZE_gm 0x07 /* Character Size group mask. */ -#define USART_CHSIZE_gp 0 /* Character Size group position. */ -#define USART_CHSIZE0_bm (1<<0) /* Character Size bit 0 mask. */ -#define USART_CHSIZE0_bp 0 /* Character Size bit 0 position. */ -#define USART_CHSIZE1_bm (1<<1) /* Character Size bit 1 mask. */ -#define USART_CHSIZE1_bp 1 /* Character Size bit 1 position. */ -#define USART_CHSIZE2_bm (1<<2) /* Character Size bit 2 mask. */ -#define USART_CHSIZE2_bp 2 /* Character Size bit 2 position. */ - - -/* USART.BAUDCTRLA bit masks and bit positions */ -#define USART_BSEL_gm 0xFF /* Baud Rate Selection Bits [7:0] group mask. */ -#define USART_BSEL_gp 0 /* Baud Rate Selection Bits [7:0] group position. */ -#define USART_BSEL0_bm (1<<0) /* Baud Rate Selection Bits [7:0] bit 0 mask. */ -#define USART_BSEL0_bp 0 /* Baud Rate Selection Bits [7:0] bit 0 position. */ -#define USART_BSEL1_bm (1<<1) /* Baud Rate Selection Bits [7:0] bit 1 mask. */ -#define USART_BSEL1_bp 1 /* Baud Rate Selection Bits [7:0] bit 1 position. */ -#define USART_BSEL2_bm (1<<2) /* Baud Rate Selection Bits [7:0] bit 2 mask. */ -#define USART_BSEL2_bp 2 /* Baud Rate Selection Bits [7:0] bit 2 position. */ -#define USART_BSEL3_bm (1<<3) /* Baud Rate Selection Bits [7:0] bit 3 mask. */ -#define USART_BSEL3_bp 3 /* Baud Rate Selection Bits [7:0] bit 3 position. */ -#define USART_BSEL4_bm (1<<4) /* Baud Rate Selection Bits [7:0] bit 4 mask. */ -#define USART_BSEL4_bp 4 /* Baud Rate Selection Bits [7:0] bit 4 position. */ -#define USART_BSEL5_bm (1<<5) /* Baud Rate Selection Bits [7:0] bit 5 mask. */ -#define USART_BSEL5_bp 5 /* Baud Rate Selection Bits [7:0] bit 5 position. */ -#define USART_BSEL6_bm (1<<6) /* Baud Rate Selection Bits [7:0] bit 6 mask. */ -#define USART_BSEL6_bp 6 /* Baud Rate Selection Bits [7:0] bit 6 position. */ -#define USART_BSEL7_bm (1<<7) /* Baud Rate Selection Bits [7:0] bit 7 mask. */ -#define USART_BSEL7_bp 7 /* Baud Rate Selection Bits [7:0] bit 7 position. */ - - -/* USART.BAUDCTRLB bit masks and bit positions */ -#define USART_BSCALE_gm 0xF0 /* Baud Rate Scale group mask. */ -#define USART_BSCALE_gp 4 /* Baud Rate Scale group position. */ -#define USART_BSCALE0_bm (1<<4) /* Baud Rate Scale bit 0 mask. */ -#define USART_BSCALE0_bp 4 /* Baud Rate Scale bit 0 position. */ -#define USART_BSCALE1_bm (1<<5) /* Baud Rate Scale bit 1 mask. */ -#define USART_BSCALE1_bp 5 /* Baud Rate Scale bit 1 position. */ -#define USART_BSCALE2_bm (1<<6) /* Baud Rate Scale bit 2 mask. */ -#define USART_BSCALE2_bp 6 /* Baud Rate Scale bit 2 position. */ -#define USART_BSCALE3_bm (1<<7) /* Baud Rate Scale bit 3 mask. */ -#define USART_BSCALE3_bp 7 /* Baud Rate Scale bit 3 position. */ - -/* USART_BSEL_gm Predefined. */ -/* USART_BSEL_gp Predefined. */ -/* USART_BSEL0_bm Predefined. */ -/* USART_BSEL0_bp Predefined. */ -/* USART_BSEL1_bm Predefined. */ -/* USART_BSEL1_bp Predefined. */ -/* USART_BSEL2_bm Predefined. */ -/* USART_BSEL2_bp Predefined. */ -/* USART_BSEL3_bm Predefined. */ -/* USART_BSEL3_bp Predefined. */ - - -/* SPI - Serial Peripheral Interface */ -/* SPI.CTRL bit masks and bit positions */ -#define SPI_CLK2X_bm 0x80 /* Enable Double Speed bit mask. */ -#define SPI_CLK2X_bp 7 /* Enable Double Speed bit position. */ - -#define SPI_ENABLE_bm 0x40 /* Enable Module bit mask. */ -#define SPI_ENABLE_bp 6 /* Enable Module bit position. */ - -#define SPI_DORD_bm 0x20 /* Data Order Setting bit mask. */ -#define SPI_DORD_bp 5 /* Data Order Setting bit position. */ - -#define SPI_MASTER_bm 0x10 /* Master Operation Enable bit mask. */ -#define SPI_MASTER_bp 4 /* Master Operation Enable bit position. */ - -#define SPI_MODE_gm 0x0C /* SPI Mode group mask. */ -#define SPI_MODE_gp 2 /* SPI Mode group position. */ -#define SPI_MODE0_bm (1<<2) /* SPI Mode bit 0 mask. */ -#define SPI_MODE0_bp 2 /* SPI Mode bit 0 position. */ -#define SPI_MODE1_bm (1<<3) /* SPI Mode bit 1 mask. */ -#define SPI_MODE1_bp 3 /* SPI Mode bit 1 position. */ - -#define SPI_PRESCALER_gm 0x03 /* Prescaler group mask. */ -#define SPI_PRESCALER_gp 0 /* Prescaler group position. */ -#define SPI_PRESCALER0_bm (1<<0) /* Prescaler bit 0 mask. */ -#define SPI_PRESCALER0_bp 0 /* Prescaler bit 0 position. */ -#define SPI_PRESCALER1_bm (1<<1) /* Prescaler bit 1 mask. */ -#define SPI_PRESCALER1_bp 1 /* Prescaler bit 1 position. */ - - -/* SPI.INTCTRL bit masks and bit positions */ -#define SPI_INTLVL_gm 0x03 /* Interrupt level group mask. */ -#define SPI_INTLVL_gp 0 /* Interrupt level group position. */ -#define SPI_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */ -#define SPI_INTLVL0_bp 0 /* Interrupt level bit 0 position. */ -#define SPI_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */ -#define SPI_INTLVL1_bp 1 /* Interrupt level bit 1 position. */ - - -/* SPI.STATUS bit masks and bit positions */ -#define SPI_IF_bm 0x80 /* Interrupt Flag bit mask. */ -#define SPI_IF_bp 7 /* Interrupt Flag bit position. */ - -#define SPI_WRCOL_bm 0x40 /* Write Collision bit mask. */ -#define SPI_WRCOL_bp 6 /* Write Collision bit position. */ - - -/* IRCOM - IR Communication Module */ -/* IRCOM.CTRL bit masks and bit positions */ -#define IRCOM_EVSEL_gm 0x0F /* Event Channel Select group mask. */ -#define IRCOM_EVSEL_gp 0 /* Event Channel Select group position. */ -#define IRCOM_EVSEL0_bm (1<<0) /* Event Channel Select bit 0 mask. */ -#define IRCOM_EVSEL0_bp 0 /* Event Channel Select bit 0 position. */ -#define IRCOM_EVSEL1_bm (1<<1) /* Event Channel Select bit 1 mask. */ -#define IRCOM_EVSEL1_bp 1 /* Event Channel Select bit 1 position. */ -#define IRCOM_EVSEL2_bm (1<<2) /* Event Channel Select bit 2 mask. */ -#define IRCOM_EVSEL2_bp 2 /* Event Channel Select bit 2 position. */ -#define IRCOM_EVSEL3_bm (1<<3) /* Event Channel Select bit 3 mask. */ -#define IRCOM_EVSEL3_bp 3 /* Event Channel Select bit 3 position. */ - - -/* AES - AES Module */ -/* AES.CTRL bit masks and bit positions */ -#define AES_START_bm 0x80 /* Start/Run bit mask. */ -#define AES_START_bp 7 /* Start/Run bit position. */ - -#define AES_AUTO_bm 0x40 /* Auto Start Trigger bit mask. */ -#define AES_AUTO_bp 6 /* Auto Start Trigger bit position. */ - -#define AES_RESET_bm 0x20 /* AES Software Reset bit mask. */ -#define AES_RESET_bp 5 /* AES Software Reset bit position. */ - -#define AES_DECRYPT_bm 0x10 /* Decryption / Direction bit mask. */ -#define AES_DECRYPT_bp 4 /* Decryption / Direction bit position. */ - -#define AES_XOR_bm 0x04 /* State XOR Load Enable bit mask. */ -#define AES_XOR_bp 2 /* State XOR Load Enable bit position. */ - - -/* AES.STATUS bit masks and bit positions */ -#define AES_ERROR_bm 0x80 /* AES Error bit mask. */ -#define AES_ERROR_bp 7 /* AES Error bit position. */ - -#define AES_SRIF_bm 0x01 /* State Ready Interrupt Flag bit mask. */ -#define AES_SRIF_bp 0 /* State Ready Interrupt Flag bit position. */ - - -/* AES.INTCTRL bit masks and bit positions */ -#define AES_INTLVL_gm 0x03 /* Interrupt level group mask. */ -#define AES_INTLVL_gp 0 /* Interrupt level group position. */ -#define AES_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */ -#define AES_INTLVL0_bp 0 /* Interrupt level bit 0 position. */ -#define AES_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */ -#define AES_INTLVL1_bp 1 /* Interrupt level bit 1 position. */ - - - -// Generic Port Pins - -#define PIN0_bm 0x01 -#define PIN0_bp 0 -#define PIN1_bm 0x02 -#define PIN1_bp 1 -#define PIN2_bm 0x04 -#define PIN2_bp 2 -#define PIN3_bm 0x08 -#define PIN3_bp 3 -#define PIN4_bm 0x10 -#define PIN4_bp 4 -#define PIN5_bm 0x20 -#define PIN5_bp 5 -#define PIN6_bm 0x40 -#define PIN6_bp 6 -#define PIN7_bm 0x80 -#define PIN7_bp 7 - - -/* ========== Interrupt Vector Definitions ========== */ -/* Vector 0 is the reset vector */ - -/* OSC interrupt vectors */ -#define OSC_XOSCF_vect_num 1 -#define OSC_XOSCF_vect _VECTOR(1) /* External Oscillator Failure Interrupt (NMI) */ - -/* PORTC interrupt vectors */ -#define PORTC_INT0_vect_num 2 -#define PORTC_INT0_vect _VECTOR(2) /* External Interrupt 0 */ -#define PORTC_INT1_vect_num 3 -#define PORTC_INT1_vect _VECTOR(3) /* External Interrupt 1 */ - -/* PORTR interrupt vectors */ -#define PORTR_INT0_vect_num 4 -#define PORTR_INT0_vect _VECTOR(4) /* External Interrupt 0 */ -#define PORTR_INT1_vect_num 5 -#define PORTR_INT1_vect _VECTOR(5) /* External Interrupt 1 */ - -/* DMA interrupt vectors */ -#define DMA_CH0_vect_num 6 -#define DMA_CH0_vect _VECTOR(6) /* Channel 0 Interrupt */ -#define DMA_CH1_vect_num 7 -#define DMA_CH1_vect _VECTOR(7) /* Channel 1 Interrupt */ -#define DMA_CH2_vect_num 8 -#define DMA_CH2_vect _VECTOR(8) /* Channel 2 Interrupt */ -#define DMA_CH3_vect_num 9 -#define DMA_CH3_vect _VECTOR(9) /* Channel 3 Interrupt */ - -/* RTC interrupt vectors */ -#define RTC_OVF_vect_num 10 -#define RTC_OVF_vect _VECTOR(10) /* Overflow Interrupt */ -#define RTC_COMP_vect_num 11 -#define RTC_COMP_vect _VECTOR(11) /* Compare Interrupt */ - -/* TWIC interrupt vectors */ -#define TWIC_TWIS_vect_num 12 -#define TWIC_TWIS_vect _VECTOR(12) /* TWI Slave Interrupt */ -#define TWIC_TWIM_vect_num 13 -#define TWIC_TWIM_vect _VECTOR(13) /* TWI Master Interrupt */ - -/* TCC0 interrupt vectors */ -#define TCC0_OVF_vect_num 14 -#define TCC0_OVF_vect _VECTOR(14) /* Overflow Interrupt */ -#define TCC0_ERR_vect_num 15 -#define TCC0_ERR_vect _VECTOR(15) /* Error Interrupt */ -#define TCC0_CCA_vect_num 16 -#define TCC0_CCA_vect _VECTOR(16) /* Compare or Capture A Interrupt */ -#define TCC0_CCB_vect_num 17 -#define TCC0_CCB_vect _VECTOR(17) /* Compare or Capture B Interrupt */ -#define TCC0_CCC_vect_num 18 -#define TCC0_CCC_vect _VECTOR(18) /* Compare or Capture C Interrupt */ -#define TCC0_CCD_vect_num 19 -#define TCC0_CCD_vect _VECTOR(19) /* Compare or Capture D Interrupt */ - -/* TCC1 interrupt vectors */ -#define TCC1_OVF_vect_num 20 -#define TCC1_OVF_vect _VECTOR(20) /* Overflow Interrupt */ -#define TCC1_ERR_vect_num 21 -#define TCC1_ERR_vect _VECTOR(21) /* Error Interrupt */ -#define TCC1_CCA_vect_num 22 -#define TCC1_CCA_vect _VECTOR(22) /* Compare or Capture A Interrupt */ -#define TCC1_CCB_vect_num 23 -#define TCC1_CCB_vect _VECTOR(23) /* Compare or Capture B Interrupt */ - -/* SPIC interrupt vectors */ -#define SPIC_INT_vect_num 24 -#define SPIC_INT_vect _VECTOR(24) /* SPI Interrupt */ - -/* USARTC0 interrupt vectors */ -#define USARTC0_RXC_vect_num 25 -#define USARTC0_RXC_vect _VECTOR(25) /* Reception Complete Interrupt */ -#define USARTC0_DRE_vect_num 26 -#define USARTC0_DRE_vect _VECTOR(26) /* Data Register Empty Interrupt */ -#define USARTC0_TXC_vect_num 27 -#define USARTC0_TXC_vect _VECTOR(27) /* Transmission Complete Interrupt */ - -/* USARTC1 interrupt vectors */ -#define USARTC1_RXC_vect_num 28 -#define USARTC1_RXC_vect _VECTOR(28) /* Reception Complete Interrupt */ -#define USARTC1_DRE_vect_num 29 -#define USARTC1_DRE_vect _VECTOR(29) /* Data Register Empty Interrupt */ -#define USARTC1_TXC_vect_num 30 -#define USARTC1_TXC_vect _VECTOR(30) /* Transmission Complete Interrupt */ - -/* AES interrupt vectors */ -#define AES_INT_vect_num 31 -#define AES_INT_vect _VECTOR(31) /* AES Interrupt */ - -/* NVM interrupt vectors */ -#define NVM_EE_vect_num 32 -#define NVM_EE_vect _VECTOR(32) /* EE Interrupt */ -#define NVM_SPM_vect_num 33 -#define NVM_SPM_vect _VECTOR(33) /* SPM Interrupt */ - -/* PORTB interrupt vectors */ -#define PORTB_INT0_vect_num 34 -#define PORTB_INT0_vect _VECTOR(34) /* External Interrupt 0 */ -#define PORTB_INT1_vect_num 35 -#define PORTB_INT1_vect _VECTOR(35) /* External Interrupt 1 */ - -/* ACB interrupt vectors */ -#define ACB_AC0_vect_num 36 -#define ACB_AC0_vect _VECTOR(36) /* AC0 Interrupt */ -#define ACB_AC1_vect_num 37 -#define ACB_AC1_vect _VECTOR(37) /* AC1 Interrupt */ -#define ACB_ACW_vect_num 38 -#define ACB_ACW_vect _VECTOR(38) /* ACW Window Mode Interrupt */ - -/* ADCB interrupt vectors */ -#define ADCB_CH0_vect_num 39 -#define ADCB_CH0_vect _VECTOR(39) /* Interrupt 0 */ -#define ADCB_CH1_vect_num 40 -#define ADCB_CH1_vect _VECTOR(40) /* Interrupt 1 */ -#define ADCB_CH2_vect_num 41 -#define ADCB_CH2_vect _VECTOR(41) /* Interrupt 2 */ -#define ADCB_CH3_vect_num 42 -#define ADCB_CH3_vect _VECTOR(42) /* Interrupt 3 */ - -/* PORTE interrupt vectors */ -#define PORTE_INT0_vect_num 43 -#define PORTE_INT0_vect _VECTOR(43) /* External Interrupt 0 */ -#define PORTE_INT1_vect_num 44 -#define PORTE_INT1_vect _VECTOR(44) /* External Interrupt 1 */ - -/* TWIE interrupt vectors */ -#define TWIE_TWIS_vect_num 45 -#define TWIE_TWIS_vect _VECTOR(45) /* TWI Slave Interrupt */ -#define TWIE_TWIM_vect_num 46 -#define TWIE_TWIM_vect _VECTOR(46) /* TWI Master Interrupt */ - -/* TCE0 interrupt vectors */ -#define TCE0_OVF_vect_num 47 -#define TCE0_OVF_vect _VECTOR(47) /* Overflow Interrupt */ -#define TCE0_ERR_vect_num 48 -#define TCE0_ERR_vect _VECTOR(48) /* Error Interrupt */ -#define TCE0_CCA_vect_num 49 -#define TCE0_CCA_vect _VECTOR(49) /* Compare or Capture A Interrupt */ -#define TCE0_CCB_vect_num 50 -#define TCE0_CCB_vect _VECTOR(50) /* Compare or Capture B Interrupt */ -#define TCE0_CCC_vect_num 51 -#define TCE0_CCC_vect _VECTOR(51) /* Compare or Capture C Interrupt */ -#define TCE0_CCD_vect_num 52 -#define TCE0_CCD_vect _VECTOR(52) /* Compare or Capture D Interrupt */ - -/* TCE1 interrupt vectors */ -#define TCE1_OVF_vect_num 53 -#define TCE1_OVF_vect _VECTOR(53) /* Overflow Interrupt */ -#define TCE1_ERR_vect_num 54 -#define TCE1_ERR_vect _VECTOR(54) /* Error Interrupt */ -#define TCE1_CCA_vect_num 55 -#define TCE1_CCA_vect _VECTOR(55) /* Compare or Capture A Interrupt */ -#define TCE1_CCB_vect_num 56 -#define TCE1_CCB_vect _VECTOR(56) /* Compare or Capture B Interrupt */ - -/* SPIE interrupt vectors */ -#define SPIE_INT_vect_num 57 -#define SPIE_INT_vect _VECTOR(57) /* SPI Interrupt */ - -/* USARTE0 interrupt vectors */ -#define USARTE0_RXC_vect_num 58 -#define USARTE0_RXC_vect _VECTOR(58) /* Reception Complete Interrupt */ -#define USARTE0_DRE_vect_num 59 -#define USARTE0_DRE_vect _VECTOR(59) /* Data Register Empty Interrupt */ -#define USARTE0_TXC_vect_num 60 -#define USARTE0_TXC_vect _VECTOR(60) /* Transmission Complete Interrupt */ - -/* USARTE1 interrupt vectors */ -#define USARTE1_RXC_vect_num 61 -#define USARTE1_RXC_vect _VECTOR(61) /* Reception Complete Interrupt */ -#define USARTE1_DRE_vect_num 62 -#define USARTE1_DRE_vect _VECTOR(62) /* Data Register Empty Interrupt */ -#define USARTE1_TXC_vect_num 63 -#define USARTE1_TXC_vect _VECTOR(63) /* Transmission Complete Interrupt */ - -/* PORTD interrupt vectors */ -#define PORTD_INT0_vect_num 64 -#define PORTD_INT0_vect _VECTOR(64) /* External Interrupt 0 */ -#define PORTD_INT1_vect_num 65 -#define PORTD_INT1_vect _VECTOR(65) /* External Interrupt 1 */ - -/* PORTA interrupt vectors */ -#define PORTA_INT0_vect_num 66 -#define PORTA_INT0_vect _VECTOR(66) /* External Interrupt 0 */ -#define PORTA_INT1_vect_num 67 -#define PORTA_INT1_vect _VECTOR(67) /* External Interrupt 1 */ - -/* ACA interrupt vectors */ -#define ACA_AC0_vect_num 68 -#define ACA_AC0_vect _VECTOR(68) /* AC0 Interrupt */ -#define ACA_AC1_vect_num 69 -#define ACA_AC1_vect _VECTOR(69) /* AC1 Interrupt */ -#define ACA_ACW_vect_num 70 -#define ACA_ACW_vect _VECTOR(70) /* ACW Window Mode Interrupt */ - -/* ADCA interrupt vectors */ -#define ADCA_CH0_vect_num 71 -#define ADCA_CH0_vect _VECTOR(71) /* Interrupt 0 */ -#define ADCA_CH1_vect_num 72 -#define ADCA_CH1_vect _VECTOR(72) /* Interrupt 1 */ -#define ADCA_CH2_vect_num 73 -#define ADCA_CH2_vect _VECTOR(73) /* Interrupt 2 */ -#define ADCA_CH3_vect_num 74 -#define ADCA_CH3_vect _VECTOR(74) /* Interrupt 3 */ - -/* TCD0 interrupt vectors */ -#define TCD0_OVF_vect_num 77 -#define TCD0_OVF_vect _VECTOR(77) /* Overflow Interrupt */ -#define TCD0_ERR_vect_num 78 -#define TCD0_ERR_vect _VECTOR(78) /* Error Interrupt */ -#define TCD0_CCA_vect_num 79 -#define TCD0_CCA_vect _VECTOR(79) /* Compare or Capture A Interrupt */ -#define TCD0_CCB_vect_num 80 -#define TCD0_CCB_vect _VECTOR(80) /* Compare or Capture B Interrupt */ -#define TCD0_CCC_vect_num 81 -#define TCD0_CCC_vect _VECTOR(81) /* Compare or Capture C Interrupt */ -#define TCD0_CCD_vect_num 82 -#define TCD0_CCD_vect _VECTOR(82) /* Compare or Capture D Interrupt */ - -/* TCD1 interrupt vectors */ -#define TCD1_OVF_vect_num 83 -#define TCD1_OVF_vect _VECTOR(83) /* Overflow Interrupt */ -#define TCD1_ERR_vect_num 84 -#define TCD1_ERR_vect _VECTOR(84) /* Error Interrupt */ -#define TCD1_CCA_vect_num 85 -#define TCD1_CCA_vect _VECTOR(85) /* Compare or Capture A Interrupt */ -#define TCD1_CCB_vect_num 86 -#define TCD1_CCB_vect _VECTOR(86) /* Compare or Capture B Interrupt */ - -/* SPID interrupt vectors */ -#define SPID_INT_vect_num 87 -#define SPID_INT_vect _VECTOR(87) /* SPI Interrupt */ - -/* USARTD0 interrupt vectors */ -#define USARTD0_RXC_vect_num 88 -#define USARTD0_RXC_vect _VECTOR(88) /* Reception Complete Interrupt */ -#define USARTD0_DRE_vect_num 89 -#define USARTD0_DRE_vect _VECTOR(89) /* Data Register Empty Interrupt */ -#define USARTD0_TXC_vect_num 90 -#define USARTD0_TXC_vect _VECTOR(90) /* Transmission Complete Interrupt */ - -/* USARTD1 interrupt vectors */ -#define USARTD1_RXC_vect_num 91 -#define USARTD1_RXC_vect _VECTOR(91) /* Reception Complete Interrupt */ -#define USARTD1_DRE_vect_num 92 -#define USARTD1_DRE_vect _VECTOR(92) /* Data Register Empty Interrupt */ -#define USARTD1_TXC_vect_num 93 -#define USARTD1_TXC_vect _VECTOR(93) /* Transmission Complete Interrupt */ - -/* PORTF interrupt vectors */ -#define PORTF_INT0_vect_num 104 -#define PORTF_INT0_vect _VECTOR(104) /* External Interrupt 0 */ -#define PORTF_INT1_vect_num 105 -#define PORTF_INT1_vect _VECTOR(105) /* External Interrupt 1 */ - -/* TCF0 interrupt vectors */ -#define TCF0_OVF_vect_num 108 -#define TCF0_OVF_vect _VECTOR(108) /* Overflow Interrupt */ -#define TCF0_ERR_vect_num 109 -#define TCF0_ERR_vect _VECTOR(109) /* Error Interrupt */ -#define TCF0_CCA_vect_num 110 -#define TCF0_CCA_vect _VECTOR(110) /* Compare or Capture A Interrupt */ -#define TCF0_CCB_vect_num 111 -#define TCF0_CCB_vect _VECTOR(111) /* Compare or Capture B Interrupt */ -#define TCF0_CCC_vect_num 112 -#define TCF0_CCC_vect _VECTOR(112) /* Compare or Capture C Interrupt */ -#define TCF0_CCD_vect_num 113 -#define TCF0_CCD_vect _VECTOR(113) /* Compare or Capture D Interrupt */ - -/* USARTF0 interrupt vectors */ -#define USARTF0_RXC_vect_num 119 -#define USARTF0_RXC_vect _VECTOR(119) /* Reception Complete Interrupt */ -#define USARTF0_DRE_vect_num 120 -#define USARTF0_DRE_vect _VECTOR(120) /* Data Register Empty Interrupt */ -#define USARTF0_TXC_vect_num 121 -#define USARTF0_TXC_vect _VECTOR(121) /* Transmission Complete Interrupt */ - - -#define _VECTOR_SIZE 4 /* Size of individual vector. */ -#define _VECTORS_SIZE (122 * _VECTOR_SIZE) - - -/* ========== Constants ========== */ - -#define PROGMEM_START (0x0000) -#define PROGMEM_SIZE (139264) -#define PROGMEM_PAGE_SIZE (512) -#define PROGMEM_END (PROGMEM_START + PROGMEM_SIZE - 1) - -#define APP_SECTION_START (0x0000) -#define APP_SECTION_SIZE (131072) -#define APP_SECTION_PAGE_SIZE (512) -#define APP_SECTION_END (APP_SECTION_START + APP_SECTION_SIZE - 1) - -#define APPTABLE_SECTION_START (0x1E000) -#define APPTABLE_SECTION_SIZE (8192) -#define APPTABLE_SECTION_PAGE_SIZE (512) -#define APPTABLE_SECTION_END (APPTABLE_SECTION_START + APPTABLE_SECTION_SIZE - 1) - -#define BOOT_SECTION_START (0x20000) -#define BOOT_SECTION_SIZE (8192) -#define BOOT_SECTION_PAGE_SIZE (512) -#define BOOT_SECTION_END (BOOT_SECTION_START + BOOT_SECTION_SIZE - 1) - -#define DATAMEM_START (0x0000) -#define DATAMEM_SIZE (16384) -#define DATAMEM_PAGE_SIZE (0) -#define DATAMEM_END (DATAMEM_START + DATAMEM_SIZE - 1) - -#define IO_START (0x0000) -#define IO_SIZE (4096) -#define IO_PAGE_SIZE (0) -#define IO_END (IO_START + IO_SIZE - 1) - -#define MAPPED_EEPROM_START (0x1000) -#define MAPPED_EEPROM_SIZE (2048) -#define MAPPED_EEPROM_PAGE_SIZE (0) -#define MAPPED_EEPROM_END (MAPPED_EEPROM_START + MAPPED_EEPROM_SIZE - 1) - -#define INTERNAL_SRAM_START (0x2000) -#define INTERNAL_SRAM_SIZE (8192) -#define INTERNAL_SRAM_PAGE_SIZE (0) -#define INTERNAL_SRAM_END (INTERNAL_SRAM_START + INTERNAL_SRAM_SIZE - 1) - -#define EEPROM_START (0x0000) -#define EEPROM_SIZE (2048) -#define EEPROM_PAGE_SIZE (32) -#define EEPROM_END (EEPROM_START + EEPROM_SIZE - 1) - -#define FUSE_START (0x0000) -#define FUSE_SIZE (6) -#define FUSE_PAGE_SIZE (0) -#define FUSE_END (FUSE_START + FUSE_SIZE - 1) - -#define LOCKBIT_START (0x0000) -#define LOCKBIT_SIZE (1) -#define LOCKBIT_PAGE_SIZE (0) -#define LOCKBIT_END (LOCKBIT_START + LOCKBIT_SIZE - 1) - -#define SIGNATURES_START (0x0000) -#define SIGNATURES_SIZE (3) -#define SIGNATURES_PAGE_SIZE (0) -#define SIGNATURES_END (SIGNATURES_START + SIGNATURES_SIZE - 1) - -#define USER_SIGNATURES_START (0x0000) -#define USER_SIGNATURES_SIZE (512) -#define USER_SIGNATURES_PAGE_SIZE (0) -#define USER_SIGNATURES_END (USER_SIGNATURES_START + USER_SIGNATURES_SIZE - 1) - -#define PROD_SIGNATURES_START (0x0000) -#define PROD_SIGNATURES_SIZE (52) -#define PROD_SIGNATURES_PAGE_SIZE (0) -#define PROD_SIGNATURES_END (PROD_SIGNATURES_START + PROD_SIGNATURES_SIZE - 1) - -#define FLASHEND PROGMEM_END -#define SPM_PAGESIZE PROGMEM_PAGE_SIZE -#define RAMSTART INTERNAL_SRAM_START -#define RAMSIZE INTERNAL_SRAM_SIZE -#define RAMEND INTERNAL_SRAM_END -#define XRAMSTART EXTERNAL_SRAM_START -#define XRAMSIZE EXTERNAL_SRAM_SIZE -#define XRAMEND INTERNAL_SRAM_END -#define E2END EEPROM_END -#define E2PAGESIZE EEPROM_PAGE_SIZE - - -/* ========== Fuses ========== */ -#define FUSE_MEMORY_SIZE 6 - -/* Fuse Byte 0 */ -#define FUSE_JTAGUSERID0 (unsigned char)~_BV(0) /* JTAG User ID Bit 0 */ -#define FUSE_JTAGUSERID1 (unsigned char)~_BV(1) /* JTAG User ID Bit 1 */ -#define FUSE_JTAGUSERID2 (unsigned char)~_BV(2) /* JTAG User ID Bit 2 */ -#define FUSE_JTAGUSERID3 (unsigned char)~_BV(3) /* JTAG User ID Bit 3 */ -#define FUSE_JTAGUSERID4 (unsigned char)~_BV(4) /* JTAG User ID Bit 4 */ -#define FUSE_JTAGUSERID5 (unsigned char)~_BV(5) /* JTAG User ID Bit 5 */ -#define FUSE_JTAGUSERID6 (unsigned char)~_BV(6) /* JTAG User ID Bit 6 */ -#define FUSE_JTAGUSERID7 (unsigned char)~_BV(7) /* JTAG User ID Bit 7 */ -#define FUSE0_DEFAULT (0xFF) - -/* Fuse Byte 1 */ -#define FUSE_WDP0 (unsigned char)~_BV(0) /* Watchdog Timeout Period Bit 0 */ -#define FUSE_WDP1 (unsigned char)~_BV(1) /* Watchdog Timeout Period Bit 1 */ -#define FUSE_WDP2 (unsigned char)~_BV(2) /* Watchdog Timeout Period Bit 2 */ -#define FUSE_WDP3 (unsigned char)~_BV(3) /* Watchdog Timeout Period Bit 3 */ -#define FUSE_WDWP0 (unsigned char)~_BV(4) /* Watchdog Window Timeout Period Bit 0 */ -#define FUSE_WDWP1 (unsigned char)~_BV(5) /* Watchdog Window Timeout Period Bit 1 */ -#define FUSE_WDWP2 (unsigned char)~_BV(6) /* Watchdog Window Timeout Period Bit 2 */ -#define FUSE_WDWP3 (unsigned char)~_BV(7) /* Watchdog Window Timeout Period Bit 3 */ -#define FUSE1_DEFAULT (0xFF) - -/* Fuse Byte 2 */ -#define FUSE_BODPD0 (unsigned char)~_BV(0) /* BOD Operation in Power-Down Mode Bit 0 */ -#define FUSE_BODPD1 (unsigned char)~_BV(1) /* BOD Operation in Power-Down Mode Bit 1 */ -#define FUSE_BOOTRST (unsigned char)~_BV(6) /* Boot Loader Section Reset Vector */ -#define FUSE_DVSDON (unsigned char)~_BV(7) /* Spike Detector Enable */ -#define FUSE2_DEFAULT (0xFF) - -/* Fuse Byte 3 Reserved */ - -/* Fuse Byte 4 */ -#define FUSE_JTAGEN (unsigned char)~_BV(0) /* JTAG Interface Enable */ -#define FUSE_WDLOCK (unsigned char)~_BV(1) /* Watchdog Timer Lock */ -#define FUSE_SUT0 (unsigned char)~_BV(2) /* Start-up Time Bit 0 */ -#define FUSE_SUT1 (unsigned char)~_BV(3) /* Start-up Time Bit 1 */ -#define FUSE4_DEFAULT (0xFF) - -/* Fuse Byte 5 */ -#define FUSE_BODLVL0 (unsigned char)~_BV(0) /* Brown Out Detection Voltage Level Bit 0 */ -#define FUSE_BODLVL1 (unsigned char)~_BV(1) /* Brown Out Detection Voltage Level Bit 1 */ -#define FUSE_BODLVL2 (unsigned char)~_BV(2) /* Brown Out Detection Voltage Level Bit 2 */ -#define FUSE_EESAVE (unsigned char)~_BV(3) /* Preserve EEPROM Through Chip Erase */ -#define FUSE_BODACT0 (unsigned char)~_BV(4) /* BOD Operation in Active Mode Bit 0 */ -#define FUSE_BODACT1 (unsigned char)~_BV(5) /* BOD Operation in Active Mode Bit 1 */ -#define FUSE5_DEFAULT (0xFF) - - -/* ========== Lock Bits ========== */ -#define __LOCK_BITS_EXIST -#define __BOOT_LOCK_APPLICATION_TABLE_BITS_EXIST -#define __BOOT_LOCK_APPLICATION_BITS_EXIST -#define __BOOT_LOCK_BOOT_BITS_EXIST - - -/* ========== Signature ========== */ -#define SIGNATURE_0 0x1E -#define SIGNATURE_1 0x97 -#define SIGNATURE_2 0x42 - -/* ========== Power Reduction Condition Definitions ========== */ - -/* PR.PRGEN */ -#define __AVR_HAVE_PRGEN (PR_AES_bm|PR_EBI_bm|PR_RTC_bm|PR_EVSYS_bm|PR_DMA_bm) -#define __AVR_HAVE_PRGEN_AES -#define __AVR_HAVE_PRGEN_EBI -#define __AVR_HAVE_PRGEN_RTC -#define __AVR_HAVE_PRGEN_EVSYS -#define __AVR_HAVE_PRGEN_DMA - -/* PR.PRPA */ -#define __AVR_HAVE_PRPA (PR_DAC_bm|PR_ADC_bm|PR_AC_bm) -#define __AVR_HAVE_PRPA_DAC -#define __AVR_HAVE_PRPA_ADC -#define __AVR_HAVE_PRPA_AC - -/* PR.PRPB */ -#define __AVR_HAVE_PRPB (PR_DAC_bm|PR_ADC_bm|PR_AC_bm) -#define __AVR_HAVE_PRPB_DAC -#define __AVR_HAVE_PRPB_ADC -#define __AVR_HAVE_PRPB_AC - -/* PR.PRPC */ -#define __AVR_HAVE_PRPC (PR_TWI_bm|PR_USART1_bm|PR_USART0_bm|PR_SPI_bm|PR_HIRES_bm|PR_TC1_bm|PR_TC0_bm) -#define __AVR_HAVE_PRPC_TWI -#define __AVR_HAVE_PRPC_USART1 -#define __AVR_HAVE_PRPC_USART0 -#define __AVR_HAVE_PRPC_SPI -#define __AVR_HAVE_PRPC_HIRES -#define __AVR_HAVE_PRPC_TC1 -#define __AVR_HAVE_PRPC_TC0 - -/* PR.PRPD */ -#define __AVR_HAVE_PRPD (PR_TWI_bm|PR_USART1_bm|PR_USART0_bm|PR_SPI_bm|PR_HIRES_bm|PR_TC1_bm|PR_TC0_bm) -#define __AVR_HAVE_PRPD_TWI -#define __AVR_HAVE_PRPD_USART1 -#define __AVR_HAVE_PRPD_USART0 -#define __AVR_HAVE_PRPD_SPI -#define __AVR_HAVE_PRPD_HIRES -#define __AVR_HAVE_PRPD_TC1 -#define __AVR_HAVE_PRPD_TC0 - -/* PR.PRPE */ -#define __AVR_HAVE_PRPE (PR_TWI_bm|PR_USART1_bm|PR_USART0_bm|PR_SPI_bm|PR_HIRES_bm|PR_TC1_bm|PR_TC0_bm) -#define __AVR_HAVE_PRPE_TWI -#define __AVR_HAVE_PRPE_USART1 -#define __AVR_HAVE_PRPE_USART0 -#define __AVR_HAVE_PRPE_SPI -#define __AVR_HAVE_PRPE_HIRES -#define __AVR_HAVE_PRPE_TC1 -#define __AVR_HAVE_PRPE_TC0 - -/* PR.PRPF */ -#define __AVR_HAVE_PRPF (PR_TWI_bm|PR_USART1_bm|PR_USART0_bm|PR_SPI_bm|PR_HIRES_bm|PR_TC1_bm|PR_TC0_bm) -#define __AVR_HAVE_PRPF_TWI -#define __AVR_HAVE_PRPF_USART1 -#define __AVR_HAVE_PRPF_USART0 -#define __AVR_HAVE_PRPF_SPI -#define __AVR_HAVE_PRPF_HIRES -#define __AVR_HAVE_PRPF_TC1 -#define __AVR_HAVE_PRPF_TC0 - - -#endif /* _AVR_ATxmega128A3_H_ */ - diff --git a/arduino/hardware/tools/avr/avr/include/avr/iox128a3u.h b/arduino/hardware/tools/avr/avr/include/avr/iox128a3u.h deleted file mode 100644 index 489caa0..0000000 --- a/arduino/hardware/tools/avr/avr/include/avr/iox128a3u.h +++ /dev/null @@ -1,7697 +0,0 @@ -/***************************************************************************** - * - * Copyright (C) 2015 Atmel Corporation - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * - * * Neither the name of the copyright holders nor the names of - * contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - ****************************************************************************/ - - -#ifndef _AVR_IO_H_ -# error "Include instead of this file." -#endif - -#ifndef _AVR_IOXXX_H_ -# define _AVR_IOXXX_H_ "iox128a3u.h" -#else -# error "Attempt to include more than one file." -#endif - -#ifndef _AVR_ATXMEGA128A3U_H_INCLUDED -#define _AVR_ATXMEGA128A3U_H_INCLUDED - -/* Ungrouped common registers */ -#define GPIOR0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ -#define GPIOR1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ -#define GPIOR2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ -#define GPIOR3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ -#define GPIOR4 _SFR_MEM8(0x0004) /* General Purpose IO Register 4 */ -#define GPIOR5 _SFR_MEM8(0x0005) /* General Purpose IO Register 5 */ -#define GPIOR6 _SFR_MEM8(0x0006) /* General Purpose IO Register 6 */ -#define GPIOR7 _SFR_MEM8(0x0007) /* General Purpose IO Register 7 */ -#define GPIOR8 _SFR_MEM8(0x0008) /* General Purpose IO Register 8 */ -#define GPIOR9 _SFR_MEM8(0x0009) /* General Purpose IO Register 9 */ -#define GPIORA _SFR_MEM8(0x000A) /* General Purpose IO Register 10 */ -#define GPIORB _SFR_MEM8(0x000B) /* General Purpose IO Register 11 */ -#define GPIORC _SFR_MEM8(0x000C) /* General Purpose IO Register 12 */ -#define GPIORD _SFR_MEM8(0x000D) /* General Purpose IO Register 13 */ -#define GPIORE _SFR_MEM8(0x000E) /* General Purpose IO Register 14 */ -#define GPIORF _SFR_MEM8(0x000F) /* General Purpose IO Register 15 */ - -/* Deprecated */ -#define GPIO0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ -#define GPIO1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ -#define GPIO2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ -#define GPIO3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ -#define GPIO4 _SFR_MEM8(0x0004) /* General Purpose IO Register 4 */ -#define GPIO5 _SFR_MEM8(0x0005) /* General Purpose IO Register 5 */ -#define GPIO6 _SFR_MEM8(0x0006) /* General Purpose IO Register 6 */ -#define GPIO7 _SFR_MEM8(0x0007) /* General Purpose IO Register 7 */ -#define GPIO8 _SFR_MEM8(0x0008) /* General Purpose IO Register 8 */ -#define GPIO9 _SFR_MEM8(0x0009) /* General Purpose IO Register 9 */ -#define GPIOA _SFR_MEM8(0x000A) /* General Purpose IO Register 10 */ -#define GPIOB _SFR_MEM8(0x000B) /* General Purpose IO Register 11 */ -#define GPIOC _SFR_MEM8(0x000C) /* General Purpose IO Register 12 */ -#define GPIOD _SFR_MEM8(0x000D) /* General Purpose IO Register 13 */ -#define GPIOE _SFR_MEM8(0x000E) /* General Purpose IO Register 14 */ -#define GPIOF _SFR_MEM8(0x000F) /* General Purpose IO Register 15 */ - -#define CCP _SFR_MEM8(0x0034) /* Configuration Change Protection */ -#define RAMPD _SFR_MEM8(0x0038) /* Ramp D */ -#define RAMPX _SFR_MEM8(0x0039) /* Ramp X */ -#define RAMPY _SFR_MEM8(0x003A) /* Ramp Y */ -#define RAMPZ _SFR_MEM8(0x003B) /* Ramp Z */ -#define EIND _SFR_MEM8(0x003C) /* Extended Indirect Jump */ -#define SPL _SFR_MEM8(0x003D) /* Stack Pointer Low */ -#define SPH _SFR_MEM8(0x003E) /* Stack Pointer High */ -#define SREG _SFR_MEM8(0x003F) /* Status Register */ - -/* C Language Only */ -#if !defined (__ASSEMBLER__) - -#include - -typedef volatile uint8_t register8_t; -typedef volatile uint16_t register16_t; -typedef volatile uint32_t register32_t; - - -#ifdef _WORDREGISTER -#undef _WORDREGISTER -#endif -#define _WORDREGISTER(regname) \ - __extension__ union \ - { \ - register16_t regname; \ - struct \ - { \ - register8_t regname ## L; \ - register8_t regname ## H; \ - }; \ - } - -#ifdef _DWORDREGISTER -#undef _DWORDREGISTER -#endif -#define _DWORDREGISTER(regname) \ - __extension__ union \ - { \ - register32_t regname; \ - struct \ - { \ - register8_t regname ## 0; \ - register8_t regname ## 1; \ - register8_t regname ## 2; \ - register8_t regname ## 3; \ - }; \ - } - - -/* -========================================================================== -IO Module Structures -========================================================================== -*/ - - -/* --------------------------------------------------------------------------- -VPORT - Virtual Ports --------------------------------------------------------------------------- -*/ - -/* Virtual Port */ -typedef struct VPORT_struct -{ - register8_t DIR; /* I/O Port Data Direction */ - register8_t OUT; /* I/O Port Output */ - register8_t IN; /* I/O Port Input */ - register8_t INTFLAGS; /* Interrupt Flag Register */ -} VPORT_t; - - -/* --------------------------------------------------------------------------- -XOCD - On-Chip Debug System --------------------------------------------------------------------------- -*/ - -/* On-Chip Debug System */ -typedef struct OCD_struct -{ - register8_t OCDR0; /* OCD Register 0 */ - register8_t OCDR1; /* OCD Register 1 */ -} OCD_t; - - -/* --------------------------------------------------------------------------- -CPU - CPU --------------------------------------------------------------------------- -*/ - -/* CCP signatures */ -typedef enum CCP_enum -{ - CCP_SPM_gc = (0x9D<<0), /* SPM Instruction Protection */ - CCP_IOREG_gc = (0xD8<<0), /* IO Register Protection */ -} CCP_t; - - -/* --------------------------------------------------------------------------- -CLK - Clock System --------------------------------------------------------------------------- -*/ - -/* Clock System */ -typedef struct CLK_struct -{ - register8_t CTRL; /* Control Register */ - register8_t PSCTRL; /* Prescaler Control Register */ - register8_t LOCK; /* Lock register */ - register8_t RTCCTRL; /* RTC Control Register */ - register8_t USBCTRL; /* USB Control Register */ -} CLK_t; - - -/* Power Reduction */ -typedef struct PR_struct -{ - register8_t PRGEN; /* General Power Reduction */ - register8_t PRPA; /* Power Reduction Port A */ - register8_t PRPB; /* Power Reduction Port B */ - register8_t PRPC; /* Power Reduction Port C */ - register8_t PRPD; /* Power Reduction Port D */ - register8_t PRPE; /* Power Reduction Port E */ - register8_t PRPF; /* Power Reduction Port F */ -} PR_t; - -/* System Clock Selection */ -typedef enum CLK_SCLKSEL_enum -{ - CLK_SCLKSEL_RC2M_gc = (0x00<<0), /* Internal 2 MHz RC Oscillator */ - CLK_SCLKSEL_RC32M_gc = (0x01<<0), /* Internal 32 MHz RC Oscillator */ - CLK_SCLKSEL_RC32K_gc = (0x02<<0), /* Internal 32.768 kHz RC Oscillator */ - CLK_SCLKSEL_XOSC_gc = (0x03<<0), /* External Crystal Oscillator or Clock */ - CLK_SCLKSEL_PLL_gc = (0x04<<0), /* Phase Locked Loop */ -} CLK_SCLKSEL_t; - -/* Prescaler A Division Factor */ -typedef enum CLK_PSADIV_enum -{ - CLK_PSADIV_1_gc = (0x00<<2), /* Divide by 1 */ - CLK_PSADIV_2_gc = (0x01<<2), /* Divide by 2 */ - CLK_PSADIV_4_gc = (0x03<<2), /* Divide by 4 */ - CLK_PSADIV_8_gc = (0x05<<2), /* Divide by 8 */ - CLK_PSADIV_16_gc = (0x07<<2), /* Divide by 16 */ - CLK_PSADIV_32_gc = (0x09<<2), /* Divide by 32 */ - CLK_PSADIV_64_gc = (0x0B<<2), /* Divide by 64 */ - CLK_PSADIV_128_gc = (0x0D<<2), /* Divide by 128 */ - CLK_PSADIV_256_gc = (0x0F<<2), /* Divide by 256 */ - CLK_PSADIV_512_gc = (0x11<<2), /* Divide by 512 */ -} CLK_PSADIV_t; - -/* Prescaler B and C Division Factor */ -typedef enum CLK_PSBCDIV_enum -{ - CLK_PSBCDIV_1_1_gc = (0x00<<0), /* Divide B by 1 and C by 1 */ - CLK_PSBCDIV_1_2_gc = (0x01<<0), /* Divide B by 1 and C by 2 */ - CLK_PSBCDIV_4_1_gc = (0x02<<0), /* Divide B by 4 and C by 1 */ - CLK_PSBCDIV_2_2_gc = (0x03<<0), /* Divide B by 2 and C by 2 */ -} CLK_PSBCDIV_t; - -/* RTC Clock Source */ -typedef enum CLK_RTCSRC_enum -{ - CLK_RTCSRC_ULP_gc = (0x00<<1), /* 1.024 kHz from internal 32kHz ULP */ - CLK_RTCSRC_TOSC_gc = (0x01<<1), /* 1.024 kHz from 32.768 kHz crystal oscillator on TOSC */ - CLK_RTCSRC_RCOSC_gc = (0x02<<1), /* 1.024 kHz from internal 32.768 kHz RC oscillator */ - CLK_RTCSRC_TOSC32_gc = (0x05<<1), /* 32.768 kHz from 32.768 kHz crystal oscillator on TOSC */ - CLK_RTCSRC_RCOSC32_gc = (0x06<<1), /* 32.768 kHz from internal 32.768 kHz RC oscillator */ - CLK_RTCSRC_EXTCLK_gc = (0x07<<1), /* External Clock from TOSC1 */ -} CLK_RTCSRC_t; - -/* USB Prescaler Division Factor */ -typedef enum CLK_USBPSDIV_enum -{ - CLK_USBPSDIV_1_gc = (0x00<<3), /* Divide by 1 */ - CLK_USBPSDIV_2_gc = (0x01<<3), /* Divide by 2 */ - CLK_USBPSDIV_4_gc = (0x02<<3), /* Divide by 4 */ - CLK_USBPSDIV_8_gc = (0x03<<3), /* Divide by 8 */ - CLK_USBPSDIV_16_gc = (0x04<<3), /* Divide by 16 */ - CLK_USBPSDIV_32_gc = (0x05<<3), /* Divide by 32 */ -} CLK_USBPSDIV_t; - -/* USB Clock Source */ -typedef enum CLK_USBSRC_enum -{ - CLK_USBSRC_PLL_gc = (0x00<<1), /* PLL */ - CLK_USBSRC_RC32M_gc = (0x01<<1), /* Internal 32 MHz RC Oscillator */ -} CLK_USBSRC_t; - - -/* --------------------------------------------------------------------------- -SLEEP - Sleep Controller --------------------------------------------------------------------------- -*/ - -/* Sleep Controller */ -typedef struct SLEEP_struct -{ - register8_t CTRL; /* Control Register */ -} SLEEP_t; - -/* Sleep Mode */ -typedef enum SLEEP_SMODE_enum -{ - SLEEP_SMODE_IDLE_gc = (0x00<<1), /* Idle mode */ - SLEEP_SMODE_PDOWN_gc = (0x02<<1), /* Power-down Mode */ - SLEEP_SMODE_PSAVE_gc = (0x03<<1), /* Power-save Mode */ - SLEEP_SMODE_STDBY_gc = (0x06<<1), /* Standby Mode */ - SLEEP_SMODE_ESTDBY_gc = (0x07<<1), /* Extended Standby Mode */ -} SLEEP_SMODE_t; - - - -#define SLEEP_MODE_IDLE (0x00<<1) -#define SLEEP_MODE_PWR_DOWN (0x02<<1) -#define SLEEP_MODE_PWR_SAVE (0x03<<1) -#define SLEEP_MODE_STANDBY (0x06<<1) -#define SLEEP_MODE_EXT_STANDBY (0x07<<1) -/* --------------------------------------------------------------------------- -OSC - Oscillator --------------------------------------------------------------------------- -*/ - -/* Oscillator */ -typedef struct OSC_struct -{ - register8_t CTRL; /* Control Register */ - register8_t STATUS; /* Status Register */ - register8_t XOSCCTRL; /* External Oscillator Control Register */ - register8_t XOSCFAIL; /* Oscillator Failure Detection Register */ - register8_t RC32KCAL; /* 32.768 kHz Internal Oscillator Calibration Register */ - register8_t PLLCTRL; /* PLL Control Register */ - register8_t DFLLCTRL; /* DFLL Control Register */ -} OSC_t; - -/* Oscillator Frequency Range */ -typedef enum OSC_FRQRANGE_enum -{ - OSC_FRQRANGE_04TO2_gc = (0x00<<6), /* 0.4 - 2 MHz */ - OSC_FRQRANGE_2TO9_gc = (0x01<<6), /* 2 - 9 MHz */ - OSC_FRQRANGE_9TO12_gc = (0x02<<6), /* 9 - 12 MHz */ - OSC_FRQRANGE_12TO16_gc = (0x03<<6), /* 12 - 16 MHz */ -} OSC_FRQRANGE_t; - -/* External Oscillator Selection and Startup Time */ -typedef enum OSC_XOSCSEL_enum -{ - OSC_XOSCSEL_EXTCLK_gc = (0x00<<0), /* External Clock - 6 CLK */ - OSC_XOSCSEL_32KHz_gc = (0x02<<0), /* 32.768 kHz TOSC - 32K CLK */ - OSC_XOSCSEL_XTAL_256CLK_gc = (0x03<<0), /* 0.4-16 MHz XTAL - 256 CLK */ - OSC_XOSCSEL_XTAL_1KCLK_gc = (0x07<<0), /* 0.4-16 MHz XTAL - 1K CLK */ - OSC_XOSCSEL_XTAL_16KCLK_gc = (0x0B<<0), /* 0.4-16 MHz XTAL - 16K CLK */ -} OSC_XOSCSEL_t; - -/* PLL Clock Source */ -typedef enum OSC_PLLSRC_enum -{ - OSC_PLLSRC_RC2M_gc = (0x00<<6), /* Internal 2 MHz RC Oscillator */ - OSC_PLLSRC_RC32M_gc = (0x02<<6), /* Internal 32 MHz RC Oscillator */ - OSC_PLLSRC_XOSC_gc = (0x03<<6), /* External Oscillator */ -} OSC_PLLSRC_t; - -/* 2 MHz DFLL Calibration Reference */ -typedef enum OSC_RC2MCREF_enum -{ - OSC_RC2MCREF_RC32K_gc = (0x00<<0), /* Internal 32.768 kHz RC Oscillator */ - OSC_RC2MCREF_XOSC32K_gc = (0x01<<0), /* External 32.768 kHz Crystal Oscillator */ -} OSC_RC2MCREF_t; - -/* 32 MHz DFLL Calibration Reference */ -typedef enum OSC_RC32MCREF_enum -{ - OSC_RC32MCREF_RC32K_gc = (0x00<<1), /* Internal 32.768 kHz RC Oscillator */ - OSC_RC32MCREF_XOSC32K_gc = (0x01<<1), /* External 32.768 kHz Crystal Oscillator */ - OSC_RC32MCREF_USBSOF_gc = (0x02<<1), /* USB Start of Frame */ -} OSC_RC32MCREF_t; - - -/* --------------------------------------------------------------------------- -DFLL - DFLL --------------------------------------------------------------------------- -*/ - -/* DFLL */ -typedef struct DFLL_struct -{ - register8_t CTRL; /* Control Register */ - register8_t reserved_0x01; - register8_t CALA; /* Calibration Register A */ - register8_t CALB; /* Calibration Register B */ - register8_t COMP0; /* Oscillator Compare Register 0 */ - register8_t COMP1; /* Oscillator Compare Register 1 */ - register8_t COMP2; /* Oscillator Compare Register 2 */ - register8_t reserved_0x07; -} DFLL_t; - - -/* --------------------------------------------------------------------------- -RST - Reset --------------------------------------------------------------------------- -*/ - -/* Reset */ -typedef struct RST_struct -{ - register8_t STATUS; /* Status Register */ - register8_t CTRL; /* Control Register */ -} RST_t; - - -/* --------------------------------------------------------------------------- -WDT - Watch-Dog Timer --------------------------------------------------------------------------- -*/ - -/* Watch-Dog Timer */ -typedef struct WDT_struct -{ - register8_t CTRL; /* Control */ - register8_t WINCTRL; /* Windowed Mode Control */ - register8_t STATUS; /* Status */ -} WDT_t; - -/* Period setting */ -typedef enum WDT_PER_enum -{ - WDT_PER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ - WDT_PER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ - WDT_PER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ - WDT_PER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ - WDT_PER_128CLK_gc = (0x04<<2), /* 128 cycles (0.128s @ 3.3V) */ - WDT_PER_256CLK_gc = (0x05<<2), /* 256 cycles (0.256s @ 3.3V) */ - WDT_PER_512CLK_gc = (0x06<<2), /* 512 cycles (0.512s @ 3.3V) */ - WDT_PER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ - WDT_PER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ - WDT_PER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ - WDT_PER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ -} WDT_PER_t; - -/* Closed window period */ -typedef enum WDT_WPER_enum -{ - WDT_WPER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ - WDT_WPER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ - WDT_WPER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ - WDT_WPER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ - WDT_WPER_128CLK_gc = (0x04<<2), /* 128 cycles (0.128s @ 3.3V) */ - WDT_WPER_256CLK_gc = (0x05<<2), /* 256 cycles (0.256s @ 3.3V) */ - WDT_WPER_512CLK_gc = (0x06<<2), /* 512 cycles (0.512s @ 3.3V) */ - WDT_WPER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ - WDT_WPER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ - WDT_WPER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ - WDT_WPER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ -} WDT_WPER_t; - - -/* --------------------------------------------------------------------------- -MCU - MCU Control --------------------------------------------------------------------------- -*/ - -/* MCU Control */ -typedef struct MCU_struct -{ - register8_t DEVID0; /* Device ID byte 0 */ - register8_t DEVID1; /* Device ID byte 1 */ - register8_t DEVID2; /* Device ID byte 2 */ - register8_t REVID; /* Revision ID */ - register8_t JTAGUID; /* JTAG User ID */ - register8_t reserved_0x05; - register8_t MCUCR; /* MCU Control */ - register8_t ANAINIT; /* Analog Startup Delay */ - register8_t EVSYSLOCK; /* Event System Lock */ - register8_t AWEXLOCK; /* AWEX Lock */ - register8_t reserved_0x0A; - register8_t reserved_0x0B; -} MCU_t; - - -/* --------------------------------------------------------------------------- -PMIC - Programmable Multi-level Interrupt Controller --------------------------------------------------------------------------- -*/ - -/* Programmable Multi-level Interrupt Controller */ -typedef struct PMIC_struct -{ - register8_t STATUS; /* Status Register */ - register8_t INTPRI; /* Interrupt Priority */ - register8_t CTRL; /* Control Register */ - register8_t reserved_0x03; - register8_t reserved_0x04; - register8_t reserved_0x05; - register8_t reserved_0x06; - register8_t reserved_0x07; - register8_t reserved_0x08; - register8_t reserved_0x09; - register8_t reserved_0x0A; - register8_t reserved_0x0B; - register8_t reserved_0x0C; - register8_t reserved_0x0D; - register8_t reserved_0x0E; - register8_t reserved_0x0F; -} PMIC_t; - - -/* --------------------------------------------------------------------------- -PORTCFG - Port Configuration --------------------------------------------------------------------------- -*/ - -/* I/O port Configuration */ -typedef struct PORTCFG_struct -{ - register8_t MPCMASK; /* Multi-pin Configuration Mask */ - register8_t reserved_0x01; - register8_t VPCTRLA; /* Virtual Port Control Register A */ - register8_t VPCTRLB; /* Virtual Port Control Register B */ - register8_t CLKEVOUT; /* Clock and Event Out Register */ - register8_t EBIOUT; /* EBI Output register */ - register8_t EVOUTSEL; /* Event Output Select */ -} PORTCFG_t; - -/* Virtual Port Mapping */ -typedef enum PORTCFG_VP02MAP_enum -{ - PORTCFG_VP02MAP_PORTA_gc = (0x00<<0), /* Mapped To PORTA */ - PORTCFG_VP02MAP_PORTB_gc = (0x01<<0), /* Mapped To PORTB */ - PORTCFG_VP02MAP_PORTC_gc = (0x02<<0), /* Mapped To PORTC */ - PORTCFG_VP02MAP_PORTD_gc = (0x03<<0), /* Mapped To PORTD */ - PORTCFG_VP02MAP_PORTE_gc = (0x04<<0), /* Mapped To PORTE */ - PORTCFG_VP02MAP_PORTF_gc = (0x05<<0), /* Mapped To PORTF */ - PORTCFG_VP02MAP_PORTG_gc = (0x06<<0), /* Mapped To PORTG */ - PORTCFG_VP02MAP_PORTH_gc = (0x07<<0), /* Mapped To PORTH */ - PORTCFG_VP02MAP_PORTJ_gc = (0x08<<0), /* Mapped To PORTJ */ - PORTCFG_VP02MAP_PORTK_gc = (0x09<<0), /* Mapped To PORTK */ - PORTCFG_VP02MAP_PORTL_gc = (0x0A<<0), /* Mapped To PORTL */ - PORTCFG_VP02MAP_PORTM_gc = (0x0B<<0), /* Mapped To PORTM */ - PORTCFG_VP02MAP_PORTN_gc = (0x0C<<0), /* Mapped To PORTN */ - PORTCFG_VP02MAP_PORTP_gc = (0x0D<<0), /* Mapped To PORTP */ - PORTCFG_VP02MAP_PORTQ_gc = (0x0E<<0), /* Mapped To PORTQ */ - PORTCFG_VP02MAP_PORTR_gc = (0x0F<<0), /* Mapped To PORTR */ -} PORTCFG_VP02MAP_t; - -/* Virtual Port Mapping */ -typedef enum PORTCFG_VP13MAP_enum -{ - PORTCFG_VP13MAP_PORTA_gc = (0x00<<4), /* Mapped To PORTA */ - PORTCFG_VP13MAP_PORTB_gc = (0x01<<4), /* Mapped To PORTB */ - PORTCFG_VP13MAP_PORTC_gc = (0x02<<4), /* Mapped To PORTC */ - PORTCFG_VP13MAP_PORTD_gc = (0x03<<4), /* Mapped To PORTD */ - PORTCFG_VP13MAP_PORTE_gc = (0x04<<4), /* Mapped To PORTE */ - PORTCFG_VP13MAP_PORTF_gc = (0x05<<4), /* Mapped To PORTF */ - PORTCFG_VP13MAP_PORTG_gc = (0x06<<4), /* Mapped To PORTG */ - PORTCFG_VP13MAP_PORTH_gc = (0x07<<4), /* Mapped To PORTH */ - PORTCFG_VP13MAP_PORTJ_gc = (0x08<<4), /* Mapped To PORTJ */ - PORTCFG_VP13MAP_PORTK_gc = (0x09<<4), /* Mapped To PORTK */ - PORTCFG_VP13MAP_PORTL_gc = (0x0A<<4), /* Mapped To PORTL */ - PORTCFG_VP13MAP_PORTM_gc = (0x0B<<4), /* Mapped To PORTM */ - PORTCFG_VP13MAP_PORTN_gc = (0x0C<<4), /* Mapped To PORTN */ - PORTCFG_VP13MAP_PORTP_gc = (0x0D<<4), /* Mapped To PORTP */ - PORTCFG_VP13MAP_PORTQ_gc = (0x0E<<4), /* Mapped To PORTQ */ - PORTCFG_VP13MAP_PORTR_gc = (0x0F<<4), /* Mapped To PORTR */ -} PORTCFG_VP13MAP_t; - -/* System Clock Output Port */ -typedef enum PORTCFG_CLKOUT_enum -{ - PORTCFG_CLKOUT_OFF_gc = (0x00<<0), /* System Clock Output Disabled */ - PORTCFG_CLKOUT_PC7_gc = (0x01<<0), /* System Clock Output on Port C pin 7 */ - PORTCFG_CLKOUT_PD7_gc = (0x02<<0), /* System Clock Output on Port D pin 7 */ - PORTCFG_CLKOUT_PE7_gc = (0x03<<0), /* System Clock Output on Port E pin 7 */ -} PORTCFG_CLKOUT_t; - -/* Peripheral Clock Output Select */ -typedef enum PORTCFG_CLKOUTSEL_enum -{ - PORTCFG_CLKOUTSEL_CLK1X_gc = (0x00<<2), /* 1x Peripheral Clock Output to pin */ - PORTCFG_CLKOUTSEL_CLK2X_gc = (0x01<<2), /* 2x Peripheral Clock Output to pin */ - PORTCFG_CLKOUTSEL_CLK4X_gc = (0x02<<2), /* 4x Peripheral Clock Output to pin */ -} PORTCFG_CLKOUTSEL_t; - -/* Event Output Port */ -typedef enum PORTCFG_EVOUT_enum -{ - PORTCFG_EVOUT_OFF_gc = (0x00<<4), /* Event Output Disabled */ - PORTCFG_EVOUT_PC7_gc = (0x01<<4), /* Event Channel 7 Output on Port C pin 7 */ - PORTCFG_EVOUT_PD7_gc = (0x02<<4), /* Event Channel 7 Output on Port D pin 7 */ - PORTCFG_EVOUT_PE7_gc = (0x03<<4), /* Event Channel 7 Output on Port E pin 7 */ -} PORTCFG_EVOUT_t; - -/* Clock and Event Output Port */ -typedef enum PORTCFG_CLKEVPIN_enum -{ - PORTCFG_CLKEVPIN_PIN7_gc = (0x00<<7), /* Clock and Event Ouput on PIN 7 */ - PORTCFG_CLKEVPIN_PIN4_gc = (0x01<<7), /* Clock and Event Ouput on PIN 4 */ -} PORTCFG_CLKEVPIN_t; - -/* EBI Address Output Port */ -typedef enum PORTCFG_EBIADROUT_enum -{ - PORTCFG_EBIADROUT_PF_gc = (0x00<<2), /* EBI port 3 address output on PORTF pins 0 to 7 */ - PORTCFG_EBIADROUT_PE_gc = (0x01<<2), /* EBI port 3 address output on PORTE pins 0 to 7 */ - PORTCFG_EBIADROUT_PFH_gc = (0x02<<2), /* EBI port 3 address output on PORTF pins 4 to 7 */ - PORTCFG_EBIADROUT_PEH_gc = (0x03<<2), /* EBI port 3 address output on PORTE pins 4 to 7 */ -} PORTCFG_EBIADROUT_t; - -/* EBI Chip Select Output Port */ -typedef enum PORTCFG_EBICSOUT_enum -{ - PORTCFG_EBICSOUT_PH_gc = (0x00<<0), /* EBI chip select output to PORTH pin 4 to 7 */ - PORTCFG_EBICSOUT_PL_gc = (0x01<<0), /* EBI chip select output to PORTL pin 4 to 7 */ - PORTCFG_EBICSOUT_PF_gc = (0x02<<0), /* EBI chip select output to PORTF pin 4 to 7 */ - PORTCFG_EBICSOUT_PE_gc = (0x03<<0), /* EBI chip select output to PORTE pin 4 to 7 */ -} PORTCFG_EBICSOUT_t; - -/* Event Output Select */ -typedef enum PORTCFG_EVOUTSEL_enum -{ - PORTCFG_EVOUTSEL_0_gc = (0x00<<0), /* Event Channel 0 output to pin */ - PORTCFG_EVOUTSEL_1_gc = (0x01<<0), /* Event Channel 1 output to pin */ - PORTCFG_EVOUTSEL_2_gc = (0x02<<0), /* Event Channel 2 output to pin */ - PORTCFG_EVOUTSEL_3_gc = (0x03<<0), /* Event Channel 3 output to pin */ - PORTCFG_EVOUTSEL_4_gc = (0x04<<0), /* Event Channel 4 output to pin */ - PORTCFG_EVOUTSEL_5_gc = (0x05<<0), /* Event Channel 5 output to pin */ - PORTCFG_EVOUTSEL_6_gc = (0x06<<0), /* Event Channel 6 output to pin */ - PORTCFG_EVOUTSEL_7_gc = (0x07<<0), /* Event Channel 7 output to pin */ -} PORTCFG_EVOUTSEL_t; - - -/* --------------------------------------------------------------------------- -AES - AES Module --------------------------------------------------------------------------- -*/ - -/* AES Module */ -typedef struct AES_struct -{ - register8_t CTRL; /* AES Control Register */ - register8_t STATUS; /* AES Status Register */ - register8_t STATE; /* AES State Register */ - register8_t KEY; /* AES Key Register */ - register8_t INTCTRL; /* AES Interrupt Control Register */ -} AES_t; - -/* Interrupt level */ -typedef enum AES_INTLVL_enum -{ - AES_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - AES_INTLVL_LO_gc = (0x01<<0), /* Low Level */ - AES_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ - AES_INTLVL_HI_gc = (0x03<<0), /* High Level */ -} AES_INTLVL_t; - - -/* --------------------------------------------------------------------------- -CRC - Cyclic Redundancy Checker --------------------------------------------------------------------------- -*/ - -/* Cyclic Redundancy Checker */ -typedef struct CRC_struct -{ - register8_t CTRL; /* Control Register */ - register8_t STATUS; /* Status Register */ - register8_t reserved_0x02; - register8_t DATAIN; /* Data Input */ - register8_t CHECKSUM0; /* Checksum byte 0 */ - register8_t CHECKSUM1; /* Checksum byte 1 */ - register8_t CHECKSUM2; /* Checksum byte 2 */ - register8_t CHECKSUM3; /* Checksum byte 3 */ -} CRC_t; - -/* Reset */ -typedef enum CRC_RESET_enum -{ - CRC_RESET_NO_gc = (0x00<<6), /* No Reset */ - CRC_RESET_RESET0_gc = (0x02<<6), /* Reset CRC with CHECKSUM to all zeros */ - CRC_RESET_RESET1_gc = (0x03<<6), /* Reset CRC with CHECKSUM to all ones */ -} CRC_RESET_t; - -/* Input Source */ -typedef enum CRC_SOURCE_enum -{ - CRC_SOURCE_DISABLE_gc = (0x00<<0), /* Disabled */ - CRC_SOURCE_IO_gc = (0x01<<0), /* I/O Interface */ - CRC_SOURCE_FLASH_gc = (0x02<<0), /* Flash */ - CRC_SOURCE_DMAC0_gc = (0x04<<0), /* DMAC Channel 0 */ - CRC_SOURCE_DMAC1_gc = (0x05<<0), /* DMAC Channel 1 */ - CRC_SOURCE_DMAC2_gc = (0x06<<0), /* DMAC Channel 2 */ - CRC_SOURCE_DMAC3_gc = (0x07<<0), /* DMAC Channel 3 */ -} CRC_SOURCE_t; - - -/* --------------------------------------------------------------------------- -DMA - DMA Controller --------------------------------------------------------------------------- -*/ - -/* DMA Channel */ -typedef struct DMA_CH_struct -{ - register8_t CTRLA; /* Channel Control */ - register8_t CTRLB; /* Channel Control */ - register8_t ADDRCTRL; /* Address Control */ - register8_t TRIGSRC; /* Channel Trigger Source */ - _WORDREGISTER(TRFCNT); /* Channel Block Transfer Count */ - register8_t REPCNT; /* Channel Repeat Count */ - register8_t reserved_0x07; - register8_t SRCADDR0; /* Channel Source Address 0 */ - register8_t SRCADDR1; /* Channel Source Address 1 */ - register8_t SRCADDR2; /* Channel Source Address 2 */ - register8_t reserved_0x0B; - register8_t DESTADDR0; /* Channel Destination Address 0 */ - register8_t DESTADDR1; /* Channel Destination Address 1 */ - register8_t DESTADDR2; /* Channel Destination Address 2 */ - register8_t reserved_0x0F; -} DMA_CH_t; - - -/* DMA Controller */ -typedef struct DMA_struct -{ - register8_t CTRL; /* Control */ - register8_t reserved_0x01; - register8_t reserved_0x02; - register8_t INTFLAGS; /* Transfer Interrupt Status */ - register8_t STATUS; /* Status */ - register8_t reserved_0x05; - _WORDREGISTER(TEMP); /* Temporary Register For 16/24-bit Access */ - register8_t reserved_0x08; - register8_t reserved_0x09; - register8_t reserved_0x0A; - register8_t reserved_0x0B; - register8_t reserved_0x0C; - register8_t reserved_0x0D; - register8_t reserved_0x0E; - register8_t reserved_0x0F; - DMA_CH_t CH0; /* DMA Channel 0 */ - DMA_CH_t CH1; /* DMA Channel 1 */ - DMA_CH_t CH2; /* DMA Channel 2 */ - DMA_CH_t CH3; /* DMA Channel 3 */ -} DMA_t; - -/* Burst mode */ -typedef enum DMA_CH_BURSTLEN_enum -{ - DMA_CH_BURSTLEN_1BYTE_gc = (0x00<<0), /* 1-byte burst mode */ - DMA_CH_BURSTLEN_2BYTE_gc = (0x01<<0), /* 2-byte burst mode */ - DMA_CH_BURSTLEN_4BYTE_gc = (0x02<<0), /* 4-byte burst mode */ - DMA_CH_BURSTLEN_8BYTE_gc = (0x03<<0), /* 8-byte burst mode */ -} DMA_CH_BURSTLEN_t; - -/* Source address reload mode */ -typedef enum DMA_CH_SRCRELOAD_enum -{ - DMA_CH_SRCRELOAD_NONE_gc = (0x00<<6), /* No reload */ - DMA_CH_SRCRELOAD_BLOCK_gc = (0x01<<6), /* Reload at end of block */ - DMA_CH_SRCRELOAD_BURST_gc = (0x02<<6), /* Reload at end of burst */ - DMA_CH_SRCRELOAD_TRANSACTION_gc = (0x03<<6), /* Reload at end of transaction */ -} DMA_CH_SRCRELOAD_t; - -/* Source addressing mode */ -typedef enum DMA_CH_SRCDIR_enum -{ - DMA_CH_SRCDIR_FIXED_gc = (0x00<<4), /* Fixed */ - DMA_CH_SRCDIR_INC_gc = (0x01<<4), /* Increment */ - DMA_CH_SRCDIR_DEC_gc = (0x02<<4), /* Decrement */ -} DMA_CH_SRCDIR_t; - -/* Destination adress reload mode */ -typedef enum DMA_CH_DESTRELOAD_enum -{ - DMA_CH_DESTRELOAD_NONE_gc = (0x00<<2), /* No reload */ - DMA_CH_DESTRELOAD_BLOCK_gc = (0x01<<2), /* Reload at end of block */ - DMA_CH_DESTRELOAD_BURST_gc = (0x02<<2), /* Reload at end of burst */ - DMA_CH_DESTRELOAD_TRANSACTION_gc = (0x03<<2), /* Reload at end of transaction */ -} DMA_CH_DESTRELOAD_t; - -/* Destination adressing mode */ -typedef enum DMA_CH_DESTDIR_enum -{ - DMA_CH_DESTDIR_FIXED_gc = (0x00<<0), /* Fixed */ - DMA_CH_DESTDIR_INC_gc = (0x01<<0), /* Increment */ - DMA_CH_DESTDIR_DEC_gc = (0x02<<0), /* Decrement */ -} DMA_CH_DESTDIR_t; - -/* Transfer trigger source */ -typedef enum DMA_CH_TRIGSRC_enum -{ - DMA_CH_TRIGSRC_OFF_gc = (0x00<<0), /* Off software triggers only */ - DMA_CH_TRIGSRC_EVSYS_CH0_gc = (0x01<<0), /* Event System Channel 0 */ - DMA_CH_TRIGSRC_EVSYS_CH1_gc = (0x02<<0), /* Event System Channel 1 */ - DMA_CH_TRIGSRC_EVSYS_CH2_gc = (0x03<<0), /* Event System Channel 2 */ - DMA_CH_TRIGSRC_ADCA_CH0_gc = (0x10<<0), /* ADCA Channel 0 */ - DMA_CH_TRIGSRC_ADCA_CH1_gc = (0x11<<0), /* ADCA Channel 1 */ - DMA_CH_TRIGSRC_ADCA_CH2_gc = (0x12<<0), /* ADCA Channel 2 */ - DMA_CH_TRIGSRC_ADCA_CH3_gc = (0x13<<0), /* ADCA Channel 3 */ - DMA_CH_TRIGSRC_ADCA_CH4_gc = (0x14<<0), /* ADCA Channel 0,1,2,3 combined */ - DMA_CH_TRIGSRC_DACA_CH0_gc = (0x15<<0), /* DACA Channel 0 */ - DMA_CH_TRIGSRC_DACA_CH1_gc = (0x16<<0), /* DACA Channel 1 */ - DMA_CH_TRIGSRC_ADCB_CH0_gc = (0x20<<0), /* ADCB Channel 0 */ - DMA_CH_TRIGSRC_ADCB_CH1_gc = (0x21<<0), /* ADCB Channel 1 */ - DMA_CH_TRIGSRC_ADCB_CH2_gc = (0x22<<0), /* ADCB Channel 2 */ - DMA_CH_TRIGSRC_ADCB_CH3_gc = (0x23<<0), /* ADCB Channel 3 */ - DMA_CH_TRIGSRC_ADCB_CH4_gc = (0x24<<0), /* ADCB Channel 0,1,2,3 combined */ - DMA_CH_TRIGSRC_DACB_CH0_gc = (0x25<<0), /* DACB Channel 0 */ - DMA_CH_TRIGSRC_DACB_CH1_gc = (0x26<<0), /* DACB Channel 1 */ - DMA_CH_TRIGSRC_TCC0_OVF_gc = (0x40<<0), /* Timer/Counter C0 Overflow */ - DMA_CH_TRIGSRC_TCC0_ERR_gc = (0x41<<0), /* Timer/Counter C0 Error */ - DMA_CH_TRIGSRC_TCC0_CCA_gc = (0x42<<0), /* Timer/Counter C0 Compare or Capture A */ - DMA_CH_TRIGSRC_TCC0_CCB_gc = (0x43<<0), /* Timer/Counter C0 Compare or Capture B */ - DMA_CH_TRIGSRC_TCC0_CCC_gc = (0x44<<0), /* Timer/Counter C0 Compare or Capture C */ - DMA_CH_TRIGSRC_TCC0_CCD_gc = (0x45<<0), /* Timer/Counter C0 Compare or Capture D */ - DMA_CH_TRIGSRC_TCC1_OVF_gc = (0x46<<0), /* Timer/Counter C1 Overflow */ - DMA_CH_TRIGSRC_TCC1_ERR_gc = (0x47<<0), /* Timer/Counter C1 Error */ - DMA_CH_TRIGSRC_TCC1_CCA_gc = (0x48<<0), /* Timer/Counter C1 Compare or Capture A */ - DMA_CH_TRIGSRC_TCC1_CCB_gc = (0x49<<0), /* Timer/Counter C1 Compare or Capture B */ - DMA_CH_TRIGSRC_SPIC_gc = (0x4A<<0), /* SPI C Transfer Complete */ - DMA_CH_TRIGSRC_USARTC0_RXC_gc = (0x4B<<0), /* USART C0 Receive Complete */ - DMA_CH_TRIGSRC_USARTC0_DRE_gc = (0x4C<<0), /* USART C0 Data Register Empty */ - DMA_CH_TRIGSRC_USARTC1_RXC_gc = (0x4E<<0), /* USART C1 Receive Complete */ - DMA_CH_TRIGSRC_USARTC1_DRE_gc = (0x4F<<0), /* USART C1 Data Register Empty */ - DMA_CH_TRIGSRC_TCD0_OVF_gc = (0x60<<0), /* Timer/Counter D0 Overflow */ - DMA_CH_TRIGSRC_TCD0_ERR_gc = (0x61<<0), /* Timer/Counter D0 Error */ - DMA_CH_TRIGSRC_TCD0_CCA_gc = (0x62<<0), /* Timer/Counter D0 Compare or Capture A */ - DMA_CH_TRIGSRC_TCD0_CCB_gc = (0x63<<0), /* Timer/Counter D0 Compare or Capture B */ - DMA_CH_TRIGSRC_TCD0_CCC_gc = (0x64<<0), /* Timer/Counter D0 Compare or Capture C */ - DMA_CH_TRIGSRC_TCD0_CCD_gc = (0x65<<0), /* Timer/Counter D0 Compare or Capture D */ - DMA_CH_TRIGSRC_TCD1_OVF_gc = (0x66<<0), /* Timer/Counter D1 Overflow */ - DMA_CH_TRIGSRC_TCD1_ERR_gc = (0x67<<0), /* Timer/Counter D1 Error */ - DMA_CH_TRIGSRC_TCD1_CCA_gc = (0x68<<0), /* Timer/Counter D1 Compare or Capture A */ - DMA_CH_TRIGSRC_TCD1_CCB_gc = (0x69<<0), /* Timer/Counter D1 Compare or Capture B */ - DMA_CH_TRIGSRC_SPID_gc = (0x6A<<0), /* SPI D Transfer Complete */ - DMA_CH_TRIGSRC_USARTD0_RXC_gc = (0x6B<<0), /* USART D0 Receive Complete */ - DMA_CH_TRIGSRC_USARTD0_DRE_gc = (0x6C<<0), /* USART D0 Data Register Empty */ - DMA_CH_TRIGSRC_USARTD1_RXC_gc = (0x6E<<0), /* USART D1 Receive Complete */ - DMA_CH_TRIGSRC_USARTD1_DRE_gc = (0x6F<<0), /* USART D1 Data Register Empty */ - DMA_CH_TRIGSRC_TCE0_OVF_gc = (0x80<<0), /* Timer/Counter E0 Overflow */ - DMA_CH_TRIGSRC_TCE0_ERR_gc = (0x81<<0), /* Timer/Counter E0 Error */ - DMA_CH_TRIGSRC_TCE0_CCA_gc = (0x82<<0), /* Timer/Counter E0 Compare or Capture A */ - DMA_CH_TRIGSRC_TCE0_CCB_gc = (0x83<<0), /* Timer/Counter E0 Compare or Capture B */ - DMA_CH_TRIGSRC_TCE0_CCC_gc = (0x84<<0), /* Timer/Counter E0 Compare or Capture C */ - DMA_CH_TRIGSRC_TCE0_CCD_gc = (0x85<<0), /* Timer/Counter E0 Compare or Capture D */ - DMA_CH_TRIGSRC_TCE1_OVF_gc = (0x86<<0), /* Timer/Counter E1 Overflow */ - DMA_CH_TRIGSRC_TCE1_ERR_gc = (0x87<<0), /* Timer/Counter E1 Error */ - DMA_CH_TRIGSRC_TCE1_CCA_gc = (0x88<<0), /* Timer/Counter E1 Compare or Capture A */ - DMA_CH_TRIGSRC_TCE1_CCB_gc = (0x89<<0), /* Timer/Counter E1 Compare or Capture B */ - DMA_CH_TRIGSRC_SPIE_gc = (0x8A<<0), /* SPI E Transfer Complete */ - DMA_CH_TRIGSRC_USARTE0_RXC_gc = (0x8B<<0), /* USART E0 Receive Complete */ - DMA_CH_TRIGSRC_USARTE0_DRE_gc = (0x8C<<0), /* USART E0 Data Register Empty */ - DMA_CH_TRIGSRC_USARTE1_RXC_gc = (0x8E<<0), /* USART E1 Receive Complete */ - DMA_CH_TRIGSRC_USARTE1_DRE_gc = (0x8F<<0), /* USART E1 Data Register Empty */ - DMA_CH_TRIGSRC_TCF0_OVF_gc = (0xA0<<0), /* Timer/Counter F0 Overflow */ - DMA_CH_TRIGSRC_TCF0_ERR_gc = (0xA1<<0), /* Timer/Counter F0 Error */ - DMA_CH_TRIGSRC_TCF0_CCA_gc = (0xA2<<0), /* Timer/Counter F0 Compare or Capture A */ - DMA_CH_TRIGSRC_TCF0_CCB_gc = (0xA3<<0), /* Timer/Counter F0 Compare or Capture B */ - DMA_CH_TRIGSRC_TCF0_CCC_gc = (0xA4<<0), /* Timer/Counter F0 Compare or Capture C */ - DMA_CH_TRIGSRC_TCF0_CCD_gc = (0xA5<<0), /* Timer/Counter F0 Compare or Capture D */ - DMA_CH_TRIGSRC_TCF1_OVF_gc = (0xA6<<0), /* Timer/Counter F1 Overflow */ - DMA_CH_TRIGSRC_TCF1_ERR_gc = (0xA7<<0), /* Timer/Counter F1 Error */ - DMA_CH_TRIGSRC_TCF1_CCA_gc = (0xA8<<0), /* Timer/Counter F1 Compare or Capture A */ - DMA_CH_TRIGSRC_TCF1_CCB_gc = (0xA9<<0), /* Timer/Counter F1 Compare or Capture B */ - DMA_CH_TRIGSRC_SPIF_gc = (0xAA<<0), /* SPI F Transfer Complete */ - DMA_CH_TRIGSRC_USARTF0_RXC_gc = (0xAB<<0), /* USART F0 Receive Complete */ - DMA_CH_TRIGSRC_USARTF0_DRE_gc = (0xAC<<0), /* USART F0 Data Register Empty */ - DMA_CH_TRIGSRC_USARTF1_RXC_gc = (0xAE<<0), /* USART F1 Receive Complete */ - DMA_CH_TRIGSRC_USARTF1_DRE_gc = (0xAF<<0), /* USART F1 Data Register Empty */ -} DMA_CH_TRIGSRC_t; - -/* Double buffering mode */ -typedef enum DMA_DBUFMODE_enum -{ - DMA_DBUFMODE_DISABLED_gc = (0x00<<2), /* Double buffering disabled */ - DMA_DBUFMODE_CH01_gc = (0x01<<2), /* Double buffering enabled on channel 0/1 */ - DMA_DBUFMODE_CH23_gc = (0x02<<2), /* Double buffering enabled on channel 2/3 */ - DMA_DBUFMODE_CH01CH23_gc = (0x03<<2), /* Double buffering enabled on ch. 0/1 and ch. 2/3 */ -} DMA_DBUFMODE_t; - -/* Priority mode */ -typedef enum DMA_PRIMODE_enum -{ - DMA_PRIMODE_RR0123_gc = (0x00<<0), /* Round Robin */ - DMA_PRIMODE_CH0RR123_gc = (0x01<<0), /* Channel 0 > Round Robin on channel 1/2/3 */ - DMA_PRIMODE_CH01RR23_gc = (0x02<<0), /* Channel 0 > channel 1 > Round Robin on channel 2/3 */ - DMA_PRIMODE_CH0123_gc = (0x03<<0), /* Channel 0 > channel 1 > channel 2 > channel 3 */ -} DMA_PRIMODE_t; - -/* Interrupt level */ -typedef enum DMA_CH_ERRINTLVL_enum -{ - DMA_CH_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ - DMA_CH_ERRINTLVL_LO_gc = (0x01<<2), /* Low level */ - DMA_CH_ERRINTLVL_MED_gc = (0x02<<2), /* Medium level */ - DMA_CH_ERRINTLVL_HI_gc = (0x03<<2), /* High level */ -} DMA_CH_ERRINTLVL_t; - -/* Interrupt level */ -typedef enum DMA_CH_TRNINTLVL_enum -{ - DMA_CH_TRNINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ - DMA_CH_TRNINTLVL_LO_gc = (0x01<<0), /* Low level */ - DMA_CH_TRNINTLVL_MED_gc = (0x02<<0), /* Medium level */ - DMA_CH_TRNINTLVL_HI_gc = (0x03<<0), /* High level */ -} DMA_CH_TRNINTLVL_t; - - -/* --------------------------------------------------------------------------- -EVSYS - Event System --------------------------------------------------------------------------- -*/ - -/* Event System */ -typedef struct EVSYS_struct -{ - register8_t CH0MUX; /* Event Channel 0 Multiplexer */ - register8_t CH1MUX; /* Event Channel 1 Multiplexer */ - register8_t CH2MUX; /* Event Channel 2 Multiplexer */ - register8_t CH3MUX; /* Event Channel 3 Multiplexer */ - register8_t CH4MUX; /* Event Channel 4 Multiplexer */ - register8_t CH5MUX; /* Event Channel 5 Multiplexer */ - register8_t CH6MUX; /* Event Channel 6 Multiplexer */ - register8_t CH7MUX; /* Event Channel 7 Multiplexer */ - register8_t CH0CTRL; /* Channel 0 Control Register */ - register8_t CH1CTRL; /* Channel 1 Control Register */ - register8_t CH2CTRL; /* Channel 2 Control Register */ - register8_t CH3CTRL; /* Channel 3 Control Register */ - register8_t CH4CTRL; /* Channel 4 Control Register */ - register8_t CH5CTRL; /* Channel 5 Control Register */ - register8_t CH6CTRL; /* Channel 6 Control Register */ - register8_t CH7CTRL; /* Channel 7 Control Register */ - register8_t STROBE; /* Event Strobe */ - register8_t DATA; /* Event Data */ -} EVSYS_t; - -/* Quadrature Decoder Index Recognition Mode */ -typedef enum EVSYS_QDIRM_enum -{ - EVSYS_QDIRM_00_gc = (0x00<<5), /* QDPH0 = 0, QDPH90 = 0 */ - EVSYS_QDIRM_01_gc = (0x01<<5), /* QDPH0 = 0, QDPH90 = 1 */ - EVSYS_QDIRM_10_gc = (0x02<<5), /* QDPH0 = 1, QDPH90 = 0 */ - EVSYS_QDIRM_11_gc = (0x03<<5), /* QDPH0 = 1, QDPH90 = 1 */ -} EVSYS_QDIRM_t; - -/* Digital filter coefficient */ -typedef enum EVSYS_DIGFILT_enum -{ - EVSYS_DIGFILT_1SAMPLE_gc = (0x00<<0), /* 1 SAMPLE */ - EVSYS_DIGFILT_2SAMPLES_gc = (0x01<<0), /* 2 SAMPLES */ - EVSYS_DIGFILT_3SAMPLES_gc = (0x02<<0), /* 3 SAMPLES */ - EVSYS_DIGFILT_4SAMPLES_gc = (0x03<<0), /* 4 SAMPLES */ - EVSYS_DIGFILT_5SAMPLES_gc = (0x04<<0), /* 5 SAMPLES */ - EVSYS_DIGFILT_6SAMPLES_gc = (0x05<<0), /* 6 SAMPLES */ - EVSYS_DIGFILT_7SAMPLES_gc = (0x06<<0), /* 7 SAMPLES */ - EVSYS_DIGFILT_8SAMPLES_gc = (0x07<<0), /* 8 SAMPLES */ -} EVSYS_DIGFILT_t; - -/* Event Channel multiplexer input selection */ -typedef enum EVSYS_CHMUX_enum -{ - EVSYS_CHMUX_OFF_gc = (0x00<<0), /* Off */ - EVSYS_CHMUX_RTC_OVF_gc = (0x08<<0), /* RTC Overflow */ - EVSYS_CHMUX_RTC_CMP_gc = (0x09<<0), /* RTC Compare Match */ - EVSYS_CHMUX_USB_gc = (0x0A<<0), /* USB Setup, SOF, CRC error and UNF/OVF */ - EVSYS_CHMUX_ACA_CH0_gc = (0x10<<0), /* Analog Comparator A Channel 0 */ - EVSYS_CHMUX_ACA_CH1_gc = (0x11<<0), /* Analog Comparator A Channel 1 */ - EVSYS_CHMUX_ACA_WIN_gc = (0x12<<0), /* Analog Comparator A Window */ - EVSYS_CHMUX_ACB_CH0_gc = (0x13<<0), /* Analog Comparator B Channel 0 */ - EVSYS_CHMUX_ACB_CH1_gc = (0x14<<0), /* Analog Comparator B Channel 1 */ - EVSYS_CHMUX_ACB_WIN_gc = (0x15<<0), /* Analog Comparator B Window */ - EVSYS_CHMUX_ADCA_CH0_gc = (0x20<<0), /* ADC A Channel 0 */ - EVSYS_CHMUX_ADCA_CH1_gc = (0x21<<0), /* ADC A Channel 1 */ - EVSYS_CHMUX_ADCA_CH2_gc = (0x22<<0), /* ADC A Channel 2 */ - EVSYS_CHMUX_ADCA_CH3_gc = (0x23<<0), /* ADC A Channel 3 */ - EVSYS_CHMUX_ADCB_CH0_gc = (0x24<<0), /* ADC B Channel 0 */ - EVSYS_CHMUX_ADCB_CH1_gc = (0x25<<0), /* ADC B Channel 1 */ - EVSYS_CHMUX_ADCB_CH2_gc = (0x26<<0), /* ADC B Channel 2 */ - EVSYS_CHMUX_ADCB_CH3_gc = (0x27<<0), /* ADC B Channel 3 */ - EVSYS_CHMUX_PORTA_PIN0_gc = (0x50<<0), /* Port A, Pin0 */ - EVSYS_CHMUX_PORTA_PIN1_gc = (0x51<<0), /* Port A, Pin1 */ - EVSYS_CHMUX_PORTA_PIN2_gc = (0x52<<0), /* Port A, Pin2 */ - EVSYS_CHMUX_PORTA_PIN3_gc = (0x53<<0), /* Port A, Pin3 */ - EVSYS_CHMUX_PORTA_PIN4_gc = (0x54<<0), /* Port A, Pin4 */ - EVSYS_CHMUX_PORTA_PIN5_gc = (0x55<<0), /* Port A, Pin5 */ - EVSYS_CHMUX_PORTA_PIN6_gc = (0x56<<0), /* Port A, Pin6 */ - EVSYS_CHMUX_PORTA_PIN7_gc = (0x57<<0), /* Port A, Pin7 */ - EVSYS_CHMUX_PORTB_PIN0_gc = (0x58<<0), /* Port B, Pin0 */ - EVSYS_CHMUX_PORTB_PIN1_gc = (0x59<<0), /* Port B, Pin1 */ - EVSYS_CHMUX_PORTB_PIN2_gc = (0x5A<<0), /* Port B, Pin2 */ - EVSYS_CHMUX_PORTB_PIN3_gc = (0x5B<<0), /* Port B, Pin3 */ - EVSYS_CHMUX_PORTB_PIN4_gc = (0x5C<<0), /* Port B, Pin4 */ - EVSYS_CHMUX_PORTB_PIN5_gc = (0x5D<<0), /* Port B, Pin5 */ - EVSYS_CHMUX_PORTB_PIN6_gc = (0x5E<<0), /* Port B, Pin6 */ - EVSYS_CHMUX_PORTB_PIN7_gc = (0x5F<<0), /* Port B, Pin7 */ - EVSYS_CHMUX_PORTC_PIN0_gc = (0x60<<0), /* Port C, Pin0 */ - EVSYS_CHMUX_PORTC_PIN1_gc = (0x61<<0), /* Port C, Pin1 */ - EVSYS_CHMUX_PORTC_PIN2_gc = (0x62<<0), /* Port C, Pin2 */ - EVSYS_CHMUX_PORTC_PIN3_gc = (0x63<<0), /* Port C, Pin3 */ - EVSYS_CHMUX_PORTC_PIN4_gc = (0x64<<0), /* Port C, Pin4 */ - EVSYS_CHMUX_PORTC_PIN5_gc = (0x65<<0), /* Port C, Pin5 */ - EVSYS_CHMUX_PORTC_PIN6_gc = (0x66<<0), /* Port C, Pin6 */ - EVSYS_CHMUX_PORTC_PIN7_gc = (0x67<<0), /* Port C, Pin7 */ - EVSYS_CHMUX_PORTD_PIN0_gc = (0x68<<0), /* Port D, Pin0 */ - EVSYS_CHMUX_PORTD_PIN1_gc = (0x69<<0), /* Port D, Pin1 */ - EVSYS_CHMUX_PORTD_PIN2_gc = (0x6A<<0), /* Port D, Pin2 */ - EVSYS_CHMUX_PORTD_PIN3_gc = (0x6B<<0), /* Port D, Pin3 */ - EVSYS_CHMUX_PORTD_PIN4_gc = (0x6C<<0), /* Port D, Pin4 */ - EVSYS_CHMUX_PORTD_PIN5_gc = (0x6D<<0), /* Port D, Pin5 */ - EVSYS_CHMUX_PORTD_PIN6_gc = (0x6E<<0), /* Port D, Pin6 */ - EVSYS_CHMUX_PORTD_PIN7_gc = (0x6F<<0), /* Port D, Pin7 */ - EVSYS_CHMUX_PORTE_PIN0_gc = (0x70<<0), /* Port E, Pin0 */ - EVSYS_CHMUX_PORTE_PIN1_gc = (0x71<<0), /* Port E, Pin1 */ - EVSYS_CHMUX_PORTE_PIN2_gc = (0x72<<0), /* Port E, Pin2 */ - EVSYS_CHMUX_PORTE_PIN3_gc = (0x73<<0), /* Port E, Pin3 */ - EVSYS_CHMUX_PORTE_PIN4_gc = (0x74<<0), /* Port E, Pin4 */ - EVSYS_CHMUX_PORTE_PIN5_gc = (0x75<<0), /* Port E, Pin5 */ - EVSYS_CHMUX_PORTE_PIN6_gc = (0x76<<0), /* Port E, Pin6 */ - EVSYS_CHMUX_PORTE_PIN7_gc = (0x77<<0), /* Port E, Pin7 */ - EVSYS_CHMUX_PORTF_PIN0_gc = (0x78<<0), /* Port F, Pin0 */ - EVSYS_CHMUX_PORTF_PIN1_gc = (0x79<<0), /* Port F, Pin1 */ - EVSYS_CHMUX_PORTF_PIN2_gc = (0x7A<<0), /* Port F, Pin2 */ - EVSYS_CHMUX_PORTF_PIN3_gc = (0x7B<<0), /* Port F, Pin3 */ - EVSYS_CHMUX_PORTF_PIN4_gc = (0x7C<<0), /* Port F, Pin4 */ - EVSYS_CHMUX_PORTF_PIN5_gc = (0x7D<<0), /* Port F, Pin5 */ - EVSYS_CHMUX_PORTF_PIN6_gc = (0x7E<<0), /* Port F, Pin6 */ - EVSYS_CHMUX_PORTF_PIN7_gc = (0x7F<<0), /* Port F, Pin7 */ - EVSYS_CHMUX_PRESCALER_1_gc = (0x80<<0), /* Prescaler, divide by 1 */ - EVSYS_CHMUX_PRESCALER_2_gc = (0x81<<0), /* Prescaler, divide by 2 */ - EVSYS_CHMUX_PRESCALER_4_gc = (0x82<<0), /* Prescaler, divide by 4 */ - EVSYS_CHMUX_PRESCALER_8_gc = (0x83<<0), /* Prescaler, divide by 8 */ - EVSYS_CHMUX_PRESCALER_16_gc = (0x84<<0), /* Prescaler, divide by 16 */ - EVSYS_CHMUX_PRESCALER_32_gc = (0x85<<0), /* Prescaler, divide by 32 */ - EVSYS_CHMUX_PRESCALER_64_gc = (0x86<<0), /* Prescaler, divide by 64 */ - EVSYS_CHMUX_PRESCALER_128_gc = (0x87<<0), /* Prescaler, divide by 128 */ - EVSYS_CHMUX_PRESCALER_256_gc = (0x88<<0), /* Prescaler, divide by 256 */ - EVSYS_CHMUX_PRESCALER_512_gc = (0x89<<0), /* Prescaler, divide by 512 */ - EVSYS_CHMUX_PRESCALER_1024_gc = (0x8A<<0), /* Prescaler, divide by 1024 */ - EVSYS_CHMUX_PRESCALER_2048_gc = (0x8B<<0), /* Prescaler, divide by 2048 */ - EVSYS_CHMUX_PRESCALER_4096_gc = (0x8C<<0), /* Prescaler, divide by 4096 */ - EVSYS_CHMUX_PRESCALER_8192_gc = (0x8D<<0), /* Prescaler, divide by 8192 */ - EVSYS_CHMUX_PRESCALER_16384_gc = (0x8E<<0), /* Prescaler, divide by 16384 */ - EVSYS_CHMUX_PRESCALER_32768_gc = (0x8F<<0), /* Prescaler, divide by 32768 */ - EVSYS_CHMUX_TCC0_OVF_gc = (0xC0<<0), /* Timer/Counter C0 Overflow */ - EVSYS_CHMUX_TCC0_ERR_gc = (0xC1<<0), /* Timer/Counter C0 Error */ - EVSYS_CHMUX_TCC0_CCA_gc = (0xC4<<0), /* Timer/Counter C0 Compare or Capture A */ - EVSYS_CHMUX_TCC0_CCB_gc = (0xC5<<0), /* Timer/Counter C0 Compare or Capture B */ - EVSYS_CHMUX_TCC0_CCC_gc = (0xC6<<0), /* Timer/Counter C0 Compare or Capture C */ - EVSYS_CHMUX_TCC0_CCD_gc = (0xC7<<0), /* Timer/Counter C0 Compare or Capture D */ - EVSYS_CHMUX_TCC1_OVF_gc = (0xC8<<0), /* Timer/Counter C1 Overflow */ - EVSYS_CHMUX_TCC1_ERR_gc = (0xC9<<0), /* Timer/Counter C1 Error */ - EVSYS_CHMUX_TCC1_CCA_gc = (0xCC<<0), /* Timer/Counter C1 Compare or Capture A */ - EVSYS_CHMUX_TCC1_CCB_gc = (0xCD<<0), /* Timer/Counter C1 Compare or Capture B */ - EVSYS_CHMUX_TCD0_OVF_gc = (0xD0<<0), /* Timer/Counter D0 Overflow */ - EVSYS_CHMUX_TCD0_ERR_gc = (0xD1<<0), /* Timer/Counter D0 Error */ - EVSYS_CHMUX_TCD0_CCA_gc = (0xD4<<0), /* Timer/Counter D0 Compare or Capture A */ - EVSYS_CHMUX_TCD0_CCB_gc = (0xD5<<0), /* Timer/Counter D0 Compare or Capture B */ - EVSYS_CHMUX_TCD0_CCC_gc = (0xD6<<0), /* Timer/Counter D0 Compare or Capture C */ - EVSYS_CHMUX_TCD0_CCD_gc = (0xD7<<0), /* Timer/Counter D0 Compare or Capture D */ - EVSYS_CHMUX_TCD1_OVF_gc = (0xD8<<0), /* Timer/Counter D1 Overflow */ - EVSYS_CHMUX_TCD1_ERR_gc = (0xD9<<0), /* Timer/Counter D1 Error */ - EVSYS_CHMUX_TCD1_CCA_gc = (0xDC<<0), /* Timer/Counter D1 Compare or Capture A */ - EVSYS_CHMUX_TCD1_CCB_gc = (0xDD<<0), /* Timer/Counter D1 Compare or Capture B */ - EVSYS_CHMUX_TCE0_OVF_gc = (0xE0<<0), /* Timer/Counter E0 Overflow */ - EVSYS_CHMUX_TCE0_ERR_gc = (0xE1<<0), /* Timer/Counter E0 Error */ - EVSYS_CHMUX_TCE0_CCA_gc = (0xE4<<0), /* Timer/Counter E0 Compare or Capture A */ - EVSYS_CHMUX_TCE0_CCB_gc = (0xE5<<0), /* Timer/Counter E0 Compare or Capture B */ - EVSYS_CHMUX_TCE0_CCC_gc = (0xE6<<0), /* Timer/Counter E0 Compare or Capture C */ - EVSYS_CHMUX_TCE0_CCD_gc = (0xE7<<0), /* Timer/Counter E0 Compare or Capture D */ - EVSYS_CHMUX_TCE1_OVF_gc = (0xE8<<0), /* Timer/Counter E1 Overflow */ - EVSYS_CHMUX_TCE1_ERR_gc = (0xE9<<0), /* Timer/Counter E1 Error */ - EVSYS_CHMUX_TCE1_CCA_gc = (0xEC<<0), /* Timer/Counter E1 Compare or Capture A */ - EVSYS_CHMUX_TCE1_CCB_gc = (0xED<<0), /* Timer/Counter E1 Compare or Capture B */ - EVSYS_CHMUX_TCF0_OVF_gc = (0xF0<<0), /* Timer/Counter F0 Overflow */ - EVSYS_CHMUX_TCF0_ERR_gc = (0xF1<<0), /* Timer/Counter F0 Error */ - EVSYS_CHMUX_TCF0_CCA_gc = (0xF4<<0), /* Timer/Counter F0 Compare or Capture A */ - EVSYS_CHMUX_TCF0_CCB_gc = (0xF5<<0), /* Timer/Counter F0 Compare or Capture B */ - EVSYS_CHMUX_TCF0_CCC_gc = (0xF6<<0), /* Timer/Counter F0 Compare or Capture C */ - EVSYS_CHMUX_TCF0_CCD_gc = (0xF7<<0), /* Timer/Counter F0 Compare or Capture D */ - EVSYS_CHMUX_TCF1_OVF_gc = (0xF8<<0), /* Timer/Counter F1 Overflow */ - EVSYS_CHMUX_TCF1_ERR_gc = (0xF9<<0), /* Timer/Counter F1 Error */ - EVSYS_CHMUX_TCF1_CCA_gc = (0xFC<<0), /* Timer/Counter F1 Compare or Capture A */ - EVSYS_CHMUX_TCF1_CCB_gc = (0xFD<<0), /* Timer/Counter F1 Compare or Capture B */ -} EVSYS_CHMUX_t; - - -/* --------------------------------------------------------------------------- -NVM - Non Volatile Memory Controller --------------------------------------------------------------------------- -*/ - -/* Non-volatile Memory Controller */ -typedef struct NVM_struct -{ - register8_t ADDR0; /* Address Register 0 */ - register8_t ADDR1; /* Address Register 1 */ - register8_t ADDR2; /* Address Register 2 */ - register8_t reserved_0x03; - register8_t DATA0; /* Data Register 0 */ - register8_t DATA1; /* Data Register 1 */ - register8_t DATA2; /* Data Register 2 */ - register8_t reserved_0x07; - register8_t reserved_0x08; - register8_t reserved_0x09; - register8_t CMD; /* Command */ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t INTCTRL; /* Interrupt Control */ - register8_t reserved_0x0E; - register8_t STATUS; /* Status */ - register8_t LOCK_BITS; /* Lock Bits (Changed from LOCKBITS to avoid avr-libc collision) */ -} NVM_t; - -/* NVM Command */ -typedef enum NVM_CMD_enum -{ - NVM_CMD_NO_OPERATION_gc = (0x00<<0), /* Noop/Ordinary LPM */ - NVM_CMD_READ_USER_SIG_ROW_gc = (0x01<<0), /* Read user signature row */ - NVM_CMD_READ_CALIB_ROW_gc = (0x02<<0), /* Read calibration row */ - NVM_CMD_READ_EEPROM_gc = (0x06<<0), /* Read EEPROM */ - NVM_CMD_READ_FUSES_gc = (0x07<<0), /* Read fuse byte */ - NVM_CMD_WRITE_LOCK_BITS_gc = (0x08<<0), /* Write lock bits */ - NVM_CMD_ERASE_USER_SIG_ROW_gc = (0x18<<0), /* Erase user signature row */ - NVM_CMD_WRITE_USER_SIG_ROW_gc = (0x1A<<0), /* Write user signature row */ - NVM_CMD_ERASE_APP_gc = (0x20<<0), /* Erase Application Section */ - NVM_CMD_ERASE_APP_PAGE_gc = (0x22<<0), /* Erase Application Section page */ - NVM_CMD_LOAD_FLASH_BUFFER_gc = (0x23<<0), /* Load Flash page buffer */ - NVM_CMD_WRITE_APP_PAGE_gc = (0x24<<0), /* Write Application Section page */ - NVM_CMD_ERASE_WRITE_APP_PAGE_gc = (0x25<<0), /* Erase-and-write Application Section page */ - NVM_CMD_ERASE_FLASH_BUFFER_gc = (0x26<<0), /* Erase/flush Flash page buffer */ - NVM_CMD_ERASE_BOOT_PAGE_gc = (0x2A<<0), /* Erase Boot Section page */ - NVM_CMD_ERASE_FLASH_PAGE_gc = (0x2B<<0), /* Erase Flash Page */ - NVM_CMD_WRITE_BOOT_PAGE_gc = (0x2C<<0), /* Write Boot Section page */ - NVM_CMD_ERASE_WRITE_BOOT_PAGE_gc = (0x2D<<0), /* Erase-and-write Boot Section page */ - NVM_CMD_WRITE_FLASH_PAGE_gc = (0x2E<<0), /* Write Flash Page */ - NVM_CMD_ERASE_WRITE_FLASH_PAGE_gc = (0x2F<<0), /* Erase-and-write Flash Page */ - NVM_CMD_ERASE_EEPROM_gc = (0x30<<0), /* Erase EEPROM */ - NVM_CMD_ERASE_EEPROM_PAGE_gc = (0x32<<0), /* Erase EEPROM page */ - NVM_CMD_LOAD_EEPROM_BUFFER_gc = (0x33<<0), /* Load EEPROM page buffer */ - NVM_CMD_WRITE_EEPROM_PAGE_gc = (0x34<<0), /* Write EEPROM page */ - NVM_CMD_ERASE_WRITE_EEPROM_PAGE_gc = (0x35<<0), /* Erase-and-write EEPROM page */ - NVM_CMD_ERASE_EEPROM_BUFFER_gc = (0x36<<0), /* Erase/flush EEPROM page buffer */ - NVM_CMD_APP_CRC_gc = (0x38<<0), /* Application section CRC */ - NVM_CMD_BOOT_CRC_gc = (0x39<<0), /* Boot Section CRC */ - NVM_CMD_FLASH_RANGE_CRC_gc = (0x3A<<0), /* Flash Range CRC */ - NVM_CMD_CHIP_ERASE_gc = (0x40<<0), /* Erase Chip */ - NVM_CMD_READ_NVM_gc = (0x43<<0), /* Read NVM */ - NVM_CMD_WRITE_FUSE_gc = (0x4C<<0), /* Write Fuse byte */ - NVM_CMD_ERASE_BOOT_gc = (0x68<<0), /* Erase Boot Section */ - NVM_CMD_FLASH_CRC_gc = (0x78<<0), /* Flash CRC */ -} NVM_CMD_t; - -/* SPM ready interrupt level */ -typedef enum NVM_SPMLVL_enum -{ - NVM_SPMLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ - NVM_SPMLVL_LO_gc = (0x01<<2), /* Low level */ - NVM_SPMLVL_MED_gc = (0x02<<2), /* Medium level */ - NVM_SPMLVL_HI_gc = (0x03<<2), /* High level */ -} NVM_SPMLVL_t; - -/* EEPROM ready interrupt level */ -typedef enum NVM_EELVL_enum -{ - NVM_EELVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ - NVM_EELVL_LO_gc = (0x01<<0), /* Low level */ - NVM_EELVL_MED_gc = (0x02<<0), /* Medium level */ - NVM_EELVL_HI_gc = (0x03<<0), /* High level */ -} NVM_EELVL_t; - -/* Boot lock bits - boot setcion */ -typedef enum NVM_BLBB_enum -{ - NVM_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ - NVM_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ - NVM_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ - NVM_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ -} NVM_BLBB_t; - -/* Boot lock bits - application section */ -typedef enum NVM_BLBA_enum -{ - NVM_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ - NVM_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ - NVM_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ - NVM_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ -} NVM_BLBA_t; - -/* Boot lock bits - application table section */ -typedef enum NVM_BLBAT_enum -{ - NVM_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ - NVM_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ - NVM_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ - NVM_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ -} NVM_BLBAT_t; - -/* Lock bits */ -typedef enum NVM_LB_enum -{ - NVM_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ - NVM_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ - NVM_LB_NOLOCK_gc = (0x03<<0), /* No locks */ -} NVM_LB_t; - - -/* --------------------------------------------------------------------------- -ADC - Analog/Digital Converter --------------------------------------------------------------------------- -*/ - -/* ADC Channel */ -typedef struct ADC_CH_struct -{ - register8_t CTRL; /* Control Register */ - register8_t MUXCTRL; /* MUX Control */ - register8_t INTCTRL; /* Channel Interrupt Control Register */ - register8_t INTFLAGS; /* Interrupt Flags */ - _WORDREGISTER(RES); /* Channel Result */ - register8_t SCAN; /* Input Channel Scan */ - register8_t reserved_0x07; -} ADC_CH_t; - - -/* Analog-to-Digital Converter */ -typedef struct ADC_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t REFCTRL; /* Reference Control */ - register8_t EVCTRL; /* Event Control */ - register8_t PRESCALER; /* Clock Prescaler */ - register8_t reserved_0x05; - register8_t INTFLAGS; /* Interrupt Flags */ - register8_t TEMP; /* Temporary Register */ - register8_t reserved_0x08; - register8_t reserved_0x09; - register8_t reserved_0x0A; - register8_t reserved_0x0B; - _WORDREGISTER(CAL); /* Calibration Value */ - register8_t reserved_0x0E; - register8_t reserved_0x0F; - _WORDREGISTER(CH0RES); /* Channel 0 Result */ - _WORDREGISTER(CH1RES); /* Channel 1 Result */ - _WORDREGISTER(CH2RES); /* Channel 2 Result */ - _WORDREGISTER(CH3RES); /* Channel 3 Result */ - _WORDREGISTER(CMP); /* Compare Value */ - register8_t reserved_0x1A; - register8_t reserved_0x1B; - register8_t reserved_0x1C; - register8_t reserved_0x1D; - register8_t reserved_0x1E; - register8_t reserved_0x1F; - ADC_CH_t CH0; /* ADC Channel 0 */ - ADC_CH_t CH1; /* ADC Channel 1 */ - ADC_CH_t CH2; /* ADC Channel 2 */ - ADC_CH_t CH3; /* ADC Channel 3 */ -} ADC_t; - -/* Positive input multiplexer selection */ -typedef enum ADC_CH_MUXPOS_enum -{ - ADC_CH_MUXPOS_PIN0_gc = (0x00<<3), /* Input pin 0 */ - ADC_CH_MUXPOS_PIN1_gc = (0x01<<3), /* Input pin 1 */ - ADC_CH_MUXPOS_PIN2_gc = (0x02<<3), /* Input pin 2 */ - ADC_CH_MUXPOS_PIN3_gc = (0x03<<3), /* Input pin 3 */ - ADC_CH_MUXPOS_PIN4_gc = (0x04<<3), /* Input pin 4 */ - ADC_CH_MUXPOS_PIN5_gc = (0x05<<3), /* Input pin 5 */ - ADC_CH_MUXPOS_PIN6_gc = (0x06<<3), /* Input pin 6 */ - ADC_CH_MUXPOS_PIN7_gc = (0x07<<3), /* Input pin 7 */ - ADC_CH_MUXPOS_PIN8_gc = (0x08<<3), /* Input pin 8 */ - ADC_CH_MUXPOS_PIN9_gc = (0x09<<3), /* Input pin 9 */ - ADC_CH_MUXPOS_PIN10_gc = (0x0A<<3), /* Input pin 10 */ - ADC_CH_MUXPOS_PIN11_gc = (0x0B<<3), /* Input pin 11 */ - ADC_CH_MUXPOS_PIN12_gc = (0x0C<<3), /* Input pin 12 */ - ADC_CH_MUXPOS_PIN13_gc = (0x0D<<3), /* Input pin 13 */ - ADC_CH_MUXPOS_PIN14_gc = (0x0E<<3), /* Input pin 14 */ - ADC_CH_MUXPOS_PIN15_gc = (0x0F<<3), /* Input pin 15 */ -} ADC_CH_MUXPOS_t; - -/* Internal input multiplexer selections */ -typedef enum ADC_CH_MUXINT_enum -{ - ADC_CH_MUXINT_TEMP_gc = (0x00<<3), /* Temperature Reference */ - ADC_CH_MUXINT_BANDGAP_gc = (0x01<<3), /* Bandgap Reference */ - ADC_CH_MUXINT_SCALEDVCC_gc = (0x02<<3), /* 1/10 scaled VCC */ - ADC_CH_MUXINT_DAC_gc = (0x03<<3), /* DAC output */ -} ADC_CH_MUXINT_t; - -/* Negative input multiplexer selection */ -typedef enum ADC_CH_MUXNEG_enum -{ - ADC_CH_MUXNEG_PIN0_gc = (0x00<<0), /* Input pin 0 (Input Mode = 2) */ - ADC_CH_MUXNEG_PIN1_gc = (0x01<<0), /* Input pin 1 (Input Mode = 2) */ - ADC_CH_MUXNEG_PIN2_gc = (0x02<<0), /* Input pin 2 (Input Mode = 2) */ - ADC_CH_MUXNEG_PIN3_gc = (0x03<<0), /* Input pin 3 (Input Mode = 2) */ - ADC_CH_MUXNEG_PIN4_gc = (0x00<<0), /* Input pin 4 (Input Mode = 3) */ - ADC_CH_MUXNEG_PIN5_gc = (0x01<<0), /* Input pin 5 (Input Mode = 3) */ - ADC_CH_MUXNEG_PIN6_gc = (0x02<<0), /* Input pin 6 (Input Mode = 3) */ - ADC_CH_MUXNEG_PIN7_gc = (0x03<<0), /* Input pin 7 (Input Mode = 3) */ - ADC_CH_MUXNEG_GND_MODE3_gc = (0x05<<0), /* PAD Ground (Input Mode = 2) */ - ADC_CH_MUXNEG_INTGND_MODE3_gc = (0x07<<0), /* Internal Ground (Input Mode = 2) */ - ADC_CH_MUXNEG_INTGND_MODE4_gc = (0x04<<0), /* Internal Ground (Input Mode = 3) */ - ADC_CH_MUXNEG_GND_MODE4_gc = (0x07<<0), /* PAD Ground (Input Mode = 3) */ -} ADC_CH_MUXNEG_t; - -/* Input mode */ -typedef enum ADC_CH_INPUTMODE_enum -{ - ADC_CH_INPUTMODE_INTERNAL_gc = (0x00<<0), /* Internal inputs, no gain */ - ADC_CH_INPUTMODE_SINGLEENDED_gc = (0x01<<0), /* Single-ended input, no gain */ - ADC_CH_INPUTMODE_DIFF_gc = (0x02<<0), /* Differential input, no gain */ - ADC_CH_INPUTMODE_DIFFWGAIN_gc = (0x03<<0), /* Differential input, with gain */ -} ADC_CH_INPUTMODE_t; - -/* Gain factor */ -typedef enum ADC_CH_GAIN_enum -{ - ADC_CH_GAIN_1X_gc = (0x00<<2), /* 1x gain */ - ADC_CH_GAIN_2X_gc = (0x01<<2), /* 2x gain */ - ADC_CH_GAIN_4X_gc = (0x02<<2), /* 4x gain */ - ADC_CH_GAIN_8X_gc = (0x03<<2), /* 8x gain */ - ADC_CH_GAIN_16X_gc = (0x04<<2), /* 16x gain */ - ADC_CH_GAIN_32X_gc = (0x05<<2), /* 32x gain */ - ADC_CH_GAIN_64X_gc = (0x06<<2), /* 64x gain */ - ADC_CH_GAIN_DIV2_gc = (0x07<<2), /* x/2 gain */ -} ADC_CH_GAIN_t; - -/* Conversion result resolution */ -typedef enum ADC_RESOLUTION_enum -{ - ADC_RESOLUTION_12BIT_gc = (0x00<<1), /* 12-bit right-adjusted result */ - ADC_RESOLUTION_8BIT_gc = (0x02<<1), /* 8-bit right-adjusted result */ - ADC_RESOLUTION_LEFT12BIT_gc = (0x03<<1), /* 12-bit left-adjusted result */ -} ADC_RESOLUTION_t; - -/* Current Limitation Mode */ -typedef enum ADC_CURRLIMIT_enum -{ - ADC_CURRLIMIT_NO_gc = (0x00<<5), /* No limit */ - ADC_CURRLIMIT_LOW_gc = (0x01<<5), /* Low current limit, max. sampling rate 1.5MSPS */ - ADC_CURRLIMIT_MED_gc = (0x02<<5), /* Medium current limit, max. sampling rate 1MSPS */ - ADC_CURRLIMIT_HIGH_gc = (0x03<<5), /* High current limit, max. sampling rate 0.5MSPS */ -} ADC_CURRLIMIT_t; - -/* Voltage reference selection */ -typedef enum ADC_REFSEL_enum -{ - ADC_REFSEL_INT1V_gc = (0x00<<4), /* Internal 1V */ - ADC_REFSEL_INTVCC_gc = (0x01<<4), /* Internal VCC / 1.6 */ - ADC_REFSEL_AREFA_gc = (0x02<<4), /* External reference on PORT A */ - ADC_REFSEL_AREFB_gc = (0x03<<4), /* External reference on PORT B */ - ADC_REFSEL_INTVCC2_gc = (0x04<<4), /* Internal VCC / 2 */ -} ADC_REFSEL_t; - -/* Channel sweep selection */ -typedef enum ADC_SWEEP_enum -{ - ADC_SWEEP_0_gc = (0x00<<6), /* ADC Channel 0 */ - ADC_SWEEP_01_gc = (0x01<<6), /* ADC Channel 0,1 */ - ADC_SWEEP_012_gc = (0x02<<6), /* ADC Channel 0,1,2 */ - ADC_SWEEP_0123_gc = (0x03<<6), /* ADC Channel 0,1,2,3 */ -} ADC_SWEEP_t; - -/* Event channel input selection */ -typedef enum ADC_EVSEL_enum -{ - ADC_EVSEL_0123_gc = (0x00<<3), /* Event Channel 0,1,2,3 */ - ADC_EVSEL_1234_gc = (0x01<<3), /* Event Channel 1,2,3,4 */ - ADC_EVSEL_2345_gc = (0x02<<3), /* Event Channel 2,3,4,5 */ - ADC_EVSEL_3456_gc = (0x03<<3), /* Event Channel 3,4,5,6 */ - ADC_EVSEL_4567_gc = (0x04<<3), /* Event Channel 4,5,6,7 */ - ADC_EVSEL_567_gc = (0x05<<3), /* Event Channel 5,6,7 */ - ADC_EVSEL_67_gc = (0x06<<3), /* Event Channel 6,7 */ - ADC_EVSEL_7_gc = (0x07<<3), /* Event Channel 7 */ -} ADC_EVSEL_t; - -/* Event action selection */ -typedef enum ADC_EVACT_enum -{ - ADC_EVACT_NONE_gc = (0x00<<0), /* No event action */ - ADC_EVACT_CH0_gc = (0x01<<0), /* First event triggers channel 0 */ - ADC_EVACT_CH01_gc = (0x02<<0), /* First two events trigger channel 0,1 */ - ADC_EVACT_CH012_gc = (0x03<<0), /* First three events trigger channel 0,1,2 */ - ADC_EVACT_CH0123_gc = (0x04<<0), /* Events trigger channel 0,1,2,3 */ - ADC_EVACT_SWEEP_gc = (0x05<<0), /* First event triggers sweep */ - ADC_EVACT_SYNCSWEEP_gc = (0x06<<0), /* The ADC is flushed and restarted for accurate timing */ -} ADC_EVACT_t; - -/* Interupt mode */ -typedef enum ADC_CH_INTMODE_enum -{ - ADC_CH_INTMODE_COMPLETE_gc = (0x00<<2), /* Interrupt on conversion complete */ - ADC_CH_INTMODE_BELOW_gc = (0x01<<2), /* Interrupt on result below compare value */ - ADC_CH_INTMODE_ABOVE_gc = (0x03<<2), /* Interrupt on result above compare value */ -} ADC_CH_INTMODE_t; - -/* Interrupt level */ -typedef enum ADC_CH_INTLVL_enum -{ - ADC_CH_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ - ADC_CH_INTLVL_LO_gc = (0x01<<0), /* Low level */ - ADC_CH_INTLVL_MED_gc = (0x02<<0), /* Medium level */ - ADC_CH_INTLVL_HI_gc = (0x03<<0), /* High level */ -} ADC_CH_INTLVL_t; - -/* DMA request selection */ -typedef enum ADC_DMASEL_enum -{ - ADC_DMASEL_OFF_gc = (0x00<<6), /* Combined DMA request OFF */ - ADC_DMASEL_CH01_gc = (0x01<<6), /* ADC Channel 0 or 1 */ - ADC_DMASEL_CH012_gc = (0x02<<6), /* ADC Channel 0 or 1 or 2 */ - ADC_DMASEL_CH0123_gc = (0x03<<6), /* ADC Channel 0 or 1 or 2 or 3 */ -} ADC_DMASEL_t; - -/* Clock prescaler */ -typedef enum ADC_PRESCALER_enum -{ - ADC_PRESCALER_DIV4_gc = (0x00<<0), /* Divide clock by 4 */ - ADC_PRESCALER_DIV8_gc = (0x01<<0), /* Divide clock by 8 */ - ADC_PRESCALER_DIV16_gc = (0x02<<0), /* Divide clock by 16 */ - ADC_PRESCALER_DIV32_gc = (0x03<<0), /* Divide clock by 32 */ - ADC_PRESCALER_DIV64_gc = (0x04<<0), /* Divide clock by 64 */ - ADC_PRESCALER_DIV128_gc = (0x05<<0), /* Divide clock by 128 */ - ADC_PRESCALER_DIV256_gc = (0x06<<0), /* Divide clock by 256 */ - ADC_PRESCALER_DIV512_gc = (0x07<<0), /* Divide clock by 512 */ -} ADC_PRESCALER_t; - - -/* --------------------------------------------------------------------------- -DAC - Digital/Analog Converter --------------------------------------------------------------------------- -*/ - -/* Digital-to-Analog Converter */ -typedef struct DAC_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t CTRLC; /* Control Register C */ - register8_t EVCTRL; /* Event Input Control */ - register8_t reserved_0x04; - register8_t STATUS; /* Status */ - register8_t reserved_0x06; - register8_t reserved_0x07; - register8_t CH0GAINCAL; /* Gain Calibration */ - register8_t CH0OFFSETCAL; /* Offset Calibration */ - register8_t CH1GAINCAL; /* Gain Calibration */ - register8_t CH1OFFSETCAL; /* Offset Calibration */ - register8_t reserved_0x0C; - register8_t reserved_0x0D; - register8_t reserved_0x0E; - register8_t reserved_0x0F; - register8_t reserved_0x10; - register8_t reserved_0x11; - register8_t reserved_0x12; - register8_t reserved_0x13; - register8_t reserved_0x14; - register8_t reserved_0x15; - register8_t reserved_0x16; - register8_t reserved_0x17; - _WORDREGISTER(CH0DATA); /* Channel 0 Data */ - _WORDREGISTER(CH1DATA); /* Channel 1 Data */ -} DAC_t; - -/* Output channel selection */ -typedef enum DAC_CHSEL_enum -{ - DAC_CHSEL_SINGLE_gc = (0x00<<5), /* Single channel operation (Channel 0 only) */ - DAC_CHSEL_SINGLE1_gc = (0x01<<5), /* Single channel operation (Channel 1 only) */ - DAC_CHSEL_DUAL_gc = (0x02<<5), /* Dual channel operation (Channel 0 and channel 1) */ -} DAC_CHSEL_t; - -/* Reference voltage selection */ -typedef enum DAC_REFSEL_enum -{ - DAC_REFSEL_INT1V_gc = (0x00<<3), /* Internal 1V */ - DAC_REFSEL_AVCC_gc = (0x01<<3), /* Analog supply voltage */ - DAC_REFSEL_AREFA_gc = (0x02<<3), /* External reference on AREF on PORTA */ - DAC_REFSEL_AREFB_gc = (0x03<<3), /* External reference on AREF on PORTB */ -} DAC_REFSEL_t; - -/* Event channel selection */ -typedef enum DAC_EVSEL_enum -{ - DAC_EVSEL_0_gc = (0x00<<0), /* Event Channel 0 */ - DAC_EVSEL_1_gc = (0x01<<0), /* Event Channel 1 */ - DAC_EVSEL_2_gc = (0x02<<0), /* Event Channel 2 */ - DAC_EVSEL_3_gc = (0x03<<0), /* Event Channel 3 */ - DAC_EVSEL_4_gc = (0x04<<0), /* Event Channel 4 */ - DAC_EVSEL_5_gc = (0x05<<0), /* Event Channel 5 */ - DAC_EVSEL_6_gc = (0x06<<0), /* Event Channel 6 */ - DAC_EVSEL_7_gc = (0x07<<0), /* Event Channel 7 */ -} DAC_EVSEL_t; - - -/* --------------------------------------------------------------------------- -AC - Analog Comparator --------------------------------------------------------------------------- -*/ - -/* Analog Comparator */ -typedef struct AC_struct -{ - register8_t AC0CTRL; /* Analog Comparator 0 Control */ - register8_t AC1CTRL; /* Analog Comparator 1 Control */ - register8_t AC0MUXCTRL; /* Analog Comparator 0 MUX Control */ - register8_t AC1MUXCTRL; /* Analog Comparator 1 MUX Control */ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t WINCTRL; /* Window Mode Control */ - register8_t STATUS; /* Status */ -} AC_t; - -/* Interrupt mode */ -typedef enum AC_INTMODE_enum -{ - AC_INTMODE_BOTHEDGES_gc = (0x00<<6), /* Interrupt on both edges */ - AC_INTMODE_FALLING_gc = (0x02<<6), /* Interrupt on falling edge */ - AC_INTMODE_RISING_gc = (0x03<<6), /* Interrupt on rising edge */ -} AC_INTMODE_t; - -/* Interrupt level */ -typedef enum AC_INTLVL_enum -{ - AC_INTLVL_OFF_gc = (0x00<<4), /* Interrupt disabled */ - AC_INTLVL_LO_gc = (0x01<<4), /* Low level */ - AC_INTLVL_MED_gc = (0x02<<4), /* Medium level */ - AC_INTLVL_HI_gc = (0x03<<4), /* High level */ -} AC_INTLVL_t; - -/* Hysteresis mode selection */ -typedef enum AC_HYSMODE_enum -{ - AC_HYSMODE_NO_gc = (0x00<<1), /* No hysteresis */ - AC_HYSMODE_SMALL_gc = (0x01<<1), /* Small hysteresis */ - AC_HYSMODE_LARGE_gc = (0x02<<1), /* Large hysteresis */ -} AC_HYSMODE_t; - -/* Positive input multiplexer selection */ -typedef enum AC_MUXPOS_enum -{ - AC_MUXPOS_PIN0_gc = (0x00<<3), /* Pin 0 */ - AC_MUXPOS_PIN1_gc = (0x01<<3), /* Pin 1 */ - AC_MUXPOS_PIN2_gc = (0x02<<3), /* Pin 2 */ - AC_MUXPOS_PIN3_gc = (0x03<<3), /* Pin 3 */ - AC_MUXPOS_PIN4_gc = (0x04<<3), /* Pin 4 */ - AC_MUXPOS_PIN5_gc = (0x05<<3), /* Pin 5 */ - AC_MUXPOS_PIN6_gc = (0x06<<3), /* Pin 6 */ - AC_MUXPOS_DAC_gc = (0x07<<3), /* DAC output */ -} AC_MUXPOS_t; - -/* Negative input multiplexer selection */ -typedef enum AC_MUXNEG_enum -{ - AC_MUXNEG_PIN0_gc = (0x00<<0), /* Pin 0 */ - AC_MUXNEG_PIN1_gc = (0x01<<0), /* Pin 1 */ - AC_MUXNEG_PIN3_gc = (0x02<<0), /* Pin 3 */ - AC_MUXNEG_PIN5_gc = (0x03<<0), /* Pin 5 */ - AC_MUXNEG_PIN7_gc = (0x04<<0), /* Pin 7 */ - AC_MUXNEG_DAC_gc = (0x05<<0), /* DAC output */ - AC_MUXNEG_BANDGAP_gc = (0x06<<0), /* Bandgap Reference */ - AC_MUXNEG_SCALER_gc = (0x07<<0), /* Internal voltage scaler */ -} AC_MUXNEG_t; - -/* Windows interrupt mode */ -typedef enum AC_WINTMODE_enum -{ - AC_WINTMODE_ABOVE_gc = (0x00<<2), /* Interrupt on above window */ - AC_WINTMODE_INSIDE_gc = (0x01<<2), /* Interrupt on inside window */ - AC_WINTMODE_BELOW_gc = (0x02<<2), /* Interrupt on below window */ - AC_WINTMODE_OUTSIDE_gc = (0x03<<2), /* Interrupt on outside window */ -} AC_WINTMODE_t; - -/* Window interrupt level */ -typedef enum AC_WINTLVL_enum -{ - AC_WINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ - AC_WINTLVL_LO_gc = (0x01<<0), /* Low priority */ - AC_WINTLVL_MED_gc = (0x02<<0), /* Medium priority */ - AC_WINTLVL_HI_gc = (0x03<<0), /* High priority */ -} AC_WINTLVL_t; - -/* Window mode state */ -typedef enum AC_WSTATE_enum -{ - AC_WSTATE_ABOVE_gc = (0x00<<6), /* Signal above window */ - AC_WSTATE_INSIDE_gc = (0x01<<6), /* Signal inside window */ - AC_WSTATE_BELOW_gc = (0x02<<6), /* Signal below window */ -} AC_WSTATE_t; - - -/* --------------------------------------------------------------------------- -RTC - Real-Time Counter --------------------------------------------------------------------------- -*/ - -/* Real-Time Counter */ -typedef struct RTC_struct -{ - register8_t CTRL; /* Control Register */ - register8_t STATUS; /* Status Register */ - register8_t INTCTRL; /* Interrupt Control Register */ - register8_t INTFLAGS; /* Interrupt Flags */ - register8_t TEMP; /* Temporary register */ - register8_t reserved_0x05; - register8_t reserved_0x06; - register8_t reserved_0x07; - _WORDREGISTER(CNT); /* Count Register */ - _WORDREGISTER(PER); /* Period Register */ - _WORDREGISTER(COMP); /* Compare Register */ -} RTC_t; - -/* Prescaler Factor */ -typedef enum RTC_PRESCALER_enum -{ - RTC_PRESCALER_OFF_gc = (0x00<<0), /* RTC Off */ - RTC_PRESCALER_DIV1_gc = (0x01<<0), /* RTC Clock */ - RTC_PRESCALER_DIV2_gc = (0x02<<0), /* RTC Clock / 2 */ - RTC_PRESCALER_DIV8_gc = (0x03<<0), /* RTC Clock / 8 */ - RTC_PRESCALER_DIV16_gc = (0x04<<0), /* RTC Clock / 16 */ - RTC_PRESCALER_DIV64_gc = (0x05<<0), /* RTC Clock / 64 */ - RTC_PRESCALER_DIV256_gc = (0x06<<0), /* RTC Clock / 256 */ - RTC_PRESCALER_DIV1024_gc = (0x07<<0), /* RTC Clock / 1024 */ -} RTC_PRESCALER_t; - -/* Compare Interrupt level */ -typedef enum RTC_COMPINTLVL_enum -{ - RTC_COMPINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ - RTC_COMPINTLVL_LO_gc = (0x01<<2), /* Low Level */ - RTC_COMPINTLVL_MED_gc = (0x02<<2), /* Medium Level */ - RTC_COMPINTLVL_HI_gc = (0x03<<2), /* High Level */ -} RTC_COMPINTLVL_t; - -/* Overflow Interrupt level */ -typedef enum RTC_OVFINTLVL_enum -{ - RTC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - RTC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ - RTC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ - RTC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ -} RTC_OVFINTLVL_t; - - -/* --------------------------------------------------------------------------- -TWI - Two-Wire Interface --------------------------------------------------------------------------- -*/ - -/* */ -typedef struct TWI_MASTER_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t CTRLC; /* Control Register C */ - register8_t STATUS; /* Status Register */ - register8_t BAUD; /* Baurd Rate Control Register */ - register8_t ADDR; /* Address Register */ - register8_t DATA; /* Data Register */ -} TWI_MASTER_t; - - -/* */ -typedef struct TWI_SLAVE_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t STATUS; /* Status Register */ - register8_t ADDR; /* Address Register */ - register8_t DATA; /* Data Register */ - register8_t ADDRMASK; /* Address Mask Register */ -} TWI_SLAVE_t; - - -/* Two-Wire Interface */ -typedef struct TWI_struct -{ - register8_t CTRL; /* TWI Common Control Register */ - TWI_MASTER_t MASTER; /* TWI master module */ - TWI_SLAVE_t SLAVE; /* TWI slave module */ -} TWI_t; - -/* SDA Hold Time */ -typedef enum TWI_SDAHOLD_enum -{ - TWI_SDAHOLD_OFF_gc = (0x00<<1), /* SDA Hold Time off */ - TWI_SDAHOLD_50NS_gc = (0x01<<1), /* SDA Hold Time 50 ns */ - TWI_SDAHOLD_300NS_gc = (0x02<<1), /* SDA Hold Time 300 ns */ - TWI_SDAHOLD_400NS_gc = (0x03<<1), /* SDA Hold Time 400 ns */ -} TWI_SDAHOLD_t; - -/* Master Interrupt Level */ -typedef enum TWI_MASTER_INTLVL_enum -{ - TWI_MASTER_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ - TWI_MASTER_INTLVL_LO_gc = (0x01<<6), /* Low Level */ - TWI_MASTER_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ - TWI_MASTER_INTLVL_HI_gc = (0x03<<6), /* High Level */ -} TWI_MASTER_INTLVL_t; - -/* Inactive Timeout */ -typedef enum TWI_MASTER_TIMEOUT_enum -{ - TWI_MASTER_TIMEOUT_DISABLED_gc = (0x00<<2), /* Bus Timeout Disabled */ - TWI_MASTER_TIMEOUT_50US_gc = (0x01<<2), /* 50 Microseconds */ - TWI_MASTER_TIMEOUT_100US_gc = (0x02<<2), /* 100 Microseconds */ - TWI_MASTER_TIMEOUT_200US_gc = (0x03<<2), /* 200 Microseconds */ -} TWI_MASTER_TIMEOUT_t; - -/* Master Command */ -typedef enum TWI_MASTER_CMD_enum -{ - TWI_MASTER_CMD_NOACT_gc = (0x00<<0), /* No Action */ - TWI_MASTER_CMD_REPSTART_gc = (0x01<<0), /* Issue Repeated Start Condition */ - TWI_MASTER_CMD_RECVTRANS_gc = (0x02<<0), /* Receive or Transmit Data */ - TWI_MASTER_CMD_STOP_gc = (0x03<<0), /* Issue Stop Condition */ -} TWI_MASTER_CMD_t; - -/* Master Bus State */ -typedef enum TWI_MASTER_BUSSTATE_enum -{ - TWI_MASTER_BUSSTATE_UNKNOWN_gc = (0x00<<0), /* Unknown Bus State */ - TWI_MASTER_BUSSTATE_IDLE_gc = (0x01<<0), /* Bus is Idle */ - TWI_MASTER_BUSSTATE_OWNER_gc = (0x02<<0), /* This Module Controls The Bus */ - TWI_MASTER_BUSSTATE_BUSY_gc = (0x03<<0), /* The Bus is Busy */ -} TWI_MASTER_BUSSTATE_t; - -/* Slave Interrupt Level */ -typedef enum TWI_SLAVE_INTLVL_enum -{ - TWI_SLAVE_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ - TWI_SLAVE_INTLVL_LO_gc = (0x01<<6), /* Low Level */ - TWI_SLAVE_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ - TWI_SLAVE_INTLVL_HI_gc = (0x03<<6), /* High Level */ -} TWI_SLAVE_INTLVL_t; - -/* Slave Command */ -typedef enum TWI_SLAVE_CMD_enum -{ - TWI_SLAVE_CMD_NOACT_gc = (0x00<<0), /* No Action */ - TWI_SLAVE_CMD_COMPTRANS_gc = (0x02<<0), /* Used To Complete a Transaction */ - TWI_SLAVE_CMD_RESPONSE_gc = (0x03<<0), /* Used in Response to Address/Data Interrupt */ -} TWI_SLAVE_CMD_t; - - -/* --------------------------------------------------------------------------- -USB - USB --------------------------------------------------------------------------- -*/ - -/* USB Endpoint */ -typedef struct USB_EP_struct -{ - register8_t STATUS; /* Endpoint Status */ - register8_t CTRL; /* Endpoint Control */ - _WORDREGISTER(CNT); /* USB Endpoint Counter */ - _WORDREGISTER(DATAPTR); /* Data Pointer */ - _WORDREGISTER(AUXDATA); /* Auxiliary Data */ -} USB_EP_t; - - -/* Universal Serial Bus */ -typedef struct USB_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t STATUS; /* Status Register */ - register8_t ADDR; /* Address Register */ - register8_t FIFOWP; /* FIFO Write Pointer Register */ - register8_t FIFORP; /* FIFO Read Pointer Register */ - _WORDREGISTER(EPPTR); /* Endpoint Configuration Table Pointer */ - register8_t INTCTRLA; /* Interrupt Control Register A */ - register8_t INTCTRLB; /* Interrupt Control Register B */ - register8_t INTFLAGSACLR; /* Clear Interrupt Flag Register A */ - register8_t INTFLAGSASET; /* Set Interrupt Flag Register A */ - register8_t INTFLAGSBCLR; /* Clear Interrupt Flag Register B */ - register8_t INTFLAGSBSET; /* Set Interrupt Flag Register B */ - register8_t reserved_0x0E; - register8_t reserved_0x0F; - register8_t reserved_0x10; - register8_t reserved_0x11; - register8_t reserved_0x12; - register8_t reserved_0x13; - register8_t reserved_0x14; - register8_t reserved_0x15; - register8_t reserved_0x16; - register8_t reserved_0x17; - register8_t reserved_0x18; - register8_t reserved_0x19; - register8_t reserved_0x1A; - register8_t reserved_0x1B; - register8_t reserved_0x1C; - register8_t reserved_0x1D; - register8_t reserved_0x1E; - register8_t reserved_0x1F; - register8_t reserved_0x20; - register8_t reserved_0x21; - register8_t reserved_0x22; - register8_t reserved_0x23; - register8_t reserved_0x24; - register8_t reserved_0x25; - register8_t reserved_0x26; - register8_t reserved_0x27; - register8_t reserved_0x28; - register8_t reserved_0x29; - register8_t reserved_0x2A; - register8_t reserved_0x2B; - register8_t reserved_0x2C; - register8_t reserved_0x2D; - register8_t reserved_0x2E; - register8_t reserved_0x2F; - register8_t reserved_0x30; - register8_t reserved_0x31; - register8_t reserved_0x32; - register8_t reserved_0x33; - register8_t reserved_0x34; - register8_t reserved_0x35; - register8_t reserved_0x36; - register8_t reserved_0x37; - register8_t reserved_0x38; - register8_t reserved_0x39; - register8_t CAL0; /* Calibration Byte 0 */ - register8_t CAL1; /* Calibration Byte 1 */ -} USB_t; - - -/* USB Endpoint Table */ -typedef struct USB_EP_TABLE_struct -{ - USB_EP_t EP0OUT; /* Endpoint 0 */ - USB_EP_t EP0IN; /* Endpoint 0 */ - USB_EP_t EP1OUT; /* Endpoint 1 */ - USB_EP_t EP1IN; /* Endpoint 1 */ - USB_EP_t EP2OUT; /* Endpoint 2 */ - USB_EP_t EP2IN; /* Endpoint 2 */ - USB_EP_t EP3OUT; /* Endpoint 3 */ - USB_EP_t EP3IN; /* Endpoint 3 */ - USB_EP_t EP4OUT; /* Endpoint 4 */ - USB_EP_t EP4IN; /* Endpoint 4 */ - USB_EP_t EP5OUT; /* Endpoint 5 */ - USB_EP_t EP5IN; /* Endpoint 5 */ - USB_EP_t EP6OUT; /* Endpoint 6 */ - USB_EP_t EP6IN; /* Endpoint 6 */ - USB_EP_t EP7OUT; /* Endpoint 7 */ - USB_EP_t EP7IN; /* Endpoint 7 */ - USB_EP_t EP8OUT; /* Endpoint 8 */ - USB_EP_t EP8IN; /* Endpoint 8 */ - USB_EP_t EP9OUT; /* Endpoint 9 */ - USB_EP_t EP9IN; /* Endpoint 9 */ - USB_EP_t EP10OUT; /* Endpoint 10 */ - USB_EP_t EP10IN; /* Endpoint 10 */ - USB_EP_t EP11OUT; /* Endpoint 11 */ - USB_EP_t EP11IN; /* Endpoint 11 */ - USB_EP_t EP12OUT; /* Endpoint 12 */ - USB_EP_t EP12IN; /* Endpoint 12 */ - USB_EP_t EP13OUT; /* Endpoint 13 */ - USB_EP_t EP13IN; /* Endpoint 13 */ - USB_EP_t EP14OUT; /* Endpoint 14 */ - USB_EP_t EP14IN; /* Endpoint 14 */ - USB_EP_t EP15OUT; /* Endpoint 15 */ - USB_EP_t EP15IN; /* Endpoint 15 */ - register8_t reserved_0x100; - register8_t reserved_0x101; - register8_t reserved_0x102; - register8_t reserved_0x103; - register8_t reserved_0x104; - register8_t reserved_0x105; - register8_t reserved_0x106; - register8_t reserved_0x107; - register8_t reserved_0x108; - register8_t reserved_0x109; - register8_t reserved_0x10A; - register8_t reserved_0x10B; - register8_t reserved_0x10C; - register8_t reserved_0x10D; - register8_t reserved_0x10E; - register8_t reserved_0x10F; - register8_t FRAMENUML; /* Frame Number Low Byte */ - register8_t FRAMENUMH; /* Frame Number High Byte */ -} USB_EP_TABLE_t; - -/* Interrupt level */ -typedef enum USB_INTLVL_enum -{ - USB_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ - USB_INTLVL_LO_gc = (0x01<<0), /* Low level */ - USB_INTLVL_MED_gc = (0x02<<0), /* Medium level */ - USB_INTLVL_HI_gc = (0x03<<0), /* High level */ -} USB_INTLVL_t; - -/* USB Endpoint Type */ -typedef enum USB_EP_TYPE_enum -{ - USB_EP_TYPE_DISABLE_gc = (0x00<<6), /* Endpoint Disabled */ - USB_EP_TYPE_CONTROL_gc = (0x01<<6), /* Control */ - USB_EP_TYPE_BULK_gc = (0x02<<6), /* Bulk/Interrupt */ - USB_EP_TYPE_ISOCHRONOUS_gc = (0x03<<6), /* Isochronous */ -} USB_EP_TYPE_t; - -/* USB Endpoint Buffersize */ -typedef enum USB_EP_BUFSIZE_enum -{ - USB_EP_BUFSIZE_8_gc = (0x00<<0), /* 8 bytes buffer size */ - USB_EP_BUFSIZE_16_gc = (0x01<<0), /* 16 bytes buffer size */ - USB_EP_BUFSIZE_32_gc = (0x02<<0), /* 32 bytes buffer size */ - USB_EP_BUFSIZE_64_gc = (0x03<<0), /* 64 bytes buffer size */ - USB_EP_BUFSIZE_128_gc = (0x04<<0), /* 128 bytes buffer size */ - USB_EP_BUFSIZE_256_gc = (0x05<<0), /* 256 bytes buffer size */ - USB_EP_BUFSIZE_512_gc = (0x06<<0), /* 512 bytes buffer size */ - USB_EP_BUFSIZE_1023_gc = (0x07<<0), /* 1023 bytes buffer size */ -} USB_EP_BUFSIZE_t; - - -/* --------------------------------------------------------------------------- -PORT - I/O Port Configuration --------------------------------------------------------------------------- -*/ - -/* I/O Ports */ -typedef struct PORT_struct -{ - register8_t DIR; /* I/O Port Data Direction */ - register8_t DIRSET; /* I/O Port Data Direction Set */ - register8_t DIRCLR; /* I/O Port Data Direction Clear */ - register8_t DIRTGL; /* I/O Port Data Direction Toggle */ - register8_t OUT; /* I/O Port Output */ - register8_t OUTSET; /* I/O Port Output Set */ - register8_t OUTCLR; /* I/O Port Output Clear */ - register8_t OUTTGL; /* I/O Port Output Toggle */ - register8_t IN; /* I/O port Input */ - register8_t INTCTRL; /* Interrupt Control Register */ - register8_t INT0MASK; /* Port Interrupt 0 Mask */ - register8_t INT1MASK; /* Port Interrupt 1 Mask */ - register8_t INTFLAGS; /* Interrupt Flag Register */ - register8_t reserved_0x0D; - register8_t REMAP; /* I/O Port Pin Remap Register */ - register8_t reserved_0x0F; - register8_t PIN0CTRL; /* Pin 0 Control Register */ - register8_t PIN1CTRL; /* Pin 1 Control Register */ - register8_t PIN2CTRL; /* Pin 2 Control Register */ - register8_t PIN3CTRL; /* Pin 3 Control Register */ - register8_t PIN4CTRL; /* Pin 4 Control Register */ - register8_t PIN5CTRL; /* Pin 5 Control Register */ - register8_t PIN6CTRL; /* Pin 6 Control Register */ - register8_t PIN7CTRL; /* Pin 7 Control Register */ -} PORT_t; - -/* Port Interrupt 0 Level */ -typedef enum PORT_INT0LVL_enum -{ - PORT_INT0LVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - PORT_INT0LVL_LO_gc = (0x01<<0), /* Low Level */ - PORT_INT0LVL_MED_gc = (0x02<<0), /* Medium Level */ - PORT_INT0LVL_HI_gc = (0x03<<0), /* High Level */ -} PORT_INT0LVL_t; - -/* Port Interrupt 1 Level */ -typedef enum PORT_INT1LVL_enum -{ - PORT_INT1LVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ - PORT_INT1LVL_LO_gc = (0x01<<2), /* Low Level */ - PORT_INT1LVL_MED_gc = (0x02<<2), /* Medium Level */ - PORT_INT1LVL_HI_gc = (0x03<<2), /* High Level */ -} PORT_INT1LVL_t; - -/* Output/Pull Configuration */ -typedef enum PORT_OPC_enum -{ - PORT_OPC_TOTEM_gc = (0x00<<3), /* Totempole */ - PORT_OPC_BUSKEEPER_gc = (0x01<<3), /* Totempole w/ Bus keeper on Input and Output */ - PORT_OPC_PULLDOWN_gc = (0x02<<3), /* Totempole w/ Pull-down on Input */ - PORT_OPC_PULLUP_gc = (0x03<<3), /* Totempole w/ Pull-up on Input */ - PORT_OPC_WIREDOR_gc = (0x04<<3), /* Wired OR */ - PORT_OPC_WIREDAND_gc = (0x05<<3), /* Wired AND */ - PORT_OPC_WIREDORPULL_gc = (0x06<<3), /* Wired OR w/ Pull-down */ - PORT_OPC_WIREDANDPULL_gc = (0x07<<3), /* Wired AND w/ Pull-up */ -} PORT_OPC_t; - -/* Input/Sense Configuration */ -typedef enum PORT_ISC_enum -{ - PORT_ISC_BOTHEDGES_gc = (0x00<<0), /* Sense Both Edges */ - PORT_ISC_RISING_gc = (0x01<<0), /* Sense Rising Edge */ - PORT_ISC_FALLING_gc = (0x02<<0), /* Sense Falling Edge */ - PORT_ISC_LEVEL_gc = (0x03<<0), /* Sense Level (Transparent For Events) */ - PORT_ISC_INPUT_DISABLE_gc = (0x07<<0), /* Disable Digital Input Buffer */ -} PORT_ISC_t; - - -/* --------------------------------------------------------------------------- -TC - 16-bit Timer/Counter With PWM --------------------------------------------------------------------------- -*/ - -/* 16-bit Timer/Counter 0 */ -typedef struct TC0_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t CTRLC; /* Control register C */ - register8_t CTRLD; /* Control Register D */ - register8_t CTRLE; /* Control Register E */ - register8_t reserved_0x05; - register8_t INTCTRLA; /* Interrupt Control Register A */ - register8_t INTCTRLB; /* Interrupt Control Register B */ - register8_t CTRLFCLR; /* Control Register F Clear */ - register8_t CTRLFSET; /* Control Register F Set */ - register8_t CTRLGCLR; /* Control Register G Clear */ - register8_t CTRLGSET; /* Control Register G Set */ - register8_t INTFLAGS; /* Interrupt Flag Register */ - register8_t reserved_0x0D; - register8_t reserved_0x0E; - register8_t TEMP; /* Temporary Register For 16-bit Access */ - register8_t reserved_0x10; - register8_t reserved_0x11; - register8_t reserved_0x12; - register8_t reserved_0x13; - register8_t reserved_0x14; - register8_t reserved_0x15; - register8_t reserved_0x16; - register8_t reserved_0x17; - register8_t reserved_0x18; - register8_t reserved_0x19; - register8_t reserved_0x1A; - register8_t reserved_0x1B; - register8_t reserved_0x1C; - register8_t reserved_0x1D; - register8_t reserved_0x1E; - register8_t reserved_0x1F; - _WORDREGISTER(CNT); /* Count */ - register8_t reserved_0x22; - register8_t reserved_0x23; - register8_t reserved_0x24; - register8_t reserved_0x25; - _WORDREGISTER(PER); /* Period */ - _WORDREGISTER(CCA); /* Compare or Capture A */ - _WORDREGISTER(CCB); /* Compare or Capture B */ - _WORDREGISTER(CCC); /* Compare or Capture C */ - _WORDREGISTER(CCD); /* Compare or Capture D */ - register8_t reserved_0x30; - register8_t reserved_0x31; - register8_t reserved_0x32; - register8_t reserved_0x33; - register8_t reserved_0x34; - register8_t reserved_0x35; - _WORDREGISTER(PERBUF); /* Period Buffer */ - _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ - _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ - _WORDREGISTER(CCCBUF); /* Compare Or Capture C Buffer */ - _WORDREGISTER(CCDBUF); /* Compare Or Capture D Buffer */ -} TC0_t; - - -/* 16-bit Timer/Counter 1 */ -typedef struct TC1_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t CTRLC; /* Control register C */ - register8_t CTRLD; /* Control Register D */ - register8_t CTRLE; /* Control Register E */ - register8_t reserved_0x05; - register8_t INTCTRLA; /* Interrupt Control Register A */ - register8_t INTCTRLB; /* Interrupt Control Register B */ - register8_t CTRLFCLR; /* Control Register F Clear */ - register8_t CTRLFSET; /* Control Register F Set */ - register8_t CTRLGCLR; /* Control Register G Clear */ - register8_t CTRLGSET; /* Control Register G Set */ - register8_t INTFLAGS; /* Interrupt Flag Register */ - register8_t reserved_0x0D; - register8_t reserved_0x0E; - register8_t TEMP; /* Temporary Register For 16-bit Access */ - register8_t reserved_0x10; - register8_t reserved_0x11; - register8_t reserved_0x12; - register8_t reserved_0x13; - register8_t reserved_0x14; - register8_t reserved_0x15; - register8_t reserved_0x16; - register8_t reserved_0x17; - register8_t reserved_0x18; - register8_t reserved_0x19; - register8_t reserved_0x1A; - register8_t reserved_0x1B; - register8_t reserved_0x1C; - register8_t reserved_0x1D; - register8_t reserved_0x1E; - register8_t reserved_0x1F; - _WORDREGISTER(CNT); /* Count */ - register8_t reserved_0x22; - register8_t reserved_0x23; - register8_t reserved_0x24; - register8_t reserved_0x25; - _WORDREGISTER(PER); /* Period */ - _WORDREGISTER(CCA); /* Compare or Capture A */ - _WORDREGISTER(CCB); /* Compare or Capture B */ - register8_t reserved_0x2C; - register8_t reserved_0x2D; - register8_t reserved_0x2E; - register8_t reserved_0x2F; - register8_t reserved_0x30; - register8_t reserved_0x31; - register8_t reserved_0x32; - register8_t reserved_0x33; - register8_t reserved_0x34; - register8_t reserved_0x35; - _WORDREGISTER(PERBUF); /* Period Buffer */ - _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ - _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ -} TC1_t; - -/* Clock Selection */ -typedef enum TC_CLKSEL_enum -{ - TC_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */ - TC_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */ - TC_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */ - TC_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */ - TC_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */ - TC_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */ - TC_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */ - TC_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */ - TC_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */ - TC_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */ - TC_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */ - TC_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */ - TC_CLKSEL_EVCH4_gc = (0x0C<<0), /* Event Channel 4 */ - TC_CLKSEL_EVCH5_gc = (0x0D<<0), /* Event Channel 5 */ - TC_CLKSEL_EVCH6_gc = (0x0E<<0), /* Event Channel 6 */ - TC_CLKSEL_EVCH7_gc = (0x0F<<0), /* Event Channel 7 */ -} TC_CLKSEL_t; - -/* Waveform Generation Mode */ -typedef enum TC_WGMODE_enum -{ - TC_WGMODE_NORMAL_gc = (0x00<<0), /* Normal Mode */ - TC_WGMODE_FRQ_gc = (0x01<<0), /* Frequency Generation Mode */ - TC_WGMODE_SINGLESLOPE_gc = (0x03<<0), /* Single Slope */ - TC_WGMODE_SS_gc = (0x03<<0), /* Single Slope */ - TC_WGMODE_DSTOP_gc = (0x05<<0), /* Dual Slope, Update on TOP */ - TC_WGMODE_DS_T_gc = (0x05<<0), /* Dual Slope, Update on TOP */ - TC_WGMODE_DSBOTH_gc = (0x06<<0), /* Dual Slope, Update on both TOP and BOTTOM */ - TC_WGMODE_DS_TB_gc = (0x06<<0), /* Dual Slope, Update on both TOP and BOTTOM */ - TC_WGMODE_DSBOTTOM_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */ - TC_WGMODE_DS_B_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */ -} TC_WGMODE_t; - -/* Byte Mode */ -typedef enum TC_BYTEM_enum -{ - TC_BYTEM_NORMAL_gc = (0x00<<0), /* 16-bit mode */ - TC_BYTEM_BYTEMODE_gc = (0x01<<0), /* Timer/Counter operating in byte mode only */ - TC_BYTEM_SPLITMODE_gc = (0x02<<0), /* Timer/Counter split into two 8-bit Counters (TC2) */ -} TC_BYTEM_t; - -/* Event Action */ -typedef enum TC_EVACT_enum -{ - TC_EVACT_OFF_gc = (0x00<<5), /* No Event Action */ - TC_EVACT_CAPT_gc = (0x01<<5), /* Input Capture */ - TC_EVACT_UPDOWN_gc = (0x02<<5), /* Externally Controlled Up/Down Count */ - TC_EVACT_QDEC_gc = (0x03<<5), /* Quadrature Decode */ - TC_EVACT_RESTART_gc = (0x04<<5), /* Restart */ - TC_EVACT_FRQ_gc = (0x05<<5), /* Frequency Capture */ - TC_EVACT_PW_gc = (0x06<<5), /* Pulse-width Capture */ -} TC_EVACT_t; - -/* Event Selection */ -typedef enum TC_EVSEL_enum -{ - TC_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ - TC_EVSEL_CH0_gc = (0x08<<0), /* Event Channel 0 */ - TC_EVSEL_CH1_gc = (0x09<<0), /* Event Channel 1 */ - TC_EVSEL_CH2_gc = (0x0A<<0), /* Event Channel 2 */ - TC_EVSEL_CH3_gc = (0x0B<<0), /* Event Channel 3 */ - TC_EVSEL_CH4_gc = (0x0C<<0), /* Event Channel 4 */ - TC_EVSEL_CH5_gc = (0x0D<<0), /* Event Channel 5 */ - TC_EVSEL_CH6_gc = (0x0E<<0), /* Event Channel 6 */ - TC_EVSEL_CH7_gc = (0x0F<<0), /* Event Channel 7 */ -} TC_EVSEL_t; - -/* Error Interrupt Level */ -typedef enum TC_ERRINTLVL_enum -{ - TC_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ - TC_ERRINTLVL_LO_gc = (0x01<<2), /* Low Level */ - TC_ERRINTLVL_MED_gc = (0x02<<2), /* Medium Level */ - TC_ERRINTLVL_HI_gc = (0x03<<2), /* High Level */ -} TC_ERRINTLVL_t; - -/* Overflow Interrupt Level */ -typedef enum TC_OVFINTLVL_enum -{ - TC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - TC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ - TC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ - TC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ -} TC_OVFINTLVL_t; - -/* Compare or Capture D Interrupt Level */ -typedef enum TC_CCDINTLVL_enum -{ - TC_CCDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ - TC_CCDINTLVL_LO_gc = (0x01<<6), /* Low Level */ - TC_CCDINTLVL_MED_gc = (0x02<<6), /* Medium Level */ - TC_CCDINTLVL_HI_gc = (0x03<<6), /* High Level */ -} TC_CCDINTLVL_t; - -/* Compare or Capture C Interrupt Level */ -typedef enum TC_CCCINTLVL_enum -{ - TC_CCCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ - TC_CCCINTLVL_LO_gc = (0x01<<4), /* Low Level */ - TC_CCCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ - TC_CCCINTLVL_HI_gc = (0x03<<4), /* High Level */ -} TC_CCCINTLVL_t; - -/* Compare or Capture B Interrupt Level */ -typedef enum TC_CCBINTLVL_enum -{ - TC_CCBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ - TC_CCBINTLVL_LO_gc = (0x01<<2), /* Low Level */ - TC_CCBINTLVL_MED_gc = (0x02<<2), /* Medium Level */ - TC_CCBINTLVL_HI_gc = (0x03<<2), /* High Level */ -} TC_CCBINTLVL_t; - -/* Compare or Capture A Interrupt Level */ -typedef enum TC_CCAINTLVL_enum -{ - TC_CCAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - TC_CCAINTLVL_LO_gc = (0x01<<0), /* Low Level */ - TC_CCAINTLVL_MED_gc = (0x02<<0), /* Medium Level */ - TC_CCAINTLVL_HI_gc = (0x03<<0), /* High Level */ -} TC_CCAINTLVL_t; - -/* Timer/Counter Command */ -typedef enum TC_CMD_enum -{ - TC_CMD_NONE_gc = (0x00<<2), /* No Command */ - TC_CMD_UPDATE_gc = (0x01<<2), /* Force Update */ - TC_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ - TC_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ -} TC_CMD_t; - - -/* --------------------------------------------------------------------------- -TC2 - 16-bit Timer/Counter type 2 --------------------------------------------------------------------------- -*/ - -/* 16-bit Timer/Counter type 2 */ -typedef struct TC2_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t CTRLC; /* Control register C */ - register8_t reserved_0x03; - register8_t CTRLE; /* Control Register E */ - register8_t reserved_0x05; - register8_t INTCTRLA; /* Interrupt Control Register A */ - register8_t INTCTRLB; /* Interrupt Control Register B */ - register8_t reserved_0x08; - register8_t CTRLF; /* Control Register F */ - register8_t reserved_0x0A; - register8_t reserved_0x0B; - register8_t INTFLAGS; /* Interrupt Flag Register */ - register8_t reserved_0x0D; - register8_t reserved_0x0E; - register8_t reserved_0x0F; - register8_t reserved_0x10; - register8_t reserved_0x11; - register8_t reserved_0x12; - register8_t reserved_0x13; - register8_t reserved_0x14; - register8_t reserved_0x15; - register8_t reserved_0x16; - register8_t reserved_0x17; - register8_t reserved_0x18; - register8_t reserved_0x19; - register8_t reserved_0x1A; - register8_t reserved_0x1B; - register8_t reserved_0x1C; - register8_t reserved_0x1D; - register8_t reserved_0x1E; - register8_t reserved_0x1F; - register8_t LCNT; /* Low Byte Count */ - register8_t HCNT; /* High Byte Count */ - register8_t reserved_0x22; - register8_t reserved_0x23; - register8_t reserved_0x24; - register8_t reserved_0x25; - register8_t LPER; /* Low Byte Period */ - register8_t HPER; /* High Byte Period */ - register8_t LCMPA; /* Low Byte Compare A */ - register8_t HCMPA; /* High Byte Compare A */ - register8_t LCMPB; /* Low Byte Compare B */ - register8_t HCMPB; /* High Byte Compare B */ - register8_t LCMPC; /* Low Byte Compare C */ - register8_t HCMPC; /* High Byte Compare C */ - register8_t LCMPD; /* Low Byte Compare D */ - register8_t HCMPD; /* High Byte Compare D */ -} TC2_t; - -/* Clock Selection */ -typedef enum TC2_CLKSEL_enum -{ - TC2_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */ - TC2_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */ - TC2_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */ - TC2_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */ - TC2_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */ - TC2_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */ - TC2_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */ - TC2_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */ - TC2_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */ - TC2_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */ - TC2_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */ - TC2_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */ - TC2_CLKSEL_EVCH4_gc = (0x0C<<0), /* Event Channel 4 */ - TC2_CLKSEL_EVCH5_gc = (0x0D<<0), /* Event Channel 5 */ - TC2_CLKSEL_EVCH6_gc = (0x0E<<0), /* Event Channel 6 */ - TC2_CLKSEL_EVCH7_gc = (0x0F<<0), /* Event Channel 7 */ -} TC2_CLKSEL_t; - -/* Byte Mode */ -typedef enum TC2_BYTEM_enum -{ - TC2_BYTEM_NORMAL_gc = (0x00<<0), /* 16-bit mode */ - TC2_BYTEM_BYTEMODE_gc = (0x01<<0), /* Timer/Counter operating in byte mode only (TC2) */ - TC2_BYTEM_SPLITMODE_gc = (0x02<<0), /* Timer/Counter split into two 8-bit Counters */ -} TC2_BYTEM_t; - -/* High Byte Underflow Interrupt Level */ -typedef enum TC2_HUNFINTLVL_enum -{ - TC2_HUNFINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ - TC2_HUNFINTLVL_LO_gc = (0x01<<2), /* Low Level */ - TC2_HUNFINTLVL_MED_gc = (0x02<<2), /* Medium Level */ - TC2_HUNFINTLVL_HI_gc = (0x03<<2), /* High Level */ -} TC2_HUNFINTLVL_t; - -/* Low Byte Underflow Interrupt Level */ -typedef enum TC2_LUNFINTLVL_enum -{ - TC2_LUNFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - TC2_LUNFINTLVL_LO_gc = (0x01<<0), /* Low Level */ - TC2_LUNFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ - TC2_LUNFINTLVL_HI_gc = (0x03<<0), /* High Level */ -} TC2_LUNFINTLVL_t; - -/* Low Byte Compare D Interrupt Level */ -typedef enum TC2_LCMPDINTLVL_enum -{ - TC2_LCMPDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ - TC2_LCMPDINTLVL_LO_gc = (0x01<<6), /* Low Level */ - TC2_LCMPDINTLVL_MED_gc = (0x02<<6), /* Medium Level */ - TC2_LCMPDINTLVL_HI_gc = (0x03<<6), /* High Level */ -} TC2_LCMPDINTLVL_t; - -/* Low Byte Compare C Interrupt Level */ -typedef enum TC2_LCMPCINTLVL_enum -{ - TC2_LCMPCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ - TC2_LCMPCINTLVL_LO_gc = (0x01<<4), /* Low Level */ - TC2_LCMPCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ - TC2_LCMPCINTLVL_HI_gc = (0x03<<4), /* High Level */ -} TC2_LCMPCINTLVL_t; - -/* Low Byte Compare B Interrupt Level */ -typedef enum TC2_LCMPBINTLVL_enum -{ - TC2_LCMPBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ - TC2_LCMPBINTLVL_LO_gc = (0x01<<2), /* Low Level */ - TC2_LCMPBINTLVL_MED_gc = (0x02<<2), /* Medium Level */ - TC2_LCMPBINTLVL_HI_gc = (0x03<<2), /* High Level */ -} TC2_LCMPBINTLVL_t; - -/* Low Byte Compare A Interrupt Level */ -typedef enum TC2_LCMPAINTLVL_enum -{ - TC2_LCMPAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - TC2_LCMPAINTLVL_LO_gc = (0x01<<0), /* Low Level */ - TC2_LCMPAINTLVL_MED_gc = (0x02<<0), /* Medium Level */ - TC2_LCMPAINTLVL_HI_gc = (0x03<<0), /* High Level */ -} TC2_LCMPAINTLVL_t; - -/* Timer/Counter Command */ -typedef enum TC2_CMD_enum -{ - TC2_CMD_NONE_gc = (0x00<<2), /* No Command */ - TC2_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ - TC2_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ -} TC2_CMD_t; - -/* Timer/Counter Command */ -typedef enum TC2_CMDEN_enum -{ - TC2_CMDEN_LOW_gc = (0x01<<0), /* Low Byte Timer/Counter */ - TC2_CMDEN_HIGH_gc = (0x02<<0), /* High Byte Timer/Counter */ - TC2_CMDEN_BOTH_gc = (0x03<<0), /* Both Low Byte and High Byte Timer/Counters */ -} TC2_CMDEN_t; - - -/* --------------------------------------------------------------------------- -AWEX - Timer/Counter Advanced Waveform Extension --------------------------------------------------------------------------- -*/ - -/* Advanced Waveform Extension */ -typedef struct AWEX_struct -{ - register8_t CTRL; /* Control Register */ - register8_t reserved_0x01; - register8_t FDEMASK; /* Fault Detection Event Mask */ - register8_t FDCTRL; /* Fault Detection Control Register */ - register8_t STATUS; /* Status Register */ - register8_t STATUSSET; /* Status Set Register */ - register8_t DTBOTH; /* Dead Time Both Sides */ - register8_t DTBOTHBUF; /* Dead Time Both Sides Buffer */ - register8_t DTLS; /* Dead Time Low Side */ - register8_t DTHS; /* Dead Time High Side */ - register8_t DTLSBUF; /* Dead Time Low Side Buffer */ - register8_t DTHSBUF; /* Dead Time High Side Buffer */ - register8_t OUTOVEN; /* Output Override Enable */ -} AWEX_t; - -/* Fault Detect Action */ -typedef enum AWEX_FDACT_enum -{ - AWEX_FDACT_NONE_gc = (0x00<<0), /* No Fault Protection */ - AWEX_FDACT_CLEAROE_gc = (0x01<<0), /* Clear Output Enable Bits */ - AWEX_FDACT_CLEARDIR_gc = (0x03<<0), /* Clear I/O Port Direction Bits */ -} AWEX_FDACT_t; - - -/* --------------------------------------------------------------------------- -HIRES - Timer/Counter High-Resolution Extension --------------------------------------------------------------------------- -*/ - -/* High-Resolution Extension */ -typedef struct HIRES_struct -{ - register8_t CTRLA; /* Control Register */ -} HIRES_t; - -/* High Resolution Enable */ -typedef enum HIRES_HREN_enum -{ - HIRES_HREN_NONE_gc = (0x00<<0), /* No Fault Protection */ - HIRES_HREN_TC0_gc = (0x01<<0), /* Enable High Resolution on Timer/Counter 0 */ - HIRES_HREN_TC1_gc = (0x02<<0), /* Enable High Resolution on Timer/Counter 1 */ - HIRES_HREN_BOTH_gc = (0x03<<0), /* Enable High Resolution both Timer/Counters */ -} HIRES_HREN_t; - - -/* --------------------------------------------------------------------------- -USART - Universal Asynchronous Receiver-Transmitter --------------------------------------------------------------------------- -*/ - -/* Universal Synchronous/Asynchronous Receiver/Transmitter */ -typedef struct USART_struct -{ - register8_t DATA; /* Data Register */ - register8_t STATUS; /* Status Register */ - register8_t reserved_0x02; - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t CTRLC; /* Control Register C */ - register8_t BAUDCTRLA; /* Baud Rate Control Register A */ - register8_t BAUDCTRLB; /* Baud Rate Control Register B */ -} USART_t; - -/* Receive Complete Interrupt level */ -typedef enum USART_RXCINTLVL_enum -{ - USART_RXCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ - USART_RXCINTLVL_LO_gc = (0x01<<4), /* Low Level */ - USART_RXCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ - USART_RXCINTLVL_HI_gc = (0x03<<4), /* High Level */ -} USART_RXCINTLVL_t; - -/* Transmit Complete Interrupt level */ -typedef enum USART_TXCINTLVL_enum -{ - USART_TXCINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ - USART_TXCINTLVL_LO_gc = (0x01<<2), /* Low Level */ - USART_TXCINTLVL_MED_gc = (0x02<<2), /* Medium Level */ - USART_TXCINTLVL_HI_gc = (0x03<<2), /* High Level */ -} USART_TXCINTLVL_t; - -/* Data Register Empty Interrupt level */ -typedef enum USART_DREINTLVL_enum -{ - USART_DREINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - USART_DREINTLVL_LO_gc = (0x01<<0), /* Low Level */ - USART_DREINTLVL_MED_gc = (0x02<<0), /* Medium Level */ - USART_DREINTLVL_HI_gc = (0x03<<0), /* High Level */ -} USART_DREINTLVL_t; - -/* Character Size */ -typedef enum USART_CHSIZE_enum -{ - USART_CHSIZE_5BIT_gc = (0x00<<0), /* Character size: 5 bit */ - USART_CHSIZE_6BIT_gc = (0x01<<0), /* Character size: 6 bit */ - USART_CHSIZE_7BIT_gc = (0x02<<0), /* Character size: 7 bit */ - USART_CHSIZE_8BIT_gc = (0x03<<0), /* Character size: 8 bit */ - USART_CHSIZE_9BIT_gc = (0x07<<0), /* Character size: 9 bit */ -} USART_CHSIZE_t; - -/* Communication Mode */ -typedef enum USART_CMODE_enum -{ - USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6), /* Asynchronous Mode */ - USART_CMODE_SYNCHRONOUS_gc = (0x01<<6), /* Synchronous Mode */ - USART_CMODE_IRDA_gc = (0x02<<6), /* IrDA Mode */ - USART_CMODE_MSPI_gc = (0x03<<6), /* Master SPI Mode */ -} USART_CMODE_t; - -/* Parity Mode */ -typedef enum USART_PMODE_enum -{ - USART_PMODE_DISABLED_gc = (0x00<<4), /* No Parity */ - USART_PMODE_EVEN_gc = (0x02<<4), /* Even Parity */ - USART_PMODE_ODD_gc = (0x03<<4), /* Odd Parity */ -} USART_PMODE_t; - - -/* --------------------------------------------------------------------------- -SPI - Serial Peripheral Interface --------------------------------------------------------------------------- -*/ - -/* Serial Peripheral Interface */ -typedef struct SPI_struct -{ - register8_t CTRL; /* Control Register */ - register8_t INTCTRL; /* Interrupt Control Register */ - register8_t STATUS; /* Status Register */ - register8_t DATA; /* Data Register */ -} SPI_t; - -/* SPI Mode */ -typedef enum SPI_MODE_enum -{ - SPI_MODE_0_gc = (0x00<<2), /* SPI Mode 0 */ - SPI_MODE_1_gc = (0x01<<2), /* SPI Mode 1 */ - SPI_MODE_2_gc = (0x02<<2), /* SPI Mode 2 */ - SPI_MODE_3_gc = (0x03<<2), /* SPI Mode 3 */ -} SPI_MODE_t; - -/* Prescaler setting */ -typedef enum SPI_PRESCALER_enum -{ - SPI_PRESCALER_DIV4_gc = (0x00<<0), /* System Clock / 4 */ - SPI_PRESCALER_DIV16_gc = (0x01<<0), /* System Clock / 16 */ - SPI_PRESCALER_DIV64_gc = (0x02<<0), /* System Clock / 64 */ - SPI_PRESCALER_DIV128_gc = (0x03<<0), /* System Clock / 128 */ -} SPI_PRESCALER_t; - -/* Interrupt level */ -typedef enum SPI_INTLVL_enum -{ - SPI_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - SPI_INTLVL_LO_gc = (0x01<<0), /* Low Level */ - SPI_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ - SPI_INTLVL_HI_gc = (0x03<<0), /* High Level */ -} SPI_INTLVL_t; - - -/* --------------------------------------------------------------------------- -IRCOM - IR Communication Module --------------------------------------------------------------------------- -*/ - -/* IR Communication Module */ -typedef struct IRCOM_struct -{ - register8_t CTRL; /* Control Register */ - register8_t TXPLCTRL; /* IrDA Transmitter Pulse Length Control Register */ - register8_t RXPLCTRL; /* IrDA Receiver Pulse Length Control Register */ -} IRCOM_t; - -/* Event channel selection */ -typedef enum IRDA_EVSEL_enum -{ - IRDA_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ - IRDA_EVSEL_0_gc = (0x08<<0), /* Event Channel 0 */ - IRDA_EVSEL_1_gc = (0x09<<0), /* Event Channel 1 */ - IRDA_EVSEL_2_gc = (0x0A<<0), /* Event Channel 2 */ - IRDA_EVSEL_3_gc = (0x0B<<0), /* Event Channel 3 */ - IRDA_EVSEL_4_gc = (0x0C<<0), /* Event Channel 4 */ - IRDA_EVSEL_5_gc = (0x0D<<0), /* Event Channel 5 */ - IRDA_EVSEL_6_gc = (0x0E<<0), /* Event Channel 6 */ - IRDA_EVSEL_7_gc = (0x0F<<0), /* Event Channel 7 */ -} IRDA_EVSEL_t; - - -/* --------------------------------------------------------------------------- -FUSE - Fuses and Lockbits --------------------------------------------------------------------------- -*/ - -/* Fuses */ -typedef struct NVM_FUSES_struct -{ - register8_t FUSEBYTE0; /* JTAG User ID */ - register8_t FUSEBYTE1; /* Watchdog Configuration */ - register8_t FUSEBYTE2; /* Reset Configuration */ - register8_t reserved_0x03; - register8_t FUSEBYTE4; /* Start-up Configuration */ - register8_t FUSEBYTE5; /* EESAVE and BOD Level */ -} NVM_FUSES_t; - -/* Boot Loader Section Reset Vector */ -typedef enum BOOTRST_enum -{ - BOOTRST_BOOTLDR_gc = (0x00<<6), /* Boot Loader Reset */ - BOOTRST_APPLICATION_gc = (0x01<<6), /* Application Reset */ -} BOOTRST_t; - -/* Timer Oscillator pin location */ -typedef enum TOSCSEL_enum -{ - TOSCSEL_ALTERNATE_gc = (0x00<<5), /* TOSC1 / TOSC2 on separate pins */ - TOSCSEL_XTAL_gc = (0x01<<5), /* TOSC1 / TOSC2 shared with XTAL1 / XTAL2 */ -} TOSCSEL_t; - -/* BOD operation */ -typedef enum BOD_enum -{ - BOD_SAMPLED_gc = (0x01<<0), /* BOD enabled in sampled mode */ - BOD_CONTINUOUS_gc = (0x02<<0), /* BOD enabled continuously */ - BOD_DISABLED_gc = (0x03<<0), /* BOD Disabled */ -} BOD_t; - -/* BOD operation */ -typedef enum BODACT_enum -{ - BODACT_SAMPLED_gc = (0x01<<4), /* BOD enabled in sampled mode */ - BODACT_CONTINUOUS_gc = (0x02<<4), /* BOD enabled continuously */ - BODACT_DISABLED_gc = (0x03<<4), /* BOD Disabled */ -} BODACT_t; - -/* Watchdog (Window) Timeout Period */ -typedef enum WD_enum -{ - WD_8CLK_gc = (0x00<<4), /* 8 cycles (8ms @ 3.3V) */ - WD_16CLK_gc = (0x01<<4), /* 16 cycles (16ms @ 3.3V) */ - WD_32CLK_gc = (0x02<<4), /* 32 cycles (32ms @ 3.3V) */ - WD_64CLK_gc = (0x03<<4), /* 64 cycles (64ms @ 3.3V) */ - WD_128CLK_gc = (0x04<<4), /* 128 cycles (0.125s @ 3.3V) */ - WD_256CLK_gc = (0x05<<4), /* 256 cycles (0.25s @ 3.3V) */ - WD_512CLK_gc = (0x06<<4), /* 512 cycles (0.5s @ 3.3V) */ - WD_1KCLK_gc = (0x07<<4), /* 1K cycles (1s @ 3.3V) */ - WD_2KCLK_gc = (0x08<<4), /* 2K cycles (2s @ 3.3V) */ - WD_4KCLK_gc = (0x09<<4), /* 4K cycles (4s @ 3.3V) */ - WD_8KCLK_gc = (0x0A<<4), /* 8K cycles (8s @ 3.3V) */ -} WD_t; - -/* Watchdog (Window) Timeout Period */ -typedef enum WDP_enum -{ - WDP_8CLK_gc = (0x00<<0), /* 8 cycles (8ms @ 3.3V) */ - WDP_16CLK_gc = (0x01<<0), /* 16 cycles (16ms @ 3.3V) */ - WDP_32CLK_gc = (0x02<<0), /* 32 cycles (32ms @ 3.3V) */ - WDP_64CLK_gc = (0x03<<0), /* 64 cycles (64ms @ 3.3V) */ - WDP_128CLK_gc = (0x04<<0), /* 128 cycles (0.125s @ 3.3V) */ - WDP_256CLK_gc = (0x05<<0), /* 256 cycles (0.25s @ 3.3V) */ - WDP_512CLK_gc = (0x06<<0), /* 512 cycles (0.5s @ 3.3V) */ - WDP_1KCLK_gc = (0x07<<0), /* 1K cycles (1s @ 3.3V) */ - WDP_2KCLK_gc = (0x08<<0), /* 2K cycles (2s @ 3.3V) */ - WDP_4KCLK_gc = (0x09<<0), /* 4K cycles (4s @ 3.3V) */ - WDP_8KCLK_gc = (0x0A<<0), /* 8K cycles (8s @ 3.3V) */ -} WDP_t; - -/* Start-up Time */ -typedef enum SUT_enum -{ - SUT_0MS_gc = (0x03<<2), /* 0 ms */ - SUT_4MS_gc = (0x01<<2), /* 4 ms */ - SUT_64MS_gc = (0x00<<2), /* 64 ms */ -} SUT_t; - -/* Brownout Detection Voltage Level */ -typedef enum BODLVL_enum -{ - BODLVL_1V6_gc = (0x07<<0), /* 1.6 V */ - BODLVL_1V8_gc = (0x06<<0), /* 1.8 V */ - BODLVL_2V0_gc = (0x05<<0), /* 2.0 V */ - BODLVL_2V2_gc = (0x04<<0), /* 2.2 V */ - BODLVL_2V4_gc = (0x03<<0), /* 2.4 V */ - BODLVL_2V6_gc = (0x02<<0), /* 2.6 V */ - BODLVL_2V8_gc = (0x01<<0), /* 2.8 V */ - BODLVL_3V0_gc = (0x00<<0), /* 3.0 V */ -} BODLVL_t; - - -/* --------------------------------------------------------------------------- -LOCKBIT - Fuses and Lockbits --------------------------------------------------------------------------- -*/ - -/* Lock Bits */ -typedef struct NVM_LOCKBITS_struct -{ - register8_t LOCK_BITS; /* Lock Bits (Changed from LOCKBITS to avoid avr-libc collision) */ -} NVM_LOCKBITS_t; - -/* Boot lock bits - boot setcion */ -typedef enum FUSE_BLBB_enum -{ - FUSE_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ - FUSE_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ - FUSE_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ - FUSE_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ -} FUSE_BLBB_t; - -/* Boot lock bits - application section */ -typedef enum FUSE_BLBA_enum -{ - FUSE_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ - FUSE_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ - FUSE_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ - FUSE_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ -} FUSE_BLBA_t; - -/* Boot lock bits - application table section */ -typedef enum FUSE_BLBAT_enum -{ - FUSE_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ - FUSE_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ - FUSE_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ - FUSE_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ -} FUSE_BLBAT_t; - -/* Lock bits */ -typedef enum FUSE_LB_enum -{ - FUSE_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ - FUSE_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ - FUSE_LB_NOLOCK_gc = (0x03<<0), /* No locks */ -} FUSE_LB_t; - - -/* --------------------------------------------------------------------------- -SIGROW - Signature Row --------------------------------------------------------------------------- -*/ - -/* Production Signatures */ -typedef struct NVM_PROD_SIGNATURES_struct -{ - register8_t RCOSC2M; /* RCOSC 2 MHz Calibration Value B */ - register8_t RCOSC2MA; /* RCOSC 2 MHz Calibration Value A */ - register8_t RCOSC32K; /* RCOSC 32.768 kHz Calibration Value */ - register8_t RCOSC32M; /* RCOSC 32 MHz Calibration Value B */ - register8_t RCOSC32MA; /* RCOSC 32 MHz Calibration Value A */ - register8_t reserved_0x05; - register8_t reserved_0x06; - register8_t reserved_0x07; - register8_t LOTNUM0; /* Lot Number Byte 0, ASCII */ - register8_t LOTNUM1; /* Lot Number Byte 1, ASCII */ - register8_t LOTNUM2; /* Lot Number Byte 2, ASCII */ - register8_t LOTNUM3; /* Lot Number Byte 3, ASCII */ - register8_t LOTNUM4; /* Lot Number Byte 4, ASCII */ - register8_t LOTNUM5; /* Lot Number Byte 5, ASCII */ - register8_t reserved_0x0E; - register8_t reserved_0x0F; - register8_t WAFNUM; /* Wafer Number */ - register8_t reserved_0x11; - register8_t COORDX0; /* Wafer Coordinate X Byte 0 */ - register8_t COORDX1; /* Wafer Coordinate X Byte 1 */ - register8_t COORDY0; /* Wafer Coordinate Y Byte 0 */ - register8_t COORDY1; /* Wafer Coordinate Y Byte 1 */ - register8_t reserved_0x16; - register8_t reserved_0x17; - register8_t reserved_0x18; - register8_t reserved_0x19; - register8_t USBCAL0; /* USB Calibration Byte 0 */ - register8_t USBCAL1; /* USB Calibration Byte 1 */ - register8_t USBRCOSC; /* USB RCOSC Calibration Value B */ - register8_t USBRCOSCA; /* USB RCOSC Calibration Value A */ - register8_t reserved_0x1E; - register8_t reserved_0x1F; - register8_t ADCACAL0; /* ADCA Calibration Byte 0 */ - register8_t ADCACAL1; /* ADCA Calibration Byte 1 */ - register8_t reserved_0x22; - register8_t reserved_0x23; - register8_t ADCBCAL0; /* ADCB Calibration Byte 0 */ - register8_t ADCBCAL1; /* ADCB Calibration Byte 1 */ - register8_t reserved_0x26; - register8_t reserved_0x27; - register8_t reserved_0x28; - register8_t reserved_0x29; - register8_t reserved_0x2A; - register8_t reserved_0x2B; - register8_t reserved_0x2C; - register8_t reserved_0x2D; - register8_t TEMPSENSE0; /* Temperature Sensor Calibration Byte 0 */ - register8_t TEMPSENSE1; /* Temperature Sensor Calibration Byte 1 */ - register8_t DACA0OFFCAL; /* DACA0 Calibration Byte 0 */ - register8_t DACA0GAINCAL; /* DACA0 Calibration Byte 1 */ - register8_t DACB0OFFCAL; /* DACB0 Calibration Byte 0 */ - register8_t DACB0GAINCAL; /* DACB0 Calibration Byte 1 */ - register8_t DACA1OFFCAL; /* DACA1 Calibration Byte 0 */ - register8_t DACA1GAINCAL; /* DACA1 Calibration Byte 1 */ - register8_t DACB1OFFCAL; /* DACB1 Calibration Byte 0 */ - register8_t DACB1GAINCAL; /* DACB1 Calibration Byte 1 */ - register8_t reserved_0x38; - register8_t reserved_0x39; - register8_t reserved_0x3A; - register8_t reserved_0x3B; - register8_t reserved_0x3C; - register8_t reserved_0x3D; - register8_t reserved_0x3E; - register8_t reserved_0x3F; - register8_t reserved_0x40; - register8_t reserved_0x41; - register8_t reserved_0x42; - register8_t reserved_0x43; - register8_t reserved_0x44; - register8_t reserved_0x45; - register8_t reserved_0x46; - register8_t reserved_0x47; -} NVM_PROD_SIGNATURES_t; - -/* -========================================================================== -IO Module Instances. Mapped to memory. -========================================================================== -*/ - -#define VPORT0 (*(VPORT_t *) 0x0010) /* Virtual Port */ -#define VPORT1 (*(VPORT_t *) 0x0014) /* Virtual Port */ -#define VPORT2 (*(VPORT_t *) 0x0018) /* Virtual Port */ -#define VPORT3 (*(VPORT_t *) 0x001C) /* Virtual Port */ -#define OCD (*(OCD_t *) 0x002E) /* On-Chip Debug System */ -#define CLK (*(CLK_t *) 0x0040) /* Clock System */ -#define SLEEP (*(SLEEP_t *) 0x0048) /* Sleep Controller */ -#define OSC (*(OSC_t *) 0x0050) /* Oscillator */ -#define DFLLRC32M (*(DFLL_t *) 0x0060) /* DFLL */ -#define DFLLRC2M (*(DFLL_t *) 0x0068) /* DFLL */ -#define PR (*(PR_t *) 0x0070) /* Power Reduction */ -#define RST (*(RST_t *) 0x0078) /* Reset */ -#define WDT (*(WDT_t *) 0x0080) /* Watch-Dog Timer */ -#define MCU (*(MCU_t *) 0x0090) /* MCU Control */ -#define PMIC (*(PMIC_t *) 0x00A0) /* Programmable Multi-level Interrupt Controller */ -#define PORTCFG (*(PORTCFG_t *) 0x00B0) /* I/O port Configuration */ -#define AES (*(AES_t *) 0x00C0) /* AES Module */ -#define CRC (*(CRC_t *) 0x00D0) /* Cyclic Redundancy Checker */ -#define DMA (*(DMA_t *) 0x0100) /* DMA Controller */ -#define EVSYS (*(EVSYS_t *) 0x0180) /* Event System */ -#define NVM (*(NVM_t *) 0x01C0) /* Non-volatile Memory Controller */ -#define ADCA (*(ADC_t *) 0x0200) /* Analog-to-Digital Converter */ -#define ADCB (*(ADC_t *) 0x0240) /* Analog-to-Digital Converter */ -#define DACB (*(DAC_t *) 0x0320) /* Digital-to-Analog Converter */ -#define ACA (*(AC_t *) 0x0380) /* Analog Comparator */ -#define ACB (*(AC_t *) 0x0390) /* Analog Comparator */ -#define RTC (*(RTC_t *) 0x0400) /* Real-Time Counter */ -#define TWIC (*(TWI_t *) 0x0480) /* Two-Wire Interface */ -#define TWIE (*(TWI_t *) 0x04A0) /* Two-Wire Interface */ -#define USB (*(USB_t *) 0x04C0) /* Universal Serial Bus */ -#define PORTA (*(PORT_t *) 0x0600) /* I/O Ports */ -#define PORTB (*(PORT_t *) 0x0620) /* I/O Ports */ -#define PORTC (*(PORT_t *) 0x0640) /* I/O Ports */ -#define PORTD (*(PORT_t *) 0x0660) /* I/O Ports */ -#define PORTE (*(PORT_t *) 0x0680) /* I/O Ports */ -#define PORTF (*(PORT_t *) 0x06A0) /* I/O Ports */ -#define PORTR (*(PORT_t *) 0x07E0) /* I/O Ports */ -#define TCC0 (*(TC0_t *) 0x0800) /* 16-bit Timer/Counter 0 */ -#define TCC2 (*(TC2_t *) 0x0800) /* 16-bit Timer/Counter type 2 */ -#define TCC1 (*(TC1_t *) 0x0840) /* 16-bit Timer/Counter 1 */ -#define AWEXC (*(AWEX_t *) 0x0880) /* Advanced Waveform Extension */ -#define HIRESC (*(HIRES_t *) 0x0890) /* High-Resolution Extension */ -#define USARTC0 (*(USART_t *) 0x08A0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ -#define USARTC1 (*(USART_t *) 0x08B0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ -#define SPIC (*(SPI_t *) 0x08C0) /* Serial Peripheral Interface */ -#define IRCOM (*(IRCOM_t *) 0x08F8) /* IR Communication Module */ -#define TCD0 (*(TC0_t *) 0x0900) /* 16-bit Timer/Counter 0 */ -#define TCD2 (*(TC2_t *) 0x0900) /* 16-bit Timer/Counter type 2 */ -#define TCD1 (*(TC1_t *) 0x0940) /* 16-bit Timer/Counter 1 */ -#define HIRESD (*(HIRES_t *) 0x0990) /* High-Resolution Extension */ -#define USARTD0 (*(USART_t *) 0x09A0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ -#define USARTD1 (*(USART_t *) 0x09B0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ -#define SPID (*(SPI_t *) 0x09C0) /* Serial Peripheral Interface */ -#define TCE0 (*(TC0_t *) 0x0A00) /* 16-bit Timer/Counter 0 */ -#define TCE2 (*(TC2_t *) 0x0A00) /* 16-bit Timer/Counter type 2 */ -#define TCE1 (*(TC1_t *) 0x0A40) /* 16-bit Timer/Counter 1 */ -#define AWEXE (*(AWEX_t *) 0x0A80) /* Advanced Waveform Extension */ -#define HIRESE (*(HIRES_t *) 0x0A90) /* High-Resolution Extension */ -#define USARTE0 (*(USART_t *) 0x0AA0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ -#define USARTE1 (*(USART_t *) 0x0AB0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ -#define SPIE (*(SPI_t *) 0x0AC0) /* Serial Peripheral Interface */ -#define TCF0 (*(TC0_t *) 0x0B00) /* 16-bit Timer/Counter 0 */ -#define TCF2 (*(TC2_t *) 0x0B00) /* 16-bit Timer/Counter type 2 */ -#define HIRESF (*(HIRES_t *) 0x0B90) /* High-Resolution Extension */ -#define USARTF0 (*(USART_t *) 0x0BA0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ - - -#endif /* !defined (__ASSEMBLER__) */ - - -/* ========== Flattened fully qualified IO register names ========== */ - -/* GPIO - General Purpose IO Registers */ -#define GPIO_GPIOR0 _SFR_MEM8(0x0000) -#define GPIO_GPIOR1 _SFR_MEM8(0x0001) -#define GPIO_GPIOR2 _SFR_MEM8(0x0002) -#define GPIO_GPIOR3 _SFR_MEM8(0x0003) -#define GPIO_GPIOR4 _SFR_MEM8(0x0004) -#define GPIO_GPIOR5 _SFR_MEM8(0x0005) -#define GPIO_GPIOR6 _SFR_MEM8(0x0006) -#define GPIO_GPIOR7 _SFR_MEM8(0x0007) -#define GPIO_GPIOR8 _SFR_MEM8(0x0008) -#define GPIO_GPIOR9 _SFR_MEM8(0x0009) -#define GPIO_GPIORA _SFR_MEM8(0x000A) -#define GPIO_GPIORB _SFR_MEM8(0x000B) -#define GPIO_GPIORC _SFR_MEM8(0x000C) -#define GPIO_GPIORD _SFR_MEM8(0x000D) -#define GPIO_GPIORE _SFR_MEM8(0x000E) -#define GPIO_GPIORF _SFR_MEM8(0x000F) - -/* Deprecated */ -#define GPIO_GPIO0 _SFR_MEM8(0x0000) -#define GPIO_GPIO1 _SFR_MEM8(0x0001) -#define GPIO_GPIO2 _SFR_MEM8(0x0002) -#define GPIO_GPIO3 _SFR_MEM8(0x0003) -#define GPIO_GPIO4 _SFR_MEM8(0x0004) -#define GPIO_GPIO5 _SFR_MEM8(0x0005) -#define GPIO_GPIO6 _SFR_MEM8(0x0006) -#define GPIO_GPIO7 _SFR_MEM8(0x0007) -#define GPIO_GPIO8 _SFR_MEM8(0x0008) -#define GPIO_GPIO9 _SFR_MEM8(0x0009) -#define GPIO_GPIOA _SFR_MEM8(0x000A) -#define GPIO_GPIOB _SFR_MEM8(0x000B) -#define GPIO_GPIOC _SFR_MEM8(0x000C) -#define GPIO_GPIOD _SFR_MEM8(0x000D) -#define GPIO_GPIOE _SFR_MEM8(0x000E) -#define GPIO_GPIOF _SFR_MEM8(0x000F) - -/* NVM_FUSES - Fuses */ -#define FUSE_FUSEBYTE0 _SFR_MEM8(0x0000) -#define FUSE_FUSEBYTE1 _SFR_MEM8(0x0001) -#define FUSE_FUSEBYTE2 _SFR_MEM8(0x0002) -#define FUSE_FUSEBYTE4 _SFR_MEM8(0x0004) -#define FUSE_FUSEBYTE5 _SFR_MEM8(0x0005) - -/* NVM_LOCKBITS - Lock Bits */ -#define LOCKBIT_LOCKBITS _SFR_MEM8(0x0000) - -/* NVM_PROD_SIGNATURES - Production Signatures */ -#define PRODSIGNATURES_RCOSC2M _SFR_MEM8(0x0000) -#define PRODSIGNATURES_RCOSC2MA _SFR_MEM8(0x0001) -#define PRODSIGNATURES_RCOSC32K _SFR_MEM8(0x0002) -#define PRODSIGNATURES_RCOSC32M _SFR_MEM8(0x0003) -#define PRODSIGNATURES_RCOSC32MA _SFR_MEM8(0x0004) -#define PRODSIGNATURES_LOTNUM0 _SFR_MEM8(0x0008) -#define PRODSIGNATURES_LOTNUM1 _SFR_MEM8(0x0009) -#define PRODSIGNATURES_LOTNUM2 _SFR_MEM8(0x000A) -#define PRODSIGNATURES_LOTNUM3 _SFR_MEM8(0x000B) -#define PRODSIGNATURES_LOTNUM4 _SFR_MEM8(0x000C) -#define PRODSIGNATURES_LOTNUM5 _SFR_MEM8(0x000D) -#define PRODSIGNATURES_WAFNUM _SFR_MEM8(0x0010) -#define PRODSIGNATURES_COORDX0 _SFR_MEM8(0x0012) -#define PRODSIGNATURES_COORDX1 _SFR_MEM8(0x0013) -#define PRODSIGNATURES_COORDY0 _SFR_MEM8(0x0014) -#define PRODSIGNATURES_COORDY1 _SFR_MEM8(0x0015) -#define PRODSIGNATURES_USBCAL0 _SFR_MEM8(0x001A) -#define PRODSIGNATURES_USBCAL1 _SFR_MEM8(0x001B) -#define PRODSIGNATURES_USBRCOSC _SFR_MEM8(0x001C) -#define PRODSIGNATURES_USBRCOSCA _SFR_MEM8(0x001D) -#define PRODSIGNATURES_ADCACAL0 _SFR_MEM8(0x0020) -#define PRODSIGNATURES_ADCACAL1 _SFR_MEM8(0x0021) -#define PRODSIGNATURES_ADCBCAL0 _SFR_MEM8(0x0024) -#define PRODSIGNATURES_ADCBCAL1 _SFR_MEM8(0x0025) -#define PRODSIGNATURES_TEMPSENSE0 _SFR_MEM8(0x002E) -#define PRODSIGNATURES_TEMPSENSE1 _SFR_MEM8(0x002F) -#define PRODSIGNATURES_DACA0OFFCAL _SFR_MEM8(0x0030) -#define PRODSIGNATURES_DACA0GAINCAL _SFR_MEM8(0x0031) -#define PRODSIGNATURES_DACB0OFFCAL _SFR_MEM8(0x0032) -#define PRODSIGNATURES_DACB0GAINCAL _SFR_MEM8(0x0033) -#define PRODSIGNATURES_DACA1OFFCAL _SFR_MEM8(0x0034) -#define PRODSIGNATURES_DACA1GAINCAL _SFR_MEM8(0x0035) -#define PRODSIGNATURES_DACB1OFFCAL _SFR_MEM8(0x0036) -#define PRODSIGNATURES_DACB1GAINCAL _SFR_MEM8(0x0037) - -/* VPORT - Virtual Port */ -#define VPORT0_DIR _SFR_MEM8(0x0010) -#define VPORT0_OUT _SFR_MEM8(0x0011) -#define VPORT0_IN _SFR_MEM8(0x0012) -#define VPORT0_INTFLAGS _SFR_MEM8(0x0013) - -/* VPORT - Virtual Port */ -#define VPORT1_DIR _SFR_MEM8(0x0014) -#define VPORT1_OUT _SFR_MEM8(0x0015) -#define VPORT1_IN _SFR_MEM8(0x0016) -#define VPORT1_INTFLAGS _SFR_MEM8(0x0017) - -/* VPORT - Virtual Port */ -#define VPORT2_DIR _SFR_MEM8(0x0018) -#define VPORT2_OUT _SFR_MEM8(0x0019) -#define VPORT2_IN _SFR_MEM8(0x001A) -#define VPORT2_INTFLAGS _SFR_MEM8(0x001B) - -/* VPORT - Virtual Port */ -#define VPORT3_DIR _SFR_MEM8(0x001C) -#define VPORT3_OUT _SFR_MEM8(0x001D) -#define VPORT3_IN _SFR_MEM8(0x001E) -#define VPORT3_INTFLAGS _SFR_MEM8(0x001F) - -/* OCD - On-Chip Debug System */ -#define OCD_OCDR0 _SFR_MEM8(0x002E) -#define OCD_OCDR1 _SFR_MEM8(0x002F) - -/* CPU - CPU registers */ -#define CPU_CCP _SFR_MEM8(0x0034) -#define CPU_RAMPD _SFR_MEM8(0x0038) -#define CPU_RAMPX _SFR_MEM8(0x0039) -#define CPU_RAMPY _SFR_MEM8(0x003A) -#define CPU_RAMPZ _SFR_MEM8(0x003B) -#define CPU_EIND _SFR_MEM8(0x003C) -#define CPU_SPL _SFR_MEM8(0x003D) -#define CPU_SPH _SFR_MEM8(0x003E) -#define CPU_SREG _SFR_MEM8(0x003F) - -/* CLK - Clock System */ -#define CLK_CTRL _SFR_MEM8(0x0040) -#define CLK_PSCTRL _SFR_MEM8(0x0041) -#define CLK_LOCK _SFR_MEM8(0x0042) -#define CLK_RTCCTRL _SFR_MEM8(0x0043) -#define CLK_USBCTRL _SFR_MEM8(0x0044) - -/* SLEEP - Sleep Controller */ -#define SLEEP_CTRL _SFR_MEM8(0x0048) - -/* OSC - Oscillator */ -#define OSC_CTRL _SFR_MEM8(0x0050) -#define OSC_STATUS _SFR_MEM8(0x0051) -#define OSC_XOSCCTRL _SFR_MEM8(0x0052) -#define OSC_XOSCFAIL _SFR_MEM8(0x0053) -#define OSC_RC32KCAL _SFR_MEM8(0x0054) -#define OSC_PLLCTRL _SFR_MEM8(0x0055) -#define OSC_DFLLCTRL _SFR_MEM8(0x0056) - -/* DFLL - DFLL */ -#define DFLLRC32M_CTRL _SFR_MEM8(0x0060) -#define DFLLRC32M_CALA _SFR_MEM8(0x0062) -#define DFLLRC32M_CALB _SFR_MEM8(0x0063) -#define DFLLRC32M_COMP0 _SFR_MEM8(0x0064) -#define DFLLRC32M_COMP1 _SFR_MEM8(0x0065) -#define DFLLRC32M_COMP2 _SFR_MEM8(0x0066) - -/* DFLL - DFLL */ -#define DFLLRC2M_CTRL _SFR_MEM8(0x0068) -#define DFLLRC2M_CALA _SFR_MEM8(0x006A) -#define DFLLRC2M_CALB _SFR_MEM8(0x006B) -#define DFLLRC2M_COMP0 _SFR_MEM8(0x006C) -#define DFLLRC2M_COMP1 _SFR_MEM8(0x006D) -#define DFLLRC2M_COMP2 _SFR_MEM8(0x006E) - -/* PR - Power Reduction */ -#define PR_PRGEN _SFR_MEM8(0x0070) -#define PR_PRPA _SFR_MEM8(0x0071) -#define PR_PRPB _SFR_MEM8(0x0072) -#define PR_PRPC _SFR_MEM8(0x0073) -#define PR_PRPD _SFR_MEM8(0x0074) -#define PR_PRPE _SFR_MEM8(0x0075) -#define PR_PRPF _SFR_MEM8(0x0076) - -/* RST - Reset */ -#define RST_STATUS _SFR_MEM8(0x0078) -#define RST_CTRL _SFR_MEM8(0x0079) - -/* WDT - Watch-Dog Timer */ -#define WDT_CTRL _SFR_MEM8(0x0080) -#define WDT_WINCTRL _SFR_MEM8(0x0081) -#define WDT_STATUS _SFR_MEM8(0x0082) - -/* MCU - MCU Control */ -#define MCU_DEVID0 _SFR_MEM8(0x0090) -#define MCU_DEVID1 _SFR_MEM8(0x0091) -#define MCU_DEVID2 _SFR_MEM8(0x0092) -#define MCU_REVID _SFR_MEM8(0x0093) -#define MCU_JTAGUID _SFR_MEM8(0x0094) -#define MCU_MCUCR _SFR_MEM8(0x0096) -#define MCU_ANAINIT _SFR_MEM8(0x0097) -#define MCU_EVSYSLOCK _SFR_MEM8(0x0098) -#define MCU_AWEXLOCK _SFR_MEM8(0x0099) - -/* PMIC - Programmable Multi-level Interrupt Controller */ -#define PMIC_STATUS _SFR_MEM8(0x00A0) -#define PMIC_INTPRI _SFR_MEM8(0x00A1) -#define PMIC_CTRL _SFR_MEM8(0x00A2) - -/* PORTCFG - I/O port Configuration */ -#define PORTCFG_MPCMASK _SFR_MEM8(0x00B0) -#define PORTCFG_VPCTRLA _SFR_MEM8(0x00B2) -#define PORTCFG_VPCTRLB _SFR_MEM8(0x00B3) -#define PORTCFG_CLKEVOUT _SFR_MEM8(0x00B4) -#define PORTCFG_EBIOUT _SFR_MEM8(0x00B5) -#define PORTCFG_EVOUTSEL _SFR_MEM8(0x00B6) - -/* AES - AES Module */ -#define AES_CTRL _SFR_MEM8(0x00C0) -#define AES_STATUS _SFR_MEM8(0x00C1) -#define AES_STATE _SFR_MEM8(0x00C2) -#define AES_KEY _SFR_MEM8(0x00C3) -#define AES_INTCTRL _SFR_MEM8(0x00C4) - -/* CRC - Cyclic Redundancy Checker */ -#define CRC_CTRL _SFR_MEM8(0x00D0) -#define CRC_STATUS _SFR_MEM8(0x00D1) -#define CRC_DATAIN _SFR_MEM8(0x00D3) -#define CRC_CHECKSUM0 _SFR_MEM8(0x00D4) -#define CRC_CHECKSUM1 _SFR_MEM8(0x00D5) -#define CRC_CHECKSUM2 _SFR_MEM8(0x00D6) -#define CRC_CHECKSUM3 _SFR_MEM8(0x00D7) - -/* DMA - DMA Controller */ -#define DMA_CTRL _SFR_MEM8(0x0100) -#define DMA_INTFLAGS _SFR_MEM8(0x0103) -#define DMA_STATUS _SFR_MEM8(0x0104) -#define DMA_TEMP _SFR_MEM16(0x0106) -#define DMA_CH0_CTRLA _SFR_MEM8(0x0110) -#define DMA_CH0_CTRLB _SFR_MEM8(0x0111) -#define DMA_CH0_ADDRCTRL _SFR_MEM8(0x0112) -#define DMA_CH0_TRIGSRC _SFR_MEM8(0x0113) -#define DMA_CH0_TRFCNT _SFR_MEM16(0x0114) -#define DMA_CH0_REPCNT _SFR_MEM8(0x0116) -#define DMA_CH0_SRCADDR0 _SFR_MEM8(0x0118) -#define DMA_CH0_SRCADDR1 _SFR_MEM8(0x0119) -#define DMA_CH0_SRCADDR2 _SFR_MEM8(0x011A) -#define DMA_CH0_DESTADDR0 _SFR_MEM8(0x011C) -#define DMA_CH0_DESTADDR1 _SFR_MEM8(0x011D) -#define DMA_CH0_DESTADDR2 _SFR_MEM8(0x011E) -#define DMA_CH1_CTRLA _SFR_MEM8(0x0120) -#define DMA_CH1_CTRLB _SFR_MEM8(0x0121) -#define DMA_CH1_ADDRCTRL _SFR_MEM8(0x0122) -#define DMA_CH1_TRIGSRC _SFR_MEM8(0x0123) -#define DMA_CH1_TRFCNT _SFR_MEM16(0x0124) -#define DMA_CH1_REPCNT _SFR_MEM8(0x0126) -#define DMA_CH1_SRCADDR0 _SFR_MEM8(0x0128) -#define DMA_CH1_SRCADDR1 _SFR_MEM8(0x0129) -#define DMA_CH1_SRCADDR2 _SFR_MEM8(0x012A) -#define DMA_CH1_DESTADDR0 _SFR_MEM8(0x012C) -#define DMA_CH1_DESTADDR1 _SFR_MEM8(0x012D) -#define DMA_CH1_DESTADDR2 _SFR_MEM8(0x012E) -#define DMA_CH2_CTRLA _SFR_MEM8(0x0130) -#define DMA_CH2_CTRLB _SFR_MEM8(0x0131) -#define DMA_CH2_ADDRCTRL _SFR_MEM8(0x0132) -#define DMA_CH2_TRIGSRC _SFR_MEM8(0x0133) -#define DMA_CH2_TRFCNT _SFR_MEM16(0x0134) -#define DMA_CH2_REPCNT _SFR_MEM8(0x0136) -#define DMA_CH2_SRCADDR0 _SFR_MEM8(0x0138) -#define DMA_CH2_SRCADDR1 _SFR_MEM8(0x0139) -#define DMA_CH2_SRCADDR2 _SFR_MEM8(0x013A) -#define DMA_CH2_DESTADDR0 _SFR_MEM8(0x013C) -#define DMA_CH2_DESTADDR1 _SFR_MEM8(0x013D) -#define DMA_CH2_DESTADDR2 _SFR_MEM8(0x013E) -#define DMA_CH3_CTRLA _SFR_MEM8(0x0140) -#define DMA_CH3_CTRLB _SFR_MEM8(0x0141) -#define DMA_CH3_ADDRCTRL _SFR_MEM8(0x0142) -#define DMA_CH3_TRIGSRC _SFR_MEM8(0x0143) -#define DMA_CH3_TRFCNT _SFR_MEM16(0x0144) -#define DMA_CH3_REPCNT _SFR_MEM8(0x0146) -#define DMA_CH3_SRCADDR0 _SFR_MEM8(0x0148) -#define DMA_CH3_SRCADDR1 _SFR_MEM8(0x0149) -#define DMA_CH3_SRCADDR2 _SFR_MEM8(0x014A) -#define DMA_CH3_DESTADDR0 _SFR_MEM8(0x014C) -#define DMA_CH3_DESTADDR1 _SFR_MEM8(0x014D) -#define DMA_CH3_DESTADDR2 _SFR_MEM8(0x014E) - -/* EVSYS - Event System */ -#define EVSYS_CH0MUX _SFR_MEM8(0x0180) -#define EVSYS_CH1MUX _SFR_MEM8(0x0181) -#define EVSYS_CH2MUX _SFR_MEM8(0x0182) -#define EVSYS_CH3MUX _SFR_MEM8(0x0183) -#define EVSYS_CH4MUX _SFR_MEM8(0x0184) -#define EVSYS_CH5MUX _SFR_MEM8(0x0185) -#define EVSYS_CH6MUX _SFR_MEM8(0x0186) -#define EVSYS_CH7MUX _SFR_MEM8(0x0187) -#define EVSYS_CH0CTRL _SFR_MEM8(0x0188) -#define EVSYS_CH1CTRL _SFR_MEM8(0x0189) -#define EVSYS_CH2CTRL _SFR_MEM8(0x018A) -#define EVSYS_CH3CTRL _SFR_MEM8(0x018B) -#define EVSYS_CH4CTRL _SFR_MEM8(0x018C) -#define EVSYS_CH5CTRL _SFR_MEM8(0x018D) -#define EVSYS_CH6CTRL _SFR_MEM8(0x018E) -#define EVSYS_CH7CTRL _SFR_MEM8(0x018F) -#define EVSYS_STROBE _SFR_MEM8(0x0190) -#define EVSYS_DATA _SFR_MEM8(0x0191) - -/* NVM - Non-volatile Memory Controller */ -#define NVM_ADDR0 _SFR_MEM8(0x01C0) -#define NVM_ADDR1 _SFR_MEM8(0x01C1) -#define NVM_ADDR2 _SFR_MEM8(0x01C2) -#define NVM_DATA0 _SFR_MEM8(0x01C4) -#define NVM_DATA1 _SFR_MEM8(0x01C5) -#define NVM_DATA2 _SFR_MEM8(0x01C6) -#define NVM_CMD _SFR_MEM8(0x01CA) -#define NVM_CTRLA _SFR_MEM8(0x01CB) -#define NVM_CTRLB _SFR_MEM8(0x01CC) -#define NVM_INTCTRL _SFR_MEM8(0x01CD) -#define NVM_STATUS _SFR_MEM8(0x01CF) -#define NVM_LOCKBITS _SFR_MEM8(0x01D0) - -/* ADC - Analog-to-Digital Converter */ -#define ADCA_CTRLA _SFR_MEM8(0x0200) -#define ADCA_CTRLB _SFR_MEM8(0x0201) -#define ADCA_REFCTRL _SFR_MEM8(0x0202) -#define ADCA_EVCTRL _SFR_MEM8(0x0203) -#define ADCA_PRESCALER _SFR_MEM8(0x0204) -#define ADCA_INTFLAGS _SFR_MEM8(0x0206) -#define ADCA_TEMP _SFR_MEM8(0x0207) -#define ADCA_CAL _SFR_MEM16(0x020C) -#define ADCA_CH0RES _SFR_MEM16(0x0210) -#define ADCA_CH1RES _SFR_MEM16(0x0212) -#define ADCA_CH2RES _SFR_MEM16(0x0214) -#define ADCA_CH3RES _SFR_MEM16(0x0216) -#define ADCA_CMP _SFR_MEM16(0x0218) -#define ADCA_CH0_CTRL _SFR_MEM8(0x0220) -#define ADCA_CH0_MUXCTRL _SFR_MEM8(0x0221) -#define ADCA_CH0_INTCTRL _SFR_MEM8(0x0222) -#define ADCA_CH0_INTFLAGS _SFR_MEM8(0x0223) -#define ADCA_CH0_RES _SFR_MEM16(0x0224) -#define ADCA_CH0_SCAN _SFR_MEM8(0x0226) -#define ADCA_CH1_CTRL _SFR_MEM8(0x0228) -#define ADCA_CH1_MUXCTRL _SFR_MEM8(0x0229) -#define ADCA_CH1_INTCTRL _SFR_MEM8(0x022A) -#define ADCA_CH1_INTFLAGS _SFR_MEM8(0x022B) -#define ADCA_CH1_RES _SFR_MEM16(0x022C) -#define ADCA_CH1_SCAN _SFR_MEM8(0x022E) -#define ADCA_CH2_CTRL _SFR_MEM8(0x0230) -#define ADCA_CH2_MUXCTRL _SFR_MEM8(0x0231) -#define ADCA_CH2_INTCTRL _SFR_MEM8(0x0232) -#define ADCA_CH2_INTFLAGS _SFR_MEM8(0x0233) -#define ADCA_CH2_RES _SFR_MEM16(0x0234) -#define ADCA_CH2_SCAN _SFR_MEM8(0x0236) -#define ADCA_CH3_CTRL _SFR_MEM8(0x0238) -#define ADCA_CH3_MUXCTRL _SFR_MEM8(0x0239) -#define ADCA_CH3_INTCTRL _SFR_MEM8(0x023A) -#define ADCA_CH3_INTFLAGS _SFR_MEM8(0x023B) -#define ADCA_CH3_RES _SFR_MEM16(0x023C) -#define ADCA_CH3_SCAN _SFR_MEM8(0x023E) - -/* ADC - Analog-to-Digital Converter */ -#define ADCB_CTRLA _SFR_MEM8(0x0240) -#define ADCB_CTRLB _SFR_MEM8(0x0241) -#define ADCB_REFCTRL _SFR_MEM8(0x0242) -#define ADCB_EVCTRL _SFR_MEM8(0x0243) -#define ADCB_PRESCALER _SFR_MEM8(0x0244) -#define ADCB_INTFLAGS _SFR_MEM8(0x0246) -#define ADCB_TEMP _SFR_MEM8(0x0247) -#define ADCB_CAL _SFR_MEM16(0x024C) -#define ADCB_CH0RES _SFR_MEM16(0x0250) -#define ADCB_CH1RES _SFR_MEM16(0x0252) -#define ADCB_CH2RES _SFR_MEM16(0x0254) -#define ADCB_CH3RES _SFR_MEM16(0x0256) -#define ADCB_CMP _SFR_MEM16(0x0258) -#define ADCB_CH0_CTRL _SFR_MEM8(0x0260) -#define ADCB_CH0_MUXCTRL _SFR_MEM8(0x0261) -#define ADCB_CH0_INTCTRL _SFR_MEM8(0x0262) -#define ADCB_CH0_INTFLAGS _SFR_MEM8(0x0263) -#define ADCB_CH0_RES _SFR_MEM16(0x0264) -#define ADCB_CH0_SCAN _SFR_MEM8(0x0266) -#define ADCB_CH1_CTRL _SFR_MEM8(0x0268) -#define ADCB_CH1_MUXCTRL _SFR_MEM8(0x0269) -#define ADCB_CH1_INTCTRL _SFR_MEM8(0x026A) -#define ADCB_CH1_INTFLAGS _SFR_MEM8(0x026B) -#define ADCB_CH1_RES _SFR_MEM16(0x026C) -#define ADCB_CH1_SCAN _SFR_MEM8(0x026E) -#define ADCB_CH2_CTRL _SFR_MEM8(0x0270) -#define ADCB_CH2_MUXCTRL _SFR_MEM8(0x0271) -#define ADCB_CH2_INTCTRL _SFR_MEM8(0x0272) -#define ADCB_CH2_INTFLAGS _SFR_MEM8(0x0273) -#define ADCB_CH2_RES _SFR_MEM16(0x0274) -#define ADCB_CH2_SCAN _SFR_MEM8(0x0276) -#define ADCB_CH3_CTRL _SFR_MEM8(0x0278) -#define ADCB_CH3_MUXCTRL _SFR_MEM8(0x0279) -#define ADCB_CH3_INTCTRL _SFR_MEM8(0x027A) -#define ADCB_CH3_INTFLAGS _SFR_MEM8(0x027B) -#define ADCB_CH3_RES _SFR_MEM16(0x027C) -#define ADCB_CH3_SCAN _SFR_MEM8(0x027E) - -/* DAC - Digital-to-Analog Converter */ -#define DACB_CTRLA _SFR_MEM8(0x0320) -#define DACB_CTRLB _SFR_MEM8(0x0321) -#define DACB_CTRLC _SFR_MEM8(0x0322) -#define DACB_EVCTRL _SFR_MEM8(0x0323) -#define DACB_STATUS _SFR_MEM8(0x0325) -#define DACB_CH0GAINCAL _SFR_MEM8(0x0328) -#define DACB_CH0OFFSETCAL _SFR_MEM8(0x0329) -#define DACB_CH1GAINCAL _SFR_MEM8(0x032A) -#define DACB_CH1OFFSETCAL _SFR_MEM8(0x032B) -#define DACB_CH0DATA _SFR_MEM16(0x0338) -#define DACB_CH1DATA _SFR_MEM16(0x033A) - -/* AC - Analog Comparator */ -#define ACA_AC0CTRL _SFR_MEM8(0x0380) -#define ACA_AC1CTRL _SFR_MEM8(0x0381) -#define ACA_AC0MUXCTRL _SFR_MEM8(0x0382) -#define ACA_AC1MUXCTRL _SFR_MEM8(0x0383) -#define ACA_CTRLA _SFR_MEM8(0x0384) -#define ACA_CTRLB _SFR_MEM8(0x0385) -#define ACA_WINCTRL _SFR_MEM8(0x0386) -#define ACA_STATUS _SFR_MEM8(0x0387) - -/* AC - Analog Comparator */ -#define ACB_AC0CTRL _SFR_MEM8(0x0390) -#define ACB_AC1CTRL _SFR_MEM8(0x0391) -#define ACB_AC0MUXCTRL _SFR_MEM8(0x0392) -#define ACB_AC1MUXCTRL _SFR_MEM8(0x0393) -#define ACB_CTRLA _SFR_MEM8(0x0394) -#define ACB_CTRLB _SFR_MEM8(0x0395) -#define ACB_WINCTRL _SFR_MEM8(0x0396) -#define ACB_STATUS _SFR_MEM8(0x0397) - -/* RTC - Real-Time Counter */ -#define RTC_CTRL _SFR_MEM8(0x0400) -#define RTC_STATUS _SFR_MEM8(0x0401) -#define RTC_INTCTRL _SFR_MEM8(0x0402) -#define RTC_INTFLAGS _SFR_MEM8(0x0403) -#define RTC_TEMP _SFR_MEM8(0x0404) -#define RTC_CNT _SFR_MEM16(0x0408) -#define RTC_PER _SFR_MEM16(0x040A) -#define RTC_COMP _SFR_MEM16(0x040C) - -/* TWI - Two-Wire Interface */ -#define TWIC_CTRL _SFR_MEM8(0x0480) -#define TWIC_MASTER_CTRLA _SFR_MEM8(0x0481) -#define TWIC_MASTER_CTRLB _SFR_MEM8(0x0482) -#define TWIC_MASTER_CTRLC _SFR_MEM8(0x0483) -#define TWIC_MASTER_STATUS _SFR_MEM8(0x0484) -#define TWIC_MASTER_BAUD _SFR_MEM8(0x0485) -#define TWIC_MASTER_ADDR _SFR_MEM8(0x0486) -#define TWIC_MASTER_DATA _SFR_MEM8(0x0487) -#define TWIC_SLAVE_CTRLA _SFR_MEM8(0x0488) -#define TWIC_SLAVE_CTRLB _SFR_MEM8(0x0489) -#define TWIC_SLAVE_STATUS _SFR_MEM8(0x048A) -#define TWIC_SLAVE_ADDR _SFR_MEM8(0x048B) -#define TWIC_SLAVE_DATA _SFR_MEM8(0x048C) -#define TWIC_SLAVE_ADDRMASK _SFR_MEM8(0x048D) - -/* TWI - Two-Wire Interface */ -#define TWIE_CTRL _SFR_MEM8(0x04A0) -#define TWIE_MASTER_CTRLA _SFR_MEM8(0x04A1) -#define TWIE_MASTER_CTRLB _SFR_MEM8(0x04A2) -#define TWIE_MASTER_CTRLC _SFR_MEM8(0x04A3) -#define TWIE_MASTER_STATUS _SFR_MEM8(0x04A4) -#define TWIE_MASTER_BAUD _SFR_MEM8(0x04A5) -#define TWIE_MASTER_ADDR _SFR_MEM8(0x04A6) -#define TWIE_MASTER_DATA _SFR_MEM8(0x04A7) -#define TWIE_SLAVE_CTRLA _SFR_MEM8(0x04A8) -#define TWIE_SLAVE_CTRLB _SFR_MEM8(0x04A9) -#define TWIE_SLAVE_STATUS _SFR_MEM8(0x04AA) -#define TWIE_SLAVE_ADDR _SFR_MEM8(0x04AB) -#define TWIE_SLAVE_DATA _SFR_MEM8(0x04AC) -#define TWIE_SLAVE_ADDRMASK _SFR_MEM8(0x04AD) - -/* USB - Universal Serial Bus */ -#define USB_CTRLA _SFR_MEM8(0x04C0) -#define USB_CTRLB _SFR_MEM8(0x04C1) -#define USB_STATUS _SFR_MEM8(0x04C2) -#define USB_ADDR _SFR_MEM8(0x04C3) -#define USB_FIFOWP _SFR_MEM8(0x04C4) -#define USB_FIFORP _SFR_MEM8(0x04C5) -#define USB_EPPTR _SFR_MEM16(0x04C6) -#define USB_INTCTRLA _SFR_MEM8(0x04C8) -#define USB_INTCTRLB _SFR_MEM8(0x04C9) -#define USB_INTFLAGSACLR _SFR_MEM8(0x04CA) -#define USB_INTFLAGSASET _SFR_MEM8(0x04CB) -#define USB_INTFLAGSBCLR _SFR_MEM8(0x04CC) -#define USB_INTFLAGSBSET _SFR_MEM8(0x04CD) -#define USB_CAL0 _SFR_MEM8(0x04FA) -#define USB_CAL1 _SFR_MEM8(0x04FB) - -/* PORT - I/O Ports */ -#define PORTA_DIR _SFR_MEM8(0x0600) -#define PORTA_DIRSET _SFR_MEM8(0x0601) -#define PORTA_DIRCLR _SFR_MEM8(0x0602) -#define PORTA_DIRTGL _SFR_MEM8(0x0603) -#define PORTA_OUT _SFR_MEM8(0x0604) -#define PORTA_OUTSET _SFR_MEM8(0x0605) -#define PORTA_OUTCLR _SFR_MEM8(0x0606) -#define PORTA_OUTTGL _SFR_MEM8(0x0607) -#define PORTA_IN _SFR_MEM8(0x0608) -#define PORTA_INTCTRL _SFR_MEM8(0x0609) -#define PORTA_INT0MASK _SFR_MEM8(0x060A) -#define PORTA_INT1MASK _SFR_MEM8(0x060B) -#define PORTA_INTFLAGS _SFR_MEM8(0x060C) -#define PORTA_REMAP _SFR_MEM8(0x060E) -#define PORTA_PIN0CTRL _SFR_MEM8(0x0610) -#define PORTA_PIN1CTRL _SFR_MEM8(0x0611) -#define PORTA_PIN2CTRL _SFR_MEM8(0x0612) -#define PORTA_PIN3CTRL _SFR_MEM8(0x0613) -#define PORTA_PIN4CTRL _SFR_MEM8(0x0614) -#define PORTA_PIN5CTRL _SFR_MEM8(0x0615) -#define PORTA_PIN6CTRL _SFR_MEM8(0x0616) -#define PORTA_PIN7CTRL _SFR_MEM8(0x0617) - -/* PORT - I/O Ports */ -#define PORTB_DIR _SFR_MEM8(0x0620) -#define PORTB_DIRSET _SFR_MEM8(0x0621) -#define PORTB_DIRCLR _SFR_MEM8(0x0622) -#define PORTB_DIRTGL _SFR_MEM8(0x0623) -#define PORTB_OUT _SFR_MEM8(0x0624) -#define PORTB_OUTSET _SFR_MEM8(0x0625) -#define PORTB_OUTCLR _SFR_MEM8(0x0626) -#define PORTB_OUTTGL _SFR_MEM8(0x0627) -#define PORTB_IN _SFR_MEM8(0x0628) -#define PORTB_INTCTRL _SFR_MEM8(0x0629) -#define PORTB_INT0MASK _SFR_MEM8(0x062A) -#define PORTB_INT1MASK _SFR_MEM8(0x062B) -#define PORTB_INTFLAGS _SFR_MEM8(0x062C) -#define PORTB_REMAP _SFR_MEM8(0x062E) -#define PORTB_PIN0CTRL _SFR_MEM8(0x0630) -#define PORTB_PIN1CTRL _SFR_MEM8(0x0631) -#define PORTB_PIN2CTRL _SFR_MEM8(0x0632) -#define PORTB_PIN3CTRL _SFR_MEM8(0x0633) -#define PORTB_PIN4CTRL _SFR_MEM8(0x0634) -#define PORTB_PIN5CTRL _SFR_MEM8(0x0635) -#define PORTB_PIN6CTRL _SFR_MEM8(0x0636) -#define PORTB_PIN7CTRL _SFR_MEM8(0x0637) - -/* PORT - I/O Ports */ -#define PORTC_DIR _SFR_MEM8(0x0640) -#define PORTC_DIRSET _SFR_MEM8(0x0641) -#define PORTC_DIRCLR _SFR_MEM8(0x0642) -#define PORTC_DIRTGL _SFR_MEM8(0x0643) -#define PORTC_OUT _SFR_MEM8(0x0644) -#define PORTC_OUTSET _SFR_MEM8(0x0645) -#define PORTC_OUTCLR _SFR_MEM8(0x0646) -#define PORTC_OUTTGL _SFR_MEM8(0x0647) -#define PORTC_IN _SFR_MEM8(0x0648) -#define PORTC_INTCTRL _SFR_MEM8(0x0649) -#define PORTC_INT0MASK _SFR_MEM8(0x064A) -#define PORTC_INT1MASK _SFR_MEM8(0x064B) -#define PORTC_INTFLAGS _SFR_MEM8(0x064C) -#define PORTC_REMAP _SFR_MEM8(0x064E) -#define PORTC_PIN0CTRL _SFR_MEM8(0x0650) -#define PORTC_PIN1CTRL _SFR_MEM8(0x0651) -#define PORTC_PIN2CTRL _SFR_MEM8(0x0652) -#define PORTC_PIN3CTRL _SFR_MEM8(0x0653) -#define PORTC_PIN4CTRL _SFR_MEM8(0x0654) -#define PORTC_PIN5CTRL _SFR_MEM8(0x0655) -#define PORTC_PIN6CTRL _SFR_MEM8(0x0656) -#define PORTC_PIN7CTRL _SFR_MEM8(0x0657) - -/* PORT - I/O Ports */ -#define PORTD_DIR _SFR_MEM8(0x0660) -#define PORTD_DIRSET _SFR_MEM8(0x0661) -#define PORTD_DIRCLR _SFR_MEM8(0x0662) -#define PORTD_DIRTGL _SFR_MEM8(0x0663) -#define PORTD_OUT _SFR_MEM8(0x0664) -#define PORTD_OUTSET _SFR_MEM8(0x0665) -#define PORTD_OUTCLR _SFR_MEM8(0x0666) -#define PORTD_OUTTGL _SFR_MEM8(0x0667) -#define PORTD_IN _SFR_MEM8(0x0668) -#define PORTD_INTCTRL _SFR_MEM8(0x0669) -#define PORTD_INT0MASK _SFR_MEM8(0x066A) -#define PORTD_INT1MASK _SFR_MEM8(0x066B) -#define PORTD_INTFLAGS _SFR_MEM8(0x066C) -#define PORTD_REMAP _SFR_MEM8(0x066E) -#define PORTD_PIN0CTRL _SFR_MEM8(0x0670) -#define PORTD_PIN1CTRL _SFR_MEM8(0x0671) -#define PORTD_PIN2CTRL _SFR_MEM8(0x0672) -#define PORTD_PIN3CTRL _SFR_MEM8(0x0673) -#define PORTD_PIN4CTRL _SFR_MEM8(0x0674) -#define PORTD_PIN5CTRL _SFR_MEM8(0x0675) -#define PORTD_PIN6CTRL _SFR_MEM8(0x0676) -#define PORTD_PIN7CTRL _SFR_MEM8(0x0677) - -/* PORT - I/O Ports */ -#define PORTE_DIR _SFR_MEM8(0x0680) -#define PORTE_DIRSET _SFR_MEM8(0x0681) -#define PORTE_DIRCLR _SFR_MEM8(0x0682) -#define PORTE_DIRTGL _SFR_MEM8(0x0683) -#define PORTE_OUT _SFR_MEM8(0x0684) -#define PORTE_OUTSET _SFR_MEM8(0x0685) -#define PORTE_OUTCLR _SFR_MEM8(0x0686) -#define PORTE_OUTTGL _SFR_MEM8(0x0687) -#define PORTE_IN _SFR_MEM8(0x0688) -#define PORTE_INTCTRL _SFR_MEM8(0x0689) -#define PORTE_INT0MASK _SFR_MEM8(0x068A) -#define PORTE_INT1MASK _SFR_MEM8(0x068B) -#define PORTE_INTFLAGS _SFR_MEM8(0x068C) -#define PORTE_REMAP _SFR_MEM8(0x068E) -#define PORTE_PIN0CTRL _SFR_MEM8(0x0690) -#define PORTE_PIN1CTRL _SFR_MEM8(0x0691) -#define PORTE_PIN2CTRL _SFR_MEM8(0x0692) -#define PORTE_PIN3CTRL _SFR_MEM8(0x0693) -#define PORTE_PIN4CTRL _SFR_MEM8(0x0694) -#define PORTE_PIN5CTRL _SFR_MEM8(0x0695) -#define PORTE_PIN6CTRL _SFR_MEM8(0x0696) -#define PORTE_PIN7CTRL _SFR_MEM8(0x0697) - -/* PORT - I/O Ports */ -#define PORTF_DIR _SFR_MEM8(0x06A0) -#define PORTF_DIRSET _SFR_MEM8(0x06A1) -#define PORTF_DIRCLR _SFR_MEM8(0x06A2) -#define PORTF_DIRTGL _SFR_MEM8(0x06A3) -#define PORTF_OUT _SFR_MEM8(0x06A4) -#define PORTF_OUTSET _SFR_MEM8(0x06A5) -#define PORTF_OUTCLR _SFR_MEM8(0x06A6) -#define PORTF_OUTTGL _SFR_MEM8(0x06A7) -#define PORTF_IN _SFR_MEM8(0x06A8) -#define PORTF_INTCTRL _SFR_MEM8(0x06A9) -#define PORTF_INT0MASK _SFR_MEM8(0x06AA) -#define PORTF_INT1MASK _SFR_MEM8(0x06AB) -#define PORTF_INTFLAGS _SFR_MEM8(0x06AC) -#define PORTF_REMAP _SFR_MEM8(0x06AE) -#define PORTF_PIN0CTRL _SFR_MEM8(0x06B0) -#define PORTF_PIN1CTRL _SFR_MEM8(0x06B1) -#define PORTF_PIN2CTRL _SFR_MEM8(0x06B2) -#define PORTF_PIN3CTRL _SFR_MEM8(0x06B3) -#define PORTF_PIN4CTRL _SFR_MEM8(0x06B4) -#define PORTF_PIN5CTRL _SFR_MEM8(0x06B5) -#define PORTF_PIN6CTRL _SFR_MEM8(0x06B6) -#define PORTF_PIN7CTRL _SFR_MEM8(0x06B7) - -/* PORT - I/O Ports */ -#define PORTR_DIR _SFR_MEM8(0x07E0) -#define PORTR_DIRSET _SFR_MEM8(0x07E1) -#define PORTR_DIRCLR _SFR_MEM8(0x07E2) -#define PORTR_DIRTGL _SFR_MEM8(0x07E3) -#define PORTR_OUT _SFR_MEM8(0x07E4) -#define PORTR_OUTSET _SFR_MEM8(0x07E5) -#define PORTR_OUTCLR _SFR_MEM8(0x07E6) -#define PORTR_OUTTGL _SFR_MEM8(0x07E7) -#define PORTR_IN _SFR_MEM8(0x07E8) -#define PORTR_INTCTRL _SFR_MEM8(0x07E9) -#define PORTR_INT0MASK _SFR_MEM8(0x07EA) -#define PORTR_INT1MASK _SFR_MEM8(0x07EB) -#define PORTR_INTFLAGS _SFR_MEM8(0x07EC) -#define PORTR_REMAP _SFR_MEM8(0x07EE) -#define PORTR_PIN0CTRL _SFR_MEM8(0x07F0) -#define PORTR_PIN1CTRL _SFR_MEM8(0x07F1) -#define PORTR_PIN2CTRL _SFR_MEM8(0x07F2) -#define PORTR_PIN3CTRL _SFR_MEM8(0x07F3) -#define PORTR_PIN4CTRL _SFR_MEM8(0x07F4) -#define PORTR_PIN5CTRL _SFR_MEM8(0x07F5) -#define PORTR_PIN6CTRL _SFR_MEM8(0x07F6) -#define PORTR_PIN7CTRL _SFR_MEM8(0x07F7) - -/* TC0 - 16-bit Timer/Counter 0 */ -#define TCC0_CTRLA _SFR_MEM8(0x0800) -#define TCC0_CTRLB _SFR_MEM8(0x0801) -#define TCC0_CTRLC _SFR_MEM8(0x0802) -#define TCC0_CTRLD _SFR_MEM8(0x0803) -#define TCC0_CTRLE _SFR_MEM8(0x0804) -#define TCC0_INTCTRLA _SFR_MEM8(0x0806) -#define TCC0_INTCTRLB _SFR_MEM8(0x0807) -#define TCC0_CTRLFCLR _SFR_MEM8(0x0808) -#define TCC0_CTRLFSET _SFR_MEM8(0x0809) -#define TCC0_CTRLGCLR _SFR_MEM8(0x080A) -#define TCC0_CTRLGSET _SFR_MEM8(0x080B) -#define TCC0_INTFLAGS _SFR_MEM8(0x080C) -#define TCC0_TEMP _SFR_MEM8(0x080F) -#define TCC0_CNT _SFR_MEM16(0x0820) -#define TCC0_PER _SFR_MEM16(0x0826) -#define TCC0_CCA _SFR_MEM16(0x0828) -#define TCC0_CCB _SFR_MEM16(0x082A) -#define TCC0_CCC _SFR_MEM16(0x082C) -#define TCC0_CCD _SFR_MEM16(0x082E) -#define TCC0_PERBUF _SFR_MEM16(0x0836) -#define TCC0_CCABUF _SFR_MEM16(0x0838) -#define TCC0_CCBBUF _SFR_MEM16(0x083A) -#define TCC0_CCCBUF _SFR_MEM16(0x083C) -#define TCC0_CCDBUF _SFR_MEM16(0x083E) - -/* TC2 - 16-bit Timer/Counter type 2 */ -#define TCC2_CTRLA _SFR_MEM8(0x0800) -#define TCC2_CTRLB _SFR_MEM8(0x0801) -#define TCC2_CTRLC _SFR_MEM8(0x0802) -#define TCC2_CTRLE _SFR_MEM8(0x0804) -#define TCC2_INTCTRLA _SFR_MEM8(0x0806) -#define TCC2_INTCTRLB _SFR_MEM8(0x0807) -#define TCC2_CTRLF _SFR_MEM8(0x0809) -#define TCC2_INTFLAGS _SFR_MEM8(0x080C) -#define TCC2_LCNT _SFR_MEM8(0x0820) -#define TCC2_HCNT _SFR_MEM8(0x0821) -#define TCC2_LPER _SFR_MEM8(0x0826) -#define TCC2_HPER _SFR_MEM8(0x0827) -#define TCC2_LCMPA _SFR_MEM8(0x0828) -#define TCC2_HCMPA _SFR_MEM8(0x0829) -#define TCC2_LCMPB _SFR_MEM8(0x082A) -#define TCC2_HCMPB _SFR_MEM8(0x082B) -#define TCC2_LCMPC _SFR_MEM8(0x082C) -#define TCC2_HCMPC _SFR_MEM8(0x082D) -#define TCC2_LCMPD _SFR_MEM8(0x082E) -#define TCC2_HCMPD _SFR_MEM8(0x082F) - -/* TC1 - 16-bit Timer/Counter 1 */ -#define TCC1_CTRLA _SFR_MEM8(0x0840) -#define TCC1_CTRLB _SFR_MEM8(0x0841) -#define TCC1_CTRLC _SFR_MEM8(0x0842) -#define TCC1_CTRLD _SFR_MEM8(0x0843) -#define TCC1_CTRLE _SFR_MEM8(0x0844) -#define TCC1_INTCTRLA _SFR_MEM8(0x0846) -#define TCC1_INTCTRLB _SFR_MEM8(0x0847) -#define TCC1_CTRLFCLR _SFR_MEM8(0x0848) -#define TCC1_CTRLFSET _SFR_MEM8(0x0849) -#define TCC1_CTRLGCLR _SFR_MEM8(0x084A) -#define TCC1_CTRLGSET _SFR_MEM8(0x084B) -#define TCC1_INTFLAGS _SFR_MEM8(0x084C) -#define TCC1_TEMP _SFR_MEM8(0x084F) -#define TCC1_CNT _SFR_MEM16(0x0860) -#define TCC1_PER _SFR_MEM16(0x0866) -#define TCC1_CCA _SFR_MEM16(0x0868) -#define TCC1_CCB _SFR_MEM16(0x086A) -#define TCC1_PERBUF _SFR_MEM16(0x0876) -#define TCC1_CCABUF _SFR_MEM16(0x0878) -#define TCC1_CCBBUF _SFR_MEM16(0x087A) - -/* AWEX - Advanced Waveform Extension */ -#define AWEXC_CTRL _SFR_MEM8(0x0880) -#define AWEXC_FDEMASK _SFR_MEM8(0x0882) -#define AWEXC_FDCTRL _SFR_MEM8(0x0883) -#define AWEXC_STATUS _SFR_MEM8(0x0884) -#define AWEXC_STATUSSET _SFR_MEM8(0x0885) -#define AWEXC_DTBOTH _SFR_MEM8(0x0886) -#define AWEXC_DTBOTHBUF _SFR_MEM8(0x0887) -#define AWEXC_DTLS _SFR_MEM8(0x0888) -#define AWEXC_DTHS _SFR_MEM8(0x0889) -#define AWEXC_DTLSBUF _SFR_MEM8(0x088A) -#define AWEXC_DTHSBUF _SFR_MEM8(0x088B) -#define AWEXC_OUTOVEN _SFR_MEM8(0x088C) - -/* HIRES - High-Resolution Extension */ -#define HIRESC_CTRLA _SFR_MEM8(0x0890) - -/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ -#define USARTC0_DATA _SFR_MEM8(0x08A0) -#define USARTC0_STATUS _SFR_MEM8(0x08A1) -#define USARTC0_CTRLA _SFR_MEM8(0x08A3) -#define USARTC0_CTRLB _SFR_MEM8(0x08A4) -#define USARTC0_CTRLC _SFR_MEM8(0x08A5) -#define USARTC0_BAUDCTRLA _SFR_MEM8(0x08A6) -#define USARTC0_BAUDCTRLB _SFR_MEM8(0x08A7) - -/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ -#define USARTC1_DATA _SFR_MEM8(0x08B0) -#define USARTC1_STATUS _SFR_MEM8(0x08B1) -#define USARTC1_CTRLA _SFR_MEM8(0x08B3) -#define USARTC1_CTRLB _SFR_MEM8(0x08B4) -#define USARTC1_CTRLC _SFR_MEM8(0x08B5) -#define USARTC1_BAUDCTRLA _SFR_MEM8(0x08B6) -#define USARTC1_BAUDCTRLB _SFR_MEM8(0x08B7) - -/* SPI - Serial Peripheral Interface */ -#define SPIC_CTRL _SFR_MEM8(0x08C0) -#define SPIC_INTCTRL _SFR_MEM8(0x08C1) -#define SPIC_STATUS _SFR_MEM8(0x08C2) -#define SPIC_DATA _SFR_MEM8(0x08C3) - -/* IRCOM - IR Communication Module */ -#define IRCOM_CTRL _SFR_MEM8(0x08F8) -#define IRCOM_TXPLCTRL _SFR_MEM8(0x08F9) -#define IRCOM_RXPLCTRL _SFR_MEM8(0x08FA) - -/* TC0 - 16-bit Timer/Counter 0 */ -#define TCD0_CTRLA _SFR_MEM8(0x0900) -#define TCD0_CTRLB _SFR_MEM8(0x0901) -#define TCD0_CTRLC _SFR_MEM8(0x0902) -#define TCD0_CTRLD _SFR_MEM8(0x0903) -#define TCD0_CTRLE _SFR_MEM8(0x0904) -#define TCD0_INTCTRLA _SFR_MEM8(0x0906) -#define TCD0_INTCTRLB _SFR_MEM8(0x0907) -#define TCD0_CTRLFCLR _SFR_MEM8(0x0908) -#define TCD0_CTRLFSET _SFR_MEM8(0x0909) -#define TCD0_CTRLGCLR _SFR_MEM8(0x090A) -#define TCD0_CTRLGSET _SFR_MEM8(0x090B) -#define TCD0_INTFLAGS _SFR_MEM8(0x090C) -#define TCD0_TEMP _SFR_MEM8(0x090F) -#define TCD0_CNT _SFR_MEM16(0x0920) -#define TCD0_PER _SFR_MEM16(0x0926) -#define TCD0_CCA _SFR_MEM16(0x0928) -#define TCD0_CCB _SFR_MEM16(0x092A) -#define TCD0_CCC _SFR_MEM16(0x092C) -#define TCD0_CCD _SFR_MEM16(0x092E) -#define TCD0_PERBUF _SFR_MEM16(0x0936) -#define TCD0_CCABUF _SFR_MEM16(0x0938) -#define TCD0_CCBBUF _SFR_MEM16(0x093A) -#define TCD0_CCCBUF _SFR_MEM16(0x093C) -#define TCD0_CCDBUF _SFR_MEM16(0x093E) - -/* TC2 - 16-bit Timer/Counter type 2 */ -#define TCD2_CTRLA _SFR_MEM8(0x0900) -#define TCD2_CTRLB _SFR_MEM8(0x0901) -#define TCD2_CTRLC _SFR_MEM8(0x0902) -#define TCD2_CTRLE _SFR_MEM8(0x0904) -#define TCD2_INTCTRLA _SFR_MEM8(0x0906) -#define TCD2_INTCTRLB _SFR_MEM8(0x0907) -#define TCD2_CTRLF _SFR_MEM8(0x0909) -#define TCD2_INTFLAGS _SFR_MEM8(0x090C) -#define TCD2_LCNT _SFR_MEM8(0x0920) -#define TCD2_HCNT _SFR_MEM8(0x0921) -#define TCD2_LPER _SFR_MEM8(0x0926) -#define TCD2_HPER _SFR_MEM8(0x0927) -#define TCD2_LCMPA _SFR_MEM8(0x0928) -#define TCD2_HCMPA _SFR_MEM8(0x0929) -#define TCD2_LCMPB _SFR_MEM8(0x092A) -#define TCD2_HCMPB _SFR_MEM8(0x092B) -#define TCD2_LCMPC _SFR_MEM8(0x092C) -#define TCD2_HCMPC _SFR_MEM8(0x092D) -#define TCD2_LCMPD _SFR_MEM8(0x092E) -#define TCD2_HCMPD _SFR_MEM8(0x092F) - -/* TC1 - 16-bit Timer/Counter 1 */ -#define TCD1_CTRLA _SFR_MEM8(0x0940) -#define TCD1_CTRLB _SFR_MEM8(0x0941) -#define TCD1_CTRLC _SFR_MEM8(0x0942) -#define TCD1_CTRLD _SFR_MEM8(0x0943) -#define TCD1_CTRLE _SFR_MEM8(0x0944) -#define TCD1_INTCTRLA _SFR_MEM8(0x0946) -#define TCD1_INTCTRLB _SFR_MEM8(0x0947) -#define TCD1_CTRLFCLR _SFR_MEM8(0x0948) -#define TCD1_CTRLFSET _SFR_MEM8(0x0949) -#define TCD1_CTRLGCLR _SFR_MEM8(0x094A) -#define TCD1_CTRLGSET _SFR_MEM8(0x094B) -#define TCD1_INTFLAGS _SFR_MEM8(0x094C) -#define TCD1_TEMP _SFR_MEM8(0x094F) -#define TCD1_CNT _SFR_MEM16(0x0960) -#define TCD1_PER _SFR_MEM16(0x0966) -#define TCD1_CCA _SFR_MEM16(0x0968) -#define TCD1_CCB _SFR_MEM16(0x096A) -#define TCD1_PERBUF _SFR_MEM16(0x0976) -#define TCD1_CCABUF _SFR_MEM16(0x0978) -#define TCD1_CCBBUF _SFR_MEM16(0x097A) - -/* HIRES - High-Resolution Extension */ -#define HIRESD_CTRLA _SFR_MEM8(0x0990) - -/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ -#define USARTD0_DATA _SFR_MEM8(0x09A0) -#define USARTD0_STATUS _SFR_MEM8(0x09A1) -#define USARTD0_CTRLA _SFR_MEM8(0x09A3) -#define USARTD0_CTRLB _SFR_MEM8(0x09A4) -#define USARTD0_CTRLC _SFR_MEM8(0x09A5) -#define USARTD0_BAUDCTRLA _SFR_MEM8(0x09A6) -#define USARTD0_BAUDCTRLB _SFR_MEM8(0x09A7) - -/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ -#define USARTD1_DATA _SFR_MEM8(0x09B0) -#define USARTD1_STATUS _SFR_MEM8(0x09B1) -#define USARTD1_CTRLA _SFR_MEM8(0x09B3) -#define USARTD1_CTRLB _SFR_MEM8(0x09B4) -#define USARTD1_CTRLC _SFR_MEM8(0x09B5) -#define USARTD1_BAUDCTRLA _SFR_MEM8(0x09B6) -#define USARTD1_BAUDCTRLB _SFR_MEM8(0x09B7) - -/* SPI - Serial Peripheral Interface */ -#define SPID_CTRL _SFR_MEM8(0x09C0) -#define SPID_INTCTRL _SFR_MEM8(0x09C1) -#define SPID_STATUS _SFR_MEM8(0x09C2) -#define SPID_DATA _SFR_MEM8(0x09C3) - -/* TC0 - 16-bit Timer/Counter 0 */ -#define TCE0_CTRLA _SFR_MEM8(0x0A00) -#define TCE0_CTRLB _SFR_MEM8(0x0A01) -#define TCE0_CTRLC _SFR_MEM8(0x0A02) -#define TCE0_CTRLD _SFR_MEM8(0x0A03) -#define TCE0_CTRLE _SFR_MEM8(0x0A04) -#define TCE0_INTCTRLA _SFR_MEM8(0x0A06) -#define TCE0_INTCTRLB _SFR_MEM8(0x0A07) -#define TCE0_CTRLFCLR _SFR_MEM8(0x0A08) -#define TCE0_CTRLFSET _SFR_MEM8(0x0A09) -#define TCE0_CTRLGCLR _SFR_MEM8(0x0A0A) -#define TCE0_CTRLGSET _SFR_MEM8(0x0A0B) -#define TCE0_INTFLAGS _SFR_MEM8(0x0A0C) -#define TCE0_TEMP _SFR_MEM8(0x0A0F) -#define TCE0_CNT _SFR_MEM16(0x0A20) -#define TCE0_PER _SFR_MEM16(0x0A26) -#define TCE0_CCA _SFR_MEM16(0x0A28) -#define TCE0_CCB _SFR_MEM16(0x0A2A) -#define TCE0_CCC _SFR_MEM16(0x0A2C) -#define TCE0_CCD _SFR_MEM16(0x0A2E) -#define TCE0_PERBUF _SFR_MEM16(0x0A36) -#define TCE0_CCABUF _SFR_MEM16(0x0A38) -#define TCE0_CCBBUF _SFR_MEM16(0x0A3A) -#define TCE0_CCCBUF _SFR_MEM16(0x0A3C) -#define TCE0_CCDBUF _SFR_MEM16(0x0A3E) - -/* TC2 - 16-bit Timer/Counter type 2 */ -#define TCE2_CTRLA _SFR_MEM8(0x0A00) -#define TCE2_CTRLB _SFR_MEM8(0x0A01) -#define TCE2_CTRLC _SFR_MEM8(0x0A02) -#define TCE2_CTRLE _SFR_MEM8(0x0A04) -#define TCE2_INTCTRLA _SFR_MEM8(0x0A06) -#define TCE2_INTCTRLB _SFR_MEM8(0x0A07) -#define TCE2_CTRLF _SFR_MEM8(0x0A09) -#define TCE2_INTFLAGS _SFR_MEM8(0x0A0C) -#define TCE2_LCNT _SFR_MEM8(0x0A20) -#define TCE2_HCNT _SFR_MEM8(0x0A21) -#define TCE2_LPER _SFR_MEM8(0x0A26) -#define TCE2_HPER _SFR_MEM8(0x0A27) -#define TCE2_LCMPA _SFR_MEM8(0x0A28) -#define TCE2_HCMPA _SFR_MEM8(0x0A29) -#define TCE2_LCMPB _SFR_MEM8(0x0A2A) -#define TCE2_HCMPB _SFR_MEM8(0x0A2B) -#define TCE2_LCMPC _SFR_MEM8(0x0A2C) -#define TCE2_HCMPC _SFR_MEM8(0x0A2D) -#define TCE2_LCMPD _SFR_MEM8(0x0A2E) -#define TCE2_HCMPD _SFR_MEM8(0x0A2F) - -/* TC1 - 16-bit Timer/Counter 1 */ -#define TCE1_CTRLA _SFR_MEM8(0x0A40) -#define TCE1_CTRLB _SFR_MEM8(0x0A41) -#define TCE1_CTRLC _SFR_MEM8(0x0A42) -#define TCE1_CTRLD _SFR_MEM8(0x0A43) -#define TCE1_CTRLE _SFR_MEM8(0x0A44) -#define TCE1_INTCTRLA _SFR_MEM8(0x0A46) -#define TCE1_INTCTRLB _SFR_MEM8(0x0A47) -#define TCE1_CTRLFCLR _SFR_MEM8(0x0A48) -#define TCE1_CTRLFSET _SFR_MEM8(0x0A49) -#define TCE1_CTRLGCLR _SFR_MEM8(0x0A4A) -#define TCE1_CTRLGSET _SFR_MEM8(0x0A4B) -#define TCE1_INTFLAGS _SFR_MEM8(0x0A4C) -#define TCE1_TEMP _SFR_MEM8(0x0A4F) -#define TCE1_CNT _SFR_MEM16(0x0A60) -#define TCE1_PER _SFR_MEM16(0x0A66) -#define TCE1_CCA _SFR_MEM16(0x0A68) -#define TCE1_CCB _SFR_MEM16(0x0A6A) -#define TCE1_PERBUF _SFR_MEM16(0x0A76) -#define TCE1_CCABUF _SFR_MEM16(0x0A78) -#define TCE1_CCBBUF _SFR_MEM16(0x0A7A) - -/* AWEX - Advanced Waveform Extension */ -#define AWEXE_CTRL _SFR_MEM8(0x0A80) -#define AWEXE_FDEMASK _SFR_MEM8(0x0A82) -#define AWEXE_FDCTRL _SFR_MEM8(0x0A83) -#define AWEXE_STATUS _SFR_MEM8(0x0A84) -#define AWEXE_STATUSSET _SFR_MEM8(0x0A85) -#define AWEXE_DTBOTH _SFR_MEM8(0x0A86) -#define AWEXE_DTBOTHBUF _SFR_MEM8(0x0A87) -#define AWEXE_DTLS _SFR_MEM8(0x0A88) -#define AWEXE_DTHS _SFR_MEM8(0x0A89) -#define AWEXE_DTLSBUF _SFR_MEM8(0x0A8A) -#define AWEXE_DTHSBUF _SFR_MEM8(0x0A8B) -#define AWEXE_OUTOVEN _SFR_MEM8(0x0A8C) - -/* HIRES - High-Resolution Extension */ -#define HIRESE_CTRLA _SFR_MEM8(0x0A90) - -/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ -#define USARTE0_DATA _SFR_MEM8(0x0AA0) -#define USARTE0_STATUS _SFR_MEM8(0x0AA1) -#define USARTE0_CTRLA _SFR_MEM8(0x0AA3) -#define USARTE0_CTRLB _SFR_MEM8(0x0AA4) -#define USARTE0_CTRLC _SFR_MEM8(0x0AA5) -#define USARTE0_BAUDCTRLA _SFR_MEM8(0x0AA6) -#define USARTE0_BAUDCTRLB _SFR_MEM8(0x0AA7) - -/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ -#define USARTE1_DATA _SFR_MEM8(0x0AB0) -#define USARTE1_STATUS _SFR_MEM8(0x0AB1) -#define USARTE1_CTRLA _SFR_MEM8(0x0AB3) -#define USARTE1_CTRLB _SFR_MEM8(0x0AB4) -#define USARTE1_CTRLC _SFR_MEM8(0x0AB5) -#define USARTE1_BAUDCTRLA _SFR_MEM8(0x0AB6) -#define USARTE1_BAUDCTRLB _SFR_MEM8(0x0AB7) - -/* SPI - Serial Peripheral Interface */ -#define SPIE_CTRL _SFR_MEM8(0x0AC0) -#define SPIE_INTCTRL _SFR_MEM8(0x0AC1) -#define SPIE_STATUS _SFR_MEM8(0x0AC2) -#define SPIE_DATA _SFR_MEM8(0x0AC3) - -/* TC0 - 16-bit Timer/Counter 0 */ -#define TCF0_CTRLA _SFR_MEM8(0x0B00) -#define TCF0_CTRLB _SFR_MEM8(0x0B01) -#define TCF0_CTRLC _SFR_MEM8(0x0B02) -#define TCF0_CTRLD _SFR_MEM8(0x0B03) -#define TCF0_CTRLE _SFR_MEM8(0x0B04) -#define TCF0_INTCTRLA _SFR_MEM8(0x0B06) -#define TCF0_INTCTRLB _SFR_MEM8(0x0B07) -#define TCF0_CTRLFCLR _SFR_MEM8(0x0B08) -#define TCF0_CTRLFSET _SFR_MEM8(0x0B09) -#define TCF0_CTRLGCLR _SFR_MEM8(0x0B0A) -#define TCF0_CTRLGSET _SFR_MEM8(0x0B0B) -#define TCF0_INTFLAGS _SFR_MEM8(0x0B0C) -#define TCF0_TEMP _SFR_MEM8(0x0B0F) -#define TCF0_CNT _SFR_MEM16(0x0B20) -#define TCF0_PER _SFR_MEM16(0x0B26) -#define TCF0_CCA _SFR_MEM16(0x0B28) -#define TCF0_CCB _SFR_MEM16(0x0B2A) -#define TCF0_CCC _SFR_MEM16(0x0B2C) -#define TCF0_CCD _SFR_MEM16(0x0B2E) -#define TCF0_PERBUF _SFR_MEM16(0x0B36) -#define TCF0_CCABUF _SFR_MEM16(0x0B38) -#define TCF0_CCBBUF _SFR_MEM16(0x0B3A) -#define TCF0_CCCBUF _SFR_MEM16(0x0B3C) -#define TCF0_CCDBUF _SFR_MEM16(0x0B3E) - -/* TC2 - 16-bit Timer/Counter type 2 */ -#define TCF2_CTRLA _SFR_MEM8(0x0B00) -#define TCF2_CTRLB _SFR_MEM8(0x0B01) -#define TCF2_CTRLC _SFR_MEM8(0x0B02) -#define TCF2_CTRLE _SFR_MEM8(0x0B04) -#define TCF2_INTCTRLA _SFR_MEM8(0x0B06) -#define TCF2_INTCTRLB _SFR_MEM8(0x0B07) -#define TCF2_CTRLF _SFR_MEM8(0x0B09) -#define TCF2_INTFLAGS _SFR_MEM8(0x0B0C) -#define TCF2_LCNT _SFR_MEM8(0x0B20) -#define TCF2_HCNT _SFR_MEM8(0x0B21) -#define TCF2_LPER _SFR_MEM8(0x0B26) -#define TCF2_HPER _SFR_MEM8(0x0B27) -#define TCF2_LCMPA _SFR_MEM8(0x0B28) -#define TCF2_HCMPA _SFR_MEM8(0x0B29) -#define TCF2_LCMPB _SFR_MEM8(0x0B2A) -#define TCF2_HCMPB _SFR_MEM8(0x0B2B) -#define TCF2_LCMPC _SFR_MEM8(0x0B2C) -#define TCF2_HCMPC _SFR_MEM8(0x0B2D) -#define TCF2_LCMPD _SFR_MEM8(0x0B2E) -#define TCF2_HCMPD _SFR_MEM8(0x0B2F) - -/* HIRES - High-Resolution Extension */ -#define HIRESF_CTRLA _SFR_MEM8(0x0B90) - -/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ -#define USARTF0_DATA _SFR_MEM8(0x0BA0) -#define USARTF0_STATUS _SFR_MEM8(0x0BA1) -#define USARTF0_CTRLA _SFR_MEM8(0x0BA3) -#define USARTF0_CTRLB _SFR_MEM8(0x0BA4) -#define USARTF0_CTRLC _SFR_MEM8(0x0BA5) -#define USARTF0_BAUDCTRLA _SFR_MEM8(0x0BA6) -#define USARTF0_BAUDCTRLB _SFR_MEM8(0x0BA7) - - - -/*================== Bitfield Definitions ================== */ - -/* VPORT - Virtual Ports */ -/* VPORT.INTFLAGS bit masks and bit positions */ -#define VPORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ -#define VPORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ - -#define VPORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ -#define VPORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ - -/* XOCD - On-Chip Debug System */ -/* OCD.OCDR0 bit masks and bit positions */ -#define OCD_OCDRD_gm 0xFF /* OCDR Dirty group mask. */ -#define OCD_OCDRD_gp 0 /* OCDR Dirty group position. */ -#define OCD_OCDRD0_bm (1<<0) /* OCDR Dirty bit 0 mask. */ -#define OCD_OCDRD0_bp 0 /* OCDR Dirty bit 0 position. */ -#define OCD_OCDRD1_bm (1<<1) /* OCDR Dirty bit 1 mask. */ -#define OCD_OCDRD1_bp 1 /* OCDR Dirty bit 1 position. */ -#define OCD_OCDRD2_bm (1<<2) /* OCDR Dirty bit 2 mask. */ -#define OCD_OCDRD2_bp 2 /* OCDR Dirty bit 2 position. */ -#define OCD_OCDRD3_bm (1<<3) /* OCDR Dirty bit 3 mask. */ -#define OCD_OCDRD3_bp 3 /* OCDR Dirty bit 3 position. */ -#define OCD_OCDRD4_bm (1<<4) /* OCDR Dirty bit 4 mask. */ -#define OCD_OCDRD4_bp 4 /* OCDR Dirty bit 4 position. */ -#define OCD_OCDRD5_bm (1<<5) /* OCDR Dirty bit 5 mask. */ -#define OCD_OCDRD5_bp 5 /* OCDR Dirty bit 5 position. */ -#define OCD_OCDRD6_bm (1<<6) /* OCDR Dirty bit 6 mask. */ -#define OCD_OCDRD6_bp 6 /* OCDR Dirty bit 6 position. */ -#define OCD_OCDRD7_bm (1<<7) /* OCDR Dirty bit 7 mask. */ -#define OCD_OCDRD7_bp 7 /* OCDR Dirty bit 7 position. */ - -/* OCD.OCDR1 bit masks and bit positions */ -/* OCD_OCDRD Predefined. */ -/* OCD_OCDRD Predefined. */ - -/* CPU - CPU */ -/* CPU.CCP bit masks and bit positions */ -#define CPU_CCP_gm 0xFF /* CCP signature group mask. */ -#define CPU_CCP_gp 0 /* CCP signature group position. */ -#define CPU_CCP0_bm (1<<0) /* CCP signature bit 0 mask. */ -#define CPU_CCP0_bp 0 /* CCP signature bit 0 position. */ -#define CPU_CCP1_bm (1<<1) /* CCP signature bit 1 mask. */ -#define CPU_CCP1_bp 1 /* CCP signature bit 1 position. */ -#define CPU_CCP2_bm (1<<2) /* CCP signature bit 2 mask. */ -#define CPU_CCP2_bp 2 /* CCP signature bit 2 position. */ -#define CPU_CCP3_bm (1<<3) /* CCP signature bit 3 mask. */ -#define CPU_CCP3_bp 3 /* CCP signature bit 3 position. */ -#define CPU_CCP4_bm (1<<4) /* CCP signature bit 4 mask. */ -#define CPU_CCP4_bp 4 /* CCP signature bit 4 position. */ -#define CPU_CCP5_bm (1<<5) /* CCP signature bit 5 mask. */ -#define CPU_CCP5_bp 5 /* CCP signature bit 5 position. */ -#define CPU_CCP6_bm (1<<6) /* CCP signature bit 6 mask. */ -#define CPU_CCP6_bp 6 /* CCP signature bit 6 position. */ -#define CPU_CCP7_bm (1<<7) /* CCP signature bit 7 mask. */ -#define CPU_CCP7_bp 7 /* CCP signature bit 7 position. */ - -/* CPU.SREG bit masks and bit positions */ -#define CPU_I_bm 0x80 /* Global Interrupt Enable Flag bit mask. */ -#define CPU_I_bp 7 /* Global Interrupt Enable Flag bit position. */ - -#define CPU_T_bm 0x40 /* Transfer Bit bit mask. */ -#define CPU_T_bp 6 /* Transfer Bit bit position. */ - -#define CPU_H_bm 0x20 /* Half Carry Flag bit mask. */ -#define CPU_H_bp 5 /* Half Carry Flag bit position. */ - -#define CPU_S_bm 0x10 /* N Exclusive Or V Flag bit mask. */ -#define CPU_S_bp 4 /* N Exclusive Or V Flag bit position. */ - -#define CPU_V_bm 0x08 /* Two's Complement Overflow Flag bit mask. */ -#define CPU_V_bp 3 /* Two's Complement Overflow Flag bit position. */ - -#define CPU_N_bm 0x04 /* Negative Flag bit mask. */ -#define CPU_N_bp 2 /* Negative Flag bit position. */ - -#define CPU_Z_bm 0x02 /* Zero Flag bit mask. */ -#define CPU_Z_bp 1 /* Zero Flag bit position. */ - -#define CPU_C_bm 0x01 /* Carry Flag bit mask. */ -#define CPU_C_bp 0 /* Carry Flag bit position. */ - -/* CLK - Clock System */ -/* CLK.CTRL bit masks and bit positions */ -#define CLK_SCLKSEL_gm 0x07 /* System Clock Selection group mask. */ -#define CLK_SCLKSEL_gp 0 /* System Clock Selection group position. */ -#define CLK_SCLKSEL0_bm (1<<0) /* System Clock Selection bit 0 mask. */ -#define CLK_SCLKSEL0_bp 0 /* System Clock Selection bit 0 position. */ -#define CLK_SCLKSEL1_bm (1<<1) /* System Clock Selection bit 1 mask. */ -#define CLK_SCLKSEL1_bp 1 /* System Clock Selection bit 1 position. */ -#define CLK_SCLKSEL2_bm (1<<2) /* System Clock Selection bit 2 mask. */ -#define CLK_SCLKSEL2_bp 2 /* System Clock Selection bit 2 position. */ - -/* CLK.PSCTRL bit masks and bit positions */ -#define CLK_PSADIV_gm 0x7C /* Prescaler A Division Factor group mask. */ -#define CLK_PSADIV_gp 2 /* Prescaler A Division Factor group position. */ -#define CLK_PSADIV0_bm (1<<2) /* Prescaler A Division Factor bit 0 mask. */ -#define CLK_PSADIV0_bp 2 /* Prescaler A Division Factor bit 0 position. */ -#define CLK_PSADIV1_bm (1<<3) /* Prescaler A Division Factor bit 1 mask. */ -#define CLK_PSADIV1_bp 3 /* Prescaler A Division Factor bit 1 position. */ -#define CLK_PSADIV2_bm (1<<4) /* Prescaler A Division Factor bit 2 mask. */ -#define CLK_PSADIV2_bp 4 /* Prescaler A Division Factor bit 2 position. */ -#define CLK_PSADIV3_bm (1<<5) /* Prescaler A Division Factor bit 3 mask. */ -#define CLK_PSADIV3_bp 5 /* Prescaler A Division Factor bit 3 position. */ -#define CLK_PSADIV4_bm (1<<6) /* Prescaler A Division Factor bit 4 mask. */ -#define CLK_PSADIV4_bp 6 /* Prescaler A Division Factor bit 4 position. */ - -#define CLK_PSBCDIV_gm 0x03 /* Prescaler B and C Division factor group mask. */ -#define CLK_PSBCDIV_gp 0 /* Prescaler B and C Division factor group position. */ -#define CLK_PSBCDIV0_bm (1<<0) /* Prescaler B and C Division factor bit 0 mask. */ -#define CLK_PSBCDIV0_bp 0 /* Prescaler B and C Division factor bit 0 position. */ -#define CLK_PSBCDIV1_bm (1<<1) /* Prescaler B and C Division factor bit 1 mask. */ -#define CLK_PSBCDIV1_bp 1 /* Prescaler B and C Division factor bit 1 position. */ - -/* CLK.LOCK bit masks and bit positions */ -#define CLK_LOCK_bm 0x01 /* Clock System Lock bit mask. */ -#define CLK_LOCK_bp 0 /* Clock System Lock bit position. */ - -/* CLK.RTCCTRL bit masks and bit positions */ -#define CLK_RTCSRC_gm 0x0E /* Clock Source group mask. */ -#define CLK_RTCSRC_gp 1 /* Clock Source group position. */ -#define CLK_RTCSRC0_bm (1<<1) /* Clock Source bit 0 mask. */ -#define CLK_RTCSRC0_bp 1 /* Clock Source bit 0 position. */ -#define CLK_RTCSRC1_bm (1<<2) /* Clock Source bit 1 mask. */ -#define CLK_RTCSRC1_bp 2 /* Clock Source bit 1 position. */ -#define CLK_RTCSRC2_bm (1<<3) /* Clock Source bit 2 mask. */ -#define CLK_RTCSRC2_bp 3 /* Clock Source bit 2 position. */ - -#define CLK_RTCEN_bm 0x01 /* Clock Source Enable bit mask. */ -#define CLK_RTCEN_bp 0 /* Clock Source Enable bit position. */ - -/* CLK.USBCTRL bit masks and bit positions */ -#define CLK_USBPSDIV_gm 0x38 /* Prescaler Division Factor group mask. */ -#define CLK_USBPSDIV_gp 3 /* Prescaler Division Factor group position. */ -#define CLK_USBPSDIV0_bm (1<<3) /* Prescaler Division Factor bit 0 mask. */ -#define CLK_USBPSDIV0_bp 3 /* Prescaler Division Factor bit 0 position. */ -#define CLK_USBPSDIV1_bm (1<<4) /* Prescaler Division Factor bit 1 mask. */ -#define CLK_USBPSDIV1_bp 4 /* Prescaler Division Factor bit 1 position. */ -#define CLK_USBPSDIV2_bm (1<<5) /* Prescaler Division Factor bit 2 mask. */ -#define CLK_USBPSDIV2_bp 5 /* Prescaler Division Factor bit 2 position. */ - -#define CLK_USBSRC_gm 0x06 /* Clock Source group mask. */ -#define CLK_USBSRC_gp 1 /* Clock Source group position. */ -#define CLK_USBSRC0_bm (1<<1) /* Clock Source bit 0 mask. */ -#define CLK_USBSRC0_bp 1 /* Clock Source bit 0 position. */ -#define CLK_USBSRC1_bm (1<<2) /* Clock Source bit 1 mask. */ -#define CLK_USBSRC1_bp 2 /* Clock Source bit 1 position. */ - -#define CLK_USBSEN_bm 0x01 /* Clock Source Enable bit mask. */ -#define CLK_USBSEN_bp 0 /* Clock Source Enable bit position. */ - -/* PR.PRGEN bit masks and bit positions */ -#define PR_USB_bm 0x40 /* USB bit mask. */ -#define PR_USB_bp 6 /* USB bit position. */ - -#define PR_AES_bm 0x10 /* AES bit mask. */ -#define PR_AES_bp 4 /* AES bit position. */ - -#define PR_EBI_bm 0x08 /* External Bus Interface bit mask. */ -#define PR_EBI_bp 3 /* External Bus Interface bit position. */ - -#define PR_RTC_bm 0x04 /* Real-time Counter bit mask. */ -#define PR_RTC_bp 2 /* Real-time Counter bit position. */ - -#define PR_EVSYS_bm 0x02 /* Event System bit mask. */ -#define PR_EVSYS_bp 1 /* Event System bit position. */ - -#define PR_DMA_bm 0x01 /* DMA-Controller bit mask. */ -#define PR_DMA_bp 0 /* DMA-Controller bit position. */ - -/* PR.PRPA bit masks and bit positions */ -#define PR_DAC_bm 0x04 /* Port A DAC bit mask. */ -#define PR_DAC_bp 2 /* Port A DAC bit position. */ - -#define PR_ADC_bm 0x02 /* Port A ADC bit mask. */ -#define PR_ADC_bp 1 /* Port A ADC bit position. */ - -#define PR_AC_bm 0x01 /* Port A Analog Comparator bit mask. */ -#define PR_AC_bp 0 /* Port A Analog Comparator bit position. */ - -/* PR.PRPB bit masks and bit positions */ -/* PR_DAC Predefined. */ -/* PR_DAC Predefined. */ - -/* PR_ADC Predefined. */ -/* PR_ADC Predefined. */ - -/* PR_AC Predefined. */ -/* PR_AC Predefined. */ - -/* PR.PRPC bit masks and bit positions */ -#define PR_TWI_bm 0x40 /* Port C Two-wire Interface bit mask. */ -#define PR_TWI_bp 6 /* Port C Two-wire Interface bit position. */ - -#define PR_USART1_bm 0x20 /* Port C USART1 bit mask. */ -#define PR_USART1_bp 5 /* Port C USART1 bit position. */ - -#define PR_USART0_bm 0x10 /* Port C USART0 bit mask. */ -#define PR_USART0_bp 4 /* Port C USART0 bit position. */ - -#define PR_SPI_bm 0x08 /* Port C SPI bit mask. */ -#define PR_SPI_bp 3 /* Port C SPI bit position. */ - -#define PR_HIRES_bm 0x04 /* Port C AWEX bit mask. */ -#define PR_HIRES_bp 2 /* Port C AWEX bit position. */ - -#define PR_TC1_bm 0x02 /* Port C Timer/Counter1 bit mask. */ -#define PR_TC1_bp 1 /* Port C Timer/Counter1 bit position. */ - -#define PR_TC0_bm 0x01 /* Port C Timer/Counter0 bit mask. */ -#define PR_TC0_bp 0 /* Port C Timer/Counter0 bit position. */ - -/* PR.PRPD bit masks and bit positions */ -/* PR_TWI Predefined. */ -/* PR_TWI Predefined. */ - -/* PR_USART1 Predefined. */ -/* PR_USART1 Predefined. */ - -/* PR_USART0 Predefined. */ -/* PR_USART0 Predefined. */ - -/* PR_SPI Predefined. */ -/* PR_SPI Predefined. */ - -/* PR_HIRES Predefined. */ -/* PR_HIRES Predefined. */ - -/* PR_TC1 Predefined. */ -/* PR_TC1 Predefined. */ - -/* PR_TC0 Predefined. */ -/* PR_TC0 Predefined. */ - -/* PR.PRPE bit masks and bit positions */ -/* PR_TWI Predefined. */ -/* PR_TWI Predefined. */ - -/* PR_USART1 Predefined. */ -/* PR_USART1 Predefined. */ - -/* PR_USART0 Predefined. */ -/* PR_USART0 Predefined. */ - -/* PR_SPI Predefined. */ -/* PR_SPI Predefined. */ - -/* PR_HIRES Predefined. */ -/* PR_HIRES Predefined. */ - -/* PR_TC1 Predefined. */ -/* PR_TC1 Predefined. */ - -/* PR_TC0 Predefined. */ -/* PR_TC0 Predefined. */ - -/* PR.PRPF bit masks and bit positions */ -/* PR_TWI Predefined. */ -/* PR_TWI Predefined. */ - -/* PR_USART1 Predefined. */ -/* PR_USART1 Predefined. */ - -/* PR_USART0 Predefined. */ -/* PR_USART0 Predefined. */ - -/* PR_SPI Predefined. */ -/* PR_SPI Predefined. */ - -/* PR_HIRES Predefined. */ -/* PR_HIRES Predefined. */ - -/* PR_TC1 Predefined. */ -/* PR_TC1 Predefined. */ - -/* PR_TC0 Predefined. */ -/* PR_TC0 Predefined. */ - -/* SLEEP - Sleep Controller */ -/* SLEEP.CTRL bit masks and bit positions */ -#define SLEEP_SMODE_gm 0x0E /* Sleep Mode group mask. */ -#define SLEEP_SMODE_gp 1 /* Sleep Mode group position. */ -#define SLEEP_SMODE0_bm (1<<1) /* Sleep Mode bit 0 mask. */ -#define SLEEP_SMODE0_bp 1 /* Sleep Mode bit 0 position. */ -#define SLEEP_SMODE1_bm (1<<2) /* Sleep Mode bit 1 mask. */ -#define SLEEP_SMODE1_bp 2 /* Sleep Mode bit 1 position. */ -#define SLEEP_SMODE2_bm (1<<3) /* Sleep Mode bit 2 mask. */ -#define SLEEP_SMODE2_bp 3 /* Sleep Mode bit 2 position. */ - -#define SLEEP_SEN_bm 0x01 /* Sleep Enable bit mask. */ -#define SLEEP_SEN_bp 0 /* Sleep Enable bit position. */ - -/* OSC - Oscillator */ -/* OSC.CTRL bit masks and bit positions */ -#define OSC_PLLEN_bm 0x10 /* PLL Enable bit mask. */ -#define OSC_PLLEN_bp 4 /* PLL Enable bit position. */ - -#define OSC_XOSCEN_bm 0x08 /* External Oscillator Enable bit mask. */ -#define OSC_XOSCEN_bp 3 /* External Oscillator Enable bit position. */ - -#define OSC_RC32KEN_bm 0x04 /* Internal 32.768 kHz RC Oscillator Enable bit mask. */ -#define OSC_RC32KEN_bp 2 /* Internal 32.768 kHz RC Oscillator Enable bit position. */ - -#define OSC_RC32MEN_bm 0x02 /* Internal 32 MHz RC Oscillator Enable bit mask. */ -#define OSC_RC32MEN_bp 1 /* Internal 32 MHz RC Oscillator Enable bit position. */ - -#define OSC_RC2MEN_bm 0x01 /* Internal 2 MHz RC Oscillator Enable bit mask. */ -#define OSC_RC2MEN_bp 0 /* Internal 2 MHz RC Oscillator Enable bit position. */ - -/* OSC.STATUS bit masks and bit positions */ -#define OSC_PLLRDY_bm 0x10 /* PLL Ready bit mask. */ -#define OSC_PLLRDY_bp 4 /* PLL Ready bit position. */ - -#define OSC_XOSCRDY_bm 0x08 /* External Oscillator Ready bit mask. */ -#define OSC_XOSCRDY_bp 3 /* External Oscillator Ready bit position. */ - -#define OSC_RC32KRDY_bm 0x04 /* Internal 32.768 kHz RC Oscillator Ready bit mask. */ -#define OSC_RC32KRDY_bp 2 /* Internal 32.768 kHz RC Oscillator Ready bit position. */ - -#define OSC_RC32MRDY_bm 0x02 /* Internal 32 MHz RC Oscillator Ready bit mask. */ -#define OSC_RC32MRDY_bp 1 /* Internal 32 MHz RC Oscillator Ready bit position. */ - -#define OSC_RC2MRDY_bm 0x01 /* Internal 2 MHz RC Oscillator Ready bit mask. */ -#define OSC_RC2MRDY_bp 0 /* Internal 2 MHz RC Oscillator Ready bit position. */ - -/* OSC.XOSCCTRL bit masks and bit positions */ -#define OSC_FRQRANGE_gm 0xC0 /* Frequency Range group mask. */ -#define OSC_FRQRANGE_gp 6 /* Frequency Range group position. */ -#define OSC_FRQRANGE0_bm (1<<6) /* Frequency Range bit 0 mask. */ -#define OSC_FRQRANGE0_bp 6 /* Frequency Range bit 0 position. */ -#define OSC_FRQRANGE1_bm (1<<7) /* Frequency Range bit 1 mask. */ -#define OSC_FRQRANGE1_bp 7 /* Frequency Range bit 1 position. */ - -#define OSC_X32KLPM_bm 0x20 /* 32.768 kHz XTAL OSC Low-power Mode bit mask. */ -#define OSC_X32KLPM_bp 5 /* 32.768 kHz XTAL OSC Low-power Mode bit position. */ - -#define OSC_XOSCPWR_bm 0x10 /* 16 MHz Crystal Oscillator High Power mode bit mask. */ -#define OSC_XOSCPWR_bp 4 /* 16 MHz Crystal Oscillator High Power mode bit position. */ - -#define OSC_XOSCSEL_gm 0x0F /* External Oscillator Selection and Startup Time group mask. */ -#define OSC_XOSCSEL_gp 0 /* External Oscillator Selection and Startup Time group position. */ -#define OSC_XOSCSEL0_bm (1<<0) /* External Oscillator Selection and Startup Time bit 0 mask. */ -#define OSC_XOSCSEL0_bp 0 /* External Oscillator Selection and Startup Time bit 0 position. */ -#define OSC_XOSCSEL1_bm (1<<1) /* External Oscillator Selection and Startup Time bit 1 mask. */ -#define OSC_XOSCSEL1_bp 1 /* External Oscillator Selection and Startup Time bit 1 position. */ -#define OSC_XOSCSEL2_bm (1<<2) /* External Oscillator Selection and Startup Time bit 2 mask. */ -#define OSC_XOSCSEL2_bp 2 /* External Oscillator Selection and Startup Time bit 2 position. */ -#define OSC_XOSCSEL3_bm (1<<3) /* External Oscillator Selection and Startup Time bit 3 mask. */ -#define OSC_XOSCSEL3_bp 3 /* External Oscillator Selection and Startup Time bit 3 position. */ - -/* OSC.XOSCFAIL bit masks and bit positions */ -#define OSC_PLLFDIF_bm 0x08 /* PLL Failure Detection Interrupt Flag bit mask. */ -#define OSC_PLLFDIF_bp 3 /* PLL Failure Detection Interrupt Flag bit position. */ - -#define OSC_PLLFDEN_bm 0x04 /* PLL Failure Detection Enable bit mask. */ -#define OSC_PLLFDEN_bp 2 /* PLL Failure Detection Enable bit position. */ - -#define OSC_XOSCFDIF_bm 0x02 /* XOSC Failure Detection Interrupt Flag bit mask. */ -#define OSC_XOSCFDIF_bp 1 /* XOSC Failure Detection Interrupt Flag bit position. */ - -#define OSC_XOSCFDEN_bm 0x01 /* XOSC Failure Detection Enable bit mask. */ -#define OSC_XOSCFDEN_bp 0 /* XOSC Failure Detection Enable bit position. */ - -/* OSC.PLLCTRL bit masks and bit positions */ -#define OSC_PLLSRC_gm 0xC0 /* Clock Source group mask. */ -#define OSC_PLLSRC_gp 6 /* Clock Source group position. */ -#define OSC_PLLSRC0_bm (1<<6) /* Clock Source bit 0 mask. */ -#define OSC_PLLSRC0_bp 6 /* Clock Source bit 0 position. */ -#define OSC_PLLSRC1_bm (1<<7) /* Clock Source bit 1 mask. */ -#define OSC_PLLSRC1_bp 7 /* Clock Source bit 1 position. */ - -#define OSC_PLLDIV_bm 0x20 /* Divide by 2 bit mask. */ -#define OSC_PLLDIV_bp 5 /* Divide by 2 bit position. */ - -#define OSC_PLLFAC_gm 0x1F /* Multiplication Factor group mask. */ -#define OSC_PLLFAC_gp 0 /* Multiplication Factor group position. */ -#define OSC_PLLFAC0_bm (1<<0) /* Multiplication Factor bit 0 mask. */ -#define OSC_PLLFAC0_bp 0 /* Multiplication Factor bit 0 position. */ -#define OSC_PLLFAC1_bm (1<<1) /* Multiplication Factor bit 1 mask. */ -#define OSC_PLLFAC1_bp 1 /* Multiplication Factor bit 1 position. */ -#define OSC_PLLFAC2_bm (1<<2) /* Multiplication Factor bit 2 mask. */ -#define OSC_PLLFAC2_bp 2 /* Multiplication Factor bit 2 position. */ -#define OSC_PLLFAC3_bm (1<<3) /* Multiplication Factor bit 3 mask. */ -#define OSC_PLLFAC3_bp 3 /* Multiplication Factor bit 3 position. */ -#define OSC_PLLFAC4_bm (1<<4) /* Multiplication Factor bit 4 mask. */ -#define OSC_PLLFAC4_bp 4 /* Multiplication Factor bit 4 position. */ - -/* OSC.DFLLCTRL bit masks and bit positions */ -#define OSC_RC32MCREF_gm 0x06 /* 32 MHz DFLL Calibration Reference group mask. */ -#define OSC_RC32MCREF_gp 1 /* 32 MHz DFLL Calibration Reference group position. */ -#define OSC_RC32MCREF0_bm (1<<1) /* 32 MHz DFLL Calibration Reference bit 0 mask. */ -#define OSC_RC32MCREF0_bp 1 /* 32 MHz DFLL Calibration Reference bit 0 position. */ -#define OSC_RC32MCREF1_bm (1<<2) /* 32 MHz DFLL Calibration Reference bit 1 mask. */ -#define OSC_RC32MCREF1_bp 2 /* 32 MHz DFLL Calibration Reference bit 1 position. */ - -#define OSC_RC2MCREF_bm 0x01 /* 2 MHz DFLL Calibration Reference bit mask. */ -#define OSC_RC2MCREF_bp 0 /* 2 MHz DFLL Calibration Reference bit position. */ - -/* DFLL - DFLL */ -/* DFLL.CTRL bit masks and bit positions */ -#define DFLL_ENABLE_bm 0x01 /* DFLL Enable bit mask. */ -#define DFLL_ENABLE_bp 0 /* DFLL Enable bit position. */ - -/* DFLL.CALA bit masks and bit positions */ -#define DFLL_CALL_gm 0x7F /* DFLL Calibration Value A group mask. */ -#define DFLL_CALL_gp 0 /* DFLL Calibration Value A group position. */ -#define DFLL_CALL0_bm (1<<0) /* DFLL Calibration Value A bit 0 mask. */ -#define DFLL_CALL0_bp 0 /* DFLL Calibration Value A bit 0 position. */ -#define DFLL_CALL1_bm (1<<1) /* DFLL Calibration Value A bit 1 mask. */ -#define DFLL_CALL1_bp 1 /* DFLL Calibration Value A bit 1 position. */ -#define DFLL_CALL2_bm (1<<2) /* DFLL Calibration Value A bit 2 mask. */ -#define DFLL_CALL2_bp 2 /* DFLL Calibration Value A bit 2 position. */ -#define DFLL_CALL3_bm (1<<3) /* DFLL Calibration Value A bit 3 mask. */ -#define DFLL_CALL3_bp 3 /* DFLL Calibration Value A bit 3 position. */ -#define DFLL_CALL4_bm (1<<4) /* DFLL Calibration Value A bit 4 mask. */ -#define DFLL_CALL4_bp 4 /* DFLL Calibration Value A bit 4 position. */ -#define DFLL_CALL5_bm (1<<5) /* DFLL Calibration Value A bit 5 mask. */ -#define DFLL_CALL5_bp 5 /* DFLL Calibration Value A bit 5 position. */ -#define DFLL_CALL6_bm (1<<6) /* DFLL Calibration Value A bit 6 mask. */ -#define DFLL_CALL6_bp 6 /* DFLL Calibration Value A bit 6 position. */ - -/* DFLL.CALB bit masks and bit positions */ -#define DFLL_CALH_gm 0x3F /* DFLL Calibration Value B group mask. */ -#define DFLL_CALH_gp 0 /* DFLL Calibration Value B group position. */ -#define DFLL_CALH0_bm (1<<0) /* DFLL Calibration Value B bit 0 mask. */ -#define DFLL_CALH0_bp 0 /* DFLL Calibration Value B bit 0 position. */ -#define DFLL_CALH1_bm (1<<1) /* DFLL Calibration Value B bit 1 mask. */ -#define DFLL_CALH1_bp 1 /* DFLL Calibration Value B bit 1 position. */ -#define DFLL_CALH2_bm (1<<2) /* DFLL Calibration Value B bit 2 mask. */ -#define DFLL_CALH2_bp 2 /* DFLL Calibration Value B bit 2 position. */ -#define DFLL_CALH3_bm (1<<3) /* DFLL Calibration Value B bit 3 mask. */ -#define DFLL_CALH3_bp 3 /* DFLL Calibration Value B bit 3 position. */ -#define DFLL_CALH4_bm (1<<4) /* DFLL Calibration Value B bit 4 mask. */ -#define DFLL_CALH4_bp 4 /* DFLL Calibration Value B bit 4 position. */ -#define DFLL_CALH5_bm (1<<5) /* DFLL Calibration Value B bit 5 mask. */ -#define DFLL_CALH5_bp 5 /* DFLL Calibration Value B bit 5 position. */ - -/* RST - Reset */ -/* RST.STATUS bit masks and bit positions */ -#define RST_SDRF_bm 0x40 /* Spike Detection Reset Flag bit mask. */ -#define RST_SDRF_bp 6 /* Spike Detection Reset Flag bit position. */ - -#define RST_SRF_bm 0x20 /* Software Reset Flag bit mask. */ -#define RST_SRF_bp 5 /* Software Reset Flag bit position. */ - -#define RST_PDIRF_bm 0x10 /* Programming and Debug Interface Interface Reset Flag bit mask. */ -#define RST_PDIRF_bp 4 /* Programming and Debug Interface Interface Reset Flag bit position. */ - -#define RST_WDRF_bm 0x08 /* Watchdog Reset Flag bit mask. */ -#define RST_WDRF_bp 3 /* Watchdog Reset Flag bit position. */ - -#define RST_BORF_bm 0x04 /* Brown-out Reset Flag bit mask. */ -#define RST_BORF_bp 2 /* Brown-out Reset Flag bit position. */ - -#define RST_EXTRF_bm 0x02 /* External Reset Flag bit mask. */ -#define RST_EXTRF_bp 1 /* External Reset Flag bit position. */ - -#define RST_PORF_bm 0x01 /* Power-on Reset Flag bit mask. */ -#define RST_PORF_bp 0 /* Power-on Reset Flag bit position. */ - -/* RST.CTRL bit masks and bit positions */ -#define RST_SWRST_bm 0x01 /* Software Reset bit mask. */ -#define RST_SWRST_bp 0 /* Software Reset bit position. */ - -/* WDT - Watch-Dog Timer */ -/* WDT.CTRL bit masks and bit positions */ -#define WDT_PER_gm 0x3C /* Period group mask. */ -#define WDT_PER_gp 2 /* Period group position. */ -#define WDT_PER0_bm (1<<2) /* Period bit 0 mask. */ -#define WDT_PER0_bp 2 /* Period bit 0 position. */ -#define WDT_PER1_bm (1<<3) /* Period bit 1 mask. */ -#define WDT_PER1_bp 3 /* Period bit 1 position. */ -#define WDT_PER2_bm (1<<4) /* Period bit 2 mask. */ -#define WDT_PER2_bp 4 /* Period bit 2 position. */ -#define WDT_PER3_bm (1<<5) /* Period bit 3 mask. */ -#define WDT_PER3_bp 5 /* Period bit 3 position. */ - -#define WDT_ENABLE_bm 0x02 /* Enable bit mask. */ -#define WDT_ENABLE_bp 1 /* Enable bit position. */ - -#define WDT_CEN_bm 0x01 /* Change Enable bit mask. */ -#define WDT_CEN_bp 0 /* Change Enable bit position. */ - -/* WDT.WINCTRL bit masks and bit positions */ -#define WDT_WPER_gm 0x3C /* Windowed Mode Period group mask. */ -#define WDT_WPER_gp 2 /* Windowed Mode Period group position. */ -#define WDT_WPER0_bm (1<<2) /* Windowed Mode Period bit 0 mask. */ -#define WDT_WPER0_bp 2 /* Windowed Mode Period bit 0 position. */ -#define WDT_WPER1_bm (1<<3) /* Windowed Mode Period bit 1 mask. */ -#define WDT_WPER1_bp 3 /* Windowed Mode Period bit 1 position. */ -#define WDT_WPER2_bm (1<<4) /* Windowed Mode Period bit 2 mask. */ -#define WDT_WPER2_bp 4 /* Windowed Mode Period bit 2 position. */ -#define WDT_WPER3_bm (1<<5) /* Windowed Mode Period bit 3 mask. */ -#define WDT_WPER3_bp 5 /* Windowed Mode Period bit 3 position. */ - -#define WDT_WEN_bm 0x02 /* Windowed Mode Enable bit mask. */ -#define WDT_WEN_bp 1 /* Windowed Mode Enable bit position. */ - -#define WDT_WCEN_bm 0x01 /* Windowed Mode Change Enable bit mask. */ -#define WDT_WCEN_bp 0 /* Windowed Mode Change Enable bit position. */ - -/* WDT.STATUS bit masks and bit positions */ -#define WDT_SYNCBUSY_bm 0x01 /* Syncronization busy bit mask. */ -#define WDT_SYNCBUSY_bp 0 /* Syncronization busy bit position. */ - -/* MCU - MCU Control */ -/* MCU.MCUCR bit masks and bit positions */ -#define MCU_JTAGD_bm 0x01 /* JTAG Disable bit mask. */ -#define MCU_JTAGD_bp 0 /* JTAG Disable bit position. */ - -/* MCU.ANAINIT bit masks and bit positions */ -#define MCU_STARTUPDLYB_gm 0x0C /* Analog startup delay Port B group mask. */ -#define MCU_STARTUPDLYB_gp 2 /* Analog startup delay Port B group position. */ -#define MCU_STARTUPDLYB0_bm (1<<2) /* Analog startup delay Port B bit 0 mask. */ -#define MCU_STARTUPDLYB0_bp 2 /* Analog startup delay Port B bit 0 position. */ -#define MCU_STARTUPDLYB1_bm (1<<3) /* Analog startup delay Port B bit 1 mask. */ -#define MCU_STARTUPDLYB1_bp 3 /* Analog startup delay Port B bit 1 position. */ - -#define MCU_STARTUPDLYA_gm 0x03 /* Analog startup delay Port A group mask. */ -#define MCU_STARTUPDLYA_gp 0 /* Analog startup delay Port A group position. */ -#define MCU_STARTUPDLYA0_bm (1<<0) /* Analog startup delay Port A bit 0 mask. */ -#define MCU_STARTUPDLYA0_bp 0 /* Analog startup delay Port A bit 0 position. */ -#define MCU_STARTUPDLYA1_bm (1<<1) /* Analog startup delay Port A bit 1 mask. */ -#define MCU_STARTUPDLYA1_bp 1 /* Analog startup delay Port A bit 1 position. */ - -/* MCU.EVSYSLOCK bit masks and bit positions */ -#define MCU_EVSYS1LOCK_bm 0x10 /* Event Channel 4-7 Lock bit mask. */ -#define MCU_EVSYS1LOCK_bp 4 /* Event Channel 4-7 Lock bit position. */ - -#define MCU_EVSYS0LOCK_bm 0x01 /* Event Channel 0-3 Lock bit mask. */ -#define MCU_EVSYS0LOCK_bp 0 /* Event Channel 0-3 Lock bit position. */ - -/* MCU.AWEXLOCK bit masks and bit positions */ -#define MCU_AWEXFLOCK_bm 0x08 /* AWeX on T/C F0 Lock bit mask. */ -#define MCU_AWEXFLOCK_bp 3 /* AWeX on T/C F0 Lock bit position. */ - -#define MCU_AWEXELOCK_bm 0x04 /* AWeX on T/C E0 Lock bit mask. */ -#define MCU_AWEXELOCK_bp 2 /* AWeX on T/C E0 Lock bit position. */ - -#define MCU_AWEXDLOCK_bm 0x02 /* AWeX on T/C D0 Lock bit mask. */ -#define MCU_AWEXDLOCK_bp 1 /* AWeX on T/C D0 Lock bit position. */ - -#define MCU_AWEXCLOCK_bm 0x01 /* AWeX on T/C C0 Lock bit mask. */ -#define MCU_AWEXCLOCK_bp 0 /* AWeX on T/C C0 Lock bit position. */ - -/* PMIC - Programmable Multi-level Interrupt Controller */ -/* PMIC.STATUS bit masks and bit positions */ -#define PMIC_NMIEX_bm 0x80 /* Non-maskable Interrupt Executing bit mask. */ -#define PMIC_NMIEX_bp 7 /* Non-maskable Interrupt Executing bit position. */ - -#define PMIC_HILVLEX_bm 0x04 /* High Level Interrupt Executing bit mask. */ -#define PMIC_HILVLEX_bp 2 /* High Level Interrupt Executing bit position. */ - -#define PMIC_MEDLVLEX_bm 0x02 /* Medium Level Interrupt Executing bit mask. */ -#define PMIC_MEDLVLEX_bp 1 /* Medium Level Interrupt Executing bit position. */ - -#define PMIC_LOLVLEX_bm 0x01 /* Low Level Interrupt Executing bit mask. */ -#define PMIC_LOLVLEX_bp 0 /* Low Level Interrupt Executing bit position. */ - -/* PMIC.INTPRI bit masks and bit positions */ -#define PMIC_INTPRI_gm 0xFF /* Interrupt Priority group mask. */ -#define PMIC_INTPRI_gp 0 /* Interrupt Priority group position. */ -#define PMIC_INTPRI0_bm (1<<0) /* Interrupt Priority bit 0 mask. */ -#define PMIC_INTPRI0_bp 0 /* Interrupt Priority bit 0 position. */ -#define PMIC_INTPRI1_bm (1<<1) /* Interrupt Priority bit 1 mask. */ -#define PMIC_INTPRI1_bp 1 /* Interrupt Priority bit 1 position. */ -#define PMIC_INTPRI2_bm (1<<2) /* Interrupt Priority bit 2 mask. */ -#define PMIC_INTPRI2_bp 2 /* Interrupt Priority bit 2 position. */ -#define PMIC_INTPRI3_bm (1<<3) /* Interrupt Priority bit 3 mask. */ -#define PMIC_INTPRI3_bp 3 /* Interrupt Priority bit 3 position. */ -#define PMIC_INTPRI4_bm (1<<4) /* Interrupt Priority bit 4 mask. */ -#define PMIC_INTPRI4_bp 4 /* Interrupt Priority bit 4 position. */ -#define PMIC_INTPRI5_bm (1<<5) /* Interrupt Priority bit 5 mask. */ -#define PMIC_INTPRI5_bp 5 /* Interrupt Priority bit 5 position. */ -#define PMIC_INTPRI6_bm (1<<6) /* Interrupt Priority bit 6 mask. */ -#define PMIC_INTPRI6_bp 6 /* Interrupt Priority bit 6 position. */ -#define PMIC_INTPRI7_bm (1<<7) /* Interrupt Priority bit 7 mask. */ -#define PMIC_INTPRI7_bp 7 /* Interrupt Priority bit 7 position. */ - -/* PMIC.CTRL bit masks and bit positions */ -#define PMIC_RREN_bm 0x80 /* Round-Robin Priority Enable bit mask. */ -#define PMIC_RREN_bp 7 /* Round-Robin Priority Enable bit position. */ - -#define PMIC_IVSEL_bm 0x40 /* Interrupt Vector Select bit mask. */ -#define PMIC_IVSEL_bp 6 /* Interrupt Vector Select bit position. */ - -#define PMIC_HILVLEN_bm 0x04 /* High Level Enable bit mask. */ -#define PMIC_HILVLEN_bp 2 /* High Level Enable bit position. */ - -#define PMIC_MEDLVLEN_bm 0x02 /* Medium Level Enable bit mask. */ -#define PMIC_MEDLVLEN_bp 1 /* Medium Level Enable bit position. */ - -#define PMIC_LOLVLEN_bm 0x01 /* Low Level Enable bit mask. */ -#define PMIC_LOLVLEN_bp 0 /* Low Level Enable bit position. */ - -/* PORTCFG - Port Configuration */ -/* PORTCFG.VPCTRLA bit masks and bit positions */ -#define PORTCFG_VP1MAP_gm 0xF0 /* Virtual Port 1 Mapping group mask. */ -#define PORTCFG_VP1MAP_gp 4 /* Virtual Port 1 Mapping group position. */ -#define PORTCFG_VP1MAP0_bm (1<<4) /* Virtual Port 1 Mapping bit 0 mask. */ -#define PORTCFG_VP1MAP0_bp 4 /* Virtual Port 1 Mapping bit 0 position. */ -#define PORTCFG_VP1MAP1_bm (1<<5) /* Virtual Port 1 Mapping bit 1 mask. */ -#define PORTCFG_VP1MAP1_bp 5 /* Virtual Port 1 Mapping bit 1 position. */ -#define PORTCFG_VP1MAP2_bm (1<<6) /* Virtual Port 1 Mapping bit 2 mask. */ -#define PORTCFG_VP1MAP2_bp 6 /* Virtual Port 1 Mapping bit 2 position. */ -#define PORTCFG_VP1MAP3_bm (1<<7) /* Virtual Port 1 Mapping bit 3 mask. */ -#define PORTCFG_VP1MAP3_bp 7 /* Virtual Port 1 Mapping bit 3 position. */ - -#define PORTCFG_VP0MAP_gm 0x0F /* Virtual Port 0 Mapping group mask. */ -#define PORTCFG_VP0MAP_gp 0 /* Virtual Port 0 Mapping group position. */ -#define PORTCFG_VP0MAP0_bm (1<<0) /* Virtual Port 0 Mapping bit 0 mask. */ -#define PORTCFG_VP0MAP0_bp 0 /* Virtual Port 0 Mapping bit 0 position. */ -#define PORTCFG_VP0MAP1_bm (1<<1) /* Virtual Port 0 Mapping bit 1 mask. */ -#define PORTCFG_VP0MAP1_bp 1 /* Virtual Port 0 Mapping bit 1 position. */ -#define PORTCFG_VP0MAP2_bm (1<<2) /* Virtual Port 0 Mapping bit 2 mask. */ -#define PORTCFG_VP0MAP2_bp 2 /* Virtual Port 0 Mapping bit 2 position. */ -#define PORTCFG_VP0MAP3_bm (1<<3) /* Virtual Port 0 Mapping bit 3 mask. */ -#define PORTCFG_VP0MAP3_bp 3 /* Virtual Port 0 Mapping bit 3 position. */ - -/* PORTCFG.VPCTRLB bit masks and bit positions */ -#define PORTCFG_VP3MAP_gm 0xF0 /* Virtual Port 3 Mapping group mask. */ -#define PORTCFG_VP3MAP_gp 4 /* Virtual Port 3 Mapping group position. */ -#define PORTCFG_VP3MAP0_bm (1<<4) /* Virtual Port 3 Mapping bit 0 mask. */ -#define PORTCFG_VP3MAP0_bp 4 /* Virtual Port 3 Mapping bit 0 position. */ -#define PORTCFG_VP3MAP1_bm (1<<5) /* Virtual Port 3 Mapping bit 1 mask. */ -#define PORTCFG_VP3MAP1_bp 5 /* Virtual Port 3 Mapping bit 1 position. */ -#define PORTCFG_VP3MAP2_bm (1<<6) /* Virtual Port 3 Mapping bit 2 mask. */ -#define PORTCFG_VP3MAP2_bp 6 /* Virtual Port 3 Mapping bit 2 position. */ -#define PORTCFG_VP3MAP3_bm (1<<7) /* Virtual Port 3 Mapping bit 3 mask. */ -#define PORTCFG_VP3MAP3_bp 7 /* Virtual Port 3 Mapping bit 3 position. */ - -#define PORTCFG_VP2MAP_gm 0x0F /* Virtual Port 2 Mapping group mask. */ -#define PORTCFG_VP2MAP_gp 0 /* Virtual Port 2 Mapping group position. */ -#define PORTCFG_VP2MAP0_bm (1<<0) /* Virtual Port 2 Mapping bit 0 mask. */ -#define PORTCFG_VP2MAP0_bp 0 /* Virtual Port 2 Mapping bit 0 position. */ -#define PORTCFG_VP2MAP1_bm (1<<1) /* Virtual Port 2 Mapping bit 1 mask. */ -#define PORTCFG_VP2MAP1_bp 1 /* Virtual Port 2 Mapping bit 1 position. */ -#define PORTCFG_VP2MAP2_bm (1<<2) /* Virtual Port 2 Mapping bit 2 mask. */ -#define PORTCFG_VP2MAP2_bp 2 /* Virtual Port 2 Mapping bit 2 position. */ -#define PORTCFG_VP2MAP3_bm (1<<3) /* Virtual Port 2 Mapping bit 3 mask. */ -#define PORTCFG_VP2MAP3_bp 3 /* Virtual Port 2 Mapping bit 3 position. */ - -/* PORTCFG.CLKEVOUT bit masks and bit positions */ -#define PORTCFG_CLKOUT_gm 0x03 /* Peripheral Clock Output Port group mask. */ -#define PORTCFG_CLKOUT_gp 0 /* Peripheral Clock Output Port group position. */ -#define PORTCFG_CLKOUT0_bm (1<<0) /* Peripheral Clock Output Port bit 0 mask. */ -#define PORTCFG_CLKOUT0_bp 0 /* Peripheral Clock Output Port bit 0 position. */ -#define PORTCFG_CLKOUT1_bm (1<<1) /* Peripheral Clock Output Port bit 1 mask. */ -#define PORTCFG_CLKOUT1_bp 1 /* Peripheral Clock Output Port bit 1 position. */ - -#define PORTCFG_CLKOUTSEL_gm 0x0C /* Peripheral Clock Output Select group mask. */ -#define PORTCFG_CLKOUTSEL_gp 2 /* Peripheral Clock Output Select group position. */ -#define PORTCFG_CLKOUTSEL0_bm (1<<2) /* Peripheral Clock Output Select bit 0 mask. */ -#define PORTCFG_CLKOUTSEL0_bp 2 /* Peripheral Clock Output Select bit 0 position. */ -#define PORTCFG_CLKOUTSEL1_bm (1<<3) /* Peripheral Clock Output Select bit 1 mask. */ -#define PORTCFG_CLKOUTSEL1_bp 3 /* Peripheral Clock Output Select bit 1 position. */ - -#define PORTCFG_EVOUT_gm 0x30 /* Event Output Port group mask. */ -#define PORTCFG_EVOUT_gp 4 /* Event Output Port group position. */ -#define PORTCFG_EVOUT0_bm (1<<4) /* Event Output Port bit 0 mask. */ -#define PORTCFG_EVOUT0_bp 4 /* Event Output Port bit 0 position. */ -#define PORTCFG_EVOUT1_bm (1<<5) /* Event Output Port bit 1 mask. */ -#define PORTCFG_EVOUT1_bp 5 /* Event Output Port bit 1 position. */ - -#define PORTCFG_RTCOUT_bm 0x40 /* RTC Clock Output bit mask. */ -#define PORTCFG_RTCOUT_bp 6 /* RTC Clock Output bit position. */ - -#define PORTCFG_CLKEVPIN_bm 0x80 /* Peripheral Clock and Event Output pin Select bit mask. */ -#define PORTCFG_CLKEVPIN_bp 7 /* Peripheral Clock and Event Output pin Select bit position. */ - -/* PORTCFG.EBIOUT bit masks and bit positions */ -#define PORTCFG_EBICSOUT_gm 0x03 /* EBI Chip Select Output group mask. */ -#define PORTCFG_EBICSOUT_gp 0 /* EBI Chip Select Output group position. */ -#define PORTCFG_EBICSOUT0_bm (1<<0) /* EBI Chip Select Output bit 0 mask. */ -#define PORTCFG_EBICSOUT0_bp 0 /* EBI Chip Select Output bit 0 position. */ -#define PORTCFG_EBICSOUT1_bm (1<<1) /* EBI Chip Select Output bit 1 mask. */ -#define PORTCFG_EBICSOUT1_bp 1 /* EBI Chip Select Output bit 1 position. */ - -#define PORTCFG_EBIADROUT_gm 0x0C /* EBI Address Output group mask. */ -#define PORTCFG_EBIADROUT_gp 2 /* EBI Address Output group position. */ -#define PORTCFG_EBIADROUT0_bm (1<<2) /* EBI Address Output bit 0 mask. */ -#define PORTCFG_EBIADROUT0_bp 2 /* EBI Address Output bit 0 position. */ -#define PORTCFG_EBIADROUT1_bm (1<<3) /* EBI Address Output bit 1 mask. */ -#define PORTCFG_EBIADROUT1_bp 3 /* EBI Address Output bit 1 position. */ - -/* PORTCFG.EVOUTSEL bit masks and bit positions */ -#define PORTCFG_EVOUTSEL_gm 0x07 /* Event Output Select group mask. */ -#define PORTCFG_EVOUTSEL_gp 0 /* Event Output Select group position. */ -#define PORTCFG_EVOUTSEL0_bm (1<<0) /* Event Output Select bit 0 mask. */ -#define PORTCFG_EVOUTSEL0_bp 0 /* Event Output Select bit 0 position. */ -#define PORTCFG_EVOUTSEL1_bm (1<<1) /* Event Output Select bit 1 mask. */ -#define PORTCFG_EVOUTSEL1_bp 1 /* Event Output Select bit 1 position. */ -#define PORTCFG_EVOUTSEL2_bm (1<<2) /* Event Output Select bit 2 mask. */ -#define PORTCFG_EVOUTSEL2_bp 2 /* Event Output Select bit 2 position. */ - -/* AES - AES Module */ -/* AES.CTRL bit masks and bit positions */ -#define AES_START_bm 0x80 /* Start/Run bit mask. */ -#define AES_START_bp 7 /* Start/Run bit position. */ - -#define AES_AUTO_bm 0x40 /* Auto Start Trigger bit mask. */ -#define AES_AUTO_bp 6 /* Auto Start Trigger bit position. */ - -#define AES_RESET_bm 0x20 /* AES Software Reset bit mask. */ -#define AES_RESET_bp 5 /* AES Software Reset bit position. */ - -#define AES_DECRYPT_bm 0x10 /* Decryption / Direction bit mask. */ -#define AES_DECRYPT_bp 4 /* Decryption / Direction bit position. */ - -#define AES_XOR_bm 0x04 /* State XOR Load Enable bit mask. */ -#define AES_XOR_bp 2 /* State XOR Load Enable bit position. */ - -/* AES.STATUS bit masks and bit positions */ -#define AES_ERROR_bm 0x80 /* AES Error bit mask. */ -#define AES_ERROR_bp 7 /* AES Error bit position. */ - -#define AES_SRIF_bm 0x01 /* State Ready Interrupt Flag bit mask. */ -#define AES_SRIF_bp 0 /* State Ready Interrupt Flag bit position. */ - -/* AES.INTCTRL bit masks and bit positions */ -#define AES_INTLVL_gm 0x03 /* Interrupt level group mask. */ -#define AES_INTLVL_gp 0 /* Interrupt level group position. */ -#define AES_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */ -#define AES_INTLVL0_bp 0 /* Interrupt level bit 0 position. */ -#define AES_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */ -#define AES_INTLVL1_bp 1 /* Interrupt level bit 1 position. */ - -/* CRC - Cyclic Redundancy Checker */ -/* CRC.CTRL bit masks and bit positions */ -#define CRC_RESET_gm 0xC0 /* Reset group mask. */ -#define CRC_RESET_gp 6 /* Reset group position. */ -#define CRC_RESET0_bm (1<<6) /* Reset bit 0 mask. */ -#define CRC_RESET0_bp 6 /* Reset bit 0 position. */ -#define CRC_RESET1_bm (1<<7) /* Reset bit 1 mask. */ -#define CRC_RESET1_bp 7 /* Reset bit 1 position. */ - -#define CRC_CRC32_bm 0x20 /* CRC Mode bit mask. */ -#define CRC_CRC32_bp 5 /* CRC Mode bit position. */ - -#define CRC_SOURCE_gm 0x0F /* Input Source group mask. */ -#define CRC_SOURCE_gp 0 /* Input Source group position. */ -#define CRC_SOURCE0_bm (1<<0) /* Input Source bit 0 mask. */ -#define CRC_SOURCE0_bp 0 /* Input Source bit 0 position. */ -#define CRC_SOURCE1_bm (1<<1) /* Input Source bit 1 mask. */ -#define CRC_SOURCE1_bp 1 /* Input Source bit 1 position. */ -#define CRC_SOURCE2_bm (1<<2) /* Input Source bit 2 mask. */ -#define CRC_SOURCE2_bp 2 /* Input Source bit 2 position. */ -#define CRC_SOURCE3_bm (1<<3) /* Input Source bit 3 mask. */ -#define CRC_SOURCE3_bp 3 /* Input Source bit 3 position. */ - -/* CRC.STATUS bit masks and bit positions */ -#define CRC_ZERO_bm 0x02 /* Zero detection bit mask. */ -#define CRC_ZERO_bp 1 /* Zero detection bit position. */ - -#define CRC_BUSY_bm 0x01 /* Busy bit mask. */ -#define CRC_BUSY_bp 0 /* Busy bit position. */ - -/* DMA - DMA Controller */ -/* DMA_CH.CTRLA bit masks and bit positions */ -#define DMA_CH_ENABLE_bm 0x80 /* Channel Enable bit mask. */ -#define DMA_CH_ENABLE_bp 7 /* Channel Enable bit position. */ - -#define DMA_CH_RESET_bm 0x40 /* Channel Software Reset bit mask. */ -#define DMA_CH_RESET_bp 6 /* Channel Software Reset bit position. */ - -#define DMA_CH_REPEAT_bm 0x20 /* Channel Repeat Mode bit mask. */ -#define DMA_CH_REPEAT_bp 5 /* Channel Repeat Mode bit position. */ - -#define DMA_CH_TRFREQ_bm 0x10 /* Channel Transfer Request bit mask. */ -#define DMA_CH_TRFREQ_bp 4 /* Channel Transfer Request bit position. */ - -#define DMA_CH_SINGLE_bm 0x04 /* Channel Single Shot Data Transfer bit mask. */ -#define DMA_CH_SINGLE_bp 2 /* Channel Single Shot Data Transfer bit position. */ - -#define DMA_CH_BURSTLEN_gm 0x03 /* Channel Transfer Mode group mask. */ -#define DMA_CH_BURSTLEN_gp 0 /* Channel Transfer Mode group position. */ -#define DMA_CH_BURSTLEN0_bm (1<<0) /* Channel Transfer Mode bit 0 mask. */ -#define DMA_CH_BURSTLEN0_bp 0 /* Channel Transfer Mode bit 0 position. */ -#define DMA_CH_BURSTLEN1_bm (1<<1) /* Channel Transfer Mode bit 1 mask. */ -#define DMA_CH_BURSTLEN1_bp 1 /* Channel Transfer Mode bit 1 position. */ - -/* DMA_CH.CTRLB bit masks and bit positions */ -#define DMA_CH_CHBUSY_bm 0x80 /* Block Transfer Busy bit mask. */ -#define DMA_CH_CHBUSY_bp 7 /* Block Transfer Busy bit position. */ - -#define DMA_CH_CHPEND_bm 0x40 /* Block Transfer Pending bit mask. */ -#define DMA_CH_CHPEND_bp 6 /* Block Transfer Pending bit position. */ - -#define DMA_CH_ERRIF_bm 0x20 /* Block Transfer Error Interrupt Flag bit mask. */ -#define DMA_CH_ERRIF_bp 5 /* Block Transfer Error Interrupt Flag bit position. */ - -#define DMA_CH_TRNIF_bm 0x10 /* Transaction Complete Interrup Flag bit mask. */ -#define DMA_CH_TRNIF_bp 4 /* Transaction Complete Interrup Flag bit position. */ - -#define DMA_CH_ERRINTLVL_gm 0x0C /* Transfer Error Interrupt Level group mask. */ -#define DMA_CH_ERRINTLVL_gp 2 /* Transfer Error Interrupt Level group position. */ -#define DMA_CH_ERRINTLVL0_bm (1<<2) /* Transfer Error Interrupt Level bit 0 mask. */ -#define DMA_CH_ERRINTLVL0_bp 2 /* Transfer Error Interrupt Level bit 0 position. */ -#define DMA_CH_ERRINTLVL1_bm (1<<3) /* Transfer Error Interrupt Level bit 1 mask. */ -#define DMA_CH_ERRINTLVL1_bp 3 /* Transfer Error Interrupt Level bit 1 position. */ - -#define DMA_CH_TRNINTLVL_gm 0x03 /* Transaction Complete Interrupt Level group mask. */ -#define DMA_CH_TRNINTLVL_gp 0 /* Transaction Complete Interrupt Level group position. */ -#define DMA_CH_TRNINTLVL0_bm (1<<0) /* Transaction Complete Interrupt Level bit 0 mask. */ -#define DMA_CH_TRNINTLVL0_bp 0 /* Transaction Complete Interrupt Level bit 0 position. */ -#define DMA_CH_TRNINTLVL1_bm (1<<1) /* Transaction Complete Interrupt Level bit 1 mask. */ -#define DMA_CH_TRNINTLVL1_bp 1 /* Transaction Complete Interrupt Level bit 1 position. */ - -/* DMA_CH.ADDRCTRL bit masks and bit positions */ -#define DMA_CH_SRCRELOAD_gm 0xC0 /* Channel Source Address Reload group mask. */ -#define DMA_CH_SRCRELOAD_gp 6 /* Channel Source Address Reload group position. */ -#define DMA_CH_SRCRELOAD0_bm (1<<6) /* Channel Source Address Reload bit 0 mask. */ -#define DMA_CH_SRCRELOAD0_bp 6 /* Channel Source Address Reload bit 0 position. */ -#define DMA_CH_SRCRELOAD1_bm (1<<7) /* Channel Source Address Reload bit 1 mask. */ -#define DMA_CH_SRCRELOAD1_bp 7 /* Channel Source Address Reload bit 1 position. */ - -#define DMA_CH_SRCDIR_gm 0x30 /* Channel Source Address Mode group mask. */ -#define DMA_CH_SRCDIR_gp 4 /* Channel Source Address Mode group position. */ -#define DMA_CH_SRCDIR0_bm (1<<4) /* Channel Source Address Mode bit 0 mask. */ -#define DMA_CH_SRCDIR0_bp 4 /* Channel Source Address Mode bit 0 position. */ -#define DMA_CH_SRCDIR1_bm (1<<5) /* Channel Source Address Mode bit 1 mask. */ -#define DMA_CH_SRCDIR1_bp 5 /* Channel Source Address Mode bit 1 position. */ - -#define DMA_CH_DESTRELOAD_gm 0x0C /* Channel Destination Address Reload group mask. */ -#define DMA_CH_DESTRELOAD_gp 2 /* Channel Destination Address Reload group position. */ -#define DMA_CH_DESTRELOAD0_bm (1<<2) /* Channel Destination Address Reload bit 0 mask. */ -#define DMA_CH_DESTRELOAD0_bp 2 /* Channel Destination Address Reload bit 0 position. */ -#define DMA_CH_DESTRELOAD1_bm (1<<3) /* Channel Destination Address Reload bit 1 mask. */ -#define DMA_CH_DESTRELOAD1_bp 3 /* Channel Destination Address Reload bit 1 position. */ - -#define DMA_CH_DESTDIR_gm 0x03 /* Channel Destination Address Mode group mask. */ -#define DMA_CH_DESTDIR_gp 0 /* Channel Destination Address Mode group position. */ -#define DMA_CH_DESTDIR0_bm (1<<0) /* Channel Destination Address Mode bit 0 mask. */ -#define DMA_CH_DESTDIR0_bp 0 /* Channel Destination Address Mode bit 0 position. */ -#define DMA_CH_DESTDIR1_bm (1<<1) /* Channel Destination Address Mode bit 1 mask. */ -#define DMA_CH_DESTDIR1_bp 1 /* Channel Destination Address Mode bit 1 position. */ - -/* DMA_CH.TRIGSRC bit masks and bit positions */ -#define DMA_CH_TRIGSRC_gm 0xFF /* Channel Trigger Source group mask. */ -#define DMA_CH_TRIGSRC_gp 0 /* Channel Trigger Source group position. */ -#define DMA_CH_TRIGSRC0_bm (1<<0) /* Channel Trigger Source bit 0 mask. */ -#define DMA_CH_TRIGSRC0_bp 0 /* Channel Trigger Source bit 0 position. */ -#define DMA_CH_TRIGSRC1_bm (1<<1) /* Channel Trigger Source bit 1 mask. */ -#define DMA_CH_TRIGSRC1_bp 1 /* Channel Trigger Source bit 1 position. */ -#define DMA_CH_TRIGSRC2_bm (1<<2) /* Channel Trigger Source bit 2 mask. */ -#define DMA_CH_TRIGSRC2_bp 2 /* Channel Trigger Source bit 2 position. */ -#define DMA_CH_TRIGSRC3_bm (1<<3) /* Channel Trigger Source bit 3 mask. */ -#define DMA_CH_TRIGSRC3_bp 3 /* Channel Trigger Source bit 3 position. */ -#define DMA_CH_TRIGSRC4_bm (1<<4) /* Channel Trigger Source bit 4 mask. */ -#define DMA_CH_TRIGSRC4_bp 4 /* Channel Trigger Source bit 4 position. */ -#define DMA_CH_TRIGSRC5_bm (1<<5) /* Channel Trigger Source bit 5 mask. */ -#define DMA_CH_TRIGSRC5_bp 5 /* Channel Trigger Source bit 5 position. */ -#define DMA_CH_TRIGSRC6_bm (1<<6) /* Channel Trigger Source bit 6 mask. */ -#define DMA_CH_TRIGSRC6_bp 6 /* Channel Trigger Source bit 6 position. */ -#define DMA_CH_TRIGSRC7_bm (1<<7) /* Channel Trigger Source bit 7 mask. */ -#define DMA_CH_TRIGSRC7_bp 7 /* Channel Trigger Source bit 7 position. */ - -/* DMA.CTRL bit masks and bit positions */ -#define DMA_ENABLE_bm 0x80 /* Enable bit mask. */ -#define DMA_ENABLE_bp 7 /* Enable bit position. */ - -#define DMA_RESET_bm 0x40 /* Software Reset bit mask. */ -#define DMA_RESET_bp 6 /* Software Reset bit position. */ - -#define DMA_DBUFMODE_gm 0x0C /* Double Buffering Mode group mask. */ -#define DMA_DBUFMODE_gp 2 /* Double Buffering Mode group position. */ -#define DMA_DBUFMODE0_bm (1<<2) /* Double Buffering Mode bit 0 mask. */ -#define DMA_DBUFMODE0_bp 2 /* Double Buffering Mode bit 0 position. */ -#define DMA_DBUFMODE1_bm (1<<3) /* Double Buffering Mode bit 1 mask. */ -#define DMA_DBUFMODE1_bp 3 /* Double Buffering Mode bit 1 position. */ - -#define DMA_PRIMODE_gm 0x03 /* Channel Priority Mode group mask. */ -#define DMA_PRIMODE_gp 0 /* Channel Priority Mode group position. */ -#define DMA_PRIMODE0_bm (1<<0) /* Channel Priority Mode bit 0 mask. */ -#define DMA_PRIMODE0_bp 0 /* Channel Priority Mode bit 0 position. */ -#define DMA_PRIMODE1_bm (1<<1) /* Channel Priority Mode bit 1 mask. */ -#define DMA_PRIMODE1_bp 1 /* Channel Priority Mode bit 1 position. */ - -/* DMA.INTFLAGS bit masks and bit positions */ -#define DMA_CH3ERRIF_bm 0x80 /* Channel 3 Block Transfer Error Interrupt Flag bit mask. */ -#define DMA_CH3ERRIF_bp 7 /* Channel 3 Block Transfer Error Interrupt Flag bit position. */ - -#define DMA_CH2ERRIF_bm 0x40 /* Channel 2 Block Transfer Error Interrupt Flag bit mask. */ -#define DMA_CH2ERRIF_bp 6 /* Channel 2 Block Transfer Error Interrupt Flag bit position. */ - -#define DMA_CH1ERRIF_bm 0x20 /* Channel 1 Block Transfer Error Interrupt Flag bit mask. */ -#define DMA_CH1ERRIF_bp 5 /* Channel 1 Block Transfer Error Interrupt Flag bit position. */ - -#define DMA_CH0ERRIF_bm 0x10 /* Channel 0 Block Transfer Error Interrupt Flag bit mask. */ -#define DMA_CH0ERRIF_bp 4 /* Channel 0 Block Transfer Error Interrupt Flag bit position. */ - -#define DMA_CH3TRNIF_bm 0x08 /* Channel 3 Transaction Complete Interrupt Flag bit mask. */ -#define DMA_CH3TRNIF_bp 3 /* Channel 3 Transaction Complete Interrupt Flag bit position. */ - -#define DMA_CH2TRNIF_bm 0x04 /* Channel 2 Transaction Complete Interrupt Flag bit mask. */ -#define DMA_CH2TRNIF_bp 2 /* Channel 2 Transaction Complete Interrupt Flag bit position. */ - -#define DMA_CH1TRNIF_bm 0x02 /* Channel 1 Transaction Complete Interrupt Flag bit mask. */ -#define DMA_CH1TRNIF_bp 1 /* Channel 1 Transaction Complete Interrupt Flag bit position. */ - -#define DMA_CH0TRNIF_bm 0x01 /* Channel 0 Transaction Complete Interrupt Flag bit mask. */ -#define DMA_CH0TRNIF_bp 0 /* Channel 0 Transaction Complete Interrupt Flag bit position. */ - -/* DMA.STATUS bit masks and bit positions */ -#define DMA_CH3BUSY_bm 0x80 /* Channel 3 Block Transfer Busy bit mask. */ -#define DMA_CH3BUSY_bp 7 /* Channel 3 Block Transfer Busy bit position. */ - -#define DMA_CH2BUSY_bm 0x40 /* Channel 2 Block Transfer Busy bit mask. */ -#define DMA_CH2BUSY_bp 6 /* Channel 2 Block Transfer Busy bit position. */ - -#define DMA_CH1BUSY_bm 0x20 /* Channel 1 Block Transfer Busy bit mask. */ -#define DMA_CH1BUSY_bp 5 /* Channel 1 Block Transfer Busy bit position. */ - -#define DMA_CH0BUSY_bm 0x10 /* Channel 0 Block Transfer Busy bit mask. */ -#define DMA_CH0BUSY_bp 4 /* Channel 0 Block Transfer Busy bit position. */ - -#define DMA_CH3PEND_bm 0x08 /* Channel 3 Block Transfer Pending bit mask. */ -#define DMA_CH3PEND_bp 3 /* Channel 3 Block Transfer Pending bit position. */ - -#define DMA_CH2PEND_bm 0x04 /* Channel 2 Block Transfer Pending bit mask. */ -#define DMA_CH2PEND_bp 2 /* Channel 2 Block Transfer Pending bit position. */ - -#define DMA_CH1PEND_bm 0x02 /* Channel 1 Block Transfer Pending bit mask. */ -#define DMA_CH1PEND_bp 1 /* Channel 1 Block Transfer Pending bit position. */ - -#define DMA_CH0PEND_bm 0x01 /* Channel 0 Block Transfer Pending bit mask. */ -#define DMA_CH0PEND_bp 0 /* Channel 0 Block Transfer Pending bit position. */ - -/* EVSYS - Event System */ -/* EVSYS.CH0MUX bit masks and bit positions */ -#define EVSYS_CHMUX_gm 0xFF /* Event Channel 0 Multiplexer group mask. */ -#define EVSYS_CHMUX_gp 0 /* Event Channel 0 Multiplexer group position. */ -#define EVSYS_CHMUX0_bm (1<<0) /* Event Channel 0 Multiplexer bit 0 mask. */ -#define EVSYS_CHMUX0_bp 0 /* Event Channel 0 Multiplexer bit 0 position. */ -#define EVSYS_CHMUX1_bm (1<<1) /* Event Channel 0 Multiplexer bit 1 mask. */ -#define EVSYS_CHMUX1_bp 1 /* Event Channel 0 Multiplexer bit 1 position. */ -#define EVSYS_CHMUX2_bm (1<<2) /* Event Channel 0 Multiplexer bit 2 mask. */ -#define EVSYS_CHMUX2_bp 2 /* Event Channel 0 Multiplexer bit 2 position. */ -#define EVSYS_CHMUX3_bm (1<<3) /* Event Channel 0 Multiplexer bit 3 mask. */ -#define EVSYS_CHMUX3_bp 3 /* Event Channel 0 Multiplexer bit 3 position. */ -#define EVSYS_CHMUX4_bm (1<<4) /* Event Channel 0 Multiplexer bit 4 mask. */ -#define EVSYS_CHMUX4_bp 4 /* Event Channel 0 Multiplexer bit 4 position. */ -#define EVSYS_CHMUX5_bm (1<<5) /* Event Channel 0 Multiplexer bit 5 mask. */ -#define EVSYS_CHMUX5_bp 5 /* Event Channel 0 Multiplexer bit 5 position. */ -#define EVSYS_CHMUX6_bm (1<<6) /* Event Channel 0 Multiplexer bit 6 mask. */ -#define EVSYS_CHMUX6_bp 6 /* Event Channel 0 Multiplexer bit 6 position. */ -#define EVSYS_CHMUX7_bm (1<<7) /* Event Channel 0 Multiplexer bit 7 mask. */ -#define EVSYS_CHMUX7_bp 7 /* Event Channel 0 Multiplexer bit 7 position. */ - -/* EVSYS.CH1MUX bit masks and bit positions */ -/* EVSYS_CHMUX Predefined. */ -/* EVSYS_CHMUX Predefined. */ - -/* EVSYS.CH2MUX bit masks and bit positions */ -/* EVSYS_CHMUX Predefined. */ -/* EVSYS_CHMUX Predefined. */ - -/* EVSYS.CH3MUX bit masks and bit positions */ -/* EVSYS_CHMUX Predefined. */ -/* EVSYS_CHMUX Predefined. */ - -/* EVSYS.CH4MUX bit masks and bit positions */ -/* EVSYS_CHMUX Predefined. */ -/* EVSYS_CHMUX Predefined. */ - -/* EVSYS.CH5MUX bit masks and bit positions */ -/* EVSYS_CHMUX Predefined. */ -/* EVSYS_CHMUX Predefined. */ - -/* EVSYS.CH6MUX bit masks and bit positions */ -/* EVSYS_CHMUX Predefined. */ -/* EVSYS_CHMUX Predefined. */ - -/* EVSYS.CH7MUX bit masks and bit positions */ -/* EVSYS_CHMUX Predefined. */ -/* EVSYS_CHMUX Predefined. */ - -/* EVSYS.CH0CTRL bit masks and bit positions */ -#define EVSYS_QDIRM_gm 0x60 /* Quadrature Decoder Index Recognition Mode group mask. */ -#define EVSYS_QDIRM_gp 5 /* Quadrature Decoder Index Recognition Mode group position. */ -#define EVSYS_QDIRM0_bm (1<<5) /* Quadrature Decoder Index Recognition Mode bit 0 mask. */ -#define EVSYS_QDIRM0_bp 5 /* Quadrature Decoder Index Recognition Mode bit 0 position. */ -#define EVSYS_QDIRM1_bm (1<<6) /* Quadrature Decoder Index Recognition Mode bit 1 mask. */ -#define EVSYS_QDIRM1_bp 6 /* Quadrature Decoder Index Recognition Mode bit 1 position. */ - -#define EVSYS_QDIEN_bm 0x10 /* Quadrature Decoder Index Enable bit mask. */ -#define EVSYS_QDIEN_bp 4 /* Quadrature Decoder Index Enable bit position. */ - -#define EVSYS_QDEN_bm 0x08 /* Quadrature Decoder Enable bit mask. */ -#define EVSYS_QDEN_bp 3 /* Quadrature Decoder Enable bit position. */ - -#define EVSYS_DIGFILT_gm 0x07 /* Digital Filter group mask. */ -#define EVSYS_DIGFILT_gp 0 /* Digital Filter group position. */ -#define EVSYS_DIGFILT0_bm (1<<0) /* Digital Filter bit 0 mask. */ -#define EVSYS_DIGFILT0_bp 0 /* Digital Filter bit 0 position. */ -#define EVSYS_DIGFILT1_bm (1<<1) /* Digital Filter bit 1 mask. */ -#define EVSYS_DIGFILT1_bp 1 /* Digital Filter bit 1 position. */ -#define EVSYS_DIGFILT2_bm (1<<2) /* Digital Filter bit 2 mask. */ -#define EVSYS_DIGFILT2_bp 2 /* Digital Filter bit 2 position. */ - -/* EVSYS.CH1CTRL bit masks and bit positions */ -/* EVSYS_DIGFILT Predefined. */ -/* EVSYS_DIGFILT Predefined. */ - -/* EVSYS.CH2CTRL bit masks and bit positions */ -/* EVSYS_QDIRM Predefined. */ -/* EVSYS_QDIRM Predefined. */ - -/* EVSYS_QDIEN Predefined. */ -/* EVSYS_QDIEN Predefined. */ - -/* EVSYS_QDEN Predefined. */ -/* EVSYS_QDEN Predefined. */ - -/* EVSYS_DIGFILT Predefined. */ -/* EVSYS_DIGFILT Predefined. */ - -/* EVSYS.CH3CTRL bit masks and bit positions */ -/* EVSYS_DIGFILT Predefined. */ -/* EVSYS_DIGFILT Predefined. */ - -/* EVSYS.CH4CTRL bit masks and bit positions */ -/* EVSYS_QDIRM Predefined. */ -/* EVSYS_QDIRM Predefined. */ - -/* EVSYS_QDIEN Predefined. */ -/* EVSYS_QDIEN Predefined. */ - -/* EVSYS_QDEN Predefined. */ -/* EVSYS_QDEN Predefined. */ - -/* EVSYS_DIGFILT Predefined. */ -/* EVSYS_DIGFILT Predefined. */ - -/* EVSYS.CH5CTRL bit masks and bit positions */ -/* EVSYS_DIGFILT Predefined. */ -/* EVSYS_DIGFILT Predefined. */ - -/* EVSYS.CH6CTRL bit masks and bit positions */ -/* EVSYS_DIGFILT Predefined. */ -/* EVSYS_DIGFILT Predefined. */ - -/* EVSYS.CH7CTRL bit masks and bit positions */ -/* EVSYS_DIGFILT Predefined. */ -/* EVSYS_DIGFILT Predefined. */ - -/* NVM - Non Volatile Memory Controller */ -/* NVM.CMD bit masks and bit positions */ -#define NVM_CMD_gm 0x7F /* Command group mask. */ -#define NVM_CMD_gp 0 /* Command group position. */ -#define NVM_CMD0_bm (1<<0) /* Command bit 0 mask. */ -#define NVM_CMD0_bp 0 /* Command bit 0 position. */ -#define NVM_CMD1_bm (1<<1) /* Command bit 1 mask. */ -#define NVM_CMD1_bp 1 /* Command bit 1 position. */ -#define NVM_CMD2_bm (1<<2) /* Command bit 2 mask. */ -#define NVM_CMD2_bp 2 /* Command bit 2 position. */ -#define NVM_CMD3_bm (1<<3) /* Command bit 3 mask. */ -#define NVM_CMD3_bp 3 /* Command bit 3 position. */ -#define NVM_CMD4_bm (1<<4) /* Command bit 4 mask. */ -#define NVM_CMD4_bp 4 /* Command bit 4 position. */ -#define NVM_CMD5_bm (1<<5) /* Command bit 5 mask. */ -#define NVM_CMD5_bp 5 /* Command bit 5 position. */ -#define NVM_CMD6_bm (1<<6) /* Command bit 6 mask. */ -#define NVM_CMD6_bp 6 /* Command bit 6 position. */ - -/* NVM.CTRLA bit masks and bit positions */ -#define NVM_CMDEX_bm 0x01 /* Command Execute bit mask. */ -#define NVM_CMDEX_bp 0 /* Command Execute bit position. */ - -/* NVM.CTRLB bit masks and bit positions */ -#define NVM_EEMAPEN_bm 0x08 /* EEPROM Mapping Enable bit mask. */ -#define NVM_EEMAPEN_bp 3 /* EEPROM Mapping Enable bit position. */ - -#define NVM_FPRM_bm 0x04 /* Flash Power Reduction Enable bit mask. */ -#define NVM_FPRM_bp 2 /* Flash Power Reduction Enable bit position. */ - -#define NVM_EPRM_bm 0x02 /* EEPROM Power Reduction Enable bit mask. */ -#define NVM_EPRM_bp 1 /* EEPROM Power Reduction Enable bit position. */ - -#define NVM_SPMLOCK_bm 0x01 /* SPM Lock bit mask. */ -#define NVM_SPMLOCK_bp 0 /* SPM Lock bit position. */ - -/* NVM.INTCTRL bit masks and bit positions */ -#define NVM_SPMLVL_gm 0x0C /* SPM Interrupt Level group mask. */ -#define NVM_SPMLVL_gp 2 /* SPM Interrupt Level group position. */ -#define NVM_SPMLVL0_bm (1<<2) /* SPM Interrupt Level bit 0 mask. */ -#define NVM_SPMLVL0_bp 2 /* SPM Interrupt Level bit 0 position. */ -#define NVM_SPMLVL1_bm (1<<3) /* SPM Interrupt Level bit 1 mask. */ -#define NVM_SPMLVL1_bp 3 /* SPM Interrupt Level bit 1 position. */ - -#define NVM_EELVL_gm 0x03 /* EEPROM Interrupt Level group mask. */ -#define NVM_EELVL_gp 0 /* EEPROM Interrupt Level group position. */ -#define NVM_EELVL0_bm (1<<0) /* EEPROM Interrupt Level bit 0 mask. */ -#define NVM_EELVL0_bp 0 /* EEPROM Interrupt Level bit 0 position. */ -#define NVM_EELVL1_bm (1<<1) /* EEPROM Interrupt Level bit 1 mask. */ -#define NVM_EELVL1_bp 1 /* EEPROM Interrupt Level bit 1 position. */ - -/* NVM.STATUS bit masks and bit positions */ -#define NVM_NVMBUSY_bm 0x80 /* Non-volatile Memory Busy bit mask. */ -#define NVM_NVMBUSY_bp 7 /* Non-volatile Memory Busy bit position. */ - -#define NVM_FBUSY_bm 0x40 /* Flash Memory Busy bit mask. */ -#define NVM_FBUSY_bp 6 /* Flash Memory Busy bit position. */ - -#define NVM_EELOAD_bm 0x02 /* EEPROM Page Buffer Active Loading bit mask. */ -#define NVM_EELOAD_bp 1 /* EEPROM Page Buffer Active Loading bit position. */ - -#define NVM_FLOAD_bm 0x01 /* Flash Page Buffer Active Loading bit mask. */ -#define NVM_FLOAD_bp 0 /* Flash Page Buffer Active Loading bit position. */ - -/* NVM.LOCKBITS bit masks and bit positions */ -#define NVM_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ -#define NVM_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ -#define NVM_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ -#define NVM_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ -#define NVM_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ -#define NVM_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ - -#define NVM_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ -#define NVM_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ -#define NVM_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ -#define NVM_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ -#define NVM_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ -#define NVM_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ - -#define NVM_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ -#define NVM_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ -#define NVM_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ -#define NVM_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ -#define NVM_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ -#define NVM_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ - -#define NVM_LB_gm 0x03 /* Lock Bits group mask. */ -#define NVM_LB_gp 0 /* Lock Bits group position. */ -#define NVM_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ -#define NVM_LB0_bp 0 /* Lock Bits bit 0 position. */ -#define NVM_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ -#define NVM_LB1_bp 1 /* Lock Bits bit 1 position. */ - -/* ADC - Analog/Digital Converter */ -/* ADC_CH.CTRL bit masks and bit positions */ -#define ADC_CH_START_bm 0x80 /* Channel Start Conversion bit mask. */ -#define ADC_CH_START_bp 7 /* Channel Start Conversion bit position. */ - -#define ADC_CH_GAIN_gm 0x1C /* Gain Factor group mask. */ -#define ADC_CH_GAIN_gp 2 /* Gain Factor group position. */ -#define ADC_CH_GAIN0_bm (1<<2) /* Gain Factor bit 0 mask. */ -#define ADC_CH_GAIN0_bp 2 /* Gain Factor bit 0 position. */ -#define ADC_CH_GAIN1_bm (1<<3) /* Gain Factor bit 1 mask. */ -#define ADC_CH_GAIN1_bp 3 /* Gain Factor bit 1 position. */ -#define ADC_CH_GAIN2_bm (1<<4) /* Gain Factor bit 2 mask. */ -#define ADC_CH_GAIN2_bp 4 /* Gain Factor bit 2 position. */ - -#define ADC_CH_INPUTMODE_gm 0x03 /* Input Mode Select group mask. */ -#define ADC_CH_INPUTMODE_gp 0 /* Input Mode Select group position. */ -#define ADC_CH_INPUTMODE0_bm (1<<0) /* Input Mode Select bit 0 mask. */ -#define ADC_CH_INPUTMODE0_bp 0 /* Input Mode Select bit 0 position. */ -#define ADC_CH_INPUTMODE1_bm (1<<1) /* Input Mode Select bit 1 mask. */ -#define ADC_CH_INPUTMODE1_bp 1 /* Input Mode Select bit 1 position. */ - -/* ADC_CH.MUXCTRL bit masks and bit positions */ -#define ADC_CH_MUXPOS_gm 0x78 /* MUX selection on Positive ADC input group mask. */ -#define ADC_CH_MUXPOS_gp 3 /* MUX selection on Positive ADC input group position. */ -#define ADC_CH_MUXPOS0_bm (1<<3) /* MUX selection on Positive ADC input bit 0 mask. */ -#define ADC_CH_MUXPOS0_bp 3 /* MUX selection on Positive ADC input bit 0 position. */ -#define ADC_CH_MUXPOS1_bm (1<<4) /* MUX selection on Positive ADC input bit 1 mask. */ -#define ADC_CH_MUXPOS1_bp 4 /* MUX selection on Positive ADC input bit 1 position. */ -#define ADC_CH_MUXPOS2_bm (1<<5) /* MUX selection on Positive ADC input bit 2 mask. */ -#define ADC_CH_MUXPOS2_bp 5 /* MUX selection on Positive ADC input bit 2 position. */ -#define ADC_CH_MUXPOS3_bm (1<<6) /* MUX selection on Positive ADC input bit 3 mask. */ -#define ADC_CH_MUXPOS3_bp 6 /* MUX selection on Positive ADC input bit 3 position. */ - -#define ADC_CH_MUXINT_gm 0x78 /* MUX selection on Internal ADC input group mask. */ -#define ADC_CH_MUXINT_gp 3 /* MUX selection on Internal ADC input group position. */ -#define ADC_CH_MUXINT0_bm (1<<3) /* MUX selection on Internal ADC input bit 0 mask. */ -#define ADC_CH_MUXINT0_bp 3 /* MUX selection on Internal ADC input bit 0 position. */ -#define ADC_CH_MUXINT1_bm (1<<4) /* MUX selection on Internal ADC input bit 1 mask. */ -#define ADC_CH_MUXINT1_bp 4 /* MUX selection on Internal ADC input bit 1 position. */ -#define ADC_CH_MUXINT2_bm (1<<5) /* MUX selection on Internal ADC input bit 2 mask. */ -#define ADC_CH_MUXINT2_bp 5 /* MUX selection on Internal ADC input bit 2 position. */ -#define ADC_CH_MUXINT3_bm (1<<6) /* MUX selection on Internal ADC input bit 3 mask. */ -#define ADC_CH_MUXINT3_bp 6 /* MUX selection on Internal ADC input bit 3 position. */ - -#define ADC_CH_MUXNEG_gm 0x07 /* MUX selection on Negative ADC input group mask. */ -#define ADC_CH_MUXNEG_gp 0 /* MUX selection on Negative ADC input group position. */ -#define ADC_CH_MUXNEG0_bm (1<<0) /* MUX selection on Negative ADC input bit 0 mask. */ -#define ADC_CH_MUXNEG0_bp 0 /* MUX selection on Negative ADC input bit 0 position. */ -#define ADC_CH_MUXNEG1_bm (1<<1) /* MUX selection on Negative ADC input bit 1 mask. */ -#define ADC_CH_MUXNEG1_bp 1 /* MUX selection on Negative ADC input bit 1 position. */ -#define ADC_CH_MUXNEG2_bm (1<<2) /* MUX selection on Negative ADC input bit 2 mask. */ -#define ADC_CH_MUXNEG2_bp 2 /* MUX selection on Negative ADC input bit 2 position. */ - -/* ADC_CH.INTCTRL bit masks and bit positions */ -#define ADC_CH_INTMODE_gm 0x0C /* Interrupt Mode group mask. */ -#define ADC_CH_INTMODE_gp 2 /* Interrupt Mode group position. */ -#define ADC_CH_INTMODE0_bm (1<<2) /* Interrupt Mode bit 0 mask. */ -#define ADC_CH_INTMODE0_bp 2 /* Interrupt Mode bit 0 position. */ -#define ADC_CH_INTMODE1_bm (1<<3) /* Interrupt Mode bit 1 mask. */ -#define ADC_CH_INTMODE1_bp 3 /* Interrupt Mode bit 1 position. */ - -#define ADC_CH_INTLVL_gm 0x03 /* Interrupt Level group mask. */ -#define ADC_CH_INTLVL_gp 0 /* Interrupt Level group position. */ -#define ADC_CH_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */ -#define ADC_CH_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */ -#define ADC_CH_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ -#define ADC_CH_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */ - -/* ADC_CH.INTFLAGS bit masks and bit positions */ -#define ADC_CH_CHIF_bm 0x01 /* Channel Interrupt Flag bit mask. */ -#define ADC_CH_CHIF_bp 0 /* Channel Interrupt Flag bit position. */ - -/* ADC_CH.SCAN bit masks and bit positions */ -#define ADC_CH_OFFSET_gm 0xF0 /* Positive MUX setting offset group mask. */ -#define ADC_CH_OFFSET_gp 4 /* Positive MUX setting offset group position. */ -#define ADC_CH_OFFSET0_bm (1<<4) /* Positive MUX setting offset bit 0 mask. */ -#define ADC_CH_OFFSET0_bp 4 /* Positive MUX setting offset bit 0 position. */ -#define ADC_CH_OFFSET1_bm (1<<5) /* Positive MUX setting offset bit 1 mask. */ -#define ADC_CH_OFFSET1_bp 5 /* Positive MUX setting offset bit 1 position. */ -#define ADC_CH_OFFSET2_bm (1<<6) /* Positive MUX setting offset bit 2 mask. */ -#define ADC_CH_OFFSET2_bp 6 /* Positive MUX setting offset bit 2 position. */ -#define ADC_CH_OFFSET3_bm (1<<7) /* Positive MUX setting offset bit 3 mask. */ -#define ADC_CH_OFFSET3_bp 7 /* Positive MUX setting offset bit 3 position. */ - -#define ADC_CH_SCANNUM_gm 0x0F /* Number of Channels included in scan group mask. */ -#define ADC_CH_SCANNUM_gp 0 /* Number of Channels included in scan group position. */ -#define ADC_CH_SCANNUM0_bm (1<<0) /* Number of Channels included in scan bit 0 mask. */ -#define ADC_CH_SCANNUM0_bp 0 /* Number of Channels included in scan bit 0 position. */ -#define ADC_CH_SCANNUM1_bm (1<<1) /* Number of Channels included in scan bit 1 mask. */ -#define ADC_CH_SCANNUM1_bp 1 /* Number of Channels included in scan bit 1 position. */ -#define ADC_CH_SCANNUM2_bm (1<<2) /* Number of Channels included in scan bit 2 mask. */ -#define ADC_CH_SCANNUM2_bp 2 /* Number of Channels included in scan bit 2 position. */ -#define ADC_CH_SCANNUM3_bm (1<<3) /* Number of Channels included in scan bit 3 mask. */ -#define ADC_CH_SCANNUM3_bp 3 /* Number of Channels included in scan bit 3 position. */ - -/* ADC.CTRLA bit masks and bit positions */ -#define ADC_DMASEL_gm 0xC0 /* DMA Selection group mask. */ -#define ADC_DMASEL_gp 6 /* DMA Selection group position. */ -#define ADC_DMASEL0_bm (1<<6) /* DMA Selection bit 0 mask. */ -#define ADC_DMASEL0_bp 6 /* DMA Selection bit 0 position. */ -#define ADC_DMASEL1_bm (1<<7) /* DMA Selection bit 1 mask. */ -#define ADC_DMASEL1_bp 7 /* DMA Selection bit 1 position. */ - -#define ADC_CH3START_bm 0x20 /* Channel 3 Start Conversion bit mask. */ -#define ADC_CH3START_bp 5 /* Channel 3 Start Conversion bit position. */ - -#define ADC_CH2START_bm 0x10 /* Channel 2 Start Conversion bit mask. */ -#define ADC_CH2START_bp 4 /* Channel 2 Start Conversion bit position. */ - -#define ADC_CH1START_bm 0x08 /* Channel 1 Start Conversion bit mask. */ -#define ADC_CH1START_bp 3 /* Channel 1 Start Conversion bit position. */ - -#define ADC_CH0START_bm 0x04 /* Channel 0 Start Conversion bit mask. */ -#define ADC_CH0START_bp 2 /* Channel 0 Start Conversion bit position. */ - -#define ADC_FLUSH_bm 0x02 /* Flush Pipeline bit mask. */ -#define ADC_FLUSH_bp 1 /* Flush Pipeline bit position. */ - -#define ADC_ENABLE_bm 0x01 /* Enable ADC bit mask. */ -#define ADC_ENABLE_bp 0 /* Enable ADC bit position. */ - -/* ADC.CTRLB bit masks and bit positions */ -#define ADC_IMPMODE_bm 0x80 /* Gain Stage Impedance Mode bit mask. */ -#define ADC_IMPMODE_bp 7 /* Gain Stage Impedance Mode bit position. */ - -#define ADC_CURRLIMIT_gm 0x60 /* Current Limitation group mask. */ -#define ADC_CURRLIMIT_gp 5 /* Current Limitation group position. */ -#define ADC_CURRLIMIT0_bm (1<<5) /* Current Limitation bit 0 mask. */ -#define ADC_CURRLIMIT0_bp 5 /* Current Limitation bit 0 position. */ -#define ADC_CURRLIMIT1_bm (1<<6) /* Current Limitation bit 1 mask. */ -#define ADC_CURRLIMIT1_bp 6 /* Current Limitation bit 1 position. */ - -#define ADC_CONMODE_bm 0x10 /* Conversion Mode bit mask. */ -#define ADC_CONMODE_bp 4 /* Conversion Mode bit position. */ - -#define ADC_FREERUN_bm 0x08 /* Free Running Mode Enable bit mask. */ -#define ADC_FREERUN_bp 3 /* Free Running Mode Enable bit position. */ - -#define ADC_RESOLUTION_gm 0x06 /* Result Resolution group mask. */ -#define ADC_RESOLUTION_gp 1 /* Result Resolution group position. */ -#define ADC_RESOLUTION0_bm (1<<1) /* Result Resolution bit 0 mask. */ -#define ADC_RESOLUTION0_bp 1 /* Result Resolution bit 0 position. */ -#define ADC_RESOLUTION1_bm (1<<2) /* Result Resolution bit 1 mask. */ -#define ADC_RESOLUTION1_bp 2 /* Result Resolution bit 1 position. */ - -/* ADC.REFCTRL bit masks and bit positions */ -#define ADC_REFSEL_gm 0x70 /* Reference Selection group mask. */ -#define ADC_REFSEL_gp 4 /* Reference Selection group position. */ -#define ADC_REFSEL0_bm (1<<4) /* Reference Selection bit 0 mask. */ -#define ADC_REFSEL0_bp 4 /* Reference Selection bit 0 position. */ -#define ADC_REFSEL1_bm (1<<5) /* Reference Selection bit 1 mask. */ -#define ADC_REFSEL1_bp 5 /* Reference Selection bit 1 position. */ -#define ADC_REFSEL2_bm (1<<6) /* Reference Selection bit 2 mask. */ -#define ADC_REFSEL2_bp 6 /* Reference Selection bit 2 position. */ - -#define ADC_BANDGAP_bm 0x02 /* Bandgap enable bit mask. */ -#define ADC_BANDGAP_bp 1 /* Bandgap enable bit position. */ - -#define ADC_TEMPREF_bm 0x01 /* Temperature Reference Enable bit mask. */ -#define ADC_TEMPREF_bp 0 /* Temperature Reference Enable bit position. */ - -/* ADC.EVCTRL bit masks and bit positions */ -#define ADC_SWEEP_gm 0xC0 /* Channel Sweep Selection group mask. */ -#define ADC_SWEEP_gp 6 /* Channel Sweep Selection group position. */ -#define ADC_SWEEP0_bm (1<<6) /* Channel Sweep Selection bit 0 mask. */ -#define ADC_SWEEP0_bp 6 /* Channel Sweep Selection bit 0 position. */ -#define ADC_SWEEP1_bm (1<<7) /* Channel Sweep Selection bit 1 mask. */ -#define ADC_SWEEP1_bp 7 /* Channel Sweep Selection bit 1 position. */ - -#define ADC_EVSEL_gm 0x38 /* Event Input Select group mask. */ -#define ADC_EVSEL_gp 3 /* Event Input Select group position. */ -#define ADC_EVSEL0_bm (1<<3) /* Event Input Select bit 0 mask. */ -#define ADC_EVSEL0_bp 3 /* Event Input Select bit 0 position. */ -#define ADC_EVSEL1_bm (1<<4) /* Event Input Select bit 1 mask. */ -#define ADC_EVSEL1_bp 4 /* Event Input Select bit 1 position. */ -#define ADC_EVSEL2_bm (1<<5) /* Event Input Select bit 2 mask. */ -#define ADC_EVSEL2_bp 5 /* Event Input Select bit 2 position. */ - -#define ADC_EVACT_gm 0x07 /* Event Action Select group mask. */ -#define ADC_EVACT_gp 0 /* Event Action Select group position. */ -#define ADC_EVACT0_bm (1<<0) /* Event Action Select bit 0 mask. */ -#define ADC_EVACT0_bp 0 /* Event Action Select bit 0 position. */ -#define ADC_EVACT1_bm (1<<1) /* Event Action Select bit 1 mask. */ -#define ADC_EVACT1_bp 1 /* Event Action Select bit 1 position. */ -#define ADC_EVACT2_bm (1<<2) /* Event Action Select bit 2 mask. */ -#define ADC_EVACT2_bp 2 /* Event Action Select bit 2 position. */ - -/* ADC.PRESCALER bit masks and bit positions */ -#define ADC_PRESCALER_gm 0x07 /* Clock Prescaler Selection group mask. */ -#define ADC_PRESCALER_gp 0 /* Clock Prescaler Selection group position. */ -#define ADC_PRESCALER0_bm (1<<0) /* Clock Prescaler Selection bit 0 mask. */ -#define ADC_PRESCALER0_bp 0 /* Clock Prescaler Selection bit 0 position. */ -#define ADC_PRESCALER1_bm (1<<1) /* Clock Prescaler Selection bit 1 mask. */ -#define ADC_PRESCALER1_bp 1 /* Clock Prescaler Selection bit 1 position. */ -#define ADC_PRESCALER2_bm (1<<2) /* Clock Prescaler Selection bit 2 mask. */ -#define ADC_PRESCALER2_bp 2 /* Clock Prescaler Selection bit 2 position. */ - -/* ADC.INTFLAGS bit masks and bit positions */ -#define ADC_CH3IF_bm 0x08 /* Channel 3 Interrupt Flag bit mask. */ -#define ADC_CH3IF_bp 3 /* Channel 3 Interrupt Flag bit position. */ - -#define ADC_CH2IF_bm 0x04 /* Channel 2 Interrupt Flag bit mask. */ -#define ADC_CH2IF_bp 2 /* Channel 2 Interrupt Flag bit position. */ - -#define ADC_CH1IF_bm 0x02 /* Channel 1 Interrupt Flag bit mask. */ -#define ADC_CH1IF_bp 1 /* Channel 1 Interrupt Flag bit position. */ - -#define ADC_CH0IF_bm 0x01 /* Channel 0 Interrupt Flag bit mask. */ -#define ADC_CH0IF_bp 0 /* Channel 0 Interrupt Flag bit position. */ - -/* DAC - Digital/Analog Converter */ -/* DAC.CTRLA bit masks and bit positions */ -#define DAC_IDOEN_bm 0x10 /* Internal Output Enable bit mask. */ -#define DAC_IDOEN_bp 4 /* Internal Output Enable bit position. */ - -#define DAC_CH1EN_bm 0x08 /* Channel 1 Output Enable bit mask. */ -#define DAC_CH1EN_bp 3 /* Channel 1 Output Enable bit position. */ - -#define DAC_CH0EN_bm 0x04 /* Channel 0 Output Enable bit mask. */ -#define DAC_CH0EN_bp 2 /* Channel 0 Output Enable bit position. */ - -#define DAC_LPMODE_bm 0x02 /* Low Power Mode bit mask. */ -#define DAC_LPMODE_bp 1 /* Low Power Mode bit position. */ - -#define DAC_ENABLE_bm 0x01 /* Enable bit mask. */ -#define DAC_ENABLE_bp 0 /* Enable bit position. */ - -/* DAC.CTRLB bit masks and bit positions */ -#define DAC_CHSEL_gm 0x60 /* Channel Select group mask. */ -#define DAC_CHSEL_gp 5 /* Channel Select group position. */ -#define DAC_CHSEL0_bm (1<<5) /* Channel Select bit 0 mask. */ -#define DAC_CHSEL0_bp 5 /* Channel Select bit 0 position. */ -#define DAC_CHSEL1_bm (1<<6) /* Channel Select bit 1 mask. */ -#define DAC_CHSEL1_bp 6 /* Channel Select bit 1 position. */ - -#define DAC_CH1TRIG_bm 0x02 /* Channel 1 Event Trig Enable bit mask. */ -#define DAC_CH1TRIG_bp 1 /* Channel 1 Event Trig Enable bit position. */ - -#define DAC_CH0TRIG_bm 0x01 /* Channel 0 Event Trig Enable bit mask. */ -#define DAC_CH0TRIG_bp 0 /* Channel 0 Event Trig Enable bit position. */ - -/* DAC.CTRLC bit masks and bit positions */ -#define DAC_REFSEL_gm 0x18 /* Reference Select group mask. */ -#define DAC_REFSEL_gp 3 /* Reference Select group position. */ -#define DAC_REFSEL0_bm (1<<3) /* Reference Select bit 0 mask. */ -#define DAC_REFSEL0_bp 3 /* Reference Select bit 0 position. */ -#define DAC_REFSEL1_bm (1<<4) /* Reference Select bit 1 mask. */ -#define DAC_REFSEL1_bp 4 /* Reference Select bit 1 position. */ - -#define DAC_LEFTADJ_bm 0x01 /* Left-adjust Result bit mask. */ -#define DAC_LEFTADJ_bp 0 /* Left-adjust Result bit position. */ - -/* DAC.EVCTRL bit masks and bit positions */ -#define DAC_EVSPLIT_bm 0x08 /* Separate Event Channel Input for Channel 1 bit mask. */ -#define DAC_EVSPLIT_bp 3 /* Separate Event Channel Input for Channel 1 bit position. */ - -#define DAC_EVSEL_gm 0x07 /* Event Input Selection group mask. */ -#define DAC_EVSEL_gp 0 /* Event Input Selection group position. */ -#define DAC_EVSEL0_bm (1<<0) /* Event Input Selection bit 0 mask. */ -#define DAC_EVSEL0_bp 0 /* Event Input Selection bit 0 position. */ -#define DAC_EVSEL1_bm (1<<1) /* Event Input Selection bit 1 mask. */ -#define DAC_EVSEL1_bp 1 /* Event Input Selection bit 1 position. */ -#define DAC_EVSEL2_bm (1<<2) /* Event Input Selection bit 2 mask. */ -#define DAC_EVSEL2_bp 2 /* Event Input Selection bit 2 position. */ - -/* DAC.STATUS bit masks and bit positions */ -#define DAC_CH1DRE_bm 0x02 /* Channel 1 Data Register Empty bit mask. */ -#define DAC_CH1DRE_bp 1 /* Channel 1 Data Register Empty bit position. */ - -#define DAC_CH0DRE_bm 0x01 /* Channel 0 Data Register Empty bit mask. */ -#define DAC_CH0DRE_bp 0 /* Channel 0 Data Register Empty bit position. */ - -/* DAC.CH0GAINCAL bit masks and bit positions */ -#define DAC_CH0GAINCAL_gm 0x7F /* Gain Calibration group mask. */ -#define DAC_CH0GAINCAL_gp 0 /* Gain Calibration group position. */ -#define DAC_CH0GAINCAL0_bm (1<<0) /* Gain Calibration bit 0 mask. */ -#define DAC_CH0GAINCAL0_bp 0 /* Gain Calibration bit 0 position. */ -#define DAC_CH0GAINCAL1_bm (1<<1) /* Gain Calibration bit 1 mask. */ -#define DAC_CH0GAINCAL1_bp 1 /* Gain Calibration bit 1 position. */ -#define DAC_CH0GAINCAL2_bm (1<<2) /* Gain Calibration bit 2 mask. */ -#define DAC_CH0GAINCAL2_bp 2 /* Gain Calibration bit 2 position. */ -#define DAC_CH0GAINCAL3_bm (1<<3) /* Gain Calibration bit 3 mask. */ -#define DAC_CH0GAINCAL3_bp 3 /* Gain Calibration bit 3 position. */ -#define DAC_CH0GAINCAL4_bm (1<<4) /* Gain Calibration bit 4 mask. */ -#define DAC_CH0GAINCAL4_bp 4 /* Gain Calibration bit 4 position. */ -#define DAC_CH0GAINCAL5_bm (1<<5) /* Gain Calibration bit 5 mask. */ -#define DAC_CH0GAINCAL5_bp 5 /* Gain Calibration bit 5 position. */ -#define DAC_CH0GAINCAL6_bm (1<<6) /* Gain Calibration bit 6 mask. */ -#define DAC_CH0GAINCAL6_bp 6 /* Gain Calibration bit 6 position. */ - -/* DAC.CH0OFFSETCAL bit masks and bit positions */ -#define DAC_CH0OFFSETCAL_gm 0x7F /* Offset Calibration group mask. */ -#define DAC_CH0OFFSETCAL_gp 0 /* Offset Calibration group position. */ -#define DAC_CH0OFFSETCAL0_bm (1<<0) /* Offset Calibration bit 0 mask. */ -#define DAC_CH0OFFSETCAL0_bp 0 /* Offset Calibration bit 0 position. */ -#define DAC_CH0OFFSETCAL1_bm (1<<1) /* Offset Calibration bit 1 mask. */ -#define DAC_CH0OFFSETCAL1_bp 1 /* Offset Calibration bit 1 position. */ -#define DAC_CH0OFFSETCAL2_bm (1<<2) /* Offset Calibration bit 2 mask. */ -#define DAC_CH0OFFSETCAL2_bp 2 /* Offset Calibration bit 2 position. */ -#define DAC_CH0OFFSETCAL3_bm (1<<3) /* Offset Calibration bit 3 mask. */ -#define DAC_CH0OFFSETCAL3_bp 3 /* Offset Calibration bit 3 position. */ -#define DAC_CH0OFFSETCAL4_bm (1<<4) /* Offset Calibration bit 4 mask. */ -#define DAC_CH0OFFSETCAL4_bp 4 /* Offset Calibration bit 4 position. */ -#define DAC_CH0OFFSETCAL5_bm (1<<5) /* Offset Calibration bit 5 mask. */ -#define DAC_CH0OFFSETCAL5_bp 5 /* Offset Calibration bit 5 position. */ -#define DAC_CH0OFFSETCAL6_bm (1<<6) /* Offset Calibration bit 6 mask. */ -#define DAC_CH0OFFSETCAL6_bp 6 /* Offset Calibration bit 6 position. */ - -/* DAC.CH1GAINCAL bit masks and bit positions */ -#define DAC_CH1GAINCAL_gm 0x7F /* Gain Calibration group mask. */ -#define DAC_CH1GAINCAL_gp 0 /* Gain Calibration group position. */ -#define DAC_CH1GAINCAL0_bm (1<<0) /* Gain Calibration bit 0 mask. */ -#define DAC_CH1GAINCAL0_bp 0 /* Gain Calibration bit 0 position. */ -#define DAC_CH1GAINCAL1_bm (1<<1) /* Gain Calibration bit 1 mask. */ -#define DAC_CH1GAINCAL1_bp 1 /* Gain Calibration bit 1 position. */ -#define DAC_CH1GAINCAL2_bm (1<<2) /* Gain Calibration bit 2 mask. */ -#define DAC_CH1GAINCAL2_bp 2 /* Gain Calibration bit 2 position. */ -#define DAC_CH1GAINCAL3_bm (1<<3) /* Gain Calibration bit 3 mask. */ -#define DAC_CH1GAINCAL3_bp 3 /* Gain Calibration bit 3 position. */ -#define DAC_CH1GAINCAL4_bm (1<<4) /* Gain Calibration bit 4 mask. */ -#define DAC_CH1GAINCAL4_bp 4 /* Gain Calibration bit 4 position. */ -#define DAC_CH1GAINCAL5_bm (1<<5) /* Gain Calibration bit 5 mask. */ -#define DAC_CH1GAINCAL5_bp 5 /* Gain Calibration bit 5 position. */ -#define DAC_CH1GAINCAL6_bm (1<<6) /* Gain Calibration bit 6 mask. */ -#define DAC_CH1GAINCAL6_bp 6 /* Gain Calibration bit 6 position. */ - -/* DAC.CH1OFFSETCAL bit masks and bit positions */ -#define DAC_CH1OFFSETCAL_gm 0x7F /* Offset Calibration group mask. */ -#define DAC_CH1OFFSETCAL_gp 0 /* Offset Calibration group position. */ -#define DAC_CH1OFFSETCAL0_bm (1<<0) /* Offset Calibration bit 0 mask. */ -#define DAC_CH1OFFSETCAL0_bp 0 /* Offset Calibration bit 0 position. */ -#define DAC_CH1OFFSETCAL1_bm (1<<1) /* Offset Calibration bit 1 mask. */ -#define DAC_CH1OFFSETCAL1_bp 1 /* Offset Calibration bit 1 position. */ -#define DAC_CH1OFFSETCAL2_bm (1<<2) /* Offset Calibration bit 2 mask. */ -#define DAC_CH1OFFSETCAL2_bp 2 /* Offset Calibration bit 2 position. */ -#define DAC_CH1OFFSETCAL3_bm (1<<3) /* Offset Calibration bit 3 mask. */ -#define DAC_CH1OFFSETCAL3_bp 3 /* Offset Calibration bit 3 position. */ -#define DAC_CH1OFFSETCAL4_bm (1<<4) /* Offset Calibration bit 4 mask. */ -#define DAC_CH1OFFSETCAL4_bp 4 /* Offset Calibration bit 4 position. */ -#define DAC_CH1OFFSETCAL5_bm (1<<5) /* Offset Calibration bit 5 mask. */ -#define DAC_CH1OFFSETCAL5_bp 5 /* Offset Calibration bit 5 position. */ -#define DAC_CH1OFFSETCAL6_bm (1<<6) /* Offset Calibration bit 6 mask. */ -#define DAC_CH1OFFSETCAL6_bp 6 /* Offset Calibration bit 6 position. */ - -/* AC - Analog Comparator */ -/* AC.AC0CTRL bit masks and bit positions */ -#define AC_INTMODE_gm 0xC0 /* Interrupt Mode group mask. */ -#define AC_INTMODE_gp 6 /* Interrupt Mode group position. */ -#define AC_INTMODE0_bm (1<<6) /* Interrupt Mode bit 0 mask. */ -#define AC_INTMODE0_bp 6 /* Interrupt Mode bit 0 position. */ -#define AC_INTMODE1_bm (1<<7) /* Interrupt Mode bit 1 mask. */ -#define AC_INTMODE1_bp 7 /* Interrupt Mode bit 1 position. */ - -#define AC_INTLVL_gm 0x30 /* Interrupt Level group mask. */ -#define AC_INTLVL_gp 4 /* Interrupt Level group position. */ -#define AC_INTLVL0_bm (1<<4) /* Interrupt Level bit 0 mask. */ -#define AC_INTLVL0_bp 4 /* Interrupt Level bit 0 position. */ -#define AC_INTLVL1_bm (1<<5) /* Interrupt Level bit 1 mask. */ -#define AC_INTLVL1_bp 5 /* Interrupt Level bit 1 position. */ - -#define AC_HSMODE_bm 0x08 /* High-speed Mode bit mask. */ -#define AC_HSMODE_bp 3 /* High-speed Mode bit position. */ - -#define AC_HYSMODE_gm 0x06 /* Hysteresis Mode group mask. */ -#define AC_HYSMODE_gp 1 /* Hysteresis Mode group position. */ -#define AC_HYSMODE0_bm (1<<1) /* Hysteresis Mode bit 0 mask. */ -#define AC_HYSMODE0_bp 1 /* Hysteresis Mode bit 0 position. */ -#define AC_HYSMODE1_bm (1<<2) /* Hysteresis Mode bit 1 mask. */ -#define AC_HYSMODE1_bp 2 /* Hysteresis Mode bit 1 position. */ - -#define AC_ENABLE_bm 0x01 /* Enable bit mask. */ -#define AC_ENABLE_bp 0 /* Enable bit position. */ - -/* AC.AC1CTRL bit masks and bit positions */ -/* AC_INTMODE Predefined. */ -/* AC_INTMODE Predefined. */ - -/* AC_INTLVL Predefined. */ -/* AC_INTLVL Predefined. */ - -/* AC_HSMODE Predefined. */ -/* AC_HSMODE Predefined. */ - -/* AC_HYSMODE Predefined. */ -/* AC_HYSMODE Predefined. */ - -/* AC_ENABLE Predefined. */ -/* AC_ENABLE Predefined. */ - -/* AC.AC0MUXCTRL bit masks and bit positions */ -#define AC_MUXPOS_gm 0x38 /* MUX Positive Input group mask. */ -#define AC_MUXPOS_gp 3 /* MUX Positive Input group position. */ -#define AC_MUXPOS0_bm (1<<3) /* MUX Positive Input bit 0 mask. */ -#define AC_MUXPOS0_bp 3 /* MUX Positive Input bit 0 position. */ -#define AC_MUXPOS1_bm (1<<4) /* MUX Positive Input bit 1 mask. */ -#define AC_MUXPOS1_bp 4 /* MUX Positive Input bit 1 position. */ -#define AC_MUXPOS2_bm (1<<5) /* MUX Positive Input bit 2 mask. */ -#define AC_MUXPOS2_bp 5 /* MUX Positive Input bit 2 position. */ - -#define AC_MUXNEG_gm 0x07 /* MUX Negative Input group mask. */ -#define AC_MUXNEG_gp 0 /* MUX Negative Input group position. */ -#define AC_MUXNEG0_bm (1<<0) /* MUX Negative Input bit 0 mask. */ -#define AC_MUXNEG0_bp 0 /* MUX Negative Input bit 0 position. */ -#define AC_MUXNEG1_bm (1<<1) /* MUX Negative Input bit 1 mask. */ -#define AC_MUXNEG1_bp 1 /* MUX Negative Input bit 1 position. */ -#define AC_MUXNEG2_bm (1<<2) /* MUX Negative Input bit 2 mask. */ -#define AC_MUXNEG2_bp 2 /* MUX Negative Input bit 2 position. */ - -/* AC.AC1MUXCTRL bit masks and bit positions */ -/* AC_MUXPOS Predefined. */ -/* AC_MUXPOS Predefined. */ - -/* AC_MUXNEG Predefined. */ -/* AC_MUXNEG Predefined. */ - -/* AC.CTRLA bit masks and bit positions */ -#define AC_AC1OUT_bm 0x02 /* Analog Comparator 1 Output Enable bit mask. */ -#define AC_AC1OUT_bp 1 /* Analog Comparator 1 Output Enable bit position. */ - -#define AC_AC0OUT_bm 0x01 /* Analog Comparator 0 Output Enable bit mask. */ -#define AC_AC0OUT_bp 0 /* Analog Comparator 0 Output Enable bit position. */ - -/* AC.CTRLB bit masks and bit positions */ -#define AC_SCALEFAC_gm 0x3F /* VCC Voltage Scaler Factor group mask. */ -#define AC_SCALEFAC_gp 0 /* VCC Voltage Scaler Factor group position. */ -#define AC_SCALEFAC0_bm (1<<0) /* VCC Voltage Scaler Factor bit 0 mask. */ -#define AC_SCALEFAC0_bp 0 /* VCC Voltage Scaler Factor bit 0 position. */ -#define AC_SCALEFAC1_bm (1<<1) /* VCC Voltage Scaler Factor bit 1 mask. */ -#define AC_SCALEFAC1_bp 1 /* VCC Voltage Scaler Factor bit 1 position. */ -#define AC_SCALEFAC2_bm (1<<2) /* VCC Voltage Scaler Factor bit 2 mask. */ -#define AC_SCALEFAC2_bp 2 /* VCC Voltage Scaler Factor bit 2 position. */ -#define AC_SCALEFAC3_bm (1<<3) /* VCC Voltage Scaler Factor bit 3 mask. */ -#define AC_SCALEFAC3_bp 3 /* VCC Voltage Scaler Factor bit 3 position. */ -#define AC_SCALEFAC4_bm (1<<4) /* VCC Voltage Scaler Factor bit 4 mask. */ -#define AC_SCALEFAC4_bp 4 /* VCC Voltage Scaler Factor bit 4 position. */ -#define AC_SCALEFAC5_bm (1<<5) /* VCC Voltage Scaler Factor bit 5 mask. */ -#define AC_SCALEFAC5_bp 5 /* VCC Voltage Scaler Factor bit 5 position. */ - -/* AC.WINCTRL bit masks and bit positions */ -#define AC_WEN_bm 0x10 /* Window Mode Enable bit mask. */ -#define AC_WEN_bp 4 /* Window Mode Enable bit position. */ - -#define AC_WINTMODE_gm 0x0C /* Window Interrupt Mode group mask. */ -#define AC_WINTMODE_gp 2 /* Window Interrupt Mode group position. */ -#define AC_WINTMODE0_bm (1<<2) /* Window Interrupt Mode bit 0 mask. */ -#define AC_WINTMODE0_bp 2 /* Window Interrupt Mode bit 0 position. */ -#define AC_WINTMODE1_bm (1<<3) /* Window Interrupt Mode bit 1 mask. */ -#define AC_WINTMODE1_bp 3 /* Window Interrupt Mode bit 1 position. */ - -#define AC_WINTLVL_gm 0x03 /* Window Interrupt Level group mask. */ -#define AC_WINTLVL_gp 0 /* Window Interrupt Level group position. */ -#define AC_WINTLVL0_bm (1<<0) /* Window Interrupt Level bit 0 mask. */ -#define AC_WINTLVL0_bp 0 /* Window Interrupt Level bit 0 position. */ -#define AC_WINTLVL1_bm (1<<1) /* Window Interrupt Level bit 1 mask. */ -#define AC_WINTLVL1_bp 1 /* Window Interrupt Level bit 1 position. */ - -/* AC.STATUS bit masks and bit positions */ -#define AC_WSTATE_gm 0xC0 /* Window Mode State group mask. */ -#define AC_WSTATE_gp 6 /* Window Mode State group position. */ -#define AC_WSTATE0_bm (1<<6) /* Window Mode State bit 0 mask. */ -#define AC_WSTATE0_bp 6 /* Window Mode State bit 0 position. */ -#define AC_WSTATE1_bm (1<<7) /* Window Mode State bit 1 mask. */ -#define AC_WSTATE1_bp 7 /* Window Mode State bit 1 position. */ - -#define AC_AC1STATE_bm 0x20 /* Analog Comparator 1 State bit mask. */ -#define AC_AC1STATE_bp 5 /* Analog Comparator 1 State bit position. */ - -#define AC_AC0STATE_bm 0x10 /* Analog Comparator 0 State bit mask. */ -#define AC_AC0STATE_bp 4 /* Analog Comparator 0 State bit position. */ - -#define AC_WIF_bm 0x04 /* Window Mode Interrupt Flag bit mask. */ -#define AC_WIF_bp 2 /* Window Mode Interrupt Flag bit position. */ - -#define AC_AC1IF_bm 0x02 /* Analog Comparator 1 Interrupt Flag bit mask. */ -#define AC_AC1IF_bp 1 /* Analog Comparator 1 Interrupt Flag bit position. */ - -#define AC_AC0IF_bm 0x01 /* Analog Comparator 0 Interrupt Flag bit mask. */ -#define AC_AC0IF_bp 0 /* Analog Comparator 0 Interrupt Flag bit position. */ - -/* RTC - Real-Time Counter */ -/* RTC.CTRL bit masks and bit positions */ -#define RTC_PRESCALER_gm 0x07 /* Prescaling Factor group mask. */ -#define RTC_PRESCALER_gp 0 /* Prescaling Factor group position. */ -#define RTC_PRESCALER0_bm (1<<0) /* Prescaling Factor bit 0 mask. */ -#define RTC_PRESCALER0_bp 0 /* Prescaling Factor bit 0 position. */ -#define RTC_PRESCALER1_bm (1<<1) /* Prescaling Factor bit 1 mask. */ -#define RTC_PRESCALER1_bp 1 /* Prescaling Factor bit 1 position. */ -#define RTC_PRESCALER2_bm (1<<2) /* Prescaling Factor bit 2 mask. */ -#define RTC_PRESCALER2_bp 2 /* Prescaling Factor bit 2 position. */ - -/* RTC.STATUS bit masks and bit positions */ -#define RTC_SYNCBUSY_bm 0x01 /* Synchronization Busy Flag bit mask. */ -#define RTC_SYNCBUSY_bp 0 /* Synchronization Busy Flag bit position. */ - -/* RTC.INTCTRL bit masks and bit positions */ -#define RTC_COMPINTLVL_gm 0x0C /* Compare Match Interrupt Level group mask. */ -#define RTC_COMPINTLVL_gp 2 /* Compare Match Interrupt Level group position. */ -#define RTC_COMPINTLVL0_bm (1<<2) /* Compare Match Interrupt Level bit 0 mask. */ -#define RTC_COMPINTLVL0_bp 2 /* Compare Match Interrupt Level bit 0 position. */ -#define RTC_COMPINTLVL1_bm (1<<3) /* Compare Match Interrupt Level bit 1 mask. */ -#define RTC_COMPINTLVL1_bp 3 /* Compare Match Interrupt Level bit 1 position. */ - -#define RTC_OVFINTLVL_gm 0x03 /* Overflow Interrupt Level group mask. */ -#define RTC_OVFINTLVL_gp 0 /* Overflow Interrupt Level group position. */ -#define RTC_OVFINTLVL0_bm (1<<0) /* Overflow Interrupt Level bit 0 mask. */ -#define RTC_OVFINTLVL0_bp 0 /* Overflow Interrupt Level bit 0 position. */ -#define RTC_OVFINTLVL1_bm (1<<1) /* Overflow Interrupt Level bit 1 mask. */ -#define RTC_OVFINTLVL1_bp 1 /* Overflow Interrupt Level bit 1 position. */ - -/* RTC.INTFLAGS bit masks and bit positions */ -#define RTC_COMPIF_bm 0x02 /* Compare Match Interrupt Flag bit mask. */ -#define RTC_COMPIF_bp 1 /* Compare Match Interrupt Flag bit position. */ - -#define RTC_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ -#define RTC_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ - -/* TWI - Two-Wire Interface */ -/* TWI_MASTER.CTRLA bit masks and bit positions */ -#define TWI_MASTER_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ -#define TWI_MASTER_INTLVL_gp 6 /* Interrupt Level group position. */ -#define TWI_MASTER_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ -#define TWI_MASTER_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ -#define TWI_MASTER_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ -#define TWI_MASTER_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ - -#define TWI_MASTER_RIEN_bm 0x20 /* Read Interrupt Enable bit mask. */ -#define TWI_MASTER_RIEN_bp 5 /* Read Interrupt Enable bit position. */ - -#define TWI_MASTER_WIEN_bm 0x10 /* Write Interrupt Enable bit mask. */ -#define TWI_MASTER_WIEN_bp 4 /* Write Interrupt Enable bit position. */ - -#define TWI_MASTER_ENABLE_bm 0x08 /* Enable TWI Master bit mask. */ -#define TWI_MASTER_ENABLE_bp 3 /* Enable TWI Master bit position. */ - -/* TWI_MASTER.CTRLB bit masks and bit positions */ -#define TWI_MASTER_TIMEOUT_gm 0x0C /* Inactive Bus Timeout group mask. */ -#define TWI_MASTER_TIMEOUT_gp 2 /* Inactive Bus Timeout group position. */ -#define TWI_MASTER_TIMEOUT0_bm (1<<2) /* Inactive Bus Timeout bit 0 mask. */ -#define TWI_MASTER_TIMEOUT0_bp 2 /* Inactive Bus Timeout bit 0 position. */ -#define TWI_MASTER_TIMEOUT1_bm (1<<3) /* Inactive Bus Timeout bit 1 mask. */ -#define TWI_MASTER_TIMEOUT1_bp 3 /* Inactive Bus Timeout bit 1 position. */ - -#define TWI_MASTER_QCEN_bm 0x02 /* Quick Command Enable bit mask. */ -#define TWI_MASTER_QCEN_bp 1 /* Quick Command Enable bit position. */ - -#define TWI_MASTER_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ -#define TWI_MASTER_SMEN_bp 0 /* Smart Mode Enable bit position. */ - -/* TWI_MASTER.CTRLC bit masks and bit positions */ -#define TWI_MASTER_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ -#define TWI_MASTER_ACKACT_bp 2 /* Acknowledge Action bit position. */ - -#define TWI_MASTER_CMD_gm 0x03 /* Command group mask. */ -#define TWI_MASTER_CMD_gp 0 /* Command group position. */ -#define TWI_MASTER_CMD0_bm (1<<0) /* Command bit 0 mask. */ -#define TWI_MASTER_CMD0_bp 0 /* Command bit 0 position. */ -#define TWI_MASTER_CMD1_bm (1<<1) /* Command bit 1 mask. */ -#define TWI_MASTER_CMD1_bp 1 /* Command bit 1 position. */ - -/* TWI_MASTER.STATUS bit masks and bit positions */ -#define TWI_MASTER_RIF_bm 0x80 /* Read Interrupt Flag bit mask. */ -#define TWI_MASTER_RIF_bp 7 /* Read Interrupt Flag bit position. */ - -#define TWI_MASTER_WIF_bm 0x40 /* Write Interrupt Flag bit mask. */ -#define TWI_MASTER_WIF_bp 6 /* Write Interrupt Flag bit position. */ - -#define TWI_MASTER_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ -#define TWI_MASTER_CLKHOLD_bp 5 /* Clock Hold bit position. */ - -#define TWI_MASTER_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ -#define TWI_MASTER_RXACK_bp 4 /* Received Acknowledge bit position. */ - -#define TWI_MASTER_ARBLOST_bm 0x08 /* Arbitration Lost bit mask. */ -#define TWI_MASTER_ARBLOST_bp 3 /* Arbitration Lost bit position. */ - -#define TWI_MASTER_BUSERR_bm 0x04 /* Bus Error bit mask. */ -#define TWI_MASTER_BUSERR_bp 2 /* Bus Error bit position. */ - -#define TWI_MASTER_BUSSTATE_gm 0x03 /* Bus State group mask. */ -#define TWI_MASTER_BUSSTATE_gp 0 /* Bus State group position. */ -#define TWI_MASTER_BUSSTATE0_bm (1<<0) /* Bus State bit 0 mask. */ -#define TWI_MASTER_BUSSTATE0_bp 0 /* Bus State bit 0 position. */ -#define TWI_MASTER_BUSSTATE1_bm (1<<1) /* Bus State bit 1 mask. */ -#define TWI_MASTER_BUSSTATE1_bp 1 /* Bus State bit 1 position. */ - -/* TWI_SLAVE.CTRLA bit masks and bit positions */ -#define TWI_SLAVE_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ -#define TWI_SLAVE_INTLVL_gp 6 /* Interrupt Level group position. */ -#define TWI_SLAVE_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ -#define TWI_SLAVE_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ -#define TWI_SLAVE_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ -#define TWI_SLAVE_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ - -#define TWI_SLAVE_DIEN_bm 0x20 /* Data Interrupt Enable bit mask. */ -#define TWI_SLAVE_DIEN_bp 5 /* Data Interrupt Enable bit position. */ - -#define TWI_SLAVE_APIEN_bm 0x10 /* Address/Stop Interrupt Enable bit mask. */ -#define TWI_SLAVE_APIEN_bp 4 /* Address/Stop Interrupt Enable bit position. */ - -#define TWI_SLAVE_ENABLE_bm 0x08 /* Enable TWI Slave bit mask. */ -#define TWI_SLAVE_ENABLE_bp 3 /* Enable TWI Slave bit position. */ - -#define TWI_SLAVE_PIEN_bm 0x04 /* Stop Interrupt Enable bit mask. */ -#define TWI_SLAVE_PIEN_bp 2 /* Stop Interrupt Enable bit position. */ - -#define TWI_SLAVE_PMEN_bm 0x02 /* Promiscuous Mode Enable bit mask. */ -#define TWI_SLAVE_PMEN_bp 1 /* Promiscuous Mode Enable bit position. */ - -#define TWI_SLAVE_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ -#define TWI_SLAVE_SMEN_bp 0 /* Smart Mode Enable bit position. */ - -/* TWI_SLAVE.CTRLB bit masks and bit positions */ -#define TWI_SLAVE_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ -#define TWI_SLAVE_ACKACT_bp 2 /* Acknowledge Action bit position. */ - -#define TWI_SLAVE_CMD_gm 0x03 /* Command group mask. */ -#define TWI_SLAVE_CMD_gp 0 /* Command group position. */ -#define TWI_SLAVE_CMD0_bm (1<<0) /* Command bit 0 mask. */ -#define TWI_SLAVE_CMD0_bp 0 /* Command bit 0 position. */ -#define TWI_SLAVE_CMD1_bm (1<<1) /* Command bit 1 mask. */ -#define TWI_SLAVE_CMD1_bp 1 /* Command bit 1 position. */ - -/* TWI_SLAVE.STATUS bit masks and bit positions */ -#define TWI_SLAVE_DIF_bm 0x80 /* Data Interrupt Flag bit mask. */ -#define TWI_SLAVE_DIF_bp 7 /* Data Interrupt Flag bit position. */ - -#define TWI_SLAVE_APIF_bm 0x40 /* Address/Stop Interrupt Flag bit mask. */ -#define TWI_SLAVE_APIF_bp 6 /* Address/Stop Interrupt Flag bit position. */ - -#define TWI_SLAVE_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ -#define TWI_SLAVE_CLKHOLD_bp 5 /* Clock Hold bit position. */ - -#define TWI_SLAVE_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ -#define TWI_SLAVE_RXACK_bp 4 /* Received Acknowledge bit position. */ - -#define TWI_SLAVE_COLL_bm 0x08 /* Collision bit mask. */ -#define TWI_SLAVE_COLL_bp 3 /* Collision bit position. */ - -#define TWI_SLAVE_BUSERR_bm 0x04 /* Bus Error bit mask. */ -#define TWI_SLAVE_BUSERR_bp 2 /* Bus Error bit position. */ - -#define TWI_SLAVE_DIR_bm 0x02 /* Read/Write Direction bit mask. */ -#define TWI_SLAVE_DIR_bp 1 /* Read/Write Direction bit position. */ - -#define TWI_SLAVE_AP_bm 0x01 /* Slave Address or Stop bit mask. */ -#define TWI_SLAVE_AP_bp 0 /* Slave Address or Stop bit position. */ - -/* TWI_SLAVE.ADDRMASK bit masks and bit positions */ -#define TWI_SLAVE_ADDRMASK_gm 0xFE /* Address Mask group mask. */ -#define TWI_SLAVE_ADDRMASK_gp 1 /* Address Mask group position. */ -#define TWI_SLAVE_ADDRMASK0_bm (1<<1) /* Address Mask bit 0 mask. */ -#define TWI_SLAVE_ADDRMASK0_bp 1 /* Address Mask bit 0 position. */ -#define TWI_SLAVE_ADDRMASK1_bm (1<<2) /* Address Mask bit 1 mask. */ -#define TWI_SLAVE_ADDRMASK1_bp 2 /* Address Mask bit 1 position. */ -#define TWI_SLAVE_ADDRMASK2_bm (1<<3) /* Address Mask bit 2 mask. */ -#define TWI_SLAVE_ADDRMASK2_bp 3 /* Address Mask bit 2 position. */ -#define TWI_SLAVE_ADDRMASK3_bm (1<<4) /* Address Mask bit 3 mask. */ -#define TWI_SLAVE_ADDRMASK3_bp 4 /* Address Mask bit 3 position. */ -#define TWI_SLAVE_ADDRMASK4_bm (1<<5) /* Address Mask bit 4 mask. */ -#define TWI_SLAVE_ADDRMASK4_bp 5 /* Address Mask bit 4 position. */ -#define TWI_SLAVE_ADDRMASK5_bm (1<<6) /* Address Mask bit 5 mask. */ -#define TWI_SLAVE_ADDRMASK5_bp 6 /* Address Mask bit 5 position. */ -#define TWI_SLAVE_ADDRMASK6_bm (1<<7) /* Address Mask bit 6 mask. */ -#define TWI_SLAVE_ADDRMASK6_bp 7 /* Address Mask bit 6 position. */ - -#define TWI_SLAVE_ADDREN_bm 0x01 /* Address Enable bit mask. */ -#define TWI_SLAVE_ADDREN_bp 0 /* Address Enable bit position. */ - -/* TWI.CTRL bit masks and bit positions */ -#define TWI_SDAHOLD_gm 0x06 /* SDA Hold Time Enable group mask. */ -#define TWI_SDAHOLD_gp 1 /* SDA Hold Time Enable group position. */ -#define TWI_SDAHOLD0_bm (1<<1) /* SDA Hold Time Enable bit 0 mask. */ -#define TWI_SDAHOLD0_bp 1 /* SDA Hold Time Enable bit 0 position. */ -#define TWI_SDAHOLD1_bm (1<<2) /* SDA Hold Time Enable bit 1 mask. */ -#define TWI_SDAHOLD1_bp 2 /* SDA Hold Time Enable bit 1 position. */ - -#define TWI_EDIEN_bm 0x01 /* External Driver Interface Enable bit mask. */ -#define TWI_EDIEN_bp 0 /* External Driver Interface Enable bit position. */ - -/* USB - USB */ -/* USB_EP.STATUS bit masks and bit positions */ -#define USB_EP_STALLF_bm 0x80 /* Endpoint Stall Flag bit mask. */ -#define USB_EP_STALLF_bp 7 /* Endpoint Stall Flag bit position. */ - -#define USB_EP_CRC_bm 0x80 /* CRC Error Flag bit mask. */ -#define USB_EP_CRC_bp 7 /* CRC Error Flag bit position. */ - -#define USB_EP_UNF_bm 0x40 /* Underflow Enpoint FLag bit mask. */ -#define USB_EP_UNF_bp 6 /* Underflow Enpoint FLag bit position. */ - -#define USB_EP_OVF_bm 0x40 /* Overflow Enpoint Flag for Output Endpoints bit mask. */ -#define USB_EP_OVF_bp 6 /* Overflow Enpoint Flag for Output Endpoints bit position. */ - -#define USB_EP_TRNCOMPL0_bm 0x20 /* Transaction Complete 0 Flag bit mask. */ -#define USB_EP_TRNCOMPL0_bp 5 /* Transaction Complete 0 Flag bit position. */ - -#define USB_EP_TRNCOMPL1_bm 0x10 /* Transaction Complete 1 Flag bit mask. */ -#define USB_EP_TRNCOMPL1_bp 4 /* Transaction Complete 1 Flag bit position. */ - -#define USB_EP_SETUP_bm 0x10 /* SETUP Transaction Complete Flag bit mask. */ -#define USB_EP_SETUP_bp 4 /* SETUP Transaction Complete Flag bit position. */ - -#define USB_EP_BANK_bm 0x08 /* Bank Select bit mask. */ -#define USB_EP_BANK_bp 3 /* Bank Select bit position. */ - -#define USB_EP_BUSNACK1_bm 0x04 /* Data Buffer 1 Not Acknowledge bit mask. */ -#define USB_EP_BUSNACK1_bp 2 /* Data Buffer 1 Not Acknowledge bit position. */ - -#define USB_EP_BUSNACK0_bm 0x02 /* Data Buffer 0 Not Acknowledge bit mask. */ -#define USB_EP_BUSNACK0_bp 1 /* Data Buffer 0 Not Acknowledge bit position. */ - -#define USB_EP_TOGGLE_bm 0x01 /* Data Toggle bit mask. */ -#define USB_EP_TOGGLE_bp 0 /* Data Toggle bit position. */ - -/* USB_EP.CTRL bit masks and bit positions */ -#define USB_EP_TYPE_gm 0xC0 /* Endpoint Type group mask. */ -#define USB_EP_TYPE_gp 6 /* Endpoint Type group position. */ -#define USB_EP_TYPE0_bm (1<<6) /* Endpoint Type bit 0 mask. */ -#define USB_EP_TYPE0_bp 6 /* Endpoint Type bit 0 position. */ -#define USB_EP_TYPE1_bm (1<<7) /* Endpoint Type bit 1 mask. */ -#define USB_EP_TYPE1_bp 7 /* Endpoint Type bit 1 position. */ - -#define USB_EP_MULTIPKT_bm 0x20 /* Multi Packet Transfer Enable bit mask. */ -#define USB_EP_MULTIPKT_bp 5 /* Multi Packet Transfer Enable bit position. */ - -#define USB_EP_PINGPONG_bm 0x10 /* Ping-Pong Enable bit mask. */ -#define USB_EP_PINGPONG_bp 4 /* Ping-Pong Enable bit position. */ - -#define USB_EP_INTDSBL_bm 0x08 /* Interrupt Disable bit mask. */ -#define USB_EP_INTDSBL_bp 3 /* Interrupt Disable bit position. */ - -#define USB_EP_STALL_bm 0x04 /* Data Stall bit mask. */ -#define USB_EP_STALL_bp 2 /* Data Stall bit position. */ - -#define USB_EP_BUFSIZE_gm 0x07 /* Data Buffer Size group mask. */ -#define USB_EP_BUFSIZE_gp 0 /* Data Buffer Size group position. */ -#define USB_EP_BUFSIZE0_bm (1<<0) /* Data Buffer Size bit 0 mask. */ -#define USB_EP_BUFSIZE0_bp 0 /* Data Buffer Size bit 0 position. */ -#define USB_EP_BUFSIZE1_bm (1<<1) /* Data Buffer Size bit 1 mask. */ -#define USB_EP_BUFSIZE1_bp 1 /* Data Buffer Size bit 1 position. */ -#define USB_EP_BUFSIZE2_bm (1<<2) /* Data Buffer Size bit 2 mask. */ -#define USB_EP_BUFSIZE2_bp 2 /* Data Buffer Size bit 2 position. */ - -/* USB_EP.CNT bit masks and bit positions */ -#define USB_EP_ZLP_bm 0x8000 /* Zero Length Packet bit mask. */ -#define USB_EP_ZLP_bp 15 /* Zero Length Packet bit position. */ - -/* USB.CTRLA bit masks and bit positions */ -#define USB_ENABLE_bm 0x80 /* USB Enable bit mask. */ -#define USB_ENABLE_bp 7 /* USB Enable bit position. */ - -#define USB_SPEED_bm 0x40 /* Speed Select bit mask. */ -#define USB_SPEED_bp 6 /* Speed Select bit position. */ - -#define USB_FIFOEN_bm 0x20 /* USB FIFO Enable bit mask. */ -#define USB_FIFOEN_bp 5 /* USB FIFO Enable bit position. */ - -#define USB_STFRNUM_bm 0x10 /* Store Frame Number Enable bit mask. */ -#define USB_STFRNUM_bp 4 /* Store Frame Number Enable bit position. */ - -#define USB_MAXEP_gm 0x0F /* Maximum Endpoint Addresses group mask. */ -#define USB_MAXEP_gp 0 /* Maximum Endpoint Addresses group position. */ -#define USB_MAXEP0_bm (1<<0) /* Maximum Endpoint Addresses bit 0 mask. */ -#define USB_MAXEP0_bp 0 /* Maximum Endpoint Addresses bit 0 position. */ -#define USB_MAXEP1_bm (1<<1) /* Maximum Endpoint Addresses bit 1 mask. */ -#define USB_MAXEP1_bp 1 /* Maximum Endpoint Addresses bit 1 position. */ -#define USB_MAXEP2_bm (1<<2) /* Maximum Endpoint Addresses bit 2 mask. */ -#define USB_MAXEP2_bp 2 /* Maximum Endpoint Addresses bit 2 position. */ -#define USB_MAXEP3_bm (1<<3) /* Maximum Endpoint Addresses bit 3 mask. */ -#define USB_MAXEP3_bp 3 /* Maximum Endpoint Addresses bit 3 position. */ - -/* USB.CTRLB bit masks and bit positions */ -#define USB_PULLRST_bm 0x10 /* Pull during Reset bit mask. */ -#define USB_PULLRST_bp 4 /* Pull during Reset bit position. */ - -#define USB_RWAKEUP_bm 0x04 /* Remote Wake-up bit mask. */ -#define USB_RWAKEUP_bp 2 /* Remote Wake-up bit position. */ - -#define USB_GNACK_bm 0x02 /* Global NACK bit mask. */ -#define USB_GNACK_bp 1 /* Global NACK bit position. */ - -#define USB_ATTACH_bm 0x01 /* Attach bit mask. */ -#define USB_ATTACH_bp 0 /* Attach bit position. */ - -/* USB.STATUS bit masks and bit positions */ -#define USB_URESUME_bm 0x08 /* Upstream Resume bit mask. */ -#define USB_URESUME_bp 3 /* Upstream Resume bit position. */ - -#define USB_RESUME_bm 0x04 /* Resume bit mask. */ -#define USB_RESUME_bp 2 /* Resume bit position. */ - -#define USB_SUSPEND_bm 0x02 /* Bus Suspended bit mask. */ -#define USB_SUSPEND_bp 1 /* Bus Suspended bit position. */ - -#define USB_BUSRST_bm 0x01 /* Bus Reset bit mask. */ -#define USB_BUSRST_bp 0 /* Bus Reset bit position. */ - -/* USB.ADDR bit masks and bit positions */ -#define USB_ADDR_gm 0x7F /* Device Address group mask. */ -#define USB_ADDR_gp 0 /* Device Address group position. */ -#define USB_ADDR0_bm (1<<0) /* Device Address bit 0 mask. */ -#define USB_ADDR0_bp 0 /* Device Address bit 0 position. */ -#define USB_ADDR1_bm (1<<1) /* Device Address bit 1 mask. */ -#define USB_ADDR1_bp 1 /* Device Address bit 1 position. */ -#define USB_ADDR2_bm (1<<2) /* Device Address bit 2 mask. */ -#define USB_ADDR2_bp 2 /* Device Address bit 2 position. */ -#define USB_ADDR3_bm (1<<3) /* Device Address bit 3 mask. */ -#define USB_ADDR3_bp 3 /* Device Address bit 3 position. */ -#define USB_ADDR4_bm (1<<4) /* Device Address bit 4 mask. */ -#define USB_ADDR4_bp 4 /* Device Address bit 4 position. */ -#define USB_ADDR5_bm (1<<5) /* Device Address bit 5 mask. */ -#define USB_ADDR5_bp 5 /* Device Address bit 5 position. */ -#define USB_ADDR6_bm (1<<6) /* Device Address bit 6 mask. */ -#define USB_ADDR6_bp 6 /* Device Address bit 6 position. */ - -/* USB.FIFOWP bit masks and bit positions */ -#define USB_FIFOWP_gm 0x1F /* FIFO Write Pointer group mask. */ -#define USB_FIFOWP_gp 0 /* FIFO Write Pointer group position. */ -#define USB_FIFOWP0_bm (1<<0) /* FIFO Write Pointer bit 0 mask. */ -#define USB_FIFOWP0_bp 0 /* FIFO Write Pointer bit 0 position. */ -#define USB_FIFOWP1_bm (1<<1) /* FIFO Write Pointer bit 1 mask. */ -#define USB_FIFOWP1_bp 1 /* FIFO Write Pointer bit 1 position. */ -#define USB_FIFOWP2_bm (1<<2) /* FIFO Write Pointer bit 2 mask. */ -#define USB_FIFOWP2_bp 2 /* FIFO Write Pointer bit 2 position. */ -#define USB_FIFOWP3_bm (1<<3) /* FIFO Write Pointer bit 3 mask. */ -#define USB_FIFOWP3_bp 3 /* FIFO Write Pointer bit 3 position. */ -#define USB_FIFOWP4_bm (1<<4) /* FIFO Write Pointer bit 4 mask. */ -#define USB_FIFOWP4_bp 4 /* FIFO Write Pointer bit 4 position. */ - -/* USB.FIFORP bit masks and bit positions */ -#define USB_FIFORP_gm 0x1F /* FIFO Read Pointer group mask. */ -#define USB_FIFORP_gp 0 /* FIFO Read Pointer group position. */ -#define USB_FIFORP0_bm (1<<0) /* FIFO Read Pointer bit 0 mask. */ -#define USB_FIFORP0_bp 0 /* FIFO Read Pointer bit 0 position. */ -#define USB_FIFORP1_bm (1<<1) /* FIFO Read Pointer bit 1 mask. */ -#define USB_FIFORP1_bp 1 /* FIFO Read Pointer bit 1 position. */ -#define USB_FIFORP2_bm (1<<2) /* FIFO Read Pointer bit 2 mask. */ -#define USB_FIFORP2_bp 2 /* FIFO Read Pointer bit 2 position. */ -#define USB_FIFORP3_bm (1<<3) /* FIFO Read Pointer bit 3 mask. */ -#define USB_FIFORP3_bp 3 /* FIFO Read Pointer bit 3 position. */ -#define USB_FIFORP4_bm (1<<4) /* FIFO Read Pointer bit 4 mask. */ -#define USB_FIFORP4_bp 4 /* FIFO Read Pointer bit 4 position. */ - -/* USB.INTCTRLA bit masks and bit positions */ -#define USB_SOFIE_bm 0x80 /* Start Of Frame Interrupt Enable bit mask. */ -#define USB_SOFIE_bp 7 /* Start Of Frame Interrupt Enable bit position. */ - -#define USB_BUSEVIE_bm 0x40 /* Bus Event Interrupt Enable bit mask. */ -#define USB_BUSEVIE_bp 6 /* Bus Event Interrupt Enable bit position. */ - -#define USB_BUSERRIE_bm 0x20 /* Bus Error Interrupt Enable bit mask. */ -#define USB_BUSERRIE_bp 5 /* Bus Error Interrupt Enable bit position. */ - -#define USB_STALLIE_bm 0x10 /* STALL Interrupt Enable bit mask. */ -#define USB_STALLIE_bp 4 /* STALL Interrupt Enable bit position. */ - -#define USB_INTLVL_gm 0x03 /* Interrupt Level group mask. */ -#define USB_INTLVL_gp 0 /* Interrupt Level group position. */ -#define USB_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */ -#define USB_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */ -#define USB_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ -#define USB_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */ - -/* USB.INTCTRLB bit masks and bit positions */ -#define USB_TRNIE_bm 0x02 /* Transaction Complete Interrupt Enable bit mask. */ -#define USB_TRNIE_bp 1 /* Transaction Complete Interrupt Enable bit position. */ - -#define USB_SETUPIE_bm 0x01 /* SETUP Transaction Complete Interrupt Enable bit mask. */ -#define USB_SETUPIE_bp 0 /* SETUP Transaction Complete Interrupt Enable bit position. */ - -/* USB.INTFLAGSACLR bit masks and bit positions */ -#define USB_SOFIF_bm 0x80 /* Start Of Frame Interrupt Flag bit mask. */ -#define USB_SOFIF_bp 7 /* Start Of Frame Interrupt Flag bit position. */ - -#define USB_SUSPENDIF_bm 0x40 /* Suspend Interrupt Flag bit mask. */ -#define USB_SUSPENDIF_bp 6 /* Suspend Interrupt Flag bit position. */ - -#define USB_RESUMEIF_bm 0x20 /* Resume Interrupt Flag bit mask. */ -#define USB_RESUMEIF_bp 5 /* Resume Interrupt Flag bit position. */ - -#define USB_RSTIF_bm 0x10 /* Reset Interrupt Flag bit mask. */ -#define USB_RSTIF_bp 4 /* Reset Interrupt Flag bit position. */ - -#define USB_CRCIF_bm 0x08 /* Isochronous CRC Error Interrupt Flag bit mask. */ -#define USB_CRCIF_bp 3 /* Isochronous CRC Error Interrupt Flag bit position. */ - -#define USB_UNFIF_bm 0x04 /* Underflow Interrupt Flag bit mask. */ -#define USB_UNFIF_bp 2 /* Underflow Interrupt Flag bit position. */ - -#define USB_OVFIF_bm 0x02 /* Overflow Interrupt Flag bit mask. */ -#define USB_OVFIF_bp 1 /* Overflow Interrupt Flag bit position. */ - -#define USB_STALLIF_bm 0x01 /* STALL Interrupt Flag bit mask. */ -#define USB_STALLIF_bp 0 /* STALL Interrupt Flag bit position. */ - -/* USB.INTFLAGSASET bit masks and bit positions */ -/* USB_SOFIF Predefined. */ -/* USB_SOFIF Predefined. */ - -/* USB_SUSPENDIF Predefined. */ -/* USB_SUSPENDIF Predefined. */ - -/* USB_RESUMEIF Predefined. */ -/* USB_RESUMEIF Predefined. */ - -/* USB_RSTIF Predefined. */ -/* USB_RSTIF Predefined. */ - -/* USB_CRCIF Predefined. */ -/* USB_CRCIF Predefined. */ - -/* USB_UNFIF Predefined. */ -/* USB_UNFIF Predefined. */ - -/* USB_OVFIF Predefined. */ -/* USB_OVFIF Predefined. */ - -/* USB_STALLIF Predefined. */ -/* USB_STALLIF Predefined. */ - -/* USB.INTFLAGSBCLR bit masks and bit positions */ -#define USB_TRNIF_bm 0x02 /* Transaction Complete Interrupt Flag bit mask. */ -#define USB_TRNIF_bp 1 /* Transaction Complete Interrupt Flag bit position. */ - -#define USB_SETUPIF_bm 0x01 /* SETUP Transaction Complete Interrupt Flag bit mask. */ -#define USB_SETUPIF_bp 0 /* SETUP Transaction Complete Interrupt Flag bit position. */ - -/* USB.INTFLAGSBSET bit masks and bit positions */ -/* USB_TRNIF Predefined. */ -/* USB_TRNIF Predefined. */ - -/* USB_SETUPIF Predefined. */ -/* USB_SETUPIF Predefined. */ - -/* PORT - I/O Port Configuration */ -/* PORT.INTCTRL bit masks and bit positions */ -#define PORT_INT1LVL_gm 0x0C /* Port Interrupt 1 Level group mask. */ -#define PORT_INT1LVL_gp 2 /* Port Interrupt 1 Level group position. */ -#define PORT_INT1LVL0_bm (1<<2) /* Port Interrupt 1 Level bit 0 mask. */ -#define PORT_INT1LVL0_bp 2 /* Port Interrupt 1 Level bit 0 position. */ -#define PORT_INT1LVL1_bm (1<<3) /* Port Interrupt 1 Level bit 1 mask. */ -#define PORT_INT1LVL1_bp 3 /* Port Interrupt 1 Level bit 1 position. */ - -#define PORT_INT0LVL_gm 0x03 /* Port Interrupt 0 Level group mask. */ -#define PORT_INT0LVL_gp 0 /* Port Interrupt 0 Level group position. */ -#define PORT_INT0LVL0_bm (1<<0) /* Port Interrupt 0 Level bit 0 mask. */ -#define PORT_INT0LVL0_bp 0 /* Port Interrupt 0 Level bit 0 position. */ -#define PORT_INT0LVL1_bm (1<<1) /* Port Interrupt 0 Level bit 1 mask. */ -#define PORT_INT0LVL1_bp 1 /* Port Interrupt 0 Level bit 1 position. */ - -/* PORT.INTFLAGS bit masks and bit positions */ -#define PORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ -#define PORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ - -#define PORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ -#define PORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ - -/* PORT.REMAP bit masks and bit positions */ -#define PORT_SPI_bm 0x20 /* SPI bit mask. */ -#define PORT_SPI_bp 5 /* SPI bit position. */ - -#define PORT_USART0_bm 0x10 /* USART0 bit mask. */ -#define PORT_USART0_bp 4 /* USART0 bit position. */ - -#define PORT_TC0D_bm 0x08 /* Timer/Counter 0 Output Compare D bit mask. */ -#define PORT_TC0D_bp 3 /* Timer/Counter 0 Output Compare D bit position. */ - -#define PORT_TC0C_bm 0x04 /* Timer/Counter 0 Output Compare C bit mask. */ -#define PORT_TC0C_bp 2 /* Timer/Counter 0 Output Compare C bit position. */ - -#define PORT_TC0B_bm 0x02 /* Timer/Counter 0 Output Compare B bit mask. */ -#define PORT_TC0B_bp 1 /* Timer/Counter 0 Output Compare B bit position. */ - -#define PORT_TC0A_bm 0x01 /* Timer/Counter 0 Output Compare A bit mask. */ -#define PORT_TC0A_bp 0 /* Timer/Counter 0 Output Compare A bit position. */ - -/* PORT.PIN0CTRL bit masks and bit positions */ -#define PORT_SRLEN_bm 0x80 /* Slew Rate Enable bit mask. */ -#define PORT_SRLEN_bp 7 /* Slew Rate Enable bit position. */ - -#define PORT_INVEN_bm 0x40 /* Inverted I/O Enable bit mask. */ -#define PORT_INVEN_bp 6 /* Inverted I/O Enable bit position. */ - -#define PORT_OPC_gm 0x38 /* Output/Pull Configuration group mask. */ -#define PORT_OPC_gp 3 /* Output/Pull Configuration group position. */ -#define PORT_OPC0_bm (1<<3) /* Output/Pull Configuration bit 0 mask. */ -#define PORT_OPC0_bp 3 /* Output/Pull Configuration bit 0 position. */ -#define PORT_OPC1_bm (1<<4) /* Output/Pull Configuration bit 1 mask. */ -#define PORT_OPC1_bp 4 /* Output/Pull Configuration bit 1 position. */ -#define PORT_OPC2_bm (1<<5) /* Output/Pull Configuration bit 2 mask. */ -#define PORT_OPC2_bp 5 /* Output/Pull Configuration bit 2 position. */ - -#define PORT_ISC_gm 0x07 /* Input/Sense Configuration group mask. */ -#define PORT_ISC_gp 0 /* Input/Sense Configuration group position. */ -#define PORT_ISC0_bm (1<<0) /* Input/Sense Configuration bit 0 mask. */ -#define PORT_ISC0_bp 0 /* Input/Sense Configuration bit 0 position. */ -#define PORT_ISC1_bm (1<<1) /* Input/Sense Configuration bit 1 mask. */ -#define PORT_ISC1_bp 1 /* Input/Sense Configuration bit 1 position. */ -#define PORT_ISC2_bm (1<<2) /* Input/Sense Configuration bit 2 mask. */ -#define PORT_ISC2_bp 2 /* Input/Sense Configuration bit 2 position. */ - -/* PORT.PIN1CTRL bit masks and bit positions */ -/* PORT_SRLEN Predefined. */ -/* PORT_SRLEN Predefined. */ - -/* PORT_INVEN Predefined. */ -/* PORT_INVEN Predefined. */ - -/* PORT_OPC Predefined. */ -/* PORT_OPC Predefined. */ - -/* PORT_ISC Predefined. */ -/* PORT_ISC Predefined. */ - -/* PORT.PIN2CTRL bit masks and bit positions */ -/* PORT_SRLEN Predefined. */ -/* PORT_SRLEN Predefined. */ - -/* PORT_INVEN Predefined. */ -/* PORT_INVEN Predefined. */ - -/* PORT_OPC Predefined. */ -/* PORT_OPC Predefined. */ - -/* PORT_ISC Predefined. */ -/* PORT_ISC Predefined. */ - -/* PORT.PIN3CTRL bit masks and bit positions */ -/* PORT_SRLEN Predefined. */ -/* PORT_SRLEN Predefined. */ - -/* PORT_INVEN Predefined. */ -/* PORT_INVEN Predefined. */ - -/* PORT_OPC Predefined. */ -/* PORT_OPC Predefined. */ - -/* PORT_ISC Predefined. */ -/* PORT_ISC Predefined. */ - -/* PORT.PIN4CTRL bit masks and bit positions */ -/* PORT_SRLEN Predefined. */ -/* PORT_SRLEN Predefined. */ - -/* PORT_INVEN Predefined. */ -/* PORT_INVEN Predefined. */ - -/* PORT_OPC Predefined. */ -/* PORT_OPC Predefined. */ - -/* PORT_ISC Predefined. */ -/* PORT_ISC Predefined. */ - -/* PORT.PIN5CTRL bit masks and bit positions */ -/* PORT_SRLEN Predefined. */ -/* PORT_SRLEN Predefined. */ - -/* PORT_INVEN Predefined. */ -/* PORT_INVEN Predefined. */ - -/* PORT_OPC Predefined. */ -/* PORT_OPC Predefined. */ - -/* PORT_ISC Predefined. */ -/* PORT_ISC Predefined. */ - -/* PORT.PIN6CTRL bit masks and bit positions */ -/* PORT_SRLEN Predefined. */ -/* PORT_SRLEN Predefined. */ - -/* PORT_INVEN Predefined. */ -/* PORT_INVEN Predefined. */ - -/* PORT_OPC Predefined. */ -/* PORT_OPC Predefined. */ - -/* PORT_ISC Predefined. */ -/* PORT_ISC Predefined. */ - -/* PORT.PIN7CTRL bit masks and bit positions */ -/* PORT_SRLEN Predefined. */ -/* PORT_SRLEN Predefined. */ - -/* PORT_INVEN Predefined. */ -/* PORT_INVEN Predefined. */ - -/* PORT_OPC Predefined. */ -/* PORT_OPC Predefined. */ - -/* PORT_ISC Predefined. */ -/* PORT_ISC Predefined. */ - -/* TC - 16-bit Timer/Counter With PWM */ -/* TC0.CTRLA bit masks and bit positions */ -#define TC0_CLKSEL_gm 0x0F /* Clock Selection group mask. */ -#define TC0_CLKSEL_gp 0 /* Clock Selection group position. */ -#define TC0_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ -#define TC0_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ -#define TC0_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ -#define TC0_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ -#define TC0_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ -#define TC0_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ -#define TC0_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ -#define TC0_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ - -/* TC0.CTRLB bit masks and bit positions */ -#define TC0_CCDEN_bm 0x80 /* Compare or Capture D Enable bit mask. */ -#define TC0_CCDEN_bp 7 /* Compare or Capture D Enable bit position. */ - -#define TC0_CCCEN_bm 0x40 /* Compare or Capture C Enable bit mask. */ -#define TC0_CCCEN_bp 6 /* Compare or Capture C Enable bit position. */ - -#define TC0_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ -#define TC0_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ - -#define TC0_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ -#define TC0_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ - -#define TC0_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ -#define TC0_WGMODE_gp 0 /* Waveform generation mode group position. */ -#define TC0_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ -#define TC0_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ -#define TC0_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ -#define TC0_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ -#define TC0_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ -#define TC0_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ - -/* TC0.CTRLC bit masks and bit positions */ -#define TC0_CMPD_bm 0x08 /* Compare D Output Value bit mask. */ -#define TC0_CMPD_bp 3 /* Compare D Output Value bit position. */ - -#define TC0_CMPC_bm 0x04 /* Compare C Output Value bit mask. */ -#define TC0_CMPC_bp 2 /* Compare C Output Value bit position. */ - -#define TC0_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ -#define TC0_CMPB_bp 1 /* Compare B Output Value bit position. */ - -#define TC0_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ -#define TC0_CMPA_bp 0 /* Compare A Output Value bit position. */ - -/* TC0.CTRLD bit masks and bit positions */ -#define TC0_EVACT_gm 0xE0 /* Event Action group mask. */ -#define TC0_EVACT_gp 5 /* Event Action group position. */ -#define TC0_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ -#define TC0_EVACT0_bp 5 /* Event Action bit 0 position. */ -#define TC0_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ -#define TC0_EVACT1_bp 6 /* Event Action bit 1 position. */ -#define TC0_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ -#define TC0_EVACT2_bp 7 /* Event Action bit 2 position. */ - -#define TC0_EVDLY_bm 0x10 /* Event Delay bit mask. */ -#define TC0_EVDLY_bp 4 /* Event Delay bit position. */ - -#define TC0_EVSEL_gm 0x0F /* Event Source Select group mask. */ -#define TC0_EVSEL_gp 0 /* Event Source Select group position. */ -#define TC0_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ -#define TC0_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ -#define TC0_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ -#define TC0_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ -#define TC0_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ -#define TC0_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ -#define TC0_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ -#define TC0_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ - -/* TC0.CTRLE bit masks and bit positions */ -#define TC0_BYTEM_gm 0x03 /* Byte Mode group mask. */ -#define TC0_BYTEM_gp 0 /* Byte Mode group position. */ -#define TC0_BYTEM0_bm (1<<0) /* Byte Mode bit 0 mask. */ -#define TC0_BYTEM0_bp 0 /* Byte Mode bit 0 position. */ -#define TC0_BYTEM1_bm (1<<1) /* Byte Mode bit 1 mask. */ -#define TC0_BYTEM1_bp 1 /* Byte Mode bit 1 position. */ - -/* TC0.INTCTRLA bit masks and bit positions */ -#define TC0_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ -#define TC0_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ -#define TC0_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ -#define TC0_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ -#define TC0_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ -#define TC0_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ - -#define TC0_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ -#define TC0_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ -#define TC0_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ -#define TC0_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ -#define TC0_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ -#define TC0_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ - -/* TC0.INTCTRLB bit masks and bit positions */ -#define TC0_CCDINTLVL_gm 0xC0 /* Compare or Capture D Interrupt Level group mask. */ -#define TC0_CCDINTLVL_gp 6 /* Compare or Capture D Interrupt Level group position. */ -#define TC0_CCDINTLVL0_bm (1<<6) /* Compare or Capture D Interrupt Level bit 0 mask. */ -#define TC0_CCDINTLVL0_bp 6 /* Compare or Capture D Interrupt Level bit 0 position. */ -#define TC0_CCDINTLVL1_bm (1<<7) /* Compare or Capture D Interrupt Level bit 1 mask. */ -#define TC0_CCDINTLVL1_bp 7 /* Compare or Capture D Interrupt Level bit 1 position. */ - -#define TC0_CCCINTLVL_gm 0x30 /* Compare or Capture C Interrupt Level group mask. */ -#define TC0_CCCINTLVL_gp 4 /* Compare or Capture C Interrupt Level group position. */ -#define TC0_CCCINTLVL0_bm (1<<4) /* Compare or Capture C Interrupt Level bit 0 mask. */ -#define TC0_CCCINTLVL0_bp 4 /* Compare or Capture C Interrupt Level bit 0 position. */ -#define TC0_CCCINTLVL1_bm (1<<5) /* Compare or Capture C Interrupt Level bit 1 mask. */ -#define TC0_CCCINTLVL1_bp 5 /* Compare or Capture C Interrupt Level bit 1 position. */ - -#define TC0_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ -#define TC0_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ -#define TC0_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ -#define TC0_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ -#define TC0_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ -#define TC0_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ - -#define TC0_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ -#define TC0_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ -#define TC0_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ -#define TC0_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ -#define TC0_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ -#define TC0_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ - -/* TC0.CTRLFCLR bit masks and bit positions */ -#define TC0_CMD_gm 0x0C /* Command group mask. */ -#define TC0_CMD_gp 2 /* Command group position. */ -#define TC0_CMD0_bm (1<<2) /* Command bit 0 mask. */ -#define TC0_CMD0_bp 2 /* Command bit 0 position. */ -#define TC0_CMD1_bm (1<<3) /* Command bit 1 mask. */ -#define TC0_CMD1_bp 3 /* Command bit 1 position. */ - -#define TC0_LUPD_bm 0x02 /* Lock Update bit mask. */ -#define TC0_LUPD_bp 1 /* Lock Update bit position. */ - -#define TC0_DIR_bm 0x01 /* Direction bit mask. */ -#define TC0_DIR_bp 0 /* Direction bit position. */ - -/* TC0.CTRLFSET bit masks and bit positions */ -/* TC0_CMD Predefined. */ -/* TC0_CMD Predefined. */ - -/* TC0_LUPD Predefined. */ -/* TC0_LUPD Predefined. */ - -/* TC0_DIR Predefined. */ -/* TC0_DIR Predefined. */ - -/* TC0.CTRLGCLR bit masks and bit positions */ -#define TC0_CCDBV_bm 0x10 /* Compare or Capture D Buffer Valid bit mask. */ -#define TC0_CCDBV_bp 4 /* Compare or Capture D Buffer Valid bit position. */ - -#define TC0_CCCBV_bm 0x08 /* Compare or Capture C Buffer Valid bit mask. */ -#define TC0_CCCBV_bp 3 /* Compare or Capture C Buffer Valid bit position. */ - -#define TC0_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ -#define TC0_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ - -#define TC0_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ -#define TC0_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ - -#define TC0_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ -#define TC0_PERBV_bp 0 /* Period Buffer Valid bit position. */ - -/* TC0.CTRLGSET bit masks and bit positions */ -/* TC0_CCDBV Predefined. */ -/* TC0_CCDBV Predefined. */ - -/* TC0_CCCBV Predefined. */ -/* TC0_CCCBV Predefined. */ - -/* TC0_CCBBV Predefined. */ -/* TC0_CCBBV Predefined. */ - -/* TC0_CCABV Predefined. */ -/* TC0_CCABV Predefined. */ - -/* TC0_PERBV Predefined. */ -/* TC0_PERBV Predefined. */ - -/* TC0.INTFLAGS bit masks and bit positions */ -#define TC0_CCDIF_bm 0x80 /* Compare or Capture D Interrupt Flag bit mask. */ -#define TC0_CCDIF_bp 7 /* Compare or Capture D Interrupt Flag bit position. */ - -#define TC0_CCCIF_bm 0x40 /* Compare or Capture C Interrupt Flag bit mask. */ -#define TC0_CCCIF_bp 6 /* Compare or Capture C Interrupt Flag bit position. */ - -#define TC0_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ -#define TC0_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ - -#define TC0_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ -#define TC0_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ - -#define TC0_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ -#define TC0_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ - -#define TC0_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ -#define TC0_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ - -/* TC1.CTRLA bit masks and bit positions */ -#define TC1_CLKSEL_gm 0x0F /* Clock Selection group mask. */ -#define TC1_CLKSEL_gp 0 /* Clock Selection group position. */ -#define TC1_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ -#define TC1_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ -#define TC1_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ -#define TC1_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ -#define TC1_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ -#define TC1_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ -#define TC1_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ -#define TC1_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ - -/* TC1.CTRLB bit masks and bit positions */ -#define TC1_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ -#define TC1_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ - -#define TC1_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ -#define TC1_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ - -#define TC1_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ -#define TC1_WGMODE_gp 0 /* Waveform generation mode group position. */ -#define TC1_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ -#define TC1_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ -#define TC1_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ -#define TC1_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ -#define TC1_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ -#define TC1_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ - -/* TC1.CTRLC bit masks and bit positions */ -#define TC1_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ -#define TC1_CMPB_bp 1 /* Compare B Output Value bit position. */ - -#define TC1_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ -#define TC1_CMPA_bp 0 /* Compare A Output Value bit position. */ - -/* TC1.CTRLD bit masks and bit positions */ -#define TC1_EVACT_gm 0xE0 /* Event Action group mask. */ -#define TC1_EVACT_gp 5 /* Event Action group position. */ -#define TC1_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ -#define TC1_EVACT0_bp 5 /* Event Action bit 0 position. */ -#define TC1_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ -#define TC1_EVACT1_bp 6 /* Event Action bit 1 position. */ -#define TC1_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ -#define TC1_EVACT2_bp 7 /* Event Action bit 2 position. */ - -#define TC1_EVDLY_bm 0x10 /* Event Delay bit mask. */ -#define TC1_EVDLY_bp 4 /* Event Delay bit position. */ - -#define TC1_EVSEL_gm 0x0F /* Event Source Select group mask. */ -#define TC1_EVSEL_gp 0 /* Event Source Select group position. */ -#define TC1_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ -#define TC1_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ -#define TC1_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ -#define TC1_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ -#define TC1_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ -#define TC1_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ -#define TC1_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ -#define TC1_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ - -/* TC1.CTRLE bit masks and bit positions */ -#define TC1_BYTEM_bm 0x01 /* Byte Mode bit mask. */ -#define TC1_BYTEM_bp 0 /* Byte Mode bit position. */ - -/* TC1.INTCTRLA bit masks and bit positions */ -#define TC1_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ -#define TC1_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ -#define TC1_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ -#define TC1_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ -#define TC1_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ -#define TC1_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ - -#define TC1_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ -#define TC1_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ -#define TC1_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ -#define TC1_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ -#define TC1_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ -#define TC1_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ - -/* TC1.INTCTRLB bit masks and bit positions */ -#define TC1_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ -#define TC1_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ -#define TC1_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ -#define TC1_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ -#define TC1_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ -#define TC1_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ - -#define TC1_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ -#define TC1_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ -#define TC1_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ -#define TC1_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ -#define TC1_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ -#define TC1_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ - -/* TC1.CTRLFCLR bit masks and bit positions */ -#define TC1_CMD_gm 0x0C /* Command group mask. */ -#define TC1_CMD_gp 2 /* Command group position. */ -#define TC1_CMD0_bm (1<<2) /* Command bit 0 mask. */ -#define TC1_CMD0_bp 2 /* Command bit 0 position. */ -#define TC1_CMD1_bm (1<<3) /* Command bit 1 mask. */ -#define TC1_CMD1_bp 3 /* Command bit 1 position. */ - -#define TC1_LUPD_bm 0x02 /* Lock Update bit mask. */ -#define TC1_LUPD_bp 1 /* Lock Update bit position. */ - -#define TC1_DIR_bm 0x01 /* Direction bit mask. */ -#define TC1_DIR_bp 0 /* Direction bit position. */ - -/* TC1.CTRLFSET bit masks and bit positions */ -/* TC1_CMD Predefined. */ -/* TC1_CMD Predefined. */ - -/* TC1_LUPD Predefined. */ -/* TC1_LUPD Predefined. */ - -/* TC1_DIR Predefined. */ -/* TC1_DIR Predefined. */ - -/* TC1.CTRLGCLR bit masks and bit positions */ -#define TC1_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ -#define TC1_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ - -#define TC1_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ -#define TC1_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ - -#define TC1_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ -#define TC1_PERBV_bp 0 /* Period Buffer Valid bit position. */ - -/* TC1.CTRLGSET bit masks and bit positions */ -/* TC1_CCBBV Predefined. */ -/* TC1_CCBBV Predefined. */ - -/* TC1_CCABV Predefined. */ -/* TC1_CCABV Predefined. */ - -/* TC1_PERBV Predefined. */ -/* TC1_PERBV Predefined. */ - -/* TC1.INTFLAGS bit masks and bit positions */ -#define TC1_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ -#define TC1_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ - -#define TC1_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ -#define TC1_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ - -#define TC1_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ -#define TC1_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ - -#define TC1_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ -#define TC1_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ - -/* TC2 - 16-bit Timer/Counter type 2 */ -/* TC2.CTRLA bit masks and bit positions */ -#define TC2_CLKSEL_gm 0x0F /* Clock Selection group mask. */ -#define TC2_CLKSEL_gp 0 /* Clock Selection group position. */ -#define TC2_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ -#define TC2_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ -#define TC2_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ -#define TC2_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ -#define TC2_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ -#define TC2_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ -#define TC2_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ -#define TC2_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ - -/* TC2.CTRLB bit masks and bit positions */ -#define TC2_HCMPDEN_bm 0x80 /* High Byte Compare D Enable bit mask. */ -#define TC2_HCMPDEN_bp 7 /* High Byte Compare D Enable bit position. */ - -#define TC2_HCMPCEN_bm 0x40 /* High Byte Compare C Enable bit mask. */ -#define TC2_HCMPCEN_bp 6 /* High Byte Compare C Enable bit position. */ - -#define TC2_HCMPBEN_bm 0x20 /* High Byte Compare B Enable bit mask. */ -#define TC2_HCMPBEN_bp 5 /* High Byte Compare B Enable bit position. */ - -#define TC2_HCMPAEN_bm 0x10 /* High Byte Compare A Enable bit mask. */ -#define TC2_HCMPAEN_bp 4 /* High Byte Compare A Enable bit position. */ - -#define TC2_LCMPDEN_bm 0x08 /* Low Byte Compare D Enable bit mask. */ -#define TC2_LCMPDEN_bp 3 /* Low Byte Compare D Enable bit position. */ - -#define TC2_LCMPCEN_bm 0x04 /* Low Byte Compare C Enable bit mask. */ -#define TC2_LCMPCEN_bp 2 /* Low Byte Compare C Enable bit position. */ - -#define TC2_LCMPBEN_bm 0x02 /* Low Byte Compare B Enable bit mask. */ -#define TC2_LCMPBEN_bp 1 /* Low Byte Compare B Enable bit position. */ - -#define TC2_LCMPAEN_bm 0x01 /* Low Byte Compare A Enable bit mask. */ -#define TC2_LCMPAEN_bp 0 /* Low Byte Compare A Enable bit position. */ - -/* TC2.CTRLC bit masks and bit positions */ -#define TC2_HCMPD_bm 0x80 /* High Byte Compare D Output Value bit mask. */ -#define TC2_HCMPD_bp 7 /* High Byte Compare D Output Value bit position. */ - -#define TC2_HCMPC_bm 0x40 /* High Byte Compare C Output Value bit mask. */ -#define TC2_HCMPC_bp 6 /* High Byte Compare C Output Value bit position. */ - -#define TC2_HCMPB_bm 0x20 /* High Byte Compare B Output Value bit mask. */ -#define TC2_HCMPB_bp 5 /* High Byte Compare B Output Value bit position. */ - -#define TC2_HCMPA_bm 0x10 /* High Byte Compare A Output Value bit mask. */ -#define TC2_HCMPA_bp 4 /* High Byte Compare A Output Value bit position. */ - -#define TC2_LCMPD_bm 0x08 /* Low Byte Compare D Output Value bit mask. */ -#define TC2_LCMPD_bp 3 /* Low Byte Compare D Output Value bit position. */ - -#define TC2_LCMPC_bm 0x04 /* Low Byte Compare C Output Value bit mask. */ -#define TC2_LCMPC_bp 2 /* Low Byte Compare C Output Value bit position. */ - -#define TC2_LCMPB_bm 0x02 /* Low Byte Compare B Output Value bit mask. */ -#define TC2_LCMPB_bp 1 /* Low Byte Compare B Output Value bit position. */ - -#define TC2_LCMPA_bm 0x01 /* Low Byte Compare A Output Value bit mask. */ -#define TC2_LCMPA_bp 0 /* Low Byte Compare A Output Value bit position. */ - -/* TC2.CTRLE bit masks and bit positions */ -#define TC2_BYTEM_gm 0x03 /* Byte Mode group mask. */ -#define TC2_BYTEM_gp 0 /* Byte Mode group position. */ -#define TC2_BYTEM0_bm (1<<0) /* Byte Mode bit 0 mask. */ -#define TC2_BYTEM0_bp 0 /* Byte Mode bit 0 position. */ -#define TC2_BYTEM1_bm (1<<1) /* Byte Mode bit 1 mask. */ -#define TC2_BYTEM1_bp 1 /* Byte Mode bit 1 position. */ - -/* TC2.INTCTRLA bit masks and bit positions */ -#define TC2_HUNFINTLVL_gm 0x0C /* High Byte Underflow Interrupt Level group mask. */ -#define TC2_HUNFINTLVL_gp 2 /* High Byte Underflow Interrupt Level group position. */ -#define TC2_HUNFINTLVL0_bm (1<<2) /* High Byte Underflow Interrupt Level bit 0 mask. */ -#define TC2_HUNFINTLVL0_bp 2 /* High Byte Underflow Interrupt Level bit 0 position. */ -#define TC2_HUNFINTLVL1_bm (1<<3) /* High Byte Underflow Interrupt Level bit 1 mask. */ -#define TC2_HUNFINTLVL1_bp 3 /* High Byte Underflow Interrupt Level bit 1 position. */ - -#define TC2_LUNFINTLVL_gm 0x03 /* Low Byte Underflow interrupt level group mask. */ -#define TC2_LUNFINTLVL_gp 0 /* Low Byte Underflow interrupt level group position. */ -#define TC2_LUNFINTLVL0_bm (1<<0) /* Low Byte Underflow interrupt level bit 0 mask. */ -#define TC2_LUNFINTLVL0_bp 0 /* Low Byte Underflow interrupt level bit 0 position. */ -#define TC2_LUNFINTLVL1_bm (1<<1) /* Low Byte Underflow interrupt level bit 1 mask. */ -#define TC2_LUNFINTLVL1_bp 1 /* Low Byte Underflow interrupt level bit 1 position. */ - -/* TC2.INTCTRLB bit masks and bit positions */ -#define TC2_LCMPDINTLVL_gm 0xC0 /* Low Byte Compare D Interrupt Level group mask. */ -#define TC2_LCMPDINTLVL_gp 6 /* Low Byte Compare D Interrupt Level group position. */ -#define TC2_LCMPDINTLVL0_bm (1<<6) /* Low Byte Compare D Interrupt Level bit 0 mask. */ -#define TC2_LCMPDINTLVL0_bp 6 /* Low Byte Compare D Interrupt Level bit 0 position. */ -#define TC2_LCMPDINTLVL1_bm (1<<7) /* Low Byte Compare D Interrupt Level bit 1 mask. */ -#define TC2_LCMPDINTLVL1_bp 7 /* Low Byte Compare D Interrupt Level bit 1 position. */ - -#define TC2_LCMPCINTLVL_gm 0x30 /* Low Byte Compare C Interrupt Level group mask. */ -#define TC2_LCMPCINTLVL_gp 4 /* Low Byte Compare C Interrupt Level group position. */ -#define TC2_LCMPCINTLVL0_bm (1<<4) /* Low Byte Compare C Interrupt Level bit 0 mask. */ -#define TC2_LCMPCINTLVL0_bp 4 /* Low Byte Compare C Interrupt Level bit 0 position. */ -#define TC2_LCMPCINTLVL1_bm (1<<5) /* Low Byte Compare C Interrupt Level bit 1 mask. */ -#define TC2_LCMPCINTLVL1_bp 5 /* Low Byte Compare C Interrupt Level bit 1 position. */ - -#define TC2_LCMPBINTLVL_gm 0x0C /* Low Byte Compare B Interrupt Level group mask. */ -#define TC2_LCMPBINTLVL_gp 2 /* Low Byte Compare B Interrupt Level group position. */ -#define TC2_LCMPBINTLVL0_bm (1<<2) /* Low Byte Compare B Interrupt Level bit 0 mask. */ -#define TC2_LCMPBINTLVL0_bp 2 /* Low Byte Compare B Interrupt Level bit 0 position. */ -#define TC2_LCMPBINTLVL1_bm (1<<3) /* Low Byte Compare B Interrupt Level bit 1 mask. */ -#define TC2_LCMPBINTLVL1_bp 3 /* Low Byte Compare B Interrupt Level bit 1 position. */ - -#define TC2_LCMPAINTLVL_gm 0x03 /* Low Byte Compare A Interrupt Level group mask. */ -#define TC2_LCMPAINTLVL_gp 0 /* Low Byte Compare A Interrupt Level group position. */ -#define TC2_LCMPAINTLVL0_bm (1<<0) /* Low Byte Compare A Interrupt Level bit 0 mask. */ -#define TC2_LCMPAINTLVL0_bp 0 /* Low Byte Compare A Interrupt Level bit 0 position. */ -#define TC2_LCMPAINTLVL1_bm (1<<1) /* Low Byte Compare A Interrupt Level bit 1 mask. */ -#define TC2_LCMPAINTLVL1_bp 1 /* Low Byte Compare A Interrupt Level bit 1 position. */ - -/* TC2.CTRLF bit masks and bit positions */ -#define TC2_CMD_gm 0x0C /* Command group mask. */ -#define TC2_CMD_gp 2 /* Command group position. */ -#define TC2_CMD0_bm (1<<2) /* Command bit 0 mask. */ -#define TC2_CMD0_bp 2 /* Command bit 0 position. */ -#define TC2_CMD1_bm (1<<3) /* Command bit 1 mask. */ -#define TC2_CMD1_bp 3 /* Command bit 1 position. */ - -#define TC2_CMDEN_gm 0x03 /* Command Enable group mask. */ -#define TC2_CMDEN_gp 0 /* Command Enable group position. */ -#define TC2_CMDEN0_bm (1<<0) /* Command Enable bit 0 mask. */ -#define TC2_CMDEN0_bp 0 /* Command Enable bit 0 position. */ -#define TC2_CMDEN1_bm (1<<1) /* Command Enable bit 1 mask. */ -#define TC2_CMDEN1_bp 1 /* Command Enable bit 1 position. */ - -/* TC2.INTFLAGS bit masks and bit positions */ -#define TC2_LCMPDIF_bm 0x80 /* Low Byte Compare D Interrupt Flag bit mask. */ -#define TC2_LCMPDIF_bp 7 /* Low Byte Compare D Interrupt Flag bit position. */ - -#define TC2_LCMPCIF_bm 0x40 /* Low Byte Compare C Interrupt Flag bit mask. */ -#define TC2_LCMPCIF_bp 6 /* Low Byte Compare C Interrupt Flag bit position. */ - -#define TC2_LCMPBIF_bm 0x20 /* Low Byte Compare B Interrupt Flag bit mask. */ -#define TC2_LCMPBIF_bp 5 /* Low Byte Compare B Interrupt Flag bit position. */ - -#define TC2_LCMPAIF_bm 0x10 /* Low Byte Compare A Interrupt Flag bit mask. */ -#define TC2_LCMPAIF_bp 4 /* Low Byte Compare A Interrupt Flag bit position. */ - -#define TC2_HUNFIF_bm 0x02 /* High Byte Underflow Interrupt Flag bit mask. */ -#define TC2_HUNFIF_bp 1 /* High Byte Underflow Interrupt Flag bit position. */ - -#define TC2_LUNFIF_bm 0x01 /* Low Byte Underflow Interrupt Flag bit mask. */ -#define TC2_LUNFIF_bp 0 /* Low Byte Underflow Interrupt Flag bit position. */ - -/* AWEX - Timer/Counter Advanced Waveform Extension */ -/* AWEX.CTRL bit masks and bit positions */ -#define AWEX_PGM_bm 0x20 /* Pattern Generation Mode bit mask. */ -#define AWEX_PGM_bp 5 /* Pattern Generation Mode bit position. */ - -#define AWEX_CWCM_bm 0x10 /* Common Waveform Channel Mode bit mask. */ -#define AWEX_CWCM_bp 4 /* Common Waveform Channel Mode bit position. */ - -#define AWEX_DTICCDEN_bm 0x08 /* Dead Time Insertion Compare Channel D Enable bit mask. */ -#define AWEX_DTICCDEN_bp 3 /* Dead Time Insertion Compare Channel D Enable bit position. */ - -#define AWEX_DTICCCEN_bm 0x04 /* Dead Time Insertion Compare Channel C Enable bit mask. */ -#define AWEX_DTICCCEN_bp 2 /* Dead Time Insertion Compare Channel C Enable bit position. */ - -#define AWEX_DTICCBEN_bm 0x02 /* Dead Time Insertion Compare Channel B Enable bit mask. */ -#define AWEX_DTICCBEN_bp 1 /* Dead Time Insertion Compare Channel B Enable bit position. */ - -#define AWEX_DTICCAEN_bm 0x01 /* Dead Time Insertion Compare Channel A Enable bit mask. */ -#define AWEX_DTICCAEN_bp 0 /* Dead Time Insertion Compare Channel A Enable bit position. */ - -/* AWEX.FDCTRL bit masks and bit positions */ -#define AWEX_FDDBD_bm 0x10 /* Fault Detect on Disable Break Disable bit mask. */ -#define AWEX_FDDBD_bp 4 /* Fault Detect on Disable Break Disable bit position. */ - -#define AWEX_FDMODE_bm 0x04 /* Fault Detect Mode bit mask. */ -#define AWEX_FDMODE_bp 2 /* Fault Detect Mode bit position. */ - -#define AWEX_FDACT_gm 0x03 /* Fault Detect Action group mask. */ -#define AWEX_FDACT_gp 0 /* Fault Detect Action group position. */ -#define AWEX_FDACT0_bm (1<<0) /* Fault Detect Action bit 0 mask. */ -#define AWEX_FDACT0_bp 0 /* Fault Detect Action bit 0 position. */ -#define AWEX_FDACT1_bm (1<<1) /* Fault Detect Action bit 1 mask. */ -#define AWEX_FDACT1_bp 1 /* Fault Detect Action bit 1 position. */ - -/* AWEX.STATUS bit masks and bit positions */ -#define AWEX_FDF_bm 0x04 /* Fault Detect Flag bit mask. */ -#define AWEX_FDF_bp 2 /* Fault Detect Flag bit position. */ - -#define AWEX_DTHSBUFV_bm 0x02 /* Dead Time High Side Buffer Valid bit mask. */ -#define AWEX_DTHSBUFV_bp 1 /* Dead Time High Side Buffer Valid bit position. */ - -#define AWEX_DTLSBUFV_bm 0x01 /* Dead Time Low Side Buffer Valid bit mask. */ -#define AWEX_DTLSBUFV_bp 0 /* Dead Time Low Side Buffer Valid bit position. */ - -/* AWEX.STATUSSET bit masks and bit positions */ -/* AWEX_FDF Predefined. */ -/* AWEX_FDF Predefined. */ - -/* AWEX_DTHSBUFV Predefined. */ -/* AWEX_DTHSBUFV Predefined. */ - -/* AWEX_DTLSBUFV Predefined. */ -/* AWEX_DTLSBUFV Predefined. */ - -/* HIRES - Timer/Counter High-Resolution Extension */ -/* HIRES.CTRLA bit masks and bit positions */ -#define HIRES_HREN_gm 0x03 /* High Resolution Enable group mask. */ -#define HIRES_HREN_gp 0 /* High Resolution Enable group position. */ -#define HIRES_HREN0_bm (1<<0) /* High Resolution Enable bit 0 mask. */ -#define HIRES_HREN0_bp 0 /* High Resolution Enable bit 0 position. */ -#define HIRES_HREN1_bm (1<<1) /* High Resolution Enable bit 1 mask. */ -#define HIRES_HREN1_bp 1 /* High Resolution Enable bit 1 position. */ - -/* USART - Universal Asynchronous Receiver-Transmitter */ -/* USART.STATUS bit masks and bit positions */ -#define USART_RXCIF_bm 0x80 /* Receive Interrupt Flag bit mask. */ -#define USART_RXCIF_bp 7 /* Receive Interrupt Flag bit position. */ - -#define USART_TXCIF_bm 0x40 /* Transmit Interrupt Flag bit mask. */ -#define USART_TXCIF_bp 6 /* Transmit Interrupt Flag bit position. */ - -#define USART_DREIF_bm 0x20 /* Data Register Empty Flag bit mask. */ -#define USART_DREIF_bp 5 /* Data Register Empty Flag bit position. */ - -#define USART_FERR_bm 0x10 /* Frame Error bit mask. */ -#define USART_FERR_bp 4 /* Frame Error bit position. */ - -#define USART_BUFOVF_bm 0x08 /* Buffer Overflow bit mask. */ -#define USART_BUFOVF_bp 3 /* Buffer Overflow bit position. */ - -#define USART_PERR_bm 0x04 /* Parity Error bit mask. */ -#define USART_PERR_bp 2 /* Parity Error bit position. */ - -#define USART_RXB8_bm 0x01 /* Receive Bit 8 bit mask. */ -#define USART_RXB8_bp 0 /* Receive Bit 8 bit position. */ - -/* USART.CTRLA bit masks and bit positions */ -#define USART_RXCINTLVL_gm 0x30 /* Receive Interrupt Level group mask. */ -#define USART_RXCINTLVL_gp 4 /* Receive Interrupt Level group position. */ -#define USART_RXCINTLVL0_bm (1<<4) /* Receive Interrupt Level bit 0 mask. */ -#define USART_RXCINTLVL0_bp 4 /* Receive Interrupt Level bit 0 position. */ -#define USART_RXCINTLVL1_bm (1<<5) /* Receive Interrupt Level bit 1 mask. */ -#define USART_RXCINTLVL1_bp 5 /* Receive Interrupt Level bit 1 position. */ - -#define USART_TXCINTLVL_gm 0x0C /* Transmit Interrupt Level group mask. */ -#define USART_TXCINTLVL_gp 2 /* Transmit Interrupt Level group position. */ -#define USART_TXCINTLVL0_bm (1<<2) /* Transmit Interrupt Level bit 0 mask. */ -#define USART_TXCINTLVL0_bp 2 /* Transmit Interrupt Level bit 0 position. */ -#define USART_TXCINTLVL1_bm (1<<3) /* Transmit Interrupt Level bit 1 mask. */ -#define USART_TXCINTLVL1_bp 3 /* Transmit Interrupt Level bit 1 position. */ - -#define USART_DREINTLVL_gm 0x03 /* Data Register Empty Interrupt Level group mask. */ -#define USART_DREINTLVL_gp 0 /* Data Register Empty Interrupt Level group position. */ -#define USART_DREINTLVL0_bm (1<<0) /* Data Register Empty Interrupt Level bit 0 mask. */ -#define USART_DREINTLVL0_bp 0 /* Data Register Empty Interrupt Level bit 0 position. */ -#define USART_DREINTLVL1_bm (1<<1) /* Data Register Empty Interrupt Level bit 1 mask. */ -#define USART_DREINTLVL1_bp 1 /* Data Register Empty Interrupt Level bit 1 position. */ - -/* USART.CTRLB bit masks and bit positions */ -#define USART_RXEN_bm 0x10 /* Receiver Enable bit mask. */ -#define USART_RXEN_bp 4 /* Receiver Enable bit position. */ - -#define USART_TXEN_bm 0x08 /* Transmitter Enable bit mask. */ -#define USART_TXEN_bp 3 /* Transmitter Enable bit position. */ - -#define USART_CLK2X_bm 0x04 /* Double transmission speed bit mask. */ -#define USART_CLK2X_bp 2 /* Double transmission speed bit position. */ - -#define USART_MPCM_bm 0x02 /* Multi-processor Communication Mode bit mask. */ -#define USART_MPCM_bp 1 /* Multi-processor Communication Mode bit position. */ - -#define USART_TXB8_bm 0x01 /* Transmit bit 8 bit mask. */ -#define USART_TXB8_bp 0 /* Transmit bit 8 bit position. */ - -/* USART.CTRLC bit masks and bit positions */ -#define USART_CMODE_gm 0xC0 /* Communication Mode group mask. */ -#define USART_CMODE_gp 6 /* Communication Mode group position. */ -#define USART_CMODE0_bm (1<<6) /* Communication Mode bit 0 mask. */ -#define USART_CMODE0_bp 6 /* Communication Mode bit 0 position. */ -#define USART_CMODE1_bm (1<<7) /* Communication Mode bit 1 mask. */ -#define USART_CMODE1_bp 7 /* Communication Mode bit 1 position. */ - -#define USART_PMODE_gm 0x30 /* Parity Mode group mask. */ -#define USART_PMODE_gp 4 /* Parity Mode group position. */ -#define USART_PMODE0_bm (1<<4) /* Parity Mode bit 0 mask. */ -#define USART_PMODE0_bp 4 /* Parity Mode bit 0 position. */ -#define USART_PMODE1_bm (1<<5) /* Parity Mode bit 1 mask. */ -#define USART_PMODE1_bp 5 /* Parity Mode bit 1 position. */ - -#define USART_SBMODE_bm 0x08 /* Stop Bit Mode bit mask. */ -#define USART_SBMODE_bp 3 /* Stop Bit Mode bit position. */ - -#define USART_CHSIZE_gm 0x07 /* Character Size group mask. */ -#define USART_CHSIZE_gp 0 /* Character Size group position. */ -#define USART_CHSIZE0_bm (1<<0) /* Character Size bit 0 mask. */ -#define USART_CHSIZE0_bp 0 /* Character Size bit 0 position. */ -#define USART_CHSIZE1_bm (1<<1) /* Character Size bit 1 mask. */ -#define USART_CHSIZE1_bp 1 /* Character Size bit 1 position. */ -#define USART_CHSIZE2_bm (1<<2) /* Character Size bit 2 mask. */ -#define USART_CHSIZE2_bp 2 /* Character Size bit 2 position. */ - -/* USART.BAUDCTRLA bit masks and bit positions */ -#define USART_BSEL_gm 0xFF /* Baud Rate Selection Bits [7:0] group mask. */ -#define USART_BSEL_gp 0 /* Baud Rate Selection Bits [7:0] group position. */ -#define USART_BSEL0_bm (1<<0) /* Baud Rate Selection Bits [7:0] bit 0 mask. */ -#define USART_BSEL0_bp 0 /* Baud Rate Selection Bits [7:0] bit 0 position. */ -#define USART_BSEL1_bm (1<<1) /* Baud Rate Selection Bits [7:0] bit 1 mask. */ -#define USART_BSEL1_bp 1 /* Baud Rate Selection Bits [7:0] bit 1 position. */ -#define USART_BSEL2_bm (1<<2) /* Baud Rate Selection Bits [7:0] bit 2 mask. */ -#define USART_BSEL2_bp 2 /* Baud Rate Selection Bits [7:0] bit 2 position. */ -#define USART_BSEL3_bm (1<<3) /* Baud Rate Selection Bits [7:0] bit 3 mask. */ -#define USART_BSEL3_bp 3 /* Baud Rate Selection Bits [7:0] bit 3 position. */ -#define USART_BSEL4_bm (1<<4) /* Baud Rate Selection Bits [7:0] bit 4 mask. */ -#define USART_BSEL4_bp 4 /* Baud Rate Selection Bits [7:0] bit 4 position. */ -#define USART_BSEL5_bm (1<<5) /* Baud Rate Selection Bits [7:0] bit 5 mask. */ -#define USART_BSEL5_bp 5 /* Baud Rate Selection Bits [7:0] bit 5 position. */ -#define USART_BSEL6_bm (1<<6) /* Baud Rate Selection Bits [7:0] bit 6 mask. */ -#define USART_BSEL6_bp 6 /* Baud Rate Selection Bits [7:0] bit 6 position. */ -#define USART_BSEL7_bm (1<<7) /* Baud Rate Selection Bits [7:0] bit 7 mask. */ -#define USART_BSEL7_bp 7 /* Baud Rate Selection Bits [7:0] bit 7 position. */ - -/* USART.BAUDCTRLB bit masks and bit positions */ -#define USART_BSCALE_gm 0xF0 /* Baud Rate Scale group mask. */ -#define USART_BSCALE_gp 4 /* Baud Rate Scale group position. */ -#define USART_BSCALE0_bm (1<<4) /* Baud Rate Scale bit 0 mask. */ -#define USART_BSCALE0_bp 4 /* Baud Rate Scale bit 0 position. */ -#define USART_BSCALE1_bm (1<<5) /* Baud Rate Scale bit 1 mask. */ -#define USART_BSCALE1_bp 5 /* Baud Rate Scale bit 1 position. */ -#define USART_BSCALE2_bm (1<<6) /* Baud Rate Scale bit 2 mask. */ -#define USART_BSCALE2_bp 6 /* Baud Rate Scale bit 2 position. */ -#define USART_BSCALE3_bm (1<<7) /* Baud Rate Scale bit 3 mask. */ -#define USART_BSCALE3_bp 7 /* Baud Rate Scale bit 3 position. */ - -/* USART_BSEL Predefined. */ -/* USART_BSEL Predefined. */ - -/* SPI - Serial Peripheral Interface */ -/* SPI.CTRL bit masks and bit positions */ -#define SPI_CLK2X_bm 0x80 /* Enable Double Speed bit mask. */ -#define SPI_CLK2X_bp 7 /* Enable Double Speed bit position. */ - -#define SPI_ENABLE_bm 0x40 /* Enable Module bit mask. */ -#define SPI_ENABLE_bp 6 /* Enable Module bit position. */ - -#define SPI_DORD_bm 0x20 /* Data Order Setting bit mask. */ -#define SPI_DORD_bp 5 /* Data Order Setting bit position. */ - -#define SPI_MASTER_bm 0x10 /* Master Operation Enable bit mask. */ -#define SPI_MASTER_bp 4 /* Master Operation Enable bit position. */ - -#define SPI_MODE_gm 0x0C /* SPI Mode group mask. */ -#define SPI_MODE_gp 2 /* SPI Mode group position. */ -#define SPI_MODE0_bm (1<<2) /* SPI Mode bit 0 mask. */ -#define SPI_MODE0_bp 2 /* SPI Mode bit 0 position. */ -#define SPI_MODE1_bm (1<<3) /* SPI Mode bit 1 mask. */ -#define SPI_MODE1_bp 3 /* SPI Mode bit 1 position. */ - -#define SPI_PRESCALER_gm 0x03 /* Prescaler group mask. */ -#define SPI_PRESCALER_gp 0 /* Prescaler group position. */ -#define SPI_PRESCALER0_bm (1<<0) /* Prescaler bit 0 mask. */ -#define SPI_PRESCALER0_bp 0 /* Prescaler bit 0 position. */ -#define SPI_PRESCALER1_bm (1<<1) /* Prescaler bit 1 mask. */ -#define SPI_PRESCALER1_bp 1 /* Prescaler bit 1 position. */ - -/* SPI.INTCTRL bit masks and bit positions */ -#define SPI_INTLVL_gm 0x03 /* Interrupt level group mask. */ -#define SPI_INTLVL_gp 0 /* Interrupt level group position. */ -#define SPI_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */ -#define SPI_INTLVL0_bp 0 /* Interrupt level bit 0 position. */ -#define SPI_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */ -#define SPI_INTLVL1_bp 1 /* Interrupt level bit 1 position. */ - -/* SPI.STATUS bit masks and bit positions */ -#define SPI_IF_bm 0x80 /* Interrupt Flag bit mask. */ -#define SPI_IF_bp 7 /* Interrupt Flag bit position. */ - -#define SPI_WRCOL_bm 0x40 /* Write Collision bit mask. */ -#define SPI_WRCOL_bp 6 /* Write Collision bit position. */ - -/* IRCOM - IR Communication Module */ -/* IRCOM.CTRL bit masks and bit positions */ -#define IRCOM_EVSEL_gm 0x0F /* Event Channel Select group mask. */ -#define IRCOM_EVSEL_gp 0 /* Event Channel Select group position. */ -#define IRCOM_EVSEL0_bm (1<<0) /* Event Channel Select bit 0 mask. */ -#define IRCOM_EVSEL0_bp 0 /* Event Channel Select bit 0 position. */ -#define IRCOM_EVSEL1_bm (1<<1) /* Event Channel Select bit 1 mask. */ -#define IRCOM_EVSEL1_bp 1 /* Event Channel Select bit 1 position. */ -#define IRCOM_EVSEL2_bm (1<<2) /* Event Channel Select bit 2 mask. */ -#define IRCOM_EVSEL2_bp 2 /* Event Channel Select bit 2 position. */ -#define IRCOM_EVSEL3_bm (1<<3) /* Event Channel Select bit 3 mask. */ -#define IRCOM_EVSEL3_bp 3 /* Event Channel Select bit 3 position. */ - -/* FUSE - Fuses and Lockbits */ -/* NVM_FUSES.FUSEBYTE0 bit masks and bit positions */ -#define NVM_FUSES_JTAGUSERID_gm 0xFF /* JTAG User ID group mask. */ -#define NVM_FUSES_JTAGUSERID_gp 0 /* JTAG User ID group position. */ -#define NVM_FUSES_JTAGUSERID0_bm (1<<0) /* JTAG User ID bit 0 mask. */ -#define NVM_FUSES_JTAGUSERID0_bp 0 /* JTAG User ID bit 0 position. */ -#define NVM_FUSES_JTAGUSERID1_bm (1<<1) /* JTAG User ID bit 1 mask. */ -#define NVM_FUSES_JTAGUSERID1_bp 1 /* JTAG User ID bit 1 position. */ -#define NVM_FUSES_JTAGUSERID2_bm (1<<2) /* JTAG User ID bit 2 mask. */ -#define NVM_FUSES_JTAGUSERID2_bp 2 /* JTAG User ID bit 2 position. */ -#define NVM_FUSES_JTAGUSERID3_bm (1<<3) /* JTAG User ID bit 3 mask. */ -#define NVM_FUSES_JTAGUSERID3_bp 3 /* JTAG User ID bit 3 position. */ -#define NVM_FUSES_JTAGUSERID4_bm (1<<4) /* JTAG User ID bit 4 mask. */ -#define NVM_FUSES_JTAGUSERID4_bp 4 /* JTAG User ID bit 4 position. */ -#define NVM_FUSES_JTAGUSERID5_bm (1<<5) /* JTAG User ID bit 5 mask. */ -#define NVM_FUSES_JTAGUSERID5_bp 5 /* JTAG User ID bit 5 position. */ -#define NVM_FUSES_JTAGUSERID6_bm (1<<6) /* JTAG User ID bit 6 mask. */ -#define NVM_FUSES_JTAGUSERID6_bp 6 /* JTAG User ID bit 6 position. */ -#define NVM_FUSES_JTAGUSERID7_bm (1<<7) /* JTAG User ID bit 7 mask. */ -#define NVM_FUSES_JTAGUSERID7_bp 7 /* JTAG User ID bit 7 position. */ - -/* NVM_FUSES.FUSEBYTE1 bit masks and bit positions */ -#define NVM_FUSES_WDWP_gm 0xF0 /* Watchdog Window Timeout Period group mask. */ -#define NVM_FUSES_WDWP_gp 4 /* Watchdog Window Timeout Period group position. */ -#define NVM_FUSES_WDWP0_bm (1<<4) /* Watchdog Window Timeout Period bit 0 mask. */ -#define NVM_FUSES_WDWP0_bp 4 /* Watchdog Window Timeout Period bit 0 position. */ -#define NVM_FUSES_WDWP1_bm (1<<5) /* Watchdog Window Timeout Period bit 1 mask. */ -#define NVM_FUSES_WDWP1_bp 5 /* Watchdog Window Timeout Period bit 1 position. */ -#define NVM_FUSES_WDWP2_bm (1<<6) /* Watchdog Window Timeout Period bit 2 mask. */ -#define NVM_FUSES_WDWP2_bp 6 /* Watchdog Window Timeout Period bit 2 position. */ -#define NVM_FUSES_WDWP3_bm (1<<7) /* Watchdog Window Timeout Period bit 3 mask. */ -#define NVM_FUSES_WDWP3_bp 7 /* Watchdog Window Timeout Period bit 3 position. */ - -#define NVM_FUSES_WDP_gm 0x0F /* Watchdog Timeout Period group mask. */ -#define NVM_FUSES_WDP_gp 0 /* Watchdog Timeout Period group position. */ -#define NVM_FUSES_WDP0_bm (1<<0) /* Watchdog Timeout Period bit 0 mask. */ -#define NVM_FUSES_WDP0_bp 0 /* Watchdog Timeout Period bit 0 position. */ -#define NVM_FUSES_WDP1_bm (1<<1) /* Watchdog Timeout Period bit 1 mask. */ -#define NVM_FUSES_WDP1_bp 1 /* Watchdog Timeout Period bit 1 position. */ -#define NVM_FUSES_WDP2_bm (1<<2) /* Watchdog Timeout Period bit 2 mask. */ -#define NVM_FUSES_WDP2_bp 2 /* Watchdog Timeout Period bit 2 position. */ -#define NVM_FUSES_WDP3_bm (1<<3) /* Watchdog Timeout Period bit 3 mask. */ -#define NVM_FUSES_WDP3_bp 3 /* Watchdog Timeout Period bit 3 position. */ - -/* NVM_FUSES.FUSEBYTE2 bit masks and bit positions */ -#define NVM_FUSES_BOOTRST_bm 0x40 /* Boot Loader Section Reset Vector bit mask. */ -#define NVM_FUSES_BOOTRST_bp 6 /* Boot Loader Section Reset Vector bit position. */ - -#define NVM_FUSES_TOSCSEL_bm 0x20 /* Timer Oscillator pin location bit mask. */ -#define NVM_FUSES_TOSCSEL_bp 5 /* Timer Oscillator pin location bit position. */ - -#define NVM_FUSES_BODPD_gm 0x03 /* BOD Operation in Power-Down Mode group mask. */ -#define NVM_FUSES_BODPD_gp 0 /* BOD Operation in Power-Down Mode group position. */ -#define NVM_FUSES_BODPD0_bm (1<<0) /* BOD Operation in Power-Down Mode bit 0 mask. */ -#define NVM_FUSES_BODPD0_bp 0 /* BOD Operation in Power-Down Mode bit 0 position. */ -#define NVM_FUSES_BODPD1_bm (1<<1) /* BOD Operation in Power-Down Mode bit 1 mask. */ -#define NVM_FUSES_BODPD1_bp 1 /* BOD Operation in Power-Down Mode bit 1 position. */ - -/* NVM_FUSES.FUSEBYTE4 bit masks and bit positions */ -#define NVM_FUSES_RSTDISBL_bm 0x10 /* External Reset Disable bit mask. */ -#define NVM_FUSES_RSTDISBL_bp 4 /* External Reset Disable bit position. */ - -#define NVM_FUSES_SUT_gm 0x0C /* Start-up Time group mask. */ -#define NVM_FUSES_SUT_gp 2 /* Start-up Time group position. */ -#define NVM_FUSES_SUT0_bm (1<<2) /* Start-up Time bit 0 mask. */ -#define NVM_FUSES_SUT0_bp 2 /* Start-up Time bit 0 position. */ -#define NVM_FUSES_SUT1_bm (1<<3) /* Start-up Time bit 1 mask. */ -#define NVM_FUSES_SUT1_bp 3 /* Start-up Time bit 1 position. */ - -#define NVM_FUSES_WDLOCK_bm 0x02 /* Watchdog Timer Lock bit mask. */ -#define NVM_FUSES_WDLOCK_bp 1 /* Watchdog Timer Lock bit position. */ - -#define NVM_FUSES_JTAGEN_bm 0x01 /* JTAG Interface Enable bit mask. */ -#define NVM_FUSES_JTAGEN_bp 0 /* JTAG Interface Enable bit position. */ - -/* NVM_FUSES.FUSEBYTE5 bit masks and bit positions */ -#define NVM_FUSES_BODACT_gm 0x30 /* BOD Operation in Active Mode group mask. */ -#define NVM_FUSES_BODACT_gp 4 /* BOD Operation in Active Mode group position. */ -#define NVM_FUSES_BODACT0_bm (1<<4) /* BOD Operation in Active Mode bit 0 mask. */ -#define NVM_FUSES_BODACT0_bp 4 /* BOD Operation in Active Mode bit 0 position. */ -#define NVM_FUSES_BODACT1_bm (1<<5) /* BOD Operation in Active Mode bit 1 mask. */ -#define NVM_FUSES_BODACT1_bp 5 /* BOD Operation in Active Mode bit 1 position. */ - -#define NVM_FUSES_EESAVE_bm 0x08 /* Preserve EEPROM Through Chip Erase bit mask. */ -#define NVM_FUSES_EESAVE_bp 3 /* Preserve EEPROM Through Chip Erase bit position. */ - -#define NVM_FUSES_BODLVL_gm 0x07 /* Brownout Detection Voltage Level group mask. */ -#define NVM_FUSES_BODLVL_gp 0 /* Brownout Detection Voltage Level group position. */ -#define NVM_FUSES_BODLVL0_bm (1<<0) /* Brownout Detection Voltage Level bit 0 mask. */ -#define NVM_FUSES_BODLVL0_bp 0 /* Brownout Detection Voltage Level bit 0 position. */ -#define NVM_FUSES_BODLVL1_bm (1<<1) /* Brownout Detection Voltage Level bit 1 mask. */ -#define NVM_FUSES_BODLVL1_bp 1 /* Brownout Detection Voltage Level bit 1 position. */ -#define NVM_FUSES_BODLVL2_bm (1<<2) /* Brownout Detection Voltage Level bit 2 mask. */ -#define NVM_FUSES_BODLVL2_bp 2 /* Brownout Detection Voltage Level bit 2 position. */ - -/* LOCKBIT - Fuses and Lockbits */ -/* NVM_LOCKBITS.LOCKBITS bit masks and bit positions */ -#define NVM_LOCKBITS_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ -#define NVM_LOCKBITS_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ -#define NVM_LOCKBITS_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ -#define NVM_LOCKBITS_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ -#define NVM_LOCKBITS_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ -#define NVM_LOCKBITS_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ - -#define NVM_LOCKBITS_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ -#define NVM_LOCKBITS_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ -#define NVM_LOCKBITS_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ -#define NVM_LOCKBITS_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ -#define NVM_LOCKBITS_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ -#define NVM_LOCKBITS_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ - -#define NVM_LOCKBITS_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ -#define NVM_LOCKBITS_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ -#define NVM_LOCKBITS_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ -#define NVM_LOCKBITS_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ -#define NVM_LOCKBITS_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ -#define NVM_LOCKBITS_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ - -#define NVM_LOCKBITS_LB_gm 0x03 /* Lock Bits group mask. */ -#define NVM_LOCKBITS_LB_gp 0 /* Lock Bits group position. */ -#define NVM_LOCKBITS_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ -#define NVM_LOCKBITS_LB0_bp 0 /* Lock Bits bit 0 position. */ -#define NVM_LOCKBITS_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ -#define NVM_LOCKBITS_LB1_bp 1 /* Lock Bits bit 1 position. */ - - - -// Generic Port Pins - -#define PIN0_bm 0x01 -#define PIN0_bp 0 -#define PIN1_bm 0x02 -#define PIN1_bp 1 -#define PIN2_bm 0x04 -#define PIN2_bp 2 -#define PIN3_bm 0x08 -#define PIN3_bp 3 -#define PIN4_bm 0x10 -#define PIN4_bp 4 -#define PIN5_bm 0x20 -#define PIN5_bp 5 -#define PIN6_bm 0x40 -#define PIN6_bp 6 -#define PIN7_bm 0x80 -#define PIN7_bp 7 - -/* ========== Interrupt Vector Definitions ========== */ -/* Vector 0 is the reset vector */ - -/* OSC interrupt vectors */ -#define OSC_OSCF_vect_num 1 -#define OSC_OSCF_vect _VECTOR(1) /* Oscillator Failure Interrupt (NMI) */ - -/* PORTC interrupt vectors */ -#define PORTC_INT0_vect_num 2 -#define PORTC_INT0_vect _VECTOR(2) /* External Interrupt 0 */ -#define PORTC_INT1_vect_num 3 -#define PORTC_INT1_vect _VECTOR(3) /* External Interrupt 1 */ - -/* PORTR interrupt vectors */ -#define PORTR_INT0_vect_num 4 -#define PORTR_INT0_vect _VECTOR(4) /* External Interrupt 0 */ -#define PORTR_INT1_vect_num 5 -#define PORTR_INT1_vect _VECTOR(5) /* External Interrupt 1 */ - -/* DMA interrupt vectors */ -#define DMA_CH0_vect_num 6 -#define DMA_CH0_vect _VECTOR(6) /* Channel 0 Interrupt */ -#define DMA_CH1_vect_num 7 -#define DMA_CH1_vect _VECTOR(7) /* Channel 1 Interrupt */ -#define DMA_CH2_vect_num 8 -#define DMA_CH2_vect _VECTOR(8) /* Channel 2 Interrupt */ -#define DMA_CH3_vect_num 9 -#define DMA_CH3_vect _VECTOR(9) /* Channel 3 Interrupt */ - -/* RTC interrupt vectors */ -#define RTC_OVF_vect_num 10 -#define RTC_OVF_vect _VECTOR(10) /* Overflow Interrupt */ -#define RTC_COMP_vect_num 11 -#define RTC_COMP_vect _VECTOR(11) /* Compare Interrupt */ - -/* TWIC interrupt vectors */ -#define TWIC_TWIS_vect_num 12 -#define TWIC_TWIS_vect _VECTOR(12) /* TWI Slave Interrupt */ -#define TWIC_TWIM_vect_num 13 -#define TWIC_TWIM_vect _VECTOR(13) /* TWI Master Interrupt */ - -/* TCC0 interrupt vectors */ -#define TCC0_OVF_vect_num 14 -#define TCC0_OVF_vect _VECTOR(14) /* Overflow Interrupt */ - -/* TCC2 interrupt vectors */ -#define TCC2_LUNF_vect_num 14 -#define TCC2_LUNF_vect _VECTOR(14) /* Low Byte Underflow Interrupt */ - -/* TCC0 interrupt vectors */ -#define TCC0_ERR_vect_num 15 -#define TCC0_ERR_vect _VECTOR(15) /* Error Interrupt */ - -/* TCC2 interrupt vectors */ -#define TCC2_HUNF_vect_num 15 -#define TCC2_HUNF_vect _VECTOR(15) /* High Byte Underflow Interrupt */ - -/* TCC0 interrupt vectors */ -#define TCC0_CCA_vect_num 16 -#define TCC0_CCA_vect _VECTOR(16) /* Compare or Capture A Interrupt */ - -/* TCC2 interrupt vectors */ -#define TCC2_LCMPA_vect_num 16 -#define TCC2_LCMPA_vect _VECTOR(16) /* Low Byte Compare A Interrupt */ - -/* TCC0 interrupt vectors */ -#define TCC0_CCB_vect_num 17 -#define TCC0_CCB_vect _VECTOR(17) /* Compare or Capture B Interrupt */ - -/* TCC2 interrupt vectors */ -#define TCC2_LCMPB_vect_num 17 -#define TCC2_LCMPB_vect _VECTOR(17) /* Low Byte Compare B Interrupt */ - -/* TCC0 interrupt vectors */ -#define TCC0_CCC_vect_num 18 -#define TCC0_CCC_vect _VECTOR(18) /* Compare or Capture C Interrupt */ - -/* TCC2 interrupt vectors */ -#define TCC2_LCMPC_vect_num 18 -#define TCC2_LCMPC_vect _VECTOR(18) /* Low Byte Compare C Interrupt */ - -/* TCC0 interrupt vectors */ -#define TCC0_CCD_vect_num 19 -#define TCC0_CCD_vect _VECTOR(19) /* Compare or Capture D Interrupt */ - -/* TCC2 interrupt vectors */ -#define TCC2_LCMPD_vect_num 19 -#define TCC2_LCMPD_vect _VECTOR(19) /* Low Byte Compare D Interrupt */ - -/* TCC1 interrupt vectors */ -#define TCC1_OVF_vect_num 20 -#define TCC1_OVF_vect _VECTOR(20) /* Overflow Interrupt */ -#define TCC1_ERR_vect_num 21 -#define TCC1_ERR_vect _VECTOR(21) /* Error Interrupt */ -#define TCC1_CCA_vect_num 22 -#define TCC1_CCA_vect _VECTOR(22) /* Compare or Capture A Interrupt */ -#define TCC1_CCB_vect_num 23 -#define TCC1_CCB_vect _VECTOR(23) /* Compare or Capture B Interrupt */ - -/* SPIC interrupt vectors */ -#define SPIC_INT_vect_num 24 -#define SPIC_INT_vect _VECTOR(24) /* SPI Interrupt */ - -/* USARTC0 interrupt vectors */ -#define USARTC0_RXC_vect_num 25 -#define USARTC0_RXC_vect _VECTOR(25) /* Reception Complete Interrupt */ -#define USARTC0_DRE_vect_num 26 -#define USARTC0_DRE_vect _VECTOR(26) /* Data Register Empty Interrupt */ -#define USARTC0_TXC_vect_num 27 -#define USARTC0_TXC_vect _VECTOR(27) /* Transmission Complete Interrupt */ - -/* USARTC1 interrupt vectors */ -#define USARTC1_RXC_vect_num 28 -#define USARTC1_RXC_vect _VECTOR(28) /* Reception Complete Interrupt */ -#define USARTC1_DRE_vect_num 29 -#define USARTC1_DRE_vect _VECTOR(29) /* Data Register Empty Interrupt */ -#define USARTC1_TXC_vect_num 30 -#define USARTC1_TXC_vect _VECTOR(30) /* Transmission Complete Interrupt */ - -/* AES interrupt vectors */ -#define AES_INT_vect_num 31 -#define AES_INT_vect _VECTOR(31) /* AES Interrupt */ - -/* NVM interrupt vectors */ -#define NVM_EE_vect_num 32 -#define NVM_EE_vect _VECTOR(32) /* EE Interrupt */ -#define NVM_SPM_vect_num 33 -#define NVM_SPM_vect _VECTOR(33) /* SPM Interrupt */ - -/* PORTB interrupt vectors */ -#define PORTB_INT0_vect_num 34 -#define PORTB_INT0_vect _VECTOR(34) /* External Interrupt 0 */ -#define PORTB_INT1_vect_num 35 -#define PORTB_INT1_vect _VECTOR(35) /* External Interrupt 1 */ - -/* ACB interrupt vectors */ -#define ACB_AC0_vect_num 36 -#define ACB_AC0_vect _VECTOR(36) /* AC0 Interrupt */ -#define ACB_AC1_vect_num 37 -#define ACB_AC1_vect _VECTOR(37) /* AC1 Interrupt */ -#define ACB_ACW_vect_num 38 -#define ACB_ACW_vect _VECTOR(38) /* ACW Window Mode Interrupt */ - -/* ADCB interrupt vectors */ -#define ADCB_CH0_vect_num 39 -#define ADCB_CH0_vect _VECTOR(39) /* Interrupt 0 */ -#define ADCB_CH1_vect_num 40 -#define ADCB_CH1_vect _VECTOR(40) /* Interrupt 1 */ -#define ADCB_CH2_vect_num 41 -#define ADCB_CH2_vect _VECTOR(41) /* Interrupt 2 */ -#define ADCB_CH3_vect_num 42 -#define ADCB_CH3_vect _VECTOR(42) /* Interrupt 3 */ - -/* PORTE interrupt vectors */ -#define PORTE_INT0_vect_num 43 -#define PORTE_INT0_vect _VECTOR(43) /* External Interrupt 0 */ -#define PORTE_INT1_vect_num 44 -#define PORTE_INT1_vect _VECTOR(44) /* External Interrupt 1 */ - -/* TWIE interrupt vectors */ -#define TWIE_TWIS_vect_num 45 -#define TWIE_TWIS_vect _VECTOR(45) /* TWI Slave Interrupt */ -#define TWIE_TWIM_vect_num 46 -#define TWIE_TWIM_vect _VECTOR(46) /* TWI Master Interrupt */ - -/* TCE0 interrupt vectors */ -#define TCE0_OVF_vect_num 47 -#define TCE0_OVF_vect _VECTOR(47) /* Overflow Interrupt */ - -/* TCE2 interrupt vectors */ -#define TCE2_LUNF_vect_num 47 -#define TCE2_LUNF_vect _VECTOR(47) /* Low Byte Underflow Interrupt */ - -/* TCE0 interrupt vectors */ -#define TCE0_ERR_vect_num 48 -#define TCE0_ERR_vect _VECTOR(48) /* Error Interrupt */ - -/* TCE2 interrupt vectors */ -#define TCE2_HUNF_vect_num 48 -#define TCE2_HUNF_vect _VECTOR(48) /* High Byte Underflow Interrupt */ - -/* TCE0 interrupt vectors */ -#define TCE0_CCA_vect_num 49 -#define TCE0_CCA_vect _VECTOR(49) /* Compare or Capture A Interrupt */ - -/* TCE2 interrupt vectors */ -#define TCE2_LCMPA_vect_num 49 -#define TCE2_LCMPA_vect _VECTOR(49) /* Low Byte Compare A Interrupt */ - -/* TCE0 interrupt vectors */ -#define TCE0_CCB_vect_num 50 -#define TCE0_CCB_vect _VECTOR(50) /* Compare or Capture B Interrupt */ - -/* TCE2 interrupt vectors */ -#define TCE2_LCMPB_vect_num 50 -#define TCE2_LCMPB_vect _VECTOR(50) /* Low Byte Compare B Interrupt */ - -/* TCE0 interrupt vectors */ -#define TCE0_CCC_vect_num 51 -#define TCE0_CCC_vect _VECTOR(51) /* Compare or Capture C Interrupt */ - -/* TCE2 interrupt vectors */ -#define TCE2_LCMPC_vect_num 51 -#define TCE2_LCMPC_vect _VECTOR(51) /* Low Byte Compare C Interrupt */ - -/* TCE0 interrupt vectors */ -#define TCE0_CCD_vect_num 52 -#define TCE0_CCD_vect _VECTOR(52) /* Compare or Capture D Interrupt */ - -/* TCE2 interrupt vectors */ -#define TCE2_LCMPD_vect_num 52 -#define TCE2_LCMPD_vect _VECTOR(52) /* Low Byte Compare D Interrupt */ - -/* TCE1 interrupt vectors */ -#define TCE1_OVF_vect_num 53 -#define TCE1_OVF_vect _VECTOR(53) /* Overflow Interrupt */ -#define TCE1_ERR_vect_num 54 -#define TCE1_ERR_vect _VECTOR(54) /* Error Interrupt */ -#define TCE1_CCA_vect_num 55 -#define TCE1_CCA_vect _VECTOR(55) /* Compare or Capture A Interrupt */ -#define TCE1_CCB_vect_num 56 -#define TCE1_CCB_vect _VECTOR(56) /* Compare or Capture B Interrupt */ - -/* SPIE interrupt vectors */ -#define SPIE_INT_vect_num 57 -#define SPIE_INT_vect _VECTOR(57) /* SPI Interrupt */ - -/* USARTE0 interrupt vectors */ -#define USARTE0_RXC_vect_num 58 -#define USARTE0_RXC_vect _VECTOR(58) /* Reception Complete Interrupt */ -#define USARTE0_DRE_vect_num 59 -#define USARTE0_DRE_vect _VECTOR(59) /* Data Register Empty Interrupt */ -#define USARTE0_TXC_vect_num 60 -#define USARTE0_TXC_vect _VECTOR(60) /* Transmission Complete Interrupt */ - -/* USARTE1 interrupt vectors */ -#define USARTE1_RXC_vect_num 61 -#define USARTE1_RXC_vect _VECTOR(61) /* Reception Complete Interrupt */ -#define USARTE1_DRE_vect_num 62 -#define USARTE1_DRE_vect _VECTOR(62) /* Data Register Empty Interrupt */ -#define USARTE1_TXC_vect_num 63 -#define USARTE1_TXC_vect _VECTOR(63) /* Transmission Complete Interrupt */ - -/* PORTD interrupt vectors */ -#define PORTD_INT0_vect_num 64 -#define PORTD_INT0_vect _VECTOR(64) /* External Interrupt 0 */ -#define PORTD_INT1_vect_num 65 -#define PORTD_INT1_vect _VECTOR(65) /* External Interrupt 1 */ - -/* PORTA interrupt vectors */ -#define PORTA_INT0_vect_num 66 -#define PORTA_INT0_vect _VECTOR(66) /* External Interrupt 0 */ -#define PORTA_INT1_vect_num 67 -#define PORTA_INT1_vect _VECTOR(67) /* External Interrupt 1 */ - -/* ACA interrupt vectors */ -#define ACA_AC0_vect_num 68 -#define ACA_AC0_vect _VECTOR(68) /* AC0 Interrupt */ -#define ACA_AC1_vect_num 69 -#define ACA_AC1_vect _VECTOR(69) /* AC1 Interrupt */ -#define ACA_ACW_vect_num 70 -#define ACA_ACW_vect _VECTOR(70) /* ACW Window Mode Interrupt */ - -/* ADCA interrupt vectors */ -#define ADCA_CH0_vect_num 71 -#define ADCA_CH0_vect _VECTOR(71) /* Interrupt 0 */ -#define ADCA_CH1_vect_num 72 -#define ADCA_CH1_vect _VECTOR(72) /* Interrupt 1 */ -#define ADCA_CH2_vect_num 73 -#define ADCA_CH2_vect _VECTOR(73) /* Interrupt 2 */ -#define ADCA_CH3_vect_num 74 -#define ADCA_CH3_vect _VECTOR(74) /* Interrupt 3 */ - -/* TCD0 interrupt vectors */ -#define TCD0_OVF_vect_num 77 -#define TCD0_OVF_vect _VECTOR(77) /* Overflow Interrupt */ - -/* TCD2 interrupt vectors */ -#define TCD2_LUNF_vect_num 77 -#define TCD2_LUNF_vect _VECTOR(77) /* Low Byte Underflow Interrupt */ - -/* TCD0 interrupt vectors */ -#define TCD0_ERR_vect_num 78 -#define TCD0_ERR_vect _VECTOR(78) /* Error Interrupt */ - -/* TCD2 interrupt vectors */ -#define TCD2_HUNF_vect_num 78 -#define TCD2_HUNF_vect _VECTOR(78) /* High Byte Underflow Interrupt */ - -/* TCD0 interrupt vectors */ -#define TCD0_CCA_vect_num 79 -#define TCD0_CCA_vect _VECTOR(79) /* Compare or Capture A Interrupt */ - -/* TCD2 interrupt vectors */ -#define TCD2_LCMPA_vect_num 79 -#define TCD2_LCMPA_vect _VECTOR(79) /* Low Byte Compare A Interrupt */ - -/* TCD0 interrupt vectors */ -#define TCD0_CCB_vect_num 80 -#define TCD0_CCB_vect _VECTOR(80) /* Compare or Capture B Interrupt */ - -/* TCD2 interrupt vectors */ -#define TCD2_LCMPB_vect_num 80 -#define TCD2_LCMPB_vect _VECTOR(80) /* Low Byte Compare B Interrupt */ - -/* TCD0 interrupt vectors */ -#define TCD0_CCC_vect_num 81 -#define TCD0_CCC_vect _VECTOR(81) /* Compare or Capture C Interrupt */ - -/* TCD2 interrupt vectors */ -#define TCD2_LCMPC_vect_num 81 -#define TCD2_LCMPC_vect _VECTOR(81) /* Low Byte Compare C Interrupt */ - -/* TCD0 interrupt vectors */ -#define TCD0_CCD_vect_num 82 -#define TCD0_CCD_vect _VECTOR(82) /* Compare or Capture D Interrupt */ - -/* TCD2 interrupt vectors */ -#define TCD2_LCMPD_vect_num 82 -#define TCD2_LCMPD_vect _VECTOR(82) /* Low Byte Compare D Interrupt */ - -/* TCD1 interrupt vectors */ -#define TCD1_OVF_vect_num 83 -#define TCD1_OVF_vect _VECTOR(83) /* Overflow Interrupt */ -#define TCD1_ERR_vect_num 84 -#define TCD1_ERR_vect _VECTOR(84) /* Error Interrupt */ -#define TCD1_CCA_vect_num 85 -#define TCD1_CCA_vect _VECTOR(85) /* Compare or Capture A Interrupt */ -#define TCD1_CCB_vect_num 86 -#define TCD1_CCB_vect _VECTOR(86) /* Compare or Capture B Interrupt */ - -/* SPID interrupt vectors */ -#define SPID_INT_vect_num 87 -#define SPID_INT_vect _VECTOR(87) /* SPI Interrupt */ - -/* USARTD0 interrupt vectors */ -#define USARTD0_RXC_vect_num 88 -#define USARTD0_RXC_vect _VECTOR(88) /* Reception Complete Interrupt */ -#define USARTD0_DRE_vect_num 89 -#define USARTD0_DRE_vect _VECTOR(89) /* Data Register Empty Interrupt */ -#define USARTD0_TXC_vect_num 90 -#define USARTD0_TXC_vect _VECTOR(90) /* Transmission Complete Interrupt */ - -/* USARTD1 interrupt vectors */ -#define USARTD1_RXC_vect_num 91 -#define USARTD1_RXC_vect _VECTOR(91) /* Reception Complete Interrupt */ -#define USARTD1_DRE_vect_num 92 -#define USARTD1_DRE_vect _VECTOR(92) /* Data Register Empty Interrupt */ -#define USARTD1_TXC_vect_num 93 -#define USARTD1_TXC_vect _VECTOR(93) /* Transmission Complete Interrupt */ - -/* PORTF interrupt vectors */ -#define PORTF_INT0_vect_num 104 -#define PORTF_INT0_vect _VECTOR(104) /* External Interrupt 0 */ -#define PORTF_INT1_vect_num 105 -#define PORTF_INT1_vect _VECTOR(105) /* External Interrupt 1 */ - -/* TCF0 interrupt vectors */ -#define TCF0_OVF_vect_num 108 -#define TCF0_OVF_vect _VECTOR(108) /* Overflow Interrupt */ - -/* TCF2 interrupt vectors */ -#define TCF2_LUNF_vect_num 108 -#define TCF2_LUNF_vect _VECTOR(108) /* Low Byte Underflow Interrupt */ - -/* TCF0 interrupt vectors */ -#define TCF0_ERR_vect_num 109 -#define TCF0_ERR_vect _VECTOR(109) /* Error Interrupt */ - -/* TCF2 interrupt vectors */ -#define TCF2_HUNF_vect_num 109 -#define TCF2_HUNF_vect _VECTOR(109) /* High Byte Underflow Interrupt */ - -/* TCF0 interrupt vectors */ -#define TCF0_CCA_vect_num 110 -#define TCF0_CCA_vect _VECTOR(110) /* Compare or Capture A Interrupt */ - -/* TCF2 interrupt vectors */ -#define TCF2_LCMPA_vect_num 110 -#define TCF2_LCMPA_vect _VECTOR(110) /* Low Byte Compare A Interrupt */ - -/* TCF0 interrupt vectors */ -#define TCF0_CCB_vect_num 111 -#define TCF0_CCB_vect _VECTOR(111) /* Compare or Capture B Interrupt */ - -/* TCF2 interrupt vectors */ -#define TCF2_LCMPB_vect_num 111 -#define TCF2_LCMPB_vect _VECTOR(111) /* Low Byte Compare B Interrupt */ - -/* TCF0 interrupt vectors */ -#define TCF0_CCC_vect_num 112 -#define TCF0_CCC_vect _VECTOR(112) /* Compare or Capture C Interrupt */ - -/* TCF2 interrupt vectors */ -#define TCF2_LCMPC_vect_num 112 -#define TCF2_LCMPC_vect _VECTOR(112) /* Low Byte Compare C Interrupt */ - -/* TCF0 interrupt vectors */ -#define TCF0_CCD_vect_num 113 -#define TCF0_CCD_vect _VECTOR(113) /* Compare or Capture D Interrupt */ - -/* TCF2 interrupt vectors */ -#define TCF2_LCMPD_vect_num 113 -#define TCF2_LCMPD_vect _VECTOR(113) /* Low Byte Compare D Interrupt */ - -/* USARTF0 interrupt vectors */ -#define USARTF0_RXC_vect_num 119 -#define USARTF0_RXC_vect _VECTOR(119) /* Reception Complete Interrupt */ -#define USARTF0_DRE_vect_num 120 -#define USARTF0_DRE_vect _VECTOR(120) /* Data Register Empty Interrupt */ -#define USARTF0_TXC_vect_num 121 -#define USARTF0_TXC_vect _VECTOR(121) /* Transmission Complete Interrupt */ - -/* USB interrupt vectors */ -#define USB_BUSEVENT_vect_num 125 -#define USB_BUSEVENT_vect _VECTOR(125) /* SOF, suspend, resume, reset bus event interrupts, crc, underflow, overflow and stall error interrupts */ -#define USB_TRNCOMPL_vect_num 126 -#define USB_TRNCOMPL_vect _VECTOR(126) /* Transaction complete interrupt */ - -#define _VECTOR_SIZE 4 /* Size of individual vector. */ -#define _VECTORS_SIZE (127 * _VECTOR_SIZE) - - -/* ========== Constants ========== */ - -#define PROGMEM_START (0x0000) -#define PROGMEM_SIZE (139264) -#define PROGMEM_END (PROGMEM_START + PROGMEM_SIZE - 1) - -#define APP_SECTION_START (0x0000) -#define APP_SECTION_SIZE (131072) -#define APP_SECTION_PAGE_SIZE (512) -#define APP_SECTION_END (APP_SECTION_START + APP_SECTION_SIZE - 1) - -#define APPTABLE_SECTION_START (0x1E000) -#define APPTABLE_SECTION_SIZE (8192) -#define APPTABLE_SECTION_PAGE_SIZE (512) -#define APPTABLE_SECTION_END (APPTABLE_SECTION_START + APPTABLE_SECTION_SIZE - 1) - -#define BOOT_SECTION_START (0x20000) -#define BOOT_SECTION_SIZE (8192) -#define BOOT_SECTION_PAGE_SIZE (512) -#define BOOT_SECTION_END (BOOT_SECTION_START + BOOT_SECTION_SIZE - 1) - -#define DATAMEM_START (0x0000) -#define DATAMEM_SIZE (16384) -#define DATAMEM_END (DATAMEM_START + DATAMEM_SIZE - 1) - -#define IO_START (0x0000) -#define IO_SIZE (4096) -#define IO_PAGE_SIZE (0) -#define IO_END (IO_START + IO_SIZE - 1) - -#define MAPPED_EEPROM_START (0x1000) -#define MAPPED_EEPROM_SIZE (2048) -#define MAPPED_EEPROM_PAGE_SIZE (0) -#define MAPPED_EEPROM_END (MAPPED_EEPROM_START + MAPPED_EEPROM_SIZE - 1) - -#define INTERNAL_SRAM_START (0x2000) -#define INTERNAL_SRAM_SIZE (8192) -#define INTERNAL_SRAM_PAGE_SIZE (0) -#define INTERNAL_SRAM_END (INTERNAL_SRAM_START + INTERNAL_SRAM_SIZE - 1) - -#define EEPROM_START (0x0000) -#define EEPROM_SIZE (2048) -#define EEPROM_PAGE_SIZE (32) -#define EEPROM_END (EEPROM_START + EEPROM_SIZE - 1) - -#define SIGNATURES_START (0x0000) -#define SIGNATURES_SIZE (3) -#define SIGNATURES_PAGE_SIZE (0) -#define SIGNATURES_END (SIGNATURES_START + SIGNATURES_SIZE - 1) - -#define FUSES_START (0x0000) -#define FUSES_SIZE (6) -#define FUSES_PAGE_SIZE (0) -#define FUSES_END (FUSES_START + FUSES_SIZE - 1) - -#define LOCKBITS_START (0x0000) -#define LOCKBITS_SIZE (1) -#define LOCKBITS_PAGE_SIZE (0) -#define LOCKBITS_END (LOCKBITS_START + LOCKBITS_SIZE - 1) - -#define USER_SIGNATURES_START (0x0000) -#define USER_SIGNATURES_SIZE (512) -#define USER_SIGNATURES_PAGE_SIZE (512) -#define USER_SIGNATURES_END (USER_SIGNATURES_START + USER_SIGNATURES_SIZE - 1) - -#define PROD_SIGNATURES_START (0x0000) -#define PROD_SIGNATURES_SIZE (52) -#define PROD_SIGNATURES_PAGE_SIZE (512) -#define PROD_SIGNATURES_END (PROD_SIGNATURES_START + PROD_SIGNATURES_SIZE - 1) - -#define FLASHSTART PROGMEM_START -#define FLASHEND PROGMEM_END -#define SPM_PAGESIZE 512 -#define RAMSTART INTERNAL_SRAM_START -#define RAMSIZE INTERNAL_SRAM_SIZE -#define RAMEND INTERNAL_SRAM_END -#define E2END EEPROM_END -#define E2PAGESIZE EEPROM_PAGE_SIZE - - -/* ========== Fuses ========== */ -#define FUSE_MEMORY_SIZE 6 - -/* Fuse Byte 0 */ -#define FUSE_JTAGUSERID0 (unsigned char)~_BV(0) /* JTAG User ID Bit 0 */ -#define FUSE_JTAGUSERID1 (unsigned char)~_BV(1) /* JTAG User ID Bit 1 */ -#define FUSE_JTAGUSERID2 (unsigned char)~_BV(2) /* JTAG User ID Bit 2 */ -#define FUSE_JTAGUSERID3 (unsigned char)~_BV(3) /* JTAG User ID Bit 3 */ -#define FUSE_JTAGUSERID4 (unsigned char)~_BV(4) /* JTAG User ID Bit 4 */ -#define FUSE_JTAGUSERID5 (unsigned char)~_BV(5) /* JTAG User ID Bit 5 */ -#define FUSE_JTAGUSERID6 (unsigned char)~_BV(6) /* JTAG User ID Bit 6 */ -#define FUSE_JTAGUSERID7 (unsigned char)~_BV(7) /* JTAG User ID Bit 7 */ -#define FUSE0_DEFAULT (0xFF) - -/* Fuse Byte 1 */ -#define FUSE_WDP0 (unsigned char)~_BV(0) /* Watchdog Timeout Period Bit 0 */ -#define FUSE_WDP1 (unsigned char)~_BV(1) /* Watchdog Timeout Period Bit 1 */ -#define FUSE_WDP2 (unsigned char)~_BV(2) /* Watchdog Timeout Period Bit 2 */ -#define FUSE_WDP3 (unsigned char)~_BV(3) /* Watchdog Timeout Period Bit 3 */ -#define FUSE_WDWP0 (unsigned char)~_BV(4) /* Watchdog Window Timeout Period Bit 0 */ -#define FUSE_WDWP1 (unsigned char)~_BV(5) /* Watchdog Window Timeout Period Bit 1 */ -#define FUSE_WDWP2 (unsigned char)~_BV(6) /* Watchdog Window Timeout Period Bit 2 */ -#define FUSE_WDWP3 (unsigned char)~_BV(7) /* Watchdog Window Timeout Period Bit 3 */ -#define FUSE1_DEFAULT (0xFF) - -/* Fuse Byte 2 */ -#define FUSE_BODPD0 (unsigned char)~_BV(0) /* BOD Operation in Power-Down Mode Bit 0 */ -#define FUSE_BODPD1 (unsigned char)~_BV(1) /* BOD Operation in Power-Down Mode Bit 1 */ -#define FUSE_TOSCSEL (unsigned char)~_BV(5) /* Timer Oscillator pin location */ -#define FUSE_BOOTRST (unsigned char)~_BV(6) /* Boot Loader Section Reset Vector */ -#define FUSE2_DEFAULT (0xFF) - -/* Fuse Byte 3 Reserved */ - -/* Fuse Byte 4 */ -#define FUSE_JTAGEN (unsigned char)~_BV(0) /* JTAG Interface Enable */ -#define FUSE_WDLOCK (unsigned char)~_BV(1) /* Watchdog Timer Lock */ -#define FUSE_SUT0 (unsigned char)~_BV(2) /* Start-up Time Bit 0 */ -#define FUSE_SUT1 (unsigned char)~_BV(3) /* Start-up Time Bit 1 */ -#define FUSE_RSTDISBL (unsigned char)~_BV(4) /* External Reset Disable */ -#define FUSE4_DEFAULT (0xFF) - -/* Fuse Byte 5 */ -#define FUSE_BODLVL0 (unsigned char)~_BV(0) /* Brownout Detection Voltage Level Bit 0 */ -#define FUSE_BODLVL1 (unsigned char)~_BV(1) /* Brownout Detection Voltage Level Bit 1 */ -#define FUSE_BODLVL2 (unsigned char)~_BV(2) /* Brownout Detection Voltage Level Bit 2 */ -#define FUSE_EESAVE (unsigned char)~_BV(3) /* Preserve EEPROM Through Chip Erase */ -#define FUSE_BODACT0 (unsigned char)~_BV(4) /* BOD Operation in Active Mode Bit 0 */ -#define FUSE_BODACT1 (unsigned char)~_BV(5) /* BOD Operation in Active Mode Bit 1 */ -#define FUSE5_DEFAULT (0xFF) - -/* ========== Lock Bits ========== */ -#define __LOCK_BITS_EXIST -#define __BOOT_LOCK_APPLICATION_TABLE_BITS_EXIST -#define __BOOT_LOCK_APPLICATION_BITS_EXIST -#define __BOOT_LOCK_BOOT_BITS_EXIST - -/* ========== Signature ========== */ -#define SIGNATURE_0 0x1E -#define SIGNATURE_1 0x97 -#define SIGNATURE_2 0x42 - -/* ========== Power Reduction Condition Definitions ========== */ - -/* PR.PRGEN */ -#define __AVR_HAVE_PRGEN (PR_USB_bm|PR_AES_bm|PR_EBI_bm|PR_RTC_bm|PR_EVSYS_bm|PR_DMA_bm) -#define __AVR_HAVE_PRGEN_USB -#define __AVR_HAVE_PRGEN_AES -#define __AVR_HAVE_PRGEN_EBI -#define __AVR_HAVE_PRGEN_RTC -#define __AVR_HAVE_PRGEN_EVSYS -#define __AVR_HAVE_PRGEN_DMA - -/* PR.PRPA */ -#define __AVR_HAVE_PRPA (PR_DAC_bm|PR_ADC_bm|PR_AC_bm) -#define __AVR_HAVE_PRPA_DAC -#define __AVR_HAVE_PRPA_ADC -#define __AVR_HAVE_PRPA_AC - -/* PR.PRPB */ -#define __AVR_HAVE_PRPB (PR_DAC_bm|PR_ADC_bm|PR_AC_bm) -#define __AVR_HAVE_PRPB_DAC -#define __AVR_HAVE_PRPB_ADC -#define __AVR_HAVE_PRPB_AC - -/* PR.PRPC */ -#define __AVR_HAVE_PRPC (PR_TWI_bm|PR_USART1_bm|PR_USART0_bm|PR_SPI_bm|PR_HIRES_bm|PR_TC1_bm|PR_TC0_bm) -#define __AVR_HAVE_PRPC_TWI -#define __AVR_HAVE_PRPC_USART1 -#define __AVR_HAVE_PRPC_USART0 -#define __AVR_HAVE_PRPC_SPI -#define __AVR_HAVE_PRPC_HIRES -#define __AVR_HAVE_PRPC_TC1 -#define __AVR_HAVE_PRPC_TC0 - -/* PR.PRPD */ -#define __AVR_HAVE_PRPD (PR_TWI_bm|PR_USART1_bm|PR_USART0_bm|PR_SPI_bm|PR_HIRES_bm|PR_TC1_bm|PR_TC0_bm) -#define __AVR_HAVE_PRPD_TWI -#define __AVR_HAVE_PRPD_USART1 -#define __AVR_HAVE_PRPD_USART0 -#define __AVR_HAVE_PRPD_SPI -#define __AVR_HAVE_PRPD_HIRES -#define __AVR_HAVE_PRPD_TC1 -#define __AVR_HAVE_PRPD_TC0 - -/* PR.PRPE */ -#define __AVR_HAVE_PRPE (PR_TWI_bm|PR_USART1_bm|PR_USART0_bm|PR_SPI_bm|PR_HIRES_bm|PR_TC1_bm|PR_TC0_bm) -#define __AVR_HAVE_PRPE_TWI -#define __AVR_HAVE_PRPE_USART1 -#define __AVR_HAVE_PRPE_USART0 -#define __AVR_HAVE_PRPE_SPI -#define __AVR_HAVE_PRPE_HIRES -#define __AVR_HAVE_PRPE_TC1 -#define __AVR_HAVE_PRPE_TC0 - -/* PR.PRPF */ -#define __AVR_HAVE_PRPF (PR_TWI_bm|PR_USART1_bm|PR_USART0_bm|PR_SPI_bm|PR_HIRES_bm|PR_TC1_bm|PR_TC0_bm) -#define __AVR_HAVE_PRPF_TWI -#define __AVR_HAVE_PRPF_USART1 -#define __AVR_HAVE_PRPF_USART0 -#define __AVR_HAVE_PRPF_SPI -#define __AVR_HAVE_PRPF_HIRES -#define __AVR_HAVE_PRPF_TC1 -#define __AVR_HAVE_PRPF_TC0 - - -#endif /* #ifdef _AVR_ATXMEGA128A3U_H_INCLUDED */ - diff --git a/arduino/hardware/tools/avr/avr/include/avr/iox128a4u.h b/arduino/hardware/tools/avr/avr/include/avr/iox128a4u.h deleted file mode 100644 index 6365392..0000000 --- a/arduino/hardware/tools/avr/avr/include/avr/iox128a4u.h +++ /dev/null @@ -1,7309 +0,0 @@ -/***************************************************************************** - * - * Copyright (C) 2015 Atmel Corporation - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * - * * Neither the name of the copyright holders nor the names of - * contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - ****************************************************************************/ - - -#ifndef _AVR_IO_H_ -# error "Include instead of this file." -#endif - -#ifndef _AVR_IOXXX_H_ -# define _AVR_IOXXX_H_ "iox128a4u.h" -#else -# error "Attempt to include more than one file." -#endif - -#ifndef _AVR_ATXMEGA128A4U_H_INCLUDED -#define _AVR_ATXMEGA128A4U_H_INCLUDED - -/* Ungrouped common registers */ -#define GPIOR0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ -#define GPIOR1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ -#define GPIOR2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ -#define GPIOR3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ -#define GPIOR4 _SFR_MEM8(0x0004) /* General Purpose IO Register 4 */ -#define GPIOR5 _SFR_MEM8(0x0005) /* General Purpose IO Register 5 */ -#define GPIOR6 _SFR_MEM8(0x0006) /* General Purpose IO Register 6 */ -#define GPIOR7 _SFR_MEM8(0x0007) /* General Purpose IO Register 7 */ -#define GPIOR8 _SFR_MEM8(0x0008) /* General Purpose IO Register 8 */ -#define GPIOR9 _SFR_MEM8(0x0009) /* General Purpose IO Register 9 */ -#define GPIORA _SFR_MEM8(0x000A) /* General Purpose IO Register 10 */ -#define GPIORB _SFR_MEM8(0x000B) /* General Purpose IO Register 11 */ -#define GPIORC _SFR_MEM8(0x000C) /* General Purpose IO Register 12 */ -#define GPIORD _SFR_MEM8(0x000D) /* General Purpose IO Register 13 */ -#define GPIORE _SFR_MEM8(0x000E) /* General Purpose IO Register 14 */ -#define GPIORF _SFR_MEM8(0x000F) /* General Purpose IO Register 15 */ - -/* Deprecated */ -#define GPIO0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ -#define GPIO1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ -#define GPIO2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ -#define GPIO3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ -#define GPIO4 _SFR_MEM8(0x0004) /* General Purpose IO Register 4 */ -#define GPIO5 _SFR_MEM8(0x0005) /* General Purpose IO Register 5 */ -#define GPIO6 _SFR_MEM8(0x0006) /* General Purpose IO Register 6 */ -#define GPIO7 _SFR_MEM8(0x0007) /* General Purpose IO Register 7 */ -#define GPIO8 _SFR_MEM8(0x0008) /* General Purpose IO Register 8 */ -#define GPIO9 _SFR_MEM8(0x0009) /* General Purpose IO Register 9 */ -#define GPIOA _SFR_MEM8(0x000A) /* General Purpose IO Register 10 */ -#define GPIOB _SFR_MEM8(0x000B) /* General Purpose IO Register 11 */ -#define GPIOC _SFR_MEM8(0x000C) /* General Purpose IO Register 12 */ -#define GPIOD _SFR_MEM8(0x000D) /* General Purpose IO Register 13 */ -#define GPIOE _SFR_MEM8(0x000E) /* General Purpose IO Register 14 */ -#define GPIOF _SFR_MEM8(0x000F) /* General Purpose IO Register 15 */ - -#define CCP _SFR_MEM8(0x0034) /* Configuration Change Protection */ -#define RAMPD _SFR_MEM8(0x0038) /* Ramp D */ -#define RAMPX _SFR_MEM8(0x0039) /* Ramp X */ -#define RAMPY _SFR_MEM8(0x003A) /* Ramp Y */ -#define RAMPZ _SFR_MEM8(0x003B) /* Ramp Z */ -#define EIND _SFR_MEM8(0x003C) /* Extended Indirect Jump */ -#define SPL _SFR_MEM8(0x003D) /* Stack Pointer Low */ -#define SPH _SFR_MEM8(0x003E) /* Stack Pointer High */ -#define SREG _SFR_MEM8(0x003F) /* Status Register */ - -/* C Language Only */ -#if !defined (__ASSEMBLER__) - -#include - -typedef volatile uint8_t register8_t; -typedef volatile uint16_t register16_t; -typedef volatile uint32_t register32_t; - - -#ifdef _WORDREGISTER -#undef _WORDREGISTER -#endif -#define _WORDREGISTER(regname) \ - __extension__ union \ - { \ - register16_t regname; \ - struct \ - { \ - register8_t regname ## L; \ - register8_t regname ## H; \ - }; \ - } - -#ifdef _DWORDREGISTER -#undef _DWORDREGISTER -#endif -#define _DWORDREGISTER(regname) \ - __extension__ union \ - { \ - register32_t regname; \ - struct \ - { \ - register8_t regname ## 0; \ - register8_t regname ## 1; \ - register8_t regname ## 2; \ - register8_t regname ## 3; \ - }; \ - } - - -/* -========================================================================== -IO Module Structures -========================================================================== -*/ - - -/* --------------------------------------------------------------------------- -VPORT - Virtual Ports --------------------------------------------------------------------------- -*/ - -/* Virtual Port */ -typedef struct VPORT_struct -{ - register8_t DIR; /* I/O Port Data Direction */ - register8_t OUT; /* I/O Port Output */ - register8_t IN; /* I/O Port Input */ - register8_t INTFLAGS; /* Interrupt Flag Register */ -} VPORT_t; - - -/* --------------------------------------------------------------------------- -XOCD - On-Chip Debug System --------------------------------------------------------------------------- -*/ - -/* On-Chip Debug System */ -typedef struct OCD_struct -{ - register8_t OCDR0; /* OCD Register 0 */ - register8_t OCDR1; /* OCD Register 1 */ -} OCD_t; - - -/* --------------------------------------------------------------------------- -CPU - CPU --------------------------------------------------------------------------- -*/ - -/* CCP signatures */ -typedef enum CCP_enum -{ - CCP_SPM_gc = (0x9D<<0), /* SPM Instruction Protection */ - CCP_IOREG_gc = (0xD8<<0), /* IO Register Protection */ -} CCP_t; - - -/* --------------------------------------------------------------------------- -CLK - Clock System --------------------------------------------------------------------------- -*/ - -/* Clock System */ -typedef struct CLK_struct -{ - register8_t CTRL; /* Control Register */ - register8_t PSCTRL; /* Prescaler Control Register */ - register8_t LOCK; /* Lock register */ - register8_t RTCCTRL; /* RTC Control Register */ - register8_t USBCTRL; /* USB Control Register */ -} CLK_t; - - -/* Power Reduction */ -typedef struct PR_struct -{ - register8_t PRGEN; /* General Power Reduction */ - register8_t PRPA; /* Power Reduction Port A */ - register8_t PRPB; /* Power Reduction Port B */ - register8_t PRPC; /* Power Reduction Port C */ - register8_t PRPD; /* Power Reduction Port D */ - register8_t PRPE; /* Power Reduction Port E */ - register8_t PRPF; /* Power Reduction Port F */ -} PR_t; - -/* System Clock Selection */ -typedef enum CLK_SCLKSEL_enum -{ - CLK_SCLKSEL_RC2M_gc = (0x00<<0), /* Internal 2 MHz RC Oscillator */ - CLK_SCLKSEL_RC32M_gc = (0x01<<0), /* Internal 32 MHz RC Oscillator */ - CLK_SCLKSEL_RC32K_gc = (0x02<<0), /* Internal 32.768 kHz RC Oscillator */ - CLK_SCLKSEL_XOSC_gc = (0x03<<0), /* External Crystal Oscillator or Clock */ - CLK_SCLKSEL_PLL_gc = (0x04<<0), /* Phase Locked Loop */ -} CLK_SCLKSEL_t; - -/* Prescaler A Division Factor */ -typedef enum CLK_PSADIV_enum -{ - CLK_PSADIV_1_gc = (0x00<<2), /* Divide by 1 */ - CLK_PSADIV_2_gc = (0x01<<2), /* Divide by 2 */ - CLK_PSADIV_4_gc = (0x03<<2), /* Divide by 4 */ - CLK_PSADIV_8_gc = (0x05<<2), /* Divide by 8 */ - CLK_PSADIV_16_gc = (0x07<<2), /* Divide by 16 */ - CLK_PSADIV_32_gc = (0x09<<2), /* Divide by 32 */ - CLK_PSADIV_64_gc = (0x0B<<2), /* Divide by 64 */ - CLK_PSADIV_128_gc = (0x0D<<2), /* Divide by 128 */ - CLK_PSADIV_256_gc = (0x0F<<2), /* Divide by 256 */ - CLK_PSADIV_512_gc = (0x11<<2), /* Divide by 512 */ -} CLK_PSADIV_t; - -/* Prescaler B and C Division Factor */ -typedef enum CLK_PSBCDIV_enum -{ - CLK_PSBCDIV_1_1_gc = (0x00<<0), /* Divide B by 1 and C by 1 */ - CLK_PSBCDIV_1_2_gc = (0x01<<0), /* Divide B by 1 and C by 2 */ - CLK_PSBCDIV_4_1_gc = (0x02<<0), /* Divide B by 4 and C by 1 */ - CLK_PSBCDIV_2_2_gc = (0x03<<0), /* Divide B by 2 and C by 2 */ -} CLK_PSBCDIV_t; - -/* RTC Clock Source */ -typedef enum CLK_RTCSRC_enum -{ - CLK_RTCSRC_ULP_gc = (0x00<<1), /* 1.024 kHz from internal 32kHz ULP */ - CLK_RTCSRC_TOSC_gc = (0x01<<1), /* 1.024 kHz from 32.768 kHz crystal oscillator on TOSC */ - CLK_RTCSRC_RCOSC_gc = (0x02<<1), /* 1.024 kHz from internal 32.768 kHz RC oscillator */ - CLK_RTCSRC_TOSC32_gc = (0x05<<1), /* 32.768 kHz from 32.768 kHz crystal oscillator on TOSC */ - CLK_RTCSRC_RCOSC32_gc = (0x06<<1), /* 32.768 kHz from internal 32.768 kHz RC oscillator */ - CLK_RTCSRC_EXTCLK_gc = (0x07<<1), /* External Clock from TOSC1 */ -} CLK_RTCSRC_t; - -/* USB Prescaler Division Factor */ -typedef enum CLK_USBPSDIV_enum -{ - CLK_USBPSDIV_1_gc = (0x00<<3), /* Divide by 1 */ - CLK_USBPSDIV_2_gc = (0x01<<3), /* Divide by 2 */ - CLK_USBPSDIV_4_gc = (0x02<<3), /* Divide by 4 */ - CLK_USBPSDIV_8_gc = (0x03<<3), /* Divide by 8 */ - CLK_USBPSDIV_16_gc = (0x04<<3), /* Divide by 16 */ - CLK_USBPSDIV_32_gc = (0x05<<3), /* Divide by 32 */ -} CLK_USBPSDIV_t; - -/* USB Clock Source */ -typedef enum CLK_USBSRC_enum -{ - CLK_USBSRC_PLL_gc = (0x00<<1), /* PLL */ - CLK_USBSRC_RC32M_gc = (0x01<<1), /* Internal 32 MHz RC Oscillator */ -} CLK_USBSRC_t; - - -/* --------------------------------------------------------------------------- -SLEEP - Sleep Controller --------------------------------------------------------------------------- -*/ - -/* Sleep Controller */ -typedef struct SLEEP_struct -{ - register8_t CTRL; /* Control Register */ -} SLEEP_t; - -/* Sleep Mode */ -typedef enum SLEEP_SMODE_enum -{ - SLEEP_SMODE_IDLE_gc = (0x00<<1), /* Idle mode */ - SLEEP_SMODE_PDOWN_gc = (0x02<<1), /* Power-down Mode */ - SLEEP_SMODE_PSAVE_gc = (0x03<<1), /* Power-save Mode */ - SLEEP_SMODE_STDBY_gc = (0x06<<1), /* Standby Mode */ - SLEEP_SMODE_ESTDBY_gc = (0x07<<1), /* Extended Standby Mode */ -} SLEEP_SMODE_t; - - - -#define SLEEP_MODE_IDLE (0x00<<1) -#define SLEEP_MODE_PWR_DOWN (0x02<<1) -#define SLEEP_MODE_PWR_SAVE (0x03<<1) -#define SLEEP_MODE_STANDBY (0x06<<1) -#define SLEEP_MODE_EXT_STANDBY (0x07<<1) -/* --------------------------------------------------------------------------- -OSC - Oscillator --------------------------------------------------------------------------- -*/ - -/* Oscillator */ -typedef struct OSC_struct -{ - register8_t CTRL; /* Control Register */ - register8_t STATUS; /* Status Register */ - register8_t XOSCCTRL; /* External Oscillator Control Register */ - register8_t XOSCFAIL; /* Oscillator Failure Detection Register */ - register8_t RC32KCAL; /* 32.768 kHz Internal Oscillator Calibration Register */ - register8_t PLLCTRL; /* PLL Control Register */ - register8_t DFLLCTRL; /* DFLL Control Register */ -} OSC_t; - -/* Oscillator Frequency Range */ -typedef enum OSC_FRQRANGE_enum -{ - OSC_FRQRANGE_04TO2_gc = (0x00<<6), /* 0.4 - 2 MHz */ - OSC_FRQRANGE_2TO9_gc = (0x01<<6), /* 2 - 9 MHz */ - OSC_FRQRANGE_9TO12_gc = (0x02<<6), /* 9 - 12 MHz */ - OSC_FRQRANGE_12TO16_gc = (0x03<<6), /* 12 - 16 MHz */ -} OSC_FRQRANGE_t; - -/* External Oscillator Selection and Startup Time */ -typedef enum OSC_XOSCSEL_enum -{ - OSC_XOSCSEL_EXTCLK_gc = (0x00<<0), /* External Clock - 6 CLK */ - OSC_XOSCSEL_32KHz_gc = (0x02<<0), /* 32.768 kHz TOSC - 32K CLK */ - OSC_XOSCSEL_XTAL_256CLK_gc = (0x03<<0), /* 0.4-16 MHz XTAL - 256 CLK */ - OSC_XOSCSEL_XTAL_1KCLK_gc = (0x07<<0), /* 0.4-16 MHz XTAL - 1K CLK */ - OSC_XOSCSEL_XTAL_16KCLK_gc = (0x0B<<0), /* 0.4-16 MHz XTAL - 16K CLK */ -} OSC_XOSCSEL_t; - -/* PLL Clock Source */ -typedef enum OSC_PLLSRC_enum -{ - OSC_PLLSRC_RC2M_gc = (0x00<<6), /* Internal 2 MHz RC Oscillator */ - OSC_PLLSRC_RC32M_gc = (0x02<<6), /* Internal 32 MHz RC Oscillator */ - OSC_PLLSRC_XOSC_gc = (0x03<<6), /* External Oscillator */ -} OSC_PLLSRC_t; - -/* 2 MHz DFLL Calibration Reference */ -typedef enum OSC_RC2MCREF_enum -{ - OSC_RC2MCREF_RC32K_gc = (0x00<<0), /* Internal 32.768 kHz RC Oscillator */ - OSC_RC2MCREF_XOSC32K_gc = (0x01<<0), /* External 32.768 kHz Crystal Oscillator */ -} OSC_RC2MCREF_t; - -/* 32 MHz DFLL Calibration Reference */ -typedef enum OSC_RC32MCREF_enum -{ - OSC_RC32MCREF_RC32K_gc = (0x00<<1), /* Internal 32.768 kHz RC Oscillator */ - OSC_RC32MCREF_XOSC32K_gc = (0x01<<1), /* External 32.768 kHz Crystal Oscillator */ - OSC_RC32MCREF_USBSOF_gc = (0x02<<1), /* USB Start of Frame */ -} OSC_RC32MCREF_t; - - -/* --------------------------------------------------------------------------- -DFLL - DFLL --------------------------------------------------------------------------- -*/ - -/* DFLL */ -typedef struct DFLL_struct -{ - register8_t CTRL; /* Control Register */ - register8_t reserved_0x01; - register8_t CALA; /* Calibration Register A */ - register8_t CALB; /* Calibration Register B */ - register8_t COMP0; /* Oscillator Compare Register 0 */ - register8_t COMP1; /* Oscillator Compare Register 1 */ - register8_t COMP2; /* Oscillator Compare Register 2 */ - register8_t reserved_0x07; -} DFLL_t; - - -/* --------------------------------------------------------------------------- -RST - Reset --------------------------------------------------------------------------- -*/ - -/* Reset */ -typedef struct RST_struct -{ - register8_t STATUS; /* Status Register */ - register8_t CTRL; /* Control Register */ -} RST_t; - - -/* --------------------------------------------------------------------------- -WDT - Watch-Dog Timer --------------------------------------------------------------------------- -*/ - -/* Watch-Dog Timer */ -typedef struct WDT_struct -{ - register8_t CTRL; /* Control */ - register8_t WINCTRL; /* Windowed Mode Control */ - register8_t STATUS; /* Status */ -} WDT_t; - -/* Period setting */ -typedef enum WDT_PER_enum -{ - WDT_PER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ - WDT_PER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ - WDT_PER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ - WDT_PER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ - WDT_PER_128CLK_gc = (0x04<<2), /* 128 cycles (0.128s @ 3.3V) */ - WDT_PER_256CLK_gc = (0x05<<2), /* 256 cycles (0.256s @ 3.3V) */ - WDT_PER_512CLK_gc = (0x06<<2), /* 512 cycles (0.512s @ 3.3V) */ - WDT_PER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ - WDT_PER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ - WDT_PER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ - WDT_PER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ -} WDT_PER_t; - -/* Closed window period */ -typedef enum WDT_WPER_enum -{ - WDT_WPER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ - WDT_WPER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ - WDT_WPER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ - WDT_WPER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ - WDT_WPER_128CLK_gc = (0x04<<2), /* 128 cycles (0.128s @ 3.3V) */ - WDT_WPER_256CLK_gc = (0x05<<2), /* 256 cycles (0.256s @ 3.3V) */ - WDT_WPER_512CLK_gc = (0x06<<2), /* 512 cycles (0.512s @ 3.3V) */ - WDT_WPER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ - WDT_WPER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ - WDT_WPER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ - WDT_WPER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ -} WDT_WPER_t; - - -/* --------------------------------------------------------------------------- -MCU - MCU Control --------------------------------------------------------------------------- -*/ - -/* MCU Control */ -typedef struct MCU_struct -{ - register8_t DEVID0; /* Device ID byte 0 */ - register8_t DEVID1; /* Device ID byte 1 */ - register8_t DEVID2; /* Device ID byte 2 */ - register8_t REVID; /* Revision ID */ - register8_t JTAGUID; /* JTAG User ID */ - register8_t reserved_0x05; - register8_t MCUCR; /* MCU Control */ - register8_t ANAINIT; /* Analog Startup Delay */ - register8_t EVSYSLOCK; /* Event System Lock */ - register8_t AWEXLOCK; /* AWEX Lock */ - register8_t reserved_0x0A; - register8_t reserved_0x0B; -} MCU_t; - - -/* --------------------------------------------------------------------------- -PMIC - Programmable Multi-level Interrupt Controller --------------------------------------------------------------------------- -*/ - -/* Programmable Multi-level Interrupt Controller */ -typedef struct PMIC_struct -{ - register8_t STATUS; /* Status Register */ - register8_t INTPRI; /* Interrupt Priority */ - register8_t CTRL; /* Control Register */ - register8_t reserved_0x03; - register8_t reserved_0x04; - register8_t reserved_0x05; - register8_t reserved_0x06; - register8_t reserved_0x07; - register8_t reserved_0x08; - register8_t reserved_0x09; - register8_t reserved_0x0A; - register8_t reserved_0x0B; - register8_t reserved_0x0C; - register8_t reserved_0x0D; - register8_t reserved_0x0E; - register8_t reserved_0x0F; -} PMIC_t; - - -/* --------------------------------------------------------------------------- -PORTCFG - Port Configuration --------------------------------------------------------------------------- -*/ - -/* I/O port Configuration */ -typedef struct PORTCFG_struct -{ - register8_t MPCMASK; /* Multi-pin Configuration Mask */ - register8_t reserved_0x01; - register8_t VPCTRLA; /* Virtual Port Control Register A */ - register8_t VPCTRLB; /* Virtual Port Control Register B */ - register8_t CLKEVOUT; /* Clock and Event Out Register */ - register8_t EBIOUT; /* EBI Output register */ - register8_t EVOUTSEL; /* Event Output Select */ -} PORTCFG_t; - -/* Virtual Port Mapping */ -typedef enum PORTCFG_VP02MAP_enum -{ - PORTCFG_VP02MAP_PORTA_gc = (0x00<<0), /* Mapped To PORTA */ - PORTCFG_VP02MAP_PORTB_gc = (0x01<<0), /* Mapped To PORTB */ - PORTCFG_VP02MAP_PORTC_gc = (0x02<<0), /* Mapped To PORTC */ - PORTCFG_VP02MAP_PORTD_gc = (0x03<<0), /* Mapped To PORTD */ - PORTCFG_VP02MAP_PORTE_gc = (0x04<<0), /* Mapped To PORTE */ - PORTCFG_VP02MAP_PORTF_gc = (0x05<<0), /* Mapped To PORTF */ - PORTCFG_VP02MAP_PORTG_gc = (0x06<<0), /* Mapped To PORTG */ - PORTCFG_VP02MAP_PORTH_gc = (0x07<<0), /* Mapped To PORTH */ - PORTCFG_VP02MAP_PORTJ_gc = (0x08<<0), /* Mapped To PORTJ */ - PORTCFG_VP02MAP_PORTK_gc = (0x09<<0), /* Mapped To PORTK */ - PORTCFG_VP02MAP_PORTL_gc = (0x0A<<0), /* Mapped To PORTL */ - PORTCFG_VP02MAP_PORTM_gc = (0x0B<<0), /* Mapped To PORTM */ - PORTCFG_VP02MAP_PORTN_gc = (0x0C<<0), /* Mapped To PORTN */ - PORTCFG_VP02MAP_PORTP_gc = (0x0D<<0), /* Mapped To PORTP */ - PORTCFG_VP02MAP_PORTQ_gc = (0x0E<<0), /* Mapped To PORTQ */ - PORTCFG_VP02MAP_PORTR_gc = (0x0F<<0), /* Mapped To PORTR */ -} PORTCFG_VP02MAP_t; - -/* Virtual Port Mapping */ -typedef enum PORTCFG_VP13MAP_enum -{ - PORTCFG_VP13MAP_PORTA_gc = (0x00<<4), /* Mapped To PORTA */ - PORTCFG_VP13MAP_PORTB_gc = (0x01<<4), /* Mapped To PORTB */ - PORTCFG_VP13MAP_PORTC_gc = (0x02<<4), /* Mapped To PORTC */ - PORTCFG_VP13MAP_PORTD_gc = (0x03<<4), /* Mapped To PORTD */ - PORTCFG_VP13MAP_PORTE_gc = (0x04<<4), /* Mapped To PORTE */ - PORTCFG_VP13MAP_PORTF_gc = (0x05<<4), /* Mapped To PORTF */ - PORTCFG_VP13MAP_PORTG_gc = (0x06<<4), /* Mapped To PORTG */ - PORTCFG_VP13MAP_PORTH_gc = (0x07<<4), /* Mapped To PORTH */ - PORTCFG_VP13MAP_PORTJ_gc = (0x08<<4), /* Mapped To PORTJ */ - PORTCFG_VP13MAP_PORTK_gc = (0x09<<4), /* Mapped To PORTK */ - PORTCFG_VP13MAP_PORTL_gc = (0x0A<<4), /* Mapped To PORTL */ - PORTCFG_VP13MAP_PORTM_gc = (0x0B<<4), /* Mapped To PORTM */ - PORTCFG_VP13MAP_PORTN_gc = (0x0C<<4), /* Mapped To PORTN */ - PORTCFG_VP13MAP_PORTP_gc = (0x0D<<4), /* Mapped To PORTP */ - PORTCFG_VP13MAP_PORTQ_gc = (0x0E<<4), /* Mapped To PORTQ */ - PORTCFG_VP13MAP_PORTR_gc = (0x0F<<4), /* Mapped To PORTR */ -} PORTCFG_VP13MAP_t; - -/* System Clock Output Port */ -typedef enum PORTCFG_CLKOUT_enum -{ - PORTCFG_CLKOUT_OFF_gc = (0x00<<0), /* System Clock Output Disabled */ - PORTCFG_CLKOUT_PC7_gc = (0x01<<0), /* System Clock Output on Port C pin 7 */ - PORTCFG_CLKOUT_PD7_gc = (0x02<<0), /* System Clock Output on Port D pin 7 */ - PORTCFG_CLKOUT_PE7_gc = (0x03<<0), /* System Clock Output on Port E pin 7 */ -} PORTCFG_CLKOUT_t; - -/* Peripheral Clock Output Select */ -typedef enum PORTCFG_CLKOUTSEL_enum -{ - PORTCFG_CLKOUTSEL_CLK1X_gc = (0x00<<2), /* 1x Peripheral Clock Output to pin */ - PORTCFG_CLKOUTSEL_CLK2X_gc = (0x01<<2), /* 2x Peripheral Clock Output to pin */ - PORTCFG_CLKOUTSEL_CLK4X_gc = (0x02<<2), /* 4x Peripheral Clock Output to pin */ -} PORTCFG_CLKOUTSEL_t; - -/* Event Output Port */ -typedef enum PORTCFG_EVOUT_enum -{ - PORTCFG_EVOUT_OFF_gc = (0x00<<4), /* Event Output Disabled */ - PORTCFG_EVOUT_PC7_gc = (0x01<<4), /* Event Channel 7 Output on Port C pin 7 */ - PORTCFG_EVOUT_PD7_gc = (0x02<<4), /* Event Channel 7 Output on Port D pin 7 */ - PORTCFG_EVOUT_PE7_gc = (0x03<<4), /* Event Channel 7 Output on Port E pin 7 */ -} PORTCFG_EVOUT_t; - -/* Clock and Event Output Port */ -typedef enum PORTCFG_CLKEVPIN_enum -{ - PORTCFG_CLKEVPIN_PIN7_gc = (0x00<<7), /* Clock and Event Ouput on PIN 7 */ - PORTCFG_CLKEVPIN_PIN4_gc = (0x01<<7), /* Clock and Event Ouput on PIN 4 */ -} PORTCFG_CLKEVPIN_t; - -/* EBI Address Output Port */ -typedef enum PORTCFG_EBIADROUT_enum -{ - PORTCFG_EBIADROUT_PF_gc = (0x00<<2), /* EBI port 3 address output on PORTF pins 0 to 7 */ - PORTCFG_EBIADROUT_PE_gc = (0x01<<2), /* EBI port 3 address output on PORTE pins 0 to 7 */ - PORTCFG_EBIADROUT_PFH_gc = (0x02<<2), /* EBI port 3 address output on PORTF pins 4 to 7 */ - PORTCFG_EBIADROUT_PEH_gc = (0x03<<2), /* EBI port 3 address output on PORTE pins 4 to 7 */ -} PORTCFG_EBIADROUT_t; - -/* EBI Chip Select Output Port */ -typedef enum PORTCFG_EBICSOUT_enum -{ - PORTCFG_EBICSOUT_PH_gc = (0x00<<0), /* EBI chip select output to PORTH pin 4 to 7 */ - PORTCFG_EBICSOUT_PL_gc = (0x01<<0), /* EBI chip select output to PORTL pin 4 to 7 */ - PORTCFG_EBICSOUT_PF_gc = (0x02<<0), /* EBI chip select output to PORTF pin 4 to 7 */ - PORTCFG_EBICSOUT_PE_gc = (0x03<<0), /* EBI chip select output to PORTE pin 4 to 7 */ -} PORTCFG_EBICSOUT_t; - -/* Event Output Select */ -typedef enum PORTCFG_EVOUTSEL_enum -{ - PORTCFG_EVOUTSEL_0_gc = (0x00<<0), /* Event Channel 0 output to pin */ - PORTCFG_EVOUTSEL_1_gc = (0x01<<0), /* Event Channel 1 output to pin */ - PORTCFG_EVOUTSEL_2_gc = (0x02<<0), /* Event Channel 2 output to pin */ - PORTCFG_EVOUTSEL_3_gc = (0x03<<0), /* Event Channel 3 output to pin */ - PORTCFG_EVOUTSEL_4_gc = (0x04<<0), /* Event Channel 4 output to pin */ - PORTCFG_EVOUTSEL_5_gc = (0x05<<0), /* Event Channel 5 output to pin */ - PORTCFG_EVOUTSEL_6_gc = (0x06<<0), /* Event Channel 6 output to pin */ - PORTCFG_EVOUTSEL_7_gc = (0x07<<0), /* Event Channel 7 output to pin */ -} PORTCFG_EVOUTSEL_t; - - -/* --------------------------------------------------------------------------- -AES - AES Module --------------------------------------------------------------------------- -*/ - -/* AES Module */ -typedef struct AES_struct -{ - register8_t CTRL; /* AES Control Register */ - register8_t STATUS; /* AES Status Register */ - register8_t STATE; /* AES State Register */ - register8_t KEY; /* AES Key Register */ - register8_t INTCTRL; /* AES Interrupt Control Register */ -} AES_t; - -/* Interrupt level */ -typedef enum AES_INTLVL_enum -{ - AES_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - AES_INTLVL_LO_gc = (0x01<<0), /* Low Level */ - AES_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ - AES_INTLVL_HI_gc = (0x03<<0), /* High Level */ -} AES_INTLVL_t; - - -/* --------------------------------------------------------------------------- -CRC - Cyclic Redundancy Checker --------------------------------------------------------------------------- -*/ - -/* Cyclic Redundancy Checker */ -typedef struct CRC_struct -{ - register8_t CTRL; /* Control Register */ - register8_t STATUS; /* Status Register */ - register8_t reserved_0x02; - register8_t DATAIN; /* Data Input */ - register8_t CHECKSUM0; /* Checksum byte 0 */ - register8_t CHECKSUM1; /* Checksum byte 1 */ - register8_t CHECKSUM2; /* Checksum byte 2 */ - register8_t CHECKSUM3; /* Checksum byte 3 */ -} CRC_t; - -/* Reset */ -typedef enum CRC_RESET_enum -{ - CRC_RESET_NO_gc = (0x00<<6), /* No Reset */ - CRC_RESET_RESET0_gc = (0x02<<6), /* Reset CRC with CHECKSUM to all zeros */ - CRC_RESET_RESET1_gc = (0x03<<6), /* Reset CRC with CHECKSUM to all ones */ -} CRC_RESET_t; - -/* Input Source */ -typedef enum CRC_SOURCE_enum -{ - CRC_SOURCE_DISABLE_gc = (0x00<<0), /* Disabled */ - CRC_SOURCE_IO_gc = (0x01<<0), /* I/O Interface */ - CRC_SOURCE_FLASH_gc = (0x02<<0), /* Flash */ - CRC_SOURCE_DMAC0_gc = (0x04<<0), /* DMAC Channel 0 */ - CRC_SOURCE_DMAC1_gc = (0x05<<0), /* DMAC Channel 1 */ - CRC_SOURCE_DMAC2_gc = (0x06<<0), /* DMAC Channel 2 */ - CRC_SOURCE_DMAC3_gc = (0x07<<0), /* DMAC Channel 3 */ -} CRC_SOURCE_t; - - -/* --------------------------------------------------------------------------- -DMA - DMA Controller --------------------------------------------------------------------------- -*/ - -/* DMA Channel */ -typedef struct DMA_CH_struct -{ - register8_t CTRLA; /* Channel Control */ - register8_t CTRLB; /* Channel Control */ - register8_t ADDRCTRL; /* Address Control */ - register8_t TRIGSRC; /* Channel Trigger Source */ - _WORDREGISTER(TRFCNT); /* Channel Block Transfer Count */ - register8_t REPCNT; /* Channel Repeat Count */ - register8_t reserved_0x07; - register8_t SRCADDR0; /* Channel Source Address 0 */ - register8_t SRCADDR1; /* Channel Source Address 1 */ - register8_t SRCADDR2; /* Channel Source Address 2 */ - register8_t reserved_0x0B; - register8_t DESTADDR0; /* Channel Destination Address 0 */ - register8_t DESTADDR1; /* Channel Destination Address 1 */ - register8_t DESTADDR2; /* Channel Destination Address 2 */ - register8_t reserved_0x0F; -} DMA_CH_t; - - -/* DMA Controller */ -typedef struct DMA_struct -{ - register8_t CTRL; /* Control */ - register8_t reserved_0x01; - register8_t reserved_0x02; - register8_t INTFLAGS; /* Transfer Interrupt Status */ - register8_t STATUS; /* Status */ - register8_t reserved_0x05; - _WORDREGISTER(TEMP); /* Temporary Register For 16/24-bit Access */ - register8_t reserved_0x08; - register8_t reserved_0x09; - register8_t reserved_0x0A; - register8_t reserved_0x0B; - register8_t reserved_0x0C; - register8_t reserved_0x0D; - register8_t reserved_0x0E; - register8_t reserved_0x0F; - DMA_CH_t CH0; /* DMA Channel 0 */ - DMA_CH_t CH1; /* DMA Channel 1 */ - DMA_CH_t CH2; /* DMA Channel 2 */ - DMA_CH_t CH3; /* DMA Channel 3 */ -} DMA_t; - -/* Burst mode */ -typedef enum DMA_CH_BURSTLEN_enum -{ - DMA_CH_BURSTLEN_1BYTE_gc = (0x00<<0), /* 1-byte burst mode */ - DMA_CH_BURSTLEN_2BYTE_gc = (0x01<<0), /* 2-byte burst mode */ - DMA_CH_BURSTLEN_4BYTE_gc = (0x02<<0), /* 4-byte burst mode */ - DMA_CH_BURSTLEN_8BYTE_gc = (0x03<<0), /* 8-byte burst mode */ -} DMA_CH_BURSTLEN_t; - -/* Source address reload mode */ -typedef enum DMA_CH_SRCRELOAD_enum -{ - DMA_CH_SRCRELOAD_NONE_gc = (0x00<<6), /* No reload */ - DMA_CH_SRCRELOAD_BLOCK_gc = (0x01<<6), /* Reload at end of block */ - DMA_CH_SRCRELOAD_BURST_gc = (0x02<<6), /* Reload at end of burst */ - DMA_CH_SRCRELOAD_TRANSACTION_gc = (0x03<<6), /* Reload at end of transaction */ -} DMA_CH_SRCRELOAD_t; - -/* Source addressing mode */ -typedef enum DMA_CH_SRCDIR_enum -{ - DMA_CH_SRCDIR_FIXED_gc = (0x00<<4), /* Fixed */ - DMA_CH_SRCDIR_INC_gc = (0x01<<4), /* Increment */ - DMA_CH_SRCDIR_DEC_gc = (0x02<<4), /* Decrement */ -} DMA_CH_SRCDIR_t; - -/* Destination adress reload mode */ -typedef enum DMA_CH_DESTRELOAD_enum -{ - DMA_CH_DESTRELOAD_NONE_gc = (0x00<<2), /* No reload */ - DMA_CH_DESTRELOAD_BLOCK_gc = (0x01<<2), /* Reload at end of block */ - DMA_CH_DESTRELOAD_BURST_gc = (0x02<<2), /* Reload at end of burst */ - DMA_CH_DESTRELOAD_TRANSACTION_gc = (0x03<<2), /* Reload at end of transaction */ -} DMA_CH_DESTRELOAD_t; - -/* Destination adressing mode */ -typedef enum DMA_CH_DESTDIR_enum -{ - DMA_CH_DESTDIR_FIXED_gc = (0x00<<0), /* Fixed */ - DMA_CH_DESTDIR_INC_gc = (0x01<<0), /* Increment */ - DMA_CH_DESTDIR_DEC_gc = (0x02<<0), /* Decrement */ -} DMA_CH_DESTDIR_t; - -/* Transfer trigger source */ -typedef enum DMA_CH_TRIGSRC_enum -{ - DMA_CH_TRIGSRC_OFF_gc = (0x00<<0), /* Off software triggers only */ - DMA_CH_TRIGSRC_EVSYS_CH0_gc = (0x01<<0), /* Event System Channel 0 */ - DMA_CH_TRIGSRC_EVSYS_CH1_gc = (0x02<<0), /* Event System Channel 1 */ - DMA_CH_TRIGSRC_EVSYS_CH2_gc = (0x03<<0), /* Event System Channel 2 */ - DMA_CH_TRIGSRC_ADCA_CH0_gc = (0x10<<0), /* ADCA Channel 0 */ - DMA_CH_TRIGSRC_ADCA_CH1_gc = (0x11<<0), /* ADCA Channel 1 */ - DMA_CH_TRIGSRC_ADCA_CH2_gc = (0x12<<0), /* ADCA Channel 2 */ - DMA_CH_TRIGSRC_ADCA_CH3_gc = (0x13<<0), /* ADCA Channel 3 */ - DMA_CH_TRIGSRC_ADCA_CH4_gc = (0x14<<0), /* ADCA Channel 0,1,2,3 combined */ - DMA_CH_TRIGSRC_DACA_CH0_gc = (0x15<<0), /* DACA Channel 0 */ - DMA_CH_TRIGSRC_DACA_CH1_gc = (0x16<<0), /* DACA Channel 1 */ - DMA_CH_TRIGSRC_ADCB_CH0_gc = (0x20<<0), /* ADCB Channel 0 */ - DMA_CH_TRIGSRC_ADCB_CH1_gc = (0x21<<0), /* ADCB Channel 1 */ - DMA_CH_TRIGSRC_ADCB_CH2_gc = (0x22<<0), /* ADCB Channel 2 */ - DMA_CH_TRIGSRC_ADCB_CH3_gc = (0x23<<0), /* ADCB Channel 3 */ - DMA_CH_TRIGSRC_ADCB_CH4_gc = (0x24<<0), /* ADCB Channel 0,1,2,3 combined */ - DMA_CH_TRIGSRC_DACB_CH0_gc = (0x25<<0), /* DACB Channel 0 */ - DMA_CH_TRIGSRC_DACB_CH1_gc = (0x26<<0), /* DACB Channel 1 */ - DMA_CH_TRIGSRC_TCC0_OVF_gc = (0x40<<0), /* Timer/Counter C0 Overflow */ - DMA_CH_TRIGSRC_TCC0_ERR_gc = (0x41<<0), /* Timer/Counter C0 Error */ - DMA_CH_TRIGSRC_TCC0_CCA_gc = (0x42<<0), /* Timer/Counter C0 Compare or Capture A */ - DMA_CH_TRIGSRC_TCC0_CCB_gc = (0x43<<0), /* Timer/Counter C0 Compare or Capture B */ - DMA_CH_TRIGSRC_TCC0_CCC_gc = (0x44<<0), /* Timer/Counter C0 Compare or Capture C */ - DMA_CH_TRIGSRC_TCC0_CCD_gc = (0x45<<0), /* Timer/Counter C0 Compare or Capture D */ - DMA_CH_TRIGSRC_TCC1_OVF_gc = (0x46<<0), /* Timer/Counter C1 Overflow */ - DMA_CH_TRIGSRC_TCC1_ERR_gc = (0x47<<0), /* Timer/Counter C1 Error */ - DMA_CH_TRIGSRC_TCC1_CCA_gc = (0x48<<0), /* Timer/Counter C1 Compare or Capture A */ - DMA_CH_TRIGSRC_TCC1_CCB_gc = (0x49<<0), /* Timer/Counter C1 Compare or Capture B */ - DMA_CH_TRIGSRC_SPIC_gc = (0x4A<<0), /* SPI C Transfer Complete */ - DMA_CH_TRIGSRC_USARTC0_RXC_gc = (0x4B<<0), /* USART C0 Receive Complete */ - DMA_CH_TRIGSRC_USARTC0_DRE_gc = (0x4C<<0), /* USART C0 Data Register Empty */ - DMA_CH_TRIGSRC_USARTC1_RXC_gc = (0x4E<<0), /* USART C1 Receive Complete */ - DMA_CH_TRIGSRC_USARTC1_DRE_gc = (0x4F<<0), /* USART C1 Data Register Empty */ - DMA_CH_TRIGSRC_TCD0_OVF_gc = (0x60<<0), /* Timer/Counter D0 Overflow */ - DMA_CH_TRIGSRC_TCD0_ERR_gc = (0x61<<0), /* Timer/Counter D0 Error */ - DMA_CH_TRIGSRC_TCD0_CCA_gc = (0x62<<0), /* Timer/Counter D0 Compare or Capture A */ - DMA_CH_TRIGSRC_TCD0_CCB_gc = (0x63<<0), /* Timer/Counter D0 Compare or Capture B */ - DMA_CH_TRIGSRC_TCD0_CCC_gc = (0x64<<0), /* Timer/Counter D0 Compare or Capture C */ - DMA_CH_TRIGSRC_TCD0_CCD_gc = (0x65<<0), /* Timer/Counter D0 Compare or Capture D */ - DMA_CH_TRIGSRC_TCD1_OVF_gc = (0x66<<0), /* Timer/Counter D1 Overflow */ - DMA_CH_TRIGSRC_TCD1_ERR_gc = (0x67<<0), /* Timer/Counter D1 Error */ - DMA_CH_TRIGSRC_TCD1_CCA_gc = (0x68<<0), /* Timer/Counter D1 Compare or Capture A */ - DMA_CH_TRIGSRC_TCD1_CCB_gc = (0x69<<0), /* Timer/Counter D1 Compare or Capture B */ - DMA_CH_TRIGSRC_SPID_gc = (0x6A<<0), /* SPI D Transfer Complete */ - DMA_CH_TRIGSRC_USARTD0_RXC_gc = (0x6B<<0), /* USART D0 Receive Complete */ - DMA_CH_TRIGSRC_USARTD0_DRE_gc = (0x6C<<0), /* USART D0 Data Register Empty */ - DMA_CH_TRIGSRC_USARTD1_RXC_gc = (0x6E<<0), /* USART D1 Receive Complete */ - DMA_CH_TRIGSRC_USARTD1_DRE_gc = (0x6F<<0), /* USART D1 Data Register Empty */ - DMA_CH_TRIGSRC_TCE0_OVF_gc = (0x80<<0), /* Timer/Counter E0 Overflow */ - DMA_CH_TRIGSRC_TCE0_ERR_gc = (0x81<<0), /* Timer/Counter E0 Error */ - DMA_CH_TRIGSRC_TCE0_CCA_gc = (0x82<<0), /* Timer/Counter E0 Compare or Capture A */ - DMA_CH_TRIGSRC_TCE0_CCB_gc = (0x83<<0), /* Timer/Counter E0 Compare or Capture B */ - DMA_CH_TRIGSRC_TCE0_CCC_gc = (0x84<<0), /* Timer/Counter E0 Compare or Capture C */ - DMA_CH_TRIGSRC_TCE0_CCD_gc = (0x85<<0), /* Timer/Counter E0 Compare or Capture D */ - DMA_CH_TRIGSRC_TCE1_OVF_gc = (0x86<<0), /* Timer/Counter E1 Overflow */ - DMA_CH_TRIGSRC_TCE1_ERR_gc = (0x87<<0), /* Timer/Counter E1 Error */ - DMA_CH_TRIGSRC_TCE1_CCA_gc = (0x88<<0), /* Timer/Counter E1 Compare or Capture A */ - DMA_CH_TRIGSRC_TCE1_CCB_gc = (0x89<<0), /* Timer/Counter E1 Compare or Capture B */ - DMA_CH_TRIGSRC_SPIE_gc = (0x8A<<0), /* SPI E Transfer Complete */ - DMA_CH_TRIGSRC_USARTE0_RXC_gc = (0x8B<<0), /* USART E0 Receive Complete */ - DMA_CH_TRIGSRC_USARTE0_DRE_gc = (0x8C<<0), /* USART E0 Data Register Empty */ - DMA_CH_TRIGSRC_USARTE1_RXC_gc = (0x8E<<0), /* USART E1 Receive Complete */ - DMA_CH_TRIGSRC_USARTE1_DRE_gc = (0x8F<<0), /* USART E1 Data Register Empty */ - DMA_CH_TRIGSRC_TCF0_OVF_gc = (0xA0<<0), /* Timer/Counter F0 Overflow */ - DMA_CH_TRIGSRC_TCF0_ERR_gc = (0xA1<<0), /* Timer/Counter F0 Error */ - DMA_CH_TRIGSRC_TCF0_CCA_gc = (0xA2<<0), /* Timer/Counter F0 Compare or Capture A */ - DMA_CH_TRIGSRC_TCF0_CCB_gc = (0xA3<<0), /* Timer/Counter F0 Compare or Capture B */ - DMA_CH_TRIGSRC_TCF0_CCC_gc = (0xA4<<0), /* Timer/Counter F0 Compare or Capture C */ - DMA_CH_TRIGSRC_TCF0_CCD_gc = (0xA5<<0), /* Timer/Counter F0 Compare or Capture D */ - DMA_CH_TRIGSRC_TCF1_OVF_gc = (0xA6<<0), /* Timer/Counter F1 Overflow */ - DMA_CH_TRIGSRC_TCF1_ERR_gc = (0xA7<<0), /* Timer/Counter F1 Error */ - DMA_CH_TRIGSRC_TCF1_CCA_gc = (0xA8<<0), /* Timer/Counter F1 Compare or Capture A */ - DMA_CH_TRIGSRC_TCF1_CCB_gc = (0xA9<<0), /* Timer/Counter F1 Compare or Capture B */ - DMA_CH_TRIGSRC_SPIF_gc = (0xAA<<0), /* SPI F Transfer Complete */ - DMA_CH_TRIGSRC_USARTF0_RXC_gc = (0xAB<<0), /* USART F0 Receive Complete */ - DMA_CH_TRIGSRC_USARTF0_DRE_gc = (0xAC<<0), /* USART F0 Data Register Empty */ - DMA_CH_TRIGSRC_USARTF1_RXC_gc = (0xAE<<0), /* USART F1 Receive Complete */ - DMA_CH_TRIGSRC_USARTF1_DRE_gc = (0xAF<<0), /* USART F1 Data Register Empty */ -} DMA_CH_TRIGSRC_t; - -/* Double buffering mode */ -typedef enum DMA_DBUFMODE_enum -{ - DMA_DBUFMODE_DISABLED_gc = (0x00<<2), /* Double buffering disabled */ - DMA_DBUFMODE_CH01_gc = (0x01<<2), /* Double buffering enabled on channel 0/1 */ - DMA_DBUFMODE_CH23_gc = (0x02<<2), /* Double buffering enabled on channel 2/3 */ - DMA_DBUFMODE_CH01CH23_gc = (0x03<<2), /* Double buffering enabled on ch. 0/1 and ch. 2/3 */ -} DMA_DBUFMODE_t; - -/* Priority mode */ -typedef enum DMA_PRIMODE_enum -{ - DMA_PRIMODE_RR0123_gc = (0x00<<0), /* Round Robin */ - DMA_PRIMODE_CH0RR123_gc = (0x01<<0), /* Channel 0 > Round Robin on channel 1/2/3 */ - DMA_PRIMODE_CH01RR23_gc = (0x02<<0), /* Channel 0 > channel 1 > Round Robin on channel 2/3 */ - DMA_PRIMODE_CH0123_gc = (0x03<<0), /* Channel 0 > channel 1 > channel 2 > channel 3 */ -} DMA_PRIMODE_t; - -/* Interrupt level */ -typedef enum DMA_CH_ERRINTLVL_enum -{ - DMA_CH_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ - DMA_CH_ERRINTLVL_LO_gc = (0x01<<2), /* Low level */ - DMA_CH_ERRINTLVL_MED_gc = (0x02<<2), /* Medium level */ - DMA_CH_ERRINTLVL_HI_gc = (0x03<<2), /* High level */ -} DMA_CH_ERRINTLVL_t; - -/* Interrupt level */ -typedef enum DMA_CH_TRNINTLVL_enum -{ - DMA_CH_TRNINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ - DMA_CH_TRNINTLVL_LO_gc = (0x01<<0), /* Low level */ - DMA_CH_TRNINTLVL_MED_gc = (0x02<<0), /* Medium level */ - DMA_CH_TRNINTLVL_HI_gc = (0x03<<0), /* High level */ -} DMA_CH_TRNINTLVL_t; - - -/* --------------------------------------------------------------------------- -EVSYS - Event System --------------------------------------------------------------------------- -*/ - -/* Event System */ -typedef struct EVSYS_struct -{ - register8_t CH0MUX; /* Event Channel 0 Multiplexer */ - register8_t CH1MUX; /* Event Channel 1 Multiplexer */ - register8_t CH2MUX; /* Event Channel 2 Multiplexer */ - register8_t CH3MUX; /* Event Channel 3 Multiplexer */ - register8_t CH4MUX; /* Event Channel 4 Multiplexer */ - register8_t CH5MUX; /* Event Channel 5 Multiplexer */ - register8_t CH6MUX; /* Event Channel 6 Multiplexer */ - register8_t CH7MUX; /* Event Channel 7 Multiplexer */ - register8_t CH0CTRL; /* Channel 0 Control Register */ - register8_t CH1CTRL; /* Channel 1 Control Register */ - register8_t CH2CTRL; /* Channel 2 Control Register */ - register8_t CH3CTRL; /* Channel 3 Control Register */ - register8_t CH4CTRL; /* Channel 4 Control Register */ - register8_t CH5CTRL; /* Channel 5 Control Register */ - register8_t CH6CTRL; /* Channel 6 Control Register */ - register8_t CH7CTRL; /* Channel 7 Control Register */ - register8_t STROBE; /* Event Strobe */ - register8_t DATA; /* Event Data */ -} EVSYS_t; - -/* Quadrature Decoder Index Recognition Mode */ -typedef enum EVSYS_QDIRM_enum -{ - EVSYS_QDIRM_00_gc = (0x00<<5), /* QDPH0 = 0, QDPH90 = 0 */ - EVSYS_QDIRM_01_gc = (0x01<<5), /* QDPH0 = 0, QDPH90 = 1 */ - EVSYS_QDIRM_10_gc = (0x02<<5), /* QDPH0 = 1, QDPH90 = 0 */ - EVSYS_QDIRM_11_gc = (0x03<<5), /* QDPH0 = 1, QDPH90 = 1 */ -} EVSYS_QDIRM_t; - -/* Digital filter coefficient */ -typedef enum EVSYS_DIGFILT_enum -{ - EVSYS_DIGFILT_1SAMPLE_gc = (0x00<<0), /* 1 SAMPLE */ - EVSYS_DIGFILT_2SAMPLES_gc = (0x01<<0), /* 2 SAMPLES */ - EVSYS_DIGFILT_3SAMPLES_gc = (0x02<<0), /* 3 SAMPLES */ - EVSYS_DIGFILT_4SAMPLES_gc = (0x03<<0), /* 4 SAMPLES */ - EVSYS_DIGFILT_5SAMPLES_gc = (0x04<<0), /* 5 SAMPLES */ - EVSYS_DIGFILT_6SAMPLES_gc = (0x05<<0), /* 6 SAMPLES */ - EVSYS_DIGFILT_7SAMPLES_gc = (0x06<<0), /* 7 SAMPLES */ - EVSYS_DIGFILT_8SAMPLES_gc = (0x07<<0), /* 8 SAMPLES */ -} EVSYS_DIGFILT_t; - -/* Event Channel multiplexer input selection */ -typedef enum EVSYS_CHMUX_enum -{ - EVSYS_CHMUX_OFF_gc = (0x00<<0), /* Off */ - EVSYS_CHMUX_RTC_OVF_gc = (0x08<<0), /* RTC Overflow */ - EVSYS_CHMUX_RTC_CMP_gc = (0x09<<0), /* RTC Compare Match */ - EVSYS_CHMUX_USB_gc = (0x0A<<0), /* USB Setup, SOF, CRC error and UNF/OVF */ - EVSYS_CHMUX_ACA_CH0_gc = (0x10<<0), /* Analog Comparator A Channel 0 */ - EVSYS_CHMUX_ACA_CH1_gc = (0x11<<0), /* Analog Comparator A Channel 1 */ - EVSYS_CHMUX_ACA_WIN_gc = (0x12<<0), /* Analog Comparator A Window */ - EVSYS_CHMUX_ACB_CH0_gc = (0x13<<0), /* Analog Comparator B Channel 0 */ - EVSYS_CHMUX_ACB_CH1_gc = (0x14<<0), /* Analog Comparator B Channel 1 */ - EVSYS_CHMUX_ACB_WIN_gc = (0x15<<0), /* Analog Comparator B Window */ - EVSYS_CHMUX_ADCA_CH0_gc = (0x20<<0), /* ADC A Channel 0 */ - EVSYS_CHMUX_ADCA_CH1_gc = (0x21<<0), /* ADC A Channel 1 */ - EVSYS_CHMUX_ADCA_CH2_gc = (0x22<<0), /* ADC A Channel 2 */ - EVSYS_CHMUX_ADCA_CH3_gc = (0x23<<0), /* ADC A Channel 3 */ - EVSYS_CHMUX_ADCB_CH0_gc = (0x24<<0), /* ADC B Channel 0 */ - EVSYS_CHMUX_ADCB_CH1_gc = (0x25<<0), /* ADC B Channel 1 */ - EVSYS_CHMUX_ADCB_CH2_gc = (0x26<<0), /* ADC B Channel 2 */ - EVSYS_CHMUX_ADCB_CH3_gc = (0x27<<0), /* ADC B Channel 3 */ - EVSYS_CHMUX_PORTA_PIN0_gc = (0x50<<0), /* Port A, Pin0 */ - EVSYS_CHMUX_PORTA_PIN1_gc = (0x51<<0), /* Port A, Pin1 */ - EVSYS_CHMUX_PORTA_PIN2_gc = (0x52<<0), /* Port A, Pin2 */ - EVSYS_CHMUX_PORTA_PIN3_gc = (0x53<<0), /* Port A, Pin3 */ - EVSYS_CHMUX_PORTA_PIN4_gc = (0x54<<0), /* Port A, Pin4 */ - EVSYS_CHMUX_PORTA_PIN5_gc = (0x55<<0), /* Port A, Pin5 */ - EVSYS_CHMUX_PORTA_PIN6_gc = (0x56<<0), /* Port A, Pin6 */ - EVSYS_CHMUX_PORTA_PIN7_gc = (0x57<<0), /* Port A, Pin7 */ - EVSYS_CHMUX_PORTB_PIN0_gc = (0x58<<0), /* Port B, Pin0 */ - EVSYS_CHMUX_PORTB_PIN1_gc = (0x59<<0), /* Port B, Pin1 */ - EVSYS_CHMUX_PORTB_PIN2_gc = (0x5A<<0), /* Port B, Pin2 */ - EVSYS_CHMUX_PORTB_PIN3_gc = (0x5B<<0), /* Port B, Pin3 */ - EVSYS_CHMUX_PORTB_PIN4_gc = (0x5C<<0), /* Port B, Pin4 */ - EVSYS_CHMUX_PORTB_PIN5_gc = (0x5D<<0), /* Port B, Pin5 */ - EVSYS_CHMUX_PORTB_PIN6_gc = (0x5E<<0), /* Port B, Pin6 */ - EVSYS_CHMUX_PORTB_PIN7_gc = (0x5F<<0), /* Port B, Pin7 */ - EVSYS_CHMUX_PORTC_PIN0_gc = (0x60<<0), /* Port C, Pin0 */ - EVSYS_CHMUX_PORTC_PIN1_gc = (0x61<<0), /* Port C, Pin1 */ - EVSYS_CHMUX_PORTC_PIN2_gc = (0x62<<0), /* Port C, Pin2 */ - EVSYS_CHMUX_PORTC_PIN3_gc = (0x63<<0), /* Port C, Pin3 */ - EVSYS_CHMUX_PORTC_PIN4_gc = (0x64<<0), /* Port C, Pin4 */ - EVSYS_CHMUX_PORTC_PIN5_gc = (0x65<<0), /* Port C, Pin5 */ - EVSYS_CHMUX_PORTC_PIN6_gc = (0x66<<0), /* Port C, Pin6 */ - EVSYS_CHMUX_PORTC_PIN7_gc = (0x67<<0), /* Port C, Pin7 */ - EVSYS_CHMUX_PORTD_PIN0_gc = (0x68<<0), /* Port D, Pin0 */ - EVSYS_CHMUX_PORTD_PIN1_gc = (0x69<<0), /* Port D, Pin1 */ - EVSYS_CHMUX_PORTD_PIN2_gc = (0x6A<<0), /* Port D, Pin2 */ - EVSYS_CHMUX_PORTD_PIN3_gc = (0x6B<<0), /* Port D, Pin3 */ - EVSYS_CHMUX_PORTD_PIN4_gc = (0x6C<<0), /* Port D, Pin4 */ - EVSYS_CHMUX_PORTD_PIN5_gc = (0x6D<<0), /* Port D, Pin5 */ - EVSYS_CHMUX_PORTD_PIN6_gc = (0x6E<<0), /* Port D, Pin6 */ - EVSYS_CHMUX_PORTD_PIN7_gc = (0x6F<<0), /* Port D, Pin7 */ - EVSYS_CHMUX_PORTE_PIN0_gc = (0x70<<0), /* Port E, Pin0 */ - EVSYS_CHMUX_PORTE_PIN1_gc = (0x71<<0), /* Port E, Pin1 */ - EVSYS_CHMUX_PORTE_PIN2_gc = (0x72<<0), /* Port E, Pin2 */ - EVSYS_CHMUX_PORTE_PIN3_gc = (0x73<<0), /* Port E, Pin3 */ - EVSYS_CHMUX_PORTE_PIN4_gc = (0x74<<0), /* Port E, Pin4 */ - EVSYS_CHMUX_PORTE_PIN5_gc = (0x75<<0), /* Port E, Pin5 */ - EVSYS_CHMUX_PORTE_PIN6_gc = (0x76<<0), /* Port E, Pin6 */ - EVSYS_CHMUX_PORTE_PIN7_gc = (0x77<<0), /* Port E, Pin7 */ - EVSYS_CHMUX_PORTF_PIN0_gc = (0x78<<0), /* Port F, Pin0 */ - EVSYS_CHMUX_PORTF_PIN1_gc = (0x79<<0), /* Port F, Pin1 */ - EVSYS_CHMUX_PORTF_PIN2_gc = (0x7A<<0), /* Port F, Pin2 */ - EVSYS_CHMUX_PORTF_PIN3_gc = (0x7B<<0), /* Port F, Pin3 */ - EVSYS_CHMUX_PORTF_PIN4_gc = (0x7C<<0), /* Port F, Pin4 */ - EVSYS_CHMUX_PORTF_PIN5_gc = (0x7D<<0), /* Port F, Pin5 */ - EVSYS_CHMUX_PORTF_PIN6_gc = (0x7E<<0), /* Port F, Pin6 */ - EVSYS_CHMUX_PORTF_PIN7_gc = (0x7F<<0), /* Port F, Pin7 */ - EVSYS_CHMUX_PRESCALER_1_gc = (0x80<<0), /* Prescaler, divide by 1 */ - EVSYS_CHMUX_PRESCALER_2_gc = (0x81<<0), /* Prescaler, divide by 2 */ - EVSYS_CHMUX_PRESCALER_4_gc = (0x82<<0), /* Prescaler, divide by 4 */ - EVSYS_CHMUX_PRESCALER_8_gc = (0x83<<0), /* Prescaler, divide by 8 */ - EVSYS_CHMUX_PRESCALER_16_gc = (0x84<<0), /* Prescaler, divide by 16 */ - EVSYS_CHMUX_PRESCALER_32_gc = (0x85<<0), /* Prescaler, divide by 32 */ - EVSYS_CHMUX_PRESCALER_64_gc = (0x86<<0), /* Prescaler, divide by 64 */ - EVSYS_CHMUX_PRESCALER_128_gc = (0x87<<0), /* Prescaler, divide by 128 */ - EVSYS_CHMUX_PRESCALER_256_gc = (0x88<<0), /* Prescaler, divide by 256 */ - EVSYS_CHMUX_PRESCALER_512_gc = (0x89<<0), /* Prescaler, divide by 512 */ - EVSYS_CHMUX_PRESCALER_1024_gc = (0x8A<<0), /* Prescaler, divide by 1024 */ - EVSYS_CHMUX_PRESCALER_2048_gc = (0x8B<<0), /* Prescaler, divide by 2048 */ - EVSYS_CHMUX_PRESCALER_4096_gc = (0x8C<<0), /* Prescaler, divide by 4096 */ - EVSYS_CHMUX_PRESCALER_8192_gc = (0x8D<<0), /* Prescaler, divide by 8192 */ - EVSYS_CHMUX_PRESCALER_16384_gc = (0x8E<<0), /* Prescaler, divide by 16384 */ - EVSYS_CHMUX_PRESCALER_32768_gc = (0x8F<<0), /* Prescaler, divide by 32768 */ - EVSYS_CHMUX_TCC0_OVF_gc = (0xC0<<0), /* Timer/Counter C0 Overflow */ - EVSYS_CHMUX_TCC0_ERR_gc = (0xC1<<0), /* Timer/Counter C0 Error */ - EVSYS_CHMUX_TCC0_CCA_gc = (0xC4<<0), /* Timer/Counter C0 Compare or Capture A */ - EVSYS_CHMUX_TCC0_CCB_gc = (0xC5<<0), /* Timer/Counter C0 Compare or Capture B */ - EVSYS_CHMUX_TCC0_CCC_gc = (0xC6<<0), /* Timer/Counter C0 Compare or Capture C */ - EVSYS_CHMUX_TCC0_CCD_gc = (0xC7<<0), /* Timer/Counter C0 Compare or Capture D */ - EVSYS_CHMUX_TCC1_OVF_gc = (0xC8<<0), /* Timer/Counter C1 Overflow */ - EVSYS_CHMUX_TCC1_ERR_gc = (0xC9<<0), /* Timer/Counter C1 Error */ - EVSYS_CHMUX_TCC1_CCA_gc = (0xCC<<0), /* Timer/Counter C1 Compare or Capture A */ - EVSYS_CHMUX_TCC1_CCB_gc = (0xCD<<0), /* Timer/Counter C1 Compare or Capture B */ - EVSYS_CHMUX_TCD0_OVF_gc = (0xD0<<0), /* Timer/Counter D0 Overflow */ - EVSYS_CHMUX_TCD0_ERR_gc = (0xD1<<0), /* Timer/Counter D0 Error */ - EVSYS_CHMUX_TCD0_CCA_gc = (0xD4<<0), /* Timer/Counter D0 Compare or Capture A */ - EVSYS_CHMUX_TCD0_CCB_gc = (0xD5<<0), /* Timer/Counter D0 Compare or Capture B */ - EVSYS_CHMUX_TCD0_CCC_gc = (0xD6<<0), /* Timer/Counter D0 Compare or Capture C */ - EVSYS_CHMUX_TCD0_CCD_gc = (0xD7<<0), /* Timer/Counter D0 Compare or Capture D */ - EVSYS_CHMUX_TCD1_OVF_gc = (0xD8<<0), /* Timer/Counter D1 Overflow */ - EVSYS_CHMUX_TCD1_ERR_gc = (0xD9<<0), /* Timer/Counter D1 Error */ - EVSYS_CHMUX_TCD1_CCA_gc = (0xDC<<0), /* Timer/Counter D1 Compare or Capture A */ - EVSYS_CHMUX_TCD1_CCB_gc = (0xDD<<0), /* Timer/Counter D1 Compare or Capture B */ - EVSYS_CHMUX_TCE0_OVF_gc = (0xE0<<0), /* Timer/Counter E0 Overflow */ - EVSYS_CHMUX_TCE0_ERR_gc = (0xE1<<0), /* Timer/Counter E0 Error */ - EVSYS_CHMUX_TCE0_CCA_gc = (0xE4<<0), /* Timer/Counter E0 Compare or Capture A */ - EVSYS_CHMUX_TCE0_CCB_gc = (0xE5<<0), /* Timer/Counter E0 Compare or Capture B */ - EVSYS_CHMUX_TCE0_CCC_gc = (0xE6<<0), /* Timer/Counter E0 Compare or Capture C */ - EVSYS_CHMUX_TCE0_CCD_gc = (0xE7<<0), /* Timer/Counter E0 Compare or Capture D */ - EVSYS_CHMUX_TCE1_OVF_gc = (0xE8<<0), /* Timer/Counter E1 Overflow */ - EVSYS_CHMUX_TCE1_ERR_gc = (0xE9<<0), /* Timer/Counter E1 Error */ - EVSYS_CHMUX_TCE1_CCA_gc = (0xEC<<0), /* Timer/Counter E1 Compare or Capture A */ - EVSYS_CHMUX_TCE1_CCB_gc = (0xED<<0), /* Timer/Counter E1 Compare or Capture B */ - EVSYS_CHMUX_TCF0_OVF_gc = (0xF0<<0), /* Timer/Counter F0 Overflow */ - EVSYS_CHMUX_TCF0_ERR_gc = (0xF1<<0), /* Timer/Counter F0 Error */ - EVSYS_CHMUX_TCF0_CCA_gc = (0xF4<<0), /* Timer/Counter F0 Compare or Capture A */ - EVSYS_CHMUX_TCF0_CCB_gc = (0xF5<<0), /* Timer/Counter F0 Compare or Capture B */ - EVSYS_CHMUX_TCF0_CCC_gc = (0xF6<<0), /* Timer/Counter F0 Compare or Capture C */ - EVSYS_CHMUX_TCF0_CCD_gc = (0xF7<<0), /* Timer/Counter F0 Compare or Capture D */ - EVSYS_CHMUX_TCF1_OVF_gc = (0xF8<<0), /* Timer/Counter F1 Overflow */ - EVSYS_CHMUX_TCF1_ERR_gc = (0xF9<<0), /* Timer/Counter F1 Error */ - EVSYS_CHMUX_TCF1_CCA_gc = (0xFC<<0), /* Timer/Counter F1 Compare or Capture A */ - EVSYS_CHMUX_TCF1_CCB_gc = (0xFD<<0), /* Timer/Counter F1 Compare or Capture B */ -} EVSYS_CHMUX_t; - - -/* --------------------------------------------------------------------------- -NVM - Non Volatile Memory Controller --------------------------------------------------------------------------- -*/ - -/* Non-volatile Memory Controller */ -typedef struct NVM_struct -{ - register8_t ADDR0; /* Address Register 0 */ - register8_t ADDR1; /* Address Register 1 */ - register8_t ADDR2; /* Address Register 2 */ - register8_t reserved_0x03; - register8_t DATA0; /* Data Register 0 */ - register8_t DATA1; /* Data Register 1 */ - register8_t DATA2; /* Data Register 2 */ - register8_t reserved_0x07; - register8_t reserved_0x08; - register8_t reserved_0x09; - register8_t CMD; /* Command */ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t INTCTRL; /* Interrupt Control */ - register8_t reserved_0x0E; - register8_t STATUS; /* Status */ - register8_t LOCK_BITS; /* Lock Bits (Changed from LOCKBITS to avoid avr-libc collision) */ -} NVM_t; - -/* NVM Command */ -typedef enum NVM_CMD_enum -{ - NVM_CMD_NO_OPERATION_gc = (0x00<<0), /* Noop/Ordinary LPM */ - NVM_CMD_READ_USER_SIG_ROW_gc = (0x01<<0), /* Read user signature row */ - NVM_CMD_READ_CALIB_ROW_gc = (0x02<<0), /* Read calibration row */ - NVM_CMD_READ_EEPROM_gc = (0x06<<0), /* Read EEPROM */ - NVM_CMD_READ_FUSES_gc = (0x07<<0), /* Read fuse byte */ - NVM_CMD_WRITE_LOCK_BITS_gc = (0x08<<0), /* Write lock bits */ - NVM_CMD_ERASE_USER_SIG_ROW_gc = (0x18<<0), /* Erase user signature row */ - NVM_CMD_WRITE_USER_SIG_ROW_gc = (0x1A<<0), /* Write user signature row */ - NVM_CMD_ERASE_APP_gc = (0x20<<0), /* Erase Application Section */ - NVM_CMD_ERASE_APP_PAGE_gc = (0x22<<0), /* Erase Application Section page */ - NVM_CMD_LOAD_FLASH_BUFFER_gc = (0x23<<0), /* Load Flash page buffer */ - NVM_CMD_WRITE_APP_PAGE_gc = (0x24<<0), /* Write Application Section page */ - NVM_CMD_ERASE_WRITE_APP_PAGE_gc = (0x25<<0), /* Erase-and-write Application Section page */ - NVM_CMD_ERASE_FLASH_BUFFER_gc = (0x26<<0), /* Erase/flush Flash page buffer */ - NVM_CMD_ERASE_BOOT_PAGE_gc = (0x2A<<0), /* Erase Boot Section page */ - NVM_CMD_ERASE_FLASH_PAGE_gc = (0x2B<<0), /* Erase Flash Page */ - NVM_CMD_WRITE_BOOT_PAGE_gc = (0x2C<<0), /* Write Boot Section page */ - NVM_CMD_ERASE_WRITE_BOOT_PAGE_gc = (0x2D<<0), /* Erase-and-write Boot Section page */ - NVM_CMD_WRITE_FLASH_PAGE_gc = (0x2E<<0), /* Write Flash Page */ - NVM_CMD_ERASE_WRITE_FLASH_PAGE_gc = (0x2F<<0), /* Erase-and-write Flash Page */ - NVM_CMD_ERASE_EEPROM_gc = (0x30<<0), /* Erase EEPROM */ - NVM_CMD_ERASE_EEPROM_PAGE_gc = (0x32<<0), /* Erase EEPROM page */ - NVM_CMD_LOAD_EEPROM_BUFFER_gc = (0x33<<0), /* Load EEPROM page buffer */ - NVM_CMD_WRITE_EEPROM_PAGE_gc = (0x34<<0), /* Write EEPROM page */ - NVM_CMD_ERASE_WRITE_EEPROM_PAGE_gc = (0x35<<0), /* Erase-and-write EEPROM page */ - NVM_CMD_ERASE_EEPROM_BUFFER_gc = (0x36<<0), /* Erase/flush EEPROM page buffer */ - NVM_CMD_APP_CRC_gc = (0x38<<0), /* Application section CRC */ - NVM_CMD_BOOT_CRC_gc = (0x39<<0), /* Boot Section CRC */ - NVM_CMD_FLASH_RANGE_CRC_gc = (0x3A<<0), /* Flash Range CRC */ - NVM_CMD_CHIP_ERASE_gc = (0x40<<0), /* Erase Chip */ - NVM_CMD_READ_NVM_gc = (0x43<<0), /* Read NVM */ - NVM_CMD_WRITE_FUSE_gc = (0x4C<<0), /* Write Fuse byte */ - NVM_CMD_ERASE_BOOT_gc = (0x68<<0), /* Erase Boot Section */ - NVM_CMD_FLASH_CRC_gc = (0x78<<0), /* Flash CRC */ -} NVM_CMD_t; - -/* SPM ready interrupt level */ -typedef enum NVM_SPMLVL_enum -{ - NVM_SPMLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ - NVM_SPMLVL_LO_gc = (0x01<<2), /* Low level */ - NVM_SPMLVL_MED_gc = (0x02<<2), /* Medium level */ - NVM_SPMLVL_HI_gc = (0x03<<2), /* High level */ -} NVM_SPMLVL_t; - -/* EEPROM ready interrupt level */ -typedef enum NVM_EELVL_enum -{ - NVM_EELVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ - NVM_EELVL_LO_gc = (0x01<<0), /* Low level */ - NVM_EELVL_MED_gc = (0x02<<0), /* Medium level */ - NVM_EELVL_HI_gc = (0x03<<0), /* High level */ -} NVM_EELVL_t; - -/* Boot lock bits - boot setcion */ -typedef enum NVM_BLBB_enum -{ - NVM_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ - NVM_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ - NVM_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ - NVM_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ -} NVM_BLBB_t; - -/* Boot lock bits - application section */ -typedef enum NVM_BLBA_enum -{ - NVM_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ - NVM_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ - NVM_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ - NVM_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ -} NVM_BLBA_t; - -/* Boot lock bits - application table section */ -typedef enum NVM_BLBAT_enum -{ - NVM_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ - NVM_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ - NVM_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ - NVM_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ -} NVM_BLBAT_t; - -/* Lock bits */ -typedef enum NVM_LB_enum -{ - NVM_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ - NVM_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ - NVM_LB_NOLOCK_gc = (0x03<<0), /* No locks */ -} NVM_LB_t; - - -/* --------------------------------------------------------------------------- -ADC - Analog/Digital Converter --------------------------------------------------------------------------- -*/ - -/* ADC Channel */ -typedef struct ADC_CH_struct -{ - register8_t CTRL; /* Control Register */ - register8_t MUXCTRL; /* MUX Control */ - register8_t INTCTRL; /* Channel Interrupt Control Register */ - register8_t INTFLAGS; /* Interrupt Flags */ - _WORDREGISTER(RES); /* Channel Result */ - register8_t SCAN; /* Input Channel Scan */ - register8_t reserved_0x07; -} ADC_CH_t; - - -/* Analog-to-Digital Converter */ -typedef struct ADC_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t REFCTRL; /* Reference Control */ - register8_t EVCTRL; /* Event Control */ - register8_t PRESCALER; /* Clock Prescaler */ - register8_t reserved_0x05; - register8_t INTFLAGS; /* Interrupt Flags */ - register8_t TEMP; /* Temporary Register */ - register8_t reserved_0x08; - register8_t reserved_0x09; - register8_t reserved_0x0A; - register8_t reserved_0x0B; - _WORDREGISTER(CAL); /* Calibration Value */ - register8_t reserved_0x0E; - register8_t reserved_0x0F; - _WORDREGISTER(CH0RES); /* Channel 0 Result */ - _WORDREGISTER(CH1RES); /* Channel 1 Result */ - _WORDREGISTER(CH2RES); /* Channel 2 Result */ - _WORDREGISTER(CH3RES); /* Channel 3 Result */ - _WORDREGISTER(CMP); /* Compare Value */ - register8_t reserved_0x1A; - register8_t reserved_0x1B; - register8_t reserved_0x1C; - register8_t reserved_0x1D; - register8_t reserved_0x1E; - register8_t reserved_0x1F; - ADC_CH_t CH0; /* ADC Channel 0 */ - ADC_CH_t CH1; /* ADC Channel 1 */ - ADC_CH_t CH2; /* ADC Channel 2 */ - ADC_CH_t CH3; /* ADC Channel 3 */ -} ADC_t; - -/* Positive input multiplexer selection */ -typedef enum ADC_CH_MUXPOS_enum -{ - ADC_CH_MUXPOS_PIN0_gc = (0x00<<3), /* Input pin 0 */ - ADC_CH_MUXPOS_PIN1_gc = (0x01<<3), /* Input pin 1 */ - ADC_CH_MUXPOS_PIN2_gc = (0x02<<3), /* Input pin 2 */ - ADC_CH_MUXPOS_PIN3_gc = (0x03<<3), /* Input pin 3 */ - ADC_CH_MUXPOS_PIN4_gc = (0x04<<3), /* Input pin 4 */ - ADC_CH_MUXPOS_PIN5_gc = (0x05<<3), /* Input pin 5 */ - ADC_CH_MUXPOS_PIN6_gc = (0x06<<3), /* Input pin 6 */ - ADC_CH_MUXPOS_PIN7_gc = (0x07<<3), /* Input pin 7 */ - ADC_CH_MUXPOS_PIN8_gc = (0x08<<3), /* Input pin 8 */ - ADC_CH_MUXPOS_PIN9_gc = (0x09<<3), /* Input pin 9 */ - ADC_CH_MUXPOS_PIN10_gc = (0x0A<<3), /* Input pin 10 */ - ADC_CH_MUXPOS_PIN11_gc = (0x0B<<3), /* Input pin 11 */ - ADC_CH_MUXPOS_PIN12_gc = (0x0C<<3), /* Input pin 12 */ - ADC_CH_MUXPOS_PIN13_gc = (0x0D<<3), /* Input pin 13 */ - ADC_CH_MUXPOS_PIN14_gc = (0x0E<<3), /* Input pin 14 */ - ADC_CH_MUXPOS_PIN15_gc = (0x0F<<3), /* Input pin 15 */ -} ADC_CH_MUXPOS_t; - -/* Internal input multiplexer selections */ -typedef enum ADC_CH_MUXINT_enum -{ - ADC_CH_MUXINT_TEMP_gc = (0x00<<3), /* Temperature Reference */ - ADC_CH_MUXINT_BANDGAP_gc = (0x01<<3), /* Bandgap Reference */ - ADC_CH_MUXINT_SCALEDVCC_gc = (0x02<<3), /* 1/10 scaled VCC */ - ADC_CH_MUXINT_DAC_gc = (0x03<<3), /* DAC output */ -} ADC_CH_MUXINT_t; - -/* Negative input multiplexer selection */ -typedef enum ADC_CH_MUXNEG_enum -{ - ADC_CH_MUXNEG_PIN0_gc = (0x00<<0), /* Input pin 0 (Input Mode = 2) */ - ADC_CH_MUXNEG_PIN1_gc = (0x01<<0), /* Input pin 1 (Input Mode = 2) */ - ADC_CH_MUXNEG_PIN2_gc = (0x02<<0), /* Input pin 2 (Input Mode = 2) */ - ADC_CH_MUXNEG_PIN3_gc = (0x03<<0), /* Input pin 3 (Input Mode = 2) */ - ADC_CH_MUXNEG_PIN4_gc = (0x00<<0), /* Input pin 4 (Input Mode = 3) */ - ADC_CH_MUXNEG_PIN5_gc = (0x01<<0), /* Input pin 5 (Input Mode = 3) */ - ADC_CH_MUXNEG_PIN6_gc = (0x02<<0), /* Input pin 6 (Input Mode = 3) */ - ADC_CH_MUXNEG_PIN7_gc = (0x03<<0), /* Input pin 7 (Input Mode = 3) */ - ADC_CH_MUXNEG_GND_MODE3_gc = (0x05<<0), /* PAD Ground (Input Mode = 2) */ - ADC_CH_MUXNEG_INTGND_MODE3_gc = (0x07<<0), /* Internal Ground (Input Mode = 2) */ - ADC_CH_MUXNEG_INTGND_MODE4_gc = (0x04<<0), /* Internal Ground (Input Mode = 3) */ - ADC_CH_MUXNEG_GND_MODE4_gc = (0x07<<0), /* PAD Ground (Input Mode = 3) */ -} ADC_CH_MUXNEG_t; - -/* Input mode */ -typedef enum ADC_CH_INPUTMODE_enum -{ - ADC_CH_INPUTMODE_INTERNAL_gc = (0x00<<0), /* Internal inputs, no gain */ - ADC_CH_INPUTMODE_SINGLEENDED_gc = (0x01<<0), /* Single-ended input, no gain */ - ADC_CH_INPUTMODE_DIFF_gc = (0x02<<0), /* Differential input, no gain */ - ADC_CH_INPUTMODE_DIFFWGAIN_gc = (0x03<<0), /* Differential input, with gain */ -} ADC_CH_INPUTMODE_t; - -/* Gain factor */ -typedef enum ADC_CH_GAIN_enum -{ - ADC_CH_GAIN_1X_gc = (0x00<<2), /* 1x gain */ - ADC_CH_GAIN_2X_gc = (0x01<<2), /* 2x gain */ - ADC_CH_GAIN_4X_gc = (0x02<<2), /* 4x gain */ - ADC_CH_GAIN_8X_gc = (0x03<<2), /* 8x gain */ - ADC_CH_GAIN_16X_gc = (0x04<<2), /* 16x gain */ - ADC_CH_GAIN_32X_gc = (0x05<<2), /* 32x gain */ - ADC_CH_GAIN_64X_gc = (0x06<<2), /* 64x gain */ - ADC_CH_GAIN_DIV2_gc = (0x07<<2), /* x/2 gain */ -} ADC_CH_GAIN_t; - -/* Conversion result resolution */ -typedef enum ADC_RESOLUTION_enum -{ - ADC_RESOLUTION_12BIT_gc = (0x00<<1), /* 12-bit right-adjusted result */ - ADC_RESOLUTION_8BIT_gc = (0x02<<1), /* 8-bit right-adjusted result */ - ADC_RESOLUTION_LEFT12BIT_gc = (0x03<<1), /* 12-bit left-adjusted result */ -} ADC_RESOLUTION_t; - -/* Current Limitation Mode */ -typedef enum ADC_CURRLIMIT_enum -{ - ADC_CURRLIMIT_NO_gc = (0x00<<5), /* No limit */ - ADC_CURRLIMIT_LOW_gc = (0x01<<5), /* Low current limit, max. sampling rate 1.5MSPS */ - ADC_CURRLIMIT_MED_gc = (0x02<<5), /* Medium current limit, max. sampling rate 1MSPS */ - ADC_CURRLIMIT_HIGH_gc = (0x03<<5), /* High current limit, max. sampling rate 0.5MSPS */ -} ADC_CURRLIMIT_t; - -/* Voltage reference selection */ -typedef enum ADC_REFSEL_enum -{ - ADC_REFSEL_INT1V_gc = (0x00<<4), /* Internal 1V */ - ADC_REFSEL_INTVCC_gc = (0x01<<4), /* Internal VCC / 1.6 */ - ADC_REFSEL_AREFA_gc = (0x02<<4), /* External reference on PORT A */ - ADC_REFSEL_AREFB_gc = (0x03<<4), /* External reference on PORT B */ - ADC_REFSEL_INTVCC2_gc = (0x04<<4), /* Internal VCC / 2 */ -} ADC_REFSEL_t; - -/* Channel sweep selection */ -typedef enum ADC_SWEEP_enum -{ - ADC_SWEEP_0_gc = (0x00<<6), /* ADC Channel 0 */ - ADC_SWEEP_01_gc = (0x01<<6), /* ADC Channel 0,1 */ - ADC_SWEEP_012_gc = (0x02<<6), /* ADC Channel 0,1,2 */ - ADC_SWEEP_0123_gc = (0x03<<6), /* ADC Channel 0,1,2,3 */ -} ADC_SWEEP_t; - -/* Event channel input selection */ -typedef enum ADC_EVSEL_enum -{ - ADC_EVSEL_0123_gc = (0x00<<3), /* Event Channel 0,1,2,3 */ - ADC_EVSEL_1234_gc = (0x01<<3), /* Event Channel 1,2,3,4 */ - ADC_EVSEL_2345_gc = (0x02<<3), /* Event Channel 2,3,4,5 */ - ADC_EVSEL_3456_gc = (0x03<<3), /* Event Channel 3,4,5,6 */ - ADC_EVSEL_4567_gc = (0x04<<3), /* Event Channel 4,5,6,7 */ - ADC_EVSEL_567_gc = (0x05<<3), /* Event Channel 5,6,7 */ - ADC_EVSEL_67_gc = (0x06<<3), /* Event Channel 6,7 */ - ADC_EVSEL_7_gc = (0x07<<3), /* Event Channel 7 */ -} ADC_EVSEL_t; - -/* Event action selection */ -typedef enum ADC_EVACT_enum -{ - ADC_EVACT_NONE_gc = (0x00<<0), /* No event action */ - ADC_EVACT_CH0_gc = (0x01<<0), /* First event triggers channel 0 */ - ADC_EVACT_CH01_gc = (0x02<<0), /* First two events trigger channel 0,1 */ - ADC_EVACT_CH012_gc = (0x03<<0), /* First three events trigger channel 0,1,2 */ - ADC_EVACT_CH0123_gc = (0x04<<0), /* Events trigger channel 0,1,2,3 */ - ADC_EVACT_SWEEP_gc = (0x05<<0), /* First event triggers sweep */ - ADC_EVACT_SYNCSWEEP_gc = (0x06<<0), /* The ADC is flushed and restarted for accurate timing */ -} ADC_EVACT_t; - -/* Interupt mode */ -typedef enum ADC_CH_INTMODE_enum -{ - ADC_CH_INTMODE_COMPLETE_gc = (0x00<<2), /* Interrupt on conversion complete */ - ADC_CH_INTMODE_BELOW_gc = (0x01<<2), /* Interrupt on result below compare value */ - ADC_CH_INTMODE_ABOVE_gc = (0x03<<2), /* Interrupt on result above compare value */ -} ADC_CH_INTMODE_t; - -/* Interrupt level */ -typedef enum ADC_CH_INTLVL_enum -{ - ADC_CH_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ - ADC_CH_INTLVL_LO_gc = (0x01<<0), /* Low level */ - ADC_CH_INTLVL_MED_gc = (0x02<<0), /* Medium level */ - ADC_CH_INTLVL_HI_gc = (0x03<<0), /* High level */ -} ADC_CH_INTLVL_t; - -/* DMA request selection */ -typedef enum ADC_DMASEL_enum -{ - ADC_DMASEL_OFF_gc = (0x00<<6), /* Combined DMA request OFF */ - ADC_DMASEL_CH01_gc = (0x01<<6), /* ADC Channel 0 or 1 */ - ADC_DMASEL_CH012_gc = (0x02<<6), /* ADC Channel 0 or 1 or 2 */ - ADC_DMASEL_CH0123_gc = (0x03<<6), /* ADC Channel 0 or 1 or 2 or 3 */ -} ADC_DMASEL_t; - -/* Clock prescaler */ -typedef enum ADC_PRESCALER_enum -{ - ADC_PRESCALER_DIV4_gc = (0x00<<0), /* Divide clock by 4 */ - ADC_PRESCALER_DIV8_gc = (0x01<<0), /* Divide clock by 8 */ - ADC_PRESCALER_DIV16_gc = (0x02<<0), /* Divide clock by 16 */ - ADC_PRESCALER_DIV32_gc = (0x03<<0), /* Divide clock by 32 */ - ADC_PRESCALER_DIV64_gc = (0x04<<0), /* Divide clock by 64 */ - ADC_PRESCALER_DIV128_gc = (0x05<<0), /* Divide clock by 128 */ - ADC_PRESCALER_DIV256_gc = (0x06<<0), /* Divide clock by 256 */ - ADC_PRESCALER_DIV512_gc = (0x07<<0), /* Divide clock by 512 */ -} ADC_PRESCALER_t; - - -/* --------------------------------------------------------------------------- -DAC - Digital/Analog Converter --------------------------------------------------------------------------- -*/ - -/* Digital-to-Analog Converter */ -typedef struct DAC_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t CTRLC; /* Control Register C */ - register8_t EVCTRL; /* Event Input Control */ - register8_t reserved_0x04; - register8_t STATUS; /* Status */ - register8_t reserved_0x06; - register8_t reserved_0x07; - register8_t CH0GAINCAL; /* Gain Calibration */ - register8_t CH0OFFSETCAL; /* Offset Calibration */ - register8_t CH1GAINCAL; /* Gain Calibration */ - register8_t CH1OFFSETCAL; /* Offset Calibration */ - register8_t reserved_0x0C; - register8_t reserved_0x0D; - register8_t reserved_0x0E; - register8_t reserved_0x0F; - register8_t reserved_0x10; - register8_t reserved_0x11; - register8_t reserved_0x12; - register8_t reserved_0x13; - register8_t reserved_0x14; - register8_t reserved_0x15; - register8_t reserved_0x16; - register8_t reserved_0x17; - _WORDREGISTER(CH0DATA); /* Channel 0 Data */ - _WORDREGISTER(CH1DATA); /* Channel 1 Data */ -} DAC_t; - -/* Output channel selection */ -typedef enum DAC_CHSEL_enum -{ - DAC_CHSEL_SINGLE_gc = (0x00<<5), /* Single channel operation (Channel 0 only) */ - DAC_CHSEL_SINGLE1_gc = (0x01<<5), /* Single channel operation (Channel 1 only) */ - DAC_CHSEL_DUAL_gc = (0x02<<5), /* Dual channel operation (Channel 0 and channel 1) */ -} DAC_CHSEL_t; - -/* Reference voltage selection */ -typedef enum DAC_REFSEL_enum -{ - DAC_REFSEL_INT1V_gc = (0x00<<3), /* Internal 1V */ - DAC_REFSEL_AVCC_gc = (0x01<<3), /* Analog supply voltage */ - DAC_REFSEL_AREFA_gc = (0x02<<3), /* External reference on AREF on PORTA */ - DAC_REFSEL_AREFB_gc = (0x03<<3), /* External reference on AREF on PORTB */ -} DAC_REFSEL_t; - -/* Event channel selection */ -typedef enum DAC_EVSEL_enum -{ - DAC_EVSEL_0_gc = (0x00<<0), /* Event Channel 0 */ - DAC_EVSEL_1_gc = (0x01<<0), /* Event Channel 1 */ - DAC_EVSEL_2_gc = (0x02<<0), /* Event Channel 2 */ - DAC_EVSEL_3_gc = (0x03<<0), /* Event Channel 3 */ - DAC_EVSEL_4_gc = (0x04<<0), /* Event Channel 4 */ - DAC_EVSEL_5_gc = (0x05<<0), /* Event Channel 5 */ - DAC_EVSEL_6_gc = (0x06<<0), /* Event Channel 6 */ - DAC_EVSEL_7_gc = (0x07<<0), /* Event Channel 7 */ -} DAC_EVSEL_t; - - -/* --------------------------------------------------------------------------- -AC - Analog Comparator --------------------------------------------------------------------------- -*/ - -/* Analog Comparator */ -typedef struct AC_struct -{ - register8_t AC0CTRL; /* Analog Comparator 0 Control */ - register8_t AC1CTRL; /* Analog Comparator 1 Control */ - register8_t AC0MUXCTRL; /* Analog Comparator 0 MUX Control */ - register8_t AC1MUXCTRL; /* Analog Comparator 1 MUX Control */ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t WINCTRL; /* Window Mode Control */ - register8_t STATUS; /* Status */ -} AC_t; - -/* Interrupt mode */ -typedef enum AC_INTMODE_enum -{ - AC_INTMODE_BOTHEDGES_gc = (0x00<<6), /* Interrupt on both edges */ - AC_INTMODE_FALLING_gc = (0x02<<6), /* Interrupt on falling edge */ - AC_INTMODE_RISING_gc = (0x03<<6), /* Interrupt on rising edge */ -} AC_INTMODE_t; - -/* Interrupt level */ -typedef enum AC_INTLVL_enum -{ - AC_INTLVL_OFF_gc = (0x00<<4), /* Interrupt disabled */ - AC_INTLVL_LO_gc = (0x01<<4), /* Low level */ - AC_INTLVL_MED_gc = (0x02<<4), /* Medium level */ - AC_INTLVL_HI_gc = (0x03<<4), /* High level */ -} AC_INTLVL_t; - -/* Hysteresis mode selection */ -typedef enum AC_HYSMODE_enum -{ - AC_HYSMODE_NO_gc = (0x00<<1), /* No hysteresis */ - AC_HYSMODE_SMALL_gc = (0x01<<1), /* Small hysteresis */ - AC_HYSMODE_LARGE_gc = (0x02<<1), /* Large hysteresis */ -} AC_HYSMODE_t; - -/* Positive input multiplexer selection */ -typedef enum AC_MUXPOS_enum -{ - AC_MUXPOS_PIN0_gc = (0x00<<3), /* Pin 0 */ - AC_MUXPOS_PIN1_gc = (0x01<<3), /* Pin 1 */ - AC_MUXPOS_PIN2_gc = (0x02<<3), /* Pin 2 */ - AC_MUXPOS_PIN3_gc = (0x03<<3), /* Pin 3 */ - AC_MUXPOS_PIN4_gc = (0x04<<3), /* Pin 4 */ - AC_MUXPOS_PIN5_gc = (0x05<<3), /* Pin 5 */ - AC_MUXPOS_PIN6_gc = (0x06<<3), /* Pin 6 */ - AC_MUXPOS_DAC_gc = (0x07<<3), /* DAC output */ -} AC_MUXPOS_t; - -/* Negative input multiplexer selection */ -typedef enum AC_MUXNEG_enum -{ - AC_MUXNEG_PIN0_gc = (0x00<<0), /* Pin 0 */ - AC_MUXNEG_PIN1_gc = (0x01<<0), /* Pin 1 */ - AC_MUXNEG_PIN3_gc = (0x02<<0), /* Pin 3 */ - AC_MUXNEG_PIN5_gc = (0x03<<0), /* Pin 5 */ - AC_MUXNEG_PIN7_gc = (0x04<<0), /* Pin 7 */ - AC_MUXNEG_DAC_gc = (0x05<<0), /* DAC output */ - AC_MUXNEG_BANDGAP_gc = (0x06<<0), /* Bandgap Reference */ - AC_MUXNEG_SCALER_gc = (0x07<<0), /* Internal voltage scaler */ -} AC_MUXNEG_t; - -/* Windows interrupt mode */ -typedef enum AC_WINTMODE_enum -{ - AC_WINTMODE_ABOVE_gc = (0x00<<2), /* Interrupt on above window */ - AC_WINTMODE_INSIDE_gc = (0x01<<2), /* Interrupt on inside window */ - AC_WINTMODE_BELOW_gc = (0x02<<2), /* Interrupt on below window */ - AC_WINTMODE_OUTSIDE_gc = (0x03<<2), /* Interrupt on outside window */ -} AC_WINTMODE_t; - -/* Window interrupt level */ -typedef enum AC_WINTLVL_enum -{ - AC_WINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ - AC_WINTLVL_LO_gc = (0x01<<0), /* Low priority */ - AC_WINTLVL_MED_gc = (0x02<<0), /* Medium priority */ - AC_WINTLVL_HI_gc = (0x03<<0), /* High priority */ -} AC_WINTLVL_t; - -/* Window mode state */ -typedef enum AC_WSTATE_enum -{ - AC_WSTATE_ABOVE_gc = (0x00<<6), /* Signal above window */ - AC_WSTATE_INSIDE_gc = (0x01<<6), /* Signal inside window */ - AC_WSTATE_BELOW_gc = (0x02<<6), /* Signal below window */ -} AC_WSTATE_t; - - -/* --------------------------------------------------------------------------- -RTC - Real-Time Counter --------------------------------------------------------------------------- -*/ - -/* Real-Time Counter */ -typedef struct RTC_struct -{ - register8_t CTRL; /* Control Register */ - register8_t STATUS; /* Status Register */ - register8_t INTCTRL; /* Interrupt Control Register */ - register8_t INTFLAGS; /* Interrupt Flags */ - register8_t TEMP; /* Temporary register */ - register8_t reserved_0x05; - register8_t reserved_0x06; - register8_t reserved_0x07; - _WORDREGISTER(CNT); /* Count Register */ - _WORDREGISTER(PER); /* Period Register */ - _WORDREGISTER(COMP); /* Compare Register */ -} RTC_t; - -/* Prescaler Factor */ -typedef enum RTC_PRESCALER_enum -{ - RTC_PRESCALER_OFF_gc = (0x00<<0), /* RTC Off */ - RTC_PRESCALER_DIV1_gc = (0x01<<0), /* RTC Clock */ - RTC_PRESCALER_DIV2_gc = (0x02<<0), /* RTC Clock / 2 */ - RTC_PRESCALER_DIV8_gc = (0x03<<0), /* RTC Clock / 8 */ - RTC_PRESCALER_DIV16_gc = (0x04<<0), /* RTC Clock / 16 */ - RTC_PRESCALER_DIV64_gc = (0x05<<0), /* RTC Clock / 64 */ - RTC_PRESCALER_DIV256_gc = (0x06<<0), /* RTC Clock / 256 */ - RTC_PRESCALER_DIV1024_gc = (0x07<<0), /* RTC Clock / 1024 */ -} RTC_PRESCALER_t; - -/* Compare Interrupt level */ -typedef enum RTC_COMPINTLVL_enum -{ - RTC_COMPINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ - RTC_COMPINTLVL_LO_gc = (0x01<<2), /* Low Level */ - RTC_COMPINTLVL_MED_gc = (0x02<<2), /* Medium Level */ - RTC_COMPINTLVL_HI_gc = (0x03<<2), /* High Level */ -} RTC_COMPINTLVL_t; - -/* Overflow Interrupt level */ -typedef enum RTC_OVFINTLVL_enum -{ - RTC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - RTC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ - RTC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ - RTC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ -} RTC_OVFINTLVL_t; - - -/* --------------------------------------------------------------------------- -TWI - Two-Wire Interface --------------------------------------------------------------------------- -*/ - -/* */ -typedef struct TWI_MASTER_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t CTRLC; /* Control Register C */ - register8_t STATUS; /* Status Register */ - register8_t BAUD; /* Baurd Rate Control Register */ - register8_t ADDR; /* Address Register */ - register8_t DATA; /* Data Register */ -} TWI_MASTER_t; - - -/* */ -typedef struct TWI_SLAVE_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t STATUS; /* Status Register */ - register8_t ADDR; /* Address Register */ - register8_t DATA; /* Data Register */ - register8_t ADDRMASK; /* Address Mask Register */ -} TWI_SLAVE_t; - - -/* Two-Wire Interface */ -typedef struct TWI_struct -{ - register8_t CTRL; /* TWI Common Control Register */ - TWI_MASTER_t MASTER; /* TWI master module */ - TWI_SLAVE_t SLAVE; /* TWI slave module */ -} TWI_t; - -/* SDA Hold Time */ -typedef enum TWI_SDAHOLD_enum -{ - TWI_SDAHOLD_OFF_gc = (0x00<<1), /* SDA Hold Time off */ - TWI_SDAHOLD_50NS_gc = (0x01<<1), /* SDA Hold Time 50 ns */ - TWI_SDAHOLD_300NS_gc = (0x02<<1), /* SDA Hold Time 300 ns */ - TWI_SDAHOLD_400NS_gc = (0x03<<1), /* SDA Hold Time 400 ns */ -} TWI_SDAHOLD_t; - -/* Master Interrupt Level */ -typedef enum TWI_MASTER_INTLVL_enum -{ - TWI_MASTER_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ - TWI_MASTER_INTLVL_LO_gc = (0x01<<6), /* Low Level */ - TWI_MASTER_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ - TWI_MASTER_INTLVL_HI_gc = (0x03<<6), /* High Level */ -} TWI_MASTER_INTLVL_t; - -/* Inactive Timeout */ -typedef enum TWI_MASTER_TIMEOUT_enum -{ - TWI_MASTER_TIMEOUT_DISABLED_gc = (0x00<<2), /* Bus Timeout Disabled */ - TWI_MASTER_TIMEOUT_50US_gc = (0x01<<2), /* 50 Microseconds */ - TWI_MASTER_TIMEOUT_100US_gc = (0x02<<2), /* 100 Microseconds */ - TWI_MASTER_TIMEOUT_200US_gc = (0x03<<2), /* 200 Microseconds */ -} TWI_MASTER_TIMEOUT_t; - -/* Master Command */ -typedef enum TWI_MASTER_CMD_enum -{ - TWI_MASTER_CMD_NOACT_gc = (0x00<<0), /* No Action */ - TWI_MASTER_CMD_REPSTART_gc = (0x01<<0), /* Issue Repeated Start Condition */ - TWI_MASTER_CMD_RECVTRANS_gc = (0x02<<0), /* Receive or Transmit Data */ - TWI_MASTER_CMD_STOP_gc = (0x03<<0), /* Issue Stop Condition */ -} TWI_MASTER_CMD_t; - -/* Master Bus State */ -typedef enum TWI_MASTER_BUSSTATE_enum -{ - TWI_MASTER_BUSSTATE_UNKNOWN_gc = (0x00<<0), /* Unknown Bus State */ - TWI_MASTER_BUSSTATE_IDLE_gc = (0x01<<0), /* Bus is Idle */ - TWI_MASTER_BUSSTATE_OWNER_gc = (0x02<<0), /* This Module Controls The Bus */ - TWI_MASTER_BUSSTATE_BUSY_gc = (0x03<<0), /* The Bus is Busy */ -} TWI_MASTER_BUSSTATE_t; - -/* Slave Interrupt Level */ -typedef enum TWI_SLAVE_INTLVL_enum -{ - TWI_SLAVE_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ - TWI_SLAVE_INTLVL_LO_gc = (0x01<<6), /* Low Level */ - TWI_SLAVE_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ - TWI_SLAVE_INTLVL_HI_gc = (0x03<<6), /* High Level */ -} TWI_SLAVE_INTLVL_t; - -/* Slave Command */ -typedef enum TWI_SLAVE_CMD_enum -{ - TWI_SLAVE_CMD_NOACT_gc = (0x00<<0), /* No Action */ - TWI_SLAVE_CMD_COMPTRANS_gc = (0x02<<0), /* Used To Complete a Transaction */ - TWI_SLAVE_CMD_RESPONSE_gc = (0x03<<0), /* Used in Response to Address/Data Interrupt */ -} TWI_SLAVE_CMD_t; - - -/* --------------------------------------------------------------------------- -USB - USB --------------------------------------------------------------------------- -*/ - -/* USB Endpoint */ -typedef struct USB_EP_struct -{ - register8_t STATUS; /* Endpoint Status */ - register8_t CTRL; /* Endpoint Control */ - _WORDREGISTER(CNT); /* USB Endpoint Counter */ - _WORDREGISTER(DATAPTR); /* Data Pointer */ - _WORDREGISTER(AUXDATA); /* Auxiliary Data */ -} USB_EP_t; - - -/* Universal Serial Bus */ -typedef struct USB_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t STATUS; /* Status Register */ - register8_t ADDR; /* Address Register */ - register8_t FIFOWP; /* FIFO Write Pointer Register */ - register8_t FIFORP; /* FIFO Read Pointer Register */ - _WORDREGISTER(EPPTR); /* Endpoint Configuration Table Pointer */ - register8_t INTCTRLA; /* Interrupt Control Register A */ - register8_t INTCTRLB; /* Interrupt Control Register B */ - register8_t INTFLAGSACLR; /* Clear Interrupt Flag Register A */ - register8_t INTFLAGSASET; /* Set Interrupt Flag Register A */ - register8_t INTFLAGSBCLR; /* Clear Interrupt Flag Register B */ - register8_t INTFLAGSBSET; /* Set Interrupt Flag Register B */ - register8_t reserved_0x0E; - register8_t reserved_0x0F; - register8_t reserved_0x10; - register8_t reserved_0x11; - register8_t reserved_0x12; - register8_t reserved_0x13; - register8_t reserved_0x14; - register8_t reserved_0x15; - register8_t reserved_0x16; - register8_t reserved_0x17; - register8_t reserved_0x18; - register8_t reserved_0x19; - register8_t reserved_0x1A; - register8_t reserved_0x1B; - register8_t reserved_0x1C; - register8_t reserved_0x1D; - register8_t reserved_0x1E; - register8_t reserved_0x1F; - register8_t reserved_0x20; - register8_t reserved_0x21; - register8_t reserved_0x22; - register8_t reserved_0x23; - register8_t reserved_0x24; - register8_t reserved_0x25; - register8_t reserved_0x26; - register8_t reserved_0x27; - register8_t reserved_0x28; - register8_t reserved_0x29; - register8_t reserved_0x2A; - register8_t reserved_0x2B; - register8_t reserved_0x2C; - register8_t reserved_0x2D; - register8_t reserved_0x2E; - register8_t reserved_0x2F; - register8_t reserved_0x30; - register8_t reserved_0x31; - register8_t reserved_0x32; - register8_t reserved_0x33; - register8_t reserved_0x34; - register8_t reserved_0x35; - register8_t reserved_0x36; - register8_t reserved_0x37; - register8_t reserved_0x38; - register8_t reserved_0x39; - register8_t CAL0; /* Calibration Byte 0 */ - register8_t CAL1; /* Calibration Byte 1 */ -} USB_t; - - -/* USB Endpoint Table */ -typedef struct USB_EP_TABLE_struct -{ - USB_EP_t EP0OUT; /* Endpoint 0 */ - USB_EP_t EP0IN; /* Endpoint 0 */ - USB_EP_t EP1OUT; /* Endpoint 1 */ - USB_EP_t EP1IN; /* Endpoint 1 */ - USB_EP_t EP2OUT; /* Endpoint 2 */ - USB_EP_t EP2IN; /* Endpoint 2 */ - USB_EP_t EP3OUT; /* Endpoint 3 */ - USB_EP_t EP3IN; /* Endpoint 3 */ - USB_EP_t EP4OUT; /* Endpoint 4 */ - USB_EP_t EP4IN; /* Endpoint 4 */ - USB_EP_t EP5OUT; /* Endpoint 5 */ - USB_EP_t EP5IN; /* Endpoint 5 */ - USB_EP_t EP6OUT; /* Endpoint 6 */ - USB_EP_t EP6IN; /* Endpoint 6 */ - USB_EP_t EP7OUT; /* Endpoint 7 */ - USB_EP_t EP7IN; /* Endpoint 7 */ - USB_EP_t EP8OUT; /* Endpoint 8 */ - USB_EP_t EP8IN; /* Endpoint 8 */ - USB_EP_t EP9OUT; /* Endpoint 9 */ - USB_EP_t EP9IN; /* Endpoint 9 */ - USB_EP_t EP10OUT; /* Endpoint 10 */ - USB_EP_t EP10IN; /* Endpoint 10 */ - USB_EP_t EP11OUT; /* Endpoint 11 */ - USB_EP_t EP11IN; /* Endpoint 11 */ - USB_EP_t EP12OUT; /* Endpoint 12 */ - USB_EP_t EP12IN; /* Endpoint 12 */ - USB_EP_t EP13OUT; /* Endpoint 13 */ - USB_EP_t EP13IN; /* Endpoint 13 */ - USB_EP_t EP14OUT; /* Endpoint 14 */ - USB_EP_t EP14IN; /* Endpoint 14 */ - USB_EP_t EP15OUT; /* Endpoint 15 */ - USB_EP_t EP15IN; /* Endpoint 15 */ - register8_t reserved_0x100; - register8_t reserved_0x101; - register8_t reserved_0x102; - register8_t reserved_0x103; - register8_t reserved_0x104; - register8_t reserved_0x105; - register8_t reserved_0x106; - register8_t reserved_0x107; - register8_t reserved_0x108; - register8_t reserved_0x109; - register8_t reserved_0x10A; - register8_t reserved_0x10B; - register8_t reserved_0x10C; - register8_t reserved_0x10D; - register8_t reserved_0x10E; - register8_t reserved_0x10F; - register8_t FRAMENUML; /* Frame Number Low Byte */ - register8_t FRAMENUMH; /* Frame Number High Byte */ -} USB_EP_TABLE_t; - -/* Interrupt level */ -typedef enum USB_INTLVL_enum -{ - USB_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ - USB_INTLVL_LO_gc = (0x01<<0), /* Low level */ - USB_INTLVL_MED_gc = (0x02<<0), /* Medium level */ - USB_INTLVL_HI_gc = (0x03<<0), /* High level */ -} USB_INTLVL_t; - -/* USB Endpoint Type */ -typedef enum USB_EP_TYPE_enum -{ - USB_EP_TYPE_DISABLE_gc = (0x00<<6), /* Endpoint Disabled */ - USB_EP_TYPE_CONTROL_gc = (0x01<<6), /* Control */ - USB_EP_TYPE_BULK_gc = (0x02<<6), /* Bulk/Interrupt */ - USB_EP_TYPE_ISOCHRONOUS_gc = (0x03<<6), /* Isochronous */ -} USB_EP_TYPE_t; - -/* USB Endpoint Buffersize */ -typedef enum USB_EP_BUFSIZE_enum -{ - USB_EP_BUFSIZE_8_gc = (0x00<<0), /* 8 bytes buffer size */ - USB_EP_BUFSIZE_16_gc = (0x01<<0), /* 16 bytes buffer size */ - USB_EP_BUFSIZE_32_gc = (0x02<<0), /* 32 bytes buffer size */ - USB_EP_BUFSIZE_64_gc = (0x03<<0), /* 64 bytes buffer size */ - USB_EP_BUFSIZE_128_gc = (0x04<<0), /* 128 bytes buffer size */ - USB_EP_BUFSIZE_256_gc = (0x05<<0), /* 256 bytes buffer size */ - USB_EP_BUFSIZE_512_gc = (0x06<<0), /* 512 bytes buffer size */ - USB_EP_BUFSIZE_1023_gc = (0x07<<0), /* 1023 bytes buffer size */ -} USB_EP_BUFSIZE_t; - - -/* --------------------------------------------------------------------------- -PORT - I/O Port Configuration --------------------------------------------------------------------------- -*/ - -/* I/O Ports */ -typedef struct PORT_struct -{ - register8_t DIR; /* I/O Port Data Direction */ - register8_t DIRSET; /* I/O Port Data Direction Set */ - register8_t DIRCLR; /* I/O Port Data Direction Clear */ - register8_t DIRTGL; /* I/O Port Data Direction Toggle */ - register8_t OUT; /* I/O Port Output */ - register8_t OUTSET; /* I/O Port Output Set */ - register8_t OUTCLR; /* I/O Port Output Clear */ - register8_t OUTTGL; /* I/O Port Output Toggle */ - register8_t IN; /* I/O port Input */ - register8_t INTCTRL; /* Interrupt Control Register */ - register8_t INT0MASK; /* Port Interrupt 0 Mask */ - register8_t INT1MASK; /* Port Interrupt 1 Mask */ - register8_t INTFLAGS; /* Interrupt Flag Register */ - register8_t reserved_0x0D; - register8_t REMAP; /* I/O Port Pin Remap Register */ - register8_t reserved_0x0F; - register8_t PIN0CTRL; /* Pin 0 Control Register */ - register8_t PIN1CTRL; /* Pin 1 Control Register */ - register8_t PIN2CTRL; /* Pin 2 Control Register */ - register8_t PIN3CTRL; /* Pin 3 Control Register */ - register8_t PIN4CTRL; /* Pin 4 Control Register */ - register8_t PIN5CTRL; /* Pin 5 Control Register */ - register8_t PIN6CTRL; /* Pin 6 Control Register */ - register8_t PIN7CTRL; /* Pin 7 Control Register */ -} PORT_t; - -/* Port Interrupt 0 Level */ -typedef enum PORT_INT0LVL_enum -{ - PORT_INT0LVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - PORT_INT0LVL_LO_gc = (0x01<<0), /* Low Level */ - PORT_INT0LVL_MED_gc = (0x02<<0), /* Medium Level */ - PORT_INT0LVL_HI_gc = (0x03<<0), /* High Level */ -} PORT_INT0LVL_t; - -/* Port Interrupt 1 Level */ -typedef enum PORT_INT1LVL_enum -{ - PORT_INT1LVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ - PORT_INT1LVL_LO_gc = (0x01<<2), /* Low Level */ - PORT_INT1LVL_MED_gc = (0x02<<2), /* Medium Level */ - PORT_INT1LVL_HI_gc = (0x03<<2), /* High Level */ -} PORT_INT1LVL_t; - -/* Output/Pull Configuration */ -typedef enum PORT_OPC_enum -{ - PORT_OPC_TOTEM_gc = (0x00<<3), /* Totempole */ - PORT_OPC_BUSKEEPER_gc = (0x01<<3), /* Totempole w/ Bus keeper on Input and Output */ - PORT_OPC_PULLDOWN_gc = (0x02<<3), /* Totempole w/ Pull-down on Input */ - PORT_OPC_PULLUP_gc = (0x03<<3), /* Totempole w/ Pull-up on Input */ - PORT_OPC_WIREDOR_gc = (0x04<<3), /* Wired OR */ - PORT_OPC_WIREDAND_gc = (0x05<<3), /* Wired AND */ - PORT_OPC_WIREDORPULL_gc = (0x06<<3), /* Wired OR w/ Pull-down */ - PORT_OPC_WIREDANDPULL_gc = (0x07<<3), /* Wired AND w/ Pull-up */ -} PORT_OPC_t; - -/* Input/Sense Configuration */ -typedef enum PORT_ISC_enum -{ - PORT_ISC_BOTHEDGES_gc = (0x00<<0), /* Sense Both Edges */ - PORT_ISC_RISING_gc = (0x01<<0), /* Sense Rising Edge */ - PORT_ISC_FALLING_gc = (0x02<<0), /* Sense Falling Edge */ - PORT_ISC_LEVEL_gc = (0x03<<0), /* Sense Level (Transparent For Events) */ - PORT_ISC_INPUT_DISABLE_gc = (0x07<<0), /* Disable Digital Input Buffer */ -} PORT_ISC_t; - - -/* --------------------------------------------------------------------------- -TC - 16-bit Timer/Counter With PWM --------------------------------------------------------------------------- -*/ - -/* 16-bit Timer/Counter 0 */ -typedef struct TC0_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t CTRLC; /* Control register C */ - register8_t CTRLD; /* Control Register D */ - register8_t CTRLE; /* Control Register E */ - register8_t reserved_0x05; - register8_t INTCTRLA; /* Interrupt Control Register A */ - register8_t INTCTRLB; /* Interrupt Control Register B */ - register8_t CTRLFCLR; /* Control Register F Clear */ - register8_t CTRLFSET; /* Control Register F Set */ - register8_t CTRLGCLR; /* Control Register G Clear */ - register8_t CTRLGSET; /* Control Register G Set */ - register8_t INTFLAGS; /* Interrupt Flag Register */ - register8_t reserved_0x0D; - register8_t reserved_0x0E; - register8_t TEMP; /* Temporary Register For 16-bit Access */ - register8_t reserved_0x10; - register8_t reserved_0x11; - register8_t reserved_0x12; - register8_t reserved_0x13; - register8_t reserved_0x14; - register8_t reserved_0x15; - register8_t reserved_0x16; - register8_t reserved_0x17; - register8_t reserved_0x18; - register8_t reserved_0x19; - register8_t reserved_0x1A; - register8_t reserved_0x1B; - register8_t reserved_0x1C; - register8_t reserved_0x1D; - register8_t reserved_0x1E; - register8_t reserved_0x1F; - _WORDREGISTER(CNT); /* Count */ - register8_t reserved_0x22; - register8_t reserved_0x23; - register8_t reserved_0x24; - register8_t reserved_0x25; - _WORDREGISTER(PER); /* Period */ - _WORDREGISTER(CCA); /* Compare or Capture A */ - _WORDREGISTER(CCB); /* Compare or Capture B */ - _WORDREGISTER(CCC); /* Compare or Capture C */ - _WORDREGISTER(CCD); /* Compare or Capture D */ - register8_t reserved_0x30; - register8_t reserved_0x31; - register8_t reserved_0x32; - register8_t reserved_0x33; - register8_t reserved_0x34; - register8_t reserved_0x35; - _WORDREGISTER(PERBUF); /* Period Buffer */ - _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ - _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ - _WORDREGISTER(CCCBUF); /* Compare Or Capture C Buffer */ - _WORDREGISTER(CCDBUF); /* Compare Or Capture D Buffer */ -} TC0_t; - - -/* 16-bit Timer/Counter 1 */ -typedef struct TC1_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t CTRLC; /* Control register C */ - register8_t CTRLD; /* Control Register D */ - register8_t CTRLE; /* Control Register E */ - register8_t reserved_0x05; - register8_t INTCTRLA; /* Interrupt Control Register A */ - register8_t INTCTRLB; /* Interrupt Control Register B */ - register8_t CTRLFCLR; /* Control Register F Clear */ - register8_t CTRLFSET; /* Control Register F Set */ - register8_t CTRLGCLR; /* Control Register G Clear */ - register8_t CTRLGSET; /* Control Register G Set */ - register8_t INTFLAGS; /* Interrupt Flag Register */ - register8_t reserved_0x0D; - register8_t reserved_0x0E; - register8_t TEMP; /* Temporary Register For 16-bit Access */ - register8_t reserved_0x10; - register8_t reserved_0x11; - register8_t reserved_0x12; - register8_t reserved_0x13; - register8_t reserved_0x14; - register8_t reserved_0x15; - register8_t reserved_0x16; - register8_t reserved_0x17; - register8_t reserved_0x18; - register8_t reserved_0x19; - register8_t reserved_0x1A; - register8_t reserved_0x1B; - register8_t reserved_0x1C; - register8_t reserved_0x1D; - register8_t reserved_0x1E; - register8_t reserved_0x1F; - _WORDREGISTER(CNT); /* Count */ - register8_t reserved_0x22; - register8_t reserved_0x23; - register8_t reserved_0x24; - register8_t reserved_0x25; - _WORDREGISTER(PER); /* Period */ - _WORDREGISTER(CCA); /* Compare or Capture A */ - _WORDREGISTER(CCB); /* Compare or Capture B */ - register8_t reserved_0x2C; - register8_t reserved_0x2D; - register8_t reserved_0x2E; - register8_t reserved_0x2F; - register8_t reserved_0x30; - register8_t reserved_0x31; - register8_t reserved_0x32; - register8_t reserved_0x33; - register8_t reserved_0x34; - register8_t reserved_0x35; - _WORDREGISTER(PERBUF); /* Period Buffer */ - _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ - _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ -} TC1_t; - -/* Clock Selection */ -typedef enum TC_CLKSEL_enum -{ - TC_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */ - TC_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */ - TC_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */ - TC_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */ - TC_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */ - TC_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */ - TC_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */ - TC_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */ - TC_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */ - TC_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */ - TC_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */ - TC_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */ - TC_CLKSEL_EVCH4_gc = (0x0C<<0), /* Event Channel 4 */ - TC_CLKSEL_EVCH5_gc = (0x0D<<0), /* Event Channel 5 */ - TC_CLKSEL_EVCH6_gc = (0x0E<<0), /* Event Channel 6 */ - TC_CLKSEL_EVCH7_gc = (0x0F<<0), /* Event Channel 7 */ -} TC_CLKSEL_t; - -/* Waveform Generation Mode */ -typedef enum TC_WGMODE_enum -{ - TC_WGMODE_NORMAL_gc = (0x00<<0), /* Normal Mode */ - TC_WGMODE_FRQ_gc = (0x01<<0), /* Frequency Generation Mode */ - TC_WGMODE_SINGLESLOPE_gc = (0x03<<0), /* Single Slope */ - TC_WGMODE_SS_gc = (0x03<<0), /* Single Slope */ - TC_WGMODE_DSTOP_gc = (0x05<<0), /* Dual Slope, Update on TOP */ - TC_WGMODE_DS_T_gc = (0x05<<0), /* Dual Slope, Update on TOP */ - TC_WGMODE_DSBOTH_gc = (0x06<<0), /* Dual Slope, Update on both TOP and BOTTOM */ - TC_WGMODE_DS_TB_gc = (0x06<<0), /* Dual Slope, Update on both TOP and BOTTOM */ - TC_WGMODE_DSBOTTOM_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */ - TC_WGMODE_DS_B_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */ -} TC_WGMODE_t; - -/* Byte Mode */ -typedef enum TC_BYTEM_enum -{ - TC_BYTEM_NORMAL_gc = (0x00<<0), /* 16-bit mode */ - TC_BYTEM_BYTEMODE_gc = (0x01<<0), /* Timer/Counter operating in byte mode only */ - TC_BYTEM_SPLITMODE_gc = (0x02<<0), /* Timer/Counter split into two 8-bit Counters (TC2) */ -} TC_BYTEM_t; - -/* Event Action */ -typedef enum TC_EVACT_enum -{ - TC_EVACT_OFF_gc = (0x00<<5), /* No Event Action */ - TC_EVACT_CAPT_gc = (0x01<<5), /* Input Capture */ - TC_EVACT_UPDOWN_gc = (0x02<<5), /* Externally Controlled Up/Down Count */ - TC_EVACT_QDEC_gc = (0x03<<5), /* Quadrature Decode */ - TC_EVACT_RESTART_gc = (0x04<<5), /* Restart */ - TC_EVACT_FRQ_gc = (0x05<<5), /* Frequency Capture */ - TC_EVACT_PW_gc = (0x06<<5), /* Pulse-width Capture */ -} TC_EVACT_t; - -/* Event Selection */ -typedef enum TC_EVSEL_enum -{ - TC_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ - TC_EVSEL_CH0_gc = (0x08<<0), /* Event Channel 0 */ - TC_EVSEL_CH1_gc = (0x09<<0), /* Event Channel 1 */ - TC_EVSEL_CH2_gc = (0x0A<<0), /* Event Channel 2 */ - TC_EVSEL_CH3_gc = (0x0B<<0), /* Event Channel 3 */ - TC_EVSEL_CH4_gc = (0x0C<<0), /* Event Channel 4 */ - TC_EVSEL_CH5_gc = (0x0D<<0), /* Event Channel 5 */ - TC_EVSEL_CH6_gc = (0x0E<<0), /* Event Channel 6 */ - TC_EVSEL_CH7_gc = (0x0F<<0), /* Event Channel 7 */ -} TC_EVSEL_t; - -/* Error Interrupt Level */ -typedef enum TC_ERRINTLVL_enum -{ - TC_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ - TC_ERRINTLVL_LO_gc = (0x01<<2), /* Low Level */ - TC_ERRINTLVL_MED_gc = (0x02<<2), /* Medium Level */ - TC_ERRINTLVL_HI_gc = (0x03<<2), /* High Level */ -} TC_ERRINTLVL_t; - -/* Overflow Interrupt Level */ -typedef enum TC_OVFINTLVL_enum -{ - TC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - TC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ - TC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ - TC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ -} TC_OVFINTLVL_t; - -/* Compare or Capture D Interrupt Level */ -typedef enum TC_CCDINTLVL_enum -{ - TC_CCDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ - TC_CCDINTLVL_LO_gc = (0x01<<6), /* Low Level */ - TC_CCDINTLVL_MED_gc = (0x02<<6), /* Medium Level */ - TC_CCDINTLVL_HI_gc = (0x03<<6), /* High Level */ -} TC_CCDINTLVL_t; - -/* Compare or Capture C Interrupt Level */ -typedef enum TC_CCCINTLVL_enum -{ - TC_CCCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ - TC_CCCINTLVL_LO_gc = (0x01<<4), /* Low Level */ - TC_CCCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ - TC_CCCINTLVL_HI_gc = (0x03<<4), /* High Level */ -} TC_CCCINTLVL_t; - -/* Compare or Capture B Interrupt Level */ -typedef enum TC_CCBINTLVL_enum -{ - TC_CCBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ - TC_CCBINTLVL_LO_gc = (0x01<<2), /* Low Level */ - TC_CCBINTLVL_MED_gc = (0x02<<2), /* Medium Level */ - TC_CCBINTLVL_HI_gc = (0x03<<2), /* High Level */ -} TC_CCBINTLVL_t; - -/* Compare or Capture A Interrupt Level */ -typedef enum TC_CCAINTLVL_enum -{ - TC_CCAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - TC_CCAINTLVL_LO_gc = (0x01<<0), /* Low Level */ - TC_CCAINTLVL_MED_gc = (0x02<<0), /* Medium Level */ - TC_CCAINTLVL_HI_gc = (0x03<<0), /* High Level */ -} TC_CCAINTLVL_t; - -/* Timer/Counter Command */ -typedef enum TC_CMD_enum -{ - TC_CMD_NONE_gc = (0x00<<2), /* No Command */ - TC_CMD_UPDATE_gc = (0x01<<2), /* Force Update */ - TC_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ - TC_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ -} TC_CMD_t; - - -/* --------------------------------------------------------------------------- -TC2 - 16-bit Timer/Counter type 2 --------------------------------------------------------------------------- -*/ - -/* 16-bit Timer/Counter type 2 */ -typedef struct TC2_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t CTRLC; /* Control register C */ - register8_t reserved_0x03; - register8_t CTRLE; /* Control Register E */ - register8_t reserved_0x05; - register8_t INTCTRLA; /* Interrupt Control Register A */ - register8_t INTCTRLB; /* Interrupt Control Register B */ - register8_t reserved_0x08; - register8_t CTRLF; /* Control Register F */ - register8_t reserved_0x0A; - register8_t reserved_0x0B; - register8_t INTFLAGS; /* Interrupt Flag Register */ - register8_t reserved_0x0D; - register8_t reserved_0x0E; - register8_t reserved_0x0F; - register8_t reserved_0x10; - register8_t reserved_0x11; - register8_t reserved_0x12; - register8_t reserved_0x13; - register8_t reserved_0x14; - register8_t reserved_0x15; - register8_t reserved_0x16; - register8_t reserved_0x17; - register8_t reserved_0x18; - register8_t reserved_0x19; - register8_t reserved_0x1A; - register8_t reserved_0x1B; - register8_t reserved_0x1C; - register8_t reserved_0x1D; - register8_t reserved_0x1E; - register8_t reserved_0x1F; - register8_t LCNT; /* Low Byte Count */ - register8_t HCNT; /* High Byte Count */ - register8_t reserved_0x22; - register8_t reserved_0x23; - register8_t reserved_0x24; - register8_t reserved_0x25; - register8_t LPER; /* Low Byte Period */ - register8_t HPER; /* High Byte Period */ - register8_t LCMPA; /* Low Byte Compare A */ - register8_t HCMPA; /* High Byte Compare A */ - register8_t LCMPB; /* Low Byte Compare B */ - register8_t HCMPB; /* High Byte Compare B */ - register8_t LCMPC; /* Low Byte Compare C */ - register8_t HCMPC; /* High Byte Compare C */ - register8_t LCMPD; /* Low Byte Compare D */ - register8_t HCMPD; /* High Byte Compare D */ -} TC2_t; - -/* Clock Selection */ -typedef enum TC2_CLKSEL_enum -{ - TC2_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */ - TC2_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */ - TC2_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */ - TC2_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */ - TC2_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */ - TC2_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */ - TC2_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */ - TC2_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */ - TC2_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */ - TC2_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */ - TC2_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */ - TC2_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */ - TC2_CLKSEL_EVCH4_gc = (0x0C<<0), /* Event Channel 4 */ - TC2_CLKSEL_EVCH5_gc = (0x0D<<0), /* Event Channel 5 */ - TC2_CLKSEL_EVCH6_gc = (0x0E<<0), /* Event Channel 6 */ - TC2_CLKSEL_EVCH7_gc = (0x0F<<0), /* Event Channel 7 */ -} TC2_CLKSEL_t; - -/* Byte Mode */ -typedef enum TC2_BYTEM_enum -{ - TC2_BYTEM_NORMAL_gc = (0x00<<0), /* 16-bit mode */ - TC2_BYTEM_BYTEMODE_gc = (0x01<<0), /* Timer/Counter operating in byte mode only (TC2) */ - TC2_BYTEM_SPLITMODE_gc = (0x02<<0), /* Timer/Counter split into two 8-bit Counters */ -} TC2_BYTEM_t; - -/* High Byte Underflow Interrupt Level */ -typedef enum TC2_HUNFINTLVL_enum -{ - TC2_HUNFINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ - TC2_HUNFINTLVL_LO_gc = (0x01<<2), /* Low Level */ - TC2_HUNFINTLVL_MED_gc = (0x02<<2), /* Medium Level */ - TC2_HUNFINTLVL_HI_gc = (0x03<<2), /* High Level */ -} TC2_HUNFINTLVL_t; - -/* Low Byte Underflow Interrupt Level */ -typedef enum TC2_LUNFINTLVL_enum -{ - TC2_LUNFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - TC2_LUNFINTLVL_LO_gc = (0x01<<0), /* Low Level */ - TC2_LUNFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ - TC2_LUNFINTLVL_HI_gc = (0x03<<0), /* High Level */ -} TC2_LUNFINTLVL_t; - -/* Low Byte Compare D Interrupt Level */ -typedef enum TC2_LCMPDINTLVL_enum -{ - TC2_LCMPDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ - TC2_LCMPDINTLVL_LO_gc = (0x01<<6), /* Low Level */ - TC2_LCMPDINTLVL_MED_gc = (0x02<<6), /* Medium Level */ - TC2_LCMPDINTLVL_HI_gc = (0x03<<6), /* High Level */ -} TC2_LCMPDINTLVL_t; - -/* Low Byte Compare C Interrupt Level */ -typedef enum TC2_LCMPCINTLVL_enum -{ - TC2_LCMPCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ - TC2_LCMPCINTLVL_LO_gc = (0x01<<4), /* Low Level */ - TC2_LCMPCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ - TC2_LCMPCINTLVL_HI_gc = (0x03<<4), /* High Level */ -} TC2_LCMPCINTLVL_t; - -/* Low Byte Compare B Interrupt Level */ -typedef enum TC2_LCMPBINTLVL_enum -{ - TC2_LCMPBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ - TC2_LCMPBINTLVL_LO_gc = (0x01<<2), /* Low Level */ - TC2_LCMPBINTLVL_MED_gc = (0x02<<2), /* Medium Level */ - TC2_LCMPBINTLVL_HI_gc = (0x03<<2), /* High Level */ -} TC2_LCMPBINTLVL_t; - -/* Low Byte Compare A Interrupt Level */ -typedef enum TC2_LCMPAINTLVL_enum -{ - TC2_LCMPAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - TC2_LCMPAINTLVL_LO_gc = (0x01<<0), /* Low Level */ - TC2_LCMPAINTLVL_MED_gc = (0x02<<0), /* Medium Level */ - TC2_LCMPAINTLVL_HI_gc = (0x03<<0), /* High Level */ -} TC2_LCMPAINTLVL_t; - -/* Timer/Counter Command */ -typedef enum TC2_CMD_enum -{ - TC2_CMD_NONE_gc = (0x00<<2), /* No Command */ - TC2_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ - TC2_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ -} TC2_CMD_t; - -/* Timer/Counter Command */ -typedef enum TC2_CMDEN_enum -{ - TC2_CMDEN_LOW_gc = (0x01<<0), /* Low Byte Timer/Counter */ - TC2_CMDEN_HIGH_gc = (0x02<<0), /* High Byte Timer/Counter */ - TC2_CMDEN_BOTH_gc = (0x03<<0), /* Both Low Byte and High Byte Timer/Counters */ -} TC2_CMDEN_t; - - -/* --------------------------------------------------------------------------- -AWEX - Timer/Counter Advanced Waveform Extension --------------------------------------------------------------------------- -*/ - -/* Advanced Waveform Extension */ -typedef struct AWEX_struct -{ - register8_t CTRL; /* Control Register */ - register8_t reserved_0x01; - register8_t FDEMASK; /* Fault Detection Event Mask */ - register8_t FDCTRL; /* Fault Detection Control Register */ - register8_t STATUS; /* Status Register */ - register8_t STATUSSET; /* Status Set Register */ - register8_t DTBOTH; /* Dead Time Both Sides */ - register8_t DTBOTHBUF; /* Dead Time Both Sides Buffer */ - register8_t DTLS; /* Dead Time Low Side */ - register8_t DTHS; /* Dead Time High Side */ - register8_t DTLSBUF; /* Dead Time Low Side Buffer */ - register8_t DTHSBUF; /* Dead Time High Side Buffer */ - register8_t OUTOVEN; /* Output Override Enable */ -} AWEX_t; - -/* Fault Detect Action */ -typedef enum AWEX_FDACT_enum -{ - AWEX_FDACT_NONE_gc = (0x00<<0), /* No Fault Protection */ - AWEX_FDACT_CLEAROE_gc = (0x01<<0), /* Clear Output Enable Bits */ - AWEX_FDACT_CLEARDIR_gc = (0x03<<0), /* Clear I/O Port Direction Bits */ -} AWEX_FDACT_t; - - -/* --------------------------------------------------------------------------- -HIRES - Timer/Counter High-Resolution Extension --------------------------------------------------------------------------- -*/ - -/* High-Resolution Extension */ -typedef struct HIRES_struct -{ - register8_t CTRLA; /* Control Register */ -} HIRES_t; - -/* High Resolution Enable */ -typedef enum HIRES_HREN_enum -{ - HIRES_HREN_NONE_gc = (0x00<<0), /* No Fault Protection */ - HIRES_HREN_TC0_gc = (0x01<<0), /* Enable High Resolution on Timer/Counter 0 */ - HIRES_HREN_TC1_gc = (0x02<<0), /* Enable High Resolution on Timer/Counter 1 */ - HIRES_HREN_BOTH_gc = (0x03<<0), /* Enable High Resolution both Timer/Counters */ -} HIRES_HREN_t; - - -/* --------------------------------------------------------------------------- -USART - Universal Asynchronous Receiver-Transmitter --------------------------------------------------------------------------- -*/ - -/* Universal Synchronous/Asynchronous Receiver/Transmitter */ -typedef struct USART_struct -{ - register8_t DATA; /* Data Register */ - register8_t STATUS; /* Status Register */ - register8_t reserved_0x02; - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t CTRLC; /* Control Register C */ - register8_t BAUDCTRLA; /* Baud Rate Control Register A */ - register8_t BAUDCTRLB; /* Baud Rate Control Register B */ -} USART_t; - -/* Receive Complete Interrupt level */ -typedef enum USART_RXCINTLVL_enum -{ - USART_RXCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ - USART_RXCINTLVL_LO_gc = (0x01<<4), /* Low Level */ - USART_RXCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ - USART_RXCINTLVL_HI_gc = (0x03<<4), /* High Level */ -} USART_RXCINTLVL_t; - -/* Transmit Complete Interrupt level */ -typedef enum USART_TXCINTLVL_enum -{ - USART_TXCINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ - USART_TXCINTLVL_LO_gc = (0x01<<2), /* Low Level */ - USART_TXCINTLVL_MED_gc = (0x02<<2), /* Medium Level */ - USART_TXCINTLVL_HI_gc = (0x03<<2), /* High Level */ -} USART_TXCINTLVL_t; - -/* Data Register Empty Interrupt level */ -typedef enum USART_DREINTLVL_enum -{ - USART_DREINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - USART_DREINTLVL_LO_gc = (0x01<<0), /* Low Level */ - USART_DREINTLVL_MED_gc = (0x02<<0), /* Medium Level */ - USART_DREINTLVL_HI_gc = (0x03<<0), /* High Level */ -} USART_DREINTLVL_t; - -/* Character Size */ -typedef enum USART_CHSIZE_enum -{ - USART_CHSIZE_5BIT_gc = (0x00<<0), /* Character size: 5 bit */ - USART_CHSIZE_6BIT_gc = (0x01<<0), /* Character size: 6 bit */ - USART_CHSIZE_7BIT_gc = (0x02<<0), /* Character size: 7 bit */ - USART_CHSIZE_8BIT_gc = (0x03<<0), /* Character size: 8 bit */ - USART_CHSIZE_9BIT_gc = (0x07<<0), /* Character size: 9 bit */ -} USART_CHSIZE_t; - -/* Communication Mode */ -typedef enum USART_CMODE_enum -{ - USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6), /* Asynchronous Mode */ - USART_CMODE_SYNCHRONOUS_gc = (0x01<<6), /* Synchronous Mode */ - USART_CMODE_IRDA_gc = (0x02<<6), /* IrDA Mode */ - USART_CMODE_MSPI_gc = (0x03<<6), /* Master SPI Mode */ -} USART_CMODE_t; - -/* Parity Mode */ -typedef enum USART_PMODE_enum -{ - USART_PMODE_DISABLED_gc = (0x00<<4), /* No Parity */ - USART_PMODE_EVEN_gc = (0x02<<4), /* Even Parity */ - USART_PMODE_ODD_gc = (0x03<<4), /* Odd Parity */ -} USART_PMODE_t; - - -/* --------------------------------------------------------------------------- -SPI - Serial Peripheral Interface --------------------------------------------------------------------------- -*/ - -/* Serial Peripheral Interface */ -typedef struct SPI_struct -{ - register8_t CTRL; /* Control Register */ - register8_t INTCTRL; /* Interrupt Control Register */ - register8_t STATUS; /* Status Register */ - register8_t DATA; /* Data Register */ -} SPI_t; - -/* SPI Mode */ -typedef enum SPI_MODE_enum -{ - SPI_MODE_0_gc = (0x00<<2), /* SPI Mode 0 */ - SPI_MODE_1_gc = (0x01<<2), /* SPI Mode 1 */ - SPI_MODE_2_gc = (0x02<<2), /* SPI Mode 2 */ - SPI_MODE_3_gc = (0x03<<2), /* SPI Mode 3 */ -} SPI_MODE_t; - -/* Prescaler setting */ -typedef enum SPI_PRESCALER_enum -{ - SPI_PRESCALER_DIV4_gc = (0x00<<0), /* System Clock / 4 */ - SPI_PRESCALER_DIV16_gc = (0x01<<0), /* System Clock / 16 */ - SPI_PRESCALER_DIV64_gc = (0x02<<0), /* System Clock / 64 */ - SPI_PRESCALER_DIV128_gc = (0x03<<0), /* System Clock / 128 */ -} SPI_PRESCALER_t; - -/* Interrupt level */ -typedef enum SPI_INTLVL_enum -{ - SPI_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - SPI_INTLVL_LO_gc = (0x01<<0), /* Low Level */ - SPI_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ - SPI_INTLVL_HI_gc = (0x03<<0), /* High Level */ -} SPI_INTLVL_t; - - -/* --------------------------------------------------------------------------- -IRCOM - IR Communication Module --------------------------------------------------------------------------- -*/ - -/* IR Communication Module */ -typedef struct IRCOM_struct -{ - register8_t CTRL; /* Control Register */ - register8_t TXPLCTRL; /* IrDA Transmitter Pulse Length Control Register */ - register8_t RXPLCTRL; /* IrDA Receiver Pulse Length Control Register */ -} IRCOM_t; - -/* Event channel selection */ -typedef enum IRDA_EVSEL_enum -{ - IRDA_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ - IRDA_EVSEL_0_gc = (0x08<<0), /* Event Channel 0 */ - IRDA_EVSEL_1_gc = (0x09<<0), /* Event Channel 1 */ - IRDA_EVSEL_2_gc = (0x0A<<0), /* Event Channel 2 */ - IRDA_EVSEL_3_gc = (0x0B<<0), /* Event Channel 3 */ - IRDA_EVSEL_4_gc = (0x0C<<0), /* Event Channel 4 */ - IRDA_EVSEL_5_gc = (0x0D<<0), /* Event Channel 5 */ - IRDA_EVSEL_6_gc = (0x0E<<0), /* Event Channel 6 */ - IRDA_EVSEL_7_gc = (0x0F<<0), /* Event Channel 7 */ -} IRDA_EVSEL_t; - - -/* --------------------------------------------------------------------------- -FUSE - Fuses and Lockbits --------------------------------------------------------------------------- -*/ - -/* Fuses */ -typedef struct NVM_FUSES_struct -{ - register8_t reserved_0x00; - register8_t FUSEBYTE1; /* Watchdog Configuration */ - register8_t FUSEBYTE2; /* Reset Configuration */ - register8_t reserved_0x03; - register8_t FUSEBYTE4; /* Start-up Configuration */ - register8_t FUSEBYTE5; /* EESAVE and BOD Level */ -} NVM_FUSES_t; - -/* Boot Loader Section Reset Vector */ -typedef enum BOOTRST_enum -{ - BOOTRST_BOOTLDR_gc = (0x00<<6), /* Boot Loader Reset */ - BOOTRST_APPLICATION_gc = (0x01<<6), /* Application Reset */ -} BOOTRST_t; - -/* Timer Oscillator pin location */ -typedef enum TOSCSEL_enum -{ - TOSCSEL_ALTERNATE_gc = (0x00<<5), /* TOSC1 / TOSC2 on separate pins */ - TOSCSEL_XTAL_gc = (0x01<<5), /* TOSC1 / TOSC2 shared with XTAL1 / XTAL2 */ -} TOSCSEL_t; - -/* BOD operation */ -typedef enum BOD_enum -{ - BOD_SAMPLED_gc = (0x01<<0), /* BOD enabled in sampled mode */ - BOD_CONTINUOUS_gc = (0x02<<0), /* BOD enabled continuously */ - BOD_DISABLED_gc = (0x03<<0), /* BOD Disabled */ -} BOD_t; - -/* BOD operation */ -typedef enum BODACT_enum -{ - BODACT_SAMPLED_gc = (0x01<<4), /* BOD enabled in sampled mode */ - BODACT_CONTINUOUS_gc = (0x02<<4), /* BOD enabled continuously */ - BODACT_DISABLED_gc = (0x03<<4), /* BOD Disabled */ -} BODACT_t; - -/* Watchdog (Window) Timeout Period */ -typedef enum WD_enum -{ - WD_8CLK_gc = (0x00<<4), /* 8 cycles (8ms @ 3.3V) */ - WD_16CLK_gc = (0x01<<4), /* 16 cycles (16ms @ 3.3V) */ - WD_32CLK_gc = (0x02<<4), /* 32 cycles (32ms @ 3.3V) */ - WD_64CLK_gc = (0x03<<4), /* 64 cycles (64ms @ 3.3V) */ - WD_128CLK_gc = (0x04<<4), /* 128 cycles (0.125s @ 3.3V) */ - WD_256CLK_gc = (0x05<<4), /* 256 cycles (0.25s @ 3.3V) */ - WD_512CLK_gc = (0x06<<4), /* 512 cycles (0.5s @ 3.3V) */ - WD_1KCLK_gc = (0x07<<4), /* 1K cycles (1s @ 3.3V) */ - WD_2KCLK_gc = (0x08<<4), /* 2K cycles (2s @ 3.3V) */ - WD_4KCLK_gc = (0x09<<4), /* 4K cycles (4s @ 3.3V) */ - WD_8KCLK_gc = (0x0A<<4), /* 8K cycles (8s @ 3.3V) */ -} WD_t; - -/* Watchdog (Window) Timeout Period */ -typedef enum WDP_enum -{ - WDP_8CLK_gc = (0x00<<0), /* 8 cycles (8ms @ 3.3V) */ - WDP_16CLK_gc = (0x01<<0), /* 16 cycles (16ms @ 3.3V) */ - WDP_32CLK_gc = (0x02<<0), /* 32 cycles (32ms @ 3.3V) */ - WDP_64CLK_gc = (0x03<<0), /* 64 cycles (64ms @ 3.3V) */ - WDP_128CLK_gc = (0x04<<0), /* 128 cycles (0.125s @ 3.3V) */ - WDP_256CLK_gc = (0x05<<0), /* 256 cycles (0.25s @ 3.3V) */ - WDP_512CLK_gc = (0x06<<0), /* 512 cycles (0.5s @ 3.3V) */ - WDP_1KCLK_gc = (0x07<<0), /* 1K cycles (1s @ 3.3V) */ - WDP_2KCLK_gc = (0x08<<0), /* 2K cycles (2s @ 3.3V) */ - WDP_4KCLK_gc = (0x09<<0), /* 4K cycles (4s @ 3.3V) */ - WDP_8KCLK_gc = (0x0A<<0), /* 8K cycles (8s @ 3.3V) */ -} WDP_t; - -/* Start-up Time */ -typedef enum SUT_enum -{ - SUT_0MS_gc = (0x03<<2), /* 0 ms */ - SUT_4MS_gc = (0x01<<2), /* 4 ms */ - SUT_64MS_gc = (0x00<<2), /* 64 ms */ -} SUT_t; - -/* Brownout Detection Voltage Level */ -typedef enum BODLVL_enum -{ - BODLVL_1V6_gc = (0x07<<0), /* 1.6 V */ - BODLVL_1V8_gc = (0x06<<0), /* 1.8 V */ - BODLVL_2V0_gc = (0x05<<0), /* 2.0 V */ - BODLVL_2V2_gc = (0x04<<0), /* 2.2 V */ - BODLVL_2V4_gc = (0x03<<0), /* 2.4 V */ - BODLVL_2V6_gc = (0x02<<0), /* 2.6 V */ - BODLVL_2V8_gc = (0x01<<0), /* 2.8 V */ - BODLVL_3V0_gc = (0x00<<0), /* 3.0 V */ -} BODLVL_t; - - -/* --------------------------------------------------------------------------- -LOCKBIT - Fuses and Lockbits --------------------------------------------------------------------------- -*/ - -/* Lock Bits */ -typedef struct NVM_LOCKBITS_struct -{ - register8_t LOCK_BITS; /* Lock Bits (Changed from LOCKBITS to avoid avr-libc collision) */ -} NVM_LOCKBITS_t; - -/* Boot lock bits - boot setcion */ -typedef enum FUSE_BLBB_enum -{ - FUSE_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ - FUSE_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ - FUSE_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ - FUSE_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ -} FUSE_BLBB_t; - -/* Boot lock bits - application section */ -typedef enum FUSE_BLBA_enum -{ - FUSE_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ - FUSE_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ - FUSE_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ - FUSE_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ -} FUSE_BLBA_t; - -/* Boot lock bits - application table section */ -typedef enum FUSE_BLBAT_enum -{ - FUSE_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ - FUSE_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ - FUSE_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ - FUSE_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ -} FUSE_BLBAT_t; - -/* Lock bits */ -typedef enum FUSE_LB_enum -{ - FUSE_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ - FUSE_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ - FUSE_LB_NOLOCK_gc = (0x03<<0), /* No locks */ -} FUSE_LB_t; - - -/* --------------------------------------------------------------------------- -SIGROW - Signature Row --------------------------------------------------------------------------- -*/ - -/* Production Signatures */ -typedef struct NVM_PROD_SIGNATURES_struct -{ - register8_t RCOSC2M; /* RCOSC 2 MHz Calibration Value B */ - register8_t RCOSC2MA; /* RCOSC 2 MHz Calibration Value A */ - register8_t RCOSC32K; /* RCOSC 32.768 kHz Calibration Value */ - register8_t RCOSC32M; /* RCOSC 32 MHz Calibration Value B */ - register8_t RCOSC32MA; /* RCOSC 32 MHz Calibration Value A */ - register8_t reserved_0x05; - register8_t reserved_0x06; - register8_t reserved_0x07; - register8_t LOTNUM0; /* Lot Number Byte 0, ASCII */ - register8_t LOTNUM1; /* Lot Number Byte 1, ASCII */ - register8_t LOTNUM2; /* Lot Number Byte 2, ASCII */ - register8_t LOTNUM3; /* Lot Number Byte 3, ASCII */ - register8_t LOTNUM4; /* Lot Number Byte 4, ASCII */ - register8_t LOTNUM5; /* Lot Number Byte 5, ASCII */ - register8_t reserved_0x0E; - register8_t reserved_0x0F; - register8_t WAFNUM; /* Wafer Number */ - register8_t reserved_0x11; - register8_t COORDX0; /* Wafer Coordinate X Byte 0 */ - register8_t COORDX1; /* Wafer Coordinate X Byte 1 */ - register8_t COORDY0; /* Wafer Coordinate Y Byte 0 */ - register8_t COORDY1; /* Wafer Coordinate Y Byte 1 */ - register8_t reserved_0x16; - register8_t reserved_0x17; - register8_t reserved_0x18; - register8_t reserved_0x19; - register8_t USBCAL0; /* USB Calibration Byte 0 */ - register8_t USBCAL1; /* USB Calibration Byte 1 */ - register8_t USBRCOSC; /* USB RCOSC Calibration Value B */ - register8_t USBRCOSCA; /* USB RCOSC Calibration Value A */ - register8_t reserved_0x1E; - register8_t reserved_0x1F; - register8_t ADCACAL0; /* ADCA Calibration Byte 0 */ - register8_t ADCACAL1; /* ADCA Calibration Byte 1 */ - register8_t reserved_0x22; - register8_t reserved_0x23; - register8_t ADCBCAL0; /* ADCB Calibration Byte 0 */ - register8_t ADCBCAL1; /* ADCB Calibration Byte 1 */ - register8_t reserved_0x26; - register8_t reserved_0x27; - register8_t reserved_0x28; - register8_t reserved_0x29; - register8_t reserved_0x2A; - register8_t reserved_0x2B; - register8_t reserved_0x2C; - register8_t reserved_0x2D; - register8_t TEMPSENSE0; /* Temperature Sensor Calibration Byte 0 */ - register8_t TEMPSENSE1; /* Temperature Sensor Calibration Byte 1 */ - register8_t DACA0OFFCAL; /* DACA0 Calibration Byte 0 */ - register8_t DACA0GAINCAL; /* DACA0 Calibration Byte 1 */ - register8_t DACB0OFFCAL; /* DACB0 Calibration Byte 0 */ - register8_t DACB0GAINCAL; /* DACB0 Calibration Byte 1 */ - register8_t DACA1OFFCAL; /* DACA1 Calibration Byte 0 */ - register8_t DACA1GAINCAL; /* DACA1 Calibration Byte 1 */ - register8_t DACB1OFFCAL; /* DACB1 Calibration Byte 0 */ - register8_t DACB1GAINCAL; /* DACB1 Calibration Byte 1 */ - register8_t reserved_0x38; - register8_t reserved_0x39; - register8_t reserved_0x3A; - register8_t reserved_0x3B; - register8_t reserved_0x3C; - register8_t reserved_0x3D; - register8_t reserved_0x3E; - register8_t reserved_0x3F; - register8_t reserved_0x40; - register8_t reserved_0x41; - register8_t reserved_0x42; - register8_t reserved_0x43; - register8_t reserved_0x44; - register8_t reserved_0x45; - register8_t reserved_0x46; - register8_t reserved_0x47; -} NVM_PROD_SIGNATURES_t; - -/* -========================================================================== -IO Module Instances. Mapped to memory. -========================================================================== -*/ - -#define VPORT0 (*(VPORT_t *) 0x0010) /* Virtual Port */ -#define VPORT1 (*(VPORT_t *) 0x0014) /* Virtual Port */ -#define VPORT2 (*(VPORT_t *) 0x0018) /* Virtual Port */ -#define VPORT3 (*(VPORT_t *) 0x001C) /* Virtual Port */ -#define OCD (*(OCD_t *) 0x002E) /* On-Chip Debug System */ -#define CLK (*(CLK_t *) 0x0040) /* Clock System */ -#define SLEEP (*(SLEEP_t *) 0x0048) /* Sleep Controller */ -#define OSC (*(OSC_t *) 0x0050) /* Oscillator */ -#define DFLLRC32M (*(DFLL_t *) 0x0060) /* DFLL */ -#define DFLLRC2M (*(DFLL_t *) 0x0068) /* DFLL */ -#define PR (*(PR_t *) 0x0070) /* Power Reduction */ -#define RST (*(RST_t *) 0x0078) /* Reset */ -#define WDT (*(WDT_t *) 0x0080) /* Watch-Dog Timer */ -#define MCU (*(MCU_t *) 0x0090) /* MCU Control */ -#define PMIC (*(PMIC_t *) 0x00A0) /* Programmable Multi-level Interrupt Controller */ -#define PORTCFG (*(PORTCFG_t *) 0x00B0) /* I/O port Configuration */ -#define AES (*(AES_t *) 0x00C0) /* AES Module */ -#define CRC (*(CRC_t *) 0x00D0) /* Cyclic Redundancy Checker */ -#define DMA (*(DMA_t *) 0x0100) /* DMA Controller */ -#define EVSYS (*(EVSYS_t *) 0x0180) /* Event System */ -#define NVM (*(NVM_t *) 0x01C0) /* Non-volatile Memory Controller */ -#define ADCA (*(ADC_t *) 0x0200) /* Analog-to-Digital Converter */ -#define DACB (*(DAC_t *) 0x0320) /* Digital-to-Analog Converter */ -#define ACA (*(AC_t *) 0x0380) /* Analog Comparator */ -#define RTC (*(RTC_t *) 0x0400) /* Real-Time Counter */ -#define TWIC (*(TWI_t *) 0x0480) /* Two-Wire Interface */ -#define TWIE (*(TWI_t *) 0x04A0) /* Two-Wire Interface */ -#define USB (*(USB_t *) 0x04C0) /* Universal Serial Bus */ -#define PORTA (*(PORT_t *) 0x0600) /* I/O Ports */ -#define PORTB (*(PORT_t *) 0x0620) /* I/O Ports */ -#define PORTC (*(PORT_t *) 0x0640) /* I/O Ports */ -#define PORTD (*(PORT_t *) 0x0660) /* I/O Ports */ -#define PORTE (*(PORT_t *) 0x0680) /* I/O Ports */ -#define PORTR (*(PORT_t *) 0x07E0) /* I/O Ports */ -#define TCC0 (*(TC0_t *) 0x0800) /* 16-bit Timer/Counter 0 */ -#define TCC2 (*(TC2_t *) 0x0800) /* 16-bit Timer/Counter type 2 */ -#define TCC1 (*(TC1_t *) 0x0840) /* 16-bit Timer/Counter 1 */ -#define AWEXC (*(AWEX_t *) 0x0880) /* Advanced Waveform Extension */ -#define HIRESC (*(HIRES_t *) 0x0890) /* High-Resolution Extension */ -#define USARTC0 (*(USART_t *) 0x08A0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ -#define USARTC1 (*(USART_t *) 0x08B0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ -#define SPIC (*(SPI_t *) 0x08C0) /* Serial Peripheral Interface */ -#define IRCOM (*(IRCOM_t *) 0x08F8) /* IR Communication Module */ -#define TCD0 (*(TC0_t *) 0x0900) /* 16-bit Timer/Counter 0 */ -#define TCD2 (*(TC2_t *) 0x0900) /* 16-bit Timer/Counter type 2 */ -#define TCD1 (*(TC1_t *) 0x0940) /* 16-bit Timer/Counter 1 */ -#define HIRESD (*(HIRES_t *) 0x0990) /* High-Resolution Extension */ -#define USARTD0 (*(USART_t *) 0x09A0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ -#define USARTD1 (*(USART_t *) 0x09B0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ -#define SPID (*(SPI_t *) 0x09C0) /* Serial Peripheral Interface */ -#define TCE0 (*(TC0_t *) 0x0A00) /* 16-bit Timer/Counter 0 */ -#define HIRESE (*(HIRES_t *) 0x0A90) /* High-Resolution Extension */ -#define USARTE0 (*(USART_t *) 0x0AA0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ - - -#endif /* !defined (__ASSEMBLER__) */ - - -/* ========== Flattened fully qualified IO register names ========== */ - -/* GPIO - General Purpose IO Registers */ -#define GPIO_GPIOR0 _SFR_MEM8(0x0000) -#define GPIO_GPIOR1 _SFR_MEM8(0x0001) -#define GPIO_GPIOR2 _SFR_MEM8(0x0002) -#define GPIO_GPIOR3 _SFR_MEM8(0x0003) -#define GPIO_GPIOR4 _SFR_MEM8(0x0004) -#define GPIO_GPIOR5 _SFR_MEM8(0x0005) -#define GPIO_GPIOR6 _SFR_MEM8(0x0006) -#define GPIO_GPIOR7 _SFR_MEM8(0x0007) -#define GPIO_GPIOR8 _SFR_MEM8(0x0008) -#define GPIO_GPIOR9 _SFR_MEM8(0x0009) -#define GPIO_GPIORA _SFR_MEM8(0x000A) -#define GPIO_GPIORB _SFR_MEM8(0x000B) -#define GPIO_GPIORC _SFR_MEM8(0x000C) -#define GPIO_GPIORD _SFR_MEM8(0x000D) -#define GPIO_GPIORE _SFR_MEM8(0x000E) -#define GPIO_GPIORF _SFR_MEM8(0x000F) - -/* Deprecated */ -#define GPIO_GPIO0 _SFR_MEM8(0x0000) -#define GPIO_GPIO1 _SFR_MEM8(0x0001) -#define GPIO_GPIO2 _SFR_MEM8(0x0002) -#define GPIO_GPIO3 _SFR_MEM8(0x0003) -#define GPIO_GPIO4 _SFR_MEM8(0x0004) -#define GPIO_GPIO5 _SFR_MEM8(0x0005) -#define GPIO_GPIO6 _SFR_MEM8(0x0006) -#define GPIO_GPIO7 _SFR_MEM8(0x0007) -#define GPIO_GPIO8 _SFR_MEM8(0x0008) -#define GPIO_GPIO9 _SFR_MEM8(0x0009) -#define GPIO_GPIOA _SFR_MEM8(0x000A) -#define GPIO_GPIOB _SFR_MEM8(0x000B) -#define GPIO_GPIOC _SFR_MEM8(0x000C) -#define GPIO_GPIOD _SFR_MEM8(0x000D) -#define GPIO_GPIOE _SFR_MEM8(0x000E) -#define GPIO_GPIOF _SFR_MEM8(0x000F) - -/* NVM_FUSES - Fuses */ -#define FUSE_FUSEBYTE1 _SFR_MEM8(0x0001) -#define FUSE_FUSEBYTE2 _SFR_MEM8(0x0002) -#define FUSE_FUSEBYTE4 _SFR_MEM8(0x0004) -#define FUSE_FUSEBYTE5 _SFR_MEM8(0x0005) - -/* NVM_LOCKBITS - Lock Bits */ -#define LOCKBIT_LOCKBITS _SFR_MEM8(0x0000) - -/* NVM_PROD_SIGNATURES - Production Signatures */ -#define PRODSIGNATURES_RCOSC2M _SFR_MEM8(0x0000) -#define PRODSIGNATURES_RCOSC2MA _SFR_MEM8(0x0001) -#define PRODSIGNATURES_RCOSC32K _SFR_MEM8(0x0002) -#define PRODSIGNATURES_RCOSC32M _SFR_MEM8(0x0003) -#define PRODSIGNATURES_RCOSC32MA _SFR_MEM8(0x0004) -#define PRODSIGNATURES_LOTNUM0 _SFR_MEM8(0x0008) -#define PRODSIGNATURES_LOTNUM1 _SFR_MEM8(0x0009) -#define PRODSIGNATURES_LOTNUM2 _SFR_MEM8(0x000A) -#define PRODSIGNATURES_LOTNUM3 _SFR_MEM8(0x000B) -#define PRODSIGNATURES_LOTNUM4 _SFR_MEM8(0x000C) -#define PRODSIGNATURES_LOTNUM5 _SFR_MEM8(0x000D) -#define PRODSIGNATURES_WAFNUM _SFR_MEM8(0x0010) -#define PRODSIGNATURES_COORDX0 _SFR_MEM8(0x0012) -#define PRODSIGNATURES_COORDX1 _SFR_MEM8(0x0013) -#define PRODSIGNATURES_COORDY0 _SFR_MEM8(0x0014) -#define PRODSIGNATURES_COORDY1 _SFR_MEM8(0x0015) -#define PRODSIGNATURES_USBCAL0 _SFR_MEM8(0x001A) -#define PRODSIGNATURES_USBCAL1 _SFR_MEM8(0x001B) -#define PRODSIGNATURES_USBRCOSC _SFR_MEM8(0x001C) -#define PRODSIGNATURES_USBRCOSCA _SFR_MEM8(0x001D) -#define PRODSIGNATURES_ADCACAL0 _SFR_MEM8(0x0020) -#define PRODSIGNATURES_ADCACAL1 _SFR_MEM8(0x0021) -#define PRODSIGNATURES_ADCBCAL0 _SFR_MEM8(0x0024) -#define PRODSIGNATURES_ADCBCAL1 _SFR_MEM8(0x0025) -#define PRODSIGNATURES_TEMPSENSE0 _SFR_MEM8(0x002E) -#define PRODSIGNATURES_TEMPSENSE1 _SFR_MEM8(0x002F) -#define PRODSIGNATURES_DACA0OFFCAL _SFR_MEM8(0x0030) -#define PRODSIGNATURES_DACA0GAINCAL _SFR_MEM8(0x0031) -#define PRODSIGNATURES_DACB0OFFCAL _SFR_MEM8(0x0032) -#define PRODSIGNATURES_DACB0GAINCAL _SFR_MEM8(0x0033) -#define PRODSIGNATURES_DACA1OFFCAL _SFR_MEM8(0x0034) -#define PRODSIGNATURES_DACA1GAINCAL _SFR_MEM8(0x0035) -#define PRODSIGNATURES_DACB1OFFCAL _SFR_MEM8(0x0036) -#define PRODSIGNATURES_DACB1GAINCAL _SFR_MEM8(0x0037) - -/* VPORT - Virtual Port */ -#define VPORT0_DIR _SFR_MEM8(0x0010) -#define VPORT0_OUT _SFR_MEM8(0x0011) -#define VPORT0_IN _SFR_MEM8(0x0012) -#define VPORT0_INTFLAGS _SFR_MEM8(0x0013) - -/* VPORT - Virtual Port */ -#define VPORT1_DIR _SFR_MEM8(0x0014) -#define VPORT1_OUT _SFR_MEM8(0x0015) -#define VPORT1_IN _SFR_MEM8(0x0016) -#define VPORT1_INTFLAGS _SFR_MEM8(0x0017) - -/* VPORT - Virtual Port */ -#define VPORT2_DIR _SFR_MEM8(0x0018) -#define VPORT2_OUT _SFR_MEM8(0x0019) -#define VPORT2_IN _SFR_MEM8(0x001A) -#define VPORT2_INTFLAGS _SFR_MEM8(0x001B) - -/* VPORT - Virtual Port */ -#define VPORT3_DIR _SFR_MEM8(0x001C) -#define VPORT3_OUT _SFR_MEM8(0x001D) -#define VPORT3_IN _SFR_MEM8(0x001E) -#define VPORT3_INTFLAGS _SFR_MEM8(0x001F) - -/* OCD - On-Chip Debug System */ -#define OCD_OCDR0 _SFR_MEM8(0x002E) -#define OCD_OCDR1 _SFR_MEM8(0x002F) - -/* CPU - CPU registers */ -#define CPU_CCP _SFR_MEM8(0x0034) -#define CPU_RAMPD _SFR_MEM8(0x0038) -#define CPU_RAMPX _SFR_MEM8(0x0039) -#define CPU_RAMPY _SFR_MEM8(0x003A) -#define CPU_RAMPZ _SFR_MEM8(0x003B) -#define CPU_EIND _SFR_MEM8(0x003C) -#define CPU_SPL _SFR_MEM8(0x003D) -#define CPU_SPH _SFR_MEM8(0x003E) -#define CPU_SREG _SFR_MEM8(0x003F) - -/* CLK - Clock System */ -#define CLK_CTRL _SFR_MEM8(0x0040) -#define CLK_PSCTRL _SFR_MEM8(0x0041) -#define CLK_LOCK _SFR_MEM8(0x0042) -#define CLK_RTCCTRL _SFR_MEM8(0x0043) -#define CLK_USBCTRL _SFR_MEM8(0x0044) - -/* SLEEP - Sleep Controller */ -#define SLEEP_CTRL _SFR_MEM8(0x0048) - -/* OSC - Oscillator */ -#define OSC_CTRL _SFR_MEM8(0x0050) -#define OSC_STATUS _SFR_MEM8(0x0051) -#define OSC_XOSCCTRL _SFR_MEM8(0x0052) -#define OSC_XOSCFAIL _SFR_MEM8(0x0053) -#define OSC_RC32KCAL _SFR_MEM8(0x0054) -#define OSC_PLLCTRL _SFR_MEM8(0x0055) -#define OSC_DFLLCTRL _SFR_MEM8(0x0056) - -/* DFLL - DFLL */ -#define DFLLRC32M_CTRL _SFR_MEM8(0x0060) -#define DFLLRC32M_CALA _SFR_MEM8(0x0062) -#define DFLLRC32M_CALB _SFR_MEM8(0x0063) -#define DFLLRC32M_COMP0 _SFR_MEM8(0x0064) -#define DFLLRC32M_COMP1 _SFR_MEM8(0x0065) -#define DFLLRC32M_COMP2 _SFR_MEM8(0x0066) - -/* DFLL - DFLL */ -#define DFLLRC2M_CTRL _SFR_MEM8(0x0068) -#define DFLLRC2M_CALA _SFR_MEM8(0x006A) -#define DFLLRC2M_CALB _SFR_MEM8(0x006B) -#define DFLLRC2M_COMP0 _SFR_MEM8(0x006C) -#define DFLLRC2M_COMP1 _SFR_MEM8(0x006D) -#define DFLLRC2M_COMP2 _SFR_MEM8(0x006E) - -/* PR - Power Reduction */ -#define PR_PRGEN _SFR_MEM8(0x0070) -#define PR_PRPA _SFR_MEM8(0x0071) -#define PR_PRPB _SFR_MEM8(0x0072) -#define PR_PRPC _SFR_MEM8(0x0073) -#define PR_PRPD _SFR_MEM8(0x0074) -#define PR_PRPE _SFR_MEM8(0x0075) -#define PR_PRPF _SFR_MEM8(0x0076) - -/* RST - Reset */ -#define RST_STATUS _SFR_MEM8(0x0078) -#define RST_CTRL _SFR_MEM8(0x0079) - -/* WDT - Watch-Dog Timer */ -#define WDT_CTRL _SFR_MEM8(0x0080) -#define WDT_WINCTRL _SFR_MEM8(0x0081) -#define WDT_STATUS _SFR_MEM8(0x0082) - -/* MCU - MCU Control */ -#define MCU_DEVID0 _SFR_MEM8(0x0090) -#define MCU_DEVID1 _SFR_MEM8(0x0091) -#define MCU_DEVID2 _SFR_MEM8(0x0092) -#define MCU_REVID _SFR_MEM8(0x0093) -#define MCU_JTAGUID _SFR_MEM8(0x0094) -#define MCU_MCUCR _SFR_MEM8(0x0096) -#define MCU_ANAINIT _SFR_MEM8(0x0097) -#define MCU_EVSYSLOCK _SFR_MEM8(0x0098) -#define MCU_AWEXLOCK _SFR_MEM8(0x0099) - -/* PMIC - Programmable Multi-level Interrupt Controller */ -#define PMIC_STATUS _SFR_MEM8(0x00A0) -#define PMIC_INTPRI _SFR_MEM8(0x00A1) -#define PMIC_CTRL _SFR_MEM8(0x00A2) - -/* PORTCFG - I/O port Configuration */ -#define PORTCFG_MPCMASK _SFR_MEM8(0x00B0) -#define PORTCFG_VPCTRLA _SFR_MEM8(0x00B2) -#define PORTCFG_VPCTRLB _SFR_MEM8(0x00B3) -#define PORTCFG_CLKEVOUT _SFR_MEM8(0x00B4) -#define PORTCFG_EBIOUT _SFR_MEM8(0x00B5) -#define PORTCFG_EVOUTSEL _SFR_MEM8(0x00B6) - -/* AES - AES Module */ -#define AES_CTRL _SFR_MEM8(0x00C0) -#define AES_STATUS _SFR_MEM8(0x00C1) -#define AES_STATE _SFR_MEM8(0x00C2) -#define AES_KEY _SFR_MEM8(0x00C3) -#define AES_INTCTRL _SFR_MEM8(0x00C4) - -/* CRC - Cyclic Redundancy Checker */ -#define CRC_CTRL _SFR_MEM8(0x00D0) -#define CRC_STATUS _SFR_MEM8(0x00D1) -#define CRC_DATAIN _SFR_MEM8(0x00D3) -#define CRC_CHECKSUM0 _SFR_MEM8(0x00D4) -#define CRC_CHECKSUM1 _SFR_MEM8(0x00D5) -#define CRC_CHECKSUM2 _SFR_MEM8(0x00D6) -#define CRC_CHECKSUM3 _SFR_MEM8(0x00D7) - -/* DMA - DMA Controller */ -#define DMA_CTRL _SFR_MEM8(0x0100) -#define DMA_INTFLAGS _SFR_MEM8(0x0103) -#define DMA_STATUS _SFR_MEM8(0x0104) -#define DMA_TEMP _SFR_MEM16(0x0106) -#define DMA_CH0_CTRLA _SFR_MEM8(0x0110) -#define DMA_CH0_CTRLB _SFR_MEM8(0x0111) -#define DMA_CH0_ADDRCTRL _SFR_MEM8(0x0112) -#define DMA_CH0_TRIGSRC _SFR_MEM8(0x0113) -#define DMA_CH0_TRFCNT _SFR_MEM16(0x0114) -#define DMA_CH0_REPCNT _SFR_MEM8(0x0116) -#define DMA_CH0_SRCADDR0 _SFR_MEM8(0x0118) -#define DMA_CH0_SRCADDR1 _SFR_MEM8(0x0119) -#define DMA_CH0_SRCADDR2 _SFR_MEM8(0x011A) -#define DMA_CH0_DESTADDR0 _SFR_MEM8(0x011C) -#define DMA_CH0_DESTADDR1 _SFR_MEM8(0x011D) -#define DMA_CH0_DESTADDR2 _SFR_MEM8(0x011E) -#define DMA_CH1_CTRLA _SFR_MEM8(0x0120) -#define DMA_CH1_CTRLB _SFR_MEM8(0x0121) -#define DMA_CH1_ADDRCTRL _SFR_MEM8(0x0122) -#define DMA_CH1_TRIGSRC _SFR_MEM8(0x0123) -#define DMA_CH1_TRFCNT _SFR_MEM16(0x0124) -#define DMA_CH1_REPCNT _SFR_MEM8(0x0126) -#define DMA_CH1_SRCADDR0 _SFR_MEM8(0x0128) -#define DMA_CH1_SRCADDR1 _SFR_MEM8(0x0129) -#define DMA_CH1_SRCADDR2 _SFR_MEM8(0x012A) -#define DMA_CH1_DESTADDR0 _SFR_MEM8(0x012C) -#define DMA_CH1_DESTADDR1 _SFR_MEM8(0x012D) -#define DMA_CH1_DESTADDR2 _SFR_MEM8(0x012E) -#define DMA_CH2_CTRLA _SFR_MEM8(0x0130) -#define DMA_CH2_CTRLB _SFR_MEM8(0x0131) -#define DMA_CH2_ADDRCTRL _SFR_MEM8(0x0132) -#define DMA_CH2_TRIGSRC _SFR_MEM8(0x0133) -#define DMA_CH2_TRFCNT _SFR_MEM16(0x0134) -#define DMA_CH2_REPCNT _SFR_MEM8(0x0136) -#define DMA_CH2_SRCADDR0 _SFR_MEM8(0x0138) -#define DMA_CH2_SRCADDR1 _SFR_MEM8(0x0139) -#define DMA_CH2_SRCADDR2 _SFR_MEM8(0x013A) -#define DMA_CH2_DESTADDR0 _SFR_MEM8(0x013C) -#define DMA_CH2_DESTADDR1 _SFR_MEM8(0x013D) -#define DMA_CH2_DESTADDR2 _SFR_MEM8(0x013E) -#define DMA_CH3_CTRLA _SFR_MEM8(0x0140) -#define DMA_CH3_CTRLB _SFR_MEM8(0x0141) -#define DMA_CH3_ADDRCTRL _SFR_MEM8(0x0142) -#define DMA_CH3_TRIGSRC _SFR_MEM8(0x0143) -#define DMA_CH3_TRFCNT _SFR_MEM16(0x0144) -#define DMA_CH3_REPCNT _SFR_MEM8(0x0146) -#define DMA_CH3_SRCADDR0 _SFR_MEM8(0x0148) -#define DMA_CH3_SRCADDR1 _SFR_MEM8(0x0149) -#define DMA_CH3_SRCADDR2 _SFR_MEM8(0x014A) -#define DMA_CH3_DESTADDR0 _SFR_MEM8(0x014C) -#define DMA_CH3_DESTADDR1 _SFR_MEM8(0x014D) -#define DMA_CH3_DESTADDR2 _SFR_MEM8(0x014E) - -/* EVSYS - Event System */ -#define EVSYS_CH0MUX _SFR_MEM8(0x0180) -#define EVSYS_CH1MUX _SFR_MEM8(0x0181) -#define EVSYS_CH2MUX _SFR_MEM8(0x0182) -#define EVSYS_CH3MUX _SFR_MEM8(0x0183) -#define EVSYS_CH4MUX _SFR_MEM8(0x0184) -#define EVSYS_CH5MUX _SFR_MEM8(0x0185) -#define EVSYS_CH6MUX _SFR_MEM8(0x0186) -#define EVSYS_CH7MUX _SFR_MEM8(0x0187) -#define EVSYS_CH0CTRL _SFR_MEM8(0x0188) -#define EVSYS_CH1CTRL _SFR_MEM8(0x0189) -#define EVSYS_CH2CTRL _SFR_MEM8(0x018A) -#define EVSYS_CH3CTRL _SFR_MEM8(0x018B) -#define EVSYS_CH4CTRL _SFR_MEM8(0x018C) -#define EVSYS_CH5CTRL _SFR_MEM8(0x018D) -#define EVSYS_CH6CTRL _SFR_MEM8(0x018E) -#define EVSYS_CH7CTRL _SFR_MEM8(0x018F) -#define EVSYS_STROBE _SFR_MEM8(0x0190) -#define EVSYS_DATA _SFR_MEM8(0x0191) - -/* NVM - Non-volatile Memory Controller */ -#define NVM_ADDR0 _SFR_MEM8(0x01C0) -#define NVM_ADDR1 _SFR_MEM8(0x01C1) -#define NVM_ADDR2 _SFR_MEM8(0x01C2) -#define NVM_DATA0 _SFR_MEM8(0x01C4) -#define NVM_DATA1 _SFR_MEM8(0x01C5) -#define NVM_DATA2 _SFR_MEM8(0x01C6) -#define NVM_CMD _SFR_MEM8(0x01CA) -#define NVM_CTRLA _SFR_MEM8(0x01CB) -#define NVM_CTRLB _SFR_MEM8(0x01CC) -#define NVM_INTCTRL _SFR_MEM8(0x01CD) -#define NVM_STATUS _SFR_MEM8(0x01CF) -#define NVM_LOCKBITS _SFR_MEM8(0x01D0) - -/* ADC - Analog-to-Digital Converter */ -#define ADCA_CTRLA _SFR_MEM8(0x0200) -#define ADCA_CTRLB _SFR_MEM8(0x0201) -#define ADCA_REFCTRL _SFR_MEM8(0x0202) -#define ADCA_EVCTRL _SFR_MEM8(0x0203) -#define ADCA_PRESCALER _SFR_MEM8(0x0204) -#define ADCA_INTFLAGS _SFR_MEM8(0x0206) -#define ADCA_TEMP _SFR_MEM8(0x0207) -#define ADCA_CAL _SFR_MEM16(0x020C) -#define ADCA_CH0RES _SFR_MEM16(0x0210) -#define ADCA_CH1RES _SFR_MEM16(0x0212) -#define ADCA_CH2RES _SFR_MEM16(0x0214) -#define ADCA_CH3RES _SFR_MEM16(0x0216) -#define ADCA_CMP _SFR_MEM16(0x0218) -#define ADCA_CH0_CTRL _SFR_MEM8(0x0220) -#define ADCA_CH0_MUXCTRL _SFR_MEM8(0x0221) -#define ADCA_CH0_INTCTRL _SFR_MEM8(0x0222) -#define ADCA_CH0_INTFLAGS _SFR_MEM8(0x0223) -#define ADCA_CH0_RES _SFR_MEM16(0x0224) -#define ADCA_CH0_SCAN _SFR_MEM8(0x0226) -#define ADCA_CH1_CTRL _SFR_MEM8(0x0228) -#define ADCA_CH1_MUXCTRL _SFR_MEM8(0x0229) -#define ADCA_CH1_INTCTRL _SFR_MEM8(0x022A) -#define ADCA_CH1_INTFLAGS _SFR_MEM8(0x022B) -#define ADCA_CH1_RES _SFR_MEM16(0x022C) -#define ADCA_CH1_SCAN _SFR_MEM8(0x022E) -#define ADCA_CH2_CTRL _SFR_MEM8(0x0230) -#define ADCA_CH2_MUXCTRL _SFR_MEM8(0x0231) -#define ADCA_CH2_INTCTRL _SFR_MEM8(0x0232) -#define ADCA_CH2_INTFLAGS _SFR_MEM8(0x0233) -#define ADCA_CH2_RES _SFR_MEM16(0x0234) -#define ADCA_CH2_SCAN _SFR_MEM8(0x0236) -#define ADCA_CH3_CTRL _SFR_MEM8(0x0238) -#define ADCA_CH3_MUXCTRL _SFR_MEM8(0x0239) -#define ADCA_CH3_INTCTRL _SFR_MEM8(0x023A) -#define ADCA_CH3_INTFLAGS _SFR_MEM8(0x023B) -#define ADCA_CH3_RES _SFR_MEM16(0x023C) -#define ADCA_CH3_SCAN _SFR_MEM8(0x023E) - -/* DAC - Digital-to-Analog Converter */ -#define DACB_CTRLA _SFR_MEM8(0x0320) -#define DACB_CTRLB _SFR_MEM8(0x0321) -#define DACB_CTRLC _SFR_MEM8(0x0322) -#define DACB_EVCTRL _SFR_MEM8(0x0323) -#define DACB_STATUS _SFR_MEM8(0x0325) -#define DACB_CH0GAINCAL _SFR_MEM8(0x0328) -#define DACB_CH0OFFSETCAL _SFR_MEM8(0x0329) -#define DACB_CH1GAINCAL _SFR_MEM8(0x032A) -#define DACB_CH1OFFSETCAL _SFR_MEM8(0x032B) -#define DACB_CH0DATA _SFR_MEM16(0x0338) -#define DACB_CH1DATA _SFR_MEM16(0x033A) - -/* AC - Analog Comparator */ -#define ACA_AC0CTRL _SFR_MEM8(0x0380) -#define ACA_AC1CTRL _SFR_MEM8(0x0381) -#define ACA_AC0MUXCTRL _SFR_MEM8(0x0382) -#define ACA_AC1MUXCTRL _SFR_MEM8(0x0383) -#define ACA_CTRLA _SFR_MEM8(0x0384) -#define ACA_CTRLB _SFR_MEM8(0x0385) -#define ACA_WINCTRL _SFR_MEM8(0x0386) -#define ACA_STATUS _SFR_MEM8(0x0387) - -/* RTC - Real-Time Counter */ -#define RTC_CTRL _SFR_MEM8(0x0400) -#define RTC_STATUS _SFR_MEM8(0x0401) -#define RTC_INTCTRL _SFR_MEM8(0x0402) -#define RTC_INTFLAGS _SFR_MEM8(0x0403) -#define RTC_TEMP _SFR_MEM8(0x0404) -#define RTC_CNT _SFR_MEM16(0x0408) -#define RTC_PER _SFR_MEM16(0x040A) -#define RTC_COMP _SFR_MEM16(0x040C) - -/* TWI - Two-Wire Interface */ -#define TWIC_CTRL _SFR_MEM8(0x0480) -#define TWIC_MASTER_CTRLA _SFR_MEM8(0x0481) -#define TWIC_MASTER_CTRLB _SFR_MEM8(0x0482) -#define TWIC_MASTER_CTRLC _SFR_MEM8(0x0483) -#define TWIC_MASTER_STATUS _SFR_MEM8(0x0484) -#define TWIC_MASTER_BAUD _SFR_MEM8(0x0485) -#define TWIC_MASTER_ADDR _SFR_MEM8(0x0486) -#define TWIC_MASTER_DATA _SFR_MEM8(0x0487) -#define TWIC_SLAVE_CTRLA _SFR_MEM8(0x0488) -#define TWIC_SLAVE_CTRLB _SFR_MEM8(0x0489) -#define TWIC_SLAVE_STATUS _SFR_MEM8(0x048A) -#define TWIC_SLAVE_ADDR _SFR_MEM8(0x048B) -#define TWIC_SLAVE_DATA _SFR_MEM8(0x048C) -#define TWIC_SLAVE_ADDRMASK _SFR_MEM8(0x048D) - -/* TWI - Two-Wire Interface */ -#define TWIE_CTRL _SFR_MEM8(0x04A0) -#define TWIE_MASTER_CTRLA _SFR_MEM8(0x04A1) -#define TWIE_MASTER_CTRLB _SFR_MEM8(0x04A2) -#define TWIE_MASTER_CTRLC _SFR_MEM8(0x04A3) -#define TWIE_MASTER_STATUS _SFR_MEM8(0x04A4) -#define TWIE_MASTER_BAUD _SFR_MEM8(0x04A5) -#define TWIE_MASTER_ADDR _SFR_MEM8(0x04A6) -#define TWIE_MASTER_DATA _SFR_MEM8(0x04A7) -#define TWIE_SLAVE_CTRLA _SFR_MEM8(0x04A8) -#define TWIE_SLAVE_CTRLB _SFR_MEM8(0x04A9) -#define TWIE_SLAVE_STATUS _SFR_MEM8(0x04AA) -#define TWIE_SLAVE_ADDR _SFR_MEM8(0x04AB) -#define TWIE_SLAVE_DATA _SFR_MEM8(0x04AC) -#define TWIE_SLAVE_ADDRMASK _SFR_MEM8(0x04AD) - -/* USB - Universal Serial Bus */ -#define USB_CTRLA _SFR_MEM8(0x04C0) -#define USB_CTRLB _SFR_MEM8(0x04C1) -#define USB_STATUS _SFR_MEM8(0x04C2) -#define USB_ADDR _SFR_MEM8(0x04C3) -#define USB_FIFOWP _SFR_MEM8(0x04C4) -#define USB_FIFORP _SFR_MEM8(0x04C5) -#define USB_EPPTR _SFR_MEM16(0x04C6) -#define USB_INTCTRLA _SFR_MEM8(0x04C8) -#define USB_INTCTRLB _SFR_MEM8(0x04C9) -#define USB_INTFLAGSACLR _SFR_MEM8(0x04CA) -#define USB_INTFLAGSASET _SFR_MEM8(0x04CB) -#define USB_INTFLAGSBCLR _SFR_MEM8(0x04CC) -#define USB_INTFLAGSBSET _SFR_MEM8(0x04CD) -#define USB_CAL0 _SFR_MEM8(0x04FA) -#define USB_CAL1 _SFR_MEM8(0x04FB) - -/* PORT - I/O Ports */ -#define PORTA_DIR _SFR_MEM8(0x0600) -#define PORTA_DIRSET _SFR_MEM8(0x0601) -#define PORTA_DIRCLR _SFR_MEM8(0x0602) -#define PORTA_DIRTGL _SFR_MEM8(0x0603) -#define PORTA_OUT _SFR_MEM8(0x0604) -#define PORTA_OUTSET _SFR_MEM8(0x0605) -#define PORTA_OUTCLR _SFR_MEM8(0x0606) -#define PORTA_OUTTGL _SFR_MEM8(0x0607) -#define PORTA_IN _SFR_MEM8(0x0608) -#define PORTA_INTCTRL _SFR_MEM8(0x0609) -#define PORTA_INT0MASK _SFR_MEM8(0x060A) -#define PORTA_INT1MASK _SFR_MEM8(0x060B) -#define PORTA_INTFLAGS _SFR_MEM8(0x060C) -#define PORTA_REMAP _SFR_MEM8(0x060E) -#define PORTA_PIN0CTRL _SFR_MEM8(0x0610) -#define PORTA_PIN1CTRL _SFR_MEM8(0x0611) -#define PORTA_PIN2CTRL _SFR_MEM8(0x0612) -#define PORTA_PIN3CTRL _SFR_MEM8(0x0613) -#define PORTA_PIN4CTRL _SFR_MEM8(0x0614) -#define PORTA_PIN5CTRL _SFR_MEM8(0x0615) -#define PORTA_PIN6CTRL _SFR_MEM8(0x0616) -#define PORTA_PIN7CTRL _SFR_MEM8(0x0617) - -/* PORT - I/O Ports */ -#define PORTB_DIR _SFR_MEM8(0x0620) -#define PORTB_DIRSET _SFR_MEM8(0x0621) -#define PORTB_DIRCLR _SFR_MEM8(0x0622) -#define PORTB_DIRTGL _SFR_MEM8(0x0623) -#define PORTB_OUT _SFR_MEM8(0x0624) -#define PORTB_OUTSET _SFR_MEM8(0x0625) -#define PORTB_OUTCLR _SFR_MEM8(0x0626) -#define PORTB_OUTTGL _SFR_MEM8(0x0627) -#define PORTB_IN _SFR_MEM8(0x0628) -#define PORTB_INTCTRL _SFR_MEM8(0x0629) -#define PORTB_INT0MASK _SFR_MEM8(0x062A) -#define PORTB_INT1MASK _SFR_MEM8(0x062B) -#define PORTB_INTFLAGS _SFR_MEM8(0x062C) -#define PORTB_REMAP _SFR_MEM8(0x062E) -#define PORTB_PIN0CTRL _SFR_MEM8(0x0630) -#define PORTB_PIN1CTRL _SFR_MEM8(0x0631) -#define PORTB_PIN2CTRL _SFR_MEM8(0x0632) -#define PORTB_PIN3CTRL _SFR_MEM8(0x0633) -#define PORTB_PIN4CTRL _SFR_MEM8(0x0634) -#define PORTB_PIN5CTRL _SFR_MEM8(0x0635) -#define PORTB_PIN6CTRL _SFR_MEM8(0x0636) -#define PORTB_PIN7CTRL _SFR_MEM8(0x0637) - -/* PORT - I/O Ports */ -#define PORTC_DIR _SFR_MEM8(0x0640) -#define PORTC_DIRSET _SFR_MEM8(0x0641) -#define PORTC_DIRCLR _SFR_MEM8(0x0642) -#define PORTC_DIRTGL _SFR_MEM8(0x0643) -#define PORTC_OUT _SFR_MEM8(0x0644) -#define PORTC_OUTSET _SFR_MEM8(0x0645) -#define PORTC_OUTCLR _SFR_MEM8(0x0646) -#define PORTC_OUTTGL _SFR_MEM8(0x0647) -#define PORTC_IN _SFR_MEM8(0x0648) -#define PORTC_INTCTRL _SFR_MEM8(0x0649) -#define PORTC_INT0MASK _SFR_MEM8(0x064A) -#define PORTC_INT1MASK _SFR_MEM8(0x064B) -#define PORTC_INTFLAGS _SFR_MEM8(0x064C) -#define PORTC_REMAP _SFR_MEM8(0x064E) -#define PORTC_PIN0CTRL _SFR_MEM8(0x0650) -#define PORTC_PIN1CTRL _SFR_MEM8(0x0651) -#define PORTC_PIN2CTRL _SFR_MEM8(0x0652) -#define PORTC_PIN3CTRL _SFR_MEM8(0x0653) -#define PORTC_PIN4CTRL _SFR_MEM8(0x0654) -#define PORTC_PIN5CTRL _SFR_MEM8(0x0655) -#define PORTC_PIN6CTRL _SFR_MEM8(0x0656) -#define PORTC_PIN7CTRL _SFR_MEM8(0x0657) - -/* PORT - I/O Ports */ -#define PORTD_DIR _SFR_MEM8(0x0660) -#define PORTD_DIRSET _SFR_MEM8(0x0661) -#define PORTD_DIRCLR _SFR_MEM8(0x0662) -#define PORTD_DIRTGL _SFR_MEM8(0x0663) -#define PORTD_OUT _SFR_MEM8(0x0664) -#define PORTD_OUTSET _SFR_MEM8(0x0665) -#define PORTD_OUTCLR _SFR_MEM8(0x0666) -#define PORTD_OUTTGL _SFR_MEM8(0x0667) -#define PORTD_IN _SFR_MEM8(0x0668) -#define PORTD_INTCTRL _SFR_MEM8(0x0669) -#define PORTD_INT0MASK _SFR_MEM8(0x066A) -#define PORTD_INT1MASK _SFR_MEM8(0x066B) -#define PORTD_INTFLAGS _SFR_MEM8(0x066C) -#define PORTD_REMAP _SFR_MEM8(0x066E) -#define PORTD_PIN0CTRL _SFR_MEM8(0x0670) -#define PORTD_PIN1CTRL _SFR_MEM8(0x0671) -#define PORTD_PIN2CTRL _SFR_MEM8(0x0672) -#define PORTD_PIN3CTRL _SFR_MEM8(0x0673) -#define PORTD_PIN4CTRL _SFR_MEM8(0x0674) -#define PORTD_PIN5CTRL _SFR_MEM8(0x0675) -#define PORTD_PIN6CTRL _SFR_MEM8(0x0676) -#define PORTD_PIN7CTRL _SFR_MEM8(0x0677) - -/* PORT - I/O Ports */ -#define PORTE_DIR _SFR_MEM8(0x0680) -#define PORTE_DIRSET _SFR_MEM8(0x0681) -#define PORTE_DIRCLR _SFR_MEM8(0x0682) -#define PORTE_DIRTGL _SFR_MEM8(0x0683) -#define PORTE_OUT _SFR_MEM8(0x0684) -#define PORTE_OUTSET _SFR_MEM8(0x0685) -#define PORTE_OUTCLR _SFR_MEM8(0x0686) -#define PORTE_OUTTGL _SFR_MEM8(0x0687) -#define PORTE_IN _SFR_MEM8(0x0688) -#define PORTE_INTCTRL _SFR_MEM8(0x0689) -#define PORTE_INT0MASK _SFR_MEM8(0x068A) -#define PORTE_INT1MASK _SFR_MEM8(0x068B) -#define PORTE_INTFLAGS _SFR_MEM8(0x068C) -#define PORTE_REMAP _SFR_MEM8(0x068E) -#define PORTE_PIN0CTRL _SFR_MEM8(0x0690) -#define PORTE_PIN1CTRL _SFR_MEM8(0x0691) -#define PORTE_PIN2CTRL _SFR_MEM8(0x0692) -#define PORTE_PIN3CTRL _SFR_MEM8(0x0693) -#define PORTE_PIN4CTRL _SFR_MEM8(0x0694) -#define PORTE_PIN5CTRL _SFR_MEM8(0x0695) -#define PORTE_PIN6CTRL _SFR_MEM8(0x0696) -#define PORTE_PIN7CTRL _SFR_MEM8(0x0697) - -/* PORT - I/O Ports */ -#define PORTR_DIR _SFR_MEM8(0x07E0) -#define PORTR_DIRSET _SFR_MEM8(0x07E1) -#define PORTR_DIRCLR _SFR_MEM8(0x07E2) -#define PORTR_DIRTGL _SFR_MEM8(0x07E3) -#define PORTR_OUT _SFR_MEM8(0x07E4) -#define PORTR_OUTSET _SFR_MEM8(0x07E5) -#define PORTR_OUTCLR _SFR_MEM8(0x07E6) -#define PORTR_OUTTGL _SFR_MEM8(0x07E7) -#define PORTR_IN _SFR_MEM8(0x07E8) -#define PORTR_INTCTRL _SFR_MEM8(0x07E9) -#define PORTR_INT0MASK _SFR_MEM8(0x07EA) -#define PORTR_INT1MASK _SFR_MEM8(0x07EB) -#define PORTR_INTFLAGS _SFR_MEM8(0x07EC) -#define PORTR_REMAP _SFR_MEM8(0x07EE) -#define PORTR_PIN0CTRL _SFR_MEM8(0x07F0) -#define PORTR_PIN1CTRL _SFR_MEM8(0x07F1) -#define PORTR_PIN2CTRL _SFR_MEM8(0x07F2) -#define PORTR_PIN3CTRL _SFR_MEM8(0x07F3) -#define PORTR_PIN4CTRL _SFR_MEM8(0x07F4) -#define PORTR_PIN5CTRL _SFR_MEM8(0x07F5) -#define PORTR_PIN6CTRL _SFR_MEM8(0x07F6) -#define PORTR_PIN7CTRL _SFR_MEM8(0x07F7) - -/* TC0 - 16-bit Timer/Counter 0 */ -#define TCC0_CTRLA _SFR_MEM8(0x0800) -#define TCC0_CTRLB _SFR_MEM8(0x0801) -#define TCC0_CTRLC _SFR_MEM8(0x0802) -#define TCC0_CTRLD _SFR_MEM8(0x0803) -#define TCC0_CTRLE _SFR_MEM8(0x0804) -#define TCC0_INTCTRLA _SFR_MEM8(0x0806) -#define TCC0_INTCTRLB _SFR_MEM8(0x0807) -#define TCC0_CTRLFCLR _SFR_MEM8(0x0808) -#define TCC0_CTRLFSET _SFR_MEM8(0x0809) -#define TCC0_CTRLGCLR _SFR_MEM8(0x080A) -#define TCC0_CTRLGSET _SFR_MEM8(0x080B) -#define TCC0_INTFLAGS _SFR_MEM8(0x080C) -#define TCC0_TEMP _SFR_MEM8(0x080F) -#define TCC0_CNT _SFR_MEM16(0x0820) -#define TCC0_PER _SFR_MEM16(0x0826) -#define TCC0_CCA _SFR_MEM16(0x0828) -#define TCC0_CCB _SFR_MEM16(0x082A) -#define TCC0_CCC _SFR_MEM16(0x082C) -#define TCC0_CCD _SFR_MEM16(0x082E) -#define TCC0_PERBUF _SFR_MEM16(0x0836) -#define TCC0_CCABUF _SFR_MEM16(0x0838) -#define TCC0_CCBBUF _SFR_MEM16(0x083A) -#define TCC0_CCCBUF _SFR_MEM16(0x083C) -#define TCC0_CCDBUF _SFR_MEM16(0x083E) - -/* TC2 - 16-bit Timer/Counter type 2 */ -#define TCC2_CTRLA _SFR_MEM8(0x0800) -#define TCC2_CTRLB _SFR_MEM8(0x0801) -#define TCC2_CTRLC _SFR_MEM8(0x0802) -#define TCC2_CTRLE _SFR_MEM8(0x0804) -#define TCC2_INTCTRLA _SFR_MEM8(0x0806) -#define TCC2_INTCTRLB _SFR_MEM8(0x0807) -#define TCC2_CTRLF _SFR_MEM8(0x0809) -#define TCC2_INTFLAGS _SFR_MEM8(0x080C) -#define TCC2_LCNT _SFR_MEM8(0x0820) -#define TCC2_HCNT _SFR_MEM8(0x0821) -#define TCC2_LPER _SFR_MEM8(0x0826) -#define TCC2_HPER _SFR_MEM8(0x0827) -#define TCC2_LCMPA _SFR_MEM8(0x0828) -#define TCC2_HCMPA _SFR_MEM8(0x0829) -#define TCC2_LCMPB _SFR_MEM8(0x082A) -#define TCC2_HCMPB _SFR_MEM8(0x082B) -#define TCC2_LCMPC _SFR_MEM8(0x082C) -#define TCC2_HCMPC _SFR_MEM8(0x082D) -#define TCC2_LCMPD _SFR_MEM8(0x082E) -#define TCC2_HCMPD _SFR_MEM8(0x082F) - -/* TC1 - 16-bit Timer/Counter 1 */ -#define TCC1_CTRLA _SFR_MEM8(0x0840) -#define TCC1_CTRLB _SFR_MEM8(0x0841) -#define TCC1_CTRLC _SFR_MEM8(0x0842) -#define TCC1_CTRLD _SFR_MEM8(0x0843) -#define TCC1_CTRLE _SFR_MEM8(0x0844) -#define TCC1_INTCTRLA _SFR_MEM8(0x0846) -#define TCC1_INTCTRLB _SFR_MEM8(0x0847) -#define TCC1_CTRLFCLR _SFR_MEM8(0x0848) -#define TCC1_CTRLFSET _SFR_MEM8(0x0849) -#define TCC1_CTRLGCLR _SFR_MEM8(0x084A) -#define TCC1_CTRLGSET _SFR_MEM8(0x084B) -#define TCC1_INTFLAGS _SFR_MEM8(0x084C) -#define TCC1_TEMP _SFR_MEM8(0x084F) -#define TCC1_CNT _SFR_MEM16(0x0860) -#define TCC1_PER _SFR_MEM16(0x0866) -#define TCC1_CCA _SFR_MEM16(0x0868) -#define TCC1_CCB _SFR_MEM16(0x086A) -#define TCC1_PERBUF _SFR_MEM16(0x0876) -#define TCC1_CCABUF _SFR_MEM16(0x0878) -#define TCC1_CCBBUF _SFR_MEM16(0x087A) - -/* AWEX - Advanced Waveform Extension */ -#define AWEXC_CTRL _SFR_MEM8(0x0880) -#define AWEXC_FDEMASK _SFR_MEM8(0x0882) -#define AWEXC_FDCTRL _SFR_MEM8(0x0883) -#define AWEXC_STATUS _SFR_MEM8(0x0884) -#define AWEXC_STATUSSET _SFR_MEM8(0x0885) -#define AWEXC_DTBOTH _SFR_MEM8(0x0886) -#define AWEXC_DTBOTHBUF _SFR_MEM8(0x0887) -#define AWEXC_DTLS _SFR_MEM8(0x0888) -#define AWEXC_DTHS _SFR_MEM8(0x0889) -#define AWEXC_DTLSBUF _SFR_MEM8(0x088A) -#define AWEXC_DTHSBUF _SFR_MEM8(0x088B) -#define AWEXC_OUTOVEN _SFR_MEM8(0x088C) - -/* HIRES - High-Resolution Extension */ -#define HIRESC_CTRLA _SFR_MEM8(0x0890) - -/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ -#define USARTC0_DATA _SFR_MEM8(0x08A0) -#define USARTC0_STATUS _SFR_MEM8(0x08A1) -#define USARTC0_CTRLA _SFR_MEM8(0x08A3) -#define USARTC0_CTRLB _SFR_MEM8(0x08A4) -#define USARTC0_CTRLC _SFR_MEM8(0x08A5) -#define USARTC0_BAUDCTRLA _SFR_MEM8(0x08A6) -#define USARTC0_BAUDCTRLB _SFR_MEM8(0x08A7) - -/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ -#define USARTC1_DATA _SFR_MEM8(0x08B0) -#define USARTC1_STATUS _SFR_MEM8(0x08B1) -#define USARTC1_CTRLA _SFR_MEM8(0x08B3) -#define USARTC1_CTRLB _SFR_MEM8(0x08B4) -#define USARTC1_CTRLC _SFR_MEM8(0x08B5) -#define USARTC1_BAUDCTRLA _SFR_MEM8(0x08B6) -#define USARTC1_BAUDCTRLB _SFR_MEM8(0x08B7) - -/* SPI - Serial Peripheral Interface */ -#define SPIC_CTRL _SFR_MEM8(0x08C0) -#define SPIC_INTCTRL _SFR_MEM8(0x08C1) -#define SPIC_STATUS _SFR_MEM8(0x08C2) -#define SPIC_DATA _SFR_MEM8(0x08C3) - -/* IRCOM - IR Communication Module */ -#define IRCOM_CTRL _SFR_MEM8(0x08F8) -#define IRCOM_TXPLCTRL _SFR_MEM8(0x08F9) -#define IRCOM_RXPLCTRL _SFR_MEM8(0x08FA) - -/* TC0 - 16-bit Timer/Counter 0 */ -#define TCD0_CTRLA _SFR_MEM8(0x0900) -#define TCD0_CTRLB _SFR_MEM8(0x0901) -#define TCD0_CTRLC _SFR_MEM8(0x0902) -#define TCD0_CTRLD _SFR_MEM8(0x0903) -#define TCD0_CTRLE _SFR_MEM8(0x0904) -#define TCD0_INTCTRLA _SFR_MEM8(0x0906) -#define TCD0_INTCTRLB _SFR_MEM8(0x0907) -#define TCD0_CTRLFCLR _SFR_MEM8(0x0908) -#define TCD0_CTRLFSET _SFR_MEM8(0x0909) -#define TCD0_CTRLGCLR _SFR_MEM8(0x090A) -#define TCD0_CTRLGSET _SFR_MEM8(0x090B) -#define TCD0_INTFLAGS _SFR_MEM8(0x090C) -#define TCD0_TEMP _SFR_MEM8(0x090F) -#define TCD0_CNT _SFR_MEM16(0x0920) -#define TCD0_PER _SFR_MEM16(0x0926) -#define TCD0_CCA _SFR_MEM16(0x0928) -#define TCD0_CCB _SFR_MEM16(0x092A) -#define TCD0_CCC _SFR_MEM16(0x092C) -#define TCD0_CCD _SFR_MEM16(0x092E) -#define TCD0_PERBUF _SFR_MEM16(0x0936) -#define TCD0_CCABUF _SFR_MEM16(0x0938) -#define TCD0_CCBBUF _SFR_MEM16(0x093A) -#define TCD0_CCCBUF _SFR_MEM16(0x093C) -#define TCD0_CCDBUF _SFR_MEM16(0x093E) - -/* TC2 - 16-bit Timer/Counter type 2 */ -#define TCD2_CTRLA _SFR_MEM8(0x0900) -#define TCD2_CTRLB _SFR_MEM8(0x0901) -#define TCD2_CTRLC _SFR_MEM8(0x0902) -#define TCD2_CTRLE _SFR_MEM8(0x0904) -#define TCD2_INTCTRLA _SFR_MEM8(0x0906) -#define TCD2_INTCTRLB _SFR_MEM8(0x0907) -#define TCD2_CTRLF _SFR_MEM8(0x0909) -#define TCD2_INTFLAGS _SFR_MEM8(0x090C) -#define TCD2_LCNT _SFR_MEM8(0x0920) -#define TCD2_HCNT _SFR_MEM8(0x0921) -#define TCD2_LPER _SFR_MEM8(0x0926) -#define TCD2_HPER _SFR_MEM8(0x0927) -#define TCD2_LCMPA _SFR_MEM8(0x0928) -#define TCD2_HCMPA _SFR_MEM8(0x0929) -#define TCD2_LCMPB _SFR_MEM8(0x092A) -#define TCD2_HCMPB _SFR_MEM8(0x092B) -#define TCD2_LCMPC _SFR_MEM8(0x092C) -#define TCD2_HCMPC _SFR_MEM8(0x092D) -#define TCD2_LCMPD _SFR_MEM8(0x092E) -#define TCD2_HCMPD _SFR_MEM8(0x092F) - -/* TC1 - 16-bit Timer/Counter 1 */ -#define TCD1_CTRLA _SFR_MEM8(0x0940) -#define TCD1_CTRLB _SFR_MEM8(0x0941) -#define TCD1_CTRLC _SFR_MEM8(0x0942) -#define TCD1_CTRLD _SFR_MEM8(0x0943) -#define TCD1_CTRLE _SFR_MEM8(0x0944) -#define TCD1_INTCTRLA _SFR_MEM8(0x0946) -#define TCD1_INTCTRLB _SFR_MEM8(0x0947) -#define TCD1_CTRLFCLR _SFR_MEM8(0x0948) -#define TCD1_CTRLFSET _SFR_MEM8(0x0949) -#define TCD1_CTRLGCLR _SFR_MEM8(0x094A) -#define TCD1_CTRLGSET _SFR_MEM8(0x094B) -#define TCD1_INTFLAGS _SFR_MEM8(0x094C) -#define TCD1_TEMP _SFR_MEM8(0x094F) -#define TCD1_CNT _SFR_MEM16(0x0960) -#define TCD1_PER _SFR_MEM16(0x0966) -#define TCD1_CCA _SFR_MEM16(0x0968) -#define TCD1_CCB _SFR_MEM16(0x096A) -#define TCD1_PERBUF _SFR_MEM16(0x0976) -#define TCD1_CCABUF _SFR_MEM16(0x0978) -#define TCD1_CCBBUF _SFR_MEM16(0x097A) - -/* HIRES - High-Resolution Extension */ -#define HIRESD_CTRLA _SFR_MEM8(0x0990) - -/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ -#define USARTD0_DATA _SFR_MEM8(0x09A0) -#define USARTD0_STATUS _SFR_MEM8(0x09A1) -#define USARTD0_CTRLA _SFR_MEM8(0x09A3) -#define USARTD0_CTRLB _SFR_MEM8(0x09A4) -#define USARTD0_CTRLC _SFR_MEM8(0x09A5) -#define USARTD0_BAUDCTRLA _SFR_MEM8(0x09A6) -#define USARTD0_BAUDCTRLB _SFR_MEM8(0x09A7) - -/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ -#define USARTD1_DATA _SFR_MEM8(0x09B0) -#define USARTD1_STATUS _SFR_MEM8(0x09B1) -#define USARTD1_CTRLA _SFR_MEM8(0x09B3) -#define USARTD1_CTRLB _SFR_MEM8(0x09B4) -#define USARTD1_CTRLC _SFR_MEM8(0x09B5) -#define USARTD1_BAUDCTRLA _SFR_MEM8(0x09B6) -#define USARTD1_BAUDCTRLB _SFR_MEM8(0x09B7) - -/* SPI - Serial Peripheral Interface */ -#define SPID_CTRL _SFR_MEM8(0x09C0) -#define SPID_INTCTRL _SFR_MEM8(0x09C1) -#define SPID_STATUS _SFR_MEM8(0x09C2) -#define SPID_DATA _SFR_MEM8(0x09C3) - -/* TC0 - 16-bit Timer/Counter 0 */ -#define TCE0_CTRLA _SFR_MEM8(0x0A00) -#define TCE0_CTRLB _SFR_MEM8(0x0A01) -#define TCE0_CTRLC _SFR_MEM8(0x0A02) -#define TCE0_CTRLD _SFR_MEM8(0x0A03) -#define TCE0_CTRLE _SFR_MEM8(0x0A04) -#define TCE0_INTCTRLA _SFR_MEM8(0x0A06) -#define TCE0_INTCTRLB _SFR_MEM8(0x0A07) -#define TCE0_CTRLFCLR _SFR_MEM8(0x0A08) -#define TCE0_CTRLFSET _SFR_MEM8(0x0A09) -#define TCE0_CTRLGCLR _SFR_MEM8(0x0A0A) -#define TCE0_CTRLGSET _SFR_MEM8(0x0A0B) -#define TCE0_INTFLAGS _SFR_MEM8(0x0A0C) -#define TCE0_TEMP _SFR_MEM8(0x0A0F) -#define TCE0_CNT _SFR_MEM16(0x0A20) -#define TCE0_PER _SFR_MEM16(0x0A26) -#define TCE0_CCA _SFR_MEM16(0x0A28) -#define TCE0_CCB _SFR_MEM16(0x0A2A) -#define TCE0_CCC _SFR_MEM16(0x0A2C) -#define TCE0_CCD _SFR_MEM16(0x0A2E) -#define TCE0_PERBUF _SFR_MEM16(0x0A36) -#define TCE0_CCABUF _SFR_MEM16(0x0A38) -#define TCE0_CCBBUF _SFR_MEM16(0x0A3A) -#define TCE0_CCCBUF _SFR_MEM16(0x0A3C) -#define TCE0_CCDBUF _SFR_MEM16(0x0A3E) - -/* HIRES - High-Resolution Extension */ -#define HIRESE_CTRLA _SFR_MEM8(0x0A90) - -/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ -#define USARTE0_DATA _SFR_MEM8(0x0AA0) -#define USARTE0_STATUS _SFR_MEM8(0x0AA1) -#define USARTE0_CTRLA _SFR_MEM8(0x0AA3) -#define USARTE0_CTRLB _SFR_MEM8(0x0AA4) -#define USARTE0_CTRLC _SFR_MEM8(0x0AA5) -#define USARTE0_BAUDCTRLA _SFR_MEM8(0x0AA6) -#define USARTE0_BAUDCTRLB _SFR_MEM8(0x0AA7) - - - -/*================== Bitfield Definitions ================== */ - -/* VPORT - Virtual Ports */ -/* VPORT.INTFLAGS bit masks and bit positions */ -#define VPORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ -#define VPORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ - -#define VPORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ -#define VPORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ - -/* XOCD - On-Chip Debug System */ -/* OCD.OCDR0 bit masks and bit positions */ -#define OCD_OCDRD_gm 0xFF /* OCDR Dirty group mask. */ -#define OCD_OCDRD_gp 0 /* OCDR Dirty group position. */ -#define OCD_OCDRD0_bm (1<<0) /* OCDR Dirty bit 0 mask. */ -#define OCD_OCDRD0_bp 0 /* OCDR Dirty bit 0 position. */ -#define OCD_OCDRD1_bm (1<<1) /* OCDR Dirty bit 1 mask. */ -#define OCD_OCDRD1_bp 1 /* OCDR Dirty bit 1 position. */ -#define OCD_OCDRD2_bm (1<<2) /* OCDR Dirty bit 2 mask. */ -#define OCD_OCDRD2_bp 2 /* OCDR Dirty bit 2 position. */ -#define OCD_OCDRD3_bm (1<<3) /* OCDR Dirty bit 3 mask. */ -#define OCD_OCDRD3_bp 3 /* OCDR Dirty bit 3 position. */ -#define OCD_OCDRD4_bm (1<<4) /* OCDR Dirty bit 4 mask. */ -#define OCD_OCDRD4_bp 4 /* OCDR Dirty bit 4 position. */ -#define OCD_OCDRD5_bm (1<<5) /* OCDR Dirty bit 5 mask. */ -#define OCD_OCDRD5_bp 5 /* OCDR Dirty bit 5 position. */ -#define OCD_OCDRD6_bm (1<<6) /* OCDR Dirty bit 6 mask. */ -#define OCD_OCDRD6_bp 6 /* OCDR Dirty bit 6 position. */ -#define OCD_OCDRD7_bm (1<<7) /* OCDR Dirty bit 7 mask. */ -#define OCD_OCDRD7_bp 7 /* OCDR Dirty bit 7 position. */ - -/* OCD.OCDR1 bit masks and bit positions */ -/* OCD_OCDRD Predefined. */ -/* OCD_OCDRD Predefined. */ - -/* CPU - CPU */ -/* CPU.CCP bit masks and bit positions */ -#define CPU_CCP_gm 0xFF /* CCP signature group mask. */ -#define CPU_CCP_gp 0 /* CCP signature group position. */ -#define CPU_CCP0_bm (1<<0) /* CCP signature bit 0 mask. */ -#define CPU_CCP0_bp 0 /* CCP signature bit 0 position. */ -#define CPU_CCP1_bm (1<<1) /* CCP signature bit 1 mask. */ -#define CPU_CCP1_bp 1 /* CCP signature bit 1 position. */ -#define CPU_CCP2_bm (1<<2) /* CCP signature bit 2 mask. */ -#define CPU_CCP2_bp 2 /* CCP signature bit 2 position. */ -#define CPU_CCP3_bm (1<<3) /* CCP signature bit 3 mask. */ -#define CPU_CCP3_bp 3 /* CCP signature bit 3 position. */ -#define CPU_CCP4_bm (1<<4) /* CCP signature bit 4 mask. */ -#define CPU_CCP4_bp 4 /* CCP signature bit 4 position. */ -#define CPU_CCP5_bm (1<<5) /* CCP signature bit 5 mask. */ -#define CPU_CCP5_bp 5 /* CCP signature bit 5 position. */ -#define CPU_CCP6_bm (1<<6) /* CCP signature bit 6 mask. */ -#define CPU_CCP6_bp 6 /* CCP signature bit 6 position. */ -#define CPU_CCP7_bm (1<<7) /* CCP signature bit 7 mask. */ -#define CPU_CCP7_bp 7 /* CCP signature bit 7 position. */ - -/* CPU.SREG bit masks and bit positions */ -#define CPU_I_bm 0x80 /* Global Interrupt Enable Flag bit mask. */ -#define CPU_I_bp 7 /* Global Interrupt Enable Flag bit position. */ - -#define CPU_T_bm 0x40 /* Transfer Bit bit mask. */ -#define CPU_T_bp 6 /* Transfer Bit bit position. */ - -#define CPU_H_bm 0x20 /* Half Carry Flag bit mask. */ -#define CPU_H_bp 5 /* Half Carry Flag bit position. */ - -#define CPU_S_bm 0x10 /* N Exclusive Or V Flag bit mask. */ -#define CPU_S_bp 4 /* N Exclusive Or V Flag bit position. */ - -#define CPU_V_bm 0x08 /* Two's Complement Overflow Flag bit mask. */ -#define CPU_V_bp 3 /* Two's Complement Overflow Flag bit position. */ - -#define CPU_N_bm 0x04 /* Negative Flag bit mask. */ -#define CPU_N_bp 2 /* Negative Flag bit position. */ - -#define CPU_Z_bm 0x02 /* Zero Flag bit mask. */ -#define CPU_Z_bp 1 /* Zero Flag bit position. */ - -#define CPU_C_bm 0x01 /* Carry Flag bit mask. */ -#define CPU_C_bp 0 /* Carry Flag bit position. */ - -/* CLK - Clock System */ -/* CLK.CTRL bit masks and bit positions */ -#define CLK_SCLKSEL_gm 0x07 /* System Clock Selection group mask. */ -#define CLK_SCLKSEL_gp 0 /* System Clock Selection group position. */ -#define CLK_SCLKSEL0_bm (1<<0) /* System Clock Selection bit 0 mask. */ -#define CLK_SCLKSEL0_bp 0 /* System Clock Selection bit 0 position. */ -#define CLK_SCLKSEL1_bm (1<<1) /* System Clock Selection bit 1 mask. */ -#define CLK_SCLKSEL1_bp 1 /* System Clock Selection bit 1 position. */ -#define CLK_SCLKSEL2_bm (1<<2) /* System Clock Selection bit 2 mask. */ -#define CLK_SCLKSEL2_bp 2 /* System Clock Selection bit 2 position. */ - -/* CLK.PSCTRL bit masks and bit positions */ -#define CLK_PSADIV_gm 0x7C /* Prescaler A Division Factor group mask. */ -#define CLK_PSADIV_gp 2 /* Prescaler A Division Factor group position. */ -#define CLK_PSADIV0_bm (1<<2) /* Prescaler A Division Factor bit 0 mask. */ -#define CLK_PSADIV0_bp 2 /* Prescaler A Division Factor bit 0 position. */ -#define CLK_PSADIV1_bm (1<<3) /* Prescaler A Division Factor bit 1 mask. */ -#define CLK_PSADIV1_bp 3 /* Prescaler A Division Factor bit 1 position. */ -#define CLK_PSADIV2_bm (1<<4) /* Prescaler A Division Factor bit 2 mask. */ -#define CLK_PSADIV2_bp 4 /* Prescaler A Division Factor bit 2 position. */ -#define CLK_PSADIV3_bm (1<<5) /* Prescaler A Division Factor bit 3 mask. */ -#define CLK_PSADIV3_bp 5 /* Prescaler A Division Factor bit 3 position. */ -#define CLK_PSADIV4_bm (1<<6) /* Prescaler A Division Factor bit 4 mask. */ -#define CLK_PSADIV4_bp 6 /* Prescaler A Division Factor bit 4 position. */ - -#define CLK_PSBCDIV_gm 0x03 /* Prescaler B and C Division factor group mask. */ -#define CLK_PSBCDIV_gp 0 /* Prescaler B and C Division factor group position. */ -#define CLK_PSBCDIV0_bm (1<<0) /* Prescaler B and C Division factor bit 0 mask. */ -#define CLK_PSBCDIV0_bp 0 /* Prescaler B and C Division factor bit 0 position. */ -#define CLK_PSBCDIV1_bm (1<<1) /* Prescaler B and C Division factor bit 1 mask. */ -#define CLK_PSBCDIV1_bp 1 /* Prescaler B and C Division factor bit 1 position. */ - -/* CLK.LOCK bit masks and bit positions */ -#define CLK_LOCK_bm 0x01 /* Clock System Lock bit mask. */ -#define CLK_LOCK_bp 0 /* Clock System Lock bit position. */ - -/* CLK.RTCCTRL bit masks and bit positions */ -#define CLK_RTCSRC_gm 0x0E /* Clock Source group mask. */ -#define CLK_RTCSRC_gp 1 /* Clock Source group position. */ -#define CLK_RTCSRC0_bm (1<<1) /* Clock Source bit 0 mask. */ -#define CLK_RTCSRC0_bp 1 /* Clock Source bit 0 position. */ -#define CLK_RTCSRC1_bm (1<<2) /* Clock Source bit 1 mask. */ -#define CLK_RTCSRC1_bp 2 /* Clock Source bit 1 position. */ -#define CLK_RTCSRC2_bm (1<<3) /* Clock Source bit 2 mask. */ -#define CLK_RTCSRC2_bp 3 /* Clock Source bit 2 position. */ - -#define CLK_RTCEN_bm 0x01 /* Clock Source Enable bit mask. */ -#define CLK_RTCEN_bp 0 /* Clock Source Enable bit position. */ - -/* CLK.USBCTRL bit masks and bit positions */ -#define CLK_USBPSDIV_gm 0x38 /* Prescaler Division Factor group mask. */ -#define CLK_USBPSDIV_gp 3 /* Prescaler Division Factor group position. */ -#define CLK_USBPSDIV0_bm (1<<3) /* Prescaler Division Factor bit 0 mask. */ -#define CLK_USBPSDIV0_bp 3 /* Prescaler Division Factor bit 0 position. */ -#define CLK_USBPSDIV1_bm (1<<4) /* Prescaler Division Factor bit 1 mask. */ -#define CLK_USBPSDIV1_bp 4 /* Prescaler Division Factor bit 1 position. */ -#define CLK_USBPSDIV2_bm (1<<5) /* Prescaler Division Factor bit 2 mask. */ -#define CLK_USBPSDIV2_bp 5 /* Prescaler Division Factor bit 2 position. */ - -#define CLK_USBSRC_gm 0x06 /* Clock Source group mask. */ -#define CLK_USBSRC_gp 1 /* Clock Source group position. */ -#define CLK_USBSRC0_bm (1<<1) /* Clock Source bit 0 mask. */ -#define CLK_USBSRC0_bp 1 /* Clock Source bit 0 position. */ -#define CLK_USBSRC1_bm (1<<2) /* Clock Source bit 1 mask. */ -#define CLK_USBSRC1_bp 2 /* Clock Source bit 1 position. */ - -#define CLK_USBSEN_bm 0x01 /* Clock Source Enable bit mask. */ -#define CLK_USBSEN_bp 0 /* Clock Source Enable bit position. */ - -/* PR.PRGEN bit masks and bit positions */ -#define PR_USB_bm 0x40 /* USB bit mask. */ -#define PR_USB_bp 6 /* USB bit position. */ - -#define PR_AES_bm 0x10 /* AES bit mask. */ -#define PR_AES_bp 4 /* AES bit position. */ - -#define PR_EBI_bm 0x08 /* External Bus Interface bit mask. */ -#define PR_EBI_bp 3 /* External Bus Interface bit position. */ - -#define PR_RTC_bm 0x04 /* Real-time Counter bit mask. */ -#define PR_RTC_bp 2 /* Real-time Counter bit position. */ - -#define PR_EVSYS_bm 0x02 /* Event System bit mask. */ -#define PR_EVSYS_bp 1 /* Event System bit position. */ - -#define PR_DMA_bm 0x01 /* DMA-Controller bit mask. */ -#define PR_DMA_bp 0 /* DMA-Controller bit position. */ - -/* PR.PRPA bit masks and bit positions */ -#define PR_DAC_bm 0x04 /* Port A DAC bit mask. */ -#define PR_DAC_bp 2 /* Port A DAC bit position. */ - -#define PR_ADC_bm 0x02 /* Port A ADC bit mask. */ -#define PR_ADC_bp 1 /* Port A ADC bit position. */ - -#define PR_AC_bm 0x01 /* Port A Analog Comparator bit mask. */ -#define PR_AC_bp 0 /* Port A Analog Comparator bit position. */ - -/* PR.PRPB bit masks and bit positions */ -/* PR_DAC Predefined. */ -/* PR_DAC Predefined. */ - -/* PR_ADC Predefined. */ -/* PR_ADC Predefined. */ - -/* PR_AC Predefined. */ -/* PR_AC Predefined. */ - -/* PR.PRPC bit masks and bit positions */ -#define PR_TWI_bm 0x40 /* Port C Two-wire Interface bit mask. */ -#define PR_TWI_bp 6 /* Port C Two-wire Interface bit position. */ - -#define PR_USART1_bm 0x20 /* Port C USART1 bit mask. */ -#define PR_USART1_bp 5 /* Port C USART1 bit position. */ - -#define PR_USART0_bm 0x10 /* Port C USART0 bit mask. */ -#define PR_USART0_bp 4 /* Port C USART0 bit position. */ - -#define PR_SPI_bm 0x08 /* Port C SPI bit mask. */ -#define PR_SPI_bp 3 /* Port C SPI bit position. */ - -#define PR_HIRES_bm 0x04 /* Port C AWEX bit mask. */ -#define PR_HIRES_bp 2 /* Port C AWEX bit position. */ - -#define PR_TC1_bm 0x02 /* Port C Timer/Counter1 bit mask. */ -#define PR_TC1_bp 1 /* Port C Timer/Counter1 bit position. */ - -#define PR_TC0_bm 0x01 /* Port C Timer/Counter0 bit mask. */ -#define PR_TC0_bp 0 /* Port C Timer/Counter0 bit position. */ - -/* PR.PRPD bit masks and bit positions */ -/* PR_TWI Predefined. */ -/* PR_TWI Predefined. */ - -/* PR_USART1 Predefined. */ -/* PR_USART1 Predefined. */ - -/* PR_USART0 Predefined. */ -/* PR_USART0 Predefined. */ - -/* PR_SPI Predefined. */ -/* PR_SPI Predefined. */ - -/* PR_HIRES Predefined. */ -/* PR_HIRES Predefined. */ - -/* PR_TC1 Predefined. */ -/* PR_TC1 Predefined. */ - -/* PR_TC0 Predefined. */ -/* PR_TC0 Predefined. */ - -/* PR.PRPE bit masks and bit positions */ -/* PR_TWI Predefined. */ -/* PR_TWI Predefined. */ - -/* PR_USART1 Predefined. */ -/* PR_USART1 Predefined. */ - -/* PR_USART0 Predefined. */ -/* PR_USART0 Predefined. */ - -/* PR_SPI Predefined. */ -/* PR_SPI Predefined. */ - -/* PR_HIRES Predefined. */ -/* PR_HIRES Predefined. */ - -/* PR_TC1 Predefined. */ -/* PR_TC1 Predefined. */ - -/* PR_TC0 Predefined. */ -/* PR_TC0 Predefined. */ - -/* PR.PRPF bit masks and bit positions */ -/* PR_TWI Predefined. */ -/* PR_TWI Predefined. */ - -/* PR_USART1 Predefined. */ -/* PR_USART1 Predefined. */ - -/* PR_USART0 Predefined. */ -/* PR_USART0 Predefined. */ - -/* PR_SPI Predefined. */ -/* PR_SPI Predefined. */ - -/* PR_HIRES Predefined. */ -/* PR_HIRES Predefined. */ - -/* PR_TC1 Predefined. */ -/* PR_TC1 Predefined. */ - -/* PR_TC0 Predefined. */ -/* PR_TC0 Predefined. */ - -/* SLEEP - Sleep Controller */ -/* SLEEP.CTRL bit masks and bit positions */ -#define SLEEP_SMODE_gm 0x0E /* Sleep Mode group mask. */ -#define SLEEP_SMODE_gp 1 /* Sleep Mode group position. */ -#define SLEEP_SMODE0_bm (1<<1) /* Sleep Mode bit 0 mask. */ -#define SLEEP_SMODE0_bp 1 /* Sleep Mode bit 0 position. */ -#define SLEEP_SMODE1_bm (1<<2) /* Sleep Mode bit 1 mask. */ -#define SLEEP_SMODE1_bp 2 /* Sleep Mode bit 1 position. */ -#define SLEEP_SMODE2_bm (1<<3) /* Sleep Mode bit 2 mask. */ -#define SLEEP_SMODE2_bp 3 /* Sleep Mode bit 2 position. */ - -#define SLEEP_SEN_bm 0x01 /* Sleep Enable bit mask. */ -#define SLEEP_SEN_bp 0 /* Sleep Enable bit position. */ - -/* OSC - Oscillator */ -/* OSC.CTRL bit masks and bit positions */ -#define OSC_PLLEN_bm 0x10 /* PLL Enable bit mask. */ -#define OSC_PLLEN_bp 4 /* PLL Enable bit position. */ - -#define OSC_XOSCEN_bm 0x08 /* External Oscillator Enable bit mask. */ -#define OSC_XOSCEN_bp 3 /* External Oscillator Enable bit position. */ - -#define OSC_RC32KEN_bm 0x04 /* Internal 32.768 kHz RC Oscillator Enable bit mask. */ -#define OSC_RC32KEN_bp 2 /* Internal 32.768 kHz RC Oscillator Enable bit position. */ - -#define OSC_RC32MEN_bm 0x02 /* Internal 32 MHz RC Oscillator Enable bit mask. */ -#define OSC_RC32MEN_bp 1 /* Internal 32 MHz RC Oscillator Enable bit position. */ - -#define OSC_RC2MEN_bm 0x01 /* Internal 2 MHz RC Oscillator Enable bit mask. */ -#define OSC_RC2MEN_bp 0 /* Internal 2 MHz RC Oscillator Enable bit position. */ - -/* OSC.STATUS bit masks and bit positions */ -#define OSC_PLLRDY_bm 0x10 /* PLL Ready bit mask. */ -#define OSC_PLLRDY_bp 4 /* PLL Ready bit position. */ - -#define OSC_XOSCRDY_bm 0x08 /* External Oscillator Ready bit mask. */ -#define OSC_XOSCRDY_bp 3 /* External Oscillator Ready bit position. */ - -#define OSC_RC32KRDY_bm 0x04 /* Internal 32.768 kHz RC Oscillator Ready bit mask. */ -#define OSC_RC32KRDY_bp 2 /* Internal 32.768 kHz RC Oscillator Ready bit position. */ - -#define OSC_RC32MRDY_bm 0x02 /* Internal 32 MHz RC Oscillator Ready bit mask. */ -#define OSC_RC32MRDY_bp 1 /* Internal 32 MHz RC Oscillator Ready bit position. */ - -#define OSC_RC2MRDY_bm 0x01 /* Internal 2 MHz RC Oscillator Ready bit mask. */ -#define OSC_RC2MRDY_bp 0 /* Internal 2 MHz RC Oscillator Ready bit position. */ - -/* OSC.XOSCCTRL bit masks and bit positions */ -#define OSC_FRQRANGE_gm 0xC0 /* Frequency Range group mask. */ -#define OSC_FRQRANGE_gp 6 /* Frequency Range group position. */ -#define OSC_FRQRANGE0_bm (1<<6) /* Frequency Range bit 0 mask. */ -#define OSC_FRQRANGE0_bp 6 /* Frequency Range bit 0 position. */ -#define OSC_FRQRANGE1_bm (1<<7) /* Frequency Range bit 1 mask. */ -#define OSC_FRQRANGE1_bp 7 /* Frequency Range bit 1 position. */ - -#define OSC_X32KLPM_bm 0x20 /* 32.768 kHz XTAL OSC Low-power Mode bit mask. */ -#define OSC_X32KLPM_bp 5 /* 32.768 kHz XTAL OSC Low-power Mode bit position. */ - -#define OSC_XOSCPWR_bm 0x10 /* 16 MHz Crystal Oscillator High Power mode bit mask. */ -#define OSC_XOSCPWR_bp 4 /* 16 MHz Crystal Oscillator High Power mode bit position. */ - -#define OSC_XOSCSEL_gm 0x0F /* External Oscillator Selection and Startup Time group mask. */ -#define OSC_XOSCSEL_gp 0 /* External Oscillator Selection and Startup Time group position. */ -#define OSC_XOSCSEL0_bm (1<<0) /* External Oscillator Selection and Startup Time bit 0 mask. */ -#define OSC_XOSCSEL0_bp 0 /* External Oscillator Selection and Startup Time bit 0 position. */ -#define OSC_XOSCSEL1_bm (1<<1) /* External Oscillator Selection and Startup Time bit 1 mask. */ -#define OSC_XOSCSEL1_bp 1 /* External Oscillator Selection and Startup Time bit 1 position. */ -#define OSC_XOSCSEL2_bm (1<<2) /* External Oscillator Selection and Startup Time bit 2 mask. */ -#define OSC_XOSCSEL2_bp 2 /* External Oscillator Selection and Startup Time bit 2 position. */ -#define OSC_XOSCSEL3_bm (1<<3) /* External Oscillator Selection and Startup Time bit 3 mask. */ -#define OSC_XOSCSEL3_bp 3 /* External Oscillator Selection and Startup Time bit 3 position. */ - -/* OSC.XOSCFAIL bit masks and bit positions */ -#define OSC_PLLFDIF_bm 0x08 /* PLL Failure Detection Interrupt Flag bit mask. */ -#define OSC_PLLFDIF_bp 3 /* PLL Failure Detection Interrupt Flag bit position. */ - -#define OSC_PLLFDEN_bm 0x04 /* PLL Failure Detection Enable bit mask. */ -#define OSC_PLLFDEN_bp 2 /* PLL Failure Detection Enable bit position. */ - -#define OSC_XOSCFDIF_bm 0x02 /* XOSC Failure Detection Interrupt Flag bit mask. */ -#define OSC_XOSCFDIF_bp 1 /* XOSC Failure Detection Interrupt Flag bit position. */ - -#define OSC_XOSCFDEN_bm 0x01 /* XOSC Failure Detection Enable bit mask. */ -#define OSC_XOSCFDEN_bp 0 /* XOSC Failure Detection Enable bit position. */ - -/* OSC.PLLCTRL bit masks and bit positions */ -#define OSC_PLLSRC_gm 0xC0 /* Clock Source group mask. */ -#define OSC_PLLSRC_gp 6 /* Clock Source group position. */ -#define OSC_PLLSRC0_bm (1<<6) /* Clock Source bit 0 mask. */ -#define OSC_PLLSRC0_bp 6 /* Clock Source bit 0 position. */ -#define OSC_PLLSRC1_bm (1<<7) /* Clock Source bit 1 mask. */ -#define OSC_PLLSRC1_bp 7 /* Clock Source bit 1 position. */ - -#define OSC_PLLDIV_bm 0x20 /* Divide by 2 bit mask. */ -#define OSC_PLLDIV_bp 5 /* Divide by 2 bit position. */ - -#define OSC_PLLFAC_gm 0x1F /* Multiplication Factor group mask. */ -#define OSC_PLLFAC_gp 0 /* Multiplication Factor group position. */ -#define OSC_PLLFAC0_bm (1<<0) /* Multiplication Factor bit 0 mask. */ -#define OSC_PLLFAC0_bp 0 /* Multiplication Factor bit 0 position. */ -#define OSC_PLLFAC1_bm (1<<1) /* Multiplication Factor bit 1 mask. */ -#define OSC_PLLFAC1_bp 1 /* Multiplication Factor bit 1 position. */ -#define OSC_PLLFAC2_bm (1<<2) /* Multiplication Factor bit 2 mask. */ -#define OSC_PLLFAC2_bp 2 /* Multiplication Factor bit 2 position. */ -#define OSC_PLLFAC3_bm (1<<3) /* Multiplication Factor bit 3 mask. */ -#define OSC_PLLFAC3_bp 3 /* Multiplication Factor bit 3 position. */ -#define OSC_PLLFAC4_bm (1<<4) /* Multiplication Factor bit 4 mask. */ -#define OSC_PLLFAC4_bp 4 /* Multiplication Factor bit 4 position. */ - -/* OSC.DFLLCTRL bit masks and bit positions */ -#define OSC_RC32MCREF_gm 0x06 /* 32 MHz DFLL Calibration Reference group mask. */ -#define OSC_RC32MCREF_gp 1 /* 32 MHz DFLL Calibration Reference group position. */ -#define OSC_RC32MCREF0_bm (1<<1) /* 32 MHz DFLL Calibration Reference bit 0 mask. */ -#define OSC_RC32MCREF0_bp 1 /* 32 MHz DFLL Calibration Reference bit 0 position. */ -#define OSC_RC32MCREF1_bm (1<<2) /* 32 MHz DFLL Calibration Reference bit 1 mask. */ -#define OSC_RC32MCREF1_bp 2 /* 32 MHz DFLL Calibration Reference bit 1 position. */ - -#define OSC_RC2MCREF_bm 0x01 /* 2 MHz DFLL Calibration Reference bit mask. */ -#define OSC_RC2MCREF_bp 0 /* 2 MHz DFLL Calibration Reference bit position. */ - -/* DFLL - DFLL */ -/* DFLL.CTRL bit masks and bit positions */ -#define DFLL_ENABLE_bm 0x01 /* DFLL Enable bit mask. */ -#define DFLL_ENABLE_bp 0 /* DFLL Enable bit position. */ - -/* DFLL.CALA bit masks and bit positions */ -#define DFLL_CALL_gm 0x7F /* DFLL Calibration Value A group mask. */ -#define DFLL_CALL_gp 0 /* DFLL Calibration Value A group position. */ -#define DFLL_CALL0_bm (1<<0) /* DFLL Calibration Value A bit 0 mask. */ -#define DFLL_CALL0_bp 0 /* DFLL Calibration Value A bit 0 position. */ -#define DFLL_CALL1_bm (1<<1) /* DFLL Calibration Value A bit 1 mask. */ -#define DFLL_CALL1_bp 1 /* DFLL Calibration Value A bit 1 position. */ -#define DFLL_CALL2_bm (1<<2) /* DFLL Calibration Value A bit 2 mask. */ -#define DFLL_CALL2_bp 2 /* DFLL Calibration Value A bit 2 position. */ -#define DFLL_CALL3_bm (1<<3) /* DFLL Calibration Value A bit 3 mask. */ -#define DFLL_CALL3_bp 3 /* DFLL Calibration Value A bit 3 position. */ -#define DFLL_CALL4_bm (1<<4) /* DFLL Calibration Value A bit 4 mask. */ -#define DFLL_CALL4_bp 4 /* DFLL Calibration Value A bit 4 position. */ -#define DFLL_CALL5_bm (1<<5) /* DFLL Calibration Value A bit 5 mask. */ -#define DFLL_CALL5_bp 5 /* DFLL Calibration Value A bit 5 position. */ -#define DFLL_CALL6_bm (1<<6) /* DFLL Calibration Value A bit 6 mask. */ -#define DFLL_CALL6_bp 6 /* DFLL Calibration Value A bit 6 position. */ - -/* DFLL.CALB bit masks and bit positions */ -#define DFLL_CALH_gm 0x3F /* DFLL Calibration Value B group mask. */ -#define DFLL_CALH_gp 0 /* DFLL Calibration Value B group position. */ -#define DFLL_CALH0_bm (1<<0) /* DFLL Calibration Value B bit 0 mask. */ -#define DFLL_CALH0_bp 0 /* DFLL Calibration Value B bit 0 position. */ -#define DFLL_CALH1_bm (1<<1) /* DFLL Calibration Value B bit 1 mask. */ -#define DFLL_CALH1_bp 1 /* DFLL Calibration Value B bit 1 position. */ -#define DFLL_CALH2_bm (1<<2) /* DFLL Calibration Value B bit 2 mask. */ -#define DFLL_CALH2_bp 2 /* DFLL Calibration Value B bit 2 position. */ -#define DFLL_CALH3_bm (1<<3) /* DFLL Calibration Value B bit 3 mask. */ -#define DFLL_CALH3_bp 3 /* DFLL Calibration Value B bit 3 position. */ -#define DFLL_CALH4_bm (1<<4) /* DFLL Calibration Value B bit 4 mask. */ -#define DFLL_CALH4_bp 4 /* DFLL Calibration Value B bit 4 position. */ -#define DFLL_CALH5_bm (1<<5) /* DFLL Calibration Value B bit 5 mask. */ -#define DFLL_CALH5_bp 5 /* DFLL Calibration Value B bit 5 position. */ - -/* RST - Reset */ -/* RST.STATUS bit masks and bit positions */ -#define RST_SDRF_bm 0x40 /* Spike Detection Reset Flag bit mask. */ -#define RST_SDRF_bp 6 /* Spike Detection Reset Flag bit position. */ - -#define RST_SRF_bm 0x20 /* Software Reset Flag bit mask. */ -#define RST_SRF_bp 5 /* Software Reset Flag bit position. */ - -#define RST_PDIRF_bm 0x10 /* Programming and Debug Interface Interface Reset Flag bit mask. */ -#define RST_PDIRF_bp 4 /* Programming and Debug Interface Interface Reset Flag bit position. */ - -#define RST_WDRF_bm 0x08 /* Watchdog Reset Flag bit mask. */ -#define RST_WDRF_bp 3 /* Watchdog Reset Flag bit position. */ - -#define RST_BORF_bm 0x04 /* Brown-out Reset Flag bit mask. */ -#define RST_BORF_bp 2 /* Brown-out Reset Flag bit position. */ - -#define RST_EXTRF_bm 0x02 /* External Reset Flag bit mask. */ -#define RST_EXTRF_bp 1 /* External Reset Flag bit position. */ - -#define RST_PORF_bm 0x01 /* Power-on Reset Flag bit mask. */ -#define RST_PORF_bp 0 /* Power-on Reset Flag bit position. */ - -/* RST.CTRL bit masks and bit positions */ -#define RST_SWRST_bm 0x01 /* Software Reset bit mask. */ -#define RST_SWRST_bp 0 /* Software Reset bit position. */ - -/* WDT - Watch-Dog Timer */ -/* WDT.CTRL bit masks and bit positions */ -#define WDT_PER_gm 0x3C /* Period group mask. */ -#define WDT_PER_gp 2 /* Period group position. */ -#define WDT_PER0_bm (1<<2) /* Period bit 0 mask. */ -#define WDT_PER0_bp 2 /* Period bit 0 position. */ -#define WDT_PER1_bm (1<<3) /* Period bit 1 mask. */ -#define WDT_PER1_bp 3 /* Period bit 1 position. */ -#define WDT_PER2_bm (1<<4) /* Period bit 2 mask. */ -#define WDT_PER2_bp 4 /* Period bit 2 position. */ -#define WDT_PER3_bm (1<<5) /* Period bit 3 mask. */ -#define WDT_PER3_bp 5 /* Period bit 3 position. */ - -#define WDT_ENABLE_bm 0x02 /* Enable bit mask. */ -#define WDT_ENABLE_bp 1 /* Enable bit position. */ - -#define WDT_CEN_bm 0x01 /* Change Enable bit mask. */ -#define WDT_CEN_bp 0 /* Change Enable bit position. */ - -/* WDT.WINCTRL bit masks and bit positions */ -#define WDT_WPER_gm 0x3C /* Windowed Mode Period group mask. */ -#define WDT_WPER_gp 2 /* Windowed Mode Period group position. */ -#define WDT_WPER0_bm (1<<2) /* Windowed Mode Period bit 0 mask. */ -#define WDT_WPER0_bp 2 /* Windowed Mode Period bit 0 position. */ -#define WDT_WPER1_bm (1<<3) /* Windowed Mode Period bit 1 mask. */ -#define WDT_WPER1_bp 3 /* Windowed Mode Period bit 1 position. */ -#define WDT_WPER2_bm (1<<4) /* Windowed Mode Period bit 2 mask. */ -#define WDT_WPER2_bp 4 /* Windowed Mode Period bit 2 position. */ -#define WDT_WPER3_bm (1<<5) /* Windowed Mode Period bit 3 mask. */ -#define WDT_WPER3_bp 5 /* Windowed Mode Period bit 3 position. */ - -#define WDT_WEN_bm 0x02 /* Windowed Mode Enable bit mask. */ -#define WDT_WEN_bp 1 /* Windowed Mode Enable bit position. */ - -#define WDT_WCEN_bm 0x01 /* Windowed Mode Change Enable bit mask. */ -#define WDT_WCEN_bp 0 /* Windowed Mode Change Enable bit position. */ - -/* WDT.STATUS bit masks and bit positions */ -#define WDT_SYNCBUSY_bm 0x01 /* Syncronization busy bit mask. */ -#define WDT_SYNCBUSY_bp 0 /* Syncronization busy bit position. */ - -/* MCU - MCU Control */ -/* MCU.MCUCR bit masks and bit positions */ -#define MCU_JTAGD_bm 0x01 /* JTAG Disable bit mask. */ -#define MCU_JTAGD_bp 0 /* JTAG Disable bit position. */ - -/* MCU.ANAINIT bit masks and bit positions */ -#define MCU_STARTUPDLYB_gm 0x0C /* Analog startup delay Port B group mask. */ -#define MCU_STARTUPDLYB_gp 2 /* Analog startup delay Port B group position. */ -#define MCU_STARTUPDLYB0_bm (1<<2) /* Analog startup delay Port B bit 0 mask. */ -#define MCU_STARTUPDLYB0_bp 2 /* Analog startup delay Port B bit 0 position. */ -#define MCU_STARTUPDLYB1_bm (1<<3) /* Analog startup delay Port B bit 1 mask. */ -#define MCU_STARTUPDLYB1_bp 3 /* Analog startup delay Port B bit 1 position. */ - -#define MCU_STARTUPDLYA_gm 0x03 /* Analog startup delay Port A group mask. */ -#define MCU_STARTUPDLYA_gp 0 /* Analog startup delay Port A group position. */ -#define MCU_STARTUPDLYA0_bm (1<<0) /* Analog startup delay Port A bit 0 mask. */ -#define MCU_STARTUPDLYA0_bp 0 /* Analog startup delay Port A bit 0 position. */ -#define MCU_STARTUPDLYA1_bm (1<<1) /* Analog startup delay Port A bit 1 mask. */ -#define MCU_STARTUPDLYA1_bp 1 /* Analog startup delay Port A bit 1 position. */ - -/* MCU.EVSYSLOCK bit masks and bit positions */ -#define MCU_EVSYS1LOCK_bm 0x10 /* Event Channel 4-7 Lock bit mask. */ -#define MCU_EVSYS1LOCK_bp 4 /* Event Channel 4-7 Lock bit position. */ - -#define MCU_EVSYS0LOCK_bm 0x01 /* Event Channel 0-3 Lock bit mask. */ -#define MCU_EVSYS0LOCK_bp 0 /* Event Channel 0-3 Lock bit position. */ - -/* MCU.AWEXLOCK bit masks and bit positions */ -#define MCU_AWEXFLOCK_bm 0x08 /* AWeX on T/C F0 Lock bit mask. */ -#define MCU_AWEXFLOCK_bp 3 /* AWeX on T/C F0 Lock bit position. */ - -#define MCU_AWEXELOCK_bm 0x04 /* AWeX on T/C E0 Lock bit mask. */ -#define MCU_AWEXELOCK_bp 2 /* AWeX on T/C E0 Lock bit position. */ - -#define MCU_AWEXDLOCK_bm 0x02 /* AWeX on T/C D0 Lock bit mask. */ -#define MCU_AWEXDLOCK_bp 1 /* AWeX on T/C D0 Lock bit position. */ - -#define MCU_AWEXCLOCK_bm 0x01 /* AWeX on T/C C0 Lock bit mask. */ -#define MCU_AWEXCLOCK_bp 0 /* AWeX on T/C C0 Lock bit position. */ - -/* PMIC - Programmable Multi-level Interrupt Controller */ -/* PMIC.STATUS bit masks and bit positions */ -#define PMIC_NMIEX_bm 0x80 /* Non-maskable Interrupt Executing bit mask. */ -#define PMIC_NMIEX_bp 7 /* Non-maskable Interrupt Executing bit position. */ - -#define PMIC_HILVLEX_bm 0x04 /* High Level Interrupt Executing bit mask. */ -#define PMIC_HILVLEX_bp 2 /* High Level Interrupt Executing bit position. */ - -#define PMIC_MEDLVLEX_bm 0x02 /* Medium Level Interrupt Executing bit mask. */ -#define PMIC_MEDLVLEX_bp 1 /* Medium Level Interrupt Executing bit position. */ - -#define PMIC_LOLVLEX_bm 0x01 /* Low Level Interrupt Executing bit mask. */ -#define PMIC_LOLVLEX_bp 0 /* Low Level Interrupt Executing bit position. */ - -/* PMIC.INTPRI bit masks and bit positions */ -#define PMIC_INTPRI_gm 0xFF /* Interrupt Priority group mask. */ -#define PMIC_INTPRI_gp 0 /* Interrupt Priority group position. */ -#define PMIC_INTPRI0_bm (1<<0) /* Interrupt Priority bit 0 mask. */ -#define PMIC_INTPRI0_bp 0 /* Interrupt Priority bit 0 position. */ -#define PMIC_INTPRI1_bm (1<<1) /* Interrupt Priority bit 1 mask. */ -#define PMIC_INTPRI1_bp 1 /* Interrupt Priority bit 1 position. */ -#define PMIC_INTPRI2_bm (1<<2) /* Interrupt Priority bit 2 mask. */ -#define PMIC_INTPRI2_bp 2 /* Interrupt Priority bit 2 position. */ -#define PMIC_INTPRI3_bm (1<<3) /* Interrupt Priority bit 3 mask. */ -#define PMIC_INTPRI3_bp 3 /* Interrupt Priority bit 3 position. */ -#define PMIC_INTPRI4_bm (1<<4) /* Interrupt Priority bit 4 mask. */ -#define PMIC_INTPRI4_bp 4 /* Interrupt Priority bit 4 position. */ -#define PMIC_INTPRI5_bm (1<<5) /* Interrupt Priority bit 5 mask. */ -#define PMIC_INTPRI5_bp 5 /* Interrupt Priority bit 5 position. */ -#define PMIC_INTPRI6_bm (1<<6) /* Interrupt Priority bit 6 mask. */ -#define PMIC_INTPRI6_bp 6 /* Interrupt Priority bit 6 position. */ -#define PMIC_INTPRI7_bm (1<<7) /* Interrupt Priority bit 7 mask. */ -#define PMIC_INTPRI7_bp 7 /* Interrupt Priority bit 7 position. */ - -/* PMIC.CTRL bit masks and bit positions */ -#define PMIC_RREN_bm 0x80 /* Round-Robin Priority Enable bit mask. */ -#define PMIC_RREN_bp 7 /* Round-Robin Priority Enable bit position. */ - -#define PMIC_IVSEL_bm 0x40 /* Interrupt Vector Select bit mask. */ -#define PMIC_IVSEL_bp 6 /* Interrupt Vector Select bit position. */ - -#define PMIC_HILVLEN_bm 0x04 /* High Level Enable bit mask. */ -#define PMIC_HILVLEN_bp 2 /* High Level Enable bit position. */ - -#define PMIC_MEDLVLEN_bm 0x02 /* Medium Level Enable bit mask. */ -#define PMIC_MEDLVLEN_bp 1 /* Medium Level Enable bit position. */ - -#define PMIC_LOLVLEN_bm 0x01 /* Low Level Enable bit mask. */ -#define PMIC_LOLVLEN_bp 0 /* Low Level Enable bit position. */ - -/* PORTCFG - Port Configuration */ -/* PORTCFG.VPCTRLA bit masks and bit positions */ -#define PORTCFG_VP1MAP_gm 0xF0 /* Virtual Port 1 Mapping group mask. */ -#define PORTCFG_VP1MAP_gp 4 /* Virtual Port 1 Mapping group position. */ -#define PORTCFG_VP1MAP0_bm (1<<4) /* Virtual Port 1 Mapping bit 0 mask. */ -#define PORTCFG_VP1MAP0_bp 4 /* Virtual Port 1 Mapping bit 0 position. */ -#define PORTCFG_VP1MAP1_bm (1<<5) /* Virtual Port 1 Mapping bit 1 mask. */ -#define PORTCFG_VP1MAP1_bp 5 /* Virtual Port 1 Mapping bit 1 position. */ -#define PORTCFG_VP1MAP2_bm (1<<6) /* Virtual Port 1 Mapping bit 2 mask. */ -#define PORTCFG_VP1MAP2_bp 6 /* Virtual Port 1 Mapping bit 2 position. */ -#define PORTCFG_VP1MAP3_bm (1<<7) /* Virtual Port 1 Mapping bit 3 mask. */ -#define PORTCFG_VP1MAP3_bp 7 /* Virtual Port 1 Mapping bit 3 position. */ - -#define PORTCFG_VP0MAP_gm 0x0F /* Virtual Port 0 Mapping group mask. */ -#define PORTCFG_VP0MAP_gp 0 /* Virtual Port 0 Mapping group position. */ -#define PORTCFG_VP0MAP0_bm (1<<0) /* Virtual Port 0 Mapping bit 0 mask. */ -#define PORTCFG_VP0MAP0_bp 0 /* Virtual Port 0 Mapping bit 0 position. */ -#define PORTCFG_VP0MAP1_bm (1<<1) /* Virtual Port 0 Mapping bit 1 mask. */ -#define PORTCFG_VP0MAP1_bp 1 /* Virtual Port 0 Mapping bit 1 position. */ -#define PORTCFG_VP0MAP2_bm (1<<2) /* Virtual Port 0 Mapping bit 2 mask. */ -#define PORTCFG_VP0MAP2_bp 2 /* Virtual Port 0 Mapping bit 2 position. */ -#define PORTCFG_VP0MAP3_bm (1<<3) /* Virtual Port 0 Mapping bit 3 mask. */ -#define PORTCFG_VP0MAP3_bp 3 /* Virtual Port 0 Mapping bit 3 position. */ - -/* PORTCFG.VPCTRLB bit masks and bit positions */ -#define PORTCFG_VP3MAP_gm 0xF0 /* Virtual Port 3 Mapping group mask. */ -#define PORTCFG_VP3MAP_gp 4 /* Virtual Port 3 Mapping group position. */ -#define PORTCFG_VP3MAP0_bm (1<<4) /* Virtual Port 3 Mapping bit 0 mask. */ -#define PORTCFG_VP3MAP0_bp 4 /* Virtual Port 3 Mapping bit 0 position. */ -#define PORTCFG_VP3MAP1_bm (1<<5) /* Virtual Port 3 Mapping bit 1 mask. */ -#define PORTCFG_VP3MAP1_bp 5 /* Virtual Port 3 Mapping bit 1 position. */ -#define PORTCFG_VP3MAP2_bm (1<<6) /* Virtual Port 3 Mapping bit 2 mask. */ -#define PORTCFG_VP3MAP2_bp 6 /* Virtual Port 3 Mapping bit 2 position. */ -#define PORTCFG_VP3MAP3_bm (1<<7) /* Virtual Port 3 Mapping bit 3 mask. */ -#define PORTCFG_VP3MAP3_bp 7 /* Virtual Port 3 Mapping bit 3 position. */ - -#define PORTCFG_VP2MAP_gm 0x0F /* Virtual Port 2 Mapping group mask. */ -#define PORTCFG_VP2MAP_gp 0 /* Virtual Port 2 Mapping group position. */ -#define PORTCFG_VP2MAP0_bm (1<<0) /* Virtual Port 2 Mapping bit 0 mask. */ -#define PORTCFG_VP2MAP0_bp 0 /* Virtual Port 2 Mapping bit 0 position. */ -#define PORTCFG_VP2MAP1_bm (1<<1) /* Virtual Port 2 Mapping bit 1 mask. */ -#define PORTCFG_VP2MAP1_bp 1 /* Virtual Port 2 Mapping bit 1 position. */ -#define PORTCFG_VP2MAP2_bm (1<<2) /* Virtual Port 2 Mapping bit 2 mask. */ -#define PORTCFG_VP2MAP2_bp 2 /* Virtual Port 2 Mapping bit 2 position. */ -#define PORTCFG_VP2MAP3_bm (1<<3) /* Virtual Port 2 Mapping bit 3 mask. */ -#define PORTCFG_VP2MAP3_bp 3 /* Virtual Port 2 Mapping bit 3 position. */ - -/* PORTCFG.CLKEVOUT bit masks and bit positions */ -#define PORTCFG_CLKOUT_gm 0x03 /* Peripheral Clock Output Port group mask. */ -#define PORTCFG_CLKOUT_gp 0 /* Peripheral Clock Output Port group position. */ -#define PORTCFG_CLKOUT0_bm (1<<0) /* Peripheral Clock Output Port bit 0 mask. */ -#define PORTCFG_CLKOUT0_bp 0 /* Peripheral Clock Output Port bit 0 position. */ -#define PORTCFG_CLKOUT1_bm (1<<1) /* Peripheral Clock Output Port bit 1 mask. */ -#define PORTCFG_CLKOUT1_bp 1 /* Peripheral Clock Output Port bit 1 position. */ - -#define PORTCFG_CLKOUTSEL_gm 0x0C /* Peripheral Clock Output Select group mask. */ -#define PORTCFG_CLKOUTSEL_gp 2 /* Peripheral Clock Output Select group position. */ -#define PORTCFG_CLKOUTSEL0_bm (1<<2) /* Peripheral Clock Output Select bit 0 mask. */ -#define PORTCFG_CLKOUTSEL0_bp 2 /* Peripheral Clock Output Select bit 0 position. */ -#define PORTCFG_CLKOUTSEL1_bm (1<<3) /* Peripheral Clock Output Select bit 1 mask. */ -#define PORTCFG_CLKOUTSEL1_bp 3 /* Peripheral Clock Output Select bit 1 position. */ - -#define PORTCFG_EVOUT_gm 0x30 /* Event Output Port group mask. */ -#define PORTCFG_EVOUT_gp 4 /* Event Output Port group position. */ -#define PORTCFG_EVOUT0_bm (1<<4) /* Event Output Port bit 0 mask. */ -#define PORTCFG_EVOUT0_bp 4 /* Event Output Port bit 0 position. */ -#define PORTCFG_EVOUT1_bm (1<<5) /* Event Output Port bit 1 mask. */ -#define PORTCFG_EVOUT1_bp 5 /* Event Output Port bit 1 position. */ - -#define PORTCFG_RTCOUT_bm 0x40 /* RTC Clock Output bit mask. */ -#define PORTCFG_RTCOUT_bp 6 /* RTC Clock Output bit position. */ - -#define PORTCFG_CLKEVPIN_bm 0x80 /* Peripheral Clock and Event Output pin Select bit mask. */ -#define PORTCFG_CLKEVPIN_bp 7 /* Peripheral Clock and Event Output pin Select bit position. */ - -/* PORTCFG.EBIOUT bit masks and bit positions */ -#define PORTCFG_EBICSOUT_gm 0x03 /* EBI Chip Select Output group mask. */ -#define PORTCFG_EBICSOUT_gp 0 /* EBI Chip Select Output group position. */ -#define PORTCFG_EBICSOUT0_bm (1<<0) /* EBI Chip Select Output bit 0 mask. */ -#define PORTCFG_EBICSOUT0_bp 0 /* EBI Chip Select Output bit 0 position. */ -#define PORTCFG_EBICSOUT1_bm (1<<1) /* EBI Chip Select Output bit 1 mask. */ -#define PORTCFG_EBICSOUT1_bp 1 /* EBI Chip Select Output bit 1 position. */ - -#define PORTCFG_EBIADROUT_gm 0x0C /* EBI Address Output group mask. */ -#define PORTCFG_EBIADROUT_gp 2 /* EBI Address Output group position. */ -#define PORTCFG_EBIADROUT0_bm (1<<2) /* EBI Address Output bit 0 mask. */ -#define PORTCFG_EBIADROUT0_bp 2 /* EBI Address Output bit 0 position. */ -#define PORTCFG_EBIADROUT1_bm (1<<3) /* EBI Address Output bit 1 mask. */ -#define PORTCFG_EBIADROUT1_bp 3 /* EBI Address Output bit 1 position. */ - -/* PORTCFG.EVOUTSEL bit masks and bit positions */ -#define PORTCFG_EVOUTSEL_gm 0x07 /* Event Output Select group mask. */ -#define PORTCFG_EVOUTSEL_gp 0 /* Event Output Select group position. */ -#define PORTCFG_EVOUTSEL0_bm (1<<0) /* Event Output Select bit 0 mask. */ -#define PORTCFG_EVOUTSEL0_bp 0 /* Event Output Select bit 0 position. */ -#define PORTCFG_EVOUTSEL1_bm (1<<1) /* Event Output Select bit 1 mask. */ -#define PORTCFG_EVOUTSEL1_bp 1 /* Event Output Select bit 1 position. */ -#define PORTCFG_EVOUTSEL2_bm (1<<2) /* Event Output Select bit 2 mask. */ -#define PORTCFG_EVOUTSEL2_bp 2 /* Event Output Select bit 2 position. */ - -/* AES - AES Module */ -/* AES.CTRL bit masks and bit positions */ -#define AES_START_bm 0x80 /* Start/Run bit mask. */ -#define AES_START_bp 7 /* Start/Run bit position. */ - -#define AES_AUTO_bm 0x40 /* Auto Start Trigger bit mask. */ -#define AES_AUTO_bp 6 /* Auto Start Trigger bit position. */ - -#define AES_RESET_bm 0x20 /* AES Software Reset bit mask. */ -#define AES_RESET_bp 5 /* AES Software Reset bit position. */ - -#define AES_DECRYPT_bm 0x10 /* Decryption / Direction bit mask. */ -#define AES_DECRYPT_bp 4 /* Decryption / Direction bit position. */ - -#define AES_XOR_bm 0x04 /* State XOR Load Enable bit mask. */ -#define AES_XOR_bp 2 /* State XOR Load Enable bit position. */ - -/* AES.STATUS bit masks and bit positions */ -#define AES_ERROR_bm 0x80 /* AES Error bit mask. */ -#define AES_ERROR_bp 7 /* AES Error bit position. */ - -#define AES_SRIF_bm 0x01 /* State Ready Interrupt Flag bit mask. */ -#define AES_SRIF_bp 0 /* State Ready Interrupt Flag bit position. */ - -/* AES.INTCTRL bit masks and bit positions */ -#define AES_INTLVL_gm 0x03 /* Interrupt level group mask. */ -#define AES_INTLVL_gp 0 /* Interrupt level group position. */ -#define AES_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */ -#define AES_INTLVL0_bp 0 /* Interrupt level bit 0 position. */ -#define AES_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */ -#define AES_INTLVL1_bp 1 /* Interrupt level bit 1 position. */ - -/* CRC - Cyclic Redundancy Checker */ -/* CRC.CTRL bit masks and bit positions */ -#define CRC_RESET_gm 0xC0 /* Reset group mask. */ -#define CRC_RESET_gp 6 /* Reset group position. */ -#define CRC_RESET0_bm (1<<6) /* Reset bit 0 mask. */ -#define CRC_RESET0_bp 6 /* Reset bit 0 position. */ -#define CRC_RESET1_bm (1<<7) /* Reset bit 1 mask. */ -#define CRC_RESET1_bp 7 /* Reset bit 1 position. */ - -#define CRC_CRC32_bm 0x20 /* CRC Mode bit mask. */ -#define CRC_CRC32_bp 5 /* CRC Mode bit position. */ - -#define CRC_SOURCE_gm 0x0F /* Input Source group mask. */ -#define CRC_SOURCE_gp 0 /* Input Source group position. */ -#define CRC_SOURCE0_bm (1<<0) /* Input Source bit 0 mask. */ -#define CRC_SOURCE0_bp 0 /* Input Source bit 0 position. */ -#define CRC_SOURCE1_bm (1<<1) /* Input Source bit 1 mask. */ -#define CRC_SOURCE1_bp 1 /* Input Source bit 1 position. */ -#define CRC_SOURCE2_bm (1<<2) /* Input Source bit 2 mask. */ -#define CRC_SOURCE2_bp 2 /* Input Source bit 2 position. */ -#define CRC_SOURCE3_bm (1<<3) /* Input Source bit 3 mask. */ -#define CRC_SOURCE3_bp 3 /* Input Source bit 3 position. */ - -/* CRC.STATUS bit masks and bit positions */ -#define CRC_ZERO_bm 0x02 /* Zero detection bit mask. */ -#define CRC_ZERO_bp 1 /* Zero detection bit position. */ - -#define CRC_BUSY_bm 0x01 /* Busy bit mask. */ -#define CRC_BUSY_bp 0 /* Busy bit position. */ - -/* DMA - DMA Controller */ -/* DMA_CH.CTRLA bit masks and bit positions */ -#define DMA_CH_ENABLE_bm 0x80 /* Channel Enable bit mask. */ -#define DMA_CH_ENABLE_bp 7 /* Channel Enable bit position. */ - -#define DMA_CH_RESET_bm 0x40 /* Channel Software Reset bit mask. */ -#define DMA_CH_RESET_bp 6 /* Channel Software Reset bit position. */ - -#define DMA_CH_REPEAT_bm 0x20 /* Channel Repeat Mode bit mask. */ -#define DMA_CH_REPEAT_bp 5 /* Channel Repeat Mode bit position. */ - -#define DMA_CH_TRFREQ_bm 0x10 /* Channel Transfer Request bit mask. */ -#define DMA_CH_TRFREQ_bp 4 /* Channel Transfer Request bit position. */ - -#define DMA_CH_SINGLE_bm 0x04 /* Channel Single Shot Data Transfer bit mask. */ -#define DMA_CH_SINGLE_bp 2 /* Channel Single Shot Data Transfer bit position. */ - -#define DMA_CH_BURSTLEN_gm 0x03 /* Channel Transfer Mode group mask. */ -#define DMA_CH_BURSTLEN_gp 0 /* Channel Transfer Mode group position. */ -#define DMA_CH_BURSTLEN0_bm (1<<0) /* Channel Transfer Mode bit 0 mask. */ -#define DMA_CH_BURSTLEN0_bp 0 /* Channel Transfer Mode bit 0 position. */ -#define DMA_CH_BURSTLEN1_bm (1<<1) /* Channel Transfer Mode bit 1 mask. */ -#define DMA_CH_BURSTLEN1_bp 1 /* Channel Transfer Mode bit 1 position. */ - -/* DMA_CH.CTRLB bit masks and bit positions */ -#define DMA_CH_CHBUSY_bm 0x80 /* Block Transfer Busy bit mask. */ -#define DMA_CH_CHBUSY_bp 7 /* Block Transfer Busy bit position. */ - -#define DMA_CH_CHPEND_bm 0x40 /* Block Transfer Pending bit mask. */ -#define DMA_CH_CHPEND_bp 6 /* Block Transfer Pending bit position. */ - -#define DMA_CH_ERRIF_bm 0x20 /* Block Transfer Error Interrupt Flag bit mask. */ -#define DMA_CH_ERRIF_bp 5 /* Block Transfer Error Interrupt Flag bit position. */ - -#define DMA_CH_TRNIF_bm 0x10 /* Transaction Complete Interrup Flag bit mask. */ -#define DMA_CH_TRNIF_bp 4 /* Transaction Complete Interrup Flag bit position. */ - -#define DMA_CH_ERRINTLVL_gm 0x0C /* Transfer Error Interrupt Level group mask. */ -#define DMA_CH_ERRINTLVL_gp 2 /* Transfer Error Interrupt Level group position. */ -#define DMA_CH_ERRINTLVL0_bm (1<<2) /* Transfer Error Interrupt Level bit 0 mask. */ -#define DMA_CH_ERRINTLVL0_bp 2 /* Transfer Error Interrupt Level bit 0 position. */ -#define DMA_CH_ERRINTLVL1_bm (1<<3) /* Transfer Error Interrupt Level bit 1 mask. */ -#define DMA_CH_ERRINTLVL1_bp 3 /* Transfer Error Interrupt Level bit 1 position. */ - -#define DMA_CH_TRNINTLVL_gm 0x03 /* Transaction Complete Interrupt Level group mask. */ -#define DMA_CH_TRNINTLVL_gp 0 /* Transaction Complete Interrupt Level group position. */ -#define DMA_CH_TRNINTLVL0_bm (1<<0) /* Transaction Complete Interrupt Level bit 0 mask. */ -#define DMA_CH_TRNINTLVL0_bp 0 /* Transaction Complete Interrupt Level bit 0 position. */ -#define DMA_CH_TRNINTLVL1_bm (1<<1) /* Transaction Complete Interrupt Level bit 1 mask. */ -#define DMA_CH_TRNINTLVL1_bp 1 /* Transaction Complete Interrupt Level bit 1 position. */ - -/* DMA_CH.ADDRCTRL bit masks and bit positions */ -#define DMA_CH_SRCRELOAD_gm 0xC0 /* Channel Source Address Reload group mask. */ -#define DMA_CH_SRCRELOAD_gp 6 /* Channel Source Address Reload group position. */ -#define DMA_CH_SRCRELOAD0_bm (1<<6) /* Channel Source Address Reload bit 0 mask. */ -#define DMA_CH_SRCRELOAD0_bp 6 /* Channel Source Address Reload bit 0 position. */ -#define DMA_CH_SRCRELOAD1_bm (1<<7) /* Channel Source Address Reload bit 1 mask. */ -#define DMA_CH_SRCRELOAD1_bp 7 /* Channel Source Address Reload bit 1 position. */ - -#define DMA_CH_SRCDIR_gm 0x30 /* Channel Source Address Mode group mask. */ -#define DMA_CH_SRCDIR_gp 4 /* Channel Source Address Mode group position. */ -#define DMA_CH_SRCDIR0_bm (1<<4) /* Channel Source Address Mode bit 0 mask. */ -#define DMA_CH_SRCDIR0_bp 4 /* Channel Source Address Mode bit 0 position. */ -#define DMA_CH_SRCDIR1_bm (1<<5) /* Channel Source Address Mode bit 1 mask. */ -#define DMA_CH_SRCDIR1_bp 5 /* Channel Source Address Mode bit 1 position. */ - -#define DMA_CH_DESTRELOAD_gm 0x0C /* Channel Destination Address Reload group mask. */ -#define DMA_CH_DESTRELOAD_gp 2 /* Channel Destination Address Reload group position. */ -#define DMA_CH_DESTRELOAD0_bm (1<<2) /* Channel Destination Address Reload bit 0 mask. */ -#define DMA_CH_DESTRELOAD0_bp 2 /* Channel Destination Address Reload bit 0 position. */ -#define DMA_CH_DESTRELOAD1_bm (1<<3) /* Channel Destination Address Reload bit 1 mask. */ -#define DMA_CH_DESTRELOAD1_bp 3 /* Channel Destination Address Reload bit 1 position. */ - -#define DMA_CH_DESTDIR_gm 0x03 /* Channel Destination Address Mode group mask. */ -#define DMA_CH_DESTDIR_gp 0 /* Channel Destination Address Mode group position. */ -#define DMA_CH_DESTDIR0_bm (1<<0) /* Channel Destination Address Mode bit 0 mask. */ -#define DMA_CH_DESTDIR0_bp 0 /* Channel Destination Address Mode bit 0 position. */ -#define DMA_CH_DESTDIR1_bm (1<<1) /* Channel Destination Address Mode bit 1 mask. */ -#define DMA_CH_DESTDIR1_bp 1 /* Channel Destination Address Mode bit 1 position. */ - -/* DMA_CH.TRIGSRC bit masks and bit positions */ -#define DMA_CH_TRIGSRC_gm 0xFF /* Channel Trigger Source group mask. */ -#define DMA_CH_TRIGSRC_gp 0 /* Channel Trigger Source group position. */ -#define DMA_CH_TRIGSRC0_bm (1<<0) /* Channel Trigger Source bit 0 mask. */ -#define DMA_CH_TRIGSRC0_bp 0 /* Channel Trigger Source bit 0 position. */ -#define DMA_CH_TRIGSRC1_bm (1<<1) /* Channel Trigger Source bit 1 mask. */ -#define DMA_CH_TRIGSRC1_bp 1 /* Channel Trigger Source bit 1 position. */ -#define DMA_CH_TRIGSRC2_bm (1<<2) /* Channel Trigger Source bit 2 mask. */ -#define DMA_CH_TRIGSRC2_bp 2 /* Channel Trigger Source bit 2 position. */ -#define DMA_CH_TRIGSRC3_bm (1<<3) /* Channel Trigger Source bit 3 mask. */ -#define DMA_CH_TRIGSRC3_bp 3 /* Channel Trigger Source bit 3 position. */ -#define DMA_CH_TRIGSRC4_bm (1<<4) /* Channel Trigger Source bit 4 mask. */ -#define DMA_CH_TRIGSRC4_bp 4 /* Channel Trigger Source bit 4 position. */ -#define DMA_CH_TRIGSRC5_bm (1<<5) /* Channel Trigger Source bit 5 mask. */ -#define DMA_CH_TRIGSRC5_bp 5 /* Channel Trigger Source bit 5 position. */ -#define DMA_CH_TRIGSRC6_bm (1<<6) /* Channel Trigger Source bit 6 mask. */ -#define DMA_CH_TRIGSRC6_bp 6 /* Channel Trigger Source bit 6 position. */ -#define DMA_CH_TRIGSRC7_bm (1<<7) /* Channel Trigger Source bit 7 mask. */ -#define DMA_CH_TRIGSRC7_bp 7 /* Channel Trigger Source bit 7 position. */ - -/* DMA.CTRL bit masks and bit positions */ -#define DMA_ENABLE_bm 0x80 /* Enable bit mask. */ -#define DMA_ENABLE_bp 7 /* Enable bit position. */ - -#define DMA_RESET_bm 0x40 /* Software Reset bit mask. */ -#define DMA_RESET_bp 6 /* Software Reset bit position. */ - -#define DMA_DBUFMODE_gm 0x0C /* Double Buffering Mode group mask. */ -#define DMA_DBUFMODE_gp 2 /* Double Buffering Mode group position. */ -#define DMA_DBUFMODE0_bm (1<<2) /* Double Buffering Mode bit 0 mask. */ -#define DMA_DBUFMODE0_bp 2 /* Double Buffering Mode bit 0 position. */ -#define DMA_DBUFMODE1_bm (1<<3) /* Double Buffering Mode bit 1 mask. */ -#define DMA_DBUFMODE1_bp 3 /* Double Buffering Mode bit 1 position. */ - -#define DMA_PRIMODE_gm 0x03 /* Channel Priority Mode group mask. */ -#define DMA_PRIMODE_gp 0 /* Channel Priority Mode group position. */ -#define DMA_PRIMODE0_bm (1<<0) /* Channel Priority Mode bit 0 mask. */ -#define DMA_PRIMODE0_bp 0 /* Channel Priority Mode bit 0 position. */ -#define DMA_PRIMODE1_bm (1<<1) /* Channel Priority Mode bit 1 mask. */ -#define DMA_PRIMODE1_bp 1 /* Channel Priority Mode bit 1 position. */ - -/* DMA.INTFLAGS bit masks and bit positions */ -#define DMA_CH3ERRIF_bm 0x80 /* Channel 3 Block Transfer Error Interrupt Flag bit mask. */ -#define DMA_CH3ERRIF_bp 7 /* Channel 3 Block Transfer Error Interrupt Flag bit position. */ - -#define DMA_CH2ERRIF_bm 0x40 /* Channel 2 Block Transfer Error Interrupt Flag bit mask. */ -#define DMA_CH2ERRIF_bp 6 /* Channel 2 Block Transfer Error Interrupt Flag bit position. */ - -#define DMA_CH1ERRIF_bm 0x20 /* Channel 1 Block Transfer Error Interrupt Flag bit mask. */ -#define DMA_CH1ERRIF_bp 5 /* Channel 1 Block Transfer Error Interrupt Flag bit position. */ - -#define DMA_CH0ERRIF_bm 0x10 /* Channel 0 Block Transfer Error Interrupt Flag bit mask. */ -#define DMA_CH0ERRIF_bp 4 /* Channel 0 Block Transfer Error Interrupt Flag bit position. */ - -#define DMA_CH3TRNIF_bm 0x08 /* Channel 3 Transaction Complete Interrupt Flag bit mask. */ -#define DMA_CH3TRNIF_bp 3 /* Channel 3 Transaction Complete Interrupt Flag bit position. */ - -#define DMA_CH2TRNIF_bm 0x04 /* Channel 2 Transaction Complete Interrupt Flag bit mask. */ -#define DMA_CH2TRNIF_bp 2 /* Channel 2 Transaction Complete Interrupt Flag bit position. */ - -#define DMA_CH1TRNIF_bm 0x02 /* Channel 1 Transaction Complete Interrupt Flag bit mask. */ -#define DMA_CH1TRNIF_bp 1 /* Channel 1 Transaction Complete Interrupt Flag bit position. */ - -#define DMA_CH0TRNIF_bm 0x01 /* Channel 0 Transaction Complete Interrupt Flag bit mask. */ -#define DMA_CH0TRNIF_bp 0 /* Channel 0 Transaction Complete Interrupt Flag bit position. */ - -/* DMA.STATUS bit masks and bit positions */ -#define DMA_CH3BUSY_bm 0x80 /* Channel 3 Block Transfer Busy bit mask. */ -#define DMA_CH3BUSY_bp 7 /* Channel 3 Block Transfer Busy bit position. */ - -#define DMA_CH2BUSY_bm 0x40 /* Channel 2 Block Transfer Busy bit mask. */ -#define DMA_CH2BUSY_bp 6 /* Channel 2 Block Transfer Busy bit position. */ - -#define DMA_CH1BUSY_bm 0x20 /* Channel 1 Block Transfer Busy bit mask. */ -#define DMA_CH1BUSY_bp 5 /* Channel 1 Block Transfer Busy bit position. */ - -#define DMA_CH0BUSY_bm 0x10 /* Channel 0 Block Transfer Busy bit mask. */ -#define DMA_CH0BUSY_bp 4 /* Channel 0 Block Transfer Busy bit position. */ - -#define DMA_CH3PEND_bm 0x08 /* Channel 3 Block Transfer Pending bit mask. */ -#define DMA_CH3PEND_bp 3 /* Channel 3 Block Transfer Pending bit position. */ - -#define DMA_CH2PEND_bm 0x04 /* Channel 2 Block Transfer Pending bit mask. */ -#define DMA_CH2PEND_bp 2 /* Channel 2 Block Transfer Pending bit position. */ - -#define DMA_CH1PEND_bm 0x02 /* Channel 1 Block Transfer Pending bit mask. */ -#define DMA_CH1PEND_bp 1 /* Channel 1 Block Transfer Pending bit position. */ - -#define DMA_CH0PEND_bm 0x01 /* Channel 0 Block Transfer Pending bit mask. */ -#define DMA_CH0PEND_bp 0 /* Channel 0 Block Transfer Pending bit position. */ - -/* EVSYS - Event System */ -/* EVSYS.CH0MUX bit masks and bit positions */ -#define EVSYS_CHMUX_gm 0xFF /* Event Channel 0 Multiplexer group mask. */ -#define EVSYS_CHMUX_gp 0 /* Event Channel 0 Multiplexer group position. */ -#define EVSYS_CHMUX0_bm (1<<0) /* Event Channel 0 Multiplexer bit 0 mask. */ -#define EVSYS_CHMUX0_bp 0 /* Event Channel 0 Multiplexer bit 0 position. */ -#define EVSYS_CHMUX1_bm (1<<1) /* Event Channel 0 Multiplexer bit 1 mask. */ -#define EVSYS_CHMUX1_bp 1 /* Event Channel 0 Multiplexer bit 1 position. */ -#define EVSYS_CHMUX2_bm (1<<2) /* Event Channel 0 Multiplexer bit 2 mask. */ -#define EVSYS_CHMUX2_bp 2 /* Event Channel 0 Multiplexer bit 2 position. */ -#define EVSYS_CHMUX3_bm (1<<3) /* Event Channel 0 Multiplexer bit 3 mask. */ -#define EVSYS_CHMUX3_bp 3 /* Event Channel 0 Multiplexer bit 3 position. */ -#define EVSYS_CHMUX4_bm (1<<4) /* Event Channel 0 Multiplexer bit 4 mask. */ -#define EVSYS_CHMUX4_bp 4 /* Event Channel 0 Multiplexer bit 4 position. */ -#define EVSYS_CHMUX5_bm (1<<5) /* Event Channel 0 Multiplexer bit 5 mask. */ -#define EVSYS_CHMUX5_bp 5 /* Event Channel 0 Multiplexer bit 5 position. */ -#define EVSYS_CHMUX6_bm (1<<6) /* Event Channel 0 Multiplexer bit 6 mask. */ -#define EVSYS_CHMUX6_bp 6 /* Event Channel 0 Multiplexer bit 6 position. */ -#define EVSYS_CHMUX7_bm (1<<7) /* Event Channel 0 Multiplexer bit 7 mask. */ -#define EVSYS_CHMUX7_bp 7 /* Event Channel 0 Multiplexer bit 7 position. */ - -/* EVSYS.CH1MUX bit masks and bit positions */ -/* EVSYS_CHMUX Predefined. */ -/* EVSYS_CHMUX Predefined. */ - -/* EVSYS.CH2MUX bit masks and bit positions */ -/* EVSYS_CHMUX Predefined. */ -/* EVSYS_CHMUX Predefined. */ - -/* EVSYS.CH3MUX bit masks and bit positions */ -/* EVSYS_CHMUX Predefined. */ -/* EVSYS_CHMUX Predefined. */ - -/* EVSYS.CH4MUX bit masks and bit positions */ -/* EVSYS_CHMUX Predefined. */ -/* EVSYS_CHMUX Predefined. */ - -/* EVSYS.CH5MUX bit masks and bit positions */ -/* EVSYS_CHMUX Predefined. */ -/* EVSYS_CHMUX Predefined. */ - -/* EVSYS.CH6MUX bit masks and bit positions */ -/* EVSYS_CHMUX Predefined. */ -/* EVSYS_CHMUX Predefined. */ - -/* EVSYS.CH7MUX bit masks and bit positions */ -/* EVSYS_CHMUX Predefined. */ -/* EVSYS_CHMUX Predefined. */ - -/* EVSYS.CH0CTRL bit masks and bit positions */ -#define EVSYS_QDIRM_gm 0x60 /* Quadrature Decoder Index Recognition Mode group mask. */ -#define EVSYS_QDIRM_gp 5 /* Quadrature Decoder Index Recognition Mode group position. */ -#define EVSYS_QDIRM0_bm (1<<5) /* Quadrature Decoder Index Recognition Mode bit 0 mask. */ -#define EVSYS_QDIRM0_bp 5 /* Quadrature Decoder Index Recognition Mode bit 0 position. */ -#define EVSYS_QDIRM1_bm (1<<6) /* Quadrature Decoder Index Recognition Mode bit 1 mask. */ -#define EVSYS_QDIRM1_bp 6 /* Quadrature Decoder Index Recognition Mode bit 1 position. */ - -#define EVSYS_QDIEN_bm 0x10 /* Quadrature Decoder Index Enable bit mask. */ -#define EVSYS_QDIEN_bp 4 /* Quadrature Decoder Index Enable bit position. */ - -#define EVSYS_QDEN_bm 0x08 /* Quadrature Decoder Enable bit mask. */ -#define EVSYS_QDEN_bp 3 /* Quadrature Decoder Enable bit position. */ - -#define EVSYS_DIGFILT_gm 0x07 /* Digital Filter group mask. */ -#define EVSYS_DIGFILT_gp 0 /* Digital Filter group position. */ -#define EVSYS_DIGFILT0_bm (1<<0) /* Digital Filter bit 0 mask. */ -#define EVSYS_DIGFILT0_bp 0 /* Digital Filter bit 0 position. */ -#define EVSYS_DIGFILT1_bm (1<<1) /* Digital Filter bit 1 mask. */ -#define EVSYS_DIGFILT1_bp 1 /* Digital Filter bit 1 position. */ -#define EVSYS_DIGFILT2_bm (1<<2) /* Digital Filter bit 2 mask. */ -#define EVSYS_DIGFILT2_bp 2 /* Digital Filter bit 2 position. */ - -/* EVSYS.CH1CTRL bit masks and bit positions */ -/* EVSYS_DIGFILT Predefined. */ -/* EVSYS_DIGFILT Predefined. */ - -/* EVSYS.CH2CTRL bit masks and bit positions */ -/* EVSYS_QDIRM Predefined. */ -/* EVSYS_QDIRM Predefined. */ - -/* EVSYS_QDIEN Predefined. */ -/* EVSYS_QDIEN Predefined. */ - -/* EVSYS_QDEN Predefined. */ -/* EVSYS_QDEN Predefined. */ - -/* EVSYS_DIGFILT Predefined. */ -/* EVSYS_DIGFILT Predefined. */ - -/* EVSYS.CH3CTRL bit masks and bit positions */ -/* EVSYS_DIGFILT Predefined. */ -/* EVSYS_DIGFILT Predefined. */ - -/* EVSYS.CH4CTRL bit masks and bit positions */ -/* EVSYS_QDIRM Predefined. */ -/* EVSYS_QDIRM Predefined. */ - -/* EVSYS_QDIEN Predefined. */ -/* EVSYS_QDIEN Predefined. */ - -/* EVSYS_QDEN Predefined. */ -/* EVSYS_QDEN Predefined. */ - -/* EVSYS_DIGFILT Predefined. */ -/* EVSYS_DIGFILT Predefined. */ - -/* EVSYS.CH5CTRL bit masks and bit positions */ -/* EVSYS_DIGFILT Predefined. */ -/* EVSYS_DIGFILT Predefined. */ - -/* EVSYS.CH6CTRL bit masks and bit positions */ -/* EVSYS_DIGFILT Predefined. */ -/* EVSYS_DIGFILT Predefined. */ - -/* EVSYS.CH7CTRL bit masks and bit positions */ -/* EVSYS_DIGFILT Predefined. */ -/* EVSYS_DIGFILT Predefined. */ - -/* NVM - Non Volatile Memory Controller */ -/* NVM.CMD bit masks and bit positions */ -#define NVM_CMD_gm 0x7F /* Command group mask. */ -#define NVM_CMD_gp 0 /* Command group position. */ -#define NVM_CMD0_bm (1<<0) /* Command bit 0 mask. */ -#define NVM_CMD0_bp 0 /* Command bit 0 position. */ -#define NVM_CMD1_bm (1<<1) /* Command bit 1 mask. */ -#define NVM_CMD1_bp 1 /* Command bit 1 position. */ -#define NVM_CMD2_bm (1<<2) /* Command bit 2 mask. */ -#define NVM_CMD2_bp 2 /* Command bit 2 position. */ -#define NVM_CMD3_bm (1<<3) /* Command bit 3 mask. */ -#define NVM_CMD3_bp 3 /* Command bit 3 position. */ -#define NVM_CMD4_bm (1<<4) /* Command bit 4 mask. */ -#define NVM_CMD4_bp 4 /* Command bit 4 position. */ -#define NVM_CMD5_bm (1<<5) /* Command bit 5 mask. */ -#define NVM_CMD5_bp 5 /* Command bit 5 position. */ -#define NVM_CMD6_bm (1<<6) /* Command bit 6 mask. */ -#define NVM_CMD6_bp 6 /* Command bit 6 position. */ - -/* NVM.CTRLA bit masks and bit positions */ -#define NVM_CMDEX_bm 0x01 /* Command Execute bit mask. */ -#define NVM_CMDEX_bp 0 /* Command Execute bit position. */ - -/* NVM.CTRLB bit masks and bit positions */ -#define NVM_EEMAPEN_bm 0x08 /* EEPROM Mapping Enable bit mask. */ -#define NVM_EEMAPEN_bp 3 /* EEPROM Mapping Enable bit position. */ - -#define NVM_FPRM_bm 0x04 /* Flash Power Reduction Enable bit mask. */ -#define NVM_FPRM_bp 2 /* Flash Power Reduction Enable bit position. */ - -#define NVM_EPRM_bm 0x02 /* EEPROM Power Reduction Enable bit mask. */ -#define NVM_EPRM_bp 1 /* EEPROM Power Reduction Enable bit position. */ - -#define NVM_SPMLOCK_bm 0x01 /* SPM Lock bit mask. */ -#define NVM_SPMLOCK_bp 0 /* SPM Lock bit position. */ - -/* NVM.INTCTRL bit masks and bit positions */ -#define NVM_SPMLVL_gm 0x0C /* SPM Interrupt Level group mask. */ -#define NVM_SPMLVL_gp 2 /* SPM Interrupt Level group position. */ -#define NVM_SPMLVL0_bm (1<<2) /* SPM Interrupt Level bit 0 mask. */ -#define NVM_SPMLVL0_bp 2 /* SPM Interrupt Level bit 0 position. */ -#define NVM_SPMLVL1_bm (1<<3) /* SPM Interrupt Level bit 1 mask. */ -#define NVM_SPMLVL1_bp 3 /* SPM Interrupt Level bit 1 position. */ - -#define NVM_EELVL_gm 0x03 /* EEPROM Interrupt Level group mask. */ -#define NVM_EELVL_gp 0 /* EEPROM Interrupt Level group position. */ -#define NVM_EELVL0_bm (1<<0) /* EEPROM Interrupt Level bit 0 mask. */ -#define NVM_EELVL0_bp 0 /* EEPROM Interrupt Level bit 0 position. */ -#define NVM_EELVL1_bm (1<<1) /* EEPROM Interrupt Level bit 1 mask. */ -#define NVM_EELVL1_bp 1 /* EEPROM Interrupt Level bit 1 position. */ - -/* NVM.STATUS bit masks and bit positions */ -#define NVM_NVMBUSY_bm 0x80 /* Non-volatile Memory Busy bit mask. */ -#define NVM_NVMBUSY_bp 7 /* Non-volatile Memory Busy bit position. */ - -#define NVM_FBUSY_bm 0x40 /* Flash Memory Busy bit mask. */ -#define NVM_FBUSY_bp 6 /* Flash Memory Busy bit position. */ - -#define NVM_EELOAD_bm 0x02 /* EEPROM Page Buffer Active Loading bit mask. */ -#define NVM_EELOAD_bp 1 /* EEPROM Page Buffer Active Loading bit position. */ - -#define NVM_FLOAD_bm 0x01 /* Flash Page Buffer Active Loading bit mask. */ -#define NVM_FLOAD_bp 0 /* Flash Page Buffer Active Loading bit position. */ - -/* NVM.LOCKBITS bit masks and bit positions */ -#define NVM_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ -#define NVM_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ -#define NVM_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ -#define NVM_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ -#define NVM_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ -#define NVM_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ - -#define NVM_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ -#define NVM_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ -#define NVM_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ -#define NVM_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ -#define NVM_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ -#define NVM_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ - -#define NVM_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ -#define NVM_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ -#define NVM_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ -#define NVM_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ -#define NVM_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ -#define NVM_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ - -#define NVM_LB_gm 0x03 /* Lock Bits group mask. */ -#define NVM_LB_gp 0 /* Lock Bits group position. */ -#define NVM_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ -#define NVM_LB0_bp 0 /* Lock Bits bit 0 position. */ -#define NVM_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ -#define NVM_LB1_bp 1 /* Lock Bits bit 1 position. */ - -/* ADC - Analog/Digital Converter */ -/* ADC_CH.CTRL bit masks and bit positions */ -#define ADC_CH_START_bm 0x80 /* Channel Start Conversion bit mask. */ -#define ADC_CH_START_bp 7 /* Channel Start Conversion bit position. */ - -#define ADC_CH_GAIN_gm 0x1C /* Gain Factor group mask. */ -#define ADC_CH_GAIN_gp 2 /* Gain Factor group position. */ -#define ADC_CH_GAIN0_bm (1<<2) /* Gain Factor bit 0 mask. */ -#define ADC_CH_GAIN0_bp 2 /* Gain Factor bit 0 position. */ -#define ADC_CH_GAIN1_bm (1<<3) /* Gain Factor bit 1 mask. */ -#define ADC_CH_GAIN1_bp 3 /* Gain Factor bit 1 position. */ -#define ADC_CH_GAIN2_bm (1<<4) /* Gain Factor bit 2 mask. */ -#define ADC_CH_GAIN2_bp 4 /* Gain Factor bit 2 position. */ - -#define ADC_CH_INPUTMODE_gm 0x03 /* Input Mode Select group mask. */ -#define ADC_CH_INPUTMODE_gp 0 /* Input Mode Select group position. */ -#define ADC_CH_INPUTMODE0_bm (1<<0) /* Input Mode Select bit 0 mask. */ -#define ADC_CH_INPUTMODE0_bp 0 /* Input Mode Select bit 0 position. */ -#define ADC_CH_INPUTMODE1_bm (1<<1) /* Input Mode Select bit 1 mask. */ -#define ADC_CH_INPUTMODE1_bp 1 /* Input Mode Select bit 1 position. */ - -/* ADC_CH.MUXCTRL bit masks and bit positions */ -#define ADC_CH_MUXPOS_gm 0x78 /* MUX selection on Positive ADC input group mask. */ -#define ADC_CH_MUXPOS_gp 3 /* MUX selection on Positive ADC input group position. */ -#define ADC_CH_MUXPOS0_bm (1<<3) /* MUX selection on Positive ADC input bit 0 mask. */ -#define ADC_CH_MUXPOS0_bp 3 /* MUX selection on Positive ADC input bit 0 position. */ -#define ADC_CH_MUXPOS1_bm (1<<4) /* MUX selection on Positive ADC input bit 1 mask. */ -#define ADC_CH_MUXPOS1_bp 4 /* MUX selection on Positive ADC input bit 1 position. */ -#define ADC_CH_MUXPOS2_bm (1<<5) /* MUX selection on Positive ADC input bit 2 mask. */ -#define ADC_CH_MUXPOS2_bp 5 /* MUX selection on Positive ADC input bit 2 position. */ -#define ADC_CH_MUXPOS3_bm (1<<6) /* MUX selection on Positive ADC input bit 3 mask. */ -#define ADC_CH_MUXPOS3_bp 6 /* MUX selection on Positive ADC input bit 3 position. */ - -#define ADC_CH_MUXINT_gm 0x78 /* MUX selection on Internal ADC input group mask. */ -#define ADC_CH_MUXINT_gp 3 /* MUX selection on Internal ADC input group position. */ -#define ADC_CH_MUXINT0_bm (1<<3) /* MUX selection on Internal ADC input bit 0 mask. */ -#define ADC_CH_MUXINT0_bp 3 /* MUX selection on Internal ADC input bit 0 position. */ -#define ADC_CH_MUXINT1_bm (1<<4) /* MUX selection on Internal ADC input bit 1 mask. */ -#define ADC_CH_MUXINT1_bp 4 /* MUX selection on Internal ADC input bit 1 position. */ -#define ADC_CH_MUXINT2_bm (1<<5) /* MUX selection on Internal ADC input bit 2 mask. */ -#define ADC_CH_MUXINT2_bp 5 /* MUX selection on Internal ADC input bit 2 position. */ -#define ADC_CH_MUXINT3_bm (1<<6) /* MUX selection on Internal ADC input bit 3 mask. */ -#define ADC_CH_MUXINT3_bp 6 /* MUX selection on Internal ADC input bit 3 position. */ - -#define ADC_CH_MUXNEG_gm 0x07 /* MUX selection on Negative ADC input group mask. */ -#define ADC_CH_MUXNEG_gp 0 /* MUX selection on Negative ADC input group position. */ -#define ADC_CH_MUXNEG0_bm (1<<0) /* MUX selection on Negative ADC input bit 0 mask. */ -#define ADC_CH_MUXNEG0_bp 0 /* MUX selection on Negative ADC input bit 0 position. */ -#define ADC_CH_MUXNEG1_bm (1<<1) /* MUX selection on Negative ADC input bit 1 mask. */ -#define ADC_CH_MUXNEG1_bp 1 /* MUX selection on Negative ADC input bit 1 position. */ -#define ADC_CH_MUXNEG2_bm (1<<2) /* MUX selection on Negative ADC input bit 2 mask. */ -#define ADC_CH_MUXNEG2_bp 2 /* MUX selection on Negative ADC input bit 2 position. */ - -/* ADC_CH.INTCTRL bit masks and bit positions */ -#define ADC_CH_INTMODE_gm 0x0C /* Interrupt Mode group mask. */ -#define ADC_CH_INTMODE_gp 2 /* Interrupt Mode group position. */ -#define ADC_CH_INTMODE0_bm (1<<2) /* Interrupt Mode bit 0 mask. */ -#define ADC_CH_INTMODE0_bp 2 /* Interrupt Mode bit 0 position. */ -#define ADC_CH_INTMODE1_bm (1<<3) /* Interrupt Mode bit 1 mask. */ -#define ADC_CH_INTMODE1_bp 3 /* Interrupt Mode bit 1 position. */ - -#define ADC_CH_INTLVL_gm 0x03 /* Interrupt Level group mask. */ -#define ADC_CH_INTLVL_gp 0 /* Interrupt Level group position. */ -#define ADC_CH_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */ -#define ADC_CH_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */ -#define ADC_CH_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ -#define ADC_CH_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */ - -/* ADC_CH.INTFLAGS bit masks and bit positions */ -#define ADC_CH_CHIF_bm 0x01 /* Channel Interrupt Flag bit mask. */ -#define ADC_CH_CHIF_bp 0 /* Channel Interrupt Flag bit position. */ - -/* ADC_CH.SCAN bit masks and bit positions */ -#define ADC_CH_OFFSET_gm 0xF0 /* Positive MUX setting offset group mask. */ -#define ADC_CH_OFFSET_gp 4 /* Positive MUX setting offset group position. */ -#define ADC_CH_OFFSET0_bm (1<<4) /* Positive MUX setting offset bit 0 mask. */ -#define ADC_CH_OFFSET0_bp 4 /* Positive MUX setting offset bit 0 position. */ -#define ADC_CH_OFFSET1_bm (1<<5) /* Positive MUX setting offset bit 1 mask. */ -#define ADC_CH_OFFSET1_bp 5 /* Positive MUX setting offset bit 1 position. */ -#define ADC_CH_OFFSET2_bm (1<<6) /* Positive MUX setting offset bit 2 mask. */ -#define ADC_CH_OFFSET2_bp 6 /* Positive MUX setting offset bit 2 position. */ -#define ADC_CH_OFFSET3_bm (1<<7) /* Positive MUX setting offset bit 3 mask. */ -#define ADC_CH_OFFSET3_bp 7 /* Positive MUX setting offset bit 3 position. */ - -#define ADC_CH_SCANNUM_gm 0x0F /* Number of Channels included in scan group mask. */ -#define ADC_CH_SCANNUM_gp 0 /* Number of Channels included in scan group position. */ -#define ADC_CH_SCANNUM0_bm (1<<0) /* Number of Channels included in scan bit 0 mask. */ -#define ADC_CH_SCANNUM0_bp 0 /* Number of Channels included in scan bit 0 position. */ -#define ADC_CH_SCANNUM1_bm (1<<1) /* Number of Channels included in scan bit 1 mask. */ -#define ADC_CH_SCANNUM1_bp 1 /* Number of Channels included in scan bit 1 position. */ -#define ADC_CH_SCANNUM2_bm (1<<2) /* Number of Channels included in scan bit 2 mask. */ -#define ADC_CH_SCANNUM2_bp 2 /* Number of Channels included in scan bit 2 position. */ -#define ADC_CH_SCANNUM3_bm (1<<3) /* Number of Channels included in scan bit 3 mask. */ -#define ADC_CH_SCANNUM3_bp 3 /* Number of Channels included in scan bit 3 position. */ - -/* ADC.CTRLA bit masks and bit positions */ -#define ADC_DMASEL_gm 0xC0 /* DMA Selection group mask. */ -#define ADC_DMASEL_gp 6 /* DMA Selection group position. */ -#define ADC_DMASEL0_bm (1<<6) /* DMA Selection bit 0 mask. */ -#define ADC_DMASEL0_bp 6 /* DMA Selection bit 0 position. */ -#define ADC_DMASEL1_bm (1<<7) /* DMA Selection bit 1 mask. */ -#define ADC_DMASEL1_bp 7 /* DMA Selection bit 1 position. */ - -#define ADC_CH3START_bm 0x20 /* Channel 3 Start Conversion bit mask. */ -#define ADC_CH3START_bp 5 /* Channel 3 Start Conversion bit position. */ - -#define ADC_CH2START_bm 0x10 /* Channel 2 Start Conversion bit mask. */ -#define ADC_CH2START_bp 4 /* Channel 2 Start Conversion bit position. */ - -#define ADC_CH1START_bm 0x08 /* Channel 1 Start Conversion bit mask. */ -#define ADC_CH1START_bp 3 /* Channel 1 Start Conversion bit position. */ - -#define ADC_CH0START_bm 0x04 /* Channel 0 Start Conversion bit mask. */ -#define ADC_CH0START_bp 2 /* Channel 0 Start Conversion bit position. */ - -#define ADC_FLUSH_bm 0x02 /* Flush Pipeline bit mask. */ -#define ADC_FLUSH_bp 1 /* Flush Pipeline bit position. */ - -#define ADC_ENABLE_bm 0x01 /* Enable ADC bit mask. */ -#define ADC_ENABLE_bp 0 /* Enable ADC bit position. */ - -/* ADC.CTRLB bit masks and bit positions */ -#define ADC_IMPMODE_bm 0x80 /* Gain Stage Impedance Mode bit mask. */ -#define ADC_IMPMODE_bp 7 /* Gain Stage Impedance Mode bit position. */ - -#define ADC_CURRLIMIT_gm 0x60 /* Current Limitation group mask. */ -#define ADC_CURRLIMIT_gp 5 /* Current Limitation group position. */ -#define ADC_CURRLIMIT0_bm (1<<5) /* Current Limitation bit 0 mask. */ -#define ADC_CURRLIMIT0_bp 5 /* Current Limitation bit 0 position. */ -#define ADC_CURRLIMIT1_bm (1<<6) /* Current Limitation bit 1 mask. */ -#define ADC_CURRLIMIT1_bp 6 /* Current Limitation bit 1 position. */ - -#define ADC_CONMODE_bm 0x10 /* Conversion Mode bit mask. */ -#define ADC_CONMODE_bp 4 /* Conversion Mode bit position. */ - -#define ADC_FREERUN_bm 0x08 /* Free Running Mode Enable bit mask. */ -#define ADC_FREERUN_bp 3 /* Free Running Mode Enable bit position. */ - -#define ADC_RESOLUTION_gm 0x06 /* Result Resolution group mask. */ -#define ADC_RESOLUTION_gp 1 /* Result Resolution group position. */ -#define ADC_RESOLUTION0_bm (1<<1) /* Result Resolution bit 0 mask. */ -#define ADC_RESOLUTION0_bp 1 /* Result Resolution bit 0 position. */ -#define ADC_RESOLUTION1_bm (1<<2) /* Result Resolution bit 1 mask. */ -#define ADC_RESOLUTION1_bp 2 /* Result Resolution bit 1 position. */ - -/* ADC.REFCTRL bit masks and bit positions */ -#define ADC_REFSEL_gm 0x70 /* Reference Selection group mask. */ -#define ADC_REFSEL_gp 4 /* Reference Selection group position. */ -#define ADC_REFSEL0_bm (1<<4) /* Reference Selection bit 0 mask. */ -#define ADC_REFSEL0_bp 4 /* Reference Selection bit 0 position. */ -#define ADC_REFSEL1_bm (1<<5) /* Reference Selection bit 1 mask. */ -#define ADC_REFSEL1_bp 5 /* Reference Selection bit 1 position. */ -#define ADC_REFSEL2_bm (1<<6) /* Reference Selection bit 2 mask. */ -#define ADC_REFSEL2_bp 6 /* Reference Selection bit 2 position. */ - -#define ADC_BANDGAP_bm 0x02 /* Bandgap enable bit mask. */ -#define ADC_BANDGAP_bp 1 /* Bandgap enable bit position. */ - -#define ADC_TEMPREF_bm 0x01 /* Temperature Reference Enable bit mask. */ -#define ADC_TEMPREF_bp 0 /* Temperature Reference Enable bit position. */ - -/* ADC.EVCTRL bit masks and bit positions */ -#define ADC_SWEEP_gm 0xC0 /* Channel Sweep Selection group mask. */ -#define ADC_SWEEP_gp 6 /* Channel Sweep Selection group position. */ -#define ADC_SWEEP0_bm (1<<6) /* Channel Sweep Selection bit 0 mask. */ -#define ADC_SWEEP0_bp 6 /* Channel Sweep Selection bit 0 position. */ -#define ADC_SWEEP1_bm (1<<7) /* Channel Sweep Selection bit 1 mask. */ -#define ADC_SWEEP1_bp 7 /* Channel Sweep Selection bit 1 position. */ - -#define ADC_EVSEL_gm 0x38 /* Event Input Select group mask. */ -#define ADC_EVSEL_gp 3 /* Event Input Select group position. */ -#define ADC_EVSEL0_bm (1<<3) /* Event Input Select bit 0 mask. */ -#define ADC_EVSEL0_bp 3 /* Event Input Select bit 0 position. */ -#define ADC_EVSEL1_bm (1<<4) /* Event Input Select bit 1 mask. */ -#define ADC_EVSEL1_bp 4 /* Event Input Select bit 1 position. */ -#define ADC_EVSEL2_bm (1<<5) /* Event Input Select bit 2 mask. */ -#define ADC_EVSEL2_bp 5 /* Event Input Select bit 2 position. */ - -#define ADC_EVACT_gm 0x07 /* Event Action Select group mask. */ -#define ADC_EVACT_gp 0 /* Event Action Select group position. */ -#define ADC_EVACT0_bm (1<<0) /* Event Action Select bit 0 mask. */ -#define ADC_EVACT0_bp 0 /* Event Action Select bit 0 position. */ -#define ADC_EVACT1_bm (1<<1) /* Event Action Select bit 1 mask. */ -#define ADC_EVACT1_bp 1 /* Event Action Select bit 1 position. */ -#define ADC_EVACT2_bm (1<<2) /* Event Action Select bit 2 mask. */ -#define ADC_EVACT2_bp 2 /* Event Action Select bit 2 position. */ - -/* ADC.PRESCALER bit masks and bit positions */ -#define ADC_PRESCALER_gm 0x07 /* Clock Prescaler Selection group mask. */ -#define ADC_PRESCALER_gp 0 /* Clock Prescaler Selection group position. */ -#define ADC_PRESCALER0_bm (1<<0) /* Clock Prescaler Selection bit 0 mask. */ -#define ADC_PRESCALER0_bp 0 /* Clock Prescaler Selection bit 0 position. */ -#define ADC_PRESCALER1_bm (1<<1) /* Clock Prescaler Selection bit 1 mask. */ -#define ADC_PRESCALER1_bp 1 /* Clock Prescaler Selection bit 1 position. */ -#define ADC_PRESCALER2_bm (1<<2) /* Clock Prescaler Selection bit 2 mask. */ -#define ADC_PRESCALER2_bp 2 /* Clock Prescaler Selection bit 2 position. */ - -/* ADC.INTFLAGS bit masks and bit positions */ -#define ADC_CH3IF_bm 0x08 /* Channel 3 Interrupt Flag bit mask. */ -#define ADC_CH3IF_bp 3 /* Channel 3 Interrupt Flag bit position. */ - -#define ADC_CH2IF_bm 0x04 /* Channel 2 Interrupt Flag bit mask. */ -#define ADC_CH2IF_bp 2 /* Channel 2 Interrupt Flag bit position. */ - -#define ADC_CH1IF_bm 0x02 /* Channel 1 Interrupt Flag bit mask. */ -#define ADC_CH1IF_bp 1 /* Channel 1 Interrupt Flag bit position. */ - -#define ADC_CH0IF_bm 0x01 /* Channel 0 Interrupt Flag bit mask. */ -#define ADC_CH0IF_bp 0 /* Channel 0 Interrupt Flag bit position. */ - -/* DAC - Digital/Analog Converter */ -/* DAC.CTRLA bit masks and bit positions */ -#define DAC_IDOEN_bm 0x10 /* Internal Output Enable bit mask. */ -#define DAC_IDOEN_bp 4 /* Internal Output Enable bit position. */ - -#define DAC_CH1EN_bm 0x08 /* Channel 1 Output Enable bit mask. */ -#define DAC_CH1EN_bp 3 /* Channel 1 Output Enable bit position. */ - -#define DAC_CH0EN_bm 0x04 /* Channel 0 Output Enable bit mask. */ -#define DAC_CH0EN_bp 2 /* Channel 0 Output Enable bit position. */ - -#define DAC_LPMODE_bm 0x02 /* Low Power Mode bit mask. */ -#define DAC_LPMODE_bp 1 /* Low Power Mode bit position. */ - -#define DAC_ENABLE_bm 0x01 /* Enable bit mask. */ -#define DAC_ENABLE_bp 0 /* Enable bit position. */ - -/* DAC.CTRLB bit masks and bit positions */ -#define DAC_CHSEL_gm 0x60 /* Channel Select group mask. */ -#define DAC_CHSEL_gp 5 /* Channel Select group position. */ -#define DAC_CHSEL0_bm (1<<5) /* Channel Select bit 0 mask. */ -#define DAC_CHSEL0_bp 5 /* Channel Select bit 0 position. */ -#define DAC_CHSEL1_bm (1<<6) /* Channel Select bit 1 mask. */ -#define DAC_CHSEL1_bp 6 /* Channel Select bit 1 position. */ - -#define DAC_CH1TRIG_bm 0x02 /* Channel 1 Event Trig Enable bit mask. */ -#define DAC_CH1TRIG_bp 1 /* Channel 1 Event Trig Enable bit position. */ - -#define DAC_CH0TRIG_bm 0x01 /* Channel 0 Event Trig Enable bit mask. */ -#define DAC_CH0TRIG_bp 0 /* Channel 0 Event Trig Enable bit position. */ - -/* DAC.CTRLC bit masks and bit positions */ -#define DAC_REFSEL_gm 0x18 /* Reference Select group mask. */ -#define DAC_REFSEL_gp 3 /* Reference Select group position. */ -#define DAC_REFSEL0_bm (1<<3) /* Reference Select bit 0 mask. */ -#define DAC_REFSEL0_bp 3 /* Reference Select bit 0 position. */ -#define DAC_REFSEL1_bm (1<<4) /* Reference Select bit 1 mask. */ -#define DAC_REFSEL1_bp 4 /* Reference Select bit 1 position. */ - -#define DAC_LEFTADJ_bm 0x01 /* Left-adjust Result bit mask. */ -#define DAC_LEFTADJ_bp 0 /* Left-adjust Result bit position. */ - -/* DAC.EVCTRL bit masks and bit positions */ -#define DAC_EVSPLIT_bm 0x08 /* Separate Event Channel Input for Channel 1 bit mask. */ -#define DAC_EVSPLIT_bp 3 /* Separate Event Channel Input for Channel 1 bit position. */ - -#define DAC_EVSEL_gm 0x07 /* Event Input Selection group mask. */ -#define DAC_EVSEL_gp 0 /* Event Input Selection group position. */ -#define DAC_EVSEL0_bm (1<<0) /* Event Input Selection bit 0 mask. */ -#define DAC_EVSEL0_bp 0 /* Event Input Selection bit 0 position. */ -#define DAC_EVSEL1_bm (1<<1) /* Event Input Selection bit 1 mask. */ -#define DAC_EVSEL1_bp 1 /* Event Input Selection bit 1 position. */ -#define DAC_EVSEL2_bm (1<<2) /* Event Input Selection bit 2 mask. */ -#define DAC_EVSEL2_bp 2 /* Event Input Selection bit 2 position. */ - -/* DAC.STATUS bit masks and bit positions */ -#define DAC_CH1DRE_bm 0x02 /* Channel 1 Data Register Empty bit mask. */ -#define DAC_CH1DRE_bp 1 /* Channel 1 Data Register Empty bit position. */ - -#define DAC_CH0DRE_bm 0x01 /* Channel 0 Data Register Empty bit mask. */ -#define DAC_CH0DRE_bp 0 /* Channel 0 Data Register Empty bit position. */ - -/* DAC.CH0GAINCAL bit masks and bit positions */ -#define DAC_CH0GAINCAL_gm 0x7F /* Gain Calibration group mask. */ -#define DAC_CH0GAINCAL_gp 0 /* Gain Calibration group position. */ -#define DAC_CH0GAINCAL0_bm (1<<0) /* Gain Calibration bit 0 mask. */ -#define DAC_CH0GAINCAL0_bp 0 /* Gain Calibration bit 0 position. */ -#define DAC_CH0GAINCAL1_bm (1<<1) /* Gain Calibration bit 1 mask. */ -#define DAC_CH0GAINCAL1_bp 1 /* Gain Calibration bit 1 position. */ -#define DAC_CH0GAINCAL2_bm (1<<2) /* Gain Calibration bit 2 mask. */ -#define DAC_CH0GAINCAL2_bp 2 /* Gain Calibration bit 2 position. */ -#define DAC_CH0GAINCAL3_bm (1<<3) /* Gain Calibration bit 3 mask. */ -#define DAC_CH0GAINCAL3_bp 3 /* Gain Calibration bit 3 position. */ -#define DAC_CH0GAINCAL4_bm (1<<4) /* Gain Calibration bit 4 mask. */ -#define DAC_CH0GAINCAL4_bp 4 /* Gain Calibration bit 4 position. */ -#define DAC_CH0GAINCAL5_bm (1<<5) /* Gain Calibration bit 5 mask. */ -#define DAC_CH0GAINCAL5_bp 5 /* Gain Calibration bit 5 position. */ -#define DAC_CH0GAINCAL6_bm (1<<6) /* Gain Calibration bit 6 mask. */ -#define DAC_CH0GAINCAL6_bp 6 /* Gain Calibration bit 6 position. */ - -/* DAC.CH0OFFSETCAL bit masks and bit positions */ -#define DAC_CH0OFFSETCAL_gm 0x7F /* Offset Calibration group mask. */ -#define DAC_CH0OFFSETCAL_gp 0 /* Offset Calibration group position. */ -#define DAC_CH0OFFSETCAL0_bm (1<<0) /* Offset Calibration bit 0 mask. */ -#define DAC_CH0OFFSETCAL0_bp 0 /* Offset Calibration bit 0 position. */ -#define DAC_CH0OFFSETCAL1_bm (1<<1) /* Offset Calibration bit 1 mask. */ -#define DAC_CH0OFFSETCAL1_bp 1 /* Offset Calibration bit 1 position. */ -#define DAC_CH0OFFSETCAL2_bm (1<<2) /* Offset Calibration bit 2 mask. */ -#define DAC_CH0OFFSETCAL2_bp 2 /* Offset Calibration bit 2 position. */ -#define DAC_CH0OFFSETCAL3_bm (1<<3) /* Offset Calibration bit 3 mask. */ -#define DAC_CH0OFFSETCAL3_bp 3 /* Offset Calibration bit 3 position. */ -#define DAC_CH0OFFSETCAL4_bm (1<<4) /* Offset Calibration bit 4 mask. */ -#define DAC_CH0OFFSETCAL4_bp 4 /* Offset Calibration bit 4 position. */ -#define DAC_CH0OFFSETCAL5_bm (1<<5) /* Offset Calibration bit 5 mask. */ -#define DAC_CH0OFFSETCAL5_bp 5 /* Offset Calibration bit 5 position. */ -#define DAC_CH0OFFSETCAL6_bm (1<<6) /* Offset Calibration bit 6 mask. */ -#define DAC_CH0OFFSETCAL6_bp 6 /* Offset Calibration bit 6 position. */ - -/* DAC.CH1GAINCAL bit masks and bit positions */ -#define DAC_CH1GAINCAL_gm 0x7F /* Gain Calibration group mask. */ -#define DAC_CH1GAINCAL_gp 0 /* Gain Calibration group position. */ -#define DAC_CH1GAINCAL0_bm (1<<0) /* Gain Calibration bit 0 mask. */ -#define DAC_CH1GAINCAL0_bp 0 /* Gain Calibration bit 0 position. */ -#define DAC_CH1GAINCAL1_bm (1<<1) /* Gain Calibration bit 1 mask. */ -#define DAC_CH1GAINCAL1_bp 1 /* Gain Calibration bit 1 position. */ -#define DAC_CH1GAINCAL2_bm (1<<2) /* Gain Calibration bit 2 mask. */ -#define DAC_CH1GAINCAL2_bp 2 /* Gain Calibration bit 2 position. */ -#define DAC_CH1GAINCAL3_bm (1<<3) /* Gain Calibration bit 3 mask. */ -#define DAC_CH1GAINCAL3_bp 3 /* Gain Calibration bit 3 position. */ -#define DAC_CH1GAINCAL4_bm (1<<4) /* Gain Calibration bit 4 mask. */ -#define DAC_CH1GAINCAL4_bp 4 /* Gain Calibration bit 4 position. */ -#define DAC_CH1GAINCAL5_bm (1<<5) /* Gain Calibration bit 5 mask. */ -#define DAC_CH1GAINCAL5_bp 5 /* Gain Calibration bit 5 position. */ -#define DAC_CH1GAINCAL6_bm (1<<6) /* Gain Calibration bit 6 mask. */ -#define DAC_CH1GAINCAL6_bp 6 /* Gain Calibration bit 6 position. */ - -/* DAC.CH1OFFSETCAL bit masks and bit positions */ -#define DAC_CH1OFFSETCAL_gm 0x7F /* Offset Calibration group mask. */ -#define DAC_CH1OFFSETCAL_gp 0 /* Offset Calibration group position. */ -#define DAC_CH1OFFSETCAL0_bm (1<<0) /* Offset Calibration bit 0 mask. */ -#define DAC_CH1OFFSETCAL0_bp 0 /* Offset Calibration bit 0 position. */ -#define DAC_CH1OFFSETCAL1_bm (1<<1) /* Offset Calibration bit 1 mask. */ -#define DAC_CH1OFFSETCAL1_bp 1 /* Offset Calibration bit 1 position. */ -#define DAC_CH1OFFSETCAL2_bm (1<<2) /* Offset Calibration bit 2 mask. */ -#define DAC_CH1OFFSETCAL2_bp 2 /* Offset Calibration bit 2 position. */ -#define DAC_CH1OFFSETCAL3_bm (1<<3) /* Offset Calibration bit 3 mask. */ -#define DAC_CH1OFFSETCAL3_bp 3 /* Offset Calibration bit 3 position. */ -#define DAC_CH1OFFSETCAL4_bm (1<<4) /* Offset Calibration bit 4 mask. */ -#define DAC_CH1OFFSETCAL4_bp 4 /* Offset Calibration bit 4 position. */ -#define DAC_CH1OFFSETCAL5_bm (1<<5) /* Offset Calibration bit 5 mask. */ -#define DAC_CH1OFFSETCAL5_bp 5 /* Offset Calibration bit 5 position. */ -#define DAC_CH1OFFSETCAL6_bm (1<<6) /* Offset Calibration bit 6 mask. */ -#define DAC_CH1OFFSETCAL6_bp 6 /* Offset Calibration bit 6 position. */ - -/* AC - Analog Comparator */ -/* AC.AC0CTRL bit masks and bit positions */ -#define AC_INTMODE_gm 0xC0 /* Interrupt Mode group mask. */ -#define AC_INTMODE_gp 6 /* Interrupt Mode group position. */ -#define AC_INTMODE0_bm (1<<6) /* Interrupt Mode bit 0 mask. */ -#define AC_INTMODE0_bp 6 /* Interrupt Mode bit 0 position. */ -#define AC_INTMODE1_bm (1<<7) /* Interrupt Mode bit 1 mask. */ -#define AC_INTMODE1_bp 7 /* Interrupt Mode bit 1 position. */ - -#define AC_INTLVL_gm 0x30 /* Interrupt Level group mask. */ -#define AC_INTLVL_gp 4 /* Interrupt Level group position. */ -#define AC_INTLVL0_bm (1<<4) /* Interrupt Level bit 0 mask. */ -#define AC_INTLVL0_bp 4 /* Interrupt Level bit 0 position. */ -#define AC_INTLVL1_bm (1<<5) /* Interrupt Level bit 1 mask. */ -#define AC_INTLVL1_bp 5 /* Interrupt Level bit 1 position. */ - -#define AC_HSMODE_bm 0x08 /* High-speed Mode bit mask. */ -#define AC_HSMODE_bp 3 /* High-speed Mode bit position. */ - -#define AC_HYSMODE_gm 0x06 /* Hysteresis Mode group mask. */ -#define AC_HYSMODE_gp 1 /* Hysteresis Mode group position. */ -#define AC_HYSMODE0_bm (1<<1) /* Hysteresis Mode bit 0 mask. */ -#define AC_HYSMODE0_bp 1 /* Hysteresis Mode bit 0 position. */ -#define AC_HYSMODE1_bm (1<<2) /* Hysteresis Mode bit 1 mask. */ -#define AC_HYSMODE1_bp 2 /* Hysteresis Mode bit 1 position. */ - -#define AC_ENABLE_bm 0x01 /* Enable bit mask. */ -#define AC_ENABLE_bp 0 /* Enable bit position. */ - -/* AC.AC1CTRL bit masks and bit positions */ -/* AC_INTMODE Predefined. */ -/* AC_INTMODE Predefined. */ - -/* AC_INTLVL Predefined. */ -/* AC_INTLVL Predefined. */ - -/* AC_HSMODE Predefined. */ -/* AC_HSMODE Predefined. */ - -/* AC_HYSMODE Predefined. */ -/* AC_HYSMODE Predefined. */ - -/* AC_ENABLE Predefined. */ -/* AC_ENABLE Predefined. */ - -/* AC.AC0MUXCTRL bit masks and bit positions */ -#define AC_MUXPOS_gm 0x38 /* MUX Positive Input group mask. */ -#define AC_MUXPOS_gp 3 /* MUX Positive Input group position. */ -#define AC_MUXPOS0_bm (1<<3) /* MUX Positive Input bit 0 mask. */ -#define AC_MUXPOS0_bp 3 /* MUX Positive Input bit 0 position. */ -#define AC_MUXPOS1_bm (1<<4) /* MUX Positive Input bit 1 mask. */ -#define AC_MUXPOS1_bp 4 /* MUX Positive Input bit 1 position. */ -#define AC_MUXPOS2_bm (1<<5) /* MUX Positive Input bit 2 mask. */ -#define AC_MUXPOS2_bp 5 /* MUX Positive Input bit 2 position. */ - -#define AC_MUXNEG_gm 0x07 /* MUX Negative Input group mask. */ -#define AC_MUXNEG_gp 0 /* MUX Negative Input group position. */ -#define AC_MUXNEG0_bm (1<<0) /* MUX Negative Input bit 0 mask. */ -#define AC_MUXNEG0_bp 0 /* MUX Negative Input bit 0 position. */ -#define AC_MUXNEG1_bm (1<<1) /* MUX Negative Input bit 1 mask. */ -#define AC_MUXNEG1_bp 1 /* MUX Negative Input bit 1 position. */ -#define AC_MUXNEG2_bm (1<<2) /* MUX Negative Input bit 2 mask. */ -#define AC_MUXNEG2_bp 2 /* MUX Negative Input bit 2 position. */ - -/* AC.AC1MUXCTRL bit masks and bit positions */ -/* AC_MUXPOS Predefined. */ -/* AC_MUXPOS Predefined. */ - -/* AC_MUXNEG Predefined. */ -/* AC_MUXNEG Predefined. */ - -/* AC.CTRLA bit masks and bit positions */ -#define AC_AC1OUT_bm 0x02 /* Analog Comparator 1 Output Enable bit mask. */ -#define AC_AC1OUT_bp 1 /* Analog Comparator 1 Output Enable bit position. */ - -#define AC_AC0OUT_bm 0x01 /* Analog Comparator 0 Output Enable bit mask. */ -#define AC_AC0OUT_bp 0 /* Analog Comparator 0 Output Enable bit position. */ - -/* AC.CTRLB bit masks and bit positions */ -#define AC_SCALEFAC_gm 0x3F /* VCC Voltage Scaler Factor group mask. */ -#define AC_SCALEFAC_gp 0 /* VCC Voltage Scaler Factor group position. */ -#define AC_SCALEFAC0_bm (1<<0) /* VCC Voltage Scaler Factor bit 0 mask. */ -#define AC_SCALEFAC0_bp 0 /* VCC Voltage Scaler Factor bit 0 position. */ -#define AC_SCALEFAC1_bm (1<<1) /* VCC Voltage Scaler Factor bit 1 mask. */ -#define AC_SCALEFAC1_bp 1 /* VCC Voltage Scaler Factor bit 1 position. */ -#define AC_SCALEFAC2_bm (1<<2) /* VCC Voltage Scaler Factor bit 2 mask. */ -#define AC_SCALEFAC2_bp 2 /* VCC Voltage Scaler Factor bit 2 position. */ -#define AC_SCALEFAC3_bm (1<<3) /* VCC Voltage Scaler Factor bit 3 mask. */ -#define AC_SCALEFAC3_bp 3 /* VCC Voltage Scaler Factor bit 3 position. */ -#define AC_SCALEFAC4_bm (1<<4) /* VCC Voltage Scaler Factor bit 4 mask. */ -#define AC_SCALEFAC4_bp 4 /* VCC Voltage Scaler Factor bit 4 position. */ -#define AC_SCALEFAC5_bm (1<<5) /* VCC Voltage Scaler Factor bit 5 mask. */ -#define AC_SCALEFAC5_bp 5 /* VCC Voltage Scaler Factor bit 5 position. */ - -/* AC.WINCTRL bit masks and bit positions */ -#define AC_WEN_bm 0x10 /* Window Mode Enable bit mask. */ -#define AC_WEN_bp 4 /* Window Mode Enable bit position. */ - -#define AC_WINTMODE_gm 0x0C /* Window Interrupt Mode group mask. */ -#define AC_WINTMODE_gp 2 /* Window Interrupt Mode group position. */ -#define AC_WINTMODE0_bm (1<<2) /* Window Interrupt Mode bit 0 mask. */ -#define AC_WINTMODE0_bp 2 /* Window Interrupt Mode bit 0 position. */ -#define AC_WINTMODE1_bm (1<<3) /* Window Interrupt Mode bit 1 mask. */ -#define AC_WINTMODE1_bp 3 /* Window Interrupt Mode bit 1 position. */ - -#define AC_WINTLVL_gm 0x03 /* Window Interrupt Level group mask. */ -#define AC_WINTLVL_gp 0 /* Window Interrupt Level group position. */ -#define AC_WINTLVL0_bm (1<<0) /* Window Interrupt Level bit 0 mask. */ -#define AC_WINTLVL0_bp 0 /* Window Interrupt Level bit 0 position. */ -#define AC_WINTLVL1_bm (1<<1) /* Window Interrupt Level bit 1 mask. */ -#define AC_WINTLVL1_bp 1 /* Window Interrupt Level bit 1 position. */ - -/* AC.STATUS bit masks and bit positions */ -#define AC_WSTATE_gm 0xC0 /* Window Mode State group mask. */ -#define AC_WSTATE_gp 6 /* Window Mode State group position. */ -#define AC_WSTATE0_bm (1<<6) /* Window Mode State bit 0 mask. */ -#define AC_WSTATE0_bp 6 /* Window Mode State bit 0 position. */ -#define AC_WSTATE1_bm (1<<7) /* Window Mode State bit 1 mask. */ -#define AC_WSTATE1_bp 7 /* Window Mode State bit 1 position. */ - -#define AC_AC1STATE_bm 0x20 /* Analog Comparator 1 State bit mask. */ -#define AC_AC1STATE_bp 5 /* Analog Comparator 1 State bit position. */ - -#define AC_AC0STATE_bm 0x10 /* Analog Comparator 0 State bit mask. */ -#define AC_AC0STATE_bp 4 /* Analog Comparator 0 State bit position. */ - -#define AC_WIF_bm 0x04 /* Window Mode Interrupt Flag bit mask. */ -#define AC_WIF_bp 2 /* Window Mode Interrupt Flag bit position. */ - -#define AC_AC1IF_bm 0x02 /* Analog Comparator 1 Interrupt Flag bit mask. */ -#define AC_AC1IF_bp 1 /* Analog Comparator 1 Interrupt Flag bit position. */ - -#define AC_AC0IF_bm 0x01 /* Analog Comparator 0 Interrupt Flag bit mask. */ -#define AC_AC0IF_bp 0 /* Analog Comparator 0 Interrupt Flag bit position. */ - -/* RTC - Real-Time Counter */ -/* RTC.CTRL bit masks and bit positions */ -#define RTC_PRESCALER_gm 0x07 /* Prescaling Factor group mask. */ -#define RTC_PRESCALER_gp 0 /* Prescaling Factor group position. */ -#define RTC_PRESCALER0_bm (1<<0) /* Prescaling Factor bit 0 mask. */ -#define RTC_PRESCALER0_bp 0 /* Prescaling Factor bit 0 position. */ -#define RTC_PRESCALER1_bm (1<<1) /* Prescaling Factor bit 1 mask. */ -#define RTC_PRESCALER1_bp 1 /* Prescaling Factor bit 1 position. */ -#define RTC_PRESCALER2_bm (1<<2) /* Prescaling Factor bit 2 mask. */ -#define RTC_PRESCALER2_bp 2 /* Prescaling Factor bit 2 position. */ - -/* RTC.STATUS bit masks and bit positions */ -#define RTC_SYNCBUSY_bm 0x01 /* Synchronization Busy Flag bit mask. */ -#define RTC_SYNCBUSY_bp 0 /* Synchronization Busy Flag bit position. */ - -/* RTC.INTCTRL bit masks and bit positions */ -#define RTC_COMPINTLVL_gm 0x0C /* Compare Match Interrupt Level group mask. */ -#define RTC_COMPINTLVL_gp 2 /* Compare Match Interrupt Level group position. */ -#define RTC_COMPINTLVL0_bm (1<<2) /* Compare Match Interrupt Level bit 0 mask. */ -#define RTC_COMPINTLVL0_bp 2 /* Compare Match Interrupt Level bit 0 position. */ -#define RTC_COMPINTLVL1_bm (1<<3) /* Compare Match Interrupt Level bit 1 mask. */ -#define RTC_COMPINTLVL1_bp 3 /* Compare Match Interrupt Level bit 1 position. */ - -#define RTC_OVFINTLVL_gm 0x03 /* Overflow Interrupt Level group mask. */ -#define RTC_OVFINTLVL_gp 0 /* Overflow Interrupt Level group position. */ -#define RTC_OVFINTLVL0_bm (1<<0) /* Overflow Interrupt Level bit 0 mask. */ -#define RTC_OVFINTLVL0_bp 0 /* Overflow Interrupt Level bit 0 position. */ -#define RTC_OVFINTLVL1_bm (1<<1) /* Overflow Interrupt Level bit 1 mask. */ -#define RTC_OVFINTLVL1_bp 1 /* Overflow Interrupt Level bit 1 position. */ - -/* RTC.INTFLAGS bit masks and bit positions */ -#define RTC_COMPIF_bm 0x02 /* Compare Match Interrupt Flag bit mask. */ -#define RTC_COMPIF_bp 1 /* Compare Match Interrupt Flag bit position. */ - -#define RTC_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ -#define RTC_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ - -/* TWI - Two-Wire Interface */ -/* TWI_MASTER.CTRLA bit masks and bit positions */ -#define TWI_MASTER_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ -#define TWI_MASTER_INTLVL_gp 6 /* Interrupt Level group position. */ -#define TWI_MASTER_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ -#define TWI_MASTER_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ -#define TWI_MASTER_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ -#define TWI_MASTER_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ - -#define TWI_MASTER_RIEN_bm 0x20 /* Read Interrupt Enable bit mask. */ -#define TWI_MASTER_RIEN_bp 5 /* Read Interrupt Enable bit position. */ - -#define TWI_MASTER_WIEN_bm 0x10 /* Write Interrupt Enable bit mask. */ -#define TWI_MASTER_WIEN_bp 4 /* Write Interrupt Enable bit position. */ - -#define TWI_MASTER_ENABLE_bm 0x08 /* Enable TWI Master bit mask. */ -#define TWI_MASTER_ENABLE_bp 3 /* Enable TWI Master bit position. */ - -/* TWI_MASTER.CTRLB bit masks and bit positions */ -#define TWI_MASTER_TIMEOUT_gm 0x0C /* Inactive Bus Timeout group mask. */ -#define TWI_MASTER_TIMEOUT_gp 2 /* Inactive Bus Timeout group position. */ -#define TWI_MASTER_TIMEOUT0_bm (1<<2) /* Inactive Bus Timeout bit 0 mask. */ -#define TWI_MASTER_TIMEOUT0_bp 2 /* Inactive Bus Timeout bit 0 position. */ -#define TWI_MASTER_TIMEOUT1_bm (1<<3) /* Inactive Bus Timeout bit 1 mask. */ -#define TWI_MASTER_TIMEOUT1_bp 3 /* Inactive Bus Timeout bit 1 position. */ - -#define TWI_MASTER_QCEN_bm 0x02 /* Quick Command Enable bit mask. */ -#define TWI_MASTER_QCEN_bp 1 /* Quick Command Enable bit position. */ - -#define TWI_MASTER_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ -#define TWI_MASTER_SMEN_bp 0 /* Smart Mode Enable bit position. */ - -/* TWI_MASTER.CTRLC bit masks and bit positions */ -#define TWI_MASTER_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ -#define TWI_MASTER_ACKACT_bp 2 /* Acknowledge Action bit position. */ - -#define TWI_MASTER_CMD_gm 0x03 /* Command group mask. */ -#define TWI_MASTER_CMD_gp 0 /* Command group position. */ -#define TWI_MASTER_CMD0_bm (1<<0) /* Command bit 0 mask. */ -#define TWI_MASTER_CMD0_bp 0 /* Command bit 0 position. */ -#define TWI_MASTER_CMD1_bm (1<<1) /* Command bit 1 mask. */ -#define TWI_MASTER_CMD1_bp 1 /* Command bit 1 position. */ - -/* TWI_MASTER.STATUS bit masks and bit positions */ -#define TWI_MASTER_RIF_bm 0x80 /* Read Interrupt Flag bit mask. */ -#define TWI_MASTER_RIF_bp 7 /* Read Interrupt Flag bit position. */ - -#define TWI_MASTER_WIF_bm 0x40 /* Write Interrupt Flag bit mask. */ -#define TWI_MASTER_WIF_bp 6 /* Write Interrupt Flag bit position. */ - -#define TWI_MASTER_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ -#define TWI_MASTER_CLKHOLD_bp 5 /* Clock Hold bit position. */ - -#define TWI_MASTER_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ -#define TWI_MASTER_RXACK_bp 4 /* Received Acknowledge bit position. */ - -#define TWI_MASTER_ARBLOST_bm 0x08 /* Arbitration Lost bit mask. */ -#define TWI_MASTER_ARBLOST_bp 3 /* Arbitration Lost bit position. */ - -#define TWI_MASTER_BUSERR_bm 0x04 /* Bus Error bit mask. */ -#define TWI_MASTER_BUSERR_bp 2 /* Bus Error bit position. */ - -#define TWI_MASTER_BUSSTATE_gm 0x03 /* Bus State group mask. */ -#define TWI_MASTER_BUSSTATE_gp 0 /* Bus State group position. */ -#define TWI_MASTER_BUSSTATE0_bm (1<<0) /* Bus State bit 0 mask. */ -#define TWI_MASTER_BUSSTATE0_bp 0 /* Bus State bit 0 position. */ -#define TWI_MASTER_BUSSTATE1_bm (1<<1) /* Bus State bit 1 mask. */ -#define TWI_MASTER_BUSSTATE1_bp 1 /* Bus State bit 1 position. */ - -/* TWI_SLAVE.CTRLA bit masks and bit positions */ -#define TWI_SLAVE_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ -#define TWI_SLAVE_INTLVL_gp 6 /* Interrupt Level group position. */ -#define TWI_SLAVE_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ -#define TWI_SLAVE_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ -#define TWI_SLAVE_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ -#define TWI_SLAVE_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ - -#define TWI_SLAVE_DIEN_bm 0x20 /* Data Interrupt Enable bit mask. */ -#define TWI_SLAVE_DIEN_bp 5 /* Data Interrupt Enable bit position. */ - -#define TWI_SLAVE_APIEN_bm 0x10 /* Address/Stop Interrupt Enable bit mask. */ -#define TWI_SLAVE_APIEN_bp 4 /* Address/Stop Interrupt Enable bit position. */ - -#define TWI_SLAVE_ENABLE_bm 0x08 /* Enable TWI Slave bit mask. */ -#define TWI_SLAVE_ENABLE_bp 3 /* Enable TWI Slave bit position. */ - -#define TWI_SLAVE_PIEN_bm 0x04 /* Stop Interrupt Enable bit mask. */ -#define TWI_SLAVE_PIEN_bp 2 /* Stop Interrupt Enable bit position. */ - -#define TWI_SLAVE_PMEN_bm 0x02 /* Promiscuous Mode Enable bit mask. */ -#define TWI_SLAVE_PMEN_bp 1 /* Promiscuous Mode Enable bit position. */ - -#define TWI_SLAVE_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ -#define TWI_SLAVE_SMEN_bp 0 /* Smart Mode Enable bit position. */ - -/* TWI_SLAVE.CTRLB bit masks and bit positions */ -#define TWI_SLAVE_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ -#define TWI_SLAVE_ACKACT_bp 2 /* Acknowledge Action bit position. */ - -#define TWI_SLAVE_CMD_gm 0x03 /* Command group mask. */ -#define TWI_SLAVE_CMD_gp 0 /* Command group position. */ -#define TWI_SLAVE_CMD0_bm (1<<0) /* Command bit 0 mask. */ -#define TWI_SLAVE_CMD0_bp 0 /* Command bit 0 position. */ -#define TWI_SLAVE_CMD1_bm (1<<1) /* Command bit 1 mask. */ -#define TWI_SLAVE_CMD1_bp 1 /* Command bit 1 position. */ - -/* TWI_SLAVE.STATUS bit masks and bit positions */ -#define TWI_SLAVE_DIF_bm 0x80 /* Data Interrupt Flag bit mask. */ -#define TWI_SLAVE_DIF_bp 7 /* Data Interrupt Flag bit position. */ - -#define TWI_SLAVE_APIF_bm 0x40 /* Address/Stop Interrupt Flag bit mask. */ -#define TWI_SLAVE_APIF_bp 6 /* Address/Stop Interrupt Flag bit position. */ - -#define TWI_SLAVE_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ -#define TWI_SLAVE_CLKHOLD_bp 5 /* Clock Hold bit position. */ - -#define TWI_SLAVE_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ -#define TWI_SLAVE_RXACK_bp 4 /* Received Acknowledge bit position. */ - -#define TWI_SLAVE_COLL_bm 0x08 /* Collision bit mask. */ -#define TWI_SLAVE_COLL_bp 3 /* Collision bit position. */ - -#define TWI_SLAVE_BUSERR_bm 0x04 /* Bus Error bit mask. */ -#define TWI_SLAVE_BUSERR_bp 2 /* Bus Error bit position. */ - -#define TWI_SLAVE_DIR_bm 0x02 /* Read/Write Direction bit mask. */ -#define TWI_SLAVE_DIR_bp 1 /* Read/Write Direction bit position. */ - -#define TWI_SLAVE_AP_bm 0x01 /* Slave Address or Stop bit mask. */ -#define TWI_SLAVE_AP_bp 0 /* Slave Address or Stop bit position. */ - -/* TWI_SLAVE.ADDRMASK bit masks and bit positions */ -#define TWI_SLAVE_ADDRMASK_gm 0xFE /* Address Mask group mask. */ -#define TWI_SLAVE_ADDRMASK_gp 1 /* Address Mask group position. */ -#define TWI_SLAVE_ADDRMASK0_bm (1<<1) /* Address Mask bit 0 mask. */ -#define TWI_SLAVE_ADDRMASK0_bp 1 /* Address Mask bit 0 position. */ -#define TWI_SLAVE_ADDRMASK1_bm (1<<2) /* Address Mask bit 1 mask. */ -#define TWI_SLAVE_ADDRMASK1_bp 2 /* Address Mask bit 1 position. */ -#define TWI_SLAVE_ADDRMASK2_bm (1<<3) /* Address Mask bit 2 mask. */ -#define TWI_SLAVE_ADDRMASK2_bp 3 /* Address Mask bit 2 position. */ -#define TWI_SLAVE_ADDRMASK3_bm (1<<4) /* Address Mask bit 3 mask. */ -#define TWI_SLAVE_ADDRMASK3_bp 4 /* Address Mask bit 3 position. */ -#define TWI_SLAVE_ADDRMASK4_bm (1<<5) /* Address Mask bit 4 mask. */ -#define TWI_SLAVE_ADDRMASK4_bp 5 /* Address Mask bit 4 position. */ -#define TWI_SLAVE_ADDRMASK5_bm (1<<6) /* Address Mask bit 5 mask. */ -#define TWI_SLAVE_ADDRMASK5_bp 6 /* Address Mask bit 5 position. */ -#define TWI_SLAVE_ADDRMASK6_bm (1<<7) /* Address Mask bit 6 mask. */ -#define TWI_SLAVE_ADDRMASK6_bp 7 /* Address Mask bit 6 position. */ - -#define TWI_SLAVE_ADDREN_bm 0x01 /* Address Enable bit mask. */ -#define TWI_SLAVE_ADDREN_bp 0 /* Address Enable bit position. */ - -/* TWI.CTRL bit masks and bit positions */ -#define TWI_SDAHOLD_gm 0x06 /* SDA Hold Time Enable group mask. */ -#define TWI_SDAHOLD_gp 1 /* SDA Hold Time Enable group position. */ -#define TWI_SDAHOLD0_bm (1<<1) /* SDA Hold Time Enable bit 0 mask. */ -#define TWI_SDAHOLD0_bp 1 /* SDA Hold Time Enable bit 0 position. */ -#define TWI_SDAHOLD1_bm (1<<2) /* SDA Hold Time Enable bit 1 mask. */ -#define TWI_SDAHOLD1_bp 2 /* SDA Hold Time Enable bit 1 position. */ - -#define TWI_EDIEN_bm 0x01 /* External Driver Interface Enable bit mask. */ -#define TWI_EDIEN_bp 0 /* External Driver Interface Enable bit position. */ - -/* USB - USB */ -/* USB_EP.STATUS bit masks and bit positions */ -#define USB_EP_STALLF_bm 0x80 /* Endpoint Stall Flag bit mask. */ -#define USB_EP_STALLF_bp 7 /* Endpoint Stall Flag bit position. */ - -#define USB_EP_CRC_bm 0x80 /* CRC Error Flag bit mask. */ -#define USB_EP_CRC_bp 7 /* CRC Error Flag bit position. */ - -#define USB_EP_UNF_bm 0x40 /* Underflow Enpoint FLag bit mask. */ -#define USB_EP_UNF_bp 6 /* Underflow Enpoint FLag bit position. */ - -#define USB_EP_OVF_bm 0x40 /* Overflow Enpoint Flag for Output Endpoints bit mask. */ -#define USB_EP_OVF_bp 6 /* Overflow Enpoint Flag for Output Endpoints bit position. */ - -#define USB_EP_TRNCOMPL0_bm 0x20 /* Transaction Complete 0 Flag bit mask. */ -#define USB_EP_TRNCOMPL0_bp 5 /* Transaction Complete 0 Flag bit position. */ - -#define USB_EP_TRNCOMPL1_bm 0x10 /* Transaction Complete 1 Flag bit mask. */ -#define USB_EP_TRNCOMPL1_bp 4 /* Transaction Complete 1 Flag bit position. */ - -#define USB_EP_SETUP_bm 0x10 /* SETUP Transaction Complete Flag bit mask. */ -#define USB_EP_SETUP_bp 4 /* SETUP Transaction Complete Flag bit position. */ - -#define USB_EP_BANK_bm 0x08 /* Bank Select bit mask. */ -#define USB_EP_BANK_bp 3 /* Bank Select bit position. */ - -#define USB_EP_BUSNACK1_bm 0x04 /* Data Buffer 1 Not Acknowledge bit mask. */ -#define USB_EP_BUSNACK1_bp 2 /* Data Buffer 1 Not Acknowledge bit position. */ - -#define USB_EP_BUSNACK0_bm 0x02 /* Data Buffer 0 Not Acknowledge bit mask. */ -#define USB_EP_BUSNACK0_bp 1 /* Data Buffer 0 Not Acknowledge bit position. */ - -#define USB_EP_TOGGLE_bm 0x01 /* Data Toggle bit mask. */ -#define USB_EP_TOGGLE_bp 0 /* Data Toggle bit position. */ - -/* USB_EP.CTRL bit masks and bit positions */ -#define USB_EP_TYPE_gm 0xC0 /* Endpoint Type group mask. */ -#define USB_EP_TYPE_gp 6 /* Endpoint Type group position. */ -#define USB_EP_TYPE0_bm (1<<6) /* Endpoint Type bit 0 mask. */ -#define USB_EP_TYPE0_bp 6 /* Endpoint Type bit 0 position. */ -#define USB_EP_TYPE1_bm (1<<7) /* Endpoint Type bit 1 mask. */ -#define USB_EP_TYPE1_bp 7 /* Endpoint Type bit 1 position. */ - -#define USB_EP_MULTIPKT_bm 0x20 /* Multi Packet Transfer Enable bit mask. */ -#define USB_EP_MULTIPKT_bp 5 /* Multi Packet Transfer Enable bit position. */ - -#define USB_EP_PINGPONG_bm 0x10 /* Ping-Pong Enable bit mask. */ -#define USB_EP_PINGPONG_bp 4 /* Ping-Pong Enable bit position. */ - -#define USB_EP_INTDSBL_bm 0x08 /* Interrupt Disable bit mask. */ -#define USB_EP_INTDSBL_bp 3 /* Interrupt Disable bit position. */ - -#define USB_EP_STALL_bm 0x04 /* Data Stall bit mask. */ -#define USB_EP_STALL_bp 2 /* Data Stall bit position. */ - -#define USB_EP_BUFSIZE_gm 0x07 /* Data Buffer Size group mask. */ -#define USB_EP_BUFSIZE_gp 0 /* Data Buffer Size group position. */ -#define USB_EP_BUFSIZE0_bm (1<<0) /* Data Buffer Size bit 0 mask. */ -#define USB_EP_BUFSIZE0_bp 0 /* Data Buffer Size bit 0 position. */ -#define USB_EP_BUFSIZE1_bm (1<<1) /* Data Buffer Size bit 1 mask. */ -#define USB_EP_BUFSIZE1_bp 1 /* Data Buffer Size bit 1 position. */ -#define USB_EP_BUFSIZE2_bm (1<<2) /* Data Buffer Size bit 2 mask. */ -#define USB_EP_BUFSIZE2_bp 2 /* Data Buffer Size bit 2 position. */ - -/* USB_EP.CNT bit masks and bit positions */ -#define USB_EP_ZLP_bm 0x8000 /* Zero Length Packet bit mask. */ -#define USB_EP_ZLP_bp 15 /* Zero Length Packet bit position. */ - -/* USB.CTRLA bit masks and bit positions */ -#define USB_ENABLE_bm 0x80 /* USB Enable bit mask. */ -#define USB_ENABLE_bp 7 /* USB Enable bit position. */ - -#define USB_SPEED_bm 0x40 /* Speed Select bit mask. */ -#define USB_SPEED_bp 6 /* Speed Select bit position. */ - -#define USB_FIFOEN_bm 0x20 /* USB FIFO Enable bit mask. */ -#define USB_FIFOEN_bp 5 /* USB FIFO Enable bit position. */ - -#define USB_STFRNUM_bm 0x10 /* Store Frame Number Enable bit mask. */ -#define USB_STFRNUM_bp 4 /* Store Frame Number Enable bit position. */ - -#define USB_MAXEP_gm 0x0F /* Maximum Endpoint Addresses group mask. */ -#define USB_MAXEP_gp 0 /* Maximum Endpoint Addresses group position. */ -#define USB_MAXEP0_bm (1<<0) /* Maximum Endpoint Addresses bit 0 mask. */ -#define USB_MAXEP0_bp 0 /* Maximum Endpoint Addresses bit 0 position. */ -#define USB_MAXEP1_bm (1<<1) /* Maximum Endpoint Addresses bit 1 mask. */ -#define USB_MAXEP1_bp 1 /* Maximum Endpoint Addresses bit 1 position. */ -#define USB_MAXEP2_bm (1<<2) /* Maximum Endpoint Addresses bit 2 mask. */ -#define USB_MAXEP2_bp 2 /* Maximum Endpoint Addresses bit 2 position. */ -#define USB_MAXEP3_bm (1<<3) /* Maximum Endpoint Addresses bit 3 mask. */ -#define USB_MAXEP3_bp 3 /* Maximum Endpoint Addresses bit 3 position. */ - -/* USB.CTRLB bit masks and bit positions */ -#define USB_PULLRST_bm 0x10 /* Pull during Reset bit mask. */ -#define USB_PULLRST_bp 4 /* Pull during Reset bit position. */ - -#define USB_RWAKEUP_bm 0x04 /* Remote Wake-up bit mask. */ -#define USB_RWAKEUP_bp 2 /* Remote Wake-up bit position. */ - -#define USB_GNACK_bm 0x02 /* Global NACK bit mask. */ -#define USB_GNACK_bp 1 /* Global NACK bit position. */ - -#define USB_ATTACH_bm 0x01 /* Attach bit mask. */ -#define USB_ATTACH_bp 0 /* Attach bit position. */ - -/* USB.STATUS bit masks and bit positions */ -#define USB_URESUME_bm 0x08 /* Upstream Resume bit mask. */ -#define USB_URESUME_bp 3 /* Upstream Resume bit position. */ - -#define USB_RESUME_bm 0x04 /* Resume bit mask. */ -#define USB_RESUME_bp 2 /* Resume bit position. */ - -#define USB_SUSPEND_bm 0x02 /* Bus Suspended bit mask. */ -#define USB_SUSPEND_bp 1 /* Bus Suspended bit position. */ - -#define USB_BUSRST_bm 0x01 /* Bus Reset bit mask. */ -#define USB_BUSRST_bp 0 /* Bus Reset bit position. */ - -/* USB.ADDR bit masks and bit positions */ -#define USB_ADDR_gm 0x7F /* Device Address group mask. */ -#define USB_ADDR_gp 0 /* Device Address group position. */ -#define USB_ADDR0_bm (1<<0) /* Device Address bit 0 mask. */ -#define USB_ADDR0_bp 0 /* Device Address bit 0 position. */ -#define USB_ADDR1_bm (1<<1) /* Device Address bit 1 mask. */ -#define USB_ADDR1_bp 1 /* Device Address bit 1 position. */ -#define USB_ADDR2_bm (1<<2) /* Device Address bit 2 mask. */ -#define USB_ADDR2_bp 2 /* Device Address bit 2 position. */ -#define USB_ADDR3_bm (1<<3) /* Device Address bit 3 mask. */ -#define USB_ADDR3_bp 3 /* Device Address bit 3 position. */ -#define USB_ADDR4_bm (1<<4) /* Device Address bit 4 mask. */ -#define USB_ADDR4_bp 4 /* Device Address bit 4 position. */ -#define USB_ADDR5_bm (1<<5) /* Device Address bit 5 mask. */ -#define USB_ADDR5_bp 5 /* Device Address bit 5 position. */ -#define USB_ADDR6_bm (1<<6) /* Device Address bit 6 mask. */ -#define USB_ADDR6_bp 6 /* Device Address bit 6 position. */ - -/* USB.FIFOWP bit masks and bit positions */ -#define USB_FIFOWP_gm 0x1F /* FIFO Write Pointer group mask. */ -#define USB_FIFOWP_gp 0 /* FIFO Write Pointer group position. */ -#define USB_FIFOWP0_bm (1<<0) /* FIFO Write Pointer bit 0 mask. */ -#define USB_FIFOWP0_bp 0 /* FIFO Write Pointer bit 0 position. */ -#define USB_FIFOWP1_bm (1<<1) /* FIFO Write Pointer bit 1 mask. */ -#define USB_FIFOWP1_bp 1 /* FIFO Write Pointer bit 1 position. */ -#define USB_FIFOWP2_bm (1<<2) /* FIFO Write Pointer bit 2 mask. */ -#define USB_FIFOWP2_bp 2 /* FIFO Write Pointer bit 2 position. */ -#define USB_FIFOWP3_bm (1<<3) /* FIFO Write Pointer bit 3 mask. */ -#define USB_FIFOWP3_bp 3 /* FIFO Write Pointer bit 3 position. */ -#define USB_FIFOWP4_bm (1<<4) /* FIFO Write Pointer bit 4 mask. */ -#define USB_FIFOWP4_bp 4 /* FIFO Write Pointer bit 4 position. */ - -/* USB.FIFORP bit masks and bit positions */ -#define USB_FIFORP_gm 0x1F /* FIFO Read Pointer group mask. */ -#define USB_FIFORP_gp 0 /* FIFO Read Pointer group position. */ -#define USB_FIFORP0_bm (1<<0) /* FIFO Read Pointer bit 0 mask. */ -#define USB_FIFORP0_bp 0 /* FIFO Read Pointer bit 0 position. */ -#define USB_FIFORP1_bm (1<<1) /* FIFO Read Pointer bit 1 mask. */ -#define USB_FIFORP1_bp 1 /* FIFO Read Pointer bit 1 position. */ -#define USB_FIFORP2_bm (1<<2) /* FIFO Read Pointer bit 2 mask. */ -#define USB_FIFORP2_bp 2 /* FIFO Read Pointer bit 2 position. */ -#define USB_FIFORP3_bm (1<<3) /* FIFO Read Pointer bit 3 mask. */ -#define USB_FIFORP3_bp 3 /* FIFO Read Pointer bit 3 position. */ -#define USB_FIFORP4_bm (1<<4) /* FIFO Read Pointer bit 4 mask. */ -#define USB_FIFORP4_bp 4 /* FIFO Read Pointer bit 4 position. */ - -/* USB.INTCTRLA bit masks and bit positions */ -#define USB_SOFIE_bm 0x80 /* Start Of Frame Interrupt Enable bit mask. */ -#define USB_SOFIE_bp 7 /* Start Of Frame Interrupt Enable bit position. */ - -#define USB_BUSEVIE_bm 0x40 /* Bus Event Interrupt Enable bit mask. */ -#define USB_BUSEVIE_bp 6 /* Bus Event Interrupt Enable bit position. */ - -#define USB_BUSERRIE_bm 0x20 /* Bus Error Interrupt Enable bit mask. */ -#define USB_BUSERRIE_bp 5 /* Bus Error Interrupt Enable bit position. */ - -#define USB_STALLIE_bm 0x10 /* STALL Interrupt Enable bit mask. */ -#define USB_STALLIE_bp 4 /* STALL Interrupt Enable bit position. */ - -#define USB_INTLVL_gm 0x03 /* Interrupt Level group mask. */ -#define USB_INTLVL_gp 0 /* Interrupt Level group position. */ -#define USB_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */ -#define USB_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */ -#define USB_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ -#define USB_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */ - -/* USB.INTCTRLB bit masks and bit positions */ -#define USB_TRNIE_bm 0x02 /* Transaction Complete Interrupt Enable bit mask. */ -#define USB_TRNIE_bp 1 /* Transaction Complete Interrupt Enable bit position. */ - -#define USB_SETUPIE_bm 0x01 /* SETUP Transaction Complete Interrupt Enable bit mask. */ -#define USB_SETUPIE_bp 0 /* SETUP Transaction Complete Interrupt Enable bit position. */ - -/* USB.INTFLAGSACLR bit masks and bit positions */ -#define USB_SOFIF_bm 0x80 /* Start Of Frame Interrupt Flag bit mask. */ -#define USB_SOFIF_bp 7 /* Start Of Frame Interrupt Flag bit position. */ - -#define USB_SUSPENDIF_bm 0x40 /* Suspend Interrupt Flag bit mask. */ -#define USB_SUSPENDIF_bp 6 /* Suspend Interrupt Flag bit position. */ - -#define USB_RESUMEIF_bm 0x20 /* Resume Interrupt Flag bit mask. */ -#define USB_RESUMEIF_bp 5 /* Resume Interrupt Flag bit position. */ - -#define USB_RSTIF_bm 0x10 /* Reset Interrupt Flag bit mask. */ -#define USB_RSTIF_bp 4 /* Reset Interrupt Flag bit position. */ - -#define USB_CRCIF_bm 0x08 /* Isochronous CRC Error Interrupt Flag bit mask. */ -#define USB_CRCIF_bp 3 /* Isochronous CRC Error Interrupt Flag bit position. */ - -#define USB_UNFIF_bm 0x04 /* Underflow Interrupt Flag bit mask. */ -#define USB_UNFIF_bp 2 /* Underflow Interrupt Flag bit position. */ - -#define USB_OVFIF_bm 0x02 /* Overflow Interrupt Flag bit mask. */ -#define USB_OVFIF_bp 1 /* Overflow Interrupt Flag bit position. */ - -#define USB_STALLIF_bm 0x01 /* STALL Interrupt Flag bit mask. */ -#define USB_STALLIF_bp 0 /* STALL Interrupt Flag bit position. */ - -/* USB.INTFLAGSASET bit masks and bit positions */ -/* USB_SOFIF Predefined. */ -/* USB_SOFIF Predefined. */ - -/* USB_SUSPENDIF Predefined. */ -/* USB_SUSPENDIF Predefined. */ - -/* USB_RESUMEIF Predefined. */ -/* USB_RESUMEIF Predefined. */ - -/* USB_RSTIF Predefined. */ -/* USB_RSTIF Predefined. */ - -/* USB_CRCIF Predefined. */ -/* USB_CRCIF Predefined. */ - -/* USB_UNFIF Predefined. */ -/* USB_UNFIF Predefined. */ - -/* USB_OVFIF Predefined. */ -/* USB_OVFIF Predefined. */ - -/* USB_STALLIF Predefined. */ -/* USB_STALLIF Predefined. */ - -/* USB.INTFLAGSBCLR bit masks and bit positions */ -#define USB_TRNIF_bm 0x02 /* Transaction Complete Interrupt Flag bit mask. */ -#define USB_TRNIF_bp 1 /* Transaction Complete Interrupt Flag bit position. */ - -#define USB_SETUPIF_bm 0x01 /* SETUP Transaction Complete Interrupt Flag bit mask. */ -#define USB_SETUPIF_bp 0 /* SETUP Transaction Complete Interrupt Flag bit position. */ - -/* USB.INTFLAGSBSET bit masks and bit positions */ -/* USB_TRNIF Predefined. */ -/* USB_TRNIF Predefined. */ - -/* USB_SETUPIF Predefined. */ -/* USB_SETUPIF Predefined. */ - -/* PORT - I/O Port Configuration */ -/* PORT.INTCTRL bit masks and bit positions */ -#define PORT_INT1LVL_gm 0x0C /* Port Interrupt 1 Level group mask. */ -#define PORT_INT1LVL_gp 2 /* Port Interrupt 1 Level group position. */ -#define PORT_INT1LVL0_bm (1<<2) /* Port Interrupt 1 Level bit 0 mask. */ -#define PORT_INT1LVL0_bp 2 /* Port Interrupt 1 Level bit 0 position. */ -#define PORT_INT1LVL1_bm (1<<3) /* Port Interrupt 1 Level bit 1 mask. */ -#define PORT_INT1LVL1_bp 3 /* Port Interrupt 1 Level bit 1 position. */ - -#define PORT_INT0LVL_gm 0x03 /* Port Interrupt 0 Level group mask. */ -#define PORT_INT0LVL_gp 0 /* Port Interrupt 0 Level group position. */ -#define PORT_INT0LVL0_bm (1<<0) /* Port Interrupt 0 Level bit 0 mask. */ -#define PORT_INT0LVL0_bp 0 /* Port Interrupt 0 Level bit 0 position. */ -#define PORT_INT0LVL1_bm (1<<1) /* Port Interrupt 0 Level bit 1 mask. */ -#define PORT_INT0LVL1_bp 1 /* Port Interrupt 0 Level bit 1 position. */ - -/* PORT.INTFLAGS bit masks and bit positions */ -#define PORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ -#define PORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ - -#define PORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ -#define PORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ - -/* PORT.REMAP bit masks and bit positions */ -#define PORT_SPI_bm 0x20 /* SPI bit mask. */ -#define PORT_SPI_bp 5 /* SPI bit position. */ - -#define PORT_USART0_bm 0x10 /* USART0 bit mask. */ -#define PORT_USART0_bp 4 /* USART0 bit position. */ - -#define PORT_TC0D_bm 0x08 /* Timer/Counter 0 Output Compare D bit mask. */ -#define PORT_TC0D_bp 3 /* Timer/Counter 0 Output Compare D bit position. */ - -#define PORT_TC0C_bm 0x04 /* Timer/Counter 0 Output Compare C bit mask. */ -#define PORT_TC0C_bp 2 /* Timer/Counter 0 Output Compare C bit position. */ - -#define PORT_TC0B_bm 0x02 /* Timer/Counter 0 Output Compare B bit mask. */ -#define PORT_TC0B_bp 1 /* Timer/Counter 0 Output Compare B bit position. */ - -#define PORT_TC0A_bm 0x01 /* Timer/Counter 0 Output Compare A bit mask. */ -#define PORT_TC0A_bp 0 /* Timer/Counter 0 Output Compare A bit position. */ - -/* PORT.PIN0CTRL bit masks and bit positions */ -#define PORT_SRLEN_bm 0x80 /* Slew Rate Enable bit mask. */ -#define PORT_SRLEN_bp 7 /* Slew Rate Enable bit position. */ - -#define PORT_INVEN_bm 0x40 /* Inverted I/O Enable bit mask. */ -#define PORT_INVEN_bp 6 /* Inverted I/O Enable bit position. */ - -#define PORT_OPC_gm 0x38 /* Output/Pull Configuration group mask. */ -#define PORT_OPC_gp 3 /* Output/Pull Configuration group position. */ -#define PORT_OPC0_bm (1<<3) /* Output/Pull Configuration bit 0 mask. */ -#define PORT_OPC0_bp 3 /* Output/Pull Configuration bit 0 position. */ -#define PORT_OPC1_bm (1<<4) /* Output/Pull Configuration bit 1 mask. */ -#define PORT_OPC1_bp 4 /* Output/Pull Configuration bit 1 position. */ -#define PORT_OPC2_bm (1<<5) /* Output/Pull Configuration bit 2 mask. */ -#define PORT_OPC2_bp 5 /* Output/Pull Configuration bit 2 position. */ - -#define PORT_ISC_gm 0x07 /* Input/Sense Configuration group mask. */ -#define PORT_ISC_gp 0 /* Input/Sense Configuration group position. */ -#define PORT_ISC0_bm (1<<0) /* Input/Sense Configuration bit 0 mask. */ -#define PORT_ISC0_bp 0 /* Input/Sense Configuration bit 0 position. */ -#define PORT_ISC1_bm (1<<1) /* Input/Sense Configuration bit 1 mask. */ -#define PORT_ISC1_bp 1 /* Input/Sense Configuration bit 1 position. */ -#define PORT_ISC2_bm (1<<2) /* Input/Sense Configuration bit 2 mask. */ -#define PORT_ISC2_bp 2 /* Input/Sense Configuration bit 2 position. */ - -/* PORT.PIN1CTRL bit masks and bit positions */ -/* PORT_SRLEN Predefined. */ -/* PORT_SRLEN Predefined. */ - -/* PORT_INVEN Predefined. */ -/* PORT_INVEN Predefined. */ - -/* PORT_OPC Predefined. */ -/* PORT_OPC Predefined. */ - -/* PORT_ISC Predefined. */ -/* PORT_ISC Predefined. */ - -/* PORT.PIN2CTRL bit masks and bit positions */ -/* PORT_SRLEN Predefined. */ -/* PORT_SRLEN Predefined. */ - -/* PORT_INVEN Predefined. */ -/* PORT_INVEN Predefined. */ - -/* PORT_OPC Predefined. */ -/* PORT_OPC Predefined. */ - -/* PORT_ISC Predefined. */ -/* PORT_ISC Predefined. */ - -/* PORT.PIN3CTRL bit masks and bit positions */ -/* PORT_SRLEN Predefined. */ -/* PORT_SRLEN Predefined. */ - -/* PORT_INVEN Predefined. */ -/* PORT_INVEN Predefined. */ - -/* PORT_OPC Predefined. */ -/* PORT_OPC Predefined. */ - -/* PORT_ISC Predefined. */ -/* PORT_ISC Predefined. */ - -/* PORT.PIN4CTRL bit masks and bit positions */ -/* PORT_SRLEN Predefined. */ -/* PORT_SRLEN Predefined. */ - -/* PORT_INVEN Predefined. */ -/* PORT_INVEN Predefined. */ - -/* PORT_OPC Predefined. */ -/* PORT_OPC Predefined. */ - -/* PORT_ISC Predefined. */ -/* PORT_ISC Predefined. */ - -/* PORT.PIN5CTRL bit masks and bit positions */ -/* PORT_SRLEN Predefined. */ -/* PORT_SRLEN Predefined. */ - -/* PORT_INVEN Predefined. */ -/* PORT_INVEN Predefined. */ - -/* PORT_OPC Predefined. */ -/* PORT_OPC Predefined. */ - -/* PORT_ISC Predefined. */ -/* PORT_ISC Predefined. */ - -/* PORT.PIN6CTRL bit masks and bit positions */ -/* PORT_SRLEN Predefined. */ -/* PORT_SRLEN Predefined. */ - -/* PORT_INVEN Predefined. */ -/* PORT_INVEN Predefined. */ - -/* PORT_OPC Predefined. */ -/* PORT_OPC Predefined. */ - -/* PORT_ISC Predefined. */ -/* PORT_ISC Predefined. */ - -/* PORT.PIN7CTRL bit masks and bit positions */ -/* PORT_SRLEN Predefined. */ -/* PORT_SRLEN Predefined. */ - -/* PORT_INVEN Predefined. */ -/* PORT_INVEN Predefined. */ - -/* PORT_OPC Predefined. */ -/* PORT_OPC Predefined. */ - -/* PORT_ISC Predefined. */ -/* PORT_ISC Predefined. */ - -/* TC - 16-bit Timer/Counter With PWM */ -/* TC0.CTRLA bit masks and bit positions */ -#define TC0_CLKSEL_gm 0x0F /* Clock Selection group mask. */ -#define TC0_CLKSEL_gp 0 /* Clock Selection group position. */ -#define TC0_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ -#define TC0_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ -#define TC0_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ -#define TC0_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ -#define TC0_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ -#define TC0_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ -#define TC0_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ -#define TC0_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ - -/* TC0.CTRLB bit masks and bit positions */ -#define TC0_CCDEN_bm 0x80 /* Compare or Capture D Enable bit mask. */ -#define TC0_CCDEN_bp 7 /* Compare or Capture D Enable bit position. */ - -#define TC0_CCCEN_bm 0x40 /* Compare or Capture C Enable bit mask. */ -#define TC0_CCCEN_bp 6 /* Compare or Capture C Enable bit position. */ - -#define TC0_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ -#define TC0_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ - -#define TC0_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ -#define TC0_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ - -#define TC0_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ -#define TC0_WGMODE_gp 0 /* Waveform generation mode group position. */ -#define TC0_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ -#define TC0_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ -#define TC0_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ -#define TC0_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ -#define TC0_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ -#define TC0_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ - -/* TC0.CTRLC bit masks and bit positions */ -#define TC0_CMPD_bm 0x08 /* Compare D Output Value bit mask. */ -#define TC0_CMPD_bp 3 /* Compare D Output Value bit position. */ - -#define TC0_CMPC_bm 0x04 /* Compare C Output Value bit mask. */ -#define TC0_CMPC_bp 2 /* Compare C Output Value bit position. */ - -#define TC0_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ -#define TC0_CMPB_bp 1 /* Compare B Output Value bit position. */ - -#define TC0_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ -#define TC0_CMPA_bp 0 /* Compare A Output Value bit position. */ - -/* TC0.CTRLD bit masks and bit positions */ -#define TC0_EVACT_gm 0xE0 /* Event Action group mask. */ -#define TC0_EVACT_gp 5 /* Event Action group position. */ -#define TC0_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ -#define TC0_EVACT0_bp 5 /* Event Action bit 0 position. */ -#define TC0_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ -#define TC0_EVACT1_bp 6 /* Event Action bit 1 position. */ -#define TC0_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ -#define TC0_EVACT2_bp 7 /* Event Action bit 2 position. */ - -#define TC0_EVDLY_bm 0x10 /* Event Delay bit mask. */ -#define TC0_EVDLY_bp 4 /* Event Delay bit position. */ - -#define TC0_EVSEL_gm 0x0F /* Event Source Select group mask. */ -#define TC0_EVSEL_gp 0 /* Event Source Select group position. */ -#define TC0_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ -#define TC0_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ -#define TC0_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ -#define TC0_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ -#define TC0_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ -#define TC0_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ -#define TC0_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ -#define TC0_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ - -/* TC0.CTRLE bit masks and bit positions */ -#define TC0_BYTEM_gm 0x03 /* Byte Mode group mask. */ -#define TC0_BYTEM_gp 0 /* Byte Mode group position. */ -#define TC0_BYTEM0_bm (1<<0) /* Byte Mode bit 0 mask. */ -#define TC0_BYTEM0_bp 0 /* Byte Mode bit 0 position. */ -#define TC0_BYTEM1_bm (1<<1) /* Byte Mode bit 1 mask. */ -#define TC0_BYTEM1_bp 1 /* Byte Mode bit 1 position. */ - -/* TC0.INTCTRLA bit masks and bit positions */ -#define TC0_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ -#define TC0_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ -#define TC0_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ -#define TC0_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ -#define TC0_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ -#define TC0_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ - -#define TC0_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ -#define TC0_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ -#define TC0_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ -#define TC0_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ -#define TC0_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ -#define TC0_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ - -/* TC0.INTCTRLB bit masks and bit positions */ -#define TC0_CCDINTLVL_gm 0xC0 /* Compare or Capture D Interrupt Level group mask. */ -#define TC0_CCDINTLVL_gp 6 /* Compare or Capture D Interrupt Level group position. */ -#define TC0_CCDINTLVL0_bm (1<<6) /* Compare or Capture D Interrupt Level bit 0 mask. */ -#define TC0_CCDINTLVL0_bp 6 /* Compare or Capture D Interrupt Level bit 0 position. */ -#define TC0_CCDINTLVL1_bm (1<<7) /* Compare or Capture D Interrupt Level bit 1 mask. */ -#define TC0_CCDINTLVL1_bp 7 /* Compare or Capture D Interrupt Level bit 1 position. */ - -#define TC0_CCCINTLVL_gm 0x30 /* Compare or Capture C Interrupt Level group mask. */ -#define TC0_CCCINTLVL_gp 4 /* Compare or Capture C Interrupt Level group position. */ -#define TC0_CCCINTLVL0_bm (1<<4) /* Compare or Capture C Interrupt Level bit 0 mask. */ -#define TC0_CCCINTLVL0_bp 4 /* Compare or Capture C Interrupt Level bit 0 position. */ -#define TC0_CCCINTLVL1_bm (1<<5) /* Compare or Capture C Interrupt Level bit 1 mask. */ -#define TC0_CCCINTLVL1_bp 5 /* Compare or Capture C Interrupt Level bit 1 position. */ - -#define TC0_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ -#define TC0_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ -#define TC0_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ -#define TC0_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ -#define TC0_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ -#define TC0_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ - -#define TC0_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ -#define TC0_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ -#define TC0_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ -#define TC0_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ -#define TC0_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ -#define TC0_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ - -/* TC0.CTRLFCLR bit masks and bit positions */ -#define TC0_CMD_gm 0x0C /* Command group mask. */ -#define TC0_CMD_gp 2 /* Command group position. */ -#define TC0_CMD0_bm (1<<2) /* Command bit 0 mask. */ -#define TC0_CMD0_bp 2 /* Command bit 0 position. */ -#define TC0_CMD1_bm (1<<3) /* Command bit 1 mask. */ -#define TC0_CMD1_bp 3 /* Command bit 1 position. */ - -#define TC0_LUPD_bm 0x02 /* Lock Update bit mask. */ -#define TC0_LUPD_bp 1 /* Lock Update bit position. */ - -#define TC0_DIR_bm 0x01 /* Direction bit mask. */ -#define TC0_DIR_bp 0 /* Direction bit position. */ - -/* TC0.CTRLFSET bit masks and bit positions */ -/* TC0_CMD Predefined. */ -/* TC0_CMD Predefined. */ - -/* TC0_LUPD Predefined. */ -/* TC0_LUPD Predefined. */ - -/* TC0_DIR Predefined. */ -/* TC0_DIR Predefined. */ - -/* TC0.CTRLGCLR bit masks and bit positions */ -#define TC0_CCDBV_bm 0x10 /* Compare or Capture D Buffer Valid bit mask. */ -#define TC0_CCDBV_bp 4 /* Compare or Capture D Buffer Valid bit position. */ - -#define TC0_CCCBV_bm 0x08 /* Compare or Capture C Buffer Valid bit mask. */ -#define TC0_CCCBV_bp 3 /* Compare or Capture C Buffer Valid bit position. */ - -#define TC0_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ -#define TC0_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ - -#define TC0_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ -#define TC0_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ - -#define TC0_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ -#define TC0_PERBV_bp 0 /* Period Buffer Valid bit position. */ - -/* TC0.CTRLGSET bit masks and bit positions */ -/* TC0_CCDBV Predefined. */ -/* TC0_CCDBV Predefined. */ - -/* TC0_CCCBV Predefined. */ -/* TC0_CCCBV Predefined. */ - -/* TC0_CCBBV Predefined. */ -/* TC0_CCBBV Predefined. */ - -/* TC0_CCABV Predefined. */ -/* TC0_CCABV Predefined. */ - -/* TC0_PERBV Predefined. */ -/* TC0_PERBV Predefined. */ - -/* TC0.INTFLAGS bit masks and bit positions */ -#define TC0_CCDIF_bm 0x80 /* Compare or Capture D Interrupt Flag bit mask. */ -#define TC0_CCDIF_bp 7 /* Compare or Capture D Interrupt Flag bit position. */ - -#define TC0_CCCIF_bm 0x40 /* Compare or Capture C Interrupt Flag bit mask. */ -#define TC0_CCCIF_bp 6 /* Compare or Capture C Interrupt Flag bit position. */ - -#define TC0_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ -#define TC0_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ - -#define TC0_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ -#define TC0_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ - -#define TC0_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ -#define TC0_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ - -#define TC0_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ -#define TC0_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ - -/* TC1.CTRLA bit masks and bit positions */ -#define TC1_CLKSEL_gm 0x0F /* Clock Selection group mask. */ -#define TC1_CLKSEL_gp 0 /* Clock Selection group position. */ -#define TC1_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ -#define TC1_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ -#define TC1_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ -#define TC1_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ -#define TC1_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ -#define TC1_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ -#define TC1_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ -#define TC1_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ - -/* TC1.CTRLB bit masks and bit positions */ -#define TC1_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ -#define TC1_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ - -#define TC1_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ -#define TC1_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ - -#define TC1_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ -#define TC1_WGMODE_gp 0 /* Waveform generation mode group position. */ -#define TC1_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ -#define TC1_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ -#define TC1_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ -#define TC1_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ -#define TC1_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ -#define TC1_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ - -/* TC1.CTRLC bit masks and bit positions */ -#define TC1_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ -#define TC1_CMPB_bp 1 /* Compare B Output Value bit position. */ - -#define TC1_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ -#define TC1_CMPA_bp 0 /* Compare A Output Value bit position. */ - -/* TC1.CTRLD bit masks and bit positions */ -#define TC1_EVACT_gm 0xE0 /* Event Action group mask. */ -#define TC1_EVACT_gp 5 /* Event Action group position. */ -#define TC1_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ -#define TC1_EVACT0_bp 5 /* Event Action bit 0 position. */ -#define TC1_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ -#define TC1_EVACT1_bp 6 /* Event Action bit 1 position. */ -#define TC1_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ -#define TC1_EVACT2_bp 7 /* Event Action bit 2 position. */ - -#define TC1_EVDLY_bm 0x10 /* Event Delay bit mask. */ -#define TC1_EVDLY_bp 4 /* Event Delay bit position. */ - -#define TC1_EVSEL_gm 0x0F /* Event Source Select group mask. */ -#define TC1_EVSEL_gp 0 /* Event Source Select group position. */ -#define TC1_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ -#define TC1_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ -#define TC1_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ -#define TC1_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ -#define TC1_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ -#define TC1_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ -#define TC1_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ -#define TC1_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ - -/* TC1.CTRLE bit masks and bit positions */ -#define TC1_BYTEM_bm 0x01 /* Byte Mode bit mask. */ -#define TC1_BYTEM_bp 0 /* Byte Mode bit position. */ - -/* TC1.INTCTRLA bit masks and bit positions */ -#define TC1_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ -#define TC1_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ -#define TC1_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ -#define TC1_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ -#define TC1_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ -#define TC1_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ - -#define TC1_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ -#define TC1_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ -#define TC1_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ -#define TC1_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ -#define TC1_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ -#define TC1_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ - -/* TC1.INTCTRLB bit masks and bit positions */ -#define TC1_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ -#define TC1_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ -#define TC1_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ -#define TC1_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ -#define TC1_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ -#define TC1_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ - -#define TC1_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ -#define TC1_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ -#define TC1_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ -#define TC1_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ -#define TC1_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ -#define TC1_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ - -/* TC1.CTRLFCLR bit masks and bit positions */ -#define TC1_CMD_gm 0x0C /* Command group mask. */ -#define TC1_CMD_gp 2 /* Command group position. */ -#define TC1_CMD0_bm (1<<2) /* Command bit 0 mask. */ -#define TC1_CMD0_bp 2 /* Command bit 0 position. */ -#define TC1_CMD1_bm (1<<3) /* Command bit 1 mask. */ -#define TC1_CMD1_bp 3 /* Command bit 1 position. */ - -#define TC1_LUPD_bm 0x02 /* Lock Update bit mask. */ -#define TC1_LUPD_bp 1 /* Lock Update bit position. */ - -#define TC1_DIR_bm 0x01 /* Direction bit mask. */ -#define TC1_DIR_bp 0 /* Direction bit position. */ - -/* TC1.CTRLFSET bit masks and bit positions */ -/* TC1_CMD Predefined. */ -/* TC1_CMD Predefined. */ - -/* TC1_LUPD Predefined. */ -/* TC1_LUPD Predefined. */ - -/* TC1_DIR Predefined. */ -/* TC1_DIR Predefined. */ - -/* TC1.CTRLGCLR bit masks and bit positions */ -#define TC1_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ -#define TC1_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ - -#define TC1_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ -#define TC1_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ - -#define TC1_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ -#define TC1_PERBV_bp 0 /* Period Buffer Valid bit position. */ - -/* TC1.CTRLGSET bit masks and bit positions */ -/* TC1_CCBBV Predefined. */ -/* TC1_CCBBV Predefined. */ - -/* TC1_CCABV Predefined. */ -/* TC1_CCABV Predefined. */ - -/* TC1_PERBV Predefined. */ -/* TC1_PERBV Predefined. */ - -/* TC1.INTFLAGS bit masks and bit positions */ -#define TC1_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ -#define TC1_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ - -#define TC1_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ -#define TC1_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ - -#define TC1_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ -#define TC1_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ - -#define TC1_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ -#define TC1_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ - -/* TC2 - 16-bit Timer/Counter type 2 */ -/* TC2.CTRLA bit masks and bit positions */ -#define TC2_CLKSEL_gm 0x0F /* Clock Selection group mask. */ -#define TC2_CLKSEL_gp 0 /* Clock Selection group position. */ -#define TC2_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ -#define TC2_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ -#define TC2_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ -#define TC2_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ -#define TC2_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ -#define TC2_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ -#define TC2_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ -#define TC2_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ - -/* TC2.CTRLB bit masks and bit positions */ -#define TC2_HCMPDEN_bm 0x80 /* High Byte Compare D Enable bit mask. */ -#define TC2_HCMPDEN_bp 7 /* High Byte Compare D Enable bit position. */ - -#define TC2_HCMPCEN_bm 0x40 /* High Byte Compare C Enable bit mask. */ -#define TC2_HCMPCEN_bp 6 /* High Byte Compare C Enable bit position. */ - -#define TC2_HCMPBEN_bm 0x20 /* High Byte Compare B Enable bit mask. */ -#define TC2_HCMPBEN_bp 5 /* High Byte Compare B Enable bit position. */ - -#define TC2_HCMPAEN_bm 0x10 /* High Byte Compare A Enable bit mask. */ -#define TC2_HCMPAEN_bp 4 /* High Byte Compare A Enable bit position. */ - -#define TC2_LCMPDEN_bm 0x08 /* Low Byte Compare D Enable bit mask. */ -#define TC2_LCMPDEN_bp 3 /* Low Byte Compare D Enable bit position. */ - -#define TC2_LCMPCEN_bm 0x04 /* Low Byte Compare C Enable bit mask. */ -#define TC2_LCMPCEN_bp 2 /* Low Byte Compare C Enable bit position. */ - -#define TC2_LCMPBEN_bm 0x02 /* Low Byte Compare B Enable bit mask. */ -#define TC2_LCMPBEN_bp 1 /* Low Byte Compare B Enable bit position. */ - -#define TC2_LCMPAEN_bm 0x01 /* Low Byte Compare A Enable bit mask. */ -#define TC2_LCMPAEN_bp 0 /* Low Byte Compare A Enable bit position. */ - -/* TC2.CTRLC bit masks and bit positions */ -#define TC2_HCMPD_bm 0x80 /* High Byte Compare D Output Value bit mask. */ -#define TC2_HCMPD_bp 7 /* High Byte Compare D Output Value bit position. */ - -#define TC2_HCMPC_bm 0x40 /* High Byte Compare C Output Value bit mask. */ -#define TC2_HCMPC_bp 6 /* High Byte Compare C Output Value bit position. */ - -#define TC2_HCMPB_bm 0x20 /* High Byte Compare B Output Value bit mask. */ -#define TC2_HCMPB_bp 5 /* High Byte Compare B Output Value bit position. */ - -#define TC2_HCMPA_bm 0x10 /* High Byte Compare A Output Value bit mask. */ -#define TC2_HCMPA_bp 4 /* High Byte Compare A Output Value bit position. */ - -#define TC2_LCMPD_bm 0x08 /* Low Byte Compare D Output Value bit mask. */ -#define TC2_LCMPD_bp 3 /* Low Byte Compare D Output Value bit position. */ - -#define TC2_LCMPC_bm 0x04 /* Low Byte Compare C Output Value bit mask. */ -#define TC2_LCMPC_bp 2 /* Low Byte Compare C Output Value bit position. */ - -#define TC2_LCMPB_bm 0x02 /* Low Byte Compare B Output Value bit mask. */ -#define TC2_LCMPB_bp 1 /* Low Byte Compare B Output Value bit position. */ - -#define TC2_LCMPA_bm 0x01 /* Low Byte Compare A Output Value bit mask. */ -#define TC2_LCMPA_bp 0 /* Low Byte Compare A Output Value bit position. */ - -/* TC2.CTRLE bit masks and bit positions */ -#define TC2_BYTEM_gm 0x03 /* Byte Mode group mask. */ -#define TC2_BYTEM_gp 0 /* Byte Mode group position. */ -#define TC2_BYTEM0_bm (1<<0) /* Byte Mode bit 0 mask. */ -#define TC2_BYTEM0_bp 0 /* Byte Mode bit 0 position. */ -#define TC2_BYTEM1_bm (1<<1) /* Byte Mode bit 1 mask. */ -#define TC2_BYTEM1_bp 1 /* Byte Mode bit 1 position. */ - -/* TC2.INTCTRLA bit masks and bit positions */ -#define TC2_HUNFINTLVL_gm 0x0C /* High Byte Underflow Interrupt Level group mask. */ -#define TC2_HUNFINTLVL_gp 2 /* High Byte Underflow Interrupt Level group position. */ -#define TC2_HUNFINTLVL0_bm (1<<2) /* High Byte Underflow Interrupt Level bit 0 mask. */ -#define TC2_HUNFINTLVL0_bp 2 /* High Byte Underflow Interrupt Level bit 0 position. */ -#define TC2_HUNFINTLVL1_bm (1<<3) /* High Byte Underflow Interrupt Level bit 1 mask. */ -#define TC2_HUNFINTLVL1_bp 3 /* High Byte Underflow Interrupt Level bit 1 position. */ - -#define TC2_LUNFINTLVL_gm 0x03 /* Low Byte Underflow interrupt level group mask. */ -#define TC2_LUNFINTLVL_gp 0 /* Low Byte Underflow interrupt level group position. */ -#define TC2_LUNFINTLVL0_bm (1<<0) /* Low Byte Underflow interrupt level bit 0 mask. */ -#define TC2_LUNFINTLVL0_bp 0 /* Low Byte Underflow interrupt level bit 0 position. */ -#define TC2_LUNFINTLVL1_bm (1<<1) /* Low Byte Underflow interrupt level bit 1 mask. */ -#define TC2_LUNFINTLVL1_bp 1 /* Low Byte Underflow interrupt level bit 1 position. */ - -/* TC2.INTCTRLB bit masks and bit positions */ -#define TC2_LCMPDINTLVL_gm 0xC0 /* Low Byte Compare D Interrupt Level group mask. */ -#define TC2_LCMPDINTLVL_gp 6 /* Low Byte Compare D Interrupt Level group position. */ -#define TC2_LCMPDINTLVL0_bm (1<<6) /* Low Byte Compare D Interrupt Level bit 0 mask. */ -#define TC2_LCMPDINTLVL0_bp 6 /* Low Byte Compare D Interrupt Level bit 0 position. */ -#define TC2_LCMPDINTLVL1_bm (1<<7) /* Low Byte Compare D Interrupt Level bit 1 mask. */ -#define TC2_LCMPDINTLVL1_bp 7 /* Low Byte Compare D Interrupt Level bit 1 position. */ - -#define TC2_LCMPCINTLVL_gm 0x30 /* Low Byte Compare C Interrupt Level group mask. */ -#define TC2_LCMPCINTLVL_gp 4 /* Low Byte Compare C Interrupt Level group position. */ -#define TC2_LCMPCINTLVL0_bm (1<<4) /* Low Byte Compare C Interrupt Level bit 0 mask. */ -#define TC2_LCMPCINTLVL0_bp 4 /* Low Byte Compare C Interrupt Level bit 0 position. */ -#define TC2_LCMPCINTLVL1_bm (1<<5) /* Low Byte Compare C Interrupt Level bit 1 mask. */ -#define TC2_LCMPCINTLVL1_bp 5 /* Low Byte Compare C Interrupt Level bit 1 position. */ - -#define TC2_LCMPBINTLVL_gm 0x0C /* Low Byte Compare B Interrupt Level group mask. */ -#define TC2_LCMPBINTLVL_gp 2 /* Low Byte Compare B Interrupt Level group position. */ -#define TC2_LCMPBINTLVL0_bm (1<<2) /* Low Byte Compare B Interrupt Level bit 0 mask. */ -#define TC2_LCMPBINTLVL0_bp 2 /* Low Byte Compare B Interrupt Level bit 0 position. */ -#define TC2_LCMPBINTLVL1_bm (1<<3) /* Low Byte Compare B Interrupt Level bit 1 mask. */ -#define TC2_LCMPBINTLVL1_bp 3 /* Low Byte Compare B Interrupt Level bit 1 position. */ - -#define TC2_LCMPAINTLVL_gm 0x03 /* Low Byte Compare A Interrupt Level group mask. */ -#define TC2_LCMPAINTLVL_gp 0 /* Low Byte Compare A Interrupt Level group position. */ -#define TC2_LCMPAINTLVL0_bm (1<<0) /* Low Byte Compare A Interrupt Level bit 0 mask. */ -#define TC2_LCMPAINTLVL0_bp 0 /* Low Byte Compare A Interrupt Level bit 0 position. */ -#define TC2_LCMPAINTLVL1_bm (1<<1) /* Low Byte Compare A Interrupt Level bit 1 mask. */ -#define TC2_LCMPAINTLVL1_bp 1 /* Low Byte Compare A Interrupt Level bit 1 position. */ - -/* TC2.CTRLF bit masks and bit positions */ -#define TC2_CMD_gm 0x0C /* Command group mask. */ -#define TC2_CMD_gp 2 /* Command group position. */ -#define TC2_CMD0_bm (1<<2) /* Command bit 0 mask. */ -#define TC2_CMD0_bp 2 /* Command bit 0 position. */ -#define TC2_CMD1_bm (1<<3) /* Command bit 1 mask. */ -#define TC2_CMD1_bp 3 /* Command bit 1 position. */ - -#define TC2_CMDEN_gm 0x03 /* Command Enable group mask. */ -#define TC2_CMDEN_gp 0 /* Command Enable group position. */ -#define TC2_CMDEN0_bm (1<<0) /* Command Enable bit 0 mask. */ -#define TC2_CMDEN0_bp 0 /* Command Enable bit 0 position. */ -#define TC2_CMDEN1_bm (1<<1) /* Command Enable bit 1 mask. */ -#define TC2_CMDEN1_bp 1 /* Command Enable bit 1 position. */ - -/* TC2.INTFLAGS bit masks and bit positions */ -#define TC2_LCMPDIF_bm 0x80 /* Low Byte Compare D Interrupt Flag bit mask. */ -#define TC2_LCMPDIF_bp 7 /* Low Byte Compare D Interrupt Flag bit position. */ - -#define TC2_LCMPCIF_bm 0x40 /* Low Byte Compare C Interrupt Flag bit mask. */ -#define TC2_LCMPCIF_bp 6 /* Low Byte Compare C Interrupt Flag bit position. */ - -#define TC2_LCMPBIF_bm 0x20 /* Low Byte Compare B Interrupt Flag bit mask. */ -#define TC2_LCMPBIF_bp 5 /* Low Byte Compare B Interrupt Flag bit position. */ - -#define TC2_LCMPAIF_bm 0x10 /* Low Byte Compare A Interrupt Flag bit mask. */ -#define TC2_LCMPAIF_bp 4 /* Low Byte Compare A Interrupt Flag bit position. */ - -#define TC2_HUNFIF_bm 0x02 /* High Byte Underflow Interrupt Flag bit mask. */ -#define TC2_HUNFIF_bp 1 /* High Byte Underflow Interrupt Flag bit position. */ - -#define TC2_LUNFIF_bm 0x01 /* Low Byte Underflow Interrupt Flag bit mask. */ -#define TC2_LUNFIF_bp 0 /* Low Byte Underflow Interrupt Flag bit position. */ - -/* AWEX - Timer/Counter Advanced Waveform Extension */ -/* AWEX.CTRL bit masks and bit positions */ -#define AWEX_PGM_bm 0x20 /* Pattern Generation Mode bit mask. */ -#define AWEX_PGM_bp 5 /* Pattern Generation Mode bit position. */ - -#define AWEX_CWCM_bm 0x10 /* Common Waveform Channel Mode bit mask. */ -#define AWEX_CWCM_bp 4 /* Common Waveform Channel Mode bit position. */ - -#define AWEX_DTICCDEN_bm 0x08 /* Dead Time Insertion Compare Channel D Enable bit mask. */ -#define AWEX_DTICCDEN_bp 3 /* Dead Time Insertion Compare Channel D Enable bit position. */ - -#define AWEX_DTICCCEN_bm 0x04 /* Dead Time Insertion Compare Channel C Enable bit mask. */ -#define AWEX_DTICCCEN_bp 2 /* Dead Time Insertion Compare Channel C Enable bit position. */ - -#define AWEX_DTICCBEN_bm 0x02 /* Dead Time Insertion Compare Channel B Enable bit mask. */ -#define AWEX_DTICCBEN_bp 1 /* Dead Time Insertion Compare Channel B Enable bit position. */ - -#define AWEX_DTICCAEN_bm 0x01 /* Dead Time Insertion Compare Channel A Enable bit mask. */ -#define AWEX_DTICCAEN_bp 0 /* Dead Time Insertion Compare Channel A Enable bit position. */ - -/* AWEX.FDCTRL bit masks and bit positions */ -#define AWEX_FDDBD_bm 0x10 /* Fault Detect on Disable Break Disable bit mask. */ -#define AWEX_FDDBD_bp 4 /* Fault Detect on Disable Break Disable bit position. */ - -#define AWEX_FDMODE_bm 0x04 /* Fault Detect Mode bit mask. */ -#define AWEX_FDMODE_bp 2 /* Fault Detect Mode bit position. */ - -#define AWEX_FDACT_gm 0x03 /* Fault Detect Action group mask. */ -#define AWEX_FDACT_gp 0 /* Fault Detect Action group position. */ -#define AWEX_FDACT0_bm (1<<0) /* Fault Detect Action bit 0 mask. */ -#define AWEX_FDACT0_bp 0 /* Fault Detect Action bit 0 position. */ -#define AWEX_FDACT1_bm (1<<1) /* Fault Detect Action bit 1 mask. */ -#define AWEX_FDACT1_bp 1 /* Fault Detect Action bit 1 position. */ - -/* AWEX.STATUS bit masks and bit positions */ -#define AWEX_FDF_bm 0x04 /* Fault Detect Flag bit mask. */ -#define AWEX_FDF_bp 2 /* Fault Detect Flag bit position. */ - -#define AWEX_DTHSBUFV_bm 0x02 /* Dead Time High Side Buffer Valid bit mask. */ -#define AWEX_DTHSBUFV_bp 1 /* Dead Time High Side Buffer Valid bit position. */ - -#define AWEX_DTLSBUFV_bm 0x01 /* Dead Time Low Side Buffer Valid bit mask. */ -#define AWEX_DTLSBUFV_bp 0 /* Dead Time Low Side Buffer Valid bit position. */ - -/* AWEX.STATUSSET bit masks and bit positions */ -/* AWEX_FDF Predefined. */ -/* AWEX_FDF Predefined. */ - -/* AWEX_DTHSBUFV Predefined. */ -/* AWEX_DTHSBUFV Predefined. */ - -/* AWEX_DTLSBUFV Predefined. */ -/* AWEX_DTLSBUFV Predefined. */ - -/* HIRES - Timer/Counter High-Resolution Extension */ -/* HIRES.CTRLA bit masks and bit positions */ -#define HIRES_HREN_gm 0x03 /* High Resolution Enable group mask. */ -#define HIRES_HREN_gp 0 /* High Resolution Enable group position. */ -#define HIRES_HREN0_bm (1<<0) /* High Resolution Enable bit 0 mask. */ -#define HIRES_HREN0_bp 0 /* High Resolution Enable bit 0 position. */ -#define HIRES_HREN1_bm (1<<1) /* High Resolution Enable bit 1 mask. */ -#define HIRES_HREN1_bp 1 /* High Resolution Enable bit 1 position. */ - -/* USART - Universal Asynchronous Receiver-Transmitter */ -/* USART.STATUS bit masks and bit positions */ -#define USART_RXCIF_bm 0x80 /* Receive Interrupt Flag bit mask. */ -#define USART_RXCIF_bp 7 /* Receive Interrupt Flag bit position. */ - -#define USART_TXCIF_bm 0x40 /* Transmit Interrupt Flag bit mask. */ -#define USART_TXCIF_bp 6 /* Transmit Interrupt Flag bit position. */ - -#define USART_DREIF_bm 0x20 /* Data Register Empty Flag bit mask. */ -#define USART_DREIF_bp 5 /* Data Register Empty Flag bit position. */ - -#define USART_FERR_bm 0x10 /* Frame Error bit mask. */ -#define USART_FERR_bp 4 /* Frame Error bit position. */ - -#define USART_BUFOVF_bm 0x08 /* Buffer Overflow bit mask. */ -#define USART_BUFOVF_bp 3 /* Buffer Overflow bit position. */ - -#define USART_PERR_bm 0x04 /* Parity Error bit mask. */ -#define USART_PERR_bp 2 /* Parity Error bit position. */ - -#define USART_RXB8_bm 0x01 /* Receive Bit 8 bit mask. */ -#define USART_RXB8_bp 0 /* Receive Bit 8 bit position. */ - -/* USART.CTRLA bit masks and bit positions */ -#define USART_RXCINTLVL_gm 0x30 /* Receive Interrupt Level group mask. */ -#define USART_RXCINTLVL_gp 4 /* Receive Interrupt Level group position. */ -#define USART_RXCINTLVL0_bm (1<<4) /* Receive Interrupt Level bit 0 mask. */ -#define USART_RXCINTLVL0_bp 4 /* Receive Interrupt Level bit 0 position. */ -#define USART_RXCINTLVL1_bm (1<<5) /* Receive Interrupt Level bit 1 mask. */ -#define USART_RXCINTLVL1_bp 5 /* Receive Interrupt Level bit 1 position. */ - -#define USART_TXCINTLVL_gm 0x0C /* Transmit Interrupt Level group mask. */ -#define USART_TXCINTLVL_gp 2 /* Transmit Interrupt Level group position. */ -#define USART_TXCINTLVL0_bm (1<<2) /* Transmit Interrupt Level bit 0 mask. */ -#define USART_TXCINTLVL0_bp 2 /* Transmit Interrupt Level bit 0 position. */ -#define USART_TXCINTLVL1_bm (1<<3) /* Transmit Interrupt Level bit 1 mask. */ -#define USART_TXCINTLVL1_bp 3 /* Transmit Interrupt Level bit 1 position. */ - -#define USART_DREINTLVL_gm 0x03 /* Data Register Empty Interrupt Level group mask. */ -#define USART_DREINTLVL_gp 0 /* Data Register Empty Interrupt Level group position. */ -#define USART_DREINTLVL0_bm (1<<0) /* Data Register Empty Interrupt Level bit 0 mask. */ -#define USART_DREINTLVL0_bp 0 /* Data Register Empty Interrupt Level bit 0 position. */ -#define USART_DREINTLVL1_bm (1<<1) /* Data Register Empty Interrupt Level bit 1 mask. */ -#define USART_DREINTLVL1_bp 1 /* Data Register Empty Interrupt Level bit 1 position. */ - -/* USART.CTRLB bit masks and bit positions */ -#define USART_RXEN_bm 0x10 /* Receiver Enable bit mask. */ -#define USART_RXEN_bp 4 /* Receiver Enable bit position. */ - -#define USART_TXEN_bm 0x08 /* Transmitter Enable bit mask. */ -#define USART_TXEN_bp 3 /* Transmitter Enable bit position. */ - -#define USART_CLK2X_bm 0x04 /* Double transmission speed bit mask. */ -#define USART_CLK2X_bp 2 /* Double transmission speed bit position. */ - -#define USART_MPCM_bm 0x02 /* Multi-processor Communication Mode bit mask. */ -#define USART_MPCM_bp 1 /* Multi-processor Communication Mode bit position. */ - -#define USART_TXB8_bm 0x01 /* Transmit bit 8 bit mask. */ -#define USART_TXB8_bp 0 /* Transmit bit 8 bit position. */ - -/* USART.CTRLC bit masks and bit positions */ -#define USART_CMODE_gm 0xC0 /* Communication Mode group mask. */ -#define USART_CMODE_gp 6 /* Communication Mode group position. */ -#define USART_CMODE0_bm (1<<6) /* Communication Mode bit 0 mask. */ -#define USART_CMODE0_bp 6 /* Communication Mode bit 0 position. */ -#define USART_CMODE1_bm (1<<7) /* Communication Mode bit 1 mask. */ -#define USART_CMODE1_bp 7 /* Communication Mode bit 1 position. */ - -#define USART_PMODE_gm 0x30 /* Parity Mode group mask. */ -#define USART_PMODE_gp 4 /* Parity Mode group position. */ -#define USART_PMODE0_bm (1<<4) /* Parity Mode bit 0 mask. */ -#define USART_PMODE0_bp 4 /* Parity Mode bit 0 position. */ -#define USART_PMODE1_bm (1<<5) /* Parity Mode bit 1 mask. */ -#define USART_PMODE1_bp 5 /* Parity Mode bit 1 position. */ - -#define USART_SBMODE_bm 0x08 /* Stop Bit Mode bit mask. */ -#define USART_SBMODE_bp 3 /* Stop Bit Mode bit position. */ - -#define USART_CHSIZE_gm 0x07 /* Character Size group mask. */ -#define USART_CHSIZE_gp 0 /* Character Size group position. */ -#define USART_CHSIZE0_bm (1<<0) /* Character Size bit 0 mask. */ -#define USART_CHSIZE0_bp 0 /* Character Size bit 0 position. */ -#define USART_CHSIZE1_bm (1<<1) /* Character Size bit 1 mask. */ -#define USART_CHSIZE1_bp 1 /* Character Size bit 1 position. */ -#define USART_CHSIZE2_bm (1<<2) /* Character Size bit 2 mask. */ -#define USART_CHSIZE2_bp 2 /* Character Size bit 2 position. */ - -/* USART.BAUDCTRLA bit masks and bit positions */ -#define USART_BSEL_gm 0xFF /* Baud Rate Selection Bits [7:0] group mask. */ -#define USART_BSEL_gp 0 /* Baud Rate Selection Bits [7:0] group position. */ -#define USART_BSEL0_bm (1<<0) /* Baud Rate Selection Bits [7:0] bit 0 mask. */ -#define USART_BSEL0_bp 0 /* Baud Rate Selection Bits [7:0] bit 0 position. */ -#define USART_BSEL1_bm (1<<1) /* Baud Rate Selection Bits [7:0] bit 1 mask. */ -#define USART_BSEL1_bp 1 /* Baud Rate Selection Bits [7:0] bit 1 position. */ -#define USART_BSEL2_bm (1<<2) /* Baud Rate Selection Bits [7:0] bit 2 mask. */ -#define USART_BSEL2_bp 2 /* Baud Rate Selection Bits [7:0] bit 2 position. */ -#define USART_BSEL3_bm (1<<3) /* Baud Rate Selection Bits [7:0] bit 3 mask. */ -#define USART_BSEL3_bp 3 /* Baud Rate Selection Bits [7:0] bit 3 position. */ -#define USART_BSEL4_bm (1<<4) /* Baud Rate Selection Bits [7:0] bit 4 mask. */ -#define USART_BSEL4_bp 4 /* Baud Rate Selection Bits [7:0] bit 4 position. */ -#define USART_BSEL5_bm (1<<5) /* Baud Rate Selection Bits [7:0] bit 5 mask. */ -#define USART_BSEL5_bp 5 /* Baud Rate Selection Bits [7:0] bit 5 position. */ -#define USART_BSEL6_bm (1<<6) /* Baud Rate Selection Bits [7:0] bit 6 mask. */ -#define USART_BSEL6_bp 6 /* Baud Rate Selection Bits [7:0] bit 6 position. */ -#define USART_BSEL7_bm (1<<7) /* Baud Rate Selection Bits [7:0] bit 7 mask. */ -#define USART_BSEL7_bp 7 /* Baud Rate Selection Bits [7:0] bit 7 position. */ - -/* USART.BAUDCTRLB bit masks and bit positions */ -#define USART_BSCALE_gm 0xF0 /* Baud Rate Scale group mask. */ -#define USART_BSCALE_gp 4 /* Baud Rate Scale group position. */ -#define USART_BSCALE0_bm (1<<4) /* Baud Rate Scale bit 0 mask. */ -#define USART_BSCALE0_bp 4 /* Baud Rate Scale bit 0 position. */ -#define USART_BSCALE1_bm (1<<5) /* Baud Rate Scale bit 1 mask. */ -#define USART_BSCALE1_bp 5 /* Baud Rate Scale bit 1 position. */ -#define USART_BSCALE2_bm (1<<6) /* Baud Rate Scale bit 2 mask. */ -#define USART_BSCALE2_bp 6 /* Baud Rate Scale bit 2 position. */ -#define USART_BSCALE3_bm (1<<7) /* Baud Rate Scale bit 3 mask. */ -#define USART_BSCALE3_bp 7 /* Baud Rate Scale bit 3 position. */ - -/* USART_BSEL Predefined. */ -/* USART_BSEL Predefined. */ - -/* SPI - Serial Peripheral Interface */ -/* SPI.CTRL bit masks and bit positions */ -#define SPI_CLK2X_bm 0x80 /* Enable Double Speed bit mask. */ -#define SPI_CLK2X_bp 7 /* Enable Double Speed bit position. */ - -#define SPI_ENABLE_bm 0x40 /* Enable Module bit mask. */ -#define SPI_ENABLE_bp 6 /* Enable Module bit position. */ - -#define SPI_DORD_bm 0x20 /* Data Order Setting bit mask. */ -#define SPI_DORD_bp 5 /* Data Order Setting bit position. */ - -#define SPI_MASTER_bm 0x10 /* Master Operation Enable bit mask. */ -#define SPI_MASTER_bp 4 /* Master Operation Enable bit position. */ - -#define SPI_MODE_gm 0x0C /* SPI Mode group mask. */ -#define SPI_MODE_gp 2 /* SPI Mode group position. */ -#define SPI_MODE0_bm (1<<2) /* SPI Mode bit 0 mask. */ -#define SPI_MODE0_bp 2 /* SPI Mode bit 0 position. */ -#define SPI_MODE1_bm (1<<3) /* SPI Mode bit 1 mask. */ -#define SPI_MODE1_bp 3 /* SPI Mode bit 1 position. */ - -#define SPI_PRESCALER_gm 0x03 /* Prescaler group mask. */ -#define SPI_PRESCALER_gp 0 /* Prescaler group position. */ -#define SPI_PRESCALER0_bm (1<<0) /* Prescaler bit 0 mask. */ -#define SPI_PRESCALER0_bp 0 /* Prescaler bit 0 position. */ -#define SPI_PRESCALER1_bm (1<<1) /* Prescaler bit 1 mask. */ -#define SPI_PRESCALER1_bp 1 /* Prescaler bit 1 position. */ - -/* SPI.INTCTRL bit masks and bit positions */ -#define SPI_INTLVL_gm 0x03 /* Interrupt level group mask. */ -#define SPI_INTLVL_gp 0 /* Interrupt level group position. */ -#define SPI_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */ -#define SPI_INTLVL0_bp 0 /* Interrupt level bit 0 position. */ -#define SPI_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */ -#define SPI_INTLVL1_bp 1 /* Interrupt level bit 1 position. */ - -/* SPI.STATUS bit masks and bit positions */ -#define SPI_IF_bm 0x80 /* Interrupt Flag bit mask. */ -#define SPI_IF_bp 7 /* Interrupt Flag bit position. */ - -#define SPI_WRCOL_bm 0x40 /* Write Collision bit mask. */ -#define SPI_WRCOL_bp 6 /* Write Collision bit position. */ - -/* IRCOM - IR Communication Module */ -/* IRCOM.CTRL bit masks and bit positions */ -#define IRCOM_EVSEL_gm 0x0F /* Event Channel Select group mask. */ -#define IRCOM_EVSEL_gp 0 /* Event Channel Select group position. */ -#define IRCOM_EVSEL0_bm (1<<0) /* Event Channel Select bit 0 mask. */ -#define IRCOM_EVSEL0_bp 0 /* Event Channel Select bit 0 position. */ -#define IRCOM_EVSEL1_bm (1<<1) /* Event Channel Select bit 1 mask. */ -#define IRCOM_EVSEL1_bp 1 /* Event Channel Select bit 1 position. */ -#define IRCOM_EVSEL2_bm (1<<2) /* Event Channel Select bit 2 mask. */ -#define IRCOM_EVSEL2_bp 2 /* Event Channel Select bit 2 position. */ -#define IRCOM_EVSEL3_bm (1<<3) /* Event Channel Select bit 3 mask. */ -#define IRCOM_EVSEL3_bp 3 /* Event Channel Select bit 3 position. */ - -/* FUSE - Fuses and Lockbits */ -/* NVM_FUSES.FUSEBYTE1 bit masks and bit positions */ -#define NVM_FUSES_WDWP_gm 0xF0 /* Watchdog Window Timeout Period group mask. */ -#define NVM_FUSES_WDWP_gp 4 /* Watchdog Window Timeout Period group position. */ -#define NVM_FUSES_WDWP0_bm (1<<4) /* Watchdog Window Timeout Period bit 0 mask. */ -#define NVM_FUSES_WDWP0_bp 4 /* Watchdog Window Timeout Period bit 0 position. */ -#define NVM_FUSES_WDWP1_bm (1<<5) /* Watchdog Window Timeout Period bit 1 mask. */ -#define NVM_FUSES_WDWP1_bp 5 /* Watchdog Window Timeout Period bit 1 position. */ -#define NVM_FUSES_WDWP2_bm (1<<6) /* Watchdog Window Timeout Period bit 2 mask. */ -#define NVM_FUSES_WDWP2_bp 6 /* Watchdog Window Timeout Period bit 2 position. */ -#define NVM_FUSES_WDWP3_bm (1<<7) /* Watchdog Window Timeout Period bit 3 mask. */ -#define NVM_FUSES_WDWP3_bp 7 /* Watchdog Window Timeout Period bit 3 position. */ - -#define NVM_FUSES_WDP_gm 0x0F /* Watchdog Timeout Period group mask. */ -#define NVM_FUSES_WDP_gp 0 /* Watchdog Timeout Period group position. */ -#define NVM_FUSES_WDP0_bm (1<<0) /* Watchdog Timeout Period bit 0 mask. */ -#define NVM_FUSES_WDP0_bp 0 /* Watchdog Timeout Period bit 0 position. */ -#define NVM_FUSES_WDP1_bm (1<<1) /* Watchdog Timeout Period bit 1 mask. */ -#define NVM_FUSES_WDP1_bp 1 /* Watchdog Timeout Period bit 1 position. */ -#define NVM_FUSES_WDP2_bm (1<<2) /* Watchdog Timeout Period bit 2 mask. */ -#define NVM_FUSES_WDP2_bp 2 /* Watchdog Timeout Period bit 2 position. */ -#define NVM_FUSES_WDP3_bm (1<<3) /* Watchdog Timeout Period bit 3 mask. */ -#define NVM_FUSES_WDP3_bp 3 /* Watchdog Timeout Period bit 3 position. */ - -/* NVM_FUSES.FUSEBYTE2 bit masks and bit positions */ -#define NVM_FUSES_BOOTRST_bm 0x40 /* Boot Loader Section Reset Vector bit mask. */ -#define NVM_FUSES_BOOTRST_bp 6 /* Boot Loader Section Reset Vector bit position. */ - -#define NVM_FUSES_TOSCSEL_bm 0x20 /* Timer Oscillator pin location bit mask. */ -#define NVM_FUSES_TOSCSEL_bp 5 /* Timer Oscillator pin location bit position. */ - -#define NVM_FUSES_BODPD_gm 0x03 /* BOD Operation in Power-Down Mode group mask. */ -#define NVM_FUSES_BODPD_gp 0 /* BOD Operation in Power-Down Mode group position. */ -#define NVM_FUSES_BODPD0_bm (1<<0) /* BOD Operation in Power-Down Mode bit 0 mask. */ -#define NVM_FUSES_BODPD0_bp 0 /* BOD Operation in Power-Down Mode bit 0 position. */ -#define NVM_FUSES_BODPD1_bm (1<<1) /* BOD Operation in Power-Down Mode bit 1 mask. */ -#define NVM_FUSES_BODPD1_bp 1 /* BOD Operation in Power-Down Mode bit 1 position. */ - -/* NVM_FUSES.FUSEBYTE4 bit masks and bit positions */ -#define NVM_FUSES_RSTDISBL_bm 0x10 /* External Reset Disable bit mask. */ -#define NVM_FUSES_RSTDISBL_bp 4 /* External Reset Disable bit position. */ - -#define NVM_FUSES_SUT_gm 0x0C /* Start-up Time group mask. */ -#define NVM_FUSES_SUT_gp 2 /* Start-up Time group position. */ -#define NVM_FUSES_SUT0_bm (1<<2) /* Start-up Time bit 0 mask. */ -#define NVM_FUSES_SUT0_bp 2 /* Start-up Time bit 0 position. */ -#define NVM_FUSES_SUT1_bm (1<<3) /* Start-up Time bit 1 mask. */ -#define NVM_FUSES_SUT1_bp 3 /* Start-up Time bit 1 position. */ - -#define NVM_FUSES_WDLOCK_bm 0x02 /* Watchdog Timer Lock bit mask. */ -#define NVM_FUSES_WDLOCK_bp 1 /* Watchdog Timer Lock bit position. */ - -/* NVM_FUSES.FUSEBYTE5 bit masks and bit positions */ -#define NVM_FUSES_BODACT_gm 0x30 /* BOD Operation in Active Mode group mask. */ -#define NVM_FUSES_BODACT_gp 4 /* BOD Operation in Active Mode group position. */ -#define NVM_FUSES_BODACT0_bm (1<<4) /* BOD Operation in Active Mode bit 0 mask. */ -#define NVM_FUSES_BODACT0_bp 4 /* BOD Operation in Active Mode bit 0 position. */ -#define NVM_FUSES_BODACT1_bm (1<<5) /* BOD Operation in Active Mode bit 1 mask. */ -#define NVM_FUSES_BODACT1_bp 5 /* BOD Operation in Active Mode bit 1 position. */ - -#define NVM_FUSES_EESAVE_bm 0x08 /* Preserve EEPROM Through Chip Erase bit mask. */ -#define NVM_FUSES_EESAVE_bp 3 /* Preserve EEPROM Through Chip Erase bit position. */ - -#define NVM_FUSES_BODLVL_gm 0x07 /* Brownout Detection Voltage Level group mask. */ -#define NVM_FUSES_BODLVL_gp 0 /* Brownout Detection Voltage Level group position. */ -#define NVM_FUSES_BODLVL0_bm (1<<0) /* Brownout Detection Voltage Level bit 0 mask. */ -#define NVM_FUSES_BODLVL0_bp 0 /* Brownout Detection Voltage Level bit 0 position. */ -#define NVM_FUSES_BODLVL1_bm (1<<1) /* Brownout Detection Voltage Level bit 1 mask. */ -#define NVM_FUSES_BODLVL1_bp 1 /* Brownout Detection Voltage Level bit 1 position. */ -#define NVM_FUSES_BODLVL2_bm (1<<2) /* Brownout Detection Voltage Level bit 2 mask. */ -#define NVM_FUSES_BODLVL2_bp 2 /* Brownout Detection Voltage Level bit 2 position. */ - -/* LOCKBIT - Fuses and Lockbits */ -/* NVM_LOCKBITS.LOCKBITS bit masks and bit positions */ -#define NVM_LOCKBITS_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ -#define NVM_LOCKBITS_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ -#define NVM_LOCKBITS_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ -#define NVM_LOCKBITS_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ -#define NVM_LOCKBITS_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ -#define NVM_LOCKBITS_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ - -#define NVM_LOCKBITS_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ -#define NVM_LOCKBITS_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ -#define NVM_LOCKBITS_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ -#define NVM_LOCKBITS_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ -#define NVM_LOCKBITS_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ -#define NVM_LOCKBITS_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ - -#define NVM_LOCKBITS_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ -#define NVM_LOCKBITS_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ -#define NVM_LOCKBITS_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ -#define NVM_LOCKBITS_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ -#define NVM_LOCKBITS_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ -#define NVM_LOCKBITS_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ - -#define NVM_LOCKBITS_LB_gm 0x03 /* Lock Bits group mask. */ -#define NVM_LOCKBITS_LB_gp 0 /* Lock Bits group position. */ -#define NVM_LOCKBITS_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ -#define NVM_LOCKBITS_LB0_bp 0 /* Lock Bits bit 0 position. */ -#define NVM_LOCKBITS_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ -#define NVM_LOCKBITS_LB1_bp 1 /* Lock Bits bit 1 position. */ - - - -// Generic Port Pins - -#define PIN0_bm 0x01 -#define PIN0_bp 0 -#define PIN1_bm 0x02 -#define PIN1_bp 1 -#define PIN2_bm 0x04 -#define PIN2_bp 2 -#define PIN3_bm 0x08 -#define PIN3_bp 3 -#define PIN4_bm 0x10 -#define PIN4_bp 4 -#define PIN5_bm 0x20 -#define PIN5_bp 5 -#define PIN6_bm 0x40 -#define PIN6_bp 6 -#define PIN7_bm 0x80 -#define PIN7_bp 7 - -/* ========== Interrupt Vector Definitions ========== */ -/* Vector 0 is the reset vector */ - -/* OSC interrupt vectors */ -#define OSC_OSCF_vect_num 1 -#define OSC_OSCF_vect _VECTOR(1) /* Oscillator Failure Interrupt (NMI) */ - -/* PORTC interrupt vectors */ -#define PORTC_INT0_vect_num 2 -#define PORTC_INT0_vect _VECTOR(2) /* External Interrupt 0 */ -#define PORTC_INT1_vect_num 3 -#define PORTC_INT1_vect _VECTOR(3) /* External Interrupt 1 */ - -/* PORTR interrupt vectors */ -#define PORTR_INT0_vect_num 4 -#define PORTR_INT0_vect _VECTOR(4) /* External Interrupt 0 */ -#define PORTR_INT1_vect_num 5 -#define PORTR_INT1_vect _VECTOR(5) /* External Interrupt 1 */ - -/* DMA interrupt vectors */ -#define DMA_CH0_vect_num 6 -#define DMA_CH0_vect _VECTOR(6) /* Channel 0 Interrupt */ -#define DMA_CH1_vect_num 7 -#define DMA_CH1_vect _VECTOR(7) /* Channel 1 Interrupt */ -#define DMA_CH2_vect_num 8 -#define DMA_CH2_vect _VECTOR(8) /* Channel 2 Interrupt */ -#define DMA_CH3_vect_num 9 -#define DMA_CH3_vect _VECTOR(9) /* Channel 3 Interrupt */ - -/* RTC interrupt vectors */ -#define RTC_OVF_vect_num 10 -#define RTC_OVF_vect _VECTOR(10) /* Overflow Interrupt */ -#define RTC_COMP_vect_num 11 -#define RTC_COMP_vect _VECTOR(11) /* Compare Interrupt */ - -/* TWIC interrupt vectors */ -#define TWIC_TWIS_vect_num 12 -#define TWIC_TWIS_vect _VECTOR(12) /* TWI Slave Interrupt */ -#define TWIC_TWIM_vect_num 13 -#define TWIC_TWIM_vect _VECTOR(13) /* TWI Master Interrupt */ - -/* TCC0 interrupt vectors */ -#define TCC0_OVF_vect_num 14 -#define TCC0_OVF_vect _VECTOR(14) /* Overflow Interrupt */ - -/* TCC2 interrupt vectors */ -#define TCC2_LUNF_vect_num 14 -#define TCC2_LUNF_vect _VECTOR(14) /* Low Byte Underflow Interrupt */ - -/* TCC0 interrupt vectors */ -#define TCC0_ERR_vect_num 15 -#define TCC0_ERR_vect _VECTOR(15) /* Error Interrupt */ - -/* TCC2 interrupt vectors */ -#define TCC2_HUNF_vect_num 15 -#define TCC2_HUNF_vect _VECTOR(15) /* High Byte Underflow Interrupt */ - -/* TCC0 interrupt vectors */ -#define TCC0_CCA_vect_num 16 -#define TCC0_CCA_vect _VECTOR(16) /* Compare or Capture A Interrupt */ - -/* TCC2 interrupt vectors */ -#define TCC2_LCMPA_vect_num 16 -#define TCC2_LCMPA_vect _VECTOR(16) /* Low Byte Compare A Interrupt */ - -/* TCC0 interrupt vectors */ -#define TCC0_CCB_vect_num 17 -#define TCC0_CCB_vect _VECTOR(17) /* Compare or Capture B Interrupt */ - -/* TCC2 interrupt vectors */ -#define TCC2_LCMPB_vect_num 17 -#define TCC2_LCMPB_vect _VECTOR(17) /* Low Byte Compare B Interrupt */ - -/* TCC0 interrupt vectors */ -#define TCC0_CCC_vect_num 18 -#define TCC0_CCC_vect _VECTOR(18) /* Compare or Capture C Interrupt */ - -/* TCC2 interrupt vectors */ -#define TCC2_LCMPC_vect_num 18 -#define TCC2_LCMPC_vect _VECTOR(18) /* Low Byte Compare C Interrupt */ - -/* TCC0 interrupt vectors */ -#define TCC0_CCD_vect_num 19 -#define TCC0_CCD_vect _VECTOR(19) /* Compare or Capture D Interrupt */ - -/* TCC2 interrupt vectors */ -#define TCC2_LCMPD_vect_num 19 -#define TCC2_LCMPD_vect _VECTOR(19) /* Low Byte Compare D Interrupt */ - -/* TCC1 interrupt vectors */ -#define TCC1_OVF_vect_num 20 -#define TCC1_OVF_vect _VECTOR(20) /* Overflow Interrupt */ -#define TCC1_ERR_vect_num 21 -#define TCC1_ERR_vect _VECTOR(21) /* Error Interrupt */ -#define TCC1_CCA_vect_num 22 -#define TCC1_CCA_vect _VECTOR(22) /* Compare or Capture A Interrupt */ -#define TCC1_CCB_vect_num 23 -#define TCC1_CCB_vect _VECTOR(23) /* Compare or Capture B Interrupt */ - -/* SPIC interrupt vectors */ -#define SPIC_INT_vect_num 24 -#define SPIC_INT_vect _VECTOR(24) /* SPI Interrupt */ - -/* USARTC0 interrupt vectors */ -#define USARTC0_RXC_vect_num 25 -#define USARTC0_RXC_vect _VECTOR(25) /* Reception Complete Interrupt */ -#define USARTC0_DRE_vect_num 26 -#define USARTC0_DRE_vect _VECTOR(26) /* Data Register Empty Interrupt */ -#define USARTC0_TXC_vect_num 27 -#define USARTC0_TXC_vect _VECTOR(27) /* Transmission Complete Interrupt */ - -/* USARTC1 interrupt vectors */ -#define USARTC1_RXC_vect_num 28 -#define USARTC1_RXC_vect _VECTOR(28) /* Reception Complete Interrupt */ -#define USARTC1_DRE_vect_num 29 -#define USARTC1_DRE_vect _VECTOR(29) /* Data Register Empty Interrupt */ -#define USARTC1_TXC_vect_num 30 -#define USARTC1_TXC_vect _VECTOR(30) /* Transmission Complete Interrupt */ - -/* AES interrupt vectors */ -#define AES_INT_vect_num 31 -#define AES_INT_vect _VECTOR(31) /* AES Interrupt */ - -/* NVM interrupt vectors */ -#define NVM_EE_vect_num 32 -#define NVM_EE_vect _VECTOR(32) /* EE Interrupt */ -#define NVM_SPM_vect_num 33 -#define NVM_SPM_vect _VECTOR(33) /* SPM Interrupt */ - -/* PORTB interrupt vectors */ -#define PORTB_INT0_vect_num 34 -#define PORTB_INT0_vect _VECTOR(34) /* External Interrupt 0 */ -#define PORTB_INT1_vect_num 35 -#define PORTB_INT1_vect _VECTOR(35) /* External Interrupt 1 */ - -/* PORTE interrupt vectors */ -#define PORTE_INT0_vect_num 43 -#define PORTE_INT0_vect _VECTOR(43) /* External Interrupt 0 */ -#define PORTE_INT1_vect_num 44 -#define PORTE_INT1_vect _VECTOR(44) /* External Interrupt 1 */ - -/* TWIE interrupt vectors */ -#define TWIE_TWIS_vect_num 45 -#define TWIE_TWIS_vect _VECTOR(45) /* TWI Slave Interrupt */ -#define TWIE_TWIM_vect_num 46 -#define TWIE_TWIM_vect _VECTOR(46) /* TWI Master Interrupt */ - -/* TCE0 interrupt vectors */ -#define TCE0_OVF_vect_num 47 -#define TCE0_OVF_vect _VECTOR(47) /* Overflow Interrupt */ -#define TCE0_ERR_vect_num 48 -#define TCE0_ERR_vect _VECTOR(48) /* Error Interrupt */ -#define TCE0_CCA_vect_num 49 -#define TCE0_CCA_vect _VECTOR(49) /* Compare or Capture A Interrupt */ -#define TCE0_CCB_vect_num 50 -#define TCE0_CCB_vect _VECTOR(50) /* Compare or Capture B Interrupt */ -#define TCE0_CCC_vect_num 51 -#define TCE0_CCC_vect _VECTOR(51) /* Compare or Capture C Interrupt */ -#define TCE0_CCD_vect_num 52 -#define TCE0_CCD_vect _VECTOR(52) /* Compare or Capture D Interrupt */ - -/* USARTE0 interrupt vectors */ -#define USARTE0_RXC_vect_num 58 -#define USARTE0_RXC_vect _VECTOR(58) /* Reception Complete Interrupt */ -#define USARTE0_DRE_vect_num 59 -#define USARTE0_DRE_vect _VECTOR(59) /* Data Register Empty Interrupt */ -#define USARTE0_TXC_vect_num 60 -#define USARTE0_TXC_vect _VECTOR(60) /* Transmission Complete Interrupt */ - -/* PORTD interrupt vectors */ -#define PORTD_INT0_vect_num 64 -#define PORTD_INT0_vect _VECTOR(64) /* External Interrupt 0 */ -#define PORTD_INT1_vect_num 65 -#define PORTD_INT1_vect _VECTOR(65) /* External Interrupt 1 */ - -/* PORTA interrupt vectors */ -#define PORTA_INT0_vect_num 66 -#define PORTA_INT0_vect _VECTOR(66) /* External Interrupt 0 */ -#define PORTA_INT1_vect_num 67 -#define PORTA_INT1_vect _VECTOR(67) /* External Interrupt 1 */ - -/* ACA interrupt vectors */ -#define ACA_AC0_vect_num 68 -#define ACA_AC0_vect _VECTOR(68) /* AC0 Interrupt */ -#define ACA_AC1_vect_num 69 -#define ACA_AC1_vect _VECTOR(69) /* AC1 Interrupt */ -#define ACA_ACW_vect_num 70 -#define ACA_ACW_vect _VECTOR(70) /* ACW Window Mode Interrupt */ - -/* ADCA interrupt vectors */ -#define ADCA_CH0_vect_num 71 -#define ADCA_CH0_vect _VECTOR(71) /* Interrupt 0 */ -#define ADCA_CH1_vect_num 72 -#define ADCA_CH1_vect _VECTOR(72) /* Interrupt 1 */ -#define ADCA_CH2_vect_num 73 -#define ADCA_CH2_vect _VECTOR(73) /* Interrupt 2 */ -#define ADCA_CH3_vect_num 74 -#define ADCA_CH3_vect _VECTOR(74) /* Interrupt 3 */ - -/* TCD0 interrupt vectors */ -#define TCD0_OVF_vect_num 77 -#define TCD0_OVF_vect _VECTOR(77) /* Overflow Interrupt */ - -/* TCD2 interrupt vectors */ -#define TCD2_LUNF_vect_num 77 -#define TCD2_LUNF_vect _VECTOR(77) /* Low Byte Underflow Interrupt */ - -/* TCD0 interrupt vectors */ -#define TCD0_ERR_vect_num 78 -#define TCD0_ERR_vect _VECTOR(78) /* Error Interrupt */ - -/* TCD2 interrupt vectors */ -#define TCD2_HUNF_vect_num 78 -#define TCD2_HUNF_vect _VECTOR(78) /* High Byte Underflow Interrupt */ - -/* TCD0 interrupt vectors */ -#define TCD0_CCA_vect_num 79 -#define TCD0_CCA_vect _VECTOR(79) /* Compare or Capture A Interrupt */ - -/* TCD2 interrupt vectors */ -#define TCD2_LCMPA_vect_num 79 -#define TCD2_LCMPA_vect _VECTOR(79) /* Low Byte Compare A Interrupt */ - -/* TCD0 interrupt vectors */ -#define TCD0_CCB_vect_num 80 -#define TCD0_CCB_vect _VECTOR(80) /* Compare or Capture B Interrupt */ - -/* TCD2 interrupt vectors */ -#define TCD2_LCMPB_vect_num 80 -#define TCD2_LCMPB_vect _VECTOR(80) /* Low Byte Compare B Interrupt */ - -/* TCD0 interrupt vectors */ -#define TCD0_CCC_vect_num 81 -#define TCD0_CCC_vect _VECTOR(81) /* Compare or Capture C Interrupt */ - -/* TCD2 interrupt vectors */ -#define TCD2_LCMPC_vect_num 81 -#define TCD2_LCMPC_vect _VECTOR(81) /* Low Byte Compare C Interrupt */ - -/* TCD0 interrupt vectors */ -#define TCD0_CCD_vect_num 82 -#define TCD0_CCD_vect _VECTOR(82) /* Compare or Capture D Interrupt */ - -/* TCD2 interrupt vectors */ -#define TCD2_LCMPD_vect_num 82 -#define TCD2_LCMPD_vect _VECTOR(82) /* Low Byte Compare D Interrupt */ - -/* TCD1 interrupt vectors */ -#define TCD1_OVF_vect_num 83 -#define TCD1_OVF_vect _VECTOR(83) /* Overflow Interrupt */ -#define TCD1_ERR_vect_num 84 -#define TCD1_ERR_vect _VECTOR(84) /* Error Interrupt */ -#define TCD1_CCA_vect_num 85 -#define TCD1_CCA_vect _VECTOR(85) /* Compare or Capture A Interrupt */ -#define TCD1_CCB_vect_num 86 -#define TCD1_CCB_vect _VECTOR(86) /* Compare or Capture B Interrupt */ - -/* SPID interrupt vectors */ -#define SPID_INT_vect_num 87 -#define SPID_INT_vect _VECTOR(87) /* SPI Interrupt */ - -/* USARTD0 interrupt vectors */ -#define USARTD0_RXC_vect_num 88 -#define USARTD0_RXC_vect _VECTOR(88) /* Reception Complete Interrupt */ -#define USARTD0_DRE_vect_num 89 -#define USARTD0_DRE_vect _VECTOR(89) /* Data Register Empty Interrupt */ -#define USARTD0_TXC_vect_num 90 -#define USARTD0_TXC_vect _VECTOR(90) /* Transmission Complete Interrupt */ - -/* USARTD1 interrupt vectors */ -#define USARTD1_RXC_vect_num 91 -#define USARTD1_RXC_vect _VECTOR(91) /* Reception Complete Interrupt */ -#define USARTD1_DRE_vect_num 92 -#define USARTD1_DRE_vect _VECTOR(92) /* Data Register Empty Interrupt */ -#define USARTD1_TXC_vect_num 93 -#define USARTD1_TXC_vect _VECTOR(93) /* Transmission Complete Interrupt */ - -/* USB interrupt vectors */ -#define USB_BUSEVENT_vect_num 125 -#define USB_BUSEVENT_vect _VECTOR(125) /* SOF, suspend, resume, reset bus event interrupts, crc, underflow, overflow and stall error interrupts */ -#define USB_TRNCOMPL_vect_num 126 -#define USB_TRNCOMPL_vect _VECTOR(126) /* Transaction complete interrupt */ - -#define _VECTOR_SIZE 4 /* Size of individual vector. */ -#define _VECTORS_SIZE (127 * _VECTOR_SIZE) - - -/* ========== Constants ========== */ - -#define PROGMEM_START (0x0000) -#define PROGMEM_SIZE (139264) -#define PROGMEM_END (PROGMEM_START + PROGMEM_SIZE - 1) - -#define APP_SECTION_START (0x0000) -#define APP_SECTION_SIZE (131072) -#define APP_SECTION_PAGE_SIZE (256) -#define APP_SECTION_END (APP_SECTION_START + APP_SECTION_SIZE - 1) - -#define APPTABLE_SECTION_START (0x1E000) -#define APPTABLE_SECTION_SIZE (8192) -#define APPTABLE_SECTION_PAGE_SIZE (256) -#define APPTABLE_SECTION_END (APPTABLE_SECTION_START + APPTABLE_SECTION_SIZE - 1) - -#define BOOT_SECTION_START (0x20000) -#define BOOT_SECTION_SIZE (8192) -#define BOOT_SECTION_PAGE_SIZE (256) -#define BOOT_SECTION_END (BOOT_SECTION_START + BOOT_SECTION_SIZE - 1) - -#define DATAMEM_START (0x0000) -#define DATAMEM_SIZE (16384) -#define DATAMEM_END (DATAMEM_START + DATAMEM_SIZE - 1) - -#define IO_START (0x0000) -#define IO_SIZE (4096) -#define IO_PAGE_SIZE (0) -#define IO_END (IO_START + IO_SIZE - 1) - -#define MAPPED_EEPROM_START (0x1000) -#define MAPPED_EEPROM_SIZE (2048) -#define MAPPED_EEPROM_PAGE_SIZE (0) -#define MAPPED_EEPROM_END (MAPPED_EEPROM_START + MAPPED_EEPROM_SIZE - 1) - -#define INTERNAL_SRAM_START (0x2000) -#define INTERNAL_SRAM_SIZE (8192) -#define INTERNAL_SRAM_PAGE_SIZE (0) -#define INTERNAL_SRAM_END (INTERNAL_SRAM_START + INTERNAL_SRAM_SIZE - 1) - -#define EEPROM_START (0x0000) -#define EEPROM_SIZE (2048) -#define EEPROM_PAGE_SIZE (32) -#define EEPROM_END (EEPROM_START + EEPROM_SIZE - 1) - -#define SIGNATURES_START (0x0000) -#define SIGNATURES_SIZE (3) -#define SIGNATURES_PAGE_SIZE (0) -#define SIGNATURES_END (SIGNATURES_START + SIGNATURES_SIZE - 1) - -#define FUSES_START (0x0000) -#define FUSES_SIZE (6) -#define FUSES_PAGE_SIZE (0) -#define FUSES_END (FUSES_START + FUSES_SIZE - 1) - -#define LOCKBITS_START (0x0000) -#define LOCKBITS_SIZE (1) -#define LOCKBITS_PAGE_SIZE (0) -#define LOCKBITS_END (LOCKBITS_START + LOCKBITS_SIZE - 1) - -#define USER_SIGNATURES_START (0x0000) -#define USER_SIGNATURES_SIZE (256) -#define USER_SIGNATURES_PAGE_SIZE (256) -#define USER_SIGNATURES_END (USER_SIGNATURES_START + USER_SIGNATURES_SIZE - 1) - -#define PROD_SIGNATURES_START (0x0000) -#define PROD_SIGNATURES_SIZE (64) -#define PROD_SIGNATURES_PAGE_SIZE (256) -#define PROD_SIGNATURES_END (PROD_SIGNATURES_START + PROD_SIGNATURES_SIZE - 1) - -#define FLASHSTART PROGMEM_START -#define FLASHEND PROGMEM_END -#define SPM_PAGESIZE 256 -#define RAMSTART INTERNAL_SRAM_START -#define RAMSIZE INTERNAL_SRAM_SIZE -#define RAMEND INTERNAL_SRAM_END -#define E2END EEPROM_END -#define E2PAGESIZE EEPROM_PAGE_SIZE - - -/* ========== Fuses ========== */ -#define FUSE_MEMORY_SIZE 6 - -/* Fuse Byte 0 Reserved */ - -/* Fuse Byte 1 */ -#define FUSE_WDP0 (unsigned char)~_BV(0) /* Watchdog Timeout Period Bit 0 */ -#define FUSE_WDP1 (unsigned char)~_BV(1) /* Watchdog Timeout Period Bit 1 */ -#define FUSE_WDP2 (unsigned char)~_BV(2) /* Watchdog Timeout Period Bit 2 */ -#define FUSE_WDP3 (unsigned char)~_BV(3) /* Watchdog Timeout Period Bit 3 */ -#define FUSE_WDWP0 (unsigned char)~_BV(4) /* Watchdog Window Timeout Period Bit 0 */ -#define FUSE_WDWP1 (unsigned char)~_BV(5) /* Watchdog Window Timeout Period Bit 1 */ -#define FUSE_WDWP2 (unsigned char)~_BV(6) /* Watchdog Window Timeout Period Bit 2 */ -#define FUSE_WDWP3 (unsigned char)~_BV(7) /* Watchdog Window Timeout Period Bit 3 */ -#define FUSE1_DEFAULT (0xFF) - -/* Fuse Byte 2 */ -#define FUSE_BODPD0 (unsigned char)~_BV(0) /* BOD Operation in Power-Down Mode Bit 0 */ -#define FUSE_BODPD1 (unsigned char)~_BV(1) /* BOD Operation in Power-Down Mode Bit 1 */ -#define FUSE_TOSCSEL (unsigned char)~_BV(5) /* Timer Oscillator pin location */ -#define FUSE_BOOTRST (unsigned char)~_BV(6) /* Boot Loader Section Reset Vector */ -#define FUSE2_DEFAULT (0xFF) - -/* Fuse Byte 3 Reserved */ - -/* Fuse Byte 4 */ -#define FUSE_WDLOCK (unsigned char)~_BV(1) /* Watchdog Timer Lock */ -#define FUSE_SUT0 (unsigned char)~_BV(2) /* Start-up Time Bit 0 */ -#define FUSE_SUT1 (unsigned char)~_BV(3) /* Start-up Time Bit 1 */ -#define FUSE_RSTDISBL (unsigned char)~_BV(4) /* External Reset Disable */ -#define FUSE4_DEFAULT (0xFF) - -/* Fuse Byte 5 */ -#define FUSE_BODLVL0 (unsigned char)~_BV(0) /* Brownout Detection Voltage Level Bit 0 */ -#define FUSE_BODLVL1 (unsigned char)~_BV(1) /* Brownout Detection Voltage Level Bit 1 */ -#define FUSE_BODLVL2 (unsigned char)~_BV(2) /* Brownout Detection Voltage Level Bit 2 */ -#define FUSE_EESAVE (unsigned char)~_BV(3) /* Preserve EEPROM Through Chip Erase */ -#define FUSE_BODACT0 (unsigned char)~_BV(4) /* BOD Operation in Active Mode Bit 0 */ -#define FUSE_BODACT1 (unsigned char)~_BV(5) /* BOD Operation in Active Mode Bit 1 */ -#define FUSE5_DEFAULT (0xFF) - -/* ========== Lock Bits ========== */ -#define __LOCK_BITS_EXIST -#define __BOOT_LOCK_APPLICATION_TABLE_BITS_EXIST -#define __BOOT_LOCK_APPLICATION_BITS_EXIST -#define __BOOT_LOCK_BOOT_BITS_EXIST - -/* ========== Signature ========== */ -#define SIGNATURE_0 0x1E -#define SIGNATURE_1 0x97 -#define SIGNATURE_2 0x46 - -/* ========== Power Reduction Condition Definitions ========== */ - -/* PR.PRGEN */ -#define __AVR_HAVE_PRGEN (PR_USB_bm|PR_AES_bm|PR_EBI_bm|PR_RTC_bm|PR_EVSYS_bm|PR_DMA_bm) -#define __AVR_HAVE_PRGEN_USB -#define __AVR_HAVE_PRGEN_AES -#define __AVR_HAVE_PRGEN_EBI -#define __AVR_HAVE_PRGEN_RTC -#define __AVR_HAVE_PRGEN_EVSYS -#define __AVR_HAVE_PRGEN_DMA - -/* PR.PRPA */ -#define __AVR_HAVE_PRPA (PR_DAC_bm|PR_ADC_bm|PR_AC_bm) -#define __AVR_HAVE_PRPA_DAC -#define __AVR_HAVE_PRPA_ADC -#define __AVR_HAVE_PRPA_AC - -/* PR.PRPB */ -#define __AVR_HAVE_PRPB (PR_DAC_bm|PR_ADC_bm|PR_AC_bm) -#define __AVR_HAVE_PRPB_DAC -#define __AVR_HAVE_PRPB_ADC -#define __AVR_HAVE_PRPB_AC - -/* PR.PRPC */ -#define __AVR_HAVE_PRPC (PR_TWI_bm|PR_USART1_bm|PR_USART0_bm|PR_SPI_bm|PR_HIRES_bm|PR_TC1_bm|PR_TC0_bm) -#define __AVR_HAVE_PRPC_TWI -#define __AVR_HAVE_PRPC_USART1 -#define __AVR_HAVE_PRPC_USART0 -#define __AVR_HAVE_PRPC_SPI -#define __AVR_HAVE_PRPC_HIRES -#define __AVR_HAVE_PRPC_TC1 -#define __AVR_HAVE_PRPC_TC0 - -/* PR.PRPD */ -#define __AVR_HAVE_PRPD (PR_TWI_bm|PR_USART1_bm|PR_USART0_bm|PR_SPI_bm|PR_HIRES_bm|PR_TC1_bm|PR_TC0_bm) -#define __AVR_HAVE_PRPD_TWI -#define __AVR_HAVE_PRPD_USART1 -#define __AVR_HAVE_PRPD_USART0 -#define __AVR_HAVE_PRPD_SPI -#define __AVR_HAVE_PRPD_HIRES -#define __AVR_HAVE_PRPD_TC1 -#define __AVR_HAVE_PRPD_TC0 - -/* PR.PRPE */ -#define __AVR_HAVE_PRPE (PR_TWI_bm|PR_USART1_bm|PR_USART0_bm|PR_SPI_bm|PR_HIRES_bm|PR_TC1_bm|PR_TC0_bm) -#define __AVR_HAVE_PRPE_TWI -#define __AVR_HAVE_PRPE_USART1 -#define __AVR_HAVE_PRPE_USART0 -#define __AVR_HAVE_PRPE_SPI -#define __AVR_HAVE_PRPE_HIRES -#define __AVR_HAVE_PRPE_TC1 -#define __AVR_HAVE_PRPE_TC0 - -/* PR.PRPF */ -#define __AVR_HAVE_PRPF (PR_TWI_bm|PR_USART1_bm|PR_USART0_bm|PR_SPI_bm|PR_HIRES_bm|PR_TC1_bm|PR_TC0_bm) -#define __AVR_HAVE_PRPF_TWI -#define __AVR_HAVE_PRPF_USART1 -#define __AVR_HAVE_PRPF_USART0 -#define __AVR_HAVE_PRPF_SPI -#define __AVR_HAVE_PRPF_HIRES -#define __AVR_HAVE_PRPF_TC1 -#define __AVR_HAVE_PRPF_TC0 - - -#endif /* #ifdef _AVR_ATXMEGA128A4U_H_INCLUDED */ - diff --git a/arduino/hardware/tools/avr/avr/include/avr/iox128b1.h b/arduino/hardware/tools/avr/avr/include/avr/iox128b1.h deleted file mode 100644 index f3f41f4..0000000 --- a/arduino/hardware/tools/avr/avr/include/avr/iox128b1.h +++ /dev/null @@ -1,6872 +0,0 @@ -/***************************************************************************** - * - * Copyright (C) 2015 Atmel Corporation - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * - * * Neither the name of the copyright holders nor the names of - * contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - ****************************************************************************/ - - -#ifndef _AVR_IO_H_ -# error "Include instead of this file." -#endif - -#ifndef _AVR_IOXXX_H_ -# define _AVR_IOXXX_H_ "iox128b1.h" -#else -# error "Attempt to include more than one file." -#endif - -#ifndef _AVR_ATXMEGA128B1_H_INCLUDED -#define _AVR_ATXMEGA128B1_H_INCLUDED - -/* Ungrouped common registers */ -#define GPIOR0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ -#define GPIOR1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ -#define GPIOR2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ -#define GPIOR3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ - -/* Deprecated */ -#define GPIO0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ -#define GPIO1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ -#define GPIO2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ -#define GPIO3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ - -#define CCP _SFR_MEM8(0x0034) /* Configuration Change Protection */ -#define RAMPD _SFR_MEM8(0x0038) /* Ramp D */ -#define RAMPX _SFR_MEM8(0x0039) /* Ramp X */ -#define RAMPY _SFR_MEM8(0x003A) /* Ramp Y */ -#define RAMPZ _SFR_MEM8(0x003B) /* Ramp Z */ -#define EIND _SFR_MEM8(0x003C) /* Extended Indirect Jump */ -#define SPL _SFR_MEM8(0x003D) /* Stack Pointer Low */ -#define SPH _SFR_MEM8(0x003E) /* Stack Pointer High */ -#define SREG _SFR_MEM8(0x003F) /* Status Register */ - -/* C Language Only */ -#if !defined (__ASSEMBLER__) - -#include - -typedef volatile uint8_t register8_t; -typedef volatile uint16_t register16_t; -typedef volatile uint32_t register32_t; - - -#ifdef _WORDREGISTER -#undef _WORDREGISTER -#endif -#define _WORDREGISTER(regname) \ - __extension__ union \ - { \ - register16_t regname; \ - struct \ - { \ - register8_t regname ## L; \ - register8_t regname ## H; \ - }; \ - } - -#ifdef _DWORDREGISTER -#undef _DWORDREGISTER -#endif -#define _DWORDREGISTER(regname) \ - __extension__ union \ - { \ - register32_t regname; \ - struct \ - { \ - register8_t regname ## 0; \ - register8_t regname ## 1; \ - register8_t regname ## 2; \ - register8_t regname ## 3; \ - }; \ - } - - -/* -========================================================================== -IO Module Structures -========================================================================== -*/ - - -/* --------------------------------------------------------------------------- -VPORT - Virtual Ports --------------------------------------------------------------------------- -*/ - -/* Virtual Port */ -typedef struct VPORT_struct -{ - register8_t DIR; /* I/O Port Data Direction */ - register8_t OUT; /* I/O Port Output */ - register8_t IN; /* I/O Port Input */ - register8_t INTFLAGS; /* Interrupt Flag Register */ -} VPORT_t; - - -/* --------------------------------------------------------------------------- -XOCD - On-Chip Debug System --------------------------------------------------------------------------- -*/ - -/* On-Chip Debug System */ -typedef struct OCD_struct -{ - register8_t OCDR0; /* OCD Register 0 */ - register8_t OCDR1; /* OCD Register 1 */ -} OCD_t; - - -/* --------------------------------------------------------------------------- -CPU - CPU --------------------------------------------------------------------------- -*/ - -/* CCP signatures */ -typedef enum CCP_enum -{ - CCP_SPM_gc = (0x9D<<0), /* SPM Instruction Protection */ - CCP_IOREG_gc = (0xD8<<0), /* IO Register Protection */ -} CCP_t; - - -/* --------------------------------------------------------------------------- -CLK - Clock System --------------------------------------------------------------------------- -*/ - -/* Clock System */ -typedef struct CLK_struct -{ - register8_t CTRL; /* Control Register */ - register8_t PSCTRL; /* Prescaler Control Register */ - register8_t LOCK; /* Lock register */ - register8_t RTCCTRL; /* RTC Control Register */ - register8_t USBCTRL; /* USB Control Register */ -} CLK_t; - -/* System Clock Selection */ -typedef enum CLK_SCLKSEL_enum -{ - CLK_SCLKSEL_RC2M_gc = (0x00<<0), /* Internal 2 MHz RC Oscillator */ - CLK_SCLKSEL_RC32M_gc = (0x01<<0), /* Internal 32 MHz RC Oscillator */ - CLK_SCLKSEL_RC32K_gc = (0x02<<0), /* Internal 32.768 kHz RC Oscillator */ - CLK_SCLKSEL_XOSC_gc = (0x03<<0), /* External Crystal Oscillator or Clock */ - CLK_SCLKSEL_PLL_gc = (0x04<<0), /* Phase Locked Loop */ -} CLK_SCLKSEL_t; - -/* Prescaler A Division Factor */ -typedef enum CLK_PSADIV_enum -{ - CLK_PSADIV_1_gc = (0x00<<2), /* Divide by 1 */ - CLK_PSADIV_2_gc = (0x01<<2), /* Divide by 2 */ - CLK_PSADIV_4_gc = (0x03<<2), /* Divide by 4 */ - CLK_PSADIV_8_gc = (0x05<<2), /* Divide by 8 */ - CLK_PSADIV_16_gc = (0x07<<2), /* Divide by 16 */ - CLK_PSADIV_32_gc = (0x09<<2), /* Divide by 32 */ - CLK_PSADIV_64_gc = (0x0B<<2), /* Divide by 64 */ - CLK_PSADIV_128_gc = (0x0D<<2), /* Divide by 128 */ - CLK_PSADIV_256_gc = (0x0F<<2), /* Divide by 256 */ - CLK_PSADIV_512_gc = (0x11<<2), /* Divide by 512 */ -} CLK_PSADIV_t; - -/* Prescaler B and C Division Factor */ -typedef enum CLK_PSBCDIV_enum -{ - CLK_PSBCDIV_1_1_gc = (0x00<<0), /* Divide B by 1 and C by 1 */ - CLK_PSBCDIV_1_2_gc = (0x01<<0), /* Divide B by 1 and C by 2 */ - CLK_PSBCDIV_4_1_gc = (0x02<<0), /* Divide B by 4 and C by 1 */ - CLK_PSBCDIV_2_2_gc = (0x03<<0), /* Divide B by 2 and C by 2 */ -} CLK_PSBCDIV_t; - -/* RTC Clock Source */ -typedef enum CLK_RTCSRC_enum -{ - CLK_RTCSRC_ULP_gc = (0x00<<1), /* 1.024 kHz from internal 32kHz ULP */ - CLK_RTCSRC_TOSC_gc = (0x01<<1), /* 1.024 kHz from 32.768 kHz crystal oscillator on TOSC */ - CLK_RTCSRC_RCOSC_gc = (0x02<<1), /* 1.024 kHz from internal 32.768 kHz RC oscillator */ - CLK_RTCSRC_TOSC32_gc = (0x05<<1), /* 32.768 kHz from 32.768 kHz crystal oscillator on TOSC */ - CLK_RTCSRC_RCOSC32_gc = (0x06<<1), /* 32.768 kHz from internal 32.768 kHz RC oscillator */ - CLK_RTCSRC_EXTCLK_gc = (0x07<<1), /* External Clock from TOSC1 */ -} CLK_RTCSRC_t; - -/* USB Prescaler Division Factor */ -typedef enum CLK_USBPSDIV_enum -{ - CLK_USBPSDIV_1_gc = (0x00<<3), /* Divide by 1 */ - CLK_USBPSDIV_2_gc = (0x01<<3), /* Divide by 2 */ - CLK_USBPSDIV_4_gc = (0x02<<3), /* Divide by 4 */ - CLK_USBPSDIV_8_gc = (0x03<<3), /* Divide by 8 */ - CLK_USBPSDIV_16_gc = (0x04<<3), /* Divide by 16 */ - CLK_USBPSDIV_32_gc = (0x05<<3), /* Divide by 32 */ -} CLK_USBPSDIV_t; - -/* USB Clock Source */ -typedef enum CLK_USBSRC_enum -{ - CLK_USBSRC_PLL_gc = (0x00<<1), /* PLL */ - CLK_USBSRC_RC32M_gc = (0x01<<1), /* Internal 32 MHz RC Oscillator */ -} CLK_USBSRC_t; - - -/* --------------------------------------------------------------------------- -SLEEP - Sleep Controller --------------------------------------------------------------------------- -*/ - -/* Sleep Controller */ -typedef struct SLEEP_struct -{ - register8_t CTRL; /* Control Register */ -} SLEEP_t; - -/* Sleep Mode */ -typedef enum SLEEP_SMODE_enum -{ - SLEEP_SMODE_IDLE_gc = (0x00<<1), /* Idle mode */ - SLEEP_SMODE_PDOWN_gc = (0x02<<1), /* Power-down Mode */ - SLEEP_SMODE_PSAVE_gc = (0x03<<1), /* Power-save Mode */ - SLEEP_SMODE_STDBY_gc = (0x06<<1), /* Standby Mode */ - SLEEP_SMODE_ESTDBY_gc = (0x07<<1), /* Extended Standby Mode */ -} SLEEP_SMODE_t; - - - -#define SLEEP_MODE_IDLE (0x00<<1) -#define SLEEP_MODE_PWR_DOWN (0x02<<1) -#define SLEEP_MODE_PWR_SAVE (0x03<<1) -#define SLEEP_MODE_STANDBY (0x06<<1) -#define SLEEP_MODE_EXT_STANDBY (0x07<<1) -/* --------------------------------------------------------------------------- -OSC - Oscillator --------------------------------------------------------------------------- -*/ - -/* Oscillator */ -typedef struct OSC_struct -{ - register8_t CTRL; /* Control Register */ - register8_t STATUS; /* Status Register */ - register8_t XOSCCTRL; /* External Oscillator Control Register */ - register8_t XOSCFAIL; /* Oscillator Failure Detection Register */ - register8_t RC32KCAL; /* 32.768 kHz Internal Oscillator Calibration Register */ - register8_t PLLCTRL; /* PLL Control Register */ - register8_t DFLLCTRL; /* DFLL Control Register */ -} OSC_t; - -/* Oscillator Frequency Range */ -typedef enum OSC_FRQRANGE_enum -{ - OSC_FRQRANGE_04TO2_gc = (0x00<<6), /* 0.4 - 2 MHz */ - OSC_FRQRANGE_2TO9_gc = (0x01<<6), /* 2 - 9 MHz */ - OSC_FRQRANGE_9TO12_gc = (0x02<<6), /* 9 - 12 MHz */ - OSC_FRQRANGE_12TO16_gc = (0x03<<6), /* 12 - 16 MHz */ -} OSC_FRQRANGE_t; - -/* External Oscillator Selection and Startup Time */ -typedef enum OSC_XOSCSEL_enum -{ - OSC_XOSCSEL_EXTCLK_gc = (0x00<<0), /* External Clock on port R1 - 6 CLK */ - OSC_XOSCSEL_EXTCLK_C0_gc = (0x01<<0), /* External Clock on port C0 - 6 CLK */ - OSC_XOSCSEL_EXTCLK_C1_gc = (0x05<<0), /* External Clock on port C1 - 6 CLK */ - OSC_XOSCSEL_EXTCLK_C2_gc = (0x09<<0), /* External Clock on port C2 - 6 CLK */ - OSC_XOSCSEL_EXTCLK_C3_gc = (0x0D<<0), /* External Clock on port C3 - 6 CLK */ - OSC_XOSCSEL_EXTCLK_C4_gc = (0x11<<0), /* External Clock on port C4 - 6 CLK */ - OSC_XOSCSEL_EXTCLK_C5_gc = (0x15<<0), /* External Clock on port C5 - 6 CLK */ - OSC_XOSCSEL_EXTCLK_C6_gc = (0x19<<0), /* External Clock on port C6 - 6 CLK */ - OSC_XOSCSEL_EXTCLK_C7_gc = (0x1D<<0), /* External Clock on port C7 - 6 CLK */ - OSC_XOSCSEL_32KHz_gc = (0x02<<0), /* 32kHz TOSC - 32K CLK */ - OSC_XOSCSEL_XTAL_256CLK_gc = (0x03<<0), /* 0.4-16MHz XTAL - 256 CLK */ - OSC_XOSCSEL_XTAL_1KCLK_gc = (0x07<<0), /* 0.4-16MHz XTAL - 1K CLK */ - OSC_XOSCSEL_XTAL_16KCLK_gc = (0x0B<<0), /* 0.4-16MHz XTAL - 16K CLK */ -} OSC_XOSCSEL_t; - -/* PLL Clock Source */ -typedef enum OSC_PLLSRC_enum -{ - OSC_PLLSRC_RC2M_gc = (0x00<<6), /* Internal 2 MHz RC Oscillator */ - OSC_PLLSRC_RC32M_gc = (0x02<<6), /* Internal 32 MHz RC Oscillator */ - OSC_PLLSRC_XOSC_gc = (0x03<<6), /* External Oscillator */ -} OSC_PLLSRC_t; - -/* 2 MHz DFLL Calibration Reference */ -typedef enum OSC_RC2MCREF_enum -{ - OSC_RC2MCREF_RC32K_gc = (0x00<<0), /* Internal 32.768 kHz RC Oscillator */ - OSC_RC2MCREF_XOSC32K_gc = (0x01<<0), /* External 32.768 kHz Crystal Oscillator */ -} OSC_RC2MCREF_t; - -/* 32 MHz DFLL Calibration Reference */ -typedef enum OSC_RC32MCREF_enum -{ - OSC_RC32MCREF_RC32K_gc = (0x00<<1), /* Internal 32.768 kHz RC Oscillator */ - OSC_RC32MCREF_XOSC32K_gc = (0x01<<1), /* External 32.768 kHz Crystal Oscillator */ - OSC_RC32MCREF_USBSOF_gc = (0x02<<1), /* USB Start of Frame */ -} OSC_RC32MCREF_t; - - -/* --------------------------------------------------------------------------- -DFLL - DFLL --------------------------------------------------------------------------- -*/ - -/* DFLL */ -typedef struct DFLL_struct -{ - register8_t CTRL; /* Control Register */ - register8_t reserved_0x01; - register8_t CALA; /* Calibration Register A */ - register8_t CALB; /* Calibration Register B */ - register8_t COMP0; /* Oscillator Compare Register 0 */ - register8_t COMP1; /* Oscillator Compare Register 1 */ - register8_t COMP2; /* Oscillator Compare Register 2 */ - register8_t reserved_0x07; -} DFLL_t; - - -/* --------------------------------------------------------------------------- -PR - Power Reduction --------------------------------------------------------------------------- -*/ - -/* Power Reduction */ -typedef struct PR_struct -{ - register8_t PRGEN; /* General Power Reduction */ - register8_t PRPA; /* Power Reduction Port A */ - register8_t PRPB; /* Power Reduction Port B */ - register8_t PRPC; /* Power Reduction Port C */ - register8_t reserved_0x04; - register8_t PRPE; /* Power Reduction Port E */ -} PR_t; - - -/* --------------------------------------------------------------------------- -RST - Reset --------------------------------------------------------------------------- -*/ - -/* Reset */ -typedef struct RST_struct -{ - register8_t STATUS; /* Status Register */ - register8_t CTRL; /* Control Register */ -} RST_t; - - -/* --------------------------------------------------------------------------- -WDT - Watch-Dog Timer --------------------------------------------------------------------------- -*/ - -/* Watch-Dog Timer */ -typedef struct WDT_struct -{ - register8_t CTRL; /* Control */ - register8_t WINCTRL; /* Windowed Mode Control */ - register8_t STATUS; /* Status */ -} WDT_t; - -/* Period setting */ -typedef enum WDT_PER_enum -{ - WDT_PER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ - WDT_PER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ - WDT_PER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ - WDT_PER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ - WDT_PER_128CLK_gc = (0x04<<2), /* 128 cycles (0.128s @ 3.3V) */ - WDT_PER_256CLK_gc = (0x05<<2), /* 256 cycles (0.256s @ 3.3V) */ - WDT_PER_512CLK_gc = (0x06<<2), /* 512 cycles (0.512s @ 3.3V) */ - WDT_PER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ - WDT_PER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ - WDT_PER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ - WDT_PER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ -} WDT_PER_t; - -/* Closed window period */ -typedef enum WDT_WPER_enum -{ - WDT_WPER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ - WDT_WPER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ - WDT_WPER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ - WDT_WPER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ - WDT_WPER_128CLK_gc = (0x04<<2), /* 128 cycles (0.128s @ 3.3V) */ - WDT_WPER_256CLK_gc = (0x05<<2), /* 256 cycles (0.256s @ 3.3V) */ - WDT_WPER_512CLK_gc = (0x06<<2), /* 512 cycles (0.512s @ 3.3V) */ - WDT_WPER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ - WDT_WPER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ - WDT_WPER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ - WDT_WPER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ -} WDT_WPER_t; - - -/* --------------------------------------------------------------------------- -MCU - MCU Control --------------------------------------------------------------------------- -*/ - -/* MCU Control */ -typedef struct MCU_struct -{ - register8_t DEVID0; /* Device ID byte 0 */ - register8_t DEVID1; /* Device ID byte 1 */ - register8_t DEVID2; /* Device ID byte 2 */ - register8_t REVID; /* Revision ID */ - register8_t JTAGUID; /* JTAG User ID */ - register8_t reserved_0x05; - register8_t MCUCR; /* MCU Control */ - register8_t ANAINIT; /* Analog Startup Delay */ - register8_t EVSYSLOCK; /* Event System Lock */ - register8_t AWEXLOCK; /* AWEX Lock */ - register8_t reserved_0x0A; - register8_t reserved_0x0B; -} MCU_t; - - -/* --------------------------------------------------------------------------- -PMIC - Programmable Multi-level Interrupt Controller --------------------------------------------------------------------------- -*/ - -/* Programmable Multi-level Interrupt Controller */ -typedef struct PMIC_struct -{ - register8_t STATUS; /* Status Register */ - register8_t INTPRI; /* Interrupt Priority */ - register8_t CTRL; /* Control Register */ - register8_t reserved_0x03; - register8_t reserved_0x04; - register8_t reserved_0x05; - register8_t reserved_0x06; - register8_t reserved_0x07; - register8_t reserved_0x08; - register8_t reserved_0x09; - register8_t reserved_0x0A; - register8_t reserved_0x0B; - register8_t reserved_0x0C; - register8_t reserved_0x0D; - register8_t reserved_0x0E; - register8_t reserved_0x0F; -} PMIC_t; - - -/* --------------------------------------------------------------------------- -PORTCFG - Port Configuration --------------------------------------------------------------------------- -*/ - -/* I/O port Configuration */ -typedef struct PORTCFG_struct -{ - register8_t MPCMASK; /* Multi-pin Configuration Mask */ - register8_t reserved_0x01; - register8_t VPCTRLA; /* Virtual Port Control Register A */ - register8_t VPCTRLB; /* Virtual Port Control Register B */ - register8_t CLKEVOUT; /* Clock and Event Out Register */ - register8_t reserved_0x05; - register8_t EVOUTSEL; /* Event Output Select */ -} PORTCFG_t; - -/* Virtual Port Mapping */ -typedef enum PORTCFG_VP02MAP_enum -{ - PORTCFG_VP02MAP_PORTA_gc = (0x00<<0), /* Mapped To PORTA */ - PORTCFG_VP02MAP_PORTB_gc = (0x01<<0), /* Mapped To PORTB */ - PORTCFG_VP02MAP_PORTC_gc = (0x02<<0), /* Mapped To PORTC */ - PORTCFG_VP02MAP_PORTD_gc = (0x03<<0), /* Mapped To PORTD */ - PORTCFG_VP02MAP_PORTE_gc = (0x04<<0), /* Mapped To PORTE */ - PORTCFG_VP02MAP_PORTG_gc = (0x06<<0), /* Mapped To PORTG */ - PORTCFG_VP02MAP_PORTM_gc = (0x0B<<0), /* Mapped To PORTM */ - PORTCFG_VP02MAP_PORTR_gc = (0x0F<<0), /* Mapped To PORTR */ -} PORTCFG_VP02MAP_t; - -/* Virtual Port Mapping */ -typedef enum PORTCFG_VP13MAP_enum -{ - PORTCFG_VP13MAP_PORTA_gc = (0x00<<4), /* Mapped To PORTA */ - PORTCFG_VP13MAP_PORTB_gc = (0x01<<4), /* Mapped To PORTB */ - PORTCFG_VP13MAP_PORTC_gc = (0x02<<4), /* Mapped To PORTC */ - PORTCFG_VP13MAP_PORTD_gc = (0x03<<4), /* Mapped To PORTD */ - PORTCFG_VP13MAP_PORTE_gc = (0x04<<4), /* Mapped To PORTE */ - PORTCFG_VP13MAP_PORTG_gc = (0x06<<4), /* Mapped To PORTG */ - PORTCFG_VP13MAP_PORTM_gc = (0x0B<<4), /* Mapped To PORTM */ - PORTCFG_VP13MAP_PORTR_gc = (0x0F<<4), /* Mapped To PORTR */ -} PORTCFG_VP13MAP_t; - -/* System Clock Output Port */ -typedef enum PORTCFG_CLKOUT_enum -{ - PORTCFG_CLKOUT_OFF_gc = (0x00<<0), /* System Clock Output Disabled */ - PORTCFG_CLKOUT_PC_gc = (0x01<<0), /* System Clock Output on Port C */ - PORTCFG_CLKOUT_PE_gc = (0x03<<0), /* System Clock Output on Port E */ -} PORTCFG_CLKOUT_t; - -/* Peripheral Clock Output Select */ -typedef enum PORTCFG_CLKOUTSEL_enum -{ - PORTCFG_CLKOUTSEL_CLK1X_gc = (0x00<<2), /* 1x Peripheral Clock Output to pin */ - PORTCFG_CLKOUTSEL_CLK2X_gc = (0x01<<2), /* 2x Peripheral Clock Output to pin */ - PORTCFG_CLKOUTSEL_CLK4X_gc = (0x02<<2), /* 4x Peripheral Clock Output to pin */ -} PORTCFG_CLKOUTSEL_t; - -/* Event Output Port */ -typedef enum PORTCFG_EVOUT_enum -{ - PORTCFG_EVOUT_OFF_gc = (0x00<<4), /* Event Output Disabled */ - PORTCFG_EVOUT_PC_gc = (0x01<<4), /* Event Channel 0 Output on Port C */ - PORTCFG_EVOUT_PE_gc = (0x03<<4), /* Event Channel 0 Output on Port E */ -} PORTCFG_EVOUT_t; - -/* Clock and Event Output Port */ -typedef enum PORTCFG_CLKEVPIN_enum -{ - PORTCFG_CLKEVPIN_PIN7_gc = (0x00<<7), /* Clock and Event Ouput on PIN 7 */ - PORTCFG_CLKEVPIN_PIN4_gc = (0x01<<7), /* Clock and Event Ouput on PIN 4 */ -} PORTCFG_CLKEVPIN_t; - -/* Event Output Select */ -typedef enum PORTCFG_EVOUTSEL_enum -{ - PORTCFG_EVOUTSEL_0_gc = (0x00<<2), /* Event Channel 0 output to pin */ - PORTCFG_EVOUTSEL_1_gc = (0x01<<2), /* Event Channel 1 output to pin */ - PORTCFG_EVOUTSEL_2_gc = (0x02<<2), /* Event Channel 2 output to pin */ - PORTCFG_EVOUTSEL_3_gc = (0x03<<2), /* Event Channel 3 output to pin */ -} PORTCFG_EVOUTSEL_t; - - -/* --------------------------------------------------------------------------- -AES - AES Module --------------------------------------------------------------------------- -*/ - -/* AES Module */ -typedef struct AES_struct -{ - register8_t CTRL; /* AES Control Register */ - register8_t STATUS; /* AES Status Register */ - register8_t STATE; /* AES State Register */ - register8_t KEY; /* AES Key Register */ - register8_t INTCTRL; /* AES Interrupt Control Register */ -} AES_t; - -/* Interrupt level */ -typedef enum AES_INTLVL_enum -{ - AES_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - AES_INTLVL_LO_gc = (0x01<<0), /* Low Level */ - AES_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ - AES_INTLVL_HI_gc = (0x03<<0), /* High Level */ -} AES_INTLVL_t; - - -/* --------------------------------------------------------------------------- -CRC - Cyclic Redundancy Checker --------------------------------------------------------------------------- -*/ - -/* Cyclic Redundancy Checker */ -typedef struct CRC_struct -{ - register8_t CTRL; /* Control Register */ - register8_t STATUS; /* Status Register */ - register8_t reserved_0x02; - register8_t DATAIN; /* Data Input */ - register8_t CHECKSUM0; /* Checksum byte 0 */ - register8_t CHECKSUM1; /* Checksum byte 1 */ - register8_t CHECKSUM2; /* Checksum byte 2 */ - register8_t CHECKSUM3; /* Checksum byte 3 */ -} CRC_t; - -/* Reset */ -typedef enum CRC_RESET_enum -{ - CRC_RESET_NO_gc = (0x00<<6), /* No Reset */ - CRC_RESET_RESET0_gc = (0x02<<6), /* Reset CRC with CHECKSUM to all zeros */ - CRC_RESET_RESET1_gc = (0x03<<6), /* Reset CRC with CHECKSUM to all ones */ -} CRC_RESET_t; - -/* Input Source */ -typedef enum CRC_SOURCE_enum -{ - CRC_SOURCE_DISABLE_gc = (0x00<<0), /* Disabled */ - CRC_SOURCE_IO_gc = (0x01<<0), /* I/O Interface */ - CRC_SOURCE_FLASH_gc = (0x02<<0), /* Flash */ - CRC_SOURCE_DMAC0_gc = (0x04<<0), /* DMAC Channel 0 */ - CRC_SOURCE_DMAC1_gc = (0x05<<0), /* DMAC Channel 1 */ -} CRC_SOURCE_t; - - -/* --------------------------------------------------------------------------- -DMA - DMA Controller --------------------------------------------------------------------------- -*/ - -/* DMA Channel */ -typedef struct DMA_CH_struct -{ - register8_t CTRLA; /* Channel Control */ - register8_t CTRLB; /* Channel Control */ - register8_t ADDRCTRL; /* Address Control */ - register8_t TRIGSRC; /* Channel Trigger Source */ - _WORDREGISTER(TRFCNT); /* Channel Block Transfer Count */ - register8_t REPCNT; /* Channel Repeat Count */ - register8_t reserved_0x07; - register8_t SRCADDR0; /* Channel Source Address 0 */ - register8_t SRCADDR1; /* Channel Source Address 1 */ - register8_t reserved_0x0A; - register8_t reserved_0x0B; - register8_t DESTADDR0; /* Channel Destination Address 0 */ - register8_t DESTADDR1; /* Channel Destination Address 1 */ - register8_t reserved_0x0E; - register8_t reserved_0x0F; -} DMA_CH_t; - - -/* DMA Controller */ -typedef struct DMA_struct -{ - register8_t CTRL; /* Control */ - register8_t reserved_0x01; - register8_t reserved_0x02; - register8_t INTFLAGS; /* Transfer Interrupt Status */ - register8_t STATUS; /* Status */ - register8_t reserved_0x05; - _WORDREGISTER(TEMP); /* Temporary Register For 16-bit Access */ - register8_t reserved_0x08; - register8_t reserved_0x09; - register8_t reserved_0x0A; - register8_t reserved_0x0B; - register8_t reserved_0x0C; - register8_t reserved_0x0D; - register8_t reserved_0x0E; - register8_t reserved_0x0F; - DMA_CH_t CH0; /* DMA Channel 0 */ - DMA_CH_t CH1; /* DMA Channel 1 */ -} DMA_t; - -/* Burst mode */ -typedef enum DMA_CH_BURSTLEN_enum -{ - DMA_CH_BURSTLEN_1BYTE_gc = (0x00<<0), /* 1-byte burst mode */ - DMA_CH_BURSTLEN_2BYTE_gc = (0x01<<0), /* 2-byte burst mode */ - DMA_CH_BURSTLEN_4BYTE_gc = (0x02<<0), /* 4-byte burst mode */ - DMA_CH_BURSTLEN_8BYTE_gc = (0x03<<0), /* 8-byte burst mode */ -} DMA_CH_BURSTLEN_t; - -/* Source address reload mode */ -typedef enum DMA_CH_SRCRELOAD_enum -{ - DMA_CH_SRCRELOAD_NONE_gc = (0x00<<6), /* No reload */ - DMA_CH_SRCRELOAD_BLOCK_gc = (0x01<<6), /* Reload at end of block */ - DMA_CH_SRCRELOAD_BURST_gc = (0x02<<6), /* Reload at end of burst */ - DMA_CH_SRCRELOAD_TRANSACTION_gc = (0x03<<6), /* Reload at end of transaction */ -} DMA_CH_SRCRELOAD_t; - -/* Source addressing mode */ -typedef enum DMA_CH_SRCDIR_enum -{ - DMA_CH_SRCDIR_FIXED_gc = (0x00<<4), /* Fixed */ - DMA_CH_SRCDIR_INC_gc = (0x01<<4), /* Increment */ - DMA_CH_SRCDIR_DEC_gc = (0x02<<4), /* Decrement */ -} DMA_CH_SRCDIR_t; - -/* Destination adress reload mode */ -typedef enum DMA_CH_DESTRELOAD_enum -{ - DMA_CH_DESTRELOAD_NONE_gc = (0x00<<2), /* No reload */ - DMA_CH_DESTRELOAD_BLOCK_gc = (0x01<<2), /* Reload at end of block */ - DMA_CH_DESTRELOAD_BURST_gc = (0x02<<2), /* Reload at end of burst */ - DMA_CH_DESTRELOAD_TRANSACTION_gc = (0x03<<2), /* Reload at end of transaction */ -} DMA_CH_DESTRELOAD_t; - -/* Destination adressing mode */ -typedef enum DMA_CH_DESTDIR_enum -{ - DMA_CH_DESTDIR_FIXED_gc = (0x00<<0), /* Fixed */ - DMA_CH_DESTDIR_INC_gc = (0x01<<0), /* Increment */ - DMA_CH_DESTDIR_DEC_gc = (0x02<<0), /* Decrement */ -} DMA_CH_DESTDIR_t; - -/* Transfer trigger source */ -typedef enum DMA_CH_TRIGSRC_enum -{ - DMA_CH_TRIGSRC_OFF_gc = (0x00<<0), /* Off software triggers only */ - DMA_CH_TRIGSRC_EVSYS_CH0_gc = (0x01<<0), /* Event System Channel 0 */ - DMA_CH_TRIGSRC_EVSYS_CH1_gc = (0x02<<0), /* Event System Channel 1 */ - DMA_CH_TRIGSRC_EVSYS_CH2_gc = (0x03<<0), /* Event System Channel 2 */ - DMA_CH_TRIGSRC_ADCA_CH0_gc = (0x10<<0), /* ADCA Channel 0 */ - DMA_CH_TRIGSRC_ADCB_CH0_gc = (0x20<<0), /* ADCB Channel 0 */ - DMA_CH_TRIGSRC_TCC0_OVF_gc = (0x40<<0), /* Timer/Counter C0 Overflow */ - DMA_CH_TRIGSRC_TCC0_ERR_gc = (0x41<<0), /* Timer/Counter C0 Error */ - DMA_CH_TRIGSRC_TCC0_CCA_gc = (0x42<<0), /* Timer/Counter C0 Compare or Capture A */ - DMA_CH_TRIGSRC_TCC0_CCB_gc = (0x43<<0), /* Timer/Counter C0 Compare or Capture B */ - DMA_CH_TRIGSRC_TCC0_CCC_gc = (0x44<<0), /* Timer/Counter C0 Compare or Capture C */ - DMA_CH_TRIGSRC_TCC0_CCD_gc = (0x45<<0), /* Timer/Counter C0 Compare or Capture D */ - DMA_CH_TRIGSRC_TCC1_OVF_gc = (0x46<<0), /* Timer/Counter C1 Overflow */ - DMA_CH_TRIGSRC_TCC1_ERR_gc = (0x47<<0), /* Timer/Counter C1 Error */ - DMA_CH_TRIGSRC_TCC1_CCA_gc = (0x48<<0), /* Timer/Counter C1 Compare or Capture A */ - DMA_CH_TRIGSRC_TCC1_CCB_gc = (0x49<<0), /* Timer/Counter C1 Compare or Capture B */ - DMA_CH_TRIGSRC_SPIC_gc = (0x4A<<0), /* SPI C Transfer Complete */ - DMA_CH_TRIGSRC_USARTC0_RXC_gc = (0x4B<<0), /* USART C0 Receive Complete */ - DMA_CH_TRIGSRC_USARTC0_DRE_gc = (0x4C<<0), /* USART C0 Data Register Empty */ - DMA_CH_TRIGSRC_TCE0_OVF_gc = (0x80<<0), /* Timer/Counter E0 Overflow */ - DMA_CH_TRIGSRC_TCE0_ERR_gc = (0x81<<0), /* Timer/Counter E0 Error */ - DMA_CH_TRIGSRC_TCE0_CCA_gc = (0x82<<0), /* Timer/Counter E0 Compare or Capture A */ - DMA_CH_TRIGSRC_TCE0_CCB_gc = (0x83<<0), /* Timer/Counter E0 Compare or Capture B */ - DMA_CH_TRIGSRC_TCE0_CCC_gc = (0x84<<0), /* Timer/Counter E0 Compare or Capture C */ - DMA_CH_TRIGSRC_TCE0_CCD_gc = (0x85<<0), /* Timer/Counter E0 Compare or Capture D */ - DMA_CH_TRIGSRC_USARTE0_RXC_gc = (0x8B<<0), /* USART E0 Receive Complete */ - DMA_CH_TRIGSRC_USARTE0_DRE_gc = (0x8C<<0), /* USART E0 Data Register Empty */ -} DMA_CH_TRIGSRC_t; - -/* Double buffering mode */ -typedef enum DMA_DBUFMODE_enum -{ - DMA_DBUFMODE_DISABLED_gc = (0x00<<2), /* Double buffering disabled */ - DMA_DBUFMODE_CH01_gc = (0x01<<2), /* Double buffering enabled on channel 0/1 */ -} DMA_DBUFMODE_t; - -/* Priority mode */ -typedef enum DMA_PRIMODE_enum -{ - DMA_PRIMODE_RR01_gc = (0x00<<0), /* Round Robin */ - DMA_PRIMODE_CH0RR1_gc = (0x01<<0), /* Channel 0 > channel 1 */ -} DMA_PRIMODE_t; - -/* Interrupt level */ -typedef enum DMA_CH_ERRINTLVL_enum -{ - DMA_CH_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ - DMA_CH_ERRINTLVL_LO_gc = (0x01<<2), /* Low level */ - DMA_CH_ERRINTLVL_MED_gc = (0x02<<2), /* Medium level */ - DMA_CH_ERRINTLVL_HI_gc = (0x03<<2), /* High level */ -} DMA_CH_ERRINTLVL_t; - -/* Interrupt level */ -typedef enum DMA_CH_TRNINTLVL_enum -{ - DMA_CH_TRNINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ - DMA_CH_TRNINTLVL_LO_gc = (0x01<<0), /* Low level */ - DMA_CH_TRNINTLVL_MED_gc = (0x02<<0), /* Medium level */ - DMA_CH_TRNINTLVL_HI_gc = (0x03<<0), /* High level */ -} DMA_CH_TRNINTLVL_t; - - -/* --------------------------------------------------------------------------- -EVSYS - Event System --------------------------------------------------------------------------- -*/ - -/* Event System */ -typedef struct EVSYS_struct -{ - register8_t CH0MUX; /* Event Channel 0 Multiplexer */ - register8_t CH1MUX; /* Event Channel 1 Multiplexer */ - register8_t CH2MUX; /* Event Channel 2 Multiplexer */ - register8_t CH3MUX; /* Event Channel 3 Multiplexer */ - register8_t reserved_0x04; - register8_t reserved_0x05; - register8_t reserved_0x06; - register8_t reserved_0x07; - register8_t CH0CTRL; /* Channel 0 Control Register */ - register8_t CH1CTRL; /* Channel 1 Control Register */ - register8_t CH2CTRL; /* Channel 2 Control Register */ - register8_t CH3CTRL; /* Channel 3 Control Register */ - register8_t reserved_0x0C; - register8_t reserved_0x0D; - register8_t reserved_0x0E; - register8_t reserved_0x0F; - register8_t STROBE; /* Event Strobe */ - register8_t DATA; /* Event Data */ -} EVSYS_t; - -/* Quadrature Decoder Index Recognition Mode */ -typedef enum EVSYS_QDIRM_enum -{ - EVSYS_QDIRM_00_gc = (0x00<<5), /* QDPH0 = 0, QDPH90 = 0 */ - EVSYS_QDIRM_01_gc = (0x01<<5), /* QDPH0 = 0, QDPH90 = 1 */ - EVSYS_QDIRM_10_gc = (0x02<<5), /* QDPH0 = 1, QDPH90 = 0 */ - EVSYS_QDIRM_11_gc = (0x03<<5), /* QDPH0 = 1, QDPH90 = 1 */ -} EVSYS_QDIRM_t; - -/* Digital filter coefficient */ -typedef enum EVSYS_DIGFILT_enum -{ - EVSYS_DIGFILT_1SAMPLE_gc = (0x00<<0), /* 1 SAMPLE */ - EVSYS_DIGFILT_2SAMPLES_gc = (0x01<<0), /* 2 SAMPLES */ - EVSYS_DIGFILT_3SAMPLES_gc = (0x02<<0), /* 3 SAMPLES */ - EVSYS_DIGFILT_4SAMPLES_gc = (0x03<<0), /* 4 SAMPLES */ - EVSYS_DIGFILT_5SAMPLES_gc = (0x04<<0), /* 5 SAMPLES */ - EVSYS_DIGFILT_6SAMPLES_gc = (0x05<<0), /* 6 SAMPLES */ - EVSYS_DIGFILT_7SAMPLES_gc = (0x06<<0), /* 7 SAMPLES */ - EVSYS_DIGFILT_8SAMPLES_gc = (0x07<<0), /* 8 SAMPLES */ -} EVSYS_DIGFILT_t; - -/* Event Channel multiplexer input selection */ -typedef enum EVSYS_CHMUX_enum -{ - EVSYS_CHMUX_OFF_gc = (0x00<<0), /* Off */ - EVSYS_CHMUX_RTC_OVF_gc = (0x08<<0), /* RTC Overflow */ - EVSYS_CHMUX_RTC_CMP_gc = (0x09<<0), /* RTC Compare Match */ - EVSYS_CHMUX_USB_gc = (0x0A<<0), /* USB Setup, SOF, CRC error and UNF/OVF */ - EVSYS_CHMUX_ACA_CH0_gc = (0x10<<0), /* Analog Comparator A Channel 0 */ - EVSYS_CHMUX_ACA_CH1_gc = (0x11<<0), /* Analog Comparator A Channel 1 */ - EVSYS_CHMUX_ACA_WIN_gc = (0x12<<0), /* Analog Comparator A Window */ - EVSYS_CHMUX_ACB_CH0_gc = (0x13<<0), /* Analog Comparator B Channel 0 */ - EVSYS_CHMUX_ACB_CH1_gc = (0x14<<0), /* Analog Comparator B Channel 1 */ - EVSYS_CHMUX_ACB_WIN_gc = (0x15<<0), /* Analog Comparator B Window */ - EVSYS_CHMUX_ADCA_CH0_gc = (0x20<<0), /* ADC A Channel */ - EVSYS_CHMUX_ADCB_CH0_gc = (0x24<<0), /* ADC B Channel */ - EVSYS_CHMUX_PORTA_PIN0_gc = (0x50<<0), /* Port A, Pin0 */ - EVSYS_CHMUX_PORTA_PIN1_gc = (0x51<<0), /* Port A, Pin1 */ - EVSYS_CHMUX_PORTA_PIN2_gc = (0x52<<0), /* Port A, Pin2 */ - EVSYS_CHMUX_PORTA_PIN3_gc = (0x53<<0), /* Port A, Pin3 */ - EVSYS_CHMUX_PORTA_PIN4_gc = (0x54<<0), /* Port A, Pin4 */ - EVSYS_CHMUX_PORTA_PIN5_gc = (0x55<<0), /* Port A, Pin5 */ - EVSYS_CHMUX_PORTA_PIN6_gc = (0x56<<0), /* Port A, Pin6 */ - EVSYS_CHMUX_PORTA_PIN7_gc = (0x57<<0), /* Port A, Pin7 */ - EVSYS_CHMUX_PORTB_PIN0_gc = (0x58<<0), /* Port B, Pin0 */ - EVSYS_CHMUX_PORTB_PIN1_gc = (0x59<<0), /* Port B, Pin1 */ - EVSYS_CHMUX_PORTB_PIN2_gc = (0x5A<<0), /* Port B, Pin2 */ - EVSYS_CHMUX_PORTB_PIN3_gc = (0x5B<<0), /* Port B, Pin3 */ - EVSYS_CHMUX_PORTB_PIN4_gc = (0x5C<<0), /* Port B, Pin4 */ - EVSYS_CHMUX_PORTB_PIN5_gc = (0x5D<<0), /* Port B, Pin5 */ - EVSYS_CHMUX_PORTB_PIN6_gc = (0x5E<<0), /* Port B, Pin6 */ - EVSYS_CHMUX_PORTB_PIN7_gc = (0x5F<<0), /* Port B, Pin7 */ - EVSYS_CHMUX_PORTC_PIN0_gc = (0x60<<0), /* Port C, Pin0 */ - EVSYS_CHMUX_PORTC_PIN1_gc = (0x61<<0), /* Port C, Pin1 */ - EVSYS_CHMUX_PORTC_PIN2_gc = (0x62<<0), /* Port C, Pin2 */ - EVSYS_CHMUX_PORTC_PIN3_gc = (0x63<<0), /* Port C, Pin3 */ - EVSYS_CHMUX_PORTC_PIN4_gc = (0x64<<0), /* Port C, Pin4 */ - EVSYS_CHMUX_PORTC_PIN5_gc = (0x65<<0), /* Port C, Pin5 */ - EVSYS_CHMUX_PORTC_PIN6_gc = (0x66<<0), /* Port C, Pin6 */ - EVSYS_CHMUX_PORTC_PIN7_gc = (0x67<<0), /* Port C, Pin7 */ - EVSYS_CHMUX_PORTD_PIN0_gc = (0x68<<0), /* Port D, Pin0 */ - EVSYS_CHMUX_PORTD_PIN1_gc = (0x69<<0), /* Port D, Pin1 */ - EVSYS_CHMUX_PORTD_PIN2_gc = (0x6A<<0), /* Port D, Pin2 */ - EVSYS_CHMUX_PORTE_PIN0_gc = (0x70<<0), /* Port E, Pin0 */ - EVSYS_CHMUX_PORTE_PIN1_gc = (0x71<<0), /* Port E, Pin1 */ - EVSYS_CHMUX_PORTE_PIN2_gc = (0x72<<0), /* Port E, Pin2 */ - EVSYS_CHMUX_PORTE_PIN3_gc = (0x73<<0), /* Port E, Pin3 */ - EVSYS_CHMUX_PORTE_PIN4_gc = (0x74<<0), /* Port E, Pin4 */ - EVSYS_CHMUX_PORTE_PIN5_gc = (0x75<<0), /* Port E, Pin5 */ - EVSYS_CHMUX_PORTE_PIN6_gc = (0x76<<0), /* Port E, Pin6 */ - EVSYS_CHMUX_PORTE_PIN7_gc = (0x77<<0), /* Port E, Pin7 */ - EVSYS_CHMUX_PRESCALER_1_gc = (0x80<<0), /* Prescaler, divide by 1 */ - EVSYS_CHMUX_PRESCALER_2_gc = (0x81<<0), /* Prescaler, divide by 2 */ - EVSYS_CHMUX_PRESCALER_4_gc = (0x82<<0), /* Prescaler, divide by 4 */ - EVSYS_CHMUX_PRESCALER_8_gc = (0x83<<0), /* Prescaler, divide by 8 */ - EVSYS_CHMUX_PRESCALER_16_gc = (0x84<<0), /* Prescaler, divide by 16 */ - EVSYS_CHMUX_PRESCALER_32_gc = (0x85<<0), /* Prescaler, divide by 32 */ - EVSYS_CHMUX_PRESCALER_64_gc = (0x86<<0), /* Prescaler, divide by 64 */ - EVSYS_CHMUX_PRESCALER_128_gc = (0x87<<0), /* Prescaler, divide by 128 */ - EVSYS_CHMUX_PRESCALER_256_gc = (0x88<<0), /* Prescaler, divide by 256 */ - EVSYS_CHMUX_PRESCALER_512_gc = (0x89<<0), /* Prescaler, divide by 512 */ - EVSYS_CHMUX_PRESCALER_1024_gc = (0x8A<<0), /* Prescaler, divide by 1024 */ - EVSYS_CHMUX_PRESCALER_2048_gc = (0x8B<<0), /* Prescaler, divide by 2048 */ - EVSYS_CHMUX_PRESCALER_4096_gc = (0x8C<<0), /* Prescaler, divide by 4096 */ - EVSYS_CHMUX_PRESCALER_8192_gc = (0x8D<<0), /* Prescaler, divide by 8192 */ - EVSYS_CHMUX_PRESCALER_16384_gc = (0x8E<<0), /* Prescaler, divide by 16384 */ - EVSYS_CHMUX_PRESCALER_32768_gc = (0x8F<<0), /* Prescaler, divide by 32768 */ - EVSYS_CHMUX_TCC0_OVF_gc = (0xC0<<0), /* Timer/Counter C0 Overflow */ - EVSYS_CHMUX_TCC0_ERR_gc = (0xC1<<0), /* Timer/Counter C0 Error */ - EVSYS_CHMUX_TCC0_CCA_gc = (0xC4<<0), /* Timer/Counter C0 Compare or Capture A */ - EVSYS_CHMUX_TCC0_CCB_gc = (0xC5<<0), /* Timer/Counter C0 Compare or Capture B */ - EVSYS_CHMUX_TCC0_CCC_gc = (0xC6<<0), /* Timer/Counter C0 Compare or Capture C */ - EVSYS_CHMUX_TCC0_CCD_gc = (0xC7<<0), /* Timer/Counter C0 Compare or Capture D */ - EVSYS_CHMUX_TCC1_OVF_gc = (0xC8<<0), /* Timer/Counter C1 Overflow */ - EVSYS_CHMUX_TCC1_ERR_gc = (0xC9<<0), /* Timer/Counter C1 Error */ - EVSYS_CHMUX_TCC1_CCA_gc = (0xCC<<0), /* Timer/Counter C1 Compare or Capture A */ - EVSYS_CHMUX_TCC1_CCB_gc = (0xCD<<0), /* Timer/Counter C1 Compare or Capture B */ - EVSYS_CHMUX_TCE0_OVF_gc = (0xE0<<0), /* Timer/Counter E0 Overflow */ - EVSYS_CHMUX_TCE0_ERR_gc = (0xE1<<0), /* Timer/Counter E0 Error */ - EVSYS_CHMUX_TCE0_CCA_gc = (0xE4<<0), /* Timer/Counter E0 Compare or Capture A */ - EVSYS_CHMUX_TCE0_CCB_gc = (0xE5<<0), /* Timer/Counter E0 Compare or Capture B */ - EVSYS_CHMUX_TCE0_CCC_gc = (0xE6<<0), /* Timer/Counter E0 Compare or Capture C */ - EVSYS_CHMUX_TCE0_CCD_gc = (0xE7<<0), /* Timer/Counter E0 Compare or Capture D */ -} EVSYS_CHMUX_t; - - -/* --------------------------------------------------------------------------- -NVM - Non Volatile Memory Controller --------------------------------------------------------------------------- -*/ - -/* Non-volatile Memory Controller */ -typedef struct NVM_struct -{ - register8_t ADDR0; /* Address Register 0 */ - register8_t ADDR1; /* Address Register 1 */ - register8_t ADDR2; /* Address Register 2 */ - register8_t reserved_0x03; - register8_t DATA0; /* Data Register 0 */ - register8_t DATA1; /* Data Register 1 */ - register8_t DATA2; /* Data Register 2 */ - register8_t reserved_0x07; - register8_t reserved_0x08; - register8_t reserved_0x09; - register8_t CMD; /* Command */ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t INTCTRL; /* Interrupt Control */ - register8_t reserved_0x0E; - register8_t STATUS; /* Status */ - register8_t LOCK_BITS; /* Lock Bits (Changed from LOCKBITS to avoid avr-libc collision) */ -} NVM_t; - -/* NVM Command */ -typedef enum NVM_CMD_enum -{ - NVM_CMD_NO_OPERATION_gc = (0x00<<0), /* Noop/Ordinary LPM */ - NVM_CMD_READ_USER_SIG_ROW_gc = (0x01<<0), /* Read user signature row */ - NVM_CMD_READ_CALIB_ROW_gc = (0x02<<0), /* Read calibration row */ - NVM_CMD_READ_EEPROM_gc = (0x06<<0), /* Read EEPROM */ - NVM_CMD_READ_FUSES_gc = (0x07<<0), /* Read fuse byte */ - NVM_CMD_WRITE_LOCK_BITS_gc = (0x08<<0), /* Write lock bits */ - NVM_CMD_ERASE_USER_SIG_ROW_gc = (0x18<<0), /* Erase user signature row */ - NVM_CMD_WRITE_USER_SIG_ROW_gc = (0x1A<<0), /* Write user signature row */ - NVM_CMD_ERASE_APP_gc = (0x20<<0), /* Erase Application Section */ - NVM_CMD_ERASE_APP_PAGE_gc = (0x22<<0), /* Erase Application Section page */ - NVM_CMD_LOAD_FLASH_BUFFER_gc = (0x23<<0), /* Load Flash page buffer */ - NVM_CMD_WRITE_APP_PAGE_gc = (0x24<<0), /* Write Application Section page */ - NVM_CMD_ERASE_WRITE_APP_PAGE_gc = (0x25<<0), /* Erase-and-write Application Section page */ - NVM_CMD_ERASE_FLASH_BUFFER_gc = (0x26<<0), /* Erase/flush Flash page buffer */ - NVM_CMD_ERASE_BOOT_PAGE_gc = (0x2A<<0), /* Erase Boot Section page */ - NVM_CMD_ERASE_FLASH_PAGE_gc = (0x2B<<0), /* Erase Flash Page */ - NVM_CMD_WRITE_BOOT_PAGE_gc = (0x2C<<0), /* Write Boot Section page */ - NVM_CMD_ERASE_WRITE_BOOT_PAGE_gc = (0x2D<<0), /* Erase-and-write Boot Section page */ - NVM_CMD_WRITE_FLASH_PAGE_gc = (0x2E<<0), /* Write Flash Page */ - NVM_CMD_ERASE_WRITE_FLASH_PAGE_gc = (0x2F<<0), /* Erase-and-write Flash Page */ - NVM_CMD_ERASE_EEPROM_gc = (0x30<<0), /* Erase EEPROM */ - NVM_CMD_ERASE_EEPROM_PAGE_gc = (0x32<<0), /* Erase EEPROM page */ - NVM_CMD_LOAD_EEPROM_BUFFER_gc = (0x33<<0), /* Load EEPROM page buffer */ - NVM_CMD_WRITE_EEPROM_PAGE_gc = (0x34<<0), /* Write EEPROM page */ - NVM_CMD_ERASE_WRITE_EEPROM_PAGE_gc = (0x35<<0), /* Erase-and-write EEPROM page */ - NVM_CMD_ERASE_EEPROM_BUFFER_gc = (0x36<<0), /* Erase/flush EEPROM page buffer */ - NVM_CMD_APP_CRC_gc = (0x38<<0), /* Application section CRC */ - NVM_CMD_BOOT_CRC_gc = (0x39<<0), /* Boot Section CRC */ - NVM_CMD_FLASH_RANGE_CRC_gc = (0x3A<<0), /* Flash Range CRC */ - NVM_CMD_CHIP_ERASE_gc = (0x40<<0), /* Erase Chip */ - NVM_CMD_READ_NVM_gc = (0x43<<0), /* Read NVM */ - NVM_CMD_WRITE_FUSE_gc = (0x4C<<0), /* Write Fuse byte */ - NVM_CMD_ERASE_BOOT_gc = (0x68<<0), /* Erase Boot Section */ - NVM_CMD_FLASH_CRC_gc = (0x78<<0), /* Flash CRC */ -} NVM_CMD_t; - -/* SPM ready interrupt level */ -typedef enum NVM_SPMLVL_enum -{ - NVM_SPMLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ - NVM_SPMLVL_LO_gc = (0x01<<2), /* Low level */ - NVM_SPMLVL_MED_gc = (0x02<<2), /* Medium level */ - NVM_SPMLVL_HI_gc = (0x03<<2), /* High level */ -} NVM_SPMLVL_t; - -/* EEPROM ready interrupt level */ -typedef enum NVM_EELVL_enum -{ - NVM_EELVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ - NVM_EELVL_LO_gc = (0x01<<0), /* Low level */ - NVM_EELVL_MED_gc = (0x02<<0), /* Medium level */ - NVM_EELVL_HI_gc = (0x03<<0), /* High level */ -} NVM_EELVL_t; - -/* Boot lock bits - boot setcion */ -typedef enum NVM_BLBB_enum -{ - NVM_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ - NVM_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ - NVM_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ - NVM_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ -} NVM_BLBB_t; - -/* Boot lock bits - application section */ -typedef enum NVM_BLBA_enum -{ - NVM_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ - NVM_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ - NVM_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ - NVM_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ -} NVM_BLBA_t; - -/* Boot lock bits - application table section */ -typedef enum NVM_BLBAT_enum -{ - NVM_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ - NVM_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ - NVM_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ - NVM_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ -} NVM_BLBAT_t; - -/* Lock bits */ -typedef enum NVM_LB_enum -{ - NVM_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ - NVM_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ - NVM_LB_NOLOCK_gc = (0x03<<0), /* No locks */ -} NVM_LB_t; - - -/* --------------------------------------------------------------------------- -ADC - Analog/Digital Converter --------------------------------------------------------------------------- -*/ - -/* ADC Channel */ -typedef struct ADC_CH_struct -{ - register8_t CTRL; /* Control Register */ - register8_t MUXCTRL; /* MUX Control */ - register8_t INTCTRL; /* Channel Interrupt Control Register */ - register8_t INTFLAGS; /* Interrupt Flags */ - _WORDREGISTER(RES); /* Channel Result */ - register8_t SCAN; /* Input Channel Scan */ - register8_t reserved_0x07; -} ADC_CH_t; - - -/* Analog-to-Digital Converter */ -typedef struct ADC_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t REFCTRL; /* Reference Control */ - register8_t EVCTRL; /* Event Control */ - register8_t PRESCALER; /* Clock Prescaler */ - register8_t reserved_0x05; - register8_t INTFLAGS; /* Interrupt Flags */ - register8_t TEMP; /* Temporary Register */ - register8_t SAMPCTRL; /* ADC Sampling Time Control Register */ - register8_t reserved_0x09; - register8_t reserved_0x0A; - register8_t reserved_0x0B; - _WORDREGISTER(CAL); /* Calibration Value */ - register8_t reserved_0x0E; - register8_t reserved_0x0F; - _WORDREGISTER(CH0RES); /* Channel 0 Result */ - register8_t reserved_0x12; - register8_t reserved_0x13; - register8_t reserved_0x14; - register8_t reserved_0x15; - register8_t reserved_0x16; - register8_t reserved_0x17; - _WORDREGISTER(CMP); /* Compare Value */ - register8_t reserved_0x1A; - register8_t reserved_0x1B; - register8_t reserved_0x1C; - register8_t reserved_0x1D; - register8_t reserved_0x1E; - register8_t reserved_0x1F; - ADC_CH_t CH0; /* ADC Channel 0 */ -} ADC_t; - -/* Current Limitation */ -typedef enum ADC_CURRLIMIT_enum -{ - ADC_CURRLIMIT_NO_gc = (0x00<<5), /* No current limit, 300ksps max sampling rate */ - ADC_CURRLIMIT_LOW_gc = (0x01<<5), /* Low current limit, 250ksps max sampling rate */ - ADC_CURRLIMIT_MED_gc = (0x02<<5), /* Medium current limit, 150ksps max sampling rate */ - ADC_CURRLIMIT_HIGH_gc = (0x03<<5), /* High current limit, 50ksps max sampling rate */ -} ADC_CURRLIMIT_t; - -/* Positive input multiplexer selection */ -typedef enum ADC_CH_MUXPOS_enum -{ - ADC_CH_MUXPOS_PIN0_gc = (0x00<<3), /* Input pin 0 */ - ADC_CH_MUXPOS_PIN1_gc = (0x01<<3), /* Input pin 1 */ - ADC_CH_MUXPOS_PIN2_gc = (0x02<<3), /* Input pin 2 */ - ADC_CH_MUXPOS_PIN3_gc = (0x03<<3), /* Input pin 3 */ - ADC_CH_MUXPOS_PIN4_gc = (0x04<<3), /* Input pin 4 */ - ADC_CH_MUXPOS_PIN5_gc = (0x05<<3), /* Input pin 5 */ - ADC_CH_MUXPOS_PIN6_gc = (0x06<<3), /* Input pin 6 */ - ADC_CH_MUXPOS_PIN7_gc = (0x07<<3), /* Input pin 7 */ - ADC_CH_MUXPOS_PIN8_gc = (0x08<<3), /* Input pin 8 */ - ADC_CH_MUXPOS_PIN9_gc = (0x09<<3), /* Input pin 9 */ - ADC_CH_MUXPOS_PIN10_gc = (0x0A<<3), /* Input pin 10 */ - ADC_CH_MUXPOS_PIN11_gc = (0x0B<<3), /* Input pin 11 */ - ADC_CH_MUXPOS_PIN12_gc = (0x0C<<3), /* Input pin 12 */ - ADC_CH_MUXPOS_PIN13_gc = (0x0D<<3), /* Input pin 13 */ - ADC_CH_MUXPOS_PIN14_gc = (0x0E<<3), /* Input pin 14 */ - ADC_CH_MUXPOS_PIN15_gc = (0x0F<<3), /* Input pin 15 */ -} ADC_CH_MUXPOS_t; - -/* Internal input multiplexer selections */ -typedef enum ADC_CH_MUXINT_enum -{ - ADC_CH_MUXINT_TEMP_gc = (0x00<<3), /* Temperature Reference */ - ADC_CH_MUXINT_BANDGAP_gc = (0x01<<3), /* Bandgap Reference */ - ADC_CH_MUXINT_SCALEDVCC_gc = (0x02<<3), /* 1/10 scaled VCC */ -} ADC_CH_MUXINT_t; - -/* Negative input multiplexer selection */ -typedef enum ADC_CH_MUXNEG_enum -{ - ADC_CH_MUXNEG_PIN0_gc = (0x00<<0), /* Input pin 0 */ - ADC_CH_MUXNEG_PIN1_gc = (0x01<<0), /* Input pin 1 */ - ADC_CH_MUXNEG_PIN2_gc = (0x02<<0), /* Input pin 2 */ - ADC_CH_MUXNEG_PIN3_gc = (0x03<<0), /* Input pin 3 */ - ADC_CH_MUXNEG_PIN4_gc = (0x00<<0), /* Input pin 4 */ - ADC_CH_MUXNEG_PIN5_gc = (0x01<<0), /* Input pin 5 */ - ADC_CH_MUXNEG_PIN6_gc = (0x02<<0), /* Input pin 6 */ - ADC_CH_MUXNEG_PIN7_gc = (0x03<<0), /* Input pin 7 */ -} ADC_CH_MUXNEG_t; - -/* Input mode */ -typedef enum ADC_CH_INPUTMODE_enum -{ - ADC_CH_INPUTMODE_INTERNAL_gc = (0x00<<0), /* Internal inputs, no gain */ - ADC_CH_INPUTMODE_SINGLEENDED_gc = (0x01<<0), /* Single-ended input, no gain */ - ADC_CH_INPUTMODE_DIFF_gc = (0x02<<0), /* Differential input, no gain */ - ADC_CH_INPUTMODE_DIFFWGAIN_gc = (0x03<<0), /* Differential input, with gain */ -} ADC_CH_INPUTMODE_t; - -/* Gain factor */ -typedef enum ADC_CH_GAIN_enum -{ - ADC_CH_GAIN_1X_gc = (0x00<<2), /* 1x gain */ - ADC_CH_GAIN_2X_gc = (0x01<<2), /* 2x gain */ - ADC_CH_GAIN_4X_gc = (0x02<<2), /* 4x gain */ - ADC_CH_GAIN_8X_gc = (0x03<<2), /* 8x gain */ - ADC_CH_GAIN_16X_gc = (0x04<<2), /* 16x gain */ - ADC_CH_GAIN_32X_gc = (0x05<<2), /* 32x gain */ - ADC_CH_GAIN_64X_gc = (0x06<<2), /* 64x gain */ - ADC_CH_GAIN_DIV2_gc = (0x07<<2), /* x/2 gain */ -} ADC_CH_GAIN_t; - -/* Conversion result resolution */ -typedef enum ADC_RESOLUTION_enum -{ - ADC_RESOLUTION_12BIT_gc = (0x00<<1), /* 12-bit right-adjusted result */ - ADC_RESOLUTION_8BIT_gc = (0x02<<1), /* 8-bit right-adjusted result */ - ADC_RESOLUTION_LEFT12BIT_gc = (0x03<<1), /* 12-bit left-adjusted result */ -} ADC_RESOLUTION_t; - -/* Voltage reference selection */ -typedef enum ADC_REFSEL_enum -{ - ADC_REFSEL_INT1V_gc = (0x00<<4), /* Internal 1V */ - ADC_REFSEL_INTVCC_gc = (0x01<<4), /* Internal VCC / 1.6 */ - ADC_REFSEL_AREFA_gc = (0x02<<4), /* External reference on PORT A */ - ADC_REFSEL_AREFB_gc = (0x03<<4), /* External reference on PORT B */ - ADC_REFSEL_INTVCC2_gc = (0x04<<4), /* Internal VCC / 2 */ -} ADC_REFSEL_t; - -/* Event channel input selection */ -typedef enum ADC_EVSEL_enum -{ - ADC_EVSEL_0_gc = (0x00<<3), /* Event Channel 0 */ - ADC_EVSEL_1_gc = (0x01<<3), /* Event Channel 1 */ - ADC_EVSEL_2_gc = (0x02<<3), /* Event Channel 2 */ - ADC_EVSEL_3_gc = (0x03<<3), /* Event Channel 3 */ -} ADC_EVSEL_t; - -/* Event action selection */ -typedef enum ADC_EVACT_enum -{ - ADC_EVACT_NONE_gc = (0x00<<0), /* No event action */ - ADC_EVACT_CH0_gc = (0x01<<0), /* First event triggers channel 0 */ - ADC_EVACT_SYNCSWEEP_gc = (0x06<<0), /* The ADC is flushed and restarted for accurate timing */ -} ADC_EVACT_t; - -/* Interupt mode */ -typedef enum ADC_CH_INTMODE_enum -{ - ADC_CH_INTMODE_COMPLETE_gc = (0x00<<2), /* Interrupt on conversion complete */ - ADC_CH_INTMODE_BELOW_gc = (0x01<<2), /* Interrupt on result below compare value */ - ADC_CH_INTMODE_ABOVE_gc = (0x03<<2), /* Interrupt on result above compare value */ -} ADC_CH_INTMODE_t; - -/* Interrupt level */ -typedef enum ADC_CH_INTLVL_enum -{ - ADC_CH_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ - ADC_CH_INTLVL_LO_gc = (0x01<<0), /* Low level */ - ADC_CH_INTLVL_MED_gc = (0x02<<0), /* Medium level */ - ADC_CH_INTLVL_HI_gc = (0x03<<0), /* High level */ -} ADC_CH_INTLVL_t; - -/* Clock prescaler */ -typedef enum ADC_PRESCALER_enum -{ - ADC_PRESCALER_DIV4_gc = (0x00<<0), /* Divide clock by 4 */ - ADC_PRESCALER_DIV8_gc = (0x01<<0), /* Divide clock by 8 */ - ADC_PRESCALER_DIV16_gc = (0x02<<0), /* Divide clock by 16 */ - ADC_PRESCALER_DIV32_gc = (0x03<<0), /* Divide clock by 32 */ - ADC_PRESCALER_DIV64_gc = (0x04<<0), /* Divide clock by 64 */ - ADC_PRESCALER_DIV128_gc = (0x05<<0), /* Divide clock by 128 */ - ADC_PRESCALER_DIV256_gc = (0x06<<0), /* Divide clock by 256 */ - ADC_PRESCALER_DIV512_gc = (0x07<<0), /* Divide clock by 512 */ -} ADC_PRESCALER_t; - - -/* --------------------------------------------------------------------------- -AC - Analog Comparator --------------------------------------------------------------------------- -*/ - -/* Analog Comparator */ -typedef struct AC_struct -{ - register8_t AC0CTRL; /* Analog Comparator 0 Control */ - register8_t AC1CTRL; /* Analog Comparator 1 Control */ - register8_t AC0MUXCTRL; /* Analog Comparator 0 MUX Control */ - register8_t AC1MUXCTRL; /* Analog Comparator 1 MUX Control */ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t WINCTRL; /* Window Mode Control */ - register8_t STATUS; /* Status */ - register8_t CURRCTRL; /* Current Source Control Register */ - register8_t CURRCALIB; /* Current Source Calibration Register */ -} AC_t; - -/* Interrupt mode */ -typedef enum AC_INTMODE_enum -{ - AC_INTMODE_BOTHEDGES_gc = (0x00<<6), /* Interrupt on both edges */ - AC_INTMODE_FALLING_gc = (0x02<<6), /* Interrupt on falling edge */ - AC_INTMODE_RISING_gc = (0x03<<6), /* Interrupt on rising edge */ -} AC_INTMODE_t; - -/* Interrupt level */ -typedef enum AC_INTLVL_enum -{ - AC_INTLVL_OFF_gc = (0x00<<4), /* Interrupt disabled */ - AC_INTLVL_LO_gc = (0x01<<4), /* Low level */ - AC_INTLVL_MED_gc = (0x02<<4), /* Medium level */ - AC_INTLVL_HI_gc = (0x03<<4), /* High level */ -} AC_INTLVL_t; - -/* Hysteresis mode selection */ -typedef enum AC_HYSMODE_enum -{ - AC_HYSMODE_NO_gc = (0x00<<1), /* No hysteresis */ - AC_HYSMODE_SMALL_gc = (0x01<<1), /* Small hysteresis */ - AC_HYSMODE_LARGE_gc = (0x02<<1), /* Large hysteresis */ -} AC_HYSMODE_t; - -/* Positive input multiplexer selection */ -typedef enum AC_MUXPOS_enum -{ - AC_MUXPOS_PIN0_gc = (0x00<<3), /* Pin 0 */ - AC_MUXPOS_PIN1_gc = (0x01<<3), /* Pin 1 */ - AC_MUXPOS_PIN2_gc = (0x02<<3), /* Pin 2 */ - AC_MUXPOS_PIN3_gc = (0x03<<3), /* Pin 3 */ - AC_MUXPOS_PIN4_gc = (0x04<<3), /* Pin 4 */ - AC_MUXPOS_PIN5_gc = (0x05<<3), /* Pin 5 */ - AC_MUXPOS_PIN6_gc = (0x06<<3), /* Pin 6 */ -} AC_MUXPOS_t; - -/* Negative input multiplexer selection */ -typedef enum AC_MUXNEG_enum -{ - AC_MUXNEG_PIN0_gc = (0x00<<0), /* Pin 0 */ - AC_MUXNEG_PIN1_gc = (0x01<<0), /* Pin 1 */ - AC_MUXNEG_PIN3_gc = (0x02<<0), /* Pin 3 */ - AC_MUXNEG_PIN5_gc = (0x03<<0), /* Pin 5 */ - AC_MUXNEG_PIN7_gc = (0x04<<0), /* Pin 7 */ - AC_MUXNEG_BANDGAP_gc = (0x06<<0), /* Bandgap Reference */ - AC_MUXNEG_SCALER_gc = (0x07<<0), /* Internal voltage scaler */ -} AC_MUXNEG_t; - -/* Windows interrupt mode */ -typedef enum AC_WINTMODE_enum -{ - AC_WINTMODE_ABOVE_gc = (0x00<<2), /* Interrupt on above window */ - AC_WINTMODE_INSIDE_gc = (0x01<<2), /* Interrupt on inside window */ - AC_WINTMODE_BELOW_gc = (0x02<<2), /* Interrupt on below window */ - AC_WINTMODE_OUTSIDE_gc = (0x03<<2), /* Interrupt on outside window */ -} AC_WINTMODE_t; - -/* Window interrupt level */ -typedef enum AC_WINTLVL_enum -{ - AC_WINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ - AC_WINTLVL_LO_gc = (0x01<<0), /* Low priority */ - AC_WINTLVL_MED_gc = (0x02<<0), /* Medium priority */ - AC_WINTLVL_HI_gc = (0x03<<0), /* High priority */ -} AC_WINTLVL_t; - -/* Window mode state */ -typedef enum AC_WSTATE_enum -{ - AC_WSTATE_ABOVE_gc = (0x00<<6), /* Signal above window */ - AC_WSTATE_INSIDE_gc = (0x01<<6), /* Signal inside window */ - AC_WSTATE_BELOW_gc = (0x02<<6), /* Signal below window */ -} AC_WSTATE_t; - - -/* --------------------------------------------------------------------------- -RTC - Real-Time Counter --------------------------------------------------------------------------- -*/ - -/* Real-Time Counter */ -typedef struct RTC_struct -{ - register8_t CTRL; /* Control Register */ - register8_t STATUS; /* Status Register */ - register8_t INTCTRL; /* Interrupt Control Register */ - register8_t INTFLAGS; /* Interrupt Flags */ - register8_t TEMP; /* Temporary register */ - register8_t reserved_0x05; - register8_t reserved_0x06; - register8_t reserved_0x07; - _WORDREGISTER(CNT); /* Count Register */ - _WORDREGISTER(PER); /* Period Register */ - _WORDREGISTER(COMP); /* Compare Register */ -} RTC_t; - -/* Prescaler Factor */ -typedef enum RTC_PRESCALER_enum -{ - RTC_PRESCALER_OFF_gc = (0x00<<0), /* RTC Off */ - RTC_PRESCALER_DIV1_gc = (0x01<<0), /* RTC Clock */ - RTC_PRESCALER_DIV2_gc = (0x02<<0), /* RTC Clock / 2 */ - RTC_PRESCALER_DIV8_gc = (0x03<<0), /* RTC Clock / 8 */ - RTC_PRESCALER_DIV16_gc = (0x04<<0), /* RTC Clock / 16 */ - RTC_PRESCALER_DIV64_gc = (0x05<<0), /* RTC Clock / 64 */ - RTC_PRESCALER_DIV256_gc = (0x06<<0), /* RTC Clock / 256 */ - RTC_PRESCALER_DIV1024_gc = (0x07<<0), /* RTC Clock / 1024 */ -} RTC_PRESCALER_t; - -/* Compare Interrupt level */ -typedef enum RTC_COMPINTLVL_enum -{ - RTC_COMPINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ - RTC_COMPINTLVL_LO_gc = (0x01<<2), /* Low Level */ - RTC_COMPINTLVL_MED_gc = (0x02<<2), /* Medium Level */ - RTC_COMPINTLVL_HI_gc = (0x03<<2), /* High Level */ -} RTC_COMPINTLVL_t; - -/* Overflow Interrupt level */ -typedef enum RTC_OVFINTLVL_enum -{ - RTC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - RTC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ - RTC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ - RTC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ -} RTC_OVFINTLVL_t; - - -/* --------------------------------------------------------------------------- -TWI - Two-Wire Interface --------------------------------------------------------------------------- -*/ - -/* */ -typedef struct TWI_MASTER_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t CTRLC; /* Control Register C */ - register8_t STATUS; /* Status Register */ - register8_t BAUD; /* Baurd Rate Control Register */ - register8_t ADDR; /* Address Register */ - register8_t DATA; /* Data Register */ -} TWI_MASTER_t; - - -/* */ -typedef struct TWI_SLAVE_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t STATUS; /* Status Register */ - register8_t ADDR; /* Address Register */ - register8_t DATA; /* Data Register */ - register8_t ADDRMASK; /* Address Mask Register */ -} TWI_SLAVE_t; - - -/* Two-Wire Interface */ -typedef struct TWI_struct -{ - register8_t CTRL; /* TWI Common Control Register */ - TWI_MASTER_t MASTER; /* TWI master module */ - TWI_SLAVE_t SLAVE; /* TWI slave module */ -} TWI_t; - -/* SDA Hold Time */ -typedef enum TWI_SDAHOLD_enum -{ - TWI_SDAHOLD_OFF_gc = (0x00<<1), /* SDA Hold Time off */ - TWI_SDAHOLD_50NS_gc = (0x01<<1), /* SDA Hold Time 50 ns */ - TWI_SDAHOLD_300NS_gc = (0x02<<1), /* SDA Hold Time 300 ns */ - TWI_SDAHOLD_400NS_gc = (0x03<<1), /* SDA Hold Time 400 ns */ -} TWI_SDAHOLD_t; - -/* Master Interrupt Level */ -typedef enum TWI_MASTER_INTLVL_enum -{ - TWI_MASTER_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ - TWI_MASTER_INTLVL_LO_gc = (0x01<<6), /* Low Level */ - TWI_MASTER_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ - TWI_MASTER_INTLVL_HI_gc = (0x03<<6), /* High Level */ -} TWI_MASTER_INTLVL_t; - -/* Inactive Timeout */ -typedef enum TWI_MASTER_TIMEOUT_enum -{ - TWI_MASTER_TIMEOUT_DISABLED_gc = (0x00<<2), /* Bus Timeout Disabled */ - TWI_MASTER_TIMEOUT_50US_gc = (0x01<<2), /* 50 Microseconds */ - TWI_MASTER_TIMEOUT_100US_gc = (0x02<<2), /* 100 Microseconds */ - TWI_MASTER_TIMEOUT_200US_gc = (0x03<<2), /* 200 Microseconds */ -} TWI_MASTER_TIMEOUT_t; - -/* Master Command */ -typedef enum TWI_MASTER_CMD_enum -{ - TWI_MASTER_CMD_NOACT_gc = (0x00<<0), /* No Action */ - TWI_MASTER_CMD_REPSTART_gc = (0x01<<0), /* Issue Repeated Start Condition */ - TWI_MASTER_CMD_RECVTRANS_gc = (0x02<<0), /* Receive or Transmit Data */ - TWI_MASTER_CMD_STOP_gc = (0x03<<0), /* Issue Stop Condition */ -} TWI_MASTER_CMD_t; - -/* Master Bus State */ -typedef enum TWI_MASTER_BUSSTATE_enum -{ - TWI_MASTER_BUSSTATE_UNKNOWN_gc = (0x00<<0), /* Unknown Bus State */ - TWI_MASTER_BUSSTATE_IDLE_gc = (0x01<<0), /* Bus is Idle */ - TWI_MASTER_BUSSTATE_OWNER_gc = (0x02<<0), /* This Module Controls The Bus */ - TWI_MASTER_BUSSTATE_BUSY_gc = (0x03<<0), /* The Bus is Busy */ -} TWI_MASTER_BUSSTATE_t; - -/* Slave Interrupt Level */ -typedef enum TWI_SLAVE_INTLVL_enum -{ - TWI_SLAVE_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ - TWI_SLAVE_INTLVL_LO_gc = (0x01<<6), /* Low Level */ - TWI_SLAVE_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ - TWI_SLAVE_INTLVL_HI_gc = (0x03<<6), /* High Level */ -} TWI_SLAVE_INTLVL_t; - -/* Slave Command */ -typedef enum TWI_SLAVE_CMD_enum -{ - TWI_SLAVE_CMD_NOACT_gc = (0x00<<0), /* No Action */ - TWI_SLAVE_CMD_COMPTRANS_gc = (0x02<<0), /* Used To Complete a Transaction */ - TWI_SLAVE_CMD_RESPONSE_gc = (0x03<<0), /* Used in Response to Address/Data Interrupt */ -} TWI_SLAVE_CMD_t; - - -/* --------------------------------------------------------------------------- -USB - USB --------------------------------------------------------------------------- -*/ - -/* USB Endpoint */ -typedef struct USB_EP_struct -{ - register8_t STATUS; /* Endpoint Status */ - register8_t CTRL; /* Endpoint Control */ - _WORDREGISTER(CNT); /* USB Endpoint Counter */ - _WORDREGISTER(DATAPTR); /* Data Pointer */ - _WORDREGISTER(AUXDATA); /* Auxiliary Data */ -} USB_EP_t; - - -/* Universal Serial Bus */ -typedef struct USB_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t STATUS; /* Status Register */ - register8_t ADDR; /* Address Register */ - register8_t FIFOWP; /* FIFO Write Pointer Register */ - register8_t FIFORP; /* FIFO Read Pointer Register */ - _WORDREGISTER(EPPTR); /* Endpoint Configuration Table Pointer */ - register8_t INTCTRLA; /* Interrupt Control Register A */ - register8_t INTCTRLB; /* Interrupt Control Register B */ - register8_t INTFLAGSACLR; /* Clear Interrupt Flag Register A */ - register8_t INTFLAGSASET; /* Set Interrupt Flag Register A */ - register8_t INTFLAGSBCLR; /* Clear Interrupt Flag Register B */ - register8_t INTFLAGSBSET; /* Set Interrupt Flag Register B */ - register8_t reserved_0x0E; - register8_t reserved_0x0F; - register8_t reserved_0x10; - register8_t reserved_0x11; - register8_t reserved_0x12; - register8_t reserved_0x13; - register8_t reserved_0x14; - register8_t reserved_0x15; - register8_t reserved_0x16; - register8_t reserved_0x17; - register8_t reserved_0x18; - register8_t reserved_0x19; - register8_t reserved_0x1A; - register8_t reserved_0x1B; - register8_t reserved_0x1C; - register8_t reserved_0x1D; - register8_t reserved_0x1E; - register8_t reserved_0x1F; - register8_t reserved_0x20; - register8_t reserved_0x21; - register8_t reserved_0x22; - register8_t reserved_0x23; - register8_t reserved_0x24; - register8_t reserved_0x25; - register8_t reserved_0x26; - register8_t reserved_0x27; - register8_t reserved_0x28; - register8_t reserved_0x29; - register8_t reserved_0x2A; - register8_t reserved_0x2B; - register8_t reserved_0x2C; - register8_t reserved_0x2D; - register8_t reserved_0x2E; - register8_t reserved_0x2F; - register8_t reserved_0x30; - register8_t reserved_0x31; - register8_t reserved_0x32; - register8_t reserved_0x33; - register8_t reserved_0x34; - register8_t reserved_0x35; - register8_t reserved_0x36; - register8_t reserved_0x37; - register8_t reserved_0x38; - register8_t reserved_0x39; - register8_t CAL0; /* Calibration Byte 0 */ - register8_t CAL1; /* Calibration Byte 1 */ -} USB_t; - - -/* USB Endpoint Table */ -typedef struct USB_EP_TABLE_struct -{ - USB_EP_t EP0OUT; /* Endpoint 0 */ - USB_EP_t EP0IN; /* Endpoint 0 */ - USB_EP_t EP1OUT; /* Endpoint 1 */ - USB_EP_t EP1IN; /* Endpoint 1 */ - USB_EP_t EP2OUT; /* Endpoint 2 */ - USB_EP_t EP2IN; /* Endpoint 2 */ - USB_EP_t EP3OUT; /* Endpoint 3 */ - USB_EP_t EP3IN; /* Endpoint 3 */ - USB_EP_t EP4OUT; /* Endpoint 4 */ - USB_EP_t EP4IN; /* Endpoint 4 */ - USB_EP_t EP5OUT; /* Endpoint 5 */ - USB_EP_t EP5IN; /* Endpoint 5 */ - USB_EP_t EP6OUT; /* Endpoint 6 */ - USB_EP_t EP6IN; /* Endpoint 6 */ - USB_EP_t EP7OUT; /* Endpoint 7 */ - USB_EP_t EP7IN; /* Endpoint 7 */ - USB_EP_t EP8OUT; /* Endpoint 8 */ - USB_EP_t EP8IN; /* Endpoint 8 */ - USB_EP_t EP9OUT; /* Endpoint 9 */ - USB_EP_t EP9IN; /* Endpoint 9 */ - USB_EP_t EP10OUT; /* Endpoint 10 */ - USB_EP_t EP10IN; /* Endpoint 10 */ - USB_EP_t EP11OUT; /* Endpoint 11 */ - USB_EP_t EP11IN; /* Endpoint 11 */ - USB_EP_t EP12OUT; /* Endpoint 12 */ - USB_EP_t EP12IN; /* Endpoint 12 */ - USB_EP_t EP13OUT; /* Endpoint 13 */ - USB_EP_t EP13IN; /* Endpoint 13 */ - USB_EP_t EP14OUT; /* Endpoint 14 */ - USB_EP_t EP14IN; /* Endpoint 14 */ - USB_EP_t EP15OUT; /* Endpoint 15 */ - USB_EP_t EP15IN; /* Endpoint 15 */ - register8_t reserved_0x100; - register8_t reserved_0x101; - register8_t reserved_0x102; - register8_t reserved_0x103; - register8_t reserved_0x104; - register8_t reserved_0x105; - register8_t reserved_0x106; - register8_t reserved_0x107; - register8_t reserved_0x108; - register8_t reserved_0x109; - register8_t reserved_0x10A; - register8_t reserved_0x10B; - register8_t reserved_0x10C; - register8_t reserved_0x10D; - register8_t reserved_0x10E; - register8_t reserved_0x10F; - register8_t FRAMENUML; /* Frame Number Low Byte */ - register8_t FRAMENUMH; /* Frame Number High Byte */ -} USB_EP_TABLE_t; - -/* Interrupt level */ -typedef enum USB_INTLVL_enum -{ - USB_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ - USB_INTLVL_LO_gc = (0x01<<0), /* Low level */ - USB_INTLVL_MED_gc = (0x02<<0), /* Medium level */ - USB_INTLVL_HI_gc = (0x03<<0), /* High level */ -} USB_INTLVL_t; - -/* USB Endpoint Type */ -typedef enum USB_EP_TYPE_enum -{ - USB_EP_TYPE_DISABLE_gc = (0x00<<6), /* Endpoint Disabled */ - USB_EP_TYPE_CONTROL_gc = (0x01<<6), /* Control */ - USB_EP_TYPE_BULK_gc = (0x02<<6), /* Bulk/Interrupt */ - USB_EP_TYPE_ISOCHRONOUS_gc = (0x03<<6), /* Isochronous */ -} USB_EP_TYPE_t; - -/* USB Endpoint Buffersize */ -typedef enum USB_EP_BUFSIZE_enum -{ - USB_EP_BUFSIZE_8_gc = (0x00<<0), /* 8 bytes buffer size */ - USB_EP_BUFSIZE_16_gc = (0x01<<0), /* 16 bytes buffer size */ - USB_EP_BUFSIZE_32_gc = (0x02<<0), /* 32 bytes buffer size */ - USB_EP_BUFSIZE_64_gc = (0x03<<0), /* 64 bytes buffer size */ - USB_EP_BUFSIZE_128_gc = (0x04<<0), /* 128 bytes buffer size */ - USB_EP_BUFSIZE_256_gc = (0x05<<0), /* 256 bytes buffer size */ - USB_EP_BUFSIZE_512_gc = (0x06<<0), /* 512 bytes buffer size */ - USB_EP_BUFSIZE_1023_gc = (0x07<<0), /* 1023 bytes buffer size */ -} USB_EP_BUFSIZE_t; - - -/* --------------------------------------------------------------------------- -PORT - I/O Port Configuration --------------------------------------------------------------------------- -*/ - -/* I/O Ports */ -typedef struct PORT_struct -{ - register8_t DIR; /* I/O Port Data Direction */ - register8_t DIRSET; /* I/O Port Data Direction Set */ - register8_t DIRCLR; /* I/O Port Data Direction Clear */ - register8_t DIRTGL; /* I/O Port Data Direction Toggle */ - register8_t OUT; /* I/O Port Output */ - register8_t OUTSET; /* I/O Port Output Set */ - register8_t OUTCLR; /* I/O Port Output Clear */ - register8_t OUTTGL; /* I/O Port Output Toggle */ - register8_t IN; /* I/O port Input */ - register8_t INTCTRL; /* Interrupt Control Register */ - register8_t INT0MASK; /* Port Interrupt 0 Mask */ - register8_t INT1MASK; /* Port Interrupt 1 Mask */ - register8_t INTFLAGS; /* Interrupt Flag Register */ - register8_t reserved_0x0D; - register8_t REMAP; /* I/O Port Pin Remap Register */ - register8_t reserved_0x0F; - register8_t PIN0CTRL; /* Pin 0 Control Register */ - register8_t PIN1CTRL; /* Pin 1 Control Register */ - register8_t PIN2CTRL; /* Pin 2 Control Register */ - register8_t PIN3CTRL; /* Pin 3 Control Register */ - register8_t PIN4CTRL; /* Pin 4 Control Register */ - register8_t PIN5CTRL; /* Pin 5 Control Register */ - register8_t PIN6CTRL; /* Pin 6 Control Register */ - register8_t PIN7CTRL; /* Pin 7 Control Register */ -} PORT_t; - -/* Port Interrupt 0 Level */ -typedef enum PORT_INT0LVL_enum -{ - PORT_INT0LVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - PORT_INT0LVL_LO_gc = (0x01<<0), /* Low Level */ - PORT_INT0LVL_MED_gc = (0x02<<0), /* Medium Level */ - PORT_INT0LVL_HI_gc = (0x03<<0), /* High Level */ -} PORT_INT0LVL_t; - -/* Port Interrupt 1 Level */ -typedef enum PORT_INT1LVL_enum -{ - PORT_INT1LVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ - PORT_INT1LVL_LO_gc = (0x01<<2), /* Low Level */ - PORT_INT1LVL_MED_gc = (0x02<<2), /* Medium Level */ - PORT_INT1LVL_HI_gc = (0x03<<2), /* High Level */ -} PORT_INT1LVL_t; - -/* Output/Pull Configuration */ -typedef enum PORT_OPC_enum -{ - PORT_OPC_TOTEM_gc = (0x00<<3), /* Totempole */ - PORT_OPC_BUSKEEPER_gc = (0x01<<3), /* Totempole w/ Bus keeper on Input and Output */ - PORT_OPC_PULLDOWN_gc = (0x02<<3), /* Totempole w/ Pull-down on Input */ - PORT_OPC_PULLUP_gc = (0x03<<3), /* Totempole w/ Pull-up on Input */ - PORT_OPC_WIREDOR_gc = (0x04<<3), /* Wired OR */ - PORT_OPC_WIREDAND_gc = (0x05<<3), /* Wired AND */ - PORT_OPC_WIREDORPULL_gc = (0x06<<3), /* Wired OR w/ Pull-down */ - PORT_OPC_WIREDANDPULL_gc = (0x07<<3), /* Wired AND w/ Pull-up */ -} PORT_OPC_t; - -/* Input/Sense Configuration */ -typedef enum PORT_ISC_enum -{ - PORT_ISC_BOTHEDGES_gc = (0x00<<0), /* Sense Both Edges */ - PORT_ISC_RISING_gc = (0x01<<0), /* Sense Rising Edge */ - PORT_ISC_FALLING_gc = (0x02<<0), /* Sense Falling Edge */ - PORT_ISC_LEVEL_gc = (0x03<<0), /* Sense Level (Transparent For Events) */ - PORT_ISC_INPUT_DISABLE_gc = (0x07<<0), /* Disable Digital Input Buffer */ -} PORT_ISC_t; - - -/* --------------------------------------------------------------------------- -TC - 16-bit Timer/Counter With PWM --------------------------------------------------------------------------- -*/ - -/* 16-bit Timer/Counter 0 */ -typedef struct TC0_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t CTRLC; /* Control register C */ - register8_t CTRLD; /* Control Register D */ - register8_t CTRLE; /* Control Register E */ - register8_t reserved_0x05; - register8_t INTCTRLA; /* Interrupt Control Register A */ - register8_t INTCTRLB; /* Interrupt Control Register B */ - register8_t CTRLFCLR; /* Control Register F Clear */ - register8_t CTRLFSET; /* Control Register F Set */ - register8_t CTRLGCLR; /* Control Register G Clear */ - register8_t CTRLGSET; /* Control Register G Set */ - register8_t INTFLAGS; /* Interrupt Flag Register */ - register8_t reserved_0x0D; - register8_t reserved_0x0E; - register8_t TEMP; /* Temporary Register For 16-bit Access */ - register8_t reserved_0x10; - register8_t reserved_0x11; - register8_t reserved_0x12; - register8_t reserved_0x13; - register8_t reserved_0x14; - register8_t reserved_0x15; - register8_t reserved_0x16; - register8_t reserved_0x17; - register8_t reserved_0x18; - register8_t reserved_0x19; - register8_t reserved_0x1A; - register8_t reserved_0x1B; - register8_t reserved_0x1C; - register8_t reserved_0x1D; - register8_t reserved_0x1E; - register8_t reserved_0x1F; - _WORDREGISTER(CNT); /* Count */ - register8_t reserved_0x22; - register8_t reserved_0x23; - register8_t reserved_0x24; - register8_t reserved_0x25; - _WORDREGISTER(PER); /* Period */ - _WORDREGISTER(CCA); /* Compare or Capture A */ - _WORDREGISTER(CCB); /* Compare or Capture B */ - _WORDREGISTER(CCC); /* Compare or Capture C */ - _WORDREGISTER(CCD); /* Compare or Capture D */ - register8_t reserved_0x30; - register8_t reserved_0x31; - register8_t reserved_0x32; - register8_t reserved_0x33; - register8_t reserved_0x34; - register8_t reserved_0x35; - _WORDREGISTER(PERBUF); /* Period Buffer */ - _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ - _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ - _WORDREGISTER(CCCBUF); /* Compare Or Capture C Buffer */ - _WORDREGISTER(CCDBUF); /* Compare Or Capture D Buffer */ -} TC0_t; - - -/* 16-bit Timer/Counter 1 */ -typedef struct TC1_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t CTRLC; /* Control register C */ - register8_t CTRLD; /* Control Register D */ - register8_t CTRLE; /* Control Register E */ - register8_t reserved_0x05; - register8_t INTCTRLA; /* Interrupt Control Register A */ - register8_t INTCTRLB; /* Interrupt Control Register B */ - register8_t CTRLFCLR; /* Control Register F Clear */ - register8_t CTRLFSET; /* Control Register F Set */ - register8_t CTRLGCLR; /* Control Register G Clear */ - register8_t CTRLGSET; /* Control Register G Set */ - register8_t INTFLAGS; /* Interrupt Flag Register */ - register8_t reserved_0x0D; - register8_t reserved_0x0E; - register8_t TEMP; /* Temporary Register For 16-bit Access */ - register8_t reserved_0x10; - register8_t reserved_0x11; - register8_t reserved_0x12; - register8_t reserved_0x13; - register8_t reserved_0x14; - register8_t reserved_0x15; - register8_t reserved_0x16; - register8_t reserved_0x17; - register8_t reserved_0x18; - register8_t reserved_0x19; - register8_t reserved_0x1A; - register8_t reserved_0x1B; - register8_t reserved_0x1C; - register8_t reserved_0x1D; - register8_t reserved_0x1E; - register8_t reserved_0x1F; - _WORDREGISTER(CNT); /* Count */ - register8_t reserved_0x22; - register8_t reserved_0x23; - register8_t reserved_0x24; - register8_t reserved_0x25; - _WORDREGISTER(PER); /* Period */ - _WORDREGISTER(CCA); /* Compare or Capture A */ - _WORDREGISTER(CCB); /* Compare or Capture B */ - register8_t reserved_0x2C; - register8_t reserved_0x2D; - register8_t reserved_0x2E; - register8_t reserved_0x2F; - register8_t reserved_0x30; - register8_t reserved_0x31; - register8_t reserved_0x32; - register8_t reserved_0x33; - register8_t reserved_0x34; - register8_t reserved_0x35; - _WORDREGISTER(PERBUF); /* Period Buffer */ - _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ - _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ -} TC1_t; - -/* Clock Selection */ -typedef enum TC_CLKSEL_enum -{ - TC_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */ - TC_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */ - TC_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */ - TC_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */ - TC_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */ - TC_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */ - TC_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */ - TC_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */ - TC_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */ - TC_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */ - TC_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */ - TC_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */ -} TC_CLKSEL_t; - -/* Waveform Generation Mode */ -typedef enum TC_WGMODE_enum -{ - TC_WGMODE_NORMAL_gc = (0x00<<0), /* Normal Mode */ - TC_WGMODE_FRQ_gc = (0x01<<0), /* Frequency Generation Mode */ - TC_WGMODE_SINGLESLOPE_gc = (0x03<<0), /* Single Slope */ - TC_WGMODE_SS_gc = (0x03<<0), /* Single Slope */ - TC_WGMODE_DSTOP_gc = (0x05<<0), /* Dual Slope, Update on TOP */ - TC_WGMODE_DS_T_gc = (0x05<<0), /* Dual Slope, Update on TOP */ - TC_WGMODE_DSBOTH_gc = (0x06<<0), /* Dual Slope, Update on both TOP and BOTTOM */ - TC_WGMODE_DS_TB_gc = (0x06<<0), /* Dual Slope, Update on both TOP and BOTTOM */ - TC_WGMODE_DSBOTTOM_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */ - TC_WGMODE_DS_B_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */ -} TC_WGMODE_t; - -/* Byte Mode */ -typedef enum TC_BYTEM_enum -{ - TC_BYTEM_NORMAL_gc = (0x00<<0), /* 16-bit mode */ - TC_BYTEM_BYTEMODE_gc = (0x01<<0), /* Timer/Counter operating in byte mode only */ - TC_BYTEM_SPLITMODE_gc = (0x02<<0), /* Timer/Counter split into two 8-bit Counters (TC2) */ -} TC_BYTEM_t; - -/* Event Action */ -typedef enum TC_EVACT_enum -{ - TC_EVACT_OFF_gc = (0x00<<5), /* No Event Action */ - TC_EVACT_CAPT_gc = (0x01<<5), /* Input Capture */ - TC_EVACT_UPDOWN_gc = (0x02<<5), /* Externally Controlled Up/Down Count */ - TC_EVACT_QDEC_gc = (0x03<<5), /* Quadrature Decode */ - TC_EVACT_RESTART_gc = (0x04<<5), /* Restart */ - TC_EVACT_FRQ_gc = (0x05<<5), /* Frequency Capture */ - TC_EVACT_PW_gc = (0x06<<5), /* Pulse-width Capture */ -} TC_EVACT_t; - -/* Event Selection */ -typedef enum TC_EVSEL_enum -{ - TC_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ - TC_EVSEL_CH0_gc = (0x08<<0), /* Event Channel 0 */ - TC_EVSEL_CH1_gc = (0x09<<0), /* Event Channel 1 */ - TC_EVSEL_CH2_gc = (0x0A<<0), /* Event Channel 2 */ - TC_EVSEL_CH3_gc = (0x0B<<0), /* Event Channel 3 */ -} TC_EVSEL_t; - -/* Error Interrupt Level */ -typedef enum TC_ERRINTLVL_enum -{ - TC_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ - TC_ERRINTLVL_LO_gc = (0x01<<2), /* Low Level */ - TC_ERRINTLVL_MED_gc = (0x02<<2), /* Medium Level */ - TC_ERRINTLVL_HI_gc = (0x03<<2), /* High Level */ -} TC_ERRINTLVL_t; - -/* Overflow Interrupt Level */ -typedef enum TC_OVFINTLVL_enum -{ - TC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - TC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ - TC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ - TC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ -} TC_OVFINTLVL_t; - -/* Compare or Capture D Interrupt Level */ -typedef enum TC_CCDINTLVL_enum -{ - TC_CCDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ - TC_CCDINTLVL_LO_gc = (0x01<<6), /* Low Level */ - TC_CCDINTLVL_MED_gc = (0x02<<6), /* Medium Level */ - TC_CCDINTLVL_HI_gc = (0x03<<6), /* High Level */ -} TC_CCDINTLVL_t; - -/* Compare or Capture C Interrupt Level */ -typedef enum TC_CCCINTLVL_enum -{ - TC_CCCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ - TC_CCCINTLVL_LO_gc = (0x01<<4), /* Low Level */ - TC_CCCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ - TC_CCCINTLVL_HI_gc = (0x03<<4), /* High Level */ -} TC_CCCINTLVL_t; - -/* Compare or Capture B Interrupt Level */ -typedef enum TC_CCBINTLVL_enum -{ - TC_CCBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ - TC_CCBINTLVL_LO_gc = (0x01<<2), /* Low Level */ - TC_CCBINTLVL_MED_gc = (0x02<<2), /* Medium Level */ - TC_CCBINTLVL_HI_gc = (0x03<<2), /* High Level */ -} TC_CCBINTLVL_t; - -/* Compare or Capture A Interrupt Level */ -typedef enum TC_CCAINTLVL_enum -{ - TC_CCAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - TC_CCAINTLVL_LO_gc = (0x01<<0), /* Low Level */ - TC_CCAINTLVL_MED_gc = (0x02<<0), /* Medium Level */ - TC_CCAINTLVL_HI_gc = (0x03<<0), /* High Level */ -} TC_CCAINTLVL_t; - -/* Timer/Counter Command */ -typedef enum TC_CMD_enum -{ - TC_CMD_NONE_gc = (0x00<<2), /* No Command */ - TC_CMD_UPDATE_gc = (0x01<<2), /* Force Update */ - TC_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ - TC_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ -} TC_CMD_t; - - -/* --------------------------------------------------------------------------- -TC2 - 16-bit Timer/Counter type 2 --------------------------------------------------------------------------- -*/ - -/* 16-bit Timer/Counter type 2 */ -typedef struct TC2_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t CTRLC; /* Control register C */ - register8_t reserved_0x03; - register8_t CTRLE; /* Control Register E */ - register8_t reserved_0x05; - register8_t INTCTRLA; /* Interrupt Control Register A */ - register8_t INTCTRLB; /* Interrupt Control Register B */ - register8_t reserved_0x08; - register8_t CTRLF; /* Control Register F */ - register8_t reserved_0x0A; - register8_t reserved_0x0B; - register8_t INTFLAGS; /* Interrupt Flag Register */ - register8_t reserved_0x0D; - register8_t reserved_0x0E; - register8_t reserved_0x0F; - register8_t reserved_0x10; - register8_t reserved_0x11; - register8_t reserved_0x12; - register8_t reserved_0x13; - register8_t reserved_0x14; - register8_t reserved_0x15; - register8_t reserved_0x16; - register8_t reserved_0x17; - register8_t reserved_0x18; - register8_t reserved_0x19; - register8_t reserved_0x1A; - register8_t reserved_0x1B; - register8_t reserved_0x1C; - register8_t reserved_0x1D; - register8_t reserved_0x1E; - register8_t reserved_0x1F; - register8_t LCNT; /* Low Byte Count */ - register8_t HCNT; /* High Byte Count */ - register8_t reserved_0x22; - register8_t reserved_0x23; - register8_t reserved_0x24; - register8_t reserved_0x25; - register8_t LPER; /* Low Byte Period */ - register8_t HPER; /* High Byte Period */ - register8_t LCMPA; /* Low Byte Compare A */ - register8_t HCMPA; /* High Byte Compare A */ - register8_t LCMPB; /* Low Byte Compare B */ - register8_t HCMPB; /* High Byte Compare B */ - register8_t LCMPC; /* Low Byte Compare C */ - register8_t HCMPC; /* High Byte Compare C */ - register8_t LCMPD; /* Low Byte Compare D */ - register8_t HCMPD; /* High Byte Compare D */ -} TC2_t; - -/* Clock Selection */ -typedef enum TC2_CLKSEL_enum -{ - TC2_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */ - TC2_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */ - TC2_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */ - TC2_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */ - TC2_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */ - TC2_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */ - TC2_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */ - TC2_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */ - TC2_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */ - TC2_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */ - TC2_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */ - TC2_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */ -} TC2_CLKSEL_t; - -/* Byte Mode */ -typedef enum TC2_BYTEM_enum -{ - TC2_BYTEM_NORMAL_gc = (0x00<<0), /* 16-bit mode */ - TC2_BYTEM_BYTEMODE_gc = (0x01<<0), /* Timer/Counter operating in byte mode only (TC2) */ - TC2_BYTEM_SPLITMODE_gc = (0x02<<0), /* Timer/Counter split into two 8-bit Counters */ -} TC2_BYTEM_t; - -/* High Byte Underflow Interrupt Level */ -typedef enum TC2_HUNFINTLVL_enum -{ - TC2_HUNFINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ - TC2_HUNFINTLVL_LO_gc = (0x01<<2), /* Low Level */ - TC2_HUNFINTLVL_MED_gc = (0x02<<2), /* Medium Level */ - TC2_HUNFINTLVL_HI_gc = (0x03<<2), /* High Level */ -} TC2_HUNFINTLVL_t; - -/* Low Byte Underflow Interrupt Level */ -typedef enum TC2_LUNFINTLVL_enum -{ - TC2_LUNFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - TC2_LUNFINTLVL_LO_gc = (0x01<<0), /* Low Level */ - TC2_LUNFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ - TC2_LUNFINTLVL_HI_gc = (0x03<<0), /* High Level */ -} TC2_LUNFINTLVL_t; - -/* Low Byte Compare D Interrupt Level */ -typedef enum TC2_LCMPDINTLVL_enum -{ - TC2_LCMPDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ - TC2_LCMPDINTLVL_LO_gc = (0x01<<6), /* Low Level */ - TC2_LCMPDINTLVL_MED_gc = (0x02<<6), /* Medium Level */ - TC2_LCMPDINTLVL_HI_gc = (0x03<<6), /* High Level */ -} TC2_LCMPDINTLVL_t; - -/* Low Byte Compare C Interrupt Level */ -typedef enum TC2_LCMPCINTLVL_enum -{ - TC2_LCMPCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ - TC2_LCMPCINTLVL_LO_gc = (0x01<<4), /* Low Level */ - TC2_LCMPCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ - TC2_LCMPCINTLVL_HI_gc = (0x03<<4), /* High Level */ -} TC2_LCMPCINTLVL_t; - -/* Low Byte Compare B Interrupt Level */ -typedef enum TC2_LCMPBINTLVL_enum -{ - TC2_LCMPBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ - TC2_LCMPBINTLVL_LO_gc = (0x01<<2), /* Low Level */ - TC2_LCMPBINTLVL_MED_gc = (0x02<<2), /* Medium Level */ - TC2_LCMPBINTLVL_HI_gc = (0x03<<2), /* High Level */ -} TC2_LCMPBINTLVL_t; - -/* Low Byte Compare A Interrupt Level */ -typedef enum TC2_LCMPAINTLVL_enum -{ - TC2_LCMPAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - TC2_LCMPAINTLVL_LO_gc = (0x01<<0), /* Low Level */ - TC2_LCMPAINTLVL_MED_gc = (0x02<<0), /* Medium Level */ - TC2_LCMPAINTLVL_HI_gc = (0x03<<0), /* High Level */ -} TC2_LCMPAINTLVL_t; - -/* Timer/Counter Command */ -typedef enum TC2_CMD_enum -{ - TC2_CMD_NONE_gc = (0x00<<2), /* No Command */ - TC2_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ - TC2_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ -} TC2_CMD_t; - -/* Timer/Counter Command */ -typedef enum TC2_CMDEN_enum -{ - TC2_CMDEN_LOW_gc = (0x01<<0), /* Low Byte Timer/Counter */ - TC2_CMDEN_HIGH_gc = (0x02<<0), /* High Byte Timer/Counter */ - TC2_CMDEN_BOTH_gc = (0x03<<0), /* Both Low Byte and High Byte Timer/Counters */ -} TC2_CMDEN_t; - - -/* --------------------------------------------------------------------------- -AWEX - Timer/Counter Advanced Waveform Extension --------------------------------------------------------------------------- -*/ - -/* Advanced Waveform Extension */ -typedef struct AWEX_struct -{ - register8_t CTRL; /* Control Register */ - register8_t reserved_0x01; - register8_t FDEMASK; /* Fault Detection Event Mask */ - register8_t FDCTRL; /* Fault Detection Control Register */ - register8_t STATUS; /* Status Register */ - register8_t STATUSSET; /* Status Set Register */ - register8_t DTBOTH; /* Dead Time Both Sides */ - register8_t DTBOTHBUF; /* Dead Time Both Sides Buffer */ - register8_t DTLS; /* Dead Time Low Side */ - register8_t DTHS; /* Dead Time High Side */ - register8_t DTLSBUF; /* Dead Time Low Side Buffer */ - register8_t DTHSBUF; /* Dead Time High Side Buffer */ - register8_t OUTOVEN; /* Output Override Enable */ -} AWEX_t; - -/* Fault Detect Action */ -typedef enum AWEX_FDACT_enum -{ - AWEX_FDACT_NONE_gc = (0x00<<0), /* No Fault Protection */ - AWEX_FDACT_CLEAROE_gc = (0x01<<0), /* Clear Output Enable Bits */ - AWEX_FDACT_CLEARDIR_gc = (0x03<<0), /* Clear I/O Port Direction Bits */ -} AWEX_FDACT_t; - - -/* --------------------------------------------------------------------------- -HIRES - Timer/Counter High-Resolution Extension --------------------------------------------------------------------------- -*/ - -/* High-Resolution Extension */ -typedef struct HIRES_struct -{ - register8_t CTRLA; /* Control Register */ -} HIRES_t; - -/* High Resolution Enable */ -typedef enum HIRES_HREN_enum -{ - HIRES_HREN_NONE_gc = (0x00<<0), /* No Fault Protection */ - HIRES_HREN_TC0_gc = (0x01<<0), /* Enable High Resolution on Timer/Counter 0 */ - HIRES_HREN_TC1_gc = (0x02<<0), /* Enable High Resolution on Timer/Counter 1 */ - HIRES_HREN_BOTH_gc = (0x03<<0), /* Enable High Resolution both Timer/Counters */ -} HIRES_HREN_t; - - -/* --------------------------------------------------------------------------- -USART - Universal Asynchronous Receiver-Transmitter --------------------------------------------------------------------------- -*/ - -/* Universal Synchronous/Asynchronous Receiver/Transmitter */ -typedef struct USART_struct -{ - register8_t DATA; /* Data Register */ - register8_t STATUS; /* Status Register */ - register8_t reserved_0x02; - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t CTRLC; /* Control Register C */ - register8_t BAUDCTRLA; /* Baud Rate Control Register A */ - register8_t BAUDCTRLB; /* Baud Rate Control Register B */ -} USART_t; - -/* Receive Complete Interrupt level */ -typedef enum USART_RXCINTLVL_enum -{ - USART_RXCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ - USART_RXCINTLVL_LO_gc = (0x01<<4), /* Low Level */ - USART_RXCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ - USART_RXCINTLVL_HI_gc = (0x03<<4), /* High Level */ -} USART_RXCINTLVL_t; - -/* Transmit Complete Interrupt level */ -typedef enum USART_TXCINTLVL_enum -{ - USART_TXCINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ - USART_TXCINTLVL_LO_gc = (0x01<<2), /* Low Level */ - USART_TXCINTLVL_MED_gc = (0x02<<2), /* Medium Level */ - USART_TXCINTLVL_HI_gc = (0x03<<2), /* High Level */ -} USART_TXCINTLVL_t; - -/* Data Register Empty Interrupt level */ -typedef enum USART_DREINTLVL_enum -{ - USART_DREINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - USART_DREINTLVL_LO_gc = (0x01<<0), /* Low Level */ - USART_DREINTLVL_MED_gc = (0x02<<0), /* Medium Level */ - USART_DREINTLVL_HI_gc = (0x03<<0), /* High Level */ -} USART_DREINTLVL_t; - -/* Character Size */ -typedef enum USART_CHSIZE_enum -{ - USART_CHSIZE_5BIT_gc = (0x00<<0), /* Character size: 5 bit */ - USART_CHSIZE_6BIT_gc = (0x01<<0), /* Character size: 6 bit */ - USART_CHSIZE_7BIT_gc = (0x02<<0), /* Character size: 7 bit */ - USART_CHSIZE_8BIT_gc = (0x03<<0), /* Character size: 8 bit */ - USART_CHSIZE_9BIT_gc = (0x07<<0), /* Character size: 9 bit */ -} USART_CHSIZE_t; - -/* Communication Mode */ -typedef enum USART_CMODE_enum -{ - USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6), /* Asynchronous Mode */ - USART_CMODE_SYNCHRONOUS_gc = (0x01<<6), /* Synchronous Mode */ - USART_CMODE_IRDA_gc = (0x02<<6), /* IrDA Mode */ - USART_CMODE_MSPI_gc = (0x03<<6), /* Master SPI Mode */ -} USART_CMODE_t; - -/* Parity Mode */ -typedef enum USART_PMODE_enum -{ - USART_PMODE_DISABLED_gc = (0x00<<4), /* No Parity */ - USART_PMODE_EVEN_gc = (0x02<<4), /* Even Parity */ - USART_PMODE_ODD_gc = (0x03<<4), /* Odd Parity */ -} USART_PMODE_t; - - -/* --------------------------------------------------------------------------- -SPI - Serial Peripheral Interface --------------------------------------------------------------------------- -*/ - -/* Serial Peripheral Interface */ -typedef struct SPI_struct -{ - register8_t CTRL; /* Control Register */ - register8_t INTCTRL; /* Interrupt Control Register */ - register8_t STATUS; /* Status Register */ - register8_t DATA; /* Data Register */ -} SPI_t; - -/* SPI Mode */ -typedef enum SPI_MODE_enum -{ - SPI_MODE_0_gc = (0x00<<2), /* SPI Mode 0 */ - SPI_MODE_1_gc = (0x01<<2), /* SPI Mode 1 */ - SPI_MODE_2_gc = (0x02<<2), /* SPI Mode 2 */ - SPI_MODE_3_gc = (0x03<<2), /* SPI Mode 3 */ -} SPI_MODE_t; - -/* Prescaler setting */ -typedef enum SPI_PRESCALER_enum -{ - SPI_PRESCALER_DIV4_gc = (0x00<<0), /* System Clock / 4 */ - SPI_PRESCALER_DIV16_gc = (0x01<<0), /* System Clock / 16 */ - SPI_PRESCALER_DIV64_gc = (0x02<<0), /* System Clock / 64 */ - SPI_PRESCALER_DIV128_gc = (0x03<<0), /* System Clock / 128 */ -} SPI_PRESCALER_t; - -/* Interrupt level */ -typedef enum SPI_INTLVL_enum -{ - SPI_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - SPI_INTLVL_LO_gc = (0x01<<0), /* Low Level */ - SPI_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ - SPI_INTLVL_HI_gc = (0x03<<0), /* High Level */ -} SPI_INTLVL_t; - - -/* --------------------------------------------------------------------------- -IRCOM - IR Communication Module --------------------------------------------------------------------------- -*/ - -/* IR Communication Module */ -typedef struct IRCOM_struct -{ - register8_t CTRL; /* Control Register */ - register8_t TXPLCTRL; /* IrDA Transmitter Pulse Length Control Register */ - register8_t RXPLCTRL; /* IrDA Receiver Pulse Length Control Register */ -} IRCOM_t; - -/* Event channel selection */ -typedef enum IRDA_EVSEL_enum -{ - IRDA_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ - IRDA_EVSEL_0_gc = (0x08<<0), /* Event Channel 0 */ - IRDA_EVSEL_1_gc = (0x09<<0), /* Event Channel 1 */ - IRDA_EVSEL_2_gc = (0x0A<<0), /* Event Channel 2 */ - IRDA_EVSEL_3_gc = (0x0B<<0), /* Event Channel 3 */ -} IRDA_EVSEL_t; - - -/* --------------------------------------------------------------------------- -LCD - LCD Controller --------------------------------------------------------------------------- -*/ - -/* LCD Controller */ -typedef struct LCD_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t CTRLC; /* Control Register C */ - register8_t INTCTRL; /* Interrupt Enable Register */ - register8_t INTFLAG; /* Interrupt Flag Register */ - register8_t CTRLD; /* Control Register D */ - register8_t CTRLE; /* Control Register E */ - register8_t CTRLF; /* Control Register F */ - register8_t CTRLG; /* Control Register G */ - register8_t CTRLH; /* Control Register H */ - register8_t reserved_0x0A; - register8_t reserved_0x0B; - register8_t reserved_0x0C; - register8_t reserved_0x0D; - register8_t reserved_0x0E; - register8_t reserved_0x0F; - register8_t DATA0; /* LCD Data Register 0 */ - register8_t DATA1; /* LCD Data Register 1 */ - register8_t DATA2; /* LCD Data Register 2 */ - register8_t DATA3; /* LCD Data Register 3 */ - register8_t DATA4; /* LCD Data Register 4 */ - register8_t DATA5; /* LCD Data Register 5 */ - register8_t DATA6; /* LCD Data Register 6 */ - register8_t DATA7; /* LCD Data Register 7 */ - register8_t DATA8; /* LCD Data Register 8 */ - register8_t DATA9; /* LCD Data Register 9 */ - register8_t DATA10; /* LCD Data Register 10 */ - register8_t DATA11; /* LCD Data Register 11 */ - register8_t DATA12; /* LCD Data Register 12 */ - register8_t DATA13; /* LCD Data Register 13 */ - register8_t DATA14; /* LCD Data Register 14 */ - register8_t DATA15; /* LCD Data Register 15 */ - register8_t DATA16; /* LCD Data Register 16 */ - register8_t DATA17; /* LCD Data Register 17 */ - register8_t DATA18; /* LCD Data Register 18 */ - register8_t DATA19; /* LCD Data Register 19 */ -} LCD_t; - -/* LCD Blink Rate */ -typedef enum LCD_BLINKRATE_enum -{ - LCD_BLINKRATE_4Hz_gc = (0x00<<0), /* 4Hz Blink Rate */ - LCD_BLINKRATE_2Hz_gc = (0x01<<0), /* 2Hz Blink Rate */ - LCD_BLINKRATE_1Hz_gc = (0x02<<0), /* 1Hz Blink Rate */ - LCD_BLINKRATE_0Hz5_gc = (0x03<<0), /* 0.5Hz Blink Rate */ -} LCD_BLINKRATE_t; - -/* LCD Clock Divide */ -typedef enum LCD_CLKDIV_enum -{ - LCD_CLKDIV_DivBy1_gc = (0x00<<4), /* frame rate of 256 Hz */ - LCD_CLKDIV_DivBy2_gc = (0x01<<4), /* frame rate of 128 Hz */ - LCD_CLKDIV_DivBy3_gc = (0x02<<4), /* frame rate of 83.5 Hz */ - LCD_CLKDIV_DivBy4_gc = (0x03<<4), /* frame rate of 64 Hz */ - LCD_CLKDIV_DivBy5_gc = (0x04<<4), /* frame rate of 51.2 Hz */ - LCD_CLKDIV_DivBy6_gc = (0x05<<4), /* frame rate of 42.7 Hz */ - LCD_CLKDIV_DivBy7_gc = (0x06<<4), /* frame rate of 36.6 Hz */ - LCD_CLKDIV_DivBy8_gc = (0x07<<4), /* frame rate of 32 Hz */ -} LCD_CLKDIV_t; - -/* Duty Select */ -typedef enum LCD_DUTY_enum -{ - LCD_DUTY_1_4_gc = (0x00<<0), /* Duty=1/4, Bias=1/3, COM0:3 */ - LCD_DUTY_Static_gc = (0x01<<0), /* Duty=Static, Bias=Static, COM0 */ - LCD_DUTY_1_2_gc = (0x02<<0), /* Duty=1/2, Bias=1/3, COM0:1 */ - LCD_DUTY_1_3_gc = (0x03<<0), /* Duty=1/3, Bias=1/3, COM0:2 */ -} LCD_DUTY_t; - -/* LCD Prescaler Select */ -typedef enum LCD_PRESC_enum -{ - LCD_PRESC_8_gc = (0x00<<7), /* clk_lcd/8 */ - LCD_PRESC_16_gc = (0x01<<7), /* clk_lcd/16 */ -} LCD_PRESC_t; - -/* Type of Digit */ -typedef enum LCD_TDG_enum -{ - LCD_TDG_7S_3C_gc = (0x00<<6), /* 7-segment with 3 COMs */ - LCD_TDG_7S_4C_gc = (0x01<<6), /* 7-segment with 4 COMs */ - LCD_TDG_14S_4C_gc = (0x02<<6), /* 14-segment with 4 COMs */ - LCD_TDG_16S_3C_gc = (0x03<<6), /* 16-segment with 3 COMs */ -} LCD_TDG_t; - - -/* --------------------------------------------------------------------------- -FUSE - Fuses and Lockbits --------------------------------------------------------------------------- -*/ - -/* Fuses */ -typedef struct NVM_FUSES_struct -{ - register8_t FUSEBYTE0; /* JTAG User ID */ - register8_t FUSEBYTE1; /* Watchdog Configuration */ - register8_t FUSEBYTE2; /* Reset Configuration */ - register8_t reserved_0x03; - register8_t FUSEBYTE4; /* Start-up Configuration */ - register8_t FUSEBYTE5; /* EESAVE and BOD Level */ -} NVM_FUSES_t; - -/* Boot Loader Section Reset Vector */ -typedef enum BOOTRST_enum -{ - BOOTRST_BOOTLDR_gc = (0x00<<6), /* Boot Loader Reset */ - BOOTRST_APPLICATION_gc = (0x01<<6), /* Application Reset */ -} BOOTRST_t; - -/* Timer Oscillator pin location */ -typedef enum TOSCSEL_enum -{ - TOSCSEL_ALTERNATE_gc = (0x00<<5), /* TOSC1 / TOSC2 on separate pins */ - TOSCSEL_XTAL_gc = (0x01<<5), /* TOSC1 / TOSC2 shared with XTAL1 / XTAL2 */ -} TOSCSEL_t; - -/* BOD operation */ -typedef enum BOD_enum -{ - BOD_SAMPLED_gc = (0x01<<0), /* BOD enabled in sampled mode */ - BOD_CONTINUOUS_gc = (0x02<<0), /* BOD enabled continuously */ - BOD_DISABLED_gc = (0x03<<0), /* BOD Disabled */ -} BOD_t; - -/* BOD operation */ -typedef enum BODACT_enum -{ - BODACT_SAMPLED_gc = (0x01<<4), /* BOD enabled in sampled mode */ - BODACT_CONTINUOUS_gc = (0x02<<4), /* BOD enabled continuously */ - BODACT_DISABLED_gc = (0x03<<4), /* BOD Disabled */ -} BODACT_t; - -/* Watchdog (Window) Timeout Period */ -typedef enum WD_enum -{ - WD_8CLK_gc = (0x00<<4), /* 8 cycles (8ms @ 3.3V) */ - WD_16CLK_gc = (0x01<<4), /* 16 cycles (16ms @ 3.3V) */ - WD_32CLK_gc = (0x02<<4), /* 32 cycles (32ms @ 3.3V) */ - WD_64CLK_gc = (0x03<<4), /* 64 cycles (64ms @ 3.3V) */ - WD_128CLK_gc = (0x04<<4), /* 128 cycles (0.125s @ 3.3V) */ - WD_256CLK_gc = (0x05<<4), /* 256 cycles (0.25s @ 3.3V) */ - WD_512CLK_gc = (0x06<<4), /* 512 cycles (0.5s @ 3.3V) */ - WD_1KCLK_gc = (0x07<<4), /* 1K cycles (1s @ 3.3V) */ - WD_2KCLK_gc = (0x08<<4), /* 2K cycles (2s @ 3.3V) */ - WD_4KCLK_gc = (0x09<<4), /* 4K cycles (4s @ 3.3V) */ - WD_8KCLK_gc = (0x0A<<4), /* 8K cycles (8s @ 3.3V) */ -} WD_t; - -/* Watchdog (Window) Timeout Period */ -typedef enum WDP_enum -{ - WDP_8CLK_gc = (0x00<<0), /* 8 cycles (8ms @ 3.3V) */ - WDP_16CLK_gc = (0x01<<0), /* 16 cycles (16ms @ 3.3V) */ - WDP_32CLK_gc = (0x02<<0), /* 32 cycles (32ms @ 3.3V) */ - WDP_64CLK_gc = (0x03<<0), /* 64 cycles (64ms @ 3.3V) */ - WDP_128CLK_gc = (0x04<<0), /* 128 cycles (0.125s @ 3.3V) */ - WDP_256CLK_gc = (0x05<<0), /* 256 cycles (0.25s @ 3.3V) */ - WDP_512CLK_gc = (0x06<<0), /* 512 cycles (0.5s @ 3.3V) */ - WDP_1KCLK_gc = (0x07<<0), /* 1K cycles (1s @ 3.3V) */ - WDP_2KCLK_gc = (0x08<<0), /* 2K cycles (2s @ 3.3V) */ - WDP_4KCLK_gc = (0x09<<0), /* 4K cycles (4s @ 3.3V) */ - WDP_8KCLK_gc = (0x0A<<0), /* 8K cycles (8s @ 3.3V) */ -} WDP_t; - -/* Start-up Time */ -typedef enum SUT_enum -{ - SUT_0MS_gc = (0x03<<2), /* 0 ms */ - SUT_4MS_gc = (0x01<<2), /* 4 ms */ - SUT_64MS_gc = (0x00<<2), /* 64 ms */ -} SUT_t; - -/* Brownout Detection Voltage Level */ -typedef enum BODLVL_enum -{ - BODLVL_1V6_gc = (0x07<<0), /* 1.6 V */ - BODLVL_1V8_gc = (0x06<<0), /* 1.8 V */ - BODLVL_2V0_gc = (0x05<<0), /* 2.0 V */ - BODLVL_2V2_gc = (0x04<<0), /* 2.2 V */ - BODLVL_2V4_gc = (0x03<<0), /* 2.4 V */ - BODLVL_2V6_gc = (0x02<<0), /* 2.6 V */ - BODLVL_2V8_gc = (0x01<<0), /* 2.8 V */ - BODLVL_3V0_gc = (0x00<<0), /* 3.0 V */ -} BODLVL_t; - - -/* --------------------------------------------------------------------------- -LOCKBIT - Fuses and Lockbits --------------------------------------------------------------------------- -*/ - -/* Lock Bits */ -typedef struct NVM_LOCKBITS_struct -{ - register8_t LOCK_BITS; /* Lock Bits (Changed from LOCKBITS to avoid avr-libc collision) */ -} NVM_LOCKBITS_t; - -/* Boot lock bits - boot setcion */ -typedef enum FUSE_BLBB_enum -{ - FUSE_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ - FUSE_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ - FUSE_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ - FUSE_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ -} FUSE_BLBB_t; - -/* Boot lock bits - application section */ -typedef enum FUSE_BLBA_enum -{ - FUSE_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ - FUSE_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ - FUSE_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ - FUSE_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ -} FUSE_BLBA_t; - -/* Boot lock bits - application table section */ -typedef enum FUSE_BLBAT_enum -{ - FUSE_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ - FUSE_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ - FUSE_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ - FUSE_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ -} FUSE_BLBAT_t; - -/* Lock bits */ -typedef enum FUSE_LB_enum -{ - FUSE_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ - FUSE_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ - FUSE_LB_NOLOCK_gc = (0x03<<0), /* No locks */ -} FUSE_LB_t; - - -/* --------------------------------------------------------------------------- -SIGROW - Signature Row --------------------------------------------------------------------------- -*/ - -/* Production Signatures */ -typedef struct NVM_PROD_SIGNATURES_struct -{ - register8_t RCOSC2M; /* RCOSC 2 MHz Calibration Value B */ - register8_t RCOSC2MA; /* RCOSC 2 MHz Calibration Value A */ - register8_t RCOSC32K; /* RCOSC 32.768 kHz Calibration Value */ - register8_t RCOSC32M; /* RCOSC 32 MHz Calibration Value B */ - register8_t RCOSC32MA; /* RCOSC 32 MHz Calibration Value A */ - register8_t reserved_0x05; - register8_t reserved_0x06; - register8_t reserved_0x07; - register8_t LOTNUM0; /* Lot Number Byte 0, ASCII */ - register8_t LOTNUM1; /* Lot Number Byte 1, ASCII */ - register8_t LOTNUM2; /* Lot Number Byte 2, ASCII */ - register8_t LOTNUM3; /* Lot Number Byte 3, ASCII */ - register8_t LOTNUM4; /* Lot Number Byte 4, ASCII */ - register8_t LOTNUM5; /* Lot Number Byte 5, ASCII */ - register8_t reserved_0x0E; - register8_t reserved_0x0F; - register8_t WAFNUM; /* Wafer Number */ - register8_t reserved_0x11; - register8_t COORDX0; /* Wafer Coordinate X Byte 0 */ - register8_t COORDX1; /* Wafer Coordinate X Byte 1 */ - register8_t COORDY0; /* Wafer Coordinate Y Byte 0 */ - register8_t COORDY1; /* Wafer Coordinate Y Byte 1 */ - register8_t reserved_0x16; - register8_t reserved_0x17; - register8_t reserved_0x18; - register8_t reserved_0x19; - register8_t USBCAL0; /* USB Calibration Byte 0 */ - register8_t USBCAL1; /* USB Calibration Byte 1 */ - register8_t USBRCOSC; /* USB RCOSC Calibration Value B */ - register8_t USBRCOSCA; /* USB RCOSC Calibration Value A */ - register8_t reserved_0x1E; - register8_t reserved_0x1F; - register8_t ADCACAL0; /* ADCA Calibration Byte 0 */ - register8_t ADCACAL1; /* ADCA Calibration Byte 1 */ - register8_t reserved_0x22; - register8_t reserved_0x23; - register8_t ADCBCAL0; /* ADCB Calibration Byte 0 */ - register8_t ADCBCAL1; /* ADCB Calibration Byte 1 */ - register8_t reserved_0x26; - register8_t reserved_0x27; - register8_t reserved_0x28; - register8_t reserved_0x29; - register8_t reserved_0x2A; - register8_t reserved_0x2B; - register8_t reserved_0x2C; - register8_t reserved_0x2D; - register8_t TEMPSENSE0; /* Temperature Sensor Calibration Byte 0 */ - register8_t TEMPSENSE1; /* Temperature Sensor Calibration Byte 1 */ - register8_t reserved_0x30; - register8_t reserved_0x31; - register8_t reserved_0x32; - register8_t reserved_0x33; - register8_t reserved_0x34; - register8_t reserved_0x35; - register8_t reserved_0x36; - register8_t reserved_0x37; - register8_t reserved_0x38; - register8_t reserved_0x39; - register8_t reserved_0x3A; - register8_t reserved_0x3B; - register8_t reserved_0x3C; - register8_t reserved_0x3D; - register8_t reserved_0x3E; - register8_t reserved_0x3F; - register8_t reserved_0x40; - register8_t reserved_0x41; - register8_t reserved_0x42; - register8_t reserved_0x43; - register8_t reserved_0x44; - register8_t reserved_0x45; - register8_t reserved_0x46; - register8_t reserved_0x47; -} NVM_PROD_SIGNATURES_t; - -/* -========================================================================== -IO Module Instances. Mapped to memory. -========================================================================== -*/ - -#define VPORT0 (*(VPORT_t *) 0x0010) /* Virtual Port */ -#define VPORT1 (*(VPORT_t *) 0x0014) /* Virtual Port */ -#define VPORT2 (*(VPORT_t *) 0x0018) /* Virtual Port */ -#define VPORT3 (*(VPORT_t *) 0x001C) /* Virtual Port */ -#define OCD (*(OCD_t *) 0x002E) /* On-Chip Debug System */ -#define CLK (*(CLK_t *) 0x0040) /* Clock System */ -#define SLEEP (*(SLEEP_t *) 0x0048) /* Sleep Controller */ -#define OSC (*(OSC_t *) 0x0050) /* Oscillator */ -#define DFLLRC32M (*(DFLL_t *) 0x0060) /* DFLL */ -#define DFLLRC2M (*(DFLL_t *) 0x0068) /* DFLL */ -#define PR (*(PR_t *) 0x0070) /* Power Reduction */ -#define RST (*(RST_t *) 0x0078) /* Reset */ -#define WDT (*(WDT_t *) 0x0080) /* Watch-Dog Timer */ -#define MCU (*(MCU_t *) 0x0090) /* MCU Control */ -#define PMIC (*(PMIC_t *) 0x00A0) /* Programmable Multi-level Interrupt Controller */ -#define PORTCFG (*(PORTCFG_t *) 0x00B0) /* I/O port Configuration */ -#define AES (*(AES_t *) 0x00C0) /* AES Module */ -#define CRC (*(CRC_t *) 0x00D0) /* Cyclic Redundancy Checker */ -#define DMA (*(DMA_t *) 0x0100) /* DMA Controller */ -#define EVSYS (*(EVSYS_t *) 0x0180) /* Event System */ -#define NVM (*(NVM_t *) 0x01C0) /* Non-volatile Memory Controller */ -#define ADCA (*(ADC_t *) 0x0200) /* Analog-to-Digital Converter */ -#define ADCB (*(ADC_t *) 0x0240) /* Analog-to-Digital Converter */ -#define ACA (*(AC_t *) 0x0380) /* Analog Comparator */ -#define ACB (*(AC_t *) 0x0390) /* Analog Comparator */ -#define RTC (*(RTC_t *) 0x0400) /* Real-Time Counter */ -#define TWIC (*(TWI_t *) 0x0480) /* Two-Wire Interface */ -#define USB (*(USB_t *) 0x04C0) /* Universal Serial Bus */ -#define PORTA (*(PORT_t *) 0x0600) /* I/O Ports */ -#define PORTB (*(PORT_t *) 0x0620) /* I/O Ports */ -#define PORTC (*(PORT_t *) 0x0640) /* I/O Ports */ -#define PORTD (*(PORT_t *) 0x0660) /* I/O Ports */ -#define PORTE (*(PORT_t *) 0x0680) /* I/O Ports */ -#define PORTG (*(PORT_t *) 0x06C0) /* I/O Ports */ -#define PORTM (*(PORT_t *) 0x0760) /* I/O Ports */ -#define PORTR (*(PORT_t *) 0x07E0) /* I/O Ports */ -#define TCC0 (*(TC0_t *) 0x0800) /* 16-bit Timer/Counter 0 */ -#define TCC2 (*(TC2_t *) 0x0800) /* 16-bit Timer/Counter type 2 */ -#define TCC1 (*(TC1_t *) 0x0840) /* 16-bit Timer/Counter 1 */ -#define AWEXC (*(AWEX_t *) 0x0880) /* Advanced Waveform Extension */ -#define HIRESC (*(HIRES_t *) 0x0890) /* High-Resolution Extension */ -#define USARTC0 (*(USART_t *) 0x08A0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ -#define SPIC (*(SPI_t *) 0x08C0) /* Serial Peripheral Interface */ -#define IRCOM (*(IRCOM_t *) 0x08F8) /* IR Communication Module */ -#define TCE0 (*(TC0_t *) 0x0A00) /* 16-bit Timer/Counter 0 */ -#define TCE2 (*(TC2_t *) 0x0A00) /* 16-bit Timer/Counter type 2 */ -#define USARTE0 (*(USART_t *) 0x0AA0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ -#define LCD (*(LCD_t *) 0x0D00) /* LCD Controller */ - - -#endif /* !defined (__ASSEMBLER__) */ - - -/* ========== Flattened fully qualified IO register names ========== */ - -/* GPIO - General Purpose IO Registers */ -#define GPIO_GPIOR0 _SFR_MEM8(0x0000) -#define GPIO_GPIOR1 _SFR_MEM8(0x0001) -#define GPIO_GPIOR2 _SFR_MEM8(0x0002) -#define GPIO_GPIOR3 _SFR_MEM8(0x0003) - -/* Deprecated */ -#define GPIO_GPIO0 _SFR_MEM8(0x0000) -#define GPIO_GPIO1 _SFR_MEM8(0x0001) -#define GPIO_GPIO2 _SFR_MEM8(0x0002) -#define GPIO_GPIO3 _SFR_MEM8(0x0003) - -/* NVM_FUSES - Fuses */ -#define FUSE_FUSEBYTE0 _SFR_MEM8(0x0000) -#define FUSE_FUSEBYTE1 _SFR_MEM8(0x0001) -#define FUSE_FUSEBYTE2 _SFR_MEM8(0x0002) -#define FUSE_FUSEBYTE4 _SFR_MEM8(0x0004) -#define FUSE_FUSEBYTE5 _SFR_MEM8(0x0005) - -/* NVM_LOCKBITS - Lock Bits */ -#define LOCKBIT_LOCKBITS _SFR_MEM8(0x0000) - -/* NVM_PROD_SIGNATURES - Production Signatures */ -#define PRODSIGNATURES_RCOSC2M _SFR_MEM8(0x0000) -#define PRODSIGNATURES_RCOSC2MA _SFR_MEM8(0x0001) -#define PRODSIGNATURES_RCOSC32K _SFR_MEM8(0x0002) -#define PRODSIGNATURES_RCOSC32M _SFR_MEM8(0x0003) -#define PRODSIGNATURES_RCOSC32MA _SFR_MEM8(0x0004) -#define PRODSIGNATURES_LOTNUM0 _SFR_MEM8(0x0008) -#define PRODSIGNATURES_LOTNUM1 _SFR_MEM8(0x0009) -#define PRODSIGNATURES_LOTNUM2 _SFR_MEM8(0x000A) -#define PRODSIGNATURES_LOTNUM3 _SFR_MEM8(0x000B) -#define PRODSIGNATURES_LOTNUM4 _SFR_MEM8(0x000C) -#define PRODSIGNATURES_LOTNUM5 _SFR_MEM8(0x000D) -#define PRODSIGNATURES_WAFNUM _SFR_MEM8(0x0010) -#define PRODSIGNATURES_COORDX0 _SFR_MEM8(0x0012) -#define PRODSIGNATURES_COORDX1 _SFR_MEM8(0x0013) -#define PRODSIGNATURES_COORDY0 _SFR_MEM8(0x0014) -#define PRODSIGNATURES_COORDY1 _SFR_MEM8(0x0015) -#define PRODSIGNATURES_USBCAL0 _SFR_MEM8(0x001A) -#define PRODSIGNATURES_USBCAL1 _SFR_MEM8(0x001B) -#define PRODSIGNATURES_USBRCOSC _SFR_MEM8(0x001C) -#define PRODSIGNATURES_USBRCOSCA _SFR_MEM8(0x001D) -#define PRODSIGNATURES_ADCACAL0 _SFR_MEM8(0x0020) -#define PRODSIGNATURES_ADCACAL1 _SFR_MEM8(0x0021) -#define PRODSIGNATURES_ADCBCAL0 _SFR_MEM8(0x0024) -#define PRODSIGNATURES_ADCBCAL1 _SFR_MEM8(0x0025) -#define PRODSIGNATURES_TEMPSENSE0 _SFR_MEM8(0x002E) -#define PRODSIGNATURES_TEMPSENSE1 _SFR_MEM8(0x002F) - -/* VPORT - Virtual Port */ -#define VPORT0_DIR _SFR_MEM8(0x0010) -#define VPORT0_OUT _SFR_MEM8(0x0011) -#define VPORT0_IN _SFR_MEM8(0x0012) -#define VPORT0_INTFLAGS _SFR_MEM8(0x0013) - -/* VPORT - Virtual Port */ -#define VPORT1_DIR _SFR_MEM8(0x0014) -#define VPORT1_OUT _SFR_MEM8(0x0015) -#define VPORT1_IN _SFR_MEM8(0x0016) -#define VPORT1_INTFLAGS _SFR_MEM8(0x0017) - -/* VPORT - Virtual Port */ -#define VPORT2_DIR _SFR_MEM8(0x0018) -#define VPORT2_OUT _SFR_MEM8(0x0019) -#define VPORT2_IN _SFR_MEM8(0x001A) -#define VPORT2_INTFLAGS _SFR_MEM8(0x001B) - -/* VPORT - Virtual Port */ -#define VPORT3_DIR _SFR_MEM8(0x001C) -#define VPORT3_OUT _SFR_MEM8(0x001D) -#define VPORT3_IN _SFR_MEM8(0x001E) -#define VPORT3_INTFLAGS _SFR_MEM8(0x001F) - -/* OCD - On-Chip Debug System */ -#define OCD_OCDR0 _SFR_MEM8(0x002E) -#define OCD_OCDR1 _SFR_MEM8(0x002F) - -/* CPU - CPU registers */ -#define CPU_CCP _SFR_MEM8(0x0034) -#define CPU_RAMPD _SFR_MEM8(0x0038) -#define CPU_RAMPX _SFR_MEM8(0x0039) -#define CPU_RAMPY _SFR_MEM8(0x003A) -#define CPU_RAMPZ _SFR_MEM8(0x003B) -#define CPU_EIND _SFR_MEM8(0x003C) -#define CPU_SPL _SFR_MEM8(0x003D) -#define CPU_SPH _SFR_MEM8(0x003E) -#define CPU_SREG _SFR_MEM8(0x003F) - -/* CLK - Clock System */ -#define CLK_CTRL _SFR_MEM8(0x0040) -#define CLK_PSCTRL _SFR_MEM8(0x0041) -#define CLK_LOCK _SFR_MEM8(0x0042) -#define CLK_RTCCTRL _SFR_MEM8(0x0043) -#define CLK_USBCTRL _SFR_MEM8(0x0044) - -/* SLEEP - Sleep Controller */ -#define SLEEP_CTRL _SFR_MEM8(0x0048) - -/* OSC - Oscillator */ -#define OSC_CTRL _SFR_MEM8(0x0050) -#define OSC_STATUS _SFR_MEM8(0x0051) -#define OSC_XOSCCTRL _SFR_MEM8(0x0052) -#define OSC_XOSCFAIL _SFR_MEM8(0x0053) -#define OSC_RC32KCAL _SFR_MEM8(0x0054) -#define OSC_PLLCTRL _SFR_MEM8(0x0055) -#define OSC_DFLLCTRL _SFR_MEM8(0x0056) - -/* DFLL - DFLL */ -#define DFLLRC32M_CTRL _SFR_MEM8(0x0060) -#define DFLLRC32M_CALA _SFR_MEM8(0x0062) -#define DFLLRC32M_CALB _SFR_MEM8(0x0063) -#define DFLLRC32M_COMP0 _SFR_MEM8(0x0064) -#define DFLLRC32M_COMP1 _SFR_MEM8(0x0065) -#define DFLLRC32M_COMP2 _SFR_MEM8(0x0066) - -/* DFLL - DFLL */ -#define DFLLRC2M_CTRL _SFR_MEM8(0x0068) -#define DFLLRC2M_CALA _SFR_MEM8(0x006A) -#define DFLLRC2M_CALB _SFR_MEM8(0x006B) -#define DFLLRC2M_COMP0 _SFR_MEM8(0x006C) -#define DFLLRC2M_COMP1 _SFR_MEM8(0x006D) -#define DFLLRC2M_COMP2 _SFR_MEM8(0x006E) - -/* PR - Power Reduction */ -#define PR_PRGEN _SFR_MEM8(0x0070) -#define PR_PRPA _SFR_MEM8(0x0071) -#define PR_PRPB _SFR_MEM8(0x0072) -#define PR_PRPC _SFR_MEM8(0x0073) -#define PR_PRPE _SFR_MEM8(0x0075) - -/* RST - Reset */ -#define RST_STATUS _SFR_MEM8(0x0078) -#define RST_CTRL _SFR_MEM8(0x0079) - -/* WDT - Watch-Dog Timer */ -#define WDT_CTRL _SFR_MEM8(0x0080) -#define WDT_WINCTRL _SFR_MEM8(0x0081) -#define WDT_STATUS _SFR_MEM8(0x0082) - -/* MCU - MCU Control */ -#define MCU_DEVID0 _SFR_MEM8(0x0090) -#define MCU_DEVID1 _SFR_MEM8(0x0091) -#define MCU_DEVID2 _SFR_MEM8(0x0092) -#define MCU_REVID _SFR_MEM8(0x0093) -#define MCU_JTAGUID _SFR_MEM8(0x0094) -#define MCU_MCUCR _SFR_MEM8(0x0096) -#define MCU_ANAINIT _SFR_MEM8(0x0097) -#define MCU_EVSYSLOCK _SFR_MEM8(0x0098) -#define MCU_AWEXLOCK _SFR_MEM8(0x0099) - -/* PMIC - Programmable Multi-level Interrupt Controller */ -#define PMIC_STATUS _SFR_MEM8(0x00A0) -#define PMIC_INTPRI _SFR_MEM8(0x00A1) -#define PMIC_CTRL _SFR_MEM8(0x00A2) - -/* PORTCFG - I/O port Configuration */ -#define PORTCFG_MPCMASK _SFR_MEM8(0x00B0) -#define PORTCFG_VPCTRLA _SFR_MEM8(0x00B2) -#define PORTCFG_VPCTRLB _SFR_MEM8(0x00B3) -#define PORTCFG_CLKEVOUT _SFR_MEM8(0x00B4) -#define PORTCFG_EVOUTSEL _SFR_MEM8(0x00B6) - -/* AES - AES Module */ -#define AES_CTRL _SFR_MEM8(0x00C0) -#define AES_STATUS _SFR_MEM8(0x00C1) -#define AES_STATE _SFR_MEM8(0x00C2) -#define AES_KEY _SFR_MEM8(0x00C3) -#define AES_INTCTRL _SFR_MEM8(0x00C4) - -/* CRC - Cyclic Redundancy Checker */ -#define CRC_CTRL _SFR_MEM8(0x00D0) -#define CRC_STATUS _SFR_MEM8(0x00D1) -#define CRC_DATAIN _SFR_MEM8(0x00D3) -#define CRC_CHECKSUM0 _SFR_MEM8(0x00D4) -#define CRC_CHECKSUM1 _SFR_MEM8(0x00D5) -#define CRC_CHECKSUM2 _SFR_MEM8(0x00D6) -#define CRC_CHECKSUM3 _SFR_MEM8(0x00D7) - -/* DMA - DMA Controller */ -#define DMA_CTRL _SFR_MEM8(0x0100) -#define DMA_INTFLAGS _SFR_MEM8(0x0103) -#define DMA_STATUS _SFR_MEM8(0x0104) -#define DMA_TEMP _SFR_MEM16(0x0106) -#define DMA_CH0_CTRLA _SFR_MEM8(0x0110) -#define DMA_CH0_CTRLB _SFR_MEM8(0x0111) -#define DMA_CH0_ADDRCTRL _SFR_MEM8(0x0112) -#define DMA_CH0_TRIGSRC _SFR_MEM8(0x0113) -#define DMA_CH0_TRFCNT _SFR_MEM16(0x0114) -#define DMA_CH0_REPCNT _SFR_MEM8(0x0116) -#define DMA_CH0_SRCADDR0 _SFR_MEM8(0x0118) -#define DMA_CH0_SRCADDR1 _SFR_MEM8(0x0119) -#define DMA_CH0_DESTADDR0 _SFR_MEM8(0x011C) -#define DMA_CH0_DESTADDR1 _SFR_MEM8(0x011D) -#define DMA_CH1_CTRLA _SFR_MEM8(0x0120) -#define DMA_CH1_CTRLB _SFR_MEM8(0x0121) -#define DMA_CH1_ADDRCTRL _SFR_MEM8(0x0122) -#define DMA_CH1_TRIGSRC _SFR_MEM8(0x0123) -#define DMA_CH1_TRFCNT _SFR_MEM16(0x0124) -#define DMA_CH1_REPCNT _SFR_MEM8(0x0126) -#define DMA_CH1_SRCADDR0 _SFR_MEM8(0x0128) -#define DMA_CH1_SRCADDR1 _SFR_MEM8(0x0129) -#define DMA_CH1_DESTADDR0 _SFR_MEM8(0x012C) -#define DMA_CH1_DESTADDR1 _SFR_MEM8(0x012D) - -/* EVSYS - Event System */ -#define EVSYS_CH0MUX _SFR_MEM8(0x0180) -#define EVSYS_CH1MUX _SFR_MEM8(0x0181) -#define EVSYS_CH2MUX _SFR_MEM8(0x0182) -#define EVSYS_CH3MUX _SFR_MEM8(0x0183) -#define EVSYS_CH0CTRL _SFR_MEM8(0x0188) -#define EVSYS_CH1CTRL _SFR_MEM8(0x0189) -#define EVSYS_CH2CTRL _SFR_MEM8(0x018A) -#define EVSYS_CH3CTRL _SFR_MEM8(0x018B) -#define EVSYS_STROBE _SFR_MEM8(0x0190) -#define EVSYS_DATA _SFR_MEM8(0x0191) - -/* NVM - Non-volatile Memory Controller */ -#define NVM_ADDR0 _SFR_MEM8(0x01C0) -#define NVM_ADDR1 _SFR_MEM8(0x01C1) -#define NVM_ADDR2 _SFR_MEM8(0x01C2) -#define NVM_DATA0 _SFR_MEM8(0x01C4) -#define NVM_DATA1 _SFR_MEM8(0x01C5) -#define NVM_DATA2 _SFR_MEM8(0x01C6) -#define NVM_CMD _SFR_MEM8(0x01CA) -#define NVM_CTRLA _SFR_MEM8(0x01CB) -#define NVM_CTRLB _SFR_MEM8(0x01CC) -#define NVM_INTCTRL _SFR_MEM8(0x01CD) -#define NVM_STATUS _SFR_MEM8(0x01CF) -#define NVM_LOCKBITS _SFR_MEM8(0x01D0) - -/* ADC - Analog-to-Digital Converter */ -#define ADCA_CTRLA _SFR_MEM8(0x0200) -#define ADCA_CTRLB _SFR_MEM8(0x0201) -#define ADCA_REFCTRL _SFR_MEM8(0x0202) -#define ADCA_EVCTRL _SFR_MEM8(0x0203) -#define ADCA_PRESCALER _SFR_MEM8(0x0204) -#define ADCA_INTFLAGS _SFR_MEM8(0x0206) -#define ADCA_TEMP _SFR_MEM8(0x0207) -#define ADCA_SAMPCTRL _SFR_MEM8(0x0208) -#define ADCA_CAL _SFR_MEM16(0x020C) -#define ADCA_CH0RES _SFR_MEM16(0x0210) -#define ADCA_CMP _SFR_MEM16(0x0218) -#define ADCA_CH0_CTRL _SFR_MEM8(0x0220) -#define ADCA_CH0_MUXCTRL _SFR_MEM8(0x0221) -#define ADCA_CH0_INTCTRL _SFR_MEM8(0x0222) -#define ADCA_CH0_INTFLAGS _SFR_MEM8(0x0223) -#define ADCA_CH0_RES _SFR_MEM16(0x0224) -#define ADCA_CH0_SCAN _SFR_MEM8(0x0226) - -/* ADC - Analog-to-Digital Converter */ -#define ADCB_CTRLA _SFR_MEM8(0x0240) -#define ADCB_CTRLB _SFR_MEM8(0x0241) -#define ADCB_REFCTRL _SFR_MEM8(0x0242) -#define ADCB_EVCTRL _SFR_MEM8(0x0243) -#define ADCB_PRESCALER _SFR_MEM8(0x0244) -#define ADCB_INTFLAGS _SFR_MEM8(0x0246) -#define ADCB_TEMP _SFR_MEM8(0x0247) -#define ADCB_SAMPCTRL _SFR_MEM8(0x0248) -#define ADCB_CAL _SFR_MEM16(0x024C) -#define ADCB_CH0RES _SFR_MEM16(0x0250) -#define ADCB_CMP _SFR_MEM16(0x0258) -#define ADCB_CH0_CTRL _SFR_MEM8(0x0260) -#define ADCB_CH0_MUXCTRL _SFR_MEM8(0x0261) -#define ADCB_CH0_INTCTRL _SFR_MEM8(0x0262) -#define ADCB_CH0_INTFLAGS _SFR_MEM8(0x0263) -#define ADCB_CH0_RES _SFR_MEM16(0x0264) -#define ADCB_CH0_SCAN _SFR_MEM8(0x0266) - -/* AC - Analog Comparator */ -#define ACA_AC0CTRL _SFR_MEM8(0x0380) -#define ACA_AC1CTRL _SFR_MEM8(0x0381) -#define ACA_AC0MUXCTRL _SFR_MEM8(0x0382) -#define ACA_AC1MUXCTRL _SFR_MEM8(0x0383) -#define ACA_CTRLA _SFR_MEM8(0x0384) -#define ACA_CTRLB _SFR_MEM8(0x0385) -#define ACA_WINCTRL _SFR_MEM8(0x0386) -#define ACA_STATUS _SFR_MEM8(0x0387) -#define ACA_CURRCTRL _SFR_MEM8(0x0388) -#define ACA_CURRCALIB _SFR_MEM8(0x0389) - -/* AC - Analog Comparator */ -#define ACB_AC0CTRL _SFR_MEM8(0x0390) -#define ACB_AC1CTRL _SFR_MEM8(0x0391) -#define ACB_AC0MUXCTRL _SFR_MEM8(0x0392) -#define ACB_AC1MUXCTRL _SFR_MEM8(0x0393) -#define ACB_CTRLA _SFR_MEM8(0x0394) -#define ACB_CTRLB _SFR_MEM8(0x0395) -#define ACB_WINCTRL _SFR_MEM8(0x0396) -#define ACB_STATUS _SFR_MEM8(0x0397) -#define ACB_CURRCTRL _SFR_MEM8(0x0398) -#define ACB_CURRCALIB _SFR_MEM8(0x0399) - -/* RTC - Real-Time Counter */ -#define RTC_CTRL _SFR_MEM8(0x0400) -#define RTC_STATUS _SFR_MEM8(0x0401) -#define RTC_INTCTRL _SFR_MEM8(0x0402) -#define RTC_INTFLAGS _SFR_MEM8(0x0403) -#define RTC_TEMP _SFR_MEM8(0x0404) -#define RTC_CNT _SFR_MEM16(0x0408) -#define RTC_PER _SFR_MEM16(0x040A) -#define RTC_COMP _SFR_MEM16(0x040C) - -/* TWI - Two-Wire Interface */ -#define TWIC_CTRL _SFR_MEM8(0x0480) -#define TWIC_MASTER_CTRLA _SFR_MEM8(0x0481) -#define TWIC_MASTER_CTRLB _SFR_MEM8(0x0482) -#define TWIC_MASTER_CTRLC _SFR_MEM8(0x0483) -#define TWIC_MASTER_STATUS _SFR_MEM8(0x0484) -#define TWIC_MASTER_BAUD _SFR_MEM8(0x0485) -#define TWIC_MASTER_ADDR _SFR_MEM8(0x0486) -#define TWIC_MASTER_DATA _SFR_MEM8(0x0487) -#define TWIC_SLAVE_CTRLA _SFR_MEM8(0x0488) -#define TWIC_SLAVE_CTRLB _SFR_MEM8(0x0489) -#define TWIC_SLAVE_STATUS _SFR_MEM8(0x048A) -#define TWIC_SLAVE_ADDR _SFR_MEM8(0x048B) -#define TWIC_SLAVE_DATA _SFR_MEM8(0x048C) -#define TWIC_SLAVE_ADDRMASK _SFR_MEM8(0x048D) - -/* USB - Universal Serial Bus */ -#define USB_CTRLA _SFR_MEM8(0x04C0) -#define USB_CTRLB _SFR_MEM8(0x04C1) -#define USB_STATUS _SFR_MEM8(0x04C2) -#define USB_ADDR _SFR_MEM8(0x04C3) -#define USB_FIFOWP _SFR_MEM8(0x04C4) -#define USB_FIFORP _SFR_MEM8(0x04C5) -#define USB_EPPTR _SFR_MEM16(0x04C6) -#define USB_INTCTRLA _SFR_MEM8(0x04C8) -#define USB_INTCTRLB _SFR_MEM8(0x04C9) -#define USB_INTFLAGSACLR _SFR_MEM8(0x04CA) -#define USB_INTFLAGSASET _SFR_MEM8(0x04CB) -#define USB_INTFLAGSBCLR _SFR_MEM8(0x04CC) -#define USB_INTFLAGSBSET _SFR_MEM8(0x04CD) -#define USB_CAL0 _SFR_MEM8(0x04FA) -#define USB_CAL1 _SFR_MEM8(0x04FB) - -/* PORT - I/O Ports */ -#define PORTA_DIR _SFR_MEM8(0x0600) -#define PORTA_DIRSET _SFR_MEM8(0x0601) -#define PORTA_DIRCLR _SFR_MEM8(0x0602) -#define PORTA_DIRTGL _SFR_MEM8(0x0603) -#define PORTA_OUT _SFR_MEM8(0x0604) -#define PORTA_OUTSET _SFR_MEM8(0x0605) -#define PORTA_OUTCLR _SFR_MEM8(0x0606) -#define PORTA_OUTTGL _SFR_MEM8(0x0607) -#define PORTA_IN _SFR_MEM8(0x0608) -#define PORTA_INTCTRL _SFR_MEM8(0x0609) -#define PORTA_INT0MASK _SFR_MEM8(0x060A) -#define PORTA_INT1MASK _SFR_MEM8(0x060B) -#define PORTA_INTFLAGS _SFR_MEM8(0x060C) -#define PORTA_REMAP _SFR_MEM8(0x060E) -#define PORTA_PIN0CTRL _SFR_MEM8(0x0610) -#define PORTA_PIN1CTRL _SFR_MEM8(0x0611) -#define PORTA_PIN2CTRL _SFR_MEM8(0x0612) -#define PORTA_PIN3CTRL _SFR_MEM8(0x0613) -#define PORTA_PIN4CTRL _SFR_MEM8(0x0614) -#define PORTA_PIN5CTRL _SFR_MEM8(0x0615) -#define PORTA_PIN6CTRL _SFR_MEM8(0x0616) -#define PORTA_PIN7CTRL _SFR_MEM8(0x0617) - -/* PORT - I/O Ports */ -#define PORTB_DIR _SFR_MEM8(0x0620) -#define PORTB_DIRSET _SFR_MEM8(0x0621) -#define PORTB_DIRCLR _SFR_MEM8(0x0622) -#define PORTB_DIRTGL _SFR_MEM8(0x0623) -#define PORTB_OUT _SFR_MEM8(0x0624) -#define PORTB_OUTSET _SFR_MEM8(0x0625) -#define PORTB_OUTCLR _SFR_MEM8(0x0626) -#define PORTB_OUTTGL _SFR_MEM8(0x0627) -#define PORTB_IN _SFR_MEM8(0x0628) -#define PORTB_INTCTRL _SFR_MEM8(0x0629) -#define PORTB_INT0MASK _SFR_MEM8(0x062A) -#define PORTB_INT1MASK _SFR_MEM8(0x062B) -#define PORTB_INTFLAGS _SFR_MEM8(0x062C) -#define PORTB_REMAP _SFR_MEM8(0x062E) -#define PORTB_PIN0CTRL _SFR_MEM8(0x0630) -#define PORTB_PIN1CTRL _SFR_MEM8(0x0631) -#define PORTB_PIN2CTRL _SFR_MEM8(0x0632) -#define PORTB_PIN3CTRL _SFR_MEM8(0x0633) -#define PORTB_PIN4CTRL _SFR_MEM8(0x0634) -#define PORTB_PIN5CTRL _SFR_MEM8(0x0635) -#define PORTB_PIN6CTRL _SFR_MEM8(0x0636) -#define PORTB_PIN7CTRL _SFR_MEM8(0x0637) - -/* PORT - I/O Ports */ -#define PORTC_DIR _SFR_MEM8(0x0640) -#define PORTC_DIRSET _SFR_MEM8(0x0641) -#define PORTC_DIRCLR _SFR_MEM8(0x0642) -#define PORTC_DIRTGL _SFR_MEM8(0x0643) -#define PORTC_OUT _SFR_MEM8(0x0644) -#define PORTC_OUTSET _SFR_MEM8(0x0645) -#define PORTC_OUTCLR _SFR_MEM8(0x0646) -#define PORTC_OUTTGL _SFR_MEM8(0x0647) -#define PORTC_IN _SFR_MEM8(0x0648) -#define PORTC_INTCTRL _SFR_MEM8(0x0649) -#define PORTC_INT0MASK _SFR_MEM8(0x064A) -#define PORTC_INT1MASK _SFR_MEM8(0x064B) -#define PORTC_INTFLAGS _SFR_MEM8(0x064C) -#define PORTC_REMAP _SFR_MEM8(0x064E) -#define PORTC_PIN0CTRL _SFR_MEM8(0x0650) -#define PORTC_PIN1CTRL _SFR_MEM8(0x0651) -#define PORTC_PIN2CTRL _SFR_MEM8(0x0652) -#define PORTC_PIN3CTRL _SFR_MEM8(0x0653) -#define PORTC_PIN4CTRL _SFR_MEM8(0x0654) -#define PORTC_PIN5CTRL _SFR_MEM8(0x0655) -#define PORTC_PIN6CTRL _SFR_MEM8(0x0656) -#define PORTC_PIN7CTRL _SFR_MEM8(0x0657) - -/* PORT - I/O Ports */ -#define PORTD_DIR _SFR_MEM8(0x0660) -#define PORTD_DIRSET _SFR_MEM8(0x0661) -#define PORTD_DIRCLR _SFR_MEM8(0x0662) -#define PORTD_DIRTGL _SFR_MEM8(0x0663) -#define PORTD_OUT _SFR_MEM8(0x0664) -#define PORTD_OUTSET _SFR_MEM8(0x0665) -#define PORTD_OUTCLR _SFR_MEM8(0x0666) -#define PORTD_OUTTGL _SFR_MEM8(0x0667) -#define PORTD_IN _SFR_MEM8(0x0668) -#define PORTD_INTCTRL _SFR_MEM8(0x0669) -#define PORTD_INT0MASK _SFR_MEM8(0x066A) -#define PORTD_INT1MASK _SFR_MEM8(0x066B) -#define PORTD_INTFLAGS _SFR_MEM8(0x066C) -#define PORTD_REMAP _SFR_MEM8(0x066E) -#define PORTD_PIN0CTRL _SFR_MEM8(0x0670) -#define PORTD_PIN1CTRL _SFR_MEM8(0x0671) -#define PORTD_PIN2CTRL _SFR_MEM8(0x0672) -#define PORTD_PIN3CTRL _SFR_MEM8(0x0673) -#define PORTD_PIN4CTRL _SFR_MEM8(0x0674) -#define PORTD_PIN5CTRL _SFR_MEM8(0x0675) -#define PORTD_PIN6CTRL _SFR_MEM8(0x0676) -#define PORTD_PIN7CTRL _SFR_MEM8(0x0677) - -/* PORT - I/O Ports */ -#define PORTE_DIR _SFR_MEM8(0x0680) -#define PORTE_DIRSET _SFR_MEM8(0x0681) -#define PORTE_DIRCLR _SFR_MEM8(0x0682) -#define PORTE_DIRTGL _SFR_MEM8(0x0683) -#define PORTE_OUT _SFR_MEM8(0x0684) -#define PORTE_OUTSET _SFR_MEM8(0x0685) -#define PORTE_OUTCLR _SFR_MEM8(0x0686) -#define PORTE_OUTTGL _SFR_MEM8(0x0687) -#define PORTE_IN _SFR_MEM8(0x0688) -#define PORTE_INTCTRL _SFR_MEM8(0x0689) -#define PORTE_INT0MASK _SFR_MEM8(0x068A) -#define PORTE_INT1MASK _SFR_MEM8(0x068B) -#define PORTE_INTFLAGS _SFR_MEM8(0x068C) -#define PORTE_REMAP _SFR_MEM8(0x068E) -#define PORTE_PIN0CTRL _SFR_MEM8(0x0690) -#define PORTE_PIN1CTRL _SFR_MEM8(0x0691) -#define PORTE_PIN2CTRL _SFR_MEM8(0x0692) -#define PORTE_PIN3CTRL _SFR_MEM8(0x0693) -#define PORTE_PIN4CTRL _SFR_MEM8(0x0694) -#define PORTE_PIN5CTRL _SFR_MEM8(0x0695) -#define PORTE_PIN6CTRL _SFR_MEM8(0x0696) -#define PORTE_PIN7CTRL _SFR_MEM8(0x0697) - -/* PORT - I/O Ports */ -#define PORTG_DIR _SFR_MEM8(0x06C0) -#define PORTG_DIRSET _SFR_MEM8(0x06C1) -#define PORTG_DIRCLR _SFR_MEM8(0x06C2) -#define PORTG_DIRTGL _SFR_MEM8(0x06C3) -#define PORTG_OUT _SFR_MEM8(0x06C4) -#define PORTG_OUTSET _SFR_MEM8(0x06C5) -#define PORTG_OUTCLR _SFR_MEM8(0x06C6) -#define PORTG_OUTTGL _SFR_MEM8(0x06C7) -#define PORTG_IN _SFR_MEM8(0x06C8) -#define PORTG_INTCTRL _SFR_MEM8(0x06C9) -#define PORTG_INT0MASK _SFR_MEM8(0x06CA) -#define PORTG_INT1MASK _SFR_MEM8(0x06CB) -#define PORTG_INTFLAGS _SFR_MEM8(0x06CC) -#define PORTG_REMAP _SFR_MEM8(0x06CE) -#define PORTG_PIN0CTRL _SFR_MEM8(0x06D0) -#define PORTG_PIN1CTRL _SFR_MEM8(0x06D1) -#define PORTG_PIN2CTRL _SFR_MEM8(0x06D2) -#define PORTG_PIN3CTRL _SFR_MEM8(0x06D3) -#define PORTG_PIN4CTRL _SFR_MEM8(0x06D4) -#define PORTG_PIN5CTRL _SFR_MEM8(0x06D5) -#define PORTG_PIN6CTRL _SFR_MEM8(0x06D6) -#define PORTG_PIN7CTRL _SFR_MEM8(0x06D7) - -/* PORT - I/O Ports */ -#define PORTM_DIR _SFR_MEM8(0x0760) -#define PORTM_DIRSET _SFR_MEM8(0x0761) -#define PORTM_DIRCLR _SFR_MEM8(0x0762) -#define PORTM_DIRTGL _SFR_MEM8(0x0763) -#define PORTM_OUT _SFR_MEM8(0x0764) -#define PORTM_OUTSET _SFR_MEM8(0x0765) -#define PORTM_OUTCLR _SFR_MEM8(0x0766) -#define PORTM_OUTTGL _SFR_MEM8(0x0767) -#define PORTM_IN _SFR_MEM8(0x0768) -#define PORTM_INTCTRL _SFR_MEM8(0x0769) -#define PORTM_INT0MASK _SFR_MEM8(0x076A) -#define PORTM_INT1MASK _SFR_MEM8(0x076B) -#define PORTM_INTFLAGS _SFR_MEM8(0x076C) -#define PORTM_REMAP _SFR_MEM8(0x076E) -#define PORTM_PIN0CTRL _SFR_MEM8(0x0770) -#define PORTM_PIN1CTRL _SFR_MEM8(0x0771) -#define PORTM_PIN2CTRL _SFR_MEM8(0x0772) -#define PORTM_PIN3CTRL _SFR_MEM8(0x0773) -#define PORTM_PIN4CTRL _SFR_MEM8(0x0774) -#define PORTM_PIN5CTRL _SFR_MEM8(0x0775) -#define PORTM_PIN6CTRL _SFR_MEM8(0x0776) -#define PORTM_PIN7CTRL _SFR_MEM8(0x0777) - -/* PORT - I/O Ports */ -#define PORTR_DIR _SFR_MEM8(0x07E0) -#define PORTR_DIRSET _SFR_MEM8(0x07E1) -#define PORTR_DIRCLR _SFR_MEM8(0x07E2) -#define PORTR_DIRTGL _SFR_MEM8(0x07E3) -#define PORTR_OUT _SFR_MEM8(0x07E4) -#define PORTR_OUTSET _SFR_MEM8(0x07E5) -#define PORTR_OUTCLR _SFR_MEM8(0x07E6) -#define PORTR_OUTTGL _SFR_MEM8(0x07E7) -#define PORTR_IN _SFR_MEM8(0x07E8) -#define PORTR_INTCTRL _SFR_MEM8(0x07E9) -#define PORTR_INT0MASK _SFR_MEM8(0x07EA) -#define PORTR_INT1MASK _SFR_MEM8(0x07EB) -#define PORTR_INTFLAGS _SFR_MEM8(0x07EC) -#define PORTR_REMAP _SFR_MEM8(0x07EE) -#define PORTR_PIN0CTRL _SFR_MEM8(0x07F0) -#define PORTR_PIN1CTRL _SFR_MEM8(0x07F1) -#define PORTR_PIN2CTRL _SFR_MEM8(0x07F2) -#define PORTR_PIN3CTRL _SFR_MEM8(0x07F3) -#define PORTR_PIN4CTRL _SFR_MEM8(0x07F4) -#define PORTR_PIN5CTRL _SFR_MEM8(0x07F5) -#define PORTR_PIN6CTRL _SFR_MEM8(0x07F6) -#define PORTR_PIN7CTRL _SFR_MEM8(0x07F7) - -/* TC0 - 16-bit Timer/Counter 0 */ -#define TCC0_CTRLA _SFR_MEM8(0x0800) -#define TCC0_CTRLB _SFR_MEM8(0x0801) -#define TCC0_CTRLC _SFR_MEM8(0x0802) -#define TCC0_CTRLD _SFR_MEM8(0x0803) -#define TCC0_CTRLE _SFR_MEM8(0x0804) -#define TCC0_INTCTRLA _SFR_MEM8(0x0806) -#define TCC0_INTCTRLB _SFR_MEM8(0x0807) -#define TCC0_CTRLFCLR _SFR_MEM8(0x0808) -#define TCC0_CTRLFSET _SFR_MEM8(0x0809) -#define TCC0_CTRLGCLR _SFR_MEM8(0x080A) -#define TCC0_CTRLGSET _SFR_MEM8(0x080B) -#define TCC0_INTFLAGS _SFR_MEM8(0x080C) -#define TCC0_TEMP _SFR_MEM8(0x080F) -#define TCC0_CNT _SFR_MEM16(0x0820) -#define TCC0_PER _SFR_MEM16(0x0826) -#define TCC0_CCA _SFR_MEM16(0x0828) -#define TCC0_CCB _SFR_MEM16(0x082A) -#define TCC0_CCC _SFR_MEM16(0x082C) -#define TCC0_CCD _SFR_MEM16(0x082E) -#define TCC0_PERBUF _SFR_MEM16(0x0836) -#define TCC0_CCABUF _SFR_MEM16(0x0838) -#define TCC0_CCBBUF _SFR_MEM16(0x083A) -#define TCC0_CCCBUF _SFR_MEM16(0x083C) -#define TCC0_CCDBUF _SFR_MEM16(0x083E) - -/* TC2 - 16-bit Timer/Counter type 2 */ -#define TCC2_CTRLA _SFR_MEM8(0x0800) -#define TCC2_CTRLB _SFR_MEM8(0x0801) -#define TCC2_CTRLC _SFR_MEM8(0x0802) -#define TCC2_CTRLE _SFR_MEM8(0x0804) -#define TCC2_INTCTRLA _SFR_MEM8(0x0806) -#define TCC2_INTCTRLB _SFR_MEM8(0x0807) -#define TCC2_CTRLF _SFR_MEM8(0x0809) -#define TCC2_INTFLAGS _SFR_MEM8(0x080C) -#define TCC2_LCNT _SFR_MEM8(0x0820) -#define TCC2_HCNT _SFR_MEM8(0x0821) -#define TCC2_LPER _SFR_MEM8(0x0826) -#define TCC2_HPER _SFR_MEM8(0x0827) -#define TCC2_LCMPA _SFR_MEM8(0x0828) -#define TCC2_HCMPA _SFR_MEM8(0x0829) -#define TCC2_LCMPB _SFR_MEM8(0x082A) -#define TCC2_HCMPB _SFR_MEM8(0x082B) -#define TCC2_LCMPC _SFR_MEM8(0x082C) -#define TCC2_HCMPC _SFR_MEM8(0x082D) -#define TCC2_LCMPD _SFR_MEM8(0x082E) -#define TCC2_HCMPD _SFR_MEM8(0x082F) - -/* TC1 - 16-bit Timer/Counter 1 */ -#define TCC1_CTRLA _SFR_MEM8(0x0840) -#define TCC1_CTRLB _SFR_MEM8(0x0841) -#define TCC1_CTRLC _SFR_MEM8(0x0842) -#define TCC1_CTRLD _SFR_MEM8(0x0843) -#define TCC1_CTRLE _SFR_MEM8(0x0844) -#define TCC1_INTCTRLA _SFR_MEM8(0x0846) -#define TCC1_INTCTRLB _SFR_MEM8(0x0847) -#define TCC1_CTRLFCLR _SFR_MEM8(0x0848) -#define TCC1_CTRLFSET _SFR_MEM8(0x0849) -#define TCC1_CTRLGCLR _SFR_MEM8(0x084A) -#define TCC1_CTRLGSET _SFR_MEM8(0x084B) -#define TCC1_INTFLAGS _SFR_MEM8(0x084C) -#define TCC1_TEMP _SFR_MEM8(0x084F) -#define TCC1_CNT _SFR_MEM16(0x0860) -#define TCC1_PER _SFR_MEM16(0x0866) -#define TCC1_CCA _SFR_MEM16(0x0868) -#define TCC1_CCB _SFR_MEM16(0x086A) -#define TCC1_PERBUF _SFR_MEM16(0x0876) -#define TCC1_CCABUF _SFR_MEM16(0x0878) -#define TCC1_CCBBUF _SFR_MEM16(0x087A) - -/* AWEX - Advanced Waveform Extension */ -#define AWEXC_CTRL _SFR_MEM8(0x0880) -#define AWEXC_FDEMASK _SFR_MEM8(0x0882) -#define AWEXC_FDCTRL _SFR_MEM8(0x0883) -#define AWEXC_STATUS _SFR_MEM8(0x0884) -#define AWEXC_STATUSSET _SFR_MEM8(0x0885) -#define AWEXC_DTBOTH _SFR_MEM8(0x0886) -#define AWEXC_DTBOTHBUF _SFR_MEM8(0x0887) -#define AWEXC_DTLS _SFR_MEM8(0x0888) -#define AWEXC_DTHS _SFR_MEM8(0x0889) -#define AWEXC_DTLSBUF _SFR_MEM8(0x088A) -#define AWEXC_DTHSBUF _SFR_MEM8(0x088B) -#define AWEXC_OUTOVEN _SFR_MEM8(0x088C) - -/* HIRES - High-Resolution Extension */ -#define HIRESC_CTRLA _SFR_MEM8(0x0890) - -/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ -#define USARTC0_DATA _SFR_MEM8(0x08A0) -#define USARTC0_STATUS _SFR_MEM8(0x08A1) -#define USARTC0_CTRLA _SFR_MEM8(0x08A3) -#define USARTC0_CTRLB _SFR_MEM8(0x08A4) -#define USARTC0_CTRLC _SFR_MEM8(0x08A5) -#define USARTC0_BAUDCTRLA _SFR_MEM8(0x08A6) -#define USARTC0_BAUDCTRLB _SFR_MEM8(0x08A7) - -/* SPI - Serial Peripheral Interface */ -#define SPIC_CTRL _SFR_MEM8(0x08C0) -#define SPIC_INTCTRL _SFR_MEM8(0x08C1) -#define SPIC_STATUS _SFR_MEM8(0x08C2) -#define SPIC_DATA _SFR_MEM8(0x08C3) - -/* IRCOM - IR Communication Module */ -#define IRCOM_CTRL _SFR_MEM8(0x08F8) -#define IRCOM_TXPLCTRL _SFR_MEM8(0x08F9) -#define IRCOM_RXPLCTRL _SFR_MEM8(0x08FA) - -/* TC0 - 16-bit Timer/Counter 0 */ -#define TCE0_CTRLA _SFR_MEM8(0x0A00) -#define TCE0_CTRLB _SFR_MEM8(0x0A01) -#define TCE0_CTRLC _SFR_MEM8(0x0A02) -#define TCE0_CTRLD _SFR_MEM8(0x0A03) -#define TCE0_CTRLE _SFR_MEM8(0x0A04) -#define TCE0_INTCTRLA _SFR_MEM8(0x0A06) -#define TCE0_INTCTRLB _SFR_MEM8(0x0A07) -#define TCE0_CTRLFCLR _SFR_MEM8(0x0A08) -#define TCE0_CTRLFSET _SFR_MEM8(0x0A09) -#define TCE0_CTRLGCLR _SFR_MEM8(0x0A0A) -#define TCE0_CTRLGSET _SFR_MEM8(0x0A0B) -#define TCE0_INTFLAGS _SFR_MEM8(0x0A0C) -#define TCE0_TEMP _SFR_MEM8(0x0A0F) -#define TCE0_CNT _SFR_MEM16(0x0A20) -#define TCE0_PER _SFR_MEM16(0x0A26) -#define TCE0_CCA _SFR_MEM16(0x0A28) -#define TCE0_CCB _SFR_MEM16(0x0A2A) -#define TCE0_CCC _SFR_MEM16(0x0A2C) -#define TCE0_CCD _SFR_MEM16(0x0A2E) -#define TCE0_PERBUF _SFR_MEM16(0x0A36) -#define TCE0_CCABUF _SFR_MEM16(0x0A38) -#define TCE0_CCBBUF _SFR_MEM16(0x0A3A) -#define TCE0_CCCBUF _SFR_MEM16(0x0A3C) -#define TCE0_CCDBUF _SFR_MEM16(0x0A3E) - -/* TC2 - 16-bit Timer/Counter type 2 */ -#define TCE2_CTRLA _SFR_MEM8(0x0A00) -#define TCE2_CTRLB _SFR_MEM8(0x0A01) -#define TCE2_CTRLC _SFR_MEM8(0x0A02) -#define TCE2_CTRLE _SFR_MEM8(0x0A04) -#define TCE2_INTCTRLA _SFR_MEM8(0x0A06) -#define TCE2_INTCTRLB _SFR_MEM8(0x0A07) -#define TCE2_CTRLF _SFR_MEM8(0x0A09) -#define TCE2_INTFLAGS _SFR_MEM8(0x0A0C) -#define TCE2_LCNT _SFR_MEM8(0x0A20) -#define TCE2_HCNT _SFR_MEM8(0x0A21) -#define TCE2_LPER _SFR_MEM8(0x0A26) -#define TCE2_HPER _SFR_MEM8(0x0A27) -#define TCE2_LCMPA _SFR_MEM8(0x0A28) -#define TCE2_HCMPA _SFR_MEM8(0x0A29) -#define TCE2_LCMPB _SFR_MEM8(0x0A2A) -#define TCE2_HCMPB _SFR_MEM8(0x0A2B) -#define TCE2_LCMPC _SFR_MEM8(0x0A2C) -#define TCE2_HCMPC _SFR_MEM8(0x0A2D) -#define TCE2_LCMPD _SFR_MEM8(0x0A2E) -#define TCE2_HCMPD _SFR_MEM8(0x0A2F) - -/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ -#define USARTE0_DATA _SFR_MEM8(0x0AA0) -#define USARTE0_STATUS _SFR_MEM8(0x0AA1) -#define USARTE0_CTRLA _SFR_MEM8(0x0AA3) -#define USARTE0_CTRLB _SFR_MEM8(0x0AA4) -#define USARTE0_CTRLC _SFR_MEM8(0x0AA5) -#define USARTE0_BAUDCTRLA _SFR_MEM8(0x0AA6) -#define USARTE0_BAUDCTRLB _SFR_MEM8(0x0AA7) - -/* LCD - LCD Controller */ -#define LCD_CTRLA _SFR_MEM8(0x0D00) -#define LCD_CTRLB _SFR_MEM8(0x0D01) -#define LCD_CTRLC _SFR_MEM8(0x0D02) -#define LCD_INTCTRL _SFR_MEM8(0x0D03) -#define LCD_INTFLAG _SFR_MEM8(0x0D04) -#define LCD_CTRLD _SFR_MEM8(0x0D05) -#define LCD_CTRLE _SFR_MEM8(0x0D06) -#define LCD_CTRLF _SFR_MEM8(0x0D07) -#define LCD_CTRLG _SFR_MEM8(0x0D08) -#define LCD_CTRLH _SFR_MEM8(0x0D09) -#define LCD_DATA0 _SFR_MEM8(0x0D10) -#define LCD_DATA1 _SFR_MEM8(0x0D11) -#define LCD_DATA2 _SFR_MEM8(0x0D12) -#define LCD_DATA3 _SFR_MEM8(0x0D13) -#define LCD_DATA4 _SFR_MEM8(0x0D14) -#define LCD_DATA5 _SFR_MEM8(0x0D15) -#define LCD_DATA6 _SFR_MEM8(0x0D16) -#define LCD_DATA7 _SFR_MEM8(0x0D17) -#define LCD_DATA8 _SFR_MEM8(0x0D18) -#define LCD_DATA9 _SFR_MEM8(0x0D19) -#define LCD_DATA10 _SFR_MEM8(0x0D1A) -#define LCD_DATA11 _SFR_MEM8(0x0D1B) -#define LCD_DATA12 _SFR_MEM8(0x0D1C) -#define LCD_DATA13 _SFR_MEM8(0x0D1D) -#define LCD_DATA14 _SFR_MEM8(0x0D1E) -#define LCD_DATA15 _SFR_MEM8(0x0D1F) -#define LCD_DATA16 _SFR_MEM8(0x0D20) -#define LCD_DATA17 _SFR_MEM8(0x0D21) -#define LCD_DATA18 _SFR_MEM8(0x0D22) -#define LCD_DATA19 _SFR_MEM8(0x0D23) - - - -/*================== Bitfield Definitions ================== */ - -/* VPORT - Virtual Ports */ -/* VPORT.INTFLAGS bit masks and bit positions */ -#define VPORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ -#define VPORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ - -#define VPORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ -#define VPORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ - -/* XOCD - On-Chip Debug System */ -/* OCD.OCDR0 bit masks and bit positions */ -#define OCD_OCDRD_gm 0xFF /* OCDR Dirty group mask. */ -#define OCD_OCDRD_gp 0 /* OCDR Dirty group position. */ -#define OCD_OCDRD0_bm (1<<0) /* OCDR Dirty bit 0 mask. */ -#define OCD_OCDRD0_bp 0 /* OCDR Dirty bit 0 position. */ -#define OCD_OCDRD1_bm (1<<1) /* OCDR Dirty bit 1 mask. */ -#define OCD_OCDRD1_bp 1 /* OCDR Dirty bit 1 position. */ -#define OCD_OCDRD2_bm (1<<2) /* OCDR Dirty bit 2 mask. */ -#define OCD_OCDRD2_bp 2 /* OCDR Dirty bit 2 position. */ -#define OCD_OCDRD3_bm (1<<3) /* OCDR Dirty bit 3 mask. */ -#define OCD_OCDRD3_bp 3 /* OCDR Dirty bit 3 position. */ -#define OCD_OCDRD4_bm (1<<4) /* OCDR Dirty bit 4 mask. */ -#define OCD_OCDRD4_bp 4 /* OCDR Dirty bit 4 position. */ -#define OCD_OCDRD5_bm (1<<5) /* OCDR Dirty bit 5 mask. */ -#define OCD_OCDRD5_bp 5 /* OCDR Dirty bit 5 position. */ -#define OCD_OCDRD6_bm (1<<6) /* OCDR Dirty bit 6 mask. */ -#define OCD_OCDRD6_bp 6 /* OCDR Dirty bit 6 position. */ -#define OCD_OCDRD7_bm (1<<7) /* OCDR Dirty bit 7 mask. */ -#define OCD_OCDRD7_bp 7 /* OCDR Dirty bit 7 position. */ - -/* OCD.OCDR1 bit masks and bit positions */ -/* OCD_OCDRD Predefined. */ -/* OCD_OCDRD Predefined. */ - -/* CPU - CPU */ -/* CPU.CCP bit masks and bit positions */ -#define CPU_CCP_gm 0xFF /* CCP signature group mask. */ -#define CPU_CCP_gp 0 /* CCP signature group position. */ -#define CPU_CCP0_bm (1<<0) /* CCP signature bit 0 mask. */ -#define CPU_CCP0_bp 0 /* CCP signature bit 0 position. */ -#define CPU_CCP1_bm (1<<1) /* CCP signature bit 1 mask. */ -#define CPU_CCP1_bp 1 /* CCP signature bit 1 position. */ -#define CPU_CCP2_bm (1<<2) /* CCP signature bit 2 mask. */ -#define CPU_CCP2_bp 2 /* CCP signature bit 2 position. */ -#define CPU_CCP3_bm (1<<3) /* CCP signature bit 3 mask. */ -#define CPU_CCP3_bp 3 /* CCP signature bit 3 position. */ -#define CPU_CCP4_bm (1<<4) /* CCP signature bit 4 mask. */ -#define CPU_CCP4_bp 4 /* CCP signature bit 4 position. */ -#define CPU_CCP5_bm (1<<5) /* CCP signature bit 5 mask. */ -#define CPU_CCP5_bp 5 /* CCP signature bit 5 position. */ -#define CPU_CCP6_bm (1<<6) /* CCP signature bit 6 mask. */ -#define CPU_CCP6_bp 6 /* CCP signature bit 6 position. */ -#define CPU_CCP7_bm (1<<7) /* CCP signature bit 7 mask. */ -#define CPU_CCP7_bp 7 /* CCP signature bit 7 position. */ - -/* CPU.SREG bit masks and bit positions */ -#define CPU_I_bm 0x80 /* Global Interrupt Enable Flag bit mask. */ -#define CPU_I_bp 7 /* Global Interrupt Enable Flag bit position. */ - -#define CPU_T_bm 0x40 /* Transfer Bit bit mask. */ -#define CPU_T_bp 6 /* Transfer Bit bit position. */ - -#define CPU_H_bm 0x20 /* Half Carry Flag bit mask. */ -#define CPU_H_bp 5 /* Half Carry Flag bit position. */ - -#define CPU_S_bm 0x10 /* N Exclusive Or V Flag bit mask. */ -#define CPU_S_bp 4 /* N Exclusive Or V Flag bit position. */ - -#define CPU_V_bm 0x08 /* Two's Complement Overflow Flag bit mask. */ -#define CPU_V_bp 3 /* Two's Complement Overflow Flag bit position. */ - -#define CPU_N_bm 0x04 /* Negative Flag bit mask. */ -#define CPU_N_bp 2 /* Negative Flag bit position. */ - -#define CPU_Z_bm 0x02 /* Zero Flag bit mask. */ -#define CPU_Z_bp 1 /* Zero Flag bit position. */ - -#define CPU_C_bm 0x01 /* Carry Flag bit mask. */ -#define CPU_C_bp 0 /* Carry Flag bit position. */ - -/* CLK - Clock System */ -/* CLK.CTRL bit masks and bit positions */ -#define CLK_SCLKSEL_gm 0x07 /* System Clock Selection group mask. */ -#define CLK_SCLKSEL_gp 0 /* System Clock Selection group position. */ -#define CLK_SCLKSEL0_bm (1<<0) /* System Clock Selection bit 0 mask. */ -#define CLK_SCLKSEL0_bp 0 /* System Clock Selection bit 0 position. */ -#define CLK_SCLKSEL1_bm (1<<1) /* System Clock Selection bit 1 mask. */ -#define CLK_SCLKSEL1_bp 1 /* System Clock Selection bit 1 position. */ -#define CLK_SCLKSEL2_bm (1<<2) /* System Clock Selection bit 2 mask. */ -#define CLK_SCLKSEL2_bp 2 /* System Clock Selection bit 2 position. */ - -/* CLK.PSCTRL bit masks and bit positions */ -#define CLK_PSADIV_gm 0x7C /* Prescaler A Division Factor group mask. */ -#define CLK_PSADIV_gp 2 /* Prescaler A Division Factor group position. */ -#define CLK_PSADIV0_bm (1<<2) /* Prescaler A Division Factor bit 0 mask. */ -#define CLK_PSADIV0_bp 2 /* Prescaler A Division Factor bit 0 position. */ -#define CLK_PSADIV1_bm (1<<3) /* Prescaler A Division Factor bit 1 mask. */ -#define CLK_PSADIV1_bp 3 /* Prescaler A Division Factor bit 1 position. */ -#define CLK_PSADIV2_bm (1<<4) /* Prescaler A Division Factor bit 2 mask. */ -#define CLK_PSADIV2_bp 4 /* Prescaler A Division Factor bit 2 position. */ -#define CLK_PSADIV3_bm (1<<5) /* Prescaler A Division Factor bit 3 mask. */ -#define CLK_PSADIV3_bp 5 /* Prescaler A Division Factor bit 3 position. */ -#define CLK_PSADIV4_bm (1<<6) /* Prescaler A Division Factor bit 4 mask. */ -#define CLK_PSADIV4_bp 6 /* Prescaler A Division Factor bit 4 position. */ - -#define CLK_PSBCDIV_gm 0x03 /* Prescaler B and C Division factor group mask. */ -#define CLK_PSBCDIV_gp 0 /* Prescaler B and C Division factor group position. */ -#define CLK_PSBCDIV0_bm (1<<0) /* Prescaler B and C Division factor bit 0 mask. */ -#define CLK_PSBCDIV0_bp 0 /* Prescaler B and C Division factor bit 0 position. */ -#define CLK_PSBCDIV1_bm (1<<1) /* Prescaler B and C Division factor bit 1 mask. */ -#define CLK_PSBCDIV1_bp 1 /* Prescaler B and C Division factor bit 1 position. */ - -/* CLK.LOCK bit masks and bit positions */ -#define CLK_LOCK_bm 0x01 /* Clock System Lock bit mask. */ -#define CLK_LOCK_bp 0 /* Clock System Lock bit position. */ - -/* CLK.RTCCTRL bit masks and bit positions */ -#define CLK_RTCSRC_gm 0x0E /* Clock Source group mask. */ -#define CLK_RTCSRC_gp 1 /* Clock Source group position. */ -#define CLK_RTCSRC0_bm (1<<1) /* Clock Source bit 0 mask. */ -#define CLK_RTCSRC0_bp 1 /* Clock Source bit 0 position. */ -#define CLK_RTCSRC1_bm (1<<2) /* Clock Source bit 1 mask. */ -#define CLK_RTCSRC1_bp 2 /* Clock Source bit 1 position. */ -#define CLK_RTCSRC2_bm (1<<3) /* Clock Source bit 2 mask. */ -#define CLK_RTCSRC2_bp 3 /* Clock Source bit 2 position. */ - -#define CLK_RTCEN_bm 0x01 /* Clock Source Enable bit mask. */ -#define CLK_RTCEN_bp 0 /* Clock Source Enable bit position. */ - -/* CLK.USBCTRL bit masks and bit positions */ -#define CLK_USBPSDIV_gm 0x38 /* Prescaler Division Factor group mask. */ -#define CLK_USBPSDIV_gp 3 /* Prescaler Division Factor group position. */ -#define CLK_USBPSDIV0_bm (1<<3) /* Prescaler Division Factor bit 0 mask. */ -#define CLK_USBPSDIV0_bp 3 /* Prescaler Division Factor bit 0 position. */ -#define CLK_USBPSDIV1_bm (1<<4) /* Prescaler Division Factor bit 1 mask. */ -#define CLK_USBPSDIV1_bp 4 /* Prescaler Division Factor bit 1 position. */ -#define CLK_USBPSDIV2_bm (1<<5) /* Prescaler Division Factor bit 2 mask. */ -#define CLK_USBPSDIV2_bp 5 /* Prescaler Division Factor bit 2 position. */ - -#define CLK_USBSRC_gm 0x06 /* Clock Source group mask. */ -#define CLK_USBSRC_gp 1 /* Clock Source group position. */ -#define CLK_USBSRC0_bm (1<<1) /* Clock Source bit 0 mask. */ -#define CLK_USBSRC0_bp 1 /* Clock Source bit 0 position. */ -#define CLK_USBSRC1_bm (1<<2) /* Clock Source bit 1 mask. */ -#define CLK_USBSRC1_bp 2 /* Clock Source bit 1 position. */ - -#define CLK_USBSEN_bm 0x01 /* Clock Source Enable bit mask. */ -#define CLK_USBSEN_bp 0 /* Clock Source Enable bit position. */ - -/* SLEEP - Sleep Controller */ -/* SLEEP.CTRL bit masks and bit positions */ -#define SLEEP_SMODE_gm 0x0E /* Sleep Mode group mask. */ -#define SLEEP_SMODE_gp 1 /* Sleep Mode group position. */ -#define SLEEP_SMODE0_bm (1<<1) /* Sleep Mode bit 0 mask. */ -#define SLEEP_SMODE0_bp 1 /* Sleep Mode bit 0 position. */ -#define SLEEP_SMODE1_bm (1<<2) /* Sleep Mode bit 1 mask. */ -#define SLEEP_SMODE1_bp 2 /* Sleep Mode bit 1 position. */ -#define SLEEP_SMODE2_bm (1<<3) /* Sleep Mode bit 2 mask. */ -#define SLEEP_SMODE2_bp 3 /* Sleep Mode bit 2 position. */ - -#define SLEEP_SEN_bm 0x01 /* Sleep Enable bit mask. */ -#define SLEEP_SEN_bp 0 /* Sleep Enable bit position. */ - -/* OSC - Oscillator */ -/* OSC.CTRL bit masks and bit positions */ -#define OSC_PLLEN_bm 0x10 /* PLL Enable bit mask. */ -#define OSC_PLLEN_bp 4 /* PLL Enable bit position. */ - -#define OSC_XOSCEN_bm 0x08 /* External Oscillator Enable bit mask. */ -#define OSC_XOSCEN_bp 3 /* External Oscillator Enable bit position. */ - -#define OSC_RC32KEN_bm 0x04 /* Internal 32.768 kHz RC Oscillator Enable bit mask. */ -#define OSC_RC32KEN_bp 2 /* Internal 32.768 kHz RC Oscillator Enable bit position. */ - -#define OSC_RC32MEN_bm 0x02 /* Internal 32 MHz RC Oscillator Enable bit mask. */ -#define OSC_RC32MEN_bp 1 /* Internal 32 MHz RC Oscillator Enable bit position. */ - -#define OSC_RC2MEN_bm 0x01 /* Internal 2 MHz RC Oscillator Enable bit mask. */ -#define OSC_RC2MEN_bp 0 /* Internal 2 MHz RC Oscillator Enable bit position. */ - -/* OSC.STATUS bit masks and bit positions */ -#define OSC_PLLRDY_bm 0x10 /* PLL Ready bit mask. */ -#define OSC_PLLRDY_bp 4 /* PLL Ready bit position. */ - -#define OSC_XOSCRDY_bm 0x08 /* External Oscillator Ready bit mask. */ -#define OSC_XOSCRDY_bp 3 /* External Oscillator Ready bit position. */ - -#define OSC_RC32KRDY_bm 0x04 /* Internal 32.768 kHz RC Oscillator Ready bit mask. */ -#define OSC_RC32KRDY_bp 2 /* Internal 32.768 kHz RC Oscillator Ready bit position. */ - -#define OSC_RC32MRDY_bm 0x02 /* Internal 32 MHz RC Oscillator Ready bit mask. */ -#define OSC_RC32MRDY_bp 1 /* Internal 32 MHz RC Oscillator Ready bit position. */ - -#define OSC_RC2MRDY_bm 0x01 /* Internal 2 MHz RC Oscillator Ready bit mask. */ -#define OSC_RC2MRDY_bp 0 /* Internal 2 MHz RC Oscillator Ready bit position. */ - -/* OSC.XOSCCTRL bit masks and bit positions */ -#define OSC_FRQRANGE_gm 0xC0 /* Frequency Range group mask. */ -#define OSC_FRQRANGE_gp 6 /* Frequency Range group position. */ -#define OSC_FRQRANGE0_bm (1<<6) /* Frequency Range bit 0 mask. */ -#define OSC_FRQRANGE0_bp 6 /* Frequency Range bit 0 position. */ -#define OSC_FRQRANGE1_bm (1<<7) /* Frequency Range bit 1 mask. */ -#define OSC_FRQRANGE1_bp 7 /* Frequency Range bit 1 position. */ - -#define OSC_X32KLPM_bm 0x20 /* 32.768 kHz XTAL OSC Low-power Mode bit mask. */ -#define OSC_X32KLPM_bp 5 /* 32.768 kHz XTAL OSC Low-power Mode bit position. */ - -#define OSC_XOSCPWR_bm 0x10 /* 16 MHz Crystal Oscillator High Power mode bit mask. */ -#define OSC_XOSCPWR_bp 4 /* 16 MHz Crystal Oscillator High Power mode bit position. */ - -#define OSC_XOSCSEL_gm 0x1F /* External Oscillator Selection and Startup Time group mask. */ -#define OSC_XOSCSEL_gp 0 /* External Oscillator Selection and Startup Time group position. */ -#define OSC_XOSCSEL0_bm (1<<0) /* External Oscillator Selection and Startup Time bit 0 mask. */ -#define OSC_XOSCSEL0_bp 0 /* External Oscillator Selection and Startup Time bit 0 position. */ -#define OSC_XOSCSEL1_bm (1<<1) /* External Oscillator Selection and Startup Time bit 1 mask. */ -#define OSC_XOSCSEL1_bp 1 /* External Oscillator Selection and Startup Time bit 1 position. */ -#define OSC_XOSCSEL2_bm (1<<2) /* External Oscillator Selection and Startup Time bit 2 mask. */ -#define OSC_XOSCSEL2_bp 2 /* External Oscillator Selection and Startup Time bit 2 position. */ -#define OSC_XOSCSEL3_bm (1<<3) /* External Oscillator Selection and Startup Time bit 3 mask. */ -#define OSC_XOSCSEL3_bp 3 /* External Oscillator Selection and Startup Time bit 3 position. */ -#define OSC_XOSCSEL4_bm (1<<4) /* External Oscillator Selection and Startup Time bit 4 mask. */ -#define OSC_XOSCSEL4_bp 4 /* External Oscillator Selection and Startup Time bit 4 position. */ - -/* OSC.XOSCFAIL bit masks and bit positions */ -#define OSC_PLLFDIF_bm 0x08 /* PLL Failure Detection Interrupt Flag bit mask. */ -#define OSC_PLLFDIF_bp 3 /* PLL Failure Detection Interrupt Flag bit position. */ - -#define OSC_PLLFDEN_bm 0x04 /* PLL Failure Detection Enable bit mask. */ -#define OSC_PLLFDEN_bp 2 /* PLL Failure Detection Enable bit position. */ - -#define OSC_XOSCFDIF_bm 0x02 /* XOSC Failure Detection Interrupt Flag bit mask. */ -#define OSC_XOSCFDIF_bp 1 /* XOSC Failure Detection Interrupt Flag bit position. */ - -#define OSC_XOSCFDEN_bm 0x01 /* XOSC Failure Detection Enable bit mask. */ -#define OSC_XOSCFDEN_bp 0 /* XOSC Failure Detection Enable bit position. */ - -/* OSC.PLLCTRL bit masks and bit positions */ -#define OSC_PLLSRC_gm 0xC0 /* Clock Source group mask. */ -#define OSC_PLLSRC_gp 6 /* Clock Source group position. */ -#define OSC_PLLSRC0_bm (1<<6) /* Clock Source bit 0 mask. */ -#define OSC_PLLSRC0_bp 6 /* Clock Source bit 0 position. */ -#define OSC_PLLSRC1_bm (1<<7) /* Clock Source bit 1 mask. */ -#define OSC_PLLSRC1_bp 7 /* Clock Source bit 1 position. */ - -#define OSC_PLLDIV_bm 0x20 /* Divide by 2 bit mask. */ -#define OSC_PLLDIV_bp 5 /* Divide by 2 bit position. */ - -#define OSC_PLLFAC_gm 0x1F /* Multiplication Factor group mask. */ -#define OSC_PLLFAC_gp 0 /* Multiplication Factor group position. */ -#define OSC_PLLFAC0_bm (1<<0) /* Multiplication Factor bit 0 mask. */ -#define OSC_PLLFAC0_bp 0 /* Multiplication Factor bit 0 position. */ -#define OSC_PLLFAC1_bm (1<<1) /* Multiplication Factor bit 1 mask. */ -#define OSC_PLLFAC1_bp 1 /* Multiplication Factor bit 1 position. */ -#define OSC_PLLFAC2_bm (1<<2) /* Multiplication Factor bit 2 mask. */ -#define OSC_PLLFAC2_bp 2 /* Multiplication Factor bit 2 position. */ -#define OSC_PLLFAC3_bm (1<<3) /* Multiplication Factor bit 3 mask. */ -#define OSC_PLLFAC3_bp 3 /* Multiplication Factor bit 3 position. */ -#define OSC_PLLFAC4_bm (1<<4) /* Multiplication Factor bit 4 mask. */ -#define OSC_PLLFAC4_bp 4 /* Multiplication Factor bit 4 position. */ - -/* OSC.DFLLCTRL bit masks and bit positions */ -#define OSC_RC32MCREF_gm 0x06 /* 32 MHz DFLL Calibration Reference group mask. */ -#define OSC_RC32MCREF_gp 1 /* 32 MHz DFLL Calibration Reference group position. */ -#define OSC_RC32MCREF0_bm (1<<1) /* 32 MHz DFLL Calibration Reference bit 0 mask. */ -#define OSC_RC32MCREF0_bp 1 /* 32 MHz DFLL Calibration Reference bit 0 position. */ -#define OSC_RC32MCREF1_bm (1<<2) /* 32 MHz DFLL Calibration Reference bit 1 mask. */ -#define OSC_RC32MCREF1_bp 2 /* 32 MHz DFLL Calibration Reference bit 1 position. */ - -#define OSC_RC2MCREF_bm 0x01 /* 2 MHz DFLL Calibration Reference bit mask. */ -#define OSC_RC2MCREF_bp 0 /* 2 MHz DFLL Calibration Reference bit position. */ - -/* DFLL - DFLL */ -/* DFLL.CTRL bit masks and bit positions */ -#define DFLL_ENABLE_bm 0x01 /* DFLL Enable bit mask. */ -#define DFLL_ENABLE_bp 0 /* DFLL Enable bit position. */ - -/* DFLL.CALA bit masks and bit positions */ -#define DFLL_CALL_gm 0x7F /* DFLL Calibration Value A group mask. */ -#define DFLL_CALL_gp 0 /* DFLL Calibration Value A group position. */ -#define DFLL_CALL0_bm (1<<0) /* DFLL Calibration Value A bit 0 mask. */ -#define DFLL_CALL0_bp 0 /* DFLL Calibration Value A bit 0 position. */ -#define DFLL_CALL1_bm (1<<1) /* DFLL Calibration Value A bit 1 mask. */ -#define DFLL_CALL1_bp 1 /* DFLL Calibration Value A bit 1 position. */ -#define DFLL_CALL2_bm (1<<2) /* DFLL Calibration Value A bit 2 mask. */ -#define DFLL_CALL2_bp 2 /* DFLL Calibration Value A bit 2 position. */ -#define DFLL_CALL3_bm (1<<3) /* DFLL Calibration Value A bit 3 mask. */ -#define DFLL_CALL3_bp 3 /* DFLL Calibration Value A bit 3 position. */ -#define DFLL_CALL4_bm (1<<4) /* DFLL Calibration Value A bit 4 mask. */ -#define DFLL_CALL4_bp 4 /* DFLL Calibration Value A bit 4 position. */ -#define DFLL_CALL5_bm (1<<5) /* DFLL Calibration Value A bit 5 mask. */ -#define DFLL_CALL5_bp 5 /* DFLL Calibration Value A bit 5 position. */ -#define DFLL_CALL6_bm (1<<6) /* DFLL Calibration Value A bit 6 mask. */ -#define DFLL_CALL6_bp 6 /* DFLL Calibration Value A bit 6 position. */ - -/* DFLL.CALB bit masks and bit positions */ -#define DFLL_CALH_gm 0x3F /* DFLL Calibration Value B group mask. */ -#define DFLL_CALH_gp 0 /* DFLL Calibration Value B group position. */ -#define DFLL_CALH0_bm (1<<0) /* DFLL Calibration Value B bit 0 mask. */ -#define DFLL_CALH0_bp 0 /* DFLL Calibration Value B bit 0 position. */ -#define DFLL_CALH1_bm (1<<1) /* DFLL Calibration Value B bit 1 mask. */ -#define DFLL_CALH1_bp 1 /* DFLL Calibration Value B bit 1 position. */ -#define DFLL_CALH2_bm (1<<2) /* DFLL Calibration Value B bit 2 mask. */ -#define DFLL_CALH2_bp 2 /* DFLL Calibration Value B bit 2 position. */ -#define DFLL_CALH3_bm (1<<3) /* DFLL Calibration Value B bit 3 mask. */ -#define DFLL_CALH3_bp 3 /* DFLL Calibration Value B bit 3 position. */ -#define DFLL_CALH4_bm (1<<4) /* DFLL Calibration Value B bit 4 mask. */ -#define DFLL_CALH4_bp 4 /* DFLL Calibration Value B bit 4 position. */ -#define DFLL_CALH5_bm (1<<5) /* DFLL Calibration Value B bit 5 mask. */ -#define DFLL_CALH5_bp 5 /* DFLL Calibration Value B bit 5 position. */ - -/* PR - Power Reduction */ -/* PR.PRGEN bit masks and bit positions */ -#define PR_LCD_bm 0x80 /* LCD Module bit mask. */ -#define PR_LCD_bp 7 /* LCD Module bit position. */ - -#define PR_USB_bm 0x40 /* USB bit mask. */ -#define PR_USB_bp 6 /* USB bit position. */ - -#define PR_AES_bm 0x10 /* AES bit mask. */ -#define PR_AES_bp 4 /* AES bit position. */ - -#define PR_RTC_bm 0x04 /* Real-time Counter bit mask. */ -#define PR_RTC_bp 2 /* Real-time Counter bit position. */ - -#define PR_EVSYS_bm 0x02 /* Event System bit mask. */ -#define PR_EVSYS_bp 1 /* Event System bit position. */ - -#define PR_DMA_bm 0x01 /* DMA-Controller bit mask. */ -#define PR_DMA_bp 0 /* DMA-Controller bit position. */ - -/* PR.PRPA bit masks and bit positions */ -#define PR_ADC_bm 0x02 /* Port A ADC bit mask. */ -#define PR_ADC_bp 1 /* Port A ADC bit position. */ - -#define PR_AC_bm 0x01 /* Port A Analog Comparator bit mask. */ -#define PR_AC_bp 0 /* Port A Analog Comparator bit position. */ - -/* PR.PRPB bit masks and bit positions */ -/* PR_ADC Predefined. */ -/* PR_ADC Predefined. */ - -/* PR_AC Predefined. */ -/* PR_AC Predefined. */ - -/* PR.PRPC bit masks and bit positions */ -#define PR_TWI_bm 0x40 /* Port C Two-wire Interface bit mask. */ -#define PR_TWI_bp 6 /* Port C Two-wire Interface bit position. */ - -#define PR_USART0_bm 0x10 /* Port C USART0 bit mask. */ -#define PR_USART0_bp 4 /* Port C USART0 bit position. */ - -#define PR_SPI_bm 0x08 /* Port C SPI bit mask. */ -#define PR_SPI_bp 3 /* Port C SPI bit position. */ - -#define PR_HIRES_bm 0x04 /* Port C AWEX bit mask. */ -#define PR_HIRES_bp 2 /* Port C AWEX bit position. */ - -#define PR_TC1_bm 0x02 /* Port C Timer/Counter1 bit mask. */ -#define PR_TC1_bp 1 /* Port C Timer/Counter1 bit position. */ - -#define PR_TC0_bm 0x01 /* Port C Timer/Counter0 bit mask. */ -#define PR_TC0_bp 0 /* Port C Timer/Counter0 bit position. */ - -/* PR.PRPE bit masks and bit positions */ -/* PR_USART0 Predefined. */ -/* PR_USART0 Predefined. */ - -/* PR_TC0 Predefined. */ -/* PR_TC0 Predefined. */ - -/* RST - Reset */ -/* RST.STATUS bit masks and bit positions */ -#define RST_SDRF_bm 0x40 /* Spike Detection Reset Flag bit mask. */ -#define RST_SDRF_bp 6 /* Spike Detection Reset Flag bit position. */ - -#define RST_SRF_bm 0x20 /* Software Reset Flag bit mask. */ -#define RST_SRF_bp 5 /* Software Reset Flag bit position. */ - -#define RST_PDIRF_bm 0x10 /* Programming and Debug Interface Interface Reset Flag bit mask. */ -#define RST_PDIRF_bp 4 /* Programming and Debug Interface Interface Reset Flag bit position. */ - -#define RST_WDRF_bm 0x08 /* Watchdog Reset Flag bit mask. */ -#define RST_WDRF_bp 3 /* Watchdog Reset Flag bit position. */ - -#define RST_BORF_bm 0x04 /* Brown-out Reset Flag bit mask. */ -#define RST_BORF_bp 2 /* Brown-out Reset Flag bit position. */ - -#define RST_EXTRF_bm 0x02 /* External Reset Flag bit mask. */ -#define RST_EXTRF_bp 1 /* External Reset Flag bit position. */ - -#define RST_PORF_bm 0x01 /* Power-on Reset Flag bit mask. */ -#define RST_PORF_bp 0 /* Power-on Reset Flag bit position. */ - -/* RST.CTRL bit masks and bit positions */ -#define RST_SWRST_bm 0x01 /* Software Reset bit mask. */ -#define RST_SWRST_bp 0 /* Software Reset bit position. */ - -/* WDT - Watch-Dog Timer */ -/* WDT.CTRL bit masks and bit positions */ -#define WDT_PER_gm 0x3C /* Period group mask. */ -#define WDT_PER_gp 2 /* Period group position. */ -#define WDT_PER0_bm (1<<2) /* Period bit 0 mask. */ -#define WDT_PER0_bp 2 /* Period bit 0 position. */ -#define WDT_PER1_bm (1<<3) /* Period bit 1 mask. */ -#define WDT_PER1_bp 3 /* Period bit 1 position. */ -#define WDT_PER2_bm (1<<4) /* Period bit 2 mask. */ -#define WDT_PER2_bp 4 /* Period bit 2 position. */ -#define WDT_PER3_bm (1<<5) /* Period bit 3 mask. */ -#define WDT_PER3_bp 5 /* Period bit 3 position. */ - -#define WDT_ENABLE_bm 0x02 /* Enable bit mask. */ -#define WDT_ENABLE_bp 1 /* Enable bit position. */ - -#define WDT_CEN_bm 0x01 /* Change Enable bit mask. */ -#define WDT_CEN_bp 0 /* Change Enable bit position. */ - -/* WDT.WINCTRL bit masks and bit positions */ -#define WDT_WPER_gm 0x3C /* Windowed Mode Period group mask. */ -#define WDT_WPER_gp 2 /* Windowed Mode Period group position. */ -#define WDT_WPER0_bm (1<<2) /* Windowed Mode Period bit 0 mask. */ -#define WDT_WPER0_bp 2 /* Windowed Mode Period bit 0 position. */ -#define WDT_WPER1_bm (1<<3) /* Windowed Mode Period bit 1 mask. */ -#define WDT_WPER1_bp 3 /* Windowed Mode Period bit 1 position. */ -#define WDT_WPER2_bm (1<<4) /* Windowed Mode Period bit 2 mask. */ -#define WDT_WPER2_bp 4 /* Windowed Mode Period bit 2 position. */ -#define WDT_WPER3_bm (1<<5) /* Windowed Mode Period bit 3 mask. */ -#define WDT_WPER3_bp 5 /* Windowed Mode Period bit 3 position. */ - -#define WDT_WEN_bm 0x02 /* Windowed Mode Enable bit mask. */ -#define WDT_WEN_bp 1 /* Windowed Mode Enable bit position. */ - -#define WDT_WCEN_bm 0x01 /* Windowed Mode Change Enable bit mask. */ -#define WDT_WCEN_bp 0 /* Windowed Mode Change Enable bit position. */ - -/* WDT.STATUS bit masks and bit positions */ -#define WDT_SYNCBUSY_bm 0x01 /* Syncronization busy bit mask. */ -#define WDT_SYNCBUSY_bp 0 /* Syncronization busy bit position. */ - -/* MCU - MCU Control */ -/* MCU.MCUCR bit masks and bit positions */ -#define MCU_JTAGD_bm 0x01 /* JTAG Disable bit mask. */ -#define MCU_JTAGD_bp 0 /* JTAG Disable bit position. */ - -/* MCU.ANAINIT bit masks and bit positions */ -#define MCU_STARTUPDLYB_gm 0x0C /* Analog startup delay Port B group mask. */ -#define MCU_STARTUPDLYB_gp 2 /* Analog startup delay Port B group position. */ -#define MCU_STARTUPDLYB0_bm (1<<2) /* Analog startup delay Port B bit 0 mask. */ -#define MCU_STARTUPDLYB0_bp 2 /* Analog startup delay Port B bit 0 position. */ -#define MCU_STARTUPDLYB1_bm (1<<3) /* Analog startup delay Port B bit 1 mask. */ -#define MCU_STARTUPDLYB1_bp 3 /* Analog startup delay Port B bit 1 position. */ - -#define MCU_STARTUPDLYA_gm 0x03 /* Analog startup delay Port A group mask. */ -#define MCU_STARTUPDLYA_gp 0 /* Analog startup delay Port A group position. */ -#define MCU_STARTUPDLYA0_bm (1<<0) /* Analog startup delay Port A bit 0 mask. */ -#define MCU_STARTUPDLYA0_bp 0 /* Analog startup delay Port A bit 0 position. */ -#define MCU_STARTUPDLYA1_bm (1<<1) /* Analog startup delay Port A bit 1 mask. */ -#define MCU_STARTUPDLYA1_bp 1 /* Analog startup delay Port A bit 1 position. */ - -/* MCU.EVSYSLOCK bit masks and bit positions */ -#define MCU_EVSYS1LOCK_bm 0x10 /* Event Channel 4-7 Lock bit mask. */ -#define MCU_EVSYS1LOCK_bp 4 /* Event Channel 4-7 Lock bit position. */ - -#define MCU_EVSYS0LOCK_bm 0x01 /* Event Channel 0-3 Lock bit mask. */ -#define MCU_EVSYS0LOCK_bp 0 /* Event Channel 0-3 Lock bit position. */ - -/* MCU.AWEXLOCK bit masks and bit positions */ -#define MCU_AWEXCLOCK_bm 0x01 /* AWeX on T/C C0 Lock bit mask. */ -#define MCU_AWEXCLOCK_bp 0 /* AWeX on T/C C0 Lock bit position. */ - -/* PMIC - Programmable Multi-level Interrupt Controller */ -/* PMIC.STATUS bit masks and bit positions */ -#define PMIC_NMIEX_bm 0x80 /* Non-maskable Interrupt Executing bit mask. */ -#define PMIC_NMIEX_bp 7 /* Non-maskable Interrupt Executing bit position. */ - -#define PMIC_HILVLEX_bm 0x04 /* High Level Interrupt Executing bit mask. */ -#define PMIC_HILVLEX_bp 2 /* High Level Interrupt Executing bit position. */ - -#define PMIC_MEDLVLEX_bm 0x02 /* Medium Level Interrupt Executing bit mask. */ -#define PMIC_MEDLVLEX_bp 1 /* Medium Level Interrupt Executing bit position. */ - -#define PMIC_LOLVLEX_bm 0x01 /* Low Level Interrupt Executing bit mask. */ -#define PMIC_LOLVLEX_bp 0 /* Low Level Interrupt Executing bit position. */ - -/* PMIC.INTPRI bit masks and bit positions */ -#define PMIC_INTPRI_gm 0xFF /* Interrupt Priority group mask. */ -#define PMIC_INTPRI_gp 0 /* Interrupt Priority group position. */ -#define PMIC_INTPRI0_bm (1<<0) /* Interrupt Priority bit 0 mask. */ -#define PMIC_INTPRI0_bp 0 /* Interrupt Priority bit 0 position. */ -#define PMIC_INTPRI1_bm (1<<1) /* Interrupt Priority bit 1 mask. */ -#define PMIC_INTPRI1_bp 1 /* Interrupt Priority bit 1 position. */ -#define PMIC_INTPRI2_bm (1<<2) /* Interrupt Priority bit 2 mask. */ -#define PMIC_INTPRI2_bp 2 /* Interrupt Priority bit 2 position. */ -#define PMIC_INTPRI3_bm (1<<3) /* Interrupt Priority bit 3 mask. */ -#define PMIC_INTPRI3_bp 3 /* Interrupt Priority bit 3 position. */ -#define PMIC_INTPRI4_bm (1<<4) /* Interrupt Priority bit 4 mask. */ -#define PMIC_INTPRI4_bp 4 /* Interrupt Priority bit 4 position. */ -#define PMIC_INTPRI5_bm (1<<5) /* Interrupt Priority bit 5 mask. */ -#define PMIC_INTPRI5_bp 5 /* Interrupt Priority bit 5 position. */ -#define PMIC_INTPRI6_bm (1<<6) /* Interrupt Priority bit 6 mask. */ -#define PMIC_INTPRI6_bp 6 /* Interrupt Priority bit 6 position. */ -#define PMIC_INTPRI7_bm (1<<7) /* Interrupt Priority bit 7 mask. */ -#define PMIC_INTPRI7_bp 7 /* Interrupt Priority bit 7 position. */ - -/* PMIC.CTRL bit masks and bit positions */ -#define PMIC_RREN_bm 0x80 /* Round-Robin Priority Enable bit mask. */ -#define PMIC_RREN_bp 7 /* Round-Robin Priority Enable bit position. */ - -#define PMIC_IVSEL_bm 0x40 /* Interrupt Vector Select bit mask. */ -#define PMIC_IVSEL_bp 6 /* Interrupt Vector Select bit position. */ - -#define PMIC_HILVLEN_bm 0x04 /* High Level Enable bit mask. */ -#define PMIC_HILVLEN_bp 2 /* High Level Enable bit position. */ - -#define PMIC_MEDLVLEN_bm 0x02 /* Medium Level Enable bit mask. */ -#define PMIC_MEDLVLEN_bp 1 /* Medium Level Enable bit position. */ - -#define PMIC_LOLVLEN_bm 0x01 /* Low Level Enable bit mask. */ -#define PMIC_LOLVLEN_bp 0 /* Low Level Enable bit position. */ - -/* PORTCFG - Port Configuration */ -/* PORTCFG.VPCTRLA bit masks and bit positions */ -#define PORTCFG_VP1MAP_gm 0xF0 /* Virtual Port 1 Mapping group mask. */ -#define PORTCFG_VP1MAP_gp 4 /* Virtual Port 1 Mapping group position. */ -#define PORTCFG_VP1MAP0_bm (1<<4) /* Virtual Port 1 Mapping bit 0 mask. */ -#define PORTCFG_VP1MAP0_bp 4 /* Virtual Port 1 Mapping bit 0 position. */ -#define PORTCFG_VP1MAP1_bm (1<<5) /* Virtual Port 1 Mapping bit 1 mask. */ -#define PORTCFG_VP1MAP1_bp 5 /* Virtual Port 1 Mapping bit 1 position. */ -#define PORTCFG_VP1MAP2_bm (1<<6) /* Virtual Port 1 Mapping bit 2 mask. */ -#define PORTCFG_VP1MAP2_bp 6 /* Virtual Port 1 Mapping bit 2 position. */ -#define PORTCFG_VP1MAP3_bm (1<<7) /* Virtual Port 1 Mapping bit 3 mask. */ -#define PORTCFG_VP1MAP3_bp 7 /* Virtual Port 1 Mapping bit 3 position. */ - -#define PORTCFG_VP0MAP_gm 0x0F /* Virtual Port 0 Mapping group mask. */ -#define PORTCFG_VP0MAP_gp 0 /* Virtual Port 0 Mapping group position. */ -#define PORTCFG_VP0MAP0_bm (1<<0) /* Virtual Port 0 Mapping bit 0 mask. */ -#define PORTCFG_VP0MAP0_bp 0 /* Virtual Port 0 Mapping bit 0 position. */ -#define PORTCFG_VP0MAP1_bm (1<<1) /* Virtual Port 0 Mapping bit 1 mask. */ -#define PORTCFG_VP0MAP1_bp 1 /* Virtual Port 0 Mapping bit 1 position. */ -#define PORTCFG_VP0MAP2_bm (1<<2) /* Virtual Port 0 Mapping bit 2 mask. */ -#define PORTCFG_VP0MAP2_bp 2 /* Virtual Port 0 Mapping bit 2 position. */ -#define PORTCFG_VP0MAP3_bm (1<<3) /* Virtual Port 0 Mapping bit 3 mask. */ -#define PORTCFG_VP0MAP3_bp 3 /* Virtual Port 0 Mapping bit 3 position. */ - -/* PORTCFG.VPCTRLB bit masks and bit positions */ -#define PORTCFG_VP3MAP_gm 0xF0 /* Virtual Port 3 Mapping group mask. */ -#define PORTCFG_VP3MAP_gp 4 /* Virtual Port 3 Mapping group position. */ -#define PORTCFG_VP3MAP0_bm (1<<4) /* Virtual Port 3 Mapping bit 0 mask. */ -#define PORTCFG_VP3MAP0_bp 4 /* Virtual Port 3 Mapping bit 0 position. */ -#define PORTCFG_VP3MAP1_bm (1<<5) /* Virtual Port 3 Mapping bit 1 mask. */ -#define PORTCFG_VP3MAP1_bp 5 /* Virtual Port 3 Mapping bit 1 position. */ -#define PORTCFG_VP3MAP2_bm (1<<6) /* Virtual Port 3 Mapping bit 2 mask. */ -#define PORTCFG_VP3MAP2_bp 6 /* Virtual Port 3 Mapping bit 2 position. */ -#define PORTCFG_VP3MAP3_bm (1<<7) /* Virtual Port 3 Mapping bit 3 mask. */ -#define PORTCFG_VP3MAP3_bp 7 /* Virtual Port 3 Mapping bit 3 position. */ - -#define PORTCFG_VP2MAP_gm 0x0F /* Virtual Port 2 Mapping group mask. */ -#define PORTCFG_VP2MAP_gp 0 /* Virtual Port 2 Mapping group position. */ -#define PORTCFG_VP2MAP0_bm (1<<0) /* Virtual Port 2 Mapping bit 0 mask. */ -#define PORTCFG_VP2MAP0_bp 0 /* Virtual Port 2 Mapping bit 0 position. */ -#define PORTCFG_VP2MAP1_bm (1<<1) /* Virtual Port 2 Mapping bit 1 mask. */ -#define PORTCFG_VP2MAP1_bp 1 /* Virtual Port 2 Mapping bit 1 position. */ -#define PORTCFG_VP2MAP2_bm (1<<2) /* Virtual Port 2 Mapping bit 2 mask. */ -#define PORTCFG_VP2MAP2_bp 2 /* Virtual Port 2 Mapping bit 2 position. */ -#define PORTCFG_VP2MAP3_bm (1<<3) /* Virtual Port 2 Mapping bit 3 mask. */ -#define PORTCFG_VP2MAP3_bp 3 /* Virtual Port 2 Mapping bit 3 position. */ - -/* PORTCFG.CLKEVOUT bit masks and bit positions */ -#define PORTCFG_CLKOUT_gm 0x03 /* Peripheral Clock Output Port group mask. */ -#define PORTCFG_CLKOUT_gp 0 /* Peripheral Clock Output Port group position. */ -#define PORTCFG_CLKOUT0_bm (1<<0) /* Peripheral Clock Output Port bit 0 mask. */ -#define PORTCFG_CLKOUT0_bp 0 /* Peripheral Clock Output Port bit 0 position. */ -#define PORTCFG_CLKOUT1_bm (1<<1) /* Peripheral Clock Output Port bit 1 mask. */ -#define PORTCFG_CLKOUT1_bp 1 /* Peripheral Clock Output Port bit 1 position. */ - -#define PORTCFG_CLKOUTSEL_gm 0x0C /* Peripheral Clock Output Select group mask. */ -#define PORTCFG_CLKOUTSEL_gp 2 /* Peripheral Clock Output Select group position. */ -#define PORTCFG_CLKOUTSEL0_bm (1<<2) /* Peripheral Clock Output Select bit 0 mask. */ -#define PORTCFG_CLKOUTSEL0_bp 2 /* Peripheral Clock Output Select bit 0 position. */ -#define PORTCFG_CLKOUTSEL1_bm (1<<3) /* Peripheral Clock Output Select bit 1 mask. */ -#define PORTCFG_CLKOUTSEL1_bp 3 /* Peripheral Clock Output Select bit 1 position. */ - -#define PORTCFG_EVOUT_gm 0x30 /* Event Output Port group mask. */ -#define PORTCFG_EVOUT_gp 4 /* Event Output Port group position. */ -#define PORTCFG_EVOUT0_bm (1<<4) /* Event Output Port bit 0 mask. */ -#define PORTCFG_EVOUT0_bp 4 /* Event Output Port bit 0 position. */ -#define PORTCFG_EVOUT1_bm (1<<5) /* Event Output Port bit 1 mask. */ -#define PORTCFG_EVOUT1_bp 5 /* Event Output Port bit 1 position. */ - -#define PORTCFG_RTCOUT_bm 0x40 /* RTC Clock Output bit mask. */ -#define PORTCFG_RTCOUT_bp 6 /* RTC Clock Output bit position. */ - -#define PORTCFG_CLKEVPIN_bm 0x80 /* Peripheral Clock and Event Output pin Select bit mask. */ -#define PORTCFG_CLKEVPIN_bp 7 /* Peripheral Clock and Event Output pin Select bit position. */ - -/* PORTCFG.EVOUTSEL bit masks and bit positions */ -#define PORTCFG_EVOUTSEL_bm 0x04 /* Event Output Select bit mask. */ -#define PORTCFG_EVOUTSEL_bp 2 /* Event Output Select bit position. */ - -/* AES - AES Module */ -/* AES.CTRL bit masks and bit positions */ -#define AES_START_bm 0x80 /* Start/Run bit mask. */ -#define AES_START_bp 7 /* Start/Run bit position. */ - -#define AES_AUTO_bm 0x40 /* Auto Start Trigger bit mask. */ -#define AES_AUTO_bp 6 /* Auto Start Trigger bit position. */ - -#define AES_RESET_bm 0x20 /* AES Software Reset bit mask. */ -#define AES_RESET_bp 5 /* AES Software Reset bit position. */ - -#define AES_DECRYPT_bm 0x10 /* Decryption / Direction bit mask. */ -#define AES_DECRYPT_bp 4 /* Decryption / Direction bit position. */ - -#define AES_XOR_bm 0x04 /* State XOR Load Enable bit mask. */ -#define AES_XOR_bp 2 /* State XOR Load Enable bit position. */ - -/* AES.STATUS bit masks and bit positions */ -#define AES_ERROR_bm 0x80 /* AES Error bit mask. */ -#define AES_ERROR_bp 7 /* AES Error bit position. */ - -#define AES_SRIF_bm 0x01 /* State Ready Interrupt Flag bit mask. */ -#define AES_SRIF_bp 0 /* State Ready Interrupt Flag bit position. */ - -/* AES.INTCTRL bit masks and bit positions */ -#define AES_INTLVL_gm 0x03 /* Interrupt level group mask. */ -#define AES_INTLVL_gp 0 /* Interrupt level group position. */ -#define AES_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */ -#define AES_INTLVL0_bp 0 /* Interrupt level bit 0 position. */ -#define AES_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */ -#define AES_INTLVL1_bp 1 /* Interrupt level bit 1 position. */ - -/* CRC - Cyclic Redundancy Checker */ -/* CRC.CTRL bit masks and bit positions */ -#define CRC_RESET_gm 0xC0 /* Reset group mask. */ -#define CRC_RESET_gp 6 /* Reset group position. */ -#define CRC_RESET0_bm (1<<6) /* Reset bit 0 mask. */ -#define CRC_RESET0_bp 6 /* Reset bit 0 position. */ -#define CRC_RESET1_bm (1<<7) /* Reset bit 1 mask. */ -#define CRC_RESET1_bp 7 /* Reset bit 1 position. */ - -#define CRC_CRC32_bm 0x20 /* CRC Mode bit mask. */ -#define CRC_CRC32_bp 5 /* CRC Mode bit position. */ - -#define CRC_SOURCE_gm 0x0F /* Input Source group mask. */ -#define CRC_SOURCE_gp 0 /* Input Source group position. */ -#define CRC_SOURCE0_bm (1<<0) /* Input Source bit 0 mask. */ -#define CRC_SOURCE0_bp 0 /* Input Source bit 0 position. */ -#define CRC_SOURCE1_bm (1<<1) /* Input Source bit 1 mask. */ -#define CRC_SOURCE1_bp 1 /* Input Source bit 1 position. */ -#define CRC_SOURCE2_bm (1<<2) /* Input Source bit 2 mask. */ -#define CRC_SOURCE2_bp 2 /* Input Source bit 2 position. */ -#define CRC_SOURCE3_bm (1<<3) /* Input Source bit 3 mask. */ -#define CRC_SOURCE3_bp 3 /* Input Source bit 3 position. */ - -/* CRC.STATUS bit masks and bit positions */ -#define CRC_ZERO_bm 0x02 /* Zero detection bit mask. */ -#define CRC_ZERO_bp 1 /* Zero detection bit position. */ - -#define CRC_BUSY_bm 0x01 /* Busy bit mask. */ -#define CRC_BUSY_bp 0 /* Busy bit position. */ - -/* DMA - DMA Controller */ -/* DMA_CH.CTRLA bit masks and bit positions */ -#define DMA_CH_CHEN_bm 0x80 /* Channel Enable bit mask. */ -#define DMA_CH_CHEN_bp 7 /* Channel Enable bit position. */ - -#define DMA_CH_CHRST_bm 0x40 /* Channel Software Reset bit mask. */ -#define DMA_CH_CHRST_bp 6 /* Channel Software Reset bit position. */ - -#define DMA_CH_REPEAT_bm 0x20 /* Channel Repeat Mode bit mask. */ -#define DMA_CH_REPEAT_bp 5 /* Channel Repeat Mode bit position. */ - -#define DMA_CH_TRFREQ_bm 0x10 /* Channel Transfer Request bit mask. */ -#define DMA_CH_TRFREQ_bp 4 /* Channel Transfer Request bit position. */ - -#define DMA_CH_SINGLE_bm 0x04 /* Channel Single Shot Data Transfer bit mask. */ -#define DMA_CH_SINGLE_bp 2 /* Channel Single Shot Data Transfer bit position. */ - -#define DMA_CH_BURSTLEN_gm 0x03 /* Channel Transfer Mode group mask. */ -#define DMA_CH_BURSTLEN_gp 0 /* Channel Transfer Mode group position. */ -#define DMA_CH_BURSTLEN0_bm (1<<0) /* Channel Transfer Mode bit 0 mask. */ -#define DMA_CH_BURSTLEN0_bp 0 /* Channel Transfer Mode bit 0 position. */ -#define DMA_CH_BURSTLEN1_bm (1<<1) /* Channel Transfer Mode bit 1 mask. */ -#define DMA_CH_BURSTLEN1_bp 1 /* Channel Transfer Mode bit 1 position. */ - -/* DMA_CH.CTRLB bit masks and bit positions */ -#define DMA_CH_CHBUSY_bm 0x80 /* Block Transfer Busy bit mask. */ -#define DMA_CH_CHBUSY_bp 7 /* Block Transfer Busy bit position. */ - -#define DMA_CH_CHPEND_bm 0x40 /* Block Transfer Pending bit mask. */ -#define DMA_CH_CHPEND_bp 6 /* Block Transfer Pending bit position. */ - -#define DMA_CH_ERRIF_bm 0x20 /* Block Transfer Error Interrupt Flag bit mask. */ -#define DMA_CH_ERRIF_bp 5 /* Block Transfer Error Interrupt Flag bit position. */ - -#define DMA_CH_TRNIF_bm 0x10 /* Transaction Complete Interrup Flag bit mask. */ -#define DMA_CH_TRNIF_bp 4 /* Transaction Complete Interrup Flag bit position. */ - -#define DMA_CH_ERRINTLVL_gm 0x0C /* Transfer Error Interrupt Level group mask. */ -#define DMA_CH_ERRINTLVL_gp 2 /* Transfer Error Interrupt Level group position. */ -#define DMA_CH_ERRINTLVL0_bm (1<<2) /* Transfer Error Interrupt Level bit 0 mask. */ -#define DMA_CH_ERRINTLVL0_bp 2 /* Transfer Error Interrupt Level bit 0 position. */ -#define DMA_CH_ERRINTLVL1_bm (1<<3) /* Transfer Error Interrupt Level bit 1 mask. */ -#define DMA_CH_ERRINTLVL1_bp 3 /* Transfer Error Interrupt Level bit 1 position. */ - -#define DMA_CH_TRNINTLVL_gm 0x03 /* Transaction Complete Interrupt Level group mask. */ -#define DMA_CH_TRNINTLVL_gp 0 /* Transaction Complete Interrupt Level group position. */ -#define DMA_CH_TRNINTLVL0_bm (1<<0) /* Transaction Complete Interrupt Level bit 0 mask. */ -#define DMA_CH_TRNINTLVL0_bp 0 /* Transaction Complete Interrupt Level bit 0 position. */ -#define DMA_CH_TRNINTLVL1_bm (1<<1) /* Transaction Complete Interrupt Level bit 1 mask. */ -#define DMA_CH_TRNINTLVL1_bp 1 /* Transaction Complete Interrupt Level bit 1 position. */ - -/* DMA_CH.ADDRCTRL bit masks and bit positions */ -#define DMA_CH_SRCRELOAD_gm 0xC0 /* Channel Source Address Reload group mask. */ -#define DMA_CH_SRCRELOAD_gp 6 /* Channel Source Address Reload group position. */ -#define DMA_CH_SRCRELOAD0_bm (1<<6) /* Channel Source Address Reload bit 0 mask. */ -#define DMA_CH_SRCRELOAD0_bp 6 /* Channel Source Address Reload bit 0 position. */ -#define DMA_CH_SRCRELOAD1_bm (1<<7) /* Channel Source Address Reload bit 1 mask. */ -#define DMA_CH_SRCRELOAD1_bp 7 /* Channel Source Address Reload bit 1 position. */ - -#define DMA_CH_SRCDIR_gm 0x30 /* Channel Source Address Mode group mask. */ -#define DMA_CH_SRCDIR_gp 4 /* Channel Source Address Mode group position. */ -#define DMA_CH_SRCDIR0_bm (1<<4) /* Channel Source Address Mode bit 0 mask. */ -#define DMA_CH_SRCDIR0_bp 4 /* Channel Source Address Mode bit 0 position. */ -#define DMA_CH_SRCDIR1_bm (1<<5) /* Channel Source Address Mode bit 1 mask. */ -#define DMA_CH_SRCDIR1_bp 5 /* Channel Source Address Mode bit 1 position. */ - -#define DMA_CH_DESTRELOAD_gm 0x0C /* Channel Destination Address Reload group mask. */ -#define DMA_CH_DESTRELOAD_gp 2 /* Channel Destination Address Reload group position. */ -#define DMA_CH_DESTRELOAD0_bm (1<<2) /* Channel Destination Address Reload bit 0 mask. */ -#define DMA_CH_DESTRELOAD0_bp 2 /* Channel Destination Address Reload bit 0 position. */ -#define DMA_CH_DESTRELOAD1_bm (1<<3) /* Channel Destination Address Reload bit 1 mask. */ -#define DMA_CH_DESTRELOAD1_bp 3 /* Channel Destination Address Reload bit 1 position. */ - -#define DMA_CH_DESTDIR_gm 0x03 /* Channel Destination Address Mode group mask. */ -#define DMA_CH_DESTDIR_gp 0 /* Channel Destination Address Mode group position. */ -#define DMA_CH_DESTDIR0_bm (1<<0) /* Channel Destination Address Mode bit 0 mask. */ -#define DMA_CH_DESTDIR0_bp 0 /* Channel Destination Address Mode bit 0 position. */ -#define DMA_CH_DESTDIR1_bm (1<<1) /* Channel Destination Address Mode bit 1 mask. */ -#define DMA_CH_DESTDIR1_bp 1 /* Channel Destination Address Mode bit 1 position. */ - -/* DMA_CH.TRIGSRC bit masks and bit positions */ -#define DMA_CH_TRIGSRC_gm 0xFF /* Channel Trigger Source group mask. */ -#define DMA_CH_TRIGSRC_gp 0 /* Channel Trigger Source group position. */ -#define DMA_CH_TRIGSRC0_bm (1<<0) /* Channel Trigger Source bit 0 mask. */ -#define DMA_CH_TRIGSRC0_bp 0 /* Channel Trigger Source bit 0 position. */ -#define DMA_CH_TRIGSRC1_bm (1<<1) /* Channel Trigger Source bit 1 mask. */ -#define DMA_CH_TRIGSRC1_bp 1 /* Channel Trigger Source bit 1 position. */ -#define DMA_CH_TRIGSRC2_bm (1<<2) /* Channel Trigger Source bit 2 mask. */ -#define DMA_CH_TRIGSRC2_bp 2 /* Channel Trigger Source bit 2 position. */ -#define DMA_CH_TRIGSRC3_bm (1<<3) /* Channel Trigger Source bit 3 mask. */ -#define DMA_CH_TRIGSRC3_bp 3 /* Channel Trigger Source bit 3 position. */ -#define DMA_CH_TRIGSRC4_bm (1<<4) /* Channel Trigger Source bit 4 mask. */ -#define DMA_CH_TRIGSRC4_bp 4 /* Channel Trigger Source bit 4 position. */ -#define DMA_CH_TRIGSRC5_bm (1<<5) /* Channel Trigger Source bit 5 mask. */ -#define DMA_CH_TRIGSRC5_bp 5 /* Channel Trigger Source bit 5 position. */ -#define DMA_CH_TRIGSRC6_bm (1<<6) /* Channel Trigger Source bit 6 mask. */ -#define DMA_CH_TRIGSRC6_bp 6 /* Channel Trigger Source bit 6 position. */ -#define DMA_CH_TRIGSRC7_bm (1<<7) /* Channel Trigger Source bit 7 mask. */ -#define DMA_CH_TRIGSRC7_bp 7 /* Channel Trigger Source bit 7 position. */ - -/* DMA.CTRL bit masks and bit positions */ -#define DMA_ENABLE_bm 0x80 /* Enable bit mask. */ -#define DMA_ENABLE_bp 7 /* Enable bit position. */ - -#define DMA_RESET_bm 0x40 /* Software Reset bit mask. */ -#define DMA_RESET_bp 6 /* Software Reset bit position. */ - -#define DMA_DBUFMODE_bm 0x04 /* Double Buffering Mode bit mask. */ -#define DMA_DBUFMODE_bp 2 /* Double Buffering Mode bit position. */ - -#define DMA_PRIMODE_bm 0x01 /* Channel Priority Mode bit mask. */ -#define DMA_PRIMODE_bp 0 /* Channel Priority Mode bit position. */ - -/* DMA.INTFLAGS bit masks and bit positions */ -#define DMA_CH1ERRIF_bm 0x20 /* Channel 1 Block Transfer Error Interrupt Flag bit mask. */ -#define DMA_CH1ERRIF_bp 5 /* Channel 1 Block Transfer Error Interrupt Flag bit position. */ - -#define DMA_CH0ERRIF_bm 0x10 /* Channel 0 Block Transfer Error Interrupt Flag bit mask. */ -#define DMA_CH0ERRIF_bp 4 /* Channel 0 Block Transfer Error Interrupt Flag bit position. */ - -#define DMA_CH1TRNIF_bm 0x02 /* Channel 1 Transaction Complete Interrupt Flag bit mask. */ -#define DMA_CH1TRNIF_bp 1 /* Channel 1 Transaction Complete Interrupt Flag bit position. */ - -#define DMA_CH0TRNIF_bm 0x01 /* Channel 0 Transaction Complete Interrupt Flag bit mask. */ -#define DMA_CH0TRNIF_bp 0 /* Channel 0 Transaction Complete Interrupt Flag bit position. */ - -/* DMA.STATUS bit masks and bit positions */ -#define DMA_CH1BUSY_bm 0x20 /* Channel 1 Block Transfer Busy bit mask. */ -#define DMA_CH1BUSY_bp 5 /* Channel 1 Block Transfer Busy bit position. */ - -#define DMA_CH0BUSY_bm 0x10 /* Channel 0 Block Transfer Busy bit mask. */ -#define DMA_CH0BUSY_bp 4 /* Channel 0 Block Transfer Busy bit position. */ - -#define DMA_CH1PEND_bm 0x02 /* Channel 1 Block Transfer Pending bit mask. */ -#define DMA_CH1PEND_bp 1 /* Channel 1 Block Transfer Pending bit position. */ - -#define DMA_CH0PEND_bm 0x01 /* Channel 0 Block Transfer Pending bit mask. */ -#define DMA_CH0PEND_bp 0 /* Channel 0 Block Transfer Pending bit position. */ - -/* EVSYS - Event System */ -/* EVSYS.CH0MUX bit masks and bit positions */ -#define EVSYS_CHMUX_gm 0xFF /* Event Channel 0 Multiplexer group mask. */ -#define EVSYS_CHMUX_gp 0 /* Event Channel 0 Multiplexer group position. */ -#define EVSYS_CHMUX0_bm (1<<0) /* Event Channel 0 Multiplexer bit 0 mask. */ -#define EVSYS_CHMUX0_bp 0 /* Event Channel 0 Multiplexer bit 0 position. */ -#define EVSYS_CHMUX1_bm (1<<1) /* Event Channel 0 Multiplexer bit 1 mask. */ -#define EVSYS_CHMUX1_bp 1 /* Event Channel 0 Multiplexer bit 1 position. */ -#define EVSYS_CHMUX2_bm (1<<2) /* Event Channel 0 Multiplexer bit 2 mask. */ -#define EVSYS_CHMUX2_bp 2 /* Event Channel 0 Multiplexer bit 2 position. */ -#define EVSYS_CHMUX3_bm (1<<3) /* Event Channel 0 Multiplexer bit 3 mask. */ -#define EVSYS_CHMUX3_bp 3 /* Event Channel 0 Multiplexer bit 3 position. */ -#define EVSYS_CHMUX4_bm (1<<4) /* Event Channel 0 Multiplexer bit 4 mask. */ -#define EVSYS_CHMUX4_bp 4 /* Event Channel 0 Multiplexer bit 4 position. */ -#define EVSYS_CHMUX5_bm (1<<5) /* Event Channel 0 Multiplexer bit 5 mask. */ -#define EVSYS_CHMUX5_bp 5 /* Event Channel 0 Multiplexer bit 5 position. */ -#define EVSYS_CHMUX6_bm (1<<6) /* Event Channel 0 Multiplexer bit 6 mask. */ -#define EVSYS_CHMUX6_bp 6 /* Event Channel 0 Multiplexer bit 6 position. */ -#define EVSYS_CHMUX7_bm (1<<7) /* Event Channel 0 Multiplexer bit 7 mask. */ -#define EVSYS_CHMUX7_bp 7 /* Event Channel 0 Multiplexer bit 7 position. */ - -/* EVSYS.CH1MUX bit masks and bit positions */ -/* EVSYS_CHMUX Predefined. */ -/* EVSYS_CHMUX Predefined. */ - -/* EVSYS.CH2MUX bit masks and bit positions */ -/* EVSYS_CHMUX Predefined. */ -/* EVSYS_CHMUX Predefined. */ - -/* EVSYS.CH3MUX bit masks and bit positions */ -/* EVSYS_CHMUX Predefined. */ -/* EVSYS_CHMUX Predefined. */ - -/* EVSYS.CH0CTRL bit masks and bit positions */ -#define EVSYS_QDIRM_gm 0x60 /* Quadrature Decoder Index Recognition Mode group mask. */ -#define EVSYS_QDIRM_gp 5 /* Quadrature Decoder Index Recognition Mode group position. */ -#define EVSYS_QDIRM0_bm (1<<5) /* Quadrature Decoder Index Recognition Mode bit 0 mask. */ -#define EVSYS_QDIRM0_bp 5 /* Quadrature Decoder Index Recognition Mode bit 0 position. */ -#define EVSYS_QDIRM1_bm (1<<6) /* Quadrature Decoder Index Recognition Mode bit 1 mask. */ -#define EVSYS_QDIRM1_bp 6 /* Quadrature Decoder Index Recognition Mode bit 1 position. */ - -#define EVSYS_QDIEN_bm 0x10 /* Quadrature Decoder Index Enable bit mask. */ -#define EVSYS_QDIEN_bp 4 /* Quadrature Decoder Index Enable bit position. */ - -#define EVSYS_QDEN_bm 0x08 /* Quadrature Decoder Enable bit mask. */ -#define EVSYS_QDEN_bp 3 /* Quadrature Decoder Enable bit position. */ - -#define EVSYS_DIGFILT_gm 0x07 /* Digital Filter group mask. */ -#define EVSYS_DIGFILT_gp 0 /* Digital Filter group position. */ -#define EVSYS_DIGFILT0_bm (1<<0) /* Digital Filter bit 0 mask. */ -#define EVSYS_DIGFILT0_bp 0 /* Digital Filter bit 0 position. */ -#define EVSYS_DIGFILT1_bm (1<<1) /* Digital Filter bit 1 mask. */ -#define EVSYS_DIGFILT1_bp 1 /* Digital Filter bit 1 position. */ -#define EVSYS_DIGFILT2_bm (1<<2) /* Digital Filter bit 2 mask. */ -#define EVSYS_DIGFILT2_bp 2 /* Digital Filter bit 2 position. */ - -/* EVSYS.CH1CTRL bit masks and bit positions */ -/* EVSYS_DIGFILT Predefined. */ -/* EVSYS_DIGFILT Predefined. */ - -/* EVSYS.CH2CTRL bit masks and bit positions */ -/* EVSYS_DIGFILT Predefined. */ -/* EVSYS_DIGFILT Predefined. */ - -/* EVSYS.CH3CTRL bit masks and bit positions */ -/* EVSYS_DIGFILT Predefined. */ -/* EVSYS_DIGFILT Predefined. */ - -/* NVM - Non Volatile Memory Controller */ -/* NVM.CMD bit masks and bit positions */ -#define NVM_CMD_gm 0x7F /* Command group mask. */ -#define NVM_CMD_gp 0 /* Command group position. */ -#define NVM_CMD0_bm (1<<0) /* Command bit 0 mask. */ -#define NVM_CMD0_bp 0 /* Command bit 0 position. */ -#define NVM_CMD1_bm (1<<1) /* Command bit 1 mask. */ -#define NVM_CMD1_bp 1 /* Command bit 1 position. */ -#define NVM_CMD2_bm (1<<2) /* Command bit 2 mask. */ -#define NVM_CMD2_bp 2 /* Command bit 2 position. */ -#define NVM_CMD3_bm (1<<3) /* Command bit 3 mask. */ -#define NVM_CMD3_bp 3 /* Command bit 3 position. */ -#define NVM_CMD4_bm (1<<4) /* Command bit 4 mask. */ -#define NVM_CMD4_bp 4 /* Command bit 4 position. */ -#define NVM_CMD5_bm (1<<5) /* Command bit 5 mask. */ -#define NVM_CMD5_bp 5 /* Command bit 5 position. */ -#define NVM_CMD6_bm (1<<6) /* Command bit 6 mask. */ -#define NVM_CMD6_bp 6 /* Command bit 6 position. */ - -/* NVM.CTRLA bit masks and bit positions */ -#define NVM_CMDEX_bm 0x01 /* Command Execute bit mask. */ -#define NVM_CMDEX_bp 0 /* Command Execute bit position. */ - -/* NVM.CTRLB bit masks and bit positions */ -#define NVM_EEMAPEN_bm 0x08 /* EEPROM Mapping Enable bit mask. */ -#define NVM_EEMAPEN_bp 3 /* EEPROM Mapping Enable bit position. */ - -#define NVM_FPRM_bm 0x04 /* Flash Power Reduction Enable bit mask. */ -#define NVM_FPRM_bp 2 /* Flash Power Reduction Enable bit position. */ - -#define NVM_EPRM_bm 0x02 /* EEPROM Power Reduction Enable bit mask. */ -#define NVM_EPRM_bp 1 /* EEPROM Power Reduction Enable bit position. */ - -#define NVM_SPMLOCK_bm 0x01 /* SPM Lock bit mask. */ -#define NVM_SPMLOCK_bp 0 /* SPM Lock bit position. */ - -/* NVM.INTCTRL bit masks and bit positions */ -#define NVM_SPMLVL_gm 0x0C /* SPM Interrupt Level group mask. */ -#define NVM_SPMLVL_gp 2 /* SPM Interrupt Level group position. */ -#define NVM_SPMLVL0_bm (1<<2) /* SPM Interrupt Level bit 0 mask. */ -#define NVM_SPMLVL0_bp 2 /* SPM Interrupt Level bit 0 position. */ -#define NVM_SPMLVL1_bm (1<<3) /* SPM Interrupt Level bit 1 mask. */ -#define NVM_SPMLVL1_bp 3 /* SPM Interrupt Level bit 1 position. */ - -#define NVM_EELVL_gm 0x03 /* EEPROM Interrupt Level group mask. */ -#define NVM_EELVL_gp 0 /* EEPROM Interrupt Level group position. */ -#define NVM_EELVL0_bm (1<<0) /* EEPROM Interrupt Level bit 0 mask. */ -#define NVM_EELVL0_bp 0 /* EEPROM Interrupt Level bit 0 position. */ -#define NVM_EELVL1_bm (1<<1) /* EEPROM Interrupt Level bit 1 mask. */ -#define NVM_EELVL1_bp 1 /* EEPROM Interrupt Level bit 1 position. */ - -/* NVM.STATUS bit masks and bit positions */ -#define NVM_NVMBUSY_bm 0x80 /* Non-volatile Memory Busy bit mask. */ -#define NVM_NVMBUSY_bp 7 /* Non-volatile Memory Busy bit position. */ - -#define NVM_FBUSY_bm 0x40 /* Flash Memory Busy bit mask. */ -#define NVM_FBUSY_bp 6 /* Flash Memory Busy bit position. */ - -#define NVM_EELOAD_bm 0x02 /* EEPROM Page Buffer Active Loading bit mask. */ -#define NVM_EELOAD_bp 1 /* EEPROM Page Buffer Active Loading bit position. */ - -#define NVM_FLOAD_bm 0x01 /* Flash Page Buffer Active Loading bit mask. */ -#define NVM_FLOAD_bp 0 /* Flash Page Buffer Active Loading bit position. */ - -/* NVM.LOCKBITS bit masks and bit positions */ -#define NVM_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ -#define NVM_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ -#define NVM_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ -#define NVM_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ -#define NVM_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ -#define NVM_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ - -#define NVM_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ -#define NVM_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ -#define NVM_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ -#define NVM_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ -#define NVM_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ -#define NVM_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ - -#define NVM_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ -#define NVM_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ -#define NVM_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ -#define NVM_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ -#define NVM_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ -#define NVM_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ - -#define NVM_LB_gm 0x03 /* Lock Bits group mask. */ -#define NVM_LB_gp 0 /* Lock Bits group position. */ -#define NVM_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ -#define NVM_LB0_bp 0 /* Lock Bits bit 0 position. */ -#define NVM_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ -#define NVM_LB1_bp 1 /* Lock Bits bit 1 position. */ - -/* ADC - Analog/Digital Converter */ -/* ADC_CH.CTRL bit masks and bit positions */ -#define ADC_CH_START_bm 0x80 /* Channel Start Conversion bit mask. */ -#define ADC_CH_START_bp 7 /* Channel Start Conversion bit position. */ - -#define ADC_CH_GAIN_gm 0x1C /* Gain Factor group mask. */ -#define ADC_CH_GAIN_gp 2 /* Gain Factor group position. */ -#define ADC_CH_GAIN0_bm (1<<2) /* Gain Factor bit 0 mask. */ -#define ADC_CH_GAIN0_bp 2 /* Gain Factor bit 0 position. */ -#define ADC_CH_GAIN1_bm (1<<3) /* Gain Factor bit 1 mask. */ -#define ADC_CH_GAIN1_bp 3 /* Gain Factor bit 1 position. */ -#define ADC_CH_GAIN2_bm (1<<4) /* Gain Factor bit 2 mask. */ -#define ADC_CH_GAIN2_bp 4 /* Gain Factor bit 2 position. */ - -#define ADC_CH_INPUTMODE_gm 0x03 /* Input Mode Select group mask. */ -#define ADC_CH_INPUTMODE_gp 0 /* Input Mode Select group position. */ -#define ADC_CH_INPUTMODE0_bm (1<<0) /* Input Mode Select bit 0 mask. */ -#define ADC_CH_INPUTMODE0_bp 0 /* Input Mode Select bit 0 position. */ -#define ADC_CH_INPUTMODE1_bm (1<<1) /* Input Mode Select bit 1 mask. */ -#define ADC_CH_INPUTMODE1_bp 1 /* Input Mode Select bit 1 position. */ - -/* ADC_CH.MUXCTRL bit masks and bit positions */ -#define ADC_CH_MUXPOS_gm 0x78 /* MUX selection on Positive ADC input group mask. */ -#define ADC_CH_MUXPOS_gp 3 /* MUX selection on Positive ADC input group position. */ -#define ADC_CH_MUXPOS0_bm (1<<3) /* MUX selection on Positive ADC input bit 0 mask. */ -#define ADC_CH_MUXPOS0_bp 3 /* MUX selection on Positive ADC input bit 0 position. */ -#define ADC_CH_MUXPOS1_bm (1<<4) /* MUX selection on Positive ADC input bit 1 mask. */ -#define ADC_CH_MUXPOS1_bp 4 /* MUX selection on Positive ADC input bit 1 position. */ -#define ADC_CH_MUXPOS2_bm (1<<5) /* MUX selection on Positive ADC input bit 2 mask. */ -#define ADC_CH_MUXPOS2_bp 5 /* MUX selection on Positive ADC input bit 2 position. */ -#define ADC_CH_MUXPOS3_bm (1<<6) /* MUX selection on Positive ADC input bit 3 mask. */ -#define ADC_CH_MUXPOS3_bp 6 /* MUX selection on Positive ADC input bit 3 position. */ - -#define ADC_CH_MUXINT_gm 0x78 /* MUX selection on Internal ADC input group mask. */ -#define ADC_CH_MUXINT_gp 3 /* MUX selection on Internal ADC input group position. */ -#define ADC_CH_MUXINT0_bm (1<<3) /* MUX selection on Internal ADC input bit 0 mask. */ -#define ADC_CH_MUXINT0_bp 3 /* MUX selection on Internal ADC input bit 0 position. */ -#define ADC_CH_MUXINT1_bm (1<<4) /* MUX selection on Internal ADC input bit 1 mask. */ -#define ADC_CH_MUXINT1_bp 4 /* MUX selection on Internal ADC input bit 1 position. */ -#define ADC_CH_MUXINT2_bm (1<<5) /* MUX selection on Internal ADC input bit 2 mask. */ -#define ADC_CH_MUXINT2_bp 5 /* MUX selection on Internal ADC input bit 2 position. */ -#define ADC_CH_MUXINT3_bm (1<<6) /* MUX selection on Internal ADC input bit 3 mask. */ -#define ADC_CH_MUXINT3_bp 6 /* MUX selection on Internal ADC input bit 3 position. */ - -#define ADC_CH_MUXNEG_gm 0x03 /* MUX selection on Negative ADC input group mask. */ -#define ADC_CH_MUXNEG_gp 0 /* MUX selection on Negative ADC input group position. */ -#define ADC_CH_MUXNEG0_bm (1<<0) /* MUX selection on Negative ADC input bit 0 mask. */ -#define ADC_CH_MUXNEG0_bp 0 /* MUX selection on Negative ADC input bit 0 position. */ -#define ADC_CH_MUXNEG1_bm (1<<1) /* MUX selection on Negative ADC input bit 1 mask. */ -#define ADC_CH_MUXNEG1_bp 1 /* MUX selection on Negative ADC input bit 1 position. */ - -/* ADC_CH.INTCTRL bit masks and bit positions */ -#define ADC_CH_INTMODE_gm 0x0C /* Interrupt Mode group mask. */ -#define ADC_CH_INTMODE_gp 2 /* Interrupt Mode group position. */ -#define ADC_CH_INTMODE0_bm (1<<2) /* Interrupt Mode bit 0 mask. */ -#define ADC_CH_INTMODE0_bp 2 /* Interrupt Mode bit 0 position. */ -#define ADC_CH_INTMODE1_bm (1<<3) /* Interrupt Mode bit 1 mask. */ -#define ADC_CH_INTMODE1_bp 3 /* Interrupt Mode bit 1 position. */ - -#define ADC_CH_INTLVL_gm 0x03 /* Interrupt Level group mask. */ -#define ADC_CH_INTLVL_gp 0 /* Interrupt Level group position. */ -#define ADC_CH_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */ -#define ADC_CH_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */ -#define ADC_CH_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ -#define ADC_CH_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */ - -/* ADC_CH.INTFLAGS bit masks and bit positions */ -#define ADC_CH_CHIF_bm 0x01 /* Channel Interrupt Flag bit mask. */ -#define ADC_CH_CHIF_bp 0 /* Channel Interrupt Flag bit position. */ - -/* ADC_CH.SCAN bit masks and bit positions */ -#define ADC_CH_OFFSET_gm 0xF0 /* Positive MUX setting offset group mask. */ -#define ADC_CH_OFFSET_gp 4 /* Positive MUX setting offset group position. */ -#define ADC_CH_OFFSET0_bm (1<<4) /* Positive MUX setting offset bit 0 mask. */ -#define ADC_CH_OFFSET0_bp 4 /* Positive MUX setting offset bit 0 position. */ -#define ADC_CH_OFFSET1_bm (1<<5) /* Positive MUX setting offset bit 1 mask. */ -#define ADC_CH_OFFSET1_bp 5 /* Positive MUX setting offset bit 1 position. */ -#define ADC_CH_OFFSET2_bm (1<<6) /* Positive MUX setting offset bit 2 mask. */ -#define ADC_CH_OFFSET2_bp 6 /* Positive MUX setting offset bit 2 position. */ -#define ADC_CH_OFFSET3_bm (1<<7) /* Positive MUX setting offset bit 3 mask. */ -#define ADC_CH_OFFSET3_bp 7 /* Positive MUX setting offset bit 3 position. */ - -#define ADC_CH_COUNT_gm 0x0F /* Number of Channels included in scan group mask. */ -#define ADC_CH_COUNT_gp 0 /* Number of Channels included in scan group position. */ -#define ADC_CH_COUNT0_bm (1<<0) /* Number of Channels included in scan bit 0 mask. */ -#define ADC_CH_COUNT0_bp 0 /* Number of Channels included in scan bit 0 position. */ -#define ADC_CH_COUNT1_bm (1<<1) /* Number of Channels included in scan bit 1 mask. */ -#define ADC_CH_COUNT1_bp 1 /* Number of Channels included in scan bit 1 position. */ -#define ADC_CH_COUNT2_bm (1<<2) /* Number of Channels included in scan bit 2 mask. */ -#define ADC_CH_COUNT2_bp 2 /* Number of Channels included in scan bit 2 position. */ -#define ADC_CH_COUNT3_bm (1<<3) /* Number of Channels included in scan bit 3 mask. */ -#define ADC_CH_COUNT3_bp 3 /* Number of Channels included in scan bit 3 position. */ - -/* ADC.CTRLA bit masks and bit positions */ -#define ADC_CH0START_bm 0x04 /* Channel 0 Start Conversion bit mask. */ -#define ADC_CH0START_bp 2 /* Channel 0 Start Conversion bit position. */ - -#define ADC_FLUSH_bm 0x02 /* ADC Flush bit mask. */ -#define ADC_FLUSH_bp 1 /* ADC Flush bit position. */ - -#define ADC_ENABLE_bm 0x01 /* Enable ADC bit mask. */ -#define ADC_ENABLE_bp 0 /* Enable ADC bit position. */ - -/* ADC.CTRLB bit masks and bit positions */ -#define ADC_CURRLIMIT_gm 0x60 /* Current limit group mask. */ -#define ADC_CURRLIMIT_gp 5 /* Current limit group position. */ -#define ADC_CURRLIMIT0_bm (1<<5) /* Current limit bit 0 mask. */ -#define ADC_CURRLIMIT0_bp 5 /* Current limit bit 0 position. */ -#define ADC_CURRLIMIT1_bm (1<<6) /* Current limit bit 1 mask. */ -#define ADC_CURRLIMIT1_bp 6 /* Current limit bit 1 position. */ - -#define ADC_CONMODE_bm 0x10 /* Conversion Mode bit mask. */ -#define ADC_CONMODE_bp 4 /* Conversion Mode bit position. */ - -#define ADC_FREERUN_bm 0x08 /* Free Running Mode Enable bit mask. */ -#define ADC_FREERUN_bp 3 /* Free Running Mode Enable bit position. */ - -#define ADC_RESOLUTION_gm 0x06 /* Result Resolution group mask. */ -#define ADC_RESOLUTION_gp 1 /* Result Resolution group position. */ -#define ADC_RESOLUTION0_bm (1<<1) /* Result Resolution bit 0 mask. */ -#define ADC_RESOLUTION0_bp 1 /* Result Resolution bit 0 position. */ -#define ADC_RESOLUTION1_bm (1<<2) /* Result Resolution bit 1 mask. */ -#define ADC_RESOLUTION1_bp 2 /* Result Resolution bit 1 position. */ - -/* ADC.REFCTRL bit masks and bit positions */ -#define ADC_REFSEL_gm 0x70 /* Reference Selection group mask. */ -#define ADC_REFSEL_gp 4 /* Reference Selection group position. */ -#define ADC_REFSEL0_bm (1<<4) /* Reference Selection bit 0 mask. */ -#define ADC_REFSEL0_bp 4 /* Reference Selection bit 0 position. */ -#define ADC_REFSEL1_bm (1<<5) /* Reference Selection bit 1 mask. */ -#define ADC_REFSEL1_bp 5 /* Reference Selection bit 1 position. */ -#define ADC_REFSEL2_bm (1<<6) /* Reference Selection bit 2 mask. */ -#define ADC_REFSEL2_bp 6 /* Reference Selection bit 2 position. */ - -#define ADC_BANDGAP_bm 0x02 /* Bandgap enable bit mask. */ -#define ADC_BANDGAP_bp 1 /* Bandgap enable bit position. */ - -#define ADC_TEMPREF_bm 0x01 /* Temperature Reference Enable bit mask. */ -#define ADC_TEMPREF_bp 0 /* Temperature Reference Enable bit position. */ - -/* ADC.EVCTRL bit masks and bit positions */ -#define ADC_EVSEL_gm 0x18 /* Event Input Select group mask. */ -#define ADC_EVSEL_gp 3 /* Event Input Select group position. */ -#define ADC_EVSEL0_bm (1<<3) /* Event Input Select bit 0 mask. */ -#define ADC_EVSEL0_bp 3 /* Event Input Select bit 0 position. */ -#define ADC_EVSEL1_bm (1<<4) /* Event Input Select bit 1 mask. */ -#define ADC_EVSEL1_bp 4 /* Event Input Select bit 1 position. */ - -#define ADC_EVACT_gm 0x07 /* Event Action Select group mask. */ -#define ADC_EVACT_gp 0 /* Event Action Select group position. */ -#define ADC_EVACT0_bm (1<<0) /* Event Action Select bit 0 mask. */ -#define ADC_EVACT0_bp 0 /* Event Action Select bit 0 position. */ -#define ADC_EVACT1_bm (1<<1) /* Event Action Select bit 1 mask. */ -#define ADC_EVACT1_bp 1 /* Event Action Select bit 1 position. */ -#define ADC_EVACT2_bm (1<<2) /* Event Action Select bit 2 mask. */ -#define ADC_EVACT2_bp 2 /* Event Action Select bit 2 position. */ - -/* ADC.PRESCALER bit masks and bit positions */ -#define ADC_PRESCALER_gm 0x07 /* Clock Prescaler Selection group mask. */ -#define ADC_PRESCALER_gp 0 /* Clock Prescaler Selection group position. */ -#define ADC_PRESCALER0_bm (1<<0) /* Clock Prescaler Selection bit 0 mask. */ -#define ADC_PRESCALER0_bp 0 /* Clock Prescaler Selection bit 0 position. */ -#define ADC_PRESCALER1_bm (1<<1) /* Clock Prescaler Selection bit 1 mask. */ -#define ADC_PRESCALER1_bp 1 /* Clock Prescaler Selection bit 1 position. */ -#define ADC_PRESCALER2_bm (1<<2) /* Clock Prescaler Selection bit 2 mask. */ -#define ADC_PRESCALER2_bp 2 /* Clock Prescaler Selection bit 2 position. */ - -/* ADC.INTFLAGS bit masks and bit positions */ -#define ADC_CH0IF_bm 0x01 /* Channel 0 Interrupt Flag bit mask. */ -#define ADC_CH0IF_bp 0 /* Channel 0 Interrupt Flag bit position. */ - -/* ADC.SAMPCTRL bit masks and bit positions */ -#define ADC_SAMPVAL_gm 0x3F /* Sampling time control register group mask. */ -#define ADC_SAMPVAL_gp 0 /* Sampling time control register group position. */ -#define ADC_SAMPVAL0_bm (1<<0) /* Sampling time control register bit 0 mask. */ -#define ADC_SAMPVAL0_bp 0 /* Sampling time control register bit 0 position. */ -#define ADC_SAMPVAL1_bm (1<<1) /* Sampling time control register bit 1 mask. */ -#define ADC_SAMPVAL1_bp 1 /* Sampling time control register bit 1 position. */ -#define ADC_SAMPVAL2_bm (1<<2) /* Sampling time control register bit 2 mask. */ -#define ADC_SAMPVAL2_bp 2 /* Sampling time control register bit 2 position. */ -#define ADC_SAMPVAL3_bm (1<<3) /* Sampling time control register bit 3 mask. */ -#define ADC_SAMPVAL3_bp 3 /* Sampling time control register bit 3 position. */ -#define ADC_SAMPVAL4_bm (1<<4) /* Sampling time control register bit 4 mask. */ -#define ADC_SAMPVAL4_bp 4 /* Sampling time control register bit 4 position. */ -#define ADC_SAMPVAL5_bm (1<<5) /* Sampling time control register bit 5 mask. */ -#define ADC_SAMPVAL5_bp 5 /* Sampling time control register bit 5 position. */ - -/* AC - Analog Comparator */ -/* AC.AC0CTRL bit masks and bit positions */ -#define AC_INTMODE_gm 0xC0 /* Interrupt Mode group mask. */ -#define AC_INTMODE_gp 6 /* Interrupt Mode group position. */ -#define AC_INTMODE0_bm (1<<6) /* Interrupt Mode bit 0 mask. */ -#define AC_INTMODE0_bp 6 /* Interrupt Mode bit 0 position. */ -#define AC_INTMODE1_bm (1<<7) /* Interrupt Mode bit 1 mask. */ -#define AC_INTMODE1_bp 7 /* Interrupt Mode bit 1 position. */ - -#define AC_INTLVL_gm 0x30 /* Interrupt Level group mask. */ -#define AC_INTLVL_gp 4 /* Interrupt Level group position. */ -#define AC_INTLVL0_bm (1<<4) /* Interrupt Level bit 0 mask. */ -#define AC_INTLVL0_bp 4 /* Interrupt Level bit 0 position. */ -#define AC_INTLVL1_bm (1<<5) /* Interrupt Level bit 1 mask. */ -#define AC_INTLVL1_bp 5 /* Interrupt Level bit 1 position. */ - -#define AC_HYSMODE_gm 0x06 /* Hysteresis Mode group mask. */ -#define AC_HYSMODE_gp 1 /* Hysteresis Mode group position. */ -#define AC_HYSMODE0_bm (1<<1) /* Hysteresis Mode bit 0 mask. */ -#define AC_HYSMODE0_bp 1 /* Hysteresis Mode bit 0 position. */ -#define AC_HYSMODE1_bm (1<<2) /* Hysteresis Mode bit 1 mask. */ -#define AC_HYSMODE1_bp 2 /* Hysteresis Mode bit 1 position. */ - -#define AC_ENABLE_bm 0x01 /* Enable bit mask. */ -#define AC_ENABLE_bp 0 /* Enable bit position. */ - -/* AC.AC1CTRL bit masks and bit positions */ -/* AC_INTMODE Predefined. */ -/* AC_INTMODE Predefined. */ - -/* AC_INTLVL Predefined. */ -/* AC_INTLVL Predefined. */ - -/* AC_HYSMODE Predefined. */ -/* AC_HYSMODE Predefined. */ - -/* AC_ENABLE Predefined. */ -/* AC_ENABLE Predefined. */ - -/* AC.AC0MUXCTRL bit masks and bit positions */ -#define AC_MUXPOS_gm 0x38 /* MUX Positive Input group mask. */ -#define AC_MUXPOS_gp 3 /* MUX Positive Input group position. */ -#define AC_MUXPOS0_bm (1<<3) /* MUX Positive Input bit 0 mask. */ -#define AC_MUXPOS0_bp 3 /* MUX Positive Input bit 0 position. */ -#define AC_MUXPOS1_bm (1<<4) /* MUX Positive Input bit 1 mask. */ -#define AC_MUXPOS1_bp 4 /* MUX Positive Input bit 1 position. */ -#define AC_MUXPOS2_bm (1<<5) /* MUX Positive Input bit 2 mask. */ -#define AC_MUXPOS2_bp 5 /* MUX Positive Input bit 2 position. */ - -#define AC_MUXNEG_gm 0x07 /* MUX Negative Input group mask. */ -#define AC_MUXNEG_gp 0 /* MUX Negative Input group position. */ -#define AC_MUXNEG0_bm (1<<0) /* MUX Negative Input bit 0 mask. */ -#define AC_MUXNEG0_bp 0 /* MUX Negative Input bit 0 position. */ -#define AC_MUXNEG1_bm (1<<1) /* MUX Negative Input bit 1 mask. */ -#define AC_MUXNEG1_bp 1 /* MUX Negative Input bit 1 position. */ -#define AC_MUXNEG2_bm (1<<2) /* MUX Negative Input bit 2 mask. */ -#define AC_MUXNEG2_bp 2 /* MUX Negative Input bit 2 position. */ - -/* AC.AC1MUXCTRL bit masks and bit positions */ -/* AC_MUXPOS Predefined. */ -/* AC_MUXPOS Predefined. */ - -/* AC_MUXNEG Predefined. */ -/* AC_MUXNEG Predefined. */ - -/* AC.CTRLA bit masks and bit positions */ -#define AC_AC1OUT_bm 0x02 /* Analog Comparator 1 Output Enable bit mask. */ -#define AC_AC1OUT_bp 1 /* Analog Comparator 1 Output Enable bit position. */ - -#define AC_AC0OUT_bm 0x01 /* Analog Comparator 0 Output Enable bit mask. */ -#define AC_AC0OUT_bp 0 /* Analog Comparator 0 Output Enable bit position. */ - -/* AC.CTRLB bit masks and bit positions */ -#define AC_SCALEFAC_gm 0x3F /* VCC Voltage Scaler Factor group mask. */ -#define AC_SCALEFAC_gp 0 /* VCC Voltage Scaler Factor group position. */ -#define AC_SCALEFAC0_bm (1<<0) /* VCC Voltage Scaler Factor bit 0 mask. */ -#define AC_SCALEFAC0_bp 0 /* VCC Voltage Scaler Factor bit 0 position. */ -#define AC_SCALEFAC1_bm (1<<1) /* VCC Voltage Scaler Factor bit 1 mask. */ -#define AC_SCALEFAC1_bp 1 /* VCC Voltage Scaler Factor bit 1 position. */ -#define AC_SCALEFAC2_bm (1<<2) /* VCC Voltage Scaler Factor bit 2 mask. */ -#define AC_SCALEFAC2_bp 2 /* VCC Voltage Scaler Factor bit 2 position. */ -#define AC_SCALEFAC3_bm (1<<3) /* VCC Voltage Scaler Factor bit 3 mask. */ -#define AC_SCALEFAC3_bp 3 /* VCC Voltage Scaler Factor bit 3 position. */ -#define AC_SCALEFAC4_bm (1<<4) /* VCC Voltage Scaler Factor bit 4 mask. */ -#define AC_SCALEFAC4_bp 4 /* VCC Voltage Scaler Factor bit 4 position. */ -#define AC_SCALEFAC5_bm (1<<5) /* VCC Voltage Scaler Factor bit 5 mask. */ -#define AC_SCALEFAC5_bp 5 /* VCC Voltage Scaler Factor bit 5 position. */ - -/* AC.WINCTRL bit masks and bit positions */ -#define AC_WEN_bm 0x10 /* Window Mode Enable bit mask. */ -#define AC_WEN_bp 4 /* Window Mode Enable bit position. */ - -#define AC_WINTMODE_gm 0x0C /* Window Interrupt Mode group mask. */ -#define AC_WINTMODE_gp 2 /* Window Interrupt Mode group position. */ -#define AC_WINTMODE0_bm (1<<2) /* Window Interrupt Mode bit 0 mask. */ -#define AC_WINTMODE0_bp 2 /* Window Interrupt Mode bit 0 position. */ -#define AC_WINTMODE1_bm (1<<3) /* Window Interrupt Mode bit 1 mask. */ -#define AC_WINTMODE1_bp 3 /* Window Interrupt Mode bit 1 position. */ - -#define AC_WINTLVL_gm 0x03 /* Window Interrupt Level group mask. */ -#define AC_WINTLVL_gp 0 /* Window Interrupt Level group position. */ -#define AC_WINTLVL0_bm (1<<0) /* Window Interrupt Level bit 0 mask. */ -#define AC_WINTLVL0_bp 0 /* Window Interrupt Level bit 0 position. */ -#define AC_WINTLVL1_bm (1<<1) /* Window Interrupt Level bit 1 mask. */ -#define AC_WINTLVL1_bp 1 /* Window Interrupt Level bit 1 position. */ - -/* AC.STATUS bit masks and bit positions */ -#define AC_WSTATE_gm 0xC0 /* Window Mode State group mask. */ -#define AC_WSTATE_gp 6 /* Window Mode State group position. */ -#define AC_WSTATE0_bm (1<<6) /* Window Mode State bit 0 mask. */ -#define AC_WSTATE0_bp 6 /* Window Mode State bit 0 position. */ -#define AC_WSTATE1_bm (1<<7) /* Window Mode State bit 1 mask. */ -#define AC_WSTATE1_bp 7 /* Window Mode State bit 1 position. */ - -#define AC_AC1STATE_bm 0x20 /* Analog Comparator 1 State bit mask. */ -#define AC_AC1STATE_bp 5 /* Analog Comparator 1 State bit position. */ - -#define AC_AC0STATE_bm 0x10 /* Analog Comparator 0 State bit mask. */ -#define AC_AC0STATE_bp 4 /* Analog Comparator 0 State bit position. */ - -#define AC_WIF_bm 0x04 /* Window Mode Interrupt Flag bit mask. */ -#define AC_WIF_bp 2 /* Window Mode Interrupt Flag bit position. */ - -#define AC_AC1IF_bm 0x02 /* Analog Comparator 1 Interrupt Flag bit mask. */ -#define AC_AC1IF_bp 1 /* Analog Comparator 1 Interrupt Flag bit position. */ - -#define AC_AC0IF_bm 0x01 /* Analog Comparator 0 Interrupt Flag bit mask. */ -#define AC_AC0IF_bp 0 /* Analog Comparator 0 Interrupt Flag bit position. */ - -/* AC.CURRCTRL bit masks and bit positions */ -#define AC_CURREN_bm 0x80 /* Current Source Enable bit mask. */ -#define AC_CURREN_bp 7 /* Current Source Enable bit position. */ - -#define AC_CURRMODE_bm 0x40 /* Current Mode bit mask. */ -#define AC_CURRMODE_bp 6 /* Current Mode bit position. */ - -#define AC_AC1CURR_bm 0x02 /* Analog Comparator 1 current source output bit mask. */ -#define AC_AC1CURR_bp 1 /* Analog Comparator 1 current source output bit position. */ - -#define AC_AC0CURR_bm 0x01 /* Analog Comparator 0 current source output bit mask. */ -#define AC_AC0CURR_bp 0 /* Analog Comparator 0 current source output bit position. */ - -/* AC.CURRCALIB bit masks and bit positions */ -#define AC_CALIB_gm 0x0F /* Current Source Calibration group mask. */ -#define AC_CALIB_gp 0 /* Current Source Calibration group position. */ -#define AC_CALIB0_bm (1<<0) /* Current Source Calibration bit 0 mask. */ -#define AC_CALIB0_bp 0 /* Current Source Calibration bit 0 position. */ -#define AC_CALIB1_bm (1<<1) /* Current Source Calibration bit 1 mask. */ -#define AC_CALIB1_bp 1 /* Current Source Calibration bit 1 position. */ -#define AC_CALIB2_bm (1<<2) /* Current Source Calibration bit 2 mask. */ -#define AC_CALIB2_bp 2 /* Current Source Calibration bit 2 position. */ -#define AC_CALIB3_bm (1<<3) /* Current Source Calibration bit 3 mask. */ -#define AC_CALIB3_bp 3 /* Current Source Calibration bit 3 position. */ - -/* RTC - Real-Time Counter */ -/* RTC.CTRL bit masks and bit positions */ -#define RTC_PRESCALER_gm 0x07 /* Prescaling Factor group mask. */ -#define RTC_PRESCALER_gp 0 /* Prescaling Factor group position. */ -#define RTC_PRESCALER0_bm (1<<0) /* Prescaling Factor bit 0 mask. */ -#define RTC_PRESCALER0_bp 0 /* Prescaling Factor bit 0 position. */ -#define RTC_PRESCALER1_bm (1<<1) /* Prescaling Factor bit 1 mask. */ -#define RTC_PRESCALER1_bp 1 /* Prescaling Factor bit 1 position. */ -#define RTC_PRESCALER2_bm (1<<2) /* Prescaling Factor bit 2 mask. */ -#define RTC_PRESCALER2_bp 2 /* Prescaling Factor bit 2 position. */ - -/* RTC.STATUS bit masks and bit positions */ -#define RTC_SYNCBUSY_bm 0x01 /* Synchronization Busy Flag bit mask. */ -#define RTC_SYNCBUSY_bp 0 /* Synchronization Busy Flag bit position. */ - -/* RTC.INTCTRL bit masks and bit positions */ -#define RTC_COMPINTLVL_gm 0x0C /* Compare Match Interrupt Level group mask. */ -#define RTC_COMPINTLVL_gp 2 /* Compare Match Interrupt Level group position. */ -#define RTC_COMPINTLVL0_bm (1<<2) /* Compare Match Interrupt Level bit 0 mask. */ -#define RTC_COMPINTLVL0_bp 2 /* Compare Match Interrupt Level bit 0 position. */ -#define RTC_COMPINTLVL1_bm (1<<3) /* Compare Match Interrupt Level bit 1 mask. */ -#define RTC_COMPINTLVL1_bp 3 /* Compare Match Interrupt Level bit 1 position. */ - -#define RTC_OVFINTLVL_gm 0x03 /* Overflow Interrupt Level group mask. */ -#define RTC_OVFINTLVL_gp 0 /* Overflow Interrupt Level group position. */ -#define RTC_OVFINTLVL0_bm (1<<0) /* Overflow Interrupt Level bit 0 mask. */ -#define RTC_OVFINTLVL0_bp 0 /* Overflow Interrupt Level bit 0 position. */ -#define RTC_OVFINTLVL1_bm (1<<1) /* Overflow Interrupt Level bit 1 mask. */ -#define RTC_OVFINTLVL1_bp 1 /* Overflow Interrupt Level bit 1 position. */ - -/* RTC.INTFLAGS bit masks and bit positions */ -#define RTC_COMPIF_bm 0x02 /* Compare Match Interrupt Flag bit mask. */ -#define RTC_COMPIF_bp 1 /* Compare Match Interrupt Flag bit position. */ - -#define RTC_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ -#define RTC_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ - -/* TWI - Two-Wire Interface */ -/* TWI_MASTER.CTRLA bit masks and bit positions */ -#define TWI_MASTER_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ -#define TWI_MASTER_INTLVL_gp 6 /* Interrupt Level group position. */ -#define TWI_MASTER_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ -#define TWI_MASTER_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ -#define TWI_MASTER_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ -#define TWI_MASTER_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ - -#define TWI_MASTER_RIEN_bm 0x20 /* Read Interrupt Enable bit mask. */ -#define TWI_MASTER_RIEN_bp 5 /* Read Interrupt Enable bit position. */ - -#define TWI_MASTER_WIEN_bm 0x10 /* Write Interrupt Enable bit mask. */ -#define TWI_MASTER_WIEN_bp 4 /* Write Interrupt Enable bit position. */ - -#define TWI_MASTER_ENABLE_bm 0x08 /* Enable TWI Master bit mask. */ -#define TWI_MASTER_ENABLE_bp 3 /* Enable TWI Master bit position. */ - -/* TWI_MASTER.CTRLB bit masks and bit positions */ -#define TWI_MASTER_TIMEOUT_gm 0x0C /* Inactive Bus Timeout group mask. */ -#define TWI_MASTER_TIMEOUT_gp 2 /* Inactive Bus Timeout group position. */ -#define TWI_MASTER_TIMEOUT0_bm (1<<2) /* Inactive Bus Timeout bit 0 mask. */ -#define TWI_MASTER_TIMEOUT0_bp 2 /* Inactive Bus Timeout bit 0 position. */ -#define TWI_MASTER_TIMEOUT1_bm (1<<3) /* Inactive Bus Timeout bit 1 mask. */ -#define TWI_MASTER_TIMEOUT1_bp 3 /* Inactive Bus Timeout bit 1 position. */ - -#define TWI_MASTER_QCEN_bm 0x02 /* Quick Command Enable bit mask. */ -#define TWI_MASTER_QCEN_bp 1 /* Quick Command Enable bit position. */ - -#define TWI_MASTER_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ -#define TWI_MASTER_SMEN_bp 0 /* Smart Mode Enable bit position. */ - -/* TWI_MASTER.CTRLC bit masks and bit positions */ -#define TWI_MASTER_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ -#define TWI_MASTER_ACKACT_bp 2 /* Acknowledge Action bit position. */ - -#define TWI_MASTER_CMD_gm 0x03 /* Command group mask. */ -#define TWI_MASTER_CMD_gp 0 /* Command group position. */ -#define TWI_MASTER_CMD0_bm (1<<0) /* Command bit 0 mask. */ -#define TWI_MASTER_CMD0_bp 0 /* Command bit 0 position. */ -#define TWI_MASTER_CMD1_bm (1<<1) /* Command bit 1 mask. */ -#define TWI_MASTER_CMD1_bp 1 /* Command bit 1 position. */ - -/* TWI_MASTER.STATUS bit masks and bit positions */ -#define TWI_MASTER_RIF_bm 0x80 /* Read Interrupt Flag bit mask. */ -#define TWI_MASTER_RIF_bp 7 /* Read Interrupt Flag bit position. */ - -#define TWI_MASTER_WIF_bm 0x40 /* Write Interrupt Flag bit mask. */ -#define TWI_MASTER_WIF_bp 6 /* Write Interrupt Flag bit position. */ - -#define TWI_MASTER_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ -#define TWI_MASTER_CLKHOLD_bp 5 /* Clock Hold bit position. */ - -#define TWI_MASTER_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ -#define TWI_MASTER_RXACK_bp 4 /* Received Acknowledge bit position. */ - -#define TWI_MASTER_ARBLOST_bm 0x08 /* Arbitration Lost bit mask. */ -#define TWI_MASTER_ARBLOST_bp 3 /* Arbitration Lost bit position. */ - -#define TWI_MASTER_BUSERR_bm 0x04 /* Bus Error bit mask. */ -#define TWI_MASTER_BUSERR_bp 2 /* Bus Error bit position. */ - -#define TWI_MASTER_BUSSTATE_gm 0x03 /* Bus State group mask. */ -#define TWI_MASTER_BUSSTATE_gp 0 /* Bus State group position. */ -#define TWI_MASTER_BUSSTATE0_bm (1<<0) /* Bus State bit 0 mask. */ -#define TWI_MASTER_BUSSTATE0_bp 0 /* Bus State bit 0 position. */ -#define TWI_MASTER_BUSSTATE1_bm (1<<1) /* Bus State bit 1 mask. */ -#define TWI_MASTER_BUSSTATE1_bp 1 /* Bus State bit 1 position. */ - -/* TWI_SLAVE.CTRLA bit masks and bit positions */ -#define TWI_SLAVE_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ -#define TWI_SLAVE_INTLVL_gp 6 /* Interrupt Level group position. */ -#define TWI_SLAVE_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ -#define TWI_SLAVE_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ -#define TWI_SLAVE_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ -#define TWI_SLAVE_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ - -#define TWI_SLAVE_DIEN_bm 0x20 /* Data Interrupt Enable bit mask. */ -#define TWI_SLAVE_DIEN_bp 5 /* Data Interrupt Enable bit position. */ - -#define TWI_SLAVE_APIEN_bm 0x10 /* Address/Stop Interrupt Enable bit mask. */ -#define TWI_SLAVE_APIEN_bp 4 /* Address/Stop Interrupt Enable bit position. */ - -#define TWI_SLAVE_ENABLE_bm 0x08 /* Enable TWI Slave bit mask. */ -#define TWI_SLAVE_ENABLE_bp 3 /* Enable TWI Slave bit position. */ - -#define TWI_SLAVE_PIEN_bm 0x04 /* Stop Interrupt Enable bit mask. */ -#define TWI_SLAVE_PIEN_bp 2 /* Stop Interrupt Enable bit position. */ - -#define TWI_SLAVE_PMEN_bm 0x02 /* Promiscuous Mode Enable bit mask. */ -#define TWI_SLAVE_PMEN_bp 1 /* Promiscuous Mode Enable bit position. */ - -#define TWI_SLAVE_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ -#define TWI_SLAVE_SMEN_bp 0 /* Smart Mode Enable bit position. */ - -/* TWI_SLAVE.CTRLB bit masks and bit positions */ -#define TWI_SLAVE_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ -#define TWI_SLAVE_ACKACT_bp 2 /* Acknowledge Action bit position. */ - -#define TWI_SLAVE_CMD_gm 0x03 /* Command group mask. */ -#define TWI_SLAVE_CMD_gp 0 /* Command group position. */ -#define TWI_SLAVE_CMD0_bm (1<<0) /* Command bit 0 mask. */ -#define TWI_SLAVE_CMD0_bp 0 /* Command bit 0 position. */ -#define TWI_SLAVE_CMD1_bm (1<<1) /* Command bit 1 mask. */ -#define TWI_SLAVE_CMD1_bp 1 /* Command bit 1 position. */ - -/* TWI_SLAVE.STATUS bit masks and bit positions */ -#define TWI_SLAVE_DIF_bm 0x80 /* Data Interrupt Flag bit mask. */ -#define TWI_SLAVE_DIF_bp 7 /* Data Interrupt Flag bit position. */ - -#define TWI_SLAVE_APIF_bm 0x40 /* Address/Stop Interrupt Flag bit mask. */ -#define TWI_SLAVE_APIF_bp 6 /* Address/Stop Interrupt Flag bit position. */ - -#define TWI_SLAVE_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ -#define TWI_SLAVE_CLKHOLD_bp 5 /* Clock Hold bit position. */ - -#define TWI_SLAVE_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ -#define TWI_SLAVE_RXACK_bp 4 /* Received Acknowledge bit position. */ - -#define TWI_SLAVE_COLL_bm 0x08 /* Collision bit mask. */ -#define TWI_SLAVE_COLL_bp 3 /* Collision bit position. */ - -#define TWI_SLAVE_BUSERR_bm 0x04 /* Bus Error bit mask. */ -#define TWI_SLAVE_BUSERR_bp 2 /* Bus Error bit position. */ - -#define TWI_SLAVE_DIR_bm 0x02 /* Read/Write Direction bit mask. */ -#define TWI_SLAVE_DIR_bp 1 /* Read/Write Direction bit position. */ - -#define TWI_SLAVE_AP_bm 0x01 /* Slave Address or Stop bit mask. */ -#define TWI_SLAVE_AP_bp 0 /* Slave Address or Stop bit position. */ - -/* TWI_SLAVE.ADDRMASK bit masks and bit positions */ -#define TWI_SLAVE_ADDRMASK_gm 0xFE /* Address Mask group mask. */ -#define TWI_SLAVE_ADDRMASK_gp 1 /* Address Mask group position. */ -#define TWI_SLAVE_ADDRMASK0_bm (1<<1) /* Address Mask bit 0 mask. */ -#define TWI_SLAVE_ADDRMASK0_bp 1 /* Address Mask bit 0 position. */ -#define TWI_SLAVE_ADDRMASK1_bm (1<<2) /* Address Mask bit 1 mask. */ -#define TWI_SLAVE_ADDRMASK1_bp 2 /* Address Mask bit 1 position. */ -#define TWI_SLAVE_ADDRMASK2_bm (1<<3) /* Address Mask bit 2 mask. */ -#define TWI_SLAVE_ADDRMASK2_bp 3 /* Address Mask bit 2 position. */ -#define TWI_SLAVE_ADDRMASK3_bm (1<<4) /* Address Mask bit 3 mask. */ -#define TWI_SLAVE_ADDRMASK3_bp 4 /* Address Mask bit 3 position. */ -#define TWI_SLAVE_ADDRMASK4_bm (1<<5) /* Address Mask bit 4 mask. */ -#define TWI_SLAVE_ADDRMASK4_bp 5 /* Address Mask bit 4 position. */ -#define TWI_SLAVE_ADDRMASK5_bm (1<<6) /* Address Mask bit 5 mask. */ -#define TWI_SLAVE_ADDRMASK5_bp 6 /* Address Mask bit 5 position. */ -#define TWI_SLAVE_ADDRMASK6_bm (1<<7) /* Address Mask bit 6 mask. */ -#define TWI_SLAVE_ADDRMASK6_bp 7 /* Address Mask bit 6 position. */ - -#define TWI_SLAVE_ADDREN_bm 0x01 /* Address Enable bit mask. */ -#define TWI_SLAVE_ADDREN_bp 0 /* Address Enable bit position. */ - -/* TWI.CTRL bit masks and bit positions */ -#define TWI_SDAHOLD_gm 0x06 /* SDA Hold Time Enable group mask. */ -#define TWI_SDAHOLD_gp 1 /* SDA Hold Time Enable group position. */ -#define TWI_SDAHOLD0_bm (1<<1) /* SDA Hold Time Enable bit 0 mask. */ -#define TWI_SDAHOLD0_bp 1 /* SDA Hold Time Enable bit 0 position. */ -#define TWI_SDAHOLD1_bm (1<<2) /* SDA Hold Time Enable bit 1 mask. */ -#define TWI_SDAHOLD1_bp 2 /* SDA Hold Time Enable bit 1 position. */ - -#define TWI_EDIEN_bm 0x01 /* External Driver Interface Enable bit mask. */ -#define TWI_EDIEN_bp 0 /* External Driver Interface Enable bit position. */ - -/* USB - USB */ -/* USB_EP.STATUS bit masks and bit positions */ -#define USB_EP_STALLF_bm 0x80 /* Endpoint Stall Flag bit mask. */ -#define USB_EP_STALLF_bp 7 /* Endpoint Stall Flag bit position. */ - -#define USB_EP_CRC_bm 0x80 /* CRC Error Flag bit mask. */ -#define USB_EP_CRC_bp 7 /* CRC Error Flag bit position. */ - -#define USB_EP_UNF_bm 0x40 /* Underflow Enpoint FLag bit mask. */ -#define USB_EP_UNF_bp 6 /* Underflow Enpoint FLag bit position. */ - -#define USB_EP_OVF_bm 0x40 /* Overflow Enpoint Flag for Output Endpoints bit mask. */ -#define USB_EP_OVF_bp 6 /* Overflow Enpoint Flag for Output Endpoints bit position. */ - -#define USB_EP_TRNCOMPL0_bm 0x20 /* Transaction Complete 0 Flag bit mask. */ -#define USB_EP_TRNCOMPL0_bp 5 /* Transaction Complete 0 Flag bit position. */ - -#define USB_EP_TRNCOMPL1_bm 0x10 /* Transaction Complete 1 Flag bit mask. */ -#define USB_EP_TRNCOMPL1_bp 4 /* Transaction Complete 1 Flag bit position. */ - -#define USB_EP_SETUP_bm 0x10 /* SETUP Transaction Complete Flag bit mask. */ -#define USB_EP_SETUP_bp 4 /* SETUP Transaction Complete Flag bit position. */ - -#define USB_EP_BANK_bm 0x08 /* Bank Select bit mask. */ -#define USB_EP_BANK_bp 3 /* Bank Select bit position. */ - -#define USB_EP_BUSNACK1_bm 0x04 /* Data Buffer 1 Not Acknowledge bit mask. */ -#define USB_EP_BUSNACK1_bp 2 /* Data Buffer 1 Not Acknowledge bit position. */ - -#define USB_EP_BUSNACK0_bm 0x02 /* Data Buffer 0 Not Acknowledge bit mask. */ -#define USB_EP_BUSNACK0_bp 1 /* Data Buffer 0 Not Acknowledge bit position. */ - -#define USB_EP_TOGGLE_bm 0x01 /* Data Toggle bit mask. */ -#define USB_EP_TOGGLE_bp 0 /* Data Toggle bit position. */ - -/* USB_EP.CTRL bit masks and bit positions */ -#define USB_EP_TYPE_gm 0xC0 /* Endpoint Type group mask. */ -#define USB_EP_TYPE_gp 6 /* Endpoint Type group position. */ -#define USB_EP_TYPE0_bm (1<<6) /* Endpoint Type bit 0 mask. */ -#define USB_EP_TYPE0_bp 6 /* Endpoint Type bit 0 position. */ -#define USB_EP_TYPE1_bm (1<<7) /* Endpoint Type bit 1 mask. */ -#define USB_EP_TYPE1_bp 7 /* Endpoint Type bit 1 position. */ - -#define USB_EP_MULTIPKT_bm 0x20 /* Multi Packet Transfer Enable bit mask. */ -#define USB_EP_MULTIPKT_bp 5 /* Multi Packet Transfer Enable bit position. */ - -#define USB_EP_PINGPONG_bm 0x10 /* Ping-Pong Enable bit mask. */ -#define USB_EP_PINGPONG_bp 4 /* Ping-Pong Enable bit position. */ - -#define USB_EP_INTDSBL_bm 0x08 /* Interrupt Disable bit mask. */ -#define USB_EP_INTDSBL_bp 3 /* Interrupt Disable bit position. */ - -#define USB_EP_STALL_bm 0x04 /* Data Stall bit mask. */ -#define USB_EP_STALL_bp 2 /* Data Stall bit position. */ - -#define USB_EP_BUFSIZE_gm 0x07 /* Data Buffer Size group mask. */ -#define USB_EP_BUFSIZE_gp 0 /* Data Buffer Size group position. */ -#define USB_EP_BUFSIZE0_bm (1<<0) /* Data Buffer Size bit 0 mask. */ -#define USB_EP_BUFSIZE0_bp 0 /* Data Buffer Size bit 0 position. */ -#define USB_EP_BUFSIZE1_bm (1<<1) /* Data Buffer Size bit 1 mask. */ -#define USB_EP_BUFSIZE1_bp 1 /* Data Buffer Size bit 1 position. */ -#define USB_EP_BUFSIZE2_bm (1<<2) /* Data Buffer Size bit 2 mask. */ -#define USB_EP_BUFSIZE2_bp 2 /* Data Buffer Size bit 2 position. */ - -/* USB_EP.CNT bit masks and bit positions */ -#define USB_EP_ZLP_bm 0x8000 /* Zero Length Packet bit mask. */ -#define USB_EP_ZLP_bp 15 /* Zero Length Packet bit position. */ - -/* USB.CTRLA bit masks and bit positions */ -#define USB_ENABLE_bm 0x80 /* USB Enable bit mask. */ -#define USB_ENABLE_bp 7 /* USB Enable bit position. */ - -#define USB_SPEED_bm 0x40 /* Speed Select bit mask. */ -#define USB_SPEED_bp 6 /* Speed Select bit position. */ - -#define USB_FIFOEN_bm 0x20 /* USB FIFO Enable bit mask. */ -#define USB_FIFOEN_bp 5 /* USB FIFO Enable bit position. */ - -#define USB_STFRNUM_bm 0x10 /* Store Frame Number Enable bit mask. */ -#define USB_STFRNUM_bp 4 /* Store Frame Number Enable bit position. */ - -#define USB_MAXEP_gm 0x0F /* Maximum Endpoint Addresses group mask. */ -#define USB_MAXEP_gp 0 /* Maximum Endpoint Addresses group position. */ -#define USB_MAXEP0_bm (1<<0) /* Maximum Endpoint Addresses bit 0 mask. */ -#define USB_MAXEP0_bp 0 /* Maximum Endpoint Addresses bit 0 position. */ -#define USB_MAXEP1_bm (1<<1) /* Maximum Endpoint Addresses bit 1 mask. */ -#define USB_MAXEP1_bp 1 /* Maximum Endpoint Addresses bit 1 position. */ -#define USB_MAXEP2_bm (1<<2) /* Maximum Endpoint Addresses bit 2 mask. */ -#define USB_MAXEP2_bp 2 /* Maximum Endpoint Addresses bit 2 position. */ -#define USB_MAXEP3_bm (1<<3) /* Maximum Endpoint Addresses bit 3 mask. */ -#define USB_MAXEP3_bp 3 /* Maximum Endpoint Addresses bit 3 position. */ - -/* USB.CTRLB bit masks and bit positions */ -#define USB_PULLRST_bm 0x10 /* Pull during Reset bit mask. */ -#define USB_PULLRST_bp 4 /* Pull during Reset bit position. */ - -#define USB_RWAKEUP_bm 0x04 /* Remote Wake-up bit mask. */ -#define USB_RWAKEUP_bp 2 /* Remote Wake-up bit position. */ - -#define USB_GNACK_bm 0x02 /* Global NACK bit mask. */ -#define USB_GNACK_bp 1 /* Global NACK bit position. */ - -#define USB_ATTACH_bm 0x01 /* Attach bit mask. */ -#define USB_ATTACH_bp 0 /* Attach bit position. */ - -/* USB.STATUS bit masks and bit positions */ -#define USB_URESUME_bm 0x08 /* Upstream Resume bit mask. */ -#define USB_URESUME_bp 3 /* Upstream Resume bit position. */ - -#define USB_RESUME_bm 0x04 /* Resume bit mask. */ -#define USB_RESUME_bp 2 /* Resume bit position. */ - -#define USB_SUSPEND_bm 0x02 /* Bus Suspended bit mask. */ -#define USB_SUSPEND_bp 1 /* Bus Suspended bit position. */ - -#define USB_BUSRST_bm 0x01 /* Bus Reset bit mask. */ -#define USB_BUSRST_bp 0 /* Bus Reset bit position. */ - -/* USB.ADDR bit masks and bit positions */ -#define USB_ADDR_gm 0x7F /* Device Address group mask. */ -#define USB_ADDR_gp 0 /* Device Address group position. */ -#define USB_ADDR0_bm (1<<0) /* Device Address bit 0 mask. */ -#define USB_ADDR0_bp 0 /* Device Address bit 0 position. */ -#define USB_ADDR1_bm (1<<1) /* Device Address bit 1 mask. */ -#define USB_ADDR1_bp 1 /* Device Address bit 1 position. */ -#define USB_ADDR2_bm (1<<2) /* Device Address bit 2 mask. */ -#define USB_ADDR2_bp 2 /* Device Address bit 2 position. */ -#define USB_ADDR3_bm (1<<3) /* Device Address bit 3 mask. */ -#define USB_ADDR3_bp 3 /* Device Address bit 3 position. */ -#define USB_ADDR4_bm (1<<4) /* Device Address bit 4 mask. */ -#define USB_ADDR4_bp 4 /* Device Address bit 4 position. */ -#define USB_ADDR5_bm (1<<5) /* Device Address bit 5 mask. */ -#define USB_ADDR5_bp 5 /* Device Address bit 5 position. */ -#define USB_ADDR6_bm (1<<6) /* Device Address bit 6 mask. */ -#define USB_ADDR6_bp 6 /* Device Address bit 6 position. */ - -/* USB.FIFOWP bit masks and bit positions */ -#define USB_FIFOWP_gm 0x1F /* FIFO Write Pointer group mask. */ -#define USB_FIFOWP_gp 0 /* FIFO Write Pointer group position. */ -#define USB_FIFOWP0_bm (1<<0) /* FIFO Write Pointer bit 0 mask. */ -#define USB_FIFOWP0_bp 0 /* FIFO Write Pointer bit 0 position. */ -#define USB_FIFOWP1_bm (1<<1) /* FIFO Write Pointer bit 1 mask. */ -#define USB_FIFOWP1_bp 1 /* FIFO Write Pointer bit 1 position. */ -#define USB_FIFOWP2_bm (1<<2) /* FIFO Write Pointer bit 2 mask. */ -#define USB_FIFOWP2_bp 2 /* FIFO Write Pointer bit 2 position. */ -#define USB_FIFOWP3_bm (1<<3) /* FIFO Write Pointer bit 3 mask. */ -#define USB_FIFOWP3_bp 3 /* FIFO Write Pointer bit 3 position. */ -#define USB_FIFOWP4_bm (1<<4) /* FIFO Write Pointer bit 4 mask. */ -#define USB_FIFOWP4_bp 4 /* FIFO Write Pointer bit 4 position. */ - -/* USB.FIFORP bit masks and bit positions */ -#define USB_FIFORP_gm 0x1F /* FIFO Read Pointer group mask. */ -#define USB_FIFORP_gp 0 /* FIFO Read Pointer group position. */ -#define USB_FIFORP0_bm (1<<0) /* FIFO Read Pointer bit 0 mask. */ -#define USB_FIFORP0_bp 0 /* FIFO Read Pointer bit 0 position. */ -#define USB_FIFORP1_bm (1<<1) /* FIFO Read Pointer bit 1 mask. */ -#define USB_FIFORP1_bp 1 /* FIFO Read Pointer bit 1 position. */ -#define USB_FIFORP2_bm (1<<2) /* FIFO Read Pointer bit 2 mask. */ -#define USB_FIFORP2_bp 2 /* FIFO Read Pointer bit 2 position. */ -#define USB_FIFORP3_bm (1<<3) /* FIFO Read Pointer bit 3 mask. */ -#define USB_FIFORP3_bp 3 /* FIFO Read Pointer bit 3 position. */ -#define USB_FIFORP4_bm (1<<4) /* FIFO Read Pointer bit 4 mask. */ -#define USB_FIFORP4_bp 4 /* FIFO Read Pointer bit 4 position. */ - -/* USB.INTCTRLA bit masks and bit positions */ -#define USB_SOFIE_bm 0x80 /* Start Of Frame Interrupt Enable bit mask. */ -#define USB_SOFIE_bp 7 /* Start Of Frame Interrupt Enable bit position. */ - -#define USB_BUSEVIE_bm 0x40 /* Bus Event Interrupt Enable bit mask. */ -#define USB_BUSEVIE_bp 6 /* Bus Event Interrupt Enable bit position. */ - -#define USB_BUSERRIE_bm 0x20 /* Bus Error Interrupt Enable bit mask. */ -#define USB_BUSERRIE_bp 5 /* Bus Error Interrupt Enable bit position. */ - -#define USB_STALLIE_bm 0x10 /* STALL Interrupt Enable bit mask. */ -#define USB_STALLIE_bp 4 /* STALL Interrupt Enable bit position. */ - -#define USB_INTLVL_gm 0x03 /* Interrupt Level group mask. */ -#define USB_INTLVL_gp 0 /* Interrupt Level group position. */ -#define USB_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */ -#define USB_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */ -#define USB_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ -#define USB_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */ - -/* USB.INTCTRLB bit masks and bit positions */ -#define USB_TRNIE_bm 0x02 /* Transaction Complete Interrupt Enable bit mask. */ -#define USB_TRNIE_bp 1 /* Transaction Complete Interrupt Enable bit position. */ - -#define USB_SETUPIE_bm 0x01 /* SETUP Transaction Complete Interrupt Enable bit mask. */ -#define USB_SETUPIE_bp 0 /* SETUP Transaction Complete Interrupt Enable bit position. */ - -/* USB.INTFLAGSACLR bit masks and bit positions */ -#define USB_SOFIF_bm 0x80 /* Start Of Frame Interrupt Flag bit mask. */ -#define USB_SOFIF_bp 7 /* Start Of Frame Interrupt Flag bit position. */ - -#define USB_SUSPENDIF_bm 0x40 /* Suspend Interrupt Flag bit mask. */ -#define USB_SUSPENDIF_bp 6 /* Suspend Interrupt Flag bit position. */ - -#define USB_RESUMEIF_bm 0x20 /* Resume Interrupt Flag bit mask. */ -#define USB_RESUMEIF_bp 5 /* Resume Interrupt Flag bit position. */ - -#define USB_RSTIF_bm 0x10 /* Reset Interrupt Flag bit mask. */ -#define USB_RSTIF_bp 4 /* Reset Interrupt Flag bit position. */ - -#define USB_CRCIF_bm 0x08 /* Isochronous CRC Error Interrupt Flag bit mask. */ -#define USB_CRCIF_bp 3 /* Isochronous CRC Error Interrupt Flag bit position. */ - -#define USB_UNFIF_bm 0x04 /* Underflow Interrupt Flag bit mask. */ -#define USB_UNFIF_bp 2 /* Underflow Interrupt Flag bit position. */ - -#define USB_OVFIF_bm 0x02 /* Overflow Interrupt Flag bit mask. */ -#define USB_OVFIF_bp 1 /* Overflow Interrupt Flag bit position. */ - -#define USB_STALLIF_bm 0x01 /* STALL Interrupt Flag bit mask. */ -#define USB_STALLIF_bp 0 /* STALL Interrupt Flag bit position. */ - -/* USB.INTFLAGSASET bit masks and bit positions */ -/* USB_SOFIF Predefined. */ -/* USB_SOFIF Predefined. */ - -/* USB_SUSPENDIF Predefined. */ -/* USB_SUSPENDIF Predefined. */ - -/* USB_RESUMEIF Predefined. */ -/* USB_RESUMEIF Predefined. */ - -/* USB_RSTIF Predefined. */ -/* USB_RSTIF Predefined. */ - -/* USB_CRCIF Predefined. */ -/* USB_CRCIF Predefined. */ - -/* USB_UNFIF Predefined. */ -/* USB_UNFIF Predefined. */ - -/* USB_OVFIF Predefined. */ -/* USB_OVFIF Predefined. */ - -/* USB_STALLIF Predefined. */ -/* USB_STALLIF Predefined. */ - -/* USB.INTFLAGSBCLR bit masks and bit positions */ -#define USB_TRNIF_bm 0x02 /* Transaction Complete Interrupt Flag bit mask. */ -#define USB_TRNIF_bp 1 /* Transaction Complete Interrupt Flag bit position. */ - -#define USB_SETUPIF_bm 0x01 /* SETUP Transaction Complete Interrupt Flag bit mask. */ -#define USB_SETUPIF_bp 0 /* SETUP Transaction Complete Interrupt Flag bit position. */ - -/* USB.INTFLAGSBSET bit masks and bit positions */ -/* USB_TRNIF Predefined. */ -/* USB_TRNIF Predefined. */ - -/* USB_SETUPIF Predefined. */ -/* USB_SETUPIF Predefined. */ - -/* PORT - I/O Port Configuration */ -/* PORT.INTCTRL bit masks and bit positions */ -#define PORT_INT1LVL_gm 0x0C /* Port Interrupt 1 Level group mask. */ -#define PORT_INT1LVL_gp 2 /* Port Interrupt 1 Level group position. */ -#define PORT_INT1LVL0_bm (1<<2) /* Port Interrupt 1 Level bit 0 mask. */ -#define PORT_INT1LVL0_bp 2 /* Port Interrupt 1 Level bit 0 position. */ -#define PORT_INT1LVL1_bm (1<<3) /* Port Interrupt 1 Level bit 1 mask. */ -#define PORT_INT1LVL1_bp 3 /* Port Interrupt 1 Level bit 1 position. */ - -#define PORT_INT0LVL_gm 0x03 /* Port Interrupt 0 Level group mask. */ -#define PORT_INT0LVL_gp 0 /* Port Interrupt 0 Level group position. */ -#define PORT_INT0LVL0_bm (1<<0) /* Port Interrupt 0 Level bit 0 mask. */ -#define PORT_INT0LVL0_bp 0 /* Port Interrupt 0 Level bit 0 position. */ -#define PORT_INT0LVL1_bm (1<<1) /* Port Interrupt 0 Level bit 1 mask. */ -#define PORT_INT0LVL1_bp 1 /* Port Interrupt 0 Level bit 1 position. */ - -/* PORT.INTFLAGS bit masks and bit positions */ -#define PORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ -#define PORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ - -#define PORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ -#define PORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ - -/* PORT.REMAP bit masks and bit positions */ -#define PORT_SPI_bm 0x20 /* SPI bit mask. */ -#define PORT_SPI_bp 5 /* SPI bit position. */ - -#define PORT_USART0_bm 0x10 /* USART0 bit mask. */ -#define PORT_USART0_bp 4 /* USART0 bit position. */ - -#define PORT_TC0D_bm 0x08 /* Timer/Counter 0 Output Compare D bit mask. */ -#define PORT_TC0D_bp 3 /* Timer/Counter 0 Output Compare D bit position. */ - -#define PORT_TC0C_bm 0x04 /* Timer/Counter 0 Output Compare C bit mask. */ -#define PORT_TC0C_bp 2 /* Timer/Counter 0 Output Compare C bit position. */ - -#define PORT_TC0B_bm 0x02 /* Timer/Counter 0 Output Compare B bit mask. */ -#define PORT_TC0B_bp 1 /* Timer/Counter 0 Output Compare B bit position. */ - -#define PORT_TC0A_bm 0x01 /* Timer/Counter 0 Output Compare A bit mask. */ -#define PORT_TC0A_bp 0 /* Timer/Counter 0 Output Compare A bit position. */ - -/* PORT.PIN0CTRL bit masks and bit positions */ -#define PORT_SRLEN_bm 0x80 /* Slew Rate Enable bit mask. */ -#define PORT_SRLEN_bp 7 /* Slew Rate Enable bit position. */ - -#define PORT_INVEN_bm 0x40 /* Inverted I/O Enable bit mask. */ -#define PORT_INVEN_bp 6 /* Inverted I/O Enable bit position. */ - -#define PORT_OPC_gm 0x38 /* Output/Pull Configuration group mask. */ -#define PORT_OPC_gp 3 /* Output/Pull Configuration group position. */ -#define PORT_OPC0_bm (1<<3) /* Output/Pull Configuration bit 0 mask. */ -#define PORT_OPC0_bp 3 /* Output/Pull Configuration bit 0 position. */ -#define PORT_OPC1_bm (1<<4) /* Output/Pull Configuration bit 1 mask. */ -#define PORT_OPC1_bp 4 /* Output/Pull Configuration bit 1 position. */ -#define PORT_OPC2_bm (1<<5) /* Output/Pull Configuration bit 2 mask. */ -#define PORT_OPC2_bp 5 /* Output/Pull Configuration bit 2 position. */ - -#define PORT_ISC_gm 0x07 /* Input/Sense Configuration group mask. */ -#define PORT_ISC_gp 0 /* Input/Sense Configuration group position. */ -#define PORT_ISC0_bm (1<<0) /* Input/Sense Configuration bit 0 mask. */ -#define PORT_ISC0_bp 0 /* Input/Sense Configuration bit 0 position. */ -#define PORT_ISC1_bm (1<<1) /* Input/Sense Configuration bit 1 mask. */ -#define PORT_ISC1_bp 1 /* Input/Sense Configuration bit 1 position. */ -#define PORT_ISC2_bm (1<<2) /* Input/Sense Configuration bit 2 mask. */ -#define PORT_ISC2_bp 2 /* Input/Sense Configuration bit 2 position. */ - -/* PORT.PIN1CTRL bit masks and bit positions */ -/* PORT_SRLEN Predefined. */ -/* PORT_SRLEN Predefined. */ - -/* PORT_INVEN Predefined. */ -/* PORT_INVEN Predefined. */ - -/* PORT_OPC Predefined. */ -/* PORT_OPC Predefined. */ - -/* PORT_ISC Predefined. */ -/* PORT_ISC Predefined. */ - -/* PORT.PIN2CTRL bit masks and bit positions */ -/* PORT_SRLEN Predefined. */ -/* PORT_SRLEN Predefined. */ - -/* PORT_INVEN Predefined. */ -/* PORT_INVEN Predefined. */ - -/* PORT_OPC Predefined. */ -/* PORT_OPC Predefined. */ - -/* PORT_ISC Predefined. */ -/* PORT_ISC Predefined. */ - -/* PORT.PIN3CTRL bit masks and bit positions */ -/* PORT_SRLEN Predefined. */ -/* PORT_SRLEN Predefined. */ - -/* PORT_INVEN Predefined. */ -/* PORT_INVEN Predefined. */ - -/* PORT_OPC Predefined. */ -/* PORT_OPC Predefined. */ - -/* PORT_ISC Predefined. */ -/* PORT_ISC Predefined. */ - -/* PORT.PIN4CTRL bit masks and bit positions */ -/* PORT_SRLEN Predefined. */ -/* PORT_SRLEN Predefined. */ - -/* PORT_INVEN Predefined. */ -/* PORT_INVEN Predefined. */ - -/* PORT_OPC Predefined. */ -/* PORT_OPC Predefined. */ - -/* PORT_ISC Predefined. */ -/* PORT_ISC Predefined. */ - -/* PORT.PIN5CTRL bit masks and bit positions */ -/* PORT_SRLEN Predefined. */ -/* PORT_SRLEN Predefined. */ - -/* PORT_INVEN Predefined. */ -/* PORT_INVEN Predefined. */ - -/* PORT_OPC Predefined. */ -/* PORT_OPC Predefined. */ - -/* PORT_ISC Predefined. */ -/* PORT_ISC Predefined. */ - -/* PORT.PIN6CTRL bit masks and bit positions */ -/* PORT_SRLEN Predefined. */ -/* PORT_SRLEN Predefined. */ - -/* PORT_INVEN Predefined. */ -/* PORT_INVEN Predefined. */ - -/* PORT_OPC Predefined. */ -/* PORT_OPC Predefined. */ - -/* PORT_ISC Predefined. */ -/* PORT_ISC Predefined. */ - -/* PORT.PIN7CTRL bit masks and bit positions */ -/* PORT_SRLEN Predefined. */ -/* PORT_SRLEN Predefined. */ - -/* PORT_INVEN Predefined. */ -/* PORT_INVEN Predefined. */ - -/* PORT_OPC Predefined. */ -/* PORT_OPC Predefined. */ - -/* PORT_ISC Predefined. */ -/* PORT_ISC Predefined. */ - -/* TC - 16-bit Timer/Counter With PWM */ -/* TC0.CTRLA bit masks and bit positions */ -#define TC0_CLKSEL_gm 0x0F /* Clock Selection group mask. */ -#define TC0_CLKSEL_gp 0 /* Clock Selection group position. */ -#define TC0_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ -#define TC0_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ -#define TC0_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ -#define TC0_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ -#define TC0_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ -#define TC0_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ -#define TC0_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ -#define TC0_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ - -/* TC0.CTRLB bit masks and bit positions */ -#define TC0_CCDEN_bm 0x80 /* Compare or Capture D Enable bit mask. */ -#define TC0_CCDEN_bp 7 /* Compare or Capture D Enable bit position. */ - -#define TC0_CCCEN_bm 0x40 /* Compare or Capture C Enable bit mask. */ -#define TC0_CCCEN_bp 6 /* Compare or Capture C Enable bit position. */ - -#define TC0_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ -#define TC0_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ - -#define TC0_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ -#define TC0_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ - -#define TC0_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ -#define TC0_WGMODE_gp 0 /* Waveform generation mode group position. */ -#define TC0_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ -#define TC0_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ -#define TC0_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ -#define TC0_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ -#define TC0_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ -#define TC0_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ - -/* TC0.CTRLC bit masks and bit positions */ -#define TC0_CMPD_bm 0x08 /* Compare D Output Value bit mask. */ -#define TC0_CMPD_bp 3 /* Compare D Output Value bit position. */ - -#define TC0_CMPC_bm 0x04 /* Compare C Output Value bit mask. */ -#define TC0_CMPC_bp 2 /* Compare C Output Value bit position. */ - -#define TC0_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ -#define TC0_CMPB_bp 1 /* Compare B Output Value bit position. */ - -#define TC0_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ -#define TC0_CMPA_bp 0 /* Compare A Output Value bit position. */ - -/* TC0.CTRLD bit masks and bit positions */ -#define TC0_EVACT_gm 0xE0 /* Event Action group mask. */ -#define TC0_EVACT_gp 5 /* Event Action group position. */ -#define TC0_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ -#define TC0_EVACT0_bp 5 /* Event Action bit 0 position. */ -#define TC0_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ -#define TC0_EVACT1_bp 6 /* Event Action bit 1 position. */ -#define TC0_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ -#define TC0_EVACT2_bp 7 /* Event Action bit 2 position. */ - -#define TC0_EVDLY_bm 0x10 /* Event Delay bit mask. */ -#define TC0_EVDLY_bp 4 /* Event Delay bit position. */ - -#define TC0_EVSEL_gm 0x0F /* Event Source Select group mask. */ -#define TC0_EVSEL_gp 0 /* Event Source Select group position. */ -#define TC0_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ -#define TC0_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ -#define TC0_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ -#define TC0_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ -#define TC0_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ -#define TC0_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ -#define TC0_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ -#define TC0_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ - -/* TC0.CTRLE bit masks and bit positions */ -#define TC0_BYTEM_gm 0x03 /* Byte Mode group mask. */ -#define TC0_BYTEM_gp 0 /* Byte Mode group position. */ -#define TC0_BYTEM0_bm (1<<0) /* Byte Mode bit 0 mask. */ -#define TC0_BYTEM0_bp 0 /* Byte Mode bit 0 position. */ -#define TC0_BYTEM1_bm (1<<1) /* Byte Mode bit 1 mask. */ -#define TC0_BYTEM1_bp 1 /* Byte Mode bit 1 position. */ - -/* TC0.INTCTRLA bit masks and bit positions */ -#define TC0_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ -#define TC0_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ -#define TC0_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ -#define TC0_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ -#define TC0_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ -#define TC0_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ - -#define TC0_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ -#define TC0_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ -#define TC0_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ -#define TC0_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ -#define TC0_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ -#define TC0_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ - -/* TC0.INTCTRLB bit masks and bit positions */ -#define TC0_CCDINTLVL_gm 0xC0 /* Compare or Capture D Interrupt Level group mask. */ -#define TC0_CCDINTLVL_gp 6 /* Compare or Capture D Interrupt Level group position. */ -#define TC0_CCDINTLVL0_bm (1<<6) /* Compare or Capture D Interrupt Level bit 0 mask. */ -#define TC0_CCDINTLVL0_bp 6 /* Compare or Capture D Interrupt Level bit 0 position. */ -#define TC0_CCDINTLVL1_bm (1<<7) /* Compare or Capture D Interrupt Level bit 1 mask. */ -#define TC0_CCDINTLVL1_bp 7 /* Compare or Capture D Interrupt Level bit 1 position. */ - -#define TC0_CCCINTLVL_gm 0x30 /* Compare or Capture C Interrupt Level group mask. */ -#define TC0_CCCINTLVL_gp 4 /* Compare or Capture C Interrupt Level group position. */ -#define TC0_CCCINTLVL0_bm (1<<4) /* Compare or Capture C Interrupt Level bit 0 mask. */ -#define TC0_CCCINTLVL0_bp 4 /* Compare or Capture C Interrupt Level bit 0 position. */ -#define TC0_CCCINTLVL1_bm (1<<5) /* Compare or Capture C Interrupt Level bit 1 mask. */ -#define TC0_CCCINTLVL1_bp 5 /* Compare or Capture C Interrupt Level bit 1 position. */ - -#define TC0_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ -#define TC0_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ -#define TC0_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ -#define TC0_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ -#define TC0_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ -#define TC0_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ - -#define TC0_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ -#define TC0_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ -#define TC0_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ -#define TC0_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ -#define TC0_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ -#define TC0_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ - -/* TC0.CTRLFCLR bit masks and bit positions */ -#define TC0_CMD_gm 0x0C /* Command group mask. */ -#define TC0_CMD_gp 2 /* Command group position. */ -#define TC0_CMD0_bm (1<<2) /* Command bit 0 mask. */ -#define TC0_CMD0_bp 2 /* Command bit 0 position. */ -#define TC0_CMD1_bm (1<<3) /* Command bit 1 mask. */ -#define TC0_CMD1_bp 3 /* Command bit 1 position. */ - -#define TC0_LUPD_bm 0x02 /* Lock Update bit mask. */ -#define TC0_LUPD_bp 1 /* Lock Update bit position. */ - -#define TC0_DIR_bm 0x01 /* Direction bit mask. */ -#define TC0_DIR_bp 0 /* Direction bit position. */ - -/* TC0.CTRLFSET bit masks and bit positions */ -/* TC0_CMD Predefined. */ -/* TC0_CMD Predefined. */ - -/* TC0_LUPD Predefined. */ -/* TC0_LUPD Predefined. */ - -/* TC0_DIR Predefined. */ -/* TC0_DIR Predefined. */ - -/* TC0.CTRLGCLR bit masks and bit positions */ -#define TC0_CCDBV_bm 0x10 /* Compare or Capture D Buffer Valid bit mask. */ -#define TC0_CCDBV_bp 4 /* Compare or Capture D Buffer Valid bit position. */ - -#define TC0_CCCBV_bm 0x08 /* Compare or Capture C Buffer Valid bit mask. */ -#define TC0_CCCBV_bp 3 /* Compare or Capture C Buffer Valid bit position. */ - -#define TC0_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ -#define TC0_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ - -#define TC0_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ -#define TC0_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ - -#define TC0_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ -#define TC0_PERBV_bp 0 /* Period Buffer Valid bit position. */ - -/* TC0.CTRLGSET bit masks and bit positions */ -/* TC0_CCDBV Predefined. */ -/* TC0_CCDBV Predefined. */ - -/* TC0_CCCBV Predefined. */ -/* TC0_CCCBV Predefined. */ - -/* TC0_CCBBV Predefined. */ -/* TC0_CCBBV Predefined. */ - -/* TC0_CCABV Predefined. */ -/* TC0_CCABV Predefined. */ - -/* TC0_PERBV Predefined. */ -/* TC0_PERBV Predefined. */ - -/* TC0.INTFLAGS bit masks and bit positions */ -#define TC0_CCDIF_bm 0x80 /* Compare or Capture D Interrupt Flag bit mask. */ -#define TC0_CCDIF_bp 7 /* Compare or Capture D Interrupt Flag bit position. */ - -#define TC0_CCCIF_bm 0x40 /* Compare or Capture C Interrupt Flag bit mask. */ -#define TC0_CCCIF_bp 6 /* Compare or Capture C Interrupt Flag bit position. */ - -#define TC0_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ -#define TC0_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ - -#define TC0_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ -#define TC0_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ - -#define TC0_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ -#define TC0_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ - -#define TC0_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ -#define TC0_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ - -/* TC1.CTRLA bit masks and bit positions */ -#define TC1_CLKSEL_gm 0x0F /* Clock Selection group mask. */ -#define TC1_CLKSEL_gp 0 /* Clock Selection group position. */ -#define TC1_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ -#define TC1_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ -#define TC1_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ -#define TC1_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ -#define TC1_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ -#define TC1_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ -#define TC1_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ -#define TC1_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ - -/* TC1.CTRLB bit masks and bit positions */ -#define TC1_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ -#define TC1_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ - -#define TC1_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ -#define TC1_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ - -#define TC1_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ -#define TC1_WGMODE_gp 0 /* Waveform generation mode group position. */ -#define TC1_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ -#define TC1_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ -#define TC1_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ -#define TC1_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ -#define TC1_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ -#define TC1_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ - -/* TC1.CTRLC bit masks and bit positions */ -#define TC1_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ -#define TC1_CMPB_bp 1 /* Compare B Output Value bit position. */ - -#define TC1_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ -#define TC1_CMPA_bp 0 /* Compare A Output Value bit position. */ - -/* TC1.CTRLD bit masks and bit positions */ -#define TC1_EVACT_gm 0xE0 /* Event Action group mask. */ -#define TC1_EVACT_gp 5 /* Event Action group position. */ -#define TC1_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ -#define TC1_EVACT0_bp 5 /* Event Action bit 0 position. */ -#define TC1_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ -#define TC1_EVACT1_bp 6 /* Event Action bit 1 position. */ -#define TC1_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ -#define TC1_EVACT2_bp 7 /* Event Action bit 2 position. */ - -#define TC1_EVDLY_bm 0x10 /* Event Delay bit mask. */ -#define TC1_EVDLY_bp 4 /* Event Delay bit position. */ - -#define TC1_EVSEL_gm 0x0F /* Event Source Select group mask. */ -#define TC1_EVSEL_gp 0 /* Event Source Select group position. */ -#define TC1_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ -#define TC1_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ -#define TC1_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ -#define TC1_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ -#define TC1_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ -#define TC1_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ -#define TC1_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ -#define TC1_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ - -/* TC1.CTRLE bit masks and bit positions */ -#define TC1_BYTEM_bm 0x01 /* Byte Mode bit mask. */ -#define TC1_BYTEM_bp 0 /* Byte Mode bit position. */ - -/* TC1.INTCTRLA bit masks and bit positions */ -#define TC1_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ -#define TC1_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ -#define TC1_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ -#define TC1_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ -#define TC1_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ -#define TC1_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ - -#define TC1_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ -#define TC1_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ -#define TC1_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ -#define TC1_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ -#define TC1_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ -#define TC1_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ - -/* TC1.INTCTRLB bit masks and bit positions */ -#define TC1_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ -#define TC1_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ -#define TC1_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ -#define TC1_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ -#define TC1_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ -#define TC1_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ - -#define TC1_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ -#define TC1_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ -#define TC1_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ -#define TC1_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ -#define TC1_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ -#define TC1_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ - -/* TC1.CTRLFCLR bit masks and bit positions */ -#define TC1_CMD_gm 0x0C /* Command group mask. */ -#define TC1_CMD_gp 2 /* Command group position. */ -#define TC1_CMD0_bm (1<<2) /* Command bit 0 mask. */ -#define TC1_CMD0_bp 2 /* Command bit 0 position. */ -#define TC1_CMD1_bm (1<<3) /* Command bit 1 mask. */ -#define TC1_CMD1_bp 3 /* Command bit 1 position. */ - -#define TC1_LUPD_bm 0x02 /* Lock Update bit mask. */ -#define TC1_LUPD_bp 1 /* Lock Update bit position. */ - -#define TC1_DIR_bm 0x01 /* Direction bit mask. */ -#define TC1_DIR_bp 0 /* Direction bit position. */ - -/* TC1.CTRLFSET bit masks and bit positions */ -/* TC1_CMD Predefined. */ -/* TC1_CMD Predefined. */ - -/* TC1_LUPD Predefined. */ -/* TC1_LUPD Predefined. */ - -/* TC1_DIR Predefined. */ -/* TC1_DIR Predefined. */ - -/* TC1.CTRLGCLR bit masks and bit positions */ -#define TC1_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ -#define TC1_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ - -#define TC1_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ -#define TC1_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ - -#define TC1_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ -#define TC1_PERBV_bp 0 /* Period Buffer Valid bit position. */ - -/* TC1.CTRLGSET bit masks and bit positions */ -/* TC1_CCBBV Predefined. */ -/* TC1_CCBBV Predefined. */ - -/* TC1_CCABV Predefined. */ -/* TC1_CCABV Predefined. */ - -/* TC1_PERBV Predefined. */ -/* TC1_PERBV Predefined. */ - -/* TC1.INTFLAGS bit masks and bit positions */ -#define TC1_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ -#define TC1_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ - -#define TC1_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ -#define TC1_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ - -#define TC1_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ -#define TC1_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ - -#define TC1_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ -#define TC1_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ - -/* TC2 - 16-bit Timer/Counter type 2 */ -/* TC2.CTRLA bit masks and bit positions */ -#define TC2_CLKSEL_gm 0x0F /* Clock Selection group mask. */ -#define TC2_CLKSEL_gp 0 /* Clock Selection group position. */ -#define TC2_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ -#define TC2_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ -#define TC2_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ -#define TC2_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ -#define TC2_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ -#define TC2_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ -#define TC2_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ -#define TC2_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ - -/* TC2.CTRLB bit masks and bit positions */ -#define TC2_HCMPDEN_bm 0x80 /* High Byte Compare D Enable bit mask. */ -#define TC2_HCMPDEN_bp 7 /* High Byte Compare D Enable bit position. */ - -#define TC2_HCMPCEN_bm 0x40 /* High Byte Compare C Enable bit mask. */ -#define TC2_HCMPCEN_bp 6 /* High Byte Compare C Enable bit position. */ - -#define TC2_HCMPBEN_bm 0x20 /* High Byte Compare B Enable bit mask. */ -#define TC2_HCMPBEN_bp 5 /* High Byte Compare B Enable bit position. */ - -#define TC2_HCMPAEN_bm 0x10 /* High Byte Compare A Enable bit mask. */ -#define TC2_HCMPAEN_bp 4 /* High Byte Compare A Enable bit position. */ - -#define TC2_LCMPDEN_bm 0x08 /* Low Byte Compare D Enable bit mask. */ -#define TC2_LCMPDEN_bp 3 /* Low Byte Compare D Enable bit position. */ - -#define TC2_LCMPCEN_bm 0x04 /* Low Byte Compare C Enable bit mask. */ -#define TC2_LCMPCEN_bp 2 /* Low Byte Compare C Enable bit position. */ - -#define TC2_LCMPBEN_bm 0x02 /* Low Byte Compare B Enable bit mask. */ -#define TC2_LCMPBEN_bp 1 /* Low Byte Compare B Enable bit position. */ - -#define TC2_LCMPAEN_bm 0x01 /* Low Byte Compare A Enable bit mask. */ -#define TC2_LCMPAEN_bp 0 /* Low Byte Compare A Enable bit position. */ - -/* TC2.CTRLC bit masks and bit positions */ -#define TC2_HCMPD_bm 0x80 /* High Byte Compare D Output Value bit mask. */ -#define TC2_HCMPD_bp 7 /* High Byte Compare D Output Value bit position. */ - -#define TC2_HCMPC_bm 0x40 /* High Byte Compare C Output Value bit mask. */ -#define TC2_HCMPC_bp 6 /* High Byte Compare C Output Value bit position. */ - -#define TC2_HCMPB_bm 0x20 /* High Byte Compare B Output Value bit mask. */ -#define TC2_HCMPB_bp 5 /* High Byte Compare B Output Value bit position. */ - -#define TC2_HCMPA_bm 0x10 /* High Byte Compare A Output Value bit mask. */ -#define TC2_HCMPA_bp 4 /* High Byte Compare A Output Value bit position. */ - -#define TC2_LCMPD_bm 0x08 /* Low Byte Compare D Output Value bit mask. */ -#define TC2_LCMPD_bp 3 /* Low Byte Compare D Output Value bit position. */ - -#define TC2_LCMPC_bm 0x04 /* Low Byte Compare C Output Value bit mask. */ -#define TC2_LCMPC_bp 2 /* Low Byte Compare C Output Value bit position. */ - -#define TC2_LCMPB_bm 0x02 /* Low Byte Compare B Output Value bit mask. */ -#define TC2_LCMPB_bp 1 /* Low Byte Compare B Output Value bit position. */ - -#define TC2_LCMPA_bm 0x01 /* Low Byte Compare A Output Value bit mask. */ -#define TC2_LCMPA_bp 0 /* Low Byte Compare A Output Value bit position. */ - -/* TC2.CTRLE bit masks and bit positions */ -#define TC2_BYTEM_gm 0x03 /* Byte Mode group mask. */ -#define TC2_BYTEM_gp 0 /* Byte Mode group position. */ -#define TC2_BYTEM0_bm (1<<0) /* Byte Mode bit 0 mask. */ -#define TC2_BYTEM0_bp 0 /* Byte Mode bit 0 position. */ -#define TC2_BYTEM1_bm (1<<1) /* Byte Mode bit 1 mask. */ -#define TC2_BYTEM1_bp 1 /* Byte Mode bit 1 position. */ - -/* TC2.INTCTRLA bit masks and bit positions */ -#define TC2_HUNFINTLVL_gm 0x0C /* High Byte Underflow Interrupt Level group mask. */ -#define TC2_HUNFINTLVL_gp 2 /* High Byte Underflow Interrupt Level group position. */ -#define TC2_HUNFINTLVL0_bm (1<<2) /* High Byte Underflow Interrupt Level bit 0 mask. */ -#define TC2_HUNFINTLVL0_bp 2 /* High Byte Underflow Interrupt Level bit 0 position. */ -#define TC2_HUNFINTLVL1_bm (1<<3) /* High Byte Underflow Interrupt Level bit 1 mask. */ -#define TC2_HUNFINTLVL1_bp 3 /* High Byte Underflow Interrupt Level bit 1 position. */ - -#define TC2_LUNFINTLVL_gm 0x03 /* Low Byte Underflow interrupt level group mask. */ -#define TC2_LUNFINTLVL_gp 0 /* Low Byte Underflow interrupt level group position. */ -#define TC2_LUNFINTLVL0_bm (1<<0) /* Low Byte Underflow interrupt level bit 0 mask. */ -#define TC2_LUNFINTLVL0_bp 0 /* Low Byte Underflow interrupt level bit 0 position. */ -#define TC2_LUNFINTLVL1_bm (1<<1) /* Low Byte Underflow interrupt level bit 1 mask. */ -#define TC2_LUNFINTLVL1_bp 1 /* Low Byte Underflow interrupt level bit 1 position. */ - -/* TC2.INTCTRLB bit masks and bit positions */ -#define TC2_LCMPDINTLVL_gm 0xC0 /* Low Byte Compare D Interrupt Level group mask. */ -#define TC2_LCMPDINTLVL_gp 6 /* Low Byte Compare D Interrupt Level group position. */ -#define TC2_LCMPDINTLVL0_bm (1<<6) /* Low Byte Compare D Interrupt Level bit 0 mask. */ -#define TC2_LCMPDINTLVL0_bp 6 /* Low Byte Compare D Interrupt Level bit 0 position. */ -#define TC2_LCMPDINTLVL1_bm (1<<7) /* Low Byte Compare D Interrupt Level bit 1 mask. */ -#define TC2_LCMPDINTLVL1_bp 7 /* Low Byte Compare D Interrupt Level bit 1 position. */ - -#define TC2_LCMPCINTLVL_gm 0x30 /* Low Byte Compare C Interrupt Level group mask. */ -#define TC2_LCMPCINTLVL_gp 4 /* Low Byte Compare C Interrupt Level group position. */ -#define TC2_LCMPCINTLVL0_bm (1<<4) /* Low Byte Compare C Interrupt Level bit 0 mask. */ -#define TC2_LCMPCINTLVL0_bp 4 /* Low Byte Compare C Interrupt Level bit 0 position. */ -#define TC2_LCMPCINTLVL1_bm (1<<5) /* Low Byte Compare C Interrupt Level bit 1 mask. */ -#define TC2_LCMPCINTLVL1_bp 5 /* Low Byte Compare C Interrupt Level bit 1 position. */ - -#define TC2_LCMPBINTLVL_gm 0x0C /* Low Byte Compare B Interrupt Level group mask. */ -#define TC2_LCMPBINTLVL_gp 2 /* Low Byte Compare B Interrupt Level group position. */ -#define TC2_LCMPBINTLVL0_bm (1<<2) /* Low Byte Compare B Interrupt Level bit 0 mask. */ -#define TC2_LCMPBINTLVL0_bp 2 /* Low Byte Compare B Interrupt Level bit 0 position. */ -#define TC2_LCMPBINTLVL1_bm (1<<3) /* Low Byte Compare B Interrupt Level bit 1 mask. */ -#define TC2_LCMPBINTLVL1_bp 3 /* Low Byte Compare B Interrupt Level bit 1 position. */ - -#define TC2_LCMPAINTLVL_gm 0x03 /* Low Byte Compare A Interrupt Level group mask. */ -#define TC2_LCMPAINTLVL_gp 0 /* Low Byte Compare A Interrupt Level group position. */ -#define TC2_LCMPAINTLVL0_bm (1<<0) /* Low Byte Compare A Interrupt Level bit 0 mask. */ -#define TC2_LCMPAINTLVL0_bp 0 /* Low Byte Compare A Interrupt Level bit 0 position. */ -#define TC2_LCMPAINTLVL1_bm (1<<1) /* Low Byte Compare A Interrupt Level bit 1 mask. */ -#define TC2_LCMPAINTLVL1_bp 1 /* Low Byte Compare A Interrupt Level bit 1 position. */ - -/* TC2.CTRLF bit masks and bit positions */ -#define TC2_CMD_gm 0x0C /* Command group mask. */ -#define TC2_CMD_gp 2 /* Command group position. */ -#define TC2_CMD0_bm (1<<2) /* Command bit 0 mask. */ -#define TC2_CMD0_bp 2 /* Command bit 0 position. */ -#define TC2_CMD1_bm (1<<3) /* Command bit 1 mask. */ -#define TC2_CMD1_bp 3 /* Command bit 1 position. */ - -#define TC2_CMDEN_gm 0x03 /* Command Enable group mask. */ -#define TC2_CMDEN_gp 0 /* Command Enable group position. */ -#define TC2_CMDEN0_bm (1<<0) /* Command Enable bit 0 mask. */ -#define TC2_CMDEN0_bp 0 /* Command Enable bit 0 position. */ -#define TC2_CMDEN1_bm (1<<1) /* Command Enable bit 1 mask. */ -#define TC2_CMDEN1_bp 1 /* Command Enable bit 1 position. */ - -/* TC2.INTFLAGS bit masks and bit positions */ -#define TC2_LCMPDIF_bm 0x80 /* Low Byte Compare D Interrupt Flag bit mask. */ -#define TC2_LCMPDIF_bp 7 /* Low Byte Compare D Interrupt Flag bit position. */ - -#define TC2_LCMPCIF_bm 0x40 /* Low Byte Compare C Interrupt Flag bit mask. */ -#define TC2_LCMPCIF_bp 6 /* Low Byte Compare C Interrupt Flag bit position. */ - -#define TC2_LCMPBIF_bm 0x20 /* Low Byte Compare B Interrupt Flag bit mask. */ -#define TC2_LCMPBIF_bp 5 /* Low Byte Compare B Interrupt Flag bit position. */ - -#define TC2_LCMPAIF_bm 0x10 /* Low Byte Compare A Interrupt Flag bit mask. */ -#define TC2_LCMPAIF_bp 4 /* Low Byte Compare A Interrupt Flag bit position. */ - -#define TC2_HUNFIF_bm 0x02 /* High Byte Underflow Interrupt Flag bit mask. */ -#define TC2_HUNFIF_bp 1 /* High Byte Underflow Interrupt Flag bit position. */ - -#define TC2_LUNFIF_bm 0x01 /* Low Byte Underflow Interrupt Flag bit mask. */ -#define TC2_LUNFIF_bp 0 /* Low Byte Underflow Interrupt Flag bit position. */ - -/* AWEX - Timer/Counter Advanced Waveform Extension */ -/* AWEX.CTRL bit masks and bit positions */ -#define AWEX_PGM_bm 0x20 /* Pattern Generation Mode bit mask. */ -#define AWEX_PGM_bp 5 /* Pattern Generation Mode bit position. */ - -#define AWEX_CWCM_bm 0x10 /* Common Waveform Channel Mode bit mask. */ -#define AWEX_CWCM_bp 4 /* Common Waveform Channel Mode bit position. */ - -#define AWEX_DTICCDEN_bm 0x08 /* Dead Time Insertion Compare Channel D Enable bit mask. */ -#define AWEX_DTICCDEN_bp 3 /* Dead Time Insertion Compare Channel D Enable bit position. */ - -#define AWEX_DTICCCEN_bm 0x04 /* Dead Time Insertion Compare Channel C Enable bit mask. */ -#define AWEX_DTICCCEN_bp 2 /* Dead Time Insertion Compare Channel C Enable bit position. */ - -#define AWEX_DTICCBEN_bm 0x02 /* Dead Time Insertion Compare Channel B Enable bit mask. */ -#define AWEX_DTICCBEN_bp 1 /* Dead Time Insertion Compare Channel B Enable bit position. */ - -#define AWEX_DTICCAEN_bm 0x01 /* Dead Time Insertion Compare Channel A Enable bit mask. */ -#define AWEX_DTICCAEN_bp 0 /* Dead Time Insertion Compare Channel A Enable bit position. */ - -/* AWEX.FDCTRL bit masks and bit positions */ -#define AWEX_FDDBD_bm 0x10 /* Fault Detect on Disable Break Disable bit mask. */ -#define AWEX_FDDBD_bp 4 /* Fault Detect on Disable Break Disable bit position. */ - -#define AWEX_FDMODE_bm 0x04 /* Fault Detect Mode bit mask. */ -#define AWEX_FDMODE_bp 2 /* Fault Detect Mode bit position. */ - -#define AWEX_FDACT_gm 0x03 /* Fault Detect Action group mask. */ -#define AWEX_FDACT_gp 0 /* Fault Detect Action group position. */ -#define AWEX_FDACT0_bm (1<<0) /* Fault Detect Action bit 0 mask. */ -#define AWEX_FDACT0_bp 0 /* Fault Detect Action bit 0 position. */ -#define AWEX_FDACT1_bm (1<<1) /* Fault Detect Action bit 1 mask. */ -#define AWEX_FDACT1_bp 1 /* Fault Detect Action bit 1 position. */ - -/* AWEX.STATUS bit masks and bit positions */ -#define AWEX_FDF_bm 0x04 /* Fault Detect Flag bit mask. */ -#define AWEX_FDF_bp 2 /* Fault Detect Flag bit position. */ - -#define AWEX_DTHSBUFV_bm 0x02 /* Dead Time High Side Buffer Valid bit mask. */ -#define AWEX_DTHSBUFV_bp 1 /* Dead Time High Side Buffer Valid bit position. */ - -#define AWEX_DTLSBUFV_bm 0x01 /* Dead Time Low Side Buffer Valid bit mask. */ -#define AWEX_DTLSBUFV_bp 0 /* Dead Time Low Side Buffer Valid bit position. */ - -/* AWEX.STATUSSET bit masks and bit positions */ -/* AWEX_FDF Predefined. */ -/* AWEX_FDF Predefined. */ - -/* AWEX_DTHSBUFV Predefined. */ -/* AWEX_DTHSBUFV Predefined. */ - -/* AWEX_DTLSBUFV Predefined. */ -/* AWEX_DTLSBUFV Predefined. */ - -/* HIRES - Timer/Counter High-Resolution Extension */ -/* HIRES.CTRLA bit masks and bit positions */ -#define HIRES_HREN_gm 0x03 /* High Resolution Enable group mask. */ -#define HIRES_HREN_gp 0 /* High Resolution Enable group position. */ -#define HIRES_HREN0_bm (1<<0) /* High Resolution Enable bit 0 mask. */ -#define HIRES_HREN0_bp 0 /* High Resolution Enable bit 0 position. */ -#define HIRES_HREN1_bm (1<<1) /* High Resolution Enable bit 1 mask. */ -#define HIRES_HREN1_bp 1 /* High Resolution Enable bit 1 position. */ - -/* USART - Universal Asynchronous Receiver-Transmitter */ -/* USART.STATUS bit masks and bit positions */ -#define USART_RXCIF_bm 0x80 /* Receive Interrupt Flag bit mask. */ -#define USART_RXCIF_bp 7 /* Receive Interrupt Flag bit position. */ - -#define USART_TXCIF_bm 0x40 /* Transmit Interrupt Flag bit mask. */ -#define USART_TXCIF_bp 6 /* Transmit Interrupt Flag bit position. */ - -#define USART_DREIF_bm 0x20 /* Data Register Empty Flag bit mask. */ -#define USART_DREIF_bp 5 /* Data Register Empty Flag bit position. */ - -#define USART_FERR_bm 0x10 /* Frame Error bit mask. */ -#define USART_FERR_bp 4 /* Frame Error bit position. */ - -#define USART_BUFOVF_bm 0x08 /* Buffer Overflow bit mask. */ -#define USART_BUFOVF_bp 3 /* Buffer Overflow bit position. */ - -#define USART_PERR_bm 0x04 /* Parity Error bit mask. */ -#define USART_PERR_bp 2 /* Parity Error bit position. */ - -#define USART_RXB8_bm 0x01 /* Receive Bit 8 bit mask. */ -#define USART_RXB8_bp 0 /* Receive Bit 8 bit position. */ - -/* USART.CTRLA bit masks and bit positions */ -#define USART_RXCINTLVL_gm 0x30 /* Receive Interrupt Level group mask. */ -#define USART_RXCINTLVL_gp 4 /* Receive Interrupt Level group position. */ -#define USART_RXCINTLVL0_bm (1<<4) /* Receive Interrupt Level bit 0 mask. */ -#define USART_RXCINTLVL0_bp 4 /* Receive Interrupt Level bit 0 position. */ -#define USART_RXCINTLVL1_bm (1<<5) /* Receive Interrupt Level bit 1 mask. */ -#define USART_RXCINTLVL1_bp 5 /* Receive Interrupt Level bit 1 position. */ - -#define USART_TXCINTLVL_gm 0x0C /* Transmit Interrupt Level group mask. */ -#define USART_TXCINTLVL_gp 2 /* Transmit Interrupt Level group position. */ -#define USART_TXCINTLVL0_bm (1<<2) /* Transmit Interrupt Level bit 0 mask. */ -#define USART_TXCINTLVL0_bp 2 /* Transmit Interrupt Level bit 0 position. */ -#define USART_TXCINTLVL1_bm (1<<3) /* Transmit Interrupt Level bit 1 mask. */ -#define USART_TXCINTLVL1_bp 3 /* Transmit Interrupt Level bit 1 position. */ - -#define USART_DREINTLVL_gm 0x03 /* Data Register Empty Interrupt Level group mask. */ -#define USART_DREINTLVL_gp 0 /* Data Register Empty Interrupt Level group position. */ -#define USART_DREINTLVL0_bm (1<<0) /* Data Register Empty Interrupt Level bit 0 mask. */ -#define USART_DREINTLVL0_bp 0 /* Data Register Empty Interrupt Level bit 0 position. */ -#define USART_DREINTLVL1_bm (1<<1) /* Data Register Empty Interrupt Level bit 1 mask. */ -#define USART_DREINTLVL1_bp 1 /* Data Register Empty Interrupt Level bit 1 position. */ - -/* USART.CTRLB bit masks and bit positions */ -#define USART_RXEN_bm 0x10 /* Receiver Enable bit mask. */ -#define USART_RXEN_bp 4 /* Receiver Enable bit position. */ - -#define USART_TXEN_bm 0x08 /* Transmitter Enable bit mask. */ -#define USART_TXEN_bp 3 /* Transmitter Enable bit position. */ - -#define USART_CLK2X_bm 0x04 /* Double transmission speed bit mask. */ -#define USART_CLK2X_bp 2 /* Double transmission speed bit position. */ - -#define USART_MPCM_bm 0x02 /* Multi-processor Communication Mode bit mask. */ -#define USART_MPCM_bp 1 /* Multi-processor Communication Mode bit position. */ - -#define USART_TXB8_bm 0x01 /* Transmit bit 8 bit mask. */ -#define USART_TXB8_bp 0 /* Transmit bit 8 bit position. */ - -/* USART.CTRLC bit masks and bit positions */ -#define USART_CMODE_gm 0xC0 /* Communication Mode group mask. */ -#define USART_CMODE_gp 6 /* Communication Mode group position. */ -#define USART_CMODE0_bm (1<<6) /* Communication Mode bit 0 mask. */ -#define USART_CMODE0_bp 6 /* Communication Mode bit 0 position. */ -#define USART_CMODE1_bm (1<<7) /* Communication Mode bit 1 mask. */ -#define USART_CMODE1_bp 7 /* Communication Mode bit 1 position. */ - -#define USART_PMODE_gm 0x30 /* Parity Mode group mask. */ -#define USART_PMODE_gp 4 /* Parity Mode group position. */ -#define USART_PMODE0_bm (1<<4) /* Parity Mode bit 0 mask. */ -#define USART_PMODE0_bp 4 /* Parity Mode bit 0 position. */ -#define USART_PMODE1_bm (1<<5) /* Parity Mode bit 1 mask. */ -#define USART_PMODE1_bp 5 /* Parity Mode bit 1 position. */ - -#define USART_SBMODE_bm 0x08 /* Stop Bit Mode bit mask. */ -#define USART_SBMODE_bp 3 /* Stop Bit Mode bit position. */ - -#define USART_CHSIZE_gm 0x07 /* Character Size group mask. */ -#define USART_CHSIZE_gp 0 /* Character Size group position. */ -#define USART_CHSIZE0_bm (1<<0) /* Character Size bit 0 mask. */ -#define USART_CHSIZE0_bp 0 /* Character Size bit 0 position. */ -#define USART_CHSIZE1_bm (1<<1) /* Character Size bit 1 mask. */ -#define USART_CHSIZE1_bp 1 /* Character Size bit 1 position. */ -#define USART_CHSIZE2_bm (1<<2) /* Character Size bit 2 mask. */ -#define USART_CHSIZE2_bp 2 /* Character Size bit 2 position. */ - -/* USART.BAUDCTRLA bit masks and bit positions */ -#define USART_BSEL_gm 0xFF /* Baud Rate Selection Bits [7:0] group mask. */ -#define USART_BSEL_gp 0 /* Baud Rate Selection Bits [7:0] group position. */ -#define USART_BSEL0_bm (1<<0) /* Baud Rate Selection Bits [7:0] bit 0 mask. */ -#define USART_BSEL0_bp 0 /* Baud Rate Selection Bits [7:0] bit 0 position. */ -#define USART_BSEL1_bm (1<<1) /* Baud Rate Selection Bits [7:0] bit 1 mask. */ -#define USART_BSEL1_bp 1 /* Baud Rate Selection Bits [7:0] bit 1 position. */ -#define USART_BSEL2_bm (1<<2) /* Baud Rate Selection Bits [7:0] bit 2 mask. */ -#define USART_BSEL2_bp 2 /* Baud Rate Selection Bits [7:0] bit 2 position. */ -#define USART_BSEL3_bm (1<<3) /* Baud Rate Selection Bits [7:0] bit 3 mask. */ -#define USART_BSEL3_bp 3 /* Baud Rate Selection Bits [7:0] bit 3 position. */ -#define USART_BSEL4_bm (1<<4) /* Baud Rate Selection Bits [7:0] bit 4 mask. */ -#define USART_BSEL4_bp 4 /* Baud Rate Selection Bits [7:0] bit 4 position. */ -#define USART_BSEL5_bm (1<<5) /* Baud Rate Selection Bits [7:0] bit 5 mask. */ -#define USART_BSEL5_bp 5 /* Baud Rate Selection Bits [7:0] bit 5 position. */ -#define USART_BSEL6_bm (1<<6) /* Baud Rate Selection Bits [7:0] bit 6 mask. */ -#define USART_BSEL6_bp 6 /* Baud Rate Selection Bits [7:0] bit 6 position. */ -#define USART_BSEL7_bm (1<<7) /* Baud Rate Selection Bits [7:0] bit 7 mask. */ -#define USART_BSEL7_bp 7 /* Baud Rate Selection Bits [7:0] bit 7 position. */ - -/* USART.BAUDCTRLB bit masks and bit positions */ -#define USART_BSCALE_gm 0xF0 /* Baud Rate Scale group mask. */ -#define USART_BSCALE_gp 4 /* Baud Rate Scale group position. */ -#define USART_BSCALE0_bm (1<<4) /* Baud Rate Scale bit 0 mask. */ -#define USART_BSCALE0_bp 4 /* Baud Rate Scale bit 0 position. */ -#define USART_BSCALE1_bm (1<<5) /* Baud Rate Scale bit 1 mask. */ -#define USART_BSCALE1_bp 5 /* Baud Rate Scale bit 1 position. */ -#define USART_BSCALE2_bm (1<<6) /* Baud Rate Scale bit 2 mask. */ -#define USART_BSCALE2_bp 6 /* Baud Rate Scale bit 2 position. */ -#define USART_BSCALE3_bm (1<<7) /* Baud Rate Scale bit 3 mask. */ -#define USART_BSCALE3_bp 7 /* Baud Rate Scale bit 3 position. */ - -/* USART_BSEL Predefined. */ -/* USART_BSEL Predefined. */ - -/* SPI - Serial Peripheral Interface */ -/* SPI.CTRL bit masks and bit positions */ -#define SPI_CLK2X_bm 0x80 /* Enable Double Speed bit mask. */ -#define SPI_CLK2X_bp 7 /* Enable Double Speed bit position. */ - -#define SPI_ENABLE_bm 0x40 /* Enable Module bit mask. */ -#define SPI_ENABLE_bp 6 /* Enable Module bit position. */ - -#define SPI_DORD_bm 0x20 /* Data Order Setting bit mask. */ -#define SPI_DORD_bp 5 /* Data Order Setting bit position. */ - -#define SPI_MASTER_bm 0x10 /* Master Operation Enable bit mask. */ -#define SPI_MASTER_bp 4 /* Master Operation Enable bit position. */ - -#define SPI_MODE_gm 0x0C /* SPI Mode group mask. */ -#define SPI_MODE_gp 2 /* SPI Mode group position. */ -#define SPI_MODE0_bm (1<<2) /* SPI Mode bit 0 mask. */ -#define SPI_MODE0_bp 2 /* SPI Mode bit 0 position. */ -#define SPI_MODE1_bm (1<<3) /* SPI Mode bit 1 mask. */ -#define SPI_MODE1_bp 3 /* SPI Mode bit 1 position. */ - -#define SPI_PRESCALER_gm 0x03 /* Prescaler group mask. */ -#define SPI_PRESCALER_gp 0 /* Prescaler group position. */ -#define SPI_PRESCALER0_bm (1<<0) /* Prescaler bit 0 mask. */ -#define SPI_PRESCALER0_bp 0 /* Prescaler bit 0 position. */ -#define SPI_PRESCALER1_bm (1<<1) /* Prescaler bit 1 mask. */ -#define SPI_PRESCALER1_bp 1 /* Prescaler bit 1 position. */ - -/* SPI.INTCTRL bit masks and bit positions */ -#define SPI_INTLVL_gm 0x03 /* Interrupt level group mask. */ -#define SPI_INTLVL_gp 0 /* Interrupt level group position. */ -#define SPI_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */ -#define SPI_INTLVL0_bp 0 /* Interrupt level bit 0 position. */ -#define SPI_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */ -#define SPI_INTLVL1_bp 1 /* Interrupt level bit 1 position. */ - -/* SPI.STATUS bit masks and bit positions */ -#define SPI_IF_bm 0x80 /* Interrupt Flag bit mask. */ -#define SPI_IF_bp 7 /* Interrupt Flag bit position. */ - -#define SPI_WRCOL_bm 0x40 /* Write Collision bit mask. */ -#define SPI_WRCOL_bp 6 /* Write Collision bit position. */ - -/* IRCOM - IR Communication Module */ -/* IRCOM.CTRL bit masks and bit positions */ -#define IRCOM_EVSEL_gm 0x0F /* Event Channel Select group mask. */ -#define IRCOM_EVSEL_gp 0 /* Event Channel Select group position. */ -#define IRCOM_EVSEL0_bm (1<<0) /* Event Channel Select bit 0 mask. */ -#define IRCOM_EVSEL0_bp 0 /* Event Channel Select bit 0 position. */ -#define IRCOM_EVSEL1_bm (1<<1) /* Event Channel Select bit 1 mask. */ -#define IRCOM_EVSEL1_bp 1 /* Event Channel Select bit 1 position. */ -#define IRCOM_EVSEL2_bm (1<<2) /* Event Channel Select bit 2 mask. */ -#define IRCOM_EVSEL2_bp 2 /* Event Channel Select bit 2 position. */ -#define IRCOM_EVSEL3_bm (1<<3) /* Event Channel Select bit 3 mask. */ -#define IRCOM_EVSEL3_bp 3 /* Event Channel Select bit 3 position. */ - -/* LCD - LCD Controller */ -/* LCD.CTRLA bit masks and bit positions */ -#define LCD_ENABLE_bm 0x80 /* LCD Enable bit mask. */ -#define LCD_ENABLE_bp 7 /* LCD Enable bit position. */ - -#define LCD_XBIAS_bm 0x40 /* External Register Bias Generation bit mask. */ -#define LCD_XBIAS_bp 6 /* External Register Bias Generation bit position. */ - -#define LCD_DATCLK_bm 0x20 /* Data Register Lock bit mask. */ -#define LCD_DATCLK_bp 5 /* Data Register Lock bit position. */ - -#define LCD_COMSWP_bm 0x10 /* Common Bus Swap bit mask. */ -#define LCD_COMSWP_bp 4 /* Common Bus Swap bit position. */ - -#define LCD_SEGSWP_bm 0x08 /* Segment Bus Swap bit mask. */ -#define LCD_SEGSWP_bp 3 /* Segment Bus Swap bit position. */ - -#define LCD_CLRDT_bm 0x04 /* Clear Data Register bit mask. */ -#define LCD_CLRDT_bp 2 /* Clear Data Register bit position. */ - -#define LCD_SEGON_bm 0x02 /* Segments On bit mask. */ -#define LCD_SEGON_bp 1 /* Segments On bit position. */ - -#define LCD_BLANK_bm 0x01 /* Blanking Display Mode bit mask. */ -#define LCD_BLANK_bp 0 /* Blanking Display Mode bit position. */ - -/* LCD.CTRLB bit masks and bit positions */ -#define LCD_PRESC_bm 0x80 /* LCD Prescaler Select bit mask. */ -#define LCD_PRESC_bp 7 /* LCD Prescaler Select bit position. */ - -#define LCD_CLKDIV_gm 0x70 /* LCD Clock Divide group mask. */ -#define LCD_CLKDIV_gp 4 /* LCD Clock Divide group position. */ -#define LCD_CLKDIV0_bm (1<<4) /* LCD Clock Divide bit 0 mask. */ -#define LCD_CLKDIV0_bp 4 /* LCD Clock Divide bit 0 position. */ -#define LCD_CLKDIV1_bm (1<<5) /* LCD Clock Divide bit 1 mask. */ -#define LCD_CLKDIV1_bp 5 /* LCD Clock Divide bit 1 position. */ -#define LCD_CLKDIV2_bm (1<<6) /* LCD Clock Divide bit 2 mask. */ -#define LCD_CLKDIV2_bp 6 /* LCD Clock Divide bit 2 position. */ - -#define LCD_LPWAV_bm 0x08 /* Low Power Waveform bit mask. */ -#define LCD_LPWAV_bp 3 /* Low Power Waveform bit position. */ - -#define LCD_DUTY_gm 0x03 /* Duty Select group mask. */ -#define LCD_DUTY_gp 0 /* Duty Select group position. */ -#define LCD_DUTY0_bm (1<<0) /* Duty Select bit 0 mask. */ -#define LCD_DUTY0_bp 0 /* Duty Select bit 0 position. */ -#define LCD_DUTY1_bm (1<<1) /* Duty Select bit 1 mask. */ -#define LCD_DUTY1_bp 1 /* Duty Select bit 1 position. */ - -/* LCD.CTRLC bit masks and bit positions */ -#define LCD_PMSK_gm 0x3F /* LCD Port Mask group mask. */ -#define LCD_PMSK_gp 0 /* LCD Port Mask group position. */ -#define LCD_PMSK0_bm (1<<0) /* LCD Port Mask bit 0 mask. */ -#define LCD_PMSK0_bp 0 /* LCD Port Mask bit 0 position. */ -#define LCD_PMSK1_bm (1<<1) /* LCD Port Mask bit 1 mask. */ -#define LCD_PMSK1_bp 1 /* LCD Port Mask bit 1 position. */ -#define LCD_PMSK2_bm (1<<2) /* LCD Port Mask bit 2 mask. */ -#define LCD_PMSK2_bp 2 /* LCD Port Mask bit 2 position. */ -#define LCD_PMSK3_bm (1<<3) /* LCD Port Mask bit 3 mask. */ -#define LCD_PMSK3_bp 3 /* LCD Port Mask bit 3 position. */ -#define LCD_PMSK4_bm (1<<4) /* LCD Port Mask bit 4 mask. */ -#define LCD_PMSK4_bp 4 /* LCD Port Mask bit 4 position. */ -#define LCD_PMSK5_bm (1<<5) /* LCD Port Mask bit 5 mask. */ -#define LCD_PMSK5_bp 5 /* LCD Port Mask bit 5 position. */ - -/* LCD.INTCTRL bit masks and bit positions */ -#define LCD_XIME_gm 0xF8 /* eXtended Interrupt Mode Enable group mask. */ -#define LCD_XIME_gp 3 /* eXtended Interrupt Mode Enable group position. */ -#define LCD_XIME0_bm (1<<3) /* eXtended Interrupt Mode Enable bit 0 mask. */ -#define LCD_XIME0_bp 3 /* eXtended Interrupt Mode Enable bit 0 position. */ -#define LCD_XIME1_bm (1<<4) /* eXtended Interrupt Mode Enable bit 1 mask. */ -#define LCD_XIME1_bp 4 /* eXtended Interrupt Mode Enable bit 1 position. */ -#define LCD_XIME2_bm (1<<5) /* eXtended Interrupt Mode Enable bit 2 mask. */ -#define LCD_XIME2_bp 5 /* eXtended Interrupt Mode Enable bit 2 position. */ -#define LCD_XIME3_bm (1<<6) /* eXtended Interrupt Mode Enable bit 3 mask. */ -#define LCD_XIME3_bp 6 /* eXtended Interrupt Mode Enable bit 3 position. */ -#define LCD_XIME4_bm (1<<7) /* eXtended Interrupt Mode Enable bit 4 mask. */ -#define LCD_XIME4_bp 7 /* eXtended Interrupt Mode Enable bit 4 position. */ - -#define LCD_FCINTLVL_gm 0x03 /* Interrupt Level group mask. */ -#define LCD_FCINTLVL_gp 0 /* Interrupt Level group position. */ -#define LCD_FCINTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */ -#define LCD_FCINTLVL0_bp 0 /* Interrupt Level bit 0 position. */ -#define LCD_FCINTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ -#define LCD_FCINTLVL1_bp 1 /* Interrupt Level bit 1 position. */ - -/* LCD.INTFLAG bit masks and bit positions */ -#define LCD_FCIF_bm 0x01 /* LCD Frame Completed Interrupt Flag bit mask. */ -#define LCD_FCIF_bp 0 /* LCD Frame Completed Interrupt Flag bit position. */ - -/* LCD.CTRLD bit masks and bit positions */ -#define LCD_BLINKEN_bm 0x08 /* Blink Enable bit mask. */ -#define LCD_BLINKEN_bp 3 /* Blink Enable bit position. */ - -#define LCD_BLINKRATE_gm 0x03 /* LCD Blink Rate group mask. */ -#define LCD_BLINKRATE_gp 0 /* LCD Blink Rate group position. */ -#define LCD_BLINKRATE0_bm (1<<0) /* LCD Blink Rate bit 0 mask. */ -#define LCD_BLINKRATE0_bp 0 /* LCD Blink Rate bit 0 position. */ -#define LCD_BLINKRATE1_bm (1<<1) /* LCD Blink Rate bit 1 mask. */ -#define LCD_BLINKRATE1_bp 1 /* LCD Blink Rate bit 1 position. */ - -/* LCD.CTRLE bit masks and bit positions */ -#define LCD_BPS1_gm 0xF0 /* Blink Pixel Selection 1 group mask. */ -#define LCD_BPS1_gp 4 /* Blink Pixel Selection 1 group position. */ -#define LCD_BPS10_bm (1<<4) /* Blink Pixel Selection 1 bit 0 mask. */ -#define LCD_BPS10_bp 4 /* Blink Pixel Selection 1 bit 0 position. */ -#define LCD_BPS11_bm (1<<5) /* Blink Pixel Selection 1 bit 1 mask. */ -#define LCD_BPS11_bp 5 /* Blink Pixel Selection 1 bit 1 position. */ -#define LCD_BPS12_bm (1<<6) /* Blink Pixel Selection 1 bit 2 mask. */ -#define LCD_BPS12_bp 6 /* Blink Pixel Selection 1 bit 2 position. */ -#define LCD_BPS13_bm (1<<7) /* Blink Pixel Selection 1 bit 3 mask. */ -#define LCD_BPS13_bp 7 /* Blink Pixel Selection 1 bit 3 position. */ - -#define LCD_BPS0_gm 0x0F /* Blink Pixel Selection 0 group mask. */ -#define LCD_BPS0_gp 0 /* Blink Pixel Selection 0 group position. */ -#define LCD_BPS00_bm (1<<0) /* Blink Pixel Selection 0 bit 0 mask. */ -#define LCD_BPS00_bp 0 /* Blink Pixel Selection 0 bit 0 position. */ -#define LCD_BPS01_bm (1<<1) /* Blink Pixel Selection 0 bit 1 mask. */ -#define LCD_BPS01_bp 1 /* Blink Pixel Selection 0 bit 1 position. */ -#define LCD_BPS02_bm (1<<2) /* Blink Pixel Selection 0 bit 2 mask. */ -#define LCD_BPS02_bp 2 /* Blink Pixel Selection 0 bit 2 position. */ -#define LCD_BPS03_bm (1<<3) /* Blink Pixel Selection 0 bit 3 mask. */ -#define LCD_BPS03_bp 3 /* Blink Pixel Selection 0 bit 3 position. */ - -/* LCD.CTRLF bit masks and bit positions */ -#define LCD_FCONT_gm 0x3F /* Fine Contrast group mask. */ -#define LCD_FCONT_gp 0 /* Fine Contrast group position. */ -#define LCD_FCONT0_bm (1<<0) /* Fine Contrast bit 0 mask. */ -#define LCD_FCONT0_bp 0 /* Fine Contrast bit 0 position. */ -#define LCD_FCONT1_bm (1<<1) /* Fine Contrast bit 1 mask. */ -#define LCD_FCONT1_bp 1 /* Fine Contrast bit 1 position. */ -#define LCD_FCONT2_bm (1<<2) /* Fine Contrast bit 2 mask. */ -#define LCD_FCONT2_bp 2 /* Fine Contrast bit 2 position. */ -#define LCD_FCONT3_bm (1<<3) /* Fine Contrast bit 3 mask. */ -#define LCD_FCONT3_bp 3 /* Fine Contrast bit 3 position. */ -#define LCD_FCONT4_bm (1<<4) /* Fine Contrast bit 4 mask. */ -#define LCD_FCONT4_bp 4 /* Fine Contrast bit 4 position. */ -#define LCD_FCONT5_bm (1<<5) /* Fine Contrast bit 5 mask. */ -#define LCD_FCONT5_bp 5 /* Fine Contrast bit 5 position. */ - -/* LCD.CTRLG bit masks and bit positions */ -#define LCD_TDG_gm 0xC0 /* Type of Digit group mask. */ -#define LCD_TDG_gp 6 /* Type of Digit group position. */ -#define LCD_TDG0_bm (1<<6) /* Type of Digit bit 0 mask. */ -#define LCD_TDG0_bp 6 /* Type of Digit bit 0 position. */ -#define LCD_TDG1_bm (1<<7) /* Type of Digit bit 1 mask. */ -#define LCD_TDG1_bp 7 /* Type of Digit bit 1 position. */ - -#define LCD_STSEG_gm 0x3F /* Start Segment group mask. */ -#define LCD_STSEG_gp 0 /* Start Segment group position. */ -#define LCD_STSEG0_bm (1<<0) /* Start Segment bit 0 mask. */ -#define LCD_STSEG0_bp 0 /* Start Segment bit 0 position. */ -#define LCD_STSEG1_bm (1<<1) /* Start Segment bit 1 mask. */ -#define LCD_STSEG1_bp 1 /* Start Segment bit 1 position. */ -#define LCD_STSEG2_bm (1<<2) /* Start Segment bit 2 mask. */ -#define LCD_STSEG2_bp 2 /* Start Segment bit 2 position. */ -#define LCD_STSEG3_bm (1<<3) /* Start Segment bit 3 mask. */ -#define LCD_STSEG3_bp 3 /* Start Segment bit 3 position. */ -#define LCD_STSEG4_bm (1<<4) /* Start Segment bit 4 mask. */ -#define LCD_STSEG4_bp 4 /* Start Segment bit 4 position. */ -#define LCD_STSEG5_bm (1<<5) /* Start Segment bit 5 mask. */ -#define LCD_STSEG5_bp 5 /* Start Segment bit 5 position. */ - -/* LCD.CTRLH bit masks and bit positions */ -#define LCD_DEC_bm 0x80 /* Decrement of Start Segment bit mask. */ -#define LCD_DEC_bp 7 /* Decrement of Start Segment bit position. */ - -#define LCD_DCODE_gm 0x7F /* Display Code group mask. */ -#define LCD_DCODE_gp 0 /* Display Code group position. */ -#define LCD_DCODE0_bm (1<<0) /* Display Code bit 0 mask. */ -#define LCD_DCODE0_bp 0 /* Display Code bit 0 position. */ -#define LCD_DCODE1_bm (1<<1) /* Display Code bit 1 mask. */ -#define LCD_DCODE1_bp 1 /* Display Code bit 1 position. */ -#define LCD_DCODE2_bm (1<<2) /* Display Code bit 2 mask. */ -#define LCD_DCODE2_bp 2 /* Display Code bit 2 position. */ -#define LCD_DCODE3_bm (1<<3) /* Display Code bit 3 mask. */ -#define LCD_DCODE3_bp 3 /* Display Code bit 3 position. */ -#define LCD_DCODE4_bm (1<<4) /* Display Code bit 4 mask. */ -#define LCD_DCODE4_bp 4 /* Display Code bit 4 position. */ -#define LCD_DCODE5_bm (1<<5) /* Display Code bit 5 mask. */ -#define LCD_DCODE5_bp 5 /* Display Code bit 5 position. */ -#define LCD_DCODE6_bm (1<<6) /* Display Code bit 6 mask. */ -#define LCD_DCODE6_bp 6 /* Display Code bit 6 position. */ - -/* FUSE - Fuses and Lockbits */ -/* NVM_FUSES.FUSEBYTE0 bit masks and bit positions */ -#define NVM_FUSES_JTAGUSERID_gm 0xFF /* JTAG User ID group mask. */ -#define NVM_FUSES_JTAGUSERID_gp 0 /* JTAG User ID group position. */ -#define NVM_FUSES_JTAGUSERID0_bm (1<<0) /* JTAG User ID bit 0 mask. */ -#define NVM_FUSES_JTAGUSERID0_bp 0 /* JTAG User ID bit 0 position. */ -#define NVM_FUSES_JTAGUSERID1_bm (1<<1) /* JTAG User ID bit 1 mask. */ -#define NVM_FUSES_JTAGUSERID1_bp 1 /* JTAG User ID bit 1 position. */ -#define NVM_FUSES_JTAGUSERID2_bm (1<<2) /* JTAG User ID bit 2 mask. */ -#define NVM_FUSES_JTAGUSERID2_bp 2 /* JTAG User ID bit 2 position. */ -#define NVM_FUSES_JTAGUSERID3_bm (1<<3) /* JTAG User ID bit 3 mask. */ -#define NVM_FUSES_JTAGUSERID3_bp 3 /* JTAG User ID bit 3 position. */ -#define NVM_FUSES_JTAGUSERID4_bm (1<<4) /* JTAG User ID bit 4 mask. */ -#define NVM_FUSES_JTAGUSERID4_bp 4 /* JTAG User ID bit 4 position. */ -#define NVM_FUSES_JTAGUSERID5_bm (1<<5) /* JTAG User ID bit 5 mask. */ -#define NVM_FUSES_JTAGUSERID5_bp 5 /* JTAG User ID bit 5 position. */ -#define NVM_FUSES_JTAGUSERID6_bm (1<<6) /* JTAG User ID bit 6 mask. */ -#define NVM_FUSES_JTAGUSERID6_bp 6 /* JTAG User ID bit 6 position. */ -#define NVM_FUSES_JTAGUSERID7_bm (1<<7) /* JTAG User ID bit 7 mask. */ -#define NVM_FUSES_JTAGUSERID7_bp 7 /* JTAG User ID bit 7 position. */ - -/* NVM_FUSES.FUSEBYTE1 bit masks and bit positions */ -#define NVM_FUSES_WDWP_gm 0xF0 /* Watchdog Window Timeout Period group mask. */ -#define NVM_FUSES_WDWP_gp 4 /* Watchdog Window Timeout Period group position. */ -#define NVM_FUSES_WDWP0_bm (1<<4) /* Watchdog Window Timeout Period bit 0 mask. */ -#define NVM_FUSES_WDWP0_bp 4 /* Watchdog Window Timeout Period bit 0 position. */ -#define NVM_FUSES_WDWP1_bm (1<<5) /* Watchdog Window Timeout Period bit 1 mask. */ -#define NVM_FUSES_WDWP1_bp 5 /* Watchdog Window Timeout Period bit 1 position. */ -#define NVM_FUSES_WDWP2_bm (1<<6) /* Watchdog Window Timeout Period bit 2 mask. */ -#define NVM_FUSES_WDWP2_bp 6 /* Watchdog Window Timeout Period bit 2 position. */ -#define NVM_FUSES_WDWP3_bm (1<<7) /* Watchdog Window Timeout Period bit 3 mask. */ -#define NVM_FUSES_WDWP3_bp 7 /* Watchdog Window Timeout Period bit 3 position. */ - -#define NVM_FUSES_WDP_gm 0x0F /* Watchdog Timeout Period group mask. */ -#define NVM_FUSES_WDP_gp 0 /* Watchdog Timeout Period group position. */ -#define NVM_FUSES_WDP0_bm (1<<0) /* Watchdog Timeout Period bit 0 mask. */ -#define NVM_FUSES_WDP0_bp 0 /* Watchdog Timeout Period bit 0 position. */ -#define NVM_FUSES_WDP1_bm (1<<1) /* Watchdog Timeout Period bit 1 mask. */ -#define NVM_FUSES_WDP1_bp 1 /* Watchdog Timeout Period bit 1 position. */ -#define NVM_FUSES_WDP2_bm (1<<2) /* Watchdog Timeout Period bit 2 mask. */ -#define NVM_FUSES_WDP2_bp 2 /* Watchdog Timeout Period bit 2 position. */ -#define NVM_FUSES_WDP3_bm (1<<3) /* Watchdog Timeout Period bit 3 mask. */ -#define NVM_FUSES_WDP3_bp 3 /* Watchdog Timeout Period bit 3 position. */ - -/* NVM_FUSES.FUSEBYTE2 bit masks and bit positions */ -#define NVM_FUSES_BOOTRST_bm 0x40 /* Boot Loader Section Reset Vector bit mask. */ -#define NVM_FUSES_BOOTRST_bp 6 /* Boot Loader Section Reset Vector bit position. */ - -#define NVM_FUSES_TOSCSEL_bm 0x20 /* Timer Oscillator pin location bit mask. */ -#define NVM_FUSES_TOSCSEL_bp 5 /* Timer Oscillator pin location bit position. */ - -#define NVM_FUSES_BODPD_gm 0x03 /* BOD Operation in Power-Down Mode group mask. */ -#define NVM_FUSES_BODPD_gp 0 /* BOD Operation in Power-Down Mode group position. */ -#define NVM_FUSES_BODPD0_bm (1<<0) /* BOD Operation in Power-Down Mode bit 0 mask. */ -#define NVM_FUSES_BODPD0_bp 0 /* BOD Operation in Power-Down Mode bit 0 position. */ -#define NVM_FUSES_BODPD1_bm (1<<1) /* BOD Operation in Power-Down Mode bit 1 mask. */ -#define NVM_FUSES_BODPD1_bp 1 /* BOD Operation in Power-Down Mode bit 1 position. */ - -/* NVM_FUSES.FUSEBYTE4 bit masks and bit positions */ -#define NVM_FUSES_RSTDISBL_bm 0x10 /* External Reset Disable bit mask. */ -#define NVM_FUSES_RSTDISBL_bp 4 /* External Reset Disable bit position. */ - -#define NVM_FUSES_SUT_gm 0x0C /* Start-up Time group mask. */ -#define NVM_FUSES_SUT_gp 2 /* Start-up Time group position. */ -#define NVM_FUSES_SUT0_bm (1<<2) /* Start-up Time bit 0 mask. */ -#define NVM_FUSES_SUT0_bp 2 /* Start-up Time bit 0 position. */ -#define NVM_FUSES_SUT1_bm (1<<3) /* Start-up Time bit 1 mask. */ -#define NVM_FUSES_SUT1_bp 3 /* Start-up Time bit 1 position. */ - -#define NVM_FUSES_WDLOCK_bm 0x02 /* Watchdog Timer Lock bit mask. */ -#define NVM_FUSES_WDLOCK_bp 1 /* Watchdog Timer Lock bit position. */ - -#define NVM_FUSES_JTAGEN_bm 0x01 /* JTAG Interface Enable bit mask. */ -#define NVM_FUSES_JTAGEN_bp 0 /* JTAG Interface Enable bit position. */ - -/* NVM_FUSES.FUSEBYTE5 bit masks and bit positions */ -#define NVM_FUSES_BODACT_gm 0x30 /* BOD Operation in Active Mode group mask. */ -#define NVM_FUSES_BODACT_gp 4 /* BOD Operation in Active Mode group position. */ -#define NVM_FUSES_BODACT0_bm (1<<4) /* BOD Operation in Active Mode bit 0 mask. */ -#define NVM_FUSES_BODACT0_bp 4 /* BOD Operation in Active Mode bit 0 position. */ -#define NVM_FUSES_BODACT1_bm (1<<5) /* BOD Operation in Active Mode bit 1 mask. */ -#define NVM_FUSES_BODACT1_bp 5 /* BOD Operation in Active Mode bit 1 position. */ - -#define NVM_FUSES_EESAVE_bm 0x08 /* Preserve EEPROM Through Chip Erase bit mask. */ -#define NVM_FUSES_EESAVE_bp 3 /* Preserve EEPROM Through Chip Erase bit position. */ - -#define NVM_FUSES_BODLVL_gm 0x07 /* Brownout Detection Voltage Level group mask. */ -#define NVM_FUSES_BODLVL_gp 0 /* Brownout Detection Voltage Level group position. */ -#define NVM_FUSES_BODLVL0_bm (1<<0) /* Brownout Detection Voltage Level bit 0 mask. */ -#define NVM_FUSES_BODLVL0_bp 0 /* Brownout Detection Voltage Level bit 0 position. */ -#define NVM_FUSES_BODLVL1_bm (1<<1) /* Brownout Detection Voltage Level bit 1 mask. */ -#define NVM_FUSES_BODLVL1_bp 1 /* Brownout Detection Voltage Level bit 1 position. */ -#define NVM_FUSES_BODLVL2_bm (1<<2) /* Brownout Detection Voltage Level bit 2 mask. */ -#define NVM_FUSES_BODLVL2_bp 2 /* Brownout Detection Voltage Level bit 2 position. */ - -/* LOCKBIT - Fuses and Lockbits */ -/* NVM_LOCKBITS.LOCKBITS bit masks and bit positions */ -#define NVM_LOCKBITS_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ -#define NVM_LOCKBITS_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ -#define NVM_LOCKBITS_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ -#define NVM_LOCKBITS_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ -#define NVM_LOCKBITS_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ -#define NVM_LOCKBITS_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ - -#define NVM_LOCKBITS_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ -#define NVM_LOCKBITS_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ -#define NVM_LOCKBITS_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ -#define NVM_LOCKBITS_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ -#define NVM_LOCKBITS_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ -#define NVM_LOCKBITS_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ - -#define NVM_LOCKBITS_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ -#define NVM_LOCKBITS_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ -#define NVM_LOCKBITS_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ -#define NVM_LOCKBITS_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ -#define NVM_LOCKBITS_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ -#define NVM_LOCKBITS_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ - -#define NVM_LOCKBITS_LB_gm 0x03 /* Lock Bits group mask. */ -#define NVM_LOCKBITS_LB_gp 0 /* Lock Bits group position. */ -#define NVM_LOCKBITS_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ -#define NVM_LOCKBITS_LB0_bp 0 /* Lock Bits bit 0 position. */ -#define NVM_LOCKBITS_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ -#define NVM_LOCKBITS_LB1_bp 1 /* Lock Bits bit 1 position. */ - - - -// Generic Port Pins - -#define PIN0_bm 0x01 -#define PIN0_bp 0 -#define PIN1_bm 0x02 -#define PIN1_bp 1 -#define PIN2_bm 0x04 -#define PIN2_bp 2 -#define PIN3_bm 0x08 -#define PIN3_bp 3 -#define PIN4_bm 0x10 -#define PIN4_bp 4 -#define PIN5_bm 0x20 -#define PIN5_bp 5 -#define PIN6_bm 0x40 -#define PIN6_bp 6 -#define PIN7_bm 0x80 -#define PIN7_bp 7 - -/* ========== Interrupt Vector Definitions ========== */ -/* Vector 0 is the reset vector */ - -/* OSC interrupt vectors */ -#define OSC_OSCF_vect_num 1 -#define OSC_OSCF_vect _VECTOR(1) /* Oscillator Failure Interrupt (NMI) */ - -/* PORTC interrupt vectors */ -#define PORTC_INT0_vect_num 2 -#define PORTC_INT0_vect _VECTOR(2) /* External Interrupt 0 */ -#define PORTC_INT1_vect_num 3 -#define PORTC_INT1_vect _VECTOR(3) /* External Interrupt 1 */ - -/* PORTR interrupt vectors */ -#define PORTR_INT0_vect_num 4 -#define PORTR_INT0_vect _VECTOR(4) /* External Interrupt 0 */ -#define PORTR_INT1_vect_num 5 -#define PORTR_INT1_vect _VECTOR(5) /* External Interrupt 1 */ - -/* DMA interrupt vectors */ -#define DMA_CH0_vect_num 6 -#define DMA_CH0_vect _VECTOR(6) /* Channel 0 Interrupt */ -#define DMA_CH1_vect_num 7 -#define DMA_CH1_vect _VECTOR(7) /* Channel 1 Interrupt */ - -/* RTC interrupt vectors */ -#define RTC_OVF_vect_num 10 -#define RTC_OVF_vect _VECTOR(10) /* Overflow Interrupt */ -#define RTC_COMP_vect_num 11 -#define RTC_COMP_vect _VECTOR(11) /* Compare Interrupt */ - -/* TWIC interrupt vectors */ -#define TWIC_TWIS_vect_num 12 -#define TWIC_TWIS_vect _VECTOR(12) /* TWI Slave Interrupt */ -#define TWIC_TWIM_vect_num 13 -#define TWIC_TWIM_vect _VECTOR(13) /* TWI Master Interrupt */ - -/* TCC0 interrupt vectors */ -#define TCC0_OVF_vect_num 14 -#define TCC0_OVF_vect _VECTOR(14) /* Overflow Interrupt */ - -/* TCC2 interrupt vectors */ -#define TCC2_LUNF_vect_num 14 -#define TCC2_LUNF_vect _VECTOR(14) /* Low Byte Underflow Interrupt */ - -/* TCC0 interrupt vectors */ -#define TCC0_ERR_vect_num 15 -#define TCC0_ERR_vect _VECTOR(15) /* Error Interrupt */ - -/* TCC2 interrupt vectors */ -#define TCC2_HUNF_vect_num 15 -#define TCC2_HUNF_vect _VECTOR(15) /* High Byte Underflow Interrupt */ - -/* TCC0 interrupt vectors */ -#define TCC0_CCA_vect_num 16 -#define TCC0_CCA_vect _VECTOR(16) /* Compare or Capture A Interrupt */ - -/* TCC2 interrupt vectors */ -#define TCC2_LCMPA_vect_num 16 -#define TCC2_LCMPA_vect _VECTOR(16) /* Low Byte Compare A Interrupt */ - -/* TCC0 interrupt vectors */ -#define TCC0_CCB_vect_num 17 -#define TCC0_CCB_vect _VECTOR(17) /* Compare or Capture B Interrupt */ - -/* TCC2 interrupt vectors */ -#define TCC2_LCMPB_vect_num 17 -#define TCC2_LCMPB_vect _VECTOR(17) /* Low Byte Compare B Interrupt */ - -/* TCC0 interrupt vectors */ -#define TCC0_CCC_vect_num 18 -#define TCC0_CCC_vect _VECTOR(18) /* Compare or Capture C Interrupt */ - -/* TCC2 interrupt vectors */ -#define TCC2_LCMPC_vect_num 18 -#define TCC2_LCMPC_vect _VECTOR(18) /* Low Byte Compare C Interrupt */ - -/* TCC0 interrupt vectors */ -#define TCC0_CCD_vect_num 19 -#define TCC0_CCD_vect _VECTOR(19) /* Compare or Capture D Interrupt */ - -/* TCC2 interrupt vectors */ -#define TCC2_LCMPD_vect_num 19 -#define TCC2_LCMPD_vect _VECTOR(19) /* Low Byte Compare D Interrupt */ - -/* TCC1 interrupt vectors */ -#define TCC1_OVF_vect_num 20 -#define TCC1_OVF_vect _VECTOR(20) /* Overflow Interrupt */ -#define TCC1_ERR_vect_num 21 -#define TCC1_ERR_vect _VECTOR(21) /* Error Interrupt */ -#define TCC1_CCA_vect_num 22 -#define TCC1_CCA_vect _VECTOR(22) /* Compare or Capture A Interrupt */ -#define TCC1_CCB_vect_num 23 -#define TCC1_CCB_vect _VECTOR(23) /* Compare or Capture B Interrupt */ - -/* SPIC interrupt vectors */ -#define SPIC_INT_vect_num 24 -#define SPIC_INT_vect _VECTOR(24) /* SPI Interrupt */ - -/* USARTC0 interrupt vectors */ -#define USARTC0_RXC_vect_num 25 -#define USARTC0_RXC_vect _VECTOR(25) /* Reception Complete Interrupt */ -#define USARTC0_DRE_vect_num 26 -#define USARTC0_DRE_vect _VECTOR(26) /* Data Register Empty Interrupt */ -#define USARTC0_TXC_vect_num 27 -#define USARTC0_TXC_vect _VECTOR(27) /* Transmission Complete Interrupt */ - -/* USB interrupt vectors */ -#define USB_BUSEVENT_vect_num 31 -#define USB_BUSEVENT_vect _VECTOR(31) /* SOF, suspend, resume, reset bus event interrupts, crc, underflow, overflow and stall error interrupts */ -#define USB_TRNCOMPL_vect_num 32 -#define USB_TRNCOMPL_vect _VECTOR(32) /* Transaction complete interrupt */ - -/* LCD interrupt vectors */ -#define LCD_INT_vect_num 35 -#define LCD_INT_vect _VECTOR(35) /* LCD Interrupt */ - -/* AES interrupt vectors */ -#define AES_INT_vect_num 36 -#define AES_INT_vect _VECTOR(36) /* AES Interrupt */ - -/* NVM interrupt vectors */ -#define NVM_EE_vect_num 37 -#define NVM_EE_vect _VECTOR(37) /* EE Interrupt */ -#define NVM_SPM_vect_num 38 -#define NVM_SPM_vect _VECTOR(38) /* SPM Interrupt */ - -/* PORTB interrupt vectors */ -#define PORTB_INT0_vect_num 39 -#define PORTB_INT0_vect _VECTOR(39) /* External Interrupt 0 */ -#define PORTB_INT1_vect_num 40 -#define PORTB_INT1_vect _VECTOR(40) /* External Interrupt 1 */ - -/* ACB interrupt vectors */ -#define ACB_AC0_vect_num 41 -#define ACB_AC0_vect _VECTOR(41) /* AC0 Interrupt */ -#define ACB_AC1_vect_num 42 -#define ACB_AC1_vect _VECTOR(42) /* AC1 Interrupt */ -#define ACB_ACW_vect_num 43 -#define ACB_ACW_vect _VECTOR(43) /* ACW Window Mode Interrupt */ - -/* ADCB interrupt vectors */ -#define ADCB_CH0_vect_num 44 -#define ADCB_CH0_vect _VECTOR(44) /* Interrupt 0 */ - -/* PORTD interrupt vectors */ -#define PORTD_INT0_vect_num 48 -#define PORTD_INT0_vect _VECTOR(48) /* External Interrupt 0 */ -#define PORTD_INT1_vect_num 49 -#define PORTD_INT1_vect _VECTOR(49) /* External Interrupt 1 */ - -/* PORTG interrupt vectors */ -#define PORTG_INT0_vect_num 50 -#define PORTG_INT0_vect _VECTOR(50) /* External Interrupt 0 */ -#define PORTG_INT1_vect_num 51 -#define PORTG_INT1_vect _VECTOR(51) /* External Interrupt 1 */ - -/* PORTM interrupt vectors */ -#define PORTM_INT0_vect_num 52 -#define PORTM_INT0_vect _VECTOR(52) /* External Interrupt 0 */ -#define PORTM_INT1_vect_num 53 -#define PORTM_INT1_vect _VECTOR(53) /* External Interrupt 1 */ - -/* PORTE interrupt vectors */ -#define PORTE_INT0_vect_num 54 -#define PORTE_INT0_vect _VECTOR(54) /* External Interrupt 0 */ -#define PORTE_INT1_vect_num 55 -#define PORTE_INT1_vect _VECTOR(55) /* External Interrupt 1 */ - -/* TCE0 interrupt vectors */ -#define TCE0_OVF_vect_num 58 -#define TCE0_OVF_vect _VECTOR(58) /* Overflow Interrupt */ - -/* TCE2 interrupt vectors */ -#define TCE2_LUNF_vect_num 58 -#define TCE2_LUNF_vect _VECTOR(58) /* Low Byte Underflow Interrupt */ - -/* TCE0 interrupt vectors */ -#define TCE0_ERR_vect_num 59 -#define TCE0_ERR_vect _VECTOR(59) /* Error Interrupt */ - -/* TCE2 interrupt vectors */ -#define TCE2_HUNF_vect_num 59 -#define TCE2_HUNF_vect _VECTOR(59) /* High Byte Underflow Interrupt */ - -/* TCE0 interrupt vectors */ -#define TCE0_CCA_vect_num 60 -#define TCE0_CCA_vect _VECTOR(60) /* Compare or Capture A Interrupt */ - -/* TCE2 interrupt vectors */ -#define TCE2_LCMPA_vect_num 60 -#define TCE2_LCMPA_vect _VECTOR(60) /* Low Byte Compare A Interrupt */ - -/* TCE0 interrupt vectors */ -#define TCE0_CCB_vect_num 61 -#define TCE0_CCB_vect _VECTOR(61) /* Compare or Capture B Interrupt */ - -/* TCE2 interrupt vectors */ -#define TCE2_LCMPB_vect_num 61 -#define TCE2_LCMPB_vect _VECTOR(61) /* Low Byte Compare B Interrupt */ - -/* TCE0 interrupt vectors */ -#define TCE0_CCC_vect_num 62 -#define TCE0_CCC_vect _VECTOR(62) /* Compare or Capture C Interrupt */ - -/* TCE2 interrupt vectors */ -#define TCE2_LCMPC_vect_num 62 -#define TCE2_LCMPC_vect _VECTOR(62) /* Low Byte Compare C Interrupt */ - -/* TCE0 interrupt vectors */ -#define TCE0_CCD_vect_num 63 -#define TCE0_CCD_vect _VECTOR(63) /* Compare or Capture D Interrupt */ - -/* TCE2 interrupt vectors */ -#define TCE2_LCMPD_vect_num 63 -#define TCE2_LCMPD_vect _VECTOR(63) /* Low Byte Compare D Interrupt */ - -/* USARTE0 interrupt vectors */ -#define USARTE0_RXC_vect_num 69 -#define USARTE0_RXC_vect _VECTOR(69) /* Reception Complete Interrupt */ -#define USARTE0_DRE_vect_num 70 -#define USARTE0_DRE_vect _VECTOR(70) /* Data Register Empty Interrupt */ -#define USARTE0_TXC_vect_num 71 -#define USARTE0_TXC_vect _VECTOR(71) /* Transmission Complete Interrupt */ - -/* PORTA interrupt vectors */ -#define PORTA_INT0_vect_num 75 -#define PORTA_INT0_vect _VECTOR(75) /* External Interrupt 0 */ -#define PORTA_INT1_vect_num 76 -#define PORTA_INT1_vect _VECTOR(76) /* External Interrupt 1 */ - -/* ACA interrupt vectors */ -#define ACA_AC0_vect_num 77 -#define ACA_AC0_vect _VECTOR(77) /* AC0 Interrupt */ -#define ACA_AC1_vect_num 78 -#define ACA_AC1_vect _VECTOR(78) /* AC1 Interrupt */ -#define ACA_ACW_vect_num 79 -#define ACA_ACW_vect _VECTOR(79) /* ACW Window Mode Interrupt */ - -/* ADCA interrupt vectors */ -#define ADCA_CH0_vect_num 80 -#define ADCA_CH0_vect _VECTOR(80) /* Interrupt 0 */ - -#define _VECTOR_SIZE 4 /* Size of individual vector. */ -#define _VECTORS_SIZE (81 * _VECTOR_SIZE) - - -/* ========== Constants ========== */ - -#define PROGMEM_START (0x0000) -#define PROGMEM_SIZE (139264) -#define PROGMEM_END (PROGMEM_START + PROGMEM_SIZE - 1) - -#define APP_SECTION_START (0x0000) -#define APP_SECTION_SIZE (131072) -#define APP_SECTION_PAGE_SIZE (256) -#define APP_SECTION_END (APP_SECTION_START + APP_SECTION_SIZE - 1) - -#define APPTABLE_SECTION_START (0x1E000) -#define APPTABLE_SECTION_SIZE (8192) -#define APPTABLE_SECTION_PAGE_SIZE (256) -#define APPTABLE_SECTION_END (APPTABLE_SECTION_START + APPTABLE_SECTION_SIZE - 1) - -#define BOOT_SECTION_START (0x20000) -#define BOOT_SECTION_SIZE (8192) -#define BOOT_SECTION_PAGE_SIZE (256) -#define BOOT_SECTION_END (BOOT_SECTION_START + BOOT_SECTION_SIZE - 1) - -#define DATAMEM_START (0x0000) -#define DATAMEM_SIZE (16384) -#define DATAMEM_END (DATAMEM_START + DATAMEM_SIZE - 1) - -#define IO_START (0x0000) -#define IO_SIZE (4096) -#define IO_PAGE_SIZE (0) -#define IO_END (IO_START + IO_SIZE - 1) - -#define MAPPED_EEPROM_START (0x1000) -#define MAPPED_EEPROM_SIZE (2048) -#define MAPPED_EEPROM_PAGE_SIZE (0) -#define MAPPED_EEPROM_END (MAPPED_EEPROM_START + MAPPED_EEPROM_SIZE - 1) - -#define INTERNAL_SRAM_START (0x2000) -#define INTERNAL_SRAM_SIZE (8192) -#define INTERNAL_SRAM_PAGE_SIZE (0) -#define INTERNAL_SRAM_END (INTERNAL_SRAM_START + INTERNAL_SRAM_SIZE - 1) - -#define EEPROM_START (0x0000) -#define EEPROM_SIZE (2048) -#define EEPROM_PAGE_SIZE (32) -#define EEPROM_END (EEPROM_START + EEPROM_SIZE - 1) - -#define SIGNATURES_START (0x0000) -#define SIGNATURES_SIZE (3) -#define SIGNATURES_PAGE_SIZE (0) -#define SIGNATURES_END (SIGNATURES_START + SIGNATURES_SIZE - 1) - -#define FUSES_START (0x0000) -#define FUSES_SIZE (6) -#define FUSES_PAGE_SIZE (0) -#define FUSES_END (FUSES_START + FUSES_SIZE - 1) - -#define LOCKBITS_START (0x0000) -#define LOCKBITS_SIZE (1) -#define LOCKBITS_PAGE_SIZE (0) -#define LOCKBITS_END (LOCKBITS_START + LOCKBITS_SIZE - 1) - -#define USER_SIGNATURES_START (0x0000) -#define USER_SIGNATURES_SIZE (256) -#define USER_SIGNATURES_PAGE_SIZE (256) -#define USER_SIGNATURES_END (USER_SIGNATURES_START + USER_SIGNATURES_SIZE - 1) - -#define PROD_SIGNATURES_START (0x0000) -#define PROD_SIGNATURES_SIZE (52) -#define PROD_SIGNATURES_PAGE_SIZE (256) -#define PROD_SIGNATURES_END (PROD_SIGNATURES_START + PROD_SIGNATURES_SIZE - 1) - -#define FLASHSTART PROGMEM_START -#define FLASHEND PROGMEM_END -#define SPM_PAGESIZE 256 -#define RAMSTART INTERNAL_SRAM_START -#define RAMSIZE INTERNAL_SRAM_SIZE -#define RAMEND INTERNAL_SRAM_END -#define E2END EEPROM_END -#define E2PAGESIZE EEPROM_PAGE_SIZE - - -/* ========== Fuses ========== */ -#define FUSE_MEMORY_SIZE 6 - -/* Fuse Byte 0 */ -#define FUSE_JTAGUSERID0 (unsigned char)~_BV(0) /* JTAG User ID Bit 0 */ -#define FUSE_JTAGUSERID1 (unsigned char)~_BV(1) /* JTAG User ID Bit 1 */ -#define FUSE_JTAGUSERID2 (unsigned char)~_BV(2) /* JTAG User ID Bit 2 */ -#define FUSE_JTAGUSERID3 (unsigned char)~_BV(3) /* JTAG User ID Bit 3 */ -#define FUSE_JTAGUSERID4 (unsigned char)~_BV(4) /* JTAG User ID Bit 4 */ -#define FUSE_JTAGUSERID5 (unsigned char)~_BV(5) /* JTAG User ID Bit 5 */ -#define FUSE_JTAGUSERID6 (unsigned char)~_BV(6) /* JTAG User ID Bit 6 */ -#define FUSE_JTAGUSERID7 (unsigned char)~_BV(7) /* JTAG User ID Bit 7 */ -#define FUSE0_DEFAULT (0xFF) - -/* Fuse Byte 1 */ -#define FUSE_WDP0 (unsigned char)~_BV(0) /* Watchdog Timeout Period Bit 0 */ -#define FUSE_WDP1 (unsigned char)~_BV(1) /* Watchdog Timeout Period Bit 1 */ -#define FUSE_WDP2 (unsigned char)~_BV(2) /* Watchdog Timeout Period Bit 2 */ -#define FUSE_WDP3 (unsigned char)~_BV(3) /* Watchdog Timeout Period Bit 3 */ -#define FUSE_WDWP0 (unsigned char)~_BV(4) /* Watchdog Window Timeout Period Bit 0 */ -#define FUSE_WDWP1 (unsigned char)~_BV(5) /* Watchdog Window Timeout Period Bit 1 */ -#define FUSE_WDWP2 (unsigned char)~_BV(6) /* Watchdog Window Timeout Period Bit 2 */ -#define FUSE_WDWP3 (unsigned char)~_BV(7) /* Watchdog Window Timeout Period Bit 3 */ -#define FUSE1_DEFAULT (0xFF) - -/* Fuse Byte 2 */ -#define FUSE_BODPD0 (unsigned char)~_BV(0) /* BOD Operation in Power-Down Mode Bit 0 */ -#define FUSE_BODPD1 (unsigned char)~_BV(1) /* BOD Operation in Power-Down Mode Bit 1 */ -#define FUSE_TOSCSEL (unsigned char)~_BV(5) /* Timer Oscillator pin location */ -#define FUSE_BOOTRST (unsigned char)~_BV(6) /* Boot Loader Section Reset Vector */ -#define FUSE2_DEFAULT (0xFF) - -/* Fuse Byte 3 Reserved */ - -/* Fuse Byte 4 */ -#define FUSE_JTAGEN (unsigned char)~_BV(0) /* JTAG Interface Enable */ -#define FUSE_WDLOCK (unsigned char)~_BV(1) /* Watchdog Timer Lock */ -#define FUSE_SUT0 (unsigned char)~_BV(2) /* Start-up Time Bit 0 */ -#define FUSE_SUT1 (unsigned char)~_BV(3) /* Start-up Time Bit 1 */ -#define FUSE_RSTDISBL (unsigned char)~_BV(4) /* External Reset Disable */ -#define FUSE4_DEFAULT (0xFF) - -/* Fuse Byte 5 */ -#define FUSE_BODLVL0 (unsigned char)~_BV(0) /* Brownout Detection Voltage Level Bit 0 */ -#define FUSE_BODLVL1 (unsigned char)~_BV(1) /* Brownout Detection Voltage Level Bit 1 */ -#define FUSE_BODLVL2 (unsigned char)~_BV(2) /* Brownout Detection Voltage Level Bit 2 */ -#define FUSE_EESAVE (unsigned char)~_BV(3) /* Preserve EEPROM Through Chip Erase */ -#define FUSE_BODACT0 (unsigned char)~_BV(4) /* BOD Operation in Active Mode Bit 0 */ -#define FUSE_BODACT1 (unsigned char)~_BV(5) /* BOD Operation in Active Mode Bit 1 */ -#define FUSE5_DEFAULT (0xFF) - -/* ========== Lock Bits ========== */ -#define __LOCK_BITS_EXIST -#define __BOOT_LOCK_APPLICATION_TABLE_BITS_EXIST -#define __BOOT_LOCK_APPLICATION_BITS_EXIST -#define __BOOT_LOCK_BOOT_BITS_EXIST - -/* ========== Signature ========== */ -#define SIGNATURE_0 0x1E -#define SIGNATURE_1 0x97 -#define SIGNATURE_2 0x4D - -/* ========== Power Reduction Condition Definitions ========== */ - -/* PR.PRGEN */ -#define __AVR_HAVE_PRGEN (PR_LCD_bm|PR_USB_bm|PR_AES_bm|PR_RTC_bm|PR_EVSYS_bm|PR_DMA_bm) -#define __AVR_HAVE_PRGEN_LCD -#define __AVR_HAVE_PRGEN_USB -#define __AVR_HAVE_PRGEN_AES -#define __AVR_HAVE_PRGEN_RTC -#define __AVR_HAVE_PRGEN_EVSYS -#define __AVR_HAVE_PRGEN_DMA - -/* PR.PRPA */ -#define __AVR_HAVE_PRPA (PR_ADC_bm|PR_AC_bm) -#define __AVR_HAVE_PRPA_ADC -#define __AVR_HAVE_PRPA_AC - -/* PR.PRPB */ -#define __AVR_HAVE_PRPB (PR_ADC_bm|PR_AC_bm) -#define __AVR_HAVE_PRPB_ADC -#define __AVR_HAVE_PRPB_AC - -/* PR.PRPC */ -#define __AVR_HAVE_PRPC (PR_TWI_bm|PR_USART0_bm|PR_SPI_bm|PR_HIRES_bm|PR_TC1_bm|PR_TC0_bm) -#define __AVR_HAVE_PRPC_TWI -#define __AVR_HAVE_PRPC_USART0 -#define __AVR_HAVE_PRPC_SPI -#define __AVR_HAVE_PRPC_HIRES -#define __AVR_HAVE_PRPC_TC1 -#define __AVR_HAVE_PRPC_TC0 - -/* PR.PRPE */ -#define __AVR_HAVE_PRPE (PR_USART0_bm|PR_TC0_bm) -#define __AVR_HAVE_PRPE_USART0 -#define __AVR_HAVE_PRPE_TC0 - - -#endif /* #ifdef _AVR_ATXMEGA128B1_H_INCLUDED */ - diff --git a/arduino/hardware/tools/avr/avr/include/avr/iox128b3.h b/arduino/hardware/tools/avr/avr/include/avr/iox128b3.h deleted file mode 100644 index 45f1d14..0000000 --- a/arduino/hardware/tools/avr/avr/include/avr/iox128b3.h +++ /dev/null @@ -1,6288 +0,0 @@ -/***************************************************************************** - * - * Copyright (C) 2015 Atmel Corporation - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * - * * Neither the name of the copyright holders nor the names of - * contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - ****************************************************************************/ - - -#ifndef _AVR_IO_H_ -# error "Include instead of this file." -#endif - -#ifndef _AVR_IOXXX_H_ -# define _AVR_IOXXX_H_ "iox128b3.h" -#else -# error "Attempt to include more than one file." -#endif - -#ifndef _AVR_ATXMEGA128B3_H_INCLUDED -#define _AVR_ATXMEGA128B3_H_INCLUDED - -/* Ungrouped common registers */ -#define GPIOR0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ -#define GPIOR1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ -#define GPIOR2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ -#define GPIOR3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ - -/* Deprecated */ -#define GPIO0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ -#define GPIO1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ -#define GPIO2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ -#define GPIO3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ - -#define CCP _SFR_MEM8(0x0034) /* Configuration Change Protection */ -#define RAMPD _SFR_MEM8(0x0038) /* Ramp D */ -#define RAMPX _SFR_MEM8(0x0039) /* Ramp X */ -#define RAMPY _SFR_MEM8(0x003A) /* Ramp Y */ -#define RAMPZ _SFR_MEM8(0x003B) /* Ramp Z */ -#define EIND _SFR_MEM8(0x003C) /* Extended Indirect Jump */ -#define SPL _SFR_MEM8(0x003D) /* Stack Pointer Low */ -#define SPH _SFR_MEM8(0x003E) /* Stack Pointer High */ -#define SREG _SFR_MEM8(0x003F) /* Status Register */ - -/* C Language Only */ -#if !defined (__ASSEMBLER__) - -#include - -typedef volatile uint8_t register8_t; -typedef volatile uint16_t register16_t; -typedef volatile uint32_t register32_t; - - -#ifdef _WORDREGISTER -#undef _WORDREGISTER -#endif -#define _WORDREGISTER(regname) \ - __extension__ union \ - { \ - register16_t regname; \ - struct \ - { \ - register8_t regname ## L; \ - register8_t regname ## H; \ - }; \ - } - -#ifdef _DWORDREGISTER -#undef _DWORDREGISTER -#endif -#define _DWORDREGISTER(regname) \ - __extension__ union \ - { \ - register32_t regname; \ - struct \ - { \ - register8_t regname ## 0; \ - register8_t regname ## 1; \ - register8_t regname ## 2; \ - register8_t regname ## 3; \ - }; \ - } - - -/* -========================================================================== -IO Module Structures -========================================================================== -*/ - - -/* --------------------------------------------------------------------------- -VPORT - Virtual Ports --------------------------------------------------------------------------- -*/ - -/* Virtual Port */ -typedef struct VPORT_struct -{ - register8_t DIR; /* I/O Port Data Direction */ - register8_t OUT; /* I/O Port Output */ - register8_t IN; /* I/O Port Input */ - register8_t INTFLAGS; /* Interrupt Flag Register */ -} VPORT_t; - - -/* --------------------------------------------------------------------------- -XOCD - On-Chip Debug System --------------------------------------------------------------------------- -*/ - -/* On-Chip Debug System */ -typedef struct OCD_struct -{ - register8_t OCDR0; /* OCD Register 0 */ - register8_t OCDR1; /* OCD Register 1 */ -} OCD_t; - - -/* --------------------------------------------------------------------------- -CPU - CPU --------------------------------------------------------------------------- -*/ - -/* CCP signatures */ -typedef enum CCP_enum -{ - CCP_SPM_gc = (0x9D<<0), /* SPM Instruction Protection */ - CCP_IOREG_gc = (0xD8<<0), /* IO Register Protection */ -} CCP_t; - - -/* --------------------------------------------------------------------------- -CLK - Clock System --------------------------------------------------------------------------- -*/ - -/* Clock System */ -typedef struct CLK_struct -{ - register8_t CTRL; /* Control Register */ - register8_t PSCTRL; /* Prescaler Control Register */ - register8_t LOCK; /* Lock register */ - register8_t RTCCTRL; /* RTC Control Register */ - register8_t USBCTRL; /* USB Control Register */ -} CLK_t; - -/* System Clock Selection */ -typedef enum CLK_SCLKSEL_enum -{ - CLK_SCLKSEL_RC2M_gc = (0x00<<0), /* Internal 2 MHz RC Oscillator */ - CLK_SCLKSEL_RC32M_gc = (0x01<<0), /* Internal 32 MHz RC Oscillator */ - CLK_SCLKSEL_RC32K_gc = (0x02<<0), /* Internal 32.768 kHz RC Oscillator */ - CLK_SCLKSEL_XOSC_gc = (0x03<<0), /* External Crystal Oscillator or Clock */ - CLK_SCLKSEL_PLL_gc = (0x04<<0), /* Phase Locked Loop */ -} CLK_SCLKSEL_t; - -/* Prescaler A Division Factor */ -typedef enum CLK_PSADIV_enum -{ - CLK_PSADIV_1_gc = (0x00<<2), /* Divide by 1 */ - CLK_PSADIV_2_gc = (0x01<<2), /* Divide by 2 */ - CLK_PSADIV_4_gc = (0x03<<2), /* Divide by 4 */ - CLK_PSADIV_8_gc = (0x05<<2), /* Divide by 8 */ - CLK_PSADIV_16_gc = (0x07<<2), /* Divide by 16 */ - CLK_PSADIV_32_gc = (0x09<<2), /* Divide by 32 */ - CLK_PSADIV_64_gc = (0x0B<<2), /* Divide by 64 */ - CLK_PSADIV_128_gc = (0x0D<<2), /* Divide by 128 */ - CLK_PSADIV_256_gc = (0x0F<<2), /* Divide by 256 */ - CLK_PSADIV_512_gc = (0x11<<2), /* Divide by 512 */ -} CLK_PSADIV_t; - -/* Prescaler B and C Division Factor */ -typedef enum CLK_PSBCDIV_enum -{ - CLK_PSBCDIV_1_1_gc = (0x00<<0), /* Divide B by 1 and C by 1 */ - CLK_PSBCDIV_1_2_gc = (0x01<<0), /* Divide B by 1 and C by 2 */ - CLK_PSBCDIV_4_1_gc = (0x02<<0), /* Divide B by 4 and C by 1 */ - CLK_PSBCDIV_2_2_gc = (0x03<<0), /* Divide B by 2 and C by 2 */ -} CLK_PSBCDIV_t; - -/* RTC Clock Source */ -typedef enum CLK_RTCSRC_enum -{ - CLK_RTCSRC_ULP_gc = (0x00<<1), /* 1.024 kHz from internal 32kHz ULP */ - CLK_RTCSRC_TOSC_gc = (0x01<<1), /* 1.024 kHz from 32.768 kHz crystal oscillator on TOSC */ - CLK_RTCSRC_RCOSC_gc = (0x02<<1), /* 1.024 kHz from internal 32.768 kHz RC oscillator */ - CLK_RTCSRC_TOSC32_gc = (0x05<<1), /* 32.768 kHz from 32.768 kHz crystal oscillator on TOSC */ - CLK_RTCSRC_RCOSC32_gc = (0x06<<1), /* 32.768 kHz from internal 32.768 kHz RC oscillator */ - CLK_RTCSRC_EXTCLK_gc = (0x07<<1), /* External Clock from TOSC1 */ -} CLK_RTCSRC_t; - -/* USB Prescaler Division Factor */ -typedef enum CLK_USBPSDIV_enum -{ - CLK_USBPSDIV_1_gc = (0x00<<3), /* Divide by 1 */ - CLK_USBPSDIV_2_gc = (0x01<<3), /* Divide by 2 */ - CLK_USBPSDIV_4_gc = (0x02<<3), /* Divide by 4 */ - CLK_USBPSDIV_8_gc = (0x03<<3), /* Divide by 8 */ - CLK_USBPSDIV_16_gc = (0x04<<3), /* Divide by 16 */ - CLK_USBPSDIV_32_gc = (0x05<<3), /* Divide by 32 */ -} CLK_USBPSDIV_t; - -/* USB Clock Source */ -typedef enum CLK_USBSRC_enum -{ - CLK_USBSRC_PLL_gc = (0x00<<1), /* PLL */ - CLK_USBSRC_RC32M_gc = (0x01<<1), /* Internal 32 MHz RC Oscillator */ -} CLK_USBSRC_t; - - -/* --------------------------------------------------------------------------- -SLEEP - Sleep Controller --------------------------------------------------------------------------- -*/ - -/* Sleep Controller */ -typedef struct SLEEP_struct -{ - register8_t CTRL; /* Control Register */ -} SLEEP_t; - -/* Sleep Mode */ -typedef enum SLEEP_SMODE_enum -{ - SLEEP_SMODE_IDLE_gc = (0x00<<1), /* Idle mode */ - SLEEP_SMODE_PDOWN_gc = (0x02<<1), /* Power-down Mode */ - SLEEP_SMODE_PSAVE_gc = (0x03<<1), /* Power-save Mode */ - SLEEP_SMODE_STDBY_gc = (0x06<<1), /* Standby Mode */ - SLEEP_SMODE_ESTDBY_gc = (0x07<<1), /* Extended Standby Mode */ -} SLEEP_SMODE_t; - - - -#define SLEEP_MODE_IDLE (0x00<<1) -#define SLEEP_MODE_PWR_DOWN (0x02<<1) -#define SLEEP_MODE_PWR_SAVE (0x03<<1) -#define SLEEP_MODE_STANDBY (0x06<<1) -#define SLEEP_MODE_EXT_STANDBY (0x07<<1) -/* --------------------------------------------------------------------------- -OSC - Oscillator --------------------------------------------------------------------------- -*/ - -/* Oscillator */ -typedef struct OSC_struct -{ - register8_t CTRL; /* Control Register */ - register8_t STATUS; /* Status Register */ - register8_t XOSCCTRL; /* External Oscillator Control Register */ - register8_t XOSCFAIL; /* Oscillator Failure Detection Register */ - register8_t RC32KCAL; /* 32.768 kHz Internal Oscillator Calibration Register */ - register8_t PLLCTRL; /* PLL Control Register */ - register8_t DFLLCTRL; /* DFLL Control Register */ -} OSC_t; - -/* Oscillator Frequency Range */ -typedef enum OSC_FRQRANGE_enum -{ - OSC_FRQRANGE_04TO2_gc = (0x00<<6), /* 0.4 - 2 MHz */ - OSC_FRQRANGE_2TO9_gc = (0x01<<6), /* 2 - 9 MHz */ - OSC_FRQRANGE_9TO12_gc = (0x02<<6), /* 9 - 12 MHz */ - OSC_FRQRANGE_12TO16_gc = (0x03<<6), /* 12 - 16 MHz */ -} OSC_FRQRANGE_t; - -/* External Oscillator Selection and Startup Time */ -typedef enum OSC_XOSCSEL_enum -{ - OSC_XOSCSEL_EXTCLK_gc = (0x00<<0), /* External Clock on port R1 - 6 CLK */ - OSC_XOSCSEL_EXTCLK_C0_gc = (0x01<<0), /* External Clock on port C0 - 6 CLK */ - OSC_XOSCSEL_EXTCLK_C1_gc = (0x05<<0), /* External Clock on port C1 - 6 CLK */ - OSC_XOSCSEL_EXTCLK_C2_gc = (0x09<<0), /* External Clock on port C2 - 6 CLK */ - OSC_XOSCSEL_EXTCLK_C3_gc = (0x0D<<0), /* External Clock on port C3 - 6 CLK */ - OSC_XOSCSEL_EXTCLK_C4_gc = (0x11<<0), /* External Clock on port C4 - 6 CLK */ - OSC_XOSCSEL_EXTCLK_C5_gc = (0x15<<0), /* External Clock on port C5 - 6 CLK */ - OSC_XOSCSEL_EXTCLK_C6_gc = (0x19<<0), /* External Clock on port C6 - 6 CLK */ - OSC_XOSCSEL_EXTCLK_C7_gc = (0x1D<<0), /* External Clock on port C7 - 6 CLK */ - OSC_XOSCSEL_32KHz_gc = (0x02<<0), /* 32kHz TOSC - 32K CLK */ - OSC_XOSCSEL_XTAL_256CLK_gc = (0x03<<0), /* 0.4-16MHz XTAL - 256 CLK */ - OSC_XOSCSEL_XTAL_1KCLK_gc = (0x07<<0), /* 0.4-16MHz XTAL - 1K CLK */ - OSC_XOSCSEL_XTAL_16KCLK_gc = (0x0B<<0), /* 0.4-16MHz XTAL - 16K CLK */ -} OSC_XOSCSEL_t; - -/* PLL Clock Source */ -typedef enum OSC_PLLSRC_enum -{ - OSC_PLLSRC_RC2M_gc = (0x00<<6), /* Internal 2 MHz RC Oscillator */ - OSC_PLLSRC_RC32M_gc = (0x02<<6), /* Internal 32 MHz RC Oscillator */ - OSC_PLLSRC_XOSC_gc = (0x03<<6), /* External Oscillator */ -} OSC_PLLSRC_t; - -/* 2 MHz DFLL Calibration Reference */ -typedef enum OSC_RC2MCREF_enum -{ - OSC_RC2MCREF_RC32K_gc = (0x00<<0), /* Internal 32.768 kHz RC Oscillator */ - OSC_RC2MCREF_XOSC32K_gc = (0x01<<0), /* External 32.768 kHz Crystal Oscillator */ -} OSC_RC2MCREF_t; - -/* 32 MHz DFLL Calibration Reference */ -typedef enum OSC_RC32MCREF_enum -{ - OSC_RC32MCREF_RC32K_gc = (0x00<<1), /* Internal 32.768 kHz RC Oscillator */ - OSC_RC32MCREF_XOSC32K_gc = (0x01<<1), /* External 32.768 kHz Crystal Oscillator */ - OSC_RC32MCREF_USBSOF_gc = (0x02<<1), /* USB Start of Frame */ -} OSC_RC32MCREF_t; - - -/* --------------------------------------------------------------------------- -DFLL - DFLL --------------------------------------------------------------------------- -*/ - -/* DFLL */ -typedef struct DFLL_struct -{ - register8_t CTRL; /* Control Register */ - register8_t reserved_0x01; - register8_t CALA; /* Calibration Register A */ - register8_t CALB; /* Calibration Register B */ - register8_t COMP0; /* Oscillator Compare Register 0 */ - register8_t COMP1; /* Oscillator Compare Register 1 */ - register8_t COMP2; /* Oscillator Compare Register 2 */ - register8_t reserved_0x07; -} DFLL_t; - - -/* --------------------------------------------------------------------------- -PR - Power Reduction --------------------------------------------------------------------------- -*/ - -/* Power Reduction */ -typedef struct PR_struct -{ - register8_t PRGEN; /* General Power Reduction */ - register8_t PRPA; /* Power Reduction Port A */ - register8_t PRPB; /* Power Reduction Port B */ - register8_t PRPC; /* Power Reduction Port C */ - register8_t reserved_0x04; - register8_t PRPE; /* Power Reduction Port E */ -} PR_t; - - -/* --------------------------------------------------------------------------- -RST - Reset --------------------------------------------------------------------------- -*/ - -/* Reset */ -typedef struct RST_struct -{ - register8_t STATUS; /* Status Register */ - register8_t CTRL; /* Control Register */ -} RST_t; - - -/* --------------------------------------------------------------------------- -WDT - Watch-Dog Timer --------------------------------------------------------------------------- -*/ - -/* Watch-Dog Timer */ -typedef struct WDT_struct -{ - register8_t CTRL; /* Control */ - register8_t WINCTRL; /* Windowed Mode Control */ - register8_t STATUS; /* Status */ -} WDT_t; - -/* Period setting */ -typedef enum WDT_PER_enum -{ - WDT_PER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ - WDT_PER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ - WDT_PER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ - WDT_PER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ - WDT_PER_128CLK_gc = (0x04<<2), /* 128 cycles (0.128s @ 3.3V) */ - WDT_PER_256CLK_gc = (0x05<<2), /* 256 cycles (0.256s @ 3.3V) */ - WDT_PER_512CLK_gc = (0x06<<2), /* 512 cycles (0.512s @ 3.3V) */ - WDT_PER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ - WDT_PER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ - WDT_PER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ - WDT_PER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ -} WDT_PER_t; - -/* Closed window period */ -typedef enum WDT_WPER_enum -{ - WDT_WPER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ - WDT_WPER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ - WDT_WPER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ - WDT_WPER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ - WDT_WPER_128CLK_gc = (0x04<<2), /* 128 cycles (0.128s @ 3.3V) */ - WDT_WPER_256CLK_gc = (0x05<<2), /* 256 cycles (0.256s @ 3.3V) */ - WDT_WPER_512CLK_gc = (0x06<<2), /* 512 cycles (0.512s @ 3.3V) */ - WDT_WPER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ - WDT_WPER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ - WDT_WPER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ - WDT_WPER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ -} WDT_WPER_t; - - -/* --------------------------------------------------------------------------- -MCU - MCU Control --------------------------------------------------------------------------- -*/ - -/* MCU Control */ -typedef struct MCU_struct -{ - register8_t DEVID0; /* Device ID byte 0 */ - register8_t DEVID1; /* Device ID byte 1 */ - register8_t DEVID2; /* Device ID byte 2 */ - register8_t REVID; /* Revision ID */ - register8_t JTAGUID; /* JTAG User ID */ - register8_t reserved_0x05; - register8_t MCUCR; /* MCU Control */ - register8_t ANAINIT; /* Analog Startup Delay */ - register8_t EVSYSLOCK; /* Event System Lock */ - register8_t AWEXLOCK; /* AWEX Lock */ - register8_t reserved_0x0A; - register8_t reserved_0x0B; -} MCU_t; - - -/* --------------------------------------------------------------------------- -PMIC - Programmable Multi-level Interrupt Controller --------------------------------------------------------------------------- -*/ - -/* Programmable Multi-level Interrupt Controller */ -typedef struct PMIC_struct -{ - register8_t STATUS; /* Status Register */ - register8_t INTPRI; /* Interrupt Priority */ - register8_t CTRL; /* Control Register */ - register8_t reserved_0x03; - register8_t reserved_0x04; - register8_t reserved_0x05; - register8_t reserved_0x06; - register8_t reserved_0x07; - register8_t reserved_0x08; - register8_t reserved_0x09; - register8_t reserved_0x0A; - register8_t reserved_0x0B; - register8_t reserved_0x0C; - register8_t reserved_0x0D; - register8_t reserved_0x0E; - register8_t reserved_0x0F; -} PMIC_t; - - -/* --------------------------------------------------------------------------- -PORTCFG - Port Configuration --------------------------------------------------------------------------- -*/ - -/* I/O port Configuration */ -typedef struct PORTCFG_struct -{ - register8_t MPCMASK; /* Multi-pin Configuration Mask */ - register8_t reserved_0x01; - register8_t VPCTRLA; /* Virtual Port Control Register A */ - register8_t VPCTRLB; /* Virtual Port Control Register B */ - register8_t CLKEVOUT; /* Clock and Event Out Register */ - register8_t reserved_0x05; - register8_t EVOUTSEL; /* Event Output Select */ -} PORTCFG_t; - -/* Virtual Port Mapping */ -typedef enum PORTCFG_VP02MAP_enum -{ - PORTCFG_VP02MAP_PORTA_gc = (0x00<<0), /* Mapped To PORTA */ - PORTCFG_VP02MAP_PORTB_gc = (0x01<<0), /* Mapped To PORTB */ - PORTCFG_VP02MAP_PORTC_gc = (0x02<<0), /* Mapped To PORTC */ - PORTCFG_VP02MAP_PORTD_gc = (0x03<<0), /* Mapped To PORTD */ - PORTCFG_VP02MAP_PORTE_gc = (0x04<<0), /* Mapped To PORTE */ - PORTCFG_VP02MAP_PORTG_gc = (0x06<<0), /* Mapped To PORTG */ - PORTCFG_VP02MAP_PORTM_gc = (0x0B<<0), /* Mapped To PORTM */ - PORTCFG_VP02MAP_PORTR_gc = (0x0F<<0), /* Mapped To PORTR */ -} PORTCFG_VP02MAP_t; - -/* Virtual Port Mapping */ -typedef enum PORTCFG_VP13MAP_enum -{ - PORTCFG_VP13MAP_PORTA_gc = (0x00<<4), /* Mapped To PORTA */ - PORTCFG_VP13MAP_PORTB_gc = (0x01<<4), /* Mapped To PORTB */ - PORTCFG_VP13MAP_PORTC_gc = (0x02<<4), /* Mapped To PORTC */ - PORTCFG_VP13MAP_PORTD_gc = (0x03<<4), /* Mapped To PORTD */ - PORTCFG_VP13MAP_PORTE_gc = (0x04<<4), /* Mapped To PORTE */ - PORTCFG_VP13MAP_PORTG_gc = (0x06<<4), /* Mapped To PORTG */ - PORTCFG_VP13MAP_PORTM_gc = (0x0B<<4), /* Mapped To PORTM */ - PORTCFG_VP13MAP_PORTR_gc = (0x0F<<4), /* Mapped To PORTR */ -} PORTCFG_VP13MAP_t; - -/* System Clock Output Port */ -typedef enum PORTCFG_CLKOUT_enum -{ - PORTCFG_CLKOUT_OFF_gc = (0x00<<0), /* System Clock Output Disabled */ - PORTCFG_CLKOUT_PC_gc = (0x01<<0), /* System Clock Output on Port C */ - PORTCFG_CLKOUT_PE_gc = (0x03<<0), /* System Clock Output on Port E */ -} PORTCFG_CLKOUT_t; - -/* Peripheral Clock Output Select */ -typedef enum PORTCFG_CLKOUTSEL_enum -{ - PORTCFG_CLKOUTSEL_CLK1X_gc = (0x00<<2), /* 1x Peripheral Clock Output to pin */ - PORTCFG_CLKOUTSEL_CLK2X_gc = (0x01<<2), /* 2x Peripheral Clock Output to pin */ - PORTCFG_CLKOUTSEL_CLK4X_gc = (0x02<<2), /* 4x Peripheral Clock Output to pin */ -} PORTCFG_CLKOUTSEL_t; - -/* Event Output Port */ -typedef enum PORTCFG_EVOUT_enum -{ - PORTCFG_EVOUT_OFF_gc = (0x00<<4), /* Event Output Disabled */ - PORTCFG_EVOUT_PC_gc = (0x01<<4), /* Event Channel 0 Output on Port C */ - PORTCFG_EVOUT_PE_gc = (0x03<<4), /* Event Channel 0 Output on Port E */ -} PORTCFG_EVOUT_t; - -/* Clock and Event Output Port */ -typedef enum PORTCFG_CLKEVPIN_enum -{ - PORTCFG_CLKEVPIN_PIN7_gc = (0x00<<7), /* Clock and Event Ouput on PIN 7 */ - PORTCFG_CLKEVPIN_PIN4_gc = (0x01<<7), /* Clock and Event Ouput on PIN 4 */ -} PORTCFG_CLKEVPIN_t; - -/* Event Output Select */ -typedef enum PORTCFG_EVOUTSEL_enum -{ - PORTCFG_EVOUTSEL_0_gc = (0x00<<2), /* Event Channel 0 output to pin */ - PORTCFG_EVOUTSEL_1_gc = (0x01<<2), /* Event Channel 1 output to pin */ - PORTCFG_EVOUTSEL_2_gc = (0x02<<2), /* Event Channel 2 output to pin */ - PORTCFG_EVOUTSEL_3_gc = (0x03<<2), /* Event Channel 3 output to pin */ -} PORTCFG_EVOUTSEL_t; - - -/* --------------------------------------------------------------------------- -AES - AES Module --------------------------------------------------------------------------- -*/ - -/* AES Module */ -typedef struct AES_struct -{ - register8_t CTRL; /* AES Control Register */ - register8_t STATUS; /* AES Status Register */ - register8_t STATE; /* AES State Register */ - register8_t KEY; /* AES Key Register */ - register8_t INTCTRL; /* AES Interrupt Control Register */ -} AES_t; - -/* Interrupt level */ -typedef enum AES_INTLVL_enum -{ - AES_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - AES_INTLVL_LO_gc = (0x01<<0), /* Low Level */ - AES_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ - AES_INTLVL_HI_gc = (0x03<<0), /* High Level */ -} AES_INTLVL_t; - - -/* --------------------------------------------------------------------------- -CRC - Cyclic Redundancy Checker --------------------------------------------------------------------------- -*/ - -/* Cyclic Redundancy Checker */ -typedef struct CRC_struct -{ - register8_t CTRL; /* Control Register */ - register8_t STATUS; /* Status Register */ - register8_t reserved_0x02; - register8_t DATAIN; /* Data Input */ - register8_t CHECKSUM0; /* Checksum byte 0 */ - register8_t CHECKSUM1; /* Checksum byte 1 */ - register8_t CHECKSUM2; /* Checksum byte 2 */ - register8_t CHECKSUM3; /* Checksum byte 3 */ -} CRC_t; - -/* Reset */ -typedef enum CRC_RESET_enum -{ - CRC_RESET_NO_gc = (0x00<<6), /* No Reset */ - CRC_RESET_RESET0_gc = (0x02<<6), /* Reset CRC with CHECKSUM to all zeros */ - CRC_RESET_RESET1_gc = (0x03<<6), /* Reset CRC with CHECKSUM to all ones */ -} CRC_RESET_t; - -/* Input Source */ -typedef enum CRC_SOURCE_enum -{ - CRC_SOURCE_DISABLE_gc = (0x00<<0), /* Disabled */ - CRC_SOURCE_IO_gc = (0x01<<0), /* I/O Interface */ - CRC_SOURCE_FLASH_gc = (0x02<<0), /* Flash */ - CRC_SOURCE_DMAC0_gc = (0x04<<0), /* DMAC Channel 0 */ - CRC_SOURCE_DMAC1_gc = (0x05<<0), /* DMAC Channel 1 */ -} CRC_SOURCE_t; - - -/* --------------------------------------------------------------------------- -DMA - DMA Controller --------------------------------------------------------------------------- -*/ - -/* DMA Channel */ -typedef struct DMA_CH_struct -{ - register8_t CTRLA; /* Channel Control */ - register8_t CTRLB; /* Channel Control */ - register8_t ADDRCTRL; /* Address Control */ - register8_t TRIGSRC; /* Channel Trigger Source */ - _WORDREGISTER(TRFCNT); /* Channel Block Transfer Count */ - register8_t REPCNT; /* Channel Repeat Count */ - register8_t reserved_0x07; - register8_t SRCADDR0; /* Channel Source Address 0 */ - register8_t SRCADDR1; /* Channel Source Address 1 */ - register8_t reserved_0x0A; - register8_t reserved_0x0B; - register8_t DESTADDR0; /* Channel Destination Address 0 */ - register8_t DESTADDR1; /* Channel Destination Address 1 */ - register8_t reserved_0x0E; - register8_t reserved_0x0F; -} DMA_CH_t; - - -/* DMA Controller */ -typedef struct DMA_struct -{ - register8_t CTRL; /* Control */ - register8_t reserved_0x01; - register8_t reserved_0x02; - register8_t INTFLAGS; /* Transfer Interrupt Status */ - register8_t STATUS; /* Status */ - register8_t reserved_0x05; - _WORDREGISTER(TEMP); /* Temporary Register For 16-bit Access */ - register8_t reserved_0x08; - register8_t reserved_0x09; - register8_t reserved_0x0A; - register8_t reserved_0x0B; - register8_t reserved_0x0C; - register8_t reserved_0x0D; - register8_t reserved_0x0E; - register8_t reserved_0x0F; - DMA_CH_t CH0; /* DMA Channel 0 */ - DMA_CH_t CH1; /* DMA Channel 1 */ -} DMA_t; - -/* Burst mode */ -typedef enum DMA_CH_BURSTLEN_enum -{ - DMA_CH_BURSTLEN_1BYTE_gc = (0x00<<0), /* 1-byte burst mode */ - DMA_CH_BURSTLEN_2BYTE_gc = (0x01<<0), /* 2-byte burst mode */ - DMA_CH_BURSTLEN_4BYTE_gc = (0x02<<0), /* 4-byte burst mode */ - DMA_CH_BURSTLEN_8BYTE_gc = (0x03<<0), /* 8-byte burst mode */ -} DMA_CH_BURSTLEN_t; - -/* Source address reload mode */ -typedef enum DMA_CH_SRCRELOAD_enum -{ - DMA_CH_SRCRELOAD_NONE_gc = (0x00<<6), /* No reload */ - DMA_CH_SRCRELOAD_BLOCK_gc = (0x01<<6), /* Reload at end of block */ - DMA_CH_SRCRELOAD_BURST_gc = (0x02<<6), /* Reload at end of burst */ - DMA_CH_SRCRELOAD_TRANSACTION_gc = (0x03<<6), /* Reload at end of transaction */ -} DMA_CH_SRCRELOAD_t; - -/* Source addressing mode */ -typedef enum DMA_CH_SRCDIR_enum -{ - DMA_CH_SRCDIR_FIXED_gc = (0x00<<4), /* Fixed */ - DMA_CH_SRCDIR_INC_gc = (0x01<<4), /* Increment */ - DMA_CH_SRCDIR_DEC_gc = (0x02<<4), /* Decrement */ -} DMA_CH_SRCDIR_t; - -/* Destination adress reload mode */ -typedef enum DMA_CH_DESTRELOAD_enum -{ - DMA_CH_DESTRELOAD_NONE_gc = (0x00<<2), /* No reload */ - DMA_CH_DESTRELOAD_BLOCK_gc = (0x01<<2), /* Reload at end of block */ - DMA_CH_DESTRELOAD_BURST_gc = (0x02<<2), /* Reload at end of burst */ - DMA_CH_DESTRELOAD_TRANSACTION_gc = (0x03<<2), /* Reload at end of transaction */ -} DMA_CH_DESTRELOAD_t; - -/* Destination adressing mode */ -typedef enum DMA_CH_DESTDIR_enum -{ - DMA_CH_DESTDIR_FIXED_gc = (0x00<<0), /* Fixed */ - DMA_CH_DESTDIR_INC_gc = (0x01<<0), /* Increment */ - DMA_CH_DESTDIR_DEC_gc = (0x02<<0), /* Decrement */ -} DMA_CH_DESTDIR_t; - -/* Transfer trigger source */ -typedef enum DMA_CH_TRIGSRC_enum -{ - DMA_CH_TRIGSRC_OFF_gc = (0x00<<0), /* Off software triggers only */ - DMA_CH_TRIGSRC_EVSYS_CH0_gc = (0x01<<0), /* Event System Channel 0 */ - DMA_CH_TRIGSRC_EVSYS_CH1_gc = (0x02<<0), /* Event System Channel 1 */ - DMA_CH_TRIGSRC_EVSYS_CH2_gc = (0x03<<0), /* Event System Channel 2 */ - DMA_CH_TRIGSRC_ADCA_CH0_gc = (0x10<<0), /* ADCA Channel 0 */ - DMA_CH_TRIGSRC_ADCB_CH0_gc = (0x20<<0), /* ADCB Channel 0 */ - DMA_CH_TRIGSRC_TCC0_OVF_gc = (0x40<<0), /* Timer/Counter C0 Overflow */ - DMA_CH_TRIGSRC_TCC0_ERR_gc = (0x41<<0), /* Timer/Counter C0 Error */ - DMA_CH_TRIGSRC_TCC0_CCA_gc = (0x42<<0), /* Timer/Counter C0 Compare or Capture A */ - DMA_CH_TRIGSRC_TCC0_CCB_gc = (0x43<<0), /* Timer/Counter C0 Compare or Capture B */ - DMA_CH_TRIGSRC_TCC0_CCC_gc = (0x44<<0), /* Timer/Counter C0 Compare or Capture C */ - DMA_CH_TRIGSRC_TCC0_CCD_gc = (0x45<<0), /* Timer/Counter C0 Compare or Capture D */ - DMA_CH_TRIGSRC_TCC1_OVF_gc = (0x46<<0), /* Timer/Counter C1 Overflow */ - DMA_CH_TRIGSRC_TCC1_ERR_gc = (0x47<<0), /* Timer/Counter C1 Error */ - DMA_CH_TRIGSRC_TCC1_CCA_gc = (0x48<<0), /* Timer/Counter C1 Compare or Capture A */ - DMA_CH_TRIGSRC_TCC1_CCB_gc = (0x49<<0), /* Timer/Counter C1 Compare or Capture B */ - DMA_CH_TRIGSRC_SPIC_gc = (0x4A<<0), /* SPI C Transfer Complete */ - DMA_CH_TRIGSRC_USARTC0_RXC_gc = (0x4B<<0), /* USART C0 Receive Complete */ - DMA_CH_TRIGSRC_USARTC0_DRE_gc = (0x4C<<0), /* USART C0 Data Register Empty */ - DMA_CH_TRIGSRC_TCE0_OVF_gc = (0x80<<0), /* Timer/Counter E0 Overflow */ - DMA_CH_TRIGSRC_TCE0_ERR_gc = (0x81<<0), /* Timer/Counter E0 Error */ - DMA_CH_TRIGSRC_TCE0_CCA_gc = (0x82<<0), /* Timer/Counter E0 Compare or Capture A */ - DMA_CH_TRIGSRC_TCE0_CCB_gc = (0x83<<0), /* Timer/Counter E0 Compare or Capture B */ - DMA_CH_TRIGSRC_TCE0_CCC_gc = (0x84<<0), /* Timer/Counter E0 Compare or Capture C */ - DMA_CH_TRIGSRC_TCE0_CCD_gc = (0x85<<0), /* Timer/Counter E0 Compare or Capture D */ - DMA_CH_TRIGSRC_USARTE0_RXC_gc = (0x8B<<0), /* USART E0 Receive Complete */ - DMA_CH_TRIGSRC_USARTE0_DRE_gc = (0x8C<<0), /* USART E0 Data Register Empty */ -} DMA_CH_TRIGSRC_t; - -/* Double buffering mode */ -typedef enum DMA_DBUFMODE_enum -{ - DMA_DBUFMODE_DISABLED_gc = (0x00<<2), /* Double buffering disabled */ - DMA_DBUFMODE_CH01_gc = (0x01<<2), /* Double buffering enabled on channel 0/1 */ -} DMA_DBUFMODE_t; - -/* Priority mode */ -typedef enum DMA_PRIMODE_enum -{ - DMA_PRIMODE_RR01_gc = (0x00<<0), /* Round Robin */ - DMA_PRIMODE_CH0RR1_gc = (0x01<<0), /* Channel 0 > channel 1 */ -} DMA_PRIMODE_t; - -/* Interrupt level */ -typedef enum DMA_CH_ERRINTLVL_enum -{ - DMA_CH_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ - DMA_CH_ERRINTLVL_LO_gc = (0x01<<2), /* Low level */ - DMA_CH_ERRINTLVL_MED_gc = (0x02<<2), /* Medium level */ - DMA_CH_ERRINTLVL_HI_gc = (0x03<<2), /* High level */ -} DMA_CH_ERRINTLVL_t; - -/* Interrupt level */ -typedef enum DMA_CH_TRNINTLVL_enum -{ - DMA_CH_TRNINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ - DMA_CH_TRNINTLVL_LO_gc = (0x01<<0), /* Low level */ - DMA_CH_TRNINTLVL_MED_gc = (0x02<<0), /* Medium level */ - DMA_CH_TRNINTLVL_HI_gc = (0x03<<0), /* High level */ -} DMA_CH_TRNINTLVL_t; - - -/* --------------------------------------------------------------------------- -EVSYS - Event System --------------------------------------------------------------------------- -*/ - -/* Event System */ -typedef struct EVSYS_struct -{ - register8_t CH0MUX; /* Event Channel 0 Multiplexer */ - register8_t CH1MUX; /* Event Channel 1 Multiplexer */ - register8_t CH2MUX; /* Event Channel 2 Multiplexer */ - register8_t CH3MUX; /* Event Channel 3 Multiplexer */ - register8_t reserved_0x04; - register8_t reserved_0x05; - register8_t reserved_0x06; - register8_t reserved_0x07; - register8_t CH0CTRL; /* Channel 0 Control Register */ - register8_t CH1CTRL; /* Channel 1 Control Register */ - register8_t CH2CTRL; /* Channel 2 Control Register */ - register8_t CH3CTRL; /* Channel 3 Control Register */ - register8_t reserved_0x0C; - register8_t reserved_0x0D; - register8_t reserved_0x0E; - register8_t reserved_0x0F; - register8_t STROBE; /* Event Strobe */ - register8_t DATA; /* Event Data */ -} EVSYS_t; - -/* Quadrature Decoder Index Recognition Mode */ -typedef enum EVSYS_QDIRM_enum -{ - EVSYS_QDIRM_00_gc = (0x00<<5), /* QDPH0 = 0, QDPH90 = 0 */ - EVSYS_QDIRM_01_gc = (0x01<<5), /* QDPH0 = 0, QDPH90 = 1 */ - EVSYS_QDIRM_10_gc = (0x02<<5), /* QDPH0 = 1, QDPH90 = 0 */ - EVSYS_QDIRM_11_gc = (0x03<<5), /* QDPH0 = 1, QDPH90 = 1 */ -} EVSYS_QDIRM_t; - -/* Digital filter coefficient */ -typedef enum EVSYS_DIGFILT_enum -{ - EVSYS_DIGFILT_1SAMPLE_gc = (0x00<<0), /* 1 SAMPLE */ - EVSYS_DIGFILT_2SAMPLES_gc = (0x01<<0), /* 2 SAMPLES */ - EVSYS_DIGFILT_3SAMPLES_gc = (0x02<<0), /* 3 SAMPLES */ - EVSYS_DIGFILT_4SAMPLES_gc = (0x03<<0), /* 4 SAMPLES */ - EVSYS_DIGFILT_5SAMPLES_gc = (0x04<<0), /* 5 SAMPLES */ - EVSYS_DIGFILT_6SAMPLES_gc = (0x05<<0), /* 6 SAMPLES */ - EVSYS_DIGFILT_7SAMPLES_gc = (0x06<<0), /* 7 SAMPLES */ - EVSYS_DIGFILT_8SAMPLES_gc = (0x07<<0), /* 8 SAMPLES */ -} EVSYS_DIGFILT_t; - -/* Event Channel multiplexer input selection */ -typedef enum EVSYS_CHMUX_enum -{ - EVSYS_CHMUX_OFF_gc = (0x00<<0), /* Off */ - EVSYS_CHMUX_RTC_OVF_gc = (0x08<<0), /* RTC Overflow */ - EVSYS_CHMUX_RTC_CMP_gc = (0x09<<0), /* RTC Compare Match */ - EVSYS_CHMUX_USB_gc = (0x0A<<0), /* USB Setup, SOF, CRC error and UNF/OVF */ - EVSYS_CHMUX_ACA_CH0_gc = (0x10<<0), /* Analog Comparator A Channel 0 */ - EVSYS_CHMUX_ACA_CH1_gc = (0x11<<0), /* Analog Comparator A Channel 1 */ - EVSYS_CHMUX_ACA_WIN_gc = (0x12<<0), /* Analog Comparator A Window */ - EVSYS_CHMUX_ACB_CH0_gc = (0x13<<0), /* Analog Comparator B Channel 0 */ - EVSYS_CHMUX_ACB_CH1_gc = (0x14<<0), /* Analog Comparator B Channel 1 */ - EVSYS_CHMUX_ACB_WIN_gc = (0x15<<0), /* Analog Comparator B Window */ - EVSYS_CHMUX_ADCA_CH0_gc = (0x20<<0), /* ADC A Channel */ - EVSYS_CHMUX_ADCB_CH0_gc = (0x24<<0), /* ADC B Channel */ - EVSYS_CHMUX_PORTA_PIN0_gc = (0x50<<0), /* Port A, Pin0 */ - EVSYS_CHMUX_PORTA_PIN1_gc = (0x51<<0), /* Port A, Pin1 */ - EVSYS_CHMUX_PORTA_PIN2_gc = (0x52<<0), /* Port A, Pin2 */ - EVSYS_CHMUX_PORTA_PIN3_gc = (0x53<<0), /* Port A, Pin3 */ - EVSYS_CHMUX_PORTA_PIN4_gc = (0x54<<0), /* Port A, Pin4 */ - EVSYS_CHMUX_PORTA_PIN5_gc = (0x55<<0), /* Port A, Pin5 */ - EVSYS_CHMUX_PORTA_PIN6_gc = (0x56<<0), /* Port A, Pin6 */ - EVSYS_CHMUX_PORTA_PIN7_gc = (0x57<<0), /* Port A, Pin7 */ - EVSYS_CHMUX_PORTB_PIN0_gc = (0x58<<0), /* Port B, Pin0 */ - EVSYS_CHMUX_PORTB_PIN1_gc = (0x59<<0), /* Port B, Pin1 */ - EVSYS_CHMUX_PORTB_PIN2_gc = (0x5A<<0), /* Port B, Pin2 */ - EVSYS_CHMUX_PORTB_PIN3_gc = (0x5B<<0), /* Port B, Pin3 */ - EVSYS_CHMUX_PORTB_PIN4_gc = (0x5C<<0), /* Port B, Pin4 */ - EVSYS_CHMUX_PORTB_PIN5_gc = (0x5D<<0), /* Port B, Pin5 */ - EVSYS_CHMUX_PORTB_PIN6_gc = (0x5E<<0), /* Port B, Pin6 */ - EVSYS_CHMUX_PORTB_PIN7_gc = (0x5F<<0), /* Port B, Pin7 */ - EVSYS_CHMUX_PORTC_PIN0_gc = (0x60<<0), /* Port C, Pin0 */ - EVSYS_CHMUX_PORTC_PIN1_gc = (0x61<<0), /* Port C, Pin1 */ - EVSYS_CHMUX_PORTC_PIN2_gc = (0x62<<0), /* Port C, Pin2 */ - EVSYS_CHMUX_PORTC_PIN3_gc = (0x63<<0), /* Port C, Pin3 */ - EVSYS_CHMUX_PORTC_PIN4_gc = (0x64<<0), /* Port C, Pin4 */ - EVSYS_CHMUX_PORTC_PIN5_gc = (0x65<<0), /* Port C, Pin5 */ - EVSYS_CHMUX_PORTC_PIN6_gc = (0x66<<0), /* Port C, Pin6 */ - EVSYS_CHMUX_PORTC_PIN7_gc = (0x67<<0), /* Port C, Pin7 */ - EVSYS_CHMUX_PORTD_PIN0_gc = (0x68<<0), /* Port D, Pin0 */ - EVSYS_CHMUX_PORTD_PIN1_gc = (0x69<<0), /* Port D, Pin1 */ - EVSYS_CHMUX_PORTD_PIN2_gc = (0x6A<<0), /* Port D, Pin2 */ - EVSYS_CHMUX_PORTE_PIN0_gc = (0x70<<0), /* Port E, Pin0 */ - EVSYS_CHMUX_PORTE_PIN1_gc = (0x71<<0), /* Port E, Pin1 */ - EVSYS_CHMUX_PORTE_PIN2_gc = (0x72<<0), /* Port E, Pin2 */ - EVSYS_CHMUX_PORTE_PIN3_gc = (0x73<<0), /* Port E, Pin3 */ - EVSYS_CHMUX_PORTE_PIN4_gc = (0x74<<0), /* Port E, Pin4 */ - EVSYS_CHMUX_PORTE_PIN5_gc = (0x75<<0), /* Port E, Pin5 */ - EVSYS_CHMUX_PORTE_PIN6_gc = (0x76<<0), /* Port E, Pin6 */ - EVSYS_CHMUX_PORTE_PIN7_gc = (0x77<<0), /* Port E, Pin7 */ - EVSYS_CHMUX_PRESCALER_1_gc = (0x80<<0), /* Prescaler, divide by 1 */ - EVSYS_CHMUX_PRESCALER_2_gc = (0x81<<0), /* Prescaler, divide by 2 */ - EVSYS_CHMUX_PRESCALER_4_gc = (0x82<<0), /* Prescaler, divide by 4 */ - EVSYS_CHMUX_PRESCALER_8_gc = (0x83<<0), /* Prescaler, divide by 8 */ - EVSYS_CHMUX_PRESCALER_16_gc = (0x84<<0), /* Prescaler, divide by 16 */ - EVSYS_CHMUX_PRESCALER_32_gc = (0x85<<0), /* Prescaler, divide by 32 */ - EVSYS_CHMUX_PRESCALER_64_gc = (0x86<<0), /* Prescaler, divide by 64 */ - EVSYS_CHMUX_PRESCALER_128_gc = (0x87<<0), /* Prescaler, divide by 128 */ - EVSYS_CHMUX_PRESCALER_256_gc = (0x88<<0), /* Prescaler, divide by 256 */ - EVSYS_CHMUX_PRESCALER_512_gc = (0x89<<0), /* Prescaler, divide by 512 */ - EVSYS_CHMUX_PRESCALER_1024_gc = (0x8A<<0), /* Prescaler, divide by 1024 */ - EVSYS_CHMUX_PRESCALER_2048_gc = (0x8B<<0), /* Prescaler, divide by 2048 */ - EVSYS_CHMUX_PRESCALER_4096_gc = (0x8C<<0), /* Prescaler, divide by 4096 */ - EVSYS_CHMUX_PRESCALER_8192_gc = (0x8D<<0), /* Prescaler, divide by 8192 */ - EVSYS_CHMUX_PRESCALER_16384_gc = (0x8E<<0), /* Prescaler, divide by 16384 */ - EVSYS_CHMUX_PRESCALER_32768_gc = (0x8F<<0), /* Prescaler, divide by 32768 */ - EVSYS_CHMUX_TCC0_OVF_gc = (0xC0<<0), /* Timer/Counter C0 Overflow */ - EVSYS_CHMUX_TCC0_ERR_gc = (0xC1<<0), /* Timer/Counter C0 Error */ - EVSYS_CHMUX_TCC0_CCA_gc = (0xC4<<0), /* Timer/Counter C0 Compare or Capture A */ - EVSYS_CHMUX_TCC0_CCB_gc = (0xC5<<0), /* Timer/Counter C0 Compare or Capture B */ - EVSYS_CHMUX_TCC0_CCC_gc = (0xC6<<0), /* Timer/Counter C0 Compare or Capture C */ - EVSYS_CHMUX_TCC0_CCD_gc = (0xC7<<0), /* Timer/Counter C0 Compare or Capture D */ - EVSYS_CHMUX_TCC1_OVF_gc = (0xC8<<0), /* Timer/Counter C1 Overflow */ - EVSYS_CHMUX_TCC1_ERR_gc = (0xC9<<0), /* Timer/Counter C1 Error */ - EVSYS_CHMUX_TCC1_CCA_gc = (0xCC<<0), /* Timer/Counter C1 Compare or Capture A */ - EVSYS_CHMUX_TCC1_CCB_gc = (0xCD<<0), /* Timer/Counter C1 Compare or Capture B */ - EVSYS_CHMUX_TCE0_OVF_gc = (0xE0<<0), /* Timer/Counter E0 Overflow */ - EVSYS_CHMUX_TCE0_ERR_gc = (0xE1<<0), /* Timer/Counter E0 Error */ - EVSYS_CHMUX_TCE0_CCA_gc = (0xE4<<0), /* Timer/Counter E0 Compare or Capture A */ - EVSYS_CHMUX_TCE0_CCB_gc = (0xE5<<0), /* Timer/Counter E0 Compare or Capture B */ - EVSYS_CHMUX_TCE0_CCC_gc = (0xE6<<0), /* Timer/Counter E0 Compare or Capture C */ - EVSYS_CHMUX_TCE0_CCD_gc = (0xE7<<0), /* Timer/Counter E0 Compare or Capture D */ -} EVSYS_CHMUX_t; - - -/* --------------------------------------------------------------------------- -NVM - Non Volatile Memory Controller --------------------------------------------------------------------------- -*/ - -/* Non-volatile Memory Controller */ -typedef struct NVM_struct -{ - register8_t ADDR0; /* Address Register 0 */ - register8_t ADDR1; /* Address Register 1 */ - register8_t ADDR2; /* Address Register 2 */ - register8_t reserved_0x03; - register8_t DATA0; /* Data Register 0 */ - register8_t DATA1; /* Data Register 1 */ - register8_t DATA2; /* Data Register 2 */ - register8_t reserved_0x07; - register8_t reserved_0x08; - register8_t reserved_0x09; - register8_t CMD; /* Command */ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t INTCTRL; /* Interrupt Control */ - register8_t reserved_0x0E; - register8_t STATUS; /* Status */ - register8_t LOCK_BITS; /* Lock Bits (Changed from LOCKBITS to avoid avr-libc collision) */ -} NVM_t; - -/* NVM Command */ -typedef enum NVM_CMD_enum -{ - NVM_CMD_NO_OPERATION_gc = (0x00<<0), /* Noop/Ordinary LPM */ - NVM_CMD_READ_USER_SIG_ROW_gc = (0x01<<0), /* Read user signature row */ - NVM_CMD_READ_CALIB_ROW_gc = (0x02<<0), /* Read calibration row */ - NVM_CMD_READ_EEPROM_gc = (0x06<<0), /* Read EEPROM */ - NVM_CMD_READ_FUSES_gc = (0x07<<0), /* Read fuse byte */ - NVM_CMD_WRITE_LOCK_BITS_gc = (0x08<<0), /* Write lock bits */ - NVM_CMD_ERASE_USER_SIG_ROW_gc = (0x18<<0), /* Erase user signature row */ - NVM_CMD_WRITE_USER_SIG_ROW_gc = (0x1A<<0), /* Write user signature row */ - NVM_CMD_ERASE_APP_gc = (0x20<<0), /* Erase Application Section */ - NVM_CMD_ERASE_APP_PAGE_gc = (0x22<<0), /* Erase Application Section page */ - NVM_CMD_LOAD_FLASH_BUFFER_gc = (0x23<<0), /* Load Flash page buffer */ - NVM_CMD_WRITE_APP_PAGE_gc = (0x24<<0), /* Write Application Section page */ - NVM_CMD_ERASE_WRITE_APP_PAGE_gc = (0x25<<0), /* Erase-and-write Application Section page */ - NVM_CMD_ERASE_FLASH_BUFFER_gc = (0x26<<0), /* Erase/flush Flash page buffer */ - NVM_CMD_ERASE_BOOT_PAGE_gc = (0x2A<<0), /* Erase Boot Section page */ - NVM_CMD_ERASE_FLASH_PAGE_gc = (0x2B<<0), /* Erase Flash Page */ - NVM_CMD_WRITE_BOOT_PAGE_gc = (0x2C<<0), /* Write Boot Section page */ - NVM_CMD_ERASE_WRITE_BOOT_PAGE_gc = (0x2D<<0), /* Erase-and-write Boot Section page */ - NVM_CMD_WRITE_FLASH_PAGE_gc = (0x2E<<0), /* Write Flash Page */ - NVM_CMD_ERASE_WRITE_FLASH_PAGE_gc = (0x2F<<0), /* Erase-and-write Flash Page */ - NVM_CMD_ERASE_EEPROM_gc = (0x30<<0), /* Erase EEPROM */ - NVM_CMD_ERASE_EEPROM_PAGE_gc = (0x32<<0), /* Erase EEPROM page */ - NVM_CMD_LOAD_EEPROM_BUFFER_gc = (0x33<<0), /* Load EEPROM page buffer */ - NVM_CMD_WRITE_EEPROM_PAGE_gc = (0x34<<0), /* Write EEPROM page */ - NVM_CMD_ERASE_WRITE_EEPROM_PAGE_gc = (0x35<<0), /* Erase-and-write EEPROM page */ - NVM_CMD_ERASE_EEPROM_BUFFER_gc = (0x36<<0), /* Erase/flush EEPROM page buffer */ - NVM_CMD_APP_CRC_gc = (0x38<<0), /* Application section CRC */ - NVM_CMD_BOOT_CRC_gc = (0x39<<0), /* Boot Section CRC */ - NVM_CMD_FLASH_RANGE_CRC_gc = (0x3A<<0), /* Flash Range CRC */ - NVM_CMD_CHIP_ERASE_gc = (0x40<<0), /* Erase Chip */ - NVM_CMD_READ_NVM_gc = (0x43<<0), /* Read NVM */ - NVM_CMD_WRITE_FUSE_gc = (0x4C<<0), /* Write Fuse byte */ - NVM_CMD_ERASE_BOOT_gc = (0x68<<0), /* Erase Boot Section */ - NVM_CMD_FLASH_CRC_gc = (0x78<<0), /* Flash CRC */ -} NVM_CMD_t; - -/* SPM ready interrupt level */ -typedef enum NVM_SPMLVL_enum -{ - NVM_SPMLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ - NVM_SPMLVL_LO_gc = (0x01<<2), /* Low level */ - NVM_SPMLVL_MED_gc = (0x02<<2), /* Medium level */ - NVM_SPMLVL_HI_gc = (0x03<<2), /* High level */ -} NVM_SPMLVL_t; - -/* EEPROM ready interrupt level */ -typedef enum NVM_EELVL_enum -{ - NVM_EELVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ - NVM_EELVL_LO_gc = (0x01<<0), /* Low level */ - NVM_EELVL_MED_gc = (0x02<<0), /* Medium level */ - NVM_EELVL_HI_gc = (0x03<<0), /* High level */ -} NVM_EELVL_t; - -/* Boot lock bits - boot setcion */ -typedef enum NVM_BLBB_enum -{ - NVM_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ - NVM_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ - NVM_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ - NVM_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ -} NVM_BLBB_t; - -/* Boot lock bits - application section */ -typedef enum NVM_BLBA_enum -{ - NVM_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ - NVM_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ - NVM_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ - NVM_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ -} NVM_BLBA_t; - -/* Boot lock bits - application table section */ -typedef enum NVM_BLBAT_enum -{ - NVM_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ - NVM_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ - NVM_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ - NVM_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ -} NVM_BLBAT_t; - -/* Lock bits */ -typedef enum NVM_LB_enum -{ - NVM_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ - NVM_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ - NVM_LB_NOLOCK_gc = (0x03<<0), /* No locks */ -} NVM_LB_t; - - -/* --------------------------------------------------------------------------- -ADC - Analog/Digital Converter --------------------------------------------------------------------------- -*/ - -/* ADC Channel */ -typedef struct ADC_CH_struct -{ - register8_t CTRL; /* Control Register */ - register8_t MUXCTRL; /* MUX Control */ - register8_t INTCTRL; /* Channel Interrupt Control Register */ - register8_t INTFLAGS; /* Interrupt Flags */ - _WORDREGISTER(RES); /* Channel Result */ - register8_t SCAN; /* Input Channel Scan */ - register8_t reserved_0x07; -} ADC_CH_t; - - -/* Analog-to-Digital Converter */ -typedef struct ADC_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t REFCTRL; /* Reference Control */ - register8_t EVCTRL; /* Event Control */ - register8_t PRESCALER; /* Clock Prescaler */ - register8_t reserved_0x05; - register8_t INTFLAGS; /* Interrupt Flags */ - register8_t TEMP; /* Temporary Register */ - register8_t SAMPCTRL; /* ADC Sampling Time Control Register */ - register8_t reserved_0x09; - register8_t reserved_0x0A; - register8_t reserved_0x0B; - _WORDREGISTER(CAL); /* Calibration Value */ - register8_t reserved_0x0E; - register8_t reserved_0x0F; - _WORDREGISTER(CH0RES); /* Channel 0 Result */ - register8_t reserved_0x12; - register8_t reserved_0x13; - register8_t reserved_0x14; - register8_t reserved_0x15; - register8_t reserved_0x16; - register8_t reserved_0x17; - _WORDREGISTER(CMP); /* Compare Value */ - register8_t reserved_0x1A; - register8_t reserved_0x1B; - register8_t reserved_0x1C; - register8_t reserved_0x1D; - register8_t reserved_0x1E; - register8_t reserved_0x1F; - ADC_CH_t CH0; /* ADC Channel 0 */ -} ADC_t; - -/* Current Limitation */ -typedef enum ADC_CURRLIMIT_enum -{ - ADC_CURRLIMIT_NO_gc = (0x00<<5), /* No current limit, 300ksps max sampling rate */ - ADC_CURRLIMIT_LOW_gc = (0x01<<5), /* Low current limit, 250ksps max sampling rate */ - ADC_CURRLIMIT_MED_gc = (0x02<<5), /* Medium current limit, 150ksps max sampling rate */ - ADC_CURRLIMIT_HIGH_gc = (0x03<<5), /* High current limit, 50ksps max sampling rate */ -} ADC_CURRLIMIT_t; - -/* Positive input multiplexer selection */ -typedef enum ADC_CH_MUXPOS_enum -{ - ADC_CH_MUXPOS_PIN0_gc = (0x00<<3), /* Input pin 0 */ - ADC_CH_MUXPOS_PIN1_gc = (0x01<<3), /* Input pin 1 */ - ADC_CH_MUXPOS_PIN2_gc = (0x02<<3), /* Input pin 2 */ - ADC_CH_MUXPOS_PIN3_gc = (0x03<<3), /* Input pin 3 */ - ADC_CH_MUXPOS_PIN4_gc = (0x04<<3), /* Input pin 4 */ - ADC_CH_MUXPOS_PIN5_gc = (0x05<<3), /* Input pin 5 */ - ADC_CH_MUXPOS_PIN6_gc = (0x06<<3), /* Input pin 6 */ - ADC_CH_MUXPOS_PIN7_gc = (0x07<<3), /* Input pin 7 */ - ADC_CH_MUXPOS_PIN8_gc = (0x08<<3), /* Input pin 8 */ - ADC_CH_MUXPOS_PIN9_gc = (0x09<<3), /* Input pin 9 */ - ADC_CH_MUXPOS_PIN10_gc = (0x0A<<3), /* Input pin 10 */ - ADC_CH_MUXPOS_PIN11_gc = (0x0B<<3), /* Input pin 11 */ - ADC_CH_MUXPOS_PIN12_gc = (0x0C<<3), /* Input pin 12 */ - ADC_CH_MUXPOS_PIN13_gc = (0x0D<<3), /* Input pin 13 */ - ADC_CH_MUXPOS_PIN14_gc = (0x0E<<3), /* Input pin 14 */ - ADC_CH_MUXPOS_PIN15_gc = (0x0F<<3), /* Input pin 15 */ -} ADC_CH_MUXPOS_t; - -/* Internal input multiplexer selections */ -typedef enum ADC_CH_MUXINT_enum -{ - ADC_CH_MUXINT_TEMP_gc = (0x00<<3), /* Temperature Reference */ - ADC_CH_MUXINT_BANDGAP_gc = (0x01<<3), /* Bandgap Reference */ - ADC_CH_MUXINT_SCALEDVCC_gc = (0x02<<3), /* 1/10 scaled VCC */ -} ADC_CH_MUXINT_t; - -/* Negative input multiplexer selection */ -typedef enum ADC_CH_MUXNEG_enum -{ - ADC_CH_MUXNEG_PIN0_gc = (0x00<<0), /* Input pin 0 */ - ADC_CH_MUXNEG_PIN1_gc = (0x01<<0), /* Input pin 1 */ - ADC_CH_MUXNEG_PIN2_gc = (0x02<<0), /* Input pin 2 */ - ADC_CH_MUXNEG_PIN3_gc = (0x03<<0), /* Input pin 3 */ - ADC_CH_MUXNEG_PIN4_gc = (0x00<<0), /* Input pin 4 */ - ADC_CH_MUXNEG_PIN5_gc = (0x01<<0), /* Input pin 5 */ - ADC_CH_MUXNEG_PIN6_gc = (0x02<<0), /* Input pin 6 */ - ADC_CH_MUXNEG_PIN7_gc = (0x03<<0), /* Input pin 7 */ -} ADC_CH_MUXNEG_t; - -/* Input mode */ -typedef enum ADC_CH_INPUTMODE_enum -{ - ADC_CH_INPUTMODE_INTERNAL_gc = (0x00<<0), /* Internal inputs, no gain */ - ADC_CH_INPUTMODE_SINGLEENDED_gc = (0x01<<0), /* Single-ended input, no gain */ - ADC_CH_INPUTMODE_DIFF_gc = (0x02<<0), /* Differential input, no gain */ - ADC_CH_INPUTMODE_DIFFWGAIN_gc = (0x03<<0), /* Differential input, with gain */ -} ADC_CH_INPUTMODE_t; - -/* Gain factor */ -typedef enum ADC_CH_GAIN_enum -{ - ADC_CH_GAIN_1X_gc = (0x00<<2), /* 1x gain */ - ADC_CH_GAIN_2X_gc = (0x01<<2), /* 2x gain */ - ADC_CH_GAIN_4X_gc = (0x02<<2), /* 4x gain */ - ADC_CH_GAIN_8X_gc = (0x03<<2), /* 8x gain */ - ADC_CH_GAIN_16X_gc = (0x04<<2), /* 16x gain */ - ADC_CH_GAIN_32X_gc = (0x05<<2), /* 32x gain */ - ADC_CH_GAIN_64X_gc = (0x06<<2), /* 64x gain */ - ADC_CH_GAIN_DIV2_gc = (0x07<<2), /* x/2 gain */ -} ADC_CH_GAIN_t; - -/* Conversion result resolution */ -typedef enum ADC_RESOLUTION_enum -{ - ADC_RESOLUTION_12BIT_gc = (0x00<<1), /* 12-bit right-adjusted result */ - ADC_RESOLUTION_8BIT_gc = (0x02<<1), /* 8-bit right-adjusted result */ - ADC_RESOLUTION_LEFT12BIT_gc = (0x03<<1), /* 12-bit left-adjusted result */ -} ADC_RESOLUTION_t; - -/* Voltage reference selection */ -typedef enum ADC_REFSEL_enum -{ - ADC_REFSEL_INT1V_gc = (0x00<<4), /* Internal 1V */ - ADC_REFSEL_INTVCC_gc = (0x01<<4), /* Internal VCC / 1.6 */ - ADC_REFSEL_AREFA_gc = (0x02<<4), /* External reference on PORT A */ - ADC_REFSEL_AREFB_gc = (0x03<<4), /* External reference on PORT B */ - ADC_REFSEL_INTVCC2_gc = (0x04<<4), /* Internal VCC / 2 */ -} ADC_REFSEL_t; - -/* Event channel input selection */ -typedef enum ADC_EVSEL_enum -{ - ADC_EVSEL_0_gc = (0x00<<3), /* Event Channel 0 */ - ADC_EVSEL_1_gc = (0x01<<3), /* Event Channel 1 */ - ADC_EVSEL_2_gc = (0x02<<3), /* Event Channel 2 */ - ADC_EVSEL_3_gc = (0x03<<3), /* Event Channel 3 */ -} ADC_EVSEL_t; - -/* Event action selection */ -typedef enum ADC_EVACT_enum -{ - ADC_EVACT_NONE_gc = (0x00<<0), /* No event action */ - ADC_EVACT_CH0_gc = (0x01<<0), /* First event triggers channel 0 */ - ADC_EVACT_SYNCSWEEP_gc = (0x06<<0), /* The ADC is flushed and restarted for accurate timing */ -} ADC_EVACT_t; - -/* Interupt mode */ -typedef enum ADC_CH_INTMODE_enum -{ - ADC_CH_INTMODE_COMPLETE_gc = (0x00<<2), /* Interrupt on conversion complete */ - ADC_CH_INTMODE_BELOW_gc = (0x01<<2), /* Interrupt on result below compare value */ - ADC_CH_INTMODE_ABOVE_gc = (0x03<<2), /* Interrupt on result above compare value */ -} ADC_CH_INTMODE_t; - -/* Interrupt level */ -typedef enum ADC_CH_INTLVL_enum -{ - ADC_CH_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ - ADC_CH_INTLVL_LO_gc = (0x01<<0), /* Low level */ - ADC_CH_INTLVL_MED_gc = (0x02<<0), /* Medium level */ - ADC_CH_INTLVL_HI_gc = (0x03<<0), /* High level */ -} ADC_CH_INTLVL_t; - -/* Clock prescaler */ -typedef enum ADC_PRESCALER_enum -{ - ADC_PRESCALER_DIV4_gc = (0x00<<0), /* Divide clock by 4 */ - ADC_PRESCALER_DIV8_gc = (0x01<<0), /* Divide clock by 8 */ - ADC_PRESCALER_DIV16_gc = (0x02<<0), /* Divide clock by 16 */ - ADC_PRESCALER_DIV32_gc = (0x03<<0), /* Divide clock by 32 */ - ADC_PRESCALER_DIV64_gc = (0x04<<0), /* Divide clock by 64 */ - ADC_PRESCALER_DIV128_gc = (0x05<<0), /* Divide clock by 128 */ - ADC_PRESCALER_DIV256_gc = (0x06<<0), /* Divide clock by 256 */ - ADC_PRESCALER_DIV512_gc = (0x07<<0), /* Divide clock by 512 */ -} ADC_PRESCALER_t; - - -/* --------------------------------------------------------------------------- -AC - Analog Comparator --------------------------------------------------------------------------- -*/ - -/* Analog Comparator */ -typedef struct AC_struct -{ - register8_t AC0CTRL; /* Analog Comparator 0 Control */ - register8_t AC1CTRL; /* Analog Comparator 1 Control */ - register8_t AC0MUXCTRL; /* Analog Comparator 0 MUX Control */ - register8_t AC1MUXCTRL; /* Analog Comparator 1 MUX Control */ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t WINCTRL; /* Window Mode Control */ - register8_t STATUS; /* Status */ - register8_t CURRCTRL; /* Current Source Control Register */ - register8_t CURRCALIB; /* Current Source Calibration Register */ -} AC_t; - -/* Interrupt mode */ -typedef enum AC_INTMODE_enum -{ - AC_INTMODE_BOTHEDGES_gc = (0x00<<6), /* Interrupt on both edges */ - AC_INTMODE_FALLING_gc = (0x02<<6), /* Interrupt on falling edge */ - AC_INTMODE_RISING_gc = (0x03<<6), /* Interrupt on rising edge */ -} AC_INTMODE_t; - -/* Interrupt level */ -typedef enum AC_INTLVL_enum -{ - AC_INTLVL_OFF_gc = (0x00<<4), /* Interrupt disabled */ - AC_INTLVL_LO_gc = (0x01<<4), /* Low level */ - AC_INTLVL_MED_gc = (0x02<<4), /* Medium level */ - AC_INTLVL_HI_gc = (0x03<<4), /* High level */ -} AC_INTLVL_t; - -/* Hysteresis mode selection */ -typedef enum AC_HYSMODE_enum -{ - AC_HYSMODE_NO_gc = (0x00<<1), /* No hysteresis */ - AC_HYSMODE_SMALL_gc = (0x01<<1), /* Small hysteresis */ - AC_HYSMODE_LARGE_gc = (0x02<<1), /* Large hysteresis */ -} AC_HYSMODE_t; - -/* Positive input multiplexer selection */ -typedef enum AC_MUXPOS_enum -{ - AC_MUXPOS_PIN0_gc = (0x00<<3), /* Pin 0 */ - AC_MUXPOS_PIN1_gc = (0x01<<3), /* Pin 1 */ - AC_MUXPOS_PIN2_gc = (0x02<<3), /* Pin 2 */ - AC_MUXPOS_PIN3_gc = (0x03<<3), /* Pin 3 */ - AC_MUXPOS_PIN4_gc = (0x04<<3), /* Pin 4 */ - AC_MUXPOS_PIN5_gc = (0x05<<3), /* Pin 5 */ - AC_MUXPOS_PIN6_gc = (0x06<<3), /* Pin 6 */ -} AC_MUXPOS_t; - -/* Negative input multiplexer selection */ -typedef enum AC_MUXNEG_enum -{ - AC_MUXNEG_PIN0_gc = (0x00<<0), /* Pin 0 */ - AC_MUXNEG_PIN1_gc = (0x01<<0), /* Pin 1 */ - AC_MUXNEG_PIN3_gc = (0x02<<0), /* Pin 3 */ - AC_MUXNEG_PIN5_gc = (0x03<<0), /* Pin 5 */ - AC_MUXNEG_PIN7_gc = (0x04<<0), /* Pin 7 */ - AC_MUXNEG_BANDGAP_gc = (0x06<<0), /* Bandgap Reference */ - AC_MUXNEG_SCALER_gc = (0x07<<0), /* Internal voltage scaler */ -} AC_MUXNEG_t; - -/* Windows interrupt mode */ -typedef enum AC_WINTMODE_enum -{ - AC_WINTMODE_ABOVE_gc = (0x00<<2), /* Interrupt on above window */ - AC_WINTMODE_INSIDE_gc = (0x01<<2), /* Interrupt on inside window */ - AC_WINTMODE_BELOW_gc = (0x02<<2), /* Interrupt on below window */ - AC_WINTMODE_OUTSIDE_gc = (0x03<<2), /* Interrupt on outside window */ -} AC_WINTMODE_t; - -/* Window interrupt level */ -typedef enum AC_WINTLVL_enum -{ - AC_WINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ - AC_WINTLVL_LO_gc = (0x01<<0), /* Low priority */ - AC_WINTLVL_MED_gc = (0x02<<0), /* Medium priority */ - AC_WINTLVL_HI_gc = (0x03<<0), /* High priority */ -} AC_WINTLVL_t; - -/* Window mode state */ -typedef enum AC_WSTATE_enum -{ - AC_WSTATE_ABOVE_gc = (0x00<<6), /* Signal above window */ - AC_WSTATE_INSIDE_gc = (0x01<<6), /* Signal inside window */ - AC_WSTATE_BELOW_gc = (0x02<<6), /* Signal below window */ -} AC_WSTATE_t; - - -/* --------------------------------------------------------------------------- -RTC - Real-Time Counter --------------------------------------------------------------------------- -*/ - -/* Real-Time Counter */ -typedef struct RTC_struct -{ - register8_t CTRL; /* Control Register */ - register8_t STATUS; /* Status Register */ - register8_t INTCTRL; /* Interrupt Control Register */ - register8_t INTFLAGS; /* Interrupt Flags */ - register8_t TEMP; /* Temporary register */ - register8_t reserved_0x05; - register8_t reserved_0x06; - register8_t reserved_0x07; - _WORDREGISTER(CNT); /* Count Register */ - _WORDREGISTER(PER); /* Period Register */ - _WORDREGISTER(COMP); /* Compare Register */ -} RTC_t; - -/* Prescaler Factor */ -typedef enum RTC_PRESCALER_enum -{ - RTC_PRESCALER_OFF_gc = (0x00<<0), /* RTC Off */ - RTC_PRESCALER_DIV1_gc = (0x01<<0), /* RTC Clock */ - RTC_PRESCALER_DIV2_gc = (0x02<<0), /* RTC Clock / 2 */ - RTC_PRESCALER_DIV8_gc = (0x03<<0), /* RTC Clock / 8 */ - RTC_PRESCALER_DIV16_gc = (0x04<<0), /* RTC Clock / 16 */ - RTC_PRESCALER_DIV64_gc = (0x05<<0), /* RTC Clock / 64 */ - RTC_PRESCALER_DIV256_gc = (0x06<<0), /* RTC Clock / 256 */ - RTC_PRESCALER_DIV1024_gc = (0x07<<0), /* RTC Clock / 1024 */ -} RTC_PRESCALER_t; - -/* Compare Interrupt level */ -typedef enum RTC_COMPINTLVL_enum -{ - RTC_COMPINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ - RTC_COMPINTLVL_LO_gc = (0x01<<2), /* Low Level */ - RTC_COMPINTLVL_MED_gc = (0x02<<2), /* Medium Level */ - RTC_COMPINTLVL_HI_gc = (0x03<<2), /* High Level */ -} RTC_COMPINTLVL_t; - -/* Overflow Interrupt level */ -typedef enum RTC_OVFINTLVL_enum -{ - RTC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - RTC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ - RTC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ - RTC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ -} RTC_OVFINTLVL_t; - - -/* --------------------------------------------------------------------------- -TWI - Two-Wire Interface --------------------------------------------------------------------------- -*/ - -/* */ -typedef struct TWI_MASTER_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t CTRLC; /* Control Register C */ - register8_t STATUS; /* Status Register */ - register8_t BAUD; /* Baurd Rate Control Register */ - register8_t ADDR; /* Address Register */ - register8_t DATA; /* Data Register */ -} TWI_MASTER_t; - - -/* */ -typedef struct TWI_SLAVE_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t STATUS; /* Status Register */ - register8_t ADDR; /* Address Register */ - register8_t DATA; /* Data Register */ - register8_t ADDRMASK; /* Address Mask Register */ -} TWI_SLAVE_t; - - -/* Two-Wire Interface */ -typedef struct TWI_struct -{ - register8_t CTRL; /* TWI Common Control Register */ - TWI_MASTER_t MASTER; /* TWI master module */ - TWI_SLAVE_t SLAVE; /* TWI slave module */ -} TWI_t; - -/* SDA Hold Time */ -typedef enum TWI_SDAHOLD_enum -{ - TWI_SDAHOLD_OFF_gc = (0x00<<1), /* SDA Hold Time off */ - TWI_SDAHOLD_50NS_gc = (0x01<<1), /* SDA Hold Time 50 ns */ - TWI_SDAHOLD_300NS_gc = (0x02<<1), /* SDA Hold Time 300 ns */ - TWI_SDAHOLD_400NS_gc = (0x03<<1), /* SDA Hold Time 400 ns */ -} TWI_SDAHOLD_t; - -/* Master Interrupt Level */ -typedef enum TWI_MASTER_INTLVL_enum -{ - TWI_MASTER_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ - TWI_MASTER_INTLVL_LO_gc = (0x01<<6), /* Low Level */ - TWI_MASTER_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ - TWI_MASTER_INTLVL_HI_gc = (0x03<<6), /* High Level */ -} TWI_MASTER_INTLVL_t; - -/* Inactive Timeout */ -typedef enum TWI_MASTER_TIMEOUT_enum -{ - TWI_MASTER_TIMEOUT_DISABLED_gc = (0x00<<2), /* Bus Timeout Disabled */ - TWI_MASTER_TIMEOUT_50US_gc = (0x01<<2), /* 50 Microseconds */ - TWI_MASTER_TIMEOUT_100US_gc = (0x02<<2), /* 100 Microseconds */ - TWI_MASTER_TIMEOUT_200US_gc = (0x03<<2), /* 200 Microseconds */ -} TWI_MASTER_TIMEOUT_t; - -/* Master Command */ -typedef enum TWI_MASTER_CMD_enum -{ - TWI_MASTER_CMD_NOACT_gc = (0x00<<0), /* No Action */ - TWI_MASTER_CMD_REPSTART_gc = (0x01<<0), /* Issue Repeated Start Condition */ - TWI_MASTER_CMD_RECVTRANS_gc = (0x02<<0), /* Receive or Transmit Data */ - TWI_MASTER_CMD_STOP_gc = (0x03<<0), /* Issue Stop Condition */ -} TWI_MASTER_CMD_t; - -/* Master Bus State */ -typedef enum TWI_MASTER_BUSSTATE_enum -{ - TWI_MASTER_BUSSTATE_UNKNOWN_gc = (0x00<<0), /* Unknown Bus State */ - TWI_MASTER_BUSSTATE_IDLE_gc = (0x01<<0), /* Bus is Idle */ - TWI_MASTER_BUSSTATE_OWNER_gc = (0x02<<0), /* This Module Controls The Bus */ - TWI_MASTER_BUSSTATE_BUSY_gc = (0x03<<0), /* The Bus is Busy */ -} TWI_MASTER_BUSSTATE_t; - -/* Slave Interrupt Level */ -typedef enum TWI_SLAVE_INTLVL_enum -{ - TWI_SLAVE_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ - TWI_SLAVE_INTLVL_LO_gc = (0x01<<6), /* Low Level */ - TWI_SLAVE_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ - TWI_SLAVE_INTLVL_HI_gc = (0x03<<6), /* High Level */ -} TWI_SLAVE_INTLVL_t; - -/* Slave Command */ -typedef enum TWI_SLAVE_CMD_enum -{ - TWI_SLAVE_CMD_NOACT_gc = (0x00<<0), /* No Action */ - TWI_SLAVE_CMD_COMPTRANS_gc = (0x02<<0), /* Used To Complete a Transaction */ - TWI_SLAVE_CMD_RESPONSE_gc = (0x03<<0), /* Used in Response to Address/Data Interrupt */ -} TWI_SLAVE_CMD_t; - - -/* --------------------------------------------------------------------------- -USB - USB --------------------------------------------------------------------------- -*/ - -/* USB Endpoint */ -typedef struct USB_EP_struct -{ - register8_t STATUS; /* Endpoint Status */ - register8_t CTRL; /* Endpoint Control */ - _WORDREGISTER(CNT); /* USB Endpoint Counter */ - _WORDREGISTER(DATAPTR); /* Data Pointer */ - _WORDREGISTER(AUXDATA); /* Auxiliary Data */ -} USB_EP_t; - - -/* Universal Serial Bus */ -typedef struct USB_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t STATUS; /* Status Register */ - register8_t ADDR; /* Address Register */ - register8_t FIFOWP; /* FIFO Write Pointer Register */ - register8_t FIFORP; /* FIFO Read Pointer Register */ - _WORDREGISTER(EPPTR); /* Endpoint Configuration Table Pointer */ - register8_t INTCTRLA; /* Interrupt Control Register A */ - register8_t INTCTRLB; /* Interrupt Control Register B */ - register8_t INTFLAGSACLR; /* Clear Interrupt Flag Register A */ - register8_t INTFLAGSASET; /* Set Interrupt Flag Register A */ - register8_t INTFLAGSBCLR; /* Clear Interrupt Flag Register B */ - register8_t INTFLAGSBSET; /* Set Interrupt Flag Register B */ - register8_t reserved_0x0E; - register8_t reserved_0x0F; - register8_t reserved_0x10; - register8_t reserved_0x11; - register8_t reserved_0x12; - register8_t reserved_0x13; - register8_t reserved_0x14; - register8_t reserved_0x15; - register8_t reserved_0x16; - register8_t reserved_0x17; - register8_t reserved_0x18; - register8_t reserved_0x19; - register8_t reserved_0x1A; - register8_t reserved_0x1B; - register8_t reserved_0x1C; - register8_t reserved_0x1D; - register8_t reserved_0x1E; - register8_t reserved_0x1F; - register8_t reserved_0x20; - register8_t reserved_0x21; - register8_t reserved_0x22; - register8_t reserved_0x23; - register8_t reserved_0x24; - register8_t reserved_0x25; - register8_t reserved_0x26; - register8_t reserved_0x27; - register8_t reserved_0x28; - register8_t reserved_0x29; - register8_t reserved_0x2A; - register8_t reserved_0x2B; - register8_t reserved_0x2C; - register8_t reserved_0x2D; - register8_t reserved_0x2E; - register8_t reserved_0x2F; - register8_t reserved_0x30; - register8_t reserved_0x31; - register8_t reserved_0x32; - register8_t reserved_0x33; - register8_t reserved_0x34; - register8_t reserved_0x35; - register8_t reserved_0x36; - register8_t reserved_0x37; - register8_t reserved_0x38; - register8_t reserved_0x39; - register8_t CAL0; /* Calibration Byte 0 */ - register8_t CAL1; /* Calibration Byte 1 */ -} USB_t; - - -/* USB Endpoint Table */ -typedef struct USB_EP_TABLE_struct -{ - USB_EP_t EP0OUT; /* Endpoint 0 */ - USB_EP_t EP0IN; /* Endpoint 0 */ - USB_EP_t EP1OUT; /* Endpoint 1 */ - USB_EP_t EP1IN; /* Endpoint 1 */ - USB_EP_t EP2OUT; /* Endpoint 2 */ - USB_EP_t EP2IN; /* Endpoint 2 */ - USB_EP_t EP3OUT; /* Endpoint 3 */ - USB_EP_t EP3IN; /* Endpoint 3 */ - USB_EP_t EP4OUT; /* Endpoint 4 */ - USB_EP_t EP4IN; /* Endpoint 4 */ - USB_EP_t EP5OUT; /* Endpoint 5 */ - USB_EP_t EP5IN; /* Endpoint 5 */ - USB_EP_t EP6OUT; /* Endpoint 6 */ - USB_EP_t EP6IN; /* Endpoint 6 */ - USB_EP_t EP7OUT; /* Endpoint 7 */ - USB_EP_t EP7IN; /* Endpoint 7 */ - USB_EP_t EP8OUT; /* Endpoint 8 */ - USB_EP_t EP8IN; /* Endpoint 8 */ - USB_EP_t EP9OUT; /* Endpoint 9 */ - USB_EP_t EP9IN; /* Endpoint 9 */ - USB_EP_t EP10OUT; /* Endpoint 10 */ - USB_EP_t EP10IN; /* Endpoint 10 */ - USB_EP_t EP11OUT; /* Endpoint 11 */ - USB_EP_t EP11IN; /* Endpoint 11 */ - USB_EP_t EP12OUT; /* Endpoint 12 */ - USB_EP_t EP12IN; /* Endpoint 12 */ - USB_EP_t EP13OUT; /* Endpoint 13 */ - USB_EP_t EP13IN; /* Endpoint 13 */ - USB_EP_t EP14OUT; /* Endpoint 14 */ - USB_EP_t EP14IN; /* Endpoint 14 */ - USB_EP_t EP15OUT; /* Endpoint 15 */ - USB_EP_t EP15IN; /* Endpoint 15 */ - register8_t reserved_0x100; - register8_t reserved_0x101; - register8_t reserved_0x102; - register8_t reserved_0x103; - register8_t reserved_0x104; - register8_t reserved_0x105; - register8_t reserved_0x106; - register8_t reserved_0x107; - register8_t reserved_0x108; - register8_t reserved_0x109; - register8_t reserved_0x10A; - register8_t reserved_0x10B; - register8_t reserved_0x10C; - register8_t reserved_0x10D; - register8_t reserved_0x10E; - register8_t reserved_0x10F; - register8_t FRAMENUML; /* Frame Number Low Byte */ - register8_t FRAMENUMH; /* Frame Number High Byte */ -} USB_EP_TABLE_t; - -/* Interrupt level */ -typedef enum USB_INTLVL_enum -{ - USB_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ - USB_INTLVL_LO_gc = (0x01<<0), /* Low level */ - USB_INTLVL_MED_gc = (0x02<<0), /* Medium level */ - USB_INTLVL_HI_gc = (0x03<<0), /* High level */ -} USB_INTLVL_t; - -/* USB Endpoint Type */ -typedef enum USB_EP_TYPE_enum -{ - USB_EP_TYPE_DISABLE_gc = (0x00<<6), /* Endpoint Disabled */ - USB_EP_TYPE_CONTROL_gc = (0x01<<6), /* Control */ - USB_EP_TYPE_BULK_gc = (0x02<<6), /* Bulk/Interrupt */ - USB_EP_TYPE_ISOCHRONOUS_gc = (0x03<<6), /* Isochronous */ -} USB_EP_TYPE_t; - -/* USB Endpoint Buffersize */ -typedef enum USB_EP_BUFSIZE_enum -{ - USB_EP_BUFSIZE_8_gc = (0x00<<0), /* 8 bytes buffer size */ - USB_EP_BUFSIZE_16_gc = (0x01<<0), /* 16 bytes buffer size */ - USB_EP_BUFSIZE_32_gc = (0x02<<0), /* 32 bytes buffer size */ - USB_EP_BUFSIZE_64_gc = (0x03<<0), /* 64 bytes buffer size */ - USB_EP_BUFSIZE_128_gc = (0x04<<0), /* 128 bytes buffer size */ - USB_EP_BUFSIZE_256_gc = (0x05<<0), /* 256 bytes buffer size */ - USB_EP_BUFSIZE_512_gc = (0x06<<0), /* 512 bytes buffer size */ - USB_EP_BUFSIZE_1023_gc = (0x07<<0), /* 1023 bytes buffer size */ -} USB_EP_BUFSIZE_t; - - -/* --------------------------------------------------------------------------- -PORT - I/O Port Configuration --------------------------------------------------------------------------- -*/ - -/* I/O Ports */ -typedef struct PORT_struct -{ - register8_t DIR; /* I/O Port Data Direction */ - register8_t DIRSET; /* I/O Port Data Direction Set */ - register8_t DIRCLR; /* I/O Port Data Direction Clear */ - register8_t DIRTGL; /* I/O Port Data Direction Toggle */ - register8_t OUT; /* I/O Port Output */ - register8_t OUTSET; /* I/O Port Output Set */ - register8_t OUTCLR; /* I/O Port Output Clear */ - register8_t OUTTGL; /* I/O Port Output Toggle */ - register8_t IN; /* I/O port Input */ - register8_t INTCTRL; /* Interrupt Control Register */ - register8_t INT0MASK; /* Port Interrupt 0 Mask */ - register8_t INT1MASK; /* Port Interrupt 1 Mask */ - register8_t INTFLAGS; /* Interrupt Flag Register */ - register8_t reserved_0x0D; - register8_t REMAP; /* I/O Port Pin Remap Register */ - register8_t reserved_0x0F; - register8_t PIN0CTRL; /* Pin 0 Control Register */ - register8_t PIN1CTRL; /* Pin 1 Control Register */ - register8_t PIN2CTRL; /* Pin 2 Control Register */ - register8_t PIN3CTRL; /* Pin 3 Control Register */ - register8_t PIN4CTRL; /* Pin 4 Control Register */ - register8_t PIN5CTRL; /* Pin 5 Control Register */ - register8_t PIN6CTRL; /* Pin 6 Control Register */ - register8_t PIN7CTRL; /* Pin 7 Control Register */ -} PORT_t; - -/* Port Interrupt 0 Level */ -typedef enum PORT_INT0LVL_enum -{ - PORT_INT0LVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - PORT_INT0LVL_LO_gc = (0x01<<0), /* Low Level */ - PORT_INT0LVL_MED_gc = (0x02<<0), /* Medium Level */ - PORT_INT0LVL_HI_gc = (0x03<<0), /* High Level */ -} PORT_INT0LVL_t; - -/* Port Interrupt 1 Level */ -typedef enum PORT_INT1LVL_enum -{ - PORT_INT1LVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ - PORT_INT1LVL_LO_gc = (0x01<<2), /* Low Level */ - PORT_INT1LVL_MED_gc = (0x02<<2), /* Medium Level */ - PORT_INT1LVL_HI_gc = (0x03<<2), /* High Level */ -} PORT_INT1LVL_t; - -/* Output/Pull Configuration */ -typedef enum PORT_OPC_enum -{ - PORT_OPC_TOTEM_gc = (0x00<<3), /* Totempole */ - PORT_OPC_BUSKEEPER_gc = (0x01<<3), /* Totempole w/ Bus keeper on Input and Output */ - PORT_OPC_PULLDOWN_gc = (0x02<<3), /* Totempole w/ Pull-down on Input */ - PORT_OPC_PULLUP_gc = (0x03<<3), /* Totempole w/ Pull-up on Input */ - PORT_OPC_WIREDOR_gc = (0x04<<3), /* Wired OR */ - PORT_OPC_WIREDAND_gc = (0x05<<3), /* Wired AND */ - PORT_OPC_WIREDORPULL_gc = (0x06<<3), /* Wired OR w/ Pull-down */ - PORT_OPC_WIREDANDPULL_gc = (0x07<<3), /* Wired AND w/ Pull-up */ -} PORT_OPC_t; - -/* Input/Sense Configuration */ -typedef enum PORT_ISC_enum -{ - PORT_ISC_BOTHEDGES_gc = (0x00<<0), /* Sense Both Edges */ - PORT_ISC_RISING_gc = (0x01<<0), /* Sense Rising Edge */ - PORT_ISC_FALLING_gc = (0x02<<0), /* Sense Falling Edge */ - PORT_ISC_LEVEL_gc = (0x03<<0), /* Sense Level (Transparent For Events) */ - PORT_ISC_INPUT_DISABLE_gc = (0x07<<0), /* Disable Digital Input Buffer */ -} PORT_ISC_t; - - -/* --------------------------------------------------------------------------- -TC - 16-bit Timer/Counter With PWM --------------------------------------------------------------------------- -*/ - -/* 16-bit Timer/Counter 0 */ -typedef struct TC0_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t CTRLC; /* Control register C */ - register8_t CTRLD; /* Control Register D */ - register8_t CTRLE; /* Control Register E */ - register8_t reserved_0x05; - register8_t INTCTRLA; /* Interrupt Control Register A */ - register8_t INTCTRLB; /* Interrupt Control Register B */ - register8_t CTRLFCLR; /* Control Register F Clear */ - register8_t CTRLFSET; /* Control Register F Set */ - register8_t CTRLGCLR; /* Control Register G Clear */ - register8_t CTRLGSET; /* Control Register G Set */ - register8_t INTFLAGS; /* Interrupt Flag Register */ - register8_t reserved_0x0D; - register8_t reserved_0x0E; - register8_t TEMP; /* Temporary Register For 16-bit Access */ - register8_t reserved_0x10; - register8_t reserved_0x11; - register8_t reserved_0x12; - register8_t reserved_0x13; - register8_t reserved_0x14; - register8_t reserved_0x15; - register8_t reserved_0x16; - register8_t reserved_0x17; - register8_t reserved_0x18; - register8_t reserved_0x19; - register8_t reserved_0x1A; - register8_t reserved_0x1B; - register8_t reserved_0x1C; - register8_t reserved_0x1D; - register8_t reserved_0x1E; - register8_t reserved_0x1F; - _WORDREGISTER(CNT); /* Count */ - register8_t reserved_0x22; - register8_t reserved_0x23; - register8_t reserved_0x24; - register8_t reserved_0x25; - _WORDREGISTER(PER); /* Period */ - _WORDREGISTER(CCA); /* Compare or Capture A */ - _WORDREGISTER(CCB); /* Compare or Capture B */ - _WORDREGISTER(CCC); /* Compare or Capture C */ - _WORDREGISTER(CCD); /* Compare or Capture D */ - register8_t reserved_0x30; - register8_t reserved_0x31; - register8_t reserved_0x32; - register8_t reserved_0x33; - register8_t reserved_0x34; - register8_t reserved_0x35; - _WORDREGISTER(PERBUF); /* Period Buffer */ - _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ - _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ - _WORDREGISTER(CCCBUF); /* Compare Or Capture C Buffer */ - _WORDREGISTER(CCDBUF); /* Compare Or Capture D Buffer */ -} TC0_t; - - -/* 16-bit Timer/Counter 1 */ -typedef struct TC1_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t CTRLC; /* Control register C */ - register8_t CTRLD; /* Control Register D */ - register8_t CTRLE; /* Control Register E */ - register8_t reserved_0x05; - register8_t INTCTRLA; /* Interrupt Control Register A */ - register8_t INTCTRLB; /* Interrupt Control Register B */ - register8_t CTRLFCLR; /* Control Register F Clear */ - register8_t CTRLFSET; /* Control Register F Set */ - register8_t CTRLGCLR; /* Control Register G Clear */ - register8_t CTRLGSET; /* Control Register G Set */ - register8_t INTFLAGS; /* Interrupt Flag Register */ - register8_t reserved_0x0D; - register8_t reserved_0x0E; - register8_t TEMP; /* Temporary Register For 16-bit Access */ - register8_t reserved_0x10; - register8_t reserved_0x11; - register8_t reserved_0x12; - register8_t reserved_0x13; - register8_t reserved_0x14; - register8_t reserved_0x15; - register8_t reserved_0x16; - register8_t reserved_0x17; - register8_t reserved_0x18; - register8_t reserved_0x19; - register8_t reserved_0x1A; - register8_t reserved_0x1B; - register8_t reserved_0x1C; - register8_t reserved_0x1D; - register8_t reserved_0x1E; - register8_t reserved_0x1F; - _WORDREGISTER(CNT); /* Count */ - register8_t reserved_0x22; - register8_t reserved_0x23; - register8_t reserved_0x24; - register8_t reserved_0x25; - _WORDREGISTER(PER); /* Period */ - _WORDREGISTER(CCA); /* Compare or Capture A */ - _WORDREGISTER(CCB); /* Compare or Capture B */ - register8_t reserved_0x2C; - register8_t reserved_0x2D; - register8_t reserved_0x2E; - register8_t reserved_0x2F; - register8_t reserved_0x30; - register8_t reserved_0x31; - register8_t reserved_0x32; - register8_t reserved_0x33; - register8_t reserved_0x34; - register8_t reserved_0x35; - _WORDREGISTER(PERBUF); /* Period Buffer */ - _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ - _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ -} TC1_t; - -/* Clock Selection */ -typedef enum TC_CLKSEL_enum -{ - TC_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */ - TC_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */ - TC_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */ - TC_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */ - TC_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */ - TC_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */ - TC_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */ - TC_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */ - TC_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */ - TC_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */ - TC_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */ - TC_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */ -} TC_CLKSEL_t; - -/* Waveform Generation Mode */ -typedef enum TC_WGMODE_enum -{ - TC_WGMODE_NORMAL_gc = (0x00<<0), /* Normal Mode */ - TC_WGMODE_FRQ_gc = (0x01<<0), /* Frequency Generation Mode */ - TC_WGMODE_SINGLESLOPE_gc = (0x03<<0), /* Single Slope */ - TC_WGMODE_SS_gc = (0x03<<0), /* Single Slope */ - TC_WGMODE_DSTOP_gc = (0x05<<0), /* Dual Slope, Update on TOP */ - TC_WGMODE_DS_T_gc = (0x05<<0), /* Dual Slope, Update on TOP */ - TC_WGMODE_DSBOTH_gc = (0x06<<0), /* Dual Slope, Update on both TOP and BOTTOM */ - TC_WGMODE_DS_TB_gc = (0x06<<0), /* Dual Slope, Update on both TOP and BOTTOM */ - TC_WGMODE_DSBOTTOM_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */ - TC_WGMODE_DS_B_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */ -} TC_WGMODE_t; - -/* Byte Mode */ -typedef enum TC_BYTEM_enum -{ - TC_BYTEM_NORMAL_gc = (0x00<<0), /* 16-bit mode */ - TC_BYTEM_BYTEMODE_gc = (0x01<<0), /* Timer/Counter operating in byte mode only */ - TC_BYTEM_SPLITMODE_gc = (0x02<<0), /* Timer/Counter split into two 8-bit Counters */ -} TC_BYTEM_t; - -/* Event Action */ -typedef enum TC_EVACT_enum -{ - TC_EVACT_OFF_gc = (0x00<<5), /* No Event Action */ - TC_EVACT_CAPT_gc = (0x01<<5), /* Input Capture */ - TC_EVACT_UPDOWN_gc = (0x02<<5), /* Externally Controlled Up/Down Count */ - TC_EVACT_QDEC_gc = (0x03<<5), /* Quadrature Decode */ - TC_EVACT_RESTART_gc = (0x04<<5), /* Restart */ - TC_EVACT_FRQ_gc = (0x05<<5), /* Frequency Capture */ - TC_EVACT_PW_gc = (0x06<<5), /* Pulse-width Capture */ -} TC_EVACT_t; - -/* Event Selection */ -typedef enum TC_EVSEL_enum -{ - TC_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ - TC_EVSEL_CH0_gc = (0x08<<0), /* Event Channel 0 */ - TC_EVSEL_CH1_gc = (0x09<<0), /* Event Channel 1 */ - TC_EVSEL_CH2_gc = (0x0A<<0), /* Event Channel 2 */ - TC_EVSEL_CH3_gc = (0x0B<<0), /* Event Channel 3 */ -} TC_EVSEL_t; - -/* Error Interrupt Level */ -typedef enum TC_ERRINTLVL_enum -{ - TC_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ - TC_ERRINTLVL_LO_gc = (0x01<<2), /* Low Level */ - TC_ERRINTLVL_MED_gc = (0x02<<2), /* Medium Level */ - TC_ERRINTLVL_HI_gc = (0x03<<2), /* High Level */ -} TC_ERRINTLVL_t; - -/* Overflow Interrupt Level */ -typedef enum TC_OVFINTLVL_enum -{ - TC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - TC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ - TC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ - TC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ -} TC_OVFINTLVL_t; - -/* Compare or Capture D Interrupt Level */ -typedef enum TC_CCDINTLVL_enum -{ - TC_CCDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ - TC_CCDINTLVL_LO_gc = (0x01<<6), /* Low Level */ - TC_CCDINTLVL_MED_gc = (0x02<<6), /* Medium Level */ - TC_CCDINTLVL_HI_gc = (0x03<<6), /* High Level */ -} TC_CCDINTLVL_t; - -/* Compare or Capture C Interrupt Level */ -typedef enum TC_CCCINTLVL_enum -{ - TC_CCCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ - TC_CCCINTLVL_LO_gc = (0x01<<4), /* Low Level */ - TC_CCCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ - TC_CCCINTLVL_HI_gc = (0x03<<4), /* High Level */ -} TC_CCCINTLVL_t; - -/* Compare or Capture B Interrupt Level */ -typedef enum TC_CCBINTLVL_enum -{ - TC_CCBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ - TC_CCBINTLVL_LO_gc = (0x01<<2), /* Low Level */ - TC_CCBINTLVL_MED_gc = (0x02<<2), /* Medium Level */ - TC_CCBINTLVL_HI_gc = (0x03<<2), /* High Level */ -} TC_CCBINTLVL_t; - -/* Compare or Capture A Interrupt Level */ -typedef enum TC_CCAINTLVL_enum -{ - TC_CCAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - TC_CCAINTLVL_LO_gc = (0x01<<0), /* Low Level */ - TC_CCAINTLVL_MED_gc = (0x02<<0), /* Medium Level */ - TC_CCAINTLVL_HI_gc = (0x03<<0), /* High Level */ -} TC_CCAINTLVL_t; - -/* Timer/Counter Command */ -typedef enum TC_CMD_enum -{ - TC_CMD_NONE_gc = (0x00<<2), /* No Command */ - TC_CMD_UPDATE_gc = (0x01<<2), /* Force Update */ - TC_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ - TC_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ -} TC_CMD_t; - - -/* --------------------------------------------------------------------------- -AWEX - Timer/Counter Advanced Waveform Extension --------------------------------------------------------------------------- -*/ - -/* Advanced Waveform Extension */ -typedef struct AWEX_struct -{ - register8_t CTRL; /* Control Register */ - register8_t reserved_0x01; - register8_t FDEMASK; /* Fault Detection Event Mask */ - register8_t FDCTRL; /* Fault Detection Control Register */ - register8_t STATUS; /* Status Register */ - register8_t STATUSSET; /* Status Set Register */ - register8_t DTBOTH; /* Dead Time Both Sides */ - register8_t DTBOTHBUF; /* Dead Time Both Sides Buffer */ - register8_t DTLS; /* Dead Time Low Side */ - register8_t DTHS; /* Dead Time High Side */ - register8_t DTLSBUF; /* Dead Time Low Side Buffer */ - register8_t DTHSBUF; /* Dead Time High Side Buffer */ - register8_t OUTOVEN; /* Output Override Enable */ -} AWEX_t; - -/* Fault Detect Action */ -typedef enum AWEX_FDACT_enum -{ - AWEX_FDACT_NONE_gc = (0x00<<0), /* No Fault Protection */ - AWEX_FDACT_CLEAROE_gc = (0x01<<0), /* Clear Output Enable Bits */ - AWEX_FDACT_CLEARDIR_gc = (0x03<<0), /* Clear I/O Port Direction Bits */ -} AWEX_FDACT_t; - - -/* --------------------------------------------------------------------------- -HIRES - Timer/Counter High-Resolution Extension --------------------------------------------------------------------------- -*/ - -/* High-Resolution Extension */ -typedef struct HIRES_struct -{ - register8_t CTRLA; /* Control Register */ -} HIRES_t; - -/* High Resolution Enable */ -typedef enum HIRES_HREN_enum -{ - HIRES_HREN_NONE_gc = (0x00<<0), /* No Fault Protection */ - HIRES_HREN_TC0_gc = (0x01<<0), /* Enable High Resolution on Timer/Counter 0 */ - HIRES_HREN_TC1_gc = (0x02<<0), /* Enable High Resolution on Timer/Counter 1 */ - HIRES_HREN_BOTH_gc = (0x03<<0), /* Enable High Resolution both Timer/Counters */ -} HIRES_HREN_t; - - -/* --------------------------------------------------------------------------- -USART - Universal Asynchronous Receiver-Transmitter --------------------------------------------------------------------------- -*/ - -/* Universal Synchronous/Asynchronous Receiver/Transmitter */ -typedef struct USART_struct -{ - register8_t DATA; /* Data Register */ - register8_t STATUS; /* Status Register */ - register8_t reserved_0x02; - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t CTRLC; /* Control Register C */ - register8_t BAUDCTRLA; /* Baud Rate Control Register A */ - register8_t BAUDCTRLB; /* Baud Rate Control Register B */ -} USART_t; - -/* Receive Complete Interrupt level */ -typedef enum USART_RXCINTLVL_enum -{ - USART_RXCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ - USART_RXCINTLVL_LO_gc = (0x01<<4), /* Low Level */ - USART_RXCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ - USART_RXCINTLVL_HI_gc = (0x03<<4), /* High Level */ -} USART_RXCINTLVL_t; - -/* Transmit Complete Interrupt level */ -typedef enum USART_TXCINTLVL_enum -{ - USART_TXCINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ - USART_TXCINTLVL_LO_gc = (0x01<<2), /* Low Level */ - USART_TXCINTLVL_MED_gc = (0x02<<2), /* Medium Level */ - USART_TXCINTLVL_HI_gc = (0x03<<2), /* High Level */ -} USART_TXCINTLVL_t; - -/* Data Register Empty Interrupt level */ -typedef enum USART_DREINTLVL_enum -{ - USART_DREINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - USART_DREINTLVL_LO_gc = (0x01<<0), /* Low Level */ - USART_DREINTLVL_MED_gc = (0x02<<0), /* Medium Level */ - USART_DREINTLVL_HI_gc = (0x03<<0), /* High Level */ -} USART_DREINTLVL_t; - -/* Character Size */ -typedef enum USART_CHSIZE_enum -{ - USART_CHSIZE_5BIT_gc = (0x00<<0), /* Character size: 5 bit */ - USART_CHSIZE_6BIT_gc = (0x01<<0), /* Character size: 6 bit */ - USART_CHSIZE_7BIT_gc = (0x02<<0), /* Character size: 7 bit */ - USART_CHSIZE_8BIT_gc = (0x03<<0), /* Character size: 8 bit */ - USART_CHSIZE_9BIT_gc = (0x07<<0), /* Character size: 9 bit */ -} USART_CHSIZE_t; - -/* Communication Mode */ -typedef enum USART_CMODE_enum -{ - USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6), /* Asynchronous Mode */ - USART_CMODE_SYNCHRONOUS_gc = (0x01<<6), /* Synchronous Mode */ - USART_CMODE_IRDA_gc = (0x02<<6), /* IrDA Mode */ - USART_CMODE_MSPI_gc = (0x03<<6), /* Master SPI Mode */ -} USART_CMODE_t; - -/* Parity Mode */ -typedef enum USART_PMODE_enum -{ - USART_PMODE_DISABLED_gc = (0x00<<4), /* No Parity */ - USART_PMODE_EVEN_gc = (0x02<<4), /* Even Parity */ - USART_PMODE_ODD_gc = (0x03<<4), /* Odd Parity */ -} USART_PMODE_t; - - -/* --------------------------------------------------------------------------- -SPI - Serial Peripheral Interface --------------------------------------------------------------------------- -*/ - -/* Serial Peripheral Interface */ -typedef struct SPI_struct -{ - register8_t CTRL; /* Control Register */ - register8_t INTCTRL; /* Interrupt Control Register */ - register8_t STATUS; /* Status Register */ - register8_t DATA; /* Data Register */ -} SPI_t; - -/* SPI Mode */ -typedef enum SPI_MODE_enum -{ - SPI_MODE_0_gc = (0x00<<2), /* SPI Mode 0 */ - SPI_MODE_1_gc = (0x01<<2), /* SPI Mode 1 */ - SPI_MODE_2_gc = (0x02<<2), /* SPI Mode 2 */ - SPI_MODE_3_gc = (0x03<<2), /* SPI Mode 3 */ -} SPI_MODE_t; - -/* Prescaler setting */ -typedef enum SPI_PRESCALER_enum -{ - SPI_PRESCALER_DIV4_gc = (0x00<<0), /* System Clock / 4 */ - SPI_PRESCALER_DIV16_gc = (0x01<<0), /* System Clock / 16 */ - SPI_PRESCALER_DIV64_gc = (0x02<<0), /* System Clock / 64 */ - SPI_PRESCALER_DIV128_gc = (0x03<<0), /* System Clock / 128 */ -} SPI_PRESCALER_t; - -/* Interrupt level */ -typedef enum SPI_INTLVL_enum -{ - SPI_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - SPI_INTLVL_LO_gc = (0x01<<0), /* Low Level */ - SPI_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ - SPI_INTLVL_HI_gc = (0x03<<0), /* High Level */ -} SPI_INTLVL_t; - - -/* --------------------------------------------------------------------------- -IRCOM - IR Communication Module --------------------------------------------------------------------------- -*/ - -/* IR Communication Module */ -typedef struct IRCOM_struct -{ - register8_t CTRL; /* Control Register */ - register8_t TXPLCTRL; /* IrDA Transmitter Pulse Length Control Register */ - register8_t RXPLCTRL; /* IrDA Receiver Pulse Length Control Register */ -} IRCOM_t; - -/* Event channel selection */ -typedef enum IRDA_EVSEL_enum -{ - IRDA_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ - IRDA_EVSEL_0_gc = (0x08<<0), /* Event Channel 0 */ - IRDA_EVSEL_1_gc = (0x09<<0), /* Event Channel 1 */ - IRDA_EVSEL_2_gc = (0x0A<<0), /* Event Channel 2 */ - IRDA_EVSEL_3_gc = (0x0B<<0), /* Event Channel 3 */ -} IRDA_EVSEL_t; - - -/* --------------------------------------------------------------------------- -LCD - LCD Controller --------------------------------------------------------------------------- -*/ - -/* LCD Controller */ -typedef struct LCD_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t CTRLC; /* Control Register C */ - register8_t INTCTRL; /* Interrupt Enable Register */ - register8_t INTFLAG; /* Interrupt Flag Register */ - register8_t CTRLD; /* Control Register D */ - register8_t CTRLE; /* Control Register E */ - register8_t CTRLF; /* Control Register F */ - register8_t CTRLG; /* Control Register G */ - register8_t CTRLH; /* Control Register H */ - register8_t reserved_0x0A; - register8_t reserved_0x0B; - register8_t reserved_0x0C; - register8_t reserved_0x0D; - register8_t reserved_0x0E; - register8_t reserved_0x0F; - register8_t DATA0; /* LCD Data Register 0 */ - register8_t DATA1; /* LCD Data Register 1 */ - register8_t DATA2; /* LCD Data Register 2 */ - register8_t DATA3; /* LCD Data Register 3 */ - register8_t DATA4; /* LCD Data Register 4 */ - register8_t DATA5; /* LCD Data Register 5 */ - register8_t DATA6; /* LCD Data Register 6 */ - register8_t DATA7; /* LCD Data Register 7 */ - register8_t DATA8; /* LCD Data Register 8 */ - register8_t DATA9; /* LCD Data Register 9 */ - register8_t DATA10; /* LCD Data Register 10 */ - register8_t DATA11; /* LCD Data Register 11 */ - register8_t DATA12; /* LCD Data Register 12 */ - register8_t DATA13; /* LCD Data Register 13 */ - register8_t DATA14; /* LCD Data Register 14 */ - register8_t DATA15; /* LCD Data Register 15 */ - register8_t DATA16; /* LCD Data Register 16 */ - register8_t DATA17; /* LCD Data Register 17 */ - register8_t DATA18; /* LCD Data Register 18 */ - register8_t DATA19; /* LCD Data Register 19 */ -} LCD_t; - -/* LCD Blink Rate */ -typedef enum LCD_BLINKRATE_enum -{ - LCD_BLINKRATE_4Hz_gc = (0x00<<0), /* 4Hz Blink Rate */ - LCD_BLINKRATE_2Hz_gc = (0x01<<0), /* 2Hz Blink Rate */ - LCD_BLINKRATE_1Hz_gc = (0x02<<0), /* 1Hz Blink Rate */ - LCD_BLINKRATE_0Hz5_gc = (0x03<<0), /* 0.5Hz Blink Rate */ -} LCD_BLINKRATE_t; - -/* LCD Clock Divide */ -typedef enum LCD_CLKDIV_enum -{ - LCD_CLKDIV_DivBy1_gc = (0x00<<4), /* frame rate of 256 Hz */ - LCD_CLKDIV_DivBy2_gc = (0x01<<4), /* frame rate of 128 Hz */ - LCD_CLKDIV_DivBy3_gc = (0x02<<4), /* frame rate of 83.5 Hz */ - LCD_CLKDIV_DivBy4_gc = (0x03<<4), /* frame rate of 64 Hz */ - LCD_CLKDIV_DivBy5_gc = (0x04<<4), /* frame rate of 51.2 Hz */ - LCD_CLKDIV_DivBy6_gc = (0x05<<4), /* frame rate of 42.7 Hz */ - LCD_CLKDIV_DivBy7_gc = (0x06<<4), /* frame rate of 36.6 Hz */ - LCD_CLKDIV_DivBy8_gc = (0x07<<4), /* frame rate of 32 Hz */ -} LCD_CLKDIV_t; - -/* Duty Select */ -typedef enum LCD_DUTY_enum -{ - LCD_DUTY_1_4_gc = (0x00<<0), /* Duty=1/4, Bias=1/3, COM0:3 */ - LCD_DUTY_Static_gc = (0x01<<0), /* Duty=Static, Bias=Static, COM0 */ - LCD_DUTY_1_2_gc = (0x02<<0), /* Duty=1/2, Bias=1/3, COM0:1 */ - LCD_DUTY_1_3_gc = (0x03<<0), /* Duty=1/3, Bias=1/3, COM0:2 */ -} LCD_DUTY_t; - -/* LCD Prescaler Select */ -typedef enum LCD_PRESC_enum -{ - LCD_PRESC_8_gc = (0x00<<7), /* clk_lcd/8 */ - LCD_PRESC_16_gc = (0x01<<7), /* clk_lcd/16 */ -} LCD_PRESC_t; - -/* Type of Digit */ -typedef enum LCD_TDG_enum -{ - LCD_TDG_7S_3C_gc = (0x00<<6), /* 7-segment with 3 COMs */ - LCD_TDG_7S_4C_gc = (0x01<<6), /* 7-segment with 4 COMs */ - LCD_TDG_14S_4C_gc = (0x02<<6), /* 14-segment with 4 COMs */ - LCD_TDG_16S_3C_gc = (0x03<<6), /* 16-segment with 3 COMs */ -} LCD_TDG_t; - - -/* --------------------------------------------------------------------------- -FUSE - Fuses and Lockbits --------------------------------------------------------------------------- -*/ - -/* Fuses */ -typedef struct NVM_FUSES_struct -{ - register8_t FUSEBYTE0; /* JTAG User ID */ - register8_t FUSEBYTE1; /* Watchdog Configuration */ - register8_t FUSEBYTE2; /* Reset Configuration */ - register8_t reserved_0x03; - register8_t FUSEBYTE4; /* Start-up Configuration */ - register8_t FUSEBYTE5; /* EESAVE and BOD Level */ -} NVM_FUSES_t; - -/* Boot Loader Section Reset Vector */ -typedef enum BOOTRST_enum -{ - BOOTRST_BOOTLDR_gc = (0x00<<6), /* Boot Loader Reset */ - BOOTRST_APPLICATION_gc = (0x01<<6), /* Application Reset */ -} BOOTRST_t; - -/* Timer Oscillator pin location */ -typedef enum TOSCSEL_enum -{ - TOSCSEL_ALTERNATE_gc = (0x00<<5), /* TOSC1 / TOSC2 on separate pins */ - TOSCSEL_XTAL_gc = (0x01<<5), /* TOSC1 / TOSC2 shared with XTAL1 / XTAL2 */ -} TOSCSEL_t; - -/* BOD operation */ -typedef enum BOD_enum -{ - BOD_SAMPLED_gc = (0x01<<0), /* BOD enabled in sampled mode */ - BOD_CONTINUOUS_gc = (0x02<<0), /* BOD enabled continuously */ - BOD_DISABLED_gc = (0x03<<0), /* BOD Disabled */ -} BOD_t; - -/* BOD operation */ -typedef enum BODACT_enum -{ - BODACT_SAMPLED_gc = (0x01<<4), /* BOD enabled in sampled mode */ - BODACT_CONTINUOUS_gc = (0x02<<4), /* BOD enabled continuously */ - BODACT_DISABLED_gc = (0x03<<4), /* BOD Disabled */ -} BODACT_t; - -/* Watchdog (Window) Timeout Period */ -typedef enum WD_enum -{ - WD_8CLK_gc = (0x00<<4), /* 8 cycles (8ms @ 3.3V) */ - WD_16CLK_gc = (0x01<<4), /* 16 cycles (16ms @ 3.3V) */ - WD_32CLK_gc = (0x02<<4), /* 32 cycles (32ms @ 3.3V) */ - WD_64CLK_gc = (0x03<<4), /* 64 cycles (64ms @ 3.3V) */ - WD_128CLK_gc = (0x04<<4), /* 128 cycles (0.125s @ 3.3V) */ - WD_256CLK_gc = (0x05<<4), /* 256 cycles (0.25s @ 3.3V) */ - WD_512CLK_gc = (0x06<<4), /* 512 cycles (0.5s @ 3.3V) */ - WD_1KCLK_gc = (0x07<<4), /* 1K cycles (1s @ 3.3V) */ - WD_2KCLK_gc = (0x08<<4), /* 2K cycles (2s @ 3.3V) */ - WD_4KCLK_gc = (0x09<<4), /* 4K cycles (4s @ 3.3V) */ - WD_8KCLK_gc = (0x0A<<4), /* 8K cycles (8s @ 3.3V) */ -} WD_t; - -/* Watchdog (Window) Timeout Period */ -typedef enum WDP_enum -{ - WDP_8CLK_gc = (0x00<<0), /* 8 cycles (8ms @ 3.3V) */ - WDP_16CLK_gc = (0x01<<0), /* 16 cycles (16ms @ 3.3V) */ - WDP_32CLK_gc = (0x02<<0), /* 32 cycles (32ms @ 3.3V) */ - WDP_64CLK_gc = (0x03<<0), /* 64 cycles (64ms @ 3.3V) */ - WDP_128CLK_gc = (0x04<<0), /* 128 cycles (0.125s @ 3.3V) */ - WDP_256CLK_gc = (0x05<<0), /* 256 cycles (0.25s @ 3.3V) */ - WDP_512CLK_gc = (0x06<<0), /* 512 cycles (0.5s @ 3.3V) */ - WDP_1KCLK_gc = (0x07<<0), /* 1K cycles (1s @ 3.3V) */ - WDP_2KCLK_gc = (0x08<<0), /* 2K cycles (2s @ 3.3V) */ - WDP_4KCLK_gc = (0x09<<0), /* 4K cycles (4s @ 3.3V) */ - WDP_8KCLK_gc = (0x0A<<0), /* 8K cycles (8s @ 3.3V) */ -} WDP_t; - -/* Start-up Time */ -typedef enum SUT_enum -{ - SUT_0MS_gc = (0x03<<2), /* 0 ms */ - SUT_4MS_gc = (0x01<<2), /* 4 ms */ - SUT_64MS_gc = (0x00<<2), /* 64 ms */ -} SUT_t; - -/* Brownout Detection Voltage Level */ -typedef enum BODLVL_enum -{ - BODLVL_1V6_gc = (0x07<<0), /* 1.6 V */ - BODLVL_1V8_gc = (0x06<<0), /* 1.8 V */ - BODLVL_2V0_gc = (0x05<<0), /* 2.0 V */ - BODLVL_2V2_gc = (0x04<<0), /* 2.2 V */ - BODLVL_2V4_gc = (0x03<<0), /* 2.4 V */ - BODLVL_2V6_gc = (0x02<<0), /* 2.6 V */ - BODLVL_2V8_gc = (0x01<<0), /* 2.8 V */ - BODLVL_3V0_gc = (0x00<<0), /* 3.0 V */ -} BODLVL_t; - - -/* --------------------------------------------------------------------------- -LOCKBIT - Fuses and Lockbits --------------------------------------------------------------------------- -*/ - -/* Lock Bits */ -typedef struct NVM_LOCKBITS_struct -{ - register8_t LOCK_BITS; /* Lock Bits (Changed from LOCKBITS to avoid avr-libc collision) */ -} NVM_LOCKBITS_t; - -/* Boot lock bits - boot setcion */ -typedef enum FUSE_BLBB_enum -{ - FUSE_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ - FUSE_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ - FUSE_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ - FUSE_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ -} FUSE_BLBB_t; - -/* Boot lock bits - application section */ -typedef enum FUSE_BLBA_enum -{ - FUSE_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ - FUSE_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ - FUSE_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ - FUSE_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ -} FUSE_BLBA_t; - -/* Boot lock bits - application table section */ -typedef enum FUSE_BLBAT_enum -{ - FUSE_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ - FUSE_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ - FUSE_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ - FUSE_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ -} FUSE_BLBAT_t; - -/* Lock bits */ -typedef enum FUSE_LB_enum -{ - FUSE_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ - FUSE_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ - FUSE_LB_NOLOCK_gc = (0x03<<0), /* No locks */ -} FUSE_LB_t; - - -/* --------------------------------------------------------------------------- -SIGROW - Signature Row --------------------------------------------------------------------------- -*/ - -/* Production Signatures */ -typedef struct NVM_PROD_SIGNATURES_struct -{ - register8_t RCOSC2M; /* RCOSC 2 MHz Calibration Value B */ - register8_t RCOSC2MA; /* RCOSC 2 MHz Calibration Value A */ - register8_t RCOSC32K; /* RCOSC 32.768 kHz Calibration Value */ - register8_t RCOSC32M; /* RCOSC 32 MHz Calibration Value B */ - register8_t RCOSC32MA; /* RCOSC 32 MHz Calibration Value A */ - register8_t reserved_0x05; - register8_t reserved_0x06; - register8_t reserved_0x07; - register8_t LOTNUM0; /* Lot Number Byte 0, ASCII */ - register8_t LOTNUM1; /* Lot Number Byte 1, ASCII */ - register8_t LOTNUM2; /* Lot Number Byte 2, ASCII */ - register8_t LOTNUM3; /* Lot Number Byte 3, ASCII */ - register8_t LOTNUM4; /* Lot Number Byte 4, ASCII */ - register8_t LOTNUM5; /* Lot Number Byte 5, ASCII */ - register8_t reserved_0x0E; - register8_t reserved_0x0F; - register8_t WAFNUM; /* Wafer Number */ - register8_t reserved_0x11; - register8_t COORDX0; /* Wafer Coordinate X Byte 0 */ - register8_t COORDX1; /* Wafer Coordinate X Byte 1 */ - register8_t COORDY0; /* Wafer Coordinate Y Byte 0 */ - register8_t COORDY1; /* Wafer Coordinate Y Byte 1 */ - register8_t reserved_0x16; - register8_t reserved_0x17; - register8_t reserved_0x18; - register8_t reserved_0x19; - register8_t USBCAL0; /* USB Calibration Byte 0 */ - register8_t USBCAL1; /* USB Calibration Byte 1 */ - register8_t USBRCOSC; /* USB RCOSC Calibration Value B */ - register8_t USBRCOSCA; /* USB RCOSC Calibration Value A */ - register8_t reserved_0x1E; - register8_t reserved_0x1F; - register8_t ADCACAL0; /* ADCA Calibration Byte 0 */ - register8_t ADCACAL1; /* ADCA Calibration Byte 1 */ - register8_t reserved_0x22; - register8_t reserved_0x23; - register8_t ADCBCAL0; /* ADCB Calibration Byte 0 */ - register8_t ADCBCAL1; /* ADCB Calibration Byte 1 */ - register8_t reserved_0x26; - register8_t reserved_0x27; - register8_t reserved_0x28; - register8_t reserved_0x29; - register8_t reserved_0x2A; - register8_t reserved_0x2B; - register8_t reserved_0x2C; - register8_t reserved_0x2D; - register8_t TEMPSENSE0; /* Temperature Sensor Calibration Byte 0 */ - register8_t TEMPSENSE1; /* Temperature Sensor Calibration Byte 1 */ - register8_t reserved_0x30; - register8_t reserved_0x31; - register8_t reserved_0x32; - register8_t reserved_0x33; - register8_t reserved_0x34; - register8_t reserved_0x35; - register8_t reserved_0x36; - register8_t reserved_0x37; - register8_t reserved_0x38; - register8_t reserved_0x39; - register8_t reserved_0x3A; - register8_t reserved_0x3B; - register8_t reserved_0x3C; - register8_t reserved_0x3D; - register8_t reserved_0x3E; - register8_t reserved_0x3F; - register8_t reserved_0x40; - register8_t reserved_0x41; - register8_t reserved_0x42; - register8_t reserved_0x43; - register8_t reserved_0x44; - register8_t reserved_0x45; - register8_t reserved_0x46; - register8_t reserved_0x47; -} NVM_PROD_SIGNATURES_t; - -/* -========================================================================== -IO Module Instances. Mapped to memory. -========================================================================== -*/ - -#define VPORT0 (*(VPORT_t *) 0x0010) /* Virtual Port */ -#define VPORT1 (*(VPORT_t *) 0x0014) /* Virtual Port */ -#define VPORT2 (*(VPORT_t *) 0x0018) /* Virtual Port */ -#define VPORT3 (*(VPORT_t *) 0x001C) /* Virtual Port */ -#define OCD (*(OCD_t *) 0x002E) /* On-Chip Debug System */ -#define CLK (*(CLK_t *) 0x0040) /* Clock System */ -#define SLEEP (*(SLEEP_t *) 0x0048) /* Sleep Controller */ -#define OSC (*(OSC_t *) 0x0050) /* Oscillator */ -#define DFLLRC32M (*(DFLL_t *) 0x0060) /* DFLL */ -#define DFLLRC2M (*(DFLL_t *) 0x0068) /* DFLL */ -#define PR (*(PR_t *) 0x0070) /* Power Reduction */ -#define RST (*(RST_t *) 0x0078) /* Reset */ -#define WDT (*(WDT_t *) 0x0080) /* Watch-Dog Timer */ -#define MCU (*(MCU_t *) 0x0090) /* MCU Control */ -#define PMIC (*(PMIC_t *) 0x00A0) /* Programmable Multi-level Interrupt Controller */ -#define PORTCFG (*(PORTCFG_t *) 0x00B0) /* I/O port Configuration */ -#define AES (*(AES_t *) 0x00C0) /* AES Module */ -#define CRC (*(CRC_t *) 0x00D0) /* Cyclic Redundancy Checker */ -#define DMA (*(DMA_t *) 0x0100) /* DMA Controller */ -#define EVSYS (*(EVSYS_t *) 0x0180) /* Event System */ -#define NVM (*(NVM_t *) 0x01C0) /* Non-volatile Memory Controller */ -#define ADCB (*(ADC_t *) 0x0240) /* Analog-to-Digital Converter */ -#define ACB (*(AC_t *) 0x0390) /* Analog Comparator */ -#define RTC (*(RTC_t *) 0x0400) /* Real-Time Counter */ -#define TWIC (*(TWI_t *) 0x0480) /* Two-Wire Interface */ -#define USB (*(USB_t *) 0x04C0) /* Universal Serial Bus */ -#define PORTB (*(PORT_t *) 0x0620) /* I/O Ports */ -#define PORTC (*(PORT_t *) 0x0640) /* I/O Ports */ -#define PORTD (*(PORT_t *) 0x0660) /* I/O Ports */ -#define PORTG (*(PORT_t *) 0x06C0) /* I/O Ports */ -#define PORTM (*(PORT_t *) 0x0760) /* I/O Ports */ -#define PORTR (*(PORT_t *) 0x07E0) /* I/O Ports */ -#define TCC0 (*(TC0_t *) 0x0800) /* 16-bit Timer/Counter 0 */ -#define TCC1 (*(TC1_t *) 0x0840) /* 16-bit Timer/Counter 1 */ -#define AWEXC (*(AWEX_t *) 0x0880) /* Advanced Waveform Extension */ -#define HIRESC (*(HIRES_t *) 0x0890) /* High-Resolution Extension */ -#define USARTC0 (*(USART_t *) 0x08A0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ -#define SPIC (*(SPI_t *) 0x08C0) /* Serial Peripheral Interface */ -#define IRCOM (*(IRCOM_t *) 0x08F8) /* IR Communication Module */ -#define LCD (*(LCD_t *) 0x0D00) /* LCD Controller */ - - -#endif /* !defined (__ASSEMBLER__) */ - - -/* ========== Flattened fully qualified IO register names ========== */ - -/* GPIO - General Purpose IO Registers */ -#define GPIO_GPIOR0 _SFR_MEM8(0x0000) -#define GPIO_GPIOR1 _SFR_MEM8(0x0001) -#define GPIO_GPIOR2 _SFR_MEM8(0x0002) -#define GPIO_GPIOR3 _SFR_MEM8(0x0003) - -/* Deprecated */ -#define GPIO_GPIO0 _SFR_MEM8(0x0000) -#define GPIO_GPIO1 _SFR_MEM8(0x0001) -#define GPIO_GPIO2 _SFR_MEM8(0x0002) -#define GPIO_GPIO3 _SFR_MEM8(0x0003) - -/* NVM_FUSES - Fuses */ -#define FUSE_FUSEBYTE0 _SFR_MEM8(0x0000) -#define FUSE_FUSEBYTE1 _SFR_MEM8(0x0001) -#define FUSE_FUSEBYTE2 _SFR_MEM8(0x0002) -#define FUSE_FUSEBYTE4 _SFR_MEM8(0x0004) -#define FUSE_FUSEBYTE5 _SFR_MEM8(0x0005) - -/* NVM_LOCKBITS - Lock Bits */ -#define LOCKBIT_LOCKBITS _SFR_MEM8(0x0000) - -/* NVM_PROD_SIGNATURES - Production Signatures */ -#define PRODSIGNATURES_RCOSC2M _SFR_MEM8(0x0000) -#define PRODSIGNATURES_RCOSC2MA _SFR_MEM8(0x0001) -#define PRODSIGNATURES_RCOSC32K _SFR_MEM8(0x0002) -#define PRODSIGNATURES_RCOSC32M _SFR_MEM8(0x0003) -#define PRODSIGNATURES_RCOSC32MA _SFR_MEM8(0x0004) -#define PRODSIGNATURES_LOTNUM0 _SFR_MEM8(0x0008) -#define PRODSIGNATURES_LOTNUM1 _SFR_MEM8(0x0009) -#define PRODSIGNATURES_LOTNUM2 _SFR_MEM8(0x000A) -#define PRODSIGNATURES_LOTNUM3 _SFR_MEM8(0x000B) -#define PRODSIGNATURES_LOTNUM4 _SFR_MEM8(0x000C) -#define PRODSIGNATURES_LOTNUM5 _SFR_MEM8(0x000D) -#define PRODSIGNATURES_WAFNUM _SFR_MEM8(0x0010) -#define PRODSIGNATURES_COORDX0 _SFR_MEM8(0x0012) -#define PRODSIGNATURES_COORDX1 _SFR_MEM8(0x0013) -#define PRODSIGNATURES_COORDY0 _SFR_MEM8(0x0014) -#define PRODSIGNATURES_COORDY1 _SFR_MEM8(0x0015) -#define PRODSIGNATURES_USBCAL0 _SFR_MEM8(0x001A) -#define PRODSIGNATURES_USBCAL1 _SFR_MEM8(0x001B) -#define PRODSIGNATURES_USBRCOSC _SFR_MEM8(0x001C) -#define PRODSIGNATURES_USBRCOSCA _SFR_MEM8(0x001D) -#define PRODSIGNATURES_ADCACAL0 _SFR_MEM8(0x0020) -#define PRODSIGNATURES_ADCACAL1 _SFR_MEM8(0x0021) -#define PRODSIGNATURES_ADCBCAL0 _SFR_MEM8(0x0024) -#define PRODSIGNATURES_ADCBCAL1 _SFR_MEM8(0x0025) -#define PRODSIGNATURES_TEMPSENSE0 _SFR_MEM8(0x002E) -#define PRODSIGNATURES_TEMPSENSE1 _SFR_MEM8(0x002F) - -/* VPORT - Virtual Port */ -#define VPORT0_DIR _SFR_MEM8(0x0010) -#define VPORT0_OUT _SFR_MEM8(0x0011) -#define VPORT0_IN _SFR_MEM8(0x0012) -#define VPORT0_INTFLAGS _SFR_MEM8(0x0013) - -/* VPORT - Virtual Port */ -#define VPORT1_DIR _SFR_MEM8(0x0014) -#define VPORT1_OUT _SFR_MEM8(0x0015) -#define VPORT1_IN _SFR_MEM8(0x0016) -#define VPORT1_INTFLAGS _SFR_MEM8(0x0017) - -/* VPORT - Virtual Port */ -#define VPORT2_DIR _SFR_MEM8(0x0018) -#define VPORT2_OUT _SFR_MEM8(0x0019) -#define VPORT2_IN _SFR_MEM8(0x001A) -#define VPORT2_INTFLAGS _SFR_MEM8(0x001B) - -/* VPORT - Virtual Port */ -#define VPORT3_DIR _SFR_MEM8(0x001C) -#define VPORT3_OUT _SFR_MEM8(0x001D) -#define VPORT3_IN _SFR_MEM8(0x001E) -#define VPORT3_INTFLAGS _SFR_MEM8(0x001F) - -/* OCD - On-Chip Debug System */ -#define OCD_OCDR0 _SFR_MEM8(0x002E) -#define OCD_OCDR1 _SFR_MEM8(0x002F) - -/* CPU - CPU registers */ -#define CPU_CCP _SFR_MEM8(0x0034) -#define CPU_RAMPD _SFR_MEM8(0x0038) -#define CPU_RAMPX _SFR_MEM8(0x0039) -#define CPU_RAMPY _SFR_MEM8(0x003A) -#define CPU_RAMPZ _SFR_MEM8(0x003B) -#define CPU_EIND _SFR_MEM8(0x003C) -#define CPU_SPL _SFR_MEM8(0x003D) -#define CPU_SPH _SFR_MEM8(0x003E) -#define CPU_SREG _SFR_MEM8(0x003F) - -/* CLK - Clock System */ -#define CLK_CTRL _SFR_MEM8(0x0040) -#define CLK_PSCTRL _SFR_MEM8(0x0041) -#define CLK_LOCK _SFR_MEM8(0x0042) -#define CLK_RTCCTRL _SFR_MEM8(0x0043) -#define CLK_USBCTRL _SFR_MEM8(0x0044) - -/* SLEEP - Sleep Controller */ -#define SLEEP_CTRL _SFR_MEM8(0x0048) - -/* OSC - Oscillator */ -#define OSC_CTRL _SFR_MEM8(0x0050) -#define OSC_STATUS _SFR_MEM8(0x0051) -#define OSC_XOSCCTRL _SFR_MEM8(0x0052) -#define OSC_XOSCFAIL _SFR_MEM8(0x0053) -#define OSC_RC32KCAL _SFR_MEM8(0x0054) -#define OSC_PLLCTRL _SFR_MEM8(0x0055) -#define OSC_DFLLCTRL _SFR_MEM8(0x0056) - -/* DFLL - DFLL */ -#define DFLLRC32M_CTRL _SFR_MEM8(0x0060) -#define DFLLRC32M_CALA _SFR_MEM8(0x0062) -#define DFLLRC32M_CALB _SFR_MEM8(0x0063) -#define DFLLRC32M_COMP0 _SFR_MEM8(0x0064) -#define DFLLRC32M_COMP1 _SFR_MEM8(0x0065) -#define DFLLRC32M_COMP2 _SFR_MEM8(0x0066) - -/* DFLL - DFLL */ -#define DFLLRC2M_CTRL _SFR_MEM8(0x0068) -#define DFLLRC2M_CALA _SFR_MEM8(0x006A) -#define DFLLRC2M_CALB _SFR_MEM8(0x006B) -#define DFLLRC2M_COMP0 _SFR_MEM8(0x006C) -#define DFLLRC2M_COMP1 _SFR_MEM8(0x006D) -#define DFLLRC2M_COMP2 _SFR_MEM8(0x006E) - -/* PR - Power Reduction */ -#define PR_PRGEN _SFR_MEM8(0x0070) -#define PR_PRPA _SFR_MEM8(0x0071) -#define PR_PRPB _SFR_MEM8(0x0072) -#define PR_PRPC _SFR_MEM8(0x0073) -#define PR_PRPE _SFR_MEM8(0x0075) - -/* RST - Reset */ -#define RST_STATUS _SFR_MEM8(0x0078) -#define RST_CTRL _SFR_MEM8(0x0079) - -/* WDT - Watch-Dog Timer */ -#define WDT_CTRL _SFR_MEM8(0x0080) -#define WDT_WINCTRL _SFR_MEM8(0x0081) -#define WDT_STATUS _SFR_MEM8(0x0082) - -/* MCU - MCU Control */ -#define MCU_DEVID0 _SFR_MEM8(0x0090) -#define MCU_DEVID1 _SFR_MEM8(0x0091) -#define MCU_DEVID2 _SFR_MEM8(0x0092) -#define MCU_REVID _SFR_MEM8(0x0093) -#define MCU_JTAGUID _SFR_MEM8(0x0094) -#define MCU_MCUCR _SFR_MEM8(0x0096) -#define MCU_ANAINIT _SFR_MEM8(0x0097) -#define MCU_EVSYSLOCK _SFR_MEM8(0x0098) -#define MCU_AWEXLOCK _SFR_MEM8(0x0099) - -/* PMIC - Programmable Multi-level Interrupt Controller */ -#define PMIC_STATUS _SFR_MEM8(0x00A0) -#define PMIC_INTPRI _SFR_MEM8(0x00A1) -#define PMIC_CTRL _SFR_MEM8(0x00A2) - -/* PORTCFG - I/O port Configuration */ -#define PORTCFG_MPCMASK _SFR_MEM8(0x00B0) -#define PORTCFG_VPCTRLA _SFR_MEM8(0x00B2) -#define PORTCFG_VPCTRLB _SFR_MEM8(0x00B3) -#define PORTCFG_CLKEVOUT _SFR_MEM8(0x00B4) -#define PORTCFG_EVOUTSEL _SFR_MEM8(0x00B6) - -/* AES - AES Module */ -#define AES_CTRL _SFR_MEM8(0x00C0) -#define AES_STATUS _SFR_MEM8(0x00C1) -#define AES_STATE _SFR_MEM8(0x00C2) -#define AES_KEY _SFR_MEM8(0x00C3) -#define AES_INTCTRL _SFR_MEM8(0x00C4) - -/* CRC - Cyclic Redundancy Checker */ -#define CRC_CTRL _SFR_MEM8(0x00D0) -#define CRC_STATUS _SFR_MEM8(0x00D1) -#define CRC_DATAIN _SFR_MEM8(0x00D3) -#define CRC_CHECKSUM0 _SFR_MEM8(0x00D4) -#define CRC_CHECKSUM1 _SFR_MEM8(0x00D5) -#define CRC_CHECKSUM2 _SFR_MEM8(0x00D6) -#define CRC_CHECKSUM3 _SFR_MEM8(0x00D7) - -/* DMA - DMA Controller */ -#define DMA_CTRL _SFR_MEM8(0x0100) -#define DMA_INTFLAGS _SFR_MEM8(0x0103) -#define DMA_STATUS _SFR_MEM8(0x0104) -#define DMA_TEMP _SFR_MEM16(0x0106) -#define DMA_CH0_CTRLA _SFR_MEM8(0x0110) -#define DMA_CH0_CTRLB _SFR_MEM8(0x0111) -#define DMA_CH0_ADDRCTRL _SFR_MEM8(0x0112) -#define DMA_CH0_TRIGSRC _SFR_MEM8(0x0113) -#define DMA_CH0_TRFCNT _SFR_MEM16(0x0114) -#define DMA_CH0_REPCNT _SFR_MEM8(0x0116) -#define DMA_CH0_SRCADDR0 _SFR_MEM8(0x0118) -#define DMA_CH0_SRCADDR1 _SFR_MEM8(0x0119) -#define DMA_CH0_DESTADDR0 _SFR_MEM8(0x011C) -#define DMA_CH0_DESTADDR1 _SFR_MEM8(0x011D) -#define DMA_CH1_CTRLA _SFR_MEM8(0x0120) -#define DMA_CH1_CTRLB _SFR_MEM8(0x0121) -#define DMA_CH1_ADDRCTRL _SFR_MEM8(0x0122) -#define DMA_CH1_TRIGSRC _SFR_MEM8(0x0123) -#define DMA_CH1_TRFCNT _SFR_MEM16(0x0124) -#define DMA_CH1_REPCNT _SFR_MEM8(0x0126) -#define DMA_CH1_SRCADDR0 _SFR_MEM8(0x0128) -#define DMA_CH1_SRCADDR1 _SFR_MEM8(0x0129) -#define DMA_CH1_DESTADDR0 _SFR_MEM8(0x012C) -#define DMA_CH1_DESTADDR1 _SFR_MEM8(0x012D) - -/* EVSYS - Event System */ -#define EVSYS_CH0MUX _SFR_MEM8(0x0180) -#define EVSYS_CH1MUX _SFR_MEM8(0x0181) -#define EVSYS_CH2MUX _SFR_MEM8(0x0182) -#define EVSYS_CH3MUX _SFR_MEM8(0x0183) -#define EVSYS_CH0CTRL _SFR_MEM8(0x0188) -#define EVSYS_CH1CTRL _SFR_MEM8(0x0189) -#define EVSYS_CH2CTRL _SFR_MEM8(0x018A) -#define EVSYS_CH3CTRL _SFR_MEM8(0x018B) -#define EVSYS_STROBE _SFR_MEM8(0x0190) -#define EVSYS_DATA _SFR_MEM8(0x0191) - -/* NVM - Non-volatile Memory Controller */ -#define NVM_ADDR0 _SFR_MEM8(0x01C0) -#define NVM_ADDR1 _SFR_MEM8(0x01C1) -#define NVM_ADDR2 _SFR_MEM8(0x01C2) -#define NVM_DATA0 _SFR_MEM8(0x01C4) -#define NVM_DATA1 _SFR_MEM8(0x01C5) -#define NVM_DATA2 _SFR_MEM8(0x01C6) -#define NVM_CMD _SFR_MEM8(0x01CA) -#define NVM_CTRLA _SFR_MEM8(0x01CB) -#define NVM_CTRLB _SFR_MEM8(0x01CC) -#define NVM_INTCTRL _SFR_MEM8(0x01CD) -#define NVM_STATUS _SFR_MEM8(0x01CF) -#define NVM_LOCKBITS _SFR_MEM8(0x01D0) - -/* ADC - Analog-to-Digital Converter */ -#define ADCB_CTRLA _SFR_MEM8(0x0240) -#define ADCB_CTRLB _SFR_MEM8(0x0241) -#define ADCB_REFCTRL _SFR_MEM8(0x0242) -#define ADCB_EVCTRL _SFR_MEM8(0x0243) -#define ADCB_PRESCALER _SFR_MEM8(0x0244) -#define ADCB_INTFLAGS _SFR_MEM8(0x0246) -#define ADCB_TEMP _SFR_MEM8(0x0247) -#define ADCB_SAMPCTRL _SFR_MEM8(0x0248) -#define ADCB_CAL _SFR_MEM16(0x024C) -#define ADCB_CH0RES _SFR_MEM16(0x0250) -#define ADCB_CMP _SFR_MEM16(0x0258) -#define ADCB_CH0_CTRL _SFR_MEM8(0x0260) -#define ADCB_CH0_MUXCTRL _SFR_MEM8(0x0261) -#define ADCB_CH0_INTCTRL _SFR_MEM8(0x0262) -#define ADCB_CH0_INTFLAGS _SFR_MEM8(0x0263) -#define ADCB_CH0_RES _SFR_MEM16(0x0264) -#define ADCB_CH0_SCAN _SFR_MEM8(0x0266) - -/* AC - Analog Comparator */ -#define ACB_AC0CTRL _SFR_MEM8(0x0390) -#define ACB_AC1CTRL _SFR_MEM8(0x0391) -#define ACB_AC0MUXCTRL _SFR_MEM8(0x0392) -#define ACB_AC1MUXCTRL _SFR_MEM8(0x0393) -#define ACB_CTRLA _SFR_MEM8(0x0394) -#define ACB_CTRLB _SFR_MEM8(0x0395) -#define ACB_WINCTRL _SFR_MEM8(0x0396) -#define ACB_STATUS _SFR_MEM8(0x0397) -#define ACB_CURRCTRL _SFR_MEM8(0x0398) -#define ACB_CURRCALIB _SFR_MEM8(0x0399) - -/* RTC - Real-Time Counter */ -#define RTC_CTRL _SFR_MEM8(0x0400) -#define RTC_STATUS _SFR_MEM8(0x0401) -#define RTC_INTCTRL _SFR_MEM8(0x0402) -#define RTC_INTFLAGS _SFR_MEM8(0x0403) -#define RTC_TEMP _SFR_MEM8(0x0404) -#define RTC_CNT _SFR_MEM16(0x0408) -#define RTC_PER _SFR_MEM16(0x040A) -#define RTC_COMP _SFR_MEM16(0x040C) - -/* TWI - Two-Wire Interface */ -#define TWIC_CTRL _SFR_MEM8(0x0480) -#define TWIC_MASTER_CTRLA _SFR_MEM8(0x0481) -#define TWIC_MASTER_CTRLB _SFR_MEM8(0x0482) -#define TWIC_MASTER_CTRLC _SFR_MEM8(0x0483) -#define TWIC_MASTER_STATUS _SFR_MEM8(0x0484) -#define TWIC_MASTER_BAUD _SFR_MEM8(0x0485) -#define TWIC_MASTER_ADDR _SFR_MEM8(0x0486) -#define TWIC_MASTER_DATA _SFR_MEM8(0x0487) -#define TWIC_SLAVE_CTRLA _SFR_MEM8(0x0488) -#define TWIC_SLAVE_CTRLB _SFR_MEM8(0x0489) -#define TWIC_SLAVE_STATUS _SFR_MEM8(0x048A) -#define TWIC_SLAVE_ADDR _SFR_MEM8(0x048B) -#define TWIC_SLAVE_DATA _SFR_MEM8(0x048C) -#define TWIC_SLAVE_ADDRMASK _SFR_MEM8(0x048D) - -/* USB - Universal Serial Bus */ -#define USB_CTRLA _SFR_MEM8(0x04C0) -#define USB_CTRLB _SFR_MEM8(0x04C1) -#define USB_STATUS _SFR_MEM8(0x04C2) -#define USB_ADDR _SFR_MEM8(0x04C3) -#define USB_FIFOWP _SFR_MEM8(0x04C4) -#define USB_FIFORP _SFR_MEM8(0x04C5) -#define USB_EPPTR _SFR_MEM16(0x04C6) -#define USB_INTCTRLA _SFR_MEM8(0x04C8) -#define USB_INTCTRLB _SFR_MEM8(0x04C9) -#define USB_INTFLAGSACLR _SFR_MEM8(0x04CA) -#define USB_INTFLAGSASET _SFR_MEM8(0x04CB) -#define USB_INTFLAGSBCLR _SFR_MEM8(0x04CC) -#define USB_INTFLAGSBSET _SFR_MEM8(0x04CD) -#define USB_CAL0 _SFR_MEM8(0x04FA) -#define USB_CAL1 _SFR_MEM8(0x04FB) - -/* PORT - I/O Ports */ -#define PORTB_DIR _SFR_MEM8(0x0620) -#define PORTB_DIRSET _SFR_MEM8(0x0621) -#define PORTB_DIRCLR _SFR_MEM8(0x0622) -#define PORTB_DIRTGL _SFR_MEM8(0x0623) -#define PORTB_OUT _SFR_MEM8(0x0624) -#define PORTB_OUTSET _SFR_MEM8(0x0625) -#define PORTB_OUTCLR _SFR_MEM8(0x0626) -#define PORTB_OUTTGL _SFR_MEM8(0x0627) -#define PORTB_IN _SFR_MEM8(0x0628) -#define PORTB_INTCTRL _SFR_MEM8(0x0629) -#define PORTB_INT0MASK _SFR_MEM8(0x062A) -#define PORTB_INT1MASK _SFR_MEM8(0x062B) -#define PORTB_INTFLAGS _SFR_MEM8(0x062C) -#define PORTB_REMAP _SFR_MEM8(0x062E) -#define PORTB_PIN0CTRL _SFR_MEM8(0x0630) -#define PORTB_PIN1CTRL _SFR_MEM8(0x0631) -#define PORTB_PIN2CTRL _SFR_MEM8(0x0632) -#define PORTB_PIN3CTRL _SFR_MEM8(0x0633) -#define PORTB_PIN4CTRL _SFR_MEM8(0x0634) -#define PORTB_PIN5CTRL _SFR_MEM8(0x0635) -#define PORTB_PIN6CTRL _SFR_MEM8(0x0636) -#define PORTB_PIN7CTRL _SFR_MEM8(0x0637) - -/* PORT - I/O Ports */ -#define PORTC_DIR _SFR_MEM8(0x0640) -#define PORTC_DIRSET _SFR_MEM8(0x0641) -#define PORTC_DIRCLR _SFR_MEM8(0x0642) -#define PORTC_DIRTGL _SFR_MEM8(0x0643) -#define PORTC_OUT _SFR_MEM8(0x0644) -#define PORTC_OUTSET _SFR_MEM8(0x0645) -#define PORTC_OUTCLR _SFR_MEM8(0x0646) -#define PORTC_OUTTGL _SFR_MEM8(0x0647) -#define PORTC_IN _SFR_MEM8(0x0648) -#define PORTC_INTCTRL _SFR_MEM8(0x0649) -#define PORTC_INT0MASK _SFR_MEM8(0x064A) -#define PORTC_INT1MASK _SFR_MEM8(0x064B) -#define PORTC_INTFLAGS _SFR_MEM8(0x064C) -#define PORTC_REMAP _SFR_MEM8(0x064E) -#define PORTC_PIN0CTRL _SFR_MEM8(0x0650) -#define PORTC_PIN1CTRL _SFR_MEM8(0x0651) -#define PORTC_PIN2CTRL _SFR_MEM8(0x0652) -#define PORTC_PIN3CTRL _SFR_MEM8(0x0653) -#define PORTC_PIN4CTRL _SFR_MEM8(0x0654) -#define PORTC_PIN5CTRL _SFR_MEM8(0x0655) -#define PORTC_PIN6CTRL _SFR_MEM8(0x0656) -#define PORTC_PIN7CTRL _SFR_MEM8(0x0657) - -/* PORT - I/O Ports */ -#define PORTD_DIR _SFR_MEM8(0x0660) -#define PORTD_DIRSET _SFR_MEM8(0x0661) -#define PORTD_DIRCLR _SFR_MEM8(0x0662) -#define PORTD_DIRTGL _SFR_MEM8(0x0663) -#define PORTD_OUT _SFR_MEM8(0x0664) -#define PORTD_OUTSET _SFR_MEM8(0x0665) -#define PORTD_OUTCLR _SFR_MEM8(0x0666) -#define PORTD_OUTTGL _SFR_MEM8(0x0667) -#define PORTD_IN _SFR_MEM8(0x0668) -#define PORTD_INTCTRL _SFR_MEM8(0x0669) -#define PORTD_INT0MASK _SFR_MEM8(0x066A) -#define PORTD_INT1MASK _SFR_MEM8(0x066B) -#define PORTD_INTFLAGS _SFR_MEM8(0x066C) -#define PORTD_REMAP _SFR_MEM8(0x066E) -#define PORTD_PIN0CTRL _SFR_MEM8(0x0670) -#define PORTD_PIN1CTRL _SFR_MEM8(0x0671) -#define PORTD_PIN2CTRL _SFR_MEM8(0x0672) -#define PORTD_PIN3CTRL _SFR_MEM8(0x0673) -#define PORTD_PIN4CTRL _SFR_MEM8(0x0674) -#define PORTD_PIN5CTRL _SFR_MEM8(0x0675) -#define PORTD_PIN6CTRL _SFR_MEM8(0x0676) -#define PORTD_PIN7CTRL _SFR_MEM8(0x0677) - -/* PORT - I/O Ports */ -#define PORTG_DIR _SFR_MEM8(0x06C0) -#define PORTG_DIRSET _SFR_MEM8(0x06C1) -#define PORTG_DIRCLR _SFR_MEM8(0x06C2) -#define PORTG_DIRTGL _SFR_MEM8(0x06C3) -#define PORTG_OUT _SFR_MEM8(0x06C4) -#define PORTG_OUTSET _SFR_MEM8(0x06C5) -#define PORTG_OUTCLR _SFR_MEM8(0x06C6) -#define PORTG_OUTTGL _SFR_MEM8(0x06C7) -#define PORTG_IN _SFR_MEM8(0x06C8) -#define PORTG_INTCTRL _SFR_MEM8(0x06C9) -#define PORTG_INT0MASK _SFR_MEM8(0x06CA) -#define PORTG_INT1MASK _SFR_MEM8(0x06CB) -#define PORTG_INTFLAGS _SFR_MEM8(0x06CC) -#define PORTG_REMAP _SFR_MEM8(0x06CE) -#define PORTG_PIN0CTRL _SFR_MEM8(0x06D0) -#define PORTG_PIN1CTRL _SFR_MEM8(0x06D1) -#define PORTG_PIN2CTRL _SFR_MEM8(0x06D2) -#define PORTG_PIN3CTRL _SFR_MEM8(0x06D3) -#define PORTG_PIN4CTRL _SFR_MEM8(0x06D4) -#define PORTG_PIN5CTRL _SFR_MEM8(0x06D5) -#define PORTG_PIN6CTRL _SFR_MEM8(0x06D6) -#define PORTG_PIN7CTRL _SFR_MEM8(0x06D7) - -/* PORT - I/O Ports */ -#define PORTM_DIR _SFR_MEM8(0x0760) -#define PORTM_DIRSET _SFR_MEM8(0x0761) -#define PORTM_DIRCLR _SFR_MEM8(0x0762) -#define PORTM_DIRTGL _SFR_MEM8(0x0763) -#define PORTM_OUT _SFR_MEM8(0x0764) -#define PORTM_OUTSET _SFR_MEM8(0x0765) -#define PORTM_OUTCLR _SFR_MEM8(0x0766) -#define PORTM_OUTTGL _SFR_MEM8(0x0767) -#define PORTM_IN _SFR_MEM8(0x0768) -#define PORTM_INTCTRL _SFR_MEM8(0x0769) -#define PORTM_INT0MASK _SFR_MEM8(0x076A) -#define PORTM_INT1MASK _SFR_MEM8(0x076B) -#define PORTM_INTFLAGS _SFR_MEM8(0x076C) -#define PORTM_REMAP _SFR_MEM8(0x076E) -#define PORTM_PIN0CTRL _SFR_MEM8(0x0770) -#define PORTM_PIN1CTRL _SFR_MEM8(0x0771) -#define PORTM_PIN2CTRL _SFR_MEM8(0x0772) -#define PORTM_PIN3CTRL _SFR_MEM8(0x0773) -#define PORTM_PIN4CTRL _SFR_MEM8(0x0774) -#define PORTM_PIN5CTRL _SFR_MEM8(0x0775) -#define PORTM_PIN6CTRL _SFR_MEM8(0x0776) -#define PORTM_PIN7CTRL _SFR_MEM8(0x0777) - -/* PORT - I/O Ports */ -#define PORTR_DIR _SFR_MEM8(0x07E0) -#define PORTR_DIRSET _SFR_MEM8(0x07E1) -#define PORTR_DIRCLR _SFR_MEM8(0x07E2) -#define PORTR_DIRTGL _SFR_MEM8(0x07E3) -#define PORTR_OUT _SFR_MEM8(0x07E4) -#define PORTR_OUTSET _SFR_MEM8(0x07E5) -#define PORTR_OUTCLR _SFR_MEM8(0x07E6) -#define PORTR_OUTTGL _SFR_MEM8(0x07E7) -#define PORTR_IN _SFR_MEM8(0x07E8) -#define PORTR_INTCTRL _SFR_MEM8(0x07E9) -#define PORTR_INT0MASK _SFR_MEM8(0x07EA) -#define PORTR_INT1MASK _SFR_MEM8(0x07EB) -#define PORTR_INTFLAGS _SFR_MEM8(0x07EC) -#define PORTR_REMAP _SFR_MEM8(0x07EE) -#define PORTR_PIN0CTRL _SFR_MEM8(0x07F0) -#define PORTR_PIN1CTRL _SFR_MEM8(0x07F1) -#define PORTR_PIN2CTRL _SFR_MEM8(0x07F2) -#define PORTR_PIN3CTRL _SFR_MEM8(0x07F3) -#define PORTR_PIN4CTRL _SFR_MEM8(0x07F4) -#define PORTR_PIN5CTRL _SFR_MEM8(0x07F5) -#define PORTR_PIN6CTRL _SFR_MEM8(0x07F6) -#define PORTR_PIN7CTRL _SFR_MEM8(0x07F7) - -/* TC0 - 16-bit Timer/Counter 0 */ -#define TCC0_CTRLA _SFR_MEM8(0x0800) -#define TCC0_CTRLB _SFR_MEM8(0x0801) -#define TCC0_CTRLC _SFR_MEM8(0x0802) -#define TCC0_CTRLD _SFR_MEM8(0x0803) -#define TCC0_CTRLE _SFR_MEM8(0x0804) -#define TCC0_INTCTRLA _SFR_MEM8(0x0806) -#define TCC0_INTCTRLB _SFR_MEM8(0x0807) -#define TCC0_CTRLFCLR _SFR_MEM8(0x0808) -#define TCC0_CTRLFSET _SFR_MEM8(0x0809) -#define TCC0_CTRLGCLR _SFR_MEM8(0x080A) -#define TCC0_CTRLGSET _SFR_MEM8(0x080B) -#define TCC0_INTFLAGS _SFR_MEM8(0x080C) -#define TCC0_TEMP _SFR_MEM8(0x080F) -#define TCC0_CNT _SFR_MEM16(0x0820) -#define TCC0_PER _SFR_MEM16(0x0826) -#define TCC0_CCA _SFR_MEM16(0x0828) -#define TCC0_CCB _SFR_MEM16(0x082A) -#define TCC0_CCC _SFR_MEM16(0x082C) -#define TCC0_CCD _SFR_MEM16(0x082E) -#define TCC0_PERBUF _SFR_MEM16(0x0836) -#define TCC0_CCABUF _SFR_MEM16(0x0838) -#define TCC0_CCBBUF _SFR_MEM16(0x083A) -#define TCC0_CCCBUF _SFR_MEM16(0x083C) -#define TCC0_CCDBUF _SFR_MEM16(0x083E) - -/* TC1 - 16-bit Timer/Counter 1 */ -#define TCC1_CTRLA _SFR_MEM8(0x0840) -#define TCC1_CTRLB _SFR_MEM8(0x0841) -#define TCC1_CTRLC _SFR_MEM8(0x0842) -#define TCC1_CTRLD _SFR_MEM8(0x0843) -#define TCC1_CTRLE _SFR_MEM8(0x0844) -#define TCC1_INTCTRLA _SFR_MEM8(0x0846) -#define TCC1_INTCTRLB _SFR_MEM8(0x0847) -#define TCC1_CTRLFCLR _SFR_MEM8(0x0848) -#define TCC1_CTRLFSET _SFR_MEM8(0x0849) -#define TCC1_CTRLGCLR _SFR_MEM8(0x084A) -#define TCC1_CTRLGSET _SFR_MEM8(0x084B) -#define TCC1_INTFLAGS _SFR_MEM8(0x084C) -#define TCC1_TEMP _SFR_MEM8(0x084F) -#define TCC1_CNT _SFR_MEM16(0x0860) -#define TCC1_PER _SFR_MEM16(0x0866) -#define TCC1_CCA _SFR_MEM16(0x0868) -#define TCC1_CCB _SFR_MEM16(0x086A) -#define TCC1_PERBUF _SFR_MEM16(0x0876) -#define TCC1_CCABUF _SFR_MEM16(0x0878) -#define TCC1_CCBBUF _SFR_MEM16(0x087A) - -/* AWEX - Advanced Waveform Extension */ -#define AWEXC_CTRL _SFR_MEM8(0x0880) -#define AWEXC_FDEMASK _SFR_MEM8(0x0882) -#define AWEXC_FDCTRL _SFR_MEM8(0x0883) -#define AWEXC_STATUS _SFR_MEM8(0x0884) -#define AWEXC_STATUSSET _SFR_MEM8(0x0885) -#define AWEXC_DTBOTH _SFR_MEM8(0x0886) -#define AWEXC_DTBOTHBUF _SFR_MEM8(0x0887) -#define AWEXC_DTLS _SFR_MEM8(0x0888) -#define AWEXC_DTHS _SFR_MEM8(0x0889) -#define AWEXC_DTLSBUF _SFR_MEM8(0x088A) -#define AWEXC_DTHSBUF _SFR_MEM8(0x088B) -#define AWEXC_OUTOVEN _SFR_MEM8(0x088C) - -/* HIRES - High-Resolution Extension */ -#define HIRESC_CTRLA _SFR_MEM8(0x0890) - -/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ -#define USARTC0_DATA _SFR_MEM8(0x08A0) -#define USARTC0_STATUS _SFR_MEM8(0x08A1) -#define USARTC0_CTRLA _SFR_MEM8(0x08A3) -#define USARTC0_CTRLB _SFR_MEM8(0x08A4) -#define USARTC0_CTRLC _SFR_MEM8(0x08A5) -#define USARTC0_BAUDCTRLA _SFR_MEM8(0x08A6) -#define USARTC0_BAUDCTRLB _SFR_MEM8(0x08A7) - -/* SPI - Serial Peripheral Interface */ -#define SPIC_CTRL _SFR_MEM8(0x08C0) -#define SPIC_INTCTRL _SFR_MEM8(0x08C1) -#define SPIC_STATUS _SFR_MEM8(0x08C2) -#define SPIC_DATA _SFR_MEM8(0x08C3) - -/* IRCOM - IR Communication Module */ -#define IRCOM_CTRL _SFR_MEM8(0x08F8) -#define IRCOM_TXPLCTRL _SFR_MEM8(0x08F9) -#define IRCOM_RXPLCTRL _SFR_MEM8(0x08FA) - -/* LCD - LCD Controller */ -#define LCD_CTRLA _SFR_MEM8(0x0D00) -#define LCD_CTRLB _SFR_MEM8(0x0D01) -#define LCD_CTRLC _SFR_MEM8(0x0D02) -#define LCD_INTCTRL _SFR_MEM8(0x0D03) -#define LCD_INTFLAG _SFR_MEM8(0x0D04) -#define LCD_CTRLD _SFR_MEM8(0x0D05) -#define LCD_CTRLE _SFR_MEM8(0x0D06) -#define LCD_CTRLF _SFR_MEM8(0x0D07) -#define LCD_CTRLG _SFR_MEM8(0x0D08) -#define LCD_CTRLH _SFR_MEM8(0x0D09) -#define LCD_DATA0 _SFR_MEM8(0x0D10) -#define LCD_DATA1 _SFR_MEM8(0x0D11) -#define LCD_DATA2 _SFR_MEM8(0x0D12) -#define LCD_DATA3 _SFR_MEM8(0x0D13) -#define LCD_DATA4 _SFR_MEM8(0x0D14) -#define LCD_DATA5 _SFR_MEM8(0x0D15) -#define LCD_DATA6 _SFR_MEM8(0x0D16) -#define LCD_DATA7 _SFR_MEM8(0x0D17) -#define LCD_DATA8 _SFR_MEM8(0x0D18) -#define LCD_DATA9 _SFR_MEM8(0x0D19) -#define LCD_DATA10 _SFR_MEM8(0x0D1A) -#define LCD_DATA11 _SFR_MEM8(0x0D1B) -#define LCD_DATA12 _SFR_MEM8(0x0D1C) -#define LCD_DATA13 _SFR_MEM8(0x0D1D) -#define LCD_DATA14 _SFR_MEM8(0x0D1E) -#define LCD_DATA15 _SFR_MEM8(0x0D1F) -#define LCD_DATA16 _SFR_MEM8(0x0D20) -#define LCD_DATA17 _SFR_MEM8(0x0D21) -#define LCD_DATA18 _SFR_MEM8(0x0D22) -#define LCD_DATA19 _SFR_MEM8(0x0D23) - - - -/*================== Bitfield Definitions ================== */ - -/* VPORT - Virtual Ports */ -/* VPORT.INTFLAGS bit masks and bit positions */ -#define VPORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ -#define VPORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ - -#define VPORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ -#define VPORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ - -/* XOCD - On-Chip Debug System */ -/* OCD.OCDR0 bit masks and bit positions */ -#define OCD_OCDRD_gm 0xFF /* OCDR Dirty group mask. */ -#define OCD_OCDRD_gp 0 /* OCDR Dirty group position. */ -#define OCD_OCDRD0_bm (1<<0) /* OCDR Dirty bit 0 mask. */ -#define OCD_OCDRD0_bp 0 /* OCDR Dirty bit 0 position. */ -#define OCD_OCDRD1_bm (1<<1) /* OCDR Dirty bit 1 mask. */ -#define OCD_OCDRD1_bp 1 /* OCDR Dirty bit 1 position. */ -#define OCD_OCDRD2_bm (1<<2) /* OCDR Dirty bit 2 mask. */ -#define OCD_OCDRD2_bp 2 /* OCDR Dirty bit 2 position. */ -#define OCD_OCDRD3_bm (1<<3) /* OCDR Dirty bit 3 mask. */ -#define OCD_OCDRD3_bp 3 /* OCDR Dirty bit 3 position. */ -#define OCD_OCDRD4_bm (1<<4) /* OCDR Dirty bit 4 mask. */ -#define OCD_OCDRD4_bp 4 /* OCDR Dirty bit 4 position. */ -#define OCD_OCDRD5_bm (1<<5) /* OCDR Dirty bit 5 mask. */ -#define OCD_OCDRD5_bp 5 /* OCDR Dirty bit 5 position. */ -#define OCD_OCDRD6_bm (1<<6) /* OCDR Dirty bit 6 mask. */ -#define OCD_OCDRD6_bp 6 /* OCDR Dirty bit 6 position. */ -#define OCD_OCDRD7_bm (1<<7) /* OCDR Dirty bit 7 mask. */ -#define OCD_OCDRD7_bp 7 /* OCDR Dirty bit 7 position. */ - -/* OCD.OCDR1 bit masks and bit positions */ -/* OCD_OCDRD Predefined. */ -/* OCD_OCDRD Predefined. */ - -/* CPU - CPU */ -/* CPU.CCP bit masks and bit positions */ -#define CPU_CCP_gm 0xFF /* CCP signature group mask. */ -#define CPU_CCP_gp 0 /* CCP signature group position. */ -#define CPU_CCP0_bm (1<<0) /* CCP signature bit 0 mask. */ -#define CPU_CCP0_bp 0 /* CCP signature bit 0 position. */ -#define CPU_CCP1_bm (1<<1) /* CCP signature bit 1 mask. */ -#define CPU_CCP1_bp 1 /* CCP signature bit 1 position. */ -#define CPU_CCP2_bm (1<<2) /* CCP signature bit 2 mask. */ -#define CPU_CCP2_bp 2 /* CCP signature bit 2 position. */ -#define CPU_CCP3_bm (1<<3) /* CCP signature bit 3 mask. */ -#define CPU_CCP3_bp 3 /* CCP signature bit 3 position. */ -#define CPU_CCP4_bm (1<<4) /* CCP signature bit 4 mask. */ -#define CPU_CCP4_bp 4 /* CCP signature bit 4 position. */ -#define CPU_CCP5_bm (1<<5) /* CCP signature bit 5 mask. */ -#define CPU_CCP5_bp 5 /* CCP signature bit 5 position. */ -#define CPU_CCP6_bm (1<<6) /* CCP signature bit 6 mask. */ -#define CPU_CCP6_bp 6 /* CCP signature bit 6 position. */ -#define CPU_CCP7_bm (1<<7) /* CCP signature bit 7 mask. */ -#define CPU_CCP7_bp 7 /* CCP signature bit 7 position. */ - -/* CPU.SREG bit masks and bit positions */ -#define CPU_I_bm 0x80 /* Global Interrupt Enable Flag bit mask. */ -#define CPU_I_bp 7 /* Global Interrupt Enable Flag bit position. */ - -#define CPU_T_bm 0x40 /* Transfer Bit bit mask. */ -#define CPU_T_bp 6 /* Transfer Bit bit position. */ - -#define CPU_H_bm 0x20 /* Half Carry Flag bit mask. */ -#define CPU_H_bp 5 /* Half Carry Flag bit position. */ - -#define CPU_S_bm 0x10 /* N Exclusive Or V Flag bit mask. */ -#define CPU_S_bp 4 /* N Exclusive Or V Flag bit position. */ - -#define CPU_V_bm 0x08 /* Two's Complement Overflow Flag bit mask. */ -#define CPU_V_bp 3 /* Two's Complement Overflow Flag bit position. */ - -#define CPU_N_bm 0x04 /* Negative Flag bit mask. */ -#define CPU_N_bp 2 /* Negative Flag bit position. */ - -#define CPU_Z_bm 0x02 /* Zero Flag bit mask. */ -#define CPU_Z_bp 1 /* Zero Flag bit position. */ - -#define CPU_C_bm 0x01 /* Carry Flag bit mask. */ -#define CPU_C_bp 0 /* Carry Flag bit position. */ - -/* CLK - Clock System */ -/* CLK.CTRL bit masks and bit positions */ -#define CLK_SCLKSEL_gm 0x07 /* System Clock Selection group mask. */ -#define CLK_SCLKSEL_gp 0 /* System Clock Selection group position. */ -#define CLK_SCLKSEL0_bm (1<<0) /* System Clock Selection bit 0 mask. */ -#define CLK_SCLKSEL0_bp 0 /* System Clock Selection bit 0 position. */ -#define CLK_SCLKSEL1_bm (1<<1) /* System Clock Selection bit 1 mask. */ -#define CLK_SCLKSEL1_bp 1 /* System Clock Selection bit 1 position. */ -#define CLK_SCLKSEL2_bm (1<<2) /* System Clock Selection bit 2 mask. */ -#define CLK_SCLKSEL2_bp 2 /* System Clock Selection bit 2 position. */ - -/* CLK.PSCTRL bit masks and bit positions */ -#define CLK_PSADIV_gm 0x7C /* Prescaler A Division Factor group mask. */ -#define CLK_PSADIV_gp 2 /* Prescaler A Division Factor group position. */ -#define CLK_PSADIV0_bm (1<<2) /* Prescaler A Division Factor bit 0 mask. */ -#define CLK_PSADIV0_bp 2 /* Prescaler A Division Factor bit 0 position. */ -#define CLK_PSADIV1_bm (1<<3) /* Prescaler A Division Factor bit 1 mask. */ -#define CLK_PSADIV1_bp 3 /* Prescaler A Division Factor bit 1 position. */ -#define CLK_PSADIV2_bm (1<<4) /* Prescaler A Division Factor bit 2 mask. */ -#define CLK_PSADIV2_bp 4 /* Prescaler A Division Factor bit 2 position. */ -#define CLK_PSADIV3_bm (1<<5) /* Prescaler A Division Factor bit 3 mask. */ -#define CLK_PSADIV3_bp 5 /* Prescaler A Division Factor bit 3 position. */ -#define CLK_PSADIV4_bm (1<<6) /* Prescaler A Division Factor bit 4 mask. */ -#define CLK_PSADIV4_bp 6 /* Prescaler A Division Factor bit 4 position. */ - -#define CLK_PSBCDIV_gm 0x03 /* Prescaler B and C Division factor group mask. */ -#define CLK_PSBCDIV_gp 0 /* Prescaler B and C Division factor group position. */ -#define CLK_PSBCDIV0_bm (1<<0) /* Prescaler B and C Division factor bit 0 mask. */ -#define CLK_PSBCDIV0_bp 0 /* Prescaler B and C Division factor bit 0 position. */ -#define CLK_PSBCDIV1_bm (1<<1) /* Prescaler B and C Division factor bit 1 mask. */ -#define CLK_PSBCDIV1_bp 1 /* Prescaler B and C Division factor bit 1 position. */ - -/* CLK.LOCK bit masks and bit positions */ -#define CLK_LOCK_bm 0x01 /* Clock System Lock bit mask. */ -#define CLK_LOCK_bp 0 /* Clock System Lock bit position. */ - -/* CLK.RTCCTRL bit masks and bit positions */ -#define CLK_RTCSRC_gm 0x0E /* Clock Source group mask. */ -#define CLK_RTCSRC_gp 1 /* Clock Source group position. */ -#define CLK_RTCSRC0_bm (1<<1) /* Clock Source bit 0 mask. */ -#define CLK_RTCSRC0_bp 1 /* Clock Source bit 0 position. */ -#define CLK_RTCSRC1_bm (1<<2) /* Clock Source bit 1 mask. */ -#define CLK_RTCSRC1_bp 2 /* Clock Source bit 1 position. */ -#define CLK_RTCSRC2_bm (1<<3) /* Clock Source bit 2 mask. */ -#define CLK_RTCSRC2_bp 3 /* Clock Source bit 2 position. */ - -#define CLK_RTCEN_bm 0x01 /* Clock Source Enable bit mask. */ -#define CLK_RTCEN_bp 0 /* Clock Source Enable bit position. */ - -/* CLK.USBCTRL bit masks and bit positions */ -#define CLK_USBPSDIV_gm 0x38 /* Prescaler Division Factor group mask. */ -#define CLK_USBPSDIV_gp 3 /* Prescaler Division Factor group position. */ -#define CLK_USBPSDIV0_bm (1<<3) /* Prescaler Division Factor bit 0 mask. */ -#define CLK_USBPSDIV0_bp 3 /* Prescaler Division Factor bit 0 position. */ -#define CLK_USBPSDIV1_bm (1<<4) /* Prescaler Division Factor bit 1 mask. */ -#define CLK_USBPSDIV1_bp 4 /* Prescaler Division Factor bit 1 position. */ -#define CLK_USBPSDIV2_bm (1<<5) /* Prescaler Division Factor bit 2 mask. */ -#define CLK_USBPSDIV2_bp 5 /* Prescaler Division Factor bit 2 position. */ - -#define CLK_USBSRC_gm 0x06 /* Clock Source group mask. */ -#define CLK_USBSRC_gp 1 /* Clock Source group position. */ -#define CLK_USBSRC0_bm (1<<1) /* Clock Source bit 0 mask. */ -#define CLK_USBSRC0_bp 1 /* Clock Source bit 0 position. */ -#define CLK_USBSRC1_bm (1<<2) /* Clock Source bit 1 mask. */ -#define CLK_USBSRC1_bp 2 /* Clock Source bit 1 position. */ - -#define CLK_USBSEN_bm 0x01 /* Clock Source Enable bit mask. */ -#define CLK_USBSEN_bp 0 /* Clock Source Enable bit position. */ - -/* SLEEP - Sleep Controller */ -/* SLEEP.CTRL bit masks and bit positions */ -#define SLEEP_SMODE_gm 0x0E /* Sleep Mode group mask. */ -#define SLEEP_SMODE_gp 1 /* Sleep Mode group position. */ -#define SLEEP_SMODE0_bm (1<<1) /* Sleep Mode bit 0 mask. */ -#define SLEEP_SMODE0_bp 1 /* Sleep Mode bit 0 position. */ -#define SLEEP_SMODE1_bm (1<<2) /* Sleep Mode bit 1 mask. */ -#define SLEEP_SMODE1_bp 2 /* Sleep Mode bit 1 position. */ -#define SLEEP_SMODE2_bm (1<<3) /* Sleep Mode bit 2 mask. */ -#define SLEEP_SMODE2_bp 3 /* Sleep Mode bit 2 position. */ - -#define SLEEP_SEN_bm 0x01 /* Sleep Enable bit mask. */ -#define SLEEP_SEN_bp 0 /* Sleep Enable bit position. */ - -/* OSC - Oscillator */ -/* OSC.CTRL bit masks and bit positions */ -#define OSC_PLLEN_bm 0x10 /* PLL Enable bit mask. */ -#define OSC_PLLEN_bp 4 /* PLL Enable bit position. */ - -#define OSC_XOSCEN_bm 0x08 /* External Oscillator Enable bit mask. */ -#define OSC_XOSCEN_bp 3 /* External Oscillator Enable bit position. */ - -#define OSC_RC32KEN_bm 0x04 /* Internal 32.768 kHz RC Oscillator Enable bit mask. */ -#define OSC_RC32KEN_bp 2 /* Internal 32.768 kHz RC Oscillator Enable bit position. */ - -#define OSC_RC32MEN_bm 0x02 /* Internal 32 MHz RC Oscillator Enable bit mask. */ -#define OSC_RC32MEN_bp 1 /* Internal 32 MHz RC Oscillator Enable bit position. */ - -#define OSC_RC2MEN_bm 0x01 /* Internal 2 MHz RC Oscillator Enable bit mask. */ -#define OSC_RC2MEN_bp 0 /* Internal 2 MHz RC Oscillator Enable bit position. */ - -/* OSC.STATUS bit masks and bit positions */ -#define OSC_PLLRDY_bm 0x10 /* PLL Ready bit mask. */ -#define OSC_PLLRDY_bp 4 /* PLL Ready bit position. */ - -#define OSC_XOSCRDY_bm 0x08 /* External Oscillator Ready bit mask. */ -#define OSC_XOSCRDY_bp 3 /* External Oscillator Ready bit position. */ - -#define OSC_RC32KRDY_bm 0x04 /* Internal 32.768 kHz RC Oscillator Ready bit mask. */ -#define OSC_RC32KRDY_bp 2 /* Internal 32.768 kHz RC Oscillator Ready bit position. */ - -#define OSC_RC32MRDY_bm 0x02 /* Internal 32 MHz RC Oscillator Ready bit mask. */ -#define OSC_RC32MRDY_bp 1 /* Internal 32 MHz RC Oscillator Ready bit position. */ - -#define OSC_RC2MRDY_bm 0x01 /* Internal 2 MHz RC Oscillator Ready bit mask. */ -#define OSC_RC2MRDY_bp 0 /* Internal 2 MHz RC Oscillator Ready bit position. */ - -/* OSC.XOSCCTRL bit masks and bit positions */ -#define OSC_FRQRANGE_gm 0xC0 /* Frequency Range group mask. */ -#define OSC_FRQRANGE_gp 6 /* Frequency Range group position. */ -#define OSC_FRQRANGE0_bm (1<<6) /* Frequency Range bit 0 mask. */ -#define OSC_FRQRANGE0_bp 6 /* Frequency Range bit 0 position. */ -#define OSC_FRQRANGE1_bm (1<<7) /* Frequency Range bit 1 mask. */ -#define OSC_FRQRANGE1_bp 7 /* Frequency Range bit 1 position. */ - -#define OSC_X32KLPM_bm 0x20 /* 32.768 kHz XTAL OSC Low-power Mode bit mask. */ -#define OSC_X32KLPM_bp 5 /* 32.768 kHz XTAL OSC Low-power Mode bit position. */ - -#define OSC_XOSCPWR_bm 0x10 /* 16 MHz Crystal Oscillator High Power mode bit mask. */ -#define OSC_XOSCPWR_bp 4 /* 16 MHz Crystal Oscillator High Power mode bit position. */ - -#define OSC_XOSCSEL_gm 0x1F /* External Oscillator Selection and Startup Time group mask. */ -#define OSC_XOSCSEL_gp 0 /* External Oscillator Selection and Startup Time group position. */ -#define OSC_XOSCSEL0_bm (1<<0) /* External Oscillator Selection and Startup Time bit 0 mask. */ -#define OSC_XOSCSEL0_bp 0 /* External Oscillator Selection and Startup Time bit 0 position. */ -#define OSC_XOSCSEL1_bm (1<<1) /* External Oscillator Selection and Startup Time bit 1 mask. */ -#define OSC_XOSCSEL1_bp 1 /* External Oscillator Selection and Startup Time bit 1 position. */ -#define OSC_XOSCSEL2_bm (1<<2) /* External Oscillator Selection and Startup Time bit 2 mask. */ -#define OSC_XOSCSEL2_bp 2 /* External Oscillator Selection and Startup Time bit 2 position. */ -#define OSC_XOSCSEL3_bm (1<<3) /* External Oscillator Selection and Startup Time bit 3 mask. */ -#define OSC_XOSCSEL3_bp 3 /* External Oscillator Selection and Startup Time bit 3 position. */ -#define OSC_XOSCSEL4_bm (1<<4) /* External Oscillator Selection and Startup Time bit 4 mask. */ -#define OSC_XOSCSEL4_bp 4 /* External Oscillator Selection and Startup Time bit 4 position. */ - -/* OSC.XOSCFAIL bit masks and bit positions */ -#define OSC_PLLFDIF_bm 0x08 /* PLL Failure Detection Interrupt Flag bit mask. */ -#define OSC_PLLFDIF_bp 3 /* PLL Failure Detection Interrupt Flag bit position. */ - -#define OSC_PLLFDEN_bm 0x04 /* PLL Failure Detection Enable bit mask. */ -#define OSC_PLLFDEN_bp 2 /* PLL Failure Detection Enable bit position. */ - -#define OSC_XOSCFDIF_bm 0x02 /* XOSC Failure Detection Interrupt Flag bit mask. */ -#define OSC_XOSCFDIF_bp 1 /* XOSC Failure Detection Interrupt Flag bit position. */ - -#define OSC_XOSCFDEN_bm 0x01 /* XOSC Failure Detection Enable bit mask. */ -#define OSC_XOSCFDEN_bp 0 /* XOSC Failure Detection Enable bit position. */ - -/* OSC.PLLCTRL bit masks and bit positions */ -#define OSC_PLLSRC_gm 0xC0 /* Clock Source group mask. */ -#define OSC_PLLSRC_gp 6 /* Clock Source group position. */ -#define OSC_PLLSRC0_bm (1<<6) /* Clock Source bit 0 mask. */ -#define OSC_PLLSRC0_bp 6 /* Clock Source bit 0 position. */ -#define OSC_PLLSRC1_bm (1<<7) /* Clock Source bit 1 mask. */ -#define OSC_PLLSRC1_bp 7 /* Clock Source bit 1 position. */ - -#define OSC_PLLDIV_bm 0x20 /* Divide by 2 bit mask. */ -#define OSC_PLLDIV_bp 5 /* Divide by 2 bit position. */ - -#define OSC_PLLFAC_gm 0x1F /* Multiplication Factor group mask. */ -#define OSC_PLLFAC_gp 0 /* Multiplication Factor group position. */ -#define OSC_PLLFAC0_bm (1<<0) /* Multiplication Factor bit 0 mask. */ -#define OSC_PLLFAC0_bp 0 /* Multiplication Factor bit 0 position. */ -#define OSC_PLLFAC1_bm (1<<1) /* Multiplication Factor bit 1 mask. */ -#define OSC_PLLFAC1_bp 1 /* Multiplication Factor bit 1 position. */ -#define OSC_PLLFAC2_bm (1<<2) /* Multiplication Factor bit 2 mask. */ -#define OSC_PLLFAC2_bp 2 /* Multiplication Factor bit 2 position. */ -#define OSC_PLLFAC3_bm (1<<3) /* Multiplication Factor bit 3 mask. */ -#define OSC_PLLFAC3_bp 3 /* Multiplication Factor bit 3 position. */ -#define OSC_PLLFAC4_bm (1<<4) /* Multiplication Factor bit 4 mask. */ -#define OSC_PLLFAC4_bp 4 /* Multiplication Factor bit 4 position. */ - -/* OSC.DFLLCTRL bit masks and bit positions */ -#define OSC_RC32MCREF_gm 0x06 /* 32 MHz DFLL Calibration Reference group mask. */ -#define OSC_RC32MCREF_gp 1 /* 32 MHz DFLL Calibration Reference group position. */ -#define OSC_RC32MCREF0_bm (1<<1) /* 32 MHz DFLL Calibration Reference bit 0 mask. */ -#define OSC_RC32MCREF0_bp 1 /* 32 MHz DFLL Calibration Reference bit 0 position. */ -#define OSC_RC32MCREF1_bm (1<<2) /* 32 MHz DFLL Calibration Reference bit 1 mask. */ -#define OSC_RC32MCREF1_bp 2 /* 32 MHz DFLL Calibration Reference bit 1 position. */ - -#define OSC_RC2MCREF_bm 0x01 /* 2 MHz DFLL Calibration Reference bit mask. */ -#define OSC_RC2MCREF_bp 0 /* 2 MHz DFLL Calibration Reference bit position. */ - -/* DFLL - DFLL */ -/* DFLL.CTRL bit masks and bit positions */ -#define DFLL_ENABLE_bm 0x01 /* DFLL Enable bit mask. */ -#define DFLL_ENABLE_bp 0 /* DFLL Enable bit position. */ - -/* DFLL.CALA bit masks and bit positions */ -#define DFLL_CALL_gm 0x7F /* DFLL Calibration Value A group mask. */ -#define DFLL_CALL_gp 0 /* DFLL Calibration Value A group position. */ -#define DFLL_CALL0_bm (1<<0) /* DFLL Calibration Value A bit 0 mask. */ -#define DFLL_CALL0_bp 0 /* DFLL Calibration Value A bit 0 position. */ -#define DFLL_CALL1_bm (1<<1) /* DFLL Calibration Value A bit 1 mask. */ -#define DFLL_CALL1_bp 1 /* DFLL Calibration Value A bit 1 position. */ -#define DFLL_CALL2_bm (1<<2) /* DFLL Calibration Value A bit 2 mask. */ -#define DFLL_CALL2_bp 2 /* DFLL Calibration Value A bit 2 position. */ -#define DFLL_CALL3_bm (1<<3) /* DFLL Calibration Value A bit 3 mask. */ -#define DFLL_CALL3_bp 3 /* DFLL Calibration Value A bit 3 position. */ -#define DFLL_CALL4_bm (1<<4) /* DFLL Calibration Value A bit 4 mask. */ -#define DFLL_CALL4_bp 4 /* DFLL Calibration Value A bit 4 position. */ -#define DFLL_CALL5_bm (1<<5) /* DFLL Calibration Value A bit 5 mask. */ -#define DFLL_CALL5_bp 5 /* DFLL Calibration Value A bit 5 position. */ -#define DFLL_CALL6_bm (1<<6) /* DFLL Calibration Value A bit 6 mask. */ -#define DFLL_CALL6_bp 6 /* DFLL Calibration Value A bit 6 position. */ - -/* DFLL.CALB bit masks and bit positions */ -#define DFLL_CALH_gm 0x3F /* DFLL Calibration Value B group mask. */ -#define DFLL_CALH_gp 0 /* DFLL Calibration Value B group position. */ -#define DFLL_CALH0_bm (1<<0) /* DFLL Calibration Value B bit 0 mask. */ -#define DFLL_CALH0_bp 0 /* DFLL Calibration Value B bit 0 position. */ -#define DFLL_CALH1_bm (1<<1) /* DFLL Calibration Value B bit 1 mask. */ -#define DFLL_CALH1_bp 1 /* DFLL Calibration Value B bit 1 position. */ -#define DFLL_CALH2_bm (1<<2) /* DFLL Calibration Value B bit 2 mask. */ -#define DFLL_CALH2_bp 2 /* DFLL Calibration Value B bit 2 position. */ -#define DFLL_CALH3_bm (1<<3) /* DFLL Calibration Value B bit 3 mask. */ -#define DFLL_CALH3_bp 3 /* DFLL Calibration Value B bit 3 position. */ -#define DFLL_CALH4_bm (1<<4) /* DFLL Calibration Value B bit 4 mask. */ -#define DFLL_CALH4_bp 4 /* DFLL Calibration Value B bit 4 position. */ -#define DFLL_CALH5_bm (1<<5) /* DFLL Calibration Value B bit 5 mask. */ -#define DFLL_CALH5_bp 5 /* DFLL Calibration Value B bit 5 position. */ - -/* PR - Power Reduction */ -/* PR.PRGEN bit masks and bit positions */ -#define PR_LCD_bm 0x80 /* LCD Module bit mask. */ -#define PR_LCD_bp 7 /* LCD Module bit position. */ - -#define PR_USB_bm 0x40 /* USB bit mask. */ -#define PR_USB_bp 6 /* USB bit position. */ - -#define PR_AES_bm 0x10 /* AES bit mask. */ -#define PR_AES_bp 4 /* AES bit position. */ - -#define PR_RTC_bm 0x04 /* Real-time Counter bit mask. */ -#define PR_RTC_bp 2 /* Real-time Counter bit position. */ - -#define PR_EVSYS_bm 0x02 /* Event System bit mask. */ -#define PR_EVSYS_bp 1 /* Event System bit position. */ - -#define PR_DMA_bm 0x01 /* DMA-Controller bit mask. */ -#define PR_DMA_bp 0 /* DMA-Controller bit position. */ - -/* PR.PRPA bit masks and bit positions */ -#define PR_ADC_bm 0x02 /* Port A ADC bit mask. */ -#define PR_ADC_bp 1 /* Port A ADC bit position. */ - -#define PR_AC_bm 0x01 /* Port A Analog Comparator bit mask. */ -#define PR_AC_bp 0 /* Port A Analog Comparator bit position. */ - -/* PR.PRPB bit masks and bit positions */ -/* PR_ADC Predefined. */ -/* PR_ADC Predefined. */ - -/* PR_AC Predefined. */ -/* PR_AC Predefined. */ - -/* PR.PRPC bit masks and bit positions */ -#define PR_TWI_bm 0x40 /* Port C Two-wire Interface bit mask. */ -#define PR_TWI_bp 6 /* Port C Two-wire Interface bit position. */ - -#define PR_USART0_bm 0x10 /* Port C USART0 bit mask. */ -#define PR_USART0_bp 4 /* Port C USART0 bit position. */ - -#define PR_SPI_bm 0x08 /* Port C SPI bit mask. */ -#define PR_SPI_bp 3 /* Port C SPI bit position. */ - -#define PR_HIRES_bm 0x04 /* Port C AWEX bit mask. */ -#define PR_HIRES_bp 2 /* Port C AWEX bit position. */ - -#define PR_TC1_bm 0x02 /* Port C Timer/Counter1 bit mask. */ -#define PR_TC1_bp 1 /* Port C Timer/Counter1 bit position. */ - -#define PR_TC0_bm 0x01 /* Port C Timer/Counter0 bit mask. */ -#define PR_TC0_bp 0 /* Port C Timer/Counter0 bit position. */ - -/* PR.PRPE bit masks and bit positions */ -/* PR_USART0 Predefined. */ -/* PR_USART0 Predefined. */ - -/* PR_TC0 Predefined. */ -/* PR_TC0 Predefined. */ - -/* RST - Reset */ -/* RST.STATUS bit masks and bit positions */ -#define RST_SDRF_bm 0x40 /* Spike Detection Reset Flag bit mask. */ -#define RST_SDRF_bp 6 /* Spike Detection Reset Flag bit position. */ - -#define RST_SRF_bm 0x20 /* Software Reset Flag bit mask. */ -#define RST_SRF_bp 5 /* Software Reset Flag bit position. */ - -#define RST_PDIRF_bm 0x10 /* Programming and Debug Interface Interface Reset Flag bit mask. */ -#define RST_PDIRF_bp 4 /* Programming and Debug Interface Interface Reset Flag bit position. */ - -#define RST_WDRF_bm 0x08 /* Watchdog Reset Flag bit mask. */ -#define RST_WDRF_bp 3 /* Watchdog Reset Flag bit position. */ - -#define RST_BORF_bm 0x04 /* Brown-out Reset Flag bit mask. */ -#define RST_BORF_bp 2 /* Brown-out Reset Flag bit position. */ - -#define RST_EXTRF_bm 0x02 /* External Reset Flag bit mask. */ -#define RST_EXTRF_bp 1 /* External Reset Flag bit position. */ - -#define RST_PORF_bm 0x01 /* Power-on Reset Flag bit mask. */ -#define RST_PORF_bp 0 /* Power-on Reset Flag bit position. */ - -/* RST.CTRL bit masks and bit positions */ -#define RST_SWRST_bm 0x01 /* Software Reset bit mask. */ -#define RST_SWRST_bp 0 /* Software Reset bit position. */ - -/* WDT - Watch-Dog Timer */ -/* WDT.CTRL bit masks and bit positions */ -#define WDT_PER_gm 0x3C /* Period group mask. */ -#define WDT_PER_gp 2 /* Period group position. */ -#define WDT_PER0_bm (1<<2) /* Period bit 0 mask. */ -#define WDT_PER0_bp 2 /* Period bit 0 position. */ -#define WDT_PER1_bm (1<<3) /* Period bit 1 mask. */ -#define WDT_PER1_bp 3 /* Period bit 1 position. */ -#define WDT_PER2_bm (1<<4) /* Period bit 2 mask. */ -#define WDT_PER2_bp 4 /* Period bit 2 position. */ -#define WDT_PER3_bm (1<<5) /* Period bit 3 mask. */ -#define WDT_PER3_bp 5 /* Period bit 3 position. */ - -#define WDT_ENABLE_bm 0x02 /* Enable bit mask. */ -#define WDT_ENABLE_bp 1 /* Enable bit position. */ - -#define WDT_CEN_bm 0x01 /* Change Enable bit mask. */ -#define WDT_CEN_bp 0 /* Change Enable bit position. */ - -/* WDT.WINCTRL bit masks and bit positions */ -#define WDT_WPER_gm 0x3C /* Windowed Mode Period group mask. */ -#define WDT_WPER_gp 2 /* Windowed Mode Period group position. */ -#define WDT_WPER0_bm (1<<2) /* Windowed Mode Period bit 0 mask. */ -#define WDT_WPER0_bp 2 /* Windowed Mode Period bit 0 position. */ -#define WDT_WPER1_bm (1<<3) /* Windowed Mode Period bit 1 mask. */ -#define WDT_WPER1_bp 3 /* Windowed Mode Period bit 1 position. */ -#define WDT_WPER2_bm (1<<4) /* Windowed Mode Period bit 2 mask. */ -#define WDT_WPER2_bp 4 /* Windowed Mode Period bit 2 position. */ -#define WDT_WPER3_bm (1<<5) /* Windowed Mode Period bit 3 mask. */ -#define WDT_WPER3_bp 5 /* Windowed Mode Period bit 3 position. */ - -#define WDT_WEN_bm 0x02 /* Windowed Mode Enable bit mask. */ -#define WDT_WEN_bp 1 /* Windowed Mode Enable bit position. */ - -#define WDT_WCEN_bm 0x01 /* Windowed Mode Change Enable bit mask. */ -#define WDT_WCEN_bp 0 /* Windowed Mode Change Enable bit position. */ - -/* WDT.STATUS bit masks and bit positions */ -#define WDT_SYNCBUSY_bm 0x01 /* Syncronization busy bit mask. */ -#define WDT_SYNCBUSY_bp 0 /* Syncronization busy bit position. */ - -/* MCU - MCU Control */ -/* MCU.MCUCR bit masks and bit positions */ -#define MCU_JTAGD_bm 0x01 /* JTAG Disable bit mask. */ -#define MCU_JTAGD_bp 0 /* JTAG Disable bit position. */ - -/* MCU.ANAINIT bit masks and bit positions */ -#define MCU_STARTUPDLYB_gm 0x0C /* Analog startup delay Port B group mask. */ -#define MCU_STARTUPDLYB_gp 2 /* Analog startup delay Port B group position. */ -#define MCU_STARTUPDLYB0_bm (1<<2) /* Analog startup delay Port B bit 0 mask. */ -#define MCU_STARTUPDLYB0_bp 2 /* Analog startup delay Port B bit 0 position. */ -#define MCU_STARTUPDLYB1_bm (1<<3) /* Analog startup delay Port B bit 1 mask. */ -#define MCU_STARTUPDLYB1_bp 3 /* Analog startup delay Port B bit 1 position. */ - -#define MCU_STARTUPDLYA_gm 0x03 /* Analog startup delay Port A group mask. */ -#define MCU_STARTUPDLYA_gp 0 /* Analog startup delay Port A group position. */ -#define MCU_STARTUPDLYA0_bm (1<<0) /* Analog startup delay Port A bit 0 mask. */ -#define MCU_STARTUPDLYA0_bp 0 /* Analog startup delay Port A bit 0 position. */ -#define MCU_STARTUPDLYA1_bm (1<<1) /* Analog startup delay Port A bit 1 mask. */ -#define MCU_STARTUPDLYA1_bp 1 /* Analog startup delay Port A bit 1 position. */ - -/* MCU.EVSYSLOCK bit masks and bit positions */ -#define MCU_EVSYS1LOCK_bm 0x10 /* Event Channel 4-7 Lock bit mask. */ -#define MCU_EVSYS1LOCK_bp 4 /* Event Channel 4-7 Lock bit position. */ - -#define MCU_EVSYS0LOCK_bm 0x01 /* Event Channel 0-3 Lock bit mask. */ -#define MCU_EVSYS0LOCK_bp 0 /* Event Channel 0-3 Lock bit position. */ - -/* MCU.AWEXLOCK bit masks and bit positions */ -#define MCU_AWEXCLOCK_bm 0x01 /* AWeX on T/C C0 Lock bit mask. */ -#define MCU_AWEXCLOCK_bp 0 /* AWeX on T/C C0 Lock bit position. */ - -/* PMIC - Programmable Multi-level Interrupt Controller */ -/* PMIC.STATUS bit masks and bit positions */ -#define PMIC_NMIEX_bm 0x80 /* Non-maskable Interrupt Executing bit mask. */ -#define PMIC_NMIEX_bp 7 /* Non-maskable Interrupt Executing bit position. */ - -#define PMIC_HILVLEX_bm 0x04 /* High Level Interrupt Executing bit mask. */ -#define PMIC_HILVLEX_bp 2 /* High Level Interrupt Executing bit position. */ - -#define PMIC_MEDLVLEX_bm 0x02 /* Medium Level Interrupt Executing bit mask. */ -#define PMIC_MEDLVLEX_bp 1 /* Medium Level Interrupt Executing bit position. */ - -#define PMIC_LOLVLEX_bm 0x01 /* Low Level Interrupt Executing bit mask. */ -#define PMIC_LOLVLEX_bp 0 /* Low Level Interrupt Executing bit position. */ - -/* PMIC.INTPRI bit masks and bit positions */ -#define PMIC_INTPRI_gm 0xFF /* Interrupt Priority group mask. */ -#define PMIC_INTPRI_gp 0 /* Interrupt Priority group position. */ -#define PMIC_INTPRI0_bm (1<<0) /* Interrupt Priority bit 0 mask. */ -#define PMIC_INTPRI0_bp 0 /* Interrupt Priority bit 0 position. */ -#define PMIC_INTPRI1_bm (1<<1) /* Interrupt Priority bit 1 mask. */ -#define PMIC_INTPRI1_bp 1 /* Interrupt Priority bit 1 position. */ -#define PMIC_INTPRI2_bm (1<<2) /* Interrupt Priority bit 2 mask. */ -#define PMIC_INTPRI2_bp 2 /* Interrupt Priority bit 2 position. */ -#define PMIC_INTPRI3_bm (1<<3) /* Interrupt Priority bit 3 mask. */ -#define PMIC_INTPRI3_bp 3 /* Interrupt Priority bit 3 position. */ -#define PMIC_INTPRI4_bm (1<<4) /* Interrupt Priority bit 4 mask. */ -#define PMIC_INTPRI4_bp 4 /* Interrupt Priority bit 4 position. */ -#define PMIC_INTPRI5_bm (1<<5) /* Interrupt Priority bit 5 mask. */ -#define PMIC_INTPRI5_bp 5 /* Interrupt Priority bit 5 position. */ -#define PMIC_INTPRI6_bm (1<<6) /* Interrupt Priority bit 6 mask. */ -#define PMIC_INTPRI6_bp 6 /* Interrupt Priority bit 6 position. */ -#define PMIC_INTPRI7_bm (1<<7) /* Interrupt Priority bit 7 mask. */ -#define PMIC_INTPRI7_bp 7 /* Interrupt Priority bit 7 position. */ - -/* PMIC.CTRL bit masks and bit positions */ -#define PMIC_RREN_bm 0x80 /* Round-Robin Priority Enable bit mask. */ -#define PMIC_RREN_bp 7 /* Round-Robin Priority Enable bit position. */ - -#define PMIC_IVSEL_bm 0x40 /* Interrupt Vector Select bit mask. */ -#define PMIC_IVSEL_bp 6 /* Interrupt Vector Select bit position. */ - -#define PMIC_HILVLEN_bm 0x04 /* High Level Enable bit mask. */ -#define PMIC_HILVLEN_bp 2 /* High Level Enable bit position. */ - -#define PMIC_MEDLVLEN_bm 0x02 /* Medium Level Enable bit mask. */ -#define PMIC_MEDLVLEN_bp 1 /* Medium Level Enable bit position. */ - -#define PMIC_LOLVLEN_bm 0x01 /* Low Level Enable bit mask. */ -#define PMIC_LOLVLEN_bp 0 /* Low Level Enable bit position. */ - -/* PORTCFG - Port Configuration */ -/* PORTCFG.VPCTRLA bit masks and bit positions */ -#define PORTCFG_VP1MAP_gm 0xF0 /* Virtual Port 1 Mapping group mask. */ -#define PORTCFG_VP1MAP_gp 4 /* Virtual Port 1 Mapping group position. */ -#define PORTCFG_VP1MAP0_bm (1<<4) /* Virtual Port 1 Mapping bit 0 mask. */ -#define PORTCFG_VP1MAP0_bp 4 /* Virtual Port 1 Mapping bit 0 position. */ -#define PORTCFG_VP1MAP1_bm (1<<5) /* Virtual Port 1 Mapping bit 1 mask. */ -#define PORTCFG_VP1MAP1_bp 5 /* Virtual Port 1 Mapping bit 1 position. */ -#define PORTCFG_VP1MAP2_bm (1<<6) /* Virtual Port 1 Mapping bit 2 mask. */ -#define PORTCFG_VP1MAP2_bp 6 /* Virtual Port 1 Mapping bit 2 position. */ -#define PORTCFG_VP1MAP3_bm (1<<7) /* Virtual Port 1 Mapping bit 3 mask. */ -#define PORTCFG_VP1MAP3_bp 7 /* Virtual Port 1 Mapping bit 3 position. */ - -#define PORTCFG_VP0MAP_gm 0x0F /* Virtual Port 0 Mapping group mask. */ -#define PORTCFG_VP0MAP_gp 0 /* Virtual Port 0 Mapping group position. */ -#define PORTCFG_VP0MAP0_bm (1<<0) /* Virtual Port 0 Mapping bit 0 mask. */ -#define PORTCFG_VP0MAP0_bp 0 /* Virtual Port 0 Mapping bit 0 position. */ -#define PORTCFG_VP0MAP1_bm (1<<1) /* Virtual Port 0 Mapping bit 1 mask. */ -#define PORTCFG_VP0MAP1_bp 1 /* Virtual Port 0 Mapping bit 1 position. */ -#define PORTCFG_VP0MAP2_bm (1<<2) /* Virtual Port 0 Mapping bit 2 mask. */ -#define PORTCFG_VP0MAP2_bp 2 /* Virtual Port 0 Mapping bit 2 position. */ -#define PORTCFG_VP0MAP3_bm (1<<3) /* Virtual Port 0 Mapping bit 3 mask. */ -#define PORTCFG_VP0MAP3_bp 3 /* Virtual Port 0 Mapping bit 3 position. */ - -/* PORTCFG.VPCTRLB bit masks and bit positions */ -#define PORTCFG_VP3MAP_gm 0xF0 /* Virtual Port 3 Mapping group mask. */ -#define PORTCFG_VP3MAP_gp 4 /* Virtual Port 3 Mapping group position. */ -#define PORTCFG_VP3MAP0_bm (1<<4) /* Virtual Port 3 Mapping bit 0 mask. */ -#define PORTCFG_VP3MAP0_bp 4 /* Virtual Port 3 Mapping bit 0 position. */ -#define PORTCFG_VP3MAP1_bm (1<<5) /* Virtual Port 3 Mapping bit 1 mask. */ -#define PORTCFG_VP3MAP1_bp 5 /* Virtual Port 3 Mapping bit 1 position. */ -#define PORTCFG_VP3MAP2_bm (1<<6) /* Virtual Port 3 Mapping bit 2 mask. */ -#define PORTCFG_VP3MAP2_bp 6 /* Virtual Port 3 Mapping bit 2 position. */ -#define PORTCFG_VP3MAP3_bm (1<<7) /* Virtual Port 3 Mapping bit 3 mask. */ -#define PORTCFG_VP3MAP3_bp 7 /* Virtual Port 3 Mapping bit 3 position. */ - -#define PORTCFG_VP2MAP_gm 0x0F /* Virtual Port 2 Mapping group mask. */ -#define PORTCFG_VP2MAP_gp 0 /* Virtual Port 2 Mapping group position. */ -#define PORTCFG_VP2MAP0_bm (1<<0) /* Virtual Port 2 Mapping bit 0 mask. */ -#define PORTCFG_VP2MAP0_bp 0 /* Virtual Port 2 Mapping bit 0 position. */ -#define PORTCFG_VP2MAP1_bm (1<<1) /* Virtual Port 2 Mapping bit 1 mask. */ -#define PORTCFG_VP2MAP1_bp 1 /* Virtual Port 2 Mapping bit 1 position. */ -#define PORTCFG_VP2MAP2_bm (1<<2) /* Virtual Port 2 Mapping bit 2 mask. */ -#define PORTCFG_VP2MAP2_bp 2 /* Virtual Port 2 Mapping bit 2 position. */ -#define PORTCFG_VP2MAP3_bm (1<<3) /* Virtual Port 2 Mapping bit 3 mask. */ -#define PORTCFG_VP2MAP3_bp 3 /* Virtual Port 2 Mapping bit 3 position. */ - -/* PORTCFG.CLKEVOUT bit masks and bit positions */ -#define PORTCFG_CLKOUT_gm 0x03 /* Peripheral Clock Output Port group mask. */ -#define PORTCFG_CLKOUT_gp 0 /* Peripheral Clock Output Port group position. */ -#define PORTCFG_CLKOUT0_bm (1<<0) /* Peripheral Clock Output Port bit 0 mask. */ -#define PORTCFG_CLKOUT0_bp 0 /* Peripheral Clock Output Port bit 0 position. */ -#define PORTCFG_CLKOUT1_bm (1<<1) /* Peripheral Clock Output Port bit 1 mask. */ -#define PORTCFG_CLKOUT1_bp 1 /* Peripheral Clock Output Port bit 1 position. */ - -#define PORTCFG_CLKOUTSEL_gm 0x0C /* Peripheral Clock Output Select group mask. */ -#define PORTCFG_CLKOUTSEL_gp 2 /* Peripheral Clock Output Select group position. */ -#define PORTCFG_CLKOUTSEL0_bm (1<<2) /* Peripheral Clock Output Select bit 0 mask. */ -#define PORTCFG_CLKOUTSEL0_bp 2 /* Peripheral Clock Output Select bit 0 position. */ -#define PORTCFG_CLKOUTSEL1_bm (1<<3) /* Peripheral Clock Output Select bit 1 mask. */ -#define PORTCFG_CLKOUTSEL1_bp 3 /* Peripheral Clock Output Select bit 1 position. */ - -#define PORTCFG_EVOUT_gm 0x30 /* Event Output Port group mask. */ -#define PORTCFG_EVOUT_gp 4 /* Event Output Port group position. */ -#define PORTCFG_EVOUT0_bm (1<<4) /* Event Output Port bit 0 mask. */ -#define PORTCFG_EVOUT0_bp 4 /* Event Output Port bit 0 position. */ -#define PORTCFG_EVOUT1_bm (1<<5) /* Event Output Port bit 1 mask. */ -#define PORTCFG_EVOUT1_bp 5 /* Event Output Port bit 1 position. */ - -#define PORTCFG_RTCOUT_bm 0x40 /* RTC Clock Output bit mask. */ -#define PORTCFG_RTCOUT_bp 6 /* RTC Clock Output bit position. */ - -#define PORTCFG_CLKEVPIN_bm 0x80 /* Peripheral Clock and Event Output pin Select bit mask. */ -#define PORTCFG_CLKEVPIN_bp 7 /* Peripheral Clock and Event Output pin Select bit position. */ - -/* PORTCFG.EVOUTSEL bit masks and bit positions */ -#define PORTCFG_EVOUTSEL_bm 0x04 /* Event Output Select bit mask. */ -#define PORTCFG_EVOUTSEL_bp 2 /* Event Output Select bit position. */ - -/* AES - AES Module */ -/* AES.CTRL bit masks and bit positions */ -#define AES_START_bm 0x80 /* Start/Run bit mask. */ -#define AES_START_bp 7 /* Start/Run bit position. */ - -#define AES_AUTO_bm 0x40 /* Auto Start Trigger bit mask. */ -#define AES_AUTO_bp 6 /* Auto Start Trigger bit position. */ - -#define AES_RESET_bm 0x20 /* AES Software Reset bit mask. */ -#define AES_RESET_bp 5 /* AES Software Reset bit position. */ - -#define AES_DECRYPT_bm 0x10 /* Decryption / Direction bit mask. */ -#define AES_DECRYPT_bp 4 /* Decryption / Direction bit position. */ - -#define AES_XOR_bm 0x04 /* State XOR Load Enable bit mask. */ -#define AES_XOR_bp 2 /* State XOR Load Enable bit position. */ - -/* AES.STATUS bit masks and bit positions */ -#define AES_ERROR_bm 0x80 /* AES Error bit mask. */ -#define AES_ERROR_bp 7 /* AES Error bit position. */ - -#define AES_SRIF_bm 0x01 /* State Ready Interrupt Flag bit mask. */ -#define AES_SRIF_bp 0 /* State Ready Interrupt Flag bit position. */ - -/* AES.INTCTRL bit masks and bit positions */ -#define AES_INTLVL_gm 0x03 /* Interrupt level group mask. */ -#define AES_INTLVL_gp 0 /* Interrupt level group position. */ -#define AES_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */ -#define AES_INTLVL0_bp 0 /* Interrupt level bit 0 position. */ -#define AES_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */ -#define AES_INTLVL1_bp 1 /* Interrupt level bit 1 position. */ - -/* CRC - Cyclic Redundancy Checker */ -/* CRC.CTRL bit masks and bit positions */ -#define CRC_RESET_gm 0xC0 /* Reset group mask. */ -#define CRC_RESET_gp 6 /* Reset group position. */ -#define CRC_RESET0_bm (1<<6) /* Reset bit 0 mask. */ -#define CRC_RESET0_bp 6 /* Reset bit 0 position. */ -#define CRC_RESET1_bm (1<<7) /* Reset bit 1 mask. */ -#define CRC_RESET1_bp 7 /* Reset bit 1 position. */ - -#define CRC_CRC32_bm 0x20 /* CRC Mode bit mask. */ -#define CRC_CRC32_bp 5 /* CRC Mode bit position. */ - -#define CRC_SOURCE_gm 0x0F /* Input Source group mask. */ -#define CRC_SOURCE_gp 0 /* Input Source group position. */ -#define CRC_SOURCE0_bm (1<<0) /* Input Source bit 0 mask. */ -#define CRC_SOURCE0_bp 0 /* Input Source bit 0 position. */ -#define CRC_SOURCE1_bm (1<<1) /* Input Source bit 1 mask. */ -#define CRC_SOURCE1_bp 1 /* Input Source bit 1 position. */ -#define CRC_SOURCE2_bm (1<<2) /* Input Source bit 2 mask. */ -#define CRC_SOURCE2_bp 2 /* Input Source bit 2 position. */ -#define CRC_SOURCE3_bm (1<<3) /* Input Source bit 3 mask. */ -#define CRC_SOURCE3_bp 3 /* Input Source bit 3 position. */ - -/* CRC.STATUS bit masks and bit positions */ -#define CRC_ZERO_bm 0x02 /* Zero detection bit mask. */ -#define CRC_ZERO_bp 1 /* Zero detection bit position. */ - -#define CRC_BUSY_bm 0x01 /* Busy bit mask. */ -#define CRC_BUSY_bp 0 /* Busy bit position. */ - -/* DMA - DMA Controller */ -/* DMA_CH.CTRLA bit masks and bit positions */ -#define DMA_CH_CHEN_bm 0x80 /* Channel Enable bit mask. */ -#define DMA_CH_CHEN_bp 7 /* Channel Enable bit position. */ - -#define DMA_CH_CHRST_bm 0x40 /* Channel Software Reset bit mask. */ -#define DMA_CH_CHRST_bp 6 /* Channel Software Reset bit position. */ - -#define DMA_CH_REPEAT_bm 0x20 /* Channel Repeat Mode bit mask. */ -#define DMA_CH_REPEAT_bp 5 /* Channel Repeat Mode bit position. */ - -#define DMA_CH_TRFREQ_bm 0x10 /* Channel Transfer Request bit mask. */ -#define DMA_CH_TRFREQ_bp 4 /* Channel Transfer Request bit position. */ - -#define DMA_CH_SINGLE_bm 0x04 /* Channel Single Shot Data Transfer bit mask. */ -#define DMA_CH_SINGLE_bp 2 /* Channel Single Shot Data Transfer bit position. */ - -#define DMA_CH_BURSTLEN_gm 0x03 /* Channel Transfer Mode group mask. */ -#define DMA_CH_BURSTLEN_gp 0 /* Channel Transfer Mode group position. */ -#define DMA_CH_BURSTLEN0_bm (1<<0) /* Channel Transfer Mode bit 0 mask. */ -#define DMA_CH_BURSTLEN0_bp 0 /* Channel Transfer Mode bit 0 position. */ -#define DMA_CH_BURSTLEN1_bm (1<<1) /* Channel Transfer Mode bit 1 mask. */ -#define DMA_CH_BURSTLEN1_bp 1 /* Channel Transfer Mode bit 1 position. */ - -/* DMA_CH.CTRLB bit masks and bit positions */ -#define DMA_CH_CHBUSY_bm 0x80 /* Block Transfer Busy bit mask. */ -#define DMA_CH_CHBUSY_bp 7 /* Block Transfer Busy bit position. */ - -#define DMA_CH_CHPEND_bm 0x40 /* Block Transfer Pending bit mask. */ -#define DMA_CH_CHPEND_bp 6 /* Block Transfer Pending bit position. */ - -#define DMA_CH_ERRIF_bm 0x20 /* Block Transfer Error Interrupt Flag bit mask. */ -#define DMA_CH_ERRIF_bp 5 /* Block Transfer Error Interrupt Flag bit position. */ - -#define DMA_CH_TRNIF_bm 0x10 /* Transaction Complete Interrup Flag bit mask. */ -#define DMA_CH_TRNIF_bp 4 /* Transaction Complete Interrup Flag bit position. */ - -#define DMA_CH_ERRINTLVL_gm 0x0C /* Transfer Error Interrupt Level group mask. */ -#define DMA_CH_ERRINTLVL_gp 2 /* Transfer Error Interrupt Level group position. */ -#define DMA_CH_ERRINTLVL0_bm (1<<2) /* Transfer Error Interrupt Level bit 0 mask. */ -#define DMA_CH_ERRINTLVL0_bp 2 /* Transfer Error Interrupt Level bit 0 position. */ -#define DMA_CH_ERRINTLVL1_bm (1<<3) /* Transfer Error Interrupt Level bit 1 mask. */ -#define DMA_CH_ERRINTLVL1_bp 3 /* Transfer Error Interrupt Level bit 1 position. */ - -#define DMA_CH_TRNINTLVL_gm 0x03 /* Transaction Complete Interrupt Level group mask. */ -#define DMA_CH_TRNINTLVL_gp 0 /* Transaction Complete Interrupt Level group position. */ -#define DMA_CH_TRNINTLVL0_bm (1<<0) /* Transaction Complete Interrupt Level bit 0 mask. */ -#define DMA_CH_TRNINTLVL0_bp 0 /* Transaction Complete Interrupt Level bit 0 position. */ -#define DMA_CH_TRNINTLVL1_bm (1<<1) /* Transaction Complete Interrupt Level bit 1 mask. */ -#define DMA_CH_TRNINTLVL1_bp 1 /* Transaction Complete Interrupt Level bit 1 position. */ - -/* DMA_CH.ADDRCTRL bit masks and bit positions */ -#define DMA_CH_SRCRELOAD_gm 0xC0 /* Channel Source Address Reload group mask. */ -#define DMA_CH_SRCRELOAD_gp 6 /* Channel Source Address Reload group position. */ -#define DMA_CH_SRCRELOAD0_bm (1<<6) /* Channel Source Address Reload bit 0 mask. */ -#define DMA_CH_SRCRELOAD0_bp 6 /* Channel Source Address Reload bit 0 position. */ -#define DMA_CH_SRCRELOAD1_bm (1<<7) /* Channel Source Address Reload bit 1 mask. */ -#define DMA_CH_SRCRELOAD1_bp 7 /* Channel Source Address Reload bit 1 position. */ - -#define DMA_CH_SRCDIR_gm 0x30 /* Channel Source Address Mode group mask. */ -#define DMA_CH_SRCDIR_gp 4 /* Channel Source Address Mode group position. */ -#define DMA_CH_SRCDIR0_bm (1<<4) /* Channel Source Address Mode bit 0 mask. */ -#define DMA_CH_SRCDIR0_bp 4 /* Channel Source Address Mode bit 0 position. */ -#define DMA_CH_SRCDIR1_bm (1<<5) /* Channel Source Address Mode bit 1 mask. */ -#define DMA_CH_SRCDIR1_bp 5 /* Channel Source Address Mode bit 1 position. */ - -#define DMA_CH_DESTRELOAD_gm 0x0C /* Channel Destination Address Reload group mask. */ -#define DMA_CH_DESTRELOAD_gp 2 /* Channel Destination Address Reload group position. */ -#define DMA_CH_DESTRELOAD0_bm (1<<2) /* Channel Destination Address Reload bit 0 mask. */ -#define DMA_CH_DESTRELOAD0_bp 2 /* Channel Destination Address Reload bit 0 position. */ -#define DMA_CH_DESTRELOAD1_bm (1<<3) /* Channel Destination Address Reload bit 1 mask. */ -#define DMA_CH_DESTRELOAD1_bp 3 /* Channel Destination Address Reload bit 1 position. */ - -#define DMA_CH_DESTDIR_gm 0x03 /* Channel Destination Address Mode group mask. */ -#define DMA_CH_DESTDIR_gp 0 /* Channel Destination Address Mode group position. */ -#define DMA_CH_DESTDIR0_bm (1<<0) /* Channel Destination Address Mode bit 0 mask. */ -#define DMA_CH_DESTDIR0_bp 0 /* Channel Destination Address Mode bit 0 position. */ -#define DMA_CH_DESTDIR1_bm (1<<1) /* Channel Destination Address Mode bit 1 mask. */ -#define DMA_CH_DESTDIR1_bp 1 /* Channel Destination Address Mode bit 1 position. */ - -/* DMA_CH.TRIGSRC bit masks and bit positions */ -#define DMA_CH_TRIGSRC_gm 0xFF /* Channel Trigger Source group mask. */ -#define DMA_CH_TRIGSRC_gp 0 /* Channel Trigger Source group position. */ -#define DMA_CH_TRIGSRC0_bm (1<<0) /* Channel Trigger Source bit 0 mask. */ -#define DMA_CH_TRIGSRC0_bp 0 /* Channel Trigger Source bit 0 position. */ -#define DMA_CH_TRIGSRC1_bm (1<<1) /* Channel Trigger Source bit 1 mask. */ -#define DMA_CH_TRIGSRC1_bp 1 /* Channel Trigger Source bit 1 position. */ -#define DMA_CH_TRIGSRC2_bm (1<<2) /* Channel Trigger Source bit 2 mask. */ -#define DMA_CH_TRIGSRC2_bp 2 /* Channel Trigger Source bit 2 position. */ -#define DMA_CH_TRIGSRC3_bm (1<<3) /* Channel Trigger Source bit 3 mask. */ -#define DMA_CH_TRIGSRC3_bp 3 /* Channel Trigger Source bit 3 position. */ -#define DMA_CH_TRIGSRC4_bm (1<<4) /* Channel Trigger Source bit 4 mask. */ -#define DMA_CH_TRIGSRC4_bp 4 /* Channel Trigger Source bit 4 position. */ -#define DMA_CH_TRIGSRC5_bm (1<<5) /* Channel Trigger Source bit 5 mask. */ -#define DMA_CH_TRIGSRC5_bp 5 /* Channel Trigger Source bit 5 position. */ -#define DMA_CH_TRIGSRC6_bm (1<<6) /* Channel Trigger Source bit 6 mask. */ -#define DMA_CH_TRIGSRC6_bp 6 /* Channel Trigger Source bit 6 position. */ -#define DMA_CH_TRIGSRC7_bm (1<<7) /* Channel Trigger Source bit 7 mask. */ -#define DMA_CH_TRIGSRC7_bp 7 /* Channel Trigger Source bit 7 position. */ - -/* DMA.CTRL bit masks and bit positions */ -#define DMA_ENABLE_bm 0x80 /* Enable bit mask. */ -#define DMA_ENABLE_bp 7 /* Enable bit position. */ - -#define DMA_RESET_bm 0x40 /* Software Reset bit mask. */ -#define DMA_RESET_bp 6 /* Software Reset bit position. */ - -#define DMA_DBUFMODE_bm 0x04 /* Double Buffering Mode bit mask. */ -#define DMA_DBUFMODE_bp 2 /* Double Buffering Mode bit position. */ - -#define DMA_PRIMODE_bm 0x01 /* Channel Priority Mode bit mask. */ -#define DMA_PRIMODE_bp 0 /* Channel Priority Mode bit position. */ - -/* DMA.INTFLAGS bit masks and bit positions */ -#define DMA_CH1ERRIF_bm 0x20 /* Channel 1 Block Transfer Error Interrupt Flag bit mask. */ -#define DMA_CH1ERRIF_bp 5 /* Channel 1 Block Transfer Error Interrupt Flag bit position. */ - -#define DMA_CH0ERRIF_bm 0x10 /* Channel 0 Block Transfer Error Interrupt Flag bit mask. */ -#define DMA_CH0ERRIF_bp 4 /* Channel 0 Block Transfer Error Interrupt Flag bit position. */ - -#define DMA_CH1TRNIF_bm 0x02 /* Channel 1 Transaction Complete Interrupt Flag bit mask. */ -#define DMA_CH1TRNIF_bp 1 /* Channel 1 Transaction Complete Interrupt Flag bit position. */ - -#define DMA_CH0TRNIF_bm 0x01 /* Channel 0 Transaction Complete Interrupt Flag bit mask. */ -#define DMA_CH0TRNIF_bp 0 /* Channel 0 Transaction Complete Interrupt Flag bit position. */ - -/* DMA.STATUS bit masks and bit positions */ -#define DMA_CH1BUSY_bm 0x20 /* Channel 1 Block Transfer Busy bit mask. */ -#define DMA_CH1BUSY_bp 5 /* Channel 1 Block Transfer Busy bit position. */ - -#define DMA_CH0BUSY_bm 0x10 /* Channel 0 Block Transfer Busy bit mask. */ -#define DMA_CH0BUSY_bp 4 /* Channel 0 Block Transfer Busy bit position. */ - -#define DMA_CH1PEND_bm 0x02 /* Channel 1 Block Transfer Pending bit mask. */ -#define DMA_CH1PEND_bp 1 /* Channel 1 Block Transfer Pending bit position. */ - -#define DMA_CH0PEND_bm 0x01 /* Channel 0 Block Transfer Pending bit mask. */ -#define DMA_CH0PEND_bp 0 /* Channel 0 Block Transfer Pending bit position. */ - -/* EVSYS - Event System */ -/* EVSYS.CH0MUX bit masks and bit positions */ -#define EVSYS_CHMUX_gm 0xFF /* Event Channel 0 Multiplexer group mask. */ -#define EVSYS_CHMUX_gp 0 /* Event Channel 0 Multiplexer group position. */ -#define EVSYS_CHMUX0_bm (1<<0) /* Event Channel 0 Multiplexer bit 0 mask. */ -#define EVSYS_CHMUX0_bp 0 /* Event Channel 0 Multiplexer bit 0 position. */ -#define EVSYS_CHMUX1_bm (1<<1) /* Event Channel 0 Multiplexer bit 1 mask. */ -#define EVSYS_CHMUX1_bp 1 /* Event Channel 0 Multiplexer bit 1 position. */ -#define EVSYS_CHMUX2_bm (1<<2) /* Event Channel 0 Multiplexer bit 2 mask. */ -#define EVSYS_CHMUX2_bp 2 /* Event Channel 0 Multiplexer bit 2 position. */ -#define EVSYS_CHMUX3_bm (1<<3) /* Event Channel 0 Multiplexer bit 3 mask. */ -#define EVSYS_CHMUX3_bp 3 /* Event Channel 0 Multiplexer bit 3 position. */ -#define EVSYS_CHMUX4_bm (1<<4) /* Event Channel 0 Multiplexer bit 4 mask. */ -#define EVSYS_CHMUX4_bp 4 /* Event Channel 0 Multiplexer bit 4 position. */ -#define EVSYS_CHMUX5_bm (1<<5) /* Event Channel 0 Multiplexer bit 5 mask. */ -#define EVSYS_CHMUX5_bp 5 /* Event Channel 0 Multiplexer bit 5 position. */ -#define EVSYS_CHMUX6_bm (1<<6) /* Event Channel 0 Multiplexer bit 6 mask. */ -#define EVSYS_CHMUX6_bp 6 /* Event Channel 0 Multiplexer bit 6 position. */ -#define EVSYS_CHMUX7_bm (1<<7) /* Event Channel 0 Multiplexer bit 7 mask. */ -#define EVSYS_CHMUX7_bp 7 /* Event Channel 0 Multiplexer bit 7 position. */ - -/* EVSYS.CH1MUX bit masks and bit positions */ -/* EVSYS_CHMUX Predefined. */ -/* EVSYS_CHMUX Predefined. */ - -/* EVSYS.CH2MUX bit masks and bit positions */ -/* EVSYS_CHMUX Predefined. */ -/* EVSYS_CHMUX Predefined. */ - -/* EVSYS.CH3MUX bit masks and bit positions */ -/* EVSYS_CHMUX Predefined. */ -/* EVSYS_CHMUX Predefined. */ - -/* EVSYS.CH0CTRL bit masks and bit positions */ -#define EVSYS_QDIRM_gm 0x60 /* Quadrature Decoder Index Recognition Mode group mask. */ -#define EVSYS_QDIRM_gp 5 /* Quadrature Decoder Index Recognition Mode group position. */ -#define EVSYS_QDIRM0_bm (1<<5) /* Quadrature Decoder Index Recognition Mode bit 0 mask. */ -#define EVSYS_QDIRM0_bp 5 /* Quadrature Decoder Index Recognition Mode bit 0 position. */ -#define EVSYS_QDIRM1_bm (1<<6) /* Quadrature Decoder Index Recognition Mode bit 1 mask. */ -#define EVSYS_QDIRM1_bp 6 /* Quadrature Decoder Index Recognition Mode bit 1 position. */ - -#define EVSYS_QDIEN_bm 0x10 /* Quadrature Decoder Index Enable bit mask. */ -#define EVSYS_QDIEN_bp 4 /* Quadrature Decoder Index Enable bit position. */ - -#define EVSYS_QDEN_bm 0x08 /* Quadrature Decoder Enable bit mask. */ -#define EVSYS_QDEN_bp 3 /* Quadrature Decoder Enable bit position. */ - -#define EVSYS_DIGFILT_gm 0x07 /* Digital Filter group mask. */ -#define EVSYS_DIGFILT_gp 0 /* Digital Filter group position. */ -#define EVSYS_DIGFILT0_bm (1<<0) /* Digital Filter bit 0 mask. */ -#define EVSYS_DIGFILT0_bp 0 /* Digital Filter bit 0 position. */ -#define EVSYS_DIGFILT1_bm (1<<1) /* Digital Filter bit 1 mask. */ -#define EVSYS_DIGFILT1_bp 1 /* Digital Filter bit 1 position. */ -#define EVSYS_DIGFILT2_bm (1<<2) /* Digital Filter bit 2 mask. */ -#define EVSYS_DIGFILT2_bp 2 /* Digital Filter bit 2 position. */ - -/* EVSYS.CH1CTRL bit masks and bit positions */ -/* EVSYS_DIGFILT Predefined. */ -/* EVSYS_DIGFILT Predefined. */ - -/* EVSYS.CH2CTRL bit masks and bit positions */ -/* EVSYS_DIGFILT Predefined. */ -/* EVSYS_DIGFILT Predefined. */ - -/* EVSYS.CH3CTRL bit masks and bit positions */ -/* EVSYS_DIGFILT Predefined. */ -/* EVSYS_DIGFILT Predefined. */ - -/* NVM - Non Volatile Memory Controller */ -/* NVM.CMD bit masks and bit positions */ -#define NVM_CMD_gm 0x7F /* Command group mask. */ -#define NVM_CMD_gp 0 /* Command group position. */ -#define NVM_CMD0_bm (1<<0) /* Command bit 0 mask. */ -#define NVM_CMD0_bp 0 /* Command bit 0 position. */ -#define NVM_CMD1_bm (1<<1) /* Command bit 1 mask. */ -#define NVM_CMD1_bp 1 /* Command bit 1 position. */ -#define NVM_CMD2_bm (1<<2) /* Command bit 2 mask. */ -#define NVM_CMD2_bp 2 /* Command bit 2 position. */ -#define NVM_CMD3_bm (1<<3) /* Command bit 3 mask. */ -#define NVM_CMD3_bp 3 /* Command bit 3 position. */ -#define NVM_CMD4_bm (1<<4) /* Command bit 4 mask. */ -#define NVM_CMD4_bp 4 /* Command bit 4 position. */ -#define NVM_CMD5_bm (1<<5) /* Command bit 5 mask. */ -#define NVM_CMD5_bp 5 /* Command bit 5 position. */ -#define NVM_CMD6_bm (1<<6) /* Command bit 6 mask. */ -#define NVM_CMD6_bp 6 /* Command bit 6 position. */ - -/* NVM.CTRLA bit masks and bit positions */ -#define NVM_CMDEX_bm 0x01 /* Command Execute bit mask. */ -#define NVM_CMDEX_bp 0 /* Command Execute bit position. */ - -/* NVM.CTRLB bit masks and bit positions */ -#define NVM_EEMAPEN_bm 0x08 /* EEPROM Mapping Enable bit mask. */ -#define NVM_EEMAPEN_bp 3 /* EEPROM Mapping Enable bit position. */ - -#define NVM_FPRM_bm 0x04 /* Flash Power Reduction Enable bit mask. */ -#define NVM_FPRM_bp 2 /* Flash Power Reduction Enable bit position. */ - -#define NVM_EPRM_bm 0x02 /* EEPROM Power Reduction Enable bit mask. */ -#define NVM_EPRM_bp 1 /* EEPROM Power Reduction Enable bit position. */ - -#define NVM_SPMLOCK_bm 0x01 /* SPM Lock bit mask. */ -#define NVM_SPMLOCK_bp 0 /* SPM Lock bit position. */ - -/* NVM.INTCTRL bit masks and bit positions */ -#define NVM_SPMLVL_gm 0x0C /* SPM Interrupt Level group mask. */ -#define NVM_SPMLVL_gp 2 /* SPM Interrupt Level group position. */ -#define NVM_SPMLVL0_bm (1<<2) /* SPM Interrupt Level bit 0 mask. */ -#define NVM_SPMLVL0_bp 2 /* SPM Interrupt Level bit 0 position. */ -#define NVM_SPMLVL1_bm (1<<3) /* SPM Interrupt Level bit 1 mask. */ -#define NVM_SPMLVL1_bp 3 /* SPM Interrupt Level bit 1 position. */ - -#define NVM_EELVL_gm 0x03 /* EEPROM Interrupt Level group mask. */ -#define NVM_EELVL_gp 0 /* EEPROM Interrupt Level group position. */ -#define NVM_EELVL0_bm (1<<0) /* EEPROM Interrupt Level bit 0 mask. */ -#define NVM_EELVL0_bp 0 /* EEPROM Interrupt Level bit 0 position. */ -#define NVM_EELVL1_bm (1<<1) /* EEPROM Interrupt Level bit 1 mask. */ -#define NVM_EELVL1_bp 1 /* EEPROM Interrupt Level bit 1 position. */ - -/* NVM.STATUS bit masks and bit positions */ -#define NVM_NVMBUSY_bm 0x80 /* Non-volatile Memory Busy bit mask. */ -#define NVM_NVMBUSY_bp 7 /* Non-volatile Memory Busy bit position. */ - -#define NVM_FBUSY_bm 0x40 /* Flash Memory Busy bit mask. */ -#define NVM_FBUSY_bp 6 /* Flash Memory Busy bit position. */ - -#define NVM_EELOAD_bm 0x02 /* EEPROM Page Buffer Active Loading bit mask. */ -#define NVM_EELOAD_bp 1 /* EEPROM Page Buffer Active Loading bit position. */ - -#define NVM_FLOAD_bm 0x01 /* Flash Page Buffer Active Loading bit mask. */ -#define NVM_FLOAD_bp 0 /* Flash Page Buffer Active Loading bit position. */ - -/* NVM.LOCKBITS bit masks and bit positions */ -#define NVM_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ -#define NVM_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ -#define NVM_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ -#define NVM_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ -#define NVM_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ -#define NVM_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ - -#define NVM_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ -#define NVM_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ -#define NVM_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ -#define NVM_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ -#define NVM_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ -#define NVM_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ - -#define NVM_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ -#define NVM_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ -#define NVM_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ -#define NVM_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ -#define NVM_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ -#define NVM_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ - -#define NVM_LB_gm 0x03 /* Lock Bits group mask. */ -#define NVM_LB_gp 0 /* Lock Bits group position. */ -#define NVM_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ -#define NVM_LB0_bp 0 /* Lock Bits bit 0 position. */ -#define NVM_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ -#define NVM_LB1_bp 1 /* Lock Bits bit 1 position. */ - -/* ADC - Analog/Digital Converter */ -/* ADC_CH.CTRL bit masks and bit positions */ -#define ADC_CH_START_bm 0x80 /* Channel Start Conversion bit mask. */ -#define ADC_CH_START_bp 7 /* Channel Start Conversion bit position. */ - -#define ADC_CH_GAIN_gm 0x1C /* Gain Factor group mask. */ -#define ADC_CH_GAIN_gp 2 /* Gain Factor group position. */ -#define ADC_CH_GAIN0_bm (1<<2) /* Gain Factor bit 0 mask. */ -#define ADC_CH_GAIN0_bp 2 /* Gain Factor bit 0 position. */ -#define ADC_CH_GAIN1_bm (1<<3) /* Gain Factor bit 1 mask. */ -#define ADC_CH_GAIN1_bp 3 /* Gain Factor bit 1 position. */ -#define ADC_CH_GAIN2_bm (1<<4) /* Gain Factor bit 2 mask. */ -#define ADC_CH_GAIN2_bp 4 /* Gain Factor bit 2 position. */ - -#define ADC_CH_INPUTMODE_gm 0x03 /* Input Mode Select group mask. */ -#define ADC_CH_INPUTMODE_gp 0 /* Input Mode Select group position. */ -#define ADC_CH_INPUTMODE0_bm (1<<0) /* Input Mode Select bit 0 mask. */ -#define ADC_CH_INPUTMODE0_bp 0 /* Input Mode Select bit 0 position. */ -#define ADC_CH_INPUTMODE1_bm (1<<1) /* Input Mode Select bit 1 mask. */ -#define ADC_CH_INPUTMODE1_bp 1 /* Input Mode Select bit 1 position. */ - -/* ADC_CH.MUXCTRL bit masks and bit positions */ -#define ADC_CH_MUXPOS_gm 0x78 /* MUX selection on Positive ADC input group mask. */ -#define ADC_CH_MUXPOS_gp 3 /* MUX selection on Positive ADC input group position. */ -#define ADC_CH_MUXPOS0_bm (1<<3) /* MUX selection on Positive ADC input bit 0 mask. */ -#define ADC_CH_MUXPOS0_bp 3 /* MUX selection on Positive ADC input bit 0 position. */ -#define ADC_CH_MUXPOS1_bm (1<<4) /* MUX selection on Positive ADC input bit 1 mask. */ -#define ADC_CH_MUXPOS1_bp 4 /* MUX selection on Positive ADC input bit 1 position. */ -#define ADC_CH_MUXPOS2_bm (1<<5) /* MUX selection on Positive ADC input bit 2 mask. */ -#define ADC_CH_MUXPOS2_bp 5 /* MUX selection on Positive ADC input bit 2 position. */ -#define ADC_CH_MUXPOS3_bm (1<<6) /* MUX selection on Positive ADC input bit 3 mask. */ -#define ADC_CH_MUXPOS3_bp 6 /* MUX selection on Positive ADC input bit 3 position. */ - -#define ADC_CH_MUXINT_gm 0x78 /* MUX selection on Internal ADC input group mask. */ -#define ADC_CH_MUXINT_gp 3 /* MUX selection on Internal ADC input group position. */ -#define ADC_CH_MUXINT0_bm (1<<3) /* MUX selection on Internal ADC input bit 0 mask. */ -#define ADC_CH_MUXINT0_bp 3 /* MUX selection on Internal ADC input bit 0 position. */ -#define ADC_CH_MUXINT1_bm (1<<4) /* MUX selection on Internal ADC input bit 1 mask. */ -#define ADC_CH_MUXINT1_bp 4 /* MUX selection on Internal ADC input bit 1 position. */ -#define ADC_CH_MUXINT2_bm (1<<5) /* MUX selection on Internal ADC input bit 2 mask. */ -#define ADC_CH_MUXINT2_bp 5 /* MUX selection on Internal ADC input bit 2 position. */ -#define ADC_CH_MUXINT3_bm (1<<6) /* MUX selection on Internal ADC input bit 3 mask. */ -#define ADC_CH_MUXINT3_bp 6 /* MUX selection on Internal ADC input bit 3 position. */ - -#define ADC_CH_MUXNEG_gm 0x03 /* MUX selection on Negative ADC input group mask. */ -#define ADC_CH_MUXNEG_gp 0 /* MUX selection on Negative ADC input group position. */ -#define ADC_CH_MUXNEG0_bm (1<<0) /* MUX selection on Negative ADC input bit 0 mask. */ -#define ADC_CH_MUXNEG0_bp 0 /* MUX selection on Negative ADC input bit 0 position. */ -#define ADC_CH_MUXNEG1_bm (1<<1) /* MUX selection on Negative ADC input bit 1 mask. */ -#define ADC_CH_MUXNEG1_bp 1 /* MUX selection on Negative ADC input bit 1 position. */ - -/* ADC_CH.INTCTRL bit masks and bit positions */ -#define ADC_CH_INTMODE_gm 0x0C /* Interrupt Mode group mask. */ -#define ADC_CH_INTMODE_gp 2 /* Interrupt Mode group position. */ -#define ADC_CH_INTMODE0_bm (1<<2) /* Interrupt Mode bit 0 mask. */ -#define ADC_CH_INTMODE0_bp 2 /* Interrupt Mode bit 0 position. */ -#define ADC_CH_INTMODE1_bm (1<<3) /* Interrupt Mode bit 1 mask. */ -#define ADC_CH_INTMODE1_bp 3 /* Interrupt Mode bit 1 position. */ - -#define ADC_CH_INTLVL_gm 0x03 /* Interrupt Level group mask. */ -#define ADC_CH_INTLVL_gp 0 /* Interrupt Level group position. */ -#define ADC_CH_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */ -#define ADC_CH_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */ -#define ADC_CH_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ -#define ADC_CH_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */ - -/* ADC_CH.INTFLAGS bit masks and bit positions */ -#define ADC_CH_CHIF_bm 0x01 /* Channel Interrupt Flag bit mask. */ -#define ADC_CH_CHIF_bp 0 /* Channel Interrupt Flag bit position. */ - -/* ADC_CH.SCAN bit masks and bit positions */ -#define ADC_CH_OFFSET_gm 0xF0 /* Positive MUX setting offset group mask. */ -#define ADC_CH_OFFSET_gp 4 /* Positive MUX setting offset group position. */ -#define ADC_CH_OFFSET0_bm (1<<4) /* Positive MUX setting offset bit 0 mask. */ -#define ADC_CH_OFFSET0_bp 4 /* Positive MUX setting offset bit 0 position. */ -#define ADC_CH_OFFSET1_bm (1<<5) /* Positive MUX setting offset bit 1 mask. */ -#define ADC_CH_OFFSET1_bp 5 /* Positive MUX setting offset bit 1 position. */ -#define ADC_CH_OFFSET2_bm (1<<6) /* Positive MUX setting offset bit 2 mask. */ -#define ADC_CH_OFFSET2_bp 6 /* Positive MUX setting offset bit 2 position. */ -#define ADC_CH_OFFSET3_bm (1<<7) /* Positive MUX setting offset bit 3 mask. */ -#define ADC_CH_OFFSET3_bp 7 /* Positive MUX setting offset bit 3 position. */ - -#define ADC_CH_COUNT_gm 0x0F /* Number of Channels included in scan group mask. */ -#define ADC_CH_COUNT_gp 0 /* Number of Channels included in scan group position. */ -#define ADC_CH_COUNT0_bm (1<<0) /* Number of Channels included in scan bit 0 mask. */ -#define ADC_CH_COUNT0_bp 0 /* Number of Channels included in scan bit 0 position. */ -#define ADC_CH_COUNT1_bm (1<<1) /* Number of Channels included in scan bit 1 mask. */ -#define ADC_CH_COUNT1_bp 1 /* Number of Channels included in scan bit 1 position. */ -#define ADC_CH_COUNT2_bm (1<<2) /* Number of Channels included in scan bit 2 mask. */ -#define ADC_CH_COUNT2_bp 2 /* Number of Channels included in scan bit 2 position. */ -#define ADC_CH_COUNT3_bm (1<<3) /* Number of Channels included in scan bit 3 mask. */ -#define ADC_CH_COUNT3_bp 3 /* Number of Channels included in scan bit 3 position. */ - -/* ADC.CTRLA bit masks and bit positions */ -#define ADC_CH0START_bm 0x04 /* Channel 0 Start Conversion bit mask. */ -#define ADC_CH0START_bp 2 /* Channel 0 Start Conversion bit position. */ - -#define ADC_FLUSH_bm 0x02 /* ADC Flush bit mask. */ -#define ADC_FLUSH_bp 1 /* ADC Flush bit position. */ - -#define ADC_ENABLE_bm 0x01 /* Enable ADC bit mask. */ -#define ADC_ENABLE_bp 0 /* Enable ADC bit position. */ - -/* ADC.CTRLB bit masks and bit positions */ -#define ADC_CURRLIMIT_gm 0x60 /* Current limit group mask. */ -#define ADC_CURRLIMIT_gp 5 /* Current limit group position. */ -#define ADC_CURRLIMIT0_bm (1<<5) /* Current limit bit 0 mask. */ -#define ADC_CURRLIMIT0_bp 5 /* Current limit bit 0 position. */ -#define ADC_CURRLIMIT1_bm (1<<6) /* Current limit bit 1 mask. */ -#define ADC_CURRLIMIT1_bp 6 /* Current limit bit 1 position. */ - -#define ADC_CONMODE_bm 0x10 /* Conversion Mode bit mask. */ -#define ADC_CONMODE_bp 4 /* Conversion Mode bit position. */ - -#define ADC_FREERUN_bm 0x08 /* Free Running Mode Enable bit mask. */ -#define ADC_FREERUN_bp 3 /* Free Running Mode Enable bit position. */ - -#define ADC_RESOLUTION_gm 0x06 /* Result Resolution group mask. */ -#define ADC_RESOLUTION_gp 1 /* Result Resolution group position. */ -#define ADC_RESOLUTION0_bm (1<<1) /* Result Resolution bit 0 mask. */ -#define ADC_RESOLUTION0_bp 1 /* Result Resolution bit 0 position. */ -#define ADC_RESOLUTION1_bm (1<<2) /* Result Resolution bit 1 mask. */ -#define ADC_RESOLUTION1_bp 2 /* Result Resolution bit 1 position. */ - -/* ADC.REFCTRL bit masks and bit positions */ -#define ADC_REFSEL_gm 0x70 /* Reference Selection group mask. */ -#define ADC_REFSEL_gp 4 /* Reference Selection group position. */ -#define ADC_REFSEL0_bm (1<<4) /* Reference Selection bit 0 mask. */ -#define ADC_REFSEL0_bp 4 /* Reference Selection bit 0 position. */ -#define ADC_REFSEL1_bm (1<<5) /* Reference Selection bit 1 mask. */ -#define ADC_REFSEL1_bp 5 /* Reference Selection bit 1 position. */ -#define ADC_REFSEL2_bm (1<<6) /* Reference Selection bit 2 mask. */ -#define ADC_REFSEL2_bp 6 /* Reference Selection bit 2 position. */ - -#define ADC_BANDGAP_bm 0x02 /* Bandgap enable bit mask. */ -#define ADC_BANDGAP_bp 1 /* Bandgap enable bit position. */ - -#define ADC_TEMPREF_bm 0x01 /* Temperature Reference Enable bit mask. */ -#define ADC_TEMPREF_bp 0 /* Temperature Reference Enable bit position. */ - -/* ADC.EVCTRL bit masks and bit positions */ -#define ADC_EVSEL_gm 0x18 /* Event Input Select group mask. */ -#define ADC_EVSEL_gp 3 /* Event Input Select group position. */ -#define ADC_EVSEL0_bm (1<<3) /* Event Input Select bit 0 mask. */ -#define ADC_EVSEL0_bp 3 /* Event Input Select bit 0 position. */ -#define ADC_EVSEL1_bm (1<<4) /* Event Input Select bit 1 mask. */ -#define ADC_EVSEL1_bp 4 /* Event Input Select bit 1 position. */ - -#define ADC_EVACT_gm 0x07 /* Event Action Select group mask. */ -#define ADC_EVACT_gp 0 /* Event Action Select group position. */ -#define ADC_EVACT0_bm (1<<0) /* Event Action Select bit 0 mask. */ -#define ADC_EVACT0_bp 0 /* Event Action Select bit 0 position. */ -#define ADC_EVACT1_bm (1<<1) /* Event Action Select bit 1 mask. */ -#define ADC_EVACT1_bp 1 /* Event Action Select bit 1 position. */ -#define ADC_EVACT2_bm (1<<2) /* Event Action Select bit 2 mask. */ -#define ADC_EVACT2_bp 2 /* Event Action Select bit 2 position. */ - -/* ADC.PRESCALER bit masks and bit positions */ -#define ADC_PRESCALER_gm 0x07 /* Clock Prescaler Selection group mask. */ -#define ADC_PRESCALER_gp 0 /* Clock Prescaler Selection group position. */ -#define ADC_PRESCALER0_bm (1<<0) /* Clock Prescaler Selection bit 0 mask. */ -#define ADC_PRESCALER0_bp 0 /* Clock Prescaler Selection bit 0 position. */ -#define ADC_PRESCALER1_bm (1<<1) /* Clock Prescaler Selection bit 1 mask. */ -#define ADC_PRESCALER1_bp 1 /* Clock Prescaler Selection bit 1 position. */ -#define ADC_PRESCALER2_bm (1<<2) /* Clock Prescaler Selection bit 2 mask. */ -#define ADC_PRESCALER2_bp 2 /* Clock Prescaler Selection bit 2 position. */ - -/* ADC.INTFLAGS bit masks and bit positions */ -#define ADC_CH0IF_bm 0x01 /* Channel 0 Interrupt Flag bit mask. */ -#define ADC_CH0IF_bp 0 /* Channel 0 Interrupt Flag bit position. */ - -/* ADC.SAMPCTRL bit masks and bit positions */ -#define ADC_SAMPVAL_gm 0x3F /* Sampling time control register group mask. */ -#define ADC_SAMPVAL_gp 0 /* Sampling time control register group position. */ -#define ADC_SAMPVAL0_bm (1<<0) /* Sampling time control register bit 0 mask. */ -#define ADC_SAMPVAL0_bp 0 /* Sampling time control register bit 0 position. */ -#define ADC_SAMPVAL1_bm (1<<1) /* Sampling time control register bit 1 mask. */ -#define ADC_SAMPVAL1_bp 1 /* Sampling time control register bit 1 position. */ -#define ADC_SAMPVAL2_bm (1<<2) /* Sampling time control register bit 2 mask. */ -#define ADC_SAMPVAL2_bp 2 /* Sampling time control register bit 2 position. */ -#define ADC_SAMPVAL3_bm (1<<3) /* Sampling time control register bit 3 mask. */ -#define ADC_SAMPVAL3_bp 3 /* Sampling time control register bit 3 position. */ -#define ADC_SAMPVAL4_bm (1<<4) /* Sampling time control register bit 4 mask. */ -#define ADC_SAMPVAL4_bp 4 /* Sampling time control register bit 4 position. */ -#define ADC_SAMPVAL5_bm (1<<5) /* Sampling time control register bit 5 mask. */ -#define ADC_SAMPVAL5_bp 5 /* Sampling time control register bit 5 position. */ - -/* AC - Analog Comparator */ -/* AC.AC0CTRL bit masks and bit positions */ -#define AC_INTMODE_gm 0xC0 /* Interrupt Mode group mask. */ -#define AC_INTMODE_gp 6 /* Interrupt Mode group position. */ -#define AC_INTMODE0_bm (1<<6) /* Interrupt Mode bit 0 mask. */ -#define AC_INTMODE0_bp 6 /* Interrupt Mode bit 0 position. */ -#define AC_INTMODE1_bm (1<<7) /* Interrupt Mode bit 1 mask. */ -#define AC_INTMODE1_bp 7 /* Interrupt Mode bit 1 position. */ - -#define AC_INTLVL_gm 0x30 /* Interrupt Level group mask. */ -#define AC_INTLVL_gp 4 /* Interrupt Level group position. */ -#define AC_INTLVL0_bm (1<<4) /* Interrupt Level bit 0 mask. */ -#define AC_INTLVL0_bp 4 /* Interrupt Level bit 0 position. */ -#define AC_INTLVL1_bm (1<<5) /* Interrupt Level bit 1 mask. */ -#define AC_INTLVL1_bp 5 /* Interrupt Level bit 1 position. */ - -#define AC_HYSMODE_gm 0x06 /* Hysteresis Mode group mask. */ -#define AC_HYSMODE_gp 1 /* Hysteresis Mode group position. */ -#define AC_HYSMODE0_bm (1<<1) /* Hysteresis Mode bit 0 mask. */ -#define AC_HYSMODE0_bp 1 /* Hysteresis Mode bit 0 position. */ -#define AC_HYSMODE1_bm (1<<2) /* Hysteresis Mode bit 1 mask. */ -#define AC_HYSMODE1_bp 2 /* Hysteresis Mode bit 1 position. */ - -#define AC_ENABLE_bm 0x01 /* Enable bit mask. */ -#define AC_ENABLE_bp 0 /* Enable bit position. */ - -/* AC.AC1CTRL bit masks and bit positions */ -/* AC_INTMODE Predefined. */ -/* AC_INTMODE Predefined. */ - -/* AC_INTLVL Predefined. */ -/* AC_INTLVL Predefined. */ - -/* AC_HYSMODE Predefined. */ -/* AC_HYSMODE Predefined. */ - -/* AC_ENABLE Predefined. */ -/* AC_ENABLE Predefined. */ - -/* AC.AC0MUXCTRL bit masks and bit positions */ -#define AC_MUXPOS_gm 0x38 /* MUX Positive Input group mask. */ -#define AC_MUXPOS_gp 3 /* MUX Positive Input group position. */ -#define AC_MUXPOS0_bm (1<<3) /* MUX Positive Input bit 0 mask. */ -#define AC_MUXPOS0_bp 3 /* MUX Positive Input bit 0 position. */ -#define AC_MUXPOS1_bm (1<<4) /* MUX Positive Input bit 1 mask. */ -#define AC_MUXPOS1_bp 4 /* MUX Positive Input bit 1 position. */ -#define AC_MUXPOS2_bm (1<<5) /* MUX Positive Input bit 2 mask. */ -#define AC_MUXPOS2_bp 5 /* MUX Positive Input bit 2 position. */ - -#define AC_MUXNEG_gm 0x07 /* MUX Negative Input group mask. */ -#define AC_MUXNEG_gp 0 /* MUX Negative Input group position. */ -#define AC_MUXNEG0_bm (1<<0) /* MUX Negative Input bit 0 mask. */ -#define AC_MUXNEG0_bp 0 /* MUX Negative Input bit 0 position. */ -#define AC_MUXNEG1_bm (1<<1) /* MUX Negative Input bit 1 mask. */ -#define AC_MUXNEG1_bp 1 /* MUX Negative Input bit 1 position. */ -#define AC_MUXNEG2_bm (1<<2) /* MUX Negative Input bit 2 mask. */ -#define AC_MUXNEG2_bp 2 /* MUX Negative Input bit 2 position. */ - -/* AC.AC1MUXCTRL bit masks and bit positions */ -/* AC_MUXPOS Predefined. */ -/* AC_MUXPOS Predefined. */ - -/* AC_MUXNEG Predefined. */ -/* AC_MUXNEG Predefined. */ - -/* AC.CTRLA bit masks and bit positions */ -#define AC_AC1OUT_bm 0x02 /* Analog Comparator 1 Output Enable bit mask. */ -#define AC_AC1OUT_bp 1 /* Analog Comparator 1 Output Enable bit position. */ - -#define AC_AC0OUT_bm 0x01 /* Analog Comparator 0 Output Enable bit mask. */ -#define AC_AC0OUT_bp 0 /* Analog Comparator 0 Output Enable bit position. */ - -/* AC.CTRLB bit masks and bit positions */ -#define AC_SCALEFAC_gm 0x3F /* VCC Voltage Scaler Factor group mask. */ -#define AC_SCALEFAC_gp 0 /* VCC Voltage Scaler Factor group position. */ -#define AC_SCALEFAC0_bm (1<<0) /* VCC Voltage Scaler Factor bit 0 mask. */ -#define AC_SCALEFAC0_bp 0 /* VCC Voltage Scaler Factor bit 0 position. */ -#define AC_SCALEFAC1_bm (1<<1) /* VCC Voltage Scaler Factor bit 1 mask. */ -#define AC_SCALEFAC1_bp 1 /* VCC Voltage Scaler Factor bit 1 position. */ -#define AC_SCALEFAC2_bm (1<<2) /* VCC Voltage Scaler Factor bit 2 mask. */ -#define AC_SCALEFAC2_bp 2 /* VCC Voltage Scaler Factor bit 2 position. */ -#define AC_SCALEFAC3_bm (1<<3) /* VCC Voltage Scaler Factor bit 3 mask. */ -#define AC_SCALEFAC3_bp 3 /* VCC Voltage Scaler Factor bit 3 position. */ -#define AC_SCALEFAC4_bm (1<<4) /* VCC Voltage Scaler Factor bit 4 mask. */ -#define AC_SCALEFAC4_bp 4 /* VCC Voltage Scaler Factor bit 4 position. */ -#define AC_SCALEFAC5_bm (1<<5) /* VCC Voltage Scaler Factor bit 5 mask. */ -#define AC_SCALEFAC5_bp 5 /* VCC Voltage Scaler Factor bit 5 position. */ - -/* AC.WINCTRL bit masks and bit positions */ -#define AC_WEN_bm 0x10 /* Window Mode Enable bit mask. */ -#define AC_WEN_bp 4 /* Window Mode Enable bit position. */ - -#define AC_WINTMODE_gm 0x0C /* Window Interrupt Mode group mask. */ -#define AC_WINTMODE_gp 2 /* Window Interrupt Mode group position. */ -#define AC_WINTMODE0_bm (1<<2) /* Window Interrupt Mode bit 0 mask. */ -#define AC_WINTMODE0_bp 2 /* Window Interrupt Mode bit 0 position. */ -#define AC_WINTMODE1_bm (1<<3) /* Window Interrupt Mode bit 1 mask. */ -#define AC_WINTMODE1_bp 3 /* Window Interrupt Mode bit 1 position. */ - -#define AC_WINTLVL_gm 0x03 /* Window Interrupt Level group mask. */ -#define AC_WINTLVL_gp 0 /* Window Interrupt Level group position. */ -#define AC_WINTLVL0_bm (1<<0) /* Window Interrupt Level bit 0 mask. */ -#define AC_WINTLVL0_bp 0 /* Window Interrupt Level bit 0 position. */ -#define AC_WINTLVL1_bm (1<<1) /* Window Interrupt Level bit 1 mask. */ -#define AC_WINTLVL1_bp 1 /* Window Interrupt Level bit 1 position. */ - -/* AC.STATUS bit masks and bit positions */ -#define AC_WSTATE_gm 0xC0 /* Window Mode State group mask. */ -#define AC_WSTATE_gp 6 /* Window Mode State group position. */ -#define AC_WSTATE0_bm (1<<6) /* Window Mode State bit 0 mask. */ -#define AC_WSTATE0_bp 6 /* Window Mode State bit 0 position. */ -#define AC_WSTATE1_bm (1<<7) /* Window Mode State bit 1 mask. */ -#define AC_WSTATE1_bp 7 /* Window Mode State bit 1 position. */ - -#define AC_AC1STATE_bm 0x20 /* Analog Comparator 1 State bit mask. */ -#define AC_AC1STATE_bp 5 /* Analog Comparator 1 State bit position. */ - -#define AC_AC0STATE_bm 0x10 /* Analog Comparator 0 State bit mask. */ -#define AC_AC0STATE_bp 4 /* Analog Comparator 0 State bit position. */ - -#define AC_WIF_bm 0x04 /* Window Mode Interrupt Flag bit mask. */ -#define AC_WIF_bp 2 /* Window Mode Interrupt Flag bit position. */ - -#define AC_AC1IF_bm 0x02 /* Analog Comparator 1 Interrupt Flag bit mask. */ -#define AC_AC1IF_bp 1 /* Analog Comparator 1 Interrupt Flag bit position. */ - -#define AC_AC0IF_bm 0x01 /* Analog Comparator 0 Interrupt Flag bit mask. */ -#define AC_AC0IF_bp 0 /* Analog Comparator 0 Interrupt Flag bit position. */ - -/* AC.CURRCTRL bit masks and bit positions */ -#define AC_CURREN_bm 0x80 /* Current Source Enable bit mask. */ -#define AC_CURREN_bp 7 /* Current Source Enable bit position. */ - -#define AC_CURRMODE_bm 0x40 /* Current Mode bit mask. */ -#define AC_CURRMODE_bp 6 /* Current Mode bit position. */ - -#define AC_AC1CURR_bm 0x02 /* Analog Comparator 1 current source output bit mask. */ -#define AC_AC1CURR_bp 1 /* Analog Comparator 1 current source output bit position. */ - -#define AC_AC0CURR_bm 0x01 /* Analog Comparator 0 current source output bit mask. */ -#define AC_AC0CURR_bp 0 /* Analog Comparator 0 current source output bit position. */ - -/* AC.CURRCALIB bit masks and bit positions */ -#define AC_CALIB_gm 0x0F /* Current Source Calibration group mask. */ -#define AC_CALIB_gp 0 /* Current Source Calibration group position. */ -#define AC_CALIB0_bm (1<<0) /* Current Source Calibration bit 0 mask. */ -#define AC_CALIB0_bp 0 /* Current Source Calibration bit 0 position. */ -#define AC_CALIB1_bm (1<<1) /* Current Source Calibration bit 1 mask. */ -#define AC_CALIB1_bp 1 /* Current Source Calibration bit 1 position. */ -#define AC_CALIB2_bm (1<<2) /* Current Source Calibration bit 2 mask. */ -#define AC_CALIB2_bp 2 /* Current Source Calibration bit 2 position. */ -#define AC_CALIB3_bm (1<<3) /* Current Source Calibration bit 3 mask. */ -#define AC_CALIB3_bp 3 /* Current Source Calibration bit 3 position. */ - -/* RTC - Real-Time Counter */ -/* RTC.CTRL bit masks and bit positions */ -#define RTC_PRESCALER_gm 0x07 /* Prescaling Factor group mask. */ -#define RTC_PRESCALER_gp 0 /* Prescaling Factor group position. */ -#define RTC_PRESCALER0_bm (1<<0) /* Prescaling Factor bit 0 mask. */ -#define RTC_PRESCALER0_bp 0 /* Prescaling Factor bit 0 position. */ -#define RTC_PRESCALER1_bm (1<<1) /* Prescaling Factor bit 1 mask. */ -#define RTC_PRESCALER1_bp 1 /* Prescaling Factor bit 1 position. */ -#define RTC_PRESCALER2_bm (1<<2) /* Prescaling Factor bit 2 mask. */ -#define RTC_PRESCALER2_bp 2 /* Prescaling Factor bit 2 position. */ - -/* RTC.STATUS bit masks and bit positions */ -#define RTC_SYNCBUSY_bm 0x01 /* Synchronization Busy Flag bit mask. */ -#define RTC_SYNCBUSY_bp 0 /* Synchronization Busy Flag bit position. */ - -/* RTC.INTCTRL bit masks and bit positions */ -#define RTC_COMPINTLVL_gm 0x0C /* Compare Match Interrupt Level group mask. */ -#define RTC_COMPINTLVL_gp 2 /* Compare Match Interrupt Level group position. */ -#define RTC_COMPINTLVL0_bm (1<<2) /* Compare Match Interrupt Level bit 0 mask. */ -#define RTC_COMPINTLVL0_bp 2 /* Compare Match Interrupt Level bit 0 position. */ -#define RTC_COMPINTLVL1_bm (1<<3) /* Compare Match Interrupt Level bit 1 mask. */ -#define RTC_COMPINTLVL1_bp 3 /* Compare Match Interrupt Level bit 1 position. */ - -#define RTC_OVFINTLVL_gm 0x03 /* Overflow Interrupt Level group mask. */ -#define RTC_OVFINTLVL_gp 0 /* Overflow Interrupt Level group position. */ -#define RTC_OVFINTLVL0_bm (1<<0) /* Overflow Interrupt Level bit 0 mask. */ -#define RTC_OVFINTLVL0_bp 0 /* Overflow Interrupt Level bit 0 position. */ -#define RTC_OVFINTLVL1_bm (1<<1) /* Overflow Interrupt Level bit 1 mask. */ -#define RTC_OVFINTLVL1_bp 1 /* Overflow Interrupt Level bit 1 position. */ - -/* RTC.INTFLAGS bit masks and bit positions */ -#define RTC_COMPIF_bm 0x02 /* Compare Match Interrupt Flag bit mask. */ -#define RTC_COMPIF_bp 1 /* Compare Match Interrupt Flag bit position. */ - -#define RTC_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ -#define RTC_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ - -/* TWI - Two-Wire Interface */ -/* TWI_MASTER.CTRLA bit masks and bit positions */ -#define TWI_MASTER_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ -#define TWI_MASTER_INTLVL_gp 6 /* Interrupt Level group position. */ -#define TWI_MASTER_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ -#define TWI_MASTER_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ -#define TWI_MASTER_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ -#define TWI_MASTER_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ - -#define TWI_MASTER_RIEN_bm 0x20 /* Read Interrupt Enable bit mask. */ -#define TWI_MASTER_RIEN_bp 5 /* Read Interrupt Enable bit position. */ - -#define TWI_MASTER_WIEN_bm 0x10 /* Write Interrupt Enable bit mask. */ -#define TWI_MASTER_WIEN_bp 4 /* Write Interrupt Enable bit position. */ - -#define TWI_MASTER_ENABLE_bm 0x08 /* Enable TWI Master bit mask. */ -#define TWI_MASTER_ENABLE_bp 3 /* Enable TWI Master bit position. */ - -/* TWI_MASTER.CTRLB bit masks and bit positions */ -#define TWI_MASTER_TIMEOUT_gm 0x0C /* Inactive Bus Timeout group mask. */ -#define TWI_MASTER_TIMEOUT_gp 2 /* Inactive Bus Timeout group position. */ -#define TWI_MASTER_TIMEOUT0_bm (1<<2) /* Inactive Bus Timeout bit 0 mask. */ -#define TWI_MASTER_TIMEOUT0_bp 2 /* Inactive Bus Timeout bit 0 position. */ -#define TWI_MASTER_TIMEOUT1_bm (1<<3) /* Inactive Bus Timeout bit 1 mask. */ -#define TWI_MASTER_TIMEOUT1_bp 3 /* Inactive Bus Timeout bit 1 position. */ - -#define TWI_MASTER_QCEN_bm 0x02 /* Quick Command Enable bit mask. */ -#define TWI_MASTER_QCEN_bp 1 /* Quick Command Enable bit position. */ - -#define TWI_MASTER_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ -#define TWI_MASTER_SMEN_bp 0 /* Smart Mode Enable bit position. */ - -/* TWI_MASTER.CTRLC bit masks and bit positions */ -#define TWI_MASTER_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ -#define TWI_MASTER_ACKACT_bp 2 /* Acknowledge Action bit position. */ - -#define TWI_MASTER_CMD_gm 0x03 /* Command group mask. */ -#define TWI_MASTER_CMD_gp 0 /* Command group position. */ -#define TWI_MASTER_CMD0_bm (1<<0) /* Command bit 0 mask. */ -#define TWI_MASTER_CMD0_bp 0 /* Command bit 0 position. */ -#define TWI_MASTER_CMD1_bm (1<<1) /* Command bit 1 mask. */ -#define TWI_MASTER_CMD1_bp 1 /* Command bit 1 position. */ - -/* TWI_MASTER.STATUS bit masks and bit positions */ -#define TWI_MASTER_RIF_bm 0x80 /* Read Interrupt Flag bit mask. */ -#define TWI_MASTER_RIF_bp 7 /* Read Interrupt Flag bit position. */ - -#define TWI_MASTER_WIF_bm 0x40 /* Write Interrupt Flag bit mask. */ -#define TWI_MASTER_WIF_bp 6 /* Write Interrupt Flag bit position. */ - -#define TWI_MASTER_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ -#define TWI_MASTER_CLKHOLD_bp 5 /* Clock Hold bit position. */ - -#define TWI_MASTER_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ -#define TWI_MASTER_RXACK_bp 4 /* Received Acknowledge bit position. */ - -#define TWI_MASTER_ARBLOST_bm 0x08 /* Arbitration Lost bit mask. */ -#define TWI_MASTER_ARBLOST_bp 3 /* Arbitration Lost bit position. */ - -#define TWI_MASTER_BUSERR_bm 0x04 /* Bus Error bit mask. */ -#define TWI_MASTER_BUSERR_bp 2 /* Bus Error bit position. */ - -#define TWI_MASTER_BUSSTATE_gm 0x03 /* Bus State group mask. */ -#define TWI_MASTER_BUSSTATE_gp 0 /* Bus State group position. */ -#define TWI_MASTER_BUSSTATE0_bm (1<<0) /* Bus State bit 0 mask. */ -#define TWI_MASTER_BUSSTATE0_bp 0 /* Bus State bit 0 position. */ -#define TWI_MASTER_BUSSTATE1_bm (1<<1) /* Bus State bit 1 mask. */ -#define TWI_MASTER_BUSSTATE1_bp 1 /* Bus State bit 1 position. */ - -/* TWI_SLAVE.CTRLA bit masks and bit positions */ -#define TWI_SLAVE_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ -#define TWI_SLAVE_INTLVL_gp 6 /* Interrupt Level group position. */ -#define TWI_SLAVE_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ -#define TWI_SLAVE_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ -#define TWI_SLAVE_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ -#define TWI_SLAVE_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ - -#define TWI_SLAVE_DIEN_bm 0x20 /* Data Interrupt Enable bit mask. */ -#define TWI_SLAVE_DIEN_bp 5 /* Data Interrupt Enable bit position. */ - -#define TWI_SLAVE_APIEN_bm 0x10 /* Address/Stop Interrupt Enable bit mask. */ -#define TWI_SLAVE_APIEN_bp 4 /* Address/Stop Interrupt Enable bit position. */ - -#define TWI_SLAVE_ENABLE_bm 0x08 /* Enable TWI Slave bit mask. */ -#define TWI_SLAVE_ENABLE_bp 3 /* Enable TWI Slave bit position. */ - -#define TWI_SLAVE_PIEN_bm 0x04 /* Stop Interrupt Enable bit mask. */ -#define TWI_SLAVE_PIEN_bp 2 /* Stop Interrupt Enable bit position. */ - -#define TWI_SLAVE_PMEN_bm 0x02 /* Promiscuous Mode Enable bit mask. */ -#define TWI_SLAVE_PMEN_bp 1 /* Promiscuous Mode Enable bit position. */ - -#define TWI_SLAVE_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ -#define TWI_SLAVE_SMEN_bp 0 /* Smart Mode Enable bit position. */ - -/* TWI_SLAVE.CTRLB bit masks and bit positions */ -#define TWI_SLAVE_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ -#define TWI_SLAVE_ACKACT_bp 2 /* Acknowledge Action bit position. */ - -#define TWI_SLAVE_CMD_gm 0x03 /* Command group mask. */ -#define TWI_SLAVE_CMD_gp 0 /* Command group position. */ -#define TWI_SLAVE_CMD0_bm (1<<0) /* Command bit 0 mask. */ -#define TWI_SLAVE_CMD0_bp 0 /* Command bit 0 position. */ -#define TWI_SLAVE_CMD1_bm (1<<1) /* Command bit 1 mask. */ -#define TWI_SLAVE_CMD1_bp 1 /* Command bit 1 position. */ - -/* TWI_SLAVE.STATUS bit masks and bit positions */ -#define TWI_SLAVE_DIF_bm 0x80 /* Data Interrupt Flag bit mask. */ -#define TWI_SLAVE_DIF_bp 7 /* Data Interrupt Flag bit position. */ - -#define TWI_SLAVE_APIF_bm 0x40 /* Address/Stop Interrupt Flag bit mask. */ -#define TWI_SLAVE_APIF_bp 6 /* Address/Stop Interrupt Flag bit position. */ - -#define TWI_SLAVE_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ -#define TWI_SLAVE_CLKHOLD_bp 5 /* Clock Hold bit position. */ - -#define TWI_SLAVE_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ -#define TWI_SLAVE_RXACK_bp 4 /* Received Acknowledge bit position. */ - -#define TWI_SLAVE_COLL_bm 0x08 /* Collision bit mask. */ -#define TWI_SLAVE_COLL_bp 3 /* Collision bit position. */ - -#define TWI_SLAVE_BUSERR_bm 0x04 /* Bus Error bit mask. */ -#define TWI_SLAVE_BUSERR_bp 2 /* Bus Error bit position. */ - -#define TWI_SLAVE_DIR_bm 0x02 /* Read/Write Direction bit mask. */ -#define TWI_SLAVE_DIR_bp 1 /* Read/Write Direction bit position. */ - -#define TWI_SLAVE_AP_bm 0x01 /* Slave Address or Stop bit mask. */ -#define TWI_SLAVE_AP_bp 0 /* Slave Address or Stop bit position. */ - -/* TWI_SLAVE.ADDRMASK bit masks and bit positions */ -#define TWI_SLAVE_ADDRMASK_gm 0xFE /* Address Mask group mask. */ -#define TWI_SLAVE_ADDRMASK_gp 1 /* Address Mask group position. */ -#define TWI_SLAVE_ADDRMASK0_bm (1<<1) /* Address Mask bit 0 mask. */ -#define TWI_SLAVE_ADDRMASK0_bp 1 /* Address Mask bit 0 position. */ -#define TWI_SLAVE_ADDRMASK1_bm (1<<2) /* Address Mask bit 1 mask. */ -#define TWI_SLAVE_ADDRMASK1_bp 2 /* Address Mask bit 1 position. */ -#define TWI_SLAVE_ADDRMASK2_bm (1<<3) /* Address Mask bit 2 mask. */ -#define TWI_SLAVE_ADDRMASK2_bp 3 /* Address Mask bit 2 position. */ -#define TWI_SLAVE_ADDRMASK3_bm (1<<4) /* Address Mask bit 3 mask. */ -#define TWI_SLAVE_ADDRMASK3_bp 4 /* Address Mask bit 3 position. */ -#define TWI_SLAVE_ADDRMASK4_bm (1<<5) /* Address Mask bit 4 mask. */ -#define TWI_SLAVE_ADDRMASK4_bp 5 /* Address Mask bit 4 position. */ -#define TWI_SLAVE_ADDRMASK5_bm (1<<6) /* Address Mask bit 5 mask. */ -#define TWI_SLAVE_ADDRMASK5_bp 6 /* Address Mask bit 5 position. */ -#define TWI_SLAVE_ADDRMASK6_bm (1<<7) /* Address Mask bit 6 mask. */ -#define TWI_SLAVE_ADDRMASK6_bp 7 /* Address Mask bit 6 position. */ - -#define TWI_SLAVE_ADDREN_bm 0x01 /* Address Enable bit mask. */ -#define TWI_SLAVE_ADDREN_bp 0 /* Address Enable bit position. */ - -/* TWI.CTRL bit masks and bit positions */ -#define TWI_SDAHOLD_gm 0x06 /* SDA Hold Time Enable group mask. */ -#define TWI_SDAHOLD_gp 1 /* SDA Hold Time Enable group position. */ -#define TWI_SDAHOLD0_bm (1<<1) /* SDA Hold Time Enable bit 0 mask. */ -#define TWI_SDAHOLD0_bp 1 /* SDA Hold Time Enable bit 0 position. */ -#define TWI_SDAHOLD1_bm (1<<2) /* SDA Hold Time Enable bit 1 mask. */ -#define TWI_SDAHOLD1_bp 2 /* SDA Hold Time Enable bit 1 position. */ - -#define TWI_EDIEN_bm 0x01 /* External Driver Interface Enable bit mask. */ -#define TWI_EDIEN_bp 0 /* External Driver Interface Enable bit position. */ - -/* USB - USB */ -/* USB_EP.STATUS bit masks and bit positions */ -#define USB_EP_STALLF_bm 0x80 /* Endpoint Stall Flag bit mask. */ -#define USB_EP_STALLF_bp 7 /* Endpoint Stall Flag bit position. */ - -#define USB_EP_CRC_bm 0x80 /* CRC Error Flag bit mask. */ -#define USB_EP_CRC_bp 7 /* CRC Error Flag bit position. */ - -#define USB_EP_UNF_bm 0x40 /* Underflow Enpoint FLag bit mask. */ -#define USB_EP_UNF_bp 6 /* Underflow Enpoint FLag bit position. */ - -#define USB_EP_OVF_bm 0x40 /* Overflow Enpoint Flag for Output Endpoints bit mask. */ -#define USB_EP_OVF_bp 6 /* Overflow Enpoint Flag for Output Endpoints bit position. */ - -#define USB_EP_TRNCOMPL0_bm 0x20 /* Transaction Complete 0 Flag bit mask. */ -#define USB_EP_TRNCOMPL0_bp 5 /* Transaction Complete 0 Flag bit position. */ - -#define USB_EP_TRNCOMPL1_bm 0x10 /* Transaction Complete 1 Flag bit mask. */ -#define USB_EP_TRNCOMPL1_bp 4 /* Transaction Complete 1 Flag bit position. */ - -#define USB_EP_SETUP_bm 0x10 /* SETUP Transaction Complete Flag bit mask. */ -#define USB_EP_SETUP_bp 4 /* SETUP Transaction Complete Flag bit position. */ - -#define USB_EP_BANK_bm 0x08 /* Bank Select bit mask. */ -#define USB_EP_BANK_bp 3 /* Bank Select bit position. */ - -#define USB_EP_BUSNACK1_bm 0x04 /* Data Buffer 1 Not Acknowledge bit mask. */ -#define USB_EP_BUSNACK1_bp 2 /* Data Buffer 1 Not Acknowledge bit position. */ - -#define USB_EP_BUSNACK0_bm 0x02 /* Data Buffer 0 Not Acknowledge bit mask. */ -#define USB_EP_BUSNACK0_bp 1 /* Data Buffer 0 Not Acknowledge bit position. */ - -#define USB_EP_TOGGLE_bm 0x01 /* Data Toggle bit mask. */ -#define USB_EP_TOGGLE_bp 0 /* Data Toggle bit position. */ - -/* USB_EP.CTRL bit masks and bit positions */ -#define USB_EP_TYPE_gm 0xC0 /* Endpoint Type group mask. */ -#define USB_EP_TYPE_gp 6 /* Endpoint Type group position. */ -#define USB_EP_TYPE0_bm (1<<6) /* Endpoint Type bit 0 mask. */ -#define USB_EP_TYPE0_bp 6 /* Endpoint Type bit 0 position. */ -#define USB_EP_TYPE1_bm (1<<7) /* Endpoint Type bit 1 mask. */ -#define USB_EP_TYPE1_bp 7 /* Endpoint Type bit 1 position. */ - -#define USB_EP_MULTIPKT_bm 0x20 /* Multi Packet Transfer Enable bit mask. */ -#define USB_EP_MULTIPKT_bp 5 /* Multi Packet Transfer Enable bit position. */ - -#define USB_EP_PINGPONG_bm 0x10 /* Ping-Pong Enable bit mask. */ -#define USB_EP_PINGPONG_bp 4 /* Ping-Pong Enable bit position. */ - -#define USB_EP_INTDSBL_bm 0x08 /* Interrupt Disable bit mask. */ -#define USB_EP_INTDSBL_bp 3 /* Interrupt Disable bit position. */ - -#define USB_EP_STALL_bm 0x04 /* Data Stall bit mask. */ -#define USB_EP_STALL_bp 2 /* Data Stall bit position. */ - -#define USB_EP_BUFSIZE_gm 0x07 /* Data Buffer Size group mask. */ -#define USB_EP_BUFSIZE_gp 0 /* Data Buffer Size group position. */ -#define USB_EP_BUFSIZE0_bm (1<<0) /* Data Buffer Size bit 0 mask. */ -#define USB_EP_BUFSIZE0_bp 0 /* Data Buffer Size bit 0 position. */ -#define USB_EP_BUFSIZE1_bm (1<<1) /* Data Buffer Size bit 1 mask. */ -#define USB_EP_BUFSIZE1_bp 1 /* Data Buffer Size bit 1 position. */ -#define USB_EP_BUFSIZE2_bm (1<<2) /* Data Buffer Size bit 2 mask. */ -#define USB_EP_BUFSIZE2_bp 2 /* Data Buffer Size bit 2 position. */ - -/* USB_EP.CNT bit masks and bit positions */ -#define USB_EP_ZLP_bm 0x8000 /* Zero Length Packet bit mask. */ -#define USB_EP_ZLP_bp 15 /* Zero Length Packet bit position. */ - -/* USB.CTRLA bit masks and bit positions */ -#define USB_ENABLE_bm 0x80 /* USB Enable bit mask. */ -#define USB_ENABLE_bp 7 /* USB Enable bit position. */ - -#define USB_SPEED_bm 0x40 /* Speed Select bit mask. */ -#define USB_SPEED_bp 6 /* Speed Select bit position. */ - -#define USB_FIFOEN_bm 0x20 /* USB FIFO Enable bit mask. */ -#define USB_FIFOEN_bp 5 /* USB FIFO Enable bit position. */ - -#define USB_STFRNUM_bm 0x10 /* Store Frame Number Enable bit mask. */ -#define USB_STFRNUM_bp 4 /* Store Frame Number Enable bit position. */ - -#define USB_MAXEP_gm 0x0F /* Maximum Endpoint Addresses group mask. */ -#define USB_MAXEP_gp 0 /* Maximum Endpoint Addresses group position. */ -#define USB_MAXEP0_bm (1<<0) /* Maximum Endpoint Addresses bit 0 mask. */ -#define USB_MAXEP0_bp 0 /* Maximum Endpoint Addresses bit 0 position. */ -#define USB_MAXEP1_bm (1<<1) /* Maximum Endpoint Addresses bit 1 mask. */ -#define USB_MAXEP1_bp 1 /* Maximum Endpoint Addresses bit 1 position. */ -#define USB_MAXEP2_bm (1<<2) /* Maximum Endpoint Addresses bit 2 mask. */ -#define USB_MAXEP2_bp 2 /* Maximum Endpoint Addresses bit 2 position. */ -#define USB_MAXEP3_bm (1<<3) /* Maximum Endpoint Addresses bit 3 mask. */ -#define USB_MAXEP3_bp 3 /* Maximum Endpoint Addresses bit 3 position. */ - -/* USB.CTRLB bit masks and bit positions */ -#define USB_PULLRST_bm 0x10 /* Pull during Reset bit mask. */ -#define USB_PULLRST_bp 4 /* Pull during Reset bit position. */ - -#define USB_RWAKEUP_bm 0x04 /* Remote Wake-up bit mask. */ -#define USB_RWAKEUP_bp 2 /* Remote Wake-up bit position. */ - -#define USB_GNACK_bm 0x02 /* Global NACK bit mask. */ -#define USB_GNACK_bp 1 /* Global NACK bit position. */ - -#define USB_ATTACH_bm 0x01 /* Attach bit mask. */ -#define USB_ATTACH_bp 0 /* Attach bit position. */ - -/* USB.STATUS bit masks and bit positions */ -#define USB_URESUME_bm 0x08 /* Upstream Resume bit mask. */ -#define USB_URESUME_bp 3 /* Upstream Resume bit position. */ - -#define USB_RESUME_bm 0x04 /* Resume bit mask. */ -#define USB_RESUME_bp 2 /* Resume bit position. */ - -#define USB_SUSPEND_bm 0x02 /* Bus Suspended bit mask. */ -#define USB_SUSPEND_bp 1 /* Bus Suspended bit position. */ - -#define USB_BUSRST_bm 0x01 /* Bus Reset bit mask. */ -#define USB_BUSRST_bp 0 /* Bus Reset bit position. */ - -/* USB.ADDR bit masks and bit positions */ -#define USB_ADDR_gm 0x7F /* Device Address group mask. */ -#define USB_ADDR_gp 0 /* Device Address group position. */ -#define USB_ADDR0_bm (1<<0) /* Device Address bit 0 mask. */ -#define USB_ADDR0_bp 0 /* Device Address bit 0 position. */ -#define USB_ADDR1_bm (1<<1) /* Device Address bit 1 mask. */ -#define USB_ADDR1_bp 1 /* Device Address bit 1 position. */ -#define USB_ADDR2_bm (1<<2) /* Device Address bit 2 mask. */ -#define USB_ADDR2_bp 2 /* Device Address bit 2 position. */ -#define USB_ADDR3_bm (1<<3) /* Device Address bit 3 mask. */ -#define USB_ADDR3_bp 3 /* Device Address bit 3 position. */ -#define USB_ADDR4_bm (1<<4) /* Device Address bit 4 mask. */ -#define USB_ADDR4_bp 4 /* Device Address bit 4 position. */ -#define USB_ADDR5_bm (1<<5) /* Device Address bit 5 mask. */ -#define USB_ADDR5_bp 5 /* Device Address bit 5 position. */ -#define USB_ADDR6_bm (1<<6) /* Device Address bit 6 mask. */ -#define USB_ADDR6_bp 6 /* Device Address bit 6 position. */ - -/* USB.FIFOWP bit masks and bit positions */ -#define USB_FIFOWP_gm 0x1F /* FIFO Write Pointer group mask. */ -#define USB_FIFOWP_gp 0 /* FIFO Write Pointer group position. */ -#define USB_FIFOWP0_bm (1<<0) /* FIFO Write Pointer bit 0 mask. */ -#define USB_FIFOWP0_bp 0 /* FIFO Write Pointer bit 0 position. */ -#define USB_FIFOWP1_bm (1<<1) /* FIFO Write Pointer bit 1 mask. */ -#define USB_FIFOWP1_bp 1 /* FIFO Write Pointer bit 1 position. */ -#define USB_FIFOWP2_bm (1<<2) /* FIFO Write Pointer bit 2 mask. */ -#define USB_FIFOWP2_bp 2 /* FIFO Write Pointer bit 2 position. */ -#define USB_FIFOWP3_bm (1<<3) /* FIFO Write Pointer bit 3 mask. */ -#define USB_FIFOWP3_bp 3 /* FIFO Write Pointer bit 3 position. */ -#define USB_FIFOWP4_bm (1<<4) /* FIFO Write Pointer bit 4 mask. */ -#define USB_FIFOWP4_bp 4 /* FIFO Write Pointer bit 4 position. */ - -/* USB.FIFORP bit masks and bit positions */ -#define USB_FIFORP_gm 0x1F /* FIFO Read Pointer group mask. */ -#define USB_FIFORP_gp 0 /* FIFO Read Pointer group position. */ -#define USB_FIFORP0_bm (1<<0) /* FIFO Read Pointer bit 0 mask. */ -#define USB_FIFORP0_bp 0 /* FIFO Read Pointer bit 0 position. */ -#define USB_FIFORP1_bm (1<<1) /* FIFO Read Pointer bit 1 mask. */ -#define USB_FIFORP1_bp 1 /* FIFO Read Pointer bit 1 position. */ -#define USB_FIFORP2_bm (1<<2) /* FIFO Read Pointer bit 2 mask. */ -#define USB_FIFORP2_bp 2 /* FIFO Read Pointer bit 2 position. */ -#define USB_FIFORP3_bm (1<<3) /* FIFO Read Pointer bit 3 mask. */ -#define USB_FIFORP3_bp 3 /* FIFO Read Pointer bit 3 position. */ -#define USB_FIFORP4_bm (1<<4) /* FIFO Read Pointer bit 4 mask. */ -#define USB_FIFORP4_bp 4 /* FIFO Read Pointer bit 4 position. */ - -/* USB.INTCTRLA bit masks and bit positions */ -#define USB_SOFIE_bm 0x80 /* Start Of Frame Interrupt Enable bit mask. */ -#define USB_SOFIE_bp 7 /* Start Of Frame Interrupt Enable bit position. */ - -#define USB_BUSEVIE_bm 0x40 /* Bus Event Interrupt Enable bit mask. */ -#define USB_BUSEVIE_bp 6 /* Bus Event Interrupt Enable bit position. */ - -#define USB_BUSERRIE_bm 0x20 /* Bus Error Interrupt Enable bit mask. */ -#define USB_BUSERRIE_bp 5 /* Bus Error Interrupt Enable bit position. */ - -#define USB_STALLIE_bm 0x10 /* STALL Interrupt Enable bit mask. */ -#define USB_STALLIE_bp 4 /* STALL Interrupt Enable bit position. */ - -#define USB_INTLVL_gm 0x03 /* Interrupt Level group mask. */ -#define USB_INTLVL_gp 0 /* Interrupt Level group position. */ -#define USB_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */ -#define USB_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */ -#define USB_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ -#define USB_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */ - -/* USB.INTCTRLB bit masks and bit positions */ -#define USB_TRNIE_bm 0x02 /* Transaction Complete Interrupt Enable bit mask. */ -#define USB_TRNIE_bp 1 /* Transaction Complete Interrupt Enable bit position. */ - -#define USB_SETUPIE_bm 0x01 /* SETUP Transaction Complete Interrupt Enable bit mask. */ -#define USB_SETUPIE_bp 0 /* SETUP Transaction Complete Interrupt Enable bit position. */ - -/* USB.INTFLAGSACLR bit masks and bit positions */ -#define USB_SOFIF_bm 0x80 /* Start Of Frame Interrupt Flag bit mask. */ -#define USB_SOFIF_bp 7 /* Start Of Frame Interrupt Flag bit position. */ - -#define USB_SUSPENDIF_bm 0x40 /* Suspend Interrupt Flag bit mask. */ -#define USB_SUSPENDIF_bp 6 /* Suspend Interrupt Flag bit position. */ - -#define USB_RESUMEIF_bm 0x20 /* Resume Interrupt Flag bit mask. */ -#define USB_RESUMEIF_bp 5 /* Resume Interrupt Flag bit position. */ - -#define USB_RSTIF_bm 0x10 /* Reset Interrupt Flag bit mask. */ -#define USB_RSTIF_bp 4 /* Reset Interrupt Flag bit position. */ - -#define USB_CRCIF_bm 0x08 /* Isochronous CRC Error Interrupt Flag bit mask. */ -#define USB_CRCIF_bp 3 /* Isochronous CRC Error Interrupt Flag bit position. */ - -#define USB_UNFIF_bm 0x04 /* Underflow Interrupt Flag bit mask. */ -#define USB_UNFIF_bp 2 /* Underflow Interrupt Flag bit position. */ - -#define USB_OVFIF_bm 0x02 /* Overflow Interrupt Flag bit mask. */ -#define USB_OVFIF_bp 1 /* Overflow Interrupt Flag bit position. */ - -#define USB_STALLIF_bm 0x01 /* STALL Interrupt Flag bit mask. */ -#define USB_STALLIF_bp 0 /* STALL Interrupt Flag bit position. */ - -/* USB.INTFLAGSASET bit masks and bit positions */ -/* USB_SOFIF Predefined. */ -/* USB_SOFIF Predefined. */ - -/* USB_SUSPENDIF Predefined. */ -/* USB_SUSPENDIF Predefined. */ - -/* USB_RESUMEIF Predefined. */ -/* USB_RESUMEIF Predefined. */ - -/* USB_RSTIF Predefined. */ -/* USB_RSTIF Predefined. */ - -/* USB_CRCIF Predefined. */ -/* USB_CRCIF Predefined. */ - -/* USB_UNFIF Predefined. */ -/* USB_UNFIF Predefined. */ - -/* USB_OVFIF Predefined. */ -/* USB_OVFIF Predefined. */ - -/* USB_STALLIF Predefined. */ -/* USB_STALLIF Predefined. */ - -/* USB.INTFLAGSBCLR bit masks and bit positions */ -#define USB_TRNIF_bm 0x02 /* Transaction Complete Interrupt Flag bit mask. */ -#define USB_TRNIF_bp 1 /* Transaction Complete Interrupt Flag bit position. */ - -#define USB_SETUPIF_bm 0x01 /* SETUP Transaction Complete Interrupt Flag bit mask. */ -#define USB_SETUPIF_bp 0 /* SETUP Transaction Complete Interrupt Flag bit position. */ - -/* USB.INTFLAGSBSET bit masks and bit positions */ -/* USB_TRNIF Predefined. */ -/* USB_TRNIF Predefined. */ - -/* USB_SETUPIF Predefined. */ -/* USB_SETUPIF Predefined. */ - -/* PORT - I/O Port Configuration */ -/* PORT.INTCTRL bit masks and bit positions */ -#define PORT_INT1LVL_gm 0x0C /* Port Interrupt 1 Level group mask. */ -#define PORT_INT1LVL_gp 2 /* Port Interrupt 1 Level group position. */ -#define PORT_INT1LVL0_bm (1<<2) /* Port Interrupt 1 Level bit 0 mask. */ -#define PORT_INT1LVL0_bp 2 /* Port Interrupt 1 Level bit 0 position. */ -#define PORT_INT1LVL1_bm (1<<3) /* Port Interrupt 1 Level bit 1 mask. */ -#define PORT_INT1LVL1_bp 3 /* Port Interrupt 1 Level bit 1 position. */ - -#define PORT_INT0LVL_gm 0x03 /* Port Interrupt 0 Level group mask. */ -#define PORT_INT0LVL_gp 0 /* Port Interrupt 0 Level group position. */ -#define PORT_INT0LVL0_bm (1<<0) /* Port Interrupt 0 Level bit 0 mask. */ -#define PORT_INT0LVL0_bp 0 /* Port Interrupt 0 Level bit 0 position. */ -#define PORT_INT0LVL1_bm (1<<1) /* Port Interrupt 0 Level bit 1 mask. */ -#define PORT_INT0LVL1_bp 1 /* Port Interrupt 0 Level bit 1 position. */ - -/* PORT.INTFLAGS bit masks and bit positions */ -#define PORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ -#define PORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ - -#define PORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ -#define PORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ - -/* PORT.REMAP bit masks and bit positions */ -#define PORT_SPI_bm 0x20 /* SPI bit mask. */ -#define PORT_SPI_bp 5 /* SPI bit position. */ - -#define PORT_USART0_bm 0x10 /* USART0 bit mask. */ -#define PORT_USART0_bp 4 /* USART0 bit position. */ - -#define PORT_TC0D_bm 0x08 /* Timer/Counter 0 Output Compare D bit mask. */ -#define PORT_TC0D_bp 3 /* Timer/Counter 0 Output Compare D bit position. */ - -#define PORT_TC0C_bm 0x04 /* Timer/Counter 0 Output Compare C bit mask. */ -#define PORT_TC0C_bp 2 /* Timer/Counter 0 Output Compare C bit position. */ - -#define PORT_TC0B_bm 0x02 /* Timer/Counter 0 Output Compare B bit mask. */ -#define PORT_TC0B_bp 1 /* Timer/Counter 0 Output Compare B bit position. */ - -#define PORT_TC0A_bm 0x01 /* Timer/Counter 0 Output Compare A bit mask. */ -#define PORT_TC0A_bp 0 /* Timer/Counter 0 Output Compare A bit position. */ - -/* PORT.PIN0CTRL bit masks and bit positions */ -#define PORT_SRLEN_bm 0x80 /* Slew Rate Enable bit mask. */ -#define PORT_SRLEN_bp 7 /* Slew Rate Enable bit position. */ - -#define PORT_INVEN_bm 0x40 /* Inverted I/O Enable bit mask. */ -#define PORT_INVEN_bp 6 /* Inverted I/O Enable bit position. */ - -#define PORT_OPC_gm 0x38 /* Output/Pull Configuration group mask. */ -#define PORT_OPC_gp 3 /* Output/Pull Configuration group position. */ -#define PORT_OPC0_bm (1<<3) /* Output/Pull Configuration bit 0 mask. */ -#define PORT_OPC0_bp 3 /* Output/Pull Configuration bit 0 position. */ -#define PORT_OPC1_bm (1<<4) /* Output/Pull Configuration bit 1 mask. */ -#define PORT_OPC1_bp 4 /* Output/Pull Configuration bit 1 position. */ -#define PORT_OPC2_bm (1<<5) /* Output/Pull Configuration bit 2 mask. */ -#define PORT_OPC2_bp 5 /* Output/Pull Configuration bit 2 position. */ - -#define PORT_ISC_gm 0x07 /* Input/Sense Configuration group mask. */ -#define PORT_ISC_gp 0 /* Input/Sense Configuration group position. */ -#define PORT_ISC0_bm (1<<0) /* Input/Sense Configuration bit 0 mask. */ -#define PORT_ISC0_bp 0 /* Input/Sense Configuration bit 0 position. */ -#define PORT_ISC1_bm (1<<1) /* Input/Sense Configuration bit 1 mask. */ -#define PORT_ISC1_bp 1 /* Input/Sense Configuration bit 1 position. */ -#define PORT_ISC2_bm (1<<2) /* Input/Sense Configuration bit 2 mask. */ -#define PORT_ISC2_bp 2 /* Input/Sense Configuration bit 2 position. */ - -/* PORT.PIN1CTRL bit masks and bit positions */ -/* PORT_SRLEN Predefined. */ -/* PORT_SRLEN Predefined. */ - -/* PORT_INVEN Predefined. */ -/* PORT_INVEN Predefined. */ - -/* PORT_OPC Predefined. */ -/* PORT_OPC Predefined. */ - -/* PORT_ISC Predefined. */ -/* PORT_ISC Predefined. */ - -/* PORT.PIN2CTRL bit masks and bit positions */ -/* PORT_SRLEN Predefined. */ -/* PORT_SRLEN Predefined. */ - -/* PORT_INVEN Predefined. */ -/* PORT_INVEN Predefined. */ - -/* PORT_OPC Predefined. */ -/* PORT_OPC Predefined. */ - -/* PORT_ISC Predefined. */ -/* PORT_ISC Predefined. */ - -/* PORT.PIN3CTRL bit masks and bit positions */ -/* PORT_SRLEN Predefined. */ -/* PORT_SRLEN Predefined. */ - -/* PORT_INVEN Predefined. */ -/* PORT_INVEN Predefined. */ - -/* PORT_OPC Predefined. */ -/* PORT_OPC Predefined. */ - -/* PORT_ISC Predefined. */ -/* PORT_ISC Predefined. */ - -/* PORT.PIN4CTRL bit masks and bit positions */ -/* PORT_SRLEN Predefined. */ -/* PORT_SRLEN Predefined. */ - -/* PORT_INVEN Predefined. */ -/* PORT_INVEN Predefined. */ - -/* PORT_OPC Predefined. */ -/* PORT_OPC Predefined. */ - -/* PORT_ISC Predefined. */ -/* PORT_ISC Predefined. */ - -/* PORT.PIN5CTRL bit masks and bit positions */ -/* PORT_SRLEN Predefined. */ -/* PORT_SRLEN Predefined. */ - -/* PORT_INVEN Predefined. */ -/* PORT_INVEN Predefined. */ - -/* PORT_OPC Predefined. */ -/* PORT_OPC Predefined. */ - -/* PORT_ISC Predefined. */ -/* PORT_ISC Predefined. */ - -/* PORT.PIN6CTRL bit masks and bit positions */ -/* PORT_SRLEN Predefined. */ -/* PORT_SRLEN Predefined. */ - -/* PORT_INVEN Predefined. */ -/* PORT_INVEN Predefined. */ - -/* PORT_OPC Predefined. */ -/* PORT_OPC Predefined. */ - -/* PORT_ISC Predefined. */ -/* PORT_ISC Predefined. */ - -/* PORT.PIN7CTRL bit masks and bit positions */ -/* PORT_SRLEN Predefined. */ -/* PORT_SRLEN Predefined. */ - -/* PORT_INVEN Predefined. */ -/* PORT_INVEN Predefined. */ - -/* PORT_OPC Predefined. */ -/* PORT_OPC Predefined. */ - -/* PORT_ISC Predefined. */ -/* PORT_ISC Predefined. */ - -/* TC - 16-bit Timer/Counter With PWM */ -/* TC0.CTRLA bit masks and bit positions */ -#define TC0_CLKSEL_gm 0x0F /* Clock Selection group mask. */ -#define TC0_CLKSEL_gp 0 /* Clock Selection group position. */ -#define TC0_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ -#define TC0_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ -#define TC0_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ -#define TC0_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ -#define TC0_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ -#define TC0_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ -#define TC0_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ -#define TC0_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ - -/* TC0.CTRLB bit masks and bit positions */ -#define TC0_CCDEN_bm 0x80 /* Compare or Capture D Enable bit mask. */ -#define TC0_CCDEN_bp 7 /* Compare or Capture D Enable bit position. */ - -#define TC0_CCCEN_bm 0x40 /* Compare or Capture C Enable bit mask. */ -#define TC0_CCCEN_bp 6 /* Compare or Capture C Enable bit position. */ - -#define TC0_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ -#define TC0_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ - -#define TC0_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ -#define TC0_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ - -#define TC0_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ -#define TC0_WGMODE_gp 0 /* Waveform generation mode group position. */ -#define TC0_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ -#define TC0_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ -#define TC0_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ -#define TC0_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ -#define TC0_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ -#define TC0_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ - -/* TC0.CTRLC bit masks and bit positions */ -#define TC0_CMPD_bm 0x08 /* Compare D Output Value bit mask. */ -#define TC0_CMPD_bp 3 /* Compare D Output Value bit position. */ - -#define TC0_CMPC_bm 0x04 /* Compare C Output Value bit mask. */ -#define TC0_CMPC_bp 2 /* Compare C Output Value bit position. */ - -#define TC0_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ -#define TC0_CMPB_bp 1 /* Compare B Output Value bit position. */ - -#define TC0_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ -#define TC0_CMPA_bp 0 /* Compare A Output Value bit position. */ - -/* TC0.CTRLD bit masks and bit positions */ -#define TC0_EVACT_gm 0xE0 /* Event Action group mask. */ -#define TC0_EVACT_gp 5 /* Event Action group position. */ -#define TC0_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ -#define TC0_EVACT0_bp 5 /* Event Action bit 0 position. */ -#define TC0_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ -#define TC0_EVACT1_bp 6 /* Event Action bit 1 position. */ -#define TC0_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ -#define TC0_EVACT2_bp 7 /* Event Action bit 2 position. */ - -#define TC0_EVDLY_bm 0x10 /* Event Delay bit mask. */ -#define TC0_EVDLY_bp 4 /* Event Delay bit position. */ - -#define TC0_EVSEL_gm 0x0F /* Event Source Select group mask. */ -#define TC0_EVSEL_gp 0 /* Event Source Select group position. */ -#define TC0_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ -#define TC0_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ -#define TC0_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ -#define TC0_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ -#define TC0_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ -#define TC0_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ -#define TC0_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ -#define TC0_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ - -/* TC0.CTRLE bit masks and bit positions */ -#define TC0_BYTEM_gm 0x03 /* Byte Mode group mask. */ -#define TC0_BYTEM_gp 0 /* Byte Mode group position. */ -#define TC0_BYTEM0_bm (1<<0) /* Byte Mode bit 0 mask. */ -#define TC0_BYTEM0_bp 0 /* Byte Mode bit 0 position. */ -#define TC0_BYTEM1_bm (1<<1) /* Byte Mode bit 1 mask. */ -#define TC0_BYTEM1_bp 1 /* Byte Mode bit 1 position. */ - -/* TC0.INTCTRLA bit masks and bit positions */ -#define TC0_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ -#define TC0_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ -#define TC0_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ -#define TC0_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ -#define TC0_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ -#define TC0_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ - -#define TC0_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ -#define TC0_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ -#define TC0_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ -#define TC0_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ -#define TC0_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ -#define TC0_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ - -/* TC0.INTCTRLB bit masks and bit positions */ -#define TC0_CCDINTLVL_gm 0xC0 /* Compare or Capture D Interrupt Level group mask. */ -#define TC0_CCDINTLVL_gp 6 /* Compare or Capture D Interrupt Level group position. */ -#define TC0_CCDINTLVL0_bm (1<<6) /* Compare or Capture D Interrupt Level bit 0 mask. */ -#define TC0_CCDINTLVL0_bp 6 /* Compare or Capture D Interrupt Level bit 0 position. */ -#define TC0_CCDINTLVL1_bm (1<<7) /* Compare or Capture D Interrupt Level bit 1 mask. */ -#define TC0_CCDINTLVL1_bp 7 /* Compare or Capture D Interrupt Level bit 1 position. */ - -#define TC0_CCCINTLVL_gm 0x30 /* Compare or Capture C Interrupt Level group mask. */ -#define TC0_CCCINTLVL_gp 4 /* Compare or Capture C Interrupt Level group position. */ -#define TC0_CCCINTLVL0_bm (1<<4) /* Compare or Capture C Interrupt Level bit 0 mask. */ -#define TC0_CCCINTLVL0_bp 4 /* Compare or Capture C Interrupt Level bit 0 position. */ -#define TC0_CCCINTLVL1_bm (1<<5) /* Compare or Capture C Interrupt Level bit 1 mask. */ -#define TC0_CCCINTLVL1_bp 5 /* Compare or Capture C Interrupt Level bit 1 position. */ - -#define TC0_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ -#define TC0_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ -#define TC0_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ -#define TC0_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ -#define TC0_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ -#define TC0_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ - -#define TC0_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ -#define TC0_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ -#define TC0_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ -#define TC0_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ -#define TC0_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ -#define TC0_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ - -/* TC0.CTRLFCLR bit masks and bit positions */ -#define TC0_CMD_gm 0x0C /* Command group mask. */ -#define TC0_CMD_gp 2 /* Command group position. */ -#define TC0_CMD0_bm (1<<2) /* Command bit 0 mask. */ -#define TC0_CMD0_bp 2 /* Command bit 0 position. */ -#define TC0_CMD1_bm (1<<3) /* Command bit 1 mask. */ -#define TC0_CMD1_bp 3 /* Command bit 1 position. */ - -#define TC0_LUPD_bm 0x02 /* Lock Update bit mask. */ -#define TC0_LUPD_bp 1 /* Lock Update bit position. */ - -#define TC0_DIR_bm 0x01 /* Direction bit mask. */ -#define TC0_DIR_bp 0 /* Direction bit position. */ - -/* TC0.CTRLFSET bit masks and bit positions */ -/* TC0_CMD Predefined. */ -/* TC0_CMD Predefined. */ - -/* TC0_LUPD Predefined. */ -/* TC0_LUPD Predefined. */ - -/* TC0_DIR Predefined. */ -/* TC0_DIR Predefined. */ - -/* TC0.CTRLGCLR bit masks and bit positions */ -#define TC0_CCDBV_bm 0x10 /* Compare or Capture D Buffer Valid bit mask. */ -#define TC0_CCDBV_bp 4 /* Compare or Capture D Buffer Valid bit position. */ - -#define TC0_CCCBV_bm 0x08 /* Compare or Capture C Buffer Valid bit mask. */ -#define TC0_CCCBV_bp 3 /* Compare or Capture C Buffer Valid bit position. */ - -#define TC0_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ -#define TC0_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ - -#define TC0_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ -#define TC0_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ - -#define TC0_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ -#define TC0_PERBV_bp 0 /* Period Buffer Valid bit position. */ - -/* TC0.CTRLGSET bit masks and bit positions */ -/* TC0_CCDBV Predefined. */ -/* TC0_CCDBV Predefined. */ - -/* TC0_CCCBV Predefined. */ -/* TC0_CCCBV Predefined. */ - -/* TC0_CCBBV Predefined. */ -/* TC0_CCBBV Predefined. */ - -/* TC0_CCABV Predefined. */ -/* TC0_CCABV Predefined. */ - -/* TC0_PERBV Predefined. */ -/* TC0_PERBV Predefined. */ - -/* TC0.INTFLAGS bit masks and bit positions */ -#define TC0_CCDIF_bm 0x80 /* Compare or Capture D Interrupt Flag bit mask. */ -#define TC0_CCDIF_bp 7 /* Compare or Capture D Interrupt Flag bit position. */ - -#define TC0_CCCIF_bm 0x40 /* Compare or Capture C Interrupt Flag bit mask. */ -#define TC0_CCCIF_bp 6 /* Compare or Capture C Interrupt Flag bit position. */ - -#define TC0_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ -#define TC0_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ - -#define TC0_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ -#define TC0_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ - -#define TC0_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ -#define TC0_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ - -#define TC0_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ -#define TC0_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ - -/* TC1.CTRLA bit masks and bit positions */ -#define TC1_CLKSEL_gm 0x0F /* Clock Selection group mask. */ -#define TC1_CLKSEL_gp 0 /* Clock Selection group position. */ -#define TC1_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ -#define TC1_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ -#define TC1_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ -#define TC1_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ -#define TC1_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ -#define TC1_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ -#define TC1_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ -#define TC1_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ - -/* TC1.CTRLB bit masks and bit positions */ -#define TC1_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ -#define TC1_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ - -#define TC1_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ -#define TC1_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ - -#define TC1_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ -#define TC1_WGMODE_gp 0 /* Waveform generation mode group position. */ -#define TC1_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ -#define TC1_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ -#define TC1_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ -#define TC1_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ -#define TC1_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ -#define TC1_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ - -/* TC1.CTRLC bit masks and bit positions */ -#define TC1_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ -#define TC1_CMPB_bp 1 /* Compare B Output Value bit position. */ - -#define TC1_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ -#define TC1_CMPA_bp 0 /* Compare A Output Value bit position. */ - -/* TC1.CTRLD bit masks and bit positions */ -#define TC1_EVACT_gm 0xE0 /* Event Action group mask. */ -#define TC1_EVACT_gp 5 /* Event Action group position. */ -#define TC1_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ -#define TC1_EVACT0_bp 5 /* Event Action bit 0 position. */ -#define TC1_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ -#define TC1_EVACT1_bp 6 /* Event Action bit 1 position. */ -#define TC1_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ -#define TC1_EVACT2_bp 7 /* Event Action bit 2 position. */ - -#define TC1_EVDLY_bm 0x10 /* Event Delay bit mask. */ -#define TC1_EVDLY_bp 4 /* Event Delay bit position. */ - -#define TC1_EVSEL_gm 0x0F /* Event Source Select group mask. */ -#define TC1_EVSEL_gp 0 /* Event Source Select group position. */ -#define TC1_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ -#define TC1_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ -#define TC1_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ -#define TC1_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ -#define TC1_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ -#define TC1_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ -#define TC1_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ -#define TC1_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ - -/* TC1.CTRLE bit masks and bit positions */ -#define TC1_BYTEM_bm 0x01 /* Byte Mode bit mask. */ -#define TC1_BYTEM_bp 0 /* Byte Mode bit position. */ - -/* TC1.INTCTRLA bit masks and bit positions */ -#define TC1_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ -#define TC1_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ -#define TC1_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ -#define TC1_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ -#define TC1_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ -#define TC1_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ - -#define TC1_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ -#define TC1_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ -#define TC1_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ -#define TC1_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ -#define TC1_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ -#define TC1_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ - -/* TC1.INTCTRLB bit masks and bit positions */ -#define TC1_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ -#define TC1_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ -#define TC1_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ -#define TC1_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ -#define TC1_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ -#define TC1_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ - -#define TC1_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ -#define TC1_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ -#define TC1_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ -#define TC1_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ -#define TC1_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ -#define TC1_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ - -/* TC1.CTRLFCLR bit masks and bit positions */ -#define TC1_CMD_gm 0x0C /* Command group mask. */ -#define TC1_CMD_gp 2 /* Command group position. */ -#define TC1_CMD0_bm (1<<2) /* Command bit 0 mask. */ -#define TC1_CMD0_bp 2 /* Command bit 0 position. */ -#define TC1_CMD1_bm (1<<3) /* Command bit 1 mask. */ -#define TC1_CMD1_bp 3 /* Command bit 1 position. */ - -#define TC1_LUPD_bm 0x02 /* Lock Update bit mask. */ -#define TC1_LUPD_bp 1 /* Lock Update bit position. */ - -#define TC1_DIR_bm 0x01 /* Direction bit mask. */ -#define TC1_DIR_bp 0 /* Direction bit position. */ - -/* TC1.CTRLFSET bit masks and bit positions */ -/* TC1_CMD Predefined. */ -/* TC1_CMD Predefined. */ - -/* TC1_LUPD Predefined. */ -/* TC1_LUPD Predefined. */ - -/* TC1_DIR Predefined. */ -/* TC1_DIR Predefined. */ - -/* TC1.CTRLGCLR bit masks and bit positions */ -#define TC1_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ -#define TC1_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ - -#define TC1_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ -#define TC1_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ - -#define TC1_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ -#define TC1_PERBV_bp 0 /* Period Buffer Valid bit position. */ - -/* TC1.CTRLGSET bit masks and bit positions */ -/* TC1_CCBBV Predefined. */ -/* TC1_CCBBV Predefined. */ - -/* TC1_CCABV Predefined. */ -/* TC1_CCABV Predefined. */ - -/* TC1_PERBV Predefined. */ -/* TC1_PERBV Predefined. */ - -/* TC1.INTFLAGS bit masks and bit positions */ -#define TC1_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ -#define TC1_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ - -#define TC1_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ -#define TC1_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ - -#define TC1_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ -#define TC1_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ - -#define TC1_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ -#define TC1_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ - -/* AWEX - Timer/Counter Advanced Waveform Extension */ -/* AWEX.CTRL bit masks and bit positions */ -#define AWEX_PGM_bm 0x20 /* Pattern Generation Mode bit mask. */ -#define AWEX_PGM_bp 5 /* Pattern Generation Mode bit position. */ - -#define AWEX_CWCM_bm 0x10 /* Common Waveform Channel Mode bit mask. */ -#define AWEX_CWCM_bp 4 /* Common Waveform Channel Mode bit position. */ - -#define AWEX_DTICCDEN_bm 0x08 /* Dead Time Insertion Compare Channel D Enable bit mask. */ -#define AWEX_DTICCDEN_bp 3 /* Dead Time Insertion Compare Channel D Enable bit position. */ - -#define AWEX_DTICCCEN_bm 0x04 /* Dead Time Insertion Compare Channel C Enable bit mask. */ -#define AWEX_DTICCCEN_bp 2 /* Dead Time Insertion Compare Channel C Enable bit position. */ - -#define AWEX_DTICCBEN_bm 0x02 /* Dead Time Insertion Compare Channel B Enable bit mask. */ -#define AWEX_DTICCBEN_bp 1 /* Dead Time Insertion Compare Channel B Enable bit position. */ - -#define AWEX_DTICCAEN_bm 0x01 /* Dead Time Insertion Compare Channel A Enable bit mask. */ -#define AWEX_DTICCAEN_bp 0 /* Dead Time Insertion Compare Channel A Enable bit position. */ - -/* AWEX.FDCTRL bit masks and bit positions */ -#define AWEX_FDDBD_bm 0x10 /* Fault Detect on Disable Break Disable bit mask. */ -#define AWEX_FDDBD_bp 4 /* Fault Detect on Disable Break Disable bit position. */ - -#define AWEX_FDMODE_bm 0x04 /* Fault Detect Mode bit mask. */ -#define AWEX_FDMODE_bp 2 /* Fault Detect Mode bit position. */ - -#define AWEX_FDACT_gm 0x03 /* Fault Detect Action group mask. */ -#define AWEX_FDACT_gp 0 /* Fault Detect Action group position. */ -#define AWEX_FDACT0_bm (1<<0) /* Fault Detect Action bit 0 mask. */ -#define AWEX_FDACT0_bp 0 /* Fault Detect Action bit 0 position. */ -#define AWEX_FDACT1_bm (1<<1) /* Fault Detect Action bit 1 mask. */ -#define AWEX_FDACT1_bp 1 /* Fault Detect Action bit 1 position. */ - -/* AWEX.STATUS bit masks and bit positions */ -#define AWEX_FDF_bm 0x04 /* Fault Detect Flag bit mask. */ -#define AWEX_FDF_bp 2 /* Fault Detect Flag bit position. */ - -#define AWEX_DTHSBUFV_bm 0x02 /* Dead Time High Side Buffer Valid bit mask. */ -#define AWEX_DTHSBUFV_bp 1 /* Dead Time High Side Buffer Valid bit position. */ - -#define AWEX_DTLSBUFV_bm 0x01 /* Dead Time Low Side Buffer Valid bit mask. */ -#define AWEX_DTLSBUFV_bp 0 /* Dead Time Low Side Buffer Valid bit position. */ - -/* AWEX.STATUSSET bit masks and bit positions */ -/* AWEX_FDF Predefined. */ -/* AWEX_FDF Predefined. */ - -/* AWEX_DTHSBUFV Predefined. */ -/* AWEX_DTHSBUFV Predefined. */ - -/* AWEX_DTLSBUFV Predefined. */ -/* AWEX_DTLSBUFV Predefined. */ - -/* HIRES - Timer/Counter High-Resolution Extension */ -/* HIRES.CTRLA bit masks and bit positions */ -#define HIRES_HREN_gm 0x03 /* High Resolution Enable group mask. */ -#define HIRES_HREN_gp 0 /* High Resolution Enable group position. */ -#define HIRES_HREN0_bm (1<<0) /* High Resolution Enable bit 0 mask. */ -#define HIRES_HREN0_bp 0 /* High Resolution Enable bit 0 position. */ -#define HIRES_HREN1_bm (1<<1) /* High Resolution Enable bit 1 mask. */ -#define HIRES_HREN1_bp 1 /* High Resolution Enable bit 1 position. */ - -/* USART - Universal Asynchronous Receiver-Transmitter */ -/* USART.STATUS bit masks and bit positions */ -#define USART_RXCIF_bm 0x80 /* Receive Interrupt Flag bit mask. */ -#define USART_RXCIF_bp 7 /* Receive Interrupt Flag bit position. */ - -#define USART_TXCIF_bm 0x40 /* Transmit Interrupt Flag bit mask. */ -#define USART_TXCIF_bp 6 /* Transmit Interrupt Flag bit position. */ - -#define USART_DREIF_bm 0x20 /* Data Register Empty Flag bit mask. */ -#define USART_DREIF_bp 5 /* Data Register Empty Flag bit position. */ - -#define USART_FERR_bm 0x10 /* Frame Error bit mask. */ -#define USART_FERR_bp 4 /* Frame Error bit position. */ - -#define USART_BUFOVF_bm 0x08 /* Buffer Overflow bit mask. */ -#define USART_BUFOVF_bp 3 /* Buffer Overflow bit position. */ - -#define USART_PERR_bm 0x04 /* Parity Error bit mask. */ -#define USART_PERR_bp 2 /* Parity Error bit position. */ - -#define USART_RXB8_bm 0x01 /* Receive Bit 8 bit mask. */ -#define USART_RXB8_bp 0 /* Receive Bit 8 bit position. */ - -/* USART.CTRLA bit masks and bit positions */ -#define USART_RXCINTLVL_gm 0x30 /* Receive Interrupt Level group mask. */ -#define USART_RXCINTLVL_gp 4 /* Receive Interrupt Level group position. */ -#define USART_RXCINTLVL0_bm (1<<4) /* Receive Interrupt Level bit 0 mask. */ -#define USART_RXCINTLVL0_bp 4 /* Receive Interrupt Level bit 0 position. */ -#define USART_RXCINTLVL1_bm (1<<5) /* Receive Interrupt Level bit 1 mask. */ -#define USART_RXCINTLVL1_bp 5 /* Receive Interrupt Level bit 1 position. */ - -#define USART_TXCINTLVL_gm 0x0C /* Transmit Interrupt Level group mask. */ -#define USART_TXCINTLVL_gp 2 /* Transmit Interrupt Level group position. */ -#define USART_TXCINTLVL0_bm (1<<2) /* Transmit Interrupt Level bit 0 mask. */ -#define USART_TXCINTLVL0_bp 2 /* Transmit Interrupt Level bit 0 position. */ -#define USART_TXCINTLVL1_bm (1<<3) /* Transmit Interrupt Level bit 1 mask. */ -#define USART_TXCINTLVL1_bp 3 /* Transmit Interrupt Level bit 1 position. */ - -#define USART_DREINTLVL_gm 0x03 /* Data Register Empty Interrupt Level group mask. */ -#define USART_DREINTLVL_gp 0 /* Data Register Empty Interrupt Level group position. */ -#define USART_DREINTLVL0_bm (1<<0) /* Data Register Empty Interrupt Level bit 0 mask. */ -#define USART_DREINTLVL0_bp 0 /* Data Register Empty Interrupt Level bit 0 position. */ -#define USART_DREINTLVL1_bm (1<<1) /* Data Register Empty Interrupt Level bit 1 mask. */ -#define USART_DREINTLVL1_bp 1 /* Data Register Empty Interrupt Level bit 1 position. */ - -/* USART.CTRLB bit masks and bit positions */ -#define USART_RXEN_bm 0x10 /* Receiver Enable bit mask. */ -#define USART_RXEN_bp 4 /* Receiver Enable bit position. */ - -#define USART_TXEN_bm 0x08 /* Transmitter Enable bit mask. */ -#define USART_TXEN_bp 3 /* Transmitter Enable bit position. */ - -#define USART_CLK2X_bm 0x04 /* Double transmission speed bit mask. */ -#define USART_CLK2X_bp 2 /* Double transmission speed bit position. */ - -#define USART_MPCM_bm 0x02 /* Multi-processor Communication Mode bit mask. */ -#define USART_MPCM_bp 1 /* Multi-processor Communication Mode bit position. */ - -#define USART_TXB8_bm 0x01 /* Transmit bit 8 bit mask. */ -#define USART_TXB8_bp 0 /* Transmit bit 8 bit position. */ - -/* USART.CTRLC bit masks and bit positions */ -#define USART_CMODE_gm 0xC0 /* Communication Mode group mask. */ -#define USART_CMODE_gp 6 /* Communication Mode group position. */ -#define USART_CMODE0_bm (1<<6) /* Communication Mode bit 0 mask. */ -#define USART_CMODE0_bp 6 /* Communication Mode bit 0 position. */ -#define USART_CMODE1_bm (1<<7) /* Communication Mode bit 1 mask. */ -#define USART_CMODE1_bp 7 /* Communication Mode bit 1 position. */ - -#define USART_PMODE_gm 0x30 /* Parity Mode group mask. */ -#define USART_PMODE_gp 4 /* Parity Mode group position. */ -#define USART_PMODE0_bm (1<<4) /* Parity Mode bit 0 mask. */ -#define USART_PMODE0_bp 4 /* Parity Mode bit 0 position. */ -#define USART_PMODE1_bm (1<<5) /* Parity Mode bit 1 mask. */ -#define USART_PMODE1_bp 5 /* Parity Mode bit 1 position. */ - -#define USART_SBMODE_bm 0x08 /* Stop Bit Mode bit mask. */ -#define USART_SBMODE_bp 3 /* Stop Bit Mode bit position. */ - -#define USART_CHSIZE_gm 0x07 /* Character Size group mask. */ -#define USART_CHSIZE_gp 0 /* Character Size group position. */ -#define USART_CHSIZE0_bm (1<<0) /* Character Size bit 0 mask. */ -#define USART_CHSIZE0_bp 0 /* Character Size bit 0 position. */ -#define USART_CHSIZE1_bm (1<<1) /* Character Size bit 1 mask. */ -#define USART_CHSIZE1_bp 1 /* Character Size bit 1 position. */ -#define USART_CHSIZE2_bm (1<<2) /* Character Size bit 2 mask. */ -#define USART_CHSIZE2_bp 2 /* Character Size bit 2 position. */ - -/* USART.BAUDCTRLA bit masks and bit positions */ -#define USART_BSEL_gm 0xFF /* Baud Rate Selection Bits [7:0] group mask. */ -#define USART_BSEL_gp 0 /* Baud Rate Selection Bits [7:0] group position. */ -#define USART_BSEL0_bm (1<<0) /* Baud Rate Selection Bits [7:0] bit 0 mask. */ -#define USART_BSEL0_bp 0 /* Baud Rate Selection Bits [7:0] bit 0 position. */ -#define USART_BSEL1_bm (1<<1) /* Baud Rate Selection Bits [7:0] bit 1 mask. */ -#define USART_BSEL1_bp 1 /* Baud Rate Selection Bits [7:0] bit 1 position. */ -#define USART_BSEL2_bm (1<<2) /* Baud Rate Selection Bits [7:0] bit 2 mask. */ -#define USART_BSEL2_bp 2 /* Baud Rate Selection Bits [7:0] bit 2 position. */ -#define USART_BSEL3_bm (1<<3) /* Baud Rate Selection Bits [7:0] bit 3 mask. */ -#define USART_BSEL3_bp 3 /* Baud Rate Selection Bits [7:0] bit 3 position. */ -#define USART_BSEL4_bm (1<<4) /* Baud Rate Selection Bits [7:0] bit 4 mask. */ -#define USART_BSEL4_bp 4 /* Baud Rate Selection Bits [7:0] bit 4 position. */ -#define USART_BSEL5_bm (1<<5) /* Baud Rate Selection Bits [7:0] bit 5 mask. */ -#define USART_BSEL5_bp 5 /* Baud Rate Selection Bits [7:0] bit 5 position. */ -#define USART_BSEL6_bm (1<<6) /* Baud Rate Selection Bits [7:0] bit 6 mask. */ -#define USART_BSEL6_bp 6 /* Baud Rate Selection Bits [7:0] bit 6 position. */ -#define USART_BSEL7_bm (1<<7) /* Baud Rate Selection Bits [7:0] bit 7 mask. */ -#define USART_BSEL7_bp 7 /* Baud Rate Selection Bits [7:0] bit 7 position. */ - -/* USART.BAUDCTRLB bit masks and bit positions */ -#define USART_BSCALE_gm 0xF0 /* Baud Rate Scale group mask. */ -#define USART_BSCALE_gp 4 /* Baud Rate Scale group position. */ -#define USART_BSCALE0_bm (1<<4) /* Baud Rate Scale bit 0 mask. */ -#define USART_BSCALE0_bp 4 /* Baud Rate Scale bit 0 position. */ -#define USART_BSCALE1_bm (1<<5) /* Baud Rate Scale bit 1 mask. */ -#define USART_BSCALE1_bp 5 /* Baud Rate Scale bit 1 position. */ -#define USART_BSCALE2_bm (1<<6) /* Baud Rate Scale bit 2 mask. */ -#define USART_BSCALE2_bp 6 /* Baud Rate Scale bit 2 position. */ -#define USART_BSCALE3_bm (1<<7) /* Baud Rate Scale bit 3 mask. */ -#define USART_BSCALE3_bp 7 /* Baud Rate Scale bit 3 position. */ - -/* USART_BSEL Predefined. */ -/* USART_BSEL Predefined. */ - -/* SPI - Serial Peripheral Interface */ -/* SPI.CTRL bit masks and bit positions */ -#define SPI_CLK2X_bm 0x80 /* Enable Double Speed bit mask. */ -#define SPI_CLK2X_bp 7 /* Enable Double Speed bit position. */ - -#define SPI_ENABLE_bm 0x40 /* Enable Module bit mask. */ -#define SPI_ENABLE_bp 6 /* Enable Module bit position. */ - -#define SPI_DORD_bm 0x20 /* Data Order Setting bit mask. */ -#define SPI_DORD_bp 5 /* Data Order Setting bit position. */ - -#define SPI_MASTER_bm 0x10 /* Master Operation Enable bit mask. */ -#define SPI_MASTER_bp 4 /* Master Operation Enable bit position. */ - -#define SPI_MODE_gm 0x0C /* SPI Mode group mask. */ -#define SPI_MODE_gp 2 /* SPI Mode group position. */ -#define SPI_MODE0_bm (1<<2) /* SPI Mode bit 0 mask. */ -#define SPI_MODE0_bp 2 /* SPI Mode bit 0 position. */ -#define SPI_MODE1_bm (1<<3) /* SPI Mode bit 1 mask. */ -#define SPI_MODE1_bp 3 /* SPI Mode bit 1 position. */ - -#define SPI_PRESCALER_gm 0x03 /* Prescaler group mask. */ -#define SPI_PRESCALER_gp 0 /* Prescaler group position. */ -#define SPI_PRESCALER0_bm (1<<0) /* Prescaler bit 0 mask. */ -#define SPI_PRESCALER0_bp 0 /* Prescaler bit 0 position. */ -#define SPI_PRESCALER1_bm (1<<1) /* Prescaler bit 1 mask. */ -#define SPI_PRESCALER1_bp 1 /* Prescaler bit 1 position. */ - -/* SPI.INTCTRL bit masks and bit positions */ -#define SPI_INTLVL_gm 0x03 /* Interrupt level group mask. */ -#define SPI_INTLVL_gp 0 /* Interrupt level group position. */ -#define SPI_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */ -#define SPI_INTLVL0_bp 0 /* Interrupt level bit 0 position. */ -#define SPI_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */ -#define SPI_INTLVL1_bp 1 /* Interrupt level bit 1 position. */ - -/* SPI.STATUS bit masks and bit positions */ -#define SPI_IF_bm 0x80 /* Interrupt Flag bit mask. */ -#define SPI_IF_bp 7 /* Interrupt Flag bit position. */ - -#define SPI_WRCOL_bm 0x40 /* Write Collision bit mask. */ -#define SPI_WRCOL_bp 6 /* Write Collision bit position. */ - -/* IRCOM - IR Communication Module */ -/* IRCOM.CTRL bit masks and bit positions */ -#define IRCOM_EVSEL_gm 0x0F /* Event Channel Select group mask. */ -#define IRCOM_EVSEL_gp 0 /* Event Channel Select group position. */ -#define IRCOM_EVSEL0_bm (1<<0) /* Event Channel Select bit 0 mask. */ -#define IRCOM_EVSEL0_bp 0 /* Event Channel Select bit 0 position. */ -#define IRCOM_EVSEL1_bm (1<<1) /* Event Channel Select bit 1 mask. */ -#define IRCOM_EVSEL1_bp 1 /* Event Channel Select bit 1 position. */ -#define IRCOM_EVSEL2_bm (1<<2) /* Event Channel Select bit 2 mask. */ -#define IRCOM_EVSEL2_bp 2 /* Event Channel Select bit 2 position. */ -#define IRCOM_EVSEL3_bm (1<<3) /* Event Channel Select bit 3 mask. */ -#define IRCOM_EVSEL3_bp 3 /* Event Channel Select bit 3 position. */ - -/* LCD - LCD Controller */ -/* LCD.CTRLA bit masks and bit positions */ -#define LCD_ENABLE_bm 0x80 /* LCD Enable bit mask. */ -#define LCD_ENABLE_bp 7 /* LCD Enable bit position. */ - -#define LCD_XBIAS_bm 0x40 /* External Register Bias Generation bit mask. */ -#define LCD_XBIAS_bp 6 /* External Register Bias Generation bit position. */ - -#define LCD_DATCLK_bm 0x20 /* Data Register Lock bit mask. */ -#define LCD_DATCLK_bp 5 /* Data Register Lock bit position. */ - -#define LCD_COMSWP_bm 0x10 /* Common Bus Swap bit mask. */ -#define LCD_COMSWP_bp 4 /* Common Bus Swap bit position. */ - -#define LCD_SEGSWP_bm 0x08 /* Segment Bus Swap bit mask. */ -#define LCD_SEGSWP_bp 3 /* Segment Bus Swap bit position. */ - -#define LCD_CLRDT_bm 0x04 /* Clear Data Register bit mask. */ -#define LCD_CLRDT_bp 2 /* Clear Data Register bit position. */ - -#define LCD_SEGON_bm 0x02 /* Segments On bit mask. */ -#define LCD_SEGON_bp 1 /* Segments On bit position. */ - -#define LCD_BLANK_bm 0x01 /* Blanking Display Mode bit mask. */ -#define LCD_BLANK_bp 0 /* Blanking Display Mode bit position. */ - -/* LCD.CTRLB bit masks and bit positions */ -#define LCD_PRESC_bm 0x80 /* LCD Prescaler Select bit mask. */ -#define LCD_PRESC_bp 7 /* LCD Prescaler Select bit position. */ - -#define LCD_CLKDIV_gm 0x70 /* LCD Clock Divide group mask. */ -#define LCD_CLKDIV_gp 4 /* LCD Clock Divide group position. */ -#define LCD_CLKDIV0_bm (1<<4) /* LCD Clock Divide bit 0 mask. */ -#define LCD_CLKDIV0_bp 4 /* LCD Clock Divide bit 0 position. */ -#define LCD_CLKDIV1_bm (1<<5) /* LCD Clock Divide bit 1 mask. */ -#define LCD_CLKDIV1_bp 5 /* LCD Clock Divide bit 1 position. */ -#define LCD_CLKDIV2_bm (1<<6) /* LCD Clock Divide bit 2 mask. */ -#define LCD_CLKDIV2_bp 6 /* LCD Clock Divide bit 2 position. */ - -#define LCD_LPWAV_bm 0x08 /* Low Power Waveform bit mask. */ -#define LCD_LPWAV_bp 3 /* Low Power Waveform bit position. */ - -#define LCD_DUTY_gm 0x03 /* Duty Select group mask. */ -#define LCD_DUTY_gp 0 /* Duty Select group position. */ -#define LCD_DUTY0_bm (1<<0) /* Duty Select bit 0 mask. */ -#define LCD_DUTY0_bp 0 /* Duty Select bit 0 position. */ -#define LCD_DUTY1_bm (1<<1) /* Duty Select bit 1 mask. */ -#define LCD_DUTY1_bp 1 /* Duty Select bit 1 position. */ - -/* LCD.CTRLC bit masks and bit positions */ -#define LCD_PMSK_gm 0x3F /* LCD Port Mask group mask. */ -#define LCD_PMSK_gp 0 /* LCD Port Mask group position. */ -#define LCD_PMSK0_bm (1<<0) /* LCD Port Mask bit 0 mask. */ -#define LCD_PMSK0_bp 0 /* LCD Port Mask bit 0 position. */ -#define LCD_PMSK1_bm (1<<1) /* LCD Port Mask bit 1 mask. */ -#define LCD_PMSK1_bp 1 /* LCD Port Mask bit 1 position. */ -#define LCD_PMSK2_bm (1<<2) /* LCD Port Mask bit 2 mask. */ -#define LCD_PMSK2_bp 2 /* LCD Port Mask bit 2 position. */ -#define LCD_PMSK3_bm (1<<3) /* LCD Port Mask bit 3 mask. */ -#define LCD_PMSK3_bp 3 /* LCD Port Mask bit 3 position. */ -#define LCD_PMSK4_bm (1<<4) /* LCD Port Mask bit 4 mask. */ -#define LCD_PMSK4_bp 4 /* LCD Port Mask bit 4 position. */ -#define LCD_PMSK5_bm (1<<5) /* LCD Port Mask bit 5 mask. */ -#define LCD_PMSK5_bp 5 /* LCD Port Mask bit 5 position. */ - -/* LCD.INTCTRL bit masks and bit positions */ -#define LCD_XIME_gm 0xF8 /* eXtended Interrupt Mode Enable group mask. */ -#define LCD_XIME_gp 3 /* eXtended Interrupt Mode Enable group position. */ -#define LCD_XIME0_bm (1<<3) /* eXtended Interrupt Mode Enable bit 0 mask. */ -#define LCD_XIME0_bp 3 /* eXtended Interrupt Mode Enable bit 0 position. */ -#define LCD_XIME1_bm (1<<4) /* eXtended Interrupt Mode Enable bit 1 mask. */ -#define LCD_XIME1_bp 4 /* eXtended Interrupt Mode Enable bit 1 position. */ -#define LCD_XIME2_bm (1<<5) /* eXtended Interrupt Mode Enable bit 2 mask. */ -#define LCD_XIME2_bp 5 /* eXtended Interrupt Mode Enable bit 2 position. */ -#define LCD_XIME3_bm (1<<6) /* eXtended Interrupt Mode Enable bit 3 mask. */ -#define LCD_XIME3_bp 6 /* eXtended Interrupt Mode Enable bit 3 position. */ -#define LCD_XIME4_bm (1<<7) /* eXtended Interrupt Mode Enable bit 4 mask. */ -#define LCD_XIME4_bp 7 /* eXtended Interrupt Mode Enable bit 4 position. */ - -#define LCD_FCINTLVL_gm 0x03 /* Interrupt Level group mask. */ -#define LCD_FCINTLVL_gp 0 /* Interrupt Level group position. */ -#define LCD_FCINTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */ -#define LCD_FCINTLVL0_bp 0 /* Interrupt Level bit 0 position. */ -#define LCD_FCINTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ -#define LCD_FCINTLVL1_bp 1 /* Interrupt Level bit 1 position. */ - -/* LCD.INTFLAG bit masks and bit positions */ -#define LCD_FCIF_bm 0x01 /* LCD Frame Completed Interrupt Flag bit mask. */ -#define LCD_FCIF_bp 0 /* LCD Frame Completed Interrupt Flag bit position. */ - -/* LCD.CTRLD bit masks and bit positions */ -#define LCD_BLINKEN_bm 0x08 /* Blink Enable bit mask. */ -#define LCD_BLINKEN_bp 3 /* Blink Enable bit position. */ - -#define LCD_BLINKRATE_gm 0x03 /* LCD Blink Rate group mask. */ -#define LCD_BLINKRATE_gp 0 /* LCD Blink Rate group position. */ -#define LCD_BLINKRATE0_bm (1<<0) /* LCD Blink Rate bit 0 mask. */ -#define LCD_BLINKRATE0_bp 0 /* LCD Blink Rate bit 0 position. */ -#define LCD_BLINKRATE1_bm (1<<1) /* LCD Blink Rate bit 1 mask. */ -#define LCD_BLINKRATE1_bp 1 /* LCD Blink Rate bit 1 position. */ - -/* LCD.CTRLE bit masks and bit positions */ -#define LCD_BPS1_gm 0xF0 /* Blink Pixel Selection 1 group mask. */ -#define LCD_BPS1_gp 4 /* Blink Pixel Selection 1 group position. */ -#define LCD_BPS10_bm (1<<4) /* Blink Pixel Selection 1 bit 0 mask. */ -#define LCD_BPS10_bp 4 /* Blink Pixel Selection 1 bit 0 position. */ -#define LCD_BPS11_bm (1<<5) /* Blink Pixel Selection 1 bit 1 mask. */ -#define LCD_BPS11_bp 5 /* Blink Pixel Selection 1 bit 1 position. */ -#define LCD_BPS12_bm (1<<6) /* Blink Pixel Selection 1 bit 2 mask. */ -#define LCD_BPS12_bp 6 /* Blink Pixel Selection 1 bit 2 position. */ -#define LCD_BPS13_bm (1<<7) /* Blink Pixel Selection 1 bit 3 mask. */ -#define LCD_BPS13_bp 7 /* Blink Pixel Selection 1 bit 3 position. */ - -#define LCD_BPS0_gm 0x0F /* Blink Pixel Selection 0 group mask. */ -#define LCD_BPS0_gp 0 /* Blink Pixel Selection 0 group position. */ -#define LCD_BPS00_bm (1<<0) /* Blink Pixel Selection 0 bit 0 mask. */ -#define LCD_BPS00_bp 0 /* Blink Pixel Selection 0 bit 0 position. */ -#define LCD_BPS01_bm (1<<1) /* Blink Pixel Selection 0 bit 1 mask. */ -#define LCD_BPS01_bp 1 /* Blink Pixel Selection 0 bit 1 position. */ -#define LCD_BPS02_bm (1<<2) /* Blink Pixel Selection 0 bit 2 mask. */ -#define LCD_BPS02_bp 2 /* Blink Pixel Selection 0 bit 2 position. */ -#define LCD_BPS03_bm (1<<3) /* Blink Pixel Selection 0 bit 3 mask. */ -#define LCD_BPS03_bp 3 /* Blink Pixel Selection 0 bit 3 position. */ - -/* LCD.CTRLF bit masks and bit positions */ -#define LCD_FCONT_gm 0x3F /* Fine Contrast group mask. */ -#define LCD_FCONT_gp 0 /* Fine Contrast group position. */ -#define LCD_FCONT0_bm (1<<0) /* Fine Contrast bit 0 mask. */ -#define LCD_FCONT0_bp 0 /* Fine Contrast bit 0 position. */ -#define LCD_FCONT1_bm (1<<1) /* Fine Contrast bit 1 mask. */ -#define LCD_FCONT1_bp 1 /* Fine Contrast bit 1 position. */ -#define LCD_FCONT2_bm (1<<2) /* Fine Contrast bit 2 mask. */ -#define LCD_FCONT2_bp 2 /* Fine Contrast bit 2 position. */ -#define LCD_FCONT3_bm (1<<3) /* Fine Contrast bit 3 mask. */ -#define LCD_FCONT3_bp 3 /* Fine Contrast bit 3 position. */ -#define LCD_FCONT4_bm (1<<4) /* Fine Contrast bit 4 mask. */ -#define LCD_FCONT4_bp 4 /* Fine Contrast bit 4 position. */ -#define LCD_FCONT5_bm (1<<5) /* Fine Contrast bit 5 mask. */ -#define LCD_FCONT5_bp 5 /* Fine Contrast bit 5 position. */ - -/* LCD.CTRLG bit masks and bit positions */ -#define LCD_TDG_gm 0xC0 /* Type of Digit group mask. */ -#define LCD_TDG_gp 6 /* Type of Digit group position. */ -#define LCD_TDG0_bm (1<<6) /* Type of Digit bit 0 mask. */ -#define LCD_TDG0_bp 6 /* Type of Digit bit 0 position. */ -#define LCD_TDG1_bm (1<<7) /* Type of Digit bit 1 mask. */ -#define LCD_TDG1_bp 7 /* Type of Digit bit 1 position. */ - -#define LCD_STSEG_gm 0x3F /* Start Segment group mask. */ -#define LCD_STSEG_gp 0 /* Start Segment group position. */ -#define LCD_STSEG0_bm (1<<0) /* Start Segment bit 0 mask. */ -#define LCD_STSEG0_bp 0 /* Start Segment bit 0 position. */ -#define LCD_STSEG1_bm (1<<1) /* Start Segment bit 1 mask. */ -#define LCD_STSEG1_bp 1 /* Start Segment bit 1 position. */ -#define LCD_STSEG2_bm (1<<2) /* Start Segment bit 2 mask. */ -#define LCD_STSEG2_bp 2 /* Start Segment bit 2 position. */ -#define LCD_STSEG3_bm (1<<3) /* Start Segment bit 3 mask. */ -#define LCD_STSEG3_bp 3 /* Start Segment bit 3 position. */ -#define LCD_STSEG4_bm (1<<4) /* Start Segment bit 4 mask. */ -#define LCD_STSEG4_bp 4 /* Start Segment bit 4 position. */ -#define LCD_STSEG5_bm (1<<5) /* Start Segment bit 5 mask. */ -#define LCD_STSEG5_bp 5 /* Start Segment bit 5 position. */ - -/* LCD.CTRLH bit masks and bit positions */ -#define LCD_DEC_bm 0x80 /* Decrement of Start Segment bit mask. */ -#define LCD_DEC_bp 7 /* Decrement of Start Segment bit position. */ - -#define LCD_DCODE_gm 0x7F /* Display Code group mask. */ -#define LCD_DCODE_gp 0 /* Display Code group position. */ -#define LCD_DCODE0_bm (1<<0) /* Display Code bit 0 mask. */ -#define LCD_DCODE0_bp 0 /* Display Code bit 0 position. */ -#define LCD_DCODE1_bm (1<<1) /* Display Code bit 1 mask. */ -#define LCD_DCODE1_bp 1 /* Display Code bit 1 position. */ -#define LCD_DCODE2_bm (1<<2) /* Display Code bit 2 mask. */ -#define LCD_DCODE2_bp 2 /* Display Code bit 2 position. */ -#define LCD_DCODE3_bm (1<<3) /* Display Code bit 3 mask. */ -#define LCD_DCODE3_bp 3 /* Display Code bit 3 position. */ -#define LCD_DCODE4_bm (1<<4) /* Display Code bit 4 mask. */ -#define LCD_DCODE4_bp 4 /* Display Code bit 4 position. */ -#define LCD_DCODE5_bm (1<<5) /* Display Code bit 5 mask. */ -#define LCD_DCODE5_bp 5 /* Display Code bit 5 position. */ -#define LCD_DCODE6_bm (1<<6) /* Display Code bit 6 mask. */ -#define LCD_DCODE6_bp 6 /* Display Code bit 6 position. */ - -/* FUSE - Fuses and Lockbits */ -/* NVM_FUSES.FUSEBYTE0 bit masks and bit positions */ -#define NVM_FUSES_JTAGUSERID_gm 0xFF /* JTAG User ID group mask. */ -#define NVM_FUSES_JTAGUSERID_gp 0 /* JTAG User ID group position. */ -#define NVM_FUSES_JTAGUSERID0_bm (1<<0) /* JTAG User ID bit 0 mask. */ -#define NVM_FUSES_JTAGUSERID0_bp 0 /* JTAG User ID bit 0 position. */ -#define NVM_FUSES_JTAGUSERID1_bm (1<<1) /* JTAG User ID bit 1 mask. */ -#define NVM_FUSES_JTAGUSERID1_bp 1 /* JTAG User ID bit 1 position. */ -#define NVM_FUSES_JTAGUSERID2_bm (1<<2) /* JTAG User ID bit 2 mask. */ -#define NVM_FUSES_JTAGUSERID2_bp 2 /* JTAG User ID bit 2 position. */ -#define NVM_FUSES_JTAGUSERID3_bm (1<<3) /* JTAG User ID bit 3 mask. */ -#define NVM_FUSES_JTAGUSERID3_bp 3 /* JTAG User ID bit 3 position. */ -#define NVM_FUSES_JTAGUSERID4_bm (1<<4) /* JTAG User ID bit 4 mask. */ -#define NVM_FUSES_JTAGUSERID4_bp 4 /* JTAG User ID bit 4 position. */ -#define NVM_FUSES_JTAGUSERID5_bm (1<<5) /* JTAG User ID bit 5 mask. */ -#define NVM_FUSES_JTAGUSERID5_bp 5 /* JTAG User ID bit 5 position. */ -#define NVM_FUSES_JTAGUSERID6_bm (1<<6) /* JTAG User ID bit 6 mask. */ -#define NVM_FUSES_JTAGUSERID6_bp 6 /* JTAG User ID bit 6 position. */ -#define NVM_FUSES_JTAGUSERID7_bm (1<<7) /* JTAG User ID bit 7 mask. */ -#define NVM_FUSES_JTAGUSERID7_bp 7 /* JTAG User ID bit 7 position. */ - -/* NVM_FUSES.FUSEBYTE1 bit masks and bit positions */ -#define NVM_FUSES_WDWP_gm 0xF0 /* Watchdog Window Timeout Period group mask. */ -#define NVM_FUSES_WDWP_gp 4 /* Watchdog Window Timeout Period group position. */ -#define NVM_FUSES_WDWP0_bm (1<<4) /* Watchdog Window Timeout Period bit 0 mask. */ -#define NVM_FUSES_WDWP0_bp 4 /* Watchdog Window Timeout Period bit 0 position. */ -#define NVM_FUSES_WDWP1_bm (1<<5) /* Watchdog Window Timeout Period bit 1 mask. */ -#define NVM_FUSES_WDWP1_bp 5 /* Watchdog Window Timeout Period bit 1 position. */ -#define NVM_FUSES_WDWP2_bm (1<<6) /* Watchdog Window Timeout Period bit 2 mask. */ -#define NVM_FUSES_WDWP2_bp 6 /* Watchdog Window Timeout Period bit 2 position. */ -#define NVM_FUSES_WDWP3_bm (1<<7) /* Watchdog Window Timeout Period bit 3 mask. */ -#define NVM_FUSES_WDWP3_bp 7 /* Watchdog Window Timeout Period bit 3 position. */ - -#define NVM_FUSES_WDP_gm 0x0F /* Watchdog Timeout Period group mask. */ -#define NVM_FUSES_WDP_gp 0 /* Watchdog Timeout Period group position. */ -#define NVM_FUSES_WDP0_bm (1<<0) /* Watchdog Timeout Period bit 0 mask. */ -#define NVM_FUSES_WDP0_bp 0 /* Watchdog Timeout Period bit 0 position. */ -#define NVM_FUSES_WDP1_bm (1<<1) /* Watchdog Timeout Period bit 1 mask. */ -#define NVM_FUSES_WDP1_bp 1 /* Watchdog Timeout Period bit 1 position. */ -#define NVM_FUSES_WDP2_bm (1<<2) /* Watchdog Timeout Period bit 2 mask. */ -#define NVM_FUSES_WDP2_bp 2 /* Watchdog Timeout Period bit 2 position. */ -#define NVM_FUSES_WDP3_bm (1<<3) /* Watchdog Timeout Period bit 3 mask. */ -#define NVM_FUSES_WDP3_bp 3 /* Watchdog Timeout Period bit 3 position. */ - -/* NVM_FUSES.FUSEBYTE2 bit masks and bit positions */ -#define NVM_FUSES_BOOTRST_bm 0x40 /* Boot Loader Section Reset Vector bit mask. */ -#define NVM_FUSES_BOOTRST_bp 6 /* Boot Loader Section Reset Vector bit position. */ - -#define NVM_FUSES_TOSCSEL_bm 0x20 /* Timer Oscillator pin location bit mask. */ -#define NVM_FUSES_TOSCSEL_bp 5 /* Timer Oscillator pin location bit position. */ - -#define NVM_FUSES_BODPD_gm 0x03 /* BOD Operation in Power-Down Mode group mask. */ -#define NVM_FUSES_BODPD_gp 0 /* BOD Operation in Power-Down Mode group position. */ -#define NVM_FUSES_BODPD0_bm (1<<0) /* BOD Operation in Power-Down Mode bit 0 mask. */ -#define NVM_FUSES_BODPD0_bp 0 /* BOD Operation in Power-Down Mode bit 0 position. */ -#define NVM_FUSES_BODPD1_bm (1<<1) /* BOD Operation in Power-Down Mode bit 1 mask. */ -#define NVM_FUSES_BODPD1_bp 1 /* BOD Operation in Power-Down Mode bit 1 position. */ - -/* NVM_FUSES.FUSEBYTE4 bit masks and bit positions */ -#define NVM_FUSES_RSTDISBL_bm 0x10 /* External Reset Disable bit mask. */ -#define NVM_FUSES_RSTDISBL_bp 4 /* External Reset Disable bit position. */ - -#define NVM_FUSES_SUT_gm 0x0C /* Start-up Time group mask. */ -#define NVM_FUSES_SUT_gp 2 /* Start-up Time group position. */ -#define NVM_FUSES_SUT0_bm (1<<2) /* Start-up Time bit 0 mask. */ -#define NVM_FUSES_SUT0_bp 2 /* Start-up Time bit 0 position. */ -#define NVM_FUSES_SUT1_bm (1<<3) /* Start-up Time bit 1 mask. */ -#define NVM_FUSES_SUT1_bp 3 /* Start-up Time bit 1 position. */ - -#define NVM_FUSES_WDLOCK_bm 0x02 /* Watchdog Timer Lock bit mask. */ -#define NVM_FUSES_WDLOCK_bp 1 /* Watchdog Timer Lock bit position. */ - -#define NVM_FUSES_JTAGEN_bm 0x01 /* JTAG Interface Enable bit mask. */ -#define NVM_FUSES_JTAGEN_bp 0 /* JTAG Interface Enable bit position. */ - -/* NVM_FUSES.FUSEBYTE5 bit masks and bit positions */ -#define NVM_FUSES_BODACT_gm 0x30 /* BOD Operation in Active Mode group mask. */ -#define NVM_FUSES_BODACT_gp 4 /* BOD Operation in Active Mode group position. */ -#define NVM_FUSES_BODACT0_bm (1<<4) /* BOD Operation in Active Mode bit 0 mask. */ -#define NVM_FUSES_BODACT0_bp 4 /* BOD Operation in Active Mode bit 0 position. */ -#define NVM_FUSES_BODACT1_bm (1<<5) /* BOD Operation in Active Mode bit 1 mask. */ -#define NVM_FUSES_BODACT1_bp 5 /* BOD Operation in Active Mode bit 1 position. */ - -#define NVM_FUSES_EESAVE_bm 0x08 /* Preserve EEPROM Through Chip Erase bit mask. */ -#define NVM_FUSES_EESAVE_bp 3 /* Preserve EEPROM Through Chip Erase bit position. */ - -#define NVM_FUSES_BODLVL_gm 0x07 /* Brownout Detection Voltage Level group mask. */ -#define NVM_FUSES_BODLVL_gp 0 /* Brownout Detection Voltage Level group position. */ -#define NVM_FUSES_BODLVL0_bm (1<<0) /* Brownout Detection Voltage Level bit 0 mask. */ -#define NVM_FUSES_BODLVL0_bp 0 /* Brownout Detection Voltage Level bit 0 position. */ -#define NVM_FUSES_BODLVL1_bm (1<<1) /* Brownout Detection Voltage Level bit 1 mask. */ -#define NVM_FUSES_BODLVL1_bp 1 /* Brownout Detection Voltage Level bit 1 position. */ -#define NVM_FUSES_BODLVL2_bm (1<<2) /* Brownout Detection Voltage Level bit 2 mask. */ -#define NVM_FUSES_BODLVL2_bp 2 /* Brownout Detection Voltage Level bit 2 position. */ - -/* LOCKBIT - Fuses and Lockbits */ -/* NVM_LOCKBITS.LOCKBITS bit masks and bit positions */ -#define NVM_LOCKBITS_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ -#define NVM_LOCKBITS_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ -#define NVM_LOCKBITS_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ -#define NVM_LOCKBITS_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ -#define NVM_LOCKBITS_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ -#define NVM_LOCKBITS_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ - -#define NVM_LOCKBITS_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ -#define NVM_LOCKBITS_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ -#define NVM_LOCKBITS_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ -#define NVM_LOCKBITS_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ -#define NVM_LOCKBITS_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ -#define NVM_LOCKBITS_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ - -#define NVM_LOCKBITS_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ -#define NVM_LOCKBITS_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ -#define NVM_LOCKBITS_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ -#define NVM_LOCKBITS_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ -#define NVM_LOCKBITS_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ -#define NVM_LOCKBITS_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ - -#define NVM_LOCKBITS_LB_gm 0x03 /* Lock Bits group mask. */ -#define NVM_LOCKBITS_LB_gp 0 /* Lock Bits group position. */ -#define NVM_LOCKBITS_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ -#define NVM_LOCKBITS_LB0_bp 0 /* Lock Bits bit 0 position. */ -#define NVM_LOCKBITS_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ -#define NVM_LOCKBITS_LB1_bp 1 /* Lock Bits bit 1 position. */ - - - -// Generic Port Pins - -#define PIN0_bm 0x01 -#define PIN0_bp 0 -#define PIN1_bm 0x02 -#define PIN1_bp 1 -#define PIN2_bm 0x04 -#define PIN2_bp 2 -#define PIN3_bm 0x08 -#define PIN3_bp 3 -#define PIN4_bm 0x10 -#define PIN4_bp 4 -#define PIN5_bm 0x20 -#define PIN5_bp 5 -#define PIN6_bm 0x40 -#define PIN6_bp 6 -#define PIN7_bm 0x80 -#define PIN7_bp 7 - -/* ========== Interrupt Vector Definitions ========== */ -/* Vector 0 is the reset vector */ - -/* OSC interrupt vectors */ -#define OSC_OSCF_vect_num 1 -#define OSC_OSCF_vect _VECTOR(1) /* Oscillator Failure Interrupt (NMI) */ - -/* PORTC interrupt vectors */ -#define PORTC_INT0_vect_num 2 -#define PORTC_INT0_vect _VECTOR(2) /* External Interrupt 0 */ -#define PORTC_INT1_vect_num 3 -#define PORTC_INT1_vect _VECTOR(3) /* External Interrupt 1 */ - -/* PORTR interrupt vectors */ -#define PORTR_INT0_vect_num 4 -#define PORTR_INT0_vect _VECTOR(4) /* External Interrupt 0 */ -#define PORTR_INT1_vect_num 5 -#define PORTR_INT1_vect _VECTOR(5) /* External Interrupt 1 */ - -/* DMA interrupt vectors */ -#define DMA_CH0_vect_num 6 -#define DMA_CH0_vect _VECTOR(6) /* Channel 0 Interrupt */ -#define DMA_CH1_vect_num 7 -#define DMA_CH1_vect _VECTOR(7) /* Channel 1 Interrupt */ - -/* RTC interrupt vectors */ -#define RTC_OVF_vect_num 10 -#define RTC_OVF_vect _VECTOR(10) /* Overflow Interrupt */ -#define RTC_COMP_vect_num 11 -#define RTC_COMP_vect _VECTOR(11) /* Compare Interrupt */ - -/* TWIC interrupt vectors */ -#define TWIC_TWIS_vect_num 12 -#define TWIC_TWIS_vect _VECTOR(12) /* TWI Slave Interrupt */ -#define TWIC_TWIM_vect_num 13 -#define TWIC_TWIM_vect _VECTOR(13) /* TWI Master Interrupt */ - -/* TCC0 interrupt vectors */ -#define TCC0_OVF_vect_num 14 -#define TCC0_OVF_vect _VECTOR(14) /* Overflow Interrupt */ -#define TCC0_ERR_vect_num 15 -#define TCC0_ERR_vect _VECTOR(15) /* Error Interrupt */ -#define TCC0_CCA_vect_num 16 -#define TCC0_CCA_vect _VECTOR(16) /* Compare or Capture A Interrupt */ -#define TCC0_CCB_vect_num 17 -#define TCC0_CCB_vect _VECTOR(17) /* Compare or Capture B Interrupt */ -#define TCC0_CCC_vect_num 18 -#define TCC0_CCC_vect _VECTOR(18) /* Compare or Capture C Interrupt */ -#define TCC0_CCD_vect_num 19 -#define TCC0_CCD_vect _VECTOR(19) /* Compare or Capture D Interrupt */ - -/* TCC1 interrupt vectors */ -#define TCC1_OVF_vect_num 20 -#define TCC1_OVF_vect _VECTOR(20) /* Overflow Interrupt */ -#define TCC1_ERR_vect_num 21 -#define TCC1_ERR_vect _VECTOR(21) /* Error Interrupt */ -#define TCC1_CCA_vect_num 22 -#define TCC1_CCA_vect _VECTOR(22) /* Compare or Capture A Interrupt */ -#define TCC1_CCB_vect_num 23 -#define TCC1_CCB_vect _VECTOR(23) /* Compare or Capture B Interrupt */ - -/* SPIC interrupt vectors */ -#define SPIC_INT_vect_num 24 -#define SPIC_INT_vect _VECTOR(24) /* SPI Interrupt */ - -/* USARTC0 interrupt vectors */ -#define USARTC0_RXC_vect_num 25 -#define USARTC0_RXC_vect _VECTOR(25) /* Reception Complete Interrupt */ -#define USARTC0_DRE_vect_num 26 -#define USARTC0_DRE_vect _VECTOR(26) /* Data Register Empty Interrupt */ -#define USARTC0_TXC_vect_num 27 -#define USARTC0_TXC_vect _VECTOR(27) /* Transmission Complete Interrupt */ - -/* USB interrupt vectors */ -#define USB_BUSEVENT_vect_num 31 -#define USB_BUSEVENT_vect _VECTOR(31) /* SOF, suspend, resume, reset bus event interrupts, crc, underflow, overflow and stall error interrupts */ -#define USB_TRNCOMPL_vect_num 32 -#define USB_TRNCOMPL_vect _VECTOR(32) /* Transaction complete interrupt */ - -/* LCD interrupt vectors */ -#define LCD_INT_vect_num 35 -#define LCD_INT_vect _VECTOR(35) /* LCD Interrupt */ - -/* AES interrupt vectors */ -#define AES_INT_vect_num 36 -#define AES_INT_vect _VECTOR(36) /* AES Interrupt */ - -/* NVM interrupt vectors */ -#define NVM_EE_vect_num 37 -#define NVM_EE_vect _VECTOR(37) /* EE Interrupt */ -#define NVM_SPM_vect_num 38 -#define NVM_SPM_vect _VECTOR(38) /* SPM Interrupt */ - -/* PORTB interrupt vectors */ -#define PORTB_INT0_vect_num 39 -#define PORTB_INT0_vect _VECTOR(39) /* External Interrupt 0 */ -#define PORTB_INT1_vect_num 40 -#define PORTB_INT1_vect _VECTOR(40) /* External Interrupt 1 */ - -/* ACB interrupt vectors */ -#define ACB_AC0_vect_num 41 -#define ACB_AC0_vect _VECTOR(41) /* AC0 Interrupt */ -#define ACB_AC1_vect_num 42 -#define ACB_AC1_vect _VECTOR(42) /* AC1 Interrupt */ -#define ACB_ACW_vect_num 43 -#define ACB_ACW_vect _VECTOR(43) /* ACW Window Mode Interrupt */ - -/* ADCB interrupt vectors */ -#define ADCB_CH0_vect_num 44 -#define ADCB_CH0_vect _VECTOR(44) /* Interrupt 0 */ - -/* PORTD interrupt vectors */ -#define PORTD_INT0_vect_num 48 -#define PORTD_INT0_vect _VECTOR(48) /* External Interrupt 0 */ -#define PORTD_INT1_vect_num 49 -#define PORTD_INT1_vect _VECTOR(49) /* External Interrupt 1 */ - -/* PORTG interrupt vectors */ -#define PORTG_INT0_vect_num 50 -#define PORTG_INT0_vect _VECTOR(50) /* External Interrupt 0 */ -#define PORTG_INT1_vect_num 51 -#define PORTG_INT1_vect _VECTOR(51) /* External Interrupt 1 */ - -/* PORTM interrupt vectors */ -#define PORTM_INT0_vect_num 52 -#define PORTM_INT0_vect _VECTOR(52) /* External Interrupt 0 */ -#define PORTM_INT1_vect_num 53 -#define PORTM_INT1_vect _VECTOR(53) /* External Interrupt 1 */ - -#define _VECTOR_SIZE 4 /* Size of individual vector. */ -#define _VECTORS_SIZE (54 * _VECTOR_SIZE) - - -/* ========== Constants ========== */ - -#define PROGMEM_START (0x0000) -#define PROGMEM_SIZE (139264) -#define PROGMEM_END (PROGMEM_START + PROGMEM_SIZE - 1) - -#define APP_SECTION_START (0x0000) -#define APP_SECTION_SIZE (131072) -#define APP_SECTION_PAGE_SIZE (256) -#define APP_SECTION_END (APP_SECTION_START + APP_SECTION_SIZE - 1) - -#define APPTABLE_SECTION_START (0x1E000) -#define APPTABLE_SECTION_SIZE (8192) -#define APPTABLE_SECTION_PAGE_SIZE (256) -#define APPTABLE_SECTION_END (APPTABLE_SECTION_START + APPTABLE_SECTION_SIZE - 1) - -#define BOOT_SECTION_START (0x20000) -#define BOOT_SECTION_SIZE (8192) -#define BOOT_SECTION_PAGE_SIZE (256) -#define BOOT_SECTION_END (BOOT_SECTION_START + BOOT_SECTION_SIZE - 1) - -#define DATAMEM_START (0x0000) -#define DATAMEM_SIZE (16384) -#define DATAMEM_END (DATAMEM_START + DATAMEM_SIZE - 1) - -#define IO_START (0x0000) -#define IO_SIZE (4096) -#define IO_PAGE_SIZE (0) -#define IO_END (IO_START + IO_SIZE - 1) - -#define MAPPED_EEPROM_START (0x1000) -#define MAPPED_EEPROM_SIZE (2048) -#define MAPPED_EEPROM_PAGE_SIZE (0) -#define MAPPED_EEPROM_END (MAPPED_EEPROM_START + MAPPED_EEPROM_SIZE - 1) - -#define INTERNAL_SRAM_START (0x2000) -#define INTERNAL_SRAM_SIZE (8192) -#define INTERNAL_SRAM_PAGE_SIZE (0) -#define INTERNAL_SRAM_END (INTERNAL_SRAM_START + INTERNAL_SRAM_SIZE - 1) - -#define EEPROM_START (0x0000) -#define EEPROM_SIZE (2048) -#define EEPROM_PAGE_SIZE (32) -#define EEPROM_END (EEPROM_START + EEPROM_SIZE - 1) - -#define SIGNATURES_START (0x0000) -#define SIGNATURES_SIZE (3) -#define SIGNATURES_PAGE_SIZE (0) -#define SIGNATURES_END (SIGNATURES_START + SIGNATURES_SIZE - 1) - -#define FUSES_START (0x0000) -#define FUSES_SIZE (6) -#define FUSES_PAGE_SIZE (0) -#define FUSES_END (FUSES_START + FUSES_SIZE - 1) - -#define LOCKBITS_START (0x0000) -#define LOCKBITS_SIZE (1) -#define LOCKBITS_PAGE_SIZE (0) -#define LOCKBITS_END (LOCKBITS_START + LOCKBITS_SIZE - 1) - -#define USER_SIGNATURES_START (0x0000) -#define USER_SIGNATURES_SIZE (256) -#define USER_SIGNATURES_PAGE_SIZE (256) -#define USER_SIGNATURES_END (USER_SIGNATURES_START + USER_SIGNATURES_SIZE - 1) - -#define PROD_SIGNATURES_START (0x0000) -#define PROD_SIGNATURES_SIZE (52) -#define PROD_SIGNATURES_PAGE_SIZE (256) -#define PROD_SIGNATURES_END (PROD_SIGNATURES_START + PROD_SIGNATURES_SIZE - 1) - -#define FLASHSTART PROGMEM_START -#define FLASHEND PROGMEM_END -#define SPM_PAGESIZE 256 -#define RAMSTART INTERNAL_SRAM_START -#define RAMSIZE INTERNAL_SRAM_SIZE -#define RAMEND INTERNAL_SRAM_END -#define E2END EEPROM_END -#define E2PAGESIZE EEPROM_PAGE_SIZE - - -/* ========== Fuses ========== */ -#define FUSE_MEMORY_SIZE 6 - -/* Fuse Byte 0 */ -#define FUSE_JTAGUSERID0 (unsigned char)~_BV(0) /* JTAG User ID Bit 0 */ -#define FUSE_JTAGUSERID1 (unsigned char)~_BV(1) /* JTAG User ID Bit 1 */ -#define FUSE_JTAGUSERID2 (unsigned char)~_BV(2) /* JTAG User ID Bit 2 */ -#define FUSE_JTAGUSERID3 (unsigned char)~_BV(3) /* JTAG User ID Bit 3 */ -#define FUSE_JTAGUSERID4 (unsigned char)~_BV(4) /* JTAG User ID Bit 4 */ -#define FUSE_JTAGUSERID5 (unsigned char)~_BV(5) /* JTAG User ID Bit 5 */ -#define FUSE_JTAGUSERID6 (unsigned char)~_BV(6) /* JTAG User ID Bit 6 */ -#define FUSE_JTAGUSERID7 (unsigned char)~_BV(7) /* JTAG User ID Bit 7 */ -#define FUSE0_DEFAULT (0xFF) - -/* Fuse Byte 1 */ -#define FUSE_WDP0 (unsigned char)~_BV(0) /* Watchdog Timeout Period Bit 0 */ -#define FUSE_WDP1 (unsigned char)~_BV(1) /* Watchdog Timeout Period Bit 1 */ -#define FUSE_WDP2 (unsigned char)~_BV(2) /* Watchdog Timeout Period Bit 2 */ -#define FUSE_WDP3 (unsigned char)~_BV(3) /* Watchdog Timeout Period Bit 3 */ -#define FUSE_WDWP0 (unsigned char)~_BV(4) /* Watchdog Window Timeout Period Bit 0 */ -#define FUSE_WDWP1 (unsigned char)~_BV(5) /* Watchdog Window Timeout Period Bit 1 */ -#define FUSE_WDWP2 (unsigned char)~_BV(6) /* Watchdog Window Timeout Period Bit 2 */ -#define FUSE_WDWP3 (unsigned char)~_BV(7) /* Watchdog Window Timeout Period Bit 3 */ -#define FUSE1_DEFAULT (0xFF) - -/* Fuse Byte 2 */ -#define FUSE_BODPD0 (unsigned char)~_BV(0) /* BOD Operation in Power-Down Mode Bit 0 */ -#define FUSE_BODPD1 (unsigned char)~_BV(1) /* BOD Operation in Power-Down Mode Bit 1 */ -#define FUSE_TOSCSEL (unsigned char)~_BV(5) /* Timer Oscillator pin location */ -#define FUSE_BOOTRST (unsigned char)~_BV(6) /* Boot Loader Section Reset Vector */ -#define FUSE2_DEFAULT (0xFF) - -/* Fuse Byte 3 Reserved */ - -/* Fuse Byte 4 */ -#define FUSE_JTAGEN (unsigned char)~_BV(0) /* JTAG Interface Enable */ -#define FUSE_WDLOCK (unsigned char)~_BV(1) /* Watchdog Timer Lock */ -#define FUSE_SUT0 (unsigned char)~_BV(2) /* Start-up Time Bit 0 */ -#define FUSE_SUT1 (unsigned char)~_BV(3) /* Start-up Time Bit 1 */ -#define FUSE_RSTDISBL (unsigned char)~_BV(4) /* External Reset Disable */ -#define FUSE4_DEFAULT (0xFF) - -/* Fuse Byte 5 */ -#define FUSE_BODLVL0 (unsigned char)~_BV(0) /* Brownout Detection Voltage Level Bit 0 */ -#define FUSE_BODLVL1 (unsigned char)~_BV(1) /* Brownout Detection Voltage Level Bit 1 */ -#define FUSE_BODLVL2 (unsigned char)~_BV(2) /* Brownout Detection Voltage Level Bit 2 */ -#define FUSE_EESAVE (unsigned char)~_BV(3) /* Preserve EEPROM Through Chip Erase */ -#define FUSE_BODACT0 (unsigned char)~_BV(4) /* BOD Operation in Active Mode Bit 0 */ -#define FUSE_BODACT1 (unsigned char)~_BV(5) /* BOD Operation in Active Mode Bit 1 */ -#define FUSE5_DEFAULT (0xFF) - -/* ========== Lock Bits ========== */ -#define __LOCK_BITS_EXIST -#define __BOOT_LOCK_APPLICATION_TABLE_BITS_EXIST -#define __BOOT_LOCK_APPLICATION_BITS_EXIST -#define __BOOT_LOCK_BOOT_BITS_EXIST - -/* ========== Signature ========== */ -#define SIGNATURE_0 0x1E -#define SIGNATURE_1 0x97 -#define SIGNATURE_2 0x4B - -/* ========== Power Reduction Condition Definitions ========== */ - -/* PR.PRGEN */ -#define __AVR_HAVE_PRGEN (PR_LCD_bm|PR_USB_bm|PR_AES_bm|PR_RTC_bm|PR_EVSYS_bm|PR_DMA_bm) -#define __AVR_HAVE_PRGEN_LCD -#define __AVR_HAVE_PRGEN_USB -#define __AVR_HAVE_PRGEN_AES -#define __AVR_HAVE_PRGEN_RTC -#define __AVR_HAVE_PRGEN_EVSYS -#define __AVR_HAVE_PRGEN_DMA - -/* PR.PRPA */ -#define __AVR_HAVE_PRPA (PR_ADC_bm|PR_AC_bm) -#define __AVR_HAVE_PRPA_ADC -#define __AVR_HAVE_PRPA_AC - -/* PR.PRPB */ -#define __AVR_HAVE_PRPB (PR_ADC_bm|PR_AC_bm) -#define __AVR_HAVE_PRPB_ADC -#define __AVR_HAVE_PRPB_AC - -/* PR.PRPC */ -#define __AVR_HAVE_PRPC (PR_TWI_bm|PR_USART0_bm|PR_SPI_bm|PR_HIRES_bm|PR_TC1_bm|PR_TC0_bm) -#define __AVR_HAVE_PRPC_TWI -#define __AVR_HAVE_PRPC_USART0 -#define __AVR_HAVE_PRPC_SPI -#define __AVR_HAVE_PRPC_HIRES -#define __AVR_HAVE_PRPC_TC1 -#define __AVR_HAVE_PRPC_TC0 - -/* PR.PRPE */ -#define __AVR_HAVE_PRPE (PR_USART0_bm|PR_TC0_bm) -#define __AVR_HAVE_PRPE_USART0 -#define __AVR_HAVE_PRPE_TC0 - - -#endif /* #ifdef _AVR_ATXMEGA128B3_H_INCLUDED */ - diff --git a/arduino/hardware/tools/avr/avr/include/avr/iox128c3.h b/arduino/hardware/tools/avr/avr/include/avr/iox128c3.h deleted file mode 100644 index 6bc51ef..0000000 --- a/arduino/hardware/tools/avr/avr/include/avr/iox128c3.h +++ /dev/null @@ -1,6264 +0,0 @@ -/***************************************************************************** - * - * Copyright (C) 2015 Atmel Corporation - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * - * * Neither the name of the copyright holders nor the names of - * contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - ****************************************************************************/ - - -#ifndef _AVR_IO_H_ -# error "Include instead of this file." -#endif - -#ifndef _AVR_IOXXX_H_ -# define _AVR_IOXXX_H_ "iox128c3.h" -#else -# error "Attempt to include more than one file." -#endif - -#ifndef _AVR_ATXMEGA128C3_H_INCLUDED -#define _AVR_ATXMEGA128C3_H_INCLUDED - -/* Ungrouped common registers */ -#define GPIOR0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ -#define GPIOR1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ -#define GPIOR2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ -#define GPIOR3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ - -/* Deprecated */ -#define GPIO0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ -#define GPIO1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ -#define GPIO2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ -#define GPIO3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ - -#define CCP _SFR_MEM8(0x0034) /* Configuration Change Protection */ -#define RAMPD _SFR_MEM8(0x0038) /* Ramp D */ -#define RAMPX _SFR_MEM8(0x0039) /* Ramp X */ -#define RAMPY _SFR_MEM8(0x003A) /* Ramp Y */ -#define RAMPZ _SFR_MEM8(0x003B) /* Ramp Z */ -#define EIND _SFR_MEM8(0x003C) /* Extended Indirect Jump */ -#define SPL _SFR_MEM8(0x003D) /* Stack Pointer Low */ -#define SPH _SFR_MEM8(0x003E) /* Stack Pointer High */ -#define SREG _SFR_MEM8(0x003F) /* Status Register */ - -/* C Language Only */ -#if !defined (__ASSEMBLER__) - -#include - -typedef volatile uint8_t register8_t; -typedef volatile uint16_t register16_t; -typedef volatile uint32_t register32_t; - - -#ifdef _WORDREGISTER -#undef _WORDREGISTER -#endif -#define _WORDREGISTER(regname) \ - __extension__ union \ - { \ - register16_t regname; \ - struct \ - { \ - register8_t regname ## L; \ - register8_t regname ## H; \ - }; \ - } - -#ifdef _DWORDREGISTER -#undef _DWORDREGISTER -#endif -#define _DWORDREGISTER(regname) \ - __extension__ union \ - { \ - register32_t regname; \ - struct \ - { \ - register8_t regname ## 0; \ - register8_t regname ## 1; \ - register8_t regname ## 2; \ - register8_t regname ## 3; \ - }; \ - } - - -/* -========================================================================== -IO Module Structures -========================================================================== -*/ - - -/* --------------------------------------------------------------------------- -VPORT - Virtual Ports --------------------------------------------------------------------------- -*/ - -/* Virtual Port */ -typedef struct VPORT_struct -{ - register8_t DIR; /* I/O Port Data Direction */ - register8_t OUT; /* I/O Port Output */ - register8_t IN; /* I/O Port Input */ - register8_t INTFLAGS; /* Interrupt Flag Register */ -} VPORT_t; - - -/* --------------------------------------------------------------------------- -XOCD - On-Chip Debug System --------------------------------------------------------------------------- -*/ - -/* On-Chip Debug System */ -typedef struct OCD_struct -{ - register8_t OCDR0; /* OCD Register 0 */ - register8_t OCDR1; /* OCD Register 1 */ -} OCD_t; - - -/* --------------------------------------------------------------------------- -CPU - CPU --------------------------------------------------------------------------- -*/ - -/* CCP signatures */ -typedef enum CCP_enum -{ - CCP_SPM_gc = (0x9D<<0), /* SPM Instruction Protection */ - CCP_IOREG_gc = (0xD8<<0), /* IO Register Protection */ -} CCP_t; - - -/* --------------------------------------------------------------------------- -CLK - Clock System --------------------------------------------------------------------------- -*/ - -/* Clock System */ -typedef struct CLK_struct -{ - register8_t CTRL; /* Control Register */ - register8_t PSCTRL; /* Prescaler Control Register */ - register8_t LOCK; /* Lock register */ - register8_t RTCCTRL; /* RTC Control Register */ - register8_t USBCTRL; /* USB Control Register */ -} CLK_t; - - -/* Power Reduction */ -typedef struct PR_struct -{ - register8_t PRGEN; /* General Power Reduction */ - register8_t PRPA; /* Power Reduction Port A */ - register8_t reserved_0x02; - register8_t PRPC; /* Power Reduction Port C */ - register8_t PRPD; /* Power Reduction Port D */ - register8_t PRPE; /* Power Reduction Port E */ - register8_t PRPF; /* Power Reduction Port F */ -} PR_t; - -/* System Clock Selection */ -typedef enum CLK_SCLKSEL_enum -{ - CLK_SCLKSEL_RC2M_gc = (0x00<<0), /* Internal 2 MHz RC Oscillator */ - CLK_SCLKSEL_RC32M_gc = (0x01<<0), /* Internal 32 MHz RC Oscillator */ - CLK_SCLKSEL_RC32K_gc = (0x02<<0), /* Internal 32.768 kHz RC Oscillator */ - CLK_SCLKSEL_XOSC_gc = (0x03<<0), /* External Crystal Oscillator or Clock */ - CLK_SCLKSEL_PLL_gc = (0x04<<0), /* Phase Locked Loop */ -} CLK_SCLKSEL_t; - -/* Prescaler A Division Factor */ -typedef enum CLK_PSADIV_enum -{ - CLK_PSADIV_1_gc = (0x00<<2), /* Divide by 1 */ - CLK_PSADIV_2_gc = (0x01<<2), /* Divide by 2 */ - CLK_PSADIV_4_gc = (0x03<<2), /* Divide by 4 */ - CLK_PSADIV_8_gc = (0x05<<2), /* Divide by 8 */ - CLK_PSADIV_16_gc = (0x07<<2), /* Divide by 16 */ - CLK_PSADIV_32_gc = (0x09<<2), /* Divide by 32 */ - CLK_PSADIV_64_gc = (0x0B<<2), /* Divide by 64 */ - CLK_PSADIV_128_gc = (0x0D<<2), /* Divide by 128 */ - CLK_PSADIV_256_gc = (0x0F<<2), /* Divide by 256 */ - CLK_PSADIV_512_gc = (0x11<<2), /* Divide by 512 */ -} CLK_PSADIV_t; - -/* Prescaler B and C Division Factor */ -typedef enum CLK_PSBCDIV_enum -{ - CLK_PSBCDIV_1_1_gc = (0x00<<0), /* Divide B by 1 and C by 1 */ - CLK_PSBCDIV_1_2_gc = (0x01<<0), /* Divide B by 1 and C by 2 */ - CLK_PSBCDIV_4_1_gc = (0x02<<0), /* Divide B by 4 and C by 1 */ - CLK_PSBCDIV_2_2_gc = (0x03<<0), /* Divide B by 2 and C by 2 */ -} CLK_PSBCDIV_t; - -/* RTC Clock Source */ -typedef enum CLK_RTCSRC_enum -{ - CLK_RTCSRC_ULP_gc = (0x00<<1), /* 1.024 kHz from internal 32kHz ULP */ - CLK_RTCSRC_TOSC_gc = (0x01<<1), /* 1.024 kHz from 32.768 kHz crystal oscillator on TOSC */ - CLK_RTCSRC_RCOSC_gc = (0x02<<1), /* 1.024 kHz from internal 32.768 kHz RC oscillator */ - CLK_RTCSRC_TOSC32_gc = (0x05<<1), /* 32.768 kHz from 32.768 kHz crystal oscillator on TOSC */ - CLK_RTCSRC_RCOSC32_gc = (0x06<<1), /* 32.768 kHz from internal 32.768 kHz RC oscillator */ - CLK_RTCSRC_EXTCLK_gc = (0x07<<1), /* External Clock from TOSC1 */ -} CLK_RTCSRC_t; - -/* USB Prescaler Division Factor */ -typedef enum CLK_USBPSDIV_enum -{ - CLK_USBPSDIV_1_gc = (0x00<<3), /* Divide by 1 */ - CLK_USBPSDIV_2_gc = (0x01<<3), /* Divide by 2 */ - CLK_USBPSDIV_4_gc = (0x02<<3), /* Divide by 4 */ - CLK_USBPSDIV_8_gc = (0x03<<3), /* Divide by 8 */ - CLK_USBPSDIV_16_gc = (0x04<<3), /* Divide by 16 */ - CLK_USBPSDIV_32_gc = (0x05<<3), /* Divide by 32 */ -} CLK_USBPSDIV_t; - -/* USB Clock Source */ -typedef enum CLK_USBSRC_enum -{ - CLK_USBSRC_PLL_gc = (0x00<<1), /* PLL */ - CLK_USBSRC_RC32M_gc = (0x01<<1), /* Internal 32 MHz RC Oscillator */ -} CLK_USBSRC_t; - - -/* --------------------------------------------------------------------------- -SLEEP - Sleep Controller --------------------------------------------------------------------------- -*/ - -/* Sleep Controller */ -typedef struct SLEEP_struct -{ - register8_t CTRL; /* Control Register */ -} SLEEP_t; - -/* Sleep Mode */ -typedef enum SLEEP_SMODE_enum -{ - SLEEP_SMODE_IDLE_gc = (0x00<<1), /* Idle mode */ - SLEEP_SMODE_PDOWN_gc = (0x02<<1), /* Power-down Mode */ - SLEEP_SMODE_PSAVE_gc = (0x03<<1), /* Power-save Mode */ - SLEEP_SMODE_STDBY_gc = (0x06<<1), /* Standby Mode */ - SLEEP_SMODE_ESTDBY_gc = (0x07<<1), /* Extended Standby Mode */ -} SLEEP_SMODE_t; - - - -#define SLEEP_MODE_IDLE (0x00<<1) -#define SLEEP_MODE_PWR_DOWN (0x02<<1) -#define SLEEP_MODE_PWR_SAVE (0x03<<1) -#define SLEEP_MODE_STANDBY (0x06<<1) -#define SLEEP_MODE_EXT_STANDBY (0x07<<1) -/* --------------------------------------------------------------------------- -OSC - Oscillator --------------------------------------------------------------------------- -*/ - -/* Oscillator */ -typedef struct OSC_struct -{ - register8_t CTRL; /* Control Register */ - register8_t STATUS; /* Status Register */ - register8_t XOSCCTRL; /* External Oscillator Control Register */ - register8_t XOSCFAIL; /* Oscillator Failure Detection Register */ - register8_t RC32KCAL; /* 32.768 kHz Internal Oscillator Calibration Register */ - register8_t PLLCTRL; /* PLL Control Register */ - register8_t DFLLCTRL; /* DFLL Control Register */ -} OSC_t; - -/* Oscillator Frequency Range */ -typedef enum OSC_FRQRANGE_enum -{ - OSC_FRQRANGE_04TO2_gc = (0x00<<6), /* 0.4 - 2 MHz */ - OSC_FRQRANGE_2TO9_gc = (0x01<<6), /* 2 - 9 MHz */ - OSC_FRQRANGE_9TO12_gc = (0x02<<6), /* 9 - 12 MHz */ - OSC_FRQRANGE_12TO16_gc = (0x03<<6), /* 12 - 16 MHz */ -} OSC_FRQRANGE_t; - -/* External Oscillator Selection and Startup Time */ -typedef enum OSC_XOSCSEL_enum -{ - OSC_XOSCSEL_EXTCLK_gc = (0x00<<0), /* External Clock - 6 CLK */ - OSC_XOSCSEL_32KHz_gc = (0x02<<0), /* 32.768 kHz TOSC - 32K CLK */ - OSC_XOSCSEL_XTAL_256CLK_gc = (0x03<<0), /* 0.4-16 MHz XTAL - 256 CLK */ - OSC_XOSCSEL_XTAL_1KCLK_gc = (0x07<<0), /* 0.4-16 MHz XTAL - 1K CLK */ - OSC_XOSCSEL_XTAL_16KCLK_gc = (0x0B<<0), /* 0.4-16 MHz XTAL - 16K CLK */ -} OSC_XOSCSEL_t; - -/* PLL Clock Source */ -typedef enum OSC_PLLSRC_enum -{ - OSC_PLLSRC_RC2M_gc = (0x00<<6), /* Internal 2 MHz RC Oscillator */ - OSC_PLLSRC_RC32M_gc = (0x02<<6), /* Internal 32 MHz RC Oscillator */ - OSC_PLLSRC_XOSC_gc = (0x03<<6), /* External Oscillator */ -} OSC_PLLSRC_t; - -/* 2 MHz DFLL Calibration Reference */ -typedef enum OSC_RC2MCREF_enum -{ - OSC_RC2MCREF_RC32K_gc = (0x00<<0), /* Internal 32.768 kHz RC Oscillator */ - OSC_RC2MCREF_XOSC32K_gc = (0x01<<0), /* External 32.768 kHz Crystal Oscillator */ -} OSC_RC2MCREF_t; - -/* 32 MHz DFLL Calibration Reference */ -typedef enum OSC_RC32MCREF_enum -{ - OSC_RC32MCREF_RC32K_gc = (0x00<<1), /* Internal 32.768 kHz RC Oscillator */ - OSC_RC32MCREF_XOSC32K_gc = (0x01<<1), /* External 32.768 kHz Crystal Oscillator */ - OSC_RC32MCREF_USBSOF_gc = (0x02<<1), /* USB Start of Frame */ -} OSC_RC32MCREF_t; - - -/* --------------------------------------------------------------------------- -DFLL - DFLL --------------------------------------------------------------------------- -*/ - -/* DFLL */ -typedef struct DFLL_struct -{ - register8_t CTRL; /* Control Register */ - register8_t reserved_0x01; - register8_t CALA; /* Calibration Register A */ - register8_t CALB; /* Calibration Register B */ - register8_t COMP0; /* Oscillator Compare Register 0 */ - register8_t COMP1; /* Oscillator Compare Register 1 */ - register8_t COMP2; /* Oscillator Compare Register 2 */ - register8_t reserved_0x07; -} DFLL_t; - - -/* --------------------------------------------------------------------------- -RST - Reset --------------------------------------------------------------------------- -*/ - -/* Reset */ -typedef struct RST_struct -{ - register8_t STATUS; /* Status Register */ - register8_t CTRL; /* Control Register */ -} RST_t; - - -/* --------------------------------------------------------------------------- -WDT - Watch-Dog Timer --------------------------------------------------------------------------- -*/ - -/* Watch-Dog Timer */ -typedef struct WDT_struct -{ - register8_t CTRL; /* Control */ - register8_t WINCTRL; /* Windowed Mode Control */ - register8_t STATUS; /* Status */ -} WDT_t; - -/* Period setting */ -typedef enum WDT_PER_enum -{ - WDT_PER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ - WDT_PER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ - WDT_PER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ - WDT_PER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ - WDT_PER_128CLK_gc = (0x04<<2), /* 128 cycles (0.128s @ 3.3V) */ - WDT_PER_256CLK_gc = (0x05<<2), /* 256 cycles (0.256s @ 3.3V) */ - WDT_PER_512CLK_gc = (0x06<<2), /* 512 cycles (0.512s @ 3.3V) */ - WDT_PER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ - WDT_PER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ - WDT_PER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ - WDT_PER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ -} WDT_PER_t; - -/* Closed window period */ -typedef enum WDT_WPER_enum -{ - WDT_WPER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ - WDT_WPER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ - WDT_WPER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ - WDT_WPER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ - WDT_WPER_128CLK_gc = (0x04<<2), /* 128 cycles (0.128s @ 3.3V) */ - WDT_WPER_256CLK_gc = (0x05<<2), /* 256 cycles (0.256s @ 3.3V) */ - WDT_WPER_512CLK_gc = (0x06<<2), /* 512 cycles (0.512s @ 3.3V) */ - WDT_WPER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ - WDT_WPER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ - WDT_WPER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ - WDT_WPER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ -} WDT_WPER_t; - - -/* --------------------------------------------------------------------------- -MCU - MCU Control --------------------------------------------------------------------------- -*/ - -/* MCU Control */ -typedef struct MCU_struct -{ - register8_t DEVID0; /* Device ID byte 0 */ - register8_t DEVID1; /* Device ID byte 1 */ - register8_t DEVID2; /* Device ID byte 2 */ - register8_t REVID; /* Revision ID */ - register8_t reserved_0x04; - register8_t reserved_0x05; - register8_t reserved_0x06; - register8_t ANAINIT; /* Analog Startup Delay */ - register8_t EVSYSLOCK; /* Event System Lock */ - register8_t AWEXLOCK; /* AWEX Lock */ - register8_t reserved_0x0A; - register8_t reserved_0x0B; -} MCU_t; - - -/* --------------------------------------------------------------------------- -PMIC - Programmable Multi-level Interrupt Controller --------------------------------------------------------------------------- -*/ - -/* Programmable Multi-level Interrupt Controller */ -typedef struct PMIC_struct -{ - register8_t STATUS; /* Status Register */ - register8_t INTPRI; /* Interrupt Priority */ - register8_t CTRL; /* Control Register */ - register8_t reserved_0x03; - register8_t reserved_0x04; - register8_t reserved_0x05; - register8_t reserved_0x06; - register8_t reserved_0x07; - register8_t reserved_0x08; - register8_t reserved_0x09; - register8_t reserved_0x0A; - register8_t reserved_0x0B; - register8_t reserved_0x0C; - register8_t reserved_0x0D; - register8_t reserved_0x0E; - register8_t reserved_0x0F; -} PMIC_t; - - -/* --------------------------------------------------------------------------- -PORTCFG - Port Configuration --------------------------------------------------------------------------- -*/ - -/* I/O port Configuration */ -typedef struct PORTCFG_struct -{ - register8_t MPCMASK; /* Multi-pin Configuration Mask */ - register8_t reserved_0x01; - register8_t VPCTRLA; /* Virtual Port Control Register A */ - register8_t VPCTRLB; /* Virtual Port Control Register B */ - register8_t CLKEVOUT; /* Clock and Event Out Register */ - register8_t reserved_0x05; - register8_t EVOUTSEL; /* Event Output Select */ -} PORTCFG_t; - -/* Virtual Port Mapping */ -typedef enum PORTCFG_VP02MAP_enum -{ - PORTCFG_VP02MAP_PORTA_gc = (0x00<<0), /* Mapped To PORTA */ - PORTCFG_VP02MAP_PORTB_gc = (0x01<<0), /* Mapped To PORTB */ - PORTCFG_VP02MAP_PORTC_gc = (0x02<<0), /* Mapped To PORTC */ - PORTCFG_VP02MAP_PORTD_gc = (0x03<<0), /* Mapped To PORTD */ - PORTCFG_VP02MAP_PORTE_gc = (0x04<<0), /* Mapped To PORTE */ - PORTCFG_VP02MAP_PORTF_gc = (0x05<<0), /* Mapped To PORTF */ - PORTCFG_VP02MAP_PORTG_gc = (0x06<<0), /* Mapped To PORTG */ - PORTCFG_VP02MAP_PORTH_gc = (0x07<<0), /* Mapped To PORTH */ - PORTCFG_VP02MAP_PORTJ_gc = (0x08<<0), /* Mapped To PORTJ */ - PORTCFG_VP02MAP_PORTK_gc = (0x09<<0), /* Mapped To PORTK */ - PORTCFG_VP02MAP_PORTL_gc = (0x0A<<0), /* Mapped To PORTL */ - PORTCFG_VP02MAP_PORTM_gc = (0x0B<<0), /* Mapped To PORTM */ - PORTCFG_VP02MAP_PORTN_gc = (0x0C<<0), /* Mapped To PORTN */ - PORTCFG_VP02MAP_PORTP_gc = (0x0D<<0), /* Mapped To PORTP */ - PORTCFG_VP02MAP_PORTQ_gc = (0x0E<<0), /* Mapped To PORTQ */ - PORTCFG_VP02MAP_PORTR_gc = (0x0F<<0), /* Mapped To PORTR */ -} PORTCFG_VP02MAP_t; - -/* Virtual Port Mapping */ -typedef enum PORTCFG_VP13MAP_enum -{ - PORTCFG_VP13MAP_PORTA_gc = (0x00<<4), /* Mapped To PORTA */ - PORTCFG_VP13MAP_PORTB_gc = (0x01<<4), /* Mapped To PORTB */ - PORTCFG_VP13MAP_PORTC_gc = (0x02<<4), /* Mapped To PORTC */ - PORTCFG_VP13MAP_PORTD_gc = (0x03<<4), /* Mapped To PORTD */ - PORTCFG_VP13MAP_PORTE_gc = (0x04<<4), /* Mapped To PORTE */ - PORTCFG_VP13MAP_PORTF_gc = (0x05<<4), /* Mapped To PORTF */ - PORTCFG_VP13MAP_PORTG_gc = (0x06<<4), /* Mapped To PORTG */ - PORTCFG_VP13MAP_PORTH_gc = (0x07<<4), /* Mapped To PORTH */ - PORTCFG_VP13MAP_PORTJ_gc = (0x08<<4), /* Mapped To PORTJ */ - PORTCFG_VP13MAP_PORTK_gc = (0x09<<4), /* Mapped To PORTK */ - PORTCFG_VP13MAP_PORTL_gc = (0x0A<<4), /* Mapped To PORTL */ - PORTCFG_VP13MAP_PORTM_gc = (0x0B<<4), /* Mapped To PORTM */ - PORTCFG_VP13MAP_PORTN_gc = (0x0C<<4), /* Mapped To PORTN */ - PORTCFG_VP13MAP_PORTP_gc = (0x0D<<4), /* Mapped To PORTP */ - PORTCFG_VP13MAP_PORTQ_gc = (0x0E<<4), /* Mapped To PORTQ */ - PORTCFG_VP13MAP_PORTR_gc = (0x0F<<4), /* Mapped To PORTR */ -} PORTCFG_VP13MAP_t; - -/* System Clock Output Port */ -typedef enum PORTCFG_CLKOUT_enum -{ - PORTCFG_CLKOUT_OFF_gc = (0x00<<0), /* System Clock Output Disabled */ - PORTCFG_CLKOUT_PC7_gc = (0x01<<0), /* System Clock Output on Port C pin 7 */ - PORTCFG_CLKOUT_PD7_gc = (0x02<<0), /* System Clock Output on Port D pin 7 */ - PORTCFG_CLKOUT_PE7_gc = (0x03<<0), /* System Clock Output on Port E pin 7 */ -} PORTCFG_CLKOUT_t; - -/* Peripheral Clock Output Select */ -typedef enum PORTCFG_CLKOUTSEL_enum -{ - PORTCFG_CLKOUTSEL_CLK1X_gc = (0x00<<2), /* 1x Peripheral Clock Output to pin */ - PORTCFG_CLKOUTSEL_CLK2X_gc = (0x01<<2), /* 2x Peripheral Clock Output to pin */ - PORTCFG_CLKOUTSEL_CLK4X_gc = (0x02<<2), /* 4x Peripheral Clock Output to pin */ -} PORTCFG_CLKOUTSEL_t; - -/* Event Output Port */ -typedef enum PORTCFG_EVOUT_enum -{ - PORTCFG_EVOUT_OFF_gc = (0x00<<4), /* Event Output Disabled */ - PORTCFG_EVOUT_PC7_gc = (0x01<<4), /* Event Channel 7 Output on Port C pin 7 */ - PORTCFG_EVOUT_PD7_gc = (0x02<<4), /* Event Channel 7 Output on Port D pin 7 */ - PORTCFG_EVOUT_PE7_gc = (0x03<<4), /* Event Channel 7 Output on Port E pin 7 */ -} PORTCFG_EVOUT_t; - -/* Event Output Select */ -typedef enum PORTCFG_EVOUTSEL_enum -{ - PORTCFG_EVOUTSEL_0_gc = (0x00<<0), /* Event Channel 0 output to pin */ - PORTCFG_EVOUTSEL_1_gc = (0x01<<0), /* Event Channel 1 output to pin */ - PORTCFG_EVOUTSEL_2_gc = (0x02<<0), /* Event Channel 2 output to pin */ - PORTCFG_EVOUTSEL_3_gc = (0x03<<0), /* Event Channel 3 output to pin */ -} PORTCFG_EVOUTSEL_t; - - -/* --------------------------------------------------------------------------- -CRC - Cyclic Redundancy Checker --------------------------------------------------------------------------- -*/ - -/* Cyclic Redundancy Checker */ -typedef struct CRC_struct -{ - register8_t CTRL; /* Control Register */ - register8_t STATUS; /* Status Register */ - register8_t reserved_0x02; - register8_t DATAIN; /* Data Input */ - register8_t CHECKSUM0; /* Checksum byte 0 */ - register8_t CHECKSUM1; /* Checksum byte 1 */ - register8_t CHECKSUM2; /* Checksum byte 2 */ - register8_t CHECKSUM3; /* Checksum byte 3 */ -} CRC_t; - -/* Reset */ -typedef enum CRC_RESET_enum -{ - CRC_RESET_NO_gc = (0x00<<6), /* No Reset */ - CRC_RESET_RESET0_gc = (0x02<<6), /* Reset CRC with CHECKSUM to all zeros */ - CRC_RESET_RESET1_gc = (0x03<<6), /* Reset CRC with CHECKSUM to all ones */ -} CRC_RESET_t; - -/* Input Source */ -typedef enum CRC_SOURCE_enum -{ - CRC_SOURCE_DISABLE_gc = (0x00<<0), /* Disabled */ - CRC_SOURCE_IO_gc = (0x01<<0), /* I/O Interface */ - CRC_SOURCE_FLASH_gc = (0x02<<0), /* Flash */ -} CRC_SOURCE_t; - - -/* --------------------------------------------------------------------------- -EVSYS - Event System --------------------------------------------------------------------------- -*/ - -/* Event System */ -typedef struct EVSYS_struct -{ - register8_t CH0MUX; /* Event Channel 0 Multiplexer */ - register8_t CH1MUX; /* Event Channel 1 Multiplexer */ - register8_t CH2MUX; /* Event Channel 2 Multiplexer */ - register8_t CH3MUX; /* Event Channel 3 Multiplexer */ - register8_t reserved_0x04; - register8_t reserved_0x05; - register8_t reserved_0x06; - register8_t reserved_0x07; - register8_t CH0CTRL; /* Channel 0 Control Register */ - register8_t CH1CTRL; /* Channel 1 Control Register */ - register8_t CH2CTRL; /* Channel 2 Control Register */ - register8_t CH3CTRL; /* Channel 3 Control Register */ - register8_t reserved_0x0C; - register8_t reserved_0x0D; - register8_t reserved_0x0E; - register8_t reserved_0x0F; - register8_t STROBE; /* Event Strobe */ - register8_t DATA; /* Event Data */ -} EVSYS_t; - -/* Quadrature Decoder Index Recognition Mode */ -typedef enum EVSYS_QDIRM_enum -{ - EVSYS_QDIRM_00_gc = (0x00<<5), /* QDPH0 = 0, QDPH90 = 0 */ - EVSYS_QDIRM_01_gc = (0x01<<5), /* QDPH0 = 0, QDPH90 = 1 */ - EVSYS_QDIRM_10_gc = (0x02<<5), /* QDPH0 = 1, QDPH90 = 0 */ - EVSYS_QDIRM_11_gc = (0x03<<5), /* QDPH0 = 1, QDPH90 = 1 */ -} EVSYS_QDIRM_t; - -/* Digital filter coefficient */ -typedef enum EVSYS_DIGFILT_enum -{ - EVSYS_DIGFILT_1SAMPLE_gc = (0x00<<0), /* 1 SAMPLE */ - EVSYS_DIGFILT_2SAMPLES_gc = (0x01<<0), /* 2 SAMPLES */ - EVSYS_DIGFILT_3SAMPLES_gc = (0x02<<0), /* 3 SAMPLES */ - EVSYS_DIGFILT_4SAMPLES_gc = (0x03<<0), /* 4 SAMPLES */ - EVSYS_DIGFILT_5SAMPLES_gc = (0x04<<0), /* 5 SAMPLES */ - EVSYS_DIGFILT_6SAMPLES_gc = (0x05<<0), /* 6 SAMPLES */ - EVSYS_DIGFILT_7SAMPLES_gc = (0x06<<0), /* 7 SAMPLES */ - EVSYS_DIGFILT_8SAMPLES_gc = (0x07<<0), /* 8 SAMPLES */ -} EVSYS_DIGFILT_t; - -/* Event Channel multiplexer input selection */ -typedef enum EVSYS_CHMUX_enum -{ - EVSYS_CHMUX_OFF_gc = (0x00<<0), /* Off */ - EVSYS_CHMUX_RTC_OVF_gc = (0x08<<0), /* RTC Overflow */ - EVSYS_CHMUX_RTC_CMP_gc = (0x09<<0), /* RTC Compare Match */ - EVSYS_CHMUX_USB_gc = (0x0A<<0), /* USB Setup, SOF, CRC error and UNF/OVF */ - EVSYS_CHMUX_ACA_CH0_gc = (0x10<<0), /* Analog Comparator A Channel 0 */ - EVSYS_CHMUX_ACA_CH1_gc = (0x11<<0), /* Analog Comparator A Channel 1 */ - EVSYS_CHMUX_ACA_WIN_gc = (0x12<<0), /* Analog Comparator A Window */ - EVSYS_CHMUX_ADCA_CH0_gc = (0x20<<0), /* ADC A Channel */ - EVSYS_CHMUX_PORTA_PIN0_gc = (0x50<<0), /* Port A, Pin0 */ - EVSYS_CHMUX_PORTA_PIN1_gc = (0x51<<0), /* Port A, Pin1 */ - EVSYS_CHMUX_PORTA_PIN2_gc = (0x52<<0), /* Port A, Pin2 */ - EVSYS_CHMUX_PORTA_PIN3_gc = (0x53<<0), /* Port A, Pin3 */ - EVSYS_CHMUX_PORTA_PIN4_gc = (0x54<<0), /* Port A, Pin4 */ - EVSYS_CHMUX_PORTA_PIN5_gc = (0x55<<0), /* Port A, Pin5 */ - EVSYS_CHMUX_PORTA_PIN6_gc = (0x56<<0), /* Port A, Pin6 */ - EVSYS_CHMUX_PORTA_PIN7_gc = (0x57<<0), /* Port A, Pin7 */ - EVSYS_CHMUX_PORTB_PIN0_gc = (0x58<<0), /* Port B, Pin0 */ - EVSYS_CHMUX_PORTB_PIN1_gc = (0x59<<0), /* Port B, Pin1 */ - EVSYS_CHMUX_PORTB_PIN2_gc = (0x5A<<0), /* Port B, Pin2 */ - EVSYS_CHMUX_PORTB_PIN3_gc = (0x5B<<0), /* Port B, Pin3 */ - EVSYS_CHMUX_PORTB_PIN4_gc = (0x5C<<0), /* Port B, Pin4 */ - EVSYS_CHMUX_PORTB_PIN5_gc = (0x5D<<0), /* Port B, Pin5 */ - EVSYS_CHMUX_PORTB_PIN6_gc = (0x5E<<0), /* Port B, Pin6 */ - EVSYS_CHMUX_PORTB_PIN7_gc = (0x5F<<0), /* Port B, Pin7 */ - EVSYS_CHMUX_PORTC_PIN0_gc = (0x60<<0), /* Port C, Pin0 */ - EVSYS_CHMUX_PORTC_PIN1_gc = (0x61<<0), /* Port C, Pin1 */ - EVSYS_CHMUX_PORTC_PIN2_gc = (0x62<<0), /* Port C, Pin2 */ - EVSYS_CHMUX_PORTC_PIN3_gc = (0x63<<0), /* Port C, Pin3 */ - EVSYS_CHMUX_PORTC_PIN4_gc = (0x64<<0), /* Port C, Pin4 */ - EVSYS_CHMUX_PORTC_PIN5_gc = (0x65<<0), /* Port C, Pin5 */ - EVSYS_CHMUX_PORTC_PIN6_gc = (0x66<<0), /* Port C, Pin6 */ - EVSYS_CHMUX_PORTC_PIN7_gc = (0x67<<0), /* Port C, Pin7 */ - EVSYS_CHMUX_PORTD_PIN0_gc = (0x68<<0), /* Port D, Pin0 */ - EVSYS_CHMUX_PORTD_PIN1_gc = (0x69<<0), /* Port D, Pin1 */ - EVSYS_CHMUX_PORTD_PIN2_gc = (0x6A<<0), /* Port D, Pin2 */ - EVSYS_CHMUX_PORTD_PIN3_gc = (0x6B<<0), /* Port D, Pin3 */ - EVSYS_CHMUX_PORTD_PIN4_gc = (0x6C<<0), /* Port D, Pin4 */ - EVSYS_CHMUX_PORTD_PIN5_gc = (0x6D<<0), /* Port D, Pin5 */ - EVSYS_CHMUX_PORTD_PIN6_gc = (0x6E<<0), /* Port D, Pin6 */ - EVSYS_CHMUX_PORTD_PIN7_gc = (0x6F<<0), /* Port D, Pin7 */ - EVSYS_CHMUX_PORTE_PIN0_gc = (0x70<<0), /* Port E, Pin0 */ - EVSYS_CHMUX_PORTE_PIN1_gc = (0x71<<0), /* Port E, Pin1 */ - EVSYS_CHMUX_PORTE_PIN2_gc = (0x72<<0), /* Port E, Pin2 */ - EVSYS_CHMUX_PORTE_PIN3_gc = (0x73<<0), /* Port E, Pin3 */ - EVSYS_CHMUX_PORTE_PIN4_gc = (0x74<<0), /* Port E, Pin4 */ - EVSYS_CHMUX_PORTE_PIN5_gc = (0x75<<0), /* Port E, Pin5 */ - EVSYS_CHMUX_PORTE_PIN6_gc = (0x76<<0), /* Port E, Pin6 */ - EVSYS_CHMUX_PORTE_PIN7_gc = (0x77<<0), /* Port E, Pin7 */ - EVSYS_CHMUX_PORTF_PIN0_gc = (0x78<<0), /* Port F, Pin0 */ - EVSYS_CHMUX_PORTF_PIN1_gc = (0x79<<0), /* Port F, Pin1 */ - EVSYS_CHMUX_PORTF_PIN2_gc = (0x7A<<0), /* Port F, Pin2 */ - EVSYS_CHMUX_PORTF_PIN3_gc = (0x7B<<0), /* Port F, Pin3 */ - EVSYS_CHMUX_PORTF_PIN4_gc = (0x7C<<0), /* Port F, Pin4 */ - EVSYS_CHMUX_PORTF_PIN5_gc = (0x7D<<0), /* Port F, Pin5 */ - EVSYS_CHMUX_PORTF_PIN6_gc = (0x7E<<0), /* Port F, Pin6 */ - EVSYS_CHMUX_PORTF_PIN7_gc = (0x7F<<0), /* Port F, Pin7 */ - EVSYS_CHMUX_PRESCALER_1_gc = (0x80<<0), /* Prescaler, divide by 1 */ - EVSYS_CHMUX_PRESCALER_2_gc = (0x81<<0), /* Prescaler, divide by 2 */ - EVSYS_CHMUX_PRESCALER_4_gc = (0x82<<0), /* Prescaler, divide by 4 */ - EVSYS_CHMUX_PRESCALER_8_gc = (0x83<<0), /* Prescaler, divide by 8 */ - EVSYS_CHMUX_PRESCALER_16_gc = (0x84<<0), /* Prescaler, divide by 16 */ - EVSYS_CHMUX_PRESCALER_32_gc = (0x85<<0), /* Prescaler, divide by 32 */ - EVSYS_CHMUX_PRESCALER_64_gc = (0x86<<0), /* Prescaler, divide by 64 */ - EVSYS_CHMUX_PRESCALER_128_gc = (0x87<<0), /* Prescaler, divide by 128 */ - EVSYS_CHMUX_PRESCALER_256_gc = (0x88<<0), /* Prescaler, divide by 256 */ - EVSYS_CHMUX_PRESCALER_512_gc = (0x89<<0), /* Prescaler, divide by 512 */ - EVSYS_CHMUX_PRESCALER_1024_gc = (0x8A<<0), /* Prescaler, divide by 1024 */ - EVSYS_CHMUX_PRESCALER_2048_gc = (0x8B<<0), /* Prescaler, divide by 2048 */ - EVSYS_CHMUX_PRESCALER_4096_gc = (0x8C<<0), /* Prescaler, divide by 4096 */ - EVSYS_CHMUX_PRESCALER_8192_gc = (0x8D<<0), /* Prescaler, divide by 8192 */ - EVSYS_CHMUX_PRESCALER_16384_gc = (0x8E<<0), /* Prescaler, divide by 16384 */ - EVSYS_CHMUX_PRESCALER_32768_gc = (0x8F<<0), /* Prescaler, divide by 32768 */ - EVSYS_CHMUX_TCC0_OVF_gc = (0xC0<<0), /* Timer/Counter C0 Overflow */ - EVSYS_CHMUX_TCC0_ERR_gc = (0xC1<<0), /* Timer/Counter C0 Error */ - EVSYS_CHMUX_TCC0_CCA_gc = (0xC4<<0), /* Timer/Counter C0 Compare or Capture A */ - EVSYS_CHMUX_TCC0_CCB_gc = (0xC5<<0), /* Timer/Counter C0 Compare or Capture B */ - EVSYS_CHMUX_TCC0_CCC_gc = (0xC6<<0), /* Timer/Counter C0 Compare or Capture C */ - EVSYS_CHMUX_TCC0_CCD_gc = (0xC7<<0), /* Timer/Counter C0 Compare or Capture D */ - EVSYS_CHMUX_TCC1_OVF_gc = (0xC8<<0), /* Timer/Counter C1 Overflow */ - EVSYS_CHMUX_TCC1_ERR_gc = (0xC9<<0), /* Timer/Counter C1 Error */ - EVSYS_CHMUX_TCC1_CCA_gc = (0xCC<<0), /* Timer/Counter C1 Compare or Capture A */ - EVSYS_CHMUX_TCC1_CCB_gc = (0xCD<<0), /* Timer/Counter C1 Compare or Capture B */ - EVSYS_CHMUX_TCD0_OVF_gc = (0xD0<<0), /* Timer/Counter D0 Overflow */ - EVSYS_CHMUX_TCD0_ERR_gc = (0xD1<<0), /* Timer/Counter D0 Error */ - EVSYS_CHMUX_TCD0_CCA_gc = (0xD4<<0), /* Timer/Counter D0 Compare or Capture A */ - EVSYS_CHMUX_TCD0_CCB_gc = (0xD5<<0), /* Timer/Counter D0 Compare or Capture B */ - EVSYS_CHMUX_TCD0_CCC_gc = (0xD6<<0), /* Timer/Counter D0 Compare or Capture C */ - EVSYS_CHMUX_TCD0_CCD_gc = (0xD7<<0), /* Timer/Counter D0 Compare or Capture D */ - EVSYS_CHMUX_TCE0_OVF_gc = (0xE0<<0), /* Timer/Counter E0 Overflow */ - EVSYS_CHMUX_TCE0_ERR_gc = (0xE1<<0), /* Timer/Counter E0 Error */ - EVSYS_CHMUX_TCE0_CCA_gc = (0xE4<<0), /* Timer/Counter E0 Compare or Capture A */ - EVSYS_CHMUX_TCE0_CCB_gc = (0xE5<<0), /* Timer/Counter E0 Compare or Capture B */ - EVSYS_CHMUX_TCE0_CCC_gc = (0xE6<<0), /* Timer/Counter E0 Compare or Capture C */ - EVSYS_CHMUX_TCE0_CCD_gc = (0xE7<<0), /* Timer/Counter E0 Compare or Capture D */ - EVSYS_CHMUX_TCF0_OVF_gc = (0xF0<<0), /* Timer/Counter F0 Overflow */ - EVSYS_CHMUX_TCF0_ERR_gc = (0xF1<<0), /* Timer/Counter F0 Error */ - EVSYS_CHMUX_TCF0_CCA_gc = (0xF4<<0), /* Timer/Counter F0 Compare or Capture A */ - EVSYS_CHMUX_TCF0_CCB_gc = (0xF5<<0), /* Timer/Counter F0 Compare or Capture B */ - EVSYS_CHMUX_TCF0_CCC_gc = (0xF6<<0), /* Timer/Counter F0 Compare or Capture C */ - EVSYS_CHMUX_TCF0_CCD_gc = (0xF7<<0), /* Timer/Counter F0 Compare or Capture D */ -} EVSYS_CHMUX_t; - - -/* --------------------------------------------------------------------------- -NVM - Non Volatile Memory Controller --------------------------------------------------------------------------- -*/ - -/* Non-volatile Memory Controller */ -typedef struct NVM_struct -{ - register8_t ADDR0; /* Address Register 0 */ - register8_t ADDR1; /* Address Register 1 */ - register8_t ADDR2; /* Address Register 2 */ - register8_t reserved_0x03; - register8_t DATA0; /* Data Register 0 */ - register8_t DATA1; /* Data Register 1 */ - register8_t DATA2; /* Data Register 2 */ - register8_t reserved_0x07; - register8_t reserved_0x08; - register8_t reserved_0x09; - register8_t CMD; /* Command */ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t INTCTRL; /* Interrupt Control */ - register8_t reserved_0x0E; - register8_t STATUS; /* Status */ - register8_t LOCK_BITS; /* Lock Bits (Changed from LOCKBITS to avoid avr-libc collision) */ -} NVM_t; - -/* NVM Command */ -typedef enum NVM_CMD_enum -{ - NVM_CMD_NO_OPERATION_gc = (0x00<<0), /* Noop/Ordinary LPM */ - NVM_CMD_READ_USER_SIG_ROW_gc = (0x01<<0), /* Read user signature row */ - NVM_CMD_READ_CALIB_ROW_gc = (0x02<<0), /* Read calibration row */ - NVM_CMD_READ_EEPROM_gc = (0x06<<0), /* Read EEPROM */ - NVM_CMD_READ_FUSES_gc = (0x07<<0), /* Read fuse byte */ - NVM_CMD_WRITE_LOCK_BITS_gc = (0x08<<0), /* Write lock bits */ - NVM_CMD_ERASE_USER_SIG_ROW_gc = (0x18<<0), /* Erase user signature row */ - NVM_CMD_WRITE_USER_SIG_ROW_gc = (0x1A<<0), /* Write user signature row */ - NVM_CMD_ERASE_APP_gc = (0x20<<0), /* Erase Application Section */ - NVM_CMD_ERASE_APP_PAGE_gc = (0x22<<0), /* Erase Application Section page */ - NVM_CMD_LOAD_FLASH_BUFFER_gc = (0x23<<0), /* Load Flash page buffer */ - NVM_CMD_WRITE_APP_PAGE_gc = (0x24<<0), /* Write Application Section page */ - NVM_CMD_ERASE_WRITE_APP_PAGE_gc = (0x25<<0), /* Erase-and-write Application Section page */ - NVM_CMD_ERASE_FLASH_BUFFER_gc = (0x26<<0), /* Erase/flush Flash page buffer */ - NVM_CMD_ERASE_BOOT_PAGE_gc = (0x2A<<0), /* Erase Boot Section page */ - NVM_CMD_ERASE_FLASH_PAGE_gc = (0x2B<<0), /* Erase Flash Page */ - NVM_CMD_WRITE_BOOT_PAGE_gc = (0x2C<<0), /* Write Boot Section page */ - NVM_CMD_ERASE_WRITE_BOOT_PAGE_gc = (0x2D<<0), /* Erase-and-write Boot Section page */ - NVM_CMD_WRITE_FLASH_PAGE_gc = (0x2E<<0), /* Write Flash Page */ - NVM_CMD_ERASE_WRITE_FLASH_PAGE_gc = (0x2F<<0), /* Erase-and-write Flash Page */ - NVM_CMD_ERASE_EEPROM_gc = (0x30<<0), /* Erase EEPROM */ - NVM_CMD_ERASE_EEPROM_PAGE_gc = (0x32<<0), /* Erase EEPROM page */ - NVM_CMD_LOAD_EEPROM_BUFFER_gc = (0x33<<0), /* Load EEPROM page buffer */ - NVM_CMD_WRITE_EEPROM_PAGE_gc = (0x34<<0), /* Write EEPROM page */ - NVM_CMD_ERASE_WRITE_EEPROM_PAGE_gc = (0x35<<0), /* Erase-and-write EEPROM page */ - NVM_CMD_ERASE_EEPROM_BUFFER_gc = (0x36<<0), /* Erase/flush EEPROM page buffer */ - NVM_CMD_APP_CRC_gc = (0x38<<0), /* Application section CRC */ - NVM_CMD_BOOT_CRC_gc = (0x39<<0), /* Boot Section CRC */ - NVM_CMD_FLASH_RANGE_CRC_gc = (0x3A<<0), /* Flash Range CRC */ - NVM_CMD_CHIP_ERASE_gc = (0x40<<0), /* Erase Chip */ - NVM_CMD_READ_NVM_gc = (0x43<<0), /* Read NVM */ - NVM_CMD_WRITE_FUSE_gc = (0x4C<<0), /* Write Fuse byte */ - NVM_CMD_ERASE_BOOT_gc = (0x68<<0), /* Erase Boot Section */ - NVM_CMD_FLASH_CRC_gc = (0x78<<0), /* Flash CRC */ -} NVM_CMD_t; - -/* SPM ready interrupt level */ -typedef enum NVM_SPMLVL_enum -{ - NVM_SPMLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ - NVM_SPMLVL_LO_gc = (0x01<<2), /* Low level */ - NVM_SPMLVL_MED_gc = (0x02<<2), /* Medium level */ - NVM_SPMLVL_HI_gc = (0x03<<2), /* High level */ -} NVM_SPMLVL_t; - -/* EEPROM ready interrupt level */ -typedef enum NVM_EELVL_enum -{ - NVM_EELVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ - NVM_EELVL_LO_gc = (0x01<<0), /* Low level */ - NVM_EELVL_MED_gc = (0x02<<0), /* Medium level */ - NVM_EELVL_HI_gc = (0x03<<0), /* High level */ -} NVM_EELVL_t; - -/* Boot lock bits - boot setcion */ -typedef enum NVM_BLBB_enum -{ - NVM_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ - NVM_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ - NVM_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ - NVM_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ -} NVM_BLBB_t; - -/* Boot lock bits - application section */ -typedef enum NVM_BLBA_enum -{ - NVM_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ - NVM_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ - NVM_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ - NVM_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ -} NVM_BLBA_t; - -/* Boot lock bits - application table section */ -typedef enum NVM_BLBAT_enum -{ - NVM_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ - NVM_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ - NVM_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ - NVM_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ -} NVM_BLBAT_t; - -/* Lock bits */ -typedef enum NVM_LB_enum -{ - NVM_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ - NVM_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ - NVM_LB_NOLOCK_gc = (0x03<<0), /* No locks */ -} NVM_LB_t; - - -/* --------------------------------------------------------------------------- -ADC - Analog/Digital Converter --------------------------------------------------------------------------- -*/ - -/* ADC Channel */ -typedef struct ADC_CH_struct -{ - register8_t CTRL; /* Control Register */ - register8_t MUXCTRL; /* MUX Control */ - register8_t INTCTRL; /* Channel Interrupt Control Register */ - register8_t INTFLAGS; /* Interrupt Flags */ - _WORDREGISTER(RES); /* Channel Result */ - register8_t SCAN; /* Input Channel Scan */ - register8_t reserved_0x07; -} ADC_CH_t; - - -/* Analog-to-Digital Converter */ -typedef struct ADC_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t REFCTRL; /* Reference Control */ - register8_t EVCTRL; /* Event Control */ - register8_t PRESCALER; /* Clock Prescaler */ - register8_t reserved_0x05; - register8_t INTFLAGS; /* Interrupt Flags */ - register8_t TEMP; /* Temporary Register */ - register8_t reserved_0x08; - register8_t reserved_0x09; - register8_t reserved_0x0A; - register8_t reserved_0x0B; - _WORDREGISTER(CAL); /* Calibration Value */ - register8_t reserved_0x0E; - register8_t reserved_0x0F; - _WORDREGISTER(CH0RES); /* Channel 0 Result */ - register8_t reserved_0x12; - register8_t reserved_0x13; - register8_t reserved_0x14; - register8_t reserved_0x15; - register8_t reserved_0x16; - register8_t reserved_0x17; - _WORDREGISTER(CMP); /* Compare Value */ - register8_t reserved_0x1A; - register8_t reserved_0x1B; - register8_t reserved_0x1C; - register8_t reserved_0x1D; - register8_t reserved_0x1E; - register8_t reserved_0x1F; - ADC_CH_t CH0; /* ADC Channel 0 */ -} ADC_t; - -/* Current Limitation */ -typedef enum ADC_CURRLIMIT_enum -{ - ADC_CURRLIMIT_NO_gc = (0x00<<5), /* No current limit, 300ksps max sampling rate */ - ADC_CURRLIMIT_LOW_gc = (0x01<<5), /* Low current limit, 250ksps max sampling rate */ - ADC_CURRLIMIT_MED_gc = (0x02<<5), /* Medium current limit, 150ksps max sampling rate */ - ADC_CURRLIMIT_HIGH_gc = (0x03<<5), /* High current limit, 50ksps max sampling rate */ -} ADC_CURRLIMIT_t; - -/* Positive input multiplexer selection */ -typedef enum ADC_CH_MUXPOS_enum -{ - ADC_CH_MUXPOS_PIN0_gc = (0x00<<3), /* Input pin 0 */ - ADC_CH_MUXPOS_PIN1_gc = (0x01<<3), /* Input pin 1 */ - ADC_CH_MUXPOS_PIN2_gc = (0x02<<3), /* Input pin 2 */ - ADC_CH_MUXPOS_PIN3_gc = (0x03<<3), /* Input pin 3 */ - ADC_CH_MUXPOS_PIN4_gc = (0x04<<3), /* Input pin 4 */ - ADC_CH_MUXPOS_PIN5_gc = (0x05<<3), /* Input pin 5 */ - ADC_CH_MUXPOS_PIN6_gc = (0x06<<3), /* Input pin 6 */ - ADC_CH_MUXPOS_PIN7_gc = (0x07<<3), /* Input pin 7 */ - ADC_CH_MUXPOS_PIN8_gc = (0x08<<3), /* Input pin 8 */ - ADC_CH_MUXPOS_PIN9_gc = (0x09<<3), /* Input pin 9 */ - ADC_CH_MUXPOS_PIN10_gc = (0x0A<<3), /* Input pin 10 */ - ADC_CH_MUXPOS_PIN11_gc = (0x0B<<3), /* Input pin 11 */ - ADC_CH_MUXPOS_PIN12_gc = (0x0C<<3), /* Input pin 12 */ - ADC_CH_MUXPOS_PIN13_gc = (0x0D<<3), /* Input pin 13 */ - ADC_CH_MUXPOS_PIN14_gc = (0x0E<<3), /* Input pin 14 */ - ADC_CH_MUXPOS_PIN15_gc = (0x0F<<3), /* Input pin 15 */ -} ADC_CH_MUXPOS_t; - -/* Internal input multiplexer selections */ -typedef enum ADC_CH_MUXINT_enum -{ - ADC_CH_MUXINT_TEMP_gc = (0x00<<3), /* Temperature Reference */ - ADC_CH_MUXINT_BANDGAP_gc = (0x01<<3), /* Bandgap Reference */ - ADC_CH_MUXINT_SCALEDVCC_gc = (0x02<<3), /* 1/10 scaled VCC */ -} ADC_CH_MUXINT_t; - -/* Negative input multiplexer selection */ -typedef enum ADC_CH_MUXNEG_enum -{ - ADC_CH_MUXNEG_PIN0_gc = (0x00<<0), /* Input pin 0 */ - ADC_CH_MUXNEG_PIN1_gc = (0x01<<0), /* Input pin 1 */ - ADC_CH_MUXNEG_PIN2_gc = (0x02<<0), /* Input pin 2 */ - ADC_CH_MUXNEG_PIN3_gc = (0x03<<0), /* Input pin 3 */ - ADC_CH_MUXNEG_PIN4_gc = (0x00<<0), /* Input pin 4 */ - ADC_CH_MUXNEG_PIN5_gc = (0x01<<0), /* Input pin 5 */ - ADC_CH_MUXNEG_PIN6_gc = (0x02<<0), /* Input pin 6 */ - ADC_CH_MUXNEG_PIN7_gc = (0x03<<0), /* Input pin 7 */ -} ADC_CH_MUXNEG_t; - -/* Input mode */ -typedef enum ADC_CH_INPUTMODE_enum -{ - ADC_CH_INPUTMODE_INTERNAL_gc = (0x00<<0), /* Internal inputs, no gain */ - ADC_CH_INPUTMODE_SINGLEENDED_gc = (0x01<<0), /* Single-ended input, no gain */ - ADC_CH_INPUTMODE_DIFF_gc = (0x02<<0), /* Differential input, no gain */ - ADC_CH_INPUTMODE_DIFFWGAIN_gc = (0x03<<0), /* Differential input, with gain */ -} ADC_CH_INPUTMODE_t; - -/* Gain factor */ -typedef enum ADC_CH_GAIN_enum -{ - ADC_CH_GAIN_1X_gc = (0x00<<2), /* 1x gain */ - ADC_CH_GAIN_2X_gc = (0x01<<2), /* 2x gain */ - ADC_CH_GAIN_4X_gc = (0x02<<2), /* 4x gain */ - ADC_CH_GAIN_8X_gc = (0x03<<2), /* 8x gain */ - ADC_CH_GAIN_16X_gc = (0x04<<2), /* 16x gain */ - ADC_CH_GAIN_32X_gc = (0x05<<2), /* 32x gain */ - ADC_CH_GAIN_64X_gc = (0x06<<2), /* 64x gain */ - ADC_CH_GAIN_DIV2_gc = (0x07<<2), /* x/2 gain */ -} ADC_CH_GAIN_t; - -/* Conversion result resolution */ -typedef enum ADC_RESOLUTION_enum -{ - ADC_RESOLUTION_12BIT_gc = (0x00<<1), /* 12-bit right-adjusted result */ - ADC_RESOLUTION_8BIT_gc = (0x02<<1), /* 8-bit right-adjusted result */ - ADC_RESOLUTION_LEFT12BIT_gc = (0x03<<1), /* 12-bit left-adjusted result */ -} ADC_RESOLUTION_t; - -/* Voltage reference selection */ -typedef enum ADC_REFSEL_enum -{ - ADC_REFSEL_INT1V_gc = (0x00<<4), /* Internal 1V */ - ADC_REFSEL_INTVCC_gc = (0x01<<4), /* Internal VCC / 1.6 */ - ADC_REFSEL_AREFA_gc = (0x02<<4), /* External reference on PORT A */ - ADC_REFSEL_AREFB_gc = (0x03<<4), /* External reference on PORT B */ - ADC_REFSEL_INTVCC2_gc = (0x04<<4), /* Internal VCC / 2 */ -} ADC_REFSEL_t; - -/* Event channel input selection */ -typedef enum ADC_EVSEL_enum -{ - ADC_EVSEL_0_gc = (0x00<<3), /* Event Channel 0 */ - ADC_EVSEL_1_gc = (0x01<<3), /* Event Channel 1 */ - ADC_EVSEL_2_gc = (0x02<<3), /* Event Channel 2 */ - ADC_EVSEL_3_gc = (0x03<<3), /* Event Channel 3 */ -} ADC_EVSEL_t; - -/* Event action selection */ -typedef enum ADC_EVACT_enum -{ - ADC_EVACT_NONE_gc = (0x00<<0), /* No event action */ - ADC_EVACT_CH0_gc = (0x01<<0), /* First event triggers channel 0 */ - ADC_EVACT_SYNCSWEEP_gc = (0x06<<0), /* The ADC is flushed and restarted for accurate timing */ -} ADC_EVACT_t; - -/* Interupt mode */ -typedef enum ADC_CH_INTMODE_enum -{ - ADC_CH_INTMODE_COMPLETE_gc = (0x00<<2), /* Interrupt on conversion complete */ - ADC_CH_INTMODE_BELOW_gc = (0x01<<2), /* Interrupt on result below compare value */ - ADC_CH_INTMODE_ABOVE_gc = (0x03<<2), /* Interrupt on result above compare value */ -} ADC_CH_INTMODE_t; - -/* Interrupt level */ -typedef enum ADC_CH_INTLVL_enum -{ - ADC_CH_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ - ADC_CH_INTLVL_LO_gc = (0x01<<0), /* Low level */ - ADC_CH_INTLVL_MED_gc = (0x02<<0), /* Medium level */ - ADC_CH_INTLVL_HI_gc = (0x03<<0), /* High level */ -} ADC_CH_INTLVL_t; - -/* Clock prescaler */ -typedef enum ADC_PRESCALER_enum -{ - ADC_PRESCALER_DIV4_gc = (0x00<<0), /* Divide clock by 4 */ - ADC_PRESCALER_DIV8_gc = (0x01<<0), /* Divide clock by 8 */ - ADC_PRESCALER_DIV16_gc = (0x02<<0), /* Divide clock by 16 */ - ADC_PRESCALER_DIV32_gc = (0x03<<0), /* Divide clock by 32 */ - ADC_PRESCALER_DIV64_gc = (0x04<<0), /* Divide clock by 64 */ - ADC_PRESCALER_DIV128_gc = (0x05<<0), /* Divide clock by 128 */ - ADC_PRESCALER_DIV256_gc = (0x06<<0), /* Divide clock by 256 */ - ADC_PRESCALER_DIV512_gc = (0x07<<0), /* Divide clock by 512 */ -} ADC_PRESCALER_t; - - -/* --------------------------------------------------------------------------- -AC - Analog Comparator --------------------------------------------------------------------------- -*/ - -/* Analog Comparator */ -typedef struct AC_struct -{ - register8_t AC0CTRL; /* Analog Comparator 0 Control */ - register8_t AC1CTRL; /* Analog Comparator 1 Control */ - register8_t AC0MUXCTRL; /* Analog Comparator 0 MUX Control */ - register8_t AC1MUXCTRL; /* Analog Comparator 1 MUX Control */ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t WINCTRL; /* Window Mode Control */ - register8_t STATUS; /* Status */ -} AC_t; - -/* Interrupt mode */ -typedef enum AC_INTMODE_enum -{ - AC_INTMODE_BOTHEDGES_gc = (0x00<<6), /* Interrupt on both edges */ - AC_INTMODE_FALLING_gc = (0x02<<6), /* Interrupt on falling edge */ - AC_INTMODE_RISING_gc = (0x03<<6), /* Interrupt on rising edge */ -} AC_INTMODE_t; - -/* Interrupt level */ -typedef enum AC_INTLVL_enum -{ - AC_INTLVL_OFF_gc = (0x00<<4), /* Interrupt disabled */ - AC_INTLVL_LO_gc = (0x01<<4), /* Low level */ - AC_INTLVL_MED_gc = (0x02<<4), /* Medium level */ - AC_INTLVL_HI_gc = (0x03<<4), /* High level */ -} AC_INTLVL_t; - -/* Hysteresis mode selection */ -typedef enum AC_HYSMODE_enum -{ - AC_HYSMODE_NO_gc = (0x00<<1), /* No hysteresis */ - AC_HYSMODE_SMALL_gc = (0x01<<1), /* Small hysteresis */ - AC_HYSMODE_LARGE_gc = (0x02<<1), /* Large hysteresis */ -} AC_HYSMODE_t; - -/* Positive input multiplexer selection */ -typedef enum AC_MUXPOS_enum -{ - AC_MUXPOS_PIN0_gc = (0x00<<3), /* Pin 0 */ - AC_MUXPOS_PIN1_gc = (0x01<<3), /* Pin 1 */ - AC_MUXPOS_PIN2_gc = (0x02<<3), /* Pin 2 */ - AC_MUXPOS_PIN3_gc = (0x03<<3), /* Pin 3 */ - AC_MUXPOS_PIN4_gc = (0x04<<3), /* Pin 4 */ - AC_MUXPOS_PIN5_gc = (0x05<<3), /* Pin 5 */ - AC_MUXPOS_PIN6_gc = (0x06<<3), /* Pin 6 */ -} AC_MUXPOS_t; - -/* Negative input multiplexer selection */ -typedef enum AC_MUXNEG_enum -{ - AC_MUXNEG_PIN0_gc = (0x00<<0), /* Pin 0 */ - AC_MUXNEG_PIN1_gc = (0x01<<0), /* Pin 1 */ - AC_MUXNEG_PIN3_gc = (0x02<<0), /* Pin 3 */ - AC_MUXNEG_PIN5_gc = (0x03<<0), /* Pin 5 */ - AC_MUXNEG_PIN7_gc = (0x04<<0), /* Pin 7 */ - AC_MUXNEG_BANDGAP_gc = (0x06<<0), /* Bandgap Reference */ - AC_MUXNEG_SCALER_gc = (0x07<<0), /* Internal voltage scaler */ -} AC_MUXNEG_t; - -/* Windows interrupt mode */ -typedef enum AC_WINTMODE_enum -{ - AC_WINTMODE_ABOVE_gc = (0x00<<2), /* Interrupt on above window */ - AC_WINTMODE_INSIDE_gc = (0x01<<2), /* Interrupt on inside window */ - AC_WINTMODE_BELOW_gc = (0x02<<2), /* Interrupt on below window */ - AC_WINTMODE_OUTSIDE_gc = (0x03<<2), /* Interrupt on outside window */ -} AC_WINTMODE_t; - -/* Window interrupt level */ -typedef enum AC_WINTLVL_enum -{ - AC_WINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ - AC_WINTLVL_LO_gc = (0x01<<0), /* Low priority */ - AC_WINTLVL_MED_gc = (0x02<<0), /* Medium priority */ - AC_WINTLVL_HI_gc = (0x03<<0), /* High priority */ -} AC_WINTLVL_t; - -/* Window mode state */ -typedef enum AC_WSTATE_enum -{ - AC_WSTATE_ABOVE_gc = (0x00<<6), /* Signal above window */ - AC_WSTATE_INSIDE_gc = (0x01<<6), /* Signal inside window */ - AC_WSTATE_BELOW_gc = (0x02<<6), /* Signal below window */ -} AC_WSTATE_t; - - -/* --------------------------------------------------------------------------- -RTC - Real-Time Counter --------------------------------------------------------------------------- -*/ - -/* Real-Time Counter */ -typedef struct RTC_struct -{ - register8_t CTRL; /* Control Register */ - register8_t STATUS; /* Status Register */ - register8_t INTCTRL; /* Interrupt Control Register */ - register8_t INTFLAGS; /* Interrupt Flags */ - register8_t TEMP; /* Temporary register */ - register8_t reserved_0x05; - register8_t reserved_0x06; - register8_t reserved_0x07; - _WORDREGISTER(CNT); /* Count Register */ - _WORDREGISTER(PER); /* Period Register */ - _WORDREGISTER(COMP); /* Compare Register */ -} RTC_t; - -/* Prescaler Factor */ -typedef enum RTC_PRESCALER_enum -{ - RTC_PRESCALER_OFF_gc = (0x00<<0), /* RTC Off */ - RTC_PRESCALER_DIV1_gc = (0x01<<0), /* RTC Clock */ - RTC_PRESCALER_DIV2_gc = (0x02<<0), /* RTC Clock / 2 */ - RTC_PRESCALER_DIV8_gc = (0x03<<0), /* RTC Clock / 8 */ - RTC_PRESCALER_DIV16_gc = (0x04<<0), /* RTC Clock / 16 */ - RTC_PRESCALER_DIV64_gc = (0x05<<0), /* RTC Clock / 64 */ - RTC_PRESCALER_DIV256_gc = (0x06<<0), /* RTC Clock / 256 */ - RTC_PRESCALER_DIV1024_gc = (0x07<<0), /* RTC Clock / 1024 */ -} RTC_PRESCALER_t; - -/* Compare Interrupt level */ -typedef enum RTC_COMPINTLVL_enum -{ - RTC_COMPINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ - RTC_COMPINTLVL_LO_gc = (0x01<<2), /* Low Level */ - RTC_COMPINTLVL_MED_gc = (0x02<<2), /* Medium Level */ - RTC_COMPINTLVL_HI_gc = (0x03<<2), /* High Level */ -} RTC_COMPINTLVL_t; - -/* Overflow Interrupt level */ -typedef enum RTC_OVFINTLVL_enum -{ - RTC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - RTC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ - RTC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ - RTC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ -} RTC_OVFINTLVL_t; - - -/* --------------------------------------------------------------------------- -TWI - Two-Wire Interface --------------------------------------------------------------------------- -*/ - -/* */ -typedef struct TWI_MASTER_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t CTRLC; /* Control Register C */ - register8_t STATUS; /* Status Register */ - register8_t BAUD; /* Baurd Rate Control Register */ - register8_t ADDR; /* Address Register */ - register8_t DATA; /* Data Register */ -} TWI_MASTER_t; - - -/* */ -typedef struct TWI_SLAVE_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t STATUS; /* Status Register */ - register8_t ADDR; /* Address Register */ - register8_t DATA; /* Data Register */ - register8_t ADDRMASK; /* Address Mask Register */ -} TWI_SLAVE_t; - - -/* Two-Wire Interface */ -typedef struct TWI_struct -{ - register8_t CTRL; /* TWI Common Control Register */ - TWI_MASTER_t MASTER; /* TWI master module */ - TWI_SLAVE_t SLAVE; /* TWI slave module */ -} TWI_t; - -/* SDA Hold Time */ -typedef enum TWI_SDAHOLD_enum -{ - TWI_SDAHOLD_OFF_gc = (0x00<<1), /* SDA Hold Time off */ - TWI_SDAHOLD_50NS_gc = (0x01<<1), /* SDA Hold Time 50 ns */ - TWI_SDAHOLD_300NS_gc = (0x02<<1), /* SDA Hold Time 300 ns */ - TWI_SDAHOLD_400NS_gc = (0x03<<1), /* SDA Hold Time 400 ns */ -} TWI_SDAHOLD_t; - -/* Master Interrupt Level */ -typedef enum TWI_MASTER_INTLVL_enum -{ - TWI_MASTER_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ - TWI_MASTER_INTLVL_LO_gc = (0x01<<6), /* Low Level */ - TWI_MASTER_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ - TWI_MASTER_INTLVL_HI_gc = (0x03<<6), /* High Level */ -} TWI_MASTER_INTLVL_t; - -/* Inactive Timeout */ -typedef enum TWI_MASTER_TIMEOUT_enum -{ - TWI_MASTER_TIMEOUT_DISABLED_gc = (0x00<<2), /* Bus Timeout Disabled */ - TWI_MASTER_TIMEOUT_50US_gc = (0x01<<2), /* 50 Microseconds */ - TWI_MASTER_TIMEOUT_100US_gc = (0x02<<2), /* 100 Microseconds */ - TWI_MASTER_TIMEOUT_200US_gc = (0x03<<2), /* 200 Microseconds */ -} TWI_MASTER_TIMEOUT_t; - -/* Master Command */ -typedef enum TWI_MASTER_CMD_enum -{ - TWI_MASTER_CMD_NOACT_gc = (0x00<<0), /* No Action */ - TWI_MASTER_CMD_REPSTART_gc = (0x01<<0), /* Issue Repeated Start Condition */ - TWI_MASTER_CMD_RECVTRANS_gc = (0x02<<0), /* Receive or Transmit Data */ - TWI_MASTER_CMD_STOP_gc = (0x03<<0), /* Issue Stop Condition */ -} TWI_MASTER_CMD_t; - -/* Master Bus State */ -typedef enum TWI_MASTER_BUSSTATE_enum -{ - TWI_MASTER_BUSSTATE_UNKNOWN_gc = (0x00<<0), /* Unknown Bus State */ - TWI_MASTER_BUSSTATE_IDLE_gc = (0x01<<0), /* Bus is Idle */ - TWI_MASTER_BUSSTATE_OWNER_gc = (0x02<<0), /* This Module Controls The Bus */ - TWI_MASTER_BUSSTATE_BUSY_gc = (0x03<<0), /* The Bus is Busy */ -} TWI_MASTER_BUSSTATE_t; - -/* Slave Interrupt Level */ -typedef enum TWI_SLAVE_INTLVL_enum -{ - TWI_SLAVE_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ - TWI_SLAVE_INTLVL_LO_gc = (0x01<<6), /* Low Level */ - TWI_SLAVE_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ - TWI_SLAVE_INTLVL_HI_gc = (0x03<<6), /* High Level */ -} TWI_SLAVE_INTLVL_t; - -/* Slave Command */ -typedef enum TWI_SLAVE_CMD_enum -{ - TWI_SLAVE_CMD_NOACT_gc = (0x00<<0), /* No Action */ - TWI_SLAVE_CMD_COMPTRANS_gc = (0x02<<0), /* Used To Complete a Transaction */ - TWI_SLAVE_CMD_RESPONSE_gc = (0x03<<0), /* Used in Response to Address/Data Interrupt */ -} TWI_SLAVE_CMD_t; - - -/* --------------------------------------------------------------------------- -USB - USB --------------------------------------------------------------------------- -*/ - -/* USB Endpoint */ -typedef struct USB_EP_struct -{ - register8_t STATUS; /* Endpoint Status */ - register8_t CTRL; /* Endpoint Control */ - _WORDREGISTER(CNT); /* USB Endpoint Counter */ - _WORDREGISTER(DATAPTR); /* Data Pointer */ - _WORDREGISTER(AUXDATA); /* Auxiliary Data */ -} USB_EP_t; - - -/* Universal Serial Bus */ -typedef struct USB_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t STATUS; /* Status Register */ - register8_t ADDR; /* Address Register */ - register8_t FIFOWP; /* FIFO Write Pointer Register */ - register8_t FIFORP; /* FIFO Read Pointer Register */ - _WORDREGISTER(EPPTR); /* Endpoint Configuration Table Pointer */ - register8_t INTCTRLA; /* Interrupt Control Register A */ - register8_t INTCTRLB; /* Interrupt Control Register B */ - register8_t INTFLAGSACLR; /* Clear Interrupt Flag Register A */ - register8_t INTFLAGSASET; /* Set Interrupt Flag Register A */ - register8_t INTFLAGSBCLR; /* Clear Interrupt Flag Register B */ - register8_t INTFLAGSBSET; /* Set Interrupt Flag Register B */ - register8_t reserved_0x0E; - register8_t reserved_0x0F; - register8_t reserved_0x10; - register8_t reserved_0x11; - register8_t reserved_0x12; - register8_t reserved_0x13; - register8_t reserved_0x14; - register8_t reserved_0x15; - register8_t reserved_0x16; - register8_t reserved_0x17; - register8_t reserved_0x18; - register8_t reserved_0x19; - register8_t reserved_0x1A; - register8_t reserved_0x1B; - register8_t reserved_0x1C; - register8_t reserved_0x1D; - register8_t reserved_0x1E; - register8_t reserved_0x1F; - register8_t reserved_0x20; - register8_t reserved_0x21; - register8_t reserved_0x22; - register8_t reserved_0x23; - register8_t reserved_0x24; - register8_t reserved_0x25; - register8_t reserved_0x26; - register8_t reserved_0x27; - register8_t reserved_0x28; - register8_t reserved_0x29; - register8_t reserved_0x2A; - register8_t reserved_0x2B; - register8_t reserved_0x2C; - register8_t reserved_0x2D; - register8_t reserved_0x2E; - register8_t reserved_0x2F; - register8_t reserved_0x30; - register8_t reserved_0x31; - register8_t reserved_0x32; - register8_t reserved_0x33; - register8_t reserved_0x34; - register8_t reserved_0x35; - register8_t reserved_0x36; - register8_t reserved_0x37; - register8_t reserved_0x38; - register8_t reserved_0x39; - register8_t CAL0; /* Calibration Byte 0 */ - register8_t CAL1; /* Calibration Byte 1 */ -} USB_t; - - -/* USB Endpoint Table */ -typedef struct USB_EP_TABLE_struct -{ - USB_EP_t EP0OUT; /* Endpoint 0 */ - USB_EP_t EP0IN; /* Endpoint 0 */ - USB_EP_t EP1OUT; /* Endpoint 1 */ - USB_EP_t EP1IN; /* Endpoint 1 */ - USB_EP_t EP2OUT; /* Endpoint 2 */ - USB_EP_t EP2IN; /* Endpoint 2 */ - USB_EP_t EP3OUT; /* Endpoint 3 */ - USB_EP_t EP3IN; /* Endpoint 3 */ - USB_EP_t EP4OUT; /* Endpoint 4 */ - USB_EP_t EP4IN; /* Endpoint 4 */ - USB_EP_t EP5OUT; /* Endpoint 5 */ - USB_EP_t EP5IN; /* Endpoint 5 */ - USB_EP_t EP6OUT; /* Endpoint 6 */ - USB_EP_t EP6IN; /* Endpoint 6 */ - USB_EP_t EP7OUT; /* Endpoint 7 */ - USB_EP_t EP7IN; /* Endpoint 7 */ - USB_EP_t EP8OUT; /* Endpoint 8 */ - USB_EP_t EP8IN; /* Endpoint 8 */ - USB_EP_t EP9OUT; /* Endpoint 9 */ - USB_EP_t EP9IN; /* Endpoint 9 */ - USB_EP_t EP10OUT; /* Endpoint 10 */ - USB_EP_t EP10IN; /* Endpoint 10 */ - USB_EP_t EP11OUT; /* Endpoint 11 */ - USB_EP_t EP11IN; /* Endpoint 11 */ - USB_EP_t EP12OUT; /* Endpoint 12 */ - USB_EP_t EP12IN; /* Endpoint 12 */ - USB_EP_t EP13OUT; /* Endpoint 13 */ - USB_EP_t EP13IN; /* Endpoint 13 */ - USB_EP_t EP14OUT; /* Endpoint 14 */ - USB_EP_t EP14IN; /* Endpoint 14 */ - USB_EP_t EP15OUT; /* Endpoint 15 */ - USB_EP_t EP15IN; /* Endpoint 15 */ - register8_t reserved_0x100; - register8_t reserved_0x101; - register8_t reserved_0x102; - register8_t reserved_0x103; - register8_t reserved_0x104; - register8_t reserved_0x105; - register8_t reserved_0x106; - register8_t reserved_0x107; - register8_t reserved_0x108; - register8_t reserved_0x109; - register8_t reserved_0x10A; - register8_t reserved_0x10B; - register8_t reserved_0x10C; - register8_t reserved_0x10D; - register8_t reserved_0x10E; - register8_t reserved_0x10F; - register8_t FRAMENUML; /* Frame Number Low Byte */ - register8_t FRAMENUMH; /* Frame Number High Byte */ -} USB_EP_TABLE_t; - -/* Interrupt level */ -typedef enum USB_INTLVL_enum -{ - USB_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ - USB_INTLVL_LO_gc = (0x01<<0), /* Low level */ - USB_INTLVL_MED_gc = (0x02<<0), /* Medium level */ - USB_INTLVL_HI_gc = (0x03<<0), /* High level */ -} USB_INTLVL_t; - -/* USB Endpoint Type */ -typedef enum USB_EP_TYPE_enum -{ - USB_EP_TYPE_DISABLE_gc = (0x00<<6), /* Endpoint Disabled */ - USB_EP_TYPE_CONTROL_gc = (0x01<<6), /* Control */ - USB_EP_TYPE_BULK_gc = (0x02<<6), /* Bulk/Interrupt */ - USB_EP_TYPE_ISOCHRONOUS_gc = (0x03<<6), /* Isochronous */ -} USB_EP_TYPE_t; - -/* USB Endpoint Buffersize */ -typedef enum USB_EP_BUFSIZE_enum -{ - USB_EP_BUFSIZE_8_gc = (0x00<<0), /* 8 bytes buffer size */ - USB_EP_BUFSIZE_16_gc = (0x01<<0), /* 16 bytes buffer size */ - USB_EP_BUFSIZE_32_gc = (0x02<<0), /* 32 bytes buffer size */ - USB_EP_BUFSIZE_64_gc = (0x03<<0), /* 64 bytes buffer size */ - USB_EP_BUFSIZE_128_gc = (0x04<<0), /* 128 bytes buffer size */ - USB_EP_BUFSIZE_256_gc = (0x05<<0), /* 256 bytes buffer size */ - USB_EP_BUFSIZE_512_gc = (0x06<<0), /* 512 bytes buffer size */ - USB_EP_BUFSIZE_1023_gc = (0x07<<0), /* 1023 bytes buffer size */ -} USB_EP_BUFSIZE_t; - - -/* --------------------------------------------------------------------------- -PORT - I/O Port Configuration --------------------------------------------------------------------------- -*/ - -/* I/O Ports */ -typedef struct PORT_struct -{ - register8_t DIR; /* I/O Port Data Direction */ - register8_t DIRSET; /* I/O Port Data Direction Set */ - register8_t DIRCLR; /* I/O Port Data Direction Clear */ - register8_t DIRTGL; /* I/O Port Data Direction Toggle */ - register8_t OUT; /* I/O Port Output */ - register8_t OUTSET; /* I/O Port Output Set */ - register8_t OUTCLR; /* I/O Port Output Clear */ - register8_t OUTTGL; /* I/O Port Output Toggle */ - register8_t IN; /* I/O port Input */ - register8_t INTCTRL; /* Interrupt Control Register */ - register8_t INT0MASK; /* Port Interrupt 0 Mask */ - register8_t INT1MASK; /* Port Interrupt 1 Mask */ - register8_t INTFLAGS; /* Interrupt Flag Register */ - register8_t reserved_0x0D; - register8_t REMAP; /* I/O Port Pin Remap Register */ - register8_t reserved_0x0F; - register8_t PIN0CTRL; /* Pin 0 Control Register */ - register8_t PIN1CTRL; /* Pin 1 Control Register */ - register8_t PIN2CTRL; /* Pin 2 Control Register */ - register8_t PIN3CTRL; /* Pin 3 Control Register */ - register8_t PIN4CTRL; /* Pin 4 Control Register */ - register8_t PIN5CTRL; /* Pin 5 Control Register */ - register8_t PIN6CTRL; /* Pin 6 Control Register */ - register8_t PIN7CTRL; /* Pin 7 Control Register */ -} PORT_t; - -/* Port Interrupt 0 Level */ -typedef enum PORT_INT0LVL_enum -{ - PORT_INT0LVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - PORT_INT0LVL_LO_gc = (0x01<<0), /* Low Level */ - PORT_INT0LVL_MED_gc = (0x02<<0), /* Medium Level */ - PORT_INT0LVL_HI_gc = (0x03<<0), /* High Level */ -} PORT_INT0LVL_t; - -/* Port Interrupt 1 Level */ -typedef enum PORT_INT1LVL_enum -{ - PORT_INT1LVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ - PORT_INT1LVL_LO_gc = (0x01<<2), /* Low Level */ - PORT_INT1LVL_MED_gc = (0x02<<2), /* Medium Level */ - PORT_INT1LVL_HI_gc = (0x03<<2), /* High Level */ -} PORT_INT1LVL_t; - -/* Output/Pull Configuration */ -typedef enum PORT_OPC_enum -{ - PORT_OPC_TOTEM_gc = (0x00<<3), /* Totempole */ - PORT_OPC_BUSKEEPER_gc = (0x01<<3), /* Totempole w/ Bus keeper on Input and Output */ - PORT_OPC_PULLDOWN_gc = (0x02<<3), /* Totempole w/ Pull-down on Input */ - PORT_OPC_PULLUP_gc = (0x03<<3), /* Totempole w/ Pull-up on Input */ - PORT_OPC_WIREDOR_gc = (0x04<<3), /* Wired OR */ - PORT_OPC_WIREDAND_gc = (0x05<<3), /* Wired AND */ - PORT_OPC_WIREDORPULL_gc = (0x06<<3), /* Wired OR w/ Pull-down */ - PORT_OPC_WIREDANDPULL_gc = (0x07<<3), /* Wired AND w/ Pull-up */ -} PORT_OPC_t; - -/* Input/Sense Configuration */ -typedef enum PORT_ISC_enum -{ - PORT_ISC_BOTHEDGES_gc = (0x00<<0), /* Sense Both Edges */ - PORT_ISC_RISING_gc = (0x01<<0), /* Sense Rising Edge */ - PORT_ISC_FALLING_gc = (0x02<<0), /* Sense Falling Edge */ - PORT_ISC_LEVEL_gc = (0x03<<0), /* Sense Level (Transparent For Events) */ - PORT_ISC_INPUT_DISABLE_gc = (0x07<<0), /* Disable Digital Input Buffer */ -} PORT_ISC_t; - - -/* --------------------------------------------------------------------------- -TC - 16-bit Timer/Counter With PWM --------------------------------------------------------------------------- -*/ - -/* 16-bit Timer/Counter 0 */ -typedef struct TC0_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t CTRLC; /* Control register C */ - register8_t CTRLD; /* Control Register D */ - register8_t CTRLE; /* Control Register E */ - register8_t reserved_0x05; - register8_t INTCTRLA; /* Interrupt Control Register A */ - register8_t INTCTRLB; /* Interrupt Control Register B */ - register8_t CTRLFCLR; /* Control Register F Clear */ - register8_t CTRLFSET; /* Control Register F Set */ - register8_t CTRLGCLR; /* Control Register G Clear */ - register8_t CTRLGSET; /* Control Register G Set */ - register8_t INTFLAGS; /* Interrupt Flag Register */ - register8_t reserved_0x0D; - register8_t reserved_0x0E; - register8_t TEMP; /* Temporary Register For 16-bit Access */ - register8_t reserved_0x10; - register8_t reserved_0x11; - register8_t reserved_0x12; - register8_t reserved_0x13; - register8_t reserved_0x14; - register8_t reserved_0x15; - register8_t reserved_0x16; - register8_t reserved_0x17; - register8_t reserved_0x18; - register8_t reserved_0x19; - register8_t reserved_0x1A; - register8_t reserved_0x1B; - register8_t reserved_0x1C; - register8_t reserved_0x1D; - register8_t reserved_0x1E; - register8_t reserved_0x1F; - _WORDREGISTER(CNT); /* Count */ - register8_t reserved_0x22; - register8_t reserved_0x23; - register8_t reserved_0x24; - register8_t reserved_0x25; - _WORDREGISTER(PER); /* Period */ - _WORDREGISTER(CCA); /* Compare or Capture A */ - _WORDREGISTER(CCB); /* Compare or Capture B */ - _WORDREGISTER(CCC); /* Compare or Capture C */ - _WORDREGISTER(CCD); /* Compare or Capture D */ - register8_t reserved_0x30; - register8_t reserved_0x31; - register8_t reserved_0x32; - register8_t reserved_0x33; - register8_t reserved_0x34; - register8_t reserved_0x35; - _WORDREGISTER(PERBUF); /* Period Buffer */ - _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ - _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ - _WORDREGISTER(CCCBUF); /* Compare Or Capture C Buffer */ - _WORDREGISTER(CCDBUF); /* Compare Or Capture D Buffer */ -} TC0_t; - - -/* 16-bit Timer/Counter 1 */ -typedef struct TC1_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t CTRLC; /* Control register C */ - register8_t CTRLD; /* Control Register D */ - register8_t CTRLE; /* Control Register E */ - register8_t reserved_0x05; - register8_t INTCTRLA; /* Interrupt Control Register A */ - register8_t INTCTRLB; /* Interrupt Control Register B */ - register8_t CTRLFCLR; /* Control Register F Clear */ - register8_t CTRLFSET; /* Control Register F Set */ - register8_t CTRLGCLR; /* Control Register G Clear */ - register8_t CTRLGSET; /* Control Register G Set */ - register8_t INTFLAGS; /* Interrupt Flag Register */ - register8_t reserved_0x0D; - register8_t reserved_0x0E; - register8_t TEMP; /* Temporary Register For 16-bit Access */ - register8_t reserved_0x10; - register8_t reserved_0x11; - register8_t reserved_0x12; - register8_t reserved_0x13; - register8_t reserved_0x14; - register8_t reserved_0x15; - register8_t reserved_0x16; - register8_t reserved_0x17; - register8_t reserved_0x18; - register8_t reserved_0x19; - register8_t reserved_0x1A; - register8_t reserved_0x1B; - register8_t reserved_0x1C; - register8_t reserved_0x1D; - register8_t reserved_0x1E; - register8_t reserved_0x1F; - _WORDREGISTER(CNT); /* Count */ - register8_t reserved_0x22; - register8_t reserved_0x23; - register8_t reserved_0x24; - register8_t reserved_0x25; - _WORDREGISTER(PER); /* Period */ - _WORDREGISTER(CCA); /* Compare or Capture A */ - _WORDREGISTER(CCB); /* Compare or Capture B */ - register8_t reserved_0x2C; - register8_t reserved_0x2D; - register8_t reserved_0x2E; - register8_t reserved_0x2F; - register8_t reserved_0x30; - register8_t reserved_0x31; - register8_t reserved_0x32; - register8_t reserved_0x33; - register8_t reserved_0x34; - register8_t reserved_0x35; - _WORDREGISTER(PERBUF); /* Period Buffer */ - _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ - _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ -} TC1_t; - -/* Clock Selection */ -typedef enum TC_CLKSEL_enum -{ - TC_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */ - TC_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */ - TC_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */ - TC_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */ - TC_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */ - TC_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */ - TC_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */ - TC_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */ - TC_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */ - TC_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */ - TC_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */ - TC_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */ -} TC_CLKSEL_t; - -/* Waveform Generation Mode */ -typedef enum TC_WGMODE_enum -{ - TC_WGMODE_NORMAL_gc = (0x00<<0), /* Normal Mode */ - TC_WGMODE_FRQ_gc = (0x01<<0), /* Frequency Generation Mode */ - TC_WGMODE_SINGLESLOPE_gc = (0x03<<0), /* Single Slope */ - TC_WGMODE_SS_gc = (0x03<<0), /* Single Slope */ - TC_WGMODE_DSTOP_gc = (0x05<<0), /* Dual Slope, Update on TOP */ - TC_WGMODE_DS_T_gc = (0x05<<0), /* Dual Slope, Update on TOP */ - TC_WGMODE_DSBOTH_gc = (0x06<<0), /* Dual Slope, Update on both TOP and BOTTOM */ - TC_WGMODE_DS_TB_gc = (0x06<<0), /* Dual Slope, Update on both TOP and BOTTOM */ - TC_WGMODE_DSBOTTOM_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */ - TC_WGMODE_DS_B_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */ -} TC_WGMODE_t; - -/* Byte Mode */ -typedef enum TC_BYTEM_enum -{ - TC_BYTEM_NORMAL_gc = (0x00<<0), /* 16-bit mode */ - TC_BYTEM_BYTEMODE_gc = (0x01<<0), /* Timer/Counter operating in byte mode only */ - TC_BYTEM_SPLITMODE_gc = (0x02<<0), /* Timer/Counter split into two 8-bit Counters (TC2) */ -} TC_BYTEM_t; - -/* Event Action */ -typedef enum TC_EVACT_enum -{ - TC_EVACT_OFF_gc = (0x00<<5), /* No Event Action */ - TC_EVACT_CAPT_gc = (0x01<<5), /* Input Capture */ - TC_EVACT_UPDOWN_gc = (0x02<<5), /* Externally Controlled Up/Down Count */ - TC_EVACT_QDEC_gc = (0x03<<5), /* Quadrature Decode */ - TC_EVACT_RESTART_gc = (0x04<<5), /* Restart */ - TC_EVACT_FRQ_gc = (0x05<<5), /* Frequency Capture */ - TC_EVACT_PW_gc = (0x06<<5), /* Pulse-width Capture */ -} TC_EVACT_t; - -/* Event Selection */ -typedef enum TC_EVSEL_enum -{ - TC_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ - TC_EVSEL_CH0_gc = (0x08<<0), /* Event Channel 0 */ - TC_EVSEL_CH1_gc = (0x09<<0), /* Event Channel 1 */ - TC_EVSEL_CH2_gc = (0x0A<<0), /* Event Channel 2 */ - TC_EVSEL_CH3_gc = (0x0B<<0), /* Event Channel 3 */ -} TC_EVSEL_t; - -/* Error Interrupt Level */ -typedef enum TC_ERRINTLVL_enum -{ - TC_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ - TC_ERRINTLVL_LO_gc = (0x01<<2), /* Low Level */ - TC_ERRINTLVL_MED_gc = (0x02<<2), /* Medium Level */ - TC_ERRINTLVL_HI_gc = (0x03<<2), /* High Level */ -} TC_ERRINTLVL_t; - -/* Overflow Interrupt Level */ -typedef enum TC_OVFINTLVL_enum -{ - TC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - TC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ - TC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ - TC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ -} TC_OVFINTLVL_t; - -/* Compare or Capture D Interrupt Level */ -typedef enum TC_CCDINTLVL_enum -{ - TC_CCDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ - TC_CCDINTLVL_LO_gc = (0x01<<6), /* Low Level */ - TC_CCDINTLVL_MED_gc = (0x02<<6), /* Medium Level */ - TC_CCDINTLVL_HI_gc = (0x03<<6), /* High Level */ -} TC_CCDINTLVL_t; - -/* Compare or Capture C Interrupt Level */ -typedef enum TC_CCCINTLVL_enum -{ - TC_CCCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ - TC_CCCINTLVL_LO_gc = (0x01<<4), /* Low Level */ - TC_CCCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ - TC_CCCINTLVL_HI_gc = (0x03<<4), /* High Level */ -} TC_CCCINTLVL_t; - -/* Compare or Capture B Interrupt Level */ -typedef enum TC_CCBINTLVL_enum -{ - TC_CCBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ - TC_CCBINTLVL_LO_gc = (0x01<<2), /* Low Level */ - TC_CCBINTLVL_MED_gc = (0x02<<2), /* Medium Level */ - TC_CCBINTLVL_HI_gc = (0x03<<2), /* High Level */ -} TC_CCBINTLVL_t; - -/* Compare or Capture A Interrupt Level */ -typedef enum TC_CCAINTLVL_enum -{ - TC_CCAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - TC_CCAINTLVL_LO_gc = (0x01<<0), /* Low Level */ - TC_CCAINTLVL_MED_gc = (0x02<<0), /* Medium Level */ - TC_CCAINTLVL_HI_gc = (0x03<<0), /* High Level */ -} TC_CCAINTLVL_t; - -/* Timer/Counter Command */ -typedef enum TC_CMD_enum -{ - TC_CMD_NONE_gc = (0x00<<2), /* No Command */ - TC_CMD_UPDATE_gc = (0x01<<2), /* Force Update */ - TC_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ - TC_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ -} TC_CMD_t; - - -/* --------------------------------------------------------------------------- -TC2 - 16-bit Timer/Counter type 2 --------------------------------------------------------------------------- -*/ - -/* 16-bit Timer/Counter type 2 */ -typedef struct TC2_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t CTRLC; /* Control register C */ - register8_t reserved_0x03; - register8_t CTRLE; /* Control Register E */ - register8_t reserved_0x05; - register8_t INTCTRLA; /* Interrupt Control Register A */ - register8_t INTCTRLB; /* Interrupt Control Register B */ - register8_t reserved_0x08; - register8_t CTRLF; /* Control Register F */ - register8_t reserved_0x0A; - register8_t reserved_0x0B; - register8_t INTFLAGS; /* Interrupt Flag Register */ - register8_t reserved_0x0D; - register8_t reserved_0x0E; - register8_t reserved_0x0F; - register8_t reserved_0x10; - register8_t reserved_0x11; - register8_t reserved_0x12; - register8_t reserved_0x13; - register8_t reserved_0x14; - register8_t reserved_0x15; - register8_t reserved_0x16; - register8_t reserved_0x17; - register8_t reserved_0x18; - register8_t reserved_0x19; - register8_t reserved_0x1A; - register8_t reserved_0x1B; - register8_t reserved_0x1C; - register8_t reserved_0x1D; - register8_t reserved_0x1E; - register8_t reserved_0x1F; - register8_t LCNT; /* Low Byte Count */ - register8_t HCNT; /* High Byte Count */ - register8_t reserved_0x22; - register8_t reserved_0x23; - register8_t reserved_0x24; - register8_t reserved_0x25; - register8_t LPER; /* Low Byte Period */ - register8_t HPER; /* High Byte Period */ - register8_t LCMPA; /* Low Byte Compare A */ - register8_t HCMPA; /* High Byte Compare A */ - register8_t LCMPB; /* Low Byte Compare B */ - register8_t HCMPB; /* High Byte Compare B */ - register8_t LCMPC; /* Low Byte Compare C */ - register8_t HCMPC; /* High Byte Compare C */ - register8_t LCMPD; /* Low Byte Compare D */ - register8_t HCMPD; /* High Byte Compare D */ -} TC2_t; - -/* Clock Selection */ -typedef enum TC2_CLKSEL_enum -{ - TC2_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */ - TC2_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */ - TC2_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */ - TC2_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */ - TC2_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */ - TC2_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */ - TC2_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */ - TC2_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */ - TC2_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */ - TC2_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */ - TC2_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */ - TC2_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */ -} TC2_CLKSEL_t; - -/* Byte Mode */ -typedef enum TC2_BYTEM_enum -{ - TC2_BYTEM_NORMAL_gc = (0x00<<0), /* 16-bit mode */ - TC2_BYTEM_BYTEMODE_gc = (0x01<<0), /* Timer/Counter operating in byte mode only (TC2) */ - TC2_BYTEM_SPLITMODE_gc = (0x02<<0), /* Timer/Counter split into two 8-bit Counters */ -} TC2_BYTEM_t; - -/* High Byte Underflow Interrupt Level */ -typedef enum TC2_HUNFINTLVL_enum -{ - TC2_HUNFINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ - TC2_HUNFINTLVL_LO_gc = (0x01<<2), /* Low Level */ - TC2_HUNFINTLVL_MED_gc = (0x02<<2), /* Medium Level */ - TC2_HUNFINTLVL_HI_gc = (0x03<<2), /* High Level */ -} TC2_HUNFINTLVL_t; - -/* Low Byte Underflow Interrupt Level */ -typedef enum TC2_LUNFINTLVL_enum -{ - TC2_LUNFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - TC2_LUNFINTLVL_LO_gc = (0x01<<0), /* Low Level */ - TC2_LUNFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ - TC2_LUNFINTLVL_HI_gc = (0x03<<0), /* High Level */ -} TC2_LUNFINTLVL_t; - -/* Low Byte Compare D Interrupt Level */ -typedef enum TC2_LCMPDINTLVL_enum -{ - TC2_LCMPDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ - TC2_LCMPDINTLVL_LO_gc = (0x01<<6), /* Low Level */ - TC2_LCMPDINTLVL_MED_gc = (0x02<<6), /* Medium Level */ - TC2_LCMPDINTLVL_HI_gc = (0x03<<6), /* High Level */ -} TC2_LCMPDINTLVL_t; - -/* Low Byte Compare C Interrupt Level */ -typedef enum TC2_LCMPCINTLVL_enum -{ - TC2_LCMPCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ - TC2_LCMPCINTLVL_LO_gc = (0x01<<4), /* Low Level */ - TC2_LCMPCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ - TC2_LCMPCINTLVL_HI_gc = (0x03<<4), /* High Level */ -} TC2_LCMPCINTLVL_t; - -/* Low Byte Compare B Interrupt Level */ -typedef enum TC2_LCMPBINTLVL_enum -{ - TC2_LCMPBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ - TC2_LCMPBINTLVL_LO_gc = (0x01<<2), /* Low Level */ - TC2_LCMPBINTLVL_MED_gc = (0x02<<2), /* Medium Level */ - TC2_LCMPBINTLVL_HI_gc = (0x03<<2), /* High Level */ -} TC2_LCMPBINTLVL_t; - -/* Low Byte Compare A Interrupt Level */ -typedef enum TC2_LCMPAINTLVL_enum -{ - TC2_LCMPAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - TC2_LCMPAINTLVL_LO_gc = (0x01<<0), /* Low Level */ - TC2_LCMPAINTLVL_MED_gc = (0x02<<0), /* Medium Level */ - TC2_LCMPAINTLVL_HI_gc = (0x03<<0), /* High Level */ -} TC2_LCMPAINTLVL_t; - -/* Timer/Counter Command */ -typedef enum TC2_CMD_enum -{ - TC2_CMD_NONE_gc = (0x00<<2), /* No Command */ - TC2_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ - TC2_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ -} TC2_CMD_t; - -/* Timer/Counter Command */ -typedef enum TC2_CMDEN_enum -{ - TC2_CMDEN_LOW_gc = (0x01<<0), /* Low Byte Timer/Counter */ - TC2_CMDEN_HIGH_gc = (0x02<<0), /* High Byte Timer/Counter */ - TC2_CMDEN_BOTH_gc = (0x03<<0), /* Both Low Byte and High Byte Timer/Counters */ -} TC2_CMDEN_t; - - -/* --------------------------------------------------------------------------- -AWEX - Timer/Counter Advanced Waveform Extension --------------------------------------------------------------------------- -*/ - -/* Advanced Waveform Extension */ -typedef struct AWEX_struct -{ - register8_t CTRL; /* Control Register */ - register8_t reserved_0x01; - register8_t FDEMASK; /* Fault Detection Event Mask */ - register8_t FDCTRL; /* Fault Detection Control Register */ - register8_t STATUS; /* Status Register */ - register8_t STATUSSET; /* Status Set Register */ - register8_t DTBOTH; /* Dead Time Both Sides */ - register8_t DTBOTHBUF; /* Dead Time Both Sides Buffer */ - register8_t DTLS; /* Dead Time Low Side */ - register8_t DTHS; /* Dead Time High Side */ - register8_t DTLSBUF; /* Dead Time Low Side Buffer */ - register8_t DTHSBUF; /* Dead Time High Side Buffer */ - register8_t OUTOVEN; /* Output Override Enable */ -} AWEX_t; - -/* Fault Detect Action */ -typedef enum AWEX_FDACT_enum -{ - AWEX_FDACT_NONE_gc = (0x00<<0), /* No Fault Protection */ - AWEX_FDACT_CLEAROE_gc = (0x01<<0), /* Clear Output Enable Bits */ - AWEX_FDACT_CLEARDIR_gc = (0x03<<0), /* Clear I/O Port Direction Bits */ -} AWEX_FDACT_t; - - -/* --------------------------------------------------------------------------- -HIRES - Timer/Counter High-Resolution Extension --------------------------------------------------------------------------- -*/ - -/* High-Resolution Extension */ -typedef struct HIRES_struct -{ - register8_t CTRLA; /* Control Register */ -} HIRES_t; - -/* High Resolution Enable */ -typedef enum HIRES_HREN_enum -{ - HIRES_HREN_NONE_gc = (0x00<<0), /* No Fault Protection */ - HIRES_HREN_TC0_gc = (0x01<<0), /* Enable High Resolution on Timer/Counter 0 */ - HIRES_HREN_TC1_gc = (0x02<<0), /* Enable High Resolution on Timer/Counter 1 */ - HIRES_HREN_BOTH_gc = (0x03<<0), /* Enable High Resolution both Timer/Counters */ -} HIRES_HREN_t; - - -/* --------------------------------------------------------------------------- -USART - Universal Asynchronous Receiver-Transmitter --------------------------------------------------------------------------- -*/ - -/* Universal Synchronous/Asynchronous Receiver/Transmitter */ -typedef struct USART_struct -{ - register8_t DATA; /* Data Register */ - register8_t STATUS; /* Status Register */ - register8_t reserved_0x02; - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t CTRLC; /* Control Register C */ - register8_t BAUDCTRLA; /* Baud Rate Control Register A */ - register8_t BAUDCTRLB; /* Baud Rate Control Register B */ -} USART_t; - -/* Receive Complete Interrupt level */ -typedef enum USART_RXCINTLVL_enum -{ - USART_RXCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ - USART_RXCINTLVL_LO_gc = (0x01<<4), /* Low Level */ - USART_RXCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ - USART_RXCINTLVL_HI_gc = (0x03<<4), /* High Level */ -} USART_RXCINTLVL_t; - -/* Transmit Complete Interrupt level */ -typedef enum USART_TXCINTLVL_enum -{ - USART_TXCINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ - USART_TXCINTLVL_LO_gc = (0x01<<2), /* Low Level */ - USART_TXCINTLVL_MED_gc = (0x02<<2), /* Medium Level */ - USART_TXCINTLVL_HI_gc = (0x03<<2), /* High Level */ -} USART_TXCINTLVL_t; - -/* Data Register Empty Interrupt level */ -typedef enum USART_DREINTLVL_enum -{ - USART_DREINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - USART_DREINTLVL_LO_gc = (0x01<<0), /* Low Level */ - USART_DREINTLVL_MED_gc = (0x02<<0), /* Medium Level */ - USART_DREINTLVL_HI_gc = (0x03<<0), /* High Level */ -} USART_DREINTLVL_t; - -/* Character Size */ -typedef enum USART_CHSIZE_enum -{ - USART_CHSIZE_5BIT_gc = (0x00<<0), /* Character size: 5 bit */ - USART_CHSIZE_6BIT_gc = (0x01<<0), /* Character size: 6 bit */ - USART_CHSIZE_7BIT_gc = (0x02<<0), /* Character size: 7 bit */ - USART_CHSIZE_8BIT_gc = (0x03<<0), /* Character size: 8 bit */ - USART_CHSIZE_9BIT_gc = (0x07<<0), /* Character size: 9 bit */ -} USART_CHSIZE_t; - -/* Communication Mode */ -typedef enum USART_CMODE_enum -{ - USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6), /* Asynchronous Mode */ - USART_CMODE_SYNCHRONOUS_gc = (0x01<<6), /* Synchronous Mode */ - USART_CMODE_IRDA_gc = (0x02<<6), /* IrDA Mode */ - USART_CMODE_MSPI_gc = (0x03<<6), /* Master SPI Mode */ -} USART_CMODE_t; - -/* Parity Mode */ -typedef enum USART_PMODE_enum -{ - USART_PMODE_DISABLED_gc = (0x00<<4), /* No Parity */ - USART_PMODE_EVEN_gc = (0x02<<4), /* Even Parity */ - USART_PMODE_ODD_gc = (0x03<<4), /* Odd Parity */ -} USART_PMODE_t; - - -/* --------------------------------------------------------------------------- -SPI - Serial Peripheral Interface --------------------------------------------------------------------------- -*/ - -/* Serial Peripheral Interface */ -typedef struct SPI_struct -{ - register8_t CTRL; /* Control Register */ - register8_t INTCTRL; /* Interrupt Control Register */ - register8_t STATUS; /* Status Register */ - register8_t DATA; /* Data Register */ -} SPI_t; - -/* SPI Mode */ -typedef enum SPI_MODE_enum -{ - SPI_MODE_0_gc = (0x00<<2), /* SPI Mode 0 */ - SPI_MODE_1_gc = (0x01<<2), /* SPI Mode 1 */ - SPI_MODE_2_gc = (0x02<<2), /* SPI Mode 2 */ - SPI_MODE_3_gc = (0x03<<2), /* SPI Mode 3 */ -} SPI_MODE_t; - -/* Prescaler setting */ -typedef enum SPI_PRESCALER_enum -{ - SPI_PRESCALER_DIV4_gc = (0x00<<0), /* System Clock / 4 */ - SPI_PRESCALER_DIV16_gc = (0x01<<0), /* System Clock / 16 */ - SPI_PRESCALER_DIV64_gc = (0x02<<0), /* System Clock / 64 */ - SPI_PRESCALER_DIV128_gc = (0x03<<0), /* System Clock / 128 */ -} SPI_PRESCALER_t; - -/* Interrupt level */ -typedef enum SPI_INTLVL_enum -{ - SPI_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - SPI_INTLVL_LO_gc = (0x01<<0), /* Low Level */ - SPI_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ - SPI_INTLVL_HI_gc = (0x03<<0), /* High Level */ -} SPI_INTLVL_t; - - -/* --------------------------------------------------------------------------- -IRCOM - IR Communication Module --------------------------------------------------------------------------- -*/ - -/* IR Communication Module */ -typedef struct IRCOM_struct -{ - register8_t CTRL; /* Control Register */ - register8_t TXPLCTRL; /* IrDA Transmitter Pulse Length Control Register */ - register8_t RXPLCTRL; /* IrDA Receiver Pulse Length Control Register */ -} IRCOM_t; - -/* Event channel selection */ -typedef enum IRDA_EVSEL_enum -{ - IRDA_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ - IRDA_EVSEL_0_gc = (0x08<<0), /* Event Channel 0 */ - IRDA_EVSEL_1_gc = (0x09<<0), /* Event Channel 1 */ - IRDA_EVSEL_2_gc = (0x0A<<0), /* Event Channel 2 */ - IRDA_EVSEL_3_gc = (0x0B<<0), /* Event Channel 3 */ -} IRDA_EVSEL_t; - - -/* --------------------------------------------------------------------------- -FUSE - Fuses and Lockbits --------------------------------------------------------------------------- -*/ - -/* Fuses */ -typedef struct NVM_FUSES_struct -{ - register8_t reserved_0x00; - register8_t FUSEBYTE1; /* Watchdog Configuration */ - register8_t FUSEBYTE2; /* Reset Configuration */ - register8_t reserved_0x03; - register8_t FUSEBYTE4; /* Start-up Configuration */ - register8_t FUSEBYTE5; /* EESAVE and BOD Level */ -} NVM_FUSES_t; - -/* Boot Loader Section Reset Vector */ -typedef enum BOOTRST_enum -{ - BOOTRST_BOOTLDR_gc = (0x00<<6), /* Boot Loader Reset */ - BOOTRST_APPLICATION_gc = (0x01<<6), /* Application Reset */ -} BOOTRST_t; - -/* Timer Oscillator pin location */ -typedef enum TOSCSEL_enum -{ - TOSCSEL_ALTERNATE_gc = (0x00<<5), /* TOSC1 / TOSC2 on separate pins */ - TOSCSEL_XTAL_gc = (0x01<<5), /* TOSC1 / TOSC2 shared with XTAL1 / XTAL2 */ -} TOSCSEL_t; - -/* BOD operation */ -typedef enum BOD_enum -{ - BOD_SAMPLED_gc = (0x01<<0), /* BOD enabled in sampled mode */ - BOD_CONTINUOUS_gc = (0x02<<0), /* BOD enabled continuously */ - BOD_DISABLED_gc = (0x03<<0), /* BOD Disabled */ -} BOD_t; - -/* BOD operation */ -typedef enum BODACT_enum -{ - BODACT_SAMPLED_gc = (0x01<<4), /* BOD enabled in sampled mode */ - BODACT_CONTINUOUS_gc = (0x02<<4), /* BOD enabled continuously */ - BODACT_DISABLED_gc = (0x03<<4), /* BOD Disabled */ -} BODACT_t; - -/* Watchdog (Window) Timeout Period */ -typedef enum WD_enum -{ - WD_8CLK_gc = (0x00<<4), /* 8 cycles (8ms @ 3.3V) */ - WD_16CLK_gc = (0x01<<4), /* 16 cycles (16ms @ 3.3V) */ - WD_32CLK_gc = (0x02<<4), /* 32 cycles (32ms @ 3.3V) */ - WD_64CLK_gc = (0x03<<4), /* 64 cycles (64ms @ 3.3V) */ - WD_128CLK_gc = (0x04<<4), /* 128 cycles (0.125s @ 3.3V) */ - WD_256CLK_gc = (0x05<<4), /* 256 cycles (0.25s @ 3.3V) */ - WD_512CLK_gc = (0x06<<4), /* 512 cycles (0.5s @ 3.3V) */ - WD_1KCLK_gc = (0x07<<4), /* 1K cycles (1s @ 3.3V) */ - WD_2KCLK_gc = (0x08<<4), /* 2K cycles (2s @ 3.3V) */ - WD_4KCLK_gc = (0x09<<4), /* 4K cycles (4s @ 3.3V) */ - WD_8KCLK_gc = (0x0A<<4), /* 8K cycles (8s @ 3.3V) */ -} WD_t; - -/* Watchdog (Window) Timeout Period */ -typedef enum WDP_enum -{ - WDP_8CLK_gc = (0x00<<0), /* 8 cycles (8ms @ 3.3V) */ - WDP_16CLK_gc = (0x01<<0), /* 16 cycles (16ms @ 3.3V) */ - WDP_32CLK_gc = (0x02<<0), /* 32 cycles (32ms @ 3.3V) */ - WDP_64CLK_gc = (0x03<<0), /* 64 cycles (64ms @ 3.3V) */ - WDP_128CLK_gc = (0x04<<0), /* 128 cycles (0.125s @ 3.3V) */ - WDP_256CLK_gc = (0x05<<0), /* 256 cycles (0.25s @ 3.3V) */ - WDP_512CLK_gc = (0x06<<0), /* 512 cycles (0.5s @ 3.3V) */ - WDP_1KCLK_gc = (0x07<<0), /* 1K cycles (1s @ 3.3V) */ - WDP_2KCLK_gc = (0x08<<0), /* 2K cycles (2s @ 3.3V) */ - WDP_4KCLK_gc = (0x09<<0), /* 4K cycles (4s @ 3.3V) */ - WDP_8KCLK_gc = (0x0A<<0), /* 8K cycles (8s @ 3.3V) */ -} WDP_t; - -/* Start-up Time */ -typedef enum SUT_enum -{ - SUT_0MS_gc = (0x03<<2), /* 0 ms */ - SUT_4MS_gc = (0x01<<2), /* 4 ms */ - SUT_64MS_gc = (0x00<<2), /* 64 ms */ -} SUT_t; - -/* Brownout Detection Voltage Level */ -typedef enum BODLVL_enum -{ - BODLVL_1V6_gc = (0x07<<0), /* 1.6 V */ - BODLVL_1V8_gc = (0x06<<0), /* 1.8 V */ - BODLVL_2V0_gc = (0x05<<0), /* 2.0 V */ - BODLVL_2V2_gc = (0x04<<0), /* 2.2 V */ - BODLVL_2V4_gc = (0x03<<0), /* 2.4 V */ - BODLVL_2V6_gc = (0x02<<0), /* 2.6 V */ - BODLVL_2V8_gc = (0x01<<0), /* 2.8 V */ - BODLVL_3V0_gc = (0x00<<0), /* 3.0 V */ -} BODLVL_t; - - -/* --------------------------------------------------------------------------- -LOCKBIT - Fuses and Lockbits --------------------------------------------------------------------------- -*/ - -/* Lock Bits */ -typedef struct NVM_LOCKBITS_struct -{ - register8_t LOCK_BITS; /* Lock Bits (Changed from LOCKBITS to avoid avr-libc collision) */ -} NVM_LOCKBITS_t; - -/* Boot lock bits - boot setcion */ -typedef enum FUSE_BLBB_enum -{ - FUSE_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ - FUSE_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ - FUSE_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ - FUSE_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ -} FUSE_BLBB_t; - -/* Boot lock bits - application section */ -typedef enum FUSE_BLBA_enum -{ - FUSE_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ - FUSE_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ - FUSE_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ - FUSE_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ -} FUSE_BLBA_t; - -/* Boot lock bits - application table section */ -typedef enum FUSE_BLBAT_enum -{ - FUSE_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ - FUSE_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ - FUSE_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ - FUSE_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ -} FUSE_BLBAT_t; - -/* Lock bits */ -typedef enum FUSE_LB_enum -{ - FUSE_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ - FUSE_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ - FUSE_LB_NOLOCK_gc = (0x03<<0), /* No locks */ -} FUSE_LB_t; - - -/* --------------------------------------------------------------------------- -SIGROW - Signature Row --------------------------------------------------------------------------- -*/ - -/* Production Signatures */ -typedef struct NVM_PROD_SIGNATURES_struct -{ - register8_t RCOSC2M; /* RCOSC 2 MHz Calibration Value B */ - register8_t RCOSC2MA; /* RCOSC 2 MHz Calibration Value A */ - register8_t RCOSC32K; /* RCOSC 32.768 kHz Calibration Value */ - register8_t RCOSC32M; /* RCOSC 32 MHz Calibration Value B */ - register8_t RCOSC32MA; /* RCOSC 32 MHz Calibration Value A */ - register8_t reserved_0x05; - register8_t reserved_0x06; - register8_t reserved_0x07; - register8_t LOTNUM0; /* Lot Number Byte 0, ASCII */ - register8_t LOTNUM1; /* Lot Number Byte 1, ASCII */ - register8_t LOTNUM2; /* Lot Number Byte 2, ASCII */ - register8_t LOTNUM3; /* Lot Number Byte 3, ASCII */ - register8_t LOTNUM4; /* Lot Number Byte 4, ASCII */ - register8_t LOTNUM5; /* Lot Number Byte 5, ASCII */ - register8_t reserved_0x0E; - register8_t reserved_0x0F; - register8_t WAFNUM; /* Wafer Number */ - register8_t reserved_0x11; - register8_t COORDX0; /* Wafer Coordinate X Byte 0 */ - register8_t COORDX1; /* Wafer Coordinate X Byte 1 */ - register8_t COORDY0; /* Wafer Coordinate Y Byte 0 */ - register8_t COORDY1; /* Wafer Coordinate Y Byte 1 */ - register8_t reserved_0x16; - register8_t reserved_0x17; - register8_t reserved_0x18; - register8_t reserved_0x19; - register8_t USBCAL0; /* USB Calibration Byte 0 */ - register8_t USBCAL1; /* USB Calibration Byte 1 */ - register8_t USBRCOSC; /* USB RCOSC Calibration Value B */ - register8_t USBRCOSCA; /* USB RCOSC Calibration Value A */ - register8_t reserved_0x1E; - register8_t reserved_0x1F; - register8_t ADCACAL0; /* ADCA Calibration Byte 0 */ - register8_t ADCACAL1; /* ADCA Calibration Byte 1 */ - register8_t reserved_0x22; - register8_t reserved_0x23; - register8_t reserved_0x24; - register8_t reserved_0x25; - register8_t reserved_0x26; - register8_t reserved_0x27; - register8_t reserved_0x28; - register8_t reserved_0x29; - register8_t reserved_0x2A; - register8_t reserved_0x2B; - register8_t reserved_0x2C; - register8_t reserved_0x2D; - register8_t TEMPSENSE0; /* Temperature Sensor Calibration Byte 0 */ - register8_t TEMPSENSE1; /* Temperature Sensor Calibration Byte 1 */ - register8_t reserved_0x30; - register8_t reserved_0x31; - register8_t reserved_0x32; - register8_t reserved_0x33; - register8_t reserved_0x34; - register8_t reserved_0x35; - register8_t reserved_0x36; - register8_t reserved_0x37; - register8_t reserved_0x38; - register8_t reserved_0x39; - register8_t reserved_0x3A; - register8_t reserved_0x3B; - register8_t reserved_0x3C; - register8_t reserved_0x3D; - register8_t reserved_0x3E; - register8_t reserved_0x3F; -} NVM_PROD_SIGNATURES_t; - -/* -========================================================================== -IO Module Instances. Mapped to memory. -========================================================================== -*/ - -#define VPORT0 (*(VPORT_t *) 0x0010) /* Virtual Port */ -#define VPORT1 (*(VPORT_t *) 0x0014) /* Virtual Port */ -#define VPORT2 (*(VPORT_t *) 0x0018) /* Virtual Port */ -#define VPORT3 (*(VPORT_t *) 0x001C) /* Virtual Port */ -#define OCD (*(OCD_t *) 0x002E) /* On-Chip Debug System */ -#define CLK (*(CLK_t *) 0x0040) /* Clock System */ -#define SLEEP (*(SLEEP_t *) 0x0048) /* Sleep Controller */ -#define OSC (*(OSC_t *) 0x0050) /* Oscillator */ -#define DFLLRC32M (*(DFLL_t *) 0x0060) /* DFLL */ -#define DFLLRC2M (*(DFLL_t *) 0x0068) /* DFLL */ -#define PR (*(PR_t *) 0x0070) /* Power Reduction */ -#define RST (*(RST_t *) 0x0078) /* Reset */ -#define WDT (*(WDT_t *) 0x0080) /* Watch-Dog Timer */ -#define MCU (*(MCU_t *) 0x0090) /* MCU Control */ -#define PMIC (*(PMIC_t *) 0x00A0) /* Programmable Multi-level Interrupt Controller */ -#define PORTCFG (*(PORTCFG_t *) 0x00B0) /* I/O port Configuration */ -#define CRC (*(CRC_t *) 0x00D0) /* Cyclic Redundancy Checker */ -#define EVSYS (*(EVSYS_t *) 0x0180) /* Event System */ -#define NVM (*(NVM_t *) 0x01C0) /* Non-volatile Memory Controller */ -#define ADCA (*(ADC_t *) 0x0200) /* Analog-to-Digital Converter */ -#define ACA (*(AC_t *) 0x0380) /* Analog Comparator */ -#define RTC (*(RTC_t *) 0x0400) /* Real-Time Counter */ -#define TWIC (*(TWI_t *) 0x0480) /* Two-Wire Interface */ -#define TWIE (*(TWI_t *) 0x04A0) /* Two-Wire Interface */ -#define USB (*(USB_t *) 0x04C0) /* Universal Serial Bus */ -#define PORTA (*(PORT_t *) 0x0600) /* I/O Ports */ -#define PORTB (*(PORT_t *) 0x0620) /* I/O Ports */ -#define PORTC (*(PORT_t *) 0x0640) /* I/O Ports */ -#define PORTD (*(PORT_t *) 0x0660) /* I/O Ports */ -#define PORTE (*(PORT_t *) 0x0680) /* I/O Ports */ -#define PORTF (*(PORT_t *) 0x06A0) /* I/O Ports */ -#define PORTR (*(PORT_t *) 0x07E0) /* I/O Ports */ -#define TCC0 (*(TC0_t *) 0x0800) /* 16-bit Timer/Counter 0 */ -#define TCC2 (*(TC2_t *) 0x0800) /* 16-bit Timer/Counter type 2 */ -#define TCC1 (*(TC1_t *) 0x0840) /* 16-bit Timer/Counter 1 */ -#define AWEXC (*(AWEX_t *) 0x0880) /* Advanced Waveform Extension */ -#define HIRESC (*(HIRES_t *) 0x0890) /* High-Resolution Extension */ -#define USARTC0 (*(USART_t *) 0x08A0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ -#define SPIC (*(SPI_t *) 0x08C0) /* Serial Peripheral Interface */ -#define IRCOM (*(IRCOM_t *) 0x08F8) /* IR Communication Module */ -#define TCD0 (*(TC0_t *) 0x0900) /* 16-bit Timer/Counter 0 */ -#define TCD2 (*(TC2_t *) 0x0900) /* 16-bit Timer/Counter type 2 */ -#define USARTD0 (*(USART_t *) 0x09A0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ -#define SPID (*(SPI_t *) 0x09C0) /* Serial Peripheral Interface */ -#define TCE0 (*(TC0_t *) 0x0A00) /* 16-bit Timer/Counter 0 */ -#define TCE2 (*(TC2_t *) 0x0A00) /* 16-bit Timer/Counter type 2 */ -#define USARTE0 (*(USART_t *) 0x0AA0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ -#define TCF0 (*(TC0_t *) 0x0B00) /* 16-bit Timer/Counter 0 */ -#define TCF2 (*(TC2_t *) 0x0B00) /* 16-bit Timer/Counter type 2 */ - - -#endif /* !defined (__ASSEMBLER__) */ - - -/* ========== Flattened fully qualified IO register names ========== */ - -/* GPIO - General Purpose IO Registers */ -#define GPIO_GPIOR0 _SFR_MEM8(0x0000) -#define GPIO_GPIOR1 _SFR_MEM8(0x0001) -#define GPIO_GPIOR2 _SFR_MEM8(0x0002) -#define GPIO_GPIOR3 _SFR_MEM8(0x0003) - -/* Deprecated */ -#define GPIO_GPIO0 _SFR_MEM8(0x0000) -#define GPIO_GPIO1 _SFR_MEM8(0x0001) -#define GPIO_GPIO2 _SFR_MEM8(0x0002) -#define GPIO_GPIO3 _SFR_MEM8(0x0003) - -/* NVM_FUSES - Fuses */ -#define FUSE_FUSEBYTE1 _SFR_MEM8(0x0001) -#define FUSE_FUSEBYTE2 _SFR_MEM8(0x0002) -#define FUSE_FUSEBYTE4 _SFR_MEM8(0x0004) -#define FUSE_FUSEBYTE5 _SFR_MEM8(0x0005) - -/* NVM_LOCKBITS - Lock Bits */ -#define LOCKBIT_LOCKBITS _SFR_MEM8(0x0000) - -/* NVM_PROD_SIGNATURES - Production Signatures */ -#define PRODSIGNATURES_RCOSC2M _SFR_MEM8(0x0000) -#define PRODSIGNATURES_RCOSC2MA _SFR_MEM8(0x0001) -#define PRODSIGNATURES_RCOSC32K _SFR_MEM8(0x0002) -#define PRODSIGNATURES_RCOSC32M _SFR_MEM8(0x0003) -#define PRODSIGNATURES_RCOSC32MA _SFR_MEM8(0x0004) -#define PRODSIGNATURES_LOTNUM0 _SFR_MEM8(0x0008) -#define PRODSIGNATURES_LOTNUM1 _SFR_MEM8(0x0009) -#define PRODSIGNATURES_LOTNUM2 _SFR_MEM8(0x000A) -#define PRODSIGNATURES_LOTNUM3 _SFR_MEM8(0x000B) -#define PRODSIGNATURES_LOTNUM4 _SFR_MEM8(0x000C) -#define PRODSIGNATURES_LOTNUM5 _SFR_MEM8(0x000D) -#define PRODSIGNATURES_WAFNUM _SFR_MEM8(0x0010) -#define PRODSIGNATURES_COORDX0 _SFR_MEM8(0x0012) -#define PRODSIGNATURES_COORDX1 _SFR_MEM8(0x0013) -#define PRODSIGNATURES_COORDY0 _SFR_MEM8(0x0014) -#define PRODSIGNATURES_COORDY1 _SFR_MEM8(0x0015) -#define PRODSIGNATURES_USBCAL0 _SFR_MEM8(0x001A) -#define PRODSIGNATURES_USBCAL1 _SFR_MEM8(0x001B) -#define PRODSIGNATURES_USBRCOSC _SFR_MEM8(0x001C) -#define PRODSIGNATURES_USBRCOSCA _SFR_MEM8(0x001D) -#define PRODSIGNATURES_ADCACAL0 _SFR_MEM8(0x0020) -#define PRODSIGNATURES_ADCACAL1 _SFR_MEM8(0x0021) -#define PRODSIGNATURES_TEMPSENSE0 _SFR_MEM8(0x002E) -#define PRODSIGNATURES_TEMPSENSE1 _SFR_MEM8(0x002F) - -/* VPORT - Virtual Port */ -#define VPORT0_DIR _SFR_MEM8(0x0010) -#define VPORT0_OUT _SFR_MEM8(0x0011) -#define VPORT0_IN _SFR_MEM8(0x0012) -#define VPORT0_INTFLAGS _SFR_MEM8(0x0013) - -/* VPORT - Virtual Port */ -#define VPORT1_DIR _SFR_MEM8(0x0014) -#define VPORT1_OUT _SFR_MEM8(0x0015) -#define VPORT1_IN _SFR_MEM8(0x0016) -#define VPORT1_INTFLAGS _SFR_MEM8(0x0017) - -/* VPORT - Virtual Port */ -#define VPORT2_DIR _SFR_MEM8(0x0018) -#define VPORT2_OUT _SFR_MEM8(0x0019) -#define VPORT2_IN _SFR_MEM8(0x001A) -#define VPORT2_INTFLAGS _SFR_MEM8(0x001B) - -/* VPORT - Virtual Port */ -#define VPORT3_DIR _SFR_MEM8(0x001C) -#define VPORT3_OUT _SFR_MEM8(0x001D) -#define VPORT3_IN _SFR_MEM8(0x001E) -#define VPORT3_INTFLAGS _SFR_MEM8(0x001F) - -/* OCD - On-Chip Debug System */ -#define OCD_OCDR0 _SFR_MEM8(0x002E) -#define OCD_OCDR1 _SFR_MEM8(0x002F) - -/* CPU - CPU registers */ -#define CPU_CCP _SFR_MEM8(0x0034) -#define CPU_RAMPD _SFR_MEM8(0x0038) -#define CPU_RAMPX _SFR_MEM8(0x0039) -#define CPU_RAMPY _SFR_MEM8(0x003A) -#define CPU_RAMPZ _SFR_MEM8(0x003B) -#define CPU_EIND _SFR_MEM8(0x003C) -#define CPU_SPL _SFR_MEM8(0x003D) -#define CPU_SPH _SFR_MEM8(0x003E) -#define CPU_SREG _SFR_MEM8(0x003F) - -/* CLK - Clock System */ -#define CLK_CTRL _SFR_MEM8(0x0040) -#define CLK_PSCTRL _SFR_MEM8(0x0041) -#define CLK_LOCK _SFR_MEM8(0x0042) -#define CLK_RTCCTRL _SFR_MEM8(0x0043) -#define CLK_USBCTRL _SFR_MEM8(0x0044) - -/* SLEEP - Sleep Controller */ -#define SLEEP_CTRL _SFR_MEM8(0x0048) - -/* OSC - Oscillator */ -#define OSC_CTRL _SFR_MEM8(0x0050) -#define OSC_STATUS _SFR_MEM8(0x0051) -#define OSC_XOSCCTRL _SFR_MEM8(0x0052) -#define OSC_XOSCFAIL _SFR_MEM8(0x0053) -#define OSC_RC32KCAL _SFR_MEM8(0x0054) -#define OSC_PLLCTRL _SFR_MEM8(0x0055) -#define OSC_DFLLCTRL _SFR_MEM8(0x0056) - -/* DFLL - DFLL */ -#define DFLLRC32M_CTRL _SFR_MEM8(0x0060) -#define DFLLRC32M_CALA _SFR_MEM8(0x0062) -#define DFLLRC32M_CALB _SFR_MEM8(0x0063) -#define DFLLRC32M_COMP0 _SFR_MEM8(0x0064) -#define DFLLRC32M_COMP1 _SFR_MEM8(0x0065) -#define DFLLRC32M_COMP2 _SFR_MEM8(0x0066) - -/* DFLL - DFLL */ -#define DFLLRC2M_CTRL _SFR_MEM8(0x0068) -#define DFLLRC2M_CALA _SFR_MEM8(0x006A) -#define DFLLRC2M_CALB _SFR_MEM8(0x006B) -#define DFLLRC2M_COMP0 _SFR_MEM8(0x006C) -#define DFLLRC2M_COMP1 _SFR_MEM8(0x006D) -#define DFLLRC2M_COMP2 _SFR_MEM8(0x006E) - -/* PR - Power Reduction */ -#define PR_PRGEN _SFR_MEM8(0x0070) -#define PR_PRPA _SFR_MEM8(0x0071) -#define PR_PRPC _SFR_MEM8(0x0073) -#define PR_PRPD _SFR_MEM8(0x0074) -#define PR_PRPE _SFR_MEM8(0x0075) -#define PR_PRPF _SFR_MEM8(0x0076) - -/* RST - Reset */ -#define RST_STATUS _SFR_MEM8(0x0078) -#define RST_CTRL _SFR_MEM8(0x0079) - -/* WDT - Watch-Dog Timer */ -#define WDT_CTRL _SFR_MEM8(0x0080) -#define WDT_WINCTRL _SFR_MEM8(0x0081) -#define WDT_STATUS _SFR_MEM8(0x0082) - -/* MCU - MCU Control */ -#define MCU_DEVID0 _SFR_MEM8(0x0090) -#define MCU_DEVID1 _SFR_MEM8(0x0091) -#define MCU_DEVID2 _SFR_MEM8(0x0092) -#define MCU_REVID _SFR_MEM8(0x0093) -#define MCU_ANAINIT _SFR_MEM8(0x0097) -#define MCU_EVSYSLOCK _SFR_MEM8(0x0098) -#define MCU_AWEXLOCK _SFR_MEM8(0x0099) - -/* PMIC - Programmable Multi-level Interrupt Controller */ -#define PMIC_STATUS _SFR_MEM8(0x00A0) -#define PMIC_INTPRI _SFR_MEM8(0x00A1) -#define PMIC_CTRL _SFR_MEM8(0x00A2) - -/* PORTCFG - I/O port Configuration */ -#define PORTCFG_MPCMASK _SFR_MEM8(0x00B0) -#define PORTCFG_VPCTRLA _SFR_MEM8(0x00B2) -#define PORTCFG_VPCTRLB _SFR_MEM8(0x00B3) -#define PORTCFG_CLKEVOUT _SFR_MEM8(0x00B4) -#define PORTCFG_EVOUTSEL _SFR_MEM8(0x00B6) - -/* CRC - Cyclic Redundancy Checker */ -#define CRC_CTRL _SFR_MEM8(0x00D0) -#define CRC_STATUS _SFR_MEM8(0x00D1) -#define CRC_DATAIN _SFR_MEM8(0x00D3) -#define CRC_CHECKSUM0 _SFR_MEM8(0x00D4) -#define CRC_CHECKSUM1 _SFR_MEM8(0x00D5) -#define CRC_CHECKSUM2 _SFR_MEM8(0x00D6) -#define CRC_CHECKSUM3 _SFR_MEM8(0x00D7) - -/* EVSYS - Event System */ -#define EVSYS_CH0MUX _SFR_MEM8(0x0180) -#define EVSYS_CH1MUX _SFR_MEM8(0x0181) -#define EVSYS_CH2MUX _SFR_MEM8(0x0182) -#define EVSYS_CH3MUX _SFR_MEM8(0x0183) -#define EVSYS_CH0CTRL _SFR_MEM8(0x0188) -#define EVSYS_CH1CTRL _SFR_MEM8(0x0189) -#define EVSYS_CH2CTRL _SFR_MEM8(0x018A) -#define EVSYS_CH3CTRL _SFR_MEM8(0x018B) -#define EVSYS_STROBE _SFR_MEM8(0x0190) -#define EVSYS_DATA _SFR_MEM8(0x0191) - -/* NVM - Non-volatile Memory Controller */ -#define NVM_ADDR0 _SFR_MEM8(0x01C0) -#define NVM_ADDR1 _SFR_MEM8(0x01C1) -#define NVM_ADDR2 _SFR_MEM8(0x01C2) -#define NVM_DATA0 _SFR_MEM8(0x01C4) -#define NVM_DATA1 _SFR_MEM8(0x01C5) -#define NVM_DATA2 _SFR_MEM8(0x01C6) -#define NVM_CMD _SFR_MEM8(0x01CA) -#define NVM_CTRLA _SFR_MEM8(0x01CB) -#define NVM_CTRLB _SFR_MEM8(0x01CC) -#define NVM_INTCTRL _SFR_MEM8(0x01CD) -#define NVM_STATUS _SFR_MEM8(0x01CF) -#define NVM_LOCKBITS _SFR_MEM8(0x01D0) - -/* ADC - Analog-to-Digital Converter */ -#define ADCA_CTRLA _SFR_MEM8(0x0200) -#define ADCA_CTRLB _SFR_MEM8(0x0201) -#define ADCA_REFCTRL _SFR_MEM8(0x0202) -#define ADCA_EVCTRL _SFR_MEM8(0x0203) -#define ADCA_PRESCALER _SFR_MEM8(0x0204) -#define ADCA_INTFLAGS _SFR_MEM8(0x0206) -#define ADCA_TEMP _SFR_MEM8(0x0207) -#define ADCA_CAL _SFR_MEM16(0x020C) -#define ADCA_CH0RES _SFR_MEM16(0x0210) -#define ADCA_CMP _SFR_MEM16(0x0218) -#define ADCA_CH0_CTRL _SFR_MEM8(0x0220) -#define ADCA_CH0_MUXCTRL _SFR_MEM8(0x0221) -#define ADCA_CH0_INTCTRL _SFR_MEM8(0x0222) -#define ADCA_CH0_INTFLAGS _SFR_MEM8(0x0223) -#define ADCA_CH0_RES _SFR_MEM16(0x0224) -#define ADCA_CH0_SCAN _SFR_MEM8(0x0226) - -/* AC - Analog Comparator */ -#define ACA_AC0CTRL _SFR_MEM8(0x0380) -#define ACA_AC1CTRL _SFR_MEM8(0x0381) -#define ACA_AC0MUXCTRL _SFR_MEM8(0x0382) -#define ACA_AC1MUXCTRL _SFR_MEM8(0x0383) -#define ACA_CTRLA _SFR_MEM8(0x0384) -#define ACA_CTRLB _SFR_MEM8(0x0385) -#define ACA_WINCTRL _SFR_MEM8(0x0386) -#define ACA_STATUS _SFR_MEM8(0x0387) - -/* RTC - Real-Time Counter */ -#define RTC_CTRL _SFR_MEM8(0x0400) -#define RTC_STATUS _SFR_MEM8(0x0401) -#define RTC_INTCTRL _SFR_MEM8(0x0402) -#define RTC_INTFLAGS _SFR_MEM8(0x0403) -#define RTC_TEMP _SFR_MEM8(0x0404) -#define RTC_CNT _SFR_MEM16(0x0408) -#define RTC_PER _SFR_MEM16(0x040A) -#define RTC_COMP _SFR_MEM16(0x040C) - -/* TWI - Two-Wire Interface */ -#define TWIC_CTRL _SFR_MEM8(0x0480) -#define TWIC_MASTER_CTRLA _SFR_MEM8(0x0481) -#define TWIC_MASTER_CTRLB _SFR_MEM8(0x0482) -#define TWIC_MASTER_CTRLC _SFR_MEM8(0x0483) -#define TWIC_MASTER_STATUS _SFR_MEM8(0x0484) -#define TWIC_MASTER_BAUD _SFR_MEM8(0x0485) -#define TWIC_MASTER_ADDR _SFR_MEM8(0x0486) -#define TWIC_MASTER_DATA _SFR_MEM8(0x0487) -#define TWIC_SLAVE_CTRLA _SFR_MEM8(0x0488) -#define TWIC_SLAVE_CTRLB _SFR_MEM8(0x0489) -#define TWIC_SLAVE_STATUS _SFR_MEM8(0x048A) -#define TWIC_SLAVE_ADDR _SFR_MEM8(0x048B) -#define TWIC_SLAVE_DATA _SFR_MEM8(0x048C) -#define TWIC_SLAVE_ADDRMASK _SFR_MEM8(0x048D) - -/* TWI - Two-Wire Interface */ -#define TWIE_CTRL _SFR_MEM8(0x04A0) -#define TWIE_MASTER_CTRLA _SFR_MEM8(0x04A1) -#define TWIE_MASTER_CTRLB _SFR_MEM8(0x04A2) -#define TWIE_MASTER_CTRLC _SFR_MEM8(0x04A3) -#define TWIE_MASTER_STATUS _SFR_MEM8(0x04A4) -#define TWIE_MASTER_BAUD _SFR_MEM8(0x04A5) -#define TWIE_MASTER_ADDR _SFR_MEM8(0x04A6) -#define TWIE_MASTER_DATA _SFR_MEM8(0x04A7) -#define TWIE_SLAVE_CTRLA _SFR_MEM8(0x04A8) -#define TWIE_SLAVE_CTRLB _SFR_MEM8(0x04A9) -#define TWIE_SLAVE_STATUS _SFR_MEM8(0x04AA) -#define TWIE_SLAVE_ADDR _SFR_MEM8(0x04AB) -#define TWIE_SLAVE_DATA _SFR_MEM8(0x04AC) -#define TWIE_SLAVE_ADDRMASK _SFR_MEM8(0x04AD) - -/* USB - Universal Serial Bus */ -#define USB_CTRLA _SFR_MEM8(0x04C0) -#define USB_CTRLB _SFR_MEM8(0x04C1) -#define USB_STATUS _SFR_MEM8(0x04C2) -#define USB_ADDR _SFR_MEM8(0x04C3) -#define USB_FIFOWP _SFR_MEM8(0x04C4) -#define USB_FIFORP _SFR_MEM8(0x04C5) -#define USB_EPPTR _SFR_MEM16(0x04C6) -#define USB_INTCTRLA _SFR_MEM8(0x04C8) -#define USB_INTCTRLB _SFR_MEM8(0x04C9) -#define USB_INTFLAGSACLR _SFR_MEM8(0x04CA) -#define USB_INTFLAGSASET _SFR_MEM8(0x04CB) -#define USB_INTFLAGSBCLR _SFR_MEM8(0x04CC) -#define USB_INTFLAGSBSET _SFR_MEM8(0x04CD) -#define USB_CAL0 _SFR_MEM8(0x04FA) -#define USB_CAL1 _SFR_MEM8(0x04FB) - -/* PORT - I/O Ports */ -#define PORTA_DIR _SFR_MEM8(0x0600) -#define PORTA_DIRSET _SFR_MEM8(0x0601) -#define PORTA_DIRCLR _SFR_MEM8(0x0602) -#define PORTA_DIRTGL _SFR_MEM8(0x0603) -#define PORTA_OUT _SFR_MEM8(0x0604) -#define PORTA_OUTSET _SFR_MEM8(0x0605) -#define PORTA_OUTCLR _SFR_MEM8(0x0606) -#define PORTA_OUTTGL _SFR_MEM8(0x0607) -#define PORTA_IN _SFR_MEM8(0x0608) -#define PORTA_INTCTRL _SFR_MEM8(0x0609) -#define PORTA_INT0MASK _SFR_MEM8(0x060A) -#define PORTA_INT1MASK _SFR_MEM8(0x060B) -#define PORTA_INTFLAGS _SFR_MEM8(0x060C) -#define PORTA_REMAP _SFR_MEM8(0x060E) -#define PORTA_PIN0CTRL _SFR_MEM8(0x0610) -#define PORTA_PIN1CTRL _SFR_MEM8(0x0611) -#define PORTA_PIN2CTRL _SFR_MEM8(0x0612) -#define PORTA_PIN3CTRL _SFR_MEM8(0x0613) -#define PORTA_PIN4CTRL _SFR_MEM8(0x0614) -#define PORTA_PIN5CTRL _SFR_MEM8(0x0615) -#define PORTA_PIN6CTRL _SFR_MEM8(0x0616) -#define PORTA_PIN7CTRL _SFR_MEM8(0x0617) - -/* PORT - I/O Ports */ -#define PORTB_DIR _SFR_MEM8(0x0620) -#define PORTB_DIRSET _SFR_MEM8(0x0621) -#define PORTB_DIRCLR _SFR_MEM8(0x0622) -#define PORTB_DIRTGL _SFR_MEM8(0x0623) -#define PORTB_OUT _SFR_MEM8(0x0624) -#define PORTB_OUTSET _SFR_MEM8(0x0625) -#define PORTB_OUTCLR _SFR_MEM8(0x0626) -#define PORTB_OUTTGL _SFR_MEM8(0x0627) -#define PORTB_IN _SFR_MEM8(0x0628) -#define PORTB_INTCTRL _SFR_MEM8(0x0629) -#define PORTB_INT0MASK _SFR_MEM8(0x062A) -#define PORTB_INT1MASK _SFR_MEM8(0x062B) -#define PORTB_INTFLAGS _SFR_MEM8(0x062C) -#define PORTB_REMAP _SFR_MEM8(0x062E) -#define PORTB_PIN0CTRL _SFR_MEM8(0x0630) -#define PORTB_PIN1CTRL _SFR_MEM8(0x0631) -#define PORTB_PIN2CTRL _SFR_MEM8(0x0632) -#define PORTB_PIN3CTRL _SFR_MEM8(0x0633) -#define PORTB_PIN4CTRL _SFR_MEM8(0x0634) -#define PORTB_PIN5CTRL _SFR_MEM8(0x0635) -#define PORTB_PIN6CTRL _SFR_MEM8(0x0636) -#define PORTB_PIN7CTRL _SFR_MEM8(0x0637) - -/* PORT - I/O Ports */ -#define PORTC_DIR _SFR_MEM8(0x0640) -#define PORTC_DIRSET _SFR_MEM8(0x0641) -#define PORTC_DIRCLR _SFR_MEM8(0x0642) -#define PORTC_DIRTGL _SFR_MEM8(0x0643) -#define PORTC_OUT _SFR_MEM8(0x0644) -#define PORTC_OUTSET _SFR_MEM8(0x0645) -#define PORTC_OUTCLR _SFR_MEM8(0x0646) -#define PORTC_OUTTGL _SFR_MEM8(0x0647) -#define PORTC_IN _SFR_MEM8(0x0648) -#define PORTC_INTCTRL _SFR_MEM8(0x0649) -#define PORTC_INT0MASK _SFR_MEM8(0x064A) -#define PORTC_INT1MASK _SFR_MEM8(0x064B) -#define PORTC_INTFLAGS _SFR_MEM8(0x064C) -#define PORTC_REMAP _SFR_MEM8(0x064E) -#define PORTC_PIN0CTRL _SFR_MEM8(0x0650) -#define PORTC_PIN1CTRL _SFR_MEM8(0x0651) -#define PORTC_PIN2CTRL _SFR_MEM8(0x0652) -#define PORTC_PIN3CTRL _SFR_MEM8(0x0653) -#define PORTC_PIN4CTRL _SFR_MEM8(0x0654) -#define PORTC_PIN5CTRL _SFR_MEM8(0x0655) -#define PORTC_PIN6CTRL _SFR_MEM8(0x0656) -#define PORTC_PIN7CTRL _SFR_MEM8(0x0657) - -/* PORT - I/O Ports */ -#define PORTD_DIR _SFR_MEM8(0x0660) -#define PORTD_DIRSET _SFR_MEM8(0x0661) -#define PORTD_DIRCLR _SFR_MEM8(0x0662) -#define PORTD_DIRTGL _SFR_MEM8(0x0663) -#define PORTD_OUT _SFR_MEM8(0x0664) -#define PORTD_OUTSET _SFR_MEM8(0x0665) -#define PORTD_OUTCLR _SFR_MEM8(0x0666) -#define PORTD_OUTTGL _SFR_MEM8(0x0667) -#define PORTD_IN _SFR_MEM8(0x0668) -#define PORTD_INTCTRL _SFR_MEM8(0x0669) -#define PORTD_INT0MASK _SFR_MEM8(0x066A) -#define PORTD_INT1MASK _SFR_MEM8(0x066B) -#define PORTD_INTFLAGS _SFR_MEM8(0x066C) -#define PORTD_REMAP _SFR_MEM8(0x066E) -#define PORTD_PIN0CTRL _SFR_MEM8(0x0670) -#define PORTD_PIN1CTRL _SFR_MEM8(0x0671) -#define PORTD_PIN2CTRL _SFR_MEM8(0x0672) -#define PORTD_PIN3CTRL _SFR_MEM8(0x0673) -#define PORTD_PIN4CTRL _SFR_MEM8(0x0674) -#define PORTD_PIN5CTRL _SFR_MEM8(0x0675) -#define PORTD_PIN6CTRL _SFR_MEM8(0x0676) -#define PORTD_PIN7CTRL _SFR_MEM8(0x0677) - -/* PORT - I/O Ports */ -#define PORTE_DIR _SFR_MEM8(0x0680) -#define PORTE_DIRSET _SFR_MEM8(0x0681) -#define PORTE_DIRCLR _SFR_MEM8(0x0682) -#define PORTE_DIRTGL _SFR_MEM8(0x0683) -#define PORTE_OUT _SFR_MEM8(0x0684) -#define PORTE_OUTSET _SFR_MEM8(0x0685) -#define PORTE_OUTCLR _SFR_MEM8(0x0686) -#define PORTE_OUTTGL _SFR_MEM8(0x0687) -#define PORTE_IN _SFR_MEM8(0x0688) -#define PORTE_INTCTRL _SFR_MEM8(0x0689) -#define PORTE_INT0MASK _SFR_MEM8(0x068A) -#define PORTE_INT1MASK _SFR_MEM8(0x068B) -#define PORTE_INTFLAGS _SFR_MEM8(0x068C) -#define PORTE_REMAP _SFR_MEM8(0x068E) -#define PORTE_PIN0CTRL _SFR_MEM8(0x0690) -#define PORTE_PIN1CTRL _SFR_MEM8(0x0691) -#define PORTE_PIN2CTRL _SFR_MEM8(0x0692) -#define PORTE_PIN3CTRL _SFR_MEM8(0x0693) -#define PORTE_PIN4CTRL _SFR_MEM8(0x0694) -#define PORTE_PIN5CTRL _SFR_MEM8(0x0695) -#define PORTE_PIN6CTRL _SFR_MEM8(0x0696) -#define PORTE_PIN7CTRL _SFR_MEM8(0x0697) - -/* PORT - I/O Ports */ -#define PORTF_DIR _SFR_MEM8(0x06A0) -#define PORTF_DIRSET _SFR_MEM8(0x06A1) -#define PORTF_DIRCLR _SFR_MEM8(0x06A2) -#define PORTF_DIRTGL _SFR_MEM8(0x06A3) -#define PORTF_OUT _SFR_MEM8(0x06A4) -#define PORTF_OUTSET _SFR_MEM8(0x06A5) -#define PORTF_OUTCLR _SFR_MEM8(0x06A6) -#define PORTF_OUTTGL _SFR_MEM8(0x06A7) -#define PORTF_IN _SFR_MEM8(0x06A8) -#define PORTF_INTCTRL _SFR_MEM8(0x06A9) -#define PORTF_INT0MASK _SFR_MEM8(0x06AA) -#define PORTF_INT1MASK _SFR_MEM8(0x06AB) -#define PORTF_INTFLAGS _SFR_MEM8(0x06AC) -#define PORTF_REMAP _SFR_MEM8(0x06AE) -#define PORTF_PIN0CTRL _SFR_MEM8(0x06B0) -#define PORTF_PIN1CTRL _SFR_MEM8(0x06B1) -#define PORTF_PIN2CTRL _SFR_MEM8(0x06B2) -#define PORTF_PIN3CTRL _SFR_MEM8(0x06B3) -#define PORTF_PIN4CTRL _SFR_MEM8(0x06B4) -#define PORTF_PIN5CTRL _SFR_MEM8(0x06B5) -#define PORTF_PIN6CTRL _SFR_MEM8(0x06B6) -#define PORTF_PIN7CTRL _SFR_MEM8(0x06B7) - -/* PORT - I/O Ports */ -#define PORTR_DIR _SFR_MEM8(0x07E0) -#define PORTR_DIRSET _SFR_MEM8(0x07E1) -#define PORTR_DIRCLR _SFR_MEM8(0x07E2) -#define PORTR_DIRTGL _SFR_MEM8(0x07E3) -#define PORTR_OUT _SFR_MEM8(0x07E4) -#define PORTR_OUTSET _SFR_MEM8(0x07E5) -#define PORTR_OUTCLR _SFR_MEM8(0x07E6) -#define PORTR_OUTTGL _SFR_MEM8(0x07E7) -#define PORTR_IN _SFR_MEM8(0x07E8) -#define PORTR_INTCTRL _SFR_MEM8(0x07E9) -#define PORTR_INT0MASK _SFR_MEM8(0x07EA) -#define PORTR_INT1MASK _SFR_MEM8(0x07EB) -#define PORTR_INTFLAGS _SFR_MEM8(0x07EC) -#define PORTR_REMAP _SFR_MEM8(0x07EE) -#define PORTR_PIN0CTRL _SFR_MEM8(0x07F0) -#define PORTR_PIN1CTRL _SFR_MEM8(0x07F1) -#define PORTR_PIN2CTRL _SFR_MEM8(0x07F2) -#define PORTR_PIN3CTRL _SFR_MEM8(0x07F3) -#define PORTR_PIN4CTRL _SFR_MEM8(0x07F4) -#define PORTR_PIN5CTRL _SFR_MEM8(0x07F5) -#define PORTR_PIN6CTRL _SFR_MEM8(0x07F6) -#define PORTR_PIN7CTRL _SFR_MEM8(0x07F7) - -/* TC0 - 16-bit Timer/Counter 0 */ -#define TCC0_CTRLA _SFR_MEM8(0x0800) -#define TCC0_CTRLB _SFR_MEM8(0x0801) -#define TCC0_CTRLC _SFR_MEM8(0x0802) -#define TCC0_CTRLD _SFR_MEM8(0x0803) -#define TCC0_CTRLE _SFR_MEM8(0x0804) -#define TCC0_INTCTRLA _SFR_MEM8(0x0806) -#define TCC0_INTCTRLB _SFR_MEM8(0x0807) -#define TCC0_CTRLFCLR _SFR_MEM8(0x0808) -#define TCC0_CTRLFSET _SFR_MEM8(0x0809) -#define TCC0_CTRLGCLR _SFR_MEM8(0x080A) -#define TCC0_CTRLGSET _SFR_MEM8(0x080B) -#define TCC0_INTFLAGS _SFR_MEM8(0x080C) -#define TCC0_TEMP _SFR_MEM8(0x080F) -#define TCC0_CNT _SFR_MEM16(0x0820) -#define TCC0_PER _SFR_MEM16(0x0826) -#define TCC0_CCA _SFR_MEM16(0x0828) -#define TCC0_CCB _SFR_MEM16(0x082A) -#define TCC0_CCC _SFR_MEM16(0x082C) -#define TCC0_CCD _SFR_MEM16(0x082E) -#define TCC0_PERBUF _SFR_MEM16(0x0836) -#define TCC0_CCABUF _SFR_MEM16(0x0838) -#define TCC0_CCBBUF _SFR_MEM16(0x083A) -#define TCC0_CCCBUF _SFR_MEM16(0x083C) -#define TCC0_CCDBUF _SFR_MEM16(0x083E) - -/* TC2 - 16-bit Timer/Counter type 2 */ -#define TCC2_CTRLA _SFR_MEM8(0x0800) -#define TCC2_CTRLB _SFR_MEM8(0x0801) -#define TCC2_CTRLC _SFR_MEM8(0x0802) -#define TCC2_CTRLE _SFR_MEM8(0x0804) -#define TCC2_INTCTRLA _SFR_MEM8(0x0806) -#define TCC2_INTCTRLB _SFR_MEM8(0x0807) -#define TCC2_CTRLF _SFR_MEM8(0x0809) -#define TCC2_INTFLAGS _SFR_MEM8(0x080C) -#define TCC2_LCNT _SFR_MEM8(0x0820) -#define TCC2_HCNT _SFR_MEM8(0x0821) -#define TCC2_LPER _SFR_MEM8(0x0826) -#define TCC2_HPER _SFR_MEM8(0x0827) -#define TCC2_LCMPA _SFR_MEM8(0x0828) -#define TCC2_HCMPA _SFR_MEM8(0x0829) -#define TCC2_LCMPB _SFR_MEM8(0x082A) -#define TCC2_HCMPB _SFR_MEM8(0x082B) -#define TCC2_LCMPC _SFR_MEM8(0x082C) -#define TCC2_HCMPC _SFR_MEM8(0x082D) -#define TCC2_LCMPD _SFR_MEM8(0x082E) -#define TCC2_HCMPD _SFR_MEM8(0x082F) - -/* TC1 - 16-bit Timer/Counter 1 */ -#define TCC1_CTRLA _SFR_MEM8(0x0840) -#define TCC1_CTRLB _SFR_MEM8(0x0841) -#define TCC1_CTRLC _SFR_MEM8(0x0842) -#define TCC1_CTRLD _SFR_MEM8(0x0843) -#define TCC1_CTRLE _SFR_MEM8(0x0844) -#define TCC1_INTCTRLA _SFR_MEM8(0x0846) -#define TCC1_INTCTRLB _SFR_MEM8(0x0847) -#define TCC1_CTRLFCLR _SFR_MEM8(0x0848) -#define TCC1_CTRLFSET _SFR_MEM8(0x0849) -#define TCC1_CTRLGCLR _SFR_MEM8(0x084A) -#define TCC1_CTRLGSET _SFR_MEM8(0x084B) -#define TCC1_INTFLAGS _SFR_MEM8(0x084C) -#define TCC1_TEMP _SFR_MEM8(0x084F) -#define TCC1_CNT _SFR_MEM16(0x0860) -#define TCC1_PER _SFR_MEM16(0x0866) -#define TCC1_CCA _SFR_MEM16(0x0868) -#define TCC1_CCB _SFR_MEM16(0x086A) -#define TCC1_PERBUF _SFR_MEM16(0x0876) -#define TCC1_CCABUF _SFR_MEM16(0x0878) -#define TCC1_CCBBUF _SFR_MEM16(0x087A) - -/* AWEX - Advanced Waveform Extension */ -#define AWEXC_CTRL _SFR_MEM8(0x0880) -#define AWEXC_FDEMASK _SFR_MEM8(0x0882) -#define AWEXC_FDCTRL _SFR_MEM8(0x0883) -#define AWEXC_STATUS _SFR_MEM8(0x0884) -#define AWEXC_STATUSSET _SFR_MEM8(0x0885) -#define AWEXC_DTBOTH _SFR_MEM8(0x0886) -#define AWEXC_DTBOTHBUF _SFR_MEM8(0x0887) -#define AWEXC_DTLS _SFR_MEM8(0x0888) -#define AWEXC_DTHS _SFR_MEM8(0x0889) -#define AWEXC_DTLSBUF _SFR_MEM8(0x088A) -#define AWEXC_DTHSBUF _SFR_MEM8(0x088B) -#define AWEXC_OUTOVEN _SFR_MEM8(0x088C) - -/* HIRES - High-Resolution Extension */ -#define HIRESC_CTRLA _SFR_MEM8(0x0890) - -/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ -#define USARTC0_DATA _SFR_MEM8(0x08A0) -#define USARTC0_STATUS _SFR_MEM8(0x08A1) -#define USARTC0_CTRLA _SFR_MEM8(0x08A3) -#define USARTC0_CTRLB _SFR_MEM8(0x08A4) -#define USARTC0_CTRLC _SFR_MEM8(0x08A5) -#define USARTC0_BAUDCTRLA _SFR_MEM8(0x08A6) -#define USARTC0_BAUDCTRLB _SFR_MEM8(0x08A7) - -/* SPI - Serial Peripheral Interface */ -#define SPIC_CTRL _SFR_MEM8(0x08C0) -#define SPIC_INTCTRL _SFR_MEM8(0x08C1) -#define SPIC_STATUS _SFR_MEM8(0x08C2) -#define SPIC_DATA _SFR_MEM8(0x08C3) - -/* IRCOM - IR Communication Module */ -#define IRCOM_CTRL _SFR_MEM8(0x08F8) -#define IRCOM_TXPLCTRL _SFR_MEM8(0x08F9) -#define IRCOM_RXPLCTRL _SFR_MEM8(0x08FA) - -/* TC0 - 16-bit Timer/Counter 0 */ -#define TCD0_CTRLA _SFR_MEM8(0x0900) -#define TCD0_CTRLB _SFR_MEM8(0x0901) -#define TCD0_CTRLC _SFR_MEM8(0x0902) -#define TCD0_CTRLD _SFR_MEM8(0x0903) -#define TCD0_CTRLE _SFR_MEM8(0x0904) -#define TCD0_INTCTRLA _SFR_MEM8(0x0906) -#define TCD0_INTCTRLB _SFR_MEM8(0x0907) -#define TCD0_CTRLFCLR _SFR_MEM8(0x0908) -#define TCD0_CTRLFSET _SFR_MEM8(0x0909) -#define TCD0_CTRLGCLR _SFR_MEM8(0x090A) -#define TCD0_CTRLGSET _SFR_MEM8(0x090B) -#define TCD0_INTFLAGS _SFR_MEM8(0x090C) -#define TCD0_TEMP _SFR_MEM8(0x090F) -#define TCD0_CNT _SFR_MEM16(0x0920) -#define TCD0_PER _SFR_MEM16(0x0926) -#define TCD0_CCA _SFR_MEM16(0x0928) -#define TCD0_CCB _SFR_MEM16(0x092A) -#define TCD0_CCC _SFR_MEM16(0x092C) -#define TCD0_CCD _SFR_MEM16(0x092E) -#define TCD0_PERBUF _SFR_MEM16(0x0936) -#define TCD0_CCABUF _SFR_MEM16(0x0938) -#define TCD0_CCBBUF _SFR_MEM16(0x093A) -#define TCD0_CCCBUF _SFR_MEM16(0x093C) -#define TCD0_CCDBUF _SFR_MEM16(0x093E) - -/* TC2 - 16-bit Timer/Counter type 2 */ -#define TCD2_CTRLA _SFR_MEM8(0x0900) -#define TCD2_CTRLB _SFR_MEM8(0x0901) -#define TCD2_CTRLC _SFR_MEM8(0x0902) -#define TCD2_CTRLE _SFR_MEM8(0x0904) -#define TCD2_INTCTRLA _SFR_MEM8(0x0906) -#define TCD2_INTCTRLB _SFR_MEM8(0x0907) -#define TCD2_CTRLF _SFR_MEM8(0x0909) -#define TCD2_INTFLAGS _SFR_MEM8(0x090C) -#define TCD2_LCNT _SFR_MEM8(0x0920) -#define TCD2_HCNT _SFR_MEM8(0x0921) -#define TCD2_LPER _SFR_MEM8(0x0926) -#define TCD2_HPER _SFR_MEM8(0x0927) -#define TCD2_LCMPA _SFR_MEM8(0x0928) -#define TCD2_HCMPA _SFR_MEM8(0x0929) -#define TCD2_LCMPB _SFR_MEM8(0x092A) -#define TCD2_HCMPB _SFR_MEM8(0x092B) -#define TCD2_LCMPC _SFR_MEM8(0x092C) -#define TCD2_HCMPC _SFR_MEM8(0x092D) -#define TCD2_LCMPD _SFR_MEM8(0x092E) -#define TCD2_HCMPD _SFR_MEM8(0x092F) - -/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ -#define USARTD0_DATA _SFR_MEM8(0x09A0) -#define USARTD0_STATUS _SFR_MEM8(0x09A1) -#define USARTD0_CTRLA _SFR_MEM8(0x09A3) -#define USARTD0_CTRLB _SFR_MEM8(0x09A4) -#define USARTD0_CTRLC _SFR_MEM8(0x09A5) -#define USARTD0_BAUDCTRLA _SFR_MEM8(0x09A6) -#define USARTD0_BAUDCTRLB _SFR_MEM8(0x09A7) - -/* SPI - Serial Peripheral Interface */ -#define SPID_CTRL _SFR_MEM8(0x09C0) -#define SPID_INTCTRL _SFR_MEM8(0x09C1) -#define SPID_STATUS _SFR_MEM8(0x09C2) -#define SPID_DATA _SFR_MEM8(0x09C3) - -/* TC0 - 16-bit Timer/Counter 0 */ -#define TCE0_CTRLA _SFR_MEM8(0x0A00) -#define TCE0_CTRLB _SFR_MEM8(0x0A01) -#define TCE0_CTRLC _SFR_MEM8(0x0A02) -#define TCE0_CTRLD _SFR_MEM8(0x0A03) -#define TCE0_CTRLE _SFR_MEM8(0x0A04) -#define TCE0_INTCTRLA _SFR_MEM8(0x0A06) -#define TCE0_INTCTRLB _SFR_MEM8(0x0A07) -#define TCE0_CTRLFCLR _SFR_MEM8(0x0A08) -#define TCE0_CTRLFSET _SFR_MEM8(0x0A09) -#define TCE0_CTRLGCLR _SFR_MEM8(0x0A0A) -#define TCE0_CTRLGSET _SFR_MEM8(0x0A0B) -#define TCE0_INTFLAGS _SFR_MEM8(0x0A0C) -#define TCE0_TEMP _SFR_MEM8(0x0A0F) -#define TCE0_CNT _SFR_MEM16(0x0A20) -#define TCE0_PER _SFR_MEM16(0x0A26) -#define TCE0_CCA _SFR_MEM16(0x0A28) -#define TCE0_CCB _SFR_MEM16(0x0A2A) -#define TCE0_CCC _SFR_MEM16(0x0A2C) -#define TCE0_CCD _SFR_MEM16(0x0A2E) -#define TCE0_PERBUF _SFR_MEM16(0x0A36) -#define TCE0_CCABUF _SFR_MEM16(0x0A38) -#define TCE0_CCBBUF _SFR_MEM16(0x0A3A) -#define TCE0_CCCBUF _SFR_MEM16(0x0A3C) -#define TCE0_CCDBUF _SFR_MEM16(0x0A3E) - -/* TC2 - 16-bit Timer/Counter type 2 */ -#define TCE2_CTRLA _SFR_MEM8(0x0A00) -#define TCE2_CTRLB _SFR_MEM8(0x0A01) -#define TCE2_CTRLC _SFR_MEM8(0x0A02) -#define TCE2_CTRLE _SFR_MEM8(0x0A04) -#define TCE2_INTCTRLA _SFR_MEM8(0x0A06) -#define TCE2_INTCTRLB _SFR_MEM8(0x0A07) -#define TCE2_CTRLF _SFR_MEM8(0x0A09) -#define TCE2_INTFLAGS _SFR_MEM8(0x0A0C) -#define TCE2_LCNT _SFR_MEM8(0x0A20) -#define TCE2_HCNT _SFR_MEM8(0x0A21) -#define TCE2_LPER _SFR_MEM8(0x0A26) -#define TCE2_HPER _SFR_MEM8(0x0A27) -#define TCE2_LCMPA _SFR_MEM8(0x0A28) -#define TCE2_HCMPA _SFR_MEM8(0x0A29) -#define TCE2_LCMPB _SFR_MEM8(0x0A2A) -#define TCE2_HCMPB _SFR_MEM8(0x0A2B) -#define TCE2_LCMPC _SFR_MEM8(0x0A2C) -#define TCE2_HCMPC _SFR_MEM8(0x0A2D) -#define TCE2_LCMPD _SFR_MEM8(0x0A2E) -#define TCE2_HCMPD _SFR_MEM8(0x0A2F) - -/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ -#define USARTE0_DATA _SFR_MEM8(0x0AA0) -#define USARTE0_STATUS _SFR_MEM8(0x0AA1) -#define USARTE0_CTRLA _SFR_MEM8(0x0AA3) -#define USARTE0_CTRLB _SFR_MEM8(0x0AA4) -#define USARTE0_CTRLC _SFR_MEM8(0x0AA5) -#define USARTE0_BAUDCTRLA _SFR_MEM8(0x0AA6) -#define USARTE0_BAUDCTRLB _SFR_MEM8(0x0AA7) - -/* TC0 - 16-bit Timer/Counter 0 */ -#define TCF0_CTRLA _SFR_MEM8(0x0B00) -#define TCF0_CTRLB _SFR_MEM8(0x0B01) -#define TCF0_CTRLC _SFR_MEM8(0x0B02) -#define TCF0_CTRLD _SFR_MEM8(0x0B03) -#define TCF0_CTRLE _SFR_MEM8(0x0B04) -#define TCF0_INTCTRLA _SFR_MEM8(0x0B06) -#define TCF0_INTCTRLB _SFR_MEM8(0x0B07) -#define TCF0_CTRLFCLR _SFR_MEM8(0x0B08) -#define TCF0_CTRLFSET _SFR_MEM8(0x0B09) -#define TCF0_CTRLGCLR _SFR_MEM8(0x0B0A) -#define TCF0_CTRLGSET _SFR_MEM8(0x0B0B) -#define TCF0_INTFLAGS _SFR_MEM8(0x0B0C) -#define TCF0_TEMP _SFR_MEM8(0x0B0F) -#define TCF0_CNT _SFR_MEM16(0x0B20) -#define TCF0_PER _SFR_MEM16(0x0B26) -#define TCF0_CCA _SFR_MEM16(0x0B28) -#define TCF0_CCB _SFR_MEM16(0x0B2A) -#define TCF0_CCC _SFR_MEM16(0x0B2C) -#define TCF0_CCD _SFR_MEM16(0x0B2E) -#define TCF0_PERBUF _SFR_MEM16(0x0B36) -#define TCF0_CCABUF _SFR_MEM16(0x0B38) -#define TCF0_CCBBUF _SFR_MEM16(0x0B3A) -#define TCF0_CCCBUF _SFR_MEM16(0x0B3C) -#define TCF0_CCDBUF _SFR_MEM16(0x0B3E) - -/* TC2 - 16-bit Timer/Counter type 2 */ -#define TCF2_CTRLA _SFR_MEM8(0x0B00) -#define TCF2_CTRLB _SFR_MEM8(0x0B01) -#define TCF2_CTRLC _SFR_MEM8(0x0B02) -#define TCF2_CTRLE _SFR_MEM8(0x0B04) -#define TCF2_INTCTRLA _SFR_MEM8(0x0B06) -#define TCF2_INTCTRLB _SFR_MEM8(0x0B07) -#define TCF2_CTRLF _SFR_MEM8(0x0B09) -#define TCF2_INTFLAGS _SFR_MEM8(0x0B0C) -#define TCF2_LCNT _SFR_MEM8(0x0B20) -#define TCF2_HCNT _SFR_MEM8(0x0B21) -#define TCF2_LPER _SFR_MEM8(0x0B26) -#define TCF2_HPER _SFR_MEM8(0x0B27) -#define TCF2_LCMPA _SFR_MEM8(0x0B28) -#define TCF2_HCMPA _SFR_MEM8(0x0B29) -#define TCF2_LCMPB _SFR_MEM8(0x0B2A) -#define TCF2_HCMPB _SFR_MEM8(0x0B2B) -#define TCF2_LCMPC _SFR_MEM8(0x0B2C) -#define TCF2_HCMPC _SFR_MEM8(0x0B2D) -#define TCF2_LCMPD _SFR_MEM8(0x0B2E) -#define TCF2_HCMPD _SFR_MEM8(0x0B2F) - - - -/*================== Bitfield Definitions ================== */ - -/* VPORT - Virtual Ports */ -/* VPORT.INTFLAGS bit masks and bit positions */ -#define VPORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ -#define VPORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ - -#define VPORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ -#define VPORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ - -/* XOCD - On-Chip Debug System */ -/* OCD.OCDR0 bit masks and bit positions */ -#define OCD_OCDRD_gm 0xFF /* OCDR Dirty group mask. */ -#define OCD_OCDRD_gp 0 /* OCDR Dirty group position. */ -#define OCD_OCDRD0_bm (1<<0) /* OCDR Dirty bit 0 mask. */ -#define OCD_OCDRD0_bp 0 /* OCDR Dirty bit 0 position. */ -#define OCD_OCDRD1_bm (1<<1) /* OCDR Dirty bit 1 mask. */ -#define OCD_OCDRD1_bp 1 /* OCDR Dirty bit 1 position. */ -#define OCD_OCDRD2_bm (1<<2) /* OCDR Dirty bit 2 mask. */ -#define OCD_OCDRD2_bp 2 /* OCDR Dirty bit 2 position. */ -#define OCD_OCDRD3_bm (1<<3) /* OCDR Dirty bit 3 mask. */ -#define OCD_OCDRD3_bp 3 /* OCDR Dirty bit 3 position. */ -#define OCD_OCDRD4_bm (1<<4) /* OCDR Dirty bit 4 mask. */ -#define OCD_OCDRD4_bp 4 /* OCDR Dirty bit 4 position. */ -#define OCD_OCDRD5_bm (1<<5) /* OCDR Dirty bit 5 mask. */ -#define OCD_OCDRD5_bp 5 /* OCDR Dirty bit 5 position. */ -#define OCD_OCDRD6_bm (1<<6) /* OCDR Dirty bit 6 mask. */ -#define OCD_OCDRD6_bp 6 /* OCDR Dirty bit 6 position. */ -#define OCD_OCDRD7_bm (1<<7) /* OCDR Dirty bit 7 mask. */ -#define OCD_OCDRD7_bp 7 /* OCDR Dirty bit 7 position. */ - -/* OCD.OCDR1 bit masks and bit positions */ -/* OCD_OCDRD Predefined. */ -/* OCD_OCDRD Predefined. */ - -/* CPU - CPU */ -/* CPU.CCP bit masks and bit positions */ -#define CPU_CCP_gm 0xFF /* CCP signature group mask. */ -#define CPU_CCP_gp 0 /* CCP signature group position. */ -#define CPU_CCP0_bm (1<<0) /* CCP signature bit 0 mask. */ -#define CPU_CCP0_bp 0 /* CCP signature bit 0 position. */ -#define CPU_CCP1_bm (1<<1) /* CCP signature bit 1 mask. */ -#define CPU_CCP1_bp 1 /* CCP signature bit 1 position. */ -#define CPU_CCP2_bm (1<<2) /* CCP signature bit 2 mask. */ -#define CPU_CCP2_bp 2 /* CCP signature bit 2 position. */ -#define CPU_CCP3_bm (1<<3) /* CCP signature bit 3 mask. */ -#define CPU_CCP3_bp 3 /* CCP signature bit 3 position. */ -#define CPU_CCP4_bm (1<<4) /* CCP signature bit 4 mask. */ -#define CPU_CCP4_bp 4 /* CCP signature bit 4 position. */ -#define CPU_CCP5_bm (1<<5) /* CCP signature bit 5 mask. */ -#define CPU_CCP5_bp 5 /* CCP signature bit 5 position. */ -#define CPU_CCP6_bm (1<<6) /* CCP signature bit 6 mask. */ -#define CPU_CCP6_bp 6 /* CCP signature bit 6 position. */ -#define CPU_CCP7_bm (1<<7) /* CCP signature bit 7 mask. */ -#define CPU_CCP7_bp 7 /* CCP signature bit 7 position. */ - -/* CPU.SREG bit masks and bit positions */ -#define CPU_I_bm 0x80 /* Global Interrupt Enable Flag bit mask. */ -#define CPU_I_bp 7 /* Global Interrupt Enable Flag bit position. */ - -#define CPU_T_bm 0x40 /* Transfer Bit bit mask. */ -#define CPU_T_bp 6 /* Transfer Bit bit position. */ - -#define CPU_H_bm 0x20 /* Half Carry Flag bit mask. */ -#define CPU_H_bp 5 /* Half Carry Flag bit position. */ - -#define CPU_S_bm 0x10 /* N Exclusive Or V Flag bit mask. */ -#define CPU_S_bp 4 /* N Exclusive Or V Flag bit position. */ - -#define CPU_V_bm 0x08 /* Two's Complement Overflow Flag bit mask. */ -#define CPU_V_bp 3 /* Two's Complement Overflow Flag bit position. */ - -#define CPU_N_bm 0x04 /* Negative Flag bit mask. */ -#define CPU_N_bp 2 /* Negative Flag bit position. */ - -#define CPU_Z_bm 0x02 /* Zero Flag bit mask. */ -#define CPU_Z_bp 1 /* Zero Flag bit position. */ - -#define CPU_C_bm 0x01 /* Carry Flag bit mask. */ -#define CPU_C_bp 0 /* Carry Flag bit position. */ - -/* CLK - Clock System */ -/* CLK.CTRL bit masks and bit positions */ -#define CLK_SCLKSEL_gm 0x07 /* System Clock Selection group mask. */ -#define CLK_SCLKSEL_gp 0 /* System Clock Selection group position. */ -#define CLK_SCLKSEL0_bm (1<<0) /* System Clock Selection bit 0 mask. */ -#define CLK_SCLKSEL0_bp 0 /* System Clock Selection bit 0 position. */ -#define CLK_SCLKSEL1_bm (1<<1) /* System Clock Selection bit 1 mask. */ -#define CLK_SCLKSEL1_bp 1 /* System Clock Selection bit 1 position. */ -#define CLK_SCLKSEL2_bm (1<<2) /* System Clock Selection bit 2 mask. */ -#define CLK_SCLKSEL2_bp 2 /* System Clock Selection bit 2 position. */ - -/* CLK.PSCTRL bit masks and bit positions */ -#define CLK_PSADIV_gm 0x7C /* Prescaler A Division Factor group mask. */ -#define CLK_PSADIV_gp 2 /* Prescaler A Division Factor group position. */ -#define CLK_PSADIV0_bm (1<<2) /* Prescaler A Division Factor bit 0 mask. */ -#define CLK_PSADIV0_bp 2 /* Prescaler A Division Factor bit 0 position. */ -#define CLK_PSADIV1_bm (1<<3) /* Prescaler A Division Factor bit 1 mask. */ -#define CLK_PSADIV1_bp 3 /* Prescaler A Division Factor bit 1 position. */ -#define CLK_PSADIV2_bm (1<<4) /* Prescaler A Division Factor bit 2 mask. */ -#define CLK_PSADIV2_bp 4 /* Prescaler A Division Factor bit 2 position. */ -#define CLK_PSADIV3_bm (1<<5) /* Prescaler A Division Factor bit 3 mask. */ -#define CLK_PSADIV3_bp 5 /* Prescaler A Division Factor bit 3 position. */ -#define CLK_PSADIV4_bm (1<<6) /* Prescaler A Division Factor bit 4 mask. */ -#define CLK_PSADIV4_bp 6 /* Prescaler A Division Factor bit 4 position. */ - -#define CLK_PSBCDIV_gm 0x03 /* Prescaler B and C Division factor group mask. */ -#define CLK_PSBCDIV_gp 0 /* Prescaler B and C Division factor group position. */ -#define CLK_PSBCDIV0_bm (1<<0) /* Prescaler B and C Division factor bit 0 mask. */ -#define CLK_PSBCDIV0_bp 0 /* Prescaler B and C Division factor bit 0 position. */ -#define CLK_PSBCDIV1_bm (1<<1) /* Prescaler B and C Division factor bit 1 mask. */ -#define CLK_PSBCDIV1_bp 1 /* Prescaler B and C Division factor bit 1 position. */ - -/* CLK.LOCK bit masks and bit positions */ -#define CLK_LOCK_bm 0x01 /* Clock System Lock bit mask. */ -#define CLK_LOCK_bp 0 /* Clock System Lock bit position. */ - -/* CLK.RTCCTRL bit masks and bit positions */ -#define CLK_RTCSRC_gm 0x0E /* Clock Source group mask. */ -#define CLK_RTCSRC_gp 1 /* Clock Source group position. */ -#define CLK_RTCSRC0_bm (1<<1) /* Clock Source bit 0 mask. */ -#define CLK_RTCSRC0_bp 1 /* Clock Source bit 0 position. */ -#define CLK_RTCSRC1_bm (1<<2) /* Clock Source bit 1 mask. */ -#define CLK_RTCSRC1_bp 2 /* Clock Source bit 1 position. */ -#define CLK_RTCSRC2_bm (1<<3) /* Clock Source bit 2 mask. */ -#define CLK_RTCSRC2_bp 3 /* Clock Source bit 2 position. */ - -#define CLK_RTCEN_bm 0x01 /* Clock Source Enable bit mask. */ -#define CLK_RTCEN_bp 0 /* Clock Source Enable bit position. */ - -/* CLK.USBCTRL bit masks and bit positions */ -#define CLK_USBPSDIV_gm 0x38 /* Prescaler Division Factor group mask. */ -#define CLK_USBPSDIV_gp 3 /* Prescaler Division Factor group position. */ -#define CLK_USBPSDIV0_bm (1<<3) /* Prescaler Division Factor bit 0 mask. */ -#define CLK_USBPSDIV0_bp 3 /* Prescaler Division Factor bit 0 position. */ -#define CLK_USBPSDIV1_bm (1<<4) /* Prescaler Division Factor bit 1 mask. */ -#define CLK_USBPSDIV1_bp 4 /* Prescaler Division Factor bit 1 position. */ -#define CLK_USBPSDIV2_bm (1<<5) /* Prescaler Division Factor bit 2 mask. */ -#define CLK_USBPSDIV2_bp 5 /* Prescaler Division Factor bit 2 position. */ - -#define CLK_USBSRC_gm 0x06 /* Clock Source group mask. */ -#define CLK_USBSRC_gp 1 /* Clock Source group position. */ -#define CLK_USBSRC0_bm (1<<1) /* Clock Source bit 0 mask. */ -#define CLK_USBSRC0_bp 1 /* Clock Source bit 0 position. */ -#define CLK_USBSRC1_bm (1<<2) /* Clock Source bit 1 mask. */ -#define CLK_USBSRC1_bp 2 /* Clock Source bit 1 position. */ - -#define CLK_USBSEN_bm 0x01 /* Clock Source Enable bit mask. */ -#define CLK_USBSEN_bp 0 /* Clock Source Enable bit position. */ - -/* PR.PRGEN bit masks and bit positions */ -#define PR_USB_bm 0x40 /* USB bit mask. */ -#define PR_USB_bp 6 /* USB bit position. */ - -#define PR_AES_bm 0x10 /* AES bit mask. */ -#define PR_AES_bp 4 /* AES bit position. */ - -#define PR_RTC_bm 0x04 /* Real-time Counter bit mask. */ -#define PR_RTC_bp 2 /* Real-time Counter bit position. */ - -#define PR_EVSYS_bm 0x02 /* Event System bit mask. */ -#define PR_EVSYS_bp 1 /* Event System bit position. */ - -#define PR_DMA_bm 0x01 /* DMA-Controller bit mask. */ -#define PR_DMA_bp 0 /* DMA-Controller bit position. */ - -/* PR.PRPA bit masks and bit positions */ -#define PR_ADC_bm 0x02 /* Port A ADC bit mask. */ -#define PR_ADC_bp 1 /* Port A ADC bit position. */ - -#define PR_AC_bm 0x01 /* Port A Analog Comparator bit mask. */ -#define PR_AC_bp 0 /* Port A Analog Comparator bit position. */ - -/* PR.PRPC bit masks and bit positions */ -#define PR_TWI_bm 0x40 /* Port C Two-wire Interface bit mask. */ -#define PR_TWI_bp 6 /* Port C Two-wire Interface bit position. */ - -#define PR_USART1_bm 0x20 /* Port C USART1 bit mask. */ -#define PR_USART1_bp 5 /* Port C USART1 bit position. */ - -#define PR_USART0_bm 0x10 /* Port C USART0 bit mask. */ -#define PR_USART0_bp 4 /* Port C USART0 bit position. */ - -#define PR_SPI_bm 0x08 /* Port C SPI bit mask. */ -#define PR_SPI_bp 3 /* Port C SPI bit position. */ - -#define PR_HIRES_bm 0x04 /* Port C AWEX bit mask. */ -#define PR_HIRES_bp 2 /* Port C AWEX bit position. */ - -#define PR_TC1_bm 0x02 /* Port C Timer/Counter1 bit mask. */ -#define PR_TC1_bp 1 /* Port C Timer/Counter1 bit position. */ - -#define PR_TC0_bm 0x01 /* Port C Timer/Counter0 bit mask. */ -#define PR_TC0_bp 0 /* Port C Timer/Counter0 bit position. */ - -/* PR.PRPD bit masks and bit positions */ -/* PR_USART0 Predefined. */ -/* PR_USART0 Predefined. */ - -/* PR_SPI Predefined. */ -/* PR_SPI Predefined. */ - -/* PR_TC0 Predefined. */ -/* PR_TC0 Predefined. */ - -/* PR.PRPE bit masks and bit positions */ -/* PR_TWI Predefined. */ -/* PR_TWI Predefined. */ - -/* PR_USART0 Predefined. */ -/* PR_USART0 Predefined. */ - -/* PR_TC0 Predefined. */ -/* PR_TC0 Predefined. */ - -/* PR.PRPF bit masks and bit positions */ -/* PR_USART0 Predefined. */ -/* PR_USART0 Predefined. */ - -/* PR_TC0 Predefined. */ -/* PR_TC0 Predefined. */ - -/* SLEEP - Sleep Controller */ -/* SLEEP.CTRL bit masks and bit positions */ -#define SLEEP_SMODE_gm 0x0E /* Sleep Mode group mask. */ -#define SLEEP_SMODE_gp 1 /* Sleep Mode group position. */ -#define SLEEP_SMODE0_bm (1<<1) /* Sleep Mode bit 0 mask. */ -#define SLEEP_SMODE0_bp 1 /* Sleep Mode bit 0 position. */ -#define SLEEP_SMODE1_bm (1<<2) /* Sleep Mode bit 1 mask. */ -#define SLEEP_SMODE1_bp 2 /* Sleep Mode bit 1 position. */ -#define SLEEP_SMODE2_bm (1<<3) /* Sleep Mode bit 2 mask. */ -#define SLEEP_SMODE2_bp 3 /* Sleep Mode bit 2 position. */ - -#define SLEEP_SEN_bm 0x01 /* Sleep Enable bit mask. */ -#define SLEEP_SEN_bp 0 /* Sleep Enable bit position. */ - -/* OSC - Oscillator */ -/* OSC.CTRL bit masks and bit positions */ -#define OSC_PLLEN_bm 0x10 /* PLL Enable bit mask. */ -#define OSC_PLLEN_bp 4 /* PLL Enable bit position. */ - -#define OSC_XOSCEN_bm 0x08 /* External Oscillator Enable bit mask. */ -#define OSC_XOSCEN_bp 3 /* External Oscillator Enable bit position. */ - -#define OSC_RC32KEN_bm 0x04 /* Internal 32.768 kHz RC Oscillator Enable bit mask. */ -#define OSC_RC32KEN_bp 2 /* Internal 32.768 kHz RC Oscillator Enable bit position. */ - -#define OSC_RC32MEN_bm 0x02 /* Internal 32 MHz RC Oscillator Enable bit mask. */ -#define OSC_RC32MEN_bp 1 /* Internal 32 MHz RC Oscillator Enable bit position. */ - -#define OSC_RC2MEN_bm 0x01 /* Internal 2 MHz RC Oscillator Enable bit mask. */ -#define OSC_RC2MEN_bp 0 /* Internal 2 MHz RC Oscillator Enable bit position. */ - -/* OSC.STATUS bit masks and bit positions */ -#define OSC_PLLRDY_bm 0x10 /* PLL Ready bit mask. */ -#define OSC_PLLRDY_bp 4 /* PLL Ready bit position. */ - -#define OSC_XOSCRDY_bm 0x08 /* External Oscillator Ready bit mask. */ -#define OSC_XOSCRDY_bp 3 /* External Oscillator Ready bit position. */ - -#define OSC_RC32KRDY_bm 0x04 /* Internal 32.768 kHz RC Oscillator Ready bit mask. */ -#define OSC_RC32KRDY_bp 2 /* Internal 32.768 kHz RC Oscillator Ready bit position. */ - -#define OSC_RC32MRDY_bm 0x02 /* Internal 32 MHz RC Oscillator Ready bit mask. */ -#define OSC_RC32MRDY_bp 1 /* Internal 32 MHz RC Oscillator Ready bit position. */ - -#define OSC_RC2MRDY_bm 0x01 /* Internal 2 MHz RC Oscillator Ready bit mask. */ -#define OSC_RC2MRDY_bp 0 /* Internal 2 MHz RC Oscillator Ready bit position. */ - -/* OSC.XOSCCTRL bit masks and bit positions */ -#define OSC_FRQRANGE_gm 0xC0 /* Frequency Range group mask. */ -#define OSC_FRQRANGE_gp 6 /* Frequency Range group position. */ -#define OSC_FRQRANGE0_bm (1<<6) /* Frequency Range bit 0 mask. */ -#define OSC_FRQRANGE0_bp 6 /* Frequency Range bit 0 position. */ -#define OSC_FRQRANGE1_bm (1<<7) /* Frequency Range bit 1 mask. */ -#define OSC_FRQRANGE1_bp 7 /* Frequency Range bit 1 position. */ - -#define OSC_X32KLPM_bm 0x20 /* 32.768 kHz XTAL OSC Low-power Mode bit mask. */ -#define OSC_X32KLPM_bp 5 /* 32.768 kHz XTAL OSC Low-power Mode bit position. */ - -#define OSC_XOSCPWR_bm 0x10 /* 16 MHz Crystal Oscillator High Power mode bit mask. */ -#define OSC_XOSCPWR_bp 4 /* 16 MHz Crystal Oscillator High Power mode bit position. */ - -#define OSC_XOSCSEL_gm 0x0F /* External Oscillator Selection and Startup Time group mask. */ -#define OSC_XOSCSEL_gp 0 /* External Oscillator Selection and Startup Time group position. */ -#define OSC_XOSCSEL0_bm (1<<0) /* External Oscillator Selection and Startup Time bit 0 mask. */ -#define OSC_XOSCSEL0_bp 0 /* External Oscillator Selection and Startup Time bit 0 position. */ -#define OSC_XOSCSEL1_bm (1<<1) /* External Oscillator Selection and Startup Time bit 1 mask. */ -#define OSC_XOSCSEL1_bp 1 /* External Oscillator Selection and Startup Time bit 1 position. */ -#define OSC_XOSCSEL2_bm (1<<2) /* External Oscillator Selection and Startup Time bit 2 mask. */ -#define OSC_XOSCSEL2_bp 2 /* External Oscillator Selection and Startup Time bit 2 position. */ -#define OSC_XOSCSEL3_bm (1<<3) /* External Oscillator Selection and Startup Time bit 3 mask. */ -#define OSC_XOSCSEL3_bp 3 /* External Oscillator Selection and Startup Time bit 3 position. */ - -/* OSC.XOSCFAIL bit masks and bit positions */ -#define OSC_PLLFDIF_bm 0x08 /* PLL Failure Detection Interrupt Flag bit mask. */ -#define OSC_PLLFDIF_bp 3 /* PLL Failure Detection Interrupt Flag bit position. */ - -#define OSC_PLLFDEN_bm 0x04 /* PLL Failure Detection Enable bit mask. */ -#define OSC_PLLFDEN_bp 2 /* PLL Failure Detection Enable bit position. */ - -#define OSC_XOSCFDIF_bm 0x02 /* XOSC Failure Detection Interrupt Flag bit mask. */ -#define OSC_XOSCFDIF_bp 1 /* XOSC Failure Detection Interrupt Flag bit position. */ - -#define OSC_XOSCFDEN_bm 0x01 /* XOSC Failure Detection Enable bit mask. */ -#define OSC_XOSCFDEN_bp 0 /* XOSC Failure Detection Enable bit position. */ - -/* OSC.PLLCTRL bit masks and bit positions */ -#define OSC_PLLSRC_gm 0xC0 /* Clock Source group mask. */ -#define OSC_PLLSRC_gp 6 /* Clock Source group position. */ -#define OSC_PLLSRC0_bm (1<<6) /* Clock Source bit 0 mask. */ -#define OSC_PLLSRC0_bp 6 /* Clock Source bit 0 position. */ -#define OSC_PLLSRC1_bm (1<<7) /* Clock Source bit 1 mask. */ -#define OSC_PLLSRC1_bp 7 /* Clock Source bit 1 position. */ - -#define OSC_PLLDIV_bm 0x20 /* Divide by 2 bit mask. */ -#define OSC_PLLDIV_bp 5 /* Divide by 2 bit position. */ - -#define OSC_PLLFAC_gm 0x1F /* Multiplication Factor group mask. */ -#define OSC_PLLFAC_gp 0 /* Multiplication Factor group position. */ -#define OSC_PLLFAC0_bm (1<<0) /* Multiplication Factor bit 0 mask. */ -#define OSC_PLLFAC0_bp 0 /* Multiplication Factor bit 0 position. */ -#define OSC_PLLFAC1_bm (1<<1) /* Multiplication Factor bit 1 mask. */ -#define OSC_PLLFAC1_bp 1 /* Multiplication Factor bit 1 position. */ -#define OSC_PLLFAC2_bm (1<<2) /* Multiplication Factor bit 2 mask. */ -#define OSC_PLLFAC2_bp 2 /* Multiplication Factor bit 2 position. */ -#define OSC_PLLFAC3_bm (1<<3) /* Multiplication Factor bit 3 mask. */ -#define OSC_PLLFAC3_bp 3 /* Multiplication Factor bit 3 position. */ -#define OSC_PLLFAC4_bm (1<<4) /* Multiplication Factor bit 4 mask. */ -#define OSC_PLLFAC4_bp 4 /* Multiplication Factor bit 4 position. */ - -/* OSC.DFLLCTRL bit masks and bit positions */ -#define OSC_RC32MCREF_gm 0x06 /* 32 MHz DFLL Calibration Reference group mask. */ -#define OSC_RC32MCREF_gp 1 /* 32 MHz DFLL Calibration Reference group position. */ -#define OSC_RC32MCREF0_bm (1<<1) /* 32 MHz DFLL Calibration Reference bit 0 mask. */ -#define OSC_RC32MCREF0_bp 1 /* 32 MHz DFLL Calibration Reference bit 0 position. */ -#define OSC_RC32MCREF1_bm (1<<2) /* 32 MHz DFLL Calibration Reference bit 1 mask. */ -#define OSC_RC32MCREF1_bp 2 /* 32 MHz DFLL Calibration Reference bit 1 position. */ - -#define OSC_RC2MCREF_bm 0x01 /* 2 MHz DFLL Calibration Reference bit mask. */ -#define OSC_RC2MCREF_bp 0 /* 2 MHz DFLL Calibration Reference bit position. */ - -/* DFLL - DFLL */ -/* DFLL.CTRL bit masks and bit positions */ -#define DFLL_ENABLE_bm 0x01 /* DFLL Enable bit mask. */ -#define DFLL_ENABLE_bp 0 /* DFLL Enable bit position. */ - -/* DFLL.CALA bit masks and bit positions */ -#define DFLL_CALL_gm 0x7F /* DFLL Calibration Value A group mask. */ -#define DFLL_CALL_gp 0 /* DFLL Calibration Value A group position. */ -#define DFLL_CALL0_bm (1<<0) /* DFLL Calibration Value A bit 0 mask. */ -#define DFLL_CALL0_bp 0 /* DFLL Calibration Value A bit 0 position. */ -#define DFLL_CALL1_bm (1<<1) /* DFLL Calibration Value A bit 1 mask. */ -#define DFLL_CALL1_bp 1 /* DFLL Calibration Value A bit 1 position. */ -#define DFLL_CALL2_bm (1<<2) /* DFLL Calibration Value A bit 2 mask. */ -#define DFLL_CALL2_bp 2 /* DFLL Calibration Value A bit 2 position. */ -#define DFLL_CALL3_bm (1<<3) /* DFLL Calibration Value A bit 3 mask. */ -#define DFLL_CALL3_bp 3 /* DFLL Calibration Value A bit 3 position. */ -#define DFLL_CALL4_bm (1<<4) /* DFLL Calibration Value A bit 4 mask. */ -#define DFLL_CALL4_bp 4 /* DFLL Calibration Value A bit 4 position. */ -#define DFLL_CALL5_bm (1<<5) /* DFLL Calibration Value A bit 5 mask. */ -#define DFLL_CALL5_bp 5 /* DFLL Calibration Value A bit 5 position. */ -#define DFLL_CALL6_bm (1<<6) /* DFLL Calibration Value A bit 6 mask. */ -#define DFLL_CALL6_bp 6 /* DFLL Calibration Value A bit 6 position. */ - -/* DFLL.CALB bit masks and bit positions */ -#define DFLL_CALH_gm 0x3F /* DFLL Calibration Value B group mask. */ -#define DFLL_CALH_gp 0 /* DFLL Calibration Value B group position. */ -#define DFLL_CALH0_bm (1<<0) /* DFLL Calibration Value B bit 0 mask. */ -#define DFLL_CALH0_bp 0 /* DFLL Calibration Value B bit 0 position. */ -#define DFLL_CALH1_bm (1<<1) /* DFLL Calibration Value B bit 1 mask. */ -#define DFLL_CALH1_bp 1 /* DFLL Calibration Value B bit 1 position. */ -#define DFLL_CALH2_bm (1<<2) /* DFLL Calibration Value B bit 2 mask. */ -#define DFLL_CALH2_bp 2 /* DFLL Calibration Value B bit 2 position. */ -#define DFLL_CALH3_bm (1<<3) /* DFLL Calibration Value B bit 3 mask. */ -#define DFLL_CALH3_bp 3 /* DFLL Calibration Value B bit 3 position. */ -#define DFLL_CALH4_bm (1<<4) /* DFLL Calibration Value B bit 4 mask. */ -#define DFLL_CALH4_bp 4 /* DFLL Calibration Value B bit 4 position. */ -#define DFLL_CALH5_bm (1<<5) /* DFLL Calibration Value B bit 5 mask. */ -#define DFLL_CALH5_bp 5 /* DFLL Calibration Value B bit 5 position. */ - -/* RST - Reset */ -/* RST.STATUS bit masks and bit positions */ -#define RST_SDRF_bm 0x40 /* Spike Detection Reset Flag bit mask. */ -#define RST_SDRF_bp 6 /* Spike Detection Reset Flag bit position. */ - -#define RST_SRF_bm 0x20 /* Software Reset Flag bit mask. */ -#define RST_SRF_bp 5 /* Software Reset Flag bit position. */ - -#define RST_PDIRF_bm 0x10 /* Programming and Debug Interface Interface Reset Flag bit mask. */ -#define RST_PDIRF_bp 4 /* Programming and Debug Interface Interface Reset Flag bit position. */ - -#define RST_WDRF_bm 0x08 /* Watchdog Reset Flag bit mask. */ -#define RST_WDRF_bp 3 /* Watchdog Reset Flag bit position. */ - -#define RST_BORF_bm 0x04 /* Brown-out Reset Flag bit mask. */ -#define RST_BORF_bp 2 /* Brown-out Reset Flag bit position. */ - -#define RST_EXTRF_bm 0x02 /* External Reset Flag bit mask. */ -#define RST_EXTRF_bp 1 /* External Reset Flag bit position. */ - -#define RST_PORF_bm 0x01 /* Power-on Reset Flag bit mask. */ -#define RST_PORF_bp 0 /* Power-on Reset Flag bit position. */ - -/* RST.CTRL bit masks and bit positions */ -#define RST_SWRST_bm 0x01 /* Software Reset bit mask. */ -#define RST_SWRST_bp 0 /* Software Reset bit position. */ - -/* WDT - Watch-Dog Timer */ -/* WDT.CTRL bit masks and bit positions */ -#define WDT_PER_gm 0x3C /* Period group mask. */ -#define WDT_PER_gp 2 /* Period group position. */ -#define WDT_PER0_bm (1<<2) /* Period bit 0 mask. */ -#define WDT_PER0_bp 2 /* Period bit 0 position. */ -#define WDT_PER1_bm (1<<3) /* Period bit 1 mask. */ -#define WDT_PER1_bp 3 /* Period bit 1 position. */ -#define WDT_PER2_bm (1<<4) /* Period bit 2 mask. */ -#define WDT_PER2_bp 4 /* Period bit 2 position. */ -#define WDT_PER3_bm (1<<5) /* Period bit 3 mask. */ -#define WDT_PER3_bp 5 /* Period bit 3 position. */ - -#define WDT_ENABLE_bm 0x02 /* Enable bit mask. */ -#define WDT_ENABLE_bp 1 /* Enable bit position. */ - -#define WDT_CEN_bm 0x01 /* Change Enable bit mask. */ -#define WDT_CEN_bp 0 /* Change Enable bit position. */ - -/* WDT.WINCTRL bit masks and bit positions */ -#define WDT_WPER_gm 0x3C /* Windowed Mode Period group mask. */ -#define WDT_WPER_gp 2 /* Windowed Mode Period group position. */ -#define WDT_WPER0_bm (1<<2) /* Windowed Mode Period bit 0 mask. */ -#define WDT_WPER0_bp 2 /* Windowed Mode Period bit 0 position. */ -#define WDT_WPER1_bm (1<<3) /* Windowed Mode Period bit 1 mask. */ -#define WDT_WPER1_bp 3 /* Windowed Mode Period bit 1 position. */ -#define WDT_WPER2_bm (1<<4) /* Windowed Mode Period bit 2 mask. */ -#define WDT_WPER2_bp 4 /* Windowed Mode Period bit 2 position. */ -#define WDT_WPER3_bm (1<<5) /* Windowed Mode Period bit 3 mask. */ -#define WDT_WPER3_bp 5 /* Windowed Mode Period bit 3 position. */ - -#define WDT_WEN_bm 0x02 /* Windowed Mode Enable bit mask. */ -#define WDT_WEN_bp 1 /* Windowed Mode Enable bit position. */ - -#define WDT_WCEN_bm 0x01 /* Windowed Mode Change Enable bit mask. */ -#define WDT_WCEN_bp 0 /* Windowed Mode Change Enable bit position. */ - -/* WDT.STATUS bit masks and bit positions */ -#define WDT_SYNCBUSY_bm 0x01 /* Syncronization busy bit mask. */ -#define WDT_SYNCBUSY_bp 0 /* Syncronization busy bit position. */ - -/* MCU - MCU Control */ -/* MCU.ANAINIT bit masks and bit positions */ -#define MCU_STARTUPDLYA_gm 0x03 /* Analog startup delay Port A group mask. */ -#define MCU_STARTUPDLYA_gp 0 /* Analog startup delay Port A group position. */ -#define MCU_STARTUPDLYA0_bm (1<<0) /* Analog startup delay Port A bit 0 mask. */ -#define MCU_STARTUPDLYA0_bp 0 /* Analog startup delay Port A bit 0 position. */ -#define MCU_STARTUPDLYA1_bm (1<<1) /* Analog startup delay Port A bit 1 mask. */ -#define MCU_STARTUPDLYA1_bp 1 /* Analog startup delay Port A bit 1 position. */ - -/* MCU.EVSYSLOCK bit masks and bit positions */ -#define MCU_EVSYS0LOCK_bm 0x01 /* Event Channel 0-3 Lock bit mask. */ -#define MCU_EVSYS0LOCK_bp 0 /* Event Channel 0-3 Lock bit position. */ - -/* MCU.AWEXLOCK bit masks and bit positions */ -#define MCU_AWEXCLOCK_bm 0x01 /* AWeX on T/C C0 Lock bit mask. */ -#define MCU_AWEXCLOCK_bp 0 /* AWeX on T/C C0 Lock bit position. */ - -/* PMIC - Programmable Multi-level Interrupt Controller */ -/* PMIC.STATUS bit masks and bit positions */ -#define PMIC_NMIEX_bm 0x80 /* Non-maskable Interrupt Executing bit mask. */ -#define PMIC_NMIEX_bp 7 /* Non-maskable Interrupt Executing bit position. */ - -#define PMIC_HILVLEX_bm 0x04 /* High Level Interrupt Executing bit mask. */ -#define PMIC_HILVLEX_bp 2 /* High Level Interrupt Executing bit position. */ - -#define PMIC_MEDLVLEX_bm 0x02 /* Medium Level Interrupt Executing bit mask. */ -#define PMIC_MEDLVLEX_bp 1 /* Medium Level Interrupt Executing bit position. */ - -#define PMIC_LOLVLEX_bm 0x01 /* Low Level Interrupt Executing bit mask. */ -#define PMIC_LOLVLEX_bp 0 /* Low Level Interrupt Executing bit position. */ - -/* PMIC.INTPRI bit masks and bit positions */ -#define PMIC_INTPRI_gm 0xFF /* Interrupt Priority group mask. */ -#define PMIC_INTPRI_gp 0 /* Interrupt Priority group position. */ -#define PMIC_INTPRI0_bm (1<<0) /* Interrupt Priority bit 0 mask. */ -#define PMIC_INTPRI0_bp 0 /* Interrupt Priority bit 0 position. */ -#define PMIC_INTPRI1_bm (1<<1) /* Interrupt Priority bit 1 mask. */ -#define PMIC_INTPRI1_bp 1 /* Interrupt Priority bit 1 position. */ -#define PMIC_INTPRI2_bm (1<<2) /* Interrupt Priority bit 2 mask. */ -#define PMIC_INTPRI2_bp 2 /* Interrupt Priority bit 2 position. */ -#define PMIC_INTPRI3_bm (1<<3) /* Interrupt Priority bit 3 mask. */ -#define PMIC_INTPRI3_bp 3 /* Interrupt Priority bit 3 position. */ -#define PMIC_INTPRI4_bm (1<<4) /* Interrupt Priority bit 4 mask. */ -#define PMIC_INTPRI4_bp 4 /* Interrupt Priority bit 4 position. */ -#define PMIC_INTPRI5_bm (1<<5) /* Interrupt Priority bit 5 mask. */ -#define PMIC_INTPRI5_bp 5 /* Interrupt Priority bit 5 position. */ -#define PMIC_INTPRI6_bm (1<<6) /* Interrupt Priority bit 6 mask. */ -#define PMIC_INTPRI6_bp 6 /* Interrupt Priority bit 6 position. */ -#define PMIC_INTPRI7_bm (1<<7) /* Interrupt Priority bit 7 mask. */ -#define PMIC_INTPRI7_bp 7 /* Interrupt Priority bit 7 position. */ - -/* PMIC.CTRL bit masks and bit positions */ -#define PMIC_RREN_bm 0x80 /* Round-Robin Priority Enable bit mask. */ -#define PMIC_RREN_bp 7 /* Round-Robin Priority Enable bit position. */ - -#define PMIC_IVSEL_bm 0x40 /* Interrupt Vector Select bit mask. */ -#define PMIC_IVSEL_bp 6 /* Interrupt Vector Select bit position. */ - -#define PMIC_HILVLEN_bm 0x04 /* High Level Enable bit mask. */ -#define PMIC_HILVLEN_bp 2 /* High Level Enable bit position. */ - -#define PMIC_MEDLVLEN_bm 0x02 /* Medium Level Enable bit mask. */ -#define PMIC_MEDLVLEN_bp 1 /* Medium Level Enable bit position. */ - -#define PMIC_LOLVLEN_bm 0x01 /* Low Level Enable bit mask. */ -#define PMIC_LOLVLEN_bp 0 /* Low Level Enable bit position. */ - -/* PORTCFG - Port Configuration */ -/* PORTCFG.VPCTRLA bit masks and bit positions */ -#define PORTCFG_VP1MAP_gm 0xF0 /* Virtual Port 1 Mapping group mask. */ -#define PORTCFG_VP1MAP_gp 4 /* Virtual Port 1 Mapping group position. */ -#define PORTCFG_VP1MAP0_bm (1<<4) /* Virtual Port 1 Mapping bit 0 mask. */ -#define PORTCFG_VP1MAP0_bp 4 /* Virtual Port 1 Mapping bit 0 position. */ -#define PORTCFG_VP1MAP1_bm (1<<5) /* Virtual Port 1 Mapping bit 1 mask. */ -#define PORTCFG_VP1MAP1_bp 5 /* Virtual Port 1 Mapping bit 1 position. */ -#define PORTCFG_VP1MAP2_bm (1<<6) /* Virtual Port 1 Mapping bit 2 mask. */ -#define PORTCFG_VP1MAP2_bp 6 /* Virtual Port 1 Mapping bit 2 position. */ -#define PORTCFG_VP1MAP3_bm (1<<7) /* Virtual Port 1 Mapping bit 3 mask. */ -#define PORTCFG_VP1MAP3_bp 7 /* Virtual Port 1 Mapping bit 3 position. */ - -#define PORTCFG_VP0MAP_gm 0x0F /* Virtual Port 0 Mapping group mask. */ -#define PORTCFG_VP0MAP_gp 0 /* Virtual Port 0 Mapping group position. */ -#define PORTCFG_VP0MAP0_bm (1<<0) /* Virtual Port 0 Mapping bit 0 mask. */ -#define PORTCFG_VP0MAP0_bp 0 /* Virtual Port 0 Mapping bit 0 position. */ -#define PORTCFG_VP0MAP1_bm (1<<1) /* Virtual Port 0 Mapping bit 1 mask. */ -#define PORTCFG_VP0MAP1_bp 1 /* Virtual Port 0 Mapping bit 1 position. */ -#define PORTCFG_VP0MAP2_bm (1<<2) /* Virtual Port 0 Mapping bit 2 mask. */ -#define PORTCFG_VP0MAP2_bp 2 /* Virtual Port 0 Mapping bit 2 position. */ -#define PORTCFG_VP0MAP3_bm (1<<3) /* Virtual Port 0 Mapping bit 3 mask. */ -#define PORTCFG_VP0MAP3_bp 3 /* Virtual Port 0 Mapping bit 3 position. */ - -/* PORTCFG.VPCTRLB bit masks and bit positions */ -#define PORTCFG_VP3MAP_gm 0xF0 /* Virtual Port 3 Mapping group mask. */ -#define PORTCFG_VP3MAP_gp 4 /* Virtual Port 3 Mapping group position. */ -#define PORTCFG_VP3MAP0_bm (1<<4) /* Virtual Port 3 Mapping bit 0 mask. */ -#define PORTCFG_VP3MAP0_bp 4 /* Virtual Port 3 Mapping bit 0 position. */ -#define PORTCFG_VP3MAP1_bm (1<<5) /* Virtual Port 3 Mapping bit 1 mask. */ -#define PORTCFG_VP3MAP1_bp 5 /* Virtual Port 3 Mapping bit 1 position. */ -#define PORTCFG_VP3MAP2_bm (1<<6) /* Virtual Port 3 Mapping bit 2 mask. */ -#define PORTCFG_VP3MAP2_bp 6 /* Virtual Port 3 Mapping bit 2 position. */ -#define PORTCFG_VP3MAP3_bm (1<<7) /* Virtual Port 3 Mapping bit 3 mask. */ -#define PORTCFG_VP3MAP3_bp 7 /* Virtual Port 3 Mapping bit 3 position. */ - -#define PORTCFG_VP2MAP_gm 0x0F /* Virtual Port 2 Mapping group mask. */ -#define PORTCFG_VP2MAP_gp 0 /* Virtual Port 2 Mapping group position. */ -#define PORTCFG_VP2MAP0_bm (1<<0) /* Virtual Port 2 Mapping bit 0 mask. */ -#define PORTCFG_VP2MAP0_bp 0 /* Virtual Port 2 Mapping bit 0 position. */ -#define PORTCFG_VP2MAP1_bm (1<<1) /* Virtual Port 2 Mapping bit 1 mask. */ -#define PORTCFG_VP2MAP1_bp 1 /* Virtual Port 2 Mapping bit 1 position. */ -#define PORTCFG_VP2MAP2_bm (1<<2) /* Virtual Port 2 Mapping bit 2 mask. */ -#define PORTCFG_VP2MAP2_bp 2 /* Virtual Port 2 Mapping bit 2 position. */ -#define PORTCFG_VP2MAP3_bm (1<<3) /* Virtual Port 2 Mapping bit 3 mask. */ -#define PORTCFG_VP2MAP3_bp 3 /* Virtual Port 2 Mapping bit 3 position. */ - -/* PORTCFG.CLKEVOUT bit masks and bit positions */ -#define PORTCFG_CLKOUT_gm 0x03 /* Peripheral Clock Output Port group mask. */ -#define PORTCFG_CLKOUT_gp 0 /* Peripheral Clock Output Port group position. */ -#define PORTCFG_CLKOUT0_bm (1<<0) /* Peripheral Clock Output Port bit 0 mask. */ -#define PORTCFG_CLKOUT0_bp 0 /* Peripheral Clock Output Port bit 0 position. */ -#define PORTCFG_CLKOUT1_bm (1<<1) /* Peripheral Clock Output Port bit 1 mask. */ -#define PORTCFG_CLKOUT1_bp 1 /* Peripheral Clock Output Port bit 1 position. */ - -#define PORTCFG_CLKOUTSEL_gm 0x0C /* Peripheral Clock Output Select group mask. */ -#define PORTCFG_CLKOUTSEL_gp 2 /* Peripheral Clock Output Select group position. */ -#define PORTCFG_CLKOUTSEL0_bm (1<<2) /* Peripheral Clock Output Select bit 0 mask. */ -#define PORTCFG_CLKOUTSEL0_bp 2 /* Peripheral Clock Output Select bit 0 position. */ -#define PORTCFG_CLKOUTSEL1_bm (1<<3) /* Peripheral Clock Output Select bit 1 mask. */ -#define PORTCFG_CLKOUTSEL1_bp 3 /* Peripheral Clock Output Select bit 1 position. */ - -#define PORTCFG_EVOUT_gm 0x30 /* Event Output Port group mask. */ -#define PORTCFG_EVOUT_gp 4 /* Event Output Port group position. */ -#define PORTCFG_EVOUT0_bm (1<<4) /* Event Output Port bit 0 mask. */ -#define PORTCFG_EVOUT0_bp 4 /* Event Output Port bit 0 position. */ -#define PORTCFG_EVOUT1_bm (1<<5) /* Event Output Port bit 1 mask. */ -#define PORTCFG_EVOUT1_bp 5 /* Event Output Port bit 1 position. */ - -#define PORTCFG_RTCOUT_bm 0x40 /* RTC Clock Output bit mask. */ -#define PORTCFG_RTCOUT_bp 6 /* RTC Clock Output bit position. */ - -#define PORTCFG_CLKEVPIN_bm 0x80 /* Peripheral Clock and Event Output pin Select bit mask. */ -#define PORTCFG_CLKEVPIN_bp 7 /* Peripheral Clock and Event Output pin Select bit position. */ - -/* PORTCFG.EVOUTSEL bit masks and bit positions */ -#define PORTCFG_EVOUTSEL_gm 0x07 /* Event Output Select group mask. */ -#define PORTCFG_EVOUTSEL_gp 0 /* Event Output Select group position. */ -#define PORTCFG_EVOUTSEL0_bm (1<<0) /* Event Output Select bit 0 mask. */ -#define PORTCFG_EVOUTSEL0_bp 0 /* Event Output Select bit 0 position. */ -#define PORTCFG_EVOUTSEL1_bm (1<<1) /* Event Output Select bit 1 mask. */ -#define PORTCFG_EVOUTSEL1_bp 1 /* Event Output Select bit 1 position. */ -#define PORTCFG_EVOUTSEL2_bm (1<<2) /* Event Output Select bit 2 mask. */ -#define PORTCFG_EVOUTSEL2_bp 2 /* Event Output Select bit 2 position. */ - -/* CRC - Cyclic Redundancy Checker */ -/* CRC.CTRL bit masks and bit positions */ -#define CRC_RESET_gm 0xC0 /* Reset group mask. */ -#define CRC_RESET_gp 6 /* Reset group position. */ -#define CRC_RESET0_bm (1<<6) /* Reset bit 0 mask. */ -#define CRC_RESET0_bp 6 /* Reset bit 0 position. */ -#define CRC_RESET1_bm (1<<7) /* Reset bit 1 mask. */ -#define CRC_RESET1_bp 7 /* Reset bit 1 position. */ - -#define CRC_CRC32_bm 0x20 /* CRC Mode bit mask. */ -#define CRC_CRC32_bp 5 /* CRC Mode bit position. */ - -#define CRC_SOURCE_gm 0x0F /* Input Source group mask. */ -#define CRC_SOURCE_gp 0 /* Input Source group position. */ -#define CRC_SOURCE0_bm (1<<0) /* Input Source bit 0 mask. */ -#define CRC_SOURCE0_bp 0 /* Input Source bit 0 position. */ -#define CRC_SOURCE1_bm (1<<1) /* Input Source bit 1 mask. */ -#define CRC_SOURCE1_bp 1 /* Input Source bit 1 position. */ -#define CRC_SOURCE2_bm (1<<2) /* Input Source bit 2 mask. */ -#define CRC_SOURCE2_bp 2 /* Input Source bit 2 position. */ -#define CRC_SOURCE3_bm (1<<3) /* Input Source bit 3 mask. */ -#define CRC_SOURCE3_bp 3 /* Input Source bit 3 position. */ - -/* CRC.STATUS bit masks and bit positions */ -#define CRC_ZERO_bm 0x02 /* Zero detection bit mask. */ -#define CRC_ZERO_bp 1 /* Zero detection bit position. */ - -#define CRC_BUSY_bm 0x01 /* Busy bit mask. */ -#define CRC_BUSY_bp 0 /* Busy bit position. */ - -/* EVSYS - Event System */ -/* EVSYS.CH0MUX bit masks and bit positions */ -#define EVSYS_CHMUX_gm 0xFF /* Event Channel 0 Multiplexer group mask. */ -#define EVSYS_CHMUX_gp 0 /* Event Channel 0 Multiplexer group position. */ -#define EVSYS_CHMUX0_bm (1<<0) /* Event Channel 0 Multiplexer bit 0 mask. */ -#define EVSYS_CHMUX0_bp 0 /* Event Channel 0 Multiplexer bit 0 position. */ -#define EVSYS_CHMUX1_bm (1<<1) /* Event Channel 0 Multiplexer bit 1 mask. */ -#define EVSYS_CHMUX1_bp 1 /* Event Channel 0 Multiplexer bit 1 position. */ -#define EVSYS_CHMUX2_bm (1<<2) /* Event Channel 0 Multiplexer bit 2 mask. */ -#define EVSYS_CHMUX2_bp 2 /* Event Channel 0 Multiplexer bit 2 position. */ -#define EVSYS_CHMUX3_bm (1<<3) /* Event Channel 0 Multiplexer bit 3 mask. */ -#define EVSYS_CHMUX3_bp 3 /* Event Channel 0 Multiplexer bit 3 position. */ -#define EVSYS_CHMUX4_bm (1<<4) /* Event Channel 0 Multiplexer bit 4 mask. */ -#define EVSYS_CHMUX4_bp 4 /* Event Channel 0 Multiplexer bit 4 position. */ -#define EVSYS_CHMUX5_bm (1<<5) /* Event Channel 0 Multiplexer bit 5 mask. */ -#define EVSYS_CHMUX5_bp 5 /* Event Channel 0 Multiplexer bit 5 position. */ -#define EVSYS_CHMUX6_bm (1<<6) /* Event Channel 0 Multiplexer bit 6 mask. */ -#define EVSYS_CHMUX6_bp 6 /* Event Channel 0 Multiplexer bit 6 position. */ -#define EVSYS_CHMUX7_bm (1<<7) /* Event Channel 0 Multiplexer bit 7 mask. */ -#define EVSYS_CHMUX7_bp 7 /* Event Channel 0 Multiplexer bit 7 position. */ - -/* EVSYS.CH1MUX bit masks and bit positions */ -/* EVSYS_CHMUX Predefined. */ -/* EVSYS_CHMUX Predefined. */ - -/* EVSYS.CH2MUX bit masks and bit positions */ -/* EVSYS_CHMUX Predefined. */ -/* EVSYS_CHMUX Predefined. */ - -/* EVSYS.CH3MUX bit masks and bit positions */ -/* EVSYS_CHMUX Predefined. */ -/* EVSYS_CHMUX Predefined. */ - -/* EVSYS.CH0CTRL bit masks and bit positions */ -#define EVSYS_QDIRM_gm 0x60 /* Quadrature Decoder Index Recognition Mode group mask. */ -#define EVSYS_QDIRM_gp 5 /* Quadrature Decoder Index Recognition Mode group position. */ -#define EVSYS_QDIRM0_bm (1<<5) /* Quadrature Decoder Index Recognition Mode bit 0 mask. */ -#define EVSYS_QDIRM0_bp 5 /* Quadrature Decoder Index Recognition Mode bit 0 position. */ -#define EVSYS_QDIRM1_bm (1<<6) /* Quadrature Decoder Index Recognition Mode bit 1 mask. */ -#define EVSYS_QDIRM1_bp 6 /* Quadrature Decoder Index Recognition Mode bit 1 position. */ - -#define EVSYS_QDIEN_bm 0x10 /* Quadrature Decoder Index Enable bit mask. */ -#define EVSYS_QDIEN_bp 4 /* Quadrature Decoder Index Enable bit position. */ - -#define EVSYS_QDEN_bm 0x08 /* Quadrature Decoder Enable bit mask. */ -#define EVSYS_QDEN_bp 3 /* Quadrature Decoder Enable bit position. */ - -#define EVSYS_DIGFILT_gm 0x07 /* Digital Filter group mask. */ -#define EVSYS_DIGFILT_gp 0 /* Digital Filter group position. */ -#define EVSYS_DIGFILT0_bm (1<<0) /* Digital Filter bit 0 mask. */ -#define EVSYS_DIGFILT0_bp 0 /* Digital Filter bit 0 position. */ -#define EVSYS_DIGFILT1_bm (1<<1) /* Digital Filter bit 1 mask. */ -#define EVSYS_DIGFILT1_bp 1 /* Digital Filter bit 1 position. */ -#define EVSYS_DIGFILT2_bm (1<<2) /* Digital Filter bit 2 mask. */ -#define EVSYS_DIGFILT2_bp 2 /* Digital Filter bit 2 position. */ - -/* EVSYS.CH1CTRL bit masks and bit positions */ -/* EVSYS_DIGFILT Predefined. */ -/* EVSYS_DIGFILT Predefined. */ - -/* EVSYS.CH2CTRL bit masks and bit positions */ -/* EVSYS_DIGFILT Predefined. */ -/* EVSYS_DIGFILT Predefined. */ - -/* EVSYS.CH3CTRL bit masks and bit positions */ -/* EVSYS_DIGFILT Predefined. */ -/* EVSYS_DIGFILT Predefined. */ - -/* NVM - Non Volatile Memory Controller */ -/* NVM.CMD bit masks and bit positions */ -#define NVM_CMD_gm 0x7F /* Command group mask. */ -#define NVM_CMD_gp 0 /* Command group position. */ -#define NVM_CMD0_bm (1<<0) /* Command bit 0 mask. */ -#define NVM_CMD0_bp 0 /* Command bit 0 position. */ -#define NVM_CMD1_bm (1<<1) /* Command bit 1 mask. */ -#define NVM_CMD1_bp 1 /* Command bit 1 position. */ -#define NVM_CMD2_bm (1<<2) /* Command bit 2 mask. */ -#define NVM_CMD2_bp 2 /* Command bit 2 position. */ -#define NVM_CMD3_bm (1<<3) /* Command bit 3 mask. */ -#define NVM_CMD3_bp 3 /* Command bit 3 position. */ -#define NVM_CMD4_bm (1<<4) /* Command bit 4 mask. */ -#define NVM_CMD4_bp 4 /* Command bit 4 position. */ -#define NVM_CMD5_bm (1<<5) /* Command bit 5 mask. */ -#define NVM_CMD5_bp 5 /* Command bit 5 position. */ -#define NVM_CMD6_bm (1<<6) /* Command bit 6 mask. */ -#define NVM_CMD6_bp 6 /* Command bit 6 position. */ - -/* NVM.CTRLA bit masks and bit positions */ -#define NVM_CMDEX_bm 0x01 /* Command Execute bit mask. */ -#define NVM_CMDEX_bp 0 /* Command Execute bit position. */ - -/* NVM.CTRLB bit masks and bit positions */ -#define NVM_EEMAPEN_bm 0x08 /* EEPROM Mapping Enable bit mask. */ -#define NVM_EEMAPEN_bp 3 /* EEPROM Mapping Enable bit position. */ - -#define NVM_FPRM_bm 0x04 /* Flash Power Reduction Enable bit mask. */ -#define NVM_FPRM_bp 2 /* Flash Power Reduction Enable bit position. */ - -#define NVM_EPRM_bm 0x02 /* EEPROM Power Reduction Enable bit mask. */ -#define NVM_EPRM_bp 1 /* EEPROM Power Reduction Enable bit position. */ - -#define NVM_SPMLOCK_bm 0x01 /* SPM Lock bit mask. */ -#define NVM_SPMLOCK_bp 0 /* SPM Lock bit position. */ - -/* NVM.INTCTRL bit masks and bit positions */ -#define NVM_SPMLVL_gm 0x0C /* SPM Interrupt Level group mask. */ -#define NVM_SPMLVL_gp 2 /* SPM Interrupt Level group position. */ -#define NVM_SPMLVL0_bm (1<<2) /* SPM Interrupt Level bit 0 mask. */ -#define NVM_SPMLVL0_bp 2 /* SPM Interrupt Level bit 0 position. */ -#define NVM_SPMLVL1_bm (1<<3) /* SPM Interrupt Level bit 1 mask. */ -#define NVM_SPMLVL1_bp 3 /* SPM Interrupt Level bit 1 position. */ - -#define NVM_EELVL_gm 0x03 /* EEPROM Interrupt Level group mask. */ -#define NVM_EELVL_gp 0 /* EEPROM Interrupt Level group position. */ -#define NVM_EELVL0_bm (1<<0) /* EEPROM Interrupt Level bit 0 mask. */ -#define NVM_EELVL0_bp 0 /* EEPROM Interrupt Level bit 0 position. */ -#define NVM_EELVL1_bm (1<<1) /* EEPROM Interrupt Level bit 1 mask. */ -#define NVM_EELVL1_bp 1 /* EEPROM Interrupt Level bit 1 position. */ - -/* NVM.STATUS bit masks and bit positions */ -#define NVM_NVMBUSY_bm 0x80 /* Non-volatile Memory Busy bit mask. */ -#define NVM_NVMBUSY_bp 7 /* Non-volatile Memory Busy bit position. */ - -#define NVM_FBUSY_bm 0x40 /* Flash Memory Busy bit mask. */ -#define NVM_FBUSY_bp 6 /* Flash Memory Busy bit position. */ - -#define NVM_EELOAD_bm 0x02 /* EEPROM Page Buffer Active Loading bit mask. */ -#define NVM_EELOAD_bp 1 /* EEPROM Page Buffer Active Loading bit position. */ - -#define NVM_FLOAD_bm 0x01 /* Flash Page Buffer Active Loading bit mask. */ -#define NVM_FLOAD_bp 0 /* Flash Page Buffer Active Loading bit position. */ - -/* NVM.LOCKBITS bit masks and bit positions */ -#define NVM_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ -#define NVM_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ -#define NVM_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ -#define NVM_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ -#define NVM_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ -#define NVM_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ - -#define NVM_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ -#define NVM_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ -#define NVM_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ -#define NVM_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ -#define NVM_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ -#define NVM_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ - -#define NVM_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ -#define NVM_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ -#define NVM_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ -#define NVM_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ -#define NVM_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ -#define NVM_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ - -#define NVM_LB_gm 0x03 /* Lock Bits group mask. */ -#define NVM_LB_gp 0 /* Lock Bits group position. */ -#define NVM_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ -#define NVM_LB0_bp 0 /* Lock Bits bit 0 position. */ -#define NVM_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ -#define NVM_LB1_bp 1 /* Lock Bits bit 1 position. */ - -/* ADC - Analog/Digital Converter */ -/* ADC_CH.CTRL bit masks and bit positions */ -#define ADC_CH_START_bm 0x80 /* Channel Start Conversion bit mask. */ -#define ADC_CH_START_bp 7 /* Channel Start Conversion bit position. */ - -#define ADC_CH_GAIN_gm 0x1C /* Gain Factor group mask. */ -#define ADC_CH_GAIN_gp 2 /* Gain Factor group position. */ -#define ADC_CH_GAIN0_bm (1<<2) /* Gain Factor bit 0 mask. */ -#define ADC_CH_GAIN0_bp 2 /* Gain Factor bit 0 position. */ -#define ADC_CH_GAIN1_bm (1<<3) /* Gain Factor bit 1 mask. */ -#define ADC_CH_GAIN1_bp 3 /* Gain Factor bit 1 position. */ -#define ADC_CH_GAIN2_bm (1<<4) /* Gain Factor bit 2 mask. */ -#define ADC_CH_GAIN2_bp 4 /* Gain Factor bit 2 position. */ - -#define ADC_CH_INPUTMODE_gm 0x03 /* Input Mode Select group mask. */ -#define ADC_CH_INPUTMODE_gp 0 /* Input Mode Select group position. */ -#define ADC_CH_INPUTMODE0_bm (1<<0) /* Input Mode Select bit 0 mask. */ -#define ADC_CH_INPUTMODE0_bp 0 /* Input Mode Select bit 0 position. */ -#define ADC_CH_INPUTMODE1_bm (1<<1) /* Input Mode Select bit 1 mask. */ -#define ADC_CH_INPUTMODE1_bp 1 /* Input Mode Select bit 1 position. */ - -/* ADC_CH.MUXCTRL bit masks and bit positions */ -#define ADC_CH_MUXPOS_gm 0x78 /* MUX selection on Positive ADC input group mask. */ -#define ADC_CH_MUXPOS_gp 3 /* MUX selection on Positive ADC input group position. */ -#define ADC_CH_MUXPOS0_bm (1<<3) /* MUX selection on Positive ADC input bit 0 mask. */ -#define ADC_CH_MUXPOS0_bp 3 /* MUX selection on Positive ADC input bit 0 position. */ -#define ADC_CH_MUXPOS1_bm (1<<4) /* MUX selection on Positive ADC input bit 1 mask. */ -#define ADC_CH_MUXPOS1_bp 4 /* MUX selection on Positive ADC input bit 1 position. */ -#define ADC_CH_MUXPOS2_bm (1<<5) /* MUX selection on Positive ADC input bit 2 mask. */ -#define ADC_CH_MUXPOS2_bp 5 /* MUX selection on Positive ADC input bit 2 position. */ -#define ADC_CH_MUXPOS3_bm (1<<6) /* MUX selection on Positive ADC input bit 3 mask. */ -#define ADC_CH_MUXPOS3_bp 6 /* MUX selection on Positive ADC input bit 3 position. */ - -#define ADC_CH_MUXINT_gm 0x78 /* MUX selection on Internal ADC input group mask. */ -#define ADC_CH_MUXINT_gp 3 /* MUX selection on Internal ADC input group position. */ -#define ADC_CH_MUXINT0_bm (1<<3) /* MUX selection on Internal ADC input bit 0 mask. */ -#define ADC_CH_MUXINT0_bp 3 /* MUX selection on Internal ADC input bit 0 position. */ -#define ADC_CH_MUXINT1_bm (1<<4) /* MUX selection on Internal ADC input bit 1 mask. */ -#define ADC_CH_MUXINT1_bp 4 /* MUX selection on Internal ADC input bit 1 position. */ -#define ADC_CH_MUXINT2_bm (1<<5) /* MUX selection on Internal ADC input bit 2 mask. */ -#define ADC_CH_MUXINT2_bp 5 /* MUX selection on Internal ADC input bit 2 position. */ -#define ADC_CH_MUXINT3_bm (1<<6) /* MUX selection on Internal ADC input bit 3 mask. */ -#define ADC_CH_MUXINT3_bp 6 /* MUX selection on Internal ADC input bit 3 position. */ - -#define ADC_CH_MUXNEG_gm 0x03 /* MUX selection on Negative ADC input group mask. */ -#define ADC_CH_MUXNEG_gp 0 /* MUX selection on Negative ADC input group position. */ -#define ADC_CH_MUXNEG0_bm (1<<0) /* MUX selection on Negative ADC input bit 0 mask. */ -#define ADC_CH_MUXNEG0_bp 0 /* MUX selection on Negative ADC input bit 0 position. */ -#define ADC_CH_MUXNEG1_bm (1<<1) /* MUX selection on Negative ADC input bit 1 mask. */ -#define ADC_CH_MUXNEG1_bp 1 /* MUX selection on Negative ADC input bit 1 position. */ - -/* ADC_CH.INTCTRL bit masks and bit positions */ -#define ADC_CH_INTMODE_gm 0x0C /* Interrupt Mode group mask. */ -#define ADC_CH_INTMODE_gp 2 /* Interrupt Mode group position. */ -#define ADC_CH_INTMODE0_bm (1<<2) /* Interrupt Mode bit 0 mask. */ -#define ADC_CH_INTMODE0_bp 2 /* Interrupt Mode bit 0 position. */ -#define ADC_CH_INTMODE1_bm (1<<3) /* Interrupt Mode bit 1 mask. */ -#define ADC_CH_INTMODE1_bp 3 /* Interrupt Mode bit 1 position. */ - -#define ADC_CH_INTLVL_gm 0x03 /* Interrupt Level group mask. */ -#define ADC_CH_INTLVL_gp 0 /* Interrupt Level group position. */ -#define ADC_CH_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */ -#define ADC_CH_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */ -#define ADC_CH_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ -#define ADC_CH_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */ - -/* ADC_CH.INTFLAGS bit masks and bit positions */ -#define ADC_CH_CHIF_bm 0x01 /* Channel Interrupt Flag bit mask. */ -#define ADC_CH_CHIF_bp 0 /* Channel Interrupt Flag bit position. */ - -/* ADC_CH.SCAN bit masks and bit positions */ -#define ADC_CH_OFFSET_gm 0xF0 /* Positive MUX setting offset group mask. */ -#define ADC_CH_OFFSET_gp 4 /* Positive MUX setting offset group position. */ -#define ADC_CH_OFFSET0_bm (1<<4) /* Positive MUX setting offset bit 0 mask. */ -#define ADC_CH_OFFSET0_bp 4 /* Positive MUX setting offset bit 0 position. */ -#define ADC_CH_OFFSET1_bm (1<<5) /* Positive MUX setting offset bit 1 mask. */ -#define ADC_CH_OFFSET1_bp 5 /* Positive MUX setting offset bit 1 position. */ -#define ADC_CH_OFFSET2_bm (1<<6) /* Positive MUX setting offset bit 2 mask. */ -#define ADC_CH_OFFSET2_bp 6 /* Positive MUX setting offset bit 2 position. */ -#define ADC_CH_OFFSET3_bm (1<<7) /* Positive MUX setting offset bit 3 mask. */ -#define ADC_CH_OFFSET3_bp 7 /* Positive MUX setting offset bit 3 position. */ - -#define ADC_CH_SCANNUM_gm 0x0F /* Number of Channels included in scan group mask. */ -#define ADC_CH_SCANNUM_gp 0 /* Number of Channels included in scan group position. */ -#define ADC_CH_SCANNUM0_bm (1<<0) /* Number of Channels included in scan bit 0 mask. */ -#define ADC_CH_SCANNUM0_bp 0 /* Number of Channels included in scan bit 0 position. */ -#define ADC_CH_SCANNUM1_bm (1<<1) /* Number of Channels included in scan bit 1 mask. */ -#define ADC_CH_SCANNUM1_bp 1 /* Number of Channels included in scan bit 1 position. */ -#define ADC_CH_SCANNUM2_bm (1<<2) /* Number of Channels included in scan bit 2 mask. */ -#define ADC_CH_SCANNUM2_bp 2 /* Number of Channels included in scan bit 2 position. */ -#define ADC_CH_SCANNUM3_bm (1<<3) /* Number of Channels included in scan bit 3 mask. */ -#define ADC_CH_SCANNUM3_bp 3 /* Number of Channels included in scan bit 3 position. */ - -/* ADC.CTRLA bit masks and bit positions */ -#define ADC_CH0START_bm 0x04 /* Channel 0 Start Conversion bit mask. */ -#define ADC_CH0START_bp 2 /* Channel 0 Start Conversion bit position. */ - -#define ADC_FLUSH_bm 0x02 /* ADC Flush bit mask. */ -#define ADC_FLUSH_bp 1 /* ADC Flush bit position. */ - -#define ADC_ENABLE_bm 0x01 /* Enable ADC bit mask. */ -#define ADC_ENABLE_bp 0 /* Enable ADC bit position. */ - -/* ADC.CTRLB bit masks and bit positions */ -#define ADC_CURRLIMIT_gm 0x60 /* Current Limitation group mask. */ -#define ADC_CURRLIMIT_gp 5 /* Current Limitation group position. */ -#define ADC_CURRLIMIT0_bm (1<<5) /* Current Limitation bit 0 mask. */ -#define ADC_CURRLIMIT0_bp 5 /* Current Limitation bit 0 position. */ -#define ADC_CURRLIMIT1_bm (1<<6) /* Current Limitation bit 1 mask. */ -#define ADC_CURRLIMIT1_bp 6 /* Current Limitation bit 1 position. */ - -#define ADC_CONMODE_bm 0x10 /* Conversion Mode bit mask. */ -#define ADC_CONMODE_bp 4 /* Conversion Mode bit position. */ - -#define ADC_FREERUN_bm 0x08 /* Free Running Mode Enable bit mask. */ -#define ADC_FREERUN_bp 3 /* Free Running Mode Enable bit position. */ - -#define ADC_RESOLUTION_gm 0x06 /* Result Resolution group mask. */ -#define ADC_RESOLUTION_gp 1 /* Result Resolution group position. */ -#define ADC_RESOLUTION0_bm (1<<1) /* Result Resolution bit 0 mask. */ -#define ADC_RESOLUTION0_bp 1 /* Result Resolution bit 0 position. */ -#define ADC_RESOLUTION1_bm (1<<2) /* Result Resolution bit 1 mask. */ -#define ADC_RESOLUTION1_bp 2 /* Result Resolution bit 1 position. */ - -/* ADC.REFCTRL bit masks and bit positions */ -#define ADC_REFSEL_gm 0x70 /* Reference Selection group mask. */ -#define ADC_REFSEL_gp 4 /* Reference Selection group position. */ -#define ADC_REFSEL0_bm (1<<4) /* Reference Selection bit 0 mask. */ -#define ADC_REFSEL0_bp 4 /* Reference Selection bit 0 position. */ -#define ADC_REFSEL1_bm (1<<5) /* Reference Selection bit 1 mask. */ -#define ADC_REFSEL1_bp 5 /* Reference Selection bit 1 position. */ -#define ADC_REFSEL2_bm (1<<6) /* Reference Selection bit 2 mask. */ -#define ADC_REFSEL2_bp 6 /* Reference Selection bit 2 position. */ - -#define ADC_BANDGAP_bm 0x02 /* Bandgap enable bit mask. */ -#define ADC_BANDGAP_bp 1 /* Bandgap enable bit position. */ - -#define ADC_TEMPREF_bm 0x01 /* Temperature Reference Enable bit mask. */ -#define ADC_TEMPREF_bp 0 /* Temperature Reference Enable bit position. */ - -/* ADC.EVCTRL bit masks and bit positions */ -#define ADC_EVSEL_gm 0x18 /* Event Input Select group mask. */ -#define ADC_EVSEL_gp 3 /* Event Input Select group position. */ -#define ADC_EVSEL0_bm (1<<3) /* Event Input Select bit 0 mask. */ -#define ADC_EVSEL0_bp 3 /* Event Input Select bit 0 position. */ -#define ADC_EVSEL1_bm (1<<4) /* Event Input Select bit 1 mask. */ -#define ADC_EVSEL1_bp 4 /* Event Input Select bit 1 position. */ - -#define ADC_EVACT_gm 0x07 /* Event Action Select group mask. */ -#define ADC_EVACT_gp 0 /* Event Action Select group position. */ -#define ADC_EVACT0_bm (1<<0) /* Event Action Select bit 0 mask. */ -#define ADC_EVACT0_bp 0 /* Event Action Select bit 0 position. */ -#define ADC_EVACT1_bm (1<<1) /* Event Action Select bit 1 mask. */ -#define ADC_EVACT1_bp 1 /* Event Action Select bit 1 position. */ -#define ADC_EVACT2_bm (1<<2) /* Event Action Select bit 2 mask. */ -#define ADC_EVACT2_bp 2 /* Event Action Select bit 2 position. */ - -/* ADC.PRESCALER bit masks and bit positions */ -#define ADC_PRESCALER_gm 0x07 /* Clock Prescaler Selection group mask. */ -#define ADC_PRESCALER_gp 0 /* Clock Prescaler Selection group position. */ -#define ADC_PRESCALER0_bm (1<<0) /* Clock Prescaler Selection bit 0 mask. */ -#define ADC_PRESCALER0_bp 0 /* Clock Prescaler Selection bit 0 position. */ -#define ADC_PRESCALER1_bm (1<<1) /* Clock Prescaler Selection bit 1 mask. */ -#define ADC_PRESCALER1_bp 1 /* Clock Prescaler Selection bit 1 position. */ -#define ADC_PRESCALER2_bm (1<<2) /* Clock Prescaler Selection bit 2 mask. */ -#define ADC_PRESCALER2_bp 2 /* Clock Prescaler Selection bit 2 position. */ - -/* ADC.INTFLAGS bit masks and bit positions */ -#define ADC_CH0IF_bm 0x01 /* Channel 0 Interrupt Flag bit mask. */ -#define ADC_CH0IF_bp 0 /* Channel 0 Interrupt Flag bit position. */ - -/* AC - Analog Comparator */ -/* AC.AC0CTRL bit masks and bit positions */ -#define AC_INTMODE_gm 0xC0 /* Interrupt Mode group mask. */ -#define AC_INTMODE_gp 6 /* Interrupt Mode group position. */ -#define AC_INTMODE0_bm (1<<6) /* Interrupt Mode bit 0 mask. */ -#define AC_INTMODE0_bp 6 /* Interrupt Mode bit 0 position. */ -#define AC_INTMODE1_bm (1<<7) /* Interrupt Mode bit 1 mask. */ -#define AC_INTMODE1_bp 7 /* Interrupt Mode bit 1 position. */ - -#define AC_INTLVL_gm 0x30 /* Interrupt Level group mask. */ -#define AC_INTLVL_gp 4 /* Interrupt Level group position. */ -#define AC_INTLVL0_bm (1<<4) /* Interrupt Level bit 0 mask. */ -#define AC_INTLVL0_bp 4 /* Interrupt Level bit 0 position. */ -#define AC_INTLVL1_bm (1<<5) /* Interrupt Level bit 1 mask. */ -#define AC_INTLVL1_bp 5 /* Interrupt Level bit 1 position. */ - -#define AC_HYSMODE_gm 0x06 /* Hysteresis Mode group mask. */ -#define AC_HYSMODE_gp 1 /* Hysteresis Mode group position. */ -#define AC_HYSMODE0_bm (1<<1) /* Hysteresis Mode bit 0 mask. */ -#define AC_HYSMODE0_bp 1 /* Hysteresis Mode bit 0 position. */ -#define AC_HYSMODE1_bm (1<<2) /* Hysteresis Mode bit 1 mask. */ -#define AC_HYSMODE1_bp 2 /* Hysteresis Mode bit 1 position. */ - -#define AC_ENABLE_bm 0x01 /* Enable bit mask. */ -#define AC_ENABLE_bp 0 /* Enable bit position. */ - -/* AC.AC1CTRL bit masks and bit positions */ -/* AC_INTMODE Predefined. */ -/* AC_INTMODE Predefined. */ - -/* AC_INTLVL Predefined. */ -/* AC_INTLVL Predefined. */ - -/* AC_HYSMODE Predefined. */ -/* AC_HYSMODE Predefined. */ - -/* AC_ENABLE Predefined. */ -/* AC_ENABLE Predefined. */ - -/* AC.AC0MUXCTRL bit masks and bit positions */ -#define AC_MUXPOS_gm 0x38 /* MUX Positive Input group mask. */ -#define AC_MUXPOS_gp 3 /* MUX Positive Input group position. */ -#define AC_MUXPOS0_bm (1<<3) /* MUX Positive Input bit 0 mask. */ -#define AC_MUXPOS0_bp 3 /* MUX Positive Input bit 0 position. */ -#define AC_MUXPOS1_bm (1<<4) /* MUX Positive Input bit 1 mask. */ -#define AC_MUXPOS1_bp 4 /* MUX Positive Input bit 1 position. */ -#define AC_MUXPOS2_bm (1<<5) /* MUX Positive Input bit 2 mask. */ -#define AC_MUXPOS2_bp 5 /* MUX Positive Input bit 2 position. */ - -#define AC_MUXNEG_gm 0x07 /* MUX Negative Input group mask. */ -#define AC_MUXNEG_gp 0 /* MUX Negative Input group position. */ -#define AC_MUXNEG0_bm (1<<0) /* MUX Negative Input bit 0 mask. */ -#define AC_MUXNEG0_bp 0 /* MUX Negative Input bit 0 position. */ -#define AC_MUXNEG1_bm (1<<1) /* MUX Negative Input bit 1 mask. */ -#define AC_MUXNEG1_bp 1 /* MUX Negative Input bit 1 position. */ -#define AC_MUXNEG2_bm (1<<2) /* MUX Negative Input bit 2 mask. */ -#define AC_MUXNEG2_bp 2 /* MUX Negative Input bit 2 position. */ - -/* AC.AC1MUXCTRL bit masks and bit positions */ -/* AC_MUXPOS Predefined. */ -/* AC_MUXPOS Predefined. */ - -/* AC_MUXNEG Predefined. */ -/* AC_MUXNEG Predefined. */ - -/* AC.CTRLA bit masks and bit positions */ -#define AC_AC1OUT_bm 0x02 /* Analog Comparator 1 Output Enable bit mask. */ -#define AC_AC1OUT_bp 1 /* Analog Comparator 1 Output Enable bit position. */ - -#define AC_AC0OUT_bm 0x01 /* Analog Comparator 0 Output Enable bit mask. */ -#define AC_AC0OUT_bp 0 /* Analog Comparator 0 Output Enable bit position. */ - -/* AC.CTRLB bit masks and bit positions */ -#define AC_SCALEFAC_gm 0x3F /* VCC Voltage Scaler Factor group mask. */ -#define AC_SCALEFAC_gp 0 /* VCC Voltage Scaler Factor group position. */ -#define AC_SCALEFAC0_bm (1<<0) /* VCC Voltage Scaler Factor bit 0 mask. */ -#define AC_SCALEFAC0_bp 0 /* VCC Voltage Scaler Factor bit 0 position. */ -#define AC_SCALEFAC1_bm (1<<1) /* VCC Voltage Scaler Factor bit 1 mask. */ -#define AC_SCALEFAC1_bp 1 /* VCC Voltage Scaler Factor bit 1 position. */ -#define AC_SCALEFAC2_bm (1<<2) /* VCC Voltage Scaler Factor bit 2 mask. */ -#define AC_SCALEFAC2_bp 2 /* VCC Voltage Scaler Factor bit 2 position. */ -#define AC_SCALEFAC3_bm (1<<3) /* VCC Voltage Scaler Factor bit 3 mask. */ -#define AC_SCALEFAC3_bp 3 /* VCC Voltage Scaler Factor bit 3 position. */ -#define AC_SCALEFAC4_bm (1<<4) /* VCC Voltage Scaler Factor bit 4 mask. */ -#define AC_SCALEFAC4_bp 4 /* VCC Voltage Scaler Factor bit 4 position. */ -#define AC_SCALEFAC5_bm (1<<5) /* VCC Voltage Scaler Factor bit 5 mask. */ -#define AC_SCALEFAC5_bp 5 /* VCC Voltage Scaler Factor bit 5 position. */ - -/* AC.WINCTRL bit masks and bit positions */ -#define AC_WEN_bm 0x10 /* Window Mode Enable bit mask. */ -#define AC_WEN_bp 4 /* Window Mode Enable bit position. */ - -#define AC_WINTMODE_gm 0x0C /* Window Interrupt Mode group mask. */ -#define AC_WINTMODE_gp 2 /* Window Interrupt Mode group position. */ -#define AC_WINTMODE0_bm (1<<2) /* Window Interrupt Mode bit 0 mask. */ -#define AC_WINTMODE0_bp 2 /* Window Interrupt Mode bit 0 position. */ -#define AC_WINTMODE1_bm (1<<3) /* Window Interrupt Mode bit 1 mask. */ -#define AC_WINTMODE1_bp 3 /* Window Interrupt Mode bit 1 position. */ - -#define AC_WINTLVL_gm 0x03 /* Window Interrupt Level group mask. */ -#define AC_WINTLVL_gp 0 /* Window Interrupt Level group position. */ -#define AC_WINTLVL0_bm (1<<0) /* Window Interrupt Level bit 0 mask. */ -#define AC_WINTLVL0_bp 0 /* Window Interrupt Level bit 0 position. */ -#define AC_WINTLVL1_bm (1<<1) /* Window Interrupt Level bit 1 mask. */ -#define AC_WINTLVL1_bp 1 /* Window Interrupt Level bit 1 position. */ - -/* AC.STATUS bit masks and bit positions */ -#define AC_WSTATE_gm 0xC0 /* Window Mode State group mask. */ -#define AC_WSTATE_gp 6 /* Window Mode State group position. */ -#define AC_WSTATE0_bm (1<<6) /* Window Mode State bit 0 mask. */ -#define AC_WSTATE0_bp 6 /* Window Mode State bit 0 position. */ -#define AC_WSTATE1_bm (1<<7) /* Window Mode State bit 1 mask. */ -#define AC_WSTATE1_bp 7 /* Window Mode State bit 1 position. */ - -#define AC_AC1STATE_bm 0x20 /* Analog Comparator 1 State bit mask. */ -#define AC_AC1STATE_bp 5 /* Analog Comparator 1 State bit position. */ - -#define AC_AC0STATE_bm 0x10 /* Analog Comparator 0 State bit mask. */ -#define AC_AC0STATE_bp 4 /* Analog Comparator 0 State bit position. */ - -#define AC_WIF_bm 0x04 /* Window Mode Interrupt Flag bit mask. */ -#define AC_WIF_bp 2 /* Window Mode Interrupt Flag bit position. */ - -#define AC_AC1IF_bm 0x02 /* Analog Comparator 1 Interrupt Flag bit mask. */ -#define AC_AC1IF_bp 1 /* Analog Comparator 1 Interrupt Flag bit position. */ - -#define AC_AC0IF_bm 0x01 /* Analog Comparator 0 Interrupt Flag bit mask. */ -#define AC_AC0IF_bp 0 /* Analog Comparator 0 Interrupt Flag bit position. */ - -/* RTC - Real-Time Counter */ -/* RTC.CTRL bit masks and bit positions */ -#define RTC_PRESCALER_gm 0x07 /* Prescaling Factor group mask. */ -#define RTC_PRESCALER_gp 0 /* Prescaling Factor group position. */ -#define RTC_PRESCALER0_bm (1<<0) /* Prescaling Factor bit 0 mask. */ -#define RTC_PRESCALER0_bp 0 /* Prescaling Factor bit 0 position. */ -#define RTC_PRESCALER1_bm (1<<1) /* Prescaling Factor bit 1 mask. */ -#define RTC_PRESCALER1_bp 1 /* Prescaling Factor bit 1 position. */ -#define RTC_PRESCALER2_bm (1<<2) /* Prescaling Factor bit 2 mask. */ -#define RTC_PRESCALER2_bp 2 /* Prescaling Factor bit 2 position. */ - -/* RTC.STATUS bit masks and bit positions */ -#define RTC_SYNCBUSY_bm 0x01 /* Synchronization Busy Flag bit mask. */ -#define RTC_SYNCBUSY_bp 0 /* Synchronization Busy Flag bit position. */ - -/* RTC.INTCTRL bit masks and bit positions */ -#define RTC_COMPINTLVL_gm 0x0C /* Compare Match Interrupt Level group mask. */ -#define RTC_COMPINTLVL_gp 2 /* Compare Match Interrupt Level group position. */ -#define RTC_COMPINTLVL0_bm (1<<2) /* Compare Match Interrupt Level bit 0 mask. */ -#define RTC_COMPINTLVL0_bp 2 /* Compare Match Interrupt Level bit 0 position. */ -#define RTC_COMPINTLVL1_bm (1<<3) /* Compare Match Interrupt Level bit 1 mask. */ -#define RTC_COMPINTLVL1_bp 3 /* Compare Match Interrupt Level bit 1 position. */ - -#define RTC_OVFINTLVL_gm 0x03 /* Overflow Interrupt Level group mask. */ -#define RTC_OVFINTLVL_gp 0 /* Overflow Interrupt Level group position. */ -#define RTC_OVFINTLVL0_bm (1<<0) /* Overflow Interrupt Level bit 0 mask. */ -#define RTC_OVFINTLVL0_bp 0 /* Overflow Interrupt Level bit 0 position. */ -#define RTC_OVFINTLVL1_bm (1<<1) /* Overflow Interrupt Level bit 1 mask. */ -#define RTC_OVFINTLVL1_bp 1 /* Overflow Interrupt Level bit 1 position. */ - -/* RTC.INTFLAGS bit masks and bit positions */ -#define RTC_COMPIF_bm 0x02 /* Compare Match Interrupt Flag bit mask. */ -#define RTC_COMPIF_bp 1 /* Compare Match Interrupt Flag bit position. */ - -#define RTC_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ -#define RTC_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ - -/* TWI - Two-Wire Interface */ -/* TWI_MASTER.CTRLA bit masks and bit positions */ -#define TWI_MASTER_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ -#define TWI_MASTER_INTLVL_gp 6 /* Interrupt Level group position. */ -#define TWI_MASTER_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ -#define TWI_MASTER_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ -#define TWI_MASTER_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ -#define TWI_MASTER_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ - -#define TWI_MASTER_RIEN_bm 0x20 /* Read Interrupt Enable bit mask. */ -#define TWI_MASTER_RIEN_bp 5 /* Read Interrupt Enable bit position. */ - -#define TWI_MASTER_WIEN_bm 0x10 /* Write Interrupt Enable bit mask. */ -#define TWI_MASTER_WIEN_bp 4 /* Write Interrupt Enable bit position. */ - -#define TWI_MASTER_ENABLE_bm 0x08 /* Enable TWI Master bit mask. */ -#define TWI_MASTER_ENABLE_bp 3 /* Enable TWI Master bit position. */ - -/* TWI_MASTER.CTRLB bit masks and bit positions */ -#define TWI_MASTER_TIMEOUT_gm 0x0C /* Inactive Bus Timeout group mask. */ -#define TWI_MASTER_TIMEOUT_gp 2 /* Inactive Bus Timeout group position. */ -#define TWI_MASTER_TIMEOUT0_bm (1<<2) /* Inactive Bus Timeout bit 0 mask. */ -#define TWI_MASTER_TIMEOUT0_bp 2 /* Inactive Bus Timeout bit 0 position. */ -#define TWI_MASTER_TIMEOUT1_bm (1<<3) /* Inactive Bus Timeout bit 1 mask. */ -#define TWI_MASTER_TIMEOUT1_bp 3 /* Inactive Bus Timeout bit 1 position. */ - -#define TWI_MASTER_QCEN_bm 0x02 /* Quick Command Enable bit mask. */ -#define TWI_MASTER_QCEN_bp 1 /* Quick Command Enable bit position. */ - -#define TWI_MASTER_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ -#define TWI_MASTER_SMEN_bp 0 /* Smart Mode Enable bit position. */ - -/* TWI_MASTER.CTRLC bit masks and bit positions */ -#define TWI_MASTER_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ -#define TWI_MASTER_ACKACT_bp 2 /* Acknowledge Action bit position. */ - -#define TWI_MASTER_CMD_gm 0x03 /* Command group mask. */ -#define TWI_MASTER_CMD_gp 0 /* Command group position. */ -#define TWI_MASTER_CMD0_bm (1<<0) /* Command bit 0 mask. */ -#define TWI_MASTER_CMD0_bp 0 /* Command bit 0 position. */ -#define TWI_MASTER_CMD1_bm (1<<1) /* Command bit 1 mask. */ -#define TWI_MASTER_CMD1_bp 1 /* Command bit 1 position. */ - -/* TWI_MASTER.STATUS bit masks and bit positions */ -#define TWI_MASTER_RIF_bm 0x80 /* Read Interrupt Flag bit mask. */ -#define TWI_MASTER_RIF_bp 7 /* Read Interrupt Flag bit position. */ - -#define TWI_MASTER_WIF_bm 0x40 /* Write Interrupt Flag bit mask. */ -#define TWI_MASTER_WIF_bp 6 /* Write Interrupt Flag bit position. */ - -#define TWI_MASTER_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ -#define TWI_MASTER_CLKHOLD_bp 5 /* Clock Hold bit position. */ - -#define TWI_MASTER_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ -#define TWI_MASTER_RXACK_bp 4 /* Received Acknowledge bit position. */ - -#define TWI_MASTER_ARBLOST_bm 0x08 /* Arbitration Lost bit mask. */ -#define TWI_MASTER_ARBLOST_bp 3 /* Arbitration Lost bit position. */ - -#define TWI_MASTER_BUSERR_bm 0x04 /* Bus Error bit mask. */ -#define TWI_MASTER_BUSERR_bp 2 /* Bus Error bit position. */ - -#define TWI_MASTER_BUSSTATE_gm 0x03 /* Bus State group mask. */ -#define TWI_MASTER_BUSSTATE_gp 0 /* Bus State group position. */ -#define TWI_MASTER_BUSSTATE0_bm (1<<0) /* Bus State bit 0 mask. */ -#define TWI_MASTER_BUSSTATE0_bp 0 /* Bus State bit 0 position. */ -#define TWI_MASTER_BUSSTATE1_bm (1<<1) /* Bus State bit 1 mask. */ -#define TWI_MASTER_BUSSTATE1_bp 1 /* Bus State bit 1 position. */ - -/* TWI_SLAVE.CTRLA bit masks and bit positions */ -#define TWI_SLAVE_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ -#define TWI_SLAVE_INTLVL_gp 6 /* Interrupt Level group position. */ -#define TWI_SLAVE_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ -#define TWI_SLAVE_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ -#define TWI_SLAVE_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ -#define TWI_SLAVE_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ - -#define TWI_SLAVE_DIEN_bm 0x20 /* Data Interrupt Enable bit mask. */ -#define TWI_SLAVE_DIEN_bp 5 /* Data Interrupt Enable bit position. */ - -#define TWI_SLAVE_APIEN_bm 0x10 /* Address/Stop Interrupt Enable bit mask. */ -#define TWI_SLAVE_APIEN_bp 4 /* Address/Stop Interrupt Enable bit position. */ - -#define TWI_SLAVE_ENABLE_bm 0x08 /* Enable TWI Slave bit mask. */ -#define TWI_SLAVE_ENABLE_bp 3 /* Enable TWI Slave bit position. */ - -#define TWI_SLAVE_PIEN_bm 0x04 /* Stop Interrupt Enable bit mask. */ -#define TWI_SLAVE_PIEN_bp 2 /* Stop Interrupt Enable bit position. */ - -#define TWI_SLAVE_PMEN_bm 0x02 /* Promiscuous Mode Enable bit mask. */ -#define TWI_SLAVE_PMEN_bp 1 /* Promiscuous Mode Enable bit position. */ - -#define TWI_SLAVE_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ -#define TWI_SLAVE_SMEN_bp 0 /* Smart Mode Enable bit position. */ - -/* TWI_SLAVE.CTRLB bit masks and bit positions */ -#define TWI_SLAVE_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ -#define TWI_SLAVE_ACKACT_bp 2 /* Acknowledge Action bit position. */ - -#define TWI_SLAVE_CMD_gm 0x03 /* Command group mask. */ -#define TWI_SLAVE_CMD_gp 0 /* Command group position. */ -#define TWI_SLAVE_CMD0_bm (1<<0) /* Command bit 0 mask. */ -#define TWI_SLAVE_CMD0_bp 0 /* Command bit 0 position. */ -#define TWI_SLAVE_CMD1_bm (1<<1) /* Command bit 1 mask. */ -#define TWI_SLAVE_CMD1_bp 1 /* Command bit 1 position. */ - -/* TWI_SLAVE.STATUS bit masks and bit positions */ -#define TWI_SLAVE_DIF_bm 0x80 /* Data Interrupt Flag bit mask. */ -#define TWI_SLAVE_DIF_bp 7 /* Data Interrupt Flag bit position. */ - -#define TWI_SLAVE_APIF_bm 0x40 /* Address/Stop Interrupt Flag bit mask. */ -#define TWI_SLAVE_APIF_bp 6 /* Address/Stop Interrupt Flag bit position. */ - -#define TWI_SLAVE_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ -#define TWI_SLAVE_CLKHOLD_bp 5 /* Clock Hold bit position. */ - -#define TWI_SLAVE_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ -#define TWI_SLAVE_RXACK_bp 4 /* Received Acknowledge bit position. */ - -#define TWI_SLAVE_COLL_bm 0x08 /* Collision bit mask. */ -#define TWI_SLAVE_COLL_bp 3 /* Collision bit position. */ - -#define TWI_SLAVE_BUSERR_bm 0x04 /* Bus Error bit mask. */ -#define TWI_SLAVE_BUSERR_bp 2 /* Bus Error bit position. */ - -#define TWI_SLAVE_DIR_bm 0x02 /* Read/Write Direction bit mask. */ -#define TWI_SLAVE_DIR_bp 1 /* Read/Write Direction bit position. */ - -#define TWI_SLAVE_AP_bm 0x01 /* Slave Address or Stop bit mask. */ -#define TWI_SLAVE_AP_bp 0 /* Slave Address or Stop bit position. */ - -/* TWI_SLAVE.ADDRMASK bit masks and bit positions */ -#define TWI_SLAVE_ADDRMASK_gm 0xFE /* Address Mask group mask. */ -#define TWI_SLAVE_ADDRMASK_gp 1 /* Address Mask group position. */ -#define TWI_SLAVE_ADDRMASK0_bm (1<<1) /* Address Mask bit 0 mask. */ -#define TWI_SLAVE_ADDRMASK0_bp 1 /* Address Mask bit 0 position. */ -#define TWI_SLAVE_ADDRMASK1_bm (1<<2) /* Address Mask bit 1 mask. */ -#define TWI_SLAVE_ADDRMASK1_bp 2 /* Address Mask bit 1 position. */ -#define TWI_SLAVE_ADDRMASK2_bm (1<<3) /* Address Mask bit 2 mask. */ -#define TWI_SLAVE_ADDRMASK2_bp 3 /* Address Mask bit 2 position. */ -#define TWI_SLAVE_ADDRMASK3_bm (1<<4) /* Address Mask bit 3 mask. */ -#define TWI_SLAVE_ADDRMASK3_bp 4 /* Address Mask bit 3 position. */ -#define TWI_SLAVE_ADDRMASK4_bm (1<<5) /* Address Mask bit 4 mask. */ -#define TWI_SLAVE_ADDRMASK4_bp 5 /* Address Mask bit 4 position. */ -#define TWI_SLAVE_ADDRMASK5_bm (1<<6) /* Address Mask bit 5 mask. */ -#define TWI_SLAVE_ADDRMASK5_bp 6 /* Address Mask bit 5 position. */ -#define TWI_SLAVE_ADDRMASK6_bm (1<<7) /* Address Mask bit 6 mask. */ -#define TWI_SLAVE_ADDRMASK6_bp 7 /* Address Mask bit 6 position. */ - -#define TWI_SLAVE_ADDREN_bm 0x01 /* Address Enable bit mask. */ -#define TWI_SLAVE_ADDREN_bp 0 /* Address Enable bit position. */ - -/* TWI.CTRL bit masks and bit positions */ -#define TWI_SDAHOLD_gm 0x06 /* SDA Hold Time Enable group mask. */ -#define TWI_SDAHOLD_gp 1 /* SDA Hold Time Enable group position. */ -#define TWI_SDAHOLD0_bm (1<<1) /* SDA Hold Time Enable bit 0 mask. */ -#define TWI_SDAHOLD0_bp 1 /* SDA Hold Time Enable bit 0 position. */ -#define TWI_SDAHOLD1_bm (1<<2) /* SDA Hold Time Enable bit 1 mask. */ -#define TWI_SDAHOLD1_bp 2 /* SDA Hold Time Enable bit 1 position. */ - -#define TWI_EDIEN_bm 0x01 /* External Driver Interface Enable bit mask. */ -#define TWI_EDIEN_bp 0 /* External Driver Interface Enable bit position. */ - -/* USB - USB */ -/* USB_EP.STATUS bit masks and bit positions */ -#define USB_EP_STALLF_bm 0x80 /* Endpoint Stall Flag bit mask. */ -#define USB_EP_STALLF_bp 7 /* Endpoint Stall Flag bit position. */ - -#define USB_EP_CRC_bm 0x80 /* CRC Error Flag bit mask. */ -#define USB_EP_CRC_bp 7 /* CRC Error Flag bit position. */ - -#define USB_EP_UNF_bm 0x40 /* Underflow Enpoint FLag bit mask. */ -#define USB_EP_UNF_bp 6 /* Underflow Enpoint FLag bit position. */ - -#define USB_EP_OVF_bm 0x40 /* Overflow Enpoint Flag for Output Endpoints bit mask. */ -#define USB_EP_OVF_bp 6 /* Overflow Enpoint Flag for Output Endpoints bit position. */ - -#define USB_EP_TRNCOMPL0_bm 0x20 /* Transaction Complete 0 Flag bit mask. */ -#define USB_EP_TRNCOMPL0_bp 5 /* Transaction Complete 0 Flag bit position. */ - -#define USB_EP_TRNCOMPL1_bm 0x10 /* Transaction Complete 1 Flag bit mask. */ -#define USB_EP_TRNCOMPL1_bp 4 /* Transaction Complete 1 Flag bit position. */ - -#define USB_EP_SETUP_bm 0x10 /* SETUP Transaction Complete Flag bit mask. */ -#define USB_EP_SETUP_bp 4 /* SETUP Transaction Complete Flag bit position. */ - -#define USB_EP_BANK_bm 0x08 /* Bank Select bit mask. */ -#define USB_EP_BANK_bp 3 /* Bank Select bit position. */ - -#define USB_EP_BUSNACK1_bm 0x04 /* Data Buffer 1 Not Acknowledge bit mask. */ -#define USB_EP_BUSNACK1_bp 2 /* Data Buffer 1 Not Acknowledge bit position. */ - -#define USB_EP_BUSNACK0_bm 0x02 /* Data Buffer 0 Not Acknowledge bit mask. */ -#define USB_EP_BUSNACK0_bp 1 /* Data Buffer 0 Not Acknowledge bit position. */ - -#define USB_EP_TOGGLE_bm 0x01 /* Data Toggle bit mask. */ -#define USB_EP_TOGGLE_bp 0 /* Data Toggle bit position. */ - -/* USB_EP.CTRL bit masks and bit positions */ -#define USB_EP_TYPE_gm 0xC0 /* Endpoint Type group mask. */ -#define USB_EP_TYPE_gp 6 /* Endpoint Type group position. */ -#define USB_EP_TYPE0_bm (1<<6) /* Endpoint Type bit 0 mask. */ -#define USB_EP_TYPE0_bp 6 /* Endpoint Type bit 0 position. */ -#define USB_EP_TYPE1_bm (1<<7) /* Endpoint Type bit 1 mask. */ -#define USB_EP_TYPE1_bp 7 /* Endpoint Type bit 1 position. */ - -#define USB_EP_MULTIPKT_bm 0x20 /* Multi Packet Transfer Enable bit mask. */ -#define USB_EP_MULTIPKT_bp 5 /* Multi Packet Transfer Enable bit position. */ - -#define USB_EP_PINGPONG_bm 0x10 /* Ping-Pong Enable bit mask. */ -#define USB_EP_PINGPONG_bp 4 /* Ping-Pong Enable bit position. */ - -#define USB_EP_INTDSBL_bm 0x08 /* Interrupt Disable bit mask. */ -#define USB_EP_INTDSBL_bp 3 /* Interrupt Disable bit position. */ - -#define USB_EP_STALL_bm 0x04 /* Data Stall bit mask. */ -#define USB_EP_STALL_bp 2 /* Data Stall bit position. */ - -#define USB_EP_BUFSIZE_gm 0x07 /* Data Buffer Size group mask. */ -#define USB_EP_BUFSIZE_gp 0 /* Data Buffer Size group position. */ -#define USB_EP_BUFSIZE0_bm (1<<0) /* Data Buffer Size bit 0 mask. */ -#define USB_EP_BUFSIZE0_bp 0 /* Data Buffer Size bit 0 position. */ -#define USB_EP_BUFSIZE1_bm (1<<1) /* Data Buffer Size bit 1 mask. */ -#define USB_EP_BUFSIZE1_bp 1 /* Data Buffer Size bit 1 position. */ -#define USB_EP_BUFSIZE2_bm (1<<2) /* Data Buffer Size bit 2 mask. */ -#define USB_EP_BUFSIZE2_bp 2 /* Data Buffer Size bit 2 position. */ - -/* USB_EP.CNT bit masks and bit positions */ -#define USB_EP_ZLP_bm 0x8000 /* Zero Length Packet bit mask. */ -#define USB_EP_ZLP_bp 15 /* Zero Length Packet bit position. */ - -/* USB.CTRLA bit masks and bit positions */ -#define USB_ENABLE_bm 0x80 /* USB Enable bit mask. */ -#define USB_ENABLE_bp 7 /* USB Enable bit position. */ - -#define USB_SPEED_bm 0x40 /* Speed Select bit mask. */ -#define USB_SPEED_bp 6 /* Speed Select bit position. */ - -#define USB_FIFOEN_bm 0x20 /* USB FIFO Enable bit mask. */ -#define USB_FIFOEN_bp 5 /* USB FIFO Enable bit position. */ - -#define USB_STFRNUM_bm 0x10 /* Store Frame Number Enable bit mask. */ -#define USB_STFRNUM_bp 4 /* Store Frame Number Enable bit position. */ - -#define USB_MAXEP_gm 0x0F /* Maximum Endpoint Addresses group mask. */ -#define USB_MAXEP_gp 0 /* Maximum Endpoint Addresses group position. */ -#define USB_MAXEP0_bm (1<<0) /* Maximum Endpoint Addresses bit 0 mask. */ -#define USB_MAXEP0_bp 0 /* Maximum Endpoint Addresses bit 0 position. */ -#define USB_MAXEP1_bm (1<<1) /* Maximum Endpoint Addresses bit 1 mask. */ -#define USB_MAXEP1_bp 1 /* Maximum Endpoint Addresses bit 1 position. */ -#define USB_MAXEP2_bm (1<<2) /* Maximum Endpoint Addresses bit 2 mask. */ -#define USB_MAXEP2_bp 2 /* Maximum Endpoint Addresses bit 2 position. */ -#define USB_MAXEP3_bm (1<<3) /* Maximum Endpoint Addresses bit 3 mask. */ -#define USB_MAXEP3_bp 3 /* Maximum Endpoint Addresses bit 3 position. */ - -/* USB.CTRLB bit masks and bit positions */ -#define USB_PULLRST_bm 0x10 /* Pull during Reset bit mask. */ -#define USB_PULLRST_bp 4 /* Pull during Reset bit position. */ - -#define USB_RWAKEUP_bm 0x04 /* Remote Wake-up bit mask. */ -#define USB_RWAKEUP_bp 2 /* Remote Wake-up bit position. */ - -#define USB_GNACK_bm 0x02 /* Global NACK bit mask. */ -#define USB_GNACK_bp 1 /* Global NACK bit position. */ - -#define USB_ATTACH_bm 0x01 /* Attach bit mask. */ -#define USB_ATTACH_bp 0 /* Attach bit position. */ - -/* USB.STATUS bit masks and bit positions */ -#define USB_URESUME_bm 0x08 /* Upstream Resume bit mask. */ -#define USB_URESUME_bp 3 /* Upstream Resume bit position. */ - -#define USB_RESUME_bm 0x04 /* Resume bit mask. */ -#define USB_RESUME_bp 2 /* Resume bit position. */ - -#define USB_SUSPEND_bm 0x02 /* Bus Suspended bit mask. */ -#define USB_SUSPEND_bp 1 /* Bus Suspended bit position. */ - -#define USB_BUSRST_bm 0x01 /* Bus Reset bit mask. */ -#define USB_BUSRST_bp 0 /* Bus Reset bit position. */ - -/* USB.ADDR bit masks and bit positions */ -#define USB_ADDR_gm 0x7F /* Device Address group mask. */ -#define USB_ADDR_gp 0 /* Device Address group position. */ -#define USB_ADDR0_bm (1<<0) /* Device Address bit 0 mask. */ -#define USB_ADDR0_bp 0 /* Device Address bit 0 position. */ -#define USB_ADDR1_bm (1<<1) /* Device Address bit 1 mask. */ -#define USB_ADDR1_bp 1 /* Device Address bit 1 position. */ -#define USB_ADDR2_bm (1<<2) /* Device Address bit 2 mask. */ -#define USB_ADDR2_bp 2 /* Device Address bit 2 position. */ -#define USB_ADDR3_bm (1<<3) /* Device Address bit 3 mask. */ -#define USB_ADDR3_bp 3 /* Device Address bit 3 position. */ -#define USB_ADDR4_bm (1<<4) /* Device Address bit 4 mask. */ -#define USB_ADDR4_bp 4 /* Device Address bit 4 position. */ -#define USB_ADDR5_bm (1<<5) /* Device Address bit 5 mask. */ -#define USB_ADDR5_bp 5 /* Device Address bit 5 position. */ -#define USB_ADDR6_bm (1<<6) /* Device Address bit 6 mask. */ -#define USB_ADDR6_bp 6 /* Device Address bit 6 position. */ - -/* USB.FIFOWP bit masks and bit positions */ -#define USB_FIFOWP_gm 0x1F /* FIFO Write Pointer group mask. */ -#define USB_FIFOWP_gp 0 /* FIFO Write Pointer group position. */ -#define USB_FIFOWP0_bm (1<<0) /* FIFO Write Pointer bit 0 mask. */ -#define USB_FIFOWP0_bp 0 /* FIFO Write Pointer bit 0 position. */ -#define USB_FIFOWP1_bm (1<<1) /* FIFO Write Pointer bit 1 mask. */ -#define USB_FIFOWP1_bp 1 /* FIFO Write Pointer bit 1 position. */ -#define USB_FIFOWP2_bm (1<<2) /* FIFO Write Pointer bit 2 mask. */ -#define USB_FIFOWP2_bp 2 /* FIFO Write Pointer bit 2 position. */ -#define USB_FIFOWP3_bm (1<<3) /* FIFO Write Pointer bit 3 mask. */ -#define USB_FIFOWP3_bp 3 /* FIFO Write Pointer bit 3 position. */ -#define USB_FIFOWP4_bm (1<<4) /* FIFO Write Pointer bit 4 mask. */ -#define USB_FIFOWP4_bp 4 /* FIFO Write Pointer bit 4 position. */ - -/* USB.FIFORP bit masks and bit positions */ -#define USB_FIFORP_gm 0x1F /* FIFO Read Pointer group mask. */ -#define USB_FIFORP_gp 0 /* FIFO Read Pointer group position. */ -#define USB_FIFORP0_bm (1<<0) /* FIFO Read Pointer bit 0 mask. */ -#define USB_FIFORP0_bp 0 /* FIFO Read Pointer bit 0 position. */ -#define USB_FIFORP1_bm (1<<1) /* FIFO Read Pointer bit 1 mask. */ -#define USB_FIFORP1_bp 1 /* FIFO Read Pointer bit 1 position. */ -#define USB_FIFORP2_bm (1<<2) /* FIFO Read Pointer bit 2 mask. */ -#define USB_FIFORP2_bp 2 /* FIFO Read Pointer bit 2 position. */ -#define USB_FIFORP3_bm (1<<3) /* FIFO Read Pointer bit 3 mask. */ -#define USB_FIFORP3_bp 3 /* FIFO Read Pointer bit 3 position. */ -#define USB_FIFORP4_bm (1<<4) /* FIFO Read Pointer bit 4 mask. */ -#define USB_FIFORP4_bp 4 /* FIFO Read Pointer bit 4 position. */ - -/* USB.INTCTRLA bit masks and bit positions */ -#define USB_SOFIE_bm 0x80 /* Start Of Frame Interrupt Enable bit mask. */ -#define USB_SOFIE_bp 7 /* Start Of Frame Interrupt Enable bit position. */ - -#define USB_BUSEVIE_bm 0x40 /* Bus Event Interrupt Enable bit mask. */ -#define USB_BUSEVIE_bp 6 /* Bus Event Interrupt Enable bit position. */ - -#define USB_BUSERRIE_bm 0x20 /* Bus Error Interrupt Enable bit mask. */ -#define USB_BUSERRIE_bp 5 /* Bus Error Interrupt Enable bit position. */ - -#define USB_STALLIE_bm 0x10 /* STALL Interrupt Enable bit mask. */ -#define USB_STALLIE_bp 4 /* STALL Interrupt Enable bit position. */ - -#define USB_INTLVL_gm 0x03 /* Interrupt Level group mask. */ -#define USB_INTLVL_gp 0 /* Interrupt Level group position. */ -#define USB_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */ -#define USB_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */ -#define USB_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ -#define USB_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */ - -/* USB.INTCTRLB bit masks and bit positions */ -#define USB_TRNIE_bm 0x02 /* Transaction Complete Interrupt Enable bit mask. */ -#define USB_TRNIE_bp 1 /* Transaction Complete Interrupt Enable bit position. */ - -#define USB_SETUPIE_bm 0x01 /* SETUP Transaction Complete Interrupt Enable bit mask. */ -#define USB_SETUPIE_bp 0 /* SETUP Transaction Complete Interrupt Enable bit position. */ - -/* USB.INTFLAGSACLR bit masks and bit positions */ -#define USB_SOFIF_bm 0x80 /* Start Of Frame Interrupt Flag bit mask. */ -#define USB_SOFIF_bp 7 /* Start Of Frame Interrupt Flag bit position. */ - -#define USB_SUSPENDIF_bm 0x40 /* Suspend Interrupt Flag bit mask. */ -#define USB_SUSPENDIF_bp 6 /* Suspend Interrupt Flag bit position. */ - -#define USB_RESUMEIF_bm 0x20 /* Resume Interrupt Flag bit mask. */ -#define USB_RESUMEIF_bp 5 /* Resume Interrupt Flag bit position. */ - -#define USB_RSTIF_bm 0x10 /* Reset Interrupt Flag bit mask. */ -#define USB_RSTIF_bp 4 /* Reset Interrupt Flag bit position. */ - -#define USB_CRCIF_bm 0x08 /* Isochronous CRC Error Interrupt Flag bit mask. */ -#define USB_CRCIF_bp 3 /* Isochronous CRC Error Interrupt Flag bit position. */ - -#define USB_UNFIF_bm 0x04 /* Underflow Interrupt Flag bit mask. */ -#define USB_UNFIF_bp 2 /* Underflow Interrupt Flag bit position. */ - -#define USB_OVFIF_bm 0x02 /* Overflow Interrupt Flag bit mask. */ -#define USB_OVFIF_bp 1 /* Overflow Interrupt Flag bit position. */ - -#define USB_STALLIF_bm 0x01 /* STALL Interrupt Flag bit mask. */ -#define USB_STALLIF_bp 0 /* STALL Interrupt Flag bit position. */ - -/* USB.INTFLAGSASET bit masks and bit positions */ -/* USB_SOFIF Predefined. */ -/* USB_SOFIF Predefined. */ - -/* USB_SUSPENDIF Predefined. */ -/* USB_SUSPENDIF Predefined. */ - -/* USB_RESUMEIF Predefined. */ -/* USB_RESUMEIF Predefined. */ - -/* USB_RSTIF Predefined. */ -/* USB_RSTIF Predefined. */ - -/* USB_CRCIF Predefined. */ -/* USB_CRCIF Predefined. */ - -/* USB_UNFIF Predefined. */ -/* USB_UNFIF Predefined. */ - -/* USB_OVFIF Predefined. */ -/* USB_OVFIF Predefined. */ - -/* USB_STALLIF Predefined. */ -/* USB_STALLIF Predefined. */ - -/* USB.INTFLAGSBCLR bit masks and bit positions */ -#define USB_TRNIF_bm 0x02 /* Transaction Complete Interrupt Flag bit mask. */ -#define USB_TRNIF_bp 1 /* Transaction Complete Interrupt Flag bit position. */ - -#define USB_SETUPIF_bm 0x01 /* SETUP Transaction Complete Interrupt Flag bit mask. */ -#define USB_SETUPIF_bp 0 /* SETUP Transaction Complete Interrupt Flag bit position. */ - -/* USB.INTFLAGSBSET bit masks and bit positions */ -/* USB_TRNIF Predefined. */ -/* USB_TRNIF Predefined. */ - -/* USB_SETUPIF Predefined. */ -/* USB_SETUPIF Predefined. */ - -/* PORT - I/O Port Configuration */ -/* PORT.INTCTRL bit masks and bit positions */ -#define PORT_INT1LVL_gm 0x0C /* Port Interrupt 1 Level group mask. */ -#define PORT_INT1LVL_gp 2 /* Port Interrupt 1 Level group position. */ -#define PORT_INT1LVL0_bm (1<<2) /* Port Interrupt 1 Level bit 0 mask. */ -#define PORT_INT1LVL0_bp 2 /* Port Interrupt 1 Level bit 0 position. */ -#define PORT_INT1LVL1_bm (1<<3) /* Port Interrupt 1 Level bit 1 mask. */ -#define PORT_INT1LVL1_bp 3 /* Port Interrupt 1 Level bit 1 position. */ - -#define PORT_INT0LVL_gm 0x03 /* Port Interrupt 0 Level group mask. */ -#define PORT_INT0LVL_gp 0 /* Port Interrupt 0 Level group position. */ -#define PORT_INT0LVL0_bm (1<<0) /* Port Interrupt 0 Level bit 0 mask. */ -#define PORT_INT0LVL0_bp 0 /* Port Interrupt 0 Level bit 0 position. */ -#define PORT_INT0LVL1_bm (1<<1) /* Port Interrupt 0 Level bit 1 mask. */ -#define PORT_INT0LVL1_bp 1 /* Port Interrupt 0 Level bit 1 position. */ - -/* PORT.INTFLAGS bit masks and bit positions */ -#define PORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ -#define PORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ - -#define PORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ -#define PORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ - -/* PORT.REMAP bit masks and bit positions */ -#define PORT_SPI_bm 0x20 /* SPI bit mask. */ -#define PORT_SPI_bp 5 /* SPI bit position. */ - -#define PORT_USART0_bm 0x10 /* USART0 bit mask. */ -#define PORT_USART0_bp 4 /* USART0 bit position. */ - -#define PORT_TC0D_bm 0x08 /* Timer/Counter 0 Output Compare D bit mask. */ -#define PORT_TC0D_bp 3 /* Timer/Counter 0 Output Compare D bit position. */ - -#define PORT_TC0C_bm 0x04 /* Timer/Counter 0 Output Compare C bit mask. */ -#define PORT_TC0C_bp 2 /* Timer/Counter 0 Output Compare C bit position. */ - -#define PORT_TC0B_bm 0x02 /* Timer/Counter 0 Output Compare B bit mask. */ -#define PORT_TC0B_bp 1 /* Timer/Counter 0 Output Compare B bit position. */ - -#define PORT_TC0A_bm 0x01 /* Timer/Counter 0 Output Compare A bit mask. */ -#define PORT_TC0A_bp 0 /* Timer/Counter 0 Output Compare A bit position. */ - -/* PORT.PIN0CTRL bit masks and bit positions */ -#define PORT_SRLEN_bm 0x80 /* Slew Rate Enable bit mask. */ -#define PORT_SRLEN_bp 7 /* Slew Rate Enable bit position. */ - -#define PORT_INVEN_bm 0x40 /* Inverted I/O Enable bit mask. */ -#define PORT_INVEN_bp 6 /* Inverted I/O Enable bit position. */ - -#define PORT_OPC_gm 0x38 /* Output/Pull Configuration group mask. */ -#define PORT_OPC_gp 3 /* Output/Pull Configuration group position. */ -#define PORT_OPC0_bm (1<<3) /* Output/Pull Configuration bit 0 mask. */ -#define PORT_OPC0_bp 3 /* Output/Pull Configuration bit 0 position. */ -#define PORT_OPC1_bm (1<<4) /* Output/Pull Configuration bit 1 mask. */ -#define PORT_OPC1_bp 4 /* Output/Pull Configuration bit 1 position. */ -#define PORT_OPC2_bm (1<<5) /* Output/Pull Configuration bit 2 mask. */ -#define PORT_OPC2_bp 5 /* Output/Pull Configuration bit 2 position. */ - -#define PORT_ISC_gm 0x07 /* Input/Sense Configuration group mask. */ -#define PORT_ISC_gp 0 /* Input/Sense Configuration group position. */ -#define PORT_ISC0_bm (1<<0) /* Input/Sense Configuration bit 0 mask. */ -#define PORT_ISC0_bp 0 /* Input/Sense Configuration bit 0 position. */ -#define PORT_ISC1_bm (1<<1) /* Input/Sense Configuration bit 1 mask. */ -#define PORT_ISC1_bp 1 /* Input/Sense Configuration bit 1 position. */ -#define PORT_ISC2_bm (1<<2) /* Input/Sense Configuration bit 2 mask. */ -#define PORT_ISC2_bp 2 /* Input/Sense Configuration bit 2 position. */ - -/* PORT.PIN1CTRL bit masks and bit positions */ -/* PORT_SRLEN Predefined. */ -/* PORT_SRLEN Predefined. */ - -/* PORT_INVEN Predefined. */ -/* PORT_INVEN Predefined. */ - -/* PORT_OPC Predefined. */ -/* PORT_OPC Predefined. */ - -/* PORT_ISC Predefined. */ -/* PORT_ISC Predefined. */ - -/* PORT.PIN2CTRL bit masks and bit positions */ -/* PORT_SRLEN Predefined. */ -/* PORT_SRLEN Predefined. */ - -/* PORT_INVEN Predefined. */ -/* PORT_INVEN Predefined. */ - -/* PORT_OPC Predefined. */ -/* PORT_OPC Predefined. */ - -/* PORT_ISC Predefined. */ -/* PORT_ISC Predefined. */ - -/* PORT.PIN3CTRL bit masks and bit positions */ -/* PORT_SRLEN Predefined. */ -/* PORT_SRLEN Predefined. */ - -/* PORT_INVEN Predefined. */ -/* PORT_INVEN Predefined. */ - -/* PORT_OPC Predefined. */ -/* PORT_OPC Predefined. */ - -/* PORT_ISC Predefined. */ -/* PORT_ISC Predefined. */ - -/* PORT.PIN4CTRL bit masks and bit positions */ -/* PORT_SRLEN Predefined. */ -/* PORT_SRLEN Predefined. */ - -/* PORT_INVEN Predefined. */ -/* PORT_INVEN Predefined. */ - -/* PORT_OPC Predefined. */ -/* PORT_OPC Predefined. */ - -/* PORT_ISC Predefined. */ -/* PORT_ISC Predefined. */ - -/* PORT.PIN5CTRL bit masks and bit positions */ -/* PORT_SRLEN Predefined. */ -/* PORT_SRLEN Predefined. */ - -/* PORT_INVEN Predefined. */ -/* PORT_INVEN Predefined. */ - -/* PORT_OPC Predefined. */ -/* PORT_OPC Predefined. */ - -/* PORT_ISC Predefined. */ -/* PORT_ISC Predefined. */ - -/* PORT.PIN6CTRL bit masks and bit positions */ -/* PORT_SRLEN Predefined. */ -/* PORT_SRLEN Predefined. */ - -/* PORT_INVEN Predefined. */ -/* PORT_INVEN Predefined. */ - -/* PORT_OPC Predefined. */ -/* PORT_OPC Predefined. */ - -/* PORT_ISC Predefined. */ -/* PORT_ISC Predefined. */ - -/* PORT.PIN7CTRL bit masks and bit positions */ -/* PORT_SRLEN Predefined. */ -/* PORT_SRLEN Predefined. */ - -/* PORT_INVEN Predefined. */ -/* PORT_INVEN Predefined. */ - -/* PORT_OPC Predefined. */ -/* PORT_OPC Predefined. */ - -/* PORT_ISC Predefined. */ -/* PORT_ISC Predefined. */ - -/* TC - 16-bit Timer/Counter With PWM */ -/* TC0.CTRLA bit masks and bit positions */ -#define TC0_CLKSEL_gm 0x0F /* Clock Selection group mask. */ -#define TC0_CLKSEL_gp 0 /* Clock Selection group position. */ -#define TC0_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ -#define TC0_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ -#define TC0_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ -#define TC0_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ -#define TC0_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ -#define TC0_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ -#define TC0_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ -#define TC0_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ - -/* TC0.CTRLB bit masks and bit positions */ -#define TC0_CCDEN_bm 0x80 /* Compare or Capture D Enable bit mask. */ -#define TC0_CCDEN_bp 7 /* Compare or Capture D Enable bit position. */ - -#define TC0_CCCEN_bm 0x40 /* Compare or Capture C Enable bit mask. */ -#define TC0_CCCEN_bp 6 /* Compare or Capture C Enable bit position. */ - -#define TC0_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ -#define TC0_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ - -#define TC0_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ -#define TC0_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ - -#define TC0_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ -#define TC0_WGMODE_gp 0 /* Waveform generation mode group position. */ -#define TC0_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ -#define TC0_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ -#define TC0_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ -#define TC0_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ -#define TC0_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ -#define TC0_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ - -/* TC0.CTRLC bit masks and bit positions */ -#define TC0_CMPD_bm 0x08 /* Compare D Output Value bit mask. */ -#define TC0_CMPD_bp 3 /* Compare D Output Value bit position. */ - -#define TC0_CMPC_bm 0x04 /* Compare C Output Value bit mask. */ -#define TC0_CMPC_bp 2 /* Compare C Output Value bit position. */ - -#define TC0_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ -#define TC0_CMPB_bp 1 /* Compare B Output Value bit position. */ - -#define TC0_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ -#define TC0_CMPA_bp 0 /* Compare A Output Value bit position. */ - -/* TC0.CTRLD bit masks and bit positions */ -#define TC0_EVACT_gm 0xE0 /* Event Action group mask. */ -#define TC0_EVACT_gp 5 /* Event Action group position. */ -#define TC0_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ -#define TC0_EVACT0_bp 5 /* Event Action bit 0 position. */ -#define TC0_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ -#define TC0_EVACT1_bp 6 /* Event Action bit 1 position. */ -#define TC0_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ -#define TC0_EVACT2_bp 7 /* Event Action bit 2 position. */ - -#define TC0_EVDLY_bm 0x10 /* Event Delay bit mask. */ -#define TC0_EVDLY_bp 4 /* Event Delay bit position. */ - -#define TC0_EVSEL_gm 0x0F /* Event Source Select group mask. */ -#define TC0_EVSEL_gp 0 /* Event Source Select group position. */ -#define TC0_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ -#define TC0_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ -#define TC0_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ -#define TC0_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ -#define TC0_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ -#define TC0_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ -#define TC0_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ -#define TC0_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ - -/* TC0.CTRLE bit masks and bit positions */ -#define TC0_BYTEM_gm 0x03 /* Byte Mode group mask. */ -#define TC0_BYTEM_gp 0 /* Byte Mode group position. */ -#define TC0_BYTEM0_bm (1<<0) /* Byte Mode bit 0 mask. */ -#define TC0_BYTEM0_bp 0 /* Byte Mode bit 0 position. */ -#define TC0_BYTEM1_bm (1<<1) /* Byte Mode bit 1 mask. */ -#define TC0_BYTEM1_bp 1 /* Byte Mode bit 1 position. */ - -/* TC0.INTCTRLA bit masks and bit positions */ -#define TC0_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ -#define TC0_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ -#define TC0_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ -#define TC0_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ -#define TC0_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ -#define TC0_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ - -#define TC0_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ -#define TC0_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ -#define TC0_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ -#define TC0_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ -#define TC0_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ -#define TC0_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ - -/* TC0.INTCTRLB bit masks and bit positions */ -#define TC0_CCDINTLVL_gm 0xC0 /* Compare or Capture D Interrupt Level group mask. */ -#define TC0_CCDINTLVL_gp 6 /* Compare or Capture D Interrupt Level group position. */ -#define TC0_CCDINTLVL0_bm (1<<6) /* Compare or Capture D Interrupt Level bit 0 mask. */ -#define TC0_CCDINTLVL0_bp 6 /* Compare or Capture D Interrupt Level bit 0 position. */ -#define TC0_CCDINTLVL1_bm (1<<7) /* Compare or Capture D Interrupt Level bit 1 mask. */ -#define TC0_CCDINTLVL1_bp 7 /* Compare or Capture D Interrupt Level bit 1 position. */ - -#define TC0_CCCINTLVL_gm 0x30 /* Compare or Capture C Interrupt Level group mask. */ -#define TC0_CCCINTLVL_gp 4 /* Compare or Capture C Interrupt Level group position. */ -#define TC0_CCCINTLVL0_bm (1<<4) /* Compare or Capture C Interrupt Level bit 0 mask. */ -#define TC0_CCCINTLVL0_bp 4 /* Compare or Capture C Interrupt Level bit 0 position. */ -#define TC0_CCCINTLVL1_bm (1<<5) /* Compare or Capture C Interrupt Level bit 1 mask. */ -#define TC0_CCCINTLVL1_bp 5 /* Compare or Capture C Interrupt Level bit 1 position. */ - -#define TC0_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ -#define TC0_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ -#define TC0_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ -#define TC0_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ -#define TC0_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ -#define TC0_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ - -#define TC0_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ -#define TC0_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ -#define TC0_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ -#define TC0_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ -#define TC0_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ -#define TC0_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ - -/* TC0.CTRLFCLR bit masks and bit positions */ -#define TC0_CMD_gm 0x0C /* Command group mask. */ -#define TC0_CMD_gp 2 /* Command group position. */ -#define TC0_CMD0_bm (1<<2) /* Command bit 0 mask. */ -#define TC0_CMD0_bp 2 /* Command bit 0 position. */ -#define TC0_CMD1_bm (1<<3) /* Command bit 1 mask. */ -#define TC0_CMD1_bp 3 /* Command bit 1 position. */ - -#define TC0_LUPD_bm 0x02 /* Lock Update bit mask. */ -#define TC0_LUPD_bp 1 /* Lock Update bit position. */ - -#define TC0_DIR_bm 0x01 /* Direction bit mask. */ -#define TC0_DIR_bp 0 /* Direction bit position. */ - -/* TC0.CTRLFSET bit masks and bit positions */ -/* TC0_CMD Predefined. */ -/* TC0_CMD Predefined. */ - -/* TC0_LUPD Predefined. */ -/* TC0_LUPD Predefined. */ - -/* TC0_DIR Predefined. */ -/* TC0_DIR Predefined. */ - -/* TC0.CTRLGCLR bit masks and bit positions */ -#define TC0_CCDBV_bm 0x10 /* Compare or Capture D Buffer Valid bit mask. */ -#define TC0_CCDBV_bp 4 /* Compare or Capture D Buffer Valid bit position. */ - -#define TC0_CCCBV_bm 0x08 /* Compare or Capture C Buffer Valid bit mask. */ -#define TC0_CCCBV_bp 3 /* Compare or Capture C Buffer Valid bit position. */ - -#define TC0_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ -#define TC0_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ - -#define TC0_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ -#define TC0_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ - -#define TC0_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ -#define TC0_PERBV_bp 0 /* Period Buffer Valid bit position. */ - -/* TC0.CTRLGSET bit masks and bit positions */ -/* TC0_CCDBV Predefined. */ -/* TC0_CCDBV Predefined. */ - -/* TC0_CCCBV Predefined. */ -/* TC0_CCCBV Predefined. */ - -/* TC0_CCBBV Predefined. */ -/* TC0_CCBBV Predefined. */ - -/* TC0_CCABV Predefined. */ -/* TC0_CCABV Predefined. */ - -/* TC0_PERBV Predefined. */ -/* TC0_PERBV Predefined. */ - -/* TC0.INTFLAGS bit masks and bit positions */ -#define TC0_CCDIF_bm 0x80 /* Compare or Capture D Interrupt Flag bit mask. */ -#define TC0_CCDIF_bp 7 /* Compare or Capture D Interrupt Flag bit position. */ - -#define TC0_CCCIF_bm 0x40 /* Compare or Capture C Interrupt Flag bit mask. */ -#define TC0_CCCIF_bp 6 /* Compare or Capture C Interrupt Flag bit position. */ - -#define TC0_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ -#define TC0_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ - -#define TC0_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ -#define TC0_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ - -#define TC0_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ -#define TC0_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ - -#define TC0_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ -#define TC0_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ - -/* TC1.CTRLA bit masks and bit positions */ -#define TC1_CLKSEL_gm 0x0F /* Clock Selection group mask. */ -#define TC1_CLKSEL_gp 0 /* Clock Selection group position. */ -#define TC1_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ -#define TC1_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ -#define TC1_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ -#define TC1_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ -#define TC1_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ -#define TC1_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ -#define TC1_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ -#define TC1_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ - -/* TC1.CTRLB bit masks and bit positions */ -#define TC1_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ -#define TC1_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ - -#define TC1_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ -#define TC1_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ - -#define TC1_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ -#define TC1_WGMODE_gp 0 /* Waveform generation mode group position. */ -#define TC1_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ -#define TC1_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ -#define TC1_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ -#define TC1_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ -#define TC1_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ -#define TC1_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ - -/* TC1.CTRLC bit masks and bit positions */ -#define TC1_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ -#define TC1_CMPB_bp 1 /* Compare B Output Value bit position. */ - -#define TC1_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ -#define TC1_CMPA_bp 0 /* Compare A Output Value bit position. */ - -/* TC1.CTRLD bit masks and bit positions */ -#define TC1_EVACT_gm 0xE0 /* Event Action group mask. */ -#define TC1_EVACT_gp 5 /* Event Action group position. */ -#define TC1_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ -#define TC1_EVACT0_bp 5 /* Event Action bit 0 position. */ -#define TC1_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ -#define TC1_EVACT1_bp 6 /* Event Action bit 1 position. */ -#define TC1_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ -#define TC1_EVACT2_bp 7 /* Event Action bit 2 position. */ - -#define TC1_EVDLY_bm 0x10 /* Event Delay bit mask. */ -#define TC1_EVDLY_bp 4 /* Event Delay bit position. */ - -#define TC1_EVSEL_gm 0x0F /* Event Source Select group mask. */ -#define TC1_EVSEL_gp 0 /* Event Source Select group position. */ -#define TC1_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ -#define TC1_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ -#define TC1_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ -#define TC1_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ -#define TC1_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ -#define TC1_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ -#define TC1_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ -#define TC1_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ - -/* TC1.CTRLE bit masks and bit positions */ -#define TC1_BYTEM_bm 0x01 /* Byte Mode bit mask. */ -#define TC1_BYTEM_bp 0 /* Byte Mode bit position. */ - -/* TC1.INTCTRLA bit masks and bit positions */ -#define TC1_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ -#define TC1_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ -#define TC1_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ -#define TC1_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ -#define TC1_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ -#define TC1_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ - -#define TC1_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ -#define TC1_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ -#define TC1_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ -#define TC1_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ -#define TC1_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ -#define TC1_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ - -/* TC1.INTCTRLB bit masks and bit positions */ -#define TC1_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ -#define TC1_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ -#define TC1_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ -#define TC1_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ -#define TC1_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ -#define TC1_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ - -#define TC1_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ -#define TC1_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ -#define TC1_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ -#define TC1_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ -#define TC1_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ -#define TC1_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ - -/* TC1.CTRLFCLR bit masks and bit positions */ -#define TC1_CMD_gm 0x0C /* Command group mask. */ -#define TC1_CMD_gp 2 /* Command group position. */ -#define TC1_CMD0_bm (1<<2) /* Command bit 0 mask. */ -#define TC1_CMD0_bp 2 /* Command bit 0 position. */ -#define TC1_CMD1_bm (1<<3) /* Command bit 1 mask. */ -#define TC1_CMD1_bp 3 /* Command bit 1 position. */ - -#define TC1_LUPD_bm 0x02 /* Lock Update bit mask. */ -#define TC1_LUPD_bp 1 /* Lock Update bit position. */ - -#define TC1_DIR_bm 0x01 /* Direction bit mask. */ -#define TC1_DIR_bp 0 /* Direction bit position. */ - -/* TC1.CTRLFSET bit masks and bit positions */ -/* TC1_CMD Predefined. */ -/* TC1_CMD Predefined. */ - -/* TC1_LUPD Predefined. */ -/* TC1_LUPD Predefined. */ - -/* TC1_DIR Predefined. */ -/* TC1_DIR Predefined. */ - -/* TC1.CTRLGCLR bit masks and bit positions */ -#define TC1_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ -#define TC1_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ - -#define TC1_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ -#define TC1_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ - -#define TC1_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ -#define TC1_PERBV_bp 0 /* Period Buffer Valid bit position. */ - -/* TC1.CTRLGSET bit masks and bit positions */ -/* TC1_CCBBV Predefined. */ -/* TC1_CCBBV Predefined. */ - -/* TC1_CCABV Predefined. */ -/* TC1_CCABV Predefined. */ - -/* TC1_PERBV Predefined. */ -/* TC1_PERBV Predefined. */ - -/* TC1.INTFLAGS bit masks and bit positions */ -#define TC1_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ -#define TC1_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ - -#define TC1_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ -#define TC1_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ - -#define TC1_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ -#define TC1_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ - -#define TC1_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ -#define TC1_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ - -/* TC2 - 16-bit Timer/Counter type 2 */ -/* TC2.CTRLA bit masks and bit positions */ -#define TC2_CLKSEL_gm 0x0F /* Clock Selection group mask. */ -#define TC2_CLKSEL_gp 0 /* Clock Selection group position. */ -#define TC2_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ -#define TC2_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ -#define TC2_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ -#define TC2_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ -#define TC2_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ -#define TC2_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ -#define TC2_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ -#define TC2_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ - -/* TC2.CTRLB bit masks and bit positions */ -#define TC2_HCMPDEN_bm 0x80 /* High Byte Compare D Enable bit mask. */ -#define TC2_HCMPDEN_bp 7 /* High Byte Compare D Enable bit position. */ - -#define TC2_HCMPCEN_bm 0x40 /* High Byte Compare C Enable bit mask. */ -#define TC2_HCMPCEN_bp 6 /* High Byte Compare C Enable bit position. */ - -#define TC2_HCMPBEN_bm 0x20 /* High Byte Compare B Enable bit mask. */ -#define TC2_HCMPBEN_bp 5 /* High Byte Compare B Enable bit position. */ - -#define TC2_HCMPAEN_bm 0x10 /* High Byte Compare A Enable bit mask. */ -#define TC2_HCMPAEN_bp 4 /* High Byte Compare A Enable bit position. */ - -#define TC2_LCMPDEN_bm 0x08 /* Low Byte Compare D Enable bit mask. */ -#define TC2_LCMPDEN_bp 3 /* Low Byte Compare D Enable bit position. */ - -#define TC2_LCMPCEN_bm 0x04 /* Low Byte Compare C Enable bit mask. */ -#define TC2_LCMPCEN_bp 2 /* Low Byte Compare C Enable bit position. */ - -#define TC2_LCMPBEN_bm 0x02 /* Low Byte Compare B Enable bit mask. */ -#define TC2_LCMPBEN_bp 1 /* Low Byte Compare B Enable bit position. */ - -#define TC2_LCMPAEN_bm 0x01 /* Low Byte Compare A Enable bit mask. */ -#define TC2_LCMPAEN_bp 0 /* Low Byte Compare A Enable bit position. */ - -/* TC2.CTRLC bit masks and bit positions */ -#define TC2_HCMPD_bm 0x80 /* High Byte Compare D Output Value bit mask. */ -#define TC2_HCMPD_bp 7 /* High Byte Compare D Output Value bit position. */ - -#define TC2_HCMPC_bm 0x40 /* High Byte Compare C Output Value bit mask. */ -#define TC2_HCMPC_bp 6 /* High Byte Compare C Output Value bit position. */ - -#define TC2_HCMPB_bm 0x20 /* High Byte Compare B Output Value bit mask. */ -#define TC2_HCMPB_bp 5 /* High Byte Compare B Output Value bit position. */ - -#define TC2_HCMPA_bm 0x10 /* High Byte Compare A Output Value bit mask. */ -#define TC2_HCMPA_bp 4 /* High Byte Compare A Output Value bit position. */ - -#define TC2_LCMPD_bm 0x08 /* Low Byte Compare D Output Value bit mask. */ -#define TC2_LCMPD_bp 3 /* Low Byte Compare D Output Value bit position. */ - -#define TC2_LCMPC_bm 0x04 /* Low Byte Compare C Output Value bit mask. */ -#define TC2_LCMPC_bp 2 /* Low Byte Compare C Output Value bit position. */ - -#define TC2_LCMPB_bm 0x02 /* Low Byte Compare B Output Value bit mask. */ -#define TC2_LCMPB_bp 1 /* Low Byte Compare B Output Value bit position. */ - -#define TC2_LCMPA_bm 0x01 /* Low Byte Compare A Output Value bit mask. */ -#define TC2_LCMPA_bp 0 /* Low Byte Compare A Output Value bit position. */ - -/* TC2.CTRLE bit masks and bit positions */ -#define TC2_BYTEM_gm 0x03 /* Byte Mode group mask. */ -#define TC2_BYTEM_gp 0 /* Byte Mode group position. */ -#define TC2_BYTEM0_bm (1<<0) /* Byte Mode bit 0 mask. */ -#define TC2_BYTEM0_bp 0 /* Byte Mode bit 0 position. */ -#define TC2_BYTEM1_bm (1<<1) /* Byte Mode bit 1 mask. */ -#define TC2_BYTEM1_bp 1 /* Byte Mode bit 1 position. */ - -/* TC2.INTCTRLA bit masks and bit positions */ -#define TC2_HUNFINTLVL_gm 0x0C /* High Byte Underflow Interrupt Level group mask. */ -#define TC2_HUNFINTLVL_gp 2 /* High Byte Underflow Interrupt Level group position. */ -#define TC2_HUNFINTLVL0_bm (1<<2) /* High Byte Underflow Interrupt Level bit 0 mask. */ -#define TC2_HUNFINTLVL0_bp 2 /* High Byte Underflow Interrupt Level bit 0 position. */ -#define TC2_HUNFINTLVL1_bm (1<<3) /* High Byte Underflow Interrupt Level bit 1 mask. */ -#define TC2_HUNFINTLVL1_bp 3 /* High Byte Underflow Interrupt Level bit 1 position. */ - -#define TC2_LUNFINTLVL_gm 0x03 /* Low Byte Underflow interrupt level group mask. */ -#define TC2_LUNFINTLVL_gp 0 /* Low Byte Underflow interrupt level group position. */ -#define TC2_LUNFINTLVL0_bm (1<<0) /* Low Byte Underflow interrupt level bit 0 mask. */ -#define TC2_LUNFINTLVL0_bp 0 /* Low Byte Underflow interrupt level bit 0 position. */ -#define TC2_LUNFINTLVL1_bm (1<<1) /* Low Byte Underflow interrupt level bit 1 mask. */ -#define TC2_LUNFINTLVL1_bp 1 /* Low Byte Underflow interrupt level bit 1 position. */ - -/* TC2.INTCTRLB bit masks and bit positions */ -#define TC2_LCMPDINTLVL_gm 0xC0 /* Low Byte Compare D Interrupt Level group mask. */ -#define TC2_LCMPDINTLVL_gp 6 /* Low Byte Compare D Interrupt Level group position. */ -#define TC2_LCMPDINTLVL0_bm (1<<6) /* Low Byte Compare D Interrupt Level bit 0 mask. */ -#define TC2_LCMPDINTLVL0_bp 6 /* Low Byte Compare D Interrupt Level bit 0 position. */ -#define TC2_LCMPDINTLVL1_bm (1<<7) /* Low Byte Compare D Interrupt Level bit 1 mask. */ -#define TC2_LCMPDINTLVL1_bp 7 /* Low Byte Compare D Interrupt Level bit 1 position. */ - -#define TC2_LCMPCINTLVL_gm 0x30 /* Low Byte Compare C Interrupt Level group mask. */ -#define TC2_LCMPCINTLVL_gp 4 /* Low Byte Compare C Interrupt Level group position. */ -#define TC2_LCMPCINTLVL0_bm (1<<4) /* Low Byte Compare C Interrupt Level bit 0 mask. */ -#define TC2_LCMPCINTLVL0_bp 4 /* Low Byte Compare C Interrupt Level bit 0 position. */ -#define TC2_LCMPCINTLVL1_bm (1<<5) /* Low Byte Compare C Interrupt Level bit 1 mask. */ -#define TC2_LCMPCINTLVL1_bp 5 /* Low Byte Compare C Interrupt Level bit 1 position. */ - -#define TC2_LCMPBINTLVL_gm 0x0C /* Low Byte Compare B Interrupt Level group mask. */ -#define TC2_LCMPBINTLVL_gp 2 /* Low Byte Compare B Interrupt Level group position. */ -#define TC2_LCMPBINTLVL0_bm (1<<2) /* Low Byte Compare B Interrupt Level bit 0 mask. */ -#define TC2_LCMPBINTLVL0_bp 2 /* Low Byte Compare B Interrupt Level bit 0 position. */ -#define TC2_LCMPBINTLVL1_bm (1<<3) /* Low Byte Compare B Interrupt Level bit 1 mask. */ -#define TC2_LCMPBINTLVL1_bp 3 /* Low Byte Compare B Interrupt Level bit 1 position. */ - -#define TC2_LCMPAINTLVL_gm 0x03 /* Low Byte Compare A Interrupt Level group mask. */ -#define TC2_LCMPAINTLVL_gp 0 /* Low Byte Compare A Interrupt Level group position. */ -#define TC2_LCMPAINTLVL0_bm (1<<0) /* Low Byte Compare A Interrupt Level bit 0 mask. */ -#define TC2_LCMPAINTLVL0_bp 0 /* Low Byte Compare A Interrupt Level bit 0 position. */ -#define TC2_LCMPAINTLVL1_bm (1<<1) /* Low Byte Compare A Interrupt Level bit 1 mask. */ -#define TC2_LCMPAINTLVL1_bp 1 /* Low Byte Compare A Interrupt Level bit 1 position. */ - -/* TC2.CTRLF bit masks and bit positions */ -#define TC2_CMD_gm 0x0C /* Command group mask. */ -#define TC2_CMD_gp 2 /* Command group position. */ -#define TC2_CMD0_bm (1<<2) /* Command bit 0 mask. */ -#define TC2_CMD0_bp 2 /* Command bit 0 position. */ -#define TC2_CMD1_bm (1<<3) /* Command bit 1 mask. */ -#define TC2_CMD1_bp 3 /* Command bit 1 position. */ - -#define TC2_CMDEN_gm 0x03 /* Command Enable group mask. */ -#define TC2_CMDEN_gp 0 /* Command Enable group position. */ -#define TC2_CMDEN0_bm (1<<0) /* Command Enable bit 0 mask. */ -#define TC2_CMDEN0_bp 0 /* Command Enable bit 0 position. */ -#define TC2_CMDEN1_bm (1<<1) /* Command Enable bit 1 mask. */ -#define TC2_CMDEN1_bp 1 /* Command Enable bit 1 position. */ - -/* TC2.INTFLAGS bit masks and bit positions */ -#define TC2_LCMPDIF_bm 0x80 /* Low Byte Compare D Interrupt Flag bit mask. */ -#define TC2_LCMPDIF_bp 7 /* Low Byte Compare D Interrupt Flag bit position. */ - -#define TC2_LCMPCIF_bm 0x40 /* Low Byte Compare C Interrupt Flag bit mask. */ -#define TC2_LCMPCIF_bp 6 /* Low Byte Compare C Interrupt Flag bit position. */ - -#define TC2_LCMPBIF_bm 0x20 /* Low Byte Compare B Interrupt Flag bit mask. */ -#define TC2_LCMPBIF_bp 5 /* Low Byte Compare B Interrupt Flag bit position. */ - -#define TC2_LCMPAIF_bm 0x10 /* Low Byte Compare A Interrupt Flag bit mask. */ -#define TC2_LCMPAIF_bp 4 /* Low Byte Compare A Interrupt Flag bit position. */ - -#define TC2_HUNFIF_bm 0x02 /* High Byte Underflow Interrupt Flag bit mask. */ -#define TC2_HUNFIF_bp 1 /* High Byte Underflow Interrupt Flag bit position. */ - -#define TC2_LUNFIF_bm 0x01 /* Low Byte Underflow Interrupt Flag bit mask. */ -#define TC2_LUNFIF_bp 0 /* Low Byte Underflow Interrupt Flag bit position. */ - -/* AWEX - Timer/Counter Advanced Waveform Extension */ -/* AWEX.CTRL bit masks and bit positions */ -#define AWEX_PGM_bm 0x20 /* Pattern Generation Mode bit mask. */ -#define AWEX_PGM_bp 5 /* Pattern Generation Mode bit position. */ - -#define AWEX_CWCM_bm 0x10 /* Common Waveform Channel Mode bit mask. */ -#define AWEX_CWCM_bp 4 /* Common Waveform Channel Mode bit position. */ - -#define AWEX_DTICCDEN_bm 0x08 /* Dead Time Insertion Compare Channel D Enable bit mask. */ -#define AWEX_DTICCDEN_bp 3 /* Dead Time Insertion Compare Channel D Enable bit position. */ - -#define AWEX_DTICCCEN_bm 0x04 /* Dead Time Insertion Compare Channel C Enable bit mask. */ -#define AWEX_DTICCCEN_bp 2 /* Dead Time Insertion Compare Channel C Enable bit position. */ - -#define AWEX_DTICCBEN_bm 0x02 /* Dead Time Insertion Compare Channel B Enable bit mask. */ -#define AWEX_DTICCBEN_bp 1 /* Dead Time Insertion Compare Channel B Enable bit position. */ - -#define AWEX_DTICCAEN_bm 0x01 /* Dead Time Insertion Compare Channel A Enable bit mask. */ -#define AWEX_DTICCAEN_bp 0 /* Dead Time Insertion Compare Channel A Enable bit position. */ - -/* AWEX.FDCTRL bit masks and bit positions */ -#define AWEX_FDDBD_bm 0x10 /* Fault Detect on Disable Break Disable bit mask. */ -#define AWEX_FDDBD_bp 4 /* Fault Detect on Disable Break Disable bit position. */ - -#define AWEX_FDMODE_bm 0x04 /* Fault Detect Mode bit mask. */ -#define AWEX_FDMODE_bp 2 /* Fault Detect Mode bit position. */ - -#define AWEX_FDACT_gm 0x03 /* Fault Detect Action group mask. */ -#define AWEX_FDACT_gp 0 /* Fault Detect Action group position. */ -#define AWEX_FDACT0_bm (1<<0) /* Fault Detect Action bit 0 mask. */ -#define AWEX_FDACT0_bp 0 /* Fault Detect Action bit 0 position. */ -#define AWEX_FDACT1_bm (1<<1) /* Fault Detect Action bit 1 mask. */ -#define AWEX_FDACT1_bp 1 /* Fault Detect Action bit 1 position. */ - -/* AWEX.STATUS bit masks and bit positions */ -#define AWEX_FDF_bm 0x04 /* Fault Detect Flag bit mask. */ -#define AWEX_FDF_bp 2 /* Fault Detect Flag bit position. */ - -#define AWEX_DTHSBUFV_bm 0x02 /* Dead Time High Side Buffer Valid bit mask. */ -#define AWEX_DTHSBUFV_bp 1 /* Dead Time High Side Buffer Valid bit position. */ - -#define AWEX_DTLSBUFV_bm 0x01 /* Dead Time Low Side Buffer Valid bit mask. */ -#define AWEX_DTLSBUFV_bp 0 /* Dead Time Low Side Buffer Valid bit position. */ - -/* AWEX.STATUSSET bit masks and bit positions */ -/* AWEX_FDF Predefined. */ -/* AWEX_FDF Predefined. */ - -/* AWEX_DTHSBUFV Predefined. */ -/* AWEX_DTHSBUFV Predefined. */ - -/* AWEX_DTLSBUFV Predefined. */ -/* AWEX_DTLSBUFV Predefined. */ - -/* HIRES - Timer/Counter High-Resolution Extension */ -/* HIRES.CTRLA bit masks and bit positions */ -#define HIRES_HREN_gm 0x03 /* High Resolution Enable group mask. */ -#define HIRES_HREN_gp 0 /* High Resolution Enable group position. */ -#define HIRES_HREN0_bm (1<<0) /* High Resolution Enable bit 0 mask. */ -#define HIRES_HREN0_bp 0 /* High Resolution Enable bit 0 position. */ -#define HIRES_HREN1_bm (1<<1) /* High Resolution Enable bit 1 mask. */ -#define HIRES_HREN1_bp 1 /* High Resolution Enable bit 1 position. */ - -/* USART - Universal Asynchronous Receiver-Transmitter */ -/* USART.STATUS bit masks and bit positions */ -#define USART_RXCIF_bm 0x80 /* Receive Interrupt Flag bit mask. */ -#define USART_RXCIF_bp 7 /* Receive Interrupt Flag bit position. */ - -#define USART_TXCIF_bm 0x40 /* Transmit Interrupt Flag bit mask. */ -#define USART_TXCIF_bp 6 /* Transmit Interrupt Flag bit position. */ - -#define USART_DREIF_bm 0x20 /* Data Register Empty Flag bit mask. */ -#define USART_DREIF_bp 5 /* Data Register Empty Flag bit position. */ - -#define USART_FERR_bm 0x10 /* Frame Error bit mask. */ -#define USART_FERR_bp 4 /* Frame Error bit position. */ - -#define USART_BUFOVF_bm 0x08 /* Buffer Overflow bit mask. */ -#define USART_BUFOVF_bp 3 /* Buffer Overflow bit position. */ - -#define USART_PERR_bm 0x04 /* Parity Error bit mask. */ -#define USART_PERR_bp 2 /* Parity Error bit position. */ - -#define USART_RXB8_bm 0x01 /* Receive Bit 8 bit mask. */ -#define USART_RXB8_bp 0 /* Receive Bit 8 bit position. */ - -/* USART.CTRLA bit masks and bit positions */ -#define USART_RXCINTLVL_gm 0x30 /* Receive Interrupt Level group mask. */ -#define USART_RXCINTLVL_gp 4 /* Receive Interrupt Level group position. */ -#define USART_RXCINTLVL0_bm (1<<4) /* Receive Interrupt Level bit 0 mask. */ -#define USART_RXCINTLVL0_bp 4 /* Receive Interrupt Level bit 0 position. */ -#define USART_RXCINTLVL1_bm (1<<5) /* Receive Interrupt Level bit 1 mask. */ -#define USART_RXCINTLVL1_bp 5 /* Receive Interrupt Level bit 1 position. */ - -#define USART_TXCINTLVL_gm 0x0C /* Transmit Interrupt Level group mask. */ -#define USART_TXCINTLVL_gp 2 /* Transmit Interrupt Level group position. */ -#define USART_TXCINTLVL0_bm (1<<2) /* Transmit Interrupt Level bit 0 mask. */ -#define USART_TXCINTLVL0_bp 2 /* Transmit Interrupt Level bit 0 position. */ -#define USART_TXCINTLVL1_bm (1<<3) /* Transmit Interrupt Level bit 1 mask. */ -#define USART_TXCINTLVL1_bp 3 /* Transmit Interrupt Level bit 1 position. */ - -#define USART_DREINTLVL_gm 0x03 /* Data Register Empty Interrupt Level group mask. */ -#define USART_DREINTLVL_gp 0 /* Data Register Empty Interrupt Level group position. */ -#define USART_DREINTLVL0_bm (1<<0) /* Data Register Empty Interrupt Level bit 0 mask. */ -#define USART_DREINTLVL0_bp 0 /* Data Register Empty Interrupt Level bit 0 position. */ -#define USART_DREINTLVL1_bm (1<<1) /* Data Register Empty Interrupt Level bit 1 mask. */ -#define USART_DREINTLVL1_bp 1 /* Data Register Empty Interrupt Level bit 1 position. */ - -/* USART.CTRLB bit masks and bit positions */ -#define USART_RXEN_bm 0x10 /* Receiver Enable bit mask. */ -#define USART_RXEN_bp 4 /* Receiver Enable bit position. */ - -#define USART_TXEN_bm 0x08 /* Transmitter Enable bit mask. */ -#define USART_TXEN_bp 3 /* Transmitter Enable bit position. */ - -#define USART_CLK2X_bm 0x04 /* Double transmission speed bit mask. */ -#define USART_CLK2X_bp 2 /* Double transmission speed bit position. */ - -#define USART_MPCM_bm 0x02 /* Multi-processor Communication Mode bit mask. */ -#define USART_MPCM_bp 1 /* Multi-processor Communication Mode bit position. */ - -#define USART_TXB8_bm 0x01 /* Transmit bit 8 bit mask. */ -#define USART_TXB8_bp 0 /* Transmit bit 8 bit position. */ - -/* USART.CTRLC bit masks and bit positions */ -#define USART_CMODE_gm 0xC0 /* Communication Mode group mask. */ -#define USART_CMODE_gp 6 /* Communication Mode group position. */ -#define USART_CMODE0_bm (1<<6) /* Communication Mode bit 0 mask. */ -#define USART_CMODE0_bp 6 /* Communication Mode bit 0 position. */ -#define USART_CMODE1_bm (1<<7) /* Communication Mode bit 1 mask. */ -#define USART_CMODE1_bp 7 /* Communication Mode bit 1 position. */ - -#define USART_PMODE_gm 0x30 /* Parity Mode group mask. */ -#define USART_PMODE_gp 4 /* Parity Mode group position. */ -#define USART_PMODE0_bm (1<<4) /* Parity Mode bit 0 mask. */ -#define USART_PMODE0_bp 4 /* Parity Mode bit 0 position. */ -#define USART_PMODE1_bm (1<<5) /* Parity Mode bit 1 mask. */ -#define USART_PMODE1_bp 5 /* Parity Mode bit 1 position. */ - -#define USART_SBMODE_bm 0x08 /* Stop Bit Mode bit mask. */ -#define USART_SBMODE_bp 3 /* Stop Bit Mode bit position. */ - -#define USART_CHSIZE_gm 0x07 /* Character Size group mask. */ -#define USART_CHSIZE_gp 0 /* Character Size group position. */ -#define USART_CHSIZE0_bm (1<<0) /* Character Size bit 0 mask. */ -#define USART_CHSIZE0_bp 0 /* Character Size bit 0 position. */ -#define USART_CHSIZE1_bm (1<<1) /* Character Size bit 1 mask. */ -#define USART_CHSIZE1_bp 1 /* Character Size bit 1 position. */ -#define USART_CHSIZE2_bm (1<<2) /* Character Size bit 2 mask. */ -#define USART_CHSIZE2_bp 2 /* Character Size bit 2 position. */ - -/* USART.BAUDCTRLA bit masks and bit positions */ -#define USART_BSEL_gm 0xFF /* Baud Rate Selection Bits [7:0] group mask. */ -#define USART_BSEL_gp 0 /* Baud Rate Selection Bits [7:0] group position. */ -#define USART_BSEL0_bm (1<<0) /* Baud Rate Selection Bits [7:0] bit 0 mask. */ -#define USART_BSEL0_bp 0 /* Baud Rate Selection Bits [7:0] bit 0 position. */ -#define USART_BSEL1_bm (1<<1) /* Baud Rate Selection Bits [7:0] bit 1 mask. */ -#define USART_BSEL1_bp 1 /* Baud Rate Selection Bits [7:0] bit 1 position. */ -#define USART_BSEL2_bm (1<<2) /* Baud Rate Selection Bits [7:0] bit 2 mask. */ -#define USART_BSEL2_bp 2 /* Baud Rate Selection Bits [7:0] bit 2 position. */ -#define USART_BSEL3_bm (1<<3) /* Baud Rate Selection Bits [7:0] bit 3 mask. */ -#define USART_BSEL3_bp 3 /* Baud Rate Selection Bits [7:0] bit 3 position. */ -#define USART_BSEL4_bm (1<<4) /* Baud Rate Selection Bits [7:0] bit 4 mask. */ -#define USART_BSEL4_bp 4 /* Baud Rate Selection Bits [7:0] bit 4 position. */ -#define USART_BSEL5_bm (1<<5) /* Baud Rate Selection Bits [7:0] bit 5 mask. */ -#define USART_BSEL5_bp 5 /* Baud Rate Selection Bits [7:0] bit 5 position. */ -#define USART_BSEL6_bm (1<<6) /* Baud Rate Selection Bits [7:0] bit 6 mask. */ -#define USART_BSEL6_bp 6 /* Baud Rate Selection Bits [7:0] bit 6 position. */ -#define USART_BSEL7_bm (1<<7) /* Baud Rate Selection Bits [7:0] bit 7 mask. */ -#define USART_BSEL7_bp 7 /* Baud Rate Selection Bits [7:0] bit 7 position. */ - -/* USART.BAUDCTRLB bit masks and bit positions */ -#define USART_BSCALE_gm 0xF0 /* Baud Rate Scale group mask. */ -#define USART_BSCALE_gp 4 /* Baud Rate Scale group position. */ -#define USART_BSCALE0_bm (1<<4) /* Baud Rate Scale bit 0 mask. */ -#define USART_BSCALE0_bp 4 /* Baud Rate Scale bit 0 position. */ -#define USART_BSCALE1_bm (1<<5) /* Baud Rate Scale bit 1 mask. */ -#define USART_BSCALE1_bp 5 /* Baud Rate Scale bit 1 position. */ -#define USART_BSCALE2_bm (1<<6) /* Baud Rate Scale bit 2 mask. */ -#define USART_BSCALE2_bp 6 /* Baud Rate Scale bit 2 position. */ -#define USART_BSCALE3_bm (1<<7) /* Baud Rate Scale bit 3 mask. */ -#define USART_BSCALE3_bp 7 /* Baud Rate Scale bit 3 position. */ - -/* USART_BSEL Predefined. */ -/* USART_BSEL Predefined. */ - -/* SPI - Serial Peripheral Interface */ -/* SPI.CTRL bit masks and bit positions */ -#define SPI_CLK2X_bm 0x80 /* Enable Double Speed bit mask. */ -#define SPI_CLK2X_bp 7 /* Enable Double Speed bit position. */ - -#define SPI_ENABLE_bm 0x40 /* Enable Module bit mask. */ -#define SPI_ENABLE_bp 6 /* Enable Module bit position. */ - -#define SPI_DORD_bm 0x20 /* Data Order Setting bit mask. */ -#define SPI_DORD_bp 5 /* Data Order Setting bit position. */ - -#define SPI_MASTER_bm 0x10 /* Master Operation Enable bit mask. */ -#define SPI_MASTER_bp 4 /* Master Operation Enable bit position. */ - -#define SPI_MODE_gm 0x0C /* SPI Mode group mask. */ -#define SPI_MODE_gp 2 /* SPI Mode group position. */ -#define SPI_MODE0_bm (1<<2) /* SPI Mode bit 0 mask. */ -#define SPI_MODE0_bp 2 /* SPI Mode bit 0 position. */ -#define SPI_MODE1_bm (1<<3) /* SPI Mode bit 1 mask. */ -#define SPI_MODE1_bp 3 /* SPI Mode bit 1 position. */ - -#define SPI_PRESCALER_gm 0x03 /* Prescaler group mask. */ -#define SPI_PRESCALER_gp 0 /* Prescaler group position. */ -#define SPI_PRESCALER0_bm (1<<0) /* Prescaler bit 0 mask. */ -#define SPI_PRESCALER0_bp 0 /* Prescaler bit 0 position. */ -#define SPI_PRESCALER1_bm (1<<1) /* Prescaler bit 1 mask. */ -#define SPI_PRESCALER1_bp 1 /* Prescaler bit 1 position. */ - -/* SPI.INTCTRL bit masks and bit positions */ -#define SPI_INTLVL_gm 0x03 /* Interrupt level group mask. */ -#define SPI_INTLVL_gp 0 /* Interrupt level group position. */ -#define SPI_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */ -#define SPI_INTLVL0_bp 0 /* Interrupt level bit 0 position. */ -#define SPI_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */ -#define SPI_INTLVL1_bp 1 /* Interrupt level bit 1 position. */ - -/* SPI.STATUS bit masks and bit positions */ -#define SPI_IF_bm 0x80 /* Interrupt Flag bit mask. */ -#define SPI_IF_bp 7 /* Interrupt Flag bit position. */ - -#define SPI_WRCOL_bm 0x40 /* Write Collision bit mask. */ -#define SPI_WRCOL_bp 6 /* Write Collision bit position. */ - -/* IRCOM - IR Communication Module */ -/* IRCOM.CTRL bit masks and bit positions */ -#define IRCOM_EVSEL_gm 0x0F /* Event Channel Select group mask. */ -#define IRCOM_EVSEL_gp 0 /* Event Channel Select group position. */ -#define IRCOM_EVSEL0_bm (1<<0) /* Event Channel Select bit 0 mask. */ -#define IRCOM_EVSEL0_bp 0 /* Event Channel Select bit 0 position. */ -#define IRCOM_EVSEL1_bm (1<<1) /* Event Channel Select bit 1 mask. */ -#define IRCOM_EVSEL1_bp 1 /* Event Channel Select bit 1 position. */ -#define IRCOM_EVSEL2_bm (1<<2) /* Event Channel Select bit 2 mask. */ -#define IRCOM_EVSEL2_bp 2 /* Event Channel Select bit 2 position. */ -#define IRCOM_EVSEL3_bm (1<<3) /* Event Channel Select bit 3 mask. */ -#define IRCOM_EVSEL3_bp 3 /* Event Channel Select bit 3 position. */ - -/* FUSE - Fuses and Lockbits */ -/* NVM_FUSES.FUSEBYTE1 bit masks and bit positions */ -#define NVM_FUSES_WDWP_gm 0xF0 /* Watchdog Window Timeout Period group mask. */ -#define NVM_FUSES_WDWP_gp 4 /* Watchdog Window Timeout Period group position. */ -#define NVM_FUSES_WDWP0_bm (1<<4) /* Watchdog Window Timeout Period bit 0 mask. */ -#define NVM_FUSES_WDWP0_bp 4 /* Watchdog Window Timeout Period bit 0 position. */ -#define NVM_FUSES_WDWP1_bm (1<<5) /* Watchdog Window Timeout Period bit 1 mask. */ -#define NVM_FUSES_WDWP1_bp 5 /* Watchdog Window Timeout Period bit 1 position. */ -#define NVM_FUSES_WDWP2_bm (1<<6) /* Watchdog Window Timeout Period bit 2 mask. */ -#define NVM_FUSES_WDWP2_bp 6 /* Watchdog Window Timeout Period bit 2 position. */ -#define NVM_FUSES_WDWP3_bm (1<<7) /* Watchdog Window Timeout Period bit 3 mask. */ -#define NVM_FUSES_WDWP3_bp 7 /* Watchdog Window Timeout Period bit 3 position. */ - -#define NVM_FUSES_WDP_gm 0x0F /* Watchdog Timeout Period group mask. */ -#define NVM_FUSES_WDP_gp 0 /* Watchdog Timeout Period group position. */ -#define NVM_FUSES_WDP0_bm (1<<0) /* Watchdog Timeout Period bit 0 mask. */ -#define NVM_FUSES_WDP0_bp 0 /* Watchdog Timeout Period bit 0 position. */ -#define NVM_FUSES_WDP1_bm (1<<1) /* Watchdog Timeout Period bit 1 mask. */ -#define NVM_FUSES_WDP1_bp 1 /* Watchdog Timeout Period bit 1 position. */ -#define NVM_FUSES_WDP2_bm (1<<2) /* Watchdog Timeout Period bit 2 mask. */ -#define NVM_FUSES_WDP2_bp 2 /* Watchdog Timeout Period bit 2 position. */ -#define NVM_FUSES_WDP3_bm (1<<3) /* Watchdog Timeout Period bit 3 mask. */ -#define NVM_FUSES_WDP3_bp 3 /* Watchdog Timeout Period bit 3 position. */ - -/* NVM_FUSES.FUSEBYTE2 bit masks and bit positions */ -#define NVM_FUSES_BOOTRST_bm 0x40 /* Boot Loader Section Reset Vector bit mask. */ -#define NVM_FUSES_BOOTRST_bp 6 /* Boot Loader Section Reset Vector bit position. */ - -#define NVM_FUSES_TOSCSEL_bm 0x20 /* Timer Oscillator pin location bit mask. */ -#define NVM_FUSES_TOSCSEL_bp 5 /* Timer Oscillator pin location bit position. */ - -#define NVM_FUSES_BODPD_gm 0x03 /* BOD Operation in Power-Down Mode group mask. */ -#define NVM_FUSES_BODPD_gp 0 /* BOD Operation in Power-Down Mode group position. */ -#define NVM_FUSES_BODPD0_bm (1<<0) /* BOD Operation in Power-Down Mode bit 0 mask. */ -#define NVM_FUSES_BODPD0_bp 0 /* BOD Operation in Power-Down Mode bit 0 position. */ -#define NVM_FUSES_BODPD1_bm (1<<1) /* BOD Operation in Power-Down Mode bit 1 mask. */ -#define NVM_FUSES_BODPD1_bp 1 /* BOD Operation in Power-Down Mode bit 1 position. */ - -/* NVM_FUSES.FUSEBYTE4 bit masks and bit positions */ -#define NVM_FUSES_RSTDISBL_bm 0x10 /* External Reset Disable bit mask. */ -#define NVM_FUSES_RSTDISBL_bp 4 /* External Reset Disable bit position. */ - -#define NVM_FUSES_SUT_gm 0x0C /* Start-up Time group mask. */ -#define NVM_FUSES_SUT_gp 2 /* Start-up Time group position. */ -#define NVM_FUSES_SUT0_bm (1<<2) /* Start-up Time bit 0 mask. */ -#define NVM_FUSES_SUT0_bp 2 /* Start-up Time bit 0 position. */ -#define NVM_FUSES_SUT1_bm (1<<3) /* Start-up Time bit 1 mask. */ -#define NVM_FUSES_SUT1_bp 3 /* Start-up Time bit 1 position. */ - -#define NVM_FUSES_WDLOCK_bm 0x02 /* Watchdog Timer Lock bit mask. */ -#define NVM_FUSES_WDLOCK_bp 1 /* Watchdog Timer Lock bit position. */ - -/* NVM_FUSES.FUSEBYTE5 bit masks and bit positions */ -#define NVM_FUSES_BODACT_gm 0x30 /* BOD Operation in Active Mode group mask. */ -#define NVM_FUSES_BODACT_gp 4 /* BOD Operation in Active Mode group position. */ -#define NVM_FUSES_BODACT0_bm (1<<4) /* BOD Operation in Active Mode bit 0 mask. */ -#define NVM_FUSES_BODACT0_bp 4 /* BOD Operation in Active Mode bit 0 position. */ -#define NVM_FUSES_BODACT1_bm (1<<5) /* BOD Operation in Active Mode bit 1 mask. */ -#define NVM_FUSES_BODACT1_bp 5 /* BOD Operation in Active Mode bit 1 position. */ - -#define NVM_FUSES_EESAVE_bm 0x08 /* Preserve EEPROM Through Chip Erase bit mask. */ -#define NVM_FUSES_EESAVE_bp 3 /* Preserve EEPROM Through Chip Erase bit position. */ - -#define NVM_FUSES_BODLVL_gm 0x07 /* Brownout Detection Voltage Level group mask. */ -#define NVM_FUSES_BODLVL_gp 0 /* Brownout Detection Voltage Level group position. */ -#define NVM_FUSES_BODLVL0_bm (1<<0) /* Brownout Detection Voltage Level bit 0 mask. */ -#define NVM_FUSES_BODLVL0_bp 0 /* Brownout Detection Voltage Level bit 0 position. */ -#define NVM_FUSES_BODLVL1_bm (1<<1) /* Brownout Detection Voltage Level bit 1 mask. */ -#define NVM_FUSES_BODLVL1_bp 1 /* Brownout Detection Voltage Level bit 1 position. */ -#define NVM_FUSES_BODLVL2_bm (1<<2) /* Brownout Detection Voltage Level bit 2 mask. */ -#define NVM_FUSES_BODLVL2_bp 2 /* Brownout Detection Voltage Level bit 2 position. */ - -/* LOCKBIT - Fuses and Lockbits */ -/* NVM_LOCKBITS.LOCKBITS bit masks and bit positions */ -#define NVM_LOCKBITS_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ -#define NVM_LOCKBITS_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ -#define NVM_LOCKBITS_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ -#define NVM_LOCKBITS_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ -#define NVM_LOCKBITS_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ -#define NVM_LOCKBITS_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ - -#define NVM_LOCKBITS_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ -#define NVM_LOCKBITS_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ -#define NVM_LOCKBITS_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ -#define NVM_LOCKBITS_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ -#define NVM_LOCKBITS_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ -#define NVM_LOCKBITS_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ - -#define NVM_LOCKBITS_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ -#define NVM_LOCKBITS_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ -#define NVM_LOCKBITS_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ -#define NVM_LOCKBITS_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ -#define NVM_LOCKBITS_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ -#define NVM_LOCKBITS_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ - -#define NVM_LOCKBITS_LB_gm 0x03 /* Lock Bits group mask. */ -#define NVM_LOCKBITS_LB_gp 0 /* Lock Bits group position. */ -#define NVM_LOCKBITS_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ -#define NVM_LOCKBITS_LB0_bp 0 /* Lock Bits bit 0 position. */ -#define NVM_LOCKBITS_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ -#define NVM_LOCKBITS_LB1_bp 1 /* Lock Bits bit 1 position. */ - - - -// Generic Port Pins - -#define PIN0_bm 0x01 -#define PIN0_bp 0 -#define PIN1_bm 0x02 -#define PIN1_bp 1 -#define PIN2_bm 0x04 -#define PIN2_bp 2 -#define PIN3_bm 0x08 -#define PIN3_bp 3 -#define PIN4_bm 0x10 -#define PIN4_bp 4 -#define PIN5_bm 0x20 -#define PIN5_bp 5 -#define PIN6_bm 0x40 -#define PIN6_bp 6 -#define PIN7_bm 0x80 -#define PIN7_bp 7 - -/* ========== Interrupt Vector Definitions ========== */ -/* Vector 0 is the reset vector */ - -/* OSC interrupt vectors */ -#define OSC_OSCF_vect_num 1 -#define OSC_OSCF_vect _VECTOR(1) /* Oscillator Failure Interrupt (NMI) */ - -/* PORTC interrupt vectors */ -#define PORTC_INT0_vect_num 2 -#define PORTC_INT0_vect _VECTOR(2) /* External Interrupt 0 */ -#define PORTC_INT1_vect_num 3 -#define PORTC_INT1_vect _VECTOR(3) /* External Interrupt 1 */ - -/* PORTR interrupt vectors */ -#define PORTR_INT0_vect_num 4 -#define PORTR_INT0_vect _VECTOR(4) /* External Interrupt 0 */ -#define PORTR_INT1_vect_num 5 -#define PORTR_INT1_vect _VECTOR(5) /* External Interrupt 1 */ - -/* RTC interrupt vectors */ -#define RTC_OVF_vect_num 10 -#define RTC_OVF_vect _VECTOR(10) /* Overflow Interrupt */ -#define RTC_COMP_vect_num 11 -#define RTC_COMP_vect _VECTOR(11) /* Compare Interrupt */ - -/* TWIC interrupt vectors */ -#define TWIC_TWIS_vect_num 12 -#define TWIC_TWIS_vect _VECTOR(12) /* TWI Slave Interrupt */ -#define TWIC_TWIM_vect_num 13 -#define TWIC_TWIM_vect _VECTOR(13) /* TWI Master Interrupt */ - -/* TCC0 interrupt vectors */ -#define TCC0_OVF_vect_num 14 -#define TCC0_OVF_vect _VECTOR(14) /* Overflow Interrupt */ - -/* TCC2 interrupt vectors */ -#define TCC2_LUNF_vect_num 14 -#define TCC2_LUNF_vect _VECTOR(14) /* Low Byte Underflow Interrupt */ - -/* TCC0 interrupt vectors */ -#define TCC0_ERR_vect_num 15 -#define TCC0_ERR_vect _VECTOR(15) /* Error Interrupt */ - -/* TCC2 interrupt vectors */ -#define TCC2_HUNF_vect_num 15 -#define TCC2_HUNF_vect _VECTOR(15) /* High Byte Underflow Interrupt */ - -/* TCC0 interrupt vectors */ -#define TCC0_CCA_vect_num 16 -#define TCC0_CCA_vect _VECTOR(16) /* Compare or Capture A Interrupt */ - -/* TCC2 interrupt vectors */ -#define TCC2_LCMPA_vect_num 16 -#define TCC2_LCMPA_vect _VECTOR(16) /* Low Byte Compare A Interrupt */ - -/* TCC0 interrupt vectors */ -#define TCC0_CCB_vect_num 17 -#define TCC0_CCB_vect _VECTOR(17) /* Compare or Capture B Interrupt */ - -/* TCC2 interrupt vectors */ -#define TCC2_LCMPB_vect_num 17 -#define TCC2_LCMPB_vect _VECTOR(17) /* Low Byte Compare B Interrupt */ - -/* TCC0 interrupt vectors */ -#define TCC0_CCC_vect_num 18 -#define TCC0_CCC_vect _VECTOR(18) /* Compare or Capture C Interrupt */ - -/* TCC2 interrupt vectors */ -#define TCC2_LCMPC_vect_num 18 -#define TCC2_LCMPC_vect _VECTOR(18) /* Low Byte Compare C Interrupt */ - -/* TCC0 interrupt vectors */ -#define TCC0_CCD_vect_num 19 -#define TCC0_CCD_vect _VECTOR(19) /* Compare or Capture D Interrupt */ - -/* TCC2 interrupt vectors */ -#define TCC2_LCMPD_vect_num 19 -#define TCC2_LCMPD_vect _VECTOR(19) /* Low Byte Compare D Interrupt */ - -/* TCC1 interrupt vectors */ -#define TCC1_OVF_vect_num 20 -#define TCC1_OVF_vect _VECTOR(20) /* Overflow Interrupt */ -#define TCC1_ERR_vect_num 21 -#define TCC1_ERR_vect _VECTOR(21) /* Error Interrupt */ -#define TCC1_CCA_vect_num 22 -#define TCC1_CCA_vect _VECTOR(22) /* Compare or Capture A Interrupt */ -#define TCC1_CCB_vect_num 23 -#define TCC1_CCB_vect _VECTOR(23) /* Compare or Capture B Interrupt */ - -/* SPIC interrupt vectors */ -#define SPIC_INT_vect_num 24 -#define SPIC_INT_vect _VECTOR(24) /* SPI Interrupt */ - -/* USARTC0 interrupt vectors */ -#define USARTC0_RXC_vect_num 25 -#define USARTC0_RXC_vect _VECTOR(25) /* Reception Complete Interrupt */ -#define USARTC0_DRE_vect_num 26 -#define USARTC0_DRE_vect _VECTOR(26) /* Data Register Empty Interrupt */ -#define USARTC0_TXC_vect_num 27 -#define USARTC0_TXC_vect _VECTOR(27) /* Transmission Complete Interrupt */ - -/* NVM interrupt vectors */ -#define NVM_EE_vect_num 32 -#define NVM_EE_vect _VECTOR(32) /* EE Interrupt */ -#define NVM_SPM_vect_num 33 -#define NVM_SPM_vect _VECTOR(33) /* SPM Interrupt */ - -/* PORTB interrupt vectors */ -#define PORTB_INT0_vect_num 34 -#define PORTB_INT0_vect _VECTOR(34) /* External Interrupt 0 */ -#define PORTB_INT1_vect_num 35 -#define PORTB_INT1_vect _VECTOR(35) /* External Interrupt 1 */ - -/* PORTE interrupt vectors */ -#define PORTE_INT0_vect_num 43 -#define PORTE_INT0_vect _VECTOR(43) /* External Interrupt 0 */ -#define PORTE_INT1_vect_num 44 -#define PORTE_INT1_vect _VECTOR(44) /* External Interrupt 1 */ - -/* TWIE interrupt vectors */ -#define TWIE_TWIS_vect_num 45 -#define TWIE_TWIS_vect _VECTOR(45) /* TWI Slave Interrupt */ -#define TWIE_TWIM_vect_num 46 -#define TWIE_TWIM_vect _VECTOR(46) /* TWI Master Interrupt */ - -/* TCE0 interrupt vectors */ -#define TCE0_OVF_vect_num 47 -#define TCE0_OVF_vect _VECTOR(47) /* Overflow Interrupt */ - -/* TCE2 interrupt vectors */ -#define TCE2_LUNF_vect_num 47 -#define TCE2_LUNF_vect _VECTOR(47) /* Low Byte Underflow Interrupt */ - -/* TCE0 interrupt vectors */ -#define TCE0_ERR_vect_num 48 -#define TCE0_ERR_vect _VECTOR(48) /* Error Interrupt */ - -/* TCE2 interrupt vectors */ -#define TCE2_HUNF_vect_num 48 -#define TCE2_HUNF_vect _VECTOR(48) /* High Byte Underflow Interrupt */ - -/* TCE0 interrupt vectors */ -#define TCE0_CCA_vect_num 49 -#define TCE0_CCA_vect _VECTOR(49) /* Compare or Capture A Interrupt */ - -/* TCE2 interrupt vectors */ -#define TCE2_LCMPA_vect_num 49 -#define TCE2_LCMPA_vect _VECTOR(49) /* Low Byte Compare A Interrupt */ - -/* TCE0 interrupt vectors */ -#define TCE0_CCB_vect_num 50 -#define TCE0_CCB_vect _VECTOR(50) /* Compare or Capture B Interrupt */ - -/* TCE2 interrupt vectors */ -#define TCE2_LCMPB_vect_num 50 -#define TCE2_LCMPB_vect _VECTOR(50) /* Low Byte Compare B Interrupt */ - -/* TCE0 interrupt vectors */ -#define TCE0_CCC_vect_num 51 -#define TCE0_CCC_vect _VECTOR(51) /* Compare or Capture C Interrupt */ - -/* TCE2 interrupt vectors */ -#define TCE2_LCMPC_vect_num 51 -#define TCE2_LCMPC_vect _VECTOR(51) /* Low Byte Compare C Interrupt */ - -/* TCE0 interrupt vectors */ -#define TCE0_CCD_vect_num 52 -#define TCE0_CCD_vect _VECTOR(52) /* Compare or Capture D Interrupt */ - -/* TCE2 interrupt vectors */ -#define TCE2_LCMPD_vect_num 52 -#define TCE2_LCMPD_vect _VECTOR(52) /* Low Byte Compare D Interrupt */ - -/* USARTE0 interrupt vectors */ -#define USARTE0_RXC_vect_num 58 -#define USARTE0_RXC_vect _VECTOR(58) /* Reception Complete Interrupt */ -#define USARTE0_DRE_vect_num 59 -#define USARTE0_DRE_vect _VECTOR(59) /* Data Register Empty Interrupt */ -#define USARTE0_TXC_vect_num 60 -#define USARTE0_TXC_vect _VECTOR(60) /* Transmission Complete Interrupt */ - -/* PORTD interrupt vectors */ -#define PORTD_INT0_vect_num 64 -#define PORTD_INT0_vect _VECTOR(64) /* External Interrupt 0 */ -#define PORTD_INT1_vect_num 65 -#define PORTD_INT1_vect _VECTOR(65) /* External Interrupt 1 */ - -/* PORTA interrupt vectors */ -#define PORTA_INT0_vect_num 66 -#define PORTA_INT0_vect _VECTOR(66) /* External Interrupt 0 */ -#define PORTA_INT1_vect_num 67 -#define PORTA_INT1_vect _VECTOR(67) /* External Interrupt 1 */ - -/* ACA interrupt vectors */ -#define ACA_AC0_vect_num 68 -#define ACA_AC0_vect _VECTOR(68) /* AC0 Interrupt */ -#define ACA_AC1_vect_num 69 -#define ACA_AC1_vect _VECTOR(69) /* AC1 Interrupt */ -#define ACA_ACW_vect_num 70 -#define ACA_ACW_vect _VECTOR(70) /* ACW Window Mode Interrupt */ - -/* ADCA interrupt vectors */ -#define ADCA_CH0_vect_num 71 -#define ADCA_CH0_vect _VECTOR(71) /* Interrupt 0 */ - -/* TCD0 interrupt vectors */ -#define TCD0_OVF_vect_num 77 -#define TCD0_OVF_vect _VECTOR(77) /* Overflow Interrupt */ - -/* TCD2 interrupt vectors */ -#define TCD2_LUNF_vect_num 77 -#define TCD2_LUNF_vect _VECTOR(77) /* Low Byte Underflow Interrupt */ - -/* TCD0 interrupt vectors */ -#define TCD0_ERR_vect_num 78 -#define TCD0_ERR_vect _VECTOR(78) /* Error Interrupt */ - -/* TCD2 interrupt vectors */ -#define TCD2_HUNF_vect_num 78 -#define TCD2_HUNF_vect _VECTOR(78) /* High Byte Underflow Interrupt */ - -/* TCD0 interrupt vectors */ -#define TCD0_CCA_vect_num 79 -#define TCD0_CCA_vect _VECTOR(79) /* Compare or Capture A Interrupt */ - -/* TCD2 interrupt vectors */ -#define TCD2_LCMPA_vect_num 79 -#define TCD2_LCMPA_vect _VECTOR(79) /* Low Byte Compare A Interrupt */ - -/* TCD0 interrupt vectors */ -#define TCD0_CCB_vect_num 80 -#define TCD0_CCB_vect _VECTOR(80) /* Compare or Capture B Interrupt */ - -/* TCD2 interrupt vectors */ -#define TCD2_LCMPB_vect_num 80 -#define TCD2_LCMPB_vect _VECTOR(80) /* Low Byte Compare B Interrupt */ - -/* TCD0 interrupt vectors */ -#define TCD0_CCC_vect_num 81 -#define TCD0_CCC_vect _VECTOR(81) /* Compare or Capture C Interrupt */ - -/* TCD2 interrupt vectors */ -#define TCD2_LCMPC_vect_num 81 -#define TCD2_LCMPC_vect _VECTOR(81) /* Low Byte Compare C Interrupt */ - -/* TCD0 interrupt vectors */ -#define TCD0_CCD_vect_num 82 -#define TCD0_CCD_vect _VECTOR(82) /* Compare or Capture D Interrupt */ - -/* TCD2 interrupt vectors */ -#define TCD2_LCMPD_vect_num 82 -#define TCD2_LCMPD_vect _VECTOR(82) /* Low Byte Compare D Interrupt */ - -/* SPID interrupt vectors */ -#define SPID_INT_vect_num 87 -#define SPID_INT_vect _VECTOR(87) /* SPI Interrupt */ - -/* USARTD0 interrupt vectors */ -#define USARTD0_RXC_vect_num 88 -#define USARTD0_RXC_vect _VECTOR(88) /* Reception Complete Interrupt */ -#define USARTD0_DRE_vect_num 89 -#define USARTD0_DRE_vect _VECTOR(89) /* Data Register Empty Interrupt */ -#define USARTD0_TXC_vect_num 90 -#define USARTD0_TXC_vect _VECTOR(90) /* Transmission Complete Interrupt */ - -/* PORTF interrupt vectors */ -#define PORTF_INT0_vect_num 104 -#define PORTF_INT0_vect _VECTOR(104) /* External Interrupt 0 */ -#define PORTF_INT1_vect_num 105 -#define PORTF_INT1_vect _VECTOR(105) /* External Interrupt 1 */ - -/* TCF0 interrupt vectors */ -#define TCF0_OVF_vect_num 108 -#define TCF0_OVF_vect _VECTOR(108) /* Overflow Interrupt */ - -/* TCF2 interrupt vectors */ -#define TCF2_LUNF_vect_num 108 -#define TCF2_LUNF_vect _VECTOR(108) /* Low Byte Underflow Interrupt */ - -/* TCF0 interrupt vectors */ -#define TCF0_ERR_vect_num 109 -#define TCF0_ERR_vect _VECTOR(109) /* Error Interrupt */ - -/* TCF2 interrupt vectors */ -#define TCF2_HUNF_vect_num 109 -#define TCF2_HUNF_vect _VECTOR(109) /* High Byte Underflow Interrupt */ - -/* TCF0 interrupt vectors */ -#define TCF0_CCA_vect_num 110 -#define TCF0_CCA_vect _VECTOR(110) /* Compare or Capture A Interrupt */ - -/* TCF2 interrupt vectors */ -#define TCF2_LCMPA_vect_num 110 -#define TCF2_LCMPA_vect _VECTOR(110) /* Low Byte Compare A Interrupt */ - -/* TCF0 interrupt vectors */ -#define TCF0_CCB_vect_num 111 -#define TCF0_CCB_vect _VECTOR(111) /* Compare or Capture B Interrupt */ - -/* TCF2 interrupt vectors */ -#define TCF2_LCMPB_vect_num 111 -#define TCF2_LCMPB_vect _VECTOR(111) /* Low Byte Compare B Interrupt */ - -/* TCF0 interrupt vectors */ -#define TCF0_CCC_vect_num 112 -#define TCF0_CCC_vect _VECTOR(112) /* Compare or Capture C Interrupt */ - -/* TCF2 interrupt vectors */ -#define TCF2_LCMPC_vect_num 112 -#define TCF2_LCMPC_vect _VECTOR(112) /* Low Byte Compare C Interrupt */ - -/* TCF0 interrupt vectors */ -#define TCF0_CCD_vect_num 113 -#define TCF0_CCD_vect _VECTOR(113) /* Compare or Capture D Interrupt */ - -/* TCF2 interrupt vectors */ -#define TCF2_LCMPD_vect_num 113 -#define TCF2_LCMPD_vect _VECTOR(113) /* Low Byte Compare D Interrupt */ - -/* USB interrupt vectors */ -#define USB_BUSEVENT_vect_num 125 -#define USB_BUSEVENT_vect _VECTOR(125) /* SOF, suspend, resume, reset bus event interrupts, crc, underflow, overflow and stall error interrupts */ -#define USB_TRNCOMPL_vect_num 126 -#define USB_TRNCOMPL_vect _VECTOR(126) /* Transaction complete interrupt */ - -#define _VECTOR_SIZE 4 /* Size of individual vector. */ -#define _VECTORS_SIZE (127 * _VECTOR_SIZE) - - -/* ========== Constants ========== */ - -#define PROGMEM_START (0x0000) -#define PROGMEM_SIZE (139264) -#define PROGMEM_END (PROGMEM_START + PROGMEM_SIZE - 1) - -#define APP_SECTION_START (0x0000) -#define APP_SECTION_SIZE (131072) -#define APP_SECTION_PAGE_SIZE (512) -#define APP_SECTION_END (APP_SECTION_START + APP_SECTION_SIZE - 1) - -#define APPTABLE_SECTION_START (0x1E000) -#define APPTABLE_SECTION_SIZE (8192) -#define APPTABLE_SECTION_PAGE_SIZE (512) -#define APPTABLE_SECTION_END (APPTABLE_SECTION_START + APPTABLE_SECTION_SIZE - 1) - -#define BOOT_SECTION_START (0x20000) -#define BOOT_SECTION_SIZE (8192) -#define BOOT_SECTION_PAGE_SIZE (512) -#define BOOT_SECTION_END (BOOT_SECTION_START + BOOT_SECTION_SIZE - 1) - -#define DATAMEM_START (0x0000) -#define DATAMEM_SIZE (16384) -#define DATAMEM_END (DATAMEM_START + DATAMEM_SIZE - 1) - -#define IO_START (0x0000) -#define IO_SIZE (4096) -#define IO_PAGE_SIZE (0) -#define IO_END (IO_START + IO_SIZE - 1) - -#define MAPPED_EEPROM_START (0x1000) -#define MAPPED_EEPROM_SIZE (2048) -#define MAPPED_EEPROM_PAGE_SIZE (0) -#define MAPPED_EEPROM_END (MAPPED_EEPROM_START + MAPPED_EEPROM_SIZE - 1) - -#define INTERNAL_SRAM_START (0x2000) -#define INTERNAL_SRAM_SIZE (8192) -#define INTERNAL_SRAM_PAGE_SIZE (0) -#define INTERNAL_SRAM_END (INTERNAL_SRAM_START + INTERNAL_SRAM_SIZE - 1) - -#define EEPROM_START (0x0000) -#define EEPROM_SIZE (2048) -#define EEPROM_PAGE_SIZE (32) -#define EEPROM_END (EEPROM_START + EEPROM_SIZE - 1) - -#define SIGNATURES_START (0x0000) -#define SIGNATURES_SIZE (3) -#define SIGNATURES_PAGE_SIZE (0) -#define SIGNATURES_END (SIGNATURES_START + SIGNATURES_SIZE - 1) - -#define FUSES_START (0x0000) -#define FUSES_SIZE (6) -#define FUSES_PAGE_SIZE (0) -#define FUSES_END (FUSES_START + FUSES_SIZE - 1) - -#define LOCKBITS_START (0x0000) -#define LOCKBITS_SIZE (1) -#define LOCKBITS_PAGE_SIZE (0) -#define LOCKBITS_END (LOCKBITS_START + LOCKBITS_SIZE - 1) - -#define USER_SIGNATURES_START (0x0000) -#define USER_SIGNATURES_SIZE (512) -#define USER_SIGNATURES_PAGE_SIZE (512) -#define USER_SIGNATURES_END (USER_SIGNATURES_START + USER_SIGNATURES_SIZE - 1) - -#define PROD_SIGNATURES_START (0x0000) -#define PROD_SIGNATURES_SIZE (64) -#define PROD_SIGNATURES_PAGE_SIZE (512) -#define PROD_SIGNATURES_END (PROD_SIGNATURES_START + PROD_SIGNATURES_SIZE - 1) - -#define FLASHSTART PROGMEM_START -#define FLASHEND PROGMEM_END -#define SPM_PAGESIZE 512 -#define RAMSTART INTERNAL_SRAM_START -#define RAMSIZE INTERNAL_SRAM_SIZE -#define RAMEND INTERNAL_SRAM_END -#define E2END EEPROM_END -#define E2PAGESIZE EEPROM_PAGE_SIZE - - -/* ========== Fuses ========== */ -#define FUSE_MEMORY_SIZE 6 - -/* Fuse Byte 0 Reserved */ - -/* Fuse Byte 1 */ -#define FUSE_WDP0 (unsigned char)~_BV(0) /* Watchdog Timeout Period Bit 0 */ -#define FUSE_WDP1 (unsigned char)~_BV(1) /* Watchdog Timeout Period Bit 1 */ -#define FUSE_WDP2 (unsigned char)~_BV(2) /* Watchdog Timeout Period Bit 2 */ -#define FUSE_WDP3 (unsigned char)~_BV(3) /* Watchdog Timeout Period Bit 3 */ -#define FUSE_WDWP0 (unsigned char)~_BV(4) /* Watchdog Window Timeout Period Bit 0 */ -#define FUSE_WDWP1 (unsigned char)~_BV(5) /* Watchdog Window Timeout Period Bit 1 */ -#define FUSE_WDWP2 (unsigned char)~_BV(6) /* Watchdog Window Timeout Period Bit 2 */ -#define FUSE_WDWP3 (unsigned char)~_BV(7) /* Watchdog Window Timeout Period Bit 3 */ -#define FUSE1_DEFAULT (0xFF) - -/* Fuse Byte 2 */ -#define FUSE_BODPD0 (unsigned char)~_BV(0) /* BOD Operation in Power-Down Mode Bit 0 */ -#define FUSE_BODPD1 (unsigned char)~_BV(1) /* BOD Operation in Power-Down Mode Bit 1 */ -#define FUSE_TOSCSEL (unsigned char)~_BV(5) /* Timer Oscillator pin location */ -#define FUSE_BOOTRST (unsigned char)~_BV(6) /* Boot Loader Section Reset Vector */ -#define FUSE2_DEFAULT (0xFF) - -/* Fuse Byte 3 Reserved */ - -/* Fuse Byte 4 */ -#define FUSE_WDLOCK (unsigned char)~_BV(1) /* Watchdog Timer Lock */ -#define FUSE_SUT0 (unsigned char)~_BV(2) /* Start-up Time Bit 0 */ -#define FUSE_SUT1 (unsigned char)~_BV(3) /* Start-up Time Bit 1 */ -#define FUSE_RSTDISBL (unsigned char)~_BV(4) /* External Reset Disable */ -#define FUSE4_DEFAULT (0xFF) - -/* Fuse Byte 5 */ -#define FUSE_BODLVL0 (unsigned char)~_BV(0) /* Brownout Detection Voltage Level Bit 0 */ -#define FUSE_BODLVL1 (unsigned char)~_BV(1) /* Brownout Detection Voltage Level Bit 1 */ -#define FUSE_BODLVL2 (unsigned char)~_BV(2) /* Brownout Detection Voltage Level Bit 2 */ -#define FUSE_EESAVE (unsigned char)~_BV(3) /* Preserve EEPROM Through Chip Erase */ -#define FUSE_BODACT0 (unsigned char)~_BV(4) /* BOD Operation in Active Mode Bit 0 */ -#define FUSE_BODACT1 (unsigned char)~_BV(5) /* BOD Operation in Active Mode Bit 1 */ -#define FUSE5_DEFAULT (0xFF) - -/* ========== Lock Bits ========== */ -#define __LOCK_BITS_EXIST -#define __BOOT_LOCK_APPLICATION_TABLE_BITS_EXIST -#define __BOOT_LOCK_APPLICATION_BITS_EXIST -#define __BOOT_LOCK_BOOT_BITS_EXIST - -/* ========== Signature ========== */ -#define SIGNATURE_0 0x1E -#define SIGNATURE_1 0x97 -#define SIGNATURE_2 0x52 - -/* ========== Power Reduction Condition Definitions ========== */ - -/* PR.PRGEN */ -#define __AVR_HAVE_PRGEN (PR_USB_bm|PR_AES_bm|PR_RTC_bm|PR_EVSYS_bm|PR_DMA_bm) -#define __AVR_HAVE_PRGEN_USB -#define __AVR_HAVE_PRGEN_AES -#define __AVR_HAVE_PRGEN_RTC -#define __AVR_HAVE_PRGEN_EVSYS -#define __AVR_HAVE_PRGEN_DMA - -/* PR.PRPA */ -#define __AVR_HAVE_PRPA (PR_ADC_bm|PR_AC_bm) -#define __AVR_HAVE_PRPA_ADC -#define __AVR_HAVE_PRPA_AC - -/* PR.PRPC */ -#define __AVR_HAVE_PRPC (PR_TWI_bm|PR_USART1_bm|PR_USART0_bm|PR_SPI_bm|PR_HIRES_bm|PR_TC1_bm|PR_TC0_bm) -#define __AVR_HAVE_PRPC_TWI -#define __AVR_HAVE_PRPC_USART1 -#define __AVR_HAVE_PRPC_USART0 -#define __AVR_HAVE_PRPC_SPI -#define __AVR_HAVE_PRPC_HIRES -#define __AVR_HAVE_PRPC_TC1 -#define __AVR_HAVE_PRPC_TC0 - -/* PR.PRPD */ -#define __AVR_HAVE_PRPD (PR_USART0_bm|PR_SPI_bm|PR_TC0_bm) -#define __AVR_HAVE_PRPD_USART0 -#define __AVR_HAVE_PRPD_SPI -#define __AVR_HAVE_PRPD_TC0 - -/* PR.PRPE */ -#define __AVR_HAVE_PRPE (PR_TWI_bm|PR_USART0_bm|PR_TC0_bm) -#define __AVR_HAVE_PRPE_TWI -#define __AVR_HAVE_PRPE_USART0 -#define __AVR_HAVE_PRPE_TC0 - -/* PR.PRPF */ -#define __AVR_HAVE_PRPF (PR_USART0_bm|PR_TC0_bm) -#define __AVR_HAVE_PRPF_USART0 -#define __AVR_HAVE_PRPF_TC0 - - -#endif /* #ifdef _AVR_ATXMEGA128C3_H_INCLUDED */ - diff --git a/arduino/hardware/tools/avr/avr/include/avr/iox128d3.h b/arduino/hardware/tools/avr/avr/include/avr/iox128d3.h deleted file mode 100644 index 15d4f33..0000000 --- a/arduino/hardware/tools/avr/avr/include/avr/iox128d3.h +++ /dev/null @@ -1,5749 +0,0 @@ -/* Copyright (c) 2009-2010 Atmel Corporation - All rights reserved. - - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - * Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - * Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in - the documentation and/or other materials provided with the - distribution. - - * Neither the name of the copyright holders nor the names of - contributors may be used to endorse or promote products derived - from this software without specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. */ - -/* $Id: iox128d3.h 2194 2010-11-16 15:10:51Z arcanum $ */ - -/* avr/iox128d3.h - definitions for ATxmega128D3 */ - -/* This file should only be included from , never directly. */ - -#ifndef _AVR_IO_H_ -# error "Include instead of this file." -#endif - -#ifndef _AVR_IOXXX_H_ -# define _AVR_IOXXX_H_ "iox128d3.h" -#else -# error "Attempt to include more than one file." -#endif - - -#ifndef _AVR_ATxmega128D3_H_ -#define _AVR_ATxmega128D3_H_ 1 - - -/* Ungrouped common registers */ -#define GPIOR0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ -#define GPIOR1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ -#define GPIOR2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ -#define GPIOR3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ -#define GPIOR4 _SFR_MEM8(0x0004) /* General Purpose IO Register 4 */ -#define GPIOR5 _SFR_MEM8(0x0005) /* General Purpose IO Register 5 */ -#define GPIOR6 _SFR_MEM8(0x0006) /* General Purpose IO Register 6 */ -#define GPIOR7 _SFR_MEM8(0x0007) /* General Purpose IO Register 7 */ -#define GPIOR8 _SFR_MEM8(0x0008) /* General Purpose IO Register 8 */ -#define GPIOR9 _SFR_MEM8(0x0009) /* General Purpose IO Register 9 */ -#define GPIORA _SFR_MEM8(0x000A) /* General Purpose IO Register 10 */ -#define GPIORB _SFR_MEM8(0x000B) /* General Purpose IO Register 11 */ -#define GPIORC _SFR_MEM8(0x000C) /* General Purpose IO Register 12 */ -#define GPIORD _SFR_MEM8(0x000D) /* General Purpose IO Register 13 */ -#define GPIORE _SFR_MEM8(0x000E) /* General Purpose IO Register 14 */ -#define GPIORF _SFR_MEM8(0x000F) /* General Purpose IO Register 15 */ - -#define CCP _SFR_MEM8(0x0034) /* Configuration Change Protection */ -#define RAMPD _SFR_MEM8(0x0038) /* Ramp D */ -#define RAMPX _SFR_MEM8(0x0039) /* Ramp X */ -#define RAMPY _SFR_MEM8(0x003A) /* Ramp Y */ -#define RAMPZ _SFR_MEM8(0x003B) /* Ramp Z */ -#define EIND _SFR_MEM8(0x003C) /* Extended Indirect Jump */ -#define SPL _SFR_MEM8(0x003D) /* Stack Pointer Low */ -#define SPH _SFR_MEM8(0x003E) /* Stack Pointer High */ -#define SREG _SFR_MEM8(0x003F) /* Status Register */ - - -/* C Language Only */ -#if !defined (__ASSEMBLER__) - -#include - -typedef volatile uint8_t register8_t; -typedef volatile uint16_t register16_t; -typedef volatile uint32_t register32_t; - - -#ifdef _WORDREGISTER -#undef _WORDREGISTER -#endif -#define _WORDREGISTER(regname) \ - __extension__ union \ - { \ - register16_t regname; \ - struct \ - { \ - register8_t regname ## L; \ - register8_t regname ## H; \ - }; \ - } - -#ifdef _DWORDREGISTER -#undef _DWORDREGISTER -#endif -#define _DWORDREGISTER(regname) \ - __extension__ union \ - { \ - register32_t regname; \ - struct \ - { \ - register8_t regname ## 0; \ - register8_t regname ## 1; \ - register8_t regname ## 2; \ - register8_t regname ## 3; \ - }; \ - } - - -/* -========================================================================== -IO Module Structures -========================================================================== -*/ - - -/* --------------------------------------------------------------------------- -XOCD - On-Chip Debug System --------------------------------------------------------------------------- -*/ - -/* On-Chip Debug System */ -typedef struct OCD_struct -{ - register8_t OCDR0; /* OCD Register 0 */ - register8_t OCDR1; /* OCD Register 1 */ -} OCD_t; - - -/* CCP signatures */ -typedef enum CCP_enum -{ - CCP_SPM_gc = (0x9D<<0), /* SPM Instruction Protection */ - CCP_IOREG_gc = (0xD8<<0), /* IO Register Protection */ -} CCP_t; - - -/* --------------------------------------------------------------------------- -CLK - Clock System --------------------------------------------------------------------------- -*/ - -/* Clock System */ -typedef struct CLK_struct -{ - register8_t CTRL; /* Control Register */ - register8_t PSCTRL; /* Prescaler Control Register */ - register8_t LOCK; /* Lock register */ - register8_t RTCCTRL; /* RTC Control Register */ -} CLK_t; - -/* --------------------------------------------------------------------------- -CLK - Clock System --------------------------------------------------------------------------- -*/ - -/* Power Reduction */ -typedef struct PR_struct -{ - register8_t PRGEN; /* General Power Reduction */ - register8_t PRPA; /* Power Reduction Port A */ - register8_t reserved_0x02; - register8_t PRPC; /* Power Reduction Port C */ - register8_t PRPD; /* Power Reduction Port D */ - register8_t PRPE; /* Power Reduction Port E */ - register8_t PRPF; /* Power Reduction Port F */ -} PR_t; - -/* System Clock Selection */ -typedef enum CLK_SCLKSEL_enum -{ - CLK_SCLKSEL_RC2M_gc = (0x00<<0), /* Internal 2MHz RC Oscillator */ - CLK_SCLKSEL_RC32M_gc = (0x01<<0), /* Internal 32MHz RC Oscillator */ - CLK_SCLKSEL_RC32K_gc = (0x02<<0), /* Internal 32kHz RC Oscillator */ - CLK_SCLKSEL_XOSC_gc = (0x03<<0), /* External Crystal Oscillator or Clock */ - CLK_SCLKSEL_PLL_gc = (0x04<<0), /* Phase Locked Loop */ -} CLK_SCLKSEL_t; - -/* Prescaler A Division Factor */ -typedef enum CLK_PSADIV_enum -{ - CLK_PSADIV_1_gc = (0x00<<2), /* Divide by 1 */ - CLK_PSADIV_2_gc = (0x01<<2), /* Divide by 2 */ - CLK_PSADIV_4_gc = (0x03<<2), /* Divide by 4 */ - CLK_PSADIV_8_gc = (0x05<<2), /* Divide by 8 */ - CLK_PSADIV_16_gc = (0x07<<2), /* Divide by 16 */ - CLK_PSADIV_32_gc = (0x09<<2), /* Divide by 32 */ - CLK_PSADIV_64_gc = (0x0B<<2), /* Divide by 64 */ - CLK_PSADIV_128_gc = (0x0D<<2), /* Divide by 128 */ - CLK_PSADIV_256_gc = (0x0F<<2), /* Divide by 256 */ - CLK_PSADIV_512_gc = (0x11<<2), /* Divide by 512 */ -} CLK_PSADIV_t; - -/* Prescaler B and C Division Factor */ -typedef enum CLK_PSBCDIV_enum -{ - CLK_PSBCDIV_1_1_gc = (0x00<<0), /* Divide B by 1 and C by 1 */ - CLK_PSBCDIV_1_2_gc = (0x01<<0), /* Divide B by 1 and C by 2 */ - CLK_PSBCDIV_4_1_gc = (0x02<<0), /* Divide B by 4 and C by 1 */ - CLK_PSBCDIV_2_2_gc = (0x03<<0), /* Divide B by 2 and C by 2 */ -} CLK_PSBCDIV_t; - -/* RTC Clock Source */ -typedef enum CLK_RTCSRC_enum -{ - CLK_RTCSRC_ULP_gc = (0x00<<1), /* 1kHz from internal 32kHz ULP */ - CLK_RTCSRC_TOSC_gc = (0x01<<1), /* 1kHz from 32kHz crystal oscillator on TOSC */ - CLK_RTCSRC_RCOSC_gc = (0x02<<1), /* 1kHz from internal 32kHz RC oscillator */ - CLK_RTCSRC_TOSC32_gc = (0x05<<1), /* 32kHz from 32kHz crystal oscillator on TOSC */ -} CLK_RTCSRC_t; - - -/* --------------------------------------------------------------------------- -SLEEP - Sleep Controller --------------------------------------------------------------------------- -*/ - -/* Sleep Controller */ -typedef struct SLEEP_struct -{ - register8_t CTRL; /* Control Register */ -} SLEEP_t; - -/* Sleep Mode */ -typedef enum SLEEP_SMODE_enum -{ - SLEEP_SMODE_IDLE_gc = (0x00<<1), /* Idle mode */ - SLEEP_SMODE_PDOWN_gc = (0x02<<1), /* Power-down Mode */ - SLEEP_SMODE_PSAVE_gc = (0x03<<1), /* Power-save Mode */ - SLEEP_SMODE_STDBY_gc = (0x06<<1), /* Standby Mode */ - SLEEP_SMODE_ESTDBY_gc = (0x07<<1), /* Extended Standby Mode */ -} SLEEP_SMODE_t; - - -#define SLEEP_MODE_IDLE (0x00<<1) -#define SLEEP_MODE_PWR_DOWN (0x02<<1) -#define SLEEP_MODE_PWR_SAVE (0x03<<1) -#define SLEEP_MODE_STANDBY (0x06<<1) -#define SLEEP_MODE_EXT_STANDBY (0x07<<1) - -/* --------------------------------------------------------------------------- -OSC - Oscillator --------------------------------------------------------------------------- -*/ - -/* Oscillator */ -typedef struct OSC_struct -{ - register8_t CTRL; /* Control Register */ - register8_t STATUS; /* Status Register */ - register8_t XOSCCTRL; /* External Oscillator Control Register */ - register8_t XOSCFAIL; /* External Oscillator Failure Detection Register */ - register8_t RC32KCAL; /* 32kHz Internal Oscillator Calibration Register */ - register8_t PLLCTRL; /* PLL Control REgister */ - register8_t DFLLCTRL; /* DFLL Control Register */ -} OSC_t; - -/* Oscillator Frequency Range */ -typedef enum OSC_FRQRANGE_enum -{ - OSC_FRQRANGE_04TO2_gc = (0x00<<6), /* 0.4 - 2 MHz */ - OSC_FRQRANGE_2TO9_gc = (0x01<<6), /* 2 - 9 MHz */ - OSC_FRQRANGE_9TO12_gc = (0x02<<6), /* 9 - 12 MHz */ - OSC_FRQRANGE_12TO16_gc = (0x03<<6), /* 12 - 16 MHz */ -} OSC_FRQRANGE_t; - -/* External Oscillator Selection and Startup Time */ -typedef enum OSC_XOSCSEL_enum -{ - OSC_XOSCSEL_EXTCLK_gc = (0x00<<0), /* External Clock - 6 CLK */ - OSC_XOSCSEL_32KHz_gc = (0x02<<0), /* 32kHz TOSC - 32K CLK */ - OSC_XOSCSEL_XTAL_256CLK_gc = (0x03<<0), /* 0.4-16MHz XTAL - 256 CLK */ - OSC_XOSCSEL_XTAL_1KCLK_gc = (0x07<<0), /* 0.4-16MHz XTAL - 1K CLK */ - OSC_XOSCSEL_XTAL_16KCLK_gc = (0x0B<<0), /* 0.4-16MHz XTAL - 16K CLK */ -} OSC_XOSCSEL_t; - -/* PLL Clock Source */ -typedef enum OSC_PLLSRC_enum -{ - OSC_PLLSRC_RC2M_gc = (0x00<<6), /* Internal 2MHz RC Oscillator */ - OSC_PLLSRC_RC32M_gc = (0x02<<6), /* Internal 32MHz RC Oscillator */ - OSC_PLLSRC_XOSC_gc = (0x03<<6), /* External Oscillator */ -} OSC_PLLSRC_t; - - -/* --------------------------------------------------------------------------- -DFLL - DFLL --------------------------------------------------------------------------- -*/ - -/* DFLL */ -typedef struct DFLL_struct -{ - register8_t CTRL; /* Control Register */ - register8_t reserved_0x01; - register8_t CALA; /* Calibration Register A */ - register8_t CALB; /* Calibration Register B */ - register8_t COMP0; /* Oscillator Compare Register 0 */ - register8_t COMP1; /* Oscillator Compare Register 1 */ - register8_t COMP2; /* Oscillator Compare Register 2 */ - register8_t reserved_0x07; -} DFLL_t; - - -/* --------------------------------------------------------------------------- -RST - Reset --------------------------------------------------------------------------- -*/ - -/* Reset */ -typedef struct RST_struct -{ - register8_t STATUS; /* Status Register */ - register8_t CTRL; /* Control Register */ -} RST_t; - - -/* --------------------------------------------------------------------------- -WDT - Watch-Dog Timer --------------------------------------------------------------------------- -*/ - -/* Watch-Dog Timer */ -typedef struct WDT_struct -{ - register8_t CTRL; /* Control */ - register8_t WINCTRL; /* Windowed Mode Control */ - register8_t STATUS; /* Status */ -} WDT_t; - -/* Period setting */ -typedef enum WDT_PER_enum -{ - WDT_PER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ - WDT_PER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ - WDT_PER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ - WDT_PER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ - WDT_PER_125CLK_gc = (0x04<<2), /* 125 cycles (0.125s @ 3.3V) */ - WDT_PER_250CLK_gc = (0x05<<2), /* 250 cycles (0.25s @ 3.3V) */ - WDT_PER_500CLK_gc = (0x06<<2), /* 500 cycles (0.5s @ 3.3V) */ - WDT_PER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ - WDT_PER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ - WDT_PER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ - WDT_PER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ -} WDT_PER_t; - -/* Closed window period */ -typedef enum WDT_WPER_enum -{ - WDT_WPER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ - WDT_WPER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ - WDT_WPER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ - WDT_WPER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ - WDT_WPER_125CLK_gc = (0x04<<2), /* 125 cycles (0.125s @ 3.3V) */ - WDT_WPER_250CLK_gc = (0x05<<2), /* 250 cycles (0.25s @ 3.3V) */ - WDT_WPER_500CLK_gc = (0x06<<2), /* 500 cycles (0.5s @ 3.3V) */ - WDT_WPER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ - WDT_WPER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ - WDT_WPER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ - WDT_WPER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ -} WDT_WPER_t; - - -/* --------------------------------------------------------------------------- -MCU - MCU Control --------------------------------------------------------------------------- -*/ - -/* MCU Control */ -typedef struct MCU_struct -{ - register8_t DEVID0; /* Device ID byte 0 */ - register8_t DEVID1; /* Device ID byte 1 */ - register8_t DEVID2; /* Device ID byte 2 */ - register8_t REVID; /* Revision ID */ - register8_t JTAGUID; /* JTAG User ID */ - register8_t reserved_0x05; - register8_t MCUCR; /* MCU Control */ - register8_t reserved_0x07; - register8_t EVSYSLOCK; /* Event System Lock */ - register8_t AWEXLOCK; /* AWEX Lock */ - register8_t reserved_0x0A; - register8_t reserved_0x0B; -} MCU_t; - - -/* --------------------------------------------------------------------------- -PMIC - Programmable Multi-level Interrupt Controller --------------------------------------------------------------------------- -*/ - -/* Programmable Multi-level Interrupt Controller */ -typedef struct PMIC_struct -{ - register8_t STATUS; /* Status Register */ - register8_t INTPRI; /* Interrupt Priority */ - register8_t CTRL; /* Control Register */ -} PMIC_t; - - -/* --------------------------------------------------------------------------- -CRC - Cyclic Redundancy Checker --------------------------------------------------------------------------- -*/ - -/* Cyclic Redundancy Checker */ -typedef struct CRC_struct -{ - register8_t CTRL; /* Control Register */ - register8_t STATUS; /* Status Register */ - register8_t reserved_0x02; - register8_t DATAIN; /* Data Input */ - register8_t CHECKSUM0; /* Checksum byte 0 */ - register8_t CHECKSUM1; /* Checksum byte 1 */ - register8_t CHECKSUM2; /* Checksum byte 2 */ - register8_t CHECKSUM3; /* Checksum byte 3 */ -} CRC_t; - -/* Reset */ -typedef enum CRC_RESET_enum -{ - CRC_RESET_NO_gc = (0x00<<6), /* No Reset */ - CRC_RESET_RESET0_gc = (0x02<<6), /* Reset CRC with CHECKSUM to all zeros */ - CRC_RESET_RESET1_gc = (0x03<<6), /* Reset CRC with CHECKSUM to all ones */ -} CRC_RESET_t; - -/* Input Source */ -typedef enum CRC_SOURCE_enum -{ - CRC_SOURCE_DISABLE_gc = (0x00<<0), /* Disabled */ - CRC_SOURCE_IO_gc = (0x01<<0), /* I/O Interface */ - CRC_SOURCE_FLASH_gc = (0x02<<0), /* Flash */ - CRC_SOURCE_DMAC0_gc = (0x04<<0), /* DMAC Channel 0 */ - CRC_SOURCE_DMAC1_gc = (0x05<<0), /* DMAC Channel 1 */ - CRC_SOURCE_DMAC2_gc = (0x06<<0), /* DMAC Channel 2 */ - CRC_SOURCE_DMAC3_gc = (0x07<<0), /* DMAC Channel 3 */ -} CRC_SOURCE_t; - - -/* --------------------------------------------------------------------------- -EVSYS - Event System --------------------------------------------------------------------------- -*/ - -/* Event System */ -typedef struct EVSYS_struct -{ - register8_t CH0MUX; /* Event Channel 0 Multiplexer */ - register8_t CH1MUX; /* Event Channel 1 Multiplexer */ - register8_t CH2MUX; /* Event Channel 2 Multiplexer */ - register8_t CH3MUX; /* Event Channel 3 Multiplexer */ - register8_t reserved_0x04; - register8_t reserved_0x05; - register8_t reserved_0x06; - register8_t reserved_0x07; - register8_t CH0CTRL; /* Channel 0 Control Register */ - register8_t CH1CTRL; /* Channel 1 Control Register */ - register8_t CH2CTRL; /* Channel 2 Control Register */ - register8_t CH3CTRL; /* Channel 3 Control Register */ - register8_t reserved_0x0C; - register8_t reserved_0x0D; - register8_t reserved_0x0E; - register8_t reserved_0x0F; - register8_t STROBE; /* Event Strobe */ - register8_t DATA; /* Event Data */ -} EVSYS_t; - -/* Quadrature Decoder Index Recognition Mode */ -typedef enum EVSYS_QDIRM_enum -{ - EVSYS_QDIRM_00_gc = (0x00<<5), /* QDPH0 = 0, QDPH90 = 0 */ - EVSYS_QDIRM_01_gc = (0x01<<5), /* QDPH0 = 0, QDPH90 = 1 */ - EVSYS_QDIRM_10_gc = (0x02<<5), /* QDPH0 = 1, QDPH90 = 0 */ - EVSYS_QDIRM_11_gc = (0x03<<5), /* QDPH0 = 1, QDPH90 = 1 */ -} EVSYS_QDIRM_t; - -/* Digital filter coefficient */ -typedef enum EVSYS_DIGFILT_enum -{ - EVSYS_DIGFILT_1SAMPLE_gc = (0x00<<0), /* 1 SAMPLE */ - EVSYS_DIGFILT_2SAMPLES_gc = (0x01<<0), /* 2 SAMPLES */ - EVSYS_DIGFILT_3SAMPLES_gc = (0x02<<0), /* 3 SAMPLES */ - EVSYS_DIGFILT_4SAMPLES_gc = (0x03<<0), /* 4 SAMPLES */ - EVSYS_DIGFILT_5SAMPLES_gc = (0x04<<0), /* 5 SAMPLES */ - EVSYS_DIGFILT_6SAMPLES_gc = (0x05<<0), /* 6 SAMPLES */ - EVSYS_DIGFILT_7SAMPLES_gc = (0x06<<0), /* 7 SAMPLES */ - EVSYS_DIGFILT_8SAMPLES_gc = (0x07<<0), /* 8 SAMPLES */ -} EVSYS_DIGFILT_t; - -/* Event Channel multiplexer input selection */ -typedef enum EVSYS_CHMUX_enum -{ - EVSYS_CHMUX_OFF_gc = (0x00<<0), /* Off */ - EVSYS_CHMUX_RTC_OVF_gc = (0x08<<0), /* RTC Overflow */ - EVSYS_CHMUX_RTC_CMP_gc = (0x09<<0), /* RTC Compare Match */ - EVSYS_CHMUX_ACA_CH0_gc = (0x10<<0), /* Analog Comparator A Channel 0 */ - EVSYS_CHMUX_ACA_CH1_gc = (0x11<<0), /* Analog Comparator A Channel 1 */ - EVSYS_CHMUX_ACA_WIN_gc = (0x12<<0), /* Analog Comparator A Window */ - EVSYS_CHMUX_ADCA_CH0_gc = (0x20<<0), /* ADC A Channel 0 */ - EVSYS_CHMUX_PORTA_PIN0_gc = (0x50<<0), /* Port A, Pin0 */ - EVSYS_CHMUX_PORTA_PIN1_gc = (0x51<<0), /* Port A, Pin1 */ - EVSYS_CHMUX_PORTA_PIN2_gc = (0x52<<0), /* Port A, Pin2 */ - EVSYS_CHMUX_PORTA_PIN3_gc = (0x53<<0), /* Port A, Pin3 */ - EVSYS_CHMUX_PORTA_PIN4_gc = (0x54<<0), /* Port A, Pin4 */ - EVSYS_CHMUX_PORTA_PIN5_gc = (0x55<<0), /* Port A, Pin5 */ - EVSYS_CHMUX_PORTA_PIN6_gc = (0x56<<0), /* Port A, Pin6 */ - EVSYS_CHMUX_PORTA_PIN7_gc = (0x57<<0), /* Port A, Pin7 */ - EVSYS_CHMUX_PORTB_PIN0_gc = (0x58<<0), /* Port B, Pin0 */ - EVSYS_CHMUX_PORTB_PIN1_gc = (0x59<<0), /* Port B, Pin1 */ - EVSYS_CHMUX_PORTB_PIN2_gc = (0x5A<<0), /* Port B, Pin2 */ - EVSYS_CHMUX_PORTB_PIN3_gc = (0x5B<<0), /* Port B, Pin3 */ - EVSYS_CHMUX_PORTB_PIN4_gc = (0x5C<<0), /* Port B, Pin4 */ - EVSYS_CHMUX_PORTB_PIN5_gc = (0x5D<<0), /* Port B, Pin5 */ - EVSYS_CHMUX_PORTB_PIN6_gc = (0x5E<<0), /* Port B, Pin6 */ - EVSYS_CHMUX_PORTB_PIN7_gc = (0x5F<<0), /* Port B, Pin7 */ - EVSYS_CHMUX_PORTC_PIN0_gc = (0x60<<0), /* Port C, Pin0 */ - EVSYS_CHMUX_PORTC_PIN1_gc = (0x61<<0), /* Port C, Pin1 */ - EVSYS_CHMUX_PORTC_PIN2_gc = (0x62<<0), /* Port C, Pin2 */ - EVSYS_CHMUX_PORTC_PIN3_gc = (0x63<<0), /* Port C, Pin3 */ - EVSYS_CHMUX_PORTC_PIN4_gc = (0x64<<0), /* Port C, Pin4 */ - EVSYS_CHMUX_PORTC_PIN5_gc = (0x65<<0), /* Port C, Pin5 */ - EVSYS_CHMUX_PORTC_PIN6_gc = (0x66<<0), /* Port C, Pin6 */ - EVSYS_CHMUX_PORTC_PIN7_gc = (0x67<<0), /* Port C, Pin7 */ - EVSYS_CHMUX_PORTD_PIN0_gc = (0x68<<0), /* Port D, Pin0 */ - EVSYS_CHMUX_PORTD_PIN1_gc = (0x69<<0), /* Port D, Pin1 */ - EVSYS_CHMUX_PORTD_PIN2_gc = (0x6A<<0), /* Port D, Pin2 */ - EVSYS_CHMUX_PORTD_PIN3_gc = (0x6B<<0), /* Port D, Pin3 */ - EVSYS_CHMUX_PORTD_PIN4_gc = (0x6C<<0), /* Port D, Pin4 */ - EVSYS_CHMUX_PORTD_PIN5_gc = (0x6D<<0), /* Port D, Pin5 */ - EVSYS_CHMUX_PORTD_PIN6_gc = (0x6E<<0), /* Port D, Pin6 */ - EVSYS_CHMUX_PORTD_PIN7_gc = (0x6F<<0), /* Port D, Pin7 */ - EVSYS_CHMUX_PORTE_PIN0_gc = (0x70<<0), /* Port E, Pin0 */ - EVSYS_CHMUX_PORTE_PIN1_gc = (0x71<<0), /* Port E, Pin1 */ - EVSYS_CHMUX_PORTE_PIN2_gc = (0x72<<0), /* Port E, Pin2 */ - EVSYS_CHMUX_PORTE_PIN3_gc = (0x73<<0), /* Port E, Pin3 */ - EVSYS_CHMUX_PORTE_PIN4_gc = (0x74<<0), /* Port E, Pin4 */ - EVSYS_CHMUX_PORTE_PIN5_gc = (0x75<<0), /* Port E, Pin5 */ - EVSYS_CHMUX_PORTE_PIN6_gc = (0x76<<0), /* Port E, Pin6 */ - EVSYS_CHMUX_PORTE_PIN7_gc = (0x77<<0), /* Port E, Pin7 */ - EVSYS_CHMUX_PORTF_PIN0_gc = (0x78<<0), /* Port F, Pin0 */ - EVSYS_CHMUX_PORTF_PIN1_gc = (0x79<<0), /* Port F, Pin1 */ - EVSYS_CHMUX_PORTF_PIN2_gc = (0x7A<<0), /* Port F, Pin2 */ - EVSYS_CHMUX_PORTF_PIN3_gc = (0x7B<<0), /* Port F, Pin3 */ - EVSYS_CHMUX_PORTF_PIN4_gc = (0x7C<<0), /* Port F, Pin4 */ - EVSYS_CHMUX_PORTF_PIN5_gc = (0x7D<<0), /* Port F, Pin5 */ - EVSYS_CHMUX_PORTF_PIN6_gc = (0x7E<<0), /* Port F, Pin6 */ - EVSYS_CHMUX_PORTF_PIN7_gc = (0x7F<<0), /* Port F, Pin7 */ - EVSYS_CHMUX_PRESCALER_1_gc = (0x80<<0), /* Prescaler, divide by 1 */ - EVSYS_CHMUX_PRESCALER_2_gc = (0x81<<0), /* Prescaler, divide by 2 */ - EVSYS_CHMUX_PRESCALER_4_gc = (0x82<<0), /* Prescaler, divide by 4 */ - EVSYS_CHMUX_PRESCALER_8_gc = (0x83<<0), /* Prescaler, divide by 8 */ - EVSYS_CHMUX_PRESCALER_16_gc = (0x84<<0), /* Prescaler, divide by 16 */ - EVSYS_CHMUX_PRESCALER_32_gc = (0x85<<0), /* Prescaler, divide by 32 */ - EVSYS_CHMUX_PRESCALER_64_gc = (0x86<<0), /* Prescaler, divide by 64 */ - EVSYS_CHMUX_PRESCALER_128_gc = (0x87<<0), /* Prescaler, divide by 128 */ - EVSYS_CHMUX_PRESCALER_256_gc = (0x88<<0), /* Prescaler, divide by 256 */ - EVSYS_CHMUX_PRESCALER_512_gc = (0x89<<0), /* Prescaler, divide by 512 */ - EVSYS_CHMUX_PRESCALER_1024_gc = (0x8A<<0), /* Prescaler, divide by 1024 */ - EVSYS_CHMUX_PRESCALER_2048_gc = (0x8B<<0), /* Prescaler, divide by 2048 */ - EVSYS_CHMUX_PRESCALER_4096_gc = (0x8C<<0), /* Prescaler, divide by 4096 */ - EVSYS_CHMUX_PRESCALER_8192_gc = (0x8D<<0), /* Prescaler, divide by 8192 */ - EVSYS_CHMUX_PRESCALER_16384_gc = (0x8E<<0), /* Prescaler, divide by 16384 */ - EVSYS_CHMUX_PRESCALER_32768_gc = (0x8F<<0), /* Prescaler, divide by 32768 */ - EVSYS_CHMUX_TCC0_OVF_gc = (0xC0<<0), /* Timer/Counter C0 Overflow */ - EVSYS_CHMUX_TCC0_ERR_gc = (0xC1<<0), /* Timer/Counter C0 Error */ - EVSYS_CHMUX_TCC0_CCA_gc = (0xC4<<0), /* Timer/Counter C0 Compare or Capture A */ - EVSYS_CHMUX_TCC0_CCB_gc = (0xC5<<0), /* Timer/Counter C0 Compare or Capture B */ - EVSYS_CHMUX_TCC0_CCC_gc = (0xC6<<0), /* Timer/Counter C0 Compare or Capture C */ - EVSYS_CHMUX_TCC0_CCD_gc = (0xC7<<0), /* Timer/Counter C0 Compare or Capture D */ - EVSYS_CHMUX_TCC1_OVF_gc = (0xC8<<0), /* Timer/Counter C1 Overflow */ - EVSYS_CHMUX_TCC1_ERR_gc = (0xC9<<0), /* Timer/Counter C1 Error */ - EVSYS_CHMUX_TCC1_CCA_gc = (0xCC<<0), /* Timer/Counter C1 Compare or Capture A */ - EVSYS_CHMUX_TCC1_CCB_gc = (0xCD<<0), /* Timer/Counter C1 Compare or Capture B */ - EVSYS_CHMUX_TCD0_OVF_gc = (0xD0<<0), /* Timer/Counter D0 Overflow */ - EVSYS_CHMUX_TCD0_ERR_gc = (0xD1<<0), /* Timer/Counter D0 Error */ - EVSYS_CHMUX_TCD0_CCA_gc = (0xD4<<0), /* Timer/Counter D0 Compare or Capture A */ - EVSYS_CHMUX_TCD0_CCB_gc = (0xD5<<0), /* Timer/Counter D0 Compare or Capture B */ - EVSYS_CHMUX_TCD0_CCC_gc = (0xD6<<0), /* Timer/Counter D0 Compare or Capture C */ - EVSYS_CHMUX_TCD0_CCD_gc = (0xD7<<0), /* Timer/Counter D0 Compare or Capture D */ - EVSYS_CHMUX_TCD1_OVF_gc = (0xD8<<0), /* Timer/Counter D1 Overflow */ - EVSYS_CHMUX_TCD1_ERR_gc = (0xD9<<0), /* Timer/Counter D1 Error */ - EVSYS_CHMUX_TCD1_CCA_gc = (0xDC<<0), /* Timer/Counter D1 Compare or Capture A */ - EVSYS_CHMUX_TCD1_CCB_gc = (0xDD<<0), /* Timer/Counter D1 Compare or Capture B */ - EVSYS_CHMUX_TCE0_OVF_gc = (0xE0<<0), /* Timer/Counter E0 Overflow */ - EVSYS_CHMUX_TCE0_ERR_gc = (0xE1<<0), /* Timer/Counter E0 Error */ - EVSYS_CHMUX_TCE0_CCA_gc = (0xE4<<0), /* Timer/Counter E0 Compare or Capture A */ - EVSYS_CHMUX_TCE0_CCB_gc = (0xE5<<0), /* Timer/Counter E0 Compare or Capture B */ - EVSYS_CHMUX_TCE0_CCC_gc = (0xE6<<0), /* Timer/Counter E0 Compare or Capture C */ - EVSYS_CHMUX_TCE0_CCD_gc = (0xE7<<0), /* Timer/Counter E0 Compare or Capture D */ - EVSYS_CHMUX_TCE1_OVF_gc = (0xE8<<0), /* Timer/Counter E1 Overflow */ - EVSYS_CHMUX_TCE1_ERR_gc = (0xE9<<0), /* Timer/Counter E1 Error */ - EVSYS_CHMUX_TCE1_CCA_gc = (0xEC<<0), /* Timer/Counter E1 Compare or Capture A */ - EVSYS_CHMUX_TCE1_CCB_gc = (0xED<<0), /* Timer/Counter E1 Compare or Capture B */ - EVSYS_CHMUX_TCF0_OVF_gc = (0xF0<<0), /* Timer/Counter F0 Overflow */ - EVSYS_CHMUX_TCF0_ERR_gc = (0xF1<<0), /* Timer/Counter F0 Error */ - EVSYS_CHMUX_TCF0_CCA_gc = (0xF4<<0), /* Timer/Counter F0 Compare or Capture A */ - EVSYS_CHMUX_TCF0_CCB_gc = (0xF5<<0), /* Timer/Counter F0 Compare or Capture B */ - EVSYS_CHMUX_TCF0_CCC_gc = (0xF6<<0), /* Timer/Counter F0 Compare or Capture C */ - EVSYS_CHMUX_TCF0_CCD_gc = (0xF7<<0), /* Timer/Counter F0 Compare or Capture D */ - EVSYS_CHMUX_TCF1_OVF_gc = (0xF8<<0), /* Timer/Counter F1 Overflow */ - EVSYS_CHMUX_TCF1_ERR_gc = (0xF9<<0), /* Timer/Counter F1 Error */ - EVSYS_CHMUX_TCF1_CCA_gc = (0xFC<<0), /* Timer/Counter F1 Compare or Capture A */ - EVSYS_CHMUX_TCF1_CCB_gc = (0xFD<<0), /* Timer/Counter F1 Compare or Capture B */ -} EVSYS_CHMUX_t; - - -/* --------------------------------------------------------------------------- -NVM - Non Volatile Memory Controller --------------------------------------------------------------------------- -*/ - -/* Non-volatile Memory Controller */ -typedef struct NVM_struct -{ - register8_t ADDR0; /* Address Register 0 */ - register8_t ADDR1; /* Address Register 1 */ - register8_t ADDR2; /* Address Register 2 */ - register8_t reserved_0x03; - register8_t DATA0; /* Data Register 0 */ - register8_t DATA1; /* Data Register 1 */ - register8_t DATA2; /* Data Register 2 */ - register8_t reserved_0x07; - register8_t reserved_0x08; - register8_t reserved_0x09; - register8_t CMD; /* Command */ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t INTCTRL; /* Interrupt Control */ - register8_t reserved_0x0E; - register8_t STATUS; /* Status */ - register8_t LOCK_BITS; /* Lock Bits */ -} NVM_t; - -/* --------------------------------------------------------------------------- -NVM - Non Volatile Memory Controller --------------------------------------------------------------------------- -*/ - -/* Lock Bits */ -typedef struct NVM_LOCKBITS_struct -{ - register8_t LOCKBITS; /* Lock Bits */ -} NVM_LOCKBITS_t; - -/* --------------------------------------------------------------------------- -NVM - Non Volatile Memory Controller --------------------------------------------------------------------------- -*/ - -/* Fuses */ -typedef struct NVM_FUSES_struct -{ - register8_t FUSEBYTE0; /* User ID */ - register8_t FUSEBYTE1; /* Watchdog Configuration */ - register8_t FUSEBYTE2; /* Reset Configuration */ - register8_t reserved_0x03; - register8_t FUSEBYTE4; /* Start-up Configuration */ - register8_t FUSEBYTE5; /* EESAVE and BOD Level */ -} NVM_FUSES_t; - -/* --------------------------------------------------------------------------- -NVM - Non Volatile Memory Controller --------------------------------------------------------------------------- -*/ - -/* Production Signatures */ -typedef struct NVM_PROD_SIGNATURES_struct -{ - register8_t RCOSC2M; /* RCOSC 2MHz Calibration Value */ - register8_t reserved_0x01; - register8_t RCOSC32K; /* RCOSC 32kHz Calibration Value */ - register8_t RCOSC32M; /* RCOSC 32MHz Calibration Value */ - register8_t reserved_0x04; - register8_t reserved_0x05; - register8_t reserved_0x06; - register8_t reserved_0x07; - register8_t LOTNUM0; /* Lot Number Byte 0, ASCII */ - register8_t LOTNUM1; /* Lot Number Byte 1, ASCII */ - register8_t LOTNUM2; /* Lot Number Byte 2, ASCII */ - register8_t LOTNUM3; /* Lot Number Byte 3, ASCII */ - register8_t LOTNUM4; /* Lot Number Byte 4, ASCII */ - register8_t LOTNUM5; /* Lot Number Byte 5, ASCII */ - register8_t reserved_0x0E; - register8_t reserved_0x0F; - register8_t WAFNUM; /* Wafer Number */ - register8_t reserved_0x11; - register8_t COORDX0; /* Wafer Coordinate X Byte 0 */ - register8_t COORDX1; /* Wafer Coordinate X Byte 1 */ - register8_t COORDY0; /* Wafer Coordinate Y Byte 0 */ - register8_t COORDY1; /* Wafer Coordinate Y Byte 1 */ - register8_t reserved_0x16; - register8_t reserved_0x17; - register8_t reserved_0x18; - register8_t reserved_0x19; - register8_t reserved_0x1A; - register8_t reserved_0x1B; - register8_t reserved_0x1C; - register8_t reserved_0x1D; - register8_t reserved_0x1E; - register8_t reserved_0x1F; - register8_t ADCACAL0; /* ADCA Calibration Byte 0 */ - register8_t ADCACAL1; /* ADCA Calibration Byte 1 */ - register8_t reserved_0x22; - register8_t reserved_0x23; - register8_t ADCBCAL0; /* ADCB Calibration Byte 0 */ - register8_t ADCBCAL1; /* ADCB Calibration Byte 1 */ - register8_t reserved_0x26; - register8_t reserved_0x27; - register8_t reserved_0x28; - register8_t reserved_0x29; - register8_t reserved_0x2A; - register8_t reserved_0x2B; - register8_t reserved_0x2C; - register8_t reserved_0x2D; - register8_t TEMPSENSE0; /* Temperature Sensor Calibration Byte 0 */ - register8_t TEMPSENSE1; /* Temperature Sensor Calibration Byte 0 */ - register8_t DACAOFFCAL; /* DACA Calibration Byte 0 */ - register8_t DACAGAINCAL; /* DACA Calibration Byte 1 */ - register8_t DACBOFFCAL; /* DACB Calibration Byte 0 */ - register8_t DACBGAINCAL; /* DACB Calibration Byte 1 */ - register8_t reserved_0x34; - register8_t reserved_0x35; - register8_t reserved_0x36; - register8_t reserved_0x37; - register8_t reserved_0x38; - register8_t reserved_0x39; - register8_t reserved_0x3A; - register8_t reserved_0x3B; - register8_t reserved_0x3C; - register8_t reserved_0x3D; - register8_t reserved_0x3E; -} NVM_PROD_SIGNATURES_t; - -/* NVM Command */ -typedef enum NVM_CMD_enum -{ - NVM_CMD_NO_OPERATION_gc = (0x00<<0), /* Noop/Ordinary LPM */ - NVM_CMD_READ_CALIB_ROW_gc = (0x02<<0), /* Read calibration row */ - NVM_CMD_READ_USER_SIG_ROW_gc = (0x01<<0), /* Read user signature row */ - NVM_CMD_READ_EEPROM_gc = (0x06<<0), /* Read EEPROM */ - NVM_CMD_READ_FUSES_gc = (0x07<<0), /* Read fuse byte */ - NVM_CMD_WRITE_LOCK_BITS_gc = (0x08<<0), /* Write lock bits */ - NVM_CMD_ERASE_USER_SIG_ROW_gc = (0x18<<0), /* Erase user signature row */ - NVM_CMD_WRITE_USER_SIG_ROW_gc = (0x1A<<0), /* Write user signature row */ - NVM_CMD_ERASE_APP_gc = (0x20<<0), /* Erase Application Section */ - NVM_CMD_ERASE_APP_PAGE_gc = (0x22<<0), /* Erase Application Section page */ - NVM_CMD_LOAD_FLASH_BUFFER_gc = (0x23<<0), /* Load Flash page buffer */ - NVM_CMD_WRITE_APP_PAGE_gc = (0x24<<0), /* Write Application Section page */ - NVM_CMD_ERASE_WRITE_APP_PAGE_gc = (0x25<<0), /* Erase-and-write Application Section page */ - NVM_CMD_ERASE_FLASH_BUFFER_gc = (0x26<<0), /* Erase/flush Flash page buffer */ - NVM_CMD_ERASE_BOOT_PAGE_gc = (0x2A<<0), /* Erase Boot Section page */ - NVM_CMD_WRITE_BOOT_PAGE_gc = (0x2C<<0), /* Write Boot Section page */ - NVM_CMD_ERASE_WRITE_BOOT_PAGE_gc = (0x2D<<0), /* Erase-and-write Boot Section page */ - NVM_CMD_ERASE_EEPROM_gc = (0x30<<0), /* Erase EEPROM */ - NVM_CMD_ERASE_EEPROM_PAGE_gc = (0x32<<0), /* Erase EEPROM page */ - NVM_CMD_LOAD_EEPROM_BUFFER_gc = (0x33<<0), /* Load EEPROM page buffer */ - NVM_CMD_WRITE_EEPROM_PAGE_gc = (0x34<<0), /* Write EEPROM page */ - NVM_CMD_ERASE_WRITE_EEPROM_PAGE_gc = (0x35<<0), /* Erase-and-write EEPROM page */ - NVM_CMD_ERASE_EEPROM_BUFFER_gc = (0x36<<0), /* Erase/flush EEPROM page buffer */ - NVM_CMD_APP_CRC_gc = (0x38<<0), /* Generate Application section CRC */ - NVM_CMD_BOOT_CRC_gc = (0x39<<0), /* Generate Boot Section CRC */ - NVM_CMD_FLASH_RANGE_CRC_gc = (0x3A<<0), /* Generate Flash Range CRC */ -} NVM_CMD_t; - -/* SPM ready interrupt level */ -typedef enum NVM_SPMLVL_enum -{ - NVM_SPMLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ - NVM_SPMLVL_LO_gc = (0x01<<2), /* Low level */ - NVM_SPMLVL_MED_gc = (0x02<<2), /* Medium level */ - NVM_SPMLVL_HI_gc = (0x03<<2), /* High level */ -} NVM_SPMLVL_t; - -/* EEPROM ready interrupt level */ -typedef enum NVM_EELVL_enum -{ - NVM_EELVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ - NVM_EELVL_LO_gc = (0x01<<0), /* Low level */ - NVM_EELVL_MED_gc = (0x02<<0), /* Medium level */ - NVM_EELVL_HI_gc = (0x03<<0), /* High level */ -} NVM_EELVL_t; - -/* Boot lock bits - boot setcion */ -typedef enum NVM_BLBB_enum -{ - NVM_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ - NVM_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ - NVM_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ - NVM_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ -} NVM_BLBB_t; - -/* Boot lock bits - application section */ -typedef enum NVM_BLBA_enum -{ - NVM_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ - NVM_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ - NVM_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ - NVM_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ -} NVM_BLBA_t; - -/* Boot lock bits - application table section */ -typedef enum NVM_BLBAT_enum -{ - NVM_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ - NVM_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ - NVM_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ - NVM_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ -} NVM_BLBAT_t; - -/* Lock bits */ -typedef enum NVM_LB_enum -{ - NVM_LB_NOLOCK_gc = (0x03<<0), /* No locks */ - NVM_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ - NVM_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ -} NVM_LB_t; - -/* Boot Loader Section Reset Vector */ -typedef enum BOOTRST_enum -{ - BOOTRST_BOOTLDR_gc = (0x00<<6), /* Boot Loader Reset */ - BOOTRST_APPLICATION_gc = (0x01<<6), /* Application Reset */ -} BOOTRST_t; - -/* BOD operation */ -typedef enum BOD_enum -{ - BOD_INSAMPLEDMODE_gc = (0x01<<0), /* BOD enabled in sampled mode */ - BOD_CONTINOUSLY_gc = (0x02<<0), /* BOD enabled continuously */ - BOD_DISABLED_gc = (0x03<<0), /* BOD Disabled */ -} BOD_t; - -/* Watchdog (Window) Timeout Period */ -typedef enum WD_enum -{ - WD_8CLK_gc = (0x00<<4), /* 8 cycles (8ms @ 3.3V) */ - WD_16CLK_gc = (0x01<<4), /* 16 cycles (16ms @ 3.3V) */ - WD_32CLK_gc = (0x02<<4), /* 32 cycles (32ms @ 3.3V) */ - WD_64CLK_gc = (0x03<<4), /* 64 cycles (64ms @ 3.3V) */ - WD_128CLK_gc = (0x04<<4), /* 128 cycles (0.125s @ 3.3V) */ - WD_256CLK_gc = (0x05<<4), /* 256 cycles (0.25s @ 3.3V) */ - WD_512CLK_gc = (0x06<<4), /* 512 cycles (0.5s @ 3.3V) */ - WD_1KCLK_gc = (0x07<<4), /* 1K cycles (1s @ 3.3V) */ - WD_2KCLK_gc = (0x08<<4), /* 2K cycles (2s @ 3.3V) */ - WD_4KCLK_gc = (0x09<<4), /* 4K cycles (4s @ 3.3V) */ - WD_8KCLK_gc = (0x0A<<4), /* 8K cycles (8s @ 3.3V) */ -} WD_t; - -/* Start-up Time */ -typedef enum SUT_enum -{ - SUT_0MS_gc = (0x03<<2), /* 0 ms */ - SUT_4MS_gc = (0x01<<2), /* 4 ms */ - SUT_64MS_gc = (0x00<<2), /* 64 ms */ -} SUT_t; - -/* Brown Out Detection Voltage Level */ -typedef enum BODLVL_enum -{ - BODLVL_1V6_gc = (0x07<<0), /* 1.6 V */ - BODLVL_1V8_gc = (0x06<<0), /* 1.8 V */ - BODLVL_2V0_gc = (0x05<<0), /* 2.0 V */ - BODLVL_2V2_gc = (0x04<<0), /* 2.2 V */ - BODLVL_2V4_gc = (0x03<<0), /* 2.4 V */ - BODLVL_2V6_gc = (0x02<<0), /* 2.6 V */ - BODLVL_2V8_gc = (0x01<<0), /* 2.8 V */ - BODLVL_3V0_gc = (0x00<<0), /* 3.0 V */ -} BODLVL_t; - - -/* --------------------------------------------------------------------------- -AC - Analog Comparator --------------------------------------------------------------------------- -*/ - -/* Analog Comparator */ -typedef struct AC_struct -{ - register8_t AC0CTRL; /* Comparator 0 Control */ - register8_t AC1CTRL; /* Comparator 1 Control */ - register8_t AC0MUXCTRL; /* Comparator 0 MUX Control */ - register8_t AC1MUXCTRL; /* Comparator 1 MUX Control */ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t WINCTRL; /* Window Mode Control */ - register8_t STATUS; /* Status */ -} AC_t; - -/* Interrupt mode */ -typedef enum AC_INTMODE_enum -{ - AC_INTMODE_BOTHEDGES_gc = (0x00<<6), /* Interrupt on both edges */ - AC_INTMODE_FALLING_gc = (0x02<<6), /* Interrupt on falling edge */ - AC_INTMODE_RISING_gc = (0x03<<6), /* Interrupt on rising edge */ -} AC_INTMODE_t; - -/* Interrupt level */ -typedef enum AC_INTLVL_enum -{ - AC_INTLVL_OFF_gc = (0x00<<4), /* Interrupt disabled */ - AC_INTLVL_LO_gc = (0x01<<4), /* Low level */ - AC_INTLVL_MED_gc = (0x02<<4), /* Medium level */ - AC_INTLVL_HI_gc = (0x03<<4), /* High level */ -} AC_INTLVL_t; - -/* Hysteresis mode selection */ -typedef enum AC_HYSMODE_enum -{ - AC_HYSMODE_NO_gc = (0x00<<1), /* No hysteresis */ - AC_HYSMODE_SMALL_gc = (0x01<<1), /* Small hysteresis */ - AC_HYSMODE_LARGE_gc = (0x02<<1), /* Large hysteresis */ -} AC_HYSMODE_t; - -/* Positive input multiplexer selection */ -typedef enum AC_MUXPOS_enum -{ - AC_MUXPOS_PIN0_gc = (0x00<<3), /* Pin 0 */ - AC_MUXPOS_PIN1_gc = (0x01<<3), /* Pin 1 */ - AC_MUXPOS_PIN2_gc = (0x02<<3), /* Pin 2 */ - AC_MUXPOS_PIN3_gc = (0x03<<3), /* Pin 3 */ - AC_MUXPOS_PIN4_gc = (0x04<<3), /* Pin 4 */ - AC_MUXPOS_PIN5_gc = (0x05<<3), /* Pin 5 */ - AC_MUXPOS_PIN6_gc = (0x06<<3), /* Pin 6 */ - AC_MUXPOS_DAC_gc = (0x07<<3), /* DAC output */ -} AC_MUXPOS_t; - -/* Negative input multiplexer selection */ -typedef enum AC_MUXNEG_enum -{ - AC_MUXNEG_PIN0_gc = (0x00<<0), /* Pin 0 */ - AC_MUXNEG_PIN1_gc = (0x01<<0), /* Pin 1 */ - AC_MUXNEG_PIN3_gc = (0x02<<0), /* Pin 3 */ - AC_MUXNEG_PIN5_gc = (0x03<<0), /* Pin 5 */ - AC_MUXNEG_PIN7_gc = (0x04<<0), /* Pin 7 */ - AC_MUXNEG_DAC_gc = (0x05<<0), /* DAC output */ - AC_MUXNEG_BANDGAP_gc = (0x06<<0), /* Bandgap Reference */ - AC_MUXNEG_SCALER_gc = (0x07<<0), /* Internal voltage scaler */ -} AC_MUXNEG_t; - -/* Windows interrupt mode */ -typedef enum AC_WINTMODE_enum -{ - AC_WINTMODE_ABOVE_gc = (0x00<<2), /* Interrupt on above window */ - AC_WINTMODE_INSIDE_gc = (0x01<<2), /* Interrupt on inside window */ - AC_WINTMODE_BELOW_gc = (0x02<<2), /* Interrupt on below window */ - AC_WINTMODE_OUTSIDE_gc = (0x03<<2), /* Interrupt on outside window */ -} AC_WINTMODE_t; - -/* Window interrupt level */ -typedef enum AC_WINTLVL_enum -{ - AC_WINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ - AC_WINTLVL_LO_gc = (0x01<<0), /* Low priority */ - AC_WINTLVL_MED_gc = (0x02<<0), /* Medium priority */ - AC_WINTLVL_HI_gc = (0x03<<0), /* High priority */ -} AC_WINTLVL_t; - -/* Window mode state */ -typedef enum AC_WSTATE_enum -{ - AC_WSTATE_ABOVE_gc = (0x00<<6), /* Signal above window */ - AC_WSTATE_INSIDE_gc = (0x01<<6), /* Signal inside window */ - AC_WSTATE_BELOW_gc = (0x02<<6), /* Signal below window */ -} AC_WSTATE_t; - - -/* --------------------------------------------------------------------------- -ADC - Analog/Digital Converter --------------------------------------------------------------------------- -*/ - -/* ADC Channel */ -typedef struct ADC_CH_struct -{ - register8_t CTRL; /* Control Register */ - register8_t MUXCTRL; /* MUX Control */ - register8_t INTCTRL; /* Channel Interrupt Control */ - register8_t INTFLAGS; /* Interrupt Flags */ - _WORDREGISTER(RES); /* Channel Result */ - register8_t reserved_0x6; - register8_t reserved_0x7; -} ADC_CH_t; - -/* --------------------------------------------------------------------------- -ADC - Analog/Digital Converter --------------------------------------------------------------------------- -*/ - -/* Analog-to-Digital Converter */ -typedef struct ADC_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t REFCTRL; /* Reference Control */ - register8_t EVCTRL; /* Event Control */ - register8_t PRESCALER; /* Clock Prescaler */ - register8_t reserved_0x05; - register8_t INTFLAGS; /* Interrupt Flags */ - register8_t reserved_0x07; - register8_t reserved_0x08; - register8_t reserved_0x09; - register8_t reserved_0x0A; - register8_t reserved_0x0B; - _WORDREGISTER(CAL); /* Calibration Value */ - register8_t reserved_0x0E; - register8_t reserved_0x0F; - _WORDREGISTER(CH0RES); /* Channel 0 Result */ - register8_t reserved_0x12; - register8_t reserved_0x13; - register8_t reserved_0x14; - register8_t reserved_0x15; - register8_t reserved_0x16; - register8_t reserved_0x17; - _WORDREGISTER(CMP); /* Compare Value */ - register8_t reserved_0x1A; - register8_t reserved_0x1B; - register8_t reserved_0x1C; - register8_t reserved_0x1D; - register8_t reserved_0x1E; - register8_t reserved_0x1F; - ADC_CH_t CH0; /* ADC Channel 0 */ -} ADC_t; - -/* Current Limitation */ -typedef enum ADC_CURRLIMIT_enum -{ - ADC_CURRLIMIT_NO_gc = (0x00<<5), /* No current limit, 300ksps max sampling rate */ - ADC_CURRLIMIT_LOW_gc = (0x01<<5), /* Low current limit, 225ksps max sampling rate */ - ADC_CURRLIMIT_MED_gc = (0x02<<5), /* Medium current limit, 150ksps max sampling rate */ - ADC_CURRLIMIT_HIGH_gc = (0x03<<5), /* High current limit, 75ksps max sampling rate */ -} ADC_CURRLIMIT_t; - -/* Positive input multiplexer selection */ -typedef enum ADC_CH_MUXPOS_enum -{ - ADC_CH_MUXPOS_PIN0_gc = (0x00<<3), /* Input pin 0 */ - ADC_CH_MUXPOS_PIN1_gc = (0x01<<3), /* Input pin 1 */ - ADC_CH_MUXPOS_PIN2_gc = (0x02<<3), /* Input pin 2 */ - ADC_CH_MUXPOS_PIN3_gc = (0x03<<3), /* Input pin 3 */ - ADC_CH_MUXPOS_PIN4_gc = (0x04<<3), /* Input pin 4 */ - ADC_CH_MUXPOS_PIN5_gc = (0x05<<3), /* Input pin 5 */ - ADC_CH_MUXPOS_PIN6_gc = (0x06<<3), /* Input pin 6 */ - ADC_CH_MUXPOS_PIN7_gc = (0x07<<3), /* Input pin 7 */ -} ADC_CH_MUXPOS_t; - -/* Internal input multiplexer selections */ -typedef enum ADC_CH_MUXINT_enum -{ - ADC_CH_MUXINT_TEMP_gc = (0x00<<3), /* Temperature Reference */ - ADC_CH_MUXINT_BANDGAP_gc = (0x01<<3), /* Bandgap Reference */ - ADC_CH_MUXINT_SCALEDVCC_gc = (0x02<<3), /* 1/10 scaled VCC */ - ADC_CH_MUXINT_DAC_gc = (0x03<<3), /* DAC output */ -} ADC_CH_MUXINT_t; - -/* Negative input multiplexer selection */ -typedef enum ADC_CH_MUXNEG_enum -{ - ADC_CH_MUXNEG_PIN0_gc = (0x00<<0), /* Input pin 0 */ - ADC_CH_MUXNEG_PIN1_gc = (0x01<<0), /* Input pin 1 */ - ADC_CH_MUXNEG_PIN2_gc = (0x02<<0), /* Input pin 2 */ - ADC_CH_MUXNEG_PIN3_gc = (0x03<<0), /* Input pin 3 */ - ADC_CH_MUXNEG_PIN4_gc = (0x04<<0), /* Input pin 4 */ - ADC_CH_MUXNEG_PIN5_gc = (0x05<<0), /* Input pin 5 */ - ADC_CH_MUXNEG_PIN6_gc = (0x06<<0), /* Input pin 6 */ - ADC_CH_MUXNEG_PIN7_gc = (0x07<<0), /* Input pin 7 */ -} ADC_CH_MUXNEG_t; - -/* Input mode */ -typedef enum ADC_CH_INPUTMODE_enum -{ - ADC_CH_INPUTMODE_INTERNAL_gc = (0x00<<0), /* Internal inputs, no gain */ - ADC_CH_INPUTMODE_SINGLEENDED_gc = (0x01<<0), /* Single-ended input, no gain */ - ADC_CH_INPUTMODE_DIFF_gc = (0x02<<0), /* Differential input, no gain */ - ADC_CH_INPUTMODE_DIFFWGAIN_gc = (0x03<<0), /* Differential input, with gain */ -} ADC_CH_INPUTMODE_t; - -/* Gain factor */ -typedef enum ADC_CH_GAIN_enum -{ - ADC_CH_GAIN_1X_gc = (0x00<<2), /* 1x gain */ - ADC_CH_GAIN_2X_gc = (0x01<<2), /* 2x gain */ - ADC_CH_GAIN_4X_gc = (0x02<<2), /* 4x gain */ - ADC_CH_GAIN_8X_gc = (0x03<<2), /* 8x gain */ - ADC_CH_GAIN_16X_gc = (0x04<<2), /* 16x gain */ - ADC_CH_GAIN_32X_gc = (0x05<<2), /* 32x gain */ - ADC_CH_GAIN_64X_gc = (0x06<<2), /* 64x gain */ - ADC_CH_GAIN_DIV2_gc = (0x07<<2), /* x/2 gain */ -} ADC_CH_GAIN_t; - -/* Conversion result resolution */ -typedef enum ADC_RESOLUTION_enum -{ - ADC_RESOLUTION_12BIT_gc = (0x00<<1), /* 12-bit right-adjusted result */ - ADC_RESOLUTION_8BIT_gc = (0x02<<1), /* 8-bit right-adjusted result */ - ADC_RESOLUTION_LEFT12BIT_gc = (0x03<<1), /* 12-bit left-adjusted result */ -} ADC_RESOLUTION_t; - -/* Voltage reference selection */ -typedef enum ADC_REFSEL_enum -{ - ADC_REFSEL_INT1V_gc = (0x00<<4), /* Internal 1V */ - ADC_REFSEL_VCC_gc = (0x01<<4), /* Internal VCC/1.6V */ - ADC_REFSEL_AREFA_gc = (0x02<<4), /* External reference on PORT A */ - ADC_REFSEL_AREFB_gc = (0x03<<4), /* External reference on PORT B */ -} ADC_REFSEL_t; - -/* Channel sweep selection */ -typedef enum ADC_SWEEP_enum -{ - ADC_SWEEP_0_gc = (0x00<<6), /* ADC Channel 0 */ -} ADC_SWEEP_t; - -/* Event channel input selection */ -typedef enum ADC_EVSEL_enum -{ - ADC_EVSEL_0123_gc = (0x00<<3), /* Event Channel 0,1,2,3 */ - ADC_EVSEL_1234_gc = (0x01<<3), /* Event Channel 1,2,3,4 */ - ADC_EVSEL_2345_gc = (0x02<<3), /* Event Channel 2,3,4,5 */ - ADC_EVSEL_3456_gc = (0x03<<3), /* Event Channel 3,4,5,6 */ - ADC_EVSEL_4567_gc = (0x04<<3), /* Event Channel 4,5,6,7 */ - ADC_EVSEL_567_gc = (0x05<<3), /* Event Channel 5,6,7 */ - ADC_EVSEL_67_gc = (0x06<<3), /* Event Channel 6,7 */ - ADC_EVSEL_7_gc = (0x07<<3), /* Event Channel 7 */ -} ADC_EVSEL_t; - -/* Event action selection */ -typedef enum ADC_EVACT_enum -{ - ADC_EVACT_NONE_gc = (0x00<<0), /* No event action */ - ADC_EVACT_CH0_gc = (0x01<<0), /* First event triggers channel 0 */ -} ADC_EVACT_t; - -/* Interupt mode */ -typedef enum ADC_CH_INTMODE_enum -{ - ADC_CH_INTMODE_COMPLETE_gc = (0x00<<2), /* Interrupt on conversion complete */ - ADC_CH_INTMODE_BELOW_gc = (0x01<<2), /* Interrupt on result below compare value */ - ADC_CH_INTMODE_ABOVE_gc = (0x03<<2), /* Interrupt on result above compare value */ -} ADC_CH_INTMODE_t; - -/* Interrupt level */ -typedef enum ADC_CH_INTLVL_enum -{ - ADC_CH_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ - ADC_CH_INTLVL_LO_gc = (0x01<<0), /* Low level */ - ADC_CH_INTLVL_MED_gc = (0x02<<0), /* Medium level */ - ADC_CH_INTLVL_HI_gc = (0x03<<0), /* High level */ -} ADC_CH_INTLVL_t; - -/* Clock prescaler */ -typedef enum ADC_PRESCALER_enum -{ - ADC_PRESCALER_DIV4_gc = (0x00<<0), /* Divide clock by 4 */ - ADC_PRESCALER_DIV8_gc = (0x01<<0), /* Divide clock by 8 */ - ADC_PRESCALER_DIV16_gc = (0x02<<0), /* Divide clock by 16 */ - ADC_PRESCALER_DIV32_gc = (0x03<<0), /* Divide clock by 32 */ - ADC_PRESCALER_DIV64_gc = (0x04<<0), /* Divide clock by 64 */ - ADC_PRESCALER_DIV128_gc = (0x05<<0), /* Divide clock by 128 */ - ADC_PRESCALER_DIV256_gc = (0x06<<0), /* Divide clock by 256 */ - ADC_PRESCALER_DIV512_gc = (0x07<<0), /* Divide clock by 512 */ -} ADC_PRESCALER_t; - - -/* --------------------------------------------------------------------------- -RTC - Real-Time Clounter --------------------------------------------------------------------------- -*/ - -/* Real-Time Counter */ -typedef struct RTC_struct -{ - register8_t CTRL; /* Control Register */ - register8_t STATUS; /* Status Register */ - register8_t INTCTRL; /* Interrupt Control Register */ - register8_t INTFLAGS; /* Interrupt Flags */ - register8_t TEMP; /* Temporary register */ - register8_t reserved_0x05; - register8_t reserved_0x06; - register8_t reserved_0x07; - _WORDREGISTER(CNT); /* Count Register */ - _WORDREGISTER(PER); /* Period Register */ - _WORDREGISTER(COMP); /* Compare Register */ -} RTC_t; - -/* Prescaler Factor */ -typedef enum RTC_PRESCALER_enum -{ - RTC_PRESCALER_OFF_gc = (0x00<<0), /* RTC Off */ - RTC_PRESCALER_DIV1_gc = (0x01<<0), /* RTC Clock */ - RTC_PRESCALER_DIV2_gc = (0x02<<0), /* RTC Clock / 2 */ - RTC_PRESCALER_DIV8_gc = (0x03<<0), /* RTC Clock / 8 */ - RTC_PRESCALER_DIV16_gc = (0x04<<0), /* RTC Clock / 16 */ - RTC_PRESCALER_DIV64_gc = (0x05<<0), /* RTC Clock / 64 */ - RTC_PRESCALER_DIV256_gc = (0x06<<0), /* RTC Clock / 256 */ - RTC_PRESCALER_DIV1024_gc = (0x07<<0), /* RTC Clock / 1024 */ -} RTC_PRESCALER_t; - -/* Compare Interrupt level */ -typedef enum RTC_COMPINTLVL_enum -{ - RTC_COMPINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ - RTC_COMPINTLVL_LO_gc = (0x01<<2), /* Low Level */ - RTC_COMPINTLVL_MED_gc = (0x02<<2), /* Medium Level */ - RTC_COMPINTLVL_HI_gc = (0x03<<2), /* High Level */ -} RTC_COMPINTLVL_t; - -/* Overflow Interrupt level */ -typedef enum RTC_OVFINTLVL_enum -{ - RTC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - RTC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ - RTC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ - RTC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ -} RTC_OVFINTLVL_t; - - -/* --------------------------------------------------------------------------- -EBI - External Bus Interface --------------------------------------------------------------------------- -*/ - -/* EBI Chip Select Module */ -typedef struct EBI_CS_struct -{ - register8_t CTRLA; /* Chip Select Control Register A */ - register8_t CTRLB; /* Chip Select Control Register B */ - _WORDREGISTER(BASEADDR); /* Chip Select Base Address */ -} EBI_CS_t; - -/* --------------------------------------------------------------------------- -EBI - External Bus Interface --------------------------------------------------------------------------- -*/ - -/* External Bus Interface */ -typedef struct EBI_struct -{ - register8_t CTRL; /* Control */ - register8_t SDRAMCTRLA; /* SDRAM Control Register A */ - register8_t reserved_0x02; - register8_t reserved_0x03; - _WORDREGISTER(REFRESH); /* SDRAM Refresh Period */ - _WORDREGISTER(INITDLY); /* SDRAM Initialization Delay */ - register8_t SDRAMCTRLB; /* SDRAM Control Register B */ - register8_t SDRAMCTRLC; /* SDRAM Control Register C */ - register8_t reserved_0x0A; - register8_t reserved_0x0B; - register8_t reserved_0x0C; - register8_t reserved_0x0D; - register8_t reserved_0x0E; - register8_t reserved_0x0F; - EBI_CS_t CS0; /* Chip Select 0 */ - EBI_CS_t CS1; /* Chip Select 1 */ - EBI_CS_t CS2; /* Chip Select 2 */ - EBI_CS_t CS3; /* Chip Select 3 */ -} EBI_t; - -/* Chip Select adress space */ -typedef enum EBI_CS_ASIZE_enum -{ - EBI_CS_ASIZE_256B_gc = (0x00<<2), /* 256 bytes */ - EBI_CS_ASIZE_512B_gc = (0x01<<2), /* 512 bytes */ - EBI_CS_ASIZE_1KB_gc = (0x02<<2), /* 1K bytes */ - EBI_CS_ASIZE_2KB_gc = (0x03<<2), /* 2K bytes */ - EBI_CS_ASIZE_4KB_gc = (0x04<<2), /* 4K bytes */ - EBI_CS_ASIZE_8KB_gc = (0x05<<2), /* 8K bytes */ - EBI_CS_ASIZE_16KB_gc = (0x06<<2), /* 16K bytes */ - EBI_CS_ASIZE_32KB_gc = (0x07<<2), /* 32K bytes */ - EBI_CS_ASIZE_64KB_gc = (0x08<<2), /* 64K bytes */ - EBI_CS_ASIZE_128KB_gc = (0x09<<2), /* 128K bytes */ - EBI_CS_ASIZE_256KB_gc = (0x0A<<2), /* 256K bytes */ - EBI_CS_ASIZE_512KB_gc = (0x0B<<2), /* 512K bytes */ - EBI_CS_ASIZE_1MB_gc = (0x0C<<2), /* 1M bytes */ - EBI_CS_ASIZE_2MB_gc = (0x0D<<2), /* 2M bytes */ - EBI_CS_ASIZE_4MB_gc = (0x0E<<2), /* 4M bytes */ - EBI_CS_ASIZE_8MB_gc = (0x0F<<2), /* 8M bytes */ - EBI_CS_ASIZE_16M_gc = (0x10<<2), /* 16M bytes */ -} EBI_CS_ASIZE_t; - -/* */ -typedef enum EBI_CS_SRWS_enum -{ - EBI_CS_SRWS_0CLK_gc = (0x00<<0), /* 0 cycles */ - EBI_CS_SRWS_1CLK_gc = (0x01<<0), /* 1 cycle */ - EBI_CS_SRWS_2CLK_gc = (0x02<<0), /* 2 cycles */ - EBI_CS_SRWS_3CLK_gc = (0x03<<0), /* 3 cycles */ - EBI_CS_SRWS_4CLK_gc = (0x04<<0), /* 4 cycles */ - EBI_CS_SRWS_5CLK_gc = (0x05<<0), /* 5 cycle */ - EBI_CS_SRWS_6CLK_gc = (0x06<<0), /* 6 cycles */ - EBI_CS_SRWS_7CLK_gc = (0x07<<0), /* 7 cycles */ -} EBI_CS_SRWS_t; - -/* Chip Select address mode */ -typedef enum EBI_CS_MODE_enum -{ - EBI_CS_MODE_DISABLED_gc = (0x00<<0), /* Chip Select Disabled */ - EBI_CS_MODE_SRAM_gc = (0x01<<0), /* Chip Select in SRAM mode */ - EBI_CS_MODE_LPC_gc = (0x02<<0), /* Chip Select in SRAM LPC mode */ - EBI_CS_MODE_SDRAM_gc = (0x03<<0), /* Chip Select in SDRAM mode */ -} EBI_CS_MODE_t; - -/* Chip Select SDRAM mode */ -typedef enum EBI_CS_SDMODE_enum -{ - EBI_CS_SDMODE_NORMAL_gc = (0x00<<0), /* Normal mode */ - EBI_CS_SDMODE_LOAD_gc = (0x01<<0), /* Load Mode Register command mode */ -} EBI_CS_SDMODE_t; - -/* */ -typedef enum EBI_SDDATAW_enum -{ - EBI_SDDATAW_4BIT_gc = (0x00<<6), /* 4-bit data bus */ - EBI_SDDATAW_8BIT_gc = (0x01<<6), /* 8-bit data bus */ -} EBI_SDDATAW_t; - -/* */ -typedef enum EBI_LPCMODE_enum -{ - EBI_LPCMODE_ALE1_gc = (0x00<<4), /* Data muxed with addr byte 0 */ - EBI_LPCMODE_ALE12_gc = (0x02<<4), /* Data muxed with addr byte 0 and 1 */ -} EBI_LPCMODE_t; - -/* */ -typedef enum EBI_SRMODE_enum -{ - EBI_SRMODE_ALE1_gc = (0x00<<2), /* Addr byte 0 muxed with 1 */ - EBI_SRMODE_ALE2_gc = (0x01<<2), /* Addr byte 0 muxed with 2 */ - EBI_SRMODE_ALE12_gc = (0x02<<2), /* Addr byte 0 muxed with 1 and 2 */ - EBI_SRMODE_NOALE_gc = (0x03<<2), /* No addr muxing */ -} EBI_SRMODE_t; - -/* */ -typedef enum EBI_IFMODE_enum -{ - EBI_IFMODE_DISABLED_gc = (0x00<<0), /* EBI Disabled */ - EBI_IFMODE_3PORT_gc = (0x01<<0), /* 3-port mode */ - EBI_IFMODE_4PORT_gc = (0x02<<0), /* 4-port mode */ - EBI_IFMODE_2PORT_gc = (0x03<<0), /* 2-port mode */ -} EBI_IFMODE_t; - -/* */ -typedef enum EBI_SDCOL_enum -{ - EBI_SDCOL_8BIT_gc = (0x00<<0), /* 8 column bits */ - EBI_SDCOL_9BIT_gc = (0x01<<0), /* 9 column bits */ - EBI_SDCOL_10BIT_gc = (0x02<<0), /* 10 column bits */ - EBI_SDCOL_11BIT_gc = (0x03<<0), /* 11 column bits */ -} EBI_SDCOL_t; - -/* */ -typedef enum EBI_MRDLY_enum -{ - EBI_MRDLY_0CLK_gc = (0x00<<6), /* 0 cycles */ - EBI_MRDLY_1CLK_gc = (0x01<<6), /* 1 cycle */ - EBI_MRDLY_2CLK_gc = (0x02<<6), /* 2 cycles */ - EBI_MRDLY_3CLK_gc = (0x03<<6), /* 3 cycles */ -} EBI_MRDLY_t; - -/* */ -typedef enum EBI_ROWCYCDLY_enum -{ - EBI_ROWCYCDLY_0CLK_gc = (0x00<<3), /* 0 cycles */ - EBI_ROWCYCDLY_1CLK_gc = (0x01<<3), /* 1 cycle */ - EBI_ROWCYCDLY_2CLK_gc = (0x02<<3), /* 2 cycles */ - EBI_ROWCYCDLY_3CLK_gc = (0x03<<3), /* 3 cycles */ - EBI_ROWCYCDLY_4CLK_gc = (0x04<<3), /* 4 cycles */ - EBI_ROWCYCDLY_5CLK_gc = (0x05<<3), /* 5 cycle */ - EBI_ROWCYCDLY_6CLK_gc = (0x06<<3), /* 6 cycles */ - EBI_ROWCYCDLY_7CLK_gc = (0x07<<3), /* 7 cycles */ -} EBI_ROWCYCDLY_t; - -/* */ -typedef enum EBI_RPDLY_enum -{ - EBI_RPDLY_0CLK_gc = (0x00<<0), /* 0 cycles */ - EBI_RPDLY_1CLK_gc = (0x01<<0), /* 1 cycle */ - EBI_RPDLY_2CLK_gc = (0x02<<0), /* 2 cycles */ - EBI_RPDLY_3CLK_gc = (0x03<<0), /* 3 cycles */ - EBI_RPDLY_4CLK_gc = (0x04<<0), /* 4 cycles */ - EBI_RPDLY_5CLK_gc = (0x05<<0), /* 5 cycle */ - EBI_RPDLY_6CLK_gc = (0x06<<0), /* 6 cycles */ - EBI_RPDLY_7CLK_gc = (0x07<<0), /* 7 cycles */ -} EBI_RPDLY_t; - -/* */ -typedef enum EBI_WRDLY_enum -{ - EBI_WRDLY_0CLK_gc = (0x00<<6), /* 0 cycles */ - EBI_WRDLY_1CLK_gc = (0x01<<6), /* 1 cycle */ - EBI_WRDLY_2CLK_gc = (0x02<<6), /* 2 cycles */ - EBI_WRDLY_3CLK_gc = (0x03<<6), /* 3 cycles */ -} EBI_WRDLY_t; - -/* */ -typedef enum EBI_ESRDLY_enum -{ - EBI_ESRDLY_0CLK_gc = (0x00<<3), /* 0 cycles */ - EBI_ESRDLY_1CLK_gc = (0x01<<3), /* 1 cycle */ - EBI_ESRDLY_2CLK_gc = (0x02<<3), /* 2 cycles */ - EBI_ESRDLY_3CLK_gc = (0x03<<3), /* 3 cycles */ - EBI_ESRDLY_4CLK_gc = (0x04<<3), /* 4 cycles */ - EBI_ESRDLY_5CLK_gc = (0x05<<3), /* 5 cycle */ - EBI_ESRDLY_6CLK_gc = (0x06<<3), /* 6 cycles */ - EBI_ESRDLY_7CLK_gc = (0x07<<3), /* 7 cycles */ -} EBI_ESRDLY_t; - -/* */ -typedef enum EBI_ROWCOLDLY_enum -{ - EBI_ROWCOLDLY_0CLK_gc = (0x00<<0), /* 0 cycles */ - EBI_ROWCOLDLY_1CLK_gc = (0x01<<0), /* 1 cycle */ - EBI_ROWCOLDLY_2CLK_gc = (0x02<<0), /* 2 cycles */ - EBI_ROWCOLDLY_3CLK_gc = (0x03<<0), /* 3 cycles */ - EBI_ROWCOLDLY_4CLK_gc = (0x04<<0), /* 4 cycles */ - EBI_ROWCOLDLY_5CLK_gc = (0x05<<0), /* 5 cycle */ - EBI_ROWCOLDLY_6CLK_gc = (0x06<<0), /* 6 cycles */ - EBI_ROWCOLDLY_7CLK_gc = (0x07<<0), /* 7 cycles */ -} EBI_ROWCOLDLY_t; - - -/* --------------------------------------------------------------------------- -TWI - Two-Wire Interface --------------------------------------------------------------------------- -*/ - -/* */ -typedef struct TWI_MASTER_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t CTRLC; /* Control Register C */ - register8_t STATUS; /* Status Register */ - register8_t BAUD; /* Baurd Rate Control Register */ - register8_t ADDR; /* Address Register */ - register8_t DATA; /* Data Register */ -} TWI_MASTER_t; - -/* --------------------------------------------------------------------------- -TWI - Two-Wire Interface --------------------------------------------------------------------------- -*/ - -/* */ -typedef struct TWI_SLAVE_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t STATUS; /* Status Register */ - register8_t ADDR; /* Address Register */ - register8_t DATA; /* Data Register */ - register8_t ADDRMASK; /* Address Mask Register */ -} TWI_SLAVE_t; - -/* --------------------------------------------------------------------------- -TWI - Two-Wire Interface --------------------------------------------------------------------------- -*/ - -/* Two-Wire Interface */ -typedef struct TWI_struct -{ - register8_t CTRL; /* TWI Common Control Register */ - TWI_MASTER_t MASTER; /* TWI master module */ - TWI_SLAVE_t SLAVE; /* TWI slave module */ -} TWI_t; - -/* Master Interrupt Level */ -typedef enum TWI_MASTER_INTLVL_enum -{ - TWI_MASTER_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ - TWI_MASTER_INTLVL_LO_gc = (0x01<<6), /* Low Level */ - TWI_MASTER_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ - TWI_MASTER_INTLVL_HI_gc = (0x03<<6), /* High Level */ -} TWI_MASTER_INTLVL_t; - -/* Inactive Timeout */ -typedef enum TWI_MASTER_TIMEOUT_enum -{ - TWI_MASTER_TIMEOUT_DISABLED_gc = (0x00<<2), /* Bus Timeout Disabled */ - TWI_MASTER_TIMEOUT_50US_gc = (0x01<<2), /* 50 Microseconds */ - TWI_MASTER_TIMEOUT_100US_gc = (0x02<<2), /* 100 Microseconds */ - TWI_MASTER_TIMEOUT_200US_gc = (0x03<<2), /* 200 Microseconds */ -} TWI_MASTER_TIMEOUT_t; - -/* Master Command */ -typedef enum TWI_MASTER_CMD_enum -{ - TWI_MASTER_CMD_NOACT_gc = (0x00<<0), /* No Action */ - TWI_MASTER_CMD_REPSTART_gc = (0x01<<0), /* Issue Repeated Start Condition */ - TWI_MASTER_CMD_RECVTRANS_gc = (0x02<<0), /* Receive or Transmit Data */ - TWI_MASTER_CMD_STOP_gc = (0x03<<0), /* Issue Stop Condition */ -} TWI_MASTER_CMD_t; - -/* Master Bus State */ -typedef enum TWI_MASTER_BUSSTATE_enum -{ - TWI_MASTER_BUSSTATE_UNKNOWN_gc = (0x00<<0), /* Unknown Bus State */ - TWI_MASTER_BUSSTATE_IDLE_gc = (0x01<<0), /* Bus is Idle */ - TWI_MASTER_BUSSTATE_OWNER_gc = (0x02<<0), /* This Module Controls The Bus */ - TWI_MASTER_BUSSTATE_BUSY_gc = (0x03<<0), /* The Bus is Busy */ -} TWI_MASTER_BUSSTATE_t; - -/* Slave Interrupt Level */ -typedef enum TWI_SLAVE_INTLVL_enum -{ - TWI_SLAVE_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ - TWI_SLAVE_INTLVL_LO_gc = (0x01<<6), /* Low Level */ - TWI_SLAVE_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ - TWI_SLAVE_INTLVL_HI_gc = (0x03<<6), /* High Level */ -} TWI_SLAVE_INTLVL_t; - -/* Slave Command */ -typedef enum TWI_SLAVE_CMD_enum -{ - TWI_SLAVE_CMD_NOACT_gc = (0x00<<0), /* No Action */ - TWI_SLAVE_CMD_COMPTRANS_gc = (0x02<<0), /* Used To Complete a Transaction */ - TWI_SLAVE_CMD_RESPONSE_gc = (0x03<<0), /* Used in Response to Address/Data Interrupt */ -} TWI_SLAVE_CMD_t; - - -/* --------------------------------------------------------------------------- -PORT - Port Configuration --------------------------------------------------------------------------- -*/ - -/* I/O port Configuration */ -typedef struct PORTCFG_struct -{ - register8_t MPCMASK; /* Multi-pin Configuration Mask */ - register8_t reserved_0x01; - register8_t VPCTRLA; /* Virtual Port Control Register A */ - register8_t VPCTRLB; /* Virtual Port Control Register B */ - register8_t CLKEVOUT; /* Clock and Event Out Register */ -} PORTCFG_t; - -/* --------------------------------------------------------------------------- -PORT - Port Configuration --------------------------------------------------------------------------- -*/ - -/* Virtual Port */ -typedef struct VPORT_struct -{ - register8_t DIR; /* I/O Port Data Direction */ - register8_t OUT; /* I/O Port Output */ - register8_t IN; /* I/O Port Input */ - register8_t INTFLAGS; /* Interrupt Flag Register */ -} VPORT_t; - -/* --------------------------------------------------------------------------- -PORT - Port Configuration --------------------------------------------------------------------------- -*/ - -/* I/O Ports */ -typedef struct PORT_struct -{ - register8_t DIR; /* I/O Port Data Direction */ - register8_t DIRSET; /* I/O Port Data Direction Set */ - register8_t DIRCLR; /* I/O Port Data Direction Clear */ - register8_t DIRTGL; /* I/O Port Data Direction Toggle */ - register8_t OUT; /* I/O Port Output */ - register8_t OUTSET; /* I/O Port Output Set */ - register8_t OUTCLR; /* I/O Port Output Clear */ - register8_t OUTTGL; /* I/O Port Output Toggle */ - register8_t IN; /* I/O port Input */ - register8_t INTCTRL; /* Interrupt Control Register */ - register8_t INT0MASK; /* Port Interrupt 0 Mask */ - register8_t INT1MASK; /* Port Interrupt 1 Mask */ - register8_t INTFLAGS; /* Interrupt Flag Register */ - register8_t reserved_0x0D; - register8_t reserved_0x0E; - register8_t reserved_0x0F; - register8_t PIN0CTRL; /* Pin 0 Control Register */ - register8_t PIN1CTRL; /* Pin 1 Control Register */ - register8_t PIN2CTRL; /* Pin 2 Control Register */ - register8_t PIN3CTRL; /* Pin 3 Control Register */ - register8_t PIN4CTRL; /* Pin 4 Control Register */ - register8_t PIN5CTRL; /* Pin 5 Control Register */ - register8_t PIN6CTRL; /* Pin 6 Control Register */ - register8_t PIN7CTRL; /* Pin 7 Control Register */ -} PORT_t; - -/* Virtual Port 0 Mapping */ -typedef enum PORTCFG_VP0MAP_enum -{ - PORTCFG_VP0MAP_PORTA_gc = (0x00<<0), /* Mapped To PORTA */ - PORTCFG_VP0MAP_PORTB_gc = (0x01<<0), /* Mapped To PORTB */ - PORTCFG_VP0MAP_PORTC_gc = (0x02<<0), /* Mapped To PORTC */ - PORTCFG_VP0MAP_PORTD_gc = (0x03<<0), /* Mapped To PORTD */ - PORTCFG_VP0MAP_PORTE_gc = (0x04<<0), /* Mapped To PORTE */ - PORTCFG_VP0MAP_PORTF_gc = (0x05<<0), /* Mapped To PORTF */ - PORTCFG_VP0MAP_PORTG_gc = (0x06<<0), /* Mapped To PORTG */ - PORTCFG_VP0MAP_PORTH_gc = (0x07<<0), /* Mapped To PORTH */ - PORTCFG_VP0MAP_PORTJ_gc = (0x08<<0), /* Mapped To PORTJ */ - PORTCFG_VP0MAP_PORTK_gc = (0x09<<0), /* Mapped To PORTK */ - PORTCFG_VP0MAP_PORTL_gc = (0x0A<<0), /* Mapped To PORTL */ - PORTCFG_VP0MAP_PORTM_gc = (0x0B<<0), /* Mapped To PORTM */ - PORTCFG_VP0MAP_PORTN_gc = (0x0C<<0), /* Mapped To PORTN */ - PORTCFG_VP0MAP_PORTP_gc = (0x0D<<0), /* Mapped To PORTP */ - PORTCFG_VP0MAP_PORTQ_gc = (0x0E<<0), /* Mapped To PORTQ */ - PORTCFG_VP0MAP_PORTR_gc = (0x0F<<0), /* Mapped To PORTR */ -} PORTCFG_VP0MAP_t; - -/* Virtual Port 1 Mapping */ -typedef enum PORTCFG_VP1MAP_enum -{ - PORTCFG_VP1MAP_PORTA_gc = (0x00<<4), /* Mapped To PORTA */ - PORTCFG_VP1MAP_PORTB_gc = (0x01<<4), /* Mapped To PORTB */ - PORTCFG_VP1MAP_PORTC_gc = (0x02<<4), /* Mapped To PORTC */ - PORTCFG_VP1MAP_PORTD_gc = (0x03<<4), /* Mapped To PORTD */ - PORTCFG_VP1MAP_PORTE_gc = (0x04<<4), /* Mapped To PORTE */ - PORTCFG_VP1MAP_PORTF_gc = (0x05<<4), /* Mapped To PORTF */ - PORTCFG_VP1MAP_PORTG_gc = (0x06<<4), /* Mapped To PORTG */ - PORTCFG_VP1MAP_PORTH_gc = (0x07<<4), /* Mapped To PORTH */ - PORTCFG_VP1MAP_PORTJ_gc = (0x08<<4), /* Mapped To PORTJ */ - PORTCFG_VP1MAP_PORTK_gc = (0x09<<4), /* Mapped To PORTK */ - PORTCFG_VP1MAP_PORTL_gc = (0x0A<<4), /* Mapped To PORTL */ - PORTCFG_VP1MAP_PORTM_gc = (0x0B<<4), /* Mapped To PORTM */ - PORTCFG_VP1MAP_PORTN_gc = (0x0C<<4), /* Mapped To PORTN */ - PORTCFG_VP1MAP_PORTP_gc = (0x0D<<4), /* Mapped To PORTP */ - PORTCFG_VP1MAP_PORTQ_gc = (0x0E<<4), /* Mapped To PORTQ */ - PORTCFG_VP1MAP_PORTR_gc = (0x0F<<4), /* Mapped To PORTR */ -} PORTCFG_VP1MAP_t; - -/* Virtual Port 2 Mapping */ -typedef enum PORTCFG_VP2MAP_enum -{ - PORTCFG_VP2MAP_PORTA_gc = (0x00<<0), /* Mapped To PORTA */ - PORTCFG_VP2MAP_PORTB_gc = (0x01<<0), /* Mapped To PORTB */ - PORTCFG_VP2MAP_PORTC_gc = (0x02<<0), /* Mapped To PORTC */ - PORTCFG_VP2MAP_PORTD_gc = (0x03<<0), /* Mapped To PORTD */ - PORTCFG_VP2MAP_PORTE_gc = (0x04<<0), /* Mapped To PORTE */ - PORTCFG_VP2MAP_PORTF_gc = (0x05<<0), /* Mapped To PORTF */ - PORTCFG_VP2MAP_PORTG_gc = (0x06<<0), /* Mapped To PORTG */ - PORTCFG_VP2MAP_PORTH_gc = (0x07<<0), /* Mapped To PORTH */ - PORTCFG_VP2MAP_PORTJ_gc = (0x08<<0), /* Mapped To PORTJ */ - PORTCFG_VP2MAP_PORTK_gc = (0x09<<0), /* Mapped To PORTK */ - PORTCFG_VP2MAP_PORTL_gc = (0x0A<<0), /* Mapped To PORTL */ - PORTCFG_VP2MAP_PORTM_gc = (0x0B<<0), /* Mapped To PORTM */ - PORTCFG_VP2MAP_PORTN_gc = (0x0C<<0), /* Mapped To PORTN */ - PORTCFG_VP2MAP_PORTP_gc = (0x0D<<0), /* Mapped To PORTP */ - PORTCFG_VP2MAP_PORTQ_gc = (0x0E<<0), /* Mapped To PORTQ */ - PORTCFG_VP2MAP_PORTR_gc = (0x0F<<0), /* Mapped To PORTR */ -} PORTCFG_VP2MAP_t; - -/* Virtual Port 3 Mapping */ -typedef enum PORTCFG_VP3MAP_enum -{ - PORTCFG_VP3MAP_PORTA_gc = (0x00<<4), /* Mapped To PORTA */ - PORTCFG_VP3MAP_PORTB_gc = (0x01<<4), /* Mapped To PORTB */ - PORTCFG_VP3MAP_PORTC_gc = (0x02<<4), /* Mapped To PORTC */ - PORTCFG_VP3MAP_PORTD_gc = (0x03<<4), /* Mapped To PORTD */ - PORTCFG_VP3MAP_PORTE_gc = (0x04<<4), /* Mapped To PORTE */ - PORTCFG_VP3MAP_PORTF_gc = (0x05<<4), /* Mapped To PORTF */ - PORTCFG_VP3MAP_PORTG_gc = (0x06<<4), /* Mapped To PORTG */ - PORTCFG_VP3MAP_PORTH_gc = (0x07<<4), /* Mapped To PORTH */ - PORTCFG_VP3MAP_PORTJ_gc = (0x08<<4), /* Mapped To PORTJ */ - PORTCFG_VP3MAP_PORTK_gc = (0x09<<4), /* Mapped To PORTK */ - PORTCFG_VP3MAP_PORTL_gc = (0x0A<<4), /* Mapped To PORTL */ - PORTCFG_VP3MAP_PORTM_gc = (0x0B<<4), /* Mapped To PORTM */ - PORTCFG_VP3MAP_PORTN_gc = (0x0C<<4), /* Mapped To PORTN */ - PORTCFG_VP3MAP_PORTP_gc = (0x0D<<4), /* Mapped To PORTP */ - PORTCFG_VP3MAP_PORTQ_gc = (0x0E<<4), /* Mapped To PORTQ */ - PORTCFG_VP3MAP_PORTR_gc = (0x0F<<4), /* Mapped To PORTR */ -} PORTCFG_VP3MAP_t; - -/* Clock Output Port */ -typedef enum PORTCFG_CLKOUT_enum -{ - PORTCFG_CLKOUT_OFF_gc = (0x00<<0), /* Clock Output Disabled */ - PORTCFG_CLKOUT_PC7_gc = (0x01<<0), /* Clock Output on Port C pin 7 */ - PORTCFG_CLKOUT_PD7_gc = (0x02<<0), /* Clock Output on Port D pin 7 */ - PORTCFG_CLKOUT_PE7_gc = (0x03<<0), /* Clock Output on Port E pin 7 */ -} PORTCFG_CLKOUT_t; - -/* Event Output Port */ -typedef enum PORTCFG_EVOUT_enum -{ - PORTCFG_EVOUT_OFF_gc = (0x00<<4), /* Event Output Disabled */ - PORTCFG_EVOUT_PC7_gc = (0x01<<4), /* Event Channel 7 Output on Port C pin 7 */ - PORTCFG_EVOUT_PD7_gc = (0x02<<4), /* Event Channel 7 Output on Port D pin 7 */ - PORTCFG_EVOUT_PE7_gc = (0x03<<4), /* Event Channel 7 Output on Port E pin 7 */ -} PORTCFG_EVOUT_t; - -/* Port Interrupt 0 Level */ -typedef enum PORT_INT0LVL_enum -{ - PORT_INT0LVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - PORT_INT0LVL_LO_gc = (0x01<<0), /* Low Level */ - PORT_INT0LVL_MED_gc = (0x02<<0), /* Medium Level */ - PORT_INT0LVL_HI_gc = (0x03<<0), /* High Level */ -} PORT_INT0LVL_t; - -/* Port Interrupt 1 Level */ -typedef enum PORT_INT1LVL_enum -{ - PORT_INT1LVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ - PORT_INT1LVL_LO_gc = (0x01<<2), /* Low Level */ - PORT_INT1LVL_MED_gc = (0x02<<2), /* Medium Level */ - PORT_INT1LVL_HI_gc = (0x03<<2), /* High Level */ -} PORT_INT1LVL_t; - -/* Output/Pull Configuration */ -typedef enum PORT_OPC_enum -{ - PORT_OPC_TOTEM_gc = (0x00<<3), /* Totempole */ - PORT_OPC_BUSKEEPER_gc = (0x01<<3), /* Totempole w/ Bus keeper on Input and Output */ - PORT_OPC_PULLDOWN_gc = (0x02<<3), /* Totempole w/ Pull-down on Input */ - PORT_OPC_PULLUP_gc = (0x03<<3), /* Totempole w/ Pull-up on Input */ - PORT_OPC_WIREDOR_gc = (0x04<<3), /* Wired OR */ - PORT_OPC_WIREDAND_gc = (0x05<<3), /* Wired AND */ - PORT_OPC_WIREDORPULL_gc = (0x06<<3), /* Wired OR w/ Pull-down */ - PORT_OPC_WIREDANDPULL_gc = (0x07<<3), /* Wired AND w/ Pull-up */ -} PORT_OPC_t; - -/* Input/Sense Configuration */ -typedef enum PORT_ISC_enum -{ - PORT_ISC_BOTHEDGES_gc = (0x00<<0), /* Sense Both Edges */ - PORT_ISC_RISING_gc = (0x01<<0), /* Sense Rising Edge */ - PORT_ISC_FALLING_gc = (0x02<<0), /* Sense Falling Edge */ - PORT_ISC_LEVEL_gc = (0x03<<0), /* Sense Level (Transparent For Events) */ - PORT_ISC_INPUT_DISABLE_gc = (0x07<<0), /* Disable Digital Input Buffer */ -} PORT_ISC_t; - - -/* --------------------------------------------------------------------------- -TC - 16-bit Timer/Counter With PWM --------------------------------------------------------------------------- -*/ - -/* 16-bit Timer/Counter 0 */ -typedef struct TC0_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t CTRLC; /* Control register C */ - register8_t CTRLD; /* Control Register D */ - register8_t CTRLE; /* Control Register E */ - register8_t reserved_0x05; - register8_t INTCTRLA; /* Interrupt Control Register A */ - register8_t INTCTRLB; /* Interrupt Control Register B */ - register8_t CTRLFCLR; /* Control Register F Clear */ - register8_t CTRLFSET; /* Control Register F Set */ - register8_t CTRLGCLR; /* Control Register G Clear */ - register8_t CTRLGSET; /* Control Register G Set */ - register8_t INTFLAGS; /* Interrupt Flag Register */ - register8_t reserved_0x0D; - register8_t reserved_0x0E; - register8_t TEMP; /* Temporary Register For 16-bit Access */ - register8_t reserved_0x10; - register8_t reserved_0x11; - register8_t reserved_0x12; - register8_t reserved_0x13; - register8_t reserved_0x14; - register8_t reserved_0x15; - register8_t reserved_0x16; - register8_t reserved_0x17; - register8_t reserved_0x18; - register8_t reserved_0x19; - register8_t reserved_0x1A; - register8_t reserved_0x1B; - register8_t reserved_0x1C; - register8_t reserved_0x1D; - register8_t reserved_0x1E; - register8_t reserved_0x1F; - _WORDREGISTER(CNT); /* Count */ - register8_t reserved_0x22; - register8_t reserved_0x23; - register8_t reserved_0x24; - register8_t reserved_0x25; - _WORDREGISTER(PER); /* Period */ - _WORDREGISTER(CCA); /* Compare or Capture A */ - _WORDREGISTER(CCB); /* Compare or Capture B */ - _WORDREGISTER(CCC); /* Compare or Capture C */ - _WORDREGISTER(CCD); /* Compare or Capture D */ - register8_t reserved_0x30; - register8_t reserved_0x31; - register8_t reserved_0x32; - register8_t reserved_0x33; - register8_t reserved_0x34; - register8_t reserved_0x35; - _WORDREGISTER(PERBUF); /* Period Buffer */ - _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ - _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ - _WORDREGISTER(CCCBUF); /* Compare Or Capture C Buffer */ - _WORDREGISTER(CCDBUF); /* Compare Or Capture D Buffer */ -} TC0_t; - -/* --------------------------------------------------------------------------- -TC - 16-bit Timer/Counter With PWM --------------------------------------------------------------------------- -*/ - -/* 16-bit Timer/Counter 1 */ -typedef struct TC1_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t CTRLC; /* Control register C */ - register8_t CTRLD; /* Control Register D */ - register8_t CTRLE; /* Control Register E */ - register8_t reserved_0x05; - register8_t INTCTRLA; /* Interrupt Control Register A */ - register8_t INTCTRLB; /* Interrupt Control Register B */ - register8_t CTRLFCLR; /* Control Register F Clear */ - register8_t CTRLFSET; /* Control Register F Set */ - register8_t CTRLGCLR; /* Control Register G Clear */ - register8_t CTRLGSET; /* Control Register G Set */ - register8_t INTFLAGS; /* Interrupt Flag Register */ - register8_t reserved_0x0D; - register8_t reserved_0x0E; - register8_t TEMP; /* Temporary Register For 16-bit Access */ - register8_t reserved_0x10; - register8_t reserved_0x11; - register8_t reserved_0x12; - register8_t reserved_0x13; - register8_t reserved_0x14; - register8_t reserved_0x15; - register8_t reserved_0x16; - register8_t reserved_0x17; - register8_t reserved_0x18; - register8_t reserved_0x19; - register8_t reserved_0x1A; - register8_t reserved_0x1B; - register8_t reserved_0x1C; - register8_t reserved_0x1D; - register8_t reserved_0x1E; - register8_t reserved_0x1F; - _WORDREGISTER(CNT); /* Count */ - register8_t reserved_0x22; - register8_t reserved_0x23; - register8_t reserved_0x24; - register8_t reserved_0x25; - _WORDREGISTER(PER); /* Period */ - _WORDREGISTER(CCA); /* Compare or Capture A */ - _WORDREGISTER(CCB); /* Compare or Capture B */ - register8_t reserved_0x2C; - register8_t reserved_0x2D; - register8_t reserved_0x2E; - register8_t reserved_0x2F; - register8_t reserved_0x30; - register8_t reserved_0x31; - register8_t reserved_0x32; - register8_t reserved_0x33; - register8_t reserved_0x34; - register8_t reserved_0x35; - _WORDREGISTER(PERBUF); /* Period Buffer */ - _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ - _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ -} TC1_t; - -/* --------------------------------------------------------------------------- -TC - 16-bit Timer/Counter With PWM --------------------------------------------------------------------------- -*/ - -/* Advanced Waveform Extension */ -typedef struct AWEX_struct -{ - register8_t CTRL; /* Control Register */ - register8_t reserved_0x01; - register8_t FDEMASK; /* Fault Detection Event Mask */ - register8_t FDCTRL; /* Fault Detection Control Register */ - register8_t STATUS; /* Status Register */ - register8_t reserved_0x05; - register8_t DTBOTH; /* Dead Time Both Sides */ - register8_t DTBOTHBUF; /* Dead Time Both Sides Buffer */ - register8_t DTLS; /* Dead Time Low Side */ - register8_t DTHS; /* Dead Time High Side */ - register8_t DTLSBUF; /* Dead Time Low Side Buffer */ - register8_t DTHSBUF; /* Dead Time High Side Buffer */ - register8_t OUTOVEN; /* Output Override Enable */ -} AWEX_t; - -/* --------------------------------------------------------------------------- -TC - 16-bit Timer/Counter With PWM --------------------------------------------------------------------------- -*/ - -/* High-Resolution Extension */ -typedef struct HIRES_struct -{ - register8_t CTRLA; /* Control Register */ -} HIRES_t; - -/* Clock Selection */ -typedef enum TC_CLKSEL_enum -{ - TC_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */ - TC_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */ - TC_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */ - TC_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */ - TC_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */ - TC_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */ - TC_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */ - TC_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */ - TC_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */ - TC_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */ - TC_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */ - TC_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */ - TC_CLKSEL_EVCH4_gc = (0x0C<<0), /* Event Channel 4 */ - TC_CLKSEL_EVCH5_gc = (0x0D<<0), /* Event Channel 5 */ - TC_CLKSEL_EVCH6_gc = (0x0E<<0), /* Event Channel 6 */ - TC_CLKSEL_EVCH7_gc = (0x0F<<0), /* Event Channel 7 */ -} TC_CLKSEL_t; - -/* Waveform Generation Mode */ -typedef enum TC_WGMODE_enum -{ - TC_WGMODE_NORMAL_gc = (0x00<<0), /* Normal Mode */ - TC_WGMODE_FRQ_gc = (0x01<<0), /* Frequency Generation Mode */ - TC_WGMODE_SS_gc = (0x03<<0), /* Single Slope */ - TC_WGMODE_DS_T_gc = (0x05<<0), /* Dual Slope, Update on TOP */ - TC_WGMODE_DS_TB_gc = (0x06<<0), /* Dual Slope, Update on TOP and BOTTOM */ - TC_WGMODE_DS_B_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */ -} TC_WGMODE_t; - -/* Event Action */ -typedef enum TC_EVACT_enum -{ - TC_EVACT_OFF_gc = (0x00<<5), /* No Event Action */ - TC_EVACT_CAPT_gc = (0x01<<5), /* Input Capture */ - TC_EVACT_UPDOWN_gc = (0x02<<5), /* Externally Controlled Up/Down Count */ - TC_EVACT_QDEC_gc = (0x03<<5), /* Quadrature Decode */ - TC_EVACT_RESTART_gc = (0x04<<5), /* Restart */ - TC_EVACT_FRQ_gc = (0x05<<5), /* Frequency Capture */ - TC_EVACT_PW_gc = (0x06<<5), /* Pulse-width Capture */ -} TC_EVACT_t; - -/* Event Selection */ -typedef enum TC_EVSEL_enum -{ - TC_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ - TC_EVSEL_CH0_gc = (0x08<<0), /* Event Channel 0 */ - TC_EVSEL_CH1_gc = (0x09<<0), /* Event Channel 1 */ - TC_EVSEL_CH2_gc = (0x0A<<0), /* Event Channel 2 */ - TC_EVSEL_CH3_gc = (0x0B<<0), /* Event Channel 3 */ - TC_EVSEL_CH4_gc = (0x0C<<0), /* Event Channel 4 */ - TC_EVSEL_CH5_gc = (0x0D<<0), /* Event Channel 5 */ - TC_EVSEL_CH6_gc = (0x0E<<0), /* Event Channel 6 */ - TC_EVSEL_CH7_gc = (0x0F<<0), /* Event Channel 7 */ -} TC_EVSEL_t; - -/* Error Interrupt Level */ -typedef enum TC_ERRINTLVL_enum -{ - TC_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ - TC_ERRINTLVL_LO_gc = (0x01<<2), /* Low Level */ - TC_ERRINTLVL_MED_gc = (0x02<<2), /* Medium Level */ - TC_ERRINTLVL_HI_gc = (0x03<<2), /* High Level */ -} TC_ERRINTLVL_t; - -/* Overflow Interrupt Level */ -typedef enum TC_OVFINTLVL_enum -{ - TC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - TC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ - TC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ - TC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ -} TC_OVFINTLVL_t; - -/* Compare or Capture D Interrupt Level */ -typedef enum TC_CCDINTLVL_enum -{ - TC_CCDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ - TC_CCDINTLVL_LO_gc = (0x01<<6), /* Low Level */ - TC_CCDINTLVL_MED_gc = (0x02<<6), /* Medium Level */ - TC_CCDINTLVL_HI_gc = (0x03<<6), /* High Level */ -} TC_CCDINTLVL_t; - -/* Compare or Capture C Interrupt Level */ -typedef enum TC_CCCINTLVL_enum -{ - TC_CCCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ - TC_CCCINTLVL_LO_gc = (0x01<<4), /* Low Level */ - TC_CCCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ - TC_CCCINTLVL_HI_gc = (0x03<<4), /* High Level */ -} TC_CCCINTLVL_t; - -/* Compare or Capture B Interrupt Level */ -typedef enum TC_CCBINTLVL_enum -{ - TC_CCBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ - TC_CCBINTLVL_LO_gc = (0x01<<2), /* Low Level */ - TC_CCBINTLVL_MED_gc = (0x02<<2), /* Medium Level */ - TC_CCBINTLVL_HI_gc = (0x03<<2), /* High Level */ -} TC_CCBINTLVL_t; - -/* Compare or Capture A Interrupt Level */ -typedef enum TC_CCAINTLVL_enum -{ - TC_CCAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - TC_CCAINTLVL_LO_gc = (0x01<<0), /* Low Level */ - TC_CCAINTLVL_MED_gc = (0x02<<0), /* Medium Level */ - TC_CCAINTLVL_HI_gc = (0x03<<0), /* High Level */ -} TC_CCAINTLVL_t; - -/* Timer/Counter Command */ -typedef enum TC_CMD_enum -{ - TC_CMD_NONE_gc = (0x00<<2), /* No Command */ - TC_CMD_UPDATE_gc = (0x01<<2), /* Force Update */ - TC_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ - TC_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ -} TC_CMD_t; - -/* Fault Detect Action */ -typedef enum AWEX_FDACT_enum -{ - AWEX_FDACT_NONE_gc = (0x00<<0), /* No Fault Protection */ - AWEX_FDACT_CLEAROE_gc = (0x01<<0), /* Clear Output Enable Bits */ - AWEX_FDACT_CLEARDIR_gc = (0x03<<0), /* Clear I/O Port Direction Bits */ -} AWEX_FDACT_t; - -/* High Resolution Enable */ -typedef enum HIRES_HREN_enum -{ - HIRES_HREN_NONE_gc = (0x00<<0), /* No Fault Protection */ - HIRES_HREN_TC0_gc = (0x01<<0), /* Enable High Resolution on Timer/Counter 0 */ - HIRES_HREN_TC1_gc = (0x02<<0), /* Enable High Resolution on Timer/Counter 1 */ - HIRES_HREN_BOTH_gc = (0x03<<0), /* Enable High Resolution both Timer/Counters */ -} HIRES_HREN_t; - - -/* --------------------------------------------------------------------------- -USART - Universal Asynchronous Receiver-Transmitter --------------------------------------------------------------------------- -*/ - -/* Universal Synchronous/Asynchronous Receiver/Transmitter */ -typedef struct USART_struct -{ - register8_t DATA; /* Data Register */ - register8_t STATUS; /* Status Register */ - register8_t reserved_0x02; - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t CTRLC; /* Control Register C */ - register8_t BAUDCTRLA; /* Baud Rate Control Register A */ - register8_t BAUDCTRLB; /* Baud Rate Control Register B */ -} USART_t; - -/* Receive Complete Interrupt level */ -typedef enum USART_RXCINTLVL_enum -{ - USART_RXCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ - USART_RXCINTLVL_LO_gc = (0x01<<4), /* Low Level */ - USART_RXCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ - USART_RXCINTLVL_HI_gc = (0x03<<4), /* High Level */ -} USART_RXCINTLVL_t; - -/* Transmit Complete Interrupt level */ -typedef enum USART_TXCINTLVL_enum -{ - USART_TXCINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ - USART_TXCINTLVL_LO_gc = (0x01<<2), /* Low Level */ - USART_TXCINTLVL_MED_gc = (0x02<<2), /* Medium Level */ - USART_TXCINTLVL_HI_gc = (0x03<<2), /* High Level */ -} USART_TXCINTLVL_t; - -/* Data Register Empty Interrupt level */ -typedef enum USART_DREINTLVL_enum -{ - USART_DREINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - USART_DREINTLVL_LO_gc = (0x01<<0), /* Low Level */ - USART_DREINTLVL_MED_gc = (0x02<<0), /* Medium Level */ - USART_DREINTLVL_HI_gc = (0x03<<0), /* High Level */ -} USART_DREINTLVL_t; - -/* Character Size */ -typedef enum USART_CHSIZE_enum -{ - USART_CHSIZE_5BIT_gc = (0x00<<0), /* Character size: 5 bit */ - USART_CHSIZE_6BIT_gc = (0x01<<0), /* Character size: 6 bit */ - USART_CHSIZE_7BIT_gc = (0x02<<0), /* Character size: 7 bit */ - USART_CHSIZE_8BIT_gc = (0x03<<0), /* Character size: 8 bit */ - USART_CHSIZE_9BIT_gc = (0x07<<0), /* Character size: 9 bit */ -} USART_CHSIZE_t; - -/* Communication Mode */ -typedef enum USART_CMODE_enum -{ - USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6), /* Asynchronous Mode */ - USART_CMODE_SYNCHRONOUS_gc = (0x01<<6), /* Synchronous Mode */ - USART_CMODE_IRDA_gc = (0x02<<6), /* IrDA Mode */ - USART_CMODE_MSPI_gc = (0x03<<6), /* Master SPI Mode */ -} USART_CMODE_t; - -/* Parity Mode */ -typedef enum USART_PMODE_enum -{ - USART_PMODE_DISABLED_gc = (0x00<<4), /* No Parity */ - USART_PMODE_EVEN_gc = (0x02<<4), /* Even Parity */ - USART_PMODE_ODD_gc = (0x03<<4), /* Odd Parity */ -} USART_PMODE_t; - - -/* --------------------------------------------------------------------------- -SPI - Serial Peripheral Interface --------------------------------------------------------------------------- -*/ - -/* Serial Peripheral Interface */ -typedef struct SPI_struct -{ - register8_t CTRL; /* Control Register */ - register8_t INTCTRL; /* Interrupt Control Register */ - register8_t STATUS; /* Status Register */ - register8_t DATA; /* Data Register */ -} SPI_t; - -/* SPI Mode */ -typedef enum SPI_MODE_enum -{ - SPI_MODE_0_gc = (0x00<<2), /* SPI Mode 0 */ - SPI_MODE_1_gc = (0x01<<2), /* SPI Mode 1 */ - SPI_MODE_2_gc = (0x02<<2), /* SPI Mode 2 */ - SPI_MODE_3_gc = (0x03<<2), /* SPI Mode 3 */ -} SPI_MODE_t; - -/* Prescaler setting */ -typedef enum SPI_PRESCALER_enum -{ - SPI_PRESCALER_DIV4_gc = (0x00<<0), /* System Clock / 4 */ - SPI_PRESCALER_DIV16_gc = (0x01<<0), /* System Clock / 16 */ - SPI_PRESCALER_DIV64_gc = (0x02<<0), /* System Clock / 64 */ - SPI_PRESCALER_DIV128_gc = (0x03<<0), /* System Clock / 128 */ -} SPI_PRESCALER_t; - -/* Interrupt level */ -typedef enum SPI_INTLVL_enum -{ - SPI_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - SPI_INTLVL_LO_gc = (0x01<<0), /* Low Level */ - SPI_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ - SPI_INTLVL_HI_gc = (0x03<<0), /* High Level */ -} SPI_INTLVL_t; - - -/* --------------------------------------------------------------------------- -IRCOM - IR Communication Module --------------------------------------------------------------------------- -*/ - -/* IR Communication Module */ -typedef struct IRCOM_struct -{ - register8_t TXPLCTRL; /* IrDA Transmitter Pulse Length Control Register */ - register8_t RXPLCTRL; /* IrDA Receiver Pulse Length Control Register */ - register8_t CTRL; /* Control Register */ -} IRCOM_t; - -/* Event channel selection */ -typedef enum IRDA_EVSEL_enum -{ - IRDA_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ - IRDA_EVSEL_0_gc = (0x08<<0), /* Event Channel 0 */ - IRDA_EVSEL_1_gc = (0x09<<0), /* Event Channel 1 */ - IRDA_EVSEL_2_gc = (0x0A<<0), /* Event Channel 2 */ - IRDA_EVSEL_3_gc = (0x0B<<0), /* Event Channel 3 */ - IRDA_EVSEL_4_gc = (0x0C<<0), /* Event Channel 4 */ - IRDA_EVSEL_5_gc = (0x0D<<0), /* Event Channel 5 */ - IRDA_EVSEL_6_gc = (0x0E<<0), /* Event Channel 6 */ - IRDA_EVSEL_7_gc = (0x0F<<0), /* Event Channel 7 */ -} IRDA_EVSEL_t; - - - -/* -========================================================================== -IO Module Instances. Mapped to memory. -========================================================================== -*/ - -#define VPORT0 (*(VPORT_t *) 0x0010) /* Virtual Port 0 */ -#define VPORT1 (*(VPORT_t *) 0x0014) /* Virtual Port 1 */ -#define VPORT2 (*(VPORT_t *) 0x0018) /* Virtual Port 2 */ -#define VPORT3 (*(VPORT_t *) 0x001C) /* Virtual Port 3 */ -#define OCD (*(OCD_t *) 0x002E) /* On-Chip Debug System */ -#define CLK (*(CLK_t *) 0x0040) /* Clock System */ -#define SLEEP (*(SLEEP_t *) 0x0048) /* Sleep Controller */ -#define OSC (*(OSC_t *) 0x0050) /* Oscillator Control */ -#define DFLLRC32M (*(DFLL_t *) 0x0060) /* DFLL for 32MHz RC Oscillator */ -#define DFLLRC2M (*(DFLL_t *) 0x0068) /* DFLL for 2MHz RC Oscillator */ -#define PR (*(PR_t *) 0x0070) /* Power Reduction */ -#define RST (*(RST_t *) 0x0078) /* Reset Controller */ -#define WDT (*(WDT_t *) 0x0080) /* Watch-Dog Timer */ -#define MCU (*(MCU_t *) 0x0090) /* MCU Control */ -#define PMIC (*(PMIC_t *) 0x00A0) /* Programmable Interrupt Controller */ -#define PORTCFG (*(PORTCFG_t *) 0x00B0) /* Port Configuration */ -#define CRC (*(CRC_t *) 0x00D0) /* Cyclic Redundancy Checker */ -#define EVSYS (*(EVSYS_t *) 0x0180) /* Event System */ -#define NVM (*(NVM_t *) 0x01C0) /* Non Volatile Memory Controller */ -#define ADCA (*(ADC_t *) 0x0200) /* Analog to Digital Converter A */ -#define ACA (*(AC_t *) 0x0380) /* Analog Comparator A */ -#define RTC (*(RTC_t *) 0x0400) /* Real-Time Counter */ -#define TWIC (*(TWI_t *) 0x0480) /* Two-Wire Interface C */ -#define TWIE (*(TWI_t *) 0x04A0) /* Two-Wire Interface E */ -#define PORTA (*(PORT_t *) 0x0600) /* Port A */ -#define PORTB (*(PORT_t *) 0x0620) /* Port B */ -#define PORTC (*(PORT_t *) 0x0640) /* Port C */ -#define PORTD (*(PORT_t *) 0x0660) /* Port D */ -#define PORTE (*(PORT_t *) 0x0680) /* Port E */ -#define PORTF (*(PORT_t *) 0x06A0) /* Port F */ -#define PORTR (*(PORT_t *) 0x07E0) /* Port R */ -#define TCC0 (*(TC0_t *) 0x0800) /* Timer/Counter C0 */ -#define TCC1 (*(TC1_t *) 0x0840) /* Timer/Counter C1 */ -#define AWEXC (*(AWEX_t *) 0x0880) /* Advanced Waveform Extension C */ -#define HIRESC (*(HIRES_t *) 0x0890) /* High-Resolution Extension C */ -#define USARTC0 (*(USART_t *) 0x08A0) /* Universal Asynchronous Receiver-Transmitter C0 */ -#define SPIC (*(SPI_t *) 0x08C0) /* Serial Peripheral Interface C */ -#define IRCOM (*(IRCOM_t *) 0x08F8) /* IR Communication Module */ -#define TCD0 (*(TC0_t *) 0x0900) /* Timer/Counter D0 */ -#define USARTD0 (*(USART_t *) 0x09A0) /* Universal Asynchronous Receiver-Transmitter D0 */ -#define SPID (*(SPI_t *) 0x09C0) /* Serial Peripheral Interface D */ -#define TCE0 (*(TC0_t *) 0x0A00) /* Timer/Counter E0 */ -#define AWEXE (*(AWEX_t *) 0x0A80) /* Advanced Waveform Extension E */ -#define USARTE0 (*(USART_t *) 0x0AA0) /* Universal Asynchronous Receiver-Transmitter E0 */ -#define SPIE (*(SPI_t *) 0x0AC0) /* Serial Peripheral Interface E */ -#define TCF0 (*(TC0_t *) 0x0B00) /* Timer/Counter F0 */ - - -#endif /* !defined (__ASSEMBLER__) */ - - -/* ========== Flattened fully qualified IO register names ========== */ - -/* GPIO - General Purpose IO Registers */ -#define GPIO_GPIOR0 _SFR_MEM8(0x0000) -#define GPIO_GPIOR1 _SFR_MEM8(0x0001) -#define GPIO_GPIOR2 _SFR_MEM8(0x0002) -#define GPIO_GPIOR3 _SFR_MEM8(0x0003) -#define GPIO_GPIOR4 _SFR_MEM8(0x0004) -#define GPIO_GPIOR5 _SFR_MEM8(0x0005) -#define GPIO_GPIOR6 _SFR_MEM8(0x0006) -#define GPIO_GPIOR7 _SFR_MEM8(0x0007) -#define GPIO_GPIOR8 _SFR_MEM8(0x0008) -#define GPIO_GPIOR9 _SFR_MEM8(0x0009) -#define GPIO_GPIORA _SFR_MEM8(0x000A) -#define GPIO_GPIORB _SFR_MEM8(0x000B) -#define GPIO_GPIORC _SFR_MEM8(0x000C) -#define GPIO_GPIORD _SFR_MEM8(0x000D) -#define GPIO_GPIORE _SFR_MEM8(0x000E) -#define GPIO_GPIORF _SFR_MEM8(0x000F) - -/* VPORT0 - Virtual Port 0 */ -#define VPORT0_DIR _SFR_MEM8(0x0010) -#define VPORT0_OUT _SFR_MEM8(0x0011) -#define VPORT0_IN _SFR_MEM8(0x0012) -#define VPORT0_INTFLAGS _SFR_MEM8(0x0013) - -/* VPORT1 - Virtual Port 1 */ -#define VPORT1_DIR _SFR_MEM8(0x0014) -#define VPORT1_OUT _SFR_MEM8(0x0015) -#define VPORT1_IN _SFR_MEM8(0x0016) -#define VPORT1_INTFLAGS _SFR_MEM8(0x0017) - -/* VPORT2 - Virtual Port 2 */ -#define VPORT2_DIR _SFR_MEM8(0x0018) -#define VPORT2_OUT _SFR_MEM8(0x0019) -#define VPORT2_IN _SFR_MEM8(0x001A) -#define VPORT2_INTFLAGS _SFR_MEM8(0x001B) - -/* VPORT3 - Virtual Port 3 */ -#define VPORT3_DIR _SFR_MEM8(0x001C) -#define VPORT3_OUT _SFR_MEM8(0x001D) -#define VPORT3_IN _SFR_MEM8(0x001E) -#define VPORT3_INTFLAGS _SFR_MEM8(0x001F) - -/* OCD - On-Chip Debug System */ -#define OCD_OCDR0 _SFR_MEM8(0x002E) -#define OCD_OCDR1 _SFR_MEM8(0x002F) - -/* CPU - CPU Registers */ -#define CPU_CCP _SFR_MEM8(0x0034) -#define CPU_RAMPD _SFR_MEM8(0x0038) -#define CPU_RAMPX _SFR_MEM8(0x0039) -#define CPU_RAMPY _SFR_MEM8(0x003A) -#define CPU_RAMPZ _SFR_MEM8(0x003B) -#define CPU_EIND _SFR_MEM8(0x003C) -#define CPU_SPL _SFR_MEM8(0x003D) -#define CPU_SPH _SFR_MEM8(0x003E) -#define CPU_SREG _SFR_MEM8(0x003F) - -/* CLK - Clock System */ -#define CLK_CTRL _SFR_MEM8(0x0040) -#define CLK_PSCTRL _SFR_MEM8(0x0041) -#define CLK_LOCK _SFR_MEM8(0x0042) -#define CLK_RTCCTRL _SFR_MEM8(0x0043) - -/* SLEEP - Sleep Controller */ -#define SLEEP_CTRL _SFR_MEM8(0x0048) - -/* OSC - Oscillator Control */ -#define OSC_CTRL _SFR_MEM8(0x0050) -#define OSC_STATUS _SFR_MEM8(0x0051) -#define OSC_XOSCCTRL _SFR_MEM8(0x0052) -#define OSC_XOSCFAIL _SFR_MEM8(0x0053) -#define OSC_RC32KCAL _SFR_MEM8(0x0054) -#define OSC_PLLCTRL _SFR_MEM8(0x0055) -#define OSC_DFLLCTRL _SFR_MEM8(0x0056) - -/* DFLLRC32M - DFLL for 32MHz RC Oscillator */ -#define DFLLRC32M_CTRL _SFR_MEM8(0x0060) -#define DFLLRC32M_CALA _SFR_MEM8(0x0062) -#define DFLLRC32M_CALB _SFR_MEM8(0x0063) -#define DFLLRC32M_COMP0 _SFR_MEM8(0x0064) -#define DFLLRC32M_COMP1 _SFR_MEM8(0x0065) -#define DFLLRC32M_COMP2 _SFR_MEM8(0x0066) - -/* DFLLRC2M - DFLL for 2MHz RC Oscillator */ -#define DFLLRC2M_CTRL _SFR_MEM8(0x0068) -#define DFLLRC2M_CALA _SFR_MEM8(0x006A) -#define DFLLRC2M_CALB _SFR_MEM8(0x006B) -#define DFLLRC2M_COMP0 _SFR_MEM8(0x006C) -#define DFLLRC2M_COMP1 _SFR_MEM8(0x006D) -#define DFLLRC2M_COMP2 _SFR_MEM8(0x006E) - -/* PR - Power Reduction */ -#define PR_PRGEN _SFR_MEM8(0x0070) -#define PR_PRPA _SFR_MEM8(0x0071) -#define PR_PRPC _SFR_MEM8(0x0073) -#define PR_PRPD _SFR_MEM8(0x0074) -#define PR_PRPE _SFR_MEM8(0x0075) -#define PR_PRPF _SFR_MEM8(0x0076) - -/* RST - Reset Controller */ -#define RST_STATUS _SFR_MEM8(0x0078) -#define RST_CTRL _SFR_MEM8(0x0079) - -/* WDT - Watch-Dog Timer */ -#define WDT_CTRL _SFR_MEM8(0x0080) -#define WDT_WINCTRL _SFR_MEM8(0x0081) -#define WDT_STATUS _SFR_MEM8(0x0082) - -/* MCU - MCU Control */ -#define MCU_DEVID0 _SFR_MEM8(0x0090) -#define MCU_DEVID1 _SFR_MEM8(0x0091) -#define MCU_DEVID2 _SFR_MEM8(0x0092) -#define MCU_REVID _SFR_MEM8(0x0093) -#define MCU_JTAGUID _SFR_MEM8(0x0094) -#define MCU_MCUCR _SFR_MEM8(0x0096) -#define MCU_EVSYSLOCK _SFR_MEM8(0x0098) -#define MCU_AWEXLOCK _SFR_MEM8(0x0099) - -/* PMIC - Programmable Interrupt Controller */ -#define PMIC_STATUS _SFR_MEM8(0x00A0) -#define PMIC_INTPRI _SFR_MEM8(0x00A1) -#define PMIC_CTRL _SFR_MEM8(0x00A2) - -/* PORTCFG - Port Configuration */ -#define PORTCFG_MPCMASK _SFR_MEM8(0x00B0) -#define PORTCFG_VPCTRLA _SFR_MEM8(0x00B2) -#define PORTCFG_VPCTRLB _SFR_MEM8(0x00B3) -#define PORTCFG_CLKEVOUT _SFR_MEM8(0x00B4) - -/* CRC - Cyclic Redundancy Checker */ -#define CRC_CTRL _SFR_MEM8(0x00D0) -#define CRC_STATUS _SFR_MEM8(0x00D1) -#define CRC_DATAIN _SFR_MEM8(0x00D3) -#define CRC_CHECKSUM0 _SFR_MEM8(0x00D4) -#define CRC_CHECKSUM1 _SFR_MEM8(0x00D5) -#define CRC_CHECKSUM2 _SFR_MEM8(0x00D6) -#define CRC_CHECKSUM3 _SFR_MEM8(0x00D7) - -/* EVSYS - Event System */ -#define EVSYS_CH0MUX _SFR_MEM8(0x0180) -#define EVSYS_CH1MUX _SFR_MEM8(0x0181) -#define EVSYS_CH2MUX _SFR_MEM8(0x0182) -#define EVSYS_CH3MUX _SFR_MEM8(0x0183) -#define EVSYS_CH0CTRL _SFR_MEM8(0x0188) -#define EVSYS_CH1CTRL _SFR_MEM8(0x0189) -#define EVSYS_CH2CTRL _SFR_MEM8(0x018A) -#define EVSYS_CH3CTRL _SFR_MEM8(0x018B) -#define EVSYS_STROBE _SFR_MEM8(0x0190) -#define EVSYS_DATA _SFR_MEM8(0x0191) - -/* NVM - Non Volatile Memory Controller */ -#define NVM_ADDR0 _SFR_MEM8(0x01C0) -#define NVM_ADDR1 _SFR_MEM8(0x01C1) -#define NVM_ADDR2 _SFR_MEM8(0x01C2) -#define NVM_DATA0 _SFR_MEM8(0x01C4) -#define NVM_DATA1 _SFR_MEM8(0x01C5) -#define NVM_DATA2 _SFR_MEM8(0x01C6) -#define NVM_CMD _SFR_MEM8(0x01CA) -#define NVM_CTRLA _SFR_MEM8(0x01CB) -#define NVM_CTRLB _SFR_MEM8(0x01CC) -#define NVM_INTCTRL _SFR_MEM8(0x01CD) -#define NVM_STATUS _SFR_MEM8(0x01CF) -#define NVM_LOCKBITS _SFR_MEM8(0x01D0) - -/* ADCA - Analog to Digital Converter A */ -#define ADCA_CTRLA _SFR_MEM8(0x0200) -#define ADCA_CTRLB _SFR_MEM8(0x0201) -#define ADCA_REFCTRL _SFR_MEM8(0x0202) -#define ADCA_EVCTRL _SFR_MEM8(0x0203) -#define ADCA_PRESCALER _SFR_MEM8(0x0204) -#define ADCA_INTFLAGS _SFR_MEM8(0x0206) -#define ADCA_CAL _SFR_MEM16(0x020C) -#define ADCA_CH0RES _SFR_MEM16(0x0210) -#define ADCA_CMP _SFR_MEM16(0x0218) -#define ADCA_CH0_CTRL _SFR_MEM8(0x0220) -#define ADCA_CH0_MUXCTRL _SFR_MEM8(0x0221) -#define ADCA_CH0_INTCTRL _SFR_MEM8(0x0222) -#define ADCA_CH0_INTFLAGS _SFR_MEM8(0x0223) -#define ADCA_CH0_RES _SFR_MEM16(0x0224) - -/* ACA - Analog Comparator A */ -#define ACA_AC0CTRL _SFR_MEM8(0x0380) -#define ACA_AC1CTRL _SFR_MEM8(0x0381) -#define ACA_AC0MUXCTRL _SFR_MEM8(0x0382) -#define ACA_AC1MUXCTRL _SFR_MEM8(0x0383) -#define ACA_CTRLA _SFR_MEM8(0x0384) -#define ACA_CTRLB _SFR_MEM8(0x0385) -#define ACA_WINCTRL _SFR_MEM8(0x0386) -#define ACA_STATUS _SFR_MEM8(0x0387) - -/* RTC - Real-Time Counter */ -#define RTC_CTRL _SFR_MEM8(0x0400) -#define RTC_STATUS _SFR_MEM8(0x0401) -#define RTC_INTCTRL _SFR_MEM8(0x0402) -#define RTC_INTFLAGS _SFR_MEM8(0x0403) -#define RTC_TEMP _SFR_MEM8(0x0404) -#define RTC_CNT _SFR_MEM16(0x0408) -#define RTC_PER _SFR_MEM16(0x040A) -#define RTC_COMP _SFR_MEM16(0x040C) - -/* TWIC - Two-Wire Interface C */ -#define TWIC_CTRL _SFR_MEM8(0x0480) -#define TWIC_MASTER_CTRLA _SFR_MEM8(0x0482) -#define TWIC_MASTER_CTRLB _SFR_MEM8(0x0483) -#define TWIC_MASTER_CTRLC _SFR_MEM8(0x0484) -#define TWIC_MASTER_STATUS _SFR_MEM8(0x0485) -#define TWIC_MASTER_BAUD _SFR_MEM8(0x0486) -#define TWIC_MASTER_ADDR _SFR_MEM8(0x0487) -#define TWIC_MASTER_DATA _SFR_MEM8(0x0488) -#define TWIC_SLAVE_CTRLA _SFR_MEM8(0x0488) -#define TWIC_SLAVE_CTRLB _SFR_MEM8(0x0489) -#define TWIC_SLAVE_STATUS _SFR_MEM8(0x048A) -#define TWIC_SLAVE_ADDR _SFR_MEM8(0x048B) -#define TWIC_SLAVE_DATA _SFR_MEM8(0x048C) -#define TWIC_SLAVE_ADDRMASK _SFR_MEM8(0x048D) - -/* TWIE - Two-Wire Interface E */ -#define TWIE_CTRL _SFR_MEM8(0x04A0) -#define TWIE_MASTER_CTRLA _SFR_MEM8(0x04A1) -#define TWIE_MASTER_CTRLB _SFR_MEM8(0x04A2) -#define TWIE_MASTER_CTRLC _SFR_MEM8(0x04A3) -#define TWIE_MASTER_STATUS _SFR_MEM8(0x04A4) -#define TWIE_MASTER_BAUD _SFR_MEM8(0x04A5) -#define TWIE_MASTER_ADDR _SFR_MEM8(0x04A6) -#define TWIE_MASTER_DATA _SFR_MEM8(0x04A7) -#define TWIE_SLAVE_CTRLA _SFR_MEM8(0x04A8) -#define TWIE_SLAVE_CTRLB _SFR_MEM8(0x04A9) -#define TWIE_SLAVE_STATUS _SFR_MEM8(0x04AA) -#define TWIE_SLAVE_ADDR _SFR_MEM8(0x04AB) -#define TWIE_SLAVE_DATA _SFR_MEM8(0x04AC) -#define TWIE_SLAVE_ADDRMASK _SFR_MEM8(0x04AD) - -/* PORTA - Port A */ -#define PORTA_DIR _SFR_MEM8(0x0600) -#define PORTA_DIRSET _SFR_MEM8(0x0601) -#define PORTA_DIRCLR _SFR_MEM8(0x0602) -#define PORTA_DIRTGL _SFR_MEM8(0x0603) -#define PORTA_OUT _SFR_MEM8(0x0604) -#define PORTA_OUTSET _SFR_MEM8(0x0605) -#define PORTA_OUTCLR _SFR_MEM8(0x0606) -#define PORTA_OUTTGL _SFR_MEM8(0x0607) -#define PORTA_IN _SFR_MEM8(0x0608) -#define PORTA_INTCTRL _SFR_MEM8(0x0609) -#define PORTA_INT0MASK _SFR_MEM8(0x060A) -#define PORTA_INT1MASK _SFR_MEM8(0x060B) -#define PORTA_INTFLAGS _SFR_MEM8(0x060C) -#define PORTA_PIN0CTRL _SFR_MEM8(0x0610) -#define PORTA_PIN1CTRL _SFR_MEM8(0x0611) -#define PORTA_PIN2CTRL _SFR_MEM8(0x0612) -#define PORTA_PIN3CTRL _SFR_MEM8(0x0613) -#define PORTA_PIN4CTRL _SFR_MEM8(0x0614) -#define PORTA_PIN5CTRL _SFR_MEM8(0x0615) -#define PORTA_PIN6CTRL _SFR_MEM8(0x0616) -#define PORTA_PIN7CTRL _SFR_MEM8(0x0617) - -/* PORTB - Port B */ -#define PORTB_DIR _SFR_MEM8(0x0620) -#define PORTB_DIRSET _SFR_MEM8(0x0621) -#define PORTB_DIRCLR _SFR_MEM8(0x0622) -#define PORTB_DIRTGL _SFR_MEM8(0x0623) -#define PORTB_OUT _SFR_MEM8(0x0624) -#define PORTB_OUTSET _SFR_MEM8(0x0625) -#define PORTB_OUTCLR _SFR_MEM8(0x0626) -#define PORTB_OUTTGL _SFR_MEM8(0x0627) -#define PORTB_IN _SFR_MEM8(0x0628) -#define PORTB_INTCTRL _SFR_MEM8(0x0629) -#define PORTB_INT0MASK _SFR_MEM8(0x062A) -#define PORTB_INT1MASK _SFR_MEM8(0x062B) -#define PORTB_INTFLAGS _SFR_MEM8(0x062C) -#define PORTB_PIN0CTRL _SFR_MEM8(0x0630) -#define PORTB_PIN1CTRL _SFR_MEM8(0x0631) -#define PORTB_PIN2CTRL _SFR_MEM8(0x0632) -#define PORTB_PIN3CTRL _SFR_MEM8(0x0633) -#define PORTB_PIN4CTRL _SFR_MEM8(0x0634) -#define PORTB_PIN5CTRL _SFR_MEM8(0x0635) -#define PORTB_PIN6CTRL _SFR_MEM8(0x0636) -#define PORTB_PIN7CTRL _SFR_MEM8(0x0637) - -/* PORTC - Port C */ -#define PORTC_DIR _SFR_MEM8(0x0640) -#define PORTC_DIRSET _SFR_MEM8(0x0641) -#define PORTC_DIRCLR _SFR_MEM8(0x0642) -#define PORTC_DIRTGL _SFR_MEM8(0x0643) -#define PORTC_OUT _SFR_MEM8(0x0644) -#define PORTC_OUTSET _SFR_MEM8(0x0645) -#define PORTC_OUTCLR _SFR_MEM8(0x0646) -#define PORTC_OUTTGL _SFR_MEM8(0x0647) -#define PORTC_IN _SFR_MEM8(0x0648) -#define PORTC_INTCTRL _SFR_MEM8(0x0649) -#define PORTC_INT0MASK _SFR_MEM8(0x064A) -#define PORTC_INT1MASK _SFR_MEM8(0x064B) -#define PORTC_INTFLAGS _SFR_MEM8(0x064C) -#define PORTC_PIN0CTRL _SFR_MEM8(0x0650) -#define PORTC_PIN1CTRL _SFR_MEM8(0x0651) -#define PORTC_PIN2CTRL _SFR_MEM8(0x0652) -#define PORTC_PIN3CTRL _SFR_MEM8(0x0653) -#define PORTC_PIN4CTRL _SFR_MEM8(0x0654) -#define PORTC_PIN5CTRL _SFR_MEM8(0x0655) -#define PORTC_PIN6CTRL _SFR_MEM8(0x0656) -#define PORTC_PIN7CTRL _SFR_MEM8(0x0657) - -/* PORTD - Port D */ -#define PORTD_DIR _SFR_MEM8(0x0660) -#define PORTD_DIRSET _SFR_MEM8(0x0661) -#define PORTD_DIRCLR _SFR_MEM8(0x0662) -#define PORTD_DIRTGL _SFR_MEM8(0x0663) -#define PORTD_OUT _SFR_MEM8(0x0664) -#define PORTD_OUTSET _SFR_MEM8(0x0665) -#define PORTD_OUTCLR _SFR_MEM8(0x0666) -#define PORTD_OUTTGL _SFR_MEM8(0x0667) -#define PORTD_IN _SFR_MEM8(0x0668) -#define PORTD_INTCTRL _SFR_MEM8(0x0669) -#define PORTD_INT0MASK _SFR_MEM8(0x066A) -#define PORTD_INT1MASK _SFR_MEM8(0x066B) -#define PORTD_INTFLAGS _SFR_MEM8(0x066C) -#define PORTD_PIN0CTRL _SFR_MEM8(0x0670) -#define PORTD_PIN1CTRL _SFR_MEM8(0x0671) -#define PORTD_PIN2CTRL _SFR_MEM8(0x0672) -#define PORTD_PIN3CTRL _SFR_MEM8(0x0673) -#define PORTD_PIN4CTRL _SFR_MEM8(0x0674) -#define PORTD_PIN5CTRL _SFR_MEM8(0x0675) -#define PORTD_PIN6CTRL _SFR_MEM8(0x0676) -#define PORTD_PIN7CTRL _SFR_MEM8(0x0677) - -/* PORTE - Port E */ -#define PORTE_DIR _SFR_MEM8(0x0680) -#define PORTE_DIRSET _SFR_MEM8(0x0681) -#define PORTE_DIRCLR _SFR_MEM8(0x0682) -#define PORTE_DIRTGL _SFR_MEM8(0x0683) -#define PORTE_OUT _SFR_MEM8(0x0684) -#define PORTE_OUTSET _SFR_MEM8(0x0685) -#define PORTE_OUTCLR _SFR_MEM8(0x0686) -#define PORTE_OUTTGL _SFR_MEM8(0x0687) -#define PORTE_IN _SFR_MEM8(0x0688) -#define PORTE_INTCTRL _SFR_MEM8(0x0689) -#define PORTE_INT0MASK _SFR_MEM8(0x068A) -#define PORTE_INT1MASK _SFR_MEM8(0x068B) -#define PORTE_INTFLAGS _SFR_MEM8(0x068C) -#define PORTE_PIN0CTRL _SFR_MEM8(0x0690) -#define PORTE_PIN1CTRL _SFR_MEM8(0x0691) -#define PORTE_PIN2CTRL _SFR_MEM8(0x0692) -#define PORTE_PIN3CTRL _SFR_MEM8(0x0693) -#define PORTE_PIN4CTRL _SFR_MEM8(0x0694) -#define PORTE_PIN5CTRL _SFR_MEM8(0x0695) -#define PORTE_PIN6CTRL _SFR_MEM8(0x0696) -#define PORTE_PIN7CTRL _SFR_MEM8(0x0697) - -/* PORTF - Port F */ -#define PORTF_DIR _SFR_MEM8(0x06A0) -#define PORTF_DIRSET _SFR_MEM8(0x06A1) -#define PORTF_DIRCLR _SFR_MEM8(0x06A2) -#define PORTF_DIRTGL _SFR_MEM8(0x06A3) -#define PORTF_OUT _SFR_MEM8(0x06A4) -#define PORTF_OUTSET _SFR_MEM8(0x06A5) -#define PORTF_OUTCLR _SFR_MEM8(0x06A6) -#define PORTF_OUTTGL _SFR_MEM8(0x06A7) -#define PORTF_IN _SFR_MEM8(0x06A8) -#define PORTF_INTCTRL _SFR_MEM8(0x06A9) -#define PORTF_INT0MASK _SFR_MEM8(0x06AA) -#define PORTF_INT1MASK _SFR_MEM8(0x06AB) -#define PORTF_INTFLAGS _SFR_MEM8(0x06AC) -#define PORTF_PIN0CTRL _SFR_MEM8(0x06B0) -#define PORTF_PIN1CTRL _SFR_MEM8(0x06B1) -#define PORTF_PIN2CTRL _SFR_MEM8(0x06B2) -#define PORTF_PIN3CTRL _SFR_MEM8(0x06B3) -#define PORTF_PIN4CTRL _SFR_MEM8(0x06B4) -#define PORTF_PIN5CTRL _SFR_MEM8(0x06B5) -#define PORTF_PIN6CTRL _SFR_MEM8(0x06B6) -#define PORTF_PIN7CTRL _SFR_MEM8(0x06B7) - -/* PORTR - Port R */ -#define PORTR_DIR _SFR_MEM8(0x07E0) -#define PORTR_DIRSET _SFR_MEM8(0x07E1) -#define PORTR_DIRCLR _SFR_MEM8(0x07E2) -#define PORTR_DIRTGL _SFR_MEM8(0x07E3) -#define PORTR_OUT _SFR_MEM8(0x07E4) -#define PORTR_OUTSET _SFR_MEM8(0x07E5) -#define PORTR_OUTCLR _SFR_MEM8(0x07E6) -#define PORTR_OUTTGL _SFR_MEM8(0x07E7) -#define PORTR_IN _SFR_MEM8(0x07E8) -#define PORTR_INTCTRL _SFR_MEM8(0x07E9) -#define PORTR_INT0MASK _SFR_MEM8(0x07EA) -#define PORTR_INT1MASK _SFR_MEM8(0x07EB) -#define PORTR_INTFLAGS _SFR_MEM8(0x07EC) -#define PORTR_PIN0CTRL _SFR_MEM8(0x07F0) -#define PORTR_PIN1CTRL _SFR_MEM8(0x07F1) -#define PORTR_PIN2CTRL _SFR_MEM8(0x07F2) -#define PORTR_PIN3CTRL _SFR_MEM8(0x07F3) -#define PORTR_PIN4CTRL _SFR_MEM8(0x07F4) -#define PORTR_PIN5CTRL _SFR_MEM8(0x07F5) -#define PORTR_PIN6CTRL _SFR_MEM8(0x07F6) -#define PORTR_PIN7CTRL _SFR_MEM8(0x07F7) - -/* TCC0 - Timer/Counter C0 */ -#define TCC0_CTRLA _SFR_MEM8(0x0800) -#define TCC0_CTRLB _SFR_MEM8(0x0801) -#define TCC0_CTRLC _SFR_MEM8(0x0802) -#define TCC0_CTRLD _SFR_MEM8(0x0803) -#define TCC0_CTRLE _SFR_MEM8(0x0804) -#define TCC0_INTCTRLA _SFR_MEM8(0x0806) -#define TCC0_INTCTRLB _SFR_MEM8(0x0807) -#define TCC0_CTRLFCLR _SFR_MEM8(0x0808) -#define TCC0_CTRLFSET _SFR_MEM8(0x0809) -#define TCC0_CTRLGCLR _SFR_MEM8(0x080A) -#define TCC0_CTRLGSET _SFR_MEM8(0x080B) -#define TCC0_INTFLAGS _SFR_MEM8(0x080C) -#define TCC0_TEMP _SFR_MEM8(0x080F) -#define TCC0_CNT _SFR_MEM16(0x0820) -#define TCC0_PER _SFR_MEM16(0x0826) -#define TCC0_CCA _SFR_MEM16(0x0828) -#define TCC0_CCB _SFR_MEM16(0x082A) -#define TCC0_CCC _SFR_MEM16(0x082C) -#define TCC0_CCD _SFR_MEM16(0x082E) -#define TCC0_PERBUF _SFR_MEM16(0x0836) -#define TCC0_CCABUF _SFR_MEM16(0x0838) -#define TCC0_CCBBUF _SFR_MEM16(0x083A) -#define TCC0_CCCBUF _SFR_MEM16(0x083C) -#define TCC0_CCDBUF _SFR_MEM16(0x083E) - -/* TCC1 - Timer/Counter C1 */ -#define TCC1_CTRLA _SFR_MEM8(0x0840) -#define TCC1_CTRLB _SFR_MEM8(0x0841) -#define TCC1_CTRLC _SFR_MEM8(0x0842) -#define TCC1_CTRLD _SFR_MEM8(0x0843) -#define TCC1_CTRLE _SFR_MEM8(0x0844) -#define TCC1_INTCTRLA _SFR_MEM8(0x0846) -#define TCC1_INTCTRLB _SFR_MEM8(0x0847) -#define TCC1_CTRLFCLR _SFR_MEM8(0x0848) -#define TCC1_CTRLFSET _SFR_MEM8(0x0849) -#define TCC1_CTRLGCLR _SFR_MEM8(0x084A) -#define TCC1_CTRLGSET _SFR_MEM8(0x084B) -#define TCC1_INTFLAGS _SFR_MEM8(0x084C) -#define TCC1_TEMP _SFR_MEM8(0x084F) -#define TCC1_CNT _SFR_MEM16(0x0860) -#define TCC1_PER _SFR_MEM16(0x0866) -#define TCC1_CCA _SFR_MEM16(0x0868) -#define TCC1_CCB _SFR_MEM16(0x086A) -#define TCC1_PERBUF _SFR_MEM16(0x0876) -#define TCC1_CCABUF _SFR_MEM16(0x0878) -#define TCC1_CCBBUF _SFR_MEM16(0x087A) - -/* AWEXC - Advanced Waveform Extension C */ -#define AWEXC_CTRL _SFR_MEM8(0x0880) -#define AWEXC_FDEMASK _SFR_MEM8(0x0882) -#define AWEXC_FDCTRL _SFR_MEM8(0x0883) -#define AWEXC_STATUS _SFR_MEM8(0x0884) -#define AWEXC_DTBOTH _SFR_MEM8(0x0886) -#define AWEXC_DTBOTHBUF _SFR_MEM8(0x0887) -#define AWEXC_DTLS _SFR_MEM8(0x0888) -#define AWEXC_DTHS _SFR_MEM8(0x0889) -#define AWEXC_DTLSBUF _SFR_MEM8(0x088A) -#define AWEXC_DTHSBUF _SFR_MEM8(0x088B) -#define AWEXC_OUTOVEN _SFR_MEM8(0x088C) - -/* HIRESC - High-Resolution Extension C */ -#define HIRESC_CTRLA _SFR_MEM8(0x0890) - -/* USARTC0 - Universal Asynchronous Receiver-Transmitter C0 */ -#define USARTC0_DATA _SFR_MEM8(0x08A0) -#define USARTC0_STATUS _SFR_MEM8(0x08A1) -#define USARTC0_CTRLA _SFR_MEM8(0x08A3) -#define USARTC0_CTRLB _SFR_MEM8(0x08A4) -#define USARTC0_CTRLC _SFR_MEM8(0x08A5) -#define USARTC0_BAUDCTRLA _SFR_MEM8(0x08A6) -#define USARTC0_BAUDCTRLB _SFR_MEM8(0x08A7) - -/* SPIC - Serial Peripheral Interface C */ -#define SPIC_CTRL _SFR_MEM8(0x08C0) -#define SPIC_INTCTRL _SFR_MEM8(0x08C1) -#define SPIC_STATUS _SFR_MEM8(0x08C2) -#define SPIC_DATA _SFR_MEM8(0x08C3) - -/* IRCOM - IR Communication Module */ -#define IRCOM_TXPLCTRL _SFR_MEM8(0x08F8) -#define IRCOM_RXPLCTRL _SFR_MEM8(0x08F9) -#define IRCOM_CTRL _SFR_MEM8(0x08FA) - -/* TCD0 - Timer/Counter D0 */ -#define TCD0_CTRLA _SFR_MEM8(0x0900) -#define TCD0_CTRLB _SFR_MEM8(0x0901) -#define TCD0_CTRLC _SFR_MEM8(0x0902) -#define TCD0_CTRLD _SFR_MEM8(0x0903) -#define TCD0_CTRLE _SFR_MEM8(0x0904) -#define TCD0_INTCTRLA _SFR_MEM8(0x0906) -#define TCD0_INTCTRLB _SFR_MEM8(0x0907) -#define TCD0_CTRLFCLR _SFR_MEM8(0x0908) -#define TCD0_CTRLFSET _SFR_MEM8(0x0909) -#define TCD0_CTRLGCLR _SFR_MEM8(0x090A) -#define TCD0_CTRLGSET _SFR_MEM8(0x090B) -#define TCD0_INTFLAGS _SFR_MEM8(0x090C) -#define TCD0_TEMP _SFR_MEM8(0x090F) -#define TCD0_CNT _SFR_MEM16(0x0920) -#define TCD0_PER _SFR_MEM16(0x0926) -#define TCD0_CCA _SFR_MEM16(0x0928) -#define TCD0_CCB _SFR_MEM16(0x092A) -#define TCD0_CCC _SFR_MEM16(0x092C) -#define TCD0_CCD _SFR_MEM16(0x092E) -#define TCD0_PERBUF _SFR_MEM16(0x0936) -#define TCD0_CCABUF _SFR_MEM16(0x0938) -#define TCD0_CCBBUF _SFR_MEM16(0x093A) -#define TCD0_CCCBUF _SFR_MEM16(0x093C) -#define TCD0_CCDBUF _SFR_MEM16(0x093E) - -/* USARTD0 - Universal Asynchronous Receiver-Transmitter D0 */ -#define USARTD0_DATA _SFR_MEM8(0x09A0) -#define USARTD0_STATUS _SFR_MEM8(0x09A1) -#define USARTD0_CTRLA _SFR_MEM8(0x09A3) -#define USARTD0_CTRLB _SFR_MEM8(0x09A4) -#define USARTD0_CTRLC _SFR_MEM8(0x09A5) -#define USARTD0_BAUDCTRLA _SFR_MEM8(0x09A6) -#define USARTD0_BAUDCTRLB _SFR_MEM8(0x09A7) - -/* SPID - Serial Peripheral Interface D */ -#define SPID_CTRL _SFR_MEM8(0x09C0) -#define SPID_INTCTRL _SFR_MEM8(0x09C1) -#define SPID_STATUS _SFR_MEM8(0x09C2) -#define SPID_DATA _SFR_MEM8(0x09C3) - -/* TCE0 - Timer/Counter E0 */ -#define TCE0_CTRLA _SFR_MEM8(0x0A00) -#define TCE0_CTRLB _SFR_MEM8(0x0A01) -#define TCE0_CTRLC _SFR_MEM8(0x0A02) -#define TCE0_CTRLD _SFR_MEM8(0x0A03) -#define TCE0_CTRLE _SFR_MEM8(0x0A04) -#define TCE0_INTCTRLA _SFR_MEM8(0x0A06) -#define TCE0_INTCTRLB _SFR_MEM8(0x0A07) -#define TCE0_CTRLFCLR _SFR_MEM8(0x0A08) -#define TCE0_CTRLFSET _SFR_MEM8(0x0A09) -#define TCE0_CTRLGCLR _SFR_MEM8(0x0A0A) -#define TCE0_CTRLGSET _SFR_MEM8(0x0A0B) -#define TCE0_INTFLAGS _SFR_MEM8(0x0A0C) -#define TCE0_TEMP _SFR_MEM8(0x0A0F) -#define TCE0_CNT _SFR_MEM16(0x0A20) -#define TCE0_PER _SFR_MEM16(0x0A26) -#define TCE0_CCA _SFR_MEM16(0x0A28) -#define TCE0_CCB _SFR_MEM16(0x0A2A) -#define TCE0_CCC _SFR_MEM16(0x0A2C) -#define TCE0_CCD _SFR_MEM16(0x0A2E) -#define TCE0_PERBUF _SFR_MEM16(0x0A36) -#define TCE0_CCABUF _SFR_MEM16(0x0A38) -#define TCE0_CCBBUF _SFR_MEM16(0x0A3A) -#define TCE0_CCCBUF _SFR_MEM16(0x0A3C) -#define TCE0_CCDBUF _SFR_MEM16(0x0A3E) - -/* AWEXE - Advanced Waveform Extension E */ -#define AWEXE_CTRL _SFR_MEM8(0x0A80) -#define AWEXE_FDEMASK _SFR_MEM8(0x0A82) -#define AWEXE_FDCTRL _SFR_MEM8(0x0A83) -#define AWEXE_STATUS _SFR_MEM8(0x0A84) -#define AWEXE_DTBOTH _SFR_MEM8(0x0A86) -#define AWEXE_DTBOTHBUF _SFR_MEM8(0x0A87) -#define AWEXE_DTLS _SFR_MEM8(0x0A88) -#define AWEXE_DTHS _SFR_MEM8(0x0A89) -#define AWEXE_DTLSBUF _SFR_MEM8(0x0A8A) -#define AWEXE_DTHSBUF _SFR_MEM8(0x0A8B) -#define AWEXE_OUTOVEN _SFR_MEM8(0x0A8C) - -/* USARTE0 - Universal Asynchronous Receiver-Transmitter E0 */ -#define USARTE0_DATA _SFR_MEM8(0x0AA0) -#define USARTE0_STATUS _SFR_MEM8(0x0AA1) -#define USARTE0_CTRLA _SFR_MEM8(0x0AA3) -#define USARTE0_CTRLB _SFR_MEM8(0x0AA4) -#define USARTE0_CTRLC _SFR_MEM8(0x0AA5) -#define USARTE0_BAUDCTRLA _SFR_MEM8(0x0AA6) -#define USARTE0_BAUDCTRLB _SFR_MEM8(0x0AA7) - -/* SPIE - Serial Peripheral Interface E */ -#define SPIE_CTRL _SFR_MEM8(0x0AC0) -#define SPIE_INTCTRL _SFR_MEM8(0x0AC1) -#define SPIE_STATUS _SFR_MEM8(0x0AC2) -#define SPIE_DATA _SFR_MEM8(0x0AC3) - -/* TCF0 - Timer/Counter F0 */ -#define TCF0_CTRLA _SFR_MEM8(0x0B00) -#define TCF0_CTRLB _SFR_MEM8(0x0B01) -#define TCF0_CTRLC _SFR_MEM8(0x0B02) -#define TCF0_CTRLD _SFR_MEM8(0x0B03) -#define TCF0_CTRLE _SFR_MEM8(0x0B04) -#define TCF0_INTCTRLA _SFR_MEM8(0x0B06) -#define TCF0_INTCTRLB _SFR_MEM8(0x0B07) -#define TCF0_CTRLFCLR _SFR_MEM8(0x0B08) -#define TCF0_CTRLFSET _SFR_MEM8(0x0B09) -#define TCF0_CTRLGCLR _SFR_MEM8(0x0B0A) -#define TCF0_CTRLGSET _SFR_MEM8(0x0B0B) -#define TCF0_INTFLAGS _SFR_MEM8(0x0B0C) -#define TCF0_TEMP _SFR_MEM8(0x0B0F) -#define TCF0_CNT _SFR_MEM16(0x0B20) -#define TCF0_PER _SFR_MEM16(0x0B26) -#define TCF0_CCA _SFR_MEM16(0x0B28) -#define TCF0_CCB _SFR_MEM16(0x0B2A) -#define TCF0_CCC _SFR_MEM16(0x0B2C) -#define TCF0_CCD _SFR_MEM16(0x0B2E) -#define TCF0_PERBUF _SFR_MEM16(0x0B36) -#define TCF0_CCABUF _SFR_MEM16(0x0B38) -#define TCF0_CCBBUF _SFR_MEM16(0x0B3A) -#define TCF0_CCCBUF _SFR_MEM16(0x0B3C) -#define TCF0_CCDBUF _SFR_MEM16(0x0B3E) - - - -/*================== Bitfield Definitions ================== */ - -/* XOCD - On-Chip Debug System */ -/* OCD.OCDR1 bit masks and bit positions */ -#define OCD_OCDRD_bm 0x01 /* OCDR Dirty bit mask. */ -#define OCD_OCDRD_bp 0 /* OCDR Dirty bit position. */ - - -/* CPU - CPU */ -/* CPU.CCP bit masks and bit positions */ -#define CPU_CCP_gm 0xFF /* CCP signature group mask. */ -#define CPU_CCP_gp 0 /* CCP signature group position. */ -#define CPU_CCP0_bm (1<<0) /* CCP signature bit 0 mask. */ -#define CPU_CCP0_bp 0 /* CCP signature bit 0 position. */ -#define CPU_CCP1_bm (1<<1) /* CCP signature bit 1 mask. */ -#define CPU_CCP1_bp 1 /* CCP signature bit 1 position. */ -#define CPU_CCP2_bm (1<<2) /* CCP signature bit 2 mask. */ -#define CPU_CCP2_bp 2 /* CCP signature bit 2 position. */ -#define CPU_CCP3_bm (1<<3) /* CCP signature bit 3 mask. */ -#define CPU_CCP3_bp 3 /* CCP signature bit 3 position. */ -#define CPU_CCP4_bm (1<<4) /* CCP signature bit 4 mask. */ -#define CPU_CCP4_bp 4 /* CCP signature bit 4 position. */ -#define CPU_CCP5_bm (1<<5) /* CCP signature bit 5 mask. */ -#define CPU_CCP5_bp 5 /* CCP signature bit 5 position. */ -#define CPU_CCP6_bm (1<<6) /* CCP signature bit 6 mask. */ -#define CPU_CCP6_bp 6 /* CCP signature bit 6 position. */ -#define CPU_CCP7_bm (1<<7) /* CCP signature bit 7 mask. */ -#define CPU_CCP7_bp 7 /* CCP signature bit 7 position. */ - - -/* CPU.SREG bit masks and bit positions */ -#define CPU_I_bm 0x80 /* Global Interrupt Enable Flag bit mask. */ -#define CPU_I_bp 7 /* Global Interrupt Enable Flag bit position. */ - -#define CPU_T_bm 0x40 /* Transfer Bit bit mask. */ -#define CPU_T_bp 6 /* Transfer Bit bit position. */ - -#define CPU_H_bm 0x20 /* Half Carry Flag bit mask. */ -#define CPU_H_bp 5 /* Half Carry Flag bit position. */ - -#define CPU_S_bm 0x10 /* N Exclusive Or V Flag bit mask. */ -#define CPU_S_bp 4 /* N Exclusive Or V Flag bit position. */ - -#define CPU_V_bm 0x08 /* Two's Complement Overflow Flag bit mask. */ -#define CPU_V_bp 3 /* Two's Complement Overflow Flag bit position. */ - -#define CPU_N_bm 0x04 /* Negative Flag bit mask. */ -#define CPU_N_bp 2 /* Negative Flag bit position. */ - -#define CPU_Z_bm 0x02 /* Zero Flag bit mask. */ -#define CPU_Z_bp 1 /* Zero Flag bit position. */ - -#define CPU_C_bm 0x01 /* Carry Flag bit mask. */ -#define CPU_C_bp 0 /* Carry Flag bit position. */ - - -/* CLK - Clock System */ -/* CLK.CTRL bit masks and bit positions */ -#define CLK_SCLKSEL_gm 0x07 /* System Clock Selection group mask. */ -#define CLK_SCLKSEL_gp 0 /* System Clock Selection group position. */ -#define CLK_SCLKSEL0_bm (1<<0) /* System Clock Selection bit 0 mask. */ -#define CLK_SCLKSEL0_bp 0 /* System Clock Selection bit 0 position. */ -#define CLK_SCLKSEL1_bm (1<<1) /* System Clock Selection bit 1 mask. */ -#define CLK_SCLKSEL1_bp 1 /* System Clock Selection bit 1 position. */ -#define CLK_SCLKSEL2_bm (1<<2) /* System Clock Selection bit 2 mask. */ -#define CLK_SCLKSEL2_bp 2 /* System Clock Selection bit 2 position. */ - - -/* CLK.PSCTRL bit masks and bit positions */ -#define CLK_PSADIV_gm 0x7C /* Prescaler A Division Factor group mask. */ -#define CLK_PSADIV_gp 2 /* Prescaler A Division Factor group position. */ -#define CLK_PSADIV0_bm (1<<2) /* Prescaler A Division Factor bit 0 mask. */ -#define CLK_PSADIV0_bp 2 /* Prescaler A Division Factor bit 0 position. */ -#define CLK_PSADIV1_bm (1<<3) /* Prescaler A Division Factor bit 1 mask. */ -#define CLK_PSADIV1_bp 3 /* Prescaler A Division Factor bit 1 position. */ -#define CLK_PSADIV2_bm (1<<4) /* Prescaler A Division Factor bit 2 mask. */ -#define CLK_PSADIV2_bp 4 /* Prescaler A Division Factor bit 2 position. */ -#define CLK_PSADIV3_bm (1<<5) /* Prescaler A Division Factor bit 3 mask. */ -#define CLK_PSADIV3_bp 5 /* Prescaler A Division Factor bit 3 position. */ -#define CLK_PSADIV4_bm (1<<6) /* Prescaler A Division Factor bit 4 mask. */ -#define CLK_PSADIV4_bp 6 /* Prescaler A Division Factor bit 4 position. */ - -#define CLK_PSBCDIV_gm 0x03 /* Prescaler B and C Division factor group mask. */ -#define CLK_PSBCDIV_gp 0 /* Prescaler B and C Division factor group position. */ -#define CLK_PSBCDIV0_bm (1<<0) /* Prescaler B and C Division factor bit 0 mask. */ -#define CLK_PSBCDIV0_bp 0 /* Prescaler B and C Division factor bit 0 position. */ -#define CLK_PSBCDIV1_bm (1<<1) /* Prescaler B and C Division factor bit 1 mask. */ -#define CLK_PSBCDIV1_bp 1 /* Prescaler B and C Division factor bit 1 position. */ - - -/* CLK.LOCK bit masks and bit positions */ -#define CLK_LOCK_bm 0x01 /* Clock System Lock bit mask. */ -#define CLK_LOCK_bp 0 /* Clock System Lock bit position. */ - - -/* CLK.RTCCTRL bit masks and bit positions */ -#define CLK_RTCSRC_gm 0x0E /* Clock Source group mask. */ -#define CLK_RTCSRC_gp 1 /* Clock Source group position. */ -#define CLK_RTCSRC0_bm (1<<1) /* Clock Source bit 0 mask. */ -#define CLK_RTCSRC0_bp 1 /* Clock Source bit 0 position. */ -#define CLK_RTCSRC1_bm (1<<2) /* Clock Source bit 1 mask. */ -#define CLK_RTCSRC1_bp 2 /* Clock Source bit 1 position. */ -#define CLK_RTCSRC2_bm (1<<3) /* Clock Source bit 2 mask. */ -#define CLK_RTCSRC2_bp 3 /* Clock Source bit 2 position. */ - -#define CLK_RTCEN_bm 0x01 /* RTC Clock Source Enable bit mask. */ -#define CLK_RTCEN_bp 0 /* RTC Clock Source Enable bit position. */ - - -/* PR.PRGEN bit masks and bit positions */ -#define PR_RTC_bm 0x04 /* Real-time Counter bit mask. */ -#define PR_RTC_bp 2 /* Real-time Counter bit position. */ - -#define PR_EVSYS_bm 0x02 /* Event System bit mask. */ -#define PR_EVSYS_bp 1 /* Event System bit position. */ - -/* PR.PRPA bit masks and bit positions */ -#define PR_ADC_bm 0x02 /* Port A ADC bit mask. */ -#define PR_ADC_bp 1 /* Port A ADC bit position. */ - -#define PR_AC_bm 0x01 /* Port A Analog Comparator bit mask. */ -#define PR_AC_bp 0 /* Port A Analog Comparator bit position. */ - -/* PR.PRPC bit masks and bit positions */ -#define PR_TWI_bm 0x40 /* Port C Two-wire Interface bit mask. */ -#define PR_TWI_bp 6 /* Port C Two-wire Interface bit position. */ - -#define PR_USART0_bm 0x10 /* Port C USART0 bit mask. */ -#define PR_USART0_bp 4 /* Port C USART0 bit position. */ - -#define PR_SPI_bm 0x08 /* Port C SPI bit mask. */ -#define PR_SPI_bp 3 /* Port C SPI bit position. */ - -#define PR_HIRES_bm 0x04 /* Port C HIRES bit mask. */ -#define PR_HIRES_bp 2 /* Port C HIRES bit position. */ - -#define PR_TC1_bm 0x02 /* Port C Timer/Counter1 bit mask. */ -#define PR_TC1_bp 1 /* Port C Timer/Counter1 bit position. */ - -#define PR_TC0_bm 0x01 /* Port C Timer/Counter0 bit mask. */ -#define PR_TC0_bp 0 /* Port C Timer/Counter0 bit position. */ - -/* PR.PRPD bit masks and bit positions */ -/* PR_USART0_bm Predefined. */ -/* PR_USART0_bp Predefined. */ - -/* PR_SPI_bm Predefined. */ -/* PR_SPI_bp Predefined. */ - -/* PR_TC0_bm Predefined. */ -/* PR_TC0_bp Predefined. */ - -/* PR.PRPE bit masks and bit positions */ -/* PR_TWI_bm Predefined. */ -/* PR_TWI_bp Predefined. */ - -/* PR_USART0_bm Predefined. */ -/* PR_USART0_bp Predefined. */ - -/* PR_TC0_bm Predefined. */ -/* PR_TC0_bp Predefined. */ - -/* PR.PRPF bit masks and bit positions */ -/* PR_USART0_bm Predefined. */ -/* PR_USART0_bp Predefined. */ - -/* PR_TC0_bm Predefined. */ -/* PR_TC0_bp Predefined. */ - -/* SLEEP - Sleep Controller */ -/* SLEEP.CTRL bit masks and bit positions */ -#define SLEEP_SMODE_gm 0x0E /* Sleep Mode group mask. */ -#define SLEEP_SMODE_gp 1 /* Sleep Mode group position. */ -#define SLEEP_SMODE0_bm (1<<1) /* Sleep Mode bit 0 mask. */ -#define SLEEP_SMODE0_bp 1 /* Sleep Mode bit 0 position. */ -#define SLEEP_SMODE1_bm (1<<2) /* Sleep Mode bit 1 mask. */ -#define SLEEP_SMODE1_bp 2 /* Sleep Mode bit 1 position. */ -#define SLEEP_SMODE2_bm (1<<3) /* Sleep Mode bit 2 mask. */ -#define SLEEP_SMODE2_bp 3 /* Sleep Mode bit 2 position. */ - -#define SLEEP_SEN_bm 0x01 /* Sleep Enable bit mask. */ -#define SLEEP_SEN_bp 0 /* Sleep Enable bit position. */ - - -/* OSC - Oscillator */ -/* OSC.CTRL bit masks and bit positions */ -#define OSC_PLLEN_bm 0x10 /* PLL Enable bit mask. */ -#define OSC_PLLEN_bp 4 /* PLL Enable bit position. */ - -#define OSC_XOSCEN_bm 0x08 /* External Oscillator Enable bit mask. */ -#define OSC_XOSCEN_bp 3 /* External Oscillator Enable bit position. */ - -#define OSC_RC32KEN_bm 0x04 /* Internal 32kHz RC Oscillator Enable bit mask. */ -#define OSC_RC32KEN_bp 2 /* Internal 32kHz RC Oscillator Enable bit position. */ - -#define OSC_RC32MEN_bm 0x02 /* Internal 32MHz RC Oscillator Enable bit mask. */ -#define OSC_RC32MEN_bp 1 /* Internal 32MHz RC Oscillator Enable bit position. */ - -#define OSC_RC2MEN_bm 0x01 /* Internal 2MHz RC Oscillator Enable bit mask. */ -#define OSC_RC2MEN_bp 0 /* Internal 2MHz RC Oscillator Enable bit position. */ - - -/* OSC.STATUS bit masks and bit positions */ -#define OSC_PLLRDY_bm 0x10 /* PLL Ready bit mask. */ -#define OSC_PLLRDY_bp 4 /* PLL Ready bit position. */ - -#define OSC_XOSCRDY_bm 0x08 /* External Oscillator Ready bit mask. */ -#define OSC_XOSCRDY_bp 3 /* External Oscillator Ready bit position. */ - -#define OSC_RC32KRDY_bm 0x04 /* Internal 32kHz RC Oscillator Ready bit mask. */ -#define OSC_RC32KRDY_bp 2 /* Internal 32kHz RC Oscillator Ready bit position. */ - -#define OSC_RC32MRDY_bm 0x02 /* Internal 32MHz RC Oscillator Ready bit mask. */ -#define OSC_RC32MRDY_bp 1 /* Internal 32MHz RC Oscillator Ready bit position. */ - -#define OSC_RC2MRDY_bm 0x01 /* Internal 2MHz RC Oscillator Ready bit mask. */ -#define OSC_RC2MRDY_bp 0 /* Internal 2MHz RC Oscillator Ready bit position. */ - - -/* OSC.XOSCCTRL bit masks and bit positions */ -#define OSC_FRQRANGE_gm 0xC0 /* Frequency Range group mask. */ -#define OSC_FRQRANGE_gp 6 /* Frequency Range group position. */ -#define OSC_FRQRANGE0_bm (1<<6) /* Frequency Range bit 0 mask. */ -#define OSC_FRQRANGE0_bp 6 /* Frequency Range bit 0 position. */ -#define OSC_FRQRANGE1_bm (1<<7) /* Frequency Range bit 1 mask. */ -#define OSC_FRQRANGE1_bp 7 /* Frequency Range bit 1 position. */ - -#define OSC_X32KLPM_bm 0x20 /* 32kHz XTAL OSC Low-power Mode bit mask. */ -#define OSC_X32KLPM_bp 5 /* 32kHz XTAL OSC Low-power Mode bit position. */ - -#define OSC_XOSCSEL_gm 0x0F /* External Oscillator Selection and Startup Time group mask. */ -#define OSC_XOSCSEL_gp 0 /* External Oscillator Selection and Startup Time group position. */ -#define OSC_XOSCSEL0_bm (1<<0) /* External Oscillator Selection and Startup Time bit 0 mask. */ -#define OSC_XOSCSEL0_bp 0 /* External Oscillator Selection and Startup Time bit 0 position. */ -#define OSC_XOSCSEL1_bm (1<<1) /* External Oscillator Selection and Startup Time bit 1 mask. */ -#define OSC_XOSCSEL1_bp 1 /* External Oscillator Selection and Startup Time bit 1 position. */ -#define OSC_XOSCSEL2_bm (1<<2) /* External Oscillator Selection and Startup Time bit 2 mask. */ -#define OSC_XOSCSEL2_bp 2 /* External Oscillator Selection and Startup Time bit 2 position. */ -#define OSC_XOSCSEL3_bm (1<<3) /* External Oscillator Selection and Startup Time bit 3 mask. */ -#define OSC_XOSCSEL3_bp 3 /* External Oscillator Selection and Startup Time bit 3 position. */ - - -/* OSC.XOSCFAIL bit masks and bit positions */ -#define OSC_XOSCFDIF_bm 0x02 /* Failure Detection Interrupt Flag bit mask. */ -#define OSC_XOSCFDIF_bp 1 /* Failure Detection Interrupt Flag bit position. */ - -#define OSC_XOSCFDEN_bm 0x01 /* Failure Detection Enable bit mask. */ -#define OSC_XOSCFDEN_bp 0 /* Failure Detection Enable bit position. */ - - -/* OSC.PLLCTRL bit masks and bit positions */ -#define OSC_PLLSRC_gm 0xC0 /* Clock Source group mask. */ -#define OSC_PLLSRC_gp 6 /* Clock Source group position. */ -#define OSC_PLLSRC0_bm (1<<6) /* Clock Source bit 0 mask. */ -#define OSC_PLLSRC0_bp 6 /* Clock Source bit 0 position. */ -#define OSC_PLLSRC1_bm (1<<7) /* Clock Source bit 1 mask. */ -#define OSC_PLLSRC1_bp 7 /* Clock Source bit 1 position. */ - -#define OSC_PLLFAC_gm 0x1F /* Multiplication Factor group mask. */ -#define OSC_PLLFAC_gp 0 /* Multiplication Factor group position. */ -#define OSC_PLLFAC0_bm (1<<0) /* Multiplication Factor bit 0 mask. */ -#define OSC_PLLFAC0_bp 0 /* Multiplication Factor bit 0 position. */ -#define OSC_PLLFAC1_bm (1<<1) /* Multiplication Factor bit 1 mask. */ -#define OSC_PLLFAC1_bp 1 /* Multiplication Factor bit 1 position. */ -#define OSC_PLLFAC2_bm (1<<2) /* Multiplication Factor bit 2 mask. */ -#define OSC_PLLFAC2_bp 2 /* Multiplication Factor bit 2 position. */ -#define OSC_PLLFAC3_bm (1<<3) /* Multiplication Factor bit 3 mask. */ -#define OSC_PLLFAC3_bp 3 /* Multiplication Factor bit 3 position. */ -#define OSC_PLLFAC4_bm (1<<4) /* Multiplication Factor bit 4 mask. */ -#define OSC_PLLFAC4_bp 4 /* Multiplication Factor bit 4 position. */ - - -/* OSC.DFLLCTRL bit masks and bit positions */ -#define OSC_RC32MCREF_bm 0x02 /* 32MHz Calibration Reference bit mask. */ -#define OSC_RC32MCREF_bp 1 /* 32MHz Calibration Reference bit position. */ - -#define OSC_RC2MCREF_bm 0x01 /* 2MHz Calibration Reference bit mask. */ -#define OSC_RC2MCREF_bp 0 /* 2MHz Calibration Reference bit position. */ - - -/* DFLL - DFLL */ -/* DFLL.CTRL bit masks and bit positions */ -#define DFLL_ENABLE_bm 0x01 /* DFLL Enable bit mask. */ -#define DFLL_ENABLE_bp 0 /* DFLL Enable bit position. */ - - -/* DFLL.CALA bit masks and bit positions */ -#define DFLL_CALL_gm 0x7F /* DFLL Calibration bits [6:0] group mask. */ -#define DFLL_CALL_gp 0 /* DFLL Calibration bits [6:0] group position. */ -#define DFLL_CALL0_bm (1<<0) /* DFLL Calibration bits [6:0] bit 0 mask. */ -#define DFLL_CALL0_bp 0 /* DFLL Calibration bits [6:0] bit 0 position. */ -#define DFLL_CALL1_bm (1<<1) /* DFLL Calibration bits [6:0] bit 1 mask. */ -#define DFLL_CALL1_bp 1 /* DFLL Calibration bits [6:0] bit 1 position. */ -#define DFLL_CALL2_bm (1<<2) /* DFLL Calibration bits [6:0] bit 2 mask. */ -#define DFLL_CALL2_bp 2 /* DFLL Calibration bits [6:0] bit 2 position. */ -#define DFLL_CALL3_bm (1<<3) /* DFLL Calibration bits [6:0] bit 3 mask. */ -#define DFLL_CALL3_bp 3 /* DFLL Calibration bits [6:0] bit 3 position. */ -#define DFLL_CALL4_bm (1<<4) /* DFLL Calibration bits [6:0] bit 4 mask. */ -#define DFLL_CALL4_bp 4 /* DFLL Calibration bits [6:0] bit 4 position. */ -#define DFLL_CALL5_bm (1<<5) /* DFLL Calibration bits [6:0] bit 5 mask. */ -#define DFLL_CALL5_bp 5 /* DFLL Calibration bits [6:0] bit 5 position. */ -#define DFLL_CALL6_bm (1<<6) /* DFLL Calibration bits [6:0] bit 6 mask. */ -#define DFLL_CALL6_bp 6 /* DFLL Calibration bits [6:0] bit 6 position. */ - - -/* DFLL.CALB bit masks and bit positions */ -#define DFLL_CALH_gm 0x3F /* DFLL Calibration bits [12:7] group mask. */ -#define DFLL_CALH_gp 0 /* DFLL Calibration bits [12:7] group position. */ -#define DFLL_CALH0_bm (1<<0) /* DFLL Calibration bits [12:7] bit 0 mask. */ -#define DFLL_CALH0_bp 0 /* DFLL Calibration bits [12:7] bit 0 position. */ -#define DFLL_CALH1_bm (1<<1) /* DFLL Calibration bits [12:7] bit 1 mask. */ -#define DFLL_CALH1_bp 1 /* DFLL Calibration bits [12:7] bit 1 position. */ -#define DFLL_CALH2_bm (1<<2) /* DFLL Calibration bits [12:7] bit 2 mask. */ -#define DFLL_CALH2_bp 2 /* DFLL Calibration bits [12:7] bit 2 position. */ -#define DFLL_CALH3_bm (1<<3) /* DFLL Calibration bits [12:7] bit 3 mask. */ -#define DFLL_CALH3_bp 3 /* DFLL Calibration bits [12:7] bit 3 position. */ -#define DFLL_CALH4_bm (1<<4) /* DFLL Calibration bits [12:7] bit 4 mask. */ -#define DFLL_CALH4_bp 4 /* DFLL Calibration bits [12:7] bit 4 position. */ -#define DFLL_CALH5_bm (1<<5) /* DFLL Calibration bits [12:7] bit 5 mask. */ -#define DFLL_CALH5_bp 5 /* DFLL Calibration bits [12:7] bit 5 position. */ - - -/* RST - Reset */ -/* RST.STATUS bit masks and bit positions */ -#define RST_SDRF_bm 0x40 /* Spike Detection Reset Flag bit mask. */ -#define RST_SDRF_bp 6 /* Spike Detection Reset Flag bit position. */ - -#define RST_SRF_bm 0x20 /* Software Reset Flag bit mask. */ -#define RST_SRF_bp 5 /* Software Reset Flag bit position. */ - -#define RST_PDIRF_bm 0x10 /* Programming and Debug Interface Interface Reset Flag bit mask. */ -#define RST_PDIRF_bp 4 /* Programming and Debug Interface Interface Reset Flag bit position. */ - -#define RST_WDRF_bm 0x08 /* Watchdog Reset Flag bit mask. */ -#define RST_WDRF_bp 3 /* Watchdog Reset Flag bit position. */ - -#define RST_BORF_bm 0x04 /* Brown-out Reset Flag bit mask. */ -#define RST_BORF_bp 2 /* Brown-out Reset Flag bit position. */ - -#define RST_EXTRF_bm 0x02 /* External Reset Flag bit mask. */ -#define RST_EXTRF_bp 1 /* External Reset Flag bit position. */ - -#define RST_PORF_bm 0x01 /* Power-on Reset Flag bit mask. */ -#define RST_PORF_bp 0 /* Power-on Reset Flag bit position. */ - - -/* RST.CTRL bit masks and bit positions */ -#define RST_SWRST_bm 0x01 /* Software Reset bit mask. */ -#define RST_SWRST_bp 0 /* Software Reset bit position. */ - - -/* WDT - Watch-Dog Timer */ -/* WDT.CTRL bit masks and bit positions */ -#define WDT_PER_gm 0x3C /* Period group mask. */ -#define WDT_PER_gp 2 /* Period group position. */ -#define WDT_PER0_bm (1<<2) /* Period bit 0 mask. */ -#define WDT_PER0_bp 2 /* Period bit 0 position. */ -#define WDT_PER1_bm (1<<3) /* Period bit 1 mask. */ -#define WDT_PER1_bp 3 /* Period bit 1 position. */ -#define WDT_PER2_bm (1<<4) /* Period bit 2 mask. */ -#define WDT_PER2_bp 4 /* Period bit 2 position. */ -#define WDT_PER3_bm (1<<5) /* Period bit 3 mask. */ -#define WDT_PER3_bp 5 /* Period bit 3 position. */ - -#define WDT_ENABLE_bm 0x02 /* Enable bit mask. */ -#define WDT_ENABLE_bp 1 /* Enable bit position. */ - -#define WDT_CEN_bm 0x01 /* Change Enable bit mask. */ -#define WDT_CEN_bp 0 /* Change Enable bit position. */ - - -/* WDT.WINCTRL bit masks and bit positions */ -#define WDT_WPER_gm 0x3C /* Windowed Mode Period group mask. */ -#define WDT_WPER_gp 2 /* Windowed Mode Period group position. */ -#define WDT_WPER0_bm (1<<2) /* Windowed Mode Period bit 0 mask. */ -#define WDT_WPER0_bp 2 /* Windowed Mode Period bit 0 position. */ -#define WDT_WPER1_bm (1<<3) /* Windowed Mode Period bit 1 mask. */ -#define WDT_WPER1_bp 3 /* Windowed Mode Period bit 1 position. */ -#define WDT_WPER2_bm (1<<4) /* Windowed Mode Period bit 2 mask. */ -#define WDT_WPER2_bp 4 /* Windowed Mode Period bit 2 position. */ -#define WDT_WPER3_bm (1<<5) /* Windowed Mode Period bit 3 mask. */ -#define WDT_WPER3_bp 5 /* Windowed Mode Period bit 3 position. */ - -#define WDT_WEN_bm 0x02 /* Windowed Mode Enable bit mask. */ -#define WDT_WEN_bp 1 /* Windowed Mode Enable bit position. */ - -#define WDT_WCEN_bm 0x01 /* Windowed Mode Change Enable bit mask. */ -#define WDT_WCEN_bp 0 /* Windowed Mode Change Enable bit position. */ - - -/* WDT.STATUS bit masks and bit positions */ -#define WDT_SYNCBUSY_bm 0x01 /* Syncronization busy bit mask. */ -#define WDT_SYNCBUSY_bp 0 /* Syncronization busy bit position. */ - - -/* MCU - MCU Control */ -/* MCU.MCUCR bit masks and bit positions */ -#define MCU_JTAGD_bm 0x01 /* JTAG Disable bit mask. */ -#define MCU_JTAGD_bp 0 /* JTAG Disable bit position. */ - - -/* MCU.EVSYSLOCK bit masks and bit positions */ -#define MCU_EVSYS1LOCK_bm 0x10 /* Event Channel 4-7 Lock bit mask. */ -#define MCU_EVSYS1LOCK_bp 4 /* Event Channel 4-7 Lock bit position. */ - -#define MCU_EVSYS0LOCK_bm 0x01 /* Event Channel 0-3 Lock bit mask. */ -#define MCU_EVSYS0LOCK_bp 0 /* Event Channel 0-3 Lock bit position. */ - - -/* MCU.AWEXLOCK bit masks and bit positions */ -#define MCU_AWEXELOCK_bm 0x04 /* AWeX on T/C E0 Lock bit mask. */ -#define MCU_AWEXELOCK_bp 2 /* AWeX on T/C E0 Lock bit position. */ - -#define MCU_AWEXCLOCK_bm 0x01 /* AWeX on T/C C0 Lock bit mask. */ -#define MCU_AWEXCLOCK_bp 0 /* AWeX on T/C C0 Lock bit position. */ - - -/* PMIC - Programmable Multi-level Interrupt Controller */ -/* PMIC.STATUS bit masks and bit positions */ -#define PMIC_NMIEX_bm 0x80 /* Non-maskable Interrupt Executing bit mask. */ -#define PMIC_NMIEX_bp 7 /* Non-maskable Interrupt Executing bit position. */ - -#define PMIC_HILVLEX_bm 0x04 /* High Level Interrupt Executing bit mask. */ -#define PMIC_HILVLEX_bp 2 /* High Level Interrupt Executing bit position. */ - -#define PMIC_MEDLVLEX_bm 0x02 /* Medium Level Interrupt Executing bit mask. */ -#define PMIC_MEDLVLEX_bp 1 /* Medium Level Interrupt Executing bit position. */ - -#define PMIC_LOLVLEX_bm 0x01 /* Low Level Interrupt Executing bit mask. */ -#define PMIC_LOLVLEX_bp 0 /* Low Level Interrupt Executing bit position. */ - - -/* PMIC.CTRL bit masks and bit positions */ -#define PMIC_RREN_bm 0x80 /* Round-Robin Priority Enable bit mask. */ -#define PMIC_RREN_bp 7 /* Round-Robin Priority Enable bit position. */ - -#define PMIC_IVSEL_bm 0x40 /* Interrupt Vector Select bit mask. */ -#define PMIC_IVSEL_bp 6 /* Interrupt Vector Select bit position. */ - -#define PMIC_HILVLEN_bm 0x04 /* High Level Enable bit mask. */ -#define PMIC_HILVLEN_bp 2 /* High Level Enable bit position. */ - -#define PMIC_MEDLVLEN_bm 0x02 /* Medium Level Enable bit mask. */ -#define PMIC_MEDLVLEN_bp 1 /* Medium Level Enable bit position. */ - -#define PMIC_LOLVLEN_bm 0x01 /* Low Level Enable bit mask. */ -#define PMIC_LOLVLEN_bp 0 /* Low Level Enable bit position. */ - - -/* CRC - Cyclic Redundancy Checker */ -/* CRC.CTRL bit masks and bit positions */ -#define CRC_RESET_gm 0xC0 /* Reset group mask. */ -#define CRC_RESET_gp 6 /* Reset group position. */ -#define CRC_RESET0_bm (1<<6) /* Reset bit 0 mask. */ -#define CRC_RESET0_bp 6 /* Reset bit 0 position. */ -#define CRC_RESET1_bm (1<<7) /* Reset bit 1 mask. */ -#define CRC_RESET1_bp 7 /* Reset bit 1 position. */ - -#define CRC_CRC32_bm 0x20 /* CRC Mode bit mask. */ -#define CRC_CRC32_bp 5 /* CRC Mode bit position. */ - -#define CRC_SOURCE_gm 0x0F /* Input Source group mask. */ -#define CRC_SOURCE_gp 0 /* Input Source group position. */ -#define CRC_SOURCE0_bm (1<<0) /* Input Source bit 0 mask. */ -#define CRC_SOURCE0_bp 0 /* Input Source bit 0 position. */ -#define CRC_SOURCE1_bm (1<<1) /* Input Source bit 1 mask. */ -#define CRC_SOURCE1_bp 1 /* Input Source bit 1 position. */ -#define CRC_SOURCE2_bm (1<<2) /* Input Source bit 2 mask. */ -#define CRC_SOURCE2_bp 2 /* Input Source bit 2 position. */ -#define CRC_SOURCE3_bm (1<<3) /* Input Source bit 3 mask. */ -#define CRC_SOURCE3_bp 3 /* Input Source bit 3 position. */ - -/* CRC.STATUS bit masks and bit positions */ -#define CRC_ZERO_bm 0x02 /* Zero detection bit mask. */ -#define CRC_ZERO_bp 1 /* Zero detection bit position. */ - -#define CRC_BUSY_bm 0x01 /* Busy bit mask. */ -#define CRC_BUSY_bp 0 /* Busy bit position. */ - - -/* EVSYS - Event System */ -/* EVSYS.CH0MUX bit masks and bit positions */ -#define EVSYS_CHMUX_gm 0xFF /* Event Channel 0 Multiplexer group mask. */ -#define EVSYS_CHMUX_gp 0 /* Event Channel 0 Multiplexer group position. */ -#define EVSYS_CHMUX0_bm (1<<0) /* Event Channel 0 Multiplexer bit 0 mask. */ -#define EVSYS_CHMUX0_bp 0 /* Event Channel 0 Multiplexer bit 0 position. */ -#define EVSYS_CHMUX1_bm (1<<1) /* Event Channel 0 Multiplexer bit 1 mask. */ -#define EVSYS_CHMUX1_bp 1 /* Event Channel 0 Multiplexer bit 1 position. */ -#define EVSYS_CHMUX2_bm (1<<2) /* Event Channel 0 Multiplexer bit 2 mask. */ -#define EVSYS_CHMUX2_bp 2 /* Event Channel 0 Multiplexer bit 2 position. */ -#define EVSYS_CHMUX3_bm (1<<3) /* Event Channel 0 Multiplexer bit 3 mask. */ -#define EVSYS_CHMUX3_bp 3 /* Event Channel 0 Multiplexer bit 3 position. */ -#define EVSYS_CHMUX4_bm (1<<4) /* Event Channel 0 Multiplexer bit 4 mask. */ -#define EVSYS_CHMUX4_bp 4 /* Event Channel 0 Multiplexer bit 4 position. */ -#define EVSYS_CHMUX5_bm (1<<5) /* Event Channel 0 Multiplexer bit 5 mask. */ -#define EVSYS_CHMUX5_bp 5 /* Event Channel 0 Multiplexer bit 5 position. */ -#define EVSYS_CHMUX6_bm (1<<6) /* Event Channel 0 Multiplexer bit 6 mask. */ -#define EVSYS_CHMUX6_bp 6 /* Event Channel 0 Multiplexer bit 6 position. */ -#define EVSYS_CHMUX7_bm (1<<7) /* Event Channel 0 Multiplexer bit 7 mask. */ -#define EVSYS_CHMUX7_bp 7 /* Event Channel 0 Multiplexer bit 7 position. */ - - -/* EVSYS.CH1MUX bit masks and bit positions */ -/* EVSYS_CHMUX_gm Predefined. */ -/* EVSYS_CHMUX_gp Predefined. */ -/* EVSYS_CHMUX0_bm Predefined. */ -/* EVSYS_CHMUX0_bp Predefined. */ -/* EVSYS_CHMUX1_bm Predefined. */ -/* EVSYS_CHMUX1_bp Predefined. */ -/* EVSYS_CHMUX2_bm Predefined. */ -/* EVSYS_CHMUX2_bp Predefined. */ -/* EVSYS_CHMUX3_bm Predefined. */ -/* EVSYS_CHMUX3_bp Predefined. */ -/* EVSYS_CHMUX4_bm Predefined. */ -/* EVSYS_CHMUX4_bp Predefined. */ -/* EVSYS_CHMUX5_bm Predefined. */ -/* EVSYS_CHMUX5_bp Predefined. */ -/* EVSYS_CHMUX6_bm Predefined. */ -/* EVSYS_CHMUX6_bp Predefined. */ -/* EVSYS_CHMUX7_bm Predefined. */ -/* EVSYS_CHMUX7_bp Predefined. */ - - -/* EVSYS.CH2MUX bit masks and bit positions */ -/* EVSYS_CHMUX_gm Predefined. */ -/* EVSYS_CHMUX_gp Predefined. */ -/* EVSYS_CHMUX0_bm Predefined. */ -/* EVSYS_CHMUX0_bp Predefined. */ -/* EVSYS_CHMUX1_bm Predefined. */ -/* EVSYS_CHMUX1_bp Predefined. */ -/* EVSYS_CHMUX2_bm Predefined. */ -/* EVSYS_CHMUX2_bp Predefined. */ -/* EVSYS_CHMUX3_bm Predefined. */ -/* EVSYS_CHMUX3_bp Predefined. */ -/* EVSYS_CHMUX4_bm Predefined. */ -/* EVSYS_CHMUX4_bp Predefined. */ -/* EVSYS_CHMUX5_bm Predefined. */ -/* EVSYS_CHMUX5_bp Predefined. */ -/* EVSYS_CHMUX6_bm Predefined. */ -/* EVSYS_CHMUX6_bp Predefined. */ -/* EVSYS_CHMUX7_bm Predefined. */ -/* EVSYS_CHMUX7_bp Predefined. */ - - -/* EVSYS.CH3MUX bit masks and bit positions */ -/* EVSYS_CHMUX_gm Predefined. */ -/* EVSYS_CHMUX_gp Predefined. */ -/* EVSYS_CHMUX0_bm Predefined. */ -/* EVSYS_CHMUX0_bp Predefined. */ -/* EVSYS_CHMUX1_bm Predefined. */ -/* EVSYS_CHMUX1_bp Predefined. */ -/* EVSYS_CHMUX2_bm Predefined. */ -/* EVSYS_CHMUX2_bp Predefined. */ -/* EVSYS_CHMUX3_bm Predefined. */ -/* EVSYS_CHMUX3_bp Predefined. */ -/* EVSYS_CHMUX4_bm Predefined. */ -/* EVSYS_CHMUX4_bp Predefined. */ -/* EVSYS_CHMUX5_bm Predefined. */ -/* EVSYS_CHMUX5_bp Predefined. */ -/* EVSYS_CHMUX6_bm Predefined. */ -/* EVSYS_CHMUX6_bp Predefined. */ -/* EVSYS_CHMUX7_bm Predefined. */ -/* EVSYS_CHMUX7_bp Predefined. */ - - -/* EVSYS.CH0CTRL bit masks and bit positions */ -#define EVSYS_QDIRM_gm 0x60 /* Quadrature Decoder Index Recognition Mode group mask. */ -#define EVSYS_QDIRM_gp 5 /* Quadrature Decoder Index Recognition Mode group position. */ -#define EVSYS_QDIRM0_bm (1<<5) /* Quadrature Decoder Index Recognition Mode bit 0 mask. */ -#define EVSYS_QDIRM0_bp 5 /* Quadrature Decoder Index Recognition Mode bit 0 position. */ -#define EVSYS_QDIRM1_bm (1<<6) /* Quadrature Decoder Index Recognition Mode bit 1 mask. */ -#define EVSYS_QDIRM1_bp 6 /* Quadrature Decoder Index Recognition Mode bit 1 position. */ - -#define EVSYS_QDIEN_bm 0x10 /* Quadrature Decoder Index Enable bit mask. */ -#define EVSYS_QDIEN_bp 4 /* Quadrature Decoder Index Enable bit position. */ - -#define EVSYS_QDEN_bm 0x08 /* Quadrature Decoder Enable bit mask. */ -#define EVSYS_QDEN_bp 3 /* Quadrature Decoder Enable bit position. */ - -#define EVSYS_DIGFILT_gm 0x07 /* Digital Filter group mask. */ -#define EVSYS_DIGFILT_gp 0 /* Digital Filter group position. */ -#define EVSYS_DIGFILT0_bm (1<<0) /* Digital Filter bit 0 mask. */ -#define EVSYS_DIGFILT0_bp 0 /* Digital Filter bit 0 position. */ -#define EVSYS_DIGFILT1_bm (1<<1) /* Digital Filter bit 1 mask. */ -#define EVSYS_DIGFILT1_bp 1 /* Digital Filter bit 1 position. */ -#define EVSYS_DIGFILT2_bm (1<<2) /* Digital Filter bit 2 mask. */ -#define EVSYS_DIGFILT2_bp 2 /* Digital Filter bit 2 position. */ - - -/* EVSYS.CH1CTRL bit masks and bit positions */ -/* EVSYS_DIGFILT_gm Predefined. */ -/* EVSYS_DIGFILT_gp Predefined. */ -/* EVSYS_DIGFILT0_bm Predefined. */ -/* EVSYS_DIGFILT0_bp Predefined. */ -/* EVSYS_DIGFILT1_bm Predefined. */ -/* EVSYS_DIGFILT1_bp Predefined. */ -/* EVSYS_DIGFILT2_bm Predefined. */ -/* EVSYS_DIGFILT2_bp Predefined. */ - - -/* EVSYS.CH2CTRL bit masks and bit positions */ -/* EVSYS_QDIRM_gm Predefined. */ -/* EVSYS_QDIRM_gp Predefined. */ -/* EVSYS_QDIRM0_bm Predefined. */ -/* EVSYS_QDIRM0_bp Predefined. */ -/* EVSYS_QDIRM1_bm Predefined. */ -/* EVSYS_QDIRM1_bp Predefined. */ - -/* EVSYS_QDIEN_bm Predefined. */ -/* EVSYS_QDIEN_bp Predefined. */ - -/* EVSYS_QDEN_bm Predefined. */ -/* EVSYS_QDEN_bp Predefined. */ - -/* EVSYS_DIGFILT_gm Predefined. */ -/* EVSYS_DIGFILT_gp Predefined. */ -/* EVSYS_DIGFILT0_bm Predefined. */ -/* EVSYS_DIGFILT0_bp Predefined. */ -/* EVSYS_DIGFILT1_bm Predefined. */ -/* EVSYS_DIGFILT1_bp Predefined. */ -/* EVSYS_DIGFILT2_bm Predefined. */ -/* EVSYS_DIGFILT2_bp Predefined. */ - - -/* EVSYS.CH3CTRL bit masks and bit positions */ -/* EVSYS_DIGFILT_gm Predefined. */ -/* EVSYS_DIGFILT_gp Predefined. */ -/* EVSYS_DIGFILT0_bm Predefined. */ -/* EVSYS_DIGFILT0_bp Predefined. */ -/* EVSYS_DIGFILT1_bm Predefined. */ -/* EVSYS_DIGFILT1_bp Predefined. */ -/* EVSYS_DIGFILT2_bm Predefined. */ -/* EVSYS_DIGFILT2_bp Predefined. */ - - -/* NVM - Non Volatile Memory Controller */ -/* NVM.CMD bit masks and bit positions */ -#define NVM_CMD_gm 0xFF /* Command group mask. */ -#define NVM_CMD_gp 0 /* Command group position. */ -#define NVM_CMD0_bm (1<<0) /* Command bit 0 mask. */ -#define NVM_CMD0_bp 0 /* Command bit 0 position. */ -#define NVM_CMD1_bm (1<<1) /* Command bit 1 mask. */ -#define NVM_CMD1_bp 1 /* Command bit 1 position. */ -#define NVM_CMD2_bm (1<<2) /* Command bit 2 mask. */ -#define NVM_CMD2_bp 2 /* Command bit 2 position. */ -#define NVM_CMD3_bm (1<<3) /* Command bit 3 mask. */ -#define NVM_CMD3_bp 3 /* Command bit 3 position. */ -#define NVM_CMD4_bm (1<<4) /* Command bit 4 mask. */ -#define NVM_CMD4_bp 4 /* Command bit 4 position. */ -#define NVM_CMD5_bm (1<<5) /* Command bit 5 mask. */ -#define NVM_CMD5_bp 5 /* Command bit 5 position. */ -#define NVM_CMD6_bm (1<<6) /* Command bit 6 mask. */ -#define NVM_CMD6_bp 6 /* Command bit 6 position. */ -#define NVM_CMD7_bm (1<<7) /* Command bit 7 mask. */ -#define NVM_CMD7_bp 7 /* Command bit 7 position. */ - - -/* NVM.CTRLA bit masks and bit positions */ -#define NVM_CMDEX_bm 0x01 /* Command Execute bit mask. */ -#define NVM_CMDEX_bp 0 /* Command Execute bit position. */ - - -/* NVM.CTRLB bit masks and bit positions */ -#define NVM_EEMAPEN_bm 0x08 /* EEPROM Mapping Enable bit mask. */ -#define NVM_EEMAPEN_bp 3 /* EEPROM Mapping Enable bit position. */ - -#define NVM_FPRM_bm 0x04 /* Flash Power Reduction Enable bit mask. */ -#define NVM_FPRM_bp 2 /* Flash Power Reduction Enable bit position. */ - -#define NVM_EPRM_bm 0x02 /* EEPROM Power Reduction Enable bit mask. */ -#define NVM_EPRM_bp 1 /* EEPROM Power Reduction Enable bit position. */ - -#define NVM_SPMLOCK_bm 0x01 /* SPM Lock bit mask. */ -#define NVM_SPMLOCK_bp 0 /* SPM Lock bit position. */ - - -/* NVM.INTCTRL bit masks and bit positions */ -#define NVM_SPMLVL_gm 0x0C /* SPM Interrupt Level group mask. */ -#define NVM_SPMLVL_gp 2 /* SPM Interrupt Level group position. */ -#define NVM_SPMLVL0_bm (1<<2) /* SPM Interrupt Level bit 0 mask. */ -#define NVM_SPMLVL0_bp 2 /* SPM Interrupt Level bit 0 position. */ -#define NVM_SPMLVL1_bm (1<<3) /* SPM Interrupt Level bit 1 mask. */ -#define NVM_SPMLVL1_bp 3 /* SPM Interrupt Level bit 1 position. */ - -#define NVM_EELVL_gm 0x03 /* EEPROM Interrupt Level group mask. */ -#define NVM_EELVL_gp 0 /* EEPROM Interrupt Level group position. */ -#define NVM_EELVL0_bm (1<<0) /* EEPROM Interrupt Level bit 0 mask. */ -#define NVM_EELVL0_bp 0 /* EEPROM Interrupt Level bit 0 position. */ -#define NVM_EELVL1_bm (1<<1) /* EEPROM Interrupt Level bit 1 mask. */ -#define NVM_EELVL1_bp 1 /* EEPROM Interrupt Level bit 1 position. */ - - -/* NVM.STATUS bit masks and bit positions */ -#define NVM_NVMBUSY_bm 0x80 /* Non-volatile Memory Busy bit mask. */ -#define NVM_NVMBUSY_bp 7 /* Non-volatile Memory Busy bit position. */ - -#define NVM_FBUSY_bm 0x40 /* Flash Memory Busy bit mask. */ -#define NVM_FBUSY_bp 6 /* Flash Memory Busy bit position. */ - -#define NVM_EELOAD_bm 0x02 /* EEPROM Page Buffer Active Loading bit mask. */ -#define NVM_EELOAD_bp 1 /* EEPROM Page Buffer Active Loading bit position. */ - -#define NVM_FLOAD_bm 0x01 /* Flash Page Buffer Active Loading bit mask. */ -#define NVM_FLOAD_bp 0 /* Flash Page Buffer Active Loading bit position. */ - - -/* NVM.LOCKBITS bit masks and bit positions */ -#define NVM_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ -#define NVM_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ -#define NVM_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ -#define NVM_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ -#define NVM_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ -#define NVM_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ - -#define NVM_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ -#define NVM_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ -#define NVM_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ -#define NVM_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ -#define NVM_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ -#define NVM_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ - -#define NVM_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ -#define NVM_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ -#define NVM_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ -#define NVM_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ -#define NVM_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ -#define NVM_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ - -#define NVM_LB_gm 0x03 /* Lock Bits group mask. */ -#define NVM_LB_gp 0 /* Lock Bits group position. */ -#define NVM_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ -#define NVM_LB0_bp 0 /* Lock Bits bit 0 position. */ -#define NVM_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ -#define NVM_LB1_bp 1 /* Lock Bits bit 1 position. */ - - -/* NVM_LOCKBITS.LOCKBITS bit masks and bit positions */ -#define NVM_LOCKBITS_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ -#define NVM_LOCKBITS_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ -#define NVM_LOCKBITS_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ -#define NVM_LOCKBITS_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ -#define NVM_LOCKBITS_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ -#define NVM_LOCKBITS_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ - -#define NVM_LOCKBITS_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ -#define NVM_LOCKBITS_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ -#define NVM_LOCKBITS_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ -#define NVM_LOCKBITS_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ -#define NVM_LOCKBITS_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ -#define NVM_LOCKBITS_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ - -#define NVM_LOCKBITS_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ -#define NVM_LOCKBITS_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ -#define NVM_LOCKBITS_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ -#define NVM_LOCKBITS_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ -#define NVM_LOCKBITS_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ -#define NVM_LOCKBITS_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ - -#define NVM_LOCKBITS_LB_gm 0x03 /* Lock Bits group mask. */ -#define NVM_LOCKBITS_LB_gp 0 /* Lock Bits group position. */ -#define NVM_LOCKBITS_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ -#define NVM_LOCKBITS_LB0_bp 0 /* Lock Bits bit 0 position. */ -#define NVM_LOCKBITS_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ -#define NVM_LOCKBITS_LB1_bp 1 /* Lock Bits bit 1 position. */ - - -/* NVM_FUSES.FUSEBYTE0 bit masks and bit positions */ -#define NVM_FUSES_USERID_gm 0xFF /* User ID group mask. */ -#define NVM_FUSES_USERID_gp 0 /* User ID group position. */ -#define NVM_FUSES_USERID0_bm (1<<0) /* User ID bit 0 mask. */ -#define NVM_FUSES_USERID0_bp 0 /* User ID bit 0 position. */ -#define NVM_FUSES_USERID1_bm (1<<1) /* User ID bit 1 mask. */ -#define NVM_FUSES_USERID1_bp 1 /* User ID bit 1 position. */ -#define NVM_FUSES_USERID2_bm (1<<2) /* User ID bit 2 mask. */ -#define NVM_FUSES_USERID2_bp 2 /* User ID bit 2 position. */ -#define NVM_FUSES_USERID3_bm (1<<3) /* User ID bit 3 mask. */ -#define NVM_FUSES_USERID3_bp 3 /* User ID bit 3 position. */ -#define NVM_FUSES_USERID4_bm (1<<4) /* User ID bit 4 mask. */ -#define NVM_FUSES_USERID4_bp 4 /* User ID bit 4 position. */ -#define NVM_FUSES_USERID5_bm (1<<5) /* User ID bit 5 mask. */ -#define NVM_FUSES_USERID5_bp 5 /* User ID bit 5 position. */ -#define NVM_FUSES_USERID6_bm (1<<6) /* User ID bit 6 mask. */ -#define NVM_FUSES_USERID6_bp 6 /* User ID bit 6 position. */ -#define NVM_FUSES_USERID7_bm (1<<7) /* User ID bit 7 mask. */ -#define NVM_FUSES_USERID7_bp 7 /* User ID bit 7 position. */ - - -/* NVM_FUSES.FUSEBYTE1 bit masks and bit positions */ -#define NVM_FUSES_WDWP_gm 0xF0 /* Watchdog Window Timeout Period group mask. */ -#define NVM_FUSES_WDWP_gp 4 /* Watchdog Window Timeout Period group position. */ -#define NVM_FUSES_WDWP0_bm (1<<4) /* Watchdog Window Timeout Period bit 0 mask. */ -#define NVM_FUSES_WDWP0_bp 4 /* Watchdog Window Timeout Period bit 0 position. */ -#define NVM_FUSES_WDWP1_bm (1<<5) /* Watchdog Window Timeout Period bit 1 mask. */ -#define NVM_FUSES_WDWP1_bp 5 /* Watchdog Window Timeout Period bit 1 position. */ -#define NVM_FUSES_WDWP2_bm (1<<6) /* Watchdog Window Timeout Period bit 2 mask. */ -#define NVM_FUSES_WDWP2_bp 6 /* Watchdog Window Timeout Period bit 2 position. */ -#define NVM_FUSES_WDWP3_bm (1<<7) /* Watchdog Window Timeout Period bit 3 mask. */ -#define NVM_FUSES_WDWP3_bp 7 /* Watchdog Window Timeout Period bit 3 position. */ - -#define NVM_FUSES_WDP_gm 0x0F /* Watchdog Timeout Period group mask. */ -#define NVM_FUSES_WDP_gp 0 /* Watchdog Timeout Period group position. */ -#define NVM_FUSES_WDP0_bm (1<<0) /* Watchdog Timeout Period bit 0 mask. */ -#define NVM_FUSES_WDP0_bp 0 /* Watchdog Timeout Period bit 0 position. */ -#define NVM_FUSES_WDP1_bm (1<<1) /* Watchdog Timeout Period bit 1 mask. */ -#define NVM_FUSES_WDP1_bp 1 /* Watchdog Timeout Period bit 1 position. */ -#define NVM_FUSES_WDP2_bm (1<<2) /* Watchdog Timeout Period bit 2 mask. */ -#define NVM_FUSES_WDP2_bp 2 /* Watchdog Timeout Period bit 2 position. */ -#define NVM_FUSES_WDP3_bm (1<<3) /* Watchdog Timeout Period bit 3 mask. */ -#define NVM_FUSES_WDP3_bp 3 /* Watchdog Timeout Period bit 3 position. */ - - -/* NVM_FUSES.FUSEBYTE2 bit masks and bit positions */ -#define NVM_FUSES_DVSDON_bm 0x80 /* Spike Detector Enable bit mask. */ -#define NVM_FUSES_DVSDON_bp 7 /* Spike Detector Enable bit position. */ - -#define NVM_FUSES_BOOTRST_bm 0x40 /* Boot Loader Section Reset Vector bit mask. */ -#define NVM_FUSES_BOOTRST_bp 6 /* Boot Loader Section Reset Vector bit position. */ - -#define NVM_FUSES_BODPD_gm 0x03 /* BOD Operation in Power-Down Mode group mask. */ -#define NVM_FUSES_BODPD_gp 0 /* BOD Operation in Power-Down Mode group position. */ -#define NVM_FUSES_BODPD0_bm (1<<0) /* BOD Operation in Power-Down Mode bit 0 mask. */ -#define NVM_FUSES_BODPD0_bp 0 /* BOD Operation in Power-Down Mode bit 0 position. */ -#define NVM_FUSES_BODPD1_bm (1<<1) /* BOD Operation in Power-Down Mode bit 1 mask. */ -#define NVM_FUSES_BODPD1_bp 1 /* BOD Operation in Power-Down Mode bit 1 position. */ - - -/* NVM_FUSES.FUSEBYTE4 bit masks and bit positions */ -#define NVM_FUSES_SUT_gm 0x0C /* Start-up Time group mask. */ -#define NVM_FUSES_SUT_gp 2 /* Start-up Time group position. */ -#define NVM_FUSES_SUT0_bm (1<<2) /* Start-up Time bit 0 mask. */ -#define NVM_FUSES_SUT0_bp 2 /* Start-up Time bit 0 position. */ -#define NVM_FUSES_SUT1_bm (1<<3) /* Start-up Time bit 1 mask. */ -#define NVM_FUSES_SUT1_bp 3 /* Start-up Time bit 1 position. */ - -#define NVM_FUSES_WDLOCK_bm 0x02 /* Watchdog Timer Lock bit mask. */ -#define NVM_FUSES_WDLOCK_bp 1 /* Watchdog Timer Lock bit position. */ - - -/* NVM_FUSES.FUSEBYTE5 bit masks and bit positions */ -#define NVM_FUSES_BODACT_gm 0x30 /* BOD Operation in Active Mode group mask. */ -#define NVM_FUSES_BODACT_gp 4 /* BOD Operation in Active Mode group position. */ -#define NVM_FUSES_BODACT0_bm (1<<4) /* BOD Operation in Active Mode bit 0 mask. */ -#define NVM_FUSES_BODACT0_bp 4 /* BOD Operation in Active Mode bit 0 position. */ -#define NVM_FUSES_BODACT1_bm (1<<5) /* BOD Operation in Active Mode bit 1 mask. */ -#define NVM_FUSES_BODACT1_bp 5 /* BOD Operation in Active Mode bit 1 position. */ - -#define NVM_FUSES_EESAVE_bm 0x08 /* Preserve EEPROM Through Chip Erase bit mask. */ -#define NVM_FUSES_EESAVE_bp 3 /* Preserve EEPROM Through Chip Erase bit position. */ - -#define NVM_FUSES_BODLVL_gm 0x07 /* Brown Out Detection Voltage Level group mask. */ -#define NVM_FUSES_BODLVL_gp 0 /* Brown Out Detection Voltage Level group position. */ -#define NVM_FUSES_BODLVL0_bm (1<<0) /* Brown Out Detection Voltage Level bit 0 mask. */ -#define NVM_FUSES_BODLVL0_bp 0 /* Brown Out Detection Voltage Level bit 0 position. */ -#define NVM_FUSES_BODLVL1_bm (1<<1) /* Brown Out Detection Voltage Level bit 1 mask. */ -#define NVM_FUSES_BODLVL1_bp 1 /* Brown Out Detection Voltage Level bit 1 position. */ -#define NVM_FUSES_BODLVL2_bm (1<<2) /* Brown Out Detection Voltage Level bit 2 mask. */ -#define NVM_FUSES_BODLVL2_bp 2 /* Brown Out Detection Voltage Level bit 2 position. */ - - -/* AC - Analog Comparator */ -/* AC.AC0CTRL bit masks and bit positions */ -#define AC_INTMODE_gm 0xC0 /* Interrupt Mode group mask. */ -#define AC_INTMODE_gp 6 /* Interrupt Mode group position. */ -#define AC_INTMODE0_bm (1<<6) /* Interrupt Mode bit 0 mask. */ -#define AC_INTMODE0_bp 6 /* Interrupt Mode bit 0 position. */ -#define AC_INTMODE1_bm (1<<7) /* Interrupt Mode bit 1 mask. */ -#define AC_INTMODE1_bp 7 /* Interrupt Mode bit 1 position. */ - -#define AC_INTLVL_gm 0x30 /* Interrupt Level group mask. */ -#define AC_INTLVL_gp 4 /* Interrupt Level group position. */ -#define AC_INTLVL0_bm (1<<4) /* Interrupt Level bit 0 mask. */ -#define AC_INTLVL0_bp 4 /* Interrupt Level bit 0 position. */ -#define AC_INTLVL1_bm (1<<5) /* Interrupt Level bit 1 mask. */ -#define AC_INTLVL1_bp 5 /* Interrupt Level bit 1 position. */ - -#define AC_HSMODE_bm 0x08 /* High-speed Mode bit mask. */ -#define AC_HSMODE_bp 3 /* High-speed Mode bit position. */ - -#define AC_HYSMODE_gm 0x06 /* Hysteresis Mode group mask. */ -#define AC_HYSMODE_gp 1 /* Hysteresis Mode group position. */ -#define AC_HYSMODE0_bm (1<<1) /* Hysteresis Mode bit 0 mask. */ -#define AC_HYSMODE0_bp 1 /* Hysteresis Mode bit 0 position. */ -#define AC_HYSMODE1_bm (1<<2) /* Hysteresis Mode bit 1 mask. */ -#define AC_HYSMODE1_bp 2 /* Hysteresis Mode bit 1 position. */ - -#define AC_ENABLE_bm 0x01 /* Enable bit mask. */ -#define AC_ENABLE_bp 0 /* Enable bit position. */ - - -/* AC.AC1CTRL bit masks and bit positions */ -/* AC_INTMODE_gm Predefined. */ -/* AC_INTMODE_gp Predefined. */ -/* AC_INTMODE0_bm Predefined. */ -/* AC_INTMODE0_bp Predefined. */ -/* AC_INTMODE1_bm Predefined. */ -/* AC_INTMODE1_bp Predefined. */ - -/* AC_INTLVL_gm Predefined. */ -/* AC_INTLVL_gp Predefined. */ -/* AC_INTLVL0_bm Predefined. */ -/* AC_INTLVL0_bp Predefined. */ -/* AC_INTLVL1_bm Predefined. */ -/* AC_INTLVL1_bp Predefined. */ - -/* AC_HSMODE_bm Predefined. */ -/* AC_HSMODE_bp Predefined. */ - -/* AC_HYSMODE_gm Predefined. */ -/* AC_HYSMODE_gp Predefined. */ -/* AC_HYSMODE0_bm Predefined. */ -/* AC_HYSMODE0_bp Predefined. */ -/* AC_HYSMODE1_bm Predefined. */ -/* AC_HYSMODE1_bp Predefined. */ - -/* AC_ENABLE_bm Predefined. */ -/* AC_ENABLE_bp Predefined. */ - - -/* AC.AC0MUXCTRL bit masks and bit positions */ -#define AC_MUXPOS_gm 0x38 /* MUX Positive Input group mask. */ -#define AC_MUXPOS_gp 3 /* MUX Positive Input group position. */ -#define AC_MUXPOS0_bm (1<<3) /* MUX Positive Input bit 0 mask. */ -#define AC_MUXPOS0_bp 3 /* MUX Positive Input bit 0 position. */ -#define AC_MUXPOS1_bm (1<<4) /* MUX Positive Input bit 1 mask. */ -#define AC_MUXPOS1_bp 4 /* MUX Positive Input bit 1 position. */ -#define AC_MUXPOS2_bm (1<<5) /* MUX Positive Input bit 2 mask. */ -#define AC_MUXPOS2_bp 5 /* MUX Positive Input bit 2 position. */ - -#define AC_MUXNEG_gm 0x07 /* MUX Negative Input group mask. */ -#define AC_MUXNEG_gp 0 /* MUX Negative Input group position. */ -#define AC_MUXNEG0_bm (1<<0) /* MUX Negative Input bit 0 mask. */ -#define AC_MUXNEG0_bp 0 /* MUX Negative Input bit 0 position. */ -#define AC_MUXNEG1_bm (1<<1) /* MUX Negative Input bit 1 mask. */ -#define AC_MUXNEG1_bp 1 /* MUX Negative Input bit 1 position. */ -#define AC_MUXNEG2_bm (1<<2) /* MUX Negative Input bit 2 mask. */ -#define AC_MUXNEG2_bp 2 /* MUX Negative Input bit 2 position. */ - - -/* AC.AC1MUXCTRL bit masks and bit positions */ -/* AC_MUXPOS_gm Predefined. */ -/* AC_MUXPOS_gp Predefined. */ -/* AC_MUXPOS0_bm Predefined. */ -/* AC_MUXPOS0_bp Predefined. */ -/* AC_MUXPOS1_bm Predefined. */ -/* AC_MUXPOS1_bp Predefined. */ -/* AC_MUXPOS2_bm Predefined. */ -/* AC_MUXPOS2_bp Predefined. */ - -/* AC_MUXNEG_gm Predefined. */ -/* AC_MUXNEG_gp Predefined. */ -/* AC_MUXNEG0_bm Predefined. */ -/* AC_MUXNEG0_bp Predefined. */ -/* AC_MUXNEG1_bm Predefined. */ -/* AC_MUXNEG1_bp Predefined. */ -/* AC_MUXNEG2_bm Predefined. */ -/* AC_MUXNEG2_bp Predefined. */ - - -/* AC.CTRLA bit masks and bit positions */ -#define AC_AC0OUT_bm 0x01 /* Comparator 0 Output Enable bit mask. */ -#define AC_AC0OUT_bp 0 /* Comparator 0 Output Enable bit position. */ - - -/* AC.CTRLB bit masks and bit positions */ -#define AC_SCALEFAC_gm 0x3F /* VCC Voltage Scaler Factor group mask. */ -#define AC_SCALEFAC_gp 0 /* VCC Voltage Scaler Factor group position. */ -#define AC_SCALEFAC0_bm (1<<0) /* VCC Voltage Scaler Factor bit 0 mask. */ -#define AC_SCALEFAC0_bp 0 /* VCC Voltage Scaler Factor bit 0 position. */ -#define AC_SCALEFAC1_bm (1<<1) /* VCC Voltage Scaler Factor bit 1 mask. */ -#define AC_SCALEFAC1_bp 1 /* VCC Voltage Scaler Factor bit 1 position. */ -#define AC_SCALEFAC2_bm (1<<2) /* VCC Voltage Scaler Factor bit 2 mask. */ -#define AC_SCALEFAC2_bp 2 /* VCC Voltage Scaler Factor bit 2 position. */ -#define AC_SCALEFAC3_bm (1<<3) /* VCC Voltage Scaler Factor bit 3 mask. */ -#define AC_SCALEFAC3_bp 3 /* VCC Voltage Scaler Factor bit 3 position. */ -#define AC_SCALEFAC4_bm (1<<4) /* VCC Voltage Scaler Factor bit 4 mask. */ -#define AC_SCALEFAC4_bp 4 /* VCC Voltage Scaler Factor bit 4 position. */ -#define AC_SCALEFAC5_bm (1<<5) /* VCC Voltage Scaler Factor bit 5 mask. */ -#define AC_SCALEFAC5_bp 5 /* VCC Voltage Scaler Factor bit 5 position. */ - - -/* AC.WINCTRL bit masks and bit positions */ -#define AC_WEN_bm 0x10 /* Window Mode Enable bit mask. */ -#define AC_WEN_bp 4 /* Window Mode Enable bit position. */ - -#define AC_WINTMODE_gm 0x0C /* Window Interrupt Mode group mask. */ -#define AC_WINTMODE_gp 2 /* Window Interrupt Mode group position. */ -#define AC_WINTMODE0_bm (1<<2) /* Window Interrupt Mode bit 0 mask. */ -#define AC_WINTMODE0_bp 2 /* Window Interrupt Mode bit 0 position. */ -#define AC_WINTMODE1_bm (1<<3) /* Window Interrupt Mode bit 1 mask. */ -#define AC_WINTMODE1_bp 3 /* Window Interrupt Mode bit 1 position. */ - -#define AC_WINTLVL_gm 0x03 /* Window Interrupt Level group mask. */ -#define AC_WINTLVL_gp 0 /* Window Interrupt Level group position. */ -#define AC_WINTLVL0_bm (1<<0) /* Window Interrupt Level bit 0 mask. */ -#define AC_WINTLVL0_bp 0 /* Window Interrupt Level bit 0 position. */ -#define AC_WINTLVL1_bm (1<<1) /* Window Interrupt Level bit 1 mask. */ -#define AC_WINTLVL1_bp 1 /* Window Interrupt Level bit 1 position. */ - - -/* AC.STATUS bit masks and bit positions */ -#define AC_WSTATE_gm 0xC0 /* Window Mode State group mask. */ -#define AC_WSTATE_gp 6 /* Window Mode State group position. */ -#define AC_WSTATE0_bm (1<<6) /* Window Mode State bit 0 mask. */ -#define AC_WSTATE0_bp 6 /* Window Mode State bit 0 position. */ -#define AC_WSTATE1_bm (1<<7) /* Window Mode State bit 1 mask. */ -#define AC_WSTATE1_bp 7 /* Window Mode State bit 1 position. */ - -#define AC_AC1STATE_bm 0x20 /* Comparator 1 State bit mask. */ -#define AC_AC1STATE_bp 5 /* Comparator 1 State bit position. */ - -#define AC_AC0STATE_bm 0x10 /* Comparator 0 State bit mask. */ -#define AC_AC0STATE_bp 4 /* Comparator 0 State bit position. */ - -#define AC_WIF_bm 0x04 /* Window Mode Interrupt Flag bit mask. */ -#define AC_WIF_bp 2 /* Window Mode Interrupt Flag bit position. */ - -#define AC_AC1IF_bm 0x02 /* Comparator 1 Interrupt Flag bit mask. */ -#define AC_AC1IF_bp 1 /* Comparator 1 Interrupt Flag bit position. */ - -#define AC_AC0IF_bm 0x01 /* Comparator 0 Interrupt Flag bit mask. */ -#define AC_AC0IF_bp 0 /* Comparator 0 Interrupt Flag bit position. */ - - -/* ADC - Analog/Digital Converter */ -/* ADC_CH.CTRL bit masks and bit positions */ -#define ADC_CH_START_bm 0x80 /* Channel Start Conversion bit mask. */ -#define ADC_CH_START_bp 7 /* Channel Start Conversion bit position. */ - -#define ADC_CH_GAINFAC_gm 0x1C /* Gain Factor group mask. */ -#define ADC_CH_GAINFAC_gp 2 /* Gain Factor group position. */ -#define ADC_CH_GAINFAC0_bm (1<<2) /* Gain Factor bit 0 mask. */ -#define ADC_CH_GAINFAC0_bp 2 /* Gain Factor bit 0 position. */ -#define ADC_CH_GAINFAC1_bm (1<<3) /* Gain Factor bit 1 mask. */ -#define ADC_CH_GAINFAC1_bp 3 /* Gain Factor bit 1 position. */ -#define ADC_CH_GAINFAC2_bm (1<<4) /* Gain Factor bit 2 mask. */ -#define ADC_CH_GAINFAC2_bp 4 /* Gain Factor bit 2 position. */ - -#define ADC_CH_INPUTMODE_gm 0x03 /* Input Mode Select group mask. */ -#define ADC_CH_INPUTMODE_gp 0 /* Input Mode Select group position. */ -#define ADC_CH_INPUTMODE0_bm (1<<0) /* Input Mode Select bit 0 mask. */ -#define ADC_CH_INPUTMODE0_bp 0 /* Input Mode Select bit 0 position. */ -#define ADC_CH_INPUTMODE1_bm (1<<1) /* Input Mode Select bit 1 mask. */ -#define ADC_CH_INPUTMODE1_bp 1 /* Input Mode Select bit 1 position. */ - - -/* ADC_CH.MUXCTRL bit masks and bit positions */ -#define ADC_CH_MUXPOS_gm 0x78 /* Positive Input Select group mask. */ -#define ADC_CH_MUXPOS_gp 3 /* Positive Input Select group position. */ -#define ADC_CH_MUXPOS0_bm (1<<3) /* Positive Input Select bit 0 mask. */ -#define ADC_CH_MUXPOS0_bp 3 /* Positive Input Select bit 0 position. */ -#define ADC_CH_MUXPOS1_bm (1<<4) /* Positive Input Select bit 1 mask. */ -#define ADC_CH_MUXPOS1_bp 4 /* Positive Input Select bit 1 position. */ -#define ADC_CH_MUXPOS2_bm (1<<5) /* Positive Input Select bit 2 mask. */ -#define ADC_CH_MUXPOS2_bp 5 /* Positive Input Select bit 2 position. */ -#define ADC_CH_MUXPOS3_bm (1<<6) /* Positive Input Select bit 3 mask. */ -#define ADC_CH_MUXPOS3_bp 6 /* Positive Input Select bit 3 position. */ - -#define ADC_CH_MUXINT_gm 0x78 /* Internal Input Select group mask. */ -#define ADC_CH_MUXINT_gp 3 /* Internal Input Select group position. */ -#define ADC_CH_MUXINT0_bm (1<<3) /* Internal Input Select bit 0 mask. */ -#define ADC_CH_MUXINT0_bp 3 /* Internal Input Select bit 0 position. */ -#define ADC_CH_MUXINT1_bm (1<<4) /* Internal Input Select bit 1 mask. */ -#define ADC_CH_MUXINT1_bp 4 /* Internal Input Select bit 1 position. */ -#define ADC_CH_MUXINT2_bm (1<<5) /* Internal Input Select bit 2 mask. */ -#define ADC_CH_MUXINT2_bp 5 /* Internal Input Select bit 2 position. */ -#define ADC_CH_MUXINT3_bm (1<<6) /* Internal Input Select bit 3 mask. */ -#define ADC_CH_MUXINT3_bp 6 /* Internal Input Select bit 3 position. */ - -#define ADC_CH_MUXNEG_gm 0x03 /* Negative Input Select group mask. */ -#define ADC_CH_MUXNEG_gp 0 /* Negative Input Select group position. */ -#define ADC_CH_MUXNEG0_bm (1<<0) /* Negative Input Select bit 0 mask. */ -#define ADC_CH_MUXNEG0_bp 0 /* Negative Input Select bit 0 position. */ -#define ADC_CH_MUXNEG1_bm (1<<1) /* Negative Input Select bit 1 mask. */ -#define ADC_CH_MUXNEG1_bp 1 /* Negative Input Select bit 1 position. */ - - -/* ADC_CH.INTCTRL bit masks and bit positions */ -#define ADC_CH_INTMODE_gm 0x0C /* Interrupt Mode group mask. */ -#define ADC_CH_INTMODE_gp 2 /* Interrupt Mode group position. */ -#define ADC_CH_INTMODE0_bm (1<<2) /* Interrupt Mode bit 0 mask. */ -#define ADC_CH_INTMODE0_bp 2 /* Interrupt Mode bit 0 position. */ -#define ADC_CH_INTMODE1_bm (1<<3) /* Interrupt Mode bit 1 mask. */ -#define ADC_CH_INTMODE1_bp 3 /* Interrupt Mode bit 1 position. */ - -#define ADC_CH_INTLVL_gm 0x03 /* Interrupt Level group mask. */ -#define ADC_CH_INTLVL_gp 0 /* Interrupt Level group position. */ -#define ADC_CH_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */ -#define ADC_CH_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */ -#define ADC_CH_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ -#define ADC_CH_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */ - - -/* ADC_CH.INTFLAGS bit masks and bit positions */ -#define ADC_CH_CHIF_bm 0x01 /* Channel Interrupt Flag bit mask. */ -#define ADC_CH_CHIF_bp 0 /* Channel Interrupt Flag bit position. */ - - -/* ADC.CTRLA bit masks and bit positions */ -#define ADC_CH0START_bm 0x04 /* Channel 0 Start Conversion bit mask. */ -#define ADC_CH0START_bp 2 /* Channel 0 Start Conversion bit position. */ - -#define ADC_FLUSH_bm 0x02 /* ADC Flush bit mask. */ -#define ADC_FLUSH_bp 1 /* ADC Flush bit position. */ - -#define ADC_ENABLE_bm 0x01 /* Enable ADC bit mask. */ -#define ADC_ENABLE_bp 0 /* Enable ADC bit position. */ - - -/* ADC.CTRLB bit masks and bit positions */ -#define ADC_CURRLIMIT_gm 0x60 /* Current Limitation group mask. */ -#define ADC_CURRLIMIT_gp 5 /* Current Limitation group position. */ -#define ADC_CURRLIMIT0_bm (1<<5) /* Current Limitation bit 0 mask. */ -#define ADC_CURRLIMIT0_bp 5 /* Current Limitation bit 0 position. */ -#define ADC_CURRLIMIT1_bm (1<<6) /* Current Limitation bit 1 mask. */ -#define ADC_CURRLIMIT1_bp 6 /* Current Limitation bit 1 position. */ - -#define ADC_CONMODE_bm 0x10 /* Conversion Mode bit mask. */ -#define ADC_CONMODE_bp 4 /* Conversion Mode bit position. */ - -#define ADC_FREERUN_bm 0x08 /* Free Running Mode Enable bit mask. */ -#define ADC_FREERUN_bp 3 /* Free Running Mode Enable bit position. */ - -#define ADC_RESOLUTION_gm 0x06 /* Result Resolution group mask. */ -#define ADC_RESOLUTION_gp 1 /* Result Resolution group position. */ -#define ADC_RESOLUTION0_bm (1<<1) /* Result Resolution bit 0 mask. */ -#define ADC_RESOLUTION0_bp 1 /* Result Resolution bit 0 position. */ -#define ADC_RESOLUTION1_bm (1<<2) /* Result Resolution bit 1 mask. */ -#define ADC_RESOLUTION1_bp 2 /* Result Resolution bit 1 position. */ - - -/* ADC.REFCTRL bit masks and bit positions */ -#define ADC_REFSEL_gm 0x30 /* Reference Selection group mask. */ -#define ADC_REFSEL_gp 4 /* Reference Selection group position. */ -#define ADC_REFSEL0_bm (1<<4) /* Reference Selection bit 0 mask. */ -#define ADC_REFSEL0_bp 4 /* Reference Selection bit 0 position. */ -#define ADC_REFSEL1_bm (1<<5) /* Reference Selection bit 1 mask. */ -#define ADC_REFSEL1_bp 5 /* Reference Selection bit 1 position. */ - -#define ADC_BANDGAP_bm 0x02 /* Bandgap enable bit mask. */ -#define ADC_BANDGAP_bp 1 /* Bandgap enable bit position. */ - -#define ADC_TEMPREF_bm 0x01 /* Temperature Reference Enable bit mask. */ -#define ADC_TEMPREF_bp 0 /* Temperature Reference Enable bit position. */ - - -/* ADC.EVCTRL bit masks and bit positions */ -#define ADC_SWEEP_gm 0xC0 /* Channel Sweep Selection group mask. */ -#define ADC_SWEEP_gp 6 /* Channel Sweep Selection group position. */ -#define ADC_SWEEP0_bm (1<<6) /* Channel Sweep Selection bit 0 mask. */ -#define ADC_SWEEP0_bp 6 /* Channel Sweep Selection bit 0 position. */ -#define ADC_SWEEP1_bm (1<<7) /* Channel Sweep Selection bit 1 mask. */ -#define ADC_SWEEP1_bp 7 /* Channel Sweep Selection bit 1 position. */ - -#define ADC_EVSEL_gm 0x38 /* Event Input Select group mask. */ -#define ADC_EVSEL_gp 3 /* Event Input Select group position. */ -#define ADC_EVSEL0_bm (1<<3) /* Event Input Select bit 0 mask. */ -#define ADC_EVSEL0_bp 3 /* Event Input Select bit 0 position. */ -#define ADC_EVSEL1_bm (1<<4) /* Event Input Select bit 1 mask. */ -#define ADC_EVSEL1_bp 4 /* Event Input Select bit 1 position. */ -#define ADC_EVSEL2_bm (1<<5) /* Event Input Select bit 2 mask. */ -#define ADC_EVSEL2_bp 5 /* Event Input Select bit 2 position. */ - -#define ADC_EVACT_gm 0x07 /* Event Action Select group mask. */ -#define ADC_EVACT_gp 0 /* Event Action Select group position. */ -#define ADC_EVACT0_bm (1<<0) /* Event Action Select bit 0 mask. */ -#define ADC_EVACT0_bp 0 /* Event Action Select bit 0 position. */ -#define ADC_EVACT1_bm (1<<1) /* Event Action Select bit 1 mask. */ -#define ADC_EVACT1_bp 1 /* Event Action Select bit 1 position. */ -#define ADC_EVACT2_bm (1<<2) /* Event Action Select bit 2 mask. */ -#define ADC_EVACT2_bp 2 /* Event Action Select bit 2 position. */ - - -/* ADC.PRESCALER bit masks and bit positions */ -#define ADC_PRESCALER_gm 0x07 /* Clock Prescaler Selection group mask. */ -#define ADC_PRESCALER_gp 0 /* Clock Prescaler Selection group position. */ -#define ADC_PRESCALER0_bm (1<<0) /* Clock Prescaler Selection bit 0 mask. */ -#define ADC_PRESCALER0_bp 0 /* Clock Prescaler Selection bit 0 position. */ -#define ADC_PRESCALER1_bm (1<<1) /* Clock Prescaler Selection bit 1 mask. */ -#define ADC_PRESCALER1_bp 1 /* Clock Prescaler Selection bit 1 position. */ -#define ADC_PRESCALER2_bm (1<<2) /* Clock Prescaler Selection bit 2 mask. */ -#define ADC_PRESCALER2_bp 2 /* Clock Prescaler Selection bit 2 position. */ - - -/* ADC.INTFLAGS bit masks and bit positions */ -#define ADC_CH0IF_bm 0x01 /* Channel 0 Interrupt Flag bit mask. */ -#define ADC_CH0IF_bp 0 /* Channel 0 Interrupt Flag bit position. */ - - -/* RTC - Real-Time Clounter */ -/* RTC.CTRL bit masks and bit positions */ -#define RTC_PRESCALER_gm 0x07 /* Prescaling Factor group mask. */ -#define RTC_PRESCALER_gp 0 /* Prescaling Factor group position. */ -#define RTC_PRESCALER0_bm (1<<0) /* Prescaling Factor bit 0 mask. */ -#define RTC_PRESCALER0_bp 0 /* Prescaling Factor bit 0 position. */ -#define RTC_PRESCALER1_bm (1<<1) /* Prescaling Factor bit 1 mask. */ -#define RTC_PRESCALER1_bp 1 /* Prescaling Factor bit 1 position. */ -#define RTC_PRESCALER2_bm (1<<2) /* Prescaling Factor bit 2 mask. */ -#define RTC_PRESCALER2_bp 2 /* Prescaling Factor bit 2 position. */ - - -/* RTC.STATUS bit masks and bit positions */ -#define RTC_SYNCBUSY_bm 0x01 /* Synchronization Busy Flag bit mask. */ -#define RTC_SYNCBUSY_bp 0 /* Synchronization Busy Flag bit position. */ - - -/* RTC.INTCTRL bit masks and bit positions */ -#define RTC_COMPINTLVL_gm 0x0C /* Compare Match Interrupt Level group mask. */ -#define RTC_COMPINTLVL_gp 2 /* Compare Match Interrupt Level group position. */ -#define RTC_COMPINTLVL0_bm (1<<2) /* Compare Match Interrupt Level bit 0 mask. */ -#define RTC_COMPINTLVL0_bp 2 /* Compare Match Interrupt Level bit 0 position. */ -#define RTC_COMPINTLVL1_bm (1<<3) /* Compare Match Interrupt Level bit 1 mask. */ -#define RTC_COMPINTLVL1_bp 3 /* Compare Match Interrupt Level bit 1 position. */ - -#define RTC_OVFINTLVL_gm 0x03 /* Overflow Interrupt Level group mask. */ -#define RTC_OVFINTLVL_gp 0 /* Overflow Interrupt Level group position. */ -#define RTC_OVFINTLVL0_bm (1<<0) /* Overflow Interrupt Level bit 0 mask. */ -#define RTC_OVFINTLVL0_bp 0 /* Overflow Interrupt Level bit 0 position. */ -#define RTC_OVFINTLVL1_bm (1<<1) /* Overflow Interrupt Level bit 1 mask. */ -#define RTC_OVFINTLVL1_bp 1 /* Overflow Interrupt Level bit 1 position. */ - - -/* RTC.INTFLAGS bit masks and bit positions */ -#define RTC_COMPIF_bm 0x02 /* Compare Match Interrupt Flag bit mask. */ -#define RTC_COMPIF_bp 1 /* Compare Match Interrupt Flag bit position. */ - -#define RTC_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ -#define RTC_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ - - -/* EBI - External Bus Interface */ -/* EBI_CS.CTRLA bit masks and bit positions */ -#define EBI_CS_ASIZE_gm 0x7C /* Address Size group mask. */ -#define EBI_CS_ASIZE_gp 2 /* Address Size group position. */ -#define EBI_CS_ASIZE0_bm (1<<2) /* Address Size bit 0 mask. */ -#define EBI_CS_ASIZE0_bp 2 /* Address Size bit 0 position. */ -#define EBI_CS_ASIZE1_bm (1<<3) /* Address Size bit 1 mask. */ -#define EBI_CS_ASIZE1_bp 3 /* Address Size bit 1 position. */ -#define EBI_CS_ASIZE2_bm (1<<4) /* Address Size bit 2 mask. */ -#define EBI_CS_ASIZE2_bp 4 /* Address Size bit 2 position. */ -#define EBI_CS_ASIZE3_bm (1<<5) /* Address Size bit 3 mask. */ -#define EBI_CS_ASIZE3_bp 5 /* Address Size bit 3 position. */ -#define EBI_CS_ASIZE4_bm (1<<6) /* Address Size bit 4 mask. */ -#define EBI_CS_ASIZE4_bp 6 /* Address Size bit 4 position. */ - -#define EBI_CS_MODE_gm 0x03 /* Memory Mode group mask. */ -#define EBI_CS_MODE_gp 0 /* Memory Mode group position. */ -#define EBI_CS_MODE0_bm (1<<0) /* Memory Mode bit 0 mask. */ -#define EBI_CS_MODE0_bp 0 /* Memory Mode bit 0 position. */ -#define EBI_CS_MODE1_bm (1<<1) /* Memory Mode bit 1 mask. */ -#define EBI_CS_MODE1_bp 1 /* Memory Mode bit 1 position. */ - - -/* EBI_CS.CTRLB bit masks and bit positions */ -#define EBI_CS_SRWS_gm 0x07 /* SRAM Wait State Cycles group mask. */ -#define EBI_CS_SRWS_gp 0 /* SRAM Wait State Cycles group position. */ -#define EBI_CS_SRWS0_bm (1<<0) /* SRAM Wait State Cycles bit 0 mask. */ -#define EBI_CS_SRWS0_bp 0 /* SRAM Wait State Cycles bit 0 position. */ -#define EBI_CS_SRWS1_bm (1<<1) /* SRAM Wait State Cycles bit 1 mask. */ -#define EBI_CS_SRWS1_bp 1 /* SRAM Wait State Cycles bit 1 position. */ -#define EBI_CS_SRWS2_bm (1<<2) /* SRAM Wait State Cycles bit 2 mask. */ -#define EBI_CS_SRWS2_bp 2 /* SRAM Wait State Cycles bit 2 position. */ - -#define EBI_CS_SDINITDONE_bm 0x80 /* SDRAM Initialization Done bit mask. */ -#define EBI_CS_SDINITDONE_bp 7 /* SDRAM Initialization Done bit position. */ - -#define EBI_CS_SDSREN_bm 0x04 /* SDRAM Self-refresh Enable bit mask. */ -#define EBI_CS_SDSREN_bp 2 /* SDRAM Self-refresh Enable bit position. */ - -#define EBI_CS_SDMODE_gm 0x03 /* SDRAM Mode group mask. */ -#define EBI_CS_SDMODE_gp 0 /* SDRAM Mode group position. */ -#define EBI_CS_SDMODE0_bm (1<<0) /* SDRAM Mode bit 0 mask. */ -#define EBI_CS_SDMODE0_bp 0 /* SDRAM Mode bit 0 position. */ -#define EBI_CS_SDMODE1_bm (1<<1) /* SDRAM Mode bit 1 mask. */ -#define EBI_CS_SDMODE1_bp 1 /* SDRAM Mode bit 1 position. */ - - -/* EBI.CTRL bit masks and bit positions */ -#define EBI_SDDATAW_gm 0xC0 /* SDRAM Data Width Setting group mask. */ -#define EBI_SDDATAW_gp 6 /* SDRAM Data Width Setting group position. */ -#define EBI_SDDATAW0_bm (1<<6) /* SDRAM Data Width Setting bit 0 mask. */ -#define EBI_SDDATAW0_bp 6 /* SDRAM Data Width Setting bit 0 position. */ -#define EBI_SDDATAW1_bm (1<<7) /* SDRAM Data Width Setting bit 1 mask. */ -#define EBI_SDDATAW1_bp 7 /* SDRAM Data Width Setting bit 1 position. */ - -#define EBI_LPCMODE_gm 0x30 /* SRAM LPC Mode group mask. */ -#define EBI_LPCMODE_gp 4 /* SRAM LPC Mode group position. */ -#define EBI_LPCMODE0_bm (1<<4) /* SRAM LPC Mode bit 0 mask. */ -#define EBI_LPCMODE0_bp 4 /* SRAM LPC Mode bit 0 position. */ -#define EBI_LPCMODE1_bm (1<<5) /* SRAM LPC Mode bit 1 mask. */ -#define EBI_LPCMODE1_bp 5 /* SRAM LPC Mode bit 1 position. */ - -#define EBI_SRMODE_gm 0x0C /* SRAM Mode group mask. */ -#define EBI_SRMODE_gp 2 /* SRAM Mode group position. */ -#define EBI_SRMODE0_bm (1<<2) /* SRAM Mode bit 0 mask. */ -#define EBI_SRMODE0_bp 2 /* SRAM Mode bit 0 position. */ -#define EBI_SRMODE1_bm (1<<3) /* SRAM Mode bit 1 mask. */ -#define EBI_SRMODE1_bp 3 /* SRAM Mode bit 1 position. */ - -#define EBI_IFMODE_gm 0x03 /* Interface Mode group mask. */ -#define EBI_IFMODE_gp 0 /* Interface Mode group position. */ -#define EBI_IFMODE0_bm (1<<0) /* Interface Mode bit 0 mask. */ -#define EBI_IFMODE0_bp 0 /* Interface Mode bit 0 position. */ -#define EBI_IFMODE1_bm (1<<1) /* Interface Mode bit 1 mask. */ -#define EBI_IFMODE1_bp 1 /* Interface Mode bit 1 position. */ - - -/* EBI.SDRAMCTRLA bit masks and bit positions */ -#define EBI_SDCAS_bm 0x08 /* SDRAM CAS Latency Setting bit mask. */ -#define EBI_SDCAS_bp 3 /* SDRAM CAS Latency Setting bit position. */ - -#define EBI_SDROW_bm 0x04 /* SDRAM ROW Bits Setting bit mask. */ -#define EBI_SDROW_bp 2 /* SDRAM ROW Bits Setting bit position. */ - -#define EBI_SDCOL_gm 0x03 /* SDRAM Column Bits Setting group mask. */ -#define EBI_SDCOL_gp 0 /* SDRAM Column Bits Setting group position. */ -#define EBI_SDCOL0_bm (1<<0) /* SDRAM Column Bits Setting bit 0 mask. */ -#define EBI_SDCOL0_bp 0 /* SDRAM Column Bits Setting bit 0 position. */ -#define EBI_SDCOL1_bm (1<<1) /* SDRAM Column Bits Setting bit 1 mask. */ -#define EBI_SDCOL1_bp 1 /* SDRAM Column Bits Setting bit 1 position. */ - - -/* EBI.SDRAMCTRLB bit masks and bit positions */ -#define EBI_MRDLY_gm 0xC0 /* SDRAM Mode Register Delay group mask. */ -#define EBI_MRDLY_gp 6 /* SDRAM Mode Register Delay group position. */ -#define EBI_MRDLY0_bm (1<<6) /* SDRAM Mode Register Delay bit 0 mask. */ -#define EBI_MRDLY0_bp 6 /* SDRAM Mode Register Delay bit 0 position. */ -#define EBI_MRDLY1_bm (1<<7) /* SDRAM Mode Register Delay bit 1 mask. */ -#define EBI_MRDLY1_bp 7 /* SDRAM Mode Register Delay bit 1 position. */ - -#define EBI_ROWCYCDLY_gm 0x38 /* SDRAM Row Cycle Delay group mask. */ -#define EBI_ROWCYCDLY_gp 3 /* SDRAM Row Cycle Delay group position. */ -#define EBI_ROWCYCDLY0_bm (1<<3) /* SDRAM Row Cycle Delay bit 0 mask. */ -#define EBI_ROWCYCDLY0_bp 3 /* SDRAM Row Cycle Delay bit 0 position. */ -#define EBI_ROWCYCDLY1_bm (1<<4) /* SDRAM Row Cycle Delay bit 1 mask. */ -#define EBI_ROWCYCDLY1_bp 4 /* SDRAM Row Cycle Delay bit 1 position. */ -#define EBI_ROWCYCDLY2_bm (1<<5) /* SDRAM Row Cycle Delay bit 2 mask. */ -#define EBI_ROWCYCDLY2_bp 5 /* SDRAM Row Cycle Delay bit 2 position. */ - -#define EBI_RPDLY_gm 0x07 /* SDRAM Row-to-Precharge Delay group mask. */ -#define EBI_RPDLY_gp 0 /* SDRAM Row-to-Precharge Delay group position. */ -#define EBI_RPDLY0_bm (1<<0) /* SDRAM Row-to-Precharge Delay bit 0 mask. */ -#define EBI_RPDLY0_bp 0 /* SDRAM Row-to-Precharge Delay bit 0 position. */ -#define EBI_RPDLY1_bm (1<<1) /* SDRAM Row-to-Precharge Delay bit 1 mask. */ -#define EBI_RPDLY1_bp 1 /* SDRAM Row-to-Precharge Delay bit 1 position. */ -#define EBI_RPDLY2_bm (1<<2) /* SDRAM Row-to-Precharge Delay bit 2 mask. */ -#define EBI_RPDLY2_bp 2 /* SDRAM Row-to-Precharge Delay bit 2 position. */ - - -/* EBI.SDRAMCTRLC bit masks and bit positions */ -#define EBI_WRDLY_gm 0xC0 /* SDRAM Write Recovery Delay group mask. */ -#define EBI_WRDLY_gp 6 /* SDRAM Write Recovery Delay group position. */ -#define EBI_WRDLY0_bm (1<<6) /* SDRAM Write Recovery Delay bit 0 mask. */ -#define EBI_WRDLY0_bp 6 /* SDRAM Write Recovery Delay bit 0 position. */ -#define EBI_WRDLY1_bm (1<<7) /* SDRAM Write Recovery Delay bit 1 mask. */ -#define EBI_WRDLY1_bp 7 /* SDRAM Write Recovery Delay bit 1 position. */ - -#define EBI_ESRDLY_gm 0x38 /* SDRAM Exit-Self-refresh-to-Active Delay group mask. */ -#define EBI_ESRDLY_gp 3 /* SDRAM Exit-Self-refresh-to-Active Delay group position. */ -#define EBI_ESRDLY0_bm (1<<3) /* SDRAM Exit-Self-refresh-to-Active Delay bit 0 mask. */ -#define EBI_ESRDLY0_bp 3 /* SDRAM Exit-Self-refresh-to-Active Delay bit 0 position. */ -#define EBI_ESRDLY1_bm (1<<4) /* SDRAM Exit-Self-refresh-to-Active Delay bit 1 mask. */ -#define EBI_ESRDLY1_bp 4 /* SDRAM Exit-Self-refresh-to-Active Delay bit 1 position. */ -#define EBI_ESRDLY2_bm (1<<5) /* SDRAM Exit-Self-refresh-to-Active Delay bit 2 mask. */ -#define EBI_ESRDLY2_bp 5 /* SDRAM Exit-Self-refresh-to-Active Delay bit 2 position. */ - -#define EBI_ROWCOLDLY_gm 0x07 /* SDRAM Row-to-Column Delay group mask. */ -#define EBI_ROWCOLDLY_gp 0 /* SDRAM Row-to-Column Delay group position. */ -#define EBI_ROWCOLDLY0_bm (1<<0) /* SDRAM Row-to-Column Delay bit 0 mask. */ -#define EBI_ROWCOLDLY0_bp 0 /* SDRAM Row-to-Column Delay bit 0 position. */ -#define EBI_ROWCOLDLY1_bm (1<<1) /* SDRAM Row-to-Column Delay bit 1 mask. */ -#define EBI_ROWCOLDLY1_bp 1 /* SDRAM Row-to-Column Delay bit 1 position. */ -#define EBI_ROWCOLDLY2_bm (1<<2) /* SDRAM Row-to-Column Delay bit 2 mask. */ -#define EBI_ROWCOLDLY2_bp 2 /* SDRAM Row-to-Column Delay bit 2 position. */ - - -/* TWI - Two-Wire Interface */ -/* TWI_MASTER.CTRLA bit masks and bit positions */ -#define TWI_MASTER_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ -#define TWI_MASTER_INTLVL_gp 6 /* Interrupt Level group position. */ -#define TWI_MASTER_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ -#define TWI_MASTER_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ -#define TWI_MASTER_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ -#define TWI_MASTER_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ - -#define TWI_MASTER_RIEN_bm 0x20 /* Read Interrupt Enable bit mask. */ -#define TWI_MASTER_RIEN_bp 5 /* Read Interrupt Enable bit position. */ - -#define TWI_MASTER_WIEN_bm 0x10 /* Write Interrupt Enable bit mask. */ -#define TWI_MASTER_WIEN_bp 4 /* Write Interrupt Enable bit position. */ - -#define TWI_MASTER_ENABLE_bm 0x08 /* Enable TWI Master bit mask. */ -#define TWI_MASTER_ENABLE_bp 3 /* Enable TWI Master bit position. */ - - -/* TWI_MASTER.CTRLB bit masks and bit positions */ -#define TWI_MASTER_TIMEOUT_gm 0x0C /* Inactive Bus Timeout group mask. */ -#define TWI_MASTER_TIMEOUT_gp 2 /* Inactive Bus Timeout group position. */ -#define TWI_MASTER_TIMEOUT0_bm (1<<2) /* Inactive Bus Timeout bit 0 mask. */ -#define TWI_MASTER_TIMEOUT0_bp 2 /* Inactive Bus Timeout bit 0 position. */ -#define TWI_MASTER_TIMEOUT1_bm (1<<3) /* Inactive Bus Timeout bit 1 mask. */ -#define TWI_MASTER_TIMEOUT1_bp 3 /* Inactive Bus Timeout bit 1 position. */ - -#define TWI_MASTER_QCEN_bm 0x02 /* Quick Command Enable bit mask. */ -#define TWI_MASTER_QCEN_bp 1 /* Quick Command Enable bit position. */ - -#define TWI_MASTER_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ -#define TWI_MASTER_SMEN_bp 0 /* Smart Mode Enable bit position. */ - - -/* TWI_MASTER.CTRLC bit masks and bit positions */ -#define TWI_MASTER_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ -#define TWI_MASTER_ACKACT_bp 2 /* Acknowledge Action bit position. */ - -#define TWI_MASTER_CMD_gm 0x03 /* Command group mask. */ -#define TWI_MASTER_CMD_gp 0 /* Command group position. */ -#define TWI_MASTER_CMD0_bm (1<<0) /* Command bit 0 mask. */ -#define TWI_MASTER_CMD0_bp 0 /* Command bit 0 position. */ -#define TWI_MASTER_CMD1_bm (1<<1) /* Command bit 1 mask. */ -#define TWI_MASTER_CMD1_bp 1 /* Command bit 1 position. */ - - -/* TWI_MASTER.STATUS bit masks and bit positions */ -#define TWI_MASTER_RIF_bm 0x80 /* Read Interrupt Flag bit mask. */ -#define TWI_MASTER_RIF_bp 7 /* Read Interrupt Flag bit position. */ - -#define TWI_MASTER_WIF_bm 0x40 /* Write Interrupt Flag bit mask. */ -#define TWI_MASTER_WIF_bp 6 /* Write Interrupt Flag bit position. */ - -#define TWI_MASTER_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ -#define TWI_MASTER_CLKHOLD_bp 5 /* Clock Hold bit position. */ - -#define TWI_MASTER_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ -#define TWI_MASTER_RXACK_bp 4 /* Received Acknowledge bit position. */ - -#define TWI_MASTER_ARBLOST_bm 0x08 /* Arbitration Lost bit mask. */ -#define TWI_MASTER_ARBLOST_bp 3 /* Arbitration Lost bit position. */ - -#define TWI_MASTER_BUSERR_bm 0x04 /* Bus Error bit mask. */ -#define TWI_MASTER_BUSERR_bp 2 /* Bus Error bit position. */ - -#define TWI_MASTER_BUSSTATE_gm 0x03 /* Bus State group mask. */ -#define TWI_MASTER_BUSSTATE_gp 0 /* Bus State group position. */ -#define TWI_MASTER_BUSSTATE0_bm (1<<0) /* Bus State bit 0 mask. */ -#define TWI_MASTER_BUSSTATE0_bp 0 /* Bus State bit 0 position. */ -#define TWI_MASTER_BUSSTATE1_bm (1<<1) /* Bus State bit 1 mask. */ -#define TWI_MASTER_BUSSTATE1_bp 1 /* Bus State bit 1 position. */ - - -/* TWI_SLAVE.CTRLA bit masks and bit positions */ -#define TWI_SLAVE_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ -#define TWI_SLAVE_INTLVL_gp 6 /* Interrupt Level group position. */ -#define TWI_SLAVE_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ -#define TWI_SLAVE_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ -#define TWI_SLAVE_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ -#define TWI_SLAVE_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ - -#define TWI_SLAVE_DIEN_bm 0x20 /* Data Interrupt Enable bit mask. */ -#define TWI_SLAVE_DIEN_bp 5 /* Data Interrupt Enable bit position. */ - -#define TWI_SLAVE_APIEN_bm 0x10 /* Address/Stop Interrupt Enable bit mask. */ -#define TWI_SLAVE_APIEN_bp 4 /* Address/Stop Interrupt Enable bit position. */ - -#define TWI_SLAVE_ENABLE_bm 0x08 /* Enable TWI Slave bit mask. */ -#define TWI_SLAVE_ENABLE_bp 3 /* Enable TWI Slave bit position. */ - -#define TWI_SLAVE_PIEN_bm 0x04 /* Stop Interrupt Enable bit mask. */ -#define TWI_SLAVE_PIEN_bp 2 /* Stop Interrupt Enable bit position. */ - -#define TWI_SLAVE_PMEN_bm 0x02 /* Promiscuous Mode Enable bit mask. */ -#define TWI_SLAVE_PMEN_bp 1 /* Promiscuous Mode Enable bit position. */ - -#define TWI_SLAVE_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ -#define TWI_SLAVE_SMEN_bp 0 /* Smart Mode Enable bit position. */ - - -/* TWI_SLAVE.CTRLB bit masks and bit positions */ -#define TWI_SLAVE_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ -#define TWI_SLAVE_ACKACT_bp 2 /* Acknowledge Action bit position. */ - -#define TWI_SLAVE_CMD_gm 0x03 /* Command group mask. */ -#define TWI_SLAVE_CMD_gp 0 /* Command group position. */ -#define TWI_SLAVE_CMD0_bm (1<<0) /* Command bit 0 mask. */ -#define TWI_SLAVE_CMD0_bp 0 /* Command bit 0 position. */ -#define TWI_SLAVE_CMD1_bm (1<<1) /* Command bit 1 mask. */ -#define TWI_SLAVE_CMD1_bp 1 /* Command bit 1 position. */ - - -/* TWI_SLAVE.STATUS bit masks and bit positions */ -#define TWI_SLAVE_DIF_bm 0x80 /* Data Interrupt Flag bit mask. */ -#define TWI_SLAVE_DIF_bp 7 /* Data Interrupt Flag bit position. */ - -#define TWI_SLAVE_APIF_bm 0x40 /* Address/Stop Interrupt Flag bit mask. */ -#define TWI_SLAVE_APIF_bp 6 /* Address/Stop Interrupt Flag bit position. */ - -#define TWI_SLAVE_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ -#define TWI_SLAVE_CLKHOLD_bp 5 /* Clock Hold bit position. */ - -#define TWI_SLAVE_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ -#define TWI_SLAVE_RXACK_bp 4 /* Received Acknowledge bit position. */ - -#define TWI_SLAVE_COLL_bm 0x08 /* Collision bit mask. */ -#define TWI_SLAVE_COLL_bp 3 /* Collision bit position. */ - -#define TWI_SLAVE_BUSERR_bm 0x04 /* Bus Error bit mask. */ -#define TWI_SLAVE_BUSERR_bp 2 /* Bus Error bit position. */ - -#define TWI_SLAVE_DIR_bm 0x02 /* Read/Write Direction bit mask. */ -#define TWI_SLAVE_DIR_bp 1 /* Read/Write Direction bit position. */ - -#define TWI_SLAVE_AP_bm 0x01 /* Slave Address or Stop bit mask. */ -#define TWI_SLAVE_AP_bp 0 /* Slave Address or Stop bit position. */ - - -/* TWI_SLAVE.ADDRMASK bit masks and bit positions */ -#define TWI_SLAVE_ADDRMASK_gm 0xFE /* Address Mask group mask. */ -#define TWI_SLAVE_ADDRMASK_gp 1 /* Address Mask group position. */ -#define TWI_SLAVE_ADDRMASK0_bm (1<<1) /* Address Mask bit 0 mask. */ -#define TWI_SLAVE_ADDRMASK0_bp 1 /* Address Mask bit 0 position. */ -#define TWI_SLAVE_ADDRMASK1_bm (1<<2) /* Address Mask bit 1 mask. */ -#define TWI_SLAVE_ADDRMASK1_bp 2 /* Address Mask bit 1 position. */ -#define TWI_SLAVE_ADDRMASK2_bm (1<<3) /* Address Mask bit 2 mask. */ -#define TWI_SLAVE_ADDRMASK2_bp 3 /* Address Mask bit 2 position. */ -#define TWI_SLAVE_ADDRMASK3_bm (1<<4) /* Address Mask bit 3 mask. */ -#define TWI_SLAVE_ADDRMASK3_bp 4 /* Address Mask bit 3 position. */ -#define TWI_SLAVE_ADDRMASK4_bm (1<<5) /* Address Mask bit 4 mask. */ -#define TWI_SLAVE_ADDRMASK4_bp 5 /* Address Mask bit 4 position. */ -#define TWI_SLAVE_ADDRMASK5_bm (1<<6) /* Address Mask bit 5 mask. */ -#define TWI_SLAVE_ADDRMASK5_bp 6 /* Address Mask bit 5 position. */ -#define TWI_SLAVE_ADDRMASK6_bm (1<<7) /* Address Mask bit 6 mask. */ -#define TWI_SLAVE_ADDRMASK6_bp 7 /* Address Mask bit 6 position. */ - -#define TWI_SLAVE_ADDREN_bm 0x01 /* Address Enable bit mask. */ -#define TWI_SLAVE_ADDREN_bp 0 /* Address Enable bit position. */ - - -/* TWI.CTRL bit masks and bit positions */ -#define TWI_SDAHOLD_bm 0x02 /* SDA Hold Time Enable bit mask. */ -#define TWI_SDAHOLD_bp 1 /* SDA Hold Time Enable bit position. */ - -#define TWI_EDIEN_bm 0x01 /* External Driver Interface Enable bit mask. */ -#define TWI_EDIEN_bp 0 /* External Driver Interface Enable bit position. */ - - -/* PORT - Port Configuration */ -/* PORTCFG.VPCTRLA bit masks and bit positions */ -#define PORTCFG_VP1MAP_gm 0xF0 /* Virtual Port 1 Mapping group mask. */ -#define PORTCFG_VP1MAP_gp 4 /* Virtual Port 1 Mapping group position. */ -#define PORTCFG_VP1MAP0_bm (1<<4) /* Virtual Port 1 Mapping bit 0 mask. */ -#define PORTCFG_VP1MAP0_bp 4 /* Virtual Port 1 Mapping bit 0 position. */ -#define PORTCFG_VP1MAP1_bm (1<<5) /* Virtual Port 1 Mapping bit 1 mask. */ -#define PORTCFG_VP1MAP1_bp 5 /* Virtual Port 1 Mapping bit 1 position. */ -#define PORTCFG_VP1MAP2_bm (1<<6) /* Virtual Port 1 Mapping bit 2 mask. */ -#define PORTCFG_VP1MAP2_bp 6 /* Virtual Port 1 Mapping bit 2 position. */ -#define PORTCFG_VP1MAP3_bm (1<<7) /* Virtual Port 1 Mapping bit 3 mask. */ -#define PORTCFG_VP1MAP3_bp 7 /* Virtual Port 1 Mapping bit 3 position. */ - -#define PORTCFG_VP0MAP_gm 0x0F /* Virtual Port 0 Mapping group mask. */ -#define PORTCFG_VP0MAP_gp 0 /* Virtual Port 0 Mapping group position. */ -#define PORTCFG_VP0MAP0_bm (1<<0) /* Virtual Port 0 Mapping bit 0 mask. */ -#define PORTCFG_VP0MAP0_bp 0 /* Virtual Port 0 Mapping bit 0 position. */ -#define PORTCFG_VP0MAP1_bm (1<<1) /* Virtual Port 0 Mapping bit 1 mask. */ -#define PORTCFG_VP0MAP1_bp 1 /* Virtual Port 0 Mapping bit 1 position. */ -#define PORTCFG_VP0MAP2_bm (1<<2) /* Virtual Port 0 Mapping bit 2 mask. */ -#define PORTCFG_VP0MAP2_bp 2 /* Virtual Port 0 Mapping bit 2 position. */ -#define PORTCFG_VP0MAP3_bm (1<<3) /* Virtual Port 0 Mapping bit 3 mask. */ -#define PORTCFG_VP0MAP3_bp 3 /* Virtual Port 0 Mapping bit 3 position. */ - - -/* PORTCFG.VPCTRLB bit masks and bit positions */ -#define PORTCFG_VP3MAP_gm 0xF0 /* Virtual Port 3 Mapping group mask. */ -#define PORTCFG_VP3MAP_gp 4 /* Virtual Port 3 Mapping group position. */ -#define PORTCFG_VP3MAP0_bm (1<<4) /* Virtual Port 3 Mapping bit 0 mask. */ -#define PORTCFG_VP3MAP0_bp 4 /* Virtual Port 3 Mapping bit 0 position. */ -#define PORTCFG_VP3MAP1_bm (1<<5) /* Virtual Port 3 Mapping bit 1 mask. */ -#define PORTCFG_VP3MAP1_bp 5 /* Virtual Port 3 Mapping bit 1 position. */ -#define PORTCFG_VP3MAP2_bm (1<<6) /* Virtual Port 3 Mapping bit 2 mask. */ -#define PORTCFG_VP3MAP2_bp 6 /* Virtual Port 3 Mapping bit 2 position. */ -#define PORTCFG_VP3MAP3_bm (1<<7) /* Virtual Port 3 Mapping bit 3 mask. */ -#define PORTCFG_VP3MAP3_bp 7 /* Virtual Port 3 Mapping bit 3 position. */ - -#define PORTCFG_VP2MAP_gm 0x0F /* Virtual Port 2 Mapping group mask. */ -#define PORTCFG_VP2MAP_gp 0 /* Virtual Port 2 Mapping group position. */ -#define PORTCFG_VP2MAP0_bm (1<<0) /* Virtual Port 2 Mapping bit 0 mask. */ -#define PORTCFG_VP2MAP0_bp 0 /* Virtual Port 2 Mapping bit 0 position. */ -#define PORTCFG_VP2MAP1_bm (1<<1) /* Virtual Port 2 Mapping bit 1 mask. */ -#define PORTCFG_VP2MAP1_bp 1 /* Virtual Port 2 Mapping bit 1 position. */ -#define PORTCFG_VP2MAP2_bm (1<<2) /* Virtual Port 2 Mapping bit 2 mask. */ -#define PORTCFG_VP2MAP2_bp 2 /* Virtual Port 2 Mapping bit 2 position. */ -#define PORTCFG_VP2MAP3_bm (1<<3) /* Virtual Port 2 Mapping bit 3 mask. */ -#define PORTCFG_VP2MAP3_bp 3 /* Virtual Port 2 Mapping bit 3 position. */ - - -/* PORTCFG.CLKEVOUT bit masks and bit positions */ -#define PORTCFG_CLKOUT_gm 0x03 /* Clock Output Port group mask. */ -#define PORTCFG_CLKOUT_gp 0 /* Clock Output Port group position. */ -#define PORTCFG_CLKOUT0_bm (1<<0) /* Clock Output Port bit 0 mask. */ -#define PORTCFG_CLKOUT0_bp 0 /* Clock Output Port bit 0 position. */ -#define PORTCFG_CLKOUT1_bm (1<<1) /* Clock Output Port bit 1 mask. */ -#define PORTCFG_CLKOUT1_bp 1 /* Clock Output Port bit 1 position. */ - -#define PORTCFG_EVOUT_gm 0x30 /* Event Output Port group mask. */ -#define PORTCFG_EVOUT_gp 4 /* Event Output Port group position. */ -#define PORTCFG_EVOUT0_bm (1<<4) /* Event Output Port bit 0 mask. */ -#define PORTCFG_EVOUT0_bp 4 /* Event Output Port bit 0 position. */ -#define PORTCFG_EVOUT1_bm (1<<5) /* Event Output Port bit 1 mask. */ -#define PORTCFG_EVOUT1_bp 5 /* Event Output Port bit 1 position. */ - - -/* VPORT.INTFLAGS bit masks and bit positions */ -#define VPORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ -#define VPORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ - -#define VPORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ -#define VPORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ - - -/* PORT.INTCTRL bit masks and bit positions */ -#define PORT_INT1LVL_gm 0x0C /* Port Interrupt 1 Level group mask. */ -#define PORT_INT1LVL_gp 2 /* Port Interrupt 1 Level group position. */ -#define PORT_INT1LVL0_bm (1<<2) /* Port Interrupt 1 Level bit 0 mask. */ -#define PORT_INT1LVL0_bp 2 /* Port Interrupt 1 Level bit 0 position. */ -#define PORT_INT1LVL1_bm (1<<3) /* Port Interrupt 1 Level bit 1 mask. */ -#define PORT_INT1LVL1_bp 3 /* Port Interrupt 1 Level bit 1 position. */ - -#define PORT_INT0LVL_gm 0x03 /* Port Interrupt 0 Level group mask. */ -#define PORT_INT0LVL_gp 0 /* Port Interrupt 0 Level group position. */ -#define PORT_INT0LVL0_bm (1<<0) /* Port Interrupt 0 Level bit 0 mask. */ -#define PORT_INT0LVL0_bp 0 /* Port Interrupt 0 Level bit 0 position. */ -#define PORT_INT0LVL1_bm (1<<1) /* Port Interrupt 0 Level bit 1 mask. */ -#define PORT_INT0LVL1_bp 1 /* Port Interrupt 0 Level bit 1 position. */ - - -/* PORT.INTFLAGS bit masks and bit positions */ -#define PORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ -#define PORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ - -#define PORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ -#define PORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ - - -/* PORT.PIN0CTRL bit masks and bit positions */ -#define PORT_SRLEN_bm 0x80 /* Slew Rate Enable bit mask. */ -#define PORT_SRLEN_bp 7 /* Slew Rate Enable bit position. */ - -#define PORT_INVEN_bm 0x40 /* Inverted I/O Enable bit mask. */ -#define PORT_INVEN_bp 6 /* Inverted I/O Enable bit position. */ - -#define PORT_OPC_gm 0x38 /* Output/Pull Configuration group mask. */ -#define PORT_OPC_gp 3 /* Output/Pull Configuration group position. */ -#define PORT_OPC0_bm (1<<3) /* Output/Pull Configuration bit 0 mask. */ -#define PORT_OPC0_bp 3 /* Output/Pull Configuration bit 0 position. */ -#define PORT_OPC1_bm (1<<4) /* Output/Pull Configuration bit 1 mask. */ -#define PORT_OPC1_bp 4 /* Output/Pull Configuration bit 1 position. */ -#define PORT_OPC2_bm (1<<5) /* Output/Pull Configuration bit 2 mask. */ -#define PORT_OPC2_bp 5 /* Output/Pull Configuration bit 2 position. */ - -#define PORT_ISC_gm 0x07 /* Input/Sense Configuration group mask. */ -#define PORT_ISC_gp 0 /* Input/Sense Configuration group position. */ -#define PORT_ISC0_bm (1<<0) /* Input/Sense Configuration bit 0 mask. */ -#define PORT_ISC0_bp 0 /* Input/Sense Configuration bit 0 position. */ -#define PORT_ISC1_bm (1<<1) /* Input/Sense Configuration bit 1 mask. */ -#define PORT_ISC1_bp 1 /* Input/Sense Configuration bit 1 position. */ -#define PORT_ISC2_bm (1<<2) /* Input/Sense Configuration bit 2 mask. */ -#define PORT_ISC2_bp 2 /* Input/Sense Configuration bit 2 position. */ - - -/* PORT.PIN1CTRL bit masks and bit positions */ -/* PORT_SRLEN_bm Predefined. */ -/* PORT_SRLEN_bp Predefined. */ - -/* PORT_INVEN_bm Predefined. */ -/* PORT_INVEN_bp Predefined. */ - -/* PORT_OPC_gm Predefined. */ -/* PORT_OPC_gp Predefined. */ -/* PORT_OPC0_bm Predefined. */ -/* PORT_OPC0_bp Predefined. */ -/* PORT_OPC1_bm Predefined. */ -/* PORT_OPC1_bp Predefined. */ -/* PORT_OPC2_bm Predefined. */ -/* PORT_OPC2_bp Predefined. */ - -/* PORT_ISC_gm Predefined. */ -/* PORT_ISC_gp Predefined. */ -/* PORT_ISC0_bm Predefined. */ -/* PORT_ISC0_bp Predefined. */ -/* PORT_ISC1_bm Predefined. */ -/* PORT_ISC1_bp Predefined. */ -/* PORT_ISC2_bm Predefined. */ -/* PORT_ISC2_bp Predefined. */ - - -/* PORT.PIN2CTRL bit masks and bit positions */ -/* PORT_SRLEN_bm Predefined. */ -/* PORT_SRLEN_bp Predefined. */ - -/* PORT_INVEN_bm Predefined. */ -/* PORT_INVEN_bp Predefined. */ - -/* PORT_OPC_gm Predefined. */ -/* PORT_OPC_gp Predefined. */ -/* PORT_OPC0_bm Predefined. */ -/* PORT_OPC0_bp Predefined. */ -/* PORT_OPC1_bm Predefined. */ -/* PORT_OPC1_bp Predefined. */ -/* PORT_OPC2_bm Predefined. */ -/* PORT_OPC2_bp Predefined. */ - -/* PORT_ISC_gm Predefined. */ -/* PORT_ISC_gp Predefined. */ -/* PORT_ISC0_bm Predefined. */ -/* PORT_ISC0_bp Predefined. */ -/* PORT_ISC1_bm Predefined. */ -/* PORT_ISC1_bp Predefined. */ -/* PORT_ISC2_bm Predefined. */ -/* PORT_ISC2_bp Predefined. */ - - -/* PORT.PIN3CTRL bit masks and bit positions */ -/* PORT_SRLEN_bm Predefined. */ -/* PORT_SRLEN_bp Predefined. */ - -/* PORT_INVEN_bm Predefined. */ -/* PORT_INVEN_bp Predefined. */ - -/* PORT_OPC_gm Predefined. */ -/* PORT_OPC_gp Predefined. */ -/* PORT_OPC0_bm Predefined. */ -/* PORT_OPC0_bp Predefined. */ -/* PORT_OPC1_bm Predefined. */ -/* PORT_OPC1_bp Predefined. */ -/* PORT_OPC2_bm Predefined. */ -/* PORT_OPC2_bp Predefined. */ - -/* PORT_ISC_gm Predefined. */ -/* PORT_ISC_gp Predefined. */ -/* PORT_ISC0_bm Predefined. */ -/* PORT_ISC0_bp Predefined. */ -/* PORT_ISC1_bm Predefined. */ -/* PORT_ISC1_bp Predefined. */ -/* PORT_ISC2_bm Predefined. */ -/* PORT_ISC2_bp Predefined. */ - - -/* PORT.PIN4CTRL bit masks and bit positions */ -/* PORT_SRLEN_bm Predefined. */ -/* PORT_SRLEN_bp Predefined. */ - -/* PORT_INVEN_bm Predefined. */ -/* PORT_INVEN_bp Predefined. */ - -/* PORT_OPC_gm Predefined. */ -/* PORT_OPC_gp Predefined. */ -/* PORT_OPC0_bm Predefined. */ -/* PORT_OPC0_bp Predefined. */ -/* PORT_OPC1_bm Predefined. */ -/* PORT_OPC1_bp Predefined. */ -/* PORT_OPC2_bm Predefined. */ -/* PORT_OPC2_bp Predefined. */ - -/* PORT_ISC_gm Predefined. */ -/* PORT_ISC_gp Predefined. */ -/* PORT_ISC0_bm Predefined. */ -/* PORT_ISC0_bp Predefined. */ -/* PORT_ISC1_bm Predefined. */ -/* PORT_ISC1_bp Predefined. */ -/* PORT_ISC2_bm Predefined. */ -/* PORT_ISC2_bp Predefined. */ - - -/* PORT.PIN5CTRL bit masks and bit positions */ -/* PORT_SRLEN_bm Predefined. */ -/* PORT_SRLEN_bp Predefined. */ - -/* PORT_INVEN_bm Predefined. */ -/* PORT_INVEN_bp Predefined. */ - -/* PORT_OPC_gm Predefined. */ -/* PORT_OPC_gp Predefined. */ -/* PORT_OPC0_bm Predefined. */ -/* PORT_OPC0_bp Predefined. */ -/* PORT_OPC1_bm Predefined. */ -/* PORT_OPC1_bp Predefined. */ -/* PORT_OPC2_bm Predefined. */ -/* PORT_OPC2_bp Predefined. */ - -/* PORT_ISC_gm Predefined. */ -/* PORT_ISC_gp Predefined. */ -/* PORT_ISC0_bm Predefined. */ -/* PORT_ISC0_bp Predefined. */ -/* PORT_ISC1_bm Predefined. */ -/* PORT_ISC1_bp Predefined. */ -/* PORT_ISC2_bm Predefined. */ -/* PORT_ISC2_bp Predefined. */ - - -/* PORT.PIN6CTRL bit masks and bit positions */ -/* PORT_SRLEN_bm Predefined. */ -/* PORT_SRLEN_bp Predefined. */ - -/* PORT_INVEN_bm Predefined. */ -/* PORT_INVEN_bp Predefined. */ - -/* PORT_OPC_gm Predefined. */ -/* PORT_OPC_gp Predefined. */ -/* PORT_OPC0_bm Predefined. */ -/* PORT_OPC0_bp Predefined. */ -/* PORT_OPC1_bm Predefined. */ -/* PORT_OPC1_bp Predefined. */ -/* PORT_OPC2_bm Predefined. */ -/* PORT_OPC2_bp Predefined. */ - -/* PORT_ISC_gm Predefined. */ -/* PORT_ISC_gp Predefined. */ -/* PORT_ISC0_bm Predefined. */ -/* PORT_ISC0_bp Predefined. */ -/* PORT_ISC1_bm Predefined. */ -/* PORT_ISC1_bp Predefined. */ -/* PORT_ISC2_bm Predefined. */ -/* PORT_ISC2_bp Predefined. */ - - -/* PORT.PIN7CTRL bit masks and bit positions */ -/* PORT_SRLEN_bm Predefined. */ -/* PORT_SRLEN_bp Predefined. */ - -/* PORT_INVEN_bm Predefined. */ -/* PORT_INVEN_bp Predefined. */ - -/* PORT_OPC_gm Predefined. */ -/* PORT_OPC_gp Predefined. */ -/* PORT_OPC0_bm Predefined. */ -/* PORT_OPC0_bp Predefined. */ -/* PORT_OPC1_bm Predefined. */ -/* PORT_OPC1_bp Predefined. */ -/* PORT_OPC2_bm Predefined. */ -/* PORT_OPC2_bp Predefined. */ - -/* PORT_ISC_gm Predefined. */ -/* PORT_ISC_gp Predefined. */ -/* PORT_ISC0_bm Predefined. */ -/* PORT_ISC0_bp Predefined. */ -/* PORT_ISC1_bm Predefined. */ -/* PORT_ISC1_bp Predefined. */ -/* PORT_ISC2_bm Predefined. */ -/* PORT_ISC2_bp Predefined. */ - - -/* TC - 16-bit Timer/Counter With PWM */ -/* TC0.CTRLA bit masks and bit positions */ -#define TC0_CLKSEL_gm 0x0F /* Clock Selection group mask. */ -#define TC0_CLKSEL_gp 0 /* Clock Selection group position. */ -#define TC0_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ -#define TC0_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ -#define TC0_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ -#define TC0_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ -#define TC0_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ -#define TC0_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ -#define TC0_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ -#define TC0_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ - - -/* TC0.CTRLB bit masks and bit positions */ -#define TC0_CCDEN_bm 0x80 /* Compare or Capture D Enable bit mask. */ -#define TC0_CCDEN_bp 7 /* Compare or Capture D Enable bit position. */ - -#define TC0_CCCEN_bm 0x40 /* Compare or Capture C Enable bit mask. */ -#define TC0_CCCEN_bp 6 /* Compare or Capture C Enable bit position. */ - -#define TC0_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ -#define TC0_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ - -#define TC0_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ -#define TC0_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ - -#define TC0_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ -#define TC0_WGMODE_gp 0 /* Waveform generation mode group position. */ -#define TC0_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ -#define TC0_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ -#define TC0_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ -#define TC0_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ -#define TC0_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ -#define TC0_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ - - -/* TC0.CTRLC bit masks and bit positions */ -#define TC0_CMPD_bm 0x08 /* Compare D Output Value bit mask. */ -#define TC0_CMPD_bp 3 /* Compare D Output Value bit position. */ - -#define TC0_CMPC_bm 0x04 /* Compare C Output Value bit mask. */ -#define TC0_CMPC_bp 2 /* Compare C Output Value bit position. */ - -#define TC0_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ -#define TC0_CMPB_bp 1 /* Compare B Output Value bit position. */ - -#define TC0_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ -#define TC0_CMPA_bp 0 /* Compare A Output Value bit position. */ - - -/* TC0.CTRLD bit masks and bit positions */ -#define TC0_EVACT_gm 0xE0 /* Event Action group mask. */ -#define TC0_EVACT_gp 5 /* Event Action group position. */ -#define TC0_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ -#define TC0_EVACT0_bp 5 /* Event Action bit 0 position. */ -#define TC0_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ -#define TC0_EVACT1_bp 6 /* Event Action bit 1 position. */ -#define TC0_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ -#define TC0_EVACT2_bp 7 /* Event Action bit 2 position. */ - -#define TC0_EVDLY_bm 0x10 /* Event Delay bit mask. */ -#define TC0_EVDLY_bp 4 /* Event Delay bit position. */ - -#define TC0_EVSEL_gm 0x0F /* Event Source Select group mask. */ -#define TC0_EVSEL_gp 0 /* Event Source Select group position. */ -#define TC0_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ -#define TC0_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ -#define TC0_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ -#define TC0_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ -#define TC0_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ -#define TC0_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ -#define TC0_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ -#define TC0_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ - - -/* TC0.CTRLE bit masks and bit positions */ -#define TC0_BYTEM_bm 0x01 /* Byte Mode bit mask. */ -#define TC0_BYTEM_bp 0 /* Byte Mode bit position. */ - - -/* TC0.INTCTRLA bit masks and bit positions */ -#define TC0_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ -#define TC0_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ -#define TC0_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ -#define TC0_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ -#define TC0_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ -#define TC0_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ - -#define TC0_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ -#define TC0_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ -#define TC0_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ -#define TC0_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ -#define TC0_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ -#define TC0_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ - - -/* TC0.INTCTRLB bit masks and bit positions */ -#define TC0_CCDINTLVL_gm 0xC0 /* Compare or Capture D Interrupt Level group mask. */ -#define TC0_CCDINTLVL_gp 6 /* Compare or Capture D Interrupt Level group position. */ -#define TC0_CCDINTLVL0_bm (1<<6) /* Compare or Capture D Interrupt Level bit 0 mask. */ -#define TC0_CCDINTLVL0_bp 6 /* Compare or Capture D Interrupt Level bit 0 position. */ -#define TC0_CCDINTLVL1_bm (1<<7) /* Compare or Capture D Interrupt Level bit 1 mask. */ -#define TC0_CCDINTLVL1_bp 7 /* Compare or Capture D Interrupt Level bit 1 position. */ - -#define TC0_CCCINTLVL_gm 0x30 /* Compare or Capture C Interrupt Level group mask. */ -#define TC0_CCCINTLVL_gp 4 /* Compare or Capture C Interrupt Level group position. */ -#define TC0_CCCINTLVL0_bm (1<<4) /* Compare or Capture C Interrupt Level bit 0 mask. */ -#define TC0_CCCINTLVL0_bp 4 /* Compare or Capture C Interrupt Level bit 0 position. */ -#define TC0_CCCINTLVL1_bm (1<<5) /* Compare or Capture C Interrupt Level bit 1 mask. */ -#define TC0_CCCINTLVL1_bp 5 /* Compare or Capture C Interrupt Level bit 1 position. */ - -#define TC0_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ -#define TC0_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ -#define TC0_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ -#define TC0_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ -#define TC0_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ -#define TC0_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ - -#define TC0_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ -#define TC0_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ -#define TC0_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ -#define TC0_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ -#define TC0_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ -#define TC0_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ - - -/* TC0.CTRLFCLR bit masks and bit positions */ -#define TC0_CMD_gm 0x0C /* Command group mask. */ -#define TC0_CMD_gp 2 /* Command group position. */ -#define TC0_CMD0_bm (1<<2) /* Command bit 0 mask. */ -#define TC0_CMD0_bp 2 /* Command bit 0 position. */ -#define TC0_CMD1_bm (1<<3) /* Command bit 1 mask. */ -#define TC0_CMD1_bp 3 /* Command bit 1 position. */ - -#define TC0_LUPD_bm 0x02 /* Lock Update bit mask. */ -#define TC0_LUPD_bp 1 /* Lock Update bit position. */ - -#define TC0_DIR_bm 0x01 /* Direction bit mask. */ -#define TC0_DIR_bp 0 /* Direction bit position. */ - - -/* TC0.CTRLFSET bit masks and bit positions */ -/* TC0_CMD_gm Predefined. */ -/* TC0_CMD_gp Predefined. */ -/* TC0_CMD0_bm Predefined. */ -/* TC0_CMD0_bp Predefined. */ -/* TC0_CMD1_bm Predefined. */ -/* TC0_CMD1_bp Predefined. */ - -/* TC0_LUPD_bm Predefined. */ -/* TC0_LUPD_bp Predefined. */ - -/* TC0_DIR_bm Predefined. */ -/* TC0_DIR_bp Predefined. */ - - -/* TC0.CTRLGCLR bit masks and bit positions */ -#define TC0_CCDBV_bm 0x10 /* Compare or Capture D Buffer Valid bit mask. */ -#define TC0_CCDBV_bp 4 /* Compare or Capture D Buffer Valid bit position. */ - -#define TC0_CCCBV_bm 0x08 /* Compare or Capture C Buffer Valid bit mask. */ -#define TC0_CCCBV_bp 3 /* Compare or Capture C Buffer Valid bit position. */ - -#define TC0_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ -#define TC0_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ - -#define TC0_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ -#define TC0_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ - -#define TC0_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ -#define TC0_PERBV_bp 0 /* Period Buffer Valid bit position. */ - - -/* TC0.CTRLGSET bit masks and bit positions */ -/* TC0_CCDBV_bm Predefined. */ -/* TC0_CCDBV_bp Predefined. */ - -/* TC0_CCCBV_bm Predefined. */ -/* TC0_CCCBV_bp Predefined. */ - -/* TC0_CCBBV_bm Predefined. */ -/* TC0_CCBBV_bp Predefined. */ - -/* TC0_CCABV_bm Predefined. */ -/* TC0_CCABV_bp Predefined. */ - -/* TC0_PERBV_bm Predefined. */ -/* TC0_PERBV_bp Predefined. */ - - -/* TC0.INTFLAGS bit masks and bit positions */ -#define TC0_CCDIF_bm 0x80 /* Compare or Capture D Interrupt Flag bit mask. */ -#define TC0_CCDIF_bp 7 /* Compare or Capture D Interrupt Flag bit position. */ - -#define TC0_CCCIF_bm 0x40 /* Compare or Capture C Interrupt Flag bit mask. */ -#define TC0_CCCIF_bp 6 /* Compare or Capture C Interrupt Flag bit position. */ - -#define TC0_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ -#define TC0_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ - -#define TC0_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ -#define TC0_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ - -#define TC0_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ -#define TC0_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ - -#define TC0_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ -#define TC0_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ - - -/* TC1.CTRLA bit masks and bit positions */ -#define TC1_CLKSEL_gm 0x0F /* Clock Selection group mask. */ -#define TC1_CLKSEL_gp 0 /* Clock Selection group position. */ -#define TC1_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ -#define TC1_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ -#define TC1_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ -#define TC1_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ -#define TC1_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ -#define TC1_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ -#define TC1_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ -#define TC1_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ - - -/* TC1.CTRLB bit masks and bit positions */ -#define TC1_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ -#define TC1_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ - -#define TC1_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ -#define TC1_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ - -#define TC1_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ -#define TC1_WGMODE_gp 0 /* Waveform generation mode group position. */ -#define TC1_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ -#define TC1_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ -#define TC1_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ -#define TC1_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ -#define TC1_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ -#define TC1_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ - - -/* TC1.CTRLC bit masks and bit positions */ -#define TC1_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ -#define TC1_CMPB_bp 1 /* Compare B Output Value bit position. */ - -#define TC1_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ -#define TC1_CMPA_bp 0 /* Compare A Output Value bit position. */ - - -/* TC1.CTRLD bit masks and bit positions */ -#define TC1_EVACT_gm 0xE0 /* Event Action group mask. */ -#define TC1_EVACT_gp 5 /* Event Action group position. */ -#define TC1_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ -#define TC1_EVACT0_bp 5 /* Event Action bit 0 position. */ -#define TC1_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ -#define TC1_EVACT1_bp 6 /* Event Action bit 1 position. */ -#define TC1_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ -#define TC1_EVACT2_bp 7 /* Event Action bit 2 position. */ - -#define TC1_EVDLY_bm 0x10 /* Event Delay bit mask. */ -#define TC1_EVDLY_bp 4 /* Event Delay bit position. */ - -#define TC1_EVSEL_gm 0x0F /* Event Source Select group mask. */ -#define TC1_EVSEL_gp 0 /* Event Source Select group position. */ -#define TC1_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ -#define TC1_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ -#define TC1_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ -#define TC1_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ -#define TC1_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ -#define TC1_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ -#define TC1_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ -#define TC1_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ - - -/* TC1.CTRLE bit masks and bit positions */ -#define TC1_BYTEM_bm 0x01 /* Byte Mode bit mask. */ -#define TC1_BYTEM_bp 0 /* Byte Mode bit position. */ - - -/* TC1.INTCTRLA bit masks and bit positions */ -#define TC1_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ -#define TC1_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ -#define TC1_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ -#define TC1_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ -#define TC1_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ -#define TC1_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ - -#define TC1_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ -#define TC1_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ -#define TC1_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ -#define TC1_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ -#define TC1_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ -#define TC1_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ - - -/* TC1.INTCTRLB bit masks and bit positions */ -#define TC1_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ -#define TC1_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ -#define TC1_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ -#define TC1_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ -#define TC1_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ -#define TC1_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ - -#define TC1_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ -#define TC1_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ -#define TC1_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ -#define TC1_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ -#define TC1_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ -#define TC1_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ - - -/* TC1.CTRLFCLR bit masks and bit positions */ -#define TC1_CMD_gm 0x0C /* Command group mask. */ -#define TC1_CMD_gp 2 /* Command group position. */ -#define TC1_CMD0_bm (1<<2) /* Command bit 0 mask. */ -#define TC1_CMD0_bp 2 /* Command bit 0 position. */ -#define TC1_CMD1_bm (1<<3) /* Command bit 1 mask. */ -#define TC1_CMD1_bp 3 /* Command bit 1 position. */ - -#define TC1_LUPD_bm 0x02 /* Lock Update bit mask. */ -#define TC1_LUPD_bp 1 /* Lock Update bit position. */ - -#define TC1_DIR_bm 0x01 /* Direction bit mask. */ -#define TC1_DIR_bp 0 /* Direction bit position. */ - - -/* TC1.CTRLFSET bit masks and bit positions */ -/* TC1_CMD_gm Predefined. */ -/* TC1_CMD_gp Predefined. */ -/* TC1_CMD0_bm Predefined. */ -/* TC1_CMD0_bp Predefined. */ -/* TC1_CMD1_bm Predefined. */ -/* TC1_CMD1_bp Predefined. */ - -/* TC1_LUPD_bm Predefined. */ -/* TC1_LUPD_bp Predefined. */ - -/* TC1_DIR_bm Predefined. */ -/* TC1_DIR_bp Predefined. */ - - -/* TC1.CTRLGCLR bit masks and bit positions */ -#define TC1_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ -#define TC1_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ - -#define TC1_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ -#define TC1_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ - -#define TC1_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ -#define TC1_PERBV_bp 0 /* Period Buffer Valid bit position. */ - - -/* TC1.CTRLGSET bit masks and bit positions */ -/* TC1_CCBBV_bm Predefined. */ -/* TC1_CCBBV_bp Predefined. */ - -/* TC1_CCABV_bm Predefined. */ -/* TC1_CCABV_bp Predefined. */ - -/* TC1_PERBV_bm Predefined. */ -/* TC1_PERBV_bp Predefined. */ - - -/* TC1.INTFLAGS bit masks and bit positions */ -#define TC1_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ -#define TC1_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ - -#define TC1_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ -#define TC1_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ - -#define TC1_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ -#define TC1_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ - -#define TC1_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ -#define TC1_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ - - -/* AWEX.CTRL bit masks and bit positions */ -#define AWEX_PGM_bm 0x20 /* Pattern Generation Mode bit mask. */ -#define AWEX_PGM_bp 5 /* Pattern Generation Mode bit position. */ - -#define AWEX_CWCM_bm 0x10 /* Common Waveform Channel Mode bit mask. */ -#define AWEX_CWCM_bp 4 /* Common Waveform Channel Mode bit position. */ - -#define AWEX_DTICCDEN_bm 0x08 /* Dead Time Insertion Compare Channel D Enable bit mask. */ -#define AWEX_DTICCDEN_bp 3 /* Dead Time Insertion Compare Channel D Enable bit position. */ - -#define AWEX_DTICCCEN_bm 0x04 /* Dead Time Insertion Compare Channel C Enable bit mask. */ -#define AWEX_DTICCCEN_bp 2 /* Dead Time Insertion Compare Channel C Enable bit position. */ - -#define AWEX_DTICCBEN_bm 0x02 /* Dead Time Insertion Compare Channel B Enable bit mask. */ -#define AWEX_DTICCBEN_bp 1 /* Dead Time Insertion Compare Channel B Enable bit position. */ - -#define AWEX_DTICCAEN_bm 0x01 /* Dead Time Insertion Compare Channel A Enable bit mask. */ -#define AWEX_DTICCAEN_bp 0 /* Dead Time Insertion Compare Channel A Enable bit position. */ - - -/* AWEX.FDCTRL bit masks and bit positions */ -#define AWEX_FDDBD_bm 0x10 /* Fault Detect on Disable Break Disable bit mask. */ -#define AWEX_FDDBD_bp 4 /* Fault Detect on Disable Break Disable bit position. */ - -#define AWEX_FDMODE_bm 0x04 /* Fault Detect Mode bit mask. */ -#define AWEX_FDMODE_bp 2 /* Fault Detect Mode bit position. */ - -#define AWEX_FDACT_gm 0x03 /* Fault Detect Action group mask. */ -#define AWEX_FDACT_gp 0 /* Fault Detect Action group position. */ -#define AWEX_FDACT0_bm (1<<0) /* Fault Detect Action bit 0 mask. */ -#define AWEX_FDACT0_bp 0 /* Fault Detect Action bit 0 position. */ -#define AWEX_FDACT1_bm (1<<1) /* Fault Detect Action bit 1 mask. */ -#define AWEX_FDACT1_bp 1 /* Fault Detect Action bit 1 position. */ - - -/* AWEX.STATUS bit masks and bit positions */ -#define AWEX_FDF_bm 0x04 /* Fault Detect Flag bit mask. */ -#define AWEX_FDF_bp 2 /* Fault Detect Flag bit position. */ - -#define AWEX_DTHSBUFV_bm 0x02 /* Dead Time High Side Buffer Valid bit mask. */ -#define AWEX_DTHSBUFV_bp 1 /* Dead Time High Side Buffer Valid bit position. */ - -#define AWEX_DTLSBUFV_bm 0x01 /* Dead Time Low Side Buffer Valid bit mask. */ -#define AWEX_DTLSBUFV_bp 0 /* Dead Time Low Side Buffer Valid bit position. */ - - -/* HIRES.CTRLA bit masks and bit positions */ -#define HIRES_HREN_gm 0x03 /* High Resolution Enable group mask. */ -#define HIRES_HREN_gp 0 /* High Resolution Enable group position. */ -#define HIRES_HREN0_bm (1<<0) /* High Resolution Enable bit 0 mask. */ -#define HIRES_HREN0_bp 0 /* High Resolution Enable bit 0 position. */ -#define HIRES_HREN1_bm (1<<1) /* High Resolution Enable bit 1 mask. */ -#define HIRES_HREN1_bp 1 /* High Resolution Enable bit 1 position. */ - - -/* USART - Universal Asynchronous Receiver-Transmitter */ -/* USART.STATUS bit masks and bit positions */ -#define USART_RXCIF_bm 0x80 /* Receive Interrupt Flag bit mask. */ -#define USART_RXCIF_bp 7 /* Receive Interrupt Flag bit position. */ - -#define USART_TXCIF_bm 0x40 /* Transmit Interrupt Flag bit mask. */ -#define USART_TXCIF_bp 6 /* Transmit Interrupt Flag bit position. */ - -#define USART_DREIF_bm 0x20 /* Data Register Empty Flag bit mask. */ -#define USART_DREIF_bp 5 /* Data Register Empty Flag bit position. */ - -#define USART_FERR_bm 0x10 /* Frame Error bit mask. */ -#define USART_FERR_bp 4 /* Frame Error bit position. */ - -#define USART_BUFOVF_bm 0x08 /* Buffer Overflow bit mask. */ -#define USART_BUFOVF_bp 3 /* Buffer Overflow bit position. */ - -#define USART_PERR_bm 0x04 /* Parity Error bit mask. */ -#define USART_PERR_bp 2 /* Parity Error bit position. */ - -#define USART_RXB8_bm 0x01 /* Receive Bit 8 bit mask. */ -#define USART_RXB8_bp 0 /* Receive Bit 8 bit position. */ - - -/* USART.CTRLA bit masks and bit positions */ -#define USART_RXCINTLVL_gm 0x30 /* Receive Interrupt Level group mask. */ -#define USART_RXCINTLVL_gp 4 /* Receive Interrupt Level group position. */ -#define USART_RXCINTLVL0_bm (1<<4) /* Receive Interrupt Level bit 0 mask. */ -#define USART_RXCINTLVL0_bp 4 /* Receive Interrupt Level bit 0 position. */ -#define USART_RXCINTLVL1_bm (1<<5) /* Receive Interrupt Level bit 1 mask. */ -#define USART_RXCINTLVL1_bp 5 /* Receive Interrupt Level bit 1 position. */ - -#define USART_TXCINTLVL_gm 0x0C /* Transmit Interrupt Level group mask. */ -#define USART_TXCINTLVL_gp 2 /* Transmit Interrupt Level group position. */ -#define USART_TXCINTLVL0_bm (1<<2) /* Transmit Interrupt Level bit 0 mask. */ -#define USART_TXCINTLVL0_bp 2 /* Transmit Interrupt Level bit 0 position. */ -#define USART_TXCINTLVL1_bm (1<<3) /* Transmit Interrupt Level bit 1 mask. */ -#define USART_TXCINTLVL1_bp 3 /* Transmit Interrupt Level bit 1 position. */ - -#define USART_DREINTLVL_gm 0x03 /* Data Register Empty Interrupt Level group mask. */ -#define USART_DREINTLVL_gp 0 /* Data Register Empty Interrupt Level group position. */ -#define USART_DREINTLVL0_bm (1<<0) /* Data Register Empty Interrupt Level bit 0 mask. */ -#define USART_DREINTLVL0_bp 0 /* Data Register Empty Interrupt Level bit 0 position. */ -#define USART_DREINTLVL1_bm (1<<1) /* Data Register Empty Interrupt Level bit 1 mask. */ -#define USART_DREINTLVL1_bp 1 /* Data Register Empty Interrupt Level bit 1 position. */ - - -/* USART.CTRLB bit masks and bit positions */ -#define USART_RXEN_bm 0x10 /* Receiver Enable bit mask. */ -#define USART_RXEN_bp 4 /* Receiver Enable bit position. */ - -#define USART_TXEN_bm 0x08 /* Transmitter Enable bit mask. */ -#define USART_TXEN_bp 3 /* Transmitter Enable bit position. */ - -#define USART_CLK2X_bm 0x04 /* Double transmission speed bit mask. */ -#define USART_CLK2X_bp 2 /* Double transmission speed bit position. */ - -#define USART_MPCM_bm 0x02 /* Multi-processor Communication Mode bit mask. */ -#define USART_MPCM_bp 1 /* Multi-processor Communication Mode bit position. */ - -#define USART_TXB8_bm 0x01 /* Transmit bit 8 bit mask. */ -#define USART_TXB8_bp 0 /* Transmit bit 8 bit position. */ - - -/* USART.CTRLC bit masks and bit positions */ -#define USART_CMODE_gm 0xC0 /* Communication Mode group mask. */ -#define USART_CMODE_gp 6 /* Communication Mode group position. */ -#define USART_CMODE0_bm (1<<6) /* Communication Mode bit 0 mask. */ -#define USART_CMODE0_bp 6 /* Communication Mode bit 0 position. */ -#define USART_CMODE1_bm (1<<7) /* Communication Mode bit 1 mask. */ -#define USART_CMODE1_bp 7 /* Communication Mode bit 1 position. */ - -#define USART_PMODE_gm 0x30 /* Parity Mode group mask. */ -#define USART_PMODE_gp 4 /* Parity Mode group position. */ -#define USART_PMODE0_bm (1<<4) /* Parity Mode bit 0 mask. */ -#define USART_PMODE0_bp 4 /* Parity Mode bit 0 position. */ -#define USART_PMODE1_bm (1<<5) /* Parity Mode bit 1 mask. */ -#define USART_PMODE1_bp 5 /* Parity Mode bit 1 position. */ - -#define USART_SBMODE_bm 0x08 /* Stop Bit Mode bit mask. */ -#define USART_SBMODE_bp 3 /* Stop Bit Mode bit position. */ - -#define USART_CHSIZE_gm 0x07 /* Character Size group mask. */ -#define USART_CHSIZE_gp 0 /* Character Size group position. */ -#define USART_CHSIZE0_bm (1<<0) /* Character Size bit 0 mask. */ -#define USART_CHSIZE0_bp 0 /* Character Size bit 0 position. */ -#define USART_CHSIZE1_bm (1<<1) /* Character Size bit 1 mask. */ -#define USART_CHSIZE1_bp 1 /* Character Size bit 1 position. */ -#define USART_CHSIZE2_bm (1<<2) /* Character Size bit 2 mask. */ -#define USART_CHSIZE2_bp 2 /* Character Size bit 2 position. */ - - -/* USART.BAUDCTRLA bit masks and bit positions */ -#define USART_BSEL_gm 0xFF /* Baud Rate Selection Bits [7:0] group mask. */ -#define USART_BSEL_gp 0 /* Baud Rate Selection Bits [7:0] group position. */ -#define USART_BSEL0_bm (1<<0) /* Baud Rate Selection Bits [7:0] bit 0 mask. */ -#define USART_BSEL0_bp 0 /* Baud Rate Selection Bits [7:0] bit 0 position. */ -#define USART_BSEL1_bm (1<<1) /* Baud Rate Selection Bits [7:0] bit 1 mask. */ -#define USART_BSEL1_bp 1 /* Baud Rate Selection Bits [7:0] bit 1 position. */ -#define USART_BSEL2_bm (1<<2) /* Baud Rate Selection Bits [7:0] bit 2 mask. */ -#define USART_BSEL2_bp 2 /* Baud Rate Selection Bits [7:0] bit 2 position. */ -#define USART_BSEL3_bm (1<<3) /* Baud Rate Selection Bits [7:0] bit 3 mask. */ -#define USART_BSEL3_bp 3 /* Baud Rate Selection Bits [7:0] bit 3 position. */ -#define USART_BSEL4_bm (1<<4) /* Baud Rate Selection Bits [7:0] bit 4 mask. */ -#define USART_BSEL4_bp 4 /* Baud Rate Selection Bits [7:0] bit 4 position. */ -#define USART_BSEL5_bm (1<<5) /* Baud Rate Selection Bits [7:0] bit 5 mask. */ -#define USART_BSEL5_bp 5 /* Baud Rate Selection Bits [7:0] bit 5 position. */ -#define USART_BSEL6_bm (1<<6) /* Baud Rate Selection Bits [7:0] bit 6 mask. */ -#define USART_BSEL6_bp 6 /* Baud Rate Selection Bits [7:0] bit 6 position. */ -#define USART_BSEL7_bm (1<<7) /* Baud Rate Selection Bits [7:0] bit 7 mask. */ -#define USART_BSEL7_bp 7 /* Baud Rate Selection Bits [7:0] bit 7 position. */ - - -/* USART.BAUDCTRLB bit masks and bit positions */ -#define USART_BSCALE_gm 0xF0 /* Baud Rate Scale group mask. */ -#define USART_BSCALE_gp 4 /* Baud Rate Scale group position. */ -#define USART_BSCALE0_bm (1<<4) /* Baud Rate Scale bit 0 mask. */ -#define USART_BSCALE0_bp 4 /* Baud Rate Scale bit 0 position. */ -#define USART_BSCALE1_bm (1<<5) /* Baud Rate Scale bit 1 mask. */ -#define USART_BSCALE1_bp 5 /* Baud Rate Scale bit 1 position. */ -#define USART_BSCALE2_bm (1<<6) /* Baud Rate Scale bit 2 mask. */ -#define USART_BSCALE2_bp 6 /* Baud Rate Scale bit 2 position. */ -#define USART_BSCALE3_bm (1<<7) /* Baud Rate Scale bit 3 mask. */ -#define USART_BSCALE3_bp 7 /* Baud Rate Scale bit 3 position. */ - -/* USART_BSEL_gm Predefined. */ -/* USART_BSEL_gp Predefined. */ -/* USART_BSEL0_bm Predefined. */ -/* USART_BSEL0_bp Predefined. */ -/* USART_BSEL1_bm Predefined. */ -/* USART_BSEL1_bp Predefined. */ -/* USART_BSEL2_bm Predefined. */ -/* USART_BSEL2_bp Predefined. */ -/* USART_BSEL3_bm Predefined. */ -/* USART_BSEL3_bp Predefined. */ - - -/* SPI - Serial Peripheral Interface */ -/* SPI.CTRL bit masks and bit positions */ -#define SPI_CLK2X_bm 0x80 /* Enable Double Speed bit mask. */ -#define SPI_CLK2X_bp 7 /* Enable Double Speed bit position. */ - -#define SPI_ENABLE_bm 0x40 /* Enable Module bit mask. */ -#define SPI_ENABLE_bp 6 /* Enable Module bit position. */ - -#define SPI_DORD_bm 0x20 /* Data Order Setting bit mask. */ -#define SPI_DORD_bp 5 /* Data Order Setting bit position. */ - -#define SPI_MASTER_bm 0x10 /* Master Operation Enable bit mask. */ -#define SPI_MASTER_bp 4 /* Master Operation Enable bit position. */ - -#define SPI_MODE_gm 0x0C /* SPI Mode group mask. */ -#define SPI_MODE_gp 2 /* SPI Mode group position. */ -#define SPI_MODE0_bm (1<<2) /* SPI Mode bit 0 mask. */ -#define SPI_MODE0_bp 2 /* SPI Mode bit 0 position. */ -#define SPI_MODE1_bm (1<<3) /* SPI Mode bit 1 mask. */ -#define SPI_MODE1_bp 3 /* SPI Mode bit 1 position. */ - -#define SPI_PRESCALER_gm 0x03 /* Prescaler group mask. */ -#define SPI_PRESCALER_gp 0 /* Prescaler group position. */ -#define SPI_PRESCALER0_bm (1<<0) /* Prescaler bit 0 mask. */ -#define SPI_PRESCALER0_bp 0 /* Prescaler bit 0 position. */ -#define SPI_PRESCALER1_bm (1<<1) /* Prescaler bit 1 mask. */ -#define SPI_PRESCALER1_bp 1 /* Prescaler bit 1 position. */ - - -/* SPI.INTCTRL bit masks and bit positions */ -#define SPI_INTLVL_gm 0x03 /* Interrupt level group mask. */ -#define SPI_INTLVL_gp 0 /* Interrupt level group position. */ -#define SPI_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */ -#define SPI_INTLVL0_bp 0 /* Interrupt level bit 0 position. */ -#define SPI_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */ -#define SPI_INTLVL1_bp 1 /* Interrupt level bit 1 position. */ - - -/* SPI.STATUS bit masks and bit positions */ -#define SPI_IF_bm 0x80 /* Interrupt Flag bit mask. */ -#define SPI_IF_bp 7 /* Interrupt Flag bit position. */ - -#define SPI_WRCOL_bm 0x40 /* Write Collision bit mask. */ -#define SPI_WRCOL_bp 6 /* Write Collision bit position. */ - - -/* IRCOM - IR Communication Module */ -/* IRCOM.CTRL bit masks and bit positions */ -#define IRCOM_EVSEL_gm 0x0F /* Event Channel Select group mask. */ -#define IRCOM_EVSEL_gp 0 /* Event Channel Select group position. */ -#define IRCOM_EVSEL0_bm (1<<0) /* Event Channel Select bit 0 mask. */ -#define IRCOM_EVSEL0_bp 0 /* Event Channel Select bit 0 position. */ -#define IRCOM_EVSEL1_bm (1<<1) /* Event Channel Select bit 1 mask. */ -#define IRCOM_EVSEL1_bp 1 /* Event Channel Select bit 1 position. */ -#define IRCOM_EVSEL2_bm (1<<2) /* Event Channel Select bit 2 mask. */ -#define IRCOM_EVSEL2_bp 2 /* Event Channel Select bit 2 position. */ -#define IRCOM_EVSEL3_bm (1<<3) /* Event Channel Select bit 3 mask. */ -#define IRCOM_EVSEL3_bp 3 /* Event Channel Select bit 3 position. */ - - - -// Generic Port Pins - -#define PIN0_bm 0x01 -#define PIN0_bp 0 -#define PIN1_bm 0x02 -#define PIN1_bp 1 -#define PIN2_bm 0x04 -#define PIN2_bp 2 -#define PIN3_bm 0x08 -#define PIN3_bp 3 -#define PIN4_bm 0x10 -#define PIN4_bp 4 -#define PIN5_bm 0x20 -#define PIN5_bp 5 -#define PIN6_bm 0x40 -#define PIN6_bp 6 -#define PIN7_bm 0x80 -#define PIN7_bp 7 - - -/* ========== Interrupt Vector Definitions ========== */ -/* Vector 0 is the reset vector */ - -/* OSC interrupt vectors */ -#define OSC_XOSCF_vect_num 1 -#define OSC_XOSCF_vect _VECTOR(1) /* External Oscillator Failure Interrupt (NMI) */ - -/* PORTC interrupt vectors */ -#define PORTC_INT0_vect_num 2 -#define PORTC_INT0_vect _VECTOR(2) /* External Interrupt 0 */ -#define PORTC_INT1_vect_num 3 -#define PORTC_INT1_vect _VECTOR(3) /* External Interrupt 1 */ - -/* PORTR interrupt vectors */ -#define PORTR_INT0_vect_num 4 -#define PORTR_INT0_vect _VECTOR(4) /* External Interrupt 0 */ -#define PORTR_INT1_vect_num 5 -#define PORTR_INT1_vect _VECTOR(5) /* External Interrupt 1 */ - -/* RTC interrupt vectors */ -#define RTC_OVF_vect_num 10 -#define RTC_OVF_vect _VECTOR(10) /* Overflow Interrupt */ -#define RTC_COMP_vect_num 11 -#define RTC_COMP_vect _VECTOR(11) /* Compare Interrupt */ - -/* TWIC interrupt vectors */ -#define TWIC_TWIS_vect_num 12 -#define TWIC_TWIS_vect _VECTOR(12) /* TWI Slave Interrupt */ -#define TWIC_TWIM_vect_num 13 -#define TWIC_TWIM_vect _VECTOR(13) /* TWI Master Interrupt */ - -/* TCC0 interrupt vectors */ -#define TCC0_OVF_vect_num 14 -#define TCC0_OVF_vect _VECTOR(14) /* Overflow Interrupt */ -#define TCC0_ERR_vect_num 15 -#define TCC0_ERR_vect _VECTOR(15) /* Error Interrupt */ -#define TCC0_CCA_vect_num 16 -#define TCC0_CCA_vect _VECTOR(16) /* Compare or Capture A Interrupt */ -#define TCC0_CCB_vect_num 17 -#define TCC0_CCB_vect _VECTOR(17) /* Compare or Capture B Interrupt */ -#define TCC0_CCC_vect_num 18 -#define TCC0_CCC_vect _VECTOR(18) /* Compare or Capture C Interrupt */ -#define TCC0_CCD_vect_num 19 -#define TCC0_CCD_vect _VECTOR(19) /* Compare or Capture D Interrupt */ - -/* TCC1 interrupt vectors */ -#define TCC1_OVF_vect_num 20 -#define TCC1_OVF_vect _VECTOR(20) /* Overflow Interrupt */ -#define TCC1_ERR_vect_num 21 -#define TCC1_ERR_vect _VECTOR(21) /* Error Interrupt */ -#define TCC1_CCA_vect_num 22 -#define TCC1_CCA_vect _VECTOR(22) /* Compare or Capture A Interrupt */ -#define TCC1_CCB_vect_num 23 -#define TCC1_CCB_vect _VECTOR(23) /* Compare or Capture B Interrupt */ - -/* SPIC interrupt vectors */ -#define SPIC_INT_vect_num 24 -#define SPIC_INT_vect _VECTOR(24) /* SPI Interrupt */ - -/* USARTC0 interrupt vectors */ -#define USARTC0_RXC_vect_num 25 -#define USARTC0_RXC_vect _VECTOR(25) /* Reception Complete Interrupt */ -#define USARTC0_DRE_vect_num 26 -#define USARTC0_DRE_vect _VECTOR(26) /* Data Register Empty Interrupt */ -#define USARTC0_TXC_vect_num 27 -#define USARTC0_TXC_vect _VECTOR(27) /* Transmission Complete Interrupt */ - -/* NVM interrupt vectors */ -#define NVM_EE_vect_num 32 -#define NVM_EE_vect _VECTOR(32) /* EE Interrupt */ -#define NVM_SPM_vect_num 33 -#define NVM_SPM_vect _VECTOR(33) /* SPM Interrupt */ - -/* PORTB interrupt vectors */ -#define PORTB_INT0_vect_num 34 -#define PORTB_INT0_vect _VECTOR(34) /* External Interrupt 0 */ -#define PORTB_INT1_vect_num 35 -#define PORTB_INT1_vect _VECTOR(35) /* External Interrupt 1 */ - -/* PORTE interrupt vectors */ -#define PORTE_INT0_vect_num 43 -#define PORTE_INT0_vect _VECTOR(43) /* External Interrupt 0 */ -#define PORTE_INT1_vect_num 44 -#define PORTE_INT1_vect _VECTOR(44) /* External Interrupt 1 */ - -/* TWIE interrupt vectors */ -#define TWIE_TWIS_vect_num 45 -#define TWIE_TWIS_vect _VECTOR(45) /* TWI Slave Interrupt */ -#define TWIE_TWIM_vect_num 46 -#define TWIE_TWIM_vect _VECTOR(46) /* TWI Master Interrupt */ - -/* TCE0 interrupt vectors */ -#define TCE0_OVF_vect_num 47 -#define TCE0_OVF_vect _VECTOR(47) /* Overflow Interrupt */ -#define TCE0_ERR_vect_num 48 -#define TCE0_ERR_vect _VECTOR(48) /* Error Interrupt */ -#define TCE0_CCA_vect_num 49 -#define TCE0_CCA_vect _VECTOR(49) /* Compare or Capture A Interrupt */ -#define TCE0_CCB_vect_num 50 -#define TCE0_CCB_vect _VECTOR(50) /* Compare or Capture B Interrupt */ -#define TCE0_CCC_vect_num 51 -#define TCE0_CCC_vect _VECTOR(51) /* Compare or Capture C Interrupt */ -#define TCE0_CCD_vect_num 52 -#define TCE0_CCD_vect _VECTOR(52) /* Compare or Capture D Interrupt */ - -/* USARTE0 interrupt vectors */ -#define USARTE0_RXC_vect_num 58 -#define USARTE0_RXC_vect _VECTOR(58) /* Reception Complete Interrupt */ -#define USARTE0_DRE_vect_num 59 -#define USARTE0_DRE_vect _VECTOR(59) /* Data Register Empty Interrupt */ -#define USARTE0_TXC_vect_num 60 -#define USARTE0_TXC_vect _VECTOR(60) /* Transmission Complete Interrupt */ - -/* PORTD interrupt vectors */ -#define PORTD_INT0_vect_num 64 -#define PORTD_INT0_vect _VECTOR(64) /* External Interrupt 0 */ -#define PORTD_INT1_vect_num 65 -#define PORTD_INT1_vect _VECTOR(65) /* External Interrupt 1 */ - -/* PORTA interrupt vectors */ -#define PORTA_INT0_vect_num 66 -#define PORTA_INT0_vect _VECTOR(66) /* External Interrupt 0 */ -#define PORTA_INT1_vect_num 67 -#define PORTA_INT1_vect _VECTOR(67) /* External Interrupt 1 */ - -/* ACA interrupt vectors */ -#define ACA_AC0_vect_num 68 -#define ACA_AC0_vect _VECTOR(68) /* AC0 Interrupt */ -#define ACA_AC1_vect_num 69 -#define ACA_AC1_vect _VECTOR(69) /* AC1 Interrupt */ -#define ACA_ACW_vect_num 70 -#define ACA_ACW_vect _VECTOR(70) /* ACW Window Mode Interrupt */ - -/* ADCA interrupt vectors */ -#define ADCA_CH0_vect_num 71 -#define ADCA_CH0_vect _VECTOR(71) /* Interrupt 0 */ - -/* TCD0 interrupt vectors */ -#define TCD0_OVF_vect_num 77 -#define TCD0_OVF_vect _VECTOR(77) /* Overflow Interrupt */ -#define TCD0_ERR_vect_num 78 -#define TCD0_ERR_vect _VECTOR(78) /* Error Interrupt */ -#define TCD0_CCA_vect_num 79 -#define TCD0_CCA_vect _VECTOR(79) /* Compare or Capture A Interrupt */ -#define TCD0_CCB_vect_num 80 -#define TCD0_CCB_vect _VECTOR(80) /* Compare or Capture B Interrupt */ -#define TCD0_CCC_vect_num 81 -#define TCD0_CCC_vect _VECTOR(81) /* Compare or Capture C Interrupt */ -#define TCD0_CCD_vect_num 82 -#define TCD0_CCD_vect _VECTOR(82) /* Compare or Capture D Interrupt */ - -/* SPID interrupt vectors */ -#define SPID_INT_vect_num 87 -#define SPID_INT_vect _VECTOR(87) /* SPI Interrupt */ - -/* USARTD0 interrupt vectors */ -#define USARTD0_RXC_vect_num 88 -#define USARTD0_RXC_vect _VECTOR(88) /* Reception Complete Interrupt */ -#define USARTD0_DRE_vect_num 89 -#define USARTD0_DRE_vect _VECTOR(89) /* Data Register Empty Interrupt */ -#define USARTD0_TXC_vect_num 90 -#define USARTD0_TXC_vect _VECTOR(90) /* Transmission Complete Interrupt */ - -/* PORTF interrupt vectors */ -#define PORTF_INT0_vect_num 104 -#define PORTF_INT0_vect _VECTOR(104) /* External Interrupt 0 */ -#define PORTF_INT1_vect_num 105 -#define PORTF_INT1_vect _VECTOR(105) /* External Interrupt 1 */ - -/* TCF0 interrupt vectors */ -#define TCF0_OVF_vect_num 108 -#define TCF0_OVF_vect _VECTOR(108) /* Overflow Interrupt */ -#define TCF0_ERR_vect_num 109 -#define TCF0_ERR_vect _VECTOR(109) /* Error Interrupt */ -#define TCF0_CCA_vect_num 110 -#define TCF0_CCA_vect _VECTOR(110) /* Compare or Capture A Interrupt */ -#define TCF0_CCB_vect_num 111 -#define TCF0_CCB_vect _VECTOR(111) /* Compare or Capture B Interrupt */ -#define TCF0_CCC_vect_num 112 -#define TCF0_CCC_vect _VECTOR(112) /* Compare or Capture C Interrupt */ -#define TCF0_CCD_vect_num 113 -#define TCF0_CCD_vect _VECTOR(113) /* Compare or Capture D Interrupt */ - - -#define _VECTOR_SIZE 4 /* Size of individual vector. */ -#define _VECTORS_SIZE (114 * _VECTOR_SIZE) - - -/* ========== Constants ========== */ - -#define PROGMEM_START (0x0000) -#define PROGMEM_SIZE (139264) -#define PROGMEM_PAGE_SIZE (512) -#define PROGMEM_END (PROGMEM_START + PROGMEM_SIZE - 1) - -#define APP_SECTION_START (0x0000) -#define APP_SECTION_SIZE (131072) -#define APP_SECTION_PAGE_SIZE (512) -#define APP_SECTION_END (APP_SECTION_START + APP_SECTION_SIZE - 1) - -#define APPTABLE_SECTION_START (0x1E000) -#define APPTABLE_SECTION_SIZE (8192) -#define APPTABLE_SECTION_PAGE_SIZE (512) -#define APPTABLE_SECTION_END (APPTABLE_SECTION_START + APPTABLE_SECTION_SIZE - 1) - -#define BOOT_SECTION_START (0x20000) -#define BOOT_SECTION_SIZE (8192) -#define BOOT_SECTION_PAGE_SIZE (512) -#define BOOT_SECTION_END (BOOT_SECTION_START + BOOT_SECTION_SIZE - 1) - -#define DATAMEM_START (0x0000) -#define DATAMEM_SIZE (16384) -#define DATAMEM_PAGE_SIZE (0) -#define DATAMEM_END (DATAMEM_START + DATAMEM_SIZE - 1) - -#define IO_START (0x0000) -#define IO_SIZE (4096) -#define IO_PAGE_SIZE (0) -#define IO_END (IO_START + IO_SIZE - 1) - -#define MAPPED_EEPROM_START (0x1000) -#define MAPPED_EEPROM_SIZE (2048) -#define MAPPED_EEPROM_PAGE_SIZE (0) -#define MAPPED_EEPROM_END (MAPPED_EEPROM_START + MAPPED_EEPROM_SIZE - 1) - -#define INTERNAL_SRAM_START (0x2000) -#define INTERNAL_SRAM_SIZE (8192) -#define INTERNAL_SRAM_PAGE_SIZE (0) -#define INTERNAL_SRAM_END (INTERNAL_SRAM_START + INTERNAL_SRAM_SIZE - 1) - -#define EEPROM_START (0x0000) -#define EEPROM_SIZE (2048) -#define EEPROM_PAGE_SIZE (32) -#define EEPROM_END (EEPROM_START + EEPROM_SIZE - 1) - -#define FUSE_START (0x0000) -#define FUSE_SIZE (6) -#define FUSE_PAGE_SIZE (0) -#define FUSE_END (FUSE_START + FUSE_SIZE - 1) - -#define LOCKBIT_START (0x0000) -#define LOCKBIT_SIZE (1) -#define LOCKBIT_PAGE_SIZE (0) -#define LOCKBIT_END (LOCKBIT_START + LOCKBIT_SIZE - 1) - -#define SIGNATURES_START (0x0000) -#define SIGNATURES_SIZE (3) -#define SIGNATURES_PAGE_SIZE (0) -#define SIGNATURES_END (SIGNATURES_START + SIGNATURES_SIZE - 1) - -#define USER_SIGNATURES_START (0x0000) -#define USER_SIGNATURES_SIZE (512) -#define USER_SIGNATURES_PAGE_SIZE (0) -#define USER_SIGNATURES_END (USER_SIGNATURES_START + USER_SIGNATURES_SIZE - 1) - -#define PROD_SIGNATURES_START (0x0000) -#define PROD_SIGNATURES_SIZE (52) -#define PROD_SIGNATURES_PAGE_SIZE (0) -#define PROD_SIGNATURES_END (PROD_SIGNATURES_START + PROD_SIGNATURES_SIZE - 1) - -#define FLASHEND PROGMEM_END -#define SPM_PAGESIZE PROGMEM_PAGE_SIZE -#define RAMSTART INTERNAL_SRAM_START -#define RAMSIZE INTERNAL_SRAM_SIZE -#define RAMEND INTERNAL_SRAM_END -#define XRAMSTART EXTERNAL_SRAM_START -#define XRAMSIZE EXTERNAL_SRAM_SIZE -#define XRAMEND INTERNAL_SRAM_END -#define E2END EEPROM_END -#define E2PAGESIZE EEPROM_PAGE_SIZE - - -/* ========== Fuses ========== */ -#define FUSE_MEMORY_SIZE 6 - -/* Fuse Byte 0 */ -#define FUSE_USERID0 (unsigned char)~_BV(0) /* User ID Bit 0 */ -#define FUSE_USERID1 (unsigned char)~_BV(1) /* User ID Bit 1 */ -#define FUSE_USERID2 (unsigned char)~_BV(2) /* User ID Bit 2 */ -#define FUSE_USERID3 (unsigned char)~_BV(3) /* User ID Bit 3 */ -#define FUSE_USERID4 (unsigned char)~_BV(4) /* User ID Bit 4 */ -#define FUSE_USERID5 (unsigned char)~_BV(5) /* User ID Bit 5 */ -#define FUSE_USERID6 (unsigned char)~_BV(6) /* User ID Bit 6 */ -#define FUSE_USERID7 (unsigned char)~_BV(7) /* User ID Bit 7 */ -#define FUSE0_DEFAULT (0xFF) - -/* Fuse Byte 1 */ -#define FUSE_WDP0 (unsigned char)~_BV(0) /* Watchdog Timeout Period Bit 0 */ -#define FUSE_WDP1 (unsigned char)~_BV(1) /* Watchdog Timeout Period Bit 1 */ -#define FUSE_WDP2 (unsigned char)~_BV(2) /* Watchdog Timeout Period Bit 2 */ -#define FUSE_WDP3 (unsigned char)~_BV(3) /* Watchdog Timeout Period Bit 3 */ -#define FUSE_WDWP0 (unsigned char)~_BV(4) /* Watchdog Window Timeout Period Bit 0 */ -#define FUSE_WDWP1 (unsigned char)~_BV(5) /* Watchdog Window Timeout Period Bit 1 */ -#define FUSE_WDWP2 (unsigned char)~_BV(6) /* Watchdog Window Timeout Period Bit 2 */ -#define FUSE_WDWP3 (unsigned char)~_BV(7) /* Watchdog Window Timeout Period Bit 3 */ -#define FUSE1_DEFAULT (0xFF) - -/* Fuse Byte 2 */ -#define FUSE_BODPD0 (unsigned char)~_BV(0) /* BOD Operation in Power-Down Mode Bit 0 */ -#define FUSE_BODPD1 (unsigned char)~_BV(1) /* BOD Operation in Power-Down Mode Bit 1 */ -#define FUSE_BOOTRST (unsigned char)~_BV(6) /* Boot Loader Section Reset Vector */ -#define FUSE_DVSDON (unsigned char)~_BV(7) /* Spike Detector Enable */ -#define FUSE2_DEFAULT (0xFF) - -/* Fuse Byte 3 Reserved */ - -/* Fuse Byte 4 */ -#define FUSE_WDLOCK (unsigned char)~_BV(1) /* Watchdog Timer Lock */ -#define FUSE_SUT0 (unsigned char)~_BV(2) /* Start-up Time Bit 0 */ -#define FUSE_SUT1 (unsigned char)~_BV(3) /* Start-up Time Bit 1 */ -#define FUSE4_DEFAULT (0xFF) - -/* Fuse Byte 5 */ -#define FUSE_BODLVL0 (unsigned char)~_BV(0) /* Brown Out Detection Voltage Level Bit 0 */ -#define FUSE_BODLVL1 (unsigned char)~_BV(1) /* Brown Out Detection Voltage Level Bit 1 */ -#define FUSE_BODLVL2 (unsigned char)~_BV(2) /* Brown Out Detection Voltage Level Bit 2 */ -#define FUSE_EESAVE (unsigned char)~_BV(3) /* Preserve EEPROM Through Chip Erase */ -#define FUSE_BODACT0 (unsigned char)~_BV(4) /* BOD Operation in Active Mode Bit 0 */ -#define FUSE_BODACT1 (unsigned char)~_BV(5) /* BOD Operation in Active Mode Bit 1 */ -#define FUSE5_DEFAULT (0xFF) - - -/* ========== Lock Bits ========== */ -#define __LOCK_BITS_EXIST -#define __BOOT_LOCK_APPLICATION_TABLE_BITS_EXIST -#define __BOOT_LOCK_APPLICATION_BITS_EXIST -#define __BOOT_LOCK_BOOT_BITS_EXIST - - -/* ========== Signature ========== */ -#define SIGNATURE_0 0x1E -#define SIGNATURE_1 0x97 -#define SIGNATURE_2 0x48 - -/* ========== Power Reduction Condition Definitions ========== */ - -/* PR.PRGEN */ -#define __AVR_HAVE_PRGEN (PR_RTC_bm|PR_EVSYS_bm) -#define __AVR_HAVE_PRGEN_RTC -#define __AVR_HAVE_PRGEN_EVSYS - -/* PR.PRPA */ -#define __AVR_HAVE_PRPA (PR_ADC_bm|PR_AC_bm) -#define __AVR_HAVE_PRPA_ADC -#define __AVR_HAVE_PRPA_AC - -/* PR.PRPC */ -#define __AVR_HAVE_PRPC (PR_TWI_bm|PR_USART0_bm|PR_SPI_bm|PR_HIRES_bm|PR_TC1_bm|PR_TC0_bm) -#define __AVR_HAVE_PRPC_TWI -#define __AVR_HAVE_PRPC_USART0 -#define __AVR_HAVE_PRPC_SPI -#define __AVR_HAVE_PRPC_HIRES -#define __AVR_HAVE_PRPC_TC1 -#define __AVR_HAVE_PRPC_TC0 - -/* PR.PRPD */ -#define __AVR_HAVE_PRPD (PR_USART0_bm|PR_SPI_bm|PR_TC0_bm) -#define __AVR_HAVE_PRPD_USART0 -#define __AVR_HAVE_PRPD_SPI -#define __AVR_HAVE_PRPD_TC0 - -/* PR.PRPE */ -#define __AVR_HAVE_PRPE (PR_TWI_bm|PR_USART0_bm|PR_TC0_bm) -#define __AVR_HAVE_PRPE_TWI -#define __AVR_HAVE_PRPE_USART0 -#define __AVR_HAVE_PRPE_TC0 - -/* PR.PRPF */ -#define __AVR_HAVE_PRPF (PR_USART0_bm|PR_TC0_bm) -#define __AVR_HAVE_PRPF_USART0 -#define __AVR_HAVE_PRPF_TC0 - - -#endif /* _AVR_ATxmega128D3_H_ */ - diff --git a/arduino/hardware/tools/avr/avr/include/avr/iox128d4.h b/arduino/hardware/tools/avr/avr/include/avr/iox128d4.h deleted file mode 100644 index 0d818f7..0000000 --- a/arduino/hardware/tools/avr/avr/include/avr/iox128d4.h +++ /dev/null @@ -1,5562 +0,0 @@ -/***************************************************************************** - * - * Copyright (C) 2015 Atmel Corporation - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * - * * Neither the name of the copyright holders nor the names of - * contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - ****************************************************************************/ - - -#ifndef _AVR_IO_H_ -# error "Include instead of this file." -#endif - -#ifndef _AVR_IOXXX_H_ -# define _AVR_IOXXX_H_ "iox128d4.h" -#else -# error "Attempt to include more than one file." -#endif - -#ifndef _AVR_ATXMEGA128D4_H_INCLUDED -#define _AVR_ATXMEGA128D4_H_INCLUDED - -/* Ungrouped common registers */ -#define GPIOR0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ -#define GPIOR1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ -#define GPIOR2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ -#define GPIOR3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ - -/* Deprecated */ -#define GPIO0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ -#define GPIO1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ -#define GPIO2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ -#define GPIO3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ - -#define CCP _SFR_MEM8(0x0034) /* Configuration Change Protection */ -#define RAMPD _SFR_MEM8(0x0038) /* Ramp D */ -#define RAMPX _SFR_MEM8(0x0039) /* Ramp X */ -#define RAMPY _SFR_MEM8(0x003A) /* Ramp Y */ -#define RAMPZ _SFR_MEM8(0x003B) /* Ramp Z */ -#define EIND _SFR_MEM8(0x003C) /* Extended Indirect Jump */ -#define SPL _SFR_MEM8(0x003D) /* Stack Pointer Low */ -#define SPH _SFR_MEM8(0x003E) /* Stack Pointer High */ -#define SREG _SFR_MEM8(0x003F) /* Status Register */ - -/* C Language Only */ -#if !defined (__ASSEMBLER__) - -#include - -typedef volatile uint8_t register8_t; -typedef volatile uint16_t register16_t; -typedef volatile uint32_t register32_t; - - -#ifdef _WORDREGISTER -#undef _WORDREGISTER -#endif -#define _WORDREGISTER(regname) \ - __extension__ union \ - { \ - register16_t regname; \ - struct \ - { \ - register8_t regname ## L; \ - register8_t regname ## H; \ - }; \ - } - -#ifdef _DWORDREGISTER -#undef _DWORDREGISTER -#endif -#define _DWORDREGISTER(regname) \ - __extension__ union \ - { \ - register32_t regname; \ - struct \ - { \ - register8_t regname ## 0; \ - register8_t regname ## 1; \ - register8_t regname ## 2; \ - register8_t regname ## 3; \ - }; \ - } - - -/* -========================================================================== -IO Module Structures -========================================================================== -*/ - - -/* --------------------------------------------------------------------------- -VPORT - Virtual Ports --------------------------------------------------------------------------- -*/ - -/* Virtual Port */ -typedef struct VPORT_struct -{ - register8_t DIR; /* I/O Port Data Direction */ - register8_t OUT; /* I/O Port Output */ - register8_t IN; /* I/O Port Input */ - register8_t INTFLAGS; /* Interrupt Flag Register */ -} VPORT_t; - - -/* --------------------------------------------------------------------------- -XOCD - On-Chip Debug System --------------------------------------------------------------------------- -*/ - -/* On-Chip Debug System */ -typedef struct OCD_struct -{ - register8_t OCDR0; /* OCD Register 0 */ - register8_t OCDR1; /* OCD Register 1 */ -} OCD_t; - - -/* --------------------------------------------------------------------------- -CPU - CPU --------------------------------------------------------------------------- -*/ - -/* CCP signatures */ -typedef enum CCP_enum -{ - CCP_SPM_gc = (0x9D<<0), /* SPM Instruction Protection */ - CCP_IOREG_gc = (0xD8<<0), /* IO Register Protection */ -} CCP_t; - - -/* --------------------------------------------------------------------------- -CLK - Clock System --------------------------------------------------------------------------- -*/ - -/* Clock System */ -typedef struct CLK_struct -{ - register8_t CTRL; /* Control Register */ - register8_t PSCTRL; /* Prescaler Control Register */ - register8_t LOCK; /* Lock register */ - register8_t RTCCTRL; /* RTC Control Register */ - register8_t reserved_0x04; -} CLK_t; - - -/* Power Reduction */ -typedef struct PR_struct -{ - register8_t PRGEN; /* General Power Reduction */ - register8_t PRPA; /* Power Reduction Port A */ - register8_t reserved_0x02; - register8_t PRPC; /* Power Reduction Port C */ - register8_t PRPD; /* Power Reduction Port D */ - register8_t PRPE; /* Power Reduction Port E */ - register8_t PRPF; /* Power Reduction Port F */ -} PR_t; - -/* System Clock Selection */ -typedef enum CLK_SCLKSEL_enum -{ - CLK_SCLKSEL_RC2M_gc = (0x00<<0), /* Internal 2 MHz RC Oscillator */ - CLK_SCLKSEL_RC32M_gc = (0x01<<0), /* Internal 32 MHz RC Oscillator */ - CLK_SCLKSEL_RC32K_gc = (0x02<<0), /* Internal 32.768 kHz RC Oscillator */ - CLK_SCLKSEL_XOSC_gc = (0x03<<0), /* External Crystal Oscillator or Clock */ - CLK_SCLKSEL_PLL_gc = (0x04<<0), /* Phase Locked Loop */ -} CLK_SCLKSEL_t; - -/* Prescaler A Division Factor */ -typedef enum CLK_PSADIV_enum -{ - CLK_PSADIV_1_gc = (0x00<<2), /* Divide by 1 */ - CLK_PSADIV_2_gc = (0x01<<2), /* Divide by 2 */ - CLK_PSADIV_4_gc = (0x03<<2), /* Divide by 4 */ - CLK_PSADIV_8_gc = (0x05<<2), /* Divide by 8 */ - CLK_PSADIV_16_gc = (0x07<<2), /* Divide by 16 */ - CLK_PSADIV_32_gc = (0x09<<2), /* Divide by 32 */ - CLK_PSADIV_64_gc = (0x0B<<2), /* Divide by 64 */ - CLK_PSADIV_128_gc = (0x0D<<2), /* Divide by 128 */ - CLK_PSADIV_256_gc = (0x0F<<2), /* Divide by 256 */ - CLK_PSADIV_512_gc = (0x11<<2), /* Divide by 512 */ -} CLK_PSADIV_t; - -/* Prescaler B and C Division Factor */ -typedef enum CLK_PSBCDIV_enum -{ - CLK_PSBCDIV_1_1_gc = (0x00<<0), /* Divide B by 1 and C by 1 */ - CLK_PSBCDIV_1_2_gc = (0x01<<0), /* Divide B by 1 and C by 2 */ - CLK_PSBCDIV_4_1_gc = (0x02<<0), /* Divide B by 4 and C by 1 */ - CLK_PSBCDIV_2_2_gc = (0x03<<0), /* Divide B by 2 and C by 2 */ -} CLK_PSBCDIV_t; - -/* RTC Clock Source */ -typedef enum CLK_RTCSRC_enum -{ - CLK_RTCSRC_ULP_gc = (0x00<<1), /* 1 kHz from internal 32kHz ULP */ - CLK_RTCSRC_TOSC_gc = (0x01<<1), /* 1.024 kHz from 32.768 kHz crystal oscillator on TOSC */ - CLK_RTCSRC_RCOSC_gc = (0x02<<1), /* 1.024 kHz from 32.768 kHz internal oscillator */ - CLK_RTCSRC_TOSC32_gc = (0x05<<1), /* 32.768 kHz from 32.768 kHz crystal oscillator on TOSC */ - CLK_RTCSRC_RCOSC32_gc = (0x06<<1), /* 32.768 kHz from 32.768 kHz internal oscillator */ - CLK_RTCSRC_EXTCLK_gc = (0x07<<1), /* External Clock from TOSC1 */ -} CLK_RTCSRC_t; - - -/* --------------------------------------------------------------------------- -SLEEP - Sleep Controller --------------------------------------------------------------------------- -*/ - -/* Sleep Controller */ -typedef struct SLEEP_struct -{ - register8_t CTRL; /* Control Register */ -} SLEEP_t; - -/* Sleep Mode */ -typedef enum SLEEP_SMODE_enum -{ - SLEEP_SMODE_IDLE_gc = (0x00<<1), /* Idle mode */ - SLEEP_SMODE_PDOWN_gc = (0x02<<1), /* Power-down Mode */ - SLEEP_SMODE_PSAVE_gc = (0x03<<1), /* Power-save Mode */ - SLEEP_SMODE_STDBY_gc = (0x06<<1), /* Standby Mode */ - SLEEP_SMODE_ESTDBY_gc = (0x07<<1), /* Extended Standby Mode */ -} SLEEP_SMODE_t; - - - -#define SLEEP_MODE_IDLE (0x00<<1) -#define SLEEP_MODE_PWR_DOWN (0x02<<1) -#define SLEEP_MODE_PWR_SAVE (0x03<<1) -#define SLEEP_MODE_STANDBY (0x06<<1) -#define SLEEP_MODE_EXT_STANDBY (0x07<<1) -/* --------------------------------------------------------------------------- -OSC - Oscillator --------------------------------------------------------------------------- -*/ - -/* Oscillator */ -typedef struct OSC_struct -{ - register8_t CTRL; /* Control Register */ - register8_t STATUS; /* Status Register */ - register8_t XOSCCTRL; /* External Oscillator Control Register */ - register8_t XOSCFAIL; /* Oscillator Failure Detection Register */ - register8_t RC32KCAL; /* 32.768 kHz Internal Oscillator Calibration Register */ - register8_t PLLCTRL; /* PLL Control Register */ - register8_t DFLLCTRL; /* DFLL Control Register */ -} OSC_t; - -/* Oscillator Frequency Range */ -typedef enum OSC_FRQRANGE_enum -{ - OSC_FRQRANGE_04TO2_gc = (0x00<<6), /* 0.4 - 2 MHz */ - OSC_FRQRANGE_2TO9_gc = (0x01<<6), /* 2 - 9 MHz */ - OSC_FRQRANGE_9TO12_gc = (0x02<<6), /* 9 - 12 MHz */ - OSC_FRQRANGE_12TO16_gc = (0x03<<6), /* 12 - 16 MHz */ -} OSC_FRQRANGE_t; - -/* External Oscillator Selection and Startup Time */ -typedef enum OSC_XOSCSEL_enum -{ - OSC_XOSCSEL_EXTCLK_gc = (0x00<<0), /* External Clock - 6 CLK */ - OSC_XOSCSEL_32KHz_gc = (0x02<<0), /* 32.768 kHz TOSC - 32K CLK */ - OSC_XOSCSEL_XTAL_256CLK_gc = (0x03<<0), /* 0.4-16 MHz XTAL - 256 CLK */ - OSC_XOSCSEL_XTAL_1KCLK_gc = (0x07<<0), /* 0.4-16 MHz XTAL - 1K CLK */ - OSC_XOSCSEL_XTAL_16KCLK_gc = (0x0B<<0), /* 0.4-16 MHz XTAL - 16K CLK */ -} OSC_XOSCSEL_t; - -/* PLL Clock Source */ -typedef enum OSC_PLLSRC_enum -{ - OSC_PLLSRC_RC2M_gc = (0x00<<6), /* Internal 2 MHz RC Oscillator */ - OSC_PLLSRC_RC32M_gc = (0x02<<6), /* Internal 32 MHz RC Oscillator */ - OSC_PLLSRC_XOSC_gc = (0x03<<6), /* External Oscillator */ -} OSC_PLLSRC_t; - -/* 2 MHz DFLL Calibration Reference */ -typedef enum OSC_RC2MCREF_enum -{ - OSC_RC2MCREF_RC32K_gc = (0x00<<0), /* Internal 32.768 kHz RC Oscillator */ - OSC_RC2MCREF_XOSC32K_gc = (0x01<<0), /* External 32.768 kHz Crystal Oscillator */ -} OSC_RC2MCREF_t; - -/* 32 MHz DFLL Calibration Reference */ -typedef enum OSC_RC32MCREF_enum -{ - OSC_RC32MCREF_RC32K_gc = (0x00<<1), /* Internal 32.768 kHz RC Oscillator */ - OSC_RC32MCREF_XOSC32K_gc = (0x01<<1), /* External 32.768 kHz Crystal Oscillator */ -} OSC_RC32MCREF_t; - - -/* --------------------------------------------------------------------------- -DFLL - DFLL --------------------------------------------------------------------------- -*/ - -/* DFLL */ -typedef struct DFLL_struct -{ - register8_t CTRL; /* Control Register */ - register8_t reserved_0x01; - register8_t CALA; /* Calibration Register A */ - register8_t CALB; /* Calibration Register B */ - register8_t COMP0; /* Oscillator Compare Register 0 */ - register8_t COMP1; /* Oscillator Compare Register 1 */ - register8_t COMP2; /* Oscillator Compare Register 2 */ - register8_t reserved_0x07; -} DFLL_t; - - -/* --------------------------------------------------------------------------- -RST - Reset --------------------------------------------------------------------------- -*/ - -/* Reset */ -typedef struct RST_struct -{ - register8_t STATUS; /* Status Register */ - register8_t CTRL; /* Control Register */ -} RST_t; - - -/* --------------------------------------------------------------------------- -WDT - Watch-Dog Timer --------------------------------------------------------------------------- -*/ - -/* Watch-Dog Timer */ -typedef struct WDT_struct -{ - register8_t CTRL; /* Control */ - register8_t WINCTRL; /* Windowed Mode Control */ - register8_t STATUS; /* Status */ -} WDT_t; - -/* Period setting */ -typedef enum WDT_PER_enum -{ - WDT_PER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ - WDT_PER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ - WDT_PER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ - WDT_PER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ - WDT_PER_128CLK_gc = (0x04<<2), /* 128 cycles (0.128s @ 3.3V) */ - WDT_PER_256CLK_gc = (0x05<<2), /* 256 cycles (0.256s @ 3.3V) */ - WDT_PER_512CLK_gc = (0x06<<2), /* 512 cycles (0.512s @ 3.3V) */ - WDT_PER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ - WDT_PER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ - WDT_PER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ - WDT_PER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ -} WDT_PER_t; - -/* Closed window period */ -typedef enum WDT_WPER_enum -{ - WDT_WPER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ - WDT_WPER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ - WDT_WPER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ - WDT_WPER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ - WDT_WPER_128CLK_gc = (0x04<<2), /* 128 cycles (0.128s @ 3.3V) */ - WDT_WPER_256CLK_gc = (0x05<<2), /* 256 cycles (0.256s @ 3.3V) */ - WDT_WPER_512CLK_gc = (0x06<<2), /* 512 cycles (0.512s @ 3.3V) */ - WDT_WPER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ - WDT_WPER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ - WDT_WPER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ - WDT_WPER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ -} WDT_WPER_t; - - -/* --------------------------------------------------------------------------- -MCU - MCU Control --------------------------------------------------------------------------- -*/ - -/* MCU Control */ -typedef struct MCU_struct -{ - register8_t DEVID0; /* Device ID byte 0 */ - register8_t DEVID1; /* Device ID byte 1 */ - register8_t DEVID2; /* Device ID byte 2 */ - register8_t REVID; /* Revision ID */ - register8_t reserved_0x04; - register8_t reserved_0x05; - register8_t reserved_0x06; - register8_t ANAINIT; /* Analog Startup Delay */ - register8_t EVSYSLOCK; /* Event System Lock */ - register8_t AWEXLOCK; /* AWEX Lock */ - register8_t reserved_0x0A; - register8_t reserved_0x0B; -} MCU_t; - - -/* --------------------------------------------------------------------------- -PMIC - Programmable Multi-level Interrupt Controller --------------------------------------------------------------------------- -*/ - -/* Programmable Multi-level Interrupt Controller */ -typedef struct PMIC_struct -{ - register8_t STATUS; /* Status Register */ - register8_t INTPRI; /* Interrupt Priority */ - register8_t CTRL; /* Control Register */ - register8_t reserved_0x03; - register8_t reserved_0x04; - register8_t reserved_0x05; - register8_t reserved_0x06; - register8_t reserved_0x07; - register8_t reserved_0x08; - register8_t reserved_0x09; - register8_t reserved_0x0A; - register8_t reserved_0x0B; - register8_t reserved_0x0C; - register8_t reserved_0x0D; - register8_t reserved_0x0E; - register8_t reserved_0x0F; -} PMIC_t; - - -/* --------------------------------------------------------------------------- -PORTCFG - Port Configuration --------------------------------------------------------------------------- -*/ - -/* I/O port Configuration */ -typedef struct PORTCFG_struct -{ - register8_t MPCMASK; /* Multi-pin Configuration Mask */ - register8_t reserved_0x01; - register8_t VPCTRLA; /* Virtual Port Control Register A */ - register8_t VPCTRLB; /* Virtual Port Control Register B */ - register8_t CLKEVOUT; /* Clock and Event Out Register */ - register8_t reserved_0x05; - register8_t EVOUTSEL; /* Event Output Select */ -} PORTCFG_t; - -/* Virtual Port Mapping */ -typedef enum PORTCFG_VP02MAP_enum -{ - PORTCFG_VP02MAP_PORTA_gc = (0x00<<0), /* Mapped To PORTA */ - PORTCFG_VP02MAP_PORTB_gc = (0x01<<0), /* Mapped To PORTB */ - PORTCFG_VP02MAP_PORTC_gc = (0x02<<0), /* Mapped To PORTC */ - PORTCFG_VP02MAP_PORTD_gc = (0x03<<0), /* Mapped To PORTD */ - PORTCFG_VP02MAP_PORTE_gc = (0x04<<0), /* Mapped To PORTE */ - PORTCFG_VP02MAP_PORTF_gc = (0x05<<0), /* Mapped To PORTF */ - PORTCFG_VP02MAP_PORTG_gc = (0x06<<0), /* Mapped To PORTG */ - PORTCFG_VP02MAP_PORTH_gc = (0x07<<0), /* Mapped To PORTH */ - PORTCFG_VP02MAP_PORTJ_gc = (0x08<<0), /* Mapped To PORTJ */ - PORTCFG_VP02MAP_PORTK_gc = (0x09<<0), /* Mapped To PORTK */ - PORTCFG_VP02MAP_PORTL_gc = (0x0A<<0), /* Mapped To PORTL */ - PORTCFG_VP02MAP_PORTM_gc = (0x0B<<0), /* Mapped To PORTM */ - PORTCFG_VP02MAP_PORTN_gc = (0x0C<<0), /* Mapped To PORTN */ - PORTCFG_VP02MAP_PORTP_gc = (0x0D<<0), /* Mapped To PORTP */ - PORTCFG_VP02MAP_PORTQ_gc = (0x0E<<0), /* Mapped To PORTQ */ - PORTCFG_VP02MAP_PORTR_gc = (0x0F<<0), /* Mapped To PORTR */ -} PORTCFG_VP02MAP_t; - -/* Virtual Port Mapping */ -typedef enum PORTCFG_VP13MAP_enum -{ - PORTCFG_VP13MAP_PORTA_gc = (0x00<<4), /* Mapped To PORTA */ - PORTCFG_VP13MAP_PORTB_gc = (0x01<<4), /* Mapped To PORTB */ - PORTCFG_VP13MAP_PORTC_gc = (0x02<<4), /* Mapped To PORTC */ - PORTCFG_VP13MAP_PORTD_gc = (0x03<<4), /* Mapped To PORTD */ - PORTCFG_VP13MAP_PORTE_gc = (0x04<<4), /* Mapped To PORTE */ - PORTCFG_VP13MAP_PORTF_gc = (0x05<<4), /* Mapped To PORTF */ - PORTCFG_VP13MAP_PORTG_gc = (0x06<<4), /* Mapped To PORTG */ - PORTCFG_VP13MAP_PORTH_gc = (0x07<<4), /* Mapped To PORTH */ - PORTCFG_VP13MAP_PORTJ_gc = (0x08<<4), /* Mapped To PORTJ */ - PORTCFG_VP13MAP_PORTK_gc = (0x09<<4), /* Mapped To PORTK */ - PORTCFG_VP13MAP_PORTL_gc = (0x0A<<4), /* Mapped To PORTL */ - PORTCFG_VP13MAP_PORTM_gc = (0x0B<<4), /* Mapped To PORTM */ - PORTCFG_VP13MAP_PORTN_gc = (0x0C<<4), /* Mapped To PORTN */ - PORTCFG_VP13MAP_PORTP_gc = (0x0D<<4), /* Mapped To PORTP */ - PORTCFG_VP13MAP_PORTQ_gc = (0x0E<<4), /* Mapped To PORTQ */ - PORTCFG_VP13MAP_PORTR_gc = (0x0F<<4), /* Mapped To PORTR */ -} PORTCFG_VP13MAP_t; - -/* System Clock Output Port */ -typedef enum PORTCFG_CLKOUT_enum -{ - PORTCFG_CLKOUT_OFF_gc = (0x00<<0), /* System Clock Output Disabled */ - PORTCFG_CLKOUT_PC7_gc = (0x01<<0), /* System Clock Output on Port C pin 7 */ - PORTCFG_CLKOUT_PD7_gc = (0x02<<0), /* System Clock Output on Port D pin 7 */ - PORTCFG_CLKOUT_PE7_gc = (0x03<<0), /* System Clock Output on Port E pin 7 */ -} PORTCFG_CLKOUT_t; - -/* Peripheral Clock Output Select */ -typedef enum PORTCFG_CLKOUTSEL_enum -{ - PORTCFG_CLKOUTSEL_CLK1X_gc = (0x00<<2), /* 1x Peripheral Clock Output to pin */ - PORTCFG_CLKOUTSEL_CLK2X_gc = (0x01<<2), /* 2x Peripheral Clock Output to pin */ - PORTCFG_CLKOUTSEL_CLK4X_gc = (0x02<<2), /* 4x Peripheral Clock Output to pin */ -} PORTCFG_CLKOUTSEL_t; - -/* Event Output Port */ -typedef enum PORTCFG_EVOUT_enum -{ - PORTCFG_EVOUT_OFF_gc = (0x00<<4), /* Event Output Disabled */ - PORTCFG_EVOUT_PC7_gc = (0x01<<4), /* Event Channel 7 Output on Port C pin 7 */ - PORTCFG_EVOUT_PD7_gc = (0x02<<4), /* Event Channel 7 Output on Port D pin 7 */ - PORTCFG_EVOUT_PE7_gc = (0x03<<4), /* Event Channel 7 Output on Port E pin 7 */ -} PORTCFG_EVOUT_t; - -/* Event Output Select */ -typedef enum PORTCFG_EVOUTSEL_enum -{ - PORTCFG_EVOUTSEL_0_gc = (0x00<<0), /* Event Channel 0 output to pin */ - PORTCFG_EVOUTSEL_1_gc = (0x01<<0), /* Event Channel 1 output to pin */ - PORTCFG_EVOUTSEL_2_gc = (0x02<<0), /* Event Channel 2 output to pin */ - PORTCFG_EVOUTSEL_3_gc = (0x03<<0), /* Event Channel 3 output to pin */ -} PORTCFG_EVOUTSEL_t; - - -/* --------------------------------------------------------------------------- -CRC - Cyclic Redundancy Checker --------------------------------------------------------------------------- -*/ - -/* Cyclic Redundancy Checker */ -typedef struct CRC_struct -{ - register8_t CTRL; /* Control Register */ - register8_t STATUS; /* Status Register */ - register8_t reserved_0x02; - register8_t DATAIN; /* Data Input */ - register8_t CHECKSUM0; /* Checksum byte 0 */ - register8_t CHECKSUM1; /* Checksum byte 1 */ - register8_t CHECKSUM2; /* Checksum byte 2 */ - register8_t CHECKSUM3; /* Checksum byte 3 */ -} CRC_t; - -/* Reset */ -typedef enum CRC_RESET_enum -{ - CRC_RESET_NO_gc = (0x00<<6), /* No Reset */ - CRC_RESET_RESET0_gc = (0x02<<6), /* Reset CRC with CHECKSUM to all zeros */ - CRC_RESET_RESET1_gc = (0x03<<6), /* Reset CRC with CHECKSUM to all ones */ -} CRC_RESET_t; - -/* Input Source */ -typedef enum CRC_SOURCE_enum -{ - CRC_SOURCE_DISABLE_gc = (0x00<<0), /* Disabled */ - CRC_SOURCE_IO_gc = (0x01<<0), /* I/O Interface */ - CRC_SOURCE_FLASH_gc = (0x02<<0), /* Flash */ -} CRC_SOURCE_t; - - -/* --------------------------------------------------------------------------- -EVSYS - Event System --------------------------------------------------------------------------- -*/ - -/* Event System */ -typedef struct EVSYS_struct -{ - register8_t CH0MUX; /* Event Channel 0 Multiplexer */ - register8_t CH1MUX; /* Event Channel 1 Multiplexer */ - register8_t CH2MUX; /* Event Channel 2 Multiplexer */ - register8_t CH3MUX; /* Event Channel 3 Multiplexer */ - register8_t reserved_0x04; - register8_t reserved_0x05; - register8_t reserved_0x06; - register8_t reserved_0x07; - register8_t CH0CTRL; /* Channel 0 Control Register */ - register8_t CH1CTRL; /* Channel 1 Control Register */ - register8_t CH2CTRL; /* Channel 2 Control Register */ - register8_t CH3CTRL; /* Channel 3 Control Register */ - register8_t reserved_0x0C; - register8_t reserved_0x0D; - register8_t reserved_0x0E; - register8_t reserved_0x0F; - register8_t STROBE; /* Event Strobe */ - register8_t DATA; /* Event Data */ -} EVSYS_t; - -/* Quadrature Decoder Index Recognition Mode */ -typedef enum EVSYS_QDIRM_enum -{ - EVSYS_QDIRM_00_gc = (0x00<<5), /* QDPH0 = 0, QDPH90 = 0 */ - EVSYS_QDIRM_01_gc = (0x01<<5), /* QDPH0 = 0, QDPH90 = 1 */ - EVSYS_QDIRM_10_gc = (0x02<<5), /* QDPH0 = 1, QDPH90 = 0 */ - EVSYS_QDIRM_11_gc = (0x03<<5), /* QDPH0 = 1, QDPH90 = 1 */ -} EVSYS_QDIRM_t; - -/* Digital filter coefficient */ -typedef enum EVSYS_DIGFILT_enum -{ - EVSYS_DIGFILT_1SAMPLE_gc = (0x00<<0), /* 1 SAMPLE */ - EVSYS_DIGFILT_2SAMPLES_gc = (0x01<<0), /* 2 SAMPLES */ - EVSYS_DIGFILT_3SAMPLES_gc = (0x02<<0), /* 3 SAMPLES */ - EVSYS_DIGFILT_4SAMPLES_gc = (0x03<<0), /* 4 SAMPLES */ - EVSYS_DIGFILT_5SAMPLES_gc = (0x04<<0), /* 5 SAMPLES */ - EVSYS_DIGFILT_6SAMPLES_gc = (0x05<<0), /* 6 SAMPLES */ - EVSYS_DIGFILT_7SAMPLES_gc = (0x06<<0), /* 7 SAMPLES */ - EVSYS_DIGFILT_8SAMPLES_gc = (0x07<<0), /* 8 SAMPLES */ -} EVSYS_DIGFILT_t; - -/* Event Channel multiplexer input selection */ -typedef enum EVSYS_CHMUX_enum -{ - EVSYS_CHMUX_OFF_gc = (0x00<<0), /* Off */ - EVSYS_CHMUX_RTC_OVF_gc = (0x08<<0), /* RTC Overflow */ - EVSYS_CHMUX_RTC_CMP_gc = (0x09<<0), /* RTC Compare Match */ - EVSYS_CHMUX_ACA_CH0_gc = (0x10<<0), /* Analog Comparator A Channel 0 */ - EVSYS_CHMUX_ACA_CH1_gc = (0x11<<0), /* Analog Comparator A Channel 1 */ - EVSYS_CHMUX_ACA_WIN_gc = (0x12<<0), /* Analog Comparator A Window */ - EVSYS_CHMUX_ADCA_CH0_gc = (0x20<<0), /* ADC A Channel 0 */ - EVSYS_CHMUX_PORTA_PIN0_gc = (0x50<<0), /* Port A, Pin0 */ - EVSYS_CHMUX_PORTA_PIN1_gc = (0x51<<0), /* Port A, Pin1 */ - EVSYS_CHMUX_PORTA_PIN2_gc = (0x52<<0), /* Port A, Pin2 */ - EVSYS_CHMUX_PORTA_PIN3_gc = (0x53<<0), /* Port A, Pin3 */ - EVSYS_CHMUX_PORTA_PIN4_gc = (0x54<<0), /* Port A, Pin4 */ - EVSYS_CHMUX_PORTA_PIN5_gc = (0x55<<0), /* Port A, Pin5 */ - EVSYS_CHMUX_PORTA_PIN6_gc = (0x56<<0), /* Port A, Pin6 */ - EVSYS_CHMUX_PORTA_PIN7_gc = (0x57<<0), /* Port A, Pin7 */ - EVSYS_CHMUX_PORTB_PIN0_gc = (0x58<<0), /* Port B, Pin0 */ - EVSYS_CHMUX_PORTB_PIN1_gc = (0x59<<0), /* Port B, Pin1 */ - EVSYS_CHMUX_PORTB_PIN2_gc = (0x5A<<0), /* Port B, Pin2 */ - EVSYS_CHMUX_PORTB_PIN3_gc = (0x5B<<0), /* Port B, Pin3 */ - EVSYS_CHMUX_PORTB_PIN4_gc = (0x5C<<0), /* Port B, Pin4 */ - EVSYS_CHMUX_PORTB_PIN5_gc = (0x5D<<0), /* Port B, Pin5 */ - EVSYS_CHMUX_PORTB_PIN6_gc = (0x5E<<0), /* Port B, Pin6 */ - EVSYS_CHMUX_PORTB_PIN7_gc = (0x5F<<0), /* Port B, Pin7 */ - EVSYS_CHMUX_PORTC_PIN0_gc = (0x60<<0), /* Port C, Pin0 */ - EVSYS_CHMUX_PORTC_PIN1_gc = (0x61<<0), /* Port C, Pin1 */ - EVSYS_CHMUX_PORTC_PIN2_gc = (0x62<<0), /* Port C, Pin2 */ - EVSYS_CHMUX_PORTC_PIN3_gc = (0x63<<0), /* Port C, Pin3 */ - EVSYS_CHMUX_PORTC_PIN4_gc = (0x64<<0), /* Port C, Pin4 */ - EVSYS_CHMUX_PORTC_PIN5_gc = (0x65<<0), /* Port C, Pin5 */ - EVSYS_CHMUX_PORTC_PIN6_gc = (0x66<<0), /* Port C, Pin6 */ - EVSYS_CHMUX_PORTC_PIN7_gc = (0x67<<0), /* Port C, Pin7 */ - EVSYS_CHMUX_PORTD_PIN0_gc = (0x68<<0), /* Port D, Pin0 */ - EVSYS_CHMUX_PORTD_PIN1_gc = (0x69<<0), /* Port D, Pin1 */ - EVSYS_CHMUX_PORTD_PIN2_gc = (0x6A<<0), /* Port D, Pin2 */ - EVSYS_CHMUX_PORTD_PIN3_gc = (0x6B<<0), /* Port D, Pin3 */ - EVSYS_CHMUX_PORTD_PIN4_gc = (0x6C<<0), /* Port D, Pin4 */ - EVSYS_CHMUX_PORTD_PIN5_gc = (0x6D<<0), /* Port D, Pin5 */ - EVSYS_CHMUX_PORTD_PIN6_gc = (0x6E<<0), /* Port D, Pin6 */ - EVSYS_CHMUX_PORTD_PIN7_gc = (0x6F<<0), /* Port D, Pin7 */ - EVSYS_CHMUX_PORTE_PIN0_gc = (0x70<<0), /* Port E, Pin0 */ - EVSYS_CHMUX_PORTE_PIN1_gc = (0x71<<0), /* Port E, Pin1 */ - EVSYS_CHMUX_PORTE_PIN2_gc = (0x72<<0), /* Port E, Pin2 */ - EVSYS_CHMUX_PORTE_PIN3_gc = (0x73<<0), /* Port E, Pin3 */ - EVSYS_CHMUX_PORTE_PIN4_gc = (0x74<<0), /* Port E, Pin4 */ - EVSYS_CHMUX_PORTE_PIN5_gc = (0x75<<0), /* Port E, Pin5 */ - EVSYS_CHMUX_PORTE_PIN6_gc = (0x76<<0), /* Port E, Pin6 */ - EVSYS_CHMUX_PORTE_PIN7_gc = (0x77<<0), /* Port E, Pin7 */ - EVSYS_CHMUX_PORTF_PIN0_gc = (0x78<<0), /* Port F, Pin0 */ - EVSYS_CHMUX_PORTF_PIN1_gc = (0x79<<0), /* Port F, Pin1 */ - EVSYS_CHMUX_PORTF_PIN2_gc = (0x7A<<0), /* Port F, Pin2 */ - EVSYS_CHMUX_PORTF_PIN3_gc = (0x7B<<0), /* Port F, Pin3 */ - EVSYS_CHMUX_PORTF_PIN4_gc = (0x7C<<0), /* Port F, Pin4 */ - EVSYS_CHMUX_PORTF_PIN5_gc = (0x7D<<0), /* Port F, Pin5 */ - EVSYS_CHMUX_PORTF_PIN6_gc = (0x7E<<0), /* Port F, Pin6 */ - EVSYS_CHMUX_PORTF_PIN7_gc = (0x7F<<0), /* Port F, Pin7 */ - EVSYS_CHMUX_PRESCALER_1_gc = (0x80<<0), /* Prescaler, divide by 1 */ - EVSYS_CHMUX_PRESCALER_2_gc = (0x81<<0), /* Prescaler, divide by 2 */ - EVSYS_CHMUX_PRESCALER_4_gc = (0x82<<0), /* Prescaler, divide by 4 */ - EVSYS_CHMUX_PRESCALER_8_gc = (0x83<<0), /* Prescaler, divide by 8 */ - EVSYS_CHMUX_PRESCALER_16_gc = (0x84<<0), /* Prescaler, divide by 16 */ - EVSYS_CHMUX_PRESCALER_32_gc = (0x85<<0), /* Prescaler, divide by 32 */ - EVSYS_CHMUX_PRESCALER_64_gc = (0x86<<0), /* Prescaler, divide by 64 */ - EVSYS_CHMUX_PRESCALER_128_gc = (0x87<<0), /* Prescaler, divide by 128 */ - EVSYS_CHMUX_PRESCALER_256_gc = (0x88<<0), /* Prescaler, divide by 256 */ - EVSYS_CHMUX_PRESCALER_512_gc = (0x89<<0), /* Prescaler, divide by 512 */ - EVSYS_CHMUX_PRESCALER_1024_gc = (0x8A<<0), /* Prescaler, divide by 1024 */ - EVSYS_CHMUX_PRESCALER_2048_gc = (0x8B<<0), /* Prescaler, divide by 2048 */ - EVSYS_CHMUX_PRESCALER_4096_gc = (0x8C<<0), /* Prescaler, divide by 4096 */ - EVSYS_CHMUX_PRESCALER_8192_gc = (0x8D<<0), /* Prescaler, divide by 8192 */ - EVSYS_CHMUX_PRESCALER_16384_gc = (0x8E<<0), /* Prescaler, divide by 16384 */ - EVSYS_CHMUX_PRESCALER_32768_gc = (0x8F<<0), /* Prescaler, divide by 32768 */ - EVSYS_CHMUX_TCC0_OVF_gc = (0xC0<<0), /* Timer/Counter C0 Overflow */ - EVSYS_CHMUX_TCC0_ERR_gc = (0xC1<<0), /* Timer/Counter C0 Error */ - EVSYS_CHMUX_TCC0_CCA_gc = (0xC4<<0), /* Timer/Counter C0 Compare or Capture A */ - EVSYS_CHMUX_TCC0_CCB_gc = (0xC5<<0), /* Timer/Counter C0 Compare or Capture B */ - EVSYS_CHMUX_TCC0_CCC_gc = (0xC6<<0), /* Timer/Counter C0 Compare or Capture C */ - EVSYS_CHMUX_TCC0_CCD_gc = (0xC7<<0), /* Timer/Counter C0 Compare or Capture D */ - EVSYS_CHMUX_TCC1_OVF_gc = (0xC8<<0), /* Timer/Counter C1 Overflow */ - EVSYS_CHMUX_TCC1_ERR_gc = (0xC9<<0), /* Timer/Counter C1 Error */ - EVSYS_CHMUX_TCC1_CCA_gc = (0xCC<<0), /* Timer/Counter C1 Compare or Capture A */ - EVSYS_CHMUX_TCC1_CCB_gc = (0xCD<<0), /* Timer/Counter C1 Compare or Capture B */ - EVSYS_CHMUX_TCD0_OVF_gc = (0xD0<<0), /* Timer/Counter D0 Overflow */ - EVSYS_CHMUX_TCD0_ERR_gc = (0xD1<<0), /* Timer/Counter D0 Error */ - EVSYS_CHMUX_TCD0_CCA_gc = (0xD4<<0), /* Timer/Counter D0 Compare or Capture A */ - EVSYS_CHMUX_TCD0_CCB_gc = (0xD5<<0), /* Timer/Counter D0 Compare or Capture B */ - EVSYS_CHMUX_TCD0_CCC_gc = (0xD6<<0), /* Timer/Counter D0 Compare or Capture C */ - EVSYS_CHMUX_TCD0_CCD_gc = (0xD7<<0), /* Timer/Counter D0 Compare or Capture D */ - EVSYS_CHMUX_TCE0_OVF_gc = (0xE0<<0), /* Timer/Counter E0 Overflow */ - EVSYS_CHMUX_TCE0_ERR_gc = (0xE1<<0), /* Timer/Counter E0 Error */ - EVSYS_CHMUX_TCE0_CCA_gc = (0xE4<<0), /* Timer/Counter E0 Compare or Capture A */ - EVSYS_CHMUX_TCE0_CCB_gc = (0xE5<<0), /* Timer/Counter E0 Compare or Capture B */ - EVSYS_CHMUX_TCE0_CCC_gc = (0xE6<<0), /* Timer/Counter E0 Compare or Capture C */ - EVSYS_CHMUX_TCE0_CCD_gc = (0xE7<<0), /* Timer/Counter E0 Compare or Capture D */ - EVSYS_CHMUX_TCF0_OVF_gc = (0xF0<<0), /* Timer/Counter F0 Overflow */ - EVSYS_CHMUX_TCF0_ERR_gc = (0xF1<<0), /* Timer/Counter F0 Error */ - EVSYS_CHMUX_TCF0_CCA_gc = (0xF4<<0), /* Timer/Counter F0 Compare or Capture A */ - EVSYS_CHMUX_TCF0_CCB_gc = (0xF5<<0), /* Timer/Counter F0 Compare or Capture B */ - EVSYS_CHMUX_TCF0_CCC_gc = (0xF6<<0), /* Timer/Counter F0 Compare or Capture C */ - EVSYS_CHMUX_TCF0_CCD_gc = (0xF7<<0), /* Timer/Counter F0 Compare or Capture D */ -} EVSYS_CHMUX_t; - - -/* --------------------------------------------------------------------------- -NVM - Non Volatile Memory Controller --------------------------------------------------------------------------- -*/ - -/* Non-volatile Memory Controller */ -typedef struct NVM_struct -{ - register8_t ADDR0; /* Address Register 0 */ - register8_t ADDR1; /* Address Register 1 */ - register8_t ADDR2; /* Address Register 2 */ - register8_t reserved_0x03; - register8_t DATA0; /* Data Register 0 */ - register8_t DATA1; /* Data Register 1 */ - register8_t DATA2; /* Data Register 2 */ - register8_t reserved_0x07; - register8_t reserved_0x08; - register8_t reserved_0x09; - register8_t CMD; /* Command */ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t INTCTRL; /* Interrupt Control */ - register8_t reserved_0x0E; - register8_t STATUS; /* Status */ - register8_t LOCK_BITS; /* Lock Bits (Changed from LOCKBITS to avoid avr-libc collision) */ -} NVM_t; - -/* NVM Command */ -typedef enum NVM_CMD_enum -{ - NVM_CMD_NO_OPERATION_gc = (0x00<<0), /* Noop/Ordinary LPM */ - NVM_CMD_READ_USER_SIG_ROW_gc = (0x01<<0), /* Read user signature row */ - NVM_CMD_READ_CALIB_ROW_gc = (0x02<<0), /* Read calibration row */ - NVM_CMD_READ_EEPROM_gc = (0x06<<0), /* Read EEPROM */ - NVM_CMD_READ_FUSES_gc = (0x07<<0), /* Read fuse byte */ - NVM_CMD_WRITE_LOCK_BITS_gc = (0x08<<0), /* Write lock bits */ - NVM_CMD_ERASE_USER_SIG_ROW_gc = (0x18<<0), /* Erase user signature row */ - NVM_CMD_WRITE_USER_SIG_ROW_gc = (0x1A<<0), /* Write user signature row */ - NVM_CMD_ERASE_APP_gc = (0x20<<0), /* Erase Application Section */ - NVM_CMD_ERASE_APP_PAGE_gc = (0x22<<0), /* Erase Application Section page */ - NVM_CMD_LOAD_FLASH_BUFFER_gc = (0x23<<0), /* Load Flash page buffer */ - NVM_CMD_WRITE_APP_PAGE_gc = (0x24<<0), /* Write Application Section page */ - NVM_CMD_ERASE_WRITE_APP_PAGE_gc = (0x25<<0), /* Erase-and-write Application Section page */ - NVM_CMD_ERASE_FLASH_BUFFER_gc = (0x26<<0), /* Erase/flush Flash page buffer */ - NVM_CMD_ERASE_BOOT_PAGE_gc = (0x2A<<0), /* Erase Boot Section page */ - NVM_CMD_ERASE_FLASH_PAGE_gc = (0x2B<<0), /* Erase Flash Page */ - NVM_CMD_WRITE_BOOT_PAGE_gc = (0x2C<<0), /* Write Boot Section page */ - NVM_CMD_ERASE_WRITE_BOOT_PAGE_gc = (0x2D<<0), /* Erase-and-write Boot Section page */ - NVM_CMD_WRITE_FLASH_PAGE_gc = (0x2E<<0), /* Write Flash Page */ - NVM_CMD_ERASE_WRITE_FLASH_PAGE_gc = (0x2F<<0), /* Erase-and-write Flash Page */ - NVM_CMD_ERASE_EEPROM_gc = (0x30<<0), /* Erase EEPROM */ - NVM_CMD_ERASE_EEPROM_PAGE_gc = (0x32<<0), /* Erase EEPROM page */ - NVM_CMD_LOAD_EEPROM_BUFFER_gc = (0x33<<0), /* Load EEPROM page buffer */ - NVM_CMD_WRITE_EEPROM_PAGE_gc = (0x34<<0), /* Write EEPROM page */ - NVM_CMD_ERASE_WRITE_EEPROM_PAGE_gc = (0x35<<0), /* Erase-and-write EEPROM page */ - NVM_CMD_ERASE_EEPROM_BUFFER_gc = (0x36<<0), /* Erase/flush EEPROM page buffer */ - NVM_CMD_APP_CRC_gc = (0x38<<0), /* Application section CRC */ - NVM_CMD_BOOT_CRC_gc = (0x39<<0), /* Boot Section CRC */ - NVM_CMD_FLASH_RANGE_CRC_gc = (0x3A<<0), /* Flash Range CRC */ - NVM_CMD_CHIP_ERASE_gc = (0x40<<0), /* Erase Chip */ - NVM_CMD_READ_NVM_gc = (0x43<<0), /* Read NVM */ - NVM_CMD_WRITE_FUSE_gc = (0x4C<<0), /* Write Fuse byte */ - NVM_CMD_ERASE_BOOT_gc = (0x68<<0), /* Erase Boot Section */ - NVM_CMD_FLASH_CRC_gc = (0x78<<0), /* Flash CRC */ -} NVM_CMD_t; - -/* SPM ready interrupt level */ -typedef enum NVM_SPMLVL_enum -{ - NVM_SPMLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ - NVM_SPMLVL_LO_gc = (0x01<<2), /* Low level */ - NVM_SPMLVL_MED_gc = (0x02<<2), /* Medium level */ - NVM_SPMLVL_HI_gc = (0x03<<2), /* High level */ -} NVM_SPMLVL_t; - -/* EEPROM ready interrupt level */ -typedef enum NVM_EELVL_enum -{ - NVM_EELVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ - NVM_EELVL_LO_gc = (0x01<<0), /* Low level */ - NVM_EELVL_MED_gc = (0x02<<0), /* Medium level */ - NVM_EELVL_HI_gc = (0x03<<0), /* High level */ -} NVM_EELVL_t; - -/* Boot lock bits - boot setcion */ -typedef enum NVM_BLBB_enum -{ - NVM_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ - NVM_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ - NVM_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ - NVM_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ -} NVM_BLBB_t; - -/* Boot lock bits - application section */ -typedef enum NVM_BLBA_enum -{ - NVM_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ - NVM_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ - NVM_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ - NVM_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ -} NVM_BLBA_t; - -/* Boot lock bits - application table section */ -typedef enum NVM_BLBAT_enum -{ - NVM_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ - NVM_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ - NVM_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ - NVM_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ -} NVM_BLBAT_t; - -/* Lock bits */ -typedef enum NVM_LB_enum -{ - NVM_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ - NVM_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ - NVM_LB_NOLOCK_gc = (0x03<<0), /* No locks */ -} NVM_LB_t; - - -/* --------------------------------------------------------------------------- -ADC - Analog/Digital Converter --------------------------------------------------------------------------- -*/ - -/* ADC Channel */ -typedef struct ADC_CH_struct -{ - register8_t CTRL; /* Control Register */ - register8_t MUXCTRL; /* MUX Control */ - register8_t INTCTRL; /* Channel Interrupt Control Register */ - register8_t INTFLAGS; /* Interrupt Flags */ - _WORDREGISTER(RES); /* Channel Result */ - register8_t SCAN; /* Input Channel Scan */ - register8_t reserved_0x07; -} ADC_CH_t; - - -/* Analog-to-Digital Converter */ -typedef struct ADC_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t REFCTRL; /* Reference Control */ - register8_t EVCTRL; /* Event Control */ - register8_t PRESCALER; /* Clock Prescaler */ - register8_t reserved_0x05; - register8_t INTFLAGS; /* Interrupt Flags */ - register8_t TEMP; /* Temporary Register */ - register8_t reserved_0x08; - register8_t reserved_0x09; - register8_t reserved_0x0A; - register8_t reserved_0x0B; - _WORDREGISTER(CAL); /* Calibration Value */ - register8_t reserved_0x0E; - register8_t reserved_0x0F; - _WORDREGISTER(CH0RES); /* Channel 0 Result */ - register8_t reserved_0x12; - register8_t reserved_0x13; - register8_t reserved_0x14; - register8_t reserved_0x15; - register8_t reserved_0x16; - register8_t reserved_0x17; - _WORDREGISTER(CMP); /* Compare Value */ - register8_t reserved_0x1A; - register8_t reserved_0x1B; - register8_t reserved_0x1C; - register8_t reserved_0x1D; - register8_t reserved_0x1E; - register8_t reserved_0x1F; - ADC_CH_t CH0; /* ADC Channel 0 */ -} ADC_t; - -/* Current Limitation */ -typedef enum ADC_CURRLIMIT_enum -{ - ADC_CURRLIMIT_NO_gc = (0x00<<5), /* No current limit, 300ksps max sampling rate */ - ADC_CURRLIMIT_LOW_gc = (0x01<<5), /* Low current limit, 250ksps max sampling rate */ - ADC_CURRLIMIT_MED_gc = (0x02<<5), /* Medium current limit, 150ksps max sampling rate */ - ADC_CURRLIMIT_HIGH_gc = (0x03<<5), /* High current limit, 50ksps max sampling rate */ -} ADC_CURRLIMIT_t; - -/* Positive input multiplexer selection */ -typedef enum ADC_CH_MUXPOS_enum -{ - ADC_CH_MUXPOS_PIN0_gc = (0x00<<3), /* Input pin 0 */ - ADC_CH_MUXPOS_PIN1_gc = (0x01<<3), /* Input pin 1 */ - ADC_CH_MUXPOS_PIN2_gc = (0x02<<3), /* Input pin 2 */ - ADC_CH_MUXPOS_PIN3_gc = (0x03<<3), /* Input pin 3 */ - ADC_CH_MUXPOS_PIN4_gc = (0x04<<3), /* Input pin 4 */ - ADC_CH_MUXPOS_PIN5_gc = (0x05<<3), /* Input pin 5 */ - ADC_CH_MUXPOS_PIN6_gc = (0x06<<3), /* Input pin 6 */ - ADC_CH_MUXPOS_PIN7_gc = (0x07<<3), /* Input pin 7 */ - ADC_CH_MUXPOS_PIN8_gc = (0x08<<3), /* Input pin 8 */ - ADC_CH_MUXPOS_PIN9_gc = (0x09<<3), /* Input pin 9 */ - ADC_CH_MUXPOS_PIN10_gc = (0x0A<<3), /* Input pin 10 */ - ADC_CH_MUXPOS_PIN11_gc = (0x0B<<3), /* Input pin 11 */ -} ADC_CH_MUXPOS_t; - -/* Internal input multiplexer selections */ -typedef enum ADC_CH_MUXINT_enum -{ - ADC_CH_MUXINT_TEMP_gc = (0x00<<3), /* Temperature Reference */ - ADC_CH_MUXINT_BANDGAP_gc = (0x01<<3), /* Bandgap Reference */ - ADC_CH_MUXINT_SCALEDVCC_gc = (0x02<<3), /* 1/10 scaled VCC */ -} ADC_CH_MUXINT_t; - -/* Negative input multiplexer selection */ -typedef enum ADC_CH_MUXNEG_enum -{ - ADC_CH_MUXNEG_PIN0_gc = (0x00<<0), /* Input pin 0 */ - ADC_CH_MUXNEG_PIN1_gc = (0x01<<0), /* Input pin 1 */ - ADC_CH_MUXNEG_PIN2_gc = (0x02<<0), /* Input pin 2 */ - ADC_CH_MUXNEG_PIN3_gc = (0x03<<0), /* Input pin 3 */ - ADC_CH_MUXNEG_PIN4_gc = (0x00<<0), /* Input pin 4 */ - ADC_CH_MUXNEG_PIN5_gc = (0x01<<0), /* Input pin 5 */ - ADC_CH_MUXNEG_PIN6_gc = (0x02<<0), /* Input pin 6 */ - ADC_CH_MUXNEG_PIN7_gc = (0x03<<0), /* Input pin 7 */ -} ADC_CH_MUXNEG_t; - -/* Input mode */ -typedef enum ADC_CH_INPUTMODE_enum -{ - ADC_CH_INPUTMODE_INTERNAL_gc = (0x00<<0), /* Internal inputs, no gain */ - ADC_CH_INPUTMODE_SINGLEENDED_gc = (0x01<<0), /* Single-ended input, no gain */ - ADC_CH_INPUTMODE_DIFF_gc = (0x02<<0), /* Differential input, no gain */ - ADC_CH_INPUTMODE_DIFFWGAIN_gc = (0x03<<0), /* Differential input, with gain */ -} ADC_CH_INPUTMODE_t; - -/* Gain factor */ -typedef enum ADC_CH_GAIN_enum -{ - ADC_CH_GAIN_1X_gc = (0x00<<2), /* 1x gain */ - ADC_CH_GAIN_2X_gc = (0x01<<2), /* 2x gain */ - ADC_CH_GAIN_4X_gc = (0x02<<2), /* 4x gain */ - ADC_CH_GAIN_8X_gc = (0x03<<2), /* 8x gain */ - ADC_CH_GAIN_16X_gc = (0x04<<2), /* 16x gain */ - ADC_CH_GAIN_32X_gc = (0x05<<2), /* 32x gain */ - ADC_CH_GAIN_64X_gc = (0x06<<2), /* 64x gain */ - ADC_CH_GAIN_DIV2_gc = (0x07<<2), /* x/2 gain */ -} ADC_CH_GAIN_t; - -/* Conversion result resolution */ -typedef enum ADC_RESOLUTION_enum -{ - ADC_RESOLUTION_12BIT_gc = (0x00<<1), /* 12-bit right-adjusted result */ - ADC_RESOLUTION_8BIT_gc = (0x02<<1), /* 8-bit right-adjusted result */ - ADC_RESOLUTION_LEFT12BIT_gc = (0x03<<1), /* 12-bit left-adjusted result */ -} ADC_RESOLUTION_t; - -/* Voltage reference selection */ -typedef enum ADC_REFSEL_enum -{ - ADC_REFSEL_INT1V_gc = (0x00<<4), /* Internal 1V */ - ADC_REFSEL_INTVCC_gc = (0x01<<4), /* Internal VCC / 1.6 */ - ADC_REFSEL_AREFA_gc = (0x02<<4), /* External reference on PORT A */ - ADC_REFSEL_AREFB_gc = (0x03<<4), /* External reference on PORT B */ - ADC_REFSEL_INTVCC2_gc = (0x04<<4), /* Internal VCC / 2 */ -} ADC_REFSEL_t; - -/* Event channel input selection */ -typedef enum ADC_EVSEL_enum -{ - ADC_EVSEL_0_gc = (0x00<<3), /* Event Channel 0 */ - ADC_EVSEL_1_gc = (0x01<<3), /* Event Channel 1 */ - ADC_EVSEL_2_gc = (0x02<<3), /* Event Channel 2 */ - ADC_EVSEL_3_gc = (0x03<<3), /* Event Channel 3 */ -} ADC_EVSEL_t; - -/* Event action selection */ -typedef enum ADC_EVACT_enum -{ - ADC_EVACT_NONE_gc = (0x00<<0), /* No event action */ - ADC_EVACT_CH0_gc = (0x01<<0), /* First event triggers channel 0 */ - ADC_EVACT_SYNCSWEEP_gc = (0x06<<0), /* The ADC is flushed and restarted for accurate timing */ -} ADC_EVACT_t; - -/* Interupt mode */ -typedef enum ADC_CH_INTMODE_enum -{ - ADC_CH_INTMODE_COMPLETE_gc = (0x00<<2), /* Interrupt on conversion complete */ - ADC_CH_INTMODE_BELOW_gc = (0x01<<2), /* Interrupt on result below compare value */ - ADC_CH_INTMODE_ABOVE_gc = (0x03<<2), /* Interrupt on result above compare value */ -} ADC_CH_INTMODE_t; - -/* Interrupt level */ -typedef enum ADC_CH_INTLVL_enum -{ - ADC_CH_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ - ADC_CH_INTLVL_LO_gc = (0x01<<0), /* Low level */ - ADC_CH_INTLVL_MED_gc = (0x02<<0), /* Medium level */ - ADC_CH_INTLVL_HI_gc = (0x03<<0), /* High level */ -} ADC_CH_INTLVL_t; - -/* Clock prescaler */ -typedef enum ADC_PRESCALER_enum -{ - ADC_PRESCALER_DIV4_gc = (0x00<<0), /* Divide clock by 4 */ - ADC_PRESCALER_DIV8_gc = (0x01<<0), /* Divide clock by 8 */ - ADC_PRESCALER_DIV16_gc = (0x02<<0), /* Divide clock by 16 */ - ADC_PRESCALER_DIV32_gc = (0x03<<0), /* Divide clock by 32 */ - ADC_PRESCALER_DIV64_gc = (0x04<<0), /* Divide clock by 64 */ - ADC_PRESCALER_DIV128_gc = (0x05<<0), /* Divide clock by 128 */ - ADC_PRESCALER_DIV256_gc = (0x06<<0), /* Divide clock by 256 */ - ADC_PRESCALER_DIV512_gc = (0x07<<0), /* Divide clock by 512 */ -} ADC_PRESCALER_t; - - -/* --------------------------------------------------------------------------- -AC - Analog Comparator --------------------------------------------------------------------------- -*/ - -/* Analog Comparator */ -typedef struct AC_struct -{ - register8_t AC0CTRL; /* Analog Comparator 0 Control */ - register8_t AC1CTRL; /* Analog Comparator 1 Control */ - register8_t AC0MUXCTRL; /* Analog Comparator 0 MUX Control */ - register8_t AC1MUXCTRL; /* Analog Comparator 1 MUX Control */ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t WINCTRL; /* Window Mode Control */ - register8_t STATUS; /* Status */ -} AC_t; - -/* Interrupt mode */ -typedef enum AC_INTMODE_enum -{ - AC_INTMODE_BOTHEDGES_gc = (0x00<<6), /* Interrupt on both edges */ - AC_INTMODE_FALLING_gc = (0x02<<6), /* Interrupt on falling edge */ - AC_INTMODE_RISING_gc = (0x03<<6), /* Interrupt on rising edge */ -} AC_INTMODE_t; - -/* Interrupt level */ -typedef enum AC_INTLVL_enum -{ - AC_INTLVL_OFF_gc = (0x00<<4), /* Interrupt disabled */ - AC_INTLVL_LO_gc = (0x01<<4), /* Low level */ - AC_INTLVL_MED_gc = (0x02<<4), /* Medium level */ - AC_INTLVL_HI_gc = (0x03<<4), /* High level */ -} AC_INTLVL_t; - -/* Hysteresis mode selection */ -typedef enum AC_HYSMODE_enum -{ - AC_HYSMODE_NO_gc = (0x00<<1), /* No hysteresis */ - AC_HYSMODE_SMALL_gc = (0x01<<1), /* Small hysteresis */ - AC_HYSMODE_LARGE_gc = (0x02<<1), /* Large hysteresis */ -} AC_HYSMODE_t; - -/* Positive input multiplexer selection */ -typedef enum AC_MUXPOS_enum -{ - AC_MUXPOS_PIN0_gc = (0x00<<3), /* Pin 0 */ - AC_MUXPOS_PIN1_gc = (0x01<<3), /* Pin 1 */ - AC_MUXPOS_PIN2_gc = (0x02<<3), /* Pin 2 */ - AC_MUXPOS_PIN3_gc = (0x03<<3), /* Pin 3 */ - AC_MUXPOS_PIN4_gc = (0x04<<3), /* Pin 4 */ - AC_MUXPOS_PIN5_gc = (0x05<<3), /* Pin 5 */ - AC_MUXPOS_PIN6_gc = (0x06<<3), /* Pin 6 */ -} AC_MUXPOS_t; - -/* Negative input multiplexer selection */ -typedef enum AC_MUXNEG_enum -{ - AC_MUXNEG_PIN0_gc = (0x00<<0), /* Pin 0 */ - AC_MUXNEG_PIN1_gc = (0x01<<0), /* Pin 1 */ - AC_MUXNEG_PIN3_gc = (0x02<<0), /* Pin 3 */ - AC_MUXNEG_PIN5_gc = (0x03<<0), /* Pin 5 */ - AC_MUXNEG_PIN7_gc = (0x04<<0), /* Pin 7 */ - AC_MUXNEG_BANDGAP_gc = (0x06<<0), /* Bandgap Reference */ - AC_MUXNEG_SCALER_gc = (0x07<<0), /* Internal voltage scaler */ -} AC_MUXNEG_t; - -/* Windows interrupt mode */ -typedef enum AC_WINTMODE_enum -{ - AC_WINTMODE_ABOVE_gc = (0x00<<2), /* Interrupt on above window */ - AC_WINTMODE_INSIDE_gc = (0x01<<2), /* Interrupt on inside window */ - AC_WINTMODE_BELOW_gc = (0x02<<2), /* Interrupt on below window */ - AC_WINTMODE_OUTSIDE_gc = (0x03<<2), /* Interrupt on outside window */ -} AC_WINTMODE_t; - -/* Window interrupt level */ -typedef enum AC_WINTLVL_enum -{ - AC_WINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ - AC_WINTLVL_LO_gc = (0x01<<0), /* Low priority */ - AC_WINTLVL_MED_gc = (0x02<<0), /* Medium priority */ - AC_WINTLVL_HI_gc = (0x03<<0), /* High priority */ -} AC_WINTLVL_t; - -/* Window mode state */ -typedef enum AC_WSTATE_enum -{ - AC_WSTATE_ABOVE_gc = (0x00<<6), /* Signal above window */ - AC_WSTATE_INSIDE_gc = (0x01<<6), /* Signal inside window */ - AC_WSTATE_BELOW_gc = (0x02<<6), /* Signal below window */ -} AC_WSTATE_t; - - -/* --------------------------------------------------------------------------- -RTC - Real-Time Counter --------------------------------------------------------------------------- -*/ - -/* Real-Time Counter */ -typedef struct RTC_struct -{ - register8_t CTRL; /* Control Register */ - register8_t STATUS; /* Status Register */ - register8_t INTCTRL; /* Interrupt Control Register */ - register8_t INTFLAGS; /* Interrupt Flags */ - register8_t TEMP; /* Temporary register */ - register8_t reserved_0x05; - register8_t reserved_0x06; - register8_t reserved_0x07; - _WORDREGISTER(CNT); /* Count Register */ - _WORDREGISTER(PER); /* Period Register */ - _WORDREGISTER(COMP); /* Compare Register */ -} RTC_t; - -/* Prescaler Factor */ -typedef enum RTC_PRESCALER_enum -{ - RTC_PRESCALER_OFF_gc = (0x00<<0), /* RTC Off */ - RTC_PRESCALER_DIV1_gc = (0x01<<0), /* RTC Clock */ - RTC_PRESCALER_DIV2_gc = (0x02<<0), /* RTC Clock / 2 */ - RTC_PRESCALER_DIV8_gc = (0x03<<0), /* RTC Clock / 8 */ - RTC_PRESCALER_DIV16_gc = (0x04<<0), /* RTC Clock / 16 */ - RTC_PRESCALER_DIV64_gc = (0x05<<0), /* RTC Clock / 64 */ - RTC_PRESCALER_DIV256_gc = (0x06<<0), /* RTC Clock / 256 */ - RTC_PRESCALER_DIV1024_gc = (0x07<<0), /* RTC Clock / 1024 */ -} RTC_PRESCALER_t; - -/* Compare Interrupt level */ -typedef enum RTC_COMPINTLVL_enum -{ - RTC_COMPINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ - RTC_COMPINTLVL_LO_gc = (0x01<<2), /* Low Level */ - RTC_COMPINTLVL_MED_gc = (0x02<<2), /* Medium Level */ - RTC_COMPINTLVL_HI_gc = (0x03<<2), /* High Level */ -} RTC_COMPINTLVL_t; - -/* Overflow Interrupt level */ -typedef enum RTC_OVFINTLVL_enum -{ - RTC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - RTC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ - RTC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ - RTC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ -} RTC_OVFINTLVL_t; - - -/* --------------------------------------------------------------------------- -TWI - Two-Wire Interface --------------------------------------------------------------------------- -*/ - -/* */ -typedef struct TWI_MASTER_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t CTRLC; /* Control Register C */ - register8_t STATUS; /* Status Register */ - register8_t BAUD; /* Baurd Rate Control Register */ - register8_t ADDR; /* Address Register */ - register8_t DATA; /* Data Register */ -} TWI_MASTER_t; - - -/* */ -typedef struct TWI_SLAVE_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t STATUS; /* Status Register */ - register8_t ADDR; /* Address Register */ - register8_t DATA; /* Data Register */ - register8_t ADDRMASK; /* Address Mask Register */ -} TWI_SLAVE_t; - - -/* Two-Wire Interface */ -typedef struct TWI_struct -{ - register8_t CTRL; /* TWI Common Control Register */ - TWI_MASTER_t MASTER; /* TWI master module */ - TWI_SLAVE_t SLAVE; /* TWI slave module */ -} TWI_t; - -/* SDA Hold Time */ -typedef enum TWI_SDAHOLD_enum -{ - TWI_SDAHOLD_OFF_gc = (0x00<<1), /* SDA Hold Time off */ - TWI_SDAHOLD_50NS_gc = (0x01<<1), /* SDA Hold Time 50 ns */ - TWI_SDAHOLD_300NS_gc = (0x02<<1), /* SDA Hold Time 300 ns */ - TWI_SDAHOLD_400NS_gc = (0x03<<1), /* SDA Hold Time 400 ns */ -} TWI_SDAHOLD_t; - -/* Master Interrupt Level */ -typedef enum TWI_MASTER_INTLVL_enum -{ - TWI_MASTER_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ - TWI_MASTER_INTLVL_LO_gc = (0x01<<6), /* Low Level */ - TWI_MASTER_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ - TWI_MASTER_INTLVL_HI_gc = (0x03<<6), /* High Level */ -} TWI_MASTER_INTLVL_t; - -/* Inactive Timeout */ -typedef enum TWI_MASTER_TIMEOUT_enum -{ - TWI_MASTER_TIMEOUT_DISABLED_gc = (0x00<<2), /* Bus Timeout Disabled */ - TWI_MASTER_TIMEOUT_50US_gc = (0x01<<2), /* 50 Microseconds */ - TWI_MASTER_TIMEOUT_100US_gc = (0x02<<2), /* 100 Microseconds */ - TWI_MASTER_TIMEOUT_200US_gc = (0x03<<2), /* 200 Microseconds */ -} TWI_MASTER_TIMEOUT_t; - -/* Master Command */ -typedef enum TWI_MASTER_CMD_enum -{ - TWI_MASTER_CMD_NOACT_gc = (0x00<<0), /* No Action */ - TWI_MASTER_CMD_REPSTART_gc = (0x01<<0), /* Issue Repeated Start Condition */ - TWI_MASTER_CMD_RECVTRANS_gc = (0x02<<0), /* Receive or Transmit Data */ - TWI_MASTER_CMD_STOP_gc = (0x03<<0), /* Issue Stop Condition */ -} TWI_MASTER_CMD_t; - -/* Master Bus State */ -typedef enum TWI_MASTER_BUSSTATE_enum -{ - TWI_MASTER_BUSSTATE_UNKNOWN_gc = (0x00<<0), /* Unknown Bus State */ - TWI_MASTER_BUSSTATE_IDLE_gc = (0x01<<0), /* Bus is Idle */ - TWI_MASTER_BUSSTATE_OWNER_gc = (0x02<<0), /* This Module Controls The Bus */ - TWI_MASTER_BUSSTATE_BUSY_gc = (0x03<<0), /* The Bus is Busy */ -} TWI_MASTER_BUSSTATE_t; - -/* Slave Interrupt Level */ -typedef enum TWI_SLAVE_INTLVL_enum -{ - TWI_SLAVE_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ - TWI_SLAVE_INTLVL_LO_gc = (0x01<<6), /* Low Level */ - TWI_SLAVE_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ - TWI_SLAVE_INTLVL_HI_gc = (0x03<<6), /* High Level */ -} TWI_SLAVE_INTLVL_t; - -/* Slave Command */ -typedef enum TWI_SLAVE_CMD_enum -{ - TWI_SLAVE_CMD_NOACT_gc = (0x00<<0), /* No Action */ - TWI_SLAVE_CMD_COMPTRANS_gc = (0x02<<0), /* Used To Complete a Transaction */ - TWI_SLAVE_CMD_RESPONSE_gc = (0x03<<0), /* Used in Response to Address/Data Interrupt */ -} TWI_SLAVE_CMD_t; - - -/* --------------------------------------------------------------------------- -PORT - Port Configuration --------------------------------------------------------------------------- -*/ - -/* I/O Ports */ -typedef struct PORT_struct -{ - register8_t DIR; /* I/O Port Data Direction */ - register8_t DIRSET; /* I/O Port Data Direction Set */ - register8_t DIRCLR; /* I/O Port Data Direction Clear */ - register8_t DIRTGL; /* I/O Port Data Direction Toggle */ - register8_t OUT; /* I/O Port Output */ - register8_t OUTSET; /* I/O Port Output Set */ - register8_t OUTCLR; /* I/O Port Output Clear */ - register8_t OUTTGL; /* I/O Port Output Toggle */ - register8_t IN; /* I/O port Input */ - register8_t INTCTRL; /* Interrupt Control Register */ - register8_t INT0MASK; /* Port Interrupt 0 Mask */ - register8_t INT1MASK; /* Port Interrupt 1 Mask */ - register8_t INTFLAGS; /* Interrupt Flag Register */ - register8_t reserved_0x0D; - register8_t REMAP; /* Pin Remap Register (available for PORTC to PORTF only) */ - register8_t reserved_0x0F; - register8_t PIN0CTRL; /* Pin 0 Control Register */ - register8_t PIN1CTRL; /* Pin 1 Control Register */ - register8_t PIN2CTRL; /* Pin 2 Control Register */ - register8_t PIN3CTRL; /* Pin 3 Control Register */ - register8_t PIN4CTRL; /* Pin 4 Control Register */ - register8_t PIN5CTRL; /* Pin 5 Control Register */ - register8_t PIN6CTRL; /* Pin 6 Control Register */ - register8_t PIN7CTRL; /* Pin 7 Control Register */ -} PORT_t; - -/* Port Interrupt 0 Level */ -typedef enum PORT_INT0LVL_enum -{ - PORT_INT0LVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - PORT_INT0LVL_LO_gc = (0x01<<0), /* Low Level */ - PORT_INT0LVL_MED_gc = (0x02<<0), /* Medium Level */ - PORT_INT0LVL_HI_gc = (0x03<<0), /* High Level */ -} PORT_INT0LVL_t; - -/* Port Interrupt 1 Level */ -typedef enum PORT_INT1LVL_enum -{ - PORT_INT1LVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ - PORT_INT1LVL_LO_gc = (0x01<<2), /* Low Level */ - PORT_INT1LVL_MED_gc = (0x02<<2), /* Medium Level */ - PORT_INT1LVL_HI_gc = (0x03<<2), /* High Level */ -} PORT_INT1LVL_t; - -/* Output/Pull Configuration */ -typedef enum PORT_OPC_enum -{ - PORT_OPC_TOTEM_gc = (0x00<<3), /* Totempole */ - PORT_OPC_BUSKEEPER_gc = (0x01<<3), /* Totempole w/ Bus keeper on Input and Output */ - PORT_OPC_PULLDOWN_gc = (0x02<<3), /* Totempole w/ Pull-down on Input */ - PORT_OPC_PULLUP_gc = (0x03<<3), /* Totempole w/ Pull-up on Input */ - PORT_OPC_WIREDOR_gc = (0x04<<3), /* Wired OR */ - PORT_OPC_WIREDAND_gc = (0x05<<3), /* Wired AND */ - PORT_OPC_WIREDORPULL_gc = (0x06<<3), /* Wired OR w/ Pull-down */ - PORT_OPC_WIREDANDPULL_gc = (0x07<<3), /* Wired AND w/ Pull-up */ -} PORT_OPC_t; - -/* Input/Sense Configuration */ -typedef enum PORT_ISC_enum -{ - PORT_ISC_BOTHEDGES_gc = (0x00<<0), /* Sense Both Edges */ - PORT_ISC_RISING_gc = (0x01<<0), /* Sense Rising Edge */ - PORT_ISC_FALLING_gc = (0x02<<0), /* Sense Falling Edge */ - PORT_ISC_LEVEL_gc = (0x03<<0), /* Sense Level (Transparent For Events) */ - PORT_ISC_INPUT_DISABLE_gc = (0x07<<0), /* Disable Digital Input Buffer */ -} PORT_ISC_t; - - -/* --------------------------------------------------------------------------- -TC - 16-bit Timer/Counter With PWM --------------------------------------------------------------------------- -*/ - -/* 16-bit Timer/Counter 0 */ -typedef struct TC0_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t CTRLC; /* Control register C */ - register8_t CTRLD; /* Control Register D */ - register8_t CTRLE; /* Control Register E */ - register8_t reserved_0x05; - register8_t INTCTRLA; /* Interrupt Control Register A */ - register8_t INTCTRLB; /* Interrupt Control Register B */ - register8_t CTRLFCLR; /* Control Register F Clear */ - register8_t CTRLFSET; /* Control Register F Set */ - register8_t CTRLGCLR; /* Control Register G Clear */ - register8_t CTRLGSET; /* Control Register G Set */ - register8_t INTFLAGS; /* Interrupt Flag Register */ - register8_t reserved_0x0D; - register8_t reserved_0x0E; - register8_t TEMP; /* Temporary Register For 16-bit Access */ - register8_t reserved_0x10; - register8_t reserved_0x11; - register8_t reserved_0x12; - register8_t reserved_0x13; - register8_t reserved_0x14; - register8_t reserved_0x15; - register8_t reserved_0x16; - register8_t reserved_0x17; - register8_t reserved_0x18; - register8_t reserved_0x19; - register8_t reserved_0x1A; - register8_t reserved_0x1B; - register8_t reserved_0x1C; - register8_t reserved_0x1D; - register8_t reserved_0x1E; - register8_t reserved_0x1F; - _WORDREGISTER(CNT); /* Count */ - register8_t reserved_0x22; - register8_t reserved_0x23; - register8_t reserved_0x24; - register8_t reserved_0x25; - _WORDREGISTER(PER); /* Period */ - _WORDREGISTER(CCA); /* Compare or Capture A */ - _WORDREGISTER(CCB); /* Compare or Capture B */ - _WORDREGISTER(CCC); /* Compare or Capture C */ - _WORDREGISTER(CCD); /* Compare or Capture D */ - register8_t reserved_0x30; - register8_t reserved_0x31; - register8_t reserved_0x32; - register8_t reserved_0x33; - register8_t reserved_0x34; - register8_t reserved_0x35; - _WORDREGISTER(PERBUF); /* Period Buffer */ - _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ - _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ - _WORDREGISTER(CCCBUF); /* Compare Or Capture C Buffer */ - _WORDREGISTER(CCDBUF); /* Compare Or Capture D Buffer */ -} TC0_t; - - -/* 16-bit Timer/Counter 1 */ -typedef struct TC1_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t CTRLC; /* Control register C */ - register8_t CTRLD; /* Control Register D */ - register8_t CTRLE; /* Control Register E */ - register8_t reserved_0x05; - register8_t INTCTRLA; /* Interrupt Control Register A */ - register8_t INTCTRLB; /* Interrupt Control Register B */ - register8_t CTRLFCLR; /* Control Register F Clear */ - register8_t CTRLFSET; /* Control Register F Set */ - register8_t CTRLGCLR; /* Control Register G Clear */ - register8_t CTRLGSET; /* Control Register G Set */ - register8_t INTFLAGS; /* Interrupt Flag Register */ - register8_t reserved_0x0D; - register8_t reserved_0x0E; - register8_t TEMP; /* Temporary Register For 16-bit Access */ - register8_t reserved_0x10; - register8_t reserved_0x11; - register8_t reserved_0x12; - register8_t reserved_0x13; - register8_t reserved_0x14; - register8_t reserved_0x15; - register8_t reserved_0x16; - register8_t reserved_0x17; - register8_t reserved_0x18; - register8_t reserved_0x19; - register8_t reserved_0x1A; - register8_t reserved_0x1B; - register8_t reserved_0x1C; - register8_t reserved_0x1D; - register8_t reserved_0x1E; - register8_t reserved_0x1F; - _WORDREGISTER(CNT); /* Count */ - register8_t reserved_0x22; - register8_t reserved_0x23; - register8_t reserved_0x24; - register8_t reserved_0x25; - _WORDREGISTER(PER); /* Period */ - _WORDREGISTER(CCA); /* Compare or Capture A */ - _WORDREGISTER(CCB); /* Compare or Capture B */ - register8_t reserved_0x2C; - register8_t reserved_0x2D; - register8_t reserved_0x2E; - register8_t reserved_0x2F; - register8_t reserved_0x30; - register8_t reserved_0x31; - register8_t reserved_0x32; - register8_t reserved_0x33; - register8_t reserved_0x34; - register8_t reserved_0x35; - _WORDREGISTER(PERBUF); /* Period Buffer */ - _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ - _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ -} TC1_t; - -/* Clock Selection */ -typedef enum TC_CLKSEL_enum -{ - TC_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */ - TC_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */ - TC_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */ - TC_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */ - TC_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */ - TC_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */ - TC_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */ - TC_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */ - TC_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */ - TC_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */ - TC_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */ - TC_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */ -} TC_CLKSEL_t; - -/* Waveform Generation Mode */ -typedef enum TC_WGMODE_enum -{ - TC_WGMODE_NORMAL_gc = (0x00<<0), /* Normal Mode */ - TC_WGMODE_FRQ_gc = (0x01<<0), /* Frequency Generation Mode */ - TC_WGMODE_SINGLESLOPE_gc = (0x03<<0), /* Single Slope */ - TC_WGMODE_SS_gc = (0x03<<0), /* Single Slope */ - TC_WGMODE_DSTOP_gc = (0x05<<0), /* Dual Slope, Update on TOP */ - TC_WGMODE_DS_T_gc = (0x05<<0), /* Dual Slope, Update on TOP */ - TC_WGMODE_DSBOTH_gc = (0x06<<0), /* Dual Slope, Update on both TOP and BOTTOM */ - TC_WGMODE_DS_TB_gc = (0x06<<0), /* Dual Slope, Update on both TOP and BOTTOM */ - TC_WGMODE_DSBOTTOM_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */ - TC_WGMODE_DS_B_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */ -} TC_WGMODE_t; - -/* Byte Mode */ -typedef enum TC_BYTEM_enum -{ - TC_BYTEM_NORMAL_gc = (0x00<<0), /* 16-bit mode */ - TC_BYTEM_BYTEMODE_gc = (0x01<<0), /* Timer/Counter operating in byte mode only */ - TC_BYTEM_SPLITMODE_gc = (0x02<<0), /* Timer/Counter split into two 8-bit Counters (TC2) */ -} TC_BYTEM_t; - -/* Event Action */ -typedef enum TC_EVACT_enum -{ - TC_EVACT_OFF_gc = (0x00<<5), /* No Event Action */ - TC_EVACT_CAPT_gc = (0x01<<5), /* Input Capture */ - TC_EVACT_UPDOWN_gc = (0x02<<5), /* Externally Controlled Up/Down Count */ - TC_EVACT_QDEC_gc = (0x03<<5), /* Quadrature Decode */ - TC_EVACT_RESTART_gc = (0x04<<5), /* Restart */ - TC_EVACT_FRQ_gc = (0x05<<5), /* Frequency Capture */ - TC_EVACT_PW_gc = (0x06<<5), /* Pulse-width Capture */ -} TC_EVACT_t; - -/* Event Selection */ -typedef enum TC_EVSEL_enum -{ - TC_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ - TC_EVSEL_CH0_gc = (0x08<<0), /* Event Channel 0 */ - TC_EVSEL_CH1_gc = (0x09<<0), /* Event Channel 1 */ - TC_EVSEL_CH2_gc = (0x0A<<0), /* Event Channel 2 */ - TC_EVSEL_CH3_gc = (0x0B<<0), /* Event Channel 3 */ -} TC_EVSEL_t; - -/* Error Interrupt Level */ -typedef enum TC_ERRINTLVL_enum -{ - TC_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ - TC_ERRINTLVL_LO_gc = (0x01<<2), /* Low Level */ - TC_ERRINTLVL_MED_gc = (0x02<<2), /* Medium Level */ - TC_ERRINTLVL_HI_gc = (0x03<<2), /* High Level */ -} TC_ERRINTLVL_t; - -/* Overflow Interrupt Level */ -typedef enum TC_OVFINTLVL_enum -{ - TC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - TC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ - TC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ - TC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ -} TC_OVFINTLVL_t; - -/* Compare or Capture D Interrupt Level */ -typedef enum TC_CCDINTLVL_enum -{ - TC_CCDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ - TC_CCDINTLVL_LO_gc = (0x01<<6), /* Low Level */ - TC_CCDINTLVL_MED_gc = (0x02<<6), /* Medium Level */ - TC_CCDINTLVL_HI_gc = (0x03<<6), /* High Level */ -} TC_CCDINTLVL_t; - -/* Compare or Capture C Interrupt Level */ -typedef enum TC_CCCINTLVL_enum -{ - TC_CCCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ - TC_CCCINTLVL_LO_gc = (0x01<<4), /* Low Level */ - TC_CCCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ - TC_CCCINTLVL_HI_gc = (0x03<<4), /* High Level */ -} TC_CCCINTLVL_t; - -/* Compare or Capture B Interrupt Level */ -typedef enum TC_CCBINTLVL_enum -{ - TC_CCBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ - TC_CCBINTLVL_LO_gc = (0x01<<2), /* Low Level */ - TC_CCBINTLVL_MED_gc = (0x02<<2), /* Medium Level */ - TC_CCBINTLVL_HI_gc = (0x03<<2), /* High Level */ -} TC_CCBINTLVL_t; - -/* Compare or Capture A Interrupt Level */ -typedef enum TC_CCAINTLVL_enum -{ - TC_CCAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - TC_CCAINTLVL_LO_gc = (0x01<<0), /* Low Level */ - TC_CCAINTLVL_MED_gc = (0x02<<0), /* Medium Level */ - TC_CCAINTLVL_HI_gc = (0x03<<0), /* High Level */ -} TC_CCAINTLVL_t; - -/* Timer/Counter Command */ -typedef enum TC_CMD_enum -{ - TC_CMD_NONE_gc = (0x00<<2), /* No Command */ - TC_CMD_UPDATE_gc = (0x01<<2), /* Force Update */ - TC_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ - TC_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ -} TC_CMD_t; - - -/* --------------------------------------------------------------------------- -TC2 - 16-bit Timer/Counter type 2 --------------------------------------------------------------------------- -*/ - -/* 16-bit Timer/Counter type 2 */ -typedef struct TC2_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t CTRLC; /* Control register C */ - register8_t reserved_0x03; - register8_t CTRLE; /* Control Register E */ - register8_t reserved_0x05; - register8_t INTCTRLA; /* Interrupt Control Register A */ - register8_t INTCTRLB; /* Interrupt Control Register B */ - register8_t reserved_0x08; - register8_t CTRLF; /* Control Register F */ - register8_t reserved_0x0A; - register8_t reserved_0x0B; - register8_t INTFLAGS; /* Interrupt Flag Register */ - register8_t reserved_0x0D; - register8_t reserved_0x0E; - register8_t reserved_0x0F; - register8_t reserved_0x10; - register8_t reserved_0x11; - register8_t reserved_0x12; - register8_t reserved_0x13; - register8_t reserved_0x14; - register8_t reserved_0x15; - register8_t reserved_0x16; - register8_t reserved_0x17; - register8_t reserved_0x18; - register8_t reserved_0x19; - register8_t reserved_0x1A; - register8_t reserved_0x1B; - register8_t reserved_0x1C; - register8_t reserved_0x1D; - register8_t reserved_0x1E; - register8_t reserved_0x1F; - register8_t LCNT; /* Low Byte Count */ - register8_t HCNT; /* High Byte Count */ - register8_t reserved_0x22; - register8_t reserved_0x23; - register8_t reserved_0x24; - register8_t reserved_0x25; - register8_t LPER; /* Low Byte Period */ - register8_t HPER; /* High Byte Period */ - register8_t LCMPA; /* Low Byte Compare A */ - register8_t HCMPA; /* High Byte Compare A */ - register8_t LCMPB; /* Low Byte Compare B */ - register8_t HCMPB; /* High Byte Compare B */ - register8_t LCMPC; /* Low Byte Compare C */ - register8_t HCMPC; /* High Byte Compare C */ - register8_t LCMPD; /* Low Byte Compare D */ - register8_t HCMPD; /* High Byte Compare D */ -} TC2_t; - -/* Clock Selection */ -typedef enum TC2_CLKSEL_enum -{ - TC2_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */ - TC2_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */ - TC2_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */ - TC2_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */ - TC2_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */ - TC2_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */ - TC2_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */ - TC2_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */ - TC2_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */ - TC2_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */ - TC2_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */ - TC2_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */ -} TC2_CLKSEL_t; - -/* Byte Mode */ -typedef enum TC2_BYTEM_enum -{ - TC2_BYTEM_NORMAL_gc = (0x00<<0), /* 16-bit mode */ - TC2_BYTEM_BYTEMODE_gc = (0x01<<0), /* Timer/Counter operating in byte mode only (TC2) */ - TC2_BYTEM_SPLITMODE_gc = (0x02<<0), /* Timer/Counter split into two 8-bit Counters */ -} TC2_BYTEM_t; - -/* High Byte Underflow Interrupt Level */ -typedef enum TC2_HUNFINTLVL_enum -{ - TC2_HUNFINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ - TC2_HUNFINTLVL_LO_gc = (0x01<<2), /* Low Level */ - TC2_HUNFINTLVL_MED_gc = (0x02<<2), /* Medium Level */ - TC2_HUNFINTLVL_HI_gc = (0x03<<2), /* High Level */ -} TC2_HUNFINTLVL_t; - -/* Low Byte Underflow Interrupt Level */ -typedef enum TC2_LUNFINTLVL_enum -{ - TC2_LUNFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - TC2_LUNFINTLVL_LO_gc = (0x01<<0), /* Low Level */ - TC2_LUNFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ - TC2_LUNFINTLVL_HI_gc = (0x03<<0), /* High Level */ -} TC2_LUNFINTLVL_t; - -/* Low Byte Compare D Interrupt Level */ -typedef enum TC2_LCMPDINTLVL_enum -{ - TC2_LCMPDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ - TC2_LCMPDINTLVL_LO_gc = (0x01<<6), /* Low Level */ - TC2_LCMPDINTLVL_MED_gc = (0x02<<6), /* Medium Level */ - TC2_LCMPDINTLVL_HI_gc = (0x03<<6), /* High Level */ -} TC2_LCMPDINTLVL_t; - -/* Low Byte Compare C Interrupt Level */ -typedef enum TC2_LCMPCINTLVL_enum -{ - TC2_LCMPCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ - TC2_LCMPCINTLVL_LO_gc = (0x01<<4), /* Low Level */ - TC2_LCMPCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ - TC2_LCMPCINTLVL_HI_gc = (0x03<<4), /* High Level */ -} TC2_LCMPCINTLVL_t; - -/* Low Byte Compare B Interrupt Level */ -typedef enum TC2_LCMPBINTLVL_enum -{ - TC2_LCMPBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ - TC2_LCMPBINTLVL_LO_gc = (0x01<<2), /* Low Level */ - TC2_LCMPBINTLVL_MED_gc = (0x02<<2), /* Medium Level */ - TC2_LCMPBINTLVL_HI_gc = (0x03<<2), /* High Level */ -} TC2_LCMPBINTLVL_t; - -/* Low Byte Compare A Interrupt Level */ -typedef enum TC2_LCMPAINTLVL_enum -{ - TC2_LCMPAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - TC2_LCMPAINTLVL_LO_gc = (0x01<<0), /* Low Level */ - TC2_LCMPAINTLVL_MED_gc = (0x02<<0), /* Medium Level */ - TC2_LCMPAINTLVL_HI_gc = (0x03<<0), /* High Level */ -} TC2_LCMPAINTLVL_t; - -/* Timer/Counter Command */ -typedef enum TC2_CMD_enum -{ - TC2_CMD_NONE_gc = (0x00<<2), /* No Command */ - TC2_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ - TC2_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ -} TC2_CMD_t; - -/* Timer/Counter Command */ -typedef enum TC2_CMDEN_enum -{ - TC2_CMDEN_LOW_gc = (0x01<<0), /* Low Byte Timer/Counter */ - TC2_CMDEN_HIGH_gc = (0x02<<0), /* High Byte Timer/Counter */ - TC2_CMDEN_BOTH_gc = (0x03<<0), /* Both Low Byte and High Byte Timer/Counters */ -} TC2_CMDEN_t; - - -/* --------------------------------------------------------------------------- -AWEX - Timer/Counter Advanced Waveform Extension --------------------------------------------------------------------------- -*/ - -/* Advanced Waveform Extension */ -typedef struct AWEX_struct -{ - register8_t CTRL; /* Control Register */ - register8_t reserved_0x01; - register8_t FDEMASK; /* Fault Detection Event Mask */ - register8_t FDCTRL; /* Fault Detection Control Register */ - register8_t STATUS; /* Status Register */ - register8_t STATUSSET; /* Status Set Register */ - register8_t DTBOTH; /* Dead Time Both Sides */ - register8_t DTBOTHBUF; /* Dead Time Both Sides Buffer */ - register8_t DTLS; /* Dead Time Low Side */ - register8_t DTHS; /* Dead Time High Side */ - register8_t DTLSBUF; /* Dead Time Low Side Buffer */ - register8_t DTHSBUF; /* Dead Time High Side Buffer */ - register8_t OUTOVEN; /* Output Override Enable */ -} AWEX_t; - -/* Fault Detect Action */ -typedef enum AWEX_FDACT_enum -{ - AWEX_FDACT_NONE_gc = (0x00<<0), /* No Fault Protection */ - AWEX_FDACT_CLEAROE_gc = (0x01<<0), /* Clear Output Enable Bits */ - AWEX_FDACT_CLEARDIR_gc = (0x03<<0), /* Clear I/O Port Direction Bits */ -} AWEX_FDACT_t; - - -/* --------------------------------------------------------------------------- -HIRES - Timer/Counter High-Resolution Extension --------------------------------------------------------------------------- -*/ - -/* High-Resolution Extension */ -typedef struct HIRES_struct -{ - register8_t CTRLA; /* Control Register */ -} HIRES_t; - -/* High Resolution Enable */ -typedef enum HIRES_HREN_enum -{ - HIRES_HREN_NONE_gc = (0x00<<0), /* No Fault Protection */ - HIRES_HREN_TC0_gc = (0x01<<0), /* Enable High Resolution on Timer/Counter 0 */ - HIRES_HREN_TC1_gc = (0x02<<0), /* Enable High Resolution on Timer/Counter 1 */ - HIRES_HREN_BOTH_gc = (0x03<<0), /* Enable High Resolution both Timer/Counters */ -} HIRES_HREN_t; - - -/* --------------------------------------------------------------------------- -USART - Universal Asynchronous Receiver-Transmitter --------------------------------------------------------------------------- -*/ - -/* Universal Synchronous/Asynchronous Receiver/Transmitter */ -typedef struct USART_struct -{ - register8_t DATA; /* Data Register */ - register8_t STATUS; /* Status Register */ - register8_t reserved_0x02; - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t CTRLC; /* Control Register C */ - register8_t BAUDCTRLA; /* Baud Rate Control Register A */ - register8_t BAUDCTRLB; /* Baud Rate Control Register B */ -} USART_t; - -/* Receive Complete Interrupt level */ -typedef enum USART_RXCINTLVL_enum -{ - USART_RXCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ - USART_RXCINTLVL_LO_gc = (0x01<<4), /* Low Level */ - USART_RXCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ - USART_RXCINTLVL_HI_gc = (0x03<<4), /* High Level */ -} USART_RXCINTLVL_t; - -/* Transmit Complete Interrupt level */ -typedef enum USART_TXCINTLVL_enum -{ - USART_TXCINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ - USART_TXCINTLVL_LO_gc = (0x01<<2), /* Low Level */ - USART_TXCINTLVL_MED_gc = (0x02<<2), /* Medium Level */ - USART_TXCINTLVL_HI_gc = (0x03<<2), /* High Level */ -} USART_TXCINTLVL_t; - -/* Data Register Empty Interrupt level */ -typedef enum USART_DREINTLVL_enum -{ - USART_DREINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - USART_DREINTLVL_LO_gc = (0x01<<0), /* Low Level */ - USART_DREINTLVL_MED_gc = (0x02<<0), /* Medium Level */ - USART_DREINTLVL_HI_gc = (0x03<<0), /* High Level */ -} USART_DREINTLVL_t; - -/* Character Size */ -typedef enum USART_CHSIZE_enum -{ - USART_CHSIZE_5BIT_gc = (0x00<<0), /* Character size: 5 bit */ - USART_CHSIZE_6BIT_gc = (0x01<<0), /* Character size: 6 bit */ - USART_CHSIZE_7BIT_gc = (0x02<<0), /* Character size: 7 bit */ - USART_CHSIZE_8BIT_gc = (0x03<<0), /* Character size: 8 bit */ - USART_CHSIZE_9BIT_gc = (0x07<<0), /* Character size: 9 bit */ -} USART_CHSIZE_t; - -/* Communication Mode */ -typedef enum USART_CMODE_enum -{ - USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6), /* Asynchronous Mode */ - USART_CMODE_SYNCHRONOUS_gc = (0x01<<6), /* Synchronous Mode */ - USART_CMODE_IRDA_gc = (0x02<<6), /* IrDA Mode */ - USART_CMODE_MSPI_gc = (0x03<<6), /* Master SPI Mode */ -} USART_CMODE_t; - -/* Parity Mode */ -typedef enum USART_PMODE_enum -{ - USART_PMODE_DISABLED_gc = (0x00<<4), /* No Parity */ - USART_PMODE_EVEN_gc = (0x02<<4), /* Even Parity */ - USART_PMODE_ODD_gc = (0x03<<4), /* Odd Parity */ -} USART_PMODE_t; - - -/* --------------------------------------------------------------------------- -SPI - Serial Peripheral Interface --------------------------------------------------------------------------- -*/ - -/* Serial Peripheral Interface */ -typedef struct SPI_struct -{ - register8_t CTRL; /* Control Register */ - register8_t INTCTRL; /* Interrupt Control Register */ - register8_t STATUS; /* Status Register */ - register8_t DATA; /* Data Register */ -} SPI_t; - -/* SPI Mode */ -typedef enum SPI_MODE_enum -{ - SPI_MODE_0_gc = (0x00<<2), /* SPI Mode 0 */ - SPI_MODE_1_gc = (0x01<<2), /* SPI Mode 1 */ - SPI_MODE_2_gc = (0x02<<2), /* SPI Mode 2 */ - SPI_MODE_3_gc = (0x03<<2), /* SPI Mode 3 */ -} SPI_MODE_t; - -/* Prescaler setting */ -typedef enum SPI_PRESCALER_enum -{ - SPI_PRESCALER_DIV4_gc = (0x00<<0), /* System Clock / 4 */ - SPI_PRESCALER_DIV16_gc = (0x01<<0), /* System Clock / 16 */ - SPI_PRESCALER_DIV64_gc = (0x02<<0), /* System Clock / 64 */ - SPI_PRESCALER_DIV128_gc = (0x03<<0), /* System Clock / 128 */ -} SPI_PRESCALER_t; - -/* Interrupt level */ -typedef enum SPI_INTLVL_enum -{ - SPI_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - SPI_INTLVL_LO_gc = (0x01<<0), /* Low Level */ - SPI_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ - SPI_INTLVL_HI_gc = (0x03<<0), /* High Level */ -} SPI_INTLVL_t; - - -/* --------------------------------------------------------------------------- -IRCOM - IR Communication Module --------------------------------------------------------------------------- -*/ - -/* IR Communication Module */ -typedef struct IRCOM_struct -{ - register8_t CTRL; /* Control Register */ - register8_t TXPLCTRL; /* IrDA Transmitter Pulse Length Control Register */ - register8_t RXPLCTRL; /* IrDA Receiver Pulse Length Control Register */ -} IRCOM_t; - -/* Event channel selection */ -typedef enum IRDA_EVSEL_enum -{ - IRDA_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ - IRDA_EVSEL_0_gc = (0x08<<0), /* Event Channel 0 */ - IRDA_EVSEL_1_gc = (0x09<<0), /* Event Channel 1 */ - IRDA_EVSEL_2_gc = (0x0A<<0), /* Event Channel 2 */ - IRDA_EVSEL_3_gc = (0x0B<<0), /* Event Channel 3 */ -} IRDA_EVSEL_t; - - -/* --------------------------------------------------------------------------- -FUSE - Fuses and Lockbits --------------------------------------------------------------------------- -*/ - -/* Fuses */ -typedef struct NVM_FUSES_struct -{ - register8_t reserved_0x00; - register8_t FUSEBYTE1; /* Watchdog Configuration */ - register8_t FUSEBYTE2; /* Reset Configuration */ - register8_t reserved_0x03; - register8_t FUSEBYTE4; /* Start-up Configuration */ - register8_t FUSEBYTE5; /* EESAVE and BOD Level */ -} NVM_FUSES_t; - -/* Boot Loader Section Reset Vector */ -typedef enum BOOTRST_enum -{ - BOOTRST_BOOTLDR_gc = (0x00<<6), /* Boot Loader Reset */ - BOOTRST_APPLICATION_gc = (0x01<<6), /* Application Reset */ -} BOOTRST_t; - -/* Timer Oscillator pin location */ -typedef enum TOSCSEL_enum -{ - TOSCSEL_ALTERNATE_gc = (0x00<<5), /* TOSC1 / TOSC2 on separate pins */ - TOSCSEL_XTAL_gc = (0x01<<5), /* TOSC1 / TOSC2 shared with XTAL1 / XTAL2 */ -} TOSCSEL_t; - -/* BOD operation */ -typedef enum BOD_enum -{ - BOD_SAMPLED_gc = (0x01<<0), /* BOD enabled in sampled mode */ - BOD_CONTINUOUS_gc = (0x02<<0), /* BOD enabled continuously */ - BOD_DISABLED_gc = (0x03<<0), /* BOD Disabled */ -} BOD_t; - -/* BOD operation */ -typedef enum BODACT_enum -{ - BODACT_SAMPLED_gc = (0x01<<4), /* BOD enabled in sampled mode */ - BODACT_CONTINUOUS_gc = (0x02<<4), /* BOD enabled continuously */ - BODACT_DISABLED_gc = (0x03<<4), /* BOD Disabled */ -} BODACT_t; - -/* Watchdog (Window) Timeout Period */ -typedef enum WD_enum -{ - WD_8CLK_gc = (0x00<<4), /* 8 cycles (8ms @ 3.3V) */ - WD_16CLK_gc = (0x01<<4), /* 16 cycles (16ms @ 3.3V) */ - WD_32CLK_gc = (0x02<<4), /* 32 cycles (32ms @ 3.3V) */ - WD_64CLK_gc = (0x03<<4), /* 64 cycles (64ms @ 3.3V) */ - WD_128CLK_gc = (0x04<<4), /* 128 cycles (0.125s @ 3.3V) */ - WD_256CLK_gc = (0x05<<4), /* 256 cycles (0.25s @ 3.3V) */ - WD_512CLK_gc = (0x06<<4), /* 512 cycles (0.5s @ 3.3V) */ - WD_1KCLK_gc = (0x07<<4), /* 1K cycles (1s @ 3.3V) */ - WD_2KCLK_gc = (0x08<<4), /* 2K cycles (2s @ 3.3V) */ - WD_4KCLK_gc = (0x09<<4), /* 4K cycles (4s @ 3.3V) */ - WD_8KCLK_gc = (0x0A<<4), /* 8K cycles (8s @ 3.3V) */ -} WD_t; - -/* Watchdog (Window) Timeout Period */ -typedef enum WDP_enum -{ - WDP_8CLK_gc = (0x00<<0), /* 8 cycles (8ms @ 3.3V) */ - WDP_16CLK_gc = (0x01<<0), /* 16 cycles (16ms @ 3.3V) */ - WDP_32CLK_gc = (0x02<<0), /* 32 cycles (32ms @ 3.3V) */ - WDP_64CLK_gc = (0x03<<0), /* 64 cycles (64ms @ 3.3V) */ - WDP_128CLK_gc = (0x04<<0), /* 128 cycles (0.125s @ 3.3V) */ - WDP_256CLK_gc = (0x05<<0), /* 256 cycles (0.25s @ 3.3V) */ - WDP_512CLK_gc = (0x06<<0), /* 512 cycles (0.5s @ 3.3V) */ - WDP_1KCLK_gc = (0x07<<0), /* 1K cycles (1s @ 3.3V) */ - WDP_2KCLK_gc = (0x08<<0), /* 2K cycles (2s @ 3.3V) */ - WDP_4KCLK_gc = (0x09<<0), /* 4K cycles (4s @ 3.3V) */ - WDP_8KCLK_gc = (0x0A<<0), /* 8K cycles (8s @ 3.3V) */ -} WDP_t; - -/* Start-up Time */ -typedef enum SUT_enum -{ - SUT_0MS_gc = (0x03<<2), /* 0 ms */ - SUT_4MS_gc = (0x01<<2), /* 4 ms */ - SUT_64MS_gc = (0x00<<2), /* 64 ms */ -} SUT_t; - -/* Brownout Detection Voltage Level */ -typedef enum BODLVL_enum -{ - BODLVL_1V6_gc = (0x07<<0), /* 1.6 V */ - BODLVL_1V8_gc = (0x06<<0), /* 1.8 V */ - BODLVL_2V0_gc = (0x05<<0), /* 2.0 V */ - BODLVL_2V2_gc = (0x04<<0), /* 2.2 V */ - BODLVL_2V4_gc = (0x03<<0), /* 2.4 V */ - BODLVL_2V6_gc = (0x02<<0), /* 2.6 V */ - BODLVL_2V8_gc = (0x01<<0), /* 2.8 V */ - BODLVL_3V0_gc = (0x00<<0), /* 3.0 V */ -} BODLVL_t; - - -/* --------------------------------------------------------------------------- -LOCKBIT - Fuses and Lockbits --------------------------------------------------------------------------- -*/ - -/* Lock Bits */ -typedef struct NVM_LOCKBITS_struct -{ - register8_t LOCK_BITS; /* Lock Bits (Changed from LOCKBITS to avoid avr-libc collision) */ -} NVM_LOCKBITS_t; - -/* Boot lock bits - boot setcion */ -typedef enum FUSE_BLBB_enum -{ - FUSE_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ - FUSE_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ - FUSE_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ - FUSE_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ -} FUSE_BLBB_t; - -/* Boot lock bits - application section */ -typedef enum FUSE_BLBA_enum -{ - FUSE_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ - FUSE_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ - FUSE_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ - FUSE_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ -} FUSE_BLBA_t; - -/* Boot lock bits - application table section */ -typedef enum FUSE_BLBAT_enum -{ - FUSE_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ - FUSE_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ - FUSE_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ - FUSE_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ -} FUSE_BLBAT_t; - -/* Lock bits */ -typedef enum FUSE_LB_enum -{ - FUSE_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ - FUSE_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ - FUSE_LB_NOLOCK_gc = (0x03<<0), /* No locks */ -} FUSE_LB_t; - - -/* --------------------------------------------------------------------------- -SIGROW - Signature Row --------------------------------------------------------------------------- -*/ - -/* Production Signatures */ -typedef struct NVM_PROD_SIGNATURES_struct -{ - register8_t RCOSC2M; /* RCOSC 2 MHz Calibration Value B */ - register8_t RCOSC2MA; /* RCOSC 2 MHz Calibration Value A */ - register8_t RCOSC32K; /* RCOSC 32.768 kHz Calibration Value */ - register8_t RCOSC32M; /* RCOSC 32 MHz Calibration Value B */ - register8_t RCOSC32MA; /* RCOSC 32 MHz Calibration Value A */ - register8_t reserved_0x05; - register8_t reserved_0x06; - register8_t reserved_0x07; - register8_t LOTNUM0; /* Lot Number Byte 0, ASCII */ - register8_t LOTNUM1; /* Lot Number Byte 1, ASCII */ - register8_t LOTNUM2; /* Lot Number Byte 2, ASCII */ - register8_t LOTNUM3; /* Lot Number Byte 3, ASCII */ - register8_t LOTNUM4; /* Lot Number Byte 4, ASCII */ - register8_t LOTNUM5; /* Lot Number Byte 5, ASCII */ - register8_t reserved_0x0E; - register8_t reserved_0x0F; - register8_t WAFNUM; /* Wafer Number */ - register8_t reserved_0x11; - register8_t COORDX0; /* Wafer Coordinate X Byte 0 */ - register8_t COORDX1; /* Wafer Coordinate X Byte 1 */ - register8_t COORDY0; /* Wafer Coordinate Y Byte 0 */ - register8_t COORDY1; /* Wafer Coordinate Y Byte 1 */ - register8_t reserved_0x16; - register8_t reserved_0x17; - register8_t reserved_0x18; - register8_t reserved_0x19; - register8_t reserved_0x1A; - register8_t reserved_0x1B; - register8_t reserved_0x1C; - register8_t reserved_0x1D; - register8_t reserved_0x1E; - register8_t reserved_0x1F; - register8_t ADCACAL0; /* ADCA Calibration Byte 0 */ - register8_t ADCACAL1; /* ADCA Calibration Byte 1 */ - register8_t reserved_0x22; - register8_t reserved_0x23; - register8_t reserved_0x24; - register8_t reserved_0x25; - register8_t reserved_0x26; - register8_t reserved_0x27; - register8_t reserved_0x28; - register8_t reserved_0x29; - register8_t reserved_0x2A; - register8_t reserved_0x2B; - register8_t reserved_0x2C; - register8_t reserved_0x2D; - register8_t TEMPSENSE0; /* Temperature Sensor Calibration Byte 0 */ - register8_t TEMPSENSE1; /* Temperature Sensor Calibration Byte 1 */ - register8_t reserved_0x30; - register8_t reserved_0x31; - register8_t reserved_0x32; - register8_t reserved_0x33; - register8_t reserved_0x34; - register8_t reserved_0x35; - register8_t reserved_0x36; - register8_t reserved_0x37; - register8_t reserved_0x38; - register8_t reserved_0x39; - register8_t reserved_0x3A; - register8_t reserved_0x3B; - register8_t reserved_0x3C; - register8_t reserved_0x3D; - register8_t reserved_0x3E; - register8_t reserved_0x3F; -} NVM_PROD_SIGNATURES_t; - -/* -========================================================================== -IO Module Instances. Mapped to memory. -========================================================================== -*/ - -#define VPORT0 (*(VPORT_t *) 0x0010) /* Virtual Port */ -#define VPORT1 (*(VPORT_t *) 0x0014) /* Virtual Port */ -#define VPORT2 (*(VPORT_t *) 0x0018) /* Virtual Port */ -#define VPORT3 (*(VPORT_t *) 0x001C) /* Virtual Port */ -#define OCD (*(OCD_t *) 0x002E) /* On-Chip Debug System */ -#define CLK (*(CLK_t *) 0x0040) /* Clock System */ -#define SLEEP (*(SLEEP_t *) 0x0048) /* Sleep Controller */ -#define OSC (*(OSC_t *) 0x0050) /* Oscillator */ -#define DFLLRC32M (*(DFLL_t *) 0x0060) /* DFLL */ -#define DFLLRC2M (*(DFLL_t *) 0x0068) /* DFLL */ -#define PR (*(PR_t *) 0x0070) /* Power Reduction */ -#define RST (*(RST_t *) 0x0078) /* Reset */ -#define WDT (*(WDT_t *) 0x0080) /* Watch-Dog Timer */ -#define MCU (*(MCU_t *) 0x0090) /* MCU Control */ -#define PMIC (*(PMIC_t *) 0x00A0) /* Programmable Multi-level Interrupt Controller */ -#define PORTCFG (*(PORTCFG_t *) 0x00B0) /* I/O port Configuration */ -#define CRC (*(CRC_t *) 0x00D0) /* Cyclic Redundancy Checker */ -#define EVSYS (*(EVSYS_t *) 0x0180) /* Event System */ -#define NVM (*(NVM_t *) 0x01C0) /* Non-volatile Memory Controller */ -#define ADCA (*(ADC_t *) 0x0200) /* Analog-to-Digital Converter */ -#define ACA (*(AC_t *) 0x0380) /* Analog Comparator */ -#define RTC (*(RTC_t *) 0x0400) /* Real-Time Counter */ -#define TWIC (*(TWI_t *) 0x0480) /* Two-Wire Interface */ -#define TWIE (*(TWI_t *) 0x04A0) /* Two-Wire Interface */ -#define PORTA (*(PORT_t *) 0x0600) /* I/O Ports */ -#define PORTB (*(PORT_t *) 0x0620) /* I/O Ports */ -#define PORTC (*(PORT_t *) 0x0640) /* I/O Ports */ -#define PORTD (*(PORT_t *) 0x0660) /* I/O Ports */ -#define PORTE (*(PORT_t *) 0x0680) /* I/O Ports */ -#define PORTR (*(PORT_t *) 0x07E0) /* I/O Ports */ -#define TCC0 (*(TC0_t *) 0x0800) /* 16-bit Timer/Counter 0 */ -#define TCC2 (*(TC2_t *) 0x0800) /* 16-bit Timer/Counter type 2 */ -#define TCC1 (*(TC1_t *) 0x0840) /* 16-bit Timer/Counter 1 */ -#define AWEXC (*(AWEX_t *) 0x0880) /* Advanced Waveform Extension */ -#define HIRESC (*(HIRES_t *) 0x0890) /* High-Resolution Extension */ -#define USARTC0 (*(USART_t *) 0x08A0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ -#define SPIC (*(SPI_t *) 0x08C0) /* Serial Peripheral Interface */ -#define IRCOM (*(IRCOM_t *) 0x08F8) /* IR Communication Module */ -#define TCD0 (*(TC0_t *) 0x0900) /* 16-bit Timer/Counter 0 */ -#define TCD2 (*(TC2_t *) 0x0900) /* 16-bit Timer/Counter type 2 */ -#define USARTD0 (*(USART_t *) 0x09A0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ -#define SPID (*(SPI_t *) 0x09C0) /* Serial Peripheral Interface */ -#define TCE0 (*(TC0_t *) 0x0A00) /* 16-bit Timer/Counter 0 */ - - -#endif /* !defined (__ASSEMBLER__) */ - - -/* ========== Flattened fully qualified IO register names ========== */ - -/* GPIO - General Purpose IO Registers */ -#define GPIO_GPIOR0 _SFR_MEM8(0x0000) -#define GPIO_GPIOR1 _SFR_MEM8(0x0001) -#define GPIO_GPIOR2 _SFR_MEM8(0x0002) -#define GPIO_GPIOR3 _SFR_MEM8(0x0003) - -/* Deprecated */ -#define GPIO_GPIO0 _SFR_MEM8(0x0000) -#define GPIO_GPIO1 _SFR_MEM8(0x0001) -#define GPIO_GPIO2 _SFR_MEM8(0x0002) -#define GPIO_GPIO3 _SFR_MEM8(0x0003) - -/* NVM_FUSES - Fuses */ -#define FUSE_FUSEBYTE1 _SFR_MEM8(0x0001) -#define FUSE_FUSEBYTE2 _SFR_MEM8(0x0002) -#define FUSE_FUSEBYTE4 _SFR_MEM8(0x0004) -#define FUSE_FUSEBYTE5 _SFR_MEM8(0x0005) - -/* NVM_LOCKBITS - Lock Bits */ -#define LOCKBIT_LOCKBITS _SFR_MEM8(0x0000) - -/* NVM_PROD_SIGNATURES - Production Signatures */ -#define PRODSIGNATURES_RCOSC2M _SFR_MEM8(0x0000) -#define PRODSIGNATURES_RCOSC2MA _SFR_MEM8(0x0001) -#define PRODSIGNATURES_RCOSC32K _SFR_MEM8(0x0002) -#define PRODSIGNATURES_RCOSC32M _SFR_MEM8(0x0003) -#define PRODSIGNATURES_RCOSC32MA _SFR_MEM8(0x0004) -#define PRODSIGNATURES_LOTNUM0 _SFR_MEM8(0x0008) -#define PRODSIGNATURES_LOTNUM1 _SFR_MEM8(0x0009) -#define PRODSIGNATURES_LOTNUM2 _SFR_MEM8(0x000A) -#define PRODSIGNATURES_LOTNUM3 _SFR_MEM8(0x000B) -#define PRODSIGNATURES_LOTNUM4 _SFR_MEM8(0x000C) -#define PRODSIGNATURES_LOTNUM5 _SFR_MEM8(0x000D) -#define PRODSIGNATURES_WAFNUM _SFR_MEM8(0x0010) -#define PRODSIGNATURES_COORDX0 _SFR_MEM8(0x0012) -#define PRODSIGNATURES_COORDX1 _SFR_MEM8(0x0013) -#define PRODSIGNATURES_COORDY0 _SFR_MEM8(0x0014) -#define PRODSIGNATURES_COORDY1 _SFR_MEM8(0x0015) -#define PRODSIGNATURES_ADCACAL0 _SFR_MEM8(0x0020) -#define PRODSIGNATURES_ADCACAL1 _SFR_MEM8(0x0021) -#define PRODSIGNATURES_TEMPSENSE0 _SFR_MEM8(0x002E) -#define PRODSIGNATURES_TEMPSENSE1 _SFR_MEM8(0x002F) - -/* VPORT - Virtual Port */ -#define VPORT0_DIR _SFR_MEM8(0x0010) -#define VPORT0_OUT _SFR_MEM8(0x0011) -#define VPORT0_IN _SFR_MEM8(0x0012) -#define VPORT0_INTFLAGS _SFR_MEM8(0x0013) - -/* VPORT - Virtual Port */ -#define VPORT1_DIR _SFR_MEM8(0x0014) -#define VPORT1_OUT _SFR_MEM8(0x0015) -#define VPORT1_IN _SFR_MEM8(0x0016) -#define VPORT1_INTFLAGS _SFR_MEM8(0x0017) - -/* VPORT - Virtual Port */ -#define VPORT2_DIR _SFR_MEM8(0x0018) -#define VPORT2_OUT _SFR_MEM8(0x0019) -#define VPORT2_IN _SFR_MEM8(0x001A) -#define VPORT2_INTFLAGS _SFR_MEM8(0x001B) - -/* VPORT - Virtual Port */ -#define VPORT3_DIR _SFR_MEM8(0x001C) -#define VPORT3_OUT _SFR_MEM8(0x001D) -#define VPORT3_IN _SFR_MEM8(0x001E) -#define VPORT3_INTFLAGS _SFR_MEM8(0x001F) - -/* OCD - On-Chip Debug System */ -#define OCD_OCDR0 _SFR_MEM8(0x002E) -#define OCD_OCDR1 _SFR_MEM8(0x002F) - -/* CPU - CPU registers */ -#define CPU_CCP _SFR_MEM8(0x0034) -#define CPU_RAMPD _SFR_MEM8(0x0038) -#define CPU_RAMPX _SFR_MEM8(0x0039) -#define CPU_RAMPY _SFR_MEM8(0x003A) -#define CPU_RAMPZ _SFR_MEM8(0x003B) -#define CPU_EIND _SFR_MEM8(0x003C) -#define CPU_SPL _SFR_MEM8(0x003D) -#define CPU_SPH _SFR_MEM8(0x003E) -#define CPU_SREG _SFR_MEM8(0x003F) - -/* CLK - Clock System */ -#define CLK_CTRL _SFR_MEM8(0x0040) -#define CLK_PSCTRL _SFR_MEM8(0x0041) -#define CLK_LOCK _SFR_MEM8(0x0042) -#define CLK_RTCCTRL _SFR_MEM8(0x0043) - -/* SLEEP - Sleep Controller */ -#define SLEEP_CTRL _SFR_MEM8(0x0048) - -/* OSC - Oscillator */ -#define OSC_CTRL _SFR_MEM8(0x0050) -#define OSC_STATUS _SFR_MEM8(0x0051) -#define OSC_XOSCCTRL _SFR_MEM8(0x0052) -#define OSC_XOSCFAIL _SFR_MEM8(0x0053) -#define OSC_RC32KCAL _SFR_MEM8(0x0054) -#define OSC_PLLCTRL _SFR_MEM8(0x0055) -#define OSC_DFLLCTRL _SFR_MEM8(0x0056) - -/* DFLL - DFLL */ -#define DFLLRC32M_CTRL _SFR_MEM8(0x0060) -#define DFLLRC32M_CALA _SFR_MEM8(0x0062) -#define DFLLRC32M_CALB _SFR_MEM8(0x0063) -#define DFLLRC32M_COMP0 _SFR_MEM8(0x0064) -#define DFLLRC32M_COMP1 _SFR_MEM8(0x0065) -#define DFLLRC32M_COMP2 _SFR_MEM8(0x0066) - -/* DFLL - DFLL */ -#define DFLLRC2M_CTRL _SFR_MEM8(0x0068) -#define DFLLRC2M_CALA _SFR_MEM8(0x006A) -#define DFLLRC2M_CALB _SFR_MEM8(0x006B) -#define DFLLRC2M_COMP0 _SFR_MEM8(0x006C) -#define DFLLRC2M_COMP1 _SFR_MEM8(0x006D) -#define DFLLRC2M_COMP2 _SFR_MEM8(0x006E) - -/* PR - Power Reduction */ -#define PR_PRGEN _SFR_MEM8(0x0070) -#define PR_PRPA _SFR_MEM8(0x0071) -#define PR_PRPC _SFR_MEM8(0x0073) -#define PR_PRPD _SFR_MEM8(0x0074) -#define PR_PRPE _SFR_MEM8(0x0075) -#define PR_PRPF _SFR_MEM8(0x0076) - -/* RST - Reset */ -#define RST_STATUS _SFR_MEM8(0x0078) -#define RST_CTRL _SFR_MEM8(0x0079) - -/* WDT - Watch-Dog Timer */ -#define WDT_CTRL _SFR_MEM8(0x0080) -#define WDT_WINCTRL _SFR_MEM8(0x0081) -#define WDT_STATUS _SFR_MEM8(0x0082) - -/* MCU - MCU Control */ -#define MCU_DEVID0 _SFR_MEM8(0x0090) -#define MCU_DEVID1 _SFR_MEM8(0x0091) -#define MCU_DEVID2 _SFR_MEM8(0x0092) -#define MCU_REVID _SFR_MEM8(0x0093) -#define MCU_ANAINIT _SFR_MEM8(0x0097) -#define MCU_EVSYSLOCK _SFR_MEM8(0x0098) -#define MCU_AWEXLOCK _SFR_MEM8(0x0099) - -/* PMIC - Programmable Multi-level Interrupt Controller */ -#define PMIC_STATUS _SFR_MEM8(0x00A0) -#define PMIC_INTPRI _SFR_MEM8(0x00A1) -#define PMIC_CTRL _SFR_MEM8(0x00A2) - -/* PORTCFG - I/O port Configuration */ -#define PORTCFG_MPCMASK _SFR_MEM8(0x00B0) -#define PORTCFG_VPCTRLA _SFR_MEM8(0x00B2) -#define PORTCFG_VPCTRLB _SFR_MEM8(0x00B3) -#define PORTCFG_CLKEVOUT _SFR_MEM8(0x00B4) -#define PORTCFG_EVOUTSEL _SFR_MEM8(0x00B6) - -/* CRC - Cyclic Redundancy Checker */ -#define CRC_CTRL _SFR_MEM8(0x00D0) -#define CRC_STATUS _SFR_MEM8(0x00D1) -#define CRC_DATAIN _SFR_MEM8(0x00D3) -#define CRC_CHECKSUM0 _SFR_MEM8(0x00D4) -#define CRC_CHECKSUM1 _SFR_MEM8(0x00D5) -#define CRC_CHECKSUM2 _SFR_MEM8(0x00D6) -#define CRC_CHECKSUM3 _SFR_MEM8(0x00D7) - -/* EVSYS - Event System */ -#define EVSYS_CH0MUX _SFR_MEM8(0x0180) -#define EVSYS_CH1MUX _SFR_MEM8(0x0181) -#define EVSYS_CH2MUX _SFR_MEM8(0x0182) -#define EVSYS_CH3MUX _SFR_MEM8(0x0183) -#define EVSYS_CH0CTRL _SFR_MEM8(0x0188) -#define EVSYS_CH1CTRL _SFR_MEM8(0x0189) -#define EVSYS_CH2CTRL _SFR_MEM8(0x018A) -#define EVSYS_CH3CTRL _SFR_MEM8(0x018B) -#define EVSYS_STROBE _SFR_MEM8(0x0190) -#define EVSYS_DATA _SFR_MEM8(0x0191) - -/* NVM - Non-volatile Memory Controller */ -#define NVM_ADDR0 _SFR_MEM8(0x01C0) -#define NVM_ADDR1 _SFR_MEM8(0x01C1) -#define NVM_ADDR2 _SFR_MEM8(0x01C2) -#define NVM_DATA0 _SFR_MEM8(0x01C4) -#define NVM_DATA1 _SFR_MEM8(0x01C5) -#define NVM_DATA2 _SFR_MEM8(0x01C6) -#define NVM_CMD _SFR_MEM8(0x01CA) -#define NVM_CTRLA _SFR_MEM8(0x01CB) -#define NVM_CTRLB _SFR_MEM8(0x01CC) -#define NVM_INTCTRL _SFR_MEM8(0x01CD) -#define NVM_STATUS _SFR_MEM8(0x01CF) -#define NVM_LOCKBITS _SFR_MEM8(0x01D0) - -/* ADC - Analog-to-Digital Converter */ -#define ADCA_CTRLA _SFR_MEM8(0x0200) -#define ADCA_CTRLB _SFR_MEM8(0x0201) -#define ADCA_REFCTRL _SFR_MEM8(0x0202) -#define ADCA_EVCTRL _SFR_MEM8(0x0203) -#define ADCA_PRESCALER _SFR_MEM8(0x0204) -#define ADCA_INTFLAGS _SFR_MEM8(0x0206) -#define ADCA_TEMP _SFR_MEM8(0x0207) -#define ADCA_CAL _SFR_MEM16(0x020C) -#define ADCA_CH0RES _SFR_MEM16(0x0210) -#define ADCA_CMP _SFR_MEM16(0x0218) -#define ADCA_CH0_CTRL _SFR_MEM8(0x0220) -#define ADCA_CH0_MUXCTRL _SFR_MEM8(0x0221) -#define ADCA_CH0_INTCTRL _SFR_MEM8(0x0222) -#define ADCA_CH0_INTFLAGS _SFR_MEM8(0x0223) -#define ADCA_CH0_RES _SFR_MEM16(0x0224) -#define ADCA_CH0_SCAN _SFR_MEM8(0x0226) - -/* AC - Analog Comparator */ -#define ACA_AC0CTRL _SFR_MEM8(0x0380) -#define ACA_AC1CTRL _SFR_MEM8(0x0381) -#define ACA_AC0MUXCTRL _SFR_MEM8(0x0382) -#define ACA_AC1MUXCTRL _SFR_MEM8(0x0383) -#define ACA_CTRLA _SFR_MEM8(0x0384) -#define ACA_CTRLB _SFR_MEM8(0x0385) -#define ACA_WINCTRL _SFR_MEM8(0x0386) -#define ACA_STATUS _SFR_MEM8(0x0387) - -/* RTC - Real-Time Counter */ -#define RTC_CTRL _SFR_MEM8(0x0400) -#define RTC_STATUS _SFR_MEM8(0x0401) -#define RTC_INTCTRL _SFR_MEM8(0x0402) -#define RTC_INTFLAGS _SFR_MEM8(0x0403) -#define RTC_TEMP _SFR_MEM8(0x0404) -#define RTC_CNT _SFR_MEM16(0x0408) -#define RTC_PER _SFR_MEM16(0x040A) -#define RTC_COMP _SFR_MEM16(0x040C) - -/* TWI - Two-Wire Interface */ -#define TWIC_CTRL _SFR_MEM8(0x0480) -#define TWIC_MASTER_CTRLA _SFR_MEM8(0x0481) -#define TWIC_MASTER_CTRLB _SFR_MEM8(0x0482) -#define TWIC_MASTER_CTRLC _SFR_MEM8(0x0483) -#define TWIC_MASTER_STATUS _SFR_MEM8(0x0484) -#define TWIC_MASTER_BAUD _SFR_MEM8(0x0485) -#define TWIC_MASTER_ADDR _SFR_MEM8(0x0486) -#define TWIC_MASTER_DATA _SFR_MEM8(0x0487) -#define TWIC_SLAVE_CTRLA _SFR_MEM8(0x0488) -#define TWIC_SLAVE_CTRLB _SFR_MEM8(0x0489) -#define TWIC_SLAVE_STATUS _SFR_MEM8(0x048A) -#define TWIC_SLAVE_ADDR _SFR_MEM8(0x048B) -#define TWIC_SLAVE_DATA _SFR_MEM8(0x048C) -#define TWIC_SLAVE_ADDRMASK _SFR_MEM8(0x048D) - -/* TWI - Two-Wire Interface */ -#define TWIE_CTRL _SFR_MEM8(0x04A0) -#define TWIE_MASTER_CTRLA _SFR_MEM8(0x04A1) -#define TWIE_MASTER_CTRLB _SFR_MEM8(0x04A2) -#define TWIE_MASTER_CTRLC _SFR_MEM8(0x04A3) -#define TWIE_MASTER_STATUS _SFR_MEM8(0x04A4) -#define TWIE_MASTER_BAUD _SFR_MEM8(0x04A5) -#define TWIE_MASTER_ADDR _SFR_MEM8(0x04A6) -#define TWIE_MASTER_DATA _SFR_MEM8(0x04A7) -#define TWIE_SLAVE_CTRLA _SFR_MEM8(0x04A8) -#define TWIE_SLAVE_CTRLB _SFR_MEM8(0x04A9) -#define TWIE_SLAVE_STATUS _SFR_MEM8(0x04AA) -#define TWIE_SLAVE_ADDR _SFR_MEM8(0x04AB) -#define TWIE_SLAVE_DATA _SFR_MEM8(0x04AC) -#define TWIE_SLAVE_ADDRMASK _SFR_MEM8(0x04AD) - -/* PORT - I/O Ports */ -#define PORTA_DIR _SFR_MEM8(0x0600) -#define PORTA_DIRSET _SFR_MEM8(0x0601) -#define PORTA_DIRCLR _SFR_MEM8(0x0602) -#define PORTA_DIRTGL _SFR_MEM8(0x0603) -#define PORTA_OUT _SFR_MEM8(0x0604) -#define PORTA_OUTSET _SFR_MEM8(0x0605) -#define PORTA_OUTCLR _SFR_MEM8(0x0606) -#define PORTA_OUTTGL _SFR_MEM8(0x0607) -#define PORTA_IN _SFR_MEM8(0x0608) -#define PORTA_INTCTRL _SFR_MEM8(0x0609) -#define PORTA_INT0MASK _SFR_MEM8(0x060A) -#define PORTA_INT1MASK _SFR_MEM8(0x060B) -#define PORTA_INTFLAGS _SFR_MEM8(0x060C) -#define PORTA_REMAP _SFR_MEM8(0x060E) -#define PORTA_PIN0CTRL _SFR_MEM8(0x0610) -#define PORTA_PIN1CTRL _SFR_MEM8(0x0611) -#define PORTA_PIN2CTRL _SFR_MEM8(0x0612) -#define PORTA_PIN3CTRL _SFR_MEM8(0x0613) -#define PORTA_PIN4CTRL _SFR_MEM8(0x0614) -#define PORTA_PIN5CTRL _SFR_MEM8(0x0615) -#define PORTA_PIN6CTRL _SFR_MEM8(0x0616) -#define PORTA_PIN7CTRL _SFR_MEM8(0x0617) - -/* PORT - I/O Ports */ -#define PORTB_DIR _SFR_MEM8(0x0620) -#define PORTB_DIRSET _SFR_MEM8(0x0621) -#define PORTB_DIRCLR _SFR_MEM8(0x0622) -#define PORTB_DIRTGL _SFR_MEM8(0x0623) -#define PORTB_OUT _SFR_MEM8(0x0624) -#define PORTB_OUTSET _SFR_MEM8(0x0625) -#define PORTB_OUTCLR _SFR_MEM8(0x0626) -#define PORTB_OUTTGL _SFR_MEM8(0x0627) -#define PORTB_IN _SFR_MEM8(0x0628) -#define PORTB_INTCTRL _SFR_MEM8(0x0629) -#define PORTB_INT0MASK _SFR_MEM8(0x062A) -#define PORTB_INT1MASK _SFR_MEM8(0x062B) -#define PORTB_INTFLAGS _SFR_MEM8(0x062C) -#define PORTB_REMAP _SFR_MEM8(0x062E) -#define PORTB_PIN0CTRL _SFR_MEM8(0x0630) -#define PORTB_PIN1CTRL _SFR_MEM8(0x0631) -#define PORTB_PIN2CTRL _SFR_MEM8(0x0632) -#define PORTB_PIN3CTRL _SFR_MEM8(0x0633) -#define PORTB_PIN4CTRL _SFR_MEM8(0x0634) -#define PORTB_PIN5CTRL _SFR_MEM8(0x0635) -#define PORTB_PIN6CTRL _SFR_MEM8(0x0636) -#define PORTB_PIN7CTRL _SFR_MEM8(0x0637) - -/* PORT - I/O Ports */ -#define PORTC_DIR _SFR_MEM8(0x0640) -#define PORTC_DIRSET _SFR_MEM8(0x0641) -#define PORTC_DIRCLR _SFR_MEM8(0x0642) -#define PORTC_DIRTGL _SFR_MEM8(0x0643) -#define PORTC_OUT _SFR_MEM8(0x0644) -#define PORTC_OUTSET _SFR_MEM8(0x0645) -#define PORTC_OUTCLR _SFR_MEM8(0x0646) -#define PORTC_OUTTGL _SFR_MEM8(0x0647) -#define PORTC_IN _SFR_MEM8(0x0648) -#define PORTC_INTCTRL _SFR_MEM8(0x0649) -#define PORTC_INT0MASK _SFR_MEM8(0x064A) -#define PORTC_INT1MASK _SFR_MEM8(0x064B) -#define PORTC_INTFLAGS _SFR_MEM8(0x064C) -#define PORTC_REMAP _SFR_MEM8(0x064E) -#define PORTC_PIN0CTRL _SFR_MEM8(0x0650) -#define PORTC_PIN1CTRL _SFR_MEM8(0x0651) -#define PORTC_PIN2CTRL _SFR_MEM8(0x0652) -#define PORTC_PIN3CTRL _SFR_MEM8(0x0653) -#define PORTC_PIN4CTRL _SFR_MEM8(0x0654) -#define PORTC_PIN5CTRL _SFR_MEM8(0x0655) -#define PORTC_PIN6CTRL _SFR_MEM8(0x0656) -#define PORTC_PIN7CTRL _SFR_MEM8(0x0657) - -/* PORT - I/O Ports */ -#define PORTD_DIR _SFR_MEM8(0x0660) -#define PORTD_DIRSET _SFR_MEM8(0x0661) -#define PORTD_DIRCLR _SFR_MEM8(0x0662) -#define PORTD_DIRTGL _SFR_MEM8(0x0663) -#define PORTD_OUT _SFR_MEM8(0x0664) -#define PORTD_OUTSET _SFR_MEM8(0x0665) -#define PORTD_OUTCLR _SFR_MEM8(0x0666) -#define PORTD_OUTTGL _SFR_MEM8(0x0667) -#define PORTD_IN _SFR_MEM8(0x0668) -#define PORTD_INTCTRL _SFR_MEM8(0x0669) -#define PORTD_INT0MASK _SFR_MEM8(0x066A) -#define PORTD_INT1MASK _SFR_MEM8(0x066B) -#define PORTD_INTFLAGS _SFR_MEM8(0x066C) -#define PORTD_REMAP _SFR_MEM8(0x066E) -#define PORTD_PIN0CTRL _SFR_MEM8(0x0670) -#define PORTD_PIN1CTRL _SFR_MEM8(0x0671) -#define PORTD_PIN2CTRL _SFR_MEM8(0x0672) -#define PORTD_PIN3CTRL _SFR_MEM8(0x0673) -#define PORTD_PIN4CTRL _SFR_MEM8(0x0674) -#define PORTD_PIN5CTRL _SFR_MEM8(0x0675) -#define PORTD_PIN6CTRL _SFR_MEM8(0x0676) -#define PORTD_PIN7CTRL _SFR_MEM8(0x0677) - -/* PORT - I/O Ports */ -#define PORTE_DIR _SFR_MEM8(0x0680) -#define PORTE_DIRSET _SFR_MEM8(0x0681) -#define PORTE_DIRCLR _SFR_MEM8(0x0682) -#define PORTE_DIRTGL _SFR_MEM8(0x0683) -#define PORTE_OUT _SFR_MEM8(0x0684) -#define PORTE_OUTSET _SFR_MEM8(0x0685) -#define PORTE_OUTCLR _SFR_MEM8(0x0686) -#define PORTE_OUTTGL _SFR_MEM8(0x0687) -#define PORTE_IN _SFR_MEM8(0x0688) -#define PORTE_INTCTRL _SFR_MEM8(0x0689) -#define PORTE_INT0MASK _SFR_MEM8(0x068A) -#define PORTE_INT1MASK _SFR_MEM8(0x068B) -#define PORTE_INTFLAGS _SFR_MEM8(0x068C) -#define PORTE_REMAP _SFR_MEM8(0x068E) -#define PORTE_PIN0CTRL _SFR_MEM8(0x0690) -#define PORTE_PIN1CTRL _SFR_MEM8(0x0691) -#define PORTE_PIN2CTRL _SFR_MEM8(0x0692) -#define PORTE_PIN3CTRL _SFR_MEM8(0x0693) -#define PORTE_PIN4CTRL _SFR_MEM8(0x0694) -#define PORTE_PIN5CTRL _SFR_MEM8(0x0695) -#define PORTE_PIN6CTRL _SFR_MEM8(0x0696) -#define PORTE_PIN7CTRL _SFR_MEM8(0x0697) - -/* PORT - I/O Ports */ -#define PORTR_DIR _SFR_MEM8(0x07E0) -#define PORTR_DIRSET _SFR_MEM8(0x07E1) -#define PORTR_DIRCLR _SFR_MEM8(0x07E2) -#define PORTR_DIRTGL _SFR_MEM8(0x07E3) -#define PORTR_OUT _SFR_MEM8(0x07E4) -#define PORTR_OUTSET _SFR_MEM8(0x07E5) -#define PORTR_OUTCLR _SFR_MEM8(0x07E6) -#define PORTR_OUTTGL _SFR_MEM8(0x07E7) -#define PORTR_IN _SFR_MEM8(0x07E8) -#define PORTR_INTCTRL _SFR_MEM8(0x07E9) -#define PORTR_INT0MASK _SFR_MEM8(0x07EA) -#define PORTR_INT1MASK _SFR_MEM8(0x07EB) -#define PORTR_INTFLAGS _SFR_MEM8(0x07EC) -#define PORTR_REMAP _SFR_MEM8(0x07EE) -#define PORTR_PIN0CTRL _SFR_MEM8(0x07F0) -#define PORTR_PIN1CTRL _SFR_MEM8(0x07F1) -#define PORTR_PIN2CTRL _SFR_MEM8(0x07F2) -#define PORTR_PIN3CTRL _SFR_MEM8(0x07F3) -#define PORTR_PIN4CTRL _SFR_MEM8(0x07F4) -#define PORTR_PIN5CTRL _SFR_MEM8(0x07F5) -#define PORTR_PIN6CTRL _SFR_MEM8(0x07F6) -#define PORTR_PIN7CTRL _SFR_MEM8(0x07F7) - -/* TC0 - 16-bit Timer/Counter 0 */ -#define TCC0_CTRLA _SFR_MEM8(0x0800) -#define TCC0_CTRLB _SFR_MEM8(0x0801) -#define TCC0_CTRLC _SFR_MEM8(0x0802) -#define TCC0_CTRLD _SFR_MEM8(0x0803) -#define TCC0_CTRLE _SFR_MEM8(0x0804) -#define TCC0_INTCTRLA _SFR_MEM8(0x0806) -#define TCC0_INTCTRLB _SFR_MEM8(0x0807) -#define TCC0_CTRLFCLR _SFR_MEM8(0x0808) -#define TCC0_CTRLFSET _SFR_MEM8(0x0809) -#define TCC0_CTRLGCLR _SFR_MEM8(0x080A) -#define TCC0_CTRLGSET _SFR_MEM8(0x080B) -#define TCC0_INTFLAGS _SFR_MEM8(0x080C) -#define TCC0_TEMP _SFR_MEM8(0x080F) -#define TCC0_CNT _SFR_MEM16(0x0820) -#define TCC0_PER _SFR_MEM16(0x0826) -#define TCC0_CCA _SFR_MEM16(0x0828) -#define TCC0_CCB _SFR_MEM16(0x082A) -#define TCC0_CCC _SFR_MEM16(0x082C) -#define TCC0_CCD _SFR_MEM16(0x082E) -#define TCC0_PERBUF _SFR_MEM16(0x0836) -#define TCC0_CCABUF _SFR_MEM16(0x0838) -#define TCC0_CCBBUF _SFR_MEM16(0x083A) -#define TCC0_CCCBUF _SFR_MEM16(0x083C) -#define TCC0_CCDBUF _SFR_MEM16(0x083E) - -/* TC2 - 16-bit Timer/Counter type 2 */ -#define TCC2_CTRLA _SFR_MEM8(0x0800) -#define TCC2_CTRLB _SFR_MEM8(0x0801) -#define TCC2_CTRLC _SFR_MEM8(0x0802) -#define TCC2_CTRLE _SFR_MEM8(0x0804) -#define TCC2_INTCTRLA _SFR_MEM8(0x0806) -#define TCC2_INTCTRLB _SFR_MEM8(0x0807) -#define TCC2_CTRLF _SFR_MEM8(0x0809) -#define TCC2_INTFLAGS _SFR_MEM8(0x080C) -#define TCC2_LCNT _SFR_MEM8(0x0820) -#define TCC2_HCNT _SFR_MEM8(0x0821) -#define TCC2_LPER _SFR_MEM8(0x0826) -#define TCC2_HPER _SFR_MEM8(0x0827) -#define TCC2_LCMPA _SFR_MEM8(0x0828) -#define TCC2_HCMPA _SFR_MEM8(0x0829) -#define TCC2_LCMPB _SFR_MEM8(0x082A) -#define TCC2_HCMPB _SFR_MEM8(0x082B) -#define TCC2_LCMPC _SFR_MEM8(0x082C) -#define TCC2_HCMPC _SFR_MEM8(0x082D) -#define TCC2_LCMPD _SFR_MEM8(0x082E) -#define TCC2_HCMPD _SFR_MEM8(0x082F) - -/* TC1 - 16-bit Timer/Counter 1 */ -#define TCC1_CTRLA _SFR_MEM8(0x0840) -#define TCC1_CTRLB _SFR_MEM8(0x0841) -#define TCC1_CTRLC _SFR_MEM8(0x0842) -#define TCC1_CTRLD _SFR_MEM8(0x0843) -#define TCC1_CTRLE _SFR_MEM8(0x0844) -#define TCC1_INTCTRLA _SFR_MEM8(0x0846) -#define TCC1_INTCTRLB _SFR_MEM8(0x0847) -#define TCC1_CTRLFCLR _SFR_MEM8(0x0848) -#define TCC1_CTRLFSET _SFR_MEM8(0x0849) -#define TCC1_CTRLGCLR _SFR_MEM8(0x084A) -#define TCC1_CTRLGSET _SFR_MEM8(0x084B) -#define TCC1_INTFLAGS _SFR_MEM8(0x084C) -#define TCC1_TEMP _SFR_MEM8(0x084F) -#define TCC1_CNT _SFR_MEM16(0x0860) -#define TCC1_PER _SFR_MEM16(0x0866) -#define TCC1_CCA _SFR_MEM16(0x0868) -#define TCC1_CCB _SFR_MEM16(0x086A) -#define TCC1_PERBUF _SFR_MEM16(0x0876) -#define TCC1_CCABUF _SFR_MEM16(0x0878) -#define TCC1_CCBBUF _SFR_MEM16(0x087A) - -/* AWEX - Advanced Waveform Extension */ -#define AWEXC_CTRL _SFR_MEM8(0x0880) -#define AWEXC_FDEMASK _SFR_MEM8(0x0882) -#define AWEXC_FDCTRL _SFR_MEM8(0x0883) -#define AWEXC_STATUS _SFR_MEM8(0x0884) -#define AWEXC_STATUSSET _SFR_MEM8(0x0885) -#define AWEXC_DTBOTH _SFR_MEM8(0x0886) -#define AWEXC_DTBOTHBUF _SFR_MEM8(0x0887) -#define AWEXC_DTLS _SFR_MEM8(0x0888) -#define AWEXC_DTHS _SFR_MEM8(0x0889) -#define AWEXC_DTLSBUF _SFR_MEM8(0x088A) -#define AWEXC_DTHSBUF _SFR_MEM8(0x088B) -#define AWEXC_OUTOVEN _SFR_MEM8(0x088C) - -/* HIRES - High-Resolution Extension */ -#define HIRESC_CTRLA _SFR_MEM8(0x0890) - -/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ -#define USARTC0_DATA _SFR_MEM8(0x08A0) -#define USARTC0_STATUS _SFR_MEM8(0x08A1) -#define USARTC0_CTRLA _SFR_MEM8(0x08A3) -#define USARTC0_CTRLB _SFR_MEM8(0x08A4) -#define USARTC0_CTRLC _SFR_MEM8(0x08A5) -#define USARTC0_BAUDCTRLA _SFR_MEM8(0x08A6) -#define USARTC0_BAUDCTRLB _SFR_MEM8(0x08A7) - -/* SPI - Serial Peripheral Interface */ -#define SPIC_CTRL _SFR_MEM8(0x08C0) -#define SPIC_INTCTRL _SFR_MEM8(0x08C1) -#define SPIC_STATUS _SFR_MEM8(0x08C2) -#define SPIC_DATA _SFR_MEM8(0x08C3) - -/* IRCOM - IR Communication Module */ -#define IRCOM_CTRL _SFR_MEM8(0x08F8) -#define IRCOM_TXPLCTRL _SFR_MEM8(0x08F9) -#define IRCOM_RXPLCTRL _SFR_MEM8(0x08FA) - -/* TC0 - 16-bit Timer/Counter 0 */ -#define TCD0_CTRLA _SFR_MEM8(0x0900) -#define TCD0_CTRLB _SFR_MEM8(0x0901) -#define TCD0_CTRLC _SFR_MEM8(0x0902) -#define TCD0_CTRLD _SFR_MEM8(0x0903) -#define TCD0_CTRLE _SFR_MEM8(0x0904) -#define TCD0_INTCTRLA _SFR_MEM8(0x0906) -#define TCD0_INTCTRLB _SFR_MEM8(0x0907) -#define TCD0_CTRLFCLR _SFR_MEM8(0x0908) -#define TCD0_CTRLFSET _SFR_MEM8(0x0909) -#define TCD0_CTRLGCLR _SFR_MEM8(0x090A) -#define TCD0_CTRLGSET _SFR_MEM8(0x090B) -#define TCD0_INTFLAGS _SFR_MEM8(0x090C) -#define TCD0_TEMP _SFR_MEM8(0x090F) -#define TCD0_CNT _SFR_MEM16(0x0920) -#define TCD0_PER _SFR_MEM16(0x0926) -#define TCD0_CCA _SFR_MEM16(0x0928) -#define TCD0_CCB _SFR_MEM16(0x092A) -#define TCD0_CCC _SFR_MEM16(0x092C) -#define TCD0_CCD _SFR_MEM16(0x092E) -#define TCD0_PERBUF _SFR_MEM16(0x0936) -#define TCD0_CCABUF _SFR_MEM16(0x0938) -#define TCD0_CCBBUF _SFR_MEM16(0x093A) -#define TCD0_CCCBUF _SFR_MEM16(0x093C) -#define TCD0_CCDBUF _SFR_MEM16(0x093E) - -/* TC2 - 16-bit Timer/Counter type 2 */ -#define TCD2_CTRLA _SFR_MEM8(0x0900) -#define TCD2_CTRLB _SFR_MEM8(0x0901) -#define TCD2_CTRLC _SFR_MEM8(0x0902) -#define TCD2_CTRLE _SFR_MEM8(0x0904) -#define TCD2_INTCTRLA _SFR_MEM8(0x0906) -#define TCD2_INTCTRLB _SFR_MEM8(0x0907) -#define TCD2_CTRLF _SFR_MEM8(0x0909) -#define TCD2_INTFLAGS _SFR_MEM8(0x090C) -#define TCD2_LCNT _SFR_MEM8(0x0920) -#define TCD2_HCNT _SFR_MEM8(0x0921) -#define TCD2_LPER _SFR_MEM8(0x0926) -#define TCD2_HPER _SFR_MEM8(0x0927) -#define TCD2_LCMPA _SFR_MEM8(0x0928) -#define TCD2_HCMPA _SFR_MEM8(0x0929) -#define TCD2_LCMPB _SFR_MEM8(0x092A) -#define TCD2_HCMPB _SFR_MEM8(0x092B) -#define TCD2_LCMPC _SFR_MEM8(0x092C) -#define TCD2_HCMPC _SFR_MEM8(0x092D) -#define TCD2_LCMPD _SFR_MEM8(0x092E) -#define TCD2_HCMPD _SFR_MEM8(0x092F) - -/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ -#define USARTD0_DATA _SFR_MEM8(0x09A0) -#define USARTD0_STATUS _SFR_MEM8(0x09A1) -#define USARTD0_CTRLA _SFR_MEM8(0x09A3) -#define USARTD0_CTRLB _SFR_MEM8(0x09A4) -#define USARTD0_CTRLC _SFR_MEM8(0x09A5) -#define USARTD0_BAUDCTRLA _SFR_MEM8(0x09A6) -#define USARTD0_BAUDCTRLB _SFR_MEM8(0x09A7) - -/* SPI - Serial Peripheral Interface */ -#define SPID_CTRL _SFR_MEM8(0x09C0) -#define SPID_INTCTRL _SFR_MEM8(0x09C1) -#define SPID_STATUS _SFR_MEM8(0x09C2) -#define SPID_DATA _SFR_MEM8(0x09C3) - -/* TC0 - 16-bit Timer/Counter 0 */ -#define TCE0_CTRLA _SFR_MEM8(0x0A00) -#define TCE0_CTRLB _SFR_MEM8(0x0A01) -#define TCE0_CTRLC _SFR_MEM8(0x0A02) -#define TCE0_CTRLD _SFR_MEM8(0x0A03) -#define TCE0_CTRLE _SFR_MEM8(0x0A04) -#define TCE0_INTCTRLA _SFR_MEM8(0x0A06) -#define TCE0_INTCTRLB _SFR_MEM8(0x0A07) -#define TCE0_CTRLFCLR _SFR_MEM8(0x0A08) -#define TCE0_CTRLFSET _SFR_MEM8(0x0A09) -#define TCE0_CTRLGCLR _SFR_MEM8(0x0A0A) -#define TCE0_CTRLGSET _SFR_MEM8(0x0A0B) -#define TCE0_INTFLAGS _SFR_MEM8(0x0A0C) -#define TCE0_TEMP _SFR_MEM8(0x0A0F) -#define TCE0_CNT _SFR_MEM16(0x0A20) -#define TCE0_PER _SFR_MEM16(0x0A26) -#define TCE0_CCA _SFR_MEM16(0x0A28) -#define TCE0_CCB _SFR_MEM16(0x0A2A) -#define TCE0_CCC _SFR_MEM16(0x0A2C) -#define TCE0_CCD _SFR_MEM16(0x0A2E) -#define TCE0_PERBUF _SFR_MEM16(0x0A36) -#define TCE0_CCABUF _SFR_MEM16(0x0A38) -#define TCE0_CCBBUF _SFR_MEM16(0x0A3A) -#define TCE0_CCCBUF _SFR_MEM16(0x0A3C) -#define TCE0_CCDBUF _SFR_MEM16(0x0A3E) - - - -/*================== Bitfield Definitions ================== */ - -/* VPORT - Virtual Ports */ -/* VPORT.INTFLAGS bit masks and bit positions */ -#define VPORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ -#define VPORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ - -#define VPORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ -#define VPORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ - -/* XOCD - On-Chip Debug System */ -/* OCD.OCDR0 bit masks and bit positions */ -#define OCD_OCDRD_gm 0xFF /* OCDR Dirty group mask. */ -#define OCD_OCDRD_gp 0 /* OCDR Dirty group position. */ -#define OCD_OCDRD0_bm (1<<0) /* OCDR Dirty bit 0 mask. */ -#define OCD_OCDRD0_bp 0 /* OCDR Dirty bit 0 position. */ -#define OCD_OCDRD1_bm (1<<1) /* OCDR Dirty bit 1 mask. */ -#define OCD_OCDRD1_bp 1 /* OCDR Dirty bit 1 position. */ -#define OCD_OCDRD2_bm (1<<2) /* OCDR Dirty bit 2 mask. */ -#define OCD_OCDRD2_bp 2 /* OCDR Dirty bit 2 position. */ -#define OCD_OCDRD3_bm (1<<3) /* OCDR Dirty bit 3 mask. */ -#define OCD_OCDRD3_bp 3 /* OCDR Dirty bit 3 position. */ -#define OCD_OCDRD4_bm (1<<4) /* OCDR Dirty bit 4 mask. */ -#define OCD_OCDRD4_bp 4 /* OCDR Dirty bit 4 position. */ -#define OCD_OCDRD5_bm (1<<5) /* OCDR Dirty bit 5 mask. */ -#define OCD_OCDRD5_bp 5 /* OCDR Dirty bit 5 position. */ -#define OCD_OCDRD6_bm (1<<6) /* OCDR Dirty bit 6 mask. */ -#define OCD_OCDRD6_bp 6 /* OCDR Dirty bit 6 position. */ -#define OCD_OCDRD7_bm (1<<7) /* OCDR Dirty bit 7 mask. */ -#define OCD_OCDRD7_bp 7 /* OCDR Dirty bit 7 position. */ - -/* OCD.OCDR1 bit masks and bit positions */ -/* OCD_OCDRD Predefined. */ -/* OCD_OCDRD Predefined. */ - -/* CPU - CPU */ -/* CPU.CCP bit masks and bit positions */ -#define CPU_CCP_gm 0xFF /* CCP signature group mask. */ -#define CPU_CCP_gp 0 /* CCP signature group position. */ -#define CPU_CCP0_bm (1<<0) /* CCP signature bit 0 mask. */ -#define CPU_CCP0_bp 0 /* CCP signature bit 0 position. */ -#define CPU_CCP1_bm (1<<1) /* CCP signature bit 1 mask. */ -#define CPU_CCP1_bp 1 /* CCP signature bit 1 position. */ -#define CPU_CCP2_bm (1<<2) /* CCP signature bit 2 mask. */ -#define CPU_CCP2_bp 2 /* CCP signature bit 2 position. */ -#define CPU_CCP3_bm (1<<3) /* CCP signature bit 3 mask. */ -#define CPU_CCP3_bp 3 /* CCP signature bit 3 position. */ -#define CPU_CCP4_bm (1<<4) /* CCP signature bit 4 mask. */ -#define CPU_CCP4_bp 4 /* CCP signature bit 4 position. */ -#define CPU_CCP5_bm (1<<5) /* CCP signature bit 5 mask. */ -#define CPU_CCP5_bp 5 /* CCP signature bit 5 position. */ -#define CPU_CCP6_bm (1<<6) /* CCP signature bit 6 mask. */ -#define CPU_CCP6_bp 6 /* CCP signature bit 6 position. */ -#define CPU_CCP7_bm (1<<7) /* CCP signature bit 7 mask. */ -#define CPU_CCP7_bp 7 /* CCP signature bit 7 position. */ - -/* CPU.SREG bit masks and bit positions */ -#define CPU_I_bm 0x80 /* Global Interrupt Enable Flag bit mask. */ -#define CPU_I_bp 7 /* Global Interrupt Enable Flag bit position. */ - -#define CPU_T_bm 0x40 /* Transfer Bit bit mask. */ -#define CPU_T_bp 6 /* Transfer Bit bit position. */ - -#define CPU_H_bm 0x20 /* Half Carry Flag bit mask. */ -#define CPU_H_bp 5 /* Half Carry Flag bit position. */ - -#define CPU_S_bm 0x10 /* N Exclusive Or V Flag bit mask. */ -#define CPU_S_bp 4 /* N Exclusive Or V Flag bit position. */ - -#define CPU_V_bm 0x08 /* Two's Complement Overflow Flag bit mask. */ -#define CPU_V_bp 3 /* Two's Complement Overflow Flag bit position. */ - -#define CPU_N_bm 0x04 /* Negative Flag bit mask. */ -#define CPU_N_bp 2 /* Negative Flag bit position. */ - -#define CPU_Z_bm 0x02 /* Zero Flag bit mask. */ -#define CPU_Z_bp 1 /* Zero Flag bit position. */ - -#define CPU_C_bm 0x01 /* Carry Flag bit mask. */ -#define CPU_C_bp 0 /* Carry Flag bit position. */ - -/* CLK - Clock System */ -/* CLK.CTRL bit masks and bit positions */ -#define CLK_SCLKSEL_gm 0x07 /* System Clock Selection group mask. */ -#define CLK_SCLKSEL_gp 0 /* System Clock Selection group position. */ -#define CLK_SCLKSEL0_bm (1<<0) /* System Clock Selection bit 0 mask. */ -#define CLK_SCLKSEL0_bp 0 /* System Clock Selection bit 0 position. */ -#define CLK_SCLKSEL1_bm (1<<1) /* System Clock Selection bit 1 mask. */ -#define CLK_SCLKSEL1_bp 1 /* System Clock Selection bit 1 position. */ -#define CLK_SCLKSEL2_bm (1<<2) /* System Clock Selection bit 2 mask. */ -#define CLK_SCLKSEL2_bp 2 /* System Clock Selection bit 2 position. */ - -/* CLK.PSCTRL bit masks and bit positions */ -#define CLK_PSADIV_gm 0x7C /* Prescaler A Division Factor group mask. */ -#define CLK_PSADIV_gp 2 /* Prescaler A Division Factor group position. */ -#define CLK_PSADIV0_bm (1<<2) /* Prescaler A Division Factor bit 0 mask. */ -#define CLK_PSADIV0_bp 2 /* Prescaler A Division Factor bit 0 position. */ -#define CLK_PSADIV1_bm (1<<3) /* Prescaler A Division Factor bit 1 mask. */ -#define CLK_PSADIV1_bp 3 /* Prescaler A Division Factor bit 1 position. */ -#define CLK_PSADIV2_bm (1<<4) /* Prescaler A Division Factor bit 2 mask. */ -#define CLK_PSADIV2_bp 4 /* Prescaler A Division Factor bit 2 position. */ -#define CLK_PSADIV3_bm (1<<5) /* Prescaler A Division Factor bit 3 mask. */ -#define CLK_PSADIV3_bp 5 /* Prescaler A Division Factor bit 3 position. */ -#define CLK_PSADIV4_bm (1<<6) /* Prescaler A Division Factor bit 4 mask. */ -#define CLK_PSADIV4_bp 6 /* Prescaler A Division Factor bit 4 position. */ - -#define CLK_PSBCDIV_gm 0x03 /* Prescaler B and C Division factor group mask. */ -#define CLK_PSBCDIV_gp 0 /* Prescaler B and C Division factor group position. */ -#define CLK_PSBCDIV0_bm (1<<0) /* Prescaler B and C Division factor bit 0 mask. */ -#define CLK_PSBCDIV0_bp 0 /* Prescaler B and C Division factor bit 0 position. */ -#define CLK_PSBCDIV1_bm (1<<1) /* Prescaler B and C Division factor bit 1 mask. */ -#define CLK_PSBCDIV1_bp 1 /* Prescaler B and C Division factor bit 1 position. */ - -/* CLK.LOCK bit masks and bit positions */ -#define CLK_LOCK_bm 0x01 /* Clock System Lock bit mask. */ -#define CLK_LOCK_bp 0 /* Clock System Lock bit position. */ - -/* CLK.RTCCTRL bit masks and bit positions */ -#define CLK_RTCSRC_gm 0x0E /* Clock Source group mask. */ -#define CLK_RTCSRC_gp 1 /* Clock Source group position. */ -#define CLK_RTCSRC0_bm (1<<1) /* Clock Source bit 0 mask. */ -#define CLK_RTCSRC0_bp 1 /* Clock Source bit 0 position. */ -#define CLK_RTCSRC1_bm (1<<2) /* Clock Source bit 1 mask. */ -#define CLK_RTCSRC1_bp 2 /* Clock Source bit 1 position. */ -#define CLK_RTCSRC2_bm (1<<3) /* Clock Source bit 2 mask. */ -#define CLK_RTCSRC2_bp 3 /* Clock Source bit 2 position. */ - -#define CLK_RTCEN_bm 0x01 /* Clock Source Enable bit mask. */ -#define CLK_RTCEN_bp 0 /* Clock Source Enable bit position. */ - -/* PR.PRGEN bit masks and bit positions */ -#define PR_RTC_bm 0x04 /* Real-time Counter bit mask. */ -#define PR_RTC_bp 2 /* Real-time Counter bit position. */ - -#define PR_EVSYS_bm 0x02 /* Event System bit mask. */ -#define PR_EVSYS_bp 1 /* Event System bit position. */ - -/* PR.PRPA bit masks and bit positions */ -#define PR_ADC_bm 0x02 /* Port A ADC bit mask. */ -#define PR_ADC_bp 1 /* Port A ADC bit position. */ - -#define PR_AC_bm 0x01 /* Port A Analog Comparator bit mask. */ -#define PR_AC_bp 0 /* Port A Analog Comparator bit position. */ - -/* PR.PRPC bit masks and bit positions */ -#define PR_TWI_bm 0x40 /* Port C Two-wire Interface bit mask. */ -#define PR_TWI_bp 6 /* Port C Two-wire Interface bit position. */ - -#define PR_USART0_bm 0x10 /* Port C USART0 bit mask. */ -#define PR_USART0_bp 4 /* Port C USART0 bit position. */ - -#define PR_SPI_bm 0x08 /* Port C SPI bit mask. */ -#define PR_SPI_bp 3 /* Port C SPI bit position. */ - -#define PR_HIRES_bm 0x04 /* Port C HIRES bit mask. */ -#define PR_HIRES_bp 2 /* Port C HIRES bit position. */ - -#define PR_TC1_bm 0x02 /* Port C Timer/Counter1 bit mask. */ -#define PR_TC1_bp 1 /* Port C Timer/Counter1 bit position. */ - -#define PR_TC0_bm 0x01 /* Port C Timer/Counter0 bit mask. */ -#define PR_TC0_bp 0 /* Port C Timer/Counter0 bit position. */ - -/* PR.PRPD bit masks and bit positions */ -/* PR_USART0 Predefined. */ -/* PR_USART0 Predefined. */ - -/* PR_SPI Predefined. */ -/* PR_SPI Predefined. */ - -/* PR_TC0 Predefined. */ -/* PR_TC0 Predefined. */ - -/* PR.PRPE bit masks and bit positions */ -/* PR_TWI Predefined. */ -/* PR_TWI Predefined. */ - -/* PR_USART0 Predefined. */ -/* PR_USART0 Predefined. */ - -/* PR_TC0 Predefined. */ -/* PR_TC0 Predefined. */ - -/* PR.PRPF bit masks and bit positions */ -/* PR_USART0 Predefined. */ -/* PR_USART0 Predefined. */ - -/* PR_TC0 Predefined. */ -/* PR_TC0 Predefined. */ - -/* SLEEP - Sleep Controller */ -/* SLEEP.CTRL bit masks and bit positions */ -#define SLEEP_SMODE_gm 0x0E /* Sleep Mode group mask. */ -#define SLEEP_SMODE_gp 1 /* Sleep Mode group position. */ -#define SLEEP_SMODE0_bm (1<<1) /* Sleep Mode bit 0 mask. */ -#define SLEEP_SMODE0_bp 1 /* Sleep Mode bit 0 position. */ -#define SLEEP_SMODE1_bm (1<<2) /* Sleep Mode bit 1 mask. */ -#define SLEEP_SMODE1_bp 2 /* Sleep Mode bit 1 position. */ -#define SLEEP_SMODE2_bm (1<<3) /* Sleep Mode bit 2 mask. */ -#define SLEEP_SMODE2_bp 3 /* Sleep Mode bit 2 position. */ - -#define SLEEP_SEN_bm 0x01 /* Sleep Enable bit mask. */ -#define SLEEP_SEN_bp 0 /* Sleep Enable bit position. */ - -/* OSC - Oscillator */ -/* OSC.CTRL bit masks and bit positions */ -#define OSC_PLLEN_bm 0x10 /* PLL Enable bit mask. */ -#define OSC_PLLEN_bp 4 /* PLL Enable bit position. */ - -#define OSC_XOSCEN_bm 0x08 /* External Oscillator Enable bit mask. */ -#define OSC_XOSCEN_bp 3 /* External Oscillator Enable bit position. */ - -#define OSC_RC32KEN_bm 0x04 /* Internal 32.768 kHz RC Oscillator Enable bit mask. */ -#define OSC_RC32KEN_bp 2 /* Internal 32.768 kHz RC Oscillator Enable bit position. */ - -#define OSC_RC32MEN_bm 0x02 /* Internal 32 MHz RC Oscillator Enable bit mask. */ -#define OSC_RC32MEN_bp 1 /* Internal 32 MHz RC Oscillator Enable bit position. */ - -#define OSC_RC2MEN_bm 0x01 /* Internal 2 MHz RC Oscillator Enable bit mask. */ -#define OSC_RC2MEN_bp 0 /* Internal 2 MHz RC Oscillator Enable bit position. */ - -/* OSC.STATUS bit masks and bit positions */ -#define OSC_PLLRDY_bm 0x10 /* PLL Ready bit mask. */ -#define OSC_PLLRDY_bp 4 /* PLL Ready bit position. */ - -#define OSC_XOSCRDY_bm 0x08 /* External Oscillator Ready bit mask. */ -#define OSC_XOSCRDY_bp 3 /* External Oscillator Ready bit position. */ - -#define OSC_RC32KRDY_bm 0x04 /* Internal 32.768 kHz RC Oscillator Ready bit mask. */ -#define OSC_RC32KRDY_bp 2 /* Internal 32.768 kHz RC Oscillator Ready bit position. */ - -#define OSC_RC32MRDY_bm 0x02 /* Internal 32 MHz RC Oscillator Ready bit mask. */ -#define OSC_RC32MRDY_bp 1 /* Internal 32 MHz RC Oscillator Ready bit position. */ - -#define OSC_RC2MRDY_bm 0x01 /* Internal 2 MHz RC Oscillator Ready bit mask. */ -#define OSC_RC2MRDY_bp 0 /* Internal 2 MHz RC Oscillator Ready bit position. */ - -/* OSC.XOSCCTRL bit masks and bit positions */ -#define OSC_FRQRANGE_gm 0xC0 /* Frequency Range group mask. */ -#define OSC_FRQRANGE_gp 6 /* Frequency Range group position. */ -#define OSC_FRQRANGE0_bm (1<<6) /* Frequency Range bit 0 mask. */ -#define OSC_FRQRANGE0_bp 6 /* Frequency Range bit 0 position. */ -#define OSC_FRQRANGE1_bm (1<<7) /* Frequency Range bit 1 mask. */ -#define OSC_FRQRANGE1_bp 7 /* Frequency Range bit 1 position. */ - -#define OSC_X32KLPM_bm 0x20 /* 32.768 kHz XTAL OSC Low-power Mode bit mask. */ -#define OSC_X32KLPM_bp 5 /* 32.768 kHz XTAL OSC Low-power Mode bit position. */ - -#define OSC_XOSCPWR_bm 0x10 /* 16 MHz Crystal Oscillator High Power mode bit mask. */ -#define OSC_XOSCPWR_bp 4 /* 16 MHz Crystal Oscillator High Power mode bit position. */ - -#define OSC_XOSCSEL_gm 0x0F /* External Oscillator Selection and Startup Time group mask. */ -#define OSC_XOSCSEL_gp 0 /* External Oscillator Selection and Startup Time group position. */ -#define OSC_XOSCSEL0_bm (1<<0) /* External Oscillator Selection and Startup Time bit 0 mask. */ -#define OSC_XOSCSEL0_bp 0 /* External Oscillator Selection and Startup Time bit 0 position. */ -#define OSC_XOSCSEL1_bm (1<<1) /* External Oscillator Selection and Startup Time bit 1 mask. */ -#define OSC_XOSCSEL1_bp 1 /* External Oscillator Selection and Startup Time bit 1 position. */ -#define OSC_XOSCSEL2_bm (1<<2) /* External Oscillator Selection and Startup Time bit 2 mask. */ -#define OSC_XOSCSEL2_bp 2 /* External Oscillator Selection and Startup Time bit 2 position. */ -#define OSC_XOSCSEL3_bm (1<<3) /* External Oscillator Selection and Startup Time bit 3 mask. */ -#define OSC_XOSCSEL3_bp 3 /* External Oscillator Selection and Startup Time bit 3 position. */ - -/* OSC.XOSCFAIL bit masks and bit positions */ -#define OSC_PLLFDIF_bm 0x08 /* PLL Failure Detection Interrupt Flag bit mask. */ -#define OSC_PLLFDIF_bp 3 /* PLL Failure Detection Interrupt Flag bit position. */ - -#define OSC_PLLFDEN_bm 0x04 /* PLL Failure Detection Enable bit mask. */ -#define OSC_PLLFDEN_bp 2 /* PLL Failure Detection Enable bit position. */ - -#define OSC_XOSCFDIF_bm 0x02 /* XOSC Failure Detection Interrupt Flag bit mask. */ -#define OSC_XOSCFDIF_bp 1 /* XOSC Failure Detection Interrupt Flag bit position. */ - -#define OSC_XOSCFDEN_bm 0x01 /* XOSC Failure Detection Enable bit mask. */ -#define OSC_XOSCFDEN_bp 0 /* XOSC Failure Detection Enable bit position. */ - -/* OSC.PLLCTRL bit masks and bit positions */ -#define OSC_PLLSRC_gm 0xC0 /* Clock Source group mask. */ -#define OSC_PLLSRC_gp 6 /* Clock Source group position. */ -#define OSC_PLLSRC0_bm (1<<6) /* Clock Source bit 0 mask. */ -#define OSC_PLLSRC0_bp 6 /* Clock Source bit 0 position. */ -#define OSC_PLLSRC1_bm (1<<7) /* Clock Source bit 1 mask. */ -#define OSC_PLLSRC1_bp 7 /* Clock Source bit 1 position. */ - -#define OSC_PLLDIV_bm 0x20 /* Divide by 2 bit mask. */ -#define OSC_PLLDIV_bp 5 /* Divide by 2 bit position. */ - -#define OSC_PLLFAC_gm 0x1F /* Multiplication Factor group mask. */ -#define OSC_PLLFAC_gp 0 /* Multiplication Factor group position. */ -#define OSC_PLLFAC0_bm (1<<0) /* Multiplication Factor bit 0 mask. */ -#define OSC_PLLFAC0_bp 0 /* Multiplication Factor bit 0 position. */ -#define OSC_PLLFAC1_bm (1<<1) /* Multiplication Factor bit 1 mask. */ -#define OSC_PLLFAC1_bp 1 /* Multiplication Factor bit 1 position. */ -#define OSC_PLLFAC2_bm (1<<2) /* Multiplication Factor bit 2 mask. */ -#define OSC_PLLFAC2_bp 2 /* Multiplication Factor bit 2 position. */ -#define OSC_PLLFAC3_bm (1<<3) /* Multiplication Factor bit 3 mask. */ -#define OSC_PLLFAC3_bp 3 /* Multiplication Factor bit 3 position. */ -#define OSC_PLLFAC4_bm (1<<4) /* Multiplication Factor bit 4 mask. */ -#define OSC_PLLFAC4_bp 4 /* Multiplication Factor bit 4 position. */ - -/* OSC.DFLLCTRL bit masks and bit positions */ -#define OSC_RC32MCREF_gm 0x06 /* 32 MHz DFLL Calibration Reference group mask. */ -#define OSC_RC32MCREF_gp 1 /* 32 MHz DFLL Calibration Reference group position. */ -#define OSC_RC32MCREF0_bm (1<<1) /* 32 MHz DFLL Calibration Reference bit 0 mask. */ -#define OSC_RC32MCREF0_bp 1 /* 32 MHz DFLL Calibration Reference bit 0 position. */ -#define OSC_RC32MCREF1_bm (1<<2) /* 32 MHz DFLL Calibration Reference bit 1 mask. */ -#define OSC_RC32MCREF1_bp 2 /* 32 MHz DFLL Calibration Reference bit 1 position. */ - -#define OSC_RC2MCREF_bm 0x01 /* 2 MHz DFLL Calibration Reference bit mask. */ -#define OSC_RC2MCREF_bp 0 /* 2 MHz DFLL Calibration Reference bit position. */ - -/* DFLL - DFLL */ -/* DFLL.CTRL bit masks and bit positions */ -#define DFLL_ENABLE_bm 0x01 /* DFLL Enable bit mask. */ -#define DFLL_ENABLE_bp 0 /* DFLL Enable bit position. */ - -/* DFLL.CALA bit masks and bit positions */ -#define DFLL_CALL_gm 0x7F /* DFLL Calibration Value A group mask. */ -#define DFLL_CALL_gp 0 /* DFLL Calibration Value A group position. */ -#define DFLL_CALL0_bm (1<<0) /* DFLL Calibration Value A bit 0 mask. */ -#define DFLL_CALL0_bp 0 /* DFLL Calibration Value A bit 0 position. */ -#define DFLL_CALL1_bm (1<<1) /* DFLL Calibration Value A bit 1 mask. */ -#define DFLL_CALL1_bp 1 /* DFLL Calibration Value A bit 1 position. */ -#define DFLL_CALL2_bm (1<<2) /* DFLL Calibration Value A bit 2 mask. */ -#define DFLL_CALL2_bp 2 /* DFLL Calibration Value A bit 2 position. */ -#define DFLL_CALL3_bm (1<<3) /* DFLL Calibration Value A bit 3 mask. */ -#define DFLL_CALL3_bp 3 /* DFLL Calibration Value A bit 3 position. */ -#define DFLL_CALL4_bm (1<<4) /* DFLL Calibration Value A bit 4 mask. */ -#define DFLL_CALL4_bp 4 /* DFLL Calibration Value A bit 4 position. */ -#define DFLL_CALL5_bm (1<<5) /* DFLL Calibration Value A bit 5 mask. */ -#define DFLL_CALL5_bp 5 /* DFLL Calibration Value A bit 5 position. */ -#define DFLL_CALL6_bm (1<<6) /* DFLL Calibration Value A bit 6 mask. */ -#define DFLL_CALL6_bp 6 /* DFLL Calibration Value A bit 6 position. */ - -/* DFLL.CALB bit masks and bit positions */ -#define DFLL_CALH_gm 0x3F /* DFLL Calibration Value B group mask. */ -#define DFLL_CALH_gp 0 /* DFLL Calibration Value B group position. */ -#define DFLL_CALH0_bm (1<<0) /* DFLL Calibration Value B bit 0 mask. */ -#define DFLL_CALH0_bp 0 /* DFLL Calibration Value B bit 0 position. */ -#define DFLL_CALH1_bm (1<<1) /* DFLL Calibration Value B bit 1 mask. */ -#define DFLL_CALH1_bp 1 /* DFLL Calibration Value B bit 1 position. */ -#define DFLL_CALH2_bm (1<<2) /* DFLL Calibration Value B bit 2 mask. */ -#define DFLL_CALH2_bp 2 /* DFLL Calibration Value B bit 2 position. */ -#define DFLL_CALH3_bm (1<<3) /* DFLL Calibration Value B bit 3 mask. */ -#define DFLL_CALH3_bp 3 /* DFLL Calibration Value B bit 3 position. */ -#define DFLL_CALH4_bm (1<<4) /* DFLL Calibration Value B bit 4 mask. */ -#define DFLL_CALH4_bp 4 /* DFLL Calibration Value B bit 4 position. */ -#define DFLL_CALH5_bm (1<<5) /* DFLL Calibration Value B bit 5 mask. */ -#define DFLL_CALH5_bp 5 /* DFLL Calibration Value B bit 5 position. */ - -/* RST - Reset */ -/* RST.STATUS bit masks and bit positions */ -#define RST_SDRF_bm 0x40 /* Spike Detection Reset Flag bit mask. */ -#define RST_SDRF_bp 6 /* Spike Detection Reset Flag bit position. */ - -#define RST_SRF_bm 0x20 /* Software Reset Flag bit mask. */ -#define RST_SRF_bp 5 /* Software Reset Flag bit position. */ - -#define RST_PDIRF_bm 0x10 /* Programming and Debug Interface Interface Reset Flag bit mask. */ -#define RST_PDIRF_bp 4 /* Programming and Debug Interface Interface Reset Flag bit position. */ - -#define RST_WDRF_bm 0x08 /* Watchdog Reset Flag bit mask. */ -#define RST_WDRF_bp 3 /* Watchdog Reset Flag bit position. */ - -#define RST_BORF_bm 0x04 /* Brown-out Reset Flag bit mask. */ -#define RST_BORF_bp 2 /* Brown-out Reset Flag bit position. */ - -#define RST_EXTRF_bm 0x02 /* External Reset Flag bit mask. */ -#define RST_EXTRF_bp 1 /* External Reset Flag bit position. */ - -#define RST_PORF_bm 0x01 /* Power-on Reset Flag bit mask. */ -#define RST_PORF_bp 0 /* Power-on Reset Flag bit position. */ - -/* RST.CTRL bit masks and bit positions */ -#define RST_SWRST_bm 0x01 /* Software Reset bit mask. */ -#define RST_SWRST_bp 0 /* Software Reset bit position. */ - -/* WDT - Watch-Dog Timer */ -/* WDT.CTRL bit masks and bit positions */ -#define WDT_PER_gm 0x3C /* Period group mask. */ -#define WDT_PER_gp 2 /* Period group position. */ -#define WDT_PER0_bm (1<<2) /* Period bit 0 mask. */ -#define WDT_PER0_bp 2 /* Period bit 0 position. */ -#define WDT_PER1_bm (1<<3) /* Period bit 1 mask. */ -#define WDT_PER1_bp 3 /* Period bit 1 position. */ -#define WDT_PER2_bm (1<<4) /* Period bit 2 mask. */ -#define WDT_PER2_bp 4 /* Period bit 2 position. */ -#define WDT_PER3_bm (1<<5) /* Period bit 3 mask. */ -#define WDT_PER3_bp 5 /* Period bit 3 position. */ - -#define WDT_ENABLE_bm 0x02 /* Enable bit mask. */ -#define WDT_ENABLE_bp 1 /* Enable bit position. */ - -#define WDT_CEN_bm 0x01 /* Change Enable bit mask. */ -#define WDT_CEN_bp 0 /* Change Enable bit position. */ - -/* WDT.WINCTRL bit masks and bit positions */ -#define WDT_WPER_gm 0x3C /* Windowed Mode Period group mask. */ -#define WDT_WPER_gp 2 /* Windowed Mode Period group position. */ -#define WDT_WPER0_bm (1<<2) /* Windowed Mode Period bit 0 mask. */ -#define WDT_WPER0_bp 2 /* Windowed Mode Period bit 0 position. */ -#define WDT_WPER1_bm (1<<3) /* Windowed Mode Period bit 1 mask. */ -#define WDT_WPER1_bp 3 /* Windowed Mode Period bit 1 position. */ -#define WDT_WPER2_bm (1<<4) /* Windowed Mode Period bit 2 mask. */ -#define WDT_WPER2_bp 4 /* Windowed Mode Period bit 2 position. */ -#define WDT_WPER3_bm (1<<5) /* Windowed Mode Period bit 3 mask. */ -#define WDT_WPER3_bp 5 /* Windowed Mode Period bit 3 position. */ - -#define WDT_WEN_bm 0x02 /* Windowed Mode Enable bit mask. */ -#define WDT_WEN_bp 1 /* Windowed Mode Enable bit position. */ - -#define WDT_WCEN_bm 0x01 /* Windowed Mode Change Enable bit mask. */ -#define WDT_WCEN_bp 0 /* Windowed Mode Change Enable bit position. */ - -/* WDT.STATUS bit masks and bit positions */ -#define WDT_SYNCBUSY_bm 0x01 /* Syncronization busy bit mask. */ -#define WDT_SYNCBUSY_bp 0 /* Syncronization busy bit position. */ - -/* MCU - MCU Control */ -/* MCU.ANAINIT bit masks and bit positions */ -#define MCU_STARTUPDLYA_gm 0x03 /* Analog startup delay Port A group mask. */ -#define MCU_STARTUPDLYA_gp 0 /* Analog startup delay Port A group position. */ -#define MCU_STARTUPDLYA0_bm (1<<0) /* Analog startup delay Port A bit 0 mask. */ -#define MCU_STARTUPDLYA0_bp 0 /* Analog startup delay Port A bit 0 position. */ -#define MCU_STARTUPDLYA1_bm (1<<1) /* Analog startup delay Port A bit 1 mask. */ -#define MCU_STARTUPDLYA1_bp 1 /* Analog startup delay Port A bit 1 position. */ - -/* MCU.EVSYSLOCK bit masks and bit positions */ -#define MCU_EVSYS0LOCK_bm 0x01 /* Event Channel 0-3 Lock bit mask. */ -#define MCU_EVSYS0LOCK_bp 0 /* Event Channel 0-3 Lock bit position. */ - -/* MCU.AWEXLOCK bit masks and bit positions */ -#define MCU_AWEXCLOCK_bm 0x01 /* AWeX on T/C C0 Lock bit mask. */ -#define MCU_AWEXCLOCK_bp 0 /* AWeX on T/C C0 Lock bit position. */ - -/* PMIC - Programmable Multi-level Interrupt Controller */ -/* PMIC.STATUS bit masks and bit positions */ -#define PMIC_NMIEX_bm 0x80 /* Non-maskable Interrupt Executing bit mask. */ -#define PMIC_NMIEX_bp 7 /* Non-maskable Interrupt Executing bit position. */ - -#define PMIC_HILVLEX_bm 0x04 /* High Level Interrupt Executing bit mask. */ -#define PMIC_HILVLEX_bp 2 /* High Level Interrupt Executing bit position. */ - -#define PMIC_MEDLVLEX_bm 0x02 /* Medium Level Interrupt Executing bit mask. */ -#define PMIC_MEDLVLEX_bp 1 /* Medium Level Interrupt Executing bit position. */ - -#define PMIC_LOLVLEX_bm 0x01 /* Low Level Interrupt Executing bit mask. */ -#define PMIC_LOLVLEX_bp 0 /* Low Level Interrupt Executing bit position. */ - -/* PMIC.INTPRI bit masks and bit positions */ -#define PMIC_INTPRI_gm 0xFF /* Interrupt Priority group mask. */ -#define PMIC_INTPRI_gp 0 /* Interrupt Priority group position. */ -#define PMIC_INTPRI0_bm (1<<0) /* Interrupt Priority bit 0 mask. */ -#define PMIC_INTPRI0_bp 0 /* Interrupt Priority bit 0 position. */ -#define PMIC_INTPRI1_bm (1<<1) /* Interrupt Priority bit 1 mask. */ -#define PMIC_INTPRI1_bp 1 /* Interrupt Priority bit 1 position. */ -#define PMIC_INTPRI2_bm (1<<2) /* Interrupt Priority bit 2 mask. */ -#define PMIC_INTPRI2_bp 2 /* Interrupt Priority bit 2 position. */ -#define PMIC_INTPRI3_bm (1<<3) /* Interrupt Priority bit 3 mask. */ -#define PMIC_INTPRI3_bp 3 /* Interrupt Priority bit 3 position. */ -#define PMIC_INTPRI4_bm (1<<4) /* Interrupt Priority bit 4 mask. */ -#define PMIC_INTPRI4_bp 4 /* Interrupt Priority bit 4 position. */ -#define PMIC_INTPRI5_bm (1<<5) /* Interrupt Priority bit 5 mask. */ -#define PMIC_INTPRI5_bp 5 /* Interrupt Priority bit 5 position. */ -#define PMIC_INTPRI6_bm (1<<6) /* Interrupt Priority bit 6 mask. */ -#define PMIC_INTPRI6_bp 6 /* Interrupt Priority bit 6 position. */ -#define PMIC_INTPRI7_bm (1<<7) /* Interrupt Priority bit 7 mask. */ -#define PMIC_INTPRI7_bp 7 /* Interrupt Priority bit 7 position. */ - -/* PMIC.CTRL bit masks and bit positions */ -#define PMIC_RREN_bm 0x80 /* Round-Robin Priority Enable bit mask. */ -#define PMIC_RREN_bp 7 /* Round-Robin Priority Enable bit position. */ - -#define PMIC_IVSEL_bm 0x40 /* Interrupt Vector Select bit mask. */ -#define PMIC_IVSEL_bp 6 /* Interrupt Vector Select bit position. */ - -#define PMIC_HILVLEN_bm 0x04 /* High Level Enable bit mask. */ -#define PMIC_HILVLEN_bp 2 /* High Level Enable bit position. */ - -#define PMIC_MEDLVLEN_bm 0x02 /* Medium Level Enable bit mask. */ -#define PMIC_MEDLVLEN_bp 1 /* Medium Level Enable bit position. */ - -#define PMIC_LOLVLEN_bm 0x01 /* Low Level Enable bit mask. */ -#define PMIC_LOLVLEN_bp 0 /* Low Level Enable bit position. */ - -/* PORTCFG - Port Configuration */ -/* PORTCFG.VPCTRLA bit masks and bit positions */ -#define PORTCFG_VP1MAP_gm 0xF0 /* Virtual Port 1 Mapping group mask. */ -#define PORTCFG_VP1MAP_gp 4 /* Virtual Port 1 Mapping group position. */ -#define PORTCFG_VP1MAP0_bm (1<<4) /* Virtual Port 1 Mapping bit 0 mask. */ -#define PORTCFG_VP1MAP0_bp 4 /* Virtual Port 1 Mapping bit 0 position. */ -#define PORTCFG_VP1MAP1_bm (1<<5) /* Virtual Port 1 Mapping bit 1 mask. */ -#define PORTCFG_VP1MAP1_bp 5 /* Virtual Port 1 Mapping bit 1 position. */ -#define PORTCFG_VP1MAP2_bm (1<<6) /* Virtual Port 1 Mapping bit 2 mask. */ -#define PORTCFG_VP1MAP2_bp 6 /* Virtual Port 1 Mapping bit 2 position. */ -#define PORTCFG_VP1MAP3_bm (1<<7) /* Virtual Port 1 Mapping bit 3 mask. */ -#define PORTCFG_VP1MAP3_bp 7 /* Virtual Port 1 Mapping bit 3 position. */ - -#define PORTCFG_VP0MAP_gm 0x0F /* Virtual Port 0 Mapping group mask. */ -#define PORTCFG_VP0MAP_gp 0 /* Virtual Port 0 Mapping group position. */ -#define PORTCFG_VP0MAP0_bm (1<<0) /* Virtual Port 0 Mapping bit 0 mask. */ -#define PORTCFG_VP0MAP0_bp 0 /* Virtual Port 0 Mapping bit 0 position. */ -#define PORTCFG_VP0MAP1_bm (1<<1) /* Virtual Port 0 Mapping bit 1 mask. */ -#define PORTCFG_VP0MAP1_bp 1 /* Virtual Port 0 Mapping bit 1 position. */ -#define PORTCFG_VP0MAP2_bm (1<<2) /* Virtual Port 0 Mapping bit 2 mask. */ -#define PORTCFG_VP0MAP2_bp 2 /* Virtual Port 0 Mapping bit 2 position. */ -#define PORTCFG_VP0MAP3_bm (1<<3) /* Virtual Port 0 Mapping bit 3 mask. */ -#define PORTCFG_VP0MAP3_bp 3 /* Virtual Port 0 Mapping bit 3 position. */ - -/* PORTCFG.VPCTRLB bit masks and bit positions */ -#define PORTCFG_VP3MAP_gm 0xF0 /* Virtual Port 3 Mapping group mask. */ -#define PORTCFG_VP3MAP_gp 4 /* Virtual Port 3 Mapping group position. */ -#define PORTCFG_VP3MAP0_bm (1<<4) /* Virtual Port 3 Mapping bit 0 mask. */ -#define PORTCFG_VP3MAP0_bp 4 /* Virtual Port 3 Mapping bit 0 position. */ -#define PORTCFG_VP3MAP1_bm (1<<5) /* Virtual Port 3 Mapping bit 1 mask. */ -#define PORTCFG_VP3MAP1_bp 5 /* Virtual Port 3 Mapping bit 1 position. */ -#define PORTCFG_VP3MAP2_bm (1<<6) /* Virtual Port 3 Mapping bit 2 mask. */ -#define PORTCFG_VP3MAP2_bp 6 /* Virtual Port 3 Mapping bit 2 position. */ -#define PORTCFG_VP3MAP3_bm (1<<7) /* Virtual Port 3 Mapping bit 3 mask. */ -#define PORTCFG_VP3MAP3_bp 7 /* Virtual Port 3 Mapping bit 3 position. */ - -#define PORTCFG_VP2MAP_gm 0x0F /* Virtual Port 2 Mapping group mask. */ -#define PORTCFG_VP2MAP_gp 0 /* Virtual Port 2 Mapping group position. */ -#define PORTCFG_VP2MAP0_bm (1<<0) /* Virtual Port 2 Mapping bit 0 mask. */ -#define PORTCFG_VP2MAP0_bp 0 /* Virtual Port 2 Mapping bit 0 position. */ -#define PORTCFG_VP2MAP1_bm (1<<1) /* Virtual Port 2 Mapping bit 1 mask. */ -#define PORTCFG_VP2MAP1_bp 1 /* Virtual Port 2 Mapping bit 1 position. */ -#define PORTCFG_VP2MAP2_bm (1<<2) /* Virtual Port 2 Mapping bit 2 mask. */ -#define PORTCFG_VP2MAP2_bp 2 /* Virtual Port 2 Mapping bit 2 position. */ -#define PORTCFG_VP2MAP3_bm (1<<3) /* Virtual Port 2 Mapping bit 3 mask. */ -#define PORTCFG_VP2MAP3_bp 3 /* Virtual Port 2 Mapping bit 3 position. */ - -/* PORTCFG.CLKEVOUT bit masks and bit positions */ -#define PORTCFG_CLKOUT_gm 0x03 /* Peripheral Clock Output Port group mask. */ -#define PORTCFG_CLKOUT_gp 0 /* Peripheral Clock Output Port group position. */ -#define PORTCFG_CLKOUT0_bm (1<<0) /* Peripheral Clock Output Port bit 0 mask. */ -#define PORTCFG_CLKOUT0_bp 0 /* Peripheral Clock Output Port bit 0 position. */ -#define PORTCFG_CLKOUT1_bm (1<<1) /* Peripheral Clock Output Port bit 1 mask. */ -#define PORTCFG_CLKOUT1_bp 1 /* Peripheral Clock Output Port bit 1 position. */ - -#define PORTCFG_CLKOUTSEL_gm 0x0C /* Peripheral Clock Output Select group mask. */ -#define PORTCFG_CLKOUTSEL_gp 2 /* Peripheral Clock Output Select group position. */ -#define PORTCFG_CLKOUTSEL0_bm (1<<2) /* Peripheral Clock Output Select bit 0 mask. */ -#define PORTCFG_CLKOUTSEL0_bp 2 /* Peripheral Clock Output Select bit 0 position. */ -#define PORTCFG_CLKOUTSEL1_bm (1<<3) /* Peripheral Clock Output Select bit 1 mask. */ -#define PORTCFG_CLKOUTSEL1_bp 3 /* Peripheral Clock Output Select bit 1 position. */ - -#define PORTCFG_EVOUT_gm 0x30 /* Event Output Port group mask. */ -#define PORTCFG_EVOUT_gp 4 /* Event Output Port group position. */ -#define PORTCFG_EVOUT0_bm (1<<4) /* Event Output Port bit 0 mask. */ -#define PORTCFG_EVOUT0_bp 4 /* Event Output Port bit 0 position. */ -#define PORTCFG_EVOUT1_bm (1<<5) /* Event Output Port bit 1 mask. */ -#define PORTCFG_EVOUT1_bp 5 /* Event Output Port bit 1 position. */ - -#define PORTCFG_RTCOUT_bm 0x40 /* RTC Clock Output bit mask. */ -#define PORTCFG_RTCOUT_bp 6 /* RTC Clock Output bit position. */ - -#define PORTCFG_CLKEVPIN_bm 0x80 /* Peripheral Clock and Event Output pin Select bit mask. */ -#define PORTCFG_CLKEVPIN_bp 7 /* Peripheral Clock and Event Output pin Select bit position. */ - -/* PORTCFG.EVOUTSEL bit masks and bit positions */ -#define PORTCFG_EVOUTSEL_gm 0x07 /* Event Output Select group mask. */ -#define PORTCFG_EVOUTSEL_gp 0 /* Event Output Select group position. */ -#define PORTCFG_EVOUTSEL0_bm (1<<0) /* Event Output Select bit 0 mask. */ -#define PORTCFG_EVOUTSEL0_bp 0 /* Event Output Select bit 0 position. */ -#define PORTCFG_EVOUTSEL1_bm (1<<1) /* Event Output Select bit 1 mask. */ -#define PORTCFG_EVOUTSEL1_bp 1 /* Event Output Select bit 1 position. */ -#define PORTCFG_EVOUTSEL2_bm (1<<2) /* Event Output Select bit 2 mask. */ -#define PORTCFG_EVOUTSEL2_bp 2 /* Event Output Select bit 2 position. */ - -/* CRC - Cyclic Redundancy Checker */ -/* CRC.CTRL bit masks and bit positions */ -#define CRC_RESET_gm 0xC0 /* Reset group mask. */ -#define CRC_RESET_gp 6 /* Reset group position. */ -#define CRC_RESET0_bm (1<<6) /* Reset bit 0 mask. */ -#define CRC_RESET0_bp 6 /* Reset bit 0 position. */ -#define CRC_RESET1_bm (1<<7) /* Reset bit 1 mask. */ -#define CRC_RESET1_bp 7 /* Reset bit 1 position. */ - -#define CRC_CRC32_bm 0x20 /* CRC Mode bit mask. */ -#define CRC_CRC32_bp 5 /* CRC Mode bit position. */ - -#define CRC_SOURCE_gm 0x0F /* Input Source group mask. */ -#define CRC_SOURCE_gp 0 /* Input Source group position. */ -#define CRC_SOURCE0_bm (1<<0) /* Input Source bit 0 mask. */ -#define CRC_SOURCE0_bp 0 /* Input Source bit 0 position. */ -#define CRC_SOURCE1_bm (1<<1) /* Input Source bit 1 mask. */ -#define CRC_SOURCE1_bp 1 /* Input Source bit 1 position. */ -#define CRC_SOURCE2_bm (1<<2) /* Input Source bit 2 mask. */ -#define CRC_SOURCE2_bp 2 /* Input Source bit 2 position. */ -#define CRC_SOURCE3_bm (1<<3) /* Input Source bit 3 mask. */ -#define CRC_SOURCE3_bp 3 /* Input Source bit 3 position. */ - -/* CRC.STATUS bit masks and bit positions */ -#define CRC_ZERO_bm 0x02 /* Zero detection bit mask. */ -#define CRC_ZERO_bp 1 /* Zero detection bit position. */ - -#define CRC_BUSY_bm 0x01 /* Busy bit mask. */ -#define CRC_BUSY_bp 0 /* Busy bit position. */ - -/* EVSYS - Event System */ -/* EVSYS.CH0MUX bit masks and bit positions */ -#define EVSYS_CHMUX_gm 0xFF /* Event Channel 0 Multiplexer group mask. */ -#define EVSYS_CHMUX_gp 0 /* Event Channel 0 Multiplexer group position. */ -#define EVSYS_CHMUX0_bm (1<<0) /* Event Channel 0 Multiplexer bit 0 mask. */ -#define EVSYS_CHMUX0_bp 0 /* Event Channel 0 Multiplexer bit 0 position. */ -#define EVSYS_CHMUX1_bm (1<<1) /* Event Channel 0 Multiplexer bit 1 mask. */ -#define EVSYS_CHMUX1_bp 1 /* Event Channel 0 Multiplexer bit 1 position. */ -#define EVSYS_CHMUX2_bm (1<<2) /* Event Channel 0 Multiplexer bit 2 mask. */ -#define EVSYS_CHMUX2_bp 2 /* Event Channel 0 Multiplexer bit 2 position. */ -#define EVSYS_CHMUX3_bm (1<<3) /* Event Channel 0 Multiplexer bit 3 mask. */ -#define EVSYS_CHMUX3_bp 3 /* Event Channel 0 Multiplexer bit 3 position. */ -#define EVSYS_CHMUX4_bm (1<<4) /* Event Channel 0 Multiplexer bit 4 mask. */ -#define EVSYS_CHMUX4_bp 4 /* Event Channel 0 Multiplexer bit 4 position. */ -#define EVSYS_CHMUX5_bm (1<<5) /* Event Channel 0 Multiplexer bit 5 mask. */ -#define EVSYS_CHMUX5_bp 5 /* Event Channel 0 Multiplexer bit 5 position. */ -#define EVSYS_CHMUX6_bm (1<<6) /* Event Channel 0 Multiplexer bit 6 mask. */ -#define EVSYS_CHMUX6_bp 6 /* Event Channel 0 Multiplexer bit 6 position. */ -#define EVSYS_CHMUX7_bm (1<<7) /* Event Channel 0 Multiplexer bit 7 mask. */ -#define EVSYS_CHMUX7_bp 7 /* Event Channel 0 Multiplexer bit 7 position. */ - -/* EVSYS.CH1MUX bit masks and bit positions */ -/* EVSYS_CHMUX Predefined. */ -/* EVSYS_CHMUX Predefined. */ - -/* EVSYS.CH2MUX bit masks and bit positions */ -/* EVSYS_CHMUX Predefined. */ -/* EVSYS_CHMUX Predefined. */ - -/* EVSYS.CH3MUX bit masks and bit positions */ -/* EVSYS_CHMUX Predefined. */ -/* EVSYS_CHMUX Predefined. */ - -/* EVSYS.CH0CTRL bit masks and bit positions */ -#define EVSYS_QDIRM_gm 0x60 /* Quadrature Decoder Index Recognition Mode group mask. */ -#define EVSYS_QDIRM_gp 5 /* Quadrature Decoder Index Recognition Mode group position. */ -#define EVSYS_QDIRM0_bm (1<<5) /* Quadrature Decoder Index Recognition Mode bit 0 mask. */ -#define EVSYS_QDIRM0_bp 5 /* Quadrature Decoder Index Recognition Mode bit 0 position. */ -#define EVSYS_QDIRM1_bm (1<<6) /* Quadrature Decoder Index Recognition Mode bit 1 mask. */ -#define EVSYS_QDIRM1_bp 6 /* Quadrature Decoder Index Recognition Mode bit 1 position. */ - -#define EVSYS_QDIEN_bm 0x10 /* Quadrature Decoder Index Enable bit mask. */ -#define EVSYS_QDIEN_bp 4 /* Quadrature Decoder Index Enable bit position. */ - -#define EVSYS_QDEN_bm 0x08 /* Quadrature Decoder Enable bit mask. */ -#define EVSYS_QDEN_bp 3 /* Quadrature Decoder Enable bit position. */ - -#define EVSYS_DIGFILT_gm 0x07 /* Digital Filter group mask. */ -#define EVSYS_DIGFILT_gp 0 /* Digital Filter group position. */ -#define EVSYS_DIGFILT0_bm (1<<0) /* Digital Filter bit 0 mask. */ -#define EVSYS_DIGFILT0_bp 0 /* Digital Filter bit 0 position. */ -#define EVSYS_DIGFILT1_bm (1<<1) /* Digital Filter bit 1 mask. */ -#define EVSYS_DIGFILT1_bp 1 /* Digital Filter bit 1 position. */ -#define EVSYS_DIGFILT2_bm (1<<2) /* Digital Filter bit 2 mask. */ -#define EVSYS_DIGFILT2_bp 2 /* Digital Filter bit 2 position. */ - -/* EVSYS.CH1CTRL bit masks and bit positions */ -/* EVSYS_DIGFILT Predefined. */ -/* EVSYS_DIGFILT Predefined. */ - -/* EVSYS.CH2CTRL bit masks and bit positions */ -/* EVSYS_DIGFILT Predefined. */ -/* EVSYS_DIGFILT Predefined. */ - -/* EVSYS.CH3CTRL bit masks and bit positions */ -/* EVSYS_DIGFILT Predefined. */ -/* EVSYS_DIGFILT Predefined. */ - -/* NVM - Non Volatile Memory Controller */ -/* NVM.CMD bit masks and bit positions */ -#define NVM_CMD_gm 0x7F /* Command group mask. */ -#define NVM_CMD_gp 0 /* Command group position. */ -#define NVM_CMD0_bm (1<<0) /* Command bit 0 mask. */ -#define NVM_CMD0_bp 0 /* Command bit 0 position. */ -#define NVM_CMD1_bm (1<<1) /* Command bit 1 mask. */ -#define NVM_CMD1_bp 1 /* Command bit 1 position. */ -#define NVM_CMD2_bm (1<<2) /* Command bit 2 mask. */ -#define NVM_CMD2_bp 2 /* Command bit 2 position. */ -#define NVM_CMD3_bm (1<<3) /* Command bit 3 mask. */ -#define NVM_CMD3_bp 3 /* Command bit 3 position. */ -#define NVM_CMD4_bm (1<<4) /* Command bit 4 mask. */ -#define NVM_CMD4_bp 4 /* Command bit 4 position. */ -#define NVM_CMD5_bm (1<<5) /* Command bit 5 mask. */ -#define NVM_CMD5_bp 5 /* Command bit 5 position. */ -#define NVM_CMD6_bm (1<<6) /* Command bit 6 mask. */ -#define NVM_CMD6_bp 6 /* Command bit 6 position. */ - -/* NVM.CTRLA bit masks and bit positions */ -#define NVM_CMDEX_bm 0x01 /* Command Execute bit mask. */ -#define NVM_CMDEX_bp 0 /* Command Execute bit position. */ - -/* NVM.CTRLB bit masks and bit positions */ -#define NVM_EEMAPEN_bm 0x08 /* EEPROM Mapping Enable bit mask. */ -#define NVM_EEMAPEN_bp 3 /* EEPROM Mapping Enable bit position. */ - -#define NVM_FPRM_bm 0x04 /* Flash Power Reduction Enable bit mask. */ -#define NVM_FPRM_bp 2 /* Flash Power Reduction Enable bit position. */ - -#define NVM_EPRM_bm 0x02 /* EEPROM Power Reduction Enable bit mask. */ -#define NVM_EPRM_bp 1 /* EEPROM Power Reduction Enable bit position. */ - -#define NVM_SPMLOCK_bm 0x01 /* SPM Lock bit mask. */ -#define NVM_SPMLOCK_bp 0 /* SPM Lock bit position. */ - -/* NVM.INTCTRL bit masks and bit positions */ -#define NVM_SPMLVL_gm 0x0C /* SPM Interrupt Level group mask. */ -#define NVM_SPMLVL_gp 2 /* SPM Interrupt Level group position. */ -#define NVM_SPMLVL0_bm (1<<2) /* SPM Interrupt Level bit 0 mask. */ -#define NVM_SPMLVL0_bp 2 /* SPM Interrupt Level bit 0 position. */ -#define NVM_SPMLVL1_bm (1<<3) /* SPM Interrupt Level bit 1 mask. */ -#define NVM_SPMLVL1_bp 3 /* SPM Interrupt Level bit 1 position. */ - -#define NVM_EELVL_gm 0x03 /* EEPROM Interrupt Level group mask. */ -#define NVM_EELVL_gp 0 /* EEPROM Interrupt Level group position. */ -#define NVM_EELVL0_bm (1<<0) /* EEPROM Interrupt Level bit 0 mask. */ -#define NVM_EELVL0_bp 0 /* EEPROM Interrupt Level bit 0 position. */ -#define NVM_EELVL1_bm (1<<1) /* EEPROM Interrupt Level bit 1 mask. */ -#define NVM_EELVL1_bp 1 /* EEPROM Interrupt Level bit 1 position. */ - -/* NVM.STATUS bit masks and bit positions */ -#define NVM_NVMBUSY_bm 0x80 /* Non-volatile Memory Busy bit mask. */ -#define NVM_NVMBUSY_bp 7 /* Non-volatile Memory Busy bit position. */ - -#define NVM_FBUSY_bm 0x40 /* Flash Memory Busy bit mask. */ -#define NVM_FBUSY_bp 6 /* Flash Memory Busy bit position. */ - -#define NVM_EELOAD_bm 0x02 /* EEPROM Page Buffer Active Loading bit mask. */ -#define NVM_EELOAD_bp 1 /* EEPROM Page Buffer Active Loading bit position. */ - -#define NVM_FLOAD_bm 0x01 /* Flash Page Buffer Active Loading bit mask. */ -#define NVM_FLOAD_bp 0 /* Flash Page Buffer Active Loading bit position. */ - -/* NVM.LOCKBITS bit masks and bit positions */ -#define NVM_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ -#define NVM_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ -#define NVM_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ -#define NVM_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ -#define NVM_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ -#define NVM_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ - -#define NVM_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ -#define NVM_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ -#define NVM_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ -#define NVM_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ -#define NVM_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ -#define NVM_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ - -#define NVM_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ -#define NVM_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ -#define NVM_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ -#define NVM_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ -#define NVM_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ -#define NVM_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ - -#define NVM_LB_gm 0x03 /* Lock Bits group mask. */ -#define NVM_LB_gp 0 /* Lock Bits group position. */ -#define NVM_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ -#define NVM_LB0_bp 0 /* Lock Bits bit 0 position. */ -#define NVM_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ -#define NVM_LB1_bp 1 /* Lock Bits bit 1 position. */ - -/* ADC - Analog/Digital Converter */ -/* ADC_CH.CTRL bit masks and bit positions */ -#define ADC_CH_START_bm 0x80 /* Channel Start Conversion bit mask. */ -#define ADC_CH_START_bp 7 /* Channel Start Conversion bit position. */ - -#define ADC_CH_GAIN_gm 0x1C /* Gain Factor group mask. */ -#define ADC_CH_GAIN_gp 2 /* Gain Factor group position. */ -#define ADC_CH_GAIN0_bm (1<<2) /* Gain Factor bit 0 mask. */ -#define ADC_CH_GAIN0_bp 2 /* Gain Factor bit 0 position. */ -#define ADC_CH_GAIN1_bm (1<<3) /* Gain Factor bit 1 mask. */ -#define ADC_CH_GAIN1_bp 3 /* Gain Factor bit 1 position. */ -#define ADC_CH_GAIN2_bm (1<<4) /* Gain Factor bit 2 mask. */ -#define ADC_CH_GAIN2_bp 4 /* Gain Factor bit 2 position. */ - -#define ADC_CH_INPUTMODE_gm 0x03 /* Input Mode Select group mask. */ -#define ADC_CH_INPUTMODE_gp 0 /* Input Mode Select group position. */ -#define ADC_CH_INPUTMODE0_bm (1<<0) /* Input Mode Select bit 0 mask. */ -#define ADC_CH_INPUTMODE0_bp 0 /* Input Mode Select bit 0 position. */ -#define ADC_CH_INPUTMODE1_bm (1<<1) /* Input Mode Select bit 1 mask. */ -#define ADC_CH_INPUTMODE1_bp 1 /* Input Mode Select bit 1 position. */ - -/* ADC_CH.MUXCTRL bit masks and bit positions */ -#define ADC_CH_MUXPOS_gm 0x78 /* MUX selection on Positive ADC input group mask. */ -#define ADC_CH_MUXPOS_gp 3 /* MUX selection on Positive ADC input group position. */ -#define ADC_CH_MUXPOS0_bm (1<<3) /* MUX selection on Positive ADC input bit 0 mask. */ -#define ADC_CH_MUXPOS0_bp 3 /* MUX selection on Positive ADC input bit 0 position. */ -#define ADC_CH_MUXPOS1_bm (1<<4) /* MUX selection on Positive ADC input bit 1 mask. */ -#define ADC_CH_MUXPOS1_bp 4 /* MUX selection on Positive ADC input bit 1 position. */ -#define ADC_CH_MUXPOS2_bm (1<<5) /* MUX selection on Positive ADC input bit 2 mask. */ -#define ADC_CH_MUXPOS2_bp 5 /* MUX selection on Positive ADC input bit 2 position. */ -#define ADC_CH_MUXPOS3_bm (1<<6) /* MUX selection on Positive ADC input bit 3 mask. */ -#define ADC_CH_MUXPOS3_bp 6 /* MUX selection on Positive ADC input bit 3 position. */ - -#define ADC_CH_MUXINT_gm 0x78 /* MUX selection on Internal ADC input group mask. */ -#define ADC_CH_MUXINT_gp 3 /* MUX selection on Internal ADC input group position. */ -#define ADC_CH_MUXINT0_bm (1<<3) /* MUX selection on Internal ADC input bit 0 mask. */ -#define ADC_CH_MUXINT0_bp 3 /* MUX selection on Internal ADC input bit 0 position. */ -#define ADC_CH_MUXINT1_bm (1<<4) /* MUX selection on Internal ADC input bit 1 mask. */ -#define ADC_CH_MUXINT1_bp 4 /* MUX selection on Internal ADC input bit 1 position. */ -#define ADC_CH_MUXINT2_bm (1<<5) /* MUX selection on Internal ADC input bit 2 mask. */ -#define ADC_CH_MUXINT2_bp 5 /* MUX selection on Internal ADC input bit 2 position. */ -#define ADC_CH_MUXINT3_bm (1<<6) /* MUX selection on Internal ADC input bit 3 mask. */ -#define ADC_CH_MUXINT3_bp 6 /* MUX selection on Internal ADC input bit 3 position. */ - -#define ADC_CH_MUXNEG_gm 0x03 /* MUX selection on Negative ADC input group mask. */ -#define ADC_CH_MUXNEG_gp 0 /* MUX selection on Negative ADC input group position. */ -#define ADC_CH_MUXNEG0_bm (1<<0) /* MUX selection on Negative ADC input bit 0 mask. */ -#define ADC_CH_MUXNEG0_bp 0 /* MUX selection on Negative ADC input bit 0 position. */ -#define ADC_CH_MUXNEG1_bm (1<<1) /* MUX selection on Negative ADC input bit 1 mask. */ -#define ADC_CH_MUXNEG1_bp 1 /* MUX selection on Negative ADC input bit 1 position. */ - -/* ADC_CH.INTCTRL bit masks and bit positions */ -#define ADC_CH_INTMODE_gm 0x0C /* Interrupt Mode group mask. */ -#define ADC_CH_INTMODE_gp 2 /* Interrupt Mode group position. */ -#define ADC_CH_INTMODE0_bm (1<<2) /* Interrupt Mode bit 0 mask. */ -#define ADC_CH_INTMODE0_bp 2 /* Interrupt Mode bit 0 position. */ -#define ADC_CH_INTMODE1_bm (1<<3) /* Interrupt Mode bit 1 mask. */ -#define ADC_CH_INTMODE1_bp 3 /* Interrupt Mode bit 1 position. */ - -#define ADC_CH_INTLVL_gm 0x03 /* Interrupt Level group mask. */ -#define ADC_CH_INTLVL_gp 0 /* Interrupt Level group position. */ -#define ADC_CH_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */ -#define ADC_CH_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */ -#define ADC_CH_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ -#define ADC_CH_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */ - -/* ADC_CH.INTFLAGS bit masks and bit positions */ -#define ADC_CH_CHIF_bm 0x01 /* Channel Interrupt Flag bit mask. */ -#define ADC_CH_CHIF_bp 0 /* Channel Interrupt Flag bit position. */ - -/* ADC_CH.SCAN bit masks and bit positions */ -#define ADC_CH_OFFSET_gm 0xF0 /* Positive MUX setting offset group mask. */ -#define ADC_CH_OFFSET_gp 4 /* Positive MUX setting offset group position. */ -#define ADC_CH_OFFSET0_bm (1<<4) /* Positive MUX setting offset bit 0 mask. */ -#define ADC_CH_OFFSET0_bp 4 /* Positive MUX setting offset bit 0 position. */ -#define ADC_CH_OFFSET1_bm (1<<5) /* Positive MUX setting offset bit 1 mask. */ -#define ADC_CH_OFFSET1_bp 5 /* Positive MUX setting offset bit 1 position. */ -#define ADC_CH_OFFSET2_bm (1<<6) /* Positive MUX setting offset bit 2 mask. */ -#define ADC_CH_OFFSET2_bp 6 /* Positive MUX setting offset bit 2 position. */ -#define ADC_CH_OFFSET3_bm (1<<7) /* Positive MUX setting offset bit 3 mask. */ -#define ADC_CH_OFFSET3_bp 7 /* Positive MUX setting offset bit 3 position. */ - -#define ADC_CH_SCANNUM_gm 0x0F /* Number of Channels included in scan group mask. */ -#define ADC_CH_SCANNUM_gp 0 /* Number of Channels included in scan group position. */ -#define ADC_CH_SCANNUM0_bm (1<<0) /* Number of Channels included in scan bit 0 mask. */ -#define ADC_CH_SCANNUM0_bp 0 /* Number of Channels included in scan bit 0 position. */ -#define ADC_CH_SCANNUM1_bm (1<<1) /* Number of Channels included in scan bit 1 mask. */ -#define ADC_CH_SCANNUM1_bp 1 /* Number of Channels included in scan bit 1 position. */ -#define ADC_CH_SCANNUM2_bm (1<<2) /* Number of Channels included in scan bit 2 mask. */ -#define ADC_CH_SCANNUM2_bp 2 /* Number of Channels included in scan bit 2 position. */ -#define ADC_CH_SCANNUM3_bm (1<<3) /* Number of Channels included in scan bit 3 mask. */ -#define ADC_CH_SCANNUM3_bp 3 /* Number of Channels included in scan bit 3 position. */ - -/* ADC.CTRLA bit masks and bit positions */ -#define ADC_CH0START_bm 0x04 /* Channel 0 Start Conversion bit mask. */ -#define ADC_CH0START_bp 2 /* Channel 0 Start Conversion bit position. */ - -#define ADC_FLUSH_bm 0x02 /* ADC Flush bit mask. */ -#define ADC_FLUSH_bp 1 /* ADC Flush bit position. */ - -#define ADC_ENABLE_bm 0x01 /* Enable ADC bit mask. */ -#define ADC_ENABLE_bp 0 /* Enable ADC bit position. */ - -/* ADC.CTRLB bit masks and bit positions */ -#define ADC_CURRLIMIT_gm 0x60 /* Current Limitation group mask. */ -#define ADC_CURRLIMIT_gp 5 /* Current Limitation group position. */ -#define ADC_CURRLIMIT0_bm (1<<5) /* Current Limitation bit 0 mask. */ -#define ADC_CURRLIMIT0_bp 5 /* Current Limitation bit 0 position. */ -#define ADC_CURRLIMIT1_bm (1<<6) /* Current Limitation bit 1 mask. */ -#define ADC_CURRLIMIT1_bp 6 /* Current Limitation bit 1 position. */ - -#define ADC_CONMODE_bm 0x10 /* Conversion Mode bit mask. */ -#define ADC_CONMODE_bp 4 /* Conversion Mode bit position. */ - -#define ADC_FREERUN_bm 0x08 /* Free Running Mode Enable bit mask. */ -#define ADC_FREERUN_bp 3 /* Free Running Mode Enable bit position. */ - -#define ADC_RESOLUTION_gm 0x06 /* Result Resolution group mask. */ -#define ADC_RESOLUTION_gp 1 /* Result Resolution group position. */ -#define ADC_RESOLUTION0_bm (1<<1) /* Result Resolution bit 0 mask. */ -#define ADC_RESOLUTION0_bp 1 /* Result Resolution bit 0 position. */ -#define ADC_RESOLUTION1_bm (1<<2) /* Result Resolution bit 1 mask. */ -#define ADC_RESOLUTION1_bp 2 /* Result Resolution bit 1 position. */ - -/* ADC.REFCTRL bit masks and bit positions */ -#define ADC_REFSEL_gm 0x70 /* Reference Selection group mask. */ -#define ADC_REFSEL_gp 4 /* Reference Selection group position. */ -#define ADC_REFSEL0_bm (1<<4) /* Reference Selection bit 0 mask. */ -#define ADC_REFSEL0_bp 4 /* Reference Selection bit 0 position. */ -#define ADC_REFSEL1_bm (1<<5) /* Reference Selection bit 1 mask. */ -#define ADC_REFSEL1_bp 5 /* Reference Selection bit 1 position. */ -#define ADC_REFSEL2_bm (1<<6) /* Reference Selection bit 2 mask. */ -#define ADC_REFSEL2_bp 6 /* Reference Selection bit 2 position. */ - -#define ADC_BANDGAP_bm 0x02 /* Bandgap enable bit mask. */ -#define ADC_BANDGAP_bp 1 /* Bandgap enable bit position. */ - -#define ADC_TEMPREF_bm 0x01 /* Temperature Reference Enable bit mask. */ -#define ADC_TEMPREF_bp 0 /* Temperature Reference Enable bit position. */ - -/* ADC.EVCTRL bit masks and bit positions */ -#define ADC_EVSEL_gm 0x18 /* Event Input Select group mask. */ -#define ADC_EVSEL_gp 3 /* Event Input Select group position. */ -#define ADC_EVSEL0_bm (1<<3) /* Event Input Select bit 0 mask. */ -#define ADC_EVSEL0_bp 3 /* Event Input Select bit 0 position. */ -#define ADC_EVSEL1_bm (1<<4) /* Event Input Select bit 1 mask. */ -#define ADC_EVSEL1_bp 4 /* Event Input Select bit 1 position. */ - -#define ADC_EVACT_gm 0x07 /* Event Action Select group mask. */ -#define ADC_EVACT_gp 0 /* Event Action Select group position. */ -#define ADC_EVACT0_bm (1<<0) /* Event Action Select bit 0 mask. */ -#define ADC_EVACT0_bp 0 /* Event Action Select bit 0 position. */ -#define ADC_EVACT1_bm (1<<1) /* Event Action Select bit 1 mask. */ -#define ADC_EVACT1_bp 1 /* Event Action Select bit 1 position. */ -#define ADC_EVACT2_bm (1<<2) /* Event Action Select bit 2 mask. */ -#define ADC_EVACT2_bp 2 /* Event Action Select bit 2 position. */ - -/* ADC.PRESCALER bit masks and bit positions */ -#define ADC_PRESCALER_gm 0x07 /* Clock Prescaler Selection group mask. */ -#define ADC_PRESCALER_gp 0 /* Clock Prescaler Selection group position. */ -#define ADC_PRESCALER0_bm (1<<0) /* Clock Prescaler Selection bit 0 mask. */ -#define ADC_PRESCALER0_bp 0 /* Clock Prescaler Selection bit 0 position. */ -#define ADC_PRESCALER1_bm (1<<1) /* Clock Prescaler Selection bit 1 mask. */ -#define ADC_PRESCALER1_bp 1 /* Clock Prescaler Selection bit 1 position. */ -#define ADC_PRESCALER2_bm (1<<2) /* Clock Prescaler Selection bit 2 mask. */ -#define ADC_PRESCALER2_bp 2 /* Clock Prescaler Selection bit 2 position. */ - -/* ADC.INTFLAGS bit masks and bit positions */ -#define ADC_CH0IF_bm 0x01 /* Channel 0 Interrupt Flag bit mask. */ -#define ADC_CH0IF_bp 0 /* Channel 0 Interrupt Flag bit position. */ - -/* AC - Analog Comparator */ -/* AC.AC0CTRL bit masks and bit positions */ -#define AC_INTMODE_gm 0xC0 /* Interrupt Mode group mask. */ -#define AC_INTMODE_gp 6 /* Interrupt Mode group position. */ -#define AC_INTMODE0_bm (1<<6) /* Interrupt Mode bit 0 mask. */ -#define AC_INTMODE0_bp 6 /* Interrupt Mode bit 0 position. */ -#define AC_INTMODE1_bm (1<<7) /* Interrupt Mode bit 1 mask. */ -#define AC_INTMODE1_bp 7 /* Interrupt Mode bit 1 position. */ - -#define AC_INTLVL_gm 0x30 /* Interrupt Level group mask. */ -#define AC_INTLVL_gp 4 /* Interrupt Level group position. */ -#define AC_INTLVL0_bm (1<<4) /* Interrupt Level bit 0 mask. */ -#define AC_INTLVL0_bp 4 /* Interrupt Level bit 0 position. */ -#define AC_INTLVL1_bm (1<<5) /* Interrupt Level bit 1 mask. */ -#define AC_INTLVL1_bp 5 /* Interrupt Level bit 1 position. */ - -#define AC_HYSMODE_gm 0x06 /* Hysteresis Mode group mask. */ -#define AC_HYSMODE_gp 1 /* Hysteresis Mode group position. */ -#define AC_HYSMODE0_bm (1<<1) /* Hysteresis Mode bit 0 mask. */ -#define AC_HYSMODE0_bp 1 /* Hysteresis Mode bit 0 position. */ -#define AC_HYSMODE1_bm (1<<2) /* Hysteresis Mode bit 1 mask. */ -#define AC_HYSMODE1_bp 2 /* Hysteresis Mode bit 1 position. */ - -#define AC_ENABLE_bm 0x01 /* Enable bit mask. */ -#define AC_ENABLE_bp 0 /* Enable bit position. */ - -/* AC.AC1CTRL bit masks and bit positions */ -/* AC_INTMODE Predefined. */ -/* AC_INTMODE Predefined. */ - -/* AC_INTLVL Predefined. */ -/* AC_INTLVL Predefined. */ - -/* AC_HYSMODE Predefined. */ -/* AC_HYSMODE Predefined. */ - -/* AC_ENABLE Predefined. */ -/* AC_ENABLE Predefined. */ - -/* AC.AC0MUXCTRL bit masks and bit positions */ -#define AC_MUXPOS_gm 0x38 /* MUX Positive Input group mask. */ -#define AC_MUXPOS_gp 3 /* MUX Positive Input group position. */ -#define AC_MUXPOS0_bm (1<<3) /* MUX Positive Input bit 0 mask. */ -#define AC_MUXPOS0_bp 3 /* MUX Positive Input bit 0 position. */ -#define AC_MUXPOS1_bm (1<<4) /* MUX Positive Input bit 1 mask. */ -#define AC_MUXPOS1_bp 4 /* MUX Positive Input bit 1 position. */ -#define AC_MUXPOS2_bm (1<<5) /* MUX Positive Input bit 2 mask. */ -#define AC_MUXPOS2_bp 5 /* MUX Positive Input bit 2 position. */ - -#define AC_MUXNEG_gm 0x07 /* MUX Negative Input group mask. */ -#define AC_MUXNEG_gp 0 /* MUX Negative Input group position. */ -#define AC_MUXNEG0_bm (1<<0) /* MUX Negative Input bit 0 mask. */ -#define AC_MUXNEG0_bp 0 /* MUX Negative Input bit 0 position. */ -#define AC_MUXNEG1_bm (1<<1) /* MUX Negative Input bit 1 mask. */ -#define AC_MUXNEG1_bp 1 /* MUX Negative Input bit 1 position. */ -#define AC_MUXNEG2_bm (1<<2) /* MUX Negative Input bit 2 mask. */ -#define AC_MUXNEG2_bp 2 /* MUX Negative Input bit 2 position. */ - -/* AC.AC1MUXCTRL bit masks and bit positions */ -/* AC_MUXPOS Predefined. */ -/* AC_MUXPOS Predefined. */ - -/* AC_MUXNEG Predefined. */ -/* AC_MUXNEG Predefined. */ - -/* AC.CTRLA bit masks and bit positions */ -#define AC_AC1OUT_bm 0x02 /* Analog Comparator 1 Output Enable bit mask. */ -#define AC_AC1OUT_bp 1 /* Analog Comparator 1 Output Enable bit position. */ - -#define AC_AC0OUT_bm 0x01 /* Analog Comparator 0 Output Enable bit mask. */ -#define AC_AC0OUT_bp 0 /* Analog Comparator 0 Output Enable bit position. */ - -/* AC.CTRLB bit masks and bit positions */ -#define AC_SCALEFAC_gm 0x3F /* VCC Voltage Scaler Factor group mask. */ -#define AC_SCALEFAC_gp 0 /* VCC Voltage Scaler Factor group position. */ -#define AC_SCALEFAC0_bm (1<<0) /* VCC Voltage Scaler Factor bit 0 mask. */ -#define AC_SCALEFAC0_bp 0 /* VCC Voltage Scaler Factor bit 0 position. */ -#define AC_SCALEFAC1_bm (1<<1) /* VCC Voltage Scaler Factor bit 1 mask. */ -#define AC_SCALEFAC1_bp 1 /* VCC Voltage Scaler Factor bit 1 position. */ -#define AC_SCALEFAC2_bm (1<<2) /* VCC Voltage Scaler Factor bit 2 mask. */ -#define AC_SCALEFAC2_bp 2 /* VCC Voltage Scaler Factor bit 2 position. */ -#define AC_SCALEFAC3_bm (1<<3) /* VCC Voltage Scaler Factor bit 3 mask. */ -#define AC_SCALEFAC3_bp 3 /* VCC Voltage Scaler Factor bit 3 position. */ -#define AC_SCALEFAC4_bm (1<<4) /* VCC Voltage Scaler Factor bit 4 mask. */ -#define AC_SCALEFAC4_bp 4 /* VCC Voltage Scaler Factor bit 4 position. */ -#define AC_SCALEFAC5_bm (1<<5) /* VCC Voltage Scaler Factor bit 5 mask. */ -#define AC_SCALEFAC5_bp 5 /* VCC Voltage Scaler Factor bit 5 position. */ - -/* AC.WINCTRL bit masks and bit positions */ -#define AC_WEN_bm 0x10 /* Window Mode Enable bit mask. */ -#define AC_WEN_bp 4 /* Window Mode Enable bit position. */ - -#define AC_WINTMODE_gm 0x0C /* Window Interrupt Mode group mask. */ -#define AC_WINTMODE_gp 2 /* Window Interrupt Mode group position. */ -#define AC_WINTMODE0_bm (1<<2) /* Window Interrupt Mode bit 0 mask. */ -#define AC_WINTMODE0_bp 2 /* Window Interrupt Mode bit 0 position. */ -#define AC_WINTMODE1_bm (1<<3) /* Window Interrupt Mode bit 1 mask. */ -#define AC_WINTMODE1_bp 3 /* Window Interrupt Mode bit 1 position. */ - -#define AC_WINTLVL_gm 0x03 /* Window Interrupt Level group mask. */ -#define AC_WINTLVL_gp 0 /* Window Interrupt Level group position. */ -#define AC_WINTLVL0_bm (1<<0) /* Window Interrupt Level bit 0 mask. */ -#define AC_WINTLVL0_bp 0 /* Window Interrupt Level bit 0 position. */ -#define AC_WINTLVL1_bm (1<<1) /* Window Interrupt Level bit 1 mask. */ -#define AC_WINTLVL1_bp 1 /* Window Interrupt Level bit 1 position. */ - -/* AC.STATUS bit masks and bit positions */ -#define AC_WSTATE_gm 0xC0 /* Window Mode State group mask. */ -#define AC_WSTATE_gp 6 /* Window Mode State group position. */ -#define AC_WSTATE0_bm (1<<6) /* Window Mode State bit 0 mask. */ -#define AC_WSTATE0_bp 6 /* Window Mode State bit 0 position. */ -#define AC_WSTATE1_bm (1<<7) /* Window Mode State bit 1 mask. */ -#define AC_WSTATE1_bp 7 /* Window Mode State bit 1 position. */ - -#define AC_AC1STATE_bm 0x20 /* Analog Comparator 1 State bit mask. */ -#define AC_AC1STATE_bp 5 /* Analog Comparator 1 State bit position. */ - -#define AC_AC0STATE_bm 0x10 /* Analog Comparator 0 State bit mask. */ -#define AC_AC0STATE_bp 4 /* Analog Comparator 0 State bit position. */ - -#define AC_WIF_bm 0x04 /* Window Mode Interrupt Flag bit mask. */ -#define AC_WIF_bp 2 /* Window Mode Interrupt Flag bit position. */ - -#define AC_AC1IF_bm 0x02 /* Analog Comparator 1 Interrupt Flag bit mask. */ -#define AC_AC1IF_bp 1 /* Analog Comparator 1 Interrupt Flag bit position. */ - -#define AC_AC0IF_bm 0x01 /* Analog Comparator 0 Interrupt Flag bit mask. */ -#define AC_AC0IF_bp 0 /* Analog Comparator 0 Interrupt Flag bit position. */ - -/* RTC - Real-Time Counter */ -/* RTC.CTRL bit masks and bit positions */ -#define RTC_PRESCALER_gm 0x07 /* Prescaling Factor group mask. */ -#define RTC_PRESCALER_gp 0 /* Prescaling Factor group position. */ -#define RTC_PRESCALER0_bm (1<<0) /* Prescaling Factor bit 0 mask. */ -#define RTC_PRESCALER0_bp 0 /* Prescaling Factor bit 0 position. */ -#define RTC_PRESCALER1_bm (1<<1) /* Prescaling Factor bit 1 mask. */ -#define RTC_PRESCALER1_bp 1 /* Prescaling Factor bit 1 position. */ -#define RTC_PRESCALER2_bm (1<<2) /* Prescaling Factor bit 2 mask. */ -#define RTC_PRESCALER2_bp 2 /* Prescaling Factor bit 2 position. */ - -/* RTC.STATUS bit masks and bit positions */ -#define RTC_SYNCBUSY_bm 0x01 /* Synchronization Busy Flag bit mask. */ -#define RTC_SYNCBUSY_bp 0 /* Synchronization Busy Flag bit position. */ - -/* RTC.INTCTRL bit masks and bit positions */ -#define RTC_COMPINTLVL_gm 0x0C /* Compare Match Interrupt Level group mask. */ -#define RTC_COMPINTLVL_gp 2 /* Compare Match Interrupt Level group position. */ -#define RTC_COMPINTLVL0_bm (1<<2) /* Compare Match Interrupt Level bit 0 mask. */ -#define RTC_COMPINTLVL0_bp 2 /* Compare Match Interrupt Level bit 0 position. */ -#define RTC_COMPINTLVL1_bm (1<<3) /* Compare Match Interrupt Level bit 1 mask. */ -#define RTC_COMPINTLVL1_bp 3 /* Compare Match Interrupt Level bit 1 position. */ - -#define RTC_OVFINTLVL_gm 0x03 /* Overflow Interrupt Level group mask. */ -#define RTC_OVFINTLVL_gp 0 /* Overflow Interrupt Level group position. */ -#define RTC_OVFINTLVL0_bm (1<<0) /* Overflow Interrupt Level bit 0 mask. */ -#define RTC_OVFINTLVL0_bp 0 /* Overflow Interrupt Level bit 0 position. */ -#define RTC_OVFINTLVL1_bm (1<<1) /* Overflow Interrupt Level bit 1 mask. */ -#define RTC_OVFINTLVL1_bp 1 /* Overflow Interrupt Level bit 1 position. */ - -/* RTC.INTFLAGS bit masks and bit positions */ -#define RTC_COMPIF_bm 0x02 /* Compare Match Interrupt Flag bit mask. */ -#define RTC_COMPIF_bp 1 /* Compare Match Interrupt Flag bit position. */ - -#define RTC_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ -#define RTC_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ - -/* TWI - Two-Wire Interface */ -/* TWI_MASTER.CTRLA bit masks and bit positions */ -#define TWI_MASTER_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ -#define TWI_MASTER_INTLVL_gp 6 /* Interrupt Level group position. */ -#define TWI_MASTER_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ -#define TWI_MASTER_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ -#define TWI_MASTER_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ -#define TWI_MASTER_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ - -#define TWI_MASTER_RIEN_bm 0x20 /* Read Interrupt Enable bit mask. */ -#define TWI_MASTER_RIEN_bp 5 /* Read Interrupt Enable bit position. */ - -#define TWI_MASTER_WIEN_bm 0x10 /* Write Interrupt Enable bit mask. */ -#define TWI_MASTER_WIEN_bp 4 /* Write Interrupt Enable bit position. */ - -#define TWI_MASTER_ENABLE_bm 0x08 /* Enable TWI Master bit mask. */ -#define TWI_MASTER_ENABLE_bp 3 /* Enable TWI Master bit position. */ - -/* TWI_MASTER.CTRLB bit masks and bit positions */ -#define TWI_MASTER_TIMEOUT_gm 0x0C /* Inactive Bus Timeout group mask. */ -#define TWI_MASTER_TIMEOUT_gp 2 /* Inactive Bus Timeout group position. */ -#define TWI_MASTER_TIMEOUT0_bm (1<<2) /* Inactive Bus Timeout bit 0 mask. */ -#define TWI_MASTER_TIMEOUT0_bp 2 /* Inactive Bus Timeout bit 0 position. */ -#define TWI_MASTER_TIMEOUT1_bm (1<<3) /* Inactive Bus Timeout bit 1 mask. */ -#define TWI_MASTER_TIMEOUT1_bp 3 /* Inactive Bus Timeout bit 1 position. */ - -#define TWI_MASTER_QCEN_bm 0x02 /* Quick Command Enable bit mask. */ -#define TWI_MASTER_QCEN_bp 1 /* Quick Command Enable bit position. */ - -#define TWI_MASTER_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ -#define TWI_MASTER_SMEN_bp 0 /* Smart Mode Enable bit position. */ - -/* TWI_MASTER.CTRLC bit masks and bit positions */ -#define TWI_MASTER_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ -#define TWI_MASTER_ACKACT_bp 2 /* Acknowledge Action bit position. */ - -#define TWI_MASTER_CMD_gm 0x03 /* Command group mask. */ -#define TWI_MASTER_CMD_gp 0 /* Command group position. */ -#define TWI_MASTER_CMD0_bm (1<<0) /* Command bit 0 mask. */ -#define TWI_MASTER_CMD0_bp 0 /* Command bit 0 position. */ -#define TWI_MASTER_CMD1_bm (1<<1) /* Command bit 1 mask. */ -#define TWI_MASTER_CMD1_bp 1 /* Command bit 1 position. */ - -/* TWI_MASTER.STATUS bit masks and bit positions */ -#define TWI_MASTER_RIF_bm 0x80 /* Read Interrupt Flag bit mask. */ -#define TWI_MASTER_RIF_bp 7 /* Read Interrupt Flag bit position. */ - -#define TWI_MASTER_WIF_bm 0x40 /* Write Interrupt Flag bit mask. */ -#define TWI_MASTER_WIF_bp 6 /* Write Interrupt Flag bit position. */ - -#define TWI_MASTER_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ -#define TWI_MASTER_CLKHOLD_bp 5 /* Clock Hold bit position. */ - -#define TWI_MASTER_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ -#define TWI_MASTER_RXACK_bp 4 /* Received Acknowledge bit position. */ - -#define TWI_MASTER_ARBLOST_bm 0x08 /* Arbitration Lost bit mask. */ -#define TWI_MASTER_ARBLOST_bp 3 /* Arbitration Lost bit position. */ - -#define TWI_MASTER_BUSERR_bm 0x04 /* Bus Error bit mask. */ -#define TWI_MASTER_BUSERR_bp 2 /* Bus Error bit position. */ - -#define TWI_MASTER_BUSSTATE_gm 0x03 /* Bus State group mask. */ -#define TWI_MASTER_BUSSTATE_gp 0 /* Bus State group position. */ -#define TWI_MASTER_BUSSTATE0_bm (1<<0) /* Bus State bit 0 mask. */ -#define TWI_MASTER_BUSSTATE0_bp 0 /* Bus State bit 0 position. */ -#define TWI_MASTER_BUSSTATE1_bm (1<<1) /* Bus State bit 1 mask. */ -#define TWI_MASTER_BUSSTATE1_bp 1 /* Bus State bit 1 position. */ - -/* TWI_SLAVE.CTRLA bit masks and bit positions */ -#define TWI_SLAVE_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ -#define TWI_SLAVE_INTLVL_gp 6 /* Interrupt Level group position. */ -#define TWI_SLAVE_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ -#define TWI_SLAVE_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ -#define TWI_SLAVE_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ -#define TWI_SLAVE_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ - -#define TWI_SLAVE_DIEN_bm 0x20 /* Data Interrupt Enable bit mask. */ -#define TWI_SLAVE_DIEN_bp 5 /* Data Interrupt Enable bit position. */ - -#define TWI_SLAVE_APIEN_bm 0x10 /* Address/Stop Interrupt Enable bit mask. */ -#define TWI_SLAVE_APIEN_bp 4 /* Address/Stop Interrupt Enable bit position. */ - -#define TWI_SLAVE_ENABLE_bm 0x08 /* Enable TWI Slave bit mask. */ -#define TWI_SLAVE_ENABLE_bp 3 /* Enable TWI Slave bit position. */ - -#define TWI_SLAVE_PIEN_bm 0x04 /* Stop Interrupt Enable bit mask. */ -#define TWI_SLAVE_PIEN_bp 2 /* Stop Interrupt Enable bit position. */ - -#define TWI_SLAVE_PMEN_bm 0x02 /* Promiscuous Mode Enable bit mask. */ -#define TWI_SLAVE_PMEN_bp 1 /* Promiscuous Mode Enable bit position. */ - -#define TWI_SLAVE_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ -#define TWI_SLAVE_SMEN_bp 0 /* Smart Mode Enable bit position. */ - -/* TWI_SLAVE.CTRLB bit masks and bit positions */ -#define TWI_SLAVE_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ -#define TWI_SLAVE_ACKACT_bp 2 /* Acknowledge Action bit position. */ - -#define TWI_SLAVE_CMD_gm 0x03 /* Command group mask. */ -#define TWI_SLAVE_CMD_gp 0 /* Command group position. */ -#define TWI_SLAVE_CMD0_bm (1<<0) /* Command bit 0 mask. */ -#define TWI_SLAVE_CMD0_bp 0 /* Command bit 0 position. */ -#define TWI_SLAVE_CMD1_bm (1<<1) /* Command bit 1 mask. */ -#define TWI_SLAVE_CMD1_bp 1 /* Command bit 1 position. */ - -/* TWI_SLAVE.STATUS bit masks and bit positions */ -#define TWI_SLAVE_DIF_bm 0x80 /* Data Interrupt Flag bit mask. */ -#define TWI_SLAVE_DIF_bp 7 /* Data Interrupt Flag bit position. */ - -#define TWI_SLAVE_APIF_bm 0x40 /* Address/Stop Interrupt Flag bit mask. */ -#define TWI_SLAVE_APIF_bp 6 /* Address/Stop Interrupt Flag bit position. */ - -#define TWI_SLAVE_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ -#define TWI_SLAVE_CLKHOLD_bp 5 /* Clock Hold bit position. */ - -#define TWI_SLAVE_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ -#define TWI_SLAVE_RXACK_bp 4 /* Received Acknowledge bit position. */ - -#define TWI_SLAVE_COLL_bm 0x08 /* Collision bit mask. */ -#define TWI_SLAVE_COLL_bp 3 /* Collision bit position. */ - -#define TWI_SLAVE_BUSERR_bm 0x04 /* Bus Error bit mask. */ -#define TWI_SLAVE_BUSERR_bp 2 /* Bus Error bit position. */ - -#define TWI_SLAVE_DIR_bm 0x02 /* Read/Write Direction bit mask. */ -#define TWI_SLAVE_DIR_bp 1 /* Read/Write Direction bit position. */ - -#define TWI_SLAVE_AP_bm 0x01 /* Slave Address or Stop bit mask. */ -#define TWI_SLAVE_AP_bp 0 /* Slave Address or Stop bit position. */ - -/* TWI_SLAVE.ADDRMASK bit masks and bit positions */ -#define TWI_SLAVE_ADDRMASK_gm 0xFE /* Address Mask group mask. */ -#define TWI_SLAVE_ADDRMASK_gp 1 /* Address Mask group position. */ -#define TWI_SLAVE_ADDRMASK0_bm (1<<1) /* Address Mask bit 0 mask. */ -#define TWI_SLAVE_ADDRMASK0_bp 1 /* Address Mask bit 0 position. */ -#define TWI_SLAVE_ADDRMASK1_bm (1<<2) /* Address Mask bit 1 mask. */ -#define TWI_SLAVE_ADDRMASK1_bp 2 /* Address Mask bit 1 position. */ -#define TWI_SLAVE_ADDRMASK2_bm (1<<3) /* Address Mask bit 2 mask. */ -#define TWI_SLAVE_ADDRMASK2_bp 3 /* Address Mask bit 2 position. */ -#define TWI_SLAVE_ADDRMASK3_bm (1<<4) /* Address Mask bit 3 mask. */ -#define TWI_SLAVE_ADDRMASK3_bp 4 /* Address Mask bit 3 position. */ -#define TWI_SLAVE_ADDRMASK4_bm (1<<5) /* Address Mask bit 4 mask. */ -#define TWI_SLAVE_ADDRMASK4_bp 5 /* Address Mask bit 4 position. */ -#define TWI_SLAVE_ADDRMASK5_bm (1<<6) /* Address Mask bit 5 mask. */ -#define TWI_SLAVE_ADDRMASK5_bp 6 /* Address Mask bit 5 position. */ -#define TWI_SLAVE_ADDRMASK6_bm (1<<7) /* Address Mask bit 6 mask. */ -#define TWI_SLAVE_ADDRMASK6_bp 7 /* Address Mask bit 6 position. */ - -#define TWI_SLAVE_ADDREN_bm 0x01 /* Address Enable bit mask. */ -#define TWI_SLAVE_ADDREN_bp 0 /* Address Enable bit position. */ - -/* TWI.CTRL bit masks and bit positions */ -#define TWI_SDAHOLD_gm 0x06 /* SDA Hold Time Enable group mask. */ -#define TWI_SDAHOLD_gp 1 /* SDA Hold Time Enable group position. */ -#define TWI_SDAHOLD0_bm (1<<1) /* SDA Hold Time Enable bit 0 mask. */ -#define TWI_SDAHOLD0_bp 1 /* SDA Hold Time Enable bit 0 position. */ -#define TWI_SDAHOLD1_bm (1<<2) /* SDA Hold Time Enable bit 1 mask. */ -#define TWI_SDAHOLD1_bp 2 /* SDA Hold Time Enable bit 1 position. */ - -#define TWI_EDIEN_bm 0x01 /* External Driver Interface Enable bit mask. */ -#define TWI_EDIEN_bp 0 /* External Driver Interface Enable bit position. */ - -/* PORT - Port Configuration */ -/* VPORT.INTFLAGS bit masks and bit positions */ -/* VPORT_INT1IF Predefined. */ -/* VPORT_INT1IF Predefined. */ - -/* VPORT_INT0IF Predefined. */ -/* VPORT_INT0IF Predefined. */ - -/* PORT.INTCTRL bit masks and bit positions */ -#define PORT_INT1LVL_gm 0x0C /* Port Interrupt 1 Level group mask. */ -#define PORT_INT1LVL_gp 2 /* Port Interrupt 1 Level group position. */ -#define PORT_INT1LVL0_bm (1<<2) /* Port Interrupt 1 Level bit 0 mask. */ -#define PORT_INT1LVL0_bp 2 /* Port Interrupt 1 Level bit 0 position. */ -#define PORT_INT1LVL1_bm (1<<3) /* Port Interrupt 1 Level bit 1 mask. */ -#define PORT_INT1LVL1_bp 3 /* Port Interrupt 1 Level bit 1 position. */ - -#define PORT_INT0LVL_gm 0x03 /* Port Interrupt 0 Level group mask. */ -#define PORT_INT0LVL_gp 0 /* Port Interrupt 0 Level group position. */ -#define PORT_INT0LVL0_bm (1<<0) /* Port Interrupt 0 Level bit 0 mask. */ -#define PORT_INT0LVL0_bp 0 /* Port Interrupt 0 Level bit 0 position. */ -#define PORT_INT0LVL1_bm (1<<1) /* Port Interrupt 0 Level bit 1 mask. */ -#define PORT_INT0LVL1_bp 1 /* Port Interrupt 0 Level bit 1 position. */ - -/* PORT.INTFLAGS bit masks and bit positions */ -#define PORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ -#define PORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ - -#define PORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ -#define PORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ - -/* PORT.REMAP bit masks and bit positions */ -#define PORT_SPI_bm 0x20 /* SPI Remap bit mask. */ -#define PORT_SPI_bp 5 /* SPI Remap bit position. */ - -#define PORT_USART0_bm 0x10 /* USART0 Remap bit mask. */ -#define PORT_USART0_bp 4 /* USART0 Remap bit position. */ - -#define PORT_TC0D_bm 0x08 /* Timer/Counter 0 Output Compare D bit mask. */ -#define PORT_TC0D_bp 3 /* Timer/Counter 0 Output Compare D bit position. */ - -#define PORT_TC0C_bm 0x04 /* Timer/Counter 0 Output Compare C bit mask. */ -#define PORT_TC0C_bp 2 /* Timer/Counter 0 Output Compare C bit position. */ - -#define PORT_TC0B_bm 0x02 /* Timer/Counter 0 Output Compare B bit mask. */ -#define PORT_TC0B_bp 1 /* Timer/Counter 0 Output Compare B bit position. */ - -#define PORT_TC0A_bm 0x01 /* Timer/Counter 0 Output Compare A bit mask. */ -#define PORT_TC0A_bp 0 /* Timer/Counter 0 Output Compare A bit position. */ - -/* PORT.PIN0CTRL bit masks and bit positions */ -#define PORT_SRLEN_bm 0x80 /* Slew Rate Enable bit mask. */ -#define PORT_SRLEN_bp 7 /* Slew Rate Enable bit position. */ - -#define PORT_INVEN_bm 0x40 /* Inverted I/O Enable bit mask. */ -#define PORT_INVEN_bp 6 /* Inverted I/O Enable bit position. */ - -#define PORT_OPC_gm 0x38 /* Output/Pull Configuration group mask. */ -#define PORT_OPC_gp 3 /* Output/Pull Configuration group position. */ -#define PORT_OPC0_bm (1<<3) /* Output/Pull Configuration bit 0 mask. */ -#define PORT_OPC0_bp 3 /* Output/Pull Configuration bit 0 position. */ -#define PORT_OPC1_bm (1<<4) /* Output/Pull Configuration bit 1 mask. */ -#define PORT_OPC1_bp 4 /* Output/Pull Configuration bit 1 position. */ -#define PORT_OPC2_bm (1<<5) /* Output/Pull Configuration bit 2 mask. */ -#define PORT_OPC2_bp 5 /* Output/Pull Configuration bit 2 position. */ - -#define PORT_ISC_gm 0x07 /* Input/Sense Configuration group mask. */ -#define PORT_ISC_gp 0 /* Input/Sense Configuration group position. */ -#define PORT_ISC0_bm (1<<0) /* Input/Sense Configuration bit 0 mask. */ -#define PORT_ISC0_bp 0 /* Input/Sense Configuration bit 0 position. */ -#define PORT_ISC1_bm (1<<1) /* Input/Sense Configuration bit 1 mask. */ -#define PORT_ISC1_bp 1 /* Input/Sense Configuration bit 1 position. */ -#define PORT_ISC2_bm (1<<2) /* Input/Sense Configuration bit 2 mask. */ -#define PORT_ISC2_bp 2 /* Input/Sense Configuration bit 2 position. */ - -/* PORT.PIN1CTRL bit masks and bit positions */ -/* PORT_SRLEN Predefined. */ -/* PORT_SRLEN Predefined. */ - -/* PORT_INVEN Predefined. */ -/* PORT_INVEN Predefined. */ - -/* PORT_OPC Predefined. */ -/* PORT_OPC Predefined. */ - -/* PORT_ISC Predefined. */ -/* PORT_ISC Predefined. */ - -/* PORT.PIN2CTRL bit masks and bit positions */ -/* PORT_SRLEN Predefined. */ -/* PORT_SRLEN Predefined. */ - -/* PORT_INVEN Predefined. */ -/* PORT_INVEN Predefined. */ - -/* PORT_OPC Predefined. */ -/* PORT_OPC Predefined. */ - -/* PORT_ISC Predefined. */ -/* PORT_ISC Predefined. */ - -/* PORT.PIN3CTRL bit masks and bit positions */ -/* PORT_SRLEN Predefined. */ -/* PORT_SRLEN Predefined. */ - -/* PORT_INVEN Predefined. */ -/* PORT_INVEN Predefined. */ - -/* PORT_OPC Predefined. */ -/* PORT_OPC Predefined. */ - -/* PORT_ISC Predefined. */ -/* PORT_ISC Predefined. */ - -/* PORT.PIN4CTRL bit masks and bit positions */ -/* PORT_SRLEN Predefined. */ -/* PORT_SRLEN Predefined. */ - -/* PORT_INVEN Predefined. */ -/* PORT_INVEN Predefined. */ - -/* PORT_OPC Predefined. */ -/* PORT_OPC Predefined. */ - -/* PORT_ISC Predefined. */ -/* PORT_ISC Predefined. */ - -/* PORT.PIN5CTRL bit masks and bit positions */ -/* PORT_SRLEN Predefined. */ -/* PORT_SRLEN Predefined. */ - -/* PORT_INVEN Predefined. */ -/* PORT_INVEN Predefined. */ - -/* PORT_OPC Predefined. */ -/* PORT_OPC Predefined. */ - -/* PORT_ISC Predefined. */ -/* PORT_ISC Predefined. */ - -/* PORT.PIN6CTRL bit masks and bit positions */ -/* PORT_SRLEN Predefined. */ -/* PORT_SRLEN Predefined. */ - -/* PORT_INVEN Predefined. */ -/* PORT_INVEN Predefined. */ - -/* PORT_OPC Predefined. */ -/* PORT_OPC Predefined. */ - -/* PORT_ISC Predefined. */ -/* PORT_ISC Predefined. */ - -/* PORT.PIN7CTRL bit masks and bit positions */ -/* PORT_SRLEN Predefined. */ -/* PORT_SRLEN Predefined. */ - -/* PORT_INVEN Predefined. */ -/* PORT_INVEN Predefined. */ - -/* PORT_OPC Predefined. */ -/* PORT_OPC Predefined. */ - -/* PORT_ISC Predefined. */ -/* PORT_ISC Predefined. */ - -/* TC - 16-bit Timer/Counter With PWM */ -/* TC0.CTRLA bit masks and bit positions */ -#define TC0_CLKSEL_gm 0x0F /* Clock Selection group mask. */ -#define TC0_CLKSEL_gp 0 /* Clock Selection group position. */ -#define TC0_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ -#define TC0_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ -#define TC0_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ -#define TC0_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ -#define TC0_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ -#define TC0_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ -#define TC0_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ -#define TC0_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ - -/* TC0.CTRLB bit masks and bit positions */ -#define TC0_CCDEN_bm 0x80 /* Compare or Capture D Enable bit mask. */ -#define TC0_CCDEN_bp 7 /* Compare or Capture D Enable bit position. */ - -#define TC0_CCCEN_bm 0x40 /* Compare or Capture C Enable bit mask. */ -#define TC0_CCCEN_bp 6 /* Compare or Capture C Enable bit position. */ - -#define TC0_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ -#define TC0_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ - -#define TC0_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ -#define TC0_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ - -#define TC0_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ -#define TC0_WGMODE_gp 0 /* Waveform generation mode group position. */ -#define TC0_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ -#define TC0_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ -#define TC0_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ -#define TC0_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ -#define TC0_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ -#define TC0_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ - -/* TC0.CTRLC bit masks and bit positions */ -#define TC0_CMPD_bm 0x08 /* Compare D Output Value bit mask. */ -#define TC0_CMPD_bp 3 /* Compare D Output Value bit position. */ - -#define TC0_CMPC_bm 0x04 /* Compare C Output Value bit mask. */ -#define TC0_CMPC_bp 2 /* Compare C Output Value bit position. */ - -#define TC0_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ -#define TC0_CMPB_bp 1 /* Compare B Output Value bit position. */ - -#define TC0_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ -#define TC0_CMPA_bp 0 /* Compare A Output Value bit position. */ - -/* TC0.CTRLD bit masks and bit positions */ -#define TC0_EVACT_gm 0xE0 /* Event Action group mask. */ -#define TC0_EVACT_gp 5 /* Event Action group position. */ -#define TC0_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ -#define TC0_EVACT0_bp 5 /* Event Action bit 0 position. */ -#define TC0_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ -#define TC0_EVACT1_bp 6 /* Event Action bit 1 position. */ -#define TC0_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ -#define TC0_EVACT2_bp 7 /* Event Action bit 2 position. */ - -#define TC0_EVDLY_bm 0x10 /* Event Delay bit mask. */ -#define TC0_EVDLY_bp 4 /* Event Delay bit position. */ - -#define TC0_EVSEL_gm 0x0F /* Event Source Select group mask. */ -#define TC0_EVSEL_gp 0 /* Event Source Select group position. */ -#define TC0_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ -#define TC0_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ -#define TC0_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ -#define TC0_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ -#define TC0_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ -#define TC0_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ -#define TC0_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ -#define TC0_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ - -/* TC0.CTRLE bit masks and bit positions */ -#define TC0_BYTEM_gm 0x03 /* Byte Mode group mask. */ -#define TC0_BYTEM_gp 0 /* Byte Mode group position. */ -#define TC0_BYTEM0_bm (1<<0) /* Byte Mode bit 0 mask. */ -#define TC0_BYTEM0_bp 0 /* Byte Mode bit 0 position. */ -#define TC0_BYTEM1_bm (1<<1) /* Byte Mode bit 1 mask. */ -#define TC0_BYTEM1_bp 1 /* Byte Mode bit 1 position. */ - -/* TC0.INTCTRLA bit masks and bit positions */ -#define TC0_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ -#define TC0_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ -#define TC0_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ -#define TC0_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ -#define TC0_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ -#define TC0_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ - -#define TC0_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ -#define TC0_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ -#define TC0_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ -#define TC0_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ -#define TC0_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ -#define TC0_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ - -/* TC0.INTCTRLB bit masks and bit positions */ -#define TC0_CCDINTLVL_gm 0xC0 /* Compare or Capture D Interrupt Level group mask. */ -#define TC0_CCDINTLVL_gp 6 /* Compare or Capture D Interrupt Level group position. */ -#define TC0_CCDINTLVL0_bm (1<<6) /* Compare or Capture D Interrupt Level bit 0 mask. */ -#define TC0_CCDINTLVL0_bp 6 /* Compare or Capture D Interrupt Level bit 0 position. */ -#define TC0_CCDINTLVL1_bm (1<<7) /* Compare or Capture D Interrupt Level bit 1 mask. */ -#define TC0_CCDINTLVL1_bp 7 /* Compare or Capture D Interrupt Level bit 1 position. */ - -#define TC0_CCCINTLVL_gm 0x30 /* Compare or Capture C Interrupt Level group mask. */ -#define TC0_CCCINTLVL_gp 4 /* Compare or Capture C Interrupt Level group position. */ -#define TC0_CCCINTLVL0_bm (1<<4) /* Compare or Capture C Interrupt Level bit 0 mask. */ -#define TC0_CCCINTLVL0_bp 4 /* Compare or Capture C Interrupt Level bit 0 position. */ -#define TC0_CCCINTLVL1_bm (1<<5) /* Compare or Capture C Interrupt Level bit 1 mask. */ -#define TC0_CCCINTLVL1_bp 5 /* Compare or Capture C Interrupt Level bit 1 position. */ - -#define TC0_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ -#define TC0_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ -#define TC0_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ -#define TC0_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ -#define TC0_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ -#define TC0_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ - -#define TC0_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ -#define TC0_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ -#define TC0_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ -#define TC0_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ -#define TC0_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ -#define TC0_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ - -/* TC0.CTRLFCLR bit masks and bit positions */ -#define TC0_CMD_gm 0x0C /* Command group mask. */ -#define TC0_CMD_gp 2 /* Command group position. */ -#define TC0_CMD0_bm (1<<2) /* Command bit 0 mask. */ -#define TC0_CMD0_bp 2 /* Command bit 0 position. */ -#define TC0_CMD1_bm (1<<3) /* Command bit 1 mask. */ -#define TC0_CMD1_bp 3 /* Command bit 1 position. */ - -#define TC0_LUPD_bm 0x02 /* Lock Update bit mask. */ -#define TC0_LUPD_bp 1 /* Lock Update bit position. */ - -#define TC0_DIR_bm 0x01 /* Direction bit mask. */ -#define TC0_DIR_bp 0 /* Direction bit position. */ - -/* TC0.CTRLFSET bit masks and bit positions */ -/* TC0_CMD Predefined. */ -/* TC0_CMD Predefined. */ - -/* TC0_LUPD Predefined. */ -/* TC0_LUPD Predefined. */ - -/* TC0_DIR Predefined. */ -/* TC0_DIR Predefined. */ - -/* TC0.CTRLGCLR bit masks and bit positions */ -#define TC0_CCDBV_bm 0x10 /* Compare or Capture D Buffer Valid bit mask. */ -#define TC0_CCDBV_bp 4 /* Compare or Capture D Buffer Valid bit position. */ - -#define TC0_CCCBV_bm 0x08 /* Compare or Capture C Buffer Valid bit mask. */ -#define TC0_CCCBV_bp 3 /* Compare or Capture C Buffer Valid bit position. */ - -#define TC0_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ -#define TC0_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ - -#define TC0_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ -#define TC0_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ - -#define TC0_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ -#define TC0_PERBV_bp 0 /* Period Buffer Valid bit position. */ - -/* TC0.CTRLGSET bit masks and bit positions */ -/* TC0_CCDBV Predefined. */ -/* TC0_CCDBV Predefined. */ - -/* TC0_CCCBV Predefined. */ -/* TC0_CCCBV Predefined. */ - -/* TC0_CCBBV Predefined. */ -/* TC0_CCBBV Predefined. */ - -/* TC0_CCABV Predefined. */ -/* TC0_CCABV Predefined. */ - -/* TC0_PERBV Predefined. */ -/* TC0_PERBV Predefined. */ - -/* TC0.INTFLAGS bit masks and bit positions */ -#define TC0_CCDIF_bm 0x80 /* Compare or Capture D Interrupt Flag bit mask. */ -#define TC0_CCDIF_bp 7 /* Compare or Capture D Interrupt Flag bit position. */ - -#define TC0_CCCIF_bm 0x40 /* Compare or Capture C Interrupt Flag bit mask. */ -#define TC0_CCCIF_bp 6 /* Compare or Capture C Interrupt Flag bit position. */ - -#define TC0_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ -#define TC0_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ - -#define TC0_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ -#define TC0_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ - -#define TC0_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ -#define TC0_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ - -#define TC0_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ -#define TC0_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ - -/* TC1.CTRLA bit masks and bit positions */ -#define TC1_CLKSEL_gm 0x0F /* Clock Selection group mask. */ -#define TC1_CLKSEL_gp 0 /* Clock Selection group position. */ -#define TC1_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ -#define TC1_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ -#define TC1_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ -#define TC1_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ -#define TC1_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ -#define TC1_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ -#define TC1_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ -#define TC1_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ - -/* TC1.CTRLB bit masks and bit positions */ -#define TC1_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ -#define TC1_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ - -#define TC1_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ -#define TC1_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ - -#define TC1_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ -#define TC1_WGMODE_gp 0 /* Waveform generation mode group position. */ -#define TC1_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ -#define TC1_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ -#define TC1_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ -#define TC1_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ -#define TC1_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ -#define TC1_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ - -/* TC1.CTRLC bit masks and bit positions */ -#define TC1_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ -#define TC1_CMPB_bp 1 /* Compare B Output Value bit position. */ - -#define TC1_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ -#define TC1_CMPA_bp 0 /* Compare A Output Value bit position. */ - -/* TC1.CTRLD bit masks and bit positions */ -#define TC1_EVACT_gm 0xE0 /* Event Action group mask. */ -#define TC1_EVACT_gp 5 /* Event Action group position. */ -#define TC1_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ -#define TC1_EVACT0_bp 5 /* Event Action bit 0 position. */ -#define TC1_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ -#define TC1_EVACT1_bp 6 /* Event Action bit 1 position. */ -#define TC1_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ -#define TC1_EVACT2_bp 7 /* Event Action bit 2 position. */ - -#define TC1_EVDLY_bm 0x10 /* Event Delay bit mask. */ -#define TC1_EVDLY_bp 4 /* Event Delay bit position. */ - -#define TC1_EVSEL_gm 0x0F /* Event Source Select group mask. */ -#define TC1_EVSEL_gp 0 /* Event Source Select group position. */ -#define TC1_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ -#define TC1_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ -#define TC1_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ -#define TC1_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ -#define TC1_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ -#define TC1_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ -#define TC1_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ -#define TC1_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ - -/* TC1.CTRLE bit masks and bit positions */ -#define TC1_BYTEM_bm 0x01 /* Byte Mode bit mask. */ -#define TC1_BYTEM_bp 0 /* Byte Mode bit position. */ - -/* TC1.INTCTRLA bit masks and bit positions */ -#define TC1_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ -#define TC1_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ -#define TC1_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ -#define TC1_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ -#define TC1_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ -#define TC1_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ - -#define TC1_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ -#define TC1_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ -#define TC1_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ -#define TC1_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ -#define TC1_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ -#define TC1_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ - -/* TC1.INTCTRLB bit masks and bit positions */ -#define TC1_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ -#define TC1_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ -#define TC1_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ -#define TC1_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ -#define TC1_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ -#define TC1_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ - -#define TC1_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ -#define TC1_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ -#define TC1_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ -#define TC1_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ -#define TC1_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ -#define TC1_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ - -/* TC1.CTRLFCLR bit masks and bit positions */ -#define TC1_CMD_gm 0x0C /* Command group mask. */ -#define TC1_CMD_gp 2 /* Command group position. */ -#define TC1_CMD0_bm (1<<2) /* Command bit 0 mask. */ -#define TC1_CMD0_bp 2 /* Command bit 0 position. */ -#define TC1_CMD1_bm (1<<3) /* Command bit 1 mask. */ -#define TC1_CMD1_bp 3 /* Command bit 1 position. */ - -#define TC1_LUPD_bm 0x02 /* Lock Update bit mask. */ -#define TC1_LUPD_bp 1 /* Lock Update bit position. */ - -#define TC1_DIR_bm 0x01 /* Direction bit mask. */ -#define TC1_DIR_bp 0 /* Direction bit position. */ - -/* TC1.CTRLFSET bit masks and bit positions */ -/* TC1_CMD Predefined. */ -/* TC1_CMD Predefined. */ - -/* TC1_LUPD Predefined. */ -/* TC1_LUPD Predefined. */ - -/* TC1_DIR Predefined. */ -/* TC1_DIR Predefined. */ - -/* TC1.CTRLGCLR bit masks and bit positions */ -#define TC1_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ -#define TC1_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ - -#define TC1_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ -#define TC1_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ - -#define TC1_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ -#define TC1_PERBV_bp 0 /* Period Buffer Valid bit position. */ - -/* TC1.CTRLGSET bit masks and bit positions */ -/* TC1_CCBBV Predefined. */ -/* TC1_CCBBV Predefined. */ - -/* TC1_CCABV Predefined. */ -/* TC1_CCABV Predefined. */ - -/* TC1_PERBV Predefined. */ -/* TC1_PERBV Predefined. */ - -/* TC1.INTFLAGS bit masks and bit positions */ -#define TC1_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ -#define TC1_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ - -#define TC1_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ -#define TC1_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ - -#define TC1_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ -#define TC1_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ - -#define TC1_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ -#define TC1_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ - -/* TC2 - 16-bit Timer/Counter type 2 */ -/* TC2.CTRLA bit masks and bit positions */ -#define TC2_CLKSEL_gm 0x0F /* Clock Selection group mask. */ -#define TC2_CLKSEL_gp 0 /* Clock Selection group position. */ -#define TC2_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ -#define TC2_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ -#define TC2_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ -#define TC2_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ -#define TC2_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ -#define TC2_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ -#define TC2_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ -#define TC2_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ - -/* TC2.CTRLB bit masks and bit positions */ -#define TC2_HCMPDEN_bm 0x80 /* High Byte Compare D Enable bit mask. */ -#define TC2_HCMPDEN_bp 7 /* High Byte Compare D Enable bit position. */ - -#define TC2_HCMPCEN_bm 0x40 /* High Byte Compare C Enable bit mask. */ -#define TC2_HCMPCEN_bp 6 /* High Byte Compare C Enable bit position. */ - -#define TC2_HCMPBEN_bm 0x20 /* High Byte Compare B Enable bit mask. */ -#define TC2_HCMPBEN_bp 5 /* High Byte Compare B Enable bit position. */ - -#define TC2_HCMPAEN_bm 0x10 /* High Byte Compare A Enable bit mask. */ -#define TC2_HCMPAEN_bp 4 /* High Byte Compare A Enable bit position. */ - -#define TC2_LCMPDEN_bm 0x08 /* Low Byte Compare D Enable bit mask. */ -#define TC2_LCMPDEN_bp 3 /* Low Byte Compare D Enable bit position. */ - -#define TC2_LCMPCEN_bm 0x04 /* Low Byte Compare C Enable bit mask. */ -#define TC2_LCMPCEN_bp 2 /* Low Byte Compare C Enable bit position. */ - -#define TC2_LCMPBEN_bm 0x02 /* Low Byte Compare B Enable bit mask. */ -#define TC2_LCMPBEN_bp 1 /* Low Byte Compare B Enable bit position. */ - -#define TC2_LCMPAEN_bm 0x01 /* Low Byte Compare A Enable bit mask. */ -#define TC2_LCMPAEN_bp 0 /* Low Byte Compare A Enable bit position. */ - -/* TC2.CTRLC bit masks and bit positions */ -#define TC2_HCMPD_bm 0x80 /* High Byte Compare D Output Value bit mask. */ -#define TC2_HCMPD_bp 7 /* High Byte Compare D Output Value bit position. */ - -#define TC2_HCMPC_bm 0x40 /* High Byte Compare C Output Value bit mask. */ -#define TC2_HCMPC_bp 6 /* High Byte Compare C Output Value bit position. */ - -#define TC2_HCMPB_bm 0x20 /* High Byte Compare B Output Value bit mask. */ -#define TC2_HCMPB_bp 5 /* High Byte Compare B Output Value bit position. */ - -#define TC2_HCMPA_bm 0x10 /* High Byte Compare A Output Value bit mask. */ -#define TC2_HCMPA_bp 4 /* High Byte Compare A Output Value bit position. */ - -#define TC2_LCMPD_bm 0x08 /* Low Byte Compare D Output Value bit mask. */ -#define TC2_LCMPD_bp 3 /* Low Byte Compare D Output Value bit position. */ - -#define TC2_LCMPC_bm 0x04 /* Low Byte Compare C Output Value bit mask. */ -#define TC2_LCMPC_bp 2 /* Low Byte Compare C Output Value bit position. */ - -#define TC2_LCMPB_bm 0x02 /* Low Byte Compare B Output Value bit mask. */ -#define TC2_LCMPB_bp 1 /* Low Byte Compare B Output Value bit position. */ - -#define TC2_LCMPA_bm 0x01 /* Low Byte Compare A Output Value bit mask. */ -#define TC2_LCMPA_bp 0 /* Low Byte Compare A Output Value bit position. */ - -/* TC2.CTRLE bit masks and bit positions */ -#define TC2_BYTEM_gm 0x03 /* Byte Mode group mask. */ -#define TC2_BYTEM_gp 0 /* Byte Mode group position. */ -#define TC2_BYTEM0_bm (1<<0) /* Byte Mode bit 0 mask. */ -#define TC2_BYTEM0_bp 0 /* Byte Mode bit 0 position. */ -#define TC2_BYTEM1_bm (1<<1) /* Byte Mode bit 1 mask. */ -#define TC2_BYTEM1_bp 1 /* Byte Mode bit 1 position. */ - -/* TC2.INTCTRLA bit masks and bit positions */ -#define TC2_HUNFINTLVL_gm 0x0C /* High Byte Underflow Interrupt Level group mask. */ -#define TC2_HUNFINTLVL_gp 2 /* High Byte Underflow Interrupt Level group position. */ -#define TC2_HUNFINTLVL0_bm (1<<2) /* High Byte Underflow Interrupt Level bit 0 mask. */ -#define TC2_HUNFINTLVL0_bp 2 /* High Byte Underflow Interrupt Level bit 0 position. */ -#define TC2_HUNFINTLVL1_bm (1<<3) /* High Byte Underflow Interrupt Level bit 1 mask. */ -#define TC2_HUNFINTLVL1_bp 3 /* High Byte Underflow Interrupt Level bit 1 position. */ - -#define TC2_LUNFINTLVL_gm 0x03 /* Low Byte Underflow interrupt level group mask. */ -#define TC2_LUNFINTLVL_gp 0 /* Low Byte Underflow interrupt level group position. */ -#define TC2_LUNFINTLVL0_bm (1<<0) /* Low Byte Underflow interrupt level bit 0 mask. */ -#define TC2_LUNFINTLVL0_bp 0 /* Low Byte Underflow interrupt level bit 0 position. */ -#define TC2_LUNFINTLVL1_bm (1<<1) /* Low Byte Underflow interrupt level bit 1 mask. */ -#define TC2_LUNFINTLVL1_bp 1 /* Low Byte Underflow interrupt level bit 1 position. */ - -/* TC2.INTCTRLB bit masks and bit positions */ -#define TC2_LCMPDINTLVL_gm 0xC0 /* Low Byte Compare D Interrupt Level group mask. */ -#define TC2_LCMPDINTLVL_gp 6 /* Low Byte Compare D Interrupt Level group position. */ -#define TC2_LCMPDINTLVL0_bm (1<<6) /* Low Byte Compare D Interrupt Level bit 0 mask. */ -#define TC2_LCMPDINTLVL0_bp 6 /* Low Byte Compare D Interrupt Level bit 0 position. */ -#define TC2_LCMPDINTLVL1_bm (1<<7) /* Low Byte Compare D Interrupt Level bit 1 mask. */ -#define TC2_LCMPDINTLVL1_bp 7 /* Low Byte Compare D Interrupt Level bit 1 position. */ - -#define TC2_LCMPCINTLVL_gm 0x30 /* Low Byte Compare C Interrupt Level group mask. */ -#define TC2_LCMPCINTLVL_gp 4 /* Low Byte Compare C Interrupt Level group position. */ -#define TC2_LCMPCINTLVL0_bm (1<<4) /* Low Byte Compare C Interrupt Level bit 0 mask. */ -#define TC2_LCMPCINTLVL0_bp 4 /* Low Byte Compare C Interrupt Level bit 0 position. */ -#define TC2_LCMPCINTLVL1_bm (1<<5) /* Low Byte Compare C Interrupt Level bit 1 mask. */ -#define TC2_LCMPCINTLVL1_bp 5 /* Low Byte Compare C Interrupt Level bit 1 position. */ - -#define TC2_LCMPBINTLVL_gm 0x0C /* Low Byte Compare B Interrupt Level group mask. */ -#define TC2_LCMPBINTLVL_gp 2 /* Low Byte Compare B Interrupt Level group position. */ -#define TC2_LCMPBINTLVL0_bm (1<<2) /* Low Byte Compare B Interrupt Level bit 0 mask. */ -#define TC2_LCMPBINTLVL0_bp 2 /* Low Byte Compare B Interrupt Level bit 0 position. */ -#define TC2_LCMPBINTLVL1_bm (1<<3) /* Low Byte Compare B Interrupt Level bit 1 mask. */ -#define TC2_LCMPBINTLVL1_bp 3 /* Low Byte Compare B Interrupt Level bit 1 position. */ - -#define TC2_LCMPAINTLVL_gm 0x03 /* Low Byte Compare A Interrupt Level group mask. */ -#define TC2_LCMPAINTLVL_gp 0 /* Low Byte Compare A Interrupt Level group position. */ -#define TC2_LCMPAINTLVL0_bm (1<<0) /* Low Byte Compare A Interrupt Level bit 0 mask. */ -#define TC2_LCMPAINTLVL0_bp 0 /* Low Byte Compare A Interrupt Level bit 0 position. */ -#define TC2_LCMPAINTLVL1_bm (1<<1) /* Low Byte Compare A Interrupt Level bit 1 mask. */ -#define TC2_LCMPAINTLVL1_bp 1 /* Low Byte Compare A Interrupt Level bit 1 position. */ - -/* TC2.CTRLF bit masks and bit positions */ -#define TC2_CMD_gm 0x0C /* Command group mask. */ -#define TC2_CMD_gp 2 /* Command group position. */ -#define TC2_CMD0_bm (1<<2) /* Command bit 0 mask. */ -#define TC2_CMD0_bp 2 /* Command bit 0 position. */ -#define TC2_CMD1_bm (1<<3) /* Command bit 1 mask. */ -#define TC2_CMD1_bp 3 /* Command bit 1 position. */ - -#define TC2_CMDEN_gm 0x03 /* Command Enable group mask. */ -#define TC2_CMDEN_gp 0 /* Command Enable group position. */ -#define TC2_CMDEN0_bm (1<<0) /* Command Enable bit 0 mask. */ -#define TC2_CMDEN0_bp 0 /* Command Enable bit 0 position. */ -#define TC2_CMDEN1_bm (1<<1) /* Command Enable bit 1 mask. */ -#define TC2_CMDEN1_bp 1 /* Command Enable bit 1 position. */ - -/* TC2.INTFLAGS bit masks and bit positions */ -#define TC2_LCMPDIF_bm 0x80 /* Low Byte Compare D Interrupt Flag bit mask. */ -#define TC2_LCMPDIF_bp 7 /* Low Byte Compare D Interrupt Flag bit position. */ - -#define TC2_LCMPCIF_bm 0x40 /* Low Byte Compare C Interrupt Flag bit mask. */ -#define TC2_LCMPCIF_bp 6 /* Low Byte Compare C Interrupt Flag bit position. */ - -#define TC2_LCMPBIF_bm 0x20 /* Low Byte Compare B Interrupt Flag bit mask. */ -#define TC2_LCMPBIF_bp 5 /* Low Byte Compare B Interrupt Flag bit position. */ - -#define TC2_LCMPAIF_bm 0x10 /* Low Byte Compare A Interrupt Flag bit mask. */ -#define TC2_LCMPAIF_bp 4 /* Low Byte Compare A Interrupt Flag bit position. */ - -#define TC2_HUNFIF_bm 0x02 /* High Byte Underflow Interrupt Flag bit mask. */ -#define TC2_HUNFIF_bp 1 /* High Byte Underflow Interrupt Flag bit position. */ - -#define TC2_LUNFIF_bm 0x01 /* Low Byte Underflow Interrupt Flag bit mask. */ -#define TC2_LUNFIF_bp 0 /* Low Byte Underflow Interrupt Flag bit position. */ - -/* AWEX - Timer/Counter Advanced Waveform Extension */ -/* AWEX.CTRL bit masks and bit positions */ -#define AWEX_PGM_bm 0x20 /* Pattern Generation Mode bit mask. */ -#define AWEX_PGM_bp 5 /* Pattern Generation Mode bit position. */ - -#define AWEX_CWCM_bm 0x10 /* Common Waveform Channel Mode bit mask. */ -#define AWEX_CWCM_bp 4 /* Common Waveform Channel Mode bit position. */ - -#define AWEX_DTICCDEN_bm 0x08 /* Dead Time Insertion Compare Channel D Enable bit mask. */ -#define AWEX_DTICCDEN_bp 3 /* Dead Time Insertion Compare Channel D Enable bit position. */ - -#define AWEX_DTICCCEN_bm 0x04 /* Dead Time Insertion Compare Channel C Enable bit mask. */ -#define AWEX_DTICCCEN_bp 2 /* Dead Time Insertion Compare Channel C Enable bit position. */ - -#define AWEX_DTICCBEN_bm 0x02 /* Dead Time Insertion Compare Channel B Enable bit mask. */ -#define AWEX_DTICCBEN_bp 1 /* Dead Time Insertion Compare Channel B Enable bit position. */ - -#define AWEX_DTICCAEN_bm 0x01 /* Dead Time Insertion Compare Channel A Enable bit mask. */ -#define AWEX_DTICCAEN_bp 0 /* Dead Time Insertion Compare Channel A Enable bit position. */ - -/* AWEX.FDCTRL bit masks and bit positions */ -#define AWEX_FDDBD_bm 0x10 /* Fault Detect on Disable Break Disable bit mask. */ -#define AWEX_FDDBD_bp 4 /* Fault Detect on Disable Break Disable bit position. */ - -#define AWEX_FDMODE_bm 0x04 /* Fault Detect Mode bit mask. */ -#define AWEX_FDMODE_bp 2 /* Fault Detect Mode bit position. */ - -#define AWEX_FDACT_gm 0x03 /* Fault Detect Action group mask. */ -#define AWEX_FDACT_gp 0 /* Fault Detect Action group position. */ -#define AWEX_FDACT0_bm (1<<0) /* Fault Detect Action bit 0 mask. */ -#define AWEX_FDACT0_bp 0 /* Fault Detect Action bit 0 position. */ -#define AWEX_FDACT1_bm (1<<1) /* Fault Detect Action bit 1 mask. */ -#define AWEX_FDACT1_bp 1 /* Fault Detect Action bit 1 position. */ - -/* AWEX.STATUS bit masks and bit positions */ -#define AWEX_FDF_bm 0x04 /* Fault Detect Flag bit mask. */ -#define AWEX_FDF_bp 2 /* Fault Detect Flag bit position. */ - -#define AWEX_DTHSBUFV_bm 0x02 /* Dead Time High Side Buffer Valid bit mask. */ -#define AWEX_DTHSBUFV_bp 1 /* Dead Time High Side Buffer Valid bit position. */ - -#define AWEX_DTLSBUFV_bm 0x01 /* Dead Time Low Side Buffer Valid bit mask. */ -#define AWEX_DTLSBUFV_bp 0 /* Dead Time Low Side Buffer Valid bit position. */ - -/* AWEX.STATUSSET bit masks and bit positions */ -/* AWEX_FDF Predefined. */ -/* AWEX_FDF Predefined. */ - -/* AWEX_DTHSBUFV Predefined. */ -/* AWEX_DTHSBUFV Predefined. */ - -/* AWEX_DTLSBUFV Predefined. */ -/* AWEX_DTLSBUFV Predefined. */ - -/* HIRES - Timer/Counter High-Resolution Extension */ -/* HIRES.CTRLA bit masks and bit positions */ -#define HIRES_HREN_gm 0x03 /* High Resolution Enable group mask. */ -#define HIRES_HREN_gp 0 /* High Resolution Enable group position. */ -#define HIRES_HREN0_bm (1<<0) /* High Resolution Enable bit 0 mask. */ -#define HIRES_HREN0_bp 0 /* High Resolution Enable bit 0 position. */ -#define HIRES_HREN1_bm (1<<1) /* High Resolution Enable bit 1 mask. */ -#define HIRES_HREN1_bp 1 /* High Resolution Enable bit 1 position. */ - -/* USART - Universal Asynchronous Receiver-Transmitter */ -/* USART.STATUS bit masks and bit positions */ -#define USART_RXCIF_bm 0x80 /* Receive Interrupt Flag bit mask. */ -#define USART_RXCIF_bp 7 /* Receive Interrupt Flag bit position. */ - -#define USART_TXCIF_bm 0x40 /* Transmit Interrupt Flag bit mask. */ -#define USART_TXCIF_bp 6 /* Transmit Interrupt Flag bit position. */ - -#define USART_DREIF_bm 0x20 /* Data Register Empty Flag bit mask. */ -#define USART_DREIF_bp 5 /* Data Register Empty Flag bit position. */ - -#define USART_FERR_bm 0x10 /* Frame Error bit mask. */ -#define USART_FERR_bp 4 /* Frame Error bit position. */ - -#define USART_BUFOVF_bm 0x08 /* Buffer Overflow bit mask. */ -#define USART_BUFOVF_bp 3 /* Buffer Overflow bit position. */ - -#define USART_PERR_bm 0x04 /* Parity Error bit mask. */ -#define USART_PERR_bp 2 /* Parity Error bit position. */ - -#define USART_RXB8_bm 0x01 /* Receive Bit 8 bit mask. */ -#define USART_RXB8_bp 0 /* Receive Bit 8 bit position. */ - -/* USART.CTRLA bit masks and bit positions */ -#define USART_RXCINTLVL_gm 0x30 /* Receive Interrupt Level group mask. */ -#define USART_RXCINTLVL_gp 4 /* Receive Interrupt Level group position. */ -#define USART_RXCINTLVL0_bm (1<<4) /* Receive Interrupt Level bit 0 mask. */ -#define USART_RXCINTLVL0_bp 4 /* Receive Interrupt Level bit 0 position. */ -#define USART_RXCINTLVL1_bm (1<<5) /* Receive Interrupt Level bit 1 mask. */ -#define USART_RXCINTLVL1_bp 5 /* Receive Interrupt Level bit 1 position. */ - -#define USART_TXCINTLVL_gm 0x0C /* Transmit Interrupt Level group mask. */ -#define USART_TXCINTLVL_gp 2 /* Transmit Interrupt Level group position. */ -#define USART_TXCINTLVL0_bm (1<<2) /* Transmit Interrupt Level bit 0 mask. */ -#define USART_TXCINTLVL0_bp 2 /* Transmit Interrupt Level bit 0 position. */ -#define USART_TXCINTLVL1_bm (1<<3) /* Transmit Interrupt Level bit 1 mask. */ -#define USART_TXCINTLVL1_bp 3 /* Transmit Interrupt Level bit 1 position. */ - -#define USART_DREINTLVL_gm 0x03 /* Data Register Empty Interrupt Level group mask. */ -#define USART_DREINTLVL_gp 0 /* Data Register Empty Interrupt Level group position. */ -#define USART_DREINTLVL0_bm (1<<0) /* Data Register Empty Interrupt Level bit 0 mask. */ -#define USART_DREINTLVL0_bp 0 /* Data Register Empty Interrupt Level bit 0 position. */ -#define USART_DREINTLVL1_bm (1<<1) /* Data Register Empty Interrupt Level bit 1 mask. */ -#define USART_DREINTLVL1_bp 1 /* Data Register Empty Interrupt Level bit 1 position. */ - -/* USART.CTRLB bit masks and bit positions */ -#define USART_RXEN_bm 0x10 /* Receiver Enable bit mask. */ -#define USART_RXEN_bp 4 /* Receiver Enable bit position. */ - -#define USART_TXEN_bm 0x08 /* Transmitter Enable bit mask. */ -#define USART_TXEN_bp 3 /* Transmitter Enable bit position. */ - -#define USART_CLK2X_bm 0x04 /* Double transmission speed bit mask. */ -#define USART_CLK2X_bp 2 /* Double transmission speed bit position. */ - -#define USART_MPCM_bm 0x02 /* Multi-processor Communication Mode bit mask. */ -#define USART_MPCM_bp 1 /* Multi-processor Communication Mode bit position. */ - -#define USART_TXB8_bm 0x01 /* Transmit bit 8 bit mask. */ -#define USART_TXB8_bp 0 /* Transmit bit 8 bit position. */ - -/* USART.CTRLC bit masks and bit positions */ -#define USART_CMODE_gm 0xC0 /* Communication Mode group mask. */ -#define USART_CMODE_gp 6 /* Communication Mode group position. */ -#define USART_CMODE0_bm (1<<6) /* Communication Mode bit 0 mask. */ -#define USART_CMODE0_bp 6 /* Communication Mode bit 0 position. */ -#define USART_CMODE1_bm (1<<7) /* Communication Mode bit 1 mask. */ -#define USART_CMODE1_bp 7 /* Communication Mode bit 1 position. */ - -#define USART_PMODE_gm 0x30 /* Parity Mode group mask. */ -#define USART_PMODE_gp 4 /* Parity Mode group position. */ -#define USART_PMODE0_bm (1<<4) /* Parity Mode bit 0 mask. */ -#define USART_PMODE0_bp 4 /* Parity Mode bit 0 position. */ -#define USART_PMODE1_bm (1<<5) /* Parity Mode bit 1 mask. */ -#define USART_PMODE1_bp 5 /* Parity Mode bit 1 position. */ - -#define USART_SBMODE_bm 0x08 /* Stop Bit Mode bit mask. */ -#define USART_SBMODE_bp 3 /* Stop Bit Mode bit position. */ - -#define USART_CHSIZE_gm 0x07 /* Character Size group mask. */ -#define USART_CHSIZE_gp 0 /* Character Size group position. */ -#define USART_CHSIZE0_bm (1<<0) /* Character Size bit 0 mask. */ -#define USART_CHSIZE0_bp 0 /* Character Size bit 0 position. */ -#define USART_CHSIZE1_bm (1<<1) /* Character Size bit 1 mask. */ -#define USART_CHSIZE1_bp 1 /* Character Size bit 1 position. */ -#define USART_CHSIZE2_bm (1<<2) /* Character Size bit 2 mask. */ -#define USART_CHSIZE2_bp 2 /* Character Size bit 2 position. */ - -/* USART.BAUDCTRLA bit masks and bit positions */ -#define USART_BSEL_gm 0xFF /* Baud Rate Selection Bits [7:0] group mask. */ -#define USART_BSEL_gp 0 /* Baud Rate Selection Bits [7:0] group position. */ -#define USART_BSEL0_bm (1<<0) /* Baud Rate Selection Bits [7:0] bit 0 mask. */ -#define USART_BSEL0_bp 0 /* Baud Rate Selection Bits [7:0] bit 0 position. */ -#define USART_BSEL1_bm (1<<1) /* Baud Rate Selection Bits [7:0] bit 1 mask. */ -#define USART_BSEL1_bp 1 /* Baud Rate Selection Bits [7:0] bit 1 position. */ -#define USART_BSEL2_bm (1<<2) /* Baud Rate Selection Bits [7:0] bit 2 mask. */ -#define USART_BSEL2_bp 2 /* Baud Rate Selection Bits [7:0] bit 2 position. */ -#define USART_BSEL3_bm (1<<3) /* Baud Rate Selection Bits [7:0] bit 3 mask. */ -#define USART_BSEL3_bp 3 /* Baud Rate Selection Bits [7:0] bit 3 position. */ -#define USART_BSEL4_bm (1<<4) /* Baud Rate Selection Bits [7:0] bit 4 mask. */ -#define USART_BSEL4_bp 4 /* Baud Rate Selection Bits [7:0] bit 4 position. */ -#define USART_BSEL5_bm (1<<5) /* Baud Rate Selection Bits [7:0] bit 5 mask. */ -#define USART_BSEL5_bp 5 /* Baud Rate Selection Bits [7:0] bit 5 position. */ -#define USART_BSEL6_bm (1<<6) /* Baud Rate Selection Bits [7:0] bit 6 mask. */ -#define USART_BSEL6_bp 6 /* Baud Rate Selection Bits [7:0] bit 6 position. */ -#define USART_BSEL7_bm (1<<7) /* Baud Rate Selection Bits [7:0] bit 7 mask. */ -#define USART_BSEL7_bp 7 /* Baud Rate Selection Bits [7:0] bit 7 position. */ - -/* USART.BAUDCTRLB bit masks and bit positions */ -#define USART_BSCALE_gm 0xF0 /* Baud Rate Scale group mask. */ -#define USART_BSCALE_gp 4 /* Baud Rate Scale group position. */ -#define USART_BSCALE0_bm (1<<4) /* Baud Rate Scale bit 0 mask. */ -#define USART_BSCALE0_bp 4 /* Baud Rate Scale bit 0 position. */ -#define USART_BSCALE1_bm (1<<5) /* Baud Rate Scale bit 1 mask. */ -#define USART_BSCALE1_bp 5 /* Baud Rate Scale bit 1 position. */ -#define USART_BSCALE2_bm (1<<6) /* Baud Rate Scale bit 2 mask. */ -#define USART_BSCALE2_bp 6 /* Baud Rate Scale bit 2 position. */ -#define USART_BSCALE3_bm (1<<7) /* Baud Rate Scale bit 3 mask. */ -#define USART_BSCALE3_bp 7 /* Baud Rate Scale bit 3 position. */ - -/* USART_BSEL Predefined. */ -/* USART_BSEL Predefined. */ - -/* SPI - Serial Peripheral Interface */ -/* SPI.CTRL bit masks and bit positions */ -#define SPI_CLK2X_bm 0x80 /* Enable Double Speed bit mask. */ -#define SPI_CLK2X_bp 7 /* Enable Double Speed bit position. */ - -#define SPI_ENABLE_bm 0x40 /* Enable Module bit mask. */ -#define SPI_ENABLE_bp 6 /* Enable Module bit position. */ - -#define SPI_DORD_bm 0x20 /* Data Order Setting bit mask. */ -#define SPI_DORD_bp 5 /* Data Order Setting bit position. */ - -#define SPI_MASTER_bm 0x10 /* Master Operation Enable bit mask. */ -#define SPI_MASTER_bp 4 /* Master Operation Enable bit position. */ - -#define SPI_MODE_gm 0x0C /* SPI Mode group mask. */ -#define SPI_MODE_gp 2 /* SPI Mode group position. */ -#define SPI_MODE0_bm (1<<2) /* SPI Mode bit 0 mask. */ -#define SPI_MODE0_bp 2 /* SPI Mode bit 0 position. */ -#define SPI_MODE1_bm (1<<3) /* SPI Mode bit 1 mask. */ -#define SPI_MODE1_bp 3 /* SPI Mode bit 1 position. */ - -#define SPI_PRESCALER_gm 0x03 /* Prescaler group mask. */ -#define SPI_PRESCALER_gp 0 /* Prescaler group position. */ -#define SPI_PRESCALER0_bm (1<<0) /* Prescaler bit 0 mask. */ -#define SPI_PRESCALER0_bp 0 /* Prescaler bit 0 position. */ -#define SPI_PRESCALER1_bm (1<<1) /* Prescaler bit 1 mask. */ -#define SPI_PRESCALER1_bp 1 /* Prescaler bit 1 position. */ - -/* SPI.INTCTRL bit masks and bit positions */ -#define SPI_INTLVL_gm 0x03 /* Interrupt level group mask. */ -#define SPI_INTLVL_gp 0 /* Interrupt level group position. */ -#define SPI_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */ -#define SPI_INTLVL0_bp 0 /* Interrupt level bit 0 position. */ -#define SPI_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */ -#define SPI_INTLVL1_bp 1 /* Interrupt level bit 1 position. */ - -/* SPI.STATUS bit masks and bit positions */ -#define SPI_IF_bm 0x80 /* Interrupt Flag bit mask. */ -#define SPI_IF_bp 7 /* Interrupt Flag bit position. */ - -#define SPI_WRCOL_bm 0x40 /* Write Collision bit mask. */ -#define SPI_WRCOL_bp 6 /* Write Collision bit position. */ - -/* IRCOM - IR Communication Module */ -/* IRCOM.CTRL bit masks and bit positions */ -#define IRCOM_EVSEL_gm 0x0F /* Event Channel Select group mask. */ -#define IRCOM_EVSEL_gp 0 /* Event Channel Select group position. */ -#define IRCOM_EVSEL0_bm (1<<0) /* Event Channel Select bit 0 mask. */ -#define IRCOM_EVSEL0_bp 0 /* Event Channel Select bit 0 position. */ -#define IRCOM_EVSEL1_bm (1<<1) /* Event Channel Select bit 1 mask. */ -#define IRCOM_EVSEL1_bp 1 /* Event Channel Select bit 1 position. */ -#define IRCOM_EVSEL2_bm (1<<2) /* Event Channel Select bit 2 mask. */ -#define IRCOM_EVSEL2_bp 2 /* Event Channel Select bit 2 position. */ -#define IRCOM_EVSEL3_bm (1<<3) /* Event Channel Select bit 3 mask. */ -#define IRCOM_EVSEL3_bp 3 /* Event Channel Select bit 3 position. */ - -/* FUSE - Fuses and Lockbits */ -/* NVM_FUSES.FUSEBYTE1 bit masks and bit positions */ -#define NVM_FUSES_WDWP_gm 0xF0 /* Watchdog Window Timeout Period group mask. */ -#define NVM_FUSES_WDWP_gp 4 /* Watchdog Window Timeout Period group position. */ -#define NVM_FUSES_WDWP0_bm (1<<4) /* Watchdog Window Timeout Period bit 0 mask. */ -#define NVM_FUSES_WDWP0_bp 4 /* Watchdog Window Timeout Period bit 0 position. */ -#define NVM_FUSES_WDWP1_bm (1<<5) /* Watchdog Window Timeout Period bit 1 mask. */ -#define NVM_FUSES_WDWP1_bp 5 /* Watchdog Window Timeout Period bit 1 position. */ -#define NVM_FUSES_WDWP2_bm (1<<6) /* Watchdog Window Timeout Period bit 2 mask. */ -#define NVM_FUSES_WDWP2_bp 6 /* Watchdog Window Timeout Period bit 2 position. */ -#define NVM_FUSES_WDWP3_bm (1<<7) /* Watchdog Window Timeout Period bit 3 mask. */ -#define NVM_FUSES_WDWP3_bp 7 /* Watchdog Window Timeout Period bit 3 position. */ - -#define NVM_FUSES_WDP_gm 0x0F /* Watchdog Timeout Period group mask. */ -#define NVM_FUSES_WDP_gp 0 /* Watchdog Timeout Period group position. */ -#define NVM_FUSES_WDP0_bm (1<<0) /* Watchdog Timeout Period bit 0 mask. */ -#define NVM_FUSES_WDP0_bp 0 /* Watchdog Timeout Period bit 0 position. */ -#define NVM_FUSES_WDP1_bm (1<<1) /* Watchdog Timeout Period bit 1 mask. */ -#define NVM_FUSES_WDP1_bp 1 /* Watchdog Timeout Period bit 1 position. */ -#define NVM_FUSES_WDP2_bm (1<<2) /* Watchdog Timeout Period bit 2 mask. */ -#define NVM_FUSES_WDP2_bp 2 /* Watchdog Timeout Period bit 2 position. */ -#define NVM_FUSES_WDP3_bm (1<<3) /* Watchdog Timeout Period bit 3 mask. */ -#define NVM_FUSES_WDP3_bp 3 /* Watchdog Timeout Period bit 3 position. */ - -/* NVM_FUSES.FUSEBYTE2 bit masks and bit positions */ -#define NVM_FUSES_BOOTRST_bm 0x40 /* Boot Loader Section Reset Vector bit mask. */ -#define NVM_FUSES_BOOTRST_bp 6 /* Boot Loader Section Reset Vector bit position. */ - -#define NVM_FUSES_TOSCSEL_bm 0x20 /* Timer Oscillator pin location bit mask. */ -#define NVM_FUSES_TOSCSEL_bp 5 /* Timer Oscillator pin location bit position. */ - -#define NVM_FUSES_BODPD_gm 0x03 /* BOD Operation in Power-Down Mode group mask. */ -#define NVM_FUSES_BODPD_gp 0 /* BOD Operation in Power-Down Mode group position. */ -#define NVM_FUSES_BODPD0_bm (1<<0) /* BOD Operation in Power-Down Mode bit 0 mask. */ -#define NVM_FUSES_BODPD0_bp 0 /* BOD Operation in Power-Down Mode bit 0 position. */ -#define NVM_FUSES_BODPD1_bm (1<<1) /* BOD Operation in Power-Down Mode bit 1 mask. */ -#define NVM_FUSES_BODPD1_bp 1 /* BOD Operation in Power-Down Mode bit 1 position. */ - -/* NVM_FUSES.FUSEBYTE4 bit masks and bit positions */ -#define NVM_FUSES_RSTDISBL_bm 0x10 /* External Reset Disable bit mask. */ -#define NVM_FUSES_RSTDISBL_bp 4 /* External Reset Disable bit position. */ - -#define NVM_FUSES_SUT_gm 0x0C /* Start-up Time group mask. */ -#define NVM_FUSES_SUT_gp 2 /* Start-up Time group position. */ -#define NVM_FUSES_SUT0_bm (1<<2) /* Start-up Time bit 0 mask. */ -#define NVM_FUSES_SUT0_bp 2 /* Start-up Time bit 0 position. */ -#define NVM_FUSES_SUT1_bm (1<<3) /* Start-up Time bit 1 mask. */ -#define NVM_FUSES_SUT1_bp 3 /* Start-up Time bit 1 position. */ - -#define NVM_FUSES_WDLOCK_bm 0x02 /* Watchdog Timer Lock bit mask. */ -#define NVM_FUSES_WDLOCK_bp 1 /* Watchdog Timer Lock bit position. */ - -/* NVM_FUSES.FUSEBYTE5 bit masks and bit positions */ -#define NVM_FUSES_BODACT_gm 0x30 /* BOD Operation in Active Mode group mask. */ -#define NVM_FUSES_BODACT_gp 4 /* BOD Operation in Active Mode group position. */ -#define NVM_FUSES_BODACT0_bm (1<<4) /* BOD Operation in Active Mode bit 0 mask. */ -#define NVM_FUSES_BODACT0_bp 4 /* BOD Operation in Active Mode bit 0 position. */ -#define NVM_FUSES_BODACT1_bm (1<<5) /* BOD Operation in Active Mode bit 1 mask. */ -#define NVM_FUSES_BODACT1_bp 5 /* BOD Operation in Active Mode bit 1 position. */ - -#define NVM_FUSES_EESAVE_bm 0x08 /* Preserve EEPROM Through Chip Erase bit mask. */ -#define NVM_FUSES_EESAVE_bp 3 /* Preserve EEPROM Through Chip Erase bit position. */ - -#define NVM_FUSES_BODLVL_gm 0x07 /* Brownout Detection Voltage Level group mask. */ -#define NVM_FUSES_BODLVL_gp 0 /* Brownout Detection Voltage Level group position. */ -#define NVM_FUSES_BODLVL0_bm (1<<0) /* Brownout Detection Voltage Level bit 0 mask. */ -#define NVM_FUSES_BODLVL0_bp 0 /* Brownout Detection Voltage Level bit 0 position. */ -#define NVM_FUSES_BODLVL1_bm (1<<1) /* Brownout Detection Voltage Level bit 1 mask. */ -#define NVM_FUSES_BODLVL1_bp 1 /* Brownout Detection Voltage Level bit 1 position. */ -#define NVM_FUSES_BODLVL2_bm (1<<2) /* Brownout Detection Voltage Level bit 2 mask. */ -#define NVM_FUSES_BODLVL2_bp 2 /* Brownout Detection Voltage Level bit 2 position. */ - -/* LOCKBIT - Fuses and Lockbits */ -/* NVM_LOCKBITS.LOCKBITS bit masks and bit positions */ -#define NVM_LOCKBITS_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ -#define NVM_LOCKBITS_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ -#define NVM_LOCKBITS_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ -#define NVM_LOCKBITS_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ -#define NVM_LOCKBITS_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ -#define NVM_LOCKBITS_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ - -#define NVM_LOCKBITS_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ -#define NVM_LOCKBITS_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ -#define NVM_LOCKBITS_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ -#define NVM_LOCKBITS_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ -#define NVM_LOCKBITS_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ -#define NVM_LOCKBITS_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ - -#define NVM_LOCKBITS_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ -#define NVM_LOCKBITS_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ -#define NVM_LOCKBITS_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ -#define NVM_LOCKBITS_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ -#define NVM_LOCKBITS_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ -#define NVM_LOCKBITS_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ - -#define NVM_LOCKBITS_LB_gm 0x03 /* Lock Bits group mask. */ -#define NVM_LOCKBITS_LB_gp 0 /* Lock Bits group position. */ -#define NVM_LOCKBITS_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ -#define NVM_LOCKBITS_LB0_bp 0 /* Lock Bits bit 0 position. */ -#define NVM_LOCKBITS_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ -#define NVM_LOCKBITS_LB1_bp 1 /* Lock Bits bit 1 position. */ - - - -// Generic Port Pins - -#define PIN0_bm 0x01 -#define PIN0_bp 0 -#define PIN1_bm 0x02 -#define PIN1_bp 1 -#define PIN2_bm 0x04 -#define PIN2_bp 2 -#define PIN3_bm 0x08 -#define PIN3_bp 3 -#define PIN4_bm 0x10 -#define PIN4_bp 4 -#define PIN5_bm 0x20 -#define PIN5_bp 5 -#define PIN6_bm 0x40 -#define PIN6_bp 6 -#define PIN7_bm 0x80 -#define PIN7_bp 7 - -/* ========== Interrupt Vector Definitions ========== */ -/* Vector 0 is the reset vector */ - -/* OSC interrupt vectors */ -#define OSC_OSCF_vect_num 1 -#define OSC_OSCF_vect _VECTOR(1) /* Oscillator Failure Interrupt (NMI) */ - -/* PORTC interrupt vectors */ -#define PORTC_INT0_vect_num 2 -#define PORTC_INT0_vect _VECTOR(2) /* External Interrupt 0 */ -#define PORTC_INT1_vect_num 3 -#define PORTC_INT1_vect _VECTOR(3) /* External Interrupt 1 */ - -/* PORTR interrupt vectors */ -#define PORTR_INT0_vect_num 4 -#define PORTR_INT0_vect _VECTOR(4) /* External Interrupt 0 */ -#define PORTR_INT1_vect_num 5 -#define PORTR_INT1_vect _VECTOR(5) /* External Interrupt 1 */ - -/* RTC interrupt vectors */ -#define RTC_OVF_vect_num 10 -#define RTC_OVF_vect _VECTOR(10) /* Overflow Interrupt */ -#define RTC_COMP_vect_num 11 -#define RTC_COMP_vect _VECTOR(11) /* Compare Interrupt */ - -/* TWIC interrupt vectors */ -#define TWIC_TWIS_vect_num 12 -#define TWIC_TWIS_vect _VECTOR(12) /* TWI Slave Interrupt */ -#define TWIC_TWIM_vect_num 13 -#define TWIC_TWIM_vect _VECTOR(13) /* TWI Master Interrupt */ - -/* TCC0 interrupt vectors */ -#define TCC0_OVF_vect_num 14 -#define TCC0_OVF_vect _VECTOR(14) /* Overflow Interrupt */ - -/* TCC2 interrupt vectors */ -#define TCC2_LUNF_vect_num 14 -#define TCC2_LUNF_vect _VECTOR(14) /* Low Byte Underflow Interrupt */ - -/* TCC0 interrupt vectors */ -#define TCC0_ERR_vect_num 15 -#define TCC0_ERR_vect _VECTOR(15) /* Error Interrupt */ - -/* TCC2 interrupt vectors */ -#define TCC2_HUNF_vect_num 15 -#define TCC2_HUNF_vect _VECTOR(15) /* High Byte Underflow Interrupt */ - -/* TCC0 interrupt vectors */ -#define TCC0_CCA_vect_num 16 -#define TCC0_CCA_vect _VECTOR(16) /* Compare or Capture A Interrupt */ - -/* TCC2 interrupt vectors */ -#define TCC2_LCMPA_vect_num 16 -#define TCC2_LCMPA_vect _VECTOR(16) /* Low Byte Compare A Interrupt */ - -/* TCC0 interrupt vectors */ -#define TCC0_CCB_vect_num 17 -#define TCC0_CCB_vect _VECTOR(17) /* Compare or Capture B Interrupt */ - -/* TCC2 interrupt vectors */ -#define TCC2_LCMPB_vect_num 17 -#define TCC2_LCMPB_vect _VECTOR(17) /* Low Byte Compare B Interrupt */ - -/* TCC0 interrupt vectors */ -#define TCC0_CCC_vect_num 18 -#define TCC0_CCC_vect _VECTOR(18) /* Compare or Capture C Interrupt */ - -/* TCC2 interrupt vectors */ -#define TCC2_LCMPC_vect_num 18 -#define TCC2_LCMPC_vect _VECTOR(18) /* Low Byte Compare C Interrupt */ - -/* TCC0 interrupt vectors */ -#define TCC0_CCD_vect_num 19 -#define TCC0_CCD_vect _VECTOR(19) /* Compare or Capture D Interrupt */ - -/* TCC2 interrupt vectors */ -#define TCC2_LCMPD_vect_num 19 -#define TCC2_LCMPD_vect _VECTOR(19) /* Low Byte Compare D Interrupt */ - -/* TCC1 interrupt vectors */ -#define TCC1_OVF_vect_num 20 -#define TCC1_OVF_vect _VECTOR(20) /* Overflow Interrupt */ -#define TCC1_ERR_vect_num 21 -#define TCC1_ERR_vect _VECTOR(21) /* Error Interrupt */ -#define TCC1_CCA_vect_num 22 -#define TCC1_CCA_vect _VECTOR(22) /* Compare or Capture A Interrupt */ -#define TCC1_CCB_vect_num 23 -#define TCC1_CCB_vect _VECTOR(23) /* Compare or Capture B Interrupt */ - -/* SPIC interrupt vectors */ -#define SPIC_INT_vect_num 24 -#define SPIC_INT_vect _VECTOR(24) /* SPI Interrupt */ - -/* USARTC0 interrupt vectors */ -#define USARTC0_RXC_vect_num 25 -#define USARTC0_RXC_vect _VECTOR(25) /* Reception Complete Interrupt */ -#define USARTC0_DRE_vect_num 26 -#define USARTC0_DRE_vect _VECTOR(26) /* Data Register Empty Interrupt */ -#define USARTC0_TXC_vect_num 27 -#define USARTC0_TXC_vect _VECTOR(27) /* Transmission Complete Interrupt */ - -/* NVM interrupt vectors */ -#define NVM_EE_vect_num 32 -#define NVM_EE_vect _VECTOR(32) /* EE Interrupt */ -#define NVM_SPM_vect_num 33 -#define NVM_SPM_vect _VECTOR(33) /* SPM Interrupt */ - -/* PORTB interrupt vectors */ -#define PORTB_INT0_vect_num 34 -#define PORTB_INT0_vect _VECTOR(34) /* External Interrupt 0 */ -#define PORTB_INT1_vect_num 35 -#define PORTB_INT1_vect _VECTOR(35) /* External Interrupt 1 */ - -/* PORTE interrupt vectors */ -#define PORTE_INT0_vect_num 43 -#define PORTE_INT0_vect _VECTOR(43) /* External Interrupt 0 */ -#define PORTE_INT1_vect_num 44 -#define PORTE_INT1_vect _VECTOR(44) /* External Interrupt 1 */ - -/* TWIE interrupt vectors */ -#define TWIE_TWIS_vect_num 45 -#define TWIE_TWIS_vect _VECTOR(45) /* TWI Slave Interrupt */ -#define TWIE_TWIM_vect_num 46 -#define TWIE_TWIM_vect _VECTOR(46) /* TWI Master Interrupt */ - -/* TCE0 interrupt vectors */ -#define TCE0_OVF_vect_num 47 -#define TCE0_OVF_vect _VECTOR(47) /* Overflow Interrupt */ -#define TCE0_ERR_vect_num 48 -#define TCE0_ERR_vect _VECTOR(48) /* Error Interrupt */ -#define TCE0_CCA_vect_num 49 -#define TCE0_CCA_vect _VECTOR(49) /* Compare or Capture A Interrupt */ -#define TCE0_CCB_vect_num 50 -#define TCE0_CCB_vect _VECTOR(50) /* Compare or Capture B Interrupt */ -#define TCE0_CCC_vect_num 51 -#define TCE0_CCC_vect _VECTOR(51) /* Compare or Capture C Interrupt */ -#define TCE0_CCD_vect_num 52 -#define TCE0_CCD_vect _VECTOR(52) /* Compare or Capture D Interrupt */ - -/* USARTE0 interrupt vectors */ -#define USARTE0_RXC_vect_num 58 -#define USARTE0_RXC_vect _VECTOR(58) /* Reception Complete Interrupt */ -#define USARTE0_DRE_vect_num 59 -#define USARTE0_DRE_vect _VECTOR(59) /* Data Register Empty Interrupt */ -#define USARTE0_TXC_vect_num 60 -#define USARTE0_TXC_vect _VECTOR(60) /* Transmission Complete Interrupt */ - -/* PORTD interrupt vectors */ -#define PORTD_INT0_vect_num 64 -#define PORTD_INT0_vect _VECTOR(64) /* External Interrupt 0 */ -#define PORTD_INT1_vect_num 65 -#define PORTD_INT1_vect _VECTOR(65) /* External Interrupt 1 */ - -/* PORTA interrupt vectors */ -#define PORTA_INT0_vect_num 66 -#define PORTA_INT0_vect _VECTOR(66) /* External Interrupt 0 */ -#define PORTA_INT1_vect_num 67 -#define PORTA_INT1_vect _VECTOR(67) /* External Interrupt 1 */ - -/* ACA interrupt vectors */ -#define ACA_AC0_vect_num 68 -#define ACA_AC0_vect _VECTOR(68) /* AC0 Interrupt */ -#define ACA_AC1_vect_num 69 -#define ACA_AC1_vect _VECTOR(69) /* AC1 Interrupt */ -#define ACA_ACW_vect_num 70 -#define ACA_ACW_vect _VECTOR(70) /* ACW Window Mode Interrupt */ - -/* ADCA interrupt vectors */ -#define ADCA_CH0_vect_num 71 -#define ADCA_CH0_vect _VECTOR(71) /* Interrupt 0 */ - -/* TCD0 interrupt vectors */ -#define TCD0_OVF_vect_num 77 -#define TCD0_OVF_vect _VECTOR(77) /* Overflow Interrupt */ - -/* TCD2 interrupt vectors */ -#define TCD2_LUNF_vect_num 77 -#define TCD2_LUNF_vect _VECTOR(77) /* Low Byte Underflow Interrupt */ - -/* TCD0 interrupt vectors */ -#define TCD0_ERR_vect_num 78 -#define TCD0_ERR_vect _VECTOR(78) /* Error Interrupt */ - -/* TCD2 interrupt vectors */ -#define TCD2_HUNF_vect_num 78 -#define TCD2_HUNF_vect _VECTOR(78) /* High Byte Underflow Interrupt */ - -/* TCD0 interrupt vectors */ -#define TCD0_CCA_vect_num 79 -#define TCD0_CCA_vect _VECTOR(79) /* Compare or Capture A Interrupt */ - -/* TCD2 interrupt vectors */ -#define TCD2_LCMPA_vect_num 79 -#define TCD2_LCMPA_vect _VECTOR(79) /* Low Byte Compare A Interrupt */ - -/* TCD0 interrupt vectors */ -#define TCD0_CCB_vect_num 80 -#define TCD0_CCB_vect _VECTOR(80) /* Compare or Capture B Interrupt */ - -/* TCD2 interrupt vectors */ -#define TCD2_LCMPB_vect_num 80 -#define TCD2_LCMPB_vect _VECTOR(80) /* Low Byte Compare B Interrupt */ - -/* TCD0 interrupt vectors */ -#define TCD0_CCC_vect_num 81 -#define TCD0_CCC_vect _VECTOR(81) /* Compare or Capture C Interrupt */ - -/* TCD2 interrupt vectors */ -#define TCD2_LCMPC_vect_num 81 -#define TCD2_LCMPC_vect _VECTOR(81) /* Low Byte Compare C Interrupt */ - -/* TCD0 interrupt vectors */ -#define TCD0_CCD_vect_num 82 -#define TCD0_CCD_vect _VECTOR(82) /* Compare or Capture D Interrupt */ - -/* TCD2 interrupt vectors */ -#define TCD2_LCMPD_vect_num 82 -#define TCD2_LCMPD_vect _VECTOR(82) /* Low Byte Compare D Interrupt */ - -/* SPID interrupt vectors */ -#define SPID_INT_vect_num 87 -#define SPID_INT_vect _VECTOR(87) /* SPI Interrupt */ - -/* USARTD0 interrupt vectors */ -#define USARTD0_RXC_vect_num 88 -#define USARTD0_RXC_vect _VECTOR(88) /* Reception Complete Interrupt */ -#define USARTD0_DRE_vect_num 89 -#define USARTD0_DRE_vect _VECTOR(89) /* Data Register Empty Interrupt */ -#define USARTD0_TXC_vect_num 90 -#define USARTD0_TXC_vect _VECTOR(90) /* Transmission Complete Interrupt */ - -#define _VECTOR_SIZE 4 /* Size of individual vector. */ -#define _VECTORS_SIZE (91 * _VECTOR_SIZE) - - -/* ========== Constants ========== */ - -#define PROGMEM_START (0x0000) -#define PROGMEM_SIZE (139264) -#define PROGMEM_END (PROGMEM_START + PROGMEM_SIZE - 1) - -#define APP_SECTION_START (0x0000) -#define APP_SECTION_SIZE (131072) -#define APP_SECTION_PAGE_SIZE (256) -#define APP_SECTION_END (APP_SECTION_START + APP_SECTION_SIZE - 1) - -#define APPTABLE_SECTION_START (0x1E000) -#define APPTABLE_SECTION_SIZE (8192) -#define APPTABLE_SECTION_PAGE_SIZE (256) -#define APPTABLE_SECTION_END (APPTABLE_SECTION_START + APPTABLE_SECTION_SIZE - 1) - -#define BOOT_SECTION_START (0x20000) -#define BOOT_SECTION_SIZE (8192) -#define BOOT_SECTION_PAGE_SIZE (256) -#define BOOT_SECTION_END (BOOT_SECTION_START + BOOT_SECTION_SIZE - 1) - -#define DATAMEM_START (0x0000) -#define DATAMEM_SIZE (16384) -#define DATAMEM_END (DATAMEM_START + DATAMEM_SIZE - 1) - -#define IO_START (0x0000) -#define IO_SIZE (4096) -#define IO_PAGE_SIZE (0) -#define IO_END (IO_START + IO_SIZE - 1) - -#define MAPPED_EEPROM_START (0x1000) -#define MAPPED_EEPROM_SIZE (2048) -#define MAPPED_EEPROM_PAGE_SIZE (0) -#define MAPPED_EEPROM_END (MAPPED_EEPROM_START + MAPPED_EEPROM_SIZE - 1) - -#define INTERNAL_SRAM_START (0x2000) -#define INTERNAL_SRAM_SIZE (8192) -#define INTERNAL_SRAM_PAGE_SIZE (0) -#define INTERNAL_SRAM_END (INTERNAL_SRAM_START + INTERNAL_SRAM_SIZE - 1) - -#define EEPROM_START (0x0000) -#define EEPROM_SIZE (2048) -#define EEPROM_PAGE_SIZE (32) -#define EEPROM_END (EEPROM_START + EEPROM_SIZE - 1) - -#define SIGNATURES_START (0x0000) -#define SIGNATURES_SIZE (3) -#define SIGNATURES_PAGE_SIZE (0) -#define SIGNATURES_END (SIGNATURES_START + SIGNATURES_SIZE - 1) - -#define FUSES_START (0x0000) -#define FUSES_SIZE (6) -#define FUSES_PAGE_SIZE (0) -#define FUSES_END (FUSES_START + FUSES_SIZE - 1) - -#define LOCKBITS_START (0x0000) -#define LOCKBITS_SIZE (1) -#define LOCKBITS_PAGE_SIZE (0) -#define LOCKBITS_END (LOCKBITS_START + LOCKBITS_SIZE - 1) - -#define USER_SIGNATURES_START (0x0000) -#define USER_SIGNATURES_SIZE (256) -#define USER_SIGNATURES_PAGE_SIZE (256) -#define USER_SIGNATURES_END (USER_SIGNATURES_START + USER_SIGNATURES_SIZE - 1) - -#define PROD_SIGNATURES_START (0x0000) -#define PROD_SIGNATURES_SIZE (64) -#define PROD_SIGNATURES_PAGE_SIZE (256) -#define PROD_SIGNATURES_END (PROD_SIGNATURES_START + PROD_SIGNATURES_SIZE - 1) - -#define FLASHSTART PROGMEM_START -#define FLASHEND PROGMEM_END -#define SPM_PAGESIZE 256 -#define RAMSTART INTERNAL_SRAM_START -#define RAMSIZE INTERNAL_SRAM_SIZE -#define RAMEND INTERNAL_SRAM_END -#define E2END EEPROM_END -#define E2PAGESIZE EEPROM_PAGE_SIZE - - -/* ========== Fuses ========== */ -#define FUSE_MEMORY_SIZE 6 - -/* Fuse Byte 0 Reserved */ - -/* Fuse Byte 1 */ -#define FUSE_WDP0 (unsigned char)~_BV(0) /* Watchdog Timeout Period Bit 0 */ -#define FUSE_WDP1 (unsigned char)~_BV(1) /* Watchdog Timeout Period Bit 1 */ -#define FUSE_WDP2 (unsigned char)~_BV(2) /* Watchdog Timeout Period Bit 2 */ -#define FUSE_WDP3 (unsigned char)~_BV(3) /* Watchdog Timeout Period Bit 3 */ -#define FUSE_WDWP0 (unsigned char)~_BV(4) /* Watchdog Window Timeout Period Bit 0 */ -#define FUSE_WDWP1 (unsigned char)~_BV(5) /* Watchdog Window Timeout Period Bit 1 */ -#define FUSE_WDWP2 (unsigned char)~_BV(6) /* Watchdog Window Timeout Period Bit 2 */ -#define FUSE_WDWP3 (unsigned char)~_BV(7) /* Watchdog Window Timeout Period Bit 3 */ -#define FUSE1_DEFAULT (0xFF) - -/* Fuse Byte 2 */ -#define FUSE_BODPD0 (unsigned char)~_BV(0) /* BOD Operation in Power-Down Mode Bit 0 */ -#define FUSE_BODPD1 (unsigned char)~_BV(1) /* BOD Operation in Power-Down Mode Bit 1 */ -#define FUSE_TOSCSEL (unsigned char)~_BV(5) /* Timer Oscillator pin location */ -#define FUSE_BOOTRST (unsigned char)~_BV(6) /* Boot Loader Section Reset Vector */ -#define FUSE2_DEFAULT (0xFF) - -/* Fuse Byte 3 Reserved */ - -/* Fuse Byte 4 */ -#define FUSE_WDLOCK (unsigned char)~_BV(1) /* Watchdog Timer Lock */ -#define FUSE_SUT0 (unsigned char)~_BV(2) /* Start-up Time Bit 0 */ -#define FUSE_SUT1 (unsigned char)~_BV(3) /* Start-up Time Bit 1 */ -#define FUSE_RSTDISBL (unsigned char)~_BV(4) /* External Reset Disable */ -#define FUSE4_DEFAULT (0xFF) - -/* Fuse Byte 5 */ -#define FUSE_BODLVL0 (unsigned char)~_BV(0) /* Brownout Detection Voltage Level Bit 0 */ -#define FUSE_BODLVL1 (unsigned char)~_BV(1) /* Brownout Detection Voltage Level Bit 1 */ -#define FUSE_BODLVL2 (unsigned char)~_BV(2) /* Brownout Detection Voltage Level Bit 2 */ -#define FUSE_EESAVE (unsigned char)~_BV(3) /* Preserve EEPROM Through Chip Erase */ -#define FUSE_BODACT0 (unsigned char)~_BV(4) /* BOD Operation in Active Mode Bit 0 */ -#define FUSE_BODACT1 (unsigned char)~_BV(5) /* BOD Operation in Active Mode Bit 1 */ -#define FUSE5_DEFAULT (0xFF) - -/* ========== Lock Bits ========== */ -#define __LOCK_BITS_EXIST -#define __BOOT_LOCK_APPLICATION_TABLE_BITS_EXIST -#define __BOOT_LOCK_APPLICATION_BITS_EXIST -#define __BOOT_LOCK_BOOT_BITS_EXIST - -/* ========== Signature ========== */ -#define SIGNATURE_0 0x1E -#define SIGNATURE_1 0x97 -#define SIGNATURE_2 0x47 - -/* ========== Power Reduction Condition Definitions ========== */ - -/* PR.PRGEN */ -#define __AVR_HAVE_PRGEN (PR_RTC_bm|PR_EVSYS_bm) -#define __AVR_HAVE_PRGEN_RTC -#define __AVR_HAVE_PRGEN_EVSYS - -/* PR.PRPA */ -#define __AVR_HAVE_PRPA (PR_ADC_bm|PR_AC_bm) -#define __AVR_HAVE_PRPA_ADC -#define __AVR_HAVE_PRPA_AC - -/* PR.PRPC */ -#define __AVR_HAVE_PRPC (PR_TWI_bm|PR_USART0_bm|PR_SPI_bm|PR_HIRES_bm|PR_TC1_bm|PR_TC0_bm) -#define __AVR_HAVE_PRPC_TWI -#define __AVR_HAVE_PRPC_USART0 -#define __AVR_HAVE_PRPC_SPI -#define __AVR_HAVE_PRPC_HIRES -#define __AVR_HAVE_PRPC_TC1 -#define __AVR_HAVE_PRPC_TC0 - -/* PR.PRPD */ -#define __AVR_HAVE_PRPD (PR_USART0_bm|PR_SPI_bm|PR_TC0_bm) -#define __AVR_HAVE_PRPD_USART0 -#define __AVR_HAVE_PRPD_SPI -#define __AVR_HAVE_PRPD_TC0 - -/* PR.PRPE */ -#define __AVR_HAVE_PRPE (PR_TWI_bm|PR_USART0_bm|PR_TC0_bm) -#define __AVR_HAVE_PRPE_TWI -#define __AVR_HAVE_PRPE_USART0 -#define __AVR_HAVE_PRPE_TC0 - -/* PR.PRPF */ -#define __AVR_HAVE_PRPF (PR_USART0_bm|PR_TC0_bm) -#define __AVR_HAVE_PRPF_USART0 -#define __AVR_HAVE_PRPF_TC0 - - -#endif /* #ifdef _AVR_ATXMEGA128D4_H_INCLUDED */ - diff --git a/arduino/hardware/tools/avr/avr/include/avr/iox16a4.h b/arduino/hardware/tools/avr/avr/include/avr/iox16a4.h deleted file mode 100644 index dbef5eb..0000000 --- a/arduino/hardware/tools/avr/avr/include/avr/iox16a4.h +++ /dev/null @@ -1,6748 +0,0 @@ -/* Copyright (c) 2009-2010 Atmel Corporation - All rights reserved. - - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - * Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - * Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in - the documentation and/or other materials provided with the - distribution. - - * Neither the name of the copyright holders nor the names of - contributors may be used to endorse or promote products derived - from this software without specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. */ - -/* $Id: iox16a4.h 2200 2010-12-14 04:24:24Z arcanum $ */ - -/* avr/iox16a4.h - definitions for ATxmega16A4 */ - -/* This file should only be included from , never directly. */ - -#ifndef _AVR_IO_H_ -# error "Include instead of this file." -#endif - -#ifndef _AVR_IOXXX_H_ -# define _AVR_IOXXX_H_ "iox16a4.h" -#else -# error "Attempt to include more than one file." -#endif - - -#ifndef _AVR_ATxmega16A4_H_ -#define _AVR_ATxmega16A4_H_ 1 - - -/* Ungrouped common registers */ -#define GPIOR0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ -#define GPIOR1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ -#define GPIOR2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ -#define GPIOR3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ -#define GPIOR4 _SFR_MEM8(0x0004) /* General Purpose IO Register 4 */ -#define GPIOR5 _SFR_MEM8(0x0005) /* General Purpose IO Register 5 */ -#define GPIOR6 _SFR_MEM8(0x0006) /* General Purpose IO Register 6 */ -#define GPIOR7 _SFR_MEM8(0x0007) /* General Purpose IO Register 7 */ -#define GPIOR8 _SFR_MEM8(0x0008) /* General Purpose IO Register 8 */ -#define GPIOR9 _SFR_MEM8(0x0009) /* General Purpose IO Register 9 */ -#define GPIORA _SFR_MEM8(0x000A) /* General Purpose IO Register 10 */ -#define GPIORB _SFR_MEM8(0x000B) /* General Purpose IO Register 11 */ -#define GPIORC _SFR_MEM8(0x000C) /* General Purpose IO Register 12 */ -#define GPIORD _SFR_MEM8(0x000D) /* General Purpose IO Register 13 */ -#define GPIORE _SFR_MEM8(0x000E) /* General Purpose IO Register 14 */ -#define GPIORF _SFR_MEM8(0x000F) /* General Purpose IO Register 15 */ - -/* Deprecated */ -#define GPIO0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ -#define GPIO1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ -#define GPIO2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ -#define GPIO3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ -#define GPIO4 _SFR_MEM8(0x0004) /* General Purpose IO Register 4 */ -#define GPIO5 _SFR_MEM8(0x0005) /* General Purpose IO Register 5 */ -#define GPIO6 _SFR_MEM8(0x0006) /* General Purpose IO Register 6 */ -#define GPIO7 _SFR_MEM8(0x0007) /* General Purpose IO Register 7 */ -#define GPIO8 _SFR_MEM8(0x0008) /* General Purpose IO Register 8 */ -#define GPIO9 _SFR_MEM8(0x0009) /* General Purpose IO Register 9 */ -#define GPIOA _SFR_MEM8(0x000A) /* General Purpose IO Register 10 */ -#define GPIOB _SFR_MEM8(0x000B) /* General Purpose IO Register 11 */ -#define GPIOC _SFR_MEM8(0x000C) /* General Purpose IO Register 12 */ -#define GPIOD _SFR_MEM8(0x000D) /* General Purpose IO Register 13 */ -#define GPIOE _SFR_MEM8(0x000E) /* General Purpose IO Register 14 */ -#define GPIOF _SFR_MEM8(0x000F) /* General Purpose IO Register 15 */ - -#define CCP _SFR_MEM8(0x0034) /* Configuration Change Protection */ -#define RAMPD _SFR_MEM8(0x0038) /* Ramp D */ -#define RAMPX _SFR_MEM8(0x0039) /* Ramp X */ -#define RAMPY _SFR_MEM8(0x003A) /* Ramp Y */ -#define RAMPZ _SFR_MEM8(0x003B) /* Ramp Z */ -#define EIND _SFR_MEM8(0x003C) /* Extended Indirect Jump */ -#define SPL _SFR_MEM8(0x003D) /* Stack Pointer Low */ -#define SPH _SFR_MEM8(0x003E) /* Stack Pointer High */ -#define SREG _SFR_MEM8(0x003F) /* Status Register */ - - -/* C Language Only */ -#if !defined (__ASSEMBLER__) - -#include - -typedef volatile uint8_t register8_t; -typedef volatile uint16_t register16_t; -typedef volatile uint32_t register32_t; - - -#ifdef _WORDREGISTER -#undef _WORDREGISTER -#endif -#define _WORDREGISTER(regname) \ - __extension__ union \ - { \ - register16_t regname; \ - struct \ - { \ - register8_t regname ## L; \ - register8_t regname ## H; \ - }; \ - } - -#ifdef _DWORDREGISTER -#undef _DWORDREGISTER -#endif -#define _DWORDREGISTER(regname) \ - __extension__ union \ - { \ - register32_t regname; \ - struct \ - { \ - register8_t regname ## 0; \ - register8_t regname ## 1; \ - register8_t regname ## 2; \ - register8_t regname ## 3; \ - }; \ - } - - -/* -========================================================================== -IO Module Structures -========================================================================== -*/ - - -/* --------------------------------------------------------------------------- -XOCD - On-Chip Debug System --------------------------------------------------------------------------- -*/ - -/* On-Chip Debug System */ -typedef struct OCD_struct -{ - register8_t OCDR0; /* OCD Register 0 */ - register8_t OCDR1; /* OCD Register 1 */ -} OCD_t; - - -/* CCP signatures */ -typedef enum CCP_enum -{ - CCP_SPM_gc = (0x9D<<0), /* SPM Instruction Protection */ - CCP_IOREG_gc = (0xD8<<0), /* IO Register Protection */ -} CCP_t; - - -/* --------------------------------------------------------------------------- -CLK - Clock System --------------------------------------------------------------------------- -*/ - -/* Clock System */ -typedef struct CLK_struct -{ - register8_t CTRL; /* Control Register */ - register8_t PSCTRL; /* Prescaler Control Register */ - register8_t LOCK; /* Lock register */ - register8_t RTCCTRL; /* RTC Control Register */ -} CLK_t; - -/* --------------------------------------------------------------------------- -CLK - Clock System --------------------------------------------------------------------------- -*/ - -/* Power Reduction */ -typedef struct PR_struct -{ - register8_t PRGEN; /* General Power Reduction */ - register8_t PRPA; /* Power Reduction Port A */ - register8_t PRPB; /* Power Reduction Port B */ - register8_t PRPC; /* Power Reduction Port C */ - register8_t PRPD; /* Power Reduction Port D */ - register8_t PRPE; /* Power Reduction Port E */ - register8_t PRPF; /* Power Reduction Port F */ -} PR_t; - -/* System Clock Selection */ -typedef enum CLK_SCLKSEL_enum -{ - CLK_SCLKSEL_RC2M_gc = (0x00<<0), /* Internal 2MHz RC Oscillator */ - CLK_SCLKSEL_RC32M_gc = (0x01<<0), /* Internal 32MHz RC Oscillator */ - CLK_SCLKSEL_RC32K_gc = (0x02<<0), /* Internal 32kHz RC Oscillator */ - CLK_SCLKSEL_XOSC_gc = (0x03<<0), /* External Crystal Oscillator or Clock */ - CLK_SCLKSEL_PLL_gc = (0x04<<0), /* Phase Locked Loop */ -} CLK_SCLKSEL_t; - -/* Prescaler A Division Factor */ -typedef enum CLK_PSADIV_enum -{ - CLK_PSADIV_1_gc = (0x00<<2), /* Divide by 1 */ - CLK_PSADIV_2_gc = (0x01<<2), /* Divide by 2 */ - CLK_PSADIV_4_gc = (0x03<<2), /* Divide by 4 */ - CLK_PSADIV_8_gc = (0x05<<2), /* Divide by 8 */ - CLK_PSADIV_16_gc = (0x07<<2), /* Divide by 16 */ - CLK_PSADIV_32_gc = (0x09<<2), /* Divide by 32 */ - CLK_PSADIV_64_gc = (0x0B<<2), /* Divide by 64 */ - CLK_PSADIV_128_gc = (0x0D<<2), /* Divide by 128 */ - CLK_PSADIV_256_gc = (0x0F<<2), /* Divide by 256 */ - CLK_PSADIV_512_gc = (0x11<<2), /* Divide by 512 */ -} CLK_PSADIV_t; - -/* Prescaler B and C Division Factor */ -typedef enum CLK_PSBCDIV_enum -{ - CLK_PSBCDIV_1_1_gc = (0x00<<0), /* Divide B by 1 and C by 1 */ - CLK_PSBCDIV_1_2_gc = (0x01<<0), /* Divide B by 1 and C by 2 */ - CLK_PSBCDIV_4_1_gc = (0x02<<0), /* Divide B by 4 and C by 1 */ - CLK_PSBCDIV_2_2_gc = (0x03<<0), /* Divide B by 2 and C by 2 */ -} CLK_PSBCDIV_t; - -/* RTC Clock Source */ -typedef enum CLK_RTCSRC_enum -{ - CLK_RTCSRC_ULP_gc = (0x00<<1), /* 1kHz from internal 32kHz ULP */ - CLK_RTCSRC_TOSC_gc = (0x01<<1), /* 1kHz from 32kHz crystal oscillator on TOSC */ - CLK_RTCSRC_RCOSC_gc = (0x02<<1), /* 1kHz from internal 32kHz RC oscillator */ - CLK_RTCSRC_TOSC32_gc = (0x05<<1), /* 32kHz from 32kHz crystal oscillator on TOSC */ -} CLK_RTCSRC_t; - - -/* --------------------------------------------------------------------------- -SLEEP - Sleep Controller --------------------------------------------------------------------------- -*/ - -/* Sleep Controller */ -typedef struct SLEEP_struct -{ - register8_t CTRL; /* Control Register */ -} SLEEP_t; - -/* Sleep Mode */ -typedef enum SLEEP_SMODE_enum -{ - SLEEP_SMODE_IDLE_gc = (0x00<<1), /* Idle mode */ - SLEEP_SMODE_PDOWN_gc = (0x02<<1), /* Power-down Mode */ - SLEEP_SMODE_PSAVE_gc = (0x03<<1), /* Power-save Mode */ - SLEEP_SMODE_STDBY_gc = (0x06<<1), /* Standby Mode */ - SLEEP_SMODE_ESTDBY_gc = (0x07<<1), /* Extended Standby Mode */ -} SLEEP_SMODE_t; - - -#define SLEEP_MODE_IDLE (0x00<<1) -#define SLEEP_MODE_PWR_DOWN (0x02<<1) -#define SLEEP_MODE_PWR_SAVE (0x03<<1) -#define SLEEP_MODE_STANDBY (0x06<<1) -#define SLEEP_MODE_EXT_STANDBY (0x07<<1) - - -/* --------------------------------------------------------------------------- -OSC - Oscillator --------------------------------------------------------------------------- -*/ - -/* Oscillator */ -typedef struct OSC_struct -{ - register8_t CTRL; /* Control Register */ - register8_t STATUS; /* Status Register */ - register8_t XOSCCTRL; /* External Oscillator Control Register */ - register8_t XOSCFAIL; /* External Oscillator Failure Detection Register */ - register8_t RC32KCAL; /* 32kHz Internal Oscillator Calibration Register */ - register8_t PLLCTRL; /* PLL Control REgister */ - register8_t DFLLCTRL; /* DFLL Control Register */ -} OSC_t; - -/* Oscillator Frequency Range */ -typedef enum OSC_FRQRANGE_enum -{ - OSC_FRQRANGE_04TO2_gc = (0x00<<6), /* 0.4 - 2 MHz */ - OSC_FRQRANGE_2TO9_gc = (0x01<<6), /* 2 - 9 MHz */ - OSC_FRQRANGE_9TO12_gc = (0x02<<6), /* 9 - 12 MHz */ - OSC_FRQRANGE_12TO16_gc = (0x03<<6), /* 12 - 16 MHz */ -} OSC_FRQRANGE_t; - -/* External Oscillator Selection and Startup Time */ -typedef enum OSC_XOSCSEL_enum -{ - OSC_XOSCSEL_EXTCLK_gc = (0x00<<0), /* External Clock - 6 CLK */ - OSC_XOSCSEL_32KHz_gc = (0x02<<0), /* 32kHz TOSC - 32K CLK */ - OSC_XOSCSEL_XTAL_256CLK_gc = (0x03<<0), /* 0.4-16MHz XTAL - 256 CLK */ - OSC_XOSCSEL_XTAL_1KCLK_gc = (0x07<<0), /* 0.4-16MHz XTAL - 1K CLK */ - OSC_XOSCSEL_XTAL_16KCLK_gc = (0x0B<<0), /* 0.4-16MHz XTAL - 16K CLK */ -} OSC_XOSCSEL_t; - -/* PLL Clock Source */ -typedef enum OSC_PLLSRC_enum -{ - OSC_PLLSRC_RC2M_gc = (0x00<<6), /* Internal 2MHz RC Oscillator */ - OSC_PLLSRC_RC32M_gc = (0x02<<6), /* Internal 32MHz RC Oscillator */ - OSC_PLLSRC_XOSC_gc = (0x03<<6), /* External Oscillator */ -} OSC_PLLSRC_t; - - -/* --------------------------------------------------------------------------- -DFLL - DFLL --------------------------------------------------------------------------- -*/ - -/* DFLL */ -typedef struct DFLL_struct -{ - register8_t CTRL; /* Control Register */ - register8_t reserved_0x01; - register8_t CALA; /* Calibration Register A */ - register8_t CALB; /* Calibration Register B */ - register8_t COMP0; /* Oscillator Compare Register 0 */ - register8_t COMP1; /* Oscillator Compare Register 1 */ - register8_t COMP2; /* Oscillator Compare Register 2 */ - register8_t reserved_0x07; -} DFLL_t; - - -/* --------------------------------------------------------------------------- -RST - Reset --------------------------------------------------------------------------- -*/ - -/* Reset */ -typedef struct RST_struct -{ - register8_t STATUS; /* Status Register */ - register8_t CTRL; /* Control Register */ -} RST_t; - - -/* --------------------------------------------------------------------------- -WDT - Watch-Dog Timer --------------------------------------------------------------------------- -*/ - -/* Watch-Dog Timer */ -typedef struct WDT_struct -{ - register8_t CTRL; /* Control */ - register8_t WINCTRL; /* Windowed Mode Control */ - register8_t STATUS; /* Status */ -} WDT_t; - -/* Period setting */ -typedef enum WDT_PER_enum -{ - WDT_PER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ - WDT_PER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ - WDT_PER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ - WDT_PER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ - WDT_PER_128CLK_gc = (0x04<<2), /* 128 cycles (0.125s @ 3.3V) */ - WDT_PER_256CLK_gc = (0x05<<2), /* 256 cycles (0.25s @ 3.3V) */ - WDT_PER_512CLK_gc = (0x06<<2), /* 512 cycles (0.5s @ 3.3V) */ - WDT_PER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ - WDT_PER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ - WDT_PER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ - WDT_PER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ -} WDT_PER_t; - -/* Closed window period */ -typedef enum WDT_WPER_enum -{ - WDT_WPER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ - WDT_WPER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ - WDT_WPER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ - WDT_WPER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ - WDT_WPER_128CLK_gc = (0x04<<2), /* 128 cycles (0.125s @ 3.3V) */ - WDT_WPER_256CLK_gc = (0x05<<2), /* 256 cycles (0.25s @ 3.3V) */ - WDT_WPER_512CLK_gc = (0x06<<2), /* 512 cycles (0.5s @ 3.3V) */ - WDT_WPER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ - WDT_WPER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ - WDT_WPER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ - WDT_WPER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ -} WDT_WPER_t; - - -/* --------------------------------------------------------------------------- -MCU - MCU Control --------------------------------------------------------------------------- -*/ - -/* MCU Control */ -typedef struct MCU_struct -{ - register8_t DEVID0; /* Device ID byte 0 */ - register8_t DEVID1; /* Device ID byte 1 */ - register8_t DEVID2; /* Device ID byte 2 */ - register8_t REVID; /* Revision ID */ - register8_t JTAGUID; /* JTAG User ID */ - register8_t reserved_0x05; - register8_t MCUCR; /* MCU Control */ - register8_t reserved_0x07; - register8_t EVSYSLOCK; /* Event System Lock */ - register8_t AWEXLOCK; /* AWEX Lock */ - register8_t reserved_0x0A; - register8_t reserved_0x0B; -} MCU_t; - - -/* --------------------------------------------------------------------------- -PMIC - Programmable Multi-level Interrupt Controller --------------------------------------------------------------------------- -*/ - -/* Programmable Multi-level Interrupt Controller */ -typedef struct PMIC_struct -{ - register8_t STATUS; /* Status Register */ - register8_t INTPRI; /* Interrupt Priority */ - register8_t CTRL; /* Control Register */ -} PMIC_t; - - -/* --------------------------------------------------------------------------- -DMA - DMA Controller --------------------------------------------------------------------------- -*/ - -/* DMA Channel */ -typedef struct DMA_CH_struct -{ - register8_t CTRLA; /* Channel Control */ - register8_t CTRLB; /* Channel Control */ - register8_t ADDRCTRL; /* Address Control */ - register8_t TRIGSRC; /* Channel Trigger Source */ - _WORDREGISTER(TRFCNT); /* Channel Block Transfer Count */ - register8_t REPCNT; /* Channel Repeat Count */ - register8_t reserved_0x07; - register8_t SRCADDR0; /* Channel Source Address 0 */ - register8_t SRCADDR1; /* Channel Source Address 1 */ - register8_t SRCADDR2; /* Channel Source Address 2 */ - register8_t reserved_0x0B; - register8_t DESTADDR0; /* Channel Destination Address 0 */ - register8_t DESTADDR1; /* Channel Destination Address 1 */ - register8_t DESTADDR2; /* Channel Destination Address 2 */ - register8_t reserved_0x0F; -} DMA_CH_t; - -/* --------------------------------------------------------------------------- -DMA - DMA Controller --------------------------------------------------------------------------- -*/ - -/* DMA Controller */ -typedef struct DMA_struct -{ - register8_t CTRL; /* Control */ - register8_t reserved_0x01; - register8_t reserved_0x02; - register8_t INTFLAGS; /* Transfer Interrupt Status */ - register8_t STATUS; /* Status */ - register8_t reserved_0x05; - _WORDREGISTER(TEMP); /* Temporary Register For 16/24-bit Access */ - register8_t reserved_0x08; - register8_t reserved_0x09; - register8_t reserved_0x0A; - register8_t reserved_0x0B; - register8_t reserved_0x0C; - register8_t reserved_0x0D; - register8_t reserved_0x0E; - register8_t reserved_0x0F; - DMA_CH_t CH0; /* DMA Channel 0 */ - DMA_CH_t CH1; /* DMA Channel 1 */ - DMA_CH_t CH2; /* DMA Channel 2 */ - DMA_CH_t CH3; /* DMA Channel 3 */ -} DMA_t; - -/* Burst mode */ -typedef enum DMA_CH_BURSTLEN_enum -{ - DMA_CH_BURSTLEN_1BYTE_gc = (0x00<<0), /* 1-byte burst mode */ - DMA_CH_BURSTLEN_2BYTE_gc = (0x01<<0), /* 2-byte burst mode */ - DMA_CH_BURSTLEN_4BYTE_gc = (0x02<<0), /* 4-byte burst mode */ - DMA_CH_BURSTLEN_8BYTE_gc = (0x03<<0), /* 8-byte burst mode */ -} DMA_CH_BURSTLEN_t; - -/* Source address reload mode */ -typedef enum DMA_CH_SRCRELOAD_enum -{ - DMA_CH_SRCRELOAD_NONE_gc = (0x00<<6), /* No reload */ - DMA_CH_SRCRELOAD_BLOCK_gc = (0x01<<6), /* Reload at end of block */ - DMA_CH_SRCRELOAD_BURST_gc = (0x02<<6), /* Reload at end of burst */ - DMA_CH_SRCRELOAD_TRANSACTION_gc = (0x03<<6), /* Reload at end of transaction */ -} DMA_CH_SRCRELOAD_t; - -/* Source addressing mode */ -typedef enum DMA_CH_SRCDIR_enum -{ - DMA_CH_SRCDIR_FIXED_gc = (0x00<<4), /* Fixed */ - DMA_CH_SRCDIR_INC_gc = (0x01<<4), /* Increment */ - DMA_CH_SRCDIR_DEC_gc = (0x02<<4), /* Decrement */ -} DMA_CH_SRCDIR_t; - -/* Destination adress reload mode */ -typedef enum DMA_CH_DESTRELOAD_enum -{ - DMA_CH_DESTRELOAD_NONE_gc = (0x00<<2), /* No reload */ - DMA_CH_DESTRELOAD_BLOCK_gc = (0x01<<2), /* Reload at end of block */ - DMA_CH_DESTRELOAD_BURST_gc = (0x02<<2), /* Reload at end of burst */ - DMA_CH_DESTRELOAD_TRANSACTION_gc = (0x03<<2), /* Reload at end of transaction */ -} DMA_CH_DESTRELOAD_t; - -/* Destination adressing mode */ -typedef enum DMA_CH_DESTDIR_enum -{ - DMA_CH_DESTDIR_FIXED_gc = (0x00<<0), /* Fixed */ - DMA_CH_DESTDIR_INC_gc = (0x01<<0), /* Increment */ - DMA_CH_DESTDIR_DEC_gc = (0x02<<0), /* Decrement */ -} DMA_CH_DESTDIR_t; - -/* Transfer trigger source */ -typedef enum DMA_CH_TRIGSRC_enum -{ - DMA_CH_TRIGSRC_OFF_gc = (0x00<<0), /* Off software triggers only */ - DMA_CH_TRIGSRC_EVSYS_CH0_gc = (0x01<<0), /* Event System Channel 0 */ - DMA_CH_TRIGSRC_EVSYS_CH1_gc = (0x02<<0), /* Event System Channel 1 */ - DMA_CH_TRIGSRC_EVSYS_CH2_gc = (0x03<<0), /* Event System Channel 2 */ - DMA_CH_TRIGSRC_ADCA_CH0_gc = (0x10<<0), /* ADCA Channel 0 */ - DMA_CH_TRIGSRC_ADCA_CH1_gc = (0x11<<0), /* ADCA Channel 1 */ - DMA_CH_TRIGSRC_ADCA_CH2_gc = (0x12<<0), /* ADCA Channel 2 */ - DMA_CH_TRIGSRC_ADCA_CH3_gc = (0x13<<0), /* ADCA Channel 3 */ - DMA_CH_TRIGSRC_ADCA_CH4_gc = (0x14<<0), /* ADCA Channel 0,1,2,3 combined */ - DMA_CH_TRIGSRC_DACA_CH0_gc = (0x15<<0), /* DACA Channel 0 */ - DMA_CH_TRIGSRC_DACA_CH1_gc = (0x16<<0), /* DACA Channel 1 */ - DMA_CH_TRIGSRC_ADCB_CH0_gc = (0x20<<0), /* ADCB Channel 0 */ - DMA_CH_TRIGSRC_ADCB_CH1_gc = (0x21<<0), /* ADCB Channel 1 */ - DMA_CH_TRIGSRC_ADCB_CH2_gc = (0x22<<0), /* ADCB Channel 2 */ - DMA_CH_TRIGSRC_ADCB_CH3_gc = (0x23<<0), /* ADCB Channel 3 */ - DMA_CH_TRIGSRC_ADCB_CH4_gc = (0x24<<0), /* ADCB Channel 0,1,2,3 combined */ - DMA_CH_TRIGSRC_DACB_CH0_gc = (0x25<<0), /* DACB Channel 0 */ - DMA_CH_TRIGSRC_DACB_CH1_gc = (0x26<<0), /* DACB Channel 1 */ - DMA_CH_TRIGSRC_TCC0_OVF_gc = (0x40<<0), /* Timer/Counter C0 Overflow */ - DMA_CH_TRIGSRC_TCC0_ERR_gc = (0x41<<0), /* Timer/Counter C0 Error */ - DMA_CH_TRIGSRC_TCC0_CCA_gc = (0x42<<0), /* Timer/Counter C0 Compare or Capture A */ - DMA_CH_TRIGSRC_TCC0_CCB_gc = (0x43<<0), /* Timer/Counter C0 Compare or Capture B */ - DMA_CH_TRIGSRC_TCC0_CCC_gc = (0x44<<0), /* Timer/Counter C0 Compare or Capture C */ - DMA_CH_TRIGSRC_TCC0_CCD_gc = (0x45<<0), /* Timer/Counter C0 Compare or Capture D */ - DMA_CH_TRIGSRC_TCC1_OVF_gc = (0x46<<0), /* Timer/Counter C1 Overflow */ - DMA_CH_TRIGSRC_TCC1_ERR_gc = (0x47<<0), /* Timer/Counter C1 Error */ - DMA_CH_TRIGSRC_TCC1_CCA_gc = (0x48<<0), /* Timer/Counter C1 Compare or Capture A */ - DMA_CH_TRIGSRC_TCC1_CCB_gc = (0x49<<0), /* Timer/Counter C1 Compare or Capture B */ - DMA_CH_TRIGSRC_SPIC_gc = (0x4A<<0), /* SPI C Transfer Complete */ - DMA_CH_TRIGSRC_USARTC0_RXC_gc = (0x4B<<0), /* USART C0 Receive Complete */ - DMA_CH_TRIGSRC_USARTC0_DRE_gc = (0x4C<<0), /* USART C0 Data Register Empty */ - DMA_CH_TRIGSRC_USARTC1_RXC_gc = (0x4E<<0), /* USART C1 Receive Complete */ - DMA_CH_TRIGSRC_USARTC1_DRE_gc = (0x4F<<0), /* USART C1 Data Register Empty */ - DMA_CH_TRIGSRC_TCD0_OVF_gc = (0x60<<0), /* Timer/Counter D0 Overflow */ - DMA_CH_TRIGSRC_TCD0_ERR_gc = (0x61<<0), /* Timer/Counter D0 Error */ - DMA_CH_TRIGSRC_TCD0_CCA_gc = (0x62<<0), /* Timer/Counter D0 Compare or Capture A */ - DMA_CH_TRIGSRC_TCD0_CCB_gc = (0x63<<0), /* Timer/Counter D0 Compare or Capture B */ - DMA_CH_TRIGSRC_TCD0_CCC_gc = (0x64<<0), /* Timer/Counter D0 Compare or Capture C */ - DMA_CH_TRIGSRC_TCD0_CCD_gc = (0x65<<0), /* Timer/Counter D0 Compare or Capture D */ - DMA_CH_TRIGSRC_TCD1_OVF_gc = (0x66<<0), /* Timer/Counter D1 Overflow */ - DMA_CH_TRIGSRC_TCD1_ERR_gc = (0x67<<0), /* Timer/Counter D1 Error */ - DMA_CH_TRIGSRC_TCD1_CCA_gc = (0x68<<0), /* Timer/Counter D1 Compare or Capture A */ - DMA_CH_TRIGSRC_TCD1_CCB_gc = (0x69<<0), /* Timer/Counter D1 Compare or Capture B */ - DMA_CH_TRIGSRC_SPID_gc = (0x6A<<0), /* SPI D Transfer Complete */ - DMA_CH_TRIGSRC_USARTD0_RXC_gc = (0x6B<<0), /* USART D0 Receive Complete */ - DMA_CH_TRIGSRC_USARTD0_DRE_gc = (0x6C<<0), /* USART D0 Data Register Empty */ - DMA_CH_TRIGSRC_USARTD1_RXC_gc = (0x6E<<0), /* USART D1 Receive Complete */ - DMA_CH_TRIGSRC_USARTD1_DRE_gc = (0x6F<<0), /* USART D1 Data Register Empty */ - DMA_CH_TRIGSRC_TCE0_OVF_gc = (0x80<<0), /* Timer/Counter E0 Overflow */ - DMA_CH_TRIGSRC_TCE0_ERR_gc = (0x81<<0), /* Timer/Counter E0 Error */ - DMA_CH_TRIGSRC_TCE0_CCA_gc = (0x82<<0), /* Timer/Counter E0 Compare or Capture A */ - DMA_CH_TRIGSRC_TCE0_CCB_gc = (0x83<<0), /* Timer/Counter E0 Compare or Capture B */ - DMA_CH_TRIGSRC_TCE0_CCC_gc = (0x84<<0), /* Timer/Counter E0 Compare or Capture C */ - DMA_CH_TRIGSRC_TCE0_CCD_gc = (0x85<<0), /* Timer/Counter E0 Compare or Capture D */ - DMA_CH_TRIGSRC_TCE1_OVF_gc = (0x86<<0), /* Timer/Counter E1 Overflow */ - DMA_CH_TRIGSRC_TCE1_ERR_gc = (0x87<<0), /* Timer/Counter E1 Error */ - DMA_CH_TRIGSRC_TCE1_CCA_gc = (0x88<<0), /* Timer/Counter E1 Compare or Capture A */ - DMA_CH_TRIGSRC_TCE1_CCB_gc = (0x89<<0), /* Timer/Counter E1 Compare or Capture B */ - DMA_CH_TRIGSRC_SPIE_gc = (0x8A<<0), /* SPI E Transfer Complete */ - DMA_CH_TRIGSRC_USARTE0_RXC_gc = (0x8B<<0), /* USART E0 Receive Complete */ - DMA_CH_TRIGSRC_USARTE0_DRE_gc = (0x8C<<0), /* USART E0 Data Register Empty */ - DMA_CH_TRIGSRC_USARTE1_RXC_gc = (0x8E<<0), /* USART E1 Receive Complete */ - DMA_CH_TRIGSRC_USARTE1_DRE_gc = (0x8F<<0), /* USART E1 Data Register Empty */ - DMA_CH_TRIGSRC_TCF0_OVF_gc = (0xA0<<0), /* Timer/Counter F0 Overflow */ - DMA_CH_TRIGSRC_TCF0_ERR_gc = (0xA1<<0), /* Timer/Counter F0 Error */ - DMA_CH_TRIGSRC_TCF0_CCA_gc = (0xA2<<0), /* Timer/Counter F0 Compare or Capture A */ - DMA_CH_TRIGSRC_TCF0_CCB_gc = (0xA3<<0), /* Timer/Counter F0 Compare or Capture B */ - DMA_CH_TRIGSRC_TCF0_CCC_gc = (0xA4<<0), /* Timer/Counter F0 Compare or Capture C */ - DMA_CH_TRIGSRC_TCF0_CCD_gc = (0xA5<<0), /* Timer/Counter F0 Compare or Capture D */ - DMA_CH_TRIGSRC_TCF1_OVF_gc = (0xA6<<0), /* Timer/Counter F1 Overflow */ - DMA_CH_TRIGSRC_TCF1_ERR_gc = (0xA7<<0), /* Timer/Counter F1 Error */ - DMA_CH_TRIGSRC_TCF1_CCA_gc = (0xA8<<0), /* Timer/Counter F1 Compare or Capture A */ - DMA_CH_TRIGSRC_TCF1_CCB_gc = (0xA9<<0), /* Timer/Counter F1 Compare or Capture B */ - DMA_CH_TRIGSRC_SPIF_gc = (0xAA<<0), /* SPI F Transfer Complete */ - DMA_CH_TRIGSRC_USARTF0_RXC_gc = (0xAB<<0), /* USART F0 Receive Complete */ - DMA_CH_TRIGSRC_USARTF0_DRE_gc = (0xAC<<0), /* USART F0 Data Register Empty */ - DMA_CH_TRIGSRC_USARTF1_RXC_gc = (0xAE<<0), /* USART F1 Receive Complete */ - DMA_CH_TRIGSRC_USARTF1_DRE_gc = (0xAF<<0), /* USART F1 Data Register Empty */ -} DMA_CH_TRIGSRC_t; - -/* Double buffering mode */ -typedef enum DMA_DBUFMODE_enum -{ - DMA_DBUFMODE_DISABLED_gc = (0x00<<2), /* Double buffering disabled */ - DMA_DBUFMODE_CH01_gc = (0x01<<2), /* Double buffering enabled on channel 0/1 */ - DMA_DBUFMODE_CH23_gc = (0x02<<2), /* Double buffering enabled on channel 2/3 */ - DMA_DBUFMODE_CH01CH23_gc = (0x03<<2), /* Double buffering enabled on ch. 0/1 and ch. 2/3 */ -} DMA_DBUFMODE_t; - -/* Priority mode */ -typedef enum DMA_PRIMODE_enum -{ - DMA_PRIMODE_RR0123_gc = (0x00<<0), /* Round Robin */ - DMA_PRIMODE_CH0RR123_gc = (0x01<<0), /* Channel 0 > Round Robin on channel 1/2/3 */ - DMA_PRIMODE_CH01RR23_gc = (0x02<<0), /* Channel 0 > channel 1 > Round Robin on channel 2/3 */ - DMA_PRIMODE_CH0123_gc = (0x03<<0), /* Channel 0 > channel 1 > channel 2 > channel 3 */ -} DMA_PRIMODE_t; - -/* Interrupt level */ -typedef enum DMA_CH_ERRINTLVL_enum -{ - DMA_CH_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ - DMA_CH_ERRINTLVL_LO_gc = (0x01<<2), /* Low level */ - DMA_CH_ERRINTLVL_MED_gc = (0x02<<2), /* Medium level */ - DMA_CH_ERRINTLVL_HI_gc = (0x03<<2), /* High level */ -} DMA_CH_ERRINTLVL_t; - -/* Interrupt level */ -typedef enum DMA_CH_TRNINTLVL_enum -{ - DMA_CH_TRNINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ - DMA_CH_TRNINTLVL_LO_gc = (0x01<<0), /* Low level */ - DMA_CH_TRNINTLVL_MED_gc = (0x02<<0), /* Medium level */ - DMA_CH_TRNINTLVL_HI_gc = (0x03<<0), /* High level */ -} DMA_CH_TRNINTLVL_t; - - -/* --------------------------------------------------------------------------- -EVSYS - Event System --------------------------------------------------------------------------- -*/ - -/* Event System */ -typedef struct EVSYS_struct -{ - register8_t CH0MUX; /* Event Channel 0 Multiplexer */ - register8_t CH1MUX; /* Event Channel 1 Multiplexer */ - register8_t CH2MUX; /* Event Channel 2 Multiplexer */ - register8_t CH3MUX; /* Event Channel 3 Multiplexer */ - register8_t CH4MUX; /* Event Channel 4 Multiplexer */ - register8_t CH5MUX; /* Event Channel 5 Multiplexer */ - register8_t CH6MUX; /* Event Channel 6 Multiplexer */ - register8_t CH7MUX; /* Event Channel 7 Multiplexer */ - register8_t CH0CTRL; /* Channel 0 Control Register */ - register8_t CH1CTRL; /* Channel 1 Control Register */ - register8_t CH2CTRL; /* Channel 2 Control Register */ - register8_t CH3CTRL; /* Channel 3 Control Register */ - register8_t CH4CTRL; /* Channel 4 Control Register */ - register8_t CH5CTRL; /* Channel 5 Control Register */ - register8_t CH6CTRL; /* Channel 6 Control Register */ - register8_t CH7CTRL; /* Channel 7 Control Register */ - register8_t STROBE; /* Event Strobe */ - register8_t DATA; /* Event Data */ -} EVSYS_t; - -/* Quadrature Decoder Index Recognition Mode */ -typedef enum EVSYS_QDIRM_enum -{ - EVSYS_QDIRM_00_gc = (0x00<<5), /* QDPH0 = 0, QDPH90 = 0 */ - EVSYS_QDIRM_01_gc = (0x01<<5), /* QDPH0 = 0, QDPH90 = 1 */ - EVSYS_QDIRM_10_gc = (0x02<<5), /* QDPH0 = 1, QDPH90 = 0 */ - EVSYS_QDIRM_11_gc = (0x03<<5), /* QDPH0 = 1, QDPH90 = 1 */ -} EVSYS_QDIRM_t; - -/* Digital filter coefficient */ -typedef enum EVSYS_DIGFILT_enum -{ - EVSYS_DIGFILT_1SAMPLE_gc = (0x00<<0), /* 1 SAMPLE */ - EVSYS_DIGFILT_2SAMPLES_gc = (0x01<<0), /* 2 SAMPLES */ - EVSYS_DIGFILT_3SAMPLES_gc = (0x02<<0), /* 3 SAMPLES */ - EVSYS_DIGFILT_4SAMPLES_gc = (0x03<<0), /* 4 SAMPLES */ - EVSYS_DIGFILT_5SAMPLES_gc = (0x04<<0), /* 5 SAMPLES */ - EVSYS_DIGFILT_6SAMPLES_gc = (0x05<<0), /* 6 SAMPLES */ - EVSYS_DIGFILT_7SAMPLES_gc = (0x06<<0), /* 7 SAMPLES */ - EVSYS_DIGFILT_8SAMPLES_gc = (0x07<<0), /* 8 SAMPLES */ -} EVSYS_DIGFILT_t; - -/* Event Channel multiplexer input selection */ -typedef enum EVSYS_CHMUX_enum -{ - EVSYS_CHMUX_OFF_gc = (0x00<<0), /* Off */ - EVSYS_CHMUX_RTC_OVF_gc = (0x08<<0), /* RTC Overflow */ - EVSYS_CHMUX_RTC_CMP_gc = (0x09<<0), /* RTC Compare Match */ - EVSYS_CHMUX_ACA_CH0_gc = (0x10<<0), /* Analog Comparator A Channel 0 */ - EVSYS_CHMUX_ACA_CH1_gc = (0x11<<0), /* Analog Comparator A Channel 1 */ - EVSYS_CHMUX_ACA_WIN_gc = (0x12<<0), /* Analog Comparator A Window */ - EVSYS_CHMUX_ACB_CH0_gc = (0x13<<0), /* Analog Comparator B Channel 0 */ - EVSYS_CHMUX_ACB_CH1_gc = (0x14<<0), /* Analog Comparator B Channel 1 */ - EVSYS_CHMUX_ACB_WIN_gc = (0x15<<0), /* Analog Comparator B Window */ - EVSYS_CHMUX_ADCA_CH0_gc = (0x20<<0), /* ADC A Channel 0 */ - EVSYS_CHMUX_ADCA_CH1_gc = (0x21<<0), /* ADC A Channel 1 */ - EVSYS_CHMUX_ADCA_CH2_gc = (0x22<<0), /* ADC A Channel 2 */ - EVSYS_CHMUX_ADCA_CH3_gc = (0x23<<0), /* ADC A Channel 3 */ - EVSYS_CHMUX_ADCB_CH0_gc = (0x24<<0), /* ADC B Channel 0 */ - EVSYS_CHMUX_ADCB_CH1_gc = (0x25<<0), /* ADC B Channel 1 */ - EVSYS_CHMUX_ADCB_CH2_gc = (0x26<<0), /* ADC B Channel 2 */ - EVSYS_CHMUX_ADCB_CH3_gc = (0x27<<0), /* ADC B Channel 3 */ - EVSYS_CHMUX_PORTA_PIN0_gc = (0x50<<0), /* Port A, Pin0 */ - EVSYS_CHMUX_PORTA_PIN1_gc = (0x51<<0), /* Port A, Pin1 */ - EVSYS_CHMUX_PORTA_PIN2_gc = (0x52<<0), /* Port A, Pin2 */ - EVSYS_CHMUX_PORTA_PIN3_gc = (0x53<<0), /* Port A, Pin3 */ - EVSYS_CHMUX_PORTA_PIN4_gc = (0x54<<0), /* Port A, Pin4 */ - EVSYS_CHMUX_PORTA_PIN5_gc = (0x55<<0), /* Port A, Pin5 */ - EVSYS_CHMUX_PORTA_PIN6_gc = (0x56<<0), /* Port A, Pin6 */ - EVSYS_CHMUX_PORTA_PIN7_gc = (0x57<<0), /* Port A, Pin7 */ - EVSYS_CHMUX_PORTB_PIN0_gc = (0x58<<0), /* Port B, Pin0 */ - EVSYS_CHMUX_PORTB_PIN1_gc = (0x59<<0), /* Port B, Pin1 */ - EVSYS_CHMUX_PORTB_PIN2_gc = (0x5A<<0), /* Port B, Pin2 */ - EVSYS_CHMUX_PORTB_PIN3_gc = (0x5B<<0), /* Port B, Pin3 */ - EVSYS_CHMUX_PORTB_PIN4_gc = (0x5C<<0), /* Port B, Pin4 */ - EVSYS_CHMUX_PORTB_PIN5_gc = (0x5D<<0), /* Port B, Pin5 */ - EVSYS_CHMUX_PORTB_PIN6_gc = (0x5E<<0), /* Port B, Pin6 */ - EVSYS_CHMUX_PORTB_PIN7_gc = (0x5F<<0), /* Port B, Pin7 */ - EVSYS_CHMUX_PORTC_PIN0_gc = (0x60<<0), /* Port C, Pin0 */ - EVSYS_CHMUX_PORTC_PIN1_gc = (0x61<<0), /* Port C, Pin1 */ - EVSYS_CHMUX_PORTC_PIN2_gc = (0x62<<0), /* Port C, Pin2 */ - EVSYS_CHMUX_PORTC_PIN3_gc = (0x63<<0), /* Port C, Pin3 */ - EVSYS_CHMUX_PORTC_PIN4_gc = (0x64<<0), /* Port C, Pin4 */ - EVSYS_CHMUX_PORTC_PIN5_gc = (0x65<<0), /* Port C, Pin5 */ - EVSYS_CHMUX_PORTC_PIN6_gc = (0x66<<0), /* Port C, Pin6 */ - EVSYS_CHMUX_PORTC_PIN7_gc = (0x67<<0), /* Port C, Pin7 */ - EVSYS_CHMUX_PORTD_PIN0_gc = (0x68<<0), /* Port D, Pin0 */ - EVSYS_CHMUX_PORTD_PIN1_gc = (0x69<<0), /* Port D, Pin1 */ - EVSYS_CHMUX_PORTD_PIN2_gc = (0x6A<<0), /* Port D, Pin2 */ - EVSYS_CHMUX_PORTD_PIN3_gc = (0x6B<<0), /* Port D, Pin3 */ - EVSYS_CHMUX_PORTD_PIN4_gc = (0x6C<<0), /* Port D, Pin4 */ - EVSYS_CHMUX_PORTD_PIN5_gc = (0x6D<<0), /* Port D, Pin5 */ - EVSYS_CHMUX_PORTD_PIN6_gc = (0x6E<<0), /* Port D, Pin6 */ - EVSYS_CHMUX_PORTD_PIN7_gc = (0x6F<<0), /* Port D, Pin7 */ - EVSYS_CHMUX_PORTE_PIN0_gc = (0x70<<0), /* Port E, Pin0 */ - EVSYS_CHMUX_PORTE_PIN1_gc = (0x71<<0), /* Port E, Pin1 */ - EVSYS_CHMUX_PORTE_PIN2_gc = (0x72<<0), /* Port E, Pin2 */ - EVSYS_CHMUX_PORTE_PIN3_gc = (0x73<<0), /* Port E, Pin3 */ - EVSYS_CHMUX_PORTE_PIN4_gc = (0x74<<0), /* Port E, Pin4 */ - EVSYS_CHMUX_PORTE_PIN5_gc = (0x75<<0), /* Port E, Pin5 */ - EVSYS_CHMUX_PORTE_PIN6_gc = (0x76<<0), /* Port E, Pin6 */ - EVSYS_CHMUX_PORTE_PIN7_gc = (0x77<<0), /* Port E, Pin7 */ - EVSYS_CHMUX_PORTF_PIN0_gc = (0x78<<0), /* Port F, Pin0 */ - EVSYS_CHMUX_PORTF_PIN1_gc = (0x79<<0), /* Port F, Pin1 */ - EVSYS_CHMUX_PORTF_PIN2_gc = (0x7A<<0), /* Port F, Pin2 */ - EVSYS_CHMUX_PORTF_PIN3_gc = (0x7B<<0), /* Port F, Pin3 */ - EVSYS_CHMUX_PORTF_PIN4_gc = (0x7C<<0), /* Port F, Pin4 */ - EVSYS_CHMUX_PORTF_PIN5_gc = (0x7D<<0), /* Port F, Pin5 */ - EVSYS_CHMUX_PORTF_PIN6_gc = (0x7E<<0), /* Port F, Pin6 */ - EVSYS_CHMUX_PORTF_PIN7_gc = (0x7F<<0), /* Port F, Pin7 */ - EVSYS_CHMUX_PRESCALER_1_gc = (0x80<<0), /* Prescaler, divide by 1 */ - EVSYS_CHMUX_PRESCALER_2_gc = (0x81<<0), /* Prescaler, divide by 2 */ - EVSYS_CHMUX_PRESCALER_4_gc = (0x82<<0), /* Prescaler, divide by 4 */ - EVSYS_CHMUX_PRESCALER_8_gc = (0x83<<0), /* Prescaler, divide by 8 */ - EVSYS_CHMUX_PRESCALER_16_gc = (0x84<<0), /* Prescaler, divide by 16 */ - EVSYS_CHMUX_PRESCALER_32_gc = (0x85<<0), /* Prescaler, divide by 32 */ - EVSYS_CHMUX_PRESCALER_64_gc = (0x86<<0), /* Prescaler, divide by 64 */ - EVSYS_CHMUX_PRESCALER_128_gc = (0x87<<0), /* Prescaler, divide by 128 */ - EVSYS_CHMUX_PRESCALER_256_gc = (0x88<<0), /* Prescaler, divide by 256 */ - EVSYS_CHMUX_PRESCALER_512_gc = (0x89<<0), /* Prescaler, divide by 512 */ - EVSYS_CHMUX_PRESCALER_1024_gc = (0x8A<<0), /* Prescaler, divide by 1024 */ - EVSYS_CHMUX_PRESCALER_2048_gc = (0x8B<<0), /* Prescaler, divide by 2048 */ - EVSYS_CHMUX_PRESCALER_4096_gc = (0x8C<<0), /* Prescaler, divide by 4096 */ - EVSYS_CHMUX_PRESCALER_8192_gc = (0x8D<<0), /* Prescaler, divide by 8192 */ - EVSYS_CHMUX_PRESCALER_16384_gc = (0x8E<<0), /* Prescaler, divide by 16384 */ - EVSYS_CHMUX_PRESCALER_32768_gc = (0x8F<<0), /* Prescaler, divide by 32768 */ - EVSYS_CHMUX_TCC0_OVF_gc = (0xC0<<0), /* Timer/Counter C0 Overflow */ - EVSYS_CHMUX_TCC0_ERR_gc = (0xC1<<0), /* Timer/Counter C0 Error */ - EVSYS_CHMUX_TCC0_CCA_gc = (0xC4<<0), /* Timer/Counter C0 Compare or Capture A */ - EVSYS_CHMUX_TCC0_CCB_gc = (0xC5<<0), /* Timer/Counter C0 Compare or Capture B */ - EVSYS_CHMUX_TCC0_CCC_gc = (0xC6<<0), /* Timer/Counter C0 Compare or Capture C */ - EVSYS_CHMUX_TCC0_CCD_gc = (0xC7<<0), /* Timer/Counter C0 Compare or Capture D */ - EVSYS_CHMUX_TCC1_OVF_gc = (0xC8<<0), /* Timer/Counter C1 Overflow */ - EVSYS_CHMUX_TCC1_ERR_gc = (0xC9<<0), /* Timer/Counter C1 Error */ - EVSYS_CHMUX_TCC1_CCA_gc = (0xCC<<0), /* Timer/Counter C1 Compare or Capture A */ - EVSYS_CHMUX_TCC1_CCB_gc = (0xCD<<0), /* Timer/Counter C1 Compare or Capture B */ - EVSYS_CHMUX_TCD0_OVF_gc = (0xD0<<0), /* Timer/Counter D0 Overflow */ - EVSYS_CHMUX_TCD0_ERR_gc = (0xD1<<0), /* Timer/Counter D0 Error */ - EVSYS_CHMUX_TCD0_CCA_gc = (0xD4<<0), /* Timer/Counter D0 Compare or Capture A */ - EVSYS_CHMUX_TCD0_CCB_gc = (0xD5<<0), /* Timer/Counter D0 Compare or Capture B */ - EVSYS_CHMUX_TCD0_CCC_gc = (0xD6<<0), /* Timer/Counter D0 Compare or Capture C */ - EVSYS_CHMUX_TCD0_CCD_gc = (0xD7<<0), /* Timer/Counter D0 Compare or Capture D */ - EVSYS_CHMUX_TCD1_OVF_gc = (0xD8<<0), /* Timer/Counter D1 Overflow */ - EVSYS_CHMUX_TCD1_ERR_gc = (0xD9<<0), /* Timer/Counter D1 Error */ - EVSYS_CHMUX_TCD1_CCA_gc = (0xDC<<0), /* Timer/Counter D1 Compare or Capture A */ - EVSYS_CHMUX_TCD1_CCB_gc = (0xDD<<0), /* Timer/Counter D1 Compare or Capture B */ - EVSYS_CHMUX_TCE0_OVF_gc = (0xE0<<0), /* Timer/Counter E0 Overflow */ - EVSYS_CHMUX_TCE0_ERR_gc = (0xE1<<0), /* Timer/Counter E0 Error */ - EVSYS_CHMUX_TCE0_CCA_gc = (0xE4<<0), /* Timer/Counter E0 Compare or Capture A */ - EVSYS_CHMUX_TCE0_CCB_gc = (0xE5<<0), /* Timer/Counter E0 Compare or Capture B */ - EVSYS_CHMUX_TCE0_CCC_gc = (0xE6<<0), /* Timer/Counter E0 Compare or Capture C */ - EVSYS_CHMUX_TCE0_CCD_gc = (0xE7<<0), /* Timer/Counter E0 Compare or Capture D */ - EVSYS_CHMUX_TCE1_OVF_gc = (0xE8<<0), /* Timer/Counter E1 Overflow */ - EVSYS_CHMUX_TCE1_ERR_gc = (0xE9<<0), /* Timer/Counter E1 Error */ - EVSYS_CHMUX_TCE1_CCA_gc = (0xEC<<0), /* Timer/Counter E1 Compare or Capture A */ - EVSYS_CHMUX_TCE1_CCB_gc = (0xED<<0), /* Timer/Counter E1 Compare or Capture B */ - EVSYS_CHMUX_TCF0_OVF_gc = (0xF0<<0), /* Timer/Counter F0 Overflow */ - EVSYS_CHMUX_TCF0_ERR_gc = (0xF1<<0), /* Timer/Counter F0 Error */ - EVSYS_CHMUX_TCF0_CCA_gc = (0xF4<<0), /* Timer/Counter F0 Compare or Capture A */ - EVSYS_CHMUX_TCF0_CCB_gc = (0xF5<<0), /* Timer/Counter F0 Compare or Capture B */ - EVSYS_CHMUX_TCF0_CCC_gc = (0xF6<<0), /* Timer/Counter F0 Compare or Capture C */ - EVSYS_CHMUX_TCF0_CCD_gc = (0xF7<<0), /* Timer/Counter F0 Compare or Capture D */ - EVSYS_CHMUX_TCF1_OVF_gc = (0xF8<<0), /* Timer/Counter F1 Overflow */ - EVSYS_CHMUX_TCF1_ERR_gc = (0xF9<<0), /* Timer/Counter F1 Error */ - EVSYS_CHMUX_TCF1_CCA_gc = (0xFC<<0), /* Timer/Counter F1 Compare or Capture A */ - EVSYS_CHMUX_TCF1_CCB_gc = (0xFD<<0), /* Timer/Counter F1 Compare or Capture B */ -} EVSYS_CHMUX_t; - - -/* --------------------------------------------------------------------------- -NVM - Non Volatile Memory Controller --------------------------------------------------------------------------- -*/ - -/* Non-volatile Memory Controller */ -typedef struct NVM_struct -{ - register8_t ADDR0; /* Address Register 0 */ - register8_t ADDR1; /* Address Register 1 */ - register8_t ADDR2; /* Address Register 2 */ - register8_t reserved_0x03; - register8_t DATA0; /* Data Register 0 */ - register8_t DATA1; /* Data Register 1 */ - register8_t DATA2; /* Data Register 2 */ - register8_t reserved_0x07; - register8_t reserved_0x08; - register8_t reserved_0x09; - register8_t CMD; /* Command */ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t INTCTRL; /* Interrupt Control */ - register8_t reserved_0x0E; - register8_t STATUS; /* Status */ - register8_t LOCK_BITS; /* Lock Bits */ -} NVM_t; - -/* --------------------------------------------------------------------------- -NVM - Non Volatile Memory Controller --------------------------------------------------------------------------- -*/ - -/* Lock Bits */ -typedef struct NVM_LOCKBITS_struct -{ - register8_t LOCKBITS; /* Lock Bits */ -} NVM_LOCKBITS_t; - -/* --------------------------------------------------------------------------- -NVM - Non Volatile Memory Controller --------------------------------------------------------------------------- -*/ - -/* Fuses */ -typedef struct NVM_FUSES_struct -{ - register8_t FUSEBYTE0; /* User ID */ - register8_t FUSEBYTE1; /* Watchdog Configuration */ - register8_t FUSEBYTE2; /* Reset Configuration */ - register8_t reserved_0x03; - register8_t FUSEBYTE4; /* Start-up Configuration */ - register8_t FUSEBYTE5; /* EESAVE and BOD Level */ -} NVM_FUSES_t; - -/* --------------------------------------------------------------------------- -NVM - Non Volatile Memory Controller --------------------------------------------------------------------------- -*/ - -/* Production Signatures */ -typedef struct NVM_PROD_SIGNATURES_struct -{ - register8_t RCOSC2M; /* RCOSC 2MHz Calibration Value */ - register8_t reserved_0x01; - register8_t RCOSC32K; /* RCOSC 32kHz Calibration Value */ - register8_t RCOSC32M; /* RCOSC 32MHz Calibration Value */ - register8_t reserved_0x04; - register8_t reserved_0x05; - register8_t reserved_0x06; - register8_t reserved_0x07; - register8_t LOTNUM0; /* Lot Number Byte 0, ASCII */ - register8_t LOTNUM1; /* Lot Number Byte 1, ASCII */ - register8_t LOTNUM2; /* Lot Number Byte 2, ASCII */ - register8_t LOTNUM3; /* Lot Number Byte 3, ASCII */ - register8_t LOTNUM4; /* Lot Number Byte 4, ASCII */ - register8_t LOTNUM5; /* Lot Number Byte 5, ASCII */ - register8_t reserved_0x0E; - register8_t reserved_0x0F; - register8_t WAFNUM; /* Wafer Number */ - register8_t reserved_0x11; - register8_t COORDX0; /* Wafer Coordinate X Byte 0 */ - register8_t COORDX1; /* Wafer Coordinate X Byte 1 */ - register8_t COORDY0; /* Wafer Coordinate Y Byte 0 */ - register8_t COORDY1; /* Wafer Coordinate Y Byte 1 */ - register8_t reserved_0x16; - register8_t reserved_0x17; - register8_t reserved_0x18; - register8_t reserved_0x19; - register8_t reserved_0x1A; - register8_t reserved_0x1B; - register8_t reserved_0x1C; - register8_t reserved_0x1D; - register8_t reserved_0x1E; - register8_t reserved_0x1F; - register8_t ADCACAL0; /* ADCA Calibration Byte 0 */ - register8_t ADCACAL1; /* ADCA Calibration Byte 1 */ - register8_t reserved_0x22; - register8_t reserved_0x23; - register8_t ADCBCAL0; /* ADCB Calibration Byte 0 */ - register8_t ADCBCAL1; /* ADCB Calibration Byte 1 */ - register8_t reserved_0x26; - register8_t reserved_0x27; - register8_t reserved_0x28; - register8_t reserved_0x29; - register8_t reserved_0x2A; - register8_t reserved_0x2B; - register8_t reserved_0x2C; - register8_t reserved_0x2D; - register8_t TEMPSENSE0; /* Temperature Sensor Calibration Byte 0 */ - register8_t TEMPSENSE1; /* Temperature Sensor Calibration Byte 0 */ - register8_t DACAOFFCAL; /* DACA Calibration Byte 0 */ - register8_t DACAGAINCAL; /* DACA Calibration Byte 1 */ - register8_t DACBOFFCAL; /* DACB Calibration Byte 0 */ - register8_t DACBGAINCAL; /* DACB Calibration Byte 1 */ - register8_t reserved_0x34; - register8_t reserved_0x35; - register8_t reserved_0x36; - register8_t reserved_0x37; - register8_t reserved_0x38; - register8_t reserved_0x39; - register8_t reserved_0x3A; - register8_t reserved_0x3B; - register8_t reserved_0x3C; - register8_t reserved_0x3D; - register8_t reserved_0x3E; -} NVM_PROD_SIGNATURES_t; - -/* NVM Command */ -typedef enum NVM_CMD_enum -{ - NVM_CMD_NO_OPERATION_gc = (0x00<<0), /* Noop/Ordinary LPM */ - NVM_CMD_READ_CALIB_ROW_gc = (0x02<<0), /* Read calibration row */ - NVM_CMD_READ_USER_SIG_ROW_gc = (0x01<<0), /* Read user signature row */ - NVM_CMD_READ_EEPROM_gc = (0x06<<0), /* Read EEPROM */ - NVM_CMD_READ_FUSES_gc = (0x07<<0), /* Read fuse byte */ - NVM_CMD_WRITE_LOCK_BITS_gc = (0x08<<0), /* Write lock bits */ - NVM_CMD_ERASE_USER_SIG_ROW_gc = (0x18<<0), /* Erase user signature row */ - NVM_CMD_WRITE_USER_SIG_ROW_gc = (0x1A<<0), /* Write user signature row */ - NVM_CMD_ERASE_APP_gc = (0x20<<0), /* Erase Application Section */ - NVM_CMD_ERASE_APP_PAGE_gc = (0x22<<0), /* Erase Application Section page */ - NVM_CMD_LOAD_FLASH_BUFFER_gc = (0x23<<0), /* Load Flash page buffer */ - NVM_CMD_WRITE_APP_PAGE_gc = (0x24<<0), /* Write Application Section page */ - NVM_CMD_ERASE_WRITE_APP_PAGE_gc = (0x25<<0), /* Erase-and-write Application Section page */ - NVM_CMD_ERASE_FLASH_BUFFER_gc = (0x26<<0), /* Erase/flush Flash page buffer */ - NVM_CMD_ERASE_BOOT_PAGE_gc = (0x2A<<0), /* Erase Boot Section page */ - NVM_CMD_WRITE_BOOT_PAGE_gc = (0x2C<<0), /* Write Boot Section page */ - NVM_CMD_ERASE_WRITE_BOOT_PAGE_gc = (0x2D<<0), /* Erase-and-write Boot Section page */ - NVM_CMD_ERASE_EEPROM_gc = (0x30<<0), /* Erase EEPROM */ - NVM_CMD_ERASE_EEPROM_PAGE_gc = (0x32<<0), /* Erase EEPROM page */ - NVM_CMD_LOAD_EEPROM_BUFFER_gc = (0x33<<0), /* Load EEPROM page buffer */ - NVM_CMD_WRITE_EEPROM_PAGE_gc = (0x34<<0), /* Write EEPROM page */ - NVM_CMD_ERASE_WRITE_EEPROM_PAGE_gc = (0x35<<0), /* Erase-and-write EEPROM page */ - NVM_CMD_ERASE_EEPROM_BUFFER_gc = (0x36<<0), /* Erase/flush EEPROM page buffer */ - NVM_CMD_APP_CRC_gc = (0x38<<0), /* Generate Application section CRC */ - NVM_CMD_BOOT_CRC_gc = (0x39<<0), /* Generate Boot Section CRC */ - NVM_CMD_FLASH_RANGE_CRC_gc = (0x3A<<0), /* Generate Flash Range CRC */ -} NVM_CMD_t; - -/* SPM ready interrupt level */ -typedef enum NVM_SPMLVL_enum -{ - NVM_SPMLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ - NVM_SPMLVL_LO_gc = (0x01<<2), /* Low level */ - NVM_SPMLVL_MED_gc = (0x02<<2), /* Medium level */ - NVM_SPMLVL_HI_gc = (0x03<<2), /* High level */ -} NVM_SPMLVL_t; - -/* EEPROM ready interrupt level */ -typedef enum NVM_EELVL_enum -{ - NVM_EELVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ - NVM_EELVL_LO_gc = (0x01<<0), /* Low level */ - NVM_EELVL_MED_gc = (0x02<<0), /* Medium level */ - NVM_EELVL_HI_gc = (0x03<<0), /* High level */ -} NVM_EELVL_t; - -/* Boot lock bits - boot setcion */ -typedef enum NVM_BLBB_enum -{ - NVM_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ - NVM_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ - NVM_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ - NVM_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ -} NVM_BLBB_t; - -/* Boot lock bits - application section */ -typedef enum NVM_BLBA_enum -{ - NVM_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ - NVM_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ - NVM_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ - NVM_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ -} NVM_BLBA_t; - -/* Boot lock bits - application table section */ -typedef enum NVM_BLBAT_enum -{ - NVM_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ - NVM_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ - NVM_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ - NVM_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ -} NVM_BLBAT_t; - -/* Lock bits */ -typedef enum NVM_LB_enum -{ - NVM_LB_NOLOCK_gc = (0x03<<0), /* No locks */ - NVM_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ - NVM_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ -} NVM_LB_t; - -/* Boot Loader Section Reset Vector */ -typedef enum BOOTRST_enum -{ - BOOTRST_BOOTLDR_gc = (0x00<<6), /* Boot Loader Reset */ - BOOTRST_APPLICATION_gc = (0x01<<6), /* Application Reset */ -} BOOTRST_t; - -/* BOD operation */ -typedef enum BOD_enum -{ - BOD_INSAMPLEDMODE_gc = (0x01<<0), /* BOD enabled in sampled mode */ - BOD_CONTINOUSLY_gc = (0x02<<0), /* BOD enabled continuously */ - BOD_DISABLED_gc = (0x03<<0), /* BOD Disabled */ -} BOD_t; - -/* Watchdog (Window) Timeout Period */ -typedef enum WD_enum -{ - WD_8CLK_gc = (0x00<<4), /* 8 cycles (8ms @ 3.3V) */ - WD_16CLK_gc = (0x01<<4), /* 16 cycles (16ms @ 3.3V) */ - WD_32CLK_gc = (0x02<<4), /* 32 cycles (32ms @ 3.3V) */ - WD_64CLK_gc = (0x03<<4), /* 64 cycles (64ms @ 3.3V) */ - WD_128CLK_gc = (0x04<<4), /* 128 cycles (0.125s @ 3.3V) */ - WD_256CLK_gc = (0x05<<4), /* 256 cycles (0.25s @ 3.3V) */ - WD_512CLK_gc = (0x06<<4), /* 512 cycles (0.5s @ 3.3V) */ - WD_1KCLK_gc = (0x07<<4), /* 1K cycles (1s @ 3.3V) */ - WD_2KCLK_gc = (0x08<<4), /* 2K cycles (2s @ 3.3V) */ - WD_4KCLK_gc = (0x09<<4), /* 4K cycles (4s @ 3.3V) */ - WD_8KCLK_gc = (0x0A<<4), /* 8K cycles (8s @ 3.3V) */ -} WD_t; - -/* Start-up Time */ -typedef enum SUT_enum -{ - SUT_0MS_gc = (0x03<<2), /* 0 ms */ - SUT_4MS_gc = (0x01<<2), /* 4 ms */ - SUT_64MS_gc = (0x00<<2), /* 64 ms */ -} SUT_t; - -/* Brown Out Detection Voltage Level */ -typedef enum BODLVL_enum -{ - BODLVL_1V6_gc = (0x07<<0), /* 1.6 V */ - BODLVL_1V9_gc = (0x06<<0), /* 1.9 V */ - BODLVL_2V1_gc = (0x05<<0), /* 2.1 V */ - BODLVL_2V4_gc = (0x04<<0), /* 2.4 V */ - BODLVL_2V7_gc = (0x03<<0), /* 2.7 V */ - BODLVL_3V0_gc = (0x02<<0), /* 3.0 V */ - BODLVL_3V2_gc = (0x01<<0), /* 3.2 V */ - BODLVL_3V5_gc = (0x00<<0), /* 3.5 V */ -} BODLVL_t; - - -/* --------------------------------------------------------------------------- -AC - Analog Comparator --------------------------------------------------------------------------- -*/ - -/* Analog Comparator */ -typedef struct AC_struct -{ - register8_t AC0CTRL; /* Comparator 0 Control */ - register8_t AC1CTRL; /* Comparator 1 Control */ - register8_t AC0MUXCTRL; /* Comparator 0 MUX Control */ - register8_t AC1MUXCTRL; /* Comparator 1 MUX Control */ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t WINCTRL; /* Window Mode Control */ - register8_t STATUS; /* Status */ -} AC_t; - -/* Interrupt mode */ -typedef enum AC_INTMODE_enum -{ - AC_INTMODE_BOTHEDGES_gc = (0x00<<6), /* Interrupt on both edges */ - AC_INTMODE_FALLING_gc = (0x02<<6), /* Interrupt on falling edge */ - AC_INTMODE_RISING_gc = (0x03<<6), /* Interrupt on rising edge */ -} AC_INTMODE_t; - -/* Interrupt level */ -typedef enum AC_INTLVL_enum -{ - AC_INTLVL_OFF_gc = (0x00<<4), /* Interrupt disabled */ - AC_INTLVL_LO_gc = (0x01<<4), /* Low level */ - AC_INTLVL_MED_gc = (0x02<<4), /* Medium level */ - AC_INTLVL_HI_gc = (0x03<<4), /* High level */ -} AC_INTLVL_t; - -/* Hysteresis mode selection */ -typedef enum AC_HYSMODE_enum -{ - AC_HYSMODE_NO_gc = (0x00<<1), /* No hysteresis */ - AC_HYSMODE_SMALL_gc = (0x01<<1), /* Small hysteresis */ - AC_HYSMODE_LARGE_gc = (0x02<<1), /* Large hysteresis */ -} AC_HYSMODE_t; - -/* Positive input multiplexer selection */ -typedef enum AC_MUXPOS_enum -{ - AC_MUXPOS_PIN0_gc = (0x00<<3), /* Pin 0 */ - AC_MUXPOS_PIN1_gc = (0x01<<3), /* Pin 1 */ - AC_MUXPOS_PIN2_gc = (0x02<<3), /* Pin 2 */ - AC_MUXPOS_PIN3_gc = (0x03<<3), /* Pin 3 */ - AC_MUXPOS_PIN4_gc = (0x04<<3), /* Pin 4 */ - AC_MUXPOS_PIN5_gc = (0x05<<3), /* Pin 5 */ - AC_MUXPOS_PIN6_gc = (0x06<<3), /* Pin 6 */ - AC_MUXPOS_DAC_gc = (0x07<<3), /* DAC output */ -} AC_MUXPOS_t; - -/* Negative input multiplexer selection */ -typedef enum AC_MUXNEG_enum -{ - AC_MUXNEG_PIN0_gc = (0x00<<0), /* Pin 0 */ - AC_MUXNEG_PIN1_gc = (0x01<<0), /* Pin 1 */ - AC_MUXNEG_PIN3_gc = (0x02<<0), /* Pin 3 */ - AC_MUXNEG_PIN5_gc = (0x03<<0), /* Pin 5 */ - AC_MUXNEG_PIN7_gc = (0x04<<0), /* Pin 7 */ - AC_MUXNEG_DAC_gc = (0x05<<0), /* DAC output */ - AC_MUXNEG_BANDGAP_gc = (0x06<<0), /* Bandgap Reference */ - AC_MUXNEG_SCALER_gc = (0x07<<0), /* Internal voltage scaler */ -} AC_MUXNEG_t; - -/* Windows interrupt mode */ -typedef enum AC_WINTMODE_enum -{ - AC_WINTMODE_ABOVE_gc = (0x00<<2), /* Interrupt on above window */ - AC_WINTMODE_INSIDE_gc = (0x01<<2), /* Interrupt on inside window */ - AC_WINTMODE_BELOW_gc = (0x02<<2), /* Interrupt on below window */ - AC_WINTMODE_OUTSIDE_gc = (0x03<<2), /* Interrupt on outside window */ -} AC_WINTMODE_t; - -/* Window interrupt level */ -typedef enum AC_WINTLVL_enum -{ - AC_WINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ - AC_WINTLVL_LO_gc = (0x01<<0), /* Low priority */ - AC_WINTLVL_MED_gc = (0x02<<0), /* Medium priority */ - AC_WINTLVL_HI_gc = (0x03<<0), /* High priority */ -} AC_WINTLVL_t; - -/* Window mode state */ -typedef enum AC_WSTATE_enum -{ - AC_WSTATE_ABOVE_gc = (0x00<<6), /* Signal above window */ - AC_WSTATE_INSIDE_gc = (0x01<<6), /* Signal inside window */ - AC_WSTATE_BELOW_gc = (0x02<<6), /* Signal below window */ -} AC_WSTATE_t; - - -/* --------------------------------------------------------------------------- -ADC - Analog/Digital Converter --------------------------------------------------------------------------- -*/ - -/* ADC Channel */ -typedef struct ADC_CH_struct -{ - register8_t CTRL; /* Control Register */ - register8_t MUXCTRL; /* MUX Control */ - register8_t INTCTRL; /* Channel Interrupt Control */ - register8_t INTFLAGS; /* Interrupt Flags */ - _WORDREGISTER(RES); /* Channel Result */ - register8_t reserved_0x6; - register8_t reserved_0x7; -} ADC_CH_t; - -/* --------------------------------------------------------------------------- -ADC - Analog/Digital Converter --------------------------------------------------------------------------- -*/ - -/* Analog-to-Digital Converter */ -typedef struct ADC_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t REFCTRL; /* Reference Control */ - register8_t EVCTRL; /* Event Control */ - register8_t PRESCALER; /* Clock Prescaler */ - register8_t reserved_0x05; - register8_t INTFLAGS; /* Interrupt Flags */ - register8_t reserved_0x07; - register8_t reserved_0x08; - register8_t reserved_0x09; - register8_t reserved_0x0A; - register8_t reserved_0x0B; - _WORDREGISTER(CAL); /* Calibration Value */ - register8_t reserved_0x0E; - register8_t reserved_0x0F; - _WORDREGISTER(CH0RES); /* Channel 0 Result */ - _WORDREGISTER(CH1RES); /* Channel 1 Result */ - _WORDREGISTER(CH2RES); /* Channel 2 Result */ - _WORDREGISTER(CH3RES); /* Channel 3 Result */ - _WORDREGISTER(CMP); /* Compare Value */ - register8_t reserved_0x1A; - register8_t reserved_0x1B; - register8_t reserved_0x1C; - register8_t reserved_0x1D; - register8_t reserved_0x1E; - register8_t reserved_0x1F; - ADC_CH_t CH0; /* ADC Channel 0 */ - ADC_CH_t CH1; /* ADC Channel 1 */ - ADC_CH_t CH2; /* ADC Channel 2 */ - ADC_CH_t CH3; /* ADC Channel 3 */ -} ADC_t; - -/* Positive input multiplexer selection */ -typedef enum ADC_CH_MUXPOS_enum -{ - ADC_CH_MUXPOS_PIN0_gc = (0x00<<3), /* Input pin 0 */ - ADC_CH_MUXPOS_PIN1_gc = (0x01<<3), /* Input pin 1 */ - ADC_CH_MUXPOS_PIN2_gc = (0x02<<3), /* Input pin 2 */ - ADC_CH_MUXPOS_PIN3_gc = (0x03<<3), /* Input pin 3 */ - ADC_CH_MUXPOS_PIN4_gc = (0x04<<3), /* Input pin 4 */ - ADC_CH_MUXPOS_PIN5_gc = (0x05<<3), /* Input pin 5 */ - ADC_CH_MUXPOS_PIN6_gc = (0x06<<3), /* Input pin 6 */ - ADC_CH_MUXPOS_PIN7_gc = (0x07<<3), /* Input pin 7 */ - ADC_CH_MUXPOS_PIN8_gc = (0x08<<3), /* Input pin 8 */ - ADC_CH_MUXPOS_PIN9_gc = (0x09<<3), /* Input pin 9 */ - ADC_CH_MUXPOS_PIN10_gc = (0x10<<3), /* Input pin 10 */ - ADC_CH_MUXPOS_PIN11_gc = (0x11<<3), /* Input pin 11 */ -} ADC_CH_MUXPOS_t; - -/* Internal input multiplexer selections */ -typedef enum ADC_CH_MUXINT_enum -{ - ADC_CH_MUXINT_TEMP_gc = (0x00<<3), /* Temperature Reference */ - ADC_CH_MUXINT_BANDGAP_gc = (0x01<<3), /* Bandgap Reference */ - ADC_CH_MUXINT_SCALEDVCC_gc = (0x02<<3), /* 1/10 scaled VCC */ - ADC_CH_MUXINT_DAC_gc = (0x03<<3), /* DAC output */ -} ADC_CH_MUXINT_t; - -/* Negative input multiplexer selection */ -typedef enum ADC_CH_MUXNEG_enum -{ - ADC_CH_MUXNEG_PIN0_gc = (0x00<<0), /* Input pin 0 */ - ADC_CH_MUXNEG_PIN1_gc = (0x01<<0), /* Input pin 1 */ - ADC_CH_MUXNEG_PIN2_gc = (0x02<<0), /* Input pin 2 */ - ADC_CH_MUXNEG_PIN3_gc = (0x03<<0), /* Input pin 3 */ - ADC_CH_MUXNEG_PIN4_gc = (0x04<<0), /* Input pin 4 */ - ADC_CH_MUXNEG_PIN5_gc = (0x05<<0), /* Input pin 5 */ - ADC_CH_MUXNEG_PIN6_gc = (0x06<<0), /* Input pin 6 */ - ADC_CH_MUXNEG_PIN7_gc = (0x07<<0), /* Input pin 7 */ -} ADC_CH_MUXNEG_t; - -/* Input mode */ -typedef enum ADC_CH_INPUTMODE_enum -{ - ADC_CH_INPUTMODE_INTERNAL_gc = (0x00<<0), /* Internal inputs, no gain */ - ADC_CH_INPUTMODE_SINGLEENDED_gc = (0x01<<0), /* Single-ended input, no gain */ - ADC_CH_INPUTMODE_DIFF_gc = (0x02<<0), /* Differential input, no gain */ - ADC_CH_INPUTMODE_DIFFWGAIN_gc = (0x03<<0), /* Differential input, with gain */ -} ADC_CH_INPUTMODE_t; - -/* Gain factor */ -typedef enum ADC_CH_GAIN_enum -{ - ADC_CH_GAIN_1X_gc = (0x00<<2), /* 1x gain */ - ADC_CH_GAIN_2X_gc = (0x01<<2), /* 2x gain */ - ADC_CH_GAIN_4X_gc = (0x02<<2), /* 4x gain */ - ADC_CH_GAIN_8X_gc = (0x03<<2), /* 8x gain */ - ADC_CH_GAIN_16X_gc = (0x04<<2), /* 16x gain */ - ADC_CH_GAIN_32X_gc = (0x05<<2), /* 32x gain */ - ADC_CH_GAIN_64X_gc = (0x06<<2), /* 64x gain */ -} ADC_CH_GAIN_t; - -/* Conversion result resolution */ -typedef enum ADC_RESOLUTION_enum -{ - ADC_RESOLUTION_12BIT_gc = (0x00<<1), /* 12-bit right-adjusted result */ - ADC_RESOLUTION_8BIT_gc = (0x02<<1), /* 8-bit right-adjusted result */ - ADC_RESOLUTION_LEFT12BIT_gc = (0x03<<1), /* 12-bit left-adjusted result */ -} ADC_RESOLUTION_t; - -/* Voltage reference selection */ -typedef enum ADC_REFSEL_enum -{ - ADC_REFSEL_INT1V_gc = (0x00<<4), /* Internal 1V */ - ADC_REFSEL_VCC_gc = (0x01<<4), /* Internal VCC / 1.6V */ - ADC_REFSEL_AREFA_gc = (0x02<<4), /* External reference on PORT A */ - ADC_REFSEL_AREFB_gc = (0x03<<4), /* External reference on PORT B */ -} ADC_REFSEL_t; - -/* Channel sweep selection */ -typedef enum ADC_SWEEP_enum -{ - ADC_SWEEP_0_gc = (0x00<<6), /* ADC Channel 0 */ - ADC_SWEEP_01_gc = (0x01<<6), /* ADC Channel 0,1 */ - ADC_SWEEP_012_gc = (0x02<<6), /* ADC Channel 0,1,2 */ - ADC_SWEEP_0123_gc = (0x03<<6), /* ADC Channel 0,1,2,3 */ -} ADC_SWEEP_t; - -/* Event channel input selection */ -typedef enum ADC_EVSEL_enum -{ - ADC_EVSEL_0123_gc = (0x00<<3), /* Event Channel 0,1,2,3 */ - ADC_EVSEL_1234_gc = (0x01<<3), /* Event Channel 1,2,3,4 */ - ADC_EVSEL_2345_gc = (0x02<<3), /* Event Channel 2,3,4,5 */ - ADC_EVSEL_3456_gc = (0x03<<3), /* Event Channel 3,4,5,6 */ - ADC_EVSEL_4567_gc = (0x04<<3), /* Event Channel 4,5,6,7 */ - ADC_EVSEL_567_gc = (0x05<<3), /* Event Channel 5,6,7 */ - ADC_EVSEL_67_gc = (0x06<<3), /* Event Channel 6,7 */ - ADC_EVSEL_7_gc = (0x07<<3), /* Event Channel 7 */ -} ADC_EVSEL_t; - -/* Event action selection */ -typedef enum ADC_EVACT_enum -{ - ADC_EVACT_NONE_gc = (0x00<<0), /* No event action */ - ADC_EVACT_CH0_gc = (0x01<<0), /* First event triggers channel 0 */ - ADC_EVACT_CH01_gc = (0x02<<0), /* First two events trigger channel 0,1 */ - ADC_EVACT_CH012_gc = (0x03<<0), /* First three events trigger channel 0,1,2 */ - ADC_EVACT_CH0123_gc = (0x04<<0), /* Events trigger channel 0,1,2,3 */ - ADC_EVACT_SWEEP_gc = (0x05<<0), /* First event triggers sweep */ - ADC_EVACT_SYNCHSWEEP_gc = (0x06<<0), /* First event triggers synchronized sweep */ -} ADC_EVACT_t; - -/* Interupt mode */ -typedef enum ADC_CH_INTMODE_enum -{ - ADC_CH_INTMODE_COMPLETE_gc = (0x00<<2), /* Interrupt on conversion complete */ - ADC_CH_INTMODE_BELOW_gc = (0x01<<2), /* Interrupt on result below compare value */ - ADC_CH_INTMODE_ABOVE_gc = (0x03<<2), /* Interrupt on result above compare value */ -} ADC_CH_INTMODE_t; - -/* Interrupt level */ -typedef enum ADC_CH_INTLVL_enum -{ - ADC_CH_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ - ADC_CH_INTLVL_LO_gc = (0x01<<0), /* Low level */ - ADC_CH_INTLVL_MED_gc = (0x02<<0), /* Medium level */ - ADC_CH_INTLVL_HI_gc = (0x03<<0), /* High level */ -} ADC_CH_INTLVL_t; - -/* DMA request selection */ -typedef enum ADC_DMASEL_enum -{ - ADC_DMASEL_OFF_gc = (0x00<<6), /* Combined DMA request OFF */ - ADC_DMASEL_CH01_gc = (0x01<<6), /* ADC Channel 0 or 1 */ - ADC_DMASEL_CH012_gc = (0x02<<6), /* ADC Channel 0 or 1 or 2 */ - ADC_DMASEL_CH0123_gc = (0x03<<6), /* ADC Channel 0 or 1 or 2 or 3 */ -} ADC_DMASEL_t; - -/* Clock prescaler */ -typedef enum ADC_PRESCALER_enum -{ - ADC_PRESCALER_DIV4_gc = (0x00<<0), /* Divide clock by 4 */ - ADC_PRESCALER_DIV8_gc = (0x01<<0), /* Divide clock by 8 */ - ADC_PRESCALER_DIV16_gc = (0x02<<0), /* Divide clock by 16 */ - ADC_PRESCALER_DIV32_gc = (0x03<<0), /* Divide clock by 32 */ - ADC_PRESCALER_DIV64_gc = (0x04<<0), /* Divide clock by 64 */ - ADC_PRESCALER_DIV128_gc = (0x05<<0), /* Divide clock by 128 */ - ADC_PRESCALER_DIV256_gc = (0x06<<0), /* Divide clock by 256 */ - ADC_PRESCALER_DIV512_gc = (0x07<<0), /* Divide clock by 512 */ -} ADC_PRESCALER_t; - - -/* --------------------------------------------------------------------------- -DAC - Digital/Analog Converter --------------------------------------------------------------------------- -*/ - -/* Digital-to-Analog Converter */ -typedef struct DAC_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t CTRLC; /* Control Register C */ - register8_t EVCTRL; /* Event Input Control */ - register8_t TIMCTRL; /* Timing Control */ - register8_t STATUS; /* Status */ - register8_t reserved_0x06; - register8_t reserved_0x07; - register8_t GAINCAL; /* Gain Calibration */ - register8_t OFFSETCAL; /* Offset Calibration */ - register8_t reserved_0x0A; - register8_t reserved_0x0B; - register8_t reserved_0x0C; - register8_t reserved_0x0D; - register8_t reserved_0x0E; - register8_t reserved_0x0F; - register8_t reserved_0x10; - register8_t reserved_0x11; - register8_t reserved_0x12; - register8_t reserved_0x13; - register8_t reserved_0x14; - register8_t reserved_0x15; - register8_t reserved_0x16; - register8_t reserved_0x17; - _WORDREGISTER(CH0DATA); /* Channel 0 Data */ - _WORDREGISTER(CH1DATA); /* Channel 1 Data */ -} DAC_t; - -/* Output channel selection */ -typedef enum DAC_CHSEL_enum -{ - DAC_CHSEL_SINGLE_gc = (0x00<<5), /* Single channel operation (Channel A only) */ - DAC_CHSEL_DUAL_gc = (0x02<<5), /* Dual channel operation (S/H on both channels) */ -} DAC_CHSEL_t; - -/* Reference voltage selection */ -typedef enum DAC_REFSEL_enum -{ - DAC_REFSEL_INT1V_gc = (0x00<<3), /* Internal 1V */ - DAC_REFSEL_AVCC_gc = (0x01<<3), /* Analog supply voltage */ - DAC_REFSEL_AREFA_gc = (0x02<<3), /* External reference on AREF on PORTA */ - DAC_REFSEL_AREFB_gc = (0x03<<3), /* External reference on AREF on PORTB */ -} DAC_REFSEL_t; - -/* Event channel selection */ -typedef enum DAC_EVSEL_enum -{ - DAC_EVSEL_0_gc = (0x00<<0), /* Event Channel 0 */ - DAC_EVSEL_1_gc = (0x01<<0), /* Event Channel 1 */ - DAC_EVSEL_2_gc = (0x02<<0), /* Event Channel 2 */ - DAC_EVSEL_3_gc = (0x03<<0), /* Event Channel 3 */ - DAC_EVSEL_4_gc = (0x04<<0), /* Event Channel 4 */ - DAC_EVSEL_5_gc = (0x05<<0), /* Event Channel 5 */ - DAC_EVSEL_6_gc = (0x06<<0), /* Event Channel 6 */ - DAC_EVSEL_7_gc = (0x07<<0), /* Event Channel 7 */ -} DAC_EVSEL_t; - -/* Conversion interval */ -typedef enum DAC_CONINTVAL_enum -{ - DAC_CONINTVAL_1CLK_gc = (0x00<<4), /* 1 CLK / 2 CLK in S/H mode */ - DAC_CONINTVAL_2CLK_gc = (0x01<<4), /* 2 CLK / 3 CLK in S/H mode */ - DAC_CONINTVAL_4CLK_gc = (0x02<<4), /* 4 CLK / 6 CLK in S/H mode */ - DAC_CONINTVAL_8CLK_gc = (0x03<<4), /* 8 CLK / 12 CLK in S/H mode */ - DAC_CONINTVAL_16CLK_gc = (0x04<<4), /* 16 CLK / 24 CLK in S/H mode */ - DAC_CONINTVAL_32CLK_gc = (0x05<<4), /* 32 CLK / 48 CLK in S/H mode */ - DAC_CONINTVAL_64CLK_gc = (0x06<<4), /* 64 CLK / 96 CLK in S/H mode */ - DAC_CONINTVAL_128CLK_gc = (0x07<<4), /* 128 CLK / 192 CLK in S/H mode */ -} DAC_CONINTVAL_t; - -/* Refresh rate */ -typedef enum DAC_REFRESH_enum -{ - DAC_REFRESH_16CLK_gc = (0x00<<0), /* 16 CLK */ - DAC_REFRESH_32CLK_gc = (0x01<<0), /* 32 CLK */ - DAC_REFRESH_64CLK_gc = (0x02<<0), /* 64 CLK */ - DAC_REFRESH_128CLK_gc = (0x03<<0), /* 128 CLK */ - DAC_REFRESH_256CLK_gc = (0x04<<0), /* 256 CLK */ - DAC_REFRESH_512CLK_gc = (0x05<<0), /* 512 CLK */ - DAC_REFRESH_1024CLK_gc = (0x06<<0), /* 1024 CLK */ - DAC_REFRESH_2048CLK_gc = (0x07<<0), /* 2048 CLK */ - DAC_REFRESH_4096CLK_gc = (0x08<<0), /* 4096 CLK */ - DAC_REFRESH_8192CLK_gc = (0x09<<0), /* 8192 CLK */ - DAC_REFRESH_16384CLK_gc = (0x0A<<0), /* 16384 CLK */ - DAC_REFRESH_32768CLK_gc = (0x0B<<0), /* 32768 CLK */ - DAC_REFRESH_65536CLK_gc = (0x0C<<0), /* 65536 CLK */ - DAC_REFRESH_OFF_gc = (0x0F<<0), /* Auto refresh OFF */ -} DAC_REFRESH_t; - - -/* --------------------------------------------------------------------------- -RTC - Real-Time Clounter --------------------------------------------------------------------------- -*/ - -/* Real-Time Counter */ -typedef struct RTC_struct -{ - register8_t CTRL; /* Control Register */ - register8_t STATUS; /* Status Register */ - register8_t INTCTRL; /* Interrupt Control Register */ - register8_t INTFLAGS; /* Interrupt Flags */ - register8_t TEMP; /* Temporary register */ - register8_t reserved_0x05; - register8_t reserved_0x06; - register8_t reserved_0x07; - _WORDREGISTER(CNT); /* Count Register */ - _WORDREGISTER(PER); /* Period Register */ - _WORDREGISTER(COMP); /* Compare Register */ -} RTC_t; - -/* Prescaler Factor */ -typedef enum RTC_PRESCALER_enum -{ - RTC_PRESCALER_OFF_gc = (0x00<<0), /* RTC Off */ - RTC_PRESCALER_DIV1_gc = (0x01<<0), /* RTC Clock */ - RTC_PRESCALER_DIV2_gc = (0x02<<0), /* RTC Clock / 2 */ - RTC_PRESCALER_DIV8_gc = (0x03<<0), /* RTC Clock / 8 */ - RTC_PRESCALER_DIV16_gc = (0x04<<0), /* RTC Clock / 16 */ - RTC_PRESCALER_DIV64_gc = (0x05<<0), /* RTC Clock / 64 */ - RTC_PRESCALER_DIV256_gc = (0x06<<0), /* RTC Clock / 256 */ - RTC_PRESCALER_DIV1024_gc = (0x07<<0), /* RTC Clock / 1024 */ -} RTC_PRESCALER_t; - -/* Compare Interrupt level */ -typedef enum RTC_COMPINTLVL_enum -{ - RTC_COMPINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ - RTC_COMPINTLVL_LO_gc = (0x01<<2), /* Low Level */ - RTC_COMPINTLVL_MED_gc = (0x02<<2), /* Medium Level */ - RTC_COMPINTLVL_HI_gc = (0x03<<2), /* High Level */ -} RTC_COMPINTLVL_t; - -/* Overflow Interrupt level */ -typedef enum RTC_OVFINTLVL_enum -{ - RTC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - RTC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ - RTC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ - RTC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ -} RTC_OVFINTLVL_t; - - -/* --------------------------------------------------------------------------- -EBI - External Bus Interface --------------------------------------------------------------------------- -*/ - -/* EBI Chip Select Module */ -typedef struct EBI_CS_struct -{ - register8_t CTRLA; /* Chip Select Control Register A */ - register8_t CTRLB; /* Chip Select Control Register B */ - _WORDREGISTER(BASEADDR); /* Chip Select Base Address */ -} EBI_CS_t; - -/* --------------------------------------------------------------------------- -EBI - External Bus Interface --------------------------------------------------------------------------- -*/ - -/* External Bus Interface */ -typedef struct EBI_struct -{ - register8_t CTRL; /* Control */ - register8_t SDRAMCTRLA; /* SDRAM Control Register A */ - register8_t reserved_0x02; - register8_t reserved_0x03; - _WORDREGISTER(REFRESH); /* SDRAM Refresh Period */ - _WORDREGISTER(INITDLY); /* SDRAM Initialization Delay */ - register8_t SDRAMCTRLB; /* SDRAM Control Register B */ - register8_t SDRAMCTRLC; /* SDRAM Control Register C */ - register8_t reserved_0x0A; - register8_t reserved_0x0B; - register8_t reserved_0x0C; - register8_t reserved_0x0D; - register8_t reserved_0x0E; - register8_t reserved_0x0F; - EBI_CS_t CS0; /* Chip Select 0 */ - EBI_CS_t CS1; /* Chip Select 1 */ - EBI_CS_t CS2; /* Chip Select 2 */ - EBI_CS_t CS3; /* Chip Select 3 */ -} EBI_t; - -/* Chip Select adress space */ -typedef enum EBI_CS_ASIZE_enum -{ - EBI_CS_ASIZE_256B_gc = (0x00<<2), /* 256 bytes */ - EBI_CS_ASIZE_512B_gc = (0x01<<2), /* 512 bytes */ - EBI_CS_ASIZE_1KB_gc = (0x02<<2), /* 1K bytes */ - EBI_CS_ASIZE_2KB_gc = (0x03<<2), /* 2K bytes */ - EBI_CS_ASIZE_4KB_gc = (0x04<<2), /* 4K bytes */ - EBI_CS_ASIZE_8KB_gc = (0x05<<2), /* 8K bytes */ - EBI_CS_ASIZE_16KB_gc = (0x06<<2), /* 16K bytes */ - EBI_CS_ASIZE_32KB_gc = (0x07<<2), /* 32K bytes */ - EBI_CS_ASIZE_64KB_gc = (0x08<<2), /* 64K bytes */ - EBI_CS_ASIZE_128KB_gc = (0x09<<2), /* 128K bytes */ - EBI_CS_ASIZE_256KB_gc = (0x0A<<2), /* 256K bytes */ - EBI_CS_ASIZE_512KB_gc = (0x0B<<2), /* 512K bytes */ - EBI_CS_ASIZE_1MB_gc = (0x0C<<2), /* 1M bytes */ - EBI_CS_ASIZE_2MB_gc = (0x0D<<2), /* 2M bytes */ - EBI_CS_ASIZE_4MB_gc = (0x0E<<2), /* 4M bytes */ - EBI_CS_ASIZE_8MB_gc = (0x0F<<2), /* 8M bytes */ - EBI_CS_ASIZE_16M_gc = (0x10<<2), /* 16M bytes */ -} EBI_CS_ASIZE_t; - -/* */ -typedef enum EBI_CS_SRWS_enum -{ - EBI_CS_SRWS_0CLK_gc = (0x00<<0), /* 0 cycles */ - EBI_CS_SRWS_1CLK_gc = (0x01<<0), /* 1 cycle */ - EBI_CS_SRWS_2CLK_gc = (0x02<<0), /* 2 cycles */ - EBI_CS_SRWS_3CLK_gc = (0x03<<0), /* 3 cycles */ - EBI_CS_SRWS_4CLK_gc = (0x04<<0), /* 4 cycles */ - EBI_CS_SRWS_5CLK_gc = (0x05<<0), /* 5 cycle */ - EBI_CS_SRWS_6CLK_gc = (0x06<<0), /* 6 cycles */ - EBI_CS_SRWS_7CLK_gc = (0x07<<0), /* 7 cycles */ -} EBI_CS_SRWS_t; - -/* Chip Select address mode */ -typedef enum EBI_CS_MODE_enum -{ - EBI_CS_MODE_DISABLED_gc = (0x00<<0), /* Chip Select Disabled */ - EBI_CS_MODE_SRAM_gc = (0x01<<0), /* Chip Select in SRAM mode */ - EBI_CS_MODE_LPC_gc = (0x02<<0), /* Chip Select in SRAM LPC mode */ - EBI_CS_MODE_SDRAM_gc = (0x03<<0), /* Chip Select in SDRAM mode */ -} EBI_CS_MODE_t; - -/* Chip Select SDRAM mode */ -typedef enum EBI_CS_SDMODE_enum -{ - EBI_CS_SDMODE_NORMAL_gc = (0x00<<0), /* Normal mode */ - EBI_CS_SDMODE_LOAD_gc = (0x01<<0), /* Load Mode Register command mode */ -} EBI_CS_SDMODE_t; - -/* */ -typedef enum EBI_SDDATAW_enum -{ - EBI_SDDATAW_4BIT_gc = (0x00<<6), /* 4-bit data bus */ - EBI_SDDATAW_8BIT_gc = (0x01<<6), /* 8-bit data bus */ -} EBI_SDDATAW_t; - -/* */ -typedef enum EBI_LPCMODE_enum -{ - EBI_LPCMODE_ALE1_gc = (0x00<<4), /* Data muxed with addr byte 0 */ - EBI_LPCMODE_ALE12_gc = (0x02<<4), /* Data muxed with addr byte 0 and 1 */ -} EBI_LPCMODE_t; - -/* */ -typedef enum EBI_SRMODE_enum -{ - EBI_SRMODE_ALE1_gc = (0x00<<2), /* Addr byte 0 muxed with 1 */ - EBI_SRMODE_ALE2_gc = (0x01<<2), /* Addr byte 0 muxed with 2 */ - EBI_SRMODE_ALE12_gc = (0x02<<2), /* Addr byte 0 muxed with 1 and 2 */ - EBI_SRMODE_NOALE_gc = (0x03<<2), /* No addr muxing */ -} EBI_SRMODE_t; - -/* */ -typedef enum EBI_IFMODE_enum -{ - EBI_IFMODE_DISABLED_gc = (0x00<<0), /* EBI Disabled */ - EBI_IFMODE_3PORT_gc = (0x01<<0), /* 3-port mode */ - EBI_IFMODE_4PORT_gc = (0x02<<0), /* 4-port mode */ - EBI_IFMODE_2PORT_gc = (0x03<<0), /* 2-port mode */ -} EBI_IFMODE_t; - -/* */ -typedef enum EBI_SDCOL_enum -{ - EBI_SDCOL_8BIT_gc = (0x00<<0), /* 8 column bits */ - EBI_SDCOL_9BIT_gc = (0x01<<0), /* 9 column bits */ - EBI_SDCOL_10BIT_gc = (0x02<<0), /* 10 column bits */ - EBI_SDCOL_11BIT_gc = (0x03<<0), /* 11 column bits */ -} EBI_SDCOL_t; - -/* */ -typedef enum EBI_MRDLY_enum -{ - EBI_MRDLY_0CLK_gc = (0x00<<6), /* 0 cycles */ - EBI_MRDLY_1CLK_gc = (0x01<<6), /* 1 cycle */ - EBI_MRDLY_2CLK_gc = (0x02<<6), /* 2 cycles */ - EBI_MRDLY_3CLK_gc = (0x03<<6), /* 3 cycles */ -} EBI_MRDLY_t; - -/* */ -typedef enum EBI_ROWCYCDLY_enum -{ - EBI_ROWCYCDLY_0CLK_gc = (0x00<<3), /* 0 cycles */ - EBI_ROWCYCDLY_1CLK_gc = (0x01<<3), /* 1 cycle */ - EBI_ROWCYCDLY_2CLK_gc = (0x02<<3), /* 2 cycles */ - EBI_ROWCYCDLY_3CLK_gc = (0x03<<3), /* 3 cycles */ - EBI_ROWCYCDLY_4CLK_gc = (0x04<<3), /* 4 cycles */ - EBI_ROWCYCDLY_5CLK_gc = (0x05<<3), /* 5 cycle */ - EBI_ROWCYCDLY_6CLK_gc = (0x06<<3), /* 6 cycles */ - EBI_ROWCYCDLY_7CLK_gc = (0x07<<3), /* 7 cycles */ -} EBI_ROWCYCDLY_t; - -/* */ -typedef enum EBI_RPDLY_enum -{ - EBI_RPDLY_0CLK_gc = (0x00<<0), /* 0 cycles */ - EBI_RPDLY_1CLK_gc = (0x01<<0), /* 1 cycle */ - EBI_RPDLY_2CLK_gc = (0x02<<0), /* 2 cycles */ - EBI_RPDLY_3CLK_gc = (0x03<<0), /* 3 cycles */ - EBI_RPDLY_4CLK_gc = (0x04<<0), /* 4 cycles */ - EBI_RPDLY_5CLK_gc = (0x05<<0), /* 5 cycle */ - EBI_RPDLY_6CLK_gc = (0x06<<0), /* 6 cycles */ - EBI_RPDLY_7CLK_gc = (0x07<<0), /* 7 cycles */ -} EBI_RPDLY_t; - -/* */ -typedef enum EBI_WRDLY_enum -{ - EBI_WRDLY_0CLK_gc = (0x00<<6), /* 0 cycles */ - EBI_WRDLY_1CLK_gc = (0x01<<6), /* 1 cycle */ - EBI_WRDLY_2CLK_gc = (0x02<<6), /* 2 cycles */ - EBI_WRDLY_3CLK_gc = (0x03<<6), /* 3 cycles */ -} EBI_WRDLY_t; - -/* */ -typedef enum EBI_ESRDLY_enum -{ - EBI_ESRDLY_0CLK_gc = (0x00<<3), /* 0 cycles */ - EBI_ESRDLY_1CLK_gc = (0x01<<3), /* 1 cycle */ - EBI_ESRDLY_2CLK_gc = (0x02<<3), /* 2 cycles */ - EBI_ESRDLY_3CLK_gc = (0x03<<3), /* 3 cycles */ - EBI_ESRDLY_4CLK_gc = (0x04<<3), /* 4 cycles */ - EBI_ESRDLY_5CLK_gc = (0x05<<3), /* 5 cycle */ - EBI_ESRDLY_6CLK_gc = (0x06<<3), /* 6 cycles */ - EBI_ESRDLY_7CLK_gc = (0x07<<3), /* 7 cycles */ -} EBI_ESRDLY_t; - -/* */ -typedef enum EBI_ROWCOLDLY_enum -{ - EBI_ROWCOLDLY_0CLK_gc = (0x00<<0), /* 0 cycles */ - EBI_ROWCOLDLY_1CLK_gc = (0x01<<0), /* 1 cycle */ - EBI_ROWCOLDLY_2CLK_gc = (0x02<<0), /* 2 cycles */ - EBI_ROWCOLDLY_3CLK_gc = (0x03<<0), /* 3 cycles */ - EBI_ROWCOLDLY_4CLK_gc = (0x04<<0), /* 4 cycles */ - EBI_ROWCOLDLY_5CLK_gc = (0x05<<0), /* 5 cycle */ - EBI_ROWCOLDLY_6CLK_gc = (0x06<<0), /* 6 cycles */ - EBI_ROWCOLDLY_7CLK_gc = (0x07<<0), /* 7 cycles */ -} EBI_ROWCOLDLY_t; - - -/* --------------------------------------------------------------------------- -TWI - Two-Wire Interface --------------------------------------------------------------------------- -*/ - -/* */ -typedef struct TWI_MASTER_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t CTRLC; /* Control Register C */ - register8_t STATUS; /* Status Register */ - register8_t BAUD; /* Baurd Rate Control Register */ - register8_t ADDR; /* Address Register */ - register8_t DATA; /* Data Register */ -} TWI_MASTER_t; - -/* --------------------------------------------------------------------------- -TWI - Two-Wire Interface --------------------------------------------------------------------------- -*/ - -/* */ -typedef struct TWI_SLAVE_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t STATUS; /* Status Register */ - register8_t ADDR; /* Address Register */ - register8_t DATA; /* Data Register */ - register8_t ADDRMASK; /* Address Mask Register */ -} TWI_SLAVE_t; - -/* --------------------------------------------------------------------------- -TWI - Two-Wire Interface --------------------------------------------------------------------------- -*/ - -/* Two-Wire Interface */ -typedef struct TWI_struct -{ - register8_t CTRL; /* TWI Common Control Register */ - TWI_MASTER_t MASTER; /* TWI master module */ - TWI_SLAVE_t SLAVE; /* TWI slave module */ -} TWI_t; - -/* Master Interrupt Level */ -typedef enum TWI_MASTER_INTLVL_enum -{ - TWI_MASTER_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ - TWI_MASTER_INTLVL_LO_gc = (0x01<<6), /* Low Level */ - TWI_MASTER_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ - TWI_MASTER_INTLVL_HI_gc = (0x03<<6), /* High Level */ -} TWI_MASTER_INTLVL_t; - -/* Inactive Timeout */ -typedef enum TWI_MASTER_TIMEOUT_enum -{ - TWI_MASTER_TIMEOUT_DISABLED_gc = (0x00<<2), /* Bus Timeout Disabled */ - TWI_MASTER_TIMEOUT_50US_gc = (0x01<<2), /* 50 Microseconds */ - TWI_MASTER_TIMEOUT_100US_gc = (0x02<<2), /* 100 Microseconds */ - TWI_MASTER_TIMEOUT_200US_gc = (0x03<<2), /* 200 Microseconds */ -} TWI_MASTER_TIMEOUT_t; - -/* Master Command */ -typedef enum TWI_MASTER_CMD_enum -{ - TWI_MASTER_CMD_NOACT_gc = (0x00<<0), /* No Action */ - TWI_MASTER_CMD_REPSTART_gc = (0x01<<0), /* Issue Repeated Start Condition */ - TWI_MASTER_CMD_RECVTRANS_gc = (0x02<<0), /* Receive or Transmit Data */ - TWI_MASTER_CMD_STOP_gc = (0x03<<0), /* Issue Stop Condition */ -} TWI_MASTER_CMD_t; - -/* Master Bus State */ -typedef enum TWI_MASTER_BUSSTATE_enum -{ - TWI_MASTER_BUSSTATE_UNKNOWN_gc = (0x00<<0), /* Unknown Bus State */ - TWI_MASTER_BUSSTATE_IDLE_gc = (0x01<<0), /* Bus is Idle */ - TWI_MASTER_BUSSTATE_OWNER_gc = (0x02<<0), /* This Module Controls The Bus */ - TWI_MASTER_BUSSTATE_BUSY_gc = (0x03<<0), /* The Bus is Busy */ -} TWI_MASTER_BUSSTATE_t; - -/* Slave Interrupt Level */ -typedef enum TWI_SLAVE_INTLVL_enum -{ - TWI_SLAVE_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ - TWI_SLAVE_INTLVL_LO_gc = (0x01<<6), /* Low Level */ - TWI_SLAVE_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ - TWI_SLAVE_INTLVL_HI_gc = (0x03<<6), /* High Level */ -} TWI_SLAVE_INTLVL_t; - -/* Slave Command */ -typedef enum TWI_SLAVE_CMD_enum -{ - TWI_SLAVE_CMD_NOACT_gc = (0x00<<0), /* No Action */ - TWI_SLAVE_CMD_COMPTRANS_gc = (0x02<<0), /* Used To Complete a Transaction */ - TWI_SLAVE_CMD_RESPONSE_gc = (0x03<<0), /* Used in Response to Address/Data Interrupt */ -} TWI_SLAVE_CMD_t; - - -/* --------------------------------------------------------------------------- -PORT - Port Configuration --------------------------------------------------------------------------- -*/ - -/* I/O port Configuration */ -typedef struct PORTCFG_struct -{ - register8_t MPCMASK; /* Multi-pin Configuration Mask */ - register8_t reserved_0x01; - register8_t VPCTRLA; /* Virtual Port Control Register A */ - register8_t VPCTRLB; /* Virtual Port Control Register B */ - register8_t CLKEVOUT; /* Clock and Event Out Register */ -} PORTCFG_t; - -/* --------------------------------------------------------------------------- -PORT - Port Configuration --------------------------------------------------------------------------- -*/ - -/* Virtual Port */ -typedef struct VPORT_struct -{ - register8_t DIR; /* I/O Port Data Direction */ - register8_t OUT; /* I/O Port Output */ - register8_t IN; /* I/O Port Input */ - register8_t INTFLAGS; /* Interrupt Flag Register */ -} VPORT_t; - -/* --------------------------------------------------------------------------- -PORT - Port Configuration --------------------------------------------------------------------------- -*/ - -/* I/O Ports */ -typedef struct PORT_struct -{ - register8_t DIR; /* I/O Port Data Direction */ - register8_t DIRSET; /* I/O Port Data Direction Set */ - register8_t DIRCLR; /* I/O Port Data Direction Clear */ - register8_t DIRTGL; /* I/O Port Data Direction Toggle */ - register8_t OUT; /* I/O Port Output */ - register8_t OUTSET; /* I/O Port Output Set */ - register8_t OUTCLR; /* I/O Port Output Clear */ - register8_t OUTTGL; /* I/O Port Output Toggle */ - register8_t IN; /* I/O port Input */ - register8_t INTCTRL; /* Interrupt Control Register */ - register8_t INT0MASK; /* Port Interrupt 0 Mask */ - register8_t INT1MASK; /* Port Interrupt 1 Mask */ - register8_t INTFLAGS; /* Interrupt Flag Register */ - register8_t reserved_0x0D; - register8_t reserved_0x0E; - register8_t reserved_0x0F; - register8_t PIN0CTRL; /* Pin 0 Control Register */ - register8_t PIN1CTRL; /* Pin 1 Control Register */ - register8_t PIN2CTRL; /* Pin 2 Control Register */ - register8_t PIN3CTRL; /* Pin 3 Control Register */ - register8_t PIN4CTRL; /* Pin 4 Control Register */ - register8_t PIN5CTRL; /* Pin 5 Control Register */ - register8_t PIN6CTRL; /* Pin 6 Control Register */ - register8_t PIN7CTRL; /* Pin 7 Control Register */ -} PORT_t; - -/* Virtual Port 0 Mapping */ -typedef enum PORTCFG_VP0MAP_enum -{ - PORTCFG_VP0MAP_PORTA_gc = (0x00<<0), /* Mapped To PORTA */ - PORTCFG_VP0MAP_PORTB_gc = (0x01<<0), /* Mapped To PORTB */ - PORTCFG_VP0MAP_PORTC_gc = (0x02<<0), /* Mapped To PORTC */ - PORTCFG_VP0MAP_PORTD_gc = (0x03<<0), /* Mapped To PORTD */ - PORTCFG_VP0MAP_PORTE_gc = (0x04<<0), /* Mapped To PORTE */ - PORTCFG_VP0MAP_PORTF_gc = (0x05<<0), /* Mapped To PORTF */ - PORTCFG_VP0MAP_PORTG_gc = (0x06<<0), /* Mapped To PORTG */ - PORTCFG_VP0MAP_PORTH_gc = (0x07<<0), /* Mapped To PORTH */ - PORTCFG_VP0MAP_PORTJ_gc = (0x08<<0), /* Mapped To PORTJ */ - PORTCFG_VP0MAP_PORTK_gc = (0x09<<0), /* Mapped To PORTK */ - PORTCFG_VP0MAP_PORTL_gc = (0x0A<<0), /* Mapped To PORTL */ - PORTCFG_VP0MAP_PORTM_gc = (0x0B<<0), /* Mapped To PORTM */ - PORTCFG_VP0MAP_PORTN_gc = (0x0C<<0), /* Mapped To PORTN */ - PORTCFG_VP0MAP_PORTP_gc = (0x0D<<0), /* Mapped To PORTP */ - PORTCFG_VP0MAP_PORTQ_gc = (0x0E<<0), /* Mapped To PORTQ */ - PORTCFG_VP0MAP_PORTR_gc = (0x0F<<0), /* Mapped To PORTR */ -} PORTCFG_VP0MAP_t; - -/* Virtual Port 1 Mapping */ -typedef enum PORTCFG_VP1MAP_enum -{ - PORTCFG_VP1MAP_PORTA_gc = (0x00<<4), /* Mapped To PORTA */ - PORTCFG_VP1MAP_PORTB_gc = (0x01<<4), /* Mapped To PORTB */ - PORTCFG_VP1MAP_PORTC_gc = (0x02<<4), /* Mapped To PORTC */ - PORTCFG_VP1MAP_PORTD_gc = (0x03<<4), /* Mapped To PORTD */ - PORTCFG_VP1MAP_PORTE_gc = (0x04<<4), /* Mapped To PORTE */ - PORTCFG_VP1MAP_PORTF_gc = (0x05<<4), /* Mapped To PORTF */ - PORTCFG_VP1MAP_PORTG_gc = (0x06<<4), /* Mapped To PORTG */ - PORTCFG_VP1MAP_PORTH_gc = (0x07<<4), /* Mapped To PORTH */ - PORTCFG_VP1MAP_PORTJ_gc = (0x08<<4), /* Mapped To PORTJ */ - PORTCFG_VP1MAP_PORTK_gc = (0x09<<4), /* Mapped To PORTK */ - PORTCFG_VP1MAP_PORTL_gc = (0x0A<<4), /* Mapped To PORTL */ - PORTCFG_VP1MAP_PORTM_gc = (0x0B<<4), /* Mapped To PORTM */ - PORTCFG_VP1MAP_PORTN_gc = (0x0C<<4), /* Mapped To PORTN */ - PORTCFG_VP1MAP_PORTP_gc = (0x0D<<4), /* Mapped To PORTP */ - PORTCFG_VP1MAP_PORTQ_gc = (0x0E<<4), /* Mapped To PORTQ */ - PORTCFG_VP1MAP_PORTR_gc = (0x0F<<4), /* Mapped To PORTR */ -} PORTCFG_VP1MAP_t; - -/* Virtual Port 2 Mapping */ -typedef enum PORTCFG_VP2MAP_enum -{ - PORTCFG_VP2MAP_PORTA_gc = (0x00<<0), /* Mapped To PORTA */ - PORTCFG_VP2MAP_PORTB_gc = (0x01<<0), /* Mapped To PORTB */ - PORTCFG_VP2MAP_PORTC_gc = (0x02<<0), /* Mapped To PORTC */ - PORTCFG_VP2MAP_PORTD_gc = (0x03<<0), /* Mapped To PORTD */ - PORTCFG_VP2MAP_PORTE_gc = (0x04<<0), /* Mapped To PORTE */ - PORTCFG_VP2MAP_PORTF_gc = (0x05<<0), /* Mapped To PORTF */ - PORTCFG_VP2MAP_PORTG_gc = (0x06<<0), /* Mapped To PORTG */ - PORTCFG_VP2MAP_PORTH_gc = (0x07<<0), /* Mapped To PORTH */ - PORTCFG_VP2MAP_PORTJ_gc = (0x08<<0), /* Mapped To PORTJ */ - PORTCFG_VP2MAP_PORTK_gc = (0x09<<0), /* Mapped To PORTK */ - PORTCFG_VP2MAP_PORTL_gc = (0x0A<<0), /* Mapped To PORTL */ - PORTCFG_VP2MAP_PORTM_gc = (0x0B<<0), /* Mapped To PORTM */ - PORTCFG_VP2MAP_PORTN_gc = (0x0C<<0), /* Mapped To PORTN */ - PORTCFG_VP2MAP_PORTP_gc = (0x0D<<0), /* Mapped To PORTP */ - PORTCFG_VP2MAP_PORTQ_gc = (0x0E<<0), /* Mapped To PORTQ */ - PORTCFG_VP2MAP_PORTR_gc = (0x0F<<0), /* Mapped To PORTR */ -} PORTCFG_VP2MAP_t; - -/* Virtual Port 3 Mapping */ -typedef enum PORTCFG_VP3MAP_enum -{ - PORTCFG_VP3MAP_PORTA_gc = (0x00<<4), /* Mapped To PORTA */ - PORTCFG_VP3MAP_PORTB_gc = (0x01<<4), /* Mapped To PORTB */ - PORTCFG_VP3MAP_PORTC_gc = (0x02<<4), /* Mapped To PORTC */ - PORTCFG_VP3MAP_PORTD_gc = (0x03<<4), /* Mapped To PORTD */ - PORTCFG_VP3MAP_PORTE_gc = (0x04<<4), /* Mapped To PORTE */ - PORTCFG_VP3MAP_PORTF_gc = (0x05<<4), /* Mapped To PORTF */ - PORTCFG_VP3MAP_PORTG_gc = (0x06<<4), /* Mapped To PORTG */ - PORTCFG_VP3MAP_PORTH_gc = (0x07<<4), /* Mapped To PORTH */ - PORTCFG_VP3MAP_PORTJ_gc = (0x08<<4), /* Mapped To PORTJ */ - PORTCFG_VP3MAP_PORTK_gc = (0x09<<4), /* Mapped To PORTK */ - PORTCFG_VP3MAP_PORTL_gc = (0x0A<<4), /* Mapped To PORTL */ - PORTCFG_VP3MAP_PORTM_gc = (0x0B<<4), /* Mapped To PORTM */ - PORTCFG_VP3MAP_PORTN_gc = (0x0C<<4), /* Mapped To PORTN */ - PORTCFG_VP3MAP_PORTP_gc = (0x0D<<4), /* Mapped To PORTP */ - PORTCFG_VP3MAP_PORTQ_gc = (0x0E<<4), /* Mapped To PORTQ */ - PORTCFG_VP3MAP_PORTR_gc = (0x0F<<4), /* Mapped To PORTR */ -} PORTCFG_VP3MAP_t; - -/* Clock Output Port */ -typedef enum PORTCFG_CLKOUT_enum -{ - PORTCFG_CLKOUT_OFF_gc = (0x00<<0), /* Clock Output Disabled */ - PORTCFG_CLKOUT_PC7_gc = (0x01<<0), /* Clock Output on Port C pin 7 */ - PORTCFG_CLKOUT_PD7_gc = (0x02<<0), /* Clock Output on Port D pin 7 */ - PORTCFG_CLKOUT_PE7_gc = (0x03<<0), /* Clock Output on Port E pin 7 */ -} PORTCFG_CLKOUT_t; - -/* Event Output Port */ -typedef enum PORTCFG_EVOUT_enum -{ - PORTCFG_EVOUT_OFF_gc = (0x00<<4), /* Event Output Disabled */ - PORTCFG_EVOUT_PC7_gc = (0x01<<4), /* Event Channel 7 Output on Port C pin 7 */ - PORTCFG_EVOUT_PD7_gc = (0x02<<4), /* Event Channel 7 Output on Port D pin 7 */ - PORTCFG_EVOUT_PE7_gc = (0x03<<4), /* Event Channel 7 Output on Port E pin 7 */ -} PORTCFG_EVOUT_t; - -/* Port Interrupt 0 Level */ -typedef enum PORT_INT0LVL_enum -{ - PORT_INT0LVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - PORT_INT0LVL_LO_gc = (0x01<<0), /* Low Level */ - PORT_INT0LVL_MED_gc = (0x02<<0), /* Medium Level */ - PORT_INT0LVL_HI_gc = (0x03<<0), /* High Level */ -} PORT_INT0LVL_t; - -/* Port Interrupt 1 Level */ -typedef enum PORT_INT1LVL_enum -{ - PORT_INT1LVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ - PORT_INT1LVL_LO_gc = (0x01<<2), /* Low Level */ - PORT_INT1LVL_MED_gc = (0x02<<2), /* Medium Level */ - PORT_INT1LVL_HI_gc = (0x03<<2), /* High Level */ -} PORT_INT1LVL_t; - -/* Output/Pull Configuration */ -typedef enum PORT_OPC_enum -{ - PORT_OPC_TOTEM_gc = (0x00<<3), /* Totempole */ - PORT_OPC_BUSKEEPER_gc = (0x01<<3), /* Totempole w/ Bus keeper on Input and Output */ - PORT_OPC_PULLDOWN_gc = (0x02<<3), /* Totempole w/ Pull-down on Input */ - PORT_OPC_PULLUP_gc = (0x03<<3), /* Totempole w/ Pull-up on Input */ - PORT_OPC_WIREDOR_gc = (0x04<<3), /* Wired OR */ - PORT_OPC_WIREDAND_gc = (0x05<<3), /* Wired AND */ - PORT_OPC_WIREDORPULL_gc = (0x06<<3), /* Wired OR w/ Pull-down */ - PORT_OPC_WIREDANDPULL_gc = (0x07<<3), /* Wired AND w/ Pull-up */ -} PORT_OPC_t; - -/* Input/Sense Configuration */ -typedef enum PORT_ISC_enum -{ - PORT_ISC_BOTHEDGES_gc = (0x00<<0), /* Sense Both Edges */ - PORT_ISC_RISING_gc = (0x01<<0), /* Sense Rising Edge */ - PORT_ISC_FALLING_gc = (0x02<<0), /* Sense Falling Edge */ - PORT_ISC_LEVEL_gc = (0x03<<0), /* Sense Level (Transparent For Events) */ - PORT_ISC_INPUT_DISABLE_gc = (0x07<<0), /* Disable Digital Input Buffer */ -} PORT_ISC_t; - - -/* --------------------------------------------------------------------------- -TC - 16-bit Timer/Counter With PWM --------------------------------------------------------------------------- -*/ - -/* 16-bit Timer/Counter 0 */ -typedef struct TC0_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t CTRLC; /* Control register C */ - register8_t CTRLD; /* Control Register D */ - register8_t CTRLE; /* Control Register E */ - register8_t reserved_0x05; - register8_t INTCTRLA; /* Interrupt Control Register A */ - register8_t INTCTRLB; /* Interrupt Control Register B */ - register8_t CTRLFCLR; /* Control Register F Clear */ - register8_t CTRLFSET; /* Control Register F Set */ - register8_t CTRLGCLR; /* Control Register G Clear */ - register8_t CTRLGSET; /* Control Register G Set */ - register8_t INTFLAGS; /* Interrupt Flag Register */ - register8_t reserved_0x0D; - register8_t reserved_0x0E; - register8_t TEMP; /* Temporary Register For 16-bit Access */ - register8_t reserved_0x10; - register8_t reserved_0x11; - register8_t reserved_0x12; - register8_t reserved_0x13; - register8_t reserved_0x14; - register8_t reserved_0x15; - register8_t reserved_0x16; - register8_t reserved_0x17; - register8_t reserved_0x18; - register8_t reserved_0x19; - register8_t reserved_0x1A; - register8_t reserved_0x1B; - register8_t reserved_0x1C; - register8_t reserved_0x1D; - register8_t reserved_0x1E; - register8_t reserved_0x1F; - _WORDREGISTER(CNT); /* Count */ - register8_t reserved_0x22; - register8_t reserved_0x23; - register8_t reserved_0x24; - register8_t reserved_0x25; - _WORDREGISTER(PER); /* Period */ - _WORDREGISTER(CCA); /* Compare or Capture A */ - _WORDREGISTER(CCB); /* Compare or Capture B */ - _WORDREGISTER(CCC); /* Compare or Capture C */ - _WORDREGISTER(CCD); /* Compare or Capture D */ - register8_t reserved_0x30; - register8_t reserved_0x31; - register8_t reserved_0x32; - register8_t reserved_0x33; - register8_t reserved_0x34; - register8_t reserved_0x35; - _WORDREGISTER(PERBUF); /* Period Buffer */ - _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ - _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ - _WORDREGISTER(CCCBUF); /* Compare Or Capture C Buffer */ - _WORDREGISTER(CCDBUF); /* Compare Or Capture D Buffer */ -} TC0_t; - -/* --------------------------------------------------------------------------- -TC - 16-bit Timer/Counter With PWM --------------------------------------------------------------------------- -*/ - -/* 16-bit Timer/Counter 1 */ -typedef struct TC1_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t CTRLC; /* Control register C */ - register8_t CTRLD; /* Control Register D */ - register8_t CTRLE; /* Control Register E */ - register8_t reserved_0x05; - register8_t INTCTRLA; /* Interrupt Control Register A */ - register8_t INTCTRLB; /* Interrupt Control Register B */ - register8_t CTRLFCLR; /* Control Register F Clear */ - register8_t CTRLFSET; /* Control Register F Set */ - register8_t CTRLGCLR; /* Control Register G Clear */ - register8_t CTRLGSET; /* Control Register G Set */ - register8_t INTFLAGS; /* Interrupt Flag Register */ - register8_t reserved_0x0D; - register8_t reserved_0x0E; - register8_t TEMP; /* Temporary Register For 16-bit Access */ - register8_t reserved_0x10; - register8_t reserved_0x11; - register8_t reserved_0x12; - register8_t reserved_0x13; - register8_t reserved_0x14; - register8_t reserved_0x15; - register8_t reserved_0x16; - register8_t reserved_0x17; - register8_t reserved_0x18; - register8_t reserved_0x19; - register8_t reserved_0x1A; - register8_t reserved_0x1B; - register8_t reserved_0x1C; - register8_t reserved_0x1D; - register8_t reserved_0x1E; - register8_t reserved_0x1F; - _WORDREGISTER(CNT); /* Count */ - register8_t reserved_0x22; - register8_t reserved_0x23; - register8_t reserved_0x24; - register8_t reserved_0x25; - _WORDREGISTER(PER); /* Period */ - _WORDREGISTER(CCA); /* Compare or Capture A */ - _WORDREGISTER(CCB); /* Compare or Capture B */ - register8_t reserved_0x2C; - register8_t reserved_0x2D; - register8_t reserved_0x2E; - register8_t reserved_0x2F; - register8_t reserved_0x30; - register8_t reserved_0x31; - register8_t reserved_0x32; - register8_t reserved_0x33; - register8_t reserved_0x34; - register8_t reserved_0x35; - _WORDREGISTER(PERBUF); /* Period Buffer */ - _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ - _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ -} TC1_t; - -/* --------------------------------------------------------------------------- -TC - 16-bit Timer/Counter With PWM --------------------------------------------------------------------------- -*/ - -/* Advanced Waveform Extension */ -typedef struct AWEX_struct -{ - register8_t CTRL; /* Control Register */ - register8_t reserved_0x01; - register8_t FDEMASK; /* Fault Detection Event Mask */ - register8_t FDCTRL; /* Fault Detection Control Register */ - register8_t STATUS; /* Status Register */ - register8_t reserved_0x05; - register8_t DTBOTH; /* Dead Time Both Sides */ - register8_t DTBOTHBUF; /* Dead Time Both Sides Buffer */ - register8_t DTLS; /* Dead Time Low Side */ - register8_t DTHS; /* Dead Time High Side */ - register8_t DTLSBUF; /* Dead Time Low Side Buffer */ - register8_t DTHSBUF; /* Dead Time High Side Buffer */ - register8_t OUTOVEN; /* Output Override Enable */ -} AWEX_t; - -/* --------------------------------------------------------------------------- -TC - 16-bit Timer/Counter With PWM --------------------------------------------------------------------------- -*/ - -/* High-Resolution Extension */ -typedef struct HIRES_struct -{ - register8_t CTRLA; /* Control Register */ -} HIRES_t; - -/* Clock Selection */ -typedef enum TC_CLKSEL_enum -{ - TC_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */ - TC_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */ - TC_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */ - TC_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */ - TC_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */ - TC_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */ - TC_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */ - TC_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */ - TC_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */ - TC_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */ - TC_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */ - TC_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */ - TC_CLKSEL_EVCH4_gc = (0x0C<<0), /* Event Channel 4 */ - TC_CLKSEL_EVCH5_gc = (0x0D<<0), /* Event Channel 5 */ - TC_CLKSEL_EVCH6_gc = (0x0E<<0), /* Event Channel 6 */ - TC_CLKSEL_EVCH7_gc = (0x0F<<0), /* Event Channel 7 */ -} TC_CLKSEL_t; - -/* Waveform Generation Mode */ -typedef enum TC_WGMODE_enum -{ - TC_WGMODE_NORMAL_gc = (0x00<<0), /* Normal Mode */ - TC_WGMODE_FRQ_gc = (0x01<<0), /* Frequency Generation Mode */ - TC_WGMODE_SS_gc = (0x03<<0), /* Single Slope */ - TC_WGMODE_DS_T_gc = (0x05<<0), /* Dual Slope, Update on TOP */ - TC_WGMODE_DS_TB_gc = (0x06<<0), /* Dual Slope, Update on TOP and BOTTOM */ - TC_WGMODE_DS_B_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */ -} TC_WGMODE_t; - -/* Event Action */ -typedef enum TC_EVACT_enum -{ - TC_EVACT_OFF_gc = (0x00<<5), /* No Event Action */ - TC_EVACT_CAPT_gc = (0x01<<5), /* Input Capture */ - TC_EVACT_UPDOWN_gc = (0x02<<5), /* Externally Controlled Up/Down Count */ - TC_EVACT_QDEC_gc = (0x03<<5), /* Quadrature Decode */ - TC_EVACT_RESTART_gc = (0x04<<5), /* Restart */ - TC_EVACT_FRQ_gc = (0x05<<5), /* Frequency Capture */ - TC_EVACT_FRW_gc = (0x05<<5), /* Frequency Capture (typo in earlier header file) */ - TC_EVACT_PW_gc = (0x06<<5), /* Pulse-width Capture */ -} TC_EVACT_t; - -/* Event Selection */ -typedef enum TC_EVSEL_enum -{ - TC_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ - TC_EVSEL_CH0_gc = (0x08<<0), /* Event Channel 0 */ - TC_EVSEL_CH1_gc = (0x09<<0), /* Event Channel 1 */ - TC_EVSEL_CH2_gc = (0x0A<<0), /* Event Channel 2 */ - TC_EVSEL_CH3_gc = (0x0B<<0), /* Event Channel 3 */ - TC_EVSEL_CH4_gc = (0x0C<<0), /* Event Channel 4 */ - TC_EVSEL_CH5_gc = (0x0D<<0), /* Event Channel 5 */ - TC_EVSEL_CH6_gc = (0x0E<<0), /* Event Channel 6 */ - TC_EVSEL_CH7_gc = (0x0F<<0), /* Event Channel 7 */ -} TC_EVSEL_t; - -/* Error Interrupt Level */ -typedef enum TC_ERRINTLVL_enum -{ - TC_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ - TC_ERRINTLVL_LO_gc = (0x01<<2), /* Low Level */ - TC_ERRINTLVL_MED_gc = (0x02<<2), /* Medium Level */ - TC_ERRINTLVL_HI_gc = (0x03<<2), /* High Level */ -} TC_ERRINTLVL_t; - -/* Overflow Interrupt Level */ -typedef enum TC_OVFINTLVL_enum -{ - TC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - TC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ - TC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ - TC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ -} TC_OVFINTLVL_t; - -/* Compare or Capture D Interrupt Level */ -typedef enum TC_CCDINTLVL_enum -{ - TC_CCDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ - TC_CCDINTLVL_LO_gc = (0x01<<6), /* Low Level */ - TC_CCDINTLVL_MED_gc = (0x02<<6), /* Medium Level */ - TC_CCDINTLVL_HI_gc = (0x03<<6), /* High Level */ -} TC_CCDINTLVL_t; - -/* Compare or Capture C Interrupt Level */ -typedef enum TC_CCCINTLVL_enum -{ - TC_CCCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ - TC_CCCINTLVL_LO_gc = (0x01<<4), /* Low Level */ - TC_CCCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ - TC_CCCINTLVL_HI_gc = (0x03<<4), /* High Level */ -} TC_CCCINTLVL_t; - -/* Compare or Capture B Interrupt Level */ -typedef enum TC_CCBINTLVL_enum -{ - TC_CCBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ - TC_CCBINTLVL_LO_gc = (0x01<<2), /* Low Level */ - TC_CCBINTLVL_MED_gc = (0x02<<2), /* Medium Level */ - TC_CCBINTLVL_HI_gc = (0x03<<2), /* High Level */ -} TC_CCBINTLVL_t; - -/* Compare or Capture A Interrupt Level */ -typedef enum TC_CCAINTLVL_enum -{ - TC_CCAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - TC_CCAINTLVL_LO_gc = (0x01<<0), /* Low Level */ - TC_CCAINTLVL_MED_gc = (0x02<<0), /* Medium Level */ - TC_CCAINTLVL_HI_gc = (0x03<<0), /* High Level */ -} TC_CCAINTLVL_t; - -/* Timer/Counter Command */ -typedef enum TC_CMD_enum -{ - TC_CMD_NONE_gc = (0x00<<2), /* No Command */ - TC_CMD_UPDATE_gc = (0x01<<2), /* Force Update */ - TC_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ - TC_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ -} TC_CMD_t; - -/* Fault Detect Action */ -typedef enum AWEX_FDACT_enum -{ - AWEX_FDACT_NONE_gc = (0x00<<0), /* No Fault Protection */ - AWEX_FDACT_CLEAROE_gc = (0x01<<0), /* Clear Output Enable Bits */ - AWEX_FDACT_CLEARDIR_gc = (0x03<<0), /* Clear I/O Port Direction Bits */ -} AWEX_FDACT_t; - -/* High Resolution Enable */ -typedef enum HIRES_HREN_enum -{ - HIRES_HREN_NONE_gc = (0x00<<0), /* No Fault Protection */ - HIRES_HREN_TC0_gc = (0x01<<0), /* Enable High Resolution on Timer/Counter 0 */ - HIRES_HREN_TC1_gc = (0x02<<0), /* Enable High Resolution on Timer/Counter 1 */ - HIRES_HREN_BOTH_gc = (0x03<<0), /* Enable High Resolution both Timer/Counters */ -} HIRES_HREN_t; - - -/* --------------------------------------------------------------------------- -USART - Universal Asynchronous Receiver-Transmitter --------------------------------------------------------------------------- -*/ - -/* Universal Synchronous/Asynchronous Receiver/Transmitter */ -typedef struct USART_struct -{ - register8_t DATA; /* Data Register */ - register8_t STATUS; /* Status Register */ - register8_t reserved_0x02; - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t CTRLC; /* Control Register C */ - register8_t BAUDCTRLA; /* Baud Rate Control Register A */ - register8_t BAUDCTRLB; /* Baud Rate Control Register B */ -} USART_t; - -/* Receive Complete Interrupt level */ -typedef enum USART_RXCINTLVL_enum -{ - USART_RXCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ - USART_RXCINTLVL_LO_gc = (0x01<<4), /* Low Level */ - USART_RXCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ - USART_RXCINTLVL_HI_gc = (0x03<<4), /* High Level */ -} USART_RXCINTLVL_t; - -/* Transmit Complete Interrupt level */ -typedef enum USART_TXCINTLVL_enum -{ - USART_TXCINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ - USART_TXCINTLVL_LO_gc = (0x01<<2), /* Low Level */ - USART_TXCINTLVL_MED_gc = (0x02<<2), /* Medium Level */ - USART_TXCINTLVL_HI_gc = (0x03<<2), /* High Level */ -} USART_TXCINTLVL_t; - -/* Data Register Empty Interrupt level */ -typedef enum USART_DREINTLVL_enum -{ - USART_DREINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - USART_DREINTLVL_LO_gc = (0x01<<0), /* Low Level */ - USART_DREINTLVL_MED_gc = (0x02<<0), /* Medium Level */ - USART_DREINTLVL_HI_gc = (0x03<<0), /* High Level */ -} USART_DREINTLVL_t; - -/* Character Size */ -typedef enum USART_CHSIZE_enum -{ - USART_CHSIZE_5BIT_gc = (0x00<<0), /* Character size: 5 bit */ - USART_CHSIZE_6BIT_gc = (0x01<<0), /* Character size: 6 bit */ - USART_CHSIZE_7BIT_gc = (0x02<<0), /* Character size: 7 bit */ - USART_CHSIZE_8BIT_gc = (0x03<<0), /* Character size: 8 bit */ - USART_CHSIZE_9BIT_gc = (0x07<<0), /* Character size: 9 bit */ -} USART_CHSIZE_t; - -/* Communication Mode */ -typedef enum USART_CMODE_enum -{ - USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6), /* Asynchronous Mode */ - USART_CMODE_SYNCHRONOUS_gc = (0x01<<6), /* Synchronous Mode */ - USART_CMODE_IRDA_gc = (0x02<<6), /* IrDA Mode */ - USART_CMODE_MSPI_gc = (0x03<<6), /* Master SPI Mode */ -} USART_CMODE_t; - -/* Parity Mode */ -typedef enum USART_PMODE_enum -{ - USART_PMODE_DISABLED_gc = (0x00<<4), /* No Parity */ - USART_PMODE_EVEN_gc = (0x02<<4), /* Even Parity */ - USART_PMODE_ODD_gc = (0x03<<4), /* Odd Parity */ -} USART_PMODE_t; - - -/* --------------------------------------------------------------------------- -SPI - Serial Peripheral Interface --------------------------------------------------------------------------- -*/ - -/* Serial Peripheral Interface */ -typedef struct SPI_struct -{ - register8_t CTRL; /* Control Register */ - register8_t INTCTRL; /* Interrupt Control Register */ - register8_t STATUS; /* Status Register */ - register8_t DATA; /* Data Register */ -} SPI_t; - -/* SPI Mode */ -typedef enum SPI_MODE_enum -{ - SPI_MODE_0_gc = (0x00<<2), /* SPI Mode 0 */ - SPI_MODE_1_gc = (0x01<<2), /* SPI Mode 1 */ - SPI_MODE_2_gc = (0x02<<2), /* SPI Mode 2 */ - SPI_MODE_3_gc = (0x03<<2), /* SPI Mode 3 */ -} SPI_MODE_t; - -/* Prescaler setting */ -typedef enum SPI_PRESCALER_enum -{ - SPI_PRESCALER_DIV4_gc = (0x00<<0), /* System Clock / 4 */ - SPI_PRESCALER_DIV16_gc = (0x01<<0), /* System Clock / 16 */ - SPI_PRESCALER_DIV64_gc = (0x02<<0), /* System Clock / 64 */ - SPI_PRESCALER_DIV128_gc = (0x03<<0), /* System Clock / 128 */ -} SPI_PRESCALER_t; - -/* Interrupt level */ -typedef enum SPI_INTLVL_enum -{ - SPI_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - SPI_INTLVL_LO_gc = (0x01<<0), /* Low Level */ - SPI_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ - SPI_INTLVL_HI_gc = (0x03<<0), /* High Level */ -} SPI_INTLVL_t; - - -/* --------------------------------------------------------------------------- -IRCOM - IR Communication Module --------------------------------------------------------------------------- -*/ - -/* IR Communication Module */ -typedef struct IRCOM_struct -{ - register8_t CTRL; /* Control Register */ - register8_t TXPLCTRL; /* IrDA Transmitter Pulse Length Control Register */ - register8_t RXPLCTRL; /* IrDA Receiver Pulse Length Control Register */ -} IRCOM_t; - -/* Event channel selection */ -typedef enum IRDA_EVSEL_enum -{ - IRDA_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ - IRDA_EVSEL_0_gc = (0x08<<0), /* Event Channel 0 */ - IRDA_EVSEL_1_gc = (0x09<<0), /* Event Channel 1 */ - IRDA_EVSEL_2_gc = (0x0A<<0), /* Event Channel 2 */ - IRDA_EVSEL_3_gc = (0x0B<<0), /* Event Channel 3 */ - IRDA_EVSEL_4_gc = (0x0C<<0), /* Event Channel 4 */ - IRDA_EVSEL_5_gc = (0x0D<<0), /* Event Channel 5 */ - IRDA_EVSEL_6_gc = (0x0E<<0), /* Event Channel 6 */ - IRDA_EVSEL_7_gc = (0x0F<<0), /* Event Channel 7 */ -} IRDA_EVSEL_t; - - -/* --------------------------------------------------------------------------- -AES - AES Module --------------------------------------------------------------------------- -*/ - -/* AES Module */ -typedef struct AES_struct -{ - register8_t CTRL; /* AES Control Register */ - register8_t STATUS; /* AES Status Register */ - register8_t STATE; /* AES State Register */ - register8_t KEY; /* AES Key Register */ - register8_t INTCTRL; /* AES Interrupt Control Register */ -} AES_t; - -/* Interrupt level */ -typedef enum AES_INTLVL_enum -{ - AES_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - AES_INTLVL_LO_gc = (0x01<<0), /* Low Level */ - AES_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ - AES_INTLVL_HI_gc = (0x03<<0), /* High Level */ -} AES_INTLVL_t; - - - -/* -========================================================================== -IO Module Instances. Mapped to memory. -========================================================================== -*/ - -#define VPORT0 (*(VPORT_t *) 0x0010) /* Virtual Port 0 */ -#define VPORT1 (*(VPORT_t *) 0x0014) /* Virtual Port 1 */ -#define VPORT2 (*(VPORT_t *) 0x0018) /* Virtual Port 2 */ -#define VPORT3 (*(VPORT_t *) 0x001C) /* Virtual Port 3 */ -#define OCD (*(OCD_t *) 0x002E) /* On-Chip Debug System */ -#define CLK (*(CLK_t *) 0x0040) /* Clock System */ -#define SLEEP (*(SLEEP_t *) 0x0048) /* Sleep Controller */ -#define OSC (*(OSC_t *) 0x0050) /* Oscillator Control */ -#define DFLLRC32M (*(DFLL_t *) 0x0060) /* DFLL for 32MHz RC Oscillator */ -#define DFLLRC2M (*(DFLL_t *) 0x0068) /* DFLL for 2MHz RC Oscillator */ -#define PR (*(PR_t *) 0x0070) /* Power Reduction */ -#define RST (*(RST_t *) 0x0078) /* Reset Controller */ -#define WDT (*(WDT_t *) 0x0080) /* Watch-Dog Timer */ -#define MCU (*(MCU_t *) 0x0090) /* MCU Control */ -#define PMIC (*(PMIC_t *) 0x00A0) /* Programmable Interrupt Controller */ -#define PORTCFG (*(PORTCFG_t *) 0x00B0) /* Port Configuration */ -#define AES (*(AES_t *) 0x00C0) /* AES Crypto Module */ -#define DMA (*(DMA_t *) 0x0100) /* DMA Controller */ -#define EVSYS (*(EVSYS_t *) 0x0180) /* Event System */ -#define NVM (*(NVM_t *) 0x01C0) /* Non Volatile Memory Controller */ -#define ADCA (*(ADC_t *) 0x0200) /* Analog to Digital Converter A */ -#define DACB (*(DAC_t *) 0x0320) /* Digital to Analog Converter B */ -#define ACA (*(AC_t *) 0x0380) /* Analog Comparator A */ -#define RTC (*(RTC_t *) 0x0400) /* Real-Time Counter */ -#define TWIC (*(TWI_t *) 0x0480) /* Two-Wire Interface C */ -#define TWIE (*(TWI_t *) 0x04A0) /* Two-Wire Interface E */ -#define PORTA (*(PORT_t *) 0x0600) /* Port A */ -#define PORTB (*(PORT_t *) 0x0620) /* Port B */ -#define PORTC (*(PORT_t *) 0x0640) /* Port C */ -#define PORTD (*(PORT_t *) 0x0660) /* Port D */ -#define PORTE (*(PORT_t *) 0x0680) /* Port E */ -#define PORTR (*(PORT_t *) 0x07E0) /* Port R */ -#define TCC0 (*(TC0_t *) 0x0800) /* Timer/Counter C0 */ -#define TCC1 (*(TC1_t *) 0x0840) /* Timer/Counter C1 */ -#define AWEXC (*(AWEX_t *) 0x0880) /* Advanced Waveform Extension C */ -#define HIRESC (*(HIRES_t *) 0x0890) /* High-Resolution Extension C */ -#define USARTC0 (*(USART_t *) 0x08A0) /* Universal Asynchronous Receiver-Transmitter C0 */ -#define USARTC1 (*(USART_t *) 0x08B0) /* Universal Asynchronous Receiver-Transmitter C1 */ -#define SPIC (*(SPI_t *) 0x08C0) /* Serial Peripheral Interface C */ -#define IRCOM (*(IRCOM_t *) 0x08F8) /* IR Communication Module */ -#define TCD0 (*(TC0_t *) 0x0900) /* Timer/Counter D0 */ -#define TCD1 (*(TC1_t *) 0x0940) /* Timer/Counter D1 */ -#define HIRESD (*(HIRES_t *) 0x0990) /* High-Resolution Extension D */ -#define USARTD0 (*(USART_t *) 0x09A0) /* Universal Asynchronous Receiver-Transmitter D0 */ -#define USARTD1 (*(USART_t *) 0x09B0) /* Universal Asynchronous Receiver-Transmitter D1 */ -#define SPID (*(SPI_t *) 0x09C0) /* Serial Peripheral Interface D */ -#define TCE0 (*(TC0_t *) 0x0A00) /* Timer/Counter E0 */ -#define HIRESE (*(HIRES_t *) 0x0A90) /* High-Resolution Extension E */ -#define USARTE0 (*(USART_t *) 0x0AA0) /* Universal Asynchronous Receiver-Transmitter E0 */ - - -#endif /* !defined (__ASSEMBLER__) */ - - -/* ========== Flattened fully qualified IO register names ========== */ - -/* GPIO - General Purpose IO Registers */ -#define GPIO_GPIOR0 _SFR_MEM8(0x0000) -#define GPIO_GPIOR1 _SFR_MEM8(0x0001) -#define GPIO_GPIOR2 _SFR_MEM8(0x0002) -#define GPIO_GPIOR3 _SFR_MEM8(0x0003) -#define GPIO_GPIOR4 _SFR_MEM8(0x0004) -#define GPIO_GPIOR5 _SFR_MEM8(0x0005) -#define GPIO_GPIOR6 _SFR_MEM8(0x0006) -#define GPIO_GPIOR7 _SFR_MEM8(0x0007) -#define GPIO_GPIOR8 _SFR_MEM8(0x0008) -#define GPIO_GPIOR9 _SFR_MEM8(0x0009) -#define GPIO_GPIORA _SFR_MEM8(0x000A) -#define GPIO_GPIORB _SFR_MEM8(0x000B) -#define GPIO_GPIORC _SFR_MEM8(0x000C) -#define GPIO_GPIORD _SFR_MEM8(0x000D) -#define GPIO_GPIORE _SFR_MEM8(0x000E) -#define GPIO_GPIORF _SFR_MEM8(0x000F) - -/* Deprecated */ -#define GPIO_GPIO0 _SFR_MEM8(0x0000) -#define GPIO_GPIO1 _SFR_MEM8(0x0001) -#define GPIO_GPIO2 _SFR_MEM8(0x0002) -#define GPIO_GPIO3 _SFR_MEM8(0x0003) -#define GPIO_GPIO4 _SFR_MEM8(0x0004) -#define GPIO_GPIO5 _SFR_MEM8(0x0005) -#define GPIO_GPIO6 _SFR_MEM8(0x0006) -#define GPIO_GPIO7 _SFR_MEM8(0x0007) -#define GPIO_GPIO8 _SFR_MEM8(0x0008) -#define GPIO_GPIO9 _SFR_MEM8(0x0009) -#define GPIO_GPIOA _SFR_MEM8(0x000A) -#define GPIO_GPIOB _SFR_MEM8(0x000B) -#define GPIO_GPIOC _SFR_MEM8(0x000C) -#define GPIO_GPIOD _SFR_MEM8(0x000D) -#define GPIO_GPIOE _SFR_MEM8(0x000E) -#define GPIO_GPIOF _SFR_MEM8(0x000F) - -/* VPORT0 - Virtual Port 0 */ -#define VPORT0_DIR _SFR_MEM8(0x0010) -#define VPORT0_OUT _SFR_MEM8(0x0011) -#define VPORT0_IN _SFR_MEM8(0x0012) -#define VPORT0_INTFLAGS _SFR_MEM8(0x0013) - -/* VPORT1 - Virtual Port 1 */ -#define VPORT1_DIR _SFR_MEM8(0x0014) -#define VPORT1_OUT _SFR_MEM8(0x0015) -#define VPORT1_IN _SFR_MEM8(0x0016) -#define VPORT1_INTFLAGS _SFR_MEM8(0x0017) - -/* VPORT2 - Virtual Port 2 */ -#define VPORT2_DIR _SFR_MEM8(0x0018) -#define VPORT2_OUT _SFR_MEM8(0x0019) -#define VPORT2_IN _SFR_MEM8(0x001A) -#define VPORT2_INTFLAGS _SFR_MEM8(0x001B) - -/* VPORT3 - Virtual Port 3 */ -#define VPORT3_DIR _SFR_MEM8(0x001C) -#define VPORT3_OUT _SFR_MEM8(0x001D) -#define VPORT3_IN _SFR_MEM8(0x001E) -#define VPORT3_INTFLAGS _SFR_MEM8(0x001F) - -/* OCD - On-Chip Debug System */ -#define OCD_OCDR0 _SFR_MEM8(0x002E) -#define OCD_OCDR1 _SFR_MEM8(0x002F) - -/* CPU - CPU Registers */ -#define CPU_CCP _SFR_MEM8(0x0034) -#define CPU_RAMPD _SFR_MEM8(0x0038) -#define CPU_RAMPX _SFR_MEM8(0x0039) -#define CPU_RAMPY _SFR_MEM8(0x003A) -#define CPU_RAMPZ _SFR_MEM8(0x003B) -#define CPU_EIND _SFR_MEM8(0x003C) -#define CPU_SPL _SFR_MEM8(0x003D) -#define CPU_SPH _SFR_MEM8(0x003E) -#define CPU_SREG _SFR_MEM8(0x003F) - -/* CLK - Clock System */ -#define CLK_CTRL _SFR_MEM8(0x0040) -#define CLK_PSCTRL _SFR_MEM8(0x0041) -#define CLK_LOCK _SFR_MEM8(0x0042) -#define CLK_RTCCTRL _SFR_MEM8(0x0043) - -/* SLEEP - Sleep Controller */ -#define SLEEP_CTRL _SFR_MEM8(0x0048) - -/* OSC - Oscillator Control */ -#define OSC_CTRL _SFR_MEM8(0x0050) -#define OSC_STATUS _SFR_MEM8(0x0051) -#define OSC_XOSCCTRL _SFR_MEM8(0x0052) -#define OSC_XOSCFAIL _SFR_MEM8(0x0053) -#define OSC_RC32KCAL _SFR_MEM8(0x0054) -#define OSC_PLLCTRL _SFR_MEM8(0x0055) -#define OSC_DFLLCTRL _SFR_MEM8(0x0056) - -/* DFLLRC32M - DFLL for 32MHz RC Oscillator */ -#define DFLLRC32M_CTRL _SFR_MEM8(0x0060) -#define DFLLRC32M_CALA _SFR_MEM8(0x0062) -#define DFLLRC32M_CALB _SFR_MEM8(0x0063) -#define DFLLRC32M_COMP0 _SFR_MEM8(0x0064) -#define DFLLRC32M_COMP1 _SFR_MEM8(0x0065) -#define DFLLRC32M_COMP2 _SFR_MEM8(0x0066) - -/* DFLLRC2M - DFLL for 2MHz RC Oscillator */ -#define DFLLRC2M_CTRL _SFR_MEM8(0x0068) -#define DFLLRC2M_CALA _SFR_MEM8(0x006A) -#define DFLLRC2M_CALB _SFR_MEM8(0x006B) -#define DFLLRC2M_COMP0 _SFR_MEM8(0x006C) -#define DFLLRC2M_COMP1 _SFR_MEM8(0x006D) -#define DFLLRC2M_COMP2 _SFR_MEM8(0x006E) - -/* PR - Power Reduction */ -#define PR_PRGEN _SFR_MEM8(0x0070) -#define PR_PRPA _SFR_MEM8(0x0071) -#define PR_PRPB _SFR_MEM8(0x0072) -#define PR_PRPC _SFR_MEM8(0x0073) -#define PR_PRPD _SFR_MEM8(0x0074) -#define PR_PRPE _SFR_MEM8(0x0075) -#define PR_PRPF _SFR_MEM8(0x0076) - -/* RST - Reset Controller */ -#define RST_STATUS _SFR_MEM8(0x0078) -#define RST_CTRL _SFR_MEM8(0x0079) - -/* WDT - Watch-Dog Timer */ -#define WDT_CTRL _SFR_MEM8(0x0080) -#define WDT_WINCTRL _SFR_MEM8(0x0081) -#define WDT_STATUS _SFR_MEM8(0x0082) - -/* MCU - MCU Control */ -#define MCU_DEVID0 _SFR_MEM8(0x0090) -#define MCU_DEVID1 _SFR_MEM8(0x0091) -#define MCU_DEVID2 _SFR_MEM8(0x0092) -#define MCU_REVID _SFR_MEM8(0x0093) -#define MCU_JTAGUID _SFR_MEM8(0x0094) -#define MCU_MCUCR _SFR_MEM8(0x0096) -#define MCU_EVSYSLOCK _SFR_MEM8(0x0098) -#define MCU_AWEXLOCK _SFR_MEM8(0x0099) - -/* PMIC - Programmable Interrupt Controller */ -#define PMIC_STATUS _SFR_MEM8(0x00A0) -#define PMIC_INTPRI _SFR_MEM8(0x00A1) -#define PMIC_CTRL _SFR_MEM8(0x00A2) - -/* PORTCFG - Port Configuration */ -#define PORTCFG_MPCMASK _SFR_MEM8(0x00B0) -#define PORTCFG_VPCTRLA _SFR_MEM8(0x00B2) -#define PORTCFG_VPCTRLB _SFR_MEM8(0x00B3) -#define PORTCFG_CLKEVOUT _SFR_MEM8(0x00B4) - -/* AES - AES Crypto Module */ -#define AES_CTRL _SFR_MEM8(0x00C0) -#define AES_STATUS _SFR_MEM8(0x00C1) -#define AES_STATE _SFR_MEM8(0x00C2) -#define AES_KEY _SFR_MEM8(0x00C3) -#define AES_INTCTRL _SFR_MEM8(0x00C4) - -/* DMA - DMA Controller */ -#define DMA_CTRL _SFR_MEM8(0x0100) -#define DMA_INTFLAGS _SFR_MEM8(0x0103) -#define DMA_STATUS _SFR_MEM8(0x0104) -#define DMA_TEMP _SFR_MEM16(0x0106) -#define DMA_CH0_CTRLA _SFR_MEM8(0x0110) -#define DMA_CH0_CTRLB _SFR_MEM8(0x0111) -#define DMA_CH0_ADDRCTRL _SFR_MEM8(0x0112) -#define DMA_CH0_TRIGSRC _SFR_MEM8(0x0113) -#define DMA_CH0_TRFCNT _SFR_MEM16(0x0114) -#define DMA_CH0_REPCNT _SFR_MEM8(0x0116) -#define DMA_CH0_SRCADDR0 _SFR_MEM8(0x0118) -#define DMA_CH0_SRCADDR1 _SFR_MEM8(0x0119) -#define DMA_CH0_SRCADDR2 _SFR_MEM8(0x011A) -#define DMA_CH0_DESTADDR0 _SFR_MEM8(0x011C) -#define DMA_CH0_DESTADDR1 _SFR_MEM8(0x011D) -#define DMA_CH0_DESTADDR2 _SFR_MEM8(0x011E) -#define DMA_CH1_CTRLA _SFR_MEM8(0x0120) -#define DMA_CH1_CTRLB _SFR_MEM8(0x0121) -#define DMA_CH1_ADDRCTRL _SFR_MEM8(0x0122) -#define DMA_CH1_TRIGSRC _SFR_MEM8(0x0123) -#define DMA_CH1_TRFCNT _SFR_MEM16(0x0124) -#define DMA_CH1_REPCNT _SFR_MEM8(0x0126) -#define DMA_CH1_SRCADDR0 _SFR_MEM8(0x0128) -#define DMA_CH1_SRCADDR1 _SFR_MEM8(0x0129) -#define DMA_CH1_SRCADDR2 _SFR_MEM8(0x012A) -#define DMA_CH1_DESTADDR0 _SFR_MEM8(0x012C) -#define DMA_CH1_DESTADDR1 _SFR_MEM8(0x012D) -#define DMA_CH1_DESTADDR2 _SFR_MEM8(0x012E) -#define DMA_CH2_CTRLA _SFR_MEM8(0x0130) -#define DMA_CH2_CTRLB _SFR_MEM8(0x0131) -#define DMA_CH2_ADDRCTRL _SFR_MEM8(0x0132) -#define DMA_CH2_TRIGSRC _SFR_MEM8(0x0133) -#define DMA_CH2_TRFCNT _SFR_MEM16(0x0134) -#define DMA_CH2_REPCNT _SFR_MEM8(0x0136) -#define DMA_CH2_SRCADDR0 _SFR_MEM8(0x0138) -#define DMA_CH2_SRCADDR1 _SFR_MEM8(0x0139) -#define DMA_CH2_SRCADDR2 _SFR_MEM8(0x013A) -#define DMA_CH2_DESTADDR0 _SFR_MEM8(0x013C) -#define DMA_CH2_DESTADDR1 _SFR_MEM8(0x013D) -#define DMA_CH2_DESTADDR2 _SFR_MEM8(0x013E) -#define DMA_CH3_CTRLA _SFR_MEM8(0x0140) -#define DMA_CH3_CTRLB _SFR_MEM8(0x0141) -#define DMA_CH3_ADDRCTRL _SFR_MEM8(0x0142) -#define DMA_CH3_TRIGSRC _SFR_MEM8(0x0143) -#define DMA_CH3_TRFCNT _SFR_MEM16(0x0144) -#define DMA_CH3_REPCNT _SFR_MEM8(0x0146) -#define DMA_CH3_SRCADDR0 _SFR_MEM8(0x0148) -#define DMA_CH3_SRCADDR1 _SFR_MEM8(0x0149) -#define DMA_CH3_SRCADDR2 _SFR_MEM8(0x014A) -#define DMA_CH3_DESTADDR0 _SFR_MEM8(0x014C) -#define DMA_CH3_DESTADDR1 _SFR_MEM8(0x014D) -#define DMA_CH3_DESTADDR2 _SFR_MEM8(0x014E) - -/* EVSYS - Event System */ -#define EVSYS_CH0MUX _SFR_MEM8(0x0180) -#define EVSYS_CH1MUX _SFR_MEM8(0x0181) -#define EVSYS_CH2MUX _SFR_MEM8(0x0182) -#define EVSYS_CH3MUX _SFR_MEM8(0x0183) -#define EVSYS_CH4MUX _SFR_MEM8(0x0184) -#define EVSYS_CH5MUX _SFR_MEM8(0x0185) -#define EVSYS_CH6MUX _SFR_MEM8(0x0186) -#define EVSYS_CH7MUX _SFR_MEM8(0x0187) -#define EVSYS_CH0CTRL _SFR_MEM8(0x0188) -#define EVSYS_CH1CTRL _SFR_MEM8(0x0189) -#define EVSYS_CH2CTRL _SFR_MEM8(0x018A) -#define EVSYS_CH3CTRL _SFR_MEM8(0x018B) -#define EVSYS_CH4CTRL _SFR_MEM8(0x018C) -#define EVSYS_CH5CTRL _SFR_MEM8(0x018D) -#define EVSYS_CH6CTRL _SFR_MEM8(0x018E) -#define EVSYS_CH7CTRL _SFR_MEM8(0x018F) -#define EVSYS_STROBE _SFR_MEM8(0x0190) -#define EVSYS_DATA _SFR_MEM8(0x0191) - -/* NVM - Non Volatile Memory Controller */ -#define NVM_ADDR0 _SFR_MEM8(0x01C0) -#define NVM_ADDR1 _SFR_MEM8(0x01C1) -#define NVM_ADDR2 _SFR_MEM8(0x01C2) -#define NVM_DATA0 _SFR_MEM8(0x01C4) -#define NVM_DATA1 _SFR_MEM8(0x01C5) -#define NVM_DATA2 _SFR_MEM8(0x01C6) -#define NVM_CMD _SFR_MEM8(0x01CA) -#define NVM_CTRLA _SFR_MEM8(0x01CB) -#define NVM_CTRLB _SFR_MEM8(0x01CC) -#define NVM_INTCTRL _SFR_MEM8(0x01CD) -#define NVM_STATUS _SFR_MEM8(0x01CF) -#define NVM_LOCKBITS _SFR_MEM8(0x01D0) - -/* ADCA - Analog to Digital Converter A */ -#define ADCA_CTRLA _SFR_MEM8(0x0200) -#define ADCA_CTRLB _SFR_MEM8(0x0201) -#define ADCA_REFCTRL _SFR_MEM8(0x0202) -#define ADCA_EVCTRL _SFR_MEM8(0x0203) -#define ADCA_PRESCALER _SFR_MEM8(0x0204) -#define ADCA_INTFLAGS _SFR_MEM8(0x0206) -#define ADCA_CAL _SFR_MEM16(0x020C) -#define ADCA_CH0RES _SFR_MEM16(0x0210) -#define ADCA_CH1RES _SFR_MEM16(0x0212) -#define ADCA_CH2RES _SFR_MEM16(0x0214) -#define ADCA_CH3RES _SFR_MEM16(0x0216) -#define ADCA_CMP _SFR_MEM16(0x0218) -#define ADCA_CH0_CTRL _SFR_MEM8(0x0220) -#define ADCA_CH0_MUXCTRL _SFR_MEM8(0x0221) -#define ADCA_CH0_INTCTRL _SFR_MEM8(0x0222) -#define ADCA_CH0_INTFLAGS _SFR_MEM8(0x0223) -#define ADCA_CH0_RES _SFR_MEM16(0x0224) -#define ADCA_CH1_CTRL _SFR_MEM8(0x0228) -#define ADCA_CH1_MUXCTRL _SFR_MEM8(0x0229) -#define ADCA_CH1_INTCTRL _SFR_MEM8(0x022A) -#define ADCA_CH1_INTFLAGS _SFR_MEM8(0x022B) -#define ADCA_CH1_RES _SFR_MEM16(0x022C) -#define ADCA_CH2_CTRL _SFR_MEM8(0x0230) -#define ADCA_CH2_MUXCTRL _SFR_MEM8(0x0231) -#define ADCA_CH2_INTCTRL _SFR_MEM8(0x0232) -#define ADCA_CH2_INTFLAGS _SFR_MEM8(0x0233) -#define ADCA_CH2_RES _SFR_MEM16(0x0234) -#define ADCA_CH3_CTRL _SFR_MEM8(0x0238) -#define ADCA_CH3_MUXCTRL _SFR_MEM8(0x0239) -#define ADCA_CH3_INTCTRL _SFR_MEM8(0x023A) -#define ADCA_CH3_INTFLAGS _SFR_MEM8(0x023B) -#define ADCA_CH3_RES _SFR_MEM16(0x023C) - -/* DACB - Digital to Analog Converter B */ -#define DACB_CTRLA _SFR_MEM8(0x0320) -#define DACB_CTRLB _SFR_MEM8(0x0321) -#define DACB_CTRLC _SFR_MEM8(0x0322) -#define DACB_EVCTRL _SFR_MEM8(0x0323) -#define DACB_TIMCTRL _SFR_MEM8(0x0324) -#define DACB_STATUS _SFR_MEM8(0x0325) -#define DACB_GAINCAL _SFR_MEM8(0x0328) -#define DACB_OFFSETCAL _SFR_MEM8(0x0329) -#define DACB_CH0DATA _SFR_MEM16(0x0338) -#define DACB_CH1DATA _SFR_MEM16(0x033A) - -/* ACA - Analog Comparator A */ -#define ACA_AC0CTRL _SFR_MEM8(0x0380) -#define ACA_AC1CTRL _SFR_MEM8(0x0381) -#define ACA_AC0MUXCTRL _SFR_MEM8(0x0382) -#define ACA_AC1MUXCTRL _SFR_MEM8(0x0383) -#define ACA_CTRLA _SFR_MEM8(0x0384) -#define ACA_CTRLB _SFR_MEM8(0x0385) -#define ACA_WINCTRL _SFR_MEM8(0x0386) -#define ACA_STATUS _SFR_MEM8(0x0387) - -/* RTC - Real-Time Counter */ -#define RTC_CTRL _SFR_MEM8(0x0400) -#define RTC_STATUS _SFR_MEM8(0x0401) -#define RTC_INTCTRL _SFR_MEM8(0x0402) -#define RTC_INTFLAGS _SFR_MEM8(0x0403) -#define RTC_TEMP _SFR_MEM8(0x0404) -#define RTC_CNT _SFR_MEM16(0x0408) -#define RTC_PER _SFR_MEM16(0x040A) -#define RTC_COMP _SFR_MEM16(0x040C) - -/* TWIC - Two-Wire Interface C */ -#define TWIC_CTRL _SFR_MEM8(0x0480) -#define TWIC_MASTER_CTRLA _SFR_MEM8(0x0481) -#define TWIC_MASTER_CTRLB _SFR_MEM8(0x0482) -#define TWIC_MASTER_CTRLC _SFR_MEM8(0x0483) -#define TWIC_MASTER_STATUS _SFR_MEM8(0x0484) -#define TWIC_MASTER_BAUD _SFR_MEM8(0x0485) -#define TWIC_MASTER_ADDR _SFR_MEM8(0x0486) -#define TWIC_MASTER_DATA _SFR_MEM8(0x0487) -#define TWIC_SLAVE_CTRLA _SFR_MEM8(0x0488) -#define TWIC_SLAVE_CTRLB _SFR_MEM8(0x0489) -#define TWIC_SLAVE_STATUS _SFR_MEM8(0x048A) -#define TWIC_SLAVE_ADDR _SFR_MEM8(0x048B) -#define TWIC_SLAVE_DATA _SFR_MEM8(0x048C) -#define TWIC_SLAVE_ADDRMASK _SFR_MEM8(0x048D) - -/* TWIE - Two-Wire Interface E */ -#define TWIE_CTRL _SFR_MEM8(0x04A0) -#define TWIE_MASTER_CTRLA _SFR_MEM8(0x04A1) -#define TWIE_MASTER_CTRLB _SFR_MEM8(0x04A2) -#define TWIE_MASTER_CTRLC _SFR_MEM8(0x04A3) -#define TWIE_MASTER_STATUS _SFR_MEM8(0x04A4) -#define TWIE_MASTER_BAUD _SFR_MEM8(0x04A5) -#define TWIE_MASTER_ADDR _SFR_MEM8(0x04A6) -#define TWIE_MASTER_DATA _SFR_MEM8(0x04A7) -#define TWIE_SLAVE_CTRLA _SFR_MEM8(0x04A8) -#define TWIE_SLAVE_CTRLB _SFR_MEM8(0x04A9) -#define TWIE_SLAVE_STATUS _SFR_MEM8(0x04AA) -#define TWIE_SLAVE_ADDR _SFR_MEM8(0x04AB) -#define TWIE_SLAVE_DATA _SFR_MEM8(0x04AC) -#define TWIE_SLAVE_ADDRMASK _SFR_MEM8(0x04AD) - -/* PORTA - Port A */ -#define PORTA_DIR _SFR_MEM8(0x0600) -#define PORTA_DIRSET _SFR_MEM8(0x0601) -#define PORTA_DIRCLR _SFR_MEM8(0x0602) -#define PORTA_DIRTGL _SFR_MEM8(0x0603) -#define PORTA_OUT _SFR_MEM8(0x0604) -#define PORTA_OUTSET _SFR_MEM8(0x0605) -#define PORTA_OUTCLR _SFR_MEM8(0x0606) -#define PORTA_OUTTGL _SFR_MEM8(0x0607) -#define PORTA_IN _SFR_MEM8(0x0608) -#define PORTA_INTCTRL _SFR_MEM8(0x0609) -#define PORTA_INT0MASK _SFR_MEM8(0x060A) -#define PORTA_INT1MASK _SFR_MEM8(0x060B) -#define PORTA_INTFLAGS _SFR_MEM8(0x060C) -#define PORTA_PIN0CTRL _SFR_MEM8(0x0610) -#define PORTA_PIN1CTRL _SFR_MEM8(0x0611) -#define PORTA_PIN2CTRL _SFR_MEM8(0x0612) -#define PORTA_PIN3CTRL _SFR_MEM8(0x0613) -#define PORTA_PIN4CTRL _SFR_MEM8(0x0614) -#define PORTA_PIN5CTRL _SFR_MEM8(0x0615) -#define PORTA_PIN6CTRL _SFR_MEM8(0x0616) -#define PORTA_PIN7CTRL _SFR_MEM8(0x0617) - -/* PORTB - Port B */ -#define PORTB_DIR _SFR_MEM8(0x0620) -#define PORTB_DIRSET _SFR_MEM8(0x0621) -#define PORTB_DIRCLR _SFR_MEM8(0x0622) -#define PORTB_DIRTGL _SFR_MEM8(0x0623) -#define PORTB_OUT _SFR_MEM8(0x0624) -#define PORTB_OUTSET _SFR_MEM8(0x0625) -#define PORTB_OUTCLR _SFR_MEM8(0x0626) -#define PORTB_OUTTGL _SFR_MEM8(0x0627) -#define PORTB_IN _SFR_MEM8(0x0628) -#define PORTB_INTCTRL _SFR_MEM8(0x0629) -#define PORTB_INT0MASK _SFR_MEM8(0x062A) -#define PORTB_INT1MASK _SFR_MEM8(0x062B) -#define PORTB_INTFLAGS _SFR_MEM8(0x062C) -#define PORTB_PIN0CTRL _SFR_MEM8(0x0630) -#define PORTB_PIN1CTRL _SFR_MEM8(0x0631) -#define PORTB_PIN2CTRL _SFR_MEM8(0x0632) -#define PORTB_PIN3CTRL _SFR_MEM8(0x0633) -#define PORTB_PIN4CTRL _SFR_MEM8(0x0634) -#define PORTB_PIN5CTRL _SFR_MEM8(0x0635) -#define PORTB_PIN6CTRL _SFR_MEM8(0x0636) -#define PORTB_PIN7CTRL _SFR_MEM8(0x0637) - -/* PORTC - Port C */ -#define PORTC_DIR _SFR_MEM8(0x0640) -#define PORTC_DIRSET _SFR_MEM8(0x0641) -#define PORTC_DIRCLR _SFR_MEM8(0x0642) -#define PORTC_DIRTGL _SFR_MEM8(0x0643) -#define PORTC_OUT _SFR_MEM8(0x0644) -#define PORTC_OUTSET _SFR_MEM8(0x0645) -#define PORTC_OUTCLR _SFR_MEM8(0x0646) -#define PORTC_OUTTGL _SFR_MEM8(0x0647) -#define PORTC_IN _SFR_MEM8(0x0648) -#define PORTC_INTCTRL _SFR_MEM8(0x0649) -#define PORTC_INT0MASK _SFR_MEM8(0x064A) -#define PORTC_INT1MASK _SFR_MEM8(0x064B) -#define PORTC_INTFLAGS _SFR_MEM8(0x064C) -#define PORTC_PIN0CTRL _SFR_MEM8(0x0650) -#define PORTC_PIN1CTRL _SFR_MEM8(0x0651) -#define PORTC_PIN2CTRL _SFR_MEM8(0x0652) -#define PORTC_PIN3CTRL _SFR_MEM8(0x0653) -#define PORTC_PIN4CTRL _SFR_MEM8(0x0654) -#define PORTC_PIN5CTRL _SFR_MEM8(0x0655) -#define PORTC_PIN6CTRL _SFR_MEM8(0x0656) -#define PORTC_PIN7CTRL _SFR_MEM8(0x0657) - -/* PORTD - Port D */ -#define PORTD_DIR _SFR_MEM8(0x0660) -#define PORTD_DIRSET _SFR_MEM8(0x0661) -#define PORTD_DIRCLR _SFR_MEM8(0x0662) -#define PORTD_DIRTGL _SFR_MEM8(0x0663) -#define PORTD_OUT _SFR_MEM8(0x0664) -#define PORTD_OUTSET _SFR_MEM8(0x0665) -#define PORTD_OUTCLR _SFR_MEM8(0x0666) -#define PORTD_OUTTGL _SFR_MEM8(0x0667) -#define PORTD_IN _SFR_MEM8(0x0668) -#define PORTD_INTCTRL _SFR_MEM8(0x0669) -#define PORTD_INT0MASK _SFR_MEM8(0x066A) -#define PORTD_INT1MASK _SFR_MEM8(0x066B) -#define PORTD_INTFLAGS _SFR_MEM8(0x066C) -#define PORTD_PIN0CTRL _SFR_MEM8(0x0670) -#define PORTD_PIN1CTRL _SFR_MEM8(0x0671) -#define PORTD_PIN2CTRL _SFR_MEM8(0x0672) -#define PORTD_PIN3CTRL _SFR_MEM8(0x0673) -#define PORTD_PIN4CTRL _SFR_MEM8(0x0674) -#define PORTD_PIN5CTRL _SFR_MEM8(0x0675) -#define PORTD_PIN6CTRL _SFR_MEM8(0x0676) -#define PORTD_PIN7CTRL _SFR_MEM8(0x0677) - -/* PORTE - Port E */ -#define PORTE_DIR _SFR_MEM8(0x0680) -#define PORTE_DIRSET _SFR_MEM8(0x0681) -#define PORTE_DIRCLR _SFR_MEM8(0x0682) -#define PORTE_DIRTGL _SFR_MEM8(0x0683) -#define PORTE_OUT _SFR_MEM8(0x0684) -#define PORTE_OUTSET _SFR_MEM8(0x0685) -#define PORTE_OUTCLR _SFR_MEM8(0x0686) -#define PORTE_OUTTGL _SFR_MEM8(0x0687) -#define PORTE_IN _SFR_MEM8(0x0688) -#define PORTE_INTCTRL _SFR_MEM8(0x0689) -#define PORTE_INT0MASK _SFR_MEM8(0x068A) -#define PORTE_INT1MASK _SFR_MEM8(0x068B) -#define PORTE_INTFLAGS _SFR_MEM8(0x068C) -#define PORTE_PIN0CTRL _SFR_MEM8(0x0690) -#define PORTE_PIN1CTRL _SFR_MEM8(0x0691) -#define PORTE_PIN2CTRL _SFR_MEM8(0x0692) -#define PORTE_PIN3CTRL _SFR_MEM8(0x0693) -#define PORTE_PIN4CTRL _SFR_MEM8(0x0694) -#define PORTE_PIN5CTRL _SFR_MEM8(0x0695) -#define PORTE_PIN6CTRL _SFR_MEM8(0x0696) -#define PORTE_PIN7CTRL _SFR_MEM8(0x0697) - -/* PORTR - Port R */ -#define PORTR_DIR _SFR_MEM8(0x07E0) -#define PORTR_DIRSET _SFR_MEM8(0x07E1) -#define PORTR_DIRCLR _SFR_MEM8(0x07E2) -#define PORTR_DIRTGL _SFR_MEM8(0x07E3) -#define PORTR_OUT _SFR_MEM8(0x07E4) -#define PORTR_OUTSET _SFR_MEM8(0x07E5) -#define PORTR_OUTCLR _SFR_MEM8(0x07E6) -#define PORTR_OUTTGL _SFR_MEM8(0x07E7) -#define PORTR_IN _SFR_MEM8(0x07E8) -#define PORTR_INTCTRL _SFR_MEM8(0x07E9) -#define PORTR_INT0MASK _SFR_MEM8(0x07EA) -#define PORTR_INT1MASK _SFR_MEM8(0x07EB) -#define PORTR_INTFLAGS _SFR_MEM8(0x07EC) -#define PORTR_PIN0CTRL _SFR_MEM8(0x07F0) -#define PORTR_PIN1CTRL _SFR_MEM8(0x07F1) -#define PORTR_PIN2CTRL _SFR_MEM8(0x07F2) -#define PORTR_PIN3CTRL _SFR_MEM8(0x07F3) -#define PORTR_PIN4CTRL _SFR_MEM8(0x07F4) -#define PORTR_PIN5CTRL _SFR_MEM8(0x07F5) -#define PORTR_PIN6CTRL _SFR_MEM8(0x07F6) -#define PORTR_PIN7CTRL _SFR_MEM8(0x07F7) - -/* TCC0 - Timer/Counter C0 */ -#define TCC0_CTRLA _SFR_MEM8(0x0800) -#define TCC0_CTRLB _SFR_MEM8(0x0801) -#define TCC0_CTRLC _SFR_MEM8(0x0802) -#define TCC0_CTRLD _SFR_MEM8(0x0803) -#define TCC0_CTRLE _SFR_MEM8(0x0804) -#define TCC0_INTCTRLA _SFR_MEM8(0x0806) -#define TCC0_INTCTRLB _SFR_MEM8(0x0807) -#define TCC0_CTRLFCLR _SFR_MEM8(0x0808) -#define TCC0_CTRLFSET _SFR_MEM8(0x0809) -#define TCC0_CTRLGCLR _SFR_MEM8(0x080A) -#define TCC0_CTRLGSET _SFR_MEM8(0x080B) -#define TCC0_INTFLAGS _SFR_MEM8(0x080C) -#define TCC0_TEMP _SFR_MEM8(0x080F) -#define TCC0_CNT _SFR_MEM16(0x0820) -#define TCC0_PER _SFR_MEM16(0x0826) -#define TCC0_CCA _SFR_MEM16(0x0828) -#define TCC0_CCB _SFR_MEM16(0x082A) -#define TCC0_CCC _SFR_MEM16(0x082C) -#define TCC0_CCD _SFR_MEM16(0x082E) -#define TCC0_PERBUF _SFR_MEM16(0x0836) -#define TCC0_CCABUF _SFR_MEM16(0x0838) -#define TCC0_CCBBUF _SFR_MEM16(0x083A) -#define TCC0_CCCBUF _SFR_MEM16(0x083C) -#define TCC0_CCDBUF _SFR_MEM16(0x083E) - -/* TCC1 - Timer/Counter C1 */ -#define TCC1_CTRLA _SFR_MEM8(0x0840) -#define TCC1_CTRLB _SFR_MEM8(0x0841) -#define TCC1_CTRLC _SFR_MEM8(0x0842) -#define TCC1_CTRLD _SFR_MEM8(0x0843) -#define TCC1_CTRLE _SFR_MEM8(0x0844) -#define TCC1_INTCTRLA _SFR_MEM8(0x0846) -#define TCC1_INTCTRLB _SFR_MEM8(0x0847) -#define TCC1_CTRLFCLR _SFR_MEM8(0x0848) -#define TCC1_CTRLFSET _SFR_MEM8(0x0849) -#define TCC1_CTRLGCLR _SFR_MEM8(0x084A) -#define TCC1_CTRLGSET _SFR_MEM8(0x084B) -#define TCC1_INTFLAGS _SFR_MEM8(0x084C) -#define TCC1_TEMP _SFR_MEM8(0x084F) -#define TCC1_CNT _SFR_MEM16(0x0860) -#define TCC1_PER _SFR_MEM16(0x0866) -#define TCC1_CCA _SFR_MEM16(0x0868) -#define TCC1_CCB _SFR_MEM16(0x086A) -#define TCC1_PERBUF _SFR_MEM16(0x0876) -#define TCC1_CCABUF _SFR_MEM16(0x0878) -#define TCC1_CCBBUF _SFR_MEM16(0x087A) - -/* AWEXC - Advanced Waveform Extension C */ -#define AWEXC_CTRL _SFR_MEM8(0x0880) -#define AWEXC_FDEMASK _SFR_MEM8(0x0882) -#define AWEXC_FDCTRL _SFR_MEM8(0x0883) -#define AWEXC_STATUS _SFR_MEM8(0x0884) -#define AWEXC_DTBOTH _SFR_MEM8(0x0886) -#define AWEXC_DTBOTHBUF _SFR_MEM8(0x0887) -#define AWEXC_DTLS _SFR_MEM8(0x0888) -#define AWEXC_DTHS _SFR_MEM8(0x0889) -#define AWEXC_DTLSBUF _SFR_MEM8(0x088A) -#define AWEXC_DTHSBUF _SFR_MEM8(0x088B) -#define AWEXC_OUTOVEN _SFR_MEM8(0x088C) - -/* HIRESC - High-Resolution Extension C */ -#define HIRESC_CTRLA _SFR_MEM8(0x0890) - -/* USARTC0 - Universal Asynchronous Receiver-Transmitter C0 */ -#define USARTC0_DATA _SFR_MEM8(0x08A0) -#define USARTC0_STATUS _SFR_MEM8(0x08A1) -#define USARTC0_CTRLA _SFR_MEM8(0x08A3) -#define USARTC0_CTRLB _SFR_MEM8(0x08A4) -#define USARTC0_CTRLC _SFR_MEM8(0x08A5) -#define USARTC0_BAUDCTRLA _SFR_MEM8(0x08A6) -#define USARTC0_BAUDCTRLB _SFR_MEM8(0x08A7) - -/* USARTC1 - Universal Asynchronous Receiver-Transmitter C1 */ -#define USARTC1_DATA _SFR_MEM8(0x08B0) -#define USARTC1_STATUS _SFR_MEM8(0x08B1) -#define USARTC1_CTRLA _SFR_MEM8(0x08B3) -#define USARTC1_CTRLB _SFR_MEM8(0x08B4) -#define USARTC1_CTRLC _SFR_MEM8(0x08B5) -#define USARTC1_BAUDCTRLA _SFR_MEM8(0x08B6) -#define USARTC1_BAUDCTRLB _SFR_MEM8(0x08B7) - -/* SPIC - Serial Peripheral Interface C */ -#define SPIC_CTRL _SFR_MEM8(0x08C0) -#define SPIC_INTCTRL _SFR_MEM8(0x08C1) -#define SPIC_STATUS _SFR_MEM8(0x08C2) -#define SPIC_DATA _SFR_MEM8(0x08C3) - -/* IRCOM - IR Communication Module */ -#define IRCOM_CTRL _SFR_MEM8(0x08F8) -#define IRCOM_TXPLCTRL _SFR_MEM8(0x08F9) -#define IRCOM_RXPLCTRL _SFR_MEM8(0x08FA) - -/* TCD0 - Timer/Counter D0 */ -#define TCD0_CTRLA _SFR_MEM8(0x0900) -#define TCD0_CTRLB _SFR_MEM8(0x0901) -#define TCD0_CTRLC _SFR_MEM8(0x0902) -#define TCD0_CTRLD _SFR_MEM8(0x0903) -#define TCD0_CTRLE _SFR_MEM8(0x0904) -#define TCD0_INTCTRLA _SFR_MEM8(0x0906) -#define TCD0_INTCTRLB _SFR_MEM8(0x0907) -#define TCD0_CTRLFCLR _SFR_MEM8(0x0908) -#define TCD0_CTRLFSET _SFR_MEM8(0x0909) -#define TCD0_CTRLGCLR _SFR_MEM8(0x090A) -#define TCD0_CTRLGSET _SFR_MEM8(0x090B) -#define TCD0_INTFLAGS _SFR_MEM8(0x090C) -#define TCD0_TEMP _SFR_MEM8(0x090F) -#define TCD0_CNT _SFR_MEM16(0x0920) -#define TCD0_PER _SFR_MEM16(0x0926) -#define TCD0_CCA _SFR_MEM16(0x0928) -#define TCD0_CCB _SFR_MEM16(0x092A) -#define TCD0_CCC _SFR_MEM16(0x092C) -#define TCD0_CCD _SFR_MEM16(0x092E) -#define TCD0_PERBUF _SFR_MEM16(0x0936) -#define TCD0_CCABUF _SFR_MEM16(0x0938) -#define TCD0_CCBBUF _SFR_MEM16(0x093A) -#define TCD0_CCCBUF _SFR_MEM16(0x093C) -#define TCD0_CCDBUF _SFR_MEM16(0x093E) - -/* TCD1 - Timer/Counter D1 */ -#define TCD1_CTRLA _SFR_MEM8(0x0940) -#define TCD1_CTRLB _SFR_MEM8(0x0941) -#define TCD1_CTRLC _SFR_MEM8(0x0942) -#define TCD1_CTRLD _SFR_MEM8(0x0943) -#define TCD1_CTRLE _SFR_MEM8(0x0944) -#define TCD1_INTCTRLA _SFR_MEM8(0x0946) -#define TCD1_INTCTRLB _SFR_MEM8(0x0947) -#define TCD1_CTRLFCLR _SFR_MEM8(0x0948) -#define TCD1_CTRLFSET _SFR_MEM8(0x0949) -#define TCD1_CTRLGCLR _SFR_MEM8(0x094A) -#define TCD1_CTRLGSET _SFR_MEM8(0x094B) -#define TCD1_INTFLAGS _SFR_MEM8(0x094C) -#define TCD1_TEMP _SFR_MEM8(0x094F) -#define TCD1_CNT _SFR_MEM16(0x0960) -#define TCD1_PER _SFR_MEM16(0x0966) -#define TCD1_CCA _SFR_MEM16(0x0968) -#define TCD1_CCB _SFR_MEM16(0x096A) -#define TCD1_PERBUF _SFR_MEM16(0x0976) -#define TCD1_CCABUF _SFR_MEM16(0x0978) -#define TCD1_CCBBUF _SFR_MEM16(0x097A) - -/* HIRESD - High-Resolution Extension D */ -#define HIRESD_CTRLA _SFR_MEM8(0x0990) - -/* USARTD0 - Universal Asynchronous Receiver-Transmitter D0 */ -#define USARTD0_DATA _SFR_MEM8(0x09A0) -#define USARTD0_STATUS _SFR_MEM8(0x09A1) -#define USARTD0_CTRLA _SFR_MEM8(0x09A3) -#define USARTD0_CTRLB _SFR_MEM8(0x09A4) -#define USARTD0_CTRLC _SFR_MEM8(0x09A5) -#define USARTD0_BAUDCTRLA _SFR_MEM8(0x09A6) -#define USARTD0_BAUDCTRLB _SFR_MEM8(0x09A7) - -/* USARTD1 - Universal Asynchronous Receiver-Transmitter D1 */ -#define USARTD1_DATA _SFR_MEM8(0x09B0) -#define USARTD1_STATUS _SFR_MEM8(0x09B1) -#define USARTD1_CTRLA _SFR_MEM8(0x09B3) -#define USARTD1_CTRLB _SFR_MEM8(0x09B4) -#define USARTD1_CTRLC _SFR_MEM8(0x09B5) -#define USARTD1_BAUDCTRLA _SFR_MEM8(0x09B6) -#define USARTD1_BAUDCTRLB _SFR_MEM8(0x09B7) - -/* SPID - Serial Peripheral Interface D */ -#define SPID_CTRL _SFR_MEM8(0x09C0) -#define SPID_INTCTRL _SFR_MEM8(0x09C1) -#define SPID_STATUS _SFR_MEM8(0x09C2) -#define SPID_DATA _SFR_MEM8(0x09C3) - -/* TCE0 - Timer/Counter E0 */ -#define TCE0_CTRLA _SFR_MEM8(0x0A00) -#define TCE0_CTRLB _SFR_MEM8(0x0A01) -#define TCE0_CTRLC _SFR_MEM8(0x0A02) -#define TCE0_CTRLD _SFR_MEM8(0x0A03) -#define TCE0_CTRLE _SFR_MEM8(0x0A04) -#define TCE0_INTCTRLA _SFR_MEM8(0x0A06) -#define TCE0_INTCTRLB _SFR_MEM8(0x0A07) -#define TCE0_CTRLFCLR _SFR_MEM8(0x0A08) -#define TCE0_CTRLFSET _SFR_MEM8(0x0A09) -#define TCE0_CTRLGCLR _SFR_MEM8(0x0A0A) -#define TCE0_CTRLGSET _SFR_MEM8(0x0A0B) -#define TCE0_INTFLAGS _SFR_MEM8(0x0A0C) -#define TCE0_TEMP _SFR_MEM8(0x0A0F) -#define TCE0_CNT _SFR_MEM16(0x0A20) -#define TCE0_PER _SFR_MEM16(0x0A26) -#define TCE0_CCA _SFR_MEM16(0x0A28) -#define TCE0_CCB _SFR_MEM16(0x0A2A) -#define TCE0_CCC _SFR_MEM16(0x0A2C) -#define TCE0_CCD _SFR_MEM16(0x0A2E) -#define TCE0_PERBUF _SFR_MEM16(0x0A36) -#define TCE0_CCABUF _SFR_MEM16(0x0A38) -#define TCE0_CCBBUF _SFR_MEM16(0x0A3A) -#define TCE0_CCCBUF _SFR_MEM16(0x0A3C) -#define TCE0_CCDBUF _SFR_MEM16(0x0A3E) - -/* HIRESE - High-Resolution Extension E */ -#define HIRESE_CTRLA _SFR_MEM8(0x0A90) - -/* USARTE0 - Universal Asynchronous Receiver-Transmitter E0 */ -#define USARTE0_DATA _SFR_MEM8(0x0AA0) -#define USARTE0_STATUS _SFR_MEM8(0x0AA1) -#define USARTE0_CTRLA _SFR_MEM8(0x0AA3) -#define USARTE0_CTRLB _SFR_MEM8(0x0AA4) -#define USARTE0_CTRLC _SFR_MEM8(0x0AA5) -#define USARTE0_BAUDCTRLA _SFR_MEM8(0x0AA6) -#define USARTE0_BAUDCTRLB _SFR_MEM8(0x0AA7) - - - -/*================== Bitfield Definitions ================== */ - -/* XOCD - On-Chip Debug System */ -/* OCD.OCDR1 bit masks and bit positions */ -#define OCD_OCDRD_bm 0x01 /* OCDR Dirty bit mask. */ -#define OCD_OCDRD_bp 0 /* OCDR Dirty bit position. */ - - -/* CPU - CPU */ -/* CPU.CCP bit masks and bit positions */ -#define CPU_CCP_gm 0xFF /* CCP signature group mask. */ -#define CPU_CCP_gp 0 /* CCP signature group position. */ -#define CPU_CCP0_bm (1<<0) /* CCP signature bit 0 mask. */ -#define CPU_CCP0_bp 0 /* CCP signature bit 0 position. */ -#define CPU_CCP1_bm (1<<1) /* CCP signature bit 1 mask. */ -#define CPU_CCP1_bp 1 /* CCP signature bit 1 position. */ -#define CPU_CCP2_bm (1<<2) /* CCP signature bit 2 mask. */ -#define CPU_CCP2_bp 2 /* CCP signature bit 2 position. */ -#define CPU_CCP3_bm (1<<3) /* CCP signature bit 3 mask. */ -#define CPU_CCP3_bp 3 /* CCP signature bit 3 position. */ -#define CPU_CCP4_bm (1<<4) /* CCP signature bit 4 mask. */ -#define CPU_CCP4_bp 4 /* CCP signature bit 4 position. */ -#define CPU_CCP5_bm (1<<5) /* CCP signature bit 5 mask. */ -#define CPU_CCP5_bp 5 /* CCP signature bit 5 position. */ -#define CPU_CCP6_bm (1<<6) /* CCP signature bit 6 mask. */ -#define CPU_CCP6_bp 6 /* CCP signature bit 6 position. */ -#define CPU_CCP7_bm (1<<7) /* CCP signature bit 7 mask. */ -#define CPU_CCP7_bp 7 /* CCP signature bit 7 position. */ - - -/* CPU.SREG bit masks and bit positions */ -#define CPU_I_bm 0x80 /* Global Interrupt Enable Flag bit mask. */ -#define CPU_I_bp 7 /* Global Interrupt Enable Flag bit position. */ - -#define CPU_T_bm 0x40 /* Transfer Bit bit mask. */ -#define CPU_T_bp 6 /* Transfer Bit bit position. */ - -#define CPU_H_bm 0x20 /* Half Carry Flag bit mask. */ -#define CPU_H_bp 5 /* Half Carry Flag bit position. */ - -#define CPU_S_bm 0x10 /* N Exclusive Or V Flag bit mask. */ -#define CPU_S_bp 4 /* N Exclusive Or V Flag bit position. */ - -#define CPU_V_bm 0x08 /* Two's Complement Overflow Flag bit mask. */ -#define CPU_V_bp 3 /* Two's Complement Overflow Flag bit position. */ - -#define CPU_N_bm 0x04 /* Negative Flag bit mask. */ -#define CPU_N_bp 2 /* Negative Flag bit position. */ - -#define CPU_Z_bm 0x02 /* Zero Flag bit mask. */ -#define CPU_Z_bp 1 /* Zero Flag bit position. */ - -#define CPU_C_bm 0x01 /* Carry Flag bit mask. */ -#define CPU_C_bp 0 /* Carry Flag bit position. */ - - -/* CLK - Clock System */ -/* CLK.CTRL bit masks and bit positions */ -#define CLK_SCLKSEL_gm 0x07 /* System Clock Selection group mask. */ -#define CLK_SCLKSEL_gp 0 /* System Clock Selection group position. */ -#define CLK_SCLKSEL0_bm (1<<0) /* System Clock Selection bit 0 mask. */ -#define CLK_SCLKSEL0_bp 0 /* System Clock Selection bit 0 position. */ -#define CLK_SCLKSEL1_bm (1<<1) /* System Clock Selection bit 1 mask. */ -#define CLK_SCLKSEL1_bp 1 /* System Clock Selection bit 1 position. */ -#define CLK_SCLKSEL2_bm (1<<2) /* System Clock Selection bit 2 mask. */ -#define CLK_SCLKSEL2_bp 2 /* System Clock Selection bit 2 position. */ - - -/* CLK.PSCTRL bit masks and bit positions */ -#define CLK_PSADIV_gm 0x7C /* Prescaler A Division Factor group mask. */ -#define CLK_PSADIV_gp 2 /* Prescaler A Division Factor group position. */ -#define CLK_PSADIV0_bm (1<<2) /* Prescaler A Division Factor bit 0 mask. */ -#define CLK_PSADIV0_bp 2 /* Prescaler A Division Factor bit 0 position. */ -#define CLK_PSADIV1_bm (1<<3) /* Prescaler A Division Factor bit 1 mask. */ -#define CLK_PSADIV1_bp 3 /* Prescaler A Division Factor bit 1 position. */ -#define CLK_PSADIV2_bm (1<<4) /* Prescaler A Division Factor bit 2 mask. */ -#define CLK_PSADIV2_bp 4 /* Prescaler A Division Factor bit 2 position. */ -#define CLK_PSADIV3_bm (1<<5) /* Prescaler A Division Factor bit 3 mask. */ -#define CLK_PSADIV3_bp 5 /* Prescaler A Division Factor bit 3 position. */ -#define CLK_PSADIV4_bm (1<<6) /* Prescaler A Division Factor bit 4 mask. */ -#define CLK_PSADIV4_bp 6 /* Prescaler A Division Factor bit 4 position. */ - -#define CLK_PSBCDIV_gm 0x03 /* Prescaler B and C Division factor group mask. */ -#define CLK_PSBCDIV_gp 0 /* Prescaler B and C Division factor group position. */ -#define CLK_PSBCDIV0_bm (1<<0) /* Prescaler B and C Division factor bit 0 mask. */ -#define CLK_PSBCDIV0_bp 0 /* Prescaler B and C Division factor bit 0 position. */ -#define CLK_PSBCDIV1_bm (1<<1) /* Prescaler B and C Division factor bit 1 mask. */ -#define CLK_PSBCDIV1_bp 1 /* Prescaler B and C Division factor bit 1 position. */ - - -/* CLK.LOCK bit masks and bit positions */ -#define CLK_LOCK_bm 0x01 /* Clock System Lock bit mask. */ -#define CLK_LOCK_bp 0 /* Clock System Lock bit position. */ - - -/* CLK.RTCCTRL bit masks and bit positions */ -#define CLK_RTCSRC_gm 0x0E /* Clock Source group mask. */ -#define CLK_RTCSRC_gp 1 /* Clock Source group position. */ -#define CLK_RTCSRC0_bm (1<<1) /* Clock Source bit 0 mask. */ -#define CLK_RTCSRC0_bp 1 /* Clock Source bit 0 position. */ -#define CLK_RTCSRC1_bm (1<<2) /* Clock Source bit 1 mask. */ -#define CLK_RTCSRC1_bp 2 /* Clock Source bit 1 position. */ -#define CLK_RTCSRC2_bm (1<<3) /* Clock Source bit 2 mask. */ -#define CLK_RTCSRC2_bp 3 /* Clock Source bit 2 position. */ - -#define CLK_RTCEN_bm 0x01 /* RTC Clock Source Enable bit mask. */ -#define CLK_RTCEN_bp 0 /* RTC Clock Source Enable bit position. */ - - -/* PR.PRGEN bit masks and bit positions */ -#define PR_AES_bm 0x10 /* AES bit mask. */ -#define PR_AES_bp 4 /* AES bit position. */ - -#define PR_EBI_bm 0x08 /* External Bus Interface bit mask. */ -#define PR_EBI_bp 3 /* External Bus Interface bit position. */ - -#define PR_RTC_bm 0x04 /* Real-time Counter bit mask. */ -#define PR_RTC_bp 2 /* Real-time Counter bit position. */ - -#define PR_EVSYS_bm 0x02 /* Event System bit mask. */ -#define PR_EVSYS_bp 1 /* Event System bit position. */ - -#define PR_DMA_bm 0x01 /* DMA-Controller bit mask. */ -#define PR_DMA_bp 0 /* DMA-Controller bit position. */ - - -/* PR.PRPA bit masks and bit positions */ -#define PR_DAC_bm 0x04 /* Port A DAC bit mask. */ -#define PR_DAC_bp 2 /* Port A DAC bit position. */ - -#define PR_ADC_bm 0x02 /* Port A ADC bit mask. */ -#define PR_ADC_bp 1 /* Port A ADC bit position. */ - -#define PR_AC_bm 0x01 /* Port A Analog Comparator bit mask. */ -#define PR_AC_bp 0 /* Port A Analog Comparator bit position. */ - - -/* PR.PRPB bit masks and bit positions */ -/* PR_DAC_bm Predefined. */ -/* PR_DAC_bp Predefined. */ - -/* PR_ADC_bm Predefined. */ -/* PR_ADC_bp Predefined. */ - -/* PR_AC_bm Predefined. */ -/* PR_AC_bp Predefined. */ - - -/* PR.PRPC bit masks and bit positions */ -#define PR_TWI_bm 0x40 /* Port C Two-wire Interface bit mask. */ -#define PR_TWI_bp 6 /* Port C Two-wire Interface bit position. */ - -#define PR_USART1_bm 0x20 /* Port C USART1 bit mask. */ -#define PR_USART1_bp 5 /* Port C USART1 bit position. */ - -#define PR_USART0_bm 0x10 /* Port C USART0 bit mask. */ -#define PR_USART0_bp 4 /* Port C USART0 bit position. */ - -#define PR_SPI_bm 0x08 /* Port C SPI bit mask. */ -#define PR_SPI_bp 3 /* Port C SPI bit position. */ - -#define PR_HIRES_bm 0x04 /* Port C AWEX bit mask. */ -#define PR_HIRES_bp 2 /* Port C AWEX bit position. */ - -#define PR_TC1_bm 0x02 /* Port C Timer/Counter1 bit mask. */ -#define PR_TC1_bp 1 /* Port C Timer/Counter1 bit position. */ - -#define PR_TC0_bm 0x01 /* Port C Timer/Counter0 bit mask. */ -#define PR_TC0_bp 0 /* Port C Timer/Counter0 bit position. */ - - -/* PR.PRPD bit masks and bit positions */ -/* PR_TWI_bm Predefined. */ -/* PR_TWI_bp Predefined. */ - -/* PR_USART1_bm Predefined. */ -/* PR_USART1_bp Predefined. */ - -/* PR_USART0_bm Predefined. */ -/* PR_USART0_bp Predefined. */ - -/* PR_SPI_bm Predefined. */ -/* PR_SPI_bp Predefined. */ - -/* PR_HIRES_bm Predefined. */ -/* PR_HIRES_bp Predefined. */ - -/* PR_TC1_bm Predefined. */ -/* PR_TC1_bp Predefined. */ - -/* PR_TC0_bm Predefined. */ -/* PR_TC0_bp Predefined. */ - - -/* PR.PRPE bit masks and bit positions */ -/* PR_TWI_bm Predefined. */ -/* PR_TWI_bp Predefined. */ - -/* PR_USART1_bm Predefined. */ -/* PR_USART1_bp Predefined. */ - -/* PR_USART0_bm Predefined. */ -/* PR_USART0_bp Predefined. */ - -/* PR_SPI_bm Predefined. */ -/* PR_SPI_bp Predefined. */ - -/* PR_HIRES_bm Predefined. */ -/* PR_HIRES_bp Predefined. */ - -/* PR_TC1_bm Predefined. */ -/* PR_TC1_bp Predefined. */ - -/* PR_TC0_bm Predefined. */ -/* PR_TC0_bp Predefined. */ - - -/* PR.PRPF bit masks and bit positions */ -/* PR_TWI_bm Predefined. */ -/* PR_TWI_bp Predefined. */ - -/* PR_USART1_bm Predefined. */ -/* PR_USART1_bp Predefined. */ - -/* PR_USART0_bm Predefined. */ -/* PR_USART0_bp Predefined. */ - -/* PR_SPI_bm Predefined. */ -/* PR_SPI_bp Predefined. */ - -/* PR_HIRES_bm Predefined. */ -/* PR_HIRES_bp Predefined. */ - -/* PR_TC1_bm Predefined. */ -/* PR_TC1_bp Predefined. */ - -/* PR_TC0_bm Predefined. */ -/* PR_TC0_bp Predefined. */ - - -/* SLEEP - Sleep Controller */ -/* SLEEP.CTRL bit masks and bit positions */ -#define SLEEP_SMODE_gm 0x0E /* Sleep Mode group mask. */ -#define SLEEP_SMODE_gp 1 /* Sleep Mode group position. */ -#define SLEEP_SMODE0_bm (1<<1) /* Sleep Mode bit 0 mask. */ -#define SLEEP_SMODE0_bp 1 /* Sleep Mode bit 0 position. */ -#define SLEEP_SMODE1_bm (1<<2) /* Sleep Mode bit 1 mask. */ -#define SLEEP_SMODE1_bp 2 /* Sleep Mode bit 1 position. */ -#define SLEEP_SMODE2_bm (1<<3) /* Sleep Mode bit 2 mask. */ -#define SLEEP_SMODE2_bp 3 /* Sleep Mode bit 2 position. */ - -#define SLEEP_SEN_bm 0x01 /* Sleep Enable bit mask. */ -#define SLEEP_SEN_bp 0 /* Sleep Enable bit position. */ - - -/* OSC - Oscillator */ -/* OSC.CTRL bit masks and bit positions */ -#define OSC_PLLEN_bm 0x10 /* PLL Enable bit mask. */ -#define OSC_PLLEN_bp 4 /* PLL Enable bit position. */ - -#define OSC_XOSCEN_bm 0x08 /* External Oscillator Enable bit mask. */ -#define OSC_XOSCEN_bp 3 /* External Oscillator Enable bit position. */ - -#define OSC_RC32KEN_bm 0x04 /* Internal 32kHz RC Oscillator Enable bit mask. */ -#define OSC_RC32KEN_bp 2 /* Internal 32kHz RC Oscillator Enable bit position. */ - -#define OSC_RC32MEN_bm 0x02 /* Internal 32MHz RC Oscillator Enable bit mask. */ -#define OSC_RC32MEN_bp 1 /* Internal 32MHz RC Oscillator Enable bit position. */ - -#define OSC_RC2MEN_bm 0x01 /* Internal 2MHz RC Oscillator Enable bit mask. */ -#define OSC_RC2MEN_bp 0 /* Internal 2MHz RC Oscillator Enable bit position. */ - - -/* OSC.STATUS bit masks and bit positions */ -#define OSC_PLLRDY_bm 0x10 /* PLL Ready bit mask. */ -#define OSC_PLLRDY_bp 4 /* PLL Ready bit position. */ - -#define OSC_XOSCRDY_bm 0x08 /* External Oscillator Ready bit mask. */ -#define OSC_XOSCRDY_bp 3 /* External Oscillator Ready bit position. */ - -#define OSC_RC32KRDY_bm 0x04 /* Internal 32kHz RC Oscillator Ready bit mask. */ -#define OSC_RC32KRDY_bp 2 /* Internal 32kHz RC Oscillator Ready bit position. */ - -#define OSC_RC32MRDY_bm 0x02 /* Internal 32MHz RC Oscillator Ready bit mask. */ -#define OSC_RC32MRDY_bp 1 /* Internal 32MHz RC Oscillator Ready bit position. */ - -#define OSC_RC2MRDY_bm 0x01 /* Internal 2MHz RC Oscillator Ready bit mask. */ -#define OSC_RC2MRDY_bp 0 /* Internal 2MHz RC Oscillator Ready bit position. */ - - -/* OSC.XOSCCTRL bit masks and bit positions */ -#define OSC_FRQRANGE_gm 0xC0 /* Frequency Range group mask. */ -#define OSC_FRQRANGE_gp 6 /* Frequency Range group position. */ -#define OSC_FRQRANGE0_bm (1<<6) /* Frequency Range bit 0 mask. */ -#define OSC_FRQRANGE0_bp 6 /* Frequency Range bit 0 position. */ -#define OSC_FRQRANGE1_bm (1<<7) /* Frequency Range bit 1 mask. */ -#define OSC_FRQRANGE1_bp 7 /* Frequency Range bit 1 position. */ - -#define OSC_X32KLPM_bm 0x20 /* 32kHz XTAL OSC Low-power Mode bit mask. */ -#define OSC_X32KLPM_bp 5 /* 32kHz XTAL OSC Low-power Mode bit position. */ - -#define OSC_XOSCSEL_gm 0x0F /* External Oscillator Selection and Startup Time group mask. */ -#define OSC_XOSCSEL_gp 0 /* External Oscillator Selection and Startup Time group position. */ -#define OSC_XOSCSEL0_bm (1<<0) /* External Oscillator Selection and Startup Time bit 0 mask. */ -#define OSC_XOSCSEL0_bp 0 /* External Oscillator Selection and Startup Time bit 0 position. */ -#define OSC_XOSCSEL1_bm (1<<1) /* External Oscillator Selection and Startup Time bit 1 mask. */ -#define OSC_XOSCSEL1_bp 1 /* External Oscillator Selection and Startup Time bit 1 position. */ -#define OSC_XOSCSEL2_bm (1<<2) /* External Oscillator Selection and Startup Time bit 2 mask. */ -#define OSC_XOSCSEL2_bp 2 /* External Oscillator Selection and Startup Time bit 2 position. */ -#define OSC_XOSCSEL3_bm (1<<3) /* External Oscillator Selection and Startup Time bit 3 mask. */ -#define OSC_XOSCSEL3_bp 3 /* External Oscillator Selection and Startup Time bit 3 position. */ - - -/* OSC.XOSCFAIL bit masks and bit positions */ -#define OSC_XOSCFDIF_bm 0x02 /* Failure Detection Interrupt Flag bit mask. */ -#define OSC_XOSCFDIF_bp 1 /* Failure Detection Interrupt Flag bit position. */ - -#define OSC_XOSCFDEN_bm 0x01 /* Failure Detection Enable bit mask. */ -#define OSC_XOSCFDEN_bp 0 /* Failure Detection Enable bit position. */ - - -/* OSC.PLLCTRL bit masks and bit positions */ -#define OSC_PLLSRC_gm 0xC0 /* Clock Source group mask. */ -#define OSC_PLLSRC_gp 6 /* Clock Source group position. */ -#define OSC_PLLSRC0_bm (1<<6) /* Clock Source bit 0 mask. */ -#define OSC_PLLSRC0_bp 6 /* Clock Source bit 0 position. */ -#define OSC_PLLSRC1_bm (1<<7) /* Clock Source bit 1 mask. */ -#define OSC_PLLSRC1_bp 7 /* Clock Source bit 1 position. */ - -#define OSC_PLLFAC_gm 0x1F /* Multiplication Factor group mask. */ -#define OSC_PLLFAC_gp 0 /* Multiplication Factor group position. */ -#define OSC_PLLFAC0_bm (1<<0) /* Multiplication Factor bit 0 mask. */ -#define OSC_PLLFAC0_bp 0 /* Multiplication Factor bit 0 position. */ -#define OSC_PLLFAC1_bm (1<<1) /* Multiplication Factor bit 1 mask. */ -#define OSC_PLLFAC1_bp 1 /* Multiplication Factor bit 1 position. */ -#define OSC_PLLFAC2_bm (1<<2) /* Multiplication Factor bit 2 mask. */ -#define OSC_PLLFAC2_bp 2 /* Multiplication Factor bit 2 position. */ -#define OSC_PLLFAC3_bm (1<<3) /* Multiplication Factor bit 3 mask. */ -#define OSC_PLLFAC3_bp 3 /* Multiplication Factor bit 3 position. */ -#define OSC_PLLFAC4_bm (1<<4) /* Multiplication Factor bit 4 mask. */ -#define OSC_PLLFAC4_bp 4 /* Multiplication Factor bit 4 position. */ - - -/* OSC.DFLLCTRL bit masks and bit positions */ -#define OSC_RC32MCREF_bm 0x02 /* 32MHz Calibration Reference bit mask. */ -#define OSC_RC32MCREF_bp 1 /* 32MHz Calibration Reference bit position. */ - -#define OSC_RC2MCREF_bm 0x01 /* 2MHz Calibration Reference bit mask. */ -#define OSC_RC2MCREF_bp 0 /* 2MHz Calibration Reference bit position. */ - - -/* DFLL - DFLL */ -/* DFLL.CTRL bit masks and bit positions */ -#define DFLL_ENABLE_bm 0x01 /* DFLL Enable bit mask. */ -#define DFLL_ENABLE_bp 0 /* DFLL Enable bit position. */ - - -/* DFLL.CALA bit masks and bit positions */ -#define DFLL_CALL_gm 0x7F /* DFLL Calibration bits [6:0] group mask. */ -#define DFLL_CALL_gp 0 /* DFLL Calibration bits [6:0] group position. */ -#define DFLL_CALL0_bm (1<<0) /* DFLL Calibration bits [6:0] bit 0 mask. */ -#define DFLL_CALL0_bp 0 /* DFLL Calibration bits [6:0] bit 0 position. */ -#define DFLL_CALL1_bm (1<<1) /* DFLL Calibration bits [6:0] bit 1 mask. */ -#define DFLL_CALL1_bp 1 /* DFLL Calibration bits [6:0] bit 1 position. */ -#define DFLL_CALL2_bm (1<<2) /* DFLL Calibration bits [6:0] bit 2 mask. */ -#define DFLL_CALL2_bp 2 /* DFLL Calibration bits [6:0] bit 2 position. */ -#define DFLL_CALL3_bm (1<<3) /* DFLL Calibration bits [6:0] bit 3 mask. */ -#define DFLL_CALL3_bp 3 /* DFLL Calibration bits [6:0] bit 3 position. */ -#define DFLL_CALL4_bm (1<<4) /* DFLL Calibration bits [6:0] bit 4 mask. */ -#define DFLL_CALL4_bp 4 /* DFLL Calibration bits [6:0] bit 4 position. */ -#define DFLL_CALL5_bm (1<<5) /* DFLL Calibration bits [6:0] bit 5 mask. */ -#define DFLL_CALL5_bp 5 /* DFLL Calibration bits [6:0] bit 5 position. */ -#define DFLL_CALL6_bm (1<<6) /* DFLL Calibration bits [6:0] bit 6 mask. */ -#define DFLL_CALL6_bp 6 /* DFLL Calibration bits [6:0] bit 6 position. */ - - -/* DFLL.CALB bit masks and bit positions */ -#define DFLL_CALH_gm 0x3F /* DFLL Calibration bits [12:7] group mask. */ -#define DFLL_CALH_gp 0 /* DFLL Calibration bits [12:7] group position. */ -#define DFLL_CALH0_bm (1<<0) /* DFLL Calibration bits [12:7] bit 0 mask. */ -#define DFLL_CALH0_bp 0 /* DFLL Calibration bits [12:7] bit 0 position. */ -#define DFLL_CALH1_bm (1<<1) /* DFLL Calibration bits [12:7] bit 1 mask. */ -#define DFLL_CALH1_bp 1 /* DFLL Calibration bits [12:7] bit 1 position. */ -#define DFLL_CALH2_bm (1<<2) /* DFLL Calibration bits [12:7] bit 2 mask. */ -#define DFLL_CALH2_bp 2 /* DFLL Calibration bits [12:7] bit 2 position. */ -#define DFLL_CALH3_bm (1<<3) /* DFLL Calibration bits [12:7] bit 3 mask. */ -#define DFLL_CALH3_bp 3 /* DFLL Calibration bits [12:7] bit 3 position. */ -#define DFLL_CALH4_bm (1<<4) /* DFLL Calibration bits [12:7] bit 4 mask. */ -#define DFLL_CALH4_bp 4 /* DFLL Calibration bits [12:7] bit 4 position. */ -#define DFLL_CALH5_bm (1<<5) /* DFLL Calibration bits [12:7] bit 5 mask. */ -#define DFLL_CALH5_bp 5 /* DFLL Calibration bits [12:7] bit 5 position. */ - - -/* RST - Reset */ -/* RST.STATUS bit masks and bit positions */ -#define RST_SDRF_bm 0x40 /* Spike Detection Reset Flag bit mask. */ -#define RST_SDRF_bp 6 /* Spike Detection Reset Flag bit position. */ - -#define RST_SRF_bm 0x20 /* Software Reset Flag bit mask. */ -#define RST_SRF_bp 5 /* Software Reset Flag bit position. */ - -#define RST_PDIRF_bm 0x10 /* Programming and Debug Interface Interface Reset Flag bit mask. */ -#define RST_PDIRF_bp 4 /* Programming and Debug Interface Interface Reset Flag bit position. */ - -#define RST_WDRF_bm 0x08 /* Watchdog Reset Flag bit mask. */ -#define RST_WDRF_bp 3 /* Watchdog Reset Flag bit position. */ - -#define RST_BORF_bm 0x04 /* Brown-out Reset Flag bit mask. */ -#define RST_BORF_bp 2 /* Brown-out Reset Flag bit position. */ - -#define RST_EXTRF_bm 0x02 /* External Reset Flag bit mask. */ -#define RST_EXTRF_bp 1 /* External Reset Flag bit position. */ - -#define RST_PORF_bm 0x01 /* Power-on Reset Flag bit mask. */ -#define RST_PORF_bp 0 /* Power-on Reset Flag bit position. */ - - -/* RST.CTRL bit masks and bit positions */ -#define RST_SWRST_bm 0x01 /* Software Reset bit mask. */ -#define RST_SWRST_bp 0 /* Software Reset bit position. */ - - -/* WDT - Watch-Dog Timer */ -/* WDT.CTRL bit masks and bit positions */ -#define WDT_PER_gm 0x3C /* Period group mask. */ -#define WDT_PER_gp 2 /* Period group position. */ -#define WDT_PER0_bm (1<<2) /* Period bit 0 mask. */ -#define WDT_PER0_bp 2 /* Period bit 0 position. */ -#define WDT_PER1_bm (1<<3) /* Period bit 1 mask. */ -#define WDT_PER1_bp 3 /* Period bit 1 position. */ -#define WDT_PER2_bm (1<<4) /* Period bit 2 mask. */ -#define WDT_PER2_bp 4 /* Period bit 2 position. */ -#define WDT_PER3_bm (1<<5) /* Period bit 3 mask. */ -#define WDT_PER3_bp 5 /* Period bit 3 position. */ - -#define WDT_ENABLE_bm 0x02 /* Enable bit mask. */ -#define WDT_ENABLE_bp 1 /* Enable bit position. */ - -#define WDT_CEN_bm 0x01 /* Change Enable bit mask. */ -#define WDT_CEN_bp 0 /* Change Enable bit position. */ - - -/* WDT.WINCTRL bit masks and bit positions */ -#define WDT_WPER_gm 0x3C /* Windowed Mode Period group mask. */ -#define WDT_WPER_gp 2 /* Windowed Mode Period group position. */ -#define WDT_WPER0_bm (1<<2) /* Windowed Mode Period bit 0 mask. */ -#define WDT_WPER0_bp 2 /* Windowed Mode Period bit 0 position. */ -#define WDT_WPER1_bm (1<<3) /* Windowed Mode Period bit 1 mask. */ -#define WDT_WPER1_bp 3 /* Windowed Mode Period bit 1 position. */ -#define WDT_WPER2_bm (1<<4) /* Windowed Mode Period bit 2 mask. */ -#define WDT_WPER2_bp 4 /* Windowed Mode Period bit 2 position. */ -#define WDT_WPER3_bm (1<<5) /* Windowed Mode Period bit 3 mask. */ -#define WDT_WPER3_bp 5 /* Windowed Mode Period bit 3 position. */ - -#define WDT_WEN_bm 0x02 /* Windowed Mode Enable bit mask. */ -#define WDT_WEN_bp 1 /* Windowed Mode Enable bit position. */ - -#define WDT_WCEN_bm 0x01 /* Windowed Mode Change Enable bit mask. */ -#define WDT_WCEN_bp 0 /* Windowed Mode Change Enable bit position. */ - - -/* WDT.STATUS bit masks and bit positions */ -#define WDT_SYNCBUSY_bm 0x01 /* Syncronization busy bit mask. */ -#define WDT_SYNCBUSY_bp 0 /* Syncronization busy bit position. */ - - -/* MCU - MCU Control */ -/* MCU.MCUCR bit masks and bit positions */ -#define MCU_JTAGD_bm 0x01 /* JTAG Disable bit mask. */ -#define MCU_JTAGD_bp 0 /* JTAG Disable bit position. */ - - -/* MCU.EVSYSLOCK bit masks and bit positions */ -#define MCU_EVSYS1LOCK_bm 0x10 /* Event Channel 4-7 Lock bit mask. */ -#define MCU_EVSYS1LOCK_bp 4 /* Event Channel 4-7 Lock bit position. */ - -#define MCU_EVSYS0LOCK_bm 0x01 /* Event Channel 0-3 Lock bit mask. */ -#define MCU_EVSYS0LOCK_bp 0 /* Event Channel 0-3 Lock bit position. */ - - -/* MCU.AWEXLOCK bit masks and bit positions */ -#define MCU_AWEXELOCK_bm 0x04 /* AWeX on T/C E0 Lock bit mask. */ -#define MCU_AWEXELOCK_bp 2 /* AWeX on T/C E0 Lock bit position. */ - -#define MCU_AWEXCLOCK_bm 0x01 /* AWeX on T/C C0 Lock bit mask. */ -#define MCU_AWEXCLOCK_bp 0 /* AWeX on T/C C0 Lock bit position. */ - - -/* PMIC - Programmable Multi-level Interrupt Controller */ -/* PMIC.STATUS bit masks and bit positions */ -#define PMIC_NMIEX_bm 0x80 /* Non-maskable Interrupt Executing bit mask. */ -#define PMIC_NMIEX_bp 7 /* Non-maskable Interrupt Executing bit position. */ - -#define PMIC_HILVLEX_bm 0x04 /* High Level Interrupt Executing bit mask. */ -#define PMIC_HILVLEX_bp 2 /* High Level Interrupt Executing bit position. */ - -#define PMIC_MEDLVLEX_bm 0x02 /* Medium Level Interrupt Executing bit mask. */ -#define PMIC_MEDLVLEX_bp 1 /* Medium Level Interrupt Executing bit position. */ - -#define PMIC_LOLVLEX_bm 0x01 /* Low Level Interrupt Executing bit mask. */ -#define PMIC_LOLVLEX_bp 0 /* Low Level Interrupt Executing bit position. */ - - -/* PMIC.CTRL bit masks and bit positions */ -#define PMIC_RREN_bm 0x80 /* Round-Robin Priority Enable bit mask. */ -#define PMIC_RREN_bp 7 /* Round-Robin Priority Enable bit position. */ - -#define PMIC_IVSEL_bm 0x40 /* Interrupt Vector Select bit mask. */ -#define PMIC_IVSEL_bp 6 /* Interrupt Vector Select bit position. */ - -#define PMIC_HILVLEN_bm 0x04 /* High Level Enable bit mask. */ -#define PMIC_HILVLEN_bp 2 /* High Level Enable bit position. */ - -#define PMIC_MEDLVLEN_bm 0x02 /* Medium Level Enable bit mask. */ -#define PMIC_MEDLVLEN_bp 1 /* Medium Level Enable bit position. */ - -#define PMIC_LOLVLEN_bm 0x01 /* Low Level Enable bit mask. */ -#define PMIC_LOLVLEN_bp 0 /* Low Level Enable bit position. */ - - -/* DMA - DMA Controller */ -/* DMA_CH.CTRLA bit masks and bit positions */ -#define DMA_CH_ENABLE_bm 0x80 /* Channel Enable bit mask. */ -#define DMA_CH_ENABLE_bp 7 /* Channel Enable bit position. */ - -#define DMA_CH_RESET_bm 0x40 /* Channel Software Reset bit mask. */ -#define DMA_CH_RESET_bp 6 /* Channel Software Reset bit position. */ - -#define DMA_CH_REPEAT_bm 0x20 /* Channel Repeat Mode bit mask. */ -#define DMA_CH_REPEAT_bp 5 /* Channel Repeat Mode bit position. */ - -#define DMA_CH_TRFREQ_bm 0x10 /* Channel Transfer Request bit mask. */ -#define DMA_CH_TRFREQ_bp 4 /* Channel Transfer Request bit position. */ - -#define DMA_CH_SINGLE_bm 0x04 /* Channel Single Shot Data Transfer bit mask. */ -#define DMA_CH_SINGLE_bp 2 /* Channel Single Shot Data Transfer bit position. */ - -#define DMA_CH_BURSTLEN_gm 0x03 /* Channel Transfer Mode group mask. */ -#define DMA_CH_BURSTLEN_gp 0 /* Channel Transfer Mode group position. */ -#define DMA_CH_BURSTLEN0_bm (1<<0) /* Channel Transfer Mode bit 0 mask. */ -#define DMA_CH_BURSTLEN0_bp 0 /* Channel Transfer Mode bit 0 position. */ -#define DMA_CH_BURSTLEN1_bm (1<<1) /* Channel Transfer Mode bit 1 mask. */ -#define DMA_CH_BURSTLEN1_bp 1 /* Channel Transfer Mode bit 1 position. */ - - -/* DMA_CH.CTRLB bit masks and bit positions */ -#define DMA_CH_CHBUSY_bm 0x80 /* Block Transfer Busy bit mask. */ -#define DMA_CH_CHBUSY_bp 7 /* Block Transfer Busy bit position. */ - -#define DMA_CH_CHPEND_bm 0x40 /* Block Transfer Pending bit mask. */ -#define DMA_CH_CHPEND_bp 6 /* Block Transfer Pending bit position. */ - -#define DMA_CH_ERRIF_bm 0x20 /* Block Transfer Error Interrupt Flag bit mask. */ -#define DMA_CH_ERRIF_bp 5 /* Block Transfer Error Interrupt Flag bit position. */ - -#define DMA_CH_TRNIF_bm 0x10 /* Transaction Complete Interrup Flag bit mask. */ -#define DMA_CH_TRNIF_bp 4 /* Transaction Complete Interrup Flag bit position. */ - -#define DMA_CH_ERRINTLVL_gm 0x0C /* Transfer Error Interrupt Level group mask. */ -#define DMA_CH_ERRINTLVL_gp 2 /* Transfer Error Interrupt Level group position. */ -#define DMA_CH_ERRINTLVL0_bm (1<<2) /* Transfer Error Interrupt Level bit 0 mask. */ -#define DMA_CH_ERRINTLVL0_bp 2 /* Transfer Error Interrupt Level bit 0 position. */ -#define DMA_CH_ERRINTLVL1_bm (1<<3) /* Transfer Error Interrupt Level bit 1 mask. */ -#define DMA_CH_ERRINTLVL1_bp 3 /* Transfer Error Interrupt Level bit 1 position. */ - -#define DMA_CH_TRNINTLVL_gm 0x03 /* Transaction Complete Interrupt Level group mask. */ -#define DMA_CH_TRNINTLVL_gp 0 /* Transaction Complete Interrupt Level group position. */ -#define DMA_CH_TRNINTLVL0_bm (1<<0) /* Transaction Complete Interrupt Level bit 0 mask. */ -#define DMA_CH_TRNINTLVL0_bp 0 /* Transaction Complete Interrupt Level bit 0 position. */ -#define DMA_CH_TRNINTLVL1_bm (1<<1) /* Transaction Complete Interrupt Level bit 1 mask. */ -#define DMA_CH_TRNINTLVL1_bp 1 /* Transaction Complete Interrupt Level bit 1 position. */ - - -/* DMA_CH.ADDRCTRL bit masks and bit positions */ -#define DMA_CH_SRCRELOAD_gm 0xC0 /* Channel Source Address Reload group mask. */ -#define DMA_CH_SRCRELOAD_gp 6 /* Channel Source Address Reload group position. */ -#define DMA_CH_SRCRELOAD0_bm (1<<6) /* Channel Source Address Reload bit 0 mask. */ -#define DMA_CH_SRCRELOAD0_bp 6 /* Channel Source Address Reload bit 0 position. */ -#define DMA_CH_SRCRELOAD1_bm (1<<7) /* Channel Source Address Reload bit 1 mask. */ -#define DMA_CH_SRCRELOAD1_bp 7 /* Channel Source Address Reload bit 1 position. */ - -#define DMA_CH_SRCDIR_gm 0x30 /* Channel Source Address Mode group mask. */ -#define DMA_CH_SRCDIR_gp 4 /* Channel Source Address Mode group position. */ -#define DMA_CH_SRCDIR0_bm (1<<4) /* Channel Source Address Mode bit 0 mask. */ -#define DMA_CH_SRCDIR0_bp 4 /* Channel Source Address Mode bit 0 position. */ -#define DMA_CH_SRCDIR1_bm (1<<5) /* Channel Source Address Mode bit 1 mask. */ -#define DMA_CH_SRCDIR1_bp 5 /* Channel Source Address Mode bit 1 position. */ - -#define DMA_CH_DESTRELOAD_gm 0x0C /* Channel Destination Address Reload group mask. */ -#define DMA_CH_DESTRELOAD_gp 2 /* Channel Destination Address Reload group position. */ -#define DMA_CH_DESTRELOAD0_bm (1<<2) /* Channel Destination Address Reload bit 0 mask. */ -#define DMA_CH_DESTRELOAD0_bp 2 /* Channel Destination Address Reload bit 0 position. */ -#define DMA_CH_DESTRELOAD1_bm (1<<3) /* Channel Destination Address Reload bit 1 mask. */ -#define DMA_CH_DESTRELOAD1_bp 3 /* Channel Destination Address Reload bit 1 position. */ - -#define DMA_CH_DESTDIR_gm 0x03 /* Channel Destination Address Mode group mask. */ -#define DMA_CH_DESTDIR_gp 0 /* Channel Destination Address Mode group position. */ -#define DMA_CH_DESTDIR0_bm (1<<0) /* Channel Destination Address Mode bit 0 mask. */ -#define DMA_CH_DESTDIR0_bp 0 /* Channel Destination Address Mode bit 0 position. */ -#define DMA_CH_DESTDIR1_bm (1<<1) /* Channel Destination Address Mode bit 1 mask. */ -#define DMA_CH_DESTDIR1_bp 1 /* Channel Destination Address Mode bit 1 position. */ - - -/* DMA_CH.TRIGSRC bit masks and bit positions */ -#define DMA_CH_TRIGSRC_gm 0xFF /* Channel Trigger Source group mask. */ -#define DMA_CH_TRIGSRC_gp 0 /* Channel Trigger Source group position. */ -#define DMA_CH_TRIGSRC0_bm (1<<0) /* Channel Trigger Source bit 0 mask. */ -#define DMA_CH_TRIGSRC0_bp 0 /* Channel Trigger Source bit 0 position. */ -#define DMA_CH_TRIGSRC1_bm (1<<1) /* Channel Trigger Source bit 1 mask. */ -#define DMA_CH_TRIGSRC1_bp 1 /* Channel Trigger Source bit 1 position. */ -#define DMA_CH_TRIGSRC2_bm (1<<2) /* Channel Trigger Source bit 2 mask. */ -#define DMA_CH_TRIGSRC2_bp 2 /* Channel Trigger Source bit 2 position. */ -#define DMA_CH_TRIGSRC3_bm (1<<3) /* Channel Trigger Source bit 3 mask. */ -#define DMA_CH_TRIGSRC3_bp 3 /* Channel Trigger Source bit 3 position. */ -#define DMA_CH_TRIGSRC4_bm (1<<4) /* Channel Trigger Source bit 4 mask. */ -#define DMA_CH_TRIGSRC4_bp 4 /* Channel Trigger Source bit 4 position. */ -#define DMA_CH_TRIGSRC5_bm (1<<5) /* Channel Trigger Source bit 5 mask. */ -#define DMA_CH_TRIGSRC5_bp 5 /* Channel Trigger Source bit 5 position. */ -#define DMA_CH_TRIGSRC6_bm (1<<6) /* Channel Trigger Source bit 6 mask. */ -#define DMA_CH_TRIGSRC6_bp 6 /* Channel Trigger Source bit 6 position. */ -#define DMA_CH_TRIGSRC7_bm (1<<7) /* Channel Trigger Source bit 7 mask. */ -#define DMA_CH_TRIGSRC7_bp 7 /* Channel Trigger Source bit 7 position. */ - - -/* DMA.CTRL bit masks and bit positions */ -#define DMA_ENABLE_bm 0x80 /* Enable bit mask. */ -#define DMA_ENABLE_bp 7 /* Enable bit position. */ - -#define DMA_RESET_bm 0x40 /* Software Reset bit mask. */ -#define DMA_RESET_bp 6 /* Software Reset bit position. */ - -#define DMA_DBUFMODE_gm 0x0C /* Double Buffering Mode group mask. */ -#define DMA_DBUFMODE_gp 2 /* Double Buffering Mode group position. */ -#define DMA_DBUFMODE0_bm (1<<2) /* Double Buffering Mode bit 0 mask. */ -#define DMA_DBUFMODE0_bp 2 /* Double Buffering Mode bit 0 position. */ -#define DMA_DBUFMODE1_bm (1<<3) /* Double Buffering Mode bit 1 mask. */ -#define DMA_DBUFMODE1_bp 3 /* Double Buffering Mode bit 1 position. */ - -#define DMA_PRIMODE_gm 0x03 /* Channel Priority Mode group mask. */ -#define DMA_PRIMODE_gp 0 /* Channel Priority Mode group position. */ -#define DMA_PRIMODE0_bm (1<<0) /* Channel Priority Mode bit 0 mask. */ -#define DMA_PRIMODE0_bp 0 /* Channel Priority Mode bit 0 position. */ -#define DMA_PRIMODE1_bm (1<<1) /* Channel Priority Mode bit 1 mask. */ -#define DMA_PRIMODE1_bp 1 /* Channel Priority Mode bit 1 position. */ - - -/* DMA.INTFLAGS bit masks and bit positions */ -#define DMA_CH3ERRIF_bm 0x80 /* Channel 3 Block Transfer Error Interrupt Flag bit mask. */ -#define DMA_CH3ERRIF_bp 7 /* Channel 3 Block Transfer Error Interrupt Flag bit position. */ - -#define DMA_CH2ERRIF_bm 0x40 /* Channel 2 Block Transfer Error Interrupt Flag bit mask. */ -#define DMA_CH2ERRIF_bp 6 /* Channel 2 Block Transfer Error Interrupt Flag bit position. */ - -#define DMA_CH1ERRIF_bm 0x20 /* Channel 1 Block Transfer Error Interrupt Flag bit mask. */ -#define DMA_CH1ERRIF_bp 5 /* Channel 1 Block Transfer Error Interrupt Flag bit position. */ - -#define DMA_CH0ERRIF_bm 0x10 /* Channel 0 Block Transfer Error Interrupt Flag bit mask. */ -#define DMA_CH0ERRIF_bp 4 /* Channel 0 Block Transfer Error Interrupt Flag bit position. */ - -#define DMA_CH3TRNIF_bm 0x08 /* Channel 3 Transaction Complete Interrupt Flag bit mask. */ -#define DMA_CH3TRNIF_bp 3 /* Channel 3 Transaction Complete Interrupt Flag bit position. */ - -#define DMA_CH2TRNIF_bm 0x04 /* Channel 2 Transaction Complete Interrupt Flag bit mask. */ -#define DMA_CH2TRNIF_bp 2 /* Channel 2 Transaction Complete Interrupt Flag bit position. */ - -#define DMA_CH1TRNIF_bm 0x02 /* Channel 1 Transaction Complete Interrupt Flag bit mask. */ -#define DMA_CH1TRNIF_bp 1 /* Channel 1 Transaction Complete Interrupt Flag bit position. */ - -#define DMA_CH0TRNIF_bm 0x01 /* Channel 0 Transaction Complete Interrupt Flag bit mask. */ -#define DMA_CH0TRNIF_bp 0 /* Channel 0 Transaction Complete Interrupt Flag bit position. */ - - -/* DMA.STATUS bit masks and bit positions */ -#define DMA_CH3BUSY_bm 0x80 /* Channel 3 Block Transfer Busy bit mask. */ -#define DMA_CH3BUSY_bp 7 /* Channel 3 Block Transfer Busy bit position. */ - -#define DMA_CH2BUSY_bm 0x40 /* Channel 2 Block Transfer Busy bit mask. */ -#define DMA_CH2BUSY_bp 6 /* Channel 2 Block Transfer Busy bit position. */ - -#define DMA_CH1BUSY_bm 0x20 /* Channel 1 Block Transfer Busy bit mask. */ -#define DMA_CH1BUSY_bp 5 /* Channel 1 Block Transfer Busy bit position. */ - -#define DMA_CH0BUSY_bm 0x10 /* Channel 0 Block Transfer Busy bit mask. */ -#define DMA_CH0BUSY_bp 4 /* Channel 0 Block Transfer Busy bit position. */ - -#define DMA_CH3PEND_bm 0x08 /* Channel 3 Block Transfer Pending bit mask. */ -#define DMA_CH3PEND_bp 3 /* Channel 3 Block Transfer Pending bit position. */ - -#define DMA_CH2PEND_bm 0x04 /* Channel 2 Block Transfer Pending bit mask. */ -#define DMA_CH2PEND_bp 2 /* Channel 2 Block Transfer Pending bit position. */ - -#define DMA_CH1PEND_bm 0x02 /* Channel 1 Block Transfer Pending bit mask. */ -#define DMA_CH1PEND_bp 1 /* Channel 1 Block Transfer Pending bit position. */ - -#define DMA_CH0PEND_bm 0x01 /* Channel 0 Block Transfer Pending bit mask. */ -#define DMA_CH0PEND_bp 0 /* Channel 0 Block Transfer Pending bit position. */ - - -/* EVSYS - Event System */ -/* EVSYS.CH0MUX bit masks and bit positions */ -#define EVSYS_CHMUX_gm 0xFF /* Event Channel 0 Multiplexer group mask. */ -#define EVSYS_CHMUX_gp 0 /* Event Channel 0 Multiplexer group position. */ -#define EVSYS_CHMUX0_bm (1<<0) /* Event Channel 0 Multiplexer bit 0 mask. */ -#define EVSYS_CHMUX0_bp 0 /* Event Channel 0 Multiplexer bit 0 position. */ -#define EVSYS_CHMUX1_bm (1<<1) /* Event Channel 0 Multiplexer bit 1 mask. */ -#define EVSYS_CHMUX1_bp 1 /* Event Channel 0 Multiplexer bit 1 position. */ -#define EVSYS_CHMUX2_bm (1<<2) /* Event Channel 0 Multiplexer bit 2 mask. */ -#define EVSYS_CHMUX2_bp 2 /* Event Channel 0 Multiplexer bit 2 position. */ -#define EVSYS_CHMUX3_bm (1<<3) /* Event Channel 0 Multiplexer bit 3 mask. */ -#define EVSYS_CHMUX3_bp 3 /* Event Channel 0 Multiplexer bit 3 position. */ -#define EVSYS_CHMUX4_bm (1<<4) /* Event Channel 0 Multiplexer bit 4 mask. */ -#define EVSYS_CHMUX4_bp 4 /* Event Channel 0 Multiplexer bit 4 position. */ -#define EVSYS_CHMUX5_bm (1<<5) /* Event Channel 0 Multiplexer bit 5 mask. */ -#define EVSYS_CHMUX5_bp 5 /* Event Channel 0 Multiplexer bit 5 position. */ -#define EVSYS_CHMUX6_bm (1<<6) /* Event Channel 0 Multiplexer bit 6 mask. */ -#define EVSYS_CHMUX6_bp 6 /* Event Channel 0 Multiplexer bit 6 position. */ -#define EVSYS_CHMUX7_bm (1<<7) /* Event Channel 0 Multiplexer bit 7 mask. */ -#define EVSYS_CHMUX7_bp 7 /* Event Channel 0 Multiplexer bit 7 position. */ - - -/* EVSYS.CH1MUX bit masks and bit positions */ -/* EVSYS_CHMUX_gm Predefined. */ -/* EVSYS_CHMUX_gp Predefined. */ -/* EVSYS_CHMUX0_bm Predefined. */ -/* EVSYS_CHMUX0_bp Predefined. */ -/* EVSYS_CHMUX1_bm Predefined. */ -/* EVSYS_CHMUX1_bp Predefined. */ -/* EVSYS_CHMUX2_bm Predefined. */ -/* EVSYS_CHMUX2_bp Predefined. */ -/* EVSYS_CHMUX3_bm Predefined. */ -/* EVSYS_CHMUX3_bp Predefined. */ -/* EVSYS_CHMUX4_bm Predefined. */ -/* EVSYS_CHMUX4_bp Predefined. */ -/* EVSYS_CHMUX5_bm Predefined. */ -/* EVSYS_CHMUX5_bp Predefined. */ -/* EVSYS_CHMUX6_bm Predefined. */ -/* EVSYS_CHMUX6_bp Predefined. */ -/* EVSYS_CHMUX7_bm Predefined. */ -/* EVSYS_CHMUX7_bp Predefined. */ - - -/* EVSYS.CH2MUX bit masks and bit positions */ -/* EVSYS_CHMUX_gm Predefined. */ -/* EVSYS_CHMUX_gp Predefined. */ -/* EVSYS_CHMUX0_bm Predefined. */ -/* EVSYS_CHMUX0_bp Predefined. */ -/* EVSYS_CHMUX1_bm Predefined. */ -/* EVSYS_CHMUX1_bp Predefined. */ -/* EVSYS_CHMUX2_bm Predefined. */ -/* EVSYS_CHMUX2_bp Predefined. */ -/* EVSYS_CHMUX3_bm Predefined. */ -/* EVSYS_CHMUX3_bp Predefined. */ -/* EVSYS_CHMUX4_bm Predefined. */ -/* EVSYS_CHMUX4_bp Predefined. */ -/* EVSYS_CHMUX5_bm Predefined. */ -/* EVSYS_CHMUX5_bp Predefined. */ -/* EVSYS_CHMUX6_bm Predefined. */ -/* EVSYS_CHMUX6_bp Predefined. */ -/* EVSYS_CHMUX7_bm Predefined. */ -/* EVSYS_CHMUX7_bp Predefined. */ - - -/* EVSYS.CH3MUX bit masks and bit positions */ -/* EVSYS_CHMUX_gm Predefined. */ -/* EVSYS_CHMUX_gp Predefined. */ -/* EVSYS_CHMUX0_bm Predefined. */ -/* EVSYS_CHMUX0_bp Predefined. */ -/* EVSYS_CHMUX1_bm Predefined. */ -/* EVSYS_CHMUX1_bp Predefined. */ -/* EVSYS_CHMUX2_bm Predefined. */ -/* EVSYS_CHMUX2_bp Predefined. */ -/* EVSYS_CHMUX3_bm Predefined. */ -/* EVSYS_CHMUX3_bp Predefined. */ -/* EVSYS_CHMUX4_bm Predefined. */ -/* EVSYS_CHMUX4_bp Predefined. */ -/* EVSYS_CHMUX5_bm Predefined. */ -/* EVSYS_CHMUX5_bp Predefined. */ -/* EVSYS_CHMUX6_bm Predefined. */ -/* EVSYS_CHMUX6_bp Predefined. */ -/* EVSYS_CHMUX7_bm Predefined. */ -/* EVSYS_CHMUX7_bp Predefined. */ - - -/* EVSYS.CH4MUX bit masks and bit positions */ -/* EVSYS_CHMUX_gm Predefined. */ -/* EVSYS_CHMUX_gp Predefined. */ -/* EVSYS_CHMUX0_bm Predefined. */ -/* EVSYS_CHMUX0_bp Predefined. */ -/* EVSYS_CHMUX1_bm Predefined. */ -/* EVSYS_CHMUX1_bp Predefined. */ -/* EVSYS_CHMUX2_bm Predefined. */ -/* EVSYS_CHMUX2_bp Predefined. */ -/* EVSYS_CHMUX3_bm Predefined. */ -/* EVSYS_CHMUX3_bp Predefined. */ -/* EVSYS_CHMUX4_bm Predefined. */ -/* EVSYS_CHMUX4_bp Predefined. */ -/* EVSYS_CHMUX5_bm Predefined. */ -/* EVSYS_CHMUX5_bp Predefined. */ -/* EVSYS_CHMUX6_bm Predefined. */ -/* EVSYS_CHMUX6_bp Predefined. */ -/* EVSYS_CHMUX7_bm Predefined. */ -/* EVSYS_CHMUX7_bp Predefined. */ - - -/* EVSYS.CH5MUX bit masks and bit positions */ -/* EVSYS_CHMUX_gm Predefined. */ -/* EVSYS_CHMUX_gp Predefined. */ -/* EVSYS_CHMUX0_bm Predefined. */ -/* EVSYS_CHMUX0_bp Predefined. */ -/* EVSYS_CHMUX1_bm Predefined. */ -/* EVSYS_CHMUX1_bp Predefined. */ -/* EVSYS_CHMUX2_bm Predefined. */ -/* EVSYS_CHMUX2_bp Predefined. */ -/* EVSYS_CHMUX3_bm Predefined. */ -/* EVSYS_CHMUX3_bp Predefined. */ -/* EVSYS_CHMUX4_bm Predefined. */ -/* EVSYS_CHMUX4_bp Predefined. */ -/* EVSYS_CHMUX5_bm Predefined. */ -/* EVSYS_CHMUX5_bp Predefined. */ -/* EVSYS_CHMUX6_bm Predefined. */ -/* EVSYS_CHMUX6_bp Predefined. */ -/* EVSYS_CHMUX7_bm Predefined. */ -/* EVSYS_CHMUX7_bp Predefined. */ - - -/* EVSYS.CH6MUX bit masks and bit positions */ -/* EVSYS_CHMUX_gm Predefined. */ -/* EVSYS_CHMUX_gp Predefined. */ -/* EVSYS_CHMUX0_bm Predefined. */ -/* EVSYS_CHMUX0_bp Predefined. */ -/* EVSYS_CHMUX1_bm Predefined. */ -/* EVSYS_CHMUX1_bp Predefined. */ -/* EVSYS_CHMUX2_bm Predefined. */ -/* EVSYS_CHMUX2_bp Predefined. */ -/* EVSYS_CHMUX3_bm Predefined. */ -/* EVSYS_CHMUX3_bp Predefined. */ -/* EVSYS_CHMUX4_bm Predefined. */ -/* EVSYS_CHMUX4_bp Predefined. */ -/* EVSYS_CHMUX5_bm Predefined. */ -/* EVSYS_CHMUX5_bp Predefined. */ -/* EVSYS_CHMUX6_bm Predefined. */ -/* EVSYS_CHMUX6_bp Predefined. */ -/* EVSYS_CHMUX7_bm Predefined. */ -/* EVSYS_CHMUX7_bp Predefined. */ - - -/* EVSYS.CH7MUX bit masks and bit positions */ -/* EVSYS_CHMUX_gm Predefined. */ -/* EVSYS_CHMUX_gp Predefined. */ -/* EVSYS_CHMUX0_bm Predefined. */ -/* EVSYS_CHMUX0_bp Predefined. */ -/* EVSYS_CHMUX1_bm Predefined. */ -/* EVSYS_CHMUX1_bp Predefined. */ -/* EVSYS_CHMUX2_bm Predefined. */ -/* EVSYS_CHMUX2_bp Predefined. */ -/* EVSYS_CHMUX3_bm Predefined. */ -/* EVSYS_CHMUX3_bp Predefined. */ -/* EVSYS_CHMUX4_bm Predefined. */ -/* EVSYS_CHMUX4_bp Predefined. */ -/* EVSYS_CHMUX5_bm Predefined. */ -/* EVSYS_CHMUX5_bp Predefined. */ -/* EVSYS_CHMUX6_bm Predefined. */ -/* EVSYS_CHMUX6_bp Predefined. */ -/* EVSYS_CHMUX7_bm Predefined. */ -/* EVSYS_CHMUX7_bp Predefined. */ - - -/* EVSYS.CH0CTRL bit masks and bit positions */ -#define EVSYS_QDIRM_gm 0x60 /* Quadrature Decoder Index Recognition Mode group mask. */ -#define EVSYS_QDIRM_gp 5 /* Quadrature Decoder Index Recognition Mode group position. */ -#define EVSYS_QDIRM0_bm (1<<5) /* Quadrature Decoder Index Recognition Mode bit 0 mask. */ -#define EVSYS_QDIRM0_bp 5 /* Quadrature Decoder Index Recognition Mode bit 0 position. */ -#define EVSYS_QDIRM1_bm (1<<6) /* Quadrature Decoder Index Recognition Mode bit 1 mask. */ -#define EVSYS_QDIRM1_bp 6 /* Quadrature Decoder Index Recognition Mode bit 1 position. */ - -#define EVSYS_QDIEN_bm 0x10 /* Quadrature Decoder Index Enable bit mask. */ -#define EVSYS_QDIEN_bp 4 /* Quadrature Decoder Index Enable bit position. */ - -#define EVSYS_QDEN_bm 0x08 /* Quadrature Decoder Enable bit mask. */ -#define EVSYS_QDEN_bp 3 /* Quadrature Decoder Enable bit position. */ - -#define EVSYS_DIGFILT_gm 0x07 /* Digital Filter group mask. */ -#define EVSYS_DIGFILT_gp 0 /* Digital Filter group position. */ -#define EVSYS_DIGFILT0_bm (1<<0) /* Digital Filter bit 0 mask. */ -#define EVSYS_DIGFILT0_bp 0 /* Digital Filter bit 0 position. */ -#define EVSYS_DIGFILT1_bm (1<<1) /* Digital Filter bit 1 mask. */ -#define EVSYS_DIGFILT1_bp 1 /* Digital Filter bit 1 position. */ -#define EVSYS_DIGFILT2_bm (1<<2) /* Digital Filter bit 2 mask. */ -#define EVSYS_DIGFILT2_bp 2 /* Digital Filter bit 2 position. */ - - -/* EVSYS.CH1CTRL bit masks and bit positions */ -/* EVSYS_DIGFILT_gm Predefined. */ -/* EVSYS_DIGFILT_gp Predefined. */ -/* EVSYS_DIGFILT0_bm Predefined. */ -/* EVSYS_DIGFILT0_bp Predefined. */ -/* EVSYS_DIGFILT1_bm Predefined. */ -/* EVSYS_DIGFILT1_bp Predefined. */ -/* EVSYS_DIGFILT2_bm Predefined. */ -/* EVSYS_DIGFILT2_bp Predefined. */ - - -/* EVSYS.CH2CTRL bit masks and bit positions */ -/* EVSYS_QDIRM_gm Predefined. */ -/* EVSYS_QDIRM_gp Predefined. */ -/* EVSYS_QDIRM0_bm Predefined. */ -/* EVSYS_QDIRM0_bp Predefined. */ -/* EVSYS_QDIRM1_bm Predefined. */ -/* EVSYS_QDIRM1_bp Predefined. */ - -/* EVSYS_QDIEN_bm Predefined. */ -/* EVSYS_QDIEN_bp Predefined. */ - -/* EVSYS_QDEN_bm Predefined. */ -/* EVSYS_QDEN_bp Predefined. */ - -/* EVSYS_DIGFILT_gm Predefined. */ -/* EVSYS_DIGFILT_gp Predefined. */ -/* EVSYS_DIGFILT0_bm Predefined. */ -/* EVSYS_DIGFILT0_bp Predefined. */ -/* EVSYS_DIGFILT1_bm Predefined. */ -/* EVSYS_DIGFILT1_bp Predefined. */ -/* EVSYS_DIGFILT2_bm Predefined. */ -/* EVSYS_DIGFILT2_bp Predefined. */ - - -/* EVSYS.CH3CTRL bit masks and bit positions */ -/* EVSYS_DIGFILT_gm Predefined. */ -/* EVSYS_DIGFILT_gp Predefined. */ -/* EVSYS_DIGFILT0_bm Predefined. */ -/* EVSYS_DIGFILT0_bp Predefined. */ -/* EVSYS_DIGFILT1_bm Predefined. */ -/* EVSYS_DIGFILT1_bp Predefined. */ -/* EVSYS_DIGFILT2_bm Predefined. */ -/* EVSYS_DIGFILT2_bp Predefined. */ - - -/* EVSYS.CH4CTRL bit masks and bit positions */ -/* EVSYS_QDIRM_gm Predefined. */ -/* EVSYS_QDIRM_gp Predefined. */ -/* EVSYS_QDIRM0_bm Predefined. */ -/* EVSYS_QDIRM0_bp Predefined. */ -/* EVSYS_QDIRM1_bm Predefined. */ -/* EVSYS_QDIRM1_bp Predefined. */ - -/* EVSYS_QDIEN_bm Predefined. */ -/* EVSYS_QDIEN_bp Predefined. */ - -/* EVSYS_QDEN_bm Predefined. */ -/* EVSYS_QDEN_bp Predefined. */ - -/* EVSYS_DIGFILT_gm Predefined. */ -/* EVSYS_DIGFILT_gp Predefined. */ -/* EVSYS_DIGFILT0_bm Predefined. */ -/* EVSYS_DIGFILT0_bp Predefined. */ -/* EVSYS_DIGFILT1_bm Predefined. */ -/* EVSYS_DIGFILT1_bp Predefined. */ -/* EVSYS_DIGFILT2_bm Predefined. */ -/* EVSYS_DIGFILT2_bp Predefined. */ - - -/* EVSYS.CH5CTRL bit masks and bit positions */ -/* EVSYS_DIGFILT_gm Predefined. */ -/* EVSYS_DIGFILT_gp Predefined. */ -/* EVSYS_DIGFILT0_bm Predefined. */ -/* EVSYS_DIGFILT0_bp Predefined. */ -/* EVSYS_DIGFILT1_bm Predefined. */ -/* EVSYS_DIGFILT1_bp Predefined. */ -/* EVSYS_DIGFILT2_bm Predefined. */ -/* EVSYS_DIGFILT2_bp Predefined. */ - - -/* EVSYS.CH6CTRL bit masks and bit positions */ -/* EVSYS_DIGFILT_gm Predefined. */ -/* EVSYS_DIGFILT_gp Predefined. */ -/* EVSYS_DIGFILT0_bm Predefined. */ -/* EVSYS_DIGFILT0_bp Predefined. */ -/* EVSYS_DIGFILT1_bm Predefined. */ -/* EVSYS_DIGFILT1_bp Predefined. */ -/* EVSYS_DIGFILT2_bm Predefined. */ -/* EVSYS_DIGFILT2_bp Predefined. */ - - -/* EVSYS.CH7CTRL bit masks and bit positions */ -/* EVSYS_DIGFILT_gm Predefined. */ -/* EVSYS_DIGFILT_gp Predefined. */ -/* EVSYS_DIGFILT0_bm Predefined. */ -/* EVSYS_DIGFILT0_bp Predefined. */ -/* EVSYS_DIGFILT1_bm Predefined. */ -/* EVSYS_DIGFILT1_bp Predefined. */ -/* EVSYS_DIGFILT2_bm Predefined. */ -/* EVSYS_DIGFILT2_bp Predefined. */ - - -/* NVM - Non Volatile Memory Controller */ -/* NVM.CMD bit masks and bit positions */ -#define NVM_CMD_gm 0xFF /* Command group mask. */ -#define NVM_CMD_gp 0 /* Command group position. */ -#define NVM_CMD0_bm (1<<0) /* Command bit 0 mask. */ -#define NVM_CMD0_bp 0 /* Command bit 0 position. */ -#define NVM_CMD1_bm (1<<1) /* Command bit 1 mask. */ -#define NVM_CMD1_bp 1 /* Command bit 1 position. */ -#define NVM_CMD2_bm (1<<2) /* Command bit 2 mask. */ -#define NVM_CMD2_bp 2 /* Command bit 2 position. */ -#define NVM_CMD3_bm (1<<3) /* Command bit 3 mask. */ -#define NVM_CMD3_bp 3 /* Command bit 3 position. */ -#define NVM_CMD4_bm (1<<4) /* Command bit 4 mask. */ -#define NVM_CMD4_bp 4 /* Command bit 4 position. */ -#define NVM_CMD5_bm (1<<5) /* Command bit 5 mask. */ -#define NVM_CMD5_bp 5 /* Command bit 5 position. */ -#define NVM_CMD6_bm (1<<6) /* Command bit 6 mask. */ -#define NVM_CMD6_bp 6 /* Command bit 6 position. */ -#define NVM_CMD7_bm (1<<7) /* Command bit 7 mask. */ -#define NVM_CMD7_bp 7 /* Command bit 7 position. */ - - -/* NVM.CTRLA bit masks and bit positions */ -#define NVM_CMDEX_bm 0x01 /* Command Execute bit mask. */ -#define NVM_CMDEX_bp 0 /* Command Execute bit position. */ - - -/* NVM.CTRLB bit masks and bit positions */ -#define NVM_EEMAPEN_bm 0x08 /* EEPROM Mapping Enable bit mask. */ -#define NVM_EEMAPEN_bp 3 /* EEPROM Mapping Enable bit position. */ - -#define NVM_FPRM_bm 0x04 /* Flash Power Reduction Enable bit mask. */ -#define NVM_FPRM_bp 2 /* Flash Power Reduction Enable bit position. */ - -#define NVM_EPRM_bm 0x02 /* EEPROM Power Reduction Enable bit mask. */ -#define NVM_EPRM_bp 1 /* EEPROM Power Reduction Enable bit position. */ - -#define NVM_SPMLOCK_bm 0x01 /* SPM Lock bit mask. */ -#define NVM_SPMLOCK_bp 0 /* SPM Lock bit position. */ - - -/* NVM.INTCTRL bit masks and bit positions */ -#define NVM_SPMLVL_gm 0x0C /* SPM Interrupt Level group mask. */ -#define NVM_SPMLVL_gp 2 /* SPM Interrupt Level group position. */ -#define NVM_SPMLVL0_bm (1<<2) /* SPM Interrupt Level bit 0 mask. */ -#define NVM_SPMLVL0_bp 2 /* SPM Interrupt Level bit 0 position. */ -#define NVM_SPMLVL1_bm (1<<3) /* SPM Interrupt Level bit 1 mask. */ -#define NVM_SPMLVL1_bp 3 /* SPM Interrupt Level bit 1 position. */ - -#define NVM_EELVL_gm 0x03 /* EEPROM Interrupt Level group mask. */ -#define NVM_EELVL_gp 0 /* EEPROM Interrupt Level group position. */ -#define NVM_EELVL0_bm (1<<0) /* EEPROM Interrupt Level bit 0 mask. */ -#define NVM_EELVL0_bp 0 /* EEPROM Interrupt Level bit 0 position. */ -#define NVM_EELVL1_bm (1<<1) /* EEPROM Interrupt Level bit 1 mask. */ -#define NVM_EELVL1_bp 1 /* EEPROM Interrupt Level bit 1 position. */ - - -/* NVM.STATUS bit masks and bit positions */ -#define NVM_NVMBUSY_bm 0x80 /* Non-volatile Memory Busy bit mask. */ -#define NVM_NVMBUSY_bp 7 /* Non-volatile Memory Busy bit position. */ - -#define NVM_FBUSY_bm 0x40 /* Flash Memory Busy bit mask. */ -#define NVM_FBUSY_bp 6 /* Flash Memory Busy bit position. */ - -#define NVM_EELOAD_bm 0x02 /* EEPROM Page Buffer Active Loading bit mask. */ -#define NVM_EELOAD_bp 1 /* EEPROM Page Buffer Active Loading bit position. */ - -#define NVM_FLOAD_bm 0x01 /* Flash Page Buffer Active Loading bit mask. */ -#define NVM_FLOAD_bp 0 /* Flash Page Buffer Active Loading bit position. */ - - -/* NVM.LOCKBITS bit masks and bit positions */ -#define NVM_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ -#define NVM_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ -#define NVM_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ -#define NVM_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ -#define NVM_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ -#define NVM_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ - -#define NVM_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ -#define NVM_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ -#define NVM_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ -#define NVM_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ -#define NVM_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ -#define NVM_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ - -#define NVM_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ -#define NVM_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ -#define NVM_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ -#define NVM_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ -#define NVM_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ -#define NVM_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ - -#define NVM_LB_gm 0x03 /* Lock Bits group mask. */ -#define NVM_LB_gp 0 /* Lock Bits group position. */ -#define NVM_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ -#define NVM_LB0_bp 0 /* Lock Bits bit 0 position. */ -#define NVM_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ -#define NVM_LB1_bp 1 /* Lock Bits bit 1 position. */ - - -/* NVM_LOCKBITS.LOCKBITS bit masks and bit positions */ -#define NVM_LOCKBITS_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ -#define NVM_LOCKBITS_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ -#define NVM_LOCKBITS_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ -#define NVM_LOCKBITS_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ -#define NVM_LOCKBITS_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ -#define NVM_LOCKBITS_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ - -#define NVM_LOCKBITS_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ -#define NVM_LOCKBITS_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ -#define NVM_LOCKBITS_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ -#define NVM_LOCKBITS_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ -#define NVM_LOCKBITS_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ -#define NVM_LOCKBITS_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ - -#define NVM_LOCKBITS_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ -#define NVM_LOCKBITS_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ -#define NVM_LOCKBITS_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ -#define NVM_LOCKBITS_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ -#define NVM_LOCKBITS_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ -#define NVM_LOCKBITS_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ - -#define NVM_LOCKBITS_LB_gm 0x03 /* Lock Bits group mask. */ -#define NVM_LOCKBITS_LB_gp 0 /* Lock Bits group position. */ -#define NVM_LOCKBITS_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ -#define NVM_LOCKBITS_LB0_bp 0 /* Lock Bits bit 0 position. */ -#define NVM_LOCKBITS_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ -#define NVM_LOCKBITS_LB1_bp 1 /* Lock Bits bit 1 position. */ - - -/* NVM_FUSES.FUSEBYTE0 bit masks and bit positions */ -#define NVM_FUSES_USERID_gm 0xFF /* User ID group mask. */ -#define NVM_FUSES_USERID_gp 0 /* User ID group position. */ -#define NVM_FUSES_USERID0_bm (1<<0) /* User ID bit 0 mask. */ -#define NVM_FUSES_USERID0_bp 0 /* User ID bit 0 position. */ -#define NVM_FUSES_USERID1_bm (1<<1) /* User ID bit 1 mask. */ -#define NVM_FUSES_USERID1_bp 1 /* User ID bit 1 position. */ -#define NVM_FUSES_USERID2_bm (1<<2) /* User ID bit 2 mask. */ -#define NVM_FUSES_USERID2_bp 2 /* User ID bit 2 position. */ -#define NVM_FUSES_USERID3_bm (1<<3) /* User ID bit 3 mask. */ -#define NVM_FUSES_USERID3_bp 3 /* User ID bit 3 position. */ -#define NVM_FUSES_USERID4_bm (1<<4) /* User ID bit 4 mask. */ -#define NVM_FUSES_USERID4_bp 4 /* User ID bit 4 position. */ -#define NVM_FUSES_USERID5_bm (1<<5) /* User ID bit 5 mask. */ -#define NVM_FUSES_USERID5_bp 5 /* User ID bit 5 position. */ -#define NVM_FUSES_USERID6_bm (1<<6) /* User ID bit 6 mask. */ -#define NVM_FUSES_USERID6_bp 6 /* User ID bit 6 position. */ -#define NVM_FUSES_USERID7_bm (1<<7) /* User ID bit 7 mask. */ -#define NVM_FUSES_USERID7_bp 7 /* User ID bit 7 position. */ - - -/* NVM_FUSES.FUSEBYTE1 bit masks and bit positions */ -#define NVM_FUSES_WDWP_gm 0xF0 /* Watchdog Window Timeout Period group mask. */ -#define NVM_FUSES_WDWP_gp 4 /* Watchdog Window Timeout Period group position. */ -#define NVM_FUSES_WDWP0_bm (1<<4) /* Watchdog Window Timeout Period bit 0 mask. */ -#define NVM_FUSES_WDWP0_bp 4 /* Watchdog Window Timeout Period bit 0 position. */ -#define NVM_FUSES_WDWP1_bm (1<<5) /* Watchdog Window Timeout Period bit 1 mask. */ -#define NVM_FUSES_WDWP1_bp 5 /* Watchdog Window Timeout Period bit 1 position. */ -#define NVM_FUSES_WDWP2_bm (1<<6) /* Watchdog Window Timeout Period bit 2 mask. */ -#define NVM_FUSES_WDWP2_bp 6 /* Watchdog Window Timeout Period bit 2 position. */ -#define NVM_FUSES_WDWP3_bm (1<<7) /* Watchdog Window Timeout Period bit 3 mask. */ -#define NVM_FUSES_WDWP3_bp 7 /* Watchdog Window Timeout Period bit 3 position. */ - -#define NVM_FUSES_WDP_gm 0x0F /* Watchdog Timeout Period group mask. */ -#define NVM_FUSES_WDP_gp 0 /* Watchdog Timeout Period group position. */ -#define NVM_FUSES_WDP0_bm (1<<0) /* Watchdog Timeout Period bit 0 mask. */ -#define NVM_FUSES_WDP0_bp 0 /* Watchdog Timeout Period bit 0 position. */ -#define NVM_FUSES_WDP1_bm (1<<1) /* Watchdog Timeout Period bit 1 mask. */ -#define NVM_FUSES_WDP1_bp 1 /* Watchdog Timeout Period bit 1 position. */ -#define NVM_FUSES_WDP2_bm (1<<2) /* Watchdog Timeout Period bit 2 mask. */ -#define NVM_FUSES_WDP2_bp 2 /* Watchdog Timeout Period bit 2 position. */ -#define NVM_FUSES_WDP3_bm (1<<3) /* Watchdog Timeout Period bit 3 mask. */ -#define NVM_FUSES_WDP3_bp 3 /* Watchdog Timeout Period bit 3 position. */ - - -/* NVM_FUSES.FUSEBYTE2 bit masks and bit positions */ -#define NVM_FUSES_DVSDON_bm 0x80 /* Spike Detector Enable bit mask. */ -#define NVM_FUSES_DVSDON_bp 7 /* Spike Detector Enable bit position. */ - -#define NVM_FUSES_BOOTRST_bm 0x40 /* Boot Loader Section Reset Vector bit mask. */ -#define NVM_FUSES_BOOTRST_bp 6 /* Boot Loader Section Reset Vector bit position. */ - -#define NVM_FUSES_BODPD_gm 0x03 /* BOD Operation in Power-Down Mode group mask. */ -#define NVM_FUSES_BODPD_gp 0 /* BOD Operation in Power-Down Mode group position. */ -#define NVM_FUSES_BODPD0_bm (1<<0) /* BOD Operation in Power-Down Mode bit 0 mask. */ -#define NVM_FUSES_BODPD0_bp 0 /* BOD Operation in Power-Down Mode bit 0 position. */ -#define NVM_FUSES_BODPD1_bm (1<<1) /* BOD Operation in Power-Down Mode bit 1 mask. */ -#define NVM_FUSES_BODPD1_bp 1 /* BOD Operation in Power-Down Mode bit 1 position. */ - - -/* NVM_FUSES.FUSEBYTE4 bit masks and bit positions */ -#define NVM_FUSES_SUT_gm 0x0C /* Start-up Time group mask. */ -#define NVM_FUSES_SUT_gp 2 /* Start-up Time group position. */ -#define NVM_FUSES_SUT0_bm (1<<2) /* Start-up Time bit 0 mask. */ -#define NVM_FUSES_SUT0_bp 2 /* Start-up Time bit 0 position. */ -#define NVM_FUSES_SUT1_bm (1<<3) /* Start-up Time bit 1 mask. */ -#define NVM_FUSES_SUT1_bp 3 /* Start-up Time bit 1 position. */ - -#define NVM_FUSES_WDLOCK_bm 0x02 /* Watchdog Timer Lock bit mask. */ -#define NVM_FUSES_WDLOCK_bp 1 /* Watchdog Timer Lock bit position. */ - - -/* NVM_FUSES.FUSEBYTE5 bit masks and bit positions */ -#define NVM_FUSES_BODACT_gm 0x30 /* BOD Operation in Active Mode group mask. */ -#define NVM_FUSES_BODACT_gp 4 /* BOD Operation in Active Mode group position. */ -#define NVM_FUSES_BODACT0_bm (1<<4) /* BOD Operation in Active Mode bit 0 mask. */ -#define NVM_FUSES_BODACT0_bp 4 /* BOD Operation in Active Mode bit 0 position. */ -#define NVM_FUSES_BODACT1_bm (1<<5) /* BOD Operation in Active Mode bit 1 mask. */ -#define NVM_FUSES_BODACT1_bp 5 /* BOD Operation in Active Mode bit 1 position. */ - -#define NVM_FUSES_EESAVE_bm 0x08 /* Preserve EEPROM Through Chip Erase bit mask. */ -#define NVM_FUSES_EESAVE_bp 3 /* Preserve EEPROM Through Chip Erase bit position. */ - -#define NVM_FUSES_BODLVL_gm 0x07 /* Brown Out Detection Voltage Level group mask. */ -#define NVM_FUSES_BODLVL_gp 0 /* Brown Out Detection Voltage Level group position. */ -#define NVM_FUSES_BODLVL0_bm (1<<0) /* Brown Out Detection Voltage Level bit 0 mask. */ -#define NVM_FUSES_BODLVL0_bp 0 /* Brown Out Detection Voltage Level bit 0 position. */ -#define NVM_FUSES_BODLVL1_bm (1<<1) /* Brown Out Detection Voltage Level bit 1 mask. */ -#define NVM_FUSES_BODLVL1_bp 1 /* Brown Out Detection Voltage Level bit 1 position. */ -#define NVM_FUSES_BODLVL2_bm (1<<2) /* Brown Out Detection Voltage Level bit 2 mask. */ -#define NVM_FUSES_BODLVL2_bp 2 /* Brown Out Detection Voltage Level bit 2 position. */ - - -/* AC - Analog Comparator */ -/* AC.AC0CTRL bit masks and bit positions */ -#define AC_INTMODE_gm 0xC0 /* Interrupt Mode group mask. */ -#define AC_INTMODE_gp 6 /* Interrupt Mode group position. */ -#define AC_INTMODE0_bm (1<<6) /* Interrupt Mode bit 0 mask. */ -#define AC_INTMODE0_bp 6 /* Interrupt Mode bit 0 position. */ -#define AC_INTMODE1_bm (1<<7) /* Interrupt Mode bit 1 mask. */ -#define AC_INTMODE1_bp 7 /* Interrupt Mode bit 1 position. */ - -#define AC_INTLVL_gm 0x30 /* Interrupt Level group mask. */ -#define AC_INTLVL_gp 4 /* Interrupt Level group position. */ -#define AC_INTLVL0_bm (1<<4) /* Interrupt Level bit 0 mask. */ -#define AC_INTLVL0_bp 4 /* Interrupt Level bit 0 position. */ -#define AC_INTLVL1_bm (1<<5) /* Interrupt Level bit 1 mask. */ -#define AC_INTLVL1_bp 5 /* Interrupt Level bit 1 position. */ - -#define AC_HSMODE_bm 0x08 /* High-speed Mode bit mask. */ -#define AC_HSMODE_bp 3 /* High-speed Mode bit position. */ - -#define AC_HYSMODE_gm 0x06 /* Hysteresis Mode group mask. */ -#define AC_HYSMODE_gp 1 /* Hysteresis Mode group position. */ -#define AC_HYSMODE0_bm (1<<1) /* Hysteresis Mode bit 0 mask. */ -#define AC_HYSMODE0_bp 1 /* Hysteresis Mode bit 0 position. */ -#define AC_HYSMODE1_bm (1<<2) /* Hysteresis Mode bit 1 mask. */ -#define AC_HYSMODE1_bp 2 /* Hysteresis Mode bit 1 position. */ - -#define AC_ENABLE_bm 0x01 /* Enable bit mask. */ -#define AC_ENABLE_bp 0 /* Enable bit position. */ - - -/* AC.AC1CTRL bit masks and bit positions */ -/* AC_INTMODE_gm Predefined. */ -/* AC_INTMODE_gp Predefined. */ -/* AC_INTMODE0_bm Predefined. */ -/* AC_INTMODE0_bp Predefined. */ -/* AC_INTMODE1_bm Predefined. */ -/* AC_INTMODE1_bp Predefined. */ - -/* AC_INTLVL_gm Predefined. */ -/* AC_INTLVL_gp Predefined. */ -/* AC_INTLVL0_bm Predefined. */ -/* AC_INTLVL0_bp Predefined. */ -/* AC_INTLVL1_bm Predefined. */ -/* AC_INTLVL1_bp Predefined. */ - -/* AC_HSMODE_bm Predefined. */ -/* AC_HSMODE_bp Predefined. */ - -/* AC_HYSMODE_gm Predefined. */ -/* AC_HYSMODE_gp Predefined. */ -/* AC_HYSMODE0_bm Predefined. */ -/* AC_HYSMODE0_bp Predefined. */ -/* AC_HYSMODE1_bm Predefined. */ -/* AC_HYSMODE1_bp Predefined. */ - -/* AC_ENABLE_bm Predefined. */ -/* AC_ENABLE_bp Predefined. */ - - -/* AC.AC0MUXCTRL bit masks and bit positions */ -#define AC_MUXPOS_gm 0x38 /* MUX Positive Input group mask. */ -#define AC_MUXPOS_gp 3 /* MUX Positive Input group position. */ -#define AC_MUXPOS0_bm (1<<3) /* MUX Positive Input bit 0 mask. */ -#define AC_MUXPOS0_bp 3 /* MUX Positive Input bit 0 position. */ -#define AC_MUXPOS1_bm (1<<4) /* MUX Positive Input bit 1 mask. */ -#define AC_MUXPOS1_bp 4 /* MUX Positive Input bit 1 position. */ -#define AC_MUXPOS2_bm (1<<5) /* MUX Positive Input bit 2 mask. */ -#define AC_MUXPOS2_bp 5 /* MUX Positive Input bit 2 position. */ - -#define AC_MUXNEG_gm 0x07 /* MUX Negative Input group mask. */ -#define AC_MUXNEG_gp 0 /* MUX Negative Input group position. */ -#define AC_MUXNEG0_bm (1<<0) /* MUX Negative Input bit 0 mask. */ -#define AC_MUXNEG0_bp 0 /* MUX Negative Input bit 0 position. */ -#define AC_MUXNEG1_bm (1<<1) /* MUX Negative Input bit 1 mask. */ -#define AC_MUXNEG1_bp 1 /* MUX Negative Input bit 1 position. */ -#define AC_MUXNEG2_bm (1<<2) /* MUX Negative Input bit 2 mask. */ -#define AC_MUXNEG2_bp 2 /* MUX Negative Input bit 2 position. */ - - -/* AC.AC1MUXCTRL bit masks and bit positions */ -/* AC_MUXPOS_gm Predefined. */ -/* AC_MUXPOS_gp Predefined. */ -/* AC_MUXPOS0_bm Predefined. */ -/* AC_MUXPOS0_bp Predefined. */ -/* AC_MUXPOS1_bm Predefined. */ -/* AC_MUXPOS1_bp Predefined. */ -/* AC_MUXPOS2_bm Predefined. */ -/* AC_MUXPOS2_bp Predefined. */ - -/* AC_MUXNEG_gm Predefined. */ -/* AC_MUXNEG_gp Predefined. */ -/* AC_MUXNEG0_bm Predefined. */ -/* AC_MUXNEG0_bp Predefined. */ -/* AC_MUXNEG1_bm Predefined. */ -/* AC_MUXNEG1_bp Predefined. */ -/* AC_MUXNEG2_bm Predefined. */ -/* AC_MUXNEG2_bp Predefined. */ - - -/* AC.CTRLA bit masks and bit positions */ -#define AC_AC0OUT_bm 0x01 /* Comparator 0 Output Enable bit mask. */ -#define AC_AC0OUT_bp 0 /* Comparator 0 Output Enable bit position. */ - - -/* AC.CTRLB bit masks and bit positions */ -#define AC_SCALEFAC_gm 0x3F /* VCC Voltage Scaler Factor group mask. */ -#define AC_SCALEFAC_gp 0 /* VCC Voltage Scaler Factor group position. */ -#define AC_SCALEFAC0_bm (1<<0) /* VCC Voltage Scaler Factor bit 0 mask. */ -#define AC_SCALEFAC0_bp 0 /* VCC Voltage Scaler Factor bit 0 position. */ -#define AC_SCALEFAC1_bm (1<<1) /* VCC Voltage Scaler Factor bit 1 mask. */ -#define AC_SCALEFAC1_bp 1 /* VCC Voltage Scaler Factor bit 1 position. */ -#define AC_SCALEFAC2_bm (1<<2) /* VCC Voltage Scaler Factor bit 2 mask. */ -#define AC_SCALEFAC2_bp 2 /* VCC Voltage Scaler Factor bit 2 position. */ -#define AC_SCALEFAC3_bm (1<<3) /* VCC Voltage Scaler Factor bit 3 mask. */ -#define AC_SCALEFAC3_bp 3 /* VCC Voltage Scaler Factor bit 3 position. */ -#define AC_SCALEFAC4_bm (1<<4) /* VCC Voltage Scaler Factor bit 4 mask. */ -#define AC_SCALEFAC4_bp 4 /* VCC Voltage Scaler Factor bit 4 position. */ -#define AC_SCALEFAC5_bm (1<<5) /* VCC Voltage Scaler Factor bit 5 mask. */ -#define AC_SCALEFAC5_bp 5 /* VCC Voltage Scaler Factor bit 5 position. */ - - -/* AC.WINCTRL bit masks and bit positions */ -#define AC_WEN_bm 0x10 /* Window Mode Enable bit mask. */ -#define AC_WEN_bp 4 /* Window Mode Enable bit position. */ - -#define AC_WINTMODE_gm 0x0C /* Window Interrupt Mode group mask. */ -#define AC_WINTMODE_gp 2 /* Window Interrupt Mode group position. */ -#define AC_WINTMODE0_bm (1<<2) /* Window Interrupt Mode bit 0 mask. */ -#define AC_WINTMODE0_bp 2 /* Window Interrupt Mode bit 0 position. */ -#define AC_WINTMODE1_bm (1<<3) /* Window Interrupt Mode bit 1 mask. */ -#define AC_WINTMODE1_bp 3 /* Window Interrupt Mode bit 1 position. */ - -#define AC_WINTLVL_gm 0x03 /* Window Interrupt Level group mask. */ -#define AC_WINTLVL_gp 0 /* Window Interrupt Level group position. */ -#define AC_WINTLVL0_bm (1<<0) /* Window Interrupt Level bit 0 mask. */ -#define AC_WINTLVL0_bp 0 /* Window Interrupt Level bit 0 position. */ -#define AC_WINTLVL1_bm (1<<1) /* Window Interrupt Level bit 1 mask. */ -#define AC_WINTLVL1_bp 1 /* Window Interrupt Level bit 1 position. */ - - -/* AC.STATUS bit masks and bit positions */ -#define AC_WSTATE_gm 0xC0 /* Window Mode State group mask. */ -#define AC_WSTATE_gp 6 /* Window Mode State group position. */ -#define AC_WSTATE0_bm (1<<6) /* Window Mode State bit 0 mask. */ -#define AC_WSTATE0_bp 6 /* Window Mode State bit 0 position. */ -#define AC_WSTATE1_bm (1<<7) /* Window Mode State bit 1 mask. */ -#define AC_WSTATE1_bp 7 /* Window Mode State bit 1 position. */ - -#define AC_AC1STATE_bm 0x20 /* Comparator 1 State bit mask. */ -#define AC_AC1STATE_bp 5 /* Comparator 1 State bit position. */ - -#define AC_AC0STATE_bm 0x10 /* Comparator 0 State bit mask. */ -#define AC_AC0STATE_bp 4 /* Comparator 0 State bit position. */ - -#define AC_WIF_bm 0x04 /* Window Mode Interrupt Flag bit mask. */ -#define AC_WIF_bp 2 /* Window Mode Interrupt Flag bit position. */ - -#define AC_AC1IF_bm 0x02 /* Comparator 1 Interrupt Flag bit mask. */ -#define AC_AC1IF_bp 1 /* Comparator 1 Interrupt Flag bit position. */ - -#define AC_AC0IF_bm 0x01 /* Comparator 0 Interrupt Flag bit mask. */ -#define AC_AC0IF_bp 0 /* Comparator 0 Interrupt Flag bit position. */ - - -/* ADC - Analog/Digital Converter */ -/* ADC_CH.CTRL bit masks and bit positions */ -#define ADC_CH_START_bm 0x80 /* Channel Start Conversion bit mask. */ -#define ADC_CH_START_bp 7 /* Channel Start Conversion bit position. */ - -#define ADC_CH_GAINFAC_gm 0x1C /* Gain Factor group mask. */ -#define ADC_CH_GAINFAC_gp 2 /* Gain Factor group position. */ -#define ADC_CH_GAINFAC0_bm (1<<2) /* Gain Factor bit 0 mask. */ -#define ADC_CH_GAINFAC0_bp 2 /* Gain Factor bit 0 position. */ -#define ADC_CH_GAINFAC1_bm (1<<3) /* Gain Factor bit 1 mask. */ -#define ADC_CH_GAINFAC1_bp 3 /* Gain Factor bit 1 position. */ -#define ADC_CH_GAINFAC2_bm (1<<4) /* Gain Factor bit 2 mask. */ -#define ADC_CH_GAINFAC2_bp 4 /* Gain Factor bit 2 position. */ - -#define ADC_CH_INPUTMODE_gm 0x03 /* Input Mode Select group mask. */ -#define ADC_CH_INPUTMODE_gp 0 /* Input Mode Select group position. */ -#define ADC_CH_INPUTMODE0_bm (1<<0) /* Input Mode Select bit 0 mask. */ -#define ADC_CH_INPUTMODE0_bp 0 /* Input Mode Select bit 0 position. */ -#define ADC_CH_INPUTMODE1_bm (1<<1) /* Input Mode Select bit 1 mask. */ -#define ADC_CH_INPUTMODE1_bp 1 /* Input Mode Select bit 1 position. */ - - -/* ADC_CH.MUXCTRL bit masks and bit positions */ -#define ADC_CH_MUXPOS_gm 0x78 /* Positive Input Select group mask. */ -#define ADC_CH_MUXPOS_gp 3 /* Positive Input Select group position. */ -#define ADC_CH_MUXPOS0_bm (1<<3) /* Positive Input Select bit 0 mask. */ -#define ADC_CH_MUXPOS0_bp 3 /* Positive Input Select bit 0 position. */ -#define ADC_CH_MUXPOS1_bm (1<<4) /* Positive Input Select bit 1 mask. */ -#define ADC_CH_MUXPOS1_bp 4 /* Positive Input Select bit 1 position. */ -#define ADC_CH_MUXPOS2_bm (1<<5) /* Positive Input Select bit 2 mask. */ -#define ADC_CH_MUXPOS2_bp 5 /* Positive Input Select bit 2 position. */ -#define ADC_CH_MUXPOS3_bm (1<<6) /* Positive Input Select bit 3 mask. */ -#define ADC_CH_MUXPOS3_bp 6 /* Positive Input Select bit 3 position. */ - -#define ADC_CH_MUXINT_gm 0x78 /* Internal Input Select group mask. */ -#define ADC_CH_MUXINT_gp 3 /* Internal Input Select group position. */ -#define ADC_CH_MUXINT0_bm (1<<3) /* Internal Input Select bit 0 mask. */ -#define ADC_CH_MUXINT0_bp 3 /* Internal Input Select bit 0 position. */ -#define ADC_CH_MUXINT1_bm (1<<4) /* Internal Input Select bit 1 mask. */ -#define ADC_CH_MUXINT1_bp 4 /* Internal Input Select bit 1 position. */ -#define ADC_CH_MUXINT2_bm (1<<5) /* Internal Input Select bit 2 mask. */ -#define ADC_CH_MUXINT2_bp 5 /* Internal Input Select bit 2 position. */ -#define ADC_CH_MUXINT3_bm (1<<6) /* Internal Input Select bit 3 mask. */ -#define ADC_CH_MUXINT3_bp 6 /* Internal Input Select bit 3 position. */ - -#define ADC_CH_MUXNEG_gm 0x03 /* Negative Input Select group mask. */ -#define ADC_CH_MUXNEG_gp 0 /* Negative Input Select group position. */ -#define ADC_CH_MUXNEG0_bm (1<<0) /* Negative Input Select bit 0 mask. */ -#define ADC_CH_MUXNEG0_bp 0 /* Negative Input Select bit 0 position. */ -#define ADC_CH_MUXNEG1_bm (1<<1) /* Negative Input Select bit 1 mask. */ -#define ADC_CH_MUXNEG1_bp 1 /* Negative Input Select bit 1 position. */ - - -/* ADC_CH.INTCTRL bit masks and bit positions */ -#define ADC_CH_INTMODE_gm 0x0C /* Interrupt Mode group mask. */ -#define ADC_CH_INTMODE_gp 2 /* Interrupt Mode group position. */ -#define ADC_CH_INTMODE0_bm (1<<2) /* Interrupt Mode bit 0 mask. */ -#define ADC_CH_INTMODE0_bp 2 /* Interrupt Mode bit 0 position. */ -#define ADC_CH_INTMODE1_bm (1<<3) /* Interrupt Mode bit 1 mask. */ -#define ADC_CH_INTMODE1_bp 3 /* Interrupt Mode bit 1 position. */ - -#define ADC_CH_INTLVL_gm 0x03 /* Interrupt Level group mask. */ -#define ADC_CH_INTLVL_gp 0 /* Interrupt Level group position. */ -#define ADC_CH_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */ -#define ADC_CH_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */ -#define ADC_CH_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ -#define ADC_CH_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */ - - -/* ADC_CH.INTFLAGS bit masks and bit positions */ -#define ADC_CH_CHIF_bm 0x01 /* Channel Interrupt Flag bit mask. */ -#define ADC_CH_CHIF_bp 0 /* Channel Interrupt Flag bit position. */ - - -/* ADC.CTRLA bit masks and bit positions */ -#define ADC_DMASEL_gm 0xC0 /* DMA Selection group mask. */ -#define ADC_DMASEL_gp 6 /* DMA Selection group position. */ -#define ADC_DMASEL0_bm (1<<6) /* DMA Selection bit 0 mask. */ -#define ADC_DMASEL0_bp 6 /* DMA Selection bit 0 position. */ -#define ADC_DMASEL1_bm (1<<7) /* DMA Selection bit 1 mask. */ -#define ADC_DMASEL1_bp 7 /* DMA Selection bit 1 position. */ - -#define ADC_CH3START_bm 0x20 /* Channel 3 Start Conversion bit mask. */ -#define ADC_CH3START_bp 5 /* Channel 3 Start Conversion bit position. */ - -#define ADC_CH2START_bm 0x10 /* Channel 2 Start Conversion bit mask. */ -#define ADC_CH2START_bp 4 /* Channel 2 Start Conversion bit position. */ - -#define ADC_CH1START_bm 0x08 /* Channel 1 Start Conversion bit mask. */ -#define ADC_CH1START_bp 3 /* Channel 1 Start Conversion bit position. */ - -#define ADC_CH0START_bm 0x04 /* Channel 0 Start Conversion bit mask. */ -#define ADC_CH0START_bp 2 /* Channel 0 Start Conversion bit position. */ - -#define ADC_FLUSH_bm 0x02 /* Flush Pipeline bit mask. */ -#define ADC_FLUSH_bp 1 /* Flush Pipeline bit position. */ - -#define ADC_ENABLE_bm 0x01 /* Enable ADC bit mask. */ -#define ADC_ENABLE_bp 0 /* Enable ADC bit position. */ - - -/* ADC.CTRLB bit masks and bit positions */ -#define ADC_CONMODE_bm 0x10 /* Conversion Mode bit mask. */ -#define ADC_CONMODE_bp 4 /* Conversion Mode bit position. */ - -#define ADC_FREERUN_bm 0x08 /* Free Running Mode Enable bit mask. */ -#define ADC_FREERUN_bp 3 /* Free Running Mode Enable bit position. */ - -#define ADC_RESOLUTION_gm 0x06 /* Result Resolution group mask. */ -#define ADC_RESOLUTION_gp 1 /* Result Resolution group position. */ -#define ADC_RESOLUTION0_bm (1<<1) /* Result Resolution bit 0 mask. */ -#define ADC_RESOLUTION0_bp 1 /* Result Resolution bit 0 position. */ -#define ADC_RESOLUTION1_bm (1<<2) /* Result Resolution bit 1 mask. */ -#define ADC_RESOLUTION1_bp 2 /* Result Resolution bit 1 position. */ - - -/* ADC.REFCTRL bit masks and bit positions */ -#define ADC_REFSEL_gm 0x30 /* Reference Selection group mask. */ -#define ADC_REFSEL_gp 4 /* Reference Selection group position. */ -#define ADC_REFSEL0_bm (1<<4) /* Reference Selection bit 0 mask. */ -#define ADC_REFSEL0_bp 4 /* Reference Selection bit 0 position. */ -#define ADC_REFSEL1_bm (1<<5) /* Reference Selection bit 1 mask. */ -#define ADC_REFSEL1_bp 5 /* Reference Selection bit 1 position. */ - -#define ADC_BANDGAP_bm 0x02 /* Bandgap enable bit mask. */ -#define ADC_BANDGAP_bp 1 /* Bandgap enable bit position. */ - -#define ADC_TEMPREF_bm 0x01 /* Temperature Reference Enable bit mask. */ -#define ADC_TEMPREF_bp 0 /* Temperature Reference Enable bit position. */ - - -/* ADC.EVCTRL bit masks and bit positions */ -#define ADC_SWEEP_gm 0xC0 /* Channel Sweep Selection group mask. */ -#define ADC_SWEEP_gp 6 /* Channel Sweep Selection group position. */ -#define ADC_SWEEP0_bm (1<<6) /* Channel Sweep Selection bit 0 mask. */ -#define ADC_SWEEP0_bp 6 /* Channel Sweep Selection bit 0 position. */ -#define ADC_SWEEP1_bm (1<<7) /* Channel Sweep Selection bit 1 mask. */ -#define ADC_SWEEP1_bp 7 /* Channel Sweep Selection bit 1 position. */ - -#define ADC_EVSEL_gm 0x38 /* Event Input Select group mask. */ -#define ADC_EVSEL_gp 3 /* Event Input Select group position. */ -#define ADC_EVSEL0_bm (1<<3) /* Event Input Select bit 0 mask. */ -#define ADC_EVSEL0_bp 3 /* Event Input Select bit 0 position. */ -#define ADC_EVSEL1_bm (1<<4) /* Event Input Select bit 1 mask. */ -#define ADC_EVSEL1_bp 4 /* Event Input Select bit 1 position. */ -#define ADC_EVSEL2_bm (1<<5) /* Event Input Select bit 2 mask. */ -#define ADC_EVSEL2_bp 5 /* Event Input Select bit 2 position. */ - -#define ADC_EVACT_gm 0x07 /* Event Action Select group mask. */ -#define ADC_EVACT_gp 0 /* Event Action Select group position. */ -#define ADC_EVACT0_bm (1<<0) /* Event Action Select bit 0 mask. */ -#define ADC_EVACT0_bp 0 /* Event Action Select bit 0 position. */ -#define ADC_EVACT1_bm (1<<1) /* Event Action Select bit 1 mask. */ -#define ADC_EVACT1_bp 1 /* Event Action Select bit 1 position. */ -#define ADC_EVACT2_bm (1<<2) /* Event Action Select bit 2 mask. */ -#define ADC_EVACT2_bp 2 /* Event Action Select bit 2 position. */ - - -/* ADC.PRESCALER bit masks and bit positions */ -#define ADC_PRESCALER_gm 0x07 /* Clock Prescaler Selection group mask. */ -#define ADC_PRESCALER_gp 0 /* Clock Prescaler Selection group position. */ -#define ADC_PRESCALER0_bm (1<<0) /* Clock Prescaler Selection bit 0 mask. */ -#define ADC_PRESCALER0_bp 0 /* Clock Prescaler Selection bit 0 position. */ -#define ADC_PRESCALER1_bm (1<<1) /* Clock Prescaler Selection bit 1 mask. */ -#define ADC_PRESCALER1_bp 1 /* Clock Prescaler Selection bit 1 position. */ -#define ADC_PRESCALER2_bm (1<<2) /* Clock Prescaler Selection bit 2 mask. */ -#define ADC_PRESCALER2_bp 2 /* Clock Prescaler Selection bit 2 position. */ - - -/* ADC.INTFLAGS bit masks and bit positions */ -#define ADC_CH3IF_bm 0x08 /* Channel 3 Interrupt Flag bit mask. */ -#define ADC_CH3IF_bp 3 /* Channel 3 Interrupt Flag bit position. */ - -#define ADC_CH2IF_bm 0x04 /* Channel 2 Interrupt Flag bit mask. */ -#define ADC_CH2IF_bp 2 /* Channel 2 Interrupt Flag bit position. */ - -#define ADC_CH1IF_bm 0x02 /* Channel 1 Interrupt Flag bit mask. */ -#define ADC_CH1IF_bp 1 /* Channel 1 Interrupt Flag bit position. */ - -#define ADC_CH0IF_bm 0x01 /* Channel 0 Interrupt Flag bit mask. */ -#define ADC_CH0IF_bp 0 /* Channel 0 Interrupt Flag bit position. */ - - -/* DAC - Digital/Analog Converter */ -/* DAC.CTRLA bit masks and bit positions */ -#define DAC_IDOEN_bm 0x10 /* Internal Output Enable bit mask. */ -#define DAC_IDOEN_bp 4 /* Internal Output Enable bit position. */ - -#define DAC_CH1EN_bm 0x08 /* Channel 1 Output Enable bit mask. */ -#define DAC_CH1EN_bp 3 /* Channel 1 Output Enable bit position. */ - -#define DAC_CH0EN_bm 0x04 /* Channel 0 Output Enable bit mask. */ -#define DAC_CH0EN_bp 2 /* Channel 0 Output Enable bit position. */ - -#define DAC_LPMODE_bm 0x02 /* Low Power Mode bit mask. */ -#define DAC_LPMODE_bp 1 /* Low Power Mode bit position. */ - -#define DAC_ENABLE_bm 0x01 /* Enable bit mask. */ -#define DAC_ENABLE_bp 0 /* Enable bit position. */ - - -/* DAC.CTRLB bit masks and bit positions */ -#define DAC_CHSEL_gm 0x60 /* Channel Select group mask. */ -#define DAC_CHSEL_gp 5 /* Channel Select group position. */ -#define DAC_CHSEL0_bm (1<<5) /* Channel Select bit 0 mask. */ -#define DAC_CHSEL0_bp 5 /* Channel Select bit 0 position. */ -#define DAC_CHSEL1_bm (1<<6) /* Channel Select bit 1 mask. */ -#define DAC_CHSEL1_bp 6 /* Channel Select bit 1 position. */ - -#define DAC_CH1TRIG_bm 0x02 /* Channel 1 Event Trig Enable bit mask. */ -#define DAC_CH1TRIG_bp 1 /* Channel 1 Event Trig Enable bit position. */ - -#define DAC_CH0TRIG_bm 0x01 /* Channel 0 Event Trig Enable bit mask. */ -#define DAC_CH0TRIG_bp 0 /* Channel 0 Event Trig Enable bit position. */ - - -/* DAC.CTRLC bit masks and bit positions */ -#define DAC_REFSEL_gm 0x18 /* Reference Select group mask. */ -#define DAC_REFSEL_gp 3 /* Reference Select group position. */ -#define DAC_REFSEL0_bm (1<<3) /* Reference Select bit 0 mask. */ -#define DAC_REFSEL0_bp 3 /* Reference Select bit 0 position. */ -#define DAC_REFSEL1_bm (1<<4) /* Reference Select bit 1 mask. */ -#define DAC_REFSEL1_bp 4 /* Reference Select bit 1 position. */ - -#define DAC_LEFTADJ_bm 0x01 /* Left-adjust Result bit mask. */ -#define DAC_LEFTADJ_bp 0 /* Left-adjust Result bit position. */ - - -/* DAC.EVCTRL bit masks and bit positions */ -#define DAC_EVSEL_gm 0x07 /* Event Input Selection group mask. */ -#define DAC_EVSEL_gp 0 /* Event Input Selection group position. */ -#define DAC_EVSEL0_bm (1<<0) /* Event Input Selection bit 0 mask. */ -#define DAC_EVSEL0_bp 0 /* Event Input Selection bit 0 position. */ -#define DAC_EVSEL1_bm (1<<1) /* Event Input Selection bit 1 mask. */ -#define DAC_EVSEL1_bp 1 /* Event Input Selection bit 1 position. */ -#define DAC_EVSEL2_bm (1<<2) /* Event Input Selection bit 2 mask. */ -#define DAC_EVSEL2_bp 2 /* Event Input Selection bit 2 position. */ - - -/* DAC.TIMCTRL bit masks and bit positions */ -#define DAC_CONINTVAL_gm 0x70 /* Conversion Intercal group mask. */ -#define DAC_CONINTVAL_gp 4 /* Conversion Intercal group position. */ -#define DAC_CONINTVAL0_bm (1<<4) /* Conversion Intercal bit 0 mask. */ -#define DAC_CONINTVAL0_bp 4 /* Conversion Intercal bit 0 position. */ -#define DAC_CONINTVAL1_bm (1<<5) /* Conversion Intercal bit 1 mask. */ -#define DAC_CONINTVAL1_bp 5 /* Conversion Intercal bit 1 position. */ -#define DAC_CONINTVAL2_bm (1<<6) /* Conversion Intercal bit 2 mask. */ -#define DAC_CONINTVAL2_bp 6 /* Conversion Intercal bit 2 position. */ - -#define DAC_REFRESH_gm 0x0F /* Refresh Timing Control group mask. */ -#define DAC_REFRESH_gp 0 /* Refresh Timing Control group position. */ -#define DAC_REFRESH0_bm (1<<0) /* Refresh Timing Control bit 0 mask. */ -#define DAC_REFRESH0_bp 0 /* Refresh Timing Control bit 0 position. */ -#define DAC_REFRESH1_bm (1<<1) /* Refresh Timing Control bit 1 mask. */ -#define DAC_REFRESH1_bp 1 /* Refresh Timing Control bit 1 position. */ -#define DAC_REFRESH2_bm (1<<2) /* Refresh Timing Control bit 2 mask. */ -#define DAC_REFRESH2_bp 2 /* Refresh Timing Control bit 2 position. */ -#define DAC_REFRESH3_bm (1<<3) /* Refresh Timing Control bit 3 mask. */ -#define DAC_REFRESH3_bp 3 /* Refresh Timing Control bit 3 position. */ - - -/* DAC.STATUS bit masks and bit positions */ -#define DAC_CH1DRE_bm 0x02 /* Channel 1 Data Register Empty bit mask. */ -#define DAC_CH1DRE_bp 1 /* Channel 1 Data Register Empty bit position. */ - -#define DAC_CH0DRE_bm 0x01 /* Channel 0 Data Register Empty bit mask. */ -#define DAC_CH0DRE_bp 0 /* Channel 0 Data Register Empty bit position. */ - - -/* RTC - Real-Time Clounter */ -/* RTC.CTRL bit masks and bit positions */ -#define RTC_PRESCALER_gm 0x07 /* Prescaling Factor group mask. */ -#define RTC_PRESCALER_gp 0 /* Prescaling Factor group position. */ -#define RTC_PRESCALER0_bm (1<<0) /* Prescaling Factor bit 0 mask. */ -#define RTC_PRESCALER0_bp 0 /* Prescaling Factor bit 0 position. */ -#define RTC_PRESCALER1_bm (1<<1) /* Prescaling Factor bit 1 mask. */ -#define RTC_PRESCALER1_bp 1 /* Prescaling Factor bit 1 position. */ -#define RTC_PRESCALER2_bm (1<<2) /* Prescaling Factor bit 2 mask. */ -#define RTC_PRESCALER2_bp 2 /* Prescaling Factor bit 2 position. */ - - -/* RTC.STATUS bit masks and bit positions */ -#define RTC_SYNCBUSY_bm 0x01 /* Synchronization Busy Flag bit mask. */ -#define RTC_SYNCBUSY_bp 0 /* Synchronization Busy Flag bit position. */ - - -/* RTC.INTCTRL bit masks and bit positions */ -#define RTC_COMPINTLVL_gm 0x0C /* Compare Match Interrupt Level group mask. */ -#define RTC_COMPINTLVL_gp 2 /* Compare Match Interrupt Level group position. */ -#define RTC_COMPINTLVL0_bm (1<<2) /* Compare Match Interrupt Level bit 0 mask. */ -#define RTC_COMPINTLVL0_bp 2 /* Compare Match Interrupt Level bit 0 position. */ -#define RTC_COMPINTLVL1_bm (1<<3) /* Compare Match Interrupt Level bit 1 mask. */ -#define RTC_COMPINTLVL1_bp 3 /* Compare Match Interrupt Level bit 1 position. */ - -#define RTC_OVFINTLVL_gm 0x03 /* Overflow Interrupt Level group mask. */ -#define RTC_OVFINTLVL_gp 0 /* Overflow Interrupt Level group position. */ -#define RTC_OVFINTLVL0_bm (1<<0) /* Overflow Interrupt Level bit 0 mask. */ -#define RTC_OVFINTLVL0_bp 0 /* Overflow Interrupt Level bit 0 position. */ -#define RTC_OVFINTLVL1_bm (1<<1) /* Overflow Interrupt Level bit 1 mask. */ -#define RTC_OVFINTLVL1_bp 1 /* Overflow Interrupt Level bit 1 position. */ - - -/* RTC.INTFLAGS bit masks and bit positions */ -#define RTC_COMPIF_bm 0x02 /* Compare Match Interrupt Flag bit mask. */ -#define RTC_COMPIF_bp 1 /* Compare Match Interrupt Flag bit position. */ - -#define RTC_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ -#define RTC_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ - - -/* EBI - External Bus Interface */ -/* EBI_CS.CTRLA bit masks and bit positions */ -#define EBI_CS_ASIZE_gm 0x7C /* Address Size group mask. */ -#define EBI_CS_ASIZE_gp 2 /* Address Size group position. */ -#define EBI_CS_ASIZE0_bm (1<<2) /* Address Size bit 0 mask. */ -#define EBI_CS_ASIZE0_bp 2 /* Address Size bit 0 position. */ -#define EBI_CS_ASIZE1_bm (1<<3) /* Address Size bit 1 mask. */ -#define EBI_CS_ASIZE1_bp 3 /* Address Size bit 1 position. */ -#define EBI_CS_ASIZE2_bm (1<<4) /* Address Size bit 2 mask. */ -#define EBI_CS_ASIZE2_bp 4 /* Address Size bit 2 position. */ -#define EBI_CS_ASIZE3_bm (1<<5) /* Address Size bit 3 mask. */ -#define EBI_CS_ASIZE3_bp 5 /* Address Size bit 3 position. */ -#define EBI_CS_ASIZE4_bm (1<<6) /* Address Size bit 4 mask. */ -#define EBI_CS_ASIZE4_bp 6 /* Address Size bit 4 position. */ - -#define EBI_CS_MODE_gm 0x03 /* Memory Mode group mask. */ -#define EBI_CS_MODE_gp 0 /* Memory Mode group position. */ -#define EBI_CS_MODE0_bm (1<<0) /* Memory Mode bit 0 mask. */ -#define EBI_CS_MODE0_bp 0 /* Memory Mode bit 0 position. */ -#define EBI_CS_MODE1_bm (1<<1) /* Memory Mode bit 1 mask. */ -#define EBI_CS_MODE1_bp 1 /* Memory Mode bit 1 position. */ - - -/* EBI_CS.CTRLB bit masks and bit positions */ -#define EBI_CS_SRWS_gm 0x07 /* SRAM Wait State Cycles group mask. */ -#define EBI_CS_SRWS_gp 0 /* SRAM Wait State Cycles group position. */ -#define EBI_CS_SRWS0_bm (1<<0) /* SRAM Wait State Cycles bit 0 mask. */ -#define EBI_CS_SRWS0_bp 0 /* SRAM Wait State Cycles bit 0 position. */ -#define EBI_CS_SRWS1_bm (1<<1) /* SRAM Wait State Cycles bit 1 mask. */ -#define EBI_CS_SRWS1_bp 1 /* SRAM Wait State Cycles bit 1 position. */ -#define EBI_CS_SRWS2_bm (1<<2) /* SRAM Wait State Cycles bit 2 mask. */ -#define EBI_CS_SRWS2_bp 2 /* SRAM Wait State Cycles bit 2 position. */ - -#define EBI_CS_SDINITDONE_bm 0x80 /* SDRAM Initialization Done bit mask. */ -#define EBI_CS_SDINITDONE_bp 7 /* SDRAM Initialization Done bit position. */ - -#define EBI_CS_SDSREN_bm 0x04 /* SDRAM Self-refresh Enable bit mask. */ -#define EBI_CS_SDSREN_bp 2 /* SDRAM Self-refresh Enable bit position. */ - -#define EBI_CS_SDMODE_gm 0x03 /* SDRAM Mode group mask. */ -#define EBI_CS_SDMODE_gp 0 /* SDRAM Mode group position. */ -#define EBI_CS_SDMODE0_bm (1<<0) /* SDRAM Mode bit 0 mask. */ -#define EBI_CS_SDMODE0_bp 0 /* SDRAM Mode bit 0 position. */ -#define EBI_CS_SDMODE1_bm (1<<1) /* SDRAM Mode bit 1 mask. */ -#define EBI_CS_SDMODE1_bp 1 /* SDRAM Mode bit 1 position. */ - - -/* EBI.CTRL bit masks and bit positions */ -#define EBI_SDDATAW_gm 0xC0 /* SDRAM Data Width Setting group mask. */ -#define EBI_SDDATAW_gp 6 /* SDRAM Data Width Setting group position. */ -#define EBI_SDDATAW0_bm (1<<6) /* SDRAM Data Width Setting bit 0 mask. */ -#define EBI_SDDATAW0_bp 6 /* SDRAM Data Width Setting bit 0 position. */ -#define EBI_SDDATAW1_bm (1<<7) /* SDRAM Data Width Setting bit 1 mask. */ -#define EBI_SDDATAW1_bp 7 /* SDRAM Data Width Setting bit 1 position. */ - -#define EBI_LPCMODE_gm 0x30 /* SRAM LPC Mode group mask. */ -#define EBI_LPCMODE_gp 4 /* SRAM LPC Mode group position. */ -#define EBI_LPCMODE0_bm (1<<4) /* SRAM LPC Mode bit 0 mask. */ -#define EBI_LPCMODE0_bp 4 /* SRAM LPC Mode bit 0 position. */ -#define EBI_LPCMODE1_bm (1<<5) /* SRAM LPC Mode bit 1 mask. */ -#define EBI_LPCMODE1_bp 5 /* SRAM LPC Mode bit 1 position. */ - -#define EBI_SRMODE_gm 0x0C /* SRAM Mode group mask. */ -#define EBI_SRMODE_gp 2 /* SRAM Mode group position. */ -#define EBI_SRMODE0_bm (1<<2) /* SRAM Mode bit 0 mask. */ -#define EBI_SRMODE0_bp 2 /* SRAM Mode bit 0 position. */ -#define EBI_SRMODE1_bm (1<<3) /* SRAM Mode bit 1 mask. */ -#define EBI_SRMODE1_bp 3 /* SRAM Mode bit 1 position. */ - -#define EBI_IFMODE_gm 0x03 /* Interface Mode group mask. */ -#define EBI_IFMODE_gp 0 /* Interface Mode group position. */ -#define EBI_IFMODE0_bm (1<<0) /* Interface Mode bit 0 mask. */ -#define EBI_IFMODE0_bp 0 /* Interface Mode bit 0 position. */ -#define EBI_IFMODE1_bm (1<<1) /* Interface Mode bit 1 mask. */ -#define EBI_IFMODE1_bp 1 /* Interface Mode bit 1 position. */ - - -/* EBI.SDRAMCTRLA bit masks and bit positions */ -#define EBI_SDCAS_bm 0x08 /* SDRAM CAS Latency Setting bit mask. */ -#define EBI_SDCAS_bp 3 /* SDRAM CAS Latency Setting bit position. */ - -#define EBI_SDROW_bm 0x04 /* SDRAM ROW Bits Setting bit mask. */ -#define EBI_SDROW_bp 2 /* SDRAM ROW Bits Setting bit position. */ - -#define EBI_SDCOL_gm 0x03 /* SDRAM Column Bits Setting group mask. */ -#define EBI_SDCOL_gp 0 /* SDRAM Column Bits Setting group position. */ -#define EBI_SDCOL0_bm (1<<0) /* SDRAM Column Bits Setting bit 0 mask. */ -#define EBI_SDCOL0_bp 0 /* SDRAM Column Bits Setting bit 0 position. */ -#define EBI_SDCOL1_bm (1<<1) /* SDRAM Column Bits Setting bit 1 mask. */ -#define EBI_SDCOL1_bp 1 /* SDRAM Column Bits Setting bit 1 position. */ - - -/* EBI.SDRAMCTRLB bit masks and bit positions */ -#define EBI_MRDLY_gm 0xC0 /* SDRAM Mode Register Delay group mask. */ -#define EBI_MRDLY_gp 6 /* SDRAM Mode Register Delay group position. */ -#define EBI_MRDLY0_bm (1<<6) /* SDRAM Mode Register Delay bit 0 mask. */ -#define EBI_MRDLY0_bp 6 /* SDRAM Mode Register Delay bit 0 position. */ -#define EBI_MRDLY1_bm (1<<7) /* SDRAM Mode Register Delay bit 1 mask. */ -#define EBI_MRDLY1_bp 7 /* SDRAM Mode Register Delay bit 1 position. */ - -#define EBI_ROWCYCDLY_gm 0x38 /* SDRAM Row Cycle Delay group mask. */ -#define EBI_ROWCYCDLY_gp 3 /* SDRAM Row Cycle Delay group position. */ -#define EBI_ROWCYCDLY0_bm (1<<3) /* SDRAM Row Cycle Delay bit 0 mask. */ -#define EBI_ROWCYCDLY0_bp 3 /* SDRAM Row Cycle Delay bit 0 position. */ -#define EBI_ROWCYCDLY1_bm (1<<4) /* SDRAM Row Cycle Delay bit 1 mask. */ -#define EBI_ROWCYCDLY1_bp 4 /* SDRAM Row Cycle Delay bit 1 position. */ -#define EBI_ROWCYCDLY2_bm (1<<5) /* SDRAM Row Cycle Delay bit 2 mask. */ -#define EBI_ROWCYCDLY2_bp 5 /* SDRAM Row Cycle Delay bit 2 position. */ - -#define EBI_RPDLY_gm 0x07 /* SDRAM Row-to-Precharge Delay group mask. */ -#define EBI_RPDLY_gp 0 /* SDRAM Row-to-Precharge Delay group position. */ -#define EBI_RPDLY0_bm (1<<0) /* SDRAM Row-to-Precharge Delay bit 0 mask. */ -#define EBI_RPDLY0_bp 0 /* SDRAM Row-to-Precharge Delay bit 0 position. */ -#define EBI_RPDLY1_bm (1<<1) /* SDRAM Row-to-Precharge Delay bit 1 mask. */ -#define EBI_RPDLY1_bp 1 /* SDRAM Row-to-Precharge Delay bit 1 position. */ -#define EBI_RPDLY2_bm (1<<2) /* SDRAM Row-to-Precharge Delay bit 2 mask. */ -#define EBI_RPDLY2_bp 2 /* SDRAM Row-to-Precharge Delay bit 2 position. */ - - -/* EBI.SDRAMCTRLC bit masks and bit positions */ -#define EBI_WRDLY_gm 0xC0 /* SDRAM Write Recovery Delay group mask. */ -#define EBI_WRDLY_gp 6 /* SDRAM Write Recovery Delay group position. */ -#define EBI_WRDLY0_bm (1<<6) /* SDRAM Write Recovery Delay bit 0 mask. */ -#define EBI_WRDLY0_bp 6 /* SDRAM Write Recovery Delay bit 0 position. */ -#define EBI_WRDLY1_bm (1<<7) /* SDRAM Write Recovery Delay bit 1 mask. */ -#define EBI_WRDLY1_bp 7 /* SDRAM Write Recovery Delay bit 1 position. */ - -#define EBI_ESRDLY_gm 0x38 /* SDRAM Exit-Self-refresh-to-Active Delay group mask. */ -#define EBI_ESRDLY_gp 3 /* SDRAM Exit-Self-refresh-to-Active Delay group position. */ -#define EBI_ESRDLY0_bm (1<<3) /* SDRAM Exit-Self-refresh-to-Active Delay bit 0 mask. */ -#define EBI_ESRDLY0_bp 3 /* SDRAM Exit-Self-refresh-to-Active Delay bit 0 position. */ -#define EBI_ESRDLY1_bm (1<<4) /* SDRAM Exit-Self-refresh-to-Active Delay bit 1 mask. */ -#define EBI_ESRDLY1_bp 4 /* SDRAM Exit-Self-refresh-to-Active Delay bit 1 position. */ -#define EBI_ESRDLY2_bm (1<<5) /* SDRAM Exit-Self-refresh-to-Active Delay bit 2 mask. */ -#define EBI_ESRDLY2_bp 5 /* SDRAM Exit-Self-refresh-to-Active Delay bit 2 position. */ - -#define EBI_ROWCOLDLY_gm 0x07 /* SDRAM Row-to-Column Delay group mask. */ -#define EBI_ROWCOLDLY_gp 0 /* SDRAM Row-to-Column Delay group position. */ -#define EBI_ROWCOLDLY0_bm (1<<0) /* SDRAM Row-to-Column Delay bit 0 mask. */ -#define EBI_ROWCOLDLY0_bp 0 /* SDRAM Row-to-Column Delay bit 0 position. */ -#define EBI_ROWCOLDLY1_bm (1<<1) /* SDRAM Row-to-Column Delay bit 1 mask. */ -#define EBI_ROWCOLDLY1_bp 1 /* SDRAM Row-to-Column Delay bit 1 position. */ -#define EBI_ROWCOLDLY2_bm (1<<2) /* SDRAM Row-to-Column Delay bit 2 mask. */ -#define EBI_ROWCOLDLY2_bp 2 /* SDRAM Row-to-Column Delay bit 2 position. */ - - -/* TWI - Two-Wire Interface */ -/* TWI_MASTER.CTRLA bit masks and bit positions */ -#define TWI_MASTER_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ -#define TWI_MASTER_INTLVL_gp 6 /* Interrupt Level group position. */ -#define TWI_MASTER_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ -#define TWI_MASTER_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ -#define TWI_MASTER_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ -#define TWI_MASTER_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ - -#define TWI_MASTER_RIEN_bm 0x20 /* Read Interrupt Enable bit mask. */ -#define TWI_MASTER_RIEN_bp 5 /* Read Interrupt Enable bit position. */ - -#define TWI_MASTER_WIEN_bm 0x10 /* Write Interrupt Enable bit mask. */ -#define TWI_MASTER_WIEN_bp 4 /* Write Interrupt Enable bit position. */ - -#define TWI_MASTER_ENABLE_bm 0x08 /* Enable TWI Master bit mask. */ -#define TWI_MASTER_ENABLE_bp 3 /* Enable TWI Master bit position. */ - - -/* TWI_MASTER.CTRLB bit masks and bit positions */ -#define TWI_MASTER_TIMEOUT_gm 0x0C /* Inactive Bus Timeout group mask. */ -#define TWI_MASTER_TIMEOUT_gp 2 /* Inactive Bus Timeout group position. */ -#define TWI_MASTER_TIMEOUT0_bm (1<<2) /* Inactive Bus Timeout bit 0 mask. */ -#define TWI_MASTER_TIMEOUT0_bp 2 /* Inactive Bus Timeout bit 0 position. */ -#define TWI_MASTER_TIMEOUT1_bm (1<<3) /* Inactive Bus Timeout bit 1 mask. */ -#define TWI_MASTER_TIMEOUT1_bp 3 /* Inactive Bus Timeout bit 1 position. */ - -#define TWI_MASTER_QCEN_bm 0x02 /* Quick Command Enable bit mask. */ -#define TWI_MASTER_QCEN_bp 1 /* Quick Command Enable bit position. */ - -#define TWI_MASTER_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ -#define TWI_MASTER_SMEN_bp 0 /* Smart Mode Enable bit position. */ - - -/* TWI_MASTER.CTRLC bit masks and bit positions */ -#define TWI_MASTER_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ -#define TWI_MASTER_ACKACT_bp 2 /* Acknowledge Action bit position. */ - -#define TWI_MASTER_CMD_gm 0x03 /* Command group mask. */ -#define TWI_MASTER_CMD_gp 0 /* Command group position. */ -#define TWI_MASTER_CMD0_bm (1<<0) /* Command bit 0 mask. */ -#define TWI_MASTER_CMD0_bp 0 /* Command bit 0 position. */ -#define TWI_MASTER_CMD1_bm (1<<1) /* Command bit 1 mask. */ -#define TWI_MASTER_CMD1_bp 1 /* Command bit 1 position. */ - - -/* TWI_MASTER.STATUS bit masks and bit positions */ -#define TWI_MASTER_RIF_bm 0x80 /* Read Interrupt Flag bit mask. */ -#define TWI_MASTER_RIF_bp 7 /* Read Interrupt Flag bit position. */ - -#define TWI_MASTER_WIF_bm 0x40 /* Write Interrupt Flag bit mask. */ -#define TWI_MASTER_WIF_bp 6 /* Write Interrupt Flag bit position. */ - -#define TWI_MASTER_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ -#define TWI_MASTER_CLKHOLD_bp 5 /* Clock Hold bit position. */ - -#define TWI_MASTER_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ -#define TWI_MASTER_RXACK_bp 4 /* Received Acknowledge bit position. */ - -#define TWI_MASTER_ARBLOST_bm 0x08 /* Arbitration Lost bit mask. */ -#define TWI_MASTER_ARBLOST_bp 3 /* Arbitration Lost bit position. */ - -#define TWI_MASTER_BUSERR_bm 0x04 /* Bus Error bit mask. */ -#define TWI_MASTER_BUSERR_bp 2 /* Bus Error bit position. */ - -#define TWI_MASTER_BUSSTATE_gm 0x03 /* Bus State group mask. */ -#define TWI_MASTER_BUSSTATE_gp 0 /* Bus State group position. */ -#define TWI_MASTER_BUSSTATE0_bm (1<<0) /* Bus State bit 0 mask. */ -#define TWI_MASTER_BUSSTATE0_bp 0 /* Bus State bit 0 position. */ -#define TWI_MASTER_BUSSTATE1_bm (1<<1) /* Bus State bit 1 mask. */ -#define TWI_MASTER_BUSSTATE1_bp 1 /* Bus State bit 1 position. */ - - -/* TWI_SLAVE.CTRLA bit masks and bit positions */ -#define TWI_SLAVE_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ -#define TWI_SLAVE_INTLVL_gp 6 /* Interrupt Level group position. */ -#define TWI_SLAVE_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ -#define TWI_SLAVE_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ -#define TWI_SLAVE_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ -#define TWI_SLAVE_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ - -#define TWI_SLAVE_DIEN_bm 0x20 /* Data Interrupt Enable bit mask. */ -#define TWI_SLAVE_DIEN_bp 5 /* Data Interrupt Enable bit position. */ - -#define TWI_SLAVE_APIEN_bm 0x10 /* Address/Stop Interrupt Enable bit mask. */ -#define TWI_SLAVE_APIEN_bp 4 /* Address/Stop Interrupt Enable bit position. */ - -#define TWI_SLAVE_ENABLE_bm 0x08 /* Enable TWI Slave bit mask. */ -#define TWI_SLAVE_ENABLE_bp 3 /* Enable TWI Slave bit position. */ - -#define TWI_SLAVE_PIEN_bm 0x04 /* Stop Interrupt Enable bit mask. */ -#define TWI_SLAVE_PIEN_bp 2 /* Stop Interrupt Enable bit position. */ - -#define TWI_SLAVE_PMEN_bm 0x02 /* Promiscuous Mode Enable bit mask. */ -#define TWI_SLAVE_PMEN_bp 1 /* Promiscuous Mode Enable bit position. */ - -#define TWI_SLAVE_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ -#define TWI_SLAVE_SMEN_bp 0 /* Smart Mode Enable bit position. */ - - -/* TWI_SLAVE.CTRLB bit masks and bit positions */ -#define TWI_SLAVE_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ -#define TWI_SLAVE_ACKACT_bp 2 /* Acknowledge Action bit position. */ - -#define TWI_SLAVE_CMD_gm 0x03 /* Command group mask. */ -#define TWI_SLAVE_CMD_gp 0 /* Command group position. */ -#define TWI_SLAVE_CMD0_bm (1<<0) /* Command bit 0 mask. */ -#define TWI_SLAVE_CMD0_bp 0 /* Command bit 0 position. */ -#define TWI_SLAVE_CMD1_bm (1<<1) /* Command bit 1 mask. */ -#define TWI_SLAVE_CMD1_bp 1 /* Command bit 1 position. */ - - -/* TWI_SLAVE.STATUS bit masks and bit positions */ -#define TWI_SLAVE_DIF_bm 0x80 /* Data Interrupt Flag bit mask. */ -#define TWI_SLAVE_DIF_bp 7 /* Data Interrupt Flag bit position. */ - -#define TWI_SLAVE_APIF_bm 0x40 /* Address/Stop Interrupt Flag bit mask. */ -#define TWI_SLAVE_APIF_bp 6 /* Address/Stop Interrupt Flag bit position. */ - -#define TWI_SLAVE_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ -#define TWI_SLAVE_CLKHOLD_bp 5 /* Clock Hold bit position. */ - -#define TWI_SLAVE_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ -#define TWI_SLAVE_RXACK_bp 4 /* Received Acknowledge bit position. */ - -#define TWI_SLAVE_COLL_bm 0x08 /* Collision bit mask. */ -#define TWI_SLAVE_COLL_bp 3 /* Collision bit position. */ - -#define TWI_SLAVE_BUSERR_bm 0x04 /* Bus Error bit mask. */ -#define TWI_SLAVE_BUSERR_bp 2 /* Bus Error bit position. */ - -#define TWI_SLAVE_DIR_bm 0x02 /* Read/Write Direction bit mask. */ -#define TWI_SLAVE_DIR_bp 1 /* Read/Write Direction bit position. */ - -#define TWI_SLAVE_AP_bm 0x01 /* Slave Address or Stop bit mask. */ -#define TWI_SLAVE_AP_bp 0 /* Slave Address or Stop bit position. */ - - -/* TWI_SLAVE.ADDRMASK bit masks and bit positions */ -#define TWI_SLAVE_ADDRMASK_gm 0xFE /* Address Mask group mask. */ -#define TWI_SLAVE_ADDRMASK_gp 1 /* Address Mask group position. */ -#define TWI_SLAVE_ADDRMASK0_bm (1<<1) /* Address Mask bit 0 mask. */ -#define TWI_SLAVE_ADDRMASK0_bp 1 /* Address Mask bit 0 position. */ -#define TWI_SLAVE_ADDRMASK1_bm (1<<2) /* Address Mask bit 1 mask. */ -#define TWI_SLAVE_ADDRMASK1_bp 2 /* Address Mask bit 1 position. */ -#define TWI_SLAVE_ADDRMASK2_bm (1<<3) /* Address Mask bit 2 mask. */ -#define TWI_SLAVE_ADDRMASK2_bp 3 /* Address Mask bit 2 position. */ -#define TWI_SLAVE_ADDRMASK3_bm (1<<4) /* Address Mask bit 3 mask. */ -#define TWI_SLAVE_ADDRMASK3_bp 4 /* Address Mask bit 3 position. */ -#define TWI_SLAVE_ADDRMASK4_bm (1<<5) /* Address Mask bit 4 mask. */ -#define TWI_SLAVE_ADDRMASK4_bp 5 /* Address Mask bit 4 position. */ -#define TWI_SLAVE_ADDRMASK5_bm (1<<6) /* Address Mask bit 5 mask. */ -#define TWI_SLAVE_ADDRMASK5_bp 6 /* Address Mask bit 5 position. */ -#define TWI_SLAVE_ADDRMASK6_bm (1<<7) /* Address Mask bit 6 mask. */ -#define TWI_SLAVE_ADDRMASK6_bp 7 /* Address Mask bit 6 position. */ - -#define TWI_SLAVE_ADDREN_bm 0x01 /* Address Enable bit mask. */ -#define TWI_SLAVE_ADDREN_bp 0 /* Address Enable bit position. */ - - -/* TWI.CTRL bit masks and bit positions */ -#define TWI_SDAHOLD_bm 0x02 /* SDA Hold Time Enable bit mask. */ -#define TWI_SDAHOLD_bp 1 /* SDA Hold Time Enable bit position. */ - -#define TWI_EDIEN_bm 0x01 /* External Driver Interface Enable bit mask. */ -#define TWI_EDIEN_bp 0 /* External Driver Interface Enable bit position. */ - - -/* PORT - Port Configuration */ -/* PORTCFG.VPCTRLA bit masks and bit positions */ -#define PORTCFG_VP1MAP_gm 0xF0 /* Virtual Port 1 Mapping group mask. */ -#define PORTCFG_VP1MAP_gp 4 /* Virtual Port 1 Mapping group position. */ -#define PORTCFG_VP1MAP0_bm (1<<4) /* Virtual Port 1 Mapping bit 0 mask. */ -#define PORTCFG_VP1MAP0_bp 4 /* Virtual Port 1 Mapping bit 0 position. */ -#define PORTCFG_VP1MAP1_bm (1<<5) /* Virtual Port 1 Mapping bit 1 mask. */ -#define PORTCFG_VP1MAP1_bp 5 /* Virtual Port 1 Mapping bit 1 position. */ -#define PORTCFG_VP1MAP2_bm (1<<6) /* Virtual Port 1 Mapping bit 2 mask. */ -#define PORTCFG_VP1MAP2_bp 6 /* Virtual Port 1 Mapping bit 2 position. */ -#define PORTCFG_VP1MAP3_bm (1<<7) /* Virtual Port 1 Mapping bit 3 mask. */ -#define PORTCFG_VP1MAP3_bp 7 /* Virtual Port 1 Mapping bit 3 position. */ - -#define PORTCFG_VP0MAP_gm 0x0F /* Virtual Port 0 Mapping group mask. */ -#define PORTCFG_VP0MAP_gp 0 /* Virtual Port 0 Mapping group position. */ -#define PORTCFG_VP0MAP0_bm (1<<0) /* Virtual Port 0 Mapping bit 0 mask. */ -#define PORTCFG_VP0MAP0_bp 0 /* Virtual Port 0 Mapping bit 0 position. */ -#define PORTCFG_VP0MAP1_bm (1<<1) /* Virtual Port 0 Mapping bit 1 mask. */ -#define PORTCFG_VP0MAP1_bp 1 /* Virtual Port 0 Mapping bit 1 position. */ -#define PORTCFG_VP0MAP2_bm (1<<2) /* Virtual Port 0 Mapping bit 2 mask. */ -#define PORTCFG_VP0MAP2_bp 2 /* Virtual Port 0 Mapping bit 2 position. */ -#define PORTCFG_VP0MAP3_bm (1<<3) /* Virtual Port 0 Mapping bit 3 mask. */ -#define PORTCFG_VP0MAP3_bp 3 /* Virtual Port 0 Mapping bit 3 position. */ - - -/* PORTCFG.VPCTRLB bit masks and bit positions */ -#define PORTCFG_VP3MAP_gm 0xF0 /* Virtual Port 3 Mapping group mask. */ -#define PORTCFG_VP3MAP_gp 4 /* Virtual Port 3 Mapping group position. */ -#define PORTCFG_VP3MAP0_bm (1<<4) /* Virtual Port 3 Mapping bit 0 mask. */ -#define PORTCFG_VP3MAP0_bp 4 /* Virtual Port 3 Mapping bit 0 position. */ -#define PORTCFG_VP3MAP1_bm (1<<5) /* Virtual Port 3 Mapping bit 1 mask. */ -#define PORTCFG_VP3MAP1_bp 5 /* Virtual Port 3 Mapping bit 1 position. */ -#define PORTCFG_VP3MAP2_bm (1<<6) /* Virtual Port 3 Mapping bit 2 mask. */ -#define PORTCFG_VP3MAP2_bp 6 /* Virtual Port 3 Mapping bit 2 position. */ -#define PORTCFG_VP3MAP3_bm (1<<7) /* Virtual Port 3 Mapping bit 3 mask. */ -#define PORTCFG_VP3MAP3_bp 7 /* Virtual Port 3 Mapping bit 3 position. */ - -#define PORTCFG_VP2MAP_gm 0x0F /* Virtual Port 2 Mapping group mask. */ -#define PORTCFG_VP2MAP_gp 0 /* Virtual Port 2 Mapping group position. */ -#define PORTCFG_VP2MAP0_bm (1<<0) /* Virtual Port 2 Mapping bit 0 mask. */ -#define PORTCFG_VP2MAP0_bp 0 /* Virtual Port 2 Mapping bit 0 position. */ -#define PORTCFG_VP2MAP1_bm (1<<1) /* Virtual Port 2 Mapping bit 1 mask. */ -#define PORTCFG_VP2MAP1_bp 1 /* Virtual Port 2 Mapping bit 1 position. */ -#define PORTCFG_VP2MAP2_bm (1<<2) /* Virtual Port 2 Mapping bit 2 mask. */ -#define PORTCFG_VP2MAP2_bp 2 /* Virtual Port 2 Mapping bit 2 position. */ -#define PORTCFG_VP2MAP3_bm (1<<3) /* Virtual Port 2 Mapping bit 3 mask. */ -#define PORTCFG_VP2MAP3_bp 3 /* Virtual Port 2 Mapping bit 3 position. */ - - -/* PORTCFG.CLKEVOUT bit masks and bit positions */ -#define PORTCFG_CLKOUT_gm 0x03 /* Clock Output Port group mask. */ -#define PORTCFG_CLKOUT_gp 0 /* Clock Output Port group position. */ -#define PORTCFG_CLKOUT0_bm (1<<0) /* Clock Output Port bit 0 mask. */ -#define PORTCFG_CLKOUT0_bp 0 /* Clock Output Port bit 0 position. */ -#define PORTCFG_CLKOUT1_bm (1<<1) /* Clock Output Port bit 1 mask. */ -#define PORTCFG_CLKOUT1_bp 1 /* Clock Output Port bit 1 position. */ - -#define PORTCFG_EVOUT_gm 0x30 /* Event Output Port group mask. */ -#define PORTCFG_EVOUT_gp 4 /* Event Output Port group position. */ -#define PORTCFG_EVOUT0_bm (1<<4) /* Event Output Port bit 0 mask. */ -#define PORTCFG_EVOUT0_bp 4 /* Event Output Port bit 0 position. */ -#define PORTCFG_EVOUT1_bm (1<<5) /* Event Output Port bit 1 mask. */ -#define PORTCFG_EVOUT1_bp 5 /* Event Output Port bit 1 position. */ - - -/* VPORT.INTFLAGS bit masks and bit positions */ -#define VPORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ -#define VPORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ - -#define VPORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ -#define VPORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ - - -/* PORT.INTCTRL bit masks and bit positions */ -#define PORT_INT1LVL_gm 0x0C /* Port Interrupt 1 Level group mask. */ -#define PORT_INT1LVL_gp 2 /* Port Interrupt 1 Level group position. */ -#define PORT_INT1LVL0_bm (1<<2) /* Port Interrupt 1 Level bit 0 mask. */ -#define PORT_INT1LVL0_bp 2 /* Port Interrupt 1 Level bit 0 position. */ -#define PORT_INT1LVL1_bm (1<<3) /* Port Interrupt 1 Level bit 1 mask. */ -#define PORT_INT1LVL1_bp 3 /* Port Interrupt 1 Level bit 1 position. */ - -#define PORT_INT0LVL_gm 0x03 /* Port Interrupt 0 Level group mask. */ -#define PORT_INT0LVL_gp 0 /* Port Interrupt 0 Level group position. */ -#define PORT_INT0LVL0_bm (1<<0) /* Port Interrupt 0 Level bit 0 mask. */ -#define PORT_INT0LVL0_bp 0 /* Port Interrupt 0 Level bit 0 position. */ -#define PORT_INT0LVL1_bm (1<<1) /* Port Interrupt 0 Level bit 1 mask. */ -#define PORT_INT0LVL1_bp 1 /* Port Interrupt 0 Level bit 1 position. */ - - -/* PORT.INTFLAGS bit masks and bit positions */ -#define PORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ -#define PORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ - -#define PORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ -#define PORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ - - -/* PORT.PIN0CTRL bit masks and bit positions */ -#define PORT_SRLEN_bm 0x80 /* Slew Rate Enable bit mask. */ -#define PORT_SRLEN_bp 7 /* Slew Rate Enable bit position. */ - -#define PORT_INVEN_bm 0x40 /* Inverted I/O Enable bit mask. */ -#define PORT_INVEN_bp 6 /* Inverted I/O Enable bit position. */ - -#define PORT_OPC_gm 0x38 /* Output/Pull Configuration group mask. */ -#define PORT_OPC_gp 3 /* Output/Pull Configuration group position. */ -#define PORT_OPC0_bm (1<<3) /* Output/Pull Configuration bit 0 mask. */ -#define PORT_OPC0_bp 3 /* Output/Pull Configuration bit 0 position. */ -#define PORT_OPC1_bm (1<<4) /* Output/Pull Configuration bit 1 mask. */ -#define PORT_OPC1_bp 4 /* Output/Pull Configuration bit 1 position. */ -#define PORT_OPC2_bm (1<<5) /* Output/Pull Configuration bit 2 mask. */ -#define PORT_OPC2_bp 5 /* Output/Pull Configuration bit 2 position. */ - -#define PORT_ISC_gm 0x07 /* Input/Sense Configuration group mask. */ -#define PORT_ISC_gp 0 /* Input/Sense Configuration group position. */ -#define PORT_ISC0_bm (1<<0) /* Input/Sense Configuration bit 0 mask. */ -#define PORT_ISC0_bp 0 /* Input/Sense Configuration bit 0 position. */ -#define PORT_ISC1_bm (1<<1) /* Input/Sense Configuration bit 1 mask. */ -#define PORT_ISC1_bp 1 /* Input/Sense Configuration bit 1 position. */ -#define PORT_ISC2_bm (1<<2) /* Input/Sense Configuration bit 2 mask. */ -#define PORT_ISC2_bp 2 /* Input/Sense Configuration bit 2 position. */ - - -/* PORT.PIN1CTRL bit masks and bit positions */ -/* PORT_SRLEN_bm Predefined. */ -/* PORT_SRLEN_bp Predefined. */ - -/* PORT_INVEN_bm Predefined. */ -/* PORT_INVEN_bp Predefined. */ - -/* PORT_OPC_gm Predefined. */ -/* PORT_OPC_gp Predefined. */ -/* PORT_OPC0_bm Predefined. */ -/* PORT_OPC0_bp Predefined. */ -/* PORT_OPC1_bm Predefined. */ -/* PORT_OPC1_bp Predefined. */ -/* PORT_OPC2_bm Predefined. */ -/* PORT_OPC2_bp Predefined. */ - -/* PORT_ISC_gm Predefined. */ -/* PORT_ISC_gp Predefined. */ -/* PORT_ISC0_bm Predefined. */ -/* PORT_ISC0_bp Predefined. */ -/* PORT_ISC1_bm Predefined. */ -/* PORT_ISC1_bp Predefined. */ -/* PORT_ISC2_bm Predefined. */ -/* PORT_ISC2_bp Predefined. */ - - -/* PORT.PIN2CTRL bit masks and bit positions */ -/* PORT_SRLEN_bm Predefined. */ -/* PORT_SRLEN_bp Predefined. */ - -/* PORT_INVEN_bm Predefined. */ -/* PORT_INVEN_bp Predefined. */ - -/* PORT_OPC_gm Predefined. */ -/* PORT_OPC_gp Predefined. */ -/* PORT_OPC0_bm Predefined. */ -/* PORT_OPC0_bp Predefined. */ -/* PORT_OPC1_bm Predefined. */ -/* PORT_OPC1_bp Predefined. */ -/* PORT_OPC2_bm Predefined. */ -/* PORT_OPC2_bp Predefined. */ - -/* PORT_ISC_gm Predefined. */ -/* PORT_ISC_gp Predefined. */ -/* PORT_ISC0_bm Predefined. */ -/* PORT_ISC0_bp Predefined. */ -/* PORT_ISC1_bm Predefined. */ -/* PORT_ISC1_bp Predefined. */ -/* PORT_ISC2_bm Predefined. */ -/* PORT_ISC2_bp Predefined. */ - - -/* PORT.PIN3CTRL bit masks and bit positions */ -/* PORT_SRLEN_bm Predefined. */ -/* PORT_SRLEN_bp Predefined. */ - -/* PORT_INVEN_bm Predefined. */ -/* PORT_INVEN_bp Predefined. */ - -/* PORT_OPC_gm Predefined. */ -/* PORT_OPC_gp Predefined. */ -/* PORT_OPC0_bm Predefined. */ -/* PORT_OPC0_bp Predefined. */ -/* PORT_OPC1_bm Predefined. */ -/* PORT_OPC1_bp Predefined. */ -/* PORT_OPC2_bm Predefined. */ -/* PORT_OPC2_bp Predefined. */ - -/* PORT_ISC_gm Predefined. */ -/* PORT_ISC_gp Predefined. */ -/* PORT_ISC0_bm Predefined. */ -/* PORT_ISC0_bp Predefined. */ -/* PORT_ISC1_bm Predefined. */ -/* PORT_ISC1_bp Predefined. */ -/* PORT_ISC2_bm Predefined. */ -/* PORT_ISC2_bp Predefined. */ - - -/* PORT.PIN4CTRL bit masks and bit positions */ -/* PORT_SRLEN_bm Predefined. */ -/* PORT_SRLEN_bp Predefined. */ - -/* PORT_INVEN_bm Predefined. */ -/* PORT_INVEN_bp Predefined. */ - -/* PORT_OPC_gm Predefined. */ -/* PORT_OPC_gp Predefined. */ -/* PORT_OPC0_bm Predefined. */ -/* PORT_OPC0_bp Predefined. */ -/* PORT_OPC1_bm Predefined. */ -/* PORT_OPC1_bp Predefined. */ -/* PORT_OPC2_bm Predefined. */ -/* PORT_OPC2_bp Predefined. */ - -/* PORT_ISC_gm Predefined. */ -/* PORT_ISC_gp Predefined. */ -/* PORT_ISC0_bm Predefined. */ -/* PORT_ISC0_bp Predefined. */ -/* PORT_ISC1_bm Predefined. */ -/* PORT_ISC1_bp Predefined. */ -/* PORT_ISC2_bm Predefined. */ -/* PORT_ISC2_bp Predefined. */ - - -/* PORT.PIN5CTRL bit masks and bit positions */ -/* PORT_SRLEN_bm Predefined. */ -/* PORT_SRLEN_bp Predefined. */ - -/* PORT_INVEN_bm Predefined. */ -/* PORT_INVEN_bp Predefined. */ - -/* PORT_OPC_gm Predefined. */ -/* PORT_OPC_gp Predefined. */ -/* PORT_OPC0_bm Predefined. */ -/* PORT_OPC0_bp Predefined. */ -/* PORT_OPC1_bm Predefined. */ -/* PORT_OPC1_bp Predefined. */ -/* PORT_OPC2_bm Predefined. */ -/* PORT_OPC2_bp Predefined. */ - -/* PORT_ISC_gm Predefined. */ -/* PORT_ISC_gp Predefined. */ -/* PORT_ISC0_bm Predefined. */ -/* PORT_ISC0_bp Predefined. */ -/* PORT_ISC1_bm Predefined. */ -/* PORT_ISC1_bp Predefined. */ -/* PORT_ISC2_bm Predefined. */ -/* PORT_ISC2_bp Predefined. */ - - -/* PORT.PIN6CTRL bit masks and bit positions */ -/* PORT_SRLEN_bm Predefined. */ -/* PORT_SRLEN_bp Predefined. */ - -/* PORT_INVEN_bm Predefined. */ -/* PORT_INVEN_bp Predefined. */ - -/* PORT_OPC_gm Predefined. */ -/* PORT_OPC_gp Predefined. */ -/* PORT_OPC0_bm Predefined. */ -/* PORT_OPC0_bp Predefined. */ -/* PORT_OPC1_bm Predefined. */ -/* PORT_OPC1_bp Predefined. */ -/* PORT_OPC2_bm Predefined. */ -/* PORT_OPC2_bp Predefined. */ - -/* PORT_ISC_gm Predefined. */ -/* PORT_ISC_gp Predefined. */ -/* PORT_ISC0_bm Predefined. */ -/* PORT_ISC0_bp Predefined. */ -/* PORT_ISC1_bm Predefined. */ -/* PORT_ISC1_bp Predefined. */ -/* PORT_ISC2_bm Predefined. */ -/* PORT_ISC2_bp Predefined. */ - - -/* PORT.PIN7CTRL bit masks and bit positions */ -/* PORT_SRLEN_bm Predefined. */ -/* PORT_SRLEN_bp Predefined. */ - -/* PORT_INVEN_bm Predefined. */ -/* PORT_INVEN_bp Predefined. */ - -/* PORT_OPC_gm Predefined. */ -/* PORT_OPC_gp Predefined. */ -/* PORT_OPC0_bm Predefined. */ -/* PORT_OPC0_bp Predefined. */ -/* PORT_OPC1_bm Predefined. */ -/* PORT_OPC1_bp Predefined. */ -/* PORT_OPC2_bm Predefined. */ -/* PORT_OPC2_bp Predefined. */ - -/* PORT_ISC_gm Predefined. */ -/* PORT_ISC_gp Predefined. */ -/* PORT_ISC0_bm Predefined. */ -/* PORT_ISC0_bp Predefined. */ -/* PORT_ISC1_bm Predefined. */ -/* PORT_ISC1_bp Predefined. */ -/* PORT_ISC2_bm Predefined. */ -/* PORT_ISC2_bp Predefined. */ - - -/* TC - 16-bit Timer/Counter With PWM */ -/* TC0.CTRLA bit masks and bit positions */ -#define TC0_CLKSEL_gm 0x0F /* Clock Selection group mask. */ -#define TC0_CLKSEL_gp 0 /* Clock Selection group position. */ -#define TC0_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ -#define TC0_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ -#define TC0_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ -#define TC0_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ -#define TC0_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ -#define TC0_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ -#define TC0_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ -#define TC0_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ - - -/* TC0.CTRLB bit masks and bit positions */ -#define TC0_CCDEN_bm 0x80 /* Compare or Capture D Enable bit mask. */ -#define TC0_CCDEN_bp 7 /* Compare or Capture D Enable bit position. */ - -#define TC0_CCCEN_bm 0x40 /* Compare or Capture C Enable bit mask. */ -#define TC0_CCCEN_bp 6 /* Compare or Capture C Enable bit position. */ - -#define TC0_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ -#define TC0_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ - -#define TC0_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ -#define TC0_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ - -#define TC0_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ -#define TC0_WGMODE_gp 0 /* Waveform generation mode group position. */ -#define TC0_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ -#define TC0_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ -#define TC0_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ -#define TC0_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ -#define TC0_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ -#define TC0_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ - - -/* TC0.CTRLC bit masks and bit positions */ -#define TC0_CMPD_bm 0x08 /* Compare D Output Value bit mask. */ -#define TC0_CMPD_bp 3 /* Compare D Output Value bit position. */ - -#define TC0_CMPC_bm 0x04 /* Compare C Output Value bit mask. */ -#define TC0_CMPC_bp 2 /* Compare C Output Value bit position. */ - -#define TC0_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ -#define TC0_CMPB_bp 1 /* Compare B Output Value bit position. */ - -#define TC0_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ -#define TC0_CMPA_bp 0 /* Compare A Output Value bit position. */ - - -/* TC0.CTRLD bit masks and bit positions */ -#define TC0_EVACT_gm 0xE0 /* Event Action group mask. */ -#define TC0_EVACT_gp 5 /* Event Action group position. */ -#define TC0_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ -#define TC0_EVACT0_bp 5 /* Event Action bit 0 position. */ -#define TC0_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ -#define TC0_EVACT1_bp 6 /* Event Action bit 1 position. */ -#define TC0_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ -#define TC0_EVACT2_bp 7 /* Event Action bit 2 position. */ - -#define TC0_EVDLY_bm 0x10 /* Event Delay bit mask. */ -#define TC0_EVDLY_bp 4 /* Event Delay bit position. */ - -#define TC0_EVSEL_gm 0x0F /* Event Source Select group mask. */ -#define TC0_EVSEL_gp 0 /* Event Source Select group position. */ -#define TC0_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ -#define TC0_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ -#define TC0_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ -#define TC0_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ -#define TC0_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ -#define TC0_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ -#define TC0_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ -#define TC0_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ - - -/* TC0.CTRLE bit masks and bit positions */ -#define TC0_DTHM_bm 0x02 /* Dead Time Hold Mode bit mask. */ -#define TC0_DTHM_bp 1 /* Dead Time Hold Mode bit position. */ - -#define TC0_BYTEM_bm 0x01 /* Byte Mode bit mask. */ -#define TC0_BYTEM_bp 0 /* Byte Mode bit position. */ - - -/* TC0.INTCTRLA bit masks and bit positions */ -#define TC0_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ -#define TC0_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ -#define TC0_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ -#define TC0_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ -#define TC0_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ -#define TC0_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ - -#define TC0_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ -#define TC0_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ -#define TC0_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ -#define TC0_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ -#define TC0_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ -#define TC0_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ - - -/* TC0.INTCTRLB bit masks and bit positions */ -#define TC0_CCDINTLVL_gm 0xC0 /* Compare or Capture D Interrupt Level group mask. */ -#define TC0_CCDINTLVL_gp 6 /* Compare or Capture D Interrupt Level group position. */ -#define TC0_CCDINTLVL0_bm (1<<6) /* Compare or Capture D Interrupt Level bit 0 mask. */ -#define TC0_CCDINTLVL0_bp 6 /* Compare or Capture D Interrupt Level bit 0 position. */ -#define TC0_CCDINTLVL1_bm (1<<7) /* Compare or Capture D Interrupt Level bit 1 mask. */ -#define TC0_CCDINTLVL1_bp 7 /* Compare or Capture D Interrupt Level bit 1 position. */ - -#define TC0_CCCINTLVL_gm 0x30 /* Compare or Capture C Interrupt Level group mask. */ -#define TC0_CCCINTLVL_gp 4 /* Compare or Capture C Interrupt Level group position. */ -#define TC0_CCCINTLVL0_bm (1<<4) /* Compare or Capture C Interrupt Level bit 0 mask. */ -#define TC0_CCCINTLVL0_bp 4 /* Compare or Capture C Interrupt Level bit 0 position. */ -#define TC0_CCCINTLVL1_bm (1<<5) /* Compare or Capture C Interrupt Level bit 1 mask. */ -#define TC0_CCCINTLVL1_bp 5 /* Compare or Capture C Interrupt Level bit 1 position. */ - -#define TC0_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ -#define TC0_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ -#define TC0_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ -#define TC0_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ -#define TC0_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ -#define TC0_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ - -#define TC0_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ -#define TC0_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ -#define TC0_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ -#define TC0_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ -#define TC0_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ -#define TC0_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ - - -/* TC0.CTRLFCLR bit masks and bit positions */ -#define TC0_CMD_gm 0x0C /* Command group mask. */ -#define TC0_CMD_gp 2 /* Command group position. */ -#define TC0_CMD0_bm (1<<2) /* Command bit 0 mask. */ -#define TC0_CMD0_bp 2 /* Command bit 0 position. */ -#define TC0_CMD1_bm (1<<3) /* Command bit 1 mask. */ -#define TC0_CMD1_bp 3 /* Command bit 1 position. */ - -#define TC0_LUPD_bm 0x02 /* Lock Update bit mask. */ -#define TC0_LUPD_bp 1 /* Lock Update bit position. */ - -#define TC0_DIR_bm 0x01 /* Direction bit mask. */ -#define TC0_DIR_bp 0 /* Direction bit position. */ - - -/* TC0.CTRLFSET bit masks and bit positions */ -/* TC0_CMD_gm Predefined. */ -/* TC0_CMD_gp Predefined. */ -/* TC0_CMD0_bm Predefined. */ -/* TC0_CMD0_bp Predefined. */ -/* TC0_CMD1_bm Predefined. */ -/* TC0_CMD1_bp Predefined. */ - -/* TC0_LUPD_bm Predefined. */ -/* TC0_LUPD_bp Predefined. */ - -/* TC0_DIR_bm Predefined. */ -/* TC0_DIR_bp Predefined. */ - - -/* TC0.CTRLGCLR bit masks and bit positions */ -#define TC0_CCDBV_bm 0x10 /* Compare or Capture D Buffer Valid bit mask. */ -#define TC0_CCDBV_bp 4 /* Compare or Capture D Buffer Valid bit position. */ - -#define TC0_CCCBV_bm 0x08 /* Compare or Capture C Buffer Valid bit mask. */ -#define TC0_CCCBV_bp 3 /* Compare or Capture C Buffer Valid bit position. */ - -#define TC0_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ -#define TC0_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ - -#define TC0_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ -#define TC0_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ - -#define TC0_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ -#define TC0_PERBV_bp 0 /* Period Buffer Valid bit position. */ - - -/* TC0.CTRLGSET bit masks and bit positions */ -/* TC0_CCDBV_bm Predefined. */ -/* TC0_CCDBV_bp Predefined. */ - -/* TC0_CCCBV_bm Predefined. */ -/* TC0_CCCBV_bp Predefined. */ - -/* TC0_CCBBV_bm Predefined. */ -/* TC0_CCBBV_bp Predefined. */ - -/* TC0_CCABV_bm Predefined. */ -/* TC0_CCABV_bp Predefined. */ - -/* TC0_PERBV_bm Predefined. */ -/* TC0_PERBV_bp Predefined. */ - - -/* TC0.INTFLAGS bit masks and bit positions */ -#define TC0_CCDIF_bm 0x80 /* Compare or Capture D Interrupt Flag bit mask. */ -#define TC0_CCDIF_bp 7 /* Compare or Capture D Interrupt Flag bit position. */ - -#define TC0_CCCIF_bm 0x40 /* Compare or Capture C Interrupt Flag bit mask. */ -#define TC0_CCCIF_bp 6 /* Compare or Capture C Interrupt Flag bit position. */ - -#define TC0_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ -#define TC0_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ - -#define TC0_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ -#define TC0_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ - -#define TC0_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ -#define TC0_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ - -#define TC0_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ -#define TC0_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ - - -/* TC1.CTRLA bit masks and bit positions */ -#define TC1_CLKSEL_gm 0x0F /* Clock Selection group mask. */ -#define TC1_CLKSEL_gp 0 /* Clock Selection group position. */ -#define TC1_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ -#define TC1_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ -#define TC1_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ -#define TC1_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ -#define TC1_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ -#define TC1_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ -#define TC1_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ -#define TC1_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ - - -/* TC1.CTRLB bit masks and bit positions */ -#define TC1_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ -#define TC1_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ - -#define TC1_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ -#define TC1_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ - -#define TC1_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ -#define TC1_WGMODE_gp 0 /* Waveform generation mode group position. */ -#define TC1_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ -#define TC1_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ -#define TC1_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ -#define TC1_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ -#define TC1_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ -#define TC1_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ - - -/* TC1.CTRLC bit masks and bit positions */ -#define TC1_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ -#define TC1_CMPB_bp 1 /* Compare B Output Value bit position. */ - -#define TC1_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ -#define TC1_CMPA_bp 0 /* Compare A Output Value bit position. */ - - -/* TC1.CTRLD bit masks and bit positions */ -#define TC1_EVACT_gm 0xE0 /* Event Action group mask. */ -#define TC1_EVACT_gp 5 /* Event Action group position. */ -#define TC1_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ -#define TC1_EVACT0_bp 5 /* Event Action bit 0 position. */ -#define TC1_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ -#define TC1_EVACT1_bp 6 /* Event Action bit 1 position. */ -#define TC1_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ -#define TC1_EVACT2_bp 7 /* Event Action bit 2 position. */ - -#define TC1_EVDLY_bm 0x10 /* Event Delay bit mask. */ -#define TC1_EVDLY_bp 4 /* Event Delay bit position. */ - -#define TC1_EVSEL_gm 0x0F /* Event Source Select group mask. */ -#define TC1_EVSEL_gp 0 /* Event Source Select group position. */ -#define TC1_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ -#define TC1_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ -#define TC1_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ -#define TC1_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ -#define TC1_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ -#define TC1_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ -#define TC1_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ -#define TC1_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ - - -/* TC1.CTRLE bit masks and bit positions */ -#define TC1_DTHM_bm 0x02 /* Dead Time Hold Mode bit mask. */ -#define TC1_DTHM_bp 1 /* Dead Time Hold Mode bit position. */ - -#define TC1_BYTEM_bm 0x01 /* Byte Mode bit mask. */ -#define TC1_BYTEM_bp 0 /* Byte Mode bit position. */ - - -/* TC1.INTCTRLA bit masks and bit positions */ -#define TC1_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ -#define TC1_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ -#define TC1_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ -#define TC1_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ -#define TC1_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ -#define TC1_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ - -#define TC1_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ -#define TC1_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ -#define TC1_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ -#define TC1_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ -#define TC1_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ -#define TC1_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ - - -/* TC1.INTCTRLB bit masks and bit positions */ -#define TC1_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ -#define TC1_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ -#define TC1_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ -#define TC1_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ -#define TC1_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ -#define TC1_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ - -#define TC1_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ -#define TC1_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ -#define TC1_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ -#define TC1_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ -#define TC1_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ -#define TC1_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ - - -/* TC1.CTRLFCLR bit masks and bit positions */ -#define TC1_CMD_gm 0x0C /* Command group mask. */ -#define TC1_CMD_gp 2 /* Command group position. */ -#define TC1_CMD0_bm (1<<2) /* Command bit 0 mask. */ -#define TC1_CMD0_bp 2 /* Command bit 0 position. */ -#define TC1_CMD1_bm (1<<3) /* Command bit 1 mask. */ -#define TC1_CMD1_bp 3 /* Command bit 1 position. */ - -#define TC1_LUPD_bm 0x02 /* Lock Update bit mask. */ -#define TC1_LUPD_bp 1 /* Lock Update bit position. */ - -#define TC1_DIR_bm 0x01 /* Direction bit mask. */ -#define TC1_DIR_bp 0 /* Direction bit position. */ - - -/* TC1.CTRLFSET bit masks and bit positions */ -/* TC1_CMD_gm Predefined. */ -/* TC1_CMD_gp Predefined. */ -/* TC1_CMD0_bm Predefined. */ -/* TC1_CMD0_bp Predefined. */ -/* TC1_CMD1_bm Predefined. */ -/* TC1_CMD1_bp Predefined. */ - -/* TC1_LUPD_bm Predefined. */ -/* TC1_LUPD_bp Predefined. */ - -/* TC1_DIR_bm Predefined. */ -/* TC1_DIR_bp Predefined. */ - - -/* TC1.CTRLGCLR bit masks and bit positions */ -#define TC1_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ -#define TC1_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ - -#define TC1_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ -#define TC1_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ - -#define TC1_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ -#define TC1_PERBV_bp 0 /* Period Buffer Valid bit position. */ - - -/* TC1.CTRLGSET bit masks and bit positions */ -/* TC1_CCBBV_bm Predefined. */ -/* TC1_CCBBV_bp Predefined. */ - -/* TC1_CCABV_bm Predefined. */ -/* TC1_CCABV_bp Predefined. */ - -/* TC1_PERBV_bm Predefined. */ -/* TC1_PERBV_bp Predefined. */ - - -/* TC1.INTFLAGS bit masks and bit positions */ -#define TC1_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ -#define TC1_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ - -#define TC1_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ -#define TC1_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ - -#define TC1_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ -#define TC1_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ - -#define TC1_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ -#define TC1_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ - - -/* AWEX.CTRL bit masks and bit positions */ -#define AWEX_PGM_bm 0x20 /* Pattern Generation Mode bit mask. */ -#define AWEX_PGM_bp 5 /* Pattern Generation Mode bit position. */ - -#define AWEX_CWCM_bm 0x10 /* Common Waveform Channel Mode bit mask. */ -#define AWEX_CWCM_bp 4 /* Common Waveform Channel Mode bit position. */ - -#define AWEX_DTICCDEN_bm 0x08 /* Dead Time Insertion Compare Channel D Enable bit mask. */ -#define AWEX_DTICCDEN_bp 3 /* Dead Time Insertion Compare Channel D Enable bit position. */ - -#define AWEX_DTICCCEN_bm 0x04 /* Dead Time Insertion Compare Channel C Enable bit mask. */ -#define AWEX_DTICCCEN_bp 2 /* Dead Time Insertion Compare Channel C Enable bit position. */ - -#define AWEX_DTICCBEN_bm 0x02 /* Dead Time Insertion Compare Channel B Enable bit mask. */ -#define AWEX_DTICCBEN_bp 1 /* Dead Time Insertion Compare Channel B Enable bit position. */ - -#define AWEX_DTICCAEN_bm 0x01 /* Dead Time Insertion Compare Channel A Enable bit mask. */ -#define AWEX_DTICCAEN_bp 0 /* Dead Time Insertion Compare Channel A Enable bit position. */ - - -/* AWEX.FDCTRL bit masks and bit positions */ -#define AWEX_FDDBD_bm 0x10 /* Fault Detect on Disable Break Disable bit mask. */ -#define AWEX_FDDBD_bp 4 /* Fault Detect on Disable Break Disable bit position. */ - -#define AWEX_FDMODE_bm 0x04 /* Fault Detect Mode bit mask. */ -#define AWEX_FDMODE_bp 2 /* Fault Detect Mode bit position. */ - -#define AWEX_FDACT_gm 0x03 /* Fault Detect Action group mask. */ -#define AWEX_FDACT_gp 0 /* Fault Detect Action group position. */ -#define AWEX_FDACT0_bm (1<<0) /* Fault Detect Action bit 0 mask. */ -#define AWEX_FDACT0_bp 0 /* Fault Detect Action bit 0 position. */ -#define AWEX_FDACT1_bm (1<<1) /* Fault Detect Action bit 1 mask. */ -#define AWEX_FDACT1_bp 1 /* Fault Detect Action bit 1 position. */ - - -/* AWEX.STATUS bit masks and bit positions */ -#define AWEX_FDF_bm 0x04 /* Fault Detect Flag bit mask. */ -#define AWEX_FDF_bp 2 /* Fault Detect Flag bit position. */ - -#define AWEX_DTHSBUFV_bm 0x02 /* Dead Time High Side Buffer Valid bit mask. */ -#define AWEX_DTHSBUFV_bp 1 /* Dead Time High Side Buffer Valid bit position. */ - -#define AWEX_DTLSBUFV_bm 0x01 /* Dead Time Low Side Buffer Valid bit mask. */ -#define AWEX_DTLSBUFV_bp 0 /* Dead Time Low Side Buffer Valid bit position. */ - - -/* HIRES.CTRL bit masks and bit positions */ -#define HIRES_HREN_gm 0x03 /* High Resolution Enable group mask. */ -#define HIRES_HREN_gp 0 /* High Resolution Enable group position. */ -#define HIRES_HREN0_bm (1<<0) /* High Resolution Enable bit 0 mask. */ -#define HIRES_HREN0_bp 0 /* High Resolution Enable bit 0 position. */ -#define HIRES_HREN1_bm (1<<1) /* High Resolution Enable bit 1 mask. */ -#define HIRES_HREN1_bp 1 /* High Resolution Enable bit 1 position. */ - - -/* USART - Universal Asynchronous Receiver-Transmitter */ -/* USART.STATUS bit masks and bit positions */ -#define USART_RXCIF_bm 0x80 /* Receive Interrupt Flag bit mask. */ -#define USART_RXCIF_bp 7 /* Receive Interrupt Flag bit position. */ - -#define USART_TXCIF_bm 0x40 /* Transmit Interrupt Flag bit mask. */ -#define USART_TXCIF_bp 6 /* Transmit Interrupt Flag bit position. */ - -#define USART_DREIF_bm 0x20 /* Data Register Empty Flag bit mask. */ -#define USART_DREIF_bp 5 /* Data Register Empty Flag bit position. */ - -#define USART_FERR_bm 0x10 /* Frame Error bit mask. */ -#define USART_FERR_bp 4 /* Frame Error bit position. */ - -#define USART_BUFOVF_bm 0x08 /* Buffer Overflow bit mask. */ -#define USART_BUFOVF_bp 3 /* Buffer Overflow bit position. */ - -#define USART_PERR_bm 0x04 /* Parity Error bit mask. */ -#define USART_PERR_bp 2 /* Parity Error bit position. */ - -#define USART_RXB8_bm 0x01 /* Receive Bit 8 bit mask. */ -#define USART_RXB8_bp 0 /* Receive Bit 8 bit position. */ - - -/* USART.CTRLA bit masks and bit positions */ -#define USART_RXCINTLVL_gm 0x30 /* Receive Interrupt Level group mask. */ -#define USART_RXCINTLVL_gp 4 /* Receive Interrupt Level group position. */ -#define USART_RXCINTLVL0_bm (1<<4) /* Receive Interrupt Level bit 0 mask. */ -#define USART_RXCINTLVL0_bp 4 /* Receive Interrupt Level bit 0 position. */ -#define USART_RXCINTLVL1_bm (1<<5) /* Receive Interrupt Level bit 1 mask. */ -#define USART_RXCINTLVL1_bp 5 /* Receive Interrupt Level bit 1 position. */ - -#define USART_TXCINTLVL_gm 0x0C /* Transmit Interrupt Level group mask. */ -#define USART_TXCINTLVL_gp 2 /* Transmit Interrupt Level group position. */ -#define USART_TXCINTLVL0_bm (1<<2) /* Transmit Interrupt Level bit 0 mask. */ -#define USART_TXCINTLVL0_bp 2 /* Transmit Interrupt Level bit 0 position. */ -#define USART_TXCINTLVL1_bm (1<<3) /* Transmit Interrupt Level bit 1 mask. */ -#define USART_TXCINTLVL1_bp 3 /* Transmit Interrupt Level bit 1 position. */ - -#define USART_DREINTLVL_gm 0x03 /* Data Register Empty Interrupt Level group mask. */ -#define USART_DREINTLVL_gp 0 /* Data Register Empty Interrupt Level group position. */ -#define USART_DREINTLVL0_bm (1<<0) /* Data Register Empty Interrupt Level bit 0 mask. */ -#define USART_DREINTLVL0_bp 0 /* Data Register Empty Interrupt Level bit 0 position. */ -#define USART_DREINTLVL1_bm (1<<1) /* Data Register Empty Interrupt Level bit 1 mask. */ -#define USART_DREINTLVL1_bp 1 /* Data Register Empty Interrupt Level bit 1 position. */ - - -/* USART.CTRLB bit masks and bit positions */ -#define USART_RXEN_bm 0x10 /* Receiver Enable bit mask. */ -#define USART_RXEN_bp 4 /* Receiver Enable bit position. */ - -#define USART_TXEN_bm 0x08 /* Transmitter Enable bit mask. */ -#define USART_TXEN_bp 3 /* Transmitter Enable bit position. */ - -#define USART_CLK2X_bm 0x04 /* Double transmission speed bit mask. */ -#define USART_CLK2X_bp 2 /* Double transmission speed bit position. */ - -#define USART_MPCM_bm 0x02 /* Multi-processor Communication Mode bit mask. */ -#define USART_MPCM_bp 1 /* Multi-processor Communication Mode bit position. */ - -#define USART_TXB8_bm 0x01 /* Transmit bit 8 bit mask. */ -#define USART_TXB8_bp 0 /* Transmit bit 8 bit position. */ - - -/* USART.CTRLC bit masks and bit positions */ -#define USART_CMODE_gm 0xC0 /* Communication Mode group mask. */ -#define USART_CMODE_gp 6 /* Communication Mode group position. */ -#define USART_CMODE0_bm (1<<6) /* Communication Mode bit 0 mask. */ -#define USART_CMODE0_bp 6 /* Communication Mode bit 0 position. */ -#define USART_CMODE1_bm (1<<7) /* Communication Mode bit 1 mask. */ -#define USART_CMODE1_bp 7 /* Communication Mode bit 1 position. */ - -#define USART_PMODE_gm 0x30 /* Parity Mode group mask. */ -#define USART_PMODE_gp 4 /* Parity Mode group position. */ -#define USART_PMODE0_bm (1<<4) /* Parity Mode bit 0 mask. */ -#define USART_PMODE0_bp 4 /* Parity Mode bit 0 position. */ -#define USART_PMODE1_bm (1<<5) /* Parity Mode bit 1 mask. */ -#define USART_PMODE1_bp 5 /* Parity Mode bit 1 position. */ - -#define USART_SBMODE_bm 0x08 /* Stop Bit Mode bit mask. */ -#define USART_SBMODE_bp 3 /* Stop Bit Mode bit position. */ - -#define USART_CHSIZE_gm 0x07 /* Character Size group mask. */ -#define USART_CHSIZE_gp 0 /* Character Size group position. */ -#define USART_CHSIZE0_bm (1<<0) /* Character Size bit 0 mask. */ -#define USART_CHSIZE0_bp 0 /* Character Size bit 0 position. */ -#define USART_CHSIZE1_bm (1<<1) /* Character Size bit 1 mask. */ -#define USART_CHSIZE1_bp 1 /* Character Size bit 1 position. */ -#define USART_CHSIZE2_bm (1<<2) /* Character Size bit 2 mask. */ -#define USART_CHSIZE2_bp 2 /* Character Size bit 2 position. */ - - -/* USART.BAUDCTRLA bit masks and bit positions */ -#define USART_BSEL_gm 0xFF /* Baud Rate Selection Bits [7:0] group mask. */ -#define USART_BSEL_gp 0 /* Baud Rate Selection Bits [7:0] group position. */ -#define USART_BSEL0_bm (1<<0) /* Baud Rate Selection Bits [7:0] bit 0 mask. */ -#define USART_BSEL0_bp 0 /* Baud Rate Selection Bits [7:0] bit 0 position. */ -#define USART_BSEL1_bm (1<<1) /* Baud Rate Selection Bits [7:0] bit 1 mask. */ -#define USART_BSEL1_bp 1 /* Baud Rate Selection Bits [7:0] bit 1 position. */ -#define USART_BSEL2_bm (1<<2) /* Baud Rate Selection Bits [7:0] bit 2 mask. */ -#define USART_BSEL2_bp 2 /* Baud Rate Selection Bits [7:0] bit 2 position. */ -#define USART_BSEL3_bm (1<<3) /* Baud Rate Selection Bits [7:0] bit 3 mask. */ -#define USART_BSEL3_bp 3 /* Baud Rate Selection Bits [7:0] bit 3 position. */ -#define USART_BSEL4_bm (1<<4) /* Baud Rate Selection Bits [7:0] bit 4 mask. */ -#define USART_BSEL4_bp 4 /* Baud Rate Selection Bits [7:0] bit 4 position. */ -#define USART_BSEL5_bm (1<<5) /* Baud Rate Selection Bits [7:0] bit 5 mask. */ -#define USART_BSEL5_bp 5 /* Baud Rate Selection Bits [7:0] bit 5 position. */ -#define USART_BSEL6_bm (1<<6) /* Baud Rate Selection Bits [7:0] bit 6 mask. */ -#define USART_BSEL6_bp 6 /* Baud Rate Selection Bits [7:0] bit 6 position. */ -#define USART_BSEL7_bm (1<<7) /* Baud Rate Selection Bits [7:0] bit 7 mask. */ -#define USART_BSEL7_bp 7 /* Baud Rate Selection Bits [7:0] bit 7 position. */ - - -/* USART.BAUDCTRLB bit masks and bit positions */ -#define USART_BSCALE_gm 0xF0 /* Baud Rate Scale group mask. */ -#define USART_BSCALE_gp 4 /* Baud Rate Scale group position. */ -#define USART_BSCALE0_bm (1<<4) /* Baud Rate Scale bit 0 mask. */ -#define USART_BSCALE0_bp 4 /* Baud Rate Scale bit 0 position. */ -#define USART_BSCALE1_bm (1<<5) /* Baud Rate Scale bit 1 mask. */ -#define USART_BSCALE1_bp 5 /* Baud Rate Scale bit 1 position. */ -#define USART_BSCALE2_bm (1<<6) /* Baud Rate Scale bit 2 mask. */ -#define USART_BSCALE2_bp 6 /* Baud Rate Scale bit 2 position. */ -#define USART_BSCALE3_bm (1<<7) /* Baud Rate Scale bit 3 mask. */ -#define USART_BSCALE3_bp 7 /* Baud Rate Scale bit 3 position. */ - -/* USART_BSEL_gm Predefined. */ -/* USART_BSEL_gp Predefined. */ -/* USART_BSEL0_bm Predefined. */ -/* USART_BSEL0_bp Predefined. */ -/* USART_BSEL1_bm Predefined. */ -/* USART_BSEL1_bp Predefined. */ -/* USART_BSEL2_bm Predefined. */ -/* USART_BSEL2_bp Predefined. */ -/* USART_BSEL3_bm Predefined. */ -/* USART_BSEL3_bp Predefined. */ - - -/* SPI - Serial Peripheral Interface */ -/* SPI.CTRL bit masks and bit positions */ -#define SPI_CLK2X_bm 0x80 /* Enable Double Speed bit mask. */ -#define SPI_CLK2X_bp 7 /* Enable Double Speed bit position. */ - -#define SPI_ENABLE_bm 0x40 /* Enable Module bit mask. */ -#define SPI_ENABLE_bp 6 /* Enable Module bit position. */ - -#define SPI_DORD_bm 0x20 /* Data Order Setting bit mask. */ -#define SPI_DORD_bp 5 /* Data Order Setting bit position. */ - -#define SPI_MASTER_bm 0x10 /* Master Operation Enable bit mask. */ -#define SPI_MASTER_bp 4 /* Master Operation Enable bit position. */ - -#define SPI_MODE_gm 0x0C /* SPI Mode group mask. */ -#define SPI_MODE_gp 2 /* SPI Mode group position. */ -#define SPI_MODE0_bm (1<<2) /* SPI Mode bit 0 mask. */ -#define SPI_MODE0_bp 2 /* SPI Mode bit 0 position. */ -#define SPI_MODE1_bm (1<<3) /* SPI Mode bit 1 mask. */ -#define SPI_MODE1_bp 3 /* SPI Mode bit 1 position. */ - -#define SPI_PRESCALER_gm 0x03 /* Prescaler group mask. */ -#define SPI_PRESCALER_gp 0 /* Prescaler group position. */ -#define SPI_PRESCALER0_bm (1<<0) /* Prescaler bit 0 mask. */ -#define SPI_PRESCALER0_bp 0 /* Prescaler bit 0 position. */ -#define SPI_PRESCALER1_bm (1<<1) /* Prescaler bit 1 mask. */ -#define SPI_PRESCALER1_bp 1 /* Prescaler bit 1 position. */ - - -/* SPI.INTCTRL bit masks and bit positions */ -#define SPI_INTLVL_gm 0x03 /* Interrupt level group mask. */ -#define SPI_INTLVL_gp 0 /* Interrupt level group position. */ -#define SPI_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */ -#define SPI_INTLVL0_bp 0 /* Interrupt level bit 0 position. */ -#define SPI_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */ -#define SPI_INTLVL1_bp 1 /* Interrupt level bit 1 position. */ - - -/* SPI.STATUS bit masks and bit positions */ -#define SPI_IF_bm 0x80 /* Interrupt Flag bit mask. */ -#define SPI_IF_bp 7 /* Interrupt Flag bit position. */ - -#define SPI_WRCOL_bm 0x40 /* Write Collision bit mask. */ -#define SPI_WRCOL_bp 6 /* Write Collision bit position. */ - - -/* IRCOM - IR Communication Module */ -/* IRCOM.CTRL bit masks and bit positions */ -#define IRCOM_EVSEL_gm 0x0F /* Event Channel Select group mask. */ -#define IRCOM_EVSEL_gp 0 /* Event Channel Select group position. */ -#define IRCOM_EVSEL0_bm (1<<0) /* Event Channel Select bit 0 mask. */ -#define IRCOM_EVSEL0_bp 0 /* Event Channel Select bit 0 position. */ -#define IRCOM_EVSEL1_bm (1<<1) /* Event Channel Select bit 1 mask. */ -#define IRCOM_EVSEL1_bp 1 /* Event Channel Select bit 1 position. */ -#define IRCOM_EVSEL2_bm (1<<2) /* Event Channel Select bit 2 mask. */ -#define IRCOM_EVSEL2_bp 2 /* Event Channel Select bit 2 position. */ -#define IRCOM_EVSEL3_bm (1<<3) /* Event Channel Select bit 3 mask. */ -#define IRCOM_EVSEL3_bp 3 /* Event Channel Select bit 3 position. */ - - -/* AES - AES Module */ -/* AES.CTRL bit masks and bit positions */ -#define AES_START_bm 0x80 /* Start/Run bit mask. */ -#define AES_START_bp 7 /* Start/Run bit position. */ - -#define AES_AUTO_bm 0x40 /* Auto Start Trigger bit mask. */ -#define AES_AUTO_bp 6 /* Auto Start Trigger bit position. */ - -#define AES_RESET_bm 0x20 /* AES Software Reset bit mask. */ -#define AES_RESET_bp 5 /* AES Software Reset bit position. */ - -#define AES_DECRYPT_bm 0x10 /* Decryption / Direction bit mask. */ -#define AES_DECRYPT_bp 4 /* Decryption / Direction bit position. */ - -#define AES_XOR_bm 0x04 /* State XOR Load Enable bit mask. */ -#define AES_XOR_bp 2 /* State XOR Load Enable bit position. */ - - -/* AES.STATUS bit masks and bit positions */ -#define AES_ERROR_bm 0x80 /* AES Error bit mask. */ -#define AES_ERROR_bp 7 /* AES Error bit position. */ - -#define AES_SRIF_bm 0x01 /* State Ready Interrupt Flag bit mask. */ -#define AES_SRIF_bp 0 /* State Ready Interrupt Flag bit position. */ - - -/* AES.INTCTRL bit masks and bit positions */ -#define AES_INTLVL_gm 0x03 /* Interrupt level group mask. */ -#define AES_INTLVL_gp 0 /* Interrupt level group position. */ -#define AES_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */ -#define AES_INTLVL0_bp 0 /* Interrupt level bit 0 position. */ -#define AES_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */ -#define AES_INTLVL1_bp 1 /* Interrupt level bit 1 position. */ - - - -// Generic Port Pins - -#define PIN0_bm 0x01 -#define PIN0_bp 0 -#define PIN1_bm 0x02 -#define PIN1_bp 1 -#define PIN2_bm 0x04 -#define PIN2_bp 2 -#define PIN3_bm 0x08 -#define PIN3_bp 3 -#define PIN4_bm 0x10 -#define PIN4_bp 4 -#define PIN5_bm 0x20 -#define PIN5_bp 5 -#define PIN6_bm 0x40 -#define PIN6_bp 6 -#define PIN7_bm 0x80 -#define PIN7_bp 7 - - -/* ========== Interrupt Vector Definitions ========== */ -/* Vector 0 is the reset vector */ - -/* OSC interrupt vectors */ -#define OSC_XOSCF_vect_num 1 -#define OSC_XOSCF_vect _VECTOR(1) /* External Oscillator Failure Interrupt (NMI) */ - -/* PORTC interrupt vectors */ -#define PORTC_INT0_vect_num 2 -#define PORTC_INT0_vect _VECTOR(2) /* External Interrupt 0 */ -#define PORTC_INT1_vect_num 3 -#define PORTC_INT1_vect _VECTOR(3) /* External Interrupt 1 */ - -/* PORTR interrupt vectors */ -#define PORTR_INT0_vect_num 4 -#define PORTR_INT0_vect _VECTOR(4) /* External Interrupt 0 */ -#define PORTR_INT1_vect_num 5 -#define PORTR_INT1_vect _VECTOR(5) /* External Interrupt 1 */ - -/* DMA interrupt vectors */ -#define DMA_CH0_vect_num 6 -#define DMA_CH0_vect _VECTOR(6) /* Channel 0 Interrupt */ -#define DMA_CH1_vect_num 7 -#define DMA_CH1_vect _VECTOR(7) /* Channel 1 Interrupt */ -#define DMA_CH2_vect_num 8 -#define DMA_CH2_vect _VECTOR(8) /* Channel 2 Interrupt */ -#define DMA_CH3_vect_num 9 -#define DMA_CH3_vect _VECTOR(9) /* Channel 3 Interrupt */ - -/* RTC interrupt vectors */ -#define RTC_OVF_vect_num 10 -#define RTC_OVF_vect _VECTOR(10) /* Overflow Interrupt */ -#define RTC_COMP_vect_num 11 -#define RTC_COMP_vect _VECTOR(11) /* Compare Interrupt */ - -/* TWIC interrupt vectors */ -#define TWIC_TWIS_vect_num 12 -#define TWIC_TWIS_vect _VECTOR(12) /* TWI Slave Interrupt */ -#define TWIC_TWIM_vect_num 13 -#define TWIC_TWIM_vect _VECTOR(13) /* TWI Master Interrupt */ - -/* TCC0 interrupt vectors */ -#define TCC0_OVF_vect_num 14 -#define TCC0_OVF_vect _VECTOR(14) /* Overflow Interrupt */ -#define TCC0_ERR_vect_num 15 -#define TCC0_ERR_vect _VECTOR(15) /* Error Interrupt */ -#define TCC0_CCA_vect_num 16 -#define TCC0_CCA_vect _VECTOR(16) /* Compare or Capture A Interrupt */ -#define TCC0_CCB_vect_num 17 -#define TCC0_CCB_vect _VECTOR(17) /* Compare or Capture B Interrupt */ -#define TCC0_CCC_vect_num 18 -#define TCC0_CCC_vect _VECTOR(18) /* Compare or Capture C Interrupt */ -#define TCC0_CCD_vect_num 19 -#define TCC0_CCD_vect _VECTOR(19) /* Compare or Capture D Interrupt */ - -/* TCC1 interrupt vectors */ -#define TCC1_OVF_vect_num 20 -#define TCC1_OVF_vect _VECTOR(20) /* Overflow Interrupt */ -#define TCC1_ERR_vect_num 21 -#define TCC1_ERR_vect _VECTOR(21) /* Error Interrupt */ -#define TCC1_CCA_vect_num 22 -#define TCC1_CCA_vect _VECTOR(22) /* Compare or Capture A Interrupt */ -#define TCC1_CCB_vect_num 23 -#define TCC1_CCB_vect _VECTOR(23) /* Compare or Capture B Interrupt */ - -/* SPIC interrupt vectors */ -#define SPIC_INT_vect_num 24 -#define SPIC_INT_vect _VECTOR(24) /* SPI Interrupt */ - -/* USARTC0 interrupt vectors */ -#define USARTC0_RXC_vect_num 25 -#define USARTC0_RXC_vect _VECTOR(25) /* Reception Complete Interrupt */ -#define USARTC0_DRE_vect_num 26 -#define USARTC0_DRE_vect _VECTOR(26) /* Data Register Empty Interrupt */ -#define USARTC0_TXC_vect_num 27 -#define USARTC0_TXC_vect _VECTOR(27) /* Transmission Complete Interrupt */ - -/* USARTC1 interrupt vectors */ -#define USARTC1_RXC_vect_num 28 -#define USARTC1_RXC_vect _VECTOR(28) /* Reception Complete Interrupt */ -#define USARTC1_DRE_vect_num 29 -#define USARTC1_DRE_vect _VECTOR(29) /* Data Register Empty Interrupt */ -#define USARTC1_TXC_vect_num 30 -#define USARTC1_TXC_vect _VECTOR(30) /* Transmission Complete Interrupt */ - -/* AES interrupt vectors */ -#define AES_INT_vect_num 31 -#define AES_INT_vect _VECTOR(31) /* AES Interrupt */ - -/* NVM interrupt vectors */ -#define NVM_EE_vect_num 32 -#define NVM_EE_vect _VECTOR(32) /* EE Interrupt */ -#define NVM_SPM_vect_num 33 -#define NVM_SPM_vect _VECTOR(33) /* SPM Interrupt */ - -/* PORTB interrupt vectors */ -#define PORTB_INT0_vect_num 34 -#define PORTB_INT0_vect _VECTOR(34) /* External Interrupt 0 */ -#define PORTB_INT1_vect_num 35 -#define PORTB_INT1_vect _VECTOR(35) /* External Interrupt 1 */ - -/* PORTE interrupt vectors */ -#define PORTE_INT0_vect_num 43 -#define PORTE_INT0_vect _VECTOR(43) /* External Interrupt 0 */ -#define PORTE_INT1_vect_num 44 -#define PORTE_INT1_vect _VECTOR(44) /* External Interrupt 1 */ - -/* TWIE interrupt vectors */ -#define TWIE_TWIS_vect_num 45 -#define TWIE_TWIS_vect _VECTOR(45) /* TWI Slave Interrupt */ -#define TWIE_TWIM_vect_num 46 -#define TWIE_TWIM_vect _VECTOR(46) /* TWI Master Interrupt */ - -/* TCE0 interrupt vectors */ -#define TCE0_OVF_vect_num 47 -#define TCE0_OVF_vect _VECTOR(47) /* Overflow Interrupt */ -#define TCE0_ERR_vect_num 48 -#define TCE0_ERR_vect _VECTOR(48) /* Error Interrupt */ -#define TCE0_CCA_vect_num 49 -#define TCE0_CCA_vect _VECTOR(49) /* Compare or Capture A Interrupt */ -#define TCE0_CCB_vect_num 50 -#define TCE0_CCB_vect _VECTOR(50) /* Compare or Capture B Interrupt */ -#define TCE0_CCC_vect_num 51 -#define TCE0_CCC_vect _VECTOR(51) /* Compare or Capture C Interrupt */ -#define TCE0_CCD_vect_num 52 -#define TCE0_CCD_vect _VECTOR(52) /* Compare or Capture D Interrupt */ - -/* TCE1 interrupt vectors */ -#define TCE1_OVF_vect_num 53 -#define TCE1_OVF_vect _VECTOR(53) /* Overflow Interrupt */ -#define TCE1_ERR_vect_num 54 -#define TCE1_ERR_vect _VECTOR(54) /* Error Interrupt */ -#define TCE1_CCA_vect_num 55 -#define TCE1_CCA_vect _VECTOR(55) /* Compare or Capture A Interrupt */ -#define TCE1_CCB_vect_num 56 -#define TCE1_CCB_vect _VECTOR(56) /* Compare or Capture B Interrupt */ - -/* USARTE0 interrupt vectors */ -#define USARTE0_RXC_vect_num 58 -#define USARTE0_RXC_vect _VECTOR(58) /* Reception Complete Interrupt */ -#define USARTE0_DRE_vect_num 59 -#define USARTE0_DRE_vect _VECTOR(59) /* Data Register Empty Interrupt */ -#define USARTE0_TXC_vect_num 60 -#define USARTE0_TXC_vect _VECTOR(60) /* Transmission Complete Interrupt */ - -/* PORTD interrupt vectors */ -#define PORTD_INT0_vect_num 64 -#define PORTD_INT0_vect _VECTOR(64) /* External Interrupt 0 */ -#define PORTD_INT1_vect_num 65 -#define PORTD_INT1_vect _VECTOR(65) /* External Interrupt 1 */ - -/* PORTA interrupt vectors */ -#define PORTA_INT0_vect_num 66 -#define PORTA_INT0_vect _VECTOR(66) /* External Interrupt 0 */ -#define PORTA_INT1_vect_num 67 -#define PORTA_INT1_vect _VECTOR(67) /* External Interrupt 1 */ - -/* ACA interrupt vectors */ -#define ACA_AC0_vect_num 68 -#define ACA_AC0_vect _VECTOR(68) /* AC0 Interrupt */ -#define ACA_AC1_vect_num 69 -#define ACA_AC1_vect _VECTOR(69) /* AC1 Interrupt */ -#define ACA_ACW_vect_num 70 -#define ACA_ACW_vect _VECTOR(70) /* ACW Window Mode Interrupt */ - -/* ADCA interrupt vectors */ -#define ADCA_CH0_vect_num 71 -#define ADCA_CH0_vect _VECTOR(71) /* Interrupt 0 */ -#define ADCA_CH1_vect_num 72 -#define ADCA_CH1_vect _VECTOR(72) /* Interrupt 1 */ -#define ADCA_CH2_vect_num 73 -#define ADCA_CH2_vect _VECTOR(73) /* Interrupt 2 */ -#define ADCA_CH3_vect_num 74 -#define ADCA_CH3_vect _VECTOR(74) /* Interrupt 3 */ - -/* TCD0 interrupt vectors */ -#define TCD0_OVF_vect_num 77 -#define TCD0_OVF_vect _VECTOR(77) /* Overflow Interrupt */ -#define TCD0_ERR_vect_num 78 -#define TCD0_ERR_vect _VECTOR(78) /* Error Interrupt */ -#define TCD0_CCA_vect_num 79 -#define TCD0_CCA_vect _VECTOR(79) /* Compare or Capture A Interrupt */ -#define TCD0_CCB_vect_num 80 -#define TCD0_CCB_vect _VECTOR(80) /* Compare or Capture B Interrupt */ -#define TCD0_CCC_vect_num 81 -#define TCD0_CCC_vect _VECTOR(81) /* Compare or Capture C Interrupt */ -#define TCD0_CCD_vect_num 82 -#define TCD0_CCD_vect _VECTOR(82) /* Compare or Capture D Interrupt */ - -/* TCD1 interrupt vectors */ -#define TCD1_OVF_vect_num 83 -#define TCD1_OVF_vect _VECTOR(83) /* Overflow Interrupt */ -#define TCD1_ERR_vect_num 84 -#define TCD1_ERR_vect _VECTOR(84) /* Error Interrupt */ -#define TCD1_CCA_vect_num 85 -#define TCD1_CCA_vect _VECTOR(85) /* Compare or Capture A Interrupt */ -#define TCD1_CCB_vect_num 86 -#define TCD1_CCB_vect _VECTOR(86) /* Compare or Capture B Interrupt */ - -/* SPID interrupt vectors */ -#define SPID_INT_vect_num 87 -#define SPID_INT_vect _VECTOR(87) /* SPI Interrupt */ - -/* USARTD0 interrupt vectors */ -#define USARTD0_RXC_vect_num 88 -#define USARTD0_RXC_vect _VECTOR(88) /* Reception Complete Interrupt */ -#define USARTD0_DRE_vect_num 89 -#define USARTD0_DRE_vect _VECTOR(89) /* Data Register Empty Interrupt */ -#define USARTD0_TXC_vect_num 90 -#define USARTD0_TXC_vect _VECTOR(90) /* Transmission Complete Interrupt */ - -/* USARTD1 interrupt vectors */ -#define USARTD1_RXC_vect_num 91 -#define USARTD1_RXC_vect _VECTOR(91) /* Reception Complete Interrupt */ -#define USARTD1_DRE_vect_num 92 -#define USARTD1_DRE_vect _VECTOR(92) /* Data Register Empty Interrupt */ -#define USARTD1_TXC_vect_num 93 -#define USARTD1_TXC_vect _VECTOR(93) /* Transmission Complete Interrupt */ - - -#define _VECTOR_SIZE 4 /* Size of individual vector. */ -#define _VECTORS_SIZE (94 * _VECTOR_SIZE) - - -/* ========== Constants ========== */ - -#define PROGMEM_START (0x0000) -#define PROGMEM_SIZE (20480) -#define PROGMEM_PAGE_SIZE (256) -#define PROGMEM_END (PROGMEM_START + PROGMEM_SIZE - 1) - -#define APP_SECTION_START (0x0000) -#define APP_SECTION_SIZE (16384) -#define APP_SECTION_PAGE_SIZE (256) -#define APP_SECTION_END (APP_SECTION_START + APP_SECTION_SIZE - 1) - -#define APPTABLE_SECTION_START (0x3000) -#define APPTABLE_SECTION_SIZE (4096) -#define APPTABLE_SECTION_PAGE_SIZE (256) -#define APPTABLE_SECTION_END (APPTABLE_SECTION_START + APPTABLE_SECTION_SIZE - 1) - -#define BOOT_SECTION_START (0x4000) -#define BOOT_SECTION_SIZE (4096) -#define BOOT_SECTION_PAGE_SIZE (256) -#define BOOT_SECTION_END (BOOT_SECTION_START + BOOT_SECTION_SIZE - 1) - -#define DATAMEM_START (0x0000) -#define DATAMEM_SIZE (10240) -#define DATAMEM_PAGE_SIZE (0) -#define DATAMEM_END (DATAMEM_START + DATAMEM_SIZE - 1) - -#define IO_START (0x0000) -#define IO_SIZE (4096) -#define IO_PAGE_SIZE (0) -#define IO_END (IO_START + IO_SIZE - 1) - -#define MAPPED_EEPROM_START (0x1000) -#define MAPPED_EEPROM_SIZE (1024) -#define MAPPED_EEPROM_PAGE_SIZE (0) -#define MAPPED_EEPROM_END (MAPPED_EEPROM_START + MAPPED_EEPROM_SIZE - 1) - -#define INTERNAL_SRAM_START (0x2000) -#define INTERNAL_SRAM_SIZE (2048) -#define INTERNAL_SRAM_PAGE_SIZE (0) -#define INTERNAL_SRAM_END (INTERNAL_SRAM_START + INTERNAL_SRAM_SIZE - 1) - -#define EEPROM_START (0x0000) -#define EEPROM_SIZE (1024) -#define EEPROM_PAGE_SIZE (32) -#define EEPROM_END (EEPROM_START + EEPROM_SIZE - 1) - -#define FUSE_START (0x0000) -#define FUSE_SIZE (6) -#define FUSE_PAGE_SIZE (0) -#define FUSE_END (FUSE_START + FUSE_SIZE - 1) - -#define LOCKBIT_START (0x0000) -#define LOCKBIT_SIZE (1) -#define LOCKBIT_PAGE_SIZE (0) -#define LOCKBIT_END (LOCKBIT_START + LOCKBIT_SIZE - 1) - -#define SIGNATURES_START (0x0000) -#define SIGNATURES_SIZE (3) -#define SIGNATURES_PAGE_SIZE (0) -#define SIGNATURES_END (SIGNATURES_START + SIGNATURES_SIZE - 1) - -#define USER_SIGNATURES_START (0x0000) -#define USER_SIGNATURES_SIZE (256) -#define USER_SIGNATURES_PAGE_SIZE (0) -#define USER_SIGNATURES_END (USER_SIGNATURES_START + USER_SIGNATURES_SIZE - 1) - -#define PROD_SIGNATURES_START (0x0000) -#define PROD_SIGNATURES_SIZE (52) -#define PROD_SIGNATURES_PAGE_SIZE (0) -#define PROD_SIGNATURES_END (PROD_SIGNATURES_START + PROD_SIGNATURES_SIZE - 1) - -#define FLASHEND PROGMEM_END -#define SPM_PAGESIZE PROGMEM_PAGE_SIZE -#define RAMSTART INTERNAL_SRAM_START -#define RAMSIZE INTERNAL_SRAM_SIZE -#define RAMEND INTERNAL_SRAM_END -#define XRAMSTART EXTERNAL_SRAM_START -#define XRAMSIZE EXTERNAL_SRAM_SIZE -#define XRAMEND INTERNAL_SRAM_END -#define E2END EEPROM_END -#define E2PAGESIZE EEPROM_PAGE_SIZE - - -/* ========== Fuses ========== */ -#define FUSE_MEMORY_SIZE 6 - -/* Fuse Byte 0 */ -#define FUSE_USERID0 (unsigned char)~_BV(0) /* User ID Bit 0 */ -#define FUSE_USERID1 (unsigned char)~_BV(1) /* User ID Bit 1 */ -#define FUSE_USERID2 (unsigned char)~_BV(2) /* User ID Bit 2 */ -#define FUSE_USERID3 (unsigned char)~_BV(3) /* User ID Bit 3 */ -#define FUSE_USERID4 (unsigned char)~_BV(4) /* User ID Bit 4 */ -#define FUSE_USERID5 (unsigned char)~_BV(5) /* User ID Bit 5 */ -#define FUSE_USERID6 (unsigned char)~_BV(6) /* User ID Bit 6 */ -#define FUSE_USERID7 (unsigned char)~_BV(7) /* User ID Bit 7 */ -#define FUSE0_DEFAULT (0xFF) - -/* Fuse Byte 1 */ -#define FUSE_WDP0 (unsigned char)~_BV(0) /* Watchdog Timeout Period Bit 0 */ -#define FUSE_WDP1 (unsigned char)~_BV(1) /* Watchdog Timeout Period Bit 1 */ -#define FUSE_WDP2 (unsigned char)~_BV(2) /* Watchdog Timeout Period Bit 2 */ -#define FUSE_WDP3 (unsigned char)~_BV(3) /* Watchdog Timeout Period Bit 3 */ -#define FUSE_WDWP0 (unsigned char)~_BV(4) /* Watchdog Window Timeout Period Bit 0 */ -#define FUSE_WDWP1 (unsigned char)~_BV(5) /* Watchdog Window Timeout Period Bit 1 */ -#define FUSE_WDWP2 (unsigned char)~_BV(6) /* Watchdog Window Timeout Period Bit 2 */ -#define FUSE_WDWP3 (unsigned char)~_BV(7) /* Watchdog Window Timeout Period Bit 3 */ -#define FUSE1_DEFAULT (0xFF) - -/* Fuse Byte 2 */ -#define FUSE_BODPD0 (unsigned char)~_BV(0) /* BOD Operation in Power-Down Mode Bit 0 */ -#define FUSE_BODPD1 (unsigned char)~_BV(1) /* BOD Operation in Power-Down Mode Bit 1 */ -#define FUSE_BOOTRST (unsigned char)~_BV(6) /* Boot Loader Section Reset Vector */ -#define FUSE_DVSDON (unsigned char)~_BV(7) /* Spike Detector Enable */ -#define FUSE2_DEFAULT (0xFF) - -/* Fuse Byte 3 Reserved */ - -/* Fuse Byte 4 */ -#define FUSE_WDLOCK (unsigned char)~_BV(1) /* Watchdog Timer Lock */ -#define FUSE_SUT0 (unsigned char)~_BV(2) /* Start-up Time Bit 0 */ -#define FUSE_SUT1 (unsigned char)~_BV(3) /* Start-up Time Bit 1 */ -#define FUSE4_DEFAULT (0xFF) - -/* Fuse Byte 5 */ -#define FUSE_BODLVL0 (unsigned char)~_BV(0) /* Brown Out Detection Voltage Level Bit 0 */ -#define FUSE_BODLVL1 (unsigned char)~_BV(1) /* Brown Out Detection Voltage Level Bit 1 */ -#define FUSE_BODLVL2 (unsigned char)~_BV(2) /* Brown Out Detection Voltage Level Bit 2 */ -#define FUSE_EESAVE (unsigned char)~_BV(3) /* Preserve EEPROM Through Chip Erase */ -#define FUSE_BODACT0 (unsigned char)~_BV(4) /* BOD Operation in Active Mode Bit 0 */ -#define FUSE_BODACT1 (unsigned char)~_BV(5) /* BOD Operation in Active Mode Bit 1 */ -#define FUSE5_DEFAULT (0xFF) - - -/* ========== Lock Bits ========== */ -#define __LOCK_BITS_EXIST -#define __BOOT_LOCK_APPLICATION_TABLE_BITS_EXIST -#define __BOOT_LOCK_APPLICATION_BITS_EXIST -#define __BOOT_LOCK_BOOT_BITS_EXIST - - -/* ========== Signature ========== */ -#define SIGNATURE_0 0x1E -#define SIGNATURE_1 0x94 -#define SIGNATURE_2 0x41 - -/* ========== Power Reduction Condition Definitions ========== */ - -/* PR.PRGEN */ -#define __AVR_HAVE_PRGEN (PR_AES_bm|PR_EBI_bm|PR_RTC_bm|PR_EVSYS_bm|PR_DMA_bm) -#define __AVR_HAVE_PRGEN_AES -#define __AVR_HAVE_PRGEN_EBI -#define __AVR_HAVE_PRGEN_RTC -#define __AVR_HAVE_PRGEN_EVSYS -#define __AVR_HAVE_PRGEN_DMA - -/* PR.PRPA */ -#define __AVR_HAVE_PRPA (PR_DAC_bm|PR_ADC_bm|PR_AC_bm) -#define __AVR_HAVE_PRPA_DAC -#define __AVR_HAVE_PRPA_ADC -#define __AVR_HAVE_PRPA_AC - -/* PR.PRPB */ -#define __AVR_HAVE_PRPB (PR_DAC_bm|PR_ADC_bm|PR_AC_bm) -#define __AVR_HAVE_PRPB_DAC -#define __AVR_HAVE_PRPB_ADC -#define __AVR_HAVE_PRPB_AC - -/* PR.PRPC */ -#define __AVR_HAVE_PRPC (PR_TWI_bm|PR_USART1_bm|PR_USART0_bm|PR_SPI_bm|PR_HIRES_bm|PR_TC1_bm|PR_TC0_bm) -#define __AVR_HAVE_PRPC_TWI -#define __AVR_HAVE_PRPC_USART1 -#define __AVR_HAVE_PRPC_USART0 -#define __AVR_HAVE_PRPC_SPI -#define __AVR_HAVE_PRPC_HIRES -#define __AVR_HAVE_PRPC_TC1 -#define __AVR_HAVE_PRPC_TC0 - -/* PR.PRPD */ -#define __AVR_HAVE_PRPD (PR_TWI_bm|PR_USART1_bm|PR_USART0_bm|PR_SPI_bm|PR_HIRES_bm|PR_TC1_bm|PR_TC0_bm) -#define __AVR_HAVE_PRPD_TWI -#define __AVR_HAVE_PRPD_USART1 -#define __AVR_HAVE_PRPD_USART0 -#define __AVR_HAVE_PRPD_SPI -#define __AVR_HAVE_PRPD_HIRES -#define __AVR_HAVE_PRPD_TC1 -#define __AVR_HAVE_PRPD_TC0 - -/* PR.PRPE */ -#define __AVR_HAVE_PRPE (PR_TWI_bm|PR_USART1_bm|PR_USART0_bm|PR_SPI_bm|PR_HIRES_bm|PR_TC1_bm|PR_TC0_bm) -#define __AVR_HAVE_PRPE_TWI -#define __AVR_HAVE_PRPE_USART1 -#define __AVR_HAVE_PRPE_USART0 -#define __AVR_HAVE_PRPE_SPI -#define __AVR_HAVE_PRPE_HIRES -#define __AVR_HAVE_PRPE_TC1 -#define __AVR_HAVE_PRPE_TC0 - -/* PR.PRPF */ -#define __AVR_HAVE_PRPF (PR_TWI_bm|PR_USART1_bm|PR_USART0_bm|PR_SPI_bm|PR_HIRES_bm|PR_TC1_bm|PR_TC0_bm) -#define __AVR_HAVE_PRPF_TWI -#define __AVR_HAVE_PRPF_USART1 -#define __AVR_HAVE_PRPF_USART0 -#define __AVR_HAVE_PRPF_SPI -#define __AVR_HAVE_PRPF_HIRES -#define __AVR_HAVE_PRPF_TC1 -#define __AVR_HAVE_PRPF_TC0 - - -#endif /* _AVR_ATxmega16A4_H_ */ - diff --git a/arduino/hardware/tools/avr/avr/include/avr/iox16a4u.h b/arduino/hardware/tools/avr/avr/include/avr/iox16a4u.h deleted file mode 100644 index bf79d55..0000000 --- a/arduino/hardware/tools/avr/avr/include/avr/iox16a4u.h +++ /dev/null @@ -1,7309 +0,0 @@ -/***************************************************************************** - * - * Copyright (C) 2015 Atmel Corporation - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * - * * Neither the name of the copyright holders nor the names of - * contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - ****************************************************************************/ - - -#ifndef _AVR_IO_H_ -# error "Include instead of this file." -#endif - -#ifndef _AVR_IOXXX_H_ -# define _AVR_IOXXX_H_ "iox16a4u.h" -#else -# error "Attempt to include more than one file." -#endif - -#ifndef _AVR_ATXMEGA16A4U_H_INCLUDED -#define _AVR_ATXMEGA16A4U_H_INCLUDED - -/* Ungrouped common registers */ -#define GPIOR0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ -#define GPIOR1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ -#define GPIOR2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ -#define GPIOR3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ -#define GPIOR4 _SFR_MEM8(0x0004) /* General Purpose IO Register 4 */ -#define GPIOR5 _SFR_MEM8(0x0005) /* General Purpose IO Register 5 */ -#define GPIOR6 _SFR_MEM8(0x0006) /* General Purpose IO Register 6 */ -#define GPIOR7 _SFR_MEM8(0x0007) /* General Purpose IO Register 7 */ -#define GPIOR8 _SFR_MEM8(0x0008) /* General Purpose IO Register 8 */ -#define GPIOR9 _SFR_MEM8(0x0009) /* General Purpose IO Register 9 */ -#define GPIORA _SFR_MEM8(0x000A) /* General Purpose IO Register 10 */ -#define GPIORB _SFR_MEM8(0x000B) /* General Purpose IO Register 11 */ -#define GPIORC _SFR_MEM8(0x000C) /* General Purpose IO Register 12 */ -#define GPIORD _SFR_MEM8(0x000D) /* General Purpose IO Register 13 */ -#define GPIORE _SFR_MEM8(0x000E) /* General Purpose IO Register 14 */ -#define GPIORF _SFR_MEM8(0x000F) /* General Purpose IO Register 15 */ - -/* Deprecated */ -#define GPIO0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ -#define GPIO1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ -#define GPIO2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ -#define GPIO3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ -#define GPIO4 _SFR_MEM8(0x0004) /* General Purpose IO Register 4 */ -#define GPIO5 _SFR_MEM8(0x0005) /* General Purpose IO Register 5 */ -#define GPIO6 _SFR_MEM8(0x0006) /* General Purpose IO Register 6 */ -#define GPIO7 _SFR_MEM8(0x0007) /* General Purpose IO Register 7 */ -#define GPIO8 _SFR_MEM8(0x0008) /* General Purpose IO Register 8 */ -#define GPIO9 _SFR_MEM8(0x0009) /* General Purpose IO Register 9 */ -#define GPIOA _SFR_MEM8(0x000A) /* General Purpose IO Register 10 */ -#define GPIOB _SFR_MEM8(0x000B) /* General Purpose IO Register 11 */ -#define GPIOC _SFR_MEM8(0x000C) /* General Purpose IO Register 12 */ -#define GPIOD _SFR_MEM8(0x000D) /* General Purpose IO Register 13 */ -#define GPIOE _SFR_MEM8(0x000E) /* General Purpose IO Register 14 */ -#define GPIOF _SFR_MEM8(0x000F) /* General Purpose IO Register 15 */ - -#define CCP _SFR_MEM8(0x0034) /* Configuration Change Protection */ -#define RAMPD _SFR_MEM8(0x0038) /* Ramp D */ -#define RAMPX _SFR_MEM8(0x0039) /* Ramp X */ -#define RAMPY _SFR_MEM8(0x003A) /* Ramp Y */ -#define RAMPZ _SFR_MEM8(0x003B) /* Ramp Z */ -#define EIND _SFR_MEM8(0x003C) /* Extended Indirect Jump */ -#define SPL _SFR_MEM8(0x003D) /* Stack Pointer Low */ -#define SPH _SFR_MEM8(0x003E) /* Stack Pointer High */ -#define SREG _SFR_MEM8(0x003F) /* Status Register */ - -/* C Language Only */ -#if !defined (__ASSEMBLER__) - -#include - -typedef volatile uint8_t register8_t; -typedef volatile uint16_t register16_t; -typedef volatile uint32_t register32_t; - - -#ifdef _WORDREGISTER -#undef _WORDREGISTER -#endif -#define _WORDREGISTER(regname) \ - __extension__ union \ - { \ - register16_t regname; \ - struct \ - { \ - register8_t regname ## L; \ - register8_t regname ## H; \ - }; \ - } - -#ifdef _DWORDREGISTER -#undef _DWORDREGISTER -#endif -#define _DWORDREGISTER(regname) \ - __extension__ union \ - { \ - register32_t regname; \ - struct \ - { \ - register8_t regname ## 0; \ - register8_t regname ## 1; \ - register8_t regname ## 2; \ - register8_t regname ## 3; \ - }; \ - } - - -/* -========================================================================== -IO Module Structures -========================================================================== -*/ - - -/* --------------------------------------------------------------------------- -VPORT - Virtual Ports --------------------------------------------------------------------------- -*/ - -/* Virtual Port */ -typedef struct VPORT_struct -{ - register8_t DIR; /* I/O Port Data Direction */ - register8_t OUT; /* I/O Port Output */ - register8_t IN; /* I/O Port Input */ - register8_t INTFLAGS; /* Interrupt Flag Register */ -} VPORT_t; - - -/* --------------------------------------------------------------------------- -XOCD - On-Chip Debug System --------------------------------------------------------------------------- -*/ - -/* On-Chip Debug System */ -typedef struct OCD_struct -{ - register8_t OCDR0; /* OCD Register 0 */ - register8_t OCDR1; /* OCD Register 1 */ -} OCD_t; - - -/* --------------------------------------------------------------------------- -CPU - CPU --------------------------------------------------------------------------- -*/ - -/* CCP signatures */ -typedef enum CCP_enum -{ - CCP_SPM_gc = (0x9D<<0), /* SPM Instruction Protection */ - CCP_IOREG_gc = (0xD8<<0), /* IO Register Protection */ -} CCP_t; - - -/* --------------------------------------------------------------------------- -CLK - Clock System --------------------------------------------------------------------------- -*/ - -/* Clock System */ -typedef struct CLK_struct -{ - register8_t CTRL; /* Control Register */ - register8_t PSCTRL; /* Prescaler Control Register */ - register8_t LOCK; /* Lock register */ - register8_t RTCCTRL; /* RTC Control Register */ - register8_t USBCTRL; /* USB Control Register */ -} CLK_t; - - -/* Power Reduction */ -typedef struct PR_struct -{ - register8_t PRGEN; /* General Power Reduction */ - register8_t PRPA; /* Power Reduction Port A */ - register8_t PRPB; /* Power Reduction Port B */ - register8_t PRPC; /* Power Reduction Port C */ - register8_t PRPD; /* Power Reduction Port D */ - register8_t PRPE; /* Power Reduction Port E */ - register8_t PRPF; /* Power Reduction Port F */ -} PR_t; - -/* System Clock Selection */ -typedef enum CLK_SCLKSEL_enum -{ - CLK_SCLKSEL_RC2M_gc = (0x00<<0), /* Internal 2 MHz RC Oscillator */ - CLK_SCLKSEL_RC32M_gc = (0x01<<0), /* Internal 32 MHz RC Oscillator */ - CLK_SCLKSEL_RC32K_gc = (0x02<<0), /* Internal 32.768 kHz RC Oscillator */ - CLK_SCLKSEL_XOSC_gc = (0x03<<0), /* External Crystal Oscillator or Clock */ - CLK_SCLKSEL_PLL_gc = (0x04<<0), /* Phase Locked Loop */ -} CLK_SCLKSEL_t; - -/* Prescaler A Division Factor */ -typedef enum CLK_PSADIV_enum -{ - CLK_PSADIV_1_gc = (0x00<<2), /* Divide by 1 */ - CLK_PSADIV_2_gc = (0x01<<2), /* Divide by 2 */ - CLK_PSADIV_4_gc = (0x03<<2), /* Divide by 4 */ - CLK_PSADIV_8_gc = (0x05<<2), /* Divide by 8 */ - CLK_PSADIV_16_gc = (0x07<<2), /* Divide by 16 */ - CLK_PSADIV_32_gc = (0x09<<2), /* Divide by 32 */ - CLK_PSADIV_64_gc = (0x0B<<2), /* Divide by 64 */ - CLK_PSADIV_128_gc = (0x0D<<2), /* Divide by 128 */ - CLK_PSADIV_256_gc = (0x0F<<2), /* Divide by 256 */ - CLK_PSADIV_512_gc = (0x11<<2), /* Divide by 512 */ -} CLK_PSADIV_t; - -/* Prescaler B and C Division Factor */ -typedef enum CLK_PSBCDIV_enum -{ - CLK_PSBCDIV_1_1_gc = (0x00<<0), /* Divide B by 1 and C by 1 */ - CLK_PSBCDIV_1_2_gc = (0x01<<0), /* Divide B by 1 and C by 2 */ - CLK_PSBCDIV_4_1_gc = (0x02<<0), /* Divide B by 4 and C by 1 */ - CLK_PSBCDIV_2_2_gc = (0x03<<0), /* Divide B by 2 and C by 2 */ -} CLK_PSBCDIV_t; - -/* RTC Clock Source */ -typedef enum CLK_RTCSRC_enum -{ - CLK_RTCSRC_ULP_gc = (0x00<<1), /* 1.024 kHz from internal 32kHz ULP */ - CLK_RTCSRC_TOSC_gc = (0x01<<1), /* 1.024 kHz from 32.768 kHz crystal oscillator on TOSC */ - CLK_RTCSRC_RCOSC_gc = (0x02<<1), /* 1.024 kHz from internal 32.768 kHz RC oscillator */ - CLK_RTCSRC_TOSC32_gc = (0x05<<1), /* 32.768 kHz from 32.768 kHz crystal oscillator on TOSC */ - CLK_RTCSRC_RCOSC32_gc = (0x06<<1), /* 32.768 kHz from internal 32.768 kHz RC oscillator */ - CLK_RTCSRC_EXTCLK_gc = (0x07<<1), /* External Clock from TOSC1 */ -} CLK_RTCSRC_t; - -/* USB Prescaler Division Factor */ -typedef enum CLK_USBPSDIV_enum -{ - CLK_USBPSDIV_1_gc = (0x00<<3), /* Divide by 1 */ - CLK_USBPSDIV_2_gc = (0x01<<3), /* Divide by 2 */ - CLK_USBPSDIV_4_gc = (0x02<<3), /* Divide by 4 */ - CLK_USBPSDIV_8_gc = (0x03<<3), /* Divide by 8 */ - CLK_USBPSDIV_16_gc = (0x04<<3), /* Divide by 16 */ - CLK_USBPSDIV_32_gc = (0x05<<3), /* Divide by 32 */ -} CLK_USBPSDIV_t; - -/* USB Clock Source */ -typedef enum CLK_USBSRC_enum -{ - CLK_USBSRC_PLL_gc = (0x00<<1), /* PLL */ - CLK_USBSRC_RC32M_gc = (0x01<<1), /* Internal 32 MHz RC Oscillator */ -} CLK_USBSRC_t; - - -/* --------------------------------------------------------------------------- -SLEEP - Sleep Controller --------------------------------------------------------------------------- -*/ - -/* Sleep Controller */ -typedef struct SLEEP_struct -{ - register8_t CTRL; /* Control Register */ -} SLEEP_t; - -/* Sleep Mode */ -typedef enum SLEEP_SMODE_enum -{ - SLEEP_SMODE_IDLE_gc = (0x00<<1), /* Idle mode */ - SLEEP_SMODE_PDOWN_gc = (0x02<<1), /* Power-down Mode */ - SLEEP_SMODE_PSAVE_gc = (0x03<<1), /* Power-save Mode */ - SLEEP_SMODE_STDBY_gc = (0x06<<1), /* Standby Mode */ - SLEEP_SMODE_ESTDBY_gc = (0x07<<1), /* Extended Standby Mode */ -} SLEEP_SMODE_t; - - - -#define SLEEP_MODE_IDLE (0x00<<1) -#define SLEEP_MODE_PWR_DOWN (0x02<<1) -#define SLEEP_MODE_PWR_SAVE (0x03<<1) -#define SLEEP_MODE_STANDBY (0x06<<1) -#define SLEEP_MODE_EXT_STANDBY (0x07<<1) -/* --------------------------------------------------------------------------- -OSC - Oscillator --------------------------------------------------------------------------- -*/ - -/* Oscillator */ -typedef struct OSC_struct -{ - register8_t CTRL; /* Control Register */ - register8_t STATUS; /* Status Register */ - register8_t XOSCCTRL; /* External Oscillator Control Register */ - register8_t XOSCFAIL; /* Oscillator Failure Detection Register */ - register8_t RC32KCAL; /* 32.768 kHz Internal Oscillator Calibration Register */ - register8_t PLLCTRL; /* PLL Control Register */ - register8_t DFLLCTRL; /* DFLL Control Register */ -} OSC_t; - -/* Oscillator Frequency Range */ -typedef enum OSC_FRQRANGE_enum -{ - OSC_FRQRANGE_04TO2_gc = (0x00<<6), /* 0.4 - 2 MHz */ - OSC_FRQRANGE_2TO9_gc = (0x01<<6), /* 2 - 9 MHz */ - OSC_FRQRANGE_9TO12_gc = (0x02<<6), /* 9 - 12 MHz */ - OSC_FRQRANGE_12TO16_gc = (0x03<<6), /* 12 - 16 MHz */ -} OSC_FRQRANGE_t; - -/* External Oscillator Selection and Startup Time */ -typedef enum OSC_XOSCSEL_enum -{ - OSC_XOSCSEL_EXTCLK_gc = (0x00<<0), /* External Clock - 6 CLK */ - OSC_XOSCSEL_32KHz_gc = (0x02<<0), /* 32.768 kHz TOSC - 32K CLK */ - OSC_XOSCSEL_XTAL_256CLK_gc = (0x03<<0), /* 0.4-16 MHz XTAL - 256 CLK */ - OSC_XOSCSEL_XTAL_1KCLK_gc = (0x07<<0), /* 0.4-16 MHz XTAL - 1K CLK */ - OSC_XOSCSEL_XTAL_16KCLK_gc = (0x0B<<0), /* 0.4-16 MHz XTAL - 16K CLK */ -} OSC_XOSCSEL_t; - -/* PLL Clock Source */ -typedef enum OSC_PLLSRC_enum -{ - OSC_PLLSRC_RC2M_gc = (0x00<<6), /* Internal 2 MHz RC Oscillator */ - OSC_PLLSRC_RC32M_gc = (0x02<<6), /* Internal 32 MHz RC Oscillator */ - OSC_PLLSRC_XOSC_gc = (0x03<<6), /* External Oscillator */ -} OSC_PLLSRC_t; - -/* 2 MHz DFLL Calibration Reference */ -typedef enum OSC_RC2MCREF_enum -{ - OSC_RC2MCREF_RC32K_gc = (0x00<<0), /* Internal 32.768 kHz RC Oscillator */ - OSC_RC2MCREF_XOSC32K_gc = (0x01<<0), /* External 32.768 kHz Crystal Oscillator */ -} OSC_RC2MCREF_t; - -/* 32 MHz DFLL Calibration Reference */ -typedef enum OSC_RC32MCREF_enum -{ - OSC_RC32MCREF_RC32K_gc = (0x00<<1), /* Internal 32.768 kHz RC Oscillator */ - OSC_RC32MCREF_XOSC32K_gc = (0x01<<1), /* External 32.768 kHz Crystal Oscillator */ - OSC_RC32MCREF_USBSOF_gc = (0x02<<1), /* USB Start of Frame */ -} OSC_RC32MCREF_t; - - -/* --------------------------------------------------------------------------- -DFLL - DFLL --------------------------------------------------------------------------- -*/ - -/* DFLL */ -typedef struct DFLL_struct -{ - register8_t CTRL; /* Control Register */ - register8_t reserved_0x01; - register8_t CALA; /* Calibration Register A */ - register8_t CALB; /* Calibration Register B */ - register8_t COMP0; /* Oscillator Compare Register 0 */ - register8_t COMP1; /* Oscillator Compare Register 1 */ - register8_t COMP2; /* Oscillator Compare Register 2 */ - register8_t reserved_0x07; -} DFLL_t; - - -/* --------------------------------------------------------------------------- -RST - Reset --------------------------------------------------------------------------- -*/ - -/* Reset */ -typedef struct RST_struct -{ - register8_t STATUS; /* Status Register */ - register8_t CTRL; /* Control Register */ -} RST_t; - - -/* --------------------------------------------------------------------------- -WDT - Watch-Dog Timer --------------------------------------------------------------------------- -*/ - -/* Watch-Dog Timer */ -typedef struct WDT_struct -{ - register8_t CTRL; /* Control */ - register8_t WINCTRL; /* Windowed Mode Control */ - register8_t STATUS; /* Status */ -} WDT_t; - -/* Period setting */ -typedef enum WDT_PER_enum -{ - WDT_PER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ - WDT_PER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ - WDT_PER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ - WDT_PER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ - WDT_PER_128CLK_gc = (0x04<<2), /* 128 cycles (0.128s @ 3.3V) */ - WDT_PER_256CLK_gc = (0x05<<2), /* 256 cycles (0.256s @ 3.3V) */ - WDT_PER_512CLK_gc = (0x06<<2), /* 512 cycles (0.512s @ 3.3V) */ - WDT_PER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ - WDT_PER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ - WDT_PER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ - WDT_PER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ -} WDT_PER_t; - -/* Closed window period */ -typedef enum WDT_WPER_enum -{ - WDT_WPER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ - WDT_WPER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ - WDT_WPER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ - WDT_WPER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ - WDT_WPER_128CLK_gc = (0x04<<2), /* 128 cycles (0.128s @ 3.3V) */ - WDT_WPER_256CLK_gc = (0x05<<2), /* 256 cycles (0.256s @ 3.3V) */ - WDT_WPER_512CLK_gc = (0x06<<2), /* 512 cycles (0.512s @ 3.3V) */ - WDT_WPER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ - WDT_WPER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ - WDT_WPER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ - WDT_WPER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ -} WDT_WPER_t; - - -/* --------------------------------------------------------------------------- -MCU - MCU Control --------------------------------------------------------------------------- -*/ - -/* MCU Control */ -typedef struct MCU_struct -{ - register8_t DEVID0; /* Device ID byte 0 */ - register8_t DEVID1; /* Device ID byte 1 */ - register8_t DEVID2; /* Device ID byte 2 */ - register8_t REVID; /* Revision ID */ - register8_t JTAGUID; /* JTAG User ID */ - register8_t reserved_0x05; - register8_t MCUCR; /* MCU Control */ - register8_t ANAINIT; /* Analog Startup Delay */ - register8_t EVSYSLOCK; /* Event System Lock */ - register8_t AWEXLOCK; /* AWEX Lock */ - register8_t reserved_0x0A; - register8_t reserved_0x0B; -} MCU_t; - - -/* --------------------------------------------------------------------------- -PMIC - Programmable Multi-level Interrupt Controller --------------------------------------------------------------------------- -*/ - -/* Programmable Multi-level Interrupt Controller */ -typedef struct PMIC_struct -{ - register8_t STATUS; /* Status Register */ - register8_t INTPRI; /* Interrupt Priority */ - register8_t CTRL; /* Control Register */ - register8_t reserved_0x03; - register8_t reserved_0x04; - register8_t reserved_0x05; - register8_t reserved_0x06; - register8_t reserved_0x07; - register8_t reserved_0x08; - register8_t reserved_0x09; - register8_t reserved_0x0A; - register8_t reserved_0x0B; - register8_t reserved_0x0C; - register8_t reserved_0x0D; - register8_t reserved_0x0E; - register8_t reserved_0x0F; -} PMIC_t; - - -/* --------------------------------------------------------------------------- -PORTCFG - Port Configuration --------------------------------------------------------------------------- -*/ - -/* I/O port Configuration */ -typedef struct PORTCFG_struct -{ - register8_t MPCMASK; /* Multi-pin Configuration Mask */ - register8_t reserved_0x01; - register8_t VPCTRLA; /* Virtual Port Control Register A */ - register8_t VPCTRLB; /* Virtual Port Control Register B */ - register8_t CLKEVOUT; /* Clock and Event Out Register */ - register8_t EBIOUT; /* EBI Output register */ - register8_t EVOUTSEL; /* Event Output Select */ -} PORTCFG_t; - -/* Virtual Port Mapping */ -typedef enum PORTCFG_VP02MAP_enum -{ - PORTCFG_VP02MAP_PORTA_gc = (0x00<<0), /* Mapped To PORTA */ - PORTCFG_VP02MAP_PORTB_gc = (0x01<<0), /* Mapped To PORTB */ - PORTCFG_VP02MAP_PORTC_gc = (0x02<<0), /* Mapped To PORTC */ - PORTCFG_VP02MAP_PORTD_gc = (0x03<<0), /* Mapped To PORTD */ - PORTCFG_VP02MAP_PORTE_gc = (0x04<<0), /* Mapped To PORTE */ - PORTCFG_VP02MAP_PORTF_gc = (0x05<<0), /* Mapped To PORTF */ - PORTCFG_VP02MAP_PORTG_gc = (0x06<<0), /* Mapped To PORTG */ - PORTCFG_VP02MAP_PORTH_gc = (0x07<<0), /* Mapped To PORTH */ - PORTCFG_VP02MAP_PORTJ_gc = (0x08<<0), /* Mapped To PORTJ */ - PORTCFG_VP02MAP_PORTK_gc = (0x09<<0), /* Mapped To PORTK */ - PORTCFG_VP02MAP_PORTL_gc = (0x0A<<0), /* Mapped To PORTL */ - PORTCFG_VP02MAP_PORTM_gc = (0x0B<<0), /* Mapped To PORTM */ - PORTCFG_VP02MAP_PORTN_gc = (0x0C<<0), /* Mapped To PORTN */ - PORTCFG_VP02MAP_PORTP_gc = (0x0D<<0), /* Mapped To PORTP */ - PORTCFG_VP02MAP_PORTQ_gc = (0x0E<<0), /* Mapped To PORTQ */ - PORTCFG_VP02MAP_PORTR_gc = (0x0F<<0), /* Mapped To PORTR */ -} PORTCFG_VP02MAP_t; - -/* Virtual Port Mapping */ -typedef enum PORTCFG_VP13MAP_enum -{ - PORTCFG_VP13MAP_PORTA_gc = (0x00<<4), /* Mapped To PORTA */ - PORTCFG_VP13MAP_PORTB_gc = (0x01<<4), /* Mapped To PORTB */ - PORTCFG_VP13MAP_PORTC_gc = (0x02<<4), /* Mapped To PORTC */ - PORTCFG_VP13MAP_PORTD_gc = (0x03<<4), /* Mapped To PORTD */ - PORTCFG_VP13MAP_PORTE_gc = (0x04<<4), /* Mapped To PORTE */ - PORTCFG_VP13MAP_PORTF_gc = (0x05<<4), /* Mapped To PORTF */ - PORTCFG_VP13MAP_PORTG_gc = (0x06<<4), /* Mapped To PORTG */ - PORTCFG_VP13MAP_PORTH_gc = (0x07<<4), /* Mapped To PORTH */ - PORTCFG_VP13MAP_PORTJ_gc = (0x08<<4), /* Mapped To PORTJ */ - PORTCFG_VP13MAP_PORTK_gc = (0x09<<4), /* Mapped To PORTK */ - PORTCFG_VP13MAP_PORTL_gc = (0x0A<<4), /* Mapped To PORTL */ - PORTCFG_VP13MAP_PORTM_gc = (0x0B<<4), /* Mapped To PORTM */ - PORTCFG_VP13MAP_PORTN_gc = (0x0C<<4), /* Mapped To PORTN */ - PORTCFG_VP13MAP_PORTP_gc = (0x0D<<4), /* Mapped To PORTP */ - PORTCFG_VP13MAP_PORTQ_gc = (0x0E<<4), /* Mapped To PORTQ */ - PORTCFG_VP13MAP_PORTR_gc = (0x0F<<4), /* Mapped To PORTR */ -} PORTCFG_VP13MAP_t; - -/* System Clock Output Port */ -typedef enum PORTCFG_CLKOUT_enum -{ - PORTCFG_CLKOUT_OFF_gc = (0x00<<0), /* System Clock Output Disabled */ - PORTCFG_CLKOUT_PC7_gc = (0x01<<0), /* System Clock Output on Port C pin 7 */ - PORTCFG_CLKOUT_PD7_gc = (0x02<<0), /* System Clock Output on Port D pin 7 */ - PORTCFG_CLKOUT_PE7_gc = (0x03<<0), /* System Clock Output on Port E pin 7 */ -} PORTCFG_CLKOUT_t; - -/* Peripheral Clock Output Select */ -typedef enum PORTCFG_CLKOUTSEL_enum -{ - PORTCFG_CLKOUTSEL_CLK1X_gc = (0x00<<2), /* 1x Peripheral Clock Output to pin */ - PORTCFG_CLKOUTSEL_CLK2X_gc = (0x01<<2), /* 2x Peripheral Clock Output to pin */ - PORTCFG_CLKOUTSEL_CLK4X_gc = (0x02<<2), /* 4x Peripheral Clock Output to pin */ -} PORTCFG_CLKOUTSEL_t; - -/* Event Output Port */ -typedef enum PORTCFG_EVOUT_enum -{ - PORTCFG_EVOUT_OFF_gc = (0x00<<4), /* Event Output Disabled */ - PORTCFG_EVOUT_PC7_gc = (0x01<<4), /* Event Channel 7 Output on Port C pin 7 */ - PORTCFG_EVOUT_PD7_gc = (0x02<<4), /* Event Channel 7 Output on Port D pin 7 */ - PORTCFG_EVOUT_PE7_gc = (0x03<<4), /* Event Channel 7 Output on Port E pin 7 */ -} PORTCFG_EVOUT_t; - -/* Clock and Event Output Port */ -typedef enum PORTCFG_CLKEVPIN_enum -{ - PORTCFG_CLKEVPIN_PIN7_gc = (0x00<<7), /* Clock and Event Ouput on PIN 7 */ - PORTCFG_CLKEVPIN_PIN4_gc = (0x01<<7), /* Clock and Event Ouput on PIN 4 */ -} PORTCFG_CLKEVPIN_t; - -/* EBI Address Output Port */ -typedef enum PORTCFG_EBIADROUT_enum -{ - PORTCFG_EBIADROUT_PF_gc = (0x00<<2), /* EBI port 3 address output on PORTF pins 0 to 7 */ - PORTCFG_EBIADROUT_PE_gc = (0x01<<2), /* EBI port 3 address output on PORTE pins 0 to 7 */ - PORTCFG_EBIADROUT_PFH_gc = (0x02<<2), /* EBI port 3 address output on PORTF pins 4 to 7 */ - PORTCFG_EBIADROUT_PEH_gc = (0x03<<2), /* EBI port 3 address output on PORTE pins 4 to 7 */ -} PORTCFG_EBIADROUT_t; - -/* EBI Chip Select Output Port */ -typedef enum PORTCFG_EBICSOUT_enum -{ - PORTCFG_EBICSOUT_PH_gc = (0x00<<0), /* EBI chip select output to PORTH pin 4 to 7 */ - PORTCFG_EBICSOUT_PL_gc = (0x01<<0), /* EBI chip select output to PORTL pin 4 to 7 */ - PORTCFG_EBICSOUT_PF_gc = (0x02<<0), /* EBI chip select output to PORTF pin 4 to 7 */ - PORTCFG_EBICSOUT_PE_gc = (0x03<<0), /* EBI chip select output to PORTE pin 4 to 7 */ -} PORTCFG_EBICSOUT_t; - -/* Event Output Select */ -typedef enum PORTCFG_EVOUTSEL_enum -{ - PORTCFG_EVOUTSEL_0_gc = (0x00<<0), /* Event Channel 0 output to pin */ - PORTCFG_EVOUTSEL_1_gc = (0x01<<0), /* Event Channel 1 output to pin */ - PORTCFG_EVOUTSEL_2_gc = (0x02<<0), /* Event Channel 2 output to pin */ - PORTCFG_EVOUTSEL_3_gc = (0x03<<0), /* Event Channel 3 output to pin */ - PORTCFG_EVOUTSEL_4_gc = (0x04<<0), /* Event Channel 4 output to pin */ - PORTCFG_EVOUTSEL_5_gc = (0x05<<0), /* Event Channel 5 output to pin */ - PORTCFG_EVOUTSEL_6_gc = (0x06<<0), /* Event Channel 6 output to pin */ - PORTCFG_EVOUTSEL_7_gc = (0x07<<0), /* Event Channel 7 output to pin */ -} PORTCFG_EVOUTSEL_t; - - -/* --------------------------------------------------------------------------- -AES - AES Module --------------------------------------------------------------------------- -*/ - -/* AES Module */ -typedef struct AES_struct -{ - register8_t CTRL; /* AES Control Register */ - register8_t STATUS; /* AES Status Register */ - register8_t STATE; /* AES State Register */ - register8_t KEY; /* AES Key Register */ - register8_t INTCTRL; /* AES Interrupt Control Register */ -} AES_t; - -/* Interrupt level */ -typedef enum AES_INTLVL_enum -{ - AES_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - AES_INTLVL_LO_gc = (0x01<<0), /* Low Level */ - AES_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ - AES_INTLVL_HI_gc = (0x03<<0), /* High Level */ -} AES_INTLVL_t; - - -/* --------------------------------------------------------------------------- -CRC - Cyclic Redundancy Checker --------------------------------------------------------------------------- -*/ - -/* Cyclic Redundancy Checker */ -typedef struct CRC_struct -{ - register8_t CTRL; /* Control Register */ - register8_t STATUS; /* Status Register */ - register8_t reserved_0x02; - register8_t DATAIN; /* Data Input */ - register8_t CHECKSUM0; /* Checksum byte 0 */ - register8_t CHECKSUM1; /* Checksum byte 1 */ - register8_t CHECKSUM2; /* Checksum byte 2 */ - register8_t CHECKSUM3; /* Checksum byte 3 */ -} CRC_t; - -/* Reset */ -typedef enum CRC_RESET_enum -{ - CRC_RESET_NO_gc = (0x00<<6), /* No Reset */ - CRC_RESET_RESET0_gc = (0x02<<6), /* Reset CRC with CHECKSUM to all zeros */ - CRC_RESET_RESET1_gc = (0x03<<6), /* Reset CRC with CHECKSUM to all ones */ -} CRC_RESET_t; - -/* Input Source */ -typedef enum CRC_SOURCE_enum -{ - CRC_SOURCE_DISABLE_gc = (0x00<<0), /* Disabled */ - CRC_SOURCE_IO_gc = (0x01<<0), /* I/O Interface */ - CRC_SOURCE_FLASH_gc = (0x02<<0), /* Flash */ - CRC_SOURCE_DMAC0_gc = (0x04<<0), /* DMAC Channel 0 */ - CRC_SOURCE_DMAC1_gc = (0x05<<0), /* DMAC Channel 1 */ - CRC_SOURCE_DMAC2_gc = (0x06<<0), /* DMAC Channel 2 */ - CRC_SOURCE_DMAC3_gc = (0x07<<0), /* DMAC Channel 3 */ -} CRC_SOURCE_t; - - -/* --------------------------------------------------------------------------- -DMA - DMA Controller --------------------------------------------------------------------------- -*/ - -/* DMA Channel */ -typedef struct DMA_CH_struct -{ - register8_t CTRLA; /* Channel Control */ - register8_t CTRLB; /* Channel Control */ - register8_t ADDRCTRL; /* Address Control */ - register8_t TRIGSRC; /* Channel Trigger Source */ - _WORDREGISTER(TRFCNT); /* Channel Block Transfer Count */ - register8_t REPCNT; /* Channel Repeat Count */ - register8_t reserved_0x07; - register8_t SRCADDR0; /* Channel Source Address 0 */ - register8_t SRCADDR1; /* Channel Source Address 1 */ - register8_t SRCADDR2; /* Channel Source Address 2 */ - register8_t reserved_0x0B; - register8_t DESTADDR0; /* Channel Destination Address 0 */ - register8_t DESTADDR1; /* Channel Destination Address 1 */ - register8_t DESTADDR2; /* Channel Destination Address 2 */ - register8_t reserved_0x0F; -} DMA_CH_t; - - -/* DMA Controller */ -typedef struct DMA_struct -{ - register8_t CTRL; /* Control */ - register8_t reserved_0x01; - register8_t reserved_0x02; - register8_t INTFLAGS; /* Transfer Interrupt Status */ - register8_t STATUS; /* Status */ - register8_t reserved_0x05; - _WORDREGISTER(TEMP); /* Temporary Register For 16/24-bit Access */ - register8_t reserved_0x08; - register8_t reserved_0x09; - register8_t reserved_0x0A; - register8_t reserved_0x0B; - register8_t reserved_0x0C; - register8_t reserved_0x0D; - register8_t reserved_0x0E; - register8_t reserved_0x0F; - DMA_CH_t CH0; /* DMA Channel 0 */ - DMA_CH_t CH1; /* DMA Channel 1 */ - DMA_CH_t CH2; /* DMA Channel 2 */ - DMA_CH_t CH3; /* DMA Channel 3 */ -} DMA_t; - -/* Burst mode */ -typedef enum DMA_CH_BURSTLEN_enum -{ - DMA_CH_BURSTLEN_1BYTE_gc = (0x00<<0), /* 1-byte burst mode */ - DMA_CH_BURSTLEN_2BYTE_gc = (0x01<<0), /* 2-byte burst mode */ - DMA_CH_BURSTLEN_4BYTE_gc = (0x02<<0), /* 4-byte burst mode */ - DMA_CH_BURSTLEN_8BYTE_gc = (0x03<<0), /* 8-byte burst mode */ -} DMA_CH_BURSTLEN_t; - -/* Source address reload mode */ -typedef enum DMA_CH_SRCRELOAD_enum -{ - DMA_CH_SRCRELOAD_NONE_gc = (0x00<<6), /* No reload */ - DMA_CH_SRCRELOAD_BLOCK_gc = (0x01<<6), /* Reload at end of block */ - DMA_CH_SRCRELOAD_BURST_gc = (0x02<<6), /* Reload at end of burst */ - DMA_CH_SRCRELOAD_TRANSACTION_gc = (0x03<<6), /* Reload at end of transaction */ -} DMA_CH_SRCRELOAD_t; - -/* Source addressing mode */ -typedef enum DMA_CH_SRCDIR_enum -{ - DMA_CH_SRCDIR_FIXED_gc = (0x00<<4), /* Fixed */ - DMA_CH_SRCDIR_INC_gc = (0x01<<4), /* Increment */ - DMA_CH_SRCDIR_DEC_gc = (0x02<<4), /* Decrement */ -} DMA_CH_SRCDIR_t; - -/* Destination adress reload mode */ -typedef enum DMA_CH_DESTRELOAD_enum -{ - DMA_CH_DESTRELOAD_NONE_gc = (0x00<<2), /* No reload */ - DMA_CH_DESTRELOAD_BLOCK_gc = (0x01<<2), /* Reload at end of block */ - DMA_CH_DESTRELOAD_BURST_gc = (0x02<<2), /* Reload at end of burst */ - DMA_CH_DESTRELOAD_TRANSACTION_gc = (0x03<<2), /* Reload at end of transaction */ -} DMA_CH_DESTRELOAD_t; - -/* Destination adressing mode */ -typedef enum DMA_CH_DESTDIR_enum -{ - DMA_CH_DESTDIR_FIXED_gc = (0x00<<0), /* Fixed */ - DMA_CH_DESTDIR_INC_gc = (0x01<<0), /* Increment */ - DMA_CH_DESTDIR_DEC_gc = (0x02<<0), /* Decrement */ -} DMA_CH_DESTDIR_t; - -/* Transfer trigger source */ -typedef enum DMA_CH_TRIGSRC_enum -{ - DMA_CH_TRIGSRC_OFF_gc = (0x00<<0), /* Off software triggers only */ - DMA_CH_TRIGSRC_EVSYS_CH0_gc = (0x01<<0), /* Event System Channel 0 */ - DMA_CH_TRIGSRC_EVSYS_CH1_gc = (0x02<<0), /* Event System Channel 1 */ - DMA_CH_TRIGSRC_EVSYS_CH2_gc = (0x03<<0), /* Event System Channel 2 */ - DMA_CH_TRIGSRC_ADCA_CH0_gc = (0x10<<0), /* ADCA Channel 0 */ - DMA_CH_TRIGSRC_ADCA_CH1_gc = (0x11<<0), /* ADCA Channel 1 */ - DMA_CH_TRIGSRC_ADCA_CH2_gc = (0x12<<0), /* ADCA Channel 2 */ - DMA_CH_TRIGSRC_ADCA_CH3_gc = (0x13<<0), /* ADCA Channel 3 */ - DMA_CH_TRIGSRC_ADCA_CH4_gc = (0x14<<0), /* ADCA Channel 0,1,2,3 combined */ - DMA_CH_TRIGSRC_DACA_CH0_gc = (0x15<<0), /* DACA Channel 0 */ - DMA_CH_TRIGSRC_DACA_CH1_gc = (0x16<<0), /* DACA Channel 1 */ - DMA_CH_TRIGSRC_ADCB_CH0_gc = (0x20<<0), /* ADCB Channel 0 */ - DMA_CH_TRIGSRC_ADCB_CH1_gc = (0x21<<0), /* ADCB Channel 1 */ - DMA_CH_TRIGSRC_ADCB_CH2_gc = (0x22<<0), /* ADCB Channel 2 */ - DMA_CH_TRIGSRC_ADCB_CH3_gc = (0x23<<0), /* ADCB Channel 3 */ - DMA_CH_TRIGSRC_ADCB_CH4_gc = (0x24<<0), /* ADCB Channel 0,1,2,3 combined */ - DMA_CH_TRIGSRC_DACB_CH0_gc = (0x25<<0), /* DACB Channel 0 */ - DMA_CH_TRIGSRC_DACB_CH1_gc = (0x26<<0), /* DACB Channel 1 */ - DMA_CH_TRIGSRC_TCC0_OVF_gc = (0x40<<0), /* Timer/Counter C0 Overflow */ - DMA_CH_TRIGSRC_TCC0_ERR_gc = (0x41<<0), /* Timer/Counter C0 Error */ - DMA_CH_TRIGSRC_TCC0_CCA_gc = (0x42<<0), /* Timer/Counter C0 Compare or Capture A */ - DMA_CH_TRIGSRC_TCC0_CCB_gc = (0x43<<0), /* Timer/Counter C0 Compare or Capture B */ - DMA_CH_TRIGSRC_TCC0_CCC_gc = (0x44<<0), /* Timer/Counter C0 Compare or Capture C */ - DMA_CH_TRIGSRC_TCC0_CCD_gc = (0x45<<0), /* Timer/Counter C0 Compare or Capture D */ - DMA_CH_TRIGSRC_TCC1_OVF_gc = (0x46<<0), /* Timer/Counter C1 Overflow */ - DMA_CH_TRIGSRC_TCC1_ERR_gc = (0x47<<0), /* Timer/Counter C1 Error */ - DMA_CH_TRIGSRC_TCC1_CCA_gc = (0x48<<0), /* Timer/Counter C1 Compare or Capture A */ - DMA_CH_TRIGSRC_TCC1_CCB_gc = (0x49<<0), /* Timer/Counter C1 Compare or Capture B */ - DMA_CH_TRIGSRC_SPIC_gc = (0x4A<<0), /* SPI C Transfer Complete */ - DMA_CH_TRIGSRC_USARTC0_RXC_gc = (0x4B<<0), /* USART C0 Receive Complete */ - DMA_CH_TRIGSRC_USARTC0_DRE_gc = (0x4C<<0), /* USART C0 Data Register Empty */ - DMA_CH_TRIGSRC_USARTC1_RXC_gc = (0x4E<<0), /* USART C1 Receive Complete */ - DMA_CH_TRIGSRC_USARTC1_DRE_gc = (0x4F<<0), /* USART C1 Data Register Empty */ - DMA_CH_TRIGSRC_TCD0_OVF_gc = (0x60<<0), /* Timer/Counter D0 Overflow */ - DMA_CH_TRIGSRC_TCD0_ERR_gc = (0x61<<0), /* Timer/Counter D0 Error */ - DMA_CH_TRIGSRC_TCD0_CCA_gc = (0x62<<0), /* Timer/Counter D0 Compare or Capture A */ - DMA_CH_TRIGSRC_TCD0_CCB_gc = (0x63<<0), /* Timer/Counter D0 Compare or Capture B */ - DMA_CH_TRIGSRC_TCD0_CCC_gc = (0x64<<0), /* Timer/Counter D0 Compare or Capture C */ - DMA_CH_TRIGSRC_TCD0_CCD_gc = (0x65<<0), /* Timer/Counter D0 Compare or Capture D */ - DMA_CH_TRIGSRC_TCD1_OVF_gc = (0x66<<0), /* Timer/Counter D1 Overflow */ - DMA_CH_TRIGSRC_TCD1_ERR_gc = (0x67<<0), /* Timer/Counter D1 Error */ - DMA_CH_TRIGSRC_TCD1_CCA_gc = (0x68<<0), /* Timer/Counter D1 Compare or Capture A */ - DMA_CH_TRIGSRC_TCD1_CCB_gc = (0x69<<0), /* Timer/Counter D1 Compare or Capture B */ - DMA_CH_TRIGSRC_SPID_gc = (0x6A<<0), /* SPI D Transfer Complete */ - DMA_CH_TRIGSRC_USARTD0_RXC_gc = (0x6B<<0), /* USART D0 Receive Complete */ - DMA_CH_TRIGSRC_USARTD0_DRE_gc = (0x6C<<0), /* USART D0 Data Register Empty */ - DMA_CH_TRIGSRC_USARTD1_RXC_gc = (0x6E<<0), /* USART D1 Receive Complete */ - DMA_CH_TRIGSRC_USARTD1_DRE_gc = (0x6F<<0), /* USART D1 Data Register Empty */ - DMA_CH_TRIGSRC_TCE0_OVF_gc = (0x80<<0), /* Timer/Counter E0 Overflow */ - DMA_CH_TRIGSRC_TCE0_ERR_gc = (0x81<<0), /* Timer/Counter E0 Error */ - DMA_CH_TRIGSRC_TCE0_CCA_gc = (0x82<<0), /* Timer/Counter E0 Compare or Capture A */ - DMA_CH_TRIGSRC_TCE0_CCB_gc = (0x83<<0), /* Timer/Counter E0 Compare or Capture B */ - DMA_CH_TRIGSRC_TCE0_CCC_gc = (0x84<<0), /* Timer/Counter E0 Compare or Capture C */ - DMA_CH_TRIGSRC_TCE0_CCD_gc = (0x85<<0), /* Timer/Counter E0 Compare or Capture D */ - DMA_CH_TRIGSRC_TCE1_OVF_gc = (0x86<<0), /* Timer/Counter E1 Overflow */ - DMA_CH_TRIGSRC_TCE1_ERR_gc = (0x87<<0), /* Timer/Counter E1 Error */ - DMA_CH_TRIGSRC_TCE1_CCA_gc = (0x88<<0), /* Timer/Counter E1 Compare or Capture A */ - DMA_CH_TRIGSRC_TCE1_CCB_gc = (0x89<<0), /* Timer/Counter E1 Compare or Capture B */ - DMA_CH_TRIGSRC_SPIE_gc = (0x8A<<0), /* SPI E Transfer Complete */ - DMA_CH_TRIGSRC_USARTE0_RXC_gc = (0x8B<<0), /* USART E0 Receive Complete */ - DMA_CH_TRIGSRC_USARTE0_DRE_gc = (0x8C<<0), /* USART E0 Data Register Empty */ - DMA_CH_TRIGSRC_USARTE1_RXC_gc = (0x8E<<0), /* USART E1 Receive Complete */ - DMA_CH_TRIGSRC_USARTE1_DRE_gc = (0x8F<<0), /* USART E1 Data Register Empty */ - DMA_CH_TRIGSRC_TCF0_OVF_gc = (0xA0<<0), /* Timer/Counter F0 Overflow */ - DMA_CH_TRIGSRC_TCF0_ERR_gc = (0xA1<<0), /* Timer/Counter F0 Error */ - DMA_CH_TRIGSRC_TCF0_CCA_gc = (0xA2<<0), /* Timer/Counter F0 Compare or Capture A */ - DMA_CH_TRIGSRC_TCF0_CCB_gc = (0xA3<<0), /* Timer/Counter F0 Compare or Capture B */ - DMA_CH_TRIGSRC_TCF0_CCC_gc = (0xA4<<0), /* Timer/Counter F0 Compare or Capture C */ - DMA_CH_TRIGSRC_TCF0_CCD_gc = (0xA5<<0), /* Timer/Counter F0 Compare or Capture D */ - DMA_CH_TRIGSRC_TCF1_OVF_gc = (0xA6<<0), /* Timer/Counter F1 Overflow */ - DMA_CH_TRIGSRC_TCF1_ERR_gc = (0xA7<<0), /* Timer/Counter F1 Error */ - DMA_CH_TRIGSRC_TCF1_CCA_gc = (0xA8<<0), /* Timer/Counter F1 Compare or Capture A */ - DMA_CH_TRIGSRC_TCF1_CCB_gc = (0xA9<<0), /* Timer/Counter F1 Compare or Capture B */ - DMA_CH_TRIGSRC_SPIF_gc = (0xAA<<0), /* SPI F Transfer Complete */ - DMA_CH_TRIGSRC_USARTF0_RXC_gc = (0xAB<<0), /* USART F0 Receive Complete */ - DMA_CH_TRIGSRC_USARTF0_DRE_gc = (0xAC<<0), /* USART F0 Data Register Empty */ - DMA_CH_TRIGSRC_USARTF1_RXC_gc = (0xAE<<0), /* USART F1 Receive Complete */ - DMA_CH_TRIGSRC_USARTF1_DRE_gc = (0xAF<<0), /* USART F1 Data Register Empty */ -} DMA_CH_TRIGSRC_t; - -/* Double buffering mode */ -typedef enum DMA_DBUFMODE_enum -{ - DMA_DBUFMODE_DISABLED_gc = (0x00<<2), /* Double buffering disabled */ - DMA_DBUFMODE_CH01_gc = (0x01<<2), /* Double buffering enabled on channel 0/1 */ - DMA_DBUFMODE_CH23_gc = (0x02<<2), /* Double buffering enabled on channel 2/3 */ - DMA_DBUFMODE_CH01CH23_gc = (0x03<<2), /* Double buffering enabled on ch. 0/1 and ch. 2/3 */ -} DMA_DBUFMODE_t; - -/* Priority mode */ -typedef enum DMA_PRIMODE_enum -{ - DMA_PRIMODE_RR0123_gc = (0x00<<0), /* Round Robin */ - DMA_PRIMODE_CH0RR123_gc = (0x01<<0), /* Channel 0 > Round Robin on channel 1/2/3 */ - DMA_PRIMODE_CH01RR23_gc = (0x02<<0), /* Channel 0 > channel 1 > Round Robin on channel 2/3 */ - DMA_PRIMODE_CH0123_gc = (0x03<<0), /* Channel 0 > channel 1 > channel 2 > channel 3 */ -} DMA_PRIMODE_t; - -/* Interrupt level */ -typedef enum DMA_CH_ERRINTLVL_enum -{ - DMA_CH_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ - DMA_CH_ERRINTLVL_LO_gc = (0x01<<2), /* Low level */ - DMA_CH_ERRINTLVL_MED_gc = (0x02<<2), /* Medium level */ - DMA_CH_ERRINTLVL_HI_gc = (0x03<<2), /* High level */ -} DMA_CH_ERRINTLVL_t; - -/* Interrupt level */ -typedef enum DMA_CH_TRNINTLVL_enum -{ - DMA_CH_TRNINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ - DMA_CH_TRNINTLVL_LO_gc = (0x01<<0), /* Low level */ - DMA_CH_TRNINTLVL_MED_gc = (0x02<<0), /* Medium level */ - DMA_CH_TRNINTLVL_HI_gc = (0x03<<0), /* High level */ -} DMA_CH_TRNINTLVL_t; - - -/* --------------------------------------------------------------------------- -EVSYS - Event System --------------------------------------------------------------------------- -*/ - -/* Event System */ -typedef struct EVSYS_struct -{ - register8_t CH0MUX; /* Event Channel 0 Multiplexer */ - register8_t CH1MUX; /* Event Channel 1 Multiplexer */ - register8_t CH2MUX; /* Event Channel 2 Multiplexer */ - register8_t CH3MUX; /* Event Channel 3 Multiplexer */ - register8_t CH4MUX; /* Event Channel 4 Multiplexer */ - register8_t CH5MUX; /* Event Channel 5 Multiplexer */ - register8_t CH6MUX; /* Event Channel 6 Multiplexer */ - register8_t CH7MUX; /* Event Channel 7 Multiplexer */ - register8_t CH0CTRL; /* Channel 0 Control Register */ - register8_t CH1CTRL; /* Channel 1 Control Register */ - register8_t CH2CTRL; /* Channel 2 Control Register */ - register8_t CH3CTRL; /* Channel 3 Control Register */ - register8_t CH4CTRL; /* Channel 4 Control Register */ - register8_t CH5CTRL; /* Channel 5 Control Register */ - register8_t CH6CTRL; /* Channel 6 Control Register */ - register8_t CH7CTRL; /* Channel 7 Control Register */ - register8_t STROBE; /* Event Strobe */ - register8_t DATA; /* Event Data */ -} EVSYS_t; - -/* Quadrature Decoder Index Recognition Mode */ -typedef enum EVSYS_QDIRM_enum -{ - EVSYS_QDIRM_00_gc = (0x00<<5), /* QDPH0 = 0, QDPH90 = 0 */ - EVSYS_QDIRM_01_gc = (0x01<<5), /* QDPH0 = 0, QDPH90 = 1 */ - EVSYS_QDIRM_10_gc = (0x02<<5), /* QDPH0 = 1, QDPH90 = 0 */ - EVSYS_QDIRM_11_gc = (0x03<<5), /* QDPH0 = 1, QDPH90 = 1 */ -} EVSYS_QDIRM_t; - -/* Digital filter coefficient */ -typedef enum EVSYS_DIGFILT_enum -{ - EVSYS_DIGFILT_1SAMPLE_gc = (0x00<<0), /* 1 SAMPLE */ - EVSYS_DIGFILT_2SAMPLES_gc = (0x01<<0), /* 2 SAMPLES */ - EVSYS_DIGFILT_3SAMPLES_gc = (0x02<<0), /* 3 SAMPLES */ - EVSYS_DIGFILT_4SAMPLES_gc = (0x03<<0), /* 4 SAMPLES */ - EVSYS_DIGFILT_5SAMPLES_gc = (0x04<<0), /* 5 SAMPLES */ - EVSYS_DIGFILT_6SAMPLES_gc = (0x05<<0), /* 6 SAMPLES */ - EVSYS_DIGFILT_7SAMPLES_gc = (0x06<<0), /* 7 SAMPLES */ - EVSYS_DIGFILT_8SAMPLES_gc = (0x07<<0), /* 8 SAMPLES */ -} EVSYS_DIGFILT_t; - -/* Event Channel multiplexer input selection */ -typedef enum EVSYS_CHMUX_enum -{ - EVSYS_CHMUX_OFF_gc = (0x00<<0), /* Off */ - EVSYS_CHMUX_RTC_OVF_gc = (0x08<<0), /* RTC Overflow */ - EVSYS_CHMUX_RTC_CMP_gc = (0x09<<0), /* RTC Compare Match */ - EVSYS_CHMUX_USB_gc = (0x0A<<0), /* USB Setup, SOF, CRC error and UNF/OVF */ - EVSYS_CHMUX_ACA_CH0_gc = (0x10<<0), /* Analog Comparator A Channel 0 */ - EVSYS_CHMUX_ACA_CH1_gc = (0x11<<0), /* Analog Comparator A Channel 1 */ - EVSYS_CHMUX_ACA_WIN_gc = (0x12<<0), /* Analog Comparator A Window */ - EVSYS_CHMUX_ACB_CH0_gc = (0x13<<0), /* Analog Comparator B Channel 0 */ - EVSYS_CHMUX_ACB_CH1_gc = (0x14<<0), /* Analog Comparator B Channel 1 */ - EVSYS_CHMUX_ACB_WIN_gc = (0x15<<0), /* Analog Comparator B Window */ - EVSYS_CHMUX_ADCA_CH0_gc = (0x20<<0), /* ADC A Channel 0 */ - EVSYS_CHMUX_ADCA_CH1_gc = (0x21<<0), /* ADC A Channel 1 */ - EVSYS_CHMUX_ADCA_CH2_gc = (0x22<<0), /* ADC A Channel 2 */ - EVSYS_CHMUX_ADCA_CH3_gc = (0x23<<0), /* ADC A Channel 3 */ - EVSYS_CHMUX_ADCB_CH0_gc = (0x24<<0), /* ADC B Channel 0 */ - EVSYS_CHMUX_ADCB_CH1_gc = (0x25<<0), /* ADC B Channel 1 */ - EVSYS_CHMUX_ADCB_CH2_gc = (0x26<<0), /* ADC B Channel 2 */ - EVSYS_CHMUX_ADCB_CH3_gc = (0x27<<0), /* ADC B Channel 3 */ - EVSYS_CHMUX_PORTA_PIN0_gc = (0x50<<0), /* Port A, Pin0 */ - EVSYS_CHMUX_PORTA_PIN1_gc = (0x51<<0), /* Port A, Pin1 */ - EVSYS_CHMUX_PORTA_PIN2_gc = (0x52<<0), /* Port A, Pin2 */ - EVSYS_CHMUX_PORTA_PIN3_gc = (0x53<<0), /* Port A, Pin3 */ - EVSYS_CHMUX_PORTA_PIN4_gc = (0x54<<0), /* Port A, Pin4 */ - EVSYS_CHMUX_PORTA_PIN5_gc = (0x55<<0), /* Port A, Pin5 */ - EVSYS_CHMUX_PORTA_PIN6_gc = (0x56<<0), /* Port A, Pin6 */ - EVSYS_CHMUX_PORTA_PIN7_gc = (0x57<<0), /* Port A, Pin7 */ - EVSYS_CHMUX_PORTB_PIN0_gc = (0x58<<0), /* Port B, Pin0 */ - EVSYS_CHMUX_PORTB_PIN1_gc = (0x59<<0), /* Port B, Pin1 */ - EVSYS_CHMUX_PORTB_PIN2_gc = (0x5A<<0), /* Port B, Pin2 */ - EVSYS_CHMUX_PORTB_PIN3_gc = (0x5B<<0), /* Port B, Pin3 */ - EVSYS_CHMUX_PORTB_PIN4_gc = (0x5C<<0), /* Port B, Pin4 */ - EVSYS_CHMUX_PORTB_PIN5_gc = (0x5D<<0), /* Port B, Pin5 */ - EVSYS_CHMUX_PORTB_PIN6_gc = (0x5E<<0), /* Port B, Pin6 */ - EVSYS_CHMUX_PORTB_PIN7_gc = (0x5F<<0), /* Port B, Pin7 */ - EVSYS_CHMUX_PORTC_PIN0_gc = (0x60<<0), /* Port C, Pin0 */ - EVSYS_CHMUX_PORTC_PIN1_gc = (0x61<<0), /* Port C, Pin1 */ - EVSYS_CHMUX_PORTC_PIN2_gc = (0x62<<0), /* Port C, Pin2 */ - EVSYS_CHMUX_PORTC_PIN3_gc = (0x63<<0), /* Port C, Pin3 */ - EVSYS_CHMUX_PORTC_PIN4_gc = (0x64<<0), /* Port C, Pin4 */ - EVSYS_CHMUX_PORTC_PIN5_gc = (0x65<<0), /* Port C, Pin5 */ - EVSYS_CHMUX_PORTC_PIN6_gc = (0x66<<0), /* Port C, Pin6 */ - EVSYS_CHMUX_PORTC_PIN7_gc = (0x67<<0), /* Port C, Pin7 */ - EVSYS_CHMUX_PORTD_PIN0_gc = (0x68<<0), /* Port D, Pin0 */ - EVSYS_CHMUX_PORTD_PIN1_gc = (0x69<<0), /* Port D, Pin1 */ - EVSYS_CHMUX_PORTD_PIN2_gc = (0x6A<<0), /* Port D, Pin2 */ - EVSYS_CHMUX_PORTD_PIN3_gc = (0x6B<<0), /* Port D, Pin3 */ - EVSYS_CHMUX_PORTD_PIN4_gc = (0x6C<<0), /* Port D, Pin4 */ - EVSYS_CHMUX_PORTD_PIN5_gc = (0x6D<<0), /* Port D, Pin5 */ - EVSYS_CHMUX_PORTD_PIN6_gc = (0x6E<<0), /* Port D, Pin6 */ - EVSYS_CHMUX_PORTD_PIN7_gc = (0x6F<<0), /* Port D, Pin7 */ - EVSYS_CHMUX_PORTE_PIN0_gc = (0x70<<0), /* Port E, Pin0 */ - EVSYS_CHMUX_PORTE_PIN1_gc = (0x71<<0), /* Port E, Pin1 */ - EVSYS_CHMUX_PORTE_PIN2_gc = (0x72<<0), /* Port E, Pin2 */ - EVSYS_CHMUX_PORTE_PIN3_gc = (0x73<<0), /* Port E, Pin3 */ - EVSYS_CHMUX_PORTE_PIN4_gc = (0x74<<0), /* Port E, Pin4 */ - EVSYS_CHMUX_PORTE_PIN5_gc = (0x75<<0), /* Port E, Pin5 */ - EVSYS_CHMUX_PORTE_PIN6_gc = (0x76<<0), /* Port E, Pin6 */ - EVSYS_CHMUX_PORTE_PIN7_gc = (0x77<<0), /* Port E, Pin7 */ - EVSYS_CHMUX_PORTF_PIN0_gc = (0x78<<0), /* Port F, Pin0 */ - EVSYS_CHMUX_PORTF_PIN1_gc = (0x79<<0), /* Port F, Pin1 */ - EVSYS_CHMUX_PORTF_PIN2_gc = (0x7A<<0), /* Port F, Pin2 */ - EVSYS_CHMUX_PORTF_PIN3_gc = (0x7B<<0), /* Port F, Pin3 */ - EVSYS_CHMUX_PORTF_PIN4_gc = (0x7C<<0), /* Port F, Pin4 */ - EVSYS_CHMUX_PORTF_PIN5_gc = (0x7D<<0), /* Port F, Pin5 */ - EVSYS_CHMUX_PORTF_PIN6_gc = (0x7E<<0), /* Port F, Pin6 */ - EVSYS_CHMUX_PORTF_PIN7_gc = (0x7F<<0), /* Port F, Pin7 */ - EVSYS_CHMUX_PRESCALER_1_gc = (0x80<<0), /* Prescaler, divide by 1 */ - EVSYS_CHMUX_PRESCALER_2_gc = (0x81<<0), /* Prescaler, divide by 2 */ - EVSYS_CHMUX_PRESCALER_4_gc = (0x82<<0), /* Prescaler, divide by 4 */ - EVSYS_CHMUX_PRESCALER_8_gc = (0x83<<0), /* Prescaler, divide by 8 */ - EVSYS_CHMUX_PRESCALER_16_gc = (0x84<<0), /* Prescaler, divide by 16 */ - EVSYS_CHMUX_PRESCALER_32_gc = (0x85<<0), /* Prescaler, divide by 32 */ - EVSYS_CHMUX_PRESCALER_64_gc = (0x86<<0), /* Prescaler, divide by 64 */ - EVSYS_CHMUX_PRESCALER_128_gc = (0x87<<0), /* Prescaler, divide by 128 */ - EVSYS_CHMUX_PRESCALER_256_gc = (0x88<<0), /* Prescaler, divide by 256 */ - EVSYS_CHMUX_PRESCALER_512_gc = (0x89<<0), /* Prescaler, divide by 512 */ - EVSYS_CHMUX_PRESCALER_1024_gc = (0x8A<<0), /* Prescaler, divide by 1024 */ - EVSYS_CHMUX_PRESCALER_2048_gc = (0x8B<<0), /* Prescaler, divide by 2048 */ - EVSYS_CHMUX_PRESCALER_4096_gc = (0x8C<<0), /* Prescaler, divide by 4096 */ - EVSYS_CHMUX_PRESCALER_8192_gc = (0x8D<<0), /* Prescaler, divide by 8192 */ - EVSYS_CHMUX_PRESCALER_16384_gc = (0x8E<<0), /* Prescaler, divide by 16384 */ - EVSYS_CHMUX_PRESCALER_32768_gc = (0x8F<<0), /* Prescaler, divide by 32768 */ - EVSYS_CHMUX_TCC0_OVF_gc = (0xC0<<0), /* Timer/Counter C0 Overflow */ - EVSYS_CHMUX_TCC0_ERR_gc = (0xC1<<0), /* Timer/Counter C0 Error */ - EVSYS_CHMUX_TCC0_CCA_gc = (0xC4<<0), /* Timer/Counter C0 Compare or Capture A */ - EVSYS_CHMUX_TCC0_CCB_gc = (0xC5<<0), /* Timer/Counter C0 Compare or Capture B */ - EVSYS_CHMUX_TCC0_CCC_gc = (0xC6<<0), /* Timer/Counter C0 Compare or Capture C */ - EVSYS_CHMUX_TCC0_CCD_gc = (0xC7<<0), /* Timer/Counter C0 Compare or Capture D */ - EVSYS_CHMUX_TCC1_OVF_gc = (0xC8<<0), /* Timer/Counter C1 Overflow */ - EVSYS_CHMUX_TCC1_ERR_gc = (0xC9<<0), /* Timer/Counter C1 Error */ - EVSYS_CHMUX_TCC1_CCA_gc = (0xCC<<0), /* Timer/Counter C1 Compare or Capture A */ - EVSYS_CHMUX_TCC1_CCB_gc = (0xCD<<0), /* Timer/Counter C1 Compare or Capture B */ - EVSYS_CHMUX_TCD0_OVF_gc = (0xD0<<0), /* Timer/Counter D0 Overflow */ - EVSYS_CHMUX_TCD0_ERR_gc = (0xD1<<0), /* Timer/Counter D0 Error */ - EVSYS_CHMUX_TCD0_CCA_gc = (0xD4<<0), /* Timer/Counter D0 Compare or Capture A */ - EVSYS_CHMUX_TCD0_CCB_gc = (0xD5<<0), /* Timer/Counter D0 Compare or Capture B */ - EVSYS_CHMUX_TCD0_CCC_gc = (0xD6<<0), /* Timer/Counter D0 Compare or Capture C */ - EVSYS_CHMUX_TCD0_CCD_gc = (0xD7<<0), /* Timer/Counter D0 Compare or Capture D */ - EVSYS_CHMUX_TCD1_OVF_gc = (0xD8<<0), /* Timer/Counter D1 Overflow */ - EVSYS_CHMUX_TCD1_ERR_gc = (0xD9<<0), /* Timer/Counter D1 Error */ - EVSYS_CHMUX_TCD1_CCA_gc = (0xDC<<0), /* Timer/Counter D1 Compare or Capture A */ - EVSYS_CHMUX_TCD1_CCB_gc = (0xDD<<0), /* Timer/Counter D1 Compare or Capture B */ - EVSYS_CHMUX_TCE0_OVF_gc = (0xE0<<0), /* Timer/Counter E0 Overflow */ - EVSYS_CHMUX_TCE0_ERR_gc = (0xE1<<0), /* Timer/Counter E0 Error */ - EVSYS_CHMUX_TCE0_CCA_gc = (0xE4<<0), /* Timer/Counter E0 Compare or Capture A */ - EVSYS_CHMUX_TCE0_CCB_gc = (0xE5<<0), /* Timer/Counter E0 Compare or Capture B */ - EVSYS_CHMUX_TCE0_CCC_gc = (0xE6<<0), /* Timer/Counter E0 Compare or Capture C */ - EVSYS_CHMUX_TCE0_CCD_gc = (0xE7<<0), /* Timer/Counter E0 Compare or Capture D */ - EVSYS_CHMUX_TCE1_OVF_gc = (0xE8<<0), /* Timer/Counter E1 Overflow */ - EVSYS_CHMUX_TCE1_ERR_gc = (0xE9<<0), /* Timer/Counter E1 Error */ - EVSYS_CHMUX_TCE1_CCA_gc = (0xEC<<0), /* Timer/Counter E1 Compare or Capture A */ - EVSYS_CHMUX_TCE1_CCB_gc = (0xED<<0), /* Timer/Counter E1 Compare or Capture B */ - EVSYS_CHMUX_TCF0_OVF_gc = (0xF0<<0), /* Timer/Counter F0 Overflow */ - EVSYS_CHMUX_TCF0_ERR_gc = (0xF1<<0), /* Timer/Counter F0 Error */ - EVSYS_CHMUX_TCF0_CCA_gc = (0xF4<<0), /* Timer/Counter F0 Compare or Capture A */ - EVSYS_CHMUX_TCF0_CCB_gc = (0xF5<<0), /* Timer/Counter F0 Compare or Capture B */ - EVSYS_CHMUX_TCF0_CCC_gc = (0xF6<<0), /* Timer/Counter F0 Compare or Capture C */ - EVSYS_CHMUX_TCF0_CCD_gc = (0xF7<<0), /* Timer/Counter F0 Compare or Capture D */ - EVSYS_CHMUX_TCF1_OVF_gc = (0xF8<<0), /* Timer/Counter F1 Overflow */ - EVSYS_CHMUX_TCF1_ERR_gc = (0xF9<<0), /* Timer/Counter F1 Error */ - EVSYS_CHMUX_TCF1_CCA_gc = (0xFC<<0), /* Timer/Counter F1 Compare or Capture A */ - EVSYS_CHMUX_TCF1_CCB_gc = (0xFD<<0), /* Timer/Counter F1 Compare or Capture B */ -} EVSYS_CHMUX_t; - - -/* --------------------------------------------------------------------------- -NVM - Non Volatile Memory Controller --------------------------------------------------------------------------- -*/ - -/* Non-volatile Memory Controller */ -typedef struct NVM_struct -{ - register8_t ADDR0; /* Address Register 0 */ - register8_t ADDR1; /* Address Register 1 */ - register8_t ADDR2; /* Address Register 2 */ - register8_t reserved_0x03; - register8_t DATA0; /* Data Register 0 */ - register8_t DATA1; /* Data Register 1 */ - register8_t DATA2; /* Data Register 2 */ - register8_t reserved_0x07; - register8_t reserved_0x08; - register8_t reserved_0x09; - register8_t CMD; /* Command */ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t INTCTRL; /* Interrupt Control */ - register8_t reserved_0x0E; - register8_t STATUS; /* Status */ - register8_t LOCK_BITS; /* Lock Bits (Changed from LOCKBITS to avoid avr-libc collision) */ -} NVM_t; - -/* NVM Command */ -typedef enum NVM_CMD_enum -{ - NVM_CMD_NO_OPERATION_gc = (0x00<<0), /* Noop/Ordinary LPM */ - NVM_CMD_READ_USER_SIG_ROW_gc = (0x01<<0), /* Read user signature row */ - NVM_CMD_READ_CALIB_ROW_gc = (0x02<<0), /* Read calibration row */ - NVM_CMD_READ_EEPROM_gc = (0x06<<0), /* Read EEPROM */ - NVM_CMD_READ_FUSES_gc = (0x07<<0), /* Read fuse byte */ - NVM_CMD_WRITE_LOCK_BITS_gc = (0x08<<0), /* Write lock bits */ - NVM_CMD_ERASE_USER_SIG_ROW_gc = (0x18<<0), /* Erase user signature row */ - NVM_CMD_WRITE_USER_SIG_ROW_gc = (0x1A<<0), /* Write user signature row */ - NVM_CMD_ERASE_APP_gc = (0x20<<0), /* Erase Application Section */ - NVM_CMD_ERASE_APP_PAGE_gc = (0x22<<0), /* Erase Application Section page */ - NVM_CMD_LOAD_FLASH_BUFFER_gc = (0x23<<0), /* Load Flash page buffer */ - NVM_CMD_WRITE_APP_PAGE_gc = (0x24<<0), /* Write Application Section page */ - NVM_CMD_ERASE_WRITE_APP_PAGE_gc = (0x25<<0), /* Erase-and-write Application Section page */ - NVM_CMD_ERASE_FLASH_BUFFER_gc = (0x26<<0), /* Erase/flush Flash page buffer */ - NVM_CMD_ERASE_BOOT_PAGE_gc = (0x2A<<0), /* Erase Boot Section page */ - NVM_CMD_ERASE_FLASH_PAGE_gc = (0x2B<<0), /* Erase Flash Page */ - NVM_CMD_WRITE_BOOT_PAGE_gc = (0x2C<<0), /* Write Boot Section page */ - NVM_CMD_ERASE_WRITE_BOOT_PAGE_gc = (0x2D<<0), /* Erase-and-write Boot Section page */ - NVM_CMD_WRITE_FLASH_PAGE_gc = (0x2E<<0), /* Write Flash Page */ - NVM_CMD_ERASE_WRITE_FLASH_PAGE_gc = (0x2F<<0), /* Erase-and-write Flash Page */ - NVM_CMD_ERASE_EEPROM_gc = (0x30<<0), /* Erase EEPROM */ - NVM_CMD_ERASE_EEPROM_PAGE_gc = (0x32<<0), /* Erase EEPROM page */ - NVM_CMD_LOAD_EEPROM_BUFFER_gc = (0x33<<0), /* Load EEPROM page buffer */ - NVM_CMD_WRITE_EEPROM_PAGE_gc = (0x34<<0), /* Write EEPROM page */ - NVM_CMD_ERASE_WRITE_EEPROM_PAGE_gc = (0x35<<0), /* Erase-and-write EEPROM page */ - NVM_CMD_ERASE_EEPROM_BUFFER_gc = (0x36<<0), /* Erase/flush EEPROM page buffer */ - NVM_CMD_APP_CRC_gc = (0x38<<0), /* Application section CRC */ - NVM_CMD_BOOT_CRC_gc = (0x39<<0), /* Boot Section CRC */ - NVM_CMD_FLASH_RANGE_CRC_gc = (0x3A<<0), /* Flash Range CRC */ - NVM_CMD_CHIP_ERASE_gc = (0x40<<0), /* Erase Chip */ - NVM_CMD_READ_NVM_gc = (0x43<<0), /* Read NVM */ - NVM_CMD_WRITE_FUSE_gc = (0x4C<<0), /* Write Fuse byte */ - NVM_CMD_ERASE_BOOT_gc = (0x68<<0), /* Erase Boot Section */ - NVM_CMD_FLASH_CRC_gc = (0x78<<0), /* Flash CRC */ -} NVM_CMD_t; - -/* SPM ready interrupt level */ -typedef enum NVM_SPMLVL_enum -{ - NVM_SPMLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ - NVM_SPMLVL_LO_gc = (0x01<<2), /* Low level */ - NVM_SPMLVL_MED_gc = (0x02<<2), /* Medium level */ - NVM_SPMLVL_HI_gc = (0x03<<2), /* High level */ -} NVM_SPMLVL_t; - -/* EEPROM ready interrupt level */ -typedef enum NVM_EELVL_enum -{ - NVM_EELVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ - NVM_EELVL_LO_gc = (0x01<<0), /* Low level */ - NVM_EELVL_MED_gc = (0x02<<0), /* Medium level */ - NVM_EELVL_HI_gc = (0x03<<0), /* High level */ -} NVM_EELVL_t; - -/* Boot lock bits - boot setcion */ -typedef enum NVM_BLBB_enum -{ - NVM_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ - NVM_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ - NVM_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ - NVM_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ -} NVM_BLBB_t; - -/* Boot lock bits - application section */ -typedef enum NVM_BLBA_enum -{ - NVM_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ - NVM_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ - NVM_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ - NVM_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ -} NVM_BLBA_t; - -/* Boot lock bits - application table section */ -typedef enum NVM_BLBAT_enum -{ - NVM_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ - NVM_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ - NVM_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ - NVM_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ -} NVM_BLBAT_t; - -/* Lock bits */ -typedef enum NVM_LB_enum -{ - NVM_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ - NVM_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ - NVM_LB_NOLOCK_gc = (0x03<<0), /* No locks */ -} NVM_LB_t; - - -/* --------------------------------------------------------------------------- -ADC - Analog/Digital Converter --------------------------------------------------------------------------- -*/ - -/* ADC Channel */ -typedef struct ADC_CH_struct -{ - register8_t CTRL; /* Control Register */ - register8_t MUXCTRL; /* MUX Control */ - register8_t INTCTRL; /* Channel Interrupt Control Register */ - register8_t INTFLAGS; /* Interrupt Flags */ - _WORDREGISTER(RES); /* Channel Result */ - register8_t SCAN; /* Input Channel Scan */ - register8_t reserved_0x07; -} ADC_CH_t; - - -/* Analog-to-Digital Converter */ -typedef struct ADC_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t REFCTRL; /* Reference Control */ - register8_t EVCTRL; /* Event Control */ - register8_t PRESCALER; /* Clock Prescaler */ - register8_t reserved_0x05; - register8_t INTFLAGS; /* Interrupt Flags */ - register8_t TEMP; /* Temporary Register */ - register8_t reserved_0x08; - register8_t reserved_0x09; - register8_t reserved_0x0A; - register8_t reserved_0x0B; - _WORDREGISTER(CAL); /* Calibration Value */ - register8_t reserved_0x0E; - register8_t reserved_0x0F; - _WORDREGISTER(CH0RES); /* Channel 0 Result */ - _WORDREGISTER(CH1RES); /* Channel 1 Result */ - _WORDREGISTER(CH2RES); /* Channel 2 Result */ - _WORDREGISTER(CH3RES); /* Channel 3 Result */ - _WORDREGISTER(CMP); /* Compare Value */ - register8_t reserved_0x1A; - register8_t reserved_0x1B; - register8_t reserved_0x1C; - register8_t reserved_0x1D; - register8_t reserved_0x1E; - register8_t reserved_0x1F; - ADC_CH_t CH0; /* ADC Channel 0 */ - ADC_CH_t CH1; /* ADC Channel 1 */ - ADC_CH_t CH2; /* ADC Channel 2 */ - ADC_CH_t CH3; /* ADC Channel 3 */ -} ADC_t; - -/* Positive input multiplexer selection */ -typedef enum ADC_CH_MUXPOS_enum -{ - ADC_CH_MUXPOS_PIN0_gc = (0x00<<3), /* Input pin 0 */ - ADC_CH_MUXPOS_PIN1_gc = (0x01<<3), /* Input pin 1 */ - ADC_CH_MUXPOS_PIN2_gc = (0x02<<3), /* Input pin 2 */ - ADC_CH_MUXPOS_PIN3_gc = (0x03<<3), /* Input pin 3 */ - ADC_CH_MUXPOS_PIN4_gc = (0x04<<3), /* Input pin 4 */ - ADC_CH_MUXPOS_PIN5_gc = (0x05<<3), /* Input pin 5 */ - ADC_CH_MUXPOS_PIN6_gc = (0x06<<3), /* Input pin 6 */ - ADC_CH_MUXPOS_PIN7_gc = (0x07<<3), /* Input pin 7 */ - ADC_CH_MUXPOS_PIN8_gc = (0x08<<3), /* Input pin 8 */ - ADC_CH_MUXPOS_PIN9_gc = (0x09<<3), /* Input pin 9 */ - ADC_CH_MUXPOS_PIN10_gc = (0x0A<<3), /* Input pin 10 */ - ADC_CH_MUXPOS_PIN11_gc = (0x0B<<3), /* Input pin 11 */ - ADC_CH_MUXPOS_PIN12_gc = (0x0C<<3), /* Input pin 12 */ - ADC_CH_MUXPOS_PIN13_gc = (0x0D<<3), /* Input pin 13 */ - ADC_CH_MUXPOS_PIN14_gc = (0x0E<<3), /* Input pin 14 */ - ADC_CH_MUXPOS_PIN15_gc = (0x0F<<3), /* Input pin 15 */ -} ADC_CH_MUXPOS_t; - -/* Internal input multiplexer selections */ -typedef enum ADC_CH_MUXINT_enum -{ - ADC_CH_MUXINT_TEMP_gc = (0x00<<3), /* Temperature Reference */ - ADC_CH_MUXINT_BANDGAP_gc = (0x01<<3), /* Bandgap Reference */ - ADC_CH_MUXINT_SCALEDVCC_gc = (0x02<<3), /* 1/10 scaled VCC */ - ADC_CH_MUXINT_DAC_gc = (0x03<<3), /* DAC output */ -} ADC_CH_MUXINT_t; - -/* Negative input multiplexer selection */ -typedef enum ADC_CH_MUXNEG_enum -{ - ADC_CH_MUXNEG_PIN0_gc = (0x00<<0), /* Input pin 0 (Input Mode = 2) */ - ADC_CH_MUXNEG_PIN1_gc = (0x01<<0), /* Input pin 1 (Input Mode = 2) */ - ADC_CH_MUXNEG_PIN2_gc = (0x02<<0), /* Input pin 2 (Input Mode = 2) */ - ADC_CH_MUXNEG_PIN3_gc = (0x03<<0), /* Input pin 3 (Input Mode = 2) */ - ADC_CH_MUXNEG_PIN4_gc = (0x00<<0), /* Input pin 4 (Input Mode = 3) */ - ADC_CH_MUXNEG_PIN5_gc = (0x01<<0), /* Input pin 5 (Input Mode = 3) */ - ADC_CH_MUXNEG_PIN6_gc = (0x02<<0), /* Input pin 6 (Input Mode = 3) */ - ADC_CH_MUXNEG_PIN7_gc = (0x03<<0), /* Input pin 7 (Input Mode = 3) */ - ADC_CH_MUXNEG_GND_MODE3_gc = (0x05<<0), /* PAD Ground (Input Mode = 2) */ - ADC_CH_MUXNEG_INTGND_MODE3_gc = (0x07<<0), /* Internal Ground (Input Mode = 2) */ - ADC_CH_MUXNEG_INTGND_MODE4_gc = (0x04<<0), /* Internal Ground (Input Mode = 3) */ - ADC_CH_MUXNEG_GND_MODE4_gc = (0x07<<0), /* PAD Ground (Input Mode = 3) */ -} ADC_CH_MUXNEG_t; - -/* Input mode */ -typedef enum ADC_CH_INPUTMODE_enum -{ - ADC_CH_INPUTMODE_INTERNAL_gc = (0x00<<0), /* Internal inputs, no gain */ - ADC_CH_INPUTMODE_SINGLEENDED_gc = (0x01<<0), /* Single-ended input, no gain */ - ADC_CH_INPUTMODE_DIFF_gc = (0x02<<0), /* Differential input, no gain */ - ADC_CH_INPUTMODE_DIFFWGAIN_gc = (0x03<<0), /* Differential input, with gain */ -} ADC_CH_INPUTMODE_t; - -/* Gain factor */ -typedef enum ADC_CH_GAIN_enum -{ - ADC_CH_GAIN_1X_gc = (0x00<<2), /* 1x gain */ - ADC_CH_GAIN_2X_gc = (0x01<<2), /* 2x gain */ - ADC_CH_GAIN_4X_gc = (0x02<<2), /* 4x gain */ - ADC_CH_GAIN_8X_gc = (0x03<<2), /* 8x gain */ - ADC_CH_GAIN_16X_gc = (0x04<<2), /* 16x gain */ - ADC_CH_GAIN_32X_gc = (0x05<<2), /* 32x gain */ - ADC_CH_GAIN_64X_gc = (0x06<<2), /* 64x gain */ - ADC_CH_GAIN_DIV2_gc = (0x07<<2), /* x/2 gain */ -} ADC_CH_GAIN_t; - -/* Conversion result resolution */ -typedef enum ADC_RESOLUTION_enum -{ - ADC_RESOLUTION_12BIT_gc = (0x00<<1), /* 12-bit right-adjusted result */ - ADC_RESOLUTION_8BIT_gc = (0x02<<1), /* 8-bit right-adjusted result */ - ADC_RESOLUTION_LEFT12BIT_gc = (0x03<<1), /* 12-bit left-adjusted result */ -} ADC_RESOLUTION_t; - -/* Current Limitation Mode */ -typedef enum ADC_CURRLIMIT_enum -{ - ADC_CURRLIMIT_NO_gc = (0x00<<5), /* No limit */ - ADC_CURRLIMIT_LOW_gc = (0x01<<5), /* Low current limit, max. sampling rate 1.5MSPS */ - ADC_CURRLIMIT_MED_gc = (0x02<<5), /* Medium current limit, max. sampling rate 1MSPS */ - ADC_CURRLIMIT_HIGH_gc = (0x03<<5), /* High current limit, max. sampling rate 0.5MSPS */ -} ADC_CURRLIMIT_t; - -/* Voltage reference selection */ -typedef enum ADC_REFSEL_enum -{ - ADC_REFSEL_INT1V_gc = (0x00<<4), /* Internal 1V */ - ADC_REFSEL_INTVCC_gc = (0x01<<4), /* Internal VCC / 1.6 */ - ADC_REFSEL_AREFA_gc = (0x02<<4), /* External reference on PORT A */ - ADC_REFSEL_AREFB_gc = (0x03<<4), /* External reference on PORT B */ - ADC_REFSEL_INTVCC2_gc = (0x04<<4), /* Internal VCC / 2 */ -} ADC_REFSEL_t; - -/* Channel sweep selection */ -typedef enum ADC_SWEEP_enum -{ - ADC_SWEEP_0_gc = (0x00<<6), /* ADC Channel 0 */ - ADC_SWEEP_01_gc = (0x01<<6), /* ADC Channel 0,1 */ - ADC_SWEEP_012_gc = (0x02<<6), /* ADC Channel 0,1,2 */ - ADC_SWEEP_0123_gc = (0x03<<6), /* ADC Channel 0,1,2,3 */ -} ADC_SWEEP_t; - -/* Event channel input selection */ -typedef enum ADC_EVSEL_enum -{ - ADC_EVSEL_0123_gc = (0x00<<3), /* Event Channel 0,1,2,3 */ - ADC_EVSEL_1234_gc = (0x01<<3), /* Event Channel 1,2,3,4 */ - ADC_EVSEL_2345_gc = (0x02<<3), /* Event Channel 2,3,4,5 */ - ADC_EVSEL_3456_gc = (0x03<<3), /* Event Channel 3,4,5,6 */ - ADC_EVSEL_4567_gc = (0x04<<3), /* Event Channel 4,5,6,7 */ - ADC_EVSEL_567_gc = (0x05<<3), /* Event Channel 5,6,7 */ - ADC_EVSEL_67_gc = (0x06<<3), /* Event Channel 6,7 */ - ADC_EVSEL_7_gc = (0x07<<3), /* Event Channel 7 */ -} ADC_EVSEL_t; - -/* Event action selection */ -typedef enum ADC_EVACT_enum -{ - ADC_EVACT_NONE_gc = (0x00<<0), /* No event action */ - ADC_EVACT_CH0_gc = (0x01<<0), /* First event triggers channel 0 */ - ADC_EVACT_CH01_gc = (0x02<<0), /* First two events trigger channel 0,1 */ - ADC_EVACT_CH012_gc = (0x03<<0), /* First three events trigger channel 0,1,2 */ - ADC_EVACT_CH0123_gc = (0x04<<0), /* Events trigger channel 0,1,2,3 */ - ADC_EVACT_SWEEP_gc = (0x05<<0), /* First event triggers sweep */ - ADC_EVACT_SYNCSWEEP_gc = (0x06<<0), /* The ADC is flushed and restarted for accurate timing */ -} ADC_EVACT_t; - -/* Interupt mode */ -typedef enum ADC_CH_INTMODE_enum -{ - ADC_CH_INTMODE_COMPLETE_gc = (0x00<<2), /* Interrupt on conversion complete */ - ADC_CH_INTMODE_BELOW_gc = (0x01<<2), /* Interrupt on result below compare value */ - ADC_CH_INTMODE_ABOVE_gc = (0x03<<2), /* Interrupt on result above compare value */ -} ADC_CH_INTMODE_t; - -/* Interrupt level */ -typedef enum ADC_CH_INTLVL_enum -{ - ADC_CH_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ - ADC_CH_INTLVL_LO_gc = (0x01<<0), /* Low level */ - ADC_CH_INTLVL_MED_gc = (0x02<<0), /* Medium level */ - ADC_CH_INTLVL_HI_gc = (0x03<<0), /* High level */ -} ADC_CH_INTLVL_t; - -/* DMA request selection */ -typedef enum ADC_DMASEL_enum -{ - ADC_DMASEL_OFF_gc = (0x00<<6), /* Combined DMA request OFF */ - ADC_DMASEL_CH01_gc = (0x01<<6), /* ADC Channel 0 or 1 */ - ADC_DMASEL_CH012_gc = (0x02<<6), /* ADC Channel 0 or 1 or 2 */ - ADC_DMASEL_CH0123_gc = (0x03<<6), /* ADC Channel 0 or 1 or 2 or 3 */ -} ADC_DMASEL_t; - -/* Clock prescaler */ -typedef enum ADC_PRESCALER_enum -{ - ADC_PRESCALER_DIV4_gc = (0x00<<0), /* Divide clock by 4 */ - ADC_PRESCALER_DIV8_gc = (0x01<<0), /* Divide clock by 8 */ - ADC_PRESCALER_DIV16_gc = (0x02<<0), /* Divide clock by 16 */ - ADC_PRESCALER_DIV32_gc = (0x03<<0), /* Divide clock by 32 */ - ADC_PRESCALER_DIV64_gc = (0x04<<0), /* Divide clock by 64 */ - ADC_PRESCALER_DIV128_gc = (0x05<<0), /* Divide clock by 128 */ - ADC_PRESCALER_DIV256_gc = (0x06<<0), /* Divide clock by 256 */ - ADC_PRESCALER_DIV512_gc = (0x07<<0), /* Divide clock by 512 */ -} ADC_PRESCALER_t; - - -/* --------------------------------------------------------------------------- -DAC - Digital/Analog Converter --------------------------------------------------------------------------- -*/ - -/* Digital-to-Analog Converter */ -typedef struct DAC_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t CTRLC; /* Control Register C */ - register8_t EVCTRL; /* Event Input Control */ - register8_t reserved_0x04; - register8_t STATUS; /* Status */ - register8_t reserved_0x06; - register8_t reserved_0x07; - register8_t CH0GAINCAL; /* Gain Calibration */ - register8_t CH0OFFSETCAL; /* Offset Calibration */ - register8_t CH1GAINCAL; /* Gain Calibration */ - register8_t CH1OFFSETCAL; /* Offset Calibration */ - register8_t reserved_0x0C; - register8_t reserved_0x0D; - register8_t reserved_0x0E; - register8_t reserved_0x0F; - register8_t reserved_0x10; - register8_t reserved_0x11; - register8_t reserved_0x12; - register8_t reserved_0x13; - register8_t reserved_0x14; - register8_t reserved_0x15; - register8_t reserved_0x16; - register8_t reserved_0x17; - _WORDREGISTER(CH0DATA); /* Channel 0 Data */ - _WORDREGISTER(CH1DATA); /* Channel 1 Data */ -} DAC_t; - -/* Output channel selection */ -typedef enum DAC_CHSEL_enum -{ - DAC_CHSEL_SINGLE_gc = (0x00<<5), /* Single channel operation (Channel 0 only) */ - DAC_CHSEL_SINGLE1_gc = (0x01<<5), /* Single channel operation (Channel 1 only) */ - DAC_CHSEL_DUAL_gc = (0x02<<5), /* Dual channel operation (Channel 0 and channel 1) */ -} DAC_CHSEL_t; - -/* Reference voltage selection */ -typedef enum DAC_REFSEL_enum -{ - DAC_REFSEL_INT1V_gc = (0x00<<3), /* Internal 1V */ - DAC_REFSEL_AVCC_gc = (0x01<<3), /* Analog supply voltage */ - DAC_REFSEL_AREFA_gc = (0x02<<3), /* External reference on AREF on PORTA */ - DAC_REFSEL_AREFB_gc = (0x03<<3), /* External reference on AREF on PORTB */ -} DAC_REFSEL_t; - -/* Event channel selection */ -typedef enum DAC_EVSEL_enum -{ - DAC_EVSEL_0_gc = (0x00<<0), /* Event Channel 0 */ - DAC_EVSEL_1_gc = (0x01<<0), /* Event Channel 1 */ - DAC_EVSEL_2_gc = (0x02<<0), /* Event Channel 2 */ - DAC_EVSEL_3_gc = (0x03<<0), /* Event Channel 3 */ - DAC_EVSEL_4_gc = (0x04<<0), /* Event Channel 4 */ - DAC_EVSEL_5_gc = (0x05<<0), /* Event Channel 5 */ - DAC_EVSEL_6_gc = (0x06<<0), /* Event Channel 6 */ - DAC_EVSEL_7_gc = (0x07<<0), /* Event Channel 7 */ -} DAC_EVSEL_t; - - -/* --------------------------------------------------------------------------- -AC - Analog Comparator --------------------------------------------------------------------------- -*/ - -/* Analog Comparator */ -typedef struct AC_struct -{ - register8_t AC0CTRL; /* Analog Comparator 0 Control */ - register8_t AC1CTRL; /* Analog Comparator 1 Control */ - register8_t AC0MUXCTRL; /* Analog Comparator 0 MUX Control */ - register8_t AC1MUXCTRL; /* Analog Comparator 1 MUX Control */ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t WINCTRL; /* Window Mode Control */ - register8_t STATUS; /* Status */ -} AC_t; - -/* Interrupt mode */ -typedef enum AC_INTMODE_enum -{ - AC_INTMODE_BOTHEDGES_gc = (0x00<<6), /* Interrupt on both edges */ - AC_INTMODE_FALLING_gc = (0x02<<6), /* Interrupt on falling edge */ - AC_INTMODE_RISING_gc = (0x03<<6), /* Interrupt on rising edge */ -} AC_INTMODE_t; - -/* Interrupt level */ -typedef enum AC_INTLVL_enum -{ - AC_INTLVL_OFF_gc = (0x00<<4), /* Interrupt disabled */ - AC_INTLVL_LO_gc = (0x01<<4), /* Low level */ - AC_INTLVL_MED_gc = (0x02<<4), /* Medium level */ - AC_INTLVL_HI_gc = (0x03<<4), /* High level */ -} AC_INTLVL_t; - -/* Hysteresis mode selection */ -typedef enum AC_HYSMODE_enum -{ - AC_HYSMODE_NO_gc = (0x00<<1), /* No hysteresis */ - AC_HYSMODE_SMALL_gc = (0x01<<1), /* Small hysteresis */ - AC_HYSMODE_LARGE_gc = (0x02<<1), /* Large hysteresis */ -} AC_HYSMODE_t; - -/* Positive input multiplexer selection */ -typedef enum AC_MUXPOS_enum -{ - AC_MUXPOS_PIN0_gc = (0x00<<3), /* Pin 0 */ - AC_MUXPOS_PIN1_gc = (0x01<<3), /* Pin 1 */ - AC_MUXPOS_PIN2_gc = (0x02<<3), /* Pin 2 */ - AC_MUXPOS_PIN3_gc = (0x03<<3), /* Pin 3 */ - AC_MUXPOS_PIN4_gc = (0x04<<3), /* Pin 4 */ - AC_MUXPOS_PIN5_gc = (0x05<<3), /* Pin 5 */ - AC_MUXPOS_PIN6_gc = (0x06<<3), /* Pin 6 */ - AC_MUXPOS_DAC_gc = (0x07<<3), /* DAC output */ -} AC_MUXPOS_t; - -/* Negative input multiplexer selection */ -typedef enum AC_MUXNEG_enum -{ - AC_MUXNEG_PIN0_gc = (0x00<<0), /* Pin 0 */ - AC_MUXNEG_PIN1_gc = (0x01<<0), /* Pin 1 */ - AC_MUXNEG_PIN3_gc = (0x02<<0), /* Pin 3 */ - AC_MUXNEG_PIN5_gc = (0x03<<0), /* Pin 5 */ - AC_MUXNEG_PIN7_gc = (0x04<<0), /* Pin 7 */ - AC_MUXNEG_DAC_gc = (0x05<<0), /* DAC output */ - AC_MUXNEG_BANDGAP_gc = (0x06<<0), /* Bandgap Reference */ - AC_MUXNEG_SCALER_gc = (0x07<<0), /* Internal voltage scaler */ -} AC_MUXNEG_t; - -/* Windows interrupt mode */ -typedef enum AC_WINTMODE_enum -{ - AC_WINTMODE_ABOVE_gc = (0x00<<2), /* Interrupt on above window */ - AC_WINTMODE_INSIDE_gc = (0x01<<2), /* Interrupt on inside window */ - AC_WINTMODE_BELOW_gc = (0x02<<2), /* Interrupt on below window */ - AC_WINTMODE_OUTSIDE_gc = (0x03<<2), /* Interrupt on outside window */ -} AC_WINTMODE_t; - -/* Window interrupt level */ -typedef enum AC_WINTLVL_enum -{ - AC_WINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ - AC_WINTLVL_LO_gc = (0x01<<0), /* Low priority */ - AC_WINTLVL_MED_gc = (0x02<<0), /* Medium priority */ - AC_WINTLVL_HI_gc = (0x03<<0), /* High priority */ -} AC_WINTLVL_t; - -/* Window mode state */ -typedef enum AC_WSTATE_enum -{ - AC_WSTATE_ABOVE_gc = (0x00<<6), /* Signal above window */ - AC_WSTATE_INSIDE_gc = (0x01<<6), /* Signal inside window */ - AC_WSTATE_BELOW_gc = (0x02<<6), /* Signal below window */ -} AC_WSTATE_t; - - -/* --------------------------------------------------------------------------- -RTC - Real-Time Counter --------------------------------------------------------------------------- -*/ - -/* Real-Time Counter */ -typedef struct RTC_struct -{ - register8_t CTRL; /* Control Register */ - register8_t STATUS; /* Status Register */ - register8_t INTCTRL; /* Interrupt Control Register */ - register8_t INTFLAGS; /* Interrupt Flags */ - register8_t TEMP; /* Temporary register */ - register8_t reserved_0x05; - register8_t reserved_0x06; - register8_t reserved_0x07; - _WORDREGISTER(CNT); /* Count Register */ - _WORDREGISTER(PER); /* Period Register */ - _WORDREGISTER(COMP); /* Compare Register */ -} RTC_t; - -/* Prescaler Factor */ -typedef enum RTC_PRESCALER_enum -{ - RTC_PRESCALER_OFF_gc = (0x00<<0), /* RTC Off */ - RTC_PRESCALER_DIV1_gc = (0x01<<0), /* RTC Clock */ - RTC_PRESCALER_DIV2_gc = (0x02<<0), /* RTC Clock / 2 */ - RTC_PRESCALER_DIV8_gc = (0x03<<0), /* RTC Clock / 8 */ - RTC_PRESCALER_DIV16_gc = (0x04<<0), /* RTC Clock / 16 */ - RTC_PRESCALER_DIV64_gc = (0x05<<0), /* RTC Clock / 64 */ - RTC_PRESCALER_DIV256_gc = (0x06<<0), /* RTC Clock / 256 */ - RTC_PRESCALER_DIV1024_gc = (0x07<<0), /* RTC Clock / 1024 */ -} RTC_PRESCALER_t; - -/* Compare Interrupt level */ -typedef enum RTC_COMPINTLVL_enum -{ - RTC_COMPINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ - RTC_COMPINTLVL_LO_gc = (0x01<<2), /* Low Level */ - RTC_COMPINTLVL_MED_gc = (0x02<<2), /* Medium Level */ - RTC_COMPINTLVL_HI_gc = (0x03<<2), /* High Level */ -} RTC_COMPINTLVL_t; - -/* Overflow Interrupt level */ -typedef enum RTC_OVFINTLVL_enum -{ - RTC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - RTC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ - RTC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ - RTC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ -} RTC_OVFINTLVL_t; - - -/* --------------------------------------------------------------------------- -TWI - Two-Wire Interface --------------------------------------------------------------------------- -*/ - -/* */ -typedef struct TWI_MASTER_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t CTRLC; /* Control Register C */ - register8_t STATUS; /* Status Register */ - register8_t BAUD; /* Baurd Rate Control Register */ - register8_t ADDR; /* Address Register */ - register8_t DATA; /* Data Register */ -} TWI_MASTER_t; - - -/* */ -typedef struct TWI_SLAVE_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t STATUS; /* Status Register */ - register8_t ADDR; /* Address Register */ - register8_t DATA; /* Data Register */ - register8_t ADDRMASK; /* Address Mask Register */ -} TWI_SLAVE_t; - - -/* Two-Wire Interface */ -typedef struct TWI_struct -{ - register8_t CTRL; /* TWI Common Control Register */ - TWI_MASTER_t MASTER; /* TWI master module */ - TWI_SLAVE_t SLAVE; /* TWI slave module */ -} TWI_t; - -/* SDA Hold Time */ -typedef enum TWI_SDAHOLD_enum -{ - TWI_SDAHOLD_OFF_gc = (0x00<<1), /* SDA Hold Time off */ - TWI_SDAHOLD_50NS_gc = (0x01<<1), /* SDA Hold Time 50 ns */ - TWI_SDAHOLD_300NS_gc = (0x02<<1), /* SDA Hold Time 300 ns */ - TWI_SDAHOLD_400NS_gc = (0x03<<1), /* SDA Hold Time 400 ns */ -} TWI_SDAHOLD_t; - -/* Master Interrupt Level */ -typedef enum TWI_MASTER_INTLVL_enum -{ - TWI_MASTER_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ - TWI_MASTER_INTLVL_LO_gc = (0x01<<6), /* Low Level */ - TWI_MASTER_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ - TWI_MASTER_INTLVL_HI_gc = (0x03<<6), /* High Level */ -} TWI_MASTER_INTLVL_t; - -/* Inactive Timeout */ -typedef enum TWI_MASTER_TIMEOUT_enum -{ - TWI_MASTER_TIMEOUT_DISABLED_gc = (0x00<<2), /* Bus Timeout Disabled */ - TWI_MASTER_TIMEOUT_50US_gc = (0x01<<2), /* 50 Microseconds */ - TWI_MASTER_TIMEOUT_100US_gc = (0x02<<2), /* 100 Microseconds */ - TWI_MASTER_TIMEOUT_200US_gc = (0x03<<2), /* 200 Microseconds */ -} TWI_MASTER_TIMEOUT_t; - -/* Master Command */ -typedef enum TWI_MASTER_CMD_enum -{ - TWI_MASTER_CMD_NOACT_gc = (0x00<<0), /* No Action */ - TWI_MASTER_CMD_REPSTART_gc = (0x01<<0), /* Issue Repeated Start Condition */ - TWI_MASTER_CMD_RECVTRANS_gc = (0x02<<0), /* Receive or Transmit Data */ - TWI_MASTER_CMD_STOP_gc = (0x03<<0), /* Issue Stop Condition */ -} TWI_MASTER_CMD_t; - -/* Master Bus State */ -typedef enum TWI_MASTER_BUSSTATE_enum -{ - TWI_MASTER_BUSSTATE_UNKNOWN_gc = (0x00<<0), /* Unknown Bus State */ - TWI_MASTER_BUSSTATE_IDLE_gc = (0x01<<0), /* Bus is Idle */ - TWI_MASTER_BUSSTATE_OWNER_gc = (0x02<<0), /* This Module Controls The Bus */ - TWI_MASTER_BUSSTATE_BUSY_gc = (0x03<<0), /* The Bus is Busy */ -} TWI_MASTER_BUSSTATE_t; - -/* Slave Interrupt Level */ -typedef enum TWI_SLAVE_INTLVL_enum -{ - TWI_SLAVE_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ - TWI_SLAVE_INTLVL_LO_gc = (0x01<<6), /* Low Level */ - TWI_SLAVE_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ - TWI_SLAVE_INTLVL_HI_gc = (0x03<<6), /* High Level */ -} TWI_SLAVE_INTLVL_t; - -/* Slave Command */ -typedef enum TWI_SLAVE_CMD_enum -{ - TWI_SLAVE_CMD_NOACT_gc = (0x00<<0), /* No Action */ - TWI_SLAVE_CMD_COMPTRANS_gc = (0x02<<0), /* Used To Complete a Transaction */ - TWI_SLAVE_CMD_RESPONSE_gc = (0x03<<0), /* Used in Response to Address/Data Interrupt */ -} TWI_SLAVE_CMD_t; - - -/* --------------------------------------------------------------------------- -USB - USB --------------------------------------------------------------------------- -*/ - -/* USB Endpoint */ -typedef struct USB_EP_struct -{ - register8_t STATUS; /* Endpoint Status */ - register8_t CTRL; /* Endpoint Control */ - _WORDREGISTER(CNT); /* USB Endpoint Counter */ - _WORDREGISTER(DATAPTR); /* Data Pointer */ - _WORDREGISTER(AUXDATA); /* Auxiliary Data */ -} USB_EP_t; - - -/* Universal Serial Bus */ -typedef struct USB_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t STATUS; /* Status Register */ - register8_t ADDR; /* Address Register */ - register8_t FIFOWP; /* FIFO Write Pointer Register */ - register8_t FIFORP; /* FIFO Read Pointer Register */ - _WORDREGISTER(EPPTR); /* Endpoint Configuration Table Pointer */ - register8_t INTCTRLA; /* Interrupt Control Register A */ - register8_t INTCTRLB; /* Interrupt Control Register B */ - register8_t INTFLAGSACLR; /* Clear Interrupt Flag Register A */ - register8_t INTFLAGSASET; /* Set Interrupt Flag Register A */ - register8_t INTFLAGSBCLR; /* Clear Interrupt Flag Register B */ - register8_t INTFLAGSBSET; /* Set Interrupt Flag Register B */ - register8_t reserved_0x0E; - register8_t reserved_0x0F; - register8_t reserved_0x10; - register8_t reserved_0x11; - register8_t reserved_0x12; - register8_t reserved_0x13; - register8_t reserved_0x14; - register8_t reserved_0x15; - register8_t reserved_0x16; - register8_t reserved_0x17; - register8_t reserved_0x18; - register8_t reserved_0x19; - register8_t reserved_0x1A; - register8_t reserved_0x1B; - register8_t reserved_0x1C; - register8_t reserved_0x1D; - register8_t reserved_0x1E; - register8_t reserved_0x1F; - register8_t reserved_0x20; - register8_t reserved_0x21; - register8_t reserved_0x22; - register8_t reserved_0x23; - register8_t reserved_0x24; - register8_t reserved_0x25; - register8_t reserved_0x26; - register8_t reserved_0x27; - register8_t reserved_0x28; - register8_t reserved_0x29; - register8_t reserved_0x2A; - register8_t reserved_0x2B; - register8_t reserved_0x2C; - register8_t reserved_0x2D; - register8_t reserved_0x2E; - register8_t reserved_0x2F; - register8_t reserved_0x30; - register8_t reserved_0x31; - register8_t reserved_0x32; - register8_t reserved_0x33; - register8_t reserved_0x34; - register8_t reserved_0x35; - register8_t reserved_0x36; - register8_t reserved_0x37; - register8_t reserved_0x38; - register8_t reserved_0x39; - register8_t CAL0; /* Calibration Byte 0 */ - register8_t CAL1; /* Calibration Byte 1 */ -} USB_t; - - -/* USB Endpoint Table */ -typedef struct USB_EP_TABLE_struct -{ - USB_EP_t EP0OUT; /* Endpoint 0 */ - USB_EP_t EP0IN; /* Endpoint 0 */ - USB_EP_t EP1OUT; /* Endpoint 1 */ - USB_EP_t EP1IN; /* Endpoint 1 */ - USB_EP_t EP2OUT; /* Endpoint 2 */ - USB_EP_t EP2IN; /* Endpoint 2 */ - USB_EP_t EP3OUT; /* Endpoint 3 */ - USB_EP_t EP3IN; /* Endpoint 3 */ - USB_EP_t EP4OUT; /* Endpoint 4 */ - USB_EP_t EP4IN; /* Endpoint 4 */ - USB_EP_t EP5OUT; /* Endpoint 5 */ - USB_EP_t EP5IN; /* Endpoint 5 */ - USB_EP_t EP6OUT; /* Endpoint 6 */ - USB_EP_t EP6IN; /* Endpoint 6 */ - USB_EP_t EP7OUT; /* Endpoint 7 */ - USB_EP_t EP7IN; /* Endpoint 7 */ - USB_EP_t EP8OUT; /* Endpoint 8 */ - USB_EP_t EP8IN; /* Endpoint 8 */ - USB_EP_t EP9OUT; /* Endpoint 9 */ - USB_EP_t EP9IN; /* Endpoint 9 */ - USB_EP_t EP10OUT; /* Endpoint 10 */ - USB_EP_t EP10IN; /* Endpoint 10 */ - USB_EP_t EP11OUT; /* Endpoint 11 */ - USB_EP_t EP11IN; /* Endpoint 11 */ - USB_EP_t EP12OUT; /* Endpoint 12 */ - USB_EP_t EP12IN; /* Endpoint 12 */ - USB_EP_t EP13OUT; /* Endpoint 13 */ - USB_EP_t EP13IN; /* Endpoint 13 */ - USB_EP_t EP14OUT; /* Endpoint 14 */ - USB_EP_t EP14IN; /* Endpoint 14 */ - USB_EP_t EP15OUT; /* Endpoint 15 */ - USB_EP_t EP15IN; /* Endpoint 15 */ - register8_t reserved_0x100; - register8_t reserved_0x101; - register8_t reserved_0x102; - register8_t reserved_0x103; - register8_t reserved_0x104; - register8_t reserved_0x105; - register8_t reserved_0x106; - register8_t reserved_0x107; - register8_t reserved_0x108; - register8_t reserved_0x109; - register8_t reserved_0x10A; - register8_t reserved_0x10B; - register8_t reserved_0x10C; - register8_t reserved_0x10D; - register8_t reserved_0x10E; - register8_t reserved_0x10F; - register8_t FRAMENUML; /* Frame Number Low Byte */ - register8_t FRAMENUMH; /* Frame Number High Byte */ -} USB_EP_TABLE_t; - -/* Interrupt level */ -typedef enum USB_INTLVL_enum -{ - USB_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ - USB_INTLVL_LO_gc = (0x01<<0), /* Low level */ - USB_INTLVL_MED_gc = (0x02<<0), /* Medium level */ - USB_INTLVL_HI_gc = (0x03<<0), /* High level */ -} USB_INTLVL_t; - -/* USB Endpoint Type */ -typedef enum USB_EP_TYPE_enum -{ - USB_EP_TYPE_DISABLE_gc = (0x00<<6), /* Endpoint Disabled */ - USB_EP_TYPE_CONTROL_gc = (0x01<<6), /* Control */ - USB_EP_TYPE_BULK_gc = (0x02<<6), /* Bulk/Interrupt */ - USB_EP_TYPE_ISOCHRONOUS_gc = (0x03<<6), /* Isochronous */ -} USB_EP_TYPE_t; - -/* USB Endpoint Buffersize */ -typedef enum USB_EP_BUFSIZE_enum -{ - USB_EP_BUFSIZE_8_gc = (0x00<<0), /* 8 bytes buffer size */ - USB_EP_BUFSIZE_16_gc = (0x01<<0), /* 16 bytes buffer size */ - USB_EP_BUFSIZE_32_gc = (0x02<<0), /* 32 bytes buffer size */ - USB_EP_BUFSIZE_64_gc = (0x03<<0), /* 64 bytes buffer size */ - USB_EP_BUFSIZE_128_gc = (0x04<<0), /* 128 bytes buffer size */ - USB_EP_BUFSIZE_256_gc = (0x05<<0), /* 256 bytes buffer size */ - USB_EP_BUFSIZE_512_gc = (0x06<<0), /* 512 bytes buffer size */ - USB_EP_BUFSIZE_1023_gc = (0x07<<0), /* 1023 bytes buffer size */ -} USB_EP_BUFSIZE_t; - - -/* --------------------------------------------------------------------------- -PORT - I/O Port Configuration --------------------------------------------------------------------------- -*/ - -/* I/O Ports */ -typedef struct PORT_struct -{ - register8_t DIR; /* I/O Port Data Direction */ - register8_t DIRSET; /* I/O Port Data Direction Set */ - register8_t DIRCLR; /* I/O Port Data Direction Clear */ - register8_t DIRTGL; /* I/O Port Data Direction Toggle */ - register8_t OUT; /* I/O Port Output */ - register8_t OUTSET; /* I/O Port Output Set */ - register8_t OUTCLR; /* I/O Port Output Clear */ - register8_t OUTTGL; /* I/O Port Output Toggle */ - register8_t IN; /* I/O port Input */ - register8_t INTCTRL; /* Interrupt Control Register */ - register8_t INT0MASK; /* Port Interrupt 0 Mask */ - register8_t INT1MASK; /* Port Interrupt 1 Mask */ - register8_t INTFLAGS; /* Interrupt Flag Register */ - register8_t reserved_0x0D; - register8_t REMAP; /* I/O Port Pin Remap Register */ - register8_t reserved_0x0F; - register8_t PIN0CTRL; /* Pin 0 Control Register */ - register8_t PIN1CTRL; /* Pin 1 Control Register */ - register8_t PIN2CTRL; /* Pin 2 Control Register */ - register8_t PIN3CTRL; /* Pin 3 Control Register */ - register8_t PIN4CTRL; /* Pin 4 Control Register */ - register8_t PIN5CTRL; /* Pin 5 Control Register */ - register8_t PIN6CTRL; /* Pin 6 Control Register */ - register8_t PIN7CTRL; /* Pin 7 Control Register */ -} PORT_t; - -/* Port Interrupt 0 Level */ -typedef enum PORT_INT0LVL_enum -{ - PORT_INT0LVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - PORT_INT0LVL_LO_gc = (0x01<<0), /* Low Level */ - PORT_INT0LVL_MED_gc = (0x02<<0), /* Medium Level */ - PORT_INT0LVL_HI_gc = (0x03<<0), /* High Level */ -} PORT_INT0LVL_t; - -/* Port Interrupt 1 Level */ -typedef enum PORT_INT1LVL_enum -{ - PORT_INT1LVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ - PORT_INT1LVL_LO_gc = (0x01<<2), /* Low Level */ - PORT_INT1LVL_MED_gc = (0x02<<2), /* Medium Level */ - PORT_INT1LVL_HI_gc = (0x03<<2), /* High Level */ -} PORT_INT1LVL_t; - -/* Output/Pull Configuration */ -typedef enum PORT_OPC_enum -{ - PORT_OPC_TOTEM_gc = (0x00<<3), /* Totempole */ - PORT_OPC_BUSKEEPER_gc = (0x01<<3), /* Totempole w/ Bus keeper on Input and Output */ - PORT_OPC_PULLDOWN_gc = (0x02<<3), /* Totempole w/ Pull-down on Input */ - PORT_OPC_PULLUP_gc = (0x03<<3), /* Totempole w/ Pull-up on Input */ - PORT_OPC_WIREDOR_gc = (0x04<<3), /* Wired OR */ - PORT_OPC_WIREDAND_gc = (0x05<<3), /* Wired AND */ - PORT_OPC_WIREDORPULL_gc = (0x06<<3), /* Wired OR w/ Pull-down */ - PORT_OPC_WIREDANDPULL_gc = (0x07<<3), /* Wired AND w/ Pull-up */ -} PORT_OPC_t; - -/* Input/Sense Configuration */ -typedef enum PORT_ISC_enum -{ - PORT_ISC_BOTHEDGES_gc = (0x00<<0), /* Sense Both Edges */ - PORT_ISC_RISING_gc = (0x01<<0), /* Sense Rising Edge */ - PORT_ISC_FALLING_gc = (0x02<<0), /* Sense Falling Edge */ - PORT_ISC_LEVEL_gc = (0x03<<0), /* Sense Level (Transparent For Events) */ - PORT_ISC_INPUT_DISABLE_gc = (0x07<<0), /* Disable Digital Input Buffer */ -} PORT_ISC_t; - - -/* --------------------------------------------------------------------------- -TC - 16-bit Timer/Counter With PWM --------------------------------------------------------------------------- -*/ - -/* 16-bit Timer/Counter 0 */ -typedef struct TC0_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t CTRLC; /* Control register C */ - register8_t CTRLD; /* Control Register D */ - register8_t CTRLE; /* Control Register E */ - register8_t reserved_0x05; - register8_t INTCTRLA; /* Interrupt Control Register A */ - register8_t INTCTRLB; /* Interrupt Control Register B */ - register8_t CTRLFCLR; /* Control Register F Clear */ - register8_t CTRLFSET; /* Control Register F Set */ - register8_t CTRLGCLR; /* Control Register G Clear */ - register8_t CTRLGSET; /* Control Register G Set */ - register8_t INTFLAGS; /* Interrupt Flag Register */ - register8_t reserved_0x0D; - register8_t reserved_0x0E; - register8_t TEMP; /* Temporary Register For 16-bit Access */ - register8_t reserved_0x10; - register8_t reserved_0x11; - register8_t reserved_0x12; - register8_t reserved_0x13; - register8_t reserved_0x14; - register8_t reserved_0x15; - register8_t reserved_0x16; - register8_t reserved_0x17; - register8_t reserved_0x18; - register8_t reserved_0x19; - register8_t reserved_0x1A; - register8_t reserved_0x1B; - register8_t reserved_0x1C; - register8_t reserved_0x1D; - register8_t reserved_0x1E; - register8_t reserved_0x1F; - _WORDREGISTER(CNT); /* Count */ - register8_t reserved_0x22; - register8_t reserved_0x23; - register8_t reserved_0x24; - register8_t reserved_0x25; - _WORDREGISTER(PER); /* Period */ - _WORDREGISTER(CCA); /* Compare or Capture A */ - _WORDREGISTER(CCB); /* Compare or Capture B */ - _WORDREGISTER(CCC); /* Compare or Capture C */ - _WORDREGISTER(CCD); /* Compare or Capture D */ - register8_t reserved_0x30; - register8_t reserved_0x31; - register8_t reserved_0x32; - register8_t reserved_0x33; - register8_t reserved_0x34; - register8_t reserved_0x35; - _WORDREGISTER(PERBUF); /* Period Buffer */ - _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ - _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ - _WORDREGISTER(CCCBUF); /* Compare Or Capture C Buffer */ - _WORDREGISTER(CCDBUF); /* Compare Or Capture D Buffer */ -} TC0_t; - - -/* 16-bit Timer/Counter 1 */ -typedef struct TC1_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t CTRLC; /* Control register C */ - register8_t CTRLD; /* Control Register D */ - register8_t CTRLE; /* Control Register E */ - register8_t reserved_0x05; - register8_t INTCTRLA; /* Interrupt Control Register A */ - register8_t INTCTRLB; /* Interrupt Control Register B */ - register8_t CTRLFCLR; /* Control Register F Clear */ - register8_t CTRLFSET; /* Control Register F Set */ - register8_t CTRLGCLR; /* Control Register G Clear */ - register8_t CTRLGSET; /* Control Register G Set */ - register8_t INTFLAGS; /* Interrupt Flag Register */ - register8_t reserved_0x0D; - register8_t reserved_0x0E; - register8_t TEMP; /* Temporary Register For 16-bit Access */ - register8_t reserved_0x10; - register8_t reserved_0x11; - register8_t reserved_0x12; - register8_t reserved_0x13; - register8_t reserved_0x14; - register8_t reserved_0x15; - register8_t reserved_0x16; - register8_t reserved_0x17; - register8_t reserved_0x18; - register8_t reserved_0x19; - register8_t reserved_0x1A; - register8_t reserved_0x1B; - register8_t reserved_0x1C; - register8_t reserved_0x1D; - register8_t reserved_0x1E; - register8_t reserved_0x1F; - _WORDREGISTER(CNT); /* Count */ - register8_t reserved_0x22; - register8_t reserved_0x23; - register8_t reserved_0x24; - register8_t reserved_0x25; - _WORDREGISTER(PER); /* Period */ - _WORDREGISTER(CCA); /* Compare or Capture A */ - _WORDREGISTER(CCB); /* Compare or Capture B */ - register8_t reserved_0x2C; - register8_t reserved_0x2D; - register8_t reserved_0x2E; - register8_t reserved_0x2F; - register8_t reserved_0x30; - register8_t reserved_0x31; - register8_t reserved_0x32; - register8_t reserved_0x33; - register8_t reserved_0x34; - register8_t reserved_0x35; - _WORDREGISTER(PERBUF); /* Period Buffer */ - _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ - _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ -} TC1_t; - -/* Clock Selection */ -typedef enum TC_CLKSEL_enum -{ - TC_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */ - TC_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */ - TC_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */ - TC_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */ - TC_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */ - TC_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */ - TC_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */ - TC_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */ - TC_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */ - TC_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */ - TC_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */ - TC_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */ - TC_CLKSEL_EVCH4_gc = (0x0C<<0), /* Event Channel 4 */ - TC_CLKSEL_EVCH5_gc = (0x0D<<0), /* Event Channel 5 */ - TC_CLKSEL_EVCH6_gc = (0x0E<<0), /* Event Channel 6 */ - TC_CLKSEL_EVCH7_gc = (0x0F<<0), /* Event Channel 7 */ -} TC_CLKSEL_t; - -/* Waveform Generation Mode */ -typedef enum TC_WGMODE_enum -{ - TC_WGMODE_NORMAL_gc = (0x00<<0), /* Normal Mode */ - TC_WGMODE_FRQ_gc = (0x01<<0), /* Frequency Generation Mode */ - TC_WGMODE_SINGLESLOPE_gc = (0x03<<0), /* Single Slope */ - TC_WGMODE_SS_gc = (0x03<<0), /* Single Slope */ - TC_WGMODE_DSTOP_gc = (0x05<<0), /* Dual Slope, Update on TOP */ - TC_WGMODE_DS_T_gc = (0x05<<0), /* Dual Slope, Update on TOP */ - TC_WGMODE_DSBOTH_gc = (0x06<<0), /* Dual Slope, Update on both TOP and BOTTOM */ - TC_WGMODE_DS_TB_gc = (0x06<<0), /* Dual Slope, Update on both TOP and BOTTOM */ - TC_WGMODE_DSBOTTOM_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */ - TC_WGMODE_DS_B_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */ -} TC_WGMODE_t; - -/* Byte Mode */ -typedef enum TC_BYTEM_enum -{ - TC_BYTEM_NORMAL_gc = (0x00<<0), /* 16-bit mode */ - TC_BYTEM_BYTEMODE_gc = (0x01<<0), /* Timer/Counter operating in byte mode only */ - TC_BYTEM_SPLITMODE_gc = (0x02<<0), /* Timer/Counter split into two 8-bit Counters (TC2) */ -} TC_BYTEM_t; - -/* Event Action */ -typedef enum TC_EVACT_enum -{ - TC_EVACT_OFF_gc = (0x00<<5), /* No Event Action */ - TC_EVACT_CAPT_gc = (0x01<<5), /* Input Capture */ - TC_EVACT_UPDOWN_gc = (0x02<<5), /* Externally Controlled Up/Down Count */ - TC_EVACT_QDEC_gc = (0x03<<5), /* Quadrature Decode */ - TC_EVACT_RESTART_gc = (0x04<<5), /* Restart */ - TC_EVACT_FRQ_gc = (0x05<<5), /* Frequency Capture */ - TC_EVACT_PW_gc = (0x06<<5), /* Pulse-width Capture */ -} TC_EVACT_t; - -/* Event Selection */ -typedef enum TC_EVSEL_enum -{ - TC_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ - TC_EVSEL_CH0_gc = (0x08<<0), /* Event Channel 0 */ - TC_EVSEL_CH1_gc = (0x09<<0), /* Event Channel 1 */ - TC_EVSEL_CH2_gc = (0x0A<<0), /* Event Channel 2 */ - TC_EVSEL_CH3_gc = (0x0B<<0), /* Event Channel 3 */ - TC_EVSEL_CH4_gc = (0x0C<<0), /* Event Channel 4 */ - TC_EVSEL_CH5_gc = (0x0D<<0), /* Event Channel 5 */ - TC_EVSEL_CH6_gc = (0x0E<<0), /* Event Channel 6 */ - TC_EVSEL_CH7_gc = (0x0F<<0), /* Event Channel 7 */ -} TC_EVSEL_t; - -/* Error Interrupt Level */ -typedef enum TC_ERRINTLVL_enum -{ - TC_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ - TC_ERRINTLVL_LO_gc = (0x01<<2), /* Low Level */ - TC_ERRINTLVL_MED_gc = (0x02<<2), /* Medium Level */ - TC_ERRINTLVL_HI_gc = (0x03<<2), /* High Level */ -} TC_ERRINTLVL_t; - -/* Overflow Interrupt Level */ -typedef enum TC_OVFINTLVL_enum -{ - TC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - TC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ - TC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ - TC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ -} TC_OVFINTLVL_t; - -/* Compare or Capture D Interrupt Level */ -typedef enum TC_CCDINTLVL_enum -{ - TC_CCDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ - TC_CCDINTLVL_LO_gc = (0x01<<6), /* Low Level */ - TC_CCDINTLVL_MED_gc = (0x02<<6), /* Medium Level */ - TC_CCDINTLVL_HI_gc = (0x03<<6), /* High Level */ -} TC_CCDINTLVL_t; - -/* Compare or Capture C Interrupt Level */ -typedef enum TC_CCCINTLVL_enum -{ - TC_CCCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ - TC_CCCINTLVL_LO_gc = (0x01<<4), /* Low Level */ - TC_CCCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ - TC_CCCINTLVL_HI_gc = (0x03<<4), /* High Level */ -} TC_CCCINTLVL_t; - -/* Compare or Capture B Interrupt Level */ -typedef enum TC_CCBINTLVL_enum -{ - TC_CCBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ - TC_CCBINTLVL_LO_gc = (0x01<<2), /* Low Level */ - TC_CCBINTLVL_MED_gc = (0x02<<2), /* Medium Level */ - TC_CCBINTLVL_HI_gc = (0x03<<2), /* High Level */ -} TC_CCBINTLVL_t; - -/* Compare or Capture A Interrupt Level */ -typedef enum TC_CCAINTLVL_enum -{ - TC_CCAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - TC_CCAINTLVL_LO_gc = (0x01<<0), /* Low Level */ - TC_CCAINTLVL_MED_gc = (0x02<<0), /* Medium Level */ - TC_CCAINTLVL_HI_gc = (0x03<<0), /* High Level */ -} TC_CCAINTLVL_t; - -/* Timer/Counter Command */ -typedef enum TC_CMD_enum -{ - TC_CMD_NONE_gc = (0x00<<2), /* No Command */ - TC_CMD_UPDATE_gc = (0x01<<2), /* Force Update */ - TC_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ - TC_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ -} TC_CMD_t; - - -/* --------------------------------------------------------------------------- -TC2 - 16-bit Timer/Counter type 2 --------------------------------------------------------------------------- -*/ - -/* 16-bit Timer/Counter type 2 */ -typedef struct TC2_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t CTRLC; /* Control register C */ - register8_t reserved_0x03; - register8_t CTRLE; /* Control Register E */ - register8_t reserved_0x05; - register8_t INTCTRLA; /* Interrupt Control Register A */ - register8_t INTCTRLB; /* Interrupt Control Register B */ - register8_t reserved_0x08; - register8_t CTRLF; /* Control Register F */ - register8_t reserved_0x0A; - register8_t reserved_0x0B; - register8_t INTFLAGS; /* Interrupt Flag Register */ - register8_t reserved_0x0D; - register8_t reserved_0x0E; - register8_t reserved_0x0F; - register8_t reserved_0x10; - register8_t reserved_0x11; - register8_t reserved_0x12; - register8_t reserved_0x13; - register8_t reserved_0x14; - register8_t reserved_0x15; - register8_t reserved_0x16; - register8_t reserved_0x17; - register8_t reserved_0x18; - register8_t reserved_0x19; - register8_t reserved_0x1A; - register8_t reserved_0x1B; - register8_t reserved_0x1C; - register8_t reserved_0x1D; - register8_t reserved_0x1E; - register8_t reserved_0x1F; - register8_t LCNT; /* Low Byte Count */ - register8_t HCNT; /* High Byte Count */ - register8_t reserved_0x22; - register8_t reserved_0x23; - register8_t reserved_0x24; - register8_t reserved_0x25; - register8_t LPER; /* Low Byte Period */ - register8_t HPER; /* High Byte Period */ - register8_t LCMPA; /* Low Byte Compare A */ - register8_t HCMPA; /* High Byte Compare A */ - register8_t LCMPB; /* Low Byte Compare B */ - register8_t HCMPB; /* High Byte Compare B */ - register8_t LCMPC; /* Low Byte Compare C */ - register8_t HCMPC; /* High Byte Compare C */ - register8_t LCMPD; /* Low Byte Compare D */ - register8_t HCMPD; /* High Byte Compare D */ -} TC2_t; - -/* Clock Selection */ -typedef enum TC2_CLKSEL_enum -{ - TC2_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */ - TC2_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */ - TC2_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */ - TC2_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */ - TC2_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */ - TC2_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */ - TC2_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */ - TC2_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */ - TC2_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */ - TC2_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */ - TC2_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */ - TC2_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */ - TC2_CLKSEL_EVCH4_gc = (0x0C<<0), /* Event Channel 4 */ - TC2_CLKSEL_EVCH5_gc = (0x0D<<0), /* Event Channel 5 */ - TC2_CLKSEL_EVCH6_gc = (0x0E<<0), /* Event Channel 6 */ - TC2_CLKSEL_EVCH7_gc = (0x0F<<0), /* Event Channel 7 */ -} TC2_CLKSEL_t; - -/* Byte Mode */ -typedef enum TC2_BYTEM_enum -{ - TC2_BYTEM_NORMAL_gc = (0x00<<0), /* 16-bit mode */ - TC2_BYTEM_BYTEMODE_gc = (0x01<<0), /* Timer/Counter operating in byte mode only (TC2) */ - TC2_BYTEM_SPLITMODE_gc = (0x02<<0), /* Timer/Counter split into two 8-bit Counters */ -} TC2_BYTEM_t; - -/* High Byte Underflow Interrupt Level */ -typedef enum TC2_HUNFINTLVL_enum -{ - TC2_HUNFINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ - TC2_HUNFINTLVL_LO_gc = (0x01<<2), /* Low Level */ - TC2_HUNFINTLVL_MED_gc = (0x02<<2), /* Medium Level */ - TC2_HUNFINTLVL_HI_gc = (0x03<<2), /* High Level */ -} TC2_HUNFINTLVL_t; - -/* Low Byte Underflow Interrupt Level */ -typedef enum TC2_LUNFINTLVL_enum -{ - TC2_LUNFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - TC2_LUNFINTLVL_LO_gc = (0x01<<0), /* Low Level */ - TC2_LUNFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ - TC2_LUNFINTLVL_HI_gc = (0x03<<0), /* High Level */ -} TC2_LUNFINTLVL_t; - -/* Low Byte Compare D Interrupt Level */ -typedef enum TC2_LCMPDINTLVL_enum -{ - TC2_LCMPDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ - TC2_LCMPDINTLVL_LO_gc = (0x01<<6), /* Low Level */ - TC2_LCMPDINTLVL_MED_gc = (0x02<<6), /* Medium Level */ - TC2_LCMPDINTLVL_HI_gc = (0x03<<6), /* High Level */ -} TC2_LCMPDINTLVL_t; - -/* Low Byte Compare C Interrupt Level */ -typedef enum TC2_LCMPCINTLVL_enum -{ - TC2_LCMPCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ - TC2_LCMPCINTLVL_LO_gc = (0x01<<4), /* Low Level */ - TC2_LCMPCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ - TC2_LCMPCINTLVL_HI_gc = (0x03<<4), /* High Level */ -} TC2_LCMPCINTLVL_t; - -/* Low Byte Compare B Interrupt Level */ -typedef enum TC2_LCMPBINTLVL_enum -{ - TC2_LCMPBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ - TC2_LCMPBINTLVL_LO_gc = (0x01<<2), /* Low Level */ - TC2_LCMPBINTLVL_MED_gc = (0x02<<2), /* Medium Level */ - TC2_LCMPBINTLVL_HI_gc = (0x03<<2), /* High Level */ -} TC2_LCMPBINTLVL_t; - -/* Low Byte Compare A Interrupt Level */ -typedef enum TC2_LCMPAINTLVL_enum -{ - TC2_LCMPAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - TC2_LCMPAINTLVL_LO_gc = (0x01<<0), /* Low Level */ - TC2_LCMPAINTLVL_MED_gc = (0x02<<0), /* Medium Level */ - TC2_LCMPAINTLVL_HI_gc = (0x03<<0), /* High Level */ -} TC2_LCMPAINTLVL_t; - -/* Timer/Counter Command */ -typedef enum TC2_CMD_enum -{ - TC2_CMD_NONE_gc = (0x00<<2), /* No Command */ - TC2_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ - TC2_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ -} TC2_CMD_t; - -/* Timer/Counter Command */ -typedef enum TC2_CMDEN_enum -{ - TC2_CMDEN_LOW_gc = (0x01<<0), /* Low Byte Timer/Counter */ - TC2_CMDEN_HIGH_gc = (0x02<<0), /* High Byte Timer/Counter */ - TC2_CMDEN_BOTH_gc = (0x03<<0), /* Both Low Byte and High Byte Timer/Counters */ -} TC2_CMDEN_t; - - -/* --------------------------------------------------------------------------- -AWEX - Timer/Counter Advanced Waveform Extension --------------------------------------------------------------------------- -*/ - -/* Advanced Waveform Extension */ -typedef struct AWEX_struct -{ - register8_t CTRL; /* Control Register */ - register8_t reserved_0x01; - register8_t FDEMASK; /* Fault Detection Event Mask */ - register8_t FDCTRL; /* Fault Detection Control Register */ - register8_t STATUS; /* Status Register */ - register8_t STATUSSET; /* Status Set Register */ - register8_t DTBOTH; /* Dead Time Both Sides */ - register8_t DTBOTHBUF; /* Dead Time Both Sides Buffer */ - register8_t DTLS; /* Dead Time Low Side */ - register8_t DTHS; /* Dead Time High Side */ - register8_t DTLSBUF; /* Dead Time Low Side Buffer */ - register8_t DTHSBUF; /* Dead Time High Side Buffer */ - register8_t OUTOVEN; /* Output Override Enable */ -} AWEX_t; - -/* Fault Detect Action */ -typedef enum AWEX_FDACT_enum -{ - AWEX_FDACT_NONE_gc = (0x00<<0), /* No Fault Protection */ - AWEX_FDACT_CLEAROE_gc = (0x01<<0), /* Clear Output Enable Bits */ - AWEX_FDACT_CLEARDIR_gc = (0x03<<0), /* Clear I/O Port Direction Bits */ -} AWEX_FDACT_t; - - -/* --------------------------------------------------------------------------- -HIRES - Timer/Counter High-Resolution Extension --------------------------------------------------------------------------- -*/ - -/* High-Resolution Extension */ -typedef struct HIRES_struct -{ - register8_t CTRLA; /* Control Register */ -} HIRES_t; - -/* High Resolution Enable */ -typedef enum HIRES_HREN_enum -{ - HIRES_HREN_NONE_gc = (0x00<<0), /* No Fault Protection */ - HIRES_HREN_TC0_gc = (0x01<<0), /* Enable High Resolution on Timer/Counter 0 */ - HIRES_HREN_TC1_gc = (0x02<<0), /* Enable High Resolution on Timer/Counter 1 */ - HIRES_HREN_BOTH_gc = (0x03<<0), /* Enable High Resolution both Timer/Counters */ -} HIRES_HREN_t; - - -/* --------------------------------------------------------------------------- -USART - Universal Asynchronous Receiver-Transmitter --------------------------------------------------------------------------- -*/ - -/* Universal Synchronous/Asynchronous Receiver/Transmitter */ -typedef struct USART_struct -{ - register8_t DATA; /* Data Register */ - register8_t STATUS; /* Status Register */ - register8_t reserved_0x02; - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t CTRLC; /* Control Register C */ - register8_t BAUDCTRLA; /* Baud Rate Control Register A */ - register8_t BAUDCTRLB; /* Baud Rate Control Register B */ -} USART_t; - -/* Receive Complete Interrupt level */ -typedef enum USART_RXCINTLVL_enum -{ - USART_RXCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ - USART_RXCINTLVL_LO_gc = (0x01<<4), /* Low Level */ - USART_RXCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ - USART_RXCINTLVL_HI_gc = (0x03<<4), /* High Level */ -} USART_RXCINTLVL_t; - -/* Transmit Complete Interrupt level */ -typedef enum USART_TXCINTLVL_enum -{ - USART_TXCINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ - USART_TXCINTLVL_LO_gc = (0x01<<2), /* Low Level */ - USART_TXCINTLVL_MED_gc = (0x02<<2), /* Medium Level */ - USART_TXCINTLVL_HI_gc = (0x03<<2), /* High Level */ -} USART_TXCINTLVL_t; - -/* Data Register Empty Interrupt level */ -typedef enum USART_DREINTLVL_enum -{ - USART_DREINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - USART_DREINTLVL_LO_gc = (0x01<<0), /* Low Level */ - USART_DREINTLVL_MED_gc = (0x02<<0), /* Medium Level */ - USART_DREINTLVL_HI_gc = (0x03<<0), /* High Level */ -} USART_DREINTLVL_t; - -/* Character Size */ -typedef enum USART_CHSIZE_enum -{ - USART_CHSIZE_5BIT_gc = (0x00<<0), /* Character size: 5 bit */ - USART_CHSIZE_6BIT_gc = (0x01<<0), /* Character size: 6 bit */ - USART_CHSIZE_7BIT_gc = (0x02<<0), /* Character size: 7 bit */ - USART_CHSIZE_8BIT_gc = (0x03<<0), /* Character size: 8 bit */ - USART_CHSIZE_9BIT_gc = (0x07<<0), /* Character size: 9 bit */ -} USART_CHSIZE_t; - -/* Communication Mode */ -typedef enum USART_CMODE_enum -{ - USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6), /* Asynchronous Mode */ - USART_CMODE_SYNCHRONOUS_gc = (0x01<<6), /* Synchronous Mode */ - USART_CMODE_IRDA_gc = (0x02<<6), /* IrDA Mode */ - USART_CMODE_MSPI_gc = (0x03<<6), /* Master SPI Mode */ -} USART_CMODE_t; - -/* Parity Mode */ -typedef enum USART_PMODE_enum -{ - USART_PMODE_DISABLED_gc = (0x00<<4), /* No Parity */ - USART_PMODE_EVEN_gc = (0x02<<4), /* Even Parity */ - USART_PMODE_ODD_gc = (0x03<<4), /* Odd Parity */ -} USART_PMODE_t; - - -/* --------------------------------------------------------------------------- -SPI - Serial Peripheral Interface --------------------------------------------------------------------------- -*/ - -/* Serial Peripheral Interface */ -typedef struct SPI_struct -{ - register8_t CTRL; /* Control Register */ - register8_t INTCTRL; /* Interrupt Control Register */ - register8_t STATUS; /* Status Register */ - register8_t DATA; /* Data Register */ -} SPI_t; - -/* SPI Mode */ -typedef enum SPI_MODE_enum -{ - SPI_MODE_0_gc = (0x00<<2), /* SPI Mode 0 */ - SPI_MODE_1_gc = (0x01<<2), /* SPI Mode 1 */ - SPI_MODE_2_gc = (0x02<<2), /* SPI Mode 2 */ - SPI_MODE_3_gc = (0x03<<2), /* SPI Mode 3 */ -} SPI_MODE_t; - -/* Prescaler setting */ -typedef enum SPI_PRESCALER_enum -{ - SPI_PRESCALER_DIV4_gc = (0x00<<0), /* System Clock / 4 */ - SPI_PRESCALER_DIV16_gc = (0x01<<0), /* System Clock / 16 */ - SPI_PRESCALER_DIV64_gc = (0x02<<0), /* System Clock / 64 */ - SPI_PRESCALER_DIV128_gc = (0x03<<0), /* System Clock / 128 */ -} SPI_PRESCALER_t; - -/* Interrupt level */ -typedef enum SPI_INTLVL_enum -{ - SPI_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - SPI_INTLVL_LO_gc = (0x01<<0), /* Low Level */ - SPI_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ - SPI_INTLVL_HI_gc = (0x03<<0), /* High Level */ -} SPI_INTLVL_t; - - -/* --------------------------------------------------------------------------- -IRCOM - IR Communication Module --------------------------------------------------------------------------- -*/ - -/* IR Communication Module */ -typedef struct IRCOM_struct -{ - register8_t CTRL; /* Control Register */ - register8_t TXPLCTRL; /* IrDA Transmitter Pulse Length Control Register */ - register8_t RXPLCTRL; /* IrDA Receiver Pulse Length Control Register */ -} IRCOM_t; - -/* Event channel selection */ -typedef enum IRDA_EVSEL_enum -{ - IRDA_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ - IRDA_EVSEL_0_gc = (0x08<<0), /* Event Channel 0 */ - IRDA_EVSEL_1_gc = (0x09<<0), /* Event Channel 1 */ - IRDA_EVSEL_2_gc = (0x0A<<0), /* Event Channel 2 */ - IRDA_EVSEL_3_gc = (0x0B<<0), /* Event Channel 3 */ - IRDA_EVSEL_4_gc = (0x0C<<0), /* Event Channel 4 */ - IRDA_EVSEL_5_gc = (0x0D<<0), /* Event Channel 5 */ - IRDA_EVSEL_6_gc = (0x0E<<0), /* Event Channel 6 */ - IRDA_EVSEL_7_gc = (0x0F<<0), /* Event Channel 7 */ -} IRDA_EVSEL_t; - - -/* --------------------------------------------------------------------------- -FUSE - Fuses and Lockbits --------------------------------------------------------------------------- -*/ - -/* Fuses */ -typedef struct NVM_FUSES_struct -{ - register8_t reserved_0x00; - register8_t FUSEBYTE1; /* Watchdog Configuration */ - register8_t FUSEBYTE2; /* Reset Configuration */ - register8_t reserved_0x03; - register8_t FUSEBYTE4; /* Start-up Configuration */ - register8_t FUSEBYTE5; /* EESAVE and BOD Level */ -} NVM_FUSES_t; - -/* Boot Loader Section Reset Vector */ -typedef enum BOOTRST_enum -{ - BOOTRST_BOOTLDR_gc = (0x00<<6), /* Boot Loader Reset */ - BOOTRST_APPLICATION_gc = (0x01<<6), /* Application Reset */ -} BOOTRST_t; - -/* Timer Oscillator pin location */ -typedef enum TOSCSEL_enum -{ - TOSCSEL_ALTERNATE_gc = (0x00<<5), /* TOSC1 / TOSC2 on separate pins */ - TOSCSEL_XTAL_gc = (0x01<<5), /* TOSC1 / TOSC2 shared with XTAL1 / XTAL2 */ -} TOSCSEL_t; - -/* BOD operation */ -typedef enum BOD_enum -{ - BOD_SAMPLED_gc = (0x01<<0), /* BOD enabled in sampled mode */ - BOD_CONTINUOUS_gc = (0x02<<0), /* BOD enabled continuously */ - BOD_DISABLED_gc = (0x03<<0), /* BOD Disabled */ -} BOD_t; - -/* BOD operation */ -typedef enum BODACT_enum -{ - BODACT_SAMPLED_gc = (0x01<<4), /* BOD enabled in sampled mode */ - BODACT_CONTINUOUS_gc = (0x02<<4), /* BOD enabled continuously */ - BODACT_DISABLED_gc = (0x03<<4), /* BOD Disabled */ -} BODACT_t; - -/* Watchdog (Window) Timeout Period */ -typedef enum WD_enum -{ - WD_8CLK_gc = (0x00<<4), /* 8 cycles (8ms @ 3.3V) */ - WD_16CLK_gc = (0x01<<4), /* 16 cycles (16ms @ 3.3V) */ - WD_32CLK_gc = (0x02<<4), /* 32 cycles (32ms @ 3.3V) */ - WD_64CLK_gc = (0x03<<4), /* 64 cycles (64ms @ 3.3V) */ - WD_128CLK_gc = (0x04<<4), /* 128 cycles (0.125s @ 3.3V) */ - WD_256CLK_gc = (0x05<<4), /* 256 cycles (0.25s @ 3.3V) */ - WD_512CLK_gc = (0x06<<4), /* 512 cycles (0.5s @ 3.3V) */ - WD_1KCLK_gc = (0x07<<4), /* 1K cycles (1s @ 3.3V) */ - WD_2KCLK_gc = (0x08<<4), /* 2K cycles (2s @ 3.3V) */ - WD_4KCLK_gc = (0x09<<4), /* 4K cycles (4s @ 3.3V) */ - WD_8KCLK_gc = (0x0A<<4), /* 8K cycles (8s @ 3.3V) */ -} WD_t; - -/* Watchdog (Window) Timeout Period */ -typedef enum WDP_enum -{ - WDP_8CLK_gc = (0x00<<0), /* 8 cycles (8ms @ 3.3V) */ - WDP_16CLK_gc = (0x01<<0), /* 16 cycles (16ms @ 3.3V) */ - WDP_32CLK_gc = (0x02<<0), /* 32 cycles (32ms @ 3.3V) */ - WDP_64CLK_gc = (0x03<<0), /* 64 cycles (64ms @ 3.3V) */ - WDP_128CLK_gc = (0x04<<0), /* 128 cycles (0.125s @ 3.3V) */ - WDP_256CLK_gc = (0x05<<0), /* 256 cycles (0.25s @ 3.3V) */ - WDP_512CLK_gc = (0x06<<0), /* 512 cycles (0.5s @ 3.3V) */ - WDP_1KCLK_gc = (0x07<<0), /* 1K cycles (1s @ 3.3V) */ - WDP_2KCLK_gc = (0x08<<0), /* 2K cycles (2s @ 3.3V) */ - WDP_4KCLK_gc = (0x09<<0), /* 4K cycles (4s @ 3.3V) */ - WDP_8KCLK_gc = (0x0A<<0), /* 8K cycles (8s @ 3.3V) */ -} WDP_t; - -/* Start-up Time */ -typedef enum SUT_enum -{ - SUT_0MS_gc = (0x03<<2), /* 0 ms */ - SUT_4MS_gc = (0x01<<2), /* 4 ms */ - SUT_64MS_gc = (0x00<<2), /* 64 ms */ -} SUT_t; - -/* Brownout Detection Voltage Level */ -typedef enum BODLVL_enum -{ - BODLVL_1V6_gc = (0x07<<0), /* 1.6 V */ - BODLVL_1V8_gc = (0x06<<0), /* 1.8 V */ - BODLVL_2V0_gc = (0x05<<0), /* 2.0 V */ - BODLVL_2V2_gc = (0x04<<0), /* 2.2 V */ - BODLVL_2V4_gc = (0x03<<0), /* 2.4 V */ - BODLVL_2V6_gc = (0x02<<0), /* 2.6 V */ - BODLVL_2V8_gc = (0x01<<0), /* 2.8 V */ - BODLVL_3V0_gc = (0x00<<0), /* 3.0 V */ -} BODLVL_t; - - -/* --------------------------------------------------------------------------- -LOCKBIT - Fuses and Lockbits --------------------------------------------------------------------------- -*/ - -/* Lock Bits */ -typedef struct NVM_LOCKBITS_struct -{ - register8_t LOCK_BITS; /* Lock Bits (Changed from LOCKBITS to avoid avr-libc collision) */ -} NVM_LOCKBITS_t; - -/* Boot lock bits - boot setcion */ -typedef enum FUSE_BLBB_enum -{ - FUSE_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ - FUSE_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ - FUSE_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ - FUSE_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ -} FUSE_BLBB_t; - -/* Boot lock bits - application section */ -typedef enum FUSE_BLBA_enum -{ - FUSE_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ - FUSE_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ - FUSE_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ - FUSE_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ -} FUSE_BLBA_t; - -/* Boot lock bits - application table section */ -typedef enum FUSE_BLBAT_enum -{ - FUSE_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ - FUSE_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ - FUSE_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ - FUSE_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ -} FUSE_BLBAT_t; - -/* Lock bits */ -typedef enum FUSE_LB_enum -{ - FUSE_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ - FUSE_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ - FUSE_LB_NOLOCK_gc = (0x03<<0), /* No locks */ -} FUSE_LB_t; - - -/* --------------------------------------------------------------------------- -SIGROW - Signature Row --------------------------------------------------------------------------- -*/ - -/* Production Signatures */ -typedef struct NVM_PROD_SIGNATURES_struct -{ - register8_t RCOSC2M; /* RCOSC 2 MHz Calibration Value B */ - register8_t RCOSC2MA; /* RCOSC 2 MHz Calibration Value A */ - register8_t RCOSC32K; /* RCOSC 32.768 kHz Calibration Value */ - register8_t RCOSC32M; /* RCOSC 32 MHz Calibration Value B */ - register8_t RCOSC32MA; /* RCOSC 32 MHz Calibration Value A */ - register8_t reserved_0x05; - register8_t reserved_0x06; - register8_t reserved_0x07; - register8_t LOTNUM0; /* Lot Number Byte 0, ASCII */ - register8_t LOTNUM1; /* Lot Number Byte 1, ASCII */ - register8_t LOTNUM2; /* Lot Number Byte 2, ASCII */ - register8_t LOTNUM3; /* Lot Number Byte 3, ASCII */ - register8_t LOTNUM4; /* Lot Number Byte 4, ASCII */ - register8_t LOTNUM5; /* Lot Number Byte 5, ASCII */ - register8_t reserved_0x0E; - register8_t reserved_0x0F; - register8_t WAFNUM; /* Wafer Number */ - register8_t reserved_0x11; - register8_t COORDX0; /* Wafer Coordinate X Byte 0 */ - register8_t COORDX1; /* Wafer Coordinate X Byte 1 */ - register8_t COORDY0; /* Wafer Coordinate Y Byte 0 */ - register8_t COORDY1; /* Wafer Coordinate Y Byte 1 */ - register8_t reserved_0x16; - register8_t reserved_0x17; - register8_t reserved_0x18; - register8_t reserved_0x19; - register8_t USBCAL0; /* USB Calibration Byte 0 */ - register8_t USBCAL1; /* USB Calibration Byte 1 */ - register8_t USBRCOSC; /* USB RCOSC Calibration Value B */ - register8_t USBRCOSCA; /* USB RCOSC Calibration Value A */ - register8_t reserved_0x1E; - register8_t reserved_0x1F; - register8_t ADCACAL0; /* ADCA Calibration Byte 0 */ - register8_t ADCACAL1; /* ADCA Calibration Byte 1 */ - register8_t reserved_0x22; - register8_t reserved_0x23; - register8_t ADCBCAL0; /* ADCB Calibration Byte 0 */ - register8_t ADCBCAL1; /* ADCB Calibration Byte 1 */ - register8_t reserved_0x26; - register8_t reserved_0x27; - register8_t reserved_0x28; - register8_t reserved_0x29; - register8_t reserved_0x2A; - register8_t reserved_0x2B; - register8_t reserved_0x2C; - register8_t reserved_0x2D; - register8_t TEMPSENSE0; /* Temperature Sensor Calibration Byte 0 */ - register8_t TEMPSENSE1; /* Temperature Sensor Calibration Byte 1 */ - register8_t DACA0OFFCAL; /* DACA0 Calibration Byte 0 */ - register8_t DACA0GAINCAL; /* DACA0 Calibration Byte 1 */ - register8_t DACB0OFFCAL; /* DACB0 Calibration Byte 0 */ - register8_t DACB0GAINCAL; /* DACB0 Calibration Byte 1 */ - register8_t DACA1OFFCAL; /* DACA1 Calibration Byte 0 */ - register8_t DACA1GAINCAL; /* DACA1 Calibration Byte 1 */ - register8_t DACB1OFFCAL; /* DACB1 Calibration Byte 0 */ - register8_t DACB1GAINCAL; /* DACB1 Calibration Byte 1 */ - register8_t reserved_0x38; - register8_t reserved_0x39; - register8_t reserved_0x3A; - register8_t reserved_0x3B; - register8_t reserved_0x3C; - register8_t reserved_0x3D; - register8_t reserved_0x3E; - register8_t reserved_0x3F; - register8_t reserved_0x40; - register8_t reserved_0x41; - register8_t reserved_0x42; - register8_t reserved_0x43; - register8_t reserved_0x44; - register8_t reserved_0x45; - register8_t reserved_0x46; - register8_t reserved_0x47; -} NVM_PROD_SIGNATURES_t; - -/* -========================================================================== -IO Module Instances. Mapped to memory. -========================================================================== -*/ - -#define VPORT0 (*(VPORT_t *) 0x0010) /* Virtual Port */ -#define VPORT1 (*(VPORT_t *) 0x0014) /* Virtual Port */ -#define VPORT2 (*(VPORT_t *) 0x0018) /* Virtual Port */ -#define VPORT3 (*(VPORT_t *) 0x001C) /* Virtual Port */ -#define OCD (*(OCD_t *) 0x002E) /* On-Chip Debug System */ -#define CLK (*(CLK_t *) 0x0040) /* Clock System */ -#define SLEEP (*(SLEEP_t *) 0x0048) /* Sleep Controller */ -#define OSC (*(OSC_t *) 0x0050) /* Oscillator */ -#define DFLLRC32M (*(DFLL_t *) 0x0060) /* DFLL */ -#define DFLLRC2M (*(DFLL_t *) 0x0068) /* DFLL */ -#define PR (*(PR_t *) 0x0070) /* Power Reduction */ -#define RST (*(RST_t *) 0x0078) /* Reset */ -#define WDT (*(WDT_t *) 0x0080) /* Watch-Dog Timer */ -#define MCU (*(MCU_t *) 0x0090) /* MCU Control */ -#define PMIC (*(PMIC_t *) 0x00A0) /* Programmable Multi-level Interrupt Controller */ -#define PORTCFG (*(PORTCFG_t *) 0x00B0) /* I/O port Configuration */ -#define AES (*(AES_t *) 0x00C0) /* AES Module */ -#define CRC (*(CRC_t *) 0x00D0) /* Cyclic Redundancy Checker */ -#define DMA (*(DMA_t *) 0x0100) /* DMA Controller */ -#define EVSYS (*(EVSYS_t *) 0x0180) /* Event System */ -#define NVM (*(NVM_t *) 0x01C0) /* Non-volatile Memory Controller */ -#define ADCA (*(ADC_t *) 0x0200) /* Analog-to-Digital Converter */ -#define DACB (*(DAC_t *) 0x0320) /* Digital-to-Analog Converter */ -#define ACA (*(AC_t *) 0x0380) /* Analog Comparator */ -#define RTC (*(RTC_t *) 0x0400) /* Real-Time Counter */ -#define TWIC (*(TWI_t *) 0x0480) /* Two-Wire Interface */ -#define TWIE (*(TWI_t *) 0x04A0) /* Two-Wire Interface */ -#define USB (*(USB_t *) 0x04C0) /* Universal Serial Bus */ -#define PORTA (*(PORT_t *) 0x0600) /* I/O Ports */ -#define PORTB (*(PORT_t *) 0x0620) /* I/O Ports */ -#define PORTC (*(PORT_t *) 0x0640) /* I/O Ports */ -#define PORTD (*(PORT_t *) 0x0660) /* I/O Ports */ -#define PORTE (*(PORT_t *) 0x0680) /* I/O Ports */ -#define PORTR (*(PORT_t *) 0x07E0) /* I/O Ports */ -#define TCC0 (*(TC0_t *) 0x0800) /* 16-bit Timer/Counter 0 */ -#define TCC2 (*(TC2_t *) 0x0800) /* 16-bit Timer/Counter type 2 */ -#define TCC1 (*(TC1_t *) 0x0840) /* 16-bit Timer/Counter 1 */ -#define AWEXC (*(AWEX_t *) 0x0880) /* Advanced Waveform Extension */ -#define HIRESC (*(HIRES_t *) 0x0890) /* High-Resolution Extension */ -#define USARTC0 (*(USART_t *) 0x08A0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ -#define USARTC1 (*(USART_t *) 0x08B0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ -#define SPIC (*(SPI_t *) 0x08C0) /* Serial Peripheral Interface */ -#define IRCOM (*(IRCOM_t *) 0x08F8) /* IR Communication Module */ -#define TCD0 (*(TC0_t *) 0x0900) /* 16-bit Timer/Counter 0 */ -#define TCD2 (*(TC2_t *) 0x0900) /* 16-bit Timer/Counter type 2 */ -#define TCD1 (*(TC1_t *) 0x0940) /* 16-bit Timer/Counter 1 */ -#define HIRESD (*(HIRES_t *) 0x0990) /* High-Resolution Extension */ -#define USARTD0 (*(USART_t *) 0x09A0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ -#define USARTD1 (*(USART_t *) 0x09B0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ -#define SPID (*(SPI_t *) 0x09C0) /* Serial Peripheral Interface */ -#define TCE0 (*(TC0_t *) 0x0A00) /* 16-bit Timer/Counter 0 */ -#define HIRESE (*(HIRES_t *) 0x0A90) /* High-Resolution Extension */ -#define USARTE0 (*(USART_t *) 0x0AA0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ - - -#endif /* !defined (__ASSEMBLER__) */ - - -/* ========== Flattened fully qualified IO register names ========== */ - -/* GPIO - General Purpose IO Registers */ -#define GPIO_GPIOR0 _SFR_MEM8(0x0000) -#define GPIO_GPIOR1 _SFR_MEM8(0x0001) -#define GPIO_GPIOR2 _SFR_MEM8(0x0002) -#define GPIO_GPIOR3 _SFR_MEM8(0x0003) -#define GPIO_GPIOR4 _SFR_MEM8(0x0004) -#define GPIO_GPIOR5 _SFR_MEM8(0x0005) -#define GPIO_GPIOR6 _SFR_MEM8(0x0006) -#define GPIO_GPIOR7 _SFR_MEM8(0x0007) -#define GPIO_GPIOR8 _SFR_MEM8(0x0008) -#define GPIO_GPIOR9 _SFR_MEM8(0x0009) -#define GPIO_GPIORA _SFR_MEM8(0x000A) -#define GPIO_GPIORB _SFR_MEM8(0x000B) -#define GPIO_GPIORC _SFR_MEM8(0x000C) -#define GPIO_GPIORD _SFR_MEM8(0x000D) -#define GPIO_GPIORE _SFR_MEM8(0x000E) -#define GPIO_GPIORF _SFR_MEM8(0x000F) - -/* Deprecated */ -#define GPIO_GPIO0 _SFR_MEM8(0x0000) -#define GPIO_GPIO1 _SFR_MEM8(0x0001) -#define GPIO_GPIO2 _SFR_MEM8(0x0002) -#define GPIO_GPIO3 _SFR_MEM8(0x0003) -#define GPIO_GPIO4 _SFR_MEM8(0x0004) -#define GPIO_GPIO5 _SFR_MEM8(0x0005) -#define GPIO_GPIO6 _SFR_MEM8(0x0006) -#define GPIO_GPIO7 _SFR_MEM8(0x0007) -#define GPIO_GPIO8 _SFR_MEM8(0x0008) -#define GPIO_GPIO9 _SFR_MEM8(0x0009) -#define GPIO_GPIOA _SFR_MEM8(0x000A) -#define GPIO_GPIOB _SFR_MEM8(0x000B) -#define GPIO_GPIOC _SFR_MEM8(0x000C) -#define GPIO_GPIOD _SFR_MEM8(0x000D) -#define GPIO_GPIOE _SFR_MEM8(0x000E) -#define GPIO_GPIOF _SFR_MEM8(0x000F) - -/* NVM_FUSES - Fuses */ -#define FUSE_FUSEBYTE1 _SFR_MEM8(0x0001) -#define FUSE_FUSEBYTE2 _SFR_MEM8(0x0002) -#define FUSE_FUSEBYTE4 _SFR_MEM8(0x0004) -#define FUSE_FUSEBYTE5 _SFR_MEM8(0x0005) - -/* NVM_LOCKBITS - Lock Bits */ -#define LOCKBIT_LOCKBITS _SFR_MEM8(0x0000) - -/* NVM_PROD_SIGNATURES - Production Signatures */ -#define PRODSIGNATURES_RCOSC2M _SFR_MEM8(0x0000) -#define PRODSIGNATURES_RCOSC2MA _SFR_MEM8(0x0001) -#define PRODSIGNATURES_RCOSC32K _SFR_MEM8(0x0002) -#define PRODSIGNATURES_RCOSC32M _SFR_MEM8(0x0003) -#define PRODSIGNATURES_RCOSC32MA _SFR_MEM8(0x0004) -#define PRODSIGNATURES_LOTNUM0 _SFR_MEM8(0x0008) -#define PRODSIGNATURES_LOTNUM1 _SFR_MEM8(0x0009) -#define PRODSIGNATURES_LOTNUM2 _SFR_MEM8(0x000A) -#define PRODSIGNATURES_LOTNUM3 _SFR_MEM8(0x000B) -#define PRODSIGNATURES_LOTNUM4 _SFR_MEM8(0x000C) -#define PRODSIGNATURES_LOTNUM5 _SFR_MEM8(0x000D) -#define PRODSIGNATURES_WAFNUM _SFR_MEM8(0x0010) -#define PRODSIGNATURES_COORDX0 _SFR_MEM8(0x0012) -#define PRODSIGNATURES_COORDX1 _SFR_MEM8(0x0013) -#define PRODSIGNATURES_COORDY0 _SFR_MEM8(0x0014) -#define PRODSIGNATURES_COORDY1 _SFR_MEM8(0x0015) -#define PRODSIGNATURES_USBCAL0 _SFR_MEM8(0x001A) -#define PRODSIGNATURES_USBCAL1 _SFR_MEM8(0x001B) -#define PRODSIGNATURES_USBRCOSC _SFR_MEM8(0x001C) -#define PRODSIGNATURES_USBRCOSCA _SFR_MEM8(0x001D) -#define PRODSIGNATURES_ADCACAL0 _SFR_MEM8(0x0020) -#define PRODSIGNATURES_ADCACAL1 _SFR_MEM8(0x0021) -#define PRODSIGNATURES_ADCBCAL0 _SFR_MEM8(0x0024) -#define PRODSIGNATURES_ADCBCAL1 _SFR_MEM8(0x0025) -#define PRODSIGNATURES_TEMPSENSE0 _SFR_MEM8(0x002E) -#define PRODSIGNATURES_TEMPSENSE1 _SFR_MEM8(0x002F) -#define PRODSIGNATURES_DACA0OFFCAL _SFR_MEM8(0x0030) -#define PRODSIGNATURES_DACA0GAINCAL _SFR_MEM8(0x0031) -#define PRODSIGNATURES_DACB0OFFCAL _SFR_MEM8(0x0032) -#define PRODSIGNATURES_DACB0GAINCAL _SFR_MEM8(0x0033) -#define PRODSIGNATURES_DACA1OFFCAL _SFR_MEM8(0x0034) -#define PRODSIGNATURES_DACA1GAINCAL _SFR_MEM8(0x0035) -#define PRODSIGNATURES_DACB1OFFCAL _SFR_MEM8(0x0036) -#define PRODSIGNATURES_DACB1GAINCAL _SFR_MEM8(0x0037) - -/* VPORT - Virtual Port */ -#define VPORT0_DIR _SFR_MEM8(0x0010) -#define VPORT0_OUT _SFR_MEM8(0x0011) -#define VPORT0_IN _SFR_MEM8(0x0012) -#define VPORT0_INTFLAGS _SFR_MEM8(0x0013) - -/* VPORT - Virtual Port */ -#define VPORT1_DIR _SFR_MEM8(0x0014) -#define VPORT1_OUT _SFR_MEM8(0x0015) -#define VPORT1_IN _SFR_MEM8(0x0016) -#define VPORT1_INTFLAGS _SFR_MEM8(0x0017) - -/* VPORT - Virtual Port */ -#define VPORT2_DIR _SFR_MEM8(0x0018) -#define VPORT2_OUT _SFR_MEM8(0x0019) -#define VPORT2_IN _SFR_MEM8(0x001A) -#define VPORT2_INTFLAGS _SFR_MEM8(0x001B) - -/* VPORT - Virtual Port */ -#define VPORT3_DIR _SFR_MEM8(0x001C) -#define VPORT3_OUT _SFR_MEM8(0x001D) -#define VPORT3_IN _SFR_MEM8(0x001E) -#define VPORT3_INTFLAGS _SFR_MEM8(0x001F) - -/* OCD - On-Chip Debug System */ -#define OCD_OCDR0 _SFR_MEM8(0x002E) -#define OCD_OCDR1 _SFR_MEM8(0x002F) - -/* CPU - CPU registers */ -#define CPU_CCP _SFR_MEM8(0x0034) -#define CPU_RAMPD _SFR_MEM8(0x0038) -#define CPU_RAMPX _SFR_MEM8(0x0039) -#define CPU_RAMPY _SFR_MEM8(0x003A) -#define CPU_RAMPZ _SFR_MEM8(0x003B) -#define CPU_EIND _SFR_MEM8(0x003C) -#define CPU_SPL _SFR_MEM8(0x003D) -#define CPU_SPH _SFR_MEM8(0x003E) -#define CPU_SREG _SFR_MEM8(0x003F) - -/* CLK - Clock System */ -#define CLK_CTRL _SFR_MEM8(0x0040) -#define CLK_PSCTRL _SFR_MEM8(0x0041) -#define CLK_LOCK _SFR_MEM8(0x0042) -#define CLK_RTCCTRL _SFR_MEM8(0x0043) -#define CLK_USBCTRL _SFR_MEM8(0x0044) - -/* SLEEP - Sleep Controller */ -#define SLEEP_CTRL _SFR_MEM8(0x0048) - -/* OSC - Oscillator */ -#define OSC_CTRL _SFR_MEM8(0x0050) -#define OSC_STATUS _SFR_MEM8(0x0051) -#define OSC_XOSCCTRL _SFR_MEM8(0x0052) -#define OSC_XOSCFAIL _SFR_MEM8(0x0053) -#define OSC_RC32KCAL _SFR_MEM8(0x0054) -#define OSC_PLLCTRL _SFR_MEM8(0x0055) -#define OSC_DFLLCTRL _SFR_MEM8(0x0056) - -/* DFLL - DFLL */ -#define DFLLRC32M_CTRL _SFR_MEM8(0x0060) -#define DFLLRC32M_CALA _SFR_MEM8(0x0062) -#define DFLLRC32M_CALB _SFR_MEM8(0x0063) -#define DFLLRC32M_COMP0 _SFR_MEM8(0x0064) -#define DFLLRC32M_COMP1 _SFR_MEM8(0x0065) -#define DFLLRC32M_COMP2 _SFR_MEM8(0x0066) - -/* DFLL - DFLL */ -#define DFLLRC2M_CTRL _SFR_MEM8(0x0068) -#define DFLLRC2M_CALA _SFR_MEM8(0x006A) -#define DFLLRC2M_CALB _SFR_MEM8(0x006B) -#define DFLLRC2M_COMP0 _SFR_MEM8(0x006C) -#define DFLLRC2M_COMP1 _SFR_MEM8(0x006D) -#define DFLLRC2M_COMP2 _SFR_MEM8(0x006E) - -/* PR - Power Reduction */ -#define PR_PRGEN _SFR_MEM8(0x0070) -#define PR_PRPA _SFR_MEM8(0x0071) -#define PR_PRPB _SFR_MEM8(0x0072) -#define PR_PRPC _SFR_MEM8(0x0073) -#define PR_PRPD _SFR_MEM8(0x0074) -#define PR_PRPE _SFR_MEM8(0x0075) -#define PR_PRPF _SFR_MEM8(0x0076) - -/* RST - Reset */ -#define RST_STATUS _SFR_MEM8(0x0078) -#define RST_CTRL _SFR_MEM8(0x0079) - -/* WDT - Watch-Dog Timer */ -#define WDT_CTRL _SFR_MEM8(0x0080) -#define WDT_WINCTRL _SFR_MEM8(0x0081) -#define WDT_STATUS _SFR_MEM8(0x0082) - -/* MCU - MCU Control */ -#define MCU_DEVID0 _SFR_MEM8(0x0090) -#define MCU_DEVID1 _SFR_MEM8(0x0091) -#define MCU_DEVID2 _SFR_MEM8(0x0092) -#define MCU_REVID _SFR_MEM8(0x0093) -#define MCU_JTAGUID _SFR_MEM8(0x0094) -#define MCU_MCUCR _SFR_MEM8(0x0096) -#define MCU_ANAINIT _SFR_MEM8(0x0097) -#define MCU_EVSYSLOCK _SFR_MEM8(0x0098) -#define MCU_AWEXLOCK _SFR_MEM8(0x0099) - -/* PMIC - Programmable Multi-level Interrupt Controller */ -#define PMIC_STATUS _SFR_MEM8(0x00A0) -#define PMIC_INTPRI _SFR_MEM8(0x00A1) -#define PMIC_CTRL _SFR_MEM8(0x00A2) - -/* PORTCFG - I/O port Configuration */ -#define PORTCFG_MPCMASK _SFR_MEM8(0x00B0) -#define PORTCFG_VPCTRLA _SFR_MEM8(0x00B2) -#define PORTCFG_VPCTRLB _SFR_MEM8(0x00B3) -#define PORTCFG_CLKEVOUT _SFR_MEM8(0x00B4) -#define PORTCFG_EBIOUT _SFR_MEM8(0x00B5) -#define PORTCFG_EVOUTSEL _SFR_MEM8(0x00B6) - -/* AES - AES Module */ -#define AES_CTRL _SFR_MEM8(0x00C0) -#define AES_STATUS _SFR_MEM8(0x00C1) -#define AES_STATE _SFR_MEM8(0x00C2) -#define AES_KEY _SFR_MEM8(0x00C3) -#define AES_INTCTRL _SFR_MEM8(0x00C4) - -/* CRC - Cyclic Redundancy Checker */ -#define CRC_CTRL _SFR_MEM8(0x00D0) -#define CRC_STATUS _SFR_MEM8(0x00D1) -#define CRC_DATAIN _SFR_MEM8(0x00D3) -#define CRC_CHECKSUM0 _SFR_MEM8(0x00D4) -#define CRC_CHECKSUM1 _SFR_MEM8(0x00D5) -#define CRC_CHECKSUM2 _SFR_MEM8(0x00D6) -#define CRC_CHECKSUM3 _SFR_MEM8(0x00D7) - -/* DMA - DMA Controller */ -#define DMA_CTRL _SFR_MEM8(0x0100) -#define DMA_INTFLAGS _SFR_MEM8(0x0103) -#define DMA_STATUS _SFR_MEM8(0x0104) -#define DMA_TEMP _SFR_MEM16(0x0106) -#define DMA_CH0_CTRLA _SFR_MEM8(0x0110) -#define DMA_CH0_CTRLB _SFR_MEM8(0x0111) -#define DMA_CH0_ADDRCTRL _SFR_MEM8(0x0112) -#define DMA_CH0_TRIGSRC _SFR_MEM8(0x0113) -#define DMA_CH0_TRFCNT _SFR_MEM16(0x0114) -#define DMA_CH0_REPCNT _SFR_MEM8(0x0116) -#define DMA_CH0_SRCADDR0 _SFR_MEM8(0x0118) -#define DMA_CH0_SRCADDR1 _SFR_MEM8(0x0119) -#define DMA_CH0_SRCADDR2 _SFR_MEM8(0x011A) -#define DMA_CH0_DESTADDR0 _SFR_MEM8(0x011C) -#define DMA_CH0_DESTADDR1 _SFR_MEM8(0x011D) -#define DMA_CH0_DESTADDR2 _SFR_MEM8(0x011E) -#define DMA_CH1_CTRLA _SFR_MEM8(0x0120) -#define DMA_CH1_CTRLB _SFR_MEM8(0x0121) -#define DMA_CH1_ADDRCTRL _SFR_MEM8(0x0122) -#define DMA_CH1_TRIGSRC _SFR_MEM8(0x0123) -#define DMA_CH1_TRFCNT _SFR_MEM16(0x0124) -#define DMA_CH1_REPCNT _SFR_MEM8(0x0126) -#define DMA_CH1_SRCADDR0 _SFR_MEM8(0x0128) -#define DMA_CH1_SRCADDR1 _SFR_MEM8(0x0129) -#define DMA_CH1_SRCADDR2 _SFR_MEM8(0x012A) -#define DMA_CH1_DESTADDR0 _SFR_MEM8(0x012C) -#define DMA_CH1_DESTADDR1 _SFR_MEM8(0x012D) -#define DMA_CH1_DESTADDR2 _SFR_MEM8(0x012E) -#define DMA_CH2_CTRLA _SFR_MEM8(0x0130) -#define DMA_CH2_CTRLB _SFR_MEM8(0x0131) -#define DMA_CH2_ADDRCTRL _SFR_MEM8(0x0132) -#define DMA_CH2_TRIGSRC _SFR_MEM8(0x0133) -#define DMA_CH2_TRFCNT _SFR_MEM16(0x0134) -#define DMA_CH2_REPCNT _SFR_MEM8(0x0136) -#define DMA_CH2_SRCADDR0 _SFR_MEM8(0x0138) -#define DMA_CH2_SRCADDR1 _SFR_MEM8(0x0139) -#define DMA_CH2_SRCADDR2 _SFR_MEM8(0x013A) -#define DMA_CH2_DESTADDR0 _SFR_MEM8(0x013C) -#define DMA_CH2_DESTADDR1 _SFR_MEM8(0x013D) -#define DMA_CH2_DESTADDR2 _SFR_MEM8(0x013E) -#define DMA_CH3_CTRLA _SFR_MEM8(0x0140) -#define DMA_CH3_CTRLB _SFR_MEM8(0x0141) -#define DMA_CH3_ADDRCTRL _SFR_MEM8(0x0142) -#define DMA_CH3_TRIGSRC _SFR_MEM8(0x0143) -#define DMA_CH3_TRFCNT _SFR_MEM16(0x0144) -#define DMA_CH3_REPCNT _SFR_MEM8(0x0146) -#define DMA_CH3_SRCADDR0 _SFR_MEM8(0x0148) -#define DMA_CH3_SRCADDR1 _SFR_MEM8(0x0149) -#define DMA_CH3_SRCADDR2 _SFR_MEM8(0x014A) -#define DMA_CH3_DESTADDR0 _SFR_MEM8(0x014C) -#define DMA_CH3_DESTADDR1 _SFR_MEM8(0x014D) -#define DMA_CH3_DESTADDR2 _SFR_MEM8(0x014E) - -/* EVSYS - Event System */ -#define EVSYS_CH0MUX _SFR_MEM8(0x0180) -#define EVSYS_CH1MUX _SFR_MEM8(0x0181) -#define EVSYS_CH2MUX _SFR_MEM8(0x0182) -#define EVSYS_CH3MUX _SFR_MEM8(0x0183) -#define EVSYS_CH4MUX _SFR_MEM8(0x0184) -#define EVSYS_CH5MUX _SFR_MEM8(0x0185) -#define EVSYS_CH6MUX _SFR_MEM8(0x0186) -#define EVSYS_CH7MUX _SFR_MEM8(0x0187) -#define EVSYS_CH0CTRL _SFR_MEM8(0x0188) -#define EVSYS_CH1CTRL _SFR_MEM8(0x0189) -#define EVSYS_CH2CTRL _SFR_MEM8(0x018A) -#define EVSYS_CH3CTRL _SFR_MEM8(0x018B) -#define EVSYS_CH4CTRL _SFR_MEM8(0x018C) -#define EVSYS_CH5CTRL _SFR_MEM8(0x018D) -#define EVSYS_CH6CTRL _SFR_MEM8(0x018E) -#define EVSYS_CH7CTRL _SFR_MEM8(0x018F) -#define EVSYS_STROBE _SFR_MEM8(0x0190) -#define EVSYS_DATA _SFR_MEM8(0x0191) - -/* NVM - Non-volatile Memory Controller */ -#define NVM_ADDR0 _SFR_MEM8(0x01C0) -#define NVM_ADDR1 _SFR_MEM8(0x01C1) -#define NVM_ADDR2 _SFR_MEM8(0x01C2) -#define NVM_DATA0 _SFR_MEM8(0x01C4) -#define NVM_DATA1 _SFR_MEM8(0x01C5) -#define NVM_DATA2 _SFR_MEM8(0x01C6) -#define NVM_CMD _SFR_MEM8(0x01CA) -#define NVM_CTRLA _SFR_MEM8(0x01CB) -#define NVM_CTRLB _SFR_MEM8(0x01CC) -#define NVM_INTCTRL _SFR_MEM8(0x01CD) -#define NVM_STATUS _SFR_MEM8(0x01CF) -#define NVM_LOCKBITS _SFR_MEM8(0x01D0) - -/* ADC - Analog-to-Digital Converter */ -#define ADCA_CTRLA _SFR_MEM8(0x0200) -#define ADCA_CTRLB _SFR_MEM8(0x0201) -#define ADCA_REFCTRL _SFR_MEM8(0x0202) -#define ADCA_EVCTRL _SFR_MEM8(0x0203) -#define ADCA_PRESCALER _SFR_MEM8(0x0204) -#define ADCA_INTFLAGS _SFR_MEM8(0x0206) -#define ADCA_TEMP _SFR_MEM8(0x0207) -#define ADCA_CAL _SFR_MEM16(0x020C) -#define ADCA_CH0RES _SFR_MEM16(0x0210) -#define ADCA_CH1RES _SFR_MEM16(0x0212) -#define ADCA_CH2RES _SFR_MEM16(0x0214) -#define ADCA_CH3RES _SFR_MEM16(0x0216) -#define ADCA_CMP _SFR_MEM16(0x0218) -#define ADCA_CH0_CTRL _SFR_MEM8(0x0220) -#define ADCA_CH0_MUXCTRL _SFR_MEM8(0x0221) -#define ADCA_CH0_INTCTRL _SFR_MEM8(0x0222) -#define ADCA_CH0_INTFLAGS _SFR_MEM8(0x0223) -#define ADCA_CH0_RES _SFR_MEM16(0x0224) -#define ADCA_CH0_SCAN _SFR_MEM8(0x0226) -#define ADCA_CH1_CTRL _SFR_MEM8(0x0228) -#define ADCA_CH1_MUXCTRL _SFR_MEM8(0x0229) -#define ADCA_CH1_INTCTRL _SFR_MEM8(0x022A) -#define ADCA_CH1_INTFLAGS _SFR_MEM8(0x022B) -#define ADCA_CH1_RES _SFR_MEM16(0x022C) -#define ADCA_CH1_SCAN _SFR_MEM8(0x022E) -#define ADCA_CH2_CTRL _SFR_MEM8(0x0230) -#define ADCA_CH2_MUXCTRL _SFR_MEM8(0x0231) -#define ADCA_CH2_INTCTRL _SFR_MEM8(0x0232) -#define ADCA_CH2_INTFLAGS _SFR_MEM8(0x0233) -#define ADCA_CH2_RES _SFR_MEM16(0x0234) -#define ADCA_CH2_SCAN _SFR_MEM8(0x0236) -#define ADCA_CH3_CTRL _SFR_MEM8(0x0238) -#define ADCA_CH3_MUXCTRL _SFR_MEM8(0x0239) -#define ADCA_CH3_INTCTRL _SFR_MEM8(0x023A) -#define ADCA_CH3_INTFLAGS _SFR_MEM8(0x023B) -#define ADCA_CH3_RES _SFR_MEM16(0x023C) -#define ADCA_CH3_SCAN _SFR_MEM8(0x023E) - -/* DAC - Digital-to-Analog Converter */ -#define DACB_CTRLA _SFR_MEM8(0x0320) -#define DACB_CTRLB _SFR_MEM8(0x0321) -#define DACB_CTRLC _SFR_MEM8(0x0322) -#define DACB_EVCTRL _SFR_MEM8(0x0323) -#define DACB_STATUS _SFR_MEM8(0x0325) -#define DACB_CH0GAINCAL _SFR_MEM8(0x0328) -#define DACB_CH0OFFSETCAL _SFR_MEM8(0x0329) -#define DACB_CH1GAINCAL _SFR_MEM8(0x032A) -#define DACB_CH1OFFSETCAL _SFR_MEM8(0x032B) -#define DACB_CH0DATA _SFR_MEM16(0x0338) -#define DACB_CH1DATA _SFR_MEM16(0x033A) - -/* AC - Analog Comparator */ -#define ACA_AC0CTRL _SFR_MEM8(0x0380) -#define ACA_AC1CTRL _SFR_MEM8(0x0381) -#define ACA_AC0MUXCTRL _SFR_MEM8(0x0382) -#define ACA_AC1MUXCTRL _SFR_MEM8(0x0383) -#define ACA_CTRLA _SFR_MEM8(0x0384) -#define ACA_CTRLB _SFR_MEM8(0x0385) -#define ACA_WINCTRL _SFR_MEM8(0x0386) -#define ACA_STATUS _SFR_MEM8(0x0387) - -/* RTC - Real-Time Counter */ -#define RTC_CTRL _SFR_MEM8(0x0400) -#define RTC_STATUS _SFR_MEM8(0x0401) -#define RTC_INTCTRL _SFR_MEM8(0x0402) -#define RTC_INTFLAGS _SFR_MEM8(0x0403) -#define RTC_TEMP _SFR_MEM8(0x0404) -#define RTC_CNT _SFR_MEM16(0x0408) -#define RTC_PER _SFR_MEM16(0x040A) -#define RTC_COMP _SFR_MEM16(0x040C) - -/* TWI - Two-Wire Interface */ -#define TWIC_CTRL _SFR_MEM8(0x0480) -#define TWIC_MASTER_CTRLA _SFR_MEM8(0x0481) -#define TWIC_MASTER_CTRLB _SFR_MEM8(0x0482) -#define TWIC_MASTER_CTRLC _SFR_MEM8(0x0483) -#define TWIC_MASTER_STATUS _SFR_MEM8(0x0484) -#define TWIC_MASTER_BAUD _SFR_MEM8(0x0485) -#define TWIC_MASTER_ADDR _SFR_MEM8(0x0486) -#define TWIC_MASTER_DATA _SFR_MEM8(0x0487) -#define TWIC_SLAVE_CTRLA _SFR_MEM8(0x0488) -#define TWIC_SLAVE_CTRLB _SFR_MEM8(0x0489) -#define TWIC_SLAVE_STATUS _SFR_MEM8(0x048A) -#define TWIC_SLAVE_ADDR _SFR_MEM8(0x048B) -#define TWIC_SLAVE_DATA _SFR_MEM8(0x048C) -#define TWIC_SLAVE_ADDRMASK _SFR_MEM8(0x048D) - -/* TWI - Two-Wire Interface */ -#define TWIE_CTRL _SFR_MEM8(0x04A0) -#define TWIE_MASTER_CTRLA _SFR_MEM8(0x04A1) -#define TWIE_MASTER_CTRLB _SFR_MEM8(0x04A2) -#define TWIE_MASTER_CTRLC _SFR_MEM8(0x04A3) -#define TWIE_MASTER_STATUS _SFR_MEM8(0x04A4) -#define TWIE_MASTER_BAUD _SFR_MEM8(0x04A5) -#define TWIE_MASTER_ADDR _SFR_MEM8(0x04A6) -#define TWIE_MASTER_DATA _SFR_MEM8(0x04A7) -#define TWIE_SLAVE_CTRLA _SFR_MEM8(0x04A8) -#define TWIE_SLAVE_CTRLB _SFR_MEM8(0x04A9) -#define TWIE_SLAVE_STATUS _SFR_MEM8(0x04AA) -#define TWIE_SLAVE_ADDR _SFR_MEM8(0x04AB) -#define TWIE_SLAVE_DATA _SFR_MEM8(0x04AC) -#define TWIE_SLAVE_ADDRMASK _SFR_MEM8(0x04AD) - -/* USB - Universal Serial Bus */ -#define USB_CTRLA _SFR_MEM8(0x04C0) -#define USB_CTRLB _SFR_MEM8(0x04C1) -#define USB_STATUS _SFR_MEM8(0x04C2) -#define USB_ADDR _SFR_MEM8(0x04C3) -#define USB_FIFOWP _SFR_MEM8(0x04C4) -#define USB_FIFORP _SFR_MEM8(0x04C5) -#define USB_EPPTR _SFR_MEM16(0x04C6) -#define USB_INTCTRLA _SFR_MEM8(0x04C8) -#define USB_INTCTRLB _SFR_MEM8(0x04C9) -#define USB_INTFLAGSACLR _SFR_MEM8(0x04CA) -#define USB_INTFLAGSASET _SFR_MEM8(0x04CB) -#define USB_INTFLAGSBCLR _SFR_MEM8(0x04CC) -#define USB_INTFLAGSBSET _SFR_MEM8(0x04CD) -#define USB_CAL0 _SFR_MEM8(0x04FA) -#define USB_CAL1 _SFR_MEM8(0x04FB) - -/* PORT - I/O Ports */ -#define PORTA_DIR _SFR_MEM8(0x0600) -#define PORTA_DIRSET _SFR_MEM8(0x0601) -#define PORTA_DIRCLR _SFR_MEM8(0x0602) -#define PORTA_DIRTGL _SFR_MEM8(0x0603) -#define PORTA_OUT _SFR_MEM8(0x0604) -#define PORTA_OUTSET _SFR_MEM8(0x0605) -#define PORTA_OUTCLR _SFR_MEM8(0x0606) -#define PORTA_OUTTGL _SFR_MEM8(0x0607) -#define PORTA_IN _SFR_MEM8(0x0608) -#define PORTA_INTCTRL _SFR_MEM8(0x0609) -#define PORTA_INT0MASK _SFR_MEM8(0x060A) -#define PORTA_INT1MASK _SFR_MEM8(0x060B) -#define PORTA_INTFLAGS _SFR_MEM8(0x060C) -#define PORTA_REMAP _SFR_MEM8(0x060E) -#define PORTA_PIN0CTRL _SFR_MEM8(0x0610) -#define PORTA_PIN1CTRL _SFR_MEM8(0x0611) -#define PORTA_PIN2CTRL _SFR_MEM8(0x0612) -#define PORTA_PIN3CTRL _SFR_MEM8(0x0613) -#define PORTA_PIN4CTRL _SFR_MEM8(0x0614) -#define PORTA_PIN5CTRL _SFR_MEM8(0x0615) -#define PORTA_PIN6CTRL _SFR_MEM8(0x0616) -#define PORTA_PIN7CTRL _SFR_MEM8(0x0617) - -/* PORT - I/O Ports */ -#define PORTB_DIR _SFR_MEM8(0x0620) -#define PORTB_DIRSET _SFR_MEM8(0x0621) -#define PORTB_DIRCLR _SFR_MEM8(0x0622) -#define PORTB_DIRTGL _SFR_MEM8(0x0623) -#define PORTB_OUT _SFR_MEM8(0x0624) -#define PORTB_OUTSET _SFR_MEM8(0x0625) -#define PORTB_OUTCLR _SFR_MEM8(0x0626) -#define PORTB_OUTTGL _SFR_MEM8(0x0627) -#define PORTB_IN _SFR_MEM8(0x0628) -#define PORTB_INTCTRL _SFR_MEM8(0x0629) -#define PORTB_INT0MASK _SFR_MEM8(0x062A) -#define PORTB_INT1MASK _SFR_MEM8(0x062B) -#define PORTB_INTFLAGS _SFR_MEM8(0x062C) -#define PORTB_REMAP _SFR_MEM8(0x062E) -#define PORTB_PIN0CTRL _SFR_MEM8(0x0630) -#define PORTB_PIN1CTRL _SFR_MEM8(0x0631) -#define PORTB_PIN2CTRL _SFR_MEM8(0x0632) -#define PORTB_PIN3CTRL _SFR_MEM8(0x0633) -#define PORTB_PIN4CTRL _SFR_MEM8(0x0634) -#define PORTB_PIN5CTRL _SFR_MEM8(0x0635) -#define PORTB_PIN6CTRL _SFR_MEM8(0x0636) -#define PORTB_PIN7CTRL _SFR_MEM8(0x0637) - -/* PORT - I/O Ports */ -#define PORTC_DIR _SFR_MEM8(0x0640) -#define PORTC_DIRSET _SFR_MEM8(0x0641) -#define PORTC_DIRCLR _SFR_MEM8(0x0642) -#define PORTC_DIRTGL _SFR_MEM8(0x0643) -#define PORTC_OUT _SFR_MEM8(0x0644) -#define PORTC_OUTSET _SFR_MEM8(0x0645) -#define PORTC_OUTCLR _SFR_MEM8(0x0646) -#define PORTC_OUTTGL _SFR_MEM8(0x0647) -#define PORTC_IN _SFR_MEM8(0x0648) -#define PORTC_INTCTRL _SFR_MEM8(0x0649) -#define PORTC_INT0MASK _SFR_MEM8(0x064A) -#define PORTC_INT1MASK _SFR_MEM8(0x064B) -#define PORTC_INTFLAGS _SFR_MEM8(0x064C) -#define PORTC_REMAP _SFR_MEM8(0x064E) -#define PORTC_PIN0CTRL _SFR_MEM8(0x0650) -#define PORTC_PIN1CTRL _SFR_MEM8(0x0651) -#define PORTC_PIN2CTRL _SFR_MEM8(0x0652) -#define PORTC_PIN3CTRL _SFR_MEM8(0x0653) -#define PORTC_PIN4CTRL _SFR_MEM8(0x0654) -#define PORTC_PIN5CTRL _SFR_MEM8(0x0655) -#define PORTC_PIN6CTRL _SFR_MEM8(0x0656) -#define PORTC_PIN7CTRL _SFR_MEM8(0x0657) - -/* PORT - I/O Ports */ -#define PORTD_DIR _SFR_MEM8(0x0660) -#define PORTD_DIRSET _SFR_MEM8(0x0661) -#define PORTD_DIRCLR _SFR_MEM8(0x0662) -#define PORTD_DIRTGL _SFR_MEM8(0x0663) -#define PORTD_OUT _SFR_MEM8(0x0664) -#define PORTD_OUTSET _SFR_MEM8(0x0665) -#define PORTD_OUTCLR _SFR_MEM8(0x0666) -#define PORTD_OUTTGL _SFR_MEM8(0x0667) -#define PORTD_IN _SFR_MEM8(0x0668) -#define PORTD_INTCTRL _SFR_MEM8(0x0669) -#define PORTD_INT0MASK _SFR_MEM8(0x066A) -#define PORTD_INT1MASK _SFR_MEM8(0x066B) -#define PORTD_INTFLAGS _SFR_MEM8(0x066C) -#define PORTD_REMAP _SFR_MEM8(0x066E) -#define PORTD_PIN0CTRL _SFR_MEM8(0x0670) -#define PORTD_PIN1CTRL _SFR_MEM8(0x0671) -#define PORTD_PIN2CTRL _SFR_MEM8(0x0672) -#define PORTD_PIN3CTRL _SFR_MEM8(0x0673) -#define PORTD_PIN4CTRL _SFR_MEM8(0x0674) -#define PORTD_PIN5CTRL _SFR_MEM8(0x0675) -#define PORTD_PIN6CTRL _SFR_MEM8(0x0676) -#define PORTD_PIN7CTRL _SFR_MEM8(0x0677) - -/* PORT - I/O Ports */ -#define PORTE_DIR _SFR_MEM8(0x0680) -#define PORTE_DIRSET _SFR_MEM8(0x0681) -#define PORTE_DIRCLR _SFR_MEM8(0x0682) -#define PORTE_DIRTGL _SFR_MEM8(0x0683) -#define PORTE_OUT _SFR_MEM8(0x0684) -#define PORTE_OUTSET _SFR_MEM8(0x0685) -#define PORTE_OUTCLR _SFR_MEM8(0x0686) -#define PORTE_OUTTGL _SFR_MEM8(0x0687) -#define PORTE_IN _SFR_MEM8(0x0688) -#define PORTE_INTCTRL _SFR_MEM8(0x0689) -#define PORTE_INT0MASK _SFR_MEM8(0x068A) -#define PORTE_INT1MASK _SFR_MEM8(0x068B) -#define PORTE_INTFLAGS _SFR_MEM8(0x068C) -#define PORTE_REMAP _SFR_MEM8(0x068E) -#define PORTE_PIN0CTRL _SFR_MEM8(0x0690) -#define PORTE_PIN1CTRL _SFR_MEM8(0x0691) -#define PORTE_PIN2CTRL _SFR_MEM8(0x0692) -#define PORTE_PIN3CTRL _SFR_MEM8(0x0693) -#define PORTE_PIN4CTRL _SFR_MEM8(0x0694) -#define PORTE_PIN5CTRL _SFR_MEM8(0x0695) -#define PORTE_PIN6CTRL _SFR_MEM8(0x0696) -#define PORTE_PIN7CTRL _SFR_MEM8(0x0697) - -/* PORT - I/O Ports */ -#define PORTR_DIR _SFR_MEM8(0x07E0) -#define PORTR_DIRSET _SFR_MEM8(0x07E1) -#define PORTR_DIRCLR _SFR_MEM8(0x07E2) -#define PORTR_DIRTGL _SFR_MEM8(0x07E3) -#define PORTR_OUT _SFR_MEM8(0x07E4) -#define PORTR_OUTSET _SFR_MEM8(0x07E5) -#define PORTR_OUTCLR _SFR_MEM8(0x07E6) -#define PORTR_OUTTGL _SFR_MEM8(0x07E7) -#define PORTR_IN _SFR_MEM8(0x07E8) -#define PORTR_INTCTRL _SFR_MEM8(0x07E9) -#define PORTR_INT0MASK _SFR_MEM8(0x07EA) -#define PORTR_INT1MASK _SFR_MEM8(0x07EB) -#define PORTR_INTFLAGS _SFR_MEM8(0x07EC) -#define PORTR_REMAP _SFR_MEM8(0x07EE) -#define PORTR_PIN0CTRL _SFR_MEM8(0x07F0) -#define PORTR_PIN1CTRL _SFR_MEM8(0x07F1) -#define PORTR_PIN2CTRL _SFR_MEM8(0x07F2) -#define PORTR_PIN3CTRL _SFR_MEM8(0x07F3) -#define PORTR_PIN4CTRL _SFR_MEM8(0x07F4) -#define PORTR_PIN5CTRL _SFR_MEM8(0x07F5) -#define PORTR_PIN6CTRL _SFR_MEM8(0x07F6) -#define PORTR_PIN7CTRL _SFR_MEM8(0x07F7) - -/* TC0 - 16-bit Timer/Counter 0 */ -#define TCC0_CTRLA _SFR_MEM8(0x0800) -#define TCC0_CTRLB _SFR_MEM8(0x0801) -#define TCC0_CTRLC _SFR_MEM8(0x0802) -#define TCC0_CTRLD _SFR_MEM8(0x0803) -#define TCC0_CTRLE _SFR_MEM8(0x0804) -#define TCC0_INTCTRLA _SFR_MEM8(0x0806) -#define TCC0_INTCTRLB _SFR_MEM8(0x0807) -#define TCC0_CTRLFCLR _SFR_MEM8(0x0808) -#define TCC0_CTRLFSET _SFR_MEM8(0x0809) -#define TCC0_CTRLGCLR _SFR_MEM8(0x080A) -#define TCC0_CTRLGSET _SFR_MEM8(0x080B) -#define TCC0_INTFLAGS _SFR_MEM8(0x080C) -#define TCC0_TEMP _SFR_MEM8(0x080F) -#define TCC0_CNT _SFR_MEM16(0x0820) -#define TCC0_PER _SFR_MEM16(0x0826) -#define TCC0_CCA _SFR_MEM16(0x0828) -#define TCC0_CCB _SFR_MEM16(0x082A) -#define TCC0_CCC _SFR_MEM16(0x082C) -#define TCC0_CCD _SFR_MEM16(0x082E) -#define TCC0_PERBUF _SFR_MEM16(0x0836) -#define TCC0_CCABUF _SFR_MEM16(0x0838) -#define TCC0_CCBBUF _SFR_MEM16(0x083A) -#define TCC0_CCCBUF _SFR_MEM16(0x083C) -#define TCC0_CCDBUF _SFR_MEM16(0x083E) - -/* TC2 - 16-bit Timer/Counter type 2 */ -#define TCC2_CTRLA _SFR_MEM8(0x0800) -#define TCC2_CTRLB _SFR_MEM8(0x0801) -#define TCC2_CTRLC _SFR_MEM8(0x0802) -#define TCC2_CTRLE _SFR_MEM8(0x0804) -#define TCC2_INTCTRLA _SFR_MEM8(0x0806) -#define TCC2_INTCTRLB _SFR_MEM8(0x0807) -#define TCC2_CTRLF _SFR_MEM8(0x0809) -#define TCC2_INTFLAGS _SFR_MEM8(0x080C) -#define TCC2_LCNT _SFR_MEM8(0x0820) -#define TCC2_HCNT _SFR_MEM8(0x0821) -#define TCC2_LPER _SFR_MEM8(0x0826) -#define TCC2_HPER _SFR_MEM8(0x0827) -#define TCC2_LCMPA _SFR_MEM8(0x0828) -#define TCC2_HCMPA _SFR_MEM8(0x0829) -#define TCC2_LCMPB _SFR_MEM8(0x082A) -#define TCC2_HCMPB _SFR_MEM8(0x082B) -#define TCC2_LCMPC _SFR_MEM8(0x082C) -#define TCC2_HCMPC _SFR_MEM8(0x082D) -#define TCC2_LCMPD _SFR_MEM8(0x082E) -#define TCC2_HCMPD _SFR_MEM8(0x082F) - -/* TC1 - 16-bit Timer/Counter 1 */ -#define TCC1_CTRLA _SFR_MEM8(0x0840) -#define TCC1_CTRLB _SFR_MEM8(0x0841) -#define TCC1_CTRLC _SFR_MEM8(0x0842) -#define TCC1_CTRLD _SFR_MEM8(0x0843) -#define TCC1_CTRLE _SFR_MEM8(0x0844) -#define TCC1_INTCTRLA _SFR_MEM8(0x0846) -#define TCC1_INTCTRLB _SFR_MEM8(0x0847) -#define TCC1_CTRLFCLR _SFR_MEM8(0x0848) -#define TCC1_CTRLFSET _SFR_MEM8(0x0849) -#define TCC1_CTRLGCLR _SFR_MEM8(0x084A) -#define TCC1_CTRLGSET _SFR_MEM8(0x084B) -#define TCC1_INTFLAGS _SFR_MEM8(0x084C) -#define TCC1_TEMP _SFR_MEM8(0x084F) -#define TCC1_CNT _SFR_MEM16(0x0860) -#define TCC1_PER _SFR_MEM16(0x0866) -#define TCC1_CCA _SFR_MEM16(0x0868) -#define TCC1_CCB _SFR_MEM16(0x086A) -#define TCC1_PERBUF _SFR_MEM16(0x0876) -#define TCC1_CCABUF _SFR_MEM16(0x0878) -#define TCC1_CCBBUF _SFR_MEM16(0x087A) - -/* AWEX - Advanced Waveform Extension */ -#define AWEXC_CTRL _SFR_MEM8(0x0880) -#define AWEXC_FDEMASK _SFR_MEM8(0x0882) -#define AWEXC_FDCTRL _SFR_MEM8(0x0883) -#define AWEXC_STATUS _SFR_MEM8(0x0884) -#define AWEXC_STATUSSET _SFR_MEM8(0x0885) -#define AWEXC_DTBOTH _SFR_MEM8(0x0886) -#define AWEXC_DTBOTHBUF _SFR_MEM8(0x0887) -#define AWEXC_DTLS _SFR_MEM8(0x0888) -#define AWEXC_DTHS _SFR_MEM8(0x0889) -#define AWEXC_DTLSBUF _SFR_MEM8(0x088A) -#define AWEXC_DTHSBUF _SFR_MEM8(0x088B) -#define AWEXC_OUTOVEN _SFR_MEM8(0x088C) - -/* HIRES - High-Resolution Extension */ -#define HIRESC_CTRLA _SFR_MEM8(0x0890) - -/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ -#define USARTC0_DATA _SFR_MEM8(0x08A0) -#define USARTC0_STATUS _SFR_MEM8(0x08A1) -#define USARTC0_CTRLA _SFR_MEM8(0x08A3) -#define USARTC0_CTRLB _SFR_MEM8(0x08A4) -#define USARTC0_CTRLC _SFR_MEM8(0x08A5) -#define USARTC0_BAUDCTRLA _SFR_MEM8(0x08A6) -#define USARTC0_BAUDCTRLB _SFR_MEM8(0x08A7) - -/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ -#define USARTC1_DATA _SFR_MEM8(0x08B0) -#define USARTC1_STATUS _SFR_MEM8(0x08B1) -#define USARTC1_CTRLA _SFR_MEM8(0x08B3) -#define USARTC1_CTRLB _SFR_MEM8(0x08B4) -#define USARTC1_CTRLC _SFR_MEM8(0x08B5) -#define USARTC1_BAUDCTRLA _SFR_MEM8(0x08B6) -#define USARTC1_BAUDCTRLB _SFR_MEM8(0x08B7) - -/* SPI - Serial Peripheral Interface */ -#define SPIC_CTRL _SFR_MEM8(0x08C0) -#define SPIC_INTCTRL _SFR_MEM8(0x08C1) -#define SPIC_STATUS _SFR_MEM8(0x08C2) -#define SPIC_DATA _SFR_MEM8(0x08C3) - -/* IRCOM - IR Communication Module */ -#define IRCOM_CTRL _SFR_MEM8(0x08F8) -#define IRCOM_TXPLCTRL _SFR_MEM8(0x08F9) -#define IRCOM_RXPLCTRL _SFR_MEM8(0x08FA) - -/* TC0 - 16-bit Timer/Counter 0 */ -#define TCD0_CTRLA _SFR_MEM8(0x0900) -#define TCD0_CTRLB _SFR_MEM8(0x0901) -#define TCD0_CTRLC _SFR_MEM8(0x0902) -#define TCD0_CTRLD _SFR_MEM8(0x0903) -#define TCD0_CTRLE _SFR_MEM8(0x0904) -#define TCD0_INTCTRLA _SFR_MEM8(0x0906) -#define TCD0_INTCTRLB _SFR_MEM8(0x0907) -#define TCD0_CTRLFCLR _SFR_MEM8(0x0908) -#define TCD0_CTRLFSET _SFR_MEM8(0x0909) -#define TCD0_CTRLGCLR _SFR_MEM8(0x090A) -#define TCD0_CTRLGSET _SFR_MEM8(0x090B) -#define TCD0_INTFLAGS _SFR_MEM8(0x090C) -#define TCD0_TEMP _SFR_MEM8(0x090F) -#define TCD0_CNT _SFR_MEM16(0x0920) -#define TCD0_PER _SFR_MEM16(0x0926) -#define TCD0_CCA _SFR_MEM16(0x0928) -#define TCD0_CCB _SFR_MEM16(0x092A) -#define TCD0_CCC _SFR_MEM16(0x092C) -#define TCD0_CCD _SFR_MEM16(0x092E) -#define TCD0_PERBUF _SFR_MEM16(0x0936) -#define TCD0_CCABUF _SFR_MEM16(0x0938) -#define TCD0_CCBBUF _SFR_MEM16(0x093A) -#define TCD0_CCCBUF _SFR_MEM16(0x093C) -#define TCD0_CCDBUF _SFR_MEM16(0x093E) - -/* TC2 - 16-bit Timer/Counter type 2 */ -#define TCD2_CTRLA _SFR_MEM8(0x0900) -#define TCD2_CTRLB _SFR_MEM8(0x0901) -#define TCD2_CTRLC _SFR_MEM8(0x0902) -#define TCD2_CTRLE _SFR_MEM8(0x0904) -#define TCD2_INTCTRLA _SFR_MEM8(0x0906) -#define TCD2_INTCTRLB _SFR_MEM8(0x0907) -#define TCD2_CTRLF _SFR_MEM8(0x0909) -#define TCD2_INTFLAGS _SFR_MEM8(0x090C) -#define TCD2_LCNT _SFR_MEM8(0x0920) -#define TCD2_HCNT _SFR_MEM8(0x0921) -#define TCD2_LPER _SFR_MEM8(0x0926) -#define TCD2_HPER _SFR_MEM8(0x0927) -#define TCD2_LCMPA _SFR_MEM8(0x0928) -#define TCD2_HCMPA _SFR_MEM8(0x0929) -#define TCD2_LCMPB _SFR_MEM8(0x092A) -#define TCD2_HCMPB _SFR_MEM8(0x092B) -#define TCD2_LCMPC _SFR_MEM8(0x092C) -#define TCD2_HCMPC _SFR_MEM8(0x092D) -#define TCD2_LCMPD _SFR_MEM8(0x092E) -#define TCD2_HCMPD _SFR_MEM8(0x092F) - -/* TC1 - 16-bit Timer/Counter 1 */ -#define TCD1_CTRLA _SFR_MEM8(0x0940) -#define TCD1_CTRLB _SFR_MEM8(0x0941) -#define TCD1_CTRLC _SFR_MEM8(0x0942) -#define TCD1_CTRLD _SFR_MEM8(0x0943) -#define TCD1_CTRLE _SFR_MEM8(0x0944) -#define TCD1_INTCTRLA _SFR_MEM8(0x0946) -#define TCD1_INTCTRLB _SFR_MEM8(0x0947) -#define TCD1_CTRLFCLR _SFR_MEM8(0x0948) -#define TCD1_CTRLFSET _SFR_MEM8(0x0949) -#define TCD1_CTRLGCLR _SFR_MEM8(0x094A) -#define TCD1_CTRLGSET _SFR_MEM8(0x094B) -#define TCD1_INTFLAGS _SFR_MEM8(0x094C) -#define TCD1_TEMP _SFR_MEM8(0x094F) -#define TCD1_CNT _SFR_MEM16(0x0960) -#define TCD1_PER _SFR_MEM16(0x0966) -#define TCD1_CCA _SFR_MEM16(0x0968) -#define TCD1_CCB _SFR_MEM16(0x096A) -#define TCD1_PERBUF _SFR_MEM16(0x0976) -#define TCD1_CCABUF _SFR_MEM16(0x0978) -#define TCD1_CCBBUF _SFR_MEM16(0x097A) - -/* HIRES - High-Resolution Extension */ -#define HIRESD_CTRLA _SFR_MEM8(0x0990) - -/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ -#define USARTD0_DATA _SFR_MEM8(0x09A0) -#define USARTD0_STATUS _SFR_MEM8(0x09A1) -#define USARTD0_CTRLA _SFR_MEM8(0x09A3) -#define USARTD0_CTRLB _SFR_MEM8(0x09A4) -#define USARTD0_CTRLC _SFR_MEM8(0x09A5) -#define USARTD0_BAUDCTRLA _SFR_MEM8(0x09A6) -#define USARTD0_BAUDCTRLB _SFR_MEM8(0x09A7) - -/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ -#define USARTD1_DATA _SFR_MEM8(0x09B0) -#define USARTD1_STATUS _SFR_MEM8(0x09B1) -#define USARTD1_CTRLA _SFR_MEM8(0x09B3) -#define USARTD1_CTRLB _SFR_MEM8(0x09B4) -#define USARTD1_CTRLC _SFR_MEM8(0x09B5) -#define USARTD1_BAUDCTRLA _SFR_MEM8(0x09B6) -#define USARTD1_BAUDCTRLB _SFR_MEM8(0x09B7) - -/* SPI - Serial Peripheral Interface */ -#define SPID_CTRL _SFR_MEM8(0x09C0) -#define SPID_INTCTRL _SFR_MEM8(0x09C1) -#define SPID_STATUS _SFR_MEM8(0x09C2) -#define SPID_DATA _SFR_MEM8(0x09C3) - -/* TC0 - 16-bit Timer/Counter 0 */ -#define TCE0_CTRLA _SFR_MEM8(0x0A00) -#define TCE0_CTRLB _SFR_MEM8(0x0A01) -#define TCE0_CTRLC _SFR_MEM8(0x0A02) -#define TCE0_CTRLD _SFR_MEM8(0x0A03) -#define TCE0_CTRLE _SFR_MEM8(0x0A04) -#define TCE0_INTCTRLA _SFR_MEM8(0x0A06) -#define TCE0_INTCTRLB _SFR_MEM8(0x0A07) -#define TCE0_CTRLFCLR _SFR_MEM8(0x0A08) -#define TCE0_CTRLFSET _SFR_MEM8(0x0A09) -#define TCE0_CTRLGCLR _SFR_MEM8(0x0A0A) -#define TCE0_CTRLGSET _SFR_MEM8(0x0A0B) -#define TCE0_INTFLAGS _SFR_MEM8(0x0A0C) -#define TCE0_TEMP _SFR_MEM8(0x0A0F) -#define TCE0_CNT _SFR_MEM16(0x0A20) -#define TCE0_PER _SFR_MEM16(0x0A26) -#define TCE0_CCA _SFR_MEM16(0x0A28) -#define TCE0_CCB _SFR_MEM16(0x0A2A) -#define TCE0_CCC _SFR_MEM16(0x0A2C) -#define TCE0_CCD _SFR_MEM16(0x0A2E) -#define TCE0_PERBUF _SFR_MEM16(0x0A36) -#define TCE0_CCABUF _SFR_MEM16(0x0A38) -#define TCE0_CCBBUF _SFR_MEM16(0x0A3A) -#define TCE0_CCCBUF _SFR_MEM16(0x0A3C) -#define TCE0_CCDBUF _SFR_MEM16(0x0A3E) - -/* HIRES - High-Resolution Extension */ -#define HIRESE_CTRLA _SFR_MEM8(0x0A90) - -/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ -#define USARTE0_DATA _SFR_MEM8(0x0AA0) -#define USARTE0_STATUS _SFR_MEM8(0x0AA1) -#define USARTE0_CTRLA _SFR_MEM8(0x0AA3) -#define USARTE0_CTRLB _SFR_MEM8(0x0AA4) -#define USARTE0_CTRLC _SFR_MEM8(0x0AA5) -#define USARTE0_BAUDCTRLA _SFR_MEM8(0x0AA6) -#define USARTE0_BAUDCTRLB _SFR_MEM8(0x0AA7) - - - -/*================== Bitfield Definitions ================== */ - -/* VPORT - Virtual Ports */ -/* VPORT.INTFLAGS bit masks and bit positions */ -#define VPORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ -#define VPORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ - -#define VPORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ -#define VPORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ - -/* XOCD - On-Chip Debug System */ -/* OCD.OCDR0 bit masks and bit positions */ -#define OCD_OCDRD_gm 0xFF /* OCDR Dirty group mask. */ -#define OCD_OCDRD_gp 0 /* OCDR Dirty group position. */ -#define OCD_OCDRD0_bm (1<<0) /* OCDR Dirty bit 0 mask. */ -#define OCD_OCDRD0_bp 0 /* OCDR Dirty bit 0 position. */ -#define OCD_OCDRD1_bm (1<<1) /* OCDR Dirty bit 1 mask. */ -#define OCD_OCDRD1_bp 1 /* OCDR Dirty bit 1 position. */ -#define OCD_OCDRD2_bm (1<<2) /* OCDR Dirty bit 2 mask. */ -#define OCD_OCDRD2_bp 2 /* OCDR Dirty bit 2 position. */ -#define OCD_OCDRD3_bm (1<<3) /* OCDR Dirty bit 3 mask. */ -#define OCD_OCDRD3_bp 3 /* OCDR Dirty bit 3 position. */ -#define OCD_OCDRD4_bm (1<<4) /* OCDR Dirty bit 4 mask. */ -#define OCD_OCDRD4_bp 4 /* OCDR Dirty bit 4 position. */ -#define OCD_OCDRD5_bm (1<<5) /* OCDR Dirty bit 5 mask. */ -#define OCD_OCDRD5_bp 5 /* OCDR Dirty bit 5 position. */ -#define OCD_OCDRD6_bm (1<<6) /* OCDR Dirty bit 6 mask. */ -#define OCD_OCDRD6_bp 6 /* OCDR Dirty bit 6 position. */ -#define OCD_OCDRD7_bm (1<<7) /* OCDR Dirty bit 7 mask. */ -#define OCD_OCDRD7_bp 7 /* OCDR Dirty bit 7 position. */ - -/* OCD.OCDR1 bit masks and bit positions */ -/* OCD_OCDRD Predefined. */ -/* OCD_OCDRD Predefined. */ - -/* CPU - CPU */ -/* CPU.CCP bit masks and bit positions */ -#define CPU_CCP_gm 0xFF /* CCP signature group mask. */ -#define CPU_CCP_gp 0 /* CCP signature group position. */ -#define CPU_CCP0_bm (1<<0) /* CCP signature bit 0 mask. */ -#define CPU_CCP0_bp 0 /* CCP signature bit 0 position. */ -#define CPU_CCP1_bm (1<<1) /* CCP signature bit 1 mask. */ -#define CPU_CCP1_bp 1 /* CCP signature bit 1 position. */ -#define CPU_CCP2_bm (1<<2) /* CCP signature bit 2 mask. */ -#define CPU_CCP2_bp 2 /* CCP signature bit 2 position. */ -#define CPU_CCP3_bm (1<<3) /* CCP signature bit 3 mask. */ -#define CPU_CCP3_bp 3 /* CCP signature bit 3 position. */ -#define CPU_CCP4_bm (1<<4) /* CCP signature bit 4 mask. */ -#define CPU_CCP4_bp 4 /* CCP signature bit 4 position. */ -#define CPU_CCP5_bm (1<<5) /* CCP signature bit 5 mask. */ -#define CPU_CCP5_bp 5 /* CCP signature bit 5 position. */ -#define CPU_CCP6_bm (1<<6) /* CCP signature bit 6 mask. */ -#define CPU_CCP6_bp 6 /* CCP signature bit 6 position. */ -#define CPU_CCP7_bm (1<<7) /* CCP signature bit 7 mask. */ -#define CPU_CCP7_bp 7 /* CCP signature bit 7 position. */ - -/* CPU.SREG bit masks and bit positions */ -#define CPU_I_bm 0x80 /* Global Interrupt Enable Flag bit mask. */ -#define CPU_I_bp 7 /* Global Interrupt Enable Flag bit position. */ - -#define CPU_T_bm 0x40 /* Transfer Bit bit mask. */ -#define CPU_T_bp 6 /* Transfer Bit bit position. */ - -#define CPU_H_bm 0x20 /* Half Carry Flag bit mask. */ -#define CPU_H_bp 5 /* Half Carry Flag bit position. */ - -#define CPU_S_bm 0x10 /* N Exclusive Or V Flag bit mask. */ -#define CPU_S_bp 4 /* N Exclusive Or V Flag bit position. */ - -#define CPU_V_bm 0x08 /* Two's Complement Overflow Flag bit mask. */ -#define CPU_V_bp 3 /* Two's Complement Overflow Flag bit position. */ - -#define CPU_N_bm 0x04 /* Negative Flag bit mask. */ -#define CPU_N_bp 2 /* Negative Flag bit position. */ - -#define CPU_Z_bm 0x02 /* Zero Flag bit mask. */ -#define CPU_Z_bp 1 /* Zero Flag bit position. */ - -#define CPU_C_bm 0x01 /* Carry Flag bit mask. */ -#define CPU_C_bp 0 /* Carry Flag bit position. */ - -/* CLK - Clock System */ -/* CLK.CTRL bit masks and bit positions */ -#define CLK_SCLKSEL_gm 0x07 /* System Clock Selection group mask. */ -#define CLK_SCLKSEL_gp 0 /* System Clock Selection group position. */ -#define CLK_SCLKSEL0_bm (1<<0) /* System Clock Selection bit 0 mask. */ -#define CLK_SCLKSEL0_bp 0 /* System Clock Selection bit 0 position. */ -#define CLK_SCLKSEL1_bm (1<<1) /* System Clock Selection bit 1 mask. */ -#define CLK_SCLKSEL1_bp 1 /* System Clock Selection bit 1 position. */ -#define CLK_SCLKSEL2_bm (1<<2) /* System Clock Selection bit 2 mask. */ -#define CLK_SCLKSEL2_bp 2 /* System Clock Selection bit 2 position. */ - -/* CLK.PSCTRL bit masks and bit positions */ -#define CLK_PSADIV_gm 0x7C /* Prescaler A Division Factor group mask. */ -#define CLK_PSADIV_gp 2 /* Prescaler A Division Factor group position. */ -#define CLK_PSADIV0_bm (1<<2) /* Prescaler A Division Factor bit 0 mask. */ -#define CLK_PSADIV0_bp 2 /* Prescaler A Division Factor bit 0 position. */ -#define CLK_PSADIV1_bm (1<<3) /* Prescaler A Division Factor bit 1 mask. */ -#define CLK_PSADIV1_bp 3 /* Prescaler A Division Factor bit 1 position. */ -#define CLK_PSADIV2_bm (1<<4) /* Prescaler A Division Factor bit 2 mask. */ -#define CLK_PSADIV2_bp 4 /* Prescaler A Division Factor bit 2 position. */ -#define CLK_PSADIV3_bm (1<<5) /* Prescaler A Division Factor bit 3 mask. */ -#define CLK_PSADIV3_bp 5 /* Prescaler A Division Factor bit 3 position. */ -#define CLK_PSADIV4_bm (1<<6) /* Prescaler A Division Factor bit 4 mask. */ -#define CLK_PSADIV4_bp 6 /* Prescaler A Division Factor bit 4 position. */ - -#define CLK_PSBCDIV_gm 0x03 /* Prescaler B and C Division factor group mask. */ -#define CLK_PSBCDIV_gp 0 /* Prescaler B and C Division factor group position. */ -#define CLK_PSBCDIV0_bm (1<<0) /* Prescaler B and C Division factor bit 0 mask. */ -#define CLK_PSBCDIV0_bp 0 /* Prescaler B and C Division factor bit 0 position. */ -#define CLK_PSBCDIV1_bm (1<<1) /* Prescaler B and C Division factor bit 1 mask. */ -#define CLK_PSBCDIV1_bp 1 /* Prescaler B and C Division factor bit 1 position. */ - -/* CLK.LOCK bit masks and bit positions */ -#define CLK_LOCK_bm 0x01 /* Clock System Lock bit mask. */ -#define CLK_LOCK_bp 0 /* Clock System Lock bit position. */ - -/* CLK.RTCCTRL bit masks and bit positions */ -#define CLK_RTCSRC_gm 0x0E /* Clock Source group mask. */ -#define CLK_RTCSRC_gp 1 /* Clock Source group position. */ -#define CLK_RTCSRC0_bm (1<<1) /* Clock Source bit 0 mask. */ -#define CLK_RTCSRC0_bp 1 /* Clock Source bit 0 position. */ -#define CLK_RTCSRC1_bm (1<<2) /* Clock Source bit 1 mask. */ -#define CLK_RTCSRC1_bp 2 /* Clock Source bit 1 position. */ -#define CLK_RTCSRC2_bm (1<<3) /* Clock Source bit 2 mask. */ -#define CLK_RTCSRC2_bp 3 /* Clock Source bit 2 position. */ - -#define CLK_RTCEN_bm 0x01 /* Clock Source Enable bit mask. */ -#define CLK_RTCEN_bp 0 /* Clock Source Enable bit position. */ - -/* CLK.USBCTRL bit masks and bit positions */ -#define CLK_USBPSDIV_gm 0x38 /* Prescaler Division Factor group mask. */ -#define CLK_USBPSDIV_gp 3 /* Prescaler Division Factor group position. */ -#define CLK_USBPSDIV0_bm (1<<3) /* Prescaler Division Factor bit 0 mask. */ -#define CLK_USBPSDIV0_bp 3 /* Prescaler Division Factor bit 0 position. */ -#define CLK_USBPSDIV1_bm (1<<4) /* Prescaler Division Factor bit 1 mask. */ -#define CLK_USBPSDIV1_bp 4 /* Prescaler Division Factor bit 1 position. */ -#define CLK_USBPSDIV2_bm (1<<5) /* Prescaler Division Factor bit 2 mask. */ -#define CLK_USBPSDIV2_bp 5 /* Prescaler Division Factor bit 2 position. */ - -#define CLK_USBSRC_gm 0x06 /* Clock Source group mask. */ -#define CLK_USBSRC_gp 1 /* Clock Source group position. */ -#define CLK_USBSRC0_bm (1<<1) /* Clock Source bit 0 mask. */ -#define CLK_USBSRC0_bp 1 /* Clock Source bit 0 position. */ -#define CLK_USBSRC1_bm (1<<2) /* Clock Source bit 1 mask. */ -#define CLK_USBSRC1_bp 2 /* Clock Source bit 1 position. */ - -#define CLK_USBSEN_bm 0x01 /* Clock Source Enable bit mask. */ -#define CLK_USBSEN_bp 0 /* Clock Source Enable bit position. */ - -/* PR.PRGEN bit masks and bit positions */ -#define PR_USB_bm 0x40 /* USB bit mask. */ -#define PR_USB_bp 6 /* USB bit position. */ - -#define PR_AES_bm 0x10 /* AES bit mask. */ -#define PR_AES_bp 4 /* AES bit position. */ - -#define PR_EBI_bm 0x08 /* External Bus Interface bit mask. */ -#define PR_EBI_bp 3 /* External Bus Interface bit position. */ - -#define PR_RTC_bm 0x04 /* Real-time Counter bit mask. */ -#define PR_RTC_bp 2 /* Real-time Counter bit position. */ - -#define PR_EVSYS_bm 0x02 /* Event System bit mask. */ -#define PR_EVSYS_bp 1 /* Event System bit position. */ - -#define PR_DMA_bm 0x01 /* DMA-Controller bit mask. */ -#define PR_DMA_bp 0 /* DMA-Controller bit position. */ - -/* PR.PRPA bit masks and bit positions */ -#define PR_DAC_bm 0x04 /* Port A DAC bit mask. */ -#define PR_DAC_bp 2 /* Port A DAC bit position. */ - -#define PR_ADC_bm 0x02 /* Port A ADC bit mask. */ -#define PR_ADC_bp 1 /* Port A ADC bit position. */ - -#define PR_AC_bm 0x01 /* Port A Analog Comparator bit mask. */ -#define PR_AC_bp 0 /* Port A Analog Comparator bit position. */ - -/* PR.PRPB bit masks and bit positions */ -/* PR_DAC Predefined. */ -/* PR_DAC Predefined. */ - -/* PR_ADC Predefined. */ -/* PR_ADC Predefined. */ - -/* PR_AC Predefined. */ -/* PR_AC Predefined. */ - -/* PR.PRPC bit masks and bit positions */ -#define PR_TWI_bm 0x40 /* Port C Two-wire Interface bit mask. */ -#define PR_TWI_bp 6 /* Port C Two-wire Interface bit position. */ - -#define PR_USART1_bm 0x20 /* Port C USART1 bit mask. */ -#define PR_USART1_bp 5 /* Port C USART1 bit position. */ - -#define PR_USART0_bm 0x10 /* Port C USART0 bit mask. */ -#define PR_USART0_bp 4 /* Port C USART0 bit position. */ - -#define PR_SPI_bm 0x08 /* Port C SPI bit mask. */ -#define PR_SPI_bp 3 /* Port C SPI bit position. */ - -#define PR_HIRES_bm 0x04 /* Port C AWEX bit mask. */ -#define PR_HIRES_bp 2 /* Port C AWEX bit position. */ - -#define PR_TC1_bm 0x02 /* Port C Timer/Counter1 bit mask. */ -#define PR_TC1_bp 1 /* Port C Timer/Counter1 bit position. */ - -#define PR_TC0_bm 0x01 /* Port C Timer/Counter0 bit mask. */ -#define PR_TC0_bp 0 /* Port C Timer/Counter0 bit position. */ - -/* PR.PRPD bit masks and bit positions */ -/* PR_TWI Predefined. */ -/* PR_TWI Predefined. */ - -/* PR_USART1 Predefined. */ -/* PR_USART1 Predefined. */ - -/* PR_USART0 Predefined. */ -/* PR_USART0 Predefined. */ - -/* PR_SPI Predefined. */ -/* PR_SPI Predefined. */ - -/* PR_HIRES Predefined. */ -/* PR_HIRES Predefined. */ - -/* PR_TC1 Predefined. */ -/* PR_TC1 Predefined. */ - -/* PR_TC0 Predefined. */ -/* PR_TC0 Predefined. */ - -/* PR.PRPE bit masks and bit positions */ -/* PR_TWI Predefined. */ -/* PR_TWI Predefined. */ - -/* PR_USART1 Predefined. */ -/* PR_USART1 Predefined. */ - -/* PR_USART0 Predefined. */ -/* PR_USART0 Predefined. */ - -/* PR_SPI Predefined. */ -/* PR_SPI Predefined. */ - -/* PR_HIRES Predefined. */ -/* PR_HIRES Predefined. */ - -/* PR_TC1 Predefined. */ -/* PR_TC1 Predefined. */ - -/* PR_TC0 Predefined. */ -/* PR_TC0 Predefined. */ - -/* PR.PRPF bit masks and bit positions */ -/* PR_TWI Predefined. */ -/* PR_TWI Predefined. */ - -/* PR_USART1 Predefined. */ -/* PR_USART1 Predefined. */ - -/* PR_USART0 Predefined. */ -/* PR_USART0 Predefined. */ - -/* PR_SPI Predefined. */ -/* PR_SPI Predefined. */ - -/* PR_HIRES Predefined. */ -/* PR_HIRES Predefined. */ - -/* PR_TC1 Predefined. */ -/* PR_TC1 Predefined. */ - -/* PR_TC0 Predefined. */ -/* PR_TC0 Predefined. */ - -/* SLEEP - Sleep Controller */ -/* SLEEP.CTRL bit masks and bit positions */ -#define SLEEP_SMODE_gm 0x0E /* Sleep Mode group mask. */ -#define SLEEP_SMODE_gp 1 /* Sleep Mode group position. */ -#define SLEEP_SMODE0_bm (1<<1) /* Sleep Mode bit 0 mask. */ -#define SLEEP_SMODE0_bp 1 /* Sleep Mode bit 0 position. */ -#define SLEEP_SMODE1_bm (1<<2) /* Sleep Mode bit 1 mask. */ -#define SLEEP_SMODE1_bp 2 /* Sleep Mode bit 1 position. */ -#define SLEEP_SMODE2_bm (1<<3) /* Sleep Mode bit 2 mask. */ -#define SLEEP_SMODE2_bp 3 /* Sleep Mode bit 2 position. */ - -#define SLEEP_SEN_bm 0x01 /* Sleep Enable bit mask. */ -#define SLEEP_SEN_bp 0 /* Sleep Enable bit position. */ - -/* OSC - Oscillator */ -/* OSC.CTRL bit masks and bit positions */ -#define OSC_PLLEN_bm 0x10 /* PLL Enable bit mask. */ -#define OSC_PLLEN_bp 4 /* PLL Enable bit position. */ - -#define OSC_XOSCEN_bm 0x08 /* External Oscillator Enable bit mask. */ -#define OSC_XOSCEN_bp 3 /* External Oscillator Enable bit position. */ - -#define OSC_RC32KEN_bm 0x04 /* Internal 32.768 kHz RC Oscillator Enable bit mask. */ -#define OSC_RC32KEN_bp 2 /* Internal 32.768 kHz RC Oscillator Enable bit position. */ - -#define OSC_RC32MEN_bm 0x02 /* Internal 32 MHz RC Oscillator Enable bit mask. */ -#define OSC_RC32MEN_bp 1 /* Internal 32 MHz RC Oscillator Enable bit position. */ - -#define OSC_RC2MEN_bm 0x01 /* Internal 2 MHz RC Oscillator Enable bit mask. */ -#define OSC_RC2MEN_bp 0 /* Internal 2 MHz RC Oscillator Enable bit position. */ - -/* OSC.STATUS bit masks and bit positions */ -#define OSC_PLLRDY_bm 0x10 /* PLL Ready bit mask. */ -#define OSC_PLLRDY_bp 4 /* PLL Ready bit position. */ - -#define OSC_XOSCRDY_bm 0x08 /* External Oscillator Ready bit mask. */ -#define OSC_XOSCRDY_bp 3 /* External Oscillator Ready bit position. */ - -#define OSC_RC32KRDY_bm 0x04 /* Internal 32.768 kHz RC Oscillator Ready bit mask. */ -#define OSC_RC32KRDY_bp 2 /* Internal 32.768 kHz RC Oscillator Ready bit position. */ - -#define OSC_RC32MRDY_bm 0x02 /* Internal 32 MHz RC Oscillator Ready bit mask. */ -#define OSC_RC32MRDY_bp 1 /* Internal 32 MHz RC Oscillator Ready bit position. */ - -#define OSC_RC2MRDY_bm 0x01 /* Internal 2 MHz RC Oscillator Ready bit mask. */ -#define OSC_RC2MRDY_bp 0 /* Internal 2 MHz RC Oscillator Ready bit position. */ - -/* OSC.XOSCCTRL bit masks and bit positions */ -#define OSC_FRQRANGE_gm 0xC0 /* Frequency Range group mask. */ -#define OSC_FRQRANGE_gp 6 /* Frequency Range group position. */ -#define OSC_FRQRANGE0_bm (1<<6) /* Frequency Range bit 0 mask. */ -#define OSC_FRQRANGE0_bp 6 /* Frequency Range bit 0 position. */ -#define OSC_FRQRANGE1_bm (1<<7) /* Frequency Range bit 1 mask. */ -#define OSC_FRQRANGE1_bp 7 /* Frequency Range bit 1 position. */ - -#define OSC_X32KLPM_bm 0x20 /* 32.768 kHz XTAL OSC Low-power Mode bit mask. */ -#define OSC_X32KLPM_bp 5 /* 32.768 kHz XTAL OSC Low-power Mode bit position. */ - -#define OSC_XOSCPWR_bm 0x10 /* 16 MHz Crystal Oscillator High Power mode bit mask. */ -#define OSC_XOSCPWR_bp 4 /* 16 MHz Crystal Oscillator High Power mode bit position. */ - -#define OSC_XOSCSEL_gm 0x0F /* External Oscillator Selection and Startup Time group mask. */ -#define OSC_XOSCSEL_gp 0 /* External Oscillator Selection and Startup Time group position. */ -#define OSC_XOSCSEL0_bm (1<<0) /* External Oscillator Selection and Startup Time bit 0 mask. */ -#define OSC_XOSCSEL0_bp 0 /* External Oscillator Selection and Startup Time bit 0 position. */ -#define OSC_XOSCSEL1_bm (1<<1) /* External Oscillator Selection and Startup Time bit 1 mask. */ -#define OSC_XOSCSEL1_bp 1 /* External Oscillator Selection and Startup Time bit 1 position. */ -#define OSC_XOSCSEL2_bm (1<<2) /* External Oscillator Selection and Startup Time bit 2 mask. */ -#define OSC_XOSCSEL2_bp 2 /* External Oscillator Selection and Startup Time bit 2 position. */ -#define OSC_XOSCSEL3_bm (1<<3) /* External Oscillator Selection and Startup Time bit 3 mask. */ -#define OSC_XOSCSEL3_bp 3 /* External Oscillator Selection and Startup Time bit 3 position. */ - -/* OSC.XOSCFAIL bit masks and bit positions */ -#define OSC_PLLFDIF_bm 0x08 /* PLL Failure Detection Interrupt Flag bit mask. */ -#define OSC_PLLFDIF_bp 3 /* PLL Failure Detection Interrupt Flag bit position. */ - -#define OSC_PLLFDEN_bm 0x04 /* PLL Failure Detection Enable bit mask. */ -#define OSC_PLLFDEN_bp 2 /* PLL Failure Detection Enable bit position. */ - -#define OSC_XOSCFDIF_bm 0x02 /* XOSC Failure Detection Interrupt Flag bit mask. */ -#define OSC_XOSCFDIF_bp 1 /* XOSC Failure Detection Interrupt Flag bit position. */ - -#define OSC_XOSCFDEN_bm 0x01 /* XOSC Failure Detection Enable bit mask. */ -#define OSC_XOSCFDEN_bp 0 /* XOSC Failure Detection Enable bit position. */ - -/* OSC.PLLCTRL bit masks and bit positions */ -#define OSC_PLLSRC_gm 0xC0 /* Clock Source group mask. */ -#define OSC_PLLSRC_gp 6 /* Clock Source group position. */ -#define OSC_PLLSRC0_bm (1<<6) /* Clock Source bit 0 mask. */ -#define OSC_PLLSRC0_bp 6 /* Clock Source bit 0 position. */ -#define OSC_PLLSRC1_bm (1<<7) /* Clock Source bit 1 mask. */ -#define OSC_PLLSRC1_bp 7 /* Clock Source bit 1 position. */ - -#define OSC_PLLDIV_bm 0x20 /* Divide by 2 bit mask. */ -#define OSC_PLLDIV_bp 5 /* Divide by 2 bit position. */ - -#define OSC_PLLFAC_gm 0x1F /* Multiplication Factor group mask. */ -#define OSC_PLLFAC_gp 0 /* Multiplication Factor group position. */ -#define OSC_PLLFAC0_bm (1<<0) /* Multiplication Factor bit 0 mask. */ -#define OSC_PLLFAC0_bp 0 /* Multiplication Factor bit 0 position. */ -#define OSC_PLLFAC1_bm (1<<1) /* Multiplication Factor bit 1 mask. */ -#define OSC_PLLFAC1_bp 1 /* Multiplication Factor bit 1 position. */ -#define OSC_PLLFAC2_bm (1<<2) /* Multiplication Factor bit 2 mask. */ -#define OSC_PLLFAC2_bp 2 /* Multiplication Factor bit 2 position. */ -#define OSC_PLLFAC3_bm (1<<3) /* Multiplication Factor bit 3 mask. */ -#define OSC_PLLFAC3_bp 3 /* Multiplication Factor bit 3 position. */ -#define OSC_PLLFAC4_bm (1<<4) /* Multiplication Factor bit 4 mask. */ -#define OSC_PLLFAC4_bp 4 /* Multiplication Factor bit 4 position. */ - -/* OSC.DFLLCTRL bit masks and bit positions */ -#define OSC_RC32MCREF_gm 0x06 /* 32 MHz DFLL Calibration Reference group mask. */ -#define OSC_RC32MCREF_gp 1 /* 32 MHz DFLL Calibration Reference group position. */ -#define OSC_RC32MCREF0_bm (1<<1) /* 32 MHz DFLL Calibration Reference bit 0 mask. */ -#define OSC_RC32MCREF0_bp 1 /* 32 MHz DFLL Calibration Reference bit 0 position. */ -#define OSC_RC32MCREF1_bm (1<<2) /* 32 MHz DFLL Calibration Reference bit 1 mask. */ -#define OSC_RC32MCREF1_bp 2 /* 32 MHz DFLL Calibration Reference bit 1 position. */ - -#define OSC_RC2MCREF_bm 0x01 /* 2 MHz DFLL Calibration Reference bit mask. */ -#define OSC_RC2MCREF_bp 0 /* 2 MHz DFLL Calibration Reference bit position. */ - -/* DFLL - DFLL */ -/* DFLL.CTRL bit masks and bit positions */ -#define DFLL_ENABLE_bm 0x01 /* DFLL Enable bit mask. */ -#define DFLL_ENABLE_bp 0 /* DFLL Enable bit position. */ - -/* DFLL.CALA bit masks and bit positions */ -#define DFLL_CALL_gm 0x7F /* DFLL Calibration Value A group mask. */ -#define DFLL_CALL_gp 0 /* DFLL Calibration Value A group position. */ -#define DFLL_CALL0_bm (1<<0) /* DFLL Calibration Value A bit 0 mask. */ -#define DFLL_CALL0_bp 0 /* DFLL Calibration Value A bit 0 position. */ -#define DFLL_CALL1_bm (1<<1) /* DFLL Calibration Value A bit 1 mask. */ -#define DFLL_CALL1_bp 1 /* DFLL Calibration Value A bit 1 position. */ -#define DFLL_CALL2_bm (1<<2) /* DFLL Calibration Value A bit 2 mask. */ -#define DFLL_CALL2_bp 2 /* DFLL Calibration Value A bit 2 position. */ -#define DFLL_CALL3_bm (1<<3) /* DFLL Calibration Value A bit 3 mask. */ -#define DFLL_CALL3_bp 3 /* DFLL Calibration Value A bit 3 position. */ -#define DFLL_CALL4_bm (1<<4) /* DFLL Calibration Value A bit 4 mask. */ -#define DFLL_CALL4_bp 4 /* DFLL Calibration Value A bit 4 position. */ -#define DFLL_CALL5_bm (1<<5) /* DFLL Calibration Value A bit 5 mask. */ -#define DFLL_CALL5_bp 5 /* DFLL Calibration Value A bit 5 position. */ -#define DFLL_CALL6_bm (1<<6) /* DFLL Calibration Value A bit 6 mask. */ -#define DFLL_CALL6_bp 6 /* DFLL Calibration Value A bit 6 position. */ - -/* DFLL.CALB bit masks and bit positions */ -#define DFLL_CALH_gm 0x3F /* DFLL Calibration Value B group mask. */ -#define DFLL_CALH_gp 0 /* DFLL Calibration Value B group position. */ -#define DFLL_CALH0_bm (1<<0) /* DFLL Calibration Value B bit 0 mask. */ -#define DFLL_CALH0_bp 0 /* DFLL Calibration Value B bit 0 position. */ -#define DFLL_CALH1_bm (1<<1) /* DFLL Calibration Value B bit 1 mask. */ -#define DFLL_CALH1_bp 1 /* DFLL Calibration Value B bit 1 position. */ -#define DFLL_CALH2_bm (1<<2) /* DFLL Calibration Value B bit 2 mask. */ -#define DFLL_CALH2_bp 2 /* DFLL Calibration Value B bit 2 position. */ -#define DFLL_CALH3_bm (1<<3) /* DFLL Calibration Value B bit 3 mask. */ -#define DFLL_CALH3_bp 3 /* DFLL Calibration Value B bit 3 position. */ -#define DFLL_CALH4_bm (1<<4) /* DFLL Calibration Value B bit 4 mask. */ -#define DFLL_CALH4_bp 4 /* DFLL Calibration Value B bit 4 position. */ -#define DFLL_CALH5_bm (1<<5) /* DFLL Calibration Value B bit 5 mask. */ -#define DFLL_CALH5_bp 5 /* DFLL Calibration Value B bit 5 position. */ - -/* RST - Reset */ -/* RST.STATUS bit masks and bit positions */ -#define RST_SDRF_bm 0x40 /* Spike Detection Reset Flag bit mask. */ -#define RST_SDRF_bp 6 /* Spike Detection Reset Flag bit position. */ - -#define RST_SRF_bm 0x20 /* Software Reset Flag bit mask. */ -#define RST_SRF_bp 5 /* Software Reset Flag bit position. */ - -#define RST_PDIRF_bm 0x10 /* Programming and Debug Interface Interface Reset Flag bit mask. */ -#define RST_PDIRF_bp 4 /* Programming and Debug Interface Interface Reset Flag bit position. */ - -#define RST_WDRF_bm 0x08 /* Watchdog Reset Flag bit mask. */ -#define RST_WDRF_bp 3 /* Watchdog Reset Flag bit position. */ - -#define RST_BORF_bm 0x04 /* Brown-out Reset Flag bit mask. */ -#define RST_BORF_bp 2 /* Brown-out Reset Flag bit position. */ - -#define RST_EXTRF_bm 0x02 /* External Reset Flag bit mask. */ -#define RST_EXTRF_bp 1 /* External Reset Flag bit position. */ - -#define RST_PORF_bm 0x01 /* Power-on Reset Flag bit mask. */ -#define RST_PORF_bp 0 /* Power-on Reset Flag bit position. */ - -/* RST.CTRL bit masks and bit positions */ -#define RST_SWRST_bm 0x01 /* Software Reset bit mask. */ -#define RST_SWRST_bp 0 /* Software Reset bit position. */ - -/* WDT - Watch-Dog Timer */ -/* WDT.CTRL bit masks and bit positions */ -#define WDT_PER_gm 0x3C /* Period group mask. */ -#define WDT_PER_gp 2 /* Period group position. */ -#define WDT_PER0_bm (1<<2) /* Period bit 0 mask. */ -#define WDT_PER0_bp 2 /* Period bit 0 position. */ -#define WDT_PER1_bm (1<<3) /* Period bit 1 mask. */ -#define WDT_PER1_bp 3 /* Period bit 1 position. */ -#define WDT_PER2_bm (1<<4) /* Period bit 2 mask. */ -#define WDT_PER2_bp 4 /* Period bit 2 position. */ -#define WDT_PER3_bm (1<<5) /* Period bit 3 mask. */ -#define WDT_PER3_bp 5 /* Period bit 3 position. */ - -#define WDT_ENABLE_bm 0x02 /* Enable bit mask. */ -#define WDT_ENABLE_bp 1 /* Enable bit position. */ - -#define WDT_CEN_bm 0x01 /* Change Enable bit mask. */ -#define WDT_CEN_bp 0 /* Change Enable bit position. */ - -/* WDT.WINCTRL bit masks and bit positions */ -#define WDT_WPER_gm 0x3C /* Windowed Mode Period group mask. */ -#define WDT_WPER_gp 2 /* Windowed Mode Period group position. */ -#define WDT_WPER0_bm (1<<2) /* Windowed Mode Period bit 0 mask. */ -#define WDT_WPER0_bp 2 /* Windowed Mode Period bit 0 position. */ -#define WDT_WPER1_bm (1<<3) /* Windowed Mode Period bit 1 mask. */ -#define WDT_WPER1_bp 3 /* Windowed Mode Period bit 1 position. */ -#define WDT_WPER2_bm (1<<4) /* Windowed Mode Period bit 2 mask. */ -#define WDT_WPER2_bp 4 /* Windowed Mode Period bit 2 position. */ -#define WDT_WPER3_bm (1<<5) /* Windowed Mode Period bit 3 mask. */ -#define WDT_WPER3_bp 5 /* Windowed Mode Period bit 3 position. */ - -#define WDT_WEN_bm 0x02 /* Windowed Mode Enable bit mask. */ -#define WDT_WEN_bp 1 /* Windowed Mode Enable bit position. */ - -#define WDT_WCEN_bm 0x01 /* Windowed Mode Change Enable bit mask. */ -#define WDT_WCEN_bp 0 /* Windowed Mode Change Enable bit position. */ - -/* WDT.STATUS bit masks and bit positions */ -#define WDT_SYNCBUSY_bm 0x01 /* Syncronization busy bit mask. */ -#define WDT_SYNCBUSY_bp 0 /* Syncronization busy bit position. */ - -/* MCU - MCU Control */ -/* MCU.MCUCR bit masks and bit positions */ -#define MCU_JTAGD_bm 0x01 /* JTAG Disable bit mask. */ -#define MCU_JTAGD_bp 0 /* JTAG Disable bit position. */ - -/* MCU.ANAINIT bit masks and bit positions */ -#define MCU_STARTUPDLYB_gm 0x0C /* Analog startup delay Port B group mask. */ -#define MCU_STARTUPDLYB_gp 2 /* Analog startup delay Port B group position. */ -#define MCU_STARTUPDLYB0_bm (1<<2) /* Analog startup delay Port B bit 0 mask. */ -#define MCU_STARTUPDLYB0_bp 2 /* Analog startup delay Port B bit 0 position. */ -#define MCU_STARTUPDLYB1_bm (1<<3) /* Analog startup delay Port B bit 1 mask. */ -#define MCU_STARTUPDLYB1_bp 3 /* Analog startup delay Port B bit 1 position. */ - -#define MCU_STARTUPDLYA_gm 0x03 /* Analog startup delay Port A group mask. */ -#define MCU_STARTUPDLYA_gp 0 /* Analog startup delay Port A group position. */ -#define MCU_STARTUPDLYA0_bm (1<<0) /* Analog startup delay Port A bit 0 mask. */ -#define MCU_STARTUPDLYA0_bp 0 /* Analog startup delay Port A bit 0 position. */ -#define MCU_STARTUPDLYA1_bm (1<<1) /* Analog startup delay Port A bit 1 mask. */ -#define MCU_STARTUPDLYA1_bp 1 /* Analog startup delay Port A bit 1 position. */ - -/* MCU.EVSYSLOCK bit masks and bit positions */ -#define MCU_EVSYS1LOCK_bm 0x10 /* Event Channel 4-7 Lock bit mask. */ -#define MCU_EVSYS1LOCK_bp 4 /* Event Channel 4-7 Lock bit position. */ - -#define MCU_EVSYS0LOCK_bm 0x01 /* Event Channel 0-3 Lock bit mask. */ -#define MCU_EVSYS0LOCK_bp 0 /* Event Channel 0-3 Lock bit position. */ - -/* MCU.AWEXLOCK bit masks and bit positions */ -#define MCU_AWEXFLOCK_bm 0x08 /* AWeX on T/C F0 Lock bit mask. */ -#define MCU_AWEXFLOCK_bp 3 /* AWeX on T/C F0 Lock bit position. */ - -#define MCU_AWEXELOCK_bm 0x04 /* AWeX on T/C E0 Lock bit mask. */ -#define MCU_AWEXELOCK_bp 2 /* AWeX on T/C E0 Lock bit position. */ - -#define MCU_AWEXDLOCK_bm 0x02 /* AWeX on T/C D0 Lock bit mask. */ -#define MCU_AWEXDLOCK_bp 1 /* AWeX on T/C D0 Lock bit position. */ - -#define MCU_AWEXCLOCK_bm 0x01 /* AWeX on T/C C0 Lock bit mask. */ -#define MCU_AWEXCLOCK_bp 0 /* AWeX on T/C C0 Lock bit position. */ - -/* PMIC - Programmable Multi-level Interrupt Controller */ -/* PMIC.STATUS bit masks and bit positions */ -#define PMIC_NMIEX_bm 0x80 /* Non-maskable Interrupt Executing bit mask. */ -#define PMIC_NMIEX_bp 7 /* Non-maskable Interrupt Executing bit position. */ - -#define PMIC_HILVLEX_bm 0x04 /* High Level Interrupt Executing bit mask. */ -#define PMIC_HILVLEX_bp 2 /* High Level Interrupt Executing bit position. */ - -#define PMIC_MEDLVLEX_bm 0x02 /* Medium Level Interrupt Executing bit mask. */ -#define PMIC_MEDLVLEX_bp 1 /* Medium Level Interrupt Executing bit position. */ - -#define PMIC_LOLVLEX_bm 0x01 /* Low Level Interrupt Executing bit mask. */ -#define PMIC_LOLVLEX_bp 0 /* Low Level Interrupt Executing bit position. */ - -/* PMIC.INTPRI bit masks and bit positions */ -#define PMIC_INTPRI_gm 0xFF /* Interrupt Priority group mask. */ -#define PMIC_INTPRI_gp 0 /* Interrupt Priority group position. */ -#define PMIC_INTPRI0_bm (1<<0) /* Interrupt Priority bit 0 mask. */ -#define PMIC_INTPRI0_bp 0 /* Interrupt Priority bit 0 position. */ -#define PMIC_INTPRI1_bm (1<<1) /* Interrupt Priority bit 1 mask. */ -#define PMIC_INTPRI1_bp 1 /* Interrupt Priority bit 1 position. */ -#define PMIC_INTPRI2_bm (1<<2) /* Interrupt Priority bit 2 mask. */ -#define PMIC_INTPRI2_bp 2 /* Interrupt Priority bit 2 position. */ -#define PMIC_INTPRI3_bm (1<<3) /* Interrupt Priority bit 3 mask. */ -#define PMIC_INTPRI3_bp 3 /* Interrupt Priority bit 3 position. */ -#define PMIC_INTPRI4_bm (1<<4) /* Interrupt Priority bit 4 mask. */ -#define PMIC_INTPRI4_bp 4 /* Interrupt Priority bit 4 position. */ -#define PMIC_INTPRI5_bm (1<<5) /* Interrupt Priority bit 5 mask. */ -#define PMIC_INTPRI5_bp 5 /* Interrupt Priority bit 5 position. */ -#define PMIC_INTPRI6_bm (1<<6) /* Interrupt Priority bit 6 mask. */ -#define PMIC_INTPRI6_bp 6 /* Interrupt Priority bit 6 position. */ -#define PMIC_INTPRI7_bm (1<<7) /* Interrupt Priority bit 7 mask. */ -#define PMIC_INTPRI7_bp 7 /* Interrupt Priority bit 7 position. */ - -/* PMIC.CTRL bit masks and bit positions */ -#define PMIC_RREN_bm 0x80 /* Round-Robin Priority Enable bit mask. */ -#define PMIC_RREN_bp 7 /* Round-Robin Priority Enable bit position. */ - -#define PMIC_IVSEL_bm 0x40 /* Interrupt Vector Select bit mask. */ -#define PMIC_IVSEL_bp 6 /* Interrupt Vector Select bit position. */ - -#define PMIC_HILVLEN_bm 0x04 /* High Level Enable bit mask. */ -#define PMIC_HILVLEN_bp 2 /* High Level Enable bit position. */ - -#define PMIC_MEDLVLEN_bm 0x02 /* Medium Level Enable bit mask. */ -#define PMIC_MEDLVLEN_bp 1 /* Medium Level Enable bit position. */ - -#define PMIC_LOLVLEN_bm 0x01 /* Low Level Enable bit mask. */ -#define PMIC_LOLVLEN_bp 0 /* Low Level Enable bit position. */ - -/* PORTCFG - Port Configuration */ -/* PORTCFG.VPCTRLA bit masks and bit positions */ -#define PORTCFG_VP1MAP_gm 0xF0 /* Virtual Port 1 Mapping group mask. */ -#define PORTCFG_VP1MAP_gp 4 /* Virtual Port 1 Mapping group position. */ -#define PORTCFG_VP1MAP0_bm (1<<4) /* Virtual Port 1 Mapping bit 0 mask. */ -#define PORTCFG_VP1MAP0_bp 4 /* Virtual Port 1 Mapping bit 0 position. */ -#define PORTCFG_VP1MAP1_bm (1<<5) /* Virtual Port 1 Mapping bit 1 mask. */ -#define PORTCFG_VP1MAP1_bp 5 /* Virtual Port 1 Mapping bit 1 position. */ -#define PORTCFG_VP1MAP2_bm (1<<6) /* Virtual Port 1 Mapping bit 2 mask. */ -#define PORTCFG_VP1MAP2_bp 6 /* Virtual Port 1 Mapping bit 2 position. */ -#define PORTCFG_VP1MAP3_bm (1<<7) /* Virtual Port 1 Mapping bit 3 mask. */ -#define PORTCFG_VP1MAP3_bp 7 /* Virtual Port 1 Mapping bit 3 position. */ - -#define PORTCFG_VP0MAP_gm 0x0F /* Virtual Port 0 Mapping group mask. */ -#define PORTCFG_VP0MAP_gp 0 /* Virtual Port 0 Mapping group position. */ -#define PORTCFG_VP0MAP0_bm (1<<0) /* Virtual Port 0 Mapping bit 0 mask. */ -#define PORTCFG_VP0MAP0_bp 0 /* Virtual Port 0 Mapping bit 0 position. */ -#define PORTCFG_VP0MAP1_bm (1<<1) /* Virtual Port 0 Mapping bit 1 mask. */ -#define PORTCFG_VP0MAP1_bp 1 /* Virtual Port 0 Mapping bit 1 position. */ -#define PORTCFG_VP0MAP2_bm (1<<2) /* Virtual Port 0 Mapping bit 2 mask. */ -#define PORTCFG_VP0MAP2_bp 2 /* Virtual Port 0 Mapping bit 2 position. */ -#define PORTCFG_VP0MAP3_bm (1<<3) /* Virtual Port 0 Mapping bit 3 mask. */ -#define PORTCFG_VP0MAP3_bp 3 /* Virtual Port 0 Mapping bit 3 position. */ - -/* PORTCFG.VPCTRLB bit masks and bit positions */ -#define PORTCFG_VP3MAP_gm 0xF0 /* Virtual Port 3 Mapping group mask. */ -#define PORTCFG_VP3MAP_gp 4 /* Virtual Port 3 Mapping group position. */ -#define PORTCFG_VP3MAP0_bm (1<<4) /* Virtual Port 3 Mapping bit 0 mask. */ -#define PORTCFG_VP3MAP0_bp 4 /* Virtual Port 3 Mapping bit 0 position. */ -#define PORTCFG_VP3MAP1_bm (1<<5) /* Virtual Port 3 Mapping bit 1 mask. */ -#define PORTCFG_VP3MAP1_bp 5 /* Virtual Port 3 Mapping bit 1 position. */ -#define PORTCFG_VP3MAP2_bm (1<<6) /* Virtual Port 3 Mapping bit 2 mask. */ -#define PORTCFG_VP3MAP2_bp 6 /* Virtual Port 3 Mapping bit 2 position. */ -#define PORTCFG_VP3MAP3_bm (1<<7) /* Virtual Port 3 Mapping bit 3 mask. */ -#define PORTCFG_VP3MAP3_bp 7 /* Virtual Port 3 Mapping bit 3 position. */ - -#define PORTCFG_VP2MAP_gm 0x0F /* Virtual Port 2 Mapping group mask. */ -#define PORTCFG_VP2MAP_gp 0 /* Virtual Port 2 Mapping group position. */ -#define PORTCFG_VP2MAP0_bm (1<<0) /* Virtual Port 2 Mapping bit 0 mask. */ -#define PORTCFG_VP2MAP0_bp 0 /* Virtual Port 2 Mapping bit 0 position. */ -#define PORTCFG_VP2MAP1_bm (1<<1) /* Virtual Port 2 Mapping bit 1 mask. */ -#define PORTCFG_VP2MAP1_bp 1 /* Virtual Port 2 Mapping bit 1 position. */ -#define PORTCFG_VP2MAP2_bm (1<<2) /* Virtual Port 2 Mapping bit 2 mask. */ -#define PORTCFG_VP2MAP2_bp 2 /* Virtual Port 2 Mapping bit 2 position. */ -#define PORTCFG_VP2MAP3_bm (1<<3) /* Virtual Port 2 Mapping bit 3 mask. */ -#define PORTCFG_VP2MAP3_bp 3 /* Virtual Port 2 Mapping bit 3 position. */ - -/* PORTCFG.CLKEVOUT bit masks and bit positions */ -#define PORTCFG_CLKOUT_gm 0x03 /* Peripheral Clock Output Port group mask. */ -#define PORTCFG_CLKOUT_gp 0 /* Peripheral Clock Output Port group position. */ -#define PORTCFG_CLKOUT0_bm (1<<0) /* Peripheral Clock Output Port bit 0 mask. */ -#define PORTCFG_CLKOUT0_bp 0 /* Peripheral Clock Output Port bit 0 position. */ -#define PORTCFG_CLKOUT1_bm (1<<1) /* Peripheral Clock Output Port bit 1 mask. */ -#define PORTCFG_CLKOUT1_bp 1 /* Peripheral Clock Output Port bit 1 position. */ - -#define PORTCFG_CLKOUTSEL_gm 0x0C /* Peripheral Clock Output Select group mask. */ -#define PORTCFG_CLKOUTSEL_gp 2 /* Peripheral Clock Output Select group position. */ -#define PORTCFG_CLKOUTSEL0_bm (1<<2) /* Peripheral Clock Output Select bit 0 mask. */ -#define PORTCFG_CLKOUTSEL0_bp 2 /* Peripheral Clock Output Select bit 0 position. */ -#define PORTCFG_CLKOUTSEL1_bm (1<<3) /* Peripheral Clock Output Select bit 1 mask. */ -#define PORTCFG_CLKOUTSEL1_bp 3 /* Peripheral Clock Output Select bit 1 position. */ - -#define PORTCFG_EVOUT_gm 0x30 /* Event Output Port group mask. */ -#define PORTCFG_EVOUT_gp 4 /* Event Output Port group position. */ -#define PORTCFG_EVOUT0_bm (1<<4) /* Event Output Port bit 0 mask. */ -#define PORTCFG_EVOUT0_bp 4 /* Event Output Port bit 0 position. */ -#define PORTCFG_EVOUT1_bm (1<<5) /* Event Output Port bit 1 mask. */ -#define PORTCFG_EVOUT1_bp 5 /* Event Output Port bit 1 position. */ - -#define PORTCFG_RTCOUT_bm 0x40 /* RTC Clock Output bit mask. */ -#define PORTCFG_RTCOUT_bp 6 /* RTC Clock Output bit position. */ - -#define PORTCFG_CLKEVPIN_bm 0x80 /* Peripheral Clock and Event Output pin Select bit mask. */ -#define PORTCFG_CLKEVPIN_bp 7 /* Peripheral Clock and Event Output pin Select bit position. */ - -/* PORTCFG.EBIOUT bit masks and bit positions */ -#define PORTCFG_EBICSOUT_gm 0x03 /* EBI Chip Select Output group mask. */ -#define PORTCFG_EBICSOUT_gp 0 /* EBI Chip Select Output group position. */ -#define PORTCFG_EBICSOUT0_bm (1<<0) /* EBI Chip Select Output bit 0 mask. */ -#define PORTCFG_EBICSOUT0_bp 0 /* EBI Chip Select Output bit 0 position. */ -#define PORTCFG_EBICSOUT1_bm (1<<1) /* EBI Chip Select Output bit 1 mask. */ -#define PORTCFG_EBICSOUT1_bp 1 /* EBI Chip Select Output bit 1 position. */ - -#define PORTCFG_EBIADROUT_gm 0x0C /* EBI Address Output group mask. */ -#define PORTCFG_EBIADROUT_gp 2 /* EBI Address Output group position. */ -#define PORTCFG_EBIADROUT0_bm (1<<2) /* EBI Address Output bit 0 mask. */ -#define PORTCFG_EBIADROUT0_bp 2 /* EBI Address Output bit 0 position. */ -#define PORTCFG_EBIADROUT1_bm (1<<3) /* EBI Address Output bit 1 mask. */ -#define PORTCFG_EBIADROUT1_bp 3 /* EBI Address Output bit 1 position. */ - -/* PORTCFG.EVOUTSEL bit masks and bit positions */ -#define PORTCFG_EVOUTSEL_gm 0x07 /* Event Output Select group mask. */ -#define PORTCFG_EVOUTSEL_gp 0 /* Event Output Select group position. */ -#define PORTCFG_EVOUTSEL0_bm (1<<0) /* Event Output Select bit 0 mask. */ -#define PORTCFG_EVOUTSEL0_bp 0 /* Event Output Select bit 0 position. */ -#define PORTCFG_EVOUTSEL1_bm (1<<1) /* Event Output Select bit 1 mask. */ -#define PORTCFG_EVOUTSEL1_bp 1 /* Event Output Select bit 1 position. */ -#define PORTCFG_EVOUTSEL2_bm (1<<2) /* Event Output Select bit 2 mask. */ -#define PORTCFG_EVOUTSEL2_bp 2 /* Event Output Select bit 2 position. */ - -/* AES - AES Module */ -/* AES.CTRL bit masks and bit positions */ -#define AES_START_bm 0x80 /* Start/Run bit mask. */ -#define AES_START_bp 7 /* Start/Run bit position. */ - -#define AES_AUTO_bm 0x40 /* Auto Start Trigger bit mask. */ -#define AES_AUTO_bp 6 /* Auto Start Trigger bit position. */ - -#define AES_RESET_bm 0x20 /* AES Software Reset bit mask. */ -#define AES_RESET_bp 5 /* AES Software Reset bit position. */ - -#define AES_DECRYPT_bm 0x10 /* Decryption / Direction bit mask. */ -#define AES_DECRYPT_bp 4 /* Decryption / Direction bit position. */ - -#define AES_XOR_bm 0x04 /* State XOR Load Enable bit mask. */ -#define AES_XOR_bp 2 /* State XOR Load Enable bit position. */ - -/* AES.STATUS bit masks and bit positions */ -#define AES_ERROR_bm 0x80 /* AES Error bit mask. */ -#define AES_ERROR_bp 7 /* AES Error bit position. */ - -#define AES_SRIF_bm 0x01 /* State Ready Interrupt Flag bit mask. */ -#define AES_SRIF_bp 0 /* State Ready Interrupt Flag bit position. */ - -/* AES.INTCTRL bit masks and bit positions */ -#define AES_INTLVL_gm 0x03 /* Interrupt level group mask. */ -#define AES_INTLVL_gp 0 /* Interrupt level group position. */ -#define AES_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */ -#define AES_INTLVL0_bp 0 /* Interrupt level bit 0 position. */ -#define AES_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */ -#define AES_INTLVL1_bp 1 /* Interrupt level bit 1 position. */ - -/* CRC - Cyclic Redundancy Checker */ -/* CRC.CTRL bit masks and bit positions */ -#define CRC_RESET_gm 0xC0 /* Reset group mask. */ -#define CRC_RESET_gp 6 /* Reset group position. */ -#define CRC_RESET0_bm (1<<6) /* Reset bit 0 mask. */ -#define CRC_RESET0_bp 6 /* Reset bit 0 position. */ -#define CRC_RESET1_bm (1<<7) /* Reset bit 1 mask. */ -#define CRC_RESET1_bp 7 /* Reset bit 1 position. */ - -#define CRC_CRC32_bm 0x20 /* CRC Mode bit mask. */ -#define CRC_CRC32_bp 5 /* CRC Mode bit position. */ - -#define CRC_SOURCE_gm 0x0F /* Input Source group mask. */ -#define CRC_SOURCE_gp 0 /* Input Source group position. */ -#define CRC_SOURCE0_bm (1<<0) /* Input Source bit 0 mask. */ -#define CRC_SOURCE0_bp 0 /* Input Source bit 0 position. */ -#define CRC_SOURCE1_bm (1<<1) /* Input Source bit 1 mask. */ -#define CRC_SOURCE1_bp 1 /* Input Source bit 1 position. */ -#define CRC_SOURCE2_bm (1<<2) /* Input Source bit 2 mask. */ -#define CRC_SOURCE2_bp 2 /* Input Source bit 2 position. */ -#define CRC_SOURCE3_bm (1<<3) /* Input Source bit 3 mask. */ -#define CRC_SOURCE3_bp 3 /* Input Source bit 3 position. */ - -/* CRC.STATUS bit masks and bit positions */ -#define CRC_ZERO_bm 0x02 /* Zero detection bit mask. */ -#define CRC_ZERO_bp 1 /* Zero detection bit position. */ - -#define CRC_BUSY_bm 0x01 /* Busy bit mask. */ -#define CRC_BUSY_bp 0 /* Busy bit position. */ - -/* DMA - DMA Controller */ -/* DMA_CH.CTRLA bit masks and bit positions */ -#define DMA_CH_ENABLE_bm 0x80 /* Channel Enable bit mask. */ -#define DMA_CH_ENABLE_bp 7 /* Channel Enable bit position. */ - -#define DMA_CH_RESET_bm 0x40 /* Channel Software Reset bit mask. */ -#define DMA_CH_RESET_bp 6 /* Channel Software Reset bit position. */ - -#define DMA_CH_REPEAT_bm 0x20 /* Channel Repeat Mode bit mask. */ -#define DMA_CH_REPEAT_bp 5 /* Channel Repeat Mode bit position. */ - -#define DMA_CH_TRFREQ_bm 0x10 /* Channel Transfer Request bit mask. */ -#define DMA_CH_TRFREQ_bp 4 /* Channel Transfer Request bit position. */ - -#define DMA_CH_SINGLE_bm 0x04 /* Channel Single Shot Data Transfer bit mask. */ -#define DMA_CH_SINGLE_bp 2 /* Channel Single Shot Data Transfer bit position. */ - -#define DMA_CH_BURSTLEN_gm 0x03 /* Channel Transfer Mode group mask. */ -#define DMA_CH_BURSTLEN_gp 0 /* Channel Transfer Mode group position. */ -#define DMA_CH_BURSTLEN0_bm (1<<0) /* Channel Transfer Mode bit 0 mask. */ -#define DMA_CH_BURSTLEN0_bp 0 /* Channel Transfer Mode bit 0 position. */ -#define DMA_CH_BURSTLEN1_bm (1<<1) /* Channel Transfer Mode bit 1 mask. */ -#define DMA_CH_BURSTLEN1_bp 1 /* Channel Transfer Mode bit 1 position. */ - -/* DMA_CH.CTRLB bit masks and bit positions */ -#define DMA_CH_CHBUSY_bm 0x80 /* Block Transfer Busy bit mask. */ -#define DMA_CH_CHBUSY_bp 7 /* Block Transfer Busy bit position. */ - -#define DMA_CH_CHPEND_bm 0x40 /* Block Transfer Pending bit mask. */ -#define DMA_CH_CHPEND_bp 6 /* Block Transfer Pending bit position. */ - -#define DMA_CH_ERRIF_bm 0x20 /* Block Transfer Error Interrupt Flag bit mask. */ -#define DMA_CH_ERRIF_bp 5 /* Block Transfer Error Interrupt Flag bit position. */ - -#define DMA_CH_TRNIF_bm 0x10 /* Transaction Complete Interrup Flag bit mask. */ -#define DMA_CH_TRNIF_bp 4 /* Transaction Complete Interrup Flag bit position. */ - -#define DMA_CH_ERRINTLVL_gm 0x0C /* Transfer Error Interrupt Level group mask. */ -#define DMA_CH_ERRINTLVL_gp 2 /* Transfer Error Interrupt Level group position. */ -#define DMA_CH_ERRINTLVL0_bm (1<<2) /* Transfer Error Interrupt Level bit 0 mask. */ -#define DMA_CH_ERRINTLVL0_bp 2 /* Transfer Error Interrupt Level bit 0 position. */ -#define DMA_CH_ERRINTLVL1_bm (1<<3) /* Transfer Error Interrupt Level bit 1 mask. */ -#define DMA_CH_ERRINTLVL1_bp 3 /* Transfer Error Interrupt Level bit 1 position. */ - -#define DMA_CH_TRNINTLVL_gm 0x03 /* Transaction Complete Interrupt Level group mask. */ -#define DMA_CH_TRNINTLVL_gp 0 /* Transaction Complete Interrupt Level group position. */ -#define DMA_CH_TRNINTLVL0_bm (1<<0) /* Transaction Complete Interrupt Level bit 0 mask. */ -#define DMA_CH_TRNINTLVL0_bp 0 /* Transaction Complete Interrupt Level bit 0 position. */ -#define DMA_CH_TRNINTLVL1_bm (1<<1) /* Transaction Complete Interrupt Level bit 1 mask. */ -#define DMA_CH_TRNINTLVL1_bp 1 /* Transaction Complete Interrupt Level bit 1 position. */ - -/* DMA_CH.ADDRCTRL bit masks and bit positions */ -#define DMA_CH_SRCRELOAD_gm 0xC0 /* Channel Source Address Reload group mask. */ -#define DMA_CH_SRCRELOAD_gp 6 /* Channel Source Address Reload group position. */ -#define DMA_CH_SRCRELOAD0_bm (1<<6) /* Channel Source Address Reload bit 0 mask. */ -#define DMA_CH_SRCRELOAD0_bp 6 /* Channel Source Address Reload bit 0 position. */ -#define DMA_CH_SRCRELOAD1_bm (1<<7) /* Channel Source Address Reload bit 1 mask. */ -#define DMA_CH_SRCRELOAD1_bp 7 /* Channel Source Address Reload bit 1 position. */ - -#define DMA_CH_SRCDIR_gm 0x30 /* Channel Source Address Mode group mask. */ -#define DMA_CH_SRCDIR_gp 4 /* Channel Source Address Mode group position. */ -#define DMA_CH_SRCDIR0_bm (1<<4) /* Channel Source Address Mode bit 0 mask. */ -#define DMA_CH_SRCDIR0_bp 4 /* Channel Source Address Mode bit 0 position. */ -#define DMA_CH_SRCDIR1_bm (1<<5) /* Channel Source Address Mode bit 1 mask. */ -#define DMA_CH_SRCDIR1_bp 5 /* Channel Source Address Mode bit 1 position. */ - -#define DMA_CH_DESTRELOAD_gm 0x0C /* Channel Destination Address Reload group mask. */ -#define DMA_CH_DESTRELOAD_gp 2 /* Channel Destination Address Reload group position. */ -#define DMA_CH_DESTRELOAD0_bm (1<<2) /* Channel Destination Address Reload bit 0 mask. */ -#define DMA_CH_DESTRELOAD0_bp 2 /* Channel Destination Address Reload bit 0 position. */ -#define DMA_CH_DESTRELOAD1_bm (1<<3) /* Channel Destination Address Reload bit 1 mask. */ -#define DMA_CH_DESTRELOAD1_bp 3 /* Channel Destination Address Reload bit 1 position. */ - -#define DMA_CH_DESTDIR_gm 0x03 /* Channel Destination Address Mode group mask. */ -#define DMA_CH_DESTDIR_gp 0 /* Channel Destination Address Mode group position. */ -#define DMA_CH_DESTDIR0_bm (1<<0) /* Channel Destination Address Mode bit 0 mask. */ -#define DMA_CH_DESTDIR0_bp 0 /* Channel Destination Address Mode bit 0 position. */ -#define DMA_CH_DESTDIR1_bm (1<<1) /* Channel Destination Address Mode bit 1 mask. */ -#define DMA_CH_DESTDIR1_bp 1 /* Channel Destination Address Mode bit 1 position. */ - -/* DMA_CH.TRIGSRC bit masks and bit positions */ -#define DMA_CH_TRIGSRC_gm 0xFF /* Channel Trigger Source group mask. */ -#define DMA_CH_TRIGSRC_gp 0 /* Channel Trigger Source group position. */ -#define DMA_CH_TRIGSRC0_bm (1<<0) /* Channel Trigger Source bit 0 mask. */ -#define DMA_CH_TRIGSRC0_bp 0 /* Channel Trigger Source bit 0 position. */ -#define DMA_CH_TRIGSRC1_bm (1<<1) /* Channel Trigger Source bit 1 mask. */ -#define DMA_CH_TRIGSRC1_bp 1 /* Channel Trigger Source bit 1 position. */ -#define DMA_CH_TRIGSRC2_bm (1<<2) /* Channel Trigger Source bit 2 mask. */ -#define DMA_CH_TRIGSRC2_bp 2 /* Channel Trigger Source bit 2 position. */ -#define DMA_CH_TRIGSRC3_bm (1<<3) /* Channel Trigger Source bit 3 mask. */ -#define DMA_CH_TRIGSRC3_bp 3 /* Channel Trigger Source bit 3 position. */ -#define DMA_CH_TRIGSRC4_bm (1<<4) /* Channel Trigger Source bit 4 mask. */ -#define DMA_CH_TRIGSRC4_bp 4 /* Channel Trigger Source bit 4 position. */ -#define DMA_CH_TRIGSRC5_bm (1<<5) /* Channel Trigger Source bit 5 mask. */ -#define DMA_CH_TRIGSRC5_bp 5 /* Channel Trigger Source bit 5 position. */ -#define DMA_CH_TRIGSRC6_bm (1<<6) /* Channel Trigger Source bit 6 mask. */ -#define DMA_CH_TRIGSRC6_bp 6 /* Channel Trigger Source bit 6 position. */ -#define DMA_CH_TRIGSRC7_bm (1<<7) /* Channel Trigger Source bit 7 mask. */ -#define DMA_CH_TRIGSRC7_bp 7 /* Channel Trigger Source bit 7 position. */ - -/* DMA.CTRL bit masks and bit positions */ -#define DMA_ENABLE_bm 0x80 /* Enable bit mask. */ -#define DMA_ENABLE_bp 7 /* Enable bit position. */ - -#define DMA_RESET_bm 0x40 /* Software Reset bit mask. */ -#define DMA_RESET_bp 6 /* Software Reset bit position. */ - -#define DMA_DBUFMODE_gm 0x0C /* Double Buffering Mode group mask. */ -#define DMA_DBUFMODE_gp 2 /* Double Buffering Mode group position. */ -#define DMA_DBUFMODE0_bm (1<<2) /* Double Buffering Mode bit 0 mask. */ -#define DMA_DBUFMODE0_bp 2 /* Double Buffering Mode bit 0 position. */ -#define DMA_DBUFMODE1_bm (1<<3) /* Double Buffering Mode bit 1 mask. */ -#define DMA_DBUFMODE1_bp 3 /* Double Buffering Mode bit 1 position. */ - -#define DMA_PRIMODE_gm 0x03 /* Channel Priority Mode group mask. */ -#define DMA_PRIMODE_gp 0 /* Channel Priority Mode group position. */ -#define DMA_PRIMODE0_bm (1<<0) /* Channel Priority Mode bit 0 mask. */ -#define DMA_PRIMODE0_bp 0 /* Channel Priority Mode bit 0 position. */ -#define DMA_PRIMODE1_bm (1<<1) /* Channel Priority Mode bit 1 mask. */ -#define DMA_PRIMODE1_bp 1 /* Channel Priority Mode bit 1 position. */ - -/* DMA.INTFLAGS bit masks and bit positions */ -#define DMA_CH3ERRIF_bm 0x80 /* Channel 3 Block Transfer Error Interrupt Flag bit mask. */ -#define DMA_CH3ERRIF_bp 7 /* Channel 3 Block Transfer Error Interrupt Flag bit position. */ - -#define DMA_CH2ERRIF_bm 0x40 /* Channel 2 Block Transfer Error Interrupt Flag bit mask. */ -#define DMA_CH2ERRIF_bp 6 /* Channel 2 Block Transfer Error Interrupt Flag bit position. */ - -#define DMA_CH1ERRIF_bm 0x20 /* Channel 1 Block Transfer Error Interrupt Flag bit mask. */ -#define DMA_CH1ERRIF_bp 5 /* Channel 1 Block Transfer Error Interrupt Flag bit position. */ - -#define DMA_CH0ERRIF_bm 0x10 /* Channel 0 Block Transfer Error Interrupt Flag bit mask. */ -#define DMA_CH0ERRIF_bp 4 /* Channel 0 Block Transfer Error Interrupt Flag bit position. */ - -#define DMA_CH3TRNIF_bm 0x08 /* Channel 3 Transaction Complete Interrupt Flag bit mask. */ -#define DMA_CH3TRNIF_bp 3 /* Channel 3 Transaction Complete Interrupt Flag bit position. */ - -#define DMA_CH2TRNIF_bm 0x04 /* Channel 2 Transaction Complete Interrupt Flag bit mask. */ -#define DMA_CH2TRNIF_bp 2 /* Channel 2 Transaction Complete Interrupt Flag bit position. */ - -#define DMA_CH1TRNIF_bm 0x02 /* Channel 1 Transaction Complete Interrupt Flag bit mask. */ -#define DMA_CH1TRNIF_bp 1 /* Channel 1 Transaction Complete Interrupt Flag bit position. */ - -#define DMA_CH0TRNIF_bm 0x01 /* Channel 0 Transaction Complete Interrupt Flag bit mask. */ -#define DMA_CH0TRNIF_bp 0 /* Channel 0 Transaction Complete Interrupt Flag bit position. */ - -/* DMA.STATUS bit masks and bit positions */ -#define DMA_CH3BUSY_bm 0x80 /* Channel 3 Block Transfer Busy bit mask. */ -#define DMA_CH3BUSY_bp 7 /* Channel 3 Block Transfer Busy bit position. */ - -#define DMA_CH2BUSY_bm 0x40 /* Channel 2 Block Transfer Busy bit mask. */ -#define DMA_CH2BUSY_bp 6 /* Channel 2 Block Transfer Busy bit position. */ - -#define DMA_CH1BUSY_bm 0x20 /* Channel 1 Block Transfer Busy bit mask. */ -#define DMA_CH1BUSY_bp 5 /* Channel 1 Block Transfer Busy bit position. */ - -#define DMA_CH0BUSY_bm 0x10 /* Channel 0 Block Transfer Busy bit mask. */ -#define DMA_CH0BUSY_bp 4 /* Channel 0 Block Transfer Busy bit position. */ - -#define DMA_CH3PEND_bm 0x08 /* Channel 3 Block Transfer Pending bit mask. */ -#define DMA_CH3PEND_bp 3 /* Channel 3 Block Transfer Pending bit position. */ - -#define DMA_CH2PEND_bm 0x04 /* Channel 2 Block Transfer Pending bit mask. */ -#define DMA_CH2PEND_bp 2 /* Channel 2 Block Transfer Pending bit position. */ - -#define DMA_CH1PEND_bm 0x02 /* Channel 1 Block Transfer Pending bit mask. */ -#define DMA_CH1PEND_bp 1 /* Channel 1 Block Transfer Pending bit position. */ - -#define DMA_CH0PEND_bm 0x01 /* Channel 0 Block Transfer Pending bit mask. */ -#define DMA_CH0PEND_bp 0 /* Channel 0 Block Transfer Pending bit position. */ - -/* EVSYS - Event System */ -/* EVSYS.CH0MUX bit masks and bit positions */ -#define EVSYS_CHMUX_gm 0xFF /* Event Channel 0 Multiplexer group mask. */ -#define EVSYS_CHMUX_gp 0 /* Event Channel 0 Multiplexer group position. */ -#define EVSYS_CHMUX0_bm (1<<0) /* Event Channel 0 Multiplexer bit 0 mask. */ -#define EVSYS_CHMUX0_bp 0 /* Event Channel 0 Multiplexer bit 0 position. */ -#define EVSYS_CHMUX1_bm (1<<1) /* Event Channel 0 Multiplexer bit 1 mask. */ -#define EVSYS_CHMUX1_bp 1 /* Event Channel 0 Multiplexer bit 1 position. */ -#define EVSYS_CHMUX2_bm (1<<2) /* Event Channel 0 Multiplexer bit 2 mask. */ -#define EVSYS_CHMUX2_bp 2 /* Event Channel 0 Multiplexer bit 2 position. */ -#define EVSYS_CHMUX3_bm (1<<3) /* Event Channel 0 Multiplexer bit 3 mask. */ -#define EVSYS_CHMUX3_bp 3 /* Event Channel 0 Multiplexer bit 3 position. */ -#define EVSYS_CHMUX4_bm (1<<4) /* Event Channel 0 Multiplexer bit 4 mask. */ -#define EVSYS_CHMUX4_bp 4 /* Event Channel 0 Multiplexer bit 4 position. */ -#define EVSYS_CHMUX5_bm (1<<5) /* Event Channel 0 Multiplexer bit 5 mask. */ -#define EVSYS_CHMUX5_bp 5 /* Event Channel 0 Multiplexer bit 5 position. */ -#define EVSYS_CHMUX6_bm (1<<6) /* Event Channel 0 Multiplexer bit 6 mask. */ -#define EVSYS_CHMUX6_bp 6 /* Event Channel 0 Multiplexer bit 6 position. */ -#define EVSYS_CHMUX7_bm (1<<7) /* Event Channel 0 Multiplexer bit 7 mask. */ -#define EVSYS_CHMUX7_bp 7 /* Event Channel 0 Multiplexer bit 7 position. */ - -/* EVSYS.CH1MUX bit masks and bit positions */ -/* EVSYS_CHMUX Predefined. */ -/* EVSYS_CHMUX Predefined. */ - -/* EVSYS.CH2MUX bit masks and bit positions */ -/* EVSYS_CHMUX Predefined. */ -/* EVSYS_CHMUX Predefined. */ - -/* EVSYS.CH3MUX bit masks and bit positions */ -/* EVSYS_CHMUX Predefined. */ -/* EVSYS_CHMUX Predefined. */ - -/* EVSYS.CH4MUX bit masks and bit positions */ -/* EVSYS_CHMUX Predefined. */ -/* EVSYS_CHMUX Predefined. */ - -/* EVSYS.CH5MUX bit masks and bit positions */ -/* EVSYS_CHMUX Predefined. */ -/* EVSYS_CHMUX Predefined. */ - -/* EVSYS.CH6MUX bit masks and bit positions */ -/* EVSYS_CHMUX Predefined. */ -/* EVSYS_CHMUX Predefined. */ - -/* EVSYS.CH7MUX bit masks and bit positions */ -/* EVSYS_CHMUX Predefined. */ -/* EVSYS_CHMUX Predefined. */ - -/* EVSYS.CH0CTRL bit masks and bit positions */ -#define EVSYS_QDIRM_gm 0x60 /* Quadrature Decoder Index Recognition Mode group mask. */ -#define EVSYS_QDIRM_gp 5 /* Quadrature Decoder Index Recognition Mode group position. */ -#define EVSYS_QDIRM0_bm (1<<5) /* Quadrature Decoder Index Recognition Mode bit 0 mask. */ -#define EVSYS_QDIRM0_bp 5 /* Quadrature Decoder Index Recognition Mode bit 0 position. */ -#define EVSYS_QDIRM1_bm (1<<6) /* Quadrature Decoder Index Recognition Mode bit 1 mask. */ -#define EVSYS_QDIRM1_bp 6 /* Quadrature Decoder Index Recognition Mode bit 1 position. */ - -#define EVSYS_QDIEN_bm 0x10 /* Quadrature Decoder Index Enable bit mask. */ -#define EVSYS_QDIEN_bp 4 /* Quadrature Decoder Index Enable bit position. */ - -#define EVSYS_QDEN_bm 0x08 /* Quadrature Decoder Enable bit mask. */ -#define EVSYS_QDEN_bp 3 /* Quadrature Decoder Enable bit position. */ - -#define EVSYS_DIGFILT_gm 0x07 /* Digital Filter group mask. */ -#define EVSYS_DIGFILT_gp 0 /* Digital Filter group position. */ -#define EVSYS_DIGFILT0_bm (1<<0) /* Digital Filter bit 0 mask. */ -#define EVSYS_DIGFILT0_bp 0 /* Digital Filter bit 0 position. */ -#define EVSYS_DIGFILT1_bm (1<<1) /* Digital Filter bit 1 mask. */ -#define EVSYS_DIGFILT1_bp 1 /* Digital Filter bit 1 position. */ -#define EVSYS_DIGFILT2_bm (1<<2) /* Digital Filter bit 2 mask. */ -#define EVSYS_DIGFILT2_bp 2 /* Digital Filter bit 2 position. */ - -/* EVSYS.CH1CTRL bit masks and bit positions */ -/* EVSYS_DIGFILT Predefined. */ -/* EVSYS_DIGFILT Predefined. */ - -/* EVSYS.CH2CTRL bit masks and bit positions */ -/* EVSYS_QDIRM Predefined. */ -/* EVSYS_QDIRM Predefined. */ - -/* EVSYS_QDIEN Predefined. */ -/* EVSYS_QDIEN Predefined. */ - -/* EVSYS_QDEN Predefined. */ -/* EVSYS_QDEN Predefined. */ - -/* EVSYS_DIGFILT Predefined. */ -/* EVSYS_DIGFILT Predefined. */ - -/* EVSYS.CH3CTRL bit masks and bit positions */ -/* EVSYS_DIGFILT Predefined. */ -/* EVSYS_DIGFILT Predefined. */ - -/* EVSYS.CH4CTRL bit masks and bit positions */ -/* EVSYS_QDIRM Predefined. */ -/* EVSYS_QDIRM Predefined. */ - -/* EVSYS_QDIEN Predefined. */ -/* EVSYS_QDIEN Predefined. */ - -/* EVSYS_QDEN Predefined. */ -/* EVSYS_QDEN Predefined. */ - -/* EVSYS_DIGFILT Predefined. */ -/* EVSYS_DIGFILT Predefined. */ - -/* EVSYS.CH5CTRL bit masks and bit positions */ -/* EVSYS_DIGFILT Predefined. */ -/* EVSYS_DIGFILT Predefined. */ - -/* EVSYS.CH6CTRL bit masks and bit positions */ -/* EVSYS_DIGFILT Predefined. */ -/* EVSYS_DIGFILT Predefined. */ - -/* EVSYS.CH7CTRL bit masks and bit positions */ -/* EVSYS_DIGFILT Predefined. */ -/* EVSYS_DIGFILT Predefined. */ - -/* NVM - Non Volatile Memory Controller */ -/* NVM.CMD bit masks and bit positions */ -#define NVM_CMD_gm 0x7F /* Command group mask. */ -#define NVM_CMD_gp 0 /* Command group position. */ -#define NVM_CMD0_bm (1<<0) /* Command bit 0 mask. */ -#define NVM_CMD0_bp 0 /* Command bit 0 position. */ -#define NVM_CMD1_bm (1<<1) /* Command bit 1 mask. */ -#define NVM_CMD1_bp 1 /* Command bit 1 position. */ -#define NVM_CMD2_bm (1<<2) /* Command bit 2 mask. */ -#define NVM_CMD2_bp 2 /* Command bit 2 position. */ -#define NVM_CMD3_bm (1<<3) /* Command bit 3 mask. */ -#define NVM_CMD3_bp 3 /* Command bit 3 position. */ -#define NVM_CMD4_bm (1<<4) /* Command bit 4 mask. */ -#define NVM_CMD4_bp 4 /* Command bit 4 position. */ -#define NVM_CMD5_bm (1<<5) /* Command bit 5 mask. */ -#define NVM_CMD5_bp 5 /* Command bit 5 position. */ -#define NVM_CMD6_bm (1<<6) /* Command bit 6 mask. */ -#define NVM_CMD6_bp 6 /* Command bit 6 position. */ - -/* NVM.CTRLA bit masks and bit positions */ -#define NVM_CMDEX_bm 0x01 /* Command Execute bit mask. */ -#define NVM_CMDEX_bp 0 /* Command Execute bit position. */ - -/* NVM.CTRLB bit masks and bit positions */ -#define NVM_EEMAPEN_bm 0x08 /* EEPROM Mapping Enable bit mask. */ -#define NVM_EEMAPEN_bp 3 /* EEPROM Mapping Enable bit position. */ - -#define NVM_FPRM_bm 0x04 /* Flash Power Reduction Enable bit mask. */ -#define NVM_FPRM_bp 2 /* Flash Power Reduction Enable bit position. */ - -#define NVM_EPRM_bm 0x02 /* EEPROM Power Reduction Enable bit mask. */ -#define NVM_EPRM_bp 1 /* EEPROM Power Reduction Enable bit position. */ - -#define NVM_SPMLOCK_bm 0x01 /* SPM Lock bit mask. */ -#define NVM_SPMLOCK_bp 0 /* SPM Lock bit position. */ - -/* NVM.INTCTRL bit masks and bit positions */ -#define NVM_SPMLVL_gm 0x0C /* SPM Interrupt Level group mask. */ -#define NVM_SPMLVL_gp 2 /* SPM Interrupt Level group position. */ -#define NVM_SPMLVL0_bm (1<<2) /* SPM Interrupt Level bit 0 mask. */ -#define NVM_SPMLVL0_bp 2 /* SPM Interrupt Level bit 0 position. */ -#define NVM_SPMLVL1_bm (1<<3) /* SPM Interrupt Level bit 1 mask. */ -#define NVM_SPMLVL1_bp 3 /* SPM Interrupt Level bit 1 position. */ - -#define NVM_EELVL_gm 0x03 /* EEPROM Interrupt Level group mask. */ -#define NVM_EELVL_gp 0 /* EEPROM Interrupt Level group position. */ -#define NVM_EELVL0_bm (1<<0) /* EEPROM Interrupt Level bit 0 mask. */ -#define NVM_EELVL0_bp 0 /* EEPROM Interrupt Level bit 0 position. */ -#define NVM_EELVL1_bm (1<<1) /* EEPROM Interrupt Level bit 1 mask. */ -#define NVM_EELVL1_bp 1 /* EEPROM Interrupt Level bit 1 position. */ - -/* NVM.STATUS bit masks and bit positions */ -#define NVM_NVMBUSY_bm 0x80 /* Non-volatile Memory Busy bit mask. */ -#define NVM_NVMBUSY_bp 7 /* Non-volatile Memory Busy bit position. */ - -#define NVM_FBUSY_bm 0x40 /* Flash Memory Busy bit mask. */ -#define NVM_FBUSY_bp 6 /* Flash Memory Busy bit position. */ - -#define NVM_EELOAD_bm 0x02 /* EEPROM Page Buffer Active Loading bit mask. */ -#define NVM_EELOAD_bp 1 /* EEPROM Page Buffer Active Loading bit position. */ - -#define NVM_FLOAD_bm 0x01 /* Flash Page Buffer Active Loading bit mask. */ -#define NVM_FLOAD_bp 0 /* Flash Page Buffer Active Loading bit position. */ - -/* NVM.LOCKBITS bit masks and bit positions */ -#define NVM_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ -#define NVM_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ -#define NVM_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ -#define NVM_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ -#define NVM_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ -#define NVM_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ - -#define NVM_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ -#define NVM_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ -#define NVM_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ -#define NVM_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ -#define NVM_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ -#define NVM_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ - -#define NVM_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ -#define NVM_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ -#define NVM_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ -#define NVM_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ -#define NVM_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ -#define NVM_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ - -#define NVM_LB_gm 0x03 /* Lock Bits group mask. */ -#define NVM_LB_gp 0 /* Lock Bits group position. */ -#define NVM_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ -#define NVM_LB0_bp 0 /* Lock Bits bit 0 position. */ -#define NVM_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ -#define NVM_LB1_bp 1 /* Lock Bits bit 1 position. */ - -/* ADC - Analog/Digital Converter */ -/* ADC_CH.CTRL bit masks and bit positions */ -#define ADC_CH_START_bm 0x80 /* Channel Start Conversion bit mask. */ -#define ADC_CH_START_bp 7 /* Channel Start Conversion bit position. */ - -#define ADC_CH_GAIN_gm 0x1C /* Gain Factor group mask. */ -#define ADC_CH_GAIN_gp 2 /* Gain Factor group position. */ -#define ADC_CH_GAIN0_bm (1<<2) /* Gain Factor bit 0 mask. */ -#define ADC_CH_GAIN0_bp 2 /* Gain Factor bit 0 position. */ -#define ADC_CH_GAIN1_bm (1<<3) /* Gain Factor bit 1 mask. */ -#define ADC_CH_GAIN1_bp 3 /* Gain Factor bit 1 position. */ -#define ADC_CH_GAIN2_bm (1<<4) /* Gain Factor bit 2 mask. */ -#define ADC_CH_GAIN2_bp 4 /* Gain Factor bit 2 position. */ - -#define ADC_CH_INPUTMODE_gm 0x03 /* Input Mode Select group mask. */ -#define ADC_CH_INPUTMODE_gp 0 /* Input Mode Select group position. */ -#define ADC_CH_INPUTMODE0_bm (1<<0) /* Input Mode Select bit 0 mask. */ -#define ADC_CH_INPUTMODE0_bp 0 /* Input Mode Select bit 0 position. */ -#define ADC_CH_INPUTMODE1_bm (1<<1) /* Input Mode Select bit 1 mask. */ -#define ADC_CH_INPUTMODE1_bp 1 /* Input Mode Select bit 1 position. */ - -/* ADC_CH.MUXCTRL bit masks and bit positions */ -#define ADC_CH_MUXPOS_gm 0x78 /* MUX selection on Positive ADC input group mask. */ -#define ADC_CH_MUXPOS_gp 3 /* MUX selection on Positive ADC input group position. */ -#define ADC_CH_MUXPOS0_bm (1<<3) /* MUX selection on Positive ADC input bit 0 mask. */ -#define ADC_CH_MUXPOS0_bp 3 /* MUX selection on Positive ADC input bit 0 position. */ -#define ADC_CH_MUXPOS1_bm (1<<4) /* MUX selection on Positive ADC input bit 1 mask. */ -#define ADC_CH_MUXPOS1_bp 4 /* MUX selection on Positive ADC input bit 1 position. */ -#define ADC_CH_MUXPOS2_bm (1<<5) /* MUX selection on Positive ADC input bit 2 mask. */ -#define ADC_CH_MUXPOS2_bp 5 /* MUX selection on Positive ADC input bit 2 position. */ -#define ADC_CH_MUXPOS3_bm (1<<6) /* MUX selection on Positive ADC input bit 3 mask. */ -#define ADC_CH_MUXPOS3_bp 6 /* MUX selection on Positive ADC input bit 3 position. */ - -#define ADC_CH_MUXINT_gm 0x78 /* MUX selection on Internal ADC input group mask. */ -#define ADC_CH_MUXINT_gp 3 /* MUX selection on Internal ADC input group position. */ -#define ADC_CH_MUXINT0_bm (1<<3) /* MUX selection on Internal ADC input bit 0 mask. */ -#define ADC_CH_MUXINT0_bp 3 /* MUX selection on Internal ADC input bit 0 position. */ -#define ADC_CH_MUXINT1_bm (1<<4) /* MUX selection on Internal ADC input bit 1 mask. */ -#define ADC_CH_MUXINT1_bp 4 /* MUX selection on Internal ADC input bit 1 position. */ -#define ADC_CH_MUXINT2_bm (1<<5) /* MUX selection on Internal ADC input bit 2 mask. */ -#define ADC_CH_MUXINT2_bp 5 /* MUX selection on Internal ADC input bit 2 position. */ -#define ADC_CH_MUXINT3_bm (1<<6) /* MUX selection on Internal ADC input bit 3 mask. */ -#define ADC_CH_MUXINT3_bp 6 /* MUX selection on Internal ADC input bit 3 position. */ - -#define ADC_CH_MUXNEG_gm 0x07 /* MUX selection on Negative ADC input group mask. */ -#define ADC_CH_MUXNEG_gp 0 /* MUX selection on Negative ADC input group position. */ -#define ADC_CH_MUXNEG0_bm (1<<0) /* MUX selection on Negative ADC input bit 0 mask. */ -#define ADC_CH_MUXNEG0_bp 0 /* MUX selection on Negative ADC input bit 0 position. */ -#define ADC_CH_MUXNEG1_bm (1<<1) /* MUX selection on Negative ADC input bit 1 mask. */ -#define ADC_CH_MUXNEG1_bp 1 /* MUX selection on Negative ADC input bit 1 position. */ -#define ADC_CH_MUXNEG2_bm (1<<2) /* MUX selection on Negative ADC input bit 2 mask. */ -#define ADC_CH_MUXNEG2_bp 2 /* MUX selection on Negative ADC input bit 2 position. */ - -/* ADC_CH.INTCTRL bit masks and bit positions */ -#define ADC_CH_INTMODE_gm 0x0C /* Interrupt Mode group mask. */ -#define ADC_CH_INTMODE_gp 2 /* Interrupt Mode group position. */ -#define ADC_CH_INTMODE0_bm (1<<2) /* Interrupt Mode bit 0 mask. */ -#define ADC_CH_INTMODE0_bp 2 /* Interrupt Mode bit 0 position. */ -#define ADC_CH_INTMODE1_bm (1<<3) /* Interrupt Mode bit 1 mask. */ -#define ADC_CH_INTMODE1_bp 3 /* Interrupt Mode bit 1 position. */ - -#define ADC_CH_INTLVL_gm 0x03 /* Interrupt Level group mask. */ -#define ADC_CH_INTLVL_gp 0 /* Interrupt Level group position. */ -#define ADC_CH_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */ -#define ADC_CH_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */ -#define ADC_CH_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ -#define ADC_CH_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */ - -/* ADC_CH.INTFLAGS bit masks and bit positions */ -#define ADC_CH_CHIF_bm 0x01 /* Channel Interrupt Flag bit mask. */ -#define ADC_CH_CHIF_bp 0 /* Channel Interrupt Flag bit position. */ - -/* ADC_CH.SCAN bit masks and bit positions */ -#define ADC_CH_OFFSET_gm 0xF0 /* Positive MUX setting offset group mask. */ -#define ADC_CH_OFFSET_gp 4 /* Positive MUX setting offset group position. */ -#define ADC_CH_OFFSET0_bm (1<<4) /* Positive MUX setting offset bit 0 mask. */ -#define ADC_CH_OFFSET0_bp 4 /* Positive MUX setting offset bit 0 position. */ -#define ADC_CH_OFFSET1_bm (1<<5) /* Positive MUX setting offset bit 1 mask. */ -#define ADC_CH_OFFSET1_bp 5 /* Positive MUX setting offset bit 1 position. */ -#define ADC_CH_OFFSET2_bm (1<<6) /* Positive MUX setting offset bit 2 mask. */ -#define ADC_CH_OFFSET2_bp 6 /* Positive MUX setting offset bit 2 position. */ -#define ADC_CH_OFFSET3_bm (1<<7) /* Positive MUX setting offset bit 3 mask. */ -#define ADC_CH_OFFSET3_bp 7 /* Positive MUX setting offset bit 3 position. */ - -#define ADC_CH_SCANNUM_gm 0x0F /* Number of Channels included in scan group mask. */ -#define ADC_CH_SCANNUM_gp 0 /* Number of Channels included in scan group position. */ -#define ADC_CH_SCANNUM0_bm (1<<0) /* Number of Channels included in scan bit 0 mask. */ -#define ADC_CH_SCANNUM0_bp 0 /* Number of Channels included in scan bit 0 position. */ -#define ADC_CH_SCANNUM1_bm (1<<1) /* Number of Channels included in scan bit 1 mask. */ -#define ADC_CH_SCANNUM1_bp 1 /* Number of Channels included in scan bit 1 position. */ -#define ADC_CH_SCANNUM2_bm (1<<2) /* Number of Channels included in scan bit 2 mask. */ -#define ADC_CH_SCANNUM2_bp 2 /* Number of Channels included in scan bit 2 position. */ -#define ADC_CH_SCANNUM3_bm (1<<3) /* Number of Channels included in scan bit 3 mask. */ -#define ADC_CH_SCANNUM3_bp 3 /* Number of Channels included in scan bit 3 position. */ - -/* ADC.CTRLA bit masks and bit positions */ -#define ADC_DMASEL_gm 0xC0 /* DMA Selection group mask. */ -#define ADC_DMASEL_gp 6 /* DMA Selection group position. */ -#define ADC_DMASEL0_bm (1<<6) /* DMA Selection bit 0 mask. */ -#define ADC_DMASEL0_bp 6 /* DMA Selection bit 0 position. */ -#define ADC_DMASEL1_bm (1<<7) /* DMA Selection bit 1 mask. */ -#define ADC_DMASEL1_bp 7 /* DMA Selection bit 1 position. */ - -#define ADC_CH3START_bm 0x20 /* Channel 3 Start Conversion bit mask. */ -#define ADC_CH3START_bp 5 /* Channel 3 Start Conversion bit position. */ - -#define ADC_CH2START_bm 0x10 /* Channel 2 Start Conversion bit mask. */ -#define ADC_CH2START_bp 4 /* Channel 2 Start Conversion bit position. */ - -#define ADC_CH1START_bm 0x08 /* Channel 1 Start Conversion bit mask. */ -#define ADC_CH1START_bp 3 /* Channel 1 Start Conversion bit position. */ - -#define ADC_CH0START_bm 0x04 /* Channel 0 Start Conversion bit mask. */ -#define ADC_CH0START_bp 2 /* Channel 0 Start Conversion bit position. */ - -#define ADC_FLUSH_bm 0x02 /* Flush Pipeline bit mask. */ -#define ADC_FLUSH_bp 1 /* Flush Pipeline bit position. */ - -#define ADC_ENABLE_bm 0x01 /* Enable ADC bit mask. */ -#define ADC_ENABLE_bp 0 /* Enable ADC bit position. */ - -/* ADC.CTRLB bit masks and bit positions */ -#define ADC_IMPMODE_bm 0x80 /* Gain Stage Impedance Mode bit mask. */ -#define ADC_IMPMODE_bp 7 /* Gain Stage Impedance Mode bit position. */ - -#define ADC_CURRLIMIT_gm 0x60 /* Current Limitation group mask. */ -#define ADC_CURRLIMIT_gp 5 /* Current Limitation group position. */ -#define ADC_CURRLIMIT0_bm (1<<5) /* Current Limitation bit 0 mask. */ -#define ADC_CURRLIMIT0_bp 5 /* Current Limitation bit 0 position. */ -#define ADC_CURRLIMIT1_bm (1<<6) /* Current Limitation bit 1 mask. */ -#define ADC_CURRLIMIT1_bp 6 /* Current Limitation bit 1 position. */ - -#define ADC_CONMODE_bm 0x10 /* Conversion Mode bit mask. */ -#define ADC_CONMODE_bp 4 /* Conversion Mode bit position. */ - -#define ADC_FREERUN_bm 0x08 /* Free Running Mode Enable bit mask. */ -#define ADC_FREERUN_bp 3 /* Free Running Mode Enable bit position. */ - -#define ADC_RESOLUTION_gm 0x06 /* Result Resolution group mask. */ -#define ADC_RESOLUTION_gp 1 /* Result Resolution group position. */ -#define ADC_RESOLUTION0_bm (1<<1) /* Result Resolution bit 0 mask. */ -#define ADC_RESOLUTION0_bp 1 /* Result Resolution bit 0 position. */ -#define ADC_RESOLUTION1_bm (1<<2) /* Result Resolution bit 1 mask. */ -#define ADC_RESOLUTION1_bp 2 /* Result Resolution bit 1 position. */ - -/* ADC.REFCTRL bit masks and bit positions */ -#define ADC_REFSEL_gm 0x70 /* Reference Selection group mask. */ -#define ADC_REFSEL_gp 4 /* Reference Selection group position. */ -#define ADC_REFSEL0_bm (1<<4) /* Reference Selection bit 0 mask. */ -#define ADC_REFSEL0_bp 4 /* Reference Selection bit 0 position. */ -#define ADC_REFSEL1_bm (1<<5) /* Reference Selection bit 1 mask. */ -#define ADC_REFSEL1_bp 5 /* Reference Selection bit 1 position. */ -#define ADC_REFSEL2_bm (1<<6) /* Reference Selection bit 2 mask. */ -#define ADC_REFSEL2_bp 6 /* Reference Selection bit 2 position. */ - -#define ADC_BANDGAP_bm 0x02 /* Bandgap enable bit mask. */ -#define ADC_BANDGAP_bp 1 /* Bandgap enable bit position. */ - -#define ADC_TEMPREF_bm 0x01 /* Temperature Reference Enable bit mask. */ -#define ADC_TEMPREF_bp 0 /* Temperature Reference Enable bit position. */ - -/* ADC.EVCTRL bit masks and bit positions */ -#define ADC_SWEEP_gm 0xC0 /* Channel Sweep Selection group mask. */ -#define ADC_SWEEP_gp 6 /* Channel Sweep Selection group position. */ -#define ADC_SWEEP0_bm (1<<6) /* Channel Sweep Selection bit 0 mask. */ -#define ADC_SWEEP0_bp 6 /* Channel Sweep Selection bit 0 position. */ -#define ADC_SWEEP1_bm (1<<7) /* Channel Sweep Selection bit 1 mask. */ -#define ADC_SWEEP1_bp 7 /* Channel Sweep Selection bit 1 position. */ - -#define ADC_EVSEL_gm 0x38 /* Event Input Select group mask. */ -#define ADC_EVSEL_gp 3 /* Event Input Select group position. */ -#define ADC_EVSEL0_bm (1<<3) /* Event Input Select bit 0 mask. */ -#define ADC_EVSEL0_bp 3 /* Event Input Select bit 0 position. */ -#define ADC_EVSEL1_bm (1<<4) /* Event Input Select bit 1 mask. */ -#define ADC_EVSEL1_bp 4 /* Event Input Select bit 1 position. */ -#define ADC_EVSEL2_bm (1<<5) /* Event Input Select bit 2 mask. */ -#define ADC_EVSEL2_bp 5 /* Event Input Select bit 2 position. */ - -#define ADC_EVACT_gm 0x07 /* Event Action Select group mask. */ -#define ADC_EVACT_gp 0 /* Event Action Select group position. */ -#define ADC_EVACT0_bm (1<<0) /* Event Action Select bit 0 mask. */ -#define ADC_EVACT0_bp 0 /* Event Action Select bit 0 position. */ -#define ADC_EVACT1_bm (1<<1) /* Event Action Select bit 1 mask. */ -#define ADC_EVACT1_bp 1 /* Event Action Select bit 1 position. */ -#define ADC_EVACT2_bm (1<<2) /* Event Action Select bit 2 mask. */ -#define ADC_EVACT2_bp 2 /* Event Action Select bit 2 position. */ - -/* ADC.PRESCALER bit masks and bit positions */ -#define ADC_PRESCALER_gm 0x07 /* Clock Prescaler Selection group mask. */ -#define ADC_PRESCALER_gp 0 /* Clock Prescaler Selection group position. */ -#define ADC_PRESCALER0_bm (1<<0) /* Clock Prescaler Selection bit 0 mask. */ -#define ADC_PRESCALER0_bp 0 /* Clock Prescaler Selection bit 0 position. */ -#define ADC_PRESCALER1_bm (1<<1) /* Clock Prescaler Selection bit 1 mask. */ -#define ADC_PRESCALER1_bp 1 /* Clock Prescaler Selection bit 1 position. */ -#define ADC_PRESCALER2_bm (1<<2) /* Clock Prescaler Selection bit 2 mask. */ -#define ADC_PRESCALER2_bp 2 /* Clock Prescaler Selection bit 2 position. */ - -/* ADC.INTFLAGS bit masks and bit positions */ -#define ADC_CH3IF_bm 0x08 /* Channel 3 Interrupt Flag bit mask. */ -#define ADC_CH3IF_bp 3 /* Channel 3 Interrupt Flag bit position. */ - -#define ADC_CH2IF_bm 0x04 /* Channel 2 Interrupt Flag bit mask. */ -#define ADC_CH2IF_bp 2 /* Channel 2 Interrupt Flag bit position. */ - -#define ADC_CH1IF_bm 0x02 /* Channel 1 Interrupt Flag bit mask. */ -#define ADC_CH1IF_bp 1 /* Channel 1 Interrupt Flag bit position. */ - -#define ADC_CH0IF_bm 0x01 /* Channel 0 Interrupt Flag bit mask. */ -#define ADC_CH0IF_bp 0 /* Channel 0 Interrupt Flag bit position. */ - -/* DAC - Digital/Analog Converter */ -/* DAC.CTRLA bit masks and bit positions */ -#define DAC_IDOEN_bm 0x10 /* Internal Output Enable bit mask. */ -#define DAC_IDOEN_bp 4 /* Internal Output Enable bit position. */ - -#define DAC_CH1EN_bm 0x08 /* Channel 1 Output Enable bit mask. */ -#define DAC_CH1EN_bp 3 /* Channel 1 Output Enable bit position. */ - -#define DAC_CH0EN_bm 0x04 /* Channel 0 Output Enable bit mask. */ -#define DAC_CH0EN_bp 2 /* Channel 0 Output Enable bit position. */ - -#define DAC_LPMODE_bm 0x02 /* Low Power Mode bit mask. */ -#define DAC_LPMODE_bp 1 /* Low Power Mode bit position. */ - -#define DAC_ENABLE_bm 0x01 /* Enable bit mask. */ -#define DAC_ENABLE_bp 0 /* Enable bit position. */ - -/* DAC.CTRLB bit masks and bit positions */ -#define DAC_CHSEL_gm 0x60 /* Channel Select group mask. */ -#define DAC_CHSEL_gp 5 /* Channel Select group position. */ -#define DAC_CHSEL0_bm (1<<5) /* Channel Select bit 0 mask. */ -#define DAC_CHSEL0_bp 5 /* Channel Select bit 0 position. */ -#define DAC_CHSEL1_bm (1<<6) /* Channel Select bit 1 mask. */ -#define DAC_CHSEL1_bp 6 /* Channel Select bit 1 position. */ - -#define DAC_CH1TRIG_bm 0x02 /* Channel 1 Event Trig Enable bit mask. */ -#define DAC_CH1TRIG_bp 1 /* Channel 1 Event Trig Enable bit position. */ - -#define DAC_CH0TRIG_bm 0x01 /* Channel 0 Event Trig Enable bit mask. */ -#define DAC_CH0TRIG_bp 0 /* Channel 0 Event Trig Enable bit position. */ - -/* DAC.CTRLC bit masks and bit positions */ -#define DAC_REFSEL_gm 0x18 /* Reference Select group mask. */ -#define DAC_REFSEL_gp 3 /* Reference Select group position. */ -#define DAC_REFSEL0_bm (1<<3) /* Reference Select bit 0 mask. */ -#define DAC_REFSEL0_bp 3 /* Reference Select bit 0 position. */ -#define DAC_REFSEL1_bm (1<<4) /* Reference Select bit 1 mask. */ -#define DAC_REFSEL1_bp 4 /* Reference Select bit 1 position. */ - -#define DAC_LEFTADJ_bm 0x01 /* Left-adjust Result bit mask. */ -#define DAC_LEFTADJ_bp 0 /* Left-adjust Result bit position. */ - -/* DAC.EVCTRL bit masks and bit positions */ -#define DAC_EVSPLIT_bm 0x08 /* Separate Event Channel Input for Channel 1 bit mask. */ -#define DAC_EVSPLIT_bp 3 /* Separate Event Channel Input for Channel 1 bit position. */ - -#define DAC_EVSEL_gm 0x07 /* Event Input Selection group mask. */ -#define DAC_EVSEL_gp 0 /* Event Input Selection group position. */ -#define DAC_EVSEL0_bm (1<<0) /* Event Input Selection bit 0 mask. */ -#define DAC_EVSEL0_bp 0 /* Event Input Selection bit 0 position. */ -#define DAC_EVSEL1_bm (1<<1) /* Event Input Selection bit 1 mask. */ -#define DAC_EVSEL1_bp 1 /* Event Input Selection bit 1 position. */ -#define DAC_EVSEL2_bm (1<<2) /* Event Input Selection bit 2 mask. */ -#define DAC_EVSEL2_bp 2 /* Event Input Selection bit 2 position. */ - -/* DAC.STATUS bit masks and bit positions */ -#define DAC_CH1DRE_bm 0x02 /* Channel 1 Data Register Empty bit mask. */ -#define DAC_CH1DRE_bp 1 /* Channel 1 Data Register Empty bit position. */ - -#define DAC_CH0DRE_bm 0x01 /* Channel 0 Data Register Empty bit mask. */ -#define DAC_CH0DRE_bp 0 /* Channel 0 Data Register Empty bit position. */ - -/* DAC.CH0GAINCAL bit masks and bit positions */ -#define DAC_CH0GAINCAL_gm 0x7F /* Gain Calibration group mask. */ -#define DAC_CH0GAINCAL_gp 0 /* Gain Calibration group position. */ -#define DAC_CH0GAINCAL0_bm (1<<0) /* Gain Calibration bit 0 mask. */ -#define DAC_CH0GAINCAL0_bp 0 /* Gain Calibration bit 0 position. */ -#define DAC_CH0GAINCAL1_bm (1<<1) /* Gain Calibration bit 1 mask. */ -#define DAC_CH0GAINCAL1_bp 1 /* Gain Calibration bit 1 position. */ -#define DAC_CH0GAINCAL2_bm (1<<2) /* Gain Calibration bit 2 mask. */ -#define DAC_CH0GAINCAL2_bp 2 /* Gain Calibration bit 2 position. */ -#define DAC_CH0GAINCAL3_bm (1<<3) /* Gain Calibration bit 3 mask. */ -#define DAC_CH0GAINCAL3_bp 3 /* Gain Calibration bit 3 position. */ -#define DAC_CH0GAINCAL4_bm (1<<4) /* Gain Calibration bit 4 mask. */ -#define DAC_CH0GAINCAL4_bp 4 /* Gain Calibration bit 4 position. */ -#define DAC_CH0GAINCAL5_bm (1<<5) /* Gain Calibration bit 5 mask. */ -#define DAC_CH0GAINCAL5_bp 5 /* Gain Calibration bit 5 position. */ -#define DAC_CH0GAINCAL6_bm (1<<6) /* Gain Calibration bit 6 mask. */ -#define DAC_CH0GAINCAL6_bp 6 /* Gain Calibration bit 6 position. */ - -/* DAC.CH0OFFSETCAL bit masks and bit positions */ -#define DAC_CH0OFFSETCAL_gm 0x7F /* Offset Calibration group mask. */ -#define DAC_CH0OFFSETCAL_gp 0 /* Offset Calibration group position. */ -#define DAC_CH0OFFSETCAL0_bm (1<<0) /* Offset Calibration bit 0 mask. */ -#define DAC_CH0OFFSETCAL0_bp 0 /* Offset Calibration bit 0 position. */ -#define DAC_CH0OFFSETCAL1_bm (1<<1) /* Offset Calibration bit 1 mask. */ -#define DAC_CH0OFFSETCAL1_bp 1 /* Offset Calibration bit 1 position. */ -#define DAC_CH0OFFSETCAL2_bm (1<<2) /* Offset Calibration bit 2 mask. */ -#define DAC_CH0OFFSETCAL2_bp 2 /* Offset Calibration bit 2 position. */ -#define DAC_CH0OFFSETCAL3_bm (1<<3) /* Offset Calibration bit 3 mask. */ -#define DAC_CH0OFFSETCAL3_bp 3 /* Offset Calibration bit 3 position. */ -#define DAC_CH0OFFSETCAL4_bm (1<<4) /* Offset Calibration bit 4 mask. */ -#define DAC_CH0OFFSETCAL4_bp 4 /* Offset Calibration bit 4 position. */ -#define DAC_CH0OFFSETCAL5_bm (1<<5) /* Offset Calibration bit 5 mask. */ -#define DAC_CH0OFFSETCAL5_bp 5 /* Offset Calibration bit 5 position. */ -#define DAC_CH0OFFSETCAL6_bm (1<<6) /* Offset Calibration bit 6 mask. */ -#define DAC_CH0OFFSETCAL6_bp 6 /* Offset Calibration bit 6 position. */ - -/* DAC.CH1GAINCAL bit masks and bit positions */ -#define DAC_CH1GAINCAL_gm 0x7F /* Gain Calibration group mask. */ -#define DAC_CH1GAINCAL_gp 0 /* Gain Calibration group position. */ -#define DAC_CH1GAINCAL0_bm (1<<0) /* Gain Calibration bit 0 mask. */ -#define DAC_CH1GAINCAL0_bp 0 /* Gain Calibration bit 0 position. */ -#define DAC_CH1GAINCAL1_bm (1<<1) /* Gain Calibration bit 1 mask. */ -#define DAC_CH1GAINCAL1_bp 1 /* Gain Calibration bit 1 position. */ -#define DAC_CH1GAINCAL2_bm (1<<2) /* Gain Calibration bit 2 mask. */ -#define DAC_CH1GAINCAL2_bp 2 /* Gain Calibration bit 2 position. */ -#define DAC_CH1GAINCAL3_bm (1<<3) /* Gain Calibration bit 3 mask. */ -#define DAC_CH1GAINCAL3_bp 3 /* Gain Calibration bit 3 position. */ -#define DAC_CH1GAINCAL4_bm (1<<4) /* Gain Calibration bit 4 mask. */ -#define DAC_CH1GAINCAL4_bp 4 /* Gain Calibration bit 4 position. */ -#define DAC_CH1GAINCAL5_bm (1<<5) /* Gain Calibration bit 5 mask. */ -#define DAC_CH1GAINCAL5_bp 5 /* Gain Calibration bit 5 position. */ -#define DAC_CH1GAINCAL6_bm (1<<6) /* Gain Calibration bit 6 mask. */ -#define DAC_CH1GAINCAL6_bp 6 /* Gain Calibration bit 6 position. */ - -/* DAC.CH1OFFSETCAL bit masks and bit positions */ -#define DAC_CH1OFFSETCAL_gm 0x7F /* Offset Calibration group mask. */ -#define DAC_CH1OFFSETCAL_gp 0 /* Offset Calibration group position. */ -#define DAC_CH1OFFSETCAL0_bm (1<<0) /* Offset Calibration bit 0 mask. */ -#define DAC_CH1OFFSETCAL0_bp 0 /* Offset Calibration bit 0 position. */ -#define DAC_CH1OFFSETCAL1_bm (1<<1) /* Offset Calibration bit 1 mask. */ -#define DAC_CH1OFFSETCAL1_bp 1 /* Offset Calibration bit 1 position. */ -#define DAC_CH1OFFSETCAL2_bm (1<<2) /* Offset Calibration bit 2 mask. */ -#define DAC_CH1OFFSETCAL2_bp 2 /* Offset Calibration bit 2 position. */ -#define DAC_CH1OFFSETCAL3_bm (1<<3) /* Offset Calibration bit 3 mask. */ -#define DAC_CH1OFFSETCAL3_bp 3 /* Offset Calibration bit 3 position. */ -#define DAC_CH1OFFSETCAL4_bm (1<<4) /* Offset Calibration bit 4 mask. */ -#define DAC_CH1OFFSETCAL4_bp 4 /* Offset Calibration bit 4 position. */ -#define DAC_CH1OFFSETCAL5_bm (1<<5) /* Offset Calibration bit 5 mask. */ -#define DAC_CH1OFFSETCAL5_bp 5 /* Offset Calibration bit 5 position. */ -#define DAC_CH1OFFSETCAL6_bm (1<<6) /* Offset Calibration bit 6 mask. */ -#define DAC_CH1OFFSETCAL6_bp 6 /* Offset Calibration bit 6 position. */ - -/* AC - Analog Comparator */ -/* AC.AC0CTRL bit masks and bit positions */ -#define AC_INTMODE_gm 0xC0 /* Interrupt Mode group mask. */ -#define AC_INTMODE_gp 6 /* Interrupt Mode group position. */ -#define AC_INTMODE0_bm (1<<6) /* Interrupt Mode bit 0 mask. */ -#define AC_INTMODE0_bp 6 /* Interrupt Mode bit 0 position. */ -#define AC_INTMODE1_bm (1<<7) /* Interrupt Mode bit 1 mask. */ -#define AC_INTMODE1_bp 7 /* Interrupt Mode bit 1 position. */ - -#define AC_INTLVL_gm 0x30 /* Interrupt Level group mask. */ -#define AC_INTLVL_gp 4 /* Interrupt Level group position. */ -#define AC_INTLVL0_bm (1<<4) /* Interrupt Level bit 0 mask. */ -#define AC_INTLVL0_bp 4 /* Interrupt Level bit 0 position. */ -#define AC_INTLVL1_bm (1<<5) /* Interrupt Level bit 1 mask. */ -#define AC_INTLVL1_bp 5 /* Interrupt Level bit 1 position. */ - -#define AC_HSMODE_bm 0x08 /* High-speed Mode bit mask. */ -#define AC_HSMODE_bp 3 /* High-speed Mode bit position. */ - -#define AC_HYSMODE_gm 0x06 /* Hysteresis Mode group mask. */ -#define AC_HYSMODE_gp 1 /* Hysteresis Mode group position. */ -#define AC_HYSMODE0_bm (1<<1) /* Hysteresis Mode bit 0 mask. */ -#define AC_HYSMODE0_bp 1 /* Hysteresis Mode bit 0 position. */ -#define AC_HYSMODE1_bm (1<<2) /* Hysteresis Mode bit 1 mask. */ -#define AC_HYSMODE1_bp 2 /* Hysteresis Mode bit 1 position. */ - -#define AC_ENABLE_bm 0x01 /* Enable bit mask. */ -#define AC_ENABLE_bp 0 /* Enable bit position. */ - -/* AC.AC1CTRL bit masks and bit positions */ -/* AC_INTMODE Predefined. */ -/* AC_INTMODE Predefined. */ - -/* AC_INTLVL Predefined. */ -/* AC_INTLVL Predefined. */ - -/* AC_HSMODE Predefined. */ -/* AC_HSMODE Predefined. */ - -/* AC_HYSMODE Predefined. */ -/* AC_HYSMODE Predefined. */ - -/* AC_ENABLE Predefined. */ -/* AC_ENABLE Predefined. */ - -/* AC.AC0MUXCTRL bit masks and bit positions */ -#define AC_MUXPOS_gm 0x38 /* MUX Positive Input group mask. */ -#define AC_MUXPOS_gp 3 /* MUX Positive Input group position. */ -#define AC_MUXPOS0_bm (1<<3) /* MUX Positive Input bit 0 mask. */ -#define AC_MUXPOS0_bp 3 /* MUX Positive Input bit 0 position. */ -#define AC_MUXPOS1_bm (1<<4) /* MUX Positive Input bit 1 mask. */ -#define AC_MUXPOS1_bp 4 /* MUX Positive Input bit 1 position. */ -#define AC_MUXPOS2_bm (1<<5) /* MUX Positive Input bit 2 mask. */ -#define AC_MUXPOS2_bp 5 /* MUX Positive Input bit 2 position. */ - -#define AC_MUXNEG_gm 0x07 /* MUX Negative Input group mask. */ -#define AC_MUXNEG_gp 0 /* MUX Negative Input group position. */ -#define AC_MUXNEG0_bm (1<<0) /* MUX Negative Input bit 0 mask. */ -#define AC_MUXNEG0_bp 0 /* MUX Negative Input bit 0 position. */ -#define AC_MUXNEG1_bm (1<<1) /* MUX Negative Input bit 1 mask. */ -#define AC_MUXNEG1_bp 1 /* MUX Negative Input bit 1 position. */ -#define AC_MUXNEG2_bm (1<<2) /* MUX Negative Input bit 2 mask. */ -#define AC_MUXNEG2_bp 2 /* MUX Negative Input bit 2 position. */ - -/* AC.AC1MUXCTRL bit masks and bit positions */ -/* AC_MUXPOS Predefined. */ -/* AC_MUXPOS Predefined. */ - -/* AC_MUXNEG Predefined. */ -/* AC_MUXNEG Predefined. */ - -/* AC.CTRLA bit masks and bit positions */ -#define AC_AC1OUT_bm 0x02 /* Analog Comparator 1 Output Enable bit mask. */ -#define AC_AC1OUT_bp 1 /* Analog Comparator 1 Output Enable bit position. */ - -#define AC_AC0OUT_bm 0x01 /* Analog Comparator 0 Output Enable bit mask. */ -#define AC_AC0OUT_bp 0 /* Analog Comparator 0 Output Enable bit position. */ - -/* AC.CTRLB bit masks and bit positions */ -#define AC_SCALEFAC_gm 0x3F /* VCC Voltage Scaler Factor group mask. */ -#define AC_SCALEFAC_gp 0 /* VCC Voltage Scaler Factor group position. */ -#define AC_SCALEFAC0_bm (1<<0) /* VCC Voltage Scaler Factor bit 0 mask. */ -#define AC_SCALEFAC0_bp 0 /* VCC Voltage Scaler Factor bit 0 position. */ -#define AC_SCALEFAC1_bm (1<<1) /* VCC Voltage Scaler Factor bit 1 mask. */ -#define AC_SCALEFAC1_bp 1 /* VCC Voltage Scaler Factor bit 1 position. */ -#define AC_SCALEFAC2_bm (1<<2) /* VCC Voltage Scaler Factor bit 2 mask. */ -#define AC_SCALEFAC2_bp 2 /* VCC Voltage Scaler Factor bit 2 position. */ -#define AC_SCALEFAC3_bm (1<<3) /* VCC Voltage Scaler Factor bit 3 mask. */ -#define AC_SCALEFAC3_bp 3 /* VCC Voltage Scaler Factor bit 3 position. */ -#define AC_SCALEFAC4_bm (1<<4) /* VCC Voltage Scaler Factor bit 4 mask. */ -#define AC_SCALEFAC4_bp 4 /* VCC Voltage Scaler Factor bit 4 position. */ -#define AC_SCALEFAC5_bm (1<<5) /* VCC Voltage Scaler Factor bit 5 mask. */ -#define AC_SCALEFAC5_bp 5 /* VCC Voltage Scaler Factor bit 5 position. */ - -/* AC.WINCTRL bit masks and bit positions */ -#define AC_WEN_bm 0x10 /* Window Mode Enable bit mask. */ -#define AC_WEN_bp 4 /* Window Mode Enable bit position. */ - -#define AC_WINTMODE_gm 0x0C /* Window Interrupt Mode group mask. */ -#define AC_WINTMODE_gp 2 /* Window Interrupt Mode group position. */ -#define AC_WINTMODE0_bm (1<<2) /* Window Interrupt Mode bit 0 mask. */ -#define AC_WINTMODE0_bp 2 /* Window Interrupt Mode bit 0 position. */ -#define AC_WINTMODE1_bm (1<<3) /* Window Interrupt Mode bit 1 mask. */ -#define AC_WINTMODE1_bp 3 /* Window Interrupt Mode bit 1 position. */ - -#define AC_WINTLVL_gm 0x03 /* Window Interrupt Level group mask. */ -#define AC_WINTLVL_gp 0 /* Window Interrupt Level group position. */ -#define AC_WINTLVL0_bm (1<<0) /* Window Interrupt Level bit 0 mask. */ -#define AC_WINTLVL0_bp 0 /* Window Interrupt Level bit 0 position. */ -#define AC_WINTLVL1_bm (1<<1) /* Window Interrupt Level bit 1 mask. */ -#define AC_WINTLVL1_bp 1 /* Window Interrupt Level bit 1 position. */ - -/* AC.STATUS bit masks and bit positions */ -#define AC_WSTATE_gm 0xC0 /* Window Mode State group mask. */ -#define AC_WSTATE_gp 6 /* Window Mode State group position. */ -#define AC_WSTATE0_bm (1<<6) /* Window Mode State bit 0 mask. */ -#define AC_WSTATE0_bp 6 /* Window Mode State bit 0 position. */ -#define AC_WSTATE1_bm (1<<7) /* Window Mode State bit 1 mask. */ -#define AC_WSTATE1_bp 7 /* Window Mode State bit 1 position. */ - -#define AC_AC1STATE_bm 0x20 /* Analog Comparator 1 State bit mask. */ -#define AC_AC1STATE_bp 5 /* Analog Comparator 1 State bit position. */ - -#define AC_AC0STATE_bm 0x10 /* Analog Comparator 0 State bit mask. */ -#define AC_AC0STATE_bp 4 /* Analog Comparator 0 State bit position. */ - -#define AC_WIF_bm 0x04 /* Window Mode Interrupt Flag bit mask. */ -#define AC_WIF_bp 2 /* Window Mode Interrupt Flag bit position. */ - -#define AC_AC1IF_bm 0x02 /* Analog Comparator 1 Interrupt Flag bit mask. */ -#define AC_AC1IF_bp 1 /* Analog Comparator 1 Interrupt Flag bit position. */ - -#define AC_AC0IF_bm 0x01 /* Analog Comparator 0 Interrupt Flag bit mask. */ -#define AC_AC0IF_bp 0 /* Analog Comparator 0 Interrupt Flag bit position. */ - -/* RTC - Real-Time Counter */ -/* RTC.CTRL bit masks and bit positions */ -#define RTC_PRESCALER_gm 0x07 /* Prescaling Factor group mask. */ -#define RTC_PRESCALER_gp 0 /* Prescaling Factor group position. */ -#define RTC_PRESCALER0_bm (1<<0) /* Prescaling Factor bit 0 mask. */ -#define RTC_PRESCALER0_bp 0 /* Prescaling Factor bit 0 position. */ -#define RTC_PRESCALER1_bm (1<<1) /* Prescaling Factor bit 1 mask. */ -#define RTC_PRESCALER1_bp 1 /* Prescaling Factor bit 1 position. */ -#define RTC_PRESCALER2_bm (1<<2) /* Prescaling Factor bit 2 mask. */ -#define RTC_PRESCALER2_bp 2 /* Prescaling Factor bit 2 position. */ - -/* RTC.STATUS bit masks and bit positions */ -#define RTC_SYNCBUSY_bm 0x01 /* Synchronization Busy Flag bit mask. */ -#define RTC_SYNCBUSY_bp 0 /* Synchronization Busy Flag bit position. */ - -/* RTC.INTCTRL bit masks and bit positions */ -#define RTC_COMPINTLVL_gm 0x0C /* Compare Match Interrupt Level group mask. */ -#define RTC_COMPINTLVL_gp 2 /* Compare Match Interrupt Level group position. */ -#define RTC_COMPINTLVL0_bm (1<<2) /* Compare Match Interrupt Level bit 0 mask. */ -#define RTC_COMPINTLVL0_bp 2 /* Compare Match Interrupt Level bit 0 position. */ -#define RTC_COMPINTLVL1_bm (1<<3) /* Compare Match Interrupt Level bit 1 mask. */ -#define RTC_COMPINTLVL1_bp 3 /* Compare Match Interrupt Level bit 1 position. */ - -#define RTC_OVFINTLVL_gm 0x03 /* Overflow Interrupt Level group mask. */ -#define RTC_OVFINTLVL_gp 0 /* Overflow Interrupt Level group position. */ -#define RTC_OVFINTLVL0_bm (1<<0) /* Overflow Interrupt Level bit 0 mask. */ -#define RTC_OVFINTLVL0_bp 0 /* Overflow Interrupt Level bit 0 position. */ -#define RTC_OVFINTLVL1_bm (1<<1) /* Overflow Interrupt Level bit 1 mask. */ -#define RTC_OVFINTLVL1_bp 1 /* Overflow Interrupt Level bit 1 position. */ - -/* RTC.INTFLAGS bit masks and bit positions */ -#define RTC_COMPIF_bm 0x02 /* Compare Match Interrupt Flag bit mask. */ -#define RTC_COMPIF_bp 1 /* Compare Match Interrupt Flag bit position. */ - -#define RTC_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ -#define RTC_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ - -/* TWI - Two-Wire Interface */ -/* TWI_MASTER.CTRLA bit masks and bit positions */ -#define TWI_MASTER_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ -#define TWI_MASTER_INTLVL_gp 6 /* Interrupt Level group position. */ -#define TWI_MASTER_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ -#define TWI_MASTER_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ -#define TWI_MASTER_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ -#define TWI_MASTER_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ - -#define TWI_MASTER_RIEN_bm 0x20 /* Read Interrupt Enable bit mask. */ -#define TWI_MASTER_RIEN_bp 5 /* Read Interrupt Enable bit position. */ - -#define TWI_MASTER_WIEN_bm 0x10 /* Write Interrupt Enable bit mask. */ -#define TWI_MASTER_WIEN_bp 4 /* Write Interrupt Enable bit position. */ - -#define TWI_MASTER_ENABLE_bm 0x08 /* Enable TWI Master bit mask. */ -#define TWI_MASTER_ENABLE_bp 3 /* Enable TWI Master bit position. */ - -/* TWI_MASTER.CTRLB bit masks and bit positions */ -#define TWI_MASTER_TIMEOUT_gm 0x0C /* Inactive Bus Timeout group mask. */ -#define TWI_MASTER_TIMEOUT_gp 2 /* Inactive Bus Timeout group position. */ -#define TWI_MASTER_TIMEOUT0_bm (1<<2) /* Inactive Bus Timeout bit 0 mask. */ -#define TWI_MASTER_TIMEOUT0_bp 2 /* Inactive Bus Timeout bit 0 position. */ -#define TWI_MASTER_TIMEOUT1_bm (1<<3) /* Inactive Bus Timeout bit 1 mask. */ -#define TWI_MASTER_TIMEOUT1_bp 3 /* Inactive Bus Timeout bit 1 position. */ - -#define TWI_MASTER_QCEN_bm 0x02 /* Quick Command Enable bit mask. */ -#define TWI_MASTER_QCEN_bp 1 /* Quick Command Enable bit position. */ - -#define TWI_MASTER_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ -#define TWI_MASTER_SMEN_bp 0 /* Smart Mode Enable bit position. */ - -/* TWI_MASTER.CTRLC bit masks and bit positions */ -#define TWI_MASTER_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ -#define TWI_MASTER_ACKACT_bp 2 /* Acknowledge Action bit position. */ - -#define TWI_MASTER_CMD_gm 0x03 /* Command group mask. */ -#define TWI_MASTER_CMD_gp 0 /* Command group position. */ -#define TWI_MASTER_CMD0_bm (1<<0) /* Command bit 0 mask. */ -#define TWI_MASTER_CMD0_bp 0 /* Command bit 0 position. */ -#define TWI_MASTER_CMD1_bm (1<<1) /* Command bit 1 mask. */ -#define TWI_MASTER_CMD1_bp 1 /* Command bit 1 position. */ - -/* TWI_MASTER.STATUS bit masks and bit positions */ -#define TWI_MASTER_RIF_bm 0x80 /* Read Interrupt Flag bit mask. */ -#define TWI_MASTER_RIF_bp 7 /* Read Interrupt Flag bit position. */ - -#define TWI_MASTER_WIF_bm 0x40 /* Write Interrupt Flag bit mask. */ -#define TWI_MASTER_WIF_bp 6 /* Write Interrupt Flag bit position. */ - -#define TWI_MASTER_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ -#define TWI_MASTER_CLKHOLD_bp 5 /* Clock Hold bit position. */ - -#define TWI_MASTER_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ -#define TWI_MASTER_RXACK_bp 4 /* Received Acknowledge bit position. */ - -#define TWI_MASTER_ARBLOST_bm 0x08 /* Arbitration Lost bit mask. */ -#define TWI_MASTER_ARBLOST_bp 3 /* Arbitration Lost bit position. */ - -#define TWI_MASTER_BUSERR_bm 0x04 /* Bus Error bit mask. */ -#define TWI_MASTER_BUSERR_bp 2 /* Bus Error bit position. */ - -#define TWI_MASTER_BUSSTATE_gm 0x03 /* Bus State group mask. */ -#define TWI_MASTER_BUSSTATE_gp 0 /* Bus State group position. */ -#define TWI_MASTER_BUSSTATE0_bm (1<<0) /* Bus State bit 0 mask. */ -#define TWI_MASTER_BUSSTATE0_bp 0 /* Bus State bit 0 position. */ -#define TWI_MASTER_BUSSTATE1_bm (1<<1) /* Bus State bit 1 mask. */ -#define TWI_MASTER_BUSSTATE1_bp 1 /* Bus State bit 1 position. */ - -/* TWI_SLAVE.CTRLA bit masks and bit positions */ -#define TWI_SLAVE_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ -#define TWI_SLAVE_INTLVL_gp 6 /* Interrupt Level group position. */ -#define TWI_SLAVE_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ -#define TWI_SLAVE_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ -#define TWI_SLAVE_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ -#define TWI_SLAVE_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ - -#define TWI_SLAVE_DIEN_bm 0x20 /* Data Interrupt Enable bit mask. */ -#define TWI_SLAVE_DIEN_bp 5 /* Data Interrupt Enable bit position. */ - -#define TWI_SLAVE_APIEN_bm 0x10 /* Address/Stop Interrupt Enable bit mask. */ -#define TWI_SLAVE_APIEN_bp 4 /* Address/Stop Interrupt Enable bit position. */ - -#define TWI_SLAVE_ENABLE_bm 0x08 /* Enable TWI Slave bit mask. */ -#define TWI_SLAVE_ENABLE_bp 3 /* Enable TWI Slave bit position. */ - -#define TWI_SLAVE_PIEN_bm 0x04 /* Stop Interrupt Enable bit mask. */ -#define TWI_SLAVE_PIEN_bp 2 /* Stop Interrupt Enable bit position. */ - -#define TWI_SLAVE_PMEN_bm 0x02 /* Promiscuous Mode Enable bit mask. */ -#define TWI_SLAVE_PMEN_bp 1 /* Promiscuous Mode Enable bit position. */ - -#define TWI_SLAVE_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ -#define TWI_SLAVE_SMEN_bp 0 /* Smart Mode Enable bit position. */ - -/* TWI_SLAVE.CTRLB bit masks and bit positions */ -#define TWI_SLAVE_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ -#define TWI_SLAVE_ACKACT_bp 2 /* Acknowledge Action bit position. */ - -#define TWI_SLAVE_CMD_gm 0x03 /* Command group mask. */ -#define TWI_SLAVE_CMD_gp 0 /* Command group position. */ -#define TWI_SLAVE_CMD0_bm (1<<0) /* Command bit 0 mask. */ -#define TWI_SLAVE_CMD0_bp 0 /* Command bit 0 position. */ -#define TWI_SLAVE_CMD1_bm (1<<1) /* Command bit 1 mask. */ -#define TWI_SLAVE_CMD1_bp 1 /* Command bit 1 position. */ - -/* TWI_SLAVE.STATUS bit masks and bit positions */ -#define TWI_SLAVE_DIF_bm 0x80 /* Data Interrupt Flag bit mask. */ -#define TWI_SLAVE_DIF_bp 7 /* Data Interrupt Flag bit position. */ - -#define TWI_SLAVE_APIF_bm 0x40 /* Address/Stop Interrupt Flag bit mask. */ -#define TWI_SLAVE_APIF_bp 6 /* Address/Stop Interrupt Flag bit position. */ - -#define TWI_SLAVE_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ -#define TWI_SLAVE_CLKHOLD_bp 5 /* Clock Hold bit position. */ - -#define TWI_SLAVE_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ -#define TWI_SLAVE_RXACK_bp 4 /* Received Acknowledge bit position. */ - -#define TWI_SLAVE_COLL_bm 0x08 /* Collision bit mask. */ -#define TWI_SLAVE_COLL_bp 3 /* Collision bit position. */ - -#define TWI_SLAVE_BUSERR_bm 0x04 /* Bus Error bit mask. */ -#define TWI_SLAVE_BUSERR_bp 2 /* Bus Error bit position. */ - -#define TWI_SLAVE_DIR_bm 0x02 /* Read/Write Direction bit mask. */ -#define TWI_SLAVE_DIR_bp 1 /* Read/Write Direction bit position. */ - -#define TWI_SLAVE_AP_bm 0x01 /* Slave Address or Stop bit mask. */ -#define TWI_SLAVE_AP_bp 0 /* Slave Address or Stop bit position. */ - -/* TWI_SLAVE.ADDRMASK bit masks and bit positions */ -#define TWI_SLAVE_ADDRMASK_gm 0xFE /* Address Mask group mask. */ -#define TWI_SLAVE_ADDRMASK_gp 1 /* Address Mask group position. */ -#define TWI_SLAVE_ADDRMASK0_bm (1<<1) /* Address Mask bit 0 mask. */ -#define TWI_SLAVE_ADDRMASK0_bp 1 /* Address Mask bit 0 position. */ -#define TWI_SLAVE_ADDRMASK1_bm (1<<2) /* Address Mask bit 1 mask. */ -#define TWI_SLAVE_ADDRMASK1_bp 2 /* Address Mask bit 1 position. */ -#define TWI_SLAVE_ADDRMASK2_bm (1<<3) /* Address Mask bit 2 mask. */ -#define TWI_SLAVE_ADDRMASK2_bp 3 /* Address Mask bit 2 position. */ -#define TWI_SLAVE_ADDRMASK3_bm (1<<4) /* Address Mask bit 3 mask. */ -#define TWI_SLAVE_ADDRMASK3_bp 4 /* Address Mask bit 3 position. */ -#define TWI_SLAVE_ADDRMASK4_bm (1<<5) /* Address Mask bit 4 mask. */ -#define TWI_SLAVE_ADDRMASK4_bp 5 /* Address Mask bit 4 position. */ -#define TWI_SLAVE_ADDRMASK5_bm (1<<6) /* Address Mask bit 5 mask. */ -#define TWI_SLAVE_ADDRMASK5_bp 6 /* Address Mask bit 5 position. */ -#define TWI_SLAVE_ADDRMASK6_bm (1<<7) /* Address Mask bit 6 mask. */ -#define TWI_SLAVE_ADDRMASK6_bp 7 /* Address Mask bit 6 position. */ - -#define TWI_SLAVE_ADDREN_bm 0x01 /* Address Enable bit mask. */ -#define TWI_SLAVE_ADDREN_bp 0 /* Address Enable bit position. */ - -/* TWI.CTRL bit masks and bit positions */ -#define TWI_SDAHOLD_gm 0x06 /* SDA Hold Time Enable group mask. */ -#define TWI_SDAHOLD_gp 1 /* SDA Hold Time Enable group position. */ -#define TWI_SDAHOLD0_bm (1<<1) /* SDA Hold Time Enable bit 0 mask. */ -#define TWI_SDAHOLD0_bp 1 /* SDA Hold Time Enable bit 0 position. */ -#define TWI_SDAHOLD1_bm (1<<2) /* SDA Hold Time Enable bit 1 mask. */ -#define TWI_SDAHOLD1_bp 2 /* SDA Hold Time Enable bit 1 position. */ - -#define TWI_EDIEN_bm 0x01 /* External Driver Interface Enable bit mask. */ -#define TWI_EDIEN_bp 0 /* External Driver Interface Enable bit position. */ - -/* USB - USB */ -/* USB_EP.STATUS bit masks and bit positions */ -#define USB_EP_STALLF_bm 0x80 /* Endpoint Stall Flag bit mask. */ -#define USB_EP_STALLF_bp 7 /* Endpoint Stall Flag bit position. */ - -#define USB_EP_CRC_bm 0x80 /* CRC Error Flag bit mask. */ -#define USB_EP_CRC_bp 7 /* CRC Error Flag bit position. */ - -#define USB_EP_UNF_bm 0x40 /* Underflow Enpoint FLag bit mask. */ -#define USB_EP_UNF_bp 6 /* Underflow Enpoint FLag bit position. */ - -#define USB_EP_OVF_bm 0x40 /* Overflow Enpoint Flag for Output Endpoints bit mask. */ -#define USB_EP_OVF_bp 6 /* Overflow Enpoint Flag for Output Endpoints bit position. */ - -#define USB_EP_TRNCOMPL0_bm 0x20 /* Transaction Complete 0 Flag bit mask. */ -#define USB_EP_TRNCOMPL0_bp 5 /* Transaction Complete 0 Flag bit position. */ - -#define USB_EP_TRNCOMPL1_bm 0x10 /* Transaction Complete 1 Flag bit mask. */ -#define USB_EP_TRNCOMPL1_bp 4 /* Transaction Complete 1 Flag bit position. */ - -#define USB_EP_SETUP_bm 0x10 /* SETUP Transaction Complete Flag bit mask. */ -#define USB_EP_SETUP_bp 4 /* SETUP Transaction Complete Flag bit position. */ - -#define USB_EP_BANK_bm 0x08 /* Bank Select bit mask. */ -#define USB_EP_BANK_bp 3 /* Bank Select bit position. */ - -#define USB_EP_BUSNACK1_bm 0x04 /* Data Buffer 1 Not Acknowledge bit mask. */ -#define USB_EP_BUSNACK1_bp 2 /* Data Buffer 1 Not Acknowledge bit position. */ - -#define USB_EP_BUSNACK0_bm 0x02 /* Data Buffer 0 Not Acknowledge bit mask. */ -#define USB_EP_BUSNACK0_bp 1 /* Data Buffer 0 Not Acknowledge bit position. */ - -#define USB_EP_TOGGLE_bm 0x01 /* Data Toggle bit mask. */ -#define USB_EP_TOGGLE_bp 0 /* Data Toggle bit position. */ - -/* USB_EP.CTRL bit masks and bit positions */ -#define USB_EP_TYPE_gm 0xC0 /* Endpoint Type group mask. */ -#define USB_EP_TYPE_gp 6 /* Endpoint Type group position. */ -#define USB_EP_TYPE0_bm (1<<6) /* Endpoint Type bit 0 mask. */ -#define USB_EP_TYPE0_bp 6 /* Endpoint Type bit 0 position. */ -#define USB_EP_TYPE1_bm (1<<7) /* Endpoint Type bit 1 mask. */ -#define USB_EP_TYPE1_bp 7 /* Endpoint Type bit 1 position. */ - -#define USB_EP_MULTIPKT_bm 0x20 /* Multi Packet Transfer Enable bit mask. */ -#define USB_EP_MULTIPKT_bp 5 /* Multi Packet Transfer Enable bit position. */ - -#define USB_EP_PINGPONG_bm 0x10 /* Ping-Pong Enable bit mask. */ -#define USB_EP_PINGPONG_bp 4 /* Ping-Pong Enable bit position. */ - -#define USB_EP_INTDSBL_bm 0x08 /* Interrupt Disable bit mask. */ -#define USB_EP_INTDSBL_bp 3 /* Interrupt Disable bit position. */ - -#define USB_EP_STALL_bm 0x04 /* Data Stall bit mask. */ -#define USB_EP_STALL_bp 2 /* Data Stall bit position. */ - -#define USB_EP_BUFSIZE_gm 0x07 /* Data Buffer Size group mask. */ -#define USB_EP_BUFSIZE_gp 0 /* Data Buffer Size group position. */ -#define USB_EP_BUFSIZE0_bm (1<<0) /* Data Buffer Size bit 0 mask. */ -#define USB_EP_BUFSIZE0_bp 0 /* Data Buffer Size bit 0 position. */ -#define USB_EP_BUFSIZE1_bm (1<<1) /* Data Buffer Size bit 1 mask. */ -#define USB_EP_BUFSIZE1_bp 1 /* Data Buffer Size bit 1 position. */ -#define USB_EP_BUFSIZE2_bm (1<<2) /* Data Buffer Size bit 2 mask. */ -#define USB_EP_BUFSIZE2_bp 2 /* Data Buffer Size bit 2 position. */ - -/* USB_EP.CNT bit masks and bit positions */ -#define USB_EP_ZLP_bm 0x8000 /* Zero Length Packet bit mask. */ -#define USB_EP_ZLP_bp 15 /* Zero Length Packet bit position. */ - -/* USB.CTRLA bit masks and bit positions */ -#define USB_ENABLE_bm 0x80 /* USB Enable bit mask. */ -#define USB_ENABLE_bp 7 /* USB Enable bit position. */ - -#define USB_SPEED_bm 0x40 /* Speed Select bit mask. */ -#define USB_SPEED_bp 6 /* Speed Select bit position. */ - -#define USB_FIFOEN_bm 0x20 /* USB FIFO Enable bit mask. */ -#define USB_FIFOEN_bp 5 /* USB FIFO Enable bit position. */ - -#define USB_STFRNUM_bm 0x10 /* Store Frame Number Enable bit mask. */ -#define USB_STFRNUM_bp 4 /* Store Frame Number Enable bit position. */ - -#define USB_MAXEP_gm 0x0F /* Maximum Endpoint Addresses group mask. */ -#define USB_MAXEP_gp 0 /* Maximum Endpoint Addresses group position. */ -#define USB_MAXEP0_bm (1<<0) /* Maximum Endpoint Addresses bit 0 mask. */ -#define USB_MAXEP0_bp 0 /* Maximum Endpoint Addresses bit 0 position. */ -#define USB_MAXEP1_bm (1<<1) /* Maximum Endpoint Addresses bit 1 mask. */ -#define USB_MAXEP1_bp 1 /* Maximum Endpoint Addresses bit 1 position. */ -#define USB_MAXEP2_bm (1<<2) /* Maximum Endpoint Addresses bit 2 mask. */ -#define USB_MAXEP2_bp 2 /* Maximum Endpoint Addresses bit 2 position. */ -#define USB_MAXEP3_bm (1<<3) /* Maximum Endpoint Addresses bit 3 mask. */ -#define USB_MAXEP3_bp 3 /* Maximum Endpoint Addresses bit 3 position. */ - -/* USB.CTRLB bit masks and bit positions */ -#define USB_PULLRST_bm 0x10 /* Pull during Reset bit mask. */ -#define USB_PULLRST_bp 4 /* Pull during Reset bit position. */ - -#define USB_RWAKEUP_bm 0x04 /* Remote Wake-up bit mask. */ -#define USB_RWAKEUP_bp 2 /* Remote Wake-up bit position. */ - -#define USB_GNACK_bm 0x02 /* Global NACK bit mask. */ -#define USB_GNACK_bp 1 /* Global NACK bit position. */ - -#define USB_ATTACH_bm 0x01 /* Attach bit mask. */ -#define USB_ATTACH_bp 0 /* Attach bit position. */ - -/* USB.STATUS bit masks and bit positions */ -#define USB_URESUME_bm 0x08 /* Upstream Resume bit mask. */ -#define USB_URESUME_bp 3 /* Upstream Resume bit position. */ - -#define USB_RESUME_bm 0x04 /* Resume bit mask. */ -#define USB_RESUME_bp 2 /* Resume bit position. */ - -#define USB_SUSPEND_bm 0x02 /* Bus Suspended bit mask. */ -#define USB_SUSPEND_bp 1 /* Bus Suspended bit position. */ - -#define USB_BUSRST_bm 0x01 /* Bus Reset bit mask. */ -#define USB_BUSRST_bp 0 /* Bus Reset bit position. */ - -/* USB.ADDR bit masks and bit positions */ -#define USB_ADDR_gm 0x7F /* Device Address group mask. */ -#define USB_ADDR_gp 0 /* Device Address group position. */ -#define USB_ADDR0_bm (1<<0) /* Device Address bit 0 mask. */ -#define USB_ADDR0_bp 0 /* Device Address bit 0 position. */ -#define USB_ADDR1_bm (1<<1) /* Device Address bit 1 mask. */ -#define USB_ADDR1_bp 1 /* Device Address bit 1 position. */ -#define USB_ADDR2_bm (1<<2) /* Device Address bit 2 mask. */ -#define USB_ADDR2_bp 2 /* Device Address bit 2 position. */ -#define USB_ADDR3_bm (1<<3) /* Device Address bit 3 mask. */ -#define USB_ADDR3_bp 3 /* Device Address bit 3 position. */ -#define USB_ADDR4_bm (1<<4) /* Device Address bit 4 mask. */ -#define USB_ADDR4_bp 4 /* Device Address bit 4 position. */ -#define USB_ADDR5_bm (1<<5) /* Device Address bit 5 mask. */ -#define USB_ADDR5_bp 5 /* Device Address bit 5 position. */ -#define USB_ADDR6_bm (1<<6) /* Device Address bit 6 mask. */ -#define USB_ADDR6_bp 6 /* Device Address bit 6 position. */ - -/* USB.FIFOWP bit masks and bit positions */ -#define USB_FIFOWP_gm 0x1F /* FIFO Write Pointer group mask. */ -#define USB_FIFOWP_gp 0 /* FIFO Write Pointer group position. */ -#define USB_FIFOWP0_bm (1<<0) /* FIFO Write Pointer bit 0 mask. */ -#define USB_FIFOWP0_bp 0 /* FIFO Write Pointer bit 0 position. */ -#define USB_FIFOWP1_bm (1<<1) /* FIFO Write Pointer bit 1 mask. */ -#define USB_FIFOWP1_bp 1 /* FIFO Write Pointer bit 1 position. */ -#define USB_FIFOWP2_bm (1<<2) /* FIFO Write Pointer bit 2 mask. */ -#define USB_FIFOWP2_bp 2 /* FIFO Write Pointer bit 2 position. */ -#define USB_FIFOWP3_bm (1<<3) /* FIFO Write Pointer bit 3 mask. */ -#define USB_FIFOWP3_bp 3 /* FIFO Write Pointer bit 3 position. */ -#define USB_FIFOWP4_bm (1<<4) /* FIFO Write Pointer bit 4 mask. */ -#define USB_FIFOWP4_bp 4 /* FIFO Write Pointer bit 4 position. */ - -/* USB.FIFORP bit masks and bit positions */ -#define USB_FIFORP_gm 0x1F /* FIFO Read Pointer group mask. */ -#define USB_FIFORP_gp 0 /* FIFO Read Pointer group position. */ -#define USB_FIFORP0_bm (1<<0) /* FIFO Read Pointer bit 0 mask. */ -#define USB_FIFORP0_bp 0 /* FIFO Read Pointer bit 0 position. */ -#define USB_FIFORP1_bm (1<<1) /* FIFO Read Pointer bit 1 mask. */ -#define USB_FIFORP1_bp 1 /* FIFO Read Pointer bit 1 position. */ -#define USB_FIFORP2_bm (1<<2) /* FIFO Read Pointer bit 2 mask. */ -#define USB_FIFORP2_bp 2 /* FIFO Read Pointer bit 2 position. */ -#define USB_FIFORP3_bm (1<<3) /* FIFO Read Pointer bit 3 mask. */ -#define USB_FIFORP3_bp 3 /* FIFO Read Pointer bit 3 position. */ -#define USB_FIFORP4_bm (1<<4) /* FIFO Read Pointer bit 4 mask. */ -#define USB_FIFORP4_bp 4 /* FIFO Read Pointer bit 4 position. */ - -/* USB.INTCTRLA bit masks and bit positions */ -#define USB_SOFIE_bm 0x80 /* Start Of Frame Interrupt Enable bit mask. */ -#define USB_SOFIE_bp 7 /* Start Of Frame Interrupt Enable bit position. */ - -#define USB_BUSEVIE_bm 0x40 /* Bus Event Interrupt Enable bit mask. */ -#define USB_BUSEVIE_bp 6 /* Bus Event Interrupt Enable bit position. */ - -#define USB_BUSERRIE_bm 0x20 /* Bus Error Interrupt Enable bit mask. */ -#define USB_BUSERRIE_bp 5 /* Bus Error Interrupt Enable bit position. */ - -#define USB_STALLIE_bm 0x10 /* STALL Interrupt Enable bit mask. */ -#define USB_STALLIE_bp 4 /* STALL Interrupt Enable bit position. */ - -#define USB_INTLVL_gm 0x03 /* Interrupt Level group mask. */ -#define USB_INTLVL_gp 0 /* Interrupt Level group position. */ -#define USB_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */ -#define USB_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */ -#define USB_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ -#define USB_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */ - -/* USB.INTCTRLB bit masks and bit positions */ -#define USB_TRNIE_bm 0x02 /* Transaction Complete Interrupt Enable bit mask. */ -#define USB_TRNIE_bp 1 /* Transaction Complete Interrupt Enable bit position. */ - -#define USB_SETUPIE_bm 0x01 /* SETUP Transaction Complete Interrupt Enable bit mask. */ -#define USB_SETUPIE_bp 0 /* SETUP Transaction Complete Interrupt Enable bit position. */ - -/* USB.INTFLAGSACLR bit masks and bit positions */ -#define USB_SOFIF_bm 0x80 /* Start Of Frame Interrupt Flag bit mask. */ -#define USB_SOFIF_bp 7 /* Start Of Frame Interrupt Flag bit position. */ - -#define USB_SUSPENDIF_bm 0x40 /* Suspend Interrupt Flag bit mask. */ -#define USB_SUSPENDIF_bp 6 /* Suspend Interrupt Flag bit position. */ - -#define USB_RESUMEIF_bm 0x20 /* Resume Interrupt Flag bit mask. */ -#define USB_RESUMEIF_bp 5 /* Resume Interrupt Flag bit position. */ - -#define USB_RSTIF_bm 0x10 /* Reset Interrupt Flag bit mask. */ -#define USB_RSTIF_bp 4 /* Reset Interrupt Flag bit position. */ - -#define USB_CRCIF_bm 0x08 /* Isochronous CRC Error Interrupt Flag bit mask. */ -#define USB_CRCIF_bp 3 /* Isochronous CRC Error Interrupt Flag bit position. */ - -#define USB_UNFIF_bm 0x04 /* Underflow Interrupt Flag bit mask. */ -#define USB_UNFIF_bp 2 /* Underflow Interrupt Flag bit position. */ - -#define USB_OVFIF_bm 0x02 /* Overflow Interrupt Flag bit mask. */ -#define USB_OVFIF_bp 1 /* Overflow Interrupt Flag bit position. */ - -#define USB_STALLIF_bm 0x01 /* STALL Interrupt Flag bit mask. */ -#define USB_STALLIF_bp 0 /* STALL Interrupt Flag bit position. */ - -/* USB.INTFLAGSASET bit masks and bit positions */ -/* USB_SOFIF Predefined. */ -/* USB_SOFIF Predefined. */ - -/* USB_SUSPENDIF Predefined. */ -/* USB_SUSPENDIF Predefined. */ - -/* USB_RESUMEIF Predefined. */ -/* USB_RESUMEIF Predefined. */ - -/* USB_RSTIF Predefined. */ -/* USB_RSTIF Predefined. */ - -/* USB_CRCIF Predefined. */ -/* USB_CRCIF Predefined. */ - -/* USB_UNFIF Predefined. */ -/* USB_UNFIF Predefined. */ - -/* USB_OVFIF Predefined. */ -/* USB_OVFIF Predefined. */ - -/* USB_STALLIF Predefined. */ -/* USB_STALLIF Predefined. */ - -/* USB.INTFLAGSBCLR bit masks and bit positions */ -#define USB_TRNIF_bm 0x02 /* Transaction Complete Interrupt Flag bit mask. */ -#define USB_TRNIF_bp 1 /* Transaction Complete Interrupt Flag bit position. */ - -#define USB_SETUPIF_bm 0x01 /* SETUP Transaction Complete Interrupt Flag bit mask. */ -#define USB_SETUPIF_bp 0 /* SETUP Transaction Complete Interrupt Flag bit position. */ - -/* USB.INTFLAGSBSET bit masks and bit positions */ -/* USB_TRNIF Predefined. */ -/* USB_TRNIF Predefined. */ - -/* USB_SETUPIF Predefined. */ -/* USB_SETUPIF Predefined. */ - -/* PORT - I/O Port Configuration */ -/* PORT.INTCTRL bit masks and bit positions */ -#define PORT_INT1LVL_gm 0x0C /* Port Interrupt 1 Level group mask. */ -#define PORT_INT1LVL_gp 2 /* Port Interrupt 1 Level group position. */ -#define PORT_INT1LVL0_bm (1<<2) /* Port Interrupt 1 Level bit 0 mask. */ -#define PORT_INT1LVL0_bp 2 /* Port Interrupt 1 Level bit 0 position. */ -#define PORT_INT1LVL1_bm (1<<3) /* Port Interrupt 1 Level bit 1 mask. */ -#define PORT_INT1LVL1_bp 3 /* Port Interrupt 1 Level bit 1 position. */ - -#define PORT_INT0LVL_gm 0x03 /* Port Interrupt 0 Level group mask. */ -#define PORT_INT0LVL_gp 0 /* Port Interrupt 0 Level group position. */ -#define PORT_INT0LVL0_bm (1<<0) /* Port Interrupt 0 Level bit 0 mask. */ -#define PORT_INT0LVL0_bp 0 /* Port Interrupt 0 Level bit 0 position. */ -#define PORT_INT0LVL1_bm (1<<1) /* Port Interrupt 0 Level bit 1 mask. */ -#define PORT_INT0LVL1_bp 1 /* Port Interrupt 0 Level bit 1 position. */ - -/* PORT.INTFLAGS bit masks and bit positions */ -#define PORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ -#define PORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ - -#define PORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ -#define PORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ - -/* PORT.REMAP bit masks and bit positions */ -#define PORT_SPI_bm 0x20 /* SPI bit mask. */ -#define PORT_SPI_bp 5 /* SPI bit position. */ - -#define PORT_USART0_bm 0x10 /* USART0 bit mask. */ -#define PORT_USART0_bp 4 /* USART0 bit position. */ - -#define PORT_TC0D_bm 0x08 /* Timer/Counter 0 Output Compare D bit mask. */ -#define PORT_TC0D_bp 3 /* Timer/Counter 0 Output Compare D bit position. */ - -#define PORT_TC0C_bm 0x04 /* Timer/Counter 0 Output Compare C bit mask. */ -#define PORT_TC0C_bp 2 /* Timer/Counter 0 Output Compare C bit position. */ - -#define PORT_TC0B_bm 0x02 /* Timer/Counter 0 Output Compare B bit mask. */ -#define PORT_TC0B_bp 1 /* Timer/Counter 0 Output Compare B bit position. */ - -#define PORT_TC0A_bm 0x01 /* Timer/Counter 0 Output Compare A bit mask. */ -#define PORT_TC0A_bp 0 /* Timer/Counter 0 Output Compare A bit position. */ - -/* PORT.PIN0CTRL bit masks and bit positions */ -#define PORT_SRLEN_bm 0x80 /* Slew Rate Enable bit mask. */ -#define PORT_SRLEN_bp 7 /* Slew Rate Enable bit position. */ - -#define PORT_INVEN_bm 0x40 /* Inverted I/O Enable bit mask. */ -#define PORT_INVEN_bp 6 /* Inverted I/O Enable bit position. */ - -#define PORT_OPC_gm 0x38 /* Output/Pull Configuration group mask. */ -#define PORT_OPC_gp 3 /* Output/Pull Configuration group position. */ -#define PORT_OPC0_bm (1<<3) /* Output/Pull Configuration bit 0 mask. */ -#define PORT_OPC0_bp 3 /* Output/Pull Configuration bit 0 position. */ -#define PORT_OPC1_bm (1<<4) /* Output/Pull Configuration bit 1 mask. */ -#define PORT_OPC1_bp 4 /* Output/Pull Configuration bit 1 position. */ -#define PORT_OPC2_bm (1<<5) /* Output/Pull Configuration bit 2 mask. */ -#define PORT_OPC2_bp 5 /* Output/Pull Configuration bit 2 position. */ - -#define PORT_ISC_gm 0x07 /* Input/Sense Configuration group mask. */ -#define PORT_ISC_gp 0 /* Input/Sense Configuration group position. */ -#define PORT_ISC0_bm (1<<0) /* Input/Sense Configuration bit 0 mask. */ -#define PORT_ISC0_bp 0 /* Input/Sense Configuration bit 0 position. */ -#define PORT_ISC1_bm (1<<1) /* Input/Sense Configuration bit 1 mask. */ -#define PORT_ISC1_bp 1 /* Input/Sense Configuration bit 1 position. */ -#define PORT_ISC2_bm (1<<2) /* Input/Sense Configuration bit 2 mask. */ -#define PORT_ISC2_bp 2 /* Input/Sense Configuration bit 2 position. */ - -/* PORT.PIN1CTRL bit masks and bit positions */ -/* PORT_SRLEN Predefined. */ -/* PORT_SRLEN Predefined. */ - -/* PORT_INVEN Predefined. */ -/* PORT_INVEN Predefined. */ - -/* PORT_OPC Predefined. */ -/* PORT_OPC Predefined. */ - -/* PORT_ISC Predefined. */ -/* PORT_ISC Predefined. */ - -/* PORT.PIN2CTRL bit masks and bit positions */ -/* PORT_SRLEN Predefined. */ -/* PORT_SRLEN Predefined. */ - -/* PORT_INVEN Predefined. */ -/* PORT_INVEN Predefined. */ - -/* PORT_OPC Predefined. */ -/* PORT_OPC Predefined. */ - -/* PORT_ISC Predefined. */ -/* PORT_ISC Predefined. */ - -/* PORT.PIN3CTRL bit masks and bit positions */ -/* PORT_SRLEN Predefined. */ -/* PORT_SRLEN Predefined. */ - -/* PORT_INVEN Predefined. */ -/* PORT_INVEN Predefined. */ - -/* PORT_OPC Predefined. */ -/* PORT_OPC Predefined. */ - -/* PORT_ISC Predefined. */ -/* PORT_ISC Predefined. */ - -/* PORT.PIN4CTRL bit masks and bit positions */ -/* PORT_SRLEN Predefined. */ -/* PORT_SRLEN Predefined. */ - -/* PORT_INVEN Predefined. */ -/* PORT_INVEN Predefined. */ - -/* PORT_OPC Predefined. */ -/* PORT_OPC Predefined. */ - -/* PORT_ISC Predefined. */ -/* PORT_ISC Predefined. */ - -/* PORT.PIN5CTRL bit masks and bit positions */ -/* PORT_SRLEN Predefined. */ -/* PORT_SRLEN Predefined. */ - -/* PORT_INVEN Predefined. */ -/* PORT_INVEN Predefined. */ - -/* PORT_OPC Predefined. */ -/* PORT_OPC Predefined. */ - -/* PORT_ISC Predefined. */ -/* PORT_ISC Predefined. */ - -/* PORT.PIN6CTRL bit masks and bit positions */ -/* PORT_SRLEN Predefined. */ -/* PORT_SRLEN Predefined. */ - -/* PORT_INVEN Predefined. */ -/* PORT_INVEN Predefined. */ - -/* PORT_OPC Predefined. */ -/* PORT_OPC Predefined. */ - -/* PORT_ISC Predefined. */ -/* PORT_ISC Predefined. */ - -/* PORT.PIN7CTRL bit masks and bit positions */ -/* PORT_SRLEN Predefined. */ -/* PORT_SRLEN Predefined. */ - -/* PORT_INVEN Predefined. */ -/* PORT_INVEN Predefined. */ - -/* PORT_OPC Predefined. */ -/* PORT_OPC Predefined. */ - -/* PORT_ISC Predefined. */ -/* PORT_ISC Predefined. */ - -/* TC - 16-bit Timer/Counter With PWM */ -/* TC0.CTRLA bit masks and bit positions */ -#define TC0_CLKSEL_gm 0x0F /* Clock Selection group mask. */ -#define TC0_CLKSEL_gp 0 /* Clock Selection group position. */ -#define TC0_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ -#define TC0_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ -#define TC0_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ -#define TC0_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ -#define TC0_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ -#define TC0_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ -#define TC0_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ -#define TC0_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ - -/* TC0.CTRLB bit masks and bit positions */ -#define TC0_CCDEN_bm 0x80 /* Compare or Capture D Enable bit mask. */ -#define TC0_CCDEN_bp 7 /* Compare or Capture D Enable bit position. */ - -#define TC0_CCCEN_bm 0x40 /* Compare or Capture C Enable bit mask. */ -#define TC0_CCCEN_bp 6 /* Compare or Capture C Enable bit position. */ - -#define TC0_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ -#define TC0_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ - -#define TC0_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ -#define TC0_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ - -#define TC0_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ -#define TC0_WGMODE_gp 0 /* Waveform generation mode group position. */ -#define TC0_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ -#define TC0_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ -#define TC0_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ -#define TC0_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ -#define TC0_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ -#define TC0_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ - -/* TC0.CTRLC bit masks and bit positions */ -#define TC0_CMPD_bm 0x08 /* Compare D Output Value bit mask. */ -#define TC0_CMPD_bp 3 /* Compare D Output Value bit position. */ - -#define TC0_CMPC_bm 0x04 /* Compare C Output Value bit mask. */ -#define TC0_CMPC_bp 2 /* Compare C Output Value bit position. */ - -#define TC0_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ -#define TC0_CMPB_bp 1 /* Compare B Output Value bit position. */ - -#define TC0_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ -#define TC0_CMPA_bp 0 /* Compare A Output Value bit position. */ - -/* TC0.CTRLD bit masks and bit positions */ -#define TC0_EVACT_gm 0xE0 /* Event Action group mask. */ -#define TC0_EVACT_gp 5 /* Event Action group position. */ -#define TC0_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ -#define TC0_EVACT0_bp 5 /* Event Action bit 0 position. */ -#define TC0_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ -#define TC0_EVACT1_bp 6 /* Event Action bit 1 position. */ -#define TC0_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ -#define TC0_EVACT2_bp 7 /* Event Action bit 2 position. */ - -#define TC0_EVDLY_bm 0x10 /* Event Delay bit mask. */ -#define TC0_EVDLY_bp 4 /* Event Delay bit position. */ - -#define TC0_EVSEL_gm 0x0F /* Event Source Select group mask. */ -#define TC0_EVSEL_gp 0 /* Event Source Select group position. */ -#define TC0_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ -#define TC0_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ -#define TC0_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ -#define TC0_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ -#define TC0_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ -#define TC0_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ -#define TC0_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ -#define TC0_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ - -/* TC0.CTRLE bit masks and bit positions */ -#define TC0_BYTEM_gm 0x03 /* Byte Mode group mask. */ -#define TC0_BYTEM_gp 0 /* Byte Mode group position. */ -#define TC0_BYTEM0_bm (1<<0) /* Byte Mode bit 0 mask. */ -#define TC0_BYTEM0_bp 0 /* Byte Mode bit 0 position. */ -#define TC0_BYTEM1_bm (1<<1) /* Byte Mode bit 1 mask. */ -#define TC0_BYTEM1_bp 1 /* Byte Mode bit 1 position. */ - -/* TC0.INTCTRLA bit masks and bit positions */ -#define TC0_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ -#define TC0_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ -#define TC0_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ -#define TC0_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ -#define TC0_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ -#define TC0_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ - -#define TC0_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ -#define TC0_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ -#define TC0_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ -#define TC0_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ -#define TC0_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ -#define TC0_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ - -/* TC0.INTCTRLB bit masks and bit positions */ -#define TC0_CCDINTLVL_gm 0xC0 /* Compare or Capture D Interrupt Level group mask. */ -#define TC0_CCDINTLVL_gp 6 /* Compare or Capture D Interrupt Level group position. */ -#define TC0_CCDINTLVL0_bm (1<<6) /* Compare or Capture D Interrupt Level bit 0 mask. */ -#define TC0_CCDINTLVL0_bp 6 /* Compare or Capture D Interrupt Level bit 0 position. */ -#define TC0_CCDINTLVL1_bm (1<<7) /* Compare or Capture D Interrupt Level bit 1 mask. */ -#define TC0_CCDINTLVL1_bp 7 /* Compare or Capture D Interrupt Level bit 1 position. */ - -#define TC0_CCCINTLVL_gm 0x30 /* Compare or Capture C Interrupt Level group mask. */ -#define TC0_CCCINTLVL_gp 4 /* Compare or Capture C Interrupt Level group position. */ -#define TC0_CCCINTLVL0_bm (1<<4) /* Compare or Capture C Interrupt Level bit 0 mask. */ -#define TC0_CCCINTLVL0_bp 4 /* Compare or Capture C Interrupt Level bit 0 position. */ -#define TC0_CCCINTLVL1_bm (1<<5) /* Compare or Capture C Interrupt Level bit 1 mask. */ -#define TC0_CCCINTLVL1_bp 5 /* Compare or Capture C Interrupt Level bit 1 position. */ - -#define TC0_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ -#define TC0_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ -#define TC0_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ -#define TC0_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ -#define TC0_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ -#define TC0_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ - -#define TC0_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ -#define TC0_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ -#define TC0_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ -#define TC0_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ -#define TC0_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ -#define TC0_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ - -/* TC0.CTRLFCLR bit masks and bit positions */ -#define TC0_CMD_gm 0x0C /* Command group mask. */ -#define TC0_CMD_gp 2 /* Command group position. */ -#define TC0_CMD0_bm (1<<2) /* Command bit 0 mask. */ -#define TC0_CMD0_bp 2 /* Command bit 0 position. */ -#define TC0_CMD1_bm (1<<3) /* Command bit 1 mask. */ -#define TC0_CMD1_bp 3 /* Command bit 1 position. */ - -#define TC0_LUPD_bm 0x02 /* Lock Update bit mask. */ -#define TC0_LUPD_bp 1 /* Lock Update bit position. */ - -#define TC0_DIR_bm 0x01 /* Direction bit mask. */ -#define TC0_DIR_bp 0 /* Direction bit position. */ - -/* TC0.CTRLFSET bit masks and bit positions */ -/* TC0_CMD Predefined. */ -/* TC0_CMD Predefined. */ - -/* TC0_LUPD Predefined. */ -/* TC0_LUPD Predefined. */ - -/* TC0_DIR Predefined. */ -/* TC0_DIR Predefined. */ - -/* TC0.CTRLGCLR bit masks and bit positions */ -#define TC0_CCDBV_bm 0x10 /* Compare or Capture D Buffer Valid bit mask. */ -#define TC0_CCDBV_bp 4 /* Compare or Capture D Buffer Valid bit position. */ - -#define TC0_CCCBV_bm 0x08 /* Compare or Capture C Buffer Valid bit mask. */ -#define TC0_CCCBV_bp 3 /* Compare or Capture C Buffer Valid bit position. */ - -#define TC0_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ -#define TC0_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ - -#define TC0_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ -#define TC0_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ - -#define TC0_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ -#define TC0_PERBV_bp 0 /* Period Buffer Valid bit position. */ - -/* TC0.CTRLGSET bit masks and bit positions */ -/* TC0_CCDBV Predefined. */ -/* TC0_CCDBV Predefined. */ - -/* TC0_CCCBV Predefined. */ -/* TC0_CCCBV Predefined. */ - -/* TC0_CCBBV Predefined. */ -/* TC0_CCBBV Predefined. */ - -/* TC0_CCABV Predefined. */ -/* TC0_CCABV Predefined. */ - -/* TC0_PERBV Predefined. */ -/* TC0_PERBV Predefined. */ - -/* TC0.INTFLAGS bit masks and bit positions */ -#define TC0_CCDIF_bm 0x80 /* Compare or Capture D Interrupt Flag bit mask. */ -#define TC0_CCDIF_bp 7 /* Compare or Capture D Interrupt Flag bit position. */ - -#define TC0_CCCIF_bm 0x40 /* Compare or Capture C Interrupt Flag bit mask. */ -#define TC0_CCCIF_bp 6 /* Compare or Capture C Interrupt Flag bit position. */ - -#define TC0_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ -#define TC0_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ - -#define TC0_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ -#define TC0_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ - -#define TC0_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ -#define TC0_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ - -#define TC0_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ -#define TC0_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ - -/* TC1.CTRLA bit masks and bit positions */ -#define TC1_CLKSEL_gm 0x0F /* Clock Selection group mask. */ -#define TC1_CLKSEL_gp 0 /* Clock Selection group position. */ -#define TC1_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ -#define TC1_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ -#define TC1_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ -#define TC1_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ -#define TC1_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ -#define TC1_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ -#define TC1_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ -#define TC1_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ - -/* TC1.CTRLB bit masks and bit positions */ -#define TC1_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ -#define TC1_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ - -#define TC1_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ -#define TC1_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ - -#define TC1_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ -#define TC1_WGMODE_gp 0 /* Waveform generation mode group position. */ -#define TC1_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ -#define TC1_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ -#define TC1_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ -#define TC1_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ -#define TC1_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ -#define TC1_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ - -/* TC1.CTRLC bit masks and bit positions */ -#define TC1_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ -#define TC1_CMPB_bp 1 /* Compare B Output Value bit position. */ - -#define TC1_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ -#define TC1_CMPA_bp 0 /* Compare A Output Value bit position. */ - -/* TC1.CTRLD bit masks and bit positions */ -#define TC1_EVACT_gm 0xE0 /* Event Action group mask. */ -#define TC1_EVACT_gp 5 /* Event Action group position. */ -#define TC1_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ -#define TC1_EVACT0_bp 5 /* Event Action bit 0 position. */ -#define TC1_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ -#define TC1_EVACT1_bp 6 /* Event Action bit 1 position. */ -#define TC1_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ -#define TC1_EVACT2_bp 7 /* Event Action bit 2 position. */ - -#define TC1_EVDLY_bm 0x10 /* Event Delay bit mask. */ -#define TC1_EVDLY_bp 4 /* Event Delay bit position. */ - -#define TC1_EVSEL_gm 0x0F /* Event Source Select group mask. */ -#define TC1_EVSEL_gp 0 /* Event Source Select group position. */ -#define TC1_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ -#define TC1_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ -#define TC1_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ -#define TC1_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ -#define TC1_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ -#define TC1_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ -#define TC1_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ -#define TC1_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ - -/* TC1.CTRLE bit masks and bit positions */ -#define TC1_BYTEM_bm 0x01 /* Byte Mode bit mask. */ -#define TC1_BYTEM_bp 0 /* Byte Mode bit position. */ - -/* TC1.INTCTRLA bit masks and bit positions */ -#define TC1_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ -#define TC1_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ -#define TC1_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ -#define TC1_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ -#define TC1_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ -#define TC1_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ - -#define TC1_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ -#define TC1_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ -#define TC1_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ -#define TC1_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ -#define TC1_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ -#define TC1_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ - -/* TC1.INTCTRLB bit masks and bit positions */ -#define TC1_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ -#define TC1_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ -#define TC1_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ -#define TC1_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ -#define TC1_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ -#define TC1_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ - -#define TC1_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ -#define TC1_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ -#define TC1_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ -#define TC1_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ -#define TC1_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ -#define TC1_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ - -/* TC1.CTRLFCLR bit masks and bit positions */ -#define TC1_CMD_gm 0x0C /* Command group mask. */ -#define TC1_CMD_gp 2 /* Command group position. */ -#define TC1_CMD0_bm (1<<2) /* Command bit 0 mask. */ -#define TC1_CMD0_bp 2 /* Command bit 0 position. */ -#define TC1_CMD1_bm (1<<3) /* Command bit 1 mask. */ -#define TC1_CMD1_bp 3 /* Command bit 1 position. */ - -#define TC1_LUPD_bm 0x02 /* Lock Update bit mask. */ -#define TC1_LUPD_bp 1 /* Lock Update bit position. */ - -#define TC1_DIR_bm 0x01 /* Direction bit mask. */ -#define TC1_DIR_bp 0 /* Direction bit position. */ - -/* TC1.CTRLFSET bit masks and bit positions */ -/* TC1_CMD Predefined. */ -/* TC1_CMD Predefined. */ - -/* TC1_LUPD Predefined. */ -/* TC1_LUPD Predefined. */ - -/* TC1_DIR Predefined. */ -/* TC1_DIR Predefined. */ - -/* TC1.CTRLGCLR bit masks and bit positions */ -#define TC1_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ -#define TC1_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ - -#define TC1_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ -#define TC1_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ - -#define TC1_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ -#define TC1_PERBV_bp 0 /* Period Buffer Valid bit position. */ - -/* TC1.CTRLGSET bit masks and bit positions */ -/* TC1_CCBBV Predefined. */ -/* TC1_CCBBV Predefined. */ - -/* TC1_CCABV Predefined. */ -/* TC1_CCABV Predefined. */ - -/* TC1_PERBV Predefined. */ -/* TC1_PERBV Predefined. */ - -/* TC1.INTFLAGS bit masks and bit positions */ -#define TC1_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ -#define TC1_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ - -#define TC1_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ -#define TC1_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ - -#define TC1_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ -#define TC1_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ - -#define TC1_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ -#define TC1_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ - -/* TC2 - 16-bit Timer/Counter type 2 */ -/* TC2.CTRLA bit masks and bit positions */ -#define TC2_CLKSEL_gm 0x0F /* Clock Selection group mask. */ -#define TC2_CLKSEL_gp 0 /* Clock Selection group position. */ -#define TC2_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ -#define TC2_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ -#define TC2_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ -#define TC2_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ -#define TC2_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ -#define TC2_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ -#define TC2_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ -#define TC2_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ - -/* TC2.CTRLB bit masks and bit positions */ -#define TC2_HCMPDEN_bm 0x80 /* High Byte Compare D Enable bit mask. */ -#define TC2_HCMPDEN_bp 7 /* High Byte Compare D Enable bit position. */ - -#define TC2_HCMPCEN_bm 0x40 /* High Byte Compare C Enable bit mask. */ -#define TC2_HCMPCEN_bp 6 /* High Byte Compare C Enable bit position. */ - -#define TC2_HCMPBEN_bm 0x20 /* High Byte Compare B Enable bit mask. */ -#define TC2_HCMPBEN_bp 5 /* High Byte Compare B Enable bit position. */ - -#define TC2_HCMPAEN_bm 0x10 /* High Byte Compare A Enable bit mask. */ -#define TC2_HCMPAEN_bp 4 /* High Byte Compare A Enable bit position. */ - -#define TC2_LCMPDEN_bm 0x08 /* Low Byte Compare D Enable bit mask. */ -#define TC2_LCMPDEN_bp 3 /* Low Byte Compare D Enable bit position. */ - -#define TC2_LCMPCEN_bm 0x04 /* Low Byte Compare C Enable bit mask. */ -#define TC2_LCMPCEN_bp 2 /* Low Byte Compare C Enable bit position. */ - -#define TC2_LCMPBEN_bm 0x02 /* Low Byte Compare B Enable bit mask. */ -#define TC2_LCMPBEN_bp 1 /* Low Byte Compare B Enable bit position. */ - -#define TC2_LCMPAEN_bm 0x01 /* Low Byte Compare A Enable bit mask. */ -#define TC2_LCMPAEN_bp 0 /* Low Byte Compare A Enable bit position. */ - -/* TC2.CTRLC bit masks and bit positions */ -#define TC2_HCMPD_bm 0x80 /* High Byte Compare D Output Value bit mask. */ -#define TC2_HCMPD_bp 7 /* High Byte Compare D Output Value bit position. */ - -#define TC2_HCMPC_bm 0x40 /* High Byte Compare C Output Value bit mask. */ -#define TC2_HCMPC_bp 6 /* High Byte Compare C Output Value bit position. */ - -#define TC2_HCMPB_bm 0x20 /* High Byte Compare B Output Value bit mask. */ -#define TC2_HCMPB_bp 5 /* High Byte Compare B Output Value bit position. */ - -#define TC2_HCMPA_bm 0x10 /* High Byte Compare A Output Value bit mask. */ -#define TC2_HCMPA_bp 4 /* High Byte Compare A Output Value bit position. */ - -#define TC2_LCMPD_bm 0x08 /* Low Byte Compare D Output Value bit mask. */ -#define TC2_LCMPD_bp 3 /* Low Byte Compare D Output Value bit position. */ - -#define TC2_LCMPC_bm 0x04 /* Low Byte Compare C Output Value bit mask. */ -#define TC2_LCMPC_bp 2 /* Low Byte Compare C Output Value bit position. */ - -#define TC2_LCMPB_bm 0x02 /* Low Byte Compare B Output Value bit mask. */ -#define TC2_LCMPB_bp 1 /* Low Byte Compare B Output Value bit position. */ - -#define TC2_LCMPA_bm 0x01 /* Low Byte Compare A Output Value bit mask. */ -#define TC2_LCMPA_bp 0 /* Low Byte Compare A Output Value bit position. */ - -/* TC2.CTRLE bit masks and bit positions */ -#define TC2_BYTEM_gm 0x03 /* Byte Mode group mask. */ -#define TC2_BYTEM_gp 0 /* Byte Mode group position. */ -#define TC2_BYTEM0_bm (1<<0) /* Byte Mode bit 0 mask. */ -#define TC2_BYTEM0_bp 0 /* Byte Mode bit 0 position. */ -#define TC2_BYTEM1_bm (1<<1) /* Byte Mode bit 1 mask. */ -#define TC2_BYTEM1_bp 1 /* Byte Mode bit 1 position. */ - -/* TC2.INTCTRLA bit masks and bit positions */ -#define TC2_HUNFINTLVL_gm 0x0C /* High Byte Underflow Interrupt Level group mask. */ -#define TC2_HUNFINTLVL_gp 2 /* High Byte Underflow Interrupt Level group position. */ -#define TC2_HUNFINTLVL0_bm (1<<2) /* High Byte Underflow Interrupt Level bit 0 mask. */ -#define TC2_HUNFINTLVL0_bp 2 /* High Byte Underflow Interrupt Level bit 0 position. */ -#define TC2_HUNFINTLVL1_bm (1<<3) /* High Byte Underflow Interrupt Level bit 1 mask. */ -#define TC2_HUNFINTLVL1_bp 3 /* High Byte Underflow Interrupt Level bit 1 position. */ - -#define TC2_LUNFINTLVL_gm 0x03 /* Low Byte Underflow interrupt level group mask. */ -#define TC2_LUNFINTLVL_gp 0 /* Low Byte Underflow interrupt level group position. */ -#define TC2_LUNFINTLVL0_bm (1<<0) /* Low Byte Underflow interrupt level bit 0 mask. */ -#define TC2_LUNFINTLVL0_bp 0 /* Low Byte Underflow interrupt level bit 0 position. */ -#define TC2_LUNFINTLVL1_bm (1<<1) /* Low Byte Underflow interrupt level bit 1 mask. */ -#define TC2_LUNFINTLVL1_bp 1 /* Low Byte Underflow interrupt level bit 1 position. */ - -/* TC2.INTCTRLB bit masks and bit positions */ -#define TC2_LCMPDINTLVL_gm 0xC0 /* Low Byte Compare D Interrupt Level group mask. */ -#define TC2_LCMPDINTLVL_gp 6 /* Low Byte Compare D Interrupt Level group position. */ -#define TC2_LCMPDINTLVL0_bm (1<<6) /* Low Byte Compare D Interrupt Level bit 0 mask. */ -#define TC2_LCMPDINTLVL0_bp 6 /* Low Byte Compare D Interrupt Level bit 0 position. */ -#define TC2_LCMPDINTLVL1_bm (1<<7) /* Low Byte Compare D Interrupt Level bit 1 mask. */ -#define TC2_LCMPDINTLVL1_bp 7 /* Low Byte Compare D Interrupt Level bit 1 position. */ - -#define TC2_LCMPCINTLVL_gm 0x30 /* Low Byte Compare C Interrupt Level group mask. */ -#define TC2_LCMPCINTLVL_gp 4 /* Low Byte Compare C Interrupt Level group position. */ -#define TC2_LCMPCINTLVL0_bm (1<<4) /* Low Byte Compare C Interrupt Level bit 0 mask. */ -#define TC2_LCMPCINTLVL0_bp 4 /* Low Byte Compare C Interrupt Level bit 0 position. */ -#define TC2_LCMPCINTLVL1_bm (1<<5) /* Low Byte Compare C Interrupt Level bit 1 mask. */ -#define TC2_LCMPCINTLVL1_bp 5 /* Low Byte Compare C Interrupt Level bit 1 position. */ - -#define TC2_LCMPBINTLVL_gm 0x0C /* Low Byte Compare B Interrupt Level group mask. */ -#define TC2_LCMPBINTLVL_gp 2 /* Low Byte Compare B Interrupt Level group position. */ -#define TC2_LCMPBINTLVL0_bm (1<<2) /* Low Byte Compare B Interrupt Level bit 0 mask. */ -#define TC2_LCMPBINTLVL0_bp 2 /* Low Byte Compare B Interrupt Level bit 0 position. */ -#define TC2_LCMPBINTLVL1_bm (1<<3) /* Low Byte Compare B Interrupt Level bit 1 mask. */ -#define TC2_LCMPBINTLVL1_bp 3 /* Low Byte Compare B Interrupt Level bit 1 position. */ - -#define TC2_LCMPAINTLVL_gm 0x03 /* Low Byte Compare A Interrupt Level group mask. */ -#define TC2_LCMPAINTLVL_gp 0 /* Low Byte Compare A Interrupt Level group position. */ -#define TC2_LCMPAINTLVL0_bm (1<<0) /* Low Byte Compare A Interrupt Level bit 0 mask. */ -#define TC2_LCMPAINTLVL0_bp 0 /* Low Byte Compare A Interrupt Level bit 0 position. */ -#define TC2_LCMPAINTLVL1_bm (1<<1) /* Low Byte Compare A Interrupt Level bit 1 mask. */ -#define TC2_LCMPAINTLVL1_bp 1 /* Low Byte Compare A Interrupt Level bit 1 position. */ - -/* TC2.CTRLF bit masks and bit positions */ -#define TC2_CMD_gm 0x0C /* Command group mask. */ -#define TC2_CMD_gp 2 /* Command group position. */ -#define TC2_CMD0_bm (1<<2) /* Command bit 0 mask. */ -#define TC2_CMD0_bp 2 /* Command bit 0 position. */ -#define TC2_CMD1_bm (1<<3) /* Command bit 1 mask. */ -#define TC2_CMD1_bp 3 /* Command bit 1 position. */ - -#define TC2_CMDEN_gm 0x03 /* Command Enable group mask. */ -#define TC2_CMDEN_gp 0 /* Command Enable group position. */ -#define TC2_CMDEN0_bm (1<<0) /* Command Enable bit 0 mask. */ -#define TC2_CMDEN0_bp 0 /* Command Enable bit 0 position. */ -#define TC2_CMDEN1_bm (1<<1) /* Command Enable bit 1 mask. */ -#define TC2_CMDEN1_bp 1 /* Command Enable bit 1 position. */ - -/* TC2.INTFLAGS bit masks and bit positions */ -#define TC2_LCMPDIF_bm 0x80 /* Low Byte Compare D Interrupt Flag bit mask. */ -#define TC2_LCMPDIF_bp 7 /* Low Byte Compare D Interrupt Flag bit position. */ - -#define TC2_LCMPCIF_bm 0x40 /* Low Byte Compare C Interrupt Flag bit mask. */ -#define TC2_LCMPCIF_bp 6 /* Low Byte Compare C Interrupt Flag bit position. */ - -#define TC2_LCMPBIF_bm 0x20 /* Low Byte Compare B Interrupt Flag bit mask. */ -#define TC2_LCMPBIF_bp 5 /* Low Byte Compare B Interrupt Flag bit position. */ - -#define TC2_LCMPAIF_bm 0x10 /* Low Byte Compare A Interrupt Flag bit mask. */ -#define TC2_LCMPAIF_bp 4 /* Low Byte Compare A Interrupt Flag bit position. */ - -#define TC2_HUNFIF_bm 0x02 /* High Byte Underflow Interrupt Flag bit mask. */ -#define TC2_HUNFIF_bp 1 /* High Byte Underflow Interrupt Flag bit position. */ - -#define TC2_LUNFIF_bm 0x01 /* Low Byte Underflow Interrupt Flag bit mask. */ -#define TC2_LUNFIF_bp 0 /* Low Byte Underflow Interrupt Flag bit position. */ - -/* AWEX - Timer/Counter Advanced Waveform Extension */ -/* AWEX.CTRL bit masks and bit positions */ -#define AWEX_PGM_bm 0x20 /* Pattern Generation Mode bit mask. */ -#define AWEX_PGM_bp 5 /* Pattern Generation Mode bit position. */ - -#define AWEX_CWCM_bm 0x10 /* Common Waveform Channel Mode bit mask. */ -#define AWEX_CWCM_bp 4 /* Common Waveform Channel Mode bit position. */ - -#define AWEX_DTICCDEN_bm 0x08 /* Dead Time Insertion Compare Channel D Enable bit mask. */ -#define AWEX_DTICCDEN_bp 3 /* Dead Time Insertion Compare Channel D Enable bit position. */ - -#define AWEX_DTICCCEN_bm 0x04 /* Dead Time Insertion Compare Channel C Enable bit mask. */ -#define AWEX_DTICCCEN_bp 2 /* Dead Time Insertion Compare Channel C Enable bit position. */ - -#define AWEX_DTICCBEN_bm 0x02 /* Dead Time Insertion Compare Channel B Enable bit mask. */ -#define AWEX_DTICCBEN_bp 1 /* Dead Time Insertion Compare Channel B Enable bit position. */ - -#define AWEX_DTICCAEN_bm 0x01 /* Dead Time Insertion Compare Channel A Enable bit mask. */ -#define AWEX_DTICCAEN_bp 0 /* Dead Time Insertion Compare Channel A Enable bit position. */ - -/* AWEX.FDCTRL bit masks and bit positions */ -#define AWEX_FDDBD_bm 0x10 /* Fault Detect on Disable Break Disable bit mask. */ -#define AWEX_FDDBD_bp 4 /* Fault Detect on Disable Break Disable bit position. */ - -#define AWEX_FDMODE_bm 0x04 /* Fault Detect Mode bit mask. */ -#define AWEX_FDMODE_bp 2 /* Fault Detect Mode bit position. */ - -#define AWEX_FDACT_gm 0x03 /* Fault Detect Action group mask. */ -#define AWEX_FDACT_gp 0 /* Fault Detect Action group position. */ -#define AWEX_FDACT0_bm (1<<0) /* Fault Detect Action bit 0 mask. */ -#define AWEX_FDACT0_bp 0 /* Fault Detect Action bit 0 position. */ -#define AWEX_FDACT1_bm (1<<1) /* Fault Detect Action bit 1 mask. */ -#define AWEX_FDACT1_bp 1 /* Fault Detect Action bit 1 position. */ - -/* AWEX.STATUS bit masks and bit positions */ -#define AWEX_FDF_bm 0x04 /* Fault Detect Flag bit mask. */ -#define AWEX_FDF_bp 2 /* Fault Detect Flag bit position. */ - -#define AWEX_DTHSBUFV_bm 0x02 /* Dead Time High Side Buffer Valid bit mask. */ -#define AWEX_DTHSBUFV_bp 1 /* Dead Time High Side Buffer Valid bit position. */ - -#define AWEX_DTLSBUFV_bm 0x01 /* Dead Time Low Side Buffer Valid bit mask. */ -#define AWEX_DTLSBUFV_bp 0 /* Dead Time Low Side Buffer Valid bit position. */ - -/* AWEX.STATUSSET bit masks and bit positions */ -/* AWEX_FDF Predefined. */ -/* AWEX_FDF Predefined. */ - -/* AWEX_DTHSBUFV Predefined. */ -/* AWEX_DTHSBUFV Predefined. */ - -/* AWEX_DTLSBUFV Predefined. */ -/* AWEX_DTLSBUFV Predefined. */ - -/* HIRES - Timer/Counter High-Resolution Extension */ -/* HIRES.CTRLA bit masks and bit positions */ -#define HIRES_HREN_gm 0x03 /* High Resolution Enable group mask. */ -#define HIRES_HREN_gp 0 /* High Resolution Enable group position. */ -#define HIRES_HREN0_bm (1<<0) /* High Resolution Enable bit 0 mask. */ -#define HIRES_HREN0_bp 0 /* High Resolution Enable bit 0 position. */ -#define HIRES_HREN1_bm (1<<1) /* High Resolution Enable bit 1 mask. */ -#define HIRES_HREN1_bp 1 /* High Resolution Enable bit 1 position. */ - -/* USART - Universal Asynchronous Receiver-Transmitter */ -/* USART.STATUS bit masks and bit positions */ -#define USART_RXCIF_bm 0x80 /* Receive Interrupt Flag bit mask. */ -#define USART_RXCIF_bp 7 /* Receive Interrupt Flag bit position. */ - -#define USART_TXCIF_bm 0x40 /* Transmit Interrupt Flag bit mask. */ -#define USART_TXCIF_bp 6 /* Transmit Interrupt Flag bit position. */ - -#define USART_DREIF_bm 0x20 /* Data Register Empty Flag bit mask. */ -#define USART_DREIF_bp 5 /* Data Register Empty Flag bit position. */ - -#define USART_FERR_bm 0x10 /* Frame Error bit mask. */ -#define USART_FERR_bp 4 /* Frame Error bit position. */ - -#define USART_BUFOVF_bm 0x08 /* Buffer Overflow bit mask. */ -#define USART_BUFOVF_bp 3 /* Buffer Overflow bit position. */ - -#define USART_PERR_bm 0x04 /* Parity Error bit mask. */ -#define USART_PERR_bp 2 /* Parity Error bit position. */ - -#define USART_RXB8_bm 0x01 /* Receive Bit 8 bit mask. */ -#define USART_RXB8_bp 0 /* Receive Bit 8 bit position. */ - -/* USART.CTRLA bit masks and bit positions */ -#define USART_RXCINTLVL_gm 0x30 /* Receive Interrupt Level group mask. */ -#define USART_RXCINTLVL_gp 4 /* Receive Interrupt Level group position. */ -#define USART_RXCINTLVL0_bm (1<<4) /* Receive Interrupt Level bit 0 mask. */ -#define USART_RXCINTLVL0_bp 4 /* Receive Interrupt Level bit 0 position. */ -#define USART_RXCINTLVL1_bm (1<<5) /* Receive Interrupt Level bit 1 mask. */ -#define USART_RXCINTLVL1_bp 5 /* Receive Interrupt Level bit 1 position. */ - -#define USART_TXCINTLVL_gm 0x0C /* Transmit Interrupt Level group mask. */ -#define USART_TXCINTLVL_gp 2 /* Transmit Interrupt Level group position. */ -#define USART_TXCINTLVL0_bm (1<<2) /* Transmit Interrupt Level bit 0 mask. */ -#define USART_TXCINTLVL0_bp 2 /* Transmit Interrupt Level bit 0 position. */ -#define USART_TXCINTLVL1_bm (1<<3) /* Transmit Interrupt Level bit 1 mask. */ -#define USART_TXCINTLVL1_bp 3 /* Transmit Interrupt Level bit 1 position. */ - -#define USART_DREINTLVL_gm 0x03 /* Data Register Empty Interrupt Level group mask. */ -#define USART_DREINTLVL_gp 0 /* Data Register Empty Interrupt Level group position. */ -#define USART_DREINTLVL0_bm (1<<0) /* Data Register Empty Interrupt Level bit 0 mask. */ -#define USART_DREINTLVL0_bp 0 /* Data Register Empty Interrupt Level bit 0 position. */ -#define USART_DREINTLVL1_bm (1<<1) /* Data Register Empty Interrupt Level bit 1 mask. */ -#define USART_DREINTLVL1_bp 1 /* Data Register Empty Interrupt Level bit 1 position. */ - -/* USART.CTRLB bit masks and bit positions */ -#define USART_RXEN_bm 0x10 /* Receiver Enable bit mask. */ -#define USART_RXEN_bp 4 /* Receiver Enable bit position. */ - -#define USART_TXEN_bm 0x08 /* Transmitter Enable bit mask. */ -#define USART_TXEN_bp 3 /* Transmitter Enable bit position. */ - -#define USART_CLK2X_bm 0x04 /* Double transmission speed bit mask. */ -#define USART_CLK2X_bp 2 /* Double transmission speed bit position. */ - -#define USART_MPCM_bm 0x02 /* Multi-processor Communication Mode bit mask. */ -#define USART_MPCM_bp 1 /* Multi-processor Communication Mode bit position. */ - -#define USART_TXB8_bm 0x01 /* Transmit bit 8 bit mask. */ -#define USART_TXB8_bp 0 /* Transmit bit 8 bit position. */ - -/* USART.CTRLC bit masks and bit positions */ -#define USART_CMODE_gm 0xC0 /* Communication Mode group mask. */ -#define USART_CMODE_gp 6 /* Communication Mode group position. */ -#define USART_CMODE0_bm (1<<6) /* Communication Mode bit 0 mask. */ -#define USART_CMODE0_bp 6 /* Communication Mode bit 0 position. */ -#define USART_CMODE1_bm (1<<7) /* Communication Mode bit 1 mask. */ -#define USART_CMODE1_bp 7 /* Communication Mode bit 1 position. */ - -#define USART_PMODE_gm 0x30 /* Parity Mode group mask. */ -#define USART_PMODE_gp 4 /* Parity Mode group position. */ -#define USART_PMODE0_bm (1<<4) /* Parity Mode bit 0 mask. */ -#define USART_PMODE0_bp 4 /* Parity Mode bit 0 position. */ -#define USART_PMODE1_bm (1<<5) /* Parity Mode bit 1 mask. */ -#define USART_PMODE1_bp 5 /* Parity Mode bit 1 position. */ - -#define USART_SBMODE_bm 0x08 /* Stop Bit Mode bit mask. */ -#define USART_SBMODE_bp 3 /* Stop Bit Mode bit position. */ - -#define USART_CHSIZE_gm 0x07 /* Character Size group mask. */ -#define USART_CHSIZE_gp 0 /* Character Size group position. */ -#define USART_CHSIZE0_bm (1<<0) /* Character Size bit 0 mask. */ -#define USART_CHSIZE0_bp 0 /* Character Size bit 0 position. */ -#define USART_CHSIZE1_bm (1<<1) /* Character Size bit 1 mask. */ -#define USART_CHSIZE1_bp 1 /* Character Size bit 1 position. */ -#define USART_CHSIZE2_bm (1<<2) /* Character Size bit 2 mask. */ -#define USART_CHSIZE2_bp 2 /* Character Size bit 2 position. */ - -/* USART.BAUDCTRLA bit masks and bit positions */ -#define USART_BSEL_gm 0xFF /* Baud Rate Selection Bits [7:0] group mask. */ -#define USART_BSEL_gp 0 /* Baud Rate Selection Bits [7:0] group position. */ -#define USART_BSEL0_bm (1<<0) /* Baud Rate Selection Bits [7:0] bit 0 mask. */ -#define USART_BSEL0_bp 0 /* Baud Rate Selection Bits [7:0] bit 0 position. */ -#define USART_BSEL1_bm (1<<1) /* Baud Rate Selection Bits [7:0] bit 1 mask. */ -#define USART_BSEL1_bp 1 /* Baud Rate Selection Bits [7:0] bit 1 position. */ -#define USART_BSEL2_bm (1<<2) /* Baud Rate Selection Bits [7:0] bit 2 mask. */ -#define USART_BSEL2_bp 2 /* Baud Rate Selection Bits [7:0] bit 2 position. */ -#define USART_BSEL3_bm (1<<3) /* Baud Rate Selection Bits [7:0] bit 3 mask. */ -#define USART_BSEL3_bp 3 /* Baud Rate Selection Bits [7:0] bit 3 position. */ -#define USART_BSEL4_bm (1<<4) /* Baud Rate Selection Bits [7:0] bit 4 mask. */ -#define USART_BSEL4_bp 4 /* Baud Rate Selection Bits [7:0] bit 4 position. */ -#define USART_BSEL5_bm (1<<5) /* Baud Rate Selection Bits [7:0] bit 5 mask. */ -#define USART_BSEL5_bp 5 /* Baud Rate Selection Bits [7:0] bit 5 position. */ -#define USART_BSEL6_bm (1<<6) /* Baud Rate Selection Bits [7:0] bit 6 mask. */ -#define USART_BSEL6_bp 6 /* Baud Rate Selection Bits [7:0] bit 6 position. */ -#define USART_BSEL7_bm (1<<7) /* Baud Rate Selection Bits [7:0] bit 7 mask. */ -#define USART_BSEL7_bp 7 /* Baud Rate Selection Bits [7:0] bit 7 position. */ - -/* USART.BAUDCTRLB bit masks and bit positions */ -#define USART_BSCALE_gm 0xF0 /* Baud Rate Scale group mask. */ -#define USART_BSCALE_gp 4 /* Baud Rate Scale group position. */ -#define USART_BSCALE0_bm (1<<4) /* Baud Rate Scale bit 0 mask. */ -#define USART_BSCALE0_bp 4 /* Baud Rate Scale bit 0 position. */ -#define USART_BSCALE1_bm (1<<5) /* Baud Rate Scale bit 1 mask. */ -#define USART_BSCALE1_bp 5 /* Baud Rate Scale bit 1 position. */ -#define USART_BSCALE2_bm (1<<6) /* Baud Rate Scale bit 2 mask. */ -#define USART_BSCALE2_bp 6 /* Baud Rate Scale bit 2 position. */ -#define USART_BSCALE3_bm (1<<7) /* Baud Rate Scale bit 3 mask. */ -#define USART_BSCALE3_bp 7 /* Baud Rate Scale bit 3 position. */ - -/* USART_BSEL Predefined. */ -/* USART_BSEL Predefined. */ - -/* SPI - Serial Peripheral Interface */ -/* SPI.CTRL bit masks and bit positions */ -#define SPI_CLK2X_bm 0x80 /* Enable Double Speed bit mask. */ -#define SPI_CLK2X_bp 7 /* Enable Double Speed bit position. */ - -#define SPI_ENABLE_bm 0x40 /* Enable Module bit mask. */ -#define SPI_ENABLE_bp 6 /* Enable Module bit position. */ - -#define SPI_DORD_bm 0x20 /* Data Order Setting bit mask. */ -#define SPI_DORD_bp 5 /* Data Order Setting bit position. */ - -#define SPI_MASTER_bm 0x10 /* Master Operation Enable bit mask. */ -#define SPI_MASTER_bp 4 /* Master Operation Enable bit position. */ - -#define SPI_MODE_gm 0x0C /* SPI Mode group mask. */ -#define SPI_MODE_gp 2 /* SPI Mode group position. */ -#define SPI_MODE0_bm (1<<2) /* SPI Mode bit 0 mask. */ -#define SPI_MODE0_bp 2 /* SPI Mode bit 0 position. */ -#define SPI_MODE1_bm (1<<3) /* SPI Mode bit 1 mask. */ -#define SPI_MODE1_bp 3 /* SPI Mode bit 1 position. */ - -#define SPI_PRESCALER_gm 0x03 /* Prescaler group mask. */ -#define SPI_PRESCALER_gp 0 /* Prescaler group position. */ -#define SPI_PRESCALER0_bm (1<<0) /* Prescaler bit 0 mask. */ -#define SPI_PRESCALER0_bp 0 /* Prescaler bit 0 position. */ -#define SPI_PRESCALER1_bm (1<<1) /* Prescaler bit 1 mask. */ -#define SPI_PRESCALER1_bp 1 /* Prescaler bit 1 position. */ - -/* SPI.INTCTRL bit masks and bit positions */ -#define SPI_INTLVL_gm 0x03 /* Interrupt level group mask. */ -#define SPI_INTLVL_gp 0 /* Interrupt level group position. */ -#define SPI_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */ -#define SPI_INTLVL0_bp 0 /* Interrupt level bit 0 position. */ -#define SPI_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */ -#define SPI_INTLVL1_bp 1 /* Interrupt level bit 1 position. */ - -/* SPI.STATUS bit masks and bit positions */ -#define SPI_IF_bm 0x80 /* Interrupt Flag bit mask. */ -#define SPI_IF_bp 7 /* Interrupt Flag bit position. */ - -#define SPI_WRCOL_bm 0x40 /* Write Collision bit mask. */ -#define SPI_WRCOL_bp 6 /* Write Collision bit position. */ - -/* IRCOM - IR Communication Module */ -/* IRCOM.CTRL bit masks and bit positions */ -#define IRCOM_EVSEL_gm 0x0F /* Event Channel Select group mask. */ -#define IRCOM_EVSEL_gp 0 /* Event Channel Select group position. */ -#define IRCOM_EVSEL0_bm (1<<0) /* Event Channel Select bit 0 mask. */ -#define IRCOM_EVSEL0_bp 0 /* Event Channel Select bit 0 position. */ -#define IRCOM_EVSEL1_bm (1<<1) /* Event Channel Select bit 1 mask. */ -#define IRCOM_EVSEL1_bp 1 /* Event Channel Select bit 1 position. */ -#define IRCOM_EVSEL2_bm (1<<2) /* Event Channel Select bit 2 mask. */ -#define IRCOM_EVSEL2_bp 2 /* Event Channel Select bit 2 position. */ -#define IRCOM_EVSEL3_bm (1<<3) /* Event Channel Select bit 3 mask. */ -#define IRCOM_EVSEL3_bp 3 /* Event Channel Select bit 3 position. */ - -/* FUSE - Fuses and Lockbits */ -/* NVM_FUSES.FUSEBYTE1 bit masks and bit positions */ -#define NVM_FUSES_WDWP_gm 0xF0 /* Watchdog Window Timeout Period group mask. */ -#define NVM_FUSES_WDWP_gp 4 /* Watchdog Window Timeout Period group position. */ -#define NVM_FUSES_WDWP0_bm (1<<4) /* Watchdog Window Timeout Period bit 0 mask. */ -#define NVM_FUSES_WDWP0_bp 4 /* Watchdog Window Timeout Period bit 0 position. */ -#define NVM_FUSES_WDWP1_bm (1<<5) /* Watchdog Window Timeout Period bit 1 mask. */ -#define NVM_FUSES_WDWP1_bp 5 /* Watchdog Window Timeout Period bit 1 position. */ -#define NVM_FUSES_WDWP2_bm (1<<6) /* Watchdog Window Timeout Period bit 2 mask. */ -#define NVM_FUSES_WDWP2_bp 6 /* Watchdog Window Timeout Period bit 2 position. */ -#define NVM_FUSES_WDWP3_bm (1<<7) /* Watchdog Window Timeout Period bit 3 mask. */ -#define NVM_FUSES_WDWP3_bp 7 /* Watchdog Window Timeout Period bit 3 position. */ - -#define NVM_FUSES_WDP_gm 0x0F /* Watchdog Timeout Period group mask. */ -#define NVM_FUSES_WDP_gp 0 /* Watchdog Timeout Period group position. */ -#define NVM_FUSES_WDP0_bm (1<<0) /* Watchdog Timeout Period bit 0 mask. */ -#define NVM_FUSES_WDP0_bp 0 /* Watchdog Timeout Period bit 0 position. */ -#define NVM_FUSES_WDP1_bm (1<<1) /* Watchdog Timeout Period bit 1 mask. */ -#define NVM_FUSES_WDP1_bp 1 /* Watchdog Timeout Period bit 1 position. */ -#define NVM_FUSES_WDP2_bm (1<<2) /* Watchdog Timeout Period bit 2 mask. */ -#define NVM_FUSES_WDP2_bp 2 /* Watchdog Timeout Period bit 2 position. */ -#define NVM_FUSES_WDP3_bm (1<<3) /* Watchdog Timeout Period bit 3 mask. */ -#define NVM_FUSES_WDP3_bp 3 /* Watchdog Timeout Period bit 3 position. */ - -/* NVM_FUSES.FUSEBYTE2 bit masks and bit positions */ -#define NVM_FUSES_BOOTRST_bm 0x40 /* Boot Loader Section Reset Vector bit mask. */ -#define NVM_FUSES_BOOTRST_bp 6 /* Boot Loader Section Reset Vector bit position. */ - -#define NVM_FUSES_TOSCSEL_bm 0x20 /* Timer Oscillator pin location bit mask. */ -#define NVM_FUSES_TOSCSEL_bp 5 /* Timer Oscillator pin location bit position. */ - -#define NVM_FUSES_BODPD_gm 0x03 /* BOD Operation in Power-Down Mode group mask. */ -#define NVM_FUSES_BODPD_gp 0 /* BOD Operation in Power-Down Mode group position. */ -#define NVM_FUSES_BODPD0_bm (1<<0) /* BOD Operation in Power-Down Mode bit 0 mask. */ -#define NVM_FUSES_BODPD0_bp 0 /* BOD Operation in Power-Down Mode bit 0 position. */ -#define NVM_FUSES_BODPD1_bm (1<<1) /* BOD Operation in Power-Down Mode bit 1 mask. */ -#define NVM_FUSES_BODPD1_bp 1 /* BOD Operation in Power-Down Mode bit 1 position. */ - -/* NVM_FUSES.FUSEBYTE4 bit masks and bit positions */ -#define NVM_FUSES_RSTDISBL_bm 0x10 /* External Reset Disable bit mask. */ -#define NVM_FUSES_RSTDISBL_bp 4 /* External Reset Disable bit position. */ - -#define NVM_FUSES_SUT_gm 0x0C /* Start-up Time group mask. */ -#define NVM_FUSES_SUT_gp 2 /* Start-up Time group position. */ -#define NVM_FUSES_SUT0_bm (1<<2) /* Start-up Time bit 0 mask. */ -#define NVM_FUSES_SUT0_bp 2 /* Start-up Time bit 0 position. */ -#define NVM_FUSES_SUT1_bm (1<<3) /* Start-up Time bit 1 mask. */ -#define NVM_FUSES_SUT1_bp 3 /* Start-up Time bit 1 position. */ - -#define NVM_FUSES_WDLOCK_bm 0x02 /* Watchdog Timer Lock bit mask. */ -#define NVM_FUSES_WDLOCK_bp 1 /* Watchdog Timer Lock bit position. */ - -/* NVM_FUSES.FUSEBYTE5 bit masks and bit positions */ -#define NVM_FUSES_BODACT_gm 0x30 /* BOD Operation in Active Mode group mask. */ -#define NVM_FUSES_BODACT_gp 4 /* BOD Operation in Active Mode group position. */ -#define NVM_FUSES_BODACT0_bm (1<<4) /* BOD Operation in Active Mode bit 0 mask. */ -#define NVM_FUSES_BODACT0_bp 4 /* BOD Operation in Active Mode bit 0 position. */ -#define NVM_FUSES_BODACT1_bm (1<<5) /* BOD Operation in Active Mode bit 1 mask. */ -#define NVM_FUSES_BODACT1_bp 5 /* BOD Operation in Active Mode bit 1 position. */ - -#define NVM_FUSES_EESAVE_bm 0x08 /* Preserve EEPROM Through Chip Erase bit mask. */ -#define NVM_FUSES_EESAVE_bp 3 /* Preserve EEPROM Through Chip Erase bit position. */ - -#define NVM_FUSES_BODLVL_gm 0x07 /* Brownout Detection Voltage Level group mask. */ -#define NVM_FUSES_BODLVL_gp 0 /* Brownout Detection Voltage Level group position. */ -#define NVM_FUSES_BODLVL0_bm (1<<0) /* Brownout Detection Voltage Level bit 0 mask. */ -#define NVM_FUSES_BODLVL0_bp 0 /* Brownout Detection Voltage Level bit 0 position. */ -#define NVM_FUSES_BODLVL1_bm (1<<1) /* Brownout Detection Voltage Level bit 1 mask. */ -#define NVM_FUSES_BODLVL1_bp 1 /* Brownout Detection Voltage Level bit 1 position. */ -#define NVM_FUSES_BODLVL2_bm (1<<2) /* Brownout Detection Voltage Level bit 2 mask. */ -#define NVM_FUSES_BODLVL2_bp 2 /* Brownout Detection Voltage Level bit 2 position. */ - -/* LOCKBIT - Fuses and Lockbits */ -/* NVM_LOCKBITS.LOCKBITS bit masks and bit positions */ -#define NVM_LOCKBITS_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ -#define NVM_LOCKBITS_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ -#define NVM_LOCKBITS_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ -#define NVM_LOCKBITS_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ -#define NVM_LOCKBITS_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ -#define NVM_LOCKBITS_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ - -#define NVM_LOCKBITS_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ -#define NVM_LOCKBITS_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ -#define NVM_LOCKBITS_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ -#define NVM_LOCKBITS_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ -#define NVM_LOCKBITS_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ -#define NVM_LOCKBITS_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ - -#define NVM_LOCKBITS_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ -#define NVM_LOCKBITS_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ -#define NVM_LOCKBITS_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ -#define NVM_LOCKBITS_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ -#define NVM_LOCKBITS_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ -#define NVM_LOCKBITS_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ - -#define NVM_LOCKBITS_LB_gm 0x03 /* Lock Bits group mask. */ -#define NVM_LOCKBITS_LB_gp 0 /* Lock Bits group position. */ -#define NVM_LOCKBITS_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ -#define NVM_LOCKBITS_LB0_bp 0 /* Lock Bits bit 0 position. */ -#define NVM_LOCKBITS_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ -#define NVM_LOCKBITS_LB1_bp 1 /* Lock Bits bit 1 position. */ - - - -// Generic Port Pins - -#define PIN0_bm 0x01 -#define PIN0_bp 0 -#define PIN1_bm 0x02 -#define PIN1_bp 1 -#define PIN2_bm 0x04 -#define PIN2_bp 2 -#define PIN3_bm 0x08 -#define PIN3_bp 3 -#define PIN4_bm 0x10 -#define PIN4_bp 4 -#define PIN5_bm 0x20 -#define PIN5_bp 5 -#define PIN6_bm 0x40 -#define PIN6_bp 6 -#define PIN7_bm 0x80 -#define PIN7_bp 7 - -/* ========== Interrupt Vector Definitions ========== */ -/* Vector 0 is the reset vector */ - -/* OSC interrupt vectors */ -#define OSC_OSCF_vect_num 1 -#define OSC_OSCF_vect _VECTOR(1) /* Oscillator Failure Interrupt (NMI) */ - -/* PORTC interrupt vectors */ -#define PORTC_INT0_vect_num 2 -#define PORTC_INT0_vect _VECTOR(2) /* External Interrupt 0 */ -#define PORTC_INT1_vect_num 3 -#define PORTC_INT1_vect _VECTOR(3) /* External Interrupt 1 */ - -/* PORTR interrupt vectors */ -#define PORTR_INT0_vect_num 4 -#define PORTR_INT0_vect _VECTOR(4) /* External Interrupt 0 */ -#define PORTR_INT1_vect_num 5 -#define PORTR_INT1_vect _VECTOR(5) /* External Interrupt 1 */ - -/* DMA interrupt vectors */ -#define DMA_CH0_vect_num 6 -#define DMA_CH0_vect _VECTOR(6) /* Channel 0 Interrupt */ -#define DMA_CH1_vect_num 7 -#define DMA_CH1_vect _VECTOR(7) /* Channel 1 Interrupt */ -#define DMA_CH2_vect_num 8 -#define DMA_CH2_vect _VECTOR(8) /* Channel 2 Interrupt */ -#define DMA_CH3_vect_num 9 -#define DMA_CH3_vect _VECTOR(9) /* Channel 3 Interrupt */ - -/* RTC interrupt vectors */ -#define RTC_OVF_vect_num 10 -#define RTC_OVF_vect _VECTOR(10) /* Overflow Interrupt */ -#define RTC_COMP_vect_num 11 -#define RTC_COMP_vect _VECTOR(11) /* Compare Interrupt */ - -/* TWIC interrupt vectors */ -#define TWIC_TWIS_vect_num 12 -#define TWIC_TWIS_vect _VECTOR(12) /* TWI Slave Interrupt */ -#define TWIC_TWIM_vect_num 13 -#define TWIC_TWIM_vect _VECTOR(13) /* TWI Master Interrupt */ - -/* TCC0 interrupt vectors */ -#define TCC0_OVF_vect_num 14 -#define TCC0_OVF_vect _VECTOR(14) /* Overflow Interrupt */ - -/* TCC2 interrupt vectors */ -#define TCC2_LUNF_vect_num 14 -#define TCC2_LUNF_vect _VECTOR(14) /* Low Byte Underflow Interrupt */ - -/* TCC0 interrupt vectors */ -#define TCC0_ERR_vect_num 15 -#define TCC0_ERR_vect _VECTOR(15) /* Error Interrupt */ - -/* TCC2 interrupt vectors */ -#define TCC2_HUNF_vect_num 15 -#define TCC2_HUNF_vect _VECTOR(15) /* High Byte Underflow Interrupt */ - -/* TCC0 interrupt vectors */ -#define TCC0_CCA_vect_num 16 -#define TCC0_CCA_vect _VECTOR(16) /* Compare or Capture A Interrupt */ - -/* TCC2 interrupt vectors */ -#define TCC2_LCMPA_vect_num 16 -#define TCC2_LCMPA_vect _VECTOR(16) /* Low Byte Compare A Interrupt */ - -/* TCC0 interrupt vectors */ -#define TCC0_CCB_vect_num 17 -#define TCC0_CCB_vect _VECTOR(17) /* Compare or Capture B Interrupt */ - -/* TCC2 interrupt vectors */ -#define TCC2_LCMPB_vect_num 17 -#define TCC2_LCMPB_vect _VECTOR(17) /* Low Byte Compare B Interrupt */ - -/* TCC0 interrupt vectors */ -#define TCC0_CCC_vect_num 18 -#define TCC0_CCC_vect _VECTOR(18) /* Compare or Capture C Interrupt */ - -/* TCC2 interrupt vectors */ -#define TCC2_LCMPC_vect_num 18 -#define TCC2_LCMPC_vect _VECTOR(18) /* Low Byte Compare C Interrupt */ - -/* TCC0 interrupt vectors */ -#define TCC0_CCD_vect_num 19 -#define TCC0_CCD_vect _VECTOR(19) /* Compare or Capture D Interrupt */ - -/* TCC2 interrupt vectors */ -#define TCC2_LCMPD_vect_num 19 -#define TCC2_LCMPD_vect _VECTOR(19) /* Low Byte Compare D Interrupt */ - -/* TCC1 interrupt vectors */ -#define TCC1_OVF_vect_num 20 -#define TCC1_OVF_vect _VECTOR(20) /* Overflow Interrupt */ -#define TCC1_ERR_vect_num 21 -#define TCC1_ERR_vect _VECTOR(21) /* Error Interrupt */ -#define TCC1_CCA_vect_num 22 -#define TCC1_CCA_vect _VECTOR(22) /* Compare or Capture A Interrupt */ -#define TCC1_CCB_vect_num 23 -#define TCC1_CCB_vect _VECTOR(23) /* Compare or Capture B Interrupt */ - -/* SPIC interrupt vectors */ -#define SPIC_INT_vect_num 24 -#define SPIC_INT_vect _VECTOR(24) /* SPI Interrupt */ - -/* USARTC0 interrupt vectors */ -#define USARTC0_RXC_vect_num 25 -#define USARTC0_RXC_vect _VECTOR(25) /* Reception Complete Interrupt */ -#define USARTC0_DRE_vect_num 26 -#define USARTC0_DRE_vect _VECTOR(26) /* Data Register Empty Interrupt */ -#define USARTC0_TXC_vect_num 27 -#define USARTC0_TXC_vect _VECTOR(27) /* Transmission Complete Interrupt */ - -/* USARTC1 interrupt vectors */ -#define USARTC1_RXC_vect_num 28 -#define USARTC1_RXC_vect _VECTOR(28) /* Reception Complete Interrupt */ -#define USARTC1_DRE_vect_num 29 -#define USARTC1_DRE_vect _VECTOR(29) /* Data Register Empty Interrupt */ -#define USARTC1_TXC_vect_num 30 -#define USARTC1_TXC_vect _VECTOR(30) /* Transmission Complete Interrupt */ - -/* AES interrupt vectors */ -#define AES_INT_vect_num 31 -#define AES_INT_vect _VECTOR(31) /* AES Interrupt */ - -/* NVM interrupt vectors */ -#define NVM_EE_vect_num 32 -#define NVM_EE_vect _VECTOR(32) /* EE Interrupt */ -#define NVM_SPM_vect_num 33 -#define NVM_SPM_vect _VECTOR(33) /* SPM Interrupt */ - -/* PORTB interrupt vectors */ -#define PORTB_INT0_vect_num 34 -#define PORTB_INT0_vect _VECTOR(34) /* External Interrupt 0 */ -#define PORTB_INT1_vect_num 35 -#define PORTB_INT1_vect _VECTOR(35) /* External Interrupt 1 */ - -/* PORTE interrupt vectors */ -#define PORTE_INT0_vect_num 43 -#define PORTE_INT0_vect _VECTOR(43) /* External Interrupt 0 */ -#define PORTE_INT1_vect_num 44 -#define PORTE_INT1_vect _VECTOR(44) /* External Interrupt 1 */ - -/* TWIE interrupt vectors */ -#define TWIE_TWIS_vect_num 45 -#define TWIE_TWIS_vect _VECTOR(45) /* TWI Slave Interrupt */ -#define TWIE_TWIM_vect_num 46 -#define TWIE_TWIM_vect _VECTOR(46) /* TWI Master Interrupt */ - -/* TCE0 interrupt vectors */ -#define TCE0_OVF_vect_num 47 -#define TCE0_OVF_vect _VECTOR(47) /* Overflow Interrupt */ -#define TCE0_ERR_vect_num 48 -#define TCE0_ERR_vect _VECTOR(48) /* Error Interrupt */ -#define TCE0_CCA_vect_num 49 -#define TCE0_CCA_vect _VECTOR(49) /* Compare or Capture A Interrupt */ -#define TCE0_CCB_vect_num 50 -#define TCE0_CCB_vect _VECTOR(50) /* Compare or Capture B Interrupt */ -#define TCE0_CCC_vect_num 51 -#define TCE0_CCC_vect _VECTOR(51) /* Compare or Capture C Interrupt */ -#define TCE0_CCD_vect_num 52 -#define TCE0_CCD_vect _VECTOR(52) /* Compare or Capture D Interrupt */ - -/* USARTE0 interrupt vectors */ -#define USARTE0_RXC_vect_num 58 -#define USARTE0_RXC_vect _VECTOR(58) /* Reception Complete Interrupt */ -#define USARTE0_DRE_vect_num 59 -#define USARTE0_DRE_vect _VECTOR(59) /* Data Register Empty Interrupt */ -#define USARTE0_TXC_vect_num 60 -#define USARTE0_TXC_vect _VECTOR(60) /* Transmission Complete Interrupt */ - -/* PORTD interrupt vectors */ -#define PORTD_INT0_vect_num 64 -#define PORTD_INT0_vect _VECTOR(64) /* External Interrupt 0 */ -#define PORTD_INT1_vect_num 65 -#define PORTD_INT1_vect _VECTOR(65) /* External Interrupt 1 */ - -/* PORTA interrupt vectors */ -#define PORTA_INT0_vect_num 66 -#define PORTA_INT0_vect _VECTOR(66) /* External Interrupt 0 */ -#define PORTA_INT1_vect_num 67 -#define PORTA_INT1_vect _VECTOR(67) /* External Interrupt 1 */ - -/* ACA interrupt vectors */ -#define ACA_AC0_vect_num 68 -#define ACA_AC0_vect _VECTOR(68) /* AC0 Interrupt */ -#define ACA_AC1_vect_num 69 -#define ACA_AC1_vect _VECTOR(69) /* AC1 Interrupt */ -#define ACA_ACW_vect_num 70 -#define ACA_ACW_vect _VECTOR(70) /* ACW Window Mode Interrupt */ - -/* ADCA interrupt vectors */ -#define ADCA_CH0_vect_num 71 -#define ADCA_CH0_vect _VECTOR(71) /* Interrupt 0 */ -#define ADCA_CH1_vect_num 72 -#define ADCA_CH1_vect _VECTOR(72) /* Interrupt 1 */ -#define ADCA_CH2_vect_num 73 -#define ADCA_CH2_vect _VECTOR(73) /* Interrupt 2 */ -#define ADCA_CH3_vect_num 74 -#define ADCA_CH3_vect _VECTOR(74) /* Interrupt 3 */ - -/* TCD0 interrupt vectors */ -#define TCD0_OVF_vect_num 77 -#define TCD0_OVF_vect _VECTOR(77) /* Overflow Interrupt */ - -/* TCD2 interrupt vectors */ -#define TCD2_LUNF_vect_num 77 -#define TCD2_LUNF_vect _VECTOR(77) /* Low Byte Underflow Interrupt */ - -/* TCD0 interrupt vectors */ -#define TCD0_ERR_vect_num 78 -#define TCD0_ERR_vect _VECTOR(78) /* Error Interrupt */ - -/* TCD2 interrupt vectors */ -#define TCD2_HUNF_vect_num 78 -#define TCD2_HUNF_vect _VECTOR(78) /* High Byte Underflow Interrupt */ - -/* TCD0 interrupt vectors */ -#define TCD0_CCA_vect_num 79 -#define TCD0_CCA_vect _VECTOR(79) /* Compare or Capture A Interrupt */ - -/* TCD2 interrupt vectors */ -#define TCD2_LCMPA_vect_num 79 -#define TCD2_LCMPA_vect _VECTOR(79) /* Low Byte Compare A Interrupt */ - -/* TCD0 interrupt vectors */ -#define TCD0_CCB_vect_num 80 -#define TCD0_CCB_vect _VECTOR(80) /* Compare or Capture B Interrupt */ - -/* TCD2 interrupt vectors */ -#define TCD2_LCMPB_vect_num 80 -#define TCD2_LCMPB_vect _VECTOR(80) /* Low Byte Compare B Interrupt */ - -/* TCD0 interrupt vectors */ -#define TCD0_CCC_vect_num 81 -#define TCD0_CCC_vect _VECTOR(81) /* Compare or Capture C Interrupt */ - -/* TCD2 interrupt vectors */ -#define TCD2_LCMPC_vect_num 81 -#define TCD2_LCMPC_vect _VECTOR(81) /* Low Byte Compare C Interrupt */ - -/* TCD0 interrupt vectors */ -#define TCD0_CCD_vect_num 82 -#define TCD0_CCD_vect _VECTOR(82) /* Compare or Capture D Interrupt */ - -/* TCD2 interrupt vectors */ -#define TCD2_LCMPD_vect_num 82 -#define TCD2_LCMPD_vect _VECTOR(82) /* Low Byte Compare D Interrupt */ - -/* TCD1 interrupt vectors */ -#define TCD1_OVF_vect_num 83 -#define TCD1_OVF_vect _VECTOR(83) /* Overflow Interrupt */ -#define TCD1_ERR_vect_num 84 -#define TCD1_ERR_vect _VECTOR(84) /* Error Interrupt */ -#define TCD1_CCA_vect_num 85 -#define TCD1_CCA_vect _VECTOR(85) /* Compare or Capture A Interrupt */ -#define TCD1_CCB_vect_num 86 -#define TCD1_CCB_vect _VECTOR(86) /* Compare or Capture B Interrupt */ - -/* SPID interrupt vectors */ -#define SPID_INT_vect_num 87 -#define SPID_INT_vect _VECTOR(87) /* SPI Interrupt */ - -/* USARTD0 interrupt vectors */ -#define USARTD0_RXC_vect_num 88 -#define USARTD0_RXC_vect _VECTOR(88) /* Reception Complete Interrupt */ -#define USARTD0_DRE_vect_num 89 -#define USARTD0_DRE_vect _VECTOR(89) /* Data Register Empty Interrupt */ -#define USARTD0_TXC_vect_num 90 -#define USARTD0_TXC_vect _VECTOR(90) /* Transmission Complete Interrupt */ - -/* USARTD1 interrupt vectors */ -#define USARTD1_RXC_vect_num 91 -#define USARTD1_RXC_vect _VECTOR(91) /* Reception Complete Interrupt */ -#define USARTD1_DRE_vect_num 92 -#define USARTD1_DRE_vect _VECTOR(92) /* Data Register Empty Interrupt */ -#define USARTD1_TXC_vect_num 93 -#define USARTD1_TXC_vect _VECTOR(93) /* Transmission Complete Interrupt */ - -/* USB interrupt vectors */ -#define USB_BUSEVENT_vect_num 125 -#define USB_BUSEVENT_vect _VECTOR(125) /* SOF, suspend, resume, reset bus event interrupts, crc, underflow, overflow and stall error interrupts */ -#define USB_TRNCOMPL_vect_num 126 -#define USB_TRNCOMPL_vect _VECTOR(126) /* Transaction complete interrupt */ - -#define _VECTOR_SIZE 4 /* Size of individual vector. */ -#define _VECTORS_SIZE (127 * _VECTOR_SIZE) - - -/* ========== Constants ========== */ - -#define PROGMEM_START (0x0000) -#define PROGMEM_SIZE (20480) -#define PROGMEM_END (PROGMEM_START + PROGMEM_SIZE - 1) - -#define APP_SECTION_START (0x0000) -#define APP_SECTION_SIZE (16384) -#define APP_SECTION_PAGE_SIZE (256) -#define APP_SECTION_END (APP_SECTION_START + APP_SECTION_SIZE - 1) - -#define APPTABLE_SECTION_START (0x3000) -#define APPTABLE_SECTION_SIZE (4096) -#define APPTABLE_SECTION_PAGE_SIZE (256) -#define APPTABLE_SECTION_END (APPTABLE_SECTION_START + APPTABLE_SECTION_SIZE - 1) - -#define BOOT_SECTION_START (0x4000) -#define BOOT_SECTION_SIZE (4096) -#define BOOT_SECTION_PAGE_SIZE (256) -#define BOOT_SECTION_END (BOOT_SECTION_START + BOOT_SECTION_SIZE - 1) - -#define DATAMEM_START (0x0000) -#define DATAMEM_SIZE (10240) -#define DATAMEM_END (DATAMEM_START + DATAMEM_SIZE - 1) - -#define IO_START (0x0000) -#define IO_SIZE (4096) -#define IO_PAGE_SIZE (0) -#define IO_END (IO_START + IO_SIZE - 1) - -#define MAPPED_EEPROM_START (0x1000) -#define MAPPED_EEPROM_SIZE (1024) -#define MAPPED_EEPROM_PAGE_SIZE (0) -#define MAPPED_EEPROM_END (MAPPED_EEPROM_START + MAPPED_EEPROM_SIZE - 1) - -#define INTERNAL_SRAM_START (0x2000) -#define INTERNAL_SRAM_SIZE (2048) -#define INTERNAL_SRAM_PAGE_SIZE (0) -#define INTERNAL_SRAM_END (INTERNAL_SRAM_START + INTERNAL_SRAM_SIZE - 1) - -#define EEPROM_START (0x0000) -#define EEPROM_SIZE (1024) -#define EEPROM_PAGE_SIZE (32) -#define EEPROM_END (EEPROM_START + EEPROM_SIZE - 1) - -#define SIGNATURES_START (0x0000) -#define SIGNATURES_SIZE (3) -#define SIGNATURES_PAGE_SIZE (0) -#define SIGNATURES_END (SIGNATURES_START + SIGNATURES_SIZE - 1) - -#define FUSES_START (0x0000) -#define FUSES_SIZE (6) -#define FUSES_PAGE_SIZE (0) -#define FUSES_END (FUSES_START + FUSES_SIZE - 1) - -#define LOCKBITS_START (0x0000) -#define LOCKBITS_SIZE (1) -#define LOCKBITS_PAGE_SIZE (0) -#define LOCKBITS_END (LOCKBITS_START + LOCKBITS_SIZE - 1) - -#define USER_SIGNATURES_START (0x0000) -#define USER_SIGNATURES_SIZE (256) -#define USER_SIGNATURES_PAGE_SIZE (256) -#define USER_SIGNATURES_END (USER_SIGNATURES_START + USER_SIGNATURES_SIZE - 1) - -#define PROD_SIGNATURES_START (0x0000) -#define PROD_SIGNATURES_SIZE (52) -#define PROD_SIGNATURES_PAGE_SIZE (256) -#define PROD_SIGNATURES_END (PROD_SIGNATURES_START + PROD_SIGNATURES_SIZE - 1) - -#define FLASHSTART PROGMEM_START -#define FLASHEND PROGMEM_END -#define SPM_PAGESIZE 256 -#define RAMSTART INTERNAL_SRAM_START -#define RAMSIZE INTERNAL_SRAM_SIZE -#define RAMEND INTERNAL_SRAM_END -#define E2END EEPROM_END -#define E2PAGESIZE EEPROM_PAGE_SIZE - - -/* ========== Fuses ========== */ -#define FUSE_MEMORY_SIZE 6 - -/* Fuse Byte 0 Reserved */ - -/* Fuse Byte 1 */ -#define FUSE_WDP0 (unsigned char)~_BV(0) /* Watchdog Timeout Period Bit 0 */ -#define FUSE_WDP1 (unsigned char)~_BV(1) /* Watchdog Timeout Period Bit 1 */ -#define FUSE_WDP2 (unsigned char)~_BV(2) /* Watchdog Timeout Period Bit 2 */ -#define FUSE_WDP3 (unsigned char)~_BV(3) /* Watchdog Timeout Period Bit 3 */ -#define FUSE_WDWP0 (unsigned char)~_BV(4) /* Watchdog Window Timeout Period Bit 0 */ -#define FUSE_WDWP1 (unsigned char)~_BV(5) /* Watchdog Window Timeout Period Bit 1 */ -#define FUSE_WDWP2 (unsigned char)~_BV(6) /* Watchdog Window Timeout Period Bit 2 */ -#define FUSE_WDWP3 (unsigned char)~_BV(7) /* Watchdog Window Timeout Period Bit 3 */ -#define FUSE1_DEFAULT (0xFF) - -/* Fuse Byte 2 */ -#define FUSE_BODPD0 (unsigned char)~_BV(0) /* BOD Operation in Power-Down Mode Bit 0 */ -#define FUSE_BODPD1 (unsigned char)~_BV(1) /* BOD Operation in Power-Down Mode Bit 1 */ -#define FUSE_TOSCSEL (unsigned char)~_BV(5) /* Timer Oscillator pin location */ -#define FUSE_BOOTRST (unsigned char)~_BV(6) /* Boot Loader Section Reset Vector */ -#define FUSE2_DEFAULT (0xFF) - -/* Fuse Byte 3 Reserved */ - -/* Fuse Byte 4 */ -#define FUSE_WDLOCK (unsigned char)~_BV(1) /* Watchdog Timer Lock */ -#define FUSE_SUT0 (unsigned char)~_BV(2) /* Start-up Time Bit 0 */ -#define FUSE_SUT1 (unsigned char)~_BV(3) /* Start-up Time Bit 1 */ -#define FUSE_RSTDISBL (unsigned char)~_BV(4) /* External Reset Disable */ -#define FUSE4_DEFAULT (0xFF) - -/* Fuse Byte 5 */ -#define FUSE_BODLVL0 (unsigned char)~_BV(0) /* Brownout Detection Voltage Level Bit 0 */ -#define FUSE_BODLVL1 (unsigned char)~_BV(1) /* Brownout Detection Voltage Level Bit 1 */ -#define FUSE_BODLVL2 (unsigned char)~_BV(2) /* Brownout Detection Voltage Level Bit 2 */ -#define FUSE_EESAVE (unsigned char)~_BV(3) /* Preserve EEPROM Through Chip Erase */ -#define FUSE_BODACT0 (unsigned char)~_BV(4) /* BOD Operation in Active Mode Bit 0 */ -#define FUSE_BODACT1 (unsigned char)~_BV(5) /* BOD Operation in Active Mode Bit 1 */ -#define FUSE5_DEFAULT (0xFF) - -/* ========== Lock Bits ========== */ -#define __LOCK_BITS_EXIST -#define __BOOT_LOCK_APPLICATION_TABLE_BITS_EXIST -#define __BOOT_LOCK_APPLICATION_BITS_EXIST -#define __BOOT_LOCK_BOOT_BITS_EXIST - -/* ========== Signature ========== */ -#define SIGNATURE_0 0x1E -#define SIGNATURE_1 0x94 -#define SIGNATURE_2 0x41 - -/* ========== Power Reduction Condition Definitions ========== */ - -/* PR.PRGEN */ -#define __AVR_HAVE_PRGEN (PR_USB_bm|PR_AES_bm|PR_EBI_bm|PR_RTC_bm|PR_EVSYS_bm|PR_DMA_bm) -#define __AVR_HAVE_PRGEN_USB -#define __AVR_HAVE_PRGEN_AES -#define __AVR_HAVE_PRGEN_EBI -#define __AVR_HAVE_PRGEN_RTC -#define __AVR_HAVE_PRGEN_EVSYS -#define __AVR_HAVE_PRGEN_DMA - -/* PR.PRPA */ -#define __AVR_HAVE_PRPA (PR_DAC_bm|PR_ADC_bm|PR_AC_bm) -#define __AVR_HAVE_PRPA_DAC -#define __AVR_HAVE_PRPA_ADC -#define __AVR_HAVE_PRPA_AC - -/* PR.PRPB */ -#define __AVR_HAVE_PRPB (PR_DAC_bm|PR_ADC_bm|PR_AC_bm) -#define __AVR_HAVE_PRPB_DAC -#define __AVR_HAVE_PRPB_ADC -#define __AVR_HAVE_PRPB_AC - -/* PR.PRPC */ -#define __AVR_HAVE_PRPC (PR_TWI_bm|PR_USART1_bm|PR_USART0_bm|PR_SPI_bm|PR_HIRES_bm|PR_TC1_bm|PR_TC0_bm) -#define __AVR_HAVE_PRPC_TWI -#define __AVR_HAVE_PRPC_USART1 -#define __AVR_HAVE_PRPC_USART0 -#define __AVR_HAVE_PRPC_SPI -#define __AVR_HAVE_PRPC_HIRES -#define __AVR_HAVE_PRPC_TC1 -#define __AVR_HAVE_PRPC_TC0 - -/* PR.PRPD */ -#define __AVR_HAVE_PRPD (PR_TWI_bm|PR_USART1_bm|PR_USART0_bm|PR_SPI_bm|PR_HIRES_bm|PR_TC1_bm|PR_TC0_bm) -#define __AVR_HAVE_PRPD_TWI -#define __AVR_HAVE_PRPD_USART1 -#define __AVR_HAVE_PRPD_USART0 -#define __AVR_HAVE_PRPD_SPI -#define __AVR_HAVE_PRPD_HIRES -#define __AVR_HAVE_PRPD_TC1 -#define __AVR_HAVE_PRPD_TC0 - -/* PR.PRPE */ -#define __AVR_HAVE_PRPE (PR_TWI_bm|PR_USART1_bm|PR_USART0_bm|PR_SPI_bm|PR_HIRES_bm|PR_TC1_bm|PR_TC0_bm) -#define __AVR_HAVE_PRPE_TWI -#define __AVR_HAVE_PRPE_USART1 -#define __AVR_HAVE_PRPE_USART0 -#define __AVR_HAVE_PRPE_SPI -#define __AVR_HAVE_PRPE_HIRES -#define __AVR_HAVE_PRPE_TC1 -#define __AVR_HAVE_PRPE_TC0 - -/* PR.PRPF */ -#define __AVR_HAVE_PRPF (PR_TWI_bm|PR_USART1_bm|PR_USART0_bm|PR_SPI_bm|PR_HIRES_bm|PR_TC1_bm|PR_TC0_bm) -#define __AVR_HAVE_PRPF_TWI -#define __AVR_HAVE_PRPF_USART1 -#define __AVR_HAVE_PRPF_USART0 -#define __AVR_HAVE_PRPF_SPI -#define __AVR_HAVE_PRPF_HIRES -#define __AVR_HAVE_PRPF_TC1 -#define __AVR_HAVE_PRPF_TC0 - - -#endif /* #ifdef _AVR_ATXMEGA16A4U_H_INCLUDED */ - diff --git a/arduino/hardware/tools/avr/avr/include/avr/iox16c4.h b/arduino/hardware/tools/avr/avr/include/avr/iox16c4.h deleted file mode 100644 index 32043b9..0000000 --- a/arduino/hardware/tools/avr/avr/include/avr/iox16c4.h +++ /dev/null @@ -1,6078 +0,0 @@ -/***************************************************************************** - * - * Copyright (C) 2015 Atmel Corporation - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * - * * Neither the name of the copyright holders nor the names of - * contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - ****************************************************************************/ - - -#ifndef _AVR_IO_H_ -# error "Include instead of this file." -#endif - -#ifndef _AVR_IOXXX_H_ -# define _AVR_IOXXX_H_ "iox16c4.h" -#else -# error "Attempt to include more than one file." -#endif - -#ifndef _AVR_ATXMEGA16C4_H_INCLUDED -#define _AVR_ATXMEGA16C4_H_INCLUDED - -/* Ungrouped common registers */ -#define GPIOR0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ -#define GPIOR1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ -#define GPIOR2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ -#define GPIOR3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ - -/* Deprecated */ -#define GPIO0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ -#define GPIO1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ -#define GPIO2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ -#define GPIO3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ - -#define CCP _SFR_MEM8(0x0034) /* Configuration Change Protection */ -#define RAMPD _SFR_MEM8(0x0038) /* Ramp D */ -#define RAMPX _SFR_MEM8(0x0039) /* Ramp X */ -#define RAMPY _SFR_MEM8(0x003A) /* Ramp Y */ -#define RAMPZ _SFR_MEM8(0x003B) /* Ramp Z */ -#define EIND _SFR_MEM8(0x003C) /* Extended Indirect Jump */ -#define SPL _SFR_MEM8(0x003D) /* Stack Pointer Low */ -#define SPH _SFR_MEM8(0x003E) /* Stack Pointer High */ -#define SREG _SFR_MEM8(0x003F) /* Status Register */ - -/* C Language Only */ -#if !defined (__ASSEMBLER__) - -#include - -typedef volatile uint8_t register8_t; -typedef volatile uint16_t register16_t; -typedef volatile uint32_t register32_t; - - -#ifdef _WORDREGISTER -#undef _WORDREGISTER -#endif -#define _WORDREGISTER(regname) \ - __extension__ union \ - { \ - register16_t regname; \ - struct \ - { \ - register8_t regname ## L; \ - register8_t regname ## H; \ - }; \ - } - -#ifdef _DWORDREGISTER -#undef _DWORDREGISTER -#endif -#define _DWORDREGISTER(regname) \ - __extension__ union \ - { \ - register32_t regname; \ - struct \ - { \ - register8_t regname ## 0; \ - register8_t regname ## 1; \ - register8_t regname ## 2; \ - register8_t regname ## 3; \ - }; \ - } - - -/* -========================================================================== -IO Module Structures -========================================================================== -*/ - - -/* --------------------------------------------------------------------------- -VPORT - Virtual Ports --------------------------------------------------------------------------- -*/ - -/* Virtual Port */ -typedef struct VPORT_struct -{ - register8_t DIR; /* I/O Port Data Direction */ - register8_t OUT; /* I/O Port Output */ - register8_t IN; /* I/O Port Input */ - register8_t INTFLAGS; /* Interrupt Flag Register */ -} VPORT_t; - - -/* --------------------------------------------------------------------------- -XOCD - On-Chip Debug System --------------------------------------------------------------------------- -*/ - -/* On-Chip Debug System */ -typedef struct OCD_struct -{ - register8_t OCDR0; /* OCD Register 0 */ - register8_t OCDR1; /* OCD Register 1 */ -} OCD_t; - - -/* --------------------------------------------------------------------------- -CPU - CPU --------------------------------------------------------------------------- -*/ - -/* CCP signatures */ -typedef enum CCP_enum -{ - CCP_SPM_gc = (0x9D<<0), /* SPM Instruction Protection */ - CCP_IOREG_gc = (0xD8<<0), /* IO Register Protection */ -} CCP_t; - - -/* --------------------------------------------------------------------------- -CLK - Clock System --------------------------------------------------------------------------- -*/ - -/* Clock System */ -typedef struct CLK_struct -{ - register8_t CTRL; /* Control Register */ - register8_t PSCTRL; /* Prescaler Control Register */ - register8_t LOCK; /* Lock register */ - register8_t RTCCTRL; /* RTC Control Register */ - register8_t USBCTRL; /* USB Control Register */ -} CLK_t; - - -/* Power Reduction */ -typedef struct PR_struct -{ - register8_t PRGEN; /* General Power Reduction */ - register8_t PRPA; /* Power Reduction Port A */ - register8_t reserved_0x02; - register8_t PRPC; /* Power Reduction Port C */ - register8_t PRPD; /* Power Reduction Port D */ - register8_t PRPE; /* Power Reduction Port E */ - register8_t PRPF; /* Power Reduction Port F */ -} PR_t; - -/* System Clock Selection */ -typedef enum CLK_SCLKSEL_enum -{ - CLK_SCLKSEL_RC2M_gc = (0x00<<0), /* Internal 2 MHz RC Oscillator */ - CLK_SCLKSEL_RC32M_gc = (0x01<<0), /* Internal 32 MHz RC Oscillator */ - CLK_SCLKSEL_RC32K_gc = (0x02<<0), /* Internal 32.768 kHz RC Oscillator */ - CLK_SCLKSEL_XOSC_gc = (0x03<<0), /* External Crystal Oscillator or Clock */ - CLK_SCLKSEL_PLL_gc = (0x04<<0), /* Phase Locked Loop */ -} CLK_SCLKSEL_t; - -/* Prescaler A Division Factor */ -typedef enum CLK_PSADIV_enum -{ - CLK_PSADIV_1_gc = (0x00<<2), /* Divide by 1 */ - CLK_PSADIV_2_gc = (0x01<<2), /* Divide by 2 */ - CLK_PSADIV_4_gc = (0x03<<2), /* Divide by 4 */ - CLK_PSADIV_8_gc = (0x05<<2), /* Divide by 8 */ - CLK_PSADIV_16_gc = (0x07<<2), /* Divide by 16 */ - CLK_PSADIV_32_gc = (0x09<<2), /* Divide by 32 */ - CLK_PSADIV_64_gc = (0x0B<<2), /* Divide by 64 */ - CLK_PSADIV_128_gc = (0x0D<<2), /* Divide by 128 */ - CLK_PSADIV_256_gc = (0x0F<<2), /* Divide by 256 */ - CLK_PSADIV_512_gc = (0x11<<2), /* Divide by 512 */ -} CLK_PSADIV_t; - -/* Prescaler B and C Division Factor */ -typedef enum CLK_PSBCDIV_enum -{ - CLK_PSBCDIV_1_1_gc = (0x00<<0), /* Divide B by 1 and C by 1 */ - CLK_PSBCDIV_1_2_gc = (0x01<<0), /* Divide B by 1 and C by 2 */ - CLK_PSBCDIV_4_1_gc = (0x02<<0), /* Divide B by 4 and C by 1 */ - CLK_PSBCDIV_2_2_gc = (0x03<<0), /* Divide B by 2 and C by 2 */ -} CLK_PSBCDIV_t; - -/* RTC Clock Source */ -typedef enum CLK_RTCSRC_enum -{ - CLK_RTCSRC_ULP_gc = (0x00<<1), /* 1.024 kHz from internal 32kHz ULP */ - CLK_RTCSRC_TOSC_gc = (0x01<<1), /* 1.024 kHz from 32.768 kHz crystal oscillator on TOSC */ - CLK_RTCSRC_RCOSC_gc = (0x02<<1), /* 1.024 kHz from internal 32.768 kHz RC oscillator */ - CLK_RTCSRC_TOSC32_gc = (0x05<<1), /* 32.768 kHz from 32.768 kHz crystal oscillator on TOSC */ - CLK_RTCSRC_RCOSC32_gc = (0x06<<1), /* 32.768 kHz from internal 32.768 kHz RC oscillator */ - CLK_RTCSRC_EXTCLK_gc = (0x07<<1), /* External Clock from TOSC1 */ -} CLK_RTCSRC_t; - -/* USB Prescaler Division Factor */ -typedef enum CLK_USBPSDIV_enum -{ - CLK_USBPSDIV_1_gc = (0x00<<3), /* Divide by 1 */ - CLK_USBPSDIV_2_gc = (0x01<<3), /* Divide by 2 */ - CLK_USBPSDIV_4_gc = (0x02<<3), /* Divide by 4 */ - CLK_USBPSDIV_8_gc = (0x03<<3), /* Divide by 8 */ - CLK_USBPSDIV_16_gc = (0x04<<3), /* Divide by 16 */ - CLK_USBPSDIV_32_gc = (0x05<<3), /* Divide by 32 */ -} CLK_USBPSDIV_t; - -/* USB Clock Source */ -typedef enum CLK_USBSRC_enum -{ - CLK_USBSRC_PLL_gc = (0x00<<1), /* PLL */ - CLK_USBSRC_RC32M_gc = (0x01<<1), /* Internal 32 MHz RC Oscillator */ -} CLK_USBSRC_t; - - -/* --------------------------------------------------------------------------- -SLEEP - Sleep Controller --------------------------------------------------------------------------- -*/ - -/* Sleep Controller */ -typedef struct SLEEP_struct -{ - register8_t CTRL; /* Control Register */ -} SLEEP_t; - -/* Sleep Mode */ -typedef enum SLEEP_SMODE_enum -{ - SLEEP_SMODE_IDLE_gc = (0x00<<1), /* Idle mode */ - SLEEP_SMODE_PDOWN_gc = (0x02<<1), /* Power-down Mode */ - SLEEP_SMODE_PSAVE_gc = (0x03<<1), /* Power-save Mode */ - SLEEP_SMODE_STDBY_gc = (0x06<<1), /* Standby Mode */ - SLEEP_SMODE_ESTDBY_gc = (0x07<<1), /* Extended Standby Mode */ -} SLEEP_SMODE_t; - - - -#define SLEEP_MODE_IDLE (0x00<<1) -#define SLEEP_MODE_PWR_DOWN (0x02<<1) -#define SLEEP_MODE_PWR_SAVE (0x03<<1) -#define SLEEP_MODE_STANDBY (0x06<<1) -#define SLEEP_MODE_EXT_STANDBY (0x07<<1) -/* --------------------------------------------------------------------------- -OSC - Oscillator --------------------------------------------------------------------------- -*/ - -/* Oscillator */ -typedef struct OSC_struct -{ - register8_t CTRL; /* Control Register */ - register8_t STATUS; /* Status Register */ - register8_t XOSCCTRL; /* External Oscillator Control Register */ - register8_t XOSCFAIL; /* Oscillator Failure Detection Register */ - register8_t RC32KCAL; /* 32.768 kHz Internal Oscillator Calibration Register */ - register8_t PLLCTRL; /* PLL Control Register */ - register8_t DFLLCTRL; /* DFLL Control Register */ -} OSC_t; - -/* Oscillator Frequency Range */ -typedef enum OSC_FRQRANGE_enum -{ - OSC_FRQRANGE_04TO2_gc = (0x00<<6), /* 0.4 - 2 MHz */ - OSC_FRQRANGE_2TO9_gc = (0x01<<6), /* 2 - 9 MHz */ - OSC_FRQRANGE_9TO12_gc = (0x02<<6), /* 9 - 12 MHz */ - OSC_FRQRANGE_12TO16_gc = (0x03<<6), /* 12 - 16 MHz */ -} OSC_FRQRANGE_t; - -/* External Oscillator Selection and Startup Time */ -typedef enum OSC_XOSCSEL_enum -{ - OSC_XOSCSEL_EXTCLK_gc = (0x00<<0), /* External Clock - 6 CLK */ - OSC_XOSCSEL_32KHz_gc = (0x02<<0), /* 32.768 kHz TOSC - 32K CLK */ - OSC_XOSCSEL_XTAL_256CLK_gc = (0x03<<0), /* 0.4-16 MHz XTAL - 256 CLK */ - OSC_XOSCSEL_XTAL_1KCLK_gc = (0x07<<0), /* 0.4-16 MHz XTAL - 1K CLK */ - OSC_XOSCSEL_XTAL_16KCLK_gc = (0x0B<<0), /* 0.4-16 MHz XTAL - 16K CLK */ -} OSC_XOSCSEL_t; - -/* PLL Clock Source */ -typedef enum OSC_PLLSRC_enum -{ - OSC_PLLSRC_RC2M_gc = (0x00<<6), /* Internal 2 MHz RC Oscillator */ - OSC_PLLSRC_RC32M_gc = (0x02<<6), /* Internal 32 MHz RC Oscillator */ - OSC_PLLSRC_XOSC_gc = (0x03<<6), /* External Oscillator */ -} OSC_PLLSRC_t; - -/* 2 MHz DFLL Calibration Reference */ -typedef enum OSC_RC2MCREF_enum -{ - OSC_RC2MCREF_RC32K_gc = (0x00<<0), /* Internal 32.768 kHz RC Oscillator */ - OSC_RC2MCREF_XOSC32K_gc = (0x01<<0), /* External 32.768 kHz Crystal Oscillator */ -} OSC_RC2MCREF_t; - -/* 32 MHz DFLL Calibration Reference */ -typedef enum OSC_RC32MCREF_enum -{ - OSC_RC32MCREF_RC32K_gc = (0x00<<1), /* Internal 32.768 kHz RC Oscillator */ - OSC_RC32MCREF_XOSC32K_gc = (0x01<<1), /* External 32.768 kHz Crystal Oscillator */ - OSC_RC32MCREF_USBSOF_gc = (0x02<<1), /* USB Start of Frame */ -} OSC_RC32MCREF_t; - - -/* --------------------------------------------------------------------------- -DFLL - DFLL --------------------------------------------------------------------------- -*/ - -/* DFLL */ -typedef struct DFLL_struct -{ - register8_t CTRL; /* Control Register */ - register8_t reserved_0x01; - register8_t CALA; /* Calibration Register A */ - register8_t CALB; /* Calibration Register B */ - register8_t COMP0; /* Oscillator Compare Register 0 */ - register8_t COMP1; /* Oscillator Compare Register 1 */ - register8_t COMP2; /* Oscillator Compare Register 2 */ - register8_t reserved_0x07; -} DFLL_t; - - -/* --------------------------------------------------------------------------- -RST - Reset --------------------------------------------------------------------------- -*/ - -/* Reset */ -typedef struct RST_struct -{ - register8_t STATUS; /* Status Register */ - register8_t CTRL; /* Control Register */ -} RST_t; - - -/* --------------------------------------------------------------------------- -WDT - Watch-Dog Timer --------------------------------------------------------------------------- -*/ - -/* Watch-Dog Timer */ -typedef struct WDT_struct -{ - register8_t CTRL; /* Control */ - register8_t WINCTRL; /* Windowed Mode Control */ - register8_t STATUS; /* Status */ -} WDT_t; - -/* Period setting */ -typedef enum WDT_PER_enum -{ - WDT_PER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ - WDT_PER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ - WDT_PER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ - WDT_PER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ - WDT_PER_128CLK_gc = (0x04<<2), /* 128 cycles (0.128s @ 3.3V) */ - WDT_PER_256CLK_gc = (0x05<<2), /* 256 cycles (0.256s @ 3.3V) */ - WDT_PER_512CLK_gc = (0x06<<2), /* 512 cycles (0.512s @ 3.3V) */ - WDT_PER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ - WDT_PER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ - WDT_PER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ - WDT_PER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ -} WDT_PER_t; - -/* Closed window period */ -typedef enum WDT_WPER_enum -{ - WDT_WPER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ - WDT_WPER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ - WDT_WPER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ - WDT_WPER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ - WDT_WPER_128CLK_gc = (0x04<<2), /* 128 cycles (0.128s @ 3.3V) */ - WDT_WPER_256CLK_gc = (0x05<<2), /* 256 cycles (0.256s @ 3.3V) */ - WDT_WPER_512CLK_gc = (0x06<<2), /* 512 cycles (0.512s @ 3.3V) */ - WDT_WPER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ - WDT_WPER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ - WDT_WPER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ - WDT_WPER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ -} WDT_WPER_t; - - -/* --------------------------------------------------------------------------- -MCU - MCU Control --------------------------------------------------------------------------- -*/ - -/* MCU Control */ -typedef struct MCU_struct -{ - register8_t DEVID0; /* Device ID byte 0 */ - register8_t DEVID1; /* Device ID byte 1 */ - register8_t DEVID2; /* Device ID byte 2 */ - register8_t REVID; /* Revision ID */ - register8_t reserved_0x04; - register8_t reserved_0x05; - register8_t reserved_0x06; - register8_t ANAINIT; /* Analog Startup Delay */ - register8_t EVSYSLOCK; /* Event System Lock */ - register8_t AWEXLOCK; /* AWEX Lock */ - register8_t reserved_0x0A; - register8_t reserved_0x0B; -} MCU_t; - - -/* --------------------------------------------------------------------------- -PMIC - Programmable Multi-level Interrupt Controller --------------------------------------------------------------------------- -*/ - -/* Programmable Multi-level Interrupt Controller */ -typedef struct PMIC_struct -{ - register8_t STATUS; /* Status Register */ - register8_t INTPRI; /* Interrupt Priority */ - register8_t CTRL; /* Control Register */ - register8_t reserved_0x03; - register8_t reserved_0x04; - register8_t reserved_0x05; - register8_t reserved_0x06; - register8_t reserved_0x07; - register8_t reserved_0x08; - register8_t reserved_0x09; - register8_t reserved_0x0A; - register8_t reserved_0x0B; - register8_t reserved_0x0C; - register8_t reserved_0x0D; - register8_t reserved_0x0E; - register8_t reserved_0x0F; -} PMIC_t; - - -/* --------------------------------------------------------------------------- -PORTCFG - Port Configuration --------------------------------------------------------------------------- -*/ - -/* I/O port Configuration */ -typedef struct PORTCFG_struct -{ - register8_t MPCMASK; /* Multi-pin Configuration Mask */ - register8_t reserved_0x01; - register8_t VPCTRLA; /* Virtual Port Control Register A */ - register8_t VPCTRLB; /* Virtual Port Control Register B */ - register8_t CLKEVOUT; /* Clock and Event Out Register */ - register8_t reserved_0x05; - register8_t EVOUTSEL; /* Event Output Select */ -} PORTCFG_t; - -/* Virtual Port Mapping */ -typedef enum PORTCFG_VP02MAP_enum -{ - PORTCFG_VP02MAP_PORTA_gc = (0x00<<0), /* Mapped To PORTA */ - PORTCFG_VP02MAP_PORTB_gc = (0x01<<0), /* Mapped To PORTB */ - PORTCFG_VP02MAP_PORTC_gc = (0x02<<0), /* Mapped To PORTC */ - PORTCFG_VP02MAP_PORTD_gc = (0x03<<0), /* Mapped To PORTD */ - PORTCFG_VP02MAP_PORTE_gc = (0x04<<0), /* Mapped To PORTE */ - PORTCFG_VP02MAP_PORTF_gc = (0x05<<0), /* Mapped To PORTF */ - PORTCFG_VP02MAP_PORTG_gc = (0x06<<0), /* Mapped To PORTG */ - PORTCFG_VP02MAP_PORTH_gc = (0x07<<0), /* Mapped To PORTH */ - PORTCFG_VP02MAP_PORTJ_gc = (0x08<<0), /* Mapped To PORTJ */ - PORTCFG_VP02MAP_PORTK_gc = (0x09<<0), /* Mapped To PORTK */ - PORTCFG_VP02MAP_PORTL_gc = (0x0A<<0), /* Mapped To PORTL */ - PORTCFG_VP02MAP_PORTM_gc = (0x0B<<0), /* Mapped To PORTM */ - PORTCFG_VP02MAP_PORTN_gc = (0x0C<<0), /* Mapped To PORTN */ - PORTCFG_VP02MAP_PORTP_gc = (0x0D<<0), /* Mapped To PORTP */ - PORTCFG_VP02MAP_PORTQ_gc = (0x0E<<0), /* Mapped To PORTQ */ - PORTCFG_VP02MAP_PORTR_gc = (0x0F<<0), /* Mapped To PORTR */ -} PORTCFG_VP02MAP_t; - -/* Virtual Port Mapping */ -typedef enum PORTCFG_VP13MAP_enum -{ - PORTCFG_VP13MAP_PORTA_gc = (0x00<<4), /* Mapped To PORTA */ - PORTCFG_VP13MAP_PORTB_gc = (0x01<<4), /* Mapped To PORTB */ - PORTCFG_VP13MAP_PORTC_gc = (0x02<<4), /* Mapped To PORTC */ - PORTCFG_VP13MAP_PORTD_gc = (0x03<<4), /* Mapped To PORTD */ - PORTCFG_VP13MAP_PORTE_gc = (0x04<<4), /* Mapped To PORTE */ - PORTCFG_VP13MAP_PORTF_gc = (0x05<<4), /* Mapped To PORTF */ - PORTCFG_VP13MAP_PORTG_gc = (0x06<<4), /* Mapped To PORTG */ - PORTCFG_VP13MAP_PORTH_gc = (0x07<<4), /* Mapped To PORTH */ - PORTCFG_VP13MAP_PORTJ_gc = (0x08<<4), /* Mapped To PORTJ */ - PORTCFG_VP13MAP_PORTK_gc = (0x09<<4), /* Mapped To PORTK */ - PORTCFG_VP13MAP_PORTL_gc = (0x0A<<4), /* Mapped To PORTL */ - PORTCFG_VP13MAP_PORTM_gc = (0x0B<<4), /* Mapped To PORTM */ - PORTCFG_VP13MAP_PORTN_gc = (0x0C<<4), /* Mapped To PORTN */ - PORTCFG_VP13MAP_PORTP_gc = (0x0D<<4), /* Mapped To PORTP */ - PORTCFG_VP13MAP_PORTQ_gc = (0x0E<<4), /* Mapped To PORTQ */ - PORTCFG_VP13MAP_PORTR_gc = (0x0F<<4), /* Mapped To PORTR */ -} PORTCFG_VP13MAP_t; - -/* System Clock Output Port */ -typedef enum PORTCFG_CLKOUT_enum -{ - PORTCFG_CLKOUT_OFF_gc = (0x00<<0), /* System Clock Output Disabled */ - PORTCFG_CLKOUT_PC7_gc = (0x01<<0), /* System Clock Output on Port C pin 7 */ - PORTCFG_CLKOUT_PD7_gc = (0x02<<0), /* System Clock Output on Port D pin 7 */ - PORTCFG_CLKOUT_PE7_gc = (0x03<<0), /* System Clock Output on Port E pin 7 */ -} PORTCFG_CLKOUT_t; - -/* Peripheral Clock Output Select */ -typedef enum PORTCFG_CLKOUTSEL_enum -{ - PORTCFG_CLKOUTSEL_CLK1X_gc = (0x00<<2), /* 1x Peripheral Clock Output to pin */ - PORTCFG_CLKOUTSEL_CLK2X_gc = (0x01<<2), /* 2x Peripheral Clock Output to pin */ - PORTCFG_CLKOUTSEL_CLK4X_gc = (0x02<<2), /* 4x Peripheral Clock Output to pin */ -} PORTCFG_CLKOUTSEL_t; - -/* Event Output Port */ -typedef enum PORTCFG_EVOUT_enum -{ - PORTCFG_EVOUT_OFF_gc = (0x00<<4), /* Event Output Disabled */ - PORTCFG_EVOUT_PC7_gc = (0x01<<4), /* Event Channel 7 Output on Port C pin 7 */ - PORTCFG_EVOUT_PD7_gc = (0x02<<4), /* Event Channel 7 Output on Port D pin 7 */ - PORTCFG_EVOUT_PE7_gc = (0x03<<4), /* Event Channel 7 Output on Port E pin 7 */ -} PORTCFG_EVOUT_t; - -/* Event Output Select */ -typedef enum PORTCFG_EVOUTSEL_enum -{ - PORTCFG_EVOUTSEL_0_gc = (0x00<<0), /* Event Channel 0 output to pin */ - PORTCFG_EVOUTSEL_1_gc = (0x01<<0), /* Event Channel 1 output to pin */ - PORTCFG_EVOUTSEL_2_gc = (0x02<<0), /* Event Channel 2 output to pin */ - PORTCFG_EVOUTSEL_3_gc = (0x03<<0), /* Event Channel 3 output to pin */ -} PORTCFG_EVOUTSEL_t; - - -/* --------------------------------------------------------------------------- -CRC - Cyclic Redundancy Checker --------------------------------------------------------------------------- -*/ - -/* Cyclic Redundancy Checker */ -typedef struct CRC_struct -{ - register8_t CTRL; /* Control Register */ - register8_t STATUS; /* Status Register */ - register8_t reserved_0x02; - register8_t DATAIN; /* Data Input */ - register8_t CHECKSUM0; /* Checksum byte 0 */ - register8_t CHECKSUM1; /* Checksum byte 1 */ - register8_t CHECKSUM2; /* Checksum byte 2 */ - register8_t CHECKSUM3; /* Checksum byte 3 */ -} CRC_t; - -/* Reset */ -typedef enum CRC_RESET_enum -{ - CRC_RESET_NO_gc = (0x00<<6), /* No Reset */ - CRC_RESET_RESET0_gc = (0x02<<6), /* Reset CRC with CHECKSUM to all zeros */ - CRC_RESET_RESET1_gc = (0x03<<6), /* Reset CRC with CHECKSUM to all ones */ -} CRC_RESET_t; - -/* Input Source */ -typedef enum CRC_SOURCE_enum -{ - CRC_SOURCE_DISABLE_gc = (0x00<<0), /* Disabled */ - CRC_SOURCE_IO_gc = (0x01<<0), /* I/O Interface */ - CRC_SOURCE_FLASH_gc = (0x02<<0), /* Flash */ -} CRC_SOURCE_t; - - -/* --------------------------------------------------------------------------- -EVSYS - Event System --------------------------------------------------------------------------- -*/ - -/* Event System */ -typedef struct EVSYS_struct -{ - register8_t CH0MUX; /* Event Channel 0 Multiplexer */ - register8_t CH1MUX; /* Event Channel 1 Multiplexer */ - register8_t CH2MUX; /* Event Channel 2 Multiplexer */ - register8_t CH3MUX; /* Event Channel 3 Multiplexer */ - register8_t reserved_0x04; - register8_t reserved_0x05; - register8_t reserved_0x06; - register8_t reserved_0x07; - register8_t CH0CTRL; /* Channel 0 Control Register */ - register8_t CH1CTRL; /* Channel 1 Control Register */ - register8_t CH2CTRL; /* Channel 2 Control Register */ - register8_t CH3CTRL; /* Channel 3 Control Register */ - register8_t reserved_0x0C; - register8_t reserved_0x0D; - register8_t reserved_0x0E; - register8_t reserved_0x0F; - register8_t STROBE; /* Event Strobe */ - register8_t DATA; /* Event Data */ -} EVSYS_t; - -/* Quadrature Decoder Index Recognition Mode */ -typedef enum EVSYS_QDIRM_enum -{ - EVSYS_QDIRM_00_gc = (0x00<<5), /* QDPH0 = 0, QDPH90 = 0 */ - EVSYS_QDIRM_01_gc = (0x01<<5), /* QDPH0 = 0, QDPH90 = 1 */ - EVSYS_QDIRM_10_gc = (0x02<<5), /* QDPH0 = 1, QDPH90 = 0 */ - EVSYS_QDIRM_11_gc = (0x03<<5), /* QDPH0 = 1, QDPH90 = 1 */ -} EVSYS_QDIRM_t; - -/* Digital filter coefficient */ -typedef enum EVSYS_DIGFILT_enum -{ - EVSYS_DIGFILT_1SAMPLE_gc = (0x00<<0), /* 1 SAMPLE */ - EVSYS_DIGFILT_2SAMPLES_gc = (0x01<<0), /* 2 SAMPLES */ - EVSYS_DIGFILT_3SAMPLES_gc = (0x02<<0), /* 3 SAMPLES */ - EVSYS_DIGFILT_4SAMPLES_gc = (0x03<<0), /* 4 SAMPLES */ - EVSYS_DIGFILT_5SAMPLES_gc = (0x04<<0), /* 5 SAMPLES */ - EVSYS_DIGFILT_6SAMPLES_gc = (0x05<<0), /* 6 SAMPLES */ - EVSYS_DIGFILT_7SAMPLES_gc = (0x06<<0), /* 7 SAMPLES */ - EVSYS_DIGFILT_8SAMPLES_gc = (0x07<<0), /* 8 SAMPLES */ -} EVSYS_DIGFILT_t; - -/* Event Channel multiplexer input selection */ -typedef enum EVSYS_CHMUX_enum -{ - EVSYS_CHMUX_OFF_gc = (0x00<<0), /* Off */ - EVSYS_CHMUX_RTC_OVF_gc = (0x08<<0), /* RTC Overflow */ - EVSYS_CHMUX_RTC_CMP_gc = (0x09<<0), /* RTC Compare Match */ - EVSYS_CHMUX_USB_gc = (0x0A<<0), /* USB Setup, SOF, CRC error and UNF/OVF */ - EVSYS_CHMUX_ACA_CH0_gc = (0x10<<0), /* Analog Comparator A Channel 0 */ - EVSYS_CHMUX_ACA_CH1_gc = (0x11<<0), /* Analog Comparator A Channel 1 */ - EVSYS_CHMUX_ACA_WIN_gc = (0x12<<0), /* Analog Comparator A Window */ - EVSYS_CHMUX_ADCA_CH0_gc = (0x20<<0), /* ADC A Channel */ - EVSYS_CHMUX_PORTA_PIN0_gc = (0x50<<0), /* Port A, Pin0 */ - EVSYS_CHMUX_PORTA_PIN1_gc = (0x51<<0), /* Port A, Pin1 */ - EVSYS_CHMUX_PORTA_PIN2_gc = (0x52<<0), /* Port A, Pin2 */ - EVSYS_CHMUX_PORTA_PIN3_gc = (0x53<<0), /* Port A, Pin3 */ - EVSYS_CHMUX_PORTA_PIN4_gc = (0x54<<0), /* Port A, Pin4 */ - EVSYS_CHMUX_PORTA_PIN5_gc = (0x55<<0), /* Port A, Pin5 */ - EVSYS_CHMUX_PORTA_PIN6_gc = (0x56<<0), /* Port A, Pin6 */ - EVSYS_CHMUX_PORTA_PIN7_gc = (0x57<<0), /* Port A, Pin7 */ - EVSYS_CHMUX_PORTB_PIN0_gc = (0x58<<0), /* Port B, Pin0 */ - EVSYS_CHMUX_PORTB_PIN1_gc = (0x59<<0), /* Port B, Pin1 */ - EVSYS_CHMUX_PORTB_PIN2_gc = (0x5A<<0), /* Port B, Pin2 */ - EVSYS_CHMUX_PORTB_PIN3_gc = (0x5B<<0), /* Port B, Pin3 */ - EVSYS_CHMUX_PORTB_PIN4_gc = (0x5C<<0), /* Port B, Pin4 */ - EVSYS_CHMUX_PORTB_PIN5_gc = (0x5D<<0), /* Port B, Pin5 */ - EVSYS_CHMUX_PORTB_PIN6_gc = (0x5E<<0), /* Port B, Pin6 */ - EVSYS_CHMUX_PORTB_PIN7_gc = (0x5F<<0), /* Port B, Pin7 */ - EVSYS_CHMUX_PORTC_PIN0_gc = (0x60<<0), /* Port C, Pin0 */ - EVSYS_CHMUX_PORTC_PIN1_gc = (0x61<<0), /* Port C, Pin1 */ - EVSYS_CHMUX_PORTC_PIN2_gc = (0x62<<0), /* Port C, Pin2 */ - EVSYS_CHMUX_PORTC_PIN3_gc = (0x63<<0), /* Port C, Pin3 */ - EVSYS_CHMUX_PORTC_PIN4_gc = (0x64<<0), /* Port C, Pin4 */ - EVSYS_CHMUX_PORTC_PIN5_gc = (0x65<<0), /* Port C, Pin5 */ - EVSYS_CHMUX_PORTC_PIN6_gc = (0x66<<0), /* Port C, Pin6 */ - EVSYS_CHMUX_PORTC_PIN7_gc = (0x67<<0), /* Port C, Pin7 */ - EVSYS_CHMUX_PORTD_PIN0_gc = (0x68<<0), /* Port D, Pin0 */ - EVSYS_CHMUX_PORTD_PIN1_gc = (0x69<<0), /* Port D, Pin1 */ - EVSYS_CHMUX_PORTD_PIN2_gc = (0x6A<<0), /* Port D, Pin2 */ - EVSYS_CHMUX_PORTD_PIN3_gc = (0x6B<<0), /* Port D, Pin3 */ - EVSYS_CHMUX_PORTD_PIN4_gc = (0x6C<<0), /* Port D, Pin4 */ - EVSYS_CHMUX_PORTD_PIN5_gc = (0x6D<<0), /* Port D, Pin5 */ - EVSYS_CHMUX_PORTD_PIN6_gc = (0x6E<<0), /* Port D, Pin6 */ - EVSYS_CHMUX_PORTD_PIN7_gc = (0x6F<<0), /* Port D, Pin7 */ - EVSYS_CHMUX_PORTE_PIN0_gc = (0x70<<0), /* Port E, Pin0 */ - EVSYS_CHMUX_PORTE_PIN1_gc = (0x71<<0), /* Port E, Pin1 */ - EVSYS_CHMUX_PORTE_PIN2_gc = (0x72<<0), /* Port E, Pin2 */ - EVSYS_CHMUX_PORTE_PIN3_gc = (0x73<<0), /* Port E, Pin3 */ - EVSYS_CHMUX_PORTE_PIN4_gc = (0x74<<0), /* Port E, Pin4 */ - EVSYS_CHMUX_PORTE_PIN5_gc = (0x75<<0), /* Port E, Pin5 */ - EVSYS_CHMUX_PORTE_PIN6_gc = (0x76<<0), /* Port E, Pin6 */ - EVSYS_CHMUX_PORTE_PIN7_gc = (0x77<<0), /* Port E, Pin7 */ - EVSYS_CHMUX_PORTF_PIN0_gc = (0x78<<0), /* Port F, Pin0 */ - EVSYS_CHMUX_PORTF_PIN1_gc = (0x79<<0), /* Port F, Pin1 */ - EVSYS_CHMUX_PORTF_PIN2_gc = (0x7A<<0), /* Port F, Pin2 */ - EVSYS_CHMUX_PORTF_PIN3_gc = (0x7B<<0), /* Port F, Pin3 */ - EVSYS_CHMUX_PORTF_PIN4_gc = (0x7C<<0), /* Port F, Pin4 */ - EVSYS_CHMUX_PORTF_PIN5_gc = (0x7D<<0), /* Port F, Pin5 */ - EVSYS_CHMUX_PORTF_PIN6_gc = (0x7E<<0), /* Port F, Pin6 */ - EVSYS_CHMUX_PORTF_PIN7_gc = (0x7F<<0), /* Port F, Pin7 */ - EVSYS_CHMUX_PRESCALER_1_gc = (0x80<<0), /* Prescaler, divide by 1 */ - EVSYS_CHMUX_PRESCALER_2_gc = (0x81<<0), /* Prescaler, divide by 2 */ - EVSYS_CHMUX_PRESCALER_4_gc = (0x82<<0), /* Prescaler, divide by 4 */ - EVSYS_CHMUX_PRESCALER_8_gc = (0x83<<0), /* Prescaler, divide by 8 */ - EVSYS_CHMUX_PRESCALER_16_gc = (0x84<<0), /* Prescaler, divide by 16 */ - EVSYS_CHMUX_PRESCALER_32_gc = (0x85<<0), /* Prescaler, divide by 32 */ - EVSYS_CHMUX_PRESCALER_64_gc = (0x86<<0), /* Prescaler, divide by 64 */ - EVSYS_CHMUX_PRESCALER_128_gc = (0x87<<0), /* Prescaler, divide by 128 */ - EVSYS_CHMUX_PRESCALER_256_gc = (0x88<<0), /* Prescaler, divide by 256 */ - EVSYS_CHMUX_PRESCALER_512_gc = (0x89<<0), /* Prescaler, divide by 512 */ - EVSYS_CHMUX_PRESCALER_1024_gc = (0x8A<<0), /* Prescaler, divide by 1024 */ - EVSYS_CHMUX_PRESCALER_2048_gc = (0x8B<<0), /* Prescaler, divide by 2048 */ - EVSYS_CHMUX_PRESCALER_4096_gc = (0x8C<<0), /* Prescaler, divide by 4096 */ - EVSYS_CHMUX_PRESCALER_8192_gc = (0x8D<<0), /* Prescaler, divide by 8192 */ - EVSYS_CHMUX_PRESCALER_16384_gc = (0x8E<<0), /* Prescaler, divide by 16384 */ - EVSYS_CHMUX_PRESCALER_32768_gc = (0x8F<<0), /* Prescaler, divide by 32768 */ - EVSYS_CHMUX_TCC0_OVF_gc = (0xC0<<0), /* Timer/Counter C0 Overflow */ - EVSYS_CHMUX_TCC0_ERR_gc = (0xC1<<0), /* Timer/Counter C0 Error */ - EVSYS_CHMUX_TCC0_CCA_gc = (0xC4<<0), /* Timer/Counter C0 Compare or Capture A */ - EVSYS_CHMUX_TCC0_CCB_gc = (0xC5<<0), /* Timer/Counter C0 Compare or Capture B */ - EVSYS_CHMUX_TCC0_CCC_gc = (0xC6<<0), /* Timer/Counter C0 Compare or Capture C */ - EVSYS_CHMUX_TCC0_CCD_gc = (0xC7<<0), /* Timer/Counter C0 Compare or Capture D */ - EVSYS_CHMUX_TCC1_OVF_gc = (0xC8<<0), /* Timer/Counter C1 Overflow */ - EVSYS_CHMUX_TCC1_ERR_gc = (0xC9<<0), /* Timer/Counter C1 Error */ - EVSYS_CHMUX_TCC1_CCA_gc = (0xCC<<0), /* Timer/Counter C1 Compare or Capture A */ - EVSYS_CHMUX_TCC1_CCB_gc = (0xCD<<0), /* Timer/Counter C1 Compare or Capture B */ - EVSYS_CHMUX_TCD0_OVF_gc = (0xD0<<0), /* Timer/Counter D0 Overflow */ - EVSYS_CHMUX_TCD0_ERR_gc = (0xD1<<0), /* Timer/Counter D0 Error */ - EVSYS_CHMUX_TCD0_CCA_gc = (0xD4<<0), /* Timer/Counter D0 Compare or Capture A */ - EVSYS_CHMUX_TCD0_CCB_gc = (0xD5<<0), /* Timer/Counter D0 Compare or Capture B */ - EVSYS_CHMUX_TCD0_CCC_gc = (0xD6<<0), /* Timer/Counter D0 Compare or Capture C */ - EVSYS_CHMUX_TCD0_CCD_gc = (0xD7<<0), /* Timer/Counter D0 Compare or Capture D */ - EVSYS_CHMUX_TCE0_OVF_gc = (0xE0<<0), /* Timer/Counter E0 Overflow */ - EVSYS_CHMUX_TCE0_ERR_gc = (0xE1<<0), /* Timer/Counter E0 Error */ - EVSYS_CHMUX_TCE0_CCA_gc = (0xE4<<0), /* Timer/Counter E0 Compare or Capture A */ - EVSYS_CHMUX_TCE0_CCB_gc = (0xE5<<0), /* Timer/Counter E0 Compare or Capture B */ - EVSYS_CHMUX_TCE0_CCC_gc = (0xE6<<0), /* Timer/Counter E0 Compare or Capture C */ - EVSYS_CHMUX_TCE0_CCD_gc = (0xE7<<0), /* Timer/Counter E0 Compare or Capture D */ - EVSYS_CHMUX_TCF0_OVF_gc = (0xF0<<0), /* Timer/Counter F0 Overflow */ - EVSYS_CHMUX_TCF0_ERR_gc = (0xF1<<0), /* Timer/Counter F0 Error */ - EVSYS_CHMUX_TCF0_CCA_gc = (0xF4<<0), /* Timer/Counter F0 Compare or Capture A */ - EVSYS_CHMUX_TCF0_CCB_gc = (0xF5<<0), /* Timer/Counter F0 Compare or Capture B */ - EVSYS_CHMUX_TCF0_CCC_gc = (0xF6<<0), /* Timer/Counter F0 Compare or Capture C */ - EVSYS_CHMUX_TCF0_CCD_gc = (0xF7<<0), /* Timer/Counter F0 Compare or Capture D */ -} EVSYS_CHMUX_t; - - -/* --------------------------------------------------------------------------- -NVM - Non Volatile Memory Controller --------------------------------------------------------------------------- -*/ - -/* Non-volatile Memory Controller */ -typedef struct NVM_struct -{ - register8_t ADDR0; /* Address Register 0 */ - register8_t ADDR1; /* Address Register 1 */ - register8_t ADDR2; /* Address Register 2 */ - register8_t reserved_0x03; - register8_t DATA0; /* Data Register 0 */ - register8_t DATA1; /* Data Register 1 */ - register8_t DATA2; /* Data Register 2 */ - register8_t reserved_0x07; - register8_t reserved_0x08; - register8_t reserved_0x09; - register8_t CMD; /* Command */ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t INTCTRL; /* Interrupt Control */ - register8_t reserved_0x0E; - register8_t STATUS; /* Status */ - register8_t LOCK_BITS; /* Lock Bits (Changed from LOCKBITS to avoid avr-libc collision) */ -} NVM_t; - -/* NVM Command */ -typedef enum NVM_CMD_enum -{ - NVM_CMD_NO_OPERATION_gc = (0x00<<0), /* Noop/Ordinary LPM */ - NVM_CMD_READ_USER_SIG_ROW_gc = (0x01<<0), /* Read user signature row */ - NVM_CMD_READ_CALIB_ROW_gc = (0x02<<0), /* Read calibration row */ - NVM_CMD_READ_EEPROM_gc = (0x06<<0), /* Read EEPROM */ - NVM_CMD_READ_FUSES_gc = (0x07<<0), /* Read fuse byte */ - NVM_CMD_WRITE_LOCK_BITS_gc = (0x08<<0), /* Write lock bits */ - NVM_CMD_ERASE_USER_SIG_ROW_gc = (0x18<<0), /* Erase user signature row */ - NVM_CMD_WRITE_USER_SIG_ROW_gc = (0x1A<<0), /* Write user signature row */ - NVM_CMD_ERASE_APP_gc = (0x20<<0), /* Erase Application Section */ - NVM_CMD_ERASE_APP_PAGE_gc = (0x22<<0), /* Erase Application Section page */ - NVM_CMD_LOAD_FLASH_BUFFER_gc = (0x23<<0), /* Load Flash page buffer */ - NVM_CMD_WRITE_APP_PAGE_gc = (0x24<<0), /* Write Application Section page */ - NVM_CMD_ERASE_WRITE_APP_PAGE_gc = (0x25<<0), /* Erase-and-write Application Section page */ - NVM_CMD_ERASE_FLASH_BUFFER_gc = (0x26<<0), /* Erase/flush Flash page buffer */ - NVM_CMD_ERASE_BOOT_PAGE_gc = (0x2A<<0), /* Erase Boot Section page */ - NVM_CMD_ERASE_FLASH_PAGE_gc = (0x2B<<0), /* Erase Flash Page */ - NVM_CMD_WRITE_BOOT_PAGE_gc = (0x2C<<0), /* Write Boot Section page */ - NVM_CMD_ERASE_WRITE_BOOT_PAGE_gc = (0x2D<<0), /* Erase-and-write Boot Section page */ - NVM_CMD_WRITE_FLASH_PAGE_gc = (0x2E<<0), /* Write Flash Page */ - NVM_CMD_ERASE_WRITE_FLASH_PAGE_gc = (0x2F<<0), /* Erase-and-write Flash Page */ - NVM_CMD_ERASE_EEPROM_gc = (0x30<<0), /* Erase EEPROM */ - NVM_CMD_ERASE_EEPROM_PAGE_gc = (0x32<<0), /* Erase EEPROM page */ - NVM_CMD_LOAD_EEPROM_BUFFER_gc = (0x33<<0), /* Load EEPROM page buffer */ - NVM_CMD_WRITE_EEPROM_PAGE_gc = (0x34<<0), /* Write EEPROM page */ - NVM_CMD_ERASE_WRITE_EEPROM_PAGE_gc = (0x35<<0), /* Erase-and-write EEPROM page */ - NVM_CMD_ERASE_EEPROM_BUFFER_gc = (0x36<<0), /* Erase/flush EEPROM page buffer */ - NVM_CMD_APP_CRC_gc = (0x38<<0), /* Application section CRC */ - NVM_CMD_BOOT_CRC_gc = (0x39<<0), /* Boot Section CRC */ - NVM_CMD_FLASH_RANGE_CRC_gc = (0x3A<<0), /* Flash Range CRC */ - NVM_CMD_CHIP_ERASE_gc = (0x40<<0), /* Erase Chip */ - NVM_CMD_READ_NVM_gc = (0x43<<0), /* Read NVM */ - NVM_CMD_WRITE_FUSE_gc = (0x4C<<0), /* Write Fuse byte */ - NVM_CMD_ERASE_BOOT_gc = (0x68<<0), /* Erase Boot Section */ - NVM_CMD_FLASH_CRC_gc = (0x78<<0), /* Flash CRC */ -} NVM_CMD_t; - -/* SPM ready interrupt level */ -typedef enum NVM_SPMLVL_enum -{ - NVM_SPMLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ - NVM_SPMLVL_LO_gc = (0x01<<2), /* Low level */ - NVM_SPMLVL_MED_gc = (0x02<<2), /* Medium level */ - NVM_SPMLVL_HI_gc = (0x03<<2), /* High level */ -} NVM_SPMLVL_t; - -/* EEPROM ready interrupt level */ -typedef enum NVM_EELVL_enum -{ - NVM_EELVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ - NVM_EELVL_LO_gc = (0x01<<0), /* Low level */ - NVM_EELVL_MED_gc = (0x02<<0), /* Medium level */ - NVM_EELVL_HI_gc = (0x03<<0), /* High level */ -} NVM_EELVL_t; - -/* Boot lock bits - boot setcion */ -typedef enum NVM_BLBB_enum -{ - NVM_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ - NVM_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ - NVM_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ - NVM_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ -} NVM_BLBB_t; - -/* Boot lock bits - application section */ -typedef enum NVM_BLBA_enum -{ - NVM_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ - NVM_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ - NVM_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ - NVM_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ -} NVM_BLBA_t; - -/* Boot lock bits - application table section */ -typedef enum NVM_BLBAT_enum -{ - NVM_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ - NVM_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ - NVM_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ - NVM_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ -} NVM_BLBAT_t; - -/* Lock bits */ -typedef enum NVM_LB_enum -{ - NVM_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ - NVM_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ - NVM_LB_NOLOCK_gc = (0x03<<0), /* No locks */ -} NVM_LB_t; - - -/* --------------------------------------------------------------------------- -ADC - Analog/Digital Converter --------------------------------------------------------------------------- -*/ - -/* ADC Channel */ -typedef struct ADC_CH_struct -{ - register8_t CTRL; /* Control Register */ - register8_t MUXCTRL; /* MUX Control */ - register8_t INTCTRL; /* Channel Interrupt Control Register */ - register8_t INTFLAGS; /* Interrupt Flags */ - _WORDREGISTER(RES); /* Channel Result */ - register8_t SCAN; /* Input Channel Scan */ - register8_t reserved_0x07; -} ADC_CH_t; - - -/* Analog-to-Digital Converter */ -typedef struct ADC_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t REFCTRL; /* Reference Control */ - register8_t EVCTRL; /* Event Control */ - register8_t PRESCALER; /* Clock Prescaler */ - register8_t reserved_0x05; - register8_t INTFLAGS; /* Interrupt Flags */ - register8_t TEMP; /* Temporary Register */ - register8_t reserved_0x08; - register8_t reserved_0x09; - register8_t reserved_0x0A; - register8_t reserved_0x0B; - _WORDREGISTER(CAL); /* Calibration Value */ - register8_t reserved_0x0E; - register8_t reserved_0x0F; - _WORDREGISTER(CH0RES); /* Channel 0 Result */ - register8_t reserved_0x12; - register8_t reserved_0x13; - register8_t reserved_0x14; - register8_t reserved_0x15; - register8_t reserved_0x16; - register8_t reserved_0x17; - _WORDREGISTER(CMP); /* Compare Value */ - register8_t reserved_0x1A; - register8_t reserved_0x1B; - register8_t reserved_0x1C; - register8_t reserved_0x1D; - register8_t reserved_0x1E; - register8_t reserved_0x1F; - ADC_CH_t CH0; /* ADC Channel 0 */ -} ADC_t; - -/* Current Limitation */ -typedef enum ADC_CURRLIMIT_enum -{ - ADC_CURRLIMIT_NO_gc = (0x00<<5), /* No current limit, 300ksps max sampling rate */ - ADC_CURRLIMIT_LOW_gc = (0x01<<5), /* Low current limit, 250ksps max sampling rate */ - ADC_CURRLIMIT_MED_gc = (0x02<<5), /* Medium current limit, 150ksps max sampling rate */ - ADC_CURRLIMIT_HIGH_gc = (0x03<<5), /* High current limit, 50ksps max sampling rate */ -} ADC_CURRLIMIT_t; - -/* Positive input multiplexer selection */ -typedef enum ADC_CH_MUXPOS_enum -{ - ADC_CH_MUXPOS_PIN0_gc = (0x00<<3), /* Input pin 0 */ - ADC_CH_MUXPOS_PIN1_gc = (0x01<<3), /* Input pin 1 */ - ADC_CH_MUXPOS_PIN2_gc = (0x02<<3), /* Input pin 2 */ - ADC_CH_MUXPOS_PIN3_gc = (0x03<<3), /* Input pin 3 */ - ADC_CH_MUXPOS_PIN4_gc = (0x04<<3), /* Input pin 4 */ - ADC_CH_MUXPOS_PIN5_gc = (0x05<<3), /* Input pin 5 */ - ADC_CH_MUXPOS_PIN6_gc = (0x06<<3), /* Input pin 6 */ - ADC_CH_MUXPOS_PIN7_gc = (0x07<<3), /* Input pin 7 */ - ADC_CH_MUXPOS_PIN8_gc = (0x08<<3), /* Input pin 8 */ - ADC_CH_MUXPOS_PIN9_gc = (0x09<<3), /* Input pin 9 */ - ADC_CH_MUXPOS_PIN10_gc = (0x0A<<3), /* Input pin 10 */ - ADC_CH_MUXPOS_PIN11_gc = (0x0B<<3), /* Input pin 11 */ - ADC_CH_MUXPOS_PIN12_gc = (0x0C<<3), /* Input pin 12 */ - ADC_CH_MUXPOS_PIN13_gc = (0x0D<<3), /* Input pin 13 */ - ADC_CH_MUXPOS_PIN14_gc = (0x0E<<3), /* Input pin 14 */ - ADC_CH_MUXPOS_PIN15_gc = (0x0F<<3), /* Input pin 15 */ -} ADC_CH_MUXPOS_t; - -/* Internal input multiplexer selections */ -typedef enum ADC_CH_MUXINT_enum -{ - ADC_CH_MUXINT_TEMP_gc = (0x00<<3), /* Temperature Reference */ - ADC_CH_MUXINT_BANDGAP_gc = (0x01<<3), /* Bandgap Reference */ - ADC_CH_MUXINT_SCALEDVCC_gc = (0x02<<3), /* 1/10 scaled VCC */ -} ADC_CH_MUXINT_t; - -/* Negative input multiplexer selection */ -typedef enum ADC_CH_MUXNEG_enum -{ - ADC_CH_MUXNEG_PIN0_gc = (0x00<<0), /* Input pin 0 */ - ADC_CH_MUXNEG_PIN1_gc = (0x01<<0), /* Input pin 1 */ - ADC_CH_MUXNEG_PIN2_gc = (0x02<<0), /* Input pin 2 */ - ADC_CH_MUXNEG_PIN3_gc = (0x03<<0), /* Input pin 3 */ - ADC_CH_MUXNEG_PIN4_gc = (0x00<<0), /* Input pin 4 */ - ADC_CH_MUXNEG_PIN5_gc = (0x01<<0), /* Input pin 5 */ - ADC_CH_MUXNEG_PIN6_gc = (0x02<<0), /* Input pin 6 */ - ADC_CH_MUXNEG_PIN7_gc = (0x03<<0), /* Input pin 7 */ -} ADC_CH_MUXNEG_t; - -/* Input mode */ -typedef enum ADC_CH_INPUTMODE_enum -{ - ADC_CH_INPUTMODE_INTERNAL_gc = (0x00<<0), /* Internal inputs, no gain */ - ADC_CH_INPUTMODE_SINGLEENDED_gc = (0x01<<0), /* Single-ended input, no gain */ - ADC_CH_INPUTMODE_DIFF_gc = (0x02<<0), /* Differential input, no gain */ - ADC_CH_INPUTMODE_DIFFWGAIN_gc = (0x03<<0), /* Differential input, with gain */ -} ADC_CH_INPUTMODE_t; - -/* Gain factor */ -typedef enum ADC_CH_GAIN_enum -{ - ADC_CH_GAIN_1X_gc = (0x00<<2), /* 1x gain */ - ADC_CH_GAIN_2X_gc = (0x01<<2), /* 2x gain */ - ADC_CH_GAIN_4X_gc = (0x02<<2), /* 4x gain */ - ADC_CH_GAIN_8X_gc = (0x03<<2), /* 8x gain */ - ADC_CH_GAIN_16X_gc = (0x04<<2), /* 16x gain */ - ADC_CH_GAIN_32X_gc = (0x05<<2), /* 32x gain */ - ADC_CH_GAIN_64X_gc = (0x06<<2), /* 64x gain */ - ADC_CH_GAIN_DIV2_gc = (0x07<<2), /* x/2 gain */ -} ADC_CH_GAIN_t; - -/* Conversion result resolution */ -typedef enum ADC_RESOLUTION_enum -{ - ADC_RESOLUTION_12BIT_gc = (0x00<<1), /* 12-bit right-adjusted result */ - ADC_RESOLUTION_8BIT_gc = (0x02<<1), /* 8-bit right-adjusted result */ - ADC_RESOLUTION_LEFT12BIT_gc = (0x03<<1), /* 12-bit left-adjusted result */ -} ADC_RESOLUTION_t; - -/* Voltage reference selection */ -typedef enum ADC_REFSEL_enum -{ - ADC_REFSEL_INT1V_gc = (0x00<<4), /* Internal 1V */ - ADC_REFSEL_INTVCC_gc = (0x01<<4), /* Internal VCC / 1.6 */ - ADC_REFSEL_AREFA_gc = (0x02<<4), /* External reference on PORT A */ - ADC_REFSEL_AREFB_gc = (0x03<<4), /* External reference on PORT B */ - ADC_REFSEL_INTVCC2_gc = (0x04<<4), /* Internal VCC / 2 */ -} ADC_REFSEL_t; - -/* Event channel input selection */ -typedef enum ADC_EVSEL_enum -{ - ADC_EVSEL_0_gc = (0x00<<3), /* Event Channel 0 */ - ADC_EVSEL_1_gc = (0x01<<3), /* Event Channel 1 */ - ADC_EVSEL_2_gc = (0x02<<3), /* Event Channel 2 */ - ADC_EVSEL_3_gc = (0x03<<3), /* Event Channel 3 */ -} ADC_EVSEL_t; - -/* Event action selection */ -typedef enum ADC_EVACT_enum -{ - ADC_EVACT_NONE_gc = (0x00<<0), /* No event action */ - ADC_EVACT_CH0_gc = (0x01<<0), /* First event triggers channel 0 */ - ADC_EVACT_SYNCSWEEP_gc = (0x06<<0), /* The ADC is flushed and restarted for accurate timing */ -} ADC_EVACT_t; - -/* Interupt mode */ -typedef enum ADC_CH_INTMODE_enum -{ - ADC_CH_INTMODE_COMPLETE_gc = (0x00<<2), /* Interrupt on conversion complete */ - ADC_CH_INTMODE_BELOW_gc = (0x01<<2), /* Interrupt on result below compare value */ - ADC_CH_INTMODE_ABOVE_gc = (0x03<<2), /* Interrupt on result above compare value */ -} ADC_CH_INTMODE_t; - -/* Interrupt level */ -typedef enum ADC_CH_INTLVL_enum -{ - ADC_CH_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ - ADC_CH_INTLVL_LO_gc = (0x01<<0), /* Low level */ - ADC_CH_INTLVL_MED_gc = (0x02<<0), /* Medium level */ - ADC_CH_INTLVL_HI_gc = (0x03<<0), /* High level */ -} ADC_CH_INTLVL_t; - -/* Clock prescaler */ -typedef enum ADC_PRESCALER_enum -{ - ADC_PRESCALER_DIV4_gc = (0x00<<0), /* Divide clock by 4 */ - ADC_PRESCALER_DIV8_gc = (0x01<<0), /* Divide clock by 8 */ - ADC_PRESCALER_DIV16_gc = (0x02<<0), /* Divide clock by 16 */ - ADC_PRESCALER_DIV32_gc = (0x03<<0), /* Divide clock by 32 */ - ADC_PRESCALER_DIV64_gc = (0x04<<0), /* Divide clock by 64 */ - ADC_PRESCALER_DIV128_gc = (0x05<<0), /* Divide clock by 128 */ - ADC_PRESCALER_DIV256_gc = (0x06<<0), /* Divide clock by 256 */ - ADC_PRESCALER_DIV512_gc = (0x07<<0), /* Divide clock by 512 */ -} ADC_PRESCALER_t; - - -/* --------------------------------------------------------------------------- -AC - Analog Comparator --------------------------------------------------------------------------- -*/ - -/* Analog Comparator */ -typedef struct AC_struct -{ - register8_t AC0CTRL; /* Analog Comparator 0 Control */ - register8_t AC1CTRL; /* Analog Comparator 1 Control */ - register8_t AC0MUXCTRL; /* Analog Comparator 0 MUX Control */ - register8_t AC1MUXCTRL; /* Analog Comparator 1 MUX Control */ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t WINCTRL; /* Window Mode Control */ - register8_t STATUS; /* Status */ -} AC_t; - -/* Interrupt mode */ -typedef enum AC_INTMODE_enum -{ - AC_INTMODE_BOTHEDGES_gc = (0x00<<6), /* Interrupt on both edges */ - AC_INTMODE_FALLING_gc = (0x02<<6), /* Interrupt on falling edge */ - AC_INTMODE_RISING_gc = (0x03<<6), /* Interrupt on rising edge */ -} AC_INTMODE_t; - -/* Interrupt level */ -typedef enum AC_INTLVL_enum -{ - AC_INTLVL_OFF_gc = (0x00<<4), /* Interrupt disabled */ - AC_INTLVL_LO_gc = (0x01<<4), /* Low level */ - AC_INTLVL_MED_gc = (0x02<<4), /* Medium level */ - AC_INTLVL_HI_gc = (0x03<<4), /* High level */ -} AC_INTLVL_t; - -/* Hysteresis mode selection */ -typedef enum AC_HYSMODE_enum -{ - AC_HYSMODE_NO_gc = (0x00<<1), /* No hysteresis */ - AC_HYSMODE_SMALL_gc = (0x01<<1), /* Small hysteresis */ - AC_HYSMODE_LARGE_gc = (0x02<<1), /* Large hysteresis */ -} AC_HYSMODE_t; - -/* Positive input multiplexer selection */ -typedef enum AC_MUXPOS_enum -{ - AC_MUXPOS_PIN0_gc = (0x00<<3), /* Pin 0 */ - AC_MUXPOS_PIN1_gc = (0x01<<3), /* Pin 1 */ - AC_MUXPOS_PIN2_gc = (0x02<<3), /* Pin 2 */ - AC_MUXPOS_PIN3_gc = (0x03<<3), /* Pin 3 */ - AC_MUXPOS_PIN4_gc = (0x04<<3), /* Pin 4 */ - AC_MUXPOS_PIN5_gc = (0x05<<3), /* Pin 5 */ - AC_MUXPOS_PIN6_gc = (0x06<<3), /* Pin 6 */ -} AC_MUXPOS_t; - -/* Negative input multiplexer selection */ -typedef enum AC_MUXNEG_enum -{ - AC_MUXNEG_PIN0_gc = (0x00<<0), /* Pin 0 */ - AC_MUXNEG_PIN1_gc = (0x01<<0), /* Pin 1 */ - AC_MUXNEG_PIN3_gc = (0x02<<0), /* Pin 3 */ - AC_MUXNEG_PIN5_gc = (0x03<<0), /* Pin 5 */ - AC_MUXNEG_PIN7_gc = (0x04<<0), /* Pin 7 */ - AC_MUXNEG_BANDGAP_gc = (0x06<<0), /* Bandgap Reference */ - AC_MUXNEG_SCALER_gc = (0x07<<0), /* Internal voltage scaler */ -} AC_MUXNEG_t; - -/* Windows interrupt mode */ -typedef enum AC_WINTMODE_enum -{ - AC_WINTMODE_ABOVE_gc = (0x00<<2), /* Interrupt on above window */ - AC_WINTMODE_INSIDE_gc = (0x01<<2), /* Interrupt on inside window */ - AC_WINTMODE_BELOW_gc = (0x02<<2), /* Interrupt on below window */ - AC_WINTMODE_OUTSIDE_gc = (0x03<<2), /* Interrupt on outside window */ -} AC_WINTMODE_t; - -/* Window interrupt level */ -typedef enum AC_WINTLVL_enum -{ - AC_WINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ - AC_WINTLVL_LO_gc = (0x01<<0), /* Low priority */ - AC_WINTLVL_MED_gc = (0x02<<0), /* Medium priority */ - AC_WINTLVL_HI_gc = (0x03<<0), /* High priority */ -} AC_WINTLVL_t; - -/* Window mode state */ -typedef enum AC_WSTATE_enum -{ - AC_WSTATE_ABOVE_gc = (0x00<<6), /* Signal above window */ - AC_WSTATE_INSIDE_gc = (0x01<<6), /* Signal inside window */ - AC_WSTATE_BELOW_gc = (0x02<<6), /* Signal below window */ -} AC_WSTATE_t; - - -/* --------------------------------------------------------------------------- -RTC - Real-Time Counter --------------------------------------------------------------------------- -*/ - -/* Real-Time Counter */ -typedef struct RTC_struct -{ - register8_t CTRL; /* Control Register */ - register8_t STATUS; /* Status Register */ - register8_t INTCTRL; /* Interrupt Control Register */ - register8_t INTFLAGS; /* Interrupt Flags */ - register8_t TEMP; /* Temporary register */ - register8_t reserved_0x05; - register8_t reserved_0x06; - register8_t reserved_0x07; - _WORDREGISTER(CNT); /* Count Register */ - _WORDREGISTER(PER); /* Period Register */ - _WORDREGISTER(COMP); /* Compare Register */ -} RTC_t; - -/* Prescaler Factor */ -typedef enum RTC_PRESCALER_enum -{ - RTC_PRESCALER_OFF_gc = (0x00<<0), /* RTC Off */ - RTC_PRESCALER_DIV1_gc = (0x01<<0), /* RTC Clock */ - RTC_PRESCALER_DIV2_gc = (0x02<<0), /* RTC Clock / 2 */ - RTC_PRESCALER_DIV8_gc = (0x03<<0), /* RTC Clock / 8 */ - RTC_PRESCALER_DIV16_gc = (0x04<<0), /* RTC Clock / 16 */ - RTC_PRESCALER_DIV64_gc = (0x05<<0), /* RTC Clock / 64 */ - RTC_PRESCALER_DIV256_gc = (0x06<<0), /* RTC Clock / 256 */ - RTC_PRESCALER_DIV1024_gc = (0x07<<0), /* RTC Clock / 1024 */ -} RTC_PRESCALER_t; - -/* Compare Interrupt level */ -typedef enum RTC_COMPINTLVL_enum -{ - RTC_COMPINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ - RTC_COMPINTLVL_LO_gc = (0x01<<2), /* Low Level */ - RTC_COMPINTLVL_MED_gc = (0x02<<2), /* Medium Level */ - RTC_COMPINTLVL_HI_gc = (0x03<<2), /* High Level */ -} RTC_COMPINTLVL_t; - -/* Overflow Interrupt level */ -typedef enum RTC_OVFINTLVL_enum -{ - RTC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - RTC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ - RTC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ - RTC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ -} RTC_OVFINTLVL_t; - - -/* --------------------------------------------------------------------------- -TWI - Two-Wire Interface --------------------------------------------------------------------------- -*/ - -/* */ -typedef struct TWI_MASTER_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t CTRLC; /* Control Register C */ - register8_t STATUS; /* Status Register */ - register8_t BAUD; /* Baurd Rate Control Register */ - register8_t ADDR; /* Address Register */ - register8_t DATA; /* Data Register */ -} TWI_MASTER_t; - - -/* */ -typedef struct TWI_SLAVE_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t STATUS; /* Status Register */ - register8_t ADDR; /* Address Register */ - register8_t DATA; /* Data Register */ - register8_t ADDRMASK; /* Address Mask Register */ -} TWI_SLAVE_t; - - -/* Two-Wire Interface */ -typedef struct TWI_struct -{ - register8_t CTRL; /* TWI Common Control Register */ - TWI_MASTER_t MASTER; /* TWI master module */ - TWI_SLAVE_t SLAVE; /* TWI slave module */ -} TWI_t; - -/* SDA Hold Time */ -typedef enum TWI_SDAHOLD_enum -{ - TWI_SDAHOLD_OFF_gc = (0x00<<1), /* SDA Hold Time off */ - TWI_SDAHOLD_50NS_gc = (0x01<<1), /* SDA Hold Time 50 ns */ - TWI_SDAHOLD_300NS_gc = (0x02<<1), /* SDA Hold Time 300 ns */ - TWI_SDAHOLD_400NS_gc = (0x03<<1), /* SDA Hold Time 400 ns */ -} TWI_SDAHOLD_t; - -/* Master Interrupt Level */ -typedef enum TWI_MASTER_INTLVL_enum -{ - TWI_MASTER_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ - TWI_MASTER_INTLVL_LO_gc = (0x01<<6), /* Low Level */ - TWI_MASTER_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ - TWI_MASTER_INTLVL_HI_gc = (0x03<<6), /* High Level */ -} TWI_MASTER_INTLVL_t; - -/* Inactive Timeout */ -typedef enum TWI_MASTER_TIMEOUT_enum -{ - TWI_MASTER_TIMEOUT_DISABLED_gc = (0x00<<2), /* Bus Timeout Disabled */ - TWI_MASTER_TIMEOUT_50US_gc = (0x01<<2), /* 50 Microseconds */ - TWI_MASTER_TIMEOUT_100US_gc = (0x02<<2), /* 100 Microseconds */ - TWI_MASTER_TIMEOUT_200US_gc = (0x03<<2), /* 200 Microseconds */ -} TWI_MASTER_TIMEOUT_t; - -/* Master Command */ -typedef enum TWI_MASTER_CMD_enum -{ - TWI_MASTER_CMD_NOACT_gc = (0x00<<0), /* No Action */ - TWI_MASTER_CMD_REPSTART_gc = (0x01<<0), /* Issue Repeated Start Condition */ - TWI_MASTER_CMD_RECVTRANS_gc = (0x02<<0), /* Receive or Transmit Data */ - TWI_MASTER_CMD_STOP_gc = (0x03<<0), /* Issue Stop Condition */ -} TWI_MASTER_CMD_t; - -/* Master Bus State */ -typedef enum TWI_MASTER_BUSSTATE_enum -{ - TWI_MASTER_BUSSTATE_UNKNOWN_gc = (0x00<<0), /* Unknown Bus State */ - TWI_MASTER_BUSSTATE_IDLE_gc = (0x01<<0), /* Bus is Idle */ - TWI_MASTER_BUSSTATE_OWNER_gc = (0x02<<0), /* This Module Controls The Bus */ - TWI_MASTER_BUSSTATE_BUSY_gc = (0x03<<0), /* The Bus is Busy */ -} TWI_MASTER_BUSSTATE_t; - -/* Slave Interrupt Level */ -typedef enum TWI_SLAVE_INTLVL_enum -{ - TWI_SLAVE_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ - TWI_SLAVE_INTLVL_LO_gc = (0x01<<6), /* Low Level */ - TWI_SLAVE_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ - TWI_SLAVE_INTLVL_HI_gc = (0x03<<6), /* High Level */ -} TWI_SLAVE_INTLVL_t; - -/* Slave Command */ -typedef enum TWI_SLAVE_CMD_enum -{ - TWI_SLAVE_CMD_NOACT_gc = (0x00<<0), /* No Action */ - TWI_SLAVE_CMD_COMPTRANS_gc = (0x02<<0), /* Used To Complete a Transaction */ - TWI_SLAVE_CMD_RESPONSE_gc = (0x03<<0), /* Used in Response to Address/Data Interrupt */ -} TWI_SLAVE_CMD_t; - - -/* --------------------------------------------------------------------------- -USB - USB --------------------------------------------------------------------------- -*/ - -/* USB Endpoint */ -typedef struct USB_EP_struct -{ - register8_t STATUS; /* Endpoint Status */ - register8_t CTRL; /* Endpoint Control */ - _WORDREGISTER(CNT); /* USB Endpoint Counter */ - _WORDREGISTER(DATAPTR); /* Data Pointer */ - _WORDREGISTER(AUXDATA); /* Auxiliary Data */ -} USB_EP_t; - - -/* Universal Serial Bus */ -typedef struct USB_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t STATUS; /* Status Register */ - register8_t ADDR; /* Address Register */ - register8_t FIFOWP; /* FIFO Write Pointer Register */ - register8_t FIFORP; /* FIFO Read Pointer Register */ - _WORDREGISTER(EPPTR); /* Endpoint Configuration Table Pointer */ - register8_t INTCTRLA; /* Interrupt Control Register A */ - register8_t INTCTRLB; /* Interrupt Control Register B */ - register8_t INTFLAGSACLR; /* Clear Interrupt Flag Register A */ - register8_t INTFLAGSASET; /* Set Interrupt Flag Register A */ - register8_t INTFLAGSBCLR; /* Clear Interrupt Flag Register B */ - register8_t INTFLAGSBSET; /* Set Interrupt Flag Register B */ - register8_t reserved_0x0E; - register8_t reserved_0x0F; - register8_t reserved_0x10; - register8_t reserved_0x11; - register8_t reserved_0x12; - register8_t reserved_0x13; - register8_t reserved_0x14; - register8_t reserved_0x15; - register8_t reserved_0x16; - register8_t reserved_0x17; - register8_t reserved_0x18; - register8_t reserved_0x19; - register8_t reserved_0x1A; - register8_t reserved_0x1B; - register8_t reserved_0x1C; - register8_t reserved_0x1D; - register8_t reserved_0x1E; - register8_t reserved_0x1F; - register8_t reserved_0x20; - register8_t reserved_0x21; - register8_t reserved_0x22; - register8_t reserved_0x23; - register8_t reserved_0x24; - register8_t reserved_0x25; - register8_t reserved_0x26; - register8_t reserved_0x27; - register8_t reserved_0x28; - register8_t reserved_0x29; - register8_t reserved_0x2A; - register8_t reserved_0x2B; - register8_t reserved_0x2C; - register8_t reserved_0x2D; - register8_t reserved_0x2E; - register8_t reserved_0x2F; - register8_t reserved_0x30; - register8_t reserved_0x31; - register8_t reserved_0x32; - register8_t reserved_0x33; - register8_t reserved_0x34; - register8_t reserved_0x35; - register8_t reserved_0x36; - register8_t reserved_0x37; - register8_t reserved_0x38; - register8_t reserved_0x39; - register8_t CAL0; /* Calibration Byte 0 */ - register8_t CAL1; /* Calibration Byte 1 */ -} USB_t; - - -/* USB Endpoint Table */ -typedef struct USB_EP_TABLE_struct -{ - USB_EP_t EP0OUT; /* Endpoint 0 */ - USB_EP_t EP0IN; /* Endpoint 0 */ - USB_EP_t EP1OUT; /* Endpoint 1 */ - USB_EP_t EP1IN; /* Endpoint 1 */ - USB_EP_t EP2OUT; /* Endpoint 2 */ - USB_EP_t EP2IN; /* Endpoint 2 */ - USB_EP_t EP3OUT; /* Endpoint 3 */ - USB_EP_t EP3IN; /* Endpoint 3 */ - USB_EP_t EP4OUT; /* Endpoint 4 */ - USB_EP_t EP4IN; /* Endpoint 4 */ - USB_EP_t EP5OUT; /* Endpoint 5 */ - USB_EP_t EP5IN; /* Endpoint 5 */ - USB_EP_t EP6OUT; /* Endpoint 6 */ - USB_EP_t EP6IN; /* Endpoint 6 */ - USB_EP_t EP7OUT; /* Endpoint 7 */ - USB_EP_t EP7IN; /* Endpoint 7 */ - USB_EP_t EP8OUT; /* Endpoint 8 */ - USB_EP_t EP8IN; /* Endpoint 8 */ - USB_EP_t EP9OUT; /* Endpoint 9 */ - USB_EP_t EP9IN; /* Endpoint 9 */ - USB_EP_t EP10OUT; /* Endpoint 10 */ - USB_EP_t EP10IN; /* Endpoint 10 */ - USB_EP_t EP11OUT; /* Endpoint 11 */ - USB_EP_t EP11IN; /* Endpoint 11 */ - USB_EP_t EP12OUT; /* Endpoint 12 */ - USB_EP_t EP12IN; /* Endpoint 12 */ - USB_EP_t EP13OUT; /* Endpoint 13 */ - USB_EP_t EP13IN; /* Endpoint 13 */ - USB_EP_t EP14OUT; /* Endpoint 14 */ - USB_EP_t EP14IN; /* Endpoint 14 */ - USB_EP_t EP15OUT; /* Endpoint 15 */ - USB_EP_t EP15IN; /* Endpoint 15 */ - register8_t reserved_0x100; - register8_t reserved_0x101; - register8_t reserved_0x102; - register8_t reserved_0x103; - register8_t reserved_0x104; - register8_t reserved_0x105; - register8_t reserved_0x106; - register8_t reserved_0x107; - register8_t reserved_0x108; - register8_t reserved_0x109; - register8_t reserved_0x10A; - register8_t reserved_0x10B; - register8_t reserved_0x10C; - register8_t reserved_0x10D; - register8_t reserved_0x10E; - register8_t reserved_0x10F; - register8_t FRAMENUML; /* Frame Number Low Byte */ - register8_t FRAMENUMH; /* Frame Number High Byte */ -} USB_EP_TABLE_t; - -/* Interrupt level */ -typedef enum USB_INTLVL_enum -{ - USB_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ - USB_INTLVL_LO_gc = (0x01<<0), /* Low level */ - USB_INTLVL_MED_gc = (0x02<<0), /* Medium level */ - USB_INTLVL_HI_gc = (0x03<<0), /* High level */ -} USB_INTLVL_t; - -/* USB Endpoint Type */ -typedef enum USB_EP_TYPE_enum -{ - USB_EP_TYPE_DISABLE_gc = (0x00<<6), /* Endpoint Disabled */ - USB_EP_TYPE_CONTROL_gc = (0x01<<6), /* Control */ - USB_EP_TYPE_BULK_gc = (0x02<<6), /* Bulk/Interrupt */ - USB_EP_TYPE_ISOCHRONOUS_gc = (0x03<<6), /* Isochronous */ -} USB_EP_TYPE_t; - -/* USB Endpoint Buffersize */ -typedef enum USB_EP_BUFSIZE_enum -{ - USB_EP_BUFSIZE_8_gc = (0x00<<0), /* 8 bytes buffer size */ - USB_EP_BUFSIZE_16_gc = (0x01<<0), /* 16 bytes buffer size */ - USB_EP_BUFSIZE_32_gc = (0x02<<0), /* 32 bytes buffer size */ - USB_EP_BUFSIZE_64_gc = (0x03<<0), /* 64 bytes buffer size */ - USB_EP_BUFSIZE_128_gc = (0x04<<0), /* 128 bytes buffer size */ - USB_EP_BUFSIZE_256_gc = (0x05<<0), /* 256 bytes buffer size */ - USB_EP_BUFSIZE_512_gc = (0x06<<0), /* 512 bytes buffer size */ - USB_EP_BUFSIZE_1023_gc = (0x07<<0), /* 1023 bytes buffer size */ -} USB_EP_BUFSIZE_t; - - -/* --------------------------------------------------------------------------- -PORT - I/O Port Configuration --------------------------------------------------------------------------- -*/ - -/* I/O Ports */ -typedef struct PORT_struct -{ - register8_t DIR; /* I/O Port Data Direction */ - register8_t DIRSET; /* I/O Port Data Direction Set */ - register8_t DIRCLR; /* I/O Port Data Direction Clear */ - register8_t DIRTGL; /* I/O Port Data Direction Toggle */ - register8_t OUT; /* I/O Port Output */ - register8_t OUTSET; /* I/O Port Output Set */ - register8_t OUTCLR; /* I/O Port Output Clear */ - register8_t OUTTGL; /* I/O Port Output Toggle */ - register8_t IN; /* I/O port Input */ - register8_t INTCTRL; /* Interrupt Control Register */ - register8_t INT0MASK; /* Port Interrupt 0 Mask */ - register8_t INT1MASK; /* Port Interrupt 1 Mask */ - register8_t INTFLAGS; /* Interrupt Flag Register */ - register8_t reserved_0x0D; - register8_t REMAP; /* I/O Port Pin Remap Register */ - register8_t reserved_0x0F; - register8_t PIN0CTRL; /* Pin 0 Control Register */ - register8_t PIN1CTRL; /* Pin 1 Control Register */ - register8_t PIN2CTRL; /* Pin 2 Control Register */ - register8_t PIN3CTRL; /* Pin 3 Control Register */ - register8_t PIN4CTRL; /* Pin 4 Control Register */ - register8_t PIN5CTRL; /* Pin 5 Control Register */ - register8_t PIN6CTRL; /* Pin 6 Control Register */ - register8_t PIN7CTRL; /* Pin 7 Control Register */ -} PORT_t; - -/* Port Interrupt 0 Level */ -typedef enum PORT_INT0LVL_enum -{ - PORT_INT0LVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - PORT_INT0LVL_LO_gc = (0x01<<0), /* Low Level */ - PORT_INT0LVL_MED_gc = (0x02<<0), /* Medium Level */ - PORT_INT0LVL_HI_gc = (0x03<<0), /* High Level */ -} PORT_INT0LVL_t; - -/* Port Interrupt 1 Level */ -typedef enum PORT_INT1LVL_enum -{ - PORT_INT1LVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ - PORT_INT1LVL_LO_gc = (0x01<<2), /* Low Level */ - PORT_INT1LVL_MED_gc = (0x02<<2), /* Medium Level */ - PORT_INT1LVL_HI_gc = (0x03<<2), /* High Level */ -} PORT_INT1LVL_t; - -/* Output/Pull Configuration */ -typedef enum PORT_OPC_enum -{ - PORT_OPC_TOTEM_gc = (0x00<<3), /* Totempole */ - PORT_OPC_BUSKEEPER_gc = (0x01<<3), /* Totempole w/ Bus keeper on Input and Output */ - PORT_OPC_PULLDOWN_gc = (0x02<<3), /* Totempole w/ Pull-down on Input */ - PORT_OPC_PULLUP_gc = (0x03<<3), /* Totempole w/ Pull-up on Input */ - PORT_OPC_WIREDOR_gc = (0x04<<3), /* Wired OR */ - PORT_OPC_WIREDAND_gc = (0x05<<3), /* Wired AND */ - PORT_OPC_WIREDORPULL_gc = (0x06<<3), /* Wired OR w/ Pull-down */ - PORT_OPC_WIREDANDPULL_gc = (0x07<<3), /* Wired AND w/ Pull-up */ -} PORT_OPC_t; - -/* Input/Sense Configuration */ -typedef enum PORT_ISC_enum -{ - PORT_ISC_BOTHEDGES_gc = (0x00<<0), /* Sense Both Edges */ - PORT_ISC_RISING_gc = (0x01<<0), /* Sense Rising Edge */ - PORT_ISC_FALLING_gc = (0x02<<0), /* Sense Falling Edge */ - PORT_ISC_LEVEL_gc = (0x03<<0), /* Sense Level (Transparent For Events) */ - PORT_ISC_INPUT_DISABLE_gc = (0x07<<0), /* Disable Digital Input Buffer */ -} PORT_ISC_t; - - -/* --------------------------------------------------------------------------- -TC - 16-bit Timer/Counter With PWM --------------------------------------------------------------------------- -*/ - -/* 16-bit Timer/Counter 0 */ -typedef struct TC0_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t CTRLC; /* Control register C */ - register8_t CTRLD; /* Control Register D */ - register8_t CTRLE; /* Control Register E */ - register8_t reserved_0x05; - register8_t INTCTRLA; /* Interrupt Control Register A */ - register8_t INTCTRLB; /* Interrupt Control Register B */ - register8_t CTRLFCLR; /* Control Register F Clear */ - register8_t CTRLFSET; /* Control Register F Set */ - register8_t CTRLGCLR; /* Control Register G Clear */ - register8_t CTRLGSET; /* Control Register G Set */ - register8_t INTFLAGS; /* Interrupt Flag Register */ - register8_t reserved_0x0D; - register8_t reserved_0x0E; - register8_t TEMP; /* Temporary Register For 16-bit Access */ - register8_t reserved_0x10; - register8_t reserved_0x11; - register8_t reserved_0x12; - register8_t reserved_0x13; - register8_t reserved_0x14; - register8_t reserved_0x15; - register8_t reserved_0x16; - register8_t reserved_0x17; - register8_t reserved_0x18; - register8_t reserved_0x19; - register8_t reserved_0x1A; - register8_t reserved_0x1B; - register8_t reserved_0x1C; - register8_t reserved_0x1D; - register8_t reserved_0x1E; - register8_t reserved_0x1F; - _WORDREGISTER(CNT); /* Count */ - register8_t reserved_0x22; - register8_t reserved_0x23; - register8_t reserved_0x24; - register8_t reserved_0x25; - _WORDREGISTER(PER); /* Period */ - _WORDREGISTER(CCA); /* Compare or Capture A */ - _WORDREGISTER(CCB); /* Compare or Capture B */ - _WORDREGISTER(CCC); /* Compare or Capture C */ - _WORDREGISTER(CCD); /* Compare or Capture D */ - register8_t reserved_0x30; - register8_t reserved_0x31; - register8_t reserved_0x32; - register8_t reserved_0x33; - register8_t reserved_0x34; - register8_t reserved_0x35; - _WORDREGISTER(PERBUF); /* Period Buffer */ - _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ - _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ - _WORDREGISTER(CCCBUF); /* Compare Or Capture C Buffer */ - _WORDREGISTER(CCDBUF); /* Compare Or Capture D Buffer */ -} TC0_t; - - -/* 16-bit Timer/Counter 1 */ -typedef struct TC1_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t CTRLC; /* Control register C */ - register8_t CTRLD; /* Control Register D */ - register8_t CTRLE; /* Control Register E */ - register8_t reserved_0x05; - register8_t INTCTRLA; /* Interrupt Control Register A */ - register8_t INTCTRLB; /* Interrupt Control Register B */ - register8_t CTRLFCLR; /* Control Register F Clear */ - register8_t CTRLFSET; /* Control Register F Set */ - register8_t CTRLGCLR; /* Control Register G Clear */ - register8_t CTRLGSET; /* Control Register G Set */ - register8_t INTFLAGS; /* Interrupt Flag Register */ - register8_t reserved_0x0D; - register8_t reserved_0x0E; - register8_t TEMP; /* Temporary Register For 16-bit Access */ - register8_t reserved_0x10; - register8_t reserved_0x11; - register8_t reserved_0x12; - register8_t reserved_0x13; - register8_t reserved_0x14; - register8_t reserved_0x15; - register8_t reserved_0x16; - register8_t reserved_0x17; - register8_t reserved_0x18; - register8_t reserved_0x19; - register8_t reserved_0x1A; - register8_t reserved_0x1B; - register8_t reserved_0x1C; - register8_t reserved_0x1D; - register8_t reserved_0x1E; - register8_t reserved_0x1F; - _WORDREGISTER(CNT); /* Count */ - register8_t reserved_0x22; - register8_t reserved_0x23; - register8_t reserved_0x24; - register8_t reserved_0x25; - _WORDREGISTER(PER); /* Period */ - _WORDREGISTER(CCA); /* Compare or Capture A */ - _WORDREGISTER(CCB); /* Compare or Capture B */ - register8_t reserved_0x2C; - register8_t reserved_0x2D; - register8_t reserved_0x2E; - register8_t reserved_0x2F; - register8_t reserved_0x30; - register8_t reserved_0x31; - register8_t reserved_0x32; - register8_t reserved_0x33; - register8_t reserved_0x34; - register8_t reserved_0x35; - _WORDREGISTER(PERBUF); /* Period Buffer */ - _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ - _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ -} TC1_t; - -/* Clock Selection */ -typedef enum TC_CLKSEL_enum -{ - TC_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */ - TC_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */ - TC_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */ - TC_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */ - TC_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */ - TC_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */ - TC_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */ - TC_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */ - TC_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */ - TC_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */ - TC_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */ - TC_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */ -} TC_CLKSEL_t; - -/* Waveform Generation Mode */ -typedef enum TC_WGMODE_enum -{ - TC_WGMODE_NORMAL_gc = (0x00<<0), /* Normal Mode */ - TC_WGMODE_FRQ_gc = (0x01<<0), /* Frequency Generation Mode */ - TC_WGMODE_SINGLESLOPE_gc = (0x03<<0), /* Single Slope */ - TC_WGMODE_SS_gc = (0x03<<0), /* Single Slope */ - TC_WGMODE_DSTOP_gc = (0x05<<0), /* Dual Slope, Update on TOP */ - TC_WGMODE_DS_T_gc = (0x05<<0), /* Dual Slope, Update on TOP */ - TC_WGMODE_DSBOTH_gc = (0x06<<0), /* Dual Slope, Update on both TOP and BOTTOM */ - TC_WGMODE_DS_TB_gc = (0x06<<0), /* Dual Slope, Update on both TOP and BOTTOM */ - TC_WGMODE_DSBOTTOM_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */ - TC_WGMODE_DS_B_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */ -} TC_WGMODE_t; - -/* Byte Mode */ -typedef enum TC_BYTEM_enum -{ - TC_BYTEM_NORMAL_gc = (0x00<<0), /* 16-bit mode */ - TC_BYTEM_BYTEMODE_gc = (0x01<<0), /* Timer/Counter operating in byte mode only */ - TC_BYTEM_SPLITMODE_gc = (0x02<<0), /* Timer/Counter split into two 8-bit Counters (TC2) */ -} TC_BYTEM_t; - -/* Event Action */ -typedef enum TC_EVACT_enum -{ - TC_EVACT_OFF_gc = (0x00<<5), /* No Event Action */ - TC_EVACT_CAPT_gc = (0x01<<5), /* Input Capture */ - TC_EVACT_UPDOWN_gc = (0x02<<5), /* Externally Controlled Up/Down Count */ - TC_EVACT_QDEC_gc = (0x03<<5), /* Quadrature Decode */ - TC_EVACT_RESTART_gc = (0x04<<5), /* Restart */ - TC_EVACT_FRQ_gc = (0x05<<5), /* Frequency Capture */ - TC_EVACT_PW_gc = (0x06<<5), /* Pulse-width Capture */ -} TC_EVACT_t; - -/* Event Selection */ -typedef enum TC_EVSEL_enum -{ - TC_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ - TC_EVSEL_CH0_gc = (0x08<<0), /* Event Channel 0 */ - TC_EVSEL_CH1_gc = (0x09<<0), /* Event Channel 1 */ - TC_EVSEL_CH2_gc = (0x0A<<0), /* Event Channel 2 */ - TC_EVSEL_CH3_gc = (0x0B<<0), /* Event Channel 3 */ -} TC_EVSEL_t; - -/* Error Interrupt Level */ -typedef enum TC_ERRINTLVL_enum -{ - TC_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ - TC_ERRINTLVL_LO_gc = (0x01<<2), /* Low Level */ - TC_ERRINTLVL_MED_gc = (0x02<<2), /* Medium Level */ - TC_ERRINTLVL_HI_gc = (0x03<<2), /* High Level */ -} TC_ERRINTLVL_t; - -/* Overflow Interrupt Level */ -typedef enum TC_OVFINTLVL_enum -{ - TC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - TC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ - TC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ - TC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ -} TC_OVFINTLVL_t; - -/* Compare or Capture D Interrupt Level */ -typedef enum TC_CCDINTLVL_enum -{ - TC_CCDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ - TC_CCDINTLVL_LO_gc = (0x01<<6), /* Low Level */ - TC_CCDINTLVL_MED_gc = (0x02<<6), /* Medium Level */ - TC_CCDINTLVL_HI_gc = (0x03<<6), /* High Level */ -} TC_CCDINTLVL_t; - -/* Compare or Capture C Interrupt Level */ -typedef enum TC_CCCINTLVL_enum -{ - TC_CCCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ - TC_CCCINTLVL_LO_gc = (0x01<<4), /* Low Level */ - TC_CCCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ - TC_CCCINTLVL_HI_gc = (0x03<<4), /* High Level */ -} TC_CCCINTLVL_t; - -/* Compare or Capture B Interrupt Level */ -typedef enum TC_CCBINTLVL_enum -{ - TC_CCBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ - TC_CCBINTLVL_LO_gc = (0x01<<2), /* Low Level */ - TC_CCBINTLVL_MED_gc = (0x02<<2), /* Medium Level */ - TC_CCBINTLVL_HI_gc = (0x03<<2), /* High Level */ -} TC_CCBINTLVL_t; - -/* Compare or Capture A Interrupt Level */ -typedef enum TC_CCAINTLVL_enum -{ - TC_CCAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - TC_CCAINTLVL_LO_gc = (0x01<<0), /* Low Level */ - TC_CCAINTLVL_MED_gc = (0x02<<0), /* Medium Level */ - TC_CCAINTLVL_HI_gc = (0x03<<0), /* High Level */ -} TC_CCAINTLVL_t; - -/* Timer/Counter Command */ -typedef enum TC_CMD_enum -{ - TC_CMD_NONE_gc = (0x00<<2), /* No Command */ - TC_CMD_UPDATE_gc = (0x01<<2), /* Force Update */ - TC_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ - TC_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ -} TC_CMD_t; - - -/* --------------------------------------------------------------------------- -TC2 - 16-bit Timer/Counter type 2 --------------------------------------------------------------------------- -*/ - -/* 16-bit Timer/Counter type 2 */ -typedef struct TC2_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t CTRLC; /* Control register C */ - register8_t reserved_0x03; - register8_t CTRLE; /* Control Register E */ - register8_t reserved_0x05; - register8_t INTCTRLA; /* Interrupt Control Register A */ - register8_t INTCTRLB; /* Interrupt Control Register B */ - register8_t reserved_0x08; - register8_t CTRLF; /* Control Register F */ - register8_t reserved_0x0A; - register8_t reserved_0x0B; - register8_t INTFLAGS; /* Interrupt Flag Register */ - register8_t reserved_0x0D; - register8_t reserved_0x0E; - register8_t reserved_0x0F; - register8_t reserved_0x10; - register8_t reserved_0x11; - register8_t reserved_0x12; - register8_t reserved_0x13; - register8_t reserved_0x14; - register8_t reserved_0x15; - register8_t reserved_0x16; - register8_t reserved_0x17; - register8_t reserved_0x18; - register8_t reserved_0x19; - register8_t reserved_0x1A; - register8_t reserved_0x1B; - register8_t reserved_0x1C; - register8_t reserved_0x1D; - register8_t reserved_0x1E; - register8_t reserved_0x1F; - register8_t LCNT; /* Low Byte Count */ - register8_t HCNT; /* High Byte Count */ - register8_t reserved_0x22; - register8_t reserved_0x23; - register8_t reserved_0x24; - register8_t reserved_0x25; - register8_t LPER; /* Low Byte Period */ - register8_t HPER; /* High Byte Period */ - register8_t LCMPA; /* Low Byte Compare A */ - register8_t HCMPA; /* High Byte Compare A */ - register8_t LCMPB; /* Low Byte Compare B */ - register8_t HCMPB; /* High Byte Compare B */ - register8_t LCMPC; /* Low Byte Compare C */ - register8_t HCMPC; /* High Byte Compare C */ - register8_t LCMPD; /* Low Byte Compare D */ - register8_t HCMPD; /* High Byte Compare D */ -} TC2_t; - -/* Clock Selection */ -typedef enum TC2_CLKSEL_enum -{ - TC2_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */ - TC2_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */ - TC2_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */ - TC2_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */ - TC2_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */ - TC2_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */ - TC2_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */ - TC2_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */ - TC2_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */ - TC2_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */ - TC2_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */ - TC2_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */ -} TC2_CLKSEL_t; - -/* Byte Mode */ -typedef enum TC2_BYTEM_enum -{ - TC2_BYTEM_NORMAL_gc = (0x00<<0), /* 16-bit mode */ - TC2_BYTEM_BYTEMODE_gc = (0x01<<0), /* Timer/Counter operating in byte mode only (TC2) */ - TC2_BYTEM_SPLITMODE_gc = (0x02<<0), /* Timer/Counter split into two 8-bit Counters */ -} TC2_BYTEM_t; - -/* High Byte Underflow Interrupt Level */ -typedef enum TC2_HUNFINTLVL_enum -{ - TC2_HUNFINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ - TC2_HUNFINTLVL_LO_gc = (0x01<<2), /* Low Level */ - TC2_HUNFINTLVL_MED_gc = (0x02<<2), /* Medium Level */ - TC2_HUNFINTLVL_HI_gc = (0x03<<2), /* High Level */ -} TC2_HUNFINTLVL_t; - -/* Low Byte Underflow Interrupt Level */ -typedef enum TC2_LUNFINTLVL_enum -{ - TC2_LUNFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - TC2_LUNFINTLVL_LO_gc = (0x01<<0), /* Low Level */ - TC2_LUNFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ - TC2_LUNFINTLVL_HI_gc = (0x03<<0), /* High Level */ -} TC2_LUNFINTLVL_t; - -/* Low Byte Compare D Interrupt Level */ -typedef enum TC2_LCMPDINTLVL_enum -{ - TC2_LCMPDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ - TC2_LCMPDINTLVL_LO_gc = (0x01<<6), /* Low Level */ - TC2_LCMPDINTLVL_MED_gc = (0x02<<6), /* Medium Level */ - TC2_LCMPDINTLVL_HI_gc = (0x03<<6), /* High Level */ -} TC2_LCMPDINTLVL_t; - -/* Low Byte Compare C Interrupt Level */ -typedef enum TC2_LCMPCINTLVL_enum -{ - TC2_LCMPCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ - TC2_LCMPCINTLVL_LO_gc = (0x01<<4), /* Low Level */ - TC2_LCMPCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ - TC2_LCMPCINTLVL_HI_gc = (0x03<<4), /* High Level */ -} TC2_LCMPCINTLVL_t; - -/* Low Byte Compare B Interrupt Level */ -typedef enum TC2_LCMPBINTLVL_enum -{ - TC2_LCMPBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ - TC2_LCMPBINTLVL_LO_gc = (0x01<<2), /* Low Level */ - TC2_LCMPBINTLVL_MED_gc = (0x02<<2), /* Medium Level */ - TC2_LCMPBINTLVL_HI_gc = (0x03<<2), /* High Level */ -} TC2_LCMPBINTLVL_t; - -/* Low Byte Compare A Interrupt Level */ -typedef enum TC2_LCMPAINTLVL_enum -{ - TC2_LCMPAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - TC2_LCMPAINTLVL_LO_gc = (0x01<<0), /* Low Level */ - TC2_LCMPAINTLVL_MED_gc = (0x02<<0), /* Medium Level */ - TC2_LCMPAINTLVL_HI_gc = (0x03<<0), /* High Level */ -} TC2_LCMPAINTLVL_t; - -/* Timer/Counter Command */ -typedef enum TC2_CMD_enum -{ - TC2_CMD_NONE_gc = (0x00<<2), /* No Command */ - TC2_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ - TC2_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ -} TC2_CMD_t; - -/* Timer/Counter Command */ -typedef enum TC2_CMDEN_enum -{ - TC2_CMDEN_LOW_gc = (0x01<<0), /* Low Byte Timer/Counter */ - TC2_CMDEN_HIGH_gc = (0x02<<0), /* High Byte Timer/Counter */ - TC2_CMDEN_BOTH_gc = (0x03<<0), /* Both Low Byte and High Byte Timer/Counters */ -} TC2_CMDEN_t; - - -/* --------------------------------------------------------------------------- -AWEX - Timer/Counter Advanced Waveform Extension --------------------------------------------------------------------------- -*/ - -/* Advanced Waveform Extension */ -typedef struct AWEX_struct -{ - register8_t CTRL; /* Control Register */ - register8_t reserved_0x01; - register8_t FDEMASK; /* Fault Detection Event Mask */ - register8_t FDCTRL; /* Fault Detection Control Register */ - register8_t STATUS; /* Status Register */ - register8_t STATUSSET; /* Status Set Register */ - register8_t DTBOTH; /* Dead Time Both Sides */ - register8_t DTBOTHBUF; /* Dead Time Both Sides Buffer */ - register8_t DTLS; /* Dead Time Low Side */ - register8_t DTHS; /* Dead Time High Side */ - register8_t DTLSBUF; /* Dead Time Low Side Buffer */ - register8_t DTHSBUF; /* Dead Time High Side Buffer */ - register8_t OUTOVEN; /* Output Override Enable */ -} AWEX_t; - -/* Fault Detect Action */ -typedef enum AWEX_FDACT_enum -{ - AWEX_FDACT_NONE_gc = (0x00<<0), /* No Fault Protection */ - AWEX_FDACT_CLEAROE_gc = (0x01<<0), /* Clear Output Enable Bits */ - AWEX_FDACT_CLEARDIR_gc = (0x03<<0), /* Clear I/O Port Direction Bits */ -} AWEX_FDACT_t; - - -/* --------------------------------------------------------------------------- -HIRES - Timer/Counter High-Resolution Extension --------------------------------------------------------------------------- -*/ - -/* High-Resolution Extension */ -typedef struct HIRES_struct -{ - register8_t CTRLA; /* Control Register */ -} HIRES_t; - -/* High Resolution Enable */ -typedef enum HIRES_HREN_enum -{ - HIRES_HREN_NONE_gc = (0x00<<0), /* No Fault Protection */ - HIRES_HREN_TC0_gc = (0x01<<0), /* Enable High Resolution on Timer/Counter 0 */ - HIRES_HREN_TC1_gc = (0x02<<0), /* Enable High Resolution on Timer/Counter 1 */ - HIRES_HREN_BOTH_gc = (0x03<<0), /* Enable High Resolution both Timer/Counters */ -} HIRES_HREN_t; - - -/* --------------------------------------------------------------------------- -USART - Universal Asynchronous Receiver-Transmitter --------------------------------------------------------------------------- -*/ - -/* Universal Synchronous/Asynchronous Receiver/Transmitter */ -typedef struct USART_struct -{ - register8_t DATA; /* Data Register */ - register8_t STATUS; /* Status Register */ - register8_t reserved_0x02; - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t CTRLC; /* Control Register C */ - register8_t BAUDCTRLA; /* Baud Rate Control Register A */ - register8_t BAUDCTRLB; /* Baud Rate Control Register B */ -} USART_t; - -/* Receive Complete Interrupt level */ -typedef enum USART_RXCINTLVL_enum -{ - USART_RXCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ - USART_RXCINTLVL_LO_gc = (0x01<<4), /* Low Level */ - USART_RXCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ - USART_RXCINTLVL_HI_gc = (0x03<<4), /* High Level */ -} USART_RXCINTLVL_t; - -/* Transmit Complete Interrupt level */ -typedef enum USART_TXCINTLVL_enum -{ - USART_TXCINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ - USART_TXCINTLVL_LO_gc = (0x01<<2), /* Low Level */ - USART_TXCINTLVL_MED_gc = (0x02<<2), /* Medium Level */ - USART_TXCINTLVL_HI_gc = (0x03<<2), /* High Level */ -} USART_TXCINTLVL_t; - -/* Data Register Empty Interrupt level */ -typedef enum USART_DREINTLVL_enum -{ - USART_DREINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - USART_DREINTLVL_LO_gc = (0x01<<0), /* Low Level */ - USART_DREINTLVL_MED_gc = (0x02<<0), /* Medium Level */ - USART_DREINTLVL_HI_gc = (0x03<<0), /* High Level */ -} USART_DREINTLVL_t; - -/* Character Size */ -typedef enum USART_CHSIZE_enum -{ - USART_CHSIZE_5BIT_gc = (0x00<<0), /* Character size: 5 bit */ - USART_CHSIZE_6BIT_gc = (0x01<<0), /* Character size: 6 bit */ - USART_CHSIZE_7BIT_gc = (0x02<<0), /* Character size: 7 bit */ - USART_CHSIZE_8BIT_gc = (0x03<<0), /* Character size: 8 bit */ - USART_CHSIZE_9BIT_gc = (0x07<<0), /* Character size: 9 bit */ -} USART_CHSIZE_t; - -/* Communication Mode */ -typedef enum USART_CMODE_enum -{ - USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6), /* Asynchronous Mode */ - USART_CMODE_SYNCHRONOUS_gc = (0x01<<6), /* Synchronous Mode */ - USART_CMODE_IRDA_gc = (0x02<<6), /* IrDA Mode */ - USART_CMODE_MSPI_gc = (0x03<<6), /* Master SPI Mode */ -} USART_CMODE_t; - -/* Parity Mode */ -typedef enum USART_PMODE_enum -{ - USART_PMODE_DISABLED_gc = (0x00<<4), /* No Parity */ - USART_PMODE_EVEN_gc = (0x02<<4), /* Even Parity */ - USART_PMODE_ODD_gc = (0x03<<4), /* Odd Parity */ -} USART_PMODE_t; - - -/* --------------------------------------------------------------------------- -SPI - Serial Peripheral Interface --------------------------------------------------------------------------- -*/ - -/* Serial Peripheral Interface */ -typedef struct SPI_struct -{ - register8_t CTRL; /* Control Register */ - register8_t INTCTRL; /* Interrupt Control Register */ - register8_t STATUS; /* Status Register */ - register8_t DATA; /* Data Register */ -} SPI_t; - -/* SPI Mode */ -typedef enum SPI_MODE_enum -{ - SPI_MODE_0_gc = (0x00<<2), /* SPI Mode 0 */ - SPI_MODE_1_gc = (0x01<<2), /* SPI Mode 1 */ - SPI_MODE_2_gc = (0x02<<2), /* SPI Mode 2 */ - SPI_MODE_3_gc = (0x03<<2), /* SPI Mode 3 */ -} SPI_MODE_t; - -/* Prescaler setting */ -typedef enum SPI_PRESCALER_enum -{ - SPI_PRESCALER_DIV4_gc = (0x00<<0), /* System Clock / 4 */ - SPI_PRESCALER_DIV16_gc = (0x01<<0), /* System Clock / 16 */ - SPI_PRESCALER_DIV64_gc = (0x02<<0), /* System Clock / 64 */ - SPI_PRESCALER_DIV128_gc = (0x03<<0), /* System Clock / 128 */ -} SPI_PRESCALER_t; - -/* Interrupt level */ -typedef enum SPI_INTLVL_enum -{ - SPI_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - SPI_INTLVL_LO_gc = (0x01<<0), /* Low Level */ - SPI_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ - SPI_INTLVL_HI_gc = (0x03<<0), /* High Level */ -} SPI_INTLVL_t; - - -/* --------------------------------------------------------------------------- -IRCOM - IR Communication Module --------------------------------------------------------------------------- -*/ - -/* IR Communication Module */ -typedef struct IRCOM_struct -{ - register8_t CTRL; /* Control Register */ - register8_t TXPLCTRL; /* IrDA Transmitter Pulse Length Control Register */ - register8_t RXPLCTRL; /* IrDA Receiver Pulse Length Control Register */ -} IRCOM_t; - -/* Event channel selection */ -typedef enum IRDA_EVSEL_enum -{ - IRDA_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ - IRDA_EVSEL_0_gc = (0x08<<0), /* Event Channel 0 */ - IRDA_EVSEL_1_gc = (0x09<<0), /* Event Channel 1 */ - IRDA_EVSEL_2_gc = (0x0A<<0), /* Event Channel 2 */ - IRDA_EVSEL_3_gc = (0x0B<<0), /* Event Channel 3 */ -} IRDA_EVSEL_t; - - -/* --------------------------------------------------------------------------- -FUSE - Fuses and Lockbits --------------------------------------------------------------------------- -*/ - -/* Fuses */ -typedef struct NVM_FUSES_struct -{ - register8_t reserved_0x00; - register8_t FUSEBYTE1; /* Watchdog Configuration */ - register8_t FUSEBYTE2; /* Reset Configuration */ - register8_t reserved_0x03; - register8_t FUSEBYTE4; /* Start-up Configuration */ - register8_t FUSEBYTE5; /* EESAVE and BOD Level */ -} NVM_FUSES_t; - -/* Boot Loader Section Reset Vector */ -typedef enum BOOTRST_enum -{ - BOOTRST_BOOTLDR_gc = (0x00<<6), /* Boot Loader Reset */ - BOOTRST_APPLICATION_gc = (0x01<<6), /* Application Reset */ -} BOOTRST_t; - -/* Timer Oscillator pin location */ -typedef enum TOSCSEL_enum -{ - TOSCSEL_ALTERNATE_gc = (0x00<<5), /* TOSC1 / TOSC2 on separate pins */ - TOSCSEL_XTAL_gc = (0x01<<5), /* TOSC1 / TOSC2 shared with XTAL1 / XTAL2 */ -} TOSCSEL_t; - -/* BOD operation */ -typedef enum BOD_enum -{ - BOD_SAMPLED_gc = (0x01<<0), /* BOD enabled in sampled mode */ - BOD_CONTINUOUS_gc = (0x02<<0), /* BOD enabled continuously */ - BOD_DISABLED_gc = (0x03<<0), /* BOD Disabled */ -} BOD_t; - -/* BOD operation */ -typedef enum BODACT_enum -{ - BODACT_SAMPLED_gc = (0x01<<4), /* BOD enabled in sampled mode */ - BODACT_CONTINUOUS_gc = (0x02<<4), /* BOD enabled continuously */ - BODACT_DISABLED_gc = (0x03<<4), /* BOD Disabled */ -} BODACT_t; - -/* Watchdog (Window) Timeout Period */ -typedef enum WD_enum -{ - WD_8CLK_gc = (0x00<<4), /* 8 cycles (8ms @ 3.3V) */ - WD_16CLK_gc = (0x01<<4), /* 16 cycles (16ms @ 3.3V) */ - WD_32CLK_gc = (0x02<<4), /* 32 cycles (32ms @ 3.3V) */ - WD_64CLK_gc = (0x03<<4), /* 64 cycles (64ms @ 3.3V) */ - WD_128CLK_gc = (0x04<<4), /* 128 cycles (0.125s @ 3.3V) */ - WD_256CLK_gc = (0x05<<4), /* 256 cycles (0.25s @ 3.3V) */ - WD_512CLK_gc = (0x06<<4), /* 512 cycles (0.5s @ 3.3V) */ - WD_1KCLK_gc = (0x07<<4), /* 1K cycles (1s @ 3.3V) */ - WD_2KCLK_gc = (0x08<<4), /* 2K cycles (2s @ 3.3V) */ - WD_4KCLK_gc = (0x09<<4), /* 4K cycles (4s @ 3.3V) */ - WD_8KCLK_gc = (0x0A<<4), /* 8K cycles (8s @ 3.3V) */ -} WD_t; - -/* Watchdog (Window) Timeout Period */ -typedef enum WDP_enum -{ - WDP_8CLK_gc = (0x00<<0), /* 8 cycles (8ms @ 3.3V) */ - WDP_16CLK_gc = (0x01<<0), /* 16 cycles (16ms @ 3.3V) */ - WDP_32CLK_gc = (0x02<<0), /* 32 cycles (32ms @ 3.3V) */ - WDP_64CLK_gc = (0x03<<0), /* 64 cycles (64ms @ 3.3V) */ - WDP_128CLK_gc = (0x04<<0), /* 128 cycles (0.125s @ 3.3V) */ - WDP_256CLK_gc = (0x05<<0), /* 256 cycles (0.25s @ 3.3V) */ - WDP_512CLK_gc = (0x06<<0), /* 512 cycles (0.5s @ 3.3V) */ - WDP_1KCLK_gc = (0x07<<0), /* 1K cycles (1s @ 3.3V) */ - WDP_2KCLK_gc = (0x08<<0), /* 2K cycles (2s @ 3.3V) */ - WDP_4KCLK_gc = (0x09<<0), /* 4K cycles (4s @ 3.3V) */ - WDP_8KCLK_gc = (0x0A<<0), /* 8K cycles (8s @ 3.3V) */ -} WDP_t; - -/* Start-up Time */ -typedef enum SUT_enum -{ - SUT_0MS_gc = (0x03<<2), /* 0 ms */ - SUT_4MS_gc = (0x01<<2), /* 4 ms */ - SUT_64MS_gc = (0x00<<2), /* 64 ms */ -} SUT_t; - -/* Brownout Detection Voltage Level */ -typedef enum BODLVL_enum -{ - BODLVL_1V6_gc = (0x07<<0), /* 1.6 V */ - BODLVL_1V8_gc = (0x06<<0), /* 1.8 V */ - BODLVL_2V0_gc = (0x05<<0), /* 2.0 V */ - BODLVL_2V2_gc = (0x04<<0), /* 2.2 V */ - BODLVL_2V4_gc = (0x03<<0), /* 2.4 V */ - BODLVL_2V6_gc = (0x02<<0), /* 2.6 V */ - BODLVL_2V8_gc = (0x01<<0), /* 2.8 V */ - BODLVL_3V0_gc = (0x00<<0), /* 3.0 V */ -} BODLVL_t; - - -/* --------------------------------------------------------------------------- -LOCKBIT - Fuses and Lockbits --------------------------------------------------------------------------- -*/ - -/* Lock Bits */ -typedef struct NVM_LOCKBITS_struct -{ - register8_t LOCK_BITS; /* Lock Bits (Changed from LOCKBITS to avoid avr-libc collision) */ -} NVM_LOCKBITS_t; - -/* Boot lock bits - boot setcion */ -typedef enum FUSE_BLBB_enum -{ - FUSE_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ - FUSE_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ - FUSE_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ - FUSE_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ -} FUSE_BLBB_t; - -/* Boot lock bits - application section */ -typedef enum FUSE_BLBA_enum -{ - FUSE_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ - FUSE_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ - FUSE_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ - FUSE_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ -} FUSE_BLBA_t; - -/* Boot lock bits - application table section */ -typedef enum FUSE_BLBAT_enum -{ - FUSE_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ - FUSE_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ - FUSE_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ - FUSE_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ -} FUSE_BLBAT_t; - -/* Lock bits */ -typedef enum FUSE_LB_enum -{ - FUSE_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ - FUSE_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ - FUSE_LB_NOLOCK_gc = (0x03<<0), /* No locks */ -} FUSE_LB_t; - - -/* --------------------------------------------------------------------------- -SIGROW - Signature Row --------------------------------------------------------------------------- -*/ - -/* Production Signatures */ -typedef struct NVM_PROD_SIGNATURES_struct -{ - register8_t RCOSC2M; /* RCOSC 2 MHz Calibration Value B */ - register8_t RCOSC2MA; /* RCOSC 2 MHz Calibration Value A */ - register8_t RCOSC32K; /* RCOSC 32.768 kHz Calibration Value */ - register8_t RCOSC32M; /* RCOSC 32 MHz Calibration Value B */ - register8_t RCOSC32MA; /* RCOSC 32 MHz Calibration Value A */ - register8_t reserved_0x05; - register8_t reserved_0x06; - register8_t reserved_0x07; - register8_t LOTNUM0; /* Lot Number Byte 0, ASCII */ - register8_t LOTNUM1; /* Lot Number Byte 1, ASCII */ - register8_t LOTNUM2; /* Lot Number Byte 2, ASCII */ - register8_t LOTNUM3; /* Lot Number Byte 3, ASCII */ - register8_t LOTNUM4; /* Lot Number Byte 4, ASCII */ - register8_t LOTNUM5; /* Lot Number Byte 5, ASCII */ - register8_t reserved_0x0E; - register8_t reserved_0x0F; - register8_t WAFNUM; /* Wafer Number */ - register8_t reserved_0x11; - register8_t COORDX0; /* Wafer Coordinate X Byte 0 */ - register8_t COORDX1; /* Wafer Coordinate X Byte 1 */ - register8_t COORDY0; /* Wafer Coordinate Y Byte 0 */ - register8_t COORDY1; /* Wafer Coordinate Y Byte 1 */ - register8_t reserved_0x16; - register8_t reserved_0x17; - register8_t reserved_0x18; - register8_t reserved_0x19; - register8_t USBCAL0; /* USB Calibration Byte 0 */ - register8_t USBCAL1; /* USB Calibration Byte 1 */ - register8_t USBRCOSC; /* USB RCOSC Calibration Value B */ - register8_t USBRCOSCA; /* USB RCOSC Calibration Value A */ - register8_t reserved_0x1E; - register8_t reserved_0x1F; - register8_t ADCACAL0; /* ADCA Calibration Byte 0 */ - register8_t ADCACAL1; /* ADCA Calibration Byte 1 */ - register8_t reserved_0x22; - register8_t reserved_0x23; - register8_t reserved_0x24; - register8_t reserved_0x25; - register8_t reserved_0x26; - register8_t reserved_0x27; - register8_t reserved_0x28; - register8_t reserved_0x29; - register8_t reserved_0x2A; - register8_t reserved_0x2B; - register8_t reserved_0x2C; - register8_t reserved_0x2D; - register8_t TEMPSENSE0; /* Temperature Sensor Calibration Byte 0 */ - register8_t TEMPSENSE1; /* Temperature Sensor Calibration Byte 1 */ - register8_t reserved_0x30; - register8_t reserved_0x31; - register8_t reserved_0x32; - register8_t reserved_0x33; - register8_t reserved_0x34; - register8_t reserved_0x35; - register8_t reserved_0x36; - register8_t reserved_0x37; - register8_t reserved_0x38; - register8_t reserved_0x39; - register8_t reserved_0x3A; - register8_t reserved_0x3B; - register8_t reserved_0x3C; - register8_t reserved_0x3D; - register8_t reserved_0x3E; - register8_t reserved_0x3F; -} NVM_PROD_SIGNATURES_t; - -/* -========================================================================== -IO Module Instances. Mapped to memory. -========================================================================== -*/ - -#define VPORT0 (*(VPORT_t *) 0x0010) /* Virtual Port */ -#define VPORT1 (*(VPORT_t *) 0x0014) /* Virtual Port */ -#define VPORT2 (*(VPORT_t *) 0x0018) /* Virtual Port */ -#define VPORT3 (*(VPORT_t *) 0x001C) /* Virtual Port */ -#define OCD (*(OCD_t *) 0x002E) /* On-Chip Debug System */ -#define CLK (*(CLK_t *) 0x0040) /* Clock System */ -#define SLEEP (*(SLEEP_t *) 0x0048) /* Sleep Controller */ -#define OSC (*(OSC_t *) 0x0050) /* Oscillator */ -#define DFLLRC32M (*(DFLL_t *) 0x0060) /* DFLL */ -#define DFLLRC2M (*(DFLL_t *) 0x0068) /* DFLL */ -#define PR (*(PR_t *) 0x0070) /* Power Reduction */ -#define RST (*(RST_t *) 0x0078) /* Reset */ -#define WDT (*(WDT_t *) 0x0080) /* Watch-Dog Timer */ -#define MCU (*(MCU_t *) 0x0090) /* MCU Control */ -#define PMIC (*(PMIC_t *) 0x00A0) /* Programmable Multi-level Interrupt Controller */ -#define PORTCFG (*(PORTCFG_t *) 0x00B0) /* I/O port Configuration */ -#define CRC (*(CRC_t *) 0x00D0) /* Cyclic Redundancy Checker */ -#define EVSYS (*(EVSYS_t *) 0x0180) /* Event System */ -#define NVM (*(NVM_t *) 0x01C0) /* Non-volatile Memory Controller */ -#define ADCA (*(ADC_t *) 0x0200) /* Analog-to-Digital Converter */ -#define ACA (*(AC_t *) 0x0380) /* Analog Comparator */ -#define RTC (*(RTC_t *) 0x0400) /* Real-Time Counter */ -#define TWIC (*(TWI_t *) 0x0480) /* Two-Wire Interface */ -#define TWIE (*(TWI_t *) 0x04A0) /* Two-Wire Interface */ -#define USB (*(USB_t *) 0x04C0) /* Universal Serial Bus */ -#define PORTA (*(PORT_t *) 0x0600) /* I/O Ports */ -#define PORTB (*(PORT_t *) 0x0620) /* I/O Ports */ -#define PORTC (*(PORT_t *) 0x0640) /* I/O Ports */ -#define PORTD (*(PORT_t *) 0x0660) /* I/O Ports */ -#define PORTE (*(PORT_t *) 0x0680) /* I/O Ports */ -#define PORTR (*(PORT_t *) 0x07E0) /* I/O Ports */ -#define TCC0 (*(TC0_t *) 0x0800) /* 16-bit Timer/Counter 0 */ -#define TCC2 (*(TC2_t *) 0x0800) /* 16-bit Timer/Counter type 2 */ -#define TCC1 (*(TC1_t *) 0x0840) /* 16-bit Timer/Counter 1 */ -#define AWEXC (*(AWEX_t *) 0x0880) /* Advanced Waveform Extension */ -#define HIRESC (*(HIRES_t *) 0x0890) /* High-Resolution Extension */ -#define USARTC0 (*(USART_t *) 0x08A0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ -#define USARTC1 (*(USART_t *) 0x08B0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ -#define SPIC (*(SPI_t *) 0x08C0) /* Serial Peripheral Interface */ -#define IRCOM (*(IRCOM_t *) 0x08F8) /* IR Communication Module */ -#define TCD0 (*(TC0_t *) 0x0900) /* 16-bit Timer/Counter 0 */ -#define TCD2 (*(TC2_t *) 0x0900) /* 16-bit Timer/Counter type 2 */ -#define USARTD0 (*(USART_t *) 0x09A0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ -#define SPID (*(SPI_t *) 0x09C0) /* Serial Peripheral Interface */ -#define TCE0 (*(TC0_t *) 0x0A00) /* 16-bit Timer/Counter 0 */ - - -#endif /* !defined (__ASSEMBLER__) */ - - -/* ========== Flattened fully qualified IO register names ========== */ - -/* GPIO - General Purpose IO Registers */ -#define GPIO_GPIOR0 _SFR_MEM8(0x0000) -#define GPIO_GPIOR1 _SFR_MEM8(0x0001) -#define GPIO_GPIOR2 _SFR_MEM8(0x0002) -#define GPIO_GPIOR3 _SFR_MEM8(0x0003) - -/* Deprecated */ -#define GPIO_GPIO0 _SFR_MEM8(0x0000) -#define GPIO_GPIO1 _SFR_MEM8(0x0001) -#define GPIO_GPIO2 _SFR_MEM8(0x0002) -#define GPIO_GPIO3 _SFR_MEM8(0x0003) - -/* NVM_FUSES - Fuses */ -#define FUSE_FUSEBYTE1 _SFR_MEM8(0x0001) -#define FUSE_FUSEBYTE2 _SFR_MEM8(0x0002) -#define FUSE_FUSEBYTE4 _SFR_MEM8(0x0004) -#define FUSE_FUSEBYTE5 _SFR_MEM8(0x0005) - -/* NVM_LOCKBITS - Lock Bits */ -#define LOCKBIT_LOCKBITS _SFR_MEM8(0x0000) - -/* NVM_PROD_SIGNATURES - Production Signatures */ -#define PRODSIGNATURES_RCOSC2M _SFR_MEM8(0x0000) -#define PRODSIGNATURES_RCOSC2MA _SFR_MEM8(0x0001) -#define PRODSIGNATURES_RCOSC32K _SFR_MEM8(0x0002) -#define PRODSIGNATURES_RCOSC32M _SFR_MEM8(0x0003) -#define PRODSIGNATURES_RCOSC32MA _SFR_MEM8(0x0004) -#define PRODSIGNATURES_LOTNUM0 _SFR_MEM8(0x0008) -#define PRODSIGNATURES_LOTNUM1 _SFR_MEM8(0x0009) -#define PRODSIGNATURES_LOTNUM2 _SFR_MEM8(0x000A) -#define PRODSIGNATURES_LOTNUM3 _SFR_MEM8(0x000B) -#define PRODSIGNATURES_LOTNUM4 _SFR_MEM8(0x000C) -#define PRODSIGNATURES_LOTNUM5 _SFR_MEM8(0x000D) -#define PRODSIGNATURES_WAFNUM _SFR_MEM8(0x0010) -#define PRODSIGNATURES_COORDX0 _SFR_MEM8(0x0012) -#define PRODSIGNATURES_COORDX1 _SFR_MEM8(0x0013) -#define PRODSIGNATURES_COORDY0 _SFR_MEM8(0x0014) -#define PRODSIGNATURES_COORDY1 _SFR_MEM8(0x0015) -#define PRODSIGNATURES_USBCAL0 _SFR_MEM8(0x001A) -#define PRODSIGNATURES_USBCAL1 _SFR_MEM8(0x001B) -#define PRODSIGNATURES_USBRCOSC _SFR_MEM8(0x001C) -#define PRODSIGNATURES_USBRCOSCA _SFR_MEM8(0x001D) -#define PRODSIGNATURES_ADCACAL0 _SFR_MEM8(0x0020) -#define PRODSIGNATURES_ADCACAL1 _SFR_MEM8(0x0021) -#define PRODSIGNATURES_TEMPSENSE0 _SFR_MEM8(0x002E) -#define PRODSIGNATURES_TEMPSENSE1 _SFR_MEM8(0x002F) - -/* VPORT - Virtual Port */ -#define VPORT0_DIR _SFR_MEM8(0x0010) -#define VPORT0_OUT _SFR_MEM8(0x0011) -#define VPORT0_IN _SFR_MEM8(0x0012) -#define VPORT0_INTFLAGS _SFR_MEM8(0x0013) - -/* VPORT - Virtual Port */ -#define VPORT1_DIR _SFR_MEM8(0x0014) -#define VPORT1_OUT _SFR_MEM8(0x0015) -#define VPORT1_IN _SFR_MEM8(0x0016) -#define VPORT1_INTFLAGS _SFR_MEM8(0x0017) - -/* VPORT - Virtual Port */ -#define VPORT2_DIR _SFR_MEM8(0x0018) -#define VPORT2_OUT _SFR_MEM8(0x0019) -#define VPORT2_IN _SFR_MEM8(0x001A) -#define VPORT2_INTFLAGS _SFR_MEM8(0x001B) - -/* VPORT - Virtual Port */ -#define VPORT3_DIR _SFR_MEM8(0x001C) -#define VPORT3_OUT _SFR_MEM8(0x001D) -#define VPORT3_IN _SFR_MEM8(0x001E) -#define VPORT3_INTFLAGS _SFR_MEM8(0x001F) - -/* OCD - On-Chip Debug System */ -#define OCD_OCDR0 _SFR_MEM8(0x002E) -#define OCD_OCDR1 _SFR_MEM8(0x002F) - -/* CPU - CPU registers */ -#define CPU_CCP _SFR_MEM8(0x0034) -#define CPU_RAMPD _SFR_MEM8(0x0038) -#define CPU_RAMPX _SFR_MEM8(0x0039) -#define CPU_RAMPY _SFR_MEM8(0x003A) -#define CPU_RAMPZ _SFR_MEM8(0x003B) -#define CPU_EIND _SFR_MEM8(0x003C) -#define CPU_SPL _SFR_MEM8(0x003D) -#define CPU_SPH _SFR_MEM8(0x003E) -#define CPU_SREG _SFR_MEM8(0x003F) - -/* CLK - Clock System */ -#define CLK_CTRL _SFR_MEM8(0x0040) -#define CLK_PSCTRL _SFR_MEM8(0x0041) -#define CLK_LOCK _SFR_MEM8(0x0042) -#define CLK_RTCCTRL _SFR_MEM8(0x0043) -#define CLK_USBCTRL _SFR_MEM8(0x0044) - -/* SLEEP - Sleep Controller */ -#define SLEEP_CTRL _SFR_MEM8(0x0048) - -/* OSC - Oscillator */ -#define OSC_CTRL _SFR_MEM8(0x0050) -#define OSC_STATUS _SFR_MEM8(0x0051) -#define OSC_XOSCCTRL _SFR_MEM8(0x0052) -#define OSC_XOSCFAIL _SFR_MEM8(0x0053) -#define OSC_RC32KCAL _SFR_MEM8(0x0054) -#define OSC_PLLCTRL _SFR_MEM8(0x0055) -#define OSC_DFLLCTRL _SFR_MEM8(0x0056) - -/* DFLL - DFLL */ -#define DFLLRC32M_CTRL _SFR_MEM8(0x0060) -#define DFLLRC32M_CALA _SFR_MEM8(0x0062) -#define DFLLRC32M_CALB _SFR_MEM8(0x0063) -#define DFLLRC32M_COMP0 _SFR_MEM8(0x0064) -#define DFLLRC32M_COMP1 _SFR_MEM8(0x0065) -#define DFLLRC32M_COMP2 _SFR_MEM8(0x0066) - -/* DFLL - DFLL */ -#define DFLLRC2M_CTRL _SFR_MEM8(0x0068) -#define DFLLRC2M_CALA _SFR_MEM8(0x006A) -#define DFLLRC2M_CALB _SFR_MEM8(0x006B) -#define DFLLRC2M_COMP0 _SFR_MEM8(0x006C) -#define DFLLRC2M_COMP1 _SFR_MEM8(0x006D) -#define DFLLRC2M_COMP2 _SFR_MEM8(0x006E) - -/* PR - Power Reduction */ -#define PR_PRGEN _SFR_MEM8(0x0070) -#define PR_PRPA _SFR_MEM8(0x0071) -#define PR_PRPC _SFR_MEM8(0x0073) -#define PR_PRPD _SFR_MEM8(0x0074) -#define PR_PRPE _SFR_MEM8(0x0075) -#define PR_PRPF _SFR_MEM8(0x0076) - -/* RST - Reset */ -#define RST_STATUS _SFR_MEM8(0x0078) -#define RST_CTRL _SFR_MEM8(0x0079) - -/* WDT - Watch-Dog Timer */ -#define WDT_CTRL _SFR_MEM8(0x0080) -#define WDT_WINCTRL _SFR_MEM8(0x0081) -#define WDT_STATUS _SFR_MEM8(0x0082) - -/* MCU - MCU Control */ -#define MCU_DEVID0 _SFR_MEM8(0x0090) -#define MCU_DEVID1 _SFR_MEM8(0x0091) -#define MCU_DEVID2 _SFR_MEM8(0x0092) -#define MCU_REVID _SFR_MEM8(0x0093) -#define MCU_ANAINIT _SFR_MEM8(0x0097) -#define MCU_EVSYSLOCK _SFR_MEM8(0x0098) -#define MCU_AWEXLOCK _SFR_MEM8(0x0099) - -/* PMIC - Programmable Multi-level Interrupt Controller */ -#define PMIC_STATUS _SFR_MEM8(0x00A0) -#define PMIC_INTPRI _SFR_MEM8(0x00A1) -#define PMIC_CTRL _SFR_MEM8(0x00A2) - -/* PORTCFG - I/O port Configuration */ -#define PORTCFG_MPCMASK _SFR_MEM8(0x00B0) -#define PORTCFG_VPCTRLA _SFR_MEM8(0x00B2) -#define PORTCFG_VPCTRLB _SFR_MEM8(0x00B3) -#define PORTCFG_CLKEVOUT _SFR_MEM8(0x00B4) -#define PORTCFG_EVOUTSEL _SFR_MEM8(0x00B6) - -/* CRC - Cyclic Redundancy Checker */ -#define CRC_CTRL _SFR_MEM8(0x00D0) -#define CRC_STATUS _SFR_MEM8(0x00D1) -#define CRC_DATAIN _SFR_MEM8(0x00D3) -#define CRC_CHECKSUM0 _SFR_MEM8(0x00D4) -#define CRC_CHECKSUM1 _SFR_MEM8(0x00D5) -#define CRC_CHECKSUM2 _SFR_MEM8(0x00D6) -#define CRC_CHECKSUM3 _SFR_MEM8(0x00D7) - -/* EVSYS - Event System */ -#define EVSYS_CH0MUX _SFR_MEM8(0x0180) -#define EVSYS_CH1MUX _SFR_MEM8(0x0181) -#define EVSYS_CH2MUX _SFR_MEM8(0x0182) -#define EVSYS_CH3MUX _SFR_MEM8(0x0183) -#define EVSYS_CH0CTRL _SFR_MEM8(0x0188) -#define EVSYS_CH1CTRL _SFR_MEM8(0x0189) -#define EVSYS_CH2CTRL _SFR_MEM8(0x018A) -#define EVSYS_CH3CTRL _SFR_MEM8(0x018B) -#define EVSYS_STROBE _SFR_MEM8(0x0190) -#define EVSYS_DATA _SFR_MEM8(0x0191) - -/* NVM - Non-volatile Memory Controller */ -#define NVM_ADDR0 _SFR_MEM8(0x01C0) -#define NVM_ADDR1 _SFR_MEM8(0x01C1) -#define NVM_ADDR2 _SFR_MEM8(0x01C2) -#define NVM_DATA0 _SFR_MEM8(0x01C4) -#define NVM_DATA1 _SFR_MEM8(0x01C5) -#define NVM_DATA2 _SFR_MEM8(0x01C6) -#define NVM_CMD _SFR_MEM8(0x01CA) -#define NVM_CTRLA _SFR_MEM8(0x01CB) -#define NVM_CTRLB _SFR_MEM8(0x01CC) -#define NVM_INTCTRL _SFR_MEM8(0x01CD) -#define NVM_STATUS _SFR_MEM8(0x01CF) -#define NVM_LOCKBITS _SFR_MEM8(0x01D0) - -/* ADC - Analog-to-Digital Converter */ -#define ADCA_CTRLA _SFR_MEM8(0x0200) -#define ADCA_CTRLB _SFR_MEM8(0x0201) -#define ADCA_REFCTRL _SFR_MEM8(0x0202) -#define ADCA_EVCTRL _SFR_MEM8(0x0203) -#define ADCA_PRESCALER _SFR_MEM8(0x0204) -#define ADCA_INTFLAGS _SFR_MEM8(0x0206) -#define ADCA_TEMP _SFR_MEM8(0x0207) -#define ADCA_CAL _SFR_MEM16(0x020C) -#define ADCA_CH0RES _SFR_MEM16(0x0210) -#define ADCA_CMP _SFR_MEM16(0x0218) -#define ADCA_CH0_CTRL _SFR_MEM8(0x0220) -#define ADCA_CH0_MUXCTRL _SFR_MEM8(0x0221) -#define ADCA_CH0_INTCTRL _SFR_MEM8(0x0222) -#define ADCA_CH0_INTFLAGS _SFR_MEM8(0x0223) -#define ADCA_CH0_RES _SFR_MEM16(0x0224) -#define ADCA_CH0_SCAN _SFR_MEM8(0x0226) - -/* AC - Analog Comparator */ -#define ACA_AC0CTRL _SFR_MEM8(0x0380) -#define ACA_AC1CTRL _SFR_MEM8(0x0381) -#define ACA_AC0MUXCTRL _SFR_MEM8(0x0382) -#define ACA_AC1MUXCTRL _SFR_MEM8(0x0383) -#define ACA_CTRLA _SFR_MEM8(0x0384) -#define ACA_CTRLB _SFR_MEM8(0x0385) -#define ACA_WINCTRL _SFR_MEM8(0x0386) -#define ACA_STATUS _SFR_MEM8(0x0387) - -/* RTC - Real-Time Counter */ -#define RTC_CTRL _SFR_MEM8(0x0400) -#define RTC_STATUS _SFR_MEM8(0x0401) -#define RTC_INTCTRL _SFR_MEM8(0x0402) -#define RTC_INTFLAGS _SFR_MEM8(0x0403) -#define RTC_TEMP _SFR_MEM8(0x0404) -#define RTC_CNT _SFR_MEM16(0x0408) -#define RTC_PER _SFR_MEM16(0x040A) -#define RTC_COMP _SFR_MEM16(0x040C) - -/* TWI - Two-Wire Interface */ -#define TWIC_CTRL _SFR_MEM8(0x0480) -#define TWIC_MASTER_CTRLA _SFR_MEM8(0x0481) -#define TWIC_MASTER_CTRLB _SFR_MEM8(0x0482) -#define TWIC_MASTER_CTRLC _SFR_MEM8(0x0483) -#define TWIC_MASTER_STATUS _SFR_MEM8(0x0484) -#define TWIC_MASTER_BAUD _SFR_MEM8(0x0485) -#define TWIC_MASTER_ADDR _SFR_MEM8(0x0486) -#define TWIC_MASTER_DATA _SFR_MEM8(0x0487) -#define TWIC_SLAVE_CTRLA _SFR_MEM8(0x0488) -#define TWIC_SLAVE_CTRLB _SFR_MEM8(0x0489) -#define TWIC_SLAVE_STATUS _SFR_MEM8(0x048A) -#define TWIC_SLAVE_ADDR _SFR_MEM8(0x048B) -#define TWIC_SLAVE_DATA _SFR_MEM8(0x048C) -#define TWIC_SLAVE_ADDRMASK _SFR_MEM8(0x048D) - -/* TWI - Two-Wire Interface */ -#define TWIE_CTRL _SFR_MEM8(0x04A0) -#define TWIE_MASTER_CTRLA _SFR_MEM8(0x04A1) -#define TWIE_MASTER_CTRLB _SFR_MEM8(0x04A2) -#define TWIE_MASTER_CTRLC _SFR_MEM8(0x04A3) -#define TWIE_MASTER_STATUS _SFR_MEM8(0x04A4) -#define TWIE_MASTER_BAUD _SFR_MEM8(0x04A5) -#define TWIE_MASTER_ADDR _SFR_MEM8(0x04A6) -#define TWIE_MASTER_DATA _SFR_MEM8(0x04A7) -#define TWIE_SLAVE_CTRLA _SFR_MEM8(0x04A8) -#define TWIE_SLAVE_CTRLB _SFR_MEM8(0x04A9) -#define TWIE_SLAVE_STATUS _SFR_MEM8(0x04AA) -#define TWIE_SLAVE_ADDR _SFR_MEM8(0x04AB) -#define TWIE_SLAVE_DATA _SFR_MEM8(0x04AC) -#define TWIE_SLAVE_ADDRMASK _SFR_MEM8(0x04AD) - -/* USB - Universal Serial Bus */ -#define USB_CTRLA _SFR_MEM8(0x04C0) -#define USB_CTRLB _SFR_MEM8(0x04C1) -#define USB_STATUS _SFR_MEM8(0x04C2) -#define USB_ADDR _SFR_MEM8(0x04C3) -#define USB_FIFOWP _SFR_MEM8(0x04C4) -#define USB_FIFORP _SFR_MEM8(0x04C5) -#define USB_EPPTR _SFR_MEM16(0x04C6) -#define USB_INTCTRLA _SFR_MEM8(0x04C8) -#define USB_INTCTRLB _SFR_MEM8(0x04C9) -#define USB_INTFLAGSACLR _SFR_MEM8(0x04CA) -#define USB_INTFLAGSASET _SFR_MEM8(0x04CB) -#define USB_INTFLAGSBCLR _SFR_MEM8(0x04CC) -#define USB_INTFLAGSBSET _SFR_MEM8(0x04CD) -#define USB_CAL0 _SFR_MEM8(0x04FA) -#define USB_CAL1 _SFR_MEM8(0x04FB) - -/* PORT - I/O Ports */ -#define PORTA_DIR _SFR_MEM8(0x0600) -#define PORTA_DIRSET _SFR_MEM8(0x0601) -#define PORTA_DIRCLR _SFR_MEM8(0x0602) -#define PORTA_DIRTGL _SFR_MEM8(0x0603) -#define PORTA_OUT _SFR_MEM8(0x0604) -#define PORTA_OUTSET _SFR_MEM8(0x0605) -#define PORTA_OUTCLR _SFR_MEM8(0x0606) -#define PORTA_OUTTGL _SFR_MEM8(0x0607) -#define PORTA_IN _SFR_MEM8(0x0608) -#define PORTA_INTCTRL _SFR_MEM8(0x0609) -#define PORTA_INT0MASK _SFR_MEM8(0x060A) -#define PORTA_INT1MASK _SFR_MEM8(0x060B) -#define PORTA_INTFLAGS _SFR_MEM8(0x060C) -#define PORTA_REMAP _SFR_MEM8(0x060E) -#define PORTA_PIN0CTRL _SFR_MEM8(0x0610) -#define PORTA_PIN1CTRL _SFR_MEM8(0x0611) -#define PORTA_PIN2CTRL _SFR_MEM8(0x0612) -#define PORTA_PIN3CTRL _SFR_MEM8(0x0613) -#define PORTA_PIN4CTRL _SFR_MEM8(0x0614) -#define PORTA_PIN5CTRL _SFR_MEM8(0x0615) -#define PORTA_PIN6CTRL _SFR_MEM8(0x0616) -#define PORTA_PIN7CTRL _SFR_MEM8(0x0617) - -/* PORT - I/O Ports */ -#define PORTB_DIR _SFR_MEM8(0x0620) -#define PORTB_DIRSET _SFR_MEM8(0x0621) -#define PORTB_DIRCLR _SFR_MEM8(0x0622) -#define PORTB_DIRTGL _SFR_MEM8(0x0623) -#define PORTB_OUT _SFR_MEM8(0x0624) -#define PORTB_OUTSET _SFR_MEM8(0x0625) -#define PORTB_OUTCLR _SFR_MEM8(0x0626) -#define PORTB_OUTTGL _SFR_MEM8(0x0627) -#define PORTB_IN _SFR_MEM8(0x0628) -#define PORTB_INTCTRL _SFR_MEM8(0x0629) -#define PORTB_INT0MASK _SFR_MEM8(0x062A) -#define PORTB_INT1MASK _SFR_MEM8(0x062B) -#define PORTB_INTFLAGS _SFR_MEM8(0x062C) -#define PORTB_REMAP _SFR_MEM8(0x062E) -#define PORTB_PIN0CTRL _SFR_MEM8(0x0630) -#define PORTB_PIN1CTRL _SFR_MEM8(0x0631) -#define PORTB_PIN2CTRL _SFR_MEM8(0x0632) -#define PORTB_PIN3CTRL _SFR_MEM8(0x0633) -#define PORTB_PIN4CTRL _SFR_MEM8(0x0634) -#define PORTB_PIN5CTRL _SFR_MEM8(0x0635) -#define PORTB_PIN6CTRL _SFR_MEM8(0x0636) -#define PORTB_PIN7CTRL _SFR_MEM8(0x0637) - -/* PORT - I/O Ports */ -#define PORTC_DIR _SFR_MEM8(0x0640) -#define PORTC_DIRSET _SFR_MEM8(0x0641) -#define PORTC_DIRCLR _SFR_MEM8(0x0642) -#define PORTC_DIRTGL _SFR_MEM8(0x0643) -#define PORTC_OUT _SFR_MEM8(0x0644) -#define PORTC_OUTSET _SFR_MEM8(0x0645) -#define PORTC_OUTCLR _SFR_MEM8(0x0646) -#define PORTC_OUTTGL _SFR_MEM8(0x0647) -#define PORTC_IN _SFR_MEM8(0x0648) -#define PORTC_INTCTRL _SFR_MEM8(0x0649) -#define PORTC_INT0MASK _SFR_MEM8(0x064A) -#define PORTC_INT1MASK _SFR_MEM8(0x064B) -#define PORTC_INTFLAGS _SFR_MEM8(0x064C) -#define PORTC_REMAP _SFR_MEM8(0x064E) -#define PORTC_PIN0CTRL _SFR_MEM8(0x0650) -#define PORTC_PIN1CTRL _SFR_MEM8(0x0651) -#define PORTC_PIN2CTRL _SFR_MEM8(0x0652) -#define PORTC_PIN3CTRL _SFR_MEM8(0x0653) -#define PORTC_PIN4CTRL _SFR_MEM8(0x0654) -#define PORTC_PIN5CTRL _SFR_MEM8(0x0655) -#define PORTC_PIN6CTRL _SFR_MEM8(0x0656) -#define PORTC_PIN7CTRL _SFR_MEM8(0x0657) - -/* PORT - I/O Ports */ -#define PORTD_DIR _SFR_MEM8(0x0660) -#define PORTD_DIRSET _SFR_MEM8(0x0661) -#define PORTD_DIRCLR _SFR_MEM8(0x0662) -#define PORTD_DIRTGL _SFR_MEM8(0x0663) -#define PORTD_OUT _SFR_MEM8(0x0664) -#define PORTD_OUTSET _SFR_MEM8(0x0665) -#define PORTD_OUTCLR _SFR_MEM8(0x0666) -#define PORTD_OUTTGL _SFR_MEM8(0x0667) -#define PORTD_IN _SFR_MEM8(0x0668) -#define PORTD_INTCTRL _SFR_MEM8(0x0669) -#define PORTD_INT0MASK _SFR_MEM8(0x066A) -#define PORTD_INT1MASK _SFR_MEM8(0x066B) -#define PORTD_INTFLAGS _SFR_MEM8(0x066C) -#define PORTD_REMAP _SFR_MEM8(0x066E) -#define PORTD_PIN0CTRL _SFR_MEM8(0x0670) -#define PORTD_PIN1CTRL _SFR_MEM8(0x0671) -#define PORTD_PIN2CTRL _SFR_MEM8(0x0672) -#define PORTD_PIN3CTRL _SFR_MEM8(0x0673) -#define PORTD_PIN4CTRL _SFR_MEM8(0x0674) -#define PORTD_PIN5CTRL _SFR_MEM8(0x0675) -#define PORTD_PIN6CTRL _SFR_MEM8(0x0676) -#define PORTD_PIN7CTRL _SFR_MEM8(0x0677) - -/* PORT - I/O Ports */ -#define PORTE_DIR _SFR_MEM8(0x0680) -#define PORTE_DIRSET _SFR_MEM8(0x0681) -#define PORTE_DIRCLR _SFR_MEM8(0x0682) -#define PORTE_DIRTGL _SFR_MEM8(0x0683) -#define PORTE_OUT _SFR_MEM8(0x0684) -#define PORTE_OUTSET _SFR_MEM8(0x0685) -#define PORTE_OUTCLR _SFR_MEM8(0x0686) -#define PORTE_OUTTGL _SFR_MEM8(0x0687) -#define PORTE_IN _SFR_MEM8(0x0688) -#define PORTE_INTCTRL _SFR_MEM8(0x0689) -#define PORTE_INT0MASK _SFR_MEM8(0x068A) -#define PORTE_INT1MASK _SFR_MEM8(0x068B) -#define PORTE_INTFLAGS _SFR_MEM8(0x068C) -#define PORTE_REMAP _SFR_MEM8(0x068E) -#define PORTE_PIN0CTRL _SFR_MEM8(0x0690) -#define PORTE_PIN1CTRL _SFR_MEM8(0x0691) -#define PORTE_PIN2CTRL _SFR_MEM8(0x0692) -#define PORTE_PIN3CTRL _SFR_MEM8(0x0693) -#define PORTE_PIN4CTRL _SFR_MEM8(0x0694) -#define PORTE_PIN5CTRL _SFR_MEM8(0x0695) -#define PORTE_PIN6CTRL _SFR_MEM8(0x0696) -#define PORTE_PIN7CTRL _SFR_MEM8(0x0697) - -/* PORT - I/O Ports */ -#define PORTR_DIR _SFR_MEM8(0x07E0) -#define PORTR_DIRSET _SFR_MEM8(0x07E1) -#define PORTR_DIRCLR _SFR_MEM8(0x07E2) -#define PORTR_DIRTGL _SFR_MEM8(0x07E3) -#define PORTR_OUT _SFR_MEM8(0x07E4) -#define PORTR_OUTSET _SFR_MEM8(0x07E5) -#define PORTR_OUTCLR _SFR_MEM8(0x07E6) -#define PORTR_OUTTGL _SFR_MEM8(0x07E7) -#define PORTR_IN _SFR_MEM8(0x07E8) -#define PORTR_INTCTRL _SFR_MEM8(0x07E9) -#define PORTR_INT0MASK _SFR_MEM8(0x07EA) -#define PORTR_INT1MASK _SFR_MEM8(0x07EB) -#define PORTR_INTFLAGS _SFR_MEM8(0x07EC) -#define PORTR_REMAP _SFR_MEM8(0x07EE) -#define PORTR_PIN0CTRL _SFR_MEM8(0x07F0) -#define PORTR_PIN1CTRL _SFR_MEM8(0x07F1) -#define PORTR_PIN2CTRL _SFR_MEM8(0x07F2) -#define PORTR_PIN3CTRL _SFR_MEM8(0x07F3) -#define PORTR_PIN4CTRL _SFR_MEM8(0x07F4) -#define PORTR_PIN5CTRL _SFR_MEM8(0x07F5) -#define PORTR_PIN6CTRL _SFR_MEM8(0x07F6) -#define PORTR_PIN7CTRL _SFR_MEM8(0x07F7) - -/* TC0 - 16-bit Timer/Counter 0 */ -#define TCC0_CTRLA _SFR_MEM8(0x0800) -#define TCC0_CTRLB _SFR_MEM8(0x0801) -#define TCC0_CTRLC _SFR_MEM8(0x0802) -#define TCC0_CTRLD _SFR_MEM8(0x0803) -#define TCC0_CTRLE _SFR_MEM8(0x0804) -#define TCC0_INTCTRLA _SFR_MEM8(0x0806) -#define TCC0_INTCTRLB _SFR_MEM8(0x0807) -#define TCC0_CTRLFCLR _SFR_MEM8(0x0808) -#define TCC0_CTRLFSET _SFR_MEM8(0x0809) -#define TCC0_CTRLGCLR _SFR_MEM8(0x080A) -#define TCC0_CTRLGSET _SFR_MEM8(0x080B) -#define TCC0_INTFLAGS _SFR_MEM8(0x080C) -#define TCC0_TEMP _SFR_MEM8(0x080F) -#define TCC0_CNT _SFR_MEM16(0x0820) -#define TCC0_PER _SFR_MEM16(0x0826) -#define TCC0_CCA _SFR_MEM16(0x0828) -#define TCC0_CCB _SFR_MEM16(0x082A) -#define TCC0_CCC _SFR_MEM16(0x082C) -#define TCC0_CCD _SFR_MEM16(0x082E) -#define TCC0_PERBUF _SFR_MEM16(0x0836) -#define TCC0_CCABUF _SFR_MEM16(0x0838) -#define TCC0_CCBBUF _SFR_MEM16(0x083A) -#define TCC0_CCCBUF _SFR_MEM16(0x083C) -#define TCC0_CCDBUF _SFR_MEM16(0x083E) - -/* TC2 - 16-bit Timer/Counter type 2 */ -#define TCC2_CTRLA _SFR_MEM8(0x0800) -#define TCC2_CTRLB _SFR_MEM8(0x0801) -#define TCC2_CTRLC _SFR_MEM8(0x0802) -#define TCC2_CTRLE _SFR_MEM8(0x0804) -#define TCC2_INTCTRLA _SFR_MEM8(0x0806) -#define TCC2_INTCTRLB _SFR_MEM8(0x0807) -#define TCC2_CTRLF _SFR_MEM8(0x0809) -#define TCC2_INTFLAGS _SFR_MEM8(0x080C) -#define TCC2_LCNT _SFR_MEM8(0x0820) -#define TCC2_HCNT _SFR_MEM8(0x0821) -#define TCC2_LPER _SFR_MEM8(0x0826) -#define TCC2_HPER _SFR_MEM8(0x0827) -#define TCC2_LCMPA _SFR_MEM8(0x0828) -#define TCC2_HCMPA _SFR_MEM8(0x0829) -#define TCC2_LCMPB _SFR_MEM8(0x082A) -#define TCC2_HCMPB _SFR_MEM8(0x082B) -#define TCC2_LCMPC _SFR_MEM8(0x082C) -#define TCC2_HCMPC _SFR_MEM8(0x082D) -#define TCC2_LCMPD _SFR_MEM8(0x082E) -#define TCC2_HCMPD _SFR_MEM8(0x082F) - -/* TC1 - 16-bit Timer/Counter 1 */ -#define TCC1_CTRLA _SFR_MEM8(0x0840) -#define TCC1_CTRLB _SFR_MEM8(0x0841) -#define TCC1_CTRLC _SFR_MEM8(0x0842) -#define TCC1_CTRLD _SFR_MEM8(0x0843) -#define TCC1_CTRLE _SFR_MEM8(0x0844) -#define TCC1_INTCTRLA _SFR_MEM8(0x0846) -#define TCC1_INTCTRLB _SFR_MEM8(0x0847) -#define TCC1_CTRLFCLR _SFR_MEM8(0x0848) -#define TCC1_CTRLFSET _SFR_MEM8(0x0849) -#define TCC1_CTRLGCLR _SFR_MEM8(0x084A) -#define TCC1_CTRLGSET _SFR_MEM8(0x084B) -#define TCC1_INTFLAGS _SFR_MEM8(0x084C) -#define TCC1_TEMP _SFR_MEM8(0x084F) -#define TCC1_CNT _SFR_MEM16(0x0860) -#define TCC1_PER _SFR_MEM16(0x0866) -#define TCC1_CCA _SFR_MEM16(0x0868) -#define TCC1_CCB _SFR_MEM16(0x086A) -#define TCC1_PERBUF _SFR_MEM16(0x0876) -#define TCC1_CCABUF _SFR_MEM16(0x0878) -#define TCC1_CCBBUF _SFR_MEM16(0x087A) - -/* AWEX - Advanced Waveform Extension */ -#define AWEXC_CTRL _SFR_MEM8(0x0880) -#define AWEXC_FDEMASK _SFR_MEM8(0x0882) -#define AWEXC_FDCTRL _SFR_MEM8(0x0883) -#define AWEXC_STATUS _SFR_MEM8(0x0884) -#define AWEXC_STATUSSET _SFR_MEM8(0x0885) -#define AWEXC_DTBOTH _SFR_MEM8(0x0886) -#define AWEXC_DTBOTHBUF _SFR_MEM8(0x0887) -#define AWEXC_DTLS _SFR_MEM8(0x0888) -#define AWEXC_DTHS _SFR_MEM8(0x0889) -#define AWEXC_DTLSBUF _SFR_MEM8(0x088A) -#define AWEXC_DTHSBUF _SFR_MEM8(0x088B) -#define AWEXC_OUTOVEN _SFR_MEM8(0x088C) - -/* HIRES - High-Resolution Extension */ -#define HIRESC_CTRLA _SFR_MEM8(0x0890) - -/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ -#define USARTC0_DATA _SFR_MEM8(0x08A0) -#define USARTC0_STATUS _SFR_MEM8(0x08A1) -#define USARTC0_CTRLA _SFR_MEM8(0x08A3) -#define USARTC0_CTRLB _SFR_MEM8(0x08A4) -#define USARTC0_CTRLC _SFR_MEM8(0x08A5) -#define USARTC0_BAUDCTRLA _SFR_MEM8(0x08A6) -#define USARTC0_BAUDCTRLB _SFR_MEM8(0x08A7) - -/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ -#define USARTC1_DATA _SFR_MEM8(0x08B0) -#define USARTC1_STATUS _SFR_MEM8(0x08B1) -#define USARTC1_CTRLA _SFR_MEM8(0x08B3) -#define USARTC1_CTRLB _SFR_MEM8(0x08B4) -#define USARTC1_CTRLC _SFR_MEM8(0x08B5) -#define USARTC1_BAUDCTRLA _SFR_MEM8(0x08B6) -#define USARTC1_BAUDCTRLB _SFR_MEM8(0x08B7) - -/* SPI - Serial Peripheral Interface */ -#define SPIC_CTRL _SFR_MEM8(0x08C0) -#define SPIC_INTCTRL _SFR_MEM8(0x08C1) -#define SPIC_STATUS _SFR_MEM8(0x08C2) -#define SPIC_DATA _SFR_MEM8(0x08C3) - -/* IRCOM - IR Communication Module */ -#define IRCOM_CTRL _SFR_MEM8(0x08F8) -#define IRCOM_TXPLCTRL _SFR_MEM8(0x08F9) -#define IRCOM_RXPLCTRL _SFR_MEM8(0x08FA) - -/* TC0 - 16-bit Timer/Counter 0 */ -#define TCD0_CTRLA _SFR_MEM8(0x0900) -#define TCD0_CTRLB _SFR_MEM8(0x0901) -#define TCD0_CTRLC _SFR_MEM8(0x0902) -#define TCD0_CTRLD _SFR_MEM8(0x0903) -#define TCD0_CTRLE _SFR_MEM8(0x0904) -#define TCD0_INTCTRLA _SFR_MEM8(0x0906) -#define TCD0_INTCTRLB _SFR_MEM8(0x0907) -#define TCD0_CTRLFCLR _SFR_MEM8(0x0908) -#define TCD0_CTRLFSET _SFR_MEM8(0x0909) -#define TCD0_CTRLGCLR _SFR_MEM8(0x090A) -#define TCD0_CTRLGSET _SFR_MEM8(0x090B) -#define TCD0_INTFLAGS _SFR_MEM8(0x090C) -#define TCD0_TEMP _SFR_MEM8(0x090F) -#define TCD0_CNT _SFR_MEM16(0x0920) -#define TCD0_PER _SFR_MEM16(0x0926) -#define TCD0_CCA _SFR_MEM16(0x0928) -#define TCD0_CCB _SFR_MEM16(0x092A) -#define TCD0_CCC _SFR_MEM16(0x092C) -#define TCD0_CCD _SFR_MEM16(0x092E) -#define TCD0_PERBUF _SFR_MEM16(0x0936) -#define TCD0_CCABUF _SFR_MEM16(0x0938) -#define TCD0_CCBBUF _SFR_MEM16(0x093A) -#define TCD0_CCCBUF _SFR_MEM16(0x093C) -#define TCD0_CCDBUF _SFR_MEM16(0x093E) - -/* TC2 - 16-bit Timer/Counter type 2 */ -#define TCD2_CTRLA _SFR_MEM8(0x0900) -#define TCD2_CTRLB _SFR_MEM8(0x0901) -#define TCD2_CTRLC _SFR_MEM8(0x0902) -#define TCD2_CTRLE _SFR_MEM8(0x0904) -#define TCD2_INTCTRLA _SFR_MEM8(0x0906) -#define TCD2_INTCTRLB _SFR_MEM8(0x0907) -#define TCD2_CTRLF _SFR_MEM8(0x0909) -#define TCD2_INTFLAGS _SFR_MEM8(0x090C) -#define TCD2_LCNT _SFR_MEM8(0x0920) -#define TCD2_HCNT _SFR_MEM8(0x0921) -#define TCD2_LPER _SFR_MEM8(0x0926) -#define TCD2_HPER _SFR_MEM8(0x0927) -#define TCD2_LCMPA _SFR_MEM8(0x0928) -#define TCD2_HCMPA _SFR_MEM8(0x0929) -#define TCD2_LCMPB _SFR_MEM8(0x092A) -#define TCD2_HCMPB _SFR_MEM8(0x092B) -#define TCD2_LCMPC _SFR_MEM8(0x092C) -#define TCD2_HCMPC _SFR_MEM8(0x092D) -#define TCD2_LCMPD _SFR_MEM8(0x092E) -#define TCD2_HCMPD _SFR_MEM8(0x092F) - -/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ -#define USARTD0_DATA _SFR_MEM8(0x09A0) -#define USARTD0_STATUS _SFR_MEM8(0x09A1) -#define USARTD0_CTRLA _SFR_MEM8(0x09A3) -#define USARTD0_CTRLB _SFR_MEM8(0x09A4) -#define USARTD0_CTRLC _SFR_MEM8(0x09A5) -#define USARTD0_BAUDCTRLA _SFR_MEM8(0x09A6) -#define USARTD0_BAUDCTRLB _SFR_MEM8(0x09A7) - -/* SPI - Serial Peripheral Interface */ -#define SPID_CTRL _SFR_MEM8(0x09C0) -#define SPID_INTCTRL _SFR_MEM8(0x09C1) -#define SPID_STATUS _SFR_MEM8(0x09C2) -#define SPID_DATA _SFR_MEM8(0x09C3) - -/* TC0 - 16-bit Timer/Counter 0 */ -#define TCE0_CTRLA _SFR_MEM8(0x0A00) -#define TCE0_CTRLB _SFR_MEM8(0x0A01) -#define TCE0_CTRLC _SFR_MEM8(0x0A02) -#define TCE0_CTRLD _SFR_MEM8(0x0A03) -#define TCE0_CTRLE _SFR_MEM8(0x0A04) -#define TCE0_INTCTRLA _SFR_MEM8(0x0A06) -#define TCE0_INTCTRLB _SFR_MEM8(0x0A07) -#define TCE0_CTRLFCLR _SFR_MEM8(0x0A08) -#define TCE0_CTRLFSET _SFR_MEM8(0x0A09) -#define TCE0_CTRLGCLR _SFR_MEM8(0x0A0A) -#define TCE0_CTRLGSET _SFR_MEM8(0x0A0B) -#define TCE0_INTFLAGS _SFR_MEM8(0x0A0C) -#define TCE0_TEMP _SFR_MEM8(0x0A0F) -#define TCE0_CNT _SFR_MEM16(0x0A20) -#define TCE0_PER _SFR_MEM16(0x0A26) -#define TCE0_CCA _SFR_MEM16(0x0A28) -#define TCE0_CCB _SFR_MEM16(0x0A2A) -#define TCE0_CCC _SFR_MEM16(0x0A2C) -#define TCE0_CCD _SFR_MEM16(0x0A2E) -#define TCE0_PERBUF _SFR_MEM16(0x0A36) -#define TCE0_CCABUF _SFR_MEM16(0x0A38) -#define TCE0_CCBBUF _SFR_MEM16(0x0A3A) -#define TCE0_CCCBUF _SFR_MEM16(0x0A3C) -#define TCE0_CCDBUF _SFR_MEM16(0x0A3E) - - - -/*================== Bitfield Definitions ================== */ - -/* VPORT - Virtual Ports */ -/* VPORT.INTFLAGS bit masks and bit positions */ -#define VPORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ -#define VPORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ - -#define VPORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ -#define VPORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ - -/* XOCD - On-Chip Debug System */ -/* OCD.OCDR0 bit masks and bit positions */ -#define OCD_OCDRD_gm 0xFF /* OCDR Dirty group mask. */ -#define OCD_OCDRD_gp 0 /* OCDR Dirty group position. */ -#define OCD_OCDRD0_bm (1<<0) /* OCDR Dirty bit 0 mask. */ -#define OCD_OCDRD0_bp 0 /* OCDR Dirty bit 0 position. */ -#define OCD_OCDRD1_bm (1<<1) /* OCDR Dirty bit 1 mask. */ -#define OCD_OCDRD1_bp 1 /* OCDR Dirty bit 1 position. */ -#define OCD_OCDRD2_bm (1<<2) /* OCDR Dirty bit 2 mask. */ -#define OCD_OCDRD2_bp 2 /* OCDR Dirty bit 2 position. */ -#define OCD_OCDRD3_bm (1<<3) /* OCDR Dirty bit 3 mask. */ -#define OCD_OCDRD3_bp 3 /* OCDR Dirty bit 3 position. */ -#define OCD_OCDRD4_bm (1<<4) /* OCDR Dirty bit 4 mask. */ -#define OCD_OCDRD4_bp 4 /* OCDR Dirty bit 4 position. */ -#define OCD_OCDRD5_bm (1<<5) /* OCDR Dirty bit 5 mask. */ -#define OCD_OCDRD5_bp 5 /* OCDR Dirty bit 5 position. */ -#define OCD_OCDRD6_bm (1<<6) /* OCDR Dirty bit 6 mask. */ -#define OCD_OCDRD6_bp 6 /* OCDR Dirty bit 6 position. */ -#define OCD_OCDRD7_bm (1<<7) /* OCDR Dirty bit 7 mask. */ -#define OCD_OCDRD7_bp 7 /* OCDR Dirty bit 7 position. */ - -/* OCD.OCDR1 bit masks and bit positions */ -/* OCD_OCDRD Predefined. */ -/* OCD_OCDRD Predefined. */ - -/* CPU - CPU */ -/* CPU.CCP bit masks and bit positions */ -#define CPU_CCP_gm 0xFF /* CCP signature group mask. */ -#define CPU_CCP_gp 0 /* CCP signature group position. */ -#define CPU_CCP0_bm (1<<0) /* CCP signature bit 0 mask. */ -#define CPU_CCP0_bp 0 /* CCP signature bit 0 position. */ -#define CPU_CCP1_bm (1<<1) /* CCP signature bit 1 mask. */ -#define CPU_CCP1_bp 1 /* CCP signature bit 1 position. */ -#define CPU_CCP2_bm (1<<2) /* CCP signature bit 2 mask. */ -#define CPU_CCP2_bp 2 /* CCP signature bit 2 position. */ -#define CPU_CCP3_bm (1<<3) /* CCP signature bit 3 mask. */ -#define CPU_CCP3_bp 3 /* CCP signature bit 3 position. */ -#define CPU_CCP4_bm (1<<4) /* CCP signature bit 4 mask. */ -#define CPU_CCP4_bp 4 /* CCP signature bit 4 position. */ -#define CPU_CCP5_bm (1<<5) /* CCP signature bit 5 mask. */ -#define CPU_CCP5_bp 5 /* CCP signature bit 5 position. */ -#define CPU_CCP6_bm (1<<6) /* CCP signature bit 6 mask. */ -#define CPU_CCP6_bp 6 /* CCP signature bit 6 position. */ -#define CPU_CCP7_bm (1<<7) /* CCP signature bit 7 mask. */ -#define CPU_CCP7_bp 7 /* CCP signature bit 7 position. */ - -/* CPU.SREG bit masks and bit positions */ -#define CPU_I_bm 0x80 /* Global Interrupt Enable Flag bit mask. */ -#define CPU_I_bp 7 /* Global Interrupt Enable Flag bit position. */ - -#define CPU_T_bm 0x40 /* Transfer Bit bit mask. */ -#define CPU_T_bp 6 /* Transfer Bit bit position. */ - -#define CPU_H_bm 0x20 /* Half Carry Flag bit mask. */ -#define CPU_H_bp 5 /* Half Carry Flag bit position. */ - -#define CPU_S_bm 0x10 /* N Exclusive Or V Flag bit mask. */ -#define CPU_S_bp 4 /* N Exclusive Or V Flag bit position. */ - -#define CPU_V_bm 0x08 /* Two's Complement Overflow Flag bit mask. */ -#define CPU_V_bp 3 /* Two's Complement Overflow Flag bit position. */ - -#define CPU_N_bm 0x04 /* Negative Flag bit mask. */ -#define CPU_N_bp 2 /* Negative Flag bit position. */ - -#define CPU_Z_bm 0x02 /* Zero Flag bit mask. */ -#define CPU_Z_bp 1 /* Zero Flag bit position. */ - -#define CPU_C_bm 0x01 /* Carry Flag bit mask. */ -#define CPU_C_bp 0 /* Carry Flag bit position. */ - -/* CLK - Clock System */ -/* CLK.CTRL bit masks and bit positions */ -#define CLK_SCLKSEL_gm 0x07 /* System Clock Selection group mask. */ -#define CLK_SCLKSEL_gp 0 /* System Clock Selection group position. */ -#define CLK_SCLKSEL0_bm (1<<0) /* System Clock Selection bit 0 mask. */ -#define CLK_SCLKSEL0_bp 0 /* System Clock Selection bit 0 position. */ -#define CLK_SCLKSEL1_bm (1<<1) /* System Clock Selection bit 1 mask. */ -#define CLK_SCLKSEL1_bp 1 /* System Clock Selection bit 1 position. */ -#define CLK_SCLKSEL2_bm (1<<2) /* System Clock Selection bit 2 mask. */ -#define CLK_SCLKSEL2_bp 2 /* System Clock Selection bit 2 position. */ - -/* CLK.PSCTRL bit masks and bit positions */ -#define CLK_PSADIV_gm 0x7C /* Prescaler A Division Factor group mask. */ -#define CLK_PSADIV_gp 2 /* Prescaler A Division Factor group position. */ -#define CLK_PSADIV0_bm (1<<2) /* Prescaler A Division Factor bit 0 mask. */ -#define CLK_PSADIV0_bp 2 /* Prescaler A Division Factor bit 0 position. */ -#define CLK_PSADIV1_bm (1<<3) /* Prescaler A Division Factor bit 1 mask. */ -#define CLK_PSADIV1_bp 3 /* Prescaler A Division Factor bit 1 position. */ -#define CLK_PSADIV2_bm (1<<4) /* Prescaler A Division Factor bit 2 mask. */ -#define CLK_PSADIV2_bp 4 /* Prescaler A Division Factor bit 2 position. */ -#define CLK_PSADIV3_bm (1<<5) /* Prescaler A Division Factor bit 3 mask. */ -#define CLK_PSADIV3_bp 5 /* Prescaler A Division Factor bit 3 position. */ -#define CLK_PSADIV4_bm (1<<6) /* Prescaler A Division Factor bit 4 mask. */ -#define CLK_PSADIV4_bp 6 /* Prescaler A Division Factor bit 4 position. */ - -#define CLK_PSBCDIV_gm 0x03 /* Prescaler B and C Division factor group mask. */ -#define CLK_PSBCDIV_gp 0 /* Prescaler B and C Division factor group position. */ -#define CLK_PSBCDIV0_bm (1<<0) /* Prescaler B and C Division factor bit 0 mask. */ -#define CLK_PSBCDIV0_bp 0 /* Prescaler B and C Division factor bit 0 position. */ -#define CLK_PSBCDIV1_bm (1<<1) /* Prescaler B and C Division factor bit 1 mask. */ -#define CLK_PSBCDIV1_bp 1 /* Prescaler B and C Division factor bit 1 position. */ - -/* CLK.LOCK bit masks and bit positions */ -#define CLK_LOCK_bm 0x01 /* Clock System Lock bit mask. */ -#define CLK_LOCK_bp 0 /* Clock System Lock bit position. */ - -/* CLK.RTCCTRL bit masks and bit positions */ -#define CLK_RTCSRC_gm 0x0E /* Clock Source group mask. */ -#define CLK_RTCSRC_gp 1 /* Clock Source group position. */ -#define CLK_RTCSRC0_bm (1<<1) /* Clock Source bit 0 mask. */ -#define CLK_RTCSRC0_bp 1 /* Clock Source bit 0 position. */ -#define CLK_RTCSRC1_bm (1<<2) /* Clock Source bit 1 mask. */ -#define CLK_RTCSRC1_bp 2 /* Clock Source bit 1 position. */ -#define CLK_RTCSRC2_bm (1<<3) /* Clock Source bit 2 mask. */ -#define CLK_RTCSRC2_bp 3 /* Clock Source bit 2 position. */ - -#define CLK_RTCEN_bm 0x01 /* Clock Source Enable bit mask. */ -#define CLK_RTCEN_bp 0 /* Clock Source Enable bit position. */ - -/* CLK.USBCTRL bit masks and bit positions */ -#define CLK_USBPSDIV_gm 0x38 /* Prescaler Division Factor group mask. */ -#define CLK_USBPSDIV_gp 3 /* Prescaler Division Factor group position. */ -#define CLK_USBPSDIV0_bm (1<<3) /* Prescaler Division Factor bit 0 mask. */ -#define CLK_USBPSDIV0_bp 3 /* Prescaler Division Factor bit 0 position. */ -#define CLK_USBPSDIV1_bm (1<<4) /* Prescaler Division Factor bit 1 mask. */ -#define CLK_USBPSDIV1_bp 4 /* Prescaler Division Factor bit 1 position. */ -#define CLK_USBPSDIV2_bm (1<<5) /* Prescaler Division Factor bit 2 mask. */ -#define CLK_USBPSDIV2_bp 5 /* Prescaler Division Factor bit 2 position. */ - -#define CLK_USBSRC_gm 0x06 /* Clock Source group mask. */ -#define CLK_USBSRC_gp 1 /* Clock Source group position. */ -#define CLK_USBSRC0_bm (1<<1) /* Clock Source bit 0 mask. */ -#define CLK_USBSRC0_bp 1 /* Clock Source bit 0 position. */ -#define CLK_USBSRC1_bm (1<<2) /* Clock Source bit 1 mask. */ -#define CLK_USBSRC1_bp 2 /* Clock Source bit 1 position. */ - -#define CLK_USBSEN_bm 0x01 /* Clock Source Enable bit mask. */ -#define CLK_USBSEN_bp 0 /* Clock Source Enable bit position. */ - -/* PR.PRGEN bit masks and bit positions */ -#define PR_USB_bm 0x40 /* USB bit mask. */ -#define PR_USB_bp 6 /* USB bit position. */ - -#define PR_AES_bm 0x10 /* AES bit mask. */ -#define PR_AES_bp 4 /* AES bit position. */ - -#define PR_RTC_bm 0x04 /* Real-time Counter bit mask. */ -#define PR_RTC_bp 2 /* Real-time Counter bit position. */ - -#define PR_EVSYS_bm 0x02 /* Event System bit mask. */ -#define PR_EVSYS_bp 1 /* Event System bit position. */ - -#define PR_DMA_bm 0x01 /* DMA-Controller bit mask. */ -#define PR_DMA_bp 0 /* DMA-Controller bit position. */ - -/* PR.PRPA bit masks and bit positions */ -#define PR_ADC_bm 0x02 /* Port A ADC bit mask. */ -#define PR_ADC_bp 1 /* Port A ADC bit position. */ - -#define PR_AC_bm 0x01 /* Port A Analog Comparator bit mask. */ -#define PR_AC_bp 0 /* Port A Analog Comparator bit position. */ - -/* PR.PRPC bit masks and bit positions */ -#define PR_TWI_bm 0x40 /* Port C Two-wire Interface bit mask. */ -#define PR_TWI_bp 6 /* Port C Two-wire Interface bit position. */ - -#define PR_USART1_bm 0x20 /* Port C USART1 bit mask. */ -#define PR_USART1_bp 5 /* Port C USART1 bit position. */ - -#define PR_USART0_bm 0x10 /* Port C USART0 bit mask. */ -#define PR_USART0_bp 4 /* Port C USART0 bit position. */ - -#define PR_SPI_bm 0x08 /* Port C SPI bit mask. */ -#define PR_SPI_bp 3 /* Port C SPI bit position. */ - -#define PR_HIRES_bm 0x04 /* Port C AWEX bit mask. */ -#define PR_HIRES_bp 2 /* Port C AWEX bit position. */ - -#define PR_TC1_bm 0x02 /* Port C Timer/Counter1 bit mask. */ -#define PR_TC1_bp 1 /* Port C Timer/Counter1 bit position. */ - -#define PR_TC0_bm 0x01 /* Port C Timer/Counter0 bit mask. */ -#define PR_TC0_bp 0 /* Port C Timer/Counter0 bit position. */ - -/* PR.PRPD bit masks and bit positions */ -/* PR_USART0 Predefined. */ -/* PR_USART0 Predefined. */ - -/* PR_SPI Predefined. */ -/* PR_SPI Predefined. */ - -/* PR_TC0 Predefined. */ -/* PR_TC0 Predefined. */ - -/* PR.PRPE bit masks and bit positions */ -/* PR_TWI Predefined. */ -/* PR_TWI Predefined. */ - -/* PR_USART0 Predefined. */ -/* PR_USART0 Predefined. */ - -/* PR_TC0 Predefined. */ -/* PR_TC0 Predefined. */ - -/* PR.PRPF bit masks and bit positions */ -/* PR_USART0 Predefined. */ -/* PR_USART0 Predefined. */ - -/* PR_TC0 Predefined. */ -/* PR_TC0 Predefined. */ - -/* SLEEP - Sleep Controller */ -/* SLEEP.CTRL bit masks and bit positions */ -#define SLEEP_SMODE_gm 0x0E /* Sleep Mode group mask. */ -#define SLEEP_SMODE_gp 1 /* Sleep Mode group position. */ -#define SLEEP_SMODE0_bm (1<<1) /* Sleep Mode bit 0 mask. */ -#define SLEEP_SMODE0_bp 1 /* Sleep Mode bit 0 position. */ -#define SLEEP_SMODE1_bm (1<<2) /* Sleep Mode bit 1 mask. */ -#define SLEEP_SMODE1_bp 2 /* Sleep Mode bit 1 position. */ -#define SLEEP_SMODE2_bm (1<<3) /* Sleep Mode bit 2 mask. */ -#define SLEEP_SMODE2_bp 3 /* Sleep Mode bit 2 position. */ - -#define SLEEP_SEN_bm 0x01 /* Sleep Enable bit mask. */ -#define SLEEP_SEN_bp 0 /* Sleep Enable bit position. */ - -/* OSC - Oscillator */ -/* OSC.CTRL bit masks and bit positions */ -#define OSC_PLLEN_bm 0x10 /* PLL Enable bit mask. */ -#define OSC_PLLEN_bp 4 /* PLL Enable bit position. */ - -#define OSC_XOSCEN_bm 0x08 /* External Oscillator Enable bit mask. */ -#define OSC_XOSCEN_bp 3 /* External Oscillator Enable bit position. */ - -#define OSC_RC32KEN_bm 0x04 /* Internal 32.768 kHz RC Oscillator Enable bit mask. */ -#define OSC_RC32KEN_bp 2 /* Internal 32.768 kHz RC Oscillator Enable bit position. */ - -#define OSC_RC32MEN_bm 0x02 /* Internal 32 MHz RC Oscillator Enable bit mask. */ -#define OSC_RC32MEN_bp 1 /* Internal 32 MHz RC Oscillator Enable bit position. */ - -#define OSC_RC2MEN_bm 0x01 /* Internal 2 MHz RC Oscillator Enable bit mask. */ -#define OSC_RC2MEN_bp 0 /* Internal 2 MHz RC Oscillator Enable bit position. */ - -/* OSC.STATUS bit masks and bit positions */ -#define OSC_PLLRDY_bm 0x10 /* PLL Ready bit mask. */ -#define OSC_PLLRDY_bp 4 /* PLL Ready bit position. */ - -#define OSC_XOSCRDY_bm 0x08 /* External Oscillator Ready bit mask. */ -#define OSC_XOSCRDY_bp 3 /* External Oscillator Ready bit position. */ - -#define OSC_RC32KRDY_bm 0x04 /* Internal 32.768 kHz RC Oscillator Ready bit mask. */ -#define OSC_RC32KRDY_bp 2 /* Internal 32.768 kHz RC Oscillator Ready bit position. */ - -#define OSC_RC32MRDY_bm 0x02 /* Internal 32 MHz RC Oscillator Ready bit mask. */ -#define OSC_RC32MRDY_bp 1 /* Internal 32 MHz RC Oscillator Ready bit position. */ - -#define OSC_RC2MRDY_bm 0x01 /* Internal 2 MHz RC Oscillator Ready bit mask. */ -#define OSC_RC2MRDY_bp 0 /* Internal 2 MHz RC Oscillator Ready bit position. */ - -/* OSC.XOSCCTRL bit masks and bit positions */ -#define OSC_FRQRANGE_gm 0xC0 /* Frequency Range group mask. */ -#define OSC_FRQRANGE_gp 6 /* Frequency Range group position. */ -#define OSC_FRQRANGE0_bm (1<<6) /* Frequency Range bit 0 mask. */ -#define OSC_FRQRANGE0_bp 6 /* Frequency Range bit 0 position. */ -#define OSC_FRQRANGE1_bm (1<<7) /* Frequency Range bit 1 mask. */ -#define OSC_FRQRANGE1_bp 7 /* Frequency Range bit 1 position. */ - -#define OSC_X32KLPM_bm 0x20 /* 32.768 kHz XTAL OSC Low-power Mode bit mask. */ -#define OSC_X32KLPM_bp 5 /* 32.768 kHz XTAL OSC Low-power Mode bit position. */ - -#define OSC_XOSCPWR_bm 0x10 /* 16 MHz Crystal Oscillator High Power mode bit mask. */ -#define OSC_XOSCPWR_bp 4 /* 16 MHz Crystal Oscillator High Power mode bit position. */ - -#define OSC_XOSCSEL_gm 0x0F /* External Oscillator Selection and Startup Time group mask. */ -#define OSC_XOSCSEL_gp 0 /* External Oscillator Selection and Startup Time group position. */ -#define OSC_XOSCSEL0_bm (1<<0) /* External Oscillator Selection and Startup Time bit 0 mask. */ -#define OSC_XOSCSEL0_bp 0 /* External Oscillator Selection and Startup Time bit 0 position. */ -#define OSC_XOSCSEL1_bm (1<<1) /* External Oscillator Selection and Startup Time bit 1 mask. */ -#define OSC_XOSCSEL1_bp 1 /* External Oscillator Selection and Startup Time bit 1 position. */ -#define OSC_XOSCSEL2_bm (1<<2) /* External Oscillator Selection and Startup Time bit 2 mask. */ -#define OSC_XOSCSEL2_bp 2 /* External Oscillator Selection and Startup Time bit 2 position. */ -#define OSC_XOSCSEL3_bm (1<<3) /* External Oscillator Selection and Startup Time bit 3 mask. */ -#define OSC_XOSCSEL3_bp 3 /* External Oscillator Selection and Startup Time bit 3 position. */ - -/* OSC.XOSCFAIL bit masks and bit positions */ -#define OSC_PLLFDIF_bm 0x08 /* PLL Failure Detection Interrupt Flag bit mask. */ -#define OSC_PLLFDIF_bp 3 /* PLL Failure Detection Interrupt Flag bit position. */ - -#define OSC_PLLFDEN_bm 0x04 /* PLL Failure Detection Enable bit mask. */ -#define OSC_PLLFDEN_bp 2 /* PLL Failure Detection Enable bit position. */ - -#define OSC_XOSCFDIF_bm 0x02 /* XOSC Failure Detection Interrupt Flag bit mask. */ -#define OSC_XOSCFDIF_bp 1 /* XOSC Failure Detection Interrupt Flag bit position. */ - -#define OSC_XOSCFDEN_bm 0x01 /* XOSC Failure Detection Enable bit mask. */ -#define OSC_XOSCFDEN_bp 0 /* XOSC Failure Detection Enable bit position. */ - -/* OSC.PLLCTRL bit masks and bit positions */ -#define OSC_PLLSRC_gm 0xC0 /* Clock Source group mask. */ -#define OSC_PLLSRC_gp 6 /* Clock Source group position. */ -#define OSC_PLLSRC0_bm (1<<6) /* Clock Source bit 0 mask. */ -#define OSC_PLLSRC0_bp 6 /* Clock Source bit 0 position. */ -#define OSC_PLLSRC1_bm (1<<7) /* Clock Source bit 1 mask. */ -#define OSC_PLLSRC1_bp 7 /* Clock Source bit 1 position. */ - -#define OSC_PLLDIV_bm 0x20 /* Divide by 2 bit mask. */ -#define OSC_PLLDIV_bp 5 /* Divide by 2 bit position. */ - -#define OSC_PLLFAC_gm 0x1F /* Multiplication Factor group mask. */ -#define OSC_PLLFAC_gp 0 /* Multiplication Factor group position. */ -#define OSC_PLLFAC0_bm (1<<0) /* Multiplication Factor bit 0 mask. */ -#define OSC_PLLFAC0_bp 0 /* Multiplication Factor bit 0 position. */ -#define OSC_PLLFAC1_bm (1<<1) /* Multiplication Factor bit 1 mask. */ -#define OSC_PLLFAC1_bp 1 /* Multiplication Factor bit 1 position. */ -#define OSC_PLLFAC2_bm (1<<2) /* Multiplication Factor bit 2 mask. */ -#define OSC_PLLFAC2_bp 2 /* Multiplication Factor bit 2 position. */ -#define OSC_PLLFAC3_bm (1<<3) /* Multiplication Factor bit 3 mask. */ -#define OSC_PLLFAC3_bp 3 /* Multiplication Factor bit 3 position. */ -#define OSC_PLLFAC4_bm (1<<4) /* Multiplication Factor bit 4 mask. */ -#define OSC_PLLFAC4_bp 4 /* Multiplication Factor bit 4 position. */ - -/* OSC.DFLLCTRL bit masks and bit positions */ -#define OSC_RC32MCREF_gm 0x06 /* 32 MHz DFLL Calibration Reference group mask. */ -#define OSC_RC32MCREF_gp 1 /* 32 MHz DFLL Calibration Reference group position. */ -#define OSC_RC32MCREF0_bm (1<<1) /* 32 MHz DFLL Calibration Reference bit 0 mask. */ -#define OSC_RC32MCREF0_bp 1 /* 32 MHz DFLL Calibration Reference bit 0 position. */ -#define OSC_RC32MCREF1_bm (1<<2) /* 32 MHz DFLL Calibration Reference bit 1 mask. */ -#define OSC_RC32MCREF1_bp 2 /* 32 MHz DFLL Calibration Reference bit 1 position. */ - -#define OSC_RC2MCREF_bm 0x01 /* 2 MHz DFLL Calibration Reference bit mask. */ -#define OSC_RC2MCREF_bp 0 /* 2 MHz DFLL Calibration Reference bit position. */ - -/* DFLL - DFLL */ -/* DFLL.CTRL bit masks and bit positions */ -#define DFLL_ENABLE_bm 0x01 /* DFLL Enable bit mask. */ -#define DFLL_ENABLE_bp 0 /* DFLL Enable bit position. */ - -/* DFLL.CALA bit masks and bit positions */ -#define DFLL_CALL_gm 0x7F /* DFLL Calibration Value A group mask. */ -#define DFLL_CALL_gp 0 /* DFLL Calibration Value A group position. */ -#define DFLL_CALL0_bm (1<<0) /* DFLL Calibration Value A bit 0 mask. */ -#define DFLL_CALL0_bp 0 /* DFLL Calibration Value A bit 0 position. */ -#define DFLL_CALL1_bm (1<<1) /* DFLL Calibration Value A bit 1 mask. */ -#define DFLL_CALL1_bp 1 /* DFLL Calibration Value A bit 1 position. */ -#define DFLL_CALL2_bm (1<<2) /* DFLL Calibration Value A bit 2 mask. */ -#define DFLL_CALL2_bp 2 /* DFLL Calibration Value A bit 2 position. */ -#define DFLL_CALL3_bm (1<<3) /* DFLL Calibration Value A bit 3 mask. */ -#define DFLL_CALL3_bp 3 /* DFLL Calibration Value A bit 3 position. */ -#define DFLL_CALL4_bm (1<<4) /* DFLL Calibration Value A bit 4 mask. */ -#define DFLL_CALL4_bp 4 /* DFLL Calibration Value A bit 4 position. */ -#define DFLL_CALL5_bm (1<<5) /* DFLL Calibration Value A bit 5 mask. */ -#define DFLL_CALL5_bp 5 /* DFLL Calibration Value A bit 5 position. */ -#define DFLL_CALL6_bm (1<<6) /* DFLL Calibration Value A bit 6 mask. */ -#define DFLL_CALL6_bp 6 /* DFLL Calibration Value A bit 6 position. */ - -/* DFLL.CALB bit masks and bit positions */ -#define DFLL_CALH_gm 0x3F /* DFLL Calibration Value B group mask. */ -#define DFLL_CALH_gp 0 /* DFLL Calibration Value B group position. */ -#define DFLL_CALH0_bm (1<<0) /* DFLL Calibration Value B bit 0 mask. */ -#define DFLL_CALH0_bp 0 /* DFLL Calibration Value B bit 0 position. */ -#define DFLL_CALH1_bm (1<<1) /* DFLL Calibration Value B bit 1 mask. */ -#define DFLL_CALH1_bp 1 /* DFLL Calibration Value B bit 1 position. */ -#define DFLL_CALH2_bm (1<<2) /* DFLL Calibration Value B bit 2 mask. */ -#define DFLL_CALH2_bp 2 /* DFLL Calibration Value B bit 2 position. */ -#define DFLL_CALH3_bm (1<<3) /* DFLL Calibration Value B bit 3 mask. */ -#define DFLL_CALH3_bp 3 /* DFLL Calibration Value B bit 3 position. */ -#define DFLL_CALH4_bm (1<<4) /* DFLL Calibration Value B bit 4 mask. */ -#define DFLL_CALH4_bp 4 /* DFLL Calibration Value B bit 4 position. */ -#define DFLL_CALH5_bm (1<<5) /* DFLL Calibration Value B bit 5 mask. */ -#define DFLL_CALH5_bp 5 /* DFLL Calibration Value B bit 5 position. */ - -/* RST - Reset */ -/* RST.STATUS bit masks and bit positions */ -#define RST_SDRF_bm 0x40 /* Spike Detection Reset Flag bit mask. */ -#define RST_SDRF_bp 6 /* Spike Detection Reset Flag bit position. */ - -#define RST_SRF_bm 0x20 /* Software Reset Flag bit mask. */ -#define RST_SRF_bp 5 /* Software Reset Flag bit position. */ - -#define RST_PDIRF_bm 0x10 /* Programming and Debug Interface Interface Reset Flag bit mask. */ -#define RST_PDIRF_bp 4 /* Programming and Debug Interface Interface Reset Flag bit position. */ - -#define RST_WDRF_bm 0x08 /* Watchdog Reset Flag bit mask. */ -#define RST_WDRF_bp 3 /* Watchdog Reset Flag bit position. */ - -#define RST_BORF_bm 0x04 /* Brown-out Reset Flag bit mask. */ -#define RST_BORF_bp 2 /* Brown-out Reset Flag bit position. */ - -#define RST_EXTRF_bm 0x02 /* External Reset Flag bit mask. */ -#define RST_EXTRF_bp 1 /* External Reset Flag bit position. */ - -#define RST_PORF_bm 0x01 /* Power-on Reset Flag bit mask. */ -#define RST_PORF_bp 0 /* Power-on Reset Flag bit position. */ - -/* RST.CTRL bit masks and bit positions */ -#define RST_SWRST_bm 0x01 /* Software Reset bit mask. */ -#define RST_SWRST_bp 0 /* Software Reset bit position. */ - -/* WDT - Watch-Dog Timer */ -/* WDT.CTRL bit masks and bit positions */ -#define WDT_PER_gm 0x3C /* Period group mask. */ -#define WDT_PER_gp 2 /* Period group position. */ -#define WDT_PER0_bm (1<<2) /* Period bit 0 mask. */ -#define WDT_PER0_bp 2 /* Period bit 0 position. */ -#define WDT_PER1_bm (1<<3) /* Period bit 1 mask. */ -#define WDT_PER1_bp 3 /* Period bit 1 position. */ -#define WDT_PER2_bm (1<<4) /* Period bit 2 mask. */ -#define WDT_PER2_bp 4 /* Period bit 2 position. */ -#define WDT_PER3_bm (1<<5) /* Period bit 3 mask. */ -#define WDT_PER3_bp 5 /* Period bit 3 position. */ - -#define WDT_ENABLE_bm 0x02 /* Enable bit mask. */ -#define WDT_ENABLE_bp 1 /* Enable bit position. */ - -#define WDT_CEN_bm 0x01 /* Change Enable bit mask. */ -#define WDT_CEN_bp 0 /* Change Enable bit position. */ - -/* WDT.WINCTRL bit masks and bit positions */ -#define WDT_WPER_gm 0x3C /* Windowed Mode Period group mask. */ -#define WDT_WPER_gp 2 /* Windowed Mode Period group position. */ -#define WDT_WPER0_bm (1<<2) /* Windowed Mode Period bit 0 mask. */ -#define WDT_WPER0_bp 2 /* Windowed Mode Period bit 0 position. */ -#define WDT_WPER1_bm (1<<3) /* Windowed Mode Period bit 1 mask. */ -#define WDT_WPER1_bp 3 /* Windowed Mode Period bit 1 position. */ -#define WDT_WPER2_bm (1<<4) /* Windowed Mode Period bit 2 mask. */ -#define WDT_WPER2_bp 4 /* Windowed Mode Period bit 2 position. */ -#define WDT_WPER3_bm (1<<5) /* Windowed Mode Period bit 3 mask. */ -#define WDT_WPER3_bp 5 /* Windowed Mode Period bit 3 position. */ - -#define WDT_WEN_bm 0x02 /* Windowed Mode Enable bit mask. */ -#define WDT_WEN_bp 1 /* Windowed Mode Enable bit position. */ - -#define WDT_WCEN_bm 0x01 /* Windowed Mode Change Enable bit mask. */ -#define WDT_WCEN_bp 0 /* Windowed Mode Change Enable bit position. */ - -/* WDT.STATUS bit masks and bit positions */ -#define WDT_SYNCBUSY_bm 0x01 /* Syncronization busy bit mask. */ -#define WDT_SYNCBUSY_bp 0 /* Syncronization busy bit position. */ - -/* MCU - MCU Control */ -/* MCU.ANAINIT bit masks and bit positions */ -#define MCU_STARTUPDLYA_gm 0x03 /* Analog startup delay Port A group mask. */ -#define MCU_STARTUPDLYA_gp 0 /* Analog startup delay Port A group position. */ -#define MCU_STARTUPDLYA0_bm (1<<0) /* Analog startup delay Port A bit 0 mask. */ -#define MCU_STARTUPDLYA0_bp 0 /* Analog startup delay Port A bit 0 position. */ -#define MCU_STARTUPDLYA1_bm (1<<1) /* Analog startup delay Port A bit 1 mask. */ -#define MCU_STARTUPDLYA1_bp 1 /* Analog startup delay Port A bit 1 position. */ - -/* MCU.EVSYSLOCK bit masks and bit positions */ -#define MCU_EVSYS0LOCK_bm 0x01 /* Event Channel 0-3 Lock bit mask. */ -#define MCU_EVSYS0LOCK_bp 0 /* Event Channel 0-3 Lock bit position. */ - -/* MCU.AWEXLOCK bit masks and bit positions */ -#define MCU_AWEXCLOCK_bm 0x01 /* AWeX on T/C C0 Lock bit mask. */ -#define MCU_AWEXCLOCK_bp 0 /* AWeX on T/C C0 Lock bit position. */ - -/* PMIC - Programmable Multi-level Interrupt Controller */ -/* PMIC.STATUS bit masks and bit positions */ -#define PMIC_NMIEX_bm 0x80 /* Non-maskable Interrupt Executing bit mask. */ -#define PMIC_NMIEX_bp 7 /* Non-maskable Interrupt Executing bit position. */ - -#define PMIC_HILVLEX_bm 0x04 /* High Level Interrupt Executing bit mask. */ -#define PMIC_HILVLEX_bp 2 /* High Level Interrupt Executing bit position. */ - -#define PMIC_MEDLVLEX_bm 0x02 /* Medium Level Interrupt Executing bit mask. */ -#define PMIC_MEDLVLEX_bp 1 /* Medium Level Interrupt Executing bit position. */ - -#define PMIC_LOLVLEX_bm 0x01 /* Low Level Interrupt Executing bit mask. */ -#define PMIC_LOLVLEX_bp 0 /* Low Level Interrupt Executing bit position. */ - -/* PMIC.INTPRI bit masks and bit positions */ -#define PMIC_INTPRI_gm 0xFF /* Interrupt Priority group mask. */ -#define PMIC_INTPRI_gp 0 /* Interrupt Priority group position. */ -#define PMIC_INTPRI0_bm (1<<0) /* Interrupt Priority bit 0 mask. */ -#define PMIC_INTPRI0_bp 0 /* Interrupt Priority bit 0 position. */ -#define PMIC_INTPRI1_bm (1<<1) /* Interrupt Priority bit 1 mask. */ -#define PMIC_INTPRI1_bp 1 /* Interrupt Priority bit 1 position. */ -#define PMIC_INTPRI2_bm (1<<2) /* Interrupt Priority bit 2 mask. */ -#define PMIC_INTPRI2_bp 2 /* Interrupt Priority bit 2 position. */ -#define PMIC_INTPRI3_bm (1<<3) /* Interrupt Priority bit 3 mask. */ -#define PMIC_INTPRI3_bp 3 /* Interrupt Priority bit 3 position. */ -#define PMIC_INTPRI4_bm (1<<4) /* Interrupt Priority bit 4 mask. */ -#define PMIC_INTPRI4_bp 4 /* Interrupt Priority bit 4 position. */ -#define PMIC_INTPRI5_bm (1<<5) /* Interrupt Priority bit 5 mask. */ -#define PMIC_INTPRI5_bp 5 /* Interrupt Priority bit 5 position. */ -#define PMIC_INTPRI6_bm (1<<6) /* Interrupt Priority bit 6 mask. */ -#define PMIC_INTPRI6_bp 6 /* Interrupt Priority bit 6 position. */ -#define PMIC_INTPRI7_bm (1<<7) /* Interrupt Priority bit 7 mask. */ -#define PMIC_INTPRI7_bp 7 /* Interrupt Priority bit 7 position. */ - -/* PMIC.CTRL bit masks and bit positions */ -#define PMIC_RREN_bm 0x80 /* Round-Robin Priority Enable bit mask. */ -#define PMIC_RREN_bp 7 /* Round-Robin Priority Enable bit position. */ - -#define PMIC_IVSEL_bm 0x40 /* Interrupt Vector Select bit mask. */ -#define PMIC_IVSEL_bp 6 /* Interrupt Vector Select bit position. */ - -#define PMIC_HILVLEN_bm 0x04 /* High Level Enable bit mask. */ -#define PMIC_HILVLEN_bp 2 /* High Level Enable bit position. */ - -#define PMIC_MEDLVLEN_bm 0x02 /* Medium Level Enable bit mask. */ -#define PMIC_MEDLVLEN_bp 1 /* Medium Level Enable bit position. */ - -#define PMIC_LOLVLEN_bm 0x01 /* Low Level Enable bit mask. */ -#define PMIC_LOLVLEN_bp 0 /* Low Level Enable bit position. */ - -/* PORTCFG - Port Configuration */ -/* PORTCFG.VPCTRLA bit masks and bit positions */ -#define PORTCFG_VP1MAP_gm 0xF0 /* Virtual Port 1 Mapping group mask. */ -#define PORTCFG_VP1MAP_gp 4 /* Virtual Port 1 Mapping group position. */ -#define PORTCFG_VP1MAP0_bm (1<<4) /* Virtual Port 1 Mapping bit 0 mask. */ -#define PORTCFG_VP1MAP0_bp 4 /* Virtual Port 1 Mapping bit 0 position. */ -#define PORTCFG_VP1MAP1_bm (1<<5) /* Virtual Port 1 Mapping bit 1 mask. */ -#define PORTCFG_VP1MAP1_bp 5 /* Virtual Port 1 Mapping bit 1 position. */ -#define PORTCFG_VP1MAP2_bm (1<<6) /* Virtual Port 1 Mapping bit 2 mask. */ -#define PORTCFG_VP1MAP2_bp 6 /* Virtual Port 1 Mapping bit 2 position. */ -#define PORTCFG_VP1MAP3_bm (1<<7) /* Virtual Port 1 Mapping bit 3 mask. */ -#define PORTCFG_VP1MAP3_bp 7 /* Virtual Port 1 Mapping bit 3 position. */ - -#define PORTCFG_VP0MAP_gm 0x0F /* Virtual Port 0 Mapping group mask. */ -#define PORTCFG_VP0MAP_gp 0 /* Virtual Port 0 Mapping group position. */ -#define PORTCFG_VP0MAP0_bm (1<<0) /* Virtual Port 0 Mapping bit 0 mask. */ -#define PORTCFG_VP0MAP0_bp 0 /* Virtual Port 0 Mapping bit 0 position. */ -#define PORTCFG_VP0MAP1_bm (1<<1) /* Virtual Port 0 Mapping bit 1 mask. */ -#define PORTCFG_VP0MAP1_bp 1 /* Virtual Port 0 Mapping bit 1 position. */ -#define PORTCFG_VP0MAP2_bm (1<<2) /* Virtual Port 0 Mapping bit 2 mask. */ -#define PORTCFG_VP0MAP2_bp 2 /* Virtual Port 0 Mapping bit 2 position. */ -#define PORTCFG_VP0MAP3_bm (1<<3) /* Virtual Port 0 Mapping bit 3 mask. */ -#define PORTCFG_VP0MAP3_bp 3 /* Virtual Port 0 Mapping bit 3 position. */ - -/* PORTCFG.VPCTRLB bit masks and bit positions */ -#define PORTCFG_VP3MAP_gm 0xF0 /* Virtual Port 3 Mapping group mask. */ -#define PORTCFG_VP3MAP_gp 4 /* Virtual Port 3 Mapping group position. */ -#define PORTCFG_VP3MAP0_bm (1<<4) /* Virtual Port 3 Mapping bit 0 mask. */ -#define PORTCFG_VP3MAP0_bp 4 /* Virtual Port 3 Mapping bit 0 position. */ -#define PORTCFG_VP3MAP1_bm (1<<5) /* Virtual Port 3 Mapping bit 1 mask. */ -#define PORTCFG_VP3MAP1_bp 5 /* Virtual Port 3 Mapping bit 1 position. */ -#define PORTCFG_VP3MAP2_bm (1<<6) /* Virtual Port 3 Mapping bit 2 mask. */ -#define PORTCFG_VP3MAP2_bp 6 /* Virtual Port 3 Mapping bit 2 position. */ -#define PORTCFG_VP3MAP3_bm (1<<7) /* Virtual Port 3 Mapping bit 3 mask. */ -#define PORTCFG_VP3MAP3_bp 7 /* Virtual Port 3 Mapping bit 3 position. */ - -#define PORTCFG_VP2MAP_gm 0x0F /* Virtual Port 2 Mapping group mask. */ -#define PORTCFG_VP2MAP_gp 0 /* Virtual Port 2 Mapping group position. */ -#define PORTCFG_VP2MAP0_bm (1<<0) /* Virtual Port 2 Mapping bit 0 mask. */ -#define PORTCFG_VP2MAP0_bp 0 /* Virtual Port 2 Mapping bit 0 position. */ -#define PORTCFG_VP2MAP1_bm (1<<1) /* Virtual Port 2 Mapping bit 1 mask. */ -#define PORTCFG_VP2MAP1_bp 1 /* Virtual Port 2 Mapping bit 1 position. */ -#define PORTCFG_VP2MAP2_bm (1<<2) /* Virtual Port 2 Mapping bit 2 mask. */ -#define PORTCFG_VP2MAP2_bp 2 /* Virtual Port 2 Mapping bit 2 position. */ -#define PORTCFG_VP2MAP3_bm (1<<3) /* Virtual Port 2 Mapping bit 3 mask. */ -#define PORTCFG_VP2MAP3_bp 3 /* Virtual Port 2 Mapping bit 3 position. */ - -/* PORTCFG.CLKEVOUT bit masks and bit positions */ -#define PORTCFG_CLKOUT_gm 0x03 /* Peripheral Clock Output Port group mask. */ -#define PORTCFG_CLKOUT_gp 0 /* Peripheral Clock Output Port group position. */ -#define PORTCFG_CLKOUT0_bm (1<<0) /* Peripheral Clock Output Port bit 0 mask. */ -#define PORTCFG_CLKOUT0_bp 0 /* Peripheral Clock Output Port bit 0 position. */ -#define PORTCFG_CLKOUT1_bm (1<<1) /* Peripheral Clock Output Port bit 1 mask. */ -#define PORTCFG_CLKOUT1_bp 1 /* Peripheral Clock Output Port bit 1 position. */ - -#define PORTCFG_CLKOUTSEL_gm 0x0C /* Peripheral Clock Output Select group mask. */ -#define PORTCFG_CLKOUTSEL_gp 2 /* Peripheral Clock Output Select group position. */ -#define PORTCFG_CLKOUTSEL0_bm (1<<2) /* Peripheral Clock Output Select bit 0 mask. */ -#define PORTCFG_CLKOUTSEL0_bp 2 /* Peripheral Clock Output Select bit 0 position. */ -#define PORTCFG_CLKOUTSEL1_bm (1<<3) /* Peripheral Clock Output Select bit 1 mask. */ -#define PORTCFG_CLKOUTSEL1_bp 3 /* Peripheral Clock Output Select bit 1 position. */ - -#define PORTCFG_EVOUT_gm 0x30 /* Event Output Port group mask. */ -#define PORTCFG_EVOUT_gp 4 /* Event Output Port group position. */ -#define PORTCFG_EVOUT0_bm (1<<4) /* Event Output Port bit 0 mask. */ -#define PORTCFG_EVOUT0_bp 4 /* Event Output Port bit 0 position. */ -#define PORTCFG_EVOUT1_bm (1<<5) /* Event Output Port bit 1 mask. */ -#define PORTCFG_EVOUT1_bp 5 /* Event Output Port bit 1 position. */ - -#define PORTCFG_RTCOUT_bm 0x40 /* RTC Clock Output bit mask. */ -#define PORTCFG_RTCOUT_bp 6 /* RTC Clock Output bit position. */ - -#define PORTCFG_CLKEVPIN_bm 0x80 /* Peripheral Clock and Event Output pin Select bit mask. */ -#define PORTCFG_CLKEVPIN_bp 7 /* Peripheral Clock and Event Output pin Select bit position. */ - -/* PORTCFG.EVOUTSEL bit masks and bit positions */ -#define PORTCFG_EVOUTSEL_gm 0x07 /* Event Output Select group mask. */ -#define PORTCFG_EVOUTSEL_gp 0 /* Event Output Select group position. */ -#define PORTCFG_EVOUTSEL0_bm (1<<0) /* Event Output Select bit 0 mask. */ -#define PORTCFG_EVOUTSEL0_bp 0 /* Event Output Select bit 0 position. */ -#define PORTCFG_EVOUTSEL1_bm (1<<1) /* Event Output Select bit 1 mask. */ -#define PORTCFG_EVOUTSEL1_bp 1 /* Event Output Select bit 1 position. */ -#define PORTCFG_EVOUTSEL2_bm (1<<2) /* Event Output Select bit 2 mask. */ -#define PORTCFG_EVOUTSEL2_bp 2 /* Event Output Select bit 2 position. */ - -/* CRC - Cyclic Redundancy Checker */ -/* CRC.CTRL bit masks and bit positions */ -#define CRC_RESET_gm 0xC0 /* Reset group mask. */ -#define CRC_RESET_gp 6 /* Reset group position. */ -#define CRC_RESET0_bm (1<<6) /* Reset bit 0 mask. */ -#define CRC_RESET0_bp 6 /* Reset bit 0 position. */ -#define CRC_RESET1_bm (1<<7) /* Reset bit 1 mask. */ -#define CRC_RESET1_bp 7 /* Reset bit 1 position. */ - -#define CRC_CRC32_bm 0x20 /* CRC Mode bit mask. */ -#define CRC_CRC32_bp 5 /* CRC Mode bit position. */ - -#define CRC_SOURCE_gm 0x0F /* Input Source group mask. */ -#define CRC_SOURCE_gp 0 /* Input Source group position. */ -#define CRC_SOURCE0_bm (1<<0) /* Input Source bit 0 mask. */ -#define CRC_SOURCE0_bp 0 /* Input Source bit 0 position. */ -#define CRC_SOURCE1_bm (1<<1) /* Input Source bit 1 mask. */ -#define CRC_SOURCE1_bp 1 /* Input Source bit 1 position. */ -#define CRC_SOURCE2_bm (1<<2) /* Input Source bit 2 mask. */ -#define CRC_SOURCE2_bp 2 /* Input Source bit 2 position. */ -#define CRC_SOURCE3_bm (1<<3) /* Input Source bit 3 mask. */ -#define CRC_SOURCE3_bp 3 /* Input Source bit 3 position. */ - -/* CRC.STATUS bit masks and bit positions */ -#define CRC_ZERO_bm 0x02 /* Zero detection bit mask. */ -#define CRC_ZERO_bp 1 /* Zero detection bit position. */ - -#define CRC_BUSY_bm 0x01 /* Busy bit mask. */ -#define CRC_BUSY_bp 0 /* Busy bit position. */ - -/* EVSYS - Event System */ -/* EVSYS.CH0MUX bit masks and bit positions */ -#define EVSYS_CHMUX_gm 0xFF /* Event Channel 0 Multiplexer group mask. */ -#define EVSYS_CHMUX_gp 0 /* Event Channel 0 Multiplexer group position. */ -#define EVSYS_CHMUX0_bm (1<<0) /* Event Channel 0 Multiplexer bit 0 mask. */ -#define EVSYS_CHMUX0_bp 0 /* Event Channel 0 Multiplexer bit 0 position. */ -#define EVSYS_CHMUX1_bm (1<<1) /* Event Channel 0 Multiplexer bit 1 mask. */ -#define EVSYS_CHMUX1_bp 1 /* Event Channel 0 Multiplexer bit 1 position. */ -#define EVSYS_CHMUX2_bm (1<<2) /* Event Channel 0 Multiplexer bit 2 mask. */ -#define EVSYS_CHMUX2_bp 2 /* Event Channel 0 Multiplexer bit 2 position. */ -#define EVSYS_CHMUX3_bm (1<<3) /* Event Channel 0 Multiplexer bit 3 mask. */ -#define EVSYS_CHMUX3_bp 3 /* Event Channel 0 Multiplexer bit 3 position. */ -#define EVSYS_CHMUX4_bm (1<<4) /* Event Channel 0 Multiplexer bit 4 mask. */ -#define EVSYS_CHMUX4_bp 4 /* Event Channel 0 Multiplexer bit 4 position. */ -#define EVSYS_CHMUX5_bm (1<<5) /* Event Channel 0 Multiplexer bit 5 mask. */ -#define EVSYS_CHMUX5_bp 5 /* Event Channel 0 Multiplexer bit 5 position. */ -#define EVSYS_CHMUX6_bm (1<<6) /* Event Channel 0 Multiplexer bit 6 mask. */ -#define EVSYS_CHMUX6_bp 6 /* Event Channel 0 Multiplexer bit 6 position. */ -#define EVSYS_CHMUX7_bm (1<<7) /* Event Channel 0 Multiplexer bit 7 mask. */ -#define EVSYS_CHMUX7_bp 7 /* Event Channel 0 Multiplexer bit 7 position. */ - -/* EVSYS.CH1MUX bit masks and bit positions */ -/* EVSYS_CHMUX Predefined. */ -/* EVSYS_CHMUX Predefined. */ - -/* EVSYS.CH2MUX bit masks and bit positions */ -/* EVSYS_CHMUX Predefined. */ -/* EVSYS_CHMUX Predefined. */ - -/* EVSYS.CH3MUX bit masks and bit positions */ -/* EVSYS_CHMUX Predefined. */ -/* EVSYS_CHMUX Predefined. */ - -/* EVSYS.CH0CTRL bit masks and bit positions */ -#define EVSYS_QDIRM_gm 0x60 /* Quadrature Decoder Index Recognition Mode group mask. */ -#define EVSYS_QDIRM_gp 5 /* Quadrature Decoder Index Recognition Mode group position. */ -#define EVSYS_QDIRM0_bm (1<<5) /* Quadrature Decoder Index Recognition Mode bit 0 mask. */ -#define EVSYS_QDIRM0_bp 5 /* Quadrature Decoder Index Recognition Mode bit 0 position. */ -#define EVSYS_QDIRM1_bm (1<<6) /* Quadrature Decoder Index Recognition Mode bit 1 mask. */ -#define EVSYS_QDIRM1_bp 6 /* Quadrature Decoder Index Recognition Mode bit 1 position. */ - -#define EVSYS_QDIEN_bm 0x10 /* Quadrature Decoder Index Enable bit mask. */ -#define EVSYS_QDIEN_bp 4 /* Quadrature Decoder Index Enable bit position. */ - -#define EVSYS_QDEN_bm 0x08 /* Quadrature Decoder Enable bit mask. */ -#define EVSYS_QDEN_bp 3 /* Quadrature Decoder Enable bit position. */ - -#define EVSYS_DIGFILT_gm 0x07 /* Digital Filter group mask. */ -#define EVSYS_DIGFILT_gp 0 /* Digital Filter group position. */ -#define EVSYS_DIGFILT0_bm (1<<0) /* Digital Filter bit 0 mask. */ -#define EVSYS_DIGFILT0_bp 0 /* Digital Filter bit 0 position. */ -#define EVSYS_DIGFILT1_bm (1<<1) /* Digital Filter bit 1 mask. */ -#define EVSYS_DIGFILT1_bp 1 /* Digital Filter bit 1 position. */ -#define EVSYS_DIGFILT2_bm (1<<2) /* Digital Filter bit 2 mask. */ -#define EVSYS_DIGFILT2_bp 2 /* Digital Filter bit 2 position. */ - -/* EVSYS.CH1CTRL bit masks and bit positions */ -/* EVSYS_DIGFILT Predefined. */ -/* EVSYS_DIGFILT Predefined. */ - -/* EVSYS.CH2CTRL bit masks and bit positions */ -/* EVSYS_DIGFILT Predefined. */ -/* EVSYS_DIGFILT Predefined. */ - -/* EVSYS.CH3CTRL bit masks and bit positions */ -/* EVSYS_DIGFILT Predefined. */ -/* EVSYS_DIGFILT Predefined. */ - -/* NVM - Non Volatile Memory Controller */ -/* NVM.CMD bit masks and bit positions */ -#define NVM_CMD_gm 0x7F /* Command group mask. */ -#define NVM_CMD_gp 0 /* Command group position. */ -#define NVM_CMD0_bm (1<<0) /* Command bit 0 mask. */ -#define NVM_CMD0_bp 0 /* Command bit 0 position. */ -#define NVM_CMD1_bm (1<<1) /* Command bit 1 mask. */ -#define NVM_CMD1_bp 1 /* Command bit 1 position. */ -#define NVM_CMD2_bm (1<<2) /* Command bit 2 mask. */ -#define NVM_CMD2_bp 2 /* Command bit 2 position. */ -#define NVM_CMD3_bm (1<<3) /* Command bit 3 mask. */ -#define NVM_CMD3_bp 3 /* Command bit 3 position. */ -#define NVM_CMD4_bm (1<<4) /* Command bit 4 mask. */ -#define NVM_CMD4_bp 4 /* Command bit 4 position. */ -#define NVM_CMD5_bm (1<<5) /* Command bit 5 mask. */ -#define NVM_CMD5_bp 5 /* Command bit 5 position. */ -#define NVM_CMD6_bm (1<<6) /* Command bit 6 mask. */ -#define NVM_CMD6_bp 6 /* Command bit 6 position. */ - -/* NVM.CTRLA bit masks and bit positions */ -#define NVM_CMDEX_bm 0x01 /* Command Execute bit mask. */ -#define NVM_CMDEX_bp 0 /* Command Execute bit position. */ - -/* NVM.CTRLB bit masks and bit positions */ -#define NVM_EEMAPEN_bm 0x08 /* EEPROM Mapping Enable bit mask. */ -#define NVM_EEMAPEN_bp 3 /* EEPROM Mapping Enable bit position. */ - -#define NVM_FPRM_bm 0x04 /* Flash Power Reduction Enable bit mask. */ -#define NVM_FPRM_bp 2 /* Flash Power Reduction Enable bit position. */ - -#define NVM_EPRM_bm 0x02 /* EEPROM Power Reduction Enable bit mask. */ -#define NVM_EPRM_bp 1 /* EEPROM Power Reduction Enable bit position. */ - -#define NVM_SPMLOCK_bm 0x01 /* SPM Lock bit mask. */ -#define NVM_SPMLOCK_bp 0 /* SPM Lock bit position. */ - -/* NVM.INTCTRL bit masks and bit positions */ -#define NVM_SPMLVL_gm 0x0C /* SPM Interrupt Level group mask. */ -#define NVM_SPMLVL_gp 2 /* SPM Interrupt Level group position. */ -#define NVM_SPMLVL0_bm (1<<2) /* SPM Interrupt Level bit 0 mask. */ -#define NVM_SPMLVL0_bp 2 /* SPM Interrupt Level bit 0 position. */ -#define NVM_SPMLVL1_bm (1<<3) /* SPM Interrupt Level bit 1 mask. */ -#define NVM_SPMLVL1_bp 3 /* SPM Interrupt Level bit 1 position. */ - -#define NVM_EELVL_gm 0x03 /* EEPROM Interrupt Level group mask. */ -#define NVM_EELVL_gp 0 /* EEPROM Interrupt Level group position. */ -#define NVM_EELVL0_bm (1<<0) /* EEPROM Interrupt Level bit 0 mask. */ -#define NVM_EELVL0_bp 0 /* EEPROM Interrupt Level bit 0 position. */ -#define NVM_EELVL1_bm (1<<1) /* EEPROM Interrupt Level bit 1 mask. */ -#define NVM_EELVL1_bp 1 /* EEPROM Interrupt Level bit 1 position. */ - -/* NVM.STATUS bit masks and bit positions */ -#define NVM_NVMBUSY_bm 0x80 /* Non-volatile Memory Busy bit mask. */ -#define NVM_NVMBUSY_bp 7 /* Non-volatile Memory Busy bit position. */ - -#define NVM_FBUSY_bm 0x40 /* Flash Memory Busy bit mask. */ -#define NVM_FBUSY_bp 6 /* Flash Memory Busy bit position. */ - -#define NVM_EELOAD_bm 0x02 /* EEPROM Page Buffer Active Loading bit mask. */ -#define NVM_EELOAD_bp 1 /* EEPROM Page Buffer Active Loading bit position. */ - -#define NVM_FLOAD_bm 0x01 /* Flash Page Buffer Active Loading bit mask. */ -#define NVM_FLOAD_bp 0 /* Flash Page Buffer Active Loading bit position. */ - -/* NVM.LOCKBITS bit masks and bit positions */ -#define NVM_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ -#define NVM_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ -#define NVM_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ -#define NVM_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ -#define NVM_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ -#define NVM_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ - -#define NVM_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ -#define NVM_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ -#define NVM_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ -#define NVM_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ -#define NVM_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ -#define NVM_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ - -#define NVM_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ -#define NVM_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ -#define NVM_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ -#define NVM_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ -#define NVM_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ -#define NVM_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ - -#define NVM_LB_gm 0x03 /* Lock Bits group mask. */ -#define NVM_LB_gp 0 /* Lock Bits group position. */ -#define NVM_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ -#define NVM_LB0_bp 0 /* Lock Bits bit 0 position. */ -#define NVM_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ -#define NVM_LB1_bp 1 /* Lock Bits bit 1 position. */ - -/* ADC - Analog/Digital Converter */ -/* ADC_CH.CTRL bit masks and bit positions */ -#define ADC_CH_START_bm 0x80 /* Channel Start Conversion bit mask. */ -#define ADC_CH_START_bp 7 /* Channel Start Conversion bit position. */ - -#define ADC_CH_GAIN_gm 0x1C /* Gain Factor group mask. */ -#define ADC_CH_GAIN_gp 2 /* Gain Factor group position. */ -#define ADC_CH_GAIN0_bm (1<<2) /* Gain Factor bit 0 mask. */ -#define ADC_CH_GAIN0_bp 2 /* Gain Factor bit 0 position. */ -#define ADC_CH_GAIN1_bm (1<<3) /* Gain Factor bit 1 mask. */ -#define ADC_CH_GAIN1_bp 3 /* Gain Factor bit 1 position. */ -#define ADC_CH_GAIN2_bm (1<<4) /* Gain Factor bit 2 mask. */ -#define ADC_CH_GAIN2_bp 4 /* Gain Factor bit 2 position. */ - -#define ADC_CH_INPUTMODE_gm 0x03 /* Input Mode Select group mask. */ -#define ADC_CH_INPUTMODE_gp 0 /* Input Mode Select group position. */ -#define ADC_CH_INPUTMODE0_bm (1<<0) /* Input Mode Select bit 0 mask. */ -#define ADC_CH_INPUTMODE0_bp 0 /* Input Mode Select bit 0 position. */ -#define ADC_CH_INPUTMODE1_bm (1<<1) /* Input Mode Select bit 1 mask. */ -#define ADC_CH_INPUTMODE1_bp 1 /* Input Mode Select bit 1 position. */ - -/* ADC_CH.MUXCTRL bit masks and bit positions */ -#define ADC_CH_MUXPOS_gm 0x78 /* MUX selection on Positive ADC input group mask. */ -#define ADC_CH_MUXPOS_gp 3 /* MUX selection on Positive ADC input group position. */ -#define ADC_CH_MUXPOS0_bm (1<<3) /* MUX selection on Positive ADC input bit 0 mask. */ -#define ADC_CH_MUXPOS0_bp 3 /* MUX selection on Positive ADC input bit 0 position. */ -#define ADC_CH_MUXPOS1_bm (1<<4) /* MUX selection on Positive ADC input bit 1 mask. */ -#define ADC_CH_MUXPOS1_bp 4 /* MUX selection on Positive ADC input bit 1 position. */ -#define ADC_CH_MUXPOS2_bm (1<<5) /* MUX selection on Positive ADC input bit 2 mask. */ -#define ADC_CH_MUXPOS2_bp 5 /* MUX selection on Positive ADC input bit 2 position. */ -#define ADC_CH_MUXPOS3_bm (1<<6) /* MUX selection on Positive ADC input bit 3 mask. */ -#define ADC_CH_MUXPOS3_bp 6 /* MUX selection on Positive ADC input bit 3 position. */ - -#define ADC_CH_MUXINT_gm 0x78 /* MUX selection on Internal ADC input group mask. */ -#define ADC_CH_MUXINT_gp 3 /* MUX selection on Internal ADC input group position. */ -#define ADC_CH_MUXINT0_bm (1<<3) /* MUX selection on Internal ADC input bit 0 mask. */ -#define ADC_CH_MUXINT0_bp 3 /* MUX selection on Internal ADC input bit 0 position. */ -#define ADC_CH_MUXINT1_bm (1<<4) /* MUX selection on Internal ADC input bit 1 mask. */ -#define ADC_CH_MUXINT1_bp 4 /* MUX selection on Internal ADC input bit 1 position. */ -#define ADC_CH_MUXINT2_bm (1<<5) /* MUX selection on Internal ADC input bit 2 mask. */ -#define ADC_CH_MUXINT2_bp 5 /* MUX selection on Internal ADC input bit 2 position. */ -#define ADC_CH_MUXINT3_bm (1<<6) /* MUX selection on Internal ADC input bit 3 mask. */ -#define ADC_CH_MUXINT3_bp 6 /* MUX selection on Internal ADC input bit 3 position. */ - -#define ADC_CH_MUXNEG_gm 0x03 /* MUX selection on Negative ADC input group mask. */ -#define ADC_CH_MUXNEG_gp 0 /* MUX selection on Negative ADC input group position. */ -#define ADC_CH_MUXNEG0_bm (1<<0) /* MUX selection on Negative ADC input bit 0 mask. */ -#define ADC_CH_MUXNEG0_bp 0 /* MUX selection on Negative ADC input bit 0 position. */ -#define ADC_CH_MUXNEG1_bm (1<<1) /* MUX selection on Negative ADC input bit 1 mask. */ -#define ADC_CH_MUXNEG1_bp 1 /* MUX selection on Negative ADC input bit 1 position. */ - -/* ADC_CH.INTCTRL bit masks and bit positions */ -#define ADC_CH_INTMODE_gm 0x0C /* Interrupt Mode group mask. */ -#define ADC_CH_INTMODE_gp 2 /* Interrupt Mode group position. */ -#define ADC_CH_INTMODE0_bm (1<<2) /* Interrupt Mode bit 0 mask. */ -#define ADC_CH_INTMODE0_bp 2 /* Interrupt Mode bit 0 position. */ -#define ADC_CH_INTMODE1_bm (1<<3) /* Interrupt Mode bit 1 mask. */ -#define ADC_CH_INTMODE1_bp 3 /* Interrupt Mode bit 1 position. */ - -#define ADC_CH_INTLVL_gm 0x03 /* Interrupt Level group mask. */ -#define ADC_CH_INTLVL_gp 0 /* Interrupt Level group position. */ -#define ADC_CH_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */ -#define ADC_CH_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */ -#define ADC_CH_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ -#define ADC_CH_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */ - -/* ADC_CH.INTFLAGS bit masks and bit positions */ -#define ADC_CH_CHIF_bm 0x01 /* Channel Interrupt Flag bit mask. */ -#define ADC_CH_CHIF_bp 0 /* Channel Interrupt Flag bit position. */ - -/* ADC_CH.SCAN bit masks and bit positions */ -#define ADC_CH_OFFSET_gm 0xF0 /* Positive MUX setting offset group mask. */ -#define ADC_CH_OFFSET_gp 4 /* Positive MUX setting offset group position. */ -#define ADC_CH_OFFSET0_bm (1<<4) /* Positive MUX setting offset bit 0 mask. */ -#define ADC_CH_OFFSET0_bp 4 /* Positive MUX setting offset bit 0 position. */ -#define ADC_CH_OFFSET1_bm (1<<5) /* Positive MUX setting offset bit 1 mask. */ -#define ADC_CH_OFFSET1_bp 5 /* Positive MUX setting offset bit 1 position. */ -#define ADC_CH_OFFSET2_bm (1<<6) /* Positive MUX setting offset bit 2 mask. */ -#define ADC_CH_OFFSET2_bp 6 /* Positive MUX setting offset bit 2 position. */ -#define ADC_CH_OFFSET3_bm (1<<7) /* Positive MUX setting offset bit 3 mask. */ -#define ADC_CH_OFFSET3_bp 7 /* Positive MUX setting offset bit 3 position. */ - -#define ADC_CH_SCANNUM_gm 0x0F /* Number of Channels included in scan group mask. */ -#define ADC_CH_SCANNUM_gp 0 /* Number of Channels included in scan group position. */ -#define ADC_CH_SCANNUM0_bm (1<<0) /* Number of Channels included in scan bit 0 mask. */ -#define ADC_CH_SCANNUM0_bp 0 /* Number of Channels included in scan bit 0 position. */ -#define ADC_CH_SCANNUM1_bm (1<<1) /* Number of Channels included in scan bit 1 mask. */ -#define ADC_CH_SCANNUM1_bp 1 /* Number of Channels included in scan bit 1 position. */ -#define ADC_CH_SCANNUM2_bm (1<<2) /* Number of Channels included in scan bit 2 mask. */ -#define ADC_CH_SCANNUM2_bp 2 /* Number of Channels included in scan bit 2 position. */ -#define ADC_CH_SCANNUM3_bm (1<<3) /* Number of Channels included in scan bit 3 mask. */ -#define ADC_CH_SCANNUM3_bp 3 /* Number of Channels included in scan bit 3 position. */ - -/* ADC.CTRLA bit masks and bit positions */ -#define ADC_CH0START_bm 0x04 /* Channel 0 Start Conversion bit mask. */ -#define ADC_CH0START_bp 2 /* Channel 0 Start Conversion bit position. */ - -#define ADC_FLUSH_bm 0x02 /* ADC Flush bit mask. */ -#define ADC_FLUSH_bp 1 /* ADC Flush bit position. */ - -#define ADC_ENABLE_bm 0x01 /* Enable ADC bit mask. */ -#define ADC_ENABLE_bp 0 /* Enable ADC bit position. */ - -/* ADC.CTRLB bit masks and bit positions */ -#define ADC_CURRLIMIT_gm 0x60 /* Current Limitation group mask. */ -#define ADC_CURRLIMIT_gp 5 /* Current Limitation group position. */ -#define ADC_CURRLIMIT0_bm (1<<5) /* Current Limitation bit 0 mask. */ -#define ADC_CURRLIMIT0_bp 5 /* Current Limitation bit 0 position. */ -#define ADC_CURRLIMIT1_bm (1<<6) /* Current Limitation bit 1 mask. */ -#define ADC_CURRLIMIT1_bp 6 /* Current Limitation bit 1 position. */ - -#define ADC_CONMODE_bm 0x10 /* Conversion Mode bit mask. */ -#define ADC_CONMODE_bp 4 /* Conversion Mode bit position. */ - -#define ADC_FREERUN_bm 0x08 /* Free Running Mode Enable bit mask. */ -#define ADC_FREERUN_bp 3 /* Free Running Mode Enable bit position. */ - -#define ADC_RESOLUTION_gm 0x06 /* Result Resolution group mask. */ -#define ADC_RESOLUTION_gp 1 /* Result Resolution group position. */ -#define ADC_RESOLUTION0_bm (1<<1) /* Result Resolution bit 0 mask. */ -#define ADC_RESOLUTION0_bp 1 /* Result Resolution bit 0 position. */ -#define ADC_RESOLUTION1_bm (1<<2) /* Result Resolution bit 1 mask. */ -#define ADC_RESOLUTION1_bp 2 /* Result Resolution bit 1 position. */ - -/* ADC.REFCTRL bit masks and bit positions */ -#define ADC_REFSEL_gm 0x70 /* Reference Selection group mask. */ -#define ADC_REFSEL_gp 4 /* Reference Selection group position. */ -#define ADC_REFSEL0_bm (1<<4) /* Reference Selection bit 0 mask. */ -#define ADC_REFSEL0_bp 4 /* Reference Selection bit 0 position. */ -#define ADC_REFSEL1_bm (1<<5) /* Reference Selection bit 1 mask. */ -#define ADC_REFSEL1_bp 5 /* Reference Selection bit 1 position. */ -#define ADC_REFSEL2_bm (1<<6) /* Reference Selection bit 2 mask. */ -#define ADC_REFSEL2_bp 6 /* Reference Selection bit 2 position. */ - -#define ADC_BANDGAP_bm 0x02 /* Bandgap enable bit mask. */ -#define ADC_BANDGAP_bp 1 /* Bandgap enable bit position. */ - -#define ADC_TEMPREF_bm 0x01 /* Temperature Reference Enable bit mask. */ -#define ADC_TEMPREF_bp 0 /* Temperature Reference Enable bit position. */ - -/* ADC.EVCTRL bit masks and bit positions */ -#define ADC_EVSEL_gm 0x18 /* Event Input Select group mask. */ -#define ADC_EVSEL_gp 3 /* Event Input Select group position. */ -#define ADC_EVSEL0_bm (1<<3) /* Event Input Select bit 0 mask. */ -#define ADC_EVSEL0_bp 3 /* Event Input Select bit 0 position. */ -#define ADC_EVSEL1_bm (1<<4) /* Event Input Select bit 1 mask. */ -#define ADC_EVSEL1_bp 4 /* Event Input Select bit 1 position. */ - -#define ADC_EVACT_gm 0x07 /* Event Action Select group mask. */ -#define ADC_EVACT_gp 0 /* Event Action Select group position. */ -#define ADC_EVACT0_bm (1<<0) /* Event Action Select bit 0 mask. */ -#define ADC_EVACT0_bp 0 /* Event Action Select bit 0 position. */ -#define ADC_EVACT1_bm (1<<1) /* Event Action Select bit 1 mask. */ -#define ADC_EVACT1_bp 1 /* Event Action Select bit 1 position. */ -#define ADC_EVACT2_bm (1<<2) /* Event Action Select bit 2 mask. */ -#define ADC_EVACT2_bp 2 /* Event Action Select bit 2 position. */ - -/* ADC.PRESCALER bit masks and bit positions */ -#define ADC_PRESCALER_gm 0x07 /* Clock Prescaler Selection group mask. */ -#define ADC_PRESCALER_gp 0 /* Clock Prescaler Selection group position. */ -#define ADC_PRESCALER0_bm (1<<0) /* Clock Prescaler Selection bit 0 mask. */ -#define ADC_PRESCALER0_bp 0 /* Clock Prescaler Selection bit 0 position. */ -#define ADC_PRESCALER1_bm (1<<1) /* Clock Prescaler Selection bit 1 mask. */ -#define ADC_PRESCALER1_bp 1 /* Clock Prescaler Selection bit 1 position. */ -#define ADC_PRESCALER2_bm (1<<2) /* Clock Prescaler Selection bit 2 mask. */ -#define ADC_PRESCALER2_bp 2 /* Clock Prescaler Selection bit 2 position. */ - -/* ADC.INTFLAGS bit masks and bit positions */ -#define ADC_CH0IF_bm 0x01 /* Channel 0 Interrupt Flag bit mask. */ -#define ADC_CH0IF_bp 0 /* Channel 0 Interrupt Flag bit position. */ - -/* AC - Analog Comparator */ -/* AC.AC0CTRL bit masks and bit positions */ -#define AC_INTMODE_gm 0xC0 /* Interrupt Mode group mask. */ -#define AC_INTMODE_gp 6 /* Interrupt Mode group position. */ -#define AC_INTMODE0_bm (1<<6) /* Interrupt Mode bit 0 mask. */ -#define AC_INTMODE0_bp 6 /* Interrupt Mode bit 0 position. */ -#define AC_INTMODE1_bm (1<<7) /* Interrupt Mode bit 1 mask. */ -#define AC_INTMODE1_bp 7 /* Interrupt Mode bit 1 position. */ - -#define AC_INTLVL_gm 0x30 /* Interrupt Level group mask. */ -#define AC_INTLVL_gp 4 /* Interrupt Level group position. */ -#define AC_INTLVL0_bm (1<<4) /* Interrupt Level bit 0 mask. */ -#define AC_INTLVL0_bp 4 /* Interrupt Level bit 0 position. */ -#define AC_INTLVL1_bm (1<<5) /* Interrupt Level bit 1 mask. */ -#define AC_INTLVL1_bp 5 /* Interrupt Level bit 1 position. */ - -#define AC_HYSMODE_gm 0x06 /* Hysteresis Mode group mask. */ -#define AC_HYSMODE_gp 1 /* Hysteresis Mode group position. */ -#define AC_HYSMODE0_bm (1<<1) /* Hysteresis Mode bit 0 mask. */ -#define AC_HYSMODE0_bp 1 /* Hysteresis Mode bit 0 position. */ -#define AC_HYSMODE1_bm (1<<2) /* Hysteresis Mode bit 1 mask. */ -#define AC_HYSMODE1_bp 2 /* Hysteresis Mode bit 1 position. */ - -#define AC_ENABLE_bm 0x01 /* Enable bit mask. */ -#define AC_ENABLE_bp 0 /* Enable bit position. */ - -/* AC.AC1CTRL bit masks and bit positions */ -/* AC_INTMODE Predefined. */ -/* AC_INTMODE Predefined. */ - -/* AC_INTLVL Predefined. */ -/* AC_INTLVL Predefined. */ - -/* AC_HYSMODE Predefined. */ -/* AC_HYSMODE Predefined. */ - -/* AC_ENABLE Predefined. */ -/* AC_ENABLE Predefined. */ - -/* AC.AC0MUXCTRL bit masks and bit positions */ -#define AC_MUXPOS_gm 0x38 /* MUX Positive Input group mask. */ -#define AC_MUXPOS_gp 3 /* MUX Positive Input group position. */ -#define AC_MUXPOS0_bm (1<<3) /* MUX Positive Input bit 0 mask. */ -#define AC_MUXPOS0_bp 3 /* MUX Positive Input bit 0 position. */ -#define AC_MUXPOS1_bm (1<<4) /* MUX Positive Input bit 1 mask. */ -#define AC_MUXPOS1_bp 4 /* MUX Positive Input bit 1 position. */ -#define AC_MUXPOS2_bm (1<<5) /* MUX Positive Input bit 2 mask. */ -#define AC_MUXPOS2_bp 5 /* MUX Positive Input bit 2 position. */ - -#define AC_MUXNEG_gm 0x07 /* MUX Negative Input group mask. */ -#define AC_MUXNEG_gp 0 /* MUX Negative Input group position. */ -#define AC_MUXNEG0_bm (1<<0) /* MUX Negative Input bit 0 mask. */ -#define AC_MUXNEG0_bp 0 /* MUX Negative Input bit 0 position. */ -#define AC_MUXNEG1_bm (1<<1) /* MUX Negative Input bit 1 mask. */ -#define AC_MUXNEG1_bp 1 /* MUX Negative Input bit 1 position. */ -#define AC_MUXNEG2_bm (1<<2) /* MUX Negative Input bit 2 mask. */ -#define AC_MUXNEG2_bp 2 /* MUX Negative Input bit 2 position. */ - -/* AC.AC1MUXCTRL bit masks and bit positions */ -/* AC_MUXPOS Predefined. */ -/* AC_MUXPOS Predefined. */ - -/* AC_MUXNEG Predefined. */ -/* AC_MUXNEG Predefined. */ - -/* AC.CTRLA bit masks and bit positions */ -#define AC_AC1OUT_bm 0x02 /* Analog Comparator 1 Output Enable bit mask. */ -#define AC_AC1OUT_bp 1 /* Analog Comparator 1 Output Enable bit position. */ - -#define AC_AC0OUT_bm 0x01 /* Analog Comparator 0 Output Enable bit mask. */ -#define AC_AC0OUT_bp 0 /* Analog Comparator 0 Output Enable bit position. */ - -/* AC.CTRLB bit masks and bit positions */ -#define AC_SCALEFAC_gm 0x3F /* VCC Voltage Scaler Factor group mask. */ -#define AC_SCALEFAC_gp 0 /* VCC Voltage Scaler Factor group position. */ -#define AC_SCALEFAC0_bm (1<<0) /* VCC Voltage Scaler Factor bit 0 mask. */ -#define AC_SCALEFAC0_bp 0 /* VCC Voltage Scaler Factor bit 0 position. */ -#define AC_SCALEFAC1_bm (1<<1) /* VCC Voltage Scaler Factor bit 1 mask. */ -#define AC_SCALEFAC1_bp 1 /* VCC Voltage Scaler Factor bit 1 position. */ -#define AC_SCALEFAC2_bm (1<<2) /* VCC Voltage Scaler Factor bit 2 mask. */ -#define AC_SCALEFAC2_bp 2 /* VCC Voltage Scaler Factor bit 2 position. */ -#define AC_SCALEFAC3_bm (1<<3) /* VCC Voltage Scaler Factor bit 3 mask. */ -#define AC_SCALEFAC3_bp 3 /* VCC Voltage Scaler Factor bit 3 position. */ -#define AC_SCALEFAC4_bm (1<<4) /* VCC Voltage Scaler Factor bit 4 mask. */ -#define AC_SCALEFAC4_bp 4 /* VCC Voltage Scaler Factor bit 4 position. */ -#define AC_SCALEFAC5_bm (1<<5) /* VCC Voltage Scaler Factor bit 5 mask. */ -#define AC_SCALEFAC5_bp 5 /* VCC Voltage Scaler Factor bit 5 position. */ - -/* AC.WINCTRL bit masks and bit positions */ -#define AC_WEN_bm 0x10 /* Window Mode Enable bit mask. */ -#define AC_WEN_bp 4 /* Window Mode Enable bit position. */ - -#define AC_WINTMODE_gm 0x0C /* Window Interrupt Mode group mask. */ -#define AC_WINTMODE_gp 2 /* Window Interrupt Mode group position. */ -#define AC_WINTMODE0_bm (1<<2) /* Window Interrupt Mode bit 0 mask. */ -#define AC_WINTMODE0_bp 2 /* Window Interrupt Mode bit 0 position. */ -#define AC_WINTMODE1_bm (1<<3) /* Window Interrupt Mode bit 1 mask. */ -#define AC_WINTMODE1_bp 3 /* Window Interrupt Mode bit 1 position. */ - -#define AC_WINTLVL_gm 0x03 /* Window Interrupt Level group mask. */ -#define AC_WINTLVL_gp 0 /* Window Interrupt Level group position. */ -#define AC_WINTLVL0_bm (1<<0) /* Window Interrupt Level bit 0 mask. */ -#define AC_WINTLVL0_bp 0 /* Window Interrupt Level bit 0 position. */ -#define AC_WINTLVL1_bm (1<<1) /* Window Interrupt Level bit 1 mask. */ -#define AC_WINTLVL1_bp 1 /* Window Interrupt Level bit 1 position. */ - -/* AC.STATUS bit masks and bit positions */ -#define AC_WSTATE_gm 0xC0 /* Window Mode State group mask. */ -#define AC_WSTATE_gp 6 /* Window Mode State group position. */ -#define AC_WSTATE0_bm (1<<6) /* Window Mode State bit 0 mask. */ -#define AC_WSTATE0_bp 6 /* Window Mode State bit 0 position. */ -#define AC_WSTATE1_bm (1<<7) /* Window Mode State bit 1 mask. */ -#define AC_WSTATE1_bp 7 /* Window Mode State bit 1 position. */ - -#define AC_AC1STATE_bm 0x20 /* Analog Comparator 1 State bit mask. */ -#define AC_AC1STATE_bp 5 /* Analog Comparator 1 State bit position. */ - -#define AC_AC0STATE_bm 0x10 /* Analog Comparator 0 State bit mask. */ -#define AC_AC0STATE_bp 4 /* Analog Comparator 0 State bit position. */ - -#define AC_WIF_bm 0x04 /* Window Mode Interrupt Flag bit mask. */ -#define AC_WIF_bp 2 /* Window Mode Interrupt Flag bit position. */ - -#define AC_AC1IF_bm 0x02 /* Analog Comparator 1 Interrupt Flag bit mask. */ -#define AC_AC1IF_bp 1 /* Analog Comparator 1 Interrupt Flag bit position. */ - -#define AC_AC0IF_bm 0x01 /* Analog Comparator 0 Interrupt Flag bit mask. */ -#define AC_AC0IF_bp 0 /* Analog Comparator 0 Interrupt Flag bit position. */ - -/* RTC - Real-Time Counter */ -/* RTC.CTRL bit masks and bit positions */ -#define RTC_PRESCALER_gm 0x07 /* Prescaling Factor group mask. */ -#define RTC_PRESCALER_gp 0 /* Prescaling Factor group position. */ -#define RTC_PRESCALER0_bm (1<<0) /* Prescaling Factor bit 0 mask. */ -#define RTC_PRESCALER0_bp 0 /* Prescaling Factor bit 0 position. */ -#define RTC_PRESCALER1_bm (1<<1) /* Prescaling Factor bit 1 mask. */ -#define RTC_PRESCALER1_bp 1 /* Prescaling Factor bit 1 position. */ -#define RTC_PRESCALER2_bm (1<<2) /* Prescaling Factor bit 2 mask. */ -#define RTC_PRESCALER2_bp 2 /* Prescaling Factor bit 2 position. */ - -/* RTC.STATUS bit masks and bit positions */ -#define RTC_SYNCBUSY_bm 0x01 /* Synchronization Busy Flag bit mask. */ -#define RTC_SYNCBUSY_bp 0 /* Synchronization Busy Flag bit position. */ - -/* RTC.INTCTRL bit masks and bit positions */ -#define RTC_COMPINTLVL_gm 0x0C /* Compare Match Interrupt Level group mask. */ -#define RTC_COMPINTLVL_gp 2 /* Compare Match Interrupt Level group position. */ -#define RTC_COMPINTLVL0_bm (1<<2) /* Compare Match Interrupt Level bit 0 mask. */ -#define RTC_COMPINTLVL0_bp 2 /* Compare Match Interrupt Level bit 0 position. */ -#define RTC_COMPINTLVL1_bm (1<<3) /* Compare Match Interrupt Level bit 1 mask. */ -#define RTC_COMPINTLVL1_bp 3 /* Compare Match Interrupt Level bit 1 position. */ - -#define RTC_OVFINTLVL_gm 0x03 /* Overflow Interrupt Level group mask. */ -#define RTC_OVFINTLVL_gp 0 /* Overflow Interrupt Level group position. */ -#define RTC_OVFINTLVL0_bm (1<<0) /* Overflow Interrupt Level bit 0 mask. */ -#define RTC_OVFINTLVL0_bp 0 /* Overflow Interrupt Level bit 0 position. */ -#define RTC_OVFINTLVL1_bm (1<<1) /* Overflow Interrupt Level bit 1 mask. */ -#define RTC_OVFINTLVL1_bp 1 /* Overflow Interrupt Level bit 1 position. */ - -/* RTC.INTFLAGS bit masks and bit positions */ -#define RTC_COMPIF_bm 0x02 /* Compare Match Interrupt Flag bit mask. */ -#define RTC_COMPIF_bp 1 /* Compare Match Interrupt Flag bit position. */ - -#define RTC_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ -#define RTC_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ - -/* TWI - Two-Wire Interface */ -/* TWI_MASTER.CTRLA bit masks and bit positions */ -#define TWI_MASTER_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ -#define TWI_MASTER_INTLVL_gp 6 /* Interrupt Level group position. */ -#define TWI_MASTER_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ -#define TWI_MASTER_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ -#define TWI_MASTER_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ -#define TWI_MASTER_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ - -#define TWI_MASTER_RIEN_bm 0x20 /* Read Interrupt Enable bit mask. */ -#define TWI_MASTER_RIEN_bp 5 /* Read Interrupt Enable bit position. */ - -#define TWI_MASTER_WIEN_bm 0x10 /* Write Interrupt Enable bit mask. */ -#define TWI_MASTER_WIEN_bp 4 /* Write Interrupt Enable bit position. */ - -#define TWI_MASTER_ENABLE_bm 0x08 /* Enable TWI Master bit mask. */ -#define TWI_MASTER_ENABLE_bp 3 /* Enable TWI Master bit position. */ - -/* TWI_MASTER.CTRLB bit masks and bit positions */ -#define TWI_MASTER_TIMEOUT_gm 0x0C /* Inactive Bus Timeout group mask. */ -#define TWI_MASTER_TIMEOUT_gp 2 /* Inactive Bus Timeout group position. */ -#define TWI_MASTER_TIMEOUT0_bm (1<<2) /* Inactive Bus Timeout bit 0 mask. */ -#define TWI_MASTER_TIMEOUT0_bp 2 /* Inactive Bus Timeout bit 0 position. */ -#define TWI_MASTER_TIMEOUT1_bm (1<<3) /* Inactive Bus Timeout bit 1 mask. */ -#define TWI_MASTER_TIMEOUT1_bp 3 /* Inactive Bus Timeout bit 1 position. */ - -#define TWI_MASTER_QCEN_bm 0x02 /* Quick Command Enable bit mask. */ -#define TWI_MASTER_QCEN_bp 1 /* Quick Command Enable bit position. */ - -#define TWI_MASTER_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ -#define TWI_MASTER_SMEN_bp 0 /* Smart Mode Enable bit position. */ - -/* TWI_MASTER.CTRLC bit masks and bit positions */ -#define TWI_MASTER_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ -#define TWI_MASTER_ACKACT_bp 2 /* Acknowledge Action bit position. */ - -#define TWI_MASTER_CMD_gm 0x03 /* Command group mask. */ -#define TWI_MASTER_CMD_gp 0 /* Command group position. */ -#define TWI_MASTER_CMD0_bm (1<<0) /* Command bit 0 mask. */ -#define TWI_MASTER_CMD0_bp 0 /* Command bit 0 position. */ -#define TWI_MASTER_CMD1_bm (1<<1) /* Command bit 1 mask. */ -#define TWI_MASTER_CMD1_bp 1 /* Command bit 1 position. */ - -/* TWI_MASTER.STATUS bit masks and bit positions */ -#define TWI_MASTER_RIF_bm 0x80 /* Read Interrupt Flag bit mask. */ -#define TWI_MASTER_RIF_bp 7 /* Read Interrupt Flag bit position. */ - -#define TWI_MASTER_WIF_bm 0x40 /* Write Interrupt Flag bit mask. */ -#define TWI_MASTER_WIF_bp 6 /* Write Interrupt Flag bit position. */ - -#define TWI_MASTER_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ -#define TWI_MASTER_CLKHOLD_bp 5 /* Clock Hold bit position. */ - -#define TWI_MASTER_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ -#define TWI_MASTER_RXACK_bp 4 /* Received Acknowledge bit position. */ - -#define TWI_MASTER_ARBLOST_bm 0x08 /* Arbitration Lost bit mask. */ -#define TWI_MASTER_ARBLOST_bp 3 /* Arbitration Lost bit position. */ - -#define TWI_MASTER_BUSERR_bm 0x04 /* Bus Error bit mask. */ -#define TWI_MASTER_BUSERR_bp 2 /* Bus Error bit position. */ - -#define TWI_MASTER_BUSSTATE_gm 0x03 /* Bus State group mask. */ -#define TWI_MASTER_BUSSTATE_gp 0 /* Bus State group position. */ -#define TWI_MASTER_BUSSTATE0_bm (1<<0) /* Bus State bit 0 mask. */ -#define TWI_MASTER_BUSSTATE0_bp 0 /* Bus State bit 0 position. */ -#define TWI_MASTER_BUSSTATE1_bm (1<<1) /* Bus State bit 1 mask. */ -#define TWI_MASTER_BUSSTATE1_bp 1 /* Bus State bit 1 position. */ - -/* TWI_SLAVE.CTRLA bit masks and bit positions */ -#define TWI_SLAVE_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ -#define TWI_SLAVE_INTLVL_gp 6 /* Interrupt Level group position. */ -#define TWI_SLAVE_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ -#define TWI_SLAVE_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ -#define TWI_SLAVE_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ -#define TWI_SLAVE_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ - -#define TWI_SLAVE_DIEN_bm 0x20 /* Data Interrupt Enable bit mask. */ -#define TWI_SLAVE_DIEN_bp 5 /* Data Interrupt Enable bit position. */ - -#define TWI_SLAVE_APIEN_bm 0x10 /* Address/Stop Interrupt Enable bit mask. */ -#define TWI_SLAVE_APIEN_bp 4 /* Address/Stop Interrupt Enable bit position. */ - -#define TWI_SLAVE_ENABLE_bm 0x08 /* Enable TWI Slave bit mask. */ -#define TWI_SLAVE_ENABLE_bp 3 /* Enable TWI Slave bit position. */ - -#define TWI_SLAVE_PIEN_bm 0x04 /* Stop Interrupt Enable bit mask. */ -#define TWI_SLAVE_PIEN_bp 2 /* Stop Interrupt Enable bit position. */ - -#define TWI_SLAVE_PMEN_bm 0x02 /* Promiscuous Mode Enable bit mask. */ -#define TWI_SLAVE_PMEN_bp 1 /* Promiscuous Mode Enable bit position. */ - -#define TWI_SLAVE_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ -#define TWI_SLAVE_SMEN_bp 0 /* Smart Mode Enable bit position. */ - -/* TWI_SLAVE.CTRLB bit masks and bit positions */ -#define TWI_SLAVE_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ -#define TWI_SLAVE_ACKACT_bp 2 /* Acknowledge Action bit position. */ - -#define TWI_SLAVE_CMD_gm 0x03 /* Command group mask. */ -#define TWI_SLAVE_CMD_gp 0 /* Command group position. */ -#define TWI_SLAVE_CMD0_bm (1<<0) /* Command bit 0 mask. */ -#define TWI_SLAVE_CMD0_bp 0 /* Command bit 0 position. */ -#define TWI_SLAVE_CMD1_bm (1<<1) /* Command bit 1 mask. */ -#define TWI_SLAVE_CMD1_bp 1 /* Command bit 1 position. */ - -/* TWI_SLAVE.STATUS bit masks and bit positions */ -#define TWI_SLAVE_DIF_bm 0x80 /* Data Interrupt Flag bit mask. */ -#define TWI_SLAVE_DIF_bp 7 /* Data Interrupt Flag bit position. */ - -#define TWI_SLAVE_APIF_bm 0x40 /* Address/Stop Interrupt Flag bit mask. */ -#define TWI_SLAVE_APIF_bp 6 /* Address/Stop Interrupt Flag bit position. */ - -#define TWI_SLAVE_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ -#define TWI_SLAVE_CLKHOLD_bp 5 /* Clock Hold bit position. */ - -#define TWI_SLAVE_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ -#define TWI_SLAVE_RXACK_bp 4 /* Received Acknowledge bit position. */ - -#define TWI_SLAVE_COLL_bm 0x08 /* Collision bit mask. */ -#define TWI_SLAVE_COLL_bp 3 /* Collision bit position. */ - -#define TWI_SLAVE_BUSERR_bm 0x04 /* Bus Error bit mask. */ -#define TWI_SLAVE_BUSERR_bp 2 /* Bus Error bit position. */ - -#define TWI_SLAVE_DIR_bm 0x02 /* Read/Write Direction bit mask. */ -#define TWI_SLAVE_DIR_bp 1 /* Read/Write Direction bit position. */ - -#define TWI_SLAVE_AP_bm 0x01 /* Slave Address or Stop bit mask. */ -#define TWI_SLAVE_AP_bp 0 /* Slave Address or Stop bit position. */ - -/* TWI_SLAVE.ADDRMASK bit masks and bit positions */ -#define TWI_SLAVE_ADDRMASK_gm 0xFE /* Address Mask group mask. */ -#define TWI_SLAVE_ADDRMASK_gp 1 /* Address Mask group position. */ -#define TWI_SLAVE_ADDRMASK0_bm (1<<1) /* Address Mask bit 0 mask. */ -#define TWI_SLAVE_ADDRMASK0_bp 1 /* Address Mask bit 0 position. */ -#define TWI_SLAVE_ADDRMASK1_bm (1<<2) /* Address Mask bit 1 mask. */ -#define TWI_SLAVE_ADDRMASK1_bp 2 /* Address Mask bit 1 position. */ -#define TWI_SLAVE_ADDRMASK2_bm (1<<3) /* Address Mask bit 2 mask. */ -#define TWI_SLAVE_ADDRMASK2_bp 3 /* Address Mask bit 2 position. */ -#define TWI_SLAVE_ADDRMASK3_bm (1<<4) /* Address Mask bit 3 mask. */ -#define TWI_SLAVE_ADDRMASK3_bp 4 /* Address Mask bit 3 position. */ -#define TWI_SLAVE_ADDRMASK4_bm (1<<5) /* Address Mask bit 4 mask. */ -#define TWI_SLAVE_ADDRMASK4_bp 5 /* Address Mask bit 4 position. */ -#define TWI_SLAVE_ADDRMASK5_bm (1<<6) /* Address Mask bit 5 mask. */ -#define TWI_SLAVE_ADDRMASK5_bp 6 /* Address Mask bit 5 position. */ -#define TWI_SLAVE_ADDRMASK6_bm (1<<7) /* Address Mask bit 6 mask. */ -#define TWI_SLAVE_ADDRMASK6_bp 7 /* Address Mask bit 6 position. */ - -#define TWI_SLAVE_ADDREN_bm 0x01 /* Address Enable bit mask. */ -#define TWI_SLAVE_ADDREN_bp 0 /* Address Enable bit position. */ - -/* TWI.CTRL bit masks and bit positions */ -#define TWI_SDAHOLD_gm 0x06 /* SDA Hold Time Enable group mask. */ -#define TWI_SDAHOLD_gp 1 /* SDA Hold Time Enable group position. */ -#define TWI_SDAHOLD0_bm (1<<1) /* SDA Hold Time Enable bit 0 mask. */ -#define TWI_SDAHOLD0_bp 1 /* SDA Hold Time Enable bit 0 position. */ -#define TWI_SDAHOLD1_bm (1<<2) /* SDA Hold Time Enable bit 1 mask. */ -#define TWI_SDAHOLD1_bp 2 /* SDA Hold Time Enable bit 1 position. */ - -#define TWI_EDIEN_bm 0x01 /* External Driver Interface Enable bit mask. */ -#define TWI_EDIEN_bp 0 /* External Driver Interface Enable bit position. */ - -/* USB - USB */ -/* USB_EP.STATUS bit masks and bit positions */ -#define USB_EP_STALLF_bm 0x80 /* Endpoint Stall Flag bit mask. */ -#define USB_EP_STALLF_bp 7 /* Endpoint Stall Flag bit position. */ - -#define USB_EP_CRC_bm 0x80 /* CRC Error Flag bit mask. */ -#define USB_EP_CRC_bp 7 /* CRC Error Flag bit position. */ - -#define USB_EP_UNF_bm 0x40 /* Underflow Enpoint FLag bit mask. */ -#define USB_EP_UNF_bp 6 /* Underflow Enpoint FLag bit position. */ - -#define USB_EP_OVF_bm 0x40 /* Overflow Enpoint Flag for Output Endpoints bit mask. */ -#define USB_EP_OVF_bp 6 /* Overflow Enpoint Flag for Output Endpoints bit position. */ - -#define USB_EP_TRNCOMPL0_bm 0x20 /* Transaction Complete 0 Flag bit mask. */ -#define USB_EP_TRNCOMPL0_bp 5 /* Transaction Complete 0 Flag bit position. */ - -#define USB_EP_TRNCOMPL1_bm 0x10 /* Transaction Complete 1 Flag bit mask. */ -#define USB_EP_TRNCOMPL1_bp 4 /* Transaction Complete 1 Flag bit position. */ - -#define USB_EP_SETUP_bm 0x10 /* SETUP Transaction Complete Flag bit mask. */ -#define USB_EP_SETUP_bp 4 /* SETUP Transaction Complete Flag bit position. */ - -#define USB_EP_BANK_bm 0x08 /* Bank Select bit mask. */ -#define USB_EP_BANK_bp 3 /* Bank Select bit position. */ - -#define USB_EP_BUSNACK1_bm 0x04 /* Data Buffer 1 Not Acknowledge bit mask. */ -#define USB_EP_BUSNACK1_bp 2 /* Data Buffer 1 Not Acknowledge bit position. */ - -#define USB_EP_BUSNACK0_bm 0x02 /* Data Buffer 0 Not Acknowledge bit mask. */ -#define USB_EP_BUSNACK0_bp 1 /* Data Buffer 0 Not Acknowledge bit position. */ - -#define USB_EP_TOGGLE_bm 0x01 /* Data Toggle bit mask. */ -#define USB_EP_TOGGLE_bp 0 /* Data Toggle bit position. */ - -/* USB_EP.CTRL bit masks and bit positions */ -#define USB_EP_TYPE_gm 0xC0 /* Endpoint Type group mask. */ -#define USB_EP_TYPE_gp 6 /* Endpoint Type group position. */ -#define USB_EP_TYPE0_bm (1<<6) /* Endpoint Type bit 0 mask. */ -#define USB_EP_TYPE0_bp 6 /* Endpoint Type bit 0 position. */ -#define USB_EP_TYPE1_bm (1<<7) /* Endpoint Type bit 1 mask. */ -#define USB_EP_TYPE1_bp 7 /* Endpoint Type bit 1 position. */ - -#define USB_EP_MULTIPKT_bm 0x20 /* Multi Packet Transfer Enable bit mask. */ -#define USB_EP_MULTIPKT_bp 5 /* Multi Packet Transfer Enable bit position. */ - -#define USB_EP_PINGPONG_bm 0x10 /* Ping-Pong Enable bit mask. */ -#define USB_EP_PINGPONG_bp 4 /* Ping-Pong Enable bit position. */ - -#define USB_EP_INTDSBL_bm 0x08 /* Interrupt Disable bit mask. */ -#define USB_EP_INTDSBL_bp 3 /* Interrupt Disable bit position. */ - -#define USB_EP_STALL_bm 0x04 /* Data Stall bit mask. */ -#define USB_EP_STALL_bp 2 /* Data Stall bit position. */ - -#define USB_EP_BUFSIZE_gm 0x07 /* Data Buffer Size group mask. */ -#define USB_EP_BUFSIZE_gp 0 /* Data Buffer Size group position. */ -#define USB_EP_BUFSIZE0_bm (1<<0) /* Data Buffer Size bit 0 mask. */ -#define USB_EP_BUFSIZE0_bp 0 /* Data Buffer Size bit 0 position. */ -#define USB_EP_BUFSIZE1_bm (1<<1) /* Data Buffer Size bit 1 mask. */ -#define USB_EP_BUFSIZE1_bp 1 /* Data Buffer Size bit 1 position. */ -#define USB_EP_BUFSIZE2_bm (1<<2) /* Data Buffer Size bit 2 mask. */ -#define USB_EP_BUFSIZE2_bp 2 /* Data Buffer Size bit 2 position. */ - -/* USB_EP.CNT bit masks and bit positions */ -#define USB_EP_ZLP_bm 0x8000 /* Zero Length Packet bit mask. */ -#define USB_EP_ZLP_bp 15 /* Zero Length Packet bit position. */ - -/* USB.CTRLA bit masks and bit positions */ -#define USB_ENABLE_bm 0x80 /* USB Enable bit mask. */ -#define USB_ENABLE_bp 7 /* USB Enable bit position. */ - -#define USB_SPEED_bm 0x40 /* Speed Select bit mask. */ -#define USB_SPEED_bp 6 /* Speed Select bit position. */ - -#define USB_FIFOEN_bm 0x20 /* USB FIFO Enable bit mask. */ -#define USB_FIFOEN_bp 5 /* USB FIFO Enable bit position. */ - -#define USB_STFRNUM_bm 0x10 /* Store Frame Number Enable bit mask. */ -#define USB_STFRNUM_bp 4 /* Store Frame Number Enable bit position. */ - -#define USB_MAXEP_gm 0x0F /* Maximum Endpoint Addresses group mask. */ -#define USB_MAXEP_gp 0 /* Maximum Endpoint Addresses group position. */ -#define USB_MAXEP0_bm (1<<0) /* Maximum Endpoint Addresses bit 0 mask. */ -#define USB_MAXEP0_bp 0 /* Maximum Endpoint Addresses bit 0 position. */ -#define USB_MAXEP1_bm (1<<1) /* Maximum Endpoint Addresses bit 1 mask. */ -#define USB_MAXEP1_bp 1 /* Maximum Endpoint Addresses bit 1 position. */ -#define USB_MAXEP2_bm (1<<2) /* Maximum Endpoint Addresses bit 2 mask. */ -#define USB_MAXEP2_bp 2 /* Maximum Endpoint Addresses bit 2 position. */ -#define USB_MAXEP3_bm (1<<3) /* Maximum Endpoint Addresses bit 3 mask. */ -#define USB_MAXEP3_bp 3 /* Maximum Endpoint Addresses bit 3 position. */ - -/* USB.CTRLB bit masks and bit positions */ -#define USB_PULLRST_bm 0x10 /* Pull during Reset bit mask. */ -#define USB_PULLRST_bp 4 /* Pull during Reset bit position. */ - -#define USB_RWAKEUP_bm 0x04 /* Remote Wake-up bit mask. */ -#define USB_RWAKEUP_bp 2 /* Remote Wake-up bit position. */ - -#define USB_GNACK_bm 0x02 /* Global NACK bit mask. */ -#define USB_GNACK_bp 1 /* Global NACK bit position. */ - -#define USB_ATTACH_bm 0x01 /* Attach bit mask. */ -#define USB_ATTACH_bp 0 /* Attach bit position. */ - -/* USB.STATUS bit masks and bit positions */ -#define USB_URESUME_bm 0x08 /* Upstream Resume bit mask. */ -#define USB_URESUME_bp 3 /* Upstream Resume bit position. */ - -#define USB_RESUME_bm 0x04 /* Resume bit mask. */ -#define USB_RESUME_bp 2 /* Resume bit position. */ - -#define USB_SUSPEND_bm 0x02 /* Bus Suspended bit mask. */ -#define USB_SUSPEND_bp 1 /* Bus Suspended bit position. */ - -#define USB_BUSRST_bm 0x01 /* Bus Reset bit mask. */ -#define USB_BUSRST_bp 0 /* Bus Reset bit position. */ - -/* USB.ADDR bit masks and bit positions */ -#define USB_ADDR_gm 0x7F /* Device Address group mask. */ -#define USB_ADDR_gp 0 /* Device Address group position. */ -#define USB_ADDR0_bm (1<<0) /* Device Address bit 0 mask. */ -#define USB_ADDR0_bp 0 /* Device Address bit 0 position. */ -#define USB_ADDR1_bm (1<<1) /* Device Address bit 1 mask. */ -#define USB_ADDR1_bp 1 /* Device Address bit 1 position. */ -#define USB_ADDR2_bm (1<<2) /* Device Address bit 2 mask. */ -#define USB_ADDR2_bp 2 /* Device Address bit 2 position. */ -#define USB_ADDR3_bm (1<<3) /* Device Address bit 3 mask. */ -#define USB_ADDR3_bp 3 /* Device Address bit 3 position. */ -#define USB_ADDR4_bm (1<<4) /* Device Address bit 4 mask. */ -#define USB_ADDR4_bp 4 /* Device Address bit 4 position. */ -#define USB_ADDR5_bm (1<<5) /* Device Address bit 5 mask. */ -#define USB_ADDR5_bp 5 /* Device Address bit 5 position. */ -#define USB_ADDR6_bm (1<<6) /* Device Address bit 6 mask. */ -#define USB_ADDR6_bp 6 /* Device Address bit 6 position. */ - -/* USB.FIFOWP bit masks and bit positions */ -#define USB_FIFOWP_gm 0x1F /* FIFO Write Pointer group mask. */ -#define USB_FIFOWP_gp 0 /* FIFO Write Pointer group position. */ -#define USB_FIFOWP0_bm (1<<0) /* FIFO Write Pointer bit 0 mask. */ -#define USB_FIFOWP0_bp 0 /* FIFO Write Pointer bit 0 position. */ -#define USB_FIFOWP1_bm (1<<1) /* FIFO Write Pointer bit 1 mask. */ -#define USB_FIFOWP1_bp 1 /* FIFO Write Pointer bit 1 position. */ -#define USB_FIFOWP2_bm (1<<2) /* FIFO Write Pointer bit 2 mask. */ -#define USB_FIFOWP2_bp 2 /* FIFO Write Pointer bit 2 position. */ -#define USB_FIFOWP3_bm (1<<3) /* FIFO Write Pointer bit 3 mask. */ -#define USB_FIFOWP3_bp 3 /* FIFO Write Pointer bit 3 position. */ -#define USB_FIFOWP4_bm (1<<4) /* FIFO Write Pointer bit 4 mask. */ -#define USB_FIFOWP4_bp 4 /* FIFO Write Pointer bit 4 position. */ - -/* USB.FIFORP bit masks and bit positions */ -#define USB_FIFORP_gm 0x1F /* FIFO Read Pointer group mask. */ -#define USB_FIFORP_gp 0 /* FIFO Read Pointer group position. */ -#define USB_FIFORP0_bm (1<<0) /* FIFO Read Pointer bit 0 mask. */ -#define USB_FIFORP0_bp 0 /* FIFO Read Pointer bit 0 position. */ -#define USB_FIFORP1_bm (1<<1) /* FIFO Read Pointer bit 1 mask. */ -#define USB_FIFORP1_bp 1 /* FIFO Read Pointer bit 1 position. */ -#define USB_FIFORP2_bm (1<<2) /* FIFO Read Pointer bit 2 mask. */ -#define USB_FIFORP2_bp 2 /* FIFO Read Pointer bit 2 position. */ -#define USB_FIFORP3_bm (1<<3) /* FIFO Read Pointer bit 3 mask. */ -#define USB_FIFORP3_bp 3 /* FIFO Read Pointer bit 3 position. */ -#define USB_FIFORP4_bm (1<<4) /* FIFO Read Pointer bit 4 mask. */ -#define USB_FIFORP4_bp 4 /* FIFO Read Pointer bit 4 position. */ - -/* USB.INTCTRLA bit masks and bit positions */ -#define USB_SOFIE_bm 0x80 /* Start Of Frame Interrupt Enable bit mask. */ -#define USB_SOFIE_bp 7 /* Start Of Frame Interrupt Enable bit position. */ - -#define USB_BUSEVIE_bm 0x40 /* Bus Event Interrupt Enable bit mask. */ -#define USB_BUSEVIE_bp 6 /* Bus Event Interrupt Enable bit position. */ - -#define USB_BUSERRIE_bm 0x20 /* Bus Error Interrupt Enable bit mask. */ -#define USB_BUSERRIE_bp 5 /* Bus Error Interrupt Enable bit position. */ - -#define USB_STALLIE_bm 0x10 /* STALL Interrupt Enable bit mask. */ -#define USB_STALLIE_bp 4 /* STALL Interrupt Enable bit position. */ - -#define USB_INTLVL_gm 0x03 /* Interrupt Level group mask. */ -#define USB_INTLVL_gp 0 /* Interrupt Level group position. */ -#define USB_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */ -#define USB_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */ -#define USB_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ -#define USB_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */ - -/* USB.INTCTRLB bit masks and bit positions */ -#define USB_TRNIE_bm 0x02 /* Transaction Complete Interrupt Enable bit mask. */ -#define USB_TRNIE_bp 1 /* Transaction Complete Interrupt Enable bit position. */ - -#define USB_SETUPIE_bm 0x01 /* SETUP Transaction Complete Interrupt Enable bit mask. */ -#define USB_SETUPIE_bp 0 /* SETUP Transaction Complete Interrupt Enable bit position. */ - -/* USB.INTFLAGSACLR bit masks and bit positions */ -#define USB_SOFIF_bm 0x80 /* Start Of Frame Interrupt Flag bit mask. */ -#define USB_SOFIF_bp 7 /* Start Of Frame Interrupt Flag bit position. */ - -#define USB_SUSPENDIF_bm 0x40 /* Suspend Interrupt Flag bit mask. */ -#define USB_SUSPENDIF_bp 6 /* Suspend Interrupt Flag bit position. */ - -#define USB_RESUMEIF_bm 0x20 /* Resume Interrupt Flag bit mask. */ -#define USB_RESUMEIF_bp 5 /* Resume Interrupt Flag bit position. */ - -#define USB_RSTIF_bm 0x10 /* Reset Interrupt Flag bit mask. */ -#define USB_RSTIF_bp 4 /* Reset Interrupt Flag bit position. */ - -#define USB_CRCIF_bm 0x08 /* Isochronous CRC Error Interrupt Flag bit mask. */ -#define USB_CRCIF_bp 3 /* Isochronous CRC Error Interrupt Flag bit position. */ - -#define USB_UNFIF_bm 0x04 /* Underflow Interrupt Flag bit mask. */ -#define USB_UNFIF_bp 2 /* Underflow Interrupt Flag bit position. */ - -#define USB_OVFIF_bm 0x02 /* Overflow Interrupt Flag bit mask. */ -#define USB_OVFIF_bp 1 /* Overflow Interrupt Flag bit position. */ - -#define USB_STALLIF_bm 0x01 /* STALL Interrupt Flag bit mask. */ -#define USB_STALLIF_bp 0 /* STALL Interrupt Flag bit position. */ - -/* USB.INTFLAGSASET bit masks and bit positions */ -/* USB_SOFIF Predefined. */ -/* USB_SOFIF Predefined. */ - -/* USB_SUSPENDIF Predefined. */ -/* USB_SUSPENDIF Predefined. */ - -/* USB_RESUMEIF Predefined. */ -/* USB_RESUMEIF Predefined. */ - -/* USB_RSTIF Predefined. */ -/* USB_RSTIF Predefined. */ - -/* USB_CRCIF Predefined. */ -/* USB_CRCIF Predefined. */ - -/* USB_UNFIF Predefined. */ -/* USB_UNFIF Predefined. */ - -/* USB_OVFIF Predefined. */ -/* USB_OVFIF Predefined. */ - -/* USB_STALLIF Predefined. */ -/* USB_STALLIF Predefined. */ - -/* USB.INTFLAGSBCLR bit masks and bit positions */ -#define USB_TRNIF_bm 0x02 /* Transaction Complete Interrupt Flag bit mask. */ -#define USB_TRNIF_bp 1 /* Transaction Complete Interrupt Flag bit position. */ - -#define USB_SETUPIF_bm 0x01 /* SETUP Transaction Complete Interrupt Flag bit mask. */ -#define USB_SETUPIF_bp 0 /* SETUP Transaction Complete Interrupt Flag bit position. */ - -/* USB.INTFLAGSBSET bit masks and bit positions */ -/* USB_TRNIF Predefined. */ -/* USB_TRNIF Predefined. */ - -/* USB_SETUPIF Predefined. */ -/* USB_SETUPIF Predefined. */ - -/* PORT - I/O Port Configuration */ -/* PORT.INTCTRL bit masks and bit positions */ -#define PORT_INT1LVL_gm 0x0C /* Port Interrupt 1 Level group mask. */ -#define PORT_INT1LVL_gp 2 /* Port Interrupt 1 Level group position. */ -#define PORT_INT1LVL0_bm (1<<2) /* Port Interrupt 1 Level bit 0 mask. */ -#define PORT_INT1LVL0_bp 2 /* Port Interrupt 1 Level bit 0 position. */ -#define PORT_INT1LVL1_bm (1<<3) /* Port Interrupt 1 Level bit 1 mask. */ -#define PORT_INT1LVL1_bp 3 /* Port Interrupt 1 Level bit 1 position. */ - -#define PORT_INT0LVL_gm 0x03 /* Port Interrupt 0 Level group mask. */ -#define PORT_INT0LVL_gp 0 /* Port Interrupt 0 Level group position. */ -#define PORT_INT0LVL0_bm (1<<0) /* Port Interrupt 0 Level bit 0 mask. */ -#define PORT_INT0LVL0_bp 0 /* Port Interrupt 0 Level bit 0 position. */ -#define PORT_INT0LVL1_bm (1<<1) /* Port Interrupt 0 Level bit 1 mask. */ -#define PORT_INT0LVL1_bp 1 /* Port Interrupt 0 Level bit 1 position. */ - -/* PORT.INTFLAGS bit masks and bit positions */ -#define PORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ -#define PORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ - -#define PORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ -#define PORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ - -/* PORT.REMAP bit masks and bit positions */ -#define PORT_SPI_bm 0x20 /* SPI bit mask. */ -#define PORT_SPI_bp 5 /* SPI bit position. */ - -#define PORT_USART0_bm 0x10 /* USART0 bit mask. */ -#define PORT_USART0_bp 4 /* USART0 bit position. */ - -#define PORT_TC0D_bm 0x08 /* Timer/Counter 0 Output Compare D bit mask. */ -#define PORT_TC0D_bp 3 /* Timer/Counter 0 Output Compare D bit position. */ - -#define PORT_TC0C_bm 0x04 /* Timer/Counter 0 Output Compare C bit mask. */ -#define PORT_TC0C_bp 2 /* Timer/Counter 0 Output Compare C bit position. */ - -#define PORT_TC0B_bm 0x02 /* Timer/Counter 0 Output Compare B bit mask. */ -#define PORT_TC0B_bp 1 /* Timer/Counter 0 Output Compare B bit position. */ - -#define PORT_TC0A_bm 0x01 /* Timer/Counter 0 Output Compare A bit mask. */ -#define PORT_TC0A_bp 0 /* Timer/Counter 0 Output Compare A bit position. */ - -/* PORT.PIN0CTRL bit masks and bit positions */ -#define PORT_SRLEN_bm 0x80 /* Slew Rate Enable bit mask. */ -#define PORT_SRLEN_bp 7 /* Slew Rate Enable bit position. */ - -#define PORT_INVEN_bm 0x40 /* Inverted I/O Enable bit mask. */ -#define PORT_INVEN_bp 6 /* Inverted I/O Enable bit position. */ - -#define PORT_OPC_gm 0x38 /* Output/Pull Configuration group mask. */ -#define PORT_OPC_gp 3 /* Output/Pull Configuration group position. */ -#define PORT_OPC0_bm (1<<3) /* Output/Pull Configuration bit 0 mask. */ -#define PORT_OPC0_bp 3 /* Output/Pull Configuration bit 0 position. */ -#define PORT_OPC1_bm (1<<4) /* Output/Pull Configuration bit 1 mask. */ -#define PORT_OPC1_bp 4 /* Output/Pull Configuration bit 1 position. */ -#define PORT_OPC2_bm (1<<5) /* Output/Pull Configuration bit 2 mask. */ -#define PORT_OPC2_bp 5 /* Output/Pull Configuration bit 2 position. */ - -#define PORT_ISC_gm 0x07 /* Input/Sense Configuration group mask. */ -#define PORT_ISC_gp 0 /* Input/Sense Configuration group position. */ -#define PORT_ISC0_bm (1<<0) /* Input/Sense Configuration bit 0 mask. */ -#define PORT_ISC0_bp 0 /* Input/Sense Configuration bit 0 position. */ -#define PORT_ISC1_bm (1<<1) /* Input/Sense Configuration bit 1 mask. */ -#define PORT_ISC1_bp 1 /* Input/Sense Configuration bit 1 position. */ -#define PORT_ISC2_bm (1<<2) /* Input/Sense Configuration bit 2 mask. */ -#define PORT_ISC2_bp 2 /* Input/Sense Configuration bit 2 position. */ - -/* PORT.PIN1CTRL bit masks and bit positions */ -/* PORT_SRLEN Predefined. */ -/* PORT_SRLEN Predefined. */ - -/* PORT_INVEN Predefined. */ -/* PORT_INVEN Predefined. */ - -/* PORT_OPC Predefined. */ -/* PORT_OPC Predefined. */ - -/* PORT_ISC Predefined. */ -/* PORT_ISC Predefined. */ - -/* PORT.PIN2CTRL bit masks and bit positions */ -/* PORT_SRLEN Predefined. */ -/* PORT_SRLEN Predefined. */ - -/* PORT_INVEN Predefined. */ -/* PORT_INVEN Predefined. */ - -/* PORT_OPC Predefined. */ -/* PORT_OPC Predefined. */ - -/* PORT_ISC Predefined. */ -/* PORT_ISC Predefined. */ - -/* PORT.PIN3CTRL bit masks and bit positions */ -/* PORT_SRLEN Predefined. */ -/* PORT_SRLEN Predefined. */ - -/* PORT_INVEN Predefined. */ -/* PORT_INVEN Predefined. */ - -/* PORT_OPC Predefined. */ -/* PORT_OPC Predefined. */ - -/* PORT_ISC Predefined. */ -/* PORT_ISC Predefined. */ - -/* PORT.PIN4CTRL bit masks and bit positions */ -/* PORT_SRLEN Predefined. */ -/* PORT_SRLEN Predefined. */ - -/* PORT_INVEN Predefined. */ -/* PORT_INVEN Predefined. */ - -/* PORT_OPC Predefined. */ -/* PORT_OPC Predefined. */ - -/* PORT_ISC Predefined. */ -/* PORT_ISC Predefined. */ - -/* PORT.PIN5CTRL bit masks and bit positions */ -/* PORT_SRLEN Predefined. */ -/* PORT_SRLEN Predefined. */ - -/* PORT_INVEN Predefined. */ -/* PORT_INVEN Predefined. */ - -/* PORT_OPC Predefined. */ -/* PORT_OPC Predefined. */ - -/* PORT_ISC Predefined. */ -/* PORT_ISC Predefined. */ - -/* PORT.PIN6CTRL bit masks and bit positions */ -/* PORT_SRLEN Predefined. */ -/* PORT_SRLEN Predefined. */ - -/* PORT_INVEN Predefined. */ -/* PORT_INVEN Predefined. */ - -/* PORT_OPC Predefined. */ -/* PORT_OPC Predefined. */ - -/* PORT_ISC Predefined. */ -/* PORT_ISC Predefined. */ - -/* PORT.PIN7CTRL bit masks and bit positions */ -/* PORT_SRLEN Predefined. */ -/* PORT_SRLEN Predefined. */ - -/* PORT_INVEN Predefined. */ -/* PORT_INVEN Predefined. */ - -/* PORT_OPC Predefined. */ -/* PORT_OPC Predefined. */ - -/* PORT_ISC Predefined. */ -/* PORT_ISC Predefined. */ - -/* TC - 16-bit Timer/Counter With PWM */ -/* TC0.CTRLA bit masks and bit positions */ -#define TC0_CLKSEL_gm 0x0F /* Clock Selection group mask. */ -#define TC0_CLKSEL_gp 0 /* Clock Selection group position. */ -#define TC0_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ -#define TC0_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ -#define TC0_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ -#define TC0_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ -#define TC0_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ -#define TC0_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ -#define TC0_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ -#define TC0_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ - -/* TC0.CTRLB bit masks and bit positions */ -#define TC0_CCDEN_bm 0x80 /* Compare or Capture D Enable bit mask. */ -#define TC0_CCDEN_bp 7 /* Compare or Capture D Enable bit position. */ - -#define TC0_CCCEN_bm 0x40 /* Compare or Capture C Enable bit mask. */ -#define TC0_CCCEN_bp 6 /* Compare or Capture C Enable bit position. */ - -#define TC0_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ -#define TC0_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ - -#define TC0_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ -#define TC0_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ - -#define TC0_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ -#define TC0_WGMODE_gp 0 /* Waveform generation mode group position. */ -#define TC0_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ -#define TC0_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ -#define TC0_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ -#define TC0_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ -#define TC0_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ -#define TC0_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ - -/* TC0.CTRLC bit masks and bit positions */ -#define TC0_CMPD_bm 0x08 /* Compare D Output Value bit mask. */ -#define TC0_CMPD_bp 3 /* Compare D Output Value bit position. */ - -#define TC0_CMPC_bm 0x04 /* Compare C Output Value bit mask. */ -#define TC0_CMPC_bp 2 /* Compare C Output Value bit position. */ - -#define TC0_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ -#define TC0_CMPB_bp 1 /* Compare B Output Value bit position. */ - -#define TC0_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ -#define TC0_CMPA_bp 0 /* Compare A Output Value bit position. */ - -/* TC0.CTRLD bit masks and bit positions */ -#define TC0_EVACT_gm 0xE0 /* Event Action group mask. */ -#define TC0_EVACT_gp 5 /* Event Action group position. */ -#define TC0_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ -#define TC0_EVACT0_bp 5 /* Event Action bit 0 position. */ -#define TC0_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ -#define TC0_EVACT1_bp 6 /* Event Action bit 1 position. */ -#define TC0_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ -#define TC0_EVACT2_bp 7 /* Event Action bit 2 position. */ - -#define TC0_EVDLY_bm 0x10 /* Event Delay bit mask. */ -#define TC0_EVDLY_bp 4 /* Event Delay bit position. */ - -#define TC0_EVSEL_gm 0x0F /* Event Source Select group mask. */ -#define TC0_EVSEL_gp 0 /* Event Source Select group position. */ -#define TC0_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ -#define TC0_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ -#define TC0_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ -#define TC0_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ -#define TC0_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ -#define TC0_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ -#define TC0_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ -#define TC0_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ - -/* TC0.CTRLE bit masks and bit positions */ -#define TC0_BYTEM_gm 0x03 /* Byte Mode group mask. */ -#define TC0_BYTEM_gp 0 /* Byte Mode group position. */ -#define TC0_BYTEM0_bm (1<<0) /* Byte Mode bit 0 mask. */ -#define TC0_BYTEM0_bp 0 /* Byte Mode bit 0 position. */ -#define TC0_BYTEM1_bm (1<<1) /* Byte Mode bit 1 mask. */ -#define TC0_BYTEM1_bp 1 /* Byte Mode bit 1 position. */ - -/* TC0.INTCTRLA bit masks and bit positions */ -#define TC0_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ -#define TC0_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ -#define TC0_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ -#define TC0_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ -#define TC0_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ -#define TC0_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ - -#define TC0_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ -#define TC0_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ -#define TC0_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ -#define TC0_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ -#define TC0_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ -#define TC0_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ - -/* TC0.INTCTRLB bit masks and bit positions */ -#define TC0_CCDINTLVL_gm 0xC0 /* Compare or Capture D Interrupt Level group mask. */ -#define TC0_CCDINTLVL_gp 6 /* Compare or Capture D Interrupt Level group position. */ -#define TC0_CCDINTLVL0_bm (1<<6) /* Compare or Capture D Interrupt Level bit 0 mask. */ -#define TC0_CCDINTLVL0_bp 6 /* Compare or Capture D Interrupt Level bit 0 position. */ -#define TC0_CCDINTLVL1_bm (1<<7) /* Compare or Capture D Interrupt Level bit 1 mask. */ -#define TC0_CCDINTLVL1_bp 7 /* Compare or Capture D Interrupt Level bit 1 position. */ - -#define TC0_CCCINTLVL_gm 0x30 /* Compare or Capture C Interrupt Level group mask. */ -#define TC0_CCCINTLVL_gp 4 /* Compare or Capture C Interrupt Level group position. */ -#define TC0_CCCINTLVL0_bm (1<<4) /* Compare or Capture C Interrupt Level bit 0 mask. */ -#define TC0_CCCINTLVL0_bp 4 /* Compare or Capture C Interrupt Level bit 0 position. */ -#define TC0_CCCINTLVL1_bm (1<<5) /* Compare or Capture C Interrupt Level bit 1 mask. */ -#define TC0_CCCINTLVL1_bp 5 /* Compare or Capture C Interrupt Level bit 1 position. */ - -#define TC0_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ -#define TC0_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ -#define TC0_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ -#define TC0_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ -#define TC0_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ -#define TC0_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ - -#define TC0_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ -#define TC0_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ -#define TC0_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ -#define TC0_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ -#define TC0_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ -#define TC0_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ - -/* TC0.CTRLFCLR bit masks and bit positions */ -#define TC0_CMD_gm 0x0C /* Command group mask. */ -#define TC0_CMD_gp 2 /* Command group position. */ -#define TC0_CMD0_bm (1<<2) /* Command bit 0 mask. */ -#define TC0_CMD0_bp 2 /* Command bit 0 position. */ -#define TC0_CMD1_bm (1<<3) /* Command bit 1 mask. */ -#define TC0_CMD1_bp 3 /* Command bit 1 position. */ - -#define TC0_LUPD_bm 0x02 /* Lock Update bit mask. */ -#define TC0_LUPD_bp 1 /* Lock Update bit position. */ - -#define TC0_DIR_bm 0x01 /* Direction bit mask. */ -#define TC0_DIR_bp 0 /* Direction bit position. */ - -/* TC0.CTRLFSET bit masks and bit positions */ -/* TC0_CMD Predefined. */ -/* TC0_CMD Predefined. */ - -/* TC0_LUPD Predefined. */ -/* TC0_LUPD Predefined. */ - -/* TC0_DIR Predefined. */ -/* TC0_DIR Predefined. */ - -/* TC0.CTRLGCLR bit masks and bit positions */ -#define TC0_CCDBV_bm 0x10 /* Compare or Capture D Buffer Valid bit mask. */ -#define TC0_CCDBV_bp 4 /* Compare or Capture D Buffer Valid bit position. */ - -#define TC0_CCCBV_bm 0x08 /* Compare or Capture C Buffer Valid bit mask. */ -#define TC0_CCCBV_bp 3 /* Compare or Capture C Buffer Valid bit position. */ - -#define TC0_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ -#define TC0_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ - -#define TC0_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ -#define TC0_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ - -#define TC0_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ -#define TC0_PERBV_bp 0 /* Period Buffer Valid bit position. */ - -/* TC0.CTRLGSET bit masks and bit positions */ -/* TC0_CCDBV Predefined. */ -/* TC0_CCDBV Predefined. */ - -/* TC0_CCCBV Predefined. */ -/* TC0_CCCBV Predefined. */ - -/* TC0_CCBBV Predefined. */ -/* TC0_CCBBV Predefined. */ - -/* TC0_CCABV Predefined. */ -/* TC0_CCABV Predefined. */ - -/* TC0_PERBV Predefined. */ -/* TC0_PERBV Predefined. */ - -/* TC0.INTFLAGS bit masks and bit positions */ -#define TC0_CCDIF_bm 0x80 /* Compare or Capture D Interrupt Flag bit mask. */ -#define TC0_CCDIF_bp 7 /* Compare or Capture D Interrupt Flag bit position. */ - -#define TC0_CCCIF_bm 0x40 /* Compare or Capture C Interrupt Flag bit mask. */ -#define TC0_CCCIF_bp 6 /* Compare or Capture C Interrupt Flag bit position. */ - -#define TC0_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ -#define TC0_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ - -#define TC0_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ -#define TC0_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ - -#define TC0_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ -#define TC0_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ - -#define TC0_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ -#define TC0_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ - -/* TC1.CTRLA bit masks and bit positions */ -#define TC1_CLKSEL_gm 0x0F /* Clock Selection group mask. */ -#define TC1_CLKSEL_gp 0 /* Clock Selection group position. */ -#define TC1_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ -#define TC1_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ -#define TC1_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ -#define TC1_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ -#define TC1_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ -#define TC1_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ -#define TC1_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ -#define TC1_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ - -/* TC1.CTRLB bit masks and bit positions */ -#define TC1_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ -#define TC1_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ - -#define TC1_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ -#define TC1_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ - -#define TC1_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ -#define TC1_WGMODE_gp 0 /* Waveform generation mode group position. */ -#define TC1_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ -#define TC1_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ -#define TC1_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ -#define TC1_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ -#define TC1_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ -#define TC1_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ - -/* TC1.CTRLC bit masks and bit positions */ -#define TC1_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ -#define TC1_CMPB_bp 1 /* Compare B Output Value bit position. */ - -#define TC1_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ -#define TC1_CMPA_bp 0 /* Compare A Output Value bit position. */ - -/* TC1.CTRLD bit masks and bit positions */ -#define TC1_EVACT_gm 0xE0 /* Event Action group mask. */ -#define TC1_EVACT_gp 5 /* Event Action group position. */ -#define TC1_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ -#define TC1_EVACT0_bp 5 /* Event Action bit 0 position. */ -#define TC1_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ -#define TC1_EVACT1_bp 6 /* Event Action bit 1 position. */ -#define TC1_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ -#define TC1_EVACT2_bp 7 /* Event Action bit 2 position. */ - -#define TC1_EVDLY_bm 0x10 /* Event Delay bit mask. */ -#define TC1_EVDLY_bp 4 /* Event Delay bit position. */ - -#define TC1_EVSEL_gm 0x0F /* Event Source Select group mask. */ -#define TC1_EVSEL_gp 0 /* Event Source Select group position. */ -#define TC1_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ -#define TC1_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ -#define TC1_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ -#define TC1_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ -#define TC1_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ -#define TC1_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ -#define TC1_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ -#define TC1_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ - -/* TC1.CTRLE bit masks and bit positions */ -#define TC1_BYTEM_bm 0x01 /* Byte Mode bit mask. */ -#define TC1_BYTEM_bp 0 /* Byte Mode bit position. */ - -/* TC1.INTCTRLA bit masks and bit positions */ -#define TC1_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ -#define TC1_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ -#define TC1_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ -#define TC1_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ -#define TC1_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ -#define TC1_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ - -#define TC1_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ -#define TC1_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ -#define TC1_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ -#define TC1_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ -#define TC1_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ -#define TC1_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ - -/* TC1.INTCTRLB bit masks and bit positions */ -#define TC1_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ -#define TC1_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ -#define TC1_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ -#define TC1_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ -#define TC1_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ -#define TC1_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ - -#define TC1_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ -#define TC1_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ -#define TC1_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ -#define TC1_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ -#define TC1_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ -#define TC1_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ - -/* TC1.CTRLFCLR bit masks and bit positions */ -#define TC1_CMD_gm 0x0C /* Command group mask. */ -#define TC1_CMD_gp 2 /* Command group position. */ -#define TC1_CMD0_bm (1<<2) /* Command bit 0 mask. */ -#define TC1_CMD0_bp 2 /* Command bit 0 position. */ -#define TC1_CMD1_bm (1<<3) /* Command bit 1 mask. */ -#define TC1_CMD1_bp 3 /* Command bit 1 position. */ - -#define TC1_LUPD_bm 0x02 /* Lock Update bit mask. */ -#define TC1_LUPD_bp 1 /* Lock Update bit position. */ - -#define TC1_DIR_bm 0x01 /* Direction bit mask. */ -#define TC1_DIR_bp 0 /* Direction bit position. */ - -/* TC1.CTRLFSET bit masks and bit positions */ -/* TC1_CMD Predefined. */ -/* TC1_CMD Predefined. */ - -/* TC1_LUPD Predefined. */ -/* TC1_LUPD Predefined. */ - -/* TC1_DIR Predefined. */ -/* TC1_DIR Predefined. */ - -/* TC1.CTRLGCLR bit masks and bit positions */ -#define TC1_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ -#define TC1_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ - -#define TC1_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ -#define TC1_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ - -#define TC1_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ -#define TC1_PERBV_bp 0 /* Period Buffer Valid bit position. */ - -/* TC1.CTRLGSET bit masks and bit positions */ -/* TC1_CCBBV Predefined. */ -/* TC1_CCBBV Predefined. */ - -/* TC1_CCABV Predefined. */ -/* TC1_CCABV Predefined. */ - -/* TC1_PERBV Predefined. */ -/* TC1_PERBV Predefined. */ - -/* TC1.INTFLAGS bit masks and bit positions */ -#define TC1_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ -#define TC1_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ - -#define TC1_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ -#define TC1_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ - -#define TC1_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ -#define TC1_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ - -#define TC1_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ -#define TC1_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ - -/* TC2 - 16-bit Timer/Counter type 2 */ -/* TC2.CTRLA bit masks and bit positions */ -#define TC2_CLKSEL_gm 0x0F /* Clock Selection group mask. */ -#define TC2_CLKSEL_gp 0 /* Clock Selection group position. */ -#define TC2_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ -#define TC2_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ -#define TC2_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ -#define TC2_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ -#define TC2_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ -#define TC2_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ -#define TC2_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ -#define TC2_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ - -/* TC2.CTRLB bit masks and bit positions */ -#define TC2_HCMPDEN_bm 0x80 /* High Byte Compare D Enable bit mask. */ -#define TC2_HCMPDEN_bp 7 /* High Byte Compare D Enable bit position. */ - -#define TC2_HCMPCEN_bm 0x40 /* High Byte Compare C Enable bit mask. */ -#define TC2_HCMPCEN_bp 6 /* High Byte Compare C Enable bit position. */ - -#define TC2_HCMPBEN_bm 0x20 /* High Byte Compare B Enable bit mask. */ -#define TC2_HCMPBEN_bp 5 /* High Byte Compare B Enable bit position. */ - -#define TC2_HCMPAEN_bm 0x10 /* High Byte Compare A Enable bit mask. */ -#define TC2_HCMPAEN_bp 4 /* High Byte Compare A Enable bit position. */ - -#define TC2_LCMPDEN_bm 0x08 /* Low Byte Compare D Enable bit mask. */ -#define TC2_LCMPDEN_bp 3 /* Low Byte Compare D Enable bit position. */ - -#define TC2_LCMPCEN_bm 0x04 /* Low Byte Compare C Enable bit mask. */ -#define TC2_LCMPCEN_bp 2 /* Low Byte Compare C Enable bit position. */ - -#define TC2_LCMPBEN_bm 0x02 /* Low Byte Compare B Enable bit mask. */ -#define TC2_LCMPBEN_bp 1 /* Low Byte Compare B Enable bit position. */ - -#define TC2_LCMPAEN_bm 0x01 /* Low Byte Compare A Enable bit mask. */ -#define TC2_LCMPAEN_bp 0 /* Low Byte Compare A Enable bit position. */ - -/* TC2.CTRLC bit masks and bit positions */ -#define TC2_HCMPD_bm 0x80 /* High Byte Compare D Output Value bit mask. */ -#define TC2_HCMPD_bp 7 /* High Byte Compare D Output Value bit position. */ - -#define TC2_HCMPC_bm 0x40 /* High Byte Compare C Output Value bit mask. */ -#define TC2_HCMPC_bp 6 /* High Byte Compare C Output Value bit position. */ - -#define TC2_HCMPB_bm 0x20 /* High Byte Compare B Output Value bit mask. */ -#define TC2_HCMPB_bp 5 /* High Byte Compare B Output Value bit position. */ - -#define TC2_HCMPA_bm 0x10 /* High Byte Compare A Output Value bit mask. */ -#define TC2_HCMPA_bp 4 /* High Byte Compare A Output Value bit position. */ - -#define TC2_LCMPD_bm 0x08 /* Low Byte Compare D Output Value bit mask. */ -#define TC2_LCMPD_bp 3 /* Low Byte Compare D Output Value bit position. */ - -#define TC2_LCMPC_bm 0x04 /* Low Byte Compare C Output Value bit mask. */ -#define TC2_LCMPC_bp 2 /* Low Byte Compare C Output Value bit position. */ - -#define TC2_LCMPB_bm 0x02 /* Low Byte Compare B Output Value bit mask. */ -#define TC2_LCMPB_bp 1 /* Low Byte Compare B Output Value bit position. */ - -#define TC2_LCMPA_bm 0x01 /* Low Byte Compare A Output Value bit mask. */ -#define TC2_LCMPA_bp 0 /* Low Byte Compare A Output Value bit position. */ - -/* TC2.CTRLE bit masks and bit positions */ -#define TC2_BYTEM_gm 0x03 /* Byte Mode group mask. */ -#define TC2_BYTEM_gp 0 /* Byte Mode group position. */ -#define TC2_BYTEM0_bm (1<<0) /* Byte Mode bit 0 mask. */ -#define TC2_BYTEM0_bp 0 /* Byte Mode bit 0 position. */ -#define TC2_BYTEM1_bm (1<<1) /* Byte Mode bit 1 mask. */ -#define TC2_BYTEM1_bp 1 /* Byte Mode bit 1 position. */ - -/* TC2.INTCTRLA bit masks and bit positions */ -#define TC2_HUNFINTLVL_gm 0x0C /* High Byte Underflow Interrupt Level group mask. */ -#define TC2_HUNFINTLVL_gp 2 /* High Byte Underflow Interrupt Level group position. */ -#define TC2_HUNFINTLVL0_bm (1<<2) /* High Byte Underflow Interrupt Level bit 0 mask. */ -#define TC2_HUNFINTLVL0_bp 2 /* High Byte Underflow Interrupt Level bit 0 position. */ -#define TC2_HUNFINTLVL1_bm (1<<3) /* High Byte Underflow Interrupt Level bit 1 mask. */ -#define TC2_HUNFINTLVL1_bp 3 /* High Byte Underflow Interrupt Level bit 1 position. */ - -#define TC2_LUNFINTLVL_gm 0x03 /* Low Byte Underflow interrupt level group mask. */ -#define TC2_LUNFINTLVL_gp 0 /* Low Byte Underflow interrupt level group position. */ -#define TC2_LUNFINTLVL0_bm (1<<0) /* Low Byte Underflow interrupt level bit 0 mask. */ -#define TC2_LUNFINTLVL0_bp 0 /* Low Byte Underflow interrupt level bit 0 position. */ -#define TC2_LUNFINTLVL1_bm (1<<1) /* Low Byte Underflow interrupt level bit 1 mask. */ -#define TC2_LUNFINTLVL1_bp 1 /* Low Byte Underflow interrupt level bit 1 position. */ - -/* TC2.INTCTRLB bit masks and bit positions */ -#define TC2_LCMPDINTLVL_gm 0xC0 /* Low Byte Compare D Interrupt Level group mask. */ -#define TC2_LCMPDINTLVL_gp 6 /* Low Byte Compare D Interrupt Level group position. */ -#define TC2_LCMPDINTLVL0_bm (1<<6) /* Low Byte Compare D Interrupt Level bit 0 mask. */ -#define TC2_LCMPDINTLVL0_bp 6 /* Low Byte Compare D Interrupt Level bit 0 position. */ -#define TC2_LCMPDINTLVL1_bm (1<<7) /* Low Byte Compare D Interrupt Level bit 1 mask. */ -#define TC2_LCMPDINTLVL1_bp 7 /* Low Byte Compare D Interrupt Level bit 1 position. */ - -#define TC2_LCMPCINTLVL_gm 0x30 /* Low Byte Compare C Interrupt Level group mask. */ -#define TC2_LCMPCINTLVL_gp 4 /* Low Byte Compare C Interrupt Level group position. */ -#define TC2_LCMPCINTLVL0_bm (1<<4) /* Low Byte Compare C Interrupt Level bit 0 mask. */ -#define TC2_LCMPCINTLVL0_bp 4 /* Low Byte Compare C Interrupt Level bit 0 position. */ -#define TC2_LCMPCINTLVL1_bm (1<<5) /* Low Byte Compare C Interrupt Level bit 1 mask. */ -#define TC2_LCMPCINTLVL1_bp 5 /* Low Byte Compare C Interrupt Level bit 1 position. */ - -#define TC2_LCMPBINTLVL_gm 0x0C /* Low Byte Compare B Interrupt Level group mask. */ -#define TC2_LCMPBINTLVL_gp 2 /* Low Byte Compare B Interrupt Level group position. */ -#define TC2_LCMPBINTLVL0_bm (1<<2) /* Low Byte Compare B Interrupt Level bit 0 mask. */ -#define TC2_LCMPBINTLVL0_bp 2 /* Low Byte Compare B Interrupt Level bit 0 position. */ -#define TC2_LCMPBINTLVL1_bm (1<<3) /* Low Byte Compare B Interrupt Level bit 1 mask. */ -#define TC2_LCMPBINTLVL1_bp 3 /* Low Byte Compare B Interrupt Level bit 1 position. */ - -#define TC2_LCMPAINTLVL_gm 0x03 /* Low Byte Compare A Interrupt Level group mask. */ -#define TC2_LCMPAINTLVL_gp 0 /* Low Byte Compare A Interrupt Level group position. */ -#define TC2_LCMPAINTLVL0_bm (1<<0) /* Low Byte Compare A Interrupt Level bit 0 mask. */ -#define TC2_LCMPAINTLVL0_bp 0 /* Low Byte Compare A Interrupt Level bit 0 position. */ -#define TC2_LCMPAINTLVL1_bm (1<<1) /* Low Byte Compare A Interrupt Level bit 1 mask. */ -#define TC2_LCMPAINTLVL1_bp 1 /* Low Byte Compare A Interrupt Level bit 1 position. */ - -/* TC2.CTRLF bit masks and bit positions */ -#define TC2_CMD_gm 0x0C /* Command group mask. */ -#define TC2_CMD_gp 2 /* Command group position. */ -#define TC2_CMD0_bm (1<<2) /* Command bit 0 mask. */ -#define TC2_CMD0_bp 2 /* Command bit 0 position. */ -#define TC2_CMD1_bm (1<<3) /* Command bit 1 mask. */ -#define TC2_CMD1_bp 3 /* Command bit 1 position. */ - -#define TC2_CMDEN_gm 0x03 /* Command Enable group mask. */ -#define TC2_CMDEN_gp 0 /* Command Enable group position. */ -#define TC2_CMDEN0_bm (1<<0) /* Command Enable bit 0 mask. */ -#define TC2_CMDEN0_bp 0 /* Command Enable bit 0 position. */ -#define TC2_CMDEN1_bm (1<<1) /* Command Enable bit 1 mask. */ -#define TC2_CMDEN1_bp 1 /* Command Enable bit 1 position. */ - -/* TC2.INTFLAGS bit masks and bit positions */ -#define TC2_LCMPDIF_bm 0x80 /* Low Byte Compare D Interrupt Flag bit mask. */ -#define TC2_LCMPDIF_bp 7 /* Low Byte Compare D Interrupt Flag bit position. */ - -#define TC2_LCMPCIF_bm 0x40 /* Low Byte Compare C Interrupt Flag bit mask. */ -#define TC2_LCMPCIF_bp 6 /* Low Byte Compare C Interrupt Flag bit position. */ - -#define TC2_LCMPBIF_bm 0x20 /* Low Byte Compare B Interrupt Flag bit mask. */ -#define TC2_LCMPBIF_bp 5 /* Low Byte Compare B Interrupt Flag bit position. */ - -#define TC2_LCMPAIF_bm 0x10 /* Low Byte Compare A Interrupt Flag bit mask. */ -#define TC2_LCMPAIF_bp 4 /* Low Byte Compare A Interrupt Flag bit position. */ - -#define TC2_HUNFIF_bm 0x02 /* High Byte Underflow Interrupt Flag bit mask. */ -#define TC2_HUNFIF_bp 1 /* High Byte Underflow Interrupt Flag bit position. */ - -#define TC2_LUNFIF_bm 0x01 /* Low Byte Underflow Interrupt Flag bit mask. */ -#define TC2_LUNFIF_bp 0 /* Low Byte Underflow Interrupt Flag bit position. */ - -/* AWEX - Timer/Counter Advanced Waveform Extension */ -/* AWEX.CTRL bit masks and bit positions */ -#define AWEX_PGM_bm 0x20 /* Pattern Generation Mode bit mask. */ -#define AWEX_PGM_bp 5 /* Pattern Generation Mode bit position. */ - -#define AWEX_CWCM_bm 0x10 /* Common Waveform Channel Mode bit mask. */ -#define AWEX_CWCM_bp 4 /* Common Waveform Channel Mode bit position. */ - -#define AWEX_DTICCDEN_bm 0x08 /* Dead Time Insertion Compare Channel D Enable bit mask. */ -#define AWEX_DTICCDEN_bp 3 /* Dead Time Insertion Compare Channel D Enable bit position. */ - -#define AWEX_DTICCCEN_bm 0x04 /* Dead Time Insertion Compare Channel C Enable bit mask. */ -#define AWEX_DTICCCEN_bp 2 /* Dead Time Insertion Compare Channel C Enable bit position. */ - -#define AWEX_DTICCBEN_bm 0x02 /* Dead Time Insertion Compare Channel B Enable bit mask. */ -#define AWEX_DTICCBEN_bp 1 /* Dead Time Insertion Compare Channel B Enable bit position. */ - -#define AWEX_DTICCAEN_bm 0x01 /* Dead Time Insertion Compare Channel A Enable bit mask. */ -#define AWEX_DTICCAEN_bp 0 /* Dead Time Insertion Compare Channel A Enable bit position. */ - -/* AWEX.FDCTRL bit masks and bit positions */ -#define AWEX_FDDBD_bm 0x10 /* Fault Detect on Disable Break Disable bit mask. */ -#define AWEX_FDDBD_bp 4 /* Fault Detect on Disable Break Disable bit position. */ - -#define AWEX_FDMODE_bm 0x04 /* Fault Detect Mode bit mask. */ -#define AWEX_FDMODE_bp 2 /* Fault Detect Mode bit position. */ - -#define AWEX_FDACT_gm 0x03 /* Fault Detect Action group mask. */ -#define AWEX_FDACT_gp 0 /* Fault Detect Action group position. */ -#define AWEX_FDACT0_bm (1<<0) /* Fault Detect Action bit 0 mask. */ -#define AWEX_FDACT0_bp 0 /* Fault Detect Action bit 0 position. */ -#define AWEX_FDACT1_bm (1<<1) /* Fault Detect Action bit 1 mask. */ -#define AWEX_FDACT1_bp 1 /* Fault Detect Action bit 1 position. */ - -/* AWEX.STATUS bit masks and bit positions */ -#define AWEX_FDF_bm 0x04 /* Fault Detect Flag bit mask. */ -#define AWEX_FDF_bp 2 /* Fault Detect Flag bit position. */ - -#define AWEX_DTHSBUFV_bm 0x02 /* Dead Time High Side Buffer Valid bit mask. */ -#define AWEX_DTHSBUFV_bp 1 /* Dead Time High Side Buffer Valid bit position. */ - -#define AWEX_DTLSBUFV_bm 0x01 /* Dead Time Low Side Buffer Valid bit mask. */ -#define AWEX_DTLSBUFV_bp 0 /* Dead Time Low Side Buffer Valid bit position. */ - -/* AWEX.STATUSSET bit masks and bit positions */ -/* AWEX_FDF Predefined. */ -/* AWEX_FDF Predefined. */ - -/* AWEX_DTHSBUFV Predefined. */ -/* AWEX_DTHSBUFV Predefined. */ - -/* AWEX_DTLSBUFV Predefined. */ -/* AWEX_DTLSBUFV Predefined. */ - -/* HIRES - Timer/Counter High-Resolution Extension */ -/* HIRES.CTRLA bit masks and bit positions */ -#define HIRES_HREN_gm 0x03 /* High Resolution Enable group mask. */ -#define HIRES_HREN_gp 0 /* High Resolution Enable group position. */ -#define HIRES_HREN0_bm (1<<0) /* High Resolution Enable bit 0 mask. */ -#define HIRES_HREN0_bp 0 /* High Resolution Enable bit 0 position. */ -#define HIRES_HREN1_bm (1<<1) /* High Resolution Enable bit 1 mask. */ -#define HIRES_HREN1_bp 1 /* High Resolution Enable bit 1 position. */ - -/* USART - Universal Asynchronous Receiver-Transmitter */ -/* USART.STATUS bit masks and bit positions */ -#define USART_RXCIF_bm 0x80 /* Receive Interrupt Flag bit mask. */ -#define USART_RXCIF_bp 7 /* Receive Interrupt Flag bit position. */ - -#define USART_TXCIF_bm 0x40 /* Transmit Interrupt Flag bit mask. */ -#define USART_TXCIF_bp 6 /* Transmit Interrupt Flag bit position. */ - -#define USART_DREIF_bm 0x20 /* Data Register Empty Flag bit mask. */ -#define USART_DREIF_bp 5 /* Data Register Empty Flag bit position. */ - -#define USART_FERR_bm 0x10 /* Frame Error bit mask. */ -#define USART_FERR_bp 4 /* Frame Error bit position. */ - -#define USART_BUFOVF_bm 0x08 /* Buffer Overflow bit mask. */ -#define USART_BUFOVF_bp 3 /* Buffer Overflow bit position. */ - -#define USART_PERR_bm 0x04 /* Parity Error bit mask. */ -#define USART_PERR_bp 2 /* Parity Error bit position. */ - -#define USART_RXB8_bm 0x01 /* Receive Bit 8 bit mask. */ -#define USART_RXB8_bp 0 /* Receive Bit 8 bit position. */ - -/* USART.CTRLA bit masks and bit positions */ -#define USART_RXCINTLVL_gm 0x30 /* Receive Interrupt Level group mask. */ -#define USART_RXCINTLVL_gp 4 /* Receive Interrupt Level group position. */ -#define USART_RXCINTLVL0_bm (1<<4) /* Receive Interrupt Level bit 0 mask. */ -#define USART_RXCINTLVL0_bp 4 /* Receive Interrupt Level bit 0 position. */ -#define USART_RXCINTLVL1_bm (1<<5) /* Receive Interrupt Level bit 1 mask. */ -#define USART_RXCINTLVL1_bp 5 /* Receive Interrupt Level bit 1 position. */ - -#define USART_TXCINTLVL_gm 0x0C /* Transmit Interrupt Level group mask. */ -#define USART_TXCINTLVL_gp 2 /* Transmit Interrupt Level group position. */ -#define USART_TXCINTLVL0_bm (1<<2) /* Transmit Interrupt Level bit 0 mask. */ -#define USART_TXCINTLVL0_bp 2 /* Transmit Interrupt Level bit 0 position. */ -#define USART_TXCINTLVL1_bm (1<<3) /* Transmit Interrupt Level bit 1 mask. */ -#define USART_TXCINTLVL1_bp 3 /* Transmit Interrupt Level bit 1 position. */ - -#define USART_DREINTLVL_gm 0x03 /* Data Register Empty Interrupt Level group mask. */ -#define USART_DREINTLVL_gp 0 /* Data Register Empty Interrupt Level group position. */ -#define USART_DREINTLVL0_bm (1<<0) /* Data Register Empty Interrupt Level bit 0 mask. */ -#define USART_DREINTLVL0_bp 0 /* Data Register Empty Interrupt Level bit 0 position. */ -#define USART_DREINTLVL1_bm (1<<1) /* Data Register Empty Interrupt Level bit 1 mask. */ -#define USART_DREINTLVL1_bp 1 /* Data Register Empty Interrupt Level bit 1 position. */ - -/* USART.CTRLB bit masks and bit positions */ -#define USART_RXEN_bm 0x10 /* Receiver Enable bit mask. */ -#define USART_RXEN_bp 4 /* Receiver Enable bit position. */ - -#define USART_TXEN_bm 0x08 /* Transmitter Enable bit mask. */ -#define USART_TXEN_bp 3 /* Transmitter Enable bit position. */ - -#define USART_CLK2X_bm 0x04 /* Double transmission speed bit mask. */ -#define USART_CLK2X_bp 2 /* Double transmission speed bit position. */ - -#define USART_MPCM_bm 0x02 /* Multi-processor Communication Mode bit mask. */ -#define USART_MPCM_bp 1 /* Multi-processor Communication Mode bit position. */ - -#define USART_TXB8_bm 0x01 /* Transmit bit 8 bit mask. */ -#define USART_TXB8_bp 0 /* Transmit bit 8 bit position. */ - -/* USART.CTRLC bit masks and bit positions */ -#define USART_CMODE_gm 0xC0 /* Communication Mode group mask. */ -#define USART_CMODE_gp 6 /* Communication Mode group position. */ -#define USART_CMODE0_bm (1<<6) /* Communication Mode bit 0 mask. */ -#define USART_CMODE0_bp 6 /* Communication Mode bit 0 position. */ -#define USART_CMODE1_bm (1<<7) /* Communication Mode bit 1 mask. */ -#define USART_CMODE1_bp 7 /* Communication Mode bit 1 position. */ - -#define USART_PMODE_gm 0x30 /* Parity Mode group mask. */ -#define USART_PMODE_gp 4 /* Parity Mode group position. */ -#define USART_PMODE0_bm (1<<4) /* Parity Mode bit 0 mask. */ -#define USART_PMODE0_bp 4 /* Parity Mode bit 0 position. */ -#define USART_PMODE1_bm (1<<5) /* Parity Mode bit 1 mask. */ -#define USART_PMODE1_bp 5 /* Parity Mode bit 1 position. */ - -#define USART_SBMODE_bm 0x08 /* Stop Bit Mode bit mask. */ -#define USART_SBMODE_bp 3 /* Stop Bit Mode bit position. */ - -#define USART_CHSIZE_gm 0x07 /* Character Size group mask. */ -#define USART_CHSIZE_gp 0 /* Character Size group position. */ -#define USART_CHSIZE0_bm (1<<0) /* Character Size bit 0 mask. */ -#define USART_CHSIZE0_bp 0 /* Character Size bit 0 position. */ -#define USART_CHSIZE1_bm (1<<1) /* Character Size bit 1 mask. */ -#define USART_CHSIZE1_bp 1 /* Character Size bit 1 position. */ -#define USART_CHSIZE2_bm (1<<2) /* Character Size bit 2 mask. */ -#define USART_CHSIZE2_bp 2 /* Character Size bit 2 position. */ - -/* USART.BAUDCTRLA bit masks and bit positions */ -#define USART_BSEL_gm 0xFF /* Baud Rate Selection Bits [7:0] group mask. */ -#define USART_BSEL_gp 0 /* Baud Rate Selection Bits [7:0] group position. */ -#define USART_BSEL0_bm (1<<0) /* Baud Rate Selection Bits [7:0] bit 0 mask. */ -#define USART_BSEL0_bp 0 /* Baud Rate Selection Bits [7:0] bit 0 position. */ -#define USART_BSEL1_bm (1<<1) /* Baud Rate Selection Bits [7:0] bit 1 mask. */ -#define USART_BSEL1_bp 1 /* Baud Rate Selection Bits [7:0] bit 1 position. */ -#define USART_BSEL2_bm (1<<2) /* Baud Rate Selection Bits [7:0] bit 2 mask. */ -#define USART_BSEL2_bp 2 /* Baud Rate Selection Bits [7:0] bit 2 position. */ -#define USART_BSEL3_bm (1<<3) /* Baud Rate Selection Bits [7:0] bit 3 mask. */ -#define USART_BSEL3_bp 3 /* Baud Rate Selection Bits [7:0] bit 3 position. */ -#define USART_BSEL4_bm (1<<4) /* Baud Rate Selection Bits [7:0] bit 4 mask. */ -#define USART_BSEL4_bp 4 /* Baud Rate Selection Bits [7:0] bit 4 position. */ -#define USART_BSEL5_bm (1<<5) /* Baud Rate Selection Bits [7:0] bit 5 mask. */ -#define USART_BSEL5_bp 5 /* Baud Rate Selection Bits [7:0] bit 5 position. */ -#define USART_BSEL6_bm (1<<6) /* Baud Rate Selection Bits [7:0] bit 6 mask. */ -#define USART_BSEL6_bp 6 /* Baud Rate Selection Bits [7:0] bit 6 position. */ -#define USART_BSEL7_bm (1<<7) /* Baud Rate Selection Bits [7:0] bit 7 mask. */ -#define USART_BSEL7_bp 7 /* Baud Rate Selection Bits [7:0] bit 7 position. */ - -/* USART.BAUDCTRLB bit masks and bit positions */ -#define USART_BSCALE_gm 0xF0 /* Baud Rate Scale group mask. */ -#define USART_BSCALE_gp 4 /* Baud Rate Scale group position. */ -#define USART_BSCALE0_bm (1<<4) /* Baud Rate Scale bit 0 mask. */ -#define USART_BSCALE0_bp 4 /* Baud Rate Scale bit 0 position. */ -#define USART_BSCALE1_bm (1<<5) /* Baud Rate Scale bit 1 mask. */ -#define USART_BSCALE1_bp 5 /* Baud Rate Scale bit 1 position. */ -#define USART_BSCALE2_bm (1<<6) /* Baud Rate Scale bit 2 mask. */ -#define USART_BSCALE2_bp 6 /* Baud Rate Scale bit 2 position. */ -#define USART_BSCALE3_bm (1<<7) /* Baud Rate Scale bit 3 mask. */ -#define USART_BSCALE3_bp 7 /* Baud Rate Scale bit 3 position. */ - -/* USART_BSEL Predefined. */ -/* USART_BSEL Predefined. */ - -/* SPI - Serial Peripheral Interface */ -/* SPI.CTRL bit masks and bit positions */ -#define SPI_CLK2X_bm 0x80 /* Enable Double Speed bit mask. */ -#define SPI_CLK2X_bp 7 /* Enable Double Speed bit position. */ - -#define SPI_ENABLE_bm 0x40 /* Enable Module bit mask. */ -#define SPI_ENABLE_bp 6 /* Enable Module bit position. */ - -#define SPI_DORD_bm 0x20 /* Data Order Setting bit mask. */ -#define SPI_DORD_bp 5 /* Data Order Setting bit position. */ - -#define SPI_MASTER_bm 0x10 /* Master Operation Enable bit mask. */ -#define SPI_MASTER_bp 4 /* Master Operation Enable bit position. */ - -#define SPI_MODE_gm 0x0C /* SPI Mode group mask. */ -#define SPI_MODE_gp 2 /* SPI Mode group position. */ -#define SPI_MODE0_bm (1<<2) /* SPI Mode bit 0 mask. */ -#define SPI_MODE0_bp 2 /* SPI Mode bit 0 position. */ -#define SPI_MODE1_bm (1<<3) /* SPI Mode bit 1 mask. */ -#define SPI_MODE1_bp 3 /* SPI Mode bit 1 position. */ - -#define SPI_PRESCALER_gm 0x03 /* Prescaler group mask. */ -#define SPI_PRESCALER_gp 0 /* Prescaler group position. */ -#define SPI_PRESCALER0_bm (1<<0) /* Prescaler bit 0 mask. */ -#define SPI_PRESCALER0_bp 0 /* Prescaler bit 0 position. */ -#define SPI_PRESCALER1_bm (1<<1) /* Prescaler bit 1 mask. */ -#define SPI_PRESCALER1_bp 1 /* Prescaler bit 1 position. */ - -/* SPI.INTCTRL bit masks and bit positions */ -#define SPI_INTLVL_gm 0x03 /* Interrupt level group mask. */ -#define SPI_INTLVL_gp 0 /* Interrupt level group position. */ -#define SPI_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */ -#define SPI_INTLVL0_bp 0 /* Interrupt level bit 0 position. */ -#define SPI_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */ -#define SPI_INTLVL1_bp 1 /* Interrupt level bit 1 position. */ - -/* SPI.STATUS bit masks and bit positions */ -#define SPI_IF_bm 0x80 /* Interrupt Flag bit mask. */ -#define SPI_IF_bp 7 /* Interrupt Flag bit position. */ - -#define SPI_WRCOL_bm 0x40 /* Write Collision bit mask. */ -#define SPI_WRCOL_bp 6 /* Write Collision bit position. */ - -/* IRCOM - IR Communication Module */ -/* IRCOM.CTRL bit masks and bit positions */ -#define IRCOM_EVSEL_gm 0x0F /* Event Channel Select group mask. */ -#define IRCOM_EVSEL_gp 0 /* Event Channel Select group position. */ -#define IRCOM_EVSEL0_bm (1<<0) /* Event Channel Select bit 0 mask. */ -#define IRCOM_EVSEL0_bp 0 /* Event Channel Select bit 0 position. */ -#define IRCOM_EVSEL1_bm (1<<1) /* Event Channel Select bit 1 mask. */ -#define IRCOM_EVSEL1_bp 1 /* Event Channel Select bit 1 position. */ -#define IRCOM_EVSEL2_bm (1<<2) /* Event Channel Select bit 2 mask. */ -#define IRCOM_EVSEL2_bp 2 /* Event Channel Select bit 2 position. */ -#define IRCOM_EVSEL3_bm (1<<3) /* Event Channel Select bit 3 mask. */ -#define IRCOM_EVSEL3_bp 3 /* Event Channel Select bit 3 position. */ - -/* FUSE - Fuses and Lockbits */ -/* NVM_FUSES.FUSEBYTE1 bit masks and bit positions */ -#define NVM_FUSES_WDWP_gm 0xF0 /* Watchdog Window Timeout Period group mask. */ -#define NVM_FUSES_WDWP_gp 4 /* Watchdog Window Timeout Period group position. */ -#define NVM_FUSES_WDWP0_bm (1<<4) /* Watchdog Window Timeout Period bit 0 mask. */ -#define NVM_FUSES_WDWP0_bp 4 /* Watchdog Window Timeout Period bit 0 position. */ -#define NVM_FUSES_WDWP1_bm (1<<5) /* Watchdog Window Timeout Period bit 1 mask. */ -#define NVM_FUSES_WDWP1_bp 5 /* Watchdog Window Timeout Period bit 1 position. */ -#define NVM_FUSES_WDWP2_bm (1<<6) /* Watchdog Window Timeout Period bit 2 mask. */ -#define NVM_FUSES_WDWP2_bp 6 /* Watchdog Window Timeout Period bit 2 position. */ -#define NVM_FUSES_WDWP3_bm (1<<7) /* Watchdog Window Timeout Period bit 3 mask. */ -#define NVM_FUSES_WDWP3_bp 7 /* Watchdog Window Timeout Period bit 3 position. */ - -#define NVM_FUSES_WDP_gm 0x0F /* Watchdog Timeout Period group mask. */ -#define NVM_FUSES_WDP_gp 0 /* Watchdog Timeout Period group position. */ -#define NVM_FUSES_WDP0_bm (1<<0) /* Watchdog Timeout Period bit 0 mask. */ -#define NVM_FUSES_WDP0_bp 0 /* Watchdog Timeout Period bit 0 position. */ -#define NVM_FUSES_WDP1_bm (1<<1) /* Watchdog Timeout Period bit 1 mask. */ -#define NVM_FUSES_WDP1_bp 1 /* Watchdog Timeout Period bit 1 position. */ -#define NVM_FUSES_WDP2_bm (1<<2) /* Watchdog Timeout Period bit 2 mask. */ -#define NVM_FUSES_WDP2_bp 2 /* Watchdog Timeout Period bit 2 position. */ -#define NVM_FUSES_WDP3_bm (1<<3) /* Watchdog Timeout Period bit 3 mask. */ -#define NVM_FUSES_WDP3_bp 3 /* Watchdog Timeout Period bit 3 position. */ - -/* NVM_FUSES.FUSEBYTE2 bit masks and bit positions */ -#define NVM_FUSES_BOOTRST_bm 0x40 /* Boot Loader Section Reset Vector bit mask. */ -#define NVM_FUSES_BOOTRST_bp 6 /* Boot Loader Section Reset Vector bit position. */ - -#define NVM_FUSES_TOSCSEL_bm 0x20 /* Timer Oscillator pin location bit mask. */ -#define NVM_FUSES_TOSCSEL_bp 5 /* Timer Oscillator pin location bit position. */ - -#define NVM_FUSES_BODPD_gm 0x03 /* BOD Operation in Power-Down Mode group mask. */ -#define NVM_FUSES_BODPD_gp 0 /* BOD Operation in Power-Down Mode group position. */ -#define NVM_FUSES_BODPD0_bm (1<<0) /* BOD Operation in Power-Down Mode bit 0 mask. */ -#define NVM_FUSES_BODPD0_bp 0 /* BOD Operation in Power-Down Mode bit 0 position. */ -#define NVM_FUSES_BODPD1_bm (1<<1) /* BOD Operation in Power-Down Mode bit 1 mask. */ -#define NVM_FUSES_BODPD1_bp 1 /* BOD Operation in Power-Down Mode bit 1 position. */ - -/* NVM_FUSES.FUSEBYTE4 bit masks and bit positions */ -#define NVM_FUSES_RSTDISBL_bm 0x10 /* External Reset Disable bit mask. */ -#define NVM_FUSES_RSTDISBL_bp 4 /* External Reset Disable bit position. */ - -#define NVM_FUSES_SUT_gm 0x0C /* Start-up Time group mask. */ -#define NVM_FUSES_SUT_gp 2 /* Start-up Time group position. */ -#define NVM_FUSES_SUT0_bm (1<<2) /* Start-up Time bit 0 mask. */ -#define NVM_FUSES_SUT0_bp 2 /* Start-up Time bit 0 position. */ -#define NVM_FUSES_SUT1_bm (1<<3) /* Start-up Time bit 1 mask. */ -#define NVM_FUSES_SUT1_bp 3 /* Start-up Time bit 1 position. */ - -#define NVM_FUSES_WDLOCK_bm 0x02 /* Watchdog Timer Lock bit mask. */ -#define NVM_FUSES_WDLOCK_bp 1 /* Watchdog Timer Lock bit position. */ - -/* NVM_FUSES.FUSEBYTE5 bit masks and bit positions */ -#define NVM_FUSES_BODACT_gm 0x30 /* BOD Operation in Active Mode group mask. */ -#define NVM_FUSES_BODACT_gp 4 /* BOD Operation in Active Mode group position. */ -#define NVM_FUSES_BODACT0_bm (1<<4) /* BOD Operation in Active Mode bit 0 mask. */ -#define NVM_FUSES_BODACT0_bp 4 /* BOD Operation in Active Mode bit 0 position. */ -#define NVM_FUSES_BODACT1_bm (1<<5) /* BOD Operation in Active Mode bit 1 mask. */ -#define NVM_FUSES_BODACT1_bp 5 /* BOD Operation in Active Mode bit 1 position. */ - -#define NVM_FUSES_EESAVE_bm 0x08 /* Preserve EEPROM Through Chip Erase bit mask. */ -#define NVM_FUSES_EESAVE_bp 3 /* Preserve EEPROM Through Chip Erase bit position. */ - -#define NVM_FUSES_BODLVL_gm 0x07 /* Brownout Detection Voltage Level group mask. */ -#define NVM_FUSES_BODLVL_gp 0 /* Brownout Detection Voltage Level group position. */ -#define NVM_FUSES_BODLVL0_bm (1<<0) /* Brownout Detection Voltage Level bit 0 mask. */ -#define NVM_FUSES_BODLVL0_bp 0 /* Brownout Detection Voltage Level bit 0 position. */ -#define NVM_FUSES_BODLVL1_bm (1<<1) /* Brownout Detection Voltage Level bit 1 mask. */ -#define NVM_FUSES_BODLVL1_bp 1 /* Brownout Detection Voltage Level bit 1 position. */ -#define NVM_FUSES_BODLVL2_bm (1<<2) /* Brownout Detection Voltage Level bit 2 mask. */ -#define NVM_FUSES_BODLVL2_bp 2 /* Brownout Detection Voltage Level bit 2 position. */ - -/* LOCKBIT - Fuses and Lockbits */ -/* NVM_LOCKBITS.LOCKBITS bit masks and bit positions */ -#define NVM_LOCKBITS_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ -#define NVM_LOCKBITS_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ -#define NVM_LOCKBITS_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ -#define NVM_LOCKBITS_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ -#define NVM_LOCKBITS_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ -#define NVM_LOCKBITS_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ - -#define NVM_LOCKBITS_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ -#define NVM_LOCKBITS_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ -#define NVM_LOCKBITS_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ -#define NVM_LOCKBITS_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ -#define NVM_LOCKBITS_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ -#define NVM_LOCKBITS_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ - -#define NVM_LOCKBITS_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ -#define NVM_LOCKBITS_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ -#define NVM_LOCKBITS_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ -#define NVM_LOCKBITS_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ -#define NVM_LOCKBITS_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ -#define NVM_LOCKBITS_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ - -#define NVM_LOCKBITS_LB_gm 0x03 /* Lock Bits group mask. */ -#define NVM_LOCKBITS_LB_gp 0 /* Lock Bits group position. */ -#define NVM_LOCKBITS_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ -#define NVM_LOCKBITS_LB0_bp 0 /* Lock Bits bit 0 position. */ -#define NVM_LOCKBITS_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ -#define NVM_LOCKBITS_LB1_bp 1 /* Lock Bits bit 1 position. */ - - - -// Generic Port Pins - -#define PIN0_bm 0x01 -#define PIN0_bp 0 -#define PIN1_bm 0x02 -#define PIN1_bp 1 -#define PIN2_bm 0x04 -#define PIN2_bp 2 -#define PIN3_bm 0x08 -#define PIN3_bp 3 -#define PIN4_bm 0x10 -#define PIN4_bp 4 -#define PIN5_bm 0x20 -#define PIN5_bp 5 -#define PIN6_bm 0x40 -#define PIN6_bp 6 -#define PIN7_bm 0x80 -#define PIN7_bp 7 - -/* ========== Interrupt Vector Definitions ========== */ -/* Vector 0 is the reset vector */ - -/* OSC interrupt vectors */ -#define OSC_OSCF_vect_num 1 -#define OSC_OSCF_vect _VECTOR(1) /* Oscillator Failure Interrupt (NMI) */ - -/* PORTC interrupt vectors */ -#define PORTC_INT0_vect_num 2 -#define PORTC_INT0_vect _VECTOR(2) /* External Interrupt 0 */ -#define PORTC_INT1_vect_num 3 -#define PORTC_INT1_vect _VECTOR(3) /* External Interrupt 1 */ - -/* PORTR interrupt vectors */ -#define PORTR_INT0_vect_num 4 -#define PORTR_INT0_vect _VECTOR(4) /* External Interrupt 0 */ -#define PORTR_INT1_vect_num 5 -#define PORTR_INT1_vect _VECTOR(5) /* External Interrupt 1 */ - -/* RTC interrupt vectors */ -#define RTC_OVF_vect_num 10 -#define RTC_OVF_vect _VECTOR(10) /* Overflow Interrupt */ -#define RTC_COMP_vect_num 11 -#define RTC_COMP_vect _VECTOR(11) /* Compare Interrupt */ - -/* TWIC interrupt vectors */ -#define TWIC_TWIS_vect_num 12 -#define TWIC_TWIS_vect _VECTOR(12) /* TWI Slave Interrupt */ -#define TWIC_TWIM_vect_num 13 -#define TWIC_TWIM_vect _VECTOR(13) /* TWI Master Interrupt */ - -/* TCC0 interrupt vectors */ -#define TCC0_OVF_vect_num 14 -#define TCC0_OVF_vect _VECTOR(14) /* Overflow Interrupt */ - -/* TCC2 interrupt vectors */ -#define TCC2_LUNF_vect_num 14 -#define TCC2_LUNF_vect _VECTOR(14) /* Low Byte Underflow Interrupt */ - -/* TCC0 interrupt vectors */ -#define TCC0_ERR_vect_num 15 -#define TCC0_ERR_vect _VECTOR(15) /* Error Interrupt */ - -/* TCC2 interrupt vectors */ -#define TCC2_HUNF_vect_num 15 -#define TCC2_HUNF_vect _VECTOR(15) /* High Byte Underflow Interrupt */ - -/* TCC0 interrupt vectors */ -#define TCC0_CCA_vect_num 16 -#define TCC0_CCA_vect _VECTOR(16) /* Compare or Capture A Interrupt */ - -/* TCC2 interrupt vectors */ -#define TCC2_LCMPA_vect_num 16 -#define TCC2_LCMPA_vect _VECTOR(16) /* Low Byte Compare A Interrupt */ - -/* TCC0 interrupt vectors */ -#define TCC0_CCB_vect_num 17 -#define TCC0_CCB_vect _VECTOR(17) /* Compare or Capture B Interrupt */ - -/* TCC2 interrupt vectors */ -#define TCC2_LCMPB_vect_num 17 -#define TCC2_LCMPB_vect _VECTOR(17) /* Low Byte Compare B Interrupt */ - -/* TCC0 interrupt vectors */ -#define TCC0_CCC_vect_num 18 -#define TCC0_CCC_vect _VECTOR(18) /* Compare or Capture C Interrupt */ - -/* TCC2 interrupt vectors */ -#define TCC2_LCMPC_vect_num 18 -#define TCC2_LCMPC_vect _VECTOR(18) /* Low Byte Compare C Interrupt */ - -/* TCC0 interrupt vectors */ -#define TCC0_CCD_vect_num 19 -#define TCC0_CCD_vect _VECTOR(19) /* Compare or Capture D Interrupt */ - -/* TCC2 interrupt vectors */ -#define TCC2_LCMPD_vect_num 19 -#define TCC2_LCMPD_vect _VECTOR(19) /* Low Byte Compare D Interrupt */ - -/* TCC1 interrupt vectors */ -#define TCC1_OVF_vect_num 20 -#define TCC1_OVF_vect _VECTOR(20) /* Overflow Interrupt */ -#define TCC1_ERR_vect_num 21 -#define TCC1_ERR_vect _VECTOR(21) /* Error Interrupt */ -#define TCC1_CCA_vect_num 22 -#define TCC1_CCA_vect _VECTOR(22) /* Compare or Capture A Interrupt */ -#define TCC1_CCB_vect_num 23 -#define TCC1_CCB_vect _VECTOR(23) /* Compare or Capture B Interrupt */ - -/* SPIC interrupt vectors */ -#define SPIC_INT_vect_num 24 -#define SPIC_INT_vect _VECTOR(24) /* SPI Interrupt */ - -/* USARTC0 interrupt vectors */ -#define USARTC0_RXC_vect_num 25 -#define USARTC0_RXC_vect _VECTOR(25) /* Reception Complete Interrupt */ -#define USARTC0_DRE_vect_num 26 -#define USARTC0_DRE_vect _VECTOR(26) /* Data Register Empty Interrupt */ -#define USARTC0_TXC_vect_num 27 -#define USARTC0_TXC_vect _VECTOR(27) /* Transmission Complete Interrupt */ - -/* USARTC1 interrupt vectors */ -#define USARTC1_RXC_vect_num 28 -#define USARTC1_RXC_vect _VECTOR(28) /* Reception Complete Interrupt */ -#define USARTC1_DRE_vect_num 29 -#define USARTC1_DRE_vect _VECTOR(29) /* Data Register Empty Interrupt */ -#define USARTC1_TXC_vect_num 30 -#define USARTC1_TXC_vect _VECTOR(30) /* Transmission Complete Interrupt */ - -/* NVM interrupt vectors */ -#define NVM_EE_vect_num 32 -#define NVM_EE_vect _VECTOR(32) /* EE Interrupt */ -#define NVM_SPM_vect_num 33 -#define NVM_SPM_vect _VECTOR(33) /* SPM Interrupt */ - -/* PORTB interrupt vectors */ -#define PORTB_INT0_vect_num 34 -#define PORTB_INT0_vect _VECTOR(34) /* External Interrupt 0 */ -#define PORTB_INT1_vect_num 35 -#define PORTB_INT1_vect _VECTOR(35) /* External Interrupt 1 */ - -/* PORTE interrupt vectors */ -#define PORTE_INT0_vect_num 43 -#define PORTE_INT0_vect _VECTOR(43) /* External Interrupt 0 */ -#define PORTE_INT1_vect_num 44 -#define PORTE_INT1_vect _VECTOR(44) /* External Interrupt 1 */ - -/* TWIE interrupt vectors */ -#define TWIE_TWIS_vect_num 45 -#define TWIE_TWIS_vect _VECTOR(45) /* TWI Slave Interrupt */ -#define TWIE_TWIM_vect_num 46 -#define TWIE_TWIM_vect _VECTOR(46) /* TWI Master Interrupt */ - -/* TCE0 interrupt vectors */ -#define TCE0_OVF_vect_num 47 -#define TCE0_OVF_vect _VECTOR(47) /* Overflow Interrupt */ -#define TCE0_ERR_vect_num 48 -#define TCE0_ERR_vect _VECTOR(48) /* Error Interrupt */ -#define TCE0_CCA_vect_num 49 -#define TCE0_CCA_vect _VECTOR(49) /* Compare or Capture A Interrupt */ -#define TCE0_CCB_vect_num 50 -#define TCE0_CCB_vect _VECTOR(50) /* Compare or Capture B Interrupt */ -#define TCE0_CCC_vect_num 51 -#define TCE0_CCC_vect _VECTOR(51) /* Compare or Capture C Interrupt */ -#define TCE0_CCD_vect_num 52 -#define TCE0_CCD_vect _VECTOR(52) /* Compare or Capture D Interrupt */ - -/* PORTD interrupt vectors */ -#define PORTD_INT0_vect_num 64 -#define PORTD_INT0_vect _VECTOR(64) /* External Interrupt 0 */ -#define PORTD_INT1_vect_num 65 -#define PORTD_INT1_vect _VECTOR(65) /* External Interrupt 1 */ - -/* PORTA interrupt vectors */ -#define PORTA_INT0_vect_num 66 -#define PORTA_INT0_vect _VECTOR(66) /* External Interrupt 0 */ -#define PORTA_INT1_vect_num 67 -#define PORTA_INT1_vect _VECTOR(67) /* External Interrupt 1 */ - -/* ACA interrupt vectors */ -#define ACA_AC0_vect_num 68 -#define ACA_AC0_vect _VECTOR(68) /* AC0 Interrupt */ -#define ACA_AC1_vect_num 69 -#define ACA_AC1_vect _VECTOR(69) /* AC1 Interrupt */ -#define ACA_ACW_vect_num 70 -#define ACA_ACW_vect _VECTOR(70) /* ACW Window Mode Interrupt */ - -/* ADCA interrupt vectors */ -#define ADCA_CH0_vect_num 71 -#define ADCA_CH0_vect _VECTOR(71) /* Interrupt 0 */ - -/* TCD0 interrupt vectors */ -#define TCD0_OVF_vect_num 77 -#define TCD0_OVF_vect _VECTOR(77) /* Overflow Interrupt */ - -/* TCD2 interrupt vectors */ -#define TCD2_LUNF_vect_num 77 -#define TCD2_LUNF_vect _VECTOR(77) /* Low Byte Underflow Interrupt */ - -/* TCD0 interrupt vectors */ -#define TCD0_ERR_vect_num 78 -#define TCD0_ERR_vect _VECTOR(78) /* Error Interrupt */ - -/* TCD2 interrupt vectors */ -#define TCD2_HUNF_vect_num 78 -#define TCD2_HUNF_vect _VECTOR(78) /* High Byte Underflow Interrupt */ - -/* TCD0 interrupt vectors */ -#define TCD0_CCA_vect_num 79 -#define TCD0_CCA_vect _VECTOR(79) /* Compare or Capture A Interrupt */ - -/* TCD2 interrupt vectors */ -#define TCD2_LCMPA_vect_num 79 -#define TCD2_LCMPA_vect _VECTOR(79) /* Low Byte Compare A Interrupt */ - -/* TCD0 interrupt vectors */ -#define TCD0_CCB_vect_num 80 -#define TCD0_CCB_vect _VECTOR(80) /* Compare or Capture B Interrupt */ - -/* TCD2 interrupt vectors */ -#define TCD2_LCMPB_vect_num 80 -#define TCD2_LCMPB_vect _VECTOR(80) /* Low Byte Compare B Interrupt */ - -/* TCD0 interrupt vectors */ -#define TCD0_CCC_vect_num 81 -#define TCD0_CCC_vect _VECTOR(81) /* Compare or Capture C Interrupt */ - -/* TCD2 interrupt vectors */ -#define TCD2_LCMPC_vect_num 81 -#define TCD2_LCMPC_vect _VECTOR(81) /* Low Byte Compare C Interrupt */ - -/* TCD0 interrupt vectors */ -#define TCD0_CCD_vect_num 82 -#define TCD0_CCD_vect _VECTOR(82) /* Compare or Capture D Interrupt */ - -/* TCD2 interrupt vectors */ -#define TCD2_LCMPD_vect_num 82 -#define TCD2_LCMPD_vect _VECTOR(82) /* Low Byte Compare D Interrupt */ - -/* SPID interrupt vectors */ -#define SPID_INT_vect_num 87 -#define SPID_INT_vect _VECTOR(87) /* SPI Interrupt */ - -/* USARTD0 interrupt vectors */ -#define USARTD0_RXC_vect_num 88 -#define USARTD0_RXC_vect _VECTOR(88) /* Reception Complete Interrupt */ -#define USARTD0_DRE_vect_num 89 -#define USARTD0_DRE_vect _VECTOR(89) /* Data Register Empty Interrupt */ -#define USARTD0_TXC_vect_num 90 -#define USARTD0_TXC_vect _VECTOR(90) /* Transmission Complete Interrupt */ - -/* USB interrupt vectors */ -#define USB_BUSEVENT_vect_num 125 -#define USB_BUSEVENT_vect _VECTOR(125) /* SOF, suspend, resume, reset bus event interrupts, crc, underflow, overflow and stall error interrupts */ -#define USB_TRNCOMPL_vect_num 126 -#define USB_TRNCOMPL_vect _VECTOR(126) /* Transaction complete interrupt */ - -#define _VECTOR_SIZE 4 /* Size of individual vector. */ -#define _VECTORS_SIZE (127 * _VECTOR_SIZE) - - -/* ========== Constants ========== */ - -#define PROGMEM_START (0x0000) -#define PROGMEM_SIZE (20480) -#define PROGMEM_END (PROGMEM_START + PROGMEM_SIZE - 1) - -#define APP_SECTION_START (0x0000) -#define APP_SECTION_SIZE (16384) -#define APP_SECTION_PAGE_SIZE (256) -#define APP_SECTION_END (APP_SECTION_START + APP_SECTION_SIZE - 1) - -#define APPTABLE_SECTION_START (0x3000) -#define APPTABLE_SECTION_SIZE (4096) -#define APPTABLE_SECTION_PAGE_SIZE (256) -#define APPTABLE_SECTION_END (APPTABLE_SECTION_START + APPTABLE_SECTION_SIZE - 1) - -#define BOOT_SECTION_START (0x4000) -#define BOOT_SECTION_SIZE (4096) -#define BOOT_SECTION_PAGE_SIZE (256) -#define BOOT_SECTION_END (BOOT_SECTION_START + BOOT_SECTION_SIZE - 1) - -#define DATAMEM_START (0x0000) -#define DATAMEM_SIZE (10240) -#define DATAMEM_END (DATAMEM_START + DATAMEM_SIZE - 1) - -#define IO_START (0x0000) -#define IO_SIZE (4096) -#define IO_PAGE_SIZE (0) -#define IO_END (IO_START + IO_SIZE - 1) - -#define MAPPED_EEPROM_START (0x1000) -#define MAPPED_EEPROM_SIZE (1024) -#define MAPPED_EEPROM_PAGE_SIZE (0) -#define MAPPED_EEPROM_END (MAPPED_EEPROM_START + MAPPED_EEPROM_SIZE - 1) - -#define INTERNAL_SRAM_START (0x2000) -#define INTERNAL_SRAM_SIZE (2048) -#define INTERNAL_SRAM_PAGE_SIZE (0) -#define INTERNAL_SRAM_END (INTERNAL_SRAM_START + INTERNAL_SRAM_SIZE - 1) - -#define EEPROM_START (0x0000) -#define EEPROM_SIZE (1024) -#define EEPROM_PAGE_SIZE (32) -#define EEPROM_END (EEPROM_START + EEPROM_SIZE - 1) - -#define SIGNATURES_START (0x0000) -#define SIGNATURES_SIZE (3) -#define SIGNATURES_PAGE_SIZE (0) -#define SIGNATURES_END (SIGNATURES_START + SIGNATURES_SIZE - 1) - -#define FUSES_START (0x0000) -#define FUSES_SIZE (6) -#define FUSES_PAGE_SIZE (0) -#define FUSES_END (FUSES_START + FUSES_SIZE - 1) - -#define LOCKBITS_START (0x0000) -#define LOCKBITS_SIZE (1) -#define LOCKBITS_PAGE_SIZE (0) -#define LOCKBITS_END (LOCKBITS_START + LOCKBITS_SIZE - 1) - -#define USER_SIGNATURES_START (0x0000) -#define USER_SIGNATURES_SIZE (256) -#define USER_SIGNATURES_PAGE_SIZE (256) -#define USER_SIGNATURES_END (USER_SIGNATURES_START + USER_SIGNATURES_SIZE - 1) - -#define PROD_SIGNATURES_START (0x0000) -#define PROD_SIGNATURES_SIZE (64) -#define PROD_SIGNATURES_PAGE_SIZE (256) -#define PROD_SIGNATURES_END (PROD_SIGNATURES_START + PROD_SIGNATURES_SIZE - 1) - -#define FLASHSTART PROGMEM_START -#define FLASHEND PROGMEM_END -#define SPM_PAGESIZE 256 -#define RAMSTART INTERNAL_SRAM_START -#define RAMSIZE INTERNAL_SRAM_SIZE -#define RAMEND INTERNAL_SRAM_END -#define E2END EEPROM_END -#define E2PAGESIZE EEPROM_PAGE_SIZE - - -/* ========== Fuses ========== */ -#define FUSE_MEMORY_SIZE 6 - -/* Fuse Byte 0 Reserved */ - -/* Fuse Byte 1 */ -#define FUSE_WDP0 (unsigned char)~_BV(0) /* Watchdog Timeout Period Bit 0 */ -#define FUSE_WDP1 (unsigned char)~_BV(1) /* Watchdog Timeout Period Bit 1 */ -#define FUSE_WDP2 (unsigned char)~_BV(2) /* Watchdog Timeout Period Bit 2 */ -#define FUSE_WDP3 (unsigned char)~_BV(3) /* Watchdog Timeout Period Bit 3 */ -#define FUSE_WDWP0 (unsigned char)~_BV(4) /* Watchdog Window Timeout Period Bit 0 */ -#define FUSE_WDWP1 (unsigned char)~_BV(5) /* Watchdog Window Timeout Period Bit 1 */ -#define FUSE_WDWP2 (unsigned char)~_BV(6) /* Watchdog Window Timeout Period Bit 2 */ -#define FUSE_WDWP3 (unsigned char)~_BV(7) /* Watchdog Window Timeout Period Bit 3 */ -#define FUSE1_DEFAULT (0xFF) - -/* Fuse Byte 2 */ -#define FUSE_BODPD0 (unsigned char)~_BV(0) /* BOD Operation in Power-Down Mode Bit 0 */ -#define FUSE_BODPD1 (unsigned char)~_BV(1) /* BOD Operation in Power-Down Mode Bit 1 */ -#define FUSE_TOSCSEL (unsigned char)~_BV(5) /* Timer Oscillator pin location */ -#define FUSE_BOOTRST (unsigned char)~_BV(6) /* Boot Loader Section Reset Vector */ -#define FUSE2_DEFAULT (0xFF) - -/* Fuse Byte 3 Reserved */ - -/* Fuse Byte 4 */ -#define FUSE_WDLOCK (unsigned char)~_BV(1) /* Watchdog Timer Lock */ -#define FUSE_SUT0 (unsigned char)~_BV(2) /* Start-up Time Bit 0 */ -#define FUSE_SUT1 (unsigned char)~_BV(3) /* Start-up Time Bit 1 */ -#define FUSE_RSTDISBL (unsigned char)~_BV(4) /* External Reset Disable */ -#define FUSE4_DEFAULT (0xFF) - -/* Fuse Byte 5 */ -#define FUSE_BODLVL0 (unsigned char)~_BV(0) /* Brownout Detection Voltage Level Bit 0 */ -#define FUSE_BODLVL1 (unsigned char)~_BV(1) /* Brownout Detection Voltage Level Bit 1 */ -#define FUSE_BODLVL2 (unsigned char)~_BV(2) /* Brownout Detection Voltage Level Bit 2 */ -#define FUSE_EESAVE (unsigned char)~_BV(3) /* Preserve EEPROM Through Chip Erase */ -#define FUSE_BODACT0 (unsigned char)~_BV(4) /* BOD Operation in Active Mode Bit 0 */ -#define FUSE_BODACT1 (unsigned char)~_BV(5) /* BOD Operation in Active Mode Bit 1 */ -#define FUSE5_DEFAULT (0xFF) - -/* ========== Lock Bits ========== */ -#define __LOCK_BITS_EXIST -#define __BOOT_LOCK_APPLICATION_TABLE_BITS_EXIST -#define __BOOT_LOCK_APPLICATION_BITS_EXIST -#define __BOOT_LOCK_BOOT_BITS_EXIST - -/* ========== Signature ========== */ -#define SIGNATURE_0 0x1E -#define SIGNATURE_1 0x94 -#define SIGNATURE_2 0x43 - -/* ========== Power Reduction Condition Definitions ========== */ - -/* PR.PRGEN */ -#define __AVR_HAVE_PRGEN (PR_USB_bm|PR_AES_bm|PR_RTC_bm|PR_EVSYS_bm|PR_DMA_bm) -#define __AVR_HAVE_PRGEN_USB -#define __AVR_HAVE_PRGEN_AES -#define __AVR_HAVE_PRGEN_RTC -#define __AVR_HAVE_PRGEN_EVSYS -#define __AVR_HAVE_PRGEN_DMA - -/* PR.PRPA */ -#define __AVR_HAVE_PRPA (PR_ADC_bm|PR_AC_bm) -#define __AVR_HAVE_PRPA_ADC -#define __AVR_HAVE_PRPA_AC - -/* PR.PRPC */ -#define __AVR_HAVE_PRPC (PR_TWI_bm|PR_USART1_bm|PR_USART0_bm|PR_SPI_bm|PR_HIRES_bm|PR_TC1_bm|PR_TC0_bm) -#define __AVR_HAVE_PRPC_TWI -#define __AVR_HAVE_PRPC_USART1 -#define __AVR_HAVE_PRPC_USART0 -#define __AVR_HAVE_PRPC_SPI -#define __AVR_HAVE_PRPC_HIRES -#define __AVR_HAVE_PRPC_TC1 -#define __AVR_HAVE_PRPC_TC0 - -/* PR.PRPD */ -#define __AVR_HAVE_PRPD (PR_USART0_bm|PR_SPI_bm|PR_TC0_bm) -#define __AVR_HAVE_PRPD_USART0 -#define __AVR_HAVE_PRPD_SPI -#define __AVR_HAVE_PRPD_TC0 - -/* PR.PRPE */ -#define __AVR_HAVE_PRPE (PR_TWI_bm|PR_USART0_bm|PR_TC0_bm) -#define __AVR_HAVE_PRPE_TWI -#define __AVR_HAVE_PRPE_USART0 -#define __AVR_HAVE_PRPE_TC0 - -/* PR.PRPF */ -#define __AVR_HAVE_PRPF (PR_USART0_bm|PR_TC0_bm) -#define __AVR_HAVE_PRPF_USART0 -#define __AVR_HAVE_PRPF_TC0 - - -#endif /* #ifdef _AVR_ATXMEGA16C4_H_INCLUDED */ - diff --git a/arduino/hardware/tools/avr/avr/include/avr/iox16d4.h b/arduino/hardware/tools/avr/avr/include/avr/iox16d4.h deleted file mode 100644 index 5aa0ef9..0000000 --- a/arduino/hardware/tools/avr/avr/include/avr/iox16d4.h +++ /dev/null @@ -1,5717 +0,0 @@ -/* Copyright (c) 2009-2010 Atmel Corporation - All rights reserved. - - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - * Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - * Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in - the documentation and/or other materials provided with the - distribution. - - * Neither the name of the copyright holders nor the names of - contributors may be used to endorse or promote products derived - from this software without specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. */ - -/* $Id: iox16d4.h 2200 2010-12-14 04:24:24Z arcanum $ */ - -/* avr/iox16d4.h - definitions for ATxmega16D4 */ - -/* This file should only be included from , never directly. */ - -#ifndef _AVR_IO_H_ -# error "Include instead of this file." -#endif - -#ifndef _AVR_IOXXX_H_ -# define _AVR_IOXXX_H_ "iox16d4.h" -#else -# error "Attempt to include more than one file." -#endif - - -#ifndef _AVR_ATxmega16D4_H_ -#define _AVR_ATxmega16D4_H_ 1 - - -/* Ungrouped common registers */ -#define GPIOR0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ -#define GPIOR1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ -#define GPIOR2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ -#define GPIOR3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ -#define GPIOR4 _SFR_MEM8(0x0004) /* General Purpose IO Register 4 */ -#define GPIOR5 _SFR_MEM8(0x0005) /* General Purpose IO Register 5 */ -#define GPIOR6 _SFR_MEM8(0x0006) /* General Purpose IO Register 6 */ -#define GPIOR7 _SFR_MEM8(0x0007) /* General Purpose IO Register 7 */ -#define GPIOR8 _SFR_MEM8(0x0008) /* General Purpose IO Register 8 */ -#define GPIOR9 _SFR_MEM8(0x0009) /* General Purpose IO Register 9 */ -#define GPIORA _SFR_MEM8(0x000A) /* General Purpose IO Register 10 */ -#define GPIORB _SFR_MEM8(0x000B) /* General Purpose IO Register 11 */ -#define GPIORC _SFR_MEM8(0x000C) /* General Purpose IO Register 12 */ -#define GPIORD _SFR_MEM8(0x000D) /* General Purpose IO Register 13 */ -#define GPIORE _SFR_MEM8(0x000E) /* General Purpose IO Register 14 */ -#define GPIORF _SFR_MEM8(0x000F) /* General Purpose IO Register 15 */ - -/* Deprecated */ -#define GPIO0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ -#define GPIO1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ -#define GPIO2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ -#define GPIO3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ -#define GPIO4 _SFR_MEM8(0x0004) /* General Purpose IO Register 4 */ -#define GPIO5 _SFR_MEM8(0x0005) /* General Purpose IO Register 5 */ -#define GPIO6 _SFR_MEM8(0x0006) /* General Purpose IO Register 6 */ -#define GPIO7 _SFR_MEM8(0x0007) /* General Purpose IO Register 7 */ -#define GPIO8 _SFR_MEM8(0x0008) /* General Purpose IO Register 8 */ -#define GPIO9 _SFR_MEM8(0x0009) /* General Purpose IO Register 9 */ -#define GPIOA _SFR_MEM8(0x000A) /* General Purpose IO Register 10 */ -#define GPIOB _SFR_MEM8(0x000B) /* General Purpose IO Register 11 */ -#define GPIOC _SFR_MEM8(0x000C) /* General Purpose IO Register 12 */ -#define GPIOD _SFR_MEM8(0x000D) /* General Purpose IO Register 13 */ -#define GPIOE _SFR_MEM8(0x000E) /* General Purpose IO Register 14 */ -#define GPIOF _SFR_MEM8(0x000F) /* General Purpose IO Register 15 */ - -#define CCP _SFR_MEM8(0x0034) /* Configuration Change Protection */ -#define RAMPD _SFR_MEM8(0x0038) /* Ramp D */ -#define RAMPX _SFR_MEM8(0x0039) /* Ramp X */ -#define RAMPY _SFR_MEM8(0x003A) /* Ramp Y */ -#define RAMPZ _SFR_MEM8(0x003B) /* Ramp Z */ -#define EIND _SFR_MEM8(0x003C) /* Extended Indirect Jump */ -#define SPL _SFR_MEM8(0x003D) /* Stack Pointer Low */ -#define SPH _SFR_MEM8(0x003E) /* Stack Pointer High */ -#define SREG _SFR_MEM8(0x003F) /* Status Register */ - - -/* C Language Only */ -#if !defined (__ASSEMBLER__) - -#include - -typedef volatile uint8_t register8_t; -typedef volatile uint16_t register16_t; -typedef volatile uint32_t register32_t; - - -#ifdef _WORDREGISTER -#undef _WORDREGISTER -#endif -#define _WORDREGISTER(regname) \ - __extension__ union \ - { \ - register16_t regname; \ - struct \ - { \ - register8_t regname ## L; \ - register8_t regname ## H; \ - }; \ - } - -#ifdef _DWORDREGISTER -#undef _DWORDREGISTER -#endif -#define _DWORDREGISTER(regname) \ - __extension__ union \ - { \ - register32_t regname; \ - struct \ - { \ - register8_t regname ## 0; \ - register8_t regname ## 1; \ - register8_t regname ## 2; \ - register8_t regname ## 3; \ - }; \ - } - - -/* -========================================================================== -IO Module Structures -========================================================================== -*/ - - -/* --------------------------------------------------------------------------- -XOCD - On-Chip Debug System --------------------------------------------------------------------------- -*/ - -/* On-Chip Debug System */ -typedef struct OCD_struct -{ - register8_t OCDR0; /* OCD Register 0 */ - register8_t OCDR1; /* OCD Register 1 */ -} OCD_t; - - -/* CCP signatures */ -typedef enum CCP_enum -{ - CCP_SPM_gc = (0x9D<<0), /* SPM Instruction Protection */ - CCP_IOREG_gc = (0xD8<<0), /* IO Register Protection */ -} CCP_t; - - -/* --------------------------------------------------------------------------- -CLK - Clock System --------------------------------------------------------------------------- -*/ - -/* Clock System */ -typedef struct CLK_struct -{ - register8_t CTRL; /* Control Register */ - register8_t PSCTRL; /* Prescaler Control Register */ - register8_t LOCK; /* Lock register */ - register8_t RTCCTRL; /* RTC Control Register */ -} CLK_t; - -/* --------------------------------------------------------------------------- -CLK - Clock System --------------------------------------------------------------------------- -*/ - -/* Power Reduction */ -typedef struct PR_struct -{ - register8_t PRGEN; /* General Power Reduction */ - register8_t PRPA; /* Power Reduction Port A */ - register8_t PRPB; /* Power Reduction Port B */ - register8_t PRPC; /* Power Reduction Port C */ - register8_t PRPD; /* Power Reduction Port D */ - register8_t PRPE; /* Power Reduction Port E */ - register8_t PRPF; /* Power Reduction Port F */ -} PR_t; - -/* System Clock Selection */ -typedef enum CLK_SCLKSEL_enum -{ - CLK_SCLKSEL_RC2M_gc = (0x00<<0), /* Internal 2MHz RC Oscillator */ - CLK_SCLKSEL_RC32M_gc = (0x01<<0), /* Internal 32MHz RC Oscillator */ - CLK_SCLKSEL_RC32K_gc = (0x02<<0), /* Internal 32kHz RC Oscillator */ - CLK_SCLKSEL_XOSC_gc = (0x03<<0), /* External Crystal Oscillator or Clock */ - CLK_SCLKSEL_PLL_gc = (0x04<<0), /* Phase Locked Loop */ -} CLK_SCLKSEL_t; - -/* Prescaler A Division Factor */ -typedef enum CLK_PSADIV_enum -{ - CLK_PSADIV_1_gc = (0x00<<2), /* Divide by 1 */ - CLK_PSADIV_2_gc = (0x01<<2), /* Divide by 2 */ - CLK_PSADIV_4_gc = (0x03<<2), /* Divide by 4 */ - CLK_PSADIV_8_gc = (0x05<<2), /* Divide by 8 */ - CLK_PSADIV_16_gc = (0x07<<2), /* Divide by 16 */ - CLK_PSADIV_32_gc = (0x09<<2), /* Divide by 32 */ - CLK_PSADIV_64_gc = (0x0B<<2), /* Divide by 64 */ - CLK_PSADIV_128_gc = (0x0D<<2), /* Divide by 128 */ - CLK_PSADIV_256_gc = (0x0F<<2), /* Divide by 256 */ - CLK_PSADIV_512_gc = (0x11<<2), /* Divide by 512 */ -} CLK_PSADIV_t; - -/* Prescaler B and C Division Factor */ -typedef enum CLK_PSBCDIV_enum -{ - CLK_PSBCDIV_1_1_gc = (0x00<<0), /* Divide B by 1 and C by 1 */ - CLK_PSBCDIV_1_2_gc = (0x01<<0), /* Divide B by 1 and C by 2 */ - CLK_PSBCDIV_4_1_gc = (0x02<<0), /* Divide B by 4 and C by 1 */ - CLK_PSBCDIV_2_2_gc = (0x03<<0), /* Divide B by 2 and C by 2 */ -} CLK_PSBCDIV_t; - -/* RTC Clock Source */ -typedef enum CLK_RTCSRC_enum -{ - CLK_RTCSRC_ULP_gc = (0x00<<1), /* 1kHz from internal 32kHz ULP */ - CLK_RTCSRC_TOSC_gc = (0x01<<1), /* 1kHz from 32kHz crystal oscillator on TOSC */ - CLK_RTCSRC_RCOSC_gc = (0x02<<1), /* 1kHz from internal 32kHz RC oscillator */ - CLK_RTCSRC_TOSC32_gc = (0x05<<1), /* 32kHz from 32kHz crystal oscillator on TOSC */ -} CLK_RTCSRC_t; - - -/* --------------------------------------------------------------------------- -SLEEP - Sleep Controller --------------------------------------------------------------------------- -*/ - -/* Sleep Controller */ -typedef struct SLEEP_struct -{ - register8_t CTRL; /* Control Register */ -} SLEEP_t; - -/* Sleep Mode */ -typedef enum SLEEP_SMODE_enum -{ - SLEEP_SMODE_IDLE_gc = (0x00<<1), /* Idle mode */ - SLEEP_SMODE_PDOWN_gc = (0x02<<1), /* Power-down Mode */ - SLEEP_SMODE_PSAVE_gc = (0x03<<1), /* Power-save Mode */ - SLEEP_SMODE_STDBY_gc = (0x06<<1), /* Standby Mode */ - SLEEP_SMODE_ESTDBY_gc = (0x07<<1), /* Extended Standby Mode */ -} SLEEP_SMODE_t; - -#define SLEEP_MODE_IDLE (0x00<<1) -#define SLEEP_MODE_PWR_DOWN (0x02<<1) -#define SLEEP_MODE_PWR_SAVE (0x03<<1) -#define SLEEP_MODE_STANDBY (0x06<<1) -#define SLEEP_MODE_EXT_STANDBY (0x07<<1) - - -/* --------------------------------------------------------------------------- -OSC - Oscillator --------------------------------------------------------------------------- -*/ - -/* Oscillator */ -typedef struct OSC_struct -{ - register8_t CTRL; /* Control Register */ - register8_t STATUS; /* Status Register */ - register8_t XOSCCTRL; /* External Oscillator Control Register */ - register8_t XOSCFAIL; /* External Oscillator Failure Detection Register */ - register8_t RC32KCAL; /* 32kHz Internal Oscillator Calibration Register */ - register8_t PLLCTRL; /* PLL Control REgister */ - register8_t DFLLCTRL; /* DFLL Control Register */ -} OSC_t; - -/* Oscillator Frequency Range */ -typedef enum OSC_FRQRANGE_enum -{ - OSC_FRQRANGE_04TO2_gc = (0x00<<6), /* 0.4 - 2 MHz */ - OSC_FRQRANGE_2TO9_gc = (0x01<<6), /* 2 - 9 MHz */ - OSC_FRQRANGE_9TO12_gc = (0x02<<6), /* 9 - 12 MHz */ - OSC_FRQRANGE_12TO16_gc = (0x03<<6), /* 12 - 16 MHz */ -} OSC_FRQRANGE_t; - -/* External Oscillator Selection and Startup Time */ -typedef enum OSC_XOSCSEL_enum -{ - OSC_XOSCSEL_EXTCLK_gc = (0x00<<0), /* External Clock - 6 CLK */ - OSC_XOSCSEL_32KHz_gc = (0x02<<0), /* 32kHz TOSC - 32K CLK */ - OSC_XOSCSEL_XTAL_256CLK_gc = (0x03<<0), /* 0.4-16MHz XTAL - 256 CLK */ - OSC_XOSCSEL_XTAL_1KCLK_gc = (0x07<<0), /* 0.4-16MHz XTAL - 1K CLK */ - OSC_XOSCSEL_XTAL_16KCLK_gc = (0x0B<<0), /* 0.4-16MHz XTAL - 16K CLK */ -} OSC_XOSCSEL_t; - -/* PLL Clock Source */ -typedef enum OSC_PLLSRC_enum -{ - OSC_PLLSRC_RC2M_gc = (0x00<<6), /* Internal 2MHz RC Oscillator */ - OSC_PLLSRC_RC32M_gc = (0x02<<6), /* Internal 32MHz RC Oscillator */ - OSC_PLLSRC_XOSC_gc = (0x03<<6), /* External Oscillator */ -} OSC_PLLSRC_t; - - -/* --------------------------------------------------------------------------- -DFLL - DFLL --------------------------------------------------------------------------- -*/ - -/* DFLL */ -typedef struct DFLL_struct -{ - register8_t CTRL; /* Control Register */ - register8_t reserved_0x01; - register8_t CALA; /* Calibration Register A */ - register8_t CALB; /* Calibration Register B */ - register8_t COMP0; /* Oscillator Compare Register 0 */ - register8_t COMP1; /* Oscillator Compare Register 1 */ - register8_t COMP2; /* Oscillator Compare Register 2 */ - register8_t reserved_0x07; -} DFLL_t; - - -/* --------------------------------------------------------------------------- -RST - Reset --------------------------------------------------------------------------- -*/ - -/* Reset */ -typedef struct RST_struct -{ - register8_t STATUS; /* Status Register */ - register8_t CTRL; /* Control Register */ -} RST_t; - - -/* --------------------------------------------------------------------------- -WDT - Watch-Dog Timer --------------------------------------------------------------------------- -*/ - -/* Watch-Dog Timer */ -typedef struct WDT_struct -{ - register8_t CTRL; /* Control */ - register8_t WINCTRL; /* Windowed Mode Control */ - register8_t STATUS; /* Status */ -} WDT_t; - -/* Period setting */ -typedef enum WDT_PER_enum -{ - WDT_PER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ - WDT_PER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ - WDT_PER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ - WDT_PER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ - WDT_PER_128CLK_gc = (0x04<<2), /* 128 cycles (0.125s @ 3.3V) */ - WDT_PER_256CLK_gc = (0x05<<2), /* 256 cycles (0.25s @ 3.3V) */ - WDT_PER_512CLK_gc = (0x06<<2), /* 512 cycles (0.5s @ 3.3V) */ - WDT_PER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ - WDT_PER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ - WDT_PER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ - WDT_PER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ -} WDT_PER_t; - -/* Closed window period */ -typedef enum WDT_WPER_enum -{ - WDT_WPER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ - WDT_WPER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ - WDT_WPER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ - WDT_WPER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ - WDT_WPER_128CLK_gc = (0x04<<2), /* 128 cycles (0.125s @ 3.3V) */ - WDT_WPER_256CLK_gc = (0x05<<2), /* 256 cycles (0.25s @ 3.3V) */ - WDT_WPER_512CLK_gc = (0x06<<2), /* 512 cycles (0.5s @ 3.3V) */ - WDT_WPER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ - WDT_WPER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ - WDT_WPER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ - WDT_WPER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ -} WDT_WPER_t; - - -/* --------------------------------------------------------------------------- -MCU - MCU Control --------------------------------------------------------------------------- -*/ - -/* MCU Control */ -typedef struct MCU_struct -{ - register8_t DEVID0; /* Device ID byte 0 */ - register8_t DEVID1; /* Device ID byte 1 */ - register8_t DEVID2; /* Device ID byte 2 */ - register8_t REVID; /* Revision ID */ - register8_t JTAGUID; /* JTAG User ID */ - register8_t reserved_0x05; - register8_t MCUCR; /* MCU Control */ - register8_t reserved_0x07; - register8_t EVSYSLOCK; /* Event System Lock */ - register8_t AWEXLOCK; /* AWEX Lock */ - register8_t reserved_0x0A; - register8_t reserved_0x0B; -} MCU_t; - - -/* --------------------------------------------------------------------------- -PMIC - Programmable Multi-level Interrupt Controller --------------------------------------------------------------------------- -*/ - -/* Programmable Multi-level Interrupt Controller */ -typedef struct PMIC_struct -{ - register8_t STATUS; /* Status Register */ - register8_t INTPRI; /* Interrupt Priority */ - register8_t CTRL; /* Control Register */ -} PMIC_t; - - -/* --------------------------------------------------------------------------- -CRC - Cyclic Redundancy Checker --------------------------------------------------------------------------- -*/ - -/* Cyclic Redundancy Checker */ -typedef struct CRC_struct -{ - register8_t CTRL; /* Control Register */ - register8_t STATUS; /* Status Register */ - register8_t reserved_0x02; - register8_t DATAIN; /* Data Input */ - register8_t CHECKSUM0; /* Checksum byte 0 */ - register8_t CHECKSUM1; /* Checksum byte 1 */ - register8_t CHECKSUM2; /* Checksum byte 2 */ - register8_t CHECKSUM3; /* Checksum byte 3 */ -} CRC_t; - -/* Reset */ -typedef enum CRC_RESET_enum -{ - CRC_RESET_NO_gc = (0x00<<6), /* No Reset */ - CRC_RESET_RESET0_gc = (0x02<<6), /* Reset CRC with CHECKSUM to all zeros */ - CRC_RESET_RESET1_gc = (0x03<<6), /* Reset CRC with CHECKSUM to all ones */ -} CRC_RESET_t; - -/* Input Source */ -typedef enum CRC_SOURCE_enum -{ - CRC_SOURCE_DISABLE_gc = (0x00<<0), /* Disabled */ - CRC_SOURCE_IO_gc = (0x01<<0), /* I/O Interface */ - CRC_SOURCE_FLASH_gc = (0x02<<0), /* Flash */ -} CRC_SOURCE_t; - - -/* --------------------------------------------------------------------------- -EVSYS - Event System --------------------------------------------------------------------------- -*/ - -/* Event System */ -typedef struct EVSYS_struct -{ - register8_t CH0MUX; /* Event Channel 0 Multiplexer */ - register8_t CH1MUX; /* Event Channel 1 Multiplexer */ - register8_t CH2MUX; /* Event Channel 2 Multiplexer */ - register8_t CH3MUX; /* Event Channel 3 Multiplexer */ - register8_t reserved_0x04; - register8_t reserved_0x05; - register8_t reserved_0x06; - register8_t reserved_0x07; - register8_t CH0CTRL; /* Channel 0 Control Register */ - register8_t CH1CTRL; /* Channel 1 Control Register */ - register8_t CH2CTRL; /* Channel 2 Control Register */ - register8_t CH3CTRL; /* Channel 3 Control Register */ - register8_t reserved_0x0C; - register8_t reserved_0x0D; - register8_t reserved_0x0E; - register8_t reserved_0x0F; - register8_t STROBE; /* Event Strobe */ - register8_t DATA; /* Event Data */ -} EVSYS_t; - -/* Quadrature Decoder Index Recognition Mode */ -typedef enum EVSYS_QDIRM_enum -{ - EVSYS_QDIRM_00_gc = (0x00<<5), /* QDPH0 = 0, QDPH90 = 0 */ - EVSYS_QDIRM_01_gc = (0x01<<5), /* QDPH0 = 0, QDPH90 = 1 */ - EVSYS_QDIRM_10_gc = (0x02<<5), /* QDPH0 = 1, QDPH90 = 0 */ - EVSYS_QDIRM_11_gc = (0x03<<5), /* QDPH0 = 1, QDPH90 = 1 */ -} EVSYS_QDIRM_t; - -/* Digital filter coefficient */ -typedef enum EVSYS_DIGFILT_enum -{ - EVSYS_DIGFILT_1SAMPLE_gc = (0x00<<0), /* 1 SAMPLE */ - EVSYS_DIGFILT_2SAMPLES_gc = (0x01<<0), /* 2 SAMPLES */ - EVSYS_DIGFILT_3SAMPLES_gc = (0x02<<0), /* 3 SAMPLES */ - EVSYS_DIGFILT_4SAMPLES_gc = (0x03<<0), /* 4 SAMPLES */ - EVSYS_DIGFILT_5SAMPLES_gc = (0x04<<0), /* 5 SAMPLES */ - EVSYS_DIGFILT_6SAMPLES_gc = (0x05<<0), /* 6 SAMPLES */ - EVSYS_DIGFILT_7SAMPLES_gc = (0x06<<0), /* 7 SAMPLES */ - EVSYS_DIGFILT_8SAMPLES_gc = (0x07<<0), /* 8 SAMPLES */ -} EVSYS_DIGFILT_t; - -/* Event Channel multiplexer input selection */ -typedef enum EVSYS_CHMUX_enum -{ - EVSYS_CHMUX_OFF_gc = (0x00<<0), /* Off */ - EVSYS_CHMUX_RTC_OVF_gc = (0x08<<0), /* RTC Overflow */ - EVSYS_CHMUX_RTC_CMP_gc = (0x09<<0), /* RTC Compare Match */ - EVSYS_CHMUX_ACA_CH0_gc = (0x10<<0), /* Analog Comparator A Channel 0 */ - EVSYS_CHMUX_ACA_CH1_gc = (0x11<<0), /* Analog Comparator A Channel 1 */ - EVSYS_CHMUX_ACA_WIN_gc = (0x12<<0), /* Analog Comparator A Window */ - EVSYS_CHMUX_ADCA_CH0_gc = (0x20<<0), /* ADC A Channel 0 */ - EVSYS_CHMUX_PORTA_PIN0_gc = (0x50<<0), /* Port A, Pin0 */ - EVSYS_CHMUX_PORTA_PIN1_gc = (0x51<<0), /* Port A, Pin1 */ - EVSYS_CHMUX_PORTA_PIN2_gc = (0x52<<0), /* Port A, Pin2 */ - EVSYS_CHMUX_PORTA_PIN3_gc = (0x53<<0), /* Port A, Pin3 */ - EVSYS_CHMUX_PORTA_PIN4_gc = (0x54<<0), /* Port A, Pin4 */ - EVSYS_CHMUX_PORTA_PIN5_gc = (0x55<<0), /* Port A, Pin5 */ - EVSYS_CHMUX_PORTA_PIN6_gc = (0x56<<0), /* Port A, Pin6 */ - EVSYS_CHMUX_PORTA_PIN7_gc = (0x57<<0), /* Port A, Pin7 */ - EVSYS_CHMUX_PORTB_PIN0_gc = (0x58<<0), /* Port B, Pin0 */ - EVSYS_CHMUX_PORTB_PIN1_gc = (0x59<<0), /* Port B, Pin1 */ - EVSYS_CHMUX_PORTB_PIN2_gc = (0x5A<<0), /* Port B, Pin2 */ - EVSYS_CHMUX_PORTB_PIN3_gc = (0x5B<<0), /* Port B, Pin3 */ - EVSYS_CHMUX_PORTB_PIN4_gc = (0x5C<<0), /* Port B, Pin4 */ - EVSYS_CHMUX_PORTB_PIN5_gc = (0x5D<<0), /* Port B, Pin5 */ - EVSYS_CHMUX_PORTB_PIN6_gc = (0x5E<<0), /* Port B, Pin6 */ - EVSYS_CHMUX_PORTB_PIN7_gc = (0x5F<<0), /* Port B, Pin7 */ - EVSYS_CHMUX_PORTC_PIN0_gc = (0x60<<0), /* Port C, Pin0 */ - EVSYS_CHMUX_PORTC_PIN1_gc = (0x61<<0), /* Port C, Pin1 */ - EVSYS_CHMUX_PORTC_PIN2_gc = (0x62<<0), /* Port C, Pin2 */ - EVSYS_CHMUX_PORTC_PIN3_gc = (0x63<<0), /* Port C, Pin3 */ - EVSYS_CHMUX_PORTC_PIN4_gc = (0x64<<0), /* Port C, Pin4 */ - EVSYS_CHMUX_PORTC_PIN5_gc = (0x65<<0), /* Port C, Pin5 */ - EVSYS_CHMUX_PORTC_PIN6_gc = (0x66<<0), /* Port C, Pin6 */ - EVSYS_CHMUX_PORTC_PIN7_gc = (0x67<<0), /* Port C, Pin7 */ - EVSYS_CHMUX_PORTD_PIN0_gc = (0x68<<0), /* Port D, Pin0 */ - EVSYS_CHMUX_PORTD_PIN1_gc = (0x69<<0), /* Port D, Pin1 */ - EVSYS_CHMUX_PORTD_PIN2_gc = (0x6A<<0), /* Port D, Pin2 */ - EVSYS_CHMUX_PORTD_PIN3_gc = (0x6B<<0), /* Port D, Pin3 */ - EVSYS_CHMUX_PORTD_PIN4_gc = (0x6C<<0), /* Port D, Pin4 */ - EVSYS_CHMUX_PORTD_PIN5_gc = (0x6D<<0), /* Port D, Pin5 */ - EVSYS_CHMUX_PORTD_PIN6_gc = (0x6E<<0), /* Port D, Pin6 */ - EVSYS_CHMUX_PORTD_PIN7_gc = (0x6F<<0), /* Port D, Pin7 */ - EVSYS_CHMUX_PORTE_PIN0_gc = (0x70<<0), /* Port E, Pin0 */ - EVSYS_CHMUX_PORTE_PIN1_gc = (0x71<<0), /* Port E, Pin1 */ - EVSYS_CHMUX_PORTE_PIN2_gc = (0x72<<0), /* Port E, Pin2 */ - EVSYS_CHMUX_PORTE_PIN3_gc = (0x73<<0), /* Port E, Pin3 */ - EVSYS_CHMUX_PORTE_PIN4_gc = (0x74<<0), /* Port E, Pin4 */ - EVSYS_CHMUX_PORTE_PIN5_gc = (0x75<<0), /* Port E, Pin5 */ - EVSYS_CHMUX_PORTE_PIN6_gc = (0x76<<0), /* Port E, Pin6 */ - EVSYS_CHMUX_PORTE_PIN7_gc = (0x77<<0), /* Port E, Pin7 */ - EVSYS_CHMUX_PORTF_PIN0_gc = (0x78<<0), /* Port F, Pin0 */ - EVSYS_CHMUX_PORTF_PIN1_gc = (0x79<<0), /* Port F, Pin1 */ - EVSYS_CHMUX_PORTF_PIN2_gc = (0x7A<<0), /* Port F, Pin2 */ - EVSYS_CHMUX_PORTF_PIN3_gc = (0x7B<<0), /* Port F, Pin3 */ - EVSYS_CHMUX_PORTF_PIN4_gc = (0x7C<<0), /* Port F, Pin4 */ - EVSYS_CHMUX_PORTF_PIN5_gc = (0x7D<<0), /* Port F, Pin5 */ - EVSYS_CHMUX_PORTF_PIN6_gc = (0x7E<<0), /* Port F, Pin6 */ - EVSYS_CHMUX_PORTF_PIN7_gc = (0x7F<<0), /* Port F, Pin7 */ - EVSYS_CHMUX_PRESCALER_1_gc = (0x80<<0), /* Prescaler, divide by 1 */ - EVSYS_CHMUX_PRESCALER_2_gc = (0x81<<0), /* Prescaler, divide by 2 */ - EVSYS_CHMUX_PRESCALER_4_gc = (0x82<<0), /* Prescaler, divide by 4 */ - EVSYS_CHMUX_PRESCALER_8_gc = (0x83<<0), /* Prescaler, divide by 8 */ - EVSYS_CHMUX_PRESCALER_16_gc = (0x84<<0), /* Prescaler, divide by 16 */ - EVSYS_CHMUX_PRESCALER_32_gc = (0x85<<0), /* Prescaler, divide by 32 */ - EVSYS_CHMUX_PRESCALER_64_gc = (0x86<<0), /* Prescaler, divide by 64 */ - EVSYS_CHMUX_PRESCALER_128_gc = (0x87<<0), /* Prescaler, divide by 128 */ - EVSYS_CHMUX_PRESCALER_256_gc = (0x88<<0), /* Prescaler, divide by 256 */ - EVSYS_CHMUX_PRESCALER_512_gc = (0x89<<0), /* Prescaler, divide by 512 */ - EVSYS_CHMUX_PRESCALER_1024_gc = (0x8A<<0), /* Prescaler, divide by 1024 */ - EVSYS_CHMUX_PRESCALER_2048_gc = (0x8B<<0), /* Prescaler, divide by 2048 */ - EVSYS_CHMUX_PRESCALER_4096_gc = (0x8C<<0), /* Prescaler, divide by 4096 */ - EVSYS_CHMUX_PRESCALER_8192_gc = (0x8D<<0), /* Prescaler, divide by 8192 */ - EVSYS_CHMUX_PRESCALER_16384_gc = (0x8E<<0), /* Prescaler, divide by 16384 */ - EVSYS_CHMUX_PRESCALER_32768_gc = (0x8F<<0), /* Prescaler, divide by 32768 */ - EVSYS_CHMUX_TCC0_OVF_gc = (0xC0<<0), /* Timer/Counter C0 Overflow */ - EVSYS_CHMUX_TCC0_ERR_gc = (0xC1<<0), /* Timer/Counter C0 Error */ - EVSYS_CHMUX_TCC0_CCA_gc = (0xC4<<0), /* Timer/Counter C0 Compare or Capture A */ - EVSYS_CHMUX_TCC0_CCB_gc = (0xC5<<0), /* Timer/Counter C0 Compare or Capture B */ - EVSYS_CHMUX_TCC0_CCC_gc = (0xC6<<0), /* Timer/Counter C0 Compare or Capture C */ - EVSYS_CHMUX_TCC0_CCD_gc = (0xC7<<0), /* Timer/Counter C0 Compare or Capture D */ - EVSYS_CHMUX_TCC1_OVF_gc = (0xC8<<0), /* Timer/Counter C1 Overflow */ - EVSYS_CHMUX_TCC1_ERR_gc = (0xC9<<0), /* Timer/Counter C1 Error */ - EVSYS_CHMUX_TCC1_CCA_gc = (0xCC<<0), /* Timer/Counter C1 Compare or Capture A */ - EVSYS_CHMUX_TCC1_CCB_gc = (0xCD<<0), /* Timer/Counter C1 Compare or Capture B */ - EVSYS_CHMUX_TCD0_OVF_gc = (0xD0<<0), /* Timer/Counter D0 Overflow */ - EVSYS_CHMUX_TCD0_ERR_gc = (0xD1<<0), /* Timer/Counter D0 Error */ - EVSYS_CHMUX_TCD0_CCA_gc = (0xD4<<0), /* Timer/Counter D0 Compare or Capture A */ - EVSYS_CHMUX_TCD0_CCB_gc = (0xD5<<0), /* Timer/Counter D0 Compare or Capture B */ - EVSYS_CHMUX_TCD0_CCC_gc = (0xD6<<0), /* Timer/Counter D0 Compare or Capture C */ - EVSYS_CHMUX_TCD0_CCD_gc = (0xD7<<0), /* Timer/Counter D0 Compare or Capture D */ - EVSYS_CHMUX_TCD1_OVF_gc = (0xD8<<0), /* Timer/Counter D1 Overflow */ - EVSYS_CHMUX_TCD1_ERR_gc = (0xD9<<0), /* Timer/Counter D1 Error */ - EVSYS_CHMUX_TCD1_CCA_gc = (0xDC<<0), /* Timer/Counter D1 Compare or Capture A */ - EVSYS_CHMUX_TCD1_CCB_gc = (0xDD<<0), /* Timer/Counter D1 Compare or Capture B */ - EVSYS_CHMUX_TCE0_OVF_gc = (0xE0<<0), /* Timer/Counter E0 Overflow */ - EVSYS_CHMUX_TCE0_ERR_gc = (0xE1<<0), /* Timer/Counter E0 Error */ - EVSYS_CHMUX_TCE0_CCA_gc = (0xE4<<0), /* Timer/Counter E0 Compare or Capture A */ - EVSYS_CHMUX_TCE0_CCB_gc = (0xE5<<0), /* Timer/Counter E0 Compare or Capture B */ - EVSYS_CHMUX_TCE0_CCC_gc = (0xE6<<0), /* Timer/Counter E0 Compare or Capture C */ - EVSYS_CHMUX_TCE0_CCD_gc = (0xE7<<0), /* Timer/Counter E0 Compare or Capture D */ - EVSYS_CHMUX_TCE1_OVF_gc = (0xE8<<0), /* Timer/Counter E1 Overflow */ - EVSYS_CHMUX_TCE1_ERR_gc = (0xE9<<0), /* Timer/Counter E1 Error */ - EVSYS_CHMUX_TCE1_CCA_gc = (0xEC<<0), /* Timer/Counter E1 Compare or Capture A */ - EVSYS_CHMUX_TCE1_CCB_gc = (0xED<<0), /* Timer/Counter E1 Compare or Capture B */ - EVSYS_CHMUX_TCF0_OVF_gc = (0xF0<<0), /* Timer/Counter F0 Overflow */ - EVSYS_CHMUX_TCF0_ERR_gc = (0xF1<<0), /* Timer/Counter F0 Error */ - EVSYS_CHMUX_TCF0_CCA_gc = (0xF4<<0), /* Timer/Counter F0 Compare or Capture A */ - EVSYS_CHMUX_TCF0_CCB_gc = (0xF5<<0), /* Timer/Counter F0 Compare or Capture B */ - EVSYS_CHMUX_TCF0_CCC_gc = (0xF6<<0), /* Timer/Counter F0 Compare or Capture C */ - EVSYS_CHMUX_TCF0_CCD_gc = (0xF7<<0), /* Timer/Counter F0 Compare or Capture D */ - EVSYS_CHMUX_TCF1_OVF_gc = (0xF8<<0), /* Timer/Counter F1 Overflow */ - EVSYS_CHMUX_TCF1_ERR_gc = (0xF9<<0), /* Timer/Counter F1 Error */ - EVSYS_CHMUX_TCF1_CCA_gc = (0xFC<<0), /* Timer/Counter F1 Compare or Capture A */ - EVSYS_CHMUX_TCF1_CCB_gc = (0xFD<<0), /* Timer/Counter F1 Compare or Capture B */ -} EVSYS_CHMUX_t; - - -/* --------------------------------------------------------------------------- -NVM - Non Volatile Memory Controller --------------------------------------------------------------------------- -*/ - -/* Non-volatile Memory Controller */ -typedef struct NVM_struct -{ - register8_t ADDR0; /* Address Register 0 */ - register8_t ADDR1; /* Address Register 1 */ - register8_t ADDR2; /* Address Register 2 */ - register8_t reserved_0x03; - register8_t DATA0; /* Data Register 0 */ - register8_t DATA1; /* Data Register 1 */ - register8_t DATA2; /* Data Register 2 */ - register8_t reserved_0x07; - register8_t reserved_0x08; - register8_t reserved_0x09; - register8_t CMD; /* Command */ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t INTCTRL; /* Interrupt Control */ - register8_t reserved_0x0E; - register8_t STATUS; /* Status */ - register8_t LOCK_BITS; /* Lock Bits */ -} NVM_t; - -/* --------------------------------------------------------------------------- -NVM - Non Volatile Memory Controller --------------------------------------------------------------------------- -*/ - -/* Lock Bits */ -typedef struct NVM_LOCKBITS_struct -{ - register8_t LOCKBITS; /* Lock Bits */ -} NVM_LOCKBITS_t; - -/* --------------------------------------------------------------------------- -NVM - Non Volatile Memory Controller --------------------------------------------------------------------------- -*/ - -/* Fuses */ -typedef struct NVM_FUSES_struct -{ - register8_t FUSEBYTE0; /* User ID */ - register8_t FUSEBYTE1; /* Watchdog Configuration */ - register8_t FUSEBYTE2; /* Reset Configuration */ - register8_t reserved_0x03; - register8_t FUSEBYTE4; /* Start-up Configuration */ - register8_t FUSEBYTE5; /* EESAVE and BOD Level */ -} NVM_FUSES_t; - -/* --------------------------------------------------------------------------- -NVM - Non Volatile Memory Controller --------------------------------------------------------------------------- -*/ - -/* Production Signatures */ -typedef struct NVM_PROD_SIGNATURES_struct -{ - register8_t RCOSC2M; /* RCOSC 2MHz Calibration Value */ - register8_t reserved_0x01; - register8_t RCOSC32K; /* RCOSC 32kHz Calibration Value */ - register8_t RCOSC32M; /* RCOSC 32MHz Calibration Value */ - register8_t reserved_0x04; - register8_t reserved_0x05; - register8_t reserved_0x06; - register8_t reserved_0x07; - register8_t LOTNUM0; /* Lot Number Byte 0, ASCII */ - register8_t LOTNUM1; /* Lot Number Byte 1, ASCII */ - register8_t LOTNUM2; /* Lot Number Byte 2, ASCII */ - register8_t LOTNUM3; /* Lot Number Byte 3, ASCII */ - register8_t LOTNUM4; /* Lot Number Byte 4, ASCII */ - register8_t LOTNUM5; /* Lot Number Byte 5, ASCII */ - register8_t reserved_0x0E; - register8_t reserved_0x0F; - register8_t WAFNUM; /* Wafer Number */ - register8_t reserved_0x11; - register8_t COORDX0; /* Wafer Coordinate X Byte 0 */ - register8_t COORDX1; /* Wafer Coordinate X Byte 1 */ - register8_t COORDY0; /* Wafer Coordinate Y Byte 0 */ - register8_t COORDY1; /* Wafer Coordinate Y Byte 1 */ - register8_t reserved_0x16; - register8_t reserved_0x17; - register8_t reserved_0x18; - register8_t reserved_0x19; - register8_t reserved_0x1A; - register8_t reserved_0x1B; - register8_t reserved_0x1C; - register8_t reserved_0x1D; - register8_t reserved_0x1E; - register8_t reserved_0x1F; - register8_t ADCACAL0; /* ADCA Calibration Byte 0 */ - register8_t ADCACAL1; /* ADCA Calibration Byte 1 */ - register8_t reserved_0x22; - register8_t reserved_0x23; - register8_t ADCBCAL0; /* ADCB Calibration Byte 0 */ - register8_t ADCBCAL1; /* ADCB Calibration Byte 1 */ - register8_t reserved_0x26; - register8_t reserved_0x27; - register8_t reserved_0x28; - register8_t reserved_0x29; - register8_t reserved_0x2A; - register8_t reserved_0x2B; - register8_t reserved_0x2C; - register8_t reserved_0x2D; - register8_t TEMPSENSE0; /* Temperature Sensor Calibration Byte 0 */ - register8_t TEMPSENSE1; /* Temperature Sensor Calibration Byte 0 */ - register8_t DACAOFFCAL; /* DACA Calibration Byte 0 */ - register8_t DACAGAINCAL; /* DACA Calibration Byte 1 */ - register8_t DACBOFFCAL; /* DACB Calibration Byte 0 */ - register8_t DACBGAINCAL; /* DACB Calibration Byte 1 */ - register8_t reserved_0x34; - register8_t reserved_0x35; - register8_t reserved_0x36; - register8_t reserved_0x37; - register8_t reserved_0x38; - register8_t reserved_0x39; - register8_t reserved_0x3A; - register8_t reserved_0x3B; - register8_t reserved_0x3C; - register8_t reserved_0x3D; - register8_t reserved_0x3E; -} NVM_PROD_SIGNATURES_t; - -/* NVM Command */ -typedef enum NVM_CMD_enum -{ - NVM_CMD_NO_OPERATION_gc = (0x00<<0), /* Noop/Ordinary LPM */ - NVM_CMD_READ_CALIB_ROW_gc = (0x02<<0), /* Read calibration row */ - NVM_CMD_READ_USER_SIG_ROW_gc = (0x01<<0), /* Read user signature row */ - NVM_CMD_READ_EEPROM_gc = (0x06<<0), /* Read EEPROM */ - NVM_CMD_READ_FUSES_gc = (0x07<<0), /* Read fuse byte */ - NVM_CMD_WRITE_LOCK_BITS_gc = (0x08<<0), /* Write lock bits */ - NVM_CMD_ERASE_USER_SIG_ROW_gc = (0x18<<0), /* Erase user signature row */ - NVM_CMD_WRITE_USER_SIG_ROW_gc = (0x1A<<0), /* Write user signature row */ - NVM_CMD_ERASE_APP_gc = (0x20<<0), /* Erase Application Section */ - NVM_CMD_ERASE_APP_PAGE_gc = (0x22<<0), /* Erase Application Section page */ - NVM_CMD_LOAD_FLASH_BUFFER_gc = (0x23<<0), /* Load Flash page buffer */ - NVM_CMD_WRITE_APP_PAGE_gc = (0x24<<0), /* Write Application Section page */ - NVM_CMD_ERASE_WRITE_APP_PAGE_gc = (0x25<<0), /* Erase-and-write Application Section page */ - NVM_CMD_ERASE_FLASH_BUFFER_gc = (0x26<<0), /* Erase/flush Flash page buffer */ - NVM_CMD_ERASE_BOOT_PAGE_gc = (0x2A<<0), /* Erase Boot Section page */ - NVM_CMD_WRITE_BOOT_PAGE_gc = (0x2C<<0), /* Write Boot Section page */ - NVM_CMD_ERASE_WRITE_BOOT_PAGE_gc = (0x2D<<0), /* Erase-and-write Boot Section page */ - NVM_CMD_ERASE_EEPROM_gc = (0x30<<0), /* Erase EEPROM */ - NVM_CMD_ERASE_EEPROM_PAGE_gc = (0x32<<0), /* Erase EEPROM page */ - NVM_CMD_LOAD_EEPROM_BUFFER_gc = (0x33<<0), /* Load EEPROM page buffer */ - NVM_CMD_WRITE_EEPROM_PAGE_gc = (0x34<<0), /* Write EEPROM page */ - NVM_CMD_ERASE_WRITE_EEPROM_PAGE_gc = (0x35<<0), /* Erase-and-write EEPROM page */ - NVM_CMD_ERASE_EEPROM_BUFFER_gc = (0x36<<0), /* Erase/flush EEPROM page buffer */ - NVM_CMD_APP_CRC_gc = (0x38<<0), /* Generate Application section CRC */ - NVM_CMD_BOOT_CRC_gc = (0x39<<0), /* Generate Boot Section CRC */ - NVM_CMD_FLASH_RANGE_CRC_gc = (0x3A<<0), /* Generate Flash Range CRC */ -} NVM_CMD_t; - -/* SPM ready interrupt level */ -typedef enum NVM_SPMLVL_enum -{ - NVM_SPMLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ - NVM_SPMLVL_LO_gc = (0x01<<2), /* Low level */ - NVM_SPMLVL_MED_gc = (0x02<<2), /* Medium level */ - NVM_SPMLVL_HI_gc = (0x03<<2), /* High level */ -} NVM_SPMLVL_t; - -/* EEPROM ready interrupt level */ -typedef enum NVM_EELVL_enum -{ - NVM_EELVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ - NVM_EELVL_LO_gc = (0x01<<0), /* Low level */ - NVM_EELVL_MED_gc = (0x02<<0), /* Medium level */ - NVM_EELVL_HI_gc = (0x03<<0), /* High level */ -} NVM_EELVL_t; - -/* Boot lock bits - boot setcion */ -typedef enum NVM_BLBB_enum -{ - NVM_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ - NVM_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ - NVM_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ - NVM_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ -} NVM_BLBB_t; - -/* Boot lock bits - application section */ -typedef enum NVM_BLBA_enum -{ - NVM_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ - NVM_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ - NVM_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ - NVM_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ -} NVM_BLBA_t; - -/* Boot lock bits - application table section */ -typedef enum NVM_BLBAT_enum -{ - NVM_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ - NVM_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ - NVM_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ - NVM_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ -} NVM_BLBAT_t; - -/* Lock bits */ -typedef enum NVM_LB_enum -{ - NVM_LB_NOLOCK_gc = (0x03<<0), /* No locks */ - NVM_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ - NVM_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ -} NVM_LB_t; - -/* Boot Loader Section Reset Vector */ -typedef enum BOOTRST_enum -{ - BOOTRST_BOOTLDR_gc = (0x00<<6), /* Boot Loader Reset */ - BOOTRST_APPLICATION_gc = (0x01<<6), /* Application Reset */ -} BOOTRST_t; - -/* BOD operation */ -typedef enum BOD_enum -{ - BOD_INSAMPLEDMODE_gc = (0x01<<0), /* BOD enabled in sampled mode */ - BOD_CONTINOUSLY_gc = (0x02<<0), /* BOD enabled continuously */ - BOD_DISABLED_gc = (0x03<<0), /* BOD Disabled */ -} BOD_t; - -/* Watchdog (Window) Timeout Period */ -typedef enum WD_enum -{ - WD_8CLK_gc = (0x00<<4), /* 8 cycles (8ms @ 3.3V) */ - WD_16CLK_gc = (0x01<<4), /* 16 cycles (16ms @ 3.3V) */ - WD_32CLK_gc = (0x02<<4), /* 32 cycles (32ms @ 3.3V) */ - WD_64CLK_gc = (0x03<<4), /* 64 cycles (64ms @ 3.3V) */ - WD_128CLK_gc = (0x04<<4), /* 128 cycles (0.125s @ 3.3V) */ - WD_256CLK_gc = (0x05<<4), /* 256 cycles (0.25s @ 3.3V) */ - WD_512CLK_gc = (0x06<<4), /* 512 cycles (0.5s @ 3.3V) */ - WD_1KCLK_gc = (0x07<<4), /* 1K cycles (1s @ 3.3V) */ - WD_2KCLK_gc = (0x08<<4), /* 2K cycles (2s @ 3.3V) */ - WD_4KCLK_gc = (0x09<<4), /* 4K cycles (4s @ 3.3V) */ - WD_8KCLK_gc = (0x0A<<4), /* 8K cycles (8s @ 3.3V) */ -} WD_t; - -/* Start-up Time */ -typedef enum SUT_enum -{ - SUT_0MS_gc = (0x03<<2), /* 0 ms */ - SUT_4MS_gc = (0x01<<2), /* 4 ms */ - SUT_64MS_gc = (0x00<<2), /* 64 ms */ -} SUT_t; - -/* Brown Out Detection Voltage Level */ -typedef enum BODLVL_enum -{ - BODLVL_1V6_gc = (0x07<<0), /* 1.6 V */ - BODLVL_1V8_gc = (0x06<<0), /* 1.8 V */ - BODLVL_2V0_gc = (0x05<<0), /* 2.0 V */ - BODLVL_2V2_gc = (0x04<<0), /* 2.2 V */ - BODLVL_2V4_gc = (0x03<<0), /* 2.4 V */ - BODLVL_2V6_gc = (0x02<<0), /* 2.6 V */ - BODLVL_2V8_gc = (0x01<<0), /* 2.8 V */ - BODLVL_3V0_gc = (0x00<<0), /* 3.0 V */ -} BODLVL_t; - - -/* --------------------------------------------------------------------------- -AC - Analog Comparator --------------------------------------------------------------------------- -*/ - -/* Analog Comparator */ -typedef struct AC_struct -{ - register8_t AC0CTRL; /* Comparator 0 Control */ - register8_t AC1CTRL; /* Comparator 1 Control */ - register8_t AC0MUXCTRL; /* Comparator 0 MUX Control */ - register8_t AC1MUXCTRL; /* Comparator 1 MUX Control */ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t WINCTRL; /* Window Mode Control */ - register8_t STATUS; /* Status */ -} AC_t; - -/* Interrupt mode */ -typedef enum AC_INTMODE_enum -{ - AC_INTMODE_BOTHEDGES_gc = (0x00<<6), /* Interrupt on both edges */ - AC_INTMODE_FALLING_gc = (0x02<<6), /* Interrupt on falling edge */ - AC_INTMODE_RISING_gc = (0x03<<6), /* Interrupt on rising edge */ -} AC_INTMODE_t; - -/* Interrupt level */ -typedef enum AC_INTLVL_enum -{ - AC_INTLVL_OFF_gc = (0x00<<4), /* Interrupt disabled */ - AC_INTLVL_LO_gc = (0x01<<4), /* Low level */ - AC_INTLVL_MED_gc = (0x02<<4), /* Medium level */ - AC_INTLVL_HI_gc = (0x03<<4), /* High level */ -} AC_INTLVL_t; - -/* Hysteresis mode selection */ -typedef enum AC_HYSMODE_enum -{ - AC_HYSMODE_NO_gc = (0x00<<1), /* No hysteresis */ - AC_HYSMODE_SMALL_gc = (0x01<<1), /* Small hysteresis */ - AC_HYSMODE_LARGE_gc = (0x02<<1), /* Large hysteresis */ -} AC_HYSMODE_t; - -/* Positive input multiplexer selection */ -typedef enum AC_MUXPOS_enum -{ - AC_MUXPOS_PIN0_gc = (0x00<<3), /* Pin 0 */ - AC_MUXPOS_PIN1_gc = (0x01<<3), /* Pin 1 */ - AC_MUXPOS_PIN2_gc = (0x02<<3), /* Pin 2 */ - AC_MUXPOS_PIN3_gc = (0x03<<3), /* Pin 3 */ - AC_MUXPOS_PIN4_gc = (0x04<<3), /* Pin 4 */ - AC_MUXPOS_PIN5_gc = (0x05<<3), /* Pin 5 */ - AC_MUXPOS_PIN6_gc = (0x06<<3), /* Pin 6 */ - AC_MUXPOS_DAC_gc = (0x07<<3), /* DAC output */ -} AC_MUXPOS_t; - -/* Negative input multiplexer selection */ -typedef enum AC_MUXNEG_enum -{ - AC_MUXNEG_PIN0_gc = (0x00<<0), /* Pin 0 */ - AC_MUXNEG_PIN1_gc = (0x01<<0), /* Pin 1 */ - AC_MUXNEG_PIN3_gc = (0x02<<0), /* Pin 3 */ - AC_MUXNEG_PIN5_gc = (0x03<<0), /* Pin 5 */ - AC_MUXNEG_PIN7_gc = (0x04<<0), /* Pin 7 */ - AC_MUXNEG_DAC_gc = (0x05<<0), /* DAC output */ - AC_MUXNEG_BANDGAP_gc = (0x06<<0), /* Bandgap Reference */ - AC_MUXNEG_SCALER_gc = (0x07<<0), /* Internal voltage scaler */ -} AC_MUXNEG_t; - -/* Windows interrupt mode */ -typedef enum AC_WINTMODE_enum -{ - AC_WINTMODE_ABOVE_gc = (0x00<<2), /* Interrupt on above window */ - AC_WINTMODE_INSIDE_gc = (0x01<<2), /* Interrupt on inside window */ - AC_WINTMODE_BELOW_gc = (0x02<<2), /* Interrupt on below window */ - AC_WINTMODE_OUTSIDE_gc = (0x03<<2), /* Interrupt on outside window */ -} AC_WINTMODE_t; - -/* Window interrupt level */ -typedef enum AC_WINTLVL_enum -{ - AC_WINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ - AC_WINTLVL_LO_gc = (0x01<<0), /* Low priority */ - AC_WINTLVL_MED_gc = (0x02<<0), /* Medium priority */ - AC_WINTLVL_HI_gc = (0x03<<0), /* High priority */ -} AC_WINTLVL_t; - -/* Window mode state */ -typedef enum AC_WSTATE_enum -{ - AC_WSTATE_ABOVE_gc = (0x00<<6), /* Signal above window */ - AC_WSTATE_INSIDE_gc = (0x01<<6), /* Signal inside window */ - AC_WSTATE_BELOW_gc = (0x02<<6), /* Signal below window */ -} AC_WSTATE_t; - - -/* --------------------------------------------------------------------------- -ADC - Analog/Digital Converter --------------------------------------------------------------------------- -*/ - -/* ADC Channel */ -typedef struct ADC_CH_struct -{ - register8_t CTRL; /* Control Register */ - register8_t MUXCTRL; /* MUX Control */ - register8_t INTCTRL; /* Channel Interrupt Control */ - register8_t INTFLAGS; /* Interrupt Flags */ - _WORDREGISTER(RES); /* Channel Result */ - register8_t reserved_0x6; - register8_t reserved_0x7; -} ADC_CH_t; - -/* --------------------------------------------------------------------------- -ADC - Analog/Digital Converter --------------------------------------------------------------------------- -*/ - -/* Analog-to-Digital Converter */ -typedef struct ADC_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t REFCTRL; /* Reference Control */ - register8_t EVCTRL; /* Event Control */ - register8_t PRESCALER; /* Clock Prescaler */ - register8_t reserved_0x05; - register8_t INTFLAGS; /* Interrupt Flags */ - register8_t reserved_0x07; - register8_t reserved_0x08; - register8_t reserved_0x09; - register8_t reserved_0x0A; - register8_t reserved_0x0B; - _WORDREGISTER(CAL); /* Calibration Value */ - register8_t reserved_0x0E; - register8_t reserved_0x0F; - _WORDREGISTER(CH0RES); /* Channel 0 Result */ - register8_t reserved_0x12; - register8_t reserved_0x13; - register8_t reserved_0x14; - register8_t reserved_0x15; - register8_t reserved_0x16; - register8_t reserved_0x17; - _WORDREGISTER(CMP); /* Compare Value */ - register8_t reserved_0x1A; - register8_t reserved_0x1B; - register8_t reserved_0x1C; - register8_t reserved_0x1D; - register8_t reserved_0x1E; - register8_t reserved_0x1F; - ADC_CH_t CH0; /* ADC Channel 0 */ -} ADC_t; - -/* Positive input multiplexer selection */ -typedef enum ADC_CH_MUXPOS_enum -{ - ADC_CH_MUXPOS_PIN0_gc = (0x00<<3), /* Input pin 0 */ - ADC_CH_MUXPOS_PIN1_gc = (0x01<<3), /* Input pin 1 */ - ADC_CH_MUXPOS_PIN2_gc = (0x02<<3), /* Input pin 2 */ - ADC_CH_MUXPOS_PIN3_gc = (0x03<<3), /* Input pin 3 */ - ADC_CH_MUXPOS_PIN4_gc = (0x04<<3), /* Input pin 4 */ - ADC_CH_MUXPOS_PIN5_gc = (0x05<<3), /* Input pin 5 */ - ADC_CH_MUXPOS_PIN6_gc = (0x06<<3), /* Input pin 6 */ - ADC_CH_MUXPOS_PIN7_gc = (0x07<<3), /* Input pin 7 */ - ADC_CH_MUXPOS_PIN8_gc = (0x08<<3), /* Input pin 8 */ - ADC_CH_MUXPOS_PIN9_gc = (0x09<<3), /* Input pin 9 */ - ADC_CH_MUXPOS_PIN10_gc = (0x10<<3), /* Input pin 10 */ - ADC_CH_MUXPOS_PIN11_gc = (0x11<<3), /* Input pin 11 */ -} ADC_CH_MUXPOS_t; - -/* Internal input multiplexer selections */ -typedef enum ADC_CH_MUXINT_enum -{ - ADC_CH_MUXINT_TEMP_gc = (0x00<<3), /* Temperature Reference */ - ADC_CH_MUXINT_BANDGAP_gc = (0x01<<3), /* Bandgap Reference */ - ADC_CH_MUXINT_SCALEDVCC_gc = (0x02<<3), /* 1/10 scaled VCC */ - ADC_CH_MUXINT_DAC_gc = (0x03<<3), /* DAC output */ -} ADC_CH_MUXINT_t; - -/* Negative input multiplexer selection */ -typedef enum ADC_CH_MUXNEG_enum -{ - ADC_CH_MUXNEG_PIN0_gc = (0x00<<0), /* Input pin 0, INPUTMODE[1:0] = 10 */ - ADC_CH_MUXNEG_PIN1_gc = (0x01<<0), /* Input pin 1, INPUTMODE[1:0] = 10 */ - ADC_CH_MUXNEG_PIN2_gc = (0x02<<0), /* Input pin 2, INPUTMODE[1:0] = 10 */ - ADC_CH_MUXNEG_PIN3_gc = (0x03<<0), /* Input pin 3, INPUTMODE[1:0] = 10 */ - ADC_CH_MUXNEG_PIN4_gc = (0x00<<0), /* Input pin 4, INPUTMODE[1:0] = 11 */ - ADC_CH_MUXNEG_PIN5_gc = (0x01<<0), /* Input pin 5, INPUTMODE[1:0] = 11 */ - ADC_CH_MUXNEG_PIN6_gc = (0x02<<0), /* Input pin 6, INPUTMODE[1:0] = 11 */ - ADC_CH_MUXNEG_PIN7_gc = (0x03<<0), /* Input pin 7, INPUTMODE[1:0] = 11 */ -} ADC_CH_MUXNEG_t; - -/* Input mode */ -typedef enum ADC_CH_INPUTMODE_enum -{ - ADC_CH_INPUTMODE_INTERNAL_gc = (0x00<<0), /* Internal inputs, no gain */ - ADC_CH_INPUTMODE_SINGLEENDED_gc = (0x01<<0), /* Single-ended input, no gain */ - ADC_CH_INPUTMODE_DIFF_gc = (0x02<<0), /* Differential input, no gain */ - ADC_CH_INPUTMODE_DIFFWGAIN_gc = (0x03<<0), /* Differential input, with gain */ -} ADC_CH_INPUTMODE_t; - -/* Gain factor */ -typedef enum ADC_CH_GAIN_enum -{ - ADC_CH_GAIN_1X_gc = (0x00<<2), /* 1x gain */ - ADC_CH_GAIN_2X_gc = (0x01<<2), /* 2x gain */ - ADC_CH_GAIN_4X_gc = (0x02<<2), /* 4x gain */ - ADC_CH_GAIN_8X_gc = (0x03<<2), /* 8x gain */ - ADC_CH_GAIN_16X_gc = (0x04<<2), /* 16x gain */ - ADC_CH_GAIN_32X_gc = (0x05<<2), /* 32x gain */ - ADC_CH_GAIN_64X_gc = (0x06<<2), /* 64x gain */ - ADC_CH_GAIN_DIV2_gc = (0x07<<2), /* x/2 gain */ -} ADC_CH_GAIN_t; - -/* Conversion result resolution */ -typedef enum ADC_RESOLUTION_enum -{ - ADC_RESOLUTION_12BIT_gc = (0x00<<1), /* 12-bit right-adjusted result */ - ADC_RESOLUTION_8BIT_gc = (0x02<<1), /* 8-bit right-adjusted result */ - ADC_RESOLUTION_LEFT12BIT_gc = (0x03<<1), /* 12-bit left-adjusted result */ -} ADC_RESOLUTION_t; - -typedef enum ADC_CURRLIMIT_enum -{ - ADC_CURRLIMIT_NO_gc = (0x00<<5), /* No limit */ - ADC_CURRLIMIT_LOW_gc = (0x01<<5), /* Low current limit, max. sampling rate 1.5MSPS */ - ADC_CURRLIMIT_MED_gc = (0x02<<5), /* Medium current limit, max. sampling rate 1MSPS */ - ADC_CURRLIMIT_HIGH_gc = (0x03<<5), /* High current limit, max. sampling rate 0.5MSPS */ -} ADC_CURRLIMIT_t; - -/* Voltage reference selection */ -typedef enum ADC_REFSEL_enum -{ - ADC_REFSEL_INT1V_gc = (0x00<<4), /* Internal 1V */ - ADC_REFSEL_VCC_gc = (0x01<<4), /* Internal VCC/1.6V */ - ADC_REFSEL_AREFA_gc = (0x02<<4), /* External reference on PORT A */ - ADC_REFSEL_AREFB_gc = (0x03<<4), /* External reference on PORT B */ -} ADC_REFSEL_t; - -/* Channel sweep selection */ -typedef enum ADC_SWEEP_enum -{ - ADC_SWEEP_0_gc = (0x00<<6), /* ADC Channel 0 */ -} ADC_SWEEP_t; - -/* Event channel input selection */ -typedef enum ADC_EVSEL_enum -{ - ADC_EVSEL_0123_gc = (0x00<<3), /* Event Channel 0,1,2,3 */ - ADC_EVSEL_1234_gc = (0x01<<3), /* Event Channel 1,2,3,4 */ - ADC_EVSEL_2345_gc = (0x02<<3), /* Event Channel 2,3,4,5 */ - ADC_EVSEL_3456_gc = (0x03<<3), /* Event Channel 3,4,5,6 */ - ADC_EVSEL_4567_gc = (0x04<<3), /* Event Channel 4,5,6,7 */ - ADC_EVSEL_567_gc = (0x05<<3), /* Event Channel 5,6,7 */ - ADC_EVSEL_67_gc = (0x06<<3), /* Event Channel 6,7 */ - ADC_EVSEL_7_gc = (0x07<<3), /* Event Channel 7 */ -} ADC_EVSEL_t; - -/* Event action selection */ -typedef enum ADC_EVACT_enum -{ - ADC_EVACT_NONE_gc = (0x00<<0), /* No event action */ - ADC_EVACT_CH0_gc = (0x01<<0), /* First event triggers channel 0 */ -} ADC_EVACT_t; - -/* Interupt mode */ -typedef enum ADC_CH_INTMODE_enum -{ - ADC_CH_INTMODE_COMPLETE_gc = (0x00<<2), /* Interrupt on conversion complete */ - ADC_CH_INTMODE_BELOW_gc = (0x01<<2), /* Interrupt on result below compare value */ - ADC_CH_INTMODE_ABOVE_gc = (0x03<<2), /* Interrupt on result above compare value */ -} ADC_CH_INTMODE_t; - -/* Interrupt level */ -typedef enum ADC_CH_INTLVL_enum -{ - ADC_CH_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ - ADC_CH_INTLVL_LO_gc = (0x01<<0), /* Low level */ - ADC_CH_INTLVL_MED_gc = (0x02<<0), /* Medium level */ - ADC_CH_INTLVL_HI_gc = (0x03<<0), /* High level */ -} ADC_CH_INTLVL_t; - -/* Clock prescaler */ -typedef enum ADC_PRESCALER_enum -{ - ADC_PRESCALER_DIV4_gc = (0x00<<0), /* Divide clock by 4 */ - ADC_PRESCALER_DIV8_gc = (0x01<<0), /* Divide clock by 8 */ - ADC_PRESCALER_DIV16_gc = (0x02<<0), /* Divide clock by 16 */ - ADC_PRESCALER_DIV32_gc = (0x03<<0), /* Divide clock by 32 */ - ADC_PRESCALER_DIV64_gc = (0x04<<0), /* Divide clock by 64 */ - ADC_PRESCALER_DIV128_gc = (0x05<<0), /* Divide clock by 128 */ - ADC_PRESCALER_DIV256_gc = (0x06<<0), /* Divide clock by 256 */ - ADC_PRESCALER_DIV512_gc = (0x07<<0), /* Divide clock by 512 */ -} ADC_PRESCALER_t; - - -/* --------------------------------------------------------------------------- -RTC - Real-Time Clounter --------------------------------------------------------------------------- -*/ - -/* Real-Time Counter */ -typedef struct RTC_struct -{ - register8_t CTRL; /* Control Register */ - register8_t STATUS; /* Status Register */ - register8_t INTCTRL; /* Interrupt Control Register */ - register8_t INTFLAGS; /* Interrupt Flags */ - register8_t TEMP; /* Temporary register */ - register8_t reserved_0x05; - register8_t reserved_0x06; - register8_t reserved_0x07; - _WORDREGISTER(CNT); /* Count Register */ - _WORDREGISTER(PER); /* Period Register */ - _WORDREGISTER(COMP); /* Compare Register */ -} RTC_t; - -/* Prescaler Factor */ -typedef enum RTC_PRESCALER_enum -{ - RTC_PRESCALER_OFF_gc = (0x00<<0), /* RTC Off */ - RTC_PRESCALER_DIV1_gc = (0x01<<0), /* RTC Clock */ - RTC_PRESCALER_DIV2_gc = (0x02<<0), /* RTC Clock / 2 */ - RTC_PRESCALER_DIV8_gc = (0x03<<0), /* RTC Clock / 8 */ - RTC_PRESCALER_DIV16_gc = (0x04<<0), /* RTC Clock / 16 */ - RTC_PRESCALER_DIV64_gc = (0x05<<0), /* RTC Clock / 64 */ - RTC_PRESCALER_DIV256_gc = (0x06<<0), /* RTC Clock / 256 */ - RTC_PRESCALER_DIV1024_gc = (0x07<<0), /* RTC Clock / 1024 */ -} RTC_PRESCALER_t; - -/* Compare Interrupt level */ -typedef enum RTC_COMPINTLVL_enum -{ - RTC_COMPINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ - RTC_COMPINTLVL_LO_gc = (0x01<<2), /* Low Level */ - RTC_COMPINTLVL_MED_gc = (0x02<<2), /* Medium Level */ - RTC_COMPINTLVL_HI_gc = (0x03<<2), /* High Level */ -} RTC_COMPINTLVL_t; - -/* Overflow Interrupt level */ -typedef enum RTC_OVFINTLVL_enum -{ - RTC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - RTC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ - RTC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ - RTC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ -} RTC_OVFINTLVL_t; - - -/* --------------------------------------------------------------------------- -EBI - External Bus Interface --------------------------------------------------------------------------- -*/ - -/* EBI Chip Select Module */ -typedef struct EBI_CS_struct -{ - register8_t CTRLA; /* Chip Select Control Register A */ - register8_t CTRLB; /* Chip Select Control Register B */ - _WORDREGISTER(BASEADDR); /* Chip Select Base Address */ -} EBI_CS_t; - -/* --------------------------------------------------------------------------- -EBI - External Bus Interface --------------------------------------------------------------------------- -*/ - -/* External Bus Interface */ -typedef struct EBI_struct -{ - register8_t CTRL; /* Control */ - register8_t SDRAMCTRLA; /* SDRAM Control Register A */ - register8_t reserved_0x02; - register8_t reserved_0x03; - _WORDREGISTER(REFRESH); /* SDRAM Refresh Period */ - _WORDREGISTER(INITDLY); /* SDRAM Initialization Delay */ - register8_t SDRAMCTRLB; /* SDRAM Control Register B */ - register8_t SDRAMCTRLC; /* SDRAM Control Register C */ - register8_t reserved_0x0A; - register8_t reserved_0x0B; - register8_t reserved_0x0C; - register8_t reserved_0x0D; - register8_t reserved_0x0E; - register8_t reserved_0x0F; - EBI_CS_t CS0; /* Chip Select 0 */ - EBI_CS_t CS1; /* Chip Select 1 */ - EBI_CS_t CS2; /* Chip Select 2 */ - EBI_CS_t CS3; /* Chip Select 3 */ -} EBI_t; - -/* Chip Select adress space */ -typedef enum EBI_CS_ASIZE_enum -{ - EBI_CS_ASIZE_256B_gc = (0x00<<2), /* 256 bytes */ - EBI_CS_ASIZE_512B_gc = (0x01<<2), /* 512 bytes */ - EBI_CS_ASIZE_1KB_gc = (0x02<<2), /* 1K bytes */ - EBI_CS_ASIZE_2KB_gc = (0x03<<2), /* 2K bytes */ - EBI_CS_ASIZE_4KB_gc = (0x04<<2), /* 4K bytes */ - EBI_CS_ASIZE_8KB_gc = (0x05<<2), /* 8K bytes */ - EBI_CS_ASIZE_16KB_gc = (0x06<<2), /* 16K bytes */ - EBI_CS_ASIZE_32KB_gc = (0x07<<2), /* 32K bytes */ - EBI_CS_ASIZE_64KB_gc = (0x08<<2), /* 64K bytes */ - EBI_CS_ASIZE_128KB_gc = (0x09<<2), /* 128K bytes */ - EBI_CS_ASIZE_256KB_gc = (0x0A<<2), /* 256K bytes */ - EBI_CS_ASIZE_512KB_gc = (0x0B<<2), /* 512K bytes */ - EBI_CS_ASIZE_1MB_gc = (0x0C<<2), /* 1M bytes */ - EBI_CS_ASIZE_2MB_gc = (0x0D<<2), /* 2M bytes */ - EBI_CS_ASIZE_4MB_gc = (0x0E<<2), /* 4M bytes */ - EBI_CS_ASIZE_8MB_gc = (0x0F<<2), /* 8M bytes */ - EBI_CS_ASIZE_16M_gc = (0x10<<2), /* 16M bytes */ -} EBI_CS_ASIZE_t; - -/* */ -typedef enum EBI_CS_SRWS_enum -{ - EBI_CS_SRWS_0CLK_gc = (0x00<<0), /* 0 cycles */ - EBI_CS_SRWS_1CLK_gc = (0x01<<0), /* 1 cycle */ - EBI_CS_SRWS_2CLK_gc = (0x02<<0), /* 2 cycles */ - EBI_CS_SRWS_3CLK_gc = (0x03<<0), /* 3 cycles */ - EBI_CS_SRWS_4CLK_gc = (0x04<<0), /* 4 cycles */ - EBI_CS_SRWS_5CLK_gc = (0x05<<0), /* 5 cycle */ - EBI_CS_SRWS_6CLK_gc = (0x06<<0), /* 6 cycles */ - EBI_CS_SRWS_7CLK_gc = (0x07<<0), /* 7 cycles */ -} EBI_CS_SRWS_t; - -/* Chip Select address mode */ -typedef enum EBI_CS_MODE_enum -{ - EBI_CS_MODE_DISABLED_gc = (0x00<<0), /* Chip Select Disabled */ - EBI_CS_MODE_SRAM_gc = (0x01<<0), /* Chip Select in SRAM mode */ - EBI_CS_MODE_LPC_gc = (0x02<<0), /* Chip Select in SRAM LPC mode */ - EBI_CS_MODE_SDRAM_gc = (0x03<<0), /* Chip Select in SDRAM mode */ -} EBI_CS_MODE_t; - -/* Chip Select SDRAM mode */ -typedef enum EBI_CS_SDMODE_enum -{ - EBI_CS_SDMODE_NORMAL_gc = (0x00<<0), /* Normal mode */ - EBI_CS_SDMODE_LOAD_gc = (0x01<<0), /* Load Mode Register command mode */ -} EBI_CS_SDMODE_t; - -/* */ -typedef enum EBI_SDDATAW_enum -{ - EBI_SDDATAW_4BIT_gc = (0x00<<6), /* 4-bit data bus */ - EBI_SDDATAW_8BIT_gc = (0x01<<6), /* 8-bit data bus */ -} EBI_SDDATAW_t; - -/* */ -typedef enum EBI_LPCMODE_enum -{ - EBI_LPCMODE_ALE1_gc = (0x00<<4), /* Data muxed with addr byte 0 */ - EBI_LPCMODE_ALE12_gc = (0x02<<4), /* Data muxed with addr byte 0 and 1 */ -} EBI_LPCMODE_t; - -/* */ -typedef enum EBI_SRMODE_enum -{ - EBI_SRMODE_ALE1_gc = (0x00<<2), /* Addr byte 0 muxed with 1 */ - EBI_SRMODE_ALE2_gc = (0x01<<2), /* Addr byte 0 muxed with 2 */ - EBI_SRMODE_ALE12_gc = (0x02<<2), /* Addr byte 0 muxed with 1 and 2 */ - EBI_SRMODE_NOALE_gc = (0x03<<2), /* No addr muxing */ -} EBI_SRMODE_t; - -/* */ -typedef enum EBI_IFMODE_enum -{ - EBI_IFMODE_DISABLED_gc = (0x00<<0), /* EBI Disabled */ - EBI_IFMODE_3PORT_gc = (0x01<<0), /* 3-port mode */ - EBI_IFMODE_4PORT_gc = (0x02<<0), /* 4-port mode */ - EBI_IFMODE_2PORT_gc = (0x03<<0), /* 2-port mode */ -} EBI_IFMODE_t; - -/* */ -typedef enum EBI_SDCOL_enum -{ - EBI_SDCOL_8BIT_gc = (0x00<<0), /* 8 column bits */ - EBI_SDCOL_9BIT_gc = (0x01<<0), /* 9 column bits */ - EBI_SDCOL_10BIT_gc = (0x02<<0), /* 10 column bits */ - EBI_SDCOL_11BIT_gc = (0x03<<0), /* 11 column bits */ -} EBI_SDCOL_t; - -/* */ -typedef enum EBI_MRDLY_enum -{ - EBI_MRDLY_0CLK_gc = (0x00<<6), /* 0 cycles */ - EBI_MRDLY_1CLK_gc = (0x01<<6), /* 1 cycle */ - EBI_MRDLY_2CLK_gc = (0x02<<6), /* 2 cycles */ - EBI_MRDLY_3CLK_gc = (0x03<<6), /* 3 cycles */ -} EBI_MRDLY_t; - -/* */ -typedef enum EBI_ROWCYCDLY_enum -{ - EBI_ROWCYCDLY_0CLK_gc = (0x00<<3), /* 0 cycles */ - EBI_ROWCYCDLY_1CLK_gc = (0x01<<3), /* 1 cycle */ - EBI_ROWCYCDLY_2CLK_gc = (0x02<<3), /* 2 cycles */ - EBI_ROWCYCDLY_3CLK_gc = (0x03<<3), /* 3 cycles */ - EBI_ROWCYCDLY_4CLK_gc = (0x04<<3), /* 4 cycles */ - EBI_ROWCYCDLY_5CLK_gc = (0x05<<3), /* 5 cycle */ - EBI_ROWCYCDLY_6CLK_gc = (0x06<<3), /* 6 cycles */ - EBI_ROWCYCDLY_7CLK_gc = (0x07<<3), /* 7 cycles */ -} EBI_ROWCYCDLY_t; - -/* */ -typedef enum EBI_RPDLY_enum -{ - EBI_RPDLY_0CLK_gc = (0x00<<0), /* 0 cycles */ - EBI_RPDLY_1CLK_gc = (0x01<<0), /* 1 cycle */ - EBI_RPDLY_2CLK_gc = (0x02<<0), /* 2 cycles */ - EBI_RPDLY_3CLK_gc = (0x03<<0), /* 3 cycles */ - EBI_RPDLY_4CLK_gc = (0x04<<0), /* 4 cycles */ - EBI_RPDLY_5CLK_gc = (0x05<<0), /* 5 cycle */ - EBI_RPDLY_6CLK_gc = (0x06<<0), /* 6 cycles */ - EBI_RPDLY_7CLK_gc = (0x07<<0), /* 7 cycles */ -} EBI_RPDLY_t; - -/* */ -typedef enum EBI_WRDLY_enum -{ - EBI_WRDLY_0CLK_gc = (0x00<<6), /* 0 cycles */ - EBI_WRDLY_1CLK_gc = (0x01<<6), /* 1 cycle */ - EBI_WRDLY_2CLK_gc = (0x02<<6), /* 2 cycles */ - EBI_WRDLY_3CLK_gc = (0x03<<6), /* 3 cycles */ -} EBI_WRDLY_t; - -/* */ -typedef enum EBI_ESRDLY_enum -{ - EBI_ESRDLY_0CLK_gc = (0x00<<3), /* 0 cycles */ - EBI_ESRDLY_1CLK_gc = (0x01<<3), /* 1 cycle */ - EBI_ESRDLY_2CLK_gc = (0x02<<3), /* 2 cycles */ - EBI_ESRDLY_3CLK_gc = (0x03<<3), /* 3 cycles */ - EBI_ESRDLY_4CLK_gc = (0x04<<3), /* 4 cycles */ - EBI_ESRDLY_5CLK_gc = (0x05<<3), /* 5 cycle */ - EBI_ESRDLY_6CLK_gc = (0x06<<3), /* 6 cycles */ - EBI_ESRDLY_7CLK_gc = (0x07<<3), /* 7 cycles */ -} EBI_ESRDLY_t; - -/* */ -typedef enum EBI_ROWCOLDLY_enum -{ - EBI_ROWCOLDLY_0CLK_gc = (0x00<<0), /* 0 cycles */ - EBI_ROWCOLDLY_1CLK_gc = (0x01<<0), /* 1 cycle */ - EBI_ROWCOLDLY_2CLK_gc = (0x02<<0), /* 2 cycles */ - EBI_ROWCOLDLY_3CLK_gc = (0x03<<0), /* 3 cycles */ - EBI_ROWCOLDLY_4CLK_gc = (0x04<<0), /* 4 cycles */ - EBI_ROWCOLDLY_5CLK_gc = (0x05<<0), /* 5 cycle */ - EBI_ROWCOLDLY_6CLK_gc = (0x06<<0), /* 6 cycles */ - EBI_ROWCOLDLY_7CLK_gc = (0x07<<0), /* 7 cycles */ -} EBI_ROWCOLDLY_t; - - -/* --------------------------------------------------------------------------- -TWI - Two-Wire Interface --------------------------------------------------------------------------- -*/ - -/* */ -typedef struct TWI_MASTER_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t CTRLC; /* Control Register C */ - register8_t STATUS; /* Status Register */ - register8_t BAUD; /* Baurd Rate Control Register */ - register8_t ADDR; /* Address Register */ - register8_t DATA; /* Data Register */ -} TWI_MASTER_t; - -/* --------------------------------------------------------------------------- -TWI - Two-Wire Interface --------------------------------------------------------------------------- -*/ - -/* */ -typedef struct TWI_SLAVE_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t STATUS; /* Status Register */ - register8_t ADDR; /* Address Register */ - register8_t DATA; /* Data Register */ - register8_t ADDRMASK; /* Address Mask Register */ -} TWI_SLAVE_t; - -/* --------------------------------------------------------------------------- -TWI - Two-Wire Interface --------------------------------------------------------------------------- -*/ - -/* Two-Wire Interface */ -typedef struct TWI_struct -{ - register8_t CTRL; /* TWI Common Control Register */ - TWI_MASTER_t MASTER; /* TWI master module */ - TWI_SLAVE_t SLAVE; /* TWI slave module */ -} TWI_t; - -/* Master Interrupt Level */ -typedef enum TWI_MASTER_INTLVL_enum -{ - TWI_MASTER_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ - TWI_MASTER_INTLVL_LO_gc = (0x01<<6), /* Low Level */ - TWI_MASTER_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ - TWI_MASTER_INTLVL_HI_gc = (0x03<<6), /* High Level */ -} TWI_MASTER_INTLVL_t; - -/* Inactive Timeout */ -typedef enum TWI_MASTER_TIMEOUT_enum -{ - TWI_MASTER_TIMEOUT_DISABLED_gc = (0x00<<2), /* Bus Timeout Disabled */ - TWI_MASTER_TIMEOUT_50US_gc = (0x01<<2), /* 50 Microseconds */ - TWI_MASTER_TIMEOUT_100US_gc = (0x02<<2), /* 100 Microseconds */ - TWI_MASTER_TIMEOUT_200US_gc = (0x03<<2), /* 200 Microseconds */ -} TWI_MASTER_TIMEOUT_t; - -/* Master Command */ -typedef enum TWI_MASTER_CMD_enum -{ - TWI_MASTER_CMD_NOACT_gc = (0x00<<0), /* No Action */ - TWI_MASTER_CMD_REPSTART_gc = (0x01<<0), /* Issue Repeated Start Condition */ - TWI_MASTER_CMD_RECVTRANS_gc = (0x02<<0), /* Receive or Transmit Data */ - TWI_MASTER_CMD_STOP_gc = (0x03<<0), /* Issue Stop Condition */ -} TWI_MASTER_CMD_t; - -/* Master Bus State */ -typedef enum TWI_MASTER_BUSSTATE_enum -{ - TWI_MASTER_BUSSTATE_UNKNOWN_gc = (0x00<<0), /* Unknown Bus State */ - TWI_MASTER_BUSSTATE_IDLE_gc = (0x01<<0), /* Bus is Idle */ - TWI_MASTER_BUSSTATE_OWNER_gc = (0x02<<0), /* This Module Controls The Bus */ - TWI_MASTER_BUSSTATE_BUSY_gc = (0x03<<0), /* The Bus is Busy */ -} TWI_MASTER_BUSSTATE_t; - -/* Slave Interrupt Level */ -typedef enum TWI_SLAVE_INTLVL_enum -{ - TWI_SLAVE_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ - TWI_SLAVE_INTLVL_LO_gc = (0x01<<6), /* Low Level */ - TWI_SLAVE_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ - TWI_SLAVE_INTLVL_HI_gc = (0x03<<6), /* High Level */ -} TWI_SLAVE_INTLVL_t; - -/* Slave Command */ -typedef enum TWI_SLAVE_CMD_enum -{ - TWI_SLAVE_CMD_NOACT_gc = (0x00<<0), /* No Action */ - TWI_SLAVE_CMD_COMPTRANS_gc = (0x02<<0), /* Used To Complete a Transaction */ - TWI_SLAVE_CMD_RESPONSE_gc = (0x03<<0), /* Used in Response to Address/Data Interrupt */ -} TWI_SLAVE_CMD_t; - - -/* --------------------------------------------------------------------------- -PORT - Port Configuration --------------------------------------------------------------------------- -*/ - -/* I/O port Configuration */ -typedef struct PORTCFG_struct -{ - register8_t MPCMASK; /* Multi-pin Configuration Mask */ - register8_t reserved_0x01; - register8_t VPCTRLA; /* Virtual Port Control Register A */ - register8_t VPCTRLB; /* Virtual Port Control Register B */ - register8_t CLKEVOUT; /* Clock and Event Out Register */ -} PORTCFG_t; - -/* --------------------------------------------------------------------------- -PORT - Port Configuration --------------------------------------------------------------------------- -*/ - -/* Virtual Port */ -typedef struct VPORT_struct -{ - register8_t DIR; /* I/O Port Data Direction */ - register8_t OUT; /* I/O Port Output */ - register8_t IN; /* I/O Port Input */ - register8_t INTFLAGS; /* Interrupt Flag Register */ -} VPORT_t; - -/* --------------------------------------------------------------------------- -PORT - Port Configuration --------------------------------------------------------------------------- -*/ - -/* I/O Ports */ -typedef struct PORT_struct -{ - register8_t DIR; /* I/O Port Data Direction */ - register8_t DIRSET; /* I/O Port Data Direction Set */ - register8_t DIRCLR; /* I/O Port Data Direction Clear */ - register8_t DIRTGL; /* I/O Port Data Direction Toggle */ - register8_t OUT; /* I/O Port Output */ - register8_t OUTSET; /* I/O Port Output Set */ - register8_t OUTCLR; /* I/O Port Output Clear */ - register8_t OUTTGL; /* I/O Port Output Toggle */ - register8_t IN; /* I/O port Input */ - register8_t INTCTRL; /* Interrupt Control Register */ - register8_t INT0MASK; /* Port Interrupt 0 Mask */ - register8_t INT1MASK; /* Port Interrupt 1 Mask */ - register8_t INTFLAGS; /* Interrupt Flag Register */ - register8_t reserved_0x0D; - register8_t reserved_0x0E; - register8_t reserved_0x0F; - register8_t PIN0CTRL; /* Pin 0 Control Register */ - register8_t PIN1CTRL; /* Pin 1 Control Register */ - register8_t PIN2CTRL; /* Pin 2 Control Register */ - register8_t PIN3CTRL; /* Pin 3 Control Register */ - register8_t PIN4CTRL; /* Pin 4 Control Register */ - register8_t PIN5CTRL; /* Pin 5 Control Register */ - register8_t PIN6CTRL; /* Pin 6 Control Register */ - register8_t PIN7CTRL; /* Pin 7 Control Register */ -} PORT_t; - -/* Virtual Port 0 Mapping */ -typedef enum PORTCFG_VP0MAP_enum -{ - PORTCFG_VP0MAP_PORTA_gc = (0x00<<0), /* Mapped To PORTA */ - PORTCFG_VP0MAP_PORTB_gc = (0x01<<0), /* Mapped To PORTB */ - PORTCFG_VP0MAP_PORTC_gc = (0x02<<0), /* Mapped To PORTC */ - PORTCFG_VP0MAP_PORTD_gc = (0x03<<0), /* Mapped To PORTD */ - PORTCFG_VP0MAP_PORTE_gc = (0x04<<0), /* Mapped To PORTE */ - PORTCFG_VP0MAP_PORTF_gc = (0x05<<0), /* Mapped To PORTF */ - PORTCFG_VP0MAP_PORTG_gc = (0x06<<0), /* Mapped To PORTG */ - PORTCFG_VP0MAP_PORTH_gc = (0x07<<0), /* Mapped To PORTH */ - PORTCFG_VP0MAP_PORTJ_gc = (0x08<<0), /* Mapped To PORTJ */ - PORTCFG_VP0MAP_PORTK_gc = (0x09<<0), /* Mapped To PORTK */ - PORTCFG_VP0MAP_PORTL_gc = (0x0A<<0), /* Mapped To PORTL */ - PORTCFG_VP0MAP_PORTM_gc = (0x0B<<0), /* Mapped To PORTM */ - PORTCFG_VP0MAP_PORTN_gc = (0x0C<<0), /* Mapped To PORTN */ - PORTCFG_VP0MAP_PORTP_gc = (0x0D<<0), /* Mapped To PORTP */ - PORTCFG_VP0MAP_PORTQ_gc = (0x0E<<0), /* Mapped To PORTQ */ - PORTCFG_VP0MAP_PORTR_gc = (0x0F<<0), /* Mapped To PORTR */ -} PORTCFG_VP0MAP_t; - -/* Virtual Port 1 Mapping */ -typedef enum PORTCFG_VP1MAP_enum -{ - PORTCFG_VP1MAP_PORTA_gc = (0x00<<4), /* Mapped To PORTA */ - PORTCFG_VP1MAP_PORTB_gc = (0x01<<4), /* Mapped To PORTB */ - PORTCFG_VP1MAP_PORTC_gc = (0x02<<4), /* Mapped To PORTC */ - PORTCFG_VP1MAP_PORTD_gc = (0x03<<4), /* Mapped To PORTD */ - PORTCFG_VP1MAP_PORTE_gc = (0x04<<4), /* Mapped To PORTE */ - PORTCFG_VP1MAP_PORTF_gc = (0x05<<4), /* Mapped To PORTF */ - PORTCFG_VP1MAP_PORTG_gc = (0x06<<4), /* Mapped To PORTG */ - PORTCFG_VP1MAP_PORTH_gc = (0x07<<4), /* Mapped To PORTH */ - PORTCFG_VP1MAP_PORTJ_gc = (0x08<<4), /* Mapped To PORTJ */ - PORTCFG_VP1MAP_PORTK_gc = (0x09<<4), /* Mapped To PORTK */ - PORTCFG_VP1MAP_PORTL_gc = (0x0A<<4), /* Mapped To PORTL */ - PORTCFG_VP1MAP_PORTM_gc = (0x0B<<4), /* Mapped To PORTM */ - PORTCFG_VP1MAP_PORTN_gc = (0x0C<<4), /* Mapped To PORTN */ - PORTCFG_VP1MAP_PORTP_gc = (0x0D<<4), /* Mapped To PORTP */ - PORTCFG_VP1MAP_PORTQ_gc = (0x0E<<4), /* Mapped To PORTQ */ - PORTCFG_VP1MAP_PORTR_gc = (0x0F<<4), /* Mapped To PORTR */ -} PORTCFG_VP1MAP_t; - -/* Virtual Port 2 Mapping */ -typedef enum PORTCFG_VP2MAP_enum -{ - PORTCFG_VP2MAP_PORTA_gc = (0x00<<0), /* Mapped To PORTA */ - PORTCFG_VP2MAP_PORTB_gc = (0x01<<0), /* Mapped To PORTB */ - PORTCFG_VP2MAP_PORTC_gc = (0x02<<0), /* Mapped To PORTC */ - PORTCFG_VP2MAP_PORTD_gc = (0x03<<0), /* Mapped To PORTD */ - PORTCFG_VP2MAP_PORTE_gc = (0x04<<0), /* Mapped To PORTE */ - PORTCFG_VP2MAP_PORTF_gc = (0x05<<0), /* Mapped To PORTF */ - PORTCFG_VP2MAP_PORTG_gc = (0x06<<0), /* Mapped To PORTG */ - PORTCFG_VP2MAP_PORTH_gc = (0x07<<0), /* Mapped To PORTH */ - PORTCFG_VP2MAP_PORTJ_gc = (0x08<<0), /* Mapped To PORTJ */ - PORTCFG_VP2MAP_PORTK_gc = (0x09<<0), /* Mapped To PORTK */ - PORTCFG_VP2MAP_PORTL_gc = (0x0A<<0), /* Mapped To PORTL */ - PORTCFG_VP2MAP_PORTM_gc = (0x0B<<0), /* Mapped To PORTM */ - PORTCFG_VP2MAP_PORTN_gc = (0x0C<<0), /* Mapped To PORTN */ - PORTCFG_VP2MAP_PORTP_gc = (0x0D<<0), /* Mapped To PORTP */ - PORTCFG_VP2MAP_PORTQ_gc = (0x0E<<0), /* Mapped To PORTQ */ - PORTCFG_VP2MAP_PORTR_gc = (0x0F<<0), /* Mapped To PORTR */ -} PORTCFG_VP2MAP_t; - -/* Virtual Port 3 Mapping */ -typedef enum PORTCFG_VP3MAP_enum -{ - PORTCFG_VP3MAP_PORTA_gc = (0x00<<4), /* Mapped To PORTA */ - PORTCFG_VP3MAP_PORTB_gc = (0x01<<4), /* Mapped To PORTB */ - PORTCFG_VP3MAP_PORTC_gc = (0x02<<4), /* Mapped To PORTC */ - PORTCFG_VP3MAP_PORTD_gc = (0x03<<4), /* Mapped To PORTD */ - PORTCFG_VP3MAP_PORTE_gc = (0x04<<4), /* Mapped To PORTE */ - PORTCFG_VP3MAP_PORTF_gc = (0x05<<4), /* Mapped To PORTF */ - PORTCFG_VP3MAP_PORTG_gc = (0x06<<4), /* Mapped To PORTG */ - PORTCFG_VP3MAP_PORTH_gc = (0x07<<4), /* Mapped To PORTH */ - PORTCFG_VP3MAP_PORTJ_gc = (0x08<<4), /* Mapped To PORTJ */ - PORTCFG_VP3MAP_PORTK_gc = (0x09<<4), /* Mapped To PORTK */ - PORTCFG_VP3MAP_PORTL_gc = (0x0A<<4), /* Mapped To PORTL */ - PORTCFG_VP3MAP_PORTM_gc = (0x0B<<4), /* Mapped To PORTM */ - PORTCFG_VP3MAP_PORTN_gc = (0x0C<<4), /* Mapped To PORTN */ - PORTCFG_VP3MAP_PORTP_gc = (0x0D<<4), /* Mapped To PORTP */ - PORTCFG_VP3MAP_PORTQ_gc = (0x0E<<4), /* Mapped To PORTQ */ - PORTCFG_VP3MAP_PORTR_gc = (0x0F<<4), /* Mapped To PORTR */ -} PORTCFG_VP3MAP_t; - -/* Clock Output Port */ -typedef enum PORTCFG_CLKOUT_enum -{ - PORTCFG_CLKOUT_OFF_gc = (0x00<<0), /* Clock Output Disabled */ - PORTCFG_CLKOUT_PC7_gc = (0x01<<0), /* Clock Output on Port C pin 7 */ - PORTCFG_CLKOUT_PD7_gc = (0x02<<0), /* Clock Output on Port D pin 7 */ - PORTCFG_CLKOUT_PE7_gc = (0x03<<0), /* Clock Output on Port E pin 7 */ -} PORTCFG_CLKOUT_t; - -/* Event Output Port */ -typedef enum PORTCFG_EVOUT_enum -{ - PORTCFG_EVOUT_OFF_gc = (0x00<<4), /* Event Output Disabled */ - PORTCFG_EVOUT_PC7_gc = (0x01<<4), /* Event Channel 7 Output on Port C pin 7 */ - PORTCFG_EVOUT_PD7_gc = (0x02<<4), /* Event Channel 7 Output on Port D pin 7 */ - PORTCFG_EVOUT_PE7_gc = (0x03<<4), /* Event Channel 7 Output on Port E pin 7 */ -} PORTCFG_EVOUT_t; - -/* Port Interrupt 0 Level */ -typedef enum PORT_INT0LVL_enum -{ - PORT_INT0LVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - PORT_INT0LVL_LO_gc = (0x01<<0), /* Low Level */ - PORT_INT0LVL_MED_gc = (0x02<<0), /* Medium Level */ - PORT_INT0LVL_HI_gc = (0x03<<0), /* High Level */ -} PORT_INT0LVL_t; - -/* Port Interrupt 1 Level */ -typedef enum PORT_INT1LVL_enum -{ - PORT_INT1LVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ - PORT_INT1LVL_LO_gc = (0x01<<2), /* Low Level */ - PORT_INT1LVL_MED_gc = (0x02<<2), /* Medium Level */ - PORT_INT1LVL_HI_gc = (0x03<<2), /* High Level */ -} PORT_INT1LVL_t; - -/* Output/Pull Configuration */ -typedef enum PORT_OPC_enum -{ - PORT_OPC_TOTEM_gc = (0x00<<3), /* Totempole */ - PORT_OPC_BUSKEEPER_gc = (0x01<<3), /* Totempole w/ Bus keeper on Input and Output */ - PORT_OPC_PULLDOWN_gc = (0x02<<3), /* Totempole w/ Pull-down on Input */ - PORT_OPC_PULLUP_gc = (0x03<<3), /* Totempole w/ Pull-up on Input */ - PORT_OPC_WIREDOR_gc = (0x04<<3), /* Wired OR */ - PORT_OPC_WIREDAND_gc = (0x05<<3), /* Wired AND */ - PORT_OPC_WIREDORPULL_gc = (0x06<<3), /* Wired OR w/ Pull-down */ - PORT_OPC_WIREDANDPULL_gc = (0x07<<3), /* Wired AND w/ Pull-up */ -} PORT_OPC_t; - -/* Input/Sense Configuration */ -typedef enum PORT_ISC_enum -{ - PORT_ISC_BOTHEDGES_gc = (0x00<<0), /* Sense Both Edges */ - PORT_ISC_RISING_gc = (0x01<<0), /* Sense Rising Edge */ - PORT_ISC_FALLING_gc = (0x02<<0), /* Sense Falling Edge */ - PORT_ISC_LEVEL_gc = (0x03<<0), /* Sense Level (Transparent For Events) */ - PORT_ISC_INPUT_DISABLE_gc = (0x07<<0), /* Disable Digital Input Buffer */ -} PORT_ISC_t; - - -/* --------------------------------------------------------------------------- -TC - 16-bit Timer/Counter With PWM --------------------------------------------------------------------------- -*/ - -/* 16-bit Timer/Counter 0 */ -typedef struct TC0_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t CTRLC; /* Control register C */ - register8_t CTRLD; /* Control Register D */ - register8_t CTRLE; /* Control Register E */ - register8_t reserved_0x05; - register8_t INTCTRLA; /* Interrupt Control Register A */ - register8_t INTCTRLB; /* Interrupt Control Register B */ - register8_t CTRLFCLR; /* Control Register F Clear */ - register8_t CTRLFSET; /* Control Register F Set */ - register8_t CTRLGCLR; /* Control Register G Clear */ - register8_t CTRLGSET; /* Control Register G Set */ - register8_t INTFLAGS; /* Interrupt Flag Register */ - register8_t reserved_0x0D; - register8_t reserved_0x0E; - register8_t TEMP; /* Temporary Register For 16-bit Access */ - register8_t reserved_0x10; - register8_t reserved_0x11; - register8_t reserved_0x12; - register8_t reserved_0x13; - register8_t reserved_0x14; - register8_t reserved_0x15; - register8_t reserved_0x16; - register8_t reserved_0x17; - register8_t reserved_0x18; - register8_t reserved_0x19; - register8_t reserved_0x1A; - register8_t reserved_0x1B; - register8_t reserved_0x1C; - register8_t reserved_0x1D; - register8_t reserved_0x1E; - register8_t reserved_0x1F; - _WORDREGISTER(CNT); /* Count */ - register8_t reserved_0x22; - register8_t reserved_0x23; - register8_t reserved_0x24; - register8_t reserved_0x25; - _WORDREGISTER(PER); /* Period */ - _WORDREGISTER(CCA); /* Compare or Capture A */ - _WORDREGISTER(CCB); /* Compare or Capture B */ - _WORDREGISTER(CCC); /* Compare or Capture C */ - _WORDREGISTER(CCD); /* Compare or Capture D */ - register8_t reserved_0x30; - register8_t reserved_0x31; - register8_t reserved_0x32; - register8_t reserved_0x33; - register8_t reserved_0x34; - register8_t reserved_0x35; - _WORDREGISTER(PERBUF); /* Period Buffer */ - _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ - _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ - _WORDREGISTER(CCCBUF); /* Compare Or Capture C Buffer */ - _WORDREGISTER(CCDBUF); /* Compare Or Capture D Buffer */ -} TC0_t; - -/* --------------------------------------------------------------------------- -TC - 16-bit Timer/Counter With PWM --------------------------------------------------------------------------- -*/ - -/* 16-bit Timer/Counter 1 */ -typedef struct TC1_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t CTRLC; /* Control register C */ - register8_t CTRLD; /* Control Register D */ - register8_t CTRLE; /* Control Register E */ - register8_t reserved_0x05; - register8_t INTCTRLA; /* Interrupt Control Register A */ - register8_t INTCTRLB; /* Interrupt Control Register B */ - register8_t CTRLFCLR; /* Control Register F Clear */ - register8_t CTRLFSET; /* Control Register F Set */ - register8_t CTRLGCLR; /* Control Register G Clear */ - register8_t CTRLGSET; /* Control Register G Set */ - register8_t INTFLAGS; /* Interrupt Flag Register */ - register8_t reserved_0x0D; - register8_t reserved_0x0E; - register8_t TEMP; /* Temporary Register For 16-bit Access */ - register8_t reserved_0x10; - register8_t reserved_0x11; - register8_t reserved_0x12; - register8_t reserved_0x13; - register8_t reserved_0x14; - register8_t reserved_0x15; - register8_t reserved_0x16; - register8_t reserved_0x17; - register8_t reserved_0x18; - register8_t reserved_0x19; - register8_t reserved_0x1A; - register8_t reserved_0x1B; - register8_t reserved_0x1C; - register8_t reserved_0x1D; - register8_t reserved_0x1E; - register8_t reserved_0x1F; - _WORDREGISTER(CNT); /* Count */ - register8_t reserved_0x22; - register8_t reserved_0x23; - register8_t reserved_0x24; - register8_t reserved_0x25; - _WORDREGISTER(PER); /* Period */ - _WORDREGISTER(CCA); /* Compare or Capture A */ - _WORDREGISTER(CCB); /* Compare or Capture B */ - register8_t reserved_0x2C; - register8_t reserved_0x2D; - register8_t reserved_0x2E; - register8_t reserved_0x2F; - register8_t reserved_0x30; - register8_t reserved_0x31; - register8_t reserved_0x32; - register8_t reserved_0x33; - register8_t reserved_0x34; - register8_t reserved_0x35; - _WORDREGISTER(PERBUF); /* Period Buffer */ - _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ - _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ -} TC1_t; - -/* --------------------------------------------------------------------------- -TC - 16-bit Timer/Counter With PWM --------------------------------------------------------------------------- -*/ - -/* Advanced Waveform Extension */ -typedef struct AWEX_struct -{ - register8_t CTRL; /* Control Register */ - register8_t reserved_0x01; - register8_t FDEMASK; /* Fault Detection Event Mask */ - register8_t FDCTRL; /* Fault Detection Control Register */ - register8_t STATUS; /* Status Register */ - register8_t reserved_0x05; - register8_t DTBOTH; /* Dead Time Both Sides */ - register8_t DTBOTHBUF; /* Dead Time Both Sides Buffer */ - register8_t DTLS; /* Dead Time Low Side */ - register8_t DTHS; /* Dead Time High Side */ - register8_t DTLSBUF; /* Dead Time Low Side Buffer */ - register8_t DTHSBUF; /* Dead Time High Side Buffer */ - register8_t OUTOVEN; /* Output Override Enable */ -} AWEX_t; - -/* --------------------------------------------------------------------------- -TC - 16-bit Timer/Counter With PWM --------------------------------------------------------------------------- -*/ - -/* High-Resolution Extension */ -typedef struct HIRES_struct -{ - register8_t CTRLA; /* Control Register */ -} HIRES_t; - -/* Clock Selection */ -typedef enum TC_CLKSEL_enum -{ - TC_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */ - TC_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */ - TC_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */ - TC_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */ - TC_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */ - TC_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */ - TC_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */ - TC_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */ - TC_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */ - TC_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */ - TC_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */ - TC_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */ - TC_CLKSEL_EVCH4_gc = (0x0C<<0), /* Event Channel 4 */ - TC_CLKSEL_EVCH5_gc = (0x0D<<0), /* Event Channel 5 */ - TC_CLKSEL_EVCH6_gc = (0x0E<<0), /* Event Channel 6 */ - TC_CLKSEL_EVCH7_gc = (0x0F<<0), /* Event Channel 7 */ -} TC_CLKSEL_t; - -/* Waveform Generation Mode */ -typedef enum TC_WGMODE_enum -{ - TC_WGMODE_NORMAL_gc = (0x00<<0), /* Normal Mode */ - TC_WGMODE_FRQ_gc = (0x01<<0), /* Frequency Generation Mode */ - TC_WGMODE_SS_gc = (0x03<<0), /* Single Slope */ - TC_WGMODE_DS_T_gc = (0x05<<0), /* Dual Slope, Update on TOP */ - TC_WGMODE_DS_TB_gc = (0x06<<0), /* Dual Slope, Update on TOP and BOTTOM */ - TC_WGMODE_DS_B_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */ -} TC_WGMODE_t; - -/* Event Action */ -typedef enum TC_EVACT_enum -{ - TC_EVACT_OFF_gc = (0x00<<5), /* No Event Action */ - TC_EVACT_CAPT_gc = (0x01<<5), /* Input Capture */ - TC_EVACT_UPDOWN_gc = (0x02<<5), /* Externally Controlled Up/Down Count */ - TC_EVACT_QDEC_gc = (0x03<<5), /* Quadrature Decode */ - TC_EVACT_RESTART_gc = (0x04<<5), /* Restart */ - TC_EVACT_FRQ_gc = (0x05<<5), /* Frequency Capture */ - TC_EVACT_FRW_gc = (0x05<<5), /* Frequency Capture (typo in earlier header file) */ - TC_EVACT_PW_gc = (0x06<<5), /* Pulse-width Capture */ -} TC_EVACT_t; - -/* Event Selection */ -typedef enum TC_EVSEL_enum -{ - TC_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ - TC_EVSEL_CH0_gc = (0x08<<0), /* Event Channel 0 */ - TC_EVSEL_CH1_gc = (0x09<<0), /* Event Channel 1 */ - TC_EVSEL_CH2_gc = (0x0A<<0), /* Event Channel 2 */ - TC_EVSEL_CH3_gc = (0x0B<<0), /* Event Channel 3 */ - TC_EVSEL_CH4_gc = (0x0C<<0), /* Event Channel 4 */ - TC_EVSEL_CH5_gc = (0x0D<<0), /* Event Channel 5 */ - TC_EVSEL_CH6_gc = (0x0E<<0), /* Event Channel 6 */ - TC_EVSEL_CH7_gc = (0x0F<<0), /* Event Channel 7 */ -} TC_EVSEL_t; - -/* Error Interrupt Level */ -typedef enum TC_ERRINTLVL_enum -{ - TC_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ - TC_ERRINTLVL_LO_gc = (0x01<<2), /* Low Level */ - TC_ERRINTLVL_MED_gc = (0x02<<2), /* Medium Level */ - TC_ERRINTLVL_HI_gc = (0x03<<2), /* High Level */ -} TC_ERRINTLVL_t; - -/* Overflow Interrupt Level */ -typedef enum TC_OVFINTLVL_enum -{ - TC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - TC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ - TC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ - TC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ -} TC_OVFINTLVL_t; - -/* Compare or Capture D Interrupt Level */ -typedef enum TC_CCDINTLVL_enum -{ - TC_CCDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ - TC_CCDINTLVL_LO_gc = (0x01<<6), /* Low Level */ - TC_CCDINTLVL_MED_gc = (0x02<<6), /* Medium Level */ - TC_CCDINTLVL_HI_gc = (0x03<<6), /* High Level */ -} TC_CCDINTLVL_t; - -/* Compare or Capture C Interrupt Level */ -typedef enum TC_CCCINTLVL_enum -{ - TC_CCCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ - TC_CCCINTLVL_LO_gc = (0x01<<4), /* Low Level */ - TC_CCCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ - TC_CCCINTLVL_HI_gc = (0x03<<4), /* High Level */ -} TC_CCCINTLVL_t; - -/* Compare or Capture B Interrupt Level */ -typedef enum TC_CCBINTLVL_enum -{ - TC_CCBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ - TC_CCBINTLVL_LO_gc = (0x01<<2), /* Low Level */ - TC_CCBINTLVL_MED_gc = (0x02<<2), /* Medium Level */ - TC_CCBINTLVL_HI_gc = (0x03<<2), /* High Level */ -} TC_CCBINTLVL_t; - -/* Compare or Capture A Interrupt Level */ -typedef enum TC_CCAINTLVL_enum -{ - TC_CCAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - TC_CCAINTLVL_LO_gc = (0x01<<0), /* Low Level */ - TC_CCAINTLVL_MED_gc = (0x02<<0), /* Medium Level */ - TC_CCAINTLVL_HI_gc = (0x03<<0), /* High Level */ -} TC_CCAINTLVL_t; - -/* Timer/Counter Command */ -typedef enum TC_CMD_enum -{ - TC_CMD_NONE_gc = (0x00<<2), /* No Command */ - TC_CMD_UPDATE_gc = (0x01<<2), /* Force Update */ - TC_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ - TC_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ -} TC_CMD_t; - -/* Fault Detect Action */ -typedef enum AWEX_FDACT_enum -{ - AWEX_FDACT_NONE_gc = (0x00<<0), /* No Fault Protection */ - AWEX_FDACT_CLEAROE_gc = (0x01<<0), /* Clear Output Enable Bits */ - AWEX_FDACT_CLEARDIR_gc = (0x03<<0), /* Clear I/O Port Direction Bits */ -} AWEX_FDACT_t; - -/* High Resolution Enable */ -typedef enum HIRES_HREN_enum -{ - HIRES_HREN_NONE_gc = (0x00<<0), /* No Fault Protection */ - HIRES_HREN_TC0_gc = (0x01<<0), /* Enable High Resolution on Timer/Counter 0 */ - HIRES_HREN_TC1_gc = (0x02<<0), /* Enable High Resolution on Timer/Counter 1 */ - HIRES_HREN_BOTH_gc = (0x03<<0), /* Enable High Resolution both Timer/Counters */ -} HIRES_HREN_t; - - -/* --------------------------------------------------------------------------- -USART - Universal Asynchronous Receiver-Transmitter --------------------------------------------------------------------------- -*/ - -/* Universal Synchronous/Asynchronous Receiver/Transmitter */ -typedef struct USART_struct -{ - register8_t DATA; /* Data Register */ - register8_t STATUS; /* Status Register */ - register8_t reserved_0x02; - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t CTRLC; /* Control Register C */ - register8_t BAUDCTRLA; /* Baud Rate Control Register A */ - register8_t BAUDCTRLB; /* Baud Rate Control Register B */ -} USART_t; - -/* Receive Complete Interrupt level */ -typedef enum USART_RXCINTLVL_enum -{ - USART_RXCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ - USART_RXCINTLVL_LO_gc = (0x01<<4), /* Low Level */ - USART_RXCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ - USART_RXCINTLVL_HI_gc = (0x03<<4), /* High Level */ -} USART_RXCINTLVL_t; - -/* Transmit Complete Interrupt level */ -typedef enum USART_TXCINTLVL_enum -{ - USART_TXCINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ - USART_TXCINTLVL_LO_gc = (0x01<<2), /* Low Level */ - USART_TXCINTLVL_MED_gc = (0x02<<2), /* Medium Level */ - USART_TXCINTLVL_HI_gc = (0x03<<2), /* High Level */ -} USART_TXCINTLVL_t; - -/* Data Register Empty Interrupt level */ -typedef enum USART_DREINTLVL_enum -{ - USART_DREINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - USART_DREINTLVL_LO_gc = (0x01<<0), /* Low Level */ - USART_DREINTLVL_MED_gc = (0x02<<0), /* Medium Level */ - USART_DREINTLVL_HI_gc = (0x03<<0), /* High Level */ -} USART_DREINTLVL_t; - -/* Character Size */ -typedef enum USART_CHSIZE_enum -{ - USART_CHSIZE_5BIT_gc = (0x00<<0), /* Character size: 5 bit */ - USART_CHSIZE_6BIT_gc = (0x01<<0), /* Character size: 6 bit */ - USART_CHSIZE_7BIT_gc = (0x02<<0), /* Character size: 7 bit */ - USART_CHSIZE_8BIT_gc = (0x03<<0), /* Character size: 8 bit */ - USART_CHSIZE_9BIT_gc = (0x07<<0), /* Character size: 9 bit */ -} USART_CHSIZE_t; - -/* Communication Mode */ -typedef enum USART_CMODE_enum -{ - USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6), /* Asynchronous Mode */ - USART_CMODE_SYNCHRONOUS_gc = (0x01<<6), /* Synchronous Mode */ - USART_CMODE_IRDA_gc = (0x02<<6), /* IrDA Mode */ - USART_CMODE_MSPI_gc = (0x03<<6), /* Master SPI Mode */ -} USART_CMODE_t; - -/* Parity Mode */ -typedef enum USART_PMODE_enum -{ - USART_PMODE_DISABLED_gc = (0x00<<4), /* No Parity */ - USART_PMODE_EVEN_gc = (0x02<<4), /* Even Parity */ - USART_PMODE_ODD_gc = (0x03<<4), /* Odd Parity */ -} USART_PMODE_t; - - -/* --------------------------------------------------------------------------- -SPI - Serial Peripheral Interface --------------------------------------------------------------------------- -*/ - -/* Serial Peripheral Interface */ -typedef struct SPI_struct -{ - register8_t CTRL; /* Control Register */ - register8_t INTCTRL; /* Interrupt Control Register */ - register8_t STATUS; /* Status Register */ - register8_t DATA; /* Data Register */ -} SPI_t; - -/* SPI Mode */ -typedef enum SPI_MODE_enum -{ - SPI_MODE_0_gc = (0x00<<2), /* SPI Mode 0 */ - SPI_MODE_1_gc = (0x01<<2), /* SPI Mode 1 */ - SPI_MODE_2_gc = (0x02<<2), /* SPI Mode 2 */ - SPI_MODE_3_gc = (0x03<<2), /* SPI Mode 3 */ -} SPI_MODE_t; - -/* Prescaler setting */ -typedef enum SPI_PRESCALER_enum -{ - SPI_PRESCALER_DIV4_gc = (0x00<<0), /* System Clock / 4 */ - SPI_PRESCALER_DIV16_gc = (0x01<<0), /* System Clock / 16 */ - SPI_PRESCALER_DIV64_gc = (0x02<<0), /* System Clock / 64 */ - SPI_PRESCALER_DIV128_gc = (0x03<<0), /* System Clock / 128 */ -} SPI_PRESCALER_t; - -/* Interrupt level */ -typedef enum SPI_INTLVL_enum -{ - SPI_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - SPI_INTLVL_LO_gc = (0x01<<0), /* Low Level */ - SPI_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ - SPI_INTLVL_HI_gc = (0x03<<0), /* High Level */ -} SPI_INTLVL_t; - - -/* --------------------------------------------------------------------------- -IRCOM - IR Communication Module --------------------------------------------------------------------------- -*/ - -/* IR Communication Module */ -typedef struct IRCOM_struct -{ - register8_t CTRL; /* Control Register */ - register8_t TXPLCTRL; /* IrDA Transmitter Pulse Length Control Register */ - register8_t RXPLCTRL; /* IrDA Receiver Pulse Length Control Register */ -} IRCOM_t; - -/* Event channel selection */ -typedef enum IRDA_EVSEL_enum -{ - IRDA_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ - IRDA_EVSEL_0_gc = (0x08<<0), /* Event Channel 0 */ - IRDA_EVSEL_1_gc = (0x09<<0), /* Event Channel 1 */ - IRDA_EVSEL_2_gc = (0x0A<<0), /* Event Channel 2 */ - IRDA_EVSEL_3_gc = (0x0B<<0), /* Event Channel 3 */ - IRDA_EVSEL_4_gc = (0x0C<<0), /* Event Channel 4 */ - IRDA_EVSEL_5_gc = (0x0D<<0), /* Event Channel 5 */ - IRDA_EVSEL_6_gc = (0x0E<<0), /* Event Channel 6 */ - IRDA_EVSEL_7_gc = (0x0F<<0), /* Event Channel 7 */ -} IRDA_EVSEL_t; - - - -/* -========================================================================== -IO Module Instances. Mapped to memory. -========================================================================== -*/ - -#define VPORT0 (*(VPORT_t *) 0x0010) /* Virtual Port 0 */ -#define VPORT1 (*(VPORT_t *) 0x0014) /* Virtual Port 1 */ -#define VPORT2 (*(VPORT_t *) 0x0018) /* Virtual Port 2 */ -#define VPORT3 (*(VPORT_t *) 0x001C) /* Virtual Port 3 */ -#define OCD (*(OCD_t *) 0x002E) /* On-Chip Debug System */ -#define CLK (*(CLK_t *) 0x0040) /* Clock System */ -#define SLEEP (*(SLEEP_t *) 0x0048) /* Sleep Controller */ -#define OSC (*(OSC_t *) 0x0050) /* Oscillator Control */ -#define DFLLRC32M (*(DFLL_t *) 0x0060) /* DFLL for 32MHz RC Oscillator */ -#define DFLLRC2M (*(DFLL_t *) 0x0068) /* DFLL for 2MHz RC Oscillator */ -#define PR (*(PR_t *) 0x0070) /* Power Reduction */ -#define RST (*(RST_t *) 0x0078) /* Reset Controller */ -#define WDT (*(WDT_t *) 0x0080) /* Watch-Dog Timer */ -#define MCU (*(MCU_t *) 0x0090) /* MCU Control */ -#define PMIC (*(PMIC_t *) 0x00A0) /* Programmable Interrupt Controller */ -#define PORTCFG (*(PORTCFG_t *) 0x00B0) /* Port Configuration */ -#define EVSYS (*(EVSYS_t *) 0x0180) /* Event System */ -#define NVM (*(NVM_t *) 0x01C0) /* Non Volatile Memory Controller */ -#define ADCA (*(ADC_t *) 0x0200) /* Analog to Digital Converter A */ -#define ACA (*(AC_t *) 0x0380) /* Analog Comparator A */ -#define RTC (*(RTC_t *) 0x0400) /* Real-Time Counter */ -#define TWIC (*(TWI_t *) 0x0480) /* Two-Wire Interface C */ -#define TWIE (*(TWI_t *) 0x04A0) /* Two-Wire Interface E */ -#define PORTA (*(PORT_t *) 0x0600) /* Port A */ -#define PORTB (*(PORT_t *) 0x0620) /* Port B */ -#define PORTC (*(PORT_t *) 0x0640) /* Port C */ -#define PORTD (*(PORT_t *) 0x0660) /* Port D */ -#define PORTE (*(PORT_t *) 0x0680) /* Port E */ -#define PORTR (*(PORT_t *) 0x07E0) /* Port R */ -#define TCC0 (*(TC0_t *) 0x0800) /* Timer/Counter C0 */ -#define TCC1 (*(TC1_t *) 0x0840) /* Timer/Counter C1 */ -#define AWEXC (*(AWEX_t *) 0x0880) /* Advanced Waveform Extension C */ -#define HIRESC (*(HIRES_t *) 0x0890) /* High-Resolution Extension C */ -#define USARTC0 (*(USART_t *) 0x08A0) /* Universal Asynchronous Receiver-Transmitter C0 */ -#define SPIC (*(SPI_t *) 0x08C0) /* Serial Peripheral Interface C */ -#define IRCOM (*(IRCOM_t *) 0x08F8) /* IR Communication Module */ -#define TCD0 (*(TC0_t *) 0x0900) /* Timer/Counter D0 */ -#define USARTD0 (*(USART_t *) 0x09A0) /* Universal Asynchronous Receiver-Transmitter D0 */ -#define SPID (*(SPI_t *) 0x09C0) /* Serial Peripheral Interface D */ -#define TCE0 (*(TC0_t *) 0x0A00) /* Timer/Counter E0 */ - - -#endif /* !defined (__ASSEMBLER__) */ - - -/* ========== Flattened fully qualified IO register names ========== */ - -/* GPIO - General Purpose IO Registers */ -#define GPIO_GPIOR0 _SFR_MEM8(0x0000) -#define GPIO_GPIOR1 _SFR_MEM8(0x0001) -#define GPIO_GPIOR2 _SFR_MEM8(0x0002) -#define GPIO_GPIOR3 _SFR_MEM8(0x0003) -#define GPIO_GPIOR4 _SFR_MEM8(0x0004) -#define GPIO_GPIOR5 _SFR_MEM8(0x0005) -#define GPIO_GPIOR6 _SFR_MEM8(0x0006) -#define GPIO_GPIOR7 _SFR_MEM8(0x0007) -#define GPIO_GPIOR8 _SFR_MEM8(0x0008) -#define GPIO_GPIOR9 _SFR_MEM8(0x0009) -#define GPIO_GPIORA _SFR_MEM8(0x000A) -#define GPIO_GPIORB _SFR_MEM8(0x000B) -#define GPIO_GPIORC _SFR_MEM8(0x000C) -#define GPIO_GPIORD _SFR_MEM8(0x000D) -#define GPIO_GPIORE _SFR_MEM8(0x000E) -#define GPIO_GPIORF _SFR_MEM8(0x000F) - -/* Deprecated */ -#define GPIO_GPIO0 _SFR_MEM8(0x0000) -#define GPIO_GPIO1 _SFR_MEM8(0x0001) -#define GPIO_GPIO2 _SFR_MEM8(0x0002) -#define GPIO_GPIO3 _SFR_MEM8(0x0003) -#define GPIO_GPIO4 _SFR_MEM8(0x0004) -#define GPIO_GPIO5 _SFR_MEM8(0x0005) -#define GPIO_GPIO6 _SFR_MEM8(0x0006) -#define GPIO_GPIO7 _SFR_MEM8(0x0007) -#define GPIO_GPIO8 _SFR_MEM8(0x0008) -#define GPIO_GPIO9 _SFR_MEM8(0x0009) -#define GPIO_GPIOA _SFR_MEM8(0x000A) -#define GPIO_GPIOB _SFR_MEM8(0x000B) -#define GPIO_GPIOC _SFR_MEM8(0x000C) -#define GPIO_GPIOD _SFR_MEM8(0x000D) -#define GPIO_GPIOE _SFR_MEM8(0x000E) -#define GPIO_GPIOF _SFR_MEM8(0x000F) - -/* VPORT0 - Virtual Port 0 */ -#define VPORT0_DIR _SFR_MEM8(0x0010) -#define VPORT0_OUT _SFR_MEM8(0x0011) -#define VPORT0_IN _SFR_MEM8(0x0012) -#define VPORT0_INTFLAGS _SFR_MEM8(0x0013) - -/* VPORT1 - Virtual Port 1 */ -#define VPORT1_DIR _SFR_MEM8(0x0014) -#define VPORT1_OUT _SFR_MEM8(0x0015) -#define VPORT1_IN _SFR_MEM8(0x0016) -#define VPORT1_INTFLAGS _SFR_MEM8(0x0017) - -/* VPORT2 - Virtual Port 2 */ -#define VPORT2_DIR _SFR_MEM8(0x0018) -#define VPORT2_OUT _SFR_MEM8(0x0019) -#define VPORT2_IN _SFR_MEM8(0x001A) -#define VPORT2_INTFLAGS _SFR_MEM8(0x001B) - -/* VPORT3 - Virtual Port 3 */ -#define VPORT3_DIR _SFR_MEM8(0x001C) -#define VPORT3_OUT _SFR_MEM8(0x001D) -#define VPORT3_IN _SFR_MEM8(0x001E) -#define VPORT3_INTFLAGS _SFR_MEM8(0x001F) - -/* OCD - On-Chip Debug System */ -#define OCD_OCDR0 _SFR_MEM8(0x002E) -#define OCD_OCDR1 _SFR_MEM8(0x002F) - -/* CPU - CPU Registers */ -#define CPU_CCP _SFR_MEM8(0x0034) -#define CPU_RAMPD _SFR_MEM8(0x0038) -#define CPU_RAMPX _SFR_MEM8(0x0039) -#define CPU_RAMPY _SFR_MEM8(0x003A) -#define CPU_RAMPZ _SFR_MEM8(0x003B) -#define CPU_EIND _SFR_MEM8(0x003C) -#define CPU_SPL _SFR_MEM8(0x003D) -#define CPU_SPH _SFR_MEM8(0x003E) -#define CPU_SREG _SFR_MEM8(0x003F) - -/* CLK - Clock System */ -#define CLK_CTRL _SFR_MEM8(0x0040) -#define CLK_PSCTRL _SFR_MEM8(0x0041) -#define CLK_LOCK _SFR_MEM8(0x0042) -#define CLK_RTCCTRL _SFR_MEM8(0x0043) - -/* SLEEP - Sleep Controller */ -#define SLEEP_CTRL _SFR_MEM8(0x0048) - -/* OSC - Oscillator Control */ -#define OSC_CTRL _SFR_MEM8(0x0050) -#define OSC_STATUS _SFR_MEM8(0x0051) -#define OSC_XOSCCTRL _SFR_MEM8(0x0052) -#define OSC_XOSCFAIL _SFR_MEM8(0x0053) -#define OSC_RC32KCAL _SFR_MEM8(0x0054) -#define OSC_PLLCTRL _SFR_MEM8(0x0055) -#define OSC_DFLLCTRL _SFR_MEM8(0x0056) - -/* DFLLRC32M - DFLL for 32MHz RC Oscillator */ -#define DFLLRC32M_CTRL _SFR_MEM8(0x0060) -#define DFLLRC32M_CALA _SFR_MEM8(0x0062) -#define DFLLRC32M_CALB _SFR_MEM8(0x0063) -#define DFLLRC32M_COMP0 _SFR_MEM8(0x0064) -#define DFLLRC32M_COMP1 _SFR_MEM8(0x0065) -#define DFLLRC32M_COMP2 _SFR_MEM8(0x0066) - -/* DFLLRC2M - DFLL for 2MHz RC Oscillator */ -#define DFLLRC2M_CTRL _SFR_MEM8(0x0068) -#define DFLLRC2M_CALA _SFR_MEM8(0x006A) -#define DFLLRC2M_CALB _SFR_MEM8(0x006B) -#define DFLLRC2M_COMP0 _SFR_MEM8(0x006C) -#define DFLLRC2M_COMP1 _SFR_MEM8(0x006D) -#define DFLLRC2M_COMP2 _SFR_MEM8(0x006E) - -/* PR - Power Reduction */ -#define PR_PRGEN _SFR_MEM8(0x0070) -#define PR_PRPA _SFR_MEM8(0x0071) -#define PR_PRPB _SFR_MEM8(0x0072) -#define PR_PRPC _SFR_MEM8(0x0073) -#define PR_PRPD _SFR_MEM8(0x0074) -#define PR_PRPE _SFR_MEM8(0x0075) -#define PR_PRPF _SFR_MEM8(0x0076) - -/* RST - Reset Controller */ -#define RST_STATUS _SFR_MEM8(0x0078) -#define RST_CTRL _SFR_MEM8(0x0079) - -/* WDT - Watch-Dog Timer */ -#define WDT_CTRL _SFR_MEM8(0x0080) -#define WDT_WINCTRL _SFR_MEM8(0x0081) -#define WDT_STATUS _SFR_MEM8(0x0082) - -/* MCU - MCU Control */ -#define MCU_DEVID0 _SFR_MEM8(0x0090) -#define MCU_DEVID1 _SFR_MEM8(0x0091) -#define MCU_DEVID2 _SFR_MEM8(0x0092) -#define MCU_REVID _SFR_MEM8(0x0093) -#define MCU_JTAGUID _SFR_MEM8(0x0094) -#define MCU_MCUCR _SFR_MEM8(0x0096) -#define MCU_EVSYSLOCK _SFR_MEM8(0x0098) -#define MCU_AWEXLOCK _SFR_MEM8(0x0099) - -/* PMIC - Programmable Interrupt Controller */ -#define PMIC_STATUS _SFR_MEM8(0x00A0) -#define PMIC_INTPRI _SFR_MEM8(0x00A1) -#define PMIC_CTRL _SFR_MEM8(0x00A2) - -/* PORTCFG - Port Configuration */ -#define PORTCFG_MPCMASK _SFR_MEM8(0x00B0) -#define PORTCFG_VPCTRLA _SFR_MEM8(0x00B2) -#define PORTCFG_VPCTRLB _SFR_MEM8(0x00B3) -#define PORTCFG_CLKEVOUT _SFR_MEM8(0x00B4) - -/* EVSYS - Event System */ -#define EVSYS_CH0MUX _SFR_MEM8(0x0180) -#define EVSYS_CH1MUX _SFR_MEM8(0x0181) -#define EVSYS_CH2MUX _SFR_MEM8(0x0182) -#define EVSYS_CH3MUX _SFR_MEM8(0x0183) -#define EVSYS_CH0CTRL _SFR_MEM8(0x0188) -#define EVSYS_CH1CTRL _SFR_MEM8(0x0189) -#define EVSYS_CH2CTRL _SFR_MEM8(0x018A) -#define EVSYS_CH3CTRL _SFR_MEM8(0x018B) -#define EVSYS_STROBE _SFR_MEM8(0x0190) -#define EVSYS_DATA _SFR_MEM8(0x0191) - -/* NVM - Non Volatile Memory Controller */ -#define NVM_ADDR0 _SFR_MEM8(0x01C0) -#define NVM_ADDR1 _SFR_MEM8(0x01C1) -#define NVM_ADDR2 _SFR_MEM8(0x01C2) -#define NVM_DATA0 _SFR_MEM8(0x01C4) -#define NVM_DATA1 _SFR_MEM8(0x01C5) -#define NVM_DATA2 _SFR_MEM8(0x01C6) -#define NVM_CMD _SFR_MEM8(0x01CA) -#define NVM_CTRLA _SFR_MEM8(0x01CB) -#define NVM_CTRLB _SFR_MEM8(0x01CC) -#define NVM_INTCTRL _SFR_MEM8(0x01CD) -#define NVM_STATUS _SFR_MEM8(0x01CF) -#define NVM_LOCKBITS _SFR_MEM8(0x01D0) - -/* ADCA - Analog to Digital Converter A */ -#define ADCA_CTRLA _SFR_MEM8(0x0200) -#define ADCA_CTRLB _SFR_MEM8(0x0201) -#define ADCA_REFCTRL _SFR_MEM8(0x0202) -#define ADCA_EVCTRL _SFR_MEM8(0x0203) -#define ADCA_PRESCALER _SFR_MEM8(0x0204) -#define ADCA_INTFLAGS _SFR_MEM8(0x0206) -#define ADCA_CAL _SFR_MEM16(0x020C) -#define ADCA_CH0RES _SFR_MEM16(0x0210) -#define ADCA_CMP _SFR_MEM16(0x0218) -#define ADCA_CH0_CTRL _SFR_MEM8(0x0220) -#define ADCA_CH0_MUXCTRL _SFR_MEM8(0x0221) -#define ADCA_CH0_INTCTRL _SFR_MEM8(0x0222) -#define ADCA_CH0_INTFLAGS _SFR_MEM8(0x0223) -#define ADCA_CH0_RES _SFR_MEM16(0x0224) - -/* ACA - Analog Comparator A */ -#define ACA_AC0CTRL _SFR_MEM8(0x0380) -#define ACA_AC1CTRL _SFR_MEM8(0x0381) -#define ACA_AC0MUXCTRL _SFR_MEM8(0x0382) -#define ACA_AC1MUXCTRL _SFR_MEM8(0x0383) -#define ACA_CTRLA _SFR_MEM8(0x0384) -#define ACA_CTRLB _SFR_MEM8(0x0385) -#define ACA_WINCTRL _SFR_MEM8(0x0386) -#define ACA_STATUS _SFR_MEM8(0x0387) - -/* RTC - Real-Time Counter */ -#define RTC_CTRL _SFR_MEM8(0x0400) -#define RTC_STATUS _SFR_MEM8(0x0401) -#define RTC_INTCTRL _SFR_MEM8(0x0402) -#define RTC_INTFLAGS _SFR_MEM8(0x0403) -#define RTC_TEMP _SFR_MEM8(0x0404) -#define RTC_CNT _SFR_MEM16(0x0408) -#define RTC_PER _SFR_MEM16(0x040A) -#define RTC_COMP _SFR_MEM16(0x040C) - -/* TWIC - Two-Wire Interface C */ -#define TWIC_CTRL _SFR_MEM8(0x0480) -#define TWIC_MASTER_CTRLA _SFR_MEM8(0x0481) -#define TWIC_MASTER_CTRLB _SFR_MEM8(0x0482) -#define TWIC_MASTER_CTRLC _SFR_MEM8(0x0483) -#define TWIC_MASTER_STATUS _SFR_MEM8(0x0484) -#define TWIC_MASTER_BAUD _SFR_MEM8(0x0485) -#define TWIC_MASTER_ADDR _SFR_MEM8(0x0486) -#define TWIC_MASTER_DATA _SFR_MEM8(0x0487) -#define TWIC_SLAVE_CTRLA _SFR_MEM8(0x0488) -#define TWIC_SLAVE_CTRLB _SFR_MEM8(0x0489) -#define TWIC_SLAVE_STATUS _SFR_MEM8(0x048A) -#define TWIC_SLAVE_ADDR _SFR_MEM8(0x048B) -#define TWIC_SLAVE_DATA _SFR_MEM8(0x048C) -#define TWIC_SLAVE_ADDRMASK _SFR_MEM8(0x048D) - -/* TWIE - Two-Wire Interface E */ -#define TWIE_CTRL _SFR_MEM8(0x04A0) -#define TWIE_MASTER_CTRLA _SFR_MEM8(0x04A1) -#define TWIE_MASTER_CTRLB _SFR_MEM8(0x04A2) -#define TWIE_MASTER_CTRLC _SFR_MEM8(0x04A3) -#define TWIE_MASTER_STATUS _SFR_MEM8(0x04A4) -#define TWIE_MASTER_BAUD _SFR_MEM8(0x04A5) -#define TWIE_MASTER_ADDR _SFR_MEM8(0x04A6) -#define TWIE_MASTER_DATA _SFR_MEM8(0x04A7) -#define TWIE_SLAVE_CTRLA _SFR_MEM8(0x04A8) -#define TWIE_SLAVE_CTRLB _SFR_MEM8(0x04A9) -#define TWIE_SLAVE_STATUS _SFR_MEM8(0x04AA) -#define TWIE_SLAVE_ADDR _SFR_MEM8(0x04AB) -#define TWIE_SLAVE_DATA _SFR_MEM8(0x04AC) -#define TWIE_SLAVE_ADDRMASK _SFR_MEM8(0x04AD) - - -/* PORTA - Port A */ -#define PORTA_DIR _SFR_MEM8(0x0600) -#define PORTA_DIRSET _SFR_MEM8(0x0601) -#define PORTA_DIRCLR _SFR_MEM8(0x0602) -#define PORTA_DIRTGL _SFR_MEM8(0x0603) -#define PORTA_OUT _SFR_MEM8(0x0604) -#define PORTA_OUTSET _SFR_MEM8(0x0605) -#define PORTA_OUTCLR _SFR_MEM8(0x0606) -#define PORTA_OUTTGL _SFR_MEM8(0x0607) -#define PORTA_IN _SFR_MEM8(0x0608) -#define PORTA_INTCTRL _SFR_MEM8(0x0609) -#define PORTA_INT0MASK _SFR_MEM8(0x060A) -#define PORTA_INT1MASK _SFR_MEM8(0x060B) -#define PORTA_INTFLAGS _SFR_MEM8(0x060C) -#define PORTA_PIN0CTRL _SFR_MEM8(0x0610) -#define PORTA_PIN1CTRL _SFR_MEM8(0x0611) -#define PORTA_PIN2CTRL _SFR_MEM8(0x0612) -#define PORTA_PIN3CTRL _SFR_MEM8(0x0613) -#define PORTA_PIN4CTRL _SFR_MEM8(0x0614) -#define PORTA_PIN5CTRL _SFR_MEM8(0x0615) -#define PORTA_PIN6CTRL _SFR_MEM8(0x0616) -#define PORTA_PIN7CTRL _SFR_MEM8(0x0617) - -/* PORTB - Port B */ -#define PORTB_DIR _SFR_MEM8(0x0620) -#define PORTB_DIRSET _SFR_MEM8(0x0621) -#define PORTB_DIRCLR _SFR_MEM8(0x0622) -#define PORTB_DIRTGL _SFR_MEM8(0x0623) -#define PORTB_OUT _SFR_MEM8(0x0624) -#define PORTB_OUTSET _SFR_MEM8(0x0625) -#define PORTB_OUTCLR _SFR_MEM8(0x0626) -#define PORTB_OUTTGL _SFR_MEM8(0x0627) -#define PORTB_IN _SFR_MEM8(0x0628) -#define PORTB_INTCTRL _SFR_MEM8(0x0629) -#define PORTB_INT0MASK _SFR_MEM8(0x062A) -#define PORTB_INT1MASK _SFR_MEM8(0x062B) -#define PORTB_INTFLAGS _SFR_MEM8(0x062C) -#define PORTB_PIN0CTRL _SFR_MEM8(0x0630) -#define PORTB_PIN1CTRL _SFR_MEM8(0x0631) -#define PORTB_PIN2CTRL _SFR_MEM8(0x0632) -#define PORTB_PIN3CTRL _SFR_MEM8(0x0633) -#define PORTB_PIN4CTRL _SFR_MEM8(0x0634) -#define PORTB_PIN5CTRL _SFR_MEM8(0x0635) -#define PORTB_PIN6CTRL _SFR_MEM8(0x0636) -#define PORTB_PIN7CTRL _SFR_MEM8(0x0637) - -/* PORTC - Port C */ -#define PORTC_DIR _SFR_MEM8(0x0640) -#define PORTC_DIRSET _SFR_MEM8(0x0641) -#define PORTC_DIRCLR _SFR_MEM8(0x0642) -#define PORTC_DIRTGL _SFR_MEM8(0x0643) -#define PORTC_OUT _SFR_MEM8(0x0644) -#define PORTC_OUTSET _SFR_MEM8(0x0645) -#define PORTC_OUTCLR _SFR_MEM8(0x0646) -#define PORTC_OUTTGL _SFR_MEM8(0x0647) -#define PORTC_IN _SFR_MEM8(0x0648) -#define PORTC_INTCTRL _SFR_MEM8(0x0649) -#define PORTC_INT0MASK _SFR_MEM8(0x064A) -#define PORTC_INT1MASK _SFR_MEM8(0x064B) -#define PORTC_INTFLAGS _SFR_MEM8(0x064C) -#define PORTC_PIN0CTRL _SFR_MEM8(0x0650) -#define PORTC_PIN1CTRL _SFR_MEM8(0x0651) -#define PORTC_PIN2CTRL _SFR_MEM8(0x0652) -#define PORTC_PIN3CTRL _SFR_MEM8(0x0653) -#define PORTC_PIN4CTRL _SFR_MEM8(0x0654) -#define PORTC_PIN5CTRL _SFR_MEM8(0x0655) -#define PORTC_PIN6CTRL _SFR_MEM8(0x0656) -#define PORTC_PIN7CTRL _SFR_MEM8(0x0657) - -/* PORTD - Port D */ -#define PORTD_DIR _SFR_MEM8(0x0660) -#define PORTD_DIRSET _SFR_MEM8(0x0661) -#define PORTD_DIRCLR _SFR_MEM8(0x0662) -#define PORTD_DIRTGL _SFR_MEM8(0x0663) -#define PORTD_OUT _SFR_MEM8(0x0664) -#define PORTD_OUTSET _SFR_MEM8(0x0665) -#define PORTD_OUTCLR _SFR_MEM8(0x0666) -#define PORTD_OUTTGL _SFR_MEM8(0x0667) -#define PORTD_IN _SFR_MEM8(0x0668) -#define PORTD_INTCTRL _SFR_MEM8(0x0669) -#define PORTD_INT0MASK _SFR_MEM8(0x066A) -#define PORTD_INT1MASK _SFR_MEM8(0x066B) -#define PORTD_INTFLAGS _SFR_MEM8(0x066C) -#define PORTD_PIN0CTRL _SFR_MEM8(0x0670) -#define PORTD_PIN1CTRL _SFR_MEM8(0x0671) -#define PORTD_PIN2CTRL _SFR_MEM8(0x0672) -#define PORTD_PIN3CTRL _SFR_MEM8(0x0673) -#define PORTD_PIN4CTRL _SFR_MEM8(0x0674) -#define PORTD_PIN5CTRL _SFR_MEM8(0x0675) -#define PORTD_PIN6CTRL _SFR_MEM8(0x0676) -#define PORTD_PIN7CTRL _SFR_MEM8(0x0677) - -/* PORTE - Port E */ -#define PORTE_DIR _SFR_MEM8(0x0680) -#define PORTE_DIRSET _SFR_MEM8(0x0681) -#define PORTE_DIRCLR _SFR_MEM8(0x0682) -#define PORTE_DIRTGL _SFR_MEM8(0x0683) -#define PORTE_OUT _SFR_MEM8(0x0684) -#define PORTE_OUTSET _SFR_MEM8(0x0685) -#define PORTE_OUTCLR _SFR_MEM8(0x0686) -#define PORTE_OUTTGL _SFR_MEM8(0x0687) -#define PORTE_IN _SFR_MEM8(0x0688) -#define PORTE_INTCTRL _SFR_MEM8(0x0689) -#define PORTE_INT0MASK _SFR_MEM8(0x068A) -#define PORTE_INT1MASK _SFR_MEM8(0x068B) -#define PORTE_INTFLAGS _SFR_MEM8(0x068C) -#define PORTE_PIN0CTRL _SFR_MEM8(0x0690) -#define PORTE_PIN1CTRL _SFR_MEM8(0x0691) -#define PORTE_PIN2CTRL _SFR_MEM8(0x0692) -#define PORTE_PIN3CTRL _SFR_MEM8(0x0693) -#define PORTE_PIN4CTRL _SFR_MEM8(0x0694) -#define PORTE_PIN5CTRL _SFR_MEM8(0x0695) -#define PORTE_PIN6CTRL _SFR_MEM8(0x0696) -#define PORTE_PIN7CTRL _SFR_MEM8(0x0697) - -/* PORTR - Port R */ -#define PORTR_DIR _SFR_MEM8(0x07E0) -#define PORTR_DIRSET _SFR_MEM8(0x07E1) -#define PORTR_DIRCLR _SFR_MEM8(0x07E2) -#define PORTR_DIRTGL _SFR_MEM8(0x07E3) -#define PORTR_OUT _SFR_MEM8(0x07E4) -#define PORTR_OUTSET _SFR_MEM8(0x07E5) -#define PORTR_OUTCLR _SFR_MEM8(0x07E6) -#define PORTR_OUTTGL _SFR_MEM8(0x07E7) -#define PORTR_IN _SFR_MEM8(0x07E8) -#define PORTR_INTCTRL _SFR_MEM8(0x07E9) -#define PORTR_INT0MASK _SFR_MEM8(0x07EA) -#define PORTR_INT1MASK _SFR_MEM8(0x07EB) -#define PORTR_INTFLAGS _SFR_MEM8(0x07EC) -#define PORTR_PIN0CTRL _SFR_MEM8(0x07F0) -#define PORTR_PIN1CTRL _SFR_MEM8(0x07F1) -#define PORTR_PIN2CTRL _SFR_MEM8(0x07F2) -#define PORTR_PIN3CTRL _SFR_MEM8(0x07F3) -#define PORTR_PIN4CTRL _SFR_MEM8(0x07F4) -#define PORTR_PIN5CTRL _SFR_MEM8(0x07F5) -#define PORTR_PIN6CTRL _SFR_MEM8(0x07F6) -#define PORTR_PIN7CTRL _SFR_MEM8(0x07F7) - -/* TCC0 - Timer/Counter C0 */ -#define TCC0_CTRLA _SFR_MEM8(0x0800) -#define TCC0_CTRLB _SFR_MEM8(0x0801) -#define TCC0_CTRLC _SFR_MEM8(0x0802) -#define TCC0_CTRLD _SFR_MEM8(0x0803) -#define TCC0_CTRLE _SFR_MEM8(0x0804) -#define TCC0_INTCTRLA _SFR_MEM8(0x0806) -#define TCC0_INTCTRLB _SFR_MEM8(0x0807) -#define TCC0_CTRLFCLR _SFR_MEM8(0x0808) -#define TCC0_CTRLFSET _SFR_MEM8(0x0809) -#define TCC0_CTRLGCLR _SFR_MEM8(0x080A) -#define TCC0_CTRLGSET _SFR_MEM8(0x080B) -#define TCC0_INTFLAGS _SFR_MEM8(0x080C) -#define TCC0_TEMP _SFR_MEM8(0x080F) -#define TCC0_CNT _SFR_MEM16(0x0820) -#define TCC0_PER _SFR_MEM16(0x0826) -#define TCC0_CCA _SFR_MEM16(0x0828) -#define TCC0_CCB _SFR_MEM16(0x082A) -#define TCC0_CCC _SFR_MEM16(0x082C) -#define TCC0_CCD _SFR_MEM16(0x082E) -#define TCC0_PERBUF _SFR_MEM16(0x0836) -#define TCC0_CCABUF _SFR_MEM16(0x0838) -#define TCC0_CCBBUF _SFR_MEM16(0x083A) -#define TCC0_CCCBUF _SFR_MEM16(0x083C) -#define TCC0_CCDBUF _SFR_MEM16(0x083E) - -/* TCC1 - Timer/Counter C1 */ -#define TCC1_CTRLA _SFR_MEM8(0x0840) -#define TCC1_CTRLB _SFR_MEM8(0x0841) -#define TCC1_CTRLC _SFR_MEM8(0x0842) -#define TCC1_CTRLD _SFR_MEM8(0x0843) -#define TCC1_CTRLE _SFR_MEM8(0x0844) -#define TCC1_INTCTRLA _SFR_MEM8(0x0846) -#define TCC1_INTCTRLB _SFR_MEM8(0x0847) -#define TCC1_CTRLFCLR _SFR_MEM8(0x0848) -#define TCC1_CTRLFSET _SFR_MEM8(0x0849) -#define TCC1_CTRLGCLR _SFR_MEM8(0x084A) -#define TCC1_CTRLGSET _SFR_MEM8(0x084B) -#define TCC1_INTFLAGS _SFR_MEM8(0x084C) -#define TCC1_TEMP _SFR_MEM8(0x084F) -#define TCC1_CNT _SFR_MEM16(0x0860) -#define TCC1_PER _SFR_MEM16(0x0866) -#define TCC1_CCA _SFR_MEM16(0x0868) -#define TCC1_CCB _SFR_MEM16(0x086A) -#define TCC1_PERBUF _SFR_MEM16(0x0876) -#define TCC1_CCABUF _SFR_MEM16(0x0878) -#define TCC1_CCBBUF _SFR_MEM16(0x087A) - -/* AWEXC - Advanced Waveform Extension C */ -#define AWEXC_CTRL _SFR_MEM8(0x0880) -#define AWEXC_FDEMASK _SFR_MEM8(0x0882) -#define AWEXC_FDCTRL _SFR_MEM8(0x0883) -#define AWEXC_STATUS _SFR_MEM8(0x0884) -#define AWEXC_DTBOTH _SFR_MEM8(0x0886) -#define AWEXC_DTBOTHBUF _SFR_MEM8(0x0887) -#define AWEXC_DTLS _SFR_MEM8(0x0888) -#define AWEXC_DTHS _SFR_MEM8(0x0889) -#define AWEXC_DTLSBUF _SFR_MEM8(0x088A) -#define AWEXC_DTHSBUF _SFR_MEM8(0x088B) -#define AWEXC_OUTOVEN _SFR_MEM8(0x088C) - -/* HIRESC - High-Resolution Extension C */ -#define HIRESC_CTRLA _SFR_MEM8(0x0890) - -/* USARTC0 - Universal Asynchronous Receiver-Transmitter C0 */ -#define USARTC0_DATA _SFR_MEM8(0x08A0) -#define USARTC0_STATUS _SFR_MEM8(0x08A1) -#define USARTC0_CTRLA _SFR_MEM8(0x08A3) -#define USARTC0_CTRLB _SFR_MEM8(0x08A4) -#define USARTC0_CTRLC _SFR_MEM8(0x08A5) -#define USARTC0_BAUDCTRLA _SFR_MEM8(0x08A6) -#define USARTC0_BAUDCTRLB _SFR_MEM8(0x08A7) - -/* SPIC - Serial Peripheral Interface C */ -#define SPIC_CTRL _SFR_MEM8(0x08C0) -#define SPIC_INTCTRL _SFR_MEM8(0x08C1) -#define SPIC_STATUS _SFR_MEM8(0x08C2) -#define SPIC_DATA _SFR_MEM8(0x08C3) - -/* IRCOM - IR Communication Module */ -#define IRCOM_CTRL _SFR_MEM8(0x08F8) -#define IRCOM_TXPLCTRL _SFR_MEM8(0x08F9) -#define IRCOM_RXPLCTRL _SFR_MEM8(0x08FA) - -/* TCD0 - Timer/Counter D0 */ -#define TCD0_CTRLA _SFR_MEM8(0x0900) -#define TCD0_CTRLB _SFR_MEM8(0x0901) -#define TCD0_CTRLC _SFR_MEM8(0x0902) -#define TCD0_CTRLD _SFR_MEM8(0x0903) -#define TCD0_CTRLE _SFR_MEM8(0x0904) -#define TCD0_INTCTRLA _SFR_MEM8(0x0906) -#define TCD0_INTCTRLB _SFR_MEM8(0x0907) -#define TCD0_CTRLFCLR _SFR_MEM8(0x0908) -#define TCD0_CTRLFSET _SFR_MEM8(0x0909) -#define TCD0_CTRLGCLR _SFR_MEM8(0x090A) -#define TCD0_CTRLGSET _SFR_MEM8(0x090B) -#define TCD0_INTFLAGS _SFR_MEM8(0x090C) -#define TCD0_TEMP _SFR_MEM8(0x090F) -#define TCD0_CNT _SFR_MEM16(0x0920) -#define TCD0_PER _SFR_MEM16(0x0926) -#define TCD0_CCA _SFR_MEM16(0x0928) -#define TCD0_CCB _SFR_MEM16(0x092A) -#define TCD0_CCC _SFR_MEM16(0x092C) -#define TCD0_CCD _SFR_MEM16(0x092E) -#define TCD0_PERBUF _SFR_MEM16(0x0936) -#define TCD0_CCABUF _SFR_MEM16(0x0938) -#define TCD0_CCBBUF _SFR_MEM16(0x093A) -#define TCD0_CCCBUF _SFR_MEM16(0x093C) -#define TCD0_CCDBUF _SFR_MEM16(0x093E) - -/* USARTD0 - Universal Asynchronous Receiver-Transmitter D0 */ -#define USARTD0_DATA _SFR_MEM8(0x09A0) -#define USARTD0_STATUS _SFR_MEM8(0x09A1) -#define USARTD0_CTRLA _SFR_MEM8(0x09A3) -#define USARTD0_CTRLB _SFR_MEM8(0x09A4) -#define USARTD0_CTRLC _SFR_MEM8(0x09A5) -#define USARTD0_BAUDCTRLA _SFR_MEM8(0x09A6) -#define USARTD0_BAUDCTRLB _SFR_MEM8(0x09A7) - -/* SPID - Serial Peripheral Interface D */ -#define SPID_CTRL _SFR_MEM8(0x09C0) -#define SPID_INTCTRL _SFR_MEM8(0x09C1) -#define SPID_STATUS _SFR_MEM8(0x09C2) -#define SPID_DATA _SFR_MEM8(0x09C3) - -/* TCE0 - Timer/Counter E0 */ -#define TCE0_CTRLA _SFR_MEM8(0x0A00) -#define TCE0_CTRLB _SFR_MEM8(0x0A01) -#define TCE0_CTRLC _SFR_MEM8(0x0A02) -#define TCE0_CTRLD _SFR_MEM8(0x0A03) -#define TCE0_CTRLE _SFR_MEM8(0x0A04) -#define TCE0_INTCTRLA _SFR_MEM8(0x0A06) -#define TCE0_INTCTRLB _SFR_MEM8(0x0A07) -#define TCE0_CTRLFCLR _SFR_MEM8(0x0A08) -#define TCE0_CTRLFSET _SFR_MEM8(0x0A09) -#define TCE0_CTRLGCLR _SFR_MEM8(0x0A0A) -#define TCE0_CTRLGSET _SFR_MEM8(0x0A0B) -#define TCE0_INTFLAGS _SFR_MEM8(0x0A0C) -#define TCE0_TEMP _SFR_MEM8(0x0A0F) -#define TCE0_CNT _SFR_MEM16(0x0A20) -#define TCE0_PER _SFR_MEM16(0x0A26) -#define TCE0_CCA _SFR_MEM16(0x0A28) -#define TCE0_CCB _SFR_MEM16(0x0A2A) -#define TCE0_CCC _SFR_MEM16(0x0A2C) -#define TCE0_CCD _SFR_MEM16(0x0A2E) -#define TCE0_PERBUF _SFR_MEM16(0x0A36) -#define TCE0_CCABUF _SFR_MEM16(0x0A38) -#define TCE0_CCBBUF _SFR_MEM16(0x0A3A) -#define TCE0_CCCBUF _SFR_MEM16(0x0A3C) -#define TCE0_CCDBUF _SFR_MEM16(0x0A3E) - - - -/*================== Bitfield Definitions ================== */ - -/* XOCD - On-Chip Debug System */ -/* OCD.OCDR1 bit masks and bit positions */ -#define OCD_OCDRD_bm 0x01 /* OCDR Dirty bit mask. */ -#define OCD_OCDRD_bp 0 /* OCDR Dirty bit position. */ - - -/* CPU - CPU */ -/* CPU.CCP bit masks and bit positions */ -#define CPU_CCP_gm 0xFF /* CCP signature group mask. */ -#define CPU_CCP_gp 0 /* CCP signature group position. */ -#define CPU_CCP0_bm (1<<0) /* CCP signature bit 0 mask. */ -#define CPU_CCP0_bp 0 /* CCP signature bit 0 position. */ -#define CPU_CCP1_bm (1<<1) /* CCP signature bit 1 mask. */ -#define CPU_CCP1_bp 1 /* CCP signature bit 1 position. */ -#define CPU_CCP2_bm (1<<2) /* CCP signature bit 2 mask. */ -#define CPU_CCP2_bp 2 /* CCP signature bit 2 position. */ -#define CPU_CCP3_bm (1<<3) /* CCP signature bit 3 mask. */ -#define CPU_CCP3_bp 3 /* CCP signature bit 3 position. */ -#define CPU_CCP4_bm (1<<4) /* CCP signature bit 4 mask. */ -#define CPU_CCP4_bp 4 /* CCP signature bit 4 position. */ -#define CPU_CCP5_bm (1<<5) /* CCP signature bit 5 mask. */ -#define CPU_CCP5_bp 5 /* CCP signature bit 5 position. */ -#define CPU_CCP6_bm (1<<6) /* CCP signature bit 6 mask. */ -#define CPU_CCP6_bp 6 /* CCP signature bit 6 position. */ -#define CPU_CCP7_bm (1<<7) /* CCP signature bit 7 mask. */ -#define CPU_CCP7_bp 7 /* CCP signature bit 7 position. */ - - -/* CPU.SREG bit masks and bit positions */ -#define CPU_I_bm 0x80 /* Global Interrupt Enable Flag bit mask. */ -#define CPU_I_bp 7 /* Global Interrupt Enable Flag bit position. */ - -#define CPU_T_bm 0x40 /* Transfer Bit bit mask. */ -#define CPU_T_bp 6 /* Transfer Bit bit position. */ - -#define CPU_H_bm 0x20 /* Half Carry Flag bit mask. */ -#define CPU_H_bp 5 /* Half Carry Flag bit position. */ - -#define CPU_S_bm 0x10 /* N Exclusive Or V Flag bit mask. */ -#define CPU_S_bp 4 /* N Exclusive Or V Flag bit position. */ - -#define CPU_V_bm 0x08 /* Two's Complement Overflow Flag bit mask. */ -#define CPU_V_bp 3 /* Two's Complement Overflow Flag bit position. */ - -#define CPU_N_bm 0x04 /* Negative Flag bit mask. */ -#define CPU_N_bp 2 /* Negative Flag bit position. */ - -#define CPU_Z_bm 0x02 /* Zero Flag bit mask. */ -#define CPU_Z_bp 1 /* Zero Flag bit position. */ - -#define CPU_C_bm 0x01 /* Carry Flag bit mask. */ -#define CPU_C_bp 0 /* Carry Flag bit position. */ - - -/* CLK - Clock System */ -/* CLK.CTRL bit masks and bit positions */ -#define CLK_SCLKSEL_gm 0x07 /* System Clock Selection group mask. */ -#define CLK_SCLKSEL_gp 0 /* System Clock Selection group position. */ -#define CLK_SCLKSEL0_bm (1<<0) /* System Clock Selection bit 0 mask. */ -#define CLK_SCLKSEL0_bp 0 /* System Clock Selection bit 0 position. */ -#define CLK_SCLKSEL1_bm (1<<1) /* System Clock Selection bit 1 mask. */ -#define CLK_SCLKSEL1_bp 1 /* System Clock Selection bit 1 position. */ -#define CLK_SCLKSEL2_bm (1<<2) /* System Clock Selection bit 2 mask. */ -#define CLK_SCLKSEL2_bp 2 /* System Clock Selection bit 2 position. */ - - -/* CLK.PSCTRL bit masks and bit positions */ -#define CLK_PSADIV_gm 0x7C /* Prescaler A Division Factor group mask. */ -#define CLK_PSADIV_gp 2 /* Prescaler A Division Factor group position. */ -#define CLK_PSADIV0_bm (1<<2) /* Prescaler A Division Factor bit 0 mask. */ -#define CLK_PSADIV0_bp 2 /* Prescaler A Division Factor bit 0 position. */ -#define CLK_PSADIV1_bm (1<<3) /* Prescaler A Division Factor bit 1 mask. */ -#define CLK_PSADIV1_bp 3 /* Prescaler A Division Factor bit 1 position. */ -#define CLK_PSADIV2_bm (1<<4) /* Prescaler A Division Factor bit 2 mask. */ -#define CLK_PSADIV2_bp 4 /* Prescaler A Division Factor bit 2 position. */ -#define CLK_PSADIV3_bm (1<<5) /* Prescaler A Division Factor bit 3 mask. */ -#define CLK_PSADIV3_bp 5 /* Prescaler A Division Factor bit 3 position. */ -#define CLK_PSADIV4_bm (1<<6) /* Prescaler A Division Factor bit 4 mask. */ -#define CLK_PSADIV4_bp 6 /* Prescaler A Division Factor bit 4 position. */ - -#define CLK_PSBCDIV_gm 0x03 /* Prescaler B and C Division factor group mask. */ -#define CLK_PSBCDIV_gp 0 /* Prescaler B and C Division factor group position. */ -#define CLK_PSBCDIV0_bm (1<<0) /* Prescaler B and C Division factor bit 0 mask. */ -#define CLK_PSBCDIV0_bp 0 /* Prescaler B and C Division factor bit 0 position. */ -#define CLK_PSBCDIV1_bm (1<<1) /* Prescaler B and C Division factor bit 1 mask. */ -#define CLK_PSBCDIV1_bp 1 /* Prescaler B and C Division factor bit 1 position. */ - - -/* CLK.LOCK bit masks and bit positions */ -#define CLK_LOCK_bm 0x01 /* Clock System Lock bit mask. */ -#define CLK_LOCK_bp 0 /* Clock System Lock bit position. */ - - -/* CLK.RTCCTRL bit masks and bit positions */ -#define CLK_RTCSRC_gm 0x0E /* Clock Source group mask. */ -#define CLK_RTCSRC_gp 1 /* Clock Source group position. */ -#define CLK_RTCSRC0_bm (1<<1) /* Clock Source bit 0 mask. */ -#define CLK_RTCSRC0_bp 1 /* Clock Source bit 0 position. */ -#define CLK_RTCSRC1_bm (1<<2) /* Clock Source bit 1 mask. */ -#define CLK_RTCSRC1_bp 2 /* Clock Source bit 1 position. */ -#define CLK_RTCSRC2_bm (1<<3) /* Clock Source bit 2 mask. */ -#define CLK_RTCSRC2_bp 3 /* Clock Source bit 2 position. */ - -#define CLK_RTCEN_bm 0x01 /* RTC Clock Source Enable bit mask. */ -#define CLK_RTCEN_bp 0 /* RTC Clock Source Enable bit position. */ - - -/* PR.PRGEN bit masks and bit positions */ -#define PR_AES_bm 0x10 /* AES bit mask. */ -#define PR_AES_bp 4 /* AES bit position. */ - -#define PR_EBI_bm 0x08 /* External Bus Interface bit mask. */ -#define PR_EBI_bp 3 /* External Bus Interface bit position. */ - -#define PR_RTC_bm 0x04 /* Real-time Counter bit mask. */ -#define PR_RTC_bp 2 /* Real-time Counter bit position. */ - -#define PR_EVSYS_bm 0x02 /* Event System bit mask. */ -#define PR_EVSYS_bp 1 /* Event System bit position. */ - -#define PR_DMA_bm 0x01 /* DMA-Controller bit mask. */ -#define PR_DMA_bp 0 /* DMA-Controller bit position. */ - - -/* PR.PRPA bit masks and bit positions */ -#define PR_DAC_bm 0x04 /* Port A DAC bit mask. */ -#define PR_DAC_bp 2 /* Port A DAC bit position. */ - -#define PR_ADC_bm 0x02 /* Port A ADC bit mask. */ -#define PR_ADC_bp 1 /* Port A ADC bit position. */ - -#define PR_AC_bm 0x01 /* Port A Analog Comparator bit mask. */ -#define PR_AC_bp 0 /* Port A Analog Comparator bit position. */ - - -/* PR.PRPB bit masks and bit positions */ -/* PR_DAC_bm Predefined. */ -/* PR_DAC_bp Predefined. */ - -/* PR_ADC_bm Predefined. */ -/* PR_ADC_bp Predefined. */ - -/* PR_AC_bm Predefined. */ -/* PR_AC_bp Predefined. */ - - -/* PR.PRPC bit masks and bit positions */ -#define PR_TWI_bm 0x40 /* Port C Two-wire Interface bit mask. */ -#define PR_TWI_bp 6 /* Port C Two-wire Interface bit position. */ - -#define PR_USART1_bm 0x20 /* Port C USART1 bit mask. */ -#define PR_USART1_bp 5 /* Port C USART1 bit position. */ - -#define PR_USART0_bm 0x10 /* Port C USART0 bit mask. */ -#define PR_USART0_bp 4 /* Port C USART0 bit position. */ - -#define PR_SPI_bm 0x08 /* Port C SPI bit mask. */ -#define PR_SPI_bp 3 /* Port C SPI bit position. */ - -#define PR_HIRES_bm 0x04 /* Port C AWEX bit mask. */ -#define PR_HIRES_bp 2 /* Port C AWEX bit position. */ - -#define PR_TC1_bm 0x02 /* Port C Timer/Counter1 bit mask. */ -#define PR_TC1_bp 1 /* Port C Timer/Counter1 bit position. */ - -#define PR_TC0_bm 0x01 /* Port C Timer/Counter0 bit mask. */ -#define PR_TC0_bp 0 /* Port C Timer/Counter0 bit position. */ - - -/* PR.PRPD bit masks and bit positions */ -/* PR_TWI_bm Predefined. */ -/* PR_TWI_bp Predefined. */ - -/* PR_USART1_bm Predefined. */ -/* PR_USART1_bp Predefined. */ - -/* PR_USART0_bm Predefined. */ -/* PR_USART0_bp Predefined. */ - -/* PR_SPI_bm Predefined. */ -/* PR_SPI_bp Predefined. */ - -/* PR_HIRES_bm Predefined. */ -/* PR_HIRES_bp Predefined. */ - -/* PR_TC1_bm Predefined. */ -/* PR_TC1_bp Predefined. */ - -/* PR_TC0_bm Predefined. */ -/* PR_TC0_bp Predefined. */ - - -/* PR.PRPE bit masks and bit positions */ -/* PR_TWI_bm Predefined. */ -/* PR_TWI_bp Predefined. */ - -/* PR_USART1_bm Predefined. */ -/* PR_USART1_bp Predefined. */ - -/* PR_USART0_bm Predefined. */ -/* PR_USART0_bp Predefined. */ - -/* PR_SPI_bm Predefined. */ -/* PR_SPI_bp Predefined. */ - -/* PR_HIRES_bm Predefined. */ -/* PR_HIRES_bp Predefined. */ - -/* PR_TC1_bm Predefined. */ -/* PR_TC1_bp Predefined. */ - -/* PR_TC0_bm Predefined. */ -/* PR_TC0_bp Predefined. */ - - -/* PR.PRPF bit masks and bit positions */ -/* PR_TWI_bm Predefined. */ -/* PR_TWI_bp Predefined. */ - -/* PR_USART1_bm Predefined. */ -/* PR_USART1_bp Predefined. */ - -/* PR_USART0_bm Predefined. */ -/* PR_USART0_bp Predefined. */ - -/* PR_SPI_bm Predefined. */ -/* PR_SPI_bp Predefined. */ - -/* PR_HIRES_bm Predefined. */ -/* PR_HIRES_bp Predefined. */ - -/* PR_TC1_bm Predefined. */ -/* PR_TC1_bp Predefined. */ - -/* PR_TC0_bm Predefined. */ -/* PR_TC0_bp Predefined. */ - - -/* SLEEP - Sleep Controller */ -/* SLEEP.CTRL bit masks and bit positions */ -#define SLEEP_SMODE_gm 0x0E /* Sleep Mode group mask. */ -#define SLEEP_SMODE_gp 1 /* Sleep Mode group position. */ -#define SLEEP_SMODE0_bm (1<<1) /* Sleep Mode bit 0 mask. */ -#define SLEEP_SMODE0_bp 1 /* Sleep Mode bit 0 position. */ -#define SLEEP_SMODE1_bm (1<<2) /* Sleep Mode bit 1 mask. */ -#define SLEEP_SMODE1_bp 2 /* Sleep Mode bit 1 position. */ -#define SLEEP_SMODE2_bm (1<<3) /* Sleep Mode bit 2 mask. */ -#define SLEEP_SMODE2_bp 3 /* Sleep Mode bit 2 position. */ - -#define SLEEP_SEN_bm 0x01 /* Sleep Enable bit mask. */ -#define SLEEP_SEN_bp 0 /* Sleep Enable bit position. */ - - -/* OSC - Oscillator */ -/* OSC.CTRL bit masks and bit positions */ -#define OSC_PLLEN_bm 0x10 /* PLL Enable bit mask. */ -#define OSC_PLLEN_bp 4 /* PLL Enable bit position. */ - -#define OSC_XOSCEN_bm 0x08 /* External Oscillator Enable bit mask. */ -#define OSC_XOSCEN_bp 3 /* External Oscillator Enable bit position. */ - -#define OSC_RC32KEN_bm 0x04 /* Internal 32kHz RC Oscillator Enable bit mask. */ -#define OSC_RC32KEN_bp 2 /* Internal 32kHz RC Oscillator Enable bit position. */ - -#define OSC_RC32MEN_bm 0x02 /* Internal 32MHz RC Oscillator Enable bit mask. */ -#define OSC_RC32MEN_bp 1 /* Internal 32MHz RC Oscillator Enable bit position. */ - -#define OSC_RC2MEN_bm 0x01 /* Internal 2MHz RC Oscillator Enable bit mask. */ -#define OSC_RC2MEN_bp 0 /* Internal 2MHz RC Oscillator Enable bit position. */ - - -/* OSC.STATUS bit masks and bit positions */ -#define OSC_PLLRDY_bm 0x10 /* PLL Ready bit mask. */ -#define OSC_PLLRDY_bp 4 /* PLL Ready bit position. */ - -#define OSC_XOSCRDY_bm 0x08 /* External Oscillator Ready bit mask. */ -#define OSC_XOSCRDY_bp 3 /* External Oscillator Ready bit position. */ - -#define OSC_RC32KRDY_bm 0x04 /* Internal 32kHz RC Oscillator Ready bit mask. */ -#define OSC_RC32KRDY_bp 2 /* Internal 32kHz RC Oscillator Ready bit position. */ - -#define OSC_RC32MRDY_bm 0x02 /* Internal 32MHz RC Oscillator Ready bit mask. */ -#define OSC_RC32MRDY_bp 1 /* Internal 32MHz RC Oscillator Ready bit position. */ - -#define OSC_RC2MRDY_bm 0x01 /* Internal 2MHz RC Oscillator Ready bit mask. */ -#define OSC_RC2MRDY_bp 0 /* Internal 2MHz RC Oscillator Ready bit position. */ - - -/* OSC.XOSCCTRL bit masks and bit positions */ -#define OSC_FRQRANGE_gm 0xC0 /* Frequency Range group mask. */ -#define OSC_FRQRANGE_gp 6 /* Frequency Range group position. */ -#define OSC_FRQRANGE0_bm (1<<6) /* Frequency Range bit 0 mask. */ -#define OSC_FRQRANGE0_bp 6 /* Frequency Range bit 0 position. */ -#define OSC_FRQRANGE1_bm (1<<7) /* Frequency Range bit 1 mask. */ -#define OSC_FRQRANGE1_bp 7 /* Frequency Range bit 1 position. */ - -#define OSC_X32KLPM_bm 0x20 /* 32kHz XTAL OSC Low-power Mode bit mask. */ -#define OSC_X32KLPM_bp 5 /* 32kHz XTAL OSC Low-power Mode bit position. */ - -#define OSC_XOSCSEL_gm 0x0F /* External Oscillator Selection and Startup Time group mask. */ -#define OSC_XOSCSEL_gp 0 /* External Oscillator Selection and Startup Time group position. */ -#define OSC_XOSCSEL0_bm (1<<0) /* External Oscillator Selection and Startup Time bit 0 mask. */ -#define OSC_XOSCSEL0_bp 0 /* External Oscillator Selection and Startup Time bit 0 position. */ -#define OSC_XOSCSEL1_bm (1<<1) /* External Oscillator Selection and Startup Time bit 1 mask. */ -#define OSC_XOSCSEL1_bp 1 /* External Oscillator Selection and Startup Time bit 1 position. */ -#define OSC_XOSCSEL2_bm (1<<2) /* External Oscillator Selection and Startup Time bit 2 mask. */ -#define OSC_XOSCSEL2_bp 2 /* External Oscillator Selection and Startup Time bit 2 position. */ -#define OSC_XOSCSEL3_bm (1<<3) /* External Oscillator Selection and Startup Time bit 3 mask. */ -#define OSC_XOSCSEL3_bp 3 /* External Oscillator Selection and Startup Time bit 3 position. */ - - -/* OSC.XOSCFAIL bit masks and bit positions */ -#define OSC_XOSCFDIF_bm 0x02 /* Failure Detection Interrupt Flag bit mask. */ -#define OSC_XOSCFDIF_bp 1 /* Failure Detection Interrupt Flag bit position. */ - -#define OSC_XOSCFDEN_bm 0x01 /* Failure Detection Enable bit mask. */ -#define OSC_XOSCFDEN_bp 0 /* Failure Detection Enable bit position. */ - - -/* OSC.PLLCTRL bit masks and bit positions */ -#define OSC_PLLSRC_gm 0xC0 /* Clock Source group mask. */ -#define OSC_PLLSRC_gp 6 /* Clock Source group position. */ -#define OSC_PLLSRC0_bm (1<<6) /* Clock Source bit 0 mask. */ -#define OSC_PLLSRC0_bp 6 /* Clock Source bit 0 position. */ -#define OSC_PLLSRC1_bm (1<<7) /* Clock Source bit 1 mask. */ -#define OSC_PLLSRC1_bp 7 /* Clock Source bit 1 position. */ - -#define OSC_PLLFAC_gm 0x1F /* Multiplication Factor group mask. */ -#define OSC_PLLFAC_gp 0 /* Multiplication Factor group position. */ -#define OSC_PLLFAC0_bm (1<<0) /* Multiplication Factor bit 0 mask. */ -#define OSC_PLLFAC0_bp 0 /* Multiplication Factor bit 0 position. */ -#define OSC_PLLFAC1_bm (1<<1) /* Multiplication Factor bit 1 mask. */ -#define OSC_PLLFAC1_bp 1 /* Multiplication Factor bit 1 position. */ -#define OSC_PLLFAC2_bm (1<<2) /* Multiplication Factor bit 2 mask. */ -#define OSC_PLLFAC2_bp 2 /* Multiplication Factor bit 2 position. */ -#define OSC_PLLFAC3_bm (1<<3) /* Multiplication Factor bit 3 mask. */ -#define OSC_PLLFAC3_bp 3 /* Multiplication Factor bit 3 position. */ -#define OSC_PLLFAC4_bm (1<<4) /* Multiplication Factor bit 4 mask. */ -#define OSC_PLLFAC4_bp 4 /* Multiplication Factor bit 4 position. */ - - -/* OSC.DFLLCTRL bit masks and bit positions */ -#define OSC_RC32MCREF_bm 0x02 /* 32MHz Calibration Reference bit mask. */ -#define OSC_RC32MCREF_bp 1 /* 32MHz Calibration Reference bit position. */ - -#define OSC_RC2MCREF_bm 0x01 /* 2MHz Calibration Reference bit mask. */ -#define OSC_RC2MCREF_bp 0 /* 2MHz Calibration Reference bit position. */ - - -/* DFLL - DFLL */ -/* DFLL.CTRL bit masks and bit positions */ -#define DFLL_ENABLE_bm 0x01 /* DFLL Enable bit mask. */ -#define DFLL_ENABLE_bp 0 /* DFLL Enable bit position. */ - - -/* DFLL.CALA bit masks and bit positions */ -#define DFLL_CALL_gm 0x7F /* DFLL Calibration bits [6:0] group mask. */ -#define DFLL_CALL_gp 0 /* DFLL Calibration bits [6:0] group position. */ -#define DFLL_CALL0_bm (1<<0) /* DFLL Calibration bits [6:0] bit 0 mask. */ -#define DFLL_CALL0_bp 0 /* DFLL Calibration bits [6:0] bit 0 position. */ -#define DFLL_CALL1_bm (1<<1) /* DFLL Calibration bits [6:0] bit 1 mask. */ -#define DFLL_CALL1_bp 1 /* DFLL Calibration bits [6:0] bit 1 position. */ -#define DFLL_CALL2_bm (1<<2) /* DFLL Calibration bits [6:0] bit 2 mask. */ -#define DFLL_CALL2_bp 2 /* DFLL Calibration bits [6:0] bit 2 position. */ -#define DFLL_CALL3_bm (1<<3) /* DFLL Calibration bits [6:0] bit 3 mask. */ -#define DFLL_CALL3_bp 3 /* DFLL Calibration bits [6:0] bit 3 position. */ -#define DFLL_CALL4_bm (1<<4) /* DFLL Calibration bits [6:0] bit 4 mask. */ -#define DFLL_CALL4_bp 4 /* DFLL Calibration bits [6:0] bit 4 position. */ -#define DFLL_CALL5_bm (1<<5) /* DFLL Calibration bits [6:0] bit 5 mask. */ -#define DFLL_CALL5_bp 5 /* DFLL Calibration bits [6:0] bit 5 position. */ -#define DFLL_CALL6_bm (1<<6) /* DFLL Calibration bits [6:0] bit 6 mask. */ -#define DFLL_CALL6_bp 6 /* DFLL Calibration bits [6:0] bit 6 position. */ - - -/* DFLL.CALB bit masks and bit positions */ -#define DFLL_CALH_gm 0x3F /* DFLL Calibration bits [12:7] group mask. */ -#define DFLL_CALH_gp 0 /* DFLL Calibration bits [12:7] group position. */ -#define DFLL_CALH0_bm (1<<0) /* DFLL Calibration bits [12:7] bit 0 mask. */ -#define DFLL_CALH0_bp 0 /* DFLL Calibration bits [12:7] bit 0 position. */ -#define DFLL_CALH1_bm (1<<1) /* DFLL Calibration bits [12:7] bit 1 mask. */ -#define DFLL_CALH1_bp 1 /* DFLL Calibration bits [12:7] bit 1 position. */ -#define DFLL_CALH2_bm (1<<2) /* DFLL Calibration bits [12:7] bit 2 mask. */ -#define DFLL_CALH2_bp 2 /* DFLL Calibration bits [12:7] bit 2 position. */ -#define DFLL_CALH3_bm (1<<3) /* DFLL Calibration bits [12:7] bit 3 mask. */ -#define DFLL_CALH3_bp 3 /* DFLL Calibration bits [12:7] bit 3 position. */ -#define DFLL_CALH4_bm (1<<4) /* DFLL Calibration bits [12:7] bit 4 mask. */ -#define DFLL_CALH4_bp 4 /* DFLL Calibration bits [12:7] bit 4 position. */ -#define DFLL_CALH5_bm (1<<5) /* DFLL Calibration bits [12:7] bit 5 mask. */ -#define DFLL_CALH5_bp 5 /* DFLL Calibration bits [12:7] bit 5 position. */ - - -/* RST - Reset */ -/* RST.STATUS bit masks and bit positions */ -#define RST_SDRF_bm 0x40 /* Spike Detection Reset Flag bit mask. */ -#define RST_SDRF_bp 6 /* Spike Detection Reset Flag bit position. */ - -#define RST_SRF_bm 0x20 /* Software Reset Flag bit mask. */ -#define RST_SRF_bp 5 /* Software Reset Flag bit position. */ - -#define RST_PDIRF_bm 0x10 /* Programming and Debug Interface Interface Reset Flag bit mask. */ -#define RST_PDIRF_bp 4 /* Programming and Debug Interface Interface Reset Flag bit position. */ - -#define RST_WDRF_bm 0x08 /* Watchdog Reset Flag bit mask. */ -#define RST_WDRF_bp 3 /* Watchdog Reset Flag bit position. */ - -#define RST_BORF_bm 0x04 /* Brown-out Reset Flag bit mask. */ -#define RST_BORF_bp 2 /* Brown-out Reset Flag bit position. */ - -#define RST_EXTRF_bm 0x02 /* External Reset Flag bit mask. */ -#define RST_EXTRF_bp 1 /* External Reset Flag bit position. */ - -#define RST_PORF_bm 0x01 /* Power-on Reset Flag bit mask. */ -#define RST_PORF_bp 0 /* Power-on Reset Flag bit position. */ - - -/* RST.CTRL bit masks and bit positions */ -#define RST_SWRST_bm 0x01 /* Software Reset bit mask. */ -#define RST_SWRST_bp 0 /* Software Reset bit position. */ - - -/* WDT - Watch-Dog Timer */ -/* WDT.CTRL bit masks and bit positions */ -#define WDT_PER_gm 0x3C /* Period group mask. */ -#define WDT_PER_gp 2 /* Period group position. */ -#define WDT_PER0_bm (1<<2) /* Period bit 0 mask. */ -#define WDT_PER0_bp 2 /* Period bit 0 position. */ -#define WDT_PER1_bm (1<<3) /* Period bit 1 mask. */ -#define WDT_PER1_bp 3 /* Period bit 1 position. */ -#define WDT_PER2_bm (1<<4) /* Period bit 2 mask. */ -#define WDT_PER2_bp 4 /* Period bit 2 position. */ -#define WDT_PER3_bm (1<<5) /* Period bit 3 mask. */ -#define WDT_PER3_bp 5 /* Period bit 3 position. */ - -#define WDT_ENABLE_bm 0x02 /* Enable bit mask. */ -#define WDT_ENABLE_bp 1 /* Enable bit position. */ - -#define WDT_CEN_bm 0x01 /* Change Enable bit mask. */ -#define WDT_CEN_bp 0 /* Change Enable bit position. */ - - -/* WDT.WINCTRL bit masks and bit positions */ -#define WDT_WPER_gm 0x3C /* Windowed Mode Period group mask. */ -#define WDT_WPER_gp 2 /* Windowed Mode Period group position. */ -#define WDT_WPER0_bm (1<<2) /* Windowed Mode Period bit 0 mask. */ -#define WDT_WPER0_bp 2 /* Windowed Mode Period bit 0 position. */ -#define WDT_WPER1_bm (1<<3) /* Windowed Mode Period bit 1 mask. */ -#define WDT_WPER1_bp 3 /* Windowed Mode Period bit 1 position. */ -#define WDT_WPER2_bm (1<<4) /* Windowed Mode Period bit 2 mask. */ -#define WDT_WPER2_bp 4 /* Windowed Mode Period bit 2 position. */ -#define WDT_WPER3_bm (1<<5) /* Windowed Mode Period bit 3 mask. */ -#define WDT_WPER3_bp 5 /* Windowed Mode Period bit 3 position. */ - -#define WDT_WEN_bm 0x02 /* Windowed Mode Enable bit mask. */ -#define WDT_WEN_bp 1 /* Windowed Mode Enable bit position. */ - -#define WDT_WCEN_bm 0x01 /* Windowed Mode Change Enable bit mask. */ -#define WDT_WCEN_bp 0 /* Windowed Mode Change Enable bit position. */ - - -/* WDT.STATUS bit masks and bit positions */ -#define WDT_SYNCBUSY_bm 0x01 /* Syncronization busy bit mask. */ -#define WDT_SYNCBUSY_bp 0 /* Syncronization busy bit position. */ - - -/* MCU - MCU Control */ -/* MCU.MCUCR bit masks and bit positions */ -#define MCU_JTAGD_bm 0x01 /* JTAG Disable bit mask. */ -#define MCU_JTAGD_bp 0 /* JTAG Disable bit position. */ - - -/* MCU.EVSYSLOCK bit masks and bit positions */ -#define MCU_EVSYS1LOCK_bm 0x10 /* Event Channel 4-7 Lock bit mask. */ -#define MCU_EVSYS1LOCK_bp 4 /* Event Channel 4-7 Lock bit position. */ - -#define MCU_EVSYS0LOCK_bm 0x01 /* Event Channel 0-3 Lock bit mask. */ -#define MCU_EVSYS0LOCK_bp 0 /* Event Channel 0-3 Lock bit position. */ - - -/* MCU.AWEXLOCK bit masks and bit positions */ -#define MCU_AWEXELOCK_bm 0x04 /* AWeX on T/C E0 Lock bit mask. */ -#define MCU_AWEXELOCK_bp 2 /* AWeX on T/C E0 Lock bit position. */ - -#define MCU_AWEXCLOCK_bm 0x01 /* AWeX on T/C C0 Lock bit mask. */ -#define MCU_AWEXCLOCK_bp 0 /* AWeX on T/C C0 Lock bit position. */ - - -/* PMIC - Programmable Multi-level Interrupt Controller */ -/* PMIC.STATUS bit masks and bit positions */ -#define PMIC_NMIEX_bm 0x80 /* Non-maskable Interrupt Executing bit mask. */ -#define PMIC_NMIEX_bp 7 /* Non-maskable Interrupt Executing bit position. */ - -#define PMIC_HILVLEX_bm 0x04 /* High Level Interrupt Executing bit mask. */ -#define PMIC_HILVLEX_bp 2 /* High Level Interrupt Executing bit position. */ - -#define PMIC_MEDLVLEX_bm 0x02 /* Medium Level Interrupt Executing bit mask. */ -#define PMIC_MEDLVLEX_bp 1 /* Medium Level Interrupt Executing bit position. */ - -#define PMIC_LOLVLEX_bm 0x01 /* Low Level Interrupt Executing bit mask. */ -#define PMIC_LOLVLEX_bp 0 /* Low Level Interrupt Executing bit position. */ - - -/* PMIC.CTRL bit masks and bit positions */ -#define PMIC_RREN_bm 0x80 /* Round-Robin Priority Enable bit mask. */ -#define PMIC_RREN_bp 7 /* Round-Robin Priority Enable bit position. */ - -#define PMIC_IVSEL_bm 0x40 /* Interrupt Vector Select bit mask. */ -#define PMIC_IVSEL_bp 6 /* Interrupt Vector Select bit position. */ - -#define PMIC_HILVLEN_bm 0x04 /* High Level Enable bit mask. */ -#define PMIC_HILVLEN_bp 2 /* High Level Enable bit position. */ - -#define PMIC_MEDLVLEN_bm 0x02 /* Medium Level Enable bit mask. */ -#define PMIC_MEDLVLEN_bp 1 /* Medium Level Enable bit position. */ - -#define PMIC_LOLVLEN_bm 0x01 /* Low Level Enable bit mask. */ -#define PMIC_LOLVLEN_bp 0 /* Low Level Enable bit position. */ - - -/* EVSYS - Event System */ -/* EVSYS.CH0MUX bit masks and bit positions */ -#define EVSYS_CHMUX_gm 0xFF /* Event Channel 0 Multiplexer group mask. */ -#define EVSYS_CHMUX_gp 0 /* Event Channel 0 Multiplexer group position. */ -#define EVSYS_CHMUX0_bm (1<<0) /* Event Channel 0 Multiplexer bit 0 mask. */ -#define EVSYS_CHMUX0_bp 0 /* Event Channel 0 Multiplexer bit 0 position. */ -#define EVSYS_CHMUX1_bm (1<<1) /* Event Channel 0 Multiplexer bit 1 mask. */ -#define EVSYS_CHMUX1_bp 1 /* Event Channel 0 Multiplexer bit 1 position. */ -#define EVSYS_CHMUX2_bm (1<<2) /* Event Channel 0 Multiplexer bit 2 mask. */ -#define EVSYS_CHMUX2_bp 2 /* Event Channel 0 Multiplexer bit 2 position. */ -#define EVSYS_CHMUX3_bm (1<<3) /* Event Channel 0 Multiplexer bit 3 mask. */ -#define EVSYS_CHMUX3_bp 3 /* Event Channel 0 Multiplexer bit 3 position. */ -#define EVSYS_CHMUX4_bm (1<<4) /* Event Channel 0 Multiplexer bit 4 mask. */ -#define EVSYS_CHMUX4_bp 4 /* Event Channel 0 Multiplexer bit 4 position. */ -#define EVSYS_CHMUX5_bm (1<<5) /* Event Channel 0 Multiplexer bit 5 mask. */ -#define EVSYS_CHMUX5_bp 5 /* Event Channel 0 Multiplexer bit 5 position. */ -#define EVSYS_CHMUX6_bm (1<<6) /* Event Channel 0 Multiplexer bit 6 mask. */ -#define EVSYS_CHMUX6_bp 6 /* Event Channel 0 Multiplexer bit 6 position. */ -#define EVSYS_CHMUX7_bm (1<<7) /* Event Channel 0 Multiplexer bit 7 mask. */ -#define EVSYS_CHMUX7_bp 7 /* Event Channel 0 Multiplexer bit 7 position. */ - - -/* EVSYS.CH1MUX bit masks and bit positions */ -/* EVSYS_CHMUX_gm Predefined. */ -/* EVSYS_CHMUX_gp Predefined. */ -/* EVSYS_CHMUX0_bm Predefined. */ -/* EVSYS_CHMUX0_bp Predefined. */ -/* EVSYS_CHMUX1_bm Predefined. */ -/* EVSYS_CHMUX1_bp Predefined. */ -/* EVSYS_CHMUX2_bm Predefined. */ -/* EVSYS_CHMUX2_bp Predefined. */ -/* EVSYS_CHMUX3_bm Predefined. */ -/* EVSYS_CHMUX3_bp Predefined. */ -/* EVSYS_CHMUX4_bm Predefined. */ -/* EVSYS_CHMUX4_bp Predefined. */ -/* EVSYS_CHMUX5_bm Predefined. */ -/* EVSYS_CHMUX5_bp Predefined. */ -/* EVSYS_CHMUX6_bm Predefined. */ -/* EVSYS_CHMUX6_bp Predefined. */ -/* EVSYS_CHMUX7_bm Predefined. */ -/* EVSYS_CHMUX7_bp Predefined. */ - - -/* EVSYS.CH2MUX bit masks and bit positions */ -/* EVSYS_CHMUX_gm Predefined. */ -/* EVSYS_CHMUX_gp Predefined. */ -/* EVSYS_CHMUX0_bm Predefined. */ -/* EVSYS_CHMUX0_bp Predefined. */ -/* EVSYS_CHMUX1_bm Predefined. */ -/* EVSYS_CHMUX1_bp Predefined. */ -/* EVSYS_CHMUX2_bm Predefined. */ -/* EVSYS_CHMUX2_bp Predefined. */ -/* EVSYS_CHMUX3_bm Predefined. */ -/* EVSYS_CHMUX3_bp Predefined. */ -/* EVSYS_CHMUX4_bm Predefined. */ -/* EVSYS_CHMUX4_bp Predefined. */ -/* EVSYS_CHMUX5_bm Predefined. */ -/* EVSYS_CHMUX5_bp Predefined. */ -/* EVSYS_CHMUX6_bm Predefined. */ -/* EVSYS_CHMUX6_bp Predefined. */ -/* EVSYS_CHMUX7_bm Predefined. */ -/* EVSYS_CHMUX7_bp Predefined. */ - - -/* EVSYS.CH3MUX bit masks and bit positions */ -/* EVSYS_CHMUX_gm Predefined. */ -/* EVSYS_CHMUX_gp Predefined. */ -/* EVSYS_CHMUX0_bm Predefined. */ -/* EVSYS_CHMUX0_bp Predefined. */ -/* EVSYS_CHMUX1_bm Predefined. */ -/* EVSYS_CHMUX1_bp Predefined. */ -/* EVSYS_CHMUX2_bm Predefined. */ -/* EVSYS_CHMUX2_bp Predefined. */ -/* EVSYS_CHMUX3_bm Predefined. */ -/* EVSYS_CHMUX3_bp Predefined. */ -/* EVSYS_CHMUX4_bm Predefined. */ -/* EVSYS_CHMUX4_bp Predefined. */ -/* EVSYS_CHMUX5_bm Predefined. */ -/* EVSYS_CHMUX5_bp Predefined. */ -/* EVSYS_CHMUX6_bm Predefined. */ -/* EVSYS_CHMUX6_bp Predefined. */ -/* EVSYS_CHMUX7_bm Predefined. */ -/* EVSYS_CHMUX7_bp Predefined. */ - - -/* EVSYS.CH0CTRL bit masks and bit positions */ -#define EVSYS_QDIRM_gm 0x60 /* Quadrature Decoder Index Recognition Mode group mask. */ -#define EVSYS_QDIRM_gp 5 /* Quadrature Decoder Index Recognition Mode group position. */ -#define EVSYS_QDIRM0_bm (1<<5) /* Quadrature Decoder Index Recognition Mode bit 0 mask. */ -#define EVSYS_QDIRM0_bp 5 /* Quadrature Decoder Index Recognition Mode bit 0 position. */ -#define EVSYS_QDIRM1_bm (1<<6) /* Quadrature Decoder Index Recognition Mode bit 1 mask. */ -#define EVSYS_QDIRM1_bp 6 /* Quadrature Decoder Index Recognition Mode bit 1 position. */ - -#define EVSYS_QDIEN_bm 0x10 /* Quadrature Decoder Index Enable bit mask. */ -#define EVSYS_QDIEN_bp 4 /* Quadrature Decoder Index Enable bit position. */ - -#define EVSYS_QDEN_bm 0x08 /* Quadrature Decoder Enable bit mask. */ -#define EVSYS_QDEN_bp 3 /* Quadrature Decoder Enable bit position. */ - -#define EVSYS_DIGFILT_gm 0x07 /* Digital Filter group mask. */ -#define EVSYS_DIGFILT_gp 0 /* Digital Filter group position. */ -#define EVSYS_DIGFILT0_bm (1<<0) /* Digital Filter bit 0 mask. */ -#define EVSYS_DIGFILT0_bp 0 /* Digital Filter bit 0 position. */ -#define EVSYS_DIGFILT1_bm (1<<1) /* Digital Filter bit 1 mask. */ -#define EVSYS_DIGFILT1_bp 1 /* Digital Filter bit 1 position. */ -#define EVSYS_DIGFILT2_bm (1<<2) /* Digital Filter bit 2 mask. */ -#define EVSYS_DIGFILT2_bp 2 /* Digital Filter bit 2 position. */ - - -/* EVSYS.CH1CTRL bit masks and bit positions */ -/* EVSYS_DIGFILT_gm Predefined. */ -/* EVSYS_DIGFILT_gp Predefined. */ -/* EVSYS_DIGFILT0_bm Predefined. */ -/* EVSYS_DIGFILT0_bp Predefined. */ -/* EVSYS_DIGFILT1_bm Predefined. */ -/* EVSYS_DIGFILT1_bp Predefined. */ -/* EVSYS_DIGFILT2_bm Predefined. */ -/* EVSYS_DIGFILT2_bp Predefined. */ - - -/* EVSYS.CH2CTRL bit masks and bit positions */ -/* EVSYS_QDIRM_gm Predefined. */ -/* EVSYS_QDIRM_gp Predefined. */ -/* EVSYS_QDIRM0_bm Predefined. */ -/* EVSYS_QDIRM0_bp Predefined. */ -/* EVSYS_QDIRM1_bm Predefined. */ -/* EVSYS_QDIRM1_bp Predefined. */ - -/* EVSYS_QDIEN_bm Predefined. */ -/* EVSYS_QDIEN_bp Predefined. */ - -/* EVSYS_QDEN_bm Predefined. */ -/* EVSYS_QDEN_bp Predefined. */ - -/* EVSYS_DIGFILT_gm Predefined. */ -/* EVSYS_DIGFILT_gp Predefined. */ -/* EVSYS_DIGFILT0_bm Predefined. */ -/* EVSYS_DIGFILT0_bp Predefined. */ -/* EVSYS_DIGFILT1_bm Predefined. */ -/* EVSYS_DIGFILT1_bp Predefined. */ -/* EVSYS_DIGFILT2_bm Predefined. */ -/* EVSYS_DIGFILT2_bp Predefined. */ - - -/* EVSYS.CH3CTRL bit masks and bit positions */ -/* EVSYS_DIGFILT_gm Predefined. */ -/* EVSYS_DIGFILT_gp Predefined. */ -/* EVSYS_DIGFILT0_bm Predefined. */ -/* EVSYS_DIGFILT0_bp Predefined. */ -/* EVSYS_DIGFILT1_bm Predefined. */ -/* EVSYS_DIGFILT1_bp Predefined. */ -/* EVSYS_DIGFILT2_bm Predefined. */ -/* EVSYS_DIGFILT2_bp Predefined. */ - - -/* NVM - Non Volatile Memory Controller */ -/* NVM.CMD bit masks and bit positions */ -#define NVM_CMD_gm 0xFF /* Command group mask. */ -#define NVM_CMD_gp 0 /* Command group position. */ -#define NVM_CMD0_bm (1<<0) /* Command bit 0 mask. */ -#define NVM_CMD0_bp 0 /* Command bit 0 position. */ -#define NVM_CMD1_bm (1<<1) /* Command bit 1 mask. */ -#define NVM_CMD1_bp 1 /* Command bit 1 position. */ -#define NVM_CMD2_bm (1<<2) /* Command bit 2 mask. */ -#define NVM_CMD2_bp 2 /* Command bit 2 position. */ -#define NVM_CMD3_bm (1<<3) /* Command bit 3 mask. */ -#define NVM_CMD3_bp 3 /* Command bit 3 position. */ -#define NVM_CMD4_bm (1<<4) /* Command bit 4 mask. */ -#define NVM_CMD4_bp 4 /* Command bit 4 position. */ -#define NVM_CMD5_bm (1<<5) /* Command bit 5 mask. */ -#define NVM_CMD5_bp 5 /* Command bit 5 position. */ -#define NVM_CMD6_bm (1<<6) /* Command bit 6 mask. */ -#define NVM_CMD6_bp 6 /* Command bit 6 position. */ -#define NVM_CMD7_bm (1<<7) /* Command bit 7 mask. */ -#define NVM_CMD7_bp 7 /* Command bit 7 position. */ - - -/* NVM.CTRLA bit masks and bit positions */ -#define NVM_CMDEX_bm 0x01 /* Command Execute bit mask. */ -#define NVM_CMDEX_bp 0 /* Command Execute bit position. */ - - -/* NVM.CTRLB bit masks and bit positions */ -#define NVM_EEMAPEN_bm 0x08 /* EEPROM Mapping Enable bit mask. */ -#define NVM_EEMAPEN_bp 3 /* EEPROM Mapping Enable bit position. */ - -#define NVM_FPRM_bm 0x04 /* Flash Power Reduction Enable bit mask. */ -#define NVM_FPRM_bp 2 /* Flash Power Reduction Enable bit position. */ - -#define NVM_EPRM_bm 0x02 /* EEPROM Power Reduction Enable bit mask. */ -#define NVM_EPRM_bp 1 /* EEPROM Power Reduction Enable bit position. */ - -#define NVM_SPMLOCK_bm 0x01 /* SPM Lock bit mask. */ -#define NVM_SPMLOCK_bp 0 /* SPM Lock bit position. */ - - -/* NVM.INTCTRL bit masks and bit positions */ -#define NVM_SPMLVL_gm 0x0C /* SPM Interrupt Level group mask. */ -#define NVM_SPMLVL_gp 2 /* SPM Interrupt Level group position. */ -#define NVM_SPMLVL0_bm (1<<2) /* SPM Interrupt Level bit 0 mask. */ -#define NVM_SPMLVL0_bp 2 /* SPM Interrupt Level bit 0 position. */ -#define NVM_SPMLVL1_bm (1<<3) /* SPM Interrupt Level bit 1 mask. */ -#define NVM_SPMLVL1_bp 3 /* SPM Interrupt Level bit 1 position. */ - -#define NVM_EELVL_gm 0x03 /* EEPROM Interrupt Level group mask. */ -#define NVM_EELVL_gp 0 /* EEPROM Interrupt Level group position. */ -#define NVM_EELVL0_bm (1<<0) /* EEPROM Interrupt Level bit 0 mask. */ -#define NVM_EELVL0_bp 0 /* EEPROM Interrupt Level bit 0 position. */ -#define NVM_EELVL1_bm (1<<1) /* EEPROM Interrupt Level bit 1 mask. */ -#define NVM_EELVL1_bp 1 /* EEPROM Interrupt Level bit 1 position. */ - - -/* NVM.STATUS bit masks and bit positions */ -#define NVM_NVMBUSY_bm 0x80 /* Non-volatile Memory Busy bit mask. */ -#define NVM_NVMBUSY_bp 7 /* Non-volatile Memory Busy bit position. */ - -#define NVM_FBUSY_bm 0x40 /* Flash Memory Busy bit mask. */ -#define NVM_FBUSY_bp 6 /* Flash Memory Busy bit position. */ - -#define NVM_EELOAD_bm 0x02 /* EEPROM Page Buffer Active Loading bit mask. */ -#define NVM_EELOAD_bp 1 /* EEPROM Page Buffer Active Loading bit position. */ - -#define NVM_FLOAD_bm 0x01 /* Flash Page Buffer Active Loading bit mask. */ -#define NVM_FLOAD_bp 0 /* Flash Page Buffer Active Loading bit position. */ - - -/* NVM.LOCKBITS bit masks and bit positions */ -#define NVM_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ -#define NVM_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ -#define NVM_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ -#define NVM_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ -#define NVM_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ -#define NVM_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ - -#define NVM_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ -#define NVM_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ -#define NVM_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ -#define NVM_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ -#define NVM_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ -#define NVM_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ - -#define NVM_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ -#define NVM_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ -#define NVM_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ -#define NVM_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ -#define NVM_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ -#define NVM_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ - -#define NVM_LB_gm 0x03 /* Lock Bits group mask. */ -#define NVM_LB_gp 0 /* Lock Bits group position. */ -#define NVM_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ -#define NVM_LB0_bp 0 /* Lock Bits bit 0 position. */ -#define NVM_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ -#define NVM_LB1_bp 1 /* Lock Bits bit 1 position. */ - - -/* NVM_LOCKBITS.LOCKBITS bit masks and bit positions */ -#define NVM_LOCKBITS_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ -#define NVM_LOCKBITS_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ -#define NVM_LOCKBITS_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ -#define NVM_LOCKBITS_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ -#define NVM_LOCKBITS_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ -#define NVM_LOCKBITS_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ - -#define NVM_LOCKBITS_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ -#define NVM_LOCKBITS_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ -#define NVM_LOCKBITS_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ -#define NVM_LOCKBITS_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ -#define NVM_LOCKBITS_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ -#define NVM_LOCKBITS_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ - -#define NVM_LOCKBITS_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ -#define NVM_LOCKBITS_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ -#define NVM_LOCKBITS_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ -#define NVM_LOCKBITS_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ -#define NVM_LOCKBITS_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ -#define NVM_LOCKBITS_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ - -#define NVM_LOCKBITS_LB_gm 0x03 /* Lock Bits group mask. */ -#define NVM_LOCKBITS_LB_gp 0 /* Lock Bits group position. */ -#define NVM_LOCKBITS_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ -#define NVM_LOCKBITS_LB0_bp 0 /* Lock Bits bit 0 position. */ -#define NVM_LOCKBITS_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ -#define NVM_LOCKBITS_LB1_bp 1 /* Lock Bits bit 1 position. */ - - -/* NVM_FUSES.FUSEBYTE0 bit masks and bit positions */ -#define NVM_FUSES_USERID_gm 0xFF /* User ID group mask. */ -#define NVM_FUSES_USERID_gp 0 /* User ID group position. */ -#define NVM_FUSES_USERID0_bm (1<<0) /* User ID bit 0 mask. */ -#define NVM_FUSES_USERID0_bp 0 /* User ID bit 0 position. */ -#define NVM_FUSES_USERID1_bm (1<<1) /* User ID bit 1 mask. */ -#define NVM_FUSES_USERID1_bp 1 /* User ID bit 1 position. */ -#define NVM_FUSES_USERID2_bm (1<<2) /* User ID bit 2 mask. */ -#define NVM_FUSES_USERID2_bp 2 /* User ID bit 2 position. */ -#define NVM_FUSES_USERID3_bm (1<<3) /* User ID bit 3 mask. */ -#define NVM_FUSES_USERID3_bp 3 /* User ID bit 3 position. */ -#define NVM_FUSES_USERID4_bm (1<<4) /* User ID bit 4 mask. */ -#define NVM_FUSES_USERID4_bp 4 /* User ID bit 4 position. */ -#define NVM_FUSES_USERID5_bm (1<<5) /* User ID bit 5 mask. */ -#define NVM_FUSES_USERID5_bp 5 /* User ID bit 5 position. */ -#define NVM_FUSES_USERID6_bm (1<<6) /* User ID bit 6 mask. */ -#define NVM_FUSES_USERID6_bp 6 /* User ID bit 6 position. */ -#define NVM_FUSES_USERID7_bm (1<<7) /* User ID bit 7 mask. */ -#define NVM_FUSES_USERID7_bp 7 /* User ID bit 7 position. */ - - -/* NVM_FUSES.FUSEBYTE1 bit masks and bit positions */ -#define NVM_FUSES_WDWP_gm 0xF0 /* Watchdog Window Timeout Period group mask. */ -#define NVM_FUSES_WDWP_gp 4 /* Watchdog Window Timeout Period group position. */ -#define NVM_FUSES_WDWP0_bm (1<<4) /* Watchdog Window Timeout Period bit 0 mask. */ -#define NVM_FUSES_WDWP0_bp 4 /* Watchdog Window Timeout Period bit 0 position. */ -#define NVM_FUSES_WDWP1_bm (1<<5) /* Watchdog Window Timeout Period bit 1 mask. */ -#define NVM_FUSES_WDWP1_bp 5 /* Watchdog Window Timeout Period bit 1 position. */ -#define NVM_FUSES_WDWP2_bm (1<<6) /* Watchdog Window Timeout Period bit 2 mask. */ -#define NVM_FUSES_WDWP2_bp 6 /* Watchdog Window Timeout Period bit 2 position. */ -#define NVM_FUSES_WDWP3_bm (1<<7) /* Watchdog Window Timeout Period bit 3 mask. */ -#define NVM_FUSES_WDWP3_bp 7 /* Watchdog Window Timeout Period bit 3 position. */ - -#define NVM_FUSES_WDP_gm 0x0F /* Watchdog Timeout Period group mask. */ -#define NVM_FUSES_WDP_gp 0 /* Watchdog Timeout Period group position. */ -#define NVM_FUSES_WDP0_bm (1<<0) /* Watchdog Timeout Period bit 0 mask. */ -#define NVM_FUSES_WDP0_bp 0 /* Watchdog Timeout Period bit 0 position. */ -#define NVM_FUSES_WDP1_bm (1<<1) /* Watchdog Timeout Period bit 1 mask. */ -#define NVM_FUSES_WDP1_bp 1 /* Watchdog Timeout Period bit 1 position. */ -#define NVM_FUSES_WDP2_bm (1<<2) /* Watchdog Timeout Period bit 2 mask. */ -#define NVM_FUSES_WDP2_bp 2 /* Watchdog Timeout Period bit 2 position. */ -#define NVM_FUSES_WDP3_bm (1<<3) /* Watchdog Timeout Period bit 3 mask. */ -#define NVM_FUSES_WDP3_bp 3 /* Watchdog Timeout Period bit 3 position. */ - - -/* NVM_FUSES.FUSEBYTE2 bit masks and bit positions */ -#define NVM_FUSES_DVSDON_bm 0x80 /* Spike Detector Enable bit mask. */ -#define NVM_FUSES_DVSDON_bp 7 /* Spike Detector Enable bit position. */ - -#define NVM_FUSES_BOOTRST_bm 0x40 /* Boot Loader Section Reset Vector bit mask. */ -#define NVM_FUSES_BOOTRST_bp 6 /* Boot Loader Section Reset Vector bit position. */ - -#define NVM_FUSES_BODPD_gm 0x03 /* BOD Operation in Power-Down Mode group mask. */ -#define NVM_FUSES_BODPD_gp 0 /* BOD Operation in Power-Down Mode group position. */ -#define NVM_FUSES_BODPD0_bm (1<<0) /* BOD Operation in Power-Down Mode bit 0 mask. */ -#define NVM_FUSES_BODPD0_bp 0 /* BOD Operation in Power-Down Mode bit 0 position. */ -#define NVM_FUSES_BODPD1_bm (1<<1) /* BOD Operation in Power-Down Mode bit 1 mask. */ -#define NVM_FUSES_BODPD1_bp 1 /* BOD Operation in Power-Down Mode bit 1 position. */ - - -/* NVM_FUSES.FUSEBYTE4 bit masks and bit positions */ -#define NVM_FUSES_SUT_gm 0x0C /* Start-up Time group mask. */ -#define NVM_FUSES_SUT_gp 2 /* Start-up Time group position. */ -#define NVM_FUSES_SUT0_bm (1<<2) /* Start-up Time bit 0 mask. */ -#define NVM_FUSES_SUT0_bp 2 /* Start-up Time bit 0 position. */ -#define NVM_FUSES_SUT1_bm (1<<3) /* Start-up Time bit 1 mask. */ -#define NVM_FUSES_SUT1_bp 3 /* Start-up Time bit 1 position. */ - -#define NVM_FUSES_WDLOCK_bm 0x02 /* Watchdog Timer Lock bit mask. */ -#define NVM_FUSES_WDLOCK_bp 1 /* Watchdog Timer Lock bit position. */ - - -/* NVM_FUSES.FUSEBYTE5 bit masks and bit positions */ -#define NVM_FUSES_BODACT_gm 0x30 /* BOD Operation in Active Mode group mask. */ -#define NVM_FUSES_BODACT_gp 4 /* BOD Operation in Active Mode group position. */ -#define NVM_FUSES_BODACT0_bm (1<<4) /* BOD Operation in Active Mode bit 0 mask. */ -#define NVM_FUSES_BODACT0_bp 4 /* BOD Operation in Active Mode bit 0 position. */ -#define NVM_FUSES_BODACT1_bm (1<<5) /* BOD Operation in Active Mode bit 1 mask. */ -#define NVM_FUSES_BODACT1_bp 5 /* BOD Operation in Active Mode bit 1 position. */ - -#define NVM_FUSES_EESAVE_bm 0x08 /* Preserve EEPROM Through Chip Erase bit mask. */ -#define NVM_FUSES_EESAVE_bp 3 /* Preserve EEPROM Through Chip Erase bit position. */ - -#define NVM_FUSES_BODLVL_gm 0x07 /* Brown Out Detection Voltage Level group mask. */ -#define NVM_FUSES_BODLVL_gp 0 /* Brown Out Detection Voltage Level group position. */ -#define NVM_FUSES_BODLVL0_bm (1<<0) /* Brown Out Detection Voltage Level bit 0 mask. */ -#define NVM_FUSES_BODLVL0_bp 0 /* Brown Out Detection Voltage Level bit 0 position. */ -#define NVM_FUSES_BODLVL1_bm (1<<1) /* Brown Out Detection Voltage Level bit 1 mask. */ -#define NVM_FUSES_BODLVL1_bp 1 /* Brown Out Detection Voltage Level bit 1 position. */ -#define NVM_FUSES_BODLVL2_bm (1<<2) /* Brown Out Detection Voltage Level bit 2 mask. */ -#define NVM_FUSES_BODLVL2_bp 2 /* Brown Out Detection Voltage Level bit 2 position. */ - - -/* AC - Analog Comparator */ -/* AC.AC0CTRL bit masks and bit positions */ -#define AC_INTMODE_gm 0xC0 /* Interrupt Mode group mask. */ -#define AC_INTMODE_gp 6 /* Interrupt Mode group position. */ -#define AC_INTMODE0_bm (1<<6) /* Interrupt Mode bit 0 mask. */ -#define AC_INTMODE0_bp 6 /* Interrupt Mode bit 0 position. */ -#define AC_INTMODE1_bm (1<<7) /* Interrupt Mode bit 1 mask. */ -#define AC_INTMODE1_bp 7 /* Interrupt Mode bit 1 position. */ - -#define AC_INTLVL_gm 0x30 /* Interrupt Level group mask. */ -#define AC_INTLVL_gp 4 /* Interrupt Level group position. */ -#define AC_INTLVL0_bm (1<<4) /* Interrupt Level bit 0 mask. */ -#define AC_INTLVL0_bp 4 /* Interrupt Level bit 0 position. */ -#define AC_INTLVL1_bm (1<<5) /* Interrupt Level bit 1 mask. */ -#define AC_INTLVL1_bp 5 /* Interrupt Level bit 1 position. */ - -#define AC_HSMODE_bm 0x08 /* High-speed Mode bit mask. */ -#define AC_HSMODE_bp 3 /* High-speed Mode bit position. */ - -#define AC_HYSMODE_gm 0x06 /* Hysteresis Mode group mask. */ -#define AC_HYSMODE_gp 1 /* Hysteresis Mode group position. */ -#define AC_HYSMODE0_bm (1<<1) /* Hysteresis Mode bit 0 mask. */ -#define AC_HYSMODE0_bp 1 /* Hysteresis Mode bit 0 position. */ -#define AC_HYSMODE1_bm (1<<2) /* Hysteresis Mode bit 1 mask. */ -#define AC_HYSMODE1_bp 2 /* Hysteresis Mode bit 1 position. */ - -#define AC_ENABLE_bm 0x01 /* Enable bit mask. */ -#define AC_ENABLE_bp 0 /* Enable bit position. */ - - -/* AC.AC1CTRL bit masks and bit positions */ -/* AC_INTMODE_gm Predefined. */ -/* AC_INTMODE_gp Predefined. */ -/* AC_INTMODE0_bm Predefined. */ -/* AC_INTMODE0_bp Predefined. */ -/* AC_INTMODE1_bm Predefined. */ -/* AC_INTMODE1_bp Predefined. */ - -/* AC_INTLVL_gm Predefined. */ -/* AC_INTLVL_gp Predefined. */ -/* AC_INTLVL0_bm Predefined. */ -/* AC_INTLVL0_bp Predefined. */ -/* AC_INTLVL1_bm Predefined. */ -/* AC_INTLVL1_bp Predefined. */ - -/* AC_HSMODE_bm Predefined. */ -/* AC_HSMODE_bp Predefined. */ - -/* AC_HYSMODE_gm Predefined. */ -/* AC_HYSMODE_gp Predefined. */ -/* AC_HYSMODE0_bm Predefined. */ -/* AC_HYSMODE0_bp Predefined. */ -/* AC_HYSMODE1_bm Predefined. */ -/* AC_HYSMODE1_bp Predefined. */ - -/* AC_ENABLE_bm Predefined. */ -/* AC_ENABLE_bp Predefined. */ - - -/* AC.AC0MUXCTRL bit masks and bit positions */ -#define AC_MUXPOS_gm 0x38 /* MUX Positive Input group mask. */ -#define AC_MUXPOS_gp 3 /* MUX Positive Input group position. */ -#define AC_MUXPOS0_bm (1<<3) /* MUX Positive Input bit 0 mask. */ -#define AC_MUXPOS0_bp 3 /* MUX Positive Input bit 0 position. */ -#define AC_MUXPOS1_bm (1<<4) /* MUX Positive Input bit 1 mask. */ -#define AC_MUXPOS1_bp 4 /* MUX Positive Input bit 1 position. */ -#define AC_MUXPOS2_bm (1<<5) /* MUX Positive Input bit 2 mask. */ -#define AC_MUXPOS2_bp 5 /* MUX Positive Input bit 2 position. */ - -#define AC_MUXNEG_gm 0x07 /* MUX Negative Input group mask. */ -#define AC_MUXNEG_gp 0 /* MUX Negative Input group position. */ -#define AC_MUXNEG0_bm (1<<0) /* MUX Negative Input bit 0 mask. */ -#define AC_MUXNEG0_bp 0 /* MUX Negative Input bit 0 position. */ -#define AC_MUXNEG1_bm (1<<1) /* MUX Negative Input bit 1 mask. */ -#define AC_MUXNEG1_bp 1 /* MUX Negative Input bit 1 position. */ -#define AC_MUXNEG2_bm (1<<2) /* MUX Negative Input bit 2 mask. */ -#define AC_MUXNEG2_bp 2 /* MUX Negative Input bit 2 position. */ - - -/* AC.AC1MUXCTRL bit masks and bit positions */ -/* AC_MUXPOS_gm Predefined. */ -/* AC_MUXPOS_gp Predefined. */ -/* AC_MUXPOS0_bm Predefined. */ -/* AC_MUXPOS0_bp Predefined. */ -/* AC_MUXPOS1_bm Predefined. */ -/* AC_MUXPOS1_bp Predefined. */ -/* AC_MUXPOS2_bm Predefined. */ -/* AC_MUXPOS2_bp Predefined. */ - -/* AC_MUXNEG_gm Predefined. */ -/* AC_MUXNEG_gp Predefined. */ -/* AC_MUXNEG0_bm Predefined. */ -/* AC_MUXNEG0_bp Predefined. */ -/* AC_MUXNEG1_bm Predefined. */ -/* AC_MUXNEG1_bp Predefined. */ -/* AC_MUXNEG2_bm Predefined. */ -/* AC_MUXNEG2_bp Predefined. */ - - -/* AC.CTRLA bit masks and bit positions */ -#define AC_AC0OUT_bm 0x01 /* Comparator 0 Output Enable bit mask. */ -#define AC_AC0OUT_bp 0 /* Comparator 0 Output Enable bit position. */ - - -/* AC.CTRLB bit masks and bit positions */ -#define AC_SCALEFAC_gm 0x3F /* VCC Voltage Scaler Factor group mask. */ -#define AC_SCALEFAC_gp 0 /* VCC Voltage Scaler Factor group position. */ -#define AC_SCALEFAC0_bm (1<<0) /* VCC Voltage Scaler Factor bit 0 mask. */ -#define AC_SCALEFAC0_bp 0 /* VCC Voltage Scaler Factor bit 0 position. */ -#define AC_SCALEFAC1_bm (1<<1) /* VCC Voltage Scaler Factor bit 1 mask. */ -#define AC_SCALEFAC1_bp 1 /* VCC Voltage Scaler Factor bit 1 position. */ -#define AC_SCALEFAC2_bm (1<<2) /* VCC Voltage Scaler Factor bit 2 mask. */ -#define AC_SCALEFAC2_bp 2 /* VCC Voltage Scaler Factor bit 2 position. */ -#define AC_SCALEFAC3_bm (1<<3) /* VCC Voltage Scaler Factor bit 3 mask. */ -#define AC_SCALEFAC3_bp 3 /* VCC Voltage Scaler Factor bit 3 position. */ -#define AC_SCALEFAC4_bm (1<<4) /* VCC Voltage Scaler Factor bit 4 mask. */ -#define AC_SCALEFAC4_bp 4 /* VCC Voltage Scaler Factor bit 4 position. */ -#define AC_SCALEFAC5_bm (1<<5) /* VCC Voltage Scaler Factor bit 5 mask. */ -#define AC_SCALEFAC5_bp 5 /* VCC Voltage Scaler Factor bit 5 position. */ - - -/* AC.WINCTRL bit masks and bit positions */ -#define AC_WEN_bm 0x10 /* Window Mode Enable bit mask. */ -#define AC_WEN_bp 4 /* Window Mode Enable bit position. */ - -#define AC_WINTMODE_gm 0x0C /* Window Interrupt Mode group mask. */ -#define AC_WINTMODE_gp 2 /* Window Interrupt Mode group position. */ -#define AC_WINTMODE0_bm (1<<2) /* Window Interrupt Mode bit 0 mask. */ -#define AC_WINTMODE0_bp 2 /* Window Interrupt Mode bit 0 position. */ -#define AC_WINTMODE1_bm (1<<3) /* Window Interrupt Mode bit 1 mask. */ -#define AC_WINTMODE1_bp 3 /* Window Interrupt Mode bit 1 position. */ - -#define AC_WINTLVL_gm 0x03 /* Window Interrupt Level group mask. */ -#define AC_WINTLVL_gp 0 /* Window Interrupt Level group position. */ -#define AC_WINTLVL0_bm (1<<0) /* Window Interrupt Level bit 0 mask. */ -#define AC_WINTLVL0_bp 0 /* Window Interrupt Level bit 0 position. */ -#define AC_WINTLVL1_bm (1<<1) /* Window Interrupt Level bit 1 mask. */ -#define AC_WINTLVL1_bp 1 /* Window Interrupt Level bit 1 position. */ - - -/* AC.STATUS bit masks and bit positions */ -#define AC_WSTATE_gm 0xC0 /* Window Mode State group mask. */ -#define AC_WSTATE_gp 6 /* Window Mode State group position. */ -#define AC_WSTATE0_bm (1<<6) /* Window Mode State bit 0 mask. */ -#define AC_WSTATE0_bp 6 /* Window Mode State bit 0 position. */ -#define AC_WSTATE1_bm (1<<7) /* Window Mode State bit 1 mask. */ -#define AC_WSTATE1_bp 7 /* Window Mode State bit 1 position. */ - -#define AC_AC1STATE_bm 0x20 /* Comparator 1 State bit mask. */ -#define AC_AC1STATE_bp 5 /* Comparator 1 State bit position. */ - -#define AC_AC0STATE_bm 0x10 /* Comparator 0 State bit mask. */ -#define AC_AC0STATE_bp 4 /* Comparator 0 State bit position. */ - -#define AC_WIF_bm 0x04 /* Window Mode Interrupt Flag bit mask. */ -#define AC_WIF_bp 2 /* Window Mode Interrupt Flag bit position. */ - -#define AC_AC1IF_bm 0x02 /* Comparator 1 Interrupt Flag bit mask. */ -#define AC_AC1IF_bp 1 /* Comparator 1 Interrupt Flag bit position. */ - -#define AC_AC0IF_bm 0x01 /* Comparator 0 Interrupt Flag bit mask. */ -#define AC_AC0IF_bp 0 /* Comparator 0 Interrupt Flag bit position. */ - - -/* ADC - Analog/Digital Converter */ -/* ADC_CH.CTRL bit masks and bit positions */ -#define ADC_CH_START_bm 0x80 /* Channel Start Conversion bit mask. */ -#define ADC_CH_START_bp 7 /* Channel Start Conversion bit position. */ - -#define ADC_CH_GAINFAC_gm 0x1C /* Gain Factor group mask. */ -#define ADC_CH_GAINFAC_gp 2 /* Gain Factor group position. */ -#define ADC_CH_GAINFAC0_bm (1<<2) /* Gain Factor bit 0 mask. */ -#define ADC_CH_GAINFAC0_bp 2 /* Gain Factor bit 0 position. */ -#define ADC_CH_GAINFAC1_bm (1<<3) /* Gain Factor bit 1 mask. */ -#define ADC_CH_GAINFAC1_bp 3 /* Gain Factor bit 1 position. */ -#define ADC_CH_GAINFAC2_bm (1<<4) /* Gain Factor bit 2 mask. */ -#define ADC_CH_GAINFAC2_bp 4 /* Gain Factor bit 2 position. */ - -#define ADC_CH_INPUTMODE_gm 0x03 /* Input Mode Select group mask. */ -#define ADC_CH_INPUTMODE_gp 0 /* Input Mode Select group position. */ -#define ADC_CH_INPUTMODE0_bm (1<<0) /* Input Mode Select bit 0 mask. */ -#define ADC_CH_INPUTMODE0_bp 0 /* Input Mode Select bit 0 position. */ -#define ADC_CH_INPUTMODE1_bm (1<<1) /* Input Mode Select bit 1 mask. */ -#define ADC_CH_INPUTMODE1_bp 1 /* Input Mode Select bit 1 position. */ - - -/* ADC_CH.MUXCTRL bit masks and bit positions */ -#define ADC_CH_MUXPOS_gm 0x78 /* Positive Input Select group mask. */ -#define ADC_CH_MUXPOS_gp 3 /* Positive Input Select group position. */ -#define ADC_CH_MUXPOS0_bm (1<<3) /* Positive Input Select bit 0 mask. */ -#define ADC_CH_MUXPOS0_bp 3 /* Positive Input Select bit 0 position. */ -#define ADC_CH_MUXPOS1_bm (1<<4) /* Positive Input Select bit 1 mask. */ -#define ADC_CH_MUXPOS1_bp 4 /* Positive Input Select bit 1 position. */ -#define ADC_CH_MUXPOS2_bm (1<<5) /* Positive Input Select bit 2 mask. */ -#define ADC_CH_MUXPOS2_bp 5 /* Positive Input Select bit 2 position. */ -#define ADC_CH_MUXPOS3_bm (1<<6) /* Positive Input Select bit 3 mask. */ -#define ADC_CH_MUXPOS3_bp 6 /* Positive Input Select bit 3 position. */ -#define ADC_CH_MUXPOS4_bm (1<<7) /* Positive Input Select bit 3 mask. */ -#define ADC_CH_MUXPOS4_bp 7 /* Positive Input Select bit 3 position. */ - -#define ADC_CH_MUXINT_gm 0x78 /* Internal Input Select group mask. */ -#define ADC_CH_MUXINT_gp 3 /* Internal Input Select group position. */ -#define ADC_CH_MUXINT0_bm (1<<3) /* Internal Input Select bit 0 mask. */ -#define ADC_CH_MUXINT0_bp 3 /* Internal Input Select bit 0 position. */ -#define ADC_CH_MUXINT1_bm (1<<4) /* Internal Input Select bit 1 mask. */ -#define ADC_CH_MUXINT1_bp 4 /* Internal Input Select bit 1 position. */ -#define ADC_CH_MUXINT2_bm (1<<5) /* Internal Input Select bit 2 mask. */ -#define ADC_CH_MUXINT2_bp 5 /* Internal Input Select bit 2 position. */ -#define ADC_CH_MUXINT3_bm (1<<6) /* Internal Input Select bit 3 mask. */ -#define ADC_CH_MUXINT3_bp 6 /* Internal Input Select bit 3 position. */ - -#define ADC_CH_MUXNEG_gm 0x03 /* Negative Input Select group mask. */ -#define ADC_CH_MUXNEG_gp 0 /* Negative Input Select group position. */ -#define ADC_CH_MUXNEG0_bm (1<<0) /* Negative Input Select bit 0 mask. */ -#define ADC_CH_MUXNEG0_bp 0 /* Negative Input Select bit 0 position. */ -#define ADC_CH_MUXNEG1_bm (1<<1) /* Negative Input Select bit 1 mask. */ -#define ADC_CH_MUXNEG1_bp 1 /* Negative Input Select bit 1 position. */ - - -/* ADC_CH.INTCTRL bit masks and bit positions */ -#define ADC_CH_INTMODE_gm 0x0C /* Interrupt Mode group mask. */ -#define ADC_CH_INTMODE_gp 2 /* Interrupt Mode group position. */ -#define ADC_CH_INTMODE0_bm (1<<2) /* Interrupt Mode bit 0 mask. */ -#define ADC_CH_INTMODE0_bp 2 /* Interrupt Mode bit 0 position. */ -#define ADC_CH_INTMODE1_bm (1<<3) /* Interrupt Mode bit 1 mask. */ -#define ADC_CH_INTMODE1_bp 3 /* Interrupt Mode bit 1 position. */ - -#define ADC_CH_INTLVL_gm 0x03 /* Interrupt Level group mask. */ -#define ADC_CH_INTLVL_gp 0 /* Interrupt Level group position. */ -#define ADC_CH_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */ -#define ADC_CH_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */ -#define ADC_CH_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ -#define ADC_CH_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */ - - -/* ADC_CH.INTFLAGS bit masks and bit positions */ -#define ADC_CH_CHIF_bm 0x01 /* Channel Interrupt Flag bit mask. */ -#define ADC_CH_CHIF_bp 0 /* Channel Interrupt Flag bit position. */ - - -/* ADC.CTRLA bit masks and bit positions */ -#define ADC_CH0START_bm 0x04 /* Channel 0 Start Conversion bit mask. */ -#define ADC_CH0START_bp 2 /* Channel 0 Start Conversion bit position. */ - -#define ADC_FLUSH_bm 0x02 /* ADC Flush bit mask. */ -#define ADC_FLUSH_bp 1 /* ADC Flush bit position. */ - -#define ADC_ENABLE_bm 0x01 /* Enable ADC bit mask. */ -#define ADC_ENABLE_bp 0 /* Enable ADC bit position. */ - - -/* ADC.CTRLB bit masks and bit positions */ -#define ADC_IMPMODE_bm 0x80 /* Impedance Mode bit mask. */ -#define ADC_IMPMODE_bp 7 /* Impedance Mode bit position. */ - -#define ADC_CURRENT_bm 0x60 /* Current bit mask. */ -#define ADC_CURRENT1_bp 6 /* Current bit position. */ -#define ADC_CURRENT0_bp 5 /* Current bit position. */ - -#define ADC_CONMODE_bm 0x10 /* Conversion Mode bit mask. */ -#define ADC_CONMODE_bp 4 /* Conversion Mode bit position. */ - -#define ADC_FREERUN_bm 0x08 /* Free Running Mode Enable bit mask. */ -#define ADC_FREERUN_bp 3 /* Free Running Mode Enable bit position. */ - -#define ADC_RESOLUTION_gm 0x06 /* Result Resolution group mask. */ -#define ADC_RESOLUTION_gp 1 /* Result Resolution group position. */ -#define ADC_RESOLUTION0_bm (1<<1) /* Result Resolution bit 0 mask. */ -#define ADC_RESOLUTION0_bp 1 /* Result Resolution bit 0 position. */ -#define ADC_RESOLUTION1_bm (1<<2) /* Result Resolution bit 1 mask. */ -#define ADC_RESOLUTION1_bp 2 /* Result Resolution bit 1 position. */ - - -/* ADC.REFCTRL bit masks and bit positions */ -#define ADC_REFSEL_gm 0x70 /* Reference Selection group mask. */ -#define ADC_REFSEL_gp 4 /* Reference Selection group position. */ -#define ADC_REFSEL0_bm (1<<4) /* Reference Selection bit 0 mask. */ -#define ADC_REFSEL0_bp 4 /* Reference Selection bit 0 position. */ -#define ADC_REFSEL1_bm (1<<5) /* Reference Selection bit 1 mask. */ -#define ADC_REFSEL1_bp 5 /* Reference Selection bit 1 position. */ -#define ADC_REFSEL2_bm (1<<6) /* Reference Selection bit 2 mask. */ -#define ADC_REFSEL2_bp 6 /* Reference Selection bit 2 position. */ - -#define ADC_BANDGAP_bm 0x02 /* Bandgap enable bit mask. */ -#define ADC_BANDGAP_bp 1 /* Bandgap enable bit position. */ - -#define ADC_TEMPREF_bm 0x01 /* Temperature Reference Enable bit mask. */ -#define ADC_TEMPREF_bp 0 /* Temperature Reference Enable bit position. */ - - -/* ADC.EVCTRL bit masks and bit positions */ -#define ADC_SWEEP_gm 0xC0 /* Channel Sweep Selection group mask. */ -#define ADC_SWEEP_gp 6 /* Channel Sweep Selection group position. */ -#define ADC_SWEEP0_bm (1<<6) /* Channel Sweep Selection bit 0 mask. */ -#define ADC_SWEEP0_bp 6 /* Channel Sweep Selection bit 0 position. */ -#define ADC_SWEEP1_bm (1<<7) /* Channel Sweep Selection bit 1 mask. */ -#define ADC_SWEEP1_bp 7 /* Channel Sweep Selection bit 1 position. */ - -#define ADC_EVSEL_gm 0x38 /* Event Input Select group mask. */ -#define ADC_EVSEL_gp 3 /* Event Input Select group position. */ -#define ADC_EVSEL0_bm (1<<3) /* Event Input Select bit 0 mask. */ -#define ADC_EVSEL0_bp 3 /* Event Input Select bit 0 position. */ -#define ADC_EVSEL1_bm (1<<4) /* Event Input Select bit 1 mask. */ -#define ADC_EVSEL1_bp 4 /* Event Input Select bit 1 position. */ -#define ADC_EVSEL2_bm (1<<5) /* Event Input Select bit 2 mask. */ -#define ADC_EVSEL2_bp 5 /* Event Input Select bit 2 position. */ - -#define ADC_EVACT_gm 0x07 /* Event Action Select group mask. */ -#define ADC_EVACT_gp 0 /* Event Action Select group position. */ -#define ADC_EVACT0_bm (1<<0) /* Event Action Select bit 0 mask. */ -#define ADC_EVACT0_bp 0 /* Event Action Select bit 0 position. */ -#define ADC_EVACT1_bm (1<<1) /* Event Action Select bit 1 mask. */ -#define ADC_EVACT1_bp 1 /* Event Action Select bit 1 position. */ -#define ADC_EVACT2_bm (1<<2) /* Event Action Select bit 2 mask. */ -#define ADC_EVACT2_bp 2 /* Event Action Select bit 2 position. */ - - -/* ADC.PRESCALER bit masks and bit positions */ -#define ADC_PRESCALER_gm 0x07 /* Clock Prescaler Selection group mask. */ -#define ADC_PRESCALER_gp 0 /* Clock Prescaler Selection group position. */ -#define ADC_PRESCALER0_bm (1<<0) /* Clock Prescaler Selection bit 0 mask. */ -#define ADC_PRESCALER0_bp 0 /* Clock Prescaler Selection bit 0 position. */ -#define ADC_PRESCALER1_bm (1<<1) /* Clock Prescaler Selection bit 1 mask. */ -#define ADC_PRESCALER1_bp 1 /* Clock Prescaler Selection bit 1 position. */ -#define ADC_PRESCALER2_bm (1<<2) /* Clock Prescaler Selection bit 2 mask. */ -#define ADC_PRESCALER2_bp 2 /* Clock Prescaler Selection bit 2 position. */ - - -/* ADC.INTFLAGS bit masks and bit positions */ -#define ADC_CH0IF_bm 0x01 /* Channel 0 Interrupt Flag bit mask. */ -#define ADC_CH0IF_bp 0 /* Channel 0 Interrupt Flag bit position. */ - - -/* RTC - Real-Time Clounter */ -/* RTC.CTRL bit masks and bit positions */ -#define RTC_PRESCALER_gm 0x07 /* Prescaling Factor group mask. */ -#define RTC_PRESCALER_gp 0 /* Prescaling Factor group position. */ -#define RTC_PRESCALER0_bm (1<<0) /* Prescaling Factor bit 0 mask. */ -#define RTC_PRESCALER0_bp 0 /* Prescaling Factor bit 0 position. */ -#define RTC_PRESCALER1_bm (1<<1) /* Prescaling Factor bit 1 mask. */ -#define RTC_PRESCALER1_bp 1 /* Prescaling Factor bit 1 position. */ -#define RTC_PRESCALER2_bm (1<<2) /* Prescaling Factor bit 2 mask. */ -#define RTC_PRESCALER2_bp 2 /* Prescaling Factor bit 2 position. */ - - -/* RTC.STATUS bit masks and bit positions */ -#define RTC_SYNCBUSY_bm 0x01 /* Synchronization Busy Flag bit mask. */ -#define RTC_SYNCBUSY_bp 0 /* Synchronization Busy Flag bit position. */ - - -/* RTC.INTCTRL bit masks and bit positions */ -#define RTC_COMPINTLVL_gm 0x0C /* Compare Match Interrupt Level group mask. */ -#define RTC_COMPINTLVL_gp 2 /* Compare Match Interrupt Level group position. */ -#define RTC_COMPINTLVL0_bm (1<<2) /* Compare Match Interrupt Level bit 0 mask. */ -#define RTC_COMPINTLVL0_bp 2 /* Compare Match Interrupt Level bit 0 position. */ -#define RTC_COMPINTLVL1_bm (1<<3) /* Compare Match Interrupt Level bit 1 mask. */ -#define RTC_COMPINTLVL1_bp 3 /* Compare Match Interrupt Level bit 1 position. */ - -#define RTC_OVFINTLVL_gm 0x03 /* Overflow Interrupt Level group mask. */ -#define RTC_OVFINTLVL_gp 0 /* Overflow Interrupt Level group position. */ -#define RTC_OVFINTLVL0_bm (1<<0) /* Overflow Interrupt Level bit 0 mask. */ -#define RTC_OVFINTLVL0_bp 0 /* Overflow Interrupt Level bit 0 position. */ -#define RTC_OVFINTLVL1_bm (1<<1) /* Overflow Interrupt Level bit 1 mask. */ -#define RTC_OVFINTLVL1_bp 1 /* Overflow Interrupt Level bit 1 position. */ - - -/* RTC.INTFLAGS bit masks and bit positions */ -#define RTC_COMPIF_bm 0x02 /* Compare Match Interrupt Flag bit mask. */ -#define RTC_COMPIF_bp 1 /* Compare Match Interrupt Flag bit position. */ - -#define RTC_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ -#define RTC_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ - - -/* EBI - External Bus Interface */ -/* EBI_CS.CTRLA bit masks and bit positions */ -#define EBI_CS_ASIZE_gm 0x7C /* Address Size group mask. */ -#define EBI_CS_ASIZE_gp 2 /* Address Size group position. */ -#define EBI_CS_ASIZE0_bm (1<<2) /* Address Size bit 0 mask. */ -#define EBI_CS_ASIZE0_bp 2 /* Address Size bit 0 position. */ -#define EBI_CS_ASIZE1_bm (1<<3) /* Address Size bit 1 mask. */ -#define EBI_CS_ASIZE1_bp 3 /* Address Size bit 1 position. */ -#define EBI_CS_ASIZE2_bm (1<<4) /* Address Size bit 2 mask. */ -#define EBI_CS_ASIZE2_bp 4 /* Address Size bit 2 position. */ -#define EBI_CS_ASIZE3_bm (1<<5) /* Address Size bit 3 mask. */ -#define EBI_CS_ASIZE3_bp 5 /* Address Size bit 3 position. */ -#define EBI_CS_ASIZE4_bm (1<<6) /* Address Size bit 4 mask. */ -#define EBI_CS_ASIZE4_bp 6 /* Address Size bit 4 position. */ - -#define EBI_CS_MODE_gm 0x03 /* Memory Mode group mask. */ -#define EBI_CS_MODE_gp 0 /* Memory Mode group position. */ -#define EBI_CS_MODE0_bm (1<<0) /* Memory Mode bit 0 mask. */ -#define EBI_CS_MODE0_bp 0 /* Memory Mode bit 0 position. */ -#define EBI_CS_MODE1_bm (1<<1) /* Memory Mode bit 1 mask. */ -#define EBI_CS_MODE1_bp 1 /* Memory Mode bit 1 position. */ - - -/* EBI_CS.CTRLB bit masks and bit positions */ -#define EBI_CS_SRWS_gm 0x07 /* SRAM Wait State Cycles group mask. */ -#define EBI_CS_SRWS_gp 0 /* SRAM Wait State Cycles group position. */ -#define EBI_CS_SRWS0_bm (1<<0) /* SRAM Wait State Cycles bit 0 mask. */ -#define EBI_CS_SRWS0_bp 0 /* SRAM Wait State Cycles bit 0 position. */ -#define EBI_CS_SRWS1_bm (1<<1) /* SRAM Wait State Cycles bit 1 mask. */ -#define EBI_CS_SRWS1_bp 1 /* SRAM Wait State Cycles bit 1 position. */ -#define EBI_CS_SRWS2_bm (1<<2) /* SRAM Wait State Cycles bit 2 mask. */ -#define EBI_CS_SRWS2_bp 2 /* SRAM Wait State Cycles bit 2 position. */ - -#define EBI_CS_SDINITDONE_bm 0x80 /* SDRAM Initialization Done bit mask. */ -#define EBI_CS_SDINITDONE_bp 7 /* SDRAM Initialization Done bit position. */ - -#define EBI_CS_SDSREN_bm 0x04 /* SDRAM Self-refresh Enable bit mask. */ -#define EBI_CS_SDSREN_bp 2 /* SDRAM Self-refresh Enable bit position. */ - -#define EBI_CS_SDMODE_gm 0x03 /* SDRAM Mode group mask. */ -#define EBI_CS_SDMODE_gp 0 /* SDRAM Mode group position. */ -#define EBI_CS_SDMODE0_bm (1<<0) /* SDRAM Mode bit 0 mask. */ -#define EBI_CS_SDMODE0_bp 0 /* SDRAM Mode bit 0 position. */ -#define EBI_CS_SDMODE1_bm (1<<1) /* SDRAM Mode bit 1 mask. */ -#define EBI_CS_SDMODE1_bp 1 /* SDRAM Mode bit 1 position. */ - - -/* EBI.CTRL bit masks and bit positions */ -#define EBI_SDDATAW_gm 0xC0 /* SDRAM Data Width Setting group mask. */ -#define EBI_SDDATAW_gp 6 /* SDRAM Data Width Setting group position. */ -#define EBI_SDDATAW0_bm (1<<6) /* SDRAM Data Width Setting bit 0 mask. */ -#define EBI_SDDATAW0_bp 6 /* SDRAM Data Width Setting bit 0 position. */ -#define EBI_SDDATAW1_bm (1<<7) /* SDRAM Data Width Setting bit 1 mask. */ -#define EBI_SDDATAW1_bp 7 /* SDRAM Data Width Setting bit 1 position. */ - -#define EBI_LPCMODE_gm 0x30 /* SRAM LPC Mode group mask. */ -#define EBI_LPCMODE_gp 4 /* SRAM LPC Mode group position. */ -#define EBI_LPCMODE0_bm (1<<4) /* SRAM LPC Mode bit 0 mask. */ -#define EBI_LPCMODE0_bp 4 /* SRAM LPC Mode bit 0 position. */ -#define EBI_LPCMODE1_bm (1<<5) /* SRAM LPC Mode bit 1 mask. */ -#define EBI_LPCMODE1_bp 5 /* SRAM LPC Mode bit 1 position. */ - -#define EBI_SRMODE_gm 0x0C /* SRAM Mode group mask. */ -#define EBI_SRMODE_gp 2 /* SRAM Mode group position. */ -#define EBI_SRMODE0_bm (1<<2) /* SRAM Mode bit 0 mask. */ -#define EBI_SRMODE0_bp 2 /* SRAM Mode bit 0 position. */ -#define EBI_SRMODE1_bm (1<<3) /* SRAM Mode bit 1 mask. */ -#define EBI_SRMODE1_bp 3 /* SRAM Mode bit 1 position. */ - -#define EBI_IFMODE_gm 0x03 /* Interface Mode group mask. */ -#define EBI_IFMODE_gp 0 /* Interface Mode group position. */ -#define EBI_IFMODE0_bm (1<<0) /* Interface Mode bit 0 mask. */ -#define EBI_IFMODE0_bp 0 /* Interface Mode bit 0 position. */ -#define EBI_IFMODE1_bm (1<<1) /* Interface Mode bit 1 mask. */ -#define EBI_IFMODE1_bp 1 /* Interface Mode bit 1 position. */ - - -/* EBI.SDRAMCTRLA bit masks and bit positions */ -#define EBI_SDCAS_bm 0x08 /* SDRAM CAS Latency Setting bit mask. */ -#define EBI_SDCAS_bp 3 /* SDRAM CAS Latency Setting bit position. */ - -#define EBI_SDROW_bm 0x04 /* SDRAM ROW Bits Setting bit mask. */ -#define EBI_SDROW_bp 2 /* SDRAM ROW Bits Setting bit position. */ - -#define EBI_SDCOL_gm 0x03 /* SDRAM Column Bits Setting group mask. */ -#define EBI_SDCOL_gp 0 /* SDRAM Column Bits Setting group position. */ -#define EBI_SDCOL0_bm (1<<0) /* SDRAM Column Bits Setting bit 0 mask. */ -#define EBI_SDCOL0_bp 0 /* SDRAM Column Bits Setting bit 0 position. */ -#define EBI_SDCOL1_bm (1<<1) /* SDRAM Column Bits Setting bit 1 mask. */ -#define EBI_SDCOL1_bp 1 /* SDRAM Column Bits Setting bit 1 position. */ - - -/* EBI.SDRAMCTRLB bit masks and bit positions */ -#define EBI_MRDLY_gm 0xC0 /* SDRAM Mode Register Delay group mask. */ -#define EBI_MRDLY_gp 6 /* SDRAM Mode Register Delay group position. */ -#define EBI_MRDLY0_bm (1<<6) /* SDRAM Mode Register Delay bit 0 mask. */ -#define EBI_MRDLY0_bp 6 /* SDRAM Mode Register Delay bit 0 position. */ -#define EBI_MRDLY1_bm (1<<7) /* SDRAM Mode Register Delay bit 1 mask. */ -#define EBI_MRDLY1_bp 7 /* SDRAM Mode Register Delay bit 1 position. */ - -#define EBI_ROWCYCDLY_gm 0x38 /* SDRAM Row Cycle Delay group mask. */ -#define EBI_ROWCYCDLY_gp 3 /* SDRAM Row Cycle Delay group position. */ -#define EBI_ROWCYCDLY0_bm (1<<3) /* SDRAM Row Cycle Delay bit 0 mask. */ -#define EBI_ROWCYCDLY0_bp 3 /* SDRAM Row Cycle Delay bit 0 position. */ -#define EBI_ROWCYCDLY1_bm (1<<4) /* SDRAM Row Cycle Delay bit 1 mask. */ -#define EBI_ROWCYCDLY1_bp 4 /* SDRAM Row Cycle Delay bit 1 position. */ -#define EBI_ROWCYCDLY2_bm (1<<5) /* SDRAM Row Cycle Delay bit 2 mask. */ -#define EBI_ROWCYCDLY2_bp 5 /* SDRAM Row Cycle Delay bit 2 position. */ - -#define EBI_RPDLY_gm 0x07 /* SDRAM Row-to-Precharge Delay group mask. */ -#define EBI_RPDLY_gp 0 /* SDRAM Row-to-Precharge Delay group position. */ -#define EBI_RPDLY0_bm (1<<0) /* SDRAM Row-to-Precharge Delay bit 0 mask. */ -#define EBI_RPDLY0_bp 0 /* SDRAM Row-to-Precharge Delay bit 0 position. */ -#define EBI_RPDLY1_bm (1<<1) /* SDRAM Row-to-Precharge Delay bit 1 mask. */ -#define EBI_RPDLY1_bp 1 /* SDRAM Row-to-Precharge Delay bit 1 position. */ -#define EBI_RPDLY2_bm (1<<2) /* SDRAM Row-to-Precharge Delay bit 2 mask. */ -#define EBI_RPDLY2_bp 2 /* SDRAM Row-to-Precharge Delay bit 2 position. */ - - -/* EBI.SDRAMCTRLC bit masks and bit positions */ -#define EBI_WRDLY_gm 0xC0 /* SDRAM Write Recovery Delay group mask. */ -#define EBI_WRDLY_gp 6 /* SDRAM Write Recovery Delay group position. */ -#define EBI_WRDLY0_bm (1<<6) /* SDRAM Write Recovery Delay bit 0 mask. */ -#define EBI_WRDLY0_bp 6 /* SDRAM Write Recovery Delay bit 0 position. */ -#define EBI_WRDLY1_bm (1<<7) /* SDRAM Write Recovery Delay bit 1 mask. */ -#define EBI_WRDLY1_bp 7 /* SDRAM Write Recovery Delay bit 1 position. */ - -#define EBI_ESRDLY_gm 0x38 /* SDRAM Exit-Self-refresh-to-Active Delay group mask. */ -#define EBI_ESRDLY_gp 3 /* SDRAM Exit-Self-refresh-to-Active Delay group position. */ -#define EBI_ESRDLY0_bm (1<<3) /* SDRAM Exit-Self-refresh-to-Active Delay bit 0 mask. */ -#define EBI_ESRDLY0_bp 3 /* SDRAM Exit-Self-refresh-to-Active Delay bit 0 position. */ -#define EBI_ESRDLY1_bm (1<<4) /* SDRAM Exit-Self-refresh-to-Active Delay bit 1 mask. */ -#define EBI_ESRDLY1_bp 4 /* SDRAM Exit-Self-refresh-to-Active Delay bit 1 position. */ -#define EBI_ESRDLY2_bm (1<<5) /* SDRAM Exit-Self-refresh-to-Active Delay bit 2 mask. */ -#define EBI_ESRDLY2_bp 5 /* SDRAM Exit-Self-refresh-to-Active Delay bit 2 position. */ - -#define EBI_ROWCOLDLY_gm 0x07 /* SDRAM Row-to-Column Delay group mask. */ -#define EBI_ROWCOLDLY_gp 0 /* SDRAM Row-to-Column Delay group position. */ -#define EBI_ROWCOLDLY0_bm (1<<0) /* SDRAM Row-to-Column Delay bit 0 mask. */ -#define EBI_ROWCOLDLY0_bp 0 /* SDRAM Row-to-Column Delay bit 0 position. */ -#define EBI_ROWCOLDLY1_bm (1<<1) /* SDRAM Row-to-Column Delay bit 1 mask. */ -#define EBI_ROWCOLDLY1_bp 1 /* SDRAM Row-to-Column Delay bit 1 position. */ -#define EBI_ROWCOLDLY2_bm (1<<2) /* SDRAM Row-to-Column Delay bit 2 mask. */ -#define EBI_ROWCOLDLY2_bp 2 /* SDRAM Row-to-Column Delay bit 2 position. */ - - -/* TWI - Two-Wire Interface */ -/* TWI_MASTER.CTRLA bit masks and bit positions */ -#define TWI_MASTER_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ -#define TWI_MASTER_INTLVL_gp 6 /* Interrupt Level group position. */ -#define TWI_MASTER_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ -#define TWI_MASTER_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ -#define TWI_MASTER_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ -#define TWI_MASTER_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ - -#define TWI_MASTER_RIEN_bm 0x20 /* Read Interrupt Enable bit mask. */ -#define TWI_MASTER_RIEN_bp 5 /* Read Interrupt Enable bit position. */ - -#define TWI_MASTER_WIEN_bm 0x10 /* Write Interrupt Enable bit mask. */ -#define TWI_MASTER_WIEN_bp 4 /* Write Interrupt Enable bit position. */ - -#define TWI_MASTER_ENABLE_bm 0x08 /* Enable TWI Master bit mask. */ -#define TWI_MASTER_ENABLE_bp 3 /* Enable TWI Master bit position. */ - - -/* TWI_MASTER.CTRLB bit masks and bit positions */ -#define TWI_MASTER_TIMEOUT_gm 0x0C /* Inactive Bus Timeout group mask. */ -#define TWI_MASTER_TIMEOUT_gp 2 /* Inactive Bus Timeout group position. */ -#define TWI_MASTER_TIMEOUT0_bm (1<<2) /* Inactive Bus Timeout bit 0 mask. */ -#define TWI_MASTER_TIMEOUT0_bp 2 /* Inactive Bus Timeout bit 0 position. */ -#define TWI_MASTER_TIMEOUT1_bm (1<<3) /* Inactive Bus Timeout bit 1 mask. */ -#define TWI_MASTER_TIMEOUT1_bp 3 /* Inactive Bus Timeout bit 1 position. */ - -#define TWI_MASTER_QCEN_bm 0x02 /* Quick Command Enable bit mask. */ -#define TWI_MASTER_QCEN_bp 1 /* Quick Command Enable bit position. */ - -#define TWI_MASTER_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ -#define TWI_MASTER_SMEN_bp 0 /* Smart Mode Enable bit position. */ - - -/* TWI_MASTER.CTRLC bit masks and bit positions */ -#define TWI_MASTER_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ -#define TWI_MASTER_ACKACT_bp 2 /* Acknowledge Action bit position. */ - -#define TWI_MASTER_CMD_gm 0x03 /* Command group mask. */ -#define TWI_MASTER_CMD_gp 0 /* Command group position. */ -#define TWI_MASTER_CMD0_bm (1<<0) /* Command bit 0 mask. */ -#define TWI_MASTER_CMD0_bp 0 /* Command bit 0 position. */ -#define TWI_MASTER_CMD1_bm (1<<1) /* Command bit 1 mask. */ -#define TWI_MASTER_CMD1_bp 1 /* Command bit 1 position. */ - - -/* TWI_MASTER.STATUS bit masks and bit positions */ -#define TWI_MASTER_RIF_bm 0x80 /* Read Interrupt Flag bit mask. */ -#define TWI_MASTER_RIF_bp 7 /* Read Interrupt Flag bit position. */ - -#define TWI_MASTER_WIF_bm 0x40 /* Write Interrupt Flag bit mask. */ -#define TWI_MASTER_WIF_bp 6 /* Write Interrupt Flag bit position. */ - -#define TWI_MASTER_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ -#define TWI_MASTER_CLKHOLD_bp 5 /* Clock Hold bit position. */ - -#define TWI_MASTER_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ -#define TWI_MASTER_RXACK_bp 4 /* Received Acknowledge bit position. */ - -#define TWI_MASTER_ARBLOST_bm 0x08 /* Arbitration Lost bit mask. */ -#define TWI_MASTER_ARBLOST_bp 3 /* Arbitration Lost bit position. */ - -#define TWI_MASTER_BUSERR_bm 0x04 /* Bus Error bit mask. */ -#define TWI_MASTER_BUSERR_bp 2 /* Bus Error bit position. */ - -#define TWI_MASTER_BUSSTATE_gm 0x03 /* Bus State group mask. */ -#define TWI_MASTER_BUSSTATE_gp 0 /* Bus State group position. */ -#define TWI_MASTER_BUSSTATE0_bm (1<<0) /* Bus State bit 0 mask. */ -#define TWI_MASTER_BUSSTATE0_bp 0 /* Bus State bit 0 position. */ -#define TWI_MASTER_BUSSTATE1_bm (1<<1) /* Bus State bit 1 mask. */ -#define TWI_MASTER_BUSSTATE1_bp 1 /* Bus State bit 1 position. */ - - -/* TWI_SLAVE.CTRLA bit masks and bit positions */ -#define TWI_SLAVE_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ -#define TWI_SLAVE_INTLVL_gp 6 /* Interrupt Level group position. */ -#define TWI_SLAVE_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ -#define TWI_SLAVE_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ -#define TWI_SLAVE_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ -#define TWI_SLAVE_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ - -#define TWI_SLAVE_DIEN_bm 0x20 /* Data Interrupt Enable bit mask. */ -#define TWI_SLAVE_DIEN_bp 5 /* Data Interrupt Enable bit position. */ - -#define TWI_SLAVE_APIEN_bm 0x10 /* Address/Stop Interrupt Enable bit mask. */ -#define TWI_SLAVE_APIEN_bp 4 /* Address/Stop Interrupt Enable bit position. */ - -#define TWI_SLAVE_ENABLE_bm 0x08 /* Enable TWI Slave bit mask. */ -#define TWI_SLAVE_ENABLE_bp 3 /* Enable TWI Slave bit position. */ - -#define TWI_SLAVE_PIEN_bm 0x04 /* Stop Interrupt Enable bit mask. */ -#define TWI_SLAVE_PIEN_bp 2 /* Stop Interrupt Enable bit position. */ - -#define TWI_SLAVE_PMEN_bm 0x02 /* Promiscuous Mode Enable bit mask. */ -#define TWI_SLAVE_PMEN_bp 1 /* Promiscuous Mode Enable bit position. */ - -#define TWI_SLAVE_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ -#define TWI_SLAVE_SMEN_bp 0 /* Smart Mode Enable bit position. */ - - -/* TWI_SLAVE.CTRLB bit masks and bit positions */ -#define TWI_SLAVE_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ -#define TWI_SLAVE_ACKACT_bp 2 /* Acknowledge Action bit position. */ - -#define TWI_SLAVE_CMD_gm 0x03 /* Command group mask. */ -#define TWI_SLAVE_CMD_gp 0 /* Command group position. */ -#define TWI_SLAVE_CMD0_bm (1<<0) /* Command bit 0 mask. */ -#define TWI_SLAVE_CMD0_bp 0 /* Command bit 0 position. */ -#define TWI_SLAVE_CMD1_bm (1<<1) /* Command bit 1 mask. */ -#define TWI_SLAVE_CMD1_bp 1 /* Command bit 1 position. */ - - -/* TWI_SLAVE.STATUS bit masks and bit positions */ -#define TWI_SLAVE_DIF_bm 0x80 /* Data Interrupt Flag bit mask. */ -#define TWI_SLAVE_DIF_bp 7 /* Data Interrupt Flag bit position. */ - -#define TWI_SLAVE_APIF_bm 0x40 /* Address/Stop Interrupt Flag bit mask. */ -#define TWI_SLAVE_APIF_bp 6 /* Address/Stop Interrupt Flag bit position. */ - -#define TWI_SLAVE_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ -#define TWI_SLAVE_CLKHOLD_bp 5 /* Clock Hold bit position. */ - -#define TWI_SLAVE_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ -#define TWI_SLAVE_RXACK_bp 4 /* Received Acknowledge bit position. */ - -#define TWI_SLAVE_COLL_bm 0x08 /* Collision bit mask. */ -#define TWI_SLAVE_COLL_bp 3 /* Collision bit position. */ - -#define TWI_SLAVE_BUSERR_bm 0x04 /* Bus Error bit mask. */ -#define TWI_SLAVE_BUSERR_bp 2 /* Bus Error bit position. */ - -#define TWI_SLAVE_DIR_bm 0x02 /* Read/Write Direction bit mask. */ -#define TWI_SLAVE_DIR_bp 1 /* Read/Write Direction bit position. */ - -#define TWI_SLAVE_AP_bm 0x01 /* Slave Address or Stop bit mask. */ -#define TWI_SLAVE_AP_bp 0 /* Slave Address or Stop bit position. */ - - -/* TWI_SLAVE.ADDRMASK bit masks and bit positions */ -#define TWI_SLAVE_ADDRMASK_gm 0xFE /* Address Mask group mask. */ -#define TWI_SLAVE_ADDRMASK_gp 1 /* Address Mask group position. */ -#define TWI_SLAVE_ADDRMASK0_bm (1<<1) /* Address Mask bit 0 mask. */ -#define TWI_SLAVE_ADDRMASK0_bp 1 /* Address Mask bit 0 position. */ -#define TWI_SLAVE_ADDRMASK1_bm (1<<2) /* Address Mask bit 1 mask. */ -#define TWI_SLAVE_ADDRMASK1_bp 2 /* Address Mask bit 1 position. */ -#define TWI_SLAVE_ADDRMASK2_bm (1<<3) /* Address Mask bit 2 mask. */ -#define TWI_SLAVE_ADDRMASK2_bp 3 /* Address Mask bit 2 position. */ -#define TWI_SLAVE_ADDRMASK3_bm (1<<4) /* Address Mask bit 3 mask. */ -#define TWI_SLAVE_ADDRMASK3_bp 4 /* Address Mask bit 3 position. */ -#define TWI_SLAVE_ADDRMASK4_bm (1<<5) /* Address Mask bit 4 mask. */ -#define TWI_SLAVE_ADDRMASK4_bp 5 /* Address Mask bit 4 position. */ -#define TWI_SLAVE_ADDRMASK5_bm (1<<6) /* Address Mask bit 5 mask. */ -#define TWI_SLAVE_ADDRMASK5_bp 6 /* Address Mask bit 5 position. */ -#define TWI_SLAVE_ADDRMASK6_bm (1<<7) /* Address Mask bit 6 mask. */ -#define TWI_SLAVE_ADDRMASK6_bp 7 /* Address Mask bit 6 position. */ - -#define TWI_SLAVE_ADDREN_bm 0x01 /* Address Enable bit mask. */ -#define TWI_SLAVE_ADDREN_bp 0 /* Address Enable bit position. */ - - -/* TWI.CTRL bit masks and bit positions */ -#define TWI_SDAHOLD_bm 0x02 /* SDA Hold Time Enable bit mask. */ -#define TWI_SDAHOLD_bp 1 /* SDA Hold Time Enable bit position. */ - -#define TWI_EDIEN_bm 0x01 /* External Driver Interface Enable bit mask. */ -#define TWI_EDIEN_bp 0 /* External Driver Interface Enable bit position. */ - - -/* PORT - Port Configuration */ -/* PORTCFG.VPCTRLA bit masks and bit positions */ -#define PORTCFG_VP1MAP_gm 0xF0 /* Virtual Port 1 Mapping group mask. */ -#define PORTCFG_VP1MAP_gp 4 /* Virtual Port 1 Mapping group position. */ -#define PORTCFG_VP1MAP0_bm (1<<4) /* Virtual Port 1 Mapping bit 0 mask. */ -#define PORTCFG_VP1MAP0_bp 4 /* Virtual Port 1 Mapping bit 0 position. */ -#define PORTCFG_VP1MAP1_bm (1<<5) /* Virtual Port 1 Mapping bit 1 mask. */ -#define PORTCFG_VP1MAP1_bp 5 /* Virtual Port 1 Mapping bit 1 position. */ -#define PORTCFG_VP1MAP2_bm (1<<6) /* Virtual Port 1 Mapping bit 2 mask. */ -#define PORTCFG_VP1MAP2_bp 6 /* Virtual Port 1 Mapping bit 2 position. */ -#define PORTCFG_VP1MAP3_bm (1<<7) /* Virtual Port 1 Mapping bit 3 mask. */ -#define PORTCFG_VP1MAP3_bp 7 /* Virtual Port 1 Mapping bit 3 position. */ - -#define PORTCFG_VP0MAP_gm 0x0F /* Virtual Port 0 Mapping group mask. */ -#define PORTCFG_VP0MAP_gp 0 /* Virtual Port 0 Mapping group position. */ -#define PORTCFG_VP0MAP0_bm (1<<0) /* Virtual Port 0 Mapping bit 0 mask. */ -#define PORTCFG_VP0MAP0_bp 0 /* Virtual Port 0 Mapping bit 0 position. */ -#define PORTCFG_VP0MAP1_bm (1<<1) /* Virtual Port 0 Mapping bit 1 mask. */ -#define PORTCFG_VP0MAP1_bp 1 /* Virtual Port 0 Mapping bit 1 position. */ -#define PORTCFG_VP0MAP2_bm (1<<2) /* Virtual Port 0 Mapping bit 2 mask. */ -#define PORTCFG_VP0MAP2_bp 2 /* Virtual Port 0 Mapping bit 2 position. */ -#define PORTCFG_VP0MAP3_bm (1<<3) /* Virtual Port 0 Mapping bit 3 mask. */ -#define PORTCFG_VP0MAP3_bp 3 /* Virtual Port 0 Mapping bit 3 position. */ - - -/* PORTCFG.VPCTRLB bit masks and bit positions */ -#define PORTCFG_VP3MAP_gm 0xF0 /* Virtual Port 3 Mapping group mask. */ -#define PORTCFG_VP3MAP_gp 4 /* Virtual Port 3 Mapping group position. */ -#define PORTCFG_VP3MAP0_bm (1<<4) /* Virtual Port 3 Mapping bit 0 mask. */ -#define PORTCFG_VP3MAP0_bp 4 /* Virtual Port 3 Mapping bit 0 position. */ -#define PORTCFG_VP3MAP1_bm (1<<5) /* Virtual Port 3 Mapping bit 1 mask. */ -#define PORTCFG_VP3MAP1_bp 5 /* Virtual Port 3 Mapping bit 1 position. */ -#define PORTCFG_VP3MAP2_bm (1<<6) /* Virtual Port 3 Mapping bit 2 mask. */ -#define PORTCFG_VP3MAP2_bp 6 /* Virtual Port 3 Mapping bit 2 position. */ -#define PORTCFG_VP3MAP3_bm (1<<7) /* Virtual Port 3 Mapping bit 3 mask. */ -#define PORTCFG_VP3MAP3_bp 7 /* Virtual Port 3 Mapping bit 3 position. */ - -#define PORTCFG_VP2MAP_gm 0x0F /* Virtual Port 2 Mapping group mask. */ -#define PORTCFG_VP2MAP_gp 0 /* Virtual Port 2 Mapping group position. */ -#define PORTCFG_VP2MAP0_bm (1<<0) /* Virtual Port 2 Mapping bit 0 mask. */ -#define PORTCFG_VP2MAP0_bp 0 /* Virtual Port 2 Mapping bit 0 position. */ -#define PORTCFG_VP2MAP1_bm (1<<1) /* Virtual Port 2 Mapping bit 1 mask. */ -#define PORTCFG_VP2MAP1_bp 1 /* Virtual Port 2 Mapping bit 1 position. */ -#define PORTCFG_VP2MAP2_bm (1<<2) /* Virtual Port 2 Mapping bit 2 mask. */ -#define PORTCFG_VP2MAP2_bp 2 /* Virtual Port 2 Mapping bit 2 position. */ -#define PORTCFG_VP2MAP3_bm (1<<3) /* Virtual Port 2 Mapping bit 3 mask. */ -#define PORTCFG_VP2MAP3_bp 3 /* Virtual Port 2 Mapping bit 3 position. */ - - -/* PORTCFG.CLKEVOUT bit masks and bit positions */ -#define PORTCFG_CLKOUT_gm 0x03 /* Clock Output Port group mask. */ -#define PORTCFG_CLKOUT_gp 0 /* Clock Output Port group position. */ -#define PORTCFG_CLKOUT0_bm (1<<0) /* Clock Output Port bit 0 mask. */ -#define PORTCFG_CLKOUT0_bp 0 /* Clock Output Port bit 0 position. */ -#define PORTCFG_CLKOUT1_bm (1<<1) /* Clock Output Port bit 1 mask. */ -#define PORTCFG_CLKOUT1_bp 1 /* Clock Output Port bit 1 position. */ - -#define PORTCFG_EVOUT_gm 0x30 /* Event Output Port group mask. */ -#define PORTCFG_EVOUT_gp 4 /* Event Output Port group position. */ -#define PORTCFG_EVOUT0_bm (1<<4) /* Event Output Port bit 0 mask. */ -#define PORTCFG_EVOUT0_bp 4 /* Event Output Port bit 0 position. */ -#define PORTCFG_EVOUT1_bm (1<<5) /* Event Output Port bit 1 mask. */ -#define PORTCFG_EVOUT1_bp 5 /* Event Output Port bit 1 position. */ - - -/* VPORT.INTFLAGS bit masks and bit positions */ -#define VPORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ -#define VPORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ - -#define VPORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ -#define VPORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ - - -/* PORT.INTCTRL bit masks and bit positions */ -#define PORT_INT1LVL_gm 0x0C /* Port Interrupt 1 Level group mask. */ -#define PORT_INT1LVL_gp 2 /* Port Interrupt 1 Level group position. */ -#define PORT_INT1LVL0_bm (1<<2) /* Port Interrupt 1 Level bit 0 mask. */ -#define PORT_INT1LVL0_bp 2 /* Port Interrupt 1 Level bit 0 position. */ -#define PORT_INT1LVL1_bm (1<<3) /* Port Interrupt 1 Level bit 1 mask. */ -#define PORT_INT1LVL1_bp 3 /* Port Interrupt 1 Level bit 1 position. */ - -#define PORT_INT0LVL_gm 0x03 /* Port Interrupt 0 Level group mask. */ -#define PORT_INT0LVL_gp 0 /* Port Interrupt 0 Level group position. */ -#define PORT_INT0LVL0_bm (1<<0) /* Port Interrupt 0 Level bit 0 mask. */ -#define PORT_INT0LVL0_bp 0 /* Port Interrupt 0 Level bit 0 position. */ -#define PORT_INT0LVL1_bm (1<<1) /* Port Interrupt 0 Level bit 1 mask. */ -#define PORT_INT0LVL1_bp 1 /* Port Interrupt 0 Level bit 1 position. */ - - -/* PORT.INTFLAGS bit masks and bit positions */ -#define PORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ -#define PORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ - -#define PORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ -#define PORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ - - -/* PORT.PIN0CTRL bit masks and bit positions */ -#define PORT_SRLEN_bm 0x80 /* Slew Rate Enable bit mask. */ -#define PORT_SRLEN_bp 7 /* Slew Rate Enable bit position. */ - -#define PORT_INVEN_bm 0x40 /* Inverted I/O Enable bit mask. */ -#define PORT_INVEN_bp 6 /* Inverted I/O Enable bit position. */ - -#define PORT_OPC_gm 0x38 /* Output/Pull Configuration group mask. */ -#define PORT_OPC_gp 3 /* Output/Pull Configuration group position. */ -#define PORT_OPC0_bm (1<<3) /* Output/Pull Configuration bit 0 mask. */ -#define PORT_OPC0_bp 3 /* Output/Pull Configuration bit 0 position. */ -#define PORT_OPC1_bm (1<<4) /* Output/Pull Configuration bit 1 mask. */ -#define PORT_OPC1_bp 4 /* Output/Pull Configuration bit 1 position. */ -#define PORT_OPC2_bm (1<<5) /* Output/Pull Configuration bit 2 mask. */ -#define PORT_OPC2_bp 5 /* Output/Pull Configuration bit 2 position. */ - -#define PORT_ISC_gm 0x07 /* Input/Sense Configuration group mask. */ -#define PORT_ISC_gp 0 /* Input/Sense Configuration group position. */ -#define PORT_ISC0_bm (1<<0) /* Input/Sense Configuration bit 0 mask. */ -#define PORT_ISC0_bp 0 /* Input/Sense Configuration bit 0 position. */ -#define PORT_ISC1_bm (1<<1) /* Input/Sense Configuration bit 1 mask. */ -#define PORT_ISC1_bp 1 /* Input/Sense Configuration bit 1 position. */ -#define PORT_ISC2_bm (1<<2) /* Input/Sense Configuration bit 2 mask. */ -#define PORT_ISC2_bp 2 /* Input/Sense Configuration bit 2 position. */ - - -/* PORT.PIN1CTRL bit masks and bit positions */ -/* PORT_SRLEN_bm Predefined. */ -/* PORT_SRLEN_bp Predefined. */ - -/* PORT_INVEN_bm Predefined. */ -/* PORT_INVEN_bp Predefined. */ - -/* PORT_OPC_gm Predefined. */ -/* PORT_OPC_gp Predefined. */ -/* PORT_OPC0_bm Predefined. */ -/* PORT_OPC0_bp Predefined. */ -/* PORT_OPC1_bm Predefined. */ -/* PORT_OPC1_bp Predefined. */ -/* PORT_OPC2_bm Predefined. */ -/* PORT_OPC2_bp Predefined. */ - -/* PORT_ISC_gm Predefined. */ -/* PORT_ISC_gp Predefined. */ -/* PORT_ISC0_bm Predefined. */ -/* PORT_ISC0_bp Predefined. */ -/* PORT_ISC1_bm Predefined. */ -/* PORT_ISC1_bp Predefined. */ -/* PORT_ISC2_bm Predefined. */ -/* PORT_ISC2_bp Predefined. */ - - -/* PORT.PIN2CTRL bit masks and bit positions */ -/* PORT_SRLEN_bm Predefined. */ -/* PORT_SRLEN_bp Predefined. */ - -/* PORT_INVEN_bm Predefined. */ -/* PORT_INVEN_bp Predefined. */ - -/* PORT_OPC_gm Predefined. */ -/* PORT_OPC_gp Predefined. */ -/* PORT_OPC0_bm Predefined. */ -/* PORT_OPC0_bp Predefined. */ -/* PORT_OPC1_bm Predefined. */ -/* PORT_OPC1_bp Predefined. */ -/* PORT_OPC2_bm Predefined. */ -/* PORT_OPC2_bp Predefined. */ - -/* PORT_ISC_gm Predefined. */ -/* PORT_ISC_gp Predefined. */ -/* PORT_ISC0_bm Predefined. */ -/* PORT_ISC0_bp Predefined. */ -/* PORT_ISC1_bm Predefined. */ -/* PORT_ISC1_bp Predefined. */ -/* PORT_ISC2_bm Predefined. */ -/* PORT_ISC2_bp Predefined. */ - - -/* PORT.PIN3CTRL bit masks and bit positions */ -/* PORT_SRLEN_bm Predefined. */ -/* PORT_SRLEN_bp Predefined. */ - -/* PORT_INVEN_bm Predefined. */ -/* PORT_INVEN_bp Predefined. */ - -/* PORT_OPC_gm Predefined. */ -/* PORT_OPC_gp Predefined. */ -/* PORT_OPC0_bm Predefined. */ -/* PORT_OPC0_bp Predefined. */ -/* PORT_OPC1_bm Predefined. */ -/* PORT_OPC1_bp Predefined. */ -/* PORT_OPC2_bm Predefined. */ -/* PORT_OPC2_bp Predefined. */ - -/* PORT_ISC_gm Predefined. */ -/* PORT_ISC_gp Predefined. */ -/* PORT_ISC0_bm Predefined. */ -/* PORT_ISC0_bp Predefined. */ -/* PORT_ISC1_bm Predefined. */ -/* PORT_ISC1_bp Predefined. */ -/* PORT_ISC2_bm Predefined. */ -/* PORT_ISC2_bp Predefined. */ - - -/* PORT.PIN4CTRL bit masks and bit positions */ -/* PORT_SRLEN_bm Predefined. */ -/* PORT_SRLEN_bp Predefined. */ - -/* PORT_INVEN_bm Predefined. */ -/* PORT_INVEN_bp Predefined. */ - -/* PORT_OPC_gm Predefined. */ -/* PORT_OPC_gp Predefined. */ -/* PORT_OPC0_bm Predefined. */ -/* PORT_OPC0_bp Predefined. */ -/* PORT_OPC1_bm Predefined. */ -/* PORT_OPC1_bp Predefined. */ -/* PORT_OPC2_bm Predefined. */ -/* PORT_OPC2_bp Predefined. */ - -/* PORT_ISC_gm Predefined. */ -/* PORT_ISC_gp Predefined. */ -/* PORT_ISC0_bm Predefined. */ -/* PORT_ISC0_bp Predefined. */ -/* PORT_ISC1_bm Predefined. */ -/* PORT_ISC1_bp Predefined. */ -/* PORT_ISC2_bm Predefined. */ -/* PORT_ISC2_bp Predefined. */ - - -/* PORT.PIN5CTRL bit masks and bit positions */ -/* PORT_SRLEN_bm Predefined. */ -/* PORT_SRLEN_bp Predefined. */ - -/* PORT_INVEN_bm Predefined. */ -/* PORT_INVEN_bp Predefined. */ - -/* PORT_OPC_gm Predefined. */ -/* PORT_OPC_gp Predefined. */ -/* PORT_OPC0_bm Predefined. */ -/* PORT_OPC0_bp Predefined. */ -/* PORT_OPC1_bm Predefined. */ -/* PORT_OPC1_bp Predefined. */ -/* PORT_OPC2_bm Predefined. */ -/* PORT_OPC2_bp Predefined. */ - -/* PORT_ISC_gm Predefined. */ -/* PORT_ISC_gp Predefined. */ -/* PORT_ISC0_bm Predefined. */ -/* PORT_ISC0_bp Predefined. */ -/* PORT_ISC1_bm Predefined. */ -/* PORT_ISC1_bp Predefined. */ -/* PORT_ISC2_bm Predefined. */ -/* PORT_ISC2_bp Predefined. */ - - -/* PORT.PIN6CTRL bit masks and bit positions */ -/* PORT_SRLEN_bm Predefined. */ -/* PORT_SRLEN_bp Predefined. */ - -/* PORT_INVEN_bm Predefined. */ -/* PORT_INVEN_bp Predefined. */ - -/* PORT_OPC_gm Predefined. */ -/* PORT_OPC_gp Predefined. */ -/* PORT_OPC0_bm Predefined. */ -/* PORT_OPC0_bp Predefined. */ -/* PORT_OPC1_bm Predefined. */ -/* PORT_OPC1_bp Predefined. */ -/* PORT_OPC2_bm Predefined. */ -/* PORT_OPC2_bp Predefined. */ - -/* PORT_ISC_gm Predefined. */ -/* PORT_ISC_gp Predefined. */ -/* PORT_ISC0_bm Predefined. */ -/* PORT_ISC0_bp Predefined. */ -/* PORT_ISC1_bm Predefined. */ -/* PORT_ISC1_bp Predefined. */ -/* PORT_ISC2_bm Predefined. */ -/* PORT_ISC2_bp Predefined. */ - - -/* PORT.PIN7CTRL bit masks and bit positions */ -/* PORT_SRLEN_bm Predefined. */ -/* PORT_SRLEN_bp Predefined. */ - -/* PORT_INVEN_bm Predefined. */ -/* PORT_INVEN_bp Predefined. */ - -/* PORT_OPC_gm Predefined. */ -/* PORT_OPC_gp Predefined. */ -/* PORT_OPC0_bm Predefined. */ -/* PORT_OPC0_bp Predefined. */ -/* PORT_OPC1_bm Predefined. */ -/* PORT_OPC1_bp Predefined. */ -/* PORT_OPC2_bm Predefined. */ -/* PORT_OPC2_bp Predefined. */ - -/* PORT_ISC_gm Predefined. */ -/* PORT_ISC_gp Predefined. */ -/* PORT_ISC0_bm Predefined. */ -/* PORT_ISC0_bp Predefined. */ -/* PORT_ISC1_bm Predefined. */ -/* PORT_ISC1_bp Predefined. */ -/* PORT_ISC2_bm Predefined. */ -/* PORT_ISC2_bp Predefined. */ - - -/* TC - 16-bit Timer/Counter With PWM */ -/* TC0.CTRLA bit masks and bit positions */ -#define TC0_CLKSEL_gm 0x0F /* Clock Selection group mask. */ -#define TC0_CLKSEL_gp 0 /* Clock Selection group position. */ -#define TC0_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ -#define TC0_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ -#define TC0_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ -#define TC0_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ -#define TC0_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ -#define TC0_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ -#define TC0_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ -#define TC0_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ - - -/* TC0.CTRLB bit masks and bit positions */ -#define TC0_CCDEN_bm 0x80 /* Compare or Capture D Enable bit mask. */ -#define TC0_CCDEN_bp 7 /* Compare or Capture D Enable bit position. */ - -#define TC0_CCCEN_bm 0x40 /* Compare or Capture C Enable bit mask. */ -#define TC0_CCCEN_bp 6 /* Compare or Capture C Enable bit position. */ - -#define TC0_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ -#define TC0_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ - -#define TC0_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ -#define TC0_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ - -#define TC0_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ -#define TC0_WGMODE_gp 0 /* Waveform generation mode group position. */ -#define TC0_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ -#define TC0_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ -#define TC0_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ -#define TC0_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ -#define TC0_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ -#define TC0_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ - - -/* TC0.CTRLC bit masks and bit positions */ -#define TC0_CMPD_bm 0x08 /* Compare D Output Value bit mask. */ -#define TC0_CMPD_bp 3 /* Compare D Output Value bit position. */ - -#define TC0_CMPC_bm 0x04 /* Compare C Output Value bit mask. */ -#define TC0_CMPC_bp 2 /* Compare C Output Value bit position. */ - -#define TC0_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ -#define TC0_CMPB_bp 1 /* Compare B Output Value bit position. */ - -#define TC0_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ -#define TC0_CMPA_bp 0 /* Compare A Output Value bit position. */ - - -/* TC0.CTRLD bit masks and bit positions */ -#define TC0_EVACT_gm 0xE0 /* Event Action group mask. */ -#define TC0_EVACT_gp 5 /* Event Action group position. */ -#define TC0_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ -#define TC0_EVACT0_bp 5 /* Event Action bit 0 position. */ -#define TC0_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ -#define TC0_EVACT1_bp 6 /* Event Action bit 1 position. */ -#define TC0_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ -#define TC0_EVACT2_bp 7 /* Event Action bit 2 position. */ - -#define TC0_EVDLY_bm 0x10 /* Event Delay bit mask. */ -#define TC0_EVDLY_bp 4 /* Event Delay bit position. */ - -#define TC0_EVSEL_gm 0x0F /* Event Source Select group mask. */ -#define TC0_EVSEL_gp 0 /* Event Source Select group position. */ -#define TC0_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ -#define TC0_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ -#define TC0_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ -#define TC0_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ -#define TC0_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ -#define TC0_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ -#define TC0_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ -#define TC0_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ - - -/* TC0.CTRLE bit masks and bit positions */ -#define TC0_DTHM_bm 0x02 /* Dead Time Hold Mode bit mask. */ -#define TC0_DTHM_bp 1 /* Dead Time Hold Mode bit position. */ - -#define TC0_BYTEM_bm 0x01 /* Byte Mode bit mask. */ -#define TC0_BYTEM_bp 0 /* Byte Mode bit position. */ - - -/* TC0.INTCTRLA bit masks and bit positions */ -#define TC0_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ -#define TC0_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ -#define TC0_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ -#define TC0_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ -#define TC0_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ -#define TC0_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ - -#define TC0_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ -#define TC0_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ -#define TC0_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ -#define TC0_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ -#define TC0_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ -#define TC0_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ - - -/* TC0.INTCTRLB bit masks and bit positions */ -#define TC0_CCDINTLVL_gm 0xC0 /* Compare or Capture D Interrupt Level group mask. */ -#define TC0_CCDINTLVL_gp 6 /* Compare or Capture D Interrupt Level group position. */ -#define TC0_CCDINTLVL0_bm (1<<6) /* Compare or Capture D Interrupt Level bit 0 mask. */ -#define TC0_CCDINTLVL0_bp 6 /* Compare or Capture D Interrupt Level bit 0 position. */ -#define TC0_CCDINTLVL1_bm (1<<7) /* Compare or Capture D Interrupt Level bit 1 mask. */ -#define TC0_CCDINTLVL1_bp 7 /* Compare or Capture D Interrupt Level bit 1 position. */ - -#define TC0_CCCINTLVL_gm 0x30 /* Compare or Capture C Interrupt Level group mask. */ -#define TC0_CCCINTLVL_gp 4 /* Compare or Capture C Interrupt Level group position. */ -#define TC0_CCCINTLVL0_bm (1<<4) /* Compare or Capture C Interrupt Level bit 0 mask. */ -#define TC0_CCCINTLVL0_bp 4 /* Compare or Capture C Interrupt Level bit 0 position. */ -#define TC0_CCCINTLVL1_bm (1<<5) /* Compare or Capture C Interrupt Level bit 1 mask. */ -#define TC0_CCCINTLVL1_bp 5 /* Compare or Capture C Interrupt Level bit 1 position. */ - -#define TC0_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ -#define TC0_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ -#define TC0_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ -#define TC0_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ -#define TC0_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ -#define TC0_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ - -#define TC0_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ -#define TC0_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ -#define TC0_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ -#define TC0_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ -#define TC0_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ -#define TC0_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ - - -/* TC0.CTRLFCLR bit masks and bit positions */ -#define TC0_CMD_gm 0x0C /* Command group mask. */ -#define TC0_CMD_gp 2 /* Command group position. */ -#define TC0_CMD0_bm (1<<2) /* Command bit 0 mask. */ -#define TC0_CMD0_bp 2 /* Command bit 0 position. */ -#define TC0_CMD1_bm (1<<3) /* Command bit 1 mask. */ -#define TC0_CMD1_bp 3 /* Command bit 1 position. */ - -#define TC0_LUPD_bm 0x02 /* Lock Update bit mask. */ -#define TC0_LUPD_bp 1 /* Lock Update bit position. */ - -#define TC0_DIR_bm 0x01 /* Direction bit mask. */ -#define TC0_DIR_bp 0 /* Direction bit position. */ - - -/* TC0.CTRLFSET bit masks and bit positions */ -/* TC0_CMD_gm Predefined. */ -/* TC0_CMD_gp Predefined. */ -/* TC0_CMD0_bm Predefined. */ -/* TC0_CMD0_bp Predefined. */ -/* TC0_CMD1_bm Predefined. */ -/* TC0_CMD1_bp Predefined. */ - -/* TC0_LUPD_bm Predefined. */ -/* TC0_LUPD_bp Predefined. */ - -/* TC0_DIR_bm Predefined. */ -/* TC0_DIR_bp Predefined. */ - - -/* TC0.CTRLGCLR bit masks and bit positions */ -#define TC0_CCDBV_bm 0x10 /* Compare or Capture D Buffer Valid bit mask. */ -#define TC0_CCDBV_bp 4 /* Compare or Capture D Buffer Valid bit position. */ - -#define TC0_CCCBV_bm 0x08 /* Compare or Capture C Buffer Valid bit mask. */ -#define TC0_CCCBV_bp 3 /* Compare or Capture C Buffer Valid bit position. */ - -#define TC0_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ -#define TC0_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ - -#define TC0_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ -#define TC0_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ - -#define TC0_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ -#define TC0_PERBV_bp 0 /* Period Buffer Valid bit position. */ - - -/* TC0.CTRLGSET bit masks and bit positions */ -/* TC0_CCDBV_bm Predefined. */ -/* TC0_CCDBV_bp Predefined. */ - -/* TC0_CCCBV_bm Predefined. */ -/* TC0_CCCBV_bp Predefined. */ - -/* TC0_CCBBV_bm Predefined. */ -/* TC0_CCBBV_bp Predefined. */ - -/* TC0_CCABV_bm Predefined. */ -/* TC0_CCABV_bp Predefined. */ - -/* TC0_PERBV_bm Predefined. */ -/* TC0_PERBV_bp Predefined. */ - - -/* TC0.INTFLAGS bit masks and bit positions */ -#define TC0_CCDIF_bm 0x80 /* Compare or Capture D Interrupt Flag bit mask. */ -#define TC0_CCDIF_bp 7 /* Compare or Capture D Interrupt Flag bit position. */ - -#define TC0_CCCIF_bm 0x40 /* Compare or Capture C Interrupt Flag bit mask. */ -#define TC0_CCCIF_bp 6 /* Compare or Capture C Interrupt Flag bit position. */ - -#define TC0_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ -#define TC0_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ - -#define TC0_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ -#define TC0_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ - -#define TC0_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ -#define TC0_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ - -#define TC0_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ -#define TC0_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ - - -/* TC1.CTRLA bit masks and bit positions */ -#define TC1_CLKSEL_gm 0x0F /* Clock Selection group mask. */ -#define TC1_CLKSEL_gp 0 /* Clock Selection group position. */ -#define TC1_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ -#define TC1_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ -#define TC1_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ -#define TC1_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ -#define TC1_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ -#define TC1_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ -#define TC1_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ -#define TC1_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ - - -/* TC1.CTRLB bit masks and bit positions */ -#define TC1_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ -#define TC1_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ - -#define TC1_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ -#define TC1_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ - -#define TC1_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ -#define TC1_WGMODE_gp 0 /* Waveform generation mode group position. */ -#define TC1_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ -#define TC1_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ -#define TC1_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ -#define TC1_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ -#define TC1_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ -#define TC1_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ - - -/* TC1.CTRLC bit masks and bit positions */ -#define TC1_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ -#define TC1_CMPB_bp 1 /* Compare B Output Value bit position. */ - -#define TC1_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ -#define TC1_CMPA_bp 0 /* Compare A Output Value bit position. */ - - -/* TC1.CTRLD bit masks and bit positions */ -#define TC1_EVACT_gm 0xE0 /* Event Action group mask. */ -#define TC1_EVACT_gp 5 /* Event Action group position. */ -#define TC1_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ -#define TC1_EVACT0_bp 5 /* Event Action bit 0 position. */ -#define TC1_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ -#define TC1_EVACT1_bp 6 /* Event Action bit 1 position. */ -#define TC1_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ -#define TC1_EVACT2_bp 7 /* Event Action bit 2 position. */ - -#define TC1_EVDLY_bm 0x10 /* Event Delay bit mask. */ -#define TC1_EVDLY_bp 4 /* Event Delay bit position. */ - -#define TC1_EVSEL_gm 0x0F /* Event Source Select group mask. */ -#define TC1_EVSEL_gp 0 /* Event Source Select group position. */ -#define TC1_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ -#define TC1_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ -#define TC1_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ -#define TC1_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ -#define TC1_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ -#define TC1_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ -#define TC1_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ -#define TC1_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ - - -/* TC1.CTRLE bit masks and bit positions */ -#define TC1_DTHM_bm 0x02 /* Dead Time Hold Mode bit mask. */ -#define TC1_DTHM_bp 1 /* Dead Time Hold Mode bit position. */ - -#define TC1_BYTEM_bm 0x01 /* Byte Mode bit mask. */ -#define TC1_BYTEM_bp 0 /* Byte Mode bit position. */ - - -/* TC1.INTCTRLA bit masks and bit positions */ -#define TC1_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ -#define TC1_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ -#define TC1_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ -#define TC1_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ -#define TC1_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ -#define TC1_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ - -#define TC1_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ -#define TC1_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ -#define TC1_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ -#define TC1_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ -#define TC1_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ -#define TC1_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ - - -/* TC1.INTCTRLB bit masks and bit positions */ -#define TC1_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ -#define TC1_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ -#define TC1_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ -#define TC1_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ -#define TC1_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ -#define TC1_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ - -#define TC1_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ -#define TC1_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ -#define TC1_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ -#define TC1_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ -#define TC1_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ -#define TC1_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ - - -/* TC1.CTRLFCLR bit masks and bit positions */ -#define TC1_CMD_gm 0x0C /* Command group mask. */ -#define TC1_CMD_gp 2 /* Command group position. */ -#define TC1_CMD0_bm (1<<2) /* Command bit 0 mask. */ -#define TC1_CMD0_bp 2 /* Command bit 0 position. */ -#define TC1_CMD1_bm (1<<3) /* Command bit 1 mask. */ -#define TC1_CMD1_bp 3 /* Command bit 1 position. */ - -#define TC1_LUPD_bm 0x02 /* Lock Update bit mask. */ -#define TC1_LUPD_bp 1 /* Lock Update bit position. */ - -#define TC1_DIR_bm 0x01 /* Direction bit mask. */ -#define TC1_DIR_bp 0 /* Direction bit position. */ - - -/* TC1.CTRLFSET bit masks and bit positions */ -/* TC1_CMD_gm Predefined. */ -/* TC1_CMD_gp Predefined. */ -/* TC1_CMD0_bm Predefined. */ -/* TC1_CMD0_bp Predefined. */ -/* TC1_CMD1_bm Predefined. */ -/* TC1_CMD1_bp Predefined. */ - -/* TC1_LUPD_bm Predefined. */ -/* TC1_LUPD_bp Predefined. */ - -/* TC1_DIR_bm Predefined. */ -/* TC1_DIR_bp Predefined. */ - - -/* TC1.CTRLGCLR bit masks and bit positions */ -#define TC1_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ -#define TC1_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ - -#define TC1_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ -#define TC1_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ - -#define TC1_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ -#define TC1_PERBV_bp 0 /* Period Buffer Valid bit position. */ - - -/* TC1.CTRLGSET bit masks and bit positions */ -/* TC1_CCBBV_bm Predefined. */ -/* TC1_CCBBV_bp Predefined. */ - -/* TC1_CCABV_bm Predefined. */ -/* TC1_CCABV_bp Predefined. */ - -/* TC1_PERBV_bm Predefined. */ -/* TC1_PERBV_bp Predefined. */ - - -/* TC1.INTFLAGS bit masks and bit positions */ -#define TC1_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ -#define TC1_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ - -#define TC1_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ -#define TC1_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ - -#define TC1_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ -#define TC1_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ - -#define TC1_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ -#define TC1_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ - - -/* AWEX.CTRL bit masks and bit positions */ -#define AWEX_PGM_bm 0x20 /* Pattern Generation Mode bit mask. */ -#define AWEX_PGM_bp 5 /* Pattern Generation Mode bit position. */ - -#define AWEX_CWCM_bm 0x10 /* Common Waveform Channel Mode bit mask. */ -#define AWEX_CWCM_bp 4 /* Common Waveform Channel Mode bit position. */ - -#define AWEX_DTICCDEN_bm 0x08 /* Dead Time Insertion Compare Channel D Enable bit mask. */ -#define AWEX_DTICCDEN_bp 3 /* Dead Time Insertion Compare Channel D Enable bit position. */ - -#define AWEX_DTICCCEN_bm 0x04 /* Dead Time Insertion Compare Channel C Enable bit mask. */ -#define AWEX_DTICCCEN_bp 2 /* Dead Time Insertion Compare Channel C Enable bit position. */ - -#define AWEX_DTICCBEN_bm 0x02 /* Dead Time Insertion Compare Channel B Enable bit mask. */ -#define AWEX_DTICCBEN_bp 1 /* Dead Time Insertion Compare Channel B Enable bit position. */ - -#define AWEX_DTICCAEN_bm 0x01 /* Dead Time Insertion Compare Channel A Enable bit mask. */ -#define AWEX_DTICCAEN_bp 0 /* Dead Time Insertion Compare Channel A Enable bit position. */ - - -/* AWEX.FDCTRL bit masks and bit positions */ -#define AWEX_FDDBD_bm 0x10 /* Fault Detect on Disable Break Disable bit mask. */ -#define AWEX_FDDBD_bp 4 /* Fault Detect on Disable Break Disable bit position. */ - -#define AWEX_FDMODE_bm 0x04 /* Fault Detect Mode bit mask. */ -#define AWEX_FDMODE_bp 2 /* Fault Detect Mode bit position. */ - -#define AWEX_FDACT_gm 0x03 /* Fault Detect Action group mask. */ -#define AWEX_FDACT_gp 0 /* Fault Detect Action group position. */ -#define AWEX_FDACT0_bm (1<<0) /* Fault Detect Action bit 0 mask. */ -#define AWEX_FDACT0_bp 0 /* Fault Detect Action bit 0 position. */ -#define AWEX_FDACT1_bm (1<<1) /* Fault Detect Action bit 1 mask. */ -#define AWEX_FDACT1_bp 1 /* Fault Detect Action bit 1 position. */ - - -/* AWEX.STATUS bit masks and bit positions */ -#define AWEX_FDF_bm 0x04 /* Fault Detect Flag bit mask. */ -#define AWEX_FDF_bp 2 /* Fault Detect Flag bit position. */ - -#define AWEX_DTHSBUFV_bm 0x02 /* Dead Time High Side Buffer Valid bit mask. */ -#define AWEX_DTHSBUFV_bp 1 /* Dead Time High Side Buffer Valid bit position. */ - -#define AWEX_DTLSBUFV_bm 0x01 /* Dead Time Low Side Buffer Valid bit mask. */ -#define AWEX_DTLSBUFV_bp 0 /* Dead Time Low Side Buffer Valid bit position. */ - - -/* HIRES.CTRL bit masks and bit positions */ -#define HIRES_HREN_gm 0x03 /* High Resolution Enable group mask. */ -#define HIRES_HREN_gp 0 /* High Resolution Enable group position. */ -#define HIRES_HREN0_bm (1<<0) /* High Resolution Enable bit 0 mask. */ -#define HIRES_HREN0_bp 0 /* High Resolution Enable bit 0 position. */ -#define HIRES_HREN1_bm (1<<1) /* High Resolution Enable bit 1 mask. */ -#define HIRES_HREN1_bp 1 /* High Resolution Enable bit 1 position. */ - - -/* USART - Universal Asynchronous Receiver-Transmitter */ -/* USART.STATUS bit masks and bit positions */ -#define USART_RXCIF_bm 0x80 /* Receive Interrupt Flag bit mask. */ -#define USART_RXCIF_bp 7 /* Receive Interrupt Flag bit position. */ - -#define USART_TXCIF_bm 0x40 /* Transmit Interrupt Flag bit mask. */ -#define USART_TXCIF_bp 6 /* Transmit Interrupt Flag bit position. */ - -#define USART_DREIF_bm 0x20 /* Data Register Empty Flag bit mask. */ -#define USART_DREIF_bp 5 /* Data Register Empty Flag bit position. */ - -#define USART_FERR_bm 0x10 /* Frame Error bit mask. */ -#define USART_FERR_bp 4 /* Frame Error bit position. */ - -#define USART_BUFOVF_bm 0x08 /* Buffer Overflow bit mask. */ -#define USART_BUFOVF_bp 3 /* Buffer Overflow bit position. */ - -#define USART_PERR_bm 0x04 /* Parity Error bit mask. */ -#define USART_PERR_bp 2 /* Parity Error bit position. */ - -#define USART_RXB8_bm 0x01 /* Receive Bit 8 bit mask. */ -#define USART_RXB8_bp 0 /* Receive Bit 8 bit position. */ - - -/* USART.CTRLA bit masks and bit positions */ -#define USART_RXCINTLVL_gm 0x30 /* Receive Interrupt Level group mask. */ -#define USART_RXCINTLVL_gp 4 /* Receive Interrupt Level group position. */ -#define USART_RXCINTLVL0_bm (1<<4) /* Receive Interrupt Level bit 0 mask. */ -#define USART_RXCINTLVL0_bp 4 /* Receive Interrupt Level bit 0 position. */ -#define USART_RXCINTLVL1_bm (1<<5) /* Receive Interrupt Level bit 1 mask. */ -#define USART_RXCINTLVL1_bp 5 /* Receive Interrupt Level bit 1 position. */ - -#define USART_TXCINTLVL_gm 0x0C /* Transmit Interrupt Level group mask. */ -#define USART_TXCINTLVL_gp 2 /* Transmit Interrupt Level group position. */ -#define USART_TXCINTLVL0_bm (1<<2) /* Transmit Interrupt Level bit 0 mask. */ -#define USART_TXCINTLVL0_bp 2 /* Transmit Interrupt Level bit 0 position. */ -#define USART_TXCINTLVL1_bm (1<<3) /* Transmit Interrupt Level bit 1 mask. */ -#define USART_TXCINTLVL1_bp 3 /* Transmit Interrupt Level bit 1 position. */ - -#define USART_DREINTLVL_gm 0x03 /* Data Register Empty Interrupt Level group mask. */ -#define USART_DREINTLVL_gp 0 /* Data Register Empty Interrupt Level group position. */ -#define USART_DREINTLVL0_bm (1<<0) /* Data Register Empty Interrupt Level bit 0 mask. */ -#define USART_DREINTLVL0_bp 0 /* Data Register Empty Interrupt Level bit 0 position. */ -#define USART_DREINTLVL1_bm (1<<1) /* Data Register Empty Interrupt Level bit 1 mask. */ -#define USART_DREINTLVL1_bp 1 /* Data Register Empty Interrupt Level bit 1 position. */ - - -/* USART.CTRLB bit masks and bit positions */ -#define USART_RXEN_bm 0x10 /* Receiver Enable bit mask. */ -#define USART_RXEN_bp 4 /* Receiver Enable bit position. */ - -#define USART_TXEN_bm 0x08 /* Transmitter Enable bit mask. */ -#define USART_TXEN_bp 3 /* Transmitter Enable bit position. */ - -#define USART_CLK2X_bm 0x04 /* Double transmission speed bit mask. */ -#define USART_CLK2X_bp 2 /* Double transmission speed bit position. */ - -#define USART_MPCM_bm 0x02 /* Multi-processor Communication Mode bit mask. */ -#define USART_MPCM_bp 1 /* Multi-processor Communication Mode bit position. */ - -#define USART_TXB8_bm 0x01 /* Transmit bit 8 bit mask. */ -#define USART_TXB8_bp 0 /* Transmit bit 8 bit position. */ - - -/* USART.CTRLC bit masks and bit positions */ -#define USART_CMODE_gm 0xC0 /* Communication Mode group mask. */ -#define USART_CMODE_gp 6 /* Communication Mode group position. */ -#define USART_CMODE0_bm (1<<6) /* Communication Mode bit 0 mask. */ -#define USART_CMODE0_bp 6 /* Communication Mode bit 0 position. */ -#define USART_CMODE1_bm (1<<7) /* Communication Mode bit 1 mask. */ -#define USART_CMODE1_bp 7 /* Communication Mode bit 1 position. */ - -#define USART_PMODE_gm 0x30 /* Parity Mode group mask. */ -#define USART_PMODE_gp 4 /* Parity Mode group position. */ -#define USART_PMODE0_bm (1<<4) /* Parity Mode bit 0 mask. */ -#define USART_PMODE0_bp 4 /* Parity Mode bit 0 position. */ -#define USART_PMODE1_bm (1<<5) /* Parity Mode bit 1 mask. */ -#define USART_PMODE1_bp 5 /* Parity Mode bit 1 position. */ - -#define USART_SBMODE_bm 0x08 /* Stop Bit Mode bit mask. */ -#define USART_SBMODE_bp 3 /* Stop Bit Mode bit position. */ - -#define USART_CHSIZE_gm 0x07 /* Character Size group mask. */ -#define USART_CHSIZE_gp 0 /* Character Size group position. */ -#define USART_CHSIZE0_bm (1<<0) /* Character Size bit 0 mask. */ -#define USART_CHSIZE0_bp 0 /* Character Size bit 0 position. */ -#define USART_CHSIZE1_bm (1<<1) /* Character Size bit 1 mask. */ -#define USART_CHSIZE1_bp 1 /* Character Size bit 1 position. */ -#define USART_CHSIZE2_bm (1<<2) /* Character Size bit 2 mask. */ -#define USART_CHSIZE2_bp 2 /* Character Size bit 2 position. */ - - -/* USART.BAUDCTRLA bit masks and bit positions */ -#define USART_BSEL_gm 0xFF /* Baud Rate Selection Bits [7:0] group mask. */ -#define USART_BSEL_gp 0 /* Baud Rate Selection Bits [7:0] group position. */ -#define USART_BSEL0_bm (1<<0) /* Baud Rate Selection Bits [7:0] bit 0 mask. */ -#define USART_BSEL0_bp 0 /* Baud Rate Selection Bits [7:0] bit 0 position. */ -#define USART_BSEL1_bm (1<<1) /* Baud Rate Selection Bits [7:0] bit 1 mask. */ -#define USART_BSEL1_bp 1 /* Baud Rate Selection Bits [7:0] bit 1 position. */ -#define USART_BSEL2_bm (1<<2) /* Baud Rate Selection Bits [7:0] bit 2 mask. */ -#define USART_BSEL2_bp 2 /* Baud Rate Selection Bits [7:0] bit 2 position. */ -#define USART_BSEL3_bm (1<<3) /* Baud Rate Selection Bits [7:0] bit 3 mask. */ -#define USART_BSEL3_bp 3 /* Baud Rate Selection Bits [7:0] bit 3 position. */ -#define USART_BSEL4_bm (1<<4) /* Baud Rate Selection Bits [7:0] bit 4 mask. */ -#define USART_BSEL4_bp 4 /* Baud Rate Selection Bits [7:0] bit 4 position. */ -#define USART_BSEL5_bm (1<<5) /* Baud Rate Selection Bits [7:0] bit 5 mask. */ -#define USART_BSEL5_bp 5 /* Baud Rate Selection Bits [7:0] bit 5 position. */ -#define USART_BSEL6_bm (1<<6) /* Baud Rate Selection Bits [7:0] bit 6 mask. */ -#define USART_BSEL6_bp 6 /* Baud Rate Selection Bits [7:0] bit 6 position. */ -#define USART_BSEL7_bm (1<<7) /* Baud Rate Selection Bits [7:0] bit 7 mask. */ -#define USART_BSEL7_bp 7 /* Baud Rate Selection Bits [7:0] bit 7 position. */ - - -/* USART.BAUDCTRLB bit masks and bit positions */ -#define USART_BSCALE_gm 0xF0 /* Baud Rate Scale group mask. */ -#define USART_BSCALE_gp 4 /* Baud Rate Scale group position. */ -#define USART_BSCALE0_bm (1<<4) /* Baud Rate Scale bit 0 mask. */ -#define USART_BSCALE0_bp 4 /* Baud Rate Scale bit 0 position. */ -#define USART_BSCALE1_bm (1<<5) /* Baud Rate Scale bit 1 mask. */ -#define USART_BSCALE1_bp 5 /* Baud Rate Scale bit 1 position. */ -#define USART_BSCALE2_bm (1<<6) /* Baud Rate Scale bit 2 mask. */ -#define USART_BSCALE2_bp 6 /* Baud Rate Scale bit 2 position. */ -#define USART_BSCALE3_bm (1<<7) /* Baud Rate Scale bit 3 mask. */ -#define USART_BSCALE3_bp 7 /* Baud Rate Scale bit 3 position. */ - -/* USART_BSEL_gm Predefined. */ -/* USART_BSEL_gp Predefined. */ -/* USART_BSEL0_bm Predefined. */ -/* USART_BSEL0_bp Predefined. */ -/* USART_BSEL1_bm Predefined. */ -/* USART_BSEL1_bp Predefined. */ -/* USART_BSEL2_bm Predefined. */ -/* USART_BSEL2_bp Predefined. */ -/* USART_BSEL3_bm Predefined. */ -/* USART_BSEL3_bp Predefined. */ - - -/* SPI - Serial Peripheral Interface */ -/* SPI.CTRL bit masks and bit positions */ -#define SPI_CLK2X_bm 0x80 /* Enable Double Speed bit mask. */ -#define SPI_CLK2X_bp 7 /* Enable Double Speed bit position. */ - -#define SPI_ENABLE_bm 0x40 /* Enable Module bit mask. */ -#define SPI_ENABLE_bp 6 /* Enable Module bit position. */ - -#define SPI_DORD_bm 0x20 /* Data Order Setting bit mask. */ -#define SPI_DORD_bp 5 /* Data Order Setting bit position. */ - -#define SPI_MASTER_bm 0x10 /* Master Operation Enable bit mask. */ -#define SPI_MASTER_bp 4 /* Master Operation Enable bit position. */ - -#define SPI_MODE_gm 0x0C /* SPI Mode group mask. */ -#define SPI_MODE_gp 2 /* SPI Mode group position. */ -#define SPI_MODE0_bm (1<<2) /* SPI Mode bit 0 mask. */ -#define SPI_MODE0_bp 2 /* SPI Mode bit 0 position. */ -#define SPI_MODE1_bm (1<<3) /* SPI Mode bit 1 mask. */ -#define SPI_MODE1_bp 3 /* SPI Mode bit 1 position. */ - -#define SPI_PRESCALER_gm 0x03 /* Prescaler group mask. */ -#define SPI_PRESCALER_gp 0 /* Prescaler group position. */ -#define SPI_PRESCALER0_bm (1<<0) /* Prescaler bit 0 mask. */ -#define SPI_PRESCALER0_bp 0 /* Prescaler bit 0 position. */ -#define SPI_PRESCALER1_bm (1<<1) /* Prescaler bit 1 mask. */ -#define SPI_PRESCALER1_bp 1 /* Prescaler bit 1 position. */ - - -/* SPI.INTCTRL bit masks and bit positions */ -#define SPI_INTLVL_gm 0x03 /* Interrupt level group mask. */ -#define SPI_INTLVL_gp 0 /* Interrupt level group position. */ -#define SPI_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */ -#define SPI_INTLVL0_bp 0 /* Interrupt level bit 0 position. */ -#define SPI_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */ -#define SPI_INTLVL1_bp 1 /* Interrupt level bit 1 position. */ - - -/* SPI.STATUS bit masks and bit positions */ -#define SPI_IF_bm 0x80 /* Interrupt Flag bit mask. */ -#define SPI_IF_bp 7 /* Interrupt Flag bit position. */ - -#define SPI_WRCOL_bm 0x40 /* Write Collision bit mask. */ -#define SPI_WRCOL_bp 6 /* Write Collision bit position. */ - - -/* IRCOM - IR Communication Module */ -/* IRCOM.CTRL bit masks and bit positions */ -#define IRCOM_EVSEL_gm 0x0F /* Event Channel Select group mask. */ -#define IRCOM_EVSEL_gp 0 /* Event Channel Select group position. */ -#define IRCOM_EVSEL0_bm (1<<0) /* Event Channel Select bit 0 mask. */ -#define IRCOM_EVSEL0_bp 0 /* Event Channel Select bit 0 position. */ -#define IRCOM_EVSEL1_bm (1<<1) /* Event Channel Select bit 1 mask. */ -#define IRCOM_EVSEL1_bp 1 /* Event Channel Select bit 1 position. */ -#define IRCOM_EVSEL2_bm (1<<2) /* Event Channel Select bit 2 mask. */ -#define IRCOM_EVSEL2_bp 2 /* Event Channel Select bit 2 position. */ -#define IRCOM_EVSEL3_bm (1<<3) /* Event Channel Select bit 3 mask. */ -#define IRCOM_EVSEL3_bp 3 /* Event Channel Select bit 3 position. */ - - - -// Generic Port Pins - -#define PIN0_bm 0x01 -#define PIN0_bp 0 -#define PIN1_bm 0x02 -#define PIN1_bp 1 -#define PIN2_bm 0x04 -#define PIN2_bp 2 -#define PIN3_bm 0x08 -#define PIN3_bp 3 -#define PIN4_bm 0x10 -#define PIN4_bp 4 -#define PIN5_bm 0x20 -#define PIN5_bp 5 -#define PIN6_bm 0x40 -#define PIN6_bp 6 -#define PIN7_bm 0x80 -#define PIN7_bp 7 - - -/* ========== Interrupt Vector Definitions ========== */ -/* Vector 0 is the reset vector */ - -/* OSC interrupt vectors */ -#define OSC_XOSCF_vect_num 1 -#define OSC_XOSCF_vect _VECTOR(1) /* External Oscillator Failure Interrupt (NMI) */ - -/* PORTC interrupt vectors */ -#define PORTC_INT0_vect_num 2 -#define PORTC_INT0_vect _VECTOR(2) /* External Interrupt 0 */ -#define PORTC_INT1_vect_num 3 -#define PORTC_INT1_vect _VECTOR(3) /* External Interrupt 1 */ - -/* PORTR interrupt vectors */ -#define PORTR_INT0_vect_num 4 -#define PORTR_INT0_vect _VECTOR(4) /* External Interrupt 0 */ -#define PORTR_INT1_vect_num 5 -#define PORTR_INT1_vect _VECTOR(5) /* External Interrupt 1 */ - -/* RTC interrupt vectors */ -#define RTC_OVF_vect_num 10 -#define RTC_OVF_vect _VECTOR(10) /* Overflow Interrupt */ -#define RTC_COMP_vect_num 11 -#define RTC_COMP_vect _VECTOR(11) /* Compare Interrupt */ - -/* TWIC interrupt vectors */ -#define TWIC_TWIS_vect_num 12 -#define TWIC_TWIS_vect _VECTOR(12) /* TWI Slave Interrupt */ -#define TWIC_TWIM_vect_num 13 -#define TWIC_TWIM_vect _VECTOR(13) /* TWI Master Interrupt */ - -/* TCC0 interrupt vectors */ -#define TCC0_OVF_vect_num 14 -#define TCC0_OVF_vect _VECTOR(14) /* Overflow Interrupt */ -#define TCC0_ERR_vect_num 15 -#define TCC0_ERR_vect _VECTOR(15) /* Error Interrupt */ -#define TCC0_CCA_vect_num 16 -#define TCC0_CCA_vect _VECTOR(16) /* Compare or Capture A Interrupt */ -#define TCC0_CCB_vect_num 17 -#define TCC0_CCB_vect _VECTOR(17) /* Compare or Capture B Interrupt */ -#define TCC0_CCC_vect_num 18 -#define TCC0_CCC_vect _VECTOR(18) /* Compare or Capture C Interrupt */ -#define TCC0_CCD_vect_num 19 -#define TCC0_CCD_vect _VECTOR(19) /* Compare or Capture D Interrupt */ - -/* TCC1 interrupt vectors */ -#define TCC1_OVF_vect_num 20 -#define TCC1_OVF_vect _VECTOR(20) /* Overflow Interrupt */ -#define TCC1_ERR_vect_num 21 -#define TCC1_ERR_vect _VECTOR(21) /* Error Interrupt */ -#define TCC1_CCA_vect_num 22 -#define TCC1_CCA_vect _VECTOR(22) /* Compare or Capture A Interrupt */ -#define TCC1_CCB_vect_num 23 -#define TCC1_CCB_vect _VECTOR(23) /* Compare or Capture B Interrupt */ - -/* SPIC interrupt vectors */ -#define SPIC_INT_vect_num 24 -#define SPIC_INT_vect _VECTOR(24) /* SPI Interrupt */ - -/* USARTC0 interrupt vectors */ -#define USARTC0_RXC_vect_num 25 -#define USARTC0_RXC_vect _VECTOR(25) /* Reception Complete Interrupt */ -#define USARTC0_DRE_vect_num 26 -#define USARTC0_DRE_vect _VECTOR(26) /* Data Register Empty Interrupt */ -#define USARTC0_TXC_vect_num 27 -#define USARTC0_TXC_vect _VECTOR(27) /* Transmission Complete Interrupt */ - -/* NVM interrupt vectors */ -#define NVM_EE_vect_num 32 -#define NVM_EE_vect _VECTOR(32) /* EE Interrupt */ -#define NVM_SPM_vect_num 33 -#define NVM_SPM_vect _VECTOR(33) /* SPM Interrupt */ - -/* PORTB interrupt vectors */ -#define PORTB_INT0_vect_num 34 -#define PORTB_INT0_vect _VECTOR(34) /* External Interrupt 0 */ -#define PORTB_INT1_vect_num 35 -#define PORTB_INT1_vect _VECTOR(35) /* External Interrupt 1 */ - -/* PORTE interrupt vectors */ -#define PORTE_INT0_vect_num 43 -#define PORTE_INT0_vect _VECTOR(43) /* External Interrupt 0 */ -#define PORTE_INT1_vect_num 44 -#define PORTE_INT1_vect _VECTOR(44) /* External Interrupt 1 */ - -/* TWIE interrupt vectors */ -#define TWIE_TWIS_vect_num 45 -#define TWIE_TWIS_vect _VECTOR(45) /* TWI Slave Interrupt */ -#define TWIE_TWIM_vect_num 46 -#define TWIE_TWIM_vect _VECTOR(46) /* TWI Master Interrupt */ - -/* TCE0 interrupt vectors */ -#define TCE0_OVF_vect_num 47 -#define TCE0_OVF_vect _VECTOR(47) /* Overflow Interrupt */ -#define TCE0_ERR_vect_num 48 -#define TCE0_ERR_vect _VECTOR(48) /* Error Interrupt */ -#define TCE0_CCA_vect_num 49 -#define TCE0_CCA_vect _VECTOR(49) /* Compare or Capture A Interrupt */ -#define TCE0_CCB_vect_num 50 -#define TCE0_CCB_vect _VECTOR(50) /* Compare or Capture B Interrupt */ -#define TCE0_CCC_vect_num 51 -#define TCE0_CCC_vect _VECTOR(51) /* Compare or Capture C Interrupt */ -#define TCE0_CCD_vect_num 52 -#define TCE0_CCD_vect _VECTOR(52) /* Compare or Capture D Interrupt */ - -/* PORTD interrupt vectors */ -#define PORTD_INT0_vect_num 64 -#define PORTD_INT0_vect _VECTOR(64) /* External Interrupt 0 */ -#define PORTD_INT1_vect_num 65 -#define PORTD_INT1_vect _VECTOR(65) /* External Interrupt 1 */ - -/* PORTA interrupt vectors */ -#define PORTA_INT0_vect_num 66 -#define PORTA_INT0_vect _VECTOR(66) /* External Interrupt 0 */ -#define PORTA_INT1_vect_num 67 -#define PORTA_INT1_vect _VECTOR(67) /* External Interrupt 1 */ - -/* ACA interrupt vectors */ -#define ACA_AC0_vect_num 68 -#define ACA_AC0_vect _VECTOR(68) /* AC0 Interrupt */ -#define ACA_AC1_vect_num 69 -#define ACA_AC1_vect _VECTOR(69) /* AC1 Interrupt */ -#define ACA_ACW_vect_num 70 -#define ACA_ACW_vect _VECTOR(70) /* ACW Window Mode Interrupt */ - -/* ADCA interrupt vectors */ -#define ADCA_CH0_vect_num 71 -#define ADCA_CH0_vect _VECTOR(71) /* Interrupt 0 */ - -/* TCD0 interrupt vectors */ -#define TCD0_OVF_vect_num 77 -#define TCD0_OVF_vect _VECTOR(77) /* Overflow Interrupt */ -#define TCD0_ERR_vect_num 78 -#define TCD0_ERR_vect _VECTOR(78) /* Error Interrupt */ -#define TCD0_CCA_vect_num 79 -#define TCD0_CCA_vect _VECTOR(79) /* Compare or Capture A Interrupt */ -#define TCD0_CCB_vect_num 80 -#define TCD0_CCB_vect _VECTOR(80) /* Compare or Capture B Interrupt */ -#define TCD0_CCC_vect_num 81 -#define TCD0_CCC_vect _VECTOR(81) /* Compare or Capture C Interrupt */ -#define TCD0_CCD_vect_num 82 -#define TCD0_CCD_vect _VECTOR(82) /* Compare or Capture D Interrupt */ - -/* SPID interrupt vectors */ -#define SPID_INT_vect_num 87 -#define SPID_INT_vect _VECTOR(87) /* SPI Interrupt */ - -/* USARTD0 interrupt vectors */ -#define USARTD0_RXC_vect_num 88 -#define USARTD0_RXC_vect _VECTOR(88) /* Reception Complete Interrupt */ -#define USARTD0_DRE_vect_num 89 -#define USARTD0_DRE_vect _VECTOR(89) /* Data Register Empty Interrupt */ -#define USARTD0_TXC_vect_num 90 -#define USARTD0_TXC_vect _VECTOR(90) /* Transmission Complete Interrupt */ - - -#define _VECTOR_SIZE 4 /* Size of individual vector. */ -#define _VECTORS_SIZE (91 * _VECTOR_SIZE) - - -/* ========== Constants ========== */ - -#define PROGMEM_START (0x0000) -#define PROGMEM_SIZE (20480) -#define PROGMEM_PAGE_SIZE (256) -#define PROGMEM_END (PROGMEM_START + PROGMEM_SIZE - 1) - -#define APP_SECTION_START (0x0000) -#define APP_SECTION_SIZE (16384) -#define APP_SECTION_PAGE_SIZE (256) -#define APP_SECTION_END (APP_SECTION_START + APP_SECTION_SIZE - 1) - -#define APPTABLE_SECTION_START (0x3000) -#define APPTABLE_SECTION_SIZE (4096) -#define APPTABLE_SECTION_PAGE_SIZE (256) -#define APPTABLE_SECTION_END (APPTABLE_SECTION_START + APPTABLE_SECTION_SIZE - 1) - -#define BOOT_SECTION_START (0x4000) -#define BOOT_SECTION_SIZE (4096) -#define BOOT_SECTION_PAGE_SIZE (256) -#define BOOT_SECTION_END (BOOT_SECTION_START + BOOT_SECTION_SIZE - 1) - -#define DATAMEM_START (0x0000) -#define DATAMEM_SIZE (10240) -#define DATAMEM_PAGE_SIZE (0) -#define DATAMEM_END (DATAMEM_START + DATAMEM_SIZE - 1) - -#define IO_START (0x0000) -#define IO_SIZE (4096) -#define IO_PAGE_SIZE (0) -#define IO_END (IO_START + IO_SIZE - 1) - -#define MAPPED_EEPROM_START (0x1000) -#define MAPPED_EEPROM_SIZE (1024) -#define MAPPED_EEPROM_PAGE_SIZE (0) -#define MAPPED_EEPROM_END (MAPPED_EEPROM_START + MAPPED_EEPROM_SIZE - 1) - -#define INTERNAL_SRAM_START (0x2000) -#define INTERNAL_SRAM_SIZE (2048) -#define INTERNAL_SRAM_PAGE_SIZE (0) -#define INTERNAL_SRAM_END (INTERNAL_SRAM_START + INTERNAL_SRAM_SIZE - 1) - -#define EEPROM_START (0x0000) -#define EEPROM_SIZE (1024) -#define EEPROM_PAGE_SIZE (32) -#define EEPROM_END (EEPROM_START + EEPROM_SIZE - 1) - -#define FUSE_START (0x0000) -#define FUSE_SIZE (6) -#define FUSE_PAGE_SIZE (0) -#define FUSE_END (FUSE_START + FUSE_SIZE - 1) - -#define LOCKBIT_START (0x0000) -#define LOCKBIT_SIZE (1) -#define LOCKBIT_PAGE_SIZE (0) -#define LOCKBIT_END (LOCKBIT_START + LOCKBIT_SIZE - 1) - -#define SIGNATURES_START (0x0000) -#define SIGNATURES_SIZE (3) -#define SIGNATURES_PAGE_SIZE (0) -#define SIGNATURES_END (SIGNATURES_START + SIGNATURES_SIZE - 1) - -#define USER_SIGNATURES_START (0x0000) -#define USER_SIGNATURES_SIZE (256) -#define USER_SIGNATURES_PAGE_SIZE (0) -#define USER_SIGNATURES_END (USER_SIGNATURES_START + USER_SIGNATURES_SIZE - 1) - -#define PROD_SIGNATURES_START (0x0000) -#define PROD_SIGNATURES_SIZE (52) -#define PROD_SIGNATURES_PAGE_SIZE (0) -#define PROD_SIGNATURES_END (PROD_SIGNATURES_START + PROD_SIGNATURES_SIZE - 1) - -#define FLASHEND PROGMEM_END -#define SPM_PAGESIZE PROGMEM_PAGE_SIZE -#define RAMSTART INTERNAL_SRAM_START -#define RAMSIZE INTERNAL_SRAM_SIZE -#define RAMEND INTERNAL_SRAM_END -#define XRAMSTART EXTERNAL_SRAM_START -#define XRAMSIZE EXTERNAL_SRAM_SIZE -#define XRAMEND INTERNAL_SRAM_END -#define E2END EEPROM_END -#define E2PAGESIZE EEPROM_PAGE_SIZE - - -/* ========== Fuses ========== */ -#define FUSE_MEMORY_SIZE 6 - -/* Fuse Byte 0 */ -#define FUSE_USERID0 (unsigned char)~_BV(0) /* User ID Bit 0 */ -#define FUSE_USERID1 (unsigned char)~_BV(1) /* User ID Bit 1 */ -#define FUSE_USERID2 (unsigned char)~_BV(2) /* User ID Bit 2 */ -#define FUSE_USERID3 (unsigned char)~_BV(3) /* User ID Bit 3 */ -#define FUSE_USERID4 (unsigned char)~_BV(4) /* User ID Bit 4 */ -#define FUSE_USERID5 (unsigned char)~_BV(5) /* User ID Bit 5 */ -#define FUSE_USERID6 (unsigned char)~_BV(6) /* User ID Bit 6 */ -#define FUSE_USERID7 (unsigned char)~_BV(7) /* User ID Bit 7 */ -#define FUSE0_DEFAULT (0xFF) - -/* Fuse Byte 1 */ -#define FUSE_WDP0 (unsigned char)~_BV(0) /* Watchdog Timeout Period Bit 0 */ -#define FUSE_WDP1 (unsigned char)~_BV(1) /* Watchdog Timeout Period Bit 1 */ -#define FUSE_WDP2 (unsigned char)~_BV(2) /* Watchdog Timeout Period Bit 2 */ -#define FUSE_WDP3 (unsigned char)~_BV(3) /* Watchdog Timeout Period Bit 3 */ -#define FUSE_WDWP0 (unsigned char)~_BV(4) /* Watchdog Window Timeout Period Bit 0 */ -#define FUSE_WDWP1 (unsigned char)~_BV(5) /* Watchdog Window Timeout Period Bit 1 */ -#define FUSE_WDWP2 (unsigned char)~_BV(6) /* Watchdog Window Timeout Period Bit 2 */ -#define FUSE_WDWP3 (unsigned char)~_BV(7) /* Watchdog Window Timeout Period Bit 3 */ -#define FUSE1_DEFAULT (0xFF) - -/* Fuse Byte 2 */ -#define FUSE_BODPD0 (unsigned char)~_BV(0) /* BOD Operation in Power-Down Mode Bit 0 */ -#define FUSE_BODPD1 (unsigned char)~_BV(1) /* BOD Operation in Power-Down Mode Bit 1 */ -#define FUSE_BOOTRST (unsigned char)~_BV(6) /* Boot Loader Section Reset Vector */ -#define FUSE_DVSDON (unsigned char)~_BV(7) /* Spike Detector Enable */ -#define FUSE2_DEFAULT (0xFF) - -/* Fuse Byte 3 Reserved */ - -/* Fuse Byte 4 */ -#define FUSE_WDLOCK (unsigned char)~_BV(1) /* Watchdog Timer Lock */ -#define FUSE_SUT0 (unsigned char)~_BV(2) /* Start-up Time Bit 0 */ -#define FUSE_SUT1 (unsigned char)~_BV(3) /* Start-up Time Bit 1 */ -#define FUSE4_DEFAULT (0xFF) - -/* Fuse Byte 5 */ -#define FUSE_BODLVL0 (unsigned char)~_BV(0) /* Brown Out Detection Voltage Level Bit 0 */ -#define FUSE_BODLVL1 (unsigned char)~_BV(1) /* Brown Out Detection Voltage Level Bit 1 */ -#define FUSE_BODLVL2 (unsigned char)~_BV(2) /* Brown Out Detection Voltage Level Bit 2 */ -#define FUSE_EESAVE (unsigned char)~_BV(3) /* Preserve EEPROM Through Chip Erase */ -#define FUSE_BODACT0 (unsigned char)~_BV(4) /* BOD Operation in Active Mode Bit 0 */ -#define FUSE_BODACT1 (unsigned char)~_BV(5) /* BOD Operation in Active Mode Bit 1 */ -#define FUSE5_DEFAULT (0xFF) - - -/* ========== Lock Bits ========== */ -#define __LOCK_BITS_EXIST -#define __BOOT_LOCK_APPLICATION_TABLE_BITS_EXIST -#define __BOOT_LOCK_APPLICATION_BITS_EXIST -#define __BOOT_LOCK_BOOT_BITS_EXIST - - -/* ========== Signature ========== */ -#define SIGNATURE_0 0x1E -#define SIGNATURE_1 0x94 -#define SIGNATURE_2 0x42 - -/* ========== Power Reduction Condition Definitions ========== */ - -/* PR.PRGEN */ -#define __AVR_HAVE_PRGEN (PR_RTC_bm|PR_EVSYS_bm) -#define __AVR_HAVE_PRGEN_RTC -#define __AVR_HAVE_PRGEN_EVSYS - -/* PR.PRPA */ -#define __AVR_HAVE_PRPA (PR_ADC_bm|PR_AC_bm) -#define __AVR_HAVE_PRPA_ADC -#define __AVR_HAVE_PRPA_AC - -/* PR.PRPC */ -#define __AVR_HAVE_PRPC (PR_TWI_bm|PR_USART0_bm|PR_SPI_bm|PR_HIRES_bm|PR_TC1_bm|PR_TC0_bm) -#define __AVR_HAVE_PRPC_TWI -#define __AVR_HAVE_PRPC_USART0 -#define __AVR_HAVE_PRPC_SPI -#define __AVR_HAVE_PRPC_HIRES -#define __AVR_HAVE_PRPC_TC1 -#define __AVR_HAVE_PRPC_TC0 - -/* PR.PRPD */ -#define __AVR_HAVE_PRPD (PR_USART0_bm|PR_SPI_bm|PR_TC0_bm) -#define __AVR_HAVE_PRPD_USART0 -#define __AVR_HAVE_PRPD_SPI -#define __AVR_HAVE_PRPD_TC0 - -/* PR.PRPE */ -#define __AVR_HAVE_PRPE (PR_TWI_bm|PR_USART0_bm|PR_TC0_bm) -#define __AVR_HAVE_PRPE_TWI -#define __AVR_HAVE_PRPE_USART0 -#define __AVR_HAVE_PRPE_TC0 - -/* PR.PRPF */ -#define __AVR_HAVE_PRPF (PR_USART0_bm|PR_TC0_bm) -#define __AVR_HAVE_PRPF_USART0 -#define __AVR_HAVE_PRPF_TC0 - - -#endif /* _AVR_ATxmega16D4_H_ */ - diff --git a/arduino/hardware/tools/avr/avr/include/avr/iox16e5.h b/arduino/hardware/tools/avr/avr/include/avr/iox16e5.h deleted file mode 100644 index 7649c5f..0000000 --- a/arduino/hardware/tools/avr/avr/include/avr/iox16e5.h +++ /dev/null @@ -1,7699 +0,0 @@ -/***************************************************************************** - * - * Copyright (C) 2015 Atmel Corporation - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * - * * Neither the name of the copyright holders nor the names of - * contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - ****************************************************************************/ - - -#ifndef _AVR_IO_H_ -# error "Include instead of this file." -#endif - -#ifndef _AVR_IOXXX_H_ -# define _AVR_IOXXX_H_ "iox16e5.h" -#else -# error "Attempt to include more than one file." -#endif - -#ifndef _AVR_ATXMEGA16E5_H_INCLUDED -#define _AVR_ATXMEGA16E5_H_INCLUDED - -/* Ungrouped common registers */ -#define GPIOR0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ -#define GPIOR1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ -#define GPIOR2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ -#define GPIOR3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ - -/* Deprecated */ -#define GPIO0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ -#define GPIO1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ -#define GPIO2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ -#define GPIO3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ - -#define CCP _SFR_MEM8(0x0034) /* Configuration Change Protection */ -#define RAMPD _SFR_MEM8(0x0038) /* Ramp D */ -#define RAMPX _SFR_MEM8(0x0039) /* Ramp X */ -#define RAMPY _SFR_MEM8(0x003A) /* Ramp Y */ -#define RAMPZ _SFR_MEM8(0x003B) /* Ramp Z */ -#define EIND _SFR_MEM8(0x003C) /* Extended Indirect Jump */ -#define SPL _SFR_MEM8(0x003D) /* Stack Pointer Low */ -#define SPH _SFR_MEM8(0x003E) /* Stack Pointer High */ -#define SREG _SFR_MEM8(0x003F) /* Status Register */ - -/* C Language Only */ -#if !defined (__ASSEMBLER__) - -#include - -typedef volatile uint8_t register8_t; -typedef volatile uint16_t register16_t; -typedef volatile uint32_t register32_t; - - -#ifdef _WORDREGISTER -#undef _WORDREGISTER -#endif -#define _WORDREGISTER(regname) \ - __extension__ union \ - { \ - register16_t regname; \ - struct \ - { \ - register8_t regname ## L; \ - register8_t regname ## H; \ - }; \ - } - -#ifdef _DWORDREGISTER -#undef _DWORDREGISTER -#endif -#define _DWORDREGISTER(regname) \ - __extension__ union \ - { \ - register32_t regname; \ - struct \ - { \ - register8_t regname ## 0; \ - register8_t regname ## 1; \ - register8_t regname ## 2; \ - register8_t regname ## 3; \ - }; \ - } - - -/* -========================================================================== -IO Module Structures -========================================================================== -*/ - - -/* --------------------------------------------------------------------------- -VPORT - Virtual Ports --------------------------------------------------------------------------- -*/ - -/* Virtual Port */ -typedef struct VPORT_struct -{ - register8_t DIR; /* I/O Port Data Direction */ - register8_t OUT; /* I/O Port Output */ - register8_t IN; /* I/O Port Input */ - register8_t INTFLAGS; /* Interrupt Flag Register */ -} VPORT_t; - - -/* --------------------------------------------------------------------------- -XOCD - On-Chip Debug System --------------------------------------------------------------------------- -*/ - -/* On-Chip Debug System */ -typedef struct OCD_struct -{ - register8_t OCDR0; /* OCD Register 0 */ - register8_t OCDR1; /* OCD Register 1 */ -} OCD_t; - - -/* --------------------------------------------------------------------------- -CPU - CPU --------------------------------------------------------------------------- -*/ - -/* CCP signatures */ -typedef enum CCP_enum -{ - CCP_SPM_gc = (0x9D<<0), /* SPM Instruction Protection */ - CCP_IOREG_gc = (0xD8<<0), /* IO Register Protection */ -} CCP_t; - - -/* --------------------------------------------------------------------------- -CLK - Clock System --------------------------------------------------------------------------- -*/ - -/* Clock System */ -typedef struct CLK_struct -{ - register8_t CTRL; /* Control Register */ - register8_t PSCTRL; /* Prescaler Control Register */ - register8_t LOCK; /* Lock register */ - register8_t RTCCTRL; /* RTC Control Register */ - register8_t reserved_0x04; -} CLK_t; - - -/* Power Reduction */ -typedef struct PR_struct -{ - register8_t PRGEN; /* General Power Reduction */ - register8_t PRPA; /* Power Reduction Port A */ - register8_t reserved_0x02; - register8_t PRPC; /* Power Reduction Port C */ - register8_t PRPD; /* Power Reduction Port D */ - register8_t reserved_0x05; - register8_t reserved_0x06; -} PR_t; - -/* System Clock Selection */ -typedef enum CLK_SCLKSEL_enum -{ - CLK_SCLKSEL_RC2M_gc = (0x00<<0), /* Internal 2 MHz RC Oscillator */ - CLK_SCLKSEL_RC32M_gc = (0x01<<0), /* Internal 32 MHz RC Oscillator */ - CLK_SCLKSEL_RC32K_gc = (0x02<<0), /* Internal 32.768 kHz RC Oscillator */ - CLK_SCLKSEL_XOSC_gc = (0x03<<0), /* External Crystal Oscillator or Clock */ - CLK_SCLKSEL_PLL_gc = (0x04<<0), /* Phase Locked Loop */ - CLK_SCLKSEL_RC8M_gc = (0x05<<0), /* Internal 8 MHz RC Oscillator */ -} CLK_SCLKSEL_t; - -/* Prescaler A Division Factor */ -typedef enum CLK_PSADIV_enum -{ - CLK_PSADIV_1_gc = (0x00<<2), /* Divide by 1 */ - CLK_PSADIV_2_gc = (0x01<<2), /* Divide by 2 */ - CLK_PSADIV_4_gc = (0x03<<2), /* Divide by 4 */ - CLK_PSADIV_8_gc = (0x05<<2), /* Divide by 8 */ - CLK_PSADIV_16_gc = (0x07<<2), /* Divide by 16 */ - CLK_PSADIV_32_gc = (0x09<<2), /* Divide by 32 */ - CLK_PSADIV_64_gc = (0x0B<<2), /* Divide by 64 */ - CLK_PSADIV_128_gc = (0x0D<<2), /* Divide by 128 */ - CLK_PSADIV_256_gc = (0x0F<<2), /* Divide by 256 */ - CLK_PSADIV_512_gc = (0x11<<2), /* Divide by 512 */ - CLK_PSADIV_6_gc = (0x13<<2), /* Divide by 6 */ - CLK_PSADIV_10_gc = (0x15<<2), /* Divide by 10 */ - CLK_PSADIV_12_gc = (0x17<<2), /* Divide by 12 */ - CLK_PSADIV_24_gc = (0x19<<2), /* Divide by 24 */ - CLK_PSADIV_48_gc = (0x1B<<2), /* Divide by 48 */ -} CLK_PSADIV_t; - -/* Prescaler B and C Division Factor */ -typedef enum CLK_PSBCDIV_enum -{ - CLK_PSBCDIV_1_1_gc = (0x00<<0), /* Divide B by 1 and C by 1 */ - CLK_PSBCDIV_1_2_gc = (0x01<<0), /* Divide B by 1 and C by 2 */ - CLK_PSBCDIV_4_1_gc = (0x02<<0), /* Divide B by 4 and C by 1 */ - CLK_PSBCDIV_2_2_gc = (0x03<<0), /* Divide B by 2 and C by 2 */ -} CLK_PSBCDIV_t; - -/* RTC Clock Source */ -typedef enum CLK_RTCSRC_enum -{ - CLK_RTCSRC_ULP_gc = (0x00<<1), /* 1.024 kHz from internal 32kHz ULP */ - CLK_RTCSRC_TOSC_gc = (0x01<<1), /* 1.024 kHz from 32.768 kHz crystal oscillator on TOSC */ - CLK_RTCSRC_RCOSC_gc = (0x02<<1), /* 1.024 kHz from internal 32.768 kHz RC oscillator */ - CLK_RTCSRC_TOSC32_gc = (0x05<<1), /* 32.768 kHz from 32.768 kHz crystal oscillator on TOSC */ - CLK_RTCSRC_RCOSC32_gc = (0x06<<1), /* 32.768 kHz from internal 32.768 kHz RC oscillator */ - CLK_RTCSRC_EXTCLK_gc = (0x07<<1), /* External Clock from TOSC1 */ -} CLK_RTCSRC_t; - - -/* --------------------------------------------------------------------------- -SLEEP - Sleep Controller --------------------------------------------------------------------------- -*/ - -/* Sleep Controller */ -typedef struct SLEEP_struct -{ - register8_t CTRL; /* Control Register */ -} SLEEP_t; - -/* Sleep Mode */ -typedef enum SLEEP_SMODE_enum -{ - SLEEP_SMODE_IDLE_gc = (0x00<<1), /* Idle mode */ - SLEEP_SMODE_PDOWN_gc = (0x02<<1), /* Power-down Mode */ - SLEEP_SMODE_PSAVE_gc = (0x03<<1), /* Power-save Mode */ - SLEEP_SMODE_STDBY_gc = (0x06<<1), /* Standby Mode */ - SLEEP_SMODE_ESTDBY_gc = (0x07<<1), /* Extended Standby Mode */ -} SLEEP_SMODE_t; - - - -#define SLEEP_MODE_IDLE (0x00<<1) -#define SLEEP_MODE_PWR_DOWN (0x02<<1) -#define SLEEP_MODE_PWR_SAVE (0x03<<1) -#define SLEEP_MODE_STANDBY (0x06<<1) -#define SLEEP_MODE_EXT_STANDBY (0x07<<1) -/* --------------------------------------------------------------------------- -OSC - Oscillator --------------------------------------------------------------------------- -*/ - -/* Oscillator */ -typedef struct OSC_struct -{ - register8_t CTRL; /* Control Register */ - register8_t STATUS; /* Status Register */ - register8_t XOSCCTRL; /* External Oscillator Control Register */ - register8_t XOSCFAIL; /* Oscillator Failure Detection Register */ - register8_t RC32KCAL; /* 32.768 kHz Internal Oscillator Calibration Register */ - register8_t PLLCTRL; /* PLL Control Register */ - register8_t DFLLCTRL; /* DFLL Control Register */ - register8_t RC8MCAL; /* Internal 8 MHz RC Oscillator Calibration Register */ -} OSC_t; - -/* Oscillator Frequency Range */ -typedef enum OSC_FRQRANGE_enum -{ - OSC_FRQRANGE_04TO2_gc = (0x00<<6), /* 0.4 - 2 MHz */ - OSC_FRQRANGE_2TO9_gc = (0x01<<6), /* 2 - 9 MHz */ - OSC_FRQRANGE_9TO12_gc = (0x02<<6), /* 9 - 12 MHz */ - OSC_FRQRANGE_12TO16_gc = (0x03<<6), /* 12 - 16 MHz */ -} OSC_FRQRANGE_t; - -/* External Oscillator Selection and Startup Time */ -typedef enum OSC_XOSCSEL_enum -{ - OSC_XOSCSEL_EXTCLK_gc = (0x00<<0), /* External Clock on port R1 - 6 CLK */ - OSC_XOSCSEL_32KHz_gc = (0x02<<0), /* 32.768 kHz TOSC - 32K CLK */ - OSC_XOSCSEL_XTAL_256CLK_gc = (0x03<<0), /* 0.4-16 MHz XTAL - 256 CLK */ - OSC_XOSCSEL_XTAL_1KCLK_gc = (0x07<<0), /* 0.4-16 MHz XTAL - 1K CLK */ - OSC_XOSCSEL_XTAL_16KCLK_gc = (0x0B<<0), /* 0.4-16 MHz XTAL - 16K CLK */ - OSC_XOSCSEL_EXTCLK_C4_gc = (0x14<<0), /* External Clock on port C4 - 6 CLK */ -} OSC_XOSCSEL_t; - -/* PLL Clock Source */ -typedef enum OSC_PLLSRC_enum -{ - OSC_PLLSRC_RC2M_gc = (0x00<<6), /* Internal 2 MHz RC Oscillator */ - OSC_PLLSRC_RC8M_gc = (0x01<<6), /* Internal 8 MHz RC Oscillator */ - OSC_PLLSRC_RC32M_gc = (0x02<<6), /* Internal 32 MHz RC Oscillator */ - OSC_PLLSRC_XOSC_gc = (0x03<<6), /* External Oscillator */ -} OSC_PLLSRC_t; - -/* 32 MHz DFLL Calibration Reference */ -typedef enum OSC_RC32MCREF_enum -{ - OSC_RC32MCREF_RC32K_gc = (0x00<<1), /* Internal 32.768 kHz RC Oscillator */ - OSC_RC32MCREF_XOSC32K_gc = (0x01<<1), /* External 32.768 kHz Crystal Oscillator */ -} OSC_RC32MCREF_t; - - -/* --------------------------------------------------------------------------- -DFLL - DFLL --------------------------------------------------------------------------- -*/ - -/* DFLL */ -typedef struct DFLL_struct -{ - register8_t CTRL; /* Control Register */ - register8_t reserved_0x01; - register8_t CALA; /* Calibration Register A */ - register8_t CALB; /* Calibration Register B */ - register8_t COMP0; /* Oscillator Compare Register 0 */ - register8_t COMP1; /* Oscillator Compare Register 1 */ - register8_t COMP2; /* Oscillator Compare Register 2 */ - register8_t reserved_0x07; -} DFLL_t; - - -/* --------------------------------------------------------------------------- -RST - Reset --------------------------------------------------------------------------- -*/ - -/* Reset */ -typedef struct RST_struct -{ - register8_t STATUS; /* Status Register */ - register8_t CTRL; /* Control Register */ -} RST_t; - - -/* --------------------------------------------------------------------------- -WDT - Watch-Dog Timer --------------------------------------------------------------------------- -*/ - -/* Watch-Dog Timer */ -typedef struct WDT_struct -{ - register8_t CTRL; /* Control */ - register8_t WINCTRL; /* Windowed Mode Control */ - register8_t STATUS; /* Status */ -} WDT_t; - -/* Period setting */ -typedef enum WDT_PER_enum -{ - WDT_PER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ - WDT_PER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ - WDT_PER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ - WDT_PER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ - WDT_PER_128CLK_gc = (0x04<<2), /* 128 cycles (0.128s @ 3.3V) */ - WDT_PER_256CLK_gc = (0x05<<2), /* 256 cycles (0.256s @ 3.3V) */ - WDT_PER_512CLK_gc = (0x06<<2), /* 512 cycles (0.512s @ 3.3V) */ - WDT_PER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ - WDT_PER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ - WDT_PER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ - WDT_PER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ -} WDT_PER_t; - -/* Closed window period */ -typedef enum WDT_WPER_enum -{ - WDT_WPER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ - WDT_WPER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ - WDT_WPER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ - WDT_WPER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ - WDT_WPER_128CLK_gc = (0x04<<2), /* 128 cycles (0.128s @ 3.3V) */ - WDT_WPER_256CLK_gc = (0x05<<2), /* 256 cycles (0.256s @ 3.3V) */ - WDT_WPER_512CLK_gc = (0x06<<2), /* 512 cycles (0.512s @ 3.3V) */ - WDT_WPER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ - WDT_WPER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ - WDT_WPER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ - WDT_WPER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ -} WDT_WPER_t; - - -/* --------------------------------------------------------------------------- -MCU - MCU Control --------------------------------------------------------------------------- -*/ - -/* MCU Control */ -typedef struct MCU_struct -{ - register8_t DEVID0; /* Device ID byte 0 */ - register8_t DEVID1; /* Device ID byte 1 */ - register8_t DEVID2; /* Device ID byte 2 */ - register8_t REVID; /* Revision ID */ - register8_t reserved_0x04; - register8_t reserved_0x05; - register8_t reserved_0x06; - register8_t ANAINIT; /* Analog Startup Delay */ - register8_t EVSYSLOCK; /* Event System Lock */ - register8_t WEXLOCK; /* WEX Lock */ - register8_t FAULTLOCK; /* FAULT Lock */ - register8_t reserved_0x0B; -} MCU_t; - - -/* --------------------------------------------------------------------------- -PMIC - Programmable Multi-level Interrupt Controller --------------------------------------------------------------------------- -*/ - -/* Programmable Multi-level Interrupt Controller */ -typedef struct PMIC_struct -{ - register8_t STATUS; /* Status Register */ - register8_t INTPRI; /* Interrupt Priority */ - register8_t CTRL; /* Control Register */ - register8_t reserved_0x03; - register8_t reserved_0x04; - register8_t reserved_0x05; - register8_t reserved_0x06; - register8_t reserved_0x07; - register8_t reserved_0x08; - register8_t reserved_0x09; - register8_t reserved_0x0A; - register8_t reserved_0x0B; - register8_t reserved_0x0C; - register8_t reserved_0x0D; - register8_t reserved_0x0E; - register8_t reserved_0x0F; -} PMIC_t; - - -/* --------------------------------------------------------------------------- -PORTCFG - Port Configuration --------------------------------------------------------------------------- -*/ - -/* I/O port Configuration */ -typedef struct PORTCFG_struct -{ - register8_t MPCMASK; /* Multi-pin Configuration Mask */ - register8_t reserved_0x01; - register8_t reserved_0x02; - register8_t reserved_0x03; - register8_t CLKOUT; /* Clock Out Register */ - register8_t reserved_0x05; - register8_t ACEVOUT; /* Analog Comparator and Event Out Register */ - register8_t SRLCTRL; /* Slew Rate Limit Control Register */ -} PORTCFG_t; - -/* Clock and Event Output Port */ -typedef enum PORTCFG_CLKEVPIN_enum -{ - PORTCFG_CLKEVPIN_PIN7_gc = (0x00<<7), /* Clock and Event Ouput on PIN 7 */ - PORTCFG_CLKEVPIN_PIN4_gc = (0x01<<7), /* Clock and Event Ouput on PIN 4 */ -} PORTCFG_CLKEVPIN_t; - -/* RTC Clock Output Port */ -typedef enum PORTCFG_RTCCLKOUT_enum -{ - PORTCFG_RTCCLKOUT_OFF_gc = (0x00<<5), /* System Clock Output Disabled */ - PORTCFG_RTCCLKOUT_PC6_gc = (0x01<<5), /* System Clock Output on Port C pin 6 */ - PORTCFG_RTCCLKOUT_PD6_gc = (0x02<<5), /* System Clock Output on Port D pin 6 */ - PORTCFG_RTCCLKOUT_PR0_gc = (0x03<<5), /* System Clock Output on Port R pin 0 */ -} PORTCFG_RTCCLKOUT_t; - -/* Peripheral Clock Output Select */ -typedef enum PORTCFG_CLKOUTSEL_enum -{ - PORTCFG_CLKOUTSEL_CLK1X_gc = (0x00<<2), /* 1x Peripheral Clock Output to pin */ - PORTCFG_CLKOUTSEL_CLK2X_gc = (0x01<<2), /* 2x Peripheral Clock Output to pin */ - PORTCFG_CLKOUTSEL_CLK4X_gc = (0x02<<2), /* 4x Peripheral Clock Output to pin */ -} PORTCFG_CLKOUTSEL_t; - -/* System Clock Output Port */ -typedef enum PORTCFG_CLKOUT_enum -{ - PORTCFG_CLKOUT_OFF_gc = (0x00<<0), /* System Clock Output Disabled */ - PORTCFG_CLKOUT_PC7_gc = (0x01<<0), /* System Clock Output on Port C pin 7 */ - PORTCFG_CLKOUT_PD7_gc = (0x02<<0), /* System Clock Output on Port D pin 7 */ - PORTCFG_CLKOUT_PR0_gc = (0x03<<0), /* System Clock Output on Port R pin 0 */ -} PORTCFG_CLKOUT_t; - -/* Analog Comparator Output Port */ -typedef enum PORTCFG_ACOUT_enum -{ - PORTCFG_ACOUT_PA_gc = (0x00<<6), /* Analog Comparator Outputs on Port A, Pin 6-7 */ - PORTCFG_ACOUT_PC_gc = (0x01<<6), /* Analog Comparator Outputs on Port C, Pin 6-7 */ - PORTCFG_ACOUT_PD_gc = (0x02<<6), /* Analog Comparator Outputs on Port D, Pin 6-7 */ - PORTCFG_ACOUT_PR_gc = (0x03<<6), /* Analog Comparator Outputs on Port R, Pin 0-1 */ -} PORTCFG_ACOUT_t; - -/* Event Output Port */ -typedef enum PORTCFG_EVOUT_enum -{ - PORTCFG_EVOUT_OFF_gc = (0x00<<4), /* Event Output Disabled */ - PORTCFG_EVOUT_PC7_gc = (0x01<<4), /* Event Channel n Output on Port C pin 7 */ - PORTCFG_EVOUT_PD7_gc = (0x02<<4), /* Event Channel n Output on Port D pin 7 */ - PORTCFG_EVOUT_PR0_gc = (0x03<<4), /* Event Channel n Output on Port R pin 0 */ -} PORTCFG_EVOUT_t; - -/* Event Output Select */ -typedef enum PORTCFG_EVOUTSEL_enum -{ - PORTCFG_EVOUTSEL_0_gc = (0x00<<0), /* Event Channel 0 output to pin */ - PORTCFG_EVOUTSEL_1_gc = (0x01<<0), /* Event Channel 1 output to pin */ - PORTCFG_EVOUTSEL_2_gc = (0x02<<0), /* Event Channel 2 output to pin */ - PORTCFG_EVOUTSEL_3_gc = (0x03<<0), /* Event Channel 3 output to pin */ - PORTCFG_EVOUTSEL_4_gc = (0x04<<0), /* Event Channel 4 output to pin */ - PORTCFG_EVOUTSEL_5_gc = (0x05<<0), /* Event Channel 5 output to pin */ - PORTCFG_EVOUTSEL_6_gc = (0x06<<0), /* Event Channel 6 output to pin */ - PORTCFG_EVOUTSEL_7_gc = (0x07<<0), /* Event Channel 7 output to pin */ -} PORTCFG_EVOUTSEL_t; - - -/* --------------------------------------------------------------------------- -CRC - Cyclic Redundancy Checker --------------------------------------------------------------------------- -*/ - -/* Cyclic Redundancy Checker */ -typedef struct CRC_struct -{ - register8_t CTRL; /* Control Register */ - register8_t STATUS; /* Status Register */ - register8_t reserved_0x02; - register8_t DATAIN; /* Data Input */ - register8_t CHECKSUM0; /* Checksum byte 0 */ - register8_t CHECKSUM1; /* Checksum byte 1 */ - register8_t CHECKSUM2; /* Checksum byte 2 */ - register8_t CHECKSUM3; /* Checksum byte 3 */ -} CRC_t; - -/* Reset */ -typedef enum CRC_RESET_enum -{ - CRC_RESET_NO_gc = (0x00<<6), /* No Reset */ - CRC_RESET_RESET0_gc = (0x02<<6), /* Reset CRC with CHECKSUM to all zeros */ - CRC_RESET_RESET1_gc = (0x03<<6), /* Reset CRC with CHECKSUM to all ones */ -} CRC_RESET_t; - -/* Input Source */ -typedef enum CRC_SOURCE_enum -{ - CRC_SOURCE_DISABLE_gc = (0x00<<0), /* Disabled */ - CRC_SOURCE_IO_gc = (0x01<<0), /* I/O Interface */ - CRC_SOURCE_FLASH_gc = (0x02<<0), /* Flash */ - CRC_SOURCE_DMAC0_gc = (0x04<<0), /* DMAC Channel 0 */ - CRC_SOURCE_DMAC1_gc = (0x05<<0), /* DMAC Channel 1 */ - CRC_SOURCE_DMAC2_gc = (0x06<<0), /* DMAC Channel 2 */ - CRC_SOURCE_DMAC3_gc = (0x07<<0), /* DMAC Channel 3 */ -} CRC_SOURCE_t; - - -/* --------------------------------------------------------------------------- -EDMA - Enhanced DMA Controller --------------------------------------------------------------------------- -*/ - -/* EDMA Channel */ -typedef struct EDMA_CH_struct -{ - register8_t CTRLA; /* Channel Control A */ - register8_t CTRLB; /* Channel Control */ - register8_t ADDRCTRL; /* Memory Address Control for Peripheral Ch., or Source Address Control for Standard Ch. */ - register8_t DESTADDRCTRL; /* Destination Address Control for Standard Channels Only. */ - register8_t TRIGSRC; /* Channel Trigger Source */ - register8_t reserved_0x05; - _WORDREGISTER(TRFCNT); /* Channel Block Transfer Count for Peripheral Ch., or Channel Block Transfer Count Low for Standard Ch. */ - _WORDREGISTER(ADDR); /* Channel Memory Address for Peripheral Ch., or Channel Source Address Low for Standard Ch. */ - register8_t reserved_0x0A; - register8_t reserved_0x0B; - _WORDREGISTER(DESTADDR); /* Channel Destination Address for Standard Channels Only. */ - register8_t reserved_0x0E; - register8_t reserved_0x0F; -} EDMA_CH_t; - - -/* Enhanced DMA Controller */ -typedef struct EDMA_struct -{ - register8_t CTRL; /* Control */ - register8_t reserved_0x01; - register8_t reserved_0x02; - register8_t INTFLAGS; /* Transfer Interrupt Status */ - register8_t STATUS; /* Status */ - register8_t reserved_0x05; - register8_t TEMP; /* Temporary Register For 16-bit Access */ - register8_t reserved_0x07; - register8_t reserved_0x08; - register8_t reserved_0x09; - register8_t reserved_0x0A; - register8_t reserved_0x0B; - register8_t reserved_0x0C; - register8_t reserved_0x0D; - register8_t reserved_0x0E; - register8_t reserved_0x0F; - EDMA_CH_t CH0; /* EDMA Channel 0 */ - EDMA_CH_t CH1; /* EDMA Channel 1 */ - EDMA_CH_t CH2; /* EDMA Channel 2 */ - EDMA_CH_t CH3; /* EDMA Channel 3 */ -} EDMA_t; - -/* Channel mode */ -typedef enum EDMA_CHMODE_enum -{ - EDMA_CHMODE_PER0123_gc = (0x00<<4), /* Channels 0, 1, 2 and 3 in peripheal conf. */ - EDMA_CHMODE_STD0_gc = (0x01<<4), /* Channel 0 in standard conf.; channels 2 and 3 in peripheral conf. */ - EDMA_CHMODE_STD2_gc = (0x02<<4), /* Channel 2 in standard conf.; channels 0 and 1 in peripheral conf. */ - EDMA_CHMODE_STD02_gc = (0x03<<4), /* Channels 0 and 2 in standard conf. */ -} EDMA_CHMODE_t; - -/* Double buffer mode */ -typedef enum EDMA_DBUFMODE_enum -{ - EDMA_DBUFMODE_DISABLE_gc = (0x00<<2), /* No double buffer enabled */ - EDMA_DBUFMODE_BUF01_gc = (0x01<<2), /* Double buffer enabled on peripheral channels 0/1 (if exist) */ - EDMA_DBUFMODE_BUF23_gc = (0x02<<2), /* Double buffer enabled on peripheral channels 2/3 (if exist) */ - EDMA_DBUFMODE_BUF0123_gc = (0x03<<2), /* Double buffer enabled on peripheral channels 0/1 and 2/3 or standard channels 0/2 */ -} EDMA_DBUFMODE_t; - -/* Priority mode */ -typedef enum EDMA_PRIMODE_enum -{ - EDMA_PRIMODE_RR0123_gc = (0x00<<0), /* Round robin on all channels */ - EDMA_PRIMODE_RR123_gc = (0x01<<0), /* Ch0 > round robin (Ch 1 ch2 Ch3) */ - EDMA_PRIMODE_RR23_gc = (0x02<<0), /* Ch0 > Ch 1 > round robin (Ch2 Ch3) */ - EDMA_PRIMODE_CH0123_gc = (0x03<<0), /* Ch0 > Ch1 > Ch2 > Ch3 */ -} EDMA_PRIMODE_t; - -/* Memory Address Reload for Peripheral Ch., or Source Address Reload for Standard Ch. */ -typedef enum EDMA_CH_RELOAD_enum -{ - EDMA_CH_RELOAD_NONE_gc = (0x00<<4), /* No reload */ - EDMA_CH_RELOAD_BLOCK_gc = (0x01<<4), /* Reload at end of each block transfer */ - EDMA_CH_RELOAD_BURST_gc = (0x02<<4), /* Reload at end of each burst transfer */ - EDMA_CH_RELOAD_TRANSACTION_gc = (0x03<<4), /* Reload at end of each transaction */ -} EDMA_CH_RELOAD_t; - -/* Memory Address Mode for Peripheral Ch., or Source Address Mode for Standard Ch. */ -typedef enum EDMA_CH_DIR_enum -{ - EDMA_CH_DIR_FIXED_gc = (0x00<<0), /* Fixed */ - EDMA_CH_DIR_INC_gc = (0x01<<0), /* Increment */ - EDMA_CH_DIR_MP1_gc = (0x04<<0), /* If Peripheral Ch. (Per ==> Mem), 1-byte 'mask-match' (data: ADDRL, mask: ADDRH), else reserved conf. */ - EDMA_CH_DIR_MP2_gc = (0x05<<0), /* If Peripheral Ch. (Per ==> Mem), 1-byte 'OR-match' (data-1: ADDRL OR data-2: ADDRH), else reserved conf. */ - EDMA_CH_DIR_MP3_gc = (0x06<<0), /* If Peripheral Ch. (Per ==> Mem), 2-byte 'match' (data-1: ADDRL followed by data-2: ADDRH), else reserved conf. */ -} EDMA_CH_DIR_t; - -/* Destination addressing mode */ -typedef enum EDMA_CH_DESTDIR_enum -{ - EDMA_CH_DESTDIR_FIXED_gc = (0x00<<0), /* Fixed */ - EDMA_CH_DESTDIR_INC_gc = (0x01<<0), /* Increment */ - EDMA_CH_DESTDIR_MP1_gc = (0x04<<0), /* 1-byte 'mask-match' (data: ADDRL, mask: ADDRH) */ - EDMA_CH_DESTDIR_MP2_gc = (0x05<<0), /* 1-byte 'OR-match' (data-1: ADDRL OR data-2: ADDRH) */ - EDMA_CH_DESTDIR_MP3_gc = (0x06<<0), /* 2-byte 'match' (data1: ADDRL followed by data2: ADDRH) */ -} EDMA_CH_DESTDIR_t; - -/* Transfer trigger source */ -typedef enum EDMA_CH_TRIGSRC_enum -{ - EDMA_CH_TRIGSRC_OFF_gc = (0x00<<0), /* Software triggers only */ - EDMA_CH_TRIGSRC_EVSYS_CH0_gc = (0x01<<0), /* Event CH0 as trigger (Standard Channels Only) */ - EDMA_CH_TRIGSRC_EVSYS_CH1_gc = (0x02<<0), /* Event CH1 as trigger (Standard Channels Only) */ - EDMA_CH_TRIGSRC_EVSYS_CH2_gc = (0x03<<0), /* Event CH2 as trigger (Standard Channels Only) */ - EDMA_CH_TRIGSRC_ADCA_CH0_gc = (0x10<<0), /* ADCA CH0 as trigger */ - EDMA_CH_TRIGSRC_DACA_CH0_gc = (0x15<<0), /* DACA CH0 as trigger */ - EDMA_CH_TRIGSRC_DACA_CH1_gc = (0x16<<0), /* DACA CH1 as trigger */ - EDMA_CH_TRIGSRC_TCC4_OVF_gc = (0x40<<0), /* TCC4 overflow/underflow as trigger (Standard Channels Only) */ - EDMA_CH_TRIGSRC_TCC4_ERR_gc = (0x41<<0), /* TCC4 error as trigger (Standard Channels Only) */ - EDMA_CH_TRIGSRC_TCC4_CCA_gc = (0x42<<0), /* TCC4 compare or capture channel A as trigger (Standard Channels Only) */ - EDMA_CH_TRIGSRC_TCC4_CCB_gc = (0x43<<0), /* TCC4 compare or capture channel B as trigger (Standard Channels Only) */ - EDMA_CH_TRIGSRC_TCC4_CCC_gc = (0x44<<0), /* TCC4 compare or capture channel C as trigger (Standard Channels Only) */ - EDMA_CH_TRIGSRC_TCC4_CCD_gc = (0x45<<0), /* TCC4 compare or capture channel D as trigger (Standard Channels Only) */ - EDMA_CH_TRIGSRC_TCC5_OVF_gc = (0x46<<0), /* TCC5 overflow/underflow as trigger (Standard Channels Only) */ - EDMA_CH_TRIGSRC_TCC5_ERR_gc = (0x47<<0), /* TCC5 error as trigger (Standard Channels Only) */ - EDMA_CH_TRIGSRC_TCC5_CCA_gc = (0x48<<0), /* TCC5 compare or capture channel A as trigger (Standard Channels Only) */ - EDMA_CH_TRIGSRC_TCC5_CCB_gc = (0x49<<0), /* TCC5 compare or capture channel B as trigger (Standard Channels Only) */ - EDMA_CH_TRIGSRC_SPIC_RXC_gc = (0x4A<<0), /* SPI C transfer complete (SPI Standard Mode) or SPI C receive complete as trigger (SPI Buffer Modes) */ - EDMA_CH_TRIGSRC_SPIC_DRE_gc = (0x4B<<0), /* SPI C transfer complete (SPI Standard Mode) or SPI C data register empty as trigger (SPI Buffer modes) */ - EDMA_CH_TRIGSRC_USARTC0_RXC_gc = (0x4C<<0), /* USART C0 receive complete as trigger */ - EDMA_CH_TRIGSRC_USARTC0_DRE_gc = (0x4D<<0), /* USART C0 data register empty as trigger */ - EDMA_CH_TRIGSRC_TCD5_OVF_gc = (0x66<<0), /* TCD5 overflow/underflow as trigger (Standard Channels Only) */ - EDMA_CH_TRIGSRC_TCD5_ERR_gc = (0x67<<0), /* TCD5 error as trigger (Standard Channels Only) */ - EDMA_CH_TRIGSRC_TCD5_CCA_gc = (0x68<<0), /* TCD5 compare or capture channel A as trigger (Standard Channels Only) */ - EDMA_CH_TRIGSRC_TCD5_CCB_gc = (0x69<<0), /* TCD5 compare or capture channel B as trigger (Standard Channels Only) */ - EDMA_CH_TRIGSRC_USARTD0_RXC_gc = (0x6C<<0), /* USART D0 receive complete as trigger */ - EDMA_CH_TRIGSRC_USARTD0_DRE_gc = (0x6D<<0), /* USART D0 data register empty as trigger */ -} EDMA_CH_TRIGSRC_t; - -/* Interrupt level */ -typedef enum EDMA_CH_INTLVL_enum -{ - EDMA_CH_INTLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ - EDMA_CH_INTLVL_LO_gc = (0x01<<2), /* Low level */ - EDMA_CH_INTLVL_MED_gc = (0x02<<2), /* Medium level */ - EDMA_CH_INTLVL_HI_gc = (0x03<<2), /* High level */ -} EDMA_CH_INTLVL_t; - - -/* --------------------------------------------------------------------------- -EVSYS - Event System --------------------------------------------------------------------------- -*/ - -/* Event System */ -typedef struct EVSYS_struct -{ - register8_t CH0MUX; /* Event Channel 0 Multiplexer */ - register8_t CH1MUX; /* Event Channel 1 Multiplexer */ - register8_t CH2MUX; /* Event Channel 2 Multiplexer */ - register8_t CH3MUX; /* Event Channel 3 Multiplexer */ - register8_t CH4MUX; /* Event Channel 4 Multiplexer */ - register8_t CH5MUX; /* Event Channel 5 Multiplexer */ - register8_t CH6MUX; /* Event Channel 6 Multiplexer */ - register8_t CH7MUX; /* Event Channel 7 Multiplexer */ - register8_t CH0CTRL; /* Channel 0 Control Register */ - register8_t CH1CTRL; /* Channel 1 Control Register */ - register8_t CH2CTRL; /* Channel 2 Control Register */ - register8_t CH3CTRL; /* Channel 3 Control Register */ - register8_t CH4CTRL; /* Channel 4 Control Register */ - register8_t CH5CTRL; /* Channel 5 Control Register */ - register8_t CH6CTRL; /* Channel 6 Control Register */ - register8_t CH7CTRL; /* Channel 7 Control Register */ - register8_t STROBE; /* Event Strobe */ - register8_t DATA; /* Event Data */ - register8_t DFCTRL; /* Digital Filter Control Register */ -} EVSYS_t; - -/* Event Channel multiplexer input selection */ -typedef enum EVSYS_CHMUX_enum -{ - EVSYS_CHMUX_OFF_gc = (0x00<<0), /* Off */ - EVSYS_CHMUX_RTC_OVF_gc = (0x08<<0), /* RTC Overflow */ - EVSYS_CHMUX_RTC_CMP_gc = (0x09<<0), /* RTC Compare Match */ - EVSYS_CHMUX_ACA_CH0_gc = (0x10<<0), /* Analog Comparator A Channel 0 */ - EVSYS_CHMUX_ACA_CH1_gc = (0x11<<0), /* Analog Comparator A Channel 1 */ - EVSYS_CHMUX_ACA_WIN_gc = (0x12<<0), /* Analog Comparator A Window */ - EVSYS_CHMUX_ADCA_CH0_gc = (0x20<<0), /* ADC A Channel 0 */ - EVSYS_CHMUX_PORTA_PIN0_gc = (0x50<<0), /* Port A, Pin0 */ - EVSYS_CHMUX_PORTA_PIN1_gc = (0x51<<0), /* Port A, Pin1 */ - EVSYS_CHMUX_PORTA_PIN2_gc = (0x52<<0), /* Port A, Pin2 */ - EVSYS_CHMUX_PORTA_PIN3_gc = (0x53<<0), /* Port A, Pin3 */ - EVSYS_CHMUX_PORTA_PIN4_gc = (0x54<<0), /* Port A, Pin4 */ - EVSYS_CHMUX_PORTA_PIN5_gc = (0x55<<0), /* Port A, Pin5 */ - EVSYS_CHMUX_PORTA_PIN6_gc = (0x56<<0), /* Port A, Pin6 */ - EVSYS_CHMUX_PORTA_PIN7_gc = (0x57<<0), /* Port A, Pin7 */ - EVSYS_CHMUX_PORTC_PIN0_gc = (0x60<<0), /* Port C, Pin0 */ - EVSYS_CHMUX_PORTC_PIN1_gc = (0x61<<0), /* Port C, Pin1 */ - EVSYS_CHMUX_PORTC_PIN2_gc = (0x62<<0), /* Port C, Pin2 */ - EVSYS_CHMUX_PORTC_PIN3_gc = (0x63<<0), /* Port C, Pin3 */ - EVSYS_CHMUX_PORTC_PIN4_gc = (0x64<<0), /* Port C, Pin4 */ - EVSYS_CHMUX_PORTC_PIN5_gc = (0x65<<0), /* Port C, Pin5 */ - EVSYS_CHMUX_PORTC_PIN6_gc = (0x66<<0), /* Port C, Pin6 */ - EVSYS_CHMUX_PORTC_PIN7_gc = (0x67<<0), /* Port C, Pin7 */ - EVSYS_CHMUX_PORTD_PIN0_gc = (0x68<<0), /* Port D, Pin0 */ - EVSYS_CHMUX_PORTD_PIN1_gc = (0x69<<0), /* Port D, Pin1 */ - EVSYS_CHMUX_PORTD_PIN2_gc = (0x6A<<0), /* Port D, Pin2 */ - EVSYS_CHMUX_PORTD_PIN3_gc = (0x6B<<0), /* Port D, Pin3 */ - EVSYS_CHMUX_PORTD_PIN4_gc = (0x6C<<0), /* Port D, Pin4 */ - EVSYS_CHMUX_PORTD_PIN5_gc = (0x6D<<0), /* Port D, Pin5 */ - EVSYS_CHMUX_PORTD_PIN6_gc = (0x6E<<0), /* Port D, Pin6 */ - EVSYS_CHMUX_PORTD_PIN7_gc = (0x6F<<0), /* Port D, Pin7 */ - EVSYS_CHMUX_PRESCALER_1_gc = (0x80<<0), /* Prescaler, divide by 1 */ - EVSYS_CHMUX_PRESCALER_2_gc = (0x81<<0), /* Prescaler, divide by 2 */ - EVSYS_CHMUX_PRESCALER_4_gc = (0x82<<0), /* Prescaler, divide by 4 */ - EVSYS_CHMUX_PRESCALER_8_gc = (0x83<<0), /* Prescaler, divide by 8 */ - EVSYS_CHMUX_PRESCALER_16_gc = (0x84<<0), /* Prescaler, divide by 16 */ - EVSYS_CHMUX_PRESCALER_32_gc = (0x85<<0), /* Prescaler, divide by 32 */ - EVSYS_CHMUX_PRESCALER_64_gc = (0x86<<0), /* Prescaler, divide by 64 */ - EVSYS_CHMUX_PRESCALER_128_gc = (0x87<<0), /* Prescaler, divide by 128 */ - EVSYS_CHMUX_PRESCALER_256_gc = (0x88<<0), /* Prescaler, divide by 256 */ - EVSYS_CHMUX_PRESCALER_512_gc = (0x89<<0), /* Prescaler, divide by 512 */ - EVSYS_CHMUX_PRESCALER_1024_gc = (0x8A<<0), /* Prescaler, divide by 1024 */ - EVSYS_CHMUX_PRESCALER_2048_gc = (0x8B<<0), /* Prescaler, divide by 2048 */ - EVSYS_CHMUX_PRESCALER_4096_gc = (0x8C<<0), /* Prescaler, divide by 4096 */ - EVSYS_CHMUX_PRESCALER_8192_gc = (0x8D<<0), /* Prescaler, divide by 8192 */ - EVSYS_CHMUX_PRESCALER_16384_gc = (0x8E<<0), /* Prescaler, divide by 16384 */ - EVSYS_CHMUX_PRESCALER_32768_gc = (0x8F<<0), /* Prescaler, divide by 32768 */ - EVSYS_CHMUX_XCL_UNF0_gc = (0xB0<<0), /* XCL BTC0 underflow */ - EVSYS_CHMUX_XCL_UNF1_gc = (0xB1<<0), /* XCL BTC1 underflow */ - EVSYS_CHMUX_XCL_CC0_gc = (0xB2<<0), /* XCL BTC0 capture or compare */ - EVSYS_CHMUX_XCL_CC1_gc = (0xB3<<0), /* XCL BTC0 capture or compare */ - EVSYS_CHMUX_XCL_PEC0_gc = (0xB4<<0), /* XCL PEC0 restart */ - EVSYS_CHMUX_XCL_PEC1_gc = (0xB5<<0), /* XCL PEC1 restart */ - EVSYS_CHMUX_XCL_LUT0_gc = (0xB6<<0), /* XCL LUT0 output */ - EVSYS_CHMUX_XCL_LUT1_gc = (0xB7<<0), /* XCL LUT1 output */ - EVSYS_CHMUX_TCC4_OVF_gc = (0xC0<<0), /* Timer/Counter C4 Overflow */ - EVSYS_CHMUX_TCC4_ERR_gc = (0xC1<<0), /* Timer/Counter C4 Error */ - EVSYS_CHMUX_TCC4_CCA_gc = (0xC4<<0), /* Timer/Counter C4 Compare or Capture A */ - EVSYS_CHMUX_TCC4_CCB_gc = (0xC5<<0), /* Timer/Counter C4 Compare or Capture B */ - EVSYS_CHMUX_TCC4_CCC_gc = (0xC6<<0), /* Timer/Counter C4 Compare or Capture C */ - EVSYS_CHMUX_TCC4_CCD_gc = (0xC7<<0), /* Timer/Counter C4 Compare or Capture D */ - EVSYS_CHMUX_TCC5_OVF_gc = (0xC8<<0), /* Timer/Counter C5 Overflow */ - EVSYS_CHMUX_TCC5_ERR_gc = (0xC9<<0), /* Timer/Counter C5 Error */ - EVSYS_CHMUX_TCC5_CCA_gc = (0xCC<<0), /* Timer/Counter C5 Compare or Capture A */ - EVSYS_CHMUX_TCC5_CCB_gc = (0xCD<<0), /* Timer/Counter C5 Compare or Capture B */ - EVSYS_CHMUX_TCD5_OVF_gc = (0xD8<<0), /* Timer/Counter D5 Overflow */ - EVSYS_CHMUX_TCD5_ERR_gc = (0xD9<<0), /* Timer/Counter D5 Error */ - EVSYS_CHMUX_TCD5_CCA_gc = (0xDC<<0), /* Timer/Counter D5 Compare or Capture A */ - EVSYS_CHMUX_TCD5_CCB_gc = (0xDD<<0), /* Timer/Counter D5 Compare or Capture B */ -} EVSYS_CHMUX_t; - -/* Quadrature Decoder Index Recognition Mode */ -typedef enum EVSYS_QDIRM_enum -{ - EVSYS_QDIRM_00_gc = (0x00<<5), /* QDPH0 = 0, QDPH90 = 0 */ - EVSYS_QDIRM_01_gc = (0x01<<5), /* QDPH0 = 0, QDPH90 = 1 */ - EVSYS_QDIRM_10_gc = (0x02<<5), /* QDPH0 = 1, QDPH90 = 0 */ - EVSYS_QDIRM_11_gc = (0x03<<5), /* QDPH0 = 1, QDPH90 = 1 */ -} EVSYS_QDIRM_t; - -/* Digital filter coefficient */ -typedef enum EVSYS_DIGFILT_enum -{ - EVSYS_DIGFILT_1SAMPLE_gc = (0x00<<0), /* 1 SAMPLE */ - EVSYS_DIGFILT_2SAMPLES_gc = (0x01<<0), /* 2 SAMPLES */ - EVSYS_DIGFILT_3SAMPLES_gc = (0x02<<0), /* 3 SAMPLES */ - EVSYS_DIGFILT_4SAMPLES_gc = (0x03<<0), /* 4 SAMPLES */ - EVSYS_DIGFILT_5SAMPLES_gc = (0x04<<0), /* 5 SAMPLES */ - EVSYS_DIGFILT_6SAMPLES_gc = (0x05<<0), /* 6 SAMPLES */ - EVSYS_DIGFILT_7SAMPLES_gc = (0x06<<0), /* 7 SAMPLES */ - EVSYS_DIGFILT_8SAMPLES_gc = (0x07<<0), /* 8 SAMPLES */ -} EVSYS_DIGFILT_t; - -/* Prescaler Filter */ -typedef enum EVSYS_PRESCFILT_enum -{ - EVSYS_PRESCFILT_CH04_gc = (0x01<<4), /* Enable prescaler filter for either channel 0 or 4 */ - EVSYS_PRESCFILT_CH15_gc = (0x02<<4), /* Enable prescaler filter for either channel 1 or 5 */ - EVSYS_PRESCFILT_CH26_gc = (0x04<<4), /* Enable prescaler filter for either channel 2 or 6 */ - EVSYS_PRESCFILT_CH37_gc = (0x08<<4), /* Enable prescaler filter for either channel 3 or 7 */ -} EVSYS_PRESCFILT_t; - -/* Prescaler */ -typedef enum EVSYS_PRESCALER_enum -{ - EVSYS_PRESCALER_CLKPER_8_gc = (0x00<<0), /* CLKPER, divide by 8 */ - EVSYS_PRESCALER_CLKPER_64_gc = (0x01<<0), /* CLKPER, divide by 64 */ - EVSYS_PRESCALER_CLKPER_512_gc = (0x02<<0), /* CLKPER, divide by 512 */ - EVSYS_PRESCALER_CLKPER_4096_gc = (0x03<<0), /* CLKPER, divide by 4096 */ - EVSYS_PRESCALER_CLKPER_32768_gc = (0x04<<0), /* CLKPER, divide by 32768 */ -} EVSYS_PRESCALER_t; - - -/* --------------------------------------------------------------------------- -NVM - Non Volatile Memory Controller --------------------------------------------------------------------------- -*/ - -/* Non-volatile Memory Controller */ -typedef struct NVM_struct -{ - register8_t ADDR0; /* Address Register 0 */ - register8_t ADDR1; /* Address Register 1 */ - register8_t ADDR2; /* Address Register 2 */ - register8_t reserved_0x03; - register8_t DATA0; /* Data Register 0 */ - register8_t DATA1; /* Data Register 1 */ - register8_t DATA2; /* Data Register 2 */ - register8_t reserved_0x07; - register8_t reserved_0x08; - register8_t reserved_0x09; - register8_t CMD; /* Command */ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t INTCTRL; /* Interrupt Control */ - register8_t reserved_0x0E; - register8_t STATUS; /* Status */ - register8_t LOCK_BITS; /* Lock Bits (Changed from LOCKBITS to avoid avr-libc collision) */ -} NVM_t; - -/* NVM Command */ -typedef enum NVM_CMD_enum -{ - NVM_CMD_NO_OPERATION_gc = (0x00<<0), /* Noop/Ordinary LPM */ - NVM_CMD_READ_USER_SIG_ROW_gc = (0x01<<0), /* Read user signature row */ - NVM_CMD_READ_CALIB_ROW_gc = (0x02<<0), /* Read calibration row */ - NVM_CMD_READ_FUSES_gc = (0x07<<0), /* Read fuse byte */ - NVM_CMD_WRITE_LOCK_BITS_gc = (0x08<<0), /* Write lock bits */ - NVM_CMD_ERASE_USER_SIG_ROW_gc = (0x18<<0), /* Erase user signature row */ - NVM_CMD_WRITE_USER_SIG_ROW_gc = (0x1A<<0), /* Write user signature row */ - NVM_CMD_ERASE_APP_gc = (0x20<<0), /* Erase Application Section */ - NVM_CMD_ERASE_APP_PAGE_gc = (0x22<<0), /* Erase Application Section page */ - NVM_CMD_LOAD_FLASH_BUFFER_gc = (0x23<<0), /* Load Flash page buffer */ - NVM_CMD_WRITE_APP_PAGE_gc = (0x24<<0), /* Write Application Section page */ - NVM_CMD_ERASE_WRITE_APP_PAGE_gc = (0x25<<0), /* Erase-and-write Application Section page */ - NVM_CMD_ERASE_FLASH_BUFFER_gc = (0x26<<0), /* Erase/flush Flash page buffer */ - NVM_CMD_ERASE_BOOT_PAGE_gc = (0x2A<<0), /* Erase Boot Section page */ - NVM_CMD_ERASE_FLASH_PAGE_gc = (0x2B<<0), /* Erase Flash Page */ - NVM_CMD_WRITE_BOOT_PAGE_gc = (0x2C<<0), /* Write Boot Section page */ - NVM_CMD_ERASE_WRITE_BOOT_PAGE_gc = (0x2D<<0), /* Erase-and-write Boot Section page */ - NVM_CMD_WRITE_FLASH_PAGE_gc = (0x2E<<0), /* Write Flash Page */ - NVM_CMD_ERASE_WRITE_FLASH_PAGE_gc = (0x2F<<0), /* Erase-and-write Flash Page */ - NVM_CMD_ERASE_EEPROM_gc = (0x30<<0), /* Erase EEPROM */ - NVM_CMD_ERASE_EEPROM_PAGE_gc = (0x32<<0), /* Erase EEPROM page */ - NVM_CMD_WRITE_EEPROM_PAGE_gc = (0x34<<0), /* Write EEPROM page */ - NVM_CMD_ERASE_WRITE_EEPROM_PAGE_gc = (0x35<<0), /* Erase-and-write EEPROM page */ - NVM_CMD_ERASE_EEPROM_BUFFER_gc = (0x36<<0), /* Erase/flush EEPROM page buffer */ - NVM_CMD_APP_CRC_gc = (0x38<<0), /* Application section CRC */ - NVM_CMD_BOOT_CRC_gc = (0x39<<0), /* Boot Section CRC */ - NVM_CMD_FLASH_RANGE_CRC_gc = (0x3A<<0), /* Flash Range CRC */ - NVM_CMD_CHIP_ERASE_gc = (0x40<<0), /* Erase Chip */ - NVM_CMD_READ_NVM_gc = (0x43<<0), /* Read NVM */ - NVM_CMD_WRITE_FUSE_gc = (0x4C<<0), /* Write Fuse byte */ - NVM_CMD_ERASE_BOOT_gc = (0x68<<0), /* Erase Boot Section */ - NVM_CMD_FLASH_CRC_gc = (0x78<<0), /* Flash CRC */ -} NVM_CMD_t; - -/* SPM ready interrupt level */ -typedef enum NVM_SPMLVL_enum -{ - NVM_SPMLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ - NVM_SPMLVL_LO_gc = (0x01<<2), /* Low level */ - NVM_SPMLVL_MED_gc = (0x02<<2), /* Medium level */ - NVM_SPMLVL_HI_gc = (0x03<<2), /* High level */ -} NVM_SPMLVL_t; - -/* EEPROM ready interrupt level */ -typedef enum NVM_EELVL_enum -{ - NVM_EELVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ - NVM_EELVL_LO_gc = (0x01<<0), /* Low level */ - NVM_EELVL_MED_gc = (0x02<<0), /* Medium level */ - NVM_EELVL_HI_gc = (0x03<<0), /* High level */ -} NVM_EELVL_t; - -/* Boot lock bits - boot setcion */ -typedef enum NVM_BLBB_enum -{ - NVM_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ - NVM_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ - NVM_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ - NVM_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ -} NVM_BLBB_t; - -/* Boot lock bits - application section */ -typedef enum NVM_BLBA_enum -{ - NVM_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ - NVM_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ - NVM_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ - NVM_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ -} NVM_BLBA_t; - -/* Boot lock bits - application table section */ -typedef enum NVM_BLBAT_enum -{ - NVM_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ - NVM_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ - NVM_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ - NVM_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ -} NVM_BLBAT_t; - -/* Lock bits */ -typedef enum NVM_LB_enum -{ - NVM_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ - NVM_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ - NVM_LB_NOLOCK_gc = (0x03<<0), /* No locks */ -} NVM_LB_t; - - -/* --------------------------------------------------------------------------- -ADC - Analog/Digital Converter --------------------------------------------------------------------------- -*/ - -/* ADC Channel */ -typedef struct ADC_CH_struct -{ - register8_t CTRL; /* Control Register */ - register8_t MUXCTRL; /* MUX Control */ - register8_t INTCTRL; /* Channel Interrupt Control Register */ - register8_t INTFLAGS; /* Interrupt Flags */ - _WORDREGISTER(RES); /* Channel Result */ - register8_t SCAN; /* Input Channel Scan */ - register8_t CORRCTRL; /* Correction Control Register */ - register8_t OFFSETCORR0; /* Offset Correction Register 0 */ - register8_t OFFSETCORR1; /* Offset Correction Register 1 */ - register8_t GAINCORR0; /* Gain Correction Register 0 */ - register8_t GAINCORR1; /* Gain Correction Register 1 */ - register8_t AVGCTRL; /* Average Control Register */ - register8_t reserved_0x0D; - register8_t reserved_0x0E; - register8_t reserved_0x0F; -} ADC_CH_t; - - -/* Analog-to-Digital Converter */ -typedef struct ADC_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t REFCTRL; /* Reference Control */ - register8_t EVCTRL; /* Event Control */ - register8_t PRESCALER; /* Clock Prescaler */ - register8_t reserved_0x05; - register8_t INTFLAGS; /* Interrupt Flags */ - register8_t TEMP; /* Temporary Register */ - register8_t SAMPCTRL; /* ADC Sampling Time Control Register */ - register8_t reserved_0x09; - register8_t reserved_0x0A; - register8_t reserved_0x0B; - _WORDREGISTER(CAL); /* Calibration Value */ - register8_t reserved_0x0E; - register8_t reserved_0x0F; - _WORDREGISTER(CH0RES); /* Channel 0 Result */ - register8_t reserved_0x12; - register8_t reserved_0x13; - register8_t reserved_0x14; - register8_t reserved_0x15; - register8_t reserved_0x16; - register8_t reserved_0x17; - _WORDREGISTER(CMP); /* Compare Value */ - register8_t reserved_0x1A; - register8_t reserved_0x1B; - register8_t reserved_0x1C; - register8_t reserved_0x1D; - register8_t reserved_0x1E; - register8_t reserved_0x1F; - ADC_CH_t CH0; /* ADC Channel 0 */ -} ADC_t; - -/* Current Limitation */ -typedef enum ADC_CURRLIMIT_enum -{ - ADC_CURRLIMIT_NO_gc = (0x00<<5), /* No current limit, 300ksps max sampling rate */ - ADC_CURRLIMIT_LOW_gc = (0x01<<5), /* Low current limit, 250ksps max sampling rate */ - ADC_CURRLIMIT_MED_gc = (0x02<<5), /* Medium current limit, 150ksps max sampling rate */ - ADC_CURRLIMIT_HIGH_gc = (0x03<<5), /* High current limit, 50ksps max sampling rate */ -} ADC_CURRLIMIT_t; - -/* Conversion result resolution */ -typedef enum ADC_RESOLUTION_enum -{ - ADC_RESOLUTION_12BIT_gc = (0x00<<1), /* 12-bit right-adjusted result */ - ADC_RESOLUTION_MT12BIT_gc = (0x01<<1), /* More than 12-bit (oversapling) right-adjusted result */ - ADC_RESOLUTION_8BIT_gc = (0x02<<1), /* 8-bit right-adjusted result */ - ADC_RESOLUTION_LEFT12BIT_gc = (0x03<<1), /* 12-bit left-adjusted result */ -} ADC_RESOLUTION_t; - -/* Voltage reference selection */ -typedef enum ADC_REFSEL_enum -{ - ADC_REFSEL_INT1V_gc = (0x00<<4), /* Internal 1V */ - ADC_REFSEL_INTVCC_gc = (0x01<<4), /* Internal VCC / 1.6 */ - ADC_REFSEL_AREFA_gc = (0x02<<4), /* External reference on PORT A */ - ADC_REFSEL_AREFD_gc = (0x03<<4), /* External reference on PORT D */ - ADC_REFSEL_INTVCC2_gc = (0x04<<4), /* Internal VCC / 2 */ -} ADC_REFSEL_t; - -/* Event channel input selection */ -typedef enum ADC_EVSEL_enum -{ - ADC_EVSEL_0_gc = (0x00<<3), /* Event Channel 0 */ - ADC_EVSEL_1_gc = (0x01<<3), /* Event Channel 1 */ - ADC_EVSEL_2_gc = (0x02<<3), /* Event Channel 2 */ - ADC_EVSEL_3_gc = (0x03<<3), /* Event Channel 3 */ - ADC_EVSEL_4_gc = (0x04<<3), /* Event Channel 4 */ - ADC_EVSEL_5_gc = (0x05<<3), /* Event Channel 5 */ - ADC_EVSEL_6_gc = (0x06<<3), /* Event Channel 6 */ - ADC_EVSEL_7_gc = (0x07<<3), /* Event Channel 7 */ -} ADC_EVSEL_t; - -/* Event action selection */ -typedef enum ADC_EVACT_enum -{ - ADC_EVACT_NONE_gc = (0x00<<0), /* No event action */ - ADC_EVACT_CH0_gc = (0x01<<0), /* First event triggers channel conversion */ - ADC_EVACT_SYNCSWEEP_gc = (0x06<<0), /* The ADC is flushed and restarted for accurate timing */ -} ADC_EVACT_t; - -/* Clock prescaler */ -typedef enum ADC_PRESCALER_enum -{ - ADC_PRESCALER_DIV4_gc = (0x00<<0), /* Divide clock by 4 */ - ADC_PRESCALER_DIV8_gc = (0x01<<0), /* Divide clock by 8 */ - ADC_PRESCALER_DIV16_gc = (0x02<<0), /* Divide clock by 16 */ - ADC_PRESCALER_DIV32_gc = (0x03<<0), /* Divide clock by 32 */ - ADC_PRESCALER_DIV64_gc = (0x04<<0), /* Divide clock by 64 */ - ADC_PRESCALER_DIV128_gc = (0x05<<0), /* Divide clock by 128 */ - ADC_PRESCALER_DIV256_gc = (0x06<<0), /* Divide clock by 256 */ - ADC_PRESCALER_DIV512_gc = (0x07<<0), /* Divide clock by 512 */ -} ADC_PRESCALER_t; - -/* Gain factor */ -typedef enum ADC_CH_GAIN_enum -{ - ADC_CH_GAIN_1X_gc = (0x00<<2), /* 1x gain */ - ADC_CH_GAIN_2X_gc = (0x01<<2), /* 2x gain */ - ADC_CH_GAIN_4X_gc = (0x02<<2), /* 4x gain */ - ADC_CH_GAIN_8X_gc = (0x03<<2), /* 8x gain */ - ADC_CH_GAIN_16X_gc = (0x04<<2), /* 16x gain */ - ADC_CH_GAIN_32X_gc = (0x05<<2), /* 32x gain */ - ADC_CH_GAIN_64X_gc = (0x06<<2), /* 64x gain */ - ADC_CH_GAIN_DIV2_gc = (0x07<<2), /* x/2 gain */ -} ADC_CH_GAIN_t; - -/* Input mode */ -typedef enum ADC_CH_INPUTMODE_enum -{ - ADC_CH_INPUTMODE_INTERNAL_gc = (0x00<<0), /* Internal inputs, no gain */ - ADC_CH_INPUTMODE_SINGLEENDED_gc = (0x01<<0), /* Single-ended input, no gain */ - ADC_CH_INPUTMODE_DIFFWGAINL_gc = (0x02<<0), /* Differential input, gain with 4 LSB pins selection */ - ADC_CH_INPUTMODE_DIFFWGAINH_gc = (0x03<<0), /* Differential input, gain with 4 MSB pins selection */ -} ADC_CH_INPUTMODE_t; - -/* Positive input multiplexer selection */ -typedef enum ADC_CH_MUXPOS_enum -{ - ADC_CH_MUXPOS_PIN0_gc = (0x00<<3), /* Input pin 0 */ - ADC_CH_MUXPOS_PIN1_gc = (0x01<<3), /* Input pin 1 */ - ADC_CH_MUXPOS_PIN2_gc = (0x02<<3), /* Input pin 2 */ - ADC_CH_MUXPOS_PIN3_gc = (0x03<<3), /* Input pin 3 */ - ADC_CH_MUXPOS_PIN4_gc = (0x04<<3), /* Input pin 4 */ - ADC_CH_MUXPOS_PIN5_gc = (0x05<<3), /* Input pin 5 */ - ADC_CH_MUXPOS_PIN6_gc = (0x06<<3), /* Input pin 6 */ - ADC_CH_MUXPOS_PIN7_gc = (0x07<<3), /* Input pin 7 */ - ADC_CH_MUXPOS_PIN8_gc = (0x08<<3), /* Input pin 8 */ - ADC_CH_MUXPOS_PIN9_gc = (0x09<<3), /* Input pin 9 */ - ADC_CH_MUXPOS_PIN10_gc = (0x0A<<3), /* Input pin 10 */ - ADC_CH_MUXPOS_PIN11_gc = (0x0B<<3), /* Input pin 11 */ - ADC_CH_MUXPOS_PIN12_gc = (0x0C<<3), /* Input pin 12 */ - ADC_CH_MUXPOS_PIN13_gc = (0x0D<<3), /* Input pin 13 */ - ADC_CH_MUXPOS_PIN14_gc = (0x0E<<3), /* Input pin 14 */ - ADC_CH_MUXPOS_PIN15_gc = (0x0F<<3), /* Input pin 15 */ -} ADC_CH_MUXPOS_t; - -/* Internal input multiplexer selections */ -typedef enum ADC_CH_MUXINT_enum -{ - ADC_CH_MUXINT_TEMP_gc = (0x00<<3), /* Temperature Reference */ - ADC_CH_MUXINT_BANDGAP_gc = (0x01<<3), /* Bandgap Reference */ - ADC_CH_MUXINT_SCALEDVCC_gc = (0x02<<3), /* 1/10 Scaled VCC */ - ADC_CH_MUXINT_DAC_gc = (0x03<<3), /* DAC Output */ -} ADC_CH_MUXINT_t; - -/* Negative input multiplexer selection when gain on 4 LSB pins */ -typedef enum ADC_CH_MUXNEGL_enum -{ - ADC_CH_MUXNEGL_PIN0_gc = (0x00<<0), /* Input pin 0 */ - ADC_CH_MUXNEGL_PIN1_gc = (0x01<<0), /* Input pin 1 */ - ADC_CH_MUXNEGL_PIN2_gc = (0x02<<0), /* Input pin 2 */ - ADC_CH_MUXNEGL_PIN3_gc = (0x03<<0), /* Input pin 3 */ - ADC_CH_MUXNEGL_GND_gc = (0x05<<0), /* PAD ground */ - ADC_CH_MUXNEGL_INTGND_gc = (0x07<<0), /* Internal ground */ -} ADC_CH_MUXNEGL_t; - -/* Negative input multiplexer selection when gain on 4 MSB pins */ -typedef enum ADC_CH_MUXNEGH_enum -{ - ADC_CH_MUXNEGH_PIN4_gc = (0x00<<0), /* Input pin 4 */ - ADC_CH_MUXNEGH_PIN5_gc = (0x01<<0), /* Input pin 5 */ - ADC_CH_MUXNEGH_PIN6_gc = (0x02<<0), /* Input pin 6 */ - ADC_CH_MUXNEGH_PIN7_gc = (0x03<<0), /* Input pin 7 */ - ADC_CH_MUXNEGH_GND_gc = (0x05<<0), /* PAD ground */ -} ADC_CH_MUXNEGH_t; - -/* Negative input multiplexer selection */ -typedef enum ADC_CH_MUXNEG_enum -{ - ADC_CH_MUXNEG_PIN0_gc = (0x00<<0), /* Input pin 0 */ -} ADC_CH_MUXNEG_t; - -/* Interupt mode */ -typedef enum ADC_CH_INTMODE_enum -{ - ADC_CH_INTMODE_COMPLETE_gc = (0x00<<2), /* Interrupt on conversion complete */ - ADC_CH_INTMODE_BELOW_gc = (0x01<<2), /* Interrupt on result below compare value */ - ADC_CH_INTMODE_ABOVE_gc = (0x03<<2), /* Interrupt on result above compare value */ -} ADC_CH_INTMODE_t; - -/* Interrupt level */ -typedef enum ADC_CH_INTLVL_enum -{ - ADC_CH_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ - ADC_CH_INTLVL_LO_gc = (0x01<<0), /* Low level */ - ADC_CH_INTLVL_MED_gc = (0x02<<0), /* Medium level */ - ADC_CH_INTLVL_HI_gc = (0x03<<0), /* High level */ -} ADC_CH_INTLVL_t; - -/* Averaged Number of Samples */ -typedef enum ADC_SAMPNUM_enum -{ - ADC_SAMPNUM_1X_gc = (0x00<<0), /* 1 Sample */ - ADC_SAMPNUM_2X_gc = (0x01<<0), /* 2 Samples */ - ADC_SAMPNUM_4X_gc = (0x02<<0), /* 4 Samples */ - ADC_SAMPNUM_8X_gc = (0x03<<0), /* 8 Samples */ - ADC_SAMPNUM_16X_gc = (0x04<<0), /* 16 Samples */ - ADC_SAMPNUM_32X_gc = (0x05<<0), /* 32 Samples */ - ADC_SAMPNUM_64X_gc = (0x06<<0), /* 64 Samples */ - ADC_SAMPNUM_128X_gc = (0x07<<0), /* 128 Samples */ - ADC_SAMPNUM_256X_gc = (0x08<<0), /* 256 Samples */ - ADC_SAMPNUM_512X_gc = (0x09<<0), /* 512 Samples */ - ADC_SAMPNUM_1024X_gc = (0x0A<<0), /* 1024 Samples */ -} ADC_SAMPNUM_t; - - -/* --------------------------------------------------------------------------- -DAC - Digital/Analog Converter --------------------------------------------------------------------------- -*/ - -/* Digital-to-Analog Converter */ -typedef struct DAC_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t CTRLC; /* Control Register C */ - register8_t EVCTRL; /* Event Input Control */ - register8_t reserved_0x04; - register8_t STATUS; /* Status */ - register8_t reserved_0x06; - register8_t reserved_0x07; - register8_t CH0GAINCAL; /* Gain Calibration */ - register8_t CH0OFFSETCAL; /* Offset Calibration */ - register8_t CH1GAINCAL; /* Gain Calibration */ - register8_t CH1OFFSETCAL; /* Offset Calibration */ - register8_t reserved_0x0C; - register8_t reserved_0x0D; - register8_t reserved_0x0E; - register8_t reserved_0x0F; - register8_t reserved_0x10; - register8_t reserved_0x11; - register8_t reserved_0x12; - register8_t reserved_0x13; - register8_t reserved_0x14; - register8_t reserved_0x15; - register8_t reserved_0x16; - register8_t reserved_0x17; - _WORDREGISTER(CH0DATA); /* Channel 0 Data */ - _WORDREGISTER(CH1DATA); /* Channel 1 Data */ -} DAC_t; - -/* Output channel selection */ -typedef enum DAC_CHSEL_enum -{ - DAC_CHSEL_SINGLE_gc = (0x00<<5), /* Single channel operation (Channel 0 only) */ - DAC_CHSEL_SINGLE1_gc = (0x01<<5), /* Single channel operation (Channel 1 only) */ - DAC_CHSEL_DUAL_gc = (0x02<<5), /* Dual channel operation (Channel 0 and channel 1) */ -} DAC_CHSEL_t; - -/* Reference voltage selection */ -typedef enum DAC_REFSEL_enum -{ - DAC_REFSEL_INT1V_gc = (0x00<<3), /* Internal 1V */ - DAC_REFSEL_AVCC_gc = (0x01<<3), /* Analog supply voltage */ - DAC_REFSEL_AREFA_gc = (0x02<<3), /* External reference on AREF on PORTA */ - DAC_REFSEL_AREFB_gc = (0x03<<3), /* External reference on AREF on PORTB */ -} DAC_REFSEL_t; - -/* Event channel selection */ -typedef enum DAC_EVSEL_enum -{ - DAC_EVSEL_0_gc = (0x00<<0), /* Event Channel 0 */ - DAC_EVSEL_1_gc = (0x01<<0), /* Event Channel 1 */ - DAC_EVSEL_2_gc = (0x02<<0), /* Event Channel 2 */ - DAC_EVSEL_3_gc = (0x03<<0), /* Event Channel 3 */ - DAC_EVSEL_4_gc = (0x04<<0), /* Event Channel 4 */ - DAC_EVSEL_5_gc = (0x05<<0), /* Event Channel 5 */ - DAC_EVSEL_6_gc = (0x06<<0), /* Event Channel 6 */ - DAC_EVSEL_7_gc = (0x07<<0), /* Event Channel 7 */ -} DAC_EVSEL_t; - - -/* --------------------------------------------------------------------------- -AC - Analog Comparator --------------------------------------------------------------------------- -*/ - -/* Analog Comparator */ -typedef struct AC_struct -{ - register8_t AC0CTRL; /* Analog Comparator 0 Control */ - register8_t AC1CTRL; /* Analog Comparator 1 Control */ - register8_t AC0MUXCTRL; /* Analog Comparator 0 MUX Control */ - register8_t AC1MUXCTRL; /* Analog Comparator 1 MUX Control */ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t WINCTRL; /* Window Mode Control */ - register8_t STATUS; /* Status */ - register8_t CURRCTRL; /* Current Source Control Register */ - register8_t CURRCALIB; /* Current Source Calibration Register */ -} AC_t; - -/* Interrupt mode */ -typedef enum AC_INTMODE_enum -{ - AC_INTMODE_BOTHEDGES_gc = (0x00<<6), /* Interrupt on both edges */ - AC_INTMODE_FALLING_gc = (0x02<<6), /* Interrupt on falling edge */ - AC_INTMODE_RISING_gc = (0x03<<6), /* Interrupt on rising edge */ -} AC_INTMODE_t; - -/* Interrupt level */ -typedef enum AC_INTLVL_enum -{ - AC_INTLVL_OFF_gc = (0x00<<4), /* Interrupt disabled */ - AC_INTLVL_LO_gc = (0x01<<4), /* Low level */ - AC_INTLVL_MED_gc = (0x02<<4), /* Medium level */ - AC_INTLVL_HI_gc = (0x03<<4), /* High level */ -} AC_INTLVL_t; - -/* Hysteresis mode selection */ -typedef enum AC_HYSMODE_enum -{ - AC_HYSMODE_NO_gc = (0x00<<1), /* No hysteresis */ - AC_HYSMODE_SMALL_gc = (0x01<<1), /* Small hysteresis */ - AC_HYSMODE_LARGE_gc = (0x02<<1), /* Large hysteresis */ -} AC_HYSMODE_t; - -/* Positive input multiplexer selection */ -typedef enum AC_MUXPOS_enum -{ - AC_MUXPOS_PIN0_gc = (0x00<<3), /* Pin 0 */ - AC_MUXPOS_PIN1_gc = (0x01<<3), /* Pin 1 */ - AC_MUXPOS_PIN2_gc = (0x02<<3), /* Pin 2 */ - AC_MUXPOS_PIN3_gc = (0x03<<3), /* Pin 3 */ - AC_MUXPOS_PIN4_gc = (0x04<<3), /* Pin 4 */ - AC_MUXPOS_PIN5_gc = (0x05<<3), /* Pin 5 */ - AC_MUXPOS_PIN6_gc = (0x06<<3), /* Pin 6 */ - AC_MUXPOS_DAC_gc = (0x07<<3), /* DAC output */ -} AC_MUXPOS_t; - -/* Negative input multiplexer selection */ -typedef enum AC_MUXNEG_enum -{ - AC_MUXNEG_PIN0_gc = (0x00<<0), /* Pin 0 */ - AC_MUXNEG_PIN1_gc = (0x01<<0), /* Pin 1 */ - AC_MUXNEG_PIN3_gc = (0x02<<0), /* Pin 3 */ - AC_MUXNEG_PIN5_gc = (0x03<<0), /* Pin 5 */ - AC_MUXNEG_PIN7_gc = (0x04<<0), /* Pin 7 */ - AC_MUXNEG_DAC_gc = (0x05<<0), /* DAC output */ - AC_MUXNEG_BANDGAP_gc = (0x06<<0), /* Bandgap Reference */ - AC_MUXNEG_SCALER_gc = (0x07<<0), /* Internal voltage scaler */ -} AC_MUXNEG_t; - -/* Windows interrupt mode */ -typedef enum AC_WINTMODE_enum -{ - AC_WINTMODE_ABOVE_gc = (0x00<<2), /* Interrupt on above window */ - AC_WINTMODE_INSIDE_gc = (0x01<<2), /* Interrupt on inside window */ - AC_WINTMODE_BELOW_gc = (0x02<<2), /* Interrupt on below window */ - AC_WINTMODE_OUTSIDE_gc = (0x03<<2), /* Interrupt on outside window */ -} AC_WINTMODE_t; - -/* Window interrupt level */ -typedef enum AC_WINTLVL_enum -{ - AC_WINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ - AC_WINTLVL_LO_gc = (0x01<<0), /* Low priority */ - AC_WINTLVL_MED_gc = (0x02<<0), /* Medium priority */ - AC_WINTLVL_HI_gc = (0x03<<0), /* High priority */ -} AC_WINTLVL_t; - -/* Window mode state */ -typedef enum AC_WSTATE_enum -{ - AC_WSTATE_ABOVE_gc = (0x00<<6), /* Signal above window */ - AC_WSTATE_INSIDE_gc = (0x01<<6), /* Signal inside window */ - AC_WSTATE_BELOW_gc = (0x02<<6), /* Signal below window */ -} AC_WSTATE_t; - - -/* --------------------------------------------------------------------------- -RTC - Real-Time Clounter --------------------------------------------------------------------------- -*/ - -/* Real-Time Counter */ -typedef struct RTC_struct -{ - register8_t CTRL; /* Control Register */ - register8_t STATUS; /* Status Register */ - register8_t INTCTRL; /* Interrupt Control Register */ - register8_t INTFLAGS; /* Interrupt Flags */ - register8_t TEMP; /* Temporary register */ - register8_t reserved_0x05; - register8_t CALIB; /* Calibration Register */ - register8_t reserved_0x07; - _WORDREGISTER(CNT); /* Count Register */ - _WORDREGISTER(PER); /* Period Register */ - _WORDREGISTER(COMP); /* Compare Register */ -} RTC_t; - -/* Prescaler Factor */ -typedef enum RTC_PRESCALER_enum -{ - RTC_PRESCALER_OFF_gc = (0x00<<0), /* RTC Off */ - RTC_PRESCALER_DIV1_gc = (0x01<<0), /* RTC Clock */ - RTC_PRESCALER_DIV2_gc = (0x02<<0), /* RTC Clock / 2 */ - RTC_PRESCALER_DIV8_gc = (0x03<<0), /* RTC Clock / 8 */ - RTC_PRESCALER_DIV16_gc = (0x04<<0), /* RTC Clock / 16 */ - RTC_PRESCALER_DIV64_gc = (0x05<<0), /* RTC Clock / 64 */ - RTC_PRESCALER_DIV256_gc = (0x06<<0), /* RTC Clock / 256 */ - RTC_PRESCALER_DIV1024_gc = (0x07<<0), /* RTC Clock / 1024 */ -} RTC_PRESCALER_t; - -/* Compare Interrupt level */ -typedef enum RTC_COMPINTLVL_enum -{ - RTC_COMPINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ - RTC_COMPINTLVL_LO_gc = (0x01<<2), /* Low Level */ - RTC_COMPINTLVL_MED_gc = (0x02<<2), /* Medium Level */ - RTC_COMPINTLVL_HI_gc = (0x03<<2), /* High Level */ -} RTC_COMPINTLVL_t; - -/* Overflow Interrupt level */ -typedef enum RTC_OVFINTLVL_enum -{ - RTC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - RTC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ - RTC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ - RTC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ -} RTC_OVFINTLVL_t; - - -/* --------------------------------------------------------------------------- -XCL - XMEGA Custom Logic --------------------------------------------------------------------------- -*/ - -/* XMEGA Custom Logic */ -typedef struct XCL_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t CTRLC; /* Control Register C */ - register8_t CTRLD; /* Control Register D */ - register8_t CTRLE; /* Control Register E */ - register8_t CTRLF; /* Control Register F */ - register8_t CTRLG; /* Control Register G */ - register8_t INTCTRL; /* Interrupt Control Register */ - register8_t INTFLAGS; /* Interrupt Flag Register */ - register8_t PLC; /* Peripheral Lenght Control Register */ - register8_t CNTL; /* Counter Register Low */ - register8_t CNTH; /* Counter Register High */ - register8_t CMPL; /* Compare Register Low */ - register8_t CMPH; /* Compare Register High */ - register8_t PERCAPTL; /* Period or Capture Register Low */ - register8_t PERCAPTH; /* Period or Capture Register High */ -} XCL_t; - -/* LUT0 Output Enable */ -typedef enum XCL_LUTOUTEN_enum -{ - XCL_LUTOUTEN_DISABLE_gc = (0x00<<6), /* LUT0 output disabled */ - XCL_LUTOUTEN_PIN0_gc = (0x01<<6), /* LUT0 Output to pin 0 */ - XCL_LUTOUTEN_PIN4_gc = (0x02<<6), /* LUT0 Output to pin 4 */ -} XCL_LUTOUTEN_t; - -/* Port Selection */ -typedef enum XCL_PORTSEL_enum -{ - XCL_PORTSEL_PC_gc = (0x00<<4), /* Port C for LUT or USARTC0 for PEC */ - XCL_PORTSEL_PD_gc = (0x01<<4), /* Port D for LUT or USARTD0 for PEC */ -} XCL_PORTSEL_t; - -/* LUT Configuration */ -typedef enum XCL_LUTCONF_enum -{ - XCL_LUTCONF_2LUT2IN_gc = (0x00<<0), /* 2-Input two LUT */ - XCL_LUTCONF_2LUT1IN_gc = (0x01<<0), /* Two LUT with duplicated input */ - XCL_LUTCONF_2LUT3IN_gc = (0x02<<0), /* Two LUT with one common input */ - XCL_LUTCONF_1LUT3IN_gc = (0x03<<0), /* 3-Input LUT */ - XCL_LUTCONF_MUX_gc = (0x04<<0), /* One LUT Mux */ - XCL_LUTCONF_DLATCH_gc = (0x05<<0), /* One D-Latch LUT */ - XCL_LUTCONF_RSLATCH_gc = (0x06<<0), /* One RS-Latch LUT */ - XCL_LUTCONF_DFF_gc = (0x07<<0), /* One DFF LUT */ -} XCL_LUTCONF_t; - -/* Input Selection */ -typedef enum XCL_INSEL_enum -{ - XCL_INSEL_EVSYS_gc = (0x00<<6), /* Event system selected as source */ - XCL_INSEL_XCL_gc = (0x01<<6), /* XCL selected as source */ - XCL_INSEL_PINL_gc = (0x02<<6), /* LSB port pin selected as source */ - XCL_INSEL_PINH_gc = (0x03<<6), /* MSB port pin selected as source */ -} XCL_INSEL_t; - -/* Delay Configuration on LUT */ -typedef enum XCL_DLYCONF_enum -{ - XCL_DLYCONF_DISABLE_gc = (0x00<<2), /* Delay element disabled */ - XCL_DLYCONF_IN_gc = (0x01<<2), /* Delay enabled on LUT input */ - XCL_DLYCONF_OUT_gc = (0x02<<2), /* Delay enabled on LUT output */ -} XCL_DLYCONF_t; - -/* Delay Selection */ -typedef enum XCL_DLYSEL_enum -{ - XCL_DLYSEL_DLY11_gc = (0x00<<4), /* One cycle delay for each LUT1 and LUT0 */ - XCL_DLYSEL_DLY12_gc = (0x01<<4), /* One cycle delay for LUT1 and two cycles for LUT0 */ - XCL_DLYSEL_DLY21_gc = (0x02<<4), /* Two cycles delay for LUT1 and one cycle for LUT0 */ - XCL_DLYSEL_DLY22_gc = (0x03<<4), /* Two cycle delays for each LUT1 and LUT0 */ -} XCL_DLYSEL_t; - -/* Clock Selection */ -typedef enum XCL_CLKSEL_enum -{ - XCL_CLKSEL_OFF_gc = (0x00<<0), /* OFF */ - XCL_CLKSEL_DIV1_gc = (0x01<<0), /* Prescaler clk */ - XCL_CLKSEL_DIV2_gc = (0x02<<0), /* Prescaler clk/2 */ - XCL_CLKSEL_DIV4_gc = (0x03<<0), /* Prescaler clk/4 */ - XCL_CLKSEL_DIV8_gc = (0x04<<0), /* Prescaler clk/8 */ - XCL_CLKSEL_DIV64_gc = (0x05<<0), /* Prescaler clk/64 */ - XCL_CLKSEL_DIV256_gc = (0x06<<0), /* Prescaler clk/256 */ - XCL_CLKSEL_DIV1024_gc = (0x07<<0), /* Prescaler clk/1024 */ - XCL_CLKSEL_EVCH0_gc = (0x08<<0), /* Event channel 0 */ - XCL_CLKSEL_EVCH1_gc = (0x09<<0), /* Event channel 1 */ - XCL_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event channel 2 */ - XCL_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event channel 3 */ - XCL_CLKSEL_EVCH4_gc = (0x0C<<0), /* Event channel 4 */ - XCL_CLKSEL_EVCH5_gc = (0x0D<<0), /* Event channel 5 */ - XCL_CLKSEL_EVCH6_gc = (0x0E<<0), /* Event channel 6 */ - XCL_CLKSEL_EVCH7_gc = (0x0F<<0), /* Event channel 7 */ -} XCL_CLKSEL_t; - -/* Timer/Counter Command Selection */ -typedef enum XCL_CMDSEL_enum -{ - XCL_CMDSEL_NONE_gc = (0x00<<7), /* None */ - XCL_CMDSEL_RESTART_gc = (0x01<<7), /* Force restart */ -} XCL_CMDSEL_t; - -/* Timer/Counter Selection */ -typedef enum XCL_TCSEL_enum -{ - XCL_TCSEL_TC16_gc = (0x00<<4), /* 16-bit timer/counter */ - XCL_TCSEL_BTC0_gc = (0x01<<4), /* One 8-bit timer/counter */ - XCL_TCSEL_BTC01_gc = (0x02<<4), /* Two 8-bit timer/counters */ - XCL_TCSEL_BTC0PEC1_gc = (0x03<<4), /* One 8-bit timer/counter and one 8-bit peripheral counter */ - XCL_TCSEL_PEC0BTC1_gc = (0x04<<4), /* One 8-bit timer/counter and one 8-bit peripheral counter */ - XCL_TCSEL_PEC01_gc = (0x05<<4), /* Two 8-bit peripheral counters */ - XCL_TCSEL_BTC0PEC2_gc = (0x06<<4), /* One 8-bit timer/counter and two 4-bit peripheral counters */ -} XCL_TCSEL_t; - -/* Timer/Counter Mode */ -typedef enum XCL_TCMODE_enum -{ - XCL_TCMODE_NORMAL_gc = (0x00<<0), /* Normal mode with compare/period */ - XCL_TCMODE_CAPT_gc = (0x01<<0), /* Capture mode */ - XCL_TCMODE_PWM_gc = (0x02<<0), /* Single Slope PWM */ -} XCL_TCMODE_t; - -/* Compare Output Value Timer */ -typedef enum XCL_CMPEN_enum -{ - XCL_CMPEN_CLEAR_gc = (0x00<<5), /* Clear WG Output */ - XCL_CMPEN_SET_gc = (0x01<<5), /* Set WG Output */ -} XCL_CMPEN_t; - -/* Command Enable */ -typedef enum XCL_CMDEN_enum -{ - XCL_CMDEN_DISABLE_gc = (0x00<<6), /* Command Ignored */ - XCL_CMDEN_CMD0_gc = (0x01<<6), /* Command valid for timer/counter 0 */ - XCL_CMDEN_CMD1_gc = (0x02<<6), /* Command valid for timer/counter 1 */ - XCL_CMDEN_CMD01_gc = (0x03<<6), /* Command valid for both timer/counter 0 and 1 */ -} XCL_CMDEN_t; - -/* Timer/Counter Event Source Selection */ -typedef enum XCL_EVSRC_enum -{ - XCL_EVSRC_EVCH0_gc = (0x00<<0), /* Event channel 0 */ - XCL_EVSRC_EVCH1_gc = (0x01<<0), /* Event channel 1 */ - XCL_EVSRC_EVCH2_gc = (0x02<<0), /* Event channel 2 */ - XCL_EVSRC_EVCH3_gc = (0x03<<0), /* Event channel 3 */ - XCL_EVSRC_EVCH4_gc = (0x04<<0), /* Event channel 4 */ - XCL_EVSRC_EVCH5_gc = (0x05<<0), /* Event channel 5 */ - XCL_EVSRC_EVCH6_gc = (0x06<<0), /* Event channel 6 */ - XCL_EVSRC_EVCH7_gc = (0x07<<0), /* Event channel 7 */ -} XCL_EVSRC_t; - -/* Timer/Counter Event Action Selection */ -typedef enum XCL_EVACT_enum -{ - XCL_EVACT_INPUT_gc = (0x00<<5), /* Input Capture */ - XCL_EVACT_FREQ_gc = (0x01<<5), /* Frequency Capture */ - XCL_EVACT_PW_gc = (0x02<<5), /* Pulse Width Capture */ - XCL_EVACT_RESTART_gc = (0x03<<5), /* Restart timer/counter */ -} XCL_EVACT_t; - -/* Underflow Interrupt level */ -typedef enum XCL_UNF_INTLVL_enum -{ - XCL_UNF_INTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ - XCL_UNF_INTLVL_LO_gc = (0x01<<2), /* Low Level */ - XCL_UNF_INTLVL_MED_gc = (0x02<<2), /* Medium Level */ - XCL_UNF_INTLVL_HI_gc = (0x03<<2), /* High Level */ -} XCL_UNF_INTLVL_t; - -/* Compare/Capture Interrupt level */ -typedef enum XCL_CC_INTLVL_enum -{ - XCL_CC_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - XCL_CC_INTLVL_LO_gc = (0x01<<0), /* Low Level */ - XCL_CC_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ - XCL_CC_INTLVL_HI_gc = (0x03<<0), /* High Level */ -} XCL_CC_INTLVL_t; - - -/* --------------------------------------------------------------------------- -TWI - Two-Wire Interface --------------------------------------------------------------------------- -*/ - -/* */ -typedef struct TWI_MASTER_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t CTRLC; /* Control Register C */ - register8_t STATUS; /* Status Register */ - register8_t BAUD; /* Baurd Rate Control Register */ - register8_t ADDR; /* Address Register */ - register8_t DATA; /* Data Register */ -} TWI_MASTER_t; - - -/* */ -typedef struct TWI_SLAVE_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t STATUS; /* Status Register */ - register8_t ADDR; /* Address Register */ - register8_t DATA; /* Data Register */ - register8_t ADDRMASK; /* Address Mask Register */ -} TWI_SLAVE_t; - - -/* */ -typedef struct TWI_TIMEOUT_struct -{ - register8_t TOS; /* Timeout Status Register */ - register8_t TOCONF; /* Timeout Configuration Register */ -} TWI_TIMEOUT_t; - - -/* Two-Wire Interface */ -typedef struct TWI_struct -{ - register8_t CTRL; /* TWI Common Control Register */ - TWI_MASTER_t MASTER; /* TWI master module */ - TWI_SLAVE_t SLAVE; /* TWI slave module */ - TWI_TIMEOUT_t TIMEOUT; /* TWI SMBUS timeout module */ -} TWI_t; - -/* SDA Hold Time */ -typedef enum TWI_SDAHOLD_enum -{ - TWI_SDAHOLD_OFF_gc = (0x00<<4), /* SDA Hold Time off */ - TWI_SDAHOLD_50NS_gc = (0x01<<4), /* SDA Hold Time 50 ns */ - TWI_SDAHOLD_300NS_gc = (0x02<<4), /* SDA Hold Time 300 ns */ - TWI_SDAHOLD_400NS_gc = (0x03<<4), /* SDA Hold Time 400 ns */ -} TWI_SDAHOLD_t; - -/* Master Interrupt Level */ -typedef enum TWI_MASTER_INTLVL_enum -{ - TWI_MASTER_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ - TWI_MASTER_INTLVL_LO_gc = (0x01<<6), /* Low Level */ - TWI_MASTER_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ - TWI_MASTER_INTLVL_HI_gc = (0x03<<6), /* High Level */ -} TWI_MASTER_INTLVL_t; - -/* Inactive Timeout */ -typedef enum TWI_MASTER_TIMEOUT_enum -{ - TWI_MASTER_TIMEOUT_DISABLED_gc = (0x00<<2), /* Bus Timeout Disabled */ - TWI_MASTER_TIMEOUT_50US_gc = (0x01<<2), /* 50 Microseconds */ - TWI_MASTER_TIMEOUT_100US_gc = (0x02<<2), /* 100 Microseconds */ - TWI_MASTER_TIMEOUT_200US_gc = (0x03<<2), /* 200 Microseconds */ -} TWI_MASTER_TIMEOUT_t; - -/* Master Command */ -typedef enum TWI_MASTER_CMD_enum -{ - TWI_MASTER_CMD_NOACT_gc = (0x00<<0), /* No Action */ - TWI_MASTER_CMD_REPSTART_gc = (0x01<<0), /* Issue Repeated Start Condition */ - TWI_MASTER_CMD_RECVTRANS_gc = (0x02<<0), /* Receive or Transmit Data */ - TWI_MASTER_CMD_STOP_gc = (0x03<<0), /* Issue Stop Condition */ -} TWI_MASTER_CMD_t; - -/* Master Bus State */ -typedef enum TWI_MASTER_BUSSTATE_enum -{ - TWI_MASTER_BUSSTATE_UNKNOWN_gc = (0x00<<0), /* Unknown Bus State */ - TWI_MASTER_BUSSTATE_IDLE_gc = (0x01<<0), /* Bus is Idle */ - TWI_MASTER_BUSSTATE_OWNER_gc = (0x02<<0), /* This Module Controls The Bus */ - TWI_MASTER_BUSSTATE_BUSY_gc = (0x03<<0), /* The Bus is Busy */ -} TWI_MASTER_BUSSTATE_t; - -/* Slave Interrupt Level */ -typedef enum TWI_SLAVE_INTLVL_enum -{ - TWI_SLAVE_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ - TWI_SLAVE_INTLVL_LO_gc = (0x01<<6), /* Low Level */ - TWI_SLAVE_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ - TWI_SLAVE_INTLVL_HI_gc = (0x03<<6), /* High Level */ -} TWI_SLAVE_INTLVL_t; - -/* Slave Command */ -typedef enum TWI_SLAVE_CMD_enum -{ - TWI_SLAVE_CMD_NOACT_gc = (0x00<<0), /* No Action */ - TWI_SLAVE_CMD_COMPTRANS_gc = (0x02<<0), /* Used To Complete a Transaction */ - TWI_SLAVE_CMD_RESPONSE_gc = (0x03<<0), /* Used in Response to Address/Data Interrupt */ -} TWI_SLAVE_CMD_t; - -/* Master Timeout */ -typedef enum TWI_MASTER_TTIMEOUT_enum -{ - TWI_MASTER_TTIMEOUT_25MS_gc = (0x00<<0), /* 25 Milliseconds */ - TWI_MASTER_TTIMEOUT_24MS_gc = (0x01<<0), /* 24 Milliseconds */ - TWI_MASTER_TTIMEOUT_23MS_gc = (0x02<<0), /* 23 Milliseconds */ - TWI_MASTER_TTIMEOUT_22MS_gc = (0x03<<0), /* 22 Milliseconds */ - TWI_MASTER_TTIMEOUT_26MS_gc = (0x04<<0), /* 26 Milliseconds */ - TWI_MASTER_TTIMEOUT_27MS_gc = (0x05<<0), /* 27 Milliseconds */ - TWI_MASTER_TTIMEOUT_28MS_gc = (0x06<<0), /* 28 Milliseconds */ - TWI_MASTER_TTIMEOUT_29MS_gc = (0x07<<0), /* 29 Milliseconds */ -} TWI_MASTER_TTIMEOUT_t; - -/* Slave Ttimeout */ -typedef enum TWI_SLAVE_TTIMEOUT_enum -{ - TWI_SLAVE_TTIMEOUT_25MS_gc = (0x00<<5), /* 25 Milliseconds */ - TWI_SLAVE_TTIMEOUT_24MS_gc = (0x01<<5), /* 24 Milliseconds */ - TWI_SLAVE_TTIMEOUT_23MS_gc = (0x02<<5), /* 23 Milliseconds */ - TWI_SLAVE_TTIMEOUT_22MS_gc = (0x03<<5), /* 22 Milliseconds */ - TWI_SLAVE_TTIMEOUT_26MS_gc = (0x04<<5), /* 26 Milliseconds */ - TWI_SLAVE_TTIMEOUT_27MS_gc = (0x05<<5), /* 27 Milliseconds */ - TWI_SLAVE_TTIMEOUT_28MS_gc = (0x06<<5), /* 28 Milliseconds */ - TWI_SLAVE_TTIMEOUT_29MS_gc = (0x07<<5), /* 29 Milliseconds */ -} TWI_SLAVE_TTIMEOUT_t; - -/* Master/Slave Extend Timeout */ -typedef enum TWI_MASTER_TMSEXT_enum -{ - TWI_MASTER_TMSEXT_10MS25MS_gc = (0x00<<3), /* Tmext 10ms Tsext 25ms */ - TWI_MASTER_TMSEXT_9MS24MS_gc = (0x01<<3), /* Tmext 9ms Tsext 24ms */ - TWI_MASTER_TMSEXT_11MS26MS_gc = (0x02<<3), /* Tmext 11ms Tsext 26ms */ - TWI_MASTER_TMSEXT_12MS27MS_gc = (0x03<<3), /* Tmext 12ms Tsext 27ms */ -} TWI_MASTER_TMSEXT_t; - - -/* --------------------------------------------------------------------------- -PORT - Port Configuration --------------------------------------------------------------------------- -*/ - -/* I/O Ports */ -typedef struct PORT_struct -{ - register8_t DIR; /* I/O Port Data Direction */ - register8_t DIRSET; /* I/O Port Data Direction Set */ - register8_t DIRCLR; /* I/O Port Data Direction Clear */ - register8_t DIRTGL; /* I/O Port Data Direction Toggle */ - register8_t OUT; /* I/O Port Output */ - register8_t OUTSET; /* I/O Port Output Set */ - register8_t OUTCLR; /* I/O Port Output Clear */ - register8_t OUTTGL; /* I/O Port Output Toggle */ - register8_t IN; /* I/O port Input */ - register8_t INTCTRL; /* Interrupt Control Register */ - register8_t INTMASK; /* Port Interrupt Mask */ - register8_t reserved_0x0B; - register8_t INTFLAGS; /* Interrupt Flag Register */ - register8_t reserved_0x0D; - register8_t REMAP; /* Pin Remap Register */ - register8_t reserved_0x0F; - register8_t PIN0CTRL; /* Pin 0 Control Register */ - register8_t PIN1CTRL; /* Pin 1 Control Register */ - register8_t PIN2CTRL; /* Pin 2 Control Register */ - register8_t PIN3CTRL; /* Pin 3 Control Register */ - register8_t PIN4CTRL; /* Pin 4 Control Register */ - register8_t PIN5CTRL; /* Pin 5 Control Register */ - register8_t PIN6CTRL; /* Pin 6 Control Register */ - register8_t PIN7CTRL; /* Pin 7 Control Register */ -} PORT_t; - -/* Port Interrupt Level */ -typedef enum PORT_INTLVL_enum -{ - PORT_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - PORT_INTLVL_LO_gc = (0x01<<0), /* Low Level */ - PORT_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ - PORT_INTLVL_HI_gc = (0x03<<0), /* High Level */ -} PORT_INTLVL_t; - -/* Output/Pull Configuration */ -typedef enum PORT_OPC_enum -{ - PORT_OPC_TOTEM_gc = (0x00<<3), /* Totempole */ - PORT_OPC_BUSKEEPER_gc = (0x01<<3), /* Totempole w/ Bus keeper on Input and Output */ - PORT_OPC_PULLDOWN_gc = (0x02<<3), /* Totempole w/ Pull-down on Input */ - PORT_OPC_PULLUP_gc = (0x03<<3), /* Totempole w/ Pull-up on Input */ - PORT_OPC_WIREDOR_gc = (0x04<<3), /* Wired OR */ - PORT_OPC_WIREDAND_gc = (0x05<<3), /* Wired AND */ - PORT_OPC_WIREDORPULL_gc = (0x06<<3), /* Wired OR w/ Pull-down */ - PORT_OPC_WIREDANDPULL_gc = (0x07<<3), /* Wired AND w/ Pull-up */ -} PORT_OPC_t; - -/* Input/Sense Configuration */ -typedef enum PORT_ISC_enum -{ - PORT_ISC_BOTHEDGES_gc = (0x00<<0), /* Sense Both Edges */ - PORT_ISC_RISING_gc = (0x01<<0), /* Sense Rising Edge */ - PORT_ISC_FALLING_gc = (0x02<<0), /* Sense Falling Edge */ - PORT_ISC_LEVEL_gc = (0x03<<0), /* Sense Level (Transparent For Events) */ - PORT_ISC_FORCE_ENABLE_gc = (0x06<<0), /* Digital Input Buffer Forced Enable */ - PORT_ISC_INPUT_DISABLE_gc = (0x07<<0), /* Disable Digital Input Buffer */ -} PORT_ISC_t; - - -/* --------------------------------------------------------------------------- -TC - 16-bit Timer/Counter With PWM --------------------------------------------------------------------------- -*/ - -/* 16-bit Timer/Counter 4 */ -typedef struct TC4_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t CTRLC; /* Control register C */ - register8_t CTRLD; /* Control Register D */ - register8_t CTRLE; /* Control Register E */ - register8_t CTRLF; /* Control Register F */ - register8_t INTCTRLA; /* Interrupt Control Register A */ - register8_t INTCTRLB; /* Interrupt Control Register B */ - register8_t CTRLGCLR; /* Control Register G Clear */ - register8_t CTRLGSET; /* Control Register G Set */ - register8_t CTRLHCLR; /* Control Register H Clear */ - register8_t CTRLHSET; /* Control Register H Set */ - register8_t INTFLAGS; /* Interrupt Flag Register */ - register8_t reserved_0x0D; - register8_t reserved_0x0E; - register8_t TEMP; /* Temporary Register For 16-bit Access */ - register8_t reserved_0x10; - register8_t reserved_0x11; - register8_t reserved_0x12; - register8_t reserved_0x13; - register8_t reserved_0x14; - register8_t reserved_0x15; - register8_t reserved_0x16; - register8_t reserved_0x17; - register8_t reserved_0x18; - register8_t reserved_0x19; - register8_t reserved_0x1A; - register8_t reserved_0x1B; - register8_t reserved_0x1C; - register8_t reserved_0x1D; - register8_t reserved_0x1E; - register8_t reserved_0x1F; - _WORDREGISTER(CNT); /* Count */ - register8_t reserved_0x22; - register8_t reserved_0x23; - register8_t reserved_0x24; - register8_t reserved_0x25; - _WORDREGISTER(PER); /* Period */ - _WORDREGISTER(CCA); /* Compare or Capture A */ - _WORDREGISTER(CCB); /* Compare or Capture B */ - _WORDREGISTER(CCC); /* Compare or Capture C */ - _WORDREGISTER(CCD); /* Compare or Capture D */ - register8_t reserved_0x30; - register8_t reserved_0x31; - register8_t reserved_0x32; - register8_t reserved_0x33; - register8_t reserved_0x34; - register8_t reserved_0x35; - _WORDREGISTER(PERBUF); /* Period Buffer */ - _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ - _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ - _WORDREGISTER(CCCBUF); /* Compare Or Capture C Buffer */ - _WORDREGISTER(CCDBUF); /* Compare Or Capture D Buffer */ -} TC4_t; - - -/* 16-bit Timer/Counter 5 */ -typedef struct TC5_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t CTRLC; /* Control register C */ - register8_t CTRLD; /* Control Register D */ - register8_t CTRLE; /* Control Register E */ - register8_t CTRLF; /* Control Register F */ - register8_t INTCTRLA; /* Interrupt Control Register A */ - register8_t INTCTRLB; /* Interrupt Control Register B */ - register8_t CTRLGCLR; /* Control Register G Clear */ - register8_t CTRLGSET; /* Control Register G Set */ - register8_t CTRLHCLR; /* Control Register H Clear */ - register8_t CTRLHSET; /* Control Register H Set */ - register8_t INTFLAGS; /* Interrupt Flag Register */ - register8_t reserved_0x0D; - register8_t reserved_0x0E; - register8_t TEMP; /* Temporary Register For 16-bit Access */ - register8_t reserved_0x10; - register8_t reserved_0x11; - register8_t reserved_0x12; - register8_t reserved_0x13; - register8_t reserved_0x14; - register8_t reserved_0x15; - register8_t reserved_0x16; - register8_t reserved_0x17; - register8_t reserved_0x18; - register8_t reserved_0x19; - register8_t reserved_0x1A; - register8_t reserved_0x1B; - register8_t reserved_0x1C; - register8_t reserved_0x1D; - register8_t reserved_0x1E; - register8_t reserved_0x1F; - _WORDREGISTER(CNT); /* Count */ - register8_t reserved_0x22; - register8_t reserved_0x23; - register8_t reserved_0x24; - register8_t reserved_0x25; - _WORDREGISTER(PER); /* Period */ - _WORDREGISTER(CCA); /* Compare or Capture A */ - _WORDREGISTER(CCB); /* Compare or Capture B */ - register8_t reserved_0x2C; - register8_t reserved_0x2D; - register8_t reserved_0x2E; - register8_t reserved_0x2F; - register8_t reserved_0x30; - register8_t reserved_0x31; - register8_t reserved_0x32; - register8_t reserved_0x33; - register8_t reserved_0x34; - register8_t reserved_0x35; - _WORDREGISTER(PERBUF); /* Period Buffer */ - _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ - _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ - register8_t reserved_0x3C; - register8_t reserved_0x3D; - register8_t reserved_0x3E; - register8_t reserved_0x3F; -} TC5_t; - -/* Clock Selection */ -typedef enum TC45_CLKSEL_enum -{ - TC45_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */ - TC45_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */ - TC45_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */ - TC45_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */ - TC45_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */ - TC45_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */ - TC45_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */ - TC45_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */ - TC45_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */ - TC45_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */ - TC45_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */ - TC45_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */ - TC45_CLKSEL_EVCH4_gc = (0x0C<<0), /* Event Channel 4 */ - TC45_CLKSEL_EVCH5_gc = (0x0D<<0), /* Event Channel 5 */ - TC45_CLKSEL_EVCH6_gc = (0x0E<<0), /* Event Channel 6 */ - TC45_CLKSEL_EVCH7_gc = (0x0F<<0), /* Event Channel 7 */ -} TC45_CLKSEL_t; - -/* Byte Mode */ -typedef enum TC45_BYTEM_enum -{ - TC45_BYTEM_NORMAL_gc = (0x00<<6), /* 16-bit mode */ - TC45_BYTEM_BYTEMODE_gc = (0x01<<6), /* Timer/Counter Operating in Byte Mode Only */ -} TC45_BYTEM_t; - -/* Circular Enable Mode */ -typedef enum TC45_CIRCEN_enum -{ - TC45_CIRCEN_DISABLE_gc = (0x00<<4), /* Circular Buffer Disabled */ - TC45_CIRCEN_PER_gc = (0x01<<4), /* Circular Buffer Enabled on PER/PERBUF */ - TC45_CIRCEN_CCA_gc = (0x02<<4), /* Circular Buffer Enabled on CCA/CCABUF */ - TC45_CIRCEN_BOTH_gc = (0x03<<4), /* Circular Buffer Enabled on All Buffered Registers */ -} TC45_CIRCEN_t; - -/* Waveform Generation Mode */ -typedef enum TC45_WGMODE_enum -{ - TC45_WGMODE_NORMAL_gc = (0x00<<0), /* Normal Mode */ - TC45_WGMODE_FRQ_gc = (0x01<<0), /* Frequency Generation Mode */ - TC45_WGMODE_SINGLESLOPE_gc = (0x03<<0), /* Single Slope */ - TC45_WGMODE_DSTOP_gc = (0x05<<0), /* Dual Slope, Update on TOP */ - TC45_WGMODE_DSBOTH_gc = (0x06<<0), /* Dual Slope, Both */ - TC45_WGMODE_DSBOTTOM_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */ -} TC45_WGMODE_t; - -/* Event Action */ -typedef enum TC45_EVACT_enum -{ - TC45_EVACT_OFF_gc = (0x00<<5), /* No Event Action */ - TC45_EVACT_FMODE1_gc = (0x01<<5), /* Fault Mode 1 capture */ - TC45_EVACT_FMODE2_gc = (0x02<<5), /* Fault Mode 2 capture */ - TC45_EVACT_UPDOWN_gc = (0x03<<5), /* Up/down count */ - TC45_EVACT_QDEC_gc = (0x04<<5), /* Quadrature decode */ - TC45_EVACT_RESTART_gc = (0x05<<5), /* Restart */ - TC45_EVACT_PWF_gc = (0x06<<5), /* Pulse-width Capture */ -} TC45_EVACT_t; - -/* Event Selection */ -typedef enum TC45_EVSEL_enum -{ - TC45_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ - TC45_EVSEL_CH0_gc = (0x08<<0), /* Event Channel 0 */ - TC45_EVSEL_CH1_gc = (0x09<<0), /* Event Channel 1 */ - TC45_EVSEL_CH2_gc = (0x0A<<0), /* Event Channel 2 */ - TC45_EVSEL_CH3_gc = (0x0B<<0), /* Event Channel 3 */ - TC45_EVSEL_CH4_gc = (0x0C<<0), /* Event Channel 4 */ - TC45_EVSEL_CH5_gc = (0x0D<<0), /* Event Channel 5 */ - TC45_EVSEL_CH6_gc = (0x0E<<0), /* Event Channel 6 */ - TC45_EVSEL_CH7_gc = (0x0F<<0), /* Event Channel 7 */ -} TC45_EVSEL_t; - -/* Compare or Capture Channel A Mode */ -typedef enum TC45_CCAMODE_enum -{ - TC45_CCAMODE_DISABLE_gc = (0x00<<0), /* Channel Disabled */ - TC45_CCAMODE_COMP_gc = (0x01<<0), /* Ouput Compare enabled */ - TC45_CCAMODE_CAPT_gc = (0x02<<0), /* Input Capture enabled */ - TC45_CCAMODE_BOTHCC_gc = (0x03<<0), /* Both Compare and Capture enabled */ -} TC45_CCAMODE_t; - -/* Compare or Capture Channel B Mode */ -typedef enum TC45_CCBMODE_enum -{ - TC45_CCBMODE_DISABLE_gc = (0x00<<2), /* Channel Disabled */ - TC45_CCBMODE_COMP_gc = (0x01<<2), /* Ouput Compare enabled */ - TC45_CCBMODE_CAPT_gc = (0x02<<2), /* Input Capture enabled */ - TC45_CCBMODE_BOTHCC_gc = (0x03<<2), /* Both Compare and Capture enabled */ -} TC45_CCBMODE_t; - -/* Compare or Capture Channel C Mode */ -typedef enum TC45_CCCMODE_enum -{ - TC45_CCCMODE_DISABLE_gc = (0x00<<4), /* Channel Disabled */ - TC45_CCCMODE_COMP_gc = (0x01<<4), /* Ouput Compare enabled */ - TC45_CCCMODE_CAPT_gc = (0x02<<4), /* Input Capture enabled */ - TC45_CCCMODE_BOTHCC_gc = (0x03<<4), /* Both Compare and Capture enabled */ -} TC45_CCCMODE_t; - -/* Compare or Capture Channel D Mode */ -typedef enum TC45_CCDMODE_enum -{ - TC45_CCDMODE_DISABLE_gc = (0x00<<6), /* Channel Disabled */ - TC45_CCDMODE_COMP_gc = (0x01<<6), /* Ouput Compare enabled */ - TC45_CCDMODE_CAPT_gc = (0x02<<6), /* Input Capture enabled */ - TC45_CCDMODE_BOTHCC_gc = (0x03<<6), /* Both Compare and Capture enabled */ -} TC45_CCDMODE_t; - -/* Compare or Capture Low Channel A Mode */ -typedef enum TC45_LCCAMODE_enum -{ - TC45_LCCAMODE_DISABLE_gc = (0x00<<0), /* Channel Disabled */ - TC45_LCCAMODE_COMP_gc = (0x01<<0), /* Ouput Compare enabled */ - TC45_LCCAMODE_CAPT_gc = (0x02<<0), /* Input Capture enabled */ - TC45_LCCAMODE_BOTHCC_gc = (0x03<<0), /* Both Compare and Capture enabled */ -} TC45_LCCAMODE_t; - -/* Compare or Capture Low Channel B Mode */ -typedef enum TC45_LCCBMODE_enum -{ - TC45_LCCBMODE_DISABLE_gc = (0x00<<2), /* Channel Disabled */ - TC45_LCCBMODE_COMP_gc = (0x01<<2), /* Ouput Compare enabled */ - TC45_LCCBMODE_CAPT_gc = (0x02<<2), /* Input Capture enabled */ - TC45_LCCBMODE_BOTHCC_gc = (0x03<<2), /* Both Compare and Capture enabled */ -} TC45_LCCBMODE_t; - -/* Compare or Capture Low Channel C Mode */ -typedef enum TC45_LCCCMODE_enum -{ - TC45_LCCCMODE_DISABLE_gc = (0x00<<4), /* Channel Disabled */ - TC45_LCCCMODE_COMP_gc = (0x01<<4), /* Ouput Compare enabled */ - TC45_LCCCMODE_CAPT_gc = (0x02<<4), /* Input Capture enabled */ - TC45_LCCCMODE_BOTHCC_gc = (0x03<<4), /* Both Compare and Capture enabled */ -} TC45_LCCCMODE_t; - -/* Compare or Capture Low Channel D Mode */ -typedef enum TC45_LCCDMODE_enum -{ - TC45_LCCDMODE_DISABLE_gc = (0x00<<6), /* Channel Disabled */ - TC45_LCCDMODE_COMP_gc = (0x01<<6), /* Ouput Compare enabled */ - TC45_LCCDMODE_CAPT_gc = (0x02<<6), /* Input Capture enabled */ - TC45_LCCDMODE_BOTHCC_gc = (0x03<<6), /* Both Compare and Capture enabled */ -} TC45_LCCDMODE_t; - -/* Compare or Capture High Channel A Mode */ -typedef enum TC45_HCCAMODE_enum -{ - TC45_HCCAMODE_DISABLE_gc = (0x00<<0), /* Channel Disabled */ - TC45_HCCAMODE_COMP_gc = (0x01<<0), /* Ouput Compare enabled */ - TC45_HCCAMODE_CAPT_gc = (0x02<<0), /* Input Capture enabled */ - TC45_HCCAMODE_BOTHCC_gc = (0x03<<0), /* Both Compare and Capture enabled */ -} TC45_HCCAMODE_t; - -/* Compare or Capture High Channel B Mode */ -typedef enum TC45_HCCBMODE_enum -{ - TC45_HCCBMODE_DISABLE_gc = (0x00<<2), /* Channel Disabled */ - TC45_HCCBMODE_COMP_gc = (0x01<<2), /* Ouput Compare enabled */ - TC45_HCCBMODE_CAPT_gc = (0x02<<2), /* Input Capture enabled */ - TC45_HCCBMODE_BOTHCC_gc = (0x03<<2), /* Both Compare and Capture enabled */ -} TC45_HCCBMODE_t; - -/* Compare or Capture High Channel C Mode */ -typedef enum TC45_HCCCMODE_enum -{ - TC45_HCCCMODE_DISABLE_gc = (0x00<<4), /* Channel Disabled */ - TC45_HCCCMODE_COMP_gc = (0x01<<4), /* Ouput Compare enabled */ - TC45_HCCCMODE_CAPT_gc = (0x02<<4), /* Input Capture enabled */ - TC45_HCCCMODE_BOTHCC_gc = (0x03<<4), /* Both Compare and Capture enabled */ -} TC45_HCCCMODE_t; - -/* Compare or Capture High Channel D Mode */ -typedef enum TC45_HCCDMODE_enum -{ - TC45_HCCDMODE_DISABLE_gc = (0x00<<6), /* Channel Disabled */ - TC45_HCCDMODE_COMP_gc = (0x01<<6), /* Ouput Compare enabled */ - TC45_HCCDMODE_CAPT_gc = (0x02<<6), /* Input Capture enabled */ - TC45_HCCDMODE_BOTHCC_gc = (0x03<<6), /* Both Compare and Capture enabled */ -} TC45_HCCDMODE_t; - -/* Timer Trigger Restart Interrupt Level */ -typedef enum TC45_TRGINTLVL_enum -{ - TC45_TRGINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ - TC45_TRGINTLVL_LO_gc = (0x01<<4), /* Low Level */ - TC45_TRGINTLVL_MED_gc = (0x02<<4), /* Medium Level */ - TC45_TRGINTLVL_HI_gc = (0x03<<4), /* High Level */ -} TC45_TRGINTLVL_t; - -/* Error Interrupt Level */ -typedef enum TC45_ERRINTLVL_enum -{ - TC45_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ - TC45_ERRINTLVL_LO_gc = (0x01<<2), /* Low Level */ - TC45_ERRINTLVL_MED_gc = (0x02<<2), /* Medium Level */ - TC45_ERRINTLVL_HI_gc = (0x03<<2), /* High Level */ -} TC45_ERRINTLVL_t; - -/* Overflow Interrupt Level */ -typedef enum TC45_OVFINTLVL_enum -{ - TC45_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - TC45_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ - TC45_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ - TC45_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ -} TC45_OVFINTLVL_t; - -/* Compare or Capture Channel A Interrupt Level */ -typedef enum TC45_CCAINTLVL_enum -{ - TC45_CCAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - TC45_CCAINTLVL_LO_gc = (0x01<<0), /* Low Level */ - TC45_CCAINTLVL_MED_gc = (0x02<<0), /* Medium Level */ - TC45_CCAINTLVL_HI_gc = (0x03<<0), /* High Level */ -} TC45_CCAINTLVL_t; - -/* Compare or Capture Channel B Interrupt Level */ -typedef enum TC45_CCBINTLVL_enum -{ - TC45_CCBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ - TC45_CCBINTLVL_LO_gc = (0x01<<2), /* Low Level */ - TC45_CCBINTLVL_MED_gc = (0x02<<2), /* Medium Level */ - TC45_CCBINTLVL_HI_gc = (0x03<<2), /* High Level */ -} TC45_CCBINTLVL_t; - -/* Compare or Capture Channel C Interrupt Level */ -typedef enum TC45_CCCINTLVL_enum -{ - TC45_CCCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ - TC45_CCCINTLVL_LO_gc = (0x01<<4), /* Low Level */ - TC45_CCCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ - TC45_CCCINTLVL_HI_gc = (0x03<<4), /* High Level */ -} TC45_CCCINTLVL_t; - -/* Compare or Capture Channel D Interrupt Level */ -typedef enum TC45_CCDINTLVL_enum -{ - TC45_CCDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ - TC45_CCDINTLVL_LO_gc = (0x01<<6), /* Low Level */ - TC45_CCDINTLVL_MED_gc = (0x02<<6), /* Medium Level */ - TC45_CCDINTLVL_HI_gc = (0x03<<6), /* High Level */ -} TC45_CCDINTLVL_t; - -/* Compare or Capture Low Channel A Interrupt Level */ -typedef enum TC45_LCCAINTLVL_enum -{ - TC45_LCCAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - TC45_LCCAINTLVL_LO_gc = (0x01<<0), /* Low Level */ - TC45_LCCAINTLVL_MED_gc = (0x02<<0), /* Medium Level */ - TC45_LCCAINTLVL_HI_gc = (0x03<<0), /* High Level */ -} TC45_LCCAINTLVL_t; - -/* Compare or Capture Low Channel B Interrupt Level */ -typedef enum TC45_LCCBINTLVL_enum -{ - TC45_LCCBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ - TC45_LCCBINTLVL_LO_gc = (0x01<<2), /* Low Level */ - TC45_LCCBINTLVL_MED_gc = (0x02<<2), /* Medium Level */ - TC45_LCCBINTLVL_HI_gc = (0x03<<2), /* High Level */ -} TC45_LCCBINTLVL_t; - -/* Compare or Capture Low Channel C Interrupt Level */ -typedef enum TC45_LCCCINTLVL_enum -{ - TC45_LCCCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ - TC45_LCCCINTLVL_LO_gc = (0x01<<4), /* Low Level */ - TC45_LCCCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ - TC45_LCCCINTLVL_HI_gc = (0x03<<4), /* High Level */ -} TC45_LCCCINTLVL_t; - -/* Compare or Capture Low Channel D Interrupt Level */ -typedef enum TC45_LCCDINTLVL_enum -{ - TC45_LCCDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ - TC45_LCCDINTLVL_LO_gc = (0x01<<6), /* Low Level */ - TC45_LCCDINTLVL_MED_gc = (0x02<<6), /* Medium Level */ - TC45_LCCDINTLVL_HI_gc = (0x03<<6), /* High Level */ -} TC45_LCCDINTLVL_t; - -/* Timer/Counter Command */ -typedef enum TC45_CMD_enum -{ - TC45_CMD_NONE_gc = (0x00<<2), /* No Command */ - TC45_CMD_UPDATE_gc = (0x01<<2), /* Force Update */ - TC45_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ - TC45_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ -} TC45_CMD_t; - - -/* --------------------------------------------------------------------------- -FAULT - Fault Extension --------------------------------------------------------------------------- -*/ - -/* Fault Extension */ -typedef struct FAULT_struct -{ - register8_t CTRLA; /* Control A Register */ - register8_t CTRLB; /* Control B Register */ - register8_t CTRLC; /* Control C Register */ - register8_t CTRLD; /* Control D Register */ - register8_t CTRLE; /* Control E Register */ - register8_t STATUS; /* Status Register */ - register8_t CTRLGCLR; /* Control Register G Clear */ - register8_t CTRLGSET; /* Control Register G set */ -} FAULT_t; - -/* Ramp Mode Selection */ -typedef enum FAULT_RAMP_enum -{ - FAULT_RAMP_RAMP1_gc = (0x00<<6), /* Normal Mode */ - FAULT_RAMP_RAMP2_gc = (0x02<<6), /* RAMP2 Mode */ -} FAULT_RAMP_t; - -/* Fault E Input Source Selection */ -typedef enum FAULT_SRCE_enum -{ - FAULT_SRCE_DISABLE_gc = (0x00<<0), /* Fault Protection Disabled */ - FAULT_SRCE_CHN_gc = (0x01<<0), /* Event Channel n */ - FAULT_SRCE_CHN1_gc = (0x02<<0), /* Event Channel n+1 */ - FAULT_SRCE_CHN2_gc = (0x03<<0), /* Event Channel n+2 */ -} FAULT_SRCE_t; - -/* Fault A Halt Action Selection */ -typedef enum FAULT_HALTA_enum -{ - FAULT_HALTA_DISABLE_gc = (0x00<<5), /* Halt Action Disabled */ - FAULT_HALTA_HW_gc = (0x01<<5), /* Hardware Halt Action */ - FAULT_HALTA_SW_gc = (0x02<<5), /* Software Halt Action */ -} FAULT_HALTA_t; - -/* Fault A Source Selection */ -typedef enum FAULT_SRCA_enum -{ - FAULT_SRCA_DISABLE_gc = (0x00<<0), /* Fault A Disabled */ - FAULT_SRCA_CHN_gc = (0x01<<0), /* Event Channel n */ - FAULT_SRCA_CHN1_gc = (0x02<<0), /* Event Channel n+1 */ - FAULT_SRCA_LINK_gc = (0x03<<0), /* Fault A linked to Fault B State from previous cycle */ -} FAULT_SRCA_t; - -/* Fault B Halt Action Selection */ -typedef enum FAULT_HALTB_enum -{ - FAULT_HALTB_DISABLE_gc = (0x00<<5), /* Halt Action Disabled */ - FAULT_HALTB_HW_gc = (0x01<<5), /* Hardware Halt Action */ - FAULT_HALTB_SW_gc = (0x02<<5), /* Software Halt Action */ -} FAULT_HALTB_t; - -/* Fault B Source Selection */ -typedef enum FAULT_SRCB_enum -{ - FAULT_SRCB_DISABLE_gc = (0x00<<0), /* Fault B disabled */ - FAULT_SRCB_CHN_gc = (0x01<<0), /* Event Channel n */ - FAULT_SRCB_CHN1_gc = (0x02<<0), /* Event Channel n+1 */ - FAULT_SRCB_LINK_gc = (0x03<<0), /* Fault B linked to Fault A State from previous cycle */ -} FAULT_SRCB_t; - -/* Channel index Command */ -typedef enum FAULT_IDXCMD_enum -{ - FAULT_IDXCMD_DISABLE_gc = (0x00<<3), /* Command Disabled */ - FAULT_IDXCMD_SET_gc = (0x01<<3), /* Force Cycle B in Next Cycle */ - FAULT_IDXCMD_CLEAR_gc = (0x02<<3), /* Force Cycle A in Next Cycle */ - FAULT_IDXCMD_HOLD_gc = (0x03<<3), /* Hold Current Cycle Index in Next Cycle */ -} FAULT_IDXCMD_t; - - -/* --------------------------------------------------------------------------- -WEX - Waveform Extension --------------------------------------------------------------------------- -*/ - -/* Waveform Extension */ -typedef struct WEX_struct -{ - register8_t CTRL; /* Control Register */ - register8_t DTBOTH; /* Dead-time Concurrent Write to Both Sides Register */ - register8_t DTLS; /* Dead-time Low Side Register */ - register8_t DTHS; /* Dead-time High Side Register */ - register8_t STATUSCLR; /* Status Clear Register */ - register8_t STATUSSET; /* Status Set Register */ - register8_t SWAP; /* Swap Register */ - register8_t PGO; /* Pattern Generation Override Register */ - register8_t PGV; /* Pattern Generation Value Register */ - register8_t reserved_0x09; - register8_t SWAPBUF; /* Dead Time Low Side Buffer */ - register8_t PGOBUF; /* Pattern Generation Overwrite Buffer Register */ - register8_t PGVBUF; /* Pattern Generation Value Buffer Register */ - register8_t reserved_0x0D; - register8_t reserved_0x0E; - register8_t OUTOVDIS; /* Output Override Disable Register */ -} WEX_t; - -/* Output Matrix Mode */ -typedef enum WEX_OTMX_enum -{ - WEX_OTMX_DEFAULT_gc = (0x00<<4), /* Default Ouput Matrix Mode */ - WEX_OTMX_FIRST_gc = (0x01<<4), /* First Output matrix Mode */ - WEX_OTMX_SECOND_gc = (0x02<<4), /* Second Output matrix Mode */ - WEX_OTMX_THIRD_gc = (0x03<<4), /* Third Output matrix Mode */ - WEX_OTMX_FOURTH_gc = (0x04<<4), /* Fourth Output matrix Mode */ -} WEX_OTMX_t; - - -/* --------------------------------------------------------------------------- -HIRES - High-Resolution Extension --------------------------------------------------------------------------- -*/ - -/* High-Resolution Extension */ -typedef struct HIRES_struct -{ - register8_t CTRLA; /* Control Register A */ -} HIRES_t; - -/* High Resolution Plus Mode */ -typedef enum HIRES_HRPLUS_enum -{ - HIRES_HRPLUS_NONE_gc = (0x00<<2), /* No Hi-Res Plus */ - HIRES_HRPLUS_HRP4_gc = (0x01<<2), /* Hi-Res Plus enabled on Timer 4 */ - HIRES_HRPLUS_HRP5_gc = (0x02<<2), /* Hi-Res Plus enabled on Timer 5 */ - HIRES_HRPLUS_BOTH_gc = (0x03<<2), /* Hi-Res Plus enabled on Timer 4 and 5 */ -} HIRES_HRPLUS_t; - -/* High Resolution Mode */ -typedef enum HIRES_HREN_enum -{ - HIRES_HREN_NONE_gc = (0x00<<0), /* No Hi-Res */ - HIRES_HREN_HRP4_gc = (0x01<<0), /* Hi-Res enabled on Timer 4 */ - HIRES_HREN_HRP5_gc = (0x02<<0), /* Hi-Res enabled on Timer 5 */ - HIRES_HREN_BOTH_gc = (0x03<<0), /* Hi-Res enabled on Timer 4 and 5 */ -} HIRES_HREN_t; - - -/* --------------------------------------------------------------------------- -USART - Universal Asynchronous Receiver-Transmitter --------------------------------------------------------------------------- -*/ - -/* Universal Synchronous/Asynchronous Receiver/Transmitter */ -typedef struct USART_struct -{ - register8_t DATA; /* Data Register */ - register8_t STATUS; /* Status Register */ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t CTRLC; /* Control Register C */ - register8_t CTRLD; /* Control Register D */ - register8_t BAUDCTRLA; /* Baud Rate Control Register A */ - register8_t BAUDCTRLB; /* Baud Rate Control Register B */ -} USART_t; - -/* Receive Start Interrupt level */ -typedef enum USART_RXSINTLVL_enum -{ - USART_RXSINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - USART_RXSINTLVL_LO_gc = (0x01<<0), /* Low Level */ - USART_RXSINTLVL_MED_gc = (0x02<<0), /* Medium Level */ - USART_RXSINTLVL_HI_gc = (0x03<<0), /* High Level */ -} USART_RXSINTLVL_t; - -/* Receive Complete Interrupt level */ -typedef enum USART_RXCINTLVL_enum -{ - USART_RXCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ - USART_RXCINTLVL_LO_gc = (0x01<<4), /* Low Level */ - USART_RXCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ - USART_RXCINTLVL_HI_gc = (0x03<<4), /* High Level */ -} USART_RXCINTLVL_t; - -/* Transmit Complete Interrupt level */ -typedef enum USART_TXCINTLVL_enum -{ - USART_TXCINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ - USART_TXCINTLVL_LO_gc = (0x01<<2), /* Low Level */ - USART_TXCINTLVL_MED_gc = (0x02<<2), /* Medium Level */ - USART_TXCINTLVL_HI_gc = (0x03<<2), /* High Level */ -} USART_TXCINTLVL_t; - -/* Data Register Empty Interrupt level */ -typedef enum USART_DREINTLVL_enum -{ - USART_DREINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - USART_DREINTLVL_LO_gc = (0x01<<0), /* Low Level */ - USART_DREINTLVL_MED_gc = (0x02<<0), /* Medium Level */ - USART_DREINTLVL_HI_gc = (0x03<<0), /* High Level */ -} USART_DREINTLVL_t; - -/* Character Size */ -typedef enum USART_CHSIZE_enum -{ - USART_CHSIZE_5BIT_gc = (0x00<<0), /* Character size: 5 bit */ - USART_CHSIZE_6BIT_gc = (0x01<<0), /* Character size: 6 bit */ - USART_CHSIZE_7BIT_gc = (0x02<<0), /* Character size: 7 bit */ - USART_CHSIZE_8BIT_gc = (0x03<<0), /* Character size: 8 bit */ - USART_CHSIZE_9BIT_gc = (0x07<<0), /* Character size: 9 bit */ -} USART_CHSIZE_t; - -/* Communication Mode */ -typedef enum USART_CMODE_enum -{ - USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6), /* Asynchronous Mode */ - USART_CMODE_SYNCHRONOUS_gc = (0x01<<6), /* Synchronous Mode */ - USART_CMODE_IRDA_gc = (0x02<<6), /* IrDA Mode */ - USART_CMODE_MSPI_gc = (0x03<<6), /* Master SPI Mode */ -} USART_CMODE_t; - -/* Parity Mode */ -typedef enum USART_PMODE_enum -{ - USART_PMODE_DISABLED_gc = (0x00<<4), /* No Parity */ - USART_PMODE_EVEN_gc = (0x02<<4), /* Even Parity */ - USART_PMODE_ODD_gc = (0x03<<4), /* Odd Parity */ -} USART_PMODE_t; - -/* Encoding and Decoding Type */ -typedef enum USART_DECTYPE_enum -{ - USART_DECTYPE_DATA_gc = (0x00<<4), /* DATA Field Encoding */ - USART_DECTYPE_SDATA_gc = (0x02<<4), /* Start and Data Fields Encoding */ - USART_DECTYPE_NOTSDATA_gc = (0x03<<4), /* Start and Data Fields Encoding, with invertion in START field */ -} USART_DECTYPE_t; - -/* XCL LUT Action */ -typedef enum USART_LUTACT_enum -{ - USART_LUTACT_OFF_gc = (0x00<<2), /* Standard Frame Configuration */ - USART_LUTACT_RX_gc = (0x01<<2), /* Receiver Decoding Enabled */ - USART_LUTACT_TX_gc = (0x02<<2), /* Transmitter Encoding Enabled */ - USART_LUTACT_BOTH_gc = (0x03<<2), /* Both Encoding and Decoding Enabled */ -} USART_LUTACT_t; - -/* XCL Peripheral Counter Action */ -typedef enum USART_PECACT_enum -{ - USART_PECACT_OFF_gc = (0x00<<0), /* Standard Mode */ - USART_PECACT_PEC0_gc = (0x01<<0), /* Variable Data Lenght in Reception */ - USART_PECACT_PEC1_gc = (0x02<<0), /* Variable Data Lenght in Transmission */ - USART_PECACT_PERC01_gc = (0x03<<0), /* Variable Data Lenght in both Reception and Transmission */ -} USART_PECACT_t; - - -/* --------------------------------------------------------------------------- -SPI - Serial Peripheral Interface --------------------------------------------------------------------------- -*/ - -/* Serial Peripheral Interface with Buffer Modes */ -typedef struct SPI_struct -{ - register8_t CTRL; /* Control Register */ - register8_t INTCTRL; /* Interrupt Control Register */ - register8_t STATUS; /* Status Register */ - register8_t DATA; /* Data Register */ - register8_t CTRLB; /* Control Register B */ -} SPI_t; - -/* SPI Mode */ -typedef enum SPI_MODE_enum -{ - SPI_MODE_0_gc = (0x00<<2), /* SPI Mode 0, base clock at "0", sampling on leading edge (rising) & set-up on trailling edge (falling). */ - SPI_MODE_1_gc = (0x01<<2), /* SPI Mode 1, base clock at "0", set-up on leading edge (rising) & sampling on trailling edge (falling). */ - SPI_MODE_2_gc = (0x02<<2), /* SPI Mode 2, base clock at "1", sampling on leading edge (falling) & set-up on trailling edge (rising). */ - SPI_MODE_3_gc = (0x03<<2), /* SPI Mode 3, base clock at "1", set-up on leading edge (falling) & sampling on trailling edge (rising). */ -} SPI_MODE_t; - -/* Prescaler setting */ -typedef enum SPI_PRESCALER_enum -{ - SPI_PRESCALER_DIV4_gc = (0x00<<0), /* If CLK2X=1 CLKper/2, else (CLK2X=0) CLKper/4. */ - SPI_PRESCALER_DIV16_gc = (0x01<<0), /* If CLK2X=1 CLKper/8, else (CLK2X=0) CLKper/16. */ - SPI_PRESCALER_DIV64_gc = (0x02<<0), /* If CLK2X=1 CLKper/32, else (CLK2X=0) CLKper/64. */ - SPI_PRESCALER_DIV128_gc = (0x03<<0), /* If CLK2X=1 CLKper/64, else (CLK2X=0) CLKper/128. */ -} SPI_PRESCALER_t; - -/* Interrupt level */ -typedef enum SPI_INTLVL_enum -{ - SPI_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - SPI_INTLVL_LO_gc = (0x01<<0), /* Low Level */ - SPI_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ - SPI_INTLVL_HI_gc = (0x03<<0), /* High Level */ -} SPI_INTLVL_t; - -/* Buffer Modes */ -typedef enum SPI_BUFMODE_enum -{ - SPI_BUFMODE_OFF_gc = (0x00<<6), /* SPI Unbuffered Mode */ - SPI_BUFMODE_BUFMODE1_gc = (0x02<<6), /* Buffer Mode 1 (with dummy byte) */ - SPI_BUFMODE_BUFMODE2_gc = (0x03<<6), /* Buffer Mode 2 (no dummy byte) */ -} SPI_BUFMODE_t; - - -/* --------------------------------------------------------------------------- -IRCOM - IR Communication Module --------------------------------------------------------------------------- -*/ - -/* IR Communication Module */ -typedef struct IRCOM_struct -{ - register8_t CTRL; /* Control Register */ - register8_t TXPLCTRL; /* IrDA Transmitter Pulse Length Control Register */ - register8_t RXPLCTRL; /* IrDA Receiver Pulse Length Control Register */ -} IRCOM_t; - -/* Event channel selection */ -typedef enum IRDA_EVSEL_enum -{ - IRDA_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ - IRDA_EVSEL_0_gc = (0x08<<0), /* Event Channel 0 */ - IRDA_EVSEL_1_gc = (0x09<<0), /* Event Channel 1 */ - IRDA_EVSEL_2_gc = (0x0A<<0), /* Event Channel 2 */ - IRDA_EVSEL_3_gc = (0x0B<<0), /* Event Channel 3 */ - IRDA_EVSEL_4_gc = (0x0C<<0), /* Event Channel 4 */ - IRDA_EVSEL_5_gc = (0x0D<<0), /* Event Channel 5 */ - IRDA_EVSEL_6_gc = (0x0E<<0), /* Event Channel 6 */ - IRDA_EVSEL_7_gc = (0x0F<<0), /* Event Channel 7 */ -} IRDA_EVSEL_t; - - -/* --------------------------------------------------------------------------- -FUSE - Fuses and Lockbits --------------------------------------------------------------------------- -*/ - -/* Lock Bits */ -typedef struct NVM_LOCKBITS_struct -{ - register8_t LOCK_BITS; /* Lock Bits (Changed from LOCKBITS to avoid avr-libc collision) */ -} NVM_LOCKBITS_t; - - -/* Fuses */ -typedef struct NVM_FUSES_struct -{ - register8_t reserved_0x00; - register8_t FUSEBYTE1; /* Watchdog Configuration */ - register8_t FUSEBYTE2; /* Reset Configuration */ - register8_t reserved_0x03; - register8_t FUSEBYTE4; /* Start-up Configuration */ - register8_t FUSEBYTE5; /* EESAVE and BOD Level */ - register8_t FUSEBYTE6; /* Fault State */ -} NVM_FUSES_t; - -/* Boot lock bits - boot setcion */ -typedef enum FUSE_BLBB_enum -{ - FUSE_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ - FUSE_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ - FUSE_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ - FUSE_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ -} FUSE_BLBB_t; - -/* Boot lock bits - application section */ -typedef enum FUSE_BLBA_enum -{ - FUSE_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ - FUSE_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ - FUSE_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ - FUSE_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ -} FUSE_BLBA_t; - -/* Boot lock bits - application table section */ -typedef enum FUSE_BLBAT_enum -{ - FUSE_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ - FUSE_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ - FUSE_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ - FUSE_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ -} FUSE_BLBAT_t; - -/* Lock bits */ -typedef enum FUSE_LB_enum -{ - FUSE_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ - FUSE_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ - FUSE_LB_NOLOCK_gc = (0x03<<0), /* No locks */ -} FUSE_LB_t; - -/* Boot Loader Section Reset Vector */ -typedef enum BOOTRST_enum -{ - BOOTRST_BOOTLDR_gc = (0x00<<6), /* Boot Loader Reset */ - BOOTRST_APPLICATION_gc = (0x01<<6), /* Application Reset */ -} BOOTRST_t; - -/* BOD operation */ -typedef enum BOD_enum -{ - BOD_SAMPLED_gc = (0x01<<4), /* BOD enabled in sampled mode */ - BOD_CONTINUOUS_gc = (0x02<<4), /* BOD enabled continuously */ - BOD_DISABLED_gc = (0x03<<4), /* BOD Disabled */ -} BOD_t; - -/* Watchdog (Window) Timeout Period */ -typedef enum WD_enum -{ - WD_8CLK_gc = (0x00<<4), /* 8 cycles (8ms @ 3.3V) */ - WD_16CLK_gc = (0x01<<4), /* 16 cycles (16ms @ 3.3V) */ - WD_32CLK_gc = (0x02<<4), /* 32 cycles (32ms @ 3.3V) */ - WD_64CLK_gc = (0x03<<4), /* 64 cycles (64ms @ 3.3V) */ - WD_128CLK_gc = (0x04<<4), /* 128 cycles (0.125s @ 3.3V) */ - WD_256CLK_gc = (0x05<<4), /* 256 cycles (0.25s @ 3.3V) */ - WD_512CLK_gc = (0x06<<4), /* 512 cycles (0.5s @ 3.3V) */ - WD_1KCLK_gc = (0x07<<4), /* 1K cycles (1s @ 3.3V) */ - WD_2KCLK_gc = (0x08<<4), /* 2K cycles (2s @ 3.3V) */ - WD_4KCLK_gc = (0x09<<4), /* 4K cycles (4s @ 3.3V) */ - WD_8KCLK_gc = (0x0A<<4), /* 8K cycles (8s @ 3.3V) */ -} WD_t; - -/* Start-up Time */ -typedef enum SUT_enum -{ - SUT_0MS_gc = (0x03<<2), /* 0 ms */ - SUT_4MS_gc = (0x01<<2), /* 4 ms */ - SUT_64MS_gc = (0x00<<2), /* 64 ms */ -} SUT_t; - -/* Brownout Detection Voltage Level */ -typedef enum BODLVL_enum -{ - BODLVL_1V6_gc = (0x07<<0), /* 1.6 V */ - BODLVL_1V8_gc = (0x06<<0), /* 1.8 V */ - BODLVL_2V0_gc = (0x05<<0), /* 2.0 V */ - BODLVL_2V2_gc = (0x04<<0), /* 2.2 V */ - BODLVL_2V4_gc = (0x03<<0), /* 2.4 V */ - BODLVL_2V6_gc = (0x02<<0), /* 2.6 V */ - BODLVL_2V8_gc = (0x01<<0), /* 2.8 V */ - BODLVL_3V0_gc = (0x00<<0), /* 3.0 V */ -} BODLVL_t; - - -/* --------------------------------------------------------------------------- -SIGROW - Signature Row --------------------------------------------------------------------------- -*/ - -/* Production Signatures */ -typedef struct NVM_PROD_SIGNATURES_struct -{ - register8_t RCOSC8M; /* RCOSC 8MHz Calibration Value */ - register8_t reserved_0x01; - register8_t RCOSC32K; /* RCOSC 32.768 kHz Calibration Value */ - register8_t RCOSC32M; /* RCOSC 32 MHz Calibration Value B */ - register8_t RCOSC32MA; /* RCOSC 32 MHz Calibration Value A */ - register8_t reserved_0x05; - register8_t reserved_0x06; - register8_t reserved_0x07; - register8_t LOTNUM0; /* Lot Number Byte 0, ASCII */ - register8_t LOTNUM1; /* Lot Number Byte 1, ASCII */ - register8_t LOTNUM2; /* Lot Number Byte 2, ASCII */ - register8_t LOTNUM3; /* Lot Number Byte 3, ASCII */ - register8_t LOTNUM4; /* Lot Number Byte 4, ASCII */ - register8_t LOTNUM5; /* Lot Number Byte 5, ASCII */ - register8_t reserved_0x0E; - register8_t reserved_0x0F; - register8_t WAFNUM; /* Wafer Number */ - register8_t reserved_0x11; - register8_t COORDX0; /* Wafer Coordinate X Byte 0 */ - register8_t COORDX1; /* Wafer Coordinate X Byte 1 */ - register8_t COORDY0; /* Wafer Coordinate Y Byte 0 */ - register8_t COORDY1; /* Wafer Coordinate Y Byte 1 */ - register8_t reserved_0x16; - register8_t reserved_0x17; - register8_t reserved_0x18; - register8_t reserved_0x19; - register8_t reserved_0x1A; - register8_t reserved_0x1B; - register8_t reserved_0x1C; - register8_t reserved_0x1D; - register8_t ROOMTEMP; /* Temperature corresponds to TEMPSENSE3/2 */ - register8_t HOTTEMP; /* Temperature corresponds to TEMPSENSE1/0 */ - register8_t ADCACAL0; /* ADCA Calibration Byte 0 */ - register8_t ADCACAL1; /* ADCA Calibration Byte 1 */ - register8_t reserved_0x22; - register8_t reserved_0x23; - register8_t reserved_0x24; - register8_t reserved_0x25; - register8_t reserved_0x26; - register8_t reserved_0x27; - register8_t ACACURRCAL; /* ACA Current Calibration Byte */ - register8_t reserved_0x29; - register8_t reserved_0x2A; - register8_t reserved_0x2B; - register8_t TEMPSENSE2; /* Temperature Sensor Calibration Byte 2 */ - register8_t TEMPSENSE3; /* Temperature Sensor Calibration Byte 3 */ - register8_t TEMPSENSE0; /* Temperature Sensor Calibration Byte 0 */ - register8_t TEMPSENSE1; /* Temperature Sensor Calibration Byte 1 */ - register8_t DACA0OFFCAL; /* DACA0 Calibration Byte 0 */ - register8_t DACA0GAINCAL; /* DACA0 Calibration Byte 1 */ - register8_t reserved_0x32; - register8_t reserved_0x33; - register8_t DACA1OFFCAL; /* DACA1 Calibration Byte 0 */ - register8_t DACA1GAINCAL; /* DACA1 Calibration Byte 1 */ - register8_t reserved_0x36; - register8_t reserved_0x37; - register8_t reserved_0x38; - register8_t reserved_0x39; - register8_t reserved_0x3A; - register8_t reserved_0x3B; - register8_t reserved_0x3C; - register8_t reserved_0x3D; - register8_t reserved_0x3E; - register8_t reserved_0x3F; -} NVM_PROD_SIGNATURES_t; - -/* -========================================================================== -IO Module Instances. Mapped to memory. -========================================================================== -*/ - -#define VPORT0 (*(VPORT_t *) 0x0010) /* Virtual Port */ -#define VPORT1 (*(VPORT_t *) 0x0014) /* Virtual Port */ -#define VPORT2 (*(VPORT_t *) 0x0018) /* Virtual Port */ -#define VPORT3 (*(VPORT_t *) 0x001C) /* Virtual Port */ -#define OCD (*(OCD_t *) 0x002E) /* On-Chip Debug System */ -#define CLK (*(CLK_t *) 0x0040) /* Clock System */ -#define SLEEP (*(SLEEP_t *) 0x0048) /* Sleep Controller */ -#define OSC (*(OSC_t *) 0x0050) /* Oscillator */ -#define DFLLRC32M (*(DFLL_t *) 0x0060) /* DFLL */ -#define PR (*(PR_t *) 0x0070) /* Power Reduction */ -#define RST (*(RST_t *) 0x0078) /* Reset */ -#define WDT (*(WDT_t *) 0x0080) /* Watch-Dog Timer */ -#define MCU (*(MCU_t *) 0x0090) /* MCU Control */ -#define PMIC (*(PMIC_t *) 0x00A0) /* Programmable Multi-level Interrupt Controller */ -#define PORTCFG (*(PORTCFG_t *) 0x00B0) /* I/O port Configuration */ -#define CRC (*(CRC_t *) 0x00D0) /* Cyclic Redundancy Checker */ -#define EDMA (*(EDMA_t *) 0x0100) /* Enhanced DMA Controller */ -#define EVSYS (*(EVSYS_t *) 0x0180) /* Event System */ -#define NVM (*(NVM_t *) 0x01C0) /* Non-volatile Memory Controller */ -#define ADCA (*(ADC_t *) 0x0200) /* Analog-to-Digital Converter */ -#define DACA (*(DAC_t *) 0x0300) /* Digital-to-Analog Converter */ -#define ACA (*(AC_t *) 0x0380) /* Analog Comparator */ -#define RTC (*(RTC_t *) 0x0400) /* Real-Time Counter */ -#define XCL (*(XCL_t *) 0x0460) /* XMEGA Custom Logic */ -#define TWIC (*(TWI_t *) 0x0480) /* Two-Wire Interface */ -#define PORTA (*(PORT_t *) 0x0600) /* I/O Ports */ -#define PORTC (*(PORT_t *) 0x0640) /* I/O Ports */ -#define PORTD (*(PORT_t *) 0x0660) /* I/O Ports */ -#define PORTR (*(PORT_t *) 0x07E0) /* I/O Ports */ -#define TCC4 (*(TC4_t *) 0x0800) /* 16-bit Timer/Counter 4 */ -#define TCC5 (*(TC5_t *) 0x0840) /* 16-bit Timer/Counter 5 */ -#define FAULTC4 (*(FAULT_t *) 0x0880) /* Fault Extension */ -#define FAULTC5 (*(FAULT_t *) 0x0890) /* Fault Extension */ -#define WEXC (*(WEX_t *) 0x08A0) /* Waveform Extension */ -#define HIRESC (*(HIRES_t *) 0x08B0) /* High-Resolution Extension */ -#define USARTC0 (*(USART_t *) 0x08C0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ -#define SPIC (*(SPI_t *) 0x08E0) /* Serial Peripheral Interface with Buffer Modes */ -#define IRCOM (*(IRCOM_t *) 0x08F8) /* IR Communication Module */ -#define TCD5 (*(TC5_t *) 0x0940) /* 16-bit Timer/Counter 5 */ -#define USARTD0 (*(USART_t *) 0x09C0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ - - -#endif /* !defined (__ASSEMBLER__) */ - - -/* ========== Flattened fully qualified IO register names ========== */ - -/* GPIO - General Purpose IO Registers */ -#define GPIO_GPIOR0 _SFR_MEM8(0x0000) -#define GPIO_GPIOR1 _SFR_MEM8(0x0001) -#define GPIO_GPIOR2 _SFR_MEM8(0x0002) -#define GPIO_GPIOR3 _SFR_MEM8(0x0003) - -/* Deprecated */ -#define GPIO_GPIO0 _SFR_MEM8(0x0000) -#define GPIO_GPIO1 _SFR_MEM8(0x0001) -#define GPIO_GPIO2 _SFR_MEM8(0x0002) -#define GPIO_GPIO3 _SFR_MEM8(0x0003) - -/* NVM_FUSES - Fuses */ -#define FUSE_FUSEBYTE1 _SFR_MEM8(0x0001) -#define FUSE_FUSEBYTE2 _SFR_MEM8(0x0002) -#define FUSE_FUSEBYTE4 _SFR_MEM8(0x0004) -#define FUSE_FUSEBYTE5 _SFR_MEM8(0x0005) -#define FUSE_FUSEBYTE6 _SFR_MEM8(0x0006) - -/* NVM_LOCKBITS - Lock Bits */ -#define LOCKBIT_LOCKBITS _SFR_MEM8(0x0000) - -/* NVM_PROD_SIGNATURES - Production Signatures */ -#define PRODSIGNATURES_RCOSC8M _SFR_MEM8(0x0000) -#define PRODSIGNATURES_RCOSC32K _SFR_MEM8(0x0002) -#define PRODSIGNATURES_RCOSC32M _SFR_MEM8(0x0003) -#define PRODSIGNATURES_RCOSC32MA _SFR_MEM8(0x0004) -#define PRODSIGNATURES_LOTNUM0 _SFR_MEM8(0x0008) -#define PRODSIGNATURES_LOTNUM1 _SFR_MEM8(0x0009) -#define PRODSIGNATURES_LOTNUM2 _SFR_MEM8(0x000A) -#define PRODSIGNATURES_LOTNUM3 _SFR_MEM8(0x000B) -#define PRODSIGNATURES_LOTNUM4 _SFR_MEM8(0x000C) -#define PRODSIGNATURES_LOTNUM5 _SFR_MEM8(0x000D) -#define PRODSIGNATURES_WAFNUM _SFR_MEM8(0x0010) -#define PRODSIGNATURES_COORDX0 _SFR_MEM8(0x0012) -#define PRODSIGNATURES_COORDX1 _SFR_MEM8(0x0013) -#define PRODSIGNATURES_COORDY0 _SFR_MEM8(0x0014) -#define PRODSIGNATURES_COORDY1 _SFR_MEM8(0x0015) -#define PRODSIGNATURES_ROOMTEMP _SFR_MEM8(0x001E) -#define PRODSIGNATURES_HOTTEMP _SFR_MEM8(0x001F) -#define PRODSIGNATURES_ADCACAL0 _SFR_MEM8(0x0020) -#define PRODSIGNATURES_ADCACAL1 _SFR_MEM8(0x0021) -#define PRODSIGNATURES_ACACURRCAL _SFR_MEM8(0x0028) -#define PRODSIGNATURES_TEMPSENSE2 _SFR_MEM8(0x002C) -#define PRODSIGNATURES_TEMPSENSE3 _SFR_MEM8(0x002D) -#define PRODSIGNATURES_TEMPSENSE0 _SFR_MEM8(0x002E) -#define PRODSIGNATURES_TEMPSENSE1 _SFR_MEM8(0x002F) -#define PRODSIGNATURES_DACA0OFFCAL _SFR_MEM8(0x0030) -#define PRODSIGNATURES_DACA0GAINCAL _SFR_MEM8(0x0031) -#define PRODSIGNATURES_DACA1OFFCAL _SFR_MEM8(0x0034) -#define PRODSIGNATURES_DACA1GAINCAL _SFR_MEM8(0x0035) - -/* VPORT - Virtual Port */ -#define VPORT0_DIR _SFR_MEM8(0x0010) -#define VPORT0_OUT _SFR_MEM8(0x0011) -#define VPORT0_IN _SFR_MEM8(0x0012) -#define VPORT0_INTFLAGS _SFR_MEM8(0x0013) - -/* VPORT - Virtual Port */ -#define VPORT1_DIR _SFR_MEM8(0x0014) -#define VPORT1_OUT _SFR_MEM8(0x0015) -#define VPORT1_IN _SFR_MEM8(0x0016) -#define VPORT1_INTFLAGS _SFR_MEM8(0x0017) - -/* VPORT - Virtual Port */ -#define VPORT2_DIR _SFR_MEM8(0x0018) -#define VPORT2_OUT _SFR_MEM8(0x0019) -#define VPORT2_IN _SFR_MEM8(0x001A) -#define VPORT2_INTFLAGS _SFR_MEM8(0x001B) - -/* VPORT - Virtual Port */ -#define VPORT3_DIR _SFR_MEM8(0x001C) -#define VPORT3_OUT _SFR_MEM8(0x001D) -#define VPORT3_IN _SFR_MEM8(0x001E) -#define VPORT3_INTFLAGS _SFR_MEM8(0x001F) - -/* OCD - On-Chip Debug System */ -#define OCD_OCDR0 _SFR_MEM8(0x002E) -#define OCD_OCDR1 _SFR_MEM8(0x002F) - -/* CPU - CPU registers */ -#define CPU_CCP _SFR_MEM8(0x0034) -#define CPU_RAMPD _SFR_MEM8(0x0038) -#define CPU_RAMPX _SFR_MEM8(0x0039) -#define CPU_RAMPY _SFR_MEM8(0x003A) -#define CPU_RAMPZ _SFR_MEM8(0x003B) -#define CPU_EIND _SFR_MEM8(0x003C) -#define CPU_SPL _SFR_MEM8(0x003D) -#define CPU_SPH _SFR_MEM8(0x003E) -#define CPU_SREG _SFR_MEM8(0x003F) - -/* CLK - Clock System */ -#define CLK_CTRL _SFR_MEM8(0x0040) -#define CLK_PSCTRL _SFR_MEM8(0x0041) -#define CLK_LOCK _SFR_MEM8(0x0042) -#define CLK_RTCCTRL _SFR_MEM8(0x0043) - -/* SLEEP - Sleep Controller */ -#define SLEEP_CTRL _SFR_MEM8(0x0048) - -/* OSC - Oscillator */ -#define OSC_CTRL _SFR_MEM8(0x0050) -#define OSC_STATUS _SFR_MEM8(0x0051) -#define OSC_XOSCCTRL _SFR_MEM8(0x0052) -#define OSC_XOSCFAIL _SFR_MEM8(0x0053) -#define OSC_RC32KCAL _SFR_MEM8(0x0054) -#define OSC_PLLCTRL _SFR_MEM8(0x0055) -#define OSC_DFLLCTRL _SFR_MEM8(0x0056) -#define OSC_RC8MCAL _SFR_MEM8(0x0057) - -/* DFLL - DFLL */ -#define DFLLRC32M_CTRL _SFR_MEM8(0x0060) -#define DFLLRC32M_CALA _SFR_MEM8(0x0062) -#define DFLLRC32M_CALB _SFR_MEM8(0x0063) -#define DFLLRC32M_COMP0 _SFR_MEM8(0x0064) -#define DFLLRC32M_COMP1 _SFR_MEM8(0x0065) -#define DFLLRC32M_COMP2 _SFR_MEM8(0x0066) - -/* PR - Power Reduction */ -#define PR_PRGEN _SFR_MEM8(0x0070) -#define PR_PRPA _SFR_MEM8(0x0071) -#define PR_PRPC _SFR_MEM8(0x0073) -#define PR_PRPD _SFR_MEM8(0x0074) - -/* RST - Reset */ -#define RST_STATUS _SFR_MEM8(0x0078) -#define RST_CTRL _SFR_MEM8(0x0079) - -/* WDT - Watch-Dog Timer */ -#define WDT_CTRL _SFR_MEM8(0x0080) -#define WDT_WINCTRL _SFR_MEM8(0x0081) -#define WDT_STATUS _SFR_MEM8(0x0082) - -/* MCU - MCU Control */ -#define MCU_DEVID0 _SFR_MEM8(0x0090) -#define MCU_DEVID1 _SFR_MEM8(0x0091) -#define MCU_DEVID2 _SFR_MEM8(0x0092) -#define MCU_REVID _SFR_MEM8(0x0093) -#define MCU_ANAINIT _SFR_MEM8(0x0097) -#define MCU_EVSYSLOCK _SFR_MEM8(0x0098) -#define MCU_WEXLOCK _SFR_MEM8(0x0099) -#define MCU_FAULTLOCK _SFR_MEM8(0x009A) - -/* PMIC - Programmable Multi-level Interrupt Controller */ -#define PMIC_STATUS _SFR_MEM8(0x00A0) -#define PMIC_INTPRI _SFR_MEM8(0x00A1) -#define PMIC_CTRL _SFR_MEM8(0x00A2) - -/* PORTCFG - I/O port Configuration */ -#define PORTCFG_MPCMASK _SFR_MEM8(0x00B0) -#define PORTCFG_CLKOUT _SFR_MEM8(0x00B4) -#define PORTCFG_ACEVOUT _SFR_MEM8(0x00B6) -#define PORTCFG_SRLCTRL _SFR_MEM8(0x00B7) - -/* CRC - Cyclic Redundancy Checker */ -#define CRC_CTRL _SFR_MEM8(0x00D0) -#define CRC_STATUS _SFR_MEM8(0x00D1) -#define CRC_DATAIN _SFR_MEM8(0x00D3) -#define CRC_CHECKSUM0 _SFR_MEM8(0x00D4) -#define CRC_CHECKSUM1 _SFR_MEM8(0x00D5) -#define CRC_CHECKSUM2 _SFR_MEM8(0x00D6) -#define CRC_CHECKSUM3 _SFR_MEM8(0x00D7) - -/* EDMA - Enhanced DMA Controller */ -#define EDMA_CTRL _SFR_MEM8(0x0100) -#define EDMA_INTFLAGS _SFR_MEM8(0x0103) -#define EDMA_STATUS _SFR_MEM8(0x0104) -#define EDMA_TEMP _SFR_MEM8(0x0106) -#define EDMA_CH0_CTRLA _SFR_MEM8(0x0110) -#define EDMA_CH0_CTRLB _SFR_MEM8(0x0111) -#define EDMA_CH0_ADDRCTRL _SFR_MEM8(0x0112) -#define EDMA_CH0_DESTADDRCTRL _SFR_MEM8(0x0113) -#define EDMA_CH0_TRIGSRC _SFR_MEM8(0x0114) -#define EDMA_CH0_TRFCNT _SFR_MEM16(0x0116) -#define EDMA_CH0_ADDR _SFR_MEM16(0x0118) -#define EDMA_CH0_DESTADDR _SFR_MEM16(0x011C) -#define EDMA_CH1_CTRLA _SFR_MEM8(0x0120) -#define EDMA_CH1_CTRLB _SFR_MEM8(0x0121) -#define EDMA_CH1_ADDRCTRL _SFR_MEM8(0x0122) -#define EDMA_CH1_DESTADDRCTRL _SFR_MEM8(0x0123) -#define EDMA_CH1_TRIGSRC _SFR_MEM8(0x0124) -#define EDMA_CH1_TRFCNT _SFR_MEM16(0x0126) -#define EDMA_CH1_ADDR _SFR_MEM16(0x0128) -#define EDMA_CH1_DESTADDR _SFR_MEM16(0x012C) -#define EDMA_CH2_CTRLA _SFR_MEM8(0x0130) -#define EDMA_CH2_CTRLB _SFR_MEM8(0x0131) -#define EDMA_CH2_ADDRCTRL _SFR_MEM8(0x0132) -#define EDMA_CH2_DESTADDRCTRL _SFR_MEM8(0x0133) -#define EDMA_CH2_TRIGSRC _SFR_MEM8(0x0134) -#define EDMA_CH2_TRFCNT _SFR_MEM16(0x0136) -#define EDMA_CH2_ADDR _SFR_MEM16(0x0138) -#define EDMA_CH2_DESTADDR _SFR_MEM16(0x013C) -#define EDMA_CH3_CTRLA _SFR_MEM8(0x0140) -#define EDMA_CH3_CTRLB _SFR_MEM8(0x0141) -#define EDMA_CH3_ADDRCTRL _SFR_MEM8(0x0142) -#define EDMA_CH3_DESTADDRCTRL _SFR_MEM8(0x0143) -#define EDMA_CH3_TRIGSRC _SFR_MEM8(0x0144) -#define EDMA_CH3_TRFCNT _SFR_MEM16(0x0146) -#define EDMA_CH3_ADDR _SFR_MEM16(0x0148) -#define EDMA_CH3_DESTADDR _SFR_MEM16(0x014C) - -/* EVSYS - Event System */ -#define EVSYS_CH0MUX _SFR_MEM8(0x0180) -#define EVSYS_CH1MUX _SFR_MEM8(0x0181) -#define EVSYS_CH2MUX _SFR_MEM8(0x0182) -#define EVSYS_CH3MUX _SFR_MEM8(0x0183) -#define EVSYS_CH4MUX _SFR_MEM8(0x0184) -#define EVSYS_CH5MUX _SFR_MEM8(0x0185) -#define EVSYS_CH6MUX _SFR_MEM8(0x0186) -#define EVSYS_CH7MUX _SFR_MEM8(0x0187) -#define EVSYS_CH0CTRL _SFR_MEM8(0x0188) -#define EVSYS_CH1CTRL _SFR_MEM8(0x0189) -#define EVSYS_CH2CTRL _SFR_MEM8(0x018A) -#define EVSYS_CH3CTRL _SFR_MEM8(0x018B) -#define EVSYS_CH4CTRL _SFR_MEM8(0x018C) -#define EVSYS_CH5CTRL _SFR_MEM8(0x018D) -#define EVSYS_CH6CTRL _SFR_MEM8(0x018E) -#define EVSYS_CH7CTRL _SFR_MEM8(0x018F) -#define EVSYS_STROBE _SFR_MEM8(0x0190) -#define EVSYS_DATA _SFR_MEM8(0x0191) -#define EVSYS_DFCTRL _SFR_MEM8(0x0192) - -/* NVM - Non-volatile Memory Controller */ -#define NVM_ADDR0 _SFR_MEM8(0x01C0) -#define NVM_ADDR1 _SFR_MEM8(0x01C1) -#define NVM_ADDR2 _SFR_MEM8(0x01C2) -#define NVM_DATA0 _SFR_MEM8(0x01C4) -#define NVM_DATA1 _SFR_MEM8(0x01C5) -#define NVM_DATA2 _SFR_MEM8(0x01C6) -#define NVM_CMD _SFR_MEM8(0x01CA) -#define NVM_CTRLA _SFR_MEM8(0x01CB) -#define NVM_CTRLB _SFR_MEM8(0x01CC) -#define NVM_INTCTRL _SFR_MEM8(0x01CD) -#define NVM_STATUS _SFR_MEM8(0x01CF) -#define NVM_LOCKBITS _SFR_MEM8(0x01D0) - -/* ADC - Analog-to-Digital Converter */ -#define ADCA_CTRLA _SFR_MEM8(0x0200) -#define ADCA_CTRLB _SFR_MEM8(0x0201) -#define ADCA_REFCTRL _SFR_MEM8(0x0202) -#define ADCA_EVCTRL _SFR_MEM8(0x0203) -#define ADCA_PRESCALER _SFR_MEM8(0x0204) -#define ADCA_INTFLAGS _SFR_MEM8(0x0206) -#define ADCA_TEMP _SFR_MEM8(0x0207) -#define ADCA_SAMPCTRL _SFR_MEM8(0x0208) -#define ADCA_CAL _SFR_MEM16(0x020C) -#define ADCA_CH0RES _SFR_MEM16(0x0210) -#define ADCA_CMP _SFR_MEM16(0x0218) -#define ADCA_CH0_CTRL _SFR_MEM8(0x0220) -#define ADCA_CH0_MUXCTRL _SFR_MEM8(0x0221) -#define ADCA_CH0_INTCTRL _SFR_MEM8(0x0222) -#define ADCA_CH0_INTFLAGS _SFR_MEM8(0x0223) -#define ADCA_CH0_RES _SFR_MEM16(0x0224) -#define ADCA_CH0_SCAN _SFR_MEM8(0x0226) -#define ADCA_CH0_CORRCTRL _SFR_MEM8(0x0227) -#define ADCA_CH0_OFFSETCORR0 _SFR_MEM8(0x0228) -#define ADCA_CH0_OFFSETCORR1 _SFR_MEM8(0x0229) -#define ADCA_CH0_GAINCORR0 _SFR_MEM8(0x022A) -#define ADCA_CH0_GAINCORR1 _SFR_MEM8(0x022B) -#define ADCA_CH0_AVGCTRL _SFR_MEM8(0x022C) - -/* DAC - Digital-to-Analog Converter */ -#define DACA_CTRLA _SFR_MEM8(0x0300) -#define DACA_CTRLB _SFR_MEM8(0x0301) -#define DACA_CTRLC _SFR_MEM8(0x0302) -#define DACA_EVCTRL _SFR_MEM8(0x0303) -#define DACA_STATUS _SFR_MEM8(0x0305) -#define DACA_CH0GAINCAL _SFR_MEM8(0x0308) -#define DACA_CH0OFFSETCAL _SFR_MEM8(0x0309) -#define DACA_CH1GAINCAL _SFR_MEM8(0x030A) -#define DACA_CH1OFFSETCAL _SFR_MEM8(0x030B) -#define DACA_CH0DATA _SFR_MEM16(0x0318) -#define DACA_CH1DATA _SFR_MEM16(0x031A) - -/* AC - Analog Comparator */ -#define ACA_AC0CTRL _SFR_MEM8(0x0380) -#define ACA_AC1CTRL _SFR_MEM8(0x0381) -#define ACA_AC0MUXCTRL _SFR_MEM8(0x0382) -#define ACA_AC1MUXCTRL _SFR_MEM8(0x0383) -#define ACA_CTRLA _SFR_MEM8(0x0384) -#define ACA_CTRLB _SFR_MEM8(0x0385) -#define ACA_WINCTRL _SFR_MEM8(0x0386) -#define ACA_STATUS _SFR_MEM8(0x0387) -#define ACA_CURRCTRL _SFR_MEM8(0x0388) -#define ACA_CURRCALIB _SFR_MEM8(0x0389) - -/* RTC - Real-Time Counter */ -#define RTC_CTRL _SFR_MEM8(0x0400) -#define RTC_STATUS _SFR_MEM8(0x0401) -#define RTC_INTCTRL _SFR_MEM8(0x0402) -#define RTC_INTFLAGS _SFR_MEM8(0x0403) -#define RTC_TEMP _SFR_MEM8(0x0404) -#define RTC_CALIB _SFR_MEM8(0x0406) -#define RTC_CNT _SFR_MEM16(0x0408) -#define RTC_PER _SFR_MEM16(0x040A) -#define RTC_COMP _SFR_MEM16(0x040C) - -/* XCL - XMEGA Custom Logic */ -#define XCL_CTRLA _SFR_MEM8(0x0460) -#define XCL_CTRLB _SFR_MEM8(0x0461) -#define XCL_CTRLC _SFR_MEM8(0x0462) -#define XCL_CTRLD _SFR_MEM8(0x0463) -#define XCL_CTRLE _SFR_MEM8(0x0464) -#define XCL_CTRLF _SFR_MEM8(0x0465) -#define XCL_CTRLG _SFR_MEM8(0x0466) -#define XCL_INTCTRL _SFR_MEM8(0x0467) -#define XCL_INTFLAGS _SFR_MEM8(0x0468) -#define XCL_PLC _SFR_MEM8(0x0469) -#define XCL_CNTL _SFR_MEM8(0x046A) -#define XCL_CNTH _SFR_MEM8(0x046B) -#define XCL_CMPL _SFR_MEM8(0x046C) -#define XCL_CMPH _SFR_MEM8(0x046D) -#define XCL_PERCAPTL _SFR_MEM8(0x046E) -#define XCL_PERCAPTH _SFR_MEM8(0x046F) - -/* TWI - Two-Wire Interface */ -#define TWIC_CTRL _SFR_MEM8(0x0480) -#define TWIC_MASTER_CTRLA _SFR_MEM8(0x0481) -#define TWIC_MASTER_CTRLB _SFR_MEM8(0x0482) -#define TWIC_MASTER_CTRLC _SFR_MEM8(0x0483) -#define TWIC_MASTER_STATUS _SFR_MEM8(0x0484) -#define TWIC_MASTER_BAUD _SFR_MEM8(0x0485) -#define TWIC_MASTER_ADDR _SFR_MEM8(0x0486) -#define TWIC_MASTER_DATA _SFR_MEM8(0x0487) -#define TWIC_SLAVE_CTRLA _SFR_MEM8(0x0488) -#define TWIC_SLAVE_CTRLB _SFR_MEM8(0x0489) -#define TWIC_SLAVE_STATUS _SFR_MEM8(0x048A) -#define TWIC_SLAVE_ADDR _SFR_MEM8(0x048B) -#define TWIC_SLAVE_DATA _SFR_MEM8(0x048C) -#define TWIC_SLAVE_ADDRMASK _SFR_MEM8(0x048D) -#define TWIC_TIMEOUT_TOS _SFR_MEM8(0x048E) -#define TWIC_TIMEOUT_TOCONF _SFR_MEM8(0x048F) - -/* PORT - I/O Ports */ -#define PORTA_DIR _SFR_MEM8(0x0600) -#define PORTA_DIRSET _SFR_MEM8(0x0601) -#define PORTA_DIRCLR _SFR_MEM8(0x0602) -#define PORTA_DIRTGL _SFR_MEM8(0x0603) -#define PORTA_OUT _SFR_MEM8(0x0604) -#define PORTA_OUTSET _SFR_MEM8(0x0605) -#define PORTA_OUTCLR _SFR_MEM8(0x0606) -#define PORTA_OUTTGL _SFR_MEM8(0x0607) -#define PORTA_IN _SFR_MEM8(0x0608) -#define PORTA_INTCTRL _SFR_MEM8(0x0609) -#define PORTA_INTMASK _SFR_MEM8(0x060A) -#define PORTA_INTFLAGS _SFR_MEM8(0x060C) -#define PORTA_REMAP _SFR_MEM8(0x060E) -#define PORTA_PIN0CTRL _SFR_MEM8(0x0610) -#define PORTA_PIN1CTRL _SFR_MEM8(0x0611) -#define PORTA_PIN2CTRL _SFR_MEM8(0x0612) -#define PORTA_PIN3CTRL _SFR_MEM8(0x0613) -#define PORTA_PIN4CTRL _SFR_MEM8(0x0614) -#define PORTA_PIN5CTRL _SFR_MEM8(0x0615) -#define PORTA_PIN6CTRL _SFR_MEM8(0x0616) -#define PORTA_PIN7CTRL _SFR_MEM8(0x0617) - -/* PORT - I/O Ports */ -#define PORTC_DIR _SFR_MEM8(0x0640) -#define PORTC_DIRSET _SFR_MEM8(0x0641) -#define PORTC_DIRCLR _SFR_MEM8(0x0642) -#define PORTC_DIRTGL _SFR_MEM8(0x0643) -#define PORTC_OUT _SFR_MEM8(0x0644) -#define PORTC_OUTSET _SFR_MEM8(0x0645) -#define PORTC_OUTCLR _SFR_MEM8(0x0646) -#define PORTC_OUTTGL _SFR_MEM8(0x0647) -#define PORTC_IN _SFR_MEM8(0x0648) -#define PORTC_INTCTRL _SFR_MEM8(0x0649) -#define PORTC_INTMASK _SFR_MEM8(0x064A) -#define PORTC_INTFLAGS _SFR_MEM8(0x064C) -#define PORTC_REMAP _SFR_MEM8(0x064E) -#define PORTC_PIN0CTRL _SFR_MEM8(0x0650) -#define PORTC_PIN1CTRL _SFR_MEM8(0x0651) -#define PORTC_PIN2CTRL _SFR_MEM8(0x0652) -#define PORTC_PIN3CTRL _SFR_MEM8(0x0653) -#define PORTC_PIN4CTRL _SFR_MEM8(0x0654) -#define PORTC_PIN5CTRL _SFR_MEM8(0x0655) -#define PORTC_PIN6CTRL _SFR_MEM8(0x0656) -#define PORTC_PIN7CTRL _SFR_MEM8(0x0657) - -/* PORT - I/O Ports */ -#define PORTD_DIR _SFR_MEM8(0x0660) -#define PORTD_DIRSET _SFR_MEM8(0x0661) -#define PORTD_DIRCLR _SFR_MEM8(0x0662) -#define PORTD_DIRTGL _SFR_MEM8(0x0663) -#define PORTD_OUT _SFR_MEM8(0x0664) -#define PORTD_OUTSET _SFR_MEM8(0x0665) -#define PORTD_OUTCLR _SFR_MEM8(0x0666) -#define PORTD_OUTTGL _SFR_MEM8(0x0667) -#define PORTD_IN _SFR_MEM8(0x0668) -#define PORTD_INTCTRL _SFR_MEM8(0x0669) -#define PORTD_INTMASK _SFR_MEM8(0x066A) -#define PORTD_INTFLAGS _SFR_MEM8(0x066C) -#define PORTD_REMAP _SFR_MEM8(0x066E) -#define PORTD_PIN0CTRL _SFR_MEM8(0x0670) -#define PORTD_PIN1CTRL _SFR_MEM8(0x0671) -#define PORTD_PIN2CTRL _SFR_MEM8(0x0672) -#define PORTD_PIN3CTRL _SFR_MEM8(0x0673) -#define PORTD_PIN4CTRL _SFR_MEM8(0x0674) -#define PORTD_PIN5CTRL _SFR_MEM8(0x0675) -#define PORTD_PIN6CTRL _SFR_MEM8(0x0676) -#define PORTD_PIN7CTRL _SFR_MEM8(0x0677) - -/* PORT - I/O Ports */ -#define PORTR_DIR _SFR_MEM8(0x07E0) -#define PORTR_DIRSET _SFR_MEM8(0x07E1) -#define PORTR_DIRCLR _SFR_MEM8(0x07E2) -#define PORTR_DIRTGL _SFR_MEM8(0x07E3) -#define PORTR_OUT _SFR_MEM8(0x07E4) -#define PORTR_OUTSET _SFR_MEM8(0x07E5) -#define PORTR_OUTCLR _SFR_MEM8(0x07E6) -#define PORTR_OUTTGL _SFR_MEM8(0x07E7) -#define PORTR_IN _SFR_MEM8(0x07E8) -#define PORTR_INTCTRL _SFR_MEM8(0x07E9) -#define PORTR_INTMASK _SFR_MEM8(0x07EA) -#define PORTR_INTFLAGS _SFR_MEM8(0x07EC) -#define PORTR_REMAP _SFR_MEM8(0x07EE) -#define PORTR_PIN0CTRL _SFR_MEM8(0x07F0) -#define PORTR_PIN1CTRL _SFR_MEM8(0x07F1) -#define PORTR_PIN2CTRL _SFR_MEM8(0x07F2) -#define PORTR_PIN3CTRL _SFR_MEM8(0x07F3) -#define PORTR_PIN4CTRL _SFR_MEM8(0x07F4) -#define PORTR_PIN5CTRL _SFR_MEM8(0x07F5) -#define PORTR_PIN6CTRL _SFR_MEM8(0x07F6) -#define PORTR_PIN7CTRL _SFR_MEM8(0x07F7) - -/* TC4 - 16-bit Timer/Counter 4 */ -#define TCC4_CTRLA _SFR_MEM8(0x0800) -#define TCC4_CTRLB _SFR_MEM8(0x0801) -#define TCC4_CTRLC _SFR_MEM8(0x0802) -#define TCC4_CTRLD _SFR_MEM8(0x0803) -#define TCC4_CTRLE _SFR_MEM8(0x0804) -#define TCC4_CTRLF _SFR_MEM8(0x0805) -#define TCC4_INTCTRLA _SFR_MEM8(0x0806) -#define TCC4_INTCTRLB _SFR_MEM8(0x0807) -#define TCC4_CTRLGCLR _SFR_MEM8(0x0808) -#define TCC4_CTRLGSET _SFR_MEM8(0x0809) -#define TCC4_CTRLHCLR _SFR_MEM8(0x080A) -#define TCC4_CTRLHSET _SFR_MEM8(0x080B) -#define TCC4_INTFLAGS _SFR_MEM8(0x080C) -#define TCC4_TEMP _SFR_MEM8(0x080F) -#define TCC4_CNT _SFR_MEM16(0x0820) -#define TCC4_PER _SFR_MEM16(0x0826) -#define TCC4_CCA _SFR_MEM16(0x0828) -#define TCC4_CCB _SFR_MEM16(0x082A) -#define TCC4_CCC _SFR_MEM16(0x082C) -#define TCC4_CCD _SFR_MEM16(0x082E) -#define TCC4_PERBUF _SFR_MEM16(0x0836) -#define TCC4_CCABUF _SFR_MEM16(0x0838) -#define TCC4_CCBBUF _SFR_MEM16(0x083A) -#define TCC4_CCCBUF _SFR_MEM16(0x083C) -#define TCC4_CCDBUF _SFR_MEM16(0x083E) - -/* TC5 - 16-bit Timer/Counter 5 */ -#define TCC5_CTRLA _SFR_MEM8(0x0840) -#define TCC5_CTRLB _SFR_MEM8(0x0841) -#define TCC5_CTRLC _SFR_MEM8(0x0842) -#define TCC5_CTRLD _SFR_MEM8(0x0843) -#define TCC5_CTRLE _SFR_MEM8(0x0844) -#define TCC5_CTRLF _SFR_MEM8(0x0845) -#define TCC5_INTCTRLA _SFR_MEM8(0x0846) -#define TCC5_INTCTRLB _SFR_MEM8(0x0847) -#define TCC5_CTRLGCLR _SFR_MEM8(0x0848) -#define TCC5_CTRLGSET _SFR_MEM8(0x0849) -#define TCC5_CTRLHCLR _SFR_MEM8(0x084A) -#define TCC5_CTRLHSET _SFR_MEM8(0x084B) -#define TCC5_INTFLAGS _SFR_MEM8(0x084C) -#define TCC5_TEMP _SFR_MEM8(0x084F) -#define TCC5_CNT _SFR_MEM16(0x0860) -#define TCC5_PER _SFR_MEM16(0x0866) -#define TCC5_CCA _SFR_MEM16(0x0868) -#define TCC5_CCB _SFR_MEM16(0x086A) -#define TCC5_PERBUF _SFR_MEM16(0x0876) -#define TCC5_CCABUF _SFR_MEM16(0x0878) -#define TCC5_CCBBUF _SFR_MEM16(0x087A) - -/* FAULT - Fault Extension */ -#define FAULTC4_CTRLA _SFR_MEM8(0x0880) -#define FAULTC4_CTRLB _SFR_MEM8(0x0881) -#define FAULTC4_CTRLC _SFR_MEM8(0x0882) -#define FAULTC4_CTRLD _SFR_MEM8(0x0883) -#define FAULTC4_CTRLE _SFR_MEM8(0x0884) -#define FAULTC4_STATUS _SFR_MEM8(0x0885) -#define FAULTC4_CTRLGCLR _SFR_MEM8(0x0886) -#define FAULTC4_CTRLGSET _SFR_MEM8(0x0887) - -/* FAULT - Fault Extension */ -#define FAULTC5_CTRLA _SFR_MEM8(0x0890) -#define FAULTC5_CTRLB _SFR_MEM8(0x0891) -#define FAULTC5_CTRLC _SFR_MEM8(0x0892) -#define FAULTC5_CTRLD _SFR_MEM8(0x0893) -#define FAULTC5_CTRLE _SFR_MEM8(0x0894) -#define FAULTC5_STATUS _SFR_MEM8(0x0895) -#define FAULTC5_CTRLGCLR _SFR_MEM8(0x0896) -#define FAULTC5_CTRLGSET _SFR_MEM8(0x0897) - -/* WEX - Waveform Extension */ -#define WEXC_CTRL _SFR_MEM8(0x08A0) -#define WEXC_DTBOTH _SFR_MEM8(0x08A1) -#define WEXC_DTLS _SFR_MEM8(0x08A2) -#define WEXC_DTHS _SFR_MEM8(0x08A3) -#define WEXC_STATUSCLR _SFR_MEM8(0x08A4) -#define WEXC_STATUSSET _SFR_MEM8(0x08A5) -#define WEXC_SWAP _SFR_MEM8(0x08A6) -#define WEXC_PGO _SFR_MEM8(0x08A7) -#define WEXC_PGV _SFR_MEM8(0x08A8) -#define WEXC_SWAPBUF _SFR_MEM8(0x08AA) -#define WEXC_PGOBUF _SFR_MEM8(0x08AB) -#define WEXC_PGVBUF _SFR_MEM8(0x08AC) -#define WEXC_OUTOVDIS _SFR_MEM8(0x08AF) - -/* HIRES - High-Resolution Extension */ -#define HIRESC_CTRLA _SFR_MEM8(0x08B0) - -/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ -#define USARTC0_DATA _SFR_MEM8(0x08C0) -#define USARTC0_STATUS _SFR_MEM8(0x08C1) -#define USARTC0_CTRLA _SFR_MEM8(0x08C2) -#define USARTC0_CTRLB _SFR_MEM8(0x08C3) -#define USARTC0_CTRLC _SFR_MEM8(0x08C4) -#define USARTC0_CTRLD _SFR_MEM8(0x08C5) -#define USARTC0_BAUDCTRLA _SFR_MEM8(0x08C6) -#define USARTC0_BAUDCTRLB _SFR_MEM8(0x08C7) - -/* SPI - Serial Peripheral Interface with Buffer Modes */ -#define SPIC_CTRL _SFR_MEM8(0x08E0) -#define SPIC_INTCTRL _SFR_MEM8(0x08E1) -#define SPIC_STATUS _SFR_MEM8(0x08E2) -#define SPIC_DATA _SFR_MEM8(0x08E3) -#define SPIC_CTRLB _SFR_MEM8(0x08E4) - -/* IRCOM - IR Communication Module */ -#define IRCOM_CTRL _SFR_MEM8(0x08F8) -#define IRCOM_TXPLCTRL _SFR_MEM8(0x08F9) -#define IRCOM_RXPLCTRL _SFR_MEM8(0x08FA) - -/* TC5 - 16-bit Timer/Counter 5 */ -#define TCD5_CTRLA _SFR_MEM8(0x0940) -#define TCD5_CTRLB _SFR_MEM8(0x0941) -#define TCD5_CTRLC _SFR_MEM8(0x0942) -#define TCD5_CTRLD _SFR_MEM8(0x0943) -#define TCD5_CTRLE _SFR_MEM8(0x0944) -#define TCD5_CTRLF _SFR_MEM8(0x0945) -#define TCD5_INTCTRLA _SFR_MEM8(0x0946) -#define TCD5_INTCTRLB _SFR_MEM8(0x0947) -#define TCD5_CTRLGCLR _SFR_MEM8(0x0948) -#define TCD5_CTRLGSET _SFR_MEM8(0x0949) -#define TCD5_CTRLHCLR _SFR_MEM8(0x094A) -#define TCD5_CTRLHSET _SFR_MEM8(0x094B) -#define TCD5_INTFLAGS _SFR_MEM8(0x094C) -#define TCD5_TEMP _SFR_MEM8(0x094F) -#define TCD5_CNT _SFR_MEM16(0x0960) -#define TCD5_PER _SFR_MEM16(0x0966) -#define TCD5_CCA _SFR_MEM16(0x0968) -#define TCD5_CCB _SFR_MEM16(0x096A) -#define TCD5_PERBUF _SFR_MEM16(0x0976) -#define TCD5_CCABUF _SFR_MEM16(0x0978) -#define TCD5_CCBBUF _SFR_MEM16(0x097A) - -/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ -#define USARTD0_DATA _SFR_MEM8(0x09C0) -#define USARTD0_STATUS _SFR_MEM8(0x09C1) -#define USARTD0_CTRLA _SFR_MEM8(0x09C2) -#define USARTD0_CTRLB _SFR_MEM8(0x09C3) -#define USARTD0_CTRLC _SFR_MEM8(0x09C4) -#define USARTD0_CTRLD _SFR_MEM8(0x09C5) -#define USARTD0_BAUDCTRLA _SFR_MEM8(0x09C6) -#define USARTD0_BAUDCTRLB _SFR_MEM8(0x09C7) - - - -/*================== Bitfield Definitions ================== */ - -/* VPORT - Virtual Ports */ -/* VPORT.INTFLAGS bit masks and bit positions */ -#define VPORT_INT7IF_bm 0x80 /* Interrupt Pin 7 Flag bit mask. */ -#define VPORT_INT7IF_bp 7 /* Interrupt Pin 7 Flag bit position. */ - -#define VPORT_INT6IF_bm 0x40 /* Interrupt Pin 6 Flag bit mask. */ -#define VPORT_INT6IF_bp 6 /* Interrupt Pin 6 Flag bit position. */ - -#define VPORT_INT5IF_bm 0x20 /* Interrupt Pin 5 Flag bit mask. */ -#define VPORT_INT5IF_bp 5 /* Interrupt Pin 5 Flag bit position. */ - -#define VPORT_INT4IF_bm 0x10 /* Interrupt Pin 4 Flag bit mask. */ -#define VPORT_INT4IF_bp 4 /* Interrupt Pin 4 Flag bit position. */ - -#define VPORT_INT3IF_bm 0x08 /* Interrupt Pin 3 Flag bit mask. */ -#define VPORT_INT3IF_bp 3 /* Interrupt Pin 3 Flag bit position. */ - -#define VPORT_INT2IF_bm 0x04 /* Interrupt Pin 2 Flag bit mask. */ -#define VPORT_INT2IF_bp 2 /* Interrupt Pin 2 Flag bit position. */ - -#define VPORT_INT1IF_bm 0x02 /* Interrupt Pin 1 Flag bit mask. */ -#define VPORT_INT1IF_bp 1 /* Interrupt Pin 1 Flag bit position. */ - -#define VPORT_INT0IF_bm 0x01 /* Interrupt Pin 0 Flag bit mask. */ -#define VPORT_INT0IF_bp 0 /* Interrupt Pin 0 Flag bit position. */ - -/* XOCD - On-Chip Debug System */ -/* OCD.OCDR0 bit masks and bit positions */ -#define OCD_OCDRD_gm 0xFF /* OCDR Dirty group mask. */ -#define OCD_OCDRD_gp 0 /* OCDR Dirty group position. */ -#define OCD_OCDRD0_bm (1<<0) /* OCDR Dirty bit 0 mask. */ -#define OCD_OCDRD0_bp 0 /* OCDR Dirty bit 0 position. */ -#define OCD_OCDRD1_bm (1<<1) /* OCDR Dirty bit 1 mask. */ -#define OCD_OCDRD1_bp 1 /* OCDR Dirty bit 1 position. */ -#define OCD_OCDRD2_bm (1<<2) /* OCDR Dirty bit 2 mask. */ -#define OCD_OCDRD2_bp 2 /* OCDR Dirty bit 2 position. */ -#define OCD_OCDRD3_bm (1<<3) /* OCDR Dirty bit 3 mask. */ -#define OCD_OCDRD3_bp 3 /* OCDR Dirty bit 3 position. */ -#define OCD_OCDRD4_bm (1<<4) /* OCDR Dirty bit 4 mask. */ -#define OCD_OCDRD4_bp 4 /* OCDR Dirty bit 4 position. */ -#define OCD_OCDRD5_bm (1<<5) /* OCDR Dirty bit 5 mask. */ -#define OCD_OCDRD5_bp 5 /* OCDR Dirty bit 5 position. */ -#define OCD_OCDRD6_bm (1<<6) /* OCDR Dirty bit 6 mask. */ -#define OCD_OCDRD6_bp 6 /* OCDR Dirty bit 6 position. */ -#define OCD_OCDRD7_bm (1<<7) /* OCDR Dirty bit 7 mask. */ -#define OCD_OCDRD7_bp 7 /* OCDR Dirty bit 7 position. */ - -/* OCD.OCDR1 bit masks and bit positions */ -/* OCD_OCDRD Predefined. */ -/* OCD_OCDRD Predefined. */ - -/* CPU - CPU */ -/* CPU.CCP bit masks and bit positions */ -#define CPU_CCP_gm 0xFF /* CCP signature group mask. */ -#define CPU_CCP_gp 0 /* CCP signature group position. */ -#define CPU_CCP0_bm (1<<0) /* CCP signature bit 0 mask. */ -#define CPU_CCP0_bp 0 /* CCP signature bit 0 position. */ -#define CPU_CCP1_bm (1<<1) /* CCP signature bit 1 mask. */ -#define CPU_CCP1_bp 1 /* CCP signature bit 1 position. */ -#define CPU_CCP2_bm (1<<2) /* CCP signature bit 2 mask. */ -#define CPU_CCP2_bp 2 /* CCP signature bit 2 position. */ -#define CPU_CCP3_bm (1<<3) /* CCP signature bit 3 mask. */ -#define CPU_CCP3_bp 3 /* CCP signature bit 3 position. */ -#define CPU_CCP4_bm (1<<4) /* CCP signature bit 4 mask. */ -#define CPU_CCP4_bp 4 /* CCP signature bit 4 position. */ -#define CPU_CCP5_bm (1<<5) /* CCP signature bit 5 mask. */ -#define CPU_CCP5_bp 5 /* CCP signature bit 5 position. */ -#define CPU_CCP6_bm (1<<6) /* CCP signature bit 6 mask. */ -#define CPU_CCP6_bp 6 /* CCP signature bit 6 position. */ -#define CPU_CCP7_bm (1<<7) /* CCP signature bit 7 mask. */ -#define CPU_CCP7_bp 7 /* CCP signature bit 7 position. */ - -/* CPU.SREG bit masks and bit positions */ -#define CPU_I_bm 0x80 /* Global Interrupt Enable Flag bit mask. */ -#define CPU_I_bp 7 /* Global Interrupt Enable Flag bit position. */ - -#define CPU_T_bm 0x40 /* Transfer Bit bit mask. */ -#define CPU_T_bp 6 /* Transfer Bit bit position. */ - -#define CPU_H_bm 0x20 /* Half Carry Flag bit mask. */ -#define CPU_H_bp 5 /* Half Carry Flag bit position. */ - -#define CPU_S_bm 0x10 /* N Exclusive Or V Flag bit mask. */ -#define CPU_S_bp 4 /* N Exclusive Or V Flag bit position. */ - -#define CPU_V_bm 0x08 /* Two's Complement Overflow Flag bit mask. */ -#define CPU_V_bp 3 /* Two's Complement Overflow Flag bit position. */ - -#define CPU_N_bm 0x04 /* Negative Flag bit mask. */ -#define CPU_N_bp 2 /* Negative Flag bit position. */ - -#define CPU_Z_bm 0x02 /* Zero Flag bit mask. */ -#define CPU_Z_bp 1 /* Zero Flag bit position. */ - -#define CPU_C_bm 0x01 /* Carry Flag bit mask. */ -#define CPU_C_bp 0 /* Carry Flag bit position. */ - -/* CLK - Clock System */ -/* CLK.CTRL bit masks and bit positions */ -#define CLK_SCLKSEL_gm 0x07 /* System Clock Selection group mask. */ -#define CLK_SCLKSEL_gp 0 /* System Clock Selection group position. */ -#define CLK_SCLKSEL0_bm (1<<0) /* System Clock Selection bit 0 mask. */ -#define CLK_SCLKSEL0_bp 0 /* System Clock Selection bit 0 position. */ -#define CLK_SCLKSEL1_bm (1<<1) /* System Clock Selection bit 1 mask. */ -#define CLK_SCLKSEL1_bp 1 /* System Clock Selection bit 1 position. */ -#define CLK_SCLKSEL2_bm (1<<2) /* System Clock Selection bit 2 mask. */ -#define CLK_SCLKSEL2_bp 2 /* System Clock Selection bit 2 position. */ - -/* CLK.PSCTRL bit masks and bit positions */ -#define CLK_PSADIV_gm 0x7C /* Prescaler A Division Factor group mask. */ -#define CLK_PSADIV_gp 2 /* Prescaler A Division Factor group position. */ -#define CLK_PSADIV0_bm (1<<2) /* Prescaler A Division Factor bit 0 mask. */ -#define CLK_PSADIV0_bp 2 /* Prescaler A Division Factor bit 0 position. */ -#define CLK_PSADIV1_bm (1<<3) /* Prescaler A Division Factor bit 1 mask. */ -#define CLK_PSADIV1_bp 3 /* Prescaler A Division Factor bit 1 position. */ -#define CLK_PSADIV2_bm (1<<4) /* Prescaler A Division Factor bit 2 mask. */ -#define CLK_PSADIV2_bp 4 /* Prescaler A Division Factor bit 2 position. */ -#define CLK_PSADIV3_bm (1<<5) /* Prescaler A Division Factor bit 3 mask. */ -#define CLK_PSADIV3_bp 5 /* Prescaler A Division Factor bit 3 position. */ -#define CLK_PSADIV4_bm (1<<6) /* Prescaler A Division Factor bit 4 mask. */ -#define CLK_PSADIV4_bp 6 /* Prescaler A Division Factor bit 4 position. */ - -#define CLK_PSBCDIV_gm 0x03 /* Prescaler B and C Division factor group mask. */ -#define CLK_PSBCDIV_gp 0 /* Prescaler B and C Division factor group position. */ -#define CLK_PSBCDIV0_bm (1<<0) /* Prescaler B and C Division factor bit 0 mask. */ -#define CLK_PSBCDIV0_bp 0 /* Prescaler B and C Division factor bit 0 position. */ -#define CLK_PSBCDIV1_bm (1<<1) /* Prescaler B and C Division factor bit 1 mask. */ -#define CLK_PSBCDIV1_bp 1 /* Prescaler B and C Division factor bit 1 position. */ - -/* CLK.LOCK bit masks and bit positions */ -#define CLK_LOCK_bm 0x01 /* Clock System Lock bit mask. */ -#define CLK_LOCK_bp 0 /* Clock System Lock bit position. */ - -/* CLK.RTCCTRL bit masks and bit positions */ -#define CLK_RTCSRC_gm 0x0E /* Clock Source group mask. */ -#define CLK_RTCSRC_gp 1 /* Clock Source group position. */ -#define CLK_RTCSRC0_bm (1<<1) /* Clock Source bit 0 mask. */ -#define CLK_RTCSRC0_bp 1 /* Clock Source bit 0 position. */ -#define CLK_RTCSRC1_bm (1<<2) /* Clock Source bit 1 mask. */ -#define CLK_RTCSRC1_bp 2 /* Clock Source bit 1 position. */ -#define CLK_RTCSRC2_bm (1<<3) /* Clock Source bit 2 mask. */ -#define CLK_RTCSRC2_bp 3 /* Clock Source bit 2 position. */ - -#define CLK_RTCEN_bm 0x01 /* Clock Source Enable bit mask. */ -#define CLK_RTCEN_bp 0 /* Clock Source Enable bit position. */ - -/* PR.PRGEN bit masks and bit positions */ -#define PR_XCL_bm 0x80 /* XMEGA Custom Logic bit mask. */ -#define PR_XCL_bp 7 /* XMEGA Custom Logic bit position. */ - -#define PR_RTC_bm 0x04 /* Real-time Counter bit mask. */ -#define PR_RTC_bp 2 /* Real-time Counter bit position. */ - -#define PR_EVSYS_bm 0x02 /* Event System bit mask. */ -#define PR_EVSYS_bp 1 /* Event System bit position. */ - -#define PR_EDMA_bm 0x01 /* Enhanced DMA-Controller bit mask. */ -#define PR_EDMA_bp 0 /* Enhanced DMA-Controller bit position. */ - -/* PR.PRPA bit masks and bit positions */ -#define PR_DAC_bm 0x04 /* Port A DAC bit mask. */ -#define PR_DAC_bp 2 /* Port A DAC bit position. */ - -#define PR_ADC_bm 0x02 /* Port A ADC bit mask. */ -#define PR_ADC_bp 1 /* Port A ADC bit position. */ - -#define PR_AC_bm 0x01 /* Port A Analog Comparator bit mask. */ -#define PR_AC_bp 0 /* Port A Analog Comparator bit position. */ - -/* PR.PRPC bit masks and bit positions */ -#define PR_TWI_bm 0x40 /* Port C Two-wire Interface bit mask. */ -#define PR_TWI_bp 6 /* Port C Two-wire Interface bit position. */ - -#define PR_USART0_bm 0x10 /* Port C USART0 bit mask. */ -#define PR_USART0_bp 4 /* Port C USART0 bit position. */ - -#define PR_SPI_bm 0x08 /* Port C SPI bit mask. */ -#define PR_SPI_bp 3 /* Port C SPI bit position. */ - -#define PR_HIRES_bm 0x04 /* Port C WEX bit mask. */ -#define PR_HIRES_bp 2 /* Port C WEX bit position. */ - -#define PR_TC5_bm 0x02 /* Port C Timer/Counter5 bit mask. */ -#define PR_TC5_bp 1 /* Port C Timer/Counter5 bit position. */ - -#define PR_TC4_bm 0x01 /* Port C Timer/Counter4 bit mask. */ -#define PR_TC4_bp 0 /* Port C Timer/Counter4 bit position. */ - -/* PR.PRPD bit masks and bit positions */ -/* PR_USART0 Predefined. */ -/* PR_USART0 Predefined. */ - -/* PR_TC5 Predefined. */ -/* PR_TC5 Predefined. */ - -/* SLEEP - Sleep Controller */ -/* SLEEP.CTRL bit masks and bit positions */ -#define SLEEP_SMODE_gm 0x0E /* Sleep Mode group mask. */ -#define SLEEP_SMODE_gp 1 /* Sleep Mode group position. */ -#define SLEEP_SMODE0_bm (1<<1) /* Sleep Mode bit 0 mask. */ -#define SLEEP_SMODE0_bp 1 /* Sleep Mode bit 0 position. */ -#define SLEEP_SMODE1_bm (1<<2) /* Sleep Mode bit 1 mask. */ -#define SLEEP_SMODE1_bp 2 /* Sleep Mode bit 1 position. */ -#define SLEEP_SMODE2_bm (1<<3) /* Sleep Mode bit 2 mask. */ -#define SLEEP_SMODE2_bp 3 /* Sleep Mode bit 2 position. */ - -#define SLEEP_SEN_bm 0x01 /* Sleep Enable bit mask. */ -#define SLEEP_SEN_bp 0 /* Sleep Enable bit position. */ - -/* OSC - Oscillator */ -/* OSC.CTRL bit masks and bit positions */ -#define OSC_RC8MLPM_bm 0x40 /* Internal 8 MHz RC Low Power Mode Enable bit mask. */ -#define OSC_RC8MLPM_bp 6 /* Internal 8 MHz RC Low Power Mode Enable bit position. */ - -#define OSC_RC8MEN_bm 0x20 /* Internal 8 MHz RC Oscillator Enable bit mask. */ -#define OSC_RC8MEN_bp 5 /* Internal 8 MHz RC Oscillator Enable bit position. */ - -#define OSC_PLLEN_bm 0x10 /* PLL Enable bit mask. */ -#define OSC_PLLEN_bp 4 /* PLL Enable bit position. */ - -#define OSC_XOSCEN_bm 0x08 /* External Oscillator Enable bit mask. */ -#define OSC_XOSCEN_bp 3 /* External Oscillator Enable bit position. */ - -#define OSC_RC32KEN_bm 0x04 /* Internal 32.768 kHz RC Oscillator Enable bit mask. */ -#define OSC_RC32KEN_bp 2 /* Internal 32.768 kHz RC Oscillator Enable bit position. */ - -#define OSC_RC32MEN_bm 0x02 /* Internal 32 MHz RC Oscillator Enable bit mask. */ -#define OSC_RC32MEN_bp 1 /* Internal 32 MHz RC Oscillator Enable bit position. */ - -#define OSC_RC2MEN_bm 0x01 /* Internal 2 MHz RC Oscillator Enable bit mask. */ -#define OSC_RC2MEN_bp 0 /* Internal 2 MHz RC Oscillator Enable bit position. */ - -/* OSC.STATUS bit masks and bit positions */ -#define OSC_RC8MRDY_bm 0x20 /* Internal 8 MHz RC Oscillator Ready bit mask. */ -#define OSC_RC8MRDY_bp 5 /* Internal 8 MHz RC Oscillator Ready bit position. */ - -#define OSC_PLLRDY_bm 0x10 /* PLL Ready bit mask. */ -#define OSC_PLLRDY_bp 4 /* PLL Ready bit position. */ - -#define OSC_XOSCRDY_bm 0x08 /* External Oscillator Ready bit mask. */ -#define OSC_XOSCRDY_bp 3 /* External Oscillator Ready bit position. */ - -#define OSC_RC32KRDY_bm 0x04 /* Internal 32.768 kHz RC Oscillator Ready bit mask. */ -#define OSC_RC32KRDY_bp 2 /* Internal 32.768 kHz RC Oscillator Ready bit position. */ - -#define OSC_RC32MRDY_bm 0x02 /* Internal 32 MHz RC Oscillator Ready bit mask. */ -#define OSC_RC32MRDY_bp 1 /* Internal 32 MHz RC Oscillator Ready bit position. */ - -#define OSC_RC2MRDY_bm 0x01 /* Internal 2 MHz RC Oscillator Ready bit mask. */ -#define OSC_RC2MRDY_bp 0 /* Internal 2 MHz RC Oscillator Ready bit position. */ - -/* OSC.XOSCCTRL bit masks and bit positions */ -#define OSC_FRQRANGE_gm 0xC0 /* Frequency Range group mask. */ -#define OSC_FRQRANGE_gp 6 /* Frequency Range group position. */ -#define OSC_FRQRANGE0_bm (1<<6) /* Frequency Range bit 0 mask. */ -#define OSC_FRQRANGE0_bp 6 /* Frequency Range bit 0 position. */ -#define OSC_FRQRANGE1_bm (1<<7) /* Frequency Range bit 1 mask. */ -#define OSC_FRQRANGE1_bp 7 /* Frequency Range bit 1 position. */ - -#define OSC_X32KLPM_bm 0x20 /* 32.768 kHz XTAL OSC Low-power Mode bit mask. */ -#define OSC_X32KLPM_bp 5 /* 32.768 kHz XTAL OSC Low-power Mode bit position. */ - -#define OSC_XOSCPWR_bm 0x10 /* 16 MHz Crystal Oscillator High Power mode bit mask. */ -#define OSC_XOSCPWR_bp 4 /* 16 MHz Crystal Oscillator High Power mode bit position. */ - -#define OSC_XOSCSEL_gm 0x1F /* External Oscillator Selection and Startup Time group mask. */ -#define OSC_XOSCSEL_gp 0 /* External Oscillator Selection and Startup Time group position. */ -#define OSC_XOSCSEL0_bm (1<<0) /* External Oscillator Selection and Startup Time bit 0 mask. */ -#define OSC_XOSCSEL0_bp 0 /* External Oscillator Selection and Startup Time bit 0 position. */ -#define OSC_XOSCSEL1_bm (1<<1) /* External Oscillator Selection and Startup Time bit 1 mask. */ -#define OSC_XOSCSEL1_bp 1 /* External Oscillator Selection and Startup Time bit 1 position. */ -#define OSC_XOSCSEL2_bm (1<<2) /* External Oscillator Selection and Startup Time bit 2 mask. */ -#define OSC_XOSCSEL2_bp 2 /* External Oscillator Selection and Startup Time bit 2 position. */ -#define OSC_XOSCSEL3_bm (1<<3) /* External Oscillator Selection and Startup Time bit 3 mask. */ -#define OSC_XOSCSEL3_bp 3 /* External Oscillator Selection and Startup Time bit 3 position. */ -#define OSC_XOSCSEL4_bm (1<<4) /* External Oscillator Selection and Startup Time bit 4 mask. */ -#define OSC_XOSCSEL4_bp 4 /* External Oscillator Selection and Startup Time bit 4 position. */ - -/* OSC.XOSCFAIL bit masks and bit positions */ -#define OSC_PLLFDIF_bm 0x08 /* PLL Failure Detection Interrupt Flag bit mask. */ -#define OSC_PLLFDIF_bp 3 /* PLL Failure Detection Interrupt Flag bit position. */ - -#define OSC_PLLFDEN_bm 0x04 /* PLL Failure Detection Enable bit mask. */ -#define OSC_PLLFDEN_bp 2 /* PLL Failure Detection Enable bit position. */ - -#define OSC_XOSCFDIF_bm 0x02 /* XOSC Failure Detection Interrupt Flag bit mask. */ -#define OSC_XOSCFDIF_bp 1 /* XOSC Failure Detection Interrupt Flag bit position. */ - -#define OSC_XOSCFDEN_bm 0x01 /* XOSC Failure Detection Enable bit mask. */ -#define OSC_XOSCFDEN_bp 0 /* XOSC Failure Detection Enable bit position. */ - -/* OSC.PLLCTRL bit masks and bit positions */ -#define OSC_PLLSRC_gm 0xC0 /* Clock Source group mask. */ -#define OSC_PLLSRC_gp 6 /* Clock Source group position. */ -#define OSC_PLLSRC0_bm (1<<6) /* Clock Source bit 0 mask. */ -#define OSC_PLLSRC0_bp 6 /* Clock Source bit 0 position. */ -#define OSC_PLLSRC1_bm (1<<7) /* Clock Source bit 1 mask. */ -#define OSC_PLLSRC1_bp 7 /* Clock Source bit 1 position. */ - -#define OSC_PLLDIV_bm 0x20 /* Divide by 2 bit mask. */ -#define OSC_PLLDIV_bp 5 /* Divide by 2 bit position. */ - -#define OSC_PLLFAC_gm 0x1F /* Multiplication Factor group mask. */ -#define OSC_PLLFAC_gp 0 /* Multiplication Factor group position. */ -#define OSC_PLLFAC0_bm (1<<0) /* Multiplication Factor bit 0 mask. */ -#define OSC_PLLFAC0_bp 0 /* Multiplication Factor bit 0 position. */ -#define OSC_PLLFAC1_bm (1<<1) /* Multiplication Factor bit 1 mask. */ -#define OSC_PLLFAC1_bp 1 /* Multiplication Factor bit 1 position. */ -#define OSC_PLLFAC2_bm (1<<2) /* Multiplication Factor bit 2 mask. */ -#define OSC_PLLFAC2_bp 2 /* Multiplication Factor bit 2 position. */ -#define OSC_PLLFAC3_bm (1<<3) /* Multiplication Factor bit 3 mask. */ -#define OSC_PLLFAC3_bp 3 /* Multiplication Factor bit 3 position. */ -#define OSC_PLLFAC4_bm (1<<4) /* Multiplication Factor bit 4 mask. */ -#define OSC_PLLFAC4_bp 4 /* Multiplication Factor bit 4 position. */ - -/* OSC.DFLLCTRL bit masks and bit positions */ -#define OSC_RC32MCREF_gm 0x06 /* 32 MHz DFLL Calibration Reference group mask. */ -#define OSC_RC32MCREF_gp 1 /* 32 MHz DFLL Calibration Reference group position. */ -#define OSC_RC32MCREF0_bm (1<<1) /* 32 MHz DFLL Calibration Reference bit 0 mask. */ -#define OSC_RC32MCREF0_bp 1 /* 32 MHz DFLL Calibration Reference bit 0 position. */ -#define OSC_RC32MCREF1_bm (1<<2) /* 32 MHz DFLL Calibration Reference bit 1 mask. */ -#define OSC_RC32MCREF1_bp 2 /* 32 MHz DFLL Calibration Reference bit 1 position. */ - -/* OSC.RC8MCAL bit masks and bit positions */ -#define OSC_RC8MCAL_gm 0xFF /* Calibration Bits group mask. */ -#define OSC_RC8MCAL_gp 0 /* Calibration Bits group position. */ -#define OSC_RC8MCAL0_bm (1<<0) /* Calibration Bits bit 0 mask. */ -#define OSC_RC8MCAL0_bp 0 /* Calibration Bits bit 0 position. */ -#define OSC_RC8MCAL1_bm (1<<1) /* Calibration Bits bit 1 mask. */ -#define OSC_RC8MCAL1_bp 1 /* Calibration Bits bit 1 position. */ -#define OSC_RC8MCAL2_bm (1<<2) /* Calibration Bits bit 2 mask. */ -#define OSC_RC8MCAL2_bp 2 /* Calibration Bits bit 2 position. */ -#define OSC_RC8MCAL3_bm (1<<3) /* Calibration Bits bit 3 mask. */ -#define OSC_RC8MCAL3_bp 3 /* Calibration Bits bit 3 position. */ -#define OSC_RC8MCAL4_bm (1<<4) /* Calibration Bits bit 4 mask. */ -#define OSC_RC8MCAL4_bp 4 /* Calibration Bits bit 4 position. */ -#define OSC_RC8MCAL5_bm (1<<5) /* Calibration Bits bit 5 mask. */ -#define OSC_RC8MCAL5_bp 5 /* Calibration Bits bit 5 position. */ -#define OSC_RC8MCAL6_bm (1<<6) /* Calibration Bits bit 6 mask. */ -#define OSC_RC8MCAL6_bp 6 /* Calibration Bits bit 6 position. */ -#define OSC_RC8MCAL7_bm (1<<7) /* Calibration Bits bit 7 mask. */ -#define OSC_RC8MCAL7_bp 7 /* Calibration Bits bit 7 position. */ - -/* DFLL - DFLL */ -/* DFLL.CTRL bit masks and bit positions */ -#define DFLL_ENABLE_bm 0x01 /* DFLL Enable bit mask. */ -#define DFLL_ENABLE_bp 0 /* DFLL Enable bit position. */ - -/* DFLL.CALA bit masks and bit positions */ -#define DFLL_CALL_gm 0x7F /* DFLL Calibration Value A group mask. */ -#define DFLL_CALL_gp 0 /* DFLL Calibration Value A group position. */ -#define DFLL_CALL0_bm (1<<0) /* DFLL Calibration Value A bit 0 mask. */ -#define DFLL_CALL0_bp 0 /* DFLL Calibration Value A bit 0 position. */ -#define DFLL_CALL1_bm (1<<1) /* DFLL Calibration Value A bit 1 mask. */ -#define DFLL_CALL1_bp 1 /* DFLL Calibration Value A bit 1 position. */ -#define DFLL_CALL2_bm (1<<2) /* DFLL Calibration Value A bit 2 mask. */ -#define DFLL_CALL2_bp 2 /* DFLL Calibration Value A bit 2 position. */ -#define DFLL_CALL3_bm (1<<3) /* DFLL Calibration Value A bit 3 mask. */ -#define DFLL_CALL3_bp 3 /* DFLL Calibration Value A bit 3 position. */ -#define DFLL_CALL4_bm (1<<4) /* DFLL Calibration Value A bit 4 mask. */ -#define DFLL_CALL4_bp 4 /* DFLL Calibration Value A bit 4 position. */ -#define DFLL_CALL5_bm (1<<5) /* DFLL Calibration Value A bit 5 mask. */ -#define DFLL_CALL5_bp 5 /* DFLL Calibration Value A bit 5 position. */ -#define DFLL_CALL6_bm (1<<6) /* DFLL Calibration Value A bit 6 mask. */ -#define DFLL_CALL6_bp 6 /* DFLL Calibration Value A bit 6 position. */ - -/* DFLL.CALB bit masks and bit positions */ -#define DFLL_CALH_gm 0x3F /* DFLL Calibration Value B group mask. */ -#define DFLL_CALH_gp 0 /* DFLL Calibration Value B group position. */ -#define DFLL_CALH0_bm (1<<0) /* DFLL Calibration Value B bit 0 mask. */ -#define DFLL_CALH0_bp 0 /* DFLL Calibration Value B bit 0 position. */ -#define DFLL_CALH1_bm (1<<1) /* DFLL Calibration Value B bit 1 mask. */ -#define DFLL_CALH1_bp 1 /* DFLL Calibration Value B bit 1 position. */ -#define DFLL_CALH2_bm (1<<2) /* DFLL Calibration Value B bit 2 mask. */ -#define DFLL_CALH2_bp 2 /* DFLL Calibration Value B bit 2 position. */ -#define DFLL_CALH3_bm (1<<3) /* DFLL Calibration Value B bit 3 mask. */ -#define DFLL_CALH3_bp 3 /* DFLL Calibration Value B bit 3 position. */ -#define DFLL_CALH4_bm (1<<4) /* DFLL Calibration Value B bit 4 mask. */ -#define DFLL_CALH4_bp 4 /* DFLL Calibration Value B bit 4 position. */ -#define DFLL_CALH5_bm (1<<5) /* DFLL Calibration Value B bit 5 mask. */ -#define DFLL_CALH5_bp 5 /* DFLL Calibration Value B bit 5 position. */ - -/* RST - Reset */ -/* RST.STATUS bit masks and bit positions */ -#define RST_SDRF_bm 0x40 /* Spike Detection Reset Flag bit mask. */ -#define RST_SDRF_bp 6 /* Spike Detection Reset Flag bit position. */ - -#define RST_SRF_bm 0x20 /* Software Reset Flag bit mask. */ -#define RST_SRF_bp 5 /* Software Reset Flag bit position. */ - -#define RST_PDIRF_bm 0x10 /* Programming and Debug Interface Interface Reset Flag bit mask. */ -#define RST_PDIRF_bp 4 /* Programming and Debug Interface Interface Reset Flag bit position. */ - -#define RST_WDRF_bm 0x08 /* Watchdog Reset Flag bit mask. */ -#define RST_WDRF_bp 3 /* Watchdog Reset Flag bit position. */ - -#define RST_BORF_bm 0x04 /* Brown-out Reset Flag bit mask. */ -#define RST_BORF_bp 2 /* Brown-out Reset Flag bit position. */ - -#define RST_EXTRF_bm 0x02 /* External Reset Flag bit mask. */ -#define RST_EXTRF_bp 1 /* External Reset Flag bit position. */ - -#define RST_PORF_bm 0x01 /* Power-on Reset Flag bit mask. */ -#define RST_PORF_bp 0 /* Power-on Reset Flag bit position. */ - -/* RST.CTRL bit masks and bit positions */ -#define RST_SWRST_bm 0x01 /* Software Reset bit mask. */ -#define RST_SWRST_bp 0 /* Software Reset bit position. */ - -/* WDT - Watch-Dog Timer */ -/* WDT.CTRL bit masks and bit positions */ -#define WDT_PER_gm 0x3C /* Period group mask. */ -#define WDT_PER_gp 2 /* Period group position. */ -#define WDT_PER0_bm (1<<2) /* Period bit 0 mask. */ -#define WDT_PER0_bp 2 /* Period bit 0 position. */ -#define WDT_PER1_bm (1<<3) /* Period bit 1 mask. */ -#define WDT_PER1_bp 3 /* Period bit 1 position. */ -#define WDT_PER2_bm (1<<4) /* Period bit 2 mask. */ -#define WDT_PER2_bp 4 /* Period bit 2 position. */ -#define WDT_PER3_bm (1<<5) /* Period bit 3 mask. */ -#define WDT_PER3_bp 5 /* Period bit 3 position. */ - -#define WDT_ENABLE_bm 0x02 /* Enable bit mask. */ -#define WDT_ENABLE_bp 1 /* Enable bit position. */ - -#define WDT_CEN_bm 0x01 /* Change Enable bit mask. */ -#define WDT_CEN_bp 0 /* Change Enable bit position. */ - -/* WDT.WINCTRL bit masks and bit positions */ -#define WDT_WPER_gm 0x3C /* Windowed Mode Period group mask. */ -#define WDT_WPER_gp 2 /* Windowed Mode Period group position. */ -#define WDT_WPER0_bm (1<<2) /* Windowed Mode Period bit 0 mask. */ -#define WDT_WPER0_bp 2 /* Windowed Mode Period bit 0 position. */ -#define WDT_WPER1_bm (1<<3) /* Windowed Mode Period bit 1 mask. */ -#define WDT_WPER1_bp 3 /* Windowed Mode Period bit 1 position. */ -#define WDT_WPER2_bm (1<<4) /* Windowed Mode Period bit 2 mask. */ -#define WDT_WPER2_bp 4 /* Windowed Mode Period bit 2 position. */ -#define WDT_WPER3_bm (1<<5) /* Windowed Mode Period bit 3 mask. */ -#define WDT_WPER3_bp 5 /* Windowed Mode Period bit 3 position. */ - -#define WDT_WEN_bm 0x02 /* Windowed Mode Enable bit mask. */ -#define WDT_WEN_bp 1 /* Windowed Mode Enable bit position. */ - -#define WDT_WCEN_bm 0x01 /* Windowed Mode Change Enable bit mask. */ -#define WDT_WCEN_bp 0 /* Windowed Mode Change Enable bit position. */ - -/* WDT.STATUS bit masks and bit positions */ -#define WDT_SYNCBUSY_bm 0x01 /* Syncronization busy bit mask. */ -#define WDT_SYNCBUSY_bp 0 /* Syncronization busy bit position. */ - -/* MCU - MCU Control */ -/* MCU.ANAINIT bit masks and bit positions */ -#define MCU_STARTUPDLYA_gm 0x03 /* Analog startup delay Port A group mask. */ -#define MCU_STARTUPDLYA_gp 0 /* Analog startup delay Port A group position. */ -#define MCU_STARTUPDLYA0_bm (1<<0) /* Analog startup delay Port A bit 0 mask. */ -#define MCU_STARTUPDLYA0_bp 0 /* Analog startup delay Port A bit 0 position. */ -#define MCU_STARTUPDLYA1_bm (1<<1) /* Analog startup delay Port A bit 1 mask. */ -#define MCU_STARTUPDLYA1_bp 1 /* Analog startup delay Port A bit 1 position. */ - -/* MCU.EVSYSLOCK bit masks and bit positions */ -#define MCU_EVSYS1LOCK_bm 0x10 /* Event Channel 4-7 Lock bit mask. */ -#define MCU_EVSYS1LOCK_bp 4 /* Event Channel 4-7 Lock bit position. */ - -#define MCU_EVSYS0LOCK_bm 0x01 /* Event Channel 0-3 Lock bit mask. */ -#define MCU_EVSYS0LOCK_bp 0 /* Event Channel 0-3 Lock bit position. */ - -/* MCU.WEXLOCK bit masks and bit positions */ -#define MCU_WEXCLOCK_bm 0x01 /* WeX on T/C C4 Lock bit mask. */ -#define MCU_WEXCLOCK_bp 0 /* WeX on T/C C4 Lock bit position. */ - -/* MCU.FAULTLOCK bit masks and bit positions */ -#define MCU_FAULTC5LOCK_bm 0x02 /* Fault on T/C C5 Lock bit mask. */ -#define MCU_FAULTC5LOCK_bp 1 /* Fault on T/C C5 Lock bit position. */ - -#define MCU_FAULTC4LOCK_bm 0x01 /* Fault on T/C C4 Lock bit mask. */ -#define MCU_FAULTC4LOCK_bp 0 /* Fault on T/C C4 Lock bit position. */ - -/* PMIC - Programmable Multi-level Interrupt Controller */ -/* PMIC.STATUS bit masks and bit positions */ -#define PMIC_NMIEX_bm 0x80 /* Non-maskable Interrupt Executing bit mask. */ -#define PMIC_NMIEX_bp 7 /* Non-maskable Interrupt Executing bit position. */ - -#define PMIC_HILVLEX_bm 0x04 /* High Level Interrupt Executing bit mask. */ -#define PMIC_HILVLEX_bp 2 /* High Level Interrupt Executing bit position. */ - -#define PMIC_MEDLVLEX_bm 0x02 /* Medium Level Interrupt Executing bit mask. */ -#define PMIC_MEDLVLEX_bp 1 /* Medium Level Interrupt Executing bit position. */ - -#define PMIC_LOLVLEX_bm 0x01 /* Low Level Interrupt Executing bit mask. */ -#define PMIC_LOLVLEX_bp 0 /* Low Level Interrupt Executing bit position. */ - -/* PMIC.INTPRI bit masks and bit positions */ -#define PMIC_INTPRI_gm 0xFF /* Interrupt Priority group mask. */ -#define PMIC_INTPRI_gp 0 /* Interrupt Priority group position. */ -#define PMIC_INTPRI0_bm (1<<0) /* Interrupt Priority bit 0 mask. */ -#define PMIC_INTPRI0_bp 0 /* Interrupt Priority bit 0 position. */ -#define PMIC_INTPRI1_bm (1<<1) /* Interrupt Priority bit 1 mask. */ -#define PMIC_INTPRI1_bp 1 /* Interrupt Priority bit 1 position. */ -#define PMIC_INTPRI2_bm (1<<2) /* Interrupt Priority bit 2 mask. */ -#define PMIC_INTPRI2_bp 2 /* Interrupt Priority bit 2 position. */ -#define PMIC_INTPRI3_bm (1<<3) /* Interrupt Priority bit 3 mask. */ -#define PMIC_INTPRI3_bp 3 /* Interrupt Priority bit 3 position. */ -#define PMIC_INTPRI4_bm (1<<4) /* Interrupt Priority bit 4 mask. */ -#define PMIC_INTPRI4_bp 4 /* Interrupt Priority bit 4 position. */ -#define PMIC_INTPRI5_bm (1<<5) /* Interrupt Priority bit 5 mask. */ -#define PMIC_INTPRI5_bp 5 /* Interrupt Priority bit 5 position. */ -#define PMIC_INTPRI6_bm (1<<6) /* Interrupt Priority bit 6 mask. */ -#define PMIC_INTPRI6_bp 6 /* Interrupt Priority bit 6 position. */ -#define PMIC_INTPRI7_bm (1<<7) /* Interrupt Priority bit 7 mask. */ -#define PMIC_INTPRI7_bp 7 /* Interrupt Priority bit 7 position. */ - -/* PMIC.CTRL bit masks and bit positions */ -#define PMIC_RREN_bm 0x80 /* Round-Robin Priority Enable bit mask. */ -#define PMIC_RREN_bp 7 /* Round-Robin Priority Enable bit position. */ - -#define PMIC_IVSEL_bm 0x40 /* Interrupt Vector Select bit mask. */ -#define PMIC_IVSEL_bp 6 /* Interrupt Vector Select bit position. */ - -#define PMIC_HILVLEN_bm 0x04 /* High Level Enable bit mask. */ -#define PMIC_HILVLEN_bp 2 /* High Level Enable bit position. */ - -#define PMIC_MEDLVLEN_bm 0x02 /* Medium Level Enable bit mask. */ -#define PMIC_MEDLVLEN_bp 1 /* Medium Level Enable bit position. */ - -#define PMIC_LOLVLEN_bm 0x01 /* Low Level Enable bit mask. */ -#define PMIC_LOLVLEN_bp 0 /* Low Level Enable bit position. */ - -/* PORTCFG - Port Configuration */ -/* PORTCFG.CLKOUT bit masks and bit positions */ -#define PORTCFG_CLKEVPIN_bm 0x80 /* Clock and Event Output Pin Select bit mask. */ -#define PORTCFG_CLKEVPIN_bp 7 /* Clock and Event Output Pin Select bit position. */ - -#define PORTCFG_RTCOUT_gm 0x60 /* RTC Clock Output Enable group mask. */ -#define PORTCFG_RTCOUT_gp 5 /* RTC Clock Output Enable group position. */ -#define PORTCFG_RTCOUT0_bm (1<<5) /* RTC Clock Output Enable bit 0 mask. */ -#define PORTCFG_RTCOUT0_bp 5 /* RTC Clock Output Enable bit 0 position. */ -#define PORTCFG_RTCOUT1_bm (1<<6) /* RTC Clock Output Enable bit 1 mask. */ -#define PORTCFG_RTCOUT1_bp 6 /* RTC Clock Output Enable bit 1 position. */ - -#define PORTCFG_CLKOUTSEL_gm 0x0C /* Clock Output Select group mask. */ -#define PORTCFG_CLKOUTSEL_gp 2 /* Clock Output Select group position. */ -#define PORTCFG_CLKOUTSEL0_bm (1<<2) /* Clock Output Select bit 0 mask. */ -#define PORTCFG_CLKOUTSEL0_bp 2 /* Clock Output Select bit 0 position. */ -#define PORTCFG_CLKOUTSEL1_bm (1<<3) /* Clock Output Select bit 1 mask. */ -#define PORTCFG_CLKOUTSEL1_bp 3 /* Clock Output Select bit 1 position. */ - -#define PORTCFG_CLKOUT_gm 0x03 /* Clock Output Port group mask. */ -#define PORTCFG_CLKOUT_gp 0 /* Clock Output Port group position. */ -#define PORTCFG_CLKOUT0_bm (1<<0) /* Clock Output Port bit 0 mask. */ -#define PORTCFG_CLKOUT0_bp 0 /* Clock Output Port bit 0 position. */ -#define PORTCFG_CLKOUT1_bm (1<<1) /* Clock Output Port bit 1 mask. */ -#define PORTCFG_CLKOUT1_bp 1 /* Clock Output Port bit 1 position. */ - -/* PORTCFG.ACEVOUT bit masks and bit positions */ -#define PORTCFG_ACOUT_gm 0xC0 /* Analog Comparator Output Port group mask. */ -#define PORTCFG_ACOUT_gp 6 /* Analog Comparator Output Port group position. */ -#define PORTCFG_ACOUT0_bm (1<<6) /* Analog Comparator Output Port bit 0 mask. */ -#define PORTCFG_ACOUT0_bp 6 /* Analog Comparator Output Port bit 0 position. */ -#define PORTCFG_ACOUT1_bm (1<<7) /* Analog Comparator Output Port bit 1 mask. */ -#define PORTCFG_ACOUT1_bp 7 /* Analog Comparator Output Port bit 1 position. */ - -#define PORTCFG_EVOUT_gm 0x30 /* Event Channel Output Port group mask. */ -#define PORTCFG_EVOUT_gp 4 /* Event Channel Output Port group position. */ -#define PORTCFG_EVOUT0_bm (1<<4) /* Event Channel Output Port bit 0 mask. */ -#define PORTCFG_EVOUT0_bp 4 /* Event Channel Output Port bit 0 position. */ -#define PORTCFG_EVOUT1_bm (1<<5) /* Event Channel Output Port bit 1 mask. */ -#define PORTCFG_EVOUT1_bp 5 /* Event Channel Output Port bit 1 position. */ - -#define PORTCFG_EVASYEN_bm 0x08 /* Asynchronous Event Enabled bit mask. */ -#define PORTCFG_EVASYEN_bp 3 /* Asynchronous Event Enabled bit position. */ - -#define PORTCFG_EVOUTSEL_gm 0x07 /* Event Channel Output Selection group mask. */ -#define PORTCFG_EVOUTSEL_gp 0 /* Event Channel Output Selection group position. */ -#define PORTCFG_EVOUTSEL0_bm (1<<0) /* Event Channel Output Selection bit 0 mask. */ -#define PORTCFG_EVOUTSEL0_bp 0 /* Event Channel Output Selection bit 0 position. */ -#define PORTCFG_EVOUTSEL1_bm (1<<1) /* Event Channel Output Selection bit 1 mask. */ -#define PORTCFG_EVOUTSEL1_bp 1 /* Event Channel Output Selection bit 1 position. */ -#define PORTCFG_EVOUTSEL2_bm (1<<2) /* Event Channel Output Selection bit 2 mask. */ -#define PORTCFG_EVOUTSEL2_bp 2 /* Event Channel Output Selection bit 2 position. */ - -/* PORTCFG.SRLCTRL bit masks and bit positions */ -#define PORTCFG_SRLENRA_bm 0x01 /* Slew Rate Limit Enable on PORTA bit mask. */ -#define PORTCFG_SRLENRA_bp 0 /* Slew Rate Limit Enable on PORTA bit position. */ - -#define PORTCFG_SRLENRC_bm 0x04 /* Slew Rate Limit Enable on PORTC bit mask. */ -#define PORTCFG_SRLENRC_bp 2 /* Slew Rate Limit Enable on PORTC bit position. */ - -#define PORTCFG_SRLENRD_bm 0x08 /* Slew Rate Limit Enable on PORTD bit mask. */ -#define PORTCFG_SRLENRD_bp 3 /* Slew Rate Limit Enable on PORTD bit position. */ - -#define PORTCFG_SRLENRR_bm 0x80 /* Slew Rate Limit Enable on PORTR bit mask. */ -#define PORTCFG_SRLENRR_bp 7 /* Slew Rate Limit Enable on PORTR bit position. */ - -/* CRC - Cyclic Redundancy Checker */ -/* CRC.CTRL bit masks and bit positions */ -#define CRC_RESET_gm 0xC0 /* Reset group mask. */ -#define CRC_RESET_gp 6 /* Reset group position. */ -#define CRC_RESET0_bm (1<<6) /* Reset bit 0 mask. */ -#define CRC_RESET0_bp 6 /* Reset bit 0 position. */ -#define CRC_RESET1_bm (1<<7) /* Reset bit 1 mask. */ -#define CRC_RESET1_bp 7 /* Reset bit 1 position. */ - -#define CRC_CRC32_bm 0x20 /* CRC Mode bit mask. */ -#define CRC_CRC32_bp 5 /* CRC Mode bit position. */ - -#define CRC_SOURCE_gm 0x0F /* Input Source group mask. */ -#define CRC_SOURCE_gp 0 /* Input Source group position. */ -#define CRC_SOURCE0_bm (1<<0) /* Input Source bit 0 mask. */ -#define CRC_SOURCE0_bp 0 /* Input Source bit 0 position. */ -#define CRC_SOURCE1_bm (1<<1) /* Input Source bit 1 mask. */ -#define CRC_SOURCE1_bp 1 /* Input Source bit 1 position. */ -#define CRC_SOURCE2_bm (1<<2) /* Input Source bit 2 mask. */ -#define CRC_SOURCE2_bp 2 /* Input Source bit 2 position. */ -#define CRC_SOURCE3_bm (1<<3) /* Input Source bit 3 mask. */ -#define CRC_SOURCE3_bp 3 /* Input Source bit 3 position. */ - -/* CRC.STATUS bit masks and bit positions */ -#define CRC_ZERO_bm 0x02 /* Zero detection bit mask. */ -#define CRC_ZERO_bp 1 /* Zero detection bit position. */ - -#define CRC_BUSY_bm 0x01 /* Busy bit mask. */ -#define CRC_BUSY_bp 0 /* Busy bit position. */ - -/* EDMA - Enhanced DMA Controller */ -/* EDMA.CTRL bit masks and bit positions */ -#define EDMA_ENABLE_bm 0x80 /* Enable bit mask. */ -#define EDMA_ENABLE_bp 7 /* Enable bit position. */ - -#define EDMA_RESET_bm 0x40 /* Software Reset bit mask. */ -#define EDMA_RESET_bp 6 /* Software Reset bit position. */ - -#define EDMA_CHMODE_gm 0x30 /* Channel Mode group mask. */ -#define EDMA_CHMODE_gp 4 /* Channel Mode group position. */ -#define EDMA_CHMODE0_bm (1<<4) /* Channel Mode bit 0 mask. */ -#define EDMA_CHMODE0_bp 4 /* Channel Mode bit 0 position. */ -#define EDMA_CHMODE1_bm (1<<5) /* Channel Mode bit 1 mask. */ -#define EDMA_CHMODE1_bp 5 /* Channel Mode bit 1 position. */ - -#define EDMA_DBUFMODE_gm 0x0C /* Double Buffer Mode group mask. */ -#define EDMA_DBUFMODE_gp 2 /* Double Buffer Mode group position. */ -#define EDMA_DBUFMODE0_bm (1<<2) /* Double Buffer Mode bit 0 mask. */ -#define EDMA_DBUFMODE0_bp 2 /* Double Buffer Mode bit 0 position. */ -#define EDMA_DBUFMODE1_bm (1<<3) /* Double Buffer Mode bit 1 mask. */ -#define EDMA_DBUFMODE1_bp 3 /* Double Buffer Mode bit 1 position. */ - -#define EDMA_PRIMODE_gm 0x03 /* Priority Mode group mask. */ -#define EDMA_PRIMODE_gp 0 /* Priority Mode group position. */ -#define EDMA_PRIMODE0_bm (1<<0) /* Priority Mode bit 0 mask. */ -#define EDMA_PRIMODE0_bp 0 /* Priority Mode bit 0 position. */ -#define EDMA_PRIMODE1_bm (1<<1) /* Priority Mode bit 1 mask. */ -#define EDMA_PRIMODE1_bp 1 /* Priority Mode bit 1 position. */ - -/* EDMA.INTFLAGS bit masks and bit positions */ -#define EDMA_CH3ERRIF_bm 0x80 /* Channel 3 Transaction Error Interrupt Flag bit mask. */ -#define EDMA_CH3ERRIF_bp 7 /* Channel 3 Transaction Error Interrupt Flag bit position. */ - -#define EDMA_CH2ERRIF_bm 0x40 /* Channel 2 Transaction Error Interrupt Flag bit mask. */ -#define EDMA_CH2ERRIF_bp 6 /* Channel 2 Transaction Error Interrupt Flag bit position. */ - -#define EDMA_CH1ERRIF_bm 0x20 /* Channel 1 Transaction Error Interrupt Flag bit mask. */ -#define EDMA_CH1ERRIF_bp 5 /* Channel 1 Transaction Error Interrupt Flag bit position. */ - -#define EDMA_CH0ERRIF_bm 0x10 /* Channel 0 Transaction Error Interrupt Flag bit mask. */ -#define EDMA_CH0ERRIF_bp 4 /* Channel 0 Transaction Error Interrupt Flag bit position. */ - -#define EDMA_CH3TRNFIF_bm 0x08 /* Channel 3 Transaction Complete Interrupt Flag bit mask. */ -#define EDMA_CH3TRNFIF_bp 3 /* Channel 3 Transaction Complete Interrupt Flag bit position. */ - -#define EDMA_CH2TRNFIF_bm 0x04 /* Channel 2 Transaction Complete Interrupt Flag bit mask. */ -#define EDMA_CH2TRNFIF_bp 2 /* Channel 2 Transaction Complete Interrupt Flag bit position. */ - -#define EDMA_CH1TRNFIF_bm 0x02 /* Channel 1 Transaction Complete Interrupt Flag bit mask. */ -#define EDMA_CH1TRNFIF_bp 1 /* Channel 1 Transaction Complete Interrupt Flag bit position. */ - -#define EDMA_CH0TRNFIF_bm 0x01 /* Channel 0 Transaction Complete Interrupt Flag bit mask. */ -#define EDMA_CH0TRNFIF_bp 0 /* Channel 0 Transaction Complete Interrupt Flag bit position. */ - -/* EDMA.STATUS bit masks and bit positions */ -#define EDMA_CH3BUSY_bm 0x80 /* Channel 3 Busy Flag bit mask. */ -#define EDMA_CH3BUSY_bp 7 /* Channel 3 Busy Flag bit position. */ - -#define EDMA_CH2BUSY_bm 0x40 /* Channel 2 Busy Flag bit mask. */ -#define EDMA_CH2BUSY_bp 6 /* Channel 2 Busy Flag bit position. */ - -#define EDMA_CH1BUSY_bm 0x20 /* Channel 1 Busy Flag bit mask. */ -#define EDMA_CH1BUSY_bp 5 /* Channel 1 Busy Flag bit position. */ - -#define EDMA_CH0BUSY_bm 0x10 /* Channel 0 Busy Flag bit mask. */ -#define EDMA_CH0BUSY_bp 4 /* Channel 0 Busy Flag bit position. */ - -#define EDMA_CH3PEND_bm 0x08 /* Channel 3 Pending Flag bit mask. */ -#define EDMA_CH3PEND_bp 3 /* Channel 3 Pending Flag bit position. */ - -#define EDMA_CH2PEND_bm 0x04 /* Channel 2 Pending Flag bit mask. */ -#define EDMA_CH2PEND_bp 2 /* Channel 2 Pending Flag bit position. */ - -#define EDMA_CH1PEND_bm 0x02 /* Channel 1 Pending Flag bit mask. */ -#define EDMA_CH1PEND_bp 1 /* Channel 1 Pending Flag bit position. */ - -#define EDMA_CH0PEND_bm 0x01 /* Channel 0 Pending Flag bit mask. */ -#define EDMA_CH0PEND_bp 0 /* Channel 0 Pending Flag bit position. */ - -/* EDMA_CH.CTRLA bit masks and bit positions */ -#define EDMA_CH_ENABLE_bm 0x80 /* Channel Enable bit mask. */ -#define EDMA_CH_ENABLE_bp 7 /* Channel Enable bit position. */ - -#define EDMA_CH_RESET_bm 0x40 /* Channel Software Reset bit mask. */ -#define EDMA_CH_RESET_bp 6 /* Channel Software Reset bit position. */ - -#define EDMA_CH_REPEAT_bm 0x20 /* Channel Repeat Mode bit mask. */ -#define EDMA_CH_REPEAT_bp 5 /* Channel Repeat Mode bit position. */ - -#define EDMA_CH_TRFREQ_bm 0x10 /* Channel Transfer Request bit mask. */ -#define EDMA_CH_TRFREQ_bp 4 /* Channel Transfer Request bit position. */ - -#define EDMA_CH_SINGLE_bm 0x04 /* Channel Single Shot Data Transfer bit mask. */ -#define EDMA_CH_SINGLE_bp 2 /* Channel Single Shot Data Transfer bit position. */ - -#define EDMA_CH_BURSTLEN_bm 0x01 /* Channel 2-bytes Burst Length bit mask. */ -#define EDMA_CH_BURSTLEN_bp 0 /* Channel 2-bytes Burst Length bit position. */ - -/* EDMA_CH.CTRLB bit masks and bit positions */ -#define EDMA_CH_CHBUSY_bm 0x80 /* Channel Block Transfer Busy bit mask. */ -#define EDMA_CH_CHBUSY_bp 7 /* Channel Block Transfer Busy bit position. */ - -#define EDMA_CH_CHPEND_bm 0x40 /* Channel Block Transfer Pending bit mask. */ -#define EDMA_CH_CHPEND_bp 6 /* Channel Block Transfer Pending bit position. */ - -#define EDMA_CH_ERRIF_bm 0x20 /* Channel Transaction Error Interrupt Flag bit mask. */ -#define EDMA_CH_ERRIF_bp 5 /* Channel Transaction Error Interrupt Flag bit position. */ - -#define EDMA_CH_TRNIF_bm 0x10 /* Channel Transaction Complete Interrup Flag bit mask. */ -#define EDMA_CH_TRNIF_bp 4 /* Channel Transaction Complete Interrup Flag bit position. */ - -#define EDMA_CH_ERRINTLVL_gm 0x0C /* Channel Transaction Error Interrupt Level group mask. */ -#define EDMA_CH_ERRINTLVL_gp 2 /* Channel Transaction Error Interrupt Level group position. */ -#define EDMA_CH_ERRINTLVL0_bm (1<<2) /* Channel Transaction Error Interrupt Level bit 0 mask. */ -#define EDMA_CH_ERRINTLVL0_bp 2 /* Channel Transaction Error Interrupt Level bit 0 position. */ -#define EDMA_CH_ERRINTLVL1_bm (1<<3) /* Channel Transaction Error Interrupt Level bit 1 mask. */ -#define EDMA_CH_ERRINTLVL1_bp 3 /* Channel Transaction Error Interrupt Level bit 1 position. */ - -#define EDMA_CH_TRNINTLVL_gm 0x03 /* Channel Transaction Complete Interrupt Level group mask. */ -#define EDMA_CH_TRNINTLVL_gp 0 /* Channel Transaction Complete Interrupt Level group position. */ -#define EDMA_CH_TRNINTLVL0_bm (1<<0) /* Channel Transaction Complete Interrupt Level bit 0 mask. */ -#define EDMA_CH_TRNINTLVL0_bp 0 /* Channel Transaction Complete Interrupt Level bit 0 position. */ -#define EDMA_CH_TRNINTLVL1_bm (1<<1) /* Channel Transaction Complete Interrupt Level bit 1 mask. */ -#define EDMA_CH_TRNINTLVL1_bp 1 /* Channel Transaction Complete Interrupt Level bit 1 position. */ - -/* EDMA_CH.ADDRCTRL bit masks and bit positions */ -#define EDMA_CH_RELOAD_gm 0x30 /* Memory Address Reload for Peripheral Ch., or Source Address Reload for Standard Ch. group mask. */ -#define EDMA_CH_RELOAD_gp 4 /* Memory Address Reload for Peripheral Ch., or Source Address Reload for Standard Ch. group position. */ -#define EDMA_CH_RELOAD0_bm (1<<4) /* Memory Address Reload for Peripheral Ch., or Source Address Reload for Standard Ch. bit 0 mask. */ -#define EDMA_CH_RELOAD0_bp 4 /* Memory Address Reload for Peripheral Ch., or Source Address Reload for Standard Ch. bit 0 position. */ -#define EDMA_CH_RELOAD1_bm (1<<5) /* Memory Address Reload for Peripheral Ch., or Source Address Reload for Standard Ch. bit 1 mask. */ -#define EDMA_CH_RELOAD1_bp 5 /* Memory Address Reload for Peripheral Ch., or Source Address Reload for Standard Ch. bit 1 position. */ - -#define EDMA_CH_DIR_gm 0x07 /* Memory Address Mode for Peripheral Ch., or Source Address Mode for Standard Ch. group mask. */ -#define EDMA_CH_DIR_gp 0 /* Memory Address Mode for Peripheral Ch., or Source Address Mode for Standard Ch. group position. */ -#define EDMA_CH_DIR0_bm (1<<0) /* Memory Address Mode for Peripheral Ch., or Source Address Mode for Standard Ch. bit 0 mask. */ -#define EDMA_CH_DIR0_bp 0 /* Memory Address Mode for Peripheral Ch., or Source Address Mode for Standard Ch. bit 0 position. */ -#define EDMA_CH_DIR1_bm (1<<1) /* Memory Address Mode for Peripheral Ch., or Source Address Mode for Standard Ch. bit 1 mask. */ -#define EDMA_CH_DIR1_bp 1 /* Memory Address Mode for Peripheral Ch., or Source Address Mode for Standard Ch. bit 1 position. */ -#define EDMA_CH_DIR2_bm (1<<2) /* Memory Address Mode for Peripheral Ch., or Source Address Mode for Standard Ch. bit 2 mask. */ -#define EDMA_CH_DIR2_bp 2 /* Memory Address Mode for Peripheral Ch., or Source Address Mode for Standard Ch. bit 2 position. */ - -/* EDMA_CH.DESTADDRCTRL bit masks and bit positions */ -#define EDMA_CH_DESTRELOAD_gm 0x30 /* Destination Address Reload for Standard Channels Only. group mask. */ -#define EDMA_CH_DESTRELOAD_gp 4 /* Destination Address Reload for Standard Channels Only. group position. */ -#define EDMA_CH_DESTRELOAD0_bm (1<<4) /* Destination Address Reload for Standard Channels Only. bit 0 mask. */ -#define EDMA_CH_DESTRELOAD0_bp 4 /* Destination Address Reload for Standard Channels Only. bit 0 position. */ -#define EDMA_CH_DESTRELOAD1_bm (1<<5) /* Destination Address Reload for Standard Channels Only. bit 1 mask. */ -#define EDMA_CH_DESTRELOAD1_bp 5 /* Destination Address Reload for Standard Channels Only. bit 1 position. */ - -#define EDMA_CH_DESTDIR_gm 0x07 /* Destination Address Mode for Standard Channels Only. group mask. */ -#define EDMA_CH_DESTDIR_gp 0 /* Destination Address Mode for Standard Channels Only. group position. */ -#define EDMA_CH_DESTDIR0_bm (1<<0) /* Destination Address Mode for Standard Channels Only. bit 0 mask. */ -#define EDMA_CH_DESTDIR0_bp 0 /* Destination Address Mode for Standard Channels Only. bit 0 position. */ -#define EDMA_CH_DESTDIR1_bm (1<<1) /* Destination Address Mode for Standard Channels Only. bit 1 mask. */ -#define EDMA_CH_DESTDIR1_bp 1 /* Destination Address Mode for Standard Channels Only. bit 1 position. */ -#define EDMA_CH_DESTDIR2_bm (1<<2) /* Destination Address Mode for Standard Channels Only. bit 2 mask. */ -#define EDMA_CH_DESTDIR2_bp 2 /* Destination Address Mode for Standard Channels Only. bit 2 position. */ - -/* EDMA_CH.TRIGSRC bit masks and bit positions */ -#define EDMA_CH_TRIGSRC_gm 0xFF /* Channel Trigger Source group mask. */ -#define EDMA_CH_TRIGSRC_gp 0 /* Channel Trigger Source group position. */ -#define EDMA_CH_TRIGSRC0_bm (1<<0) /* Channel Trigger Source bit 0 mask. */ -#define EDMA_CH_TRIGSRC0_bp 0 /* Channel Trigger Source bit 0 position. */ -#define EDMA_CH_TRIGSRC1_bm (1<<1) /* Channel Trigger Source bit 1 mask. */ -#define EDMA_CH_TRIGSRC1_bp 1 /* Channel Trigger Source bit 1 position. */ -#define EDMA_CH_TRIGSRC2_bm (1<<2) /* Channel Trigger Source bit 2 mask. */ -#define EDMA_CH_TRIGSRC2_bp 2 /* Channel Trigger Source bit 2 position. */ -#define EDMA_CH_TRIGSRC3_bm (1<<3) /* Channel Trigger Source bit 3 mask. */ -#define EDMA_CH_TRIGSRC3_bp 3 /* Channel Trigger Source bit 3 position. */ -#define EDMA_CH_TRIGSRC4_bm (1<<4) /* Channel Trigger Source bit 4 mask. */ -#define EDMA_CH_TRIGSRC4_bp 4 /* Channel Trigger Source bit 4 position. */ -#define EDMA_CH_TRIGSRC5_bm (1<<5) /* Channel Trigger Source bit 5 mask. */ -#define EDMA_CH_TRIGSRC5_bp 5 /* Channel Trigger Source bit 5 position. */ -#define EDMA_CH_TRIGSRC6_bm (1<<6) /* Channel Trigger Source bit 6 mask. */ -#define EDMA_CH_TRIGSRC6_bp 6 /* Channel Trigger Source bit 6 position. */ -#define EDMA_CH_TRIGSRC7_bm (1<<7) /* Channel Trigger Source bit 7 mask. */ -#define EDMA_CH_TRIGSRC7_bp 7 /* Channel Trigger Source bit 7 position. */ - -/* EVSYS - Event System */ -/* EVSYS.CH0MUX bit masks and bit positions */ -#define EVSYS_CHMUX_gm 0xFF /* Event Channel 0 Multiplexer group mask. */ -#define EVSYS_CHMUX_gp 0 /* Event Channel 0 Multiplexer group position. */ -#define EVSYS_CHMUX0_bm (1<<0) /* Event Channel 0 Multiplexer bit 0 mask. */ -#define EVSYS_CHMUX0_bp 0 /* Event Channel 0 Multiplexer bit 0 position. */ -#define EVSYS_CHMUX1_bm (1<<1) /* Event Channel 0 Multiplexer bit 1 mask. */ -#define EVSYS_CHMUX1_bp 1 /* Event Channel 0 Multiplexer bit 1 position. */ -#define EVSYS_CHMUX2_bm (1<<2) /* Event Channel 0 Multiplexer bit 2 mask. */ -#define EVSYS_CHMUX2_bp 2 /* Event Channel 0 Multiplexer bit 2 position. */ -#define EVSYS_CHMUX3_bm (1<<3) /* Event Channel 0 Multiplexer bit 3 mask. */ -#define EVSYS_CHMUX3_bp 3 /* Event Channel 0 Multiplexer bit 3 position. */ -#define EVSYS_CHMUX4_bm (1<<4) /* Event Channel 0 Multiplexer bit 4 mask. */ -#define EVSYS_CHMUX4_bp 4 /* Event Channel 0 Multiplexer bit 4 position. */ -#define EVSYS_CHMUX5_bm (1<<5) /* Event Channel 0 Multiplexer bit 5 mask. */ -#define EVSYS_CHMUX5_bp 5 /* Event Channel 0 Multiplexer bit 5 position. */ -#define EVSYS_CHMUX6_bm (1<<6) /* Event Channel 0 Multiplexer bit 6 mask. */ -#define EVSYS_CHMUX6_bp 6 /* Event Channel 0 Multiplexer bit 6 position. */ -#define EVSYS_CHMUX7_bm (1<<7) /* Event Channel 0 Multiplexer bit 7 mask. */ -#define EVSYS_CHMUX7_bp 7 /* Event Channel 0 Multiplexer bit 7 position. */ - -/* EVSYS.CH1MUX bit masks and bit positions */ -/* EVSYS_CHMUX Predefined. */ -/* EVSYS_CHMUX Predefined. */ - -/* EVSYS.CH2MUX bit masks and bit positions */ -/* EVSYS_CHMUX Predefined. */ -/* EVSYS_CHMUX Predefined. */ - -/* EVSYS.CH3MUX bit masks and bit positions */ -/* EVSYS_CHMUX Predefined. */ -/* EVSYS_CHMUX Predefined. */ - -/* EVSYS.CH4MUX bit masks and bit positions */ -/* EVSYS_CHMUX Predefined. */ -/* EVSYS_CHMUX Predefined. */ - -/* EVSYS.CH5MUX bit masks and bit positions */ -/* EVSYS_CHMUX Predefined. */ -/* EVSYS_CHMUX Predefined. */ - -/* EVSYS.CH6MUX bit masks and bit positions */ -/* EVSYS_CHMUX Predefined. */ -/* EVSYS_CHMUX Predefined. */ - -/* EVSYS.CH7MUX bit masks and bit positions */ -/* EVSYS_CHMUX Predefined. */ -/* EVSYS_CHMUX Predefined. */ - -/* EVSYS.CH0CTRL bit masks and bit positions */ -#define EVSYS_ROTARY_bm 0x80 /* Rotary Decoder Enable bit mask. */ -#define EVSYS_ROTARY_bp 7 /* Rotary Decoder Enable bit position. */ - -#define EVSYS_QDIRM_gm 0x60 /* Quadrature Decoder Index Recognition Mode group mask. */ -#define EVSYS_QDIRM_gp 5 /* Quadrature Decoder Index Recognition Mode group position. */ -#define EVSYS_QDIRM0_bm (1<<5) /* Quadrature Decoder Index Recognition Mode bit 0 mask. */ -#define EVSYS_QDIRM0_bp 5 /* Quadrature Decoder Index Recognition Mode bit 0 position. */ -#define EVSYS_QDIRM1_bm (1<<6) /* Quadrature Decoder Index Recognition Mode bit 1 mask. */ -#define EVSYS_QDIRM1_bp 6 /* Quadrature Decoder Index Recognition Mode bit 1 position. */ - -#define EVSYS_QDIEN_bm 0x10 /* Quadrature Decoder Index Enable bit mask. */ -#define EVSYS_QDIEN_bp 4 /* Quadrature Decoder Index Enable bit position. */ - -#define EVSYS_QDEN_bm 0x08 /* Quadrature Decoder Enable bit mask. */ -#define EVSYS_QDEN_bp 3 /* Quadrature Decoder Enable bit position. */ - -#define EVSYS_DIGFILT_gm 0x07 /* Digital Filter group mask. */ -#define EVSYS_DIGFILT_gp 0 /* Digital Filter group position. */ -#define EVSYS_DIGFILT0_bm (1<<0) /* Digital Filter bit 0 mask. */ -#define EVSYS_DIGFILT0_bp 0 /* Digital Filter bit 0 position. */ -#define EVSYS_DIGFILT1_bm (1<<1) /* Digital Filter bit 1 mask. */ -#define EVSYS_DIGFILT1_bp 1 /* Digital Filter bit 1 position. */ -#define EVSYS_DIGFILT2_bm (1<<2) /* Digital Filter bit 2 mask. */ -#define EVSYS_DIGFILT2_bp 2 /* Digital Filter bit 2 position. */ - -/* EVSYS.CH1CTRL bit masks and bit positions */ -/* EVSYS_DIGFILT Predefined. */ -/* EVSYS_DIGFILT Predefined. */ - -/* EVSYS.CH2CTRL bit masks and bit positions */ -/* EVSYS_DIGFILT Predefined. */ -/* EVSYS_DIGFILT Predefined. */ - -/* EVSYS.CH3CTRL bit masks and bit positions */ -/* EVSYS_DIGFILT Predefined. */ -/* EVSYS_DIGFILT Predefined. */ - -/* EVSYS.CH4CTRL bit masks and bit positions */ -/* EVSYS_DIGFILT Predefined. */ -/* EVSYS_DIGFILT Predefined. */ - -/* EVSYS.CH5CTRL bit masks and bit positions */ -/* EVSYS_DIGFILT Predefined. */ -/* EVSYS_DIGFILT Predefined. */ - -/* EVSYS.CH6CTRL bit masks and bit positions */ -/* EVSYS_DIGFILT Predefined. */ -/* EVSYS_DIGFILT Predefined. */ - -/* EVSYS.CH7CTRL bit masks and bit positions */ -/* EVSYS_DIGFILT Predefined. */ -/* EVSYS_DIGFILT Predefined. */ - -/* EVSYS.DFCTRL bit masks and bit positions */ -#define EVSYS_PRESCFILT_gm 0xF0 /* Prescaler Filter group mask. */ -#define EVSYS_PRESCFILT_gp 4 /* Prescaler Filter group position. */ -#define EVSYS_PRESCFILT0_bm (1<<4) /* Prescaler Filter bit 0 mask. */ -#define EVSYS_PRESCFILT0_bp 4 /* Prescaler Filter bit 0 position. */ -#define EVSYS_PRESCFILT1_bm (1<<5) /* Prescaler Filter bit 1 mask. */ -#define EVSYS_PRESCFILT1_bp 5 /* Prescaler Filter bit 1 position. */ -#define EVSYS_PRESCFILT2_bm (1<<6) /* Prescaler Filter bit 2 mask. */ -#define EVSYS_PRESCFILT2_bp 6 /* Prescaler Filter bit 2 position. */ -#define EVSYS_PRESCFILT3_bm (1<<7) /* Prescaler Filter bit 3 mask. */ -#define EVSYS_PRESCFILT3_bp 7 /* Prescaler Filter bit 3 position. */ - -#define EVSYS_FILTSEL_bm 0x08 /* Prescaler Filter Select bit mask. */ -#define EVSYS_FILTSEL_bp 3 /* Prescaler Filter Select bit position. */ - -#define EVSYS_PRESC_gm 0x07 /* Prescaler group mask. */ -#define EVSYS_PRESC_gp 0 /* Prescaler group position. */ -#define EVSYS_PRESC0_bm (1<<0) /* Prescaler bit 0 mask. */ -#define EVSYS_PRESC0_bp 0 /* Prescaler bit 0 position. */ -#define EVSYS_PRESC1_bm (1<<1) /* Prescaler bit 1 mask. */ -#define EVSYS_PRESC1_bp 1 /* Prescaler bit 1 position. */ -#define EVSYS_PRESC2_bm (1<<2) /* Prescaler bit 2 mask. */ -#define EVSYS_PRESC2_bp 2 /* Prescaler bit 2 position. */ - -/* NVM - Non Volatile Memory Controller */ -/* NVM.CMD bit masks and bit positions */ -#define NVM_CMD_gm 0x7F /* Command group mask. */ -#define NVM_CMD_gp 0 /* Command group position. */ -#define NVM_CMD0_bm (1<<0) /* Command bit 0 mask. */ -#define NVM_CMD0_bp 0 /* Command bit 0 position. */ -#define NVM_CMD1_bm (1<<1) /* Command bit 1 mask. */ -#define NVM_CMD1_bp 1 /* Command bit 1 position. */ -#define NVM_CMD2_bm (1<<2) /* Command bit 2 mask. */ -#define NVM_CMD2_bp 2 /* Command bit 2 position. */ -#define NVM_CMD3_bm (1<<3) /* Command bit 3 mask. */ -#define NVM_CMD3_bp 3 /* Command bit 3 position. */ -#define NVM_CMD4_bm (1<<4) /* Command bit 4 mask. */ -#define NVM_CMD4_bp 4 /* Command bit 4 position. */ -#define NVM_CMD5_bm (1<<5) /* Command bit 5 mask. */ -#define NVM_CMD5_bp 5 /* Command bit 5 position. */ -#define NVM_CMD6_bm (1<<6) /* Command bit 6 mask. */ -#define NVM_CMD6_bp 6 /* Command bit 6 position. */ - -/* NVM.CTRLA bit masks and bit positions */ -#define NVM_CMDEX_bm 0x01 /* Command Execute bit mask. */ -#define NVM_CMDEX_bp 0 /* Command Execute bit position. */ - -/* NVM.CTRLB bit masks and bit positions */ -#define NVM_EPRM_bm 0x02 /* EEPROM Power Reduction Enable bit mask. */ -#define NVM_EPRM_bp 1 /* EEPROM Power Reduction Enable bit position. */ - -#define NVM_SPMLOCK_bm 0x01 /* SPM Lock bit mask. */ -#define NVM_SPMLOCK_bp 0 /* SPM Lock bit position. */ - -/* NVM.INTCTRL bit masks and bit positions */ -#define NVM_SPMLVL_gm 0x0C /* SPM Interrupt Level group mask. */ -#define NVM_SPMLVL_gp 2 /* SPM Interrupt Level group position. */ -#define NVM_SPMLVL0_bm (1<<2) /* SPM Interrupt Level bit 0 mask. */ -#define NVM_SPMLVL0_bp 2 /* SPM Interrupt Level bit 0 position. */ -#define NVM_SPMLVL1_bm (1<<3) /* SPM Interrupt Level bit 1 mask. */ -#define NVM_SPMLVL1_bp 3 /* SPM Interrupt Level bit 1 position. */ - -#define NVM_EELVL_gm 0x03 /* EEPROM Interrupt Level group mask. */ -#define NVM_EELVL_gp 0 /* EEPROM Interrupt Level group position. */ -#define NVM_EELVL0_bm (1<<0) /* EEPROM Interrupt Level bit 0 mask. */ -#define NVM_EELVL0_bp 0 /* EEPROM Interrupt Level bit 0 position. */ -#define NVM_EELVL1_bm (1<<1) /* EEPROM Interrupt Level bit 1 mask. */ -#define NVM_EELVL1_bp 1 /* EEPROM Interrupt Level bit 1 position. */ - -/* NVM.STATUS bit masks and bit positions */ -#define NVM_NVMBUSY_bm 0x80 /* Non-volatile Memory Busy bit mask. */ -#define NVM_NVMBUSY_bp 7 /* Non-volatile Memory Busy bit position. */ - -#define NVM_FBUSY_bm 0x40 /* Flash Memory Busy bit mask. */ -#define NVM_FBUSY_bp 6 /* Flash Memory Busy bit position. */ - -#define NVM_EELOAD_bm 0x02 /* EEPROM Page Buffer Active Loading bit mask. */ -#define NVM_EELOAD_bp 1 /* EEPROM Page Buffer Active Loading bit position. */ - -#define NVM_FLOAD_bm 0x01 /* Flash Page Buffer Active Loading bit mask. */ -#define NVM_FLOAD_bp 0 /* Flash Page Buffer Active Loading bit position. */ - -/* NVM.LOCKBITS bit masks and bit positions */ -#define NVM_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ -#define NVM_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ -#define NVM_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ -#define NVM_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ -#define NVM_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ -#define NVM_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ - -#define NVM_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ -#define NVM_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ -#define NVM_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ -#define NVM_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ -#define NVM_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ -#define NVM_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ - -#define NVM_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ -#define NVM_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ -#define NVM_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ -#define NVM_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ -#define NVM_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ -#define NVM_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ - -#define NVM_LB_gm 0x03 /* Lock Bits group mask. */ -#define NVM_LB_gp 0 /* Lock Bits group position. */ -#define NVM_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ -#define NVM_LB0_bp 0 /* Lock Bits bit 0 position. */ -#define NVM_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ -#define NVM_LB1_bp 1 /* Lock Bits bit 1 position. */ - -/* ADC - Analog/Digital Converter */ -/* ADC_CH.CTRL bit masks and bit positions */ -#define ADC_CH_START_bm 0x80 /* Channel Start Conversion bit mask. */ -#define ADC_CH_START_bp 7 /* Channel Start Conversion bit position. */ - -#define ADC_CH_GAIN_gm 0x1C /* Gain Factor group mask. */ -#define ADC_CH_GAIN_gp 2 /* Gain Factor group position. */ -#define ADC_CH_GAIN0_bm (1<<2) /* Gain Factor bit 0 mask. */ -#define ADC_CH_GAIN0_bp 2 /* Gain Factor bit 0 position. */ -#define ADC_CH_GAIN1_bm (1<<3) /* Gain Factor bit 1 mask. */ -#define ADC_CH_GAIN1_bp 3 /* Gain Factor bit 1 position. */ -#define ADC_CH_GAIN2_bm (1<<4) /* Gain Factor bit 2 mask. */ -#define ADC_CH_GAIN2_bp 4 /* Gain Factor bit 2 position. */ - -#define ADC_CH_INPUTMODE_gm 0x03 /* Input Mode Select group mask. */ -#define ADC_CH_INPUTMODE_gp 0 /* Input Mode Select group position. */ -#define ADC_CH_INPUTMODE0_bm (1<<0) /* Input Mode Select bit 0 mask. */ -#define ADC_CH_INPUTMODE0_bp 0 /* Input Mode Select bit 0 position. */ -#define ADC_CH_INPUTMODE1_bm (1<<1) /* Input Mode Select bit 1 mask. */ -#define ADC_CH_INPUTMODE1_bp 1 /* Input Mode Select bit 1 position. */ - -/* ADC_CH.MUXCTRL bit masks and bit positions */ -#define ADC_CH_MUXPOS_gm 0x78 /* MUX selection on Positive ADC Input group mask. */ -#define ADC_CH_MUXPOS_gp 3 /* MUX selection on Positive ADC Input group position. */ -#define ADC_CH_MUXPOS0_bm (1<<3) /* MUX selection on Positive ADC Input bit 0 mask. */ -#define ADC_CH_MUXPOS0_bp 3 /* MUX selection on Positive ADC Input bit 0 position. */ -#define ADC_CH_MUXPOS1_bm (1<<4) /* MUX selection on Positive ADC Input bit 1 mask. */ -#define ADC_CH_MUXPOS1_bp 4 /* MUX selection on Positive ADC Input bit 1 position. */ -#define ADC_CH_MUXPOS2_bm (1<<5) /* MUX selection on Positive ADC Input bit 2 mask. */ -#define ADC_CH_MUXPOS2_bp 5 /* MUX selection on Positive ADC Input bit 2 position. */ -#define ADC_CH_MUXPOS3_bm (1<<6) /* MUX selection on Positive ADC Input bit 3 mask. */ -#define ADC_CH_MUXPOS3_bp 6 /* MUX selection on Positive ADC Input bit 3 position. */ - -#define ADC_CH_MUXINT_gm 0x78 /* MUX selection on Internal ADC Input group mask. */ -#define ADC_CH_MUXINT_gp 3 /* MUX selection on Internal ADC Input group position. */ -#define ADC_CH_MUXINT0_bm (1<<3) /* MUX selection on Internal ADC Input bit 0 mask. */ -#define ADC_CH_MUXINT0_bp 3 /* MUX selection on Internal ADC Input bit 0 position. */ -#define ADC_CH_MUXINT1_bm (1<<4) /* MUX selection on Internal ADC Input bit 1 mask. */ -#define ADC_CH_MUXINT1_bp 4 /* MUX selection on Internal ADC Input bit 1 position. */ -#define ADC_CH_MUXINT2_bm (1<<5) /* MUX selection on Internal ADC Input bit 2 mask. */ -#define ADC_CH_MUXINT2_bp 5 /* MUX selection on Internal ADC Input bit 2 position. */ -#define ADC_CH_MUXINT3_bm (1<<6) /* MUX selection on Internal ADC Input bit 3 mask. */ -#define ADC_CH_MUXINT3_bp 6 /* MUX selection on Internal ADC Input bit 3 position. */ - -#define ADC_CH_MUXNEG_gm 0x03 /* MUX selection on Negative ADC Input group mask. */ -#define ADC_CH_MUXNEG_gp 0 /* MUX selection on Negative ADC Input group position. */ -#define ADC_CH_MUXNEG0_bm (1<<0) /* MUX selection on Negative ADC Input bit 0 mask. */ -#define ADC_CH_MUXNEG0_bp 0 /* MUX selection on Negative ADC Input bit 0 position. */ -#define ADC_CH_MUXNEG1_bm (1<<1) /* MUX selection on Negative ADC Input bit 1 mask. */ -#define ADC_CH_MUXNEG1_bp 1 /* MUX selection on Negative ADC Input bit 1 position. */ - -#define ADC_CH_MUXNEGL_gm 0x03 /* MUX selection on Negative ADC Input Gain on 4 LSB pins group mask. */ -#define ADC_CH_MUXNEGL_gp 0 /* MUX selection on Negative ADC Input Gain on 4 LSB pins group position. */ -#define ADC_CH_MUXNEGL0_bm (1<<0) /* MUX selection on Negative ADC Input Gain on 4 LSB pins bit 0 mask. */ -#define ADC_CH_MUXNEGL0_bp 0 /* MUX selection on Negative ADC Input Gain on 4 LSB pins bit 0 position. */ -#define ADC_CH_MUXNEGL1_bm (1<<1) /* MUX selection on Negative ADC Input Gain on 4 LSB pins bit 1 mask. */ -#define ADC_CH_MUXNEGL1_bp 1 /* MUX selection on Negative ADC Input Gain on 4 LSB pins bit 1 position. */ - -#define ADC_CH_MUXNEGH_gm 0x03 /* MUX selection on Negative ADC Input Gain on 4 MSB pins group mask. */ -#define ADC_CH_MUXNEGH_gp 0 /* MUX selection on Negative ADC Input Gain on 4 MSB pins group position. */ -#define ADC_CH_MUXNEGH0_bm (1<<0) /* MUX selection on Negative ADC Input Gain on 4 MSB pins bit 0 mask. */ -#define ADC_CH_MUXNEGH0_bp 0 /* MUX selection on Negative ADC Input Gain on 4 MSB pins bit 0 position. */ -#define ADC_CH_MUXNEGH1_bm (1<<1) /* MUX selection on Negative ADC Input Gain on 4 MSB pins bit 1 mask. */ -#define ADC_CH_MUXNEGH1_bp 1 /* MUX selection on Negative ADC Input Gain on 4 MSB pins bit 1 position. */ - -/* ADC_CH.INTCTRL bit masks and bit positions */ -#define ADC_CH_INTMODE_gm 0x0C /* Interrupt Mode group mask. */ -#define ADC_CH_INTMODE_gp 2 /* Interrupt Mode group position. */ -#define ADC_CH_INTMODE0_bm (1<<2) /* Interrupt Mode bit 0 mask. */ -#define ADC_CH_INTMODE0_bp 2 /* Interrupt Mode bit 0 position. */ -#define ADC_CH_INTMODE1_bm (1<<3) /* Interrupt Mode bit 1 mask. */ -#define ADC_CH_INTMODE1_bp 3 /* Interrupt Mode bit 1 position. */ - -#define ADC_CH_INTLVL_gm 0x03 /* Interrupt Level group mask. */ -#define ADC_CH_INTLVL_gp 0 /* Interrupt Level group position. */ -#define ADC_CH_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */ -#define ADC_CH_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */ -#define ADC_CH_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ -#define ADC_CH_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */ - -/* ADC_CH.INTFLAGS bit masks and bit positions */ -#define ADC_CH_IF_bm 0x01 /* Channel Interrupt Flag bit mask. */ -#define ADC_CH_IF_bp 0 /* Channel Interrupt Flag bit position. */ - -/* ADC_CH.SCAN bit masks and bit positions */ -#define ADC_CH_INPUTOFFSET_gm 0xF0 /* Positive MUX Setting Offset group mask. */ -#define ADC_CH_INPUTOFFSET_gp 4 /* Positive MUX Setting Offset group position. */ -#define ADC_CH_INPUTOFFSET0_bm (1<<4) /* Positive MUX Setting Offset bit 0 mask. */ -#define ADC_CH_INPUTOFFSET0_bp 4 /* Positive MUX Setting Offset bit 0 position. */ -#define ADC_CH_INPUTOFFSET1_bm (1<<5) /* Positive MUX Setting Offset bit 1 mask. */ -#define ADC_CH_INPUTOFFSET1_bp 5 /* Positive MUX Setting Offset bit 1 position. */ -#define ADC_CH_INPUTOFFSET2_bm (1<<6) /* Positive MUX Setting Offset bit 2 mask. */ -#define ADC_CH_INPUTOFFSET2_bp 6 /* Positive MUX Setting Offset bit 2 position. */ -#define ADC_CH_INPUTOFFSET3_bm (1<<7) /* Positive MUX Setting Offset bit 3 mask. */ -#define ADC_CH_INPUTOFFSET3_bp 7 /* Positive MUX Setting Offset bit 3 position. */ - -#define ADC_CH_INPUTSCAN_gm 0x0F /* Number of Channels Included in Scan group mask. */ -#define ADC_CH_INPUTSCAN_gp 0 /* Number of Channels Included in Scan group position. */ -#define ADC_CH_INPUTSCAN0_bm (1<<0) /* Number of Channels Included in Scan bit 0 mask. */ -#define ADC_CH_INPUTSCAN0_bp 0 /* Number of Channels Included in Scan bit 0 position. */ -#define ADC_CH_INPUTSCAN1_bm (1<<1) /* Number of Channels Included in Scan bit 1 mask. */ -#define ADC_CH_INPUTSCAN1_bp 1 /* Number of Channels Included in Scan bit 1 position. */ -#define ADC_CH_INPUTSCAN2_bm (1<<2) /* Number of Channels Included in Scan bit 2 mask. */ -#define ADC_CH_INPUTSCAN2_bp 2 /* Number of Channels Included in Scan bit 2 position. */ -#define ADC_CH_INPUTSCAN3_bm (1<<3) /* Number of Channels Included in Scan bit 3 mask. */ -#define ADC_CH_INPUTSCAN3_bp 3 /* Number of Channels Included in Scan bit 3 position. */ - -/* ADC_CH.CORRCTRL bit masks and bit positions */ -#define ADC_CH_CORREN_bm 0x01 /* Correction Enable bit mask. */ -#define ADC_CH_CORREN_bp 0 /* Correction Enable bit position. */ - -/* ADC_CH.OFFSETCORR1 bit masks and bit positions */ -#define ADC_CH_OFFSETCORR_gm 0x0F /* Offset Correction Byte 1 group mask. */ -#define ADC_CH_OFFSETCORR_gp 0 /* Offset Correction Byte 1 group position. */ -#define ADC_CH_OFFSETCORR0_bm (1<<0) /* Offset Correction Byte 1 bit 0 mask. */ -#define ADC_CH_OFFSETCORR0_bp 0 /* Offset Correction Byte 1 bit 0 position. */ -#define ADC_CH_OFFSETCORR1_bm (1<<1) /* Offset Correction Byte 1 bit 1 mask. */ -#define ADC_CH_OFFSETCORR1_bp 1 /* Offset Correction Byte 1 bit 1 position. */ -#define ADC_CH_OFFSETCORR2_bm (1<<2) /* Offset Correction Byte 1 bit 2 mask. */ -#define ADC_CH_OFFSETCORR2_bp 2 /* Offset Correction Byte 1 bit 2 position. */ -#define ADC_CH_OFFSETCORR3_bm (1<<3) /* Offset Correction Byte 1 bit 3 mask. */ -#define ADC_CH_OFFSETCORR3_bp 3 /* Offset Correction Byte 1 bit 3 position. */ - -/* ADC_CH.GAINCORR1 bit masks and bit positions */ -#define ADC_CH_GAINCORR_gm 0x0F /* Gain Correction Byte 1 group mask. */ -#define ADC_CH_GAINCORR_gp 0 /* Gain Correction Byte 1 group position. */ -#define ADC_CH_GAINCORR0_bm (1<<0) /* Gain Correction Byte 1 bit 0 mask. */ -#define ADC_CH_GAINCORR0_bp 0 /* Gain Correction Byte 1 bit 0 position. */ -#define ADC_CH_GAINCORR1_bm (1<<1) /* Gain Correction Byte 1 bit 1 mask. */ -#define ADC_CH_GAINCORR1_bp 1 /* Gain Correction Byte 1 bit 1 position. */ -#define ADC_CH_GAINCORR2_bm (1<<2) /* Gain Correction Byte 1 bit 2 mask. */ -#define ADC_CH_GAINCORR2_bp 2 /* Gain Correction Byte 1 bit 2 position. */ -#define ADC_CH_GAINCORR3_bm (1<<3) /* Gain Correction Byte 1 bit 3 mask. */ -#define ADC_CH_GAINCORR3_bp 3 /* Gain Correction Byte 1 bit 3 position. */ - -/* ADC_CH.AVGCTRL bit masks and bit positions */ -#define ADC_CH_RIGHTSHIFT_gm 0x70 /* Right Shift group mask. */ -#define ADC_CH_RIGHTSHIFT_gp 4 /* Right Shift group position. */ -#define ADC_CH_RIGHTSHIFT0_bm (1<<4) /* Right Shift bit 0 mask. */ -#define ADC_CH_RIGHTSHIFT0_bp 4 /* Right Shift bit 0 position. */ -#define ADC_CH_RIGHTSHIFT1_bm (1<<5) /* Right Shift bit 1 mask. */ -#define ADC_CH_RIGHTSHIFT1_bp 5 /* Right Shift bit 1 position. */ -#define ADC_CH_RIGHTSHIFT2_bm (1<<6) /* Right Shift bit 2 mask. */ -#define ADC_CH_RIGHTSHIFT2_bp 6 /* Right Shift bit 2 position. */ - -#define ADC_CH_SAMPNUM_gm 0x0F /* Averaged Number of Samples group mask. */ -#define ADC_CH_SAMPNUM_gp 0 /* Averaged Number of Samples group position. */ -#define ADC_CH_SAMPNUM0_bm (1<<0) /* Averaged Number of Samples bit 0 mask. */ -#define ADC_CH_SAMPNUM0_bp 0 /* Averaged Number of Samples bit 0 position. */ -#define ADC_CH_SAMPNUM1_bm (1<<1) /* Averaged Number of Samples bit 1 mask. */ -#define ADC_CH_SAMPNUM1_bp 1 /* Averaged Number of Samples bit 1 position. */ -#define ADC_CH_SAMPNUM2_bm (1<<2) /* Averaged Number of Samples bit 2 mask. */ -#define ADC_CH_SAMPNUM2_bp 2 /* Averaged Number of Samples bit 2 position. */ -#define ADC_CH_SAMPNUM3_bm (1<<3) /* Averaged Number of Samples bit 3 mask. */ -#define ADC_CH_SAMPNUM3_bp 3 /* Averaged Number of Samples bit 3 position. */ - -/* ADC.CTRLA bit masks and bit positions */ -#define ADC_START_bm 0x04 /* Start Conversion bit mask. */ -#define ADC_START_bp 2 /* Start Conversion bit position. */ - -#define ADC_FLUSH_bm 0x02 /* ADC Flush bit mask. */ -#define ADC_FLUSH_bp 1 /* ADC Flush bit position. */ - -#define ADC_ENABLE_bm 0x01 /* Enable ADC bit mask. */ -#define ADC_ENABLE_bp 0 /* Enable ADC bit position. */ - -/* ADC.CTRLB bit masks and bit positions */ -#define ADC_CURRLIMIT_gm 0x60 /* Current Limitation group mask. */ -#define ADC_CURRLIMIT_gp 5 /* Current Limitation group position. */ -#define ADC_CURRLIMIT0_bm (1<<5) /* Current Limitation bit 0 mask. */ -#define ADC_CURRLIMIT0_bp 5 /* Current Limitation bit 0 position. */ -#define ADC_CURRLIMIT1_bm (1<<6) /* Current Limitation bit 1 mask. */ -#define ADC_CURRLIMIT1_bp 6 /* Current Limitation bit 1 position. */ - -#define ADC_CONMODE_bm 0x10 /* Conversion Mode bit mask. */ -#define ADC_CONMODE_bp 4 /* Conversion Mode bit position. */ - -#define ADC_FREERUN_bm 0x08 /* Free Running Mode Enable bit mask. */ -#define ADC_FREERUN_bp 3 /* Free Running Mode Enable bit position. */ - -#define ADC_RESOLUTION_gm 0x06 /* Result Resolution group mask. */ -#define ADC_RESOLUTION_gp 1 /* Result Resolution group position. */ -#define ADC_RESOLUTION0_bm (1<<1) /* Result Resolution bit 0 mask. */ -#define ADC_RESOLUTION0_bp 1 /* Result Resolution bit 0 position. */ -#define ADC_RESOLUTION1_bm (1<<2) /* Result Resolution bit 1 mask. */ -#define ADC_RESOLUTION1_bp 2 /* Result Resolution bit 1 position. */ - -/* ADC.REFCTRL bit masks and bit positions */ -#define ADC_REFSEL_gm 0x70 /* Reference Selection group mask. */ -#define ADC_REFSEL_gp 4 /* Reference Selection group position. */ -#define ADC_REFSEL0_bm (1<<4) /* Reference Selection bit 0 mask. */ -#define ADC_REFSEL0_bp 4 /* Reference Selection bit 0 position. */ -#define ADC_REFSEL1_bm (1<<5) /* Reference Selection bit 1 mask. */ -#define ADC_REFSEL1_bp 5 /* Reference Selection bit 1 position. */ -#define ADC_REFSEL2_bm (1<<6) /* Reference Selection bit 2 mask. */ -#define ADC_REFSEL2_bp 6 /* Reference Selection bit 2 position. */ - -#define ADC_BANDGAP_bm 0x02 /* Bandgap enable bit mask. */ -#define ADC_BANDGAP_bp 1 /* Bandgap enable bit position. */ - -#define ADC_TEMPREF_bm 0x01 /* Temperature Reference Enable bit mask. */ -#define ADC_TEMPREF_bp 0 /* Temperature Reference Enable bit position. */ - -/* ADC.EVCTRL bit masks and bit positions */ -#define ADC_EVSEL_gm 0x38 /* Event Input Select group mask. */ -#define ADC_EVSEL_gp 3 /* Event Input Select group position. */ -#define ADC_EVSEL0_bm (1<<3) /* Event Input Select bit 0 mask. */ -#define ADC_EVSEL0_bp 3 /* Event Input Select bit 0 position. */ -#define ADC_EVSEL1_bm (1<<4) /* Event Input Select bit 1 mask. */ -#define ADC_EVSEL1_bp 4 /* Event Input Select bit 1 position. */ -#define ADC_EVSEL2_bm (1<<5) /* Event Input Select bit 2 mask. */ -#define ADC_EVSEL2_bp 5 /* Event Input Select bit 2 position. */ - -#define ADC_EVACT_gm 0x07 /* Event Action Select group mask. */ -#define ADC_EVACT_gp 0 /* Event Action Select group position. */ -#define ADC_EVACT0_bm (1<<0) /* Event Action Select bit 0 mask. */ -#define ADC_EVACT0_bp 0 /* Event Action Select bit 0 position. */ -#define ADC_EVACT1_bm (1<<1) /* Event Action Select bit 1 mask. */ -#define ADC_EVACT1_bp 1 /* Event Action Select bit 1 position. */ -#define ADC_EVACT2_bm (1<<2) /* Event Action Select bit 2 mask. */ -#define ADC_EVACT2_bp 2 /* Event Action Select bit 2 position. */ - -/* ADC.PRESCALER bit masks and bit positions */ -#define ADC_PRESCALER_gm 0x07 /* Clock Prescaler Selection group mask. */ -#define ADC_PRESCALER_gp 0 /* Clock Prescaler Selection group position. */ -#define ADC_PRESCALER0_bm (1<<0) /* Clock Prescaler Selection bit 0 mask. */ -#define ADC_PRESCALER0_bp 0 /* Clock Prescaler Selection bit 0 position. */ -#define ADC_PRESCALER1_bm (1<<1) /* Clock Prescaler Selection bit 1 mask. */ -#define ADC_PRESCALER1_bp 1 /* Clock Prescaler Selection bit 1 position. */ -#define ADC_PRESCALER2_bm (1<<2) /* Clock Prescaler Selection bit 2 mask. */ -#define ADC_PRESCALER2_bp 2 /* Clock Prescaler Selection bit 2 position. */ - -/* ADC.INTFLAGS bit masks and bit positions */ -#define ADC_CH0IF_bm 0x01 /* Channel 0 Interrupt Flag bit mask. */ -#define ADC_CH0IF_bp 0 /* Channel 0 Interrupt Flag bit position. */ - -/* ADC.SAMPCTRL bit masks and bit positions */ -#define ADC_SAMPVAL_gm 0x3F /* Sampling time control register group mask. */ -#define ADC_SAMPVAL_gp 0 /* Sampling time control register group position. */ -#define ADC_SAMPVAL0_bm (1<<0) /* Sampling time control register bit 0 mask. */ -#define ADC_SAMPVAL0_bp 0 /* Sampling time control register bit 0 position. */ -#define ADC_SAMPVAL1_bm (1<<1) /* Sampling time control register bit 1 mask. */ -#define ADC_SAMPVAL1_bp 1 /* Sampling time control register bit 1 position. */ -#define ADC_SAMPVAL2_bm (1<<2) /* Sampling time control register bit 2 mask. */ -#define ADC_SAMPVAL2_bp 2 /* Sampling time control register bit 2 position. */ -#define ADC_SAMPVAL3_bm (1<<3) /* Sampling time control register bit 3 mask. */ -#define ADC_SAMPVAL3_bp 3 /* Sampling time control register bit 3 position. */ -#define ADC_SAMPVAL4_bm (1<<4) /* Sampling time control register bit 4 mask. */ -#define ADC_SAMPVAL4_bp 4 /* Sampling time control register bit 4 position. */ -#define ADC_SAMPVAL5_bm (1<<5) /* Sampling time control register bit 5 mask. */ -#define ADC_SAMPVAL5_bp 5 /* Sampling time control register bit 5 position. */ - -/* DAC - Digital/Analog Converter */ -/* DAC.CTRLA bit masks and bit positions */ -#define DAC_IDOEN_bm 0x10 /* Internal Output Enable bit mask. */ -#define DAC_IDOEN_bp 4 /* Internal Output Enable bit position. */ - -#define DAC_CH1EN_bm 0x08 /* Channel 1 Output Enable bit mask. */ -#define DAC_CH1EN_bp 3 /* Channel 1 Output Enable bit position. */ - -#define DAC_CH0EN_bm 0x04 /* Channel 0 Output Enable bit mask. */ -#define DAC_CH0EN_bp 2 /* Channel 0 Output Enable bit position. */ - -#define DAC_LPMODE_bm 0x02 /* Low Power Mode bit mask. */ -#define DAC_LPMODE_bp 1 /* Low Power Mode bit position. */ - -#define DAC_ENABLE_bm 0x01 /* Enable bit mask. */ -#define DAC_ENABLE_bp 0 /* Enable bit position. */ - -/* DAC.CTRLB bit masks and bit positions */ -#define DAC_CHSEL_gm 0x60 /* Channel Select group mask. */ -#define DAC_CHSEL_gp 5 /* Channel Select group position. */ -#define DAC_CHSEL0_bm (1<<5) /* Channel Select bit 0 mask. */ -#define DAC_CHSEL0_bp 5 /* Channel Select bit 0 position. */ -#define DAC_CHSEL1_bm (1<<6) /* Channel Select bit 1 mask. */ -#define DAC_CHSEL1_bp 6 /* Channel Select bit 1 position. */ - -#define DAC_CH1TRIG_bm 0x02 /* Channel 1 Event Trig Enable bit mask. */ -#define DAC_CH1TRIG_bp 1 /* Channel 1 Event Trig Enable bit position. */ - -#define DAC_CH0TRIG_bm 0x01 /* Channel 0 Event Trig Enable bit mask. */ -#define DAC_CH0TRIG_bp 0 /* Channel 0 Event Trig Enable bit position. */ - -/* DAC.CTRLC bit masks and bit positions */ -#define DAC_REFSEL_gm 0x18 /* Reference Select group mask. */ -#define DAC_REFSEL_gp 3 /* Reference Select group position. */ -#define DAC_REFSEL0_bm (1<<3) /* Reference Select bit 0 mask. */ -#define DAC_REFSEL0_bp 3 /* Reference Select bit 0 position. */ -#define DAC_REFSEL1_bm (1<<4) /* Reference Select bit 1 mask. */ -#define DAC_REFSEL1_bp 4 /* Reference Select bit 1 position. */ - -#define DAC_LEFTADJ_bm 0x01 /* Left-adjust Result bit mask. */ -#define DAC_LEFTADJ_bp 0 /* Left-adjust Result bit position. */ - -/* DAC.EVCTRL bit masks and bit positions */ -#define DAC_EVSPLIT_bm 0x08 /* Separate Event Channel Input for Channel 1 bit mask. */ -#define DAC_EVSPLIT_bp 3 /* Separate Event Channel Input for Channel 1 bit position. */ - -#define DAC_EVSEL_gm 0x07 /* Event Input Selection group mask. */ -#define DAC_EVSEL_gp 0 /* Event Input Selection group position. */ -#define DAC_EVSEL0_bm (1<<0) /* Event Input Selection bit 0 mask. */ -#define DAC_EVSEL0_bp 0 /* Event Input Selection bit 0 position. */ -#define DAC_EVSEL1_bm (1<<1) /* Event Input Selection bit 1 mask. */ -#define DAC_EVSEL1_bp 1 /* Event Input Selection bit 1 position. */ -#define DAC_EVSEL2_bm (1<<2) /* Event Input Selection bit 2 mask. */ -#define DAC_EVSEL2_bp 2 /* Event Input Selection bit 2 position. */ - -/* DAC.STATUS bit masks and bit positions */ -#define DAC_CH1DRE_bm 0x02 /* Channel 1 Data Register Empty bit mask. */ -#define DAC_CH1DRE_bp 1 /* Channel 1 Data Register Empty bit position. */ - -#define DAC_CH0DRE_bm 0x01 /* Channel 0 Data Register Empty bit mask. */ -#define DAC_CH0DRE_bp 0 /* Channel 0 Data Register Empty bit position. */ - -/* DAC.CH0GAINCAL bit masks and bit positions */ -#define DAC_CH0GAINCAL_gm 0x7F /* Gain Calibration group mask. */ -#define DAC_CH0GAINCAL_gp 0 /* Gain Calibration group position. */ -#define DAC_CH0GAINCAL0_bm (1<<0) /* Gain Calibration bit 0 mask. */ -#define DAC_CH0GAINCAL0_bp 0 /* Gain Calibration bit 0 position. */ -#define DAC_CH0GAINCAL1_bm (1<<1) /* Gain Calibration bit 1 mask. */ -#define DAC_CH0GAINCAL1_bp 1 /* Gain Calibration bit 1 position. */ -#define DAC_CH0GAINCAL2_bm (1<<2) /* Gain Calibration bit 2 mask. */ -#define DAC_CH0GAINCAL2_bp 2 /* Gain Calibration bit 2 position. */ -#define DAC_CH0GAINCAL3_bm (1<<3) /* Gain Calibration bit 3 mask. */ -#define DAC_CH0GAINCAL3_bp 3 /* Gain Calibration bit 3 position. */ -#define DAC_CH0GAINCAL4_bm (1<<4) /* Gain Calibration bit 4 mask. */ -#define DAC_CH0GAINCAL4_bp 4 /* Gain Calibration bit 4 position. */ -#define DAC_CH0GAINCAL5_bm (1<<5) /* Gain Calibration bit 5 mask. */ -#define DAC_CH0GAINCAL5_bp 5 /* Gain Calibration bit 5 position. */ -#define DAC_CH0GAINCAL6_bm (1<<6) /* Gain Calibration bit 6 mask. */ -#define DAC_CH0GAINCAL6_bp 6 /* Gain Calibration bit 6 position. */ - -/* DAC.CH0OFFSETCAL bit masks and bit positions */ -#define DAC_CH0OFFSETCAL_gm 0x7F /* Offset Calibration group mask. */ -#define DAC_CH0OFFSETCAL_gp 0 /* Offset Calibration group position. */ -#define DAC_CH0OFFSETCAL0_bm (1<<0) /* Offset Calibration bit 0 mask. */ -#define DAC_CH0OFFSETCAL0_bp 0 /* Offset Calibration bit 0 position. */ -#define DAC_CH0OFFSETCAL1_bm (1<<1) /* Offset Calibration bit 1 mask. */ -#define DAC_CH0OFFSETCAL1_bp 1 /* Offset Calibration bit 1 position. */ -#define DAC_CH0OFFSETCAL2_bm (1<<2) /* Offset Calibration bit 2 mask. */ -#define DAC_CH0OFFSETCAL2_bp 2 /* Offset Calibration bit 2 position. */ -#define DAC_CH0OFFSETCAL3_bm (1<<3) /* Offset Calibration bit 3 mask. */ -#define DAC_CH0OFFSETCAL3_bp 3 /* Offset Calibration bit 3 position. */ -#define DAC_CH0OFFSETCAL4_bm (1<<4) /* Offset Calibration bit 4 mask. */ -#define DAC_CH0OFFSETCAL4_bp 4 /* Offset Calibration bit 4 position. */ -#define DAC_CH0OFFSETCAL5_bm (1<<5) /* Offset Calibration bit 5 mask. */ -#define DAC_CH0OFFSETCAL5_bp 5 /* Offset Calibration bit 5 position. */ -#define DAC_CH0OFFSETCAL6_bm (1<<6) /* Offset Calibration bit 6 mask. */ -#define DAC_CH0OFFSETCAL6_bp 6 /* Offset Calibration bit 6 position. */ - -/* DAC.CH1GAINCAL bit masks and bit positions */ -#define DAC_CH1GAINCAL_gm 0x7F /* Gain Calibration group mask. */ -#define DAC_CH1GAINCAL_gp 0 /* Gain Calibration group position. */ -#define DAC_CH1GAINCAL0_bm (1<<0) /* Gain Calibration bit 0 mask. */ -#define DAC_CH1GAINCAL0_bp 0 /* Gain Calibration bit 0 position. */ -#define DAC_CH1GAINCAL1_bm (1<<1) /* Gain Calibration bit 1 mask. */ -#define DAC_CH1GAINCAL1_bp 1 /* Gain Calibration bit 1 position. */ -#define DAC_CH1GAINCAL2_bm (1<<2) /* Gain Calibration bit 2 mask. */ -#define DAC_CH1GAINCAL2_bp 2 /* Gain Calibration bit 2 position. */ -#define DAC_CH1GAINCAL3_bm (1<<3) /* Gain Calibration bit 3 mask. */ -#define DAC_CH1GAINCAL3_bp 3 /* Gain Calibration bit 3 position. */ -#define DAC_CH1GAINCAL4_bm (1<<4) /* Gain Calibration bit 4 mask. */ -#define DAC_CH1GAINCAL4_bp 4 /* Gain Calibration bit 4 position. */ -#define DAC_CH1GAINCAL5_bm (1<<5) /* Gain Calibration bit 5 mask. */ -#define DAC_CH1GAINCAL5_bp 5 /* Gain Calibration bit 5 position. */ -#define DAC_CH1GAINCAL6_bm (1<<6) /* Gain Calibration bit 6 mask. */ -#define DAC_CH1GAINCAL6_bp 6 /* Gain Calibration bit 6 position. */ - -/* DAC.CH1OFFSETCAL bit masks and bit positions */ -#define DAC_CH1OFFSETCAL_gm 0x7F /* Offset Calibration group mask. */ -#define DAC_CH1OFFSETCAL_gp 0 /* Offset Calibration group position. */ -#define DAC_CH1OFFSETCAL0_bm (1<<0) /* Offset Calibration bit 0 mask. */ -#define DAC_CH1OFFSETCAL0_bp 0 /* Offset Calibration bit 0 position. */ -#define DAC_CH1OFFSETCAL1_bm (1<<1) /* Offset Calibration bit 1 mask. */ -#define DAC_CH1OFFSETCAL1_bp 1 /* Offset Calibration bit 1 position. */ -#define DAC_CH1OFFSETCAL2_bm (1<<2) /* Offset Calibration bit 2 mask. */ -#define DAC_CH1OFFSETCAL2_bp 2 /* Offset Calibration bit 2 position. */ -#define DAC_CH1OFFSETCAL3_bm (1<<3) /* Offset Calibration bit 3 mask. */ -#define DAC_CH1OFFSETCAL3_bp 3 /* Offset Calibration bit 3 position. */ -#define DAC_CH1OFFSETCAL4_bm (1<<4) /* Offset Calibration bit 4 mask. */ -#define DAC_CH1OFFSETCAL4_bp 4 /* Offset Calibration bit 4 position. */ -#define DAC_CH1OFFSETCAL5_bm (1<<5) /* Offset Calibration bit 5 mask. */ -#define DAC_CH1OFFSETCAL5_bp 5 /* Offset Calibration bit 5 position. */ -#define DAC_CH1OFFSETCAL6_bm (1<<6) /* Offset Calibration bit 6 mask. */ -#define DAC_CH1OFFSETCAL6_bp 6 /* Offset Calibration bit 6 position. */ - -/* AC - Analog Comparator */ -/* AC.AC0CTRL bit masks and bit positions */ -#define AC_INTMODE_gm 0xC0 /* Interrupt Mode group mask. */ -#define AC_INTMODE_gp 6 /* Interrupt Mode group position. */ -#define AC_INTMODE0_bm (1<<6) /* Interrupt Mode bit 0 mask. */ -#define AC_INTMODE0_bp 6 /* Interrupt Mode bit 0 position. */ -#define AC_INTMODE1_bm (1<<7) /* Interrupt Mode bit 1 mask. */ -#define AC_INTMODE1_bp 7 /* Interrupt Mode bit 1 position. */ - -#define AC_INTLVL_gm 0x30 /* Interrupt Level group mask. */ -#define AC_INTLVL_gp 4 /* Interrupt Level group position. */ -#define AC_INTLVL0_bm (1<<4) /* Interrupt Level bit 0 mask. */ -#define AC_INTLVL0_bp 4 /* Interrupt Level bit 0 position. */ -#define AC_INTLVL1_bm (1<<5) /* Interrupt Level bit 1 mask. */ -#define AC_INTLVL1_bp 5 /* Interrupt Level bit 1 position. */ - -#define AC_HYSMODE_gm 0x06 /* Hysteresis Mode group mask. */ -#define AC_HYSMODE_gp 1 /* Hysteresis Mode group position. */ -#define AC_HYSMODE0_bm (1<<1) /* Hysteresis Mode bit 0 mask. */ -#define AC_HYSMODE0_bp 1 /* Hysteresis Mode bit 0 position. */ -#define AC_HYSMODE1_bm (1<<2) /* Hysteresis Mode bit 1 mask. */ -#define AC_HYSMODE1_bp 2 /* Hysteresis Mode bit 1 position. */ - -#define AC_ENABLE_bm 0x01 /* Enable bit mask. */ -#define AC_ENABLE_bp 0 /* Enable bit position. */ - -/* AC.AC1CTRL bit masks and bit positions */ -/* AC_INTMODE Predefined. */ -/* AC_INTMODE Predefined. */ - -/* AC_INTLVL Predefined. */ -/* AC_INTLVL Predefined. */ - -/* AC_HYSMODE Predefined. */ -/* AC_HYSMODE Predefined. */ - -/* AC_ENABLE Predefined. */ -/* AC_ENABLE Predefined. */ - -/* AC.AC0MUXCTRL bit masks and bit positions */ -#define AC_MUXPOS_gm 0x38 /* MUX Positive Input group mask. */ -#define AC_MUXPOS_gp 3 /* MUX Positive Input group position. */ -#define AC_MUXPOS0_bm (1<<3) /* MUX Positive Input bit 0 mask. */ -#define AC_MUXPOS0_bp 3 /* MUX Positive Input bit 0 position. */ -#define AC_MUXPOS1_bm (1<<4) /* MUX Positive Input bit 1 mask. */ -#define AC_MUXPOS1_bp 4 /* MUX Positive Input bit 1 position. */ -#define AC_MUXPOS2_bm (1<<5) /* MUX Positive Input bit 2 mask. */ -#define AC_MUXPOS2_bp 5 /* MUX Positive Input bit 2 position. */ - -#define AC_MUXNEG_gm 0x07 /* MUX Negative Input group mask. */ -#define AC_MUXNEG_gp 0 /* MUX Negative Input group position. */ -#define AC_MUXNEG0_bm (1<<0) /* MUX Negative Input bit 0 mask. */ -#define AC_MUXNEG0_bp 0 /* MUX Negative Input bit 0 position. */ -#define AC_MUXNEG1_bm (1<<1) /* MUX Negative Input bit 1 mask. */ -#define AC_MUXNEG1_bp 1 /* MUX Negative Input bit 1 position. */ -#define AC_MUXNEG2_bm (1<<2) /* MUX Negative Input bit 2 mask. */ -#define AC_MUXNEG2_bp 2 /* MUX Negative Input bit 2 position. */ - -/* AC.AC1MUXCTRL bit masks and bit positions */ -/* AC_MUXPOS Predefined. */ -/* AC_MUXPOS Predefined. */ - -/* AC_MUXNEG Predefined. */ -/* AC_MUXNEG Predefined. */ - -/* AC.CTRLA bit masks and bit positions */ -#define AC_AC1INVEN_bm 0x08 /* Analog Comparator 1 Output Invert Enable bit mask. */ -#define AC_AC1INVEN_bp 3 /* Analog Comparator 1 Output Invert Enable bit position. */ - -#define AC_AC0INVEN_bm 0x04 /* Analog Comparator 0 Output Invert Enable bit mask. */ -#define AC_AC0INVEN_bp 2 /* Analog Comparator 0 Output Invert Enable bit position. */ - -#define AC_AC1OUT_bm 0x02 /* Analog Comparator 1 Output Enable bit mask. */ -#define AC_AC1OUT_bp 1 /* Analog Comparator 1 Output Enable bit position. */ - -#define AC_AC0OUT_bm 0x01 /* Analog Comparator 0 Output Enable bit mask. */ -#define AC_AC0OUT_bp 0 /* Analog Comparator 0 Output Enable bit position. */ - -/* AC.CTRLB bit masks and bit positions */ -#define AC_SCALEFAC_gm 0x3F /* VCC Voltage Scaler Factor group mask. */ -#define AC_SCALEFAC_gp 0 /* VCC Voltage Scaler Factor group position. */ -#define AC_SCALEFAC0_bm (1<<0) /* VCC Voltage Scaler Factor bit 0 mask. */ -#define AC_SCALEFAC0_bp 0 /* VCC Voltage Scaler Factor bit 0 position. */ -#define AC_SCALEFAC1_bm (1<<1) /* VCC Voltage Scaler Factor bit 1 mask. */ -#define AC_SCALEFAC1_bp 1 /* VCC Voltage Scaler Factor bit 1 position. */ -#define AC_SCALEFAC2_bm (1<<2) /* VCC Voltage Scaler Factor bit 2 mask. */ -#define AC_SCALEFAC2_bp 2 /* VCC Voltage Scaler Factor bit 2 position. */ -#define AC_SCALEFAC3_bm (1<<3) /* VCC Voltage Scaler Factor bit 3 mask. */ -#define AC_SCALEFAC3_bp 3 /* VCC Voltage Scaler Factor bit 3 position. */ -#define AC_SCALEFAC4_bm (1<<4) /* VCC Voltage Scaler Factor bit 4 mask. */ -#define AC_SCALEFAC4_bp 4 /* VCC Voltage Scaler Factor bit 4 position. */ -#define AC_SCALEFAC5_bm (1<<5) /* VCC Voltage Scaler Factor bit 5 mask. */ -#define AC_SCALEFAC5_bp 5 /* VCC Voltage Scaler Factor bit 5 position. */ - -/* AC.WINCTRL bit masks and bit positions */ -#define AC_WEN_bm 0x10 /* Window Mode Enable bit mask. */ -#define AC_WEN_bp 4 /* Window Mode Enable bit position. */ - -#define AC_WINTMODE_gm 0x0C /* Window Interrupt Mode group mask. */ -#define AC_WINTMODE_gp 2 /* Window Interrupt Mode group position. */ -#define AC_WINTMODE0_bm (1<<2) /* Window Interrupt Mode bit 0 mask. */ -#define AC_WINTMODE0_bp 2 /* Window Interrupt Mode bit 0 position. */ -#define AC_WINTMODE1_bm (1<<3) /* Window Interrupt Mode bit 1 mask. */ -#define AC_WINTMODE1_bp 3 /* Window Interrupt Mode bit 1 position. */ - -#define AC_WINTLVL_gm 0x03 /* Window Interrupt Level group mask. */ -#define AC_WINTLVL_gp 0 /* Window Interrupt Level group position. */ -#define AC_WINTLVL0_bm (1<<0) /* Window Interrupt Level bit 0 mask. */ -#define AC_WINTLVL0_bp 0 /* Window Interrupt Level bit 0 position. */ -#define AC_WINTLVL1_bm (1<<1) /* Window Interrupt Level bit 1 mask. */ -#define AC_WINTLVL1_bp 1 /* Window Interrupt Level bit 1 position. */ - -/* AC.STATUS bit masks and bit positions */ -#define AC_WSTATE_gm 0xC0 /* Window Mode State group mask. */ -#define AC_WSTATE_gp 6 /* Window Mode State group position. */ -#define AC_WSTATE0_bm (1<<6) /* Window Mode State bit 0 mask. */ -#define AC_WSTATE0_bp 6 /* Window Mode State bit 0 position. */ -#define AC_WSTATE1_bm (1<<7) /* Window Mode State bit 1 mask. */ -#define AC_WSTATE1_bp 7 /* Window Mode State bit 1 position. */ - -#define AC_AC1STATE_bm 0x20 /* Analog Comparator 1 State bit mask. */ -#define AC_AC1STATE_bp 5 /* Analog Comparator 1 State bit position. */ - -#define AC_AC0STATE_bm 0x10 /* Analog Comparator 0 State bit mask. */ -#define AC_AC0STATE_bp 4 /* Analog Comparator 0 State bit position. */ - -#define AC_WIF_bm 0x04 /* Window Mode Interrupt Flag bit mask. */ -#define AC_WIF_bp 2 /* Window Mode Interrupt Flag bit position. */ - -#define AC_AC1IF_bm 0x02 /* Analog Comparator 1 Interrupt Flag bit mask. */ -#define AC_AC1IF_bp 1 /* Analog Comparator 1 Interrupt Flag bit position. */ - -#define AC_AC0IF_bm 0x01 /* Analog Comparator 0 Interrupt Flag bit mask. */ -#define AC_AC0IF_bp 0 /* Analog Comparator 0 Interrupt Flag bit position. */ - -/* AC.CURRCTRL bit masks and bit positions */ -#define AC_CURREN_bm 0x80 /* Current Source Enable bit mask. */ -#define AC_CURREN_bp 7 /* Current Source Enable bit position. */ - -#define AC_CURRMODE_bm 0x40 /* Current Mode bit mask. */ -#define AC_CURRMODE_bp 6 /* Current Mode bit position. */ - -#define AC_AC1CURR_bm 0x02 /* Analog Comparator 1 current source output bit mask. */ -#define AC_AC1CURR_bp 1 /* Analog Comparator 1 current source output bit position. */ - -#define AC_AC0CURR_bm 0x01 /* Analog Comparator 0 current source output bit mask. */ -#define AC_AC0CURR_bp 0 /* Analog Comparator 0 current source output bit position. */ - -/* AC.CURRCALIB bit masks and bit positions */ -#define AC_CALIB_gm 0x0F /* Current Source Calibration group mask. */ -#define AC_CALIB_gp 0 /* Current Source Calibration group position. */ -#define AC_CALIB0_bm (1<<0) /* Current Source Calibration bit 0 mask. */ -#define AC_CALIB0_bp 0 /* Current Source Calibration bit 0 position. */ -#define AC_CALIB1_bm (1<<1) /* Current Source Calibration bit 1 mask. */ -#define AC_CALIB1_bp 1 /* Current Source Calibration bit 1 position. */ -#define AC_CALIB2_bm (1<<2) /* Current Source Calibration bit 2 mask. */ -#define AC_CALIB2_bp 2 /* Current Source Calibration bit 2 position. */ -#define AC_CALIB3_bm (1<<3) /* Current Source Calibration bit 3 mask. */ -#define AC_CALIB3_bp 3 /* Current Source Calibration bit 3 position. */ - -/* RTC - Real-Time Clounter */ -/* RTC.CTRL bit masks and bit positions */ -#define RTC_CORREN_bm 0x08 /* Correction Enable bit mask. */ -#define RTC_CORREN_bp 3 /* Correction Enable bit position. */ - -#define RTC_PRESCALER_gm 0x07 /* Prescaling Factor group mask. */ -#define RTC_PRESCALER_gp 0 /* Prescaling Factor group position. */ -#define RTC_PRESCALER0_bm (1<<0) /* Prescaling Factor bit 0 mask. */ -#define RTC_PRESCALER0_bp 0 /* Prescaling Factor bit 0 position. */ -#define RTC_PRESCALER1_bm (1<<1) /* Prescaling Factor bit 1 mask. */ -#define RTC_PRESCALER1_bp 1 /* Prescaling Factor bit 1 position. */ -#define RTC_PRESCALER2_bm (1<<2) /* Prescaling Factor bit 2 mask. */ -#define RTC_PRESCALER2_bp 2 /* Prescaling Factor bit 2 position. */ - -/* RTC.STATUS bit masks and bit positions */ -#define RTC_SYNCBUSY_bm 0x01 /* Synchronization Busy Flag bit mask. */ -#define RTC_SYNCBUSY_bp 0 /* Synchronization Busy Flag bit position. */ - -/* RTC.INTCTRL bit masks and bit positions */ -#define RTC_COMPINTLVL_gm 0x0C /* Compare Match Interrupt Level group mask. */ -#define RTC_COMPINTLVL_gp 2 /* Compare Match Interrupt Level group position. */ -#define RTC_COMPINTLVL0_bm (1<<2) /* Compare Match Interrupt Level bit 0 mask. */ -#define RTC_COMPINTLVL0_bp 2 /* Compare Match Interrupt Level bit 0 position. */ -#define RTC_COMPINTLVL1_bm (1<<3) /* Compare Match Interrupt Level bit 1 mask. */ -#define RTC_COMPINTLVL1_bp 3 /* Compare Match Interrupt Level bit 1 position. */ - -#define RTC_OVFINTLVL_gm 0x03 /* Overflow Interrupt Level group mask. */ -#define RTC_OVFINTLVL_gp 0 /* Overflow Interrupt Level group position. */ -#define RTC_OVFINTLVL0_bm (1<<0) /* Overflow Interrupt Level bit 0 mask. */ -#define RTC_OVFINTLVL0_bp 0 /* Overflow Interrupt Level bit 0 position. */ -#define RTC_OVFINTLVL1_bm (1<<1) /* Overflow Interrupt Level bit 1 mask. */ -#define RTC_OVFINTLVL1_bp 1 /* Overflow Interrupt Level bit 1 position. */ - -/* RTC.INTFLAGS bit masks and bit positions */ -#define RTC_COMPIF_bm 0x02 /* Compare Match Interrupt Flag bit mask. */ -#define RTC_COMPIF_bp 1 /* Compare Match Interrupt Flag bit position. */ - -#define RTC_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ -#define RTC_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ - -/* RTC.CALIB bit masks and bit positions */ -#define RTC_SIGN_bm 0x80 /* Correction Sign bit mask. */ -#define RTC_SIGN_bp 7 /* Correction Sign bit position. */ - -#define RTC_ERROR_gm 0x7F /* Error Value group mask. */ -#define RTC_ERROR_gp 0 /* Error Value group position. */ -#define RTC_ERROR0_bm (1<<0) /* Error Value bit 0 mask. */ -#define RTC_ERROR0_bp 0 /* Error Value bit 0 position. */ -#define RTC_ERROR1_bm (1<<1) /* Error Value bit 1 mask. */ -#define RTC_ERROR1_bp 1 /* Error Value bit 1 position. */ -#define RTC_ERROR2_bm (1<<2) /* Error Value bit 2 mask. */ -#define RTC_ERROR2_bp 2 /* Error Value bit 2 position. */ -#define RTC_ERROR3_bm (1<<3) /* Error Value bit 3 mask. */ -#define RTC_ERROR3_bp 3 /* Error Value bit 3 position. */ -#define RTC_ERROR4_bm (1<<4) /* Error Value bit 4 mask. */ -#define RTC_ERROR4_bp 4 /* Error Value bit 4 position. */ -#define RTC_ERROR5_bm (1<<5) /* Error Value bit 5 mask. */ -#define RTC_ERROR5_bp 5 /* Error Value bit 5 position. */ -#define RTC_ERROR6_bm (1<<6) /* Error Value bit 6 mask. */ -#define RTC_ERROR6_bp 6 /* Error Value bit 6 position. */ - -/* XCL - XMEGA Custom Logic */ -/* XCL.CTRLA bit masks and bit positions */ -#define XCL_LUT0OUTEN_gm 0xC0 /* LUT0 Output Enable group mask. */ -#define XCL_LUT0OUTEN_gp 6 /* LUT0 Output Enable group position. */ -#define XCL_LUT0OUTEN0_bm (1<<6) /* LUT0 Output Enable bit 0 mask. */ -#define XCL_LUT0OUTEN0_bp 6 /* LUT0 Output Enable bit 0 position. */ -#define XCL_LUT0OUTEN1_bm (1<<7) /* LUT0 Output Enable bit 1 mask. */ -#define XCL_LUT0OUTEN1_bp 7 /* LUT0 Output Enable bit 1 position. */ - -#define XCL_PORTSEL_gm 0x30 /* Port Selection group mask. */ -#define XCL_PORTSEL_gp 4 /* Port Selection group position. */ -#define XCL_PORTSEL0_bm (1<<4) /* Port Selection bit 0 mask. */ -#define XCL_PORTSEL0_bp 4 /* Port Selection bit 0 position. */ -#define XCL_PORTSEL1_bm (1<<5) /* Port Selection bit 1 mask. */ -#define XCL_PORTSEL1_bp 5 /* Port Selection bit 1 position. */ - -#define XCL_LUTCONF_gm 0x07 /* LUT Configuration group mask. */ -#define XCL_LUTCONF_gp 0 /* LUT Configuration group position. */ -#define XCL_LUTCONF0_bm (1<<0) /* LUT Configuration bit 0 mask. */ -#define XCL_LUTCONF0_bp 0 /* LUT Configuration bit 0 position. */ -#define XCL_LUTCONF1_bm (1<<1) /* LUT Configuration bit 1 mask. */ -#define XCL_LUTCONF1_bp 1 /* LUT Configuration bit 1 position. */ -#define XCL_LUTCONF2_bm (1<<2) /* LUT Configuration bit 2 mask. */ -#define XCL_LUTCONF2_bp 2 /* LUT Configuration bit 2 position. */ - -/* XCL.CTRLB bit masks and bit positions */ -#define XCL_IN3SEL_gm 0xC0 /* Input Selection 3 group mask. */ -#define XCL_IN3SEL_gp 6 /* Input Selection 3 group position. */ -#define XCL_IN3SEL0_bm (1<<6) /* Input Selection 3 bit 0 mask. */ -#define XCL_IN3SEL0_bp 6 /* Input Selection 3 bit 0 position. */ -#define XCL_IN3SEL1_bm (1<<7) /* Input Selection 3 bit 1 mask. */ -#define XCL_IN3SEL1_bp 7 /* Input Selection 3 bit 1 position. */ - -#define XCL_IN2SEL_gm 0x30 /* Input Selection 2 group mask. */ -#define XCL_IN2SEL_gp 4 /* Input Selection 2 group position. */ -#define XCL_IN2SEL0_bm (1<<4) /* Input Selection 2 bit 0 mask. */ -#define XCL_IN2SEL0_bp 4 /* Input Selection 2 bit 0 position. */ -#define XCL_IN2SEL1_bm (1<<5) /* Input Selection 2 bit 1 mask. */ -#define XCL_IN2SEL1_bp 5 /* Input Selection 2 bit 1 position. */ - -#define XCL_IN1SEL_gm 0x0C /* Input Selection 1 group mask. */ -#define XCL_IN1SEL_gp 2 /* Input Selection 1 group position. */ -#define XCL_IN1SEL0_bm (1<<2) /* Input Selection 1 bit 0 mask. */ -#define XCL_IN1SEL0_bp 2 /* Input Selection 1 bit 0 position. */ -#define XCL_IN1SEL1_bm (1<<3) /* Input Selection 1 bit 1 mask. */ -#define XCL_IN1SEL1_bp 3 /* Input Selection 1 bit 1 position. */ - -#define XCL_IN0SEL_gm 0x03 /* Input Selection 0 group mask. */ -#define XCL_IN0SEL_gp 0 /* Input Selection 0 group position. */ -#define XCL_IN0SEL0_bm (1<<0) /* Input Selection 0 bit 0 mask. */ -#define XCL_IN0SEL0_bp 0 /* Input Selection 0 bit 0 position. */ -#define XCL_IN0SEL1_bm (1<<1) /* Input Selection 0 bit 1 mask. */ -#define XCL_IN0SEL1_bp 1 /* Input Selection 0 bit 1 position. */ - -/* XCL.CTRLC bit masks and bit positions */ -#define XCL_EVASYSEL1_bm 0x80 /* Asynchronous Event Line Selection for LUT1 bit mask. */ -#define XCL_EVASYSEL1_bp 7 /* Asynchronous Event Line Selection for LUT1 bit position. */ - -#define XCL_EVASYSEL0_bm 0x40 /* Asynchronous Event Line Selection for LUT0 bit mask. */ -#define XCL_EVASYSEL0_bp 6 /* Asynchronous Event Line Selection for LUT0 bit position. */ - -#define XCL_DLYSEL_gm 0x30 /* Delay Selection group mask. */ -#define XCL_DLYSEL_gp 4 /* Delay Selection group position. */ -#define XCL_DLYSEL0_bm (1<<4) /* Delay Selection bit 0 mask. */ -#define XCL_DLYSEL0_bp 4 /* Delay Selection bit 0 position. */ -#define XCL_DLYSEL1_bm (1<<5) /* Delay Selection bit 1 mask. */ -#define XCL_DLYSEL1_bp 5 /* Delay Selection bit 1 position. */ - -#define XCL_DLY1CONF_gm 0x0C /* Delay Configuration on LUT1 group mask. */ -#define XCL_DLY1CONF_gp 2 /* Delay Configuration on LUT1 group position. */ -#define XCL_DLY1CONF0_bm (1<<2) /* Delay Configuration on LUT1 bit 0 mask. */ -#define XCL_DLY1CONF0_bp 2 /* Delay Configuration on LUT1 bit 0 position. */ -#define XCL_DLY1CONF1_bm (1<<3) /* Delay Configuration on LUT1 bit 1 mask. */ -#define XCL_DLY1CONF1_bp 3 /* Delay Configuration on LUT1 bit 1 position. */ - -#define XCL_DLY0CONF_gm 0x03 /* Delay Configuration on LUT0 group mask. */ -#define XCL_DLY0CONF_gp 0 /* Delay Configuration on LUT0 group position. */ -#define XCL_DLY0CONF0_bm (1<<0) /* Delay Configuration on LUT0 bit 0 mask. */ -#define XCL_DLY0CONF0_bp 0 /* Delay Configuration on LUT0 bit 0 position. */ -#define XCL_DLY0CONF1_bm (1<<1) /* Delay Configuration on LUT0 bit 1 mask. */ -#define XCL_DLY0CONF1_bp 1 /* Delay Configuration on LUT0 bit 1 position. */ - -/* XCL.CTRLD bit masks and bit positions */ -#define XCL_TRUTH1_gm 0xF0 /* Truth Table of LUT1 group mask. */ -#define XCL_TRUTH1_gp 4 /* Truth Table of LUT1 group position. */ -#define XCL_TRUTH10_bm (1<<4) /* Truth Table of LUT1 bit 0 mask. */ -#define XCL_TRUTH10_bp 4 /* Truth Table of LUT1 bit 0 position. */ -#define XCL_TRUTH11_bm (1<<5) /* Truth Table of LUT1 bit 1 mask. */ -#define XCL_TRUTH11_bp 5 /* Truth Table of LUT1 bit 1 position. */ -#define XCL_TRUTH12_bm (1<<6) /* Truth Table of LUT1 bit 2 mask. */ -#define XCL_TRUTH12_bp 6 /* Truth Table of LUT1 bit 2 position. */ -#define XCL_TRUTH13_bm (1<<7) /* Truth Table of LUT1 bit 3 mask. */ -#define XCL_TRUTH13_bp 7 /* Truth Table of LUT1 bit 3 position. */ - -#define XCL_TRUTH0_gm 0x0F /* Truth Table of LUT0 group mask. */ -#define XCL_TRUTH0_gp 0 /* Truth Table of LUT0 group position. */ -#define XCL_TRUTH00_bm (1<<0) /* Truth Table of LUT0 bit 0 mask. */ -#define XCL_TRUTH00_bp 0 /* Truth Table of LUT0 bit 0 position. */ -#define XCL_TRUTH01_bm (1<<1) /* Truth Table of LUT0 bit 1 mask. */ -#define XCL_TRUTH01_bp 1 /* Truth Table of LUT0 bit 1 position. */ -#define XCL_TRUTH02_bm (1<<2) /* Truth Table of LUT0 bit 2 mask. */ -#define XCL_TRUTH02_bp 2 /* Truth Table of LUT0 bit 2 position. */ -#define XCL_TRUTH03_bm (1<<3) /* Truth Table of LUT0 bit 3 mask. */ -#define XCL_TRUTH03_bp 3 /* Truth Table of LUT0 bit 3 position. */ - -/* XCL.CTRLE bit masks and bit positions */ -#define XCL_CMDSEL_bm 0x80 /* Timer/Counter Command Selection bit mask. */ -#define XCL_CMDSEL_bp 7 /* Timer/Counter Command Selection bit position. */ - -#define XCL_TCSEL_gm 0x70 /* Timer/Counter Selection group mask. */ -#define XCL_TCSEL_gp 4 /* Timer/Counter Selection group position. */ -#define XCL_TCSEL0_bm (1<<4) /* Timer/Counter Selection bit 0 mask. */ -#define XCL_TCSEL0_bp 4 /* Timer/Counter Selection bit 0 position. */ -#define XCL_TCSEL1_bm (1<<5) /* Timer/Counter Selection bit 1 mask. */ -#define XCL_TCSEL1_bp 5 /* Timer/Counter Selection bit 1 position. */ -#define XCL_TCSEL2_bm (1<<6) /* Timer/Counter Selection bit 2 mask. */ -#define XCL_TCSEL2_bp 6 /* Timer/Counter Selection bit 2 position. */ - -#define XCL_CLKSEL_gm 0x0F /* Clock Selection group mask. */ -#define XCL_CLKSEL_gp 0 /* Clock Selection group position. */ -#define XCL_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ -#define XCL_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ -#define XCL_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ -#define XCL_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ -#define XCL_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ -#define XCL_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ -#define XCL_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ -#define XCL_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ - -/* XCL.CTRLF bit masks and bit positions */ -#define XCL_CMDEN_gm 0xC0 /* Command Enable group mask. */ -#define XCL_CMDEN_gp 6 /* Command Enable group position. */ -#define XCL_CMDEN0_bm (1<<6) /* Command Enable bit 0 mask. */ -#define XCL_CMDEN0_bp 6 /* Command Enable bit 0 position. */ -#define XCL_CMDEN1_bm (1<<7) /* Command Enable bit 1 mask. */ -#define XCL_CMDEN1_bp 7 /* Command Enable bit 1 position. */ - -#define XCL_CMP1_bm 0x20 /* Compare Channel 1 Output Value bit mask. */ -#define XCL_CMP1_bp 5 /* Compare Channel 1 Output Value bit position. */ - -#define XCL_CMP0_bm 0x10 /* Compare Channel 0 Output Value bit mask. */ -#define XCL_CMP0_bp 4 /* Compare Channel 0 Output Value bit position. */ - -#define XCL_CCEN1_bm 0x08 /* Compare or Capture Channel 1 Enable bit mask. */ -#define XCL_CCEN1_bp 3 /* Compare or Capture Channel 1 Enable bit position. */ - -#define XCL_CCEN0_bm 0x04 /* Compare or Capture Channel 0 Enable bit mask. */ -#define XCL_CCEN0_bp 2 /* Compare or Capture Channel 0 Enable bit position. */ - -#define XCL_MODE_gm 0x03 /* Timer/Counter Mode group mask. */ -#define XCL_MODE_gp 0 /* Timer/Counter Mode group position. */ -#define XCL_MODE0_bm (1<<0) /* Timer/Counter Mode bit 0 mask. */ -#define XCL_MODE0_bp 0 /* Timer/Counter Mode bit 0 position. */ -#define XCL_MODE1_bm (1<<1) /* Timer/Counter Mode bit 1 mask. */ -#define XCL_MODE1_bp 1 /* Timer/Counter Mode bit 1 position. */ - -/* XCL.CTRLG bit masks and bit positions */ -#define XCL_EVACTEN_bm 0x80 /* Event Action Enable bit mask. */ -#define XCL_EVACTEN_bp 7 /* Event Action Enable bit position. */ - -#define XCL_EVACT1_gm 0x60 /* Event Action Selection on Timer/Counter 1 group mask. */ -#define XCL_EVACT1_gp 5 /* Event Action Selection on Timer/Counter 1 group position. */ -#define XCL_EVACT10_bm (1<<5) /* Event Action Selection on Timer/Counter 1 bit 0 mask. */ -#define XCL_EVACT10_bp 5 /* Event Action Selection on Timer/Counter 1 bit 0 position. */ -#define XCL_EVACT11_bm (1<<6) /* Event Action Selection on Timer/Counter 1 bit 1 mask. */ -#define XCL_EVACT11_bp 6 /* Event Action Selection on Timer/Counter 1 bit 1 position. */ - -#define XCL_EVACT0_gm 0x18 /* Event Action Selection on Timer/Counter 0 group mask. */ -#define XCL_EVACT0_gp 3 /* Event Action Selection on Timer/Counter 0 group position. */ -#define XCL_EVACT00_bm (1<<3) /* Event Action Selection on Timer/Counter 0 bit 0 mask. */ -#define XCL_EVACT00_bp 3 /* Event Action Selection on Timer/Counter 0 bit 0 position. */ -#define XCL_EVACT01_bm (1<<4) /* Event Action Selection on Timer/Counter 0 bit 1 mask. */ -#define XCL_EVACT01_bp 4 /* Event Action Selection on Timer/Counter 0 bit 1 position. */ - -#define XCL_EVSRC_gm 0x07 /* Event Source Selection group mask. */ -#define XCL_EVSRC_gp 0 /* Event Source Selection group position. */ -#define XCL_EVSRC0_bm (1<<0) /* Event Source Selection bit 0 mask. */ -#define XCL_EVSRC0_bp 0 /* Event Source Selection bit 0 position. */ -#define XCL_EVSRC1_bm (1<<1) /* Event Source Selection bit 1 mask. */ -#define XCL_EVSRC1_bp 1 /* Event Source Selection bit 1 position. */ -#define XCL_EVSRC2_bm (1<<2) /* Event Source Selection bit 2 mask. */ -#define XCL_EVSRC2_bp 2 /* Event Source Selection bit 2 position. */ - -/* XCL.INTCTRL bit masks and bit positions */ -#define XCL_UNF1IE_bm 0x80 /* Underflow 1 Interrupt Enable bit mask. */ -#define XCL_UNF1IE_bp 7 /* Underflow 1 Interrupt Enable bit position. */ - -#define XCL_PEC1IE_bm 0x80 /* Peripheral Counter 1 Interrupt Enable bit mask. */ -#define XCL_PEC1IE_bp 7 /* Peripheral Counter 1 Interrupt Enable bit position. */ - -#define XCL_PEC21IE_bm 0x80 /* Peripheral High Counter 2 Interrupt Enable bit mask. */ -#define XCL_PEC21IE_bp 7 /* Peripheral High Counter 2 Interrupt Enable bit position. */ - -#define XCL_UNF0IE_bm 0x40 /* Underflow 0 Interrupt Enable bit mask. */ -#define XCL_UNF0IE_bp 6 /* Underflow 0 Interrupt Enable bit position. */ - -#define XCL_PEC0IE_bm 0x40 /* Peripheral Counter 0 Interrupt Enable bit mask. */ -#define XCL_PEC0IE_bp 6 /* Peripheral Counter 0 Interrupt Enable bit position. */ - -#define XCL_CC1IE_bm 0x20 /* Compare Or Capture 1 Interrupt Enable bit mask. */ -#define XCL_CC1IE_bp 5 /* Compare Or Capture 1 Interrupt Enable bit position. */ - -#define XCL_PEC20IE_bm 0x20 /* Peripheral Low Counter 2 Interrupt Enable bit mask. */ -#define XCL_PEC20IE_bp 5 /* Peripheral Low Counter 2 Interrupt Enable bit position. */ - -#define XCL_CC0IE_bm 0x10 /* Compare Or Capture 0 Interrupt Enable bit mask. */ -#define XCL_CC0IE_bp 4 /* Compare Or Capture 0 Interrupt Enable bit position. */ - -#define XCL_UNFINTLVL_gm 0x0C /* Timer Underflow Interrupt Level group mask. */ -#define XCL_UNFINTLVL_gp 2 /* Timer Underflow Interrupt Level group position. */ -#define XCL_UNFINTLVL0_bm (1<<2) /* Timer Underflow Interrupt Level bit 0 mask. */ -#define XCL_UNFINTLVL0_bp 2 /* Timer Underflow Interrupt Level bit 0 position. */ -#define XCL_UNFINTLVL1_bm (1<<3) /* Timer Underflow Interrupt Level bit 1 mask. */ -#define XCL_UNFINTLVL1_bp 3 /* Timer Underflow Interrupt Level bit 1 position. */ - -#define XCL_CCINTLVL_gm 0x03 /* Timer Compare or Capture Interrupt Level group mask. */ -#define XCL_CCINTLVL_gp 0 /* Timer Compare or Capture Interrupt Level group position. */ -#define XCL_CCINTLVL0_bm (1<<0) /* Timer Compare or Capture Interrupt Level bit 0 mask. */ -#define XCL_CCINTLVL0_bp 0 /* Timer Compare or Capture Interrupt Level bit 0 position. */ -#define XCL_CCINTLVL1_bm (1<<1) /* Timer Compare or Capture Interrupt Level bit 1 mask. */ -#define XCL_CCINTLVL1_bp 1 /* Timer Compare or Capture Interrupt Level bit 1 position. */ - -/* XCL.INTFLAGS bit masks and bit positions */ -#define XCL_UNF1IF_bm 0x80 /* Timer/Counter 1 Underflow Interrupt Flag bit mask. */ -#define XCL_UNF1IF_bp 7 /* Timer/Counter 1 Underflow Interrupt Flag bit position. */ - -#define XCL_PEC1IF_bm 0x80 /* Peripheral Counter 1 Interrupt Flag bit mask. */ -#define XCL_PEC1IF_bp 7 /* Peripheral Counter 1 Interrupt Flag bit position. */ - -#define XCL_PEC21IF_bm 0x80 /* Peripheral High Counter 2 Interrupt Flag bit mask. */ -#define XCL_PEC21IF_bp 7 /* Peripheral High Counter 2 Interrupt Flag bit position. */ - -#define XCL_UNF0IF_bm 0x40 /* Timer/Counter 0 Underflow Interrupt Flag bit mask. */ -#define XCL_UNF0IF_bp 6 /* Timer/Counter 0 Underflow Interrupt Flag bit position. */ - -#define XCL_PEC0IF_bm 0x40 /* Peripheral Counter 0 Interrupt Flag bit mask. */ -#define XCL_PEC0IF_bp 6 /* Peripheral Counter 0 Interrupt Flag bit position. */ - -#define XCL_CC1IF_bm 0x20 /* Compare or Capture Channel 1 Interrupt Flag bit mask. */ -#define XCL_CC1IF_bp 5 /* Compare or Capture Channel 1 Interrupt Flag bit position. */ - -#define XCL_PEC20IF_bm 0x20 /* Peripheral Low Counter 2 Interrupt Flag bit mask. */ -#define XCL_PEC20IF_bp 5 /* Peripheral Low Counter 2 Interrupt Flag bit position. */ - -#define XCL_CC0IF_bm 0x10 /* Compare or Capture Channel 0 Interrupt Flag bit mask. */ -#define XCL_CC0IF_bp 4 /* Compare or Capture Channel 0 Interrupt Flag bit position. */ - -/* XCL.PLC bit masks and bit positions */ -#define XCL_PLC_gm 0xFF /* Peripheral Lenght Control Bits group mask. */ -#define XCL_PLC_gp 0 /* Peripheral Lenght Control Bits group position. */ -#define XCL_PLC0_bm (1<<0) /* Peripheral Lenght Control Bits bit 0 mask. */ -#define XCL_PLC0_bp 0 /* Peripheral Lenght Control Bits bit 0 position. */ -#define XCL_PLC1_bm (1<<1) /* Peripheral Lenght Control Bits bit 1 mask. */ -#define XCL_PLC1_bp 1 /* Peripheral Lenght Control Bits bit 1 position. */ -#define XCL_PLC2_bm (1<<2) /* Peripheral Lenght Control Bits bit 2 mask. */ -#define XCL_PLC2_bp 2 /* Peripheral Lenght Control Bits bit 2 position. */ -#define XCL_PLC3_bm (1<<3) /* Peripheral Lenght Control Bits bit 3 mask. */ -#define XCL_PLC3_bp 3 /* Peripheral Lenght Control Bits bit 3 position. */ -#define XCL_PLC4_bm (1<<4) /* Peripheral Lenght Control Bits bit 4 mask. */ -#define XCL_PLC4_bp 4 /* Peripheral Lenght Control Bits bit 4 position. */ -#define XCL_PLC5_bm (1<<5) /* Peripheral Lenght Control Bits bit 5 mask. */ -#define XCL_PLC5_bp 5 /* Peripheral Lenght Control Bits bit 5 position. */ -#define XCL_PLC6_bm (1<<6) /* Peripheral Lenght Control Bits bit 6 mask. */ -#define XCL_PLC6_bp 6 /* Peripheral Lenght Control Bits bit 6 position. */ -#define XCL_PLC7_bm (1<<7) /* Peripheral Lenght Control Bits bit 7 mask. */ -#define XCL_PLC7_bp 7 /* Peripheral Lenght Control Bits bit 7 position. */ - -/* XCL.CNTL bit masks and bit positions */ -#define XCL_BCNTO_gm 0xFF /* BTC0 Counter Byte group mask. */ -#define XCL_BCNTO_gp 0 /* BTC0 Counter Byte group position. */ -#define XCL_BCNTO0_bm (1<<0) /* BTC0 Counter Byte bit 0 mask. */ -#define XCL_BCNTO0_bp 0 /* BTC0 Counter Byte bit 0 position. */ -#define XCL_BCNTO1_bm (1<<1) /* BTC0 Counter Byte bit 1 mask. */ -#define XCL_BCNTO1_bp 1 /* BTC0 Counter Byte bit 1 position. */ -#define XCL_BCNTO2_bm (1<<2) /* BTC0 Counter Byte bit 2 mask. */ -#define XCL_BCNTO2_bp 2 /* BTC0 Counter Byte bit 2 position. */ -#define XCL_BCNTO3_bm (1<<3) /* BTC0 Counter Byte bit 3 mask. */ -#define XCL_BCNTO3_bp 3 /* BTC0 Counter Byte bit 3 position. */ -#define XCL_BCNTO4_bm (1<<4) /* BTC0 Counter Byte bit 4 mask. */ -#define XCL_BCNTO4_bp 4 /* BTC0 Counter Byte bit 4 position. */ -#define XCL_BCNTO5_bm (1<<5) /* BTC0 Counter Byte bit 5 mask. */ -#define XCL_BCNTO5_bp 5 /* BTC0 Counter Byte bit 5 position. */ -#define XCL_BCNTO6_bm (1<<6) /* BTC0 Counter Byte bit 6 mask. */ -#define XCL_BCNTO6_bp 6 /* BTC0 Counter Byte bit 6 position. */ -#define XCL_BCNTO7_bm (1<<7) /* BTC0 Counter Byte bit 7 mask. */ -#define XCL_BCNTO7_bp 7 /* BTC0 Counter Byte bit 7 position. */ - -#define XCL_CNTL_gm 0xFF /* TC16 Counter Low Byte group mask. */ -#define XCL_CNTL_gp 0 /* TC16 Counter Low Byte group position. */ -#define XCL_CNTL0_bm (1<<0) /* TC16 Counter Low Byte bit 0 mask. */ -#define XCL_CNTL0_bp 0 /* TC16 Counter Low Byte bit 0 position. */ -#define XCL_CNTL1_bm (1<<1) /* TC16 Counter Low Byte bit 1 mask. */ -#define XCL_CNTL1_bp 1 /* TC16 Counter Low Byte bit 1 position. */ -#define XCL_CNTL2_bm (1<<2) /* TC16 Counter Low Byte bit 2 mask. */ -#define XCL_CNTL2_bp 2 /* TC16 Counter Low Byte bit 2 position. */ -#define XCL_CNTL3_bm (1<<3) /* TC16 Counter Low Byte bit 3 mask. */ -#define XCL_CNTL3_bp 3 /* TC16 Counter Low Byte bit 3 position. */ -#define XCL_CNTL4_bm (1<<4) /* TC16 Counter Low Byte bit 4 mask. */ -#define XCL_CNTL4_bp 4 /* TC16 Counter Low Byte bit 4 position. */ -#define XCL_CNTL5_bm (1<<5) /* TC16 Counter Low Byte bit 5 mask. */ -#define XCL_CNTL5_bp 5 /* TC16 Counter Low Byte bit 5 position. */ -#define XCL_CNTL6_bm (1<<6) /* TC16 Counter Low Byte bit 6 mask. */ -#define XCL_CNTL6_bp 6 /* TC16 Counter Low Byte bit 6 position. */ -#define XCL_CNTL7_bm (1<<7) /* TC16 Counter Low Byte bit 7 mask. */ -#define XCL_CNTL7_bp 7 /* TC16 Counter Low Byte bit 7 position. */ - -#define XCL_PCNTO_gm 0xFF /* Peripheral Counter 0 Byte group mask. */ -#define XCL_PCNTO_gp 0 /* Peripheral Counter 0 Byte group position. */ -#define XCL_PCNTO0_bm (1<<0) /* Peripheral Counter 0 Byte bit 0 mask. */ -#define XCL_PCNTO0_bp 0 /* Peripheral Counter 0 Byte bit 0 position. */ -#define XCL_PCNTO1_bm (1<<1) /* Peripheral Counter 0 Byte bit 1 mask. */ -#define XCL_PCNTO1_bp 1 /* Peripheral Counter 0 Byte bit 1 position. */ -#define XCL_PCNTO2_bm (1<<2) /* Peripheral Counter 0 Byte bit 2 mask. */ -#define XCL_PCNTO2_bp 2 /* Peripheral Counter 0 Byte bit 2 position. */ -#define XCL_PCNTO3_bm (1<<3) /* Peripheral Counter 0 Byte bit 3 mask. */ -#define XCL_PCNTO3_bp 3 /* Peripheral Counter 0 Byte bit 3 position. */ -#define XCL_PCNTO4_bm (1<<4) /* Peripheral Counter 0 Byte bit 4 mask. */ -#define XCL_PCNTO4_bp 4 /* Peripheral Counter 0 Byte bit 4 position. */ -#define XCL_PCNTO5_bm (1<<5) /* Peripheral Counter 0 Byte bit 5 mask. */ -#define XCL_PCNTO5_bp 5 /* Peripheral Counter 0 Byte bit 5 position. */ -#define XCL_PCNTO6_bm (1<<6) /* Peripheral Counter 0 Byte bit 6 mask. */ -#define XCL_PCNTO6_bp 6 /* Peripheral Counter 0 Byte bit 6 position. */ -#define XCL_PCNTO7_bm (1<<7) /* Peripheral Counter 0 Byte bit 7 mask. */ -#define XCL_PCNTO7_bp 7 /* Peripheral Counter 0 Byte bit 7 position. */ - -/* XCL.CNTH bit masks and bit positions */ -#define XCL_BCNT1_gm 0xFF /* BTC1 Counter Byte group mask. */ -#define XCL_BCNT1_gp 0 /* BTC1 Counter Byte group position. */ -#define XCL_BCNT10_bm (1<<0) /* BTC1 Counter Byte bit 0 mask. */ -#define XCL_BCNT10_bp 0 /* BTC1 Counter Byte bit 0 position. */ -#define XCL_BCNT11_bm (1<<1) /* BTC1 Counter Byte bit 1 mask. */ -#define XCL_BCNT11_bp 1 /* BTC1 Counter Byte bit 1 position. */ -#define XCL_BCNT12_bm (1<<2) /* BTC1 Counter Byte bit 2 mask. */ -#define XCL_BCNT12_bp 2 /* BTC1 Counter Byte bit 2 position. */ -#define XCL_BCNT13_bm (1<<3) /* BTC1 Counter Byte bit 3 mask. */ -#define XCL_BCNT13_bp 3 /* BTC1 Counter Byte bit 3 position. */ -#define XCL_BCNT14_bm (1<<4) /* BTC1 Counter Byte bit 4 mask. */ -#define XCL_BCNT14_bp 4 /* BTC1 Counter Byte bit 4 position. */ -#define XCL_BCNT15_bm (1<<5) /* BTC1 Counter Byte bit 5 mask. */ -#define XCL_BCNT15_bp 5 /* BTC1 Counter Byte bit 5 position. */ -#define XCL_BCNT16_bm (1<<6) /* BTC1 Counter Byte bit 6 mask. */ -#define XCL_BCNT16_bp 6 /* BTC1 Counter Byte bit 6 position. */ -#define XCL_BCNT17_bm (1<<7) /* BTC1 Counter Byte bit 7 mask. */ -#define XCL_BCNT17_bp 7 /* BTC1 Counter Byte bit 7 position. */ - -#define XCL_CNTH_gm 0xFF /* TC16 Counter High Byte group mask. */ -#define XCL_CNTH_gp 0 /* TC16 Counter High Byte group position. */ -#define XCL_CNTH0_bm (1<<0) /* TC16 Counter High Byte bit 0 mask. */ -#define XCL_CNTH0_bp 0 /* TC16 Counter High Byte bit 0 position. */ -#define XCL_CNTH1_bm (1<<1) /* TC16 Counter High Byte bit 1 mask. */ -#define XCL_CNTH1_bp 1 /* TC16 Counter High Byte bit 1 position. */ -#define XCL_CNTH2_bm (1<<2) /* TC16 Counter High Byte bit 2 mask. */ -#define XCL_CNTH2_bp 2 /* TC16 Counter High Byte bit 2 position. */ -#define XCL_CNTH3_bm (1<<3) /* TC16 Counter High Byte bit 3 mask. */ -#define XCL_CNTH3_bp 3 /* TC16 Counter High Byte bit 3 position. */ -#define XCL_CNTH4_bm (1<<4) /* TC16 Counter High Byte bit 4 mask. */ -#define XCL_CNTH4_bp 4 /* TC16 Counter High Byte bit 4 position. */ -#define XCL_CNTH5_bm (1<<5) /* TC16 Counter High Byte bit 5 mask. */ -#define XCL_CNTH5_bp 5 /* TC16 Counter High Byte bit 5 position. */ -#define XCL_CNTH6_bm (1<<6) /* TC16 Counter High Byte bit 6 mask. */ -#define XCL_CNTH6_bp 6 /* TC16 Counter High Byte bit 6 position. */ -#define XCL_CNTH7_bm (1<<7) /* TC16 Counter High Byte bit 7 mask. */ -#define XCL_CNTH7_bp 7 /* TC16 Counter High Byte bit 7 position. */ - -#define XCL_PCNT1_gm 0xFF /* Peripheral Counter 1 Byte group mask. */ -#define XCL_PCNT1_gp 0 /* Peripheral Counter 1 Byte group position. */ -#define XCL_PCNT10_bm (1<<0) /* Peripheral Counter 1 Byte bit 0 mask. */ -#define XCL_PCNT10_bp 0 /* Peripheral Counter 1 Byte bit 0 position. */ -#define XCL_PCNT11_bm (1<<1) /* Peripheral Counter 1 Byte bit 1 mask. */ -#define XCL_PCNT11_bp 1 /* Peripheral Counter 1 Byte bit 1 position. */ -#define XCL_PCNT12_bm (1<<2) /* Peripheral Counter 1 Byte bit 2 mask. */ -#define XCL_PCNT12_bp 2 /* Peripheral Counter 1 Byte bit 2 position. */ -#define XCL_PCNT13_bm (1<<3) /* Peripheral Counter 1 Byte bit 3 mask. */ -#define XCL_PCNT13_bp 3 /* Peripheral Counter 1 Byte bit 3 position. */ -#define XCL_PCNT14_bm (1<<4) /* Peripheral Counter 1 Byte bit 4 mask. */ -#define XCL_PCNT14_bp 4 /* Peripheral Counter 1 Byte bit 4 position. */ -#define XCL_PCNT15_bm (1<<5) /* Peripheral Counter 1 Byte bit 5 mask. */ -#define XCL_PCNT15_bp 5 /* Peripheral Counter 1 Byte bit 5 position. */ -#define XCL_PCNT16_bm (1<<6) /* Peripheral Counter 1 Byte bit 6 mask. */ -#define XCL_PCNT16_bp 6 /* Peripheral Counter 1 Byte bit 6 position. */ -#define XCL_PCNT17_bm (1<<7) /* Peripheral Counter 1 Byte bit 7 mask. */ -#define XCL_PCNT17_bp 7 /* Peripheral Counter 1 Byte bit 7 position. */ - -#define XCL_PCNT21_gm 0xF0 /* Peripheral High Counter 2 Bits group mask. */ -#define XCL_PCNT21_gp 4 /* Peripheral High Counter 2 Bits group position. */ -#define XCL_PCNT210_bm (1<<4) /* Peripheral High Counter 2 Bits bit 0 mask. */ -#define XCL_PCNT210_bp 4 /* Peripheral High Counter 2 Bits bit 0 position. */ -#define XCL_PCNT211_bm (1<<5) /* Peripheral High Counter 2 Bits bit 1 mask. */ -#define XCL_PCNT211_bp 5 /* Peripheral High Counter 2 Bits bit 1 position. */ -#define XCL_PCNT212_bm (1<<6) /* Peripheral High Counter 2 Bits bit 2 mask. */ -#define XCL_PCNT212_bp 6 /* Peripheral High Counter 2 Bits bit 2 position. */ -#define XCL_PCNT213_bm (1<<7) /* Peripheral High Counter 2 Bits bit 3 mask. */ -#define XCL_PCNT213_bp 7 /* Peripheral High Counter 2 Bits bit 3 position. */ - -#define XCL_PCNT20_gm 0x0F /* Peripheral Low Counter 2 Bits group mask. */ -#define XCL_PCNT20_gp 0 /* Peripheral Low Counter 2 Bits group position. */ -#define XCL_PCNT200_bm (1<<0) /* Peripheral Low Counter 2 Bits bit 0 mask. */ -#define XCL_PCNT200_bp 0 /* Peripheral Low Counter 2 Bits bit 0 position. */ -#define XCL_PCNT201_bm (1<<1) /* Peripheral Low Counter 2 Bits bit 1 mask. */ -#define XCL_PCNT201_bp 1 /* Peripheral Low Counter 2 Bits bit 1 position. */ -#define XCL_PCNT202_bm (1<<2) /* Peripheral Low Counter 2 Bits bit 2 mask. */ -#define XCL_PCNT202_bp 2 /* Peripheral Low Counter 2 Bits bit 2 position. */ -#define XCL_PCNT203_bm (1<<3) /* Peripheral Low Counter 2 Bits bit 3 mask. */ -#define XCL_PCNT203_bp 3 /* Peripheral Low Counter 2 Bits bit 3 position. */ - -/* XCL.CMPL bit masks and bit positions */ -#define XCL_CMPL_gm 0xFF /* TC16 Compare Low Byte group mask. */ -#define XCL_CMPL_gp 0 /* TC16 Compare Low Byte group position. */ -#define XCL_CMPL0_bm (1<<0) /* TC16 Compare Low Byte bit 0 mask. */ -#define XCL_CMPL0_bp 0 /* TC16 Compare Low Byte bit 0 position. */ -#define XCL_CMPL1_bm (1<<1) /* TC16 Compare Low Byte bit 1 mask. */ -#define XCL_CMPL1_bp 1 /* TC16 Compare Low Byte bit 1 position. */ -#define XCL_CMPL2_bm (1<<2) /* TC16 Compare Low Byte bit 2 mask. */ -#define XCL_CMPL2_bp 2 /* TC16 Compare Low Byte bit 2 position. */ -#define XCL_CMPL3_bm (1<<3) /* TC16 Compare Low Byte bit 3 mask. */ -#define XCL_CMPL3_bp 3 /* TC16 Compare Low Byte bit 3 position. */ -#define XCL_CMPL4_bm (1<<4) /* TC16 Compare Low Byte bit 4 mask. */ -#define XCL_CMPL4_bp 4 /* TC16 Compare Low Byte bit 4 position. */ -#define XCL_CMPL5_bm (1<<5) /* TC16 Compare Low Byte bit 5 mask. */ -#define XCL_CMPL5_bp 5 /* TC16 Compare Low Byte bit 5 position. */ -#define XCL_CMPL6_bm (1<<6) /* TC16 Compare Low Byte bit 6 mask. */ -#define XCL_CMPL6_bp 6 /* TC16 Compare Low Byte bit 6 position. */ -#define XCL_CMPL7_bm (1<<7) /* TC16 Compare Low Byte bit 7 mask. */ -#define XCL_CMPL7_bp 7 /* TC16 Compare Low Byte bit 7 position. */ - -#define XCL_BCMP0_gm 0xFF /* BTC0 Compare Byte group mask. */ -#define XCL_BCMP0_gp 0 /* BTC0 Compare Byte group position. */ -#define XCL_BCMP00_bm (1<<0) /* BTC0 Compare Byte bit 0 mask. */ -#define XCL_BCMP00_bp 0 /* BTC0 Compare Byte bit 0 position. */ -#define XCL_BCMP01_bm (1<<1) /* BTC0 Compare Byte bit 1 mask. */ -#define XCL_BCMP01_bp 1 /* BTC0 Compare Byte bit 1 position. */ -#define XCL_BCMP02_bm (1<<2) /* BTC0 Compare Byte bit 2 mask. */ -#define XCL_BCMP02_bp 2 /* BTC0 Compare Byte bit 2 position. */ -#define XCL_BCMP03_bm (1<<3) /* BTC0 Compare Byte bit 3 mask. */ -#define XCL_BCMP03_bp 3 /* BTC0 Compare Byte bit 3 position. */ -#define XCL_BCMP04_bm (1<<4) /* BTC0 Compare Byte bit 4 mask. */ -#define XCL_BCMP04_bp 4 /* BTC0 Compare Byte bit 4 position. */ -#define XCL_BCMP05_bm (1<<5) /* BTC0 Compare Byte bit 5 mask. */ -#define XCL_BCMP05_bp 5 /* BTC0 Compare Byte bit 5 position. */ -#define XCL_BCMP06_bm (1<<6) /* BTC0 Compare Byte bit 6 mask. */ -#define XCL_BCMP06_bp 6 /* BTC0 Compare Byte bit 6 position. */ -#define XCL_BCMP07_bm (1<<7) /* BTC0 Compare Byte bit 7 mask. */ -#define XCL_BCMP07_bp 7 /* BTC0 Compare Byte bit 7 position. */ - -/* XCL.CMPH bit masks and bit positions */ -#define XCL_CMPH_gm 0xFF /* TC16 Compare High Byte group mask. */ -#define XCL_CMPH_gp 0 /* TC16 Compare High Byte group position. */ -#define XCL_CMPH0_bm (1<<0) /* TC16 Compare High Byte bit 0 mask. */ -#define XCL_CMPH0_bp 0 /* TC16 Compare High Byte bit 0 position. */ -#define XCL_CMPH1_bm (1<<1) /* TC16 Compare High Byte bit 1 mask. */ -#define XCL_CMPH1_bp 1 /* TC16 Compare High Byte bit 1 position. */ -#define XCL_CMPH2_bm (1<<2) /* TC16 Compare High Byte bit 2 mask. */ -#define XCL_CMPH2_bp 2 /* TC16 Compare High Byte bit 2 position. */ -#define XCL_CMPH3_bm (1<<3) /* TC16 Compare High Byte bit 3 mask. */ -#define XCL_CMPH3_bp 3 /* TC16 Compare High Byte bit 3 position. */ -#define XCL_CMPH4_bm (1<<4) /* TC16 Compare High Byte bit 4 mask. */ -#define XCL_CMPH4_bp 4 /* TC16 Compare High Byte bit 4 position. */ -#define XCL_CMPH5_bm (1<<5) /* TC16 Compare High Byte bit 5 mask. */ -#define XCL_CMPH5_bp 5 /* TC16 Compare High Byte bit 5 position. */ -#define XCL_CMPH6_bm (1<<6) /* TC16 Compare High Byte bit 6 mask. */ -#define XCL_CMPH6_bp 6 /* TC16 Compare High Byte bit 6 position. */ -#define XCL_CMPH7_bm (1<<7) /* TC16 Compare High Byte bit 7 mask. */ -#define XCL_CMPH7_bp 7 /* TC16 Compare High Byte bit 7 position. */ - -#define XCL_BCMP1_gm 0xFF /* BTC1 Compare Byte group mask. */ -#define XCL_BCMP1_gp 0 /* BTC1 Compare Byte group position. */ -#define XCL_BCMP10_bm (1<<0) /* BTC1 Compare Byte bit 0 mask. */ -#define XCL_BCMP10_bp 0 /* BTC1 Compare Byte bit 0 position. */ -#define XCL_BCMP11_bm (1<<1) /* BTC1 Compare Byte bit 1 mask. */ -#define XCL_BCMP11_bp 1 /* BTC1 Compare Byte bit 1 position. */ -#define XCL_BCMP12_bm (1<<2) /* BTC1 Compare Byte bit 2 mask. */ -#define XCL_BCMP12_bp 2 /* BTC1 Compare Byte bit 2 position. */ -#define XCL_BCMP13_bm (1<<3) /* BTC1 Compare Byte bit 3 mask. */ -#define XCL_BCMP13_bp 3 /* BTC1 Compare Byte bit 3 position. */ -#define XCL_BCMP14_bm (1<<4) /* BTC1 Compare Byte bit 4 mask. */ -#define XCL_BCMP14_bp 4 /* BTC1 Compare Byte bit 4 position. */ -#define XCL_BCMP15_bm (1<<5) /* BTC1 Compare Byte bit 5 mask. */ -#define XCL_BCMP15_bp 5 /* BTC1 Compare Byte bit 5 position. */ -#define XCL_BCMP16_bm (1<<6) /* BTC1 Compare Byte bit 6 mask. */ -#define XCL_BCMP16_bp 6 /* BTC1 Compare Byte bit 6 position. */ -#define XCL_BCMP17_bm (1<<7) /* BTC1 Compare Byte bit 7 mask. */ -#define XCL_BCMP17_bp 7 /* BTC1 Compare Byte bit 7 position. */ - -/* XCL.PERCAPTL bit masks and bit positions */ -#define XCL_PERL_gm 0xFF /* TC16 Low Byte Period group mask. */ -#define XCL_PERL_gp 0 /* TC16 Low Byte Period group position. */ -#define XCL_PERL0_bm (1<<0) /* TC16 Low Byte Period bit 0 mask. */ -#define XCL_PERL0_bp 0 /* TC16 Low Byte Period bit 0 position. */ -#define XCL_PERL1_bm (1<<1) /* TC16 Low Byte Period bit 1 mask. */ -#define XCL_PERL1_bp 1 /* TC16 Low Byte Period bit 1 position. */ -#define XCL_PERL2_bm (1<<2) /* TC16 Low Byte Period bit 2 mask. */ -#define XCL_PERL2_bp 2 /* TC16 Low Byte Period bit 2 position. */ -#define XCL_PERL3_bm (1<<3) /* TC16 Low Byte Period bit 3 mask. */ -#define XCL_PERL3_bp 3 /* TC16 Low Byte Period bit 3 position. */ -#define XCL_PERL4_bm (1<<4) /* TC16 Low Byte Period bit 4 mask. */ -#define XCL_PERL4_bp 4 /* TC16 Low Byte Period bit 4 position. */ -#define XCL_PERL5_bm (1<<5) /* TC16 Low Byte Period bit 5 mask. */ -#define XCL_PERL5_bp 5 /* TC16 Low Byte Period bit 5 position. */ -#define XCL_PERL6_bm (1<<6) /* TC16 Low Byte Period bit 6 mask. */ -#define XCL_PERL6_bp 6 /* TC16 Low Byte Period bit 6 position. */ -#define XCL_PERL7_bm (1<<7) /* TC16 Low Byte Period bit 7 mask. */ -#define XCL_PERL7_bp 7 /* TC16 Low Byte Period bit 7 position. */ - -#define XCL_CAPTL_gm 0xFF /* TC16 Capture Value Low Byte group mask. */ -#define XCL_CAPTL_gp 0 /* TC16 Capture Value Low Byte group position. */ -#define XCL_CAPTL0_bm (1<<0) /* TC16 Capture Value Low Byte bit 0 mask. */ -#define XCL_CAPTL0_bp 0 /* TC16 Capture Value Low Byte bit 0 position. */ -#define XCL_CAPTL1_bm (1<<1) /* TC16 Capture Value Low Byte bit 1 mask. */ -#define XCL_CAPTL1_bp 1 /* TC16 Capture Value Low Byte bit 1 position. */ -#define XCL_CAPTL2_bm (1<<2) /* TC16 Capture Value Low Byte bit 2 mask. */ -#define XCL_CAPTL2_bp 2 /* TC16 Capture Value Low Byte bit 2 position. */ -#define XCL_CAPTL3_bm (1<<3) /* TC16 Capture Value Low Byte bit 3 mask. */ -#define XCL_CAPTL3_bp 3 /* TC16 Capture Value Low Byte bit 3 position. */ -#define XCL_CAPTL4_bm (1<<4) /* TC16 Capture Value Low Byte bit 4 mask. */ -#define XCL_CAPTL4_bp 4 /* TC16 Capture Value Low Byte bit 4 position. */ -#define XCL_CAPTL5_bm (1<<5) /* TC16 Capture Value Low Byte bit 5 mask. */ -#define XCL_CAPTL5_bp 5 /* TC16 Capture Value Low Byte bit 5 position. */ -#define XCL_CAPTL6_bm (1<<6) /* TC16 Capture Value Low Byte bit 6 mask. */ -#define XCL_CAPTL6_bp 6 /* TC16 Capture Value Low Byte bit 6 position. */ -#define XCL_CAPTL7_bm (1<<7) /* TC16 Capture Value Low Byte bit 7 mask. */ -#define XCL_CAPTL7_bp 7 /* TC16 Capture Value Low Byte bit 7 position. */ - -#define XCL_BPER0_gm 0xFF /* BTC0 Period group mask. */ -#define XCL_BPER0_gp 0 /* BTC0 Period group position. */ -#define XCL_BPER00_bm (1<<0) /* BTC0 Period bit 0 mask. */ -#define XCL_BPER00_bp 0 /* BTC0 Period bit 0 position. */ -#define XCL_BPER01_bm (1<<1) /* BTC0 Period bit 1 mask. */ -#define XCL_BPER01_bp 1 /* BTC0 Period bit 1 position. */ -#define XCL_BPER02_bm (1<<2) /* BTC0 Period bit 2 mask. */ -#define XCL_BPER02_bp 2 /* BTC0 Period bit 2 position. */ -#define XCL_BPER03_bm (1<<3) /* BTC0 Period bit 3 mask. */ -#define XCL_BPER03_bp 3 /* BTC0 Period bit 3 position. */ -#define XCL_BPER04_bm (1<<4) /* BTC0 Period bit 4 mask. */ -#define XCL_BPER04_bp 4 /* BTC0 Period bit 4 position. */ -#define XCL_BPER05_bm (1<<5) /* BTC0 Period bit 5 mask. */ -#define XCL_BPER05_bp 5 /* BTC0 Period bit 5 position. */ -#define XCL_BPER06_bm (1<<6) /* BTC0 Period bit 6 mask. */ -#define XCL_BPER06_bp 6 /* BTC0 Period bit 6 position. */ -#define XCL_BPER07_bm (1<<7) /* BTC0 Period bit 7 mask. */ -#define XCL_BPER07_bp 7 /* BTC0 Period bit 7 position. */ - -#define XCL_BCAPT0_gm 0xFF /* BTC0 Capture Value Byte group mask. */ -#define XCL_BCAPT0_gp 0 /* BTC0 Capture Value Byte group position. */ -#define XCL_BCAPT00_bm (1<<0) /* BTC0 Capture Value Byte bit 0 mask. */ -#define XCL_BCAPT00_bp 0 /* BTC0 Capture Value Byte bit 0 position. */ -#define XCL_BCAPT01_bm (1<<1) /* BTC0 Capture Value Byte bit 1 mask. */ -#define XCL_BCAPT01_bp 1 /* BTC0 Capture Value Byte bit 1 position. */ -#define XCL_BCAPT02_bm (1<<2) /* BTC0 Capture Value Byte bit 2 mask. */ -#define XCL_BCAPT02_bp 2 /* BTC0 Capture Value Byte bit 2 position. */ -#define XCL_BCAPT03_bm (1<<3) /* BTC0 Capture Value Byte bit 3 mask. */ -#define XCL_BCAPT03_bp 3 /* BTC0 Capture Value Byte bit 3 position. */ -#define XCL_BCAPT04_bm (1<<4) /* BTC0 Capture Value Byte bit 4 mask. */ -#define XCL_BCAPT04_bp 4 /* BTC0 Capture Value Byte bit 4 position. */ -#define XCL_BCAPT05_bm (1<<5) /* BTC0 Capture Value Byte bit 5 mask. */ -#define XCL_BCAPT05_bp 5 /* BTC0 Capture Value Byte bit 5 position. */ -#define XCL_BCAPT06_bm (1<<6) /* BTC0 Capture Value Byte bit 6 mask. */ -#define XCL_BCAPT06_bp 6 /* BTC0 Capture Value Byte bit 6 position. */ -#define XCL_BCAPT07_bm (1<<7) /* BTC0 Capture Value Byte bit 7 mask. */ -#define XCL_BCAPT07_bp 7 /* BTC0 Capture Value Byte bit 7 position. */ - -/* XCL.PERCAPTH bit masks and bit positions */ -#define XCL_PERH_gm 0xFF /* TC16 High Byte Period group mask. */ -#define XCL_PERH_gp 0 /* TC16 High Byte Period group position. */ -#define XCL_PERH0_bm (1<<0) /* TC16 High Byte Period bit 0 mask. */ -#define XCL_PERH0_bp 0 /* TC16 High Byte Period bit 0 position. */ -#define XCL_PERH1_bm (1<<1) /* TC16 High Byte Period bit 1 mask. */ -#define XCL_PERH1_bp 1 /* TC16 High Byte Period bit 1 position. */ -#define XCL_PERH2_bm (1<<2) /* TC16 High Byte Period bit 2 mask. */ -#define XCL_PERH2_bp 2 /* TC16 High Byte Period bit 2 position. */ -#define XCL_PERH3_bm (1<<3) /* TC16 High Byte Period bit 3 mask. */ -#define XCL_PERH3_bp 3 /* TC16 High Byte Period bit 3 position. */ -#define XCL_PERH4_bm (1<<4) /* TC16 High Byte Period bit 4 mask. */ -#define XCL_PERH4_bp 4 /* TC16 High Byte Period bit 4 position. */ -#define XCL_PERH5_bm (1<<5) /* TC16 High Byte Period bit 5 mask. */ -#define XCL_PERH5_bp 5 /* TC16 High Byte Period bit 5 position. */ -#define XCL_PERH6_bm (1<<6) /* TC16 High Byte Period bit 6 mask. */ -#define XCL_PERH6_bp 6 /* TC16 High Byte Period bit 6 position. */ -#define XCL_PERH7_bm (1<<7) /* TC16 High Byte Period bit 7 mask. */ -#define XCL_PERH7_bp 7 /* TC16 High Byte Period bit 7 position. */ - -#define XCL_CAPTH_gm 0xFF /* TC16 Capture Value High Byte group mask. */ -#define XCL_CAPTH_gp 0 /* TC16 Capture Value High Byte group position. */ -#define XCL_CAPTH0_bm (1<<0) /* TC16 Capture Value High Byte bit 0 mask. */ -#define XCL_CAPTH0_bp 0 /* TC16 Capture Value High Byte bit 0 position. */ -#define XCL_CAPTH1_bm (1<<1) /* TC16 Capture Value High Byte bit 1 mask. */ -#define XCL_CAPTH1_bp 1 /* TC16 Capture Value High Byte bit 1 position. */ -#define XCL_CAPTH2_bm (1<<2) /* TC16 Capture Value High Byte bit 2 mask. */ -#define XCL_CAPTH2_bp 2 /* TC16 Capture Value High Byte bit 2 position. */ -#define XCL_CAPTH3_bm (1<<3) /* TC16 Capture Value High Byte bit 3 mask. */ -#define XCL_CAPTH3_bp 3 /* TC16 Capture Value High Byte bit 3 position. */ -#define XCL_CAPTH4_bm (1<<4) /* TC16 Capture Value High Byte bit 4 mask. */ -#define XCL_CAPTH4_bp 4 /* TC16 Capture Value High Byte bit 4 position. */ -#define XCL_CAPTH5_bm (1<<5) /* TC16 Capture Value High Byte bit 5 mask. */ -#define XCL_CAPTH5_bp 5 /* TC16 Capture Value High Byte bit 5 position. */ -#define XCL_CAPTH6_bm (1<<6) /* TC16 Capture Value High Byte bit 6 mask. */ -#define XCL_CAPTH6_bp 6 /* TC16 Capture Value High Byte bit 6 position. */ -#define XCL_CAPTH7_bm (1<<7) /* TC16 Capture Value High Byte bit 7 mask. */ -#define XCL_CAPTH7_bp 7 /* TC16 Capture Value High Byte bit 7 position. */ - -#define XCL_BPER1_gm 0xFF /* BTC1 Period group mask. */ -#define XCL_BPER1_gp 0 /* BTC1 Period group position. */ -#define XCL_BPER10_bm (1<<0) /* BTC1 Period bit 0 mask. */ -#define XCL_BPER10_bp 0 /* BTC1 Period bit 0 position. */ -#define XCL_BPER11_bm (1<<1) /* BTC1 Period bit 1 mask. */ -#define XCL_BPER11_bp 1 /* BTC1 Period bit 1 position. */ -#define XCL_BPER12_bm (1<<2) /* BTC1 Period bit 2 mask. */ -#define XCL_BPER12_bp 2 /* BTC1 Period bit 2 position. */ -#define XCL_BPER13_bm (1<<3) /* BTC1 Period bit 3 mask. */ -#define XCL_BPER13_bp 3 /* BTC1 Period bit 3 position. */ -#define XCL_BPER14_bm (1<<4) /* BTC1 Period bit 4 mask. */ -#define XCL_BPER14_bp 4 /* BTC1 Period bit 4 position. */ -#define XCL_BPER15_bm (1<<5) /* BTC1 Period bit 5 mask. */ -#define XCL_BPER15_bp 5 /* BTC1 Period bit 5 position. */ -#define XCL_BPER16_bm (1<<6) /* BTC1 Period bit 6 mask. */ -#define XCL_BPER16_bp 6 /* BTC1 Period bit 6 position. */ -#define XCL_BPER17_bm (1<<7) /* BTC1 Period bit 7 mask. */ -#define XCL_BPER17_bp 7 /* BTC1 Period bit 7 position. */ - -#define XCL_BCAPT1_gm 0xFF /* BTC1 Capture Value Byte group mask. */ -#define XCL_BCAPT1_gp 0 /* BTC1 Capture Value Byte group position. */ -#define XCL_BCAPT10_bm (1<<0) /* BTC1 Capture Value Byte bit 0 mask. */ -#define XCL_BCAPT10_bp 0 /* BTC1 Capture Value Byte bit 0 position. */ -#define XCL_BCAPT11_bm (1<<1) /* BTC1 Capture Value Byte bit 1 mask. */ -#define XCL_BCAPT11_bp 1 /* BTC1 Capture Value Byte bit 1 position. */ -#define XCL_BCAPT12_bm (1<<2) /* BTC1 Capture Value Byte bit 2 mask. */ -#define XCL_BCAPT12_bp 2 /* BTC1 Capture Value Byte bit 2 position. */ -#define XCL_BCAPT13_bm (1<<3) /* BTC1 Capture Value Byte bit 3 mask. */ -#define XCL_BCAPT13_bp 3 /* BTC1 Capture Value Byte bit 3 position. */ -#define XCL_BCAPT14_bm (1<<4) /* BTC1 Capture Value Byte bit 4 mask. */ -#define XCL_BCAPT14_bp 4 /* BTC1 Capture Value Byte bit 4 position. */ -#define XCL_BCAPT15_bm (1<<5) /* BTC1 Capture Value Byte bit 5 mask. */ -#define XCL_BCAPT15_bp 5 /* BTC1 Capture Value Byte bit 5 position. */ -#define XCL_BCAPT16_bm (1<<6) /* BTC1 Capture Value Byte bit 6 mask. */ -#define XCL_BCAPT16_bp 6 /* BTC1 Capture Value Byte bit 6 position. */ -#define XCL_BCAPT17_bm (1<<7) /* BTC1 Capture Value Byte bit 7 mask. */ -#define XCL_BCAPT17_bp 7 /* BTC1 Capture Value Byte bit 7 position. */ - -/* TWI - Two-Wire Interface */ -/* TWI.CTRL bit masks and bit positions */ -#define TWI_BRIDGEEN_bm 0x80 /* Bridge Enable bit mask. */ -#define TWI_BRIDGEEN_bp 7 /* Bridge Enable bit position. */ - -#define TWI_SFMPEN_bm 0x40 /* Slave Fast Mode Plus Enable bit mask. */ -#define TWI_SFMPEN_bp 6 /* Slave Fast Mode Plus Enable bit position. */ - -#define TWI_SSDAHOLD_gm 0x30 /* Slave SDA Hold Time Enable group mask. */ -#define TWI_SSDAHOLD_gp 4 /* Slave SDA Hold Time Enable group position. */ -#define TWI_SSDAHOLD0_bm (1<<4) /* Slave SDA Hold Time Enable bit 0 mask. */ -#define TWI_SSDAHOLD0_bp 4 /* Slave SDA Hold Time Enable bit 0 position. */ -#define TWI_SSDAHOLD1_bm (1<<5) /* Slave SDA Hold Time Enable bit 1 mask. */ -#define TWI_SSDAHOLD1_bp 5 /* Slave SDA Hold Time Enable bit 1 position. */ - -#define TWI_FMPEN_bm 0x08 /* FMPLUS Enable bit mask. */ -#define TWI_FMPEN_bp 3 /* FMPLUS Enable bit position. */ - -#define TWI_SDAHOLD_gm 0x06 /* SDA Hold Time Enable group mask. */ -#define TWI_SDAHOLD_gp 1 /* SDA Hold Time Enable group position. */ -#define TWI_SDAHOLD0_bm (1<<1) /* SDA Hold Time Enable bit 0 mask. */ -#define TWI_SDAHOLD0_bp 1 /* SDA Hold Time Enable bit 0 position. */ -#define TWI_SDAHOLD1_bm (1<<2) /* SDA Hold Time Enable bit 1 mask. */ -#define TWI_SDAHOLD1_bp 2 /* SDA Hold Time Enable bit 1 position. */ - -#define TWI_EDIEN_bm 0x01 /* External Driver Interface Enable bit mask. */ -#define TWI_EDIEN_bp 0 /* External Driver Interface Enable bit position. */ - -/* TWI_MASTER.CTRLA bit masks and bit positions */ -#define TWI_MASTER_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ -#define TWI_MASTER_INTLVL_gp 6 /* Interrupt Level group position. */ -#define TWI_MASTER_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ -#define TWI_MASTER_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ -#define TWI_MASTER_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ -#define TWI_MASTER_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ - -#define TWI_MASTER_RIEN_bm 0x20 /* Read Interrupt Enable bit mask. */ -#define TWI_MASTER_RIEN_bp 5 /* Read Interrupt Enable bit position. */ - -#define TWI_MASTER_WIEN_bm 0x10 /* Write Interrupt Enable bit mask. */ -#define TWI_MASTER_WIEN_bp 4 /* Write Interrupt Enable bit position. */ - -#define TWI_MASTER_ENABLE_bm 0x08 /* Enable TWI Master bit mask. */ -#define TWI_MASTER_ENABLE_bp 3 /* Enable TWI Master bit position. */ - -/* TWI_MASTER.CTRLB bit masks and bit positions */ -#define TWI_MASTER_TIMEOUT_gm 0x0C /* Inactive Bus Timeout group mask. */ -#define TWI_MASTER_TIMEOUT_gp 2 /* Inactive Bus Timeout group position. */ -#define TWI_MASTER_TIMEOUT0_bm (1<<2) /* Inactive Bus Timeout bit 0 mask. */ -#define TWI_MASTER_TIMEOUT0_bp 2 /* Inactive Bus Timeout bit 0 position. */ -#define TWI_MASTER_TIMEOUT1_bm (1<<3) /* Inactive Bus Timeout bit 1 mask. */ -#define TWI_MASTER_TIMEOUT1_bp 3 /* Inactive Bus Timeout bit 1 position. */ - -#define TWI_MASTER_QCEN_bm 0x02 /* Quick Command Enable bit mask. */ -#define TWI_MASTER_QCEN_bp 1 /* Quick Command Enable bit position. */ - -#define TWI_MASTER_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ -#define TWI_MASTER_SMEN_bp 0 /* Smart Mode Enable bit position. */ - -#define TWI_MASTER_TTOUTEN_bm 0x10 /* Ttimeout Enable bit mask. */ -#define TWI_MASTER_TTOUTEN_bp 4 /* Ttimeout Enable bit position. */ - -#define TWI_MASTER_TSEXTEN_bm 0x20 /* Slave Extend Timeout Enable bit mask. */ -#define TWI_MASTER_TSEXTEN_bp 5 /* Slave Extend Timeout Enable bit position. */ - -#define TWI_MASTER_TMEXTEN_bm 0x40 /* Master Extend Timeout Enable bit mask. */ -#define TWI_MASTER_TMEXTEN_bp 6 /* Master Extend Timeout Enable bit position. */ - -#define TWI_MASTER_TOIE_bm 0x80 /* Timeout Interrupt Enable bit mask. */ -#define TWI_MASTER_TOIE_bp 7 /* Timeout Interrupt Enable bit position. */ - -/* TWI_MASTER.CTRLC bit masks and bit positions */ -#define TWI_MASTER_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ -#define TWI_MASTER_ACKACT_bp 2 /* Acknowledge Action bit position. */ - -#define TWI_MASTER_CMD_gm 0x03 /* Command group mask. */ -#define TWI_MASTER_CMD_gp 0 /* Command group position. */ -#define TWI_MASTER_CMD0_bm (1<<0) /* Command bit 0 mask. */ -#define TWI_MASTER_CMD0_bp 0 /* Command bit 0 position. */ -#define TWI_MASTER_CMD1_bm (1<<1) /* Command bit 1 mask. */ -#define TWI_MASTER_CMD1_bp 1 /* Command bit 1 position. */ - -/* TWI_MASTER.STATUS bit masks and bit positions */ -#define TWI_MASTER_RIF_bm 0x80 /* Read Interrupt Flag bit mask. */ -#define TWI_MASTER_RIF_bp 7 /* Read Interrupt Flag bit position. */ - -#define TWI_MASTER_WIF_bm 0x40 /* Write Interrupt Flag bit mask. */ -#define TWI_MASTER_WIF_bp 6 /* Write Interrupt Flag bit position. */ - -#define TWI_MASTER_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ -#define TWI_MASTER_CLKHOLD_bp 5 /* Clock Hold bit position. */ - -#define TWI_MASTER_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ -#define TWI_MASTER_RXACK_bp 4 /* Received Acknowledge bit position. */ - -#define TWI_MASTER_ARBLOST_bm 0x08 /* Arbitration Lost bit mask. */ -#define TWI_MASTER_ARBLOST_bp 3 /* Arbitration Lost bit position. */ - -#define TWI_MASTER_BUSERR_bm 0x04 /* Bus Error bit mask. */ -#define TWI_MASTER_BUSERR_bp 2 /* Bus Error bit position. */ - -#define TWI_MASTER_BUSSTATE_gm 0x03 /* Bus State group mask. */ -#define TWI_MASTER_BUSSTATE_gp 0 /* Bus State group position. */ -#define TWI_MASTER_BUSSTATE0_bm (1<<0) /* Bus State bit 0 mask. */ -#define TWI_MASTER_BUSSTATE0_bp 0 /* Bus State bit 0 position. */ -#define TWI_MASTER_BUSSTATE1_bm (1<<1) /* Bus State bit 1 mask. */ -#define TWI_MASTER_BUSSTATE1_bp 1 /* Bus State bit 1 position. */ - -/* TWI_SLAVE.CTRLA bit masks and bit positions */ -#define TWI_SLAVE_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ -#define TWI_SLAVE_INTLVL_gp 6 /* Interrupt Level group position. */ -#define TWI_SLAVE_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ -#define TWI_SLAVE_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ -#define TWI_SLAVE_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ -#define TWI_SLAVE_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ - -#define TWI_SLAVE_DIEN_bm 0x20 /* Data Interrupt Enable bit mask. */ -#define TWI_SLAVE_DIEN_bp 5 /* Data Interrupt Enable bit position. */ - -#define TWI_SLAVE_APIEN_bm 0x10 /* Address/Stop Interrupt Enable bit mask. */ -#define TWI_SLAVE_APIEN_bp 4 /* Address/Stop Interrupt Enable bit position. */ - -#define TWI_SLAVE_ENABLE_bm 0x08 /* Enable TWI Slave bit mask. */ -#define TWI_SLAVE_ENABLE_bp 3 /* Enable TWI Slave bit position. */ - -#define TWI_SLAVE_PIEN_bm 0x04 /* Stop Interrupt Enable bit mask. */ -#define TWI_SLAVE_PIEN_bp 2 /* Stop Interrupt Enable bit position. */ - -#define TWI_SLAVE_PMEN_bm 0x02 /* Promiscuous Mode Enable bit mask. */ -#define TWI_SLAVE_PMEN_bp 1 /* Promiscuous Mode Enable bit position. */ - -#define TWI_SLAVE_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ -#define TWI_SLAVE_SMEN_bp 0 /* Smart Mode Enable bit position. */ - -/* TWI_SLAVE.CTRLB bit masks and bit positions */ -#define TWI_SLAVE_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ -#define TWI_SLAVE_ACKACT_bp 2 /* Acknowledge Action bit position. */ - -#define TWI_SLAVE_CMD_gm 0x03 /* Command group mask. */ -#define TWI_SLAVE_CMD_gp 0 /* Command group position. */ -#define TWI_SLAVE_CMD0_bm (1<<0) /* Command bit 0 mask. */ -#define TWI_SLAVE_CMD0_bp 0 /* Command bit 0 position. */ -#define TWI_SLAVE_CMD1_bm (1<<1) /* Command bit 1 mask. */ -#define TWI_SLAVE_CMD1_bp 1 /* Command bit 1 position. */ - -#define TWI_SLAVE_TTOUTEN_bm 0x10 /* Ttimeout Enable bit mask. */ -#define TWI_SLAVE_TTOUTEN_bp 4 /* Ttimeout Enable bit position. */ - -#define TWI_SLAVE_TOIE_bm 0x80 /* Timeout Interrupt Enable bit mask. */ -#define TWI_SLAVE_TOIE_bp 7 /* Timeout Interrupt Enable bit position. */ - -/* TWI_SLAVE.STATUS bit masks and bit positions */ -#define TWI_SLAVE_DIF_bm 0x80 /* Data Interrupt Flag bit mask. */ -#define TWI_SLAVE_DIF_bp 7 /* Data Interrupt Flag bit position. */ - -#define TWI_SLAVE_APIF_bm 0x40 /* Address/Stop Interrupt Flag bit mask. */ -#define TWI_SLAVE_APIF_bp 6 /* Address/Stop Interrupt Flag bit position. */ - -#define TWI_SLAVE_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ -#define TWI_SLAVE_CLKHOLD_bp 5 /* Clock Hold bit position. */ - -#define TWI_SLAVE_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ -#define TWI_SLAVE_RXACK_bp 4 /* Received Acknowledge bit position. */ - -#define TWI_SLAVE_COLL_bm 0x08 /* Collision bit mask. */ -#define TWI_SLAVE_COLL_bp 3 /* Collision bit position. */ - -#define TWI_SLAVE_BUSERR_bm 0x04 /* Bus Error bit mask. */ -#define TWI_SLAVE_BUSERR_bp 2 /* Bus Error bit position. */ - -#define TWI_SLAVE_DIR_bm 0x02 /* Read/Write Direction bit mask. */ -#define TWI_SLAVE_DIR_bp 1 /* Read/Write Direction bit position. */ - -#define TWI_SLAVE_AP_bm 0x01 /* Slave Address or Stop bit mask. */ -#define TWI_SLAVE_AP_bp 0 /* Slave Address or Stop bit position. */ - -/* TWI_SLAVE.ADDRMASK bit masks and bit positions */ -#define TWI_SLAVE_ADDRMASK_gm 0xFE /* Address Mask group mask. */ -#define TWI_SLAVE_ADDRMASK_gp 1 /* Address Mask group position. */ -#define TWI_SLAVE_ADDRMASK0_bm (1<<1) /* Address Mask bit 0 mask. */ -#define TWI_SLAVE_ADDRMASK0_bp 1 /* Address Mask bit 0 position. */ -#define TWI_SLAVE_ADDRMASK1_bm (1<<2) /* Address Mask bit 1 mask. */ -#define TWI_SLAVE_ADDRMASK1_bp 2 /* Address Mask bit 1 position. */ -#define TWI_SLAVE_ADDRMASK2_bm (1<<3) /* Address Mask bit 2 mask. */ -#define TWI_SLAVE_ADDRMASK2_bp 3 /* Address Mask bit 2 position. */ -#define TWI_SLAVE_ADDRMASK3_bm (1<<4) /* Address Mask bit 3 mask. */ -#define TWI_SLAVE_ADDRMASK3_bp 4 /* Address Mask bit 3 position. */ -#define TWI_SLAVE_ADDRMASK4_bm (1<<5) /* Address Mask bit 4 mask. */ -#define TWI_SLAVE_ADDRMASK4_bp 5 /* Address Mask bit 4 position. */ -#define TWI_SLAVE_ADDRMASK5_bm (1<<6) /* Address Mask bit 5 mask. */ -#define TWI_SLAVE_ADDRMASK5_bp 6 /* Address Mask bit 5 position. */ -#define TWI_SLAVE_ADDRMASK6_bm (1<<7) /* Address Mask bit 6 mask. */ -#define TWI_SLAVE_ADDRMASK6_bp 7 /* Address Mask bit 6 position. */ - -#define TWI_SLAVE_ADDREN_bm 0x01 /* Address Enable bit mask. */ -#define TWI_SLAVE_ADDREN_bp 0 /* Address Enable bit position. */ - -/* TWI_TIMEOUT.TOS bit masks and bit positions */ -#define TWI_TIMEOUT_TTOUTMIF_bm 0x01 /* Master Ttimeout Interrupt Flag bit mask. */ -#define TWI_TIMEOUT_TTOUTMIF_bp 0 /* Master Ttimeout Interrupt Flag bit position. */ - -#define TWI_TIMEOUT_TSEXTIF_bm 0x02 /* Slave Extend Interrupt Flag bit mask. */ -#define TWI_TIMEOUT_TSEXTIF_bp 1 /* Slave Extend Interrupt Flag bit position. */ - -#define TWI_TIMEOUT_TMEXTIF_bm 0x04 /* Master Extend Interrupt Flag bit mask. */ -#define TWI_TIMEOUT_TMEXTIF_bp 2 /* Master Extend Interrupt Flag bit position. */ - -#define TWI_TIMEOUT_TTOUTSIF_bm 0x10 /* Slave Ttimeout Interrupt Flag bit mask. */ -#define TWI_TIMEOUT_TTOUTSIF_bp 4 /* Slave Ttimeout Interrupt Flag bit position. */ - -/* TWI_TIMEOUT.TOCONF bit masks and bit positions */ -#define TWI_TIMEOUT_TTOUTMSEL_gm 0x07 /* Master Ttimeout Select group mask. */ -#define TWI_TIMEOUT_TTOUTMSEL_gp 0 /* Master Ttimeout Select group position. */ -#define TWI_TIMEOUT_TTOUTMSEL0_bm (1<<0) /* Master Ttimeout Select bit 0 mask. */ -#define TWI_TIMEOUT_TTOUTMSEL0_bp 0 /* Master Ttimeout Select bit 0 position. */ -#define TWI_TIMEOUT_TTOUTMSEL1_bm (1<<1) /* Master Ttimeout Select bit 1 mask. */ -#define TWI_TIMEOUT_TTOUTMSEL1_bp 1 /* Master Ttimeout Select bit 1 position. */ -#define TWI_TIMEOUT_TTOUTMSEL2_bm (1<<2) /* Master Ttimeout Select bit 2 mask. */ -#define TWI_TIMEOUT_TTOUTMSEL2_bp 2 /* Master Ttimeout Select bit 2 position. */ - -#define TWI_TIMEOUT_TMSEXTSEL_gm 0x18 /* Master/Slave Timeout Select group mask. */ -#define TWI_TIMEOUT_TMSEXTSEL_gp 3 /* Master/Slave Timeout Select group position. */ -#define TWI_TIMEOUT_TMSEXTSEL0_bm (1<<3) /* Master/Slave Timeout Select bit 0 mask. */ -#define TWI_TIMEOUT_TMSEXTSEL0_bp 3 /* Master/Slave Timeout Select bit 0 position. */ -#define TWI_TIMEOUT_TMSEXTSEL1_bm (1<<4) /* Master/Slave Timeout Select bit 1 mask. */ -#define TWI_TIMEOUT_TMSEXTSEL1_bp 4 /* Master/Slave Timeout Select bit 1 position. */ - -#define TWI_TIMEOUT_TTOUTSSEL_gm 0xE0 /* Slave Ttimeout Select group mask. */ -#define TWI_TIMEOUT_TTOUTSSEL_gp 5 /* Slave Ttimeout Select group position. */ -#define TWI_TIMEOUT_TTOUTSSEL0_bm (1<<5) /* Slave Ttimeout Select bit 0 mask. */ -#define TWI_TIMEOUT_TTOUTSSEL0_bp 5 /* Slave Ttimeout Select bit 0 position. */ -#define TWI_TIMEOUT_TTOUTSSEL1_bm (1<<6) /* Slave Ttimeout Select bit 1 mask. */ -#define TWI_TIMEOUT_TTOUTSSEL1_bp 6 /* Slave Ttimeout Select bit 1 position. */ -#define TWI_TIMEOUT_TTOUTSSEL2_bm (1<<7) /* Slave Ttimeout Select bit 2 mask. */ -#define TWI_TIMEOUT_TTOUTSSEL2_bp 7 /* Slave Ttimeout Select bit 2 position. */ - -/* PORT - Port Configuration */ -/* PORT.INTCTRL bit masks and bit positions */ -#define PORT_INTLVL_gm 0x03 /* Port Interrupt Level group mask. */ -#define PORT_INTLVL_gp 0 /* Port Interrupt Level group position. */ -#define PORT_INTLVL0_bm (1<<0) /* Port Interrupt Level bit 0 mask. */ -#define PORT_INTLVL0_bp 0 /* Port Interrupt Level bit 0 position. */ -#define PORT_INTLVL1_bm (1<<1) /* Port Interrupt Level bit 1 mask. */ -#define PORT_INTLVL1_bp 1 /* Port Interrupt Level bit 1 position. */ - -/* PORT.INTFLAGS bit masks and bit positions */ -#define PORT_INT7IF_bm 0x80 /* Pin 7 Interrupt Flag bit mask. */ -#define PORT_INT7IF_bp 7 /* Pin 7 Interrupt Flag bit position. */ - -#define PORT_INT6IF_bm 0x40 /* Pin 6 Interrupt Flag bit mask. */ -#define PORT_INT6IF_bp 6 /* Pin 6 Interrupt Flag bit position. */ - -#define PORT_INT5IF_bm 0x20 /* Pin 5 Interrupt Flag bit mask. */ -#define PORT_INT5IF_bp 5 /* Pin 5 Interrupt Flag bit position. */ - -#define PORT_INT4IF_bm 0x10 /* Pin 4 Interrupt Flag bit mask. */ -#define PORT_INT4IF_bp 4 /* Pin 4 Interrupt Flag bit position. */ - -#define PORT_INT3IF_bm 0x08 /* Pin 3 Interrupt Flag bit mask. */ -#define PORT_INT3IF_bp 3 /* Pin 3 Interrupt Flag bit position. */ - -#define PORT_INT2IF_bm 0x04 /* Pin 2 Interrupt Flag bit mask. */ -#define PORT_INT2IF_bp 2 /* Pin 2 Interrupt Flag bit position. */ - -#define PORT_INT1IF_bm 0x02 /* Pin 1 Interrupt Flag bit mask. */ -#define PORT_INT1IF_bp 1 /* Pin 1 Interrupt Flag bit position. */ - -#define PORT_INT0IF_bm 0x01 /* Pin 0 Interrupt Flag bit mask. */ -#define PORT_INT0IF_bp 0 /* Pin 0 Interrupt Flag bit position. */ - -/* PORT.REMAP bit masks and bit positions */ -#define PORT_USART0_bm 0x10 /* Usart0 bit mask. */ -#define PORT_USART0_bp 4 /* Usart0 bit position. */ - -#define PORT_TC4D_bm 0x08 /* Timer/Counter 4 Output Compare D bit mask. */ -#define PORT_TC4D_bp 3 /* Timer/Counter 4 Output Compare D bit position. */ - -#define PORT_TC4C_bm 0x04 /* Timer/Counter 4 Output Compare C bit mask. */ -#define PORT_TC4C_bp 2 /* Timer/Counter 4 Output Compare C bit position. */ - -#define PORT_TC4B_bm 0x02 /* Timer/Counter 4 Output Compare B bit mask. */ -#define PORT_TC4B_bp 1 /* Timer/Counter 4 Output Compare B bit position. */ - -#define PORT_TC4A_bm 0x01 /* Timer/Counter 4 Output Compare A bit mask. */ -#define PORT_TC4A_bp 0 /* Timer/Counter 4 Output Compare A bit position. */ - -/* PORT.PIN0CTRL bit masks and bit positions */ -#define PORT_INVEN_bm 0x40 /* Inverted I/O Enable bit mask. */ -#define PORT_INVEN_bp 6 /* Inverted I/O Enable bit position. */ - -#define PORT_OPC_gm 0x38 /* Output/Pull Configuration group mask. */ -#define PORT_OPC_gp 3 /* Output/Pull Configuration group position. */ -#define PORT_OPC0_bm (1<<3) /* Output/Pull Configuration bit 0 mask. */ -#define PORT_OPC0_bp 3 /* Output/Pull Configuration bit 0 position. */ -#define PORT_OPC1_bm (1<<4) /* Output/Pull Configuration bit 1 mask. */ -#define PORT_OPC1_bp 4 /* Output/Pull Configuration bit 1 position. */ -#define PORT_OPC2_bm (1<<5) /* Output/Pull Configuration bit 2 mask. */ -#define PORT_OPC2_bp 5 /* Output/Pull Configuration bit 2 position. */ - -#define PORT_ISC_gm 0x07 /* Input/Sense Configuration group mask. */ -#define PORT_ISC_gp 0 /* Input/Sense Configuration group position. */ -#define PORT_ISC0_bm (1<<0) /* Input/Sense Configuration bit 0 mask. */ -#define PORT_ISC0_bp 0 /* Input/Sense Configuration bit 0 position. */ -#define PORT_ISC1_bm (1<<1) /* Input/Sense Configuration bit 1 mask. */ -#define PORT_ISC1_bp 1 /* Input/Sense Configuration bit 1 position. */ -#define PORT_ISC2_bm (1<<2) /* Input/Sense Configuration bit 2 mask. */ -#define PORT_ISC2_bp 2 /* Input/Sense Configuration bit 2 position. */ - -/* PORT.PIN1CTRL bit masks and bit positions */ -/* PORT_INVEN Predefined. */ -/* PORT_INVEN Predefined. */ - -/* PORT_OPC Predefined. */ -/* PORT_OPC Predefined. */ - -/* PORT_ISC Predefined. */ -/* PORT_ISC Predefined. */ - -/* PORT.PIN2CTRL bit masks and bit positions */ -/* PORT_INVEN Predefined. */ -/* PORT_INVEN Predefined. */ - -/* PORT_OPC Predefined. */ -/* PORT_OPC Predefined. */ - -/* PORT_ISC Predefined. */ -/* PORT_ISC Predefined. */ - -/* PORT.PIN3CTRL bit masks and bit positions */ -/* PORT_INVEN Predefined. */ -/* PORT_INVEN Predefined. */ - -/* PORT_OPC Predefined. */ -/* PORT_OPC Predefined. */ - -/* PORT_ISC Predefined. */ -/* PORT_ISC Predefined. */ - -/* PORT.PIN4CTRL bit masks and bit positions */ -/* PORT_INVEN Predefined. */ -/* PORT_INVEN Predefined. */ - -/* PORT_OPC Predefined. */ -/* PORT_OPC Predefined. */ - -/* PORT_ISC Predefined. */ -/* PORT_ISC Predefined. */ - -/* PORT.PIN5CTRL bit masks and bit positions */ -/* PORT_INVEN Predefined. */ -/* PORT_INVEN Predefined. */ - -/* PORT_OPC Predefined. */ -/* PORT_OPC Predefined. */ - -/* PORT_ISC Predefined. */ -/* PORT_ISC Predefined. */ - -/* PORT.PIN6CTRL bit masks and bit positions */ -/* PORT_INVEN Predefined. */ -/* PORT_INVEN Predefined. */ - -/* PORT_OPC Predefined. */ -/* PORT_OPC Predefined. */ - -/* PORT_ISC Predefined. */ -/* PORT_ISC Predefined. */ - -/* PORT.PIN7CTRL bit masks and bit positions */ -/* PORT_INVEN Predefined. */ -/* PORT_INVEN Predefined. */ - -/* PORT_OPC Predefined. */ -/* PORT_OPC Predefined. */ - -/* PORT_ISC Predefined. */ -/* PORT_ISC Predefined. */ - -/* TC - 16-bit Timer/Counter With PWM */ -/* TC4.CTRLA bit masks and bit positions */ -#define TC4_SYNCHEN_bm 0x40 /* Synchronization Enabled bit mask. */ -#define TC4_SYNCHEN_bp 6 /* Synchronization Enabled bit position. */ - -#define TC4_EVSTART_bm 0x20 /* Start on Next Event bit mask. */ -#define TC4_EVSTART_bp 5 /* Start on Next Event bit position. */ - -#define TC4_UPSTOP_bm 0x10 /* Stop on Next Update bit mask. */ -#define TC4_UPSTOP_bp 4 /* Stop on Next Update bit position. */ - -#define TC4_CLKSEL_gm 0x0F /* Clock Select group mask. */ -#define TC4_CLKSEL_gp 0 /* Clock Select group position. */ -#define TC4_CLKSEL0_bm (1<<0) /* Clock Select bit 0 mask. */ -#define TC4_CLKSEL0_bp 0 /* Clock Select bit 0 position. */ -#define TC4_CLKSEL1_bm (1<<1) /* Clock Select bit 1 mask. */ -#define TC4_CLKSEL1_bp 1 /* Clock Select bit 1 position. */ -#define TC4_CLKSEL2_bm (1<<2) /* Clock Select bit 2 mask. */ -#define TC4_CLKSEL2_bp 2 /* Clock Select bit 2 position. */ -#define TC4_CLKSEL3_bm (1<<3) /* Clock Select bit 3 mask. */ -#define TC4_CLKSEL3_bp 3 /* Clock Select bit 3 position. */ - -/* TC4.CTRLB bit masks and bit positions */ -#define TC4_BYTEM_gm 0xC0 /* Byte Mode group mask. */ -#define TC4_BYTEM_gp 6 /* Byte Mode group position. */ -#define TC4_BYTEM0_bm (1<<6) /* Byte Mode bit 0 mask. */ -#define TC4_BYTEM0_bp 6 /* Byte Mode bit 0 position. */ -#define TC4_BYTEM1_bm (1<<7) /* Byte Mode bit 1 mask. */ -#define TC4_BYTEM1_bp 7 /* Byte Mode bit 1 position. */ - -#define TC4_CIRCEN_gm 0x30 /* Circular Buffer Enable group mask. */ -#define TC4_CIRCEN_gp 4 /* Circular Buffer Enable group position. */ -#define TC4_CIRCEN0_bm (1<<4) /* Circular Buffer Enable bit 0 mask. */ -#define TC4_CIRCEN0_bp 4 /* Circular Buffer Enable bit 0 position. */ -#define TC4_CIRCEN1_bm (1<<5) /* Circular Buffer Enable bit 1 mask. */ -#define TC4_CIRCEN1_bp 5 /* Circular Buffer Enable bit 1 position. */ - -#define TC4_WGMODE_gm 0x07 /* Waveform Generation Mode group mask. */ -#define TC4_WGMODE_gp 0 /* Waveform Generation Mode group position. */ -#define TC4_WGMODE0_bm (1<<0) /* Waveform Generation Mode bit 0 mask. */ -#define TC4_WGMODE0_bp 0 /* Waveform Generation Mode bit 0 position. */ -#define TC4_WGMODE1_bm (1<<1) /* Waveform Generation Mode bit 1 mask. */ -#define TC4_WGMODE1_bp 1 /* Waveform Generation Mode bit 1 position. */ -#define TC4_WGMODE2_bm (1<<2) /* Waveform Generation Mode bit 2 mask. */ -#define TC4_WGMODE2_bp 2 /* Waveform Generation Mode bit 2 position. */ - -/* TC4.CTRLC bit masks and bit positions */ -#define TC4_POLD_bm 0x80 /* Channel D Output Polarity bit mask. */ -#define TC4_POLD_bp 7 /* Channel D Output Polarity bit position. */ - -#define TC4_POLC_bm 0x40 /* Channel C Output Polarity bit mask. */ -#define TC4_POLC_bp 6 /* Channel C Output Polarity bit position. */ - -#define TC4_POLB_bm 0x20 /* Channel B Output Polarity bit mask. */ -#define TC4_POLB_bp 5 /* Channel B Output Polarity bit position. */ - -#define TC4_POLA_bm 0x10 /* Channel A Output Polarity bit mask. */ -#define TC4_POLA_bp 4 /* Channel A Output Polarity bit position. */ - -#define TC4_CMPD_bm 0x08 /* Channel D Compare Output Value bit mask. */ -#define TC4_CMPD_bp 3 /* Channel D Compare Output Value bit position. */ - -#define TC4_CMPC_bm 0x04 /* Channel C Compare Output Value bit mask. */ -#define TC4_CMPC_bp 2 /* Channel C Compare Output Value bit position. */ - -#define TC4_CMPB_bm 0x02 /* Channel B Compare Output Value bit mask. */ -#define TC4_CMPB_bp 1 /* Channel B Compare Output Value bit position. */ - -#define TC4_CMPA_bm 0x01 /* Channel A Compare Output Value bit mask. */ -#define TC4_CMPA_bp 0 /* Channel A Compare Output Value bit position. */ - -#define TC4_HCMPD_bm 0x80 /* High Channel D Compare Output Value bit mask. */ -#define TC4_HCMPD_bp 7 /* High Channel D Compare Output Value bit position. */ - -#define TC4_HCMPC_bm 0x40 /* High Channel C Compare Output Value bit mask. */ -#define TC4_HCMPC_bp 6 /* High Channel C Compare Output Value bit position. */ - -#define TC4_HCMPB_bm 0x20 /* High Channel B Compare Output Value bit mask. */ -#define TC4_HCMPB_bp 5 /* High Channel B Compare Output Value bit position. */ - -#define TC4_HCMPA_bm 0x10 /* High Channel A Compare Output Value bit mask. */ -#define TC4_HCMPA_bp 4 /* High Channel A Compare Output Value bit position. */ - -#define TC4_LCMPD_bm 0x08 /* Low Channel D Compare Output Value bit mask. */ -#define TC4_LCMPD_bp 3 /* Low Channel D Compare Output Value bit position. */ - -#define TC4_LCMPC_bm 0x04 /* Low Channel C Compare Output Value bit mask. */ -#define TC4_LCMPC_bp 2 /* Low Channel C Compare Output Value bit position. */ - -#define TC4_LCMPB_bm 0x02 /* Low Channel B Compare Output Value bit mask. */ -#define TC4_LCMPB_bp 1 /* Low Channel B Compare Output Value bit position. */ - -#define TC4_LCMPA_bm 0x01 /* Low Channel A Compare Output Value bit mask. */ -#define TC4_LCMPA_bp 0 /* Low Channel A Compare Output Value bit position. */ - -/* TC4.CTRLD bit masks and bit positions */ -#define TC4_EVACT_gm 0xE0 /* Event Action group mask. */ -#define TC4_EVACT_gp 5 /* Event Action group position. */ -#define TC4_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ -#define TC4_EVACT0_bp 5 /* Event Action bit 0 position. */ -#define TC4_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ -#define TC4_EVACT1_bp 6 /* Event Action bit 1 position. */ -#define TC4_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ -#define TC4_EVACT2_bp 7 /* Event Action bit 2 position. */ - -#define TC4_EVDLY_bm 0x10 /* Event Delay bit mask. */ -#define TC4_EVDLY_bp 4 /* Event Delay bit position. */ - -#define TC4_EVSEL_gm 0x0F /* Event Source Select group mask. */ -#define TC4_EVSEL_gp 0 /* Event Source Select group position. */ -#define TC4_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ -#define TC4_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ -#define TC4_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ -#define TC4_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ -#define TC4_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ -#define TC4_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ -#define TC4_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ -#define TC4_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ - -/* TC4.CTRLE bit masks and bit positions */ -#define TC4_CCDMODE_gm 0xC0 /* Channel D Compare or Capture Mode group mask. */ -#define TC4_CCDMODE_gp 6 /* Channel D Compare or Capture Mode group position. */ -#define TC4_CCDMODE0_bm (1<<6) /* Channel D Compare or Capture Mode bit 0 mask. */ -#define TC4_CCDMODE0_bp 6 /* Channel D Compare or Capture Mode bit 0 position. */ -#define TC4_CCDMODE1_bm (1<<7) /* Channel D Compare or Capture Mode bit 1 mask. */ -#define TC4_CCDMODE1_bp 7 /* Channel D Compare or Capture Mode bit 1 position. */ - -#define TC4_CCCMODE_gm 0x30 /* Channel C Compare or Capture Mode group mask. */ -#define TC4_CCCMODE_gp 4 /* Channel C Compare or Capture Mode group position. */ -#define TC4_CCCMODE0_bm (1<<4) /* Channel C Compare or Capture Mode bit 0 mask. */ -#define TC4_CCCMODE0_bp 4 /* Channel C Compare or Capture Mode bit 0 position. */ -#define TC4_CCCMODE1_bm (1<<5) /* Channel C Compare or Capture Mode bit 1 mask. */ -#define TC4_CCCMODE1_bp 5 /* Channel C Compare or Capture Mode bit 1 position. */ - -#define TC4_CCBMODE_gm 0x0C /* Channel B Compare or Capture Mode group mask. */ -#define TC4_CCBMODE_gp 2 /* Channel B Compare or Capture Mode group position. */ -#define TC4_CCBMODE0_bm (1<<2) /* Channel B Compare or Capture Mode bit 0 mask. */ -#define TC4_CCBMODE0_bp 2 /* Channel B Compare or Capture Mode bit 0 position. */ -#define TC4_CCBMODE1_bm (1<<3) /* Channel B Compare or Capture Mode bit 1 mask. */ -#define TC4_CCBMODE1_bp 3 /* Channel B Compare or Capture Mode bit 1 position. */ - -#define TC4_CCAMODE_gm 0x03 /* Channel A Compare or Capture Mode group mask. */ -#define TC4_CCAMODE_gp 0 /* Channel A Compare or Capture Mode group position. */ -#define TC4_CCAMODE0_bm (1<<0) /* Channel A Compare or Capture Mode bit 0 mask. */ -#define TC4_CCAMODE0_bp 0 /* Channel A Compare or Capture Mode bit 0 position. */ -#define TC4_CCAMODE1_bm (1<<1) /* Channel A Compare or Capture Mode bit 1 mask. */ -#define TC4_CCAMODE1_bp 1 /* Channel A Compare or Capture Mode bit 1 position. */ - -#define TC4_LCCDMODE_gm 0xC0 /* Channel Low D Compare or Capture Mode group mask. */ -#define TC4_LCCDMODE_gp 6 /* Channel Low D Compare or Capture Mode group position. */ -#define TC4_LCCDMODE0_bm (1<<6) /* Channel Low D Compare or Capture Mode bit 0 mask. */ -#define TC4_LCCDMODE0_bp 6 /* Channel Low D Compare or Capture Mode bit 0 position. */ -#define TC4_LCCDMODE1_bm (1<<7) /* Channel Low D Compare or Capture Mode bit 1 mask. */ -#define TC4_LCCDMODE1_bp 7 /* Channel Low D Compare or Capture Mode bit 1 position. */ - -#define TC4_LCCCMODE_gm 0x30 /* Channel Low C Compare or Capture Mode group mask. */ -#define TC4_LCCCMODE_gp 4 /* Channel Low C Compare or Capture Mode group position. */ -#define TC4_LCCCMODE0_bm (1<<4) /* Channel Low C Compare or Capture Mode bit 0 mask. */ -#define TC4_LCCCMODE0_bp 4 /* Channel Low C Compare or Capture Mode bit 0 position. */ -#define TC4_LCCCMODE1_bm (1<<5) /* Channel Low C Compare or Capture Mode bit 1 mask. */ -#define TC4_LCCCMODE1_bp 5 /* Channel Low C Compare or Capture Mode bit 1 position. */ - -#define TC4_LCCBMODE_gm 0x0C /* Channel Low B Compare or Capture Mode group mask. */ -#define TC4_LCCBMODE_gp 2 /* Channel Low B Compare or Capture Mode group position. */ -#define TC4_LCCBMODE0_bm (1<<2) /* Channel Low B Compare or Capture Mode bit 0 mask. */ -#define TC4_LCCBMODE0_bp 2 /* Channel Low B Compare or Capture Mode bit 0 position. */ -#define TC4_LCCBMODE1_bm (1<<3) /* Channel Low B Compare or Capture Mode bit 1 mask. */ -#define TC4_LCCBMODE1_bp 3 /* Channel Low B Compare or Capture Mode bit 1 position. */ - -#define TC4_LCCAMODE_gm 0x03 /* Channel Low A Compare or Capture Mode group mask. */ -#define TC4_LCCAMODE_gp 0 /* Channel Low A Compare or Capture Mode group position. */ -#define TC4_LCCAMODE0_bm (1<<0) /* Channel Low A Compare or Capture Mode bit 0 mask. */ -#define TC4_LCCAMODE0_bp 0 /* Channel Low A Compare or Capture Mode bit 0 position. */ -#define TC4_LCCAMODE1_bm (1<<1) /* Channel Low A Compare or Capture Mode bit 1 mask. */ -#define TC4_LCCAMODE1_bp 1 /* Channel Low A Compare or Capture Mode bit 1 position. */ - -/* TC4.CTRLF bit masks and bit positions */ -#define TC4_HCCDMODE_gm 0xC0 /* Channel High D Compare or Capture Mode group mask. */ -#define TC4_HCCDMODE_gp 6 /* Channel High D Compare or Capture Mode group position. */ -#define TC4_HCCDMODE0_bm (1<<6) /* Channel High D Compare or Capture Mode bit 0 mask. */ -#define TC4_HCCDMODE0_bp 6 /* Channel High D Compare or Capture Mode bit 0 position. */ -#define TC4_HCCDMODE1_bm (1<<7) /* Channel High D Compare or Capture Mode bit 1 mask. */ -#define TC4_HCCDMODE1_bp 7 /* Channel High D Compare or Capture Mode bit 1 position. */ - -#define TC4_HCCCMODE_gm 0x30 /* Channel High C Compare or Capture Mode group mask. */ -#define TC4_HCCCMODE_gp 4 /* Channel High C Compare or Capture Mode group position. */ -#define TC4_HCCCMODE0_bm (1<<4) /* Channel High C Compare or Capture Mode bit 0 mask. */ -#define TC4_HCCCMODE0_bp 4 /* Channel High C Compare or Capture Mode bit 0 position. */ -#define TC4_HCCCMODE1_bm (1<<5) /* Channel High C Compare or Capture Mode bit 1 mask. */ -#define TC4_HCCCMODE1_bp 5 /* Channel High C Compare or Capture Mode bit 1 position. */ - -#define TC4_HCCBMODE_gm 0x0C /* Channel High B Compare or Capture Mode group mask. */ -#define TC4_HCCBMODE_gp 2 /* Channel High B Compare or Capture Mode group position. */ -#define TC4_HCCBMODE0_bm (1<<2) /* Channel High B Compare or Capture Mode bit 0 mask. */ -#define TC4_HCCBMODE0_bp 2 /* Channel High B Compare or Capture Mode bit 0 position. */ -#define TC4_HCCBMODE1_bm (1<<3) /* Channel High B Compare or Capture Mode bit 1 mask. */ -#define TC4_HCCBMODE1_bp 3 /* Channel High B Compare or Capture Mode bit 1 position. */ - -#define TC4_HCCAMODE_gm 0x03 /* Channel High A Compare or Capture Mode group mask. */ -#define TC4_HCCAMODE_gp 0 /* Channel High A Compare or Capture Mode group position. */ -#define TC4_HCCAMODE0_bm (1<<0) /* Channel High A Compare or Capture Mode bit 0 mask. */ -#define TC4_HCCAMODE0_bp 0 /* Channel High A Compare or Capture Mode bit 0 position. */ -#define TC4_HCCAMODE1_bm (1<<1) /* Channel High A Compare or Capture Mode bit 1 mask. */ -#define TC4_HCCAMODE1_bp 1 /* Channel High A Compare or Capture Mode bit 1 position. */ - -/* TC4.INTCTRLA bit masks and bit positions */ -#define TC4_TRGINTLVL_gm 0x30 /* Timer Trigger Restart Interrupt Level group mask. */ -#define TC4_TRGINTLVL_gp 4 /* Timer Trigger Restart Interrupt Level group position. */ -#define TC4_TRGINTLVL0_bm (1<<4) /* Timer Trigger Restart Interrupt Level bit 0 mask. */ -#define TC4_TRGINTLVL0_bp 4 /* Timer Trigger Restart Interrupt Level bit 0 position. */ -#define TC4_TRGINTLVL1_bm (1<<5) /* Timer Trigger Restart Interrupt Level bit 1 mask. */ -#define TC4_TRGINTLVL1_bp 5 /* Timer Trigger Restart Interrupt Level bit 1 position. */ - -#define TC4_ERRINTLVL_gm 0x0C /* Timer Error Interrupt Level group mask. */ -#define TC4_ERRINTLVL_gp 2 /* Timer Error Interrupt Level group position. */ -#define TC4_ERRINTLVL0_bm (1<<2) /* Timer Error Interrupt Level bit 0 mask. */ -#define TC4_ERRINTLVL0_bp 2 /* Timer Error Interrupt Level bit 0 position. */ -#define TC4_ERRINTLVL1_bm (1<<3) /* Timer Error Interrupt Level bit 1 mask. */ -#define TC4_ERRINTLVL1_bp 3 /* Timer Error Interrupt Level bit 1 position. */ - -#define TC4_OVFINTLVL_gm 0x03 /* Timer Overflow/Underflow Interrupt Level group mask. */ -#define TC4_OVFINTLVL_gp 0 /* Timer Overflow/Underflow Interrupt Level group position. */ -#define TC4_OVFINTLVL0_bm (1<<0) /* Timer Overflow/Underflow Interrupt Level bit 0 mask. */ -#define TC4_OVFINTLVL0_bp 0 /* Timer Overflow/Underflow Interrupt Level bit 0 position. */ -#define TC4_OVFINTLVL1_bm (1<<1) /* Timer Overflow/Underflow Interrupt Level bit 1 mask. */ -#define TC4_OVFINTLVL1_bp 1 /* Timer Overflow/Underflow Interrupt Level bit 1 position. */ - -/* TC4.INTCTRLB bit masks and bit positions */ -#define TC4_CCDINTLVL_gm 0xC0 /* Channel D Compare or Capture Interrupt Level group mask. */ -#define TC4_CCDINTLVL_gp 6 /* Channel D Compare or Capture Interrupt Level group position. */ -#define TC4_CCDINTLVL0_bm (1<<6) /* Channel D Compare or Capture Interrupt Level bit 0 mask. */ -#define TC4_CCDINTLVL0_bp 6 /* Channel D Compare or Capture Interrupt Level bit 0 position. */ -#define TC4_CCDINTLVL1_bm (1<<7) /* Channel D Compare or Capture Interrupt Level bit 1 mask. */ -#define TC4_CCDINTLVL1_bp 7 /* Channel D Compare or Capture Interrupt Level bit 1 position. */ - -#define TC4_CCCINTLVL_gm 0x30 /* Channel C Compare or Capture Interrupt Level group mask. */ -#define TC4_CCCINTLVL_gp 4 /* Channel C Compare or Capture Interrupt Level group position. */ -#define TC4_CCCINTLVL0_bm (1<<4) /* Channel C Compare or Capture Interrupt Level bit 0 mask. */ -#define TC4_CCCINTLVL0_bp 4 /* Channel C Compare or Capture Interrupt Level bit 0 position. */ -#define TC4_CCCINTLVL1_bm (1<<5) /* Channel C Compare or Capture Interrupt Level bit 1 mask. */ -#define TC4_CCCINTLVL1_bp 5 /* Channel C Compare or Capture Interrupt Level bit 1 position. */ - -#define TC4_CCBINTLVL_gm 0x0C /* Channel B Compare or Capture Interrupt Level group mask. */ -#define TC4_CCBINTLVL_gp 2 /* Channel B Compare or Capture Interrupt Level group position. */ -#define TC4_CCBINTLVL0_bm (1<<2) /* Channel B Compare or Capture Interrupt Level bit 0 mask. */ -#define TC4_CCBINTLVL0_bp 2 /* Channel B Compare or Capture Interrupt Level bit 0 position. */ -#define TC4_CCBINTLVL1_bm (1<<3) /* Channel B Compare or Capture Interrupt Level bit 1 mask. */ -#define TC4_CCBINTLVL1_bp 3 /* Channel B Compare or Capture Interrupt Level bit 1 position. */ - -#define TC4_CCAINTLVL_gm 0x03 /* Channel A Compare or Capture Interrupt Level group mask. */ -#define TC4_CCAINTLVL_gp 0 /* Channel A Compare or Capture Interrupt Level group position. */ -#define TC4_CCAINTLVL0_bm (1<<0) /* Channel A Compare or Capture Interrupt Level bit 0 mask. */ -#define TC4_CCAINTLVL0_bp 0 /* Channel A Compare or Capture Interrupt Level bit 0 position. */ -#define TC4_CCAINTLVL1_bm (1<<1) /* Channel A Compare or Capture Interrupt Level bit 1 mask. */ -#define TC4_CCAINTLVL1_bp 1 /* Channel A Compare or Capture Interrupt Level bit 1 position. */ - -#define TC4_LCCDINTLVL_gm 0xC0 /* Channel Low D Compare or Capture Interrupt Level group mask. */ -#define TC4_LCCDINTLVL_gp 6 /* Channel Low D Compare or Capture Interrupt Level group position. */ -#define TC4_LCCDINTLVL0_bm (1<<6) /* Channel Low D Compare or Capture Interrupt Level bit 0 mask. */ -#define TC4_LCCDINTLVL0_bp 6 /* Channel Low D Compare or Capture Interrupt Level bit 0 position. */ -#define TC4_LCCDINTLVL1_bm (1<<7) /* Channel Low D Compare or Capture Interrupt Level bit 1 mask. */ -#define TC4_LCCDINTLVL1_bp 7 /* Channel Low D Compare or Capture Interrupt Level bit 1 position. */ - -#define TC4_LCCCINTLVL_gm 0x30 /* Channel Low C Compare or Capture Interrupt Level group mask. */ -#define TC4_LCCCINTLVL_gp 4 /* Channel Low C Compare or Capture Interrupt Level group position. */ -#define TC4_LCCCINTLVL0_bm (1<<4) /* Channel Low C Compare or Capture Interrupt Level bit 0 mask. */ -#define TC4_LCCCINTLVL0_bp 4 /* Channel Low C Compare or Capture Interrupt Level bit 0 position. */ -#define TC4_LCCCINTLVL1_bm (1<<5) /* Channel Low C Compare or Capture Interrupt Level bit 1 mask. */ -#define TC4_LCCCINTLVL1_bp 5 /* Channel Low C Compare or Capture Interrupt Level bit 1 position. */ - -#define TC4_LCCBINTLVL_gm 0x0C /* Channel Low B Compare or Capture Interrupt Level group mask. */ -#define TC4_LCCBINTLVL_gp 2 /* Channel Low B Compare or Capture Interrupt Level group position. */ -#define TC4_LCCBINTLVL0_bm (1<<2) /* Channel Low B Compare or Capture Interrupt Level bit 0 mask. */ -#define TC4_LCCBINTLVL0_bp 2 /* Channel Low B Compare or Capture Interrupt Level bit 0 position. */ -#define TC4_LCCBINTLVL1_bm (1<<3) /* Channel Low B Compare or Capture Interrupt Level bit 1 mask. */ -#define TC4_LCCBINTLVL1_bp 3 /* Channel Low B Compare or Capture Interrupt Level bit 1 position. */ - -#define TC4_LCCAINTLVL_gm 0x03 /* Channel Low A Compare or Capture Interrupt Level group mask. */ -#define TC4_LCCAINTLVL_gp 0 /* Channel Low A Compare or Capture Interrupt Level group position. */ -#define TC4_LCCAINTLVL0_bm (1<<0) /* Channel Low A Compare or Capture Interrupt Level bit 0 mask. */ -#define TC4_LCCAINTLVL0_bp 0 /* Channel Low A Compare or Capture Interrupt Level bit 0 position. */ -#define TC4_LCCAINTLVL1_bm (1<<1) /* Channel Low A Compare or Capture Interrupt Level bit 1 mask. */ -#define TC4_LCCAINTLVL1_bp 1 /* Channel Low A Compare or Capture Interrupt Level bit 1 position. */ - -/* TC4.CTRLGCLR bit masks and bit positions */ -#define TC4_STOP_bm 0x20 /* Timer/Counter Stop bit mask. */ -#define TC4_STOP_bp 5 /* Timer/Counter Stop bit position. */ - -#define TC4_CMD_gm 0x0C /* Command group mask. */ -#define TC4_CMD_gp 2 /* Command group position. */ -#define TC4_CMD0_bm (1<<2) /* Command bit 0 mask. */ -#define TC4_CMD0_bp 2 /* Command bit 0 position. */ -#define TC4_CMD1_bm (1<<3) /* Command bit 1 mask. */ -#define TC4_CMD1_bp 3 /* Command bit 1 position. */ - -#define TC4_LUPD_bm 0x02 /* Lock Update bit mask. */ -#define TC4_LUPD_bp 1 /* Lock Update bit position. */ - -#define TC4_DIR_bm 0x01 /* Counter Direction bit mask. */ -#define TC4_DIR_bp 0 /* Counter Direction bit position. */ - -/* TC4.CTRLGSET bit masks and bit positions */ -/* TC4_STOP Predefined. */ -/* TC4_STOP Predefined. */ - -/* TC4_CMD Predefined. */ -/* TC4_CMD Predefined. */ - -/* TC4_LUPD Predefined. */ -/* TC4_LUPD Predefined. */ - -/* TC4_DIR Predefined. */ -/* TC4_DIR Predefined. */ - -/* TC4.CTRLHCLR bit masks and bit positions */ -#define TC4_CCDBV_bm 0x10 /* Channel D Compare or Capture Buffer Valid bit mask. */ -#define TC4_CCDBV_bp 4 /* Channel D Compare or Capture Buffer Valid bit position. */ - -#define TC4_CCCBV_bm 0x08 /* Channel C Compare or Capture Buffer Valid bit mask. */ -#define TC4_CCCBV_bp 3 /* Channel C Compare or Capture Buffer Valid bit position. */ - -#define TC4_CCBBV_bm 0x04 /* Channel B Compare or Capture Buffer Valid bit mask. */ -#define TC4_CCBBV_bp 2 /* Channel B Compare or Capture Buffer Valid bit position. */ - -#define TC4_CCABV_bm 0x02 /* Channel A Compare or Capture Buffer Valid bit mask. */ -#define TC4_CCABV_bp 1 /* Channel A Compare or Capture Buffer Valid bit position. */ - -#define TC4_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ -#define TC4_PERBV_bp 0 /* Period Buffer Valid bit position. */ - -#define TC4_LCCDBV_bm 0x10 /* Channel Low D Compare or Capture Buffer Valid bit mask. */ -#define TC4_LCCDBV_bp 4 /* Channel Low D Compare or Capture Buffer Valid bit position. */ - -#define TC4_LCCCBV_bm 0x08 /* Channel Low C Compare or Capture Buffer Valid bit mask. */ -#define TC4_LCCCBV_bp 3 /* Channel Low C Compare or Capture Buffer Valid bit position. */ - -#define TC4_LCCBBV_bm 0x04 /* Channel Low B Compare or Capture Buffer Valid bit mask. */ -#define TC4_LCCBBV_bp 2 /* Channel Low B Compare or Capture Buffer Valid bit position. */ - -#define TC4_LCCABV_bm 0x02 /* Channel Low A Compare or Capture Buffer Valid bit mask. */ -#define TC4_LCCABV_bp 1 /* Channel Low A Compare or Capture Buffer Valid bit position. */ - -#define TC4_LPERBV_bm 0x01 /* Period Low Buffer Valid bit mask. */ -#define TC4_LPERBV_bp 0 /* Period Low Buffer Valid bit position. */ - -/* TC4.CTRLHSET bit masks and bit positions */ -/* TC4_CCDBV Predefined. */ -/* TC4_CCDBV Predefined. */ - -/* TC4_CCCBV Predefined. */ -/* TC4_CCCBV Predefined. */ - -/* TC4_CCBBV Predefined. */ -/* TC4_CCBBV Predefined. */ - -/* TC4_CCABV Predefined. */ -/* TC4_CCABV Predefined. */ - -/* TC4_PERBV Predefined. */ -/* TC4_PERBV Predefined. */ - -/* TC4_LCCDBV Predefined. */ -/* TC4_LCCDBV Predefined. */ - -/* TC4_LCCCBV Predefined. */ -/* TC4_LCCCBV Predefined. */ - -/* TC4_LCCBBV Predefined. */ -/* TC4_LCCBBV Predefined. */ - -/* TC4_LCCABV Predefined. */ -/* TC4_LCCABV Predefined. */ - -/* TC4_LPERBV Predefined. */ -/* TC4_LPERBV Predefined. */ - -/* TC4.INTFLAGS bit masks and bit positions */ -#define TC4_CCDIF_bm 0x80 /* Channel D Compare or Capture Interrupt Flag bit mask. */ -#define TC4_CCDIF_bp 7 /* Channel D Compare or Capture Interrupt Flag bit position. */ - -#define TC4_CCCIF_bm 0x40 /* Channel C Compare or Capture Interrupt Flag bit mask. */ -#define TC4_CCCIF_bp 6 /* Channel C Compare or Capture Interrupt Flag bit position. */ - -#define TC4_CCBIF_bm 0x20 /* Channel B Compare or Capture Interrupt Flag bit mask. */ -#define TC4_CCBIF_bp 5 /* Channel B Compare or Capture Interrupt Flag bit position. */ - -#define TC4_CCAIF_bm 0x10 /* Channel A Compare or Capture Interrupt Flag bit mask. */ -#define TC4_CCAIF_bp 4 /* Channel A Compare or Capture Interrupt Flag bit position. */ - -#define TC4_TRGIF_bm 0x04 /* Trigger Restart Interrupt Flag bit mask. */ -#define TC4_TRGIF_bp 2 /* Trigger Restart Interrupt Flag bit position. */ - -#define TC4_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ -#define TC4_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ - -#define TC4_OVFIF_bm 0x01 /* Overflow/Underflow Interrupt Flag bit mask. */ -#define TC4_OVFIF_bp 0 /* Overflow/Underflow Interrupt Flag bit position. */ - -#define TC4_LCCDIF_bm 0x80 /* Channel Low D Compare or Capture Interrupt Flag bit mask. */ -#define TC4_LCCDIF_bp 7 /* Channel Low D Compare or Capture Interrupt Flag bit position. */ - -#define TC4_LCCCIF_bm 0x40 /* Channel Low C Compare or Capture Interrupt Flag bit mask. */ -#define TC4_LCCCIF_bp 6 /* Channel Low C Compare or Capture Interrupt Flag bit position. */ - -#define TC4_LCCBIF_bm 0x20 /* Channel Low B Compare or Capture Interrupt Flag bit mask. */ -#define TC4_LCCBIF_bp 5 /* Channel Low B Compare or Capture Interrupt Flag bit position. */ - -#define TC4_LCCAIF_bm 0x10 /* Channel Low A Compare or Capture Interrupt Flag bit mask. */ -#define TC4_LCCAIF_bp 4 /* Channel Low A Compare or Capture Interrupt Flag bit position. */ - -/* TC5.CTRLA bit masks and bit positions */ -#define TC5_SYNCHEN_bm 0x40 /* Synchronization Enabled bit mask. */ -#define TC5_SYNCHEN_bp 6 /* Synchronization Enabled bit position. */ - -#define TC5_EVSTART_bm 0x20 /* Start on Next Event bit mask. */ -#define TC5_EVSTART_bp 5 /* Start on Next Event bit position. */ - -#define TC5_UPSTOP_bm 0x10 /* Stop on Next Update bit mask. */ -#define TC5_UPSTOP_bp 4 /* Stop on Next Update bit position. */ - -#define TC5_CLKSEL_gm 0x0F /* Clock Select group mask. */ -#define TC5_CLKSEL_gp 0 /* Clock Select group position. */ -#define TC5_CLKSEL0_bm (1<<0) /* Clock Select bit 0 mask. */ -#define TC5_CLKSEL0_bp 0 /* Clock Select bit 0 position. */ -#define TC5_CLKSEL1_bm (1<<1) /* Clock Select bit 1 mask. */ -#define TC5_CLKSEL1_bp 1 /* Clock Select bit 1 position. */ -#define TC5_CLKSEL2_bm (1<<2) /* Clock Select bit 2 mask. */ -#define TC5_CLKSEL2_bp 2 /* Clock Select bit 2 position. */ -#define TC5_CLKSEL3_bm (1<<3) /* Clock Select bit 3 mask. */ -#define TC5_CLKSEL3_bp 3 /* Clock Select bit 3 position. */ - -/* TC5.CTRLB bit masks and bit positions */ -#define TC5_BYTEM_gm 0xC0 /* Byte Mode group mask. */ -#define TC5_BYTEM_gp 6 /* Byte Mode group position. */ -#define TC5_BYTEM0_bm (1<<6) /* Byte Mode bit 0 mask. */ -#define TC5_BYTEM0_bp 6 /* Byte Mode bit 0 position. */ -#define TC5_BYTEM1_bm (1<<7) /* Byte Mode bit 1 mask. */ -#define TC5_BYTEM1_bp 7 /* Byte Mode bit 1 position. */ - -#define TC5_CIRCEN_gm 0x30 /* Circular Buffer Enable group mask. */ -#define TC5_CIRCEN_gp 4 /* Circular Buffer Enable group position. */ -#define TC5_CIRCEN0_bm (1<<4) /* Circular Buffer Enable bit 0 mask. */ -#define TC5_CIRCEN0_bp 4 /* Circular Buffer Enable bit 0 position. */ -#define TC5_CIRCEN1_bm (1<<5) /* Circular Buffer Enable bit 1 mask. */ -#define TC5_CIRCEN1_bp 5 /* Circular Buffer Enable bit 1 position. */ - -#define TC5_WGMODE_gm 0x07 /* Waveform Generation Mode group mask. */ -#define TC5_WGMODE_gp 0 /* Waveform Generation Mode group position. */ -#define TC5_WGMODE0_bm (1<<0) /* Waveform Generation Mode bit 0 mask. */ -#define TC5_WGMODE0_bp 0 /* Waveform Generation Mode bit 0 position. */ -#define TC5_WGMODE1_bm (1<<1) /* Waveform Generation Mode bit 1 mask. */ -#define TC5_WGMODE1_bp 1 /* Waveform Generation Mode bit 1 position. */ -#define TC5_WGMODE2_bm (1<<2) /* Waveform Generation Mode bit 2 mask. */ -#define TC5_WGMODE2_bp 2 /* Waveform Generation Mode bit 2 position. */ - -/* TC5.CTRLC bit masks and bit positions */ -#define TC5_POLB_bm 0x20 /* Channel B Output Polarity bit mask. */ -#define TC5_POLB_bp 5 /* Channel B Output Polarity bit position. */ - -#define TC5_POLA_bm 0x10 /* Channel A Output Polarity bit mask. */ -#define TC5_POLA_bp 4 /* Channel A Output Polarity bit position. */ - -#define TC5_CMPB_bm 0x02 /* Channel B Compare Output Value bit mask. */ -#define TC5_CMPB_bp 1 /* Channel B Compare Output Value bit position. */ - -#define TC5_CMPA_bm 0x01 /* Channel A Compare Output Value bit mask. */ -#define TC5_CMPA_bp 0 /* Channel A Compare Output Value bit position. */ - -#define TC5_HCMPB_bm 0x20 /* High Channel B Compare Output Value bit mask. */ -#define TC5_HCMPB_bp 5 /* High Channel B Compare Output Value bit position. */ - -#define TC5_HCMPA_bm 0x10 /* High Channel A Compare Output Value bit mask. */ -#define TC5_HCMPA_bp 4 /* High Channel A Compare Output Value bit position. */ - -#define TC5_LCMPB_bm 0x02 /* Low Channel B Compare Output Value bit mask. */ -#define TC5_LCMPB_bp 1 /* Low Channel B Compare Output Value bit position. */ - -#define TC5_LCMPA_bm 0x01 /* Low Channel A Compare Output Value bit mask. */ -#define TC5_LCMPA_bp 0 /* Low Channel A Compare Output Value bit position. */ - -/* TC5.CTRLD bit masks and bit positions */ -#define TC5_EVACT_gm 0xE0 /* Event Action group mask. */ -#define TC5_EVACT_gp 5 /* Event Action group position. */ -#define TC5_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ -#define TC5_EVACT0_bp 5 /* Event Action bit 0 position. */ -#define TC5_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ -#define TC5_EVACT1_bp 6 /* Event Action bit 1 position. */ -#define TC5_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ -#define TC5_EVACT2_bp 7 /* Event Action bit 2 position. */ - -#define TC5_EVDLY_bm 0x10 /* Event Delay bit mask. */ -#define TC5_EVDLY_bp 4 /* Event Delay bit position. */ - -#define TC5_EVSEL_gm 0x0F /* Event Source Select group mask. */ -#define TC5_EVSEL_gp 0 /* Event Source Select group position. */ -#define TC5_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ -#define TC5_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ -#define TC5_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ -#define TC5_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ -#define TC5_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ -#define TC5_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ -#define TC5_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ -#define TC5_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ - -/* TC5.CTRLE bit masks and bit positions */ -#define TC5_CCBMODE_gm 0x0C /* Channel B Compare or Capture Mode group mask. */ -#define TC5_CCBMODE_gp 2 /* Channel B Compare or Capture Mode group position. */ -#define TC5_CCBMODE0_bm (1<<2) /* Channel B Compare or Capture Mode bit 0 mask. */ -#define TC5_CCBMODE0_bp 2 /* Channel B Compare or Capture Mode bit 0 position. */ -#define TC5_CCBMODE1_bm (1<<3) /* Channel B Compare or Capture Mode bit 1 mask. */ -#define TC5_CCBMODE1_bp 3 /* Channel B Compare or Capture Mode bit 1 position. */ - -#define TC5_CCAMODE_gm 0x03 /* Channel A Compare or Capture Mode group mask. */ -#define TC5_CCAMODE_gp 0 /* Channel A Compare or Capture Mode group position. */ -#define TC5_CCAMODE0_bm (1<<0) /* Channel A Compare or Capture Mode bit 0 mask. */ -#define TC5_CCAMODE0_bp 0 /* Channel A Compare or Capture Mode bit 0 position. */ -#define TC5_CCAMODE1_bm (1<<1) /* Channel A Compare or Capture Mode bit 1 mask. */ -#define TC5_CCAMODE1_bp 1 /* Channel A Compare or Capture Mode bit 1 position. */ - -#define TC5_LCCBMODE_gm 0x0C /* Channel Low B Compare or Capture Mode group mask. */ -#define TC5_LCCBMODE_gp 2 /* Channel Low B Compare or Capture Mode group position. */ -#define TC5_LCCBMODE0_bm (1<<2) /* Channel Low B Compare or Capture Mode bit 0 mask. */ -#define TC5_LCCBMODE0_bp 2 /* Channel Low B Compare or Capture Mode bit 0 position. */ -#define TC5_LCCBMODE1_bm (1<<3) /* Channel Low B Compare or Capture Mode bit 1 mask. */ -#define TC5_LCCBMODE1_bp 3 /* Channel Low B Compare or Capture Mode bit 1 position. */ - -#define TC5_LCCAMODE_gm 0x03 /* Channel Low A Compare or Capture Mode group mask. */ -#define TC5_LCCAMODE_gp 0 /* Channel Low A Compare or Capture Mode group position. */ -#define TC5_LCCAMODE0_bm (1<<0) /* Channel Low A Compare or Capture Mode bit 0 mask. */ -#define TC5_LCCAMODE0_bp 0 /* Channel Low A Compare or Capture Mode bit 0 position. */ -#define TC5_LCCAMODE1_bm (1<<1) /* Channel Low A Compare or Capture Mode bit 1 mask. */ -#define TC5_LCCAMODE1_bp 1 /* Channel Low A Compare or Capture Mode bit 1 position. */ - -/* TC5.CTRLF bit masks and bit positions */ -#define TC5_HCCBMODE_gm 0x0C /* Channel High B Compare or Capture Mode group mask. */ -#define TC5_HCCBMODE_gp 2 /* Channel High B Compare or Capture Mode group position. */ -#define TC5_HCCBMODE0_bm (1<<2) /* Channel High B Compare or Capture Mode bit 0 mask. */ -#define TC5_HCCBMODE0_bp 2 /* Channel High B Compare or Capture Mode bit 0 position. */ -#define TC5_HCCBMODE1_bm (1<<3) /* Channel High B Compare or Capture Mode bit 1 mask. */ -#define TC5_HCCBMODE1_bp 3 /* Channel High B Compare or Capture Mode bit 1 position. */ - -#define TC5_HCCAMODE_gm 0x03 /* Channel High A Compare or Capture Mode group mask. */ -#define TC5_HCCAMODE_gp 0 /* Channel High A Compare or Capture Mode group position. */ -#define TC5_HCCAMODE0_bm (1<<0) /* Channel High A Compare or Capture Mode bit 0 mask. */ -#define TC5_HCCAMODE0_bp 0 /* Channel High A Compare or Capture Mode bit 0 position. */ -#define TC5_HCCAMODE1_bm (1<<1) /* Channel High A Compare or Capture Mode bit 1 mask. */ -#define TC5_HCCAMODE1_bp 1 /* Channel High A Compare or Capture Mode bit 1 position. */ - -/* TC5.INTCTRLA bit masks and bit positions */ -#define TC5_TRGINTLVL_gm 0x30 /* Timer Trigger Restart Interrupt Level group mask. */ -#define TC5_TRGINTLVL_gp 4 /* Timer Trigger Restart Interrupt Level group position. */ -#define TC5_TRGINTLVL0_bm (1<<4) /* Timer Trigger Restart Interrupt Level bit 0 mask. */ -#define TC5_TRGINTLVL0_bp 4 /* Timer Trigger Restart Interrupt Level bit 0 position. */ -#define TC5_TRGINTLVL1_bm (1<<5) /* Timer Trigger Restart Interrupt Level bit 1 mask. */ -#define TC5_TRGINTLVL1_bp 5 /* Timer Trigger Restart Interrupt Level bit 1 position. */ - -#define TC5_ERRINTLVL_gm 0x0C /* Timer Error Interrupt Level group mask. */ -#define TC5_ERRINTLVL_gp 2 /* Timer Error Interrupt Level group position. */ -#define TC5_ERRINTLVL0_bm (1<<2) /* Timer Error Interrupt Level bit 0 mask. */ -#define TC5_ERRINTLVL0_bp 2 /* Timer Error Interrupt Level bit 0 position. */ -#define TC5_ERRINTLVL1_bm (1<<3) /* Timer Error Interrupt Level bit 1 mask. */ -#define TC5_ERRINTLVL1_bp 3 /* Timer Error Interrupt Level bit 1 position. */ - -#define TC5_OVFINTLVL_gm 0x03 /* Timer Overflow/Underflow Interrupt Level group mask. */ -#define TC5_OVFINTLVL_gp 0 /* Timer Overflow/Underflow Interrupt Level group position. */ -#define TC5_OVFINTLVL0_bm (1<<0) /* Timer Overflow/Underflow Interrupt Level bit 0 mask. */ -#define TC5_OVFINTLVL0_bp 0 /* Timer Overflow/Underflow Interrupt Level bit 0 position. */ -#define TC5_OVFINTLVL1_bm (1<<1) /* Timer Overflow/Underflow Interrupt Level bit 1 mask. */ -#define TC5_OVFINTLVL1_bp 1 /* Timer Overflow/Underflow Interrupt Level bit 1 position. */ - -/* TC5.INTCTRLB bit masks and bit positions */ -#define TC5_CCBINTLVL_gm 0x0C /* Channel B Compare or Capture Interrupt Level group mask. */ -#define TC5_CCBINTLVL_gp 2 /* Channel B Compare or Capture Interrupt Level group position. */ -#define TC5_CCBINTLVL0_bm (1<<2) /* Channel B Compare or Capture Interrupt Level bit 0 mask. */ -#define TC5_CCBINTLVL0_bp 2 /* Channel B Compare or Capture Interrupt Level bit 0 position. */ -#define TC5_CCBINTLVL1_bm (1<<3) /* Channel B Compare or Capture Interrupt Level bit 1 mask. */ -#define TC5_CCBINTLVL1_bp 3 /* Channel B Compare or Capture Interrupt Level bit 1 position. */ - -#define TC5_CCAINTLVL_gm 0x03 /* Channel A Compare or Capture Interrupt Level group mask. */ -#define TC5_CCAINTLVL_gp 0 /* Channel A Compare or Capture Interrupt Level group position. */ -#define TC5_CCAINTLVL0_bm (1<<0) /* Channel A Compare or Capture Interrupt Level bit 0 mask. */ -#define TC5_CCAINTLVL0_bp 0 /* Channel A Compare or Capture Interrupt Level bit 0 position. */ -#define TC5_CCAINTLVL1_bm (1<<1) /* Channel A Compare or Capture Interrupt Level bit 1 mask. */ -#define TC5_CCAINTLVL1_bp 1 /* Channel A Compare or Capture Interrupt Level bit 1 position. */ - -#define TC5_LCCBINTLVL_gm 0x0C /* Channel Low B Compare or Capture Interrupt Level group mask. */ -#define TC5_LCCBINTLVL_gp 2 /* Channel Low B Compare or Capture Interrupt Level group position. */ -#define TC5_LCCBINTLVL0_bm (1<<2) /* Channel Low B Compare or Capture Interrupt Level bit 0 mask. */ -#define TC5_LCCBINTLVL0_bp 2 /* Channel Low B Compare or Capture Interrupt Level bit 0 position. */ -#define TC5_LCCBINTLVL1_bm (1<<3) /* Channel Low B Compare or Capture Interrupt Level bit 1 mask. */ -#define TC5_LCCBINTLVL1_bp 3 /* Channel Low B Compare or Capture Interrupt Level bit 1 position. */ - -#define TC5_LCCAINTLVL_gm 0x03 /* Channel Low A Compare or Capture Interrupt Level group mask. */ -#define TC5_LCCAINTLVL_gp 0 /* Channel Low A Compare or Capture Interrupt Level group position. */ -#define TC5_LCCAINTLVL0_bm (1<<0) /* Channel Low A Compare or Capture Interrupt Level bit 0 mask. */ -#define TC5_LCCAINTLVL0_bp 0 /* Channel Low A Compare or Capture Interrupt Level bit 0 position. */ -#define TC5_LCCAINTLVL1_bm (1<<1) /* Channel Low A Compare or Capture Interrupt Level bit 1 mask. */ -#define TC5_LCCAINTLVL1_bp 1 /* Channel Low A Compare or Capture Interrupt Level bit 1 position. */ - -/* TC5.CTRLGCLR bit masks and bit positions */ -#define TC5_STOP_bm 0x20 /* Timer/Counter Stop bit mask. */ -#define TC5_STOP_bp 5 /* Timer/Counter Stop bit position. */ - -#define TC5_CMD_gm 0x0C /* Command group mask. */ -#define TC5_CMD_gp 2 /* Command group position. */ -#define TC5_CMD0_bm (1<<2) /* Command bit 0 mask. */ -#define TC5_CMD0_bp 2 /* Command bit 0 position. */ -#define TC5_CMD1_bm (1<<3) /* Command bit 1 mask. */ -#define TC5_CMD1_bp 3 /* Command bit 1 position. */ - -#define TC5_LUPD_bm 0x02 /* Lock Update bit mask. */ -#define TC5_LUPD_bp 1 /* Lock Update bit position. */ - -#define TC5_DIR_bm 0x01 /* Counter Direction bit mask. */ -#define TC5_DIR_bp 0 /* Counter Direction bit position. */ - -/* TC5.CTRLGSET bit masks and bit positions */ -/* TC5_STOP Predefined. */ -/* TC5_STOP Predefined. */ - -/* TC5_CMD Predefined. */ -/* TC5_CMD Predefined. */ - -/* TC5_LUPD Predefined. */ -/* TC5_LUPD Predefined. */ - -/* TC5_DIR Predefined. */ -/* TC5_DIR Predefined. */ - -/* TC5.CTRLHCLR bit masks and bit positions */ -#define TC5_CCBBV_bm 0x04 /* Channel B Compare or Capture Buffer Valid bit mask. */ -#define TC5_CCBBV_bp 2 /* Channel B Compare or Capture Buffer Valid bit position. */ - -#define TC5_CCABV_bm 0x02 /* Channel A Compare or Capture Buffer Valid bit mask. */ -#define TC5_CCABV_bp 1 /* Channel A Compare or Capture Buffer Valid bit position. */ - -#define TC5_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ -#define TC5_PERBV_bp 0 /* Period Buffer Valid bit position. */ - -#define TC5_LCCBBV_bm 0x04 /* Channel Low B Compare or Capture Buffer Valid bit mask. */ -#define TC5_LCCBBV_bp 2 /* Channel Low B Compare or Capture Buffer Valid bit position. */ - -#define TC5_LCCABV_bm 0x02 /* Channel Low A Compare or Capture Buffer Valid bit mask. */ -#define TC5_LCCABV_bp 1 /* Channel Low A Compare or Capture Buffer Valid bit position. */ - -#define TC5_LPERBV_bm 0x01 /* Period Low Buffer Valid bit mask. */ -#define TC5_LPERBV_bp 0 /* Period Low Buffer Valid bit position. */ - -/* TC5.CTRLHSET bit masks and bit positions */ -/* TC5_CCBBV Predefined. */ -/* TC5_CCBBV Predefined. */ - -/* TC5_CCABV Predefined. */ -/* TC5_CCABV Predefined. */ - -/* TC5_PERBV Predefined. */ -/* TC5_PERBV Predefined. */ - -/* TC5_LCCBBV Predefined. */ -/* TC5_LCCBBV Predefined. */ - -/* TC5_LCCABV Predefined. */ -/* TC5_LCCABV Predefined. */ - -/* TC5_LPERBV Predefined. */ -/* TC5_LPERBV Predefined. */ - -/* TC5.INTFLAGS bit masks and bit positions */ -#define TC5_CCBIF_bm 0x20 /* Channel B Compare or Capture Interrupt Flag bit mask. */ -#define TC5_CCBIF_bp 5 /* Channel B Compare or Capture Interrupt Flag bit position. */ - -#define TC5_CCAIF_bm 0x10 /* Channel A Compare or Capture Interrupt Flag bit mask. */ -#define TC5_CCAIF_bp 4 /* Channel A Compare or Capture Interrupt Flag bit position. */ - -#define TC5_TRGIF_bm 0x04 /* Trigger Restart Interrupt Flag bit mask. */ -#define TC5_TRGIF_bp 2 /* Trigger Restart Interrupt Flag bit position. */ - -#define TC5_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ -#define TC5_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ - -#define TC5_OVFIF_bm 0x01 /* Overflow/Underflow Interrupt Flag bit mask. */ -#define TC5_OVFIF_bp 0 /* Overflow/Underflow Interrupt Flag bit position. */ - -#define TC5_LCCBIF_bm 0x20 /* Channel Low B Compare or Capture Interrupt Flag bit mask. */ -#define TC5_LCCBIF_bp 5 /* Channel Low B Compare or Capture Interrupt Flag bit position. */ - -#define TC5_LCCAIF_bm 0x10 /* Channel Low A Compare or Capture Interrupt Flag bit mask. */ -#define TC5_LCCAIF_bp 4 /* Channel Low A Compare or Capture Interrupt Flag bit position. */ - -/* FAULT - Fault Extension */ -/* FAULT.CTRLA bit masks and bit positions */ -#define FAULT_RAMP_gm 0xC0 /* Ramp Mode Selection group mask. */ -#define FAULT_RAMP_gp 6 /* Ramp Mode Selection group position. */ -#define FAULT_RAMP0_bm (1<<6) /* Ramp Mode Selection bit 0 mask. */ -#define FAULT_RAMP0_bp 6 /* Ramp Mode Selection bit 0 position. */ -#define FAULT_RAMP1_bm (1<<7) /* Ramp Mode Selection bit 1 mask. */ -#define FAULT_RAMP1_bp 7 /* Ramp Mode Selection bit 1 position. */ - -#define FAULT_FDDBD_bm 0x20 /* Fault on Debug Break Detection bit mask. */ -#define FAULT_FDDBD_bp 5 /* Fault on Debug Break Detection bit position. */ - -#define FAULT_PORTCTRL_bm 0x10 /* Port Control Mode bit mask. */ -#define FAULT_PORTCTRL_bp 4 /* Port Control Mode bit position. */ - -#define FAULT_FUSE_bm 0x08 /* Fuse State bit mask. */ -#define FAULT_FUSE_bp 3 /* Fuse State bit position. */ - -#define FAULT_FILTERE_bm 0x04 /* Fault E Digital Filter Selection bit mask. */ -#define FAULT_FILTERE_bp 2 /* Fault E Digital Filter Selection bit position. */ - -#define FAULT_SRCE_gm 0x03 /* Fault E Input selection group mask. */ -#define FAULT_SRCE_gp 0 /* Fault E Input selection group position. */ -#define FAULT_SRCE0_bm (1<<0) /* Fault E Input selection bit 0 mask. */ -#define FAULT_SRCE0_bp 0 /* Fault E Input selection bit 0 position. */ -#define FAULT_SRCE1_bm (1<<1) /* Fault E Input selection bit 1 mask. */ -#define FAULT_SRCE1_bp 1 /* Fault E Input selection bit 1 position. */ - -/* FAULT.CTRLB bit masks and bit positions */ -#define FAULT_SOFTA_bm 0x80 /* Fault A Software Mode bit mask. */ -#define FAULT_SOFTA_bp 7 /* Fault A Software Mode bit position. */ - -#define FAULT_HALTA_gm 0x60 /* Fault A Halt Action group mask. */ -#define FAULT_HALTA_gp 5 /* Fault A Halt Action group position. */ -#define FAULT_HALTA0_bm (1<<5) /* Fault A Halt Action bit 0 mask. */ -#define FAULT_HALTA0_bp 5 /* Fault A Halt Action bit 0 position. */ -#define FAULT_HALTA1_bm (1<<6) /* Fault A Halt Action bit 1 mask. */ -#define FAULT_HALTA1_bp 6 /* Fault A Halt Action bit 1 position. */ - -#define FAULT_RESTARTA_bm 0x10 /* Fault A Restart Action bit mask. */ -#define FAULT_RESTARTA_bp 4 /* Fault A Restart Action bit position. */ - -#define FAULT_KEEPA_bm 0x08 /* Fault A Keep Action bit mask. */ -#define FAULT_KEEPA_bp 3 /* Fault A Keep Action bit position. */ - -#define FAULT_SRCA_gm 0x03 /* Fault A Source Selection group mask. */ -#define FAULT_SRCA_gp 0 /* Fault A Source Selection group position. */ -#define FAULT_SRCA0_bm (1<<0) /* Fault A Source Selection bit 0 mask. */ -#define FAULT_SRCA0_bp 0 /* Fault A Source Selection bit 0 position. */ -#define FAULT_SRCA1_bm (1<<1) /* Fault A Source Selection bit 1 mask. */ -#define FAULT_SRCA1_bp 1 /* Fault A Source Selection bit 1 position. */ - -/* FAULT.CTRLC bit masks and bit positions */ -#define FAULT_CAPTA_bm 0x20 /* Fault A Capture bit mask. */ -#define FAULT_CAPTA_bp 5 /* Fault A Capture bit position. */ - -#define FAULT_FILTERA_bm 0x04 /* Fault A Digital Filter Selection bit mask. */ -#define FAULT_FILTERA_bp 2 /* Fault A Digital Filter Selection bit position. */ - -#define FAULT_BLANKA_bm 0x02 /* Fault A Blanking bit mask. */ -#define FAULT_BLANKA_bp 1 /* Fault A Blanking bit position. */ - -#define FAULT_QUALA_bm 0x01 /* Fault A Qualification bit mask. */ -#define FAULT_QUALA_bp 0 /* Fault A Qualification bit position. */ - -/* FAULT.CTRLD bit masks and bit positions */ -#define FAULT_SOFTB_bm 0x80 /* Fault B Software Mode bit mask. */ -#define FAULT_SOFTB_bp 7 /* Fault B Software Mode bit position. */ - -#define FAULT_HALTB_gm 0x60 /* Fault B Halt Action group mask. */ -#define FAULT_HALTB_gp 5 /* Fault B Halt Action group position. */ -#define FAULT_HALTB0_bm (1<<5) /* Fault B Halt Action bit 0 mask. */ -#define FAULT_HALTB0_bp 5 /* Fault B Halt Action bit 0 position. */ -#define FAULT_HALTB1_bm (1<<6) /* Fault B Halt Action bit 1 mask. */ -#define FAULT_HALTB1_bp 6 /* Fault B Halt Action bit 1 position. */ - -#define FAULT_RESTARTB_bm 0x10 /* Fault B Restart Action bit mask. */ -#define FAULT_RESTARTB_bp 4 /* Fault B Restart Action bit position. */ - -#define FAULT_KEEPB_bm 0x08 /* Fault B Keep Action bit mask. */ -#define FAULT_KEEPB_bp 3 /* Fault B Keep Action bit position. */ - -#define FAULT_SRCB_gm 0x03 /* Fault B Source Selection group mask. */ -#define FAULT_SRCB_gp 0 /* Fault B Source Selection group position. */ -#define FAULT_SRCB0_bm (1<<0) /* Fault B Source Selection bit 0 mask. */ -#define FAULT_SRCB0_bp 0 /* Fault B Source Selection bit 0 position. */ -#define FAULT_SRCB1_bm (1<<1) /* Fault B Source Selection bit 1 mask. */ -#define FAULT_SRCB1_bp 1 /* Fault B Source Selection bit 1 position. */ - -/* FAULT.CTRLE bit masks and bit positions */ -#define FAULT_CAPTB_bm 0x20 /* Fault B Capture bit mask. */ -#define FAULT_CAPTB_bp 5 /* Fault B Capture bit position. */ - -#define FAULT_FILTERB_bm 0x04 /* Fault B Digital Filter Selection bit mask. */ -#define FAULT_FILTERB_bp 2 /* Fault B Digital Filter Selection bit position. */ - -#define FAULT_BLANKB_bm 0x02 /* Fault B Blanking bit mask. */ -#define FAULT_BLANKB_bp 1 /* Fault B Blanking bit position. */ - -#define FAULT_QUALB_bm 0x01 /* Fault B Qualification bit mask. */ -#define FAULT_QUALB_bp 0 /* Fault B Qualification bit position. */ - -/* FAULT.STATUS bit masks and bit positions */ -#define FAULT_STATEB_bm 0x80 /* Fault B State bit mask. */ -#define FAULT_STATEB_bp 7 /* Fault B State bit position. */ - -#define FAULT_STATEA_bm 0x40 /* Fault A State bit mask. */ -#define FAULT_STATEA_bp 6 /* Fault A State bit position. */ - -#define FAULT_STATEE_bm 0x20 /* Fault E State bit mask. */ -#define FAULT_STATEE_bp 5 /* Fault E State bit position. */ - -#define FAULT_IDX_bm 0x08 /* Channel Index Flag bit mask. */ -#define FAULT_IDX_bp 3 /* Channel Index Flag bit position. */ - -#define FAULT_FAULTBIN_bm 0x04 /* Fault B Flag bit mask. */ -#define FAULT_FAULTBIN_bp 2 /* Fault B Flag bit position. */ - -#define FAULT_FAULTAIN_bm 0x02 /* Fault A Flag bit mask. */ -#define FAULT_FAULTAIN_bp 1 /* Fault A Flag bit position. */ - -#define FAULT_FAULTEIN_bm 0x01 /* Fault E Flag bit mask. */ -#define FAULT_FAULTEIN_bp 0 /* Fault E Flag bit position. */ - -/* FAULT.CTRLGCLR bit masks and bit positions */ -#define FAULT_HALTBCLR_bm 0x80 /* State B Clear bit mask. */ -#define FAULT_HALTBCLR_bp 7 /* State B Clear bit position. */ - -#define FAULT_HALTACLR_bm 0x40 /* State A Clear bit mask. */ -#define FAULT_HALTACLR_bp 6 /* State A Clear bit position. */ - -#define FAULT_STATEECLR_bm 0x20 /* State E Clear bit mask. */ -#define FAULT_STATEECLR_bp 5 /* State E Clear bit position. */ - -#define FAULT_FAULTB_bm 0x04 /* Fault B Flag bit mask. */ -#define FAULT_FAULTB_bp 2 /* Fault B Flag bit position. */ - -#define FAULT_FAULTA_bm 0x02 /* Fault A Flag bit mask. */ -#define FAULT_FAULTA_bp 1 /* Fault A Flag bit position. */ - -#define FAULT_FAULTE_bm 0x01 /* Fault E Flag bit mask. */ -#define FAULT_FAULTE_bp 0 /* Fault E Flag bit position. */ - -/* FAULT.CTRLGSET bit masks and bit positions */ -#define FAULT_FAULTBSW_bm 0x80 /* Software Fault B bit mask. */ -#define FAULT_FAULTBSW_bp 7 /* Software Fault B bit position. */ - -#define FAULT_FAULTASW_bm 0x40 /* Software Fault A bit mask. */ -#define FAULT_FAULTASW_bp 6 /* Software Fault A bit position. */ - -#define FAULT_FAULTESW_bm 0x20 /* Software Fault E bit mask. */ -#define FAULT_FAULTESW_bp 5 /* Software Fault E bit position. */ - -#define FAULT_IDXCMD_gm 0x18 /* Channel index Command group mask. */ -#define FAULT_IDXCMD_gp 3 /* Channel index Command group position. */ -#define FAULT_IDXCMD0_bm (1<<3) /* Channel index Command bit 0 mask. */ -#define FAULT_IDXCMD0_bp 3 /* Channel index Command bit 0 position. */ -#define FAULT_IDXCMD1_bm (1<<4) /* Channel index Command bit 1 mask. */ -#define FAULT_IDXCMD1_bp 4 /* Channel index Command bit 1 position. */ - -/* WEX - Waveform Extension */ -/* WEX.CTRL bit masks and bit positions */ -#define WEX_UPSEL_bm 0x80 /* Update Source Selection bit mask. */ -#define WEX_UPSEL_bp 7 /* Update Source Selection bit position. */ - -#define WEX_OTMX_gm 0x70 /* Output Matrix group mask. */ -#define WEX_OTMX_gp 4 /* Output Matrix group position. */ -#define WEX_OTMX0_bm (1<<4) /* Output Matrix bit 0 mask. */ -#define WEX_OTMX0_bp 4 /* Output Matrix bit 0 position. */ -#define WEX_OTMX1_bm (1<<5) /* Output Matrix bit 1 mask. */ -#define WEX_OTMX1_bp 5 /* Output Matrix bit 1 position. */ -#define WEX_OTMX2_bm (1<<6) /* Output Matrix bit 2 mask. */ -#define WEX_OTMX2_bp 6 /* Output Matrix bit 2 position. */ - -#define WEX_DTI3EN_bm 0x08 /* Dead-Time Insertion Generator 3 Enable bit mask. */ -#define WEX_DTI3EN_bp 3 /* Dead-Time Insertion Generator 3 Enable bit position. */ - -#define WEX_DTI2EN_bm 0x04 /* Dead-Time Insertion Generator 2 Enable bit mask. */ -#define WEX_DTI2EN_bp 2 /* Dead-Time Insertion Generator 2 Enable bit position. */ - -#define WEX_DTI1EN_bm 0x02 /* Dead-Time Insertion Generator 1 Enable bit mask. */ -#define WEX_DTI1EN_bp 1 /* Dead-Time Insertion Generator 1 Enable bit position. */ - -#define WEX_DTI0EN_bm 0x01 /* Dead-Time Insertion Generator 0 Enable bit mask. */ -#define WEX_DTI0EN_bp 0 /* Dead-Time Insertion Generator 0 Enable bit position. */ - -/* WEX.STATUSCLR bit masks and bit positions */ -#define WEX_SWAPBUF_bm 0x04 /* Swap Buffer Valid bit mask. */ -#define WEX_SWAPBUF_bp 2 /* Swap Buffer Valid bit position. */ - -#define WEX_PGVBUFV_bm 0x02 /* Pattern Generator Value Buffer Valid bit mask. */ -#define WEX_PGVBUFV_bp 1 /* Pattern Generator Value Buffer Valid bit position. */ - -#define WEX_PGOBUFV_bm 0x01 /* Pattern Generator Overwrite Buffer Valid bit mask. */ -#define WEX_PGOBUFV_bp 0 /* Pattern Generator Overwrite Buffer Valid bit position. */ - -/* WEX.STATUSSET bit masks and bit positions */ -/* WEX_SWAPBUF Predefined. */ -/* WEX_SWAPBUF Predefined. */ - -/* WEX_PGVBUFV Predefined. */ -/* WEX_PGVBUFV Predefined. */ - -/* WEX_PGOBUFV Predefined. */ -/* WEX_PGOBUFV Predefined. */ - -/* WEX.SWAP bit masks and bit positions */ -#define WEX_SWAP3_bm 0x08 /* Swap DTI output pair 3 bit mask. */ -#define WEX_SWAP3_bp 3 /* Swap DTI output pair 3 bit position. */ - -#define WEX_SWAP2_bm 0x04 /* Swap DTI output pair 2 bit mask. */ -#define WEX_SWAP2_bp 2 /* Swap DTI output pair 2 bit position. */ - -#define WEX_SWAP1_bm 0x02 /* Swap DTI output pair 1 bit mask. */ -#define WEX_SWAP1_bp 1 /* Swap DTI output pair 1 bit position. */ - -#define WEX_SWAP0_bm 0x01 /* Swap DTI output pair 0 bit mask. */ -#define WEX_SWAP0_bp 0 /* Swap DTI output pair 0 bit position. */ - -/* WEX.SWAPBUF bit masks and bit positions */ -#define WEX_SWAP3BUF_bm 0x08 /* Swap DTI output pair 3 bit mask. */ -#define WEX_SWAP3BUF_bp 3 /* Swap DTI output pair 3 bit position. */ - -#define WEX_SWAP2BUF_bm 0x04 /* Swap DTI output pair 2 bit mask. */ -#define WEX_SWAP2BUF_bp 2 /* Swap DTI output pair 2 bit position. */ - -#define WEX_SWAP1BUF_bm 0x02 /* Swap DTI output pair 1 bit mask. */ -#define WEX_SWAP1BUF_bp 1 /* Swap DTI output pair 1 bit position. */ - -#define WEX_SWAP0BUF_bm 0x01 /* Swap DTI output pair 0 bit mask. */ -#define WEX_SWAP0BUF_bp 0 /* Swap DTI output pair 0 bit position. */ - -/* HIRES - High-Resolution Extension */ -/* HIRES.CTRLA bit masks and bit positions */ -#define HIRES_HRPLUS_gm 0x0C /* High Resolution Plus group mask. */ -#define HIRES_HRPLUS_gp 2 /* High Resolution Plus group position. */ -#define HIRES_HRPLUS0_bm (1<<2) /* High Resolution Plus bit 0 mask. */ -#define HIRES_HRPLUS0_bp 2 /* High Resolution Plus bit 0 position. */ -#define HIRES_HRPLUS1_bm (1<<3) /* High Resolution Plus bit 1 mask. */ -#define HIRES_HRPLUS1_bp 3 /* High Resolution Plus bit 1 position. */ - -#define HIRES_HREN_gm 0x03 /* High Resolution Mode group mask. */ -#define HIRES_HREN_gp 0 /* High Resolution Mode group position. */ -#define HIRES_HREN0_bm (1<<0) /* High Resolution Mode bit 0 mask. */ -#define HIRES_HREN0_bp 0 /* High Resolution Mode bit 0 position. */ -#define HIRES_HREN1_bm (1<<1) /* High Resolution Mode bit 1 mask. */ -#define HIRES_HREN1_bp 1 /* High Resolution Mode bit 1 position. */ - -/* USART - Universal Asynchronous Receiver-Transmitter */ -/* USART.STATUS bit masks and bit positions */ -#define USART_RXCIF_bm 0x80 /* Receive Interrupt Flag bit mask. */ -#define USART_RXCIF_bp 7 /* Receive Interrupt Flag bit position. */ - -#define USART_TXCIF_bm 0x40 /* Transmit Interrupt Flag bit mask. */ -#define USART_TXCIF_bp 6 /* Transmit Interrupt Flag bit position. */ - -#define USART_DREIF_bm 0x20 /* Data Register Empty Flag bit mask. */ -#define USART_DREIF_bp 5 /* Data Register Empty Flag bit position. */ - -#define USART_FERR_bm 0x10 /* Frame Error bit mask. */ -#define USART_FERR_bp 4 /* Frame Error bit position. */ - -#define USART_BUFOVF_bm 0x08 /* Buffer Overflow bit mask. */ -#define USART_BUFOVF_bp 3 /* Buffer Overflow bit position. */ - -#define USART_PERR_bm 0x04 /* Parity Error bit mask. */ -#define USART_PERR_bp 2 /* Parity Error bit position. */ - -#define USART_RXSIF_bm 0x02 /* Receive Start Bit Interrupt Flag bit mask. */ -#define USART_RXSIF_bp 1 /* Receive Start Bit Interrupt Flag bit position. */ - -#define USART_RXB8_bm 0x01 /* Receive Bit 8 bit mask. */ -#define USART_RXB8_bp 0 /* Receive Bit 8 bit position. */ - -#define USART_DRIF_bm 0x01 /* Data Reception Flag bit mask. */ -#define USART_DRIF_bp 0 /* Data Reception Flag bit position. */ - -/* USART.CTRLA bit masks and bit positions */ -#define USART_RXSIE_bm 0x80 /* Receive Start Interrupt Enable bit mask. */ -#define USART_RXSIE_bp 7 /* Receive Start Interrupt Enable bit position. */ - -#define USART_DRIE_bm 0x40 /* Data Reception Interrupt Enable bit mask. */ -#define USART_DRIE_bp 6 /* Data Reception Interrupt Enable bit position. */ - -#define USART_RXCINTLVL_gm 0x30 /* Receive Interrupt Level group mask. */ -#define USART_RXCINTLVL_gp 4 /* Receive Interrupt Level group position. */ -#define USART_RXCINTLVL0_bm (1<<4) /* Receive Interrupt Level bit 0 mask. */ -#define USART_RXCINTLVL0_bp 4 /* Receive Interrupt Level bit 0 position. */ -#define USART_RXCINTLVL1_bm (1<<5) /* Receive Interrupt Level bit 1 mask. */ -#define USART_RXCINTLVL1_bp 5 /* Receive Interrupt Level bit 1 position. */ - -#define USART_TXCINTLVL_gm 0x0C /* Transmit Interrupt Level group mask. */ -#define USART_TXCINTLVL_gp 2 /* Transmit Interrupt Level group position. */ -#define USART_TXCINTLVL0_bm (1<<2) /* Transmit Interrupt Level bit 0 mask. */ -#define USART_TXCINTLVL0_bp 2 /* Transmit Interrupt Level bit 0 position. */ -#define USART_TXCINTLVL1_bm (1<<3) /* Transmit Interrupt Level bit 1 mask. */ -#define USART_TXCINTLVL1_bp 3 /* Transmit Interrupt Level bit 1 position. */ - -#define USART_DREINTLVL_gm 0x03 /* Data Register Empty Interrupt Level group mask. */ -#define USART_DREINTLVL_gp 0 /* Data Register Empty Interrupt Level group position. */ -#define USART_DREINTLVL0_bm (1<<0) /* Data Register Empty Interrupt Level bit 0 mask. */ -#define USART_DREINTLVL0_bp 0 /* Data Register Empty Interrupt Level bit 0 position. */ -#define USART_DREINTLVL1_bm (1<<1) /* Data Register Empty Interrupt Level bit 1 mask. */ -#define USART_DREINTLVL1_bp 1 /* Data Register Empty Interrupt Level bit 1 position. */ - -/* USART.CTRLB bit masks and bit positions */ -#define USART_ONEWIRE_bm 0x80 /* One Wire Mode bit mask. */ -#define USART_ONEWIRE_bp 7 /* One Wire Mode bit position. */ - -#define USART_SFDEN_bm 0x40 /* Start Frame Detection Enable bit mask. */ -#define USART_SFDEN_bp 6 /* Start Frame Detection Enable bit position. */ - -#define USART_RXEN_bm 0x10 /* Receiver Enable bit mask. */ -#define USART_RXEN_bp 4 /* Receiver Enable bit position. */ - -#define USART_TXEN_bm 0x08 /* Transmitter Enable bit mask. */ -#define USART_TXEN_bp 3 /* Transmitter Enable bit position. */ - -#define USART_CLK2X_bm 0x04 /* Double transmission speed bit mask. */ -#define USART_CLK2X_bp 2 /* Double transmission speed bit position. */ - -#define USART_MPCM_bm 0x02 /* Multi-processor Communication Mode bit mask. */ -#define USART_MPCM_bp 1 /* Multi-processor Communication Mode bit position. */ - -#define USART_TXB8_bm 0x01 /* Transmit bit 8 bit mask. */ -#define USART_TXB8_bp 0 /* Transmit bit 8 bit position. */ - -/* USART.CTRLC bit masks and bit positions */ -#define USART_CMODE_gm 0xC0 /* Communication Mode group mask. */ -#define USART_CMODE_gp 6 /* Communication Mode group position. */ -#define USART_CMODE0_bm (1<<6) /* Communication Mode bit 0 mask. */ -#define USART_CMODE0_bp 6 /* Communication Mode bit 0 position. */ -#define USART_CMODE1_bm (1<<7) /* Communication Mode bit 1 mask. */ -#define USART_CMODE1_bp 7 /* Communication Mode bit 1 position. */ - -#define USART_PMODE_gm 0x30 /* Parity Mode group mask. */ -#define USART_PMODE_gp 4 /* Parity Mode group position. */ -#define USART_PMODE0_bm (1<<4) /* Parity Mode bit 0 mask. */ -#define USART_PMODE0_bp 4 /* Parity Mode bit 0 position. */ -#define USART_PMODE1_bm (1<<5) /* Parity Mode bit 1 mask. */ -#define USART_PMODE1_bp 5 /* Parity Mode bit 1 position. */ - -#define USART_SBMODE_bm 0x08 /* Stop Bit Mode bit mask. */ -#define USART_SBMODE_bp 3 /* Stop Bit Mode bit position. */ - -#define USART_CHSIZE_gm 0x07 /* Character Size group mask. */ -#define USART_CHSIZE_gp 0 /* Character Size group position. */ -#define USART_CHSIZE0_bm (1<<0) /* Character Size bit 0 mask. */ -#define USART_CHSIZE0_bp 0 /* Character Size bit 0 position. */ -#define USART_CHSIZE1_bm (1<<1) /* Character Size bit 1 mask. */ -#define USART_CHSIZE1_bp 1 /* Character Size bit 1 position. */ -#define USART_CHSIZE2_bm (1<<2) /* Character Size bit 2 mask. */ -#define USART_CHSIZE2_bp 2 /* Character Size bit 2 position. */ - -/* USART.CTRLD bit masks and bit positions */ -#define USART_DECTYPE_gm 0x30 /* Receive Interrupt Level group mask. */ -#define USART_DECTYPE_gp 4 /* Receive Interrupt Level group position. */ -#define USART_DECTYPE0_bm (1<<4) /* Receive Interrupt Level bit 0 mask. */ -#define USART_DECTYPE0_bp 4 /* Receive Interrupt Level bit 0 position. */ -#define USART_DECTYPE1_bm (1<<5) /* Receive Interrupt Level bit 1 mask. */ -#define USART_DECTYPE1_bp 5 /* Receive Interrupt Level bit 1 position. */ - -#define USART_LUTACT_gm 0x0C /* Transmit Interrupt Level group mask. */ -#define USART_LUTACT_gp 2 /* Transmit Interrupt Level group position. */ -#define USART_LUTACT0_bm (1<<2) /* Transmit Interrupt Level bit 0 mask. */ -#define USART_LUTACT0_bp 2 /* Transmit Interrupt Level bit 0 position. */ -#define USART_LUTACT1_bm (1<<3) /* Transmit Interrupt Level bit 1 mask. */ -#define USART_LUTACT1_bp 3 /* Transmit Interrupt Level bit 1 position. */ - -#define USART_PECACT_gm 0x03 /* Data Register Empty Interrupt Level group mask. */ -#define USART_PECACT_gp 0 /* Data Register Empty Interrupt Level group position. */ -#define USART_PECACT0_bm (1<<0) /* Data Register Empty Interrupt Level bit 0 mask. */ -#define USART_PECACT0_bp 0 /* Data Register Empty Interrupt Level bit 0 position. */ -#define USART_PECACT1_bm (1<<1) /* Data Register Empty Interrupt Level bit 1 mask. */ -#define USART_PECACT1_bp 1 /* Data Register Empty Interrupt Level bit 1 position. */ - -/* USART.BAUDCTRLA bit masks and bit positions */ -#define USART_BSEL_gm 0xFF /* Baud Rate Selection Bits [7:0] group mask. */ -#define USART_BSEL_gp 0 /* Baud Rate Selection Bits [7:0] group position. */ -#define USART_BSEL0_bm (1<<0) /* Baud Rate Selection Bits [7:0] bit 0 mask. */ -#define USART_BSEL0_bp 0 /* Baud Rate Selection Bits [7:0] bit 0 position. */ -#define USART_BSEL1_bm (1<<1) /* Baud Rate Selection Bits [7:0] bit 1 mask. */ -#define USART_BSEL1_bp 1 /* Baud Rate Selection Bits [7:0] bit 1 position. */ -#define USART_BSEL2_bm (1<<2) /* Baud Rate Selection Bits [7:0] bit 2 mask. */ -#define USART_BSEL2_bp 2 /* Baud Rate Selection Bits [7:0] bit 2 position. */ -#define USART_BSEL3_bm (1<<3) /* Baud Rate Selection Bits [7:0] bit 3 mask. */ -#define USART_BSEL3_bp 3 /* Baud Rate Selection Bits [7:0] bit 3 position. */ -#define USART_BSEL4_bm (1<<4) /* Baud Rate Selection Bits [7:0] bit 4 mask. */ -#define USART_BSEL4_bp 4 /* Baud Rate Selection Bits [7:0] bit 4 position. */ -#define USART_BSEL5_bm (1<<5) /* Baud Rate Selection Bits [7:0] bit 5 mask. */ -#define USART_BSEL5_bp 5 /* Baud Rate Selection Bits [7:0] bit 5 position. */ -#define USART_BSEL6_bm (1<<6) /* Baud Rate Selection Bits [7:0] bit 6 mask. */ -#define USART_BSEL6_bp 6 /* Baud Rate Selection Bits [7:0] bit 6 position. */ -#define USART_BSEL7_bm (1<<7) /* Baud Rate Selection Bits [7:0] bit 7 mask. */ -#define USART_BSEL7_bp 7 /* Baud Rate Selection Bits [7:0] bit 7 position. */ - -/* USART.BAUDCTRLB bit masks and bit positions */ -#define USART_BSCALE_gm 0xF0 /* Baud Rate Scale group mask. */ -#define USART_BSCALE_gp 4 /* Baud Rate Scale group position. */ -#define USART_BSCALE0_bm (1<<4) /* Baud Rate Scale bit 0 mask. */ -#define USART_BSCALE0_bp 4 /* Baud Rate Scale bit 0 position. */ -#define USART_BSCALE1_bm (1<<5) /* Baud Rate Scale bit 1 mask. */ -#define USART_BSCALE1_bp 5 /* Baud Rate Scale bit 1 position. */ -#define USART_BSCALE2_bm (1<<6) /* Baud Rate Scale bit 2 mask. */ -#define USART_BSCALE2_bp 6 /* Baud Rate Scale bit 2 position. */ -#define USART_BSCALE3_bm (1<<7) /* Baud Rate Scale bit 3 mask. */ -#define USART_BSCALE3_bp 7 /* Baud Rate Scale bit 3 position. */ - -/* USART_BSEL Predefined. */ -/* USART_BSEL Predefined. */ - -/* SPI - Serial Peripheral Interface */ -/* SPI.CTRL bit masks and bit positions */ -#define SPI_CLK2X_bm 0x80 /* Enable Double Speed bit mask. */ -#define SPI_CLK2X_bp 7 /* Enable Double Speed bit position. */ - -#define SPI_ENABLE_bm 0x40 /* Enable SPI Module bit mask. */ -#define SPI_ENABLE_bp 6 /* Enable SPI Module bit position. */ - -#define SPI_DORD_bm 0x20 /* Data Order Setting bit mask. */ -#define SPI_DORD_bp 5 /* Data Order Setting bit position. */ - -#define SPI_MASTER_bm 0x10 /* Master Operation Enable bit mask. */ -#define SPI_MASTER_bp 4 /* Master Operation Enable bit position. */ - -#define SPI_MODE_gm 0x0C /* SPI Mode group mask. */ -#define SPI_MODE_gp 2 /* SPI Mode group position. */ -#define SPI_MODE0_bm (1<<2) /* SPI Mode bit 0 mask. */ -#define SPI_MODE0_bp 2 /* SPI Mode bit 0 position. */ -#define SPI_MODE1_bm (1<<3) /* SPI Mode bit 1 mask. */ -#define SPI_MODE1_bp 3 /* SPI Mode bit 1 position. */ - -#define SPI_PRESCALER_gm 0x03 /* Prescaler group mask. */ -#define SPI_PRESCALER_gp 0 /* Prescaler group position. */ -#define SPI_PRESCALER0_bm (1<<0) /* Prescaler bit 0 mask. */ -#define SPI_PRESCALER0_bp 0 /* Prescaler bit 0 position. */ -#define SPI_PRESCALER1_bm (1<<1) /* Prescaler bit 1 mask. */ -#define SPI_PRESCALER1_bp 1 /* Prescaler bit 1 position. */ - -/* SPI.INTCTRL bit masks and bit positions */ -#define SPI_RXCIE_bm 0x80 /* Receive Complete Interrupt Enable (In Buffer Modes Only). bit mask. */ -#define SPI_RXCIE_bp 7 /* Receive Complete Interrupt Enable (In Buffer Modes Only). bit position. */ - -#define SPI_TXCIE_bm 0x40 /* Transmit Complete Interrupt Enable (In Buffer Modes Only). bit mask. */ -#define SPI_TXCIE_bp 6 /* Transmit Complete Interrupt Enable (In Buffer Modes Only). bit position. */ - -#define SPI_DREIE_bm 0x20 /* Data Register Empty Interrupt Enable (In Buffer Modes Only). bit mask. */ -#define SPI_DREIE_bp 5 /* Data Register Empty Interrupt Enable (In Buffer Modes Only). bit position. */ - -#define SPI_SSIE_bm 0x10 /* Slave Select Trigger Interrupt Enable (In Buffer Modes Only). bit mask. */ -#define SPI_SSIE_bp 4 /* Slave Select Trigger Interrupt Enable (In Buffer Modes Only). bit position. */ - -#define SPI_INTLVL_gm 0x03 /* Interrupt level group mask. */ -#define SPI_INTLVL_gp 0 /* Interrupt level group position. */ -#define SPI_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */ -#define SPI_INTLVL0_bp 0 /* Interrupt level bit 0 position. */ -#define SPI_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */ -#define SPI_INTLVL1_bp 1 /* Interrupt level bit 1 position. */ - -/* SPI.STATUS bit masks and bit positions */ -#define SPI_IF_bm 0x80 /* Interrupt Flag (In Standard Mode Only). bit mask. */ -#define SPI_IF_bp 7 /* Interrupt Flag (In Standard Mode Only). bit position. */ - -#define SPI_RXCIF_bm 0x80 /* Receive Complete Interrupt Flag (In Buffer Modes Only). bit mask. */ -#define SPI_RXCIF_bp 7 /* Receive Complete Interrupt Flag (In Buffer Modes Only). bit position. */ - -#define SPI_WRCOL_bm 0x40 /* Write Collision Flag (In Standard Mode Only). bit mask. */ -#define SPI_WRCOL_bp 6 /* Write Collision Flag (In Standard Mode Only). bit position. */ - -#define SPI_TXCIF_bm 0x40 /* Transmit Complete Interrupt Flag (In Buffer Modes Only). bit mask. */ -#define SPI_TXCIF_bp 6 /* Transmit Complete Interrupt Flag (In Buffer Modes Only). bit position. */ - -#define SPI_DREIF_bm 0x20 /* Data Register Empty Interrupt Flag (In Buffer Modes Only). bit mask. */ -#define SPI_DREIF_bp 5 /* Data Register Empty Interrupt Flag (In Buffer Modes Only). bit position. */ - -#define SPI_SSIF_bm 0x10 /* Slave Select Trigger Interrupt Flag (In Buffer Modes Only). bit mask. */ -#define SPI_SSIF_bp 4 /* Slave Select Trigger Interrupt Flag (In Buffer Modes Only). bit position. */ - -#define SPI_BUFOVF_bm 0x01 /* Buffer Overflow (In Buffer Modes Only). bit mask. */ -#define SPI_BUFOVF_bp 0 /* Buffer Overflow (In Buffer Modes Only). bit position. */ - -/* SPI.CTRLB bit masks and bit positions */ -#define SPI_BUFMODE_gm 0xC0 /* Buffer Modes group mask. */ -#define SPI_BUFMODE_gp 6 /* Buffer Modes group position. */ -#define SPI_BUFMODE0_bm (1<<6) /* Buffer Modes bit 0 mask. */ -#define SPI_BUFMODE0_bp 6 /* Buffer Modes bit 0 position. */ -#define SPI_BUFMODE1_bm (1<<7) /* Buffer Modes bit 1 mask. */ -#define SPI_BUFMODE1_bp 7 /* Buffer Modes bit 1 position. */ - -#define SPI_SSD_bm 0x04 /* Slave Select Disable bit mask. */ -#define SPI_SSD_bp 2 /* Slave Select Disable bit position. */ - -/* IRCOM - IR Communication Module */ -/* IRCOM.CTRL bit masks and bit positions */ -#define IRCOM_EVSEL_gm 0x0F /* Event Channel Select group mask. */ -#define IRCOM_EVSEL_gp 0 /* Event Channel Select group position. */ -#define IRCOM_EVSEL0_bm (1<<0) /* Event Channel Select bit 0 mask. */ -#define IRCOM_EVSEL0_bp 0 /* Event Channel Select bit 0 position. */ -#define IRCOM_EVSEL1_bm (1<<1) /* Event Channel Select bit 1 mask. */ -#define IRCOM_EVSEL1_bp 1 /* Event Channel Select bit 1 position. */ -#define IRCOM_EVSEL2_bm (1<<2) /* Event Channel Select bit 2 mask. */ -#define IRCOM_EVSEL2_bp 2 /* Event Channel Select bit 2 position. */ -#define IRCOM_EVSEL3_bm (1<<3) /* Event Channel Select bit 3 mask. */ -#define IRCOM_EVSEL3_bp 3 /* Event Channel Select bit 3 position. */ - -/* FUSE - Fuses and Lockbits */ -/* NVM_LOCKBITS.LOCKBITS bit masks and bit positions */ -#define NVM_LOCKBITS_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ -#define NVM_LOCKBITS_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ -#define NVM_LOCKBITS_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ -#define NVM_LOCKBITS_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ -#define NVM_LOCKBITS_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ -#define NVM_LOCKBITS_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ - -#define NVM_LOCKBITS_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ -#define NVM_LOCKBITS_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ -#define NVM_LOCKBITS_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ -#define NVM_LOCKBITS_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ -#define NVM_LOCKBITS_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ -#define NVM_LOCKBITS_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ - -#define NVM_LOCKBITS_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ -#define NVM_LOCKBITS_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ -#define NVM_LOCKBITS_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ -#define NVM_LOCKBITS_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ -#define NVM_LOCKBITS_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ -#define NVM_LOCKBITS_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ - -#define NVM_LOCKBITS_LB_gm 0x03 /* Lock Bits group mask. */ -#define NVM_LOCKBITS_LB_gp 0 /* Lock Bits group position. */ -#define NVM_LOCKBITS_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ -#define NVM_LOCKBITS_LB0_bp 0 /* Lock Bits bit 0 position. */ -#define NVM_LOCKBITS_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ -#define NVM_LOCKBITS_LB1_bp 1 /* Lock Bits bit 1 position. */ - -/* NVM_FUSES.FUSEBYTE1 bit masks and bit positions */ -#define NVM_FUSES_WDWP_gm 0xF0 /* Watchdog Window Timeout Period group mask. */ -#define NVM_FUSES_WDWP_gp 4 /* Watchdog Window Timeout Period group position. */ -#define NVM_FUSES_WDWP0_bm (1<<4) /* Watchdog Window Timeout Period bit 0 mask. */ -#define NVM_FUSES_WDWP0_bp 4 /* Watchdog Window Timeout Period bit 0 position. */ -#define NVM_FUSES_WDWP1_bm (1<<5) /* Watchdog Window Timeout Period bit 1 mask. */ -#define NVM_FUSES_WDWP1_bp 5 /* Watchdog Window Timeout Period bit 1 position. */ -#define NVM_FUSES_WDWP2_bm (1<<6) /* Watchdog Window Timeout Period bit 2 mask. */ -#define NVM_FUSES_WDWP2_bp 6 /* Watchdog Window Timeout Period bit 2 position. */ -#define NVM_FUSES_WDWP3_bm (1<<7) /* Watchdog Window Timeout Period bit 3 mask. */ -#define NVM_FUSES_WDWP3_bp 7 /* Watchdog Window Timeout Period bit 3 position. */ - -#define NVM_FUSES_WDP_gm 0x0F /* Watchdog Timeout Period group mask. */ -#define NVM_FUSES_WDP_gp 0 /* Watchdog Timeout Period group position. */ -#define NVM_FUSES_WDP0_bm (1<<0) /* Watchdog Timeout Period bit 0 mask. */ -#define NVM_FUSES_WDP0_bp 0 /* Watchdog Timeout Period bit 0 position. */ -#define NVM_FUSES_WDP1_bm (1<<1) /* Watchdog Timeout Period bit 1 mask. */ -#define NVM_FUSES_WDP1_bp 1 /* Watchdog Timeout Period bit 1 position. */ -#define NVM_FUSES_WDP2_bm (1<<2) /* Watchdog Timeout Period bit 2 mask. */ -#define NVM_FUSES_WDP2_bp 2 /* Watchdog Timeout Period bit 2 position. */ -#define NVM_FUSES_WDP3_bm (1<<3) /* Watchdog Timeout Period bit 3 mask. */ -#define NVM_FUSES_WDP3_bp 3 /* Watchdog Timeout Period bit 3 position. */ - -/* NVM_FUSES.FUSEBYTE2 bit masks and bit positions */ -#define NVM_FUSES_BOOTRST_bm 0x40 /* Boot Loader Section Reset Vector bit mask. */ -#define NVM_FUSES_BOOTRST_bp 6 /* Boot Loader Section Reset Vector bit position. */ - -#define NVM_FUSES_BODPD_gm 0x03 /* BOD Operation in Power-Down Mode group mask. */ -#define NVM_FUSES_BODPD_gp 0 /* BOD Operation in Power-Down Mode group position. */ -#define NVM_FUSES_BODPD0_bm (1<<0) /* BOD Operation in Power-Down Mode bit 0 mask. */ -#define NVM_FUSES_BODPD0_bp 0 /* BOD Operation in Power-Down Mode bit 0 position. */ -#define NVM_FUSES_BODPD1_bm (1<<1) /* BOD Operation in Power-Down Mode bit 1 mask. */ -#define NVM_FUSES_BODPD1_bp 1 /* BOD Operation in Power-Down Mode bit 1 position. */ - -/* NVM_FUSES.FUSEBYTE4 bit masks and bit positions */ -#define NVM_FUSES_RSTDISBL_bm 0x10 /* External Reset Disable bit mask. */ -#define NVM_FUSES_RSTDISBL_bp 4 /* External Reset Disable bit position. */ - -#define NVM_FUSES_SUT_gm 0x0C /* Start-up Time group mask. */ -#define NVM_FUSES_SUT_gp 2 /* Start-up Time group position. */ -#define NVM_FUSES_SUT0_bm (1<<2) /* Start-up Time bit 0 mask. */ -#define NVM_FUSES_SUT0_bp 2 /* Start-up Time bit 0 position. */ -#define NVM_FUSES_SUT1_bm (1<<3) /* Start-up Time bit 1 mask. */ -#define NVM_FUSES_SUT1_bp 3 /* Start-up Time bit 1 position. */ - -#define NVM_FUSES_WDLOCK_bm 0x02 /* Watchdog Timer Lock bit mask. */ -#define NVM_FUSES_WDLOCK_bp 1 /* Watchdog Timer Lock bit position. */ - -/* NVM_FUSES.FUSEBYTE5 bit masks and bit positions */ -#define NVM_FUSES_BODACT_gm 0x30 /* BOD Operation in Active Mode group mask. */ -#define NVM_FUSES_BODACT_gp 4 /* BOD Operation in Active Mode group position. */ -#define NVM_FUSES_BODACT0_bm (1<<4) /* BOD Operation in Active Mode bit 0 mask. */ -#define NVM_FUSES_BODACT0_bp 4 /* BOD Operation in Active Mode bit 0 position. */ -#define NVM_FUSES_BODACT1_bm (1<<5) /* BOD Operation in Active Mode bit 1 mask. */ -#define NVM_FUSES_BODACT1_bp 5 /* BOD Operation in Active Mode bit 1 position. */ - -#define NVM_FUSES_EESAVE_bm 0x08 /* Preserve EEPROM Through Chip Erase bit mask. */ -#define NVM_FUSES_EESAVE_bp 3 /* Preserve EEPROM Through Chip Erase bit position. */ - -#define NVM_FUSES_BODLVL_gm 0x07 /* Brownout Detection Voltage Level group mask. */ -#define NVM_FUSES_BODLVL_gp 0 /* Brownout Detection Voltage Level group position. */ -#define NVM_FUSES_BODLVL0_bm (1<<0) /* Brownout Detection Voltage Level bit 0 mask. */ -#define NVM_FUSES_BODLVL0_bp 0 /* Brownout Detection Voltage Level bit 0 position. */ -#define NVM_FUSES_BODLVL1_bm (1<<1) /* Brownout Detection Voltage Level bit 1 mask. */ -#define NVM_FUSES_BODLVL1_bp 1 /* Brownout Detection Voltage Level bit 1 position. */ -#define NVM_FUSES_BODLVL2_bm (1<<2) /* Brownout Detection Voltage Level bit 2 mask. */ -#define NVM_FUSES_BODLVL2_bp 2 /* Brownout Detection Voltage Level bit 2 position. */ - -/* NVM_FUSES.FUSEBYTE6 bit masks and bit positions */ -#define NVM_FUSES_FDACT5_bm 0x80 /* Fault Dectection Action on TC5 bit mask. */ -#define NVM_FUSES_FDACT5_bp 7 /* Fault Dectection Action on TC5 bit position. */ - -#define NVM_FUSES_FDACT4_bm 0x40 /* Fault Dectection Action on TC4 bit mask. */ -#define NVM_FUSES_FDACT4_bp 6 /* Fault Dectection Action on TC4 bit position. */ - -#define NVM_FUSES_VALUE_gm 0x3F /* Port Pin Value group mask. */ -#define NVM_FUSES_VALUE_gp 0 /* Port Pin Value group position. */ -#define NVM_FUSES_VALUE0_bm (1<<0) /* Port Pin Value bit 0 mask. */ -#define NVM_FUSES_VALUE0_bp 0 /* Port Pin Value bit 0 position. */ -#define NVM_FUSES_VALUE1_bm (1<<1) /* Port Pin Value bit 1 mask. */ -#define NVM_FUSES_VALUE1_bp 1 /* Port Pin Value bit 1 position. */ -#define NVM_FUSES_VALUE2_bm (1<<2) /* Port Pin Value bit 2 mask. */ -#define NVM_FUSES_VALUE2_bp 2 /* Port Pin Value bit 2 position. */ -#define NVM_FUSES_VALUE3_bm (1<<3) /* Port Pin Value bit 3 mask. */ -#define NVM_FUSES_VALUE3_bp 3 /* Port Pin Value bit 3 position. */ -#define NVM_FUSES_VALUE4_bm (1<<4) /* Port Pin Value bit 4 mask. */ -#define NVM_FUSES_VALUE4_bp 4 /* Port Pin Value bit 4 position. */ -#define NVM_FUSES_VALUE5_bm (1<<5) /* Port Pin Value bit 5 mask. */ -#define NVM_FUSES_VALUE5_bp 5 /* Port Pin Value bit 5 position. */ - - - -// Generic Port Pins - -#define PIN0_bm 0x01 -#define PIN0_bp 0 -#define PIN1_bm 0x02 -#define PIN1_bp 1 -#define PIN2_bm 0x04 -#define PIN2_bp 2 -#define PIN3_bm 0x08 -#define PIN3_bp 3 -#define PIN4_bm 0x10 -#define PIN4_bp 4 -#define PIN5_bm 0x20 -#define PIN5_bp 5 -#define PIN6_bm 0x40 -#define PIN6_bp 6 -#define PIN7_bm 0x80 -#define PIN7_bp 7 - -/* ========== Interrupt Vector Definitions ========== */ -/* Vector 0 is the reset vector */ - -/* OSC interrupt vectors */ -#define OSC_OSCF_vect_num 1 -#define OSC_OSCF_vect _VECTOR(1) /* Oscillator Failure Interrupt (NMI) */ - -/* PORTR interrupt vectors */ -#define PORTR_INT_vect_num 2 -#define PORTR_INT_vect _VECTOR(2) /* External Interrupt */ - -/* EDMA interrupt vectors */ -#define EDMA_CH0_vect_num 3 -#define EDMA_CH0_vect _VECTOR(3) /* EDMA Channel 0 Interrupt */ -#define EDMA_CH1_vect_num 4 -#define EDMA_CH1_vect _VECTOR(4) /* EDMA Channel 1 Interrupt */ -#define EDMA_CH2_vect_num 5 -#define EDMA_CH2_vect _VECTOR(5) /* EDMA Channel 2 Interrupt */ -#define EDMA_CH3_vect_num 6 -#define EDMA_CH3_vect _VECTOR(6) /* EDMA Channel 3 Interrupt */ - -/* RTC interrupt vectors */ -#define RTC_OVF_vect_num 7 -#define RTC_OVF_vect _VECTOR(7) /* Overflow Interrupt */ -#define RTC_COMP_vect_num 8 -#define RTC_COMP_vect _VECTOR(8) /* Compare Interrupt */ - -/* PORTC interrupt vectors */ -#define PORTC_INT_vect_num 9 -#define PORTC_INT_vect _VECTOR(9) /* External Interrupt */ - -/* TWIC interrupt vectors */ -#define TWIC_TWIS_vect_num 10 -#define TWIC_TWIS_vect _VECTOR(10) /* TWI Slave Interrupt */ -#define TWIC_TWIM_vect_num 11 -#define TWIC_TWIM_vect _VECTOR(11) /* TWI Master Interrupt */ - -/* TCC4 interrupt vectors */ -#define TCC4_OVF_vect_num 12 -#define TCC4_OVF_vect _VECTOR(12) /* Overflow Interrupt */ -#define TCC4_ERR_vect_num 13 -#define TCC4_ERR_vect _VECTOR(13) /* Error Interrupt */ -#define TCC4_CCA_vect_num 14 -#define TCC4_CCA_vect _VECTOR(14) /* Channel A Compare or Capture Interrupt */ -#define TCC4_CCB_vect_num 15 -#define TCC4_CCB_vect _VECTOR(15) /* Channel B Compare or Capture Interrupt */ -#define TCC4_CCC_vect_num 16 -#define TCC4_CCC_vect _VECTOR(16) /* Channel C Compare or Capture Interrupt */ -#define TCC4_CCD_vect_num 17 -#define TCC4_CCD_vect _VECTOR(17) /* Channel D Compare or Capture Interrupt */ - -/* TCC5 interrupt vectors */ -#define TCC5_OVF_vect_num 18 -#define TCC5_OVF_vect _VECTOR(18) /* Overflow Interrupt */ -#define TCC5_ERR_vect_num 19 -#define TCC5_ERR_vect _VECTOR(19) /* Error Interrupt */ -#define TCC5_CCA_vect_num 20 -#define TCC5_CCA_vect _VECTOR(20) /* Channel A Compare or Capture Interrupt */ -#define TCC5_CCB_vect_num 21 -#define TCC5_CCB_vect _VECTOR(21) /* Channel B Compare or Capture Interrupt */ - -/* SPIC interrupt vectors */ -#define SPIC_INT_vect_num 22 -#define SPIC_INT_vect _VECTOR(22) /* SPI Interrupt */ - -/* USARTC0 interrupt vectors */ -#define USARTC0_RXC_vect_num 23 -#define USARTC0_RXC_vect _VECTOR(23) /* Reception Complete Interrupt */ -#define USARTC0_DRE_vect_num 24 -#define USARTC0_DRE_vect _VECTOR(24) /* Data Register Empty Interrupt */ -#define USARTC0_TXC_vect_num 25 -#define USARTC0_TXC_vect _VECTOR(25) /* Transmission Complete Interrupt */ - -/* NVM interrupt vectors */ -#define NVM_EE_vect_num 26 -#define NVM_EE_vect _VECTOR(26) /* EE Interrupt */ -#define NVM_SPM_vect_num 27 -#define NVM_SPM_vect _VECTOR(27) /* SPM Interrupt */ - -/* XCL interrupt vectors */ -#define XCL_UNF_vect_num 28 -#define XCL_UNF_vect _VECTOR(28) /* Timer/Counter Underflow Interrupt */ -#define XCL_CC_vect_num 29 -#define XCL_CC_vect _VECTOR(29) /* Timer/Counter Compare or Capture Interrupt */ - -/* PORTA interrupt vectors */ -#define PORTA_INT_vect_num 30 -#define PORTA_INT_vect _VECTOR(30) /* External Interrupt */ - -/* ACA interrupt vectors */ -#define ACA_AC0_vect_num 31 -#define ACA_AC0_vect _VECTOR(31) /* AC0 Interrupt */ -#define ACA_AC1_vect_num 32 -#define ACA_AC1_vect _VECTOR(32) /* AC1 Interrupt */ -#define ACA_ACW_vect_num 33 -#define ACA_ACW_vect _VECTOR(33) /* ACW Window Mode Interrupt */ - -/* ADCA interrupt vectors */ -#define ADCA_CH0_vect_num 34 -#define ADCA_CH0_vect _VECTOR(34) /* ADC Channel Interrupt */ - -/* PORTD interrupt vectors */ -#define PORTD_INT_vect_num 35 -#define PORTD_INT_vect _VECTOR(35) /* External Interrupt */ - -/* TCD5 interrupt vectors */ -#define TCD5_OVF_vect_num 36 -#define TCD5_OVF_vect _VECTOR(36) /* Overflow Interrupt */ -#define TCD5_ERR_vect_num 37 -#define TCD5_ERR_vect _VECTOR(37) /* Error Interrupt */ -#define TCD5_CCA_vect_num 38 -#define TCD5_CCA_vect _VECTOR(38) /* Channel A Compare or Capture Interrupt */ -#define TCD5_CCB_vect_num 39 -#define TCD5_CCB_vect _VECTOR(39) /* Channel B Compare or Capture Interrupt */ - -/* USARTD0 interrupt vectors */ -#define USARTD0_RXC_vect_num 40 -#define USARTD0_RXC_vect _VECTOR(40) /* Reception Complete Interrupt */ -#define USARTD0_DRE_vect_num 41 -#define USARTD0_DRE_vect _VECTOR(41) /* Data Register Empty Interrupt */ -#define USARTD0_TXC_vect_num 42 -#define USARTD0_TXC_vect _VECTOR(42) /* Transmission Complete Interrupt */ - -#define _VECTOR_SIZE 4 /* Size of individual vector. */ -#define _VECTORS_SIZE (43 * _VECTOR_SIZE) - - -/* ========== Constants ========== */ - -#define PROGMEM_START (0x0000) -#define PROGMEM_SIZE (20480) -#define PROGMEM_END (PROGMEM_START + PROGMEM_SIZE - 1) - -#define APP_SECTION_START (0x0000) -#define APP_SECTION_SIZE (16384) -#define APP_SECTION_PAGE_SIZE (128) -#define APP_SECTION_END (APP_SECTION_START + APP_SECTION_SIZE - 1) - -#define APPTABLE_SECTION_START (0x3000) -#define APPTABLE_SECTION_SIZE (4096) -#define APPTABLE_SECTION_PAGE_SIZE (128) -#define APPTABLE_SECTION_END (APPTABLE_SECTION_START + APPTABLE_SECTION_SIZE - 1) - -#define BOOT_SECTION_START (0x4000) -#define BOOT_SECTION_SIZE (4096) -#define BOOT_SECTION_PAGE_SIZE (128) -#define BOOT_SECTION_END (BOOT_SECTION_START + BOOT_SECTION_SIZE - 1) - -#define DATAMEM_START (0x0000) -#define DATAMEM_SIZE (10240) -#define DATAMEM_END (DATAMEM_START + DATAMEM_SIZE - 1) - -#define IO_START (0x0000) -#define IO_SIZE (4096) -#define IO_PAGE_SIZE (0) -#define IO_END (IO_START + IO_SIZE - 1) - -#define MAPPED_EEPROM_START (0x1000) -#define MAPPED_EEPROM_SIZE (512) -#define MAPPED_EEPROM_PAGE_SIZE (0) -#define MAPPED_EEPROM_END (MAPPED_EEPROM_START + MAPPED_EEPROM_SIZE - 1) - -#define INTERNAL_SRAM_START (0x2000) -#define INTERNAL_SRAM_SIZE (2048) -#define INTERNAL_SRAM_PAGE_SIZE (0) -#define INTERNAL_SRAM_END (INTERNAL_SRAM_START + INTERNAL_SRAM_SIZE - 1) - -#define EEPROM_START (0x0000) -#define EEPROM_SIZE (512) -#define EEPROM_PAGE_SIZE (32) -#define EEPROM_END (EEPROM_START + EEPROM_SIZE - 1) - -#define SIGNATURES_START (0x0000) -#define SIGNATURES_SIZE (3) -#define SIGNATURES_PAGE_SIZE (0) -#define SIGNATURES_END (SIGNATURES_START + SIGNATURES_SIZE - 1) - -#define FUSES_START (0x0000) -#define FUSES_SIZE (7) -#define FUSES_PAGE_SIZE (0) -#define FUSES_END (FUSES_START + FUSES_SIZE - 1) - -#define LOCKBITS_START (0x0000) -#define LOCKBITS_SIZE (1) -#define LOCKBITS_PAGE_SIZE (0) -#define LOCKBITS_END (LOCKBITS_START + LOCKBITS_SIZE - 1) - -#define USER_SIGNATURES_START (0x0000) -#define USER_SIGNATURES_SIZE (128) -#define USER_SIGNATURES_PAGE_SIZE (128) -#define USER_SIGNATURES_END (USER_SIGNATURES_START + USER_SIGNATURES_SIZE - 1) - -#define PROD_SIGNATURES_START (0x0000) -#define PROD_SIGNATURES_SIZE (54) -#define PROD_SIGNATURES_PAGE_SIZE (128) -#define PROD_SIGNATURES_END (PROD_SIGNATURES_START + PROD_SIGNATURES_SIZE - 1) - -#define FLASHSTART PROGMEM_START -#define FLASHEND PROGMEM_END -#define SPM_PAGESIZE 128 -#define RAMSTART INTERNAL_SRAM_START -#define RAMSIZE INTERNAL_SRAM_SIZE -#define RAMEND INTERNAL_SRAM_END -#define E2END EEPROM_END -#define E2PAGESIZE EEPROM_PAGE_SIZE - - -/* ========== Fuses ========== */ -#define FUSE_MEMORY_SIZE 7 - -/* Fuse Byte 0 Reserved */ - -/* Fuse Byte 1 */ -#define FUSE_WDP0 (unsigned char)~_BV(0) /* Watchdog Timeout Period Bit 0 */ -#define FUSE_WDP1 (unsigned char)~_BV(1) /* Watchdog Timeout Period Bit 1 */ -#define FUSE_WDP2 (unsigned char)~_BV(2) /* Watchdog Timeout Period Bit 2 */ -#define FUSE_WDP3 (unsigned char)~_BV(3) /* Watchdog Timeout Period Bit 3 */ -#define FUSE_WDWP0 (unsigned char)~_BV(4) /* Watchdog Window Timeout Period Bit 0 */ -#define FUSE_WDWP1 (unsigned char)~_BV(5) /* Watchdog Window Timeout Period Bit 1 */ -#define FUSE_WDWP2 (unsigned char)~_BV(6) /* Watchdog Window Timeout Period Bit 2 */ -#define FUSE_WDWP3 (unsigned char)~_BV(7) /* Watchdog Window Timeout Period Bit 3 */ -#define FUSE1_DEFAULT (0xFF) - -/* Fuse Byte 2 */ -#define FUSE_BODPD0 (unsigned char)~_BV(0) /* BOD Operation in Power-Down Mode Bit 0 */ -#define FUSE_BODPD1 (unsigned char)~_BV(1) /* BOD Operation in Power-Down Mode Bit 1 */ -#define FUSE_BOOTRST (unsigned char)~_BV(6) /* Boot Loader Section Reset Vector */ -#define FUSE2_DEFAULT (0xFF) - -/* Fuse Byte 3 Reserved */ - -/* Fuse Byte 4 */ -#define FUSE_WDLOCK (unsigned char)~_BV(1) /* Watchdog Timer Lock */ -#define FUSE_SUT0 (unsigned char)~_BV(2) /* Start-up Time Bit 0 */ -#define FUSE_SUT1 (unsigned char)~_BV(3) /* Start-up Time Bit 1 */ -#define FUSE_RSTDISBL (unsigned char)~_BV(4) /* External Reset Disable */ -#define FUSE4_DEFAULT (0xFF) - -/* Fuse Byte 5 */ -#define FUSE_BODLVL0 (unsigned char)~_BV(0) /* Brownout Detection Voltage Level Bit 0 */ -#define FUSE_BODLVL1 (unsigned char)~_BV(1) /* Brownout Detection Voltage Level Bit 1 */ -#define FUSE_BODLVL2 (unsigned char)~_BV(2) /* Brownout Detection Voltage Level Bit 2 */ -#define FUSE_EESAVE (unsigned char)~_BV(3) /* Preserve EEPROM Through Chip Erase */ -#define FUSE_BODACT0 (unsigned char)~_BV(4) /* BOD Operation in Active Mode Bit 0 */ -#define FUSE_BODACT1 (unsigned char)~_BV(5) /* BOD Operation in Active Mode Bit 1 */ -#define FUSE5_DEFAULT (0xFF) - -/* Fuse Byte 6 */ -#define FUSE_VALUE0 (unsigned char)~_BV(0) /* Port Pin Value Bit 0 */ -#define FUSE_VALUE1 (unsigned char)~_BV(1) /* Port Pin Value Bit 1 */ -#define FUSE_VALUE2 (unsigned char)~_BV(2) /* Port Pin Value Bit 2 */ -#define FUSE_VALUE3 (unsigned char)~_BV(3) /* Port Pin Value Bit 3 */ -#define FUSE_VALUE4 (unsigned char)~_BV(4) /* Port Pin Value Bit 4 */ -#define FUSE_VALUE5 (unsigned char)~_BV(5) /* Port Pin Value Bit 5 */ -#define FUSE_FDACT4 (unsigned char)~_BV(6) /* Fault Dectection Action on TC4 */ -#define FUSE_FDACT5 (unsigned char)~_BV(7) /* Fault Dectection Action on TC5 */ -#define FUSE6_DEFAULT (0xFF) - -/* ========== Lock Bits ========== */ -#define __LOCK_BITS_EXIST -#define __BOOT_LOCK_APPLICATION_TABLE_BITS_EXIST -#define __BOOT_LOCK_APPLICATION_BITS_EXIST -#define __BOOT_LOCK_BOOT_BITS_EXIST - -/* ========== Signature ========== */ -#define SIGNATURE_0 0x1E -#define SIGNATURE_1 0x94 -#define SIGNATURE_2 0x45 - -/* ========== Power Reduction Condition Definitions ========== */ - -/* PR.PRGEN */ -#define __AVR_HAVE_PRGEN (PR_XCL_bm|PR_RTC_bm|PR_EVSYS_bm|PR_EDMA_bm) -#define __AVR_HAVE_PRGEN_XCL -#define __AVR_HAVE_PRGEN_RTC -#define __AVR_HAVE_PRGEN_EVSYS -#define __AVR_HAVE_PRGEN_EDMA - -/* PR.PRPA */ -#define __AVR_HAVE_PRPA (PR_DAC_bm|PR_ADC_bm|PR_AC_bm) -#define __AVR_HAVE_PRPA_DAC -#define __AVR_HAVE_PRPA_ADC -#define __AVR_HAVE_PRPA_AC - -/* PR.PRPC */ -#define __AVR_HAVE_PRPC (PR_TWI_bm|PR_USART0_bm|PR_SPI_bm|PR_HIRES_bm|PR_TC5_bm|PR_TC4_bm) -#define __AVR_HAVE_PRPC_TWI -#define __AVR_HAVE_PRPC_USART0 -#define __AVR_HAVE_PRPC_SPI -#define __AVR_HAVE_PRPC_HIRES -#define __AVR_HAVE_PRPC_TC5 -#define __AVR_HAVE_PRPC_TC4 - -/* PR.PRPD */ -#define __AVR_HAVE_PRPD (PR_USART0_bm|PR_TC5_bm) -#define __AVR_HAVE_PRPD_USART0 -#define __AVR_HAVE_PRPD_TC5 - - -#endif /* #ifdef _AVR_ATXMEGA16E5_H_INCLUDED */ - diff --git a/arduino/hardware/tools/avr/avr/include/avr/iox192a3.h b/arduino/hardware/tools/avr/avr/include/avr/iox192a3.h deleted file mode 100644 index e6917cb..0000000 --- a/arduino/hardware/tools/avr/avr/include/avr/iox192a3.h +++ /dev/null @@ -1,6987 +0,0 @@ -/* Copyright (c) 2009-2010 Atmel Corporation - All rights reserved. - - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - * Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - * Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in - the documentation and/or other materials provided with the - distribution. - - * Neither the name of the copyright holders nor the names of - contributors may be used to endorse or promote products derived - from this software without specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. */ - -/* $Id: iox192a3.h 2218 2011-02-21 19:43:03Z arcanum $ */ - -/* avr/iox192a3.h - definitions for ATxmega192A3 */ - -/* This file should only be included from , never directly. */ - -#ifndef _AVR_IO_H_ -# error "Include instead of this file." -#endif - -#ifndef _AVR_IOXXX_H_ -# define _AVR_IOXXX_H_ "iox192a3.h" -#else -# error "Attempt to include more than one file." -#endif - - -#ifndef _AVR_ATxmega192A3_H_ -#define _AVR_ATxmega192A3_H_ 1 - - -/* Ungrouped common registers */ -#define GPIOR0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ -#define GPIOR1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ -#define GPIOR2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ -#define GPIOR3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ -#define GPIOR4 _SFR_MEM8(0x0004) /* General Purpose IO Register 4 */ -#define GPIOR5 _SFR_MEM8(0x0005) /* General Purpose IO Register 5 */ -#define GPIOR6 _SFR_MEM8(0x0006) /* General Purpose IO Register 6 */ -#define GPIOR7 _SFR_MEM8(0x0007) /* General Purpose IO Register 7 */ -#define GPIOR8 _SFR_MEM8(0x0008) /* General Purpose IO Register 8 */ -#define GPIOR9 _SFR_MEM8(0x0009) /* General Purpose IO Register 9 */ -#define GPIORA _SFR_MEM8(0x000A) /* General Purpose IO Register 10 */ -#define GPIORB _SFR_MEM8(0x000B) /* General Purpose IO Register 11 */ -#define GPIORC _SFR_MEM8(0x000C) /* General Purpose IO Register 12 */ -#define GPIORD _SFR_MEM8(0x000D) /* General Purpose IO Register 13 */ -#define GPIORE _SFR_MEM8(0x000E) /* General Purpose IO Register 14 */ -#define GPIORF _SFR_MEM8(0x000F) /* General Purpose IO Register 15 */ - -/* Deprecated */ -#define GPIO0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ -#define GPIO1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ -#define GPIO2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ -#define GPIO3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ -#define GPIO4 _SFR_MEM8(0x0004) /* General Purpose IO Register 4 */ -#define GPIO5 _SFR_MEM8(0x0005) /* General Purpose IO Register 5 */ -#define GPIO6 _SFR_MEM8(0x0006) /* General Purpose IO Register 6 */ -#define GPIO7 _SFR_MEM8(0x0007) /* General Purpose IO Register 7 */ -#define GPIO8 _SFR_MEM8(0x0008) /* General Purpose IO Register 8 */ -#define GPIO9 _SFR_MEM8(0x0009) /* General Purpose IO Register 9 */ -#define GPIOA _SFR_MEM8(0x000A) /* General Purpose IO Register 10 */ -#define GPIOB _SFR_MEM8(0x000B) /* General Purpose IO Register 11 */ -#define GPIOC _SFR_MEM8(0x000C) /* General Purpose IO Register 12 */ -#define GPIOD _SFR_MEM8(0x000D) /* General Purpose IO Register 13 */ -#define GPIOE _SFR_MEM8(0x000E) /* General Purpose IO Register 14 */ -#define GPIOF _SFR_MEM8(0x000F) /* General Purpose IO Register 15 */ - -#define CCP _SFR_MEM8(0x0034) /* Configuration Change Protection */ -#define RAMPD _SFR_MEM8(0x0038) /* Ramp D */ -#define RAMPX _SFR_MEM8(0x0039) /* Ramp X */ -#define RAMPY _SFR_MEM8(0x003A) /* Ramp Y */ -#define RAMPZ _SFR_MEM8(0x003B) /* Ramp Z */ -#define EIND _SFR_MEM8(0x003C) /* Extended Indirect Jump */ -#define SPL _SFR_MEM8(0x003D) /* Stack Pointer Low */ -#define SPH _SFR_MEM8(0x003E) /* Stack Pointer High */ -#define SREG _SFR_MEM8(0x003F) /* Status Register */ - - -/* C Language Only */ -#if !defined (__ASSEMBLER__) - -#include - -typedef volatile uint8_t register8_t; -typedef volatile uint16_t register16_t; -typedef volatile uint32_t register32_t; - - -#ifdef _WORDREGISTER -#undef _WORDREGISTER -#endif -#define _WORDREGISTER(regname) \ - __extension__ union \ - { \ - register16_t regname; \ - struct \ - { \ - register8_t regname ## L; \ - register8_t regname ## H; \ - }; \ - } - -#ifdef _DWORDREGISTER -#undef _DWORDREGISTER -#endif -#define _DWORDREGISTER(regname) \ - __extension__ union \ - { \ - register32_t regname; \ - struct \ - { \ - register8_t regname ## 0; \ - register8_t regname ## 1; \ - register8_t regname ## 2; \ - register8_t regname ## 3; \ - }; \ - } - - -/* -========================================================================== -IO Module Structures -========================================================================== -*/ - - -/* --------------------------------------------------------------------------- -XOCD - On-Chip Debug System --------------------------------------------------------------------------- -*/ - -/* On-Chip Debug System */ -typedef struct OCD_struct -{ - register8_t OCDR0; /* OCD Register 0 */ - register8_t OCDR1; /* OCD Register 1 */ -} OCD_t; - - -/* CCP signatures */ -typedef enum CCP_enum -{ - CCP_SPM_gc = (0x9D<<0), /* SPM Instruction Protection */ - CCP_IOREG_gc = (0xD8<<0), /* IO Register Protection */ -} CCP_t; - - -/* --------------------------------------------------------------------------- -CLK - Clock System --------------------------------------------------------------------------- -*/ - -/* Clock System */ -typedef struct CLK_struct -{ - register8_t CTRL; /* Control Register */ - register8_t PSCTRL; /* Prescaler Control Register */ - register8_t LOCK; /* Lock register */ - register8_t RTCCTRL; /* RTC Control Register */ -} CLK_t; - -/* --------------------------------------------------------------------------- -CLK - Clock System --------------------------------------------------------------------------- -*/ - -/* Power Reduction */ -typedef struct PR_struct -{ - register8_t PRGEN; /* General Power Reduction */ - register8_t PRPA; /* Power Reduction Port A */ - register8_t PRPB; /* Power Reduction Port B */ - register8_t PRPC; /* Power Reduction Port C */ - register8_t PRPD; /* Power Reduction Port D */ - register8_t PRPE; /* Power Reduction Port E */ - register8_t PRPF; /* Power Reduction Port F */ -} PR_t; - -/* System Clock Selection */ -typedef enum CLK_SCLKSEL_enum -{ - CLK_SCLKSEL_RC2M_gc = (0x00<<0), /* Internal 2MHz RC Oscillator */ - CLK_SCLKSEL_RC32M_gc = (0x01<<0), /* Internal 32MHz RC Oscillator */ - CLK_SCLKSEL_RC32K_gc = (0x02<<0), /* Internal 32kHz RC Oscillator */ - CLK_SCLKSEL_XOSC_gc = (0x03<<0), /* External Crystal Oscillator or Clock */ - CLK_SCLKSEL_PLL_gc = (0x04<<0), /* Phase Locked Loop */ -} CLK_SCLKSEL_t; - -/* Prescaler A Division Factor */ -typedef enum CLK_PSADIV_enum -{ - CLK_PSADIV_1_gc = (0x00<<2), /* Divide by 1 */ - CLK_PSADIV_2_gc = (0x01<<2), /* Divide by 2 */ - CLK_PSADIV_4_gc = (0x03<<2), /* Divide by 4 */ - CLK_PSADIV_8_gc = (0x05<<2), /* Divide by 8 */ - CLK_PSADIV_16_gc = (0x07<<2), /* Divide by 16 */ - CLK_PSADIV_32_gc = (0x09<<2), /* Divide by 32 */ - CLK_PSADIV_64_gc = (0x0B<<2), /* Divide by 64 */ - CLK_PSADIV_128_gc = (0x0D<<2), /* Divide by 128 */ - CLK_PSADIV_256_gc = (0x0F<<2), /* Divide by 256 */ - CLK_PSADIV_512_gc = (0x11<<2), /* Divide by 512 */ -} CLK_PSADIV_t; - -/* Prescaler B and C Division Factor */ -typedef enum CLK_PSBCDIV_enum -{ - CLK_PSBCDIV_1_1_gc = (0x00<<0), /* Divide B by 1 and C by 1 */ - CLK_PSBCDIV_1_2_gc = (0x01<<0), /* Divide B by 1 and C by 2 */ - CLK_PSBCDIV_4_1_gc = (0x02<<0), /* Divide B by 4 and C by 1 */ - CLK_PSBCDIV_2_2_gc = (0x03<<0), /* Divide B by 2 and C by 2 */ -} CLK_PSBCDIV_t; - -/* RTC Clock Source */ -typedef enum CLK_RTCSRC_enum -{ - CLK_RTCSRC_ULP_gc = (0x00<<1), /* 1kHz from internal 32kHz ULP */ - CLK_RTCSRC_TOSC_gc = (0x01<<1), /* 1kHz from 32kHz crystal oscillator on TOSC */ - CLK_RTCSRC_RCOSC_gc = (0x02<<1), /* 1kHz from internal 32kHz RC oscillator */ - CLK_RTCSRC_TOSC32_gc = (0x05<<1), /* 32kHz from 32kHz crystal oscillator on TOSC */ -} CLK_RTCSRC_t; - - -/* --------------------------------------------------------------------------- -SLEEP - Sleep Controller --------------------------------------------------------------------------- -*/ - -/* Sleep Controller */ -typedef struct SLEEP_struct -{ - register8_t CTRL; /* Control Register */ -} SLEEP_t; - -/* Sleep Mode */ -typedef enum SLEEP_SMODE_enum -{ - SLEEP_SMODE_IDLE_gc = (0x00<<1), /* Idle mode */ - SLEEP_SMODE_PDOWN_gc = (0x02<<1), /* Power-down Mode */ - SLEEP_SMODE_PSAVE_gc = (0x03<<1), /* Power-save Mode */ - SLEEP_SMODE_STDBY_gc = (0x06<<1), /* Standby Mode */ - SLEEP_SMODE_ESTDBY_gc = (0x07<<1), /* Extended Standby Mode */ -} SLEEP_SMODE_t; - - -#define SLEEP_MODE_IDLE (0x00<<1) -#define SLEEP_MODE_PWR_DOWN (0x02<<1) -#define SLEEP_MODE_PWR_SAVE (0x03<<1) -#define SLEEP_MODE_STANDBY (0x06<<1) -#define SLEEP_MODE_EXT_STANDBY (0x07<<1) - - -/* --------------------------------------------------------------------------- -OSC - Oscillator --------------------------------------------------------------------------- -*/ - -/* Oscillator */ -typedef struct OSC_struct -{ - register8_t CTRL; /* Control Register */ - register8_t STATUS; /* Status Register */ - register8_t XOSCCTRL; /* External Oscillator Control Register */ - register8_t XOSCFAIL; /* External Oscillator Failure Detection Register */ - register8_t RC32KCAL; /* 32kHz Internal Oscillator Calibration Register */ - register8_t PLLCTRL; /* PLL Control REgister */ - register8_t DFLLCTRL; /* DFLL Control Register */ -} OSC_t; - -/* Oscillator Frequency Range */ -typedef enum OSC_FRQRANGE_enum -{ - OSC_FRQRANGE_04TO2_gc = (0x00<<6), /* 0.4 - 2 MHz */ - OSC_FRQRANGE_2TO9_gc = (0x01<<6), /* 2 - 9 MHz */ - OSC_FRQRANGE_9TO12_gc = (0x02<<6), /* 9 - 12 MHz */ - OSC_FRQRANGE_12TO16_gc = (0x03<<6), /* 12 - 16 MHz */ -} OSC_FRQRANGE_t; - -/* External Oscillator Selection and Startup Time */ -typedef enum OSC_XOSCSEL_enum -{ - OSC_XOSCSEL_EXTCLK_gc = (0x00<<0), /* External Clock - 6 CLK */ - OSC_XOSCSEL_32KHz_gc = (0x02<<0), /* 32kHz TOSC - 32K CLK */ - OSC_XOSCSEL_XTAL_256CLK_gc = (0x03<<0), /* 0.4-16MHz XTAL - 256 CLK */ - OSC_XOSCSEL_XTAL_1KCLK_gc = (0x07<<0), /* 0.4-16MHz XTAL - 1K CLK */ - OSC_XOSCSEL_XTAL_16KCLK_gc = (0x0B<<0), /* 0.4-16MHz XTAL - 16K CLK */ -} OSC_XOSCSEL_t; - -/* PLL Clock Source */ -typedef enum OSC_PLLSRC_enum -{ - OSC_PLLSRC_RC2M_gc = (0x00<<6), /* Internal 2MHz RC Oscillator */ - OSC_PLLSRC_RC32M_gc = (0x02<<6), /* Internal 32MHz RC Oscillator */ - OSC_PLLSRC_XOSC_gc = (0x03<<6), /* External Oscillator */ -} OSC_PLLSRC_t; - - -/* --------------------------------------------------------------------------- -DFLL - DFLL --------------------------------------------------------------------------- -*/ - -/* DFLL */ -typedef struct DFLL_struct -{ - register8_t CTRL; /* Control Register */ - register8_t reserved_0x01; - register8_t CALA; /* Calibration Register A */ - register8_t CALB; /* Calibration Register B */ - register8_t COMP0; /* Oscillator Compare Register 0 */ - register8_t COMP1; /* Oscillator Compare Register 1 */ - register8_t COMP2; /* Oscillator Compare Register 2 */ - register8_t reserved_0x07; -} DFLL_t; - - -/* --------------------------------------------------------------------------- -RST - Reset --------------------------------------------------------------------------- -*/ - -/* Reset */ -typedef struct RST_struct -{ - register8_t STATUS; /* Status Register */ - register8_t CTRL; /* Control Register */ -} RST_t; - - -/* --------------------------------------------------------------------------- -WDT - Watch-Dog Timer --------------------------------------------------------------------------- -*/ - -/* Watch-Dog Timer */ -typedef struct WDT_struct -{ - register8_t CTRL; /* Control */ - register8_t WINCTRL; /* Windowed Mode Control */ - register8_t STATUS; /* Status */ -} WDT_t; - -/* Period setting */ -typedef enum WDT_PER_enum -{ - WDT_PER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ - WDT_PER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ - WDT_PER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ - WDT_PER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ - WDT_PER_128CLK_gc = (0x04<<2), /* 128 cycles (0.125s @ 3.3V) */ - WDT_PER_256CLK_gc = (0x05<<2), /* 256 cycles (0.25s @ 3.3V) */ - WDT_PER_512CLK_gc = (0x06<<2), /* 512 cycles (0.5s @ 3.3V) */ - WDT_PER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ - WDT_PER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ - WDT_PER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ - WDT_PER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ -} WDT_PER_t; - -/* Closed window period */ -typedef enum WDT_WPER_enum -{ - WDT_WPER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ - WDT_WPER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ - WDT_WPER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ - WDT_WPER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ - WDT_WPER_128CLK_gc = (0x04<<2), /* 128 cycles (0.125s @ 3.3V) */ - WDT_WPER_256CLK_gc = (0x05<<2), /* 256 cycles (0.25s @ 3.3V) */ - WDT_WPER_512CLK_gc = (0x06<<2), /* 512 cycles (0.5s @ 3.3V) */ - WDT_WPER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ - WDT_WPER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ - WDT_WPER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ - WDT_WPER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ -} WDT_WPER_t; - - -/* --------------------------------------------------------------------------- -MCU - MCU Control --------------------------------------------------------------------------- -*/ - -/* MCU Control */ -typedef struct MCU_struct -{ - register8_t DEVID0; /* Device ID byte 0 */ - register8_t DEVID1; /* Device ID byte 1 */ - register8_t DEVID2; /* Device ID byte 2 */ - register8_t REVID; /* Revision ID */ - register8_t JTAGUID; /* JTAG User ID */ - register8_t reserved_0x05; - register8_t MCUCR; /* MCU Control */ - register8_t reserved_0x07; - register8_t EVSYSLOCK; /* Event System Lock */ - register8_t AWEXLOCK; /* AWEX Lock */ - register8_t reserved_0x0A; - register8_t reserved_0x0B; -} MCU_t; - - -/* --------------------------------------------------------------------------- -PMIC - Programmable Multi-level Interrupt Controller --------------------------------------------------------------------------- -*/ - -/* Programmable Multi-level Interrupt Controller */ -typedef struct PMIC_struct -{ - register8_t STATUS; /* Status Register */ - register8_t INTPRI; /* Interrupt Priority */ - register8_t CTRL; /* Control Register */ -} PMIC_t; - - -/* --------------------------------------------------------------------------- -DMA - DMA Controller --------------------------------------------------------------------------- -*/ - -/* DMA Channel */ -typedef struct DMA_CH_struct -{ - register8_t CTRLA; /* Channel Control */ - register8_t CTRLB; /* Channel Control */ - register8_t ADDRCTRL; /* Address Control */ - register8_t TRIGSRC; /* Channel Trigger Source */ - _WORDREGISTER(TRFCNT); /* Channel Block Transfer Count */ - register8_t REPCNT; /* Channel Repeat Count */ - register8_t reserved_0x07; - register8_t SRCADDR0; /* Channel Source Address 0 */ - register8_t SRCADDR1; /* Channel Source Address 1 */ - register8_t SRCADDR2; /* Channel Source Address 2 */ - register8_t reserved_0x0B; - register8_t DESTADDR0; /* Channel Destination Address 0 */ - register8_t DESTADDR1; /* Channel Destination Address 1 */ - register8_t DESTADDR2; /* Channel Destination Address 2 */ - register8_t reserved_0x0F; -} DMA_CH_t; - -/* --------------------------------------------------------------------------- -DMA - DMA Controller --------------------------------------------------------------------------- -*/ - -/* DMA Controller */ -typedef struct DMA_struct -{ - register8_t CTRL; /* Control */ - register8_t reserved_0x01; - register8_t reserved_0x02; - register8_t INTFLAGS; /* Transfer Interrupt Status */ - register8_t STATUS; /* Status */ - register8_t reserved_0x05; - _WORDREGISTER(TEMP); /* Temporary Register For 16/24-bit Access */ - register8_t reserved_0x08; - register8_t reserved_0x09; - register8_t reserved_0x0A; - register8_t reserved_0x0B; - register8_t reserved_0x0C; - register8_t reserved_0x0D; - register8_t reserved_0x0E; - register8_t reserved_0x0F; - DMA_CH_t CH0; /* DMA Channel 0 */ - DMA_CH_t CH1; /* DMA Channel 1 */ - DMA_CH_t CH2; /* DMA Channel 2 */ - DMA_CH_t CH3; /* DMA Channel 3 */ -} DMA_t; - -/* Burst mode */ -typedef enum DMA_CH_BURSTLEN_enum -{ - DMA_CH_BURSTLEN_1BYTE_gc = (0x00<<0), /* 1-byte burst mode */ - DMA_CH_BURSTLEN_2BYTE_gc = (0x01<<0), /* 2-byte burst mode */ - DMA_CH_BURSTLEN_4BYTE_gc = (0x02<<0), /* 4-byte burst mode */ - DMA_CH_BURSTLEN_8BYTE_gc = (0x03<<0), /* 8-byte burst mode */ -} DMA_CH_BURSTLEN_t; - -/* Source address reload mode */ -typedef enum DMA_CH_SRCRELOAD_enum -{ - DMA_CH_SRCRELOAD_NONE_gc = (0x00<<6), /* No reload */ - DMA_CH_SRCRELOAD_BLOCK_gc = (0x01<<6), /* Reload at end of block */ - DMA_CH_SRCRELOAD_BURST_gc = (0x02<<6), /* Reload at end of burst */ - DMA_CH_SRCRELOAD_TRANSACTION_gc = (0x03<<6), /* Reload at end of transaction */ -} DMA_CH_SRCRELOAD_t; - -/* Source addressing mode */ -typedef enum DMA_CH_SRCDIR_enum -{ - DMA_CH_SRCDIR_FIXED_gc = (0x00<<4), /* Fixed */ - DMA_CH_SRCDIR_INC_gc = (0x01<<4), /* Increment */ - DMA_CH_SRCDIR_DEC_gc = (0x02<<4), /* Decrement */ -} DMA_CH_SRCDIR_t; - -/* Destination adress reload mode */ -typedef enum DMA_CH_DESTRELOAD_enum -{ - DMA_CH_DESTRELOAD_NONE_gc = (0x00<<2), /* No reload */ - DMA_CH_DESTRELOAD_BLOCK_gc = (0x01<<2), /* Reload at end of block */ - DMA_CH_DESTRELOAD_BURST_gc = (0x02<<2), /* Reload at end of burst */ - DMA_CH_DESTRELOAD_TRANSACTION_gc = (0x03<<2), /* Reload at end of transaction */ -} DMA_CH_DESTRELOAD_t; - -/* Destination adressing mode */ -typedef enum DMA_CH_DESTDIR_enum -{ - DMA_CH_DESTDIR_FIXED_gc = (0x00<<0), /* Fixed */ - DMA_CH_DESTDIR_INC_gc = (0x01<<0), /* Increment */ - DMA_CH_DESTDIR_DEC_gc = (0x02<<0), /* Decrement */ -} DMA_CH_DESTDIR_t; - -/* Transfer trigger source */ -typedef enum DMA_CH_TRIGSRC_enum -{ - DMA_CH_TRIGSRC_OFF_gc = (0x00<<0), /* Off software triggers only */ - DMA_CH_TRIGSRC_EVSYS_CH0_gc = (0x01<<0), /* Event System Channel 0 */ - DMA_CH_TRIGSRC_EVSYS_CH1_gc = (0x02<<0), /* Event System Channel 1 */ - DMA_CH_TRIGSRC_EVSYS_CH2_gc = (0x03<<0), /* Event System Channel 2 */ - DMA_CH_TRIGSRC_ADCA_CH0_gc = (0x10<<0), /* ADCA Channel 0 */ - DMA_CH_TRIGSRC_ADCA_CH1_gc = (0x11<<0), /* ADCA Channel 1 */ - DMA_CH_TRIGSRC_ADCA_CH2_gc = (0x12<<0), /* ADCA Channel 2 */ - DMA_CH_TRIGSRC_ADCA_CH3_gc = (0x13<<0), /* ADCA Channel 3 */ - DMA_CH_TRIGSRC_ADCA_CH4_gc = (0x14<<0), /* ADCA Channel 0,1,2,3 combined */ - DMA_CH_TRIGSRC_DACA_CH0_gc = (0x15<<0), /* DACA Channel 0 */ - DMA_CH_TRIGSRC_DACA_CH1_gc = (0x16<<0), /* DACA Channel 1 */ - DMA_CH_TRIGSRC_ADCB_CH0_gc = (0x20<<0), /* ADCB Channel 0 */ - DMA_CH_TRIGSRC_ADCB_CH1_gc = (0x21<<0), /* ADCB Channel 1 */ - DMA_CH_TRIGSRC_ADCB_CH2_gc = (0x22<<0), /* ADCB Channel 2 */ - DMA_CH_TRIGSRC_ADCB_CH3_gc = (0x23<<0), /* ADCB Channel 3 */ - DMA_CH_TRIGSRC_ADCB_CH4_gc = (0x24<<0), /* ADCB Channel 0,1,2,3 combined */ - DMA_CH_TRIGSRC_DACB_CH0_gc = (0x25<<0), /* DACB Channel 0 */ - DMA_CH_TRIGSRC_DACB_CH1_gc = (0x26<<0), /* DACB Channel 1 */ - DMA_CH_TRIGSRC_TCC0_OVF_gc = (0x40<<0), /* Timer/Counter C0 Overflow */ - DMA_CH_TRIGSRC_TCC0_ERR_gc = (0x41<<0), /* Timer/Counter C0 Error */ - DMA_CH_TRIGSRC_TCC0_CCA_gc = (0x42<<0), /* Timer/Counter C0 Compare or Capture A */ - DMA_CH_TRIGSRC_TCC0_CCB_gc = (0x43<<0), /* Timer/Counter C0 Compare or Capture B */ - DMA_CH_TRIGSRC_TCC0_CCC_gc = (0x44<<0), /* Timer/Counter C0 Compare or Capture C */ - DMA_CH_TRIGSRC_TCC0_CCD_gc = (0x45<<0), /* Timer/Counter C0 Compare or Capture D */ - DMA_CH_TRIGSRC_TCC1_OVF_gc = (0x46<<0), /* Timer/Counter C1 Overflow */ - DMA_CH_TRIGSRC_TCC1_ERR_gc = (0x47<<0), /* Timer/Counter C1 Error */ - DMA_CH_TRIGSRC_TCC1_CCA_gc = (0x48<<0), /* Timer/Counter C1 Compare or Capture A */ - DMA_CH_TRIGSRC_TCC1_CCB_gc = (0x49<<0), /* Timer/Counter C1 Compare or Capture B */ - DMA_CH_TRIGSRC_SPIC_gc = (0x4A<<0), /* SPI C Transfer Complete */ - DMA_CH_TRIGSRC_USARTC0_RXC_gc = (0x4B<<0), /* USART C0 Receive Complete */ - DMA_CH_TRIGSRC_USARTC0_DRE_gc = (0x4C<<0), /* USART C0 Data Register Empty */ - DMA_CH_TRIGSRC_USARTC1_RXC_gc = (0x4E<<0), /* USART C1 Receive Complete */ - DMA_CH_TRIGSRC_USARTC1_DRE_gc = (0x4F<<0), /* USART C1 Data Register Empty */ - DMA_CH_TRIGSRC_TCD0_OVF_gc = (0x60<<0), /* Timer/Counter D0 Overflow */ - DMA_CH_TRIGSRC_TCD0_ERR_gc = (0x61<<0), /* Timer/Counter D0 Error */ - DMA_CH_TRIGSRC_TCD0_CCA_gc = (0x62<<0), /* Timer/Counter D0 Compare or Capture A */ - DMA_CH_TRIGSRC_TCD0_CCB_gc = (0x63<<0), /* Timer/Counter D0 Compare or Capture B */ - DMA_CH_TRIGSRC_TCD0_CCC_gc = (0x64<<0), /* Timer/Counter D0 Compare or Capture C */ - DMA_CH_TRIGSRC_TCD0_CCD_gc = (0x65<<0), /* Timer/Counter D0 Compare or Capture D */ - DMA_CH_TRIGSRC_TCD1_OVF_gc = (0x66<<0), /* Timer/Counter D1 Overflow */ - DMA_CH_TRIGSRC_TCD1_ERR_gc = (0x67<<0), /* Timer/Counter D1 Error */ - DMA_CH_TRIGSRC_TCD1_CCA_gc = (0x68<<0), /* Timer/Counter D1 Compare or Capture A */ - DMA_CH_TRIGSRC_TCD1_CCB_gc = (0x69<<0), /* Timer/Counter D1 Compare or Capture B */ - DMA_CH_TRIGSRC_SPID_gc = (0x6A<<0), /* SPI D Transfer Complete */ - DMA_CH_TRIGSRC_USARTD0_RXC_gc = (0x6B<<0), /* USART D0 Receive Complete */ - DMA_CH_TRIGSRC_USARTD0_DRE_gc = (0x6C<<0), /* USART D0 Data Register Empty */ - DMA_CH_TRIGSRC_USARTD1_RXC_gc = (0x6E<<0), /* USART D1 Receive Complete */ - DMA_CH_TRIGSRC_USARTD1_DRE_gc = (0x6F<<0), /* USART D1 Data Register Empty */ - DMA_CH_TRIGSRC_TCE0_OVF_gc = (0x80<<0), /* Timer/Counter E0 Overflow */ - DMA_CH_TRIGSRC_TCE0_ERR_gc = (0x81<<0), /* Timer/Counter E0 Error */ - DMA_CH_TRIGSRC_TCE0_CCA_gc = (0x82<<0), /* Timer/Counter E0 Compare or Capture A */ - DMA_CH_TRIGSRC_TCE0_CCB_gc = (0x83<<0), /* Timer/Counter E0 Compare or Capture B */ - DMA_CH_TRIGSRC_TCE0_CCC_gc = (0x84<<0), /* Timer/Counter E0 Compare or Capture C */ - DMA_CH_TRIGSRC_TCE0_CCD_gc = (0x85<<0), /* Timer/Counter E0 Compare or Capture D */ - DMA_CH_TRIGSRC_TCE1_OVF_gc = (0x86<<0), /* Timer/Counter E1 Overflow */ - DMA_CH_TRIGSRC_TCE1_ERR_gc = (0x87<<0), /* Timer/Counter E1 Error */ - DMA_CH_TRIGSRC_TCE1_CCA_gc = (0x88<<0), /* Timer/Counter E1 Compare or Capture A */ - DMA_CH_TRIGSRC_TCE1_CCB_gc = (0x89<<0), /* Timer/Counter E1 Compare or Capture B */ - DMA_CH_TRIGSRC_SPIE_gc = (0x8A<<0), /* SPI E Transfer Complete */ - DMA_CH_TRIGSRC_USARTE0_RXC_gc = (0x8B<<0), /* USART E0 Receive Complete */ - DMA_CH_TRIGSRC_USARTE0_DRE_gc = (0x8C<<0), /* USART E0 Data Register Empty */ - DMA_CH_TRIGSRC_USARTE1_RXC_gc = (0x8E<<0), /* USART E1 Receive Complete */ - DMA_CH_TRIGSRC_USARTE1_DRE_gc = (0x8F<<0), /* USART E1 Data Register Empty */ - DMA_CH_TRIGSRC_TCF0_OVF_gc = (0xA0<<0), /* Timer/Counter F0 Overflow */ - DMA_CH_TRIGSRC_TCF0_ERR_gc = (0xA1<<0), /* Timer/Counter F0 Error */ - DMA_CH_TRIGSRC_TCF0_CCA_gc = (0xA2<<0), /* Timer/Counter F0 Compare or Capture A */ - DMA_CH_TRIGSRC_TCF0_CCB_gc = (0xA3<<0), /* Timer/Counter F0 Compare or Capture B */ - DMA_CH_TRIGSRC_TCF0_CCC_gc = (0xA4<<0), /* Timer/Counter F0 Compare or Capture C */ - DMA_CH_TRIGSRC_TCF0_CCD_gc = (0xA5<<0), /* Timer/Counter F0 Compare or Capture D */ - DMA_CH_TRIGSRC_TCF1_OVF_gc = (0xA6<<0), /* Timer/Counter F1 Overflow */ - DMA_CH_TRIGSRC_TCF1_ERR_gc = (0xA7<<0), /* Timer/Counter F1 Error */ - DMA_CH_TRIGSRC_TCF1_CCA_gc = (0xA8<<0), /* Timer/Counter F1 Compare or Capture A */ - DMA_CH_TRIGSRC_TCF1_CCB_gc = (0xA9<<0), /* Timer/Counter F1 Compare or Capture B */ - DMA_CH_TRIGSRC_SPIF_gc = (0xAA<<0), /* SPI F Transfer Complete */ - DMA_CH_TRIGSRC_USARTF0_RXC_gc = (0xAB<<0), /* USART F0 Receive Complete */ - DMA_CH_TRIGSRC_USARTF0_DRE_gc = (0xAC<<0), /* USART F0 Data Register Empty */ - DMA_CH_TRIGSRC_USARTF1_RXC_gc = (0xAE<<0), /* USART F1 Receive Complete */ - DMA_CH_TRIGSRC_USARTF1_DRE_gc = (0xAF<<0), /* USART F1 Data Register Empty */ -} DMA_CH_TRIGSRC_t; - -/* Double buffering mode */ -typedef enum DMA_DBUFMODE_enum -{ - DMA_DBUFMODE_DISABLED_gc = (0x00<<2), /* Double buffering disabled */ - DMA_DBUFMODE_CH01_gc = (0x01<<2), /* Double buffering enabled on channel 0/1 */ - DMA_DBUFMODE_CH23_gc = (0x02<<2), /* Double buffering enabled on channel 2/3 */ - DMA_DBUFMODE_CH01CH23_gc = (0x03<<2), /* Double buffering enabled on ch. 0/1 and ch. 2/3 */ -} DMA_DBUFMODE_t; - -/* Priority mode */ -typedef enum DMA_PRIMODE_enum -{ - DMA_PRIMODE_RR0123_gc = (0x00<<0), /* Round Robin */ - DMA_PRIMODE_CH0RR123_gc = (0x01<<0), /* Channel 0 > Round Robin on channel 1/2/3 */ - DMA_PRIMODE_CH01RR23_gc = (0x02<<0), /* Channel 0 > channel 1 > Round Robin on channel 2/3 */ - DMA_PRIMODE_CH0123_gc = (0x03<<0), /* Channel 0 > channel 1 > channel 2 > channel 3 */ -} DMA_PRIMODE_t; - -/* Interrupt level */ -typedef enum DMA_CH_ERRINTLVL_enum -{ - DMA_CH_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ - DMA_CH_ERRINTLVL_LO_gc = (0x01<<2), /* Low level */ - DMA_CH_ERRINTLVL_MED_gc = (0x02<<2), /* Medium level */ - DMA_CH_ERRINTLVL_HI_gc = (0x03<<2), /* High level */ -} DMA_CH_ERRINTLVL_t; - -/* Interrupt level */ -typedef enum DMA_CH_TRNINTLVL_enum -{ - DMA_CH_TRNINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ - DMA_CH_TRNINTLVL_LO_gc = (0x01<<0), /* Low level */ - DMA_CH_TRNINTLVL_MED_gc = (0x02<<0), /* Medium level */ - DMA_CH_TRNINTLVL_HI_gc = (0x03<<0), /* High level */ -} DMA_CH_TRNINTLVL_t; - - -/* --------------------------------------------------------------------------- -EVSYS - Event System --------------------------------------------------------------------------- -*/ - -/* Event System */ -typedef struct EVSYS_struct -{ - register8_t CH0MUX; /* Event Channel 0 Multiplexer */ - register8_t CH1MUX; /* Event Channel 1 Multiplexer */ - register8_t CH2MUX; /* Event Channel 2 Multiplexer */ - register8_t CH3MUX; /* Event Channel 3 Multiplexer */ - register8_t CH4MUX; /* Event Channel 4 Multiplexer */ - register8_t CH5MUX; /* Event Channel 5 Multiplexer */ - register8_t CH6MUX; /* Event Channel 6 Multiplexer */ - register8_t CH7MUX; /* Event Channel 7 Multiplexer */ - register8_t CH0CTRL; /* Channel 0 Control Register */ - register8_t CH1CTRL; /* Channel 1 Control Register */ - register8_t CH2CTRL; /* Channel 2 Control Register */ - register8_t CH3CTRL; /* Channel 3 Control Register */ - register8_t CH4CTRL; /* Channel 4 Control Register */ - register8_t CH5CTRL; /* Channel 5 Control Register */ - register8_t CH6CTRL; /* Channel 6 Control Register */ - register8_t CH7CTRL; /* Channel 7 Control Register */ - register8_t STROBE; /* Event Strobe */ - register8_t DATA; /* Event Data */ -} EVSYS_t; - -/* Quadrature Decoder Index Recognition Mode */ -typedef enum EVSYS_QDIRM_enum -{ - EVSYS_QDIRM_00_gc = (0x00<<5), /* QDPH0 = 0, QDPH90 = 0 */ - EVSYS_QDIRM_01_gc = (0x01<<5), /* QDPH0 = 0, QDPH90 = 1 */ - EVSYS_QDIRM_10_gc = (0x02<<5), /* QDPH0 = 1, QDPH90 = 0 */ - EVSYS_QDIRM_11_gc = (0x03<<5), /* QDPH0 = 1, QDPH90 = 1 */ -} EVSYS_QDIRM_t; - -/* Digital filter coefficient */ -typedef enum EVSYS_DIGFILT_enum -{ - EVSYS_DIGFILT_1SAMPLE_gc = (0x00<<0), /* 1 SAMPLE */ - EVSYS_DIGFILT_2SAMPLES_gc = (0x01<<0), /* 2 SAMPLES */ - EVSYS_DIGFILT_3SAMPLES_gc = (0x02<<0), /* 3 SAMPLES */ - EVSYS_DIGFILT_4SAMPLES_gc = (0x03<<0), /* 4 SAMPLES */ - EVSYS_DIGFILT_5SAMPLES_gc = (0x04<<0), /* 5 SAMPLES */ - EVSYS_DIGFILT_6SAMPLES_gc = (0x05<<0), /* 6 SAMPLES */ - EVSYS_DIGFILT_7SAMPLES_gc = (0x06<<0), /* 7 SAMPLES */ - EVSYS_DIGFILT_8SAMPLES_gc = (0x07<<0), /* 8 SAMPLES */ -} EVSYS_DIGFILT_t; - -/* Event Channel multiplexer input selection */ -typedef enum EVSYS_CHMUX_enum -{ - EVSYS_CHMUX_OFF_gc = (0x00<<0), /* Off */ - EVSYS_CHMUX_RTC_OVF_gc = (0x08<<0), /* RTC Overflow */ - EVSYS_CHMUX_RTC_CMP_gc = (0x09<<0), /* RTC Compare Match */ - EVSYS_CHMUX_ACA_CH0_gc = (0x10<<0), /* Analog Comparator A Channel 0 */ - EVSYS_CHMUX_ACA_CH1_gc = (0x11<<0), /* Analog Comparator A Channel 1 */ - EVSYS_CHMUX_ACA_WIN_gc = (0x12<<0), /* Analog Comparator A Window */ - EVSYS_CHMUX_ACB_CH0_gc = (0x13<<0), /* Analog Comparator B Channel 0 */ - EVSYS_CHMUX_ACB_CH1_gc = (0x14<<0), /* Analog Comparator B Channel 1 */ - EVSYS_CHMUX_ACB_WIN_gc = (0x15<<0), /* Analog Comparator B Window */ - EVSYS_CHMUX_ADCA_CH0_gc = (0x20<<0), /* ADC A Channel 0 */ - EVSYS_CHMUX_ADCA_CH1_gc = (0x21<<0), /* ADC A Channel 1 */ - EVSYS_CHMUX_ADCA_CH2_gc = (0x22<<0), /* ADC A Channel 2 */ - EVSYS_CHMUX_ADCA_CH3_gc = (0x23<<0), /* ADC A Channel 3 */ - EVSYS_CHMUX_ADCB_CH0_gc = (0x24<<0), /* ADC B Channel 0 */ - EVSYS_CHMUX_ADCB_CH1_gc = (0x25<<0), /* ADC B Channel 1 */ - EVSYS_CHMUX_ADCB_CH2_gc = (0x26<<0), /* ADC B Channel 2 */ - EVSYS_CHMUX_ADCB_CH3_gc = (0x27<<0), /* ADC B Channel 3 */ - EVSYS_CHMUX_PORTA_PIN0_gc = (0x50<<0), /* Port A, Pin0 */ - EVSYS_CHMUX_PORTA_PIN1_gc = (0x51<<0), /* Port A, Pin1 */ - EVSYS_CHMUX_PORTA_PIN2_gc = (0x52<<0), /* Port A, Pin2 */ - EVSYS_CHMUX_PORTA_PIN3_gc = (0x53<<0), /* Port A, Pin3 */ - EVSYS_CHMUX_PORTA_PIN4_gc = (0x54<<0), /* Port A, Pin4 */ - EVSYS_CHMUX_PORTA_PIN5_gc = (0x55<<0), /* Port A, Pin5 */ - EVSYS_CHMUX_PORTA_PIN6_gc = (0x56<<0), /* Port A, Pin6 */ - EVSYS_CHMUX_PORTA_PIN7_gc = (0x57<<0), /* Port A, Pin7 */ - EVSYS_CHMUX_PORTB_PIN0_gc = (0x58<<0), /* Port B, Pin0 */ - EVSYS_CHMUX_PORTB_PIN1_gc = (0x59<<0), /* Port B, Pin1 */ - EVSYS_CHMUX_PORTB_PIN2_gc = (0x5A<<0), /* Port B, Pin2 */ - EVSYS_CHMUX_PORTB_PIN3_gc = (0x5B<<0), /* Port B, Pin3 */ - EVSYS_CHMUX_PORTB_PIN4_gc = (0x5C<<0), /* Port B, Pin4 */ - EVSYS_CHMUX_PORTB_PIN5_gc = (0x5D<<0), /* Port B, Pin5 */ - EVSYS_CHMUX_PORTB_PIN6_gc = (0x5E<<0), /* Port B, Pin6 */ - EVSYS_CHMUX_PORTB_PIN7_gc = (0x5F<<0), /* Port B, Pin7 */ - EVSYS_CHMUX_PORTC_PIN0_gc = (0x60<<0), /* Port C, Pin0 */ - EVSYS_CHMUX_PORTC_PIN1_gc = (0x61<<0), /* Port C, Pin1 */ - EVSYS_CHMUX_PORTC_PIN2_gc = (0x62<<0), /* Port C, Pin2 */ - EVSYS_CHMUX_PORTC_PIN3_gc = (0x63<<0), /* Port C, Pin3 */ - EVSYS_CHMUX_PORTC_PIN4_gc = (0x64<<0), /* Port C, Pin4 */ - EVSYS_CHMUX_PORTC_PIN5_gc = (0x65<<0), /* Port C, Pin5 */ - EVSYS_CHMUX_PORTC_PIN6_gc = (0x66<<0), /* Port C, Pin6 */ - EVSYS_CHMUX_PORTC_PIN7_gc = (0x67<<0), /* Port C, Pin7 */ - EVSYS_CHMUX_PORTD_PIN0_gc = (0x68<<0), /* Port D, Pin0 */ - EVSYS_CHMUX_PORTD_PIN1_gc = (0x69<<0), /* Port D, Pin1 */ - EVSYS_CHMUX_PORTD_PIN2_gc = (0x6A<<0), /* Port D, Pin2 */ - EVSYS_CHMUX_PORTD_PIN3_gc = (0x6B<<0), /* Port D, Pin3 */ - EVSYS_CHMUX_PORTD_PIN4_gc = (0x6C<<0), /* Port D, Pin4 */ - EVSYS_CHMUX_PORTD_PIN5_gc = (0x6D<<0), /* Port D, Pin5 */ - EVSYS_CHMUX_PORTD_PIN6_gc = (0x6E<<0), /* Port D, Pin6 */ - EVSYS_CHMUX_PORTD_PIN7_gc = (0x6F<<0), /* Port D, Pin7 */ - EVSYS_CHMUX_PORTE_PIN0_gc = (0x70<<0), /* Port E, Pin0 */ - EVSYS_CHMUX_PORTE_PIN1_gc = (0x71<<0), /* Port E, Pin1 */ - EVSYS_CHMUX_PORTE_PIN2_gc = (0x72<<0), /* Port E, Pin2 */ - EVSYS_CHMUX_PORTE_PIN3_gc = (0x73<<0), /* Port E, Pin3 */ - EVSYS_CHMUX_PORTE_PIN4_gc = (0x74<<0), /* Port E, Pin4 */ - EVSYS_CHMUX_PORTE_PIN5_gc = (0x75<<0), /* Port E, Pin5 */ - EVSYS_CHMUX_PORTE_PIN6_gc = (0x76<<0), /* Port E, Pin6 */ - EVSYS_CHMUX_PORTE_PIN7_gc = (0x77<<0), /* Port E, Pin7 */ - EVSYS_CHMUX_PORTF_PIN0_gc = (0x78<<0), /* Port F, Pin0 */ - EVSYS_CHMUX_PORTF_PIN1_gc = (0x79<<0), /* Port F, Pin1 */ - EVSYS_CHMUX_PORTF_PIN2_gc = (0x7A<<0), /* Port F, Pin2 */ - EVSYS_CHMUX_PORTF_PIN3_gc = (0x7B<<0), /* Port F, Pin3 */ - EVSYS_CHMUX_PORTF_PIN4_gc = (0x7C<<0), /* Port F, Pin4 */ - EVSYS_CHMUX_PORTF_PIN5_gc = (0x7D<<0), /* Port F, Pin5 */ - EVSYS_CHMUX_PORTF_PIN6_gc = (0x7E<<0), /* Port F, Pin6 */ - EVSYS_CHMUX_PORTF_PIN7_gc = (0x7F<<0), /* Port F, Pin7 */ - EVSYS_CHMUX_PRESCALER_1_gc = (0x80<<0), /* Prescaler, divide by 1 */ - EVSYS_CHMUX_PRESCALER_2_gc = (0x81<<0), /* Prescaler, divide by 2 */ - EVSYS_CHMUX_PRESCALER_4_gc = (0x82<<0), /* Prescaler, divide by 4 */ - EVSYS_CHMUX_PRESCALER_8_gc = (0x83<<0), /* Prescaler, divide by 8 */ - EVSYS_CHMUX_PRESCALER_16_gc = (0x84<<0), /* Prescaler, divide by 16 */ - EVSYS_CHMUX_PRESCALER_32_gc = (0x85<<0), /* Prescaler, divide by 32 */ - EVSYS_CHMUX_PRESCALER_64_gc = (0x86<<0), /* Prescaler, divide by 64 */ - EVSYS_CHMUX_PRESCALER_128_gc = (0x87<<0), /* Prescaler, divide by 128 */ - EVSYS_CHMUX_PRESCALER_256_gc = (0x88<<0), /* Prescaler, divide by 256 */ - EVSYS_CHMUX_PRESCALER_512_gc = (0x89<<0), /* Prescaler, divide by 512 */ - EVSYS_CHMUX_PRESCALER_1024_gc = (0x8A<<0), /* Prescaler, divide by 1024 */ - EVSYS_CHMUX_PRESCALER_2048_gc = (0x8B<<0), /* Prescaler, divide by 2048 */ - EVSYS_CHMUX_PRESCALER_4096_gc = (0x8C<<0), /* Prescaler, divide by 4096 */ - EVSYS_CHMUX_PRESCALER_8192_gc = (0x8D<<0), /* Prescaler, divide by 8192 */ - EVSYS_CHMUX_PRESCALER_16384_gc = (0x8E<<0), /* Prescaler, divide by 16384 */ - EVSYS_CHMUX_PRESCALER_32768_gc = (0x8F<<0), /* Prescaler, divide by 32768 */ - EVSYS_CHMUX_TCC0_OVF_gc = (0xC0<<0), /* Timer/Counter C0 Overflow */ - EVSYS_CHMUX_TCC0_ERR_gc = (0xC1<<0), /* Timer/Counter C0 Error */ - EVSYS_CHMUX_TCC0_CCA_gc = (0xC4<<0), /* Timer/Counter C0 Compare or Capture A */ - EVSYS_CHMUX_TCC0_CCB_gc = (0xC5<<0), /* Timer/Counter C0 Compare or Capture B */ - EVSYS_CHMUX_TCC0_CCC_gc = (0xC6<<0), /* Timer/Counter C0 Compare or Capture C */ - EVSYS_CHMUX_TCC0_CCD_gc = (0xC7<<0), /* Timer/Counter C0 Compare or Capture D */ - EVSYS_CHMUX_TCC1_OVF_gc = (0xC8<<0), /* Timer/Counter C1 Overflow */ - EVSYS_CHMUX_TCC1_ERR_gc = (0xC9<<0), /* Timer/Counter C1 Error */ - EVSYS_CHMUX_TCC1_CCA_gc = (0xCC<<0), /* Timer/Counter C1 Compare or Capture A */ - EVSYS_CHMUX_TCC1_CCB_gc = (0xCD<<0), /* Timer/Counter C1 Compare or Capture B */ - EVSYS_CHMUX_TCD0_OVF_gc = (0xD0<<0), /* Timer/Counter D0 Overflow */ - EVSYS_CHMUX_TCD0_ERR_gc = (0xD1<<0), /* Timer/Counter D0 Error */ - EVSYS_CHMUX_TCD0_CCA_gc = (0xD4<<0), /* Timer/Counter D0 Compare or Capture A */ - EVSYS_CHMUX_TCD0_CCB_gc = (0xD5<<0), /* Timer/Counter D0 Compare or Capture B */ - EVSYS_CHMUX_TCD0_CCC_gc = (0xD6<<0), /* Timer/Counter D0 Compare or Capture C */ - EVSYS_CHMUX_TCD0_CCD_gc = (0xD7<<0), /* Timer/Counter D0 Compare or Capture D */ - EVSYS_CHMUX_TCD1_OVF_gc = (0xD8<<0), /* Timer/Counter D1 Overflow */ - EVSYS_CHMUX_TCD1_ERR_gc = (0xD9<<0), /* Timer/Counter D1 Error */ - EVSYS_CHMUX_TCD1_CCA_gc = (0xDC<<0), /* Timer/Counter D1 Compare or Capture A */ - EVSYS_CHMUX_TCD1_CCB_gc = (0xDD<<0), /* Timer/Counter D1 Compare or Capture B */ - EVSYS_CHMUX_TCE0_OVF_gc = (0xE0<<0), /* Timer/Counter E0 Overflow */ - EVSYS_CHMUX_TCE0_ERR_gc = (0xE1<<0), /* Timer/Counter E0 Error */ - EVSYS_CHMUX_TCE0_CCA_gc = (0xE4<<0), /* Timer/Counter E0 Compare or Capture A */ - EVSYS_CHMUX_TCE0_CCB_gc = (0xE5<<0), /* Timer/Counter E0 Compare or Capture B */ - EVSYS_CHMUX_TCE0_CCC_gc = (0xE6<<0), /* Timer/Counter E0 Compare or Capture C */ - EVSYS_CHMUX_TCE0_CCD_gc = (0xE7<<0), /* Timer/Counter E0 Compare or Capture D */ - EVSYS_CHMUX_TCE1_OVF_gc = (0xE8<<0), /* Timer/Counter E1 Overflow */ - EVSYS_CHMUX_TCE1_ERR_gc = (0xE9<<0), /* Timer/Counter E1 Error */ - EVSYS_CHMUX_TCE1_CCA_gc = (0xEC<<0), /* Timer/Counter E1 Compare or Capture A */ - EVSYS_CHMUX_TCE1_CCB_gc = (0xED<<0), /* Timer/Counter E1 Compare or Capture B */ - EVSYS_CHMUX_TCF0_OVF_gc = (0xF0<<0), /* Timer/Counter F0 Overflow */ - EVSYS_CHMUX_TCF0_ERR_gc = (0xF1<<0), /* Timer/Counter F0 Error */ - EVSYS_CHMUX_TCF0_CCA_gc = (0xF4<<0), /* Timer/Counter F0 Compare or Capture A */ - EVSYS_CHMUX_TCF0_CCB_gc = (0xF5<<0), /* Timer/Counter F0 Compare or Capture B */ - EVSYS_CHMUX_TCF0_CCC_gc = (0xF6<<0), /* Timer/Counter F0 Compare or Capture C */ - EVSYS_CHMUX_TCF0_CCD_gc = (0xF7<<0), /* Timer/Counter F0 Compare or Capture D */ - EVSYS_CHMUX_TCF1_OVF_gc = (0xF8<<0), /* Timer/Counter F1 Overflow */ - EVSYS_CHMUX_TCF1_ERR_gc = (0xF9<<0), /* Timer/Counter F1 Error */ - EVSYS_CHMUX_TCF1_CCA_gc = (0xFC<<0), /* Timer/Counter F1 Compare or Capture A */ - EVSYS_CHMUX_TCF1_CCB_gc = (0xFD<<0), /* Timer/Counter F1 Compare or Capture B */ -} EVSYS_CHMUX_t; - - -/* --------------------------------------------------------------------------- -NVM - Non Volatile Memory Controller --------------------------------------------------------------------------- -*/ - -/* Non-volatile Memory Controller */ -typedef struct NVM_struct -{ - register8_t ADDR0; /* Address Register 0 */ - register8_t ADDR1; /* Address Register 1 */ - register8_t ADDR2; /* Address Register 2 */ - register8_t reserved_0x03; - register8_t DATA0; /* Data Register 0 */ - register8_t DATA1; /* Data Register 1 */ - register8_t DATA2; /* Data Register 2 */ - register8_t reserved_0x07; - register8_t reserved_0x08; - register8_t reserved_0x09; - register8_t CMD; /* Command */ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t INTCTRL; /* Interrupt Control */ - register8_t reserved_0x0E; - register8_t STATUS; /* Status */ - register8_t LOCK_BITS; /* Lock Bits */ -} NVM_t; - -/* --------------------------------------------------------------------------- -NVM - Non Volatile Memory Controller --------------------------------------------------------------------------- -*/ - -/* Lock Bits */ -typedef struct NVM_LOCKBITS_struct -{ - register8_t LOCKBITS; /* Lock Bits */ -} NVM_LOCKBITS_t; - -/* --------------------------------------------------------------------------- -NVM - Non Volatile Memory Controller --------------------------------------------------------------------------- -*/ - -/* Fuses */ -typedef struct NVM_FUSES_struct -{ - register8_t FUSEBYTE0; /* JTAG User ID */ - register8_t FUSEBYTE1; /* Watchdog Configuration */ - register8_t FUSEBYTE2; /* Reset Configuration */ - register8_t reserved_0x03; - register8_t FUSEBYTE4; /* Start-up Configuration */ - register8_t FUSEBYTE5; /* EESAVE and BOD Level */ -} NVM_FUSES_t; - -/* --------------------------------------------------------------------------- -NVM - Non Volatile Memory Controller --------------------------------------------------------------------------- -*/ - -/* Production Signatures */ -typedef struct NVM_PROD_SIGNATURES_struct -{ - register8_t RCOSC2M; /* RCOSC 2MHz Calibration Value */ - register8_t reserved_0x01; - register8_t RCOSC32K; /* RCOSC 32kHz Calibration Value */ - register8_t RCOSC32M; /* RCOSC 32MHz Calibration Value */ - register8_t reserved_0x04; - register8_t reserved_0x05; - register8_t reserved_0x06; - register8_t reserved_0x07; - register8_t LOTNUM0; /* Lot Number Byte 0, ASCII */ - register8_t LOTNUM1; /* Lot Number Byte 1, ASCII */ - register8_t LOTNUM2; /* Lot Number Byte 2, ASCII */ - register8_t LOTNUM3; /* Lot Number Byte 3, ASCII */ - register8_t LOTNUM4; /* Lot Number Byte 4, ASCII */ - register8_t LOTNUM5; /* Lot Number Byte 5, ASCII */ - register8_t reserved_0x0E; - register8_t reserved_0x0F; - register8_t WAFNUM; /* Wafer Number */ - register8_t reserved_0x11; - register8_t COORDX0; /* Wafer Coordinate X Byte 0 */ - register8_t COORDX1; /* Wafer Coordinate X Byte 1 */ - register8_t COORDY0; /* Wafer Coordinate Y Byte 0 */ - register8_t COORDY1; /* Wafer Coordinate Y Byte 1 */ - register8_t reserved_0x16; - register8_t reserved_0x17; - register8_t reserved_0x18; - register8_t reserved_0x19; - register8_t reserved_0x1A; - register8_t reserved_0x1B; - register8_t reserved_0x1C; - register8_t reserved_0x1D; - register8_t reserved_0x1E; - register8_t reserved_0x1F; - register8_t ADCACAL0; /* ADCA Calibration Byte 0 */ - register8_t ADCACAL1; /* ADCA Calibration Byte 1 */ - register8_t reserved_0x22; - register8_t reserved_0x23; - register8_t ADCBCAL0; /* ADCB Calibration Byte 0 */ - register8_t ADCBCAL1; /* ADCB Calibration Byte 1 */ - register8_t reserved_0x26; - register8_t reserved_0x27; - register8_t reserved_0x28; - register8_t reserved_0x29; - register8_t reserved_0x2A; - register8_t reserved_0x2B; - register8_t reserved_0x2C; - register8_t reserved_0x2D; - register8_t TEMPSENSE0; /* Temperature Sensor Calibration Byte 0 */ - register8_t TEMPSENSE1; /* Temperature Sensor Calibration Byte 0 */ - register8_t DACAOFFCAL; /* DACA Calibration Byte 0 */ - register8_t DACAGAINCAL; /* DACA Calibration Byte 1 */ - register8_t DACBOFFCAL; /* DACB Calibration Byte 0 */ - register8_t DACBGAINCAL; /* DACB Calibration Byte 1 */ - register8_t reserved_0x34; - register8_t reserved_0x35; - register8_t reserved_0x36; - register8_t reserved_0x37; - register8_t reserved_0x38; - register8_t reserved_0x39; - register8_t reserved_0x3A; - register8_t reserved_0x3B; - register8_t reserved_0x3C; - register8_t reserved_0x3D; - register8_t reserved_0x3E; -} NVM_PROD_SIGNATURES_t; - -/* NVM Command */ -typedef enum NVM_CMD_enum -{ - NVM_CMD_NO_OPERATION_gc = (0x00<<0), /* Noop/Ordinary LPM */ - NVM_CMD_READ_CALIB_ROW_gc = (0x02<<0), /* Read calibration row */ - NVM_CMD_READ_USER_SIG_ROW_gc = (0x01<<0), /* Read user signature row */ - NVM_CMD_READ_EEPROM_gc = (0x06<<0), /* Read EEPROM */ - NVM_CMD_READ_FUSES_gc = (0x07<<0), /* Read fuse byte */ - NVM_CMD_WRITE_LOCK_BITS_gc = (0x08<<0), /* Write lock bits */ - NVM_CMD_ERASE_USER_SIG_ROW_gc = (0x18<<0), /* Erase user signature row */ - NVM_CMD_WRITE_USER_SIG_ROW_gc = (0x1A<<0), /* Write user signature row */ - NVM_CMD_ERASE_APP_gc = (0x20<<0), /* Erase Application Section */ - NVM_CMD_ERASE_APP_PAGE_gc = (0x22<<0), /* Erase Application Section page */ - NVM_CMD_LOAD_FLASH_BUFFER_gc = (0x23<<0), /* Load Flash page buffer */ - NVM_CMD_WRITE_APP_PAGE_gc = (0x24<<0), /* Write Application Section page */ - NVM_CMD_ERASE_WRITE_APP_PAGE_gc = (0x25<<0), /* Erase-and-write Application Section page */ - NVM_CMD_ERASE_FLASH_BUFFER_gc = (0x26<<0), /* Erase/flush Flash page buffer */ - NVM_CMD_ERASE_BOOT_PAGE_gc = (0x2A<<0), /* Erase Boot Section page */ - NVM_CMD_WRITE_BOOT_PAGE_gc = (0x2C<<0), /* Write Boot Section page */ - NVM_CMD_ERASE_WRITE_BOOT_PAGE_gc = (0x2D<<0), /* Erase-and-write Boot Section page */ - NVM_CMD_ERASE_EEPROM_gc = (0x30<<0), /* Erase EEPROM */ - NVM_CMD_ERASE_EEPROM_PAGE_gc = (0x32<<0), /* Erase EEPROM page */ - NVM_CMD_LOAD_EEPROM_BUFFER_gc = (0x33<<0), /* Load EEPROM page buffer */ - NVM_CMD_WRITE_EEPROM_PAGE_gc = (0x34<<0), /* Write EEPROM page */ - NVM_CMD_ERASE_WRITE_EEPROM_PAGE_gc = (0x35<<0), /* Erase-and-write EEPROM page */ - NVM_CMD_ERASE_EEPROM_BUFFER_gc = (0x36<<0), /* Erase/flush EEPROM page buffer */ - NVM_CMD_APP_CRC_gc = (0x38<<0), /* Generate Application section CRC */ - NVM_CMD_BOOT_CRC_gc = (0x39<<0), /* Generate Boot Section CRC */ - NVM_CMD_FLASH_RANGE_CRC_gc = (0x3A<<0), /* Generate Flash Range CRC */ -} NVM_CMD_t; - -/* SPM ready interrupt level */ -typedef enum NVM_SPMLVL_enum -{ - NVM_SPMLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ - NVM_SPMLVL_LO_gc = (0x01<<2), /* Low level */ - NVM_SPMLVL_MED_gc = (0x02<<2), /* Medium level */ - NVM_SPMLVL_HI_gc = (0x03<<2), /* High level */ -} NVM_SPMLVL_t; - -/* EEPROM ready interrupt level */ -typedef enum NVM_EELVL_enum -{ - NVM_EELVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ - NVM_EELVL_LO_gc = (0x01<<0), /* Low level */ - NVM_EELVL_MED_gc = (0x02<<0), /* Medium level */ - NVM_EELVL_HI_gc = (0x03<<0), /* High level */ -} NVM_EELVL_t; - -/* Boot lock bits - boot setcion */ -typedef enum NVM_BLBB_enum -{ - NVM_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ - NVM_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ - NVM_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ - NVM_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ -} NVM_BLBB_t; - -/* Boot lock bits - application section */ -typedef enum NVM_BLBA_enum -{ - NVM_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ - NVM_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ - NVM_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ - NVM_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ -} NVM_BLBA_t; - -/* Boot lock bits - application table section */ -typedef enum NVM_BLBAT_enum -{ - NVM_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ - NVM_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ - NVM_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ - NVM_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ -} NVM_BLBAT_t; - -/* Lock bits */ -typedef enum NVM_LB_enum -{ - NVM_LB_NOLOCK_gc = (0x03<<0), /* No locks */ - NVM_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ - NVM_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ -} NVM_LB_t; - -/* Boot Loader Section Reset Vector */ -typedef enum BOOTRST_enum -{ - BOOTRST_BOOTLDR_gc = (0x00<<6), /* Boot Loader Reset */ - BOOTRST_APPLICATION_gc = (0x01<<6), /* Application Reset */ -} BOOTRST_t; - -/* BOD operation */ -typedef enum BOD_enum -{ - BOD_INSAMPLEDMODE_gc = (0x01<<0), /* BOD enabled in sampled mode */ - BOD_CONTINOUSLY_gc = (0x02<<0), /* BOD enabled continuously */ - BOD_DISABLED_gc = (0x03<<0), /* BOD Disabled */ -} BOD_t; - -/* Watchdog (Window) Timeout Period */ -typedef enum WD_enum -{ - WD_8CLK_gc = (0x00<<4), /* 8 cycles (8ms @ 3.3V) */ - WD_16CLK_gc = (0x01<<4), /* 16 cycles (16ms @ 3.3V) */ - WD_32CLK_gc = (0x02<<4), /* 32 cycles (32ms @ 3.3V) */ - WD_64CLK_gc = (0x03<<4), /* 64 cycles (64ms @ 3.3V) */ - WD_128CLK_gc = (0x04<<4), /* 128 cycles (0.125s @ 3.3V) */ - WD_256CLK_gc = (0x05<<4), /* 256 cycles (0.25s @ 3.3V) */ - WD_512CLK_gc = (0x06<<4), /* 512 cycles (0.5s @ 3.3V) */ - WD_1KCLK_gc = (0x07<<4), /* 1K cycles (1s @ 3.3V) */ - WD_2KCLK_gc = (0x08<<4), /* 2K cycles (2s @ 3.3V) */ - WD_4KCLK_gc = (0x09<<4), /* 4K cycles (4s @ 3.3V) */ - WD_8KCLK_gc = (0x0A<<4), /* 8K cycles (8s @ 3.3V) */ -} WD_t; - -/* Start-up Time */ -typedef enum SUT_enum -{ - SUT_0MS_gc = (0x03<<2), /* 0 ms */ - SUT_4MS_gc = (0x01<<2), /* 4 ms */ - SUT_64MS_gc = (0x00<<2), /* 64 ms */ -} SUT_t; - -/* Brown Out Detection Voltage Level */ -typedef enum BODLVL_enum -{ - BODLVL_1V6_gc = (0x07<<0), /* 1.6 V */ - BODLVL_1V9_gc = (0x06<<0), /* 1.8 V */ - BODLVL_2V1_gc = (0x05<<0), /* 2.0 V */ - BODLVL_2V4_gc = (0x04<<0), /* 2.2 V */ - BODLVL_2V6_gc = (0x03<<0), /* 2.4 V */ - BODLVL_2V9_gc = (0x02<<0), /* 2.7 V */ - BODLVL_3V2_gc = (0x01<<0), /* 2.9 V */ -} BODLVL_t; - - -/* --------------------------------------------------------------------------- -AC - Analog Comparator --------------------------------------------------------------------------- -*/ - -/* Analog Comparator */ -typedef struct AC_struct -{ - register8_t AC0CTRL; /* Comparator 0 Control */ - register8_t AC1CTRL; /* Comparator 1 Control */ - register8_t AC0MUXCTRL; /* Comparator 0 MUX Control */ - register8_t AC1MUXCTRL; /* Comparator 1 MUX Control */ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t WINCTRL; /* Window Mode Control */ - register8_t STATUS; /* Status */ -} AC_t; - -/* Interrupt mode */ -typedef enum AC_INTMODE_enum -{ - AC_INTMODE_BOTHEDGES_gc = (0x00<<6), /* Interrupt on both edges */ - AC_INTMODE_FALLING_gc = (0x02<<6), /* Interrupt on falling edge */ - AC_INTMODE_RISING_gc = (0x03<<6), /* Interrupt on rising edge */ -} AC_INTMODE_t; - -/* Interrupt level */ -typedef enum AC_INTLVL_enum -{ - AC_INTLVL_OFF_gc = (0x00<<4), /* Interrupt disabled */ - AC_INTLVL_LO_gc = (0x01<<4), /* Low level */ - AC_INTLVL_MED_gc = (0x02<<4), /* Medium level */ - AC_INTLVL_HI_gc = (0x03<<4), /* High level */ -} AC_INTLVL_t; - -/* Hysteresis mode selection */ -typedef enum AC_HYSMODE_enum -{ - AC_HYSMODE_NO_gc = (0x00<<1), /* No hysteresis */ - AC_HYSMODE_SMALL_gc = (0x01<<1), /* Small hysteresis */ - AC_HYSMODE_LARGE_gc = (0x02<<1), /* Large hysteresis */ -} AC_HYSMODE_t; - -/* Positive input multiplexer selection */ -typedef enum AC_MUXPOS_enum -{ - AC_MUXPOS_PIN0_gc = (0x00<<3), /* Pin 0 */ - AC_MUXPOS_PIN1_gc = (0x01<<3), /* Pin 1 */ - AC_MUXPOS_PIN2_gc = (0x02<<3), /* Pin 2 */ - AC_MUXPOS_PIN3_gc = (0x03<<3), /* Pin 3 */ - AC_MUXPOS_PIN4_gc = (0x04<<3), /* Pin 4 */ - AC_MUXPOS_PIN5_gc = (0x05<<3), /* Pin 5 */ - AC_MUXPOS_PIN6_gc = (0x06<<3), /* Pin 6 */ - AC_MUXPOS_DAC_gc = (0x07<<3), /* DAC output */ -} AC_MUXPOS_t; - -/* Negative input multiplexer selection */ -typedef enum AC_MUXNEG_enum -{ - AC_MUXNEG_PIN0_gc = (0x00<<0), /* Pin 0 */ - AC_MUXNEG_PIN1_gc = (0x01<<0), /* Pin 1 */ - AC_MUXNEG_PIN3_gc = (0x02<<0), /* Pin 3 */ - AC_MUXNEG_PIN5_gc = (0x03<<0), /* Pin 5 */ - AC_MUXNEG_PIN7_gc = (0x04<<0), /* Pin 7 */ - AC_MUXNEG_DAC_gc = (0x05<<0), /* DAC output */ - AC_MUXNEG_BANDGAP_gc = (0x06<<0), /* Bandgap Reference */ - AC_MUXNEG_SCALER_gc = (0x07<<0), /* Internal voltage scaler */ -} AC_MUXNEG_t; - -/* Windows interrupt mode */ -typedef enum AC_WINTMODE_enum -{ - AC_WINTMODE_ABOVE_gc = (0x00<<2), /* Interrupt on above window */ - AC_WINTMODE_INSIDE_gc = (0x01<<2), /* Interrupt on inside window */ - AC_WINTMODE_BELOW_gc = (0x02<<2), /* Interrupt on below window */ - AC_WINTMODE_OUTSIDE_gc = (0x03<<2), /* Interrupt on outside window */ -} AC_WINTMODE_t; - -/* Window interrupt level */ -typedef enum AC_WINTLVL_enum -{ - AC_WINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ - AC_WINTLVL_LO_gc = (0x01<<0), /* Low priority */ - AC_WINTLVL_MED_gc = (0x02<<0), /* Medium priority */ - AC_WINTLVL_HI_gc = (0x03<<0), /* High priority */ -} AC_WINTLVL_t; - -/* Window mode state */ -typedef enum AC_WSTATE_enum -{ - AC_WSTATE_ABOVE_gc = (0x00<<6), /* Signal above window */ - AC_WSTATE_INSIDE_gc = (0x01<<6), /* Signal inside window */ - AC_WSTATE_BELOW_gc = (0x02<<6), /* Signal below window */ -} AC_WSTATE_t; - - -/* --------------------------------------------------------------------------- -ADC - Analog/Digital Converter --------------------------------------------------------------------------- -*/ - -/* ADC Channel */ -typedef struct ADC_CH_struct -{ - register8_t CTRL; /* Control Register */ - register8_t MUXCTRL; /* MUX Control */ - register8_t INTCTRL; /* Channel Interrupt Control */ - register8_t INTFLAGS; /* Interrupt Flags */ - _WORDREGISTER(RES); /* Channel Result */ - register8_t reserved_0x6; - register8_t reserved_0x7; -} ADC_CH_t; - -/* --------------------------------------------------------------------------- -ADC - Analog/Digital Converter --------------------------------------------------------------------------- -*/ - -/* Analog-to-Digital Converter */ -typedef struct ADC_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t REFCTRL; /* Reference Control */ - register8_t EVCTRL; /* Event Control */ - register8_t PRESCALER; /* Clock Prescaler */ - register8_t reserved_0x05; - register8_t INTFLAGS; /* Interrupt Flags */ - register8_t reserved_0x07; - register8_t reserved_0x08; - register8_t reserved_0x09; - register8_t reserved_0x0A; - register8_t reserved_0x0B; - _WORDREGISTER(CAL); /* Calibration Value */ - register8_t reserved_0x0E; - register8_t reserved_0x0F; - _WORDREGISTER(CH0RES); /* Channel 0 Result */ - _WORDREGISTER(CH1RES); /* Channel 1 Result */ - _WORDREGISTER(CH2RES); /* Channel 2 Result */ - _WORDREGISTER(CH3RES); /* Channel 3 Result */ - _WORDREGISTER(CMP); /* Compare Value */ - register8_t reserved_0x1A; - register8_t reserved_0x1B; - register8_t reserved_0x1C; - register8_t reserved_0x1D; - register8_t reserved_0x1E; - register8_t reserved_0x1F; - ADC_CH_t CH0; /* ADC Channel 0 */ - ADC_CH_t CH1; /* ADC Channel 1 */ - ADC_CH_t CH2; /* ADC Channel 2 */ - ADC_CH_t CH3; /* ADC Channel 3 */ -} ADC_t; - -/* Positive input multiplexer selection */ -typedef enum ADC_CH_MUXPOS_enum -{ - ADC_CH_MUXPOS_PIN0_gc = (0x00<<3), /* Input pin 0 */ - ADC_CH_MUXPOS_PIN1_gc = (0x01<<3), /* Input pin 1 */ - ADC_CH_MUXPOS_PIN2_gc = (0x02<<3), /* Input pin 2 */ - ADC_CH_MUXPOS_PIN3_gc = (0x03<<3), /* Input pin 3 */ - ADC_CH_MUXPOS_PIN4_gc = (0x04<<3), /* Input pin 4 */ - ADC_CH_MUXPOS_PIN5_gc = (0x05<<3), /* Input pin 5 */ - ADC_CH_MUXPOS_PIN6_gc = (0x06<<3), /* Input pin 6 */ - ADC_CH_MUXPOS_PIN7_gc = (0x07<<3), /* Input pin 7 */ -} ADC_CH_MUXPOS_t; - -/* Internal input multiplexer selections */ -typedef enum ADC_CH_MUXINT_enum -{ - ADC_CH_MUXINT_TEMP_gc = (0x00<<3), /* Temperature Reference */ - ADC_CH_MUXINT_BANDGAP_gc = (0x01<<3), /* Bandgap Reference */ - ADC_CH_MUXINT_SCALEDVCC_gc = (0x02<<3), /* 1/10 scaled VCC */ - ADC_CH_MUXINT_DAC_gc = (0x03<<3), /* DAC output */ -} ADC_CH_MUXINT_t; - -/* Negative input multiplexer selection */ -typedef enum ADC_CH_MUXNEG_enum -{ - ADC_CH_MUXNEG_PIN0_gc = (0x00<<0), /* Input pin 0 */ - ADC_CH_MUXNEG_PIN1_gc = (0x01<<0), /* Input pin 1 */ - ADC_CH_MUXNEG_PIN2_gc = (0x02<<0), /* Input pin 2 */ - ADC_CH_MUXNEG_PIN3_gc = (0x03<<0), /* Input pin 3 */ - ADC_CH_MUXNEG_PIN4_gc = (0x04<<0), /* Input pin 4 */ - ADC_CH_MUXNEG_PIN5_gc = (0x05<<0), /* Input pin 5 */ - ADC_CH_MUXNEG_PIN6_gc = (0x06<<0), /* Input pin 6 */ - ADC_CH_MUXNEG_PIN7_gc = (0x07<<0), /* Input pin 7 */ -} ADC_CH_MUXNEG_t; - -/* Input mode */ -typedef enum ADC_CH_INPUTMODE_enum -{ - ADC_CH_INPUTMODE_INTERNAL_gc = (0x00<<0), /* Internal inputs, no gain */ - ADC_CH_INPUTMODE_SINGLEENDED_gc = (0x01<<0), /* Single-ended input, no gain */ - ADC_CH_INPUTMODE_DIFF_gc = (0x02<<0), /* Differential input, no gain */ - ADC_CH_INPUTMODE_DIFFWGAIN_gc = (0x03<<0), /* Differential input, with gain */ -} ADC_CH_INPUTMODE_t; - -/* Gain factor */ -typedef enum ADC_CH_GAIN_enum -{ - ADC_CH_GAIN_1X_gc = (0x00<<2), /* 1x gain */ - ADC_CH_GAIN_2X_gc = (0x01<<2), /* 2x gain */ - ADC_CH_GAIN_4X_gc = (0x02<<2), /* 4x gain */ - ADC_CH_GAIN_8X_gc = (0x03<<2), /* 8x gain */ - ADC_CH_GAIN_16X_gc = (0x04<<2), /* 16x gain */ - ADC_CH_GAIN_32X_gc = (0x05<<2), /* 32x gain */ - ADC_CH_GAIN_64X_gc = (0x06<<2), /* 64x gain */ -} ADC_CH_GAIN_t; - -/* Conversion result resolution */ -typedef enum ADC_RESOLUTION_enum -{ - ADC_RESOLUTION_12BIT_gc = (0x00<<1), /* 12-bit right-adjusted result */ - ADC_RESOLUTION_8BIT_gc = (0x02<<1), /* 8-bit right-adjusted result */ - ADC_RESOLUTION_LEFT12BIT_gc = (0x03<<1), /* 12-bit left-adjusted result */ -} ADC_RESOLUTION_t; - -/* Voltage reference selection */ -typedef enum ADC_REFSEL_enum -{ - ADC_REFSEL_INT1V_gc = (0x00<<4), /* Internal 1V */ - ADC_REFSEL_VCC_gc = (0x01<<4), /* Internal VCC / 1.6V */ - ADC_REFSEL_AREFA_gc = (0x02<<4), /* External reference on PORT A */ - ADC_REFSEL_AREFB_gc = (0x03<<4), /* External reference on PORT B */ -} ADC_REFSEL_t; - -/* Channel sweep selection */ -typedef enum ADC_SWEEP_enum -{ - ADC_SWEEP_0_gc = (0x00<<6), /* ADC Channel 0 */ - ADC_SWEEP_01_gc = (0x01<<6), /* ADC Channel 0,1 */ - ADC_SWEEP_012_gc = (0x02<<6), /* ADC Channel 0,1,2 */ - ADC_SWEEP_0123_gc = (0x03<<6), /* ADC Channel 0,1,2,3 */ -} ADC_SWEEP_t; - -/* Event channel input selection */ -typedef enum ADC_EVSEL_enum -{ - ADC_EVSEL_0123_gc = (0x00<<3), /* Event Channel 0,1,2,3 */ - ADC_EVSEL_1234_gc = (0x01<<3), /* Event Channel 1,2,3,4 */ - ADC_EVSEL_2345_gc = (0x02<<3), /* Event Channel 2,3,4,5 */ - ADC_EVSEL_3456_gc = (0x03<<3), /* Event Channel 3,4,5,6 */ - ADC_EVSEL_4567_gc = (0x04<<3), /* Event Channel 4,5,6,7 */ - ADC_EVSEL_567_gc = (0x05<<3), /* Event Channel 5,6,7 */ - ADC_EVSEL_67_gc = (0x06<<3), /* Event Channel 6,7 */ - ADC_EVSEL_7_gc = (0x07<<3), /* Event Channel 7 */ -} ADC_EVSEL_t; - -/* Event action selection */ -typedef enum ADC_EVACT_enum -{ - ADC_EVACT_NONE_gc = (0x00<<0), /* No event action */ - ADC_EVACT_CH0_gc = (0x01<<0), /* First event triggers channel 0 */ - ADC_EVACT_CH01_gc = (0x02<<0), /* First two events trigger channel 0,1 */ - ADC_EVACT_CH012_gc = (0x03<<0), /* First three events trigger channel 0,1,2 */ - ADC_EVACT_CH0123_gc = (0x04<<0), /* Events trigger channel 0,1,2,3 */ - ADC_EVACT_SWEEP_gc = (0x05<<0), /* First event triggers sweep */ - ADC_EVACT_SYNCHSWEEP_gc = (0x06<<0), /* First event triggers synchronized sweep */ -} ADC_EVACT_t; - -/* Interupt mode */ -typedef enum ADC_CH_INTMODE_enum -{ - ADC_CH_INTMODE_COMPLETE_gc = (0x00<<2), /* Interrupt on conversion complete */ - ADC_CH_INTMODE_BELOW_gc = (0x01<<2), /* Interrupt on result below compare value */ - ADC_CH_INTMODE_ABOVE_gc = (0x03<<2), /* Interrupt on result above compare value */ -} ADC_CH_INTMODE_t; - -/* Interrupt level */ -typedef enum ADC_CH_INTLVL_enum -{ - ADC_CH_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ - ADC_CH_INTLVL_LO_gc = (0x01<<0), /* Low level */ - ADC_CH_INTLVL_MED_gc = (0x02<<0), /* Medium level */ - ADC_CH_INTLVL_HI_gc = (0x03<<0), /* High level */ -} ADC_CH_INTLVL_t; - -/* DMA request selection */ -typedef enum ADC_DMASEL_enum -{ - ADC_DMASEL_OFF_gc = (0x00<<6), /* Combined DMA request OFF */ - ADC_DMASEL_CH01_gc = (0x01<<6), /* ADC Channel 0 or 1 */ - ADC_DMASEL_CH012_gc = (0x02<<6), /* ADC Channel 0 or 1 or 2 */ - ADC_DMASEL_CH0123_gc = (0x03<<6), /* ADC Channel 0 or 1 or 2 or 3 */ -} ADC_DMASEL_t; - -/* Clock prescaler */ -typedef enum ADC_PRESCALER_enum -{ - ADC_PRESCALER_DIV4_gc = (0x00<<0), /* Divide clock by 4 */ - ADC_PRESCALER_DIV8_gc = (0x01<<0), /* Divide clock by 8 */ - ADC_PRESCALER_DIV16_gc = (0x02<<0), /* Divide clock by 16 */ - ADC_PRESCALER_DIV32_gc = (0x03<<0), /* Divide clock by 32 */ - ADC_PRESCALER_DIV64_gc = (0x04<<0), /* Divide clock by 64 */ - ADC_PRESCALER_DIV128_gc = (0x05<<0), /* Divide clock by 128 */ - ADC_PRESCALER_DIV256_gc = (0x06<<0), /* Divide clock by 256 */ - ADC_PRESCALER_DIV512_gc = (0x07<<0), /* Divide clock by 512 */ -} ADC_PRESCALER_t; - - -/* --------------------------------------------------------------------------- -DAC - Digital/Analog Converter --------------------------------------------------------------------------- -*/ - -/* Digital-to-Analog Converter */ -typedef struct DAC_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t CTRLC; /* Control Register C */ - register8_t EVCTRL; /* Event Input Control */ - register8_t TIMCTRL; /* Timing Control */ - register8_t STATUS; /* Status */ - register8_t reserved_0x06; - register8_t reserved_0x07; - register8_t GAINCAL; /* Gain Calibration */ - register8_t OFFSETCAL; /* Offset Calibration */ - register8_t reserved_0x0A; - register8_t reserved_0x0B; - register8_t reserved_0x0C; - register8_t reserved_0x0D; - register8_t reserved_0x0E; - register8_t reserved_0x0F; - register8_t reserved_0x10; - register8_t reserved_0x11; - register8_t reserved_0x12; - register8_t reserved_0x13; - register8_t reserved_0x14; - register8_t reserved_0x15; - register8_t reserved_0x16; - register8_t reserved_0x17; - _WORDREGISTER(CH0DATA); /* Channel 0 Data */ - _WORDREGISTER(CH1DATA); /* Channel 1 Data */ -} DAC_t; - -/* Output channel selection */ -typedef enum DAC_CHSEL_enum -{ - DAC_CHSEL_SINGLE_gc = (0x00<<5), /* Single channel operation (Channel A only) */ - DAC_CHSEL_DUAL_gc = (0x02<<5), /* Dual channel operation (S/H on both channels) */ -} DAC_CHSEL_t; - -/* Reference voltage selection */ -typedef enum DAC_REFSEL_enum -{ - DAC_REFSEL_INT1V_gc = (0x00<<3), /* Internal 1V */ - DAC_REFSEL_AVCC_gc = (0x01<<3), /* Analog supply voltage */ - DAC_REFSEL_AREFA_gc = (0x02<<3), /* External reference on AREF on PORTA */ - DAC_REFSEL_AREFB_gc = (0x03<<3), /* External reference on AREF on PORTB */ -} DAC_REFSEL_t; - -/* Event channel selection */ -typedef enum DAC_EVSEL_enum -{ - DAC_EVSEL_0_gc = (0x00<<0), /* Event Channel 0 */ - DAC_EVSEL_1_gc = (0x01<<0), /* Event Channel 1 */ - DAC_EVSEL_2_gc = (0x02<<0), /* Event Channel 2 */ - DAC_EVSEL_3_gc = (0x03<<0), /* Event Channel 3 */ - DAC_EVSEL_4_gc = (0x04<<0), /* Event Channel 4 */ - DAC_EVSEL_5_gc = (0x05<<0), /* Event Channel 5 */ - DAC_EVSEL_6_gc = (0x06<<0), /* Event Channel 6 */ - DAC_EVSEL_7_gc = (0x07<<0), /* Event Channel 7 */ -} DAC_EVSEL_t; - -/* Conversion interval */ -typedef enum DAC_CONINTVAL_enum -{ - DAC_CONINTVAL_1CLK_gc = (0x00<<4), /* 1 CLK / 2 CLK in S/H mode */ - DAC_CONINTVAL_2CLK_gc = (0x01<<4), /* 2 CLK / 3 CLK in S/H mode */ - DAC_CONINTVAL_4CLK_gc = (0x02<<4), /* 4 CLK / 6 CLK in S/H mode */ - DAC_CONINTVAL_8CLK_gc = (0x03<<4), /* 8 CLK / 12 CLK in S/H mode */ - DAC_CONINTVAL_16CLK_gc = (0x04<<4), /* 16 CLK / 24 CLK in S/H mode */ - DAC_CONINTVAL_32CLK_gc = (0x05<<4), /* 32 CLK / 48 CLK in S/H mode */ - DAC_CONINTVAL_64CLK_gc = (0x06<<4), /* 64 CLK / 96 CLK in S/H mode */ - DAC_CONINTVAL_128CLK_gc = (0x07<<4), /* 128 CLK / 192 CLK in S/H mode */ -} DAC_CONINTVAL_t; - -/* Refresh rate */ -typedef enum DAC_REFRESH_enum -{ - DAC_REFRESH_16CLK_gc = (0x00<<0), /* 16 CLK */ - DAC_REFRESH_32CLK_gc = (0x01<<0), /* 32 CLK */ - DAC_REFRESH_64CLK_gc = (0x02<<0), /* 64 CLK */ - DAC_REFRESH_128CLK_gc = (0x03<<0), /* 128 CLK */ - DAC_REFRESH_256CLK_gc = (0x04<<0), /* 256 CLK */ - DAC_REFRESH_512CLK_gc = (0x05<<0), /* 512 CLK */ - DAC_REFRESH_1024CLK_gc = (0x06<<0), /* 1024 CLK */ - DAC_REFRESH_2048CLK_gc = (0x07<<0), /* 2048 CLK */ - DAC_REFRESH_4096CLK_gc = (0x08<<0), /* 4096 CLK */ - DAC_REFRESH_8192CLK_gc = (0x09<<0), /* 8192 CLK */ - DAC_REFRESH_16384CLK_gc = (0x0A<<0), /* 16384 CLK */ - DAC_REFRESH_32768CLK_gc = (0x0B<<0), /* 32768 CLK */ - DAC_REFRESH_65536CLK_gc = (0x0C<<0), /* 65536 CLK */ - DAC_REFRESH_OFF_gc = (0x0F<<0), /* Auto refresh OFF */ -} DAC_REFRESH_t; - - -/* --------------------------------------------------------------------------- -RTC - Real-Time Clounter --------------------------------------------------------------------------- -*/ - -/* Real-Time Counter */ -typedef struct RTC_struct -{ - register8_t CTRL; /* Control Register */ - register8_t STATUS; /* Status Register */ - register8_t INTCTRL; /* Interrupt Control Register */ - register8_t INTFLAGS; /* Interrupt Flags */ - register8_t TEMP; /* Temporary register */ - register8_t reserved_0x05; - register8_t reserved_0x06; - register8_t reserved_0x07; - _WORDREGISTER(CNT); /* Count Register */ - _WORDREGISTER(PER); /* Period Register */ - _WORDREGISTER(COMP); /* Compare Register */ -} RTC_t; - -/* Prescaler Factor */ -typedef enum RTC_PRESCALER_enum -{ - RTC_PRESCALER_OFF_gc = (0x00<<0), /* RTC Off */ - RTC_PRESCALER_DIV1_gc = (0x01<<0), /* RTC Clock */ - RTC_PRESCALER_DIV2_gc = (0x02<<0), /* RTC Clock / 2 */ - RTC_PRESCALER_DIV8_gc = (0x03<<0), /* RTC Clock / 8 */ - RTC_PRESCALER_DIV16_gc = (0x04<<0), /* RTC Clock / 16 */ - RTC_PRESCALER_DIV64_gc = (0x05<<0), /* RTC Clock / 64 */ - RTC_PRESCALER_DIV256_gc = (0x06<<0), /* RTC Clock / 256 */ - RTC_PRESCALER_DIV1024_gc = (0x07<<0), /* RTC Clock / 1024 */ -} RTC_PRESCALER_t; - -/* Compare Interrupt level */ -typedef enum RTC_COMPINTLVL_enum -{ - RTC_COMPINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ - RTC_COMPINTLVL_LO_gc = (0x01<<2), /* Low Level */ - RTC_COMPINTLVL_MED_gc = (0x02<<2), /* Medium Level */ - RTC_COMPINTLVL_HI_gc = (0x03<<2), /* High Level */ -} RTC_COMPINTLVL_t; - -/* Overflow Interrupt level */ -typedef enum RTC_OVFINTLVL_enum -{ - RTC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - RTC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ - RTC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ - RTC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ -} RTC_OVFINTLVL_t; - - -/* --------------------------------------------------------------------------- -EBI - External Bus Interface --------------------------------------------------------------------------- -*/ - -/* EBI Chip Select Module */ -typedef struct EBI_CS_struct -{ - register8_t CTRLA; /* Chip Select Control Register A */ - register8_t CTRLB; /* Chip Select Control Register B */ - _WORDREGISTER(BASEADDR); /* Chip Select Base Address */ -} EBI_CS_t; - -/* --------------------------------------------------------------------------- -EBI - External Bus Interface --------------------------------------------------------------------------- -*/ - -/* External Bus Interface */ -typedef struct EBI_struct -{ - register8_t CTRL; /* Control */ - register8_t SDRAMCTRLA; /* SDRAM Control Register A */ - register8_t reserved_0x02; - register8_t reserved_0x03; - _WORDREGISTER(REFRESH); /* SDRAM Refresh Period */ - _WORDREGISTER(INITDLY); /* SDRAM Initialization Delay */ - register8_t SDRAMCTRLB; /* SDRAM Control Register B */ - register8_t SDRAMCTRLC; /* SDRAM Control Register C */ - register8_t reserved_0x0A; - register8_t reserved_0x0B; - register8_t reserved_0x0C; - register8_t reserved_0x0D; - register8_t reserved_0x0E; - register8_t reserved_0x0F; - EBI_CS_t CS0; /* Chip Select 0 */ - EBI_CS_t CS1; /* Chip Select 1 */ - EBI_CS_t CS2; /* Chip Select 2 */ - EBI_CS_t CS3; /* Chip Select 3 */ -} EBI_t; - -/* Chip Select adress space */ -typedef enum EBI_CS_ASIZE_enum -{ - EBI_CS_ASIZE_256B_gc = (0x00<<2), /* 256 bytes */ - EBI_CS_ASIZE_512B_gc = (0x01<<2), /* 512 bytes */ - EBI_CS_ASIZE_1KB_gc = (0x02<<2), /* 1K bytes */ - EBI_CS_ASIZE_2KB_gc = (0x03<<2), /* 2K bytes */ - EBI_CS_ASIZE_4KB_gc = (0x04<<2), /* 4K bytes */ - EBI_CS_ASIZE_8KB_gc = (0x05<<2), /* 8K bytes */ - EBI_CS_ASIZE_16KB_gc = (0x06<<2), /* 16K bytes */ - EBI_CS_ASIZE_32KB_gc = (0x07<<2), /* 32K bytes */ - EBI_CS_ASIZE_64KB_gc = (0x08<<2), /* 64K bytes */ - EBI_CS_ASIZE_128KB_gc = (0x09<<2), /* 128K bytes */ - EBI_CS_ASIZE_256KB_gc = (0x0A<<2), /* 256K bytes */ - EBI_CS_ASIZE_512KB_gc = (0x0B<<2), /* 512K bytes */ - EBI_CS_ASIZE_1MB_gc = (0x0C<<2), /* 1M bytes */ - EBI_CS_ASIZE_2MB_gc = (0x0D<<2), /* 2M bytes */ - EBI_CS_ASIZE_4MB_gc = (0x0E<<2), /* 4M bytes */ - EBI_CS_ASIZE_8MB_gc = (0x0F<<2), /* 8M bytes */ - EBI_CS_ASIZE_16M_gc = (0x10<<2), /* 16M bytes */ -} EBI_CS_ASIZE_t; - -/* */ -typedef enum EBI_CS_SRWS_enum -{ - EBI_CS_SRWS_0CLK_gc = (0x00<<0), /* 0 cycles */ - EBI_CS_SRWS_1CLK_gc = (0x01<<0), /* 1 cycle */ - EBI_CS_SRWS_2CLK_gc = (0x02<<0), /* 2 cycles */ - EBI_CS_SRWS_3CLK_gc = (0x03<<0), /* 3 cycles */ - EBI_CS_SRWS_4CLK_gc = (0x04<<0), /* 4 cycles */ - EBI_CS_SRWS_5CLK_gc = (0x05<<0), /* 5 cycle */ - EBI_CS_SRWS_6CLK_gc = (0x06<<0), /* 6 cycles */ - EBI_CS_SRWS_7CLK_gc = (0x07<<0), /* 7 cycles */ -} EBI_CS_SRWS_t; - -/* Chip Select address mode */ -typedef enum EBI_CS_MODE_enum -{ - EBI_CS_MODE_DISABLED_gc = (0x00<<0), /* Chip Select Disabled */ - EBI_CS_MODE_SRAM_gc = (0x01<<0), /* Chip Select in SRAM mode */ - EBI_CS_MODE_LPC_gc = (0x02<<0), /* Chip Select in SRAM LPC mode */ - EBI_CS_MODE_SDRAM_gc = (0x03<<0), /* Chip Select in SDRAM mode */ -} EBI_CS_MODE_t; - -/* Chip Select SDRAM mode */ -typedef enum EBI_CS_SDMODE_enum -{ - EBI_CS_SDMODE_NORMAL_gc = (0x00<<0), /* Normal mode */ - EBI_CS_SDMODE_LOAD_gc = (0x01<<0), /* Load Mode Register command mode */ -} EBI_CS_SDMODE_t; - -/* */ -typedef enum EBI_SDDATAW_enum -{ - EBI_SDDATAW_4BIT_gc = (0x00<<6), /* 4-bit data bus */ - EBI_SDDATAW_8BIT_gc = (0x01<<6), /* 8-bit data bus */ -} EBI_SDDATAW_t; - -/* */ -typedef enum EBI_LPCMODE_enum -{ - EBI_LPCMODE_ALE1_gc = (0x00<<4), /* Data muxed with addr byte 0 */ - EBI_LPCMODE_ALE12_gc = (0x02<<4), /* Data muxed with addr byte 0 and 1 */ -} EBI_LPCMODE_t; - -/* */ -typedef enum EBI_SRMODE_enum -{ - EBI_SRMODE_ALE1_gc = (0x00<<2), /* Addr byte 0 muxed with 1 */ - EBI_SRMODE_ALE2_gc = (0x01<<2), /* Addr byte 0 muxed with 2 */ - EBI_SRMODE_ALE12_gc = (0x02<<2), /* Addr byte 0 muxed with 1 and 2 */ - EBI_SRMODE_NOALE_gc = (0x03<<2), /* No addr muxing */ -} EBI_SRMODE_t; - -/* */ -typedef enum EBI_IFMODE_enum -{ - EBI_IFMODE_DISABLED_gc = (0x00<<0), /* EBI Disabled */ - EBI_IFMODE_3PORT_gc = (0x01<<0), /* 3-port mode */ - EBI_IFMODE_4PORT_gc = (0x02<<0), /* 4-port mode */ - EBI_IFMODE_2PORT_gc = (0x03<<0), /* 2-port mode */ -} EBI_IFMODE_t; - -/* */ -typedef enum EBI_SDCOL_enum -{ - EBI_SDCOL_8BIT_gc = (0x00<<0), /* 8 column bits */ - EBI_SDCOL_9BIT_gc = (0x01<<0), /* 9 column bits */ - EBI_SDCOL_10BIT_gc = (0x02<<0), /* 10 column bits */ - EBI_SDCOL_11BIT_gc = (0x03<<0), /* 11 column bits */ -} EBI_SDCOL_t; - -/* */ -typedef enum EBI_MRDLY_enum -{ - EBI_MRDLY_0CLK_gc = (0x00<<6), /* 0 cycles */ - EBI_MRDLY_1CLK_gc = (0x01<<6), /* 1 cycle */ - EBI_MRDLY_2CLK_gc = (0x02<<6), /* 2 cycles */ - EBI_MRDLY_3CLK_gc = (0x03<<6), /* 3 cycles */ -} EBI_MRDLY_t; - -/* */ -typedef enum EBI_ROWCYCDLY_enum -{ - EBI_ROWCYCDLY_0CLK_gc = (0x00<<3), /* 0 cycles */ - EBI_ROWCYCDLY_1CLK_gc = (0x01<<3), /* 1 cycle */ - EBI_ROWCYCDLY_2CLK_gc = (0x02<<3), /* 2 cycles */ - EBI_ROWCYCDLY_3CLK_gc = (0x03<<3), /* 3 cycles */ - EBI_ROWCYCDLY_4CLK_gc = (0x04<<3), /* 4 cycles */ - EBI_ROWCYCDLY_5CLK_gc = (0x05<<3), /* 5 cycle */ - EBI_ROWCYCDLY_6CLK_gc = (0x06<<3), /* 6 cycles */ - EBI_ROWCYCDLY_7CLK_gc = (0x07<<3), /* 7 cycles */ -} EBI_ROWCYCDLY_t; - -/* */ -typedef enum EBI_RPDLY_enum -{ - EBI_RPDLY_0CLK_gc = (0x00<<0), /* 0 cycles */ - EBI_RPDLY_1CLK_gc = (0x01<<0), /* 1 cycle */ - EBI_RPDLY_2CLK_gc = (0x02<<0), /* 2 cycles */ - EBI_RPDLY_3CLK_gc = (0x03<<0), /* 3 cycles */ - EBI_RPDLY_4CLK_gc = (0x04<<0), /* 4 cycles */ - EBI_RPDLY_5CLK_gc = (0x05<<0), /* 5 cycle */ - EBI_RPDLY_6CLK_gc = (0x06<<0), /* 6 cycles */ - EBI_RPDLY_7CLK_gc = (0x07<<0), /* 7 cycles */ -} EBI_RPDLY_t; - -/* */ -typedef enum EBI_WRDLY_enum -{ - EBI_WRDLY_0CLK_gc = (0x00<<6), /* 0 cycles */ - EBI_WRDLY_1CLK_gc = (0x01<<6), /* 1 cycle */ - EBI_WRDLY_2CLK_gc = (0x02<<6), /* 2 cycles */ - EBI_WRDLY_3CLK_gc = (0x03<<6), /* 3 cycles */ -} EBI_WRDLY_t; - -/* */ -typedef enum EBI_ESRDLY_enum -{ - EBI_ESRDLY_0CLK_gc = (0x00<<3), /* 0 cycles */ - EBI_ESRDLY_1CLK_gc = (0x01<<3), /* 1 cycle */ - EBI_ESRDLY_2CLK_gc = (0x02<<3), /* 2 cycles */ - EBI_ESRDLY_3CLK_gc = (0x03<<3), /* 3 cycles */ - EBI_ESRDLY_4CLK_gc = (0x04<<3), /* 4 cycles */ - EBI_ESRDLY_5CLK_gc = (0x05<<3), /* 5 cycle */ - EBI_ESRDLY_6CLK_gc = (0x06<<3), /* 6 cycles */ - EBI_ESRDLY_7CLK_gc = (0x07<<3), /* 7 cycles */ -} EBI_ESRDLY_t; - -/* */ -typedef enum EBI_ROWCOLDLY_enum -{ - EBI_ROWCOLDLY_0CLK_gc = (0x00<<0), /* 0 cycles */ - EBI_ROWCOLDLY_1CLK_gc = (0x01<<0), /* 1 cycle */ - EBI_ROWCOLDLY_2CLK_gc = (0x02<<0), /* 2 cycles */ - EBI_ROWCOLDLY_3CLK_gc = (0x03<<0), /* 3 cycles */ - EBI_ROWCOLDLY_4CLK_gc = (0x04<<0), /* 4 cycles */ - EBI_ROWCOLDLY_5CLK_gc = (0x05<<0), /* 5 cycle */ - EBI_ROWCOLDLY_6CLK_gc = (0x06<<0), /* 6 cycles */ - EBI_ROWCOLDLY_7CLK_gc = (0x07<<0), /* 7 cycles */ -} EBI_ROWCOLDLY_t; - - -/* --------------------------------------------------------------------------- -TWI - Two-Wire Interface --------------------------------------------------------------------------- -*/ - -/* */ -typedef struct TWI_MASTER_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t CTRLC; /* Control Register C */ - register8_t STATUS; /* Status Register */ - register8_t BAUD; /* Baurd Rate Control Register */ - register8_t ADDR; /* Address Register */ - register8_t DATA; /* Data Register */ -} TWI_MASTER_t; - -/* --------------------------------------------------------------------------- -TWI - Two-Wire Interface --------------------------------------------------------------------------- -*/ - -/* */ -typedef struct TWI_SLAVE_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t STATUS; /* Status Register */ - register8_t ADDR; /* Address Register */ - register8_t DATA; /* Data Register */ - register8_t ADDRMASK; /* Address Mask Register */ -} TWI_SLAVE_t; - -/* --------------------------------------------------------------------------- -TWI - Two-Wire Interface --------------------------------------------------------------------------- -*/ - -/* Two-Wire Interface */ -typedef struct TWI_struct -{ - register8_t CTRL; /* TWI Common Control Register */ - TWI_MASTER_t MASTER; /* TWI master module */ - TWI_SLAVE_t SLAVE; /* TWI slave module */ -} TWI_t; - -/* Master Interrupt Level */ -typedef enum TWI_MASTER_INTLVL_enum -{ - TWI_MASTER_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ - TWI_MASTER_INTLVL_LO_gc = (0x01<<6), /* Low Level */ - TWI_MASTER_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ - TWI_MASTER_INTLVL_HI_gc = (0x03<<6), /* High Level */ -} TWI_MASTER_INTLVL_t; - -/* Inactive Timeout */ -typedef enum TWI_MASTER_TIMEOUT_enum -{ - TWI_MASTER_TIMEOUT_DISABLED_gc = (0x00<<2), /* Bus Timeout Disabled */ - TWI_MASTER_TIMEOUT_50US_gc = (0x01<<2), /* 50 Microseconds */ - TWI_MASTER_TIMEOUT_100US_gc = (0x02<<2), /* 100 Microseconds */ - TWI_MASTER_TIMEOUT_200US_gc = (0x03<<2), /* 200 Microseconds */ -} TWI_MASTER_TIMEOUT_t; - -/* Master Command */ -typedef enum TWI_MASTER_CMD_enum -{ - TWI_MASTER_CMD_NOACT_gc = (0x00<<0), /* No Action */ - TWI_MASTER_CMD_REPSTART_gc = (0x01<<0), /* Issue Repeated Start Condition */ - TWI_MASTER_CMD_RECVTRANS_gc = (0x02<<0), /* Receive or Transmit Data */ - TWI_MASTER_CMD_STOP_gc = (0x03<<0), /* Issue Stop Condition */ -} TWI_MASTER_CMD_t; - -/* Master Bus State */ -typedef enum TWI_MASTER_BUSSTATE_enum -{ - TWI_MASTER_BUSSTATE_UNKNOWN_gc = (0x00<<0), /* Unknown Bus State */ - TWI_MASTER_BUSSTATE_IDLE_gc = (0x01<<0), /* Bus is Idle */ - TWI_MASTER_BUSSTATE_OWNER_gc = (0x02<<0), /* This Module Controls The Bus */ - TWI_MASTER_BUSSTATE_BUSY_gc = (0x03<<0), /* The Bus is Busy */ -} TWI_MASTER_BUSSTATE_t; - -/* Slave Interrupt Level */ -typedef enum TWI_SLAVE_INTLVL_enum -{ - TWI_SLAVE_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ - TWI_SLAVE_INTLVL_LO_gc = (0x01<<6), /* Low Level */ - TWI_SLAVE_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ - TWI_SLAVE_INTLVL_HI_gc = (0x03<<6), /* High Level */ -} TWI_SLAVE_INTLVL_t; - -/* Slave Command */ -typedef enum TWI_SLAVE_CMD_enum -{ - TWI_SLAVE_CMD_NOACT_gc = (0x00<<0), /* No Action */ - TWI_SLAVE_CMD_COMPTRANS_gc = (0x02<<0), /* Used To Complete a Transaction */ - TWI_SLAVE_CMD_RESPONSE_gc = (0x03<<0), /* Used in Response to Address/Data Interrupt */ -} TWI_SLAVE_CMD_t; - - -/* --------------------------------------------------------------------------- -PORT - Port Configuration --------------------------------------------------------------------------- -*/ - -/* I/O port Configuration */ -typedef struct PORTCFG_struct -{ - register8_t MPCMASK; /* Multi-pin Configuration Mask */ - register8_t reserved_0x01; - register8_t VPCTRLA; /* Virtual Port Control Register A */ - register8_t VPCTRLB; /* Virtual Port Control Register B */ - register8_t CLKEVOUT; /* Clock and Event Out Register */ -} PORTCFG_t; - -/* --------------------------------------------------------------------------- -PORT - Port Configuration --------------------------------------------------------------------------- -*/ - -/* Virtual Port */ -typedef struct VPORT_struct -{ - register8_t DIR; /* I/O Port Data Direction */ - register8_t OUT; /* I/O Port Output */ - register8_t IN; /* I/O Port Input */ - register8_t INTFLAGS; /* Interrupt Flag Register */ -} VPORT_t; - -/* --------------------------------------------------------------------------- -PORT - Port Configuration --------------------------------------------------------------------------- -*/ - -/* I/O Ports */ -typedef struct PORT_struct -{ - register8_t DIR; /* I/O Port Data Direction */ - register8_t DIRSET; /* I/O Port Data Direction Set */ - register8_t DIRCLR; /* I/O Port Data Direction Clear */ - register8_t DIRTGL; /* I/O Port Data Direction Toggle */ - register8_t OUT; /* I/O Port Output */ - register8_t OUTSET; /* I/O Port Output Set */ - register8_t OUTCLR; /* I/O Port Output Clear */ - register8_t OUTTGL; /* I/O Port Output Toggle */ - register8_t IN; /* I/O port Input */ - register8_t INTCTRL; /* Interrupt Control Register */ - register8_t INT0MASK; /* Port Interrupt 0 Mask */ - register8_t INT1MASK; /* Port Interrupt 1 Mask */ - register8_t INTFLAGS; /* Interrupt Flag Register */ - register8_t reserved_0x0D; - register8_t reserved_0x0E; - register8_t reserved_0x0F; - register8_t PIN0CTRL; /* Pin 0 Control Register */ - register8_t PIN1CTRL; /* Pin 1 Control Register */ - register8_t PIN2CTRL; /* Pin 2 Control Register */ - register8_t PIN3CTRL; /* Pin 3 Control Register */ - register8_t PIN4CTRL; /* Pin 4 Control Register */ - register8_t PIN5CTRL; /* Pin 5 Control Register */ - register8_t PIN6CTRL; /* Pin 6 Control Register */ - register8_t PIN7CTRL; /* Pin 7 Control Register */ -} PORT_t; - -/* Virtual Port 0 Mapping */ -typedef enum PORTCFG_VP0MAP_enum -{ - PORTCFG_VP0MAP_PORTA_gc = (0x00<<0), /* Mapped To PORTA */ - PORTCFG_VP0MAP_PORTB_gc = (0x01<<0), /* Mapped To PORTB */ - PORTCFG_VP0MAP_PORTC_gc = (0x02<<0), /* Mapped To PORTC */ - PORTCFG_VP0MAP_PORTD_gc = (0x03<<0), /* Mapped To PORTD */ - PORTCFG_VP0MAP_PORTE_gc = (0x04<<0), /* Mapped To PORTE */ - PORTCFG_VP0MAP_PORTF_gc = (0x05<<0), /* Mapped To PORTF */ - PORTCFG_VP0MAP_PORTG_gc = (0x06<<0), /* Mapped To PORTG */ - PORTCFG_VP0MAP_PORTH_gc = (0x07<<0), /* Mapped To PORTH */ - PORTCFG_VP0MAP_PORTJ_gc = (0x08<<0), /* Mapped To PORTJ */ - PORTCFG_VP0MAP_PORTK_gc = (0x09<<0), /* Mapped To PORTK */ - PORTCFG_VP0MAP_PORTL_gc = (0x0A<<0), /* Mapped To PORTL */ - PORTCFG_VP0MAP_PORTM_gc = (0x0B<<0), /* Mapped To PORTM */ - PORTCFG_VP0MAP_PORTN_gc = (0x0C<<0), /* Mapped To PORTN */ - PORTCFG_VP0MAP_PORTP_gc = (0x0D<<0), /* Mapped To PORTP */ - PORTCFG_VP0MAP_PORTQ_gc = (0x0E<<0), /* Mapped To PORTQ */ - PORTCFG_VP0MAP_PORTR_gc = (0x0F<<0), /* Mapped To PORTR */ -} PORTCFG_VP0MAP_t; - -/* Virtual Port 1 Mapping */ -typedef enum PORTCFG_VP1MAP_enum -{ - PORTCFG_VP1MAP_PORTA_gc = (0x00<<4), /* Mapped To PORTA */ - PORTCFG_VP1MAP_PORTB_gc = (0x01<<4), /* Mapped To PORTB */ - PORTCFG_VP1MAP_PORTC_gc = (0x02<<4), /* Mapped To PORTC */ - PORTCFG_VP1MAP_PORTD_gc = (0x03<<4), /* Mapped To PORTD */ - PORTCFG_VP1MAP_PORTE_gc = (0x04<<4), /* Mapped To PORTE */ - PORTCFG_VP1MAP_PORTF_gc = (0x05<<4), /* Mapped To PORTF */ - PORTCFG_VP1MAP_PORTG_gc = (0x06<<4), /* Mapped To PORTG */ - PORTCFG_VP1MAP_PORTH_gc = (0x07<<4), /* Mapped To PORTH */ - PORTCFG_VP1MAP_PORTJ_gc = (0x08<<4), /* Mapped To PORTJ */ - PORTCFG_VP1MAP_PORTK_gc = (0x09<<4), /* Mapped To PORTK */ - PORTCFG_VP1MAP_PORTL_gc = (0x0A<<4), /* Mapped To PORTL */ - PORTCFG_VP1MAP_PORTM_gc = (0x0B<<4), /* Mapped To PORTM */ - PORTCFG_VP1MAP_PORTN_gc = (0x0C<<4), /* Mapped To PORTN */ - PORTCFG_VP1MAP_PORTP_gc = (0x0D<<4), /* Mapped To PORTP */ - PORTCFG_VP1MAP_PORTQ_gc = (0x0E<<4), /* Mapped To PORTQ */ - PORTCFG_VP1MAP_PORTR_gc = (0x0F<<4), /* Mapped To PORTR */ -} PORTCFG_VP1MAP_t; - -/* Virtual Port 2 Mapping */ -typedef enum PORTCFG_VP2MAP_enum -{ - PORTCFG_VP2MAP_PORTA_gc = (0x00<<0), /* Mapped To PORTA */ - PORTCFG_VP2MAP_PORTB_gc = (0x01<<0), /* Mapped To PORTB */ - PORTCFG_VP2MAP_PORTC_gc = (0x02<<0), /* Mapped To PORTC */ - PORTCFG_VP2MAP_PORTD_gc = (0x03<<0), /* Mapped To PORTD */ - PORTCFG_VP2MAP_PORTE_gc = (0x04<<0), /* Mapped To PORTE */ - PORTCFG_VP2MAP_PORTF_gc = (0x05<<0), /* Mapped To PORTF */ - PORTCFG_VP2MAP_PORTG_gc = (0x06<<0), /* Mapped To PORTG */ - PORTCFG_VP2MAP_PORTH_gc = (0x07<<0), /* Mapped To PORTH */ - PORTCFG_VP2MAP_PORTJ_gc = (0x08<<0), /* Mapped To PORTJ */ - PORTCFG_VP2MAP_PORTK_gc = (0x09<<0), /* Mapped To PORTK */ - PORTCFG_VP2MAP_PORTL_gc = (0x0A<<0), /* Mapped To PORTL */ - PORTCFG_VP2MAP_PORTM_gc = (0x0B<<0), /* Mapped To PORTM */ - PORTCFG_VP2MAP_PORTN_gc = (0x0C<<0), /* Mapped To PORTN */ - PORTCFG_VP2MAP_PORTP_gc = (0x0D<<0), /* Mapped To PORTP */ - PORTCFG_VP2MAP_PORTQ_gc = (0x0E<<0), /* Mapped To PORTQ */ - PORTCFG_VP2MAP_PORTR_gc = (0x0F<<0), /* Mapped To PORTR */ -} PORTCFG_VP2MAP_t; - -/* Virtual Port 3 Mapping */ -typedef enum PORTCFG_VP3MAP_enum -{ - PORTCFG_VP3MAP_PORTA_gc = (0x00<<4), /* Mapped To PORTA */ - PORTCFG_VP3MAP_PORTB_gc = (0x01<<4), /* Mapped To PORTB */ - PORTCFG_VP3MAP_PORTC_gc = (0x02<<4), /* Mapped To PORTC */ - PORTCFG_VP3MAP_PORTD_gc = (0x03<<4), /* Mapped To PORTD */ - PORTCFG_VP3MAP_PORTE_gc = (0x04<<4), /* Mapped To PORTE */ - PORTCFG_VP3MAP_PORTF_gc = (0x05<<4), /* Mapped To PORTF */ - PORTCFG_VP3MAP_PORTG_gc = (0x06<<4), /* Mapped To PORTG */ - PORTCFG_VP3MAP_PORTH_gc = (0x07<<4), /* Mapped To PORTH */ - PORTCFG_VP3MAP_PORTJ_gc = (0x08<<4), /* Mapped To PORTJ */ - PORTCFG_VP3MAP_PORTK_gc = (0x09<<4), /* Mapped To PORTK */ - PORTCFG_VP3MAP_PORTL_gc = (0x0A<<4), /* Mapped To PORTL */ - PORTCFG_VP3MAP_PORTM_gc = (0x0B<<4), /* Mapped To PORTM */ - PORTCFG_VP3MAP_PORTN_gc = (0x0C<<4), /* Mapped To PORTN */ - PORTCFG_VP3MAP_PORTP_gc = (0x0D<<4), /* Mapped To PORTP */ - PORTCFG_VP3MAP_PORTQ_gc = (0x0E<<4), /* Mapped To PORTQ */ - PORTCFG_VP3MAP_PORTR_gc = (0x0F<<4), /* Mapped To PORTR */ -} PORTCFG_VP3MAP_t; - -/* Clock Output Port */ -typedef enum PORTCFG_CLKOUT_enum -{ - PORTCFG_CLKOUT_OFF_gc = (0x00<<0), /* Clock Output Disabled */ - PORTCFG_CLKOUT_PC7_gc = (0x01<<0), /* Clock Output on Port C pin 7 */ - PORTCFG_CLKOUT_PD7_gc = (0x02<<0), /* Clock Output on Port D pin 7 */ - PORTCFG_CLKOUT_PE7_gc = (0x03<<0), /* Clock Output on Port E pin 7 */ -} PORTCFG_CLKOUT_t; - -/* Event Output Port */ -typedef enum PORTCFG_EVOUT_enum -{ - PORTCFG_EVOUT_OFF_gc = (0x00<<4), /* Event Output Disabled */ - PORTCFG_EVOUT_PC7_gc = (0x01<<4), /* Event Channel 7 Output on Port C pin 7 */ - PORTCFG_EVOUT_PD7_gc = (0x02<<4), /* Event Channel 7 Output on Port D pin 7 */ - PORTCFG_EVOUT_PE7_gc = (0x03<<4), /* Event Channel 7 Output on Port E pin 7 */ -} PORTCFG_EVOUT_t; - -/* Port Interrupt 0 Level */ -typedef enum PORT_INT0LVL_enum -{ - PORT_INT0LVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - PORT_INT0LVL_LO_gc = (0x01<<0), /* Low Level */ - PORT_INT0LVL_MED_gc = (0x02<<0), /* Medium Level */ - PORT_INT0LVL_HI_gc = (0x03<<0), /* High Level */ -} PORT_INT0LVL_t; - -/* Port Interrupt 1 Level */ -typedef enum PORT_INT1LVL_enum -{ - PORT_INT1LVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ - PORT_INT1LVL_LO_gc = (0x01<<2), /* Low Level */ - PORT_INT1LVL_MED_gc = (0x02<<2), /* Medium Level */ - PORT_INT1LVL_HI_gc = (0x03<<2), /* High Level */ -} PORT_INT1LVL_t; - -/* Output/Pull Configuration */ -typedef enum PORT_OPC_enum -{ - PORT_OPC_TOTEM_gc = (0x00<<3), /* Totempole */ - PORT_OPC_BUSKEEPER_gc = (0x01<<3), /* Totempole w/ Bus keeper on Input and Output */ - PORT_OPC_PULLDOWN_gc = (0x02<<3), /* Totempole w/ Pull-down on Input */ - PORT_OPC_PULLUP_gc = (0x03<<3), /* Totempole w/ Pull-up on Input */ - PORT_OPC_WIREDOR_gc = (0x04<<3), /* Wired OR */ - PORT_OPC_WIREDAND_gc = (0x05<<3), /* Wired AND */ - PORT_OPC_WIREDORPULL_gc = (0x06<<3), /* Wired OR w/ Pull-down */ - PORT_OPC_WIREDANDPULL_gc = (0x07<<3), /* Wired AND w/ Pull-up */ -} PORT_OPC_t; - -/* Input/Sense Configuration */ -typedef enum PORT_ISC_enum -{ - PORT_ISC_BOTHEDGES_gc = (0x00<<0), /* Sense Both Edges */ - PORT_ISC_RISING_gc = (0x01<<0), /* Sense Rising Edge */ - PORT_ISC_FALLING_gc = (0x02<<0), /* Sense Falling Edge */ - PORT_ISC_LEVEL_gc = (0x03<<0), /* Sense Level (Transparent For Events) */ - PORT_ISC_INPUT_DISABLE_gc = (0x07<<0), /* Disable Digital Input Buffer */ -} PORT_ISC_t; - - -/* --------------------------------------------------------------------------- -TC - 16-bit Timer/Counter With PWM --------------------------------------------------------------------------- -*/ - -/* 16-bit Timer/Counter 0 */ -typedef struct TC0_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t CTRLC; /* Control register C */ - register8_t CTRLD; /* Control Register D */ - register8_t CTRLE; /* Control Register E */ - register8_t reserved_0x05; - register8_t INTCTRLA; /* Interrupt Control Register A */ - register8_t INTCTRLB; /* Interrupt Control Register B */ - register8_t CTRLFCLR; /* Control Register F Clear */ - register8_t CTRLFSET; /* Control Register F Set */ - register8_t CTRLGCLR; /* Control Register G Clear */ - register8_t CTRLGSET; /* Control Register G Set */ - register8_t INTFLAGS; /* Interrupt Flag Register */ - register8_t reserved_0x0D; - register8_t reserved_0x0E; - register8_t TEMP; /* Temporary Register For 16-bit Access */ - register8_t reserved_0x10; - register8_t reserved_0x11; - register8_t reserved_0x12; - register8_t reserved_0x13; - register8_t reserved_0x14; - register8_t reserved_0x15; - register8_t reserved_0x16; - register8_t reserved_0x17; - register8_t reserved_0x18; - register8_t reserved_0x19; - register8_t reserved_0x1A; - register8_t reserved_0x1B; - register8_t reserved_0x1C; - register8_t reserved_0x1D; - register8_t reserved_0x1E; - register8_t reserved_0x1F; - _WORDREGISTER(CNT); /* Count */ - register8_t reserved_0x22; - register8_t reserved_0x23; - register8_t reserved_0x24; - register8_t reserved_0x25; - _WORDREGISTER(PER); /* Period */ - _WORDREGISTER(CCA); /* Compare or Capture A */ - _WORDREGISTER(CCB); /* Compare or Capture B */ - _WORDREGISTER(CCC); /* Compare or Capture C */ - _WORDREGISTER(CCD); /* Compare or Capture D */ - register8_t reserved_0x30; - register8_t reserved_0x31; - register8_t reserved_0x32; - register8_t reserved_0x33; - register8_t reserved_0x34; - register8_t reserved_0x35; - _WORDREGISTER(PERBUF); /* Period Buffer */ - _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ - _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ - _WORDREGISTER(CCCBUF); /* Compare Or Capture C Buffer */ - _WORDREGISTER(CCDBUF); /* Compare Or Capture D Buffer */ -} TC0_t; - -/* --------------------------------------------------------------------------- -TC - 16-bit Timer/Counter With PWM --------------------------------------------------------------------------- -*/ - -/* 16-bit Timer/Counter 1 */ -typedef struct TC1_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t CTRLC; /* Control register C */ - register8_t CTRLD; /* Control Register D */ - register8_t CTRLE; /* Control Register E */ - register8_t reserved_0x05; - register8_t INTCTRLA; /* Interrupt Control Register A */ - register8_t INTCTRLB; /* Interrupt Control Register B */ - register8_t CTRLFCLR; /* Control Register F Clear */ - register8_t CTRLFSET; /* Control Register F Set */ - register8_t CTRLGCLR; /* Control Register G Clear */ - register8_t CTRLGSET; /* Control Register G Set */ - register8_t INTFLAGS; /* Interrupt Flag Register */ - register8_t reserved_0x0D; - register8_t reserved_0x0E; - register8_t TEMP; /* Temporary Register For 16-bit Access */ - register8_t reserved_0x10; - register8_t reserved_0x11; - register8_t reserved_0x12; - register8_t reserved_0x13; - register8_t reserved_0x14; - register8_t reserved_0x15; - register8_t reserved_0x16; - register8_t reserved_0x17; - register8_t reserved_0x18; - register8_t reserved_0x19; - register8_t reserved_0x1A; - register8_t reserved_0x1B; - register8_t reserved_0x1C; - register8_t reserved_0x1D; - register8_t reserved_0x1E; - register8_t reserved_0x1F; - _WORDREGISTER(CNT); /* Count */ - register8_t reserved_0x22; - register8_t reserved_0x23; - register8_t reserved_0x24; - register8_t reserved_0x25; - _WORDREGISTER(PER); /* Period */ - _WORDREGISTER(CCA); /* Compare or Capture A */ - _WORDREGISTER(CCB); /* Compare or Capture B */ - register8_t reserved_0x2C; - register8_t reserved_0x2D; - register8_t reserved_0x2E; - register8_t reserved_0x2F; - register8_t reserved_0x30; - register8_t reserved_0x31; - register8_t reserved_0x32; - register8_t reserved_0x33; - register8_t reserved_0x34; - register8_t reserved_0x35; - _WORDREGISTER(PERBUF); /* Period Buffer */ - _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ - _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ -} TC1_t; - -/* --------------------------------------------------------------------------- -TC - 16-bit Timer/Counter With PWM --------------------------------------------------------------------------- -*/ - -/* Advanced Waveform Extension */ -typedef struct AWEX_struct -{ - register8_t CTRL; /* Control Register */ - register8_t reserved_0x01; - register8_t FDEMASK; /* Fault Detection Event Mask */ - register8_t FDCTRL; /* Fault Detection Control Register */ - register8_t STATUS; /* Status Register */ - register8_t reserved_0x05; - register8_t DTBOTH; /* Dead Time Both Sides */ - register8_t DTBOTHBUF; /* Dead Time Both Sides Buffer */ - register8_t DTLS; /* Dead Time Low Side */ - register8_t DTHS; /* Dead Time High Side */ - register8_t DTLSBUF; /* Dead Time Low Side Buffer */ - register8_t DTHSBUF; /* Dead Time High Side Buffer */ - register8_t OUTOVEN; /* Output Override Enable */ -} AWEX_t; - -/* --------------------------------------------------------------------------- -TC - 16-bit Timer/Counter With PWM --------------------------------------------------------------------------- -*/ - -/* High-Resolution Extension */ -typedef struct HIRES_struct -{ - register8_t CTRLA; /* Control Register */ -} HIRES_t; - -/* Clock Selection */ -typedef enum TC_CLKSEL_enum -{ - TC_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */ - TC_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */ - TC_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */ - TC_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */ - TC_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */ - TC_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */ - TC_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */ - TC_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */ - TC_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */ - TC_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */ - TC_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */ - TC_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */ - TC_CLKSEL_EVCH4_gc = (0x0C<<0), /* Event Channel 4 */ - TC_CLKSEL_EVCH5_gc = (0x0D<<0), /* Event Channel 5 */ - TC_CLKSEL_EVCH6_gc = (0x0E<<0), /* Event Channel 6 */ - TC_CLKSEL_EVCH7_gc = (0x0F<<0), /* Event Channel 7 */ -} TC_CLKSEL_t; - -/* Waveform Generation Mode */ -typedef enum TC_WGMODE_enum -{ - TC_WGMODE_NORMAL_gc = (0x00<<0), /* Normal Mode */ - TC_WGMODE_FRQ_gc = (0x01<<0), /* Frequency Generation Mode */ - TC_WGMODE_SS_gc = (0x03<<0), /* Single Slope */ - TC_WGMODE_DS_T_gc = (0x05<<0), /* Dual Slope, Update on TOP */ - TC_WGMODE_DS_TB_gc = (0x06<<0), /* Dual Slope, Update on TOP and BOTTOM */ - TC_WGMODE_DS_B_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */ -} TC_WGMODE_t; - -/* Event Action */ -typedef enum TC_EVACT_enum -{ - TC_EVACT_OFF_gc = (0x00<<5), /* No Event Action */ - TC_EVACT_CAPT_gc = (0x01<<5), /* Input Capture */ - TC_EVACT_UPDOWN_gc = (0x02<<5), /* Externally Controlled Up/Down Count */ - TC_EVACT_QDEC_gc = (0x03<<5), /* Quadrature Decode */ - TC_EVACT_RESTART_gc = (0x04<<5), /* Restart */ - TC_EVACT_FRQ_gc = (0x05<<5), /* Frequency Capture */ - TC_EVACT_FRW_gc = (0x05<<5), /* Frequency Capture (typo in earlier header file) */ - TC_EVACT_PW_gc = (0x06<<5), /* Pulse-width Capture */ -} TC_EVACT_t; - -/* Event Selection */ -typedef enum TC_EVSEL_enum -{ - TC_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ - TC_EVSEL_CH0_gc = (0x08<<0), /* Event Channel 0 */ - TC_EVSEL_CH1_gc = (0x09<<0), /* Event Channel 1 */ - TC_EVSEL_CH2_gc = (0x0A<<0), /* Event Channel 2 */ - TC_EVSEL_CH3_gc = (0x0B<<0), /* Event Channel 3 */ - TC_EVSEL_CH4_gc = (0x0C<<0), /* Event Channel 4 */ - TC_EVSEL_CH5_gc = (0x0D<<0), /* Event Channel 5 */ - TC_EVSEL_CH6_gc = (0x0E<<0), /* Event Channel 6 */ - TC_EVSEL_CH7_gc = (0x0F<<0), /* Event Channel 7 */ -} TC_EVSEL_t; - -/* Error Interrupt Level */ -typedef enum TC_ERRINTLVL_enum -{ - TC_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ - TC_ERRINTLVL_LO_gc = (0x01<<2), /* Low Level */ - TC_ERRINTLVL_MED_gc = (0x02<<2), /* Medium Level */ - TC_ERRINTLVL_HI_gc = (0x03<<2), /* High Level */ -} TC_ERRINTLVL_t; - -/* Overflow Interrupt Level */ -typedef enum TC_OVFINTLVL_enum -{ - TC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - TC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ - TC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ - TC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ -} TC_OVFINTLVL_t; - -/* Compare or Capture D Interrupt Level */ -typedef enum TC_CCDINTLVL_enum -{ - TC_CCDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ - TC_CCDINTLVL_LO_gc = (0x01<<6), /* Low Level */ - TC_CCDINTLVL_MED_gc = (0x02<<6), /* Medium Level */ - TC_CCDINTLVL_HI_gc = (0x03<<6), /* High Level */ -} TC_CCDINTLVL_t; - -/* Compare or Capture C Interrupt Level */ -typedef enum TC_CCCINTLVL_enum -{ - TC_CCCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ - TC_CCCINTLVL_LO_gc = (0x01<<4), /* Low Level */ - TC_CCCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ - TC_CCCINTLVL_HI_gc = (0x03<<4), /* High Level */ -} TC_CCCINTLVL_t; - -/* Compare or Capture B Interrupt Level */ -typedef enum TC_CCBINTLVL_enum -{ - TC_CCBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ - TC_CCBINTLVL_LO_gc = (0x01<<2), /* Low Level */ - TC_CCBINTLVL_MED_gc = (0x02<<2), /* Medium Level */ - TC_CCBINTLVL_HI_gc = (0x03<<2), /* High Level */ -} TC_CCBINTLVL_t; - -/* Compare or Capture A Interrupt Level */ -typedef enum TC_CCAINTLVL_enum -{ - TC_CCAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - TC_CCAINTLVL_LO_gc = (0x01<<0), /* Low Level */ - TC_CCAINTLVL_MED_gc = (0x02<<0), /* Medium Level */ - TC_CCAINTLVL_HI_gc = (0x03<<0), /* High Level */ -} TC_CCAINTLVL_t; - -/* Timer/Counter Command */ -typedef enum TC_CMD_enum -{ - TC_CMD_NONE_gc = (0x00<<2), /* No Command */ - TC_CMD_UPDATE_gc = (0x01<<2), /* Force Update */ - TC_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ - TC_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ -} TC_CMD_t; - -/* Fault Detect Action */ -typedef enum AWEX_FDACT_enum -{ - AWEX_FDACT_NONE_gc = (0x00<<0), /* No Fault Protection */ - AWEX_FDACT_CLEAROE_gc = (0x01<<0), /* Clear Output Enable Bits */ - AWEX_FDACT_CLEARDIR_gc = (0x03<<0), /* Clear I/O Port Direction Bits */ -} AWEX_FDACT_t; - -/* High Resolution Enable */ -typedef enum HIRES_HREN_enum -{ - HIRES_HREN_NONE_gc = (0x00<<0), /* No Fault Protection */ - HIRES_HREN_TC0_gc = (0x01<<0), /* Enable High Resolution on Timer/Counter 0 */ - HIRES_HREN_TC1_gc = (0x02<<0), /* Enable High Resolution on Timer/Counter 1 */ - HIRES_HREN_BOTH_gc = (0x03<<0), /* Enable High Resolution both Timer/Counters */ -} HIRES_HREN_t; - - -/* --------------------------------------------------------------------------- -USART - Universal Asynchronous Receiver-Transmitter --------------------------------------------------------------------------- -*/ - -/* Universal Synchronous/Asynchronous Receiver/Transmitter */ -typedef struct USART_struct -{ - register8_t DATA; /* Data Register */ - register8_t STATUS; /* Status Register */ - register8_t reserved_0x02; - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t CTRLC; /* Control Register C */ - register8_t BAUDCTRLA; /* Baud Rate Control Register A */ - register8_t BAUDCTRLB; /* Baud Rate Control Register B */ -} USART_t; - -/* Receive Complete Interrupt level */ -typedef enum USART_RXCINTLVL_enum -{ - USART_RXCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ - USART_RXCINTLVL_LO_gc = (0x01<<4), /* Low Level */ - USART_RXCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ - USART_RXCINTLVL_HI_gc = (0x03<<4), /* High Level */ -} USART_RXCINTLVL_t; - -/* Transmit Complete Interrupt level */ -typedef enum USART_TXCINTLVL_enum -{ - USART_TXCINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ - USART_TXCINTLVL_LO_gc = (0x01<<2), /* Low Level */ - USART_TXCINTLVL_MED_gc = (0x02<<2), /* Medium Level */ - USART_TXCINTLVL_HI_gc = (0x03<<2), /* High Level */ -} USART_TXCINTLVL_t; - -/* Data Register Empty Interrupt level */ -typedef enum USART_DREINTLVL_enum -{ - USART_DREINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - USART_DREINTLVL_LO_gc = (0x01<<0), /* Low Level */ - USART_DREINTLVL_MED_gc = (0x02<<0), /* Medium Level */ - USART_DREINTLVL_HI_gc = (0x03<<0), /* High Level */ -} USART_DREINTLVL_t; - -/* Character Size */ -typedef enum USART_CHSIZE_enum -{ - USART_CHSIZE_5BIT_gc = (0x00<<0), /* Character size: 5 bit */ - USART_CHSIZE_6BIT_gc = (0x01<<0), /* Character size: 6 bit */ - USART_CHSIZE_7BIT_gc = (0x02<<0), /* Character size: 7 bit */ - USART_CHSIZE_8BIT_gc = (0x03<<0), /* Character size: 8 bit */ - USART_CHSIZE_9BIT_gc = (0x07<<0), /* Character size: 9 bit */ -} USART_CHSIZE_t; - -/* Communication Mode */ -typedef enum USART_CMODE_enum -{ - USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6), /* Asynchronous Mode */ - USART_CMODE_SYNCHRONOUS_gc = (0x01<<6), /* Synchronous Mode */ - USART_CMODE_IRDA_gc = (0x02<<6), /* IrDA Mode */ - USART_CMODE_MSPI_gc = (0x03<<6), /* Master SPI Mode */ -} USART_CMODE_t; - -/* Parity Mode */ -typedef enum USART_PMODE_enum -{ - USART_PMODE_DISABLED_gc = (0x00<<4), /* No Parity */ - USART_PMODE_EVEN_gc = (0x02<<4), /* Even Parity */ - USART_PMODE_ODD_gc = (0x03<<4), /* Odd Parity */ -} USART_PMODE_t; - - -/* --------------------------------------------------------------------------- -SPI - Serial Peripheral Interface --------------------------------------------------------------------------- -*/ - -/* Serial Peripheral Interface */ -typedef struct SPI_struct -{ - register8_t CTRL; /* Control Register */ - register8_t INTCTRL; /* Interrupt Control Register */ - register8_t STATUS; /* Status Register */ - register8_t DATA; /* Data Register */ -} SPI_t; - -/* SPI Mode */ -typedef enum SPI_MODE_enum -{ - SPI_MODE_0_gc = (0x00<<2), /* SPI Mode 0 */ - SPI_MODE_1_gc = (0x01<<2), /* SPI Mode 1 */ - SPI_MODE_2_gc = (0x02<<2), /* SPI Mode 2 */ - SPI_MODE_3_gc = (0x03<<2), /* SPI Mode 3 */ -} SPI_MODE_t; - -/* Prescaler setting */ -typedef enum SPI_PRESCALER_enum -{ - SPI_PRESCALER_DIV4_gc = (0x00<<0), /* System Clock / 4 */ - SPI_PRESCALER_DIV16_gc = (0x01<<0), /* System Clock / 16 */ - SPI_PRESCALER_DIV64_gc = (0x02<<0), /* System Clock / 64 */ - SPI_PRESCALER_DIV128_gc = (0x03<<0), /* System Clock / 128 */ -} SPI_PRESCALER_t; - -/* Interrupt level */ -typedef enum SPI_INTLVL_enum -{ - SPI_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - SPI_INTLVL_LO_gc = (0x01<<0), /* Low Level */ - SPI_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ - SPI_INTLVL_HI_gc = (0x03<<0), /* High Level */ -} SPI_INTLVL_t; - - -/* --------------------------------------------------------------------------- -IRCOM - IR Communication Module --------------------------------------------------------------------------- -*/ - -/* IR Communication Module */ -typedef struct IRCOM_struct -{ - register8_t CTRL; /* Control Register */ - register8_t TXPLCTRL; /* IrDA Transmitter Pulse Length Control Register */ - register8_t RXPLCTRL; /* IrDA Receiver Pulse Length Control Register */ -} IRCOM_t; - -/* Event channel selection */ -typedef enum IRDA_EVSEL_enum -{ - IRDA_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ - IRDA_EVSEL_0_gc = (0x08<<0), /* Event Channel 0 */ - IRDA_EVSEL_1_gc = (0x09<<0), /* Event Channel 1 */ - IRDA_EVSEL_2_gc = (0x0A<<0), /* Event Channel 2 */ - IRDA_EVSEL_3_gc = (0x0B<<0), /* Event Channel 3 */ - IRDA_EVSEL_4_gc = (0x0C<<0), /* Event Channel 4 */ - IRDA_EVSEL_5_gc = (0x0D<<0), /* Event Channel 5 */ - IRDA_EVSEL_6_gc = (0x0E<<0), /* Event Channel 6 */ - IRDA_EVSEL_7_gc = (0x0F<<0), /* Event Channel 7 */ -} IRDA_EVSEL_t; - - -/* --------------------------------------------------------------------------- -AES - AES Module --------------------------------------------------------------------------- -*/ - -/* AES Module */ -typedef struct AES_struct -{ - register8_t CTRL; /* AES Control Register */ - register8_t STATUS; /* AES Status Register */ - register8_t STATE; /* AES State Register */ - register8_t KEY; /* AES Key Register */ - register8_t INTCTRL; /* AES Interrupt Control Register */ -} AES_t; - -/* Interrupt level */ -typedef enum AES_INTLVL_enum -{ - AES_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - AES_INTLVL_LO_gc = (0x01<<0), /* Low Level */ - AES_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ - AES_INTLVL_HI_gc = (0x03<<0), /* High Level */ -} AES_INTLVL_t; - - - -/* -========================================================================== -IO Module Instances. Mapped to memory. -========================================================================== -*/ - -#define VPORT0 (*(VPORT_t *) 0x0010) /* Virtual Port 0 */ -#define VPORT1 (*(VPORT_t *) 0x0014) /* Virtual Port 1 */ -#define VPORT2 (*(VPORT_t *) 0x0018) /* Virtual Port 2 */ -#define VPORT3 (*(VPORT_t *) 0x001C) /* Virtual Port 3 */ -#define OCD (*(OCD_t *) 0x002E) /* On-Chip Debug System */ -#define CLK (*(CLK_t *) 0x0040) /* Clock System */ -#define SLEEP (*(SLEEP_t *) 0x0048) /* Sleep Controller */ -#define OSC (*(OSC_t *) 0x0050) /* Oscillator Control */ -#define DFLLRC32M (*(DFLL_t *) 0x0060) /* DFLL for 32MHz RC Oscillator */ -#define DFLLRC2M (*(DFLL_t *) 0x0068) /* DFLL for 2MHz RC Oscillator */ -#define PR (*(PR_t *) 0x0070) /* Power Reduction */ -#define RST (*(RST_t *) 0x0078) /* Reset Controller */ -#define WDT (*(WDT_t *) 0x0080) /* Watch-Dog Timer */ -#define MCU (*(MCU_t *) 0x0090) /* MCU Control */ -#define PMIC (*(PMIC_t *) 0x00A0) /* Programmable Interrupt Controller */ -#define PORTCFG (*(PORTCFG_t *) 0x00B0) /* Port Configuration */ -#define AES (*(AES_t *) 0x00C0) /* AES Crypto Module */ -#define DMA (*(DMA_t *) 0x0100) /* DMA Controller */ -#define EVSYS (*(EVSYS_t *) 0x0180) /* Event System */ -#define NVM (*(NVM_t *) 0x01C0) /* Non Volatile Memory Controller */ -#define ADCA (*(ADC_t *) 0x0200) /* Analog to Digital Converter A */ -#define ADCB (*(ADC_t *) 0x0240) /* Analog to Digital Converter B */ -#define DACB (*(DAC_t *) 0x0320) /* Digital to Analog Converter B */ -#define ACA (*(AC_t *) 0x0380) /* Analog Comparator A */ -#define ACB (*(AC_t *) 0x0390) /* Analog Comparator B */ -#define RTC (*(RTC_t *) 0x0400) /* Real-Time Counter */ -#define TWIC (*(TWI_t *) 0x0480) /* Two-Wire Interface C */ -#define TWIE (*(TWI_t *) 0x04A0) /* Two-Wire Interface E */ -#define PORTA (*(PORT_t *) 0x0600) /* Port A */ -#define PORTB (*(PORT_t *) 0x0620) /* Port B */ -#define PORTC (*(PORT_t *) 0x0640) /* Port C */ -#define PORTD (*(PORT_t *) 0x0660) /* Port D */ -#define PORTE (*(PORT_t *) 0x0680) /* Port E */ -#define PORTF (*(PORT_t *) 0x06A0) /* Port F */ -#define PORTR (*(PORT_t *) 0x07E0) /* Port R */ -#define TCC0 (*(TC0_t *) 0x0800) /* Timer/Counter C0 */ -#define TCC1 (*(TC1_t *) 0x0840) /* Timer/Counter C1 */ -#define AWEXC (*(AWEX_t *) 0x0880) /* Advanced Waveform Extension C */ -#define HIRESC (*(HIRES_t *) 0x0890) /* High-Resolution Extension C */ -#define USARTC0 (*(USART_t *) 0x08A0) /* Universal Asynchronous Receiver-Transmitter C0 */ -#define USARTC1 (*(USART_t *) 0x08B0) /* Universal Asynchronous Receiver-Transmitter C1 */ -#define SPIC (*(SPI_t *) 0x08C0) /* Serial Peripheral Interface C */ -#define IRCOM (*(IRCOM_t *) 0x08F8) /* IR Communication Module */ -#define TCD0 (*(TC0_t *) 0x0900) /* Timer/Counter D0 */ -#define TCD1 (*(TC1_t *) 0x0940) /* Timer/Counter D1 */ -#define HIRESD (*(HIRES_t *) 0x0990) /* High-Resolution Extension D */ -#define USARTD0 (*(USART_t *) 0x09A0) /* Universal Asynchronous Receiver-Transmitter D0 */ -#define USARTD1 (*(USART_t *) 0x09B0) /* Universal Asynchronous Receiver-Transmitter D1 */ -#define SPID (*(SPI_t *) 0x09C0) /* Serial Peripheral Interface D */ -#define TCE0 (*(TC0_t *) 0x0A00) /* Timer/Counter E0 */ -#define TCE1 (*(TC1_t *) 0x0A40) /* Timer/Counter E1 */ -#define AWEXE (*(AWEX_t *) 0x0A80) /* Advanced Waveform Extension E */ -#define HIRESE (*(HIRES_t *) 0x0A90) /* High-Resolution Extension E */ -#define USARTE0 (*(USART_t *) 0x0AA0) /* Universal Asynchronous Receiver-Transmitter E0 */ -#define USARTE1 (*(USART_t *) 0x0AB0) /* Universal Asynchronous Receiver-Transmitter E1 */ -#define SPIE (*(SPI_t *) 0x0AC0) /* Serial Peripheral Interface E */ -#define TCF0 (*(TC0_t *) 0x0B00) /* Timer/Counter F0 */ -#define HIRESF (*(HIRES_t *) 0x0B90) /* High-Resolution Extension F */ -#define USARTF0 (*(USART_t *) 0x0BA0) /* Universal Asynchronous Receiver-Transmitter F0 */ -#define USARTF1 (*(USART_t *) 0x0BB0) /* Universal Asynchronous Receiver-Transmitter F1 */ -#define SPIF (*(SPI_t *) 0x0BC0) /* Serial Peripheral Interface F */ - - -#endif /* !defined (__ASSEMBLER__) */ - - -/* ========== Flattened fully qualified IO register names ========== */ - -/* GPIO - General Purpose IO Registers */ -#define GPIO_GPIOR0 _SFR_MEM8(0x0000) -#define GPIO_GPIOR1 _SFR_MEM8(0x0001) -#define GPIO_GPIOR2 _SFR_MEM8(0x0002) -#define GPIO_GPIOR3 _SFR_MEM8(0x0003) -#define GPIO_GPIOR4 _SFR_MEM8(0x0004) -#define GPIO_GPIOR5 _SFR_MEM8(0x0005) -#define GPIO_GPIOR6 _SFR_MEM8(0x0006) -#define GPIO_GPIOR7 _SFR_MEM8(0x0007) -#define GPIO_GPIOR8 _SFR_MEM8(0x0008) -#define GPIO_GPIOR9 _SFR_MEM8(0x0009) -#define GPIO_GPIORA _SFR_MEM8(0x000A) -#define GPIO_GPIORB _SFR_MEM8(0x000B) -#define GPIO_GPIORC _SFR_MEM8(0x000C) -#define GPIO_GPIORD _SFR_MEM8(0x000D) -#define GPIO_GPIORE _SFR_MEM8(0x000E) -#define GPIO_GPIORF _SFR_MEM8(0x000F) - -/* Deprecated */ -#define GPIO_GPIO0 _SFR_MEM8(0x0000) -#define GPIO_GPIO1 _SFR_MEM8(0x0001) -#define GPIO_GPIO2 _SFR_MEM8(0x0002) -#define GPIO_GPIO3 _SFR_MEM8(0x0003) -#define GPIO_GPIO4 _SFR_MEM8(0x0004) -#define GPIO_GPIO5 _SFR_MEM8(0x0005) -#define GPIO_GPIO6 _SFR_MEM8(0x0006) -#define GPIO_GPIO7 _SFR_MEM8(0x0007) -#define GPIO_GPIO8 _SFR_MEM8(0x0008) -#define GPIO_GPIO9 _SFR_MEM8(0x0009) -#define GPIO_GPIOA _SFR_MEM8(0x000A) -#define GPIO_GPIOB _SFR_MEM8(0x000B) -#define GPIO_GPIOC _SFR_MEM8(0x000C) -#define GPIO_GPIOD _SFR_MEM8(0x000D) -#define GPIO_GPIOE _SFR_MEM8(0x000E) -#define GPIO_GPIOF _SFR_MEM8(0x000F) - -/* VPORT0 - Virtual Port 0 */ -#define VPORT0_DIR _SFR_MEM8(0x0010) -#define VPORT0_OUT _SFR_MEM8(0x0011) -#define VPORT0_IN _SFR_MEM8(0x0012) -#define VPORT0_INTFLAGS _SFR_MEM8(0x0013) - -/* VPORT1 - Virtual Port 1 */ -#define VPORT1_DIR _SFR_MEM8(0x0014) -#define VPORT1_OUT _SFR_MEM8(0x0015) -#define VPORT1_IN _SFR_MEM8(0x0016) -#define VPORT1_INTFLAGS _SFR_MEM8(0x0017) - -/* VPORT2 - Virtual Port 2 */ -#define VPORT2_DIR _SFR_MEM8(0x0018) -#define VPORT2_OUT _SFR_MEM8(0x0019) -#define VPORT2_IN _SFR_MEM8(0x001A) -#define VPORT2_INTFLAGS _SFR_MEM8(0x001B) - -/* VPORT3 - Virtual Port 3 */ -#define VPORT3_DIR _SFR_MEM8(0x001C) -#define VPORT3_OUT _SFR_MEM8(0x001D) -#define VPORT3_IN _SFR_MEM8(0x001E) -#define VPORT3_INTFLAGS _SFR_MEM8(0x001F) - -/* OCD - On-Chip Debug System */ -#define OCD_OCDR0 _SFR_MEM8(0x002E) -#define OCD_OCDR1 _SFR_MEM8(0x002F) - -/* CPU - CPU Registers */ -#define CPU_CCP _SFR_MEM8(0x0034) -#define CPU_RAMPD _SFR_MEM8(0x0038) -#define CPU_RAMPX _SFR_MEM8(0x0039) -#define CPU_RAMPY _SFR_MEM8(0x003A) -#define CPU_RAMPZ _SFR_MEM8(0x003B) -#define CPU_EIND _SFR_MEM8(0x003C) -#define CPU_SPL _SFR_MEM8(0x003D) -#define CPU_SPH _SFR_MEM8(0x003E) -#define CPU_SREG _SFR_MEM8(0x003F) - -/* CLK - Clock System */ -#define CLK_CTRL _SFR_MEM8(0x0040) -#define CLK_PSCTRL _SFR_MEM8(0x0041) -#define CLK_LOCK _SFR_MEM8(0x0042) -#define CLK_RTCCTRL _SFR_MEM8(0x0043) - -/* SLEEP - Sleep Controller */ -#define SLEEP_CTRL _SFR_MEM8(0x0048) - -/* OSC - Oscillator Control */ -#define OSC_CTRL _SFR_MEM8(0x0050) -#define OSC_STATUS _SFR_MEM8(0x0051) -#define OSC_XOSCCTRL _SFR_MEM8(0x0052) -#define OSC_XOSCFAIL _SFR_MEM8(0x0053) -#define OSC_RC32KCAL _SFR_MEM8(0x0054) -#define OSC_PLLCTRL _SFR_MEM8(0x0055) -#define OSC_DFLLCTRL _SFR_MEM8(0x0056) - -/* DFLLRC32M - DFLL for 32MHz RC Oscillator */ -#define DFLLRC32M_CTRL _SFR_MEM8(0x0060) -#define DFLLRC32M_CALA _SFR_MEM8(0x0062) -#define DFLLRC32M_CALB _SFR_MEM8(0x0063) -#define DFLLRC32M_COMP0 _SFR_MEM8(0x0064) -#define DFLLRC32M_COMP1 _SFR_MEM8(0x0065) -#define DFLLRC32M_COMP2 _SFR_MEM8(0x0066) - -/* DFLLRC2M - DFLL for 2MHz RC Oscillator */ -#define DFLLRC2M_CTRL _SFR_MEM8(0x0068) -#define DFLLRC2M_CALA _SFR_MEM8(0x006A) -#define DFLLRC2M_CALB _SFR_MEM8(0x006B) -#define DFLLRC2M_COMP0 _SFR_MEM8(0x006C) -#define DFLLRC2M_COMP1 _SFR_MEM8(0x006D) -#define DFLLRC2M_COMP2 _SFR_MEM8(0x006E) - -/* PR - Power Reduction */ -#define PR_PRGEN _SFR_MEM8(0x0070) -#define PR_PRPA _SFR_MEM8(0x0071) -#define PR_PRPB _SFR_MEM8(0x0072) -#define PR_PRPC _SFR_MEM8(0x0073) -#define PR_PRPD _SFR_MEM8(0x0074) -#define PR_PRPE _SFR_MEM8(0x0075) -#define PR_PRPF _SFR_MEM8(0x0076) - -/* RST - Reset Controller */ -#define RST_STATUS _SFR_MEM8(0x0078) -#define RST_CTRL _SFR_MEM8(0x0079) - -/* WDT - Watch-Dog Timer */ -#define WDT_CTRL _SFR_MEM8(0x0080) -#define WDT_WINCTRL _SFR_MEM8(0x0081) -#define WDT_STATUS _SFR_MEM8(0x0082) - -/* MCU - MCU Control */ -#define MCU_DEVID0 _SFR_MEM8(0x0090) -#define MCU_DEVID1 _SFR_MEM8(0x0091) -#define MCU_DEVID2 _SFR_MEM8(0x0092) -#define MCU_REVID _SFR_MEM8(0x0093) -#define MCU_JTAGUID _SFR_MEM8(0x0094) -#define MCU_MCUCR _SFR_MEM8(0x0096) -#define MCU_EVSYSLOCK _SFR_MEM8(0x0098) -#define MCU_AWEXLOCK _SFR_MEM8(0x0099) - -/* PMIC - Programmable Interrupt Controller */ -#define PMIC_STATUS _SFR_MEM8(0x00A0) -#define PMIC_INTPRI _SFR_MEM8(0x00A1) -#define PMIC_CTRL _SFR_MEM8(0x00A2) - -/* PORTCFG - Port Configuration */ -#define PORTCFG_MPCMASK _SFR_MEM8(0x00B0) -#define PORTCFG_VPCTRLA _SFR_MEM8(0x00B2) -#define PORTCFG_VPCTRLB _SFR_MEM8(0x00B3) -#define PORTCFG_CLKEVOUT _SFR_MEM8(0x00B4) - -/* AES - AES Crypto Module */ -#define AES_CTRL _SFR_MEM8(0x00C0) -#define AES_STATUS _SFR_MEM8(0x00C1) -#define AES_STATE _SFR_MEM8(0x00C2) -#define AES_KEY _SFR_MEM8(0x00C3) -#define AES_INTCTRL _SFR_MEM8(0x00C4) - -/* DMA - DMA Controller */ -#define DMA_CTRL _SFR_MEM8(0x0100) -#define DMA_INTFLAGS _SFR_MEM8(0x0103) -#define DMA_STATUS _SFR_MEM8(0x0104) -#define DMA_TEMP _SFR_MEM16(0x0106) -#define DMA_CH0_CTRLA _SFR_MEM8(0x0110) -#define DMA_CH0_CTRLB _SFR_MEM8(0x0111) -#define DMA_CH0_ADDRCTRL _SFR_MEM8(0x0112) -#define DMA_CH0_TRIGSRC _SFR_MEM8(0x0113) -#define DMA_CH0_TRFCNT _SFR_MEM16(0x0114) -#define DMA_CH0_REPCNT _SFR_MEM8(0x0116) -#define DMA_CH0_SRCADDR0 _SFR_MEM8(0x0118) -#define DMA_CH0_SRCADDR1 _SFR_MEM8(0x0119) -#define DMA_CH0_SRCADDR2 _SFR_MEM8(0x011A) -#define DMA_CH0_DESTADDR0 _SFR_MEM8(0x011C) -#define DMA_CH0_DESTADDR1 _SFR_MEM8(0x011D) -#define DMA_CH0_DESTADDR2 _SFR_MEM8(0x011E) -#define DMA_CH1_CTRLA _SFR_MEM8(0x0120) -#define DMA_CH1_CTRLB _SFR_MEM8(0x0121) -#define DMA_CH1_ADDRCTRL _SFR_MEM8(0x0122) -#define DMA_CH1_TRIGSRC _SFR_MEM8(0x0123) -#define DMA_CH1_TRFCNT _SFR_MEM16(0x0124) -#define DMA_CH1_REPCNT _SFR_MEM8(0x0126) -#define DMA_CH1_SRCADDR0 _SFR_MEM8(0x0128) -#define DMA_CH1_SRCADDR1 _SFR_MEM8(0x0129) -#define DMA_CH1_SRCADDR2 _SFR_MEM8(0x012A) -#define DMA_CH1_DESTADDR0 _SFR_MEM8(0x012C) -#define DMA_CH1_DESTADDR1 _SFR_MEM8(0x012D) -#define DMA_CH1_DESTADDR2 _SFR_MEM8(0x012E) -#define DMA_CH2_CTRLA _SFR_MEM8(0x0130) -#define DMA_CH2_CTRLB _SFR_MEM8(0x0131) -#define DMA_CH2_ADDRCTRL _SFR_MEM8(0x0132) -#define DMA_CH2_TRIGSRC _SFR_MEM8(0x0133) -#define DMA_CH2_TRFCNT _SFR_MEM16(0x0134) -#define DMA_CH2_REPCNT _SFR_MEM8(0x0136) -#define DMA_CH2_SRCADDR0 _SFR_MEM8(0x0138) -#define DMA_CH2_SRCADDR1 _SFR_MEM8(0x0139) -#define DMA_CH2_SRCADDR2 _SFR_MEM8(0x013A) -#define DMA_CH2_DESTADDR0 _SFR_MEM8(0x013C) -#define DMA_CH2_DESTADDR1 _SFR_MEM8(0x013D) -#define DMA_CH2_DESTADDR2 _SFR_MEM8(0x013E) -#define DMA_CH3_CTRLA _SFR_MEM8(0x0140) -#define DMA_CH3_CTRLB _SFR_MEM8(0x0141) -#define DMA_CH3_ADDRCTRL _SFR_MEM8(0x0142) -#define DMA_CH3_TRIGSRC _SFR_MEM8(0x0143) -#define DMA_CH3_TRFCNT _SFR_MEM16(0x0144) -#define DMA_CH3_REPCNT _SFR_MEM8(0x0146) -#define DMA_CH3_SRCADDR0 _SFR_MEM8(0x0148) -#define DMA_CH3_SRCADDR1 _SFR_MEM8(0x0149) -#define DMA_CH3_SRCADDR2 _SFR_MEM8(0x014A) -#define DMA_CH3_DESTADDR0 _SFR_MEM8(0x014C) -#define DMA_CH3_DESTADDR1 _SFR_MEM8(0x014D) -#define DMA_CH3_DESTADDR2 _SFR_MEM8(0x014E) - -/* EVSYS - Event System */ -#define EVSYS_CH0MUX _SFR_MEM8(0x0180) -#define EVSYS_CH1MUX _SFR_MEM8(0x0181) -#define EVSYS_CH2MUX _SFR_MEM8(0x0182) -#define EVSYS_CH3MUX _SFR_MEM8(0x0183) -#define EVSYS_CH4MUX _SFR_MEM8(0x0184) -#define EVSYS_CH5MUX _SFR_MEM8(0x0185) -#define EVSYS_CH6MUX _SFR_MEM8(0x0186) -#define EVSYS_CH7MUX _SFR_MEM8(0x0187) -#define EVSYS_CH0CTRL _SFR_MEM8(0x0188) -#define EVSYS_CH1CTRL _SFR_MEM8(0x0189) -#define EVSYS_CH2CTRL _SFR_MEM8(0x018A) -#define EVSYS_CH3CTRL _SFR_MEM8(0x018B) -#define EVSYS_CH4CTRL _SFR_MEM8(0x018C) -#define EVSYS_CH5CTRL _SFR_MEM8(0x018D) -#define EVSYS_CH6CTRL _SFR_MEM8(0x018E) -#define EVSYS_CH7CTRL _SFR_MEM8(0x018F) -#define EVSYS_STROBE _SFR_MEM8(0x0190) -#define EVSYS_DATA _SFR_MEM8(0x0191) - -/* NVM - Non Volatile Memory Controller */ -#define NVM_ADDR0 _SFR_MEM8(0x01C0) -#define NVM_ADDR1 _SFR_MEM8(0x01C1) -#define NVM_ADDR2 _SFR_MEM8(0x01C2) -#define NVM_DATA0 _SFR_MEM8(0x01C4) -#define NVM_DATA1 _SFR_MEM8(0x01C5) -#define NVM_DATA2 _SFR_MEM8(0x01C6) -#define NVM_CMD _SFR_MEM8(0x01CA) -#define NVM_CTRLA _SFR_MEM8(0x01CB) -#define NVM_CTRLB _SFR_MEM8(0x01CC) -#define NVM_INTCTRL _SFR_MEM8(0x01CD) -#define NVM_STATUS _SFR_MEM8(0x01CF) -#define NVM_LOCKBITS _SFR_MEM8(0x01D0) - -/* ADCA - Analog to Digital Converter A */ -#define ADCA_CTRLA _SFR_MEM8(0x0200) -#define ADCA_CTRLB _SFR_MEM8(0x0201) -#define ADCA_REFCTRL _SFR_MEM8(0x0202) -#define ADCA_EVCTRL _SFR_MEM8(0x0203) -#define ADCA_PRESCALER _SFR_MEM8(0x0204) -#define ADCA_INTFLAGS _SFR_MEM8(0x0206) -#define ADCA_CAL _SFR_MEM16(0x020C) -#define ADCA_CH0RES _SFR_MEM16(0x0210) -#define ADCA_CH1RES _SFR_MEM16(0x0212) -#define ADCA_CH2RES _SFR_MEM16(0x0214) -#define ADCA_CH3RES _SFR_MEM16(0x0216) -#define ADCA_CMP _SFR_MEM16(0x0218) -#define ADCA_CH0_CTRL _SFR_MEM8(0x0220) -#define ADCA_CH0_MUXCTRL _SFR_MEM8(0x0221) -#define ADCA_CH0_INTCTRL _SFR_MEM8(0x0222) -#define ADCA_CH0_INTFLAGS _SFR_MEM8(0x0223) -#define ADCA_CH0_RES _SFR_MEM16(0x0224) -#define ADCA_CH1_CTRL _SFR_MEM8(0x0228) -#define ADCA_CH1_MUXCTRL _SFR_MEM8(0x0229) -#define ADCA_CH1_INTCTRL _SFR_MEM8(0x022A) -#define ADCA_CH1_INTFLAGS _SFR_MEM8(0x022B) -#define ADCA_CH1_RES _SFR_MEM16(0x022C) -#define ADCA_CH2_CTRL _SFR_MEM8(0x0230) -#define ADCA_CH2_MUXCTRL _SFR_MEM8(0x0231) -#define ADCA_CH2_INTCTRL _SFR_MEM8(0x0232) -#define ADCA_CH2_INTFLAGS _SFR_MEM8(0x0233) -#define ADCA_CH2_RES _SFR_MEM16(0x0234) -#define ADCA_CH3_CTRL _SFR_MEM8(0x0238) -#define ADCA_CH3_MUXCTRL _SFR_MEM8(0x0239) -#define ADCA_CH3_INTCTRL _SFR_MEM8(0x023A) -#define ADCA_CH3_INTFLAGS _SFR_MEM8(0x023B) -#define ADCA_CH3_RES _SFR_MEM16(0x023C) - -/* ADCB - Analog to Digital Converter B */ -#define ADCB_CTRLA _SFR_MEM8(0x0240) -#define ADCB_CTRLB _SFR_MEM8(0x0241) -#define ADCB_REFCTRL _SFR_MEM8(0x0242) -#define ADCB_EVCTRL _SFR_MEM8(0x0243) -#define ADCB_PRESCALER _SFR_MEM8(0x0244) -#define ADCB_INTFLAGS _SFR_MEM8(0x0246) -#define ADCB_CAL _SFR_MEM16(0x024C) -#define ADCB_CH0RES _SFR_MEM16(0x0250) -#define ADCB_CH1RES _SFR_MEM16(0x0252) -#define ADCB_CH2RES _SFR_MEM16(0x0254) -#define ADCB_CH3RES _SFR_MEM16(0x0256) -#define ADCB_CMP _SFR_MEM16(0x0258) -#define ADCB_CH0_CTRL _SFR_MEM8(0x0260) -#define ADCB_CH0_MUXCTRL _SFR_MEM8(0x0261) -#define ADCB_CH0_INTCTRL _SFR_MEM8(0x0262) -#define ADCB_CH0_INTFLAGS _SFR_MEM8(0x0263) -#define ADCB_CH0_RES _SFR_MEM16(0x0264) -#define ADCB_CH1_CTRL _SFR_MEM8(0x0268) -#define ADCB_CH1_MUXCTRL _SFR_MEM8(0x0269) -#define ADCB_CH1_INTCTRL _SFR_MEM8(0x026A) -#define ADCB_CH1_INTFLAGS _SFR_MEM8(0x026B) -#define ADCB_CH1_RES _SFR_MEM16(0x026C) -#define ADCB_CH2_CTRL _SFR_MEM8(0x0270) -#define ADCB_CH2_MUXCTRL _SFR_MEM8(0x0271) -#define ADCB_CH2_INTCTRL _SFR_MEM8(0x0272) -#define ADCB_CH2_INTFLAGS _SFR_MEM8(0x0273) -#define ADCB_CH2_RES _SFR_MEM16(0x0274) -#define ADCB_CH3_CTRL _SFR_MEM8(0x0278) -#define ADCB_CH3_MUXCTRL _SFR_MEM8(0x0279) -#define ADCB_CH3_INTCTRL _SFR_MEM8(0x027A) -#define ADCB_CH3_INTFLAGS _SFR_MEM8(0x027B) -#define ADCB_CH3_RES _SFR_MEM16(0x027C) - -/* DACB - Digital to Analog Converter B */ -#define DACB_CTRLA _SFR_MEM8(0x0320) -#define DACB_CTRLB _SFR_MEM8(0x0321) -#define DACB_CTRLC _SFR_MEM8(0x0322) -#define DACB_EVCTRL _SFR_MEM8(0x0323) -#define DACB_TIMCTRL _SFR_MEM8(0x0324) -#define DACB_STATUS _SFR_MEM8(0x0325) -#define DACB_GAINCAL _SFR_MEM8(0x0328) -#define DACB_OFFSETCAL _SFR_MEM8(0x0329) -#define DACB_CH0DATA _SFR_MEM16(0x0338) -#define DACB_CH1DATA _SFR_MEM16(0x033A) - -/* ACA - Analog Comparator A */ -#define ACA_AC0CTRL _SFR_MEM8(0x0380) -#define ACA_AC1CTRL _SFR_MEM8(0x0381) -#define ACA_AC0MUXCTRL _SFR_MEM8(0x0382) -#define ACA_AC1MUXCTRL _SFR_MEM8(0x0383) -#define ACA_CTRLA _SFR_MEM8(0x0384) -#define ACA_CTRLB _SFR_MEM8(0x0385) -#define ACA_WINCTRL _SFR_MEM8(0x0386) -#define ACA_STATUS _SFR_MEM8(0x0387) - -/* ACB - Analog Comparator B */ -#define ACB_AC0CTRL _SFR_MEM8(0x0390) -#define ACB_AC1CTRL _SFR_MEM8(0x0391) -#define ACB_AC0MUXCTRL _SFR_MEM8(0x0392) -#define ACB_AC1MUXCTRL _SFR_MEM8(0x0393) -#define ACB_CTRLA _SFR_MEM8(0x0394) -#define ACB_CTRLB _SFR_MEM8(0x0395) -#define ACB_WINCTRL _SFR_MEM8(0x0396) -#define ACB_STATUS _SFR_MEM8(0x0397) - -/* RTC - Real-Time Counter */ -#define RTC_CTRL _SFR_MEM8(0x0400) -#define RTC_STATUS _SFR_MEM8(0x0401) -#define RTC_INTCTRL _SFR_MEM8(0x0402) -#define RTC_INTFLAGS _SFR_MEM8(0x0403) -#define RTC_TEMP _SFR_MEM8(0x0404) -#define RTC_CNT _SFR_MEM16(0x0408) -#define RTC_PER _SFR_MEM16(0x040A) -#define RTC_COMP _SFR_MEM16(0x040C) - -/* TWIC - Two-Wire Interface C */ -#define TWIC_CTRL _SFR_MEM8(0x0480) -#define TWIC_MASTER_CTRLA _SFR_MEM8(0x0481) -#define TWIC_MASTER_CTRLB _SFR_MEM8(0x0482) -#define TWIC_MASTER_CTRLC _SFR_MEM8(0x0483) -#define TWIC_MASTER_STATUS _SFR_MEM8(0x0484) -#define TWIC_MASTER_BAUD _SFR_MEM8(0x0485) -#define TWIC_MASTER_ADDR _SFR_MEM8(0x0486) -#define TWIC_MASTER_DATA _SFR_MEM8(0x0487) -#define TWIC_SLAVE_CTRLA _SFR_MEM8(0x0488) -#define TWIC_SLAVE_CTRLB _SFR_MEM8(0x0489) -#define TWIC_SLAVE_STATUS _SFR_MEM8(0x048A) -#define TWIC_SLAVE_ADDR _SFR_MEM8(0x048B) -#define TWIC_SLAVE_DATA _SFR_MEM8(0x048C) -#define TWIC_SLAVE_ADDRMASK _SFR_MEM8(0x048D) - -/* TWIE - Two-Wire Interface E */ -#define TWIE_CTRL _SFR_MEM8(0x04A0) -#define TWIE_MASTER_CTRLA _SFR_MEM8(0x04A1) -#define TWIE_MASTER_CTRLB _SFR_MEM8(0x04A2) -#define TWIE_MASTER_CTRLC _SFR_MEM8(0x04A3) -#define TWIE_MASTER_STATUS _SFR_MEM8(0x04A4) -#define TWIE_MASTER_BAUD _SFR_MEM8(0x04A5) -#define TWIE_MASTER_ADDR _SFR_MEM8(0x04A6) -#define TWIE_MASTER_DATA _SFR_MEM8(0x04A7) -#define TWIE_SLAVE_CTRLA _SFR_MEM8(0x04A8) -#define TWIE_SLAVE_CTRLB _SFR_MEM8(0x04A9) -#define TWIE_SLAVE_STATUS _SFR_MEM8(0x04AA) -#define TWIE_SLAVE_ADDR _SFR_MEM8(0x04AB) -#define TWIE_SLAVE_DATA _SFR_MEM8(0x04AC) -#define TWIE_SLAVE_ADDRMASK _SFR_MEM8(0x04AD) - -/* PORTA - Port A */ -#define PORTA_DIR _SFR_MEM8(0x0600) -#define PORTA_DIRSET _SFR_MEM8(0x0601) -#define PORTA_DIRCLR _SFR_MEM8(0x0602) -#define PORTA_DIRTGL _SFR_MEM8(0x0603) -#define PORTA_OUT _SFR_MEM8(0x0604) -#define PORTA_OUTSET _SFR_MEM8(0x0605) -#define PORTA_OUTCLR _SFR_MEM8(0x0606) -#define PORTA_OUTTGL _SFR_MEM8(0x0607) -#define PORTA_IN _SFR_MEM8(0x0608) -#define PORTA_INTCTRL _SFR_MEM8(0x0609) -#define PORTA_INT0MASK _SFR_MEM8(0x060A) -#define PORTA_INT1MASK _SFR_MEM8(0x060B) -#define PORTA_INTFLAGS _SFR_MEM8(0x060C) -#define PORTA_PIN0CTRL _SFR_MEM8(0x0610) -#define PORTA_PIN1CTRL _SFR_MEM8(0x0611) -#define PORTA_PIN2CTRL _SFR_MEM8(0x0612) -#define PORTA_PIN3CTRL _SFR_MEM8(0x0613) -#define PORTA_PIN4CTRL _SFR_MEM8(0x0614) -#define PORTA_PIN5CTRL _SFR_MEM8(0x0615) -#define PORTA_PIN6CTRL _SFR_MEM8(0x0616) -#define PORTA_PIN7CTRL _SFR_MEM8(0x0617) - -/* PORTB - Port B */ -#define PORTB_DIR _SFR_MEM8(0x0620) -#define PORTB_DIRSET _SFR_MEM8(0x0621) -#define PORTB_DIRCLR _SFR_MEM8(0x0622) -#define PORTB_DIRTGL _SFR_MEM8(0x0623) -#define PORTB_OUT _SFR_MEM8(0x0624) -#define PORTB_OUTSET _SFR_MEM8(0x0625) -#define PORTB_OUTCLR _SFR_MEM8(0x0626) -#define PORTB_OUTTGL _SFR_MEM8(0x0627) -#define PORTB_IN _SFR_MEM8(0x0628) -#define PORTB_INTCTRL _SFR_MEM8(0x0629) -#define PORTB_INT0MASK _SFR_MEM8(0x062A) -#define PORTB_INT1MASK _SFR_MEM8(0x062B) -#define PORTB_INTFLAGS _SFR_MEM8(0x062C) -#define PORTB_PIN0CTRL _SFR_MEM8(0x0630) -#define PORTB_PIN1CTRL _SFR_MEM8(0x0631) -#define PORTB_PIN2CTRL _SFR_MEM8(0x0632) -#define PORTB_PIN3CTRL _SFR_MEM8(0x0633) -#define PORTB_PIN4CTRL _SFR_MEM8(0x0634) -#define PORTB_PIN5CTRL _SFR_MEM8(0x0635) -#define PORTB_PIN6CTRL _SFR_MEM8(0x0636) -#define PORTB_PIN7CTRL _SFR_MEM8(0x0637) - -/* PORTC - Port C */ -#define PORTC_DIR _SFR_MEM8(0x0640) -#define PORTC_DIRSET _SFR_MEM8(0x0641) -#define PORTC_DIRCLR _SFR_MEM8(0x0642) -#define PORTC_DIRTGL _SFR_MEM8(0x0643) -#define PORTC_OUT _SFR_MEM8(0x0644) -#define PORTC_OUTSET _SFR_MEM8(0x0645) -#define PORTC_OUTCLR _SFR_MEM8(0x0646) -#define PORTC_OUTTGL _SFR_MEM8(0x0647) -#define PORTC_IN _SFR_MEM8(0x0648) -#define PORTC_INTCTRL _SFR_MEM8(0x0649) -#define PORTC_INT0MASK _SFR_MEM8(0x064A) -#define PORTC_INT1MASK _SFR_MEM8(0x064B) -#define PORTC_INTFLAGS _SFR_MEM8(0x064C) -#define PORTC_PIN0CTRL _SFR_MEM8(0x0650) -#define PORTC_PIN1CTRL _SFR_MEM8(0x0651) -#define PORTC_PIN2CTRL _SFR_MEM8(0x0652) -#define PORTC_PIN3CTRL _SFR_MEM8(0x0653) -#define PORTC_PIN4CTRL _SFR_MEM8(0x0654) -#define PORTC_PIN5CTRL _SFR_MEM8(0x0655) -#define PORTC_PIN6CTRL _SFR_MEM8(0x0656) -#define PORTC_PIN7CTRL _SFR_MEM8(0x0657) - -/* PORTD - Port D */ -#define PORTD_DIR _SFR_MEM8(0x0660) -#define PORTD_DIRSET _SFR_MEM8(0x0661) -#define PORTD_DIRCLR _SFR_MEM8(0x0662) -#define PORTD_DIRTGL _SFR_MEM8(0x0663) -#define PORTD_OUT _SFR_MEM8(0x0664) -#define PORTD_OUTSET _SFR_MEM8(0x0665) -#define PORTD_OUTCLR _SFR_MEM8(0x0666) -#define PORTD_OUTTGL _SFR_MEM8(0x0667) -#define PORTD_IN _SFR_MEM8(0x0668) -#define PORTD_INTCTRL _SFR_MEM8(0x0669) -#define PORTD_INT0MASK _SFR_MEM8(0x066A) -#define PORTD_INT1MASK _SFR_MEM8(0x066B) -#define PORTD_INTFLAGS _SFR_MEM8(0x066C) -#define PORTD_PIN0CTRL _SFR_MEM8(0x0670) -#define PORTD_PIN1CTRL _SFR_MEM8(0x0671) -#define PORTD_PIN2CTRL _SFR_MEM8(0x0672) -#define PORTD_PIN3CTRL _SFR_MEM8(0x0673) -#define PORTD_PIN4CTRL _SFR_MEM8(0x0674) -#define PORTD_PIN5CTRL _SFR_MEM8(0x0675) -#define PORTD_PIN6CTRL _SFR_MEM8(0x0676) -#define PORTD_PIN7CTRL _SFR_MEM8(0x0677) - -/* PORTE - Port E */ -#define PORTE_DIR _SFR_MEM8(0x0680) -#define PORTE_DIRSET _SFR_MEM8(0x0681) -#define PORTE_DIRCLR _SFR_MEM8(0x0682) -#define PORTE_DIRTGL _SFR_MEM8(0x0683) -#define PORTE_OUT _SFR_MEM8(0x0684) -#define PORTE_OUTSET _SFR_MEM8(0x0685) -#define PORTE_OUTCLR _SFR_MEM8(0x0686) -#define PORTE_OUTTGL _SFR_MEM8(0x0687) -#define PORTE_IN _SFR_MEM8(0x0688) -#define PORTE_INTCTRL _SFR_MEM8(0x0689) -#define PORTE_INT0MASK _SFR_MEM8(0x068A) -#define PORTE_INT1MASK _SFR_MEM8(0x068B) -#define PORTE_INTFLAGS _SFR_MEM8(0x068C) -#define PORTE_PIN0CTRL _SFR_MEM8(0x0690) -#define PORTE_PIN1CTRL _SFR_MEM8(0x0691) -#define PORTE_PIN2CTRL _SFR_MEM8(0x0692) -#define PORTE_PIN3CTRL _SFR_MEM8(0x0693) -#define PORTE_PIN4CTRL _SFR_MEM8(0x0694) -#define PORTE_PIN5CTRL _SFR_MEM8(0x0695) -#define PORTE_PIN6CTRL _SFR_MEM8(0x0696) -#define PORTE_PIN7CTRL _SFR_MEM8(0x0697) - -/* PORTF - Port F */ -#define PORTF_DIR _SFR_MEM8(0x06A0) -#define PORTF_DIRSET _SFR_MEM8(0x06A1) -#define PORTF_DIRCLR _SFR_MEM8(0x06A2) -#define PORTF_DIRTGL _SFR_MEM8(0x06A3) -#define PORTF_OUT _SFR_MEM8(0x06A4) -#define PORTF_OUTSET _SFR_MEM8(0x06A5) -#define PORTF_OUTCLR _SFR_MEM8(0x06A6) -#define PORTF_OUTTGL _SFR_MEM8(0x06A7) -#define PORTF_IN _SFR_MEM8(0x06A8) -#define PORTF_INTCTRL _SFR_MEM8(0x06A9) -#define PORTF_INT0MASK _SFR_MEM8(0x06AA) -#define PORTF_INT1MASK _SFR_MEM8(0x06AB) -#define PORTF_INTFLAGS _SFR_MEM8(0x06AC) -#define PORTF_PIN0CTRL _SFR_MEM8(0x06B0) -#define PORTF_PIN1CTRL _SFR_MEM8(0x06B1) -#define PORTF_PIN2CTRL _SFR_MEM8(0x06B2) -#define PORTF_PIN3CTRL _SFR_MEM8(0x06B3) -#define PORTF_PIN4CTRL _SFR_MEM8(0x06B4) -#define PORTF_PIN5CTRL _SFR_MEM8(0x06B5) -#define PORTF_PIN6CTRL _SFR_MEM8(0x06B6) -#define PORTF_PIN7CTRL _SFR_MEM8(0x06B7) - -/* PORTR - Port R */ -#define PORTR_DIR _SFR_MEM8(0x07E0) -#define PORTR_DIRSET _SFR_MEM8(0x07E1) -#define PORTR_DIRCLR _SFR_MEM8(0x07E2) -#define PORTR_DIRTGL _SFR_MEM8(0x07E3) -#define PORTR_OUT _SFR_MEM8(0x07E4) -#define PORTR_OUTSET _SFR_MEM8(0x07E5) -#define PORTR_OUTCLR _SFR_MEM8(0x07E6) -#define PORTR_OUTTGL _SFR_MEM8(0x07E7) -#define PORTR_IN _SFR_MEM8(0x07E8) -#define PORTR_INTCTRL _SFR_MEM8(0x07E9) -#define PORTR_INT0MASK _SFR_MEM8(0x07EA) -#define PORTR_INT1MASK _SFR_MEM8(0x07EB) -#define PORTR_INTFLAGS _SFR_MEM8(0x07EC) -#define PORTR_PIN0CTRL _SFR_MEM8(0x07F0) -#define PORTR_PIN1CTRL _SFR_MEM8(0x07F1) -#define PORTR_PIN2CTRL _SFR_MEM8(0x07F2) -#define PORTR_PIN3CTRL _SFR_MEM8(0x07F3) -#define PORTR_PIN4CTRL _SFR_MEM8(0x07F4) -#define PORTR_PIN5CTRL _SFR_MEM8(0x07F5) -#define PORTR_PIN6CTRL _SFR_MEM8(0x07F6) -#define PORTR_PIN7CTRL _SFR_MEM8(0x07F7) - -/* TCC0 - Timer/Counter C0 */ -#define TCC0_CTRLA _SFR_MEM8(0x0800) -#define TCC0_CTRLB _SFR_MEM8(0x0801) -#define TCC0_CTRLC _SFR_MEM8(0x0802) -#define TCC0_CTRLD _SFR_MEM8(0x0803) -#define TCC0_CTRLE _SFR_MEM8(0x0804) -#define TCC0_INTCTRLA _SFR_MEM8(0x0806) -#define TCC0_INTCTRLB _SFR_MEM8(0x0807) -#define TCC0_CTRLFCLR _SFR_MEM8(0x0808) -#define TCC0_CTRLFSET _SFR_MEM8(0x0809) -#define TCC0_CTRLGCLR _SFR_MEM8(0x080A) -#define TCC0_CTRLGSET _SFR_MEM8(0x080B) -#define TCC0_INTFLAGS _SFR_MEM8(0x080C) -#define TCC0_TEMP _SFR_MEM8(0x080F) -#define TCC0_CNT _SFR_MEM16(0x0820) -#define TCC0_PER _SFR_MEM16(0x0826) -#define TCC0_CCA _SFR_MEM16(0x0828) -#define TCC0_CCB _SFR_MEM16(0x082A) -#define TCC0_CCC _SFR_MEM16(0x082C) -#define TCC0_CCD _SFR_MEM16(0x082E) -#define TCC0_PERBUF _SFR_MEM16(0x0836) -#define TCC0_CCABUF _SFR_MEM16(0x0838) -#define TCC0_CCBBUF _SFR_MEM16(0x083A) -#define TCC0_CCCBUF _SFR_MEM16(0x083C) -#define TCC0_CCDBUF _SFR_MEM16(0x083E) - -/* TCC1 - Timer/Counter C1 */ -#define TCC1_CTRLA _SFR_MEM8(0x0840) -#define TCC1_CTRLB _SFR_MEM8(0x0841) -#define TCC1_CTRLC _SFR_MEM8(0x0842) -#define TCC1_CTRLD _SFR_MEM8(0x0843) -#define TCC1_CTRLE _SFR_MEM8(0x0844) -#define TCC1_INTCTRLA _SFR_MEM8(0x0846) -#define TCC1_INTCTRLB _SFR_MEM8(0x0847) -#define TCC1_CTRLFCLR _SFR_MEM8(0x0848) -#define TCC1_CTRLFSET _SFR_MEM8(0x0849) -#define TCC1_CTRLGCLR _SFR_MEM8(0x084A) -#define TCC1_CTRLGSET _SFR_MEM8(0x084B) -#define TCC1_INTFLAGS _SFR_MEM8(0x084C) -#define TCC1_TEMP _SFR_MEM8(0x084F) -#define TCC1_CNT _SFR_MEM16(0x0860) -#define TCC1_PER _SFR_MEM16(0x0866) -#define TCC1_CCA _SFR_MEM16(0x0868) -#define TCC1_CCB _SFR_MEM16(0x086A) -#define TCC1_PERBUF _SFR_MEM16(0x0876) -#define TCC1_CCABUF _SFR_MEM16(0x0878) -#define TCC1_CCBBUF _SFR_MEM16(0x087A) - -/* AWEXC - Advanced Waveform Extension C */ -#define AWEXC_CTRL _SFR_MEM8(0x0880) -#define AWEXC_FDEMASK _SFR_MEM8(0x0882) -#define AWEXC_FDCTRL _SFR_MEM8(0x0883) -#define AWEXC_STATUS _SFR_MEM8(0x0884) -#define AWEXC_DTBOTH _SFR_MEM8(0x0886) -#define AWEXC_DTBOTHBUF _SFR_MEM8(0x0887) -#define AWEXC_DTLS _SFR_MEM8(0x0888) -#define AWEXC_DTHS _SFR_MEM8(0x0889) -#define AWEXC_DTLSBUF _SFR_MEM8(0x088A) -#define AWEXC_DTHSBUF _SFR_MEM8(0x088B) -#define AWEXC_OUTOVEN _SFR_MEM8(0x088C) - -/* HIRESC - High-Resolution Extension C */ -#define HIRESC_CTRLA _SFR_MEM8(0x0890) - -/* USARTC0 - Universal Asynchronous Receiver-Transmitter C0 */ -#define USARTC0_DATA _SFR_MEM8(0x08A0) -#define USARTC0_STATUS _SFR_MEM8(0x08A1) -#define USARTC0_CTRLA _SFR_MEM8(0x08A3) -#define USARTC0_CTRLB _SFR_MEM8(0x08A4) -#define USARTC0_CTRLC _SFR_MEM8(0x08A5) -#define USARTC0_BAUDCTRLA _SFR_MEM8(0x08A6) -#define USARTC0_BAUDCTRLB _SFR_MEM8(0x08A7) - -/* USARTC1 - Universal Asynchronous Receiver-Transmitter C1 */ -#define USARTC1_DATA _SFR_MEM8(0x08B0) -#define USARTC1_STATUS _SFR_MEM8(0x08B1) -#define USARTC1_CTRLA _SFR_MEM8(0x08B3) -#define USARTC1_CTRLB _SFR_MEM8(0x08B4) -#define USARTC1_CTRLC _SFR_MEM8(0x08B5) -#define USARTC1_BAUDCTRLA _SFR_MEM8(0x08B6) -#define USARTC1_BAUDCTRLB _SFR_MEM8(0x08B7) - -/* SPIC - Serial Peripheral Interface C */ -#define SPIC_CTRL _SFR_MEM8(0x08C0) -#define SPIC_INTCTRL _SFR_MEM8(0x08C1) -#define SPIC_STATUS _SFR_MEM8(0x08C2) -#define SPIC_DATA _SFR_MEM8(0x08C3) - -/* IRCOM - IR Communication Module */ -#define IRCOM_CTRL _SFR_MEM8(0x08F8) -#define IRCOM_TXPLCTRL _SFR_MEM8(0x08F9) -#define IRCOM_RXPLCTRL _SFR_MEM8(0x08FA) - -/* TCD0 - Timer/Counter D0 */ -#define TCD0_CTRLA _SFR_MEM8(0x0900) -#define TCD0_CTRLB _SFR_MEM8(0x0901) -#define TCD0_CTRLC _SFR_MEM8(0x0902) -#define TCD0_CTRLD _SFR_MEM8(0x0903) -#define TCD0_CTRLE _SFR_MEM8(0x0904) -#define TCD0_INTCTRLA _SFR_MEM8(0x0906) -#define TCD0_INTCTRLB _SFR_MEM8(0x0907) -#define TCD0_CTRLFCLR _SFR_MEM8(0x0908) -#define TCD0_CTRLFSET _SFR_MEM8(0x0909) -#define TCD0_CTRLGCLR _SFR_MEM8(0x090A) -#define TCD0_CTRLGSET _SFR_MEM8(0x090B) -#define TCD0_INTFLAGS _SFR_MEM8(0x090C) -#define TCD0_TEMP _SFR_MEM8(0x090F) -#define TCD0_CNT _SFR_MEM16(0x0920) -#define TCD0_PER _SFR_MEM16(0x0926) -#define TCD0_CCA _SFR_MEM16(0x0928) -#define TCD0_CCB _SFR_MEM16(0x092A) -#define TCD0_CCC _SFR_MEM16(0x092C) -#define TCD0_CCD _SFR_MEM16(0x092E) -#define TCD0_PERBUF _SFR_MEM16(0x0936) -#define TCD0_CCABUF _SFR_MEM16(0x0938) -#define TCD0_CCBBUF _SFR_MEM16(0x093A) -#define TCD0_CCCBUF _SFR_MEM16(0x093C) -#define TCD0_CCDBUF _SFR_MEM16(0x093E) - -/* TCD1 - Timer/Counter D1 */ -#define TCD1_CTRLA _SFR_MEM8(0x0940) -#define TCD1_CTRLB _SFR_MEM8(0x0941) -#define TCD1_CTRLC _SFR_MEM8(0x0942) -#define TCD1_CTRLD _SFR_MEM8(0x0943) -#define TCD1_CTRLE _SFR_MEM8(0x0944) -#define TCD1_INTCTRLA _SFR_MEM8(0x0946) -#define TCD1_INTCTRLB _SFR_MEM8(0x0947) -#define TCD1_CTRLFCLR _SFR_MEM8(0x0948) -#define TCD1_CTRLFSET _SFR_MEM8(0x0949) -#define TCD1_CTRLGCLR _SFR_MEM8(0x094A) -#define TCD1_CTRLGSET _SFR_MEM8(0x094B) -#define TCD1_INTFLAGS _SFR_MEM8(0x094C) -#define TCD1_TEMP _SFR_MEM8(0x094F) -#define TCD1_CNT _SFR_MEM16(0x0960) -#define TCD1_PER _SFR_MEM16(0x0966) -#define TCD1_CCA _SFR_MEM16(0x0968) -#define TCD1_CCB _SFR_MEM16(0x096A) -#define TCD1_PERBUF _SFR_MEM16(0x0976) -#define TCD1_CCABUF _SFR_MEM16(0x0978) -#define TCD1_CCBBUF _SFR_MEM16(0x097A) - -/* HIRESD - High-Resolution Extension D */ -#define HIRESD_CTRLA _SFR_MEM8(0x0990) - -/* USARTD0 - Universal Asynchronous Receiver-Transmitter D0 */ -#define USARTD0_DATA _SFR_MEM8(0x09A0) -#define USARTD0_STATUS _SFR_MEM8(0x09A1) -#define USARTD0_CTRLA _SFR_MEM8(0x09A3) -#define USARTD0_CTRLB _SFR_MEM8(0x09A4) -#define USARTD0_CTRLC _SFR_MEM8(0x09A5) -#define USARTD0_BAUDCTRLA _SFR_MEM8(0x09A6) -#define USARTD0_BAUDCTRLB _SFR_MEM8(0x09A7) - -/* USARTD1 - Universal Asynchronous Receiver-Transmitter D1 */ -#define USARTD1_DATA _SFR_MEM8(0x09B0) -#define USARTD1_STATUS _SFR_MEM8(0x09B1) -#define USARTD1_CTRLA _SFR_MEM8(0x09B3) -#define USARTD1_CTRLB _SFR_MEM8(0x09B4) -#define USARTD1_CTRLC _SFR_MEM8(0x09B5) -#define USARTD1_BAUDCTRLA _SFR_MEM8(0x09B6) -#define USARTD1_BAUDCTRLB _SFR_MEM8(0x09B7) - -/* SPID - Serial Peripheral Interface D */ -#define SPID_CTRL _SFR_MEM8(0x09C0) -#define SPID_INTCTRL _SFR_MEM8(0x09C1) -#define SPID_STATUS _SFR_MEM8(0x09C2) -#define SPID_DATA _SFR_MEM8(0x09C3) - -/* TCE0 - Timer/Counter E0 */ -#define TCE0_CTRLA _SFR_MEM8(0x0A00) -#define TCE0_CTRLB _SFR_MEM8(0x0A01) -#define TCE0_CTRLC _SFR_MEM8(0x0A02) -#define TCE0_CTRLD _SFR_MEM8(0x0A03) -#define TCE0_CTRLE _SFR_MEM8(0x0A04) -#define TCE0_INTCTRLA _SFR_MEM8(0x0A06) -#define TCE0_INTCTRLB _SFR_MEM8(0x0A07) -#define TCE0_CTRLFCLR _SFR_MEM8(0x0A08) -#define TCE0_CTRLFSET _SFR_MEM8(0x0A09) -#define TCE0_CTRLGCLR _SFR_MEM8(0x0A0A) -#define TCE0_CTRLGSET _SFR_MEM8(0x0A0B) -#define TCE0_INTFLAGS _SFR_MEM8(0x0A0C) -#define TCE0_TEMP _SFR_MEM8(0x0A0F) -#define TCE0_CNT _SFR_MEM16(0x0A20) -#define TCE0_PER _SFR_MEM16(0x0A26) -#define TCE0_CCA _SFR_MEM16(0x0A28) -#define TCE0_CCB _SFR_MEM16(0x0A2A) -#define TCE0_CCC _SFR_MEM16(0x0A2C) -#define TCE0_CCD _SFR_MEM16(0x0A2E) -#define TCE0_PERBUF _SFR_MEM16(0x0A36) -#define TCE0_CCABUF _SFR_MEM16(0x0A38) -#define TCE0_CCBBUF _SFR_MEM16(0x0A3A) -#define TCE0_CCCBUF _SFR_MEM16(0x0A3C) -#define TCE0_CCDBUF _SFR_MEM16(0x0A3E) - -/* TCE1 - Timer/Counter E1 */ -#define TCE1_CTRLA _SFR_MEM8(0x0A40) -#define TCE1_CTRLB _SFR_MEM8(0x0A41) -#define TCE1_CTRLC _SFR_MEM8(0x0A42) -#define TCE1_CTRLD _SFR_MEM8(0x0A43) -#define TCE1_CTRLE _SFR_MEM8(0x0A44) -#define TCE1_INTCTRLA _SFR_MEM8(0x0A46) -#define TCE1_INTCTRLB _SFR_MEM8(0x0A47) -#define TCE1_CTRLFCLR _SFR_MEM8(0x0A48) -#define TCE1_CTRLFSET _SFR_MEM8(0x0A49) -#define TCE1_CTRLGCLR _SFR_MEM8(0x0A4A) -#define TCE1_CTRLGSET _SFR_MEM8(0x0A4B) -#define TCE1_INTFLAGS _SFR_MEM8(0x0A4C) -#define TCE1_TEMP _SFR_MEM8(0x0A4F) -#define TCE1_CNT _SFR_MEM16(0x0A60) -#define TCE1_PER _SFR_MEM16(0x0A66) -#define TCE1_CCA _SFR_MEM16(0x0A68) -#define TCE1_CCB _SFR_MEM16(0x0A6A) -#define TCE1_PERBUF _SFR_MEM16(0x0A76) -#define TCE1_CCABUF _SFR_MEM16(0x0A78) -#define TCE1_CCBBUF _SFR_MEM16(0x0A7A) - -/* AWEXE - Advanced Waveform Extension E */ -#define AWEXE_CTRL _SFR_MEM8(0x0A80) -#define AWEXE_FDEMASK _SFR_MEM8(0x0A82) -#define AWEXE_FDCTRL _SFR_MEM8(0x0A83) -#define AWEXE_STATUS _SFR_MEM8(0x0A84) -#define AWEXE_DTBOTH _SFR_MEM8(0x0A86) -#define AWEXE_DTBOTHBUF _SFR_MEM8(0x0A87) -#define AWEXE_DTLS _SFR_MEM8(0x0A88) -#define AWEXE_DTHS _SFR_MEM8(0x0A89) -#define AWEXE_DTLSBUF _SFR_MEM8(0x0A8A) -#define AWEXE_DTHSBUF _SFR_MEM8(0x0A8B) -#define AWEXE_OUTOVEN _SFR_MEM8(0x0A8C) - -/* HIRESE - High-Resolution Extension E */ -#define HIRESE_CTRLA _SFR_MEM8(0x0A90) - -/* USARTE0 - Universal Asynchronous Receiver-Transmitter E0 */ -#define USARTE0_DATA _SFR_MEM8(0x0AA0) -#define USARTE0_STATUS _SFR_MEM8(0x0AA1) -#define USARTE0_CTRLA _SFR_MEM8(0x0AA3) -#define USARTE0_CTRLB _SFR_MEM8(0x0AA4) -#define USARTE0_CTRLC _SFR_MEM8(0x0AA5) -#define USARTE0_BAUDCTRLA _SFR_MEM8(0x0AA6) -#define USARTE0_BAUDCTRLB _SFR_MEM8(0x0AA7) - -/* USARTE1 - Universal Asynchronous Receiver-Transmitter E1 */ -#define USARTE1_DATA _SFR_MEM8(0x0AB0) -#define USARTE1_STATUS _SFR_MEM8(0x0AB1) -#define USARTE1_CTRLA _SFR_MEM8(0x0AB3) -#define USARTE1_CTRLB _SFR_MEM8(0x0AB4) -#define USARTE1_CTRLC _SFR_MEM8(0x0AB5) -#define USARTE1_BAUDCTRLA _SFR_MEM8(0x0AB6) -#define USARTE1_BAUDCTRLB _SFR_MEM8(0x0AB7) - -/* SPIE - Serial Peripheral Interface E */ -#define SPIE_CTRL _SFR_MEM8(0x0AC0) -#define SPIE_INTCTRL _SFR_MEM8(0x0AC1) -#define SPIE_STATUS _SFR_MEM8(0x0AC2) -#define SPIE_DATA _SFR_MEM8(0x0AC3) - -/* TCF0 - Timer/Counter F0 */ -#define TCF0_CTRLA _SFR_MEM8(0x0B00) -#define TCF0_CTRLB _SFR_MEM8(0x0B01) -#define TCF0_CTRLC _SFR_MEM8(0x0B02) -#define TCF0_CTRLD _SFR_MEM8(0x0B03) -#define TCF0_CTRLE _SFR_MEM8(0x0B04) -#define TCF0_INTCTRLA _SFR_MEM8(0x0B06) -#define TCF0_INTCTRLB _SFR_MEM8(0x0B07) -#define TCF0_CTRLFCLR _SFR_MEM8(0x0B08) -#define TCF0_CTRLFSET _SFR_MEM8(0x0B09) -#define TCF0_CTRLGCLR _SFR_MEM8(0x0B0A) -#define TCF0_CTRLGSET _SFR_MEM8(0x0B0B) -#define TCF0_INTFLAGS _SFR_MEM8(0x0B0C) -#define TCF0_TEMP _SFR_MEM8(0x0B0F) -#define TCF0_CNT _SFR_MEM16(0x0B20) -#define TCF0_PER _SFR_MEM16(0x0B26) -#define TCF0_CCA _SFR_MEM16(0x0B28) -#define TCF0_CCB _SFR_MEM16(0x0B2A) -#define TCF0_CCC _SFR_MEM16(0x0B2C) -#define TCF0_CCD _SFR_MEM16(0x0B2E) -#define TCF0_PERBUF _SFR_MEM16(0x0B36) -#define TCF0_CCABUF _SFR_MEM16(0x0B38) -#define TCF0_CCBBUF _SFR_MEM16(0x0B3A) -#define TCF0_CCCBUF _SFR_MEM16(0x0B3C) -#define TCF0_CCDBUF _SFR_MEM16(0x0B3E) - -/* HIRESF - High-Resolution Extension F */ -#define HIRESF_CTRLA _SFR_MEM8(0x0B90) - -/* USARTF0 - Universal Asynchronous Receiver-Transmitter F0 */ -#define USARTF0_DATA _SFR_MEM8(0x0BA0) -#define USARTF0_STATUS _SFR_MEM8(0x0BA1) -#define USARTF0_CTRLA _SFR_MEM8(0x0BA3) -#define USARTF0_CTRLB _SFR_MEM8(0x0BA4) -#define USARTF0_CTRLC _SFR_MEM8(0x0BA5) -#define USARTF0_BAUDCTRLA _SFR_MEM8(0x0BA6) -#define USARTF0_BAUDCTRLB _SFR_MEM8(0x0BA7) - -/* USARTF1 - Universal Asynchronous Receiver-Transmitter F1 */ -#define USARTF1_DATA _SFR_MEM8(0x0BB0) -#define USARTF1_STATUS _SFR_MEM8(0x0BB1) -#define USARTF1_CTRLA _SFR_MEM8(0x0BB3) -#define USARTF1_CTRLB _SFR_MEM8(0x0BB4) -#define USARTF1_CTRLC _SFR_MEM8(0x0BB5) -#define USARTF1_BAUDCTRLA _SFR_MEM8(0x0BB6) -#define USARTF1_BAUDCTRLB _SFR_MEM8(0x0BB7) - -/* SPIF - Serial Peripheral Interface F */ -#define SPIF_CTRL _SFR_MEM8(0x0BC0) -#define SPIF_INTCTRL _SFR_MEM8(0x0BC1) -#define SPIF_STATUS _SFR_MEM8(0x0BC2) -#define SPIF_DATA _SFR_MEM8(0x0BC3) - - - -/*================== Bitfield Definitions ================== */ - -/* XOCD - On-Chip Debug System */ -/* OCD.OCDR1 bit masks and bit positions */ -#define OCD_OCDRD_bm 0x01 /* OCDR Dirty bit mask. */ -#define OCD_OCDRD_bp 0 /* OCDR Dirty bit position. */ - - -/* CPU - CPU */ -/* CPU.CCP bit masks and bit positions */ -#define CPU_CCP_gm 0xFF /* CCP signature group mask. */ -#define CPU_CCP_gp 0 /* CCP signature group position. */ -#define CPU_CCP0_bm (1<<0) /* CCP signature bit 0 mask. */ -#define CPU_CCP0_bp 0 /* CCP signature bit 0 position. */ -#define CPU_CCP1_bm (1<<1) /* CCP signature bit 1 mask. */ -#define CPU_CCP1_bp 1 /* CCP signature bit 1 position. */ -#define CPU_CCP2_bm (1<<2) /* CCP signature bit 2 mask. */ -#define CPU_CCP2_bp 2 /* CCP signature bit 2 position. */ -#define CPU_CCP3_bm (1<<3) /* CCP signature bit 3 mask. */ -#define CPU_CCP3_bp 3 /* CCP signature bit 3 position. */ -#define CPU_CCP4_bm (1<<4) /* CCP signature bit 4 mask. */ -#define CPU_CCP4_bp 4 /* CCP signature bit 4 position. */ -#define CPU_CCP5_bm (1<<5) /* CCP signature bit 5 mask. */ -#define CPU_CCP5_bp 5 /* CCP signature bit 5 position. */ -#define CPU_CCP6_bm (1<<6) /* CCP signature bit 6 mask. */ -#define CPU_CCP6_bp 6 /* CCP signature bit 6 position. */ -#define CPU_CCP7_bm (1<<7) /* CCP signature bit 7 mask. */ -#define CPU_CCP7_bp 7 /* CCP signature bit 7 position. */ - - -/* CPU.SREG bit masks and bit positions */ -#define CPU_I_bm 0x80 /* Global Interrupt Enable Flag bit mask. */ -#define CPU_I_bp 7 /* Global Interrupt Enable Flag bit position. */ - -#define CPU_T_bm 0x40 /* Transfer Bit bit mask. */ -#define CPU_T_bp 6 /* Transfer Bit bit position. */ - -#define CPU_H_bm 0x20 /* Half Carry Flag bit mask. */ -#define CPU_H_bp 5 /* Half Carry Flag bit position. */ - -#define CPU_S_bm 0x10 /* N Exclusive Or V Flag bit mask. */ -#define CPU_S_bp 4 /* N Exclusive Or V Flag bit position. */ - -#define CPU_V_bm 0x08 /* Two's Complement Overflow Flag bit mask. */ -#define CPU_V_bp 3 /* Two's Complement Overflow Flag bit position. */ - -#define CPU_N_bm 0x04 /* Negative Flag bit mask. */ -#define CPU_N_bp 2 /* Negative Flag bit position. */ - -#define CPU_Z_bm 0x02 /* Zero Flag bit mask. */ -#define CPU_Z_bp 1 /* Zero Flag bit position. */ - -#define CPU_C_bm 0x01 /* Carry Flag bit mask. */ -#define CPU_C_bp 0 /* Carry Flag bit position. */ - - -/* CLK - Clock System */ -/* CLK.CTRL bit masks and bit positions */ -#define CLK_SCLKSEL_gm 0x07 /* System Clock Selection group mask. */ -#define CLK_SCLKSEL_gp 0 /* System Clock Selection group position. */ -#define CLK_SCLKSEL0_bm (1<<0) /* System Clock Selection bit 0 mask. */ -#define CLK_SCLKSEL0_bp 0 /* System Clock Selection bit 0 position. */ -#define CLK_SCLKSEL1_bm (1<<1) /* System Clock Selection bit 1 mask. */ -#define CLK_SCLKSEL1_bp 1 /* System Clock Selection bit 1 position. */ -#define CLK_SCLKSEL2_bm (1<<2) /* System Clock Selection bit 2 mask. */ -#define CLK_SCLKSEL2_bp 2 /* System Clock Selection bit 2 position. */ - - -/* CLK.PSCTRL bit masks and bit positions */ -#define CLK_PSADIV_gm 0x7C /* Prescaler A Division Factor group mask. */ -#define CLK_PSADIV_gp 2 /* Prescaler A Division Factor group position. */ -#define CLK_PSADIV0_bm (1<<2) /* Prescaler A Division Factor bit 0 mask. */ -#define CLK_PSADIV0_bp 2 /* Prescaler A Division Factor bit 0 position. */ -#define CLK_PSADIV1_bm (1<<3) /* Prescaler A Division Factor bit 1 mask. */ -#define CLK_PSADIV1_bp 3 /* Prescaler A Division Factor bit 1 position. */ -#define CLK_PSADIV2_bm (1<<4) /* Prescaler A Division Factor bit 2 mask. */ -#define CLK_PSADIV2_bp 4 /* Prescaler A Division Factor bit 2 position. */ -#define CLK_PSADIV3_bm (1<<5) /* Prescaler A Division Factor bit 3 mask. */ -#define CLK_PSADIV3_bp 5 /* Prescaler A Division Factor bit 3 position. */ -#define CLK_PSADIV4_bm (1<<6) /* Prescaler A Division Factor bit 4 mask. */ -#define CLK_PSADIV4_bp 6 /* Prescaler A Division Factor bit 4 position. */ - -#define CLK_PSBCDIV_gm 0x03 /* Prescaler B and C Division factor group mask. */ -#define CLK_PSBCDIV_gp 0 /* Prescaler B and C Division factor group position. */ -#define CLK_PSBCDIV0_bm (1<<0) /* Prescaler B and C Division factor bit 0 mask. */ -#define CLK_PSBCDIV0_bp 0 /* Prescaler B and C Division factor bit 0 position. */ -#define CLK_PSBCDIV1_bm (1<<1) /* Prescaler B and C Division factor bit 1 mask. */ -#define CLK_PSBCDIV1_bp 1 /* Prescaler B and C Division factor bit 1 position. */ - - -/* CLK.LOCK bit masks and bit positions */ -#define CLK_LOCK_bm 0x01 /* Clock System Lock bit mask. */ -#define CLK_LOCK_bp 0 /* Clock System Lock bit position. */ - - -/* CLK.RTCCTRL bit masks and bit positions */ -#define CLK_RTCSRC_gm 0x0E /* Clock Source group mask. */ -#define CLK_RTCSRC_gp 1 /* Clock Source group position. */ -#define CLK_RTCSRC0_bm (1<<1) /* Clock Source bit 0 mask. */ -#define CLK_RTCSRC0_bp 1 /* Clock Source bit 0 position. */ -#define CLK_RTCSRC1_bm (1<<2) /* Clock Source bit 1 mask. */ -#define CLK_RTCSRC1_bp 2 /* Clock Source bit 1 position. */ -#define CLK_RTCSRC2_bm (1<<3) /* Clock Source bit 2 mask. */ -#define CLK_RTCSRC2_bp 3 /* Clock Source bit 2 position. */ - -#define CLK_RTCEN_bm 0x01 /* RTC Clock Source Enable bit mask. */ -#define CLK_RTCEN_bp 0 /* RTC Clock Source Enable bit position. */ - - -/* PR.PRGEN bit masks and bit positions */ -#define PR_AES_bm 0x10 /* AES bit mask. */ -#define PR_AES_bp 4 /* AES bit position. */ - -#define PR_EBI_bm 0x08 /* External Bus Interface bit mask. */ -#define PR_EBI_bp 3 /* External Bus Interface bit position. */ - -#define PR_RTC_bm 0x04 /* Real-time Counter bit mask. */ -#define PR_RTC_bp 2 /* Real-time Counter bit position. */ - -#define PR_EVSYS_bm 0x02 /* Event System bit mask. */ -#define PR_EVSYS_bp 1 /* Event System bit position. */ - -#define PR_DMA_bm 0x01 /* DMA-Controller bit mask. */ -#define PR_DMA_bp 0 /* DMA-Controller bit position. */ - - -/* PR.PRPA bit masks and bit positions */ -#define PR_DAC_bm 0x04 /* Port A DAC bit mask. */ -#define PR_DAC_bp 2 /* Port A DAC bit position. */ - -#define PR_ADC_bm 0x02 /* Port A ADC bit mask. */ -#define PR_ADC_bp 1 /* Port A ADC bit position. */ - -#define PR_AC_bm 0x01 /* Port A Analog Comparator bit mask. */ -#define PR_AC_bp 0 /* Port A Analog Comparator bit position. */ - - -/* PR.PRPB bit masks and bit positions */ -/* PR_DAC_bm Predefined. */ -/* PR_DAC_bp Predefined. */ - -/* PR_ADC_bm Predefined. */ -/* PR_ADC_bp Predefined. */ - -/* PR_AC_bm Predefined. */ -/* PR_AC_bp Predefined. */ - - -/* PR.PRPC bit masks and bit positions */ -#define PR_TWI_bm 0x40 /* Port C Two-wire Interface bit mask. */ -#define PR_TWI_bp 6 /* Port C Two-wire Interface bit position. */ - -#define PR_USART1_bm 0x20 /* Port C USART1 bit mask. */ -#define PR_USART1_bp 5 /* Port C USART1 bit position. */ - -#define PR_USART0_bm 0x10 /* Port C USART0 bit mask. */ -#define PR_USART0_bp 4 /* Port C USART0 bit position. */ - -#define PR_SPI_bm 0x08 /* Port C SPI bit mask. */ -#define PR_SPI_bp 3 /* Port C SPI bit position. */ - -#define PR_HIRES_bm 0x04 /* Port C AWEX bit mask. */ -#define PR_HIRES_bp 2 /* Port C AWEX bit position. */ - -#define PR_TC1_bm 0x02 /* Port C Timer/Counter1 bit mask. */ -#define PR_TC1_bp 1 /* Port C Timer/Counter1 bit position. */ - -#define PR_TC0_bm 0x01 /* Port C Timer/Counter0 bit mask. */ -#define PR_TC0_bp 0 /* Port C Timer/Counter0 bit position. */ - - -/* PR.PRPD bit masks and bit positions */ -/* PR_TWI_bm Predefined. */ -/* PR_TWI_bp Predefined. */ - -/* PR_USART1_bm Predefined. */ -/* PR_USART1_bp Predefined. */ - -/* PR_USART0_bm Predefined. */ -/* PR_USART0_bp Predefined. */ - -/* PR_SPI_bm Predefined. */ -/* PR_SPI_bp Predefined. */ - -/* PR_HIRES_bm Predefined. */ -/* PR_HIRES_bp Predefined. */ - -/* PR_TC1_bm Predefined. */ -/* PR_TC1_bp Predefined. */ - -/* PR_TC0_bm Predefined. */ -/* PR_TC0_bp Predefined. */ - - -/* PR.PRPE bit masks and bit positions */ -/* PR_TWI_bm Predefined. */ -/* PR_TWI_bp Predefined. */ - -/* PR_USART1_bm Predefined. */ -/* PR_USART1_bp Predefined. */ - -/* PR_USART0_bm Predefined. */ -/* PR_USART0_bp Predefined. */ - -/* PR_SPI_bm Predefined. */ -/* PR_SPI_bp Predefined. */ - -/* PR_HIRES_bm Predefined. */ -/* PR_HIRES_bp Predefined. */ - -/* PR_TC1_bm Predefined. */ -/* PR_TC1_bp Predefined. */ - -/* PR_TC0_bm Predefined. */ -/* PR_TC0_bp Predefined. */ - - -/* PR.PRPF bit masks and bit positions */ -/* PR_TWI_bm Predefined. */ -/* PR_TWI_bp Predefined. */ - -/* PR_USART1_bm Predefined. */ -/* PR_USART1_bp Predefined. */ - -/* PR_USART0_bm Predefined. */ -/* PR_USART0_bp Predefined. */ - -/* PR_SPI_bm Predefined. */ -/* PR_SPI_bp Predefined. */ - -/* PR_HIRES_bm Predefined. */ -/* PR_HIRES_bp Predefined. */ - -/* PR_TC1_bm Predefined. */ -/* PR_TC1_bp Predefined. */ - -/* PR_TC0_bm Predefined. */ -/* PR_TC0_bp Predefined. */ - - -/* SLEEP - Sleep Controller */ -/* SLEEP.CTRL bit masks and bit positions */ -#define SLEEP_SMODE_gm 0x0E /* Sleep Mode group mask. */ -#define SLEEP_SMODE_gp 1 /* Sleep Mode group position. */ -#define SLEEP_SMODE0_bm (1<<1) /* Sleep Mode bit 0 mask. */ -#define SLEEP_SMODE0_bp 1 /* Sleep Mode bit 0 position. */ -#define SLEEP_SMODE1_bm (1<<2) /* Sleep Mode bit 1 mask. */ -#define SLEEP_SMODE1_bp 2 /* Sleep Mode bit 1 position. */ -#define SLEEP_SMODE2_bm (1<<3) /* Sleep Mode bit 2 mask. */ -#define SLEEP_SMODE2_bp 3 /* Sleep Mode bit 2 position. */ - -#define SLEEP_SEN_bm 0x01 /* Sleep Enable bit mask. */ -#define SLEEP_SEN_bp 0 /* Sleep Enable bit position. */ - - -/* OSC - Oscillator */ -/* OSC.CTRL bit masks and bit positions */ -#define OSC_PLLEN_bm 0x10 /* PLL Enable bit mask. */ -#define OSC_PLLEN_bp 4 /* PLL Enable bit position. */ - -#define OSC_XOSCEN_bm 0x08 /* External Oscillator Enable bit mask. */ -#define OSC_XOSCEN_bp 3 /* External Oscillator Enable bit position. */ - -#define OSC_RC32KEN_bm 0x04 /* Internal 32kHz RC Oscillator Enable bit mask. */ -#define OSC_RC32KEN_bp 2 /* Internal 32kHz RC Oscillator Enable bit position. */ - -#define OSC_RC32MEN_bm 0x02 /* Internal 32MHz RC Oscillator Enable bit mask. */ -#define OSC_RC32MEN_bp 1 /* Internal 32MHz RC Oscillator Enable bit position. */ - -#define OSC_RC2MEN_bm 0x01 /* Internal 2MHz RC Oscillator Enable bit mask. */ -#define OSC_RC2MEN_bp 0 /* Internal 2MHz RC Oscillator Enable bit position. */ - - -/* OSC.STATUS bit masks and bit positions */ -#define OSC_PLLRDY_bm 0x10 /* PLL Ready bit mask. */ -#define OSC_PLLRDY_bp 4 /* PLL Ready bit position. */ - -#define OSC_XOSCRDY_bm 0x08 /* External Oscillator Ready bit mask. */ -#define OSC_XOSCRDY_bp 3 /* External Oscillator Ready bit position. */ - -#define OSC_RC32KRDY_bm 0x04 /* Internal 32kHz RC Oscillator Ready bit mask. */ -#define OSC_RC32KRDY_bp 2 /* Internal 32kHz RC Oscillator Ready bit position. */ - -#define OSC_RC32MRDY_bm 0x02 /* Internal 32MHz RC Oscillator Ready bit mask. */ -#define OSC_RC32MRDY_bp 1 /* Internal 32MHz RC Oscillator Ready bit position. */ - -#define OSC_RC2MRDY_bm 0x01 /* Internal 2MHz RC Oscillator Ready bit mask. */ -#define OSC_RC2MRDY_bp 0 /* Internal 2MHz RC Oscillator Ready bit position. */ - - -/* OSC.XOSCCTRL bit masks and bit positions */ -#define OSC_FRQRANGE_gm 0xC0 /* Frequency Range group mask. */ -#define OSC_FRQRANGE_gp 6 /* Frequency Range group position. */ -#define OSC_FRQRANGE0_bm (1<<6) /* Frequency Range bit 0 mask. */ -#define OSC_FRQRANGE0_bp 6 /* Frequency Range bit 0 position. */ -#define OSC_FRQRANGE1_bm (1<<7) /* Frequency Range bit 1 mask. */ -#define OSC_FRQRANGE1_bp 7 /* Frequency Range bit 1 position. */ - -#define OSC_X32KLPM_bm 0x20 /* 32kHz XTAL OSC Low-power Mode bit mask. */ -#define OSC_X32KLPM_bp 5 /* 32kHz XTAL OSC Low-power Mode bit position. */ - -#define OSC_XOSCSEL_gm 0x0F /* External Oscillator Selection and Startup Time group mask. */ -#define OSC_XOSCSEL_gp 0 /* External Oscillator Selection and Startup Time group position. */ -#define OSC_XOSCSEL0_bm (1<<0) /* External Oscillator Selection and Startup Time bit 0 mask. */ -#define OSC_XOSCSEL0_bp 0 /* External Oscillator Selection and Startup Time bit 0 position. */ -#define OSC_XOSCSEL1_bm (1<<1) /* External Oscillator Selection and Startup Time bit 1 mask. */ -#define OSC_XOSCSEL1_bp 1 /* External Oscillator Selection and Startup Time bit 1 position. */ -#define OSC_XOSCSEL2_bm (1<<2) /* External Oscillator Selection and Startup Time bit 2 mask. */ -#define OSC_XOSCSEL2_bp 2 /* External Oscillator Selection and Startup Time bit 2 position. */ -#define OSC_XOSCSEL3_bm (1<<3) /* External Oscillator Selection and Startup Time bit 3 mask. */ -#define OSC_XOSCSEL3_bp 3 /* External Oscillator Selection and Startup Time bit 3 position. */ - - -/* OSC.XOSCFAIL bit masks and bit positions */ -#define OSC_XOSCFDIF_bm 0x02 /* Failure Detection Interrupt Flag bit mask. */ -#define OSC_XOSCFDIF_bp 1 /* Failure Detection Interrupt Flag bit position. */ - -#define OSC_XOSCFDEN_bm 0x01 /* Failure Detection Enable bit mask. */ -#define OSC_XOSCFDEN_bp 0 /* Failure Detection Enable bit position. */ - - -/* OSC.PLLCTRL bit masks and bit positions */ -#define OSC_PLLSRC_gm 0xC0 /* Clock Source group mask. */ -#define OSC_PLLSRC_gp 6 /* Clock Source group position. */ -#define OSC_PLLSRC0_bm (1<<6) /* Clock Source bit 0 mask. */ -#define OSC_PLLSRC0_bp 6 /* Clock Source bit 0 position. */ -#define OSC_PLLSRC1_bm (1<<7) /* Clock Source bit 1 mask. */ -#define OSC_PLLSRC1_bp 7 /* Clock Source bit 1 position. */ - -#define OSC_PLLFAC_gm 0x1F /* Multiplication Factor group mask. */ -#define OSC_PLLFAC_gp 0 /* Multiplication Factor group position. */ -#define OSC_PLLFAC0_bm (1<<0) /* Multiplication Factor bit 0 mask. */ -#define OSC_PLLFAC0_bp 0 /* Multiplication Factor bit 0 position. */ -#define OSC_PLLFAC1_bm (1<<1) /* Multiplication Factor bit 1 mask. */ -#define OSC_PLLFAC1_bp 1 /* Multiplication Factor bit 1 position. */ -#define OSC_PLLFAC2_bm (1<<2) /* Multiplication Factor bit 2 mask. */ -#define OSC_PLLFAC2_bp 2 /* Multiplication Factor bit 2 position. */ -#define OSC_PLLFAC3_bm (1<<3) /* Multiplication Factor bit 3 mask. */ -#define OSC_PLLFAC3_bp 3 /* Multiplication Factor bit 3 position. */ -#define OSC_PLLFAC4_bm (1<<4) /* Multiplication Factor bit 4 mask. */ -#define OSC_PLLFAC4_bp 4 /* Multiplication Factor bit 4 position. */ - - -/* OSC.DFLLCTRL bit masks and bit positions */ -#define OSC_RC32MCREF_bm 0x02 /* 32MHz Calibration Reference bit mask. */ -#define OSC_RC32MCREF_bp 1 /* 32MHz Calibration Reference bit position. */ - -#define OSC_RC2MCREF_bm 0x01 /* 2MHz Calibration Reference bit mask. */ -#define OSC_RC2MCREF_bp 0 /* 2MHz Calibration Reference bit position. */ - - -/* DFLL - DFLL */ -/* DFLL.CTRL bit masks and bit positions */ -#define DFLL_ENABLE_bm 0x01 /* DFLL Enable bit mask. */ -#define DFLL_ENABLE_bp 0 /* DFLL Enable bit position. */ - - -/* DFLL.CALA bit masks and bit positions */ -#define DFLL_CALL_gm 0x7F /* DFLL Calibration bits [6:0] group mask. */ -#define DFLL_CALL_gp 0 /* DFLL Calibration bits [6:0] group position. */ -#define DFLL_CALL0_bm (1<<0) /* DFLL Calibration bits [6:0] bit 0 mask. */ -#define DFLL_CALL0_bp 0 /* DFLL Calibration bits [6:0] bit 0 position. */ -#define DFLL_CALL1_bm (1<<1) /* DFLL Calibration bits [6:0] bit 1 mask. */ -#define DFLL_CALL1_bp 1 /* DFLL Calibration bits [6:0] bit 1 position. */ -#define DFLL_CALL2_bm (1<<2) /* DFLL Calibration bits [6:0] bit 2 mask. */ -#define DFLL_CALL2_bp 2 /* DFLL Calibration bits [6:0] bit 2 position. */ -#define DFLL_CALL3_bm (1<<3) /* DFLL Calibration bits [6:0] bit 3 mask. */ -#define DFLL_CALL3_bp 3 /* DFLL Calibration bits [6:0] bit 3 position. */ -#define DFLL_CALL4_bm (1<<4) /* DFLL Calibration bits [6:0] bit 4 mask. */ -#define DFLL_CALL4_bp 4 /* DFLL Calibration bits [6:0] bit 4 position. */ -#define DFLL_CALL5_bm (1<<5) /* DFLL Calibration bits [6:0] bit 5 mask. */ -#define DFLL_CALL5_bp 5 /* DFLL Calibration bits [6:0] bit 5 position. */ -#define DFLL_CALL6_bm (1<<6) /* DFLL Calibration bits [6:0] bit 6 mask. */ -#define DFLL_CALL6_bp 6 /* DFLL Calibration bits [6:0] bit 6 position. */ - - -/* DFLL.CALB bit masks and bit positions */ -#define DFLL_CALH_gm 0x3F /* DFLL Calibration bits [12:7] group mask. */ -#define DFLL_CALH_gp 0 /* DFLL Calibration bits [12:7] group position. */ -#define DFLL_CALH0_bm (1<<0) /* DFLL Calibration bits [12:7] bit 0 mask. */ -#define DFLL_CALH0_bp 0 /* DFLL Calibration bits [12:7] bit 0 position. */ -#define DFLL_CALH1_bm (1<<1) /* DFLL Calibration bits [12:7] bit 1 mask. */ -#define DFLL_CALH1_bp 1 /* DFLL Calibration bits [12:7] bit 1 position. */ -#define DFLL_CALH2_bm (1<<2) /* DFLL Calibration bits [12:7] bit 2 mask. */ -#define DFLL_CALH2_bp 2 /* DFLL Calibration bits [12:7] bit 2 position. */ -#define DFLL_CALH3_bm (1<<3) /* DFLL Calibration bits [12:7] bit 3 mask. */ -#define DFLL_CALH3_bp 3 /* DFLL Calibration bits [12:7] bit 3 position. */ -#define DFLL_CALH4_bm (1<<4) /* DFLL Calibration bits [12:7] bit 4 mask. */ -#define DFLL_CALH4_bp 4 /* DFLL Calibration bits [12:7] bit 4 position. */ -#define DFLL_CALH5_bm (1<<5) /* DFLL Calibration bits [12:7] bit 5 mask. */ -#define DFLL_CALH5_bp 5 /* DFLL Calibration bits [12:7] bit 5 position. */ - - -/* RST - Reset */ -/* RST.STATUS bit masks and bit positions */ -#define RST_SDRF_bm 0x40 /* Spike Detection Reset Flag bit mask. */ -#define RST_SDRF_bp 6 /* Spike Detection Reset Flag bit position. */ - -#define RST_SRF_bm 0x20 /* Software Reset Flag bit mask. */ -#define RST_SRF_bp 5 /* Software Reset Flag bit position. */ - -#define RST_PDIRF_bm 0x10 /* Programming and Debug Interface Interface Reset Flag bit mask. */ -#define RST_PDIRF_bp 4 /* Programming and Debug Interface Interface Reset Flag bit position. */ - -#define RST_WDRF_bm 0x08 /* Watchdog Reset Flag bit mask. */ -#define RST_WDRF_bp 3 /* Watchdog Reset Flag bit position. */ - -#define RST_BORF_bm 0x04 /* Brown-out Reset Flag bit mask. */ -#define RST_BORF_bp 2 /* Brown-out Reset Flag bit position. */ - -#define RST_EXTRF_bm 0x02 /* External Reset Flag bit mask. */ -#define RST_EXTRF_bp 1 /* External Reset Flag bit position. */ - -#define RST_PORF_bm 0x01 /* Power-on Reset Flag bit mask. */ -#define RST_PORF_bp 0 /* Power-on Reset Flag bit position. */ - - -/* RST.CTRL bit masks and bit positions */ -#define RST_SWRST_bm 0x01 /* Software Reset bit mask. */ -#define RST_SWRST_bp 0 /* Software Reset bit position. */ - - -/* WDT - Watch-Dog Timer */ -/* WDT.CTRL bit masks and bit positions */ -#define WDT_PER_gm 0x3C /* Period group mask. */ -#define WDT_PER_gp 2 /* Period group position. */ -#define WDT_PER0_bm (1<<2) /* Period bit 0 mask. */ -#define WDT_PER0_bp 2 /* Period bit 0 position. */ -#define WDT_PER1_bm (1<<3) /* Period bit 1 mask. */ -#define WDT_PER1_bp 3 /* Period bit 1 position. */ -#define WDT_PER2_bm (1<<4) /* Period bit 2 mask. */ -#define WDT_PER2_bp 4 /* Period bit 2 position. */ -#define WDT_PER3_bm (1<<5) /* Period bit 3 mask. */ -#define WDT_PER3_bp 5 /* Period bit 3 position. */ - -#define WDT_ENABLE_bm 0x02 /* Enable bit mask. */ -#define WDT_ENABLE_bp 1 /* Enable bit position. */ - -#define WDT_CEN_bm 0x01 /* Change Enable bit mask. */ -#define WDT_CEN_bp 0 /* Change Enable bit position. */ - - -/* WDT.WINCTRL bit masks and bit positions */ -#define WDT_WPER_gm 0x3C /* Windowed Mode Period group mask. */ -#define WDT_WPER_gp 2 /* Windowed Mode Period group position. */ -#define WDT_WPER0_bm (1<<2) /* Windowed Mode Period bit 0 mask. */ -#define WDT_WPER0_bp 2 /* Windowed Mode Period bit 0 position. */ -#define WDT_WPER1_bm (1<<3) /* Windowed Mode Period bit 1 mask. */ -#define WDT_WPER1_bp 3 /* Windowed Mode Period bit 1 position. */ -#define WDT_WPER2_bm (1<<4) /* Windowed Mode Period bit 2 mask. */ -#define WDT_WPER2_bp 4 /* Windowed Mode Period bit 2 position. */ -#define WDT_WPER3_bm (1<<5) /* Windowed Mode Period bit 3 mask. */ -#define WDT_WPER3_bp 5 /* Windowed Mode Period bit 3 position. */ - -#define WDT_WEN_bm 0x02 /* Windowed Mode Enable bit mask. */ -#define WDT_WEN_bp 1 /* Windowed Mode Enable bit position. */ - -#define WDT_WCEN_bm 0x01 /* Windowed Mode Change Enable bit mask. */ -#define WDT_WCEN_bp 0 /* Windowed Mode Change Enable bit position. */ - - -/* WDT.STATUS bit masks and bit positions */ -#define WDT_SYNCBUSY_bm 0x01 /* Syncronization busy bit mask. */ -#define WDT_SYNCBUSY_bp 0 /* Syncronization busy bit position. */ - - -/* MCU - MCU Control */ -/* MCU.MCUCR bit masks and bit positions */ -#define MCU_JTAGD_bm 0x01 /* JTAG Disable bit mask. */ -#define MCU_JTAGD_bp 0 /* JTAG Disable bit position. */ - - -/* MCU.EVSYSLOCK bit masks and bit positions */ -#define MCU_EVSYS1LOCK_bm 0x10 /* Event Channel 4-7 Lock bit mask. */ -#define MCU_EVSYS1LOCK_bp 4 /* Event Channel 4-7 Lock bit position. */ - -#define MCU_EVSYS0LOCK_bm 0x01 /* Event Channel 0-3 Lock bit mask. */ -#define MCU_EVSYS0LOCK_bp 0 /* Event Channel 0-3 Lock bit position. */ - - -/* MCU.AWEXLOCK bit masks and bit positions */ -#define MCU_AWEXELOCK_bm 0x04 /* AWeX on T/C E0 Lock bit mask. */ -#define MCU_AWEXELOCK_bp 2 /* AWeX on T/C E0 Lock bit position. */ - -#define MCU_AWEXCLOCK_bm 0x01 /* AWeX on T/C C0 Lock bit mask. */ -#define MCU_AWEXCLOCK_bp 0 /* AWeX on T/C C0 Lock bit position. */ - - -/* PMIC - Programmable Multi-level Interrupt Controller */ -/* PMIC.STATUS bit masks and bit positions */ -#define PMIC_NMIEX_bm 0x80 /* Non-maskable Interrupt Executing bit mask. */ -#define PMIC_NMIEX_bp 7 /* Non-maskable Interrupt Executing bit position. */ - -#define PMIC_HILVLEX_bm 0x04 /* High Level Interrupt Executing bit mask. */ -#define PMIC_HILVLEX_bp 2 /* High Level Interrupt Executing bit position. */ - -#define PMIC_MEDLVLEX_bm 0x02 /* Medium Level Interrupt Executing bit mask. */ -#define PMIC_MEDLVLEX_bp 1 /* Medium Level Interrupt Executing bit position. */ - -#define PMIC_LOLVLEX_bm 0x01 /* Low Level Interrupt Executing bit mask. */ -#define PMIC_LOLVLEX_bp 0 /* Low Level Interrupt Executing bit position. */ - - -/* PMIC.CTRL bit masks and bit positions */ -#define PMIC_RREN_bm 0x80 /* Round-Robin Priority Enable bit mask. */ -#define PMIC_RREN_bp 7 /* Round-Robin Priority Enable bit position. */ - -#define PMIC_IVSEL_bm 0x40 /* Interrupt Vector Select bit mask. */ -#define PMIC_IVSEL_bp 6 /* Interrupt Vector Select bit position. */ - -#define PMIC_HILVLEN_bm 0x04 /* High Level Enable bit mask. */ -#define PMIC_HILVLEN_bp 2 /* High Level Enable bit position. */ - -#define PMIC_MEDLVLEN_bm 0x02 /* Medium Level Enable bit mask. */ -#define PMIC_MEDLVLEN_bp 1 /* Medium Level Enable bit position. */ - -#define PMIC_LOLVLEN_bm 0x01 /* Low Level Enable bit mask. */ -#define PMIC_LOLVLEN_bp 0 /* Low Level Enable bit position. */ - - -/* DMA - DMA Controller */ -/* DMA_CH.CTRLA bit masks and bit positions */ -#define DMA_CH_ENABLE_bm 0x80 /* Channel Enable bit mask. */ -#define DMA_CH_ENABLE_bp 7 /* Channel Enable bit position. */ - -#define DMA_CH_RESET_bm 0x40 /* Channel Software Reset bit mask. */ -#define DMA_CH_RESET_bp 6 /* Channel Software Reset bit position. */ - -#define DMA_CH_REPEAT_bm 0x20 /* Channel Repeat Mode bit mask. */ -#define DMA_CH_REPEAT_bp 5 /* Channel Repeat Mode bit position. */ - -#define DMA_CH_TRFREQ_bm 0x10 /* Channel Transfer Request bit mask. */ -#define DMA_CH_TRFREQ_bp 4 /* Channel Transfer Request bit position. */ - -#define DMA_CH_SINGLE_bm 0x04 /* Channel Single Shot Data Transfer bit mask. */ -#define DMA_CH_SINGLE_bp 2 /* Channel Single Shot Data Transfer bit position. */ - -#define DMA_CH_BURSTLEN_gm 0x03 /* Channel Transfer Mode group mask. */ -#define DMA_CH_BURSTLEN_gp 0 /* Channel Transfer Mode group position. */ -#define DMA_CH_BURSTLEN0_bm (1<<0) /* Channel Transfer Mode bit 0 mask. */ -#define DMA_CH_BURSTLEN0_bp 0 /* Channel Transfer Mode bit 0 position. */ -#define DMA_CH_BURSTLEN1_bm (1<<1) /* Channel Transfer Mode bit 1 mask. */ -#define DMA_CH_BURSTLEN1_bp 1 /* Channel Transfer Mode bit 1 position. */ - - -/* DMA_CH.CTRLB bit masks and bit positions */ -#define DMA_CH_CHBUSY_bm 0x80 /* Block Transfer Busy bit mask. */ -#define DMA_CH_CHBUSY_bp 7 /* Block Transfer Busy bit position. */ - -#define DMA_CH_CHPEND_bm 0x40 /* Block Transfer Pending bit mask. */ -#define DMA_CH_CHPEND_bp 6 /* Block Transfer Pending bit position. */ - -#define DMA_CH_ERRIF_bm 0x20 /* Block Transfer Error Interrupt Flag bit mask. */ -#define DMA_CH_ERRIF_bp 5 /* Block Transfer Error Interrupt Flag bit position. */ - -#define DMA_CH_TRNIF_bm 0x10 /* Transaction Complete Interrup Flag bit mask. */ -#define DMA_CH_TRNIF_bp 4 /* Transaction Complete Interrup Flag bit position. */ - -#define DMA_CH_ERRINTLVL_gm 0x0C /* Transfer Error Interrupt Level group mask. */ -#define DMA_CH_ERRINTLVL_gp 2 /* Transfer Error Interrupt Level group position. */ -#define DMA_CH_ERRINTLVL0_bm (1<<2) /* Transfer Error Interrupt Level bit 0 mask. */ -#define DMA_CH_ERRINTLVL0_bp 2 /* Transfer Error Interrupt Level bit 0 position. */ -#define DMA_CH_ERRINTLVL1_bm (1<<3) /* Transfer Error Interrupt Level bit 1 mask. */ -#define DMA_CH_ERRINTLVL1_bp 3 /* Transfer Error Interrupt Level bit 1 position. */ - -#define DMA_CH_TRNINTLVL_gm 0x03 /* Transaction Complete Interrupt Level group mask. */ -#define DMA_CH_TRNINTLVL_gp 0 /* Transaction Complete Interrupt Level group position. */ -#define DMA_CH_TRNINTLVL0_bm (1<<0) /* Transaction Complete Interrupt Level bit 0 mask. */ -#define DMA_CH_TRNINTLVL0_bp 0 /* Transaction Complete Interrupt Level bit 0 position. */ -#define DMA_CH_TRNINTLVL1_bm (1<<1) /* Transaction Complete Interrupt Level bit 1 mask. */ -#define DMA_CH_TRNINTLVL1_bp 1 /* Transaction Complete Interrupt Level bit 1 position. */ - - -/* DMA_CH.ADDRCTRL bit masks and bit positions */ -#define DMA_CH_SRCRELOAD_gm 0xC0 /* Channel Source Address Reload group mask. */ -#define DMA_CH_SRCRELOAD_gp 6 /* Channel Source Address Reload group position. */ -#define DMA_CH_SRCRELOAD0_bm (1<<6) /* Channel Source Address Reload bit 0 mask. */ -#define DMA_CH_SRCRELOAD0_bp 6 /* Channel Source Address Reload bit 0 position. */ -#define DMA_CH_SRCRELOAD1_bm (1<<7) /* Channel Source Address Reload bit 1 mask. */ -#define DMA_CH_SRCRELOAD1_bp 7 /* Channel Source Address Reload bit 1 position. */ - -#define DMA_CH_SRCDIR_gm 0x30 /* Channel Source Address Mode group mask. */ -#define DMA_CH_SRCDIR_gp 4 /* Channel Source Address Mode group position. */ -#define DMA_CH_SRCDIR0_bm (1<<4) /* Channel Source Address Mode bit 0 mask. */ -#define DMA_CH_SRCDIR0_bp 4 /* Channel Source Address Mode bit 0 position. */ -#define DMA_CH_SRCDIR1_bm (1<<5) /* Channel Source Address Mode bit 1 mask. */ -#define DMA_CH_SRCDIR1_bp 5 /* Channel Source Address Mode bit 1 position. */ - -#define DMA_CH_DESTRELOAD_gm 0x0C /* Channel Destination Address Reload group mask. */ -#define DMA_CH_DESTRELOAD_gp 2 /* Channel Destination Address Reload group position. */ -#define DMA_CH_DESTRELOAD0_bm (1<<2) /* Channel Destination Address Reload bit 0 mask. */ -#define DMA_CH_DESTRELOAD0_bp 2 /* Channel Destination Address Reload bit 0 position. */ -#define DMA_CH_DESTRELOAD1_bm (1<<3) /* Channel Destination Address Reload bit 1 mask. */ -#define DMA_CH_DESTRELOAD1_bp 3 /* Channel Destination Address Reload bit 1 position. */ - -#define DMA_CH_DESTDIR_gm 0x03 /* Channel Destination Address Mode group mask. */ -#define DMA_CH_DESTDIR_gp 0 /* Channel Destination Address Mode group position. */ -#define DMA_CH_DESTDIR0_bm (1<<0) /* Channel Destination Address Mode bit 0 mask. */ -#define DMA_CH_DESTDIR0_bp 0 /* Channel Destination Address Mode bit 0 position. */ -#define DMA_CH_DESTDIR1_bm (1<<1) /* Channel Destination Address Mode bit 1 mask. */ -#define DMA_CH_DESTDIR1_bp 1 /* Channel Destination Address Mode bit 1 position. */ - - -/* DMA_CH.TRIGSRC bit masks and bit positions */ -#define DMA_CH_TRIGSRC_gm 0xFF /* Channel Trigger Source group mask. */ -#define DMA_CH_TRIGSRC_gp 0 /* Channel Trigger Source group position. */ -#define DMA_CH_TRIGSRC0_bm (1<<0) /* Channel Trigger Source bit 0 mask. */ -#define DMA_CH_TRIGSRC0_bp 0 /* Channel Trigger Source bit 0 position. */ -#define DMA_CH_TRIGSRC1_bm (1<<1) /* Channel Trigger Source bit 1 mask. */ -#define DMA_CH_TRIGSRC1_bp 1 /* Channel Trigger Source bit 1 position. */ -#define DMA_CH_TRIGSRC2_bm (1<<2) /* Channel Trigger Source bit 2 mask. */ -#define DMA_CH_TRIGSRC2_bp 2 /* Channel Trigger Source bit 2 position. */ -#define DMA_CH_TRIGSRC3_bm (1<<3) /* Channel Trigger Source bit 3 mask. */ -#define DMA_CH_TRIGSRC3_bp 3 /* Channel Trigger Source bit 3 position. */ -#define DMA_CH_TRIGSRC4_bm (1<<4) /* Channel Trigger Source bit 4 mask. */ -#define DMA_CH_TRIGSRC4_bp 4 /* Channel Trigger Source bit 4 position. */ -#define DMA_CH_TRIGSRC5_bm (1<<5) /* Channel Trigger Source bit 5 mask. */ -#define DMA_CH_TRIGSRC5_bp 5 /* Channel Trigger Source bit 5 position. */ -#define DMA_CH_TRIGSRC6_bm (1<<6) /* Channel Trigger Source bit 6 mask. */ -#define DMA_CH_TRIGSRC6_bp 6 /* Channel Trigger Source bit 6 position. */ -#define DMA_CH_TRIGSRC7_bm (1<<7) /* Channel Trigger Source bit 7 mask. */ -#define DMA_CH_TRIGSRC7_bp 7 /* Channel Trigger Source bit 7 position. */ - - -/* DMA.CTRL bit masks and bit positions */ -#define DMA_ENABLE_bm 0x80 /* Enable bit mask. */ -#define DMA_ENABLE_bp 7 /* Enable bit position. */ - -#define DMA_RESET_bm 0x40 /* Software Reset bit mask. */ -#define DMA_RESET_bp 6 /* Software Reset bit position. */ - -#define DMA_DBUFMODE_gm 0x0C /* Double Buffering Mode group mask. */ -#define DMA_DBUFMODE_gp 2 /* Double Buffering Mode group position. */ -#define DMA_DBUFMODE0_bm (1<<2) /* Double Buffering Mode bit 0 mask. */ -#define DMA_DBUFMODE0_bp 2 /* Double Buffering Mode bit 0 position. */ -#define DMA_DBUFMODE1_bm (1<<3) /* Double Buffering Mode bit 1 mask. */ -#define DMA_DBUFMODE1_bp 3 /* Double Buffering Mode bit 1 position. */ - -#define DMA_PRIMODE_gm 0x03 /* Channel Priority Mode group mask. */ -#define DMA_PRIMODE_gp 0 /* Channel Priority Mode group position. */ -#define DMA_PRIMODE0_bm (1<<0) /* Channel Priority Mode bit 0 mask. */ -#define DMA_PRIMODE0_bp 0 /* Channel Priority Mode bit 0 position. */ -#define DMA_PRIMODE1_bm (1<<1) /* Channel Priority Mode bit 1 mask. */ -#define DMA_PRIMODE1_bp 1 /* Channel Priority Mode bit 1 position. */ - - -/* DMA.INTFLAGS bit masks and bit positions */ -#define DMA_CH3ERRIF_bm 0x80 /* Channel 3 Block Transfer Error Interrupt Flag bit mask. */ -#define DMA_CH3ERRIF_bp 7 /* Channel 3 Block Transfer Error Interrupt Flag bit position. */ - -#define DMA_CH2ERRIF_bm 0x40 /* Channel 2 Block Transfer Error Interrupt Flag bit mask. */ -#define DMA_CH2ERRIF_bp 6 /* Channel 2 Block Transfer Error Interrupt Flag bit position. */ - -#define DMA_CH1ERRIF_bm 0x20 /* Channel 1 Block Transfer Error Interrupt Flag bit mask. */ -#define DMA_CH1ERRIF_bp 5 /* Channel 1 Block Transfer Error Interrupt Flag bit position. */ - -#define DMA_CH0ERRIF_bm 0x10 /* Channel 0 Block Transfer Error Interrupt Flag bit mask. */ -#define DMA_CH0ERRIF_bp 4 /* Channel 0 Block Transfer Error Interrupt Flag bit position. */ - -#define DMA_CH3TRNIF_bm 0x08 /* Channel 3 Transaction Complete Interrupt Flag bit mask. */ -#define DMA_CH3TRNIF_bp 3 /* Channel 3 Transaction Complete Interrupt Flag bit position. */ - -#define DMA_CH2TRNIF_bm 0x04 /* Channel 2 Transaction Complete Interrupt Flag bit mask. */ -#define DMA_CH2TRNIF_bp 2 /* Channel 2 Transaction Complete Interrupt Flag bit position. */ - -#define DMA_CH1TRNIF_bm 0x02 /* Channel 1 Transaction Complete Interrupt Flag bit mask. */ -#define DMA_CH1TRNIF_bp 1 /* Channel 1 Transaction Complete Interrupt Flag bit position. */ - -#define DMA_CH0TRNIF_bm 0x01 /* Channel 0 Transaction Complete Interrupt Flag bit mask. */ -#define DMA_CH0TRNIF_bp 0 /* Channel 0 Transaction Complete Interrupt Flag bit position. */ - - -/* DMA.STATUS bit masks and bit positions */ -#define DMA_CH3BUSY_bm 0x80 /* Channel 3 Block Transfer Busy bit mask. */ -#define DMA_CH3BUSY_bp 7 /* Channel 3 Block Transfer Busy bit position. */ - -#define DMA_CH2BUSY_bm 0x40 /* Channel 2 Block Transfer Busy bit mask. */ -#define DMA_CH2BUSY_bp 6 /* Channel 2 Block Transfer Busy bit position. */ - -#define DMA_CH1BUSY_bm 0x20 /* Channel 1 Block Transfer Busy bit mask. */ -#define DMA_CH1BUSY_bp 5 /* Channel 1 Block Transfer Busy bit position. */ - -#define DMA_CH0BUSY_bm 0x10 /* Channel 0 Block Transfer Busy bit mask. */ -#define DMA_CH0BUSY_bp 4 /* Channel 0 Block Transfer Busy bit position. */ - -#define DMA_CH3PEND_bm 0x08 /* Channel 3 Block Transfer Pending bit mask. */ -#define DMA_CH3PEND_bp 3 /* Channel 3 Block Transfer Pending bit position. */ - -#define DMA_CH2PEND_bm 0x04 /* Channel 2 Block Transfer Pending bit mask. */ -#define DMA_CH2PEND_bp 2 /* Channel 2 Block Transfer Pending bit position. */ - -#define DMA_CH1PEND_bm 0x02 /* Channel 1 Block Transfer Pending bit mask. */ -#define DMA_CH1PEND_bp 1 /* Channel 1 Block Transfer Pending bit position. */ - -#define DMA_CH0PEND_bm 0x01 /* Channel 0 Block Transfer Pending bit mask. */ -#define DMA_CH0PEND_bp 0 /* Channel 0 Block Transfer Pending bit position. */ - - -/* EVSYS - Event System */ -/* EVSYS.CH0MUX bit masks and bit positions */ -#define EVSYS_CHMUX_gm 0xFF /* Event Channel 0 Multiplexer group mask. */ -#define EVSYS_CHMUX_gp 0 /* Event Channel 0 Multiplexer group position. */ -#define EVSYS_CHMUX0_bm (1<<0) /* Event Channel 0 Multiplexer bit 0 mask. */ -#define EVSYS_CHMUX0_bp 0 /* Event Channel 0 Multiplexer bit 0 position. */ -#define EVSYS_CHMUX1_bm (1<<1) /* Event Channel 0 Multiplexer bit 1 mask. */ -#define EVSYS_CHMUX1_bp 1 /* Event Channel 0 Multiplexer bit 1 position. */ -#define EVSYS_CHMUX2_bm (1<<2) /* Event Channel 0 Multiplexer bit 2 mask. */ -#define EVSYS_CHMUX2_bp 2 /* Event Channel 0 Multiplexer bit 2 position. */ -#define EVSYS_CHMUX3_bm (1<<3) /* Event Channel 0 Multiplexer bit 3 mask. */ -#define EVSYS_CHMUX3_bp 3 /* Event Channel 0 Multiplexer bit 3 position. */ -#define EVSYS_CHMUX4_bm (1<<4) /* Event Channel 0 Multiplexer bit 4 mask. */ -#define EVSYS_CHMUX4_bp 4 /* Event Channel 0 Multiplexer bit 4 position. */ -#define EVSYS_CHMUX5_bm (1<<5) /* Event Channel 0 Multiplexer bit 5 mask. */ -#define EVSYS_CHMUX5_bp 5 /* Event Channel 0 Multiplexer bit 5 position. */ -#define EVSYS_CHMUX6_bm (1<<6) /* Event Channel 0 Multiplexer bit 6 mask. */ -#define EVSYS_CHMUX6_bp 6 /* Event Channel 0 Multiplexer bit 6 position. */ -#define EVSYS_CHMUX7_bm (1<<7) /* Event Channel 0 Multiplexer bit 7 mask. */ -#define EVSYS_CHMUX7_bp 7 /* Event Channel 0 Multiplexer bit 7 position. */ - - -/* EVSYS.CH1MUX bit masks and bit positions */ -/* EVSYS_CHMUX_gm Predefined. */ -/* EVSYS_CHMUX_gp Predefined. */ -/* EVSYS_CHMUX0_bm Predefined. */ -/* EVSYS_CHMUX0_bp Predefined. */ -/* EVSYS_CHMUX1_bm Predefined. */ -/* EVSYS_CHMUX1_bp Predefined. */ -/* EVSYS_CHMUX2_bm Predefined. */ -/* EVSYS_CHMUX2_bp Predefined. */ -/* EVSYS_CHMUX3_bm Predefined. */ -/* EVSYS_CHMUX3_bp Predefined. */ -/* EVSYS_CHMUX4_bm Predefined. */ -/* EVSYS_CHMUX4_bp Predefined. */ -/* EVSYS_CHMUX5_bm Predefined. */ -/* EVSYS_CHMUX5_bp Predefined. */ -/* EVSYS_CHMUX6_bm Predefined. */ -/* EVSYS_CHMUX6_bp Predefined. */ -/* EVSYS_CHMUX7_bm Predefined. */ -/* EVSYS_CHMUX7_bp Predefined. */ - - -/* EVSYS.CH2MUX bit masks and bit positions */ -/* EVSYS_CHMUX_gm Predefined. */ -/* EVSYS_CHMUX_gp Predefined. */ -/* EVSYS_CHMUX0_bm Predefined. */ -/* EVSYS_CHMUX0_bp Predefined. */ -/* EVSYS_CHMUX1_bm Predefined. */ -/* EVSYS_CHMUX1_bp Predefined. */ -/* EVSYS_CHMUX2_bm Predefined. */ -/* EVSYS_CHMUX2_bp Predefined. */ -/* EVSYS_CHMUX3_bm Predefined. */ -/* EVSYS_CHMUX3_bp Predefined. */ -/* EVSYS_CHMUX4_bm Predefined. */ -/* EVSYS_CHMUX4_bp Predefined. */ -/* EVSYS_CHMUX5_bm Predefined. */ -/* EVSYS_CHMUX5_bp Predefined. */ -/* EVSYS_CHMUX6_bm Predefined. */ -/* EVSYS_CHMUX6_bp Predefined. */ -/* EVSYS_CHMUX7_bm Predefined. */ -/* EVSYS_CHMUX7_bp Predefined. */ - - -/* EVSYS.CH3MUX bit masks and bit positions */ -/* EVSYS_CHMUX_gm Predefined. */ -/* EVSYS_CHMUX_gp Predefined. */ -/* EVSYS_CHMUX0_bm Predefined. */ -/* EVSYS_CHMUX0_bp Predefined. */ -/* EVSYS_CHMUX1_bm Predefined. */ -/* EVSYS_CHMUX1_bp Predefined. */ -/* EVSYS_CHMUX2_bm Predefined. */ -/* EVSYS_CHMUX2_bp Predefined. */ -/* EVSYS_CHMUX3_bm Predefined. */ -/* EVSYS_CHMUX3_bp Predefined. */ -/* EVSYS_CHMUX4_bm Predefined. */ -/* EVSYS_CHMUX4_bp Predefined. */ -/* EVSYS_CHMUX5_bm Predefined. */ -/* EVSYS_CHMUX5_bp Predefined. */ -/* EVSYS_CHMUX6_bm Predefined. */ -/* EVSYS_CHMUX6_bp Predefined. */ -/* EVSYS_CHMUX7_bm Predefined. */ -/* EVSYS_CHMUX7_bp Predefined. */ - - -/* EVSYS.CH4MUX bit masks and bit positions */ -/* EVSYS_CHMUX_gm Predefined. */ -/* EVSYS_CHMUX_gp Predefined. */ -/* EVSYS_CHMUX0_bm Predefined. */ -/* EVSYS_CHMUX0_bp Predefined. */ -/* EVSYS_CHMUX1_bm Predefined. */ -/* EVSYS_CHMUX1_bp Predefined. */ -/* EVSYS_CHMUX2_bm Predefined. */ -/* EVSYS_CHMUX2_bp Predefined. */ -/* EVSYS_CHMUX3_bm Predefined. */ -/* EVSYS_CHMUX3_bp Predefined. */ -/* EVSYS_CHMUX4_bm Predefined. */ -/* EVSYS_CHMUX4_bp Predefined. */ -/* EVSYS_CHMUX5_bm Predefined. */ -/* EVSYS_CHMUX5_bp Predefined. */ -/* EVSYS_CHMUX6_bm Predefined. */ -/* EVSYS_CHMUX6_bp Predefined. */ -/* EVSYS_CHMUX7_bm Predefined. */ -/* EVSYS_CHMUX7_bp Predefined. */ - - -/* EVSYS.CH5MUX bit masks and bit positions */ -/* EVSYS_CHMUX_gm Predefined. */ -/* EVSYS_CHMUX_gp Predefined. */ -/* EVSYS_CHMUX0_bm Predefined. */ -/* EVSYS_CHMUX0_bp Predefined. */ -/* EVSYS_CHMUX1_bm Predefined. */ -/* EVSYS_CHMUX1_bp Predefined. */ -/* EVSYS_CHMUX2_bm Predefined. */ -/* EVSYS_CHMUX2_bp Predefined. */ -/* EVSYS_CHMUX3_bm Predefined. */ -/* EVSYS_CHMUX3_bp Predefined. */ -/* EVSYS_CHMUX4_bm Predefined. */ -/* EVSYS_CHMUX4_bp Predefined. */ -/* EVSYS_CHMUX5_bm Predefined. */ -/* EVSYS_CHMUX5_bp Predefined. */ -/* EVSYS_CHMUX6_bm Predefined. */ -/* EVSYS_CHMUX6_bp Predefined. */ -/* EVSYS_CHMUX7_bm Predefined. */ -/* EVSYS_CHMUX7_bp Predefined. */ - - -/* EVSYS.CH6MUX bit masks and bit positions */ -/* EVSYS_CHMUX_gm Predefined. */ -/* EVSYS_CHMUX_gp Predefined. */ -/* EVSYS_CHMUX0_bm Predefined. */ -/* EVSYS_CHMUX0_bp Predefined. */ -/* EVSYS_CHMUX1_bm Predefined. */ -/* EVSYS_CHMUX1_bp Predefined. */ -/* EVSYS_CHMUX2_bm Predefined. */ -/* EVSYS_CHMUX2_bp Predefined. */ -/* EVSYS_CHMUX3_bm Predefined. */ -/* EVSYS_CHMUX3_bp Predefined. */ -/* EVSYS_CHMUX4_bm Predefined. */ -/* EVSYS_CHMUX4_bp Predefined. */ -/* EVSYS_CHMUX5_bm Predefined. */ -/* EVSYS_CHMUX5_bp Predefined. */ -/* EVSYS_CHMUX6_bm Predefined. */ -/* EVSYS_CHMUX6_bp Predefined. */ -/* EVSYS_CHMUX7_bm Predefined. */ -/* EVSYS_CHMUX7_bp Predefined. */ - - -/* EVSYS.CH7MUX bit masks and bit positions */ -/* EVSYS_CHMUX_gm Predefined. */ -/* EVSYS_CHMUX_gp Predefined. */ -/* EVSYS_CHMUX0_bm Predefined. */ -/* EVSYS_CHMUX0_bp Predefined. */ -/* EVSYS_CHMUX1_bm Predefined. */ -/* EVSYS_CHMUX1_bp Predefined. */ -/* EVSYS_CHMUX2_bm Predefined. */ -/* EVSYS_CHMUX2_bp Predefined. */ -/* EVSYS_CHMUX3_bm Predefined. */ -/* EVSYS_CHMUX3_bp Predefined. */ -/* EVSYS_CHMUX4_bm Predefined. */ -/* EVSYS_CHMUX4_bp Predefined. */ -/* EVSYS_CHMUX5_bm Predefined. */ -/* EVSYS_CHMUX5_bp Predefined. */ -/* EVSYS_CHMUX6_bm Predefined. */ -/* EVSYS_CHMUX6_bp Predefined. */ -/* EVSYS_CHMUX7_bm Predefined. */ -/* EVSYS_CHMUX7_bp Predefined. */ - - -/* EVSYS.CH0CTRL bit masks and bit positions */ -#define EVSYS_QDIRM_gm 0x60 /* Quadrature Decoder Index Recognition Mode group mask. */ -#define EVSYS_QDIRM_gp 5 /* Quadrature Decoder Index Recognition Mode group position. */ -#define EVSYS_QDIRM0_bm (1<<5) /* Quadrature Decoder Index Recognition Mode bit 0 mask. */ -#define EVSYS_QDIRM0_bp 5 /* Quadrature Decoder Index Recognition Mode bit 0 position. */ -#define EVSYS_QDIRM1_bm (1<<6) /* Quadrature Decoder Index Recognition Mode bit 1 mask. */ -#define EVSYS_QDIRM1_bp 6 /* Quadrature Decoder Index Recognition Mode bit 1 position. */ - -#define EVSYS_QDIEN_bm 0x10 /* Quadrature Decoder Index Enable bit mask. */ -#define EVSYS_QDIEN_bp 4 /* Quadrature Decoder Index Enable bit position. */ - -#define EVSYS_QDEN_bm 0x08 /* Quadrature Decoder Enable bit mask. */ -#define EVSYS_QDEN_bp 3 /* Quadrature Decoder Enable bit position. */ - -#define EVSYS_DIGFILT_gm 0x07 /* Digital Filter group mask. */ -#define EVSYS_DIGFILT_gp 0 /* Digital Filter group position. */ -#define EVSYS_DIGFILT0_bm (1<<0) /* Digital Filter bit 0 mask. */ -#define EVSYS_DIGFILT0_bp 0 /* Digital Filter bit 0 position. */ -#define EVSYS_DIGFILT1_bm (1<<1) /* Digital Filter bit 1 mask. */ -#define EVSYS_DIGFILT1_bp 1 /* Digital Filter bit 1 position. */ -#define EVSYS_DIGFILT2_bm (1<<2) /* Digital Filter bit 2 mask. */ -#define EVSYS_DIGFILT2_bp 2 /* Digital Filter bit 2 position. */ - - -/* EVSYS.CH1CTRL bit masks and bit positions */ -/* EVSYS_DIGFILT_gm Predefined. */ -/* EVSYS_DIGFILT_gp Predefined. */ -/* EVSYS_DIGFILT0_bm Predefined. */ -/* EVSYS_DIGFILT0_bp Predefined. */ -/* EVSYS_DIGFILT1_bm Predefined. */ -/* EVSYS_DIGFILT1_bp Predefined. */ -/* EVSYS_DIGFILT2_bm Predefined. */ -/* EVSYS_DIGFILT2_bp Predefined. */ - - -/* EVSYS.CH2CTRL bit masks and bit positions */ -/* EVSYS_QDIRM_gm Predefined. */ -/* EVSYS_QDIRM_gp Predefined. */ -/* EVSYS_QDIRM0_bm Predefined. */ -/* EVSYS_QDIRM0_bp Predefined. */ -/* EVSYS_QDIRM1_bm Predefined. */ -/* EVSYS_QDIRM1_bp Predefined. */ - -/* EVSYS_QDIEN_bm Predefined. */ -/* EVSYS_QDIEN_bp Predefined. */ - -/* EVSYS_QDEN_bm Predefined. */ -/* EVSYS_QDEN_bp Predefined. */ - -/* EVSYS_DIGFILT_gm Predefined. */ -/* EVSYS_DIGFILT_gp Predefined. */ -/* EVSYS_DIGFILT0_bm Predefined. */ -/* EVSYS_DIGFILT0_bp Predefined. */ -/* EVSYS_DIGFILT1_bm Predefined. */ -/* EVSYS_DIGFILT1_bp Predefined. */ -/* EVSYS_DIGFILT2_bm Predefined. */ -/* EVSYS_DIGFILT2_bp Predefined. */ - - -/* EVSYS.CH3CTRL bit masks and bit positions */ -/* EVSYS_DIGFILT_gm Predefined. */ -/* EVSYS_DIGFILT_gp Predefined. */ -/* EVSYS_DIGFILT0_bm Predefined. */ -/* EVSYS_DIGFILT0_bp Predefined. */ -/* EVSYS_DIGFILT1_bm Predefined. */ -/* EVSYS_DIGFILT1_bp Predefined. */ -/* EVSYS_DIGFILT2_bm Predefined. */ -/* EVSYS_DIGFILT2_bp Predefined. */ - - -/* EVSYS.CH4CTRL bit masks and bit positions */ -/* EVSYS_QDIRM_gm Predefined. */ -/* EVSYS_QDIRM_gp Predefined. */ -/* EVSYS_QDIRM0_bm Predefined. */ -/* EVSYS_QDIRM0_bp Predefined. */ -/* EVSYS_QDIRM1_bm Predefined. */ -/* EVSYS_QDIRM1_bp Predefined. */ - -/* EVSYS_QDIEN_bm Predefined. */ -/* EVSYS_QDIEN_bp Predefined. */ - -/* EVSYS_QDEN_bm Predefined. */ -/* EVSYS_QDEN_bp Predefined. */ - -/* EVSYS_DIGFILT_gm Predefined. */ -/* EVSYS_DIGFILT_gp Predefined. */ -/* EVSYS_DIGFILT0_bm Predefined. */ -/* EVSYS_DIGFILT0_bp Predefined. */ -/* EVSYS_DIGFILT1_bm Predefined. */ -/* EVSYS_DIGFILT1_bp Predefined. */ -/* EVSYS_DIGFILT2_bm Predefined. */ -/* EVSYS_DIGFILT2_bp Predefined. */ - - -/* EVSYS.CH5CTRL bit masks and bit positions */ -/* EVSYS_DIGFILT_gm Predefined. */ -/* EVSYS_DIGFILT_gp Predefined. */ -/* EVSYS_DIGFILT0_bm Predefined. */ -/* EVSYS_DIGFILT0_bp Predefined. */ -/* EVSYS_DIGFILT1_bm Predefined. */ -/* EVSYS_DIGFILT1_bp Predefined. */ -/* EVSYS_DIGFILT2_bm Predefined. */ -/* EVSYS_DIGFILT2_bp Predefined. */ - - -/* EVSYS.CH6CTRL bit masks and bit positions */ -/* EVSYS_DIGFILT_gm Predefined. */ -/* EVSYS_DIGFILT_gp Predefined. */ -/* EVSYS_DIGFILT0_bm Predefined. */ -/* EVSYS_DIGFILT0_bp Predefined. */ -/* EVSYS_DIGFILT1_bm Predefined. */ -/* EVSYS_DIGFILT1_bp Predefined. */ -/* EVSYS_DIGFILT2_bm Predefined. */ -/* EVSYS_DIGFILT2_bp Predefined. */ - - -/* EVSYS.CH7CTRL bit masks and bit positions */ -/* EVSYS_DIGFILT_gm Predefined. */ -/* EVSYS_DIGFILT_gp Predefined. */ -/* EVSYS_DIGFILT0_bm Predefined. */ -/* EVSYS_DIGFILT0_bp Predefined. */ -/* EVSYS_DIGFILT1_bm Predefined. */ -/* EVSYS_DIGFILT1_bp Predefined. */ -/* EVSYS_DIGFILT2_bm Predefined. */ -/* EVSYS_DIGFILT2_bp Predefined. */ - - -/* NVM - Non Volatile Memory Controller */ -/* NVM.CMD bit masks and bit positions */ -#define NVM_CMD_gm 0xFF /* Command group mask. */ -#define NVM_CMD_gp 0 /* Command group position. */ -#define NVM_CMD0_bm (1<<0) /* Command bit 0 mask. */ -#define NVM_CMD0_bp 0 /* Command bit 0 position. */ -#define NVM_CMD1_bm (1<<1) /* Command bit 1 mask. */ -#define NVM_CMD1_bp 1 /* Command bit 1 position. */ -#define NVM_CMD2_bm (1<<2) /* Command bit 2 mask. */ -#define NVM_CMD2_bp 2 /* Command bit 2 position. */ -#define NVM_CMD3_bm (1<<3) /* Command bit 3 mask. */ -#define NVM_CMD3_bp 3 /* Command bit 3 position. */ -#define NVM_CMD4_bm (1<<4) /* Command bit 4 mask. */ -#define NVM_CMD4_bp 4 /* Command bit 4 position. */ -#define NVM_CMD5_bm (1<<5) /* Command bit 5 mask. */ -#define NVM_CMD5_bp 5 /* Command bit 5 position. */ -#define NVM_CMD6_bm (1<<6) /* Command bit 6 mask. */ -#define NVM_CMD6_bp 6 /* Command bit 6 position. */ -#define NVM_CMD7_bm (1<<7) /* Command bit 7 mask. */ -#define NVM_CMD7_bp 7 /* Command bit 7 position. */ - - -/* NVM.CTRLA bit masks and bit positions */ -#define NVM_CMDEX_bm 0x01 /* Command Execute bit mask. */ -#define NVM_CMDEX_bp 0 /* Command Execute bit position. */ - - -/* NVM.CTRLB bit masks and bit positions */ -#define NVM_EEMAPEN_bm 0x08 /* EEPROM Mapping Enable bit mask. */ -#define NVM_EEMAPEN_bp 3 /* EEPROM Mapping Enable bit position. */ - -#define NVM_FPRM_bm 0x04 /* Flash Power Reduction Enable bit mask. */ -#define NVM_FPRM_bp 2 /* Flash Power Reduction Enable bit position. */ - -#define NVM_EPRM_bm 0x02 /* EEPROM Power Reduction Enable bit mask. */ -#define NVM_EPRM_bp 1 /* EEPROM Power Reduction Enable bit position. */ - -#define NVM_SPMLOCK_bm 0x01 /* SPM Lock bit mask. */ -#define NVM_SPMLOCK_bp 0 /* SPM Lock bit position. */ - - -/* NVM.INTCTRL bit masks and bit positions */ -#define NVM_SPMLVL_gm 0x0C /* SPM Interrupt Level group mask. */ -#define NVM_SPMLVL_gp 2 /* SPM Interrupt Level group position. */ -#define NVM_SPMLVL0_bm (1<<2) /* SPM Interrupt Level bit 0 mask. */ -#define NVM_SPMLVL0_bp 2 /* SPM Interrupt Level bit 0 position. */ -#define NVM_SPMLVL1_bm (1<<3) /* SPM Interrupt Level bit 1 mask. */ -#define NVM_SPMLVL1_bp 3 /* SPM Interrupt Level bit 1 position. */ - -#define NVM_EELVL_gm 0x03 /* EEPROM Interrupt Level group mask. */ -#define NVM_EELVL_gp 0 /* EEPROM Interrupt Level group position. */ -#define NVM_EELVL0_bm (1<<0) /* EEPROM Interrupt Level bit 0 mask. */ -#define NVM_EELVL0_bp 0 /* EEPROM Interrupt Level bit 0 position. */ -#define NVM_EELVL1_bm (1<<1) /* EEPROM Interrupt Level bit 1 mask. */ -#define NVM_EELVL1_bp 1 /* EEPROM Interrupt Level bit 1 position. */ - - -/* NVM.STATUS bit masks and bit positions */ -#define NVM_NVMBUSY_bm 0x80 /* Non-volatile Memory Busy bit mask. */ -#define NVM_NVMBUSY_bp 7 /* Non-volatile Memory Busy bit position. */ - -#define NVM_FBUSY_bm 0x40 /* Flash Memory Busy bit mask. */ -#define NVM_FBUSY_bp 6 /* Flash Memory Busy bit position. */ - -#define NVM_EELOAD_bm 0x02 /* EEPROM Page Buffer Active Loading bit mask. */ -#define NVM_EELOAD_bp 1 /* EEPROM Page Buffer Active Loading bit position. */ - -#define NVM_FLOAD_bm 0x01 /* Flash Page Buffer Active Loading bit mask. */ -#define NVM_FLOAD_bp 0 /* Flash Page Buffer Active Loading bit position. */ - - -/* NVM.LOCKBITS bit masks and bit positions */ -#define NVM_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ -#define NVM_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ -#define NVM_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ -#define NVM_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ -#define NVM_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ -#define NVM_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ - -#define NVM_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ -#define NVM_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ -#define NVM_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ -#define NVM_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ -#define NVM_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ -#define NVM_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ - -#define NVM_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ -#define NVM_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ -#define NVM_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ -#define NVM_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ -#define NVM_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ -#define NVM_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ - -#define NVM_LB_gm 0x03 /* Lock Bits group mask. */ -#define NVM_LB_gp 0 /* Lock Bits group position. */ -#define NVM_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ -#define NVM_LB0_bp 0 /* Lock Bits bit 0 position. */ -#define NVM_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ -#define NVM_LB1_bp 1 /* Lock Bits bit 1 position. */ - - -/* NVM_LOCKBITS.LOCKBITS bit masks and bit positions */ -#define NVM_LOCKBITS_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ -#define NVM_LOCKBITS_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ -#define NVM_LOCKBITS_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ -#define NVM_LOCKBITS_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ -#define NVM_LOCKBITS_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ -#define NVM_LOCKBITS_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ - -#define NVM_LOCKBITS_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ -#define NVM_LOCKBITS_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ -#define NVM_LOCKBITS_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ -#define NVM_LOCKBITS_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ -#define NVM_LOCKBITS_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ -#define NVM_LOCKBITS_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ - -#define NVM_LOCKBITS_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ -#define NVM_LOCKBITS_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ -#define NVM_LOCKBITS_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ -#define NVM_LOCKBITS_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ -#define NVM_LOCKBITS_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ -#define NVM_LOCKBITS_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ - -#define NVM_LOCKBITS_LB_gm 0x03 /* Lock Bits group mask. */ -#define NVM_LOCKBITS_LB_gp 0 /* Lock Bits group position. */ -#define NVM_LOCKBITS_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ -#define NVM_LOCKBITS_LB0_bp 0 /* Lock Bits bit 0 position. */ -#define NVM_LOCKBITS_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ -#define NVM_LOCKBITS_LB1_bp 1 /* Lock Bits bit 1 position. */ - - -/* NVM_FUSES.FUSEBYTE0 bit masks and bit positions */ -#define NVM_FUSES_JTAGUSERID_gm 0xFF /* JTAG User ID group mask. */ -#define NVM_FUSES_JTAGUSERID_gp 0 /* JTAG User ID group position. */ -#define NVM_FUSES_JTAGUSERID0_bm (1<<0) /* JTAG User ID bit 0 mask. */ -#define NVM_FUSES_JTAGUSERID0_bp 0 /* JTAG User ID bit 0 position. */ -#define NVM_FUSES_JTAGUSERID1_bm (1<<1) /* JTAG User ID bit 1 mask. */ -#define NVM_FUSES_JTAGUSERID1_bp 1 /* JTAG User ID bit 1 position. */ -#define NVM_FUSES_JTAGUSERID2_bm (1<<2) /* JTAG User ID bit 2 mask. */ -#define NVM_FUSES_JTAGUSERID2_bp 2 /* JTAG User ID bit 2 position. */ -#define NVM_FUSES_JTAGUSERID3_bm (1<<3) /* JTAG User ID bit 3 mask. */ -#define NVM_FUSES_JTAGUSERID3_bp 3 /* JTAG User ID bit 3 position. */ -#define NVM_FUSES_JTAGUSERID4_bm (1<<4) /* JTAG User ID bit 4 mask. */ -#define NVM_FUSES_JTAGUSERID4_bp 4 /* JTAG User ID bit 4 position. */ -#define NVM_FUSES_JTAGUSERID5_bm (1<<5) /* JTAG User ID bit 5 mask. */ -#define NVM_FUSES_JTAGUSERID5_bp 5 /* JTAG User ID bit 5 position. */ -#define NVM_FUSES_JTAGUSERID6_bm (1<<6) /* JTAG User ID bit 6 mask. */ -#define NVM_FUSES_JTAGUSERID6_bp 6 /* JTAG User ID bit 6 position. */ -#define NVM_FUSES_JTAGUSERID7_bm (1<<7) /* JTAG User ID bit 7 mask. */ -#define NVM_FUSES_JTAGUSERID7_bp 7 /* JTAG User ID bit 7 position. */ - - -/* NVM_FUSES.FUSEBYTE1 bit masks and bit positions */ -#define NVM_FUSES_WDWP_gm 0xF0 /* Watchdog Window Timeout Period group mask. */ -#define NVM_FUSES_WDWP_gp 4 /* Watchdog Window Timeout Period group position. */ -#define NVM_FUSES_WDWP0_bm (1<<4) /* Watchdog Window Timeout Period bit 0 mask. */ -#define NVM_FUSES_WDWP0_bp 4 /* Watchdog Window Timeout Period bit 0 position. */ -#define NVM_FUSES_WDWP1_bm (1<<5) /* Watchdog Window Timeout Period bit 1 mask. */ -#define NVM_FUSES_WDWP1_bp 5 /* Watchdog Window Timeout Period bit 1 position. */ -#define NVM_FUSES_WDWP2_bm (1<<6) /* Watchdog Window Timeout Period bit 2 mask. */ -#define NVM_FUSES_WDWP2_bp 6 /* Watchdog Window Timeout Period bit 2 position. */ -#define NVM_FUSES_WDWP3_bm (1<<7) /* Watchdog Window Timeout Period bit 3 mask. */ -#define NVM_FUSES_WDWP3_bp 7 /* Watchdog Window Timeout Period bit 3 position. */ - -#define NVM_FUSES_WDP_gm 0x0F /* Watchdog Timeout Period group mask. */ -#define NVM_FUSES_WDP_gp 0 /* Watchdog Timeout Period group position. */ -#define NVM_FUSES_WDP0_bm (1<<0) /* Watchdog Timeout Period bit 0 mask. */ -#define NVM_FUSES_WDP0_bp 0 /* Watchdog Timeout Period bit 0 position. */ -#define NVM_FUSES_WDP1_bm (1<<1) /* Watchdog Timeout Period bit 1 mask. */ -#define NVM_FUSES_WDP1_bp 1 /* Watchdog Timeout Period bit 1 position. */ -#define NVM_FUSES_WDP2_bm (1<<2) /* Watchdog Timeout Period bit 2 mask. */ -#define NVM_FUSES_WDP2_bp 2 /* Watchdog Timeout Period bit 2 position. */ -#define NVM_FUSES_WDP3_bm (1<<3) /* Watchdog Timeout Period bit 3 mask. */ -#define NVM_FUSES_WDP3_bp 3 /* Watchdog Timeout Period bit 3 position. */ - - -/* NVM_FUSES.FUSEBYTE2 bit masks and bit positions */ -#define NVM_FUSES_DVSDON_bm 0x80 /* Spike Detector Enable bit mask. */ -#define NVM_FUSES_DVSDON_bp 7 /* Spike Detector Enable bit position. */ - -#define NVM_FUSES_BOOTRST_bm 0x40 /* Boot Loader Section Reset Vector bit mask. */ -#define NVM_FUSES_BOOTRST_bp 6 /* Boot Loader Section Reset Vector bit position. */ - -#define NVM_FUSES_BODPD_gm 0x03 /* BOD Operation in Power-Down Mode group mask. */ -#define NVM_FUSES_BODPD_gp 0 /* BOD Operation in Power-Down Mode group position. */ -#define NVM_FUSES_BODPD0_bm (1<<0) /* BOD Operation in Power-Down Mode bit 0 mask. */ -#define NVM_FUSES_BODPD0_bp 0 /* BOD Operation in Power-Down Mode bit 0 position. */ -#define NVM_FUSES_BODPD1_bm (1<<1) /* BOD Operation in Power-Down Mode bit 1 mask. */ -#define NVM_FUSES_BODPD1_bp 1 /* BOD Operation in Power-Down Mode bit 1 position. */ - - -/* NVM_FUSES.FUSEBYTE4 bit masks and bit positions */ -#define NVM_FUSES_SUT_gm 0x0C /* Start-up Time group mask. */ -#define NVM_FUSES_SUT_gp 2 /* Start-up Time group position. */ -#define NVM_FUSES_SUT0_bm (1<<2) /* Start-up Time bit 0 mask. */ -#define NVM_FUSES_SUT0_bp 2 /* Start-up Time bit 0 position. */ -#define NVM_FUSES_SUT1_bm (1<<3) /* Start-up Time bit 1 mask. */ -#define NVM_FUSES_SUT1_bp 3 /* Start-up Time bit 1 position. */ - -#define NVM_FUSES_WDLOCK_bm 0x02 /* Watchdog Timer Lock bit mask. */ -#define NVM_FUSES_WDLOCK_bp 1 /* Watchdog Timer Lock bit position. */ - -#define NVM_FUSES_JTAGEN_bm 0x01 /* JTAG Interface Enable bit mask. */ -#define NVM_FUSES_JTAGEN_bp 0 /* JTAG Interface Enable bit position. */ - - -/* NVM_FUSES.FUSEBYTE5 bit masks and bit positions */ -#define NVM_FUSES_BODACT_gm 0x30 /* BOD Operation in Active Mode group mask. */ -#define NVM_FUSES_BODACT_gp 4 /* BOD Operation in Active Mode group position. */ -#define NVM_FUSES_BODACT0_bm (1<<4) /* BOD Operation in Active Mode bit 0 mask. */ -#define NVM_FUSES_BODACT0_bp 4 /* BOD Operation in Active Mode bit 0 position. */ -#define NVM_FUSES_BODACT1_bm (1<<5) /* BOD Operation in Active Mode bit 1 mask. */ -#define NVM_FUSES_BODACT1_bp 5 /* BOD Operation in Active Mode bit 1 position. */ - -#define NVM_FUSES_EESAVE_bm 0x08 /* Preserve EEPROM Through Chip Erase bit mask. */ -#define NVM_FUSES_EESAVE_bp 3 /* Preserve EEPROM Through Chip Erase bit position. */ - -#define NVM_FUSES_BODLVL_gm 0x07 /* Brown Out Detection Voltage Level group mask. */ -#define NVM_FUSES_BODLVL_gp 0 /* Brown Out Detection Voltage Level group position. */ -#define NVM_FUSES_BODLVL0_bm (1<<0) /* Brown Out Detection Voltage Level bit 0 mask. */ -#define NVM_FUSES_BODLVL0_bp 0 /* Brown Out Detection Voltage Level bit 0 position. */ -#define NVM_FUSES_BODLVL1_bm (1<<1) /* Brown Out Detection Voltage Level bit 1 mask. */ -#define NVM_FUSES_BODLVL1_bp 1 /* Brown Out Detection Voltage Level bit 1 position. */ -#define NVM_FUSES_BODLVL2_bm (1<<2) /* Brown Out Detection Voltage Level bit 2 mask. */ -#define NVM_FUSES_BODLVL2_bp 2 /* Brown Out Detection Voltage Level bit 2 position. */ - - -/* AC - Analog Comparator */ -/* AC.AC0CTRL bit masks and bit positions */ -#define AC_INTMODE_gm 0xC0 /* Interrupt Mode group mask. */ -#define AC_INTMODE_gp 6 /* Interrupt Mode group position. */ -#define AC_INTMODE0_bm (1<<6) /* Interrupt Mode bit 0 mask. */ -#define AC_INTMODE0_bp 6 /* Interrupt Mode bit 0 position. */ -#define AC_INTMODE1_bm (1<<7) /* Interrupt Mode bit 1 mask. */ -#define AC_INTMODE1_bp 7 /* Interrupt Mode bit 1 position. */ - -#define AC_INTLVL_gm 0x30 /* Interrupt Level group mask. */ -#define AC_INTLVL_gp 4 /* Interrupt Level group position. */ -#define AC_INTLVL0_bm (1<<4) /* Interrupt Level bit 0 mask. */ -#define AC_INTLVL0_bp 4 /* Interrupt Level bit 0 position. */ -#define AC_INTLVL1_bm (1<<5) /* Interrupt Level bit 1 mask. */ -#define AC_INTLVL1_bp 5 /* Interrupt Level bit 1 position. */ - -#define AC_HSMODE_bm 0x08 /* High-speed Mode bit mask. */ -#define AC_HSMODE_bp 3 /* High-speed Mode bit position. */ - -#define AC_HYSMODE_gm 0x06 /* Hysteresis Mode group mask. */ -#define AC_HYSMODE_gp 1 /* Hysteresis Mode group position. */ -#define AC_HYSMODE0_bm (1<<1) /* Hysteresis Mode bit 0 mask. */ -#define AC_HYSMODE0_bp 1 /* Hysteresis Mode bit 0 position. */ -#define AC_HYSMODE1_bm (1<<2) /* Hysteresis Mode bit 1 mask. */ -#define AC_HYSMODE1_bp 2 /* Hysteresis Mode bit 1 position. */ - -#define AC_ENABLE_bm 0x01 /* Enable bit mask. */ -#define AC_ENABLE_bp 0 /* Enable bit position. */ - - -/* AC.AC1CTRL bit masks and bit positions */ -/* AC_INTMODE_gm Predefined. */ -/* AC_INTMODE_gp Predefined. */ -/* AC_INTMODE0_bm Predefined. */ -/* AC_INTMODE0_bp Predefined. */ -/* AC_INTMODE1_bm Predefined. */ -/* AC_INTMODE1_bp Predefined. */ - -/* AC_INTLVL_gm Predefined. */ -/* AC_INTLVL_gp Predefined. */ -/* AC_INTLVL0_bm Predefined. */ -/* AC_INTLVL0_bp Predefined. */ -/* AC_INTLVL1_bm Predefined. */ -/* AC_INTLVL1_bp Predefined. */ - -/* AC_HSMODE_bm Predefined. */ -/* AC_HSMODE_bp Predefined. */ - -/* AC_HYSMODE_gm Predefined. */ -/* AC_HYSMODE_gp Predefined. */ -/* AC_HYSMODE0_bm Predefined. */ -/* AC_HYSMODE0_bp Predefined. */ -/* AC_HYSMODE1_bm Predefined. */ -/* AC_HYSMODE1_bp Predefined. */ - -/* AC_ENABLE_bm Predefined. */ -/* AC_ENABLE_bp Predefined. */ - - -/* AC.AC0MUXCTRL bit masks and bit positions */ -#define AC_MUXPOS_gm 0x38 /* MUX Positive Input group mask. */ -#define AC_MUXPOS_gp 3 /* MUX Positive Input group position. */ -#define AC_MUXPOS0_bm (1<<3) /* MUX Positive Input bit 0 mask. */ -#define AC_MUXPOS0_bp 3 /* MUX Positive Input bit 0 position. */ -#define AC_MUXPOS1_bm (1<<4) /* MUX Positive Input bit 1 mask. */ -#define AC_MUXPOS1_bp 4 /* MUX Positive Input bit 1 position. */ -#define AC_MUXPOS2_bm (1<<5) /* MUX Positive Input bit 2 mask. */ -#define AC_MUXPOS2_bp 5 /* MUX Positive Input bit 2 position. */ - -#define AC_MUXNEG_gm 0x07 /* MUX Negative Input group mask. */ -#define AC_MUXNEG_gp 0 /* MUX Negative Input group position. */ -#define AC_MUXNEG0_bm (1<<0) /* MUX Negative Input bit 0 mask. */ -#define AC_MUXNEG0_bp 0 /* MUX Negative Input bit 0 position. */ -#define AC_MUXNEG1_bm (1<<1) /* MUX Negative Input bit 1 mask. */ -#define AC_MUXNEG1_bp 1 /* MUX Negative Input bit 1 position. */ -#define AC_MUXNEG2_bm (1<<2) /* MUX Negative Input bit 2 mask. */ -#define AC_MUXNEG2_bp 2 /* MUX Negative Input bit 2 position. */ - - -/* AC.AC1MUXCTRL bit masks and bit positions */ -/* AC_MUXPOS_gm Predefined. */ -/* AC_MUXPOS_gp Predefined. */ -/* AC_MUXPOS0_bm Predefined. */ -/* AC_MUXPOS0_bp Predefined. */ -/* AC_MUXPOS1_bm Predefined. */ -/* AC_MUXPOS1_bp Predefined. */ -/* AC_MUXPOS2_bm Predefined. */ -/* AC_MUXPOS2_bp Predefined. */ - -/* AC_MUXNEG_gm Predefined. */ -/* AC_MUXNEG_gp Predefined. */ -/* AC_MUXNEG0_bm Predefined. */ -/* AC_MUXNEG0_bp Predefined. */ -/* AC_MUXNEG1_bm Predefined. */ -/* AC_MUXNEG1_bp Predefined. */ -/* AC_MUXNEG2_bm Predefined. */ -/* AC_MUXNEG2_bp Predefined. */ - - -/* AC.CTRLA bit masks and bit positions */ -#define AC_AC0OUT_bm 0x01 /* Comparator 0 Output Enable bit mask. */ -#define AC_AC0OUT_bp 0 /* Comparator 0 Output Enable bit position. */ - - -/* AC.CTRLB bit masks and bit positions */ -#define AC_SCALEFAC_gm 0x3F /* VCC Voltage Scaler Factor group mask. */ -#define AC_SCALEFAC_gp 0 /* VCC Voltage Scaler Factor group position. */ -#define AC_SCALEFAC0_bm (1<<0) /* VCC Voltage Scaler Factor bit 0 mask. */ -#define AC_SCALEFAC0_bp 0 /* VCC Voltage Scaler Factor bit 0 position. */ -#define AC_SCALEFAC1_bm (1<<1) /* VCC Voltage Scaler Factor bit 1 mask. */ -#define AC_SCALEFAC1_bp 1 /* VCC Voltage Scaler Factor bit 1 position. */ -#define AC_SCALEFAC2_bm (1<<2) /* VCC Voltage Scaler Factor bit 2 mask. */ -#define AC_SCALEFAC2_bp 2 /* VCC Voltage Scaler Factor bit 2 position. */ -#define AC_SCALEFAC3_bm (1<<3) /* VCC Voltage Scaler Factor bit 3 mask. */ -#define AC_SCALEFAC3_bp 3 /* VCC Voltage Scaler Factor bit 3 position. */ -#define AC_SCALEFAC4_bm (1<<4) /* VCC Voltage Scaler Factor bit 4 mask. */ -#define AC_SCALEFAC4_bp 4 /* VCC Voltage Scaler Factor bit 4 position. */ -#define AC_SCALEFAC5_bm (1<<5) /* VCC Voltage Scaler Factor bit 5 mask. */ -#define AC_SCALEFAC5_bp 5 /* VCC Voltage Scaler Factor bit 5 position. */ - - -/* AC.WINCTRL bit masks and bit positions */ -#define AC_WEN_bm 0x10 /* Window Mode Enable bit mask. */ -#define AC_WEN_bp 4 /* Window Mode Enable bit position. */ - -#define AC_WINTMODE_gm 0x0C /* Window Interrupt Mode group mask. */ -#define AC_WINTMODE_gp 2 /* Window Interrupt Mode group position. */ -#define AC_WINTMODE0_bm (1<<2) /* Window Interrupt Mode bit 0 mask. */ -#define AC_WINTMODE0_bp 2 /* Window Interrupt Mode bit 0 position. */ -#define AC_WINTMODE1_bm (1<<3) /* Window Interrupt Mode bit 1 mask. */ -#define AC_WINTMODE1_bp 3 /* Window Interrupt Mode bit 1 position. */ - -#define AC_WINTLVL_gm 0x03 /* Window Interrupt Level group mask. */ -#define AC_WINTLVL_gp 0 /* Window Interrupt Level group position. */ -#define AC_WINTLVL0_bm (1<<0) /* Window Interrupt Level bit 0 mask. */ -#define AC_WINTLVL0_bp 0 /* Window Interrupt Level bit 0 position. */ -#define AC_WINTLVL1_bm (1<<1) /* Window Interrupt Level bit 1 mask. */ -#define AC_WINTLVL1_bp 1 /* Window Interrupt Level bit 1 position. */ - - -/* AC.STATUS bit masks and bit positions */ -#define AC_WSTATE_gm 0xC0 /* Window Mode State group mask. */ -#define AC_WSTATE_gp 6 /* Window Mode State group position. */ -#define AC_WSTATE0_bm (1<<6) /* Window Mode State bit 0 mask. */ -#define AC_WSTATE0_bp 6 /* Window Mode State bit 0 position. */ -#define AC_WSTATE1_bm (1<<7) /* Window Mode State bit 1 mask. */ -#define AC_WSTATE1_bp 7 /* Window Mode State bit 1 position. */ - -#define AC_AC1STATE_bm 0x20 /* Comparator 1 State bit mask. */ -#define AC_AC1STATE_bp 5 /* Comparator 1 State bit position. */ - -#define AC_AC0STATE_bm 0x10 /* Comparator 0 State bit mask. */ -#define AC_AC0STATE_bp 4 /* Comparator 0 State bit position. */ - -#define AC_WIF_bm 0x04 /* Window Mode Interrupt Flag bit mask. */ -#define AC_WIF_bp 2 /* Window Mode Interrupt Flag bit position. */ - -#define AC_AC1IF_bm 0x02 /* Comparator 1 Interrupt Flag bit mask. */ -#define AC_AC1IF_bp 1 /* Comparator 1 Interrupt Flag bit position. */ - -#define AC_AC0IF_bm 0x01 /* Comparator 0 Interrupt Flag bit mask. */ -#define AC_AC0IF_bp 0 /* Comparator 0 Interrupt Flag bit position. */ - - -/* ADC - Analog/Digital Converter */ -/* ADC_CH.CTRL bit masks and bit positions */ -#define ADC_CH_START_bm 0x80 /* Channel Start Conversion bit mask. */ -#define ADC_CH_START_bp 7 /* Channel Start Conversion bit position. */ - -#define ADC_CH_GAINFAC_gm 0x1C /* Gain Factor group mask. */ -#define ADC_CH_GAINFAC_gp 2 /* Gain Factor group position. */ -#define ADC_CH_GAINFAC0_bm (1<<2) /* Gain Factor bit 0 mask. */ -#define ADC_CH_GAINFAC0_bp 2 /* Gain Factor bit 0 position. */ -#define ADC_CH_GAINFAC1_bm (1<<3) /* Gain Factor bit 1 mask. */ -#define ADC_CH_GAINFAC1_bp 3 /* Gain Factor bit 1 position. */ -#define ADC_CH_GAINFAC2_bm (1<<4) /* Gain Factor bit 2 mask. */ -#define ADC_CH_GAINFAC2_bp 4 /* Gain Factor bit 2 position. */ - -#define ADC_CH_INPUTMODE_gm 0x03 /* Input Mode Select group mask. */ -#define ADC_CH_INPUTMODE_gp 0 /* Input Mode Select group position. */ -#define ADC_CH_INPUTMODE0_bm (1<<0) /* Input Mode Select bit 0 mask. */ -#define ADC_CH_INPUTMODE0_bp 0 /* Input Mode Select bit 0 position. */ -#define ADC_CH_INPUTMODE1_bm (1<<1) /* Input Mode Select bit 1 mask. */ -#define ADC_CH_INPUTMODE1_bp 1 /* Input Mode Select bit 1 position. */ - - -/* ADC_CH.MUXCTRL bit masks and bit positions */ -#define ADC_CH_MUXPOS_gm 0x78 /* Positive Input Select group mask. */ -#define ADC_CH_MUXPOS_gp 3 /* Positive Input Select group position. */ -#define ADC_CH_MUXPOS0_bm (1<<3) /* Positive Input Select bit 0 mask. */ -#define ADC_CH_MUXPOS0_bp 3 /* Positive Input Select bit 0 position. */ -#define ADC_CH_MUXPOS1_bm (1<<4) /* Positive Input Select bit 1 mask. */ -#define ADC_CH_MUXPOS1_bp 4 /* Positive Input Select bit 1 position. */ -#define ADC_CH_MUXPOS2_bm (1<<5) /* Positive Input Select bit 2 mask. */ -#define ADC_CH_MUXPOS2_bp 5 /* Positive Input Select bit 2 position. */ -#define ADC_CH_MUXPOS3_bm (1<<6) /* Positive Input Select bit 3 mask. */ -#define ADC_CH_MUXPOS3_bp 6 /* Positive Input Select bit 3 position. */ - -#define ADC_CH_MUXINT_gm 0x78 /* Internal Input Select group mask. */ -#define ADC_CH_MUXINT_gp 3 /* Internal Input Select group position. */ -#define ADC_CH_MUXINT0_bm (1<<3) /* Internal Input Select bit 0 mask. */ -#define ADC_CH_MUXINT0_bp 3 /* Internal Input Select bit 0 position. */ -#define ADC_CH_MUXINT1_bm (1<<4) /* Internal Input Select bit 1 mask. */ -#define ADC_CH_MUXINT1_bp 4 /* Internal Input Select bit 1 position. */ -#define ADC_CH_MUXINT2_bm (1<<5) /* Internal Input Select bit 2 mask. */ -#define ADC_CH_MUXINT2_bp 5 /* Internal Input Select bit 2 position. */ -#define ADC_CH_MUXINT3_bm (1<<6) /* Internal Input Select bit 3 mask. */ -#define ADC_CH_MUXINT3_bp 6 /* Internal Input Select bit 3 position. */ - -#define ADC_CH_MUXNEG_gm 0x03 /* Negative Input Select group mask. */ -#define ADC_CH_MUXNEG_gp 0 /* Negative Input Select group position. */ -#define ADC_CH_MUXNEG0_bm (1<<0) /* Negative Input Select bit 0 mask. */ -#define ADC_CH_MUXNEG0_bp 0 /* Negative Input Select bit 0 position. */ -#define ADC_CH_MUXNEG1_bm (1<<1) /* Negative Input Select bit 1 mask. */ -#define ADC_CH_MUXNEG1_bp 1 /* Negative Input Select bit 1 position. */ - - -/* ADC_CH.INTCTRL bit masks and bit positions */ -#define ADC_CH_INTMODE_gm 0x0C /* Interrupt Mode group mask. */ -#define ADC_CH_INTMODE_gp 2 /* Interrupt Mode group position. */ -#define ADC_CH_INTMODE0_bm (1<<2) /* Interrupt Mode bit 0 mask. */ -#define ADC_CH_INTMODE0_bp 2 /* Interrupt Mode bit 0 position. */ -#define ADC_CH_INTMODE1_bm (1<<3) /* Interrupt Mode bit 1 mask. */ -#define ADC_CH_INTMODE1_bp 3 /* Interrupt Mode bit 1 position. */ - -#define ADC_CH_INTLVL_gm 0x03 /* Interrupt Level group mask. */ -#define ADC_CH_INTLVL_gp 0 /* Interrupt Level group position. */ -#define ADC_CH_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */ -#define ADC_CH_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */ -#define ADC_CH_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ -#define ADC_CH_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */ - - -/* ADC_CH.INTFLAGS bit masks and bit positions */ -#define ADC_CH_CHIF_bm 0x01 /* Channel Interrupt Flag bit mask. */ -#define ADC_CH_CHIF_bp 0 /* Channel Interrupt Flag bit position. */ - - -/* ADC.CTRLA bit masks and bit positions */ -#define ADC_DMASEL_gm 0xC0 /* DMA Selection group mask. */ -#define ADC_DMASEL_gp 6 /* DMA Selection group position. */ -#define ADC_DMASEL0_bm (1<<6) /* DMA Selection bit 0 mask. */ -#define ADC_DMASEL0_bp 6 /* DMA Selection bit 0 position. */ -#define ADC_DMASEL1_bm (1<<7) /* DMA Selection bit 1 mask. */ -#define ADC_DMASEL1_bp 7 /* DMA Selection bit 1 position. */ - -#define ADC_CH3START_bm 0x20 /* Channel 3 Start Conversion bit mask. */ -#define ADC_CH3START_bp 5 /* Channel 3 Start Conversion bit position. */ - -#define ADC_CH2START_bm 0x10 /* Channel 2 Start Conversion bit mask. */ -#define ADC_CH2START_bp 4 /* Channel 2 Start Conversion bit position. */ - -#define ADC_CH1START_bm 0x08 /* Channel 1 Start Conversion bit mask. */ -#define ADC_CH1START_bp 3 /* Channel 1 Start Conversion bit position. */ - -#define ADC_CH0START_bm 0x04 /* Channel 0 Start Conversion bit mask. */ -#define ADC_CH0START_bp 2 /* Channel 0 Start Conversion bit position. */ - -#define ADC_FLUSH_bm 0x02 /* Flush Pipeline bit mask. */ -#define ADC_FLUSH_bp 1 /* Flush Pipeline bit position. */ - -#define ADC_ENABLE_bm 0x01 /* Enable ADC bit mask. */ -#define ADC_ENABLE_bp 0 /* Enable ADC bit position. */ - - -/* ADC.CTRLB bit masks and bit positions */ -#define ADC_CONMODE_bm 0x10 /* Conversion Mode bit mask. */ -#define ADC_CONMODE_bp 4 /* Conversion Mode bit position. */ - -#define ADC_FREERUN_bm 0x08 /* Free Running Mode Enable bit mask. */ -#define ADC_FREERUN_bp 3 /* Free Running Mode Enable bit position. */ - -#define ADC_RESOLUTION_gm 0x06 /* Result Resolution group mask. */ -#define ADC_RESOLUTION_gp 1 /* Result Resolution group position. */ -#define ADC_RESOLUTION0_bm (1<<1) /* Result Resolution bit 0 mask. */ -#define ADC_RESOLUTION0_bp 1 /* Result Resolution bit 0 position. */ -#define ADC_RESOLUTION1_bm (1<<2) /* Result Resolution bit 1 mask. */ -#define ADC_RESOLUTION1_bp 2 /* Result Resolution bit 1 position. */ - - -/* ADC.REFCTRL bit masks and bit positions */ -#define ADC_REFSEL_gm 0x30 /* Reference Selection group mask. */ -#define ADC_REFSEL_gp 4 /* Reference Selection group position. */ -#define ADC_REFSEL0_bm (1<<4) /* Reference Selection bit 0 mask. */ -#define ADC_REFSEL0_bp 4 /* Reference Selection bit 0 position. */ -#define ADC_REFSEL1_bm (1<<5) /* Reference Selection bit 1 mask. */ -#define ADC_REFSEL1_bp 5 /* Reference Selection bit 1 position. */ - -#define ADC_BANDGAP_bm 0x02 /* Bandgap enable bit mask. */ -#define ADC_BANDGAP_bp 1 /* Bandgap enable bit position. */ - -#define ADC_TEMPREF_bm 0x01 /* Temperature Reference Enable bit mask. */ -#define ADC_TEMPREF_bp 0 /* Temperature Reference Enable bit position. */ - - -/* ADC.EVCTRL bit masks and bit positions */ -#define ADC_SWEEP_gm 0xC0 /* Channel Sweep Selection group mask. */ -#define ADC_SWEEP_gp 6 /* Channel Sweep Selection group position. */ -#define ADC_SWEEP0_bm (1<<6) /* Channel Sweep Selection bit 0 mask. */ -#define ADC_SWEEP0_bp 6 /* Channel Sweep Selection bit 0 position. */ -#define ADC_SWEEP1_bm (1<<7) /* Channel Sweep Selection bit 1 mask. */ -#define ADC_SWEEP1_bp 7 /* Channel Sweep Selection bit 1 position. */ - -#define ADC_EVSEL_gm 0x38 /* Event Input Select group mask. */ -#define ADC_EVSEL_gp 3 /* Event Input Select group position. */ -#define ADC_EVSEL0_bm (1<<3) /* Event Input Select bit 0 mask. */ -#define ADC_EVSEL0_bp 3 /* Event Input Select bit 0 position. */ -#define ADC_EVSEL1_bm (1<<4) /* Event Input Select bit 1 mask. */ -#define ADC_EVSEL1_bp 4 /* Event Input Select bit 1 position. */ -#define ADC_EVSEL2_bm (1<<5) /* Event Input Select bit 2 mask. */ -#define ADC_EVSEL2_bp 5 /* Event Input Select bit 2 position. */ - -#define ADC_EVACT_gm 0x07 /* Event Action Select group mask. */ -#define ADC_EVACT_gp 0 /* Event Action Select group position. */ -#define ADC_EVACT0_bm (1<<0) /* Event Action Select bit 0 mask. */ -#define ADC_EVACT0_bp 0 /* Event Action Select bit 0 position. */ -#define ADC_EVACT1_bm (1<<1) /* Event Action Select bit 1 mask. */ -#define ADC_EVACT1_bp 1 /* Event Action Select bit 1 position. */ -#define ADC_EVACT2_bm (1<<2) /* Event Action Select bit 2 mask. */ -#define ADC_EVACT2_bp 2 /* Event Action Select bit 2 position. */ - - -/* ADC.PRESCALER bit masks and bit positions */ -#define ADC_PRESCALER_gm 0x07 /* Clock Prescaler Selection group mask. */ -#define ADC_PRESCALER_gp 0 /* Clock Prescaler Selection group position. */ -#define ADC_PRESCALER0_bm (1<<0) /* Clock Prescaler Selection bit 0 mask. */ -#define ADC_PRESCALER0_bp 0 /* Clock Prescaler Selection bit 0 position. */ -#define ADC_PRESCALER1_bm (1<<1) /* Clock Prescaler Selection bit 1 mask. */ -#define ADC_PRESCALER1_bp 1 /* Clock Prescaler Selection bit 1 position. */ -#define ADC_PRESCALER2_bm (1<<2) /* Clock Prescaler Selection bit 2 mask. */ -#define ADC_PRESCALER2_bp 2 /* Clock Prescaler Selection bit 2 position. */ - - -/* ADC.INTFLAGS bit masks and bit positions */ -#define ADC_CH3IF_bm 0x08 /* Channel 3 Interrupt Flag bit mask. */ -#define ADC_CH3IF_bp 3 /* Channel 3 Interrupt Flag bit position. */ - -#define ADC_CH2IF_bm 0x04 /* Channel 2 Interrupt Flag bit mask. */ -#define ADC_CH2IF_bp 2 /* Channel 2 Interrupt Flag bit position. */ - -#define ADC_CH1IF_bm 0x02 /* Channel 1 Interrupt Flag bit mask. */ -#define ADC_CH1IF_bp 1 /* Channel 1 Interrupt Flag bit position. */ - -#define ADC_CH0IF_bm 0x01 /* Channel 0 Interrupt Flag bit mask. */ -#define ADC_CH0IF_bp 0 /* Channel 0 Interrupt Flag bit position. */ - - -/* DAC - Digital/Analog Converter */ -/* DAC.CTRLA bit masks and bit positions */ -#define DAC_IDOEN_bm 0x10 /* Internal Output Enable bit mask. */ -#define DAC_IDOEN_bp 4 /* Internal Output Enable bit position. */ - -#define DAC_CH1EN_bm 0x08 /* Channel 1 Output Enable bit mask. */ -#define DAC_CH1EN_bp 3 /* Channel 1 Output Enable bit position. */ - -#define DAC_CH0EN_bm 0x04 /* Channel 0 Output Enable bit mask. */ -#define DAC_CH0EN_bp 2 /* Channel 0 Output Enable bit position. */ - -#define DAC_LPMODE_bm 0x02 /* Low Power Mode bit mask. */ -#define DAC_LPMODE_bp 1 /* Low Power Mode bit position. */ - -#define DAC_ENABLE_bm 0x01 /* Enable bit mask. */ -#define DAC_ENABLE_bp 0 /* Enable bit position. */ - - -/* DAC.CTRLB bit masks and bit positions */ -#define DAC_CHSEL_gm 0x60 /* Channel Select group mask. */ -#define DAC_CHSEL_gp 5 /* Channel Select group position. */ -#define DAC_CHSEL0_bm (1<<5) /* Channel Select bit 0 mask. */ -#define DAC_CHSEL0_bp 5 /* Channel Select bit 0 position. */ -#define DAC_CHSEL1_bm (1<<6) /* Channel Select bit 1 mask. */ -#define DAC_CHSEL1_bp 6 /* Channel Select bit 1 position. */ - -#define DAC_CH1TRIG_bm 0x02 /* Channel 1 Event Trig Enable bit mask. */ -#define DAC_CH1TRIG_bp 1 /* Channel 1 Event Trig Enable bit position. */ - -#define DAC_CH0TRIG_bm 0x01 /* Channel 0 Event Trig Enable bit mask. */ -#define DAC_CH0TRIG_bp 0 /* Channel 0 Event Trig Enable bit position. */ - - -/* DAC.CTRLC bit masks and bit positions */ -#define DAC_REFSEL_gm 0x18 /* Reference Select group mask. */ -#define DAC_REFSEL_gp 3 /* Reference Select group position. */ -#define DAC_REFSEL0_bm (1<<3) /* Reference Select bit 0 mask. */ -#define DAC_REFSEL0_bp 3 /* Reference Select bit 0 position. */ -#define DAC_REFSEL1_bm (1<<4) /* Reference Select bit 1 mask. */ -#define DAC_REFSEL1_bp 4 /* Reference Select bit 1 position. */ - -#define DAC_LEFTADJ_bm 0x01 /* Left-adjust Result bit mask. */ -#define DAC_LEFTADJ_bp 0 /* Left-adjust Result bit position. */ - - -/* DAC.EVCTRL bit masks and bit positions */ -#define DAC_EVSEL_gm 0x07 /* Event Input Selection group mask. */ -#define DAC_EVSEL_gp 0 /* Event Input Selection group position. */ -#define DAC_EVSEL0_bm (1<<0) /* Event Input Selection bit 0 mask. */ -#define DAC_EVSEL0_bp 0 /* Event Input Selection bit 0 position. */ -#define DAC_EVSEL1_bm (1<<1) /* Event Input Selection bit 1 mask. */ -#define DAC_EVSEL1_bp 1 /* Event Input Selection bit 1 position. */ -#define DAC_EVSEL2_bm (1<<2) /* Event Input Selection bit 2 mask. */ -#define DAC_EVSEL2_bp 2 /* Event Input Selection bit 2 position. */ - - -/* DAC.TIMCTRL bit masks and bit positions */ -#define DAC_CONINTVAL_gm 0x70 /* Conversion Intercal group mask. */ -#define DAC_CONINTVAL_gp 4 /* Conversion Intercal group position. */ -#define DAC_CONINTVAL0_bm (1<<4) /* Conversion Intercal bit 0 mask. */ -#define DAC_CONINTVAL0_bp 4 /* Conversion Intercal bit 0 position. */ -#define DAC_CONINTVAL1_bm (1<<5) /* Conversion Intercal bit 1 mask. */ -#define DAC_CONINTVAL1_bp 5 /* Conversion Intercal bit 1 position. */ -#define DAC_CONINTVAL2_bm (1<<6) /* Conversion Intercal bit 2 mask. */ -#define DAC_CONINTVAL2_bp 6 /* Conversion Intercal bit 2 position. */ - -#define DAC_REFRESH_gm 0x0F /* Refresh Timing Control group mask. */ -#define DAC_REFRESH_gp 0 /* Refresh Timing Control group position. */ -#define DAC_REFRESH0_bm (1<<0) /* Refresh Timing Control bit 0 mask. */ -#define DAC_REFRESH0_bp 0 /* Refresh Timing Control bit 0 position. */ -#define DAC_REFRESH1_bm (1<<1) /* Refresh Timing Control bit 1 mask. */ -#define DAC_REFRESH1_bp 1 /* Refresh Timing Control bit 1 position. */ -#define DAC_REFRESH2_bm (1<<2) /* Refresh Timing Control bit 2 mask. */ -#define DAC_REFRESH2_bp 2 /* Refresh Timing Control bit 2 position. */ -#define DAC_REFRESH3_bm (1<<3) /* Refresh Timing Control bit 3 mask. */ -#define DAC_REFRESH3_bp 3 /* Refresh Timing Control bit 3 position. */ - - -/* DAC.STATUS bit masks and bit positions */ -#define DAC_CH1DRE_bm 0x02 /* Channel 1 Data Register Empty bit mask. */ -#define DAC_CH1DRE_bp 1 /* Channel 1 Data Register Empty bit position. */ - -#define DAC_CH0DRE_bm 0x01 /* Channel 0 Data Register Empty bit mask. */ -#define DAC_CH0DRE_bp 0 /* Channel 0 Data Register Empty bit position. */ - - -/* RTC - Real-Time Clounter */ -/* RTC.CTRL bit masks and bit positions */ -#define RTC_PRESCALER_gm 0x07 /* Prescaling Factor group mask. */ -#define RTC_PRESCALER_gp 0 /* Prescaling Factor group position. */ -#define RTC_PRESCALER0_bm (1<<0) /* Prescaling Factor bit 0 mask. */ -#define RTC_PRESCALER0_bp 0 /* Prescaling Factor bit 0 position. */ -#define RTC_PRESCALER1_bm (1<<1) /* Prescaling Factor bit 1 mask. */ -#define RTC_PRESCALER1_bp 1 /* Prescaling Factor bit 1 position. */ -#define RTC_PRESCALER2_bm (1<<2) /* Prescaling Factor bit 2 mask. */ -#define RTC_PRESCALER2_bp 2 /* Prescaling Factor bit 2 position. */ - - -/* RTC.STATUS bit masks and bit positions */ -#define RTC_SYNCBUSY_bm 0x01 /* Synchronization Busy Flag bit mask. */ -#define RTC_SYNCBUSY_bp 0 /* Synchronization Busy Flag bit position. */ - - -/* RTC.INTCTRL bit masks and bit positions */ -#define RTC_COMPINTLVL_gm 0x0C /* Compare Match Interrupt Level group mask. */ -#define RTC_COMPINTLVL_gp 2 /* Compare Match Interrupt Level group position. */ -#define RTC_COMPINTLVL0_bm (1<<2) /* Compare Match Interrupt Level bit 0 mask. */ -#define RTC_COMPINTLVL0_bp 2 /* Compare Match Interrupt Level bit 0 position. */ -#define RTC_COMPINTLVL1_bm (1<<3) /* Compare Match Interrupt Level bit 1 mask. */ -#define RTC_COMPINTLVL1_bp 3 /* Compare Match Interrupt Level bit 1 position. */ - -#define RTC_OVFINTLVL_gm 0x03 /* Overflow Interrupt Level group mask. */ -#define RTC_OVFINTLVL_gp 0 /* Overflow Interrupt Level group position. */ -#define RTC_OVFINTLVL0_bm (1<<0) /* Overflow Interrupt Level bit 0 mask. */ -#define RTC_OVFINTLVL0_bp 0 /* Overflow Interrupt Level bit 0 position. */ -#define RTC_OVFINTLVL1_bm (1<<1) /* Overflow Interrupt Level bit 1 mask. */ -#define RTC_OVFINTLVL1_bp 1 /* Overflow Interrupt Level bit 1 position. */ - - -/* RTC.INTFLAGS bit masks and bit positions */ -#define RTC_COMPIF_bm 0x02 /* Compare Match Interrupt Flag bit mask. */ -#define RTC_COMPIF_bp 1 /* Compare Match Interrupt Flag bit position. */ - -#define RTC_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ -#define RTC_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ - - -/* EBI - External Bus Interface */ -/* EBI_CS.CTRLA bit masks and bit positions */ -#define EBI_CS_ASIZE_gm 0x7C /* Address Size group mask. */ -#define EBI_CS_ASIZE_gp 2 /* Address Size group position. */ -#define EBI_CS_ASIZE0_bm (1<<2) /* Address Size bit 0 mask. */ -#define EBI_CS_ASIZE0_bp 2 /* Address Size bit 0 position. */ -#define EBI_CS_ASIZE1_bm (1<<3) /* Address Size bit 1 mask. */ -#define EBI_CS_ASIZE1_bp 3 /* Address Size bit 1 position. */ -#define EBI_CS_ASIZE2_bm (1<<4) /* Address Size bit 2 mask. */ -#define EBI_CS_ASIZE2_bp 4 /* Address Size bit 2 position. */ -#define EBI_CS_ASIZE3_bm (1<<5) /* Address Size bit 3 mask. */ -#define EBI_CS_ASIZE3_bp 5 /* Address Size bit 3 position. */ -#define EBI_CS_ASIZE4_bm (1<<6) /* Address Size bit 4 mask. */ -#define EBI_CS_ASIZE4_bp 6 /* Address Size bit 4 position. */ - -#define EBI_CS_MODE_gm 0x03 /* Memory Mode group mask. */ -#define EBI_CS_MODE_gp 0 /* Memory Mode group position. */ -#define EBI_CS_MODE0_bm (1<<0) /* Memory Mode bit 0 mask. */ -#define EBI_CS_MODE0_bp 0 /* Memory Mode bit 0 position. */ -#define EBI_CS_MODE1_bm (1<<1) /* Memory Mode bit 1 mask. */ -#define EBI_CS_MODE1_bp 1 /* Memory Mode bit 1 position. */ - - -/* EBI_CS.CTRLB bit masks and bit positions */ -#define EBI_CS_SRWS_gm 0x07 /* SRAM Wait State Cycles group mask. */ -#define EBI_CS_SRWS_gp 0 /* SRAM Wait State Cycles group position. */ -#define EBI_CS_SRWS0_bm (1<<0) /* SRAM Wait State Cycles bit 0 mask. */ -#define EBI_CS_SRWS0_bp 0 /* SRAM Wait State Cycles bit 0 position. */ -#define EBI_CS_SRWS1_bm (1<<1) /* SRAM Wait State Cycles bit 1 mask. */ -#define EBI_CS_SRWS1_bp 1 /* SRAM Wait State Cycles bit 1 position. */ -#define EBI_CS_SRWS2_bm (1<<2) /* SRAM Wait State Cycles bit 2 mask. */ -#define EBI_CS_SRWS2_bp 2 /* SRAM Wait State Cycles bit 2 position. */ - -#define EBI_CS_SDINITDONE_bm 0x80 /* SDRAM Initialization Done bit mask. */ -#define EBI_CS_SDINITDONE_bp 7 /* SDRAM Initialization Done bit position. */ - -#define EBI_CS_SDSREN_bm 0x04 /* SDRAM Self-refresh Enable bit mask. */ -#define EBI_CS_SDSREN_bp 2 /* SDRAM Self-refresh Enable bit position. */ - -#define EBI_CS_SDMODE_gm 0x03 /* SDRAM Mode group mask. */ -#define EBI_CS_SDMODE_gp 0 /* SDRAM Mode group position. */ -#define EBI_CS_SDMODE0_bm (1<<0) /* SDRAM Mode bit 0 mask. */ -#define EBI_CS_SDMODE0_bp 0 /* SDRAM Mode bit 0 position. */ -#define EBI_CS_SDMODE1_bm (1<<1) /* SDRAM Mode bit 1 mask. */ -#define EBI_CS_SDMODE1_bp 1 /* SDRAM Mode bit 1 position. */ - - -/* EBI.CTRL bit masks and bit positions */ -#define EBI_SDDATAW_gm 0xC0 /* SDRAM Data Width Setting group mask. */ -#define EBI_SDDATAW_gp 6 /* SDRAM Data Width Setting group position. */ -#define EBI_SDDATAW0_bm (1<<6) /* SDRAM Data Width Setting bit 0 mask. */ -#define EBI_SDDATAW0_bp 6 /* SDRAM Data Width Setting bit 0 position. */ -#define EBI_SDDATAW1_bm (1<<7) /* SDRAM Data Width Setting bit 1 mask. */ -#define EBI_SDDATAW1_bp 7 /* SDRAM Data Width Setting bit 1 position. */ - -#define EBI_LPCMODE_gm 0x30 /* SRAM LPC Mode group mask. */ -#define EBI_LPCMODE_gp 4 /* SRAM LPC Mode group position. */ -#define EBI_LPCMODE0_bm (1<<4) /* SRAM LPC Mode bit 0 mask. */ -#define EBI_LPCMODE0_bp 4 /* SRAM LPC Mode bit 0 position. */ -#define EBI_LPCMODE1_bm (1<<5) /* SRAM LPC Mode bit 1 mask. */ -#define EBI_LPCMODE1_bp 5 /* SRAM LPC Mode bit 1 position. */ - -#define EBI_SRMODE_gm 0x0C /* SRAM Mode group mask. */ -#define EBI_SRMODE_gp 2 /* SRAM Mode group position. */ -#define EBI_SRMODE0_bm (1<<2) /* SRAM Mode bit 0 mask. */ -#define EBI_SRMODE0_bp 2 /* SRAM Mode bit 0 position. */ -#define EBI_SRMODE1_bm (1<<3) /* SRAM Mode bit 1 mask. */ -#define EBI_SRMODE1_bp 3 /* SRAM Mode bit 1 position. */ - -#define EBI_IFMODE_gm 0x03 /* Interface Mode group mask. */ -#define EBI_IFMODE_gp 0 /* Interface Mode group position. */ -#define EBI_IFMODE0_bm (1<<0) /* Interface Mode bit 0 mask. */ -#define EBI_IFMODE0_bp 0 /* Interface Mode bit 0 position. */ -#define EBI_IFMODE1_bm (1<<1) /* Interface Mode bit 1 mask. */ -#define EBI_IFMODE1_bp 1 /* Interface Mode bit 1 position. */ - - -/* EBI.SDRAMCTRLA bit masks and bit positions */ -#define EBI_SDCAS_bm 0x08 /* SDRAM CAS Latency Setting bit mask. */ -#define EBI_SDCAS_bp 3 /* SDRAM CAS Latency Setting bit position. */ - -#define EBI_SDROW_bm 0x04 /* SDRAM ROW Bits Setting bit mask. */ -#define EBI_SDROW_bp 2 /* SDRAM ROW Bits Setting bit position. */ - -#define EBI_SDCOL_gm 0x03 /* SDRAM Column Bits Setting group mask. */ -#define EBI_SDCOL_gp 0 /* SDRAM Column Bits Setting group position. */ -#define EBI_SDCOL0_bm (1<<0) /* SDRAM Column Bits Setting bit 0 mask. */ -#define EBI_SDCOL0_bp 0 /* SDRAM Column Bits Setting bit 0 position. */ -#define EBI_SDCOL1_bm (1<<1) /* SDRAM Column Bits Setting bit 1 mask. */ -#define EBI_SDCOL1_bp 1 /* SDRAM Column Bits Setting bit 1 position. */ - - -/* EBI.SDRAMCTRLB bit masks and bit positions */ -#define EBI_MRDLY_gm 0xC0 /* SDRAM Mode Register Delay group mask. */ -#define EBI_MRDLY_gp 6 /* SDRAM Mode Register Delay group position. */ -#define EBI_MRDLY0_bm (1<<6) /* SDRAM Mode Register Delay bit 0 mask. */ -#define EBI_MRDLY0_bp 6 /* SDRAM Mode Register Delay bit 0 position. */ -#define EBI_MRDLY1_bm (1<<7) /* SDRAM Mode Register Delay bit 1 mask. */ -#define EBI_MRDLY1_bp 7 /* SDRAM Mode Register Delay bit 1 position. */ - -#define EBI_ROWCYCDLY_gm 0x38 /* SDRAM Row Cycle Delay group mask. */ -#define EBI_ROWCYCDLY_gp 3 /* SDRAM Row Cycle Delay group position. */ -#define EBI_ROWCYCDLY0_bm (1<<3) /* SDRAM Row Cycle Delay bit 0 mask. */ -#define EBI_ROWCYCDLY0_bp 3 /* SDRAM Row Cycle Delay bit 0 position. */ -#define EBI_ROWCYCDLY1_bm (1<<4) /* SDRAM Row Cycle Delay bit 1 mask. */ -#define EBI_ROWCYCDLY1_bp 4 /* SDRAM Row Cycle Delay bit 1 position. */ -#define EBI_ROWCYCDLY2_bm (1<<5) /* SDRAM Row Cycle Delay bit 2 mask. */ -#define EBI_ROWCYCDLY2_bp 5 /* SDRAM Row Cycle Delay bit 2 position. */ - -#define EBI_RPDLY_gm 0x07 /* SDRAM Row-to-Precharge Delay group mask. */ -#define EBI_RPDLY_gp 0 /* SDRAM Row-to-Precharge Delay group position. */ -#define EBI_RPDLY0_bm (1<<0) /* SDRAM Row-to-Precharge Delay bit 0 mask. */ -#define EBI_RPDLY0_bp 0 /* SDRAM Row-to-Precharge Delay bit 0 position. */ -#define EBI_RPDLY1_bm (1<<1) /* SDRAM Row-to-Precharge Delay bit 1 mask. */ -#define EBI_RPDLY1_bp 1 /* SDRAM Row-to-Precharge Delay bit 1 position. */ -#define EBI_RPDLY2_bm (1<<2) /* SDRAM Row-to-Precharge Delay bit 2 mask. */ -#define EBI_RPDLY2_bp 2 /* SDRAM Row-to-Precharge Delay bit 2 position. */ - - -/* EBI.SDRAMCTRLC bit masks and bit positions */ -#define EBI_WRDLY_gm 0xC0 /* SDRAM Write Recovery Delay group mask. */ -#define EBI_WRDLY_gp 6 /* SDRAM Write Recovery Delay group position. */ -#define EBI_WRDLY0_bm (1<<6) /* SDRAM Write Recovery Delay bit 0 mask. */ -#define EBI_WRDLY0_bp 6 /* SDRAM Write Recovery Delay bit 0 position. */ -#define EBI_WRDLY1_bm (1<<7) /* SDRAM Write Recovery Delay bit 1 mask. */ -#define EBI_WRDLY1_bp 7 /* SDRAM Write Recovery Delay bit 1 position. */ - -#define EBI_ESRDLY_gm 0x38 /* SDRAM Exit-Self-refresh-to-Active Delay group mask. */ -#define EBI_ESRDLY_gp 3 /* SDRAM Exit-Self-refresh-to-Active Delay group position. */ -#define EBI_ESRDLY0_bm (1<<3) /* SDRAM Exit-Self-refresh-to-Active Delay bit 0 mask. */ -#define EBI_ESRDLY0_bp 3 /* SDRAM Exit-Self-refresh-to-Active Delay bit 0 position. */ -#define EBI_ESRDLY1_bm (1<<4) /* SDRAM Exit-Self-refresh-to-Active Delay bit 1 mask. */ -#define EBI_ESRDLY1_bp 4 /* SDRAM Exit-Self-refresh-to-Active Delay bit 1 position. */ -#define EBI_ESRDLY2_bm (1<<5) /* SDRAM Exit-Self-refresh-to-Active Delay bit 2 mask. */ -#define EBI_ESRDLY2_bp 5 /* SDRAM Exit-Self-refresh-to-Active Delay bit 2 position. */ - -#define EBI_ROWCOLDLY_gm 0x07 /* SDRAM Row-to-Column Delay group mask. */ -#define EBI_ROWCOLDLY_gp 0 /* SDRAM Row-to-Column Delay group position. */ -#define EBI_ROWCOLDLY0_bm (1<<0) /* SDRAM Row-to-Column Delay bit 0 mask. */ -#define EBI_ROWCOLDLY0_bp 0 /* SDRAM Row-to-Column Delay bit 0 position. */ -#define EBI_ROWCOLDLY1_bm (1<<1) /* SDRAM Row-to-Column Delay bit 1 mask. */ -#define EBI_ROWCOLDLY1_bp 1 /* SDRAM Row-to-Column Delay bit 1 position. */ -#define EBI_ROWCOLDLY2_bm (1<<2) /* SDRAM Row-to-Column Delay bit 2 mask. */ -#define EBI_ROWCOLDLY2_bp 2 /* SDRAM Row-to-Column Delay bit 2 position. */ - - -/* TWI - Two-Wire Interface */ -/* TWI_MASTER.CTRLA bit masks and bit positions */ -#define TWI_MASTER_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ -#define TWI_MASTER_INTLVL_gp 6 /* Interrupt Level group position. */ -#define TWI_MASTER_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ -#define TWI_MASTER_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ -#define TWI_MASTER_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ -#define TWI_MASTER_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ - -#define TWI_MASTER_RIEN_bm 0x20 /* Read Interrupt Enable bit mask. */ -#define TWI_MASTER_RIEN_bp 5 /* Read Interrupt Enable bit position. */ - -#define TWI_MASTER_WIEN_bm 0x10 /* Write Interrupt Enable bit mask. */ -#define TWI_MASTER_WIEN_bp 4 /* Write Interrupt Enable bit position. */ - -#define TWI_MASTER_ENABLE_bm 0x08 /* Enable TWI Master bit mask. */ -#define TWI_MASTER_ENABLE_bp 3 /* Enable TWI Master bit position. */ - - -/* TWI_MASTER.CTRLB bit masks and bit positions */ -#define TWI_MASTER_TIMEOUT_gm 0x0C /* Inactive Bus Timeout group mask. */ -#define TWI_MASTER_TIMEOUT_gp 2 /* Inactive Bus Timeout group position. */ -#define TWI_MASTER_TIMEOUT0_bm (1<<2) /* Inactive Bus Timeout bit 0 mask. */ -#define TWI_MASTER_TIMEOUT0_bp 2 /* Inactive Bus Timeout bit 0 position. */ -#define TWI_MASTER_TIMEOUT1_bm (1<<3) /* Inactive Bus Timeout bit 1 mask. */ -#define TWI_MASTER_TIMEOUT1_bp 3 /* Inactive Bus Timeout bit 1 position. */ - -#define TWI_MASTER_QCEN_bm 0x02 /* Quick Command Enable bit mask. */ -#define TWI_MASTER_QCEN_bp 1 /* Quick Command Enable bit position. */ - -#define TWI_MASTER_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ -#define TWI_MASTER_SMEN_bp 0 /* Smart Mode Enable bit position. */ - - -/* TWI_MASTER.CTRLC bit masks and bit positions */ -#define TWI_MASTER_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ -#define TWI_MASTER_ACKACT_bp 2 /* Acknowledge Action bit position. */ - -#define TWI_MASTER_CMD_gm 0x03 /* Command group mask. */ -#define TWI_MASTER_CMD_gp 0 /* Command group position. */ -#define TWI_MASTER_CMD0_bm (1<<0) /* Command bit 0 mask. */ -#define TWI_MASTER_CMD0_bp 0 /* Command bit 0 position. */ -#define TWI_MASTER_CMD1_bm (1<<1) /* Command bit 1 mask. */ -#define TWI_MASTER_CMD1_bp 1 /* Command bit 1 position. */ - - -/* TWI_MASTER.STATUS bit masks and bit positions */ -#define TWI_MASTER_RIF_bm 0x80 /* Read Interrupt Flag bit mask. */ -#define TWI_MASTER_RIF_bp 7 /* Read Interrupt Flag bit position. */ - -#define TWI_MASTER_WIF_bm 0x40 /* Write Interrupt Flag bit mask. */ -#define TWI_MASTER_WIF_bp 6 /* Write Interrupt Flag bit position. */ - -#define TWI_MASTER_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ -#define TWI_MASTER_CLKHOLD_bp 5 /* Clock Hold bit position. */ - -#define TWI_MASTER_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ -#define TWI_MASTER_RXACK_bp 4 /* Received Acknowledge bit position. */ - -#define TWI_MASTER_ARBLOST_bm 0x08 /* Arbitration Lost bit mask. */ -#define TWI_MASTER_ARBLOST_bp 3 /* Arbitration Lost bit position. */ - -#define TWI_MASTER_BUSERR_bm 0x04 /* Bus Error bit mask. */ -#define TWI_MASTER_BUSERR_bp 2 /* Bus Error bit position. */ - -#define TWI_MASTER_BUSSTATE_gm 0x03 /* Bus State group mask. */ -#define TWI_MASTER_BUSSTATE_gp 0 /* Bus State group position. */ -#define TWI_MASTER_BUSSTATE0_bm (1<<0) /* Bus State bit 0 mask. */ -#define TWI_MASTER_BUSSTATE0_bp 0 /* Bus State bit 0 position. */ -#define TWI_MASTER_BUSSTATE1_bm (1<<1) /* Bus State bit 1 mask. */ -#define TWI_MASTER_BUSSTATE1_bp 1 /* Bus State bit 1 position. */ - - -/* TWI_SLAVE.CTRLA bit masks and bit positions */ -#define TWI_SLAVE_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ -#define TWI_SLAVE_INTLVL_gp 6 /* Interrupt Level group position. */ -#define TWI_SLAVE_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ -#define TWI_SLAVE_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ -#define TWI_SLAVE_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ -#define TWI_SLAVE_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ - -#define TWI_SLAVE_DIEN_bm 0x20 /* Data Interrupt Enable bit mask. */ -#define TWI_SLAVE_DIEN_bp 5 /* Data Interrupt Enable bit position. */ - -#define TWI_SLAVE_APIEN_bm 0x10 /* Address/Stop Interrupt Enable bit mask. */ -#define TWI_SLAVE_APIEN_bp 4 /* Address/Stop Interrupt Enable bit position. */ - -#define TWI_SLAVE_ENABLE_bm 0x08 /* Enable TWI Slave bit mask. */ -#define TWI_SLAVE_ENABLE_bp 3 /* Enable TWI Slave bit position. */ - -#define TWI_SLAVE_PIEN_bm 0x04 /* Stop Interrupt Enable bit mask. */ -#define TWI_SLAVE_PIEN_bp 2 /* Stop Interrupt Enable bit position. */ - -#define TWI_SLAVE_PMEN_bm 0x02 /* Promiscuous Mode Enable bit mask. */ -#define TWI_SLAVE_PMEN_bp 1 /* Promiscuous Mode Enable bit position. */ - -#define TWI_SLAVE_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ -#define TWI_SLAVE_SMEN_bp 0 /* Smart Mode Enable bit position. */ - - -/* TWI_SLAVE.CTRLB bit masks and bit positions */ -#define TWI_SLAVE_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ -#define TWI_SLAVE_ACKACT_bp 2 /* Acknowledge Action bit position. */ - -#define TWI_SLAVE_CMD_gm 0x03 /* Command group mask. */ -#define TWI_SLAVE_CMD_gp 0 /* Command group position. */ -#define TWI_SLAVE_CMD0_bm (1<<0) /* Command bit 0 mask. */ -#define TWI_SLAVE_CMD0_bp 0 /* Command bit 0 position. */ -#define TWI_SLAVE_CMD1_bm (1<<1) /* Command bit 1 mask. */ -#define TWI_SLAVE_CMD1_bp 1 /* Command bit 1 position. */ - - -/* TWI_SLAVE.STATUS bit masks and bit positions */ -#define TWI_SLAVE_DIF_bm 0x80 /* Data Interrupt Flag bit mask. */ -#define TWI_SLAVE_DIF_bp 7 /* Data Interrupt Flag bit position. */ - -#define TWI_SLAVE_APIF_bm 0x40 /* Address/Stop Interrupt Flag bit mask. */ -#define TWI_SLAVE_APIF_bp 6 /* Address/Stop Interrupt Flag bit position. */ - -#define TWI_SLAVE_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ -#define TWI_SLAVE_CLKHOLD_bp 5 /* Clock Hold bit position. */ - -#define TWI_SLAVE_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ -#define TWI_SLAVE_RXACK_bp 4 /* Received Acknowledge bit position. */ - -#define TWI_SLAVE_COLL_bm 0x08 /* Collision bit mask. */ -#define TWI_SLAVE_COLL_bp 3 /* Collision bit position. */ - -#define TWI_SLAVE_BUSERR_bm 0x04 /* Bus Error bit mask. */ -#define TWI_SLAVE_BUSERR_bp 2 /* Bus Error bit position. */ - -#define TWI_SLAVE_DIR_bm 0x02 /* Read/Write Direction bit mask. */ -#define TWI_SLAVE_DIR_bp 1 /* Read/Write Direction bit position. */ - -#define TWI_SLAVE_AP_bm 0x01 /* Slave Address or Stop bit mask. */ -#define TWI_SLAVE_AP_bp 0 /* Slave Address or Stop bit position. */ - - -/* TWI_SLAVE.ADDRMASK bit masks and bit positions */ -#define TWI_SLAVE_ADDRMASK_gm 0xFE /* Address Mask group mask. */ -#define TWI_SLAVE_ADDRMASK_gp 1 /* Address Mask group position. */ -#define TWI_SLAVE_ADDRMASK0_bm (1<<1) /* Address Mask bit 0 mask. */ -#define TWI_SLAVE_ADDRMASK0_bp 1 /* Address Mask bit 0 position. */ -#define TWI_SLAVE_ADDRMASK1_bm (1<<2) /* Address Mask bit 1 mask. */ -#define TWI_SLAVE_ADDRMASK1_bp 2 /* Address Mask bit 1 position. */ -#define TWI_SLAVE_ADDRMASK2_bm (1<<3) /* Address Mask bit 2 mask. */ -#define TWI_SLAVE_ADDRMASK2_bp 3 /* Address Mask bit 2 position. */ -#define TWI_SLAVE_ADDRMASK3_bm (1<<4) /* Address Mask bit 3 mask. */ -#define TWI_SLAVE_ADDRMASK3_bp 4 /* Address Mask bit 3 position. */ -#define TWI_SLAVE_ADDRMASK4_bm (1<<5) /* Address Mask bit 4 mask. */ -#define TWI_SLAVE_ADDRMASK4_bp 5 /* Address Mask bit 4 position. */ -#define TWI_SLAVE_ADDRMASK5_bm (1<<6) /* Address Mask bit 5 mask. */ -#define TWI_SLAVE_ADDRMASK5_bp 6 /* Address Mask bit 5 position. */ -#define TWI_SLAVE_ADDRMASK6_bm (1<<7) /* Address Mask bit 6 mask. */ -#define TWI_SLAVE_ADDRMASK6_bp 7 /* Address Mask bit 6 position. */ - -#define TWI_SLAVE_ADDREN_bm 0x01 /* Address Enable bit mask. */ -#define TWI_SLAVE_ADDREN_bp 0 /* Address Enable bit position. */ - - -/* TWI.CTRL bit masks and bit positions */ -#define TWI_SDAHOLD_bm 0x02 /* SDA Hold Time Enable bit mask. */ -#define TWI_SDAHOLD_bp 1 /* SDA Hold Time Enable bit position. */ - -#define TWI_EDIEN_bm 0x01 /* External Driver Interface Enable bit mask. */ -#define TWI_EDIEN_bp 0 /* External Driver Interface Enable bit position. */ - - -/* PORT - Port Configuration */ -/* PORTCFG.VPCTRLA bit masks and bit positions */ -#define PORTCFG_VP1MAP_gm 0xF0 /* Virtual Port 1 Mapping group mask. */ -#define PORTCFG_VP1MAP_gp 4 /* Virtual Port 1 Mapping group position. */ -#define PORTCFG_VP1MAP0_bm (1<<4) /* Virtual Port 1 Mapping bit 0 mask. */ -#define PORTCFG_VP1MAP0_bp 4 /* Virtual Port 1 Mapping bit 0 position. */ -#define PORTCFG_VP1MAP1_bm (1<<5) /* Virtual Port 1 Mapping bit 1 mask. */ -#define PORTCFG_VP1MAP1_bp 5 /* Virtual Port 1 Mapping bit 1 position. */ -#define PORTCFG_VP1MAP2_bm (1<<6) /* Virtual Port 1 Mapping bit 2 mask. */ -#define PORTCFG_VP1MAP2_bp 6 /* Virtual Port 1 Mapping bit 2 position. */ -#define PORTCFG_VP1MAP3_bm (1<<7) /* Virtual Port 1 Mapping bit 3 mask. */ -#define PORTCFG_VP1MAP3_bp 7 /* Virtual Port 1 Mapping bit 3 position. */ - -#define PORTCFG_VP0MAP_gm 0x0F /* Virtual Port 0 Mapping group mask. */ -#define PORTCFG_VP0MAP_gp 0 /* Virtual Port 0 Mapping group position. */ -#define PORTCFG_VP0MAP0_bm (1<<0) /* Virtual Port 0 Mapping bit 0 mask. */ -#define PORTCFG_VP0MAP0_bp 0 /* Virtual Port 0 Mapping bit 0 position. */ -#define PORTCFG_VP0MAP1_bm (1<<1) /* Virtual Port 0 Mapping bit 1 mask. */ -#define PORTCFG_VP0MAP1_bp 1 /* Virtual Port 0 Mapping bit 1 position. */ -#define PORTCFG_VP0MAP2_bm (1<<2) /* Virtual Port 0 Mapping bit 2 mask. */ -#define PORTCFG_VP0MAP2_bp 2 /* Virtual Port 0 Mapping bit 2 position. */ -#define PORTCFG_VP0MAP3_bm (1<<3) /* Virtual Port 0 Mapping bit 3 mask. */ -#define PORTCFG_VP0MAP3_bp 3 /* Virtual Port 0 Mapping bit 3 position. */ - - -/* PORTCFG.VPCTRLB bit masks and bit positions */ -#define PORTCFG_VP3MAP_gm 0xF0 /* Virtual Port 3 Mapping group mask. */ -#define PORTCFG_VP3MAP_gp 4 /* Virtual Port 3 Mapping group position. */ -#define PORTCFG_VP3MAP0_bm (1<<4) /* Virtual Port 3 Mapping bit 0 mask. */ -#define PORTCFG_VP3MAP0_bp 4 /* Virtual Port 3 Mapping bit 0 position. */ -#define PORTCFG_VP3MAP1_bm (1<<5) /* Virtual Port 3 Mapping bit 1 mask. */ -#define PORTCFG_VP3MAP1_bp 5 /* Virtual Port 3 Mapping bit 1 position. */ -#define PORTCFG_VP3MAP2_bm (1<<6) /* Virtual Port 3 Mapping bit 2 mask. */ -#define PORTCFG_VP3MAP2_bp 6 /* Virtual Port 3 Mapping bit 2 position. */ -#define PORTCFG_VP3MAP3_bm (1<<7) /* Virtual Port 3 Mapping bit 3 mask. */ -#define PORTCFG_VP3MAP3_bp 7 /* Virtual Port 3 Mapping bit 3 position. */ - -#define PORTCFG_VP2MAP_gm 0x0F /* Virtual Port 2 Mapping group mask. */ -#define PORTCFG_VP2MAP_gp 0 /* Virtual Port 2 Mapping group position. */ -#define PORTCFG_VP2MAP0_bm (1<<0) /* Virtual Port 2 Mapping bit 0 mask. */ -#define PORTCFG_VP2MAP0_bp 0 /* Virtual Port 2 Mapping bit 0 position. */ -#define PORTCFG_VP2MAP1_bm (1<<1) /* Virtual Port 2 Mapping bit 1 mask. */ -#define PORTCFG_VP2MAP1_bp 1 /* Virtual Port 2 Mapping bit 1 position. */ -#define PORTCFG_VP2MAP2_bm (1<<2) /* Virtual Port 2 Mapping bit 2 mask. */ -#define PORTCFG_VP2MAP2_bp 2 /* Virtual Port 2 Mapping bit 2 position. */ -#define PORTCFG_VP2MAP3_bm (1<<3) /* Virtual Port 2 Mapping bit 3 mask. */ -#define PORTCFG_VP2MAP3_bp 3 /* Virtual Port 2 Mapping bit 3 position. */ - - -/* PORTCFG.CLKEVOUT bit masks and bit positions */ -#define PORTCFG_CLKOUT_gm 0x03 /* Clock Output Port group mask. */ -#define PORTCFG_CLKOUT_gp 0 /* Clock Output Port group position. */ -#define PORTCFG_CLKOUT0_bm (1<<0) /* Clock Output Port bit 0 mask. */ -#define PORTCFG_CLKOUT0_bp 0 /* Clock Output Port bit 0 position. */ -#define PORTCFG_CLKOUT1_bm (1<<1) /* Clock Output Port bit 1 mask. */ -#define PORTCFG_CLKOUT1_bp 1 /* Clock Output Port bit 1 position. */ - -#define PORTCFG_EVOUT_gm 0x30 /* Event Output Port group mask. */ -#define PORTCFG_EVOUT_gp 4 /* Event Output Port group position. */ -#define PORTCFG_EVOUT0_bm (1<<4) /* Event Output Port bit 0 mask. */ -#define PORTCFG_EVOUT0_bp 4 /* Event Output Port bit 0 position. */ -#define PORTCFG_EVOUT1_bm (1<<5) /* Event Output Port bit 1 mask. */ -#define PORTCFG_EVOUT1_bp 5 /* Event Output Port bit 1 position. */ - - -/* VPORT.INTFLAGS bit masks and bit positions */ -#define VPORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ -#define VPORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ - -#define VPORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ -#define VPORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ - - -/* PORT.INTCTRL bit masks and bit positions */ -#define PORT_INT1LVL_gm 0x0C /* Port Interrupt 1 Level group mask. */ -#define PORT_INT1LVL_gp 2 /* Port Interrupt 1 Level group position. */ -#define PORT_INT1LVL0_bm (1<<2) /* Port Interrupt 1 Level bit 0 mask. */ -#define PORT_INT1LVL0_bp 2 /* Port Interrupt 1 Level bit 0 position. */ -#define PORT_INT1LVL1_bm (1<<3) /* Port Interrupt 1 Level bit 1 mask. */ -#define PORT_INT1LVL1_bp 3 /* Port Interrupt 1 Level bit 1 position. */ - -#define PORT_INT0LVL_gm 0x03 /* Port Interrupt 0 Level group mask. */ -#define PORT_INT0LVL_gp 0 /* Port Interrupt 0 Level group position. */ -#define PORT_INT0LVL0_bm (1<<0) /* Port Interrupt 0 Level bit 0 mask. */ -#define PORT_INT0LVL0_bp 0 /* Port Interrupt 0 Level bit 0 position. */ -#define PORT_INT0LVL1_bm (1<<1) /* Port Interrupt 0 Level bit 1 mask. */ -#define PORT_INT0LVL1_bp 1 /* Port Interrupt 0 Level bit 1 position. */ - - -/* PORT.INTFLAGS bit masks and bit positions */ -#define PORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ -#define PORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ - -#define PORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ -#define PORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ - - -/* PORT.PIN0CTRL bit masks and bit positions */ -#define PORT_SRLEN_bm 0x80 /* Slew Rate Enable bit mask. */ -#define PORT_SRLEN_bp 7 /* Slew Rate Enable bit position. */ - -#define PORT_INVEN_bm 0x40 /* Inverted I/O Enable bit mask. */ -#define PORT_INVEN_bp 6 /* Inverted I/O Enable bit position. */ - -#define PORT_OPC_gm 0x38 /* Output/Pull Configuration group mask. */ -#define PORT_OPC_gp 3 /* Output/Pull Configuration group position. */ -#define PORT_OPC0_bm (1<<3) /* Output/Pull Configuration bit 0 mask. */ -#define PORT_OPC0_bp 3 /* Output/Pull Configuration bit 0 position. */ -#define PORT_OPC1_bm (1<<4) /* Output/Pull Configuration bit 1 mask. */ -#define PORT_OPC1_bp 4 /* Output/Pull Configuration bit 1 position. */ -#define PORT_OPC2_bm (1<<5) /* Output/Pull Configuration bit 2 mask. */ -#define PORT_OPC2_bp 5 /* Output/Pull Configuration bit 2 position. */ - -#define PORT_ISC_gm 0x07 /* Input/Sense Configuration group mask. */ -#define PORT_ISC_gp 0 /* Input/Sense Configuration group position. */ -#define PORT_ISC0_bm (1<<0) /* Input/Sense Configuration bit 0 mask. */ -#define PORT_ISC0_bp 0 /* Input/Sense Configuration bit 0 position. */ -#define PORT_ISC1_bm (1<<1) /* Input/Sense Configuration bit 1 mask. */ -#define PORT_ISC1_bp 1 /* Input/Sense Configuration bit 1 position. */ -#define PORT_ISC2_bm (1<<2) /* Input/Sense Configuration bit 2 mask. */ -#define PORT_ISC2_bp 2 /* Input/Sense Configuration bit 2 position. */ - - -/* PORT.PIN1CTRL bit masks and bit positions */ -/* PORT_SRLEN_bm Predefined. */ -/* PORT_SRLEN_bp Predefined. */ - -/* PORT_INVEN_bm Predefined. */ -/* PORT_INVEN_bp Predefined. */ - -/* PORT_OPC_gm Predefined. */ -/* PORT_OPC_gp Predefined. */ -/* PORT_OPC0_bm Predefined. */ -/* PORT_OPC0_bp Predefined. */ -/* PORT_OPC1_bm Predefined. */ -/* PORT_OPC1_bp Predefined. */ -/* PORT_OPC2_bm Predefined. */ -/* PORT_OPC2_bp Predefined. */ - -/* PORT_ISC_gm Predefined. */ -/* PORT_ISC_gp Predefined. */ -/* PORT_ISC0_bm Predefined. */ -/* PORT_ISC0_bp Predefined. */ -/* PORT_ISC1_bm Predefined. */ -/* PORT_ISC1_bp Predefined. */ -/* PORT_ISC2_bm Predefined. */ -/* PORT_ISC2_bp Predefined. */ - - -/* PORT.PIN2CTRL bit masks and bit positions */ -/* PORT_SRLEN_bm Predefined. */ -/* PORT_SRLEN_bp Predefined. */ - -/* PORT_INVEN_bm Predefined. */ -/* PORT_INVEN_bp Predefined. */ - -/* PORT_OPC_gm Predefined. */ -/* PORT_OPC_gp Predefined. */ -/* PORT_OPC0_bm Predefined. */ -/* PORT_OPC0_bp Predefined. */ -/* PORT_OPC1_bm Predefined. */ -/* PORT_OPC1_bp Predefined. */ -/* PORT_OPC2_bm Predefined. */ -/* PORT_OPC2_bp Predefined. */ - -/* PORT_ISC_gm Predefined. */ -/* PORT_ISC_gp Predefined. */ -/* PORT_ISC0_bm Predefined. */ -/* PORT_ISC0_bp Predefined. */ -/* PORT_ISC1_bm Predefined. */ -/* PORT_ISC1_bp Predefined. */ -/* PORT_ISC2_bm Predefined. */ -/* PORT_ISC2_bp Predefined. */ - - -/* PORT.PIN3CTRL bit masks and bit positions */ -/* PORT_SRLEN_bm Predefined. */ -/* PORT_SRLEN_bp Predefined. */ - -/* PORT_INVEN_bm Predefined. */ -/* PORT_INVEN_bp Predefined. */ - -/* PORT_OPC_gm Predefined. */ -/* PORT_OPC_gp Predefined. */ -/* PORT_OPC0_bm Predefined. */ -/* PORT_OPC0_bp Predefined. */ -/* PORT_OPC1_bm Predefined. */ -/* PORT_OPC1_bp Predefined. */ -/* PORT_OPC2_bm Predefined. */ -/* PORT_OPC2_bp Predefined. */ - -/* PORT_ISC_gm Predefined. */ -/* PORT_ISC_gp Predefined. */ -/* PORT_ISC0_bm Predefined. */ -/* PORT_ISC0_bp Predefined. */ -/* PORT_ISC1_bm Predefined. */ -/* PORT_ISC1_bp Predefined. */ -/* PORT_ISC2_bm Predefined. */ -/* PORT_ISC2_bp Predefined. */ - - -/* PORT.PIN4CTRL bit masks and bit positions */ -/* PORT_SRLEN_bm Predefined. */ -/* PORT_SRLEN_bp Predefined. */ - -/* PORT_INVEN_bm Predefined. */ -/* PORT_INVEN_bp Predefined. */ - -/* PORT_OPC_gm Predefined. */ -/* PORT_OPC_gp Predefined. */ -/* PORT_OPC0_bm Predefined. */ -/* PORT_OPC0_bp Predefined. */ -/* PORT_OPC1_bm Predefined. */ -/* PORT_OPC1_bp Predefined. */ -/* PORT_OPC2_bm Predefined. */ -/* PORT_OPC2_bp Predefined. */ - -/* PORT_ISC_gm Predefined. */ -/* PORT_ISC_gp Predefined. */ -/* PORT_ISC0_bm Predefined. */ -/* PORT_ISC0_bp Predefined. */ -/* PORT_ISC1_bm Predefined. */ -/* PORT_ISC1_bp Predefined. */ -/* PORT_ISC2_bm Predefined. */ -/* PORT_ISC2_bp Predefined. */ - - -/* PORT.PIN5CTRL bit masks and bit positions */ -/* PORT_SRLEN_bm Predefined. */ -/* PORT_SRLEN_bp Predefined. */ - -/* PORT_INVEN_bm Predefined. */ -/* PORT_INVEN_bp Predefined. */ - -/* PORT_OPC_gm Predefined. */ -/* PORT_OPC_gp Predefined. */ -/* PORT_OPC0_bm Predefined. */ -/* PORT_OPC0_bp Predefined. */ -/* PORT_OPC1_bm Predefined. */ -/* PORT_OPC1_bp Predefined. */ -/* PORT_OPC2_bm Predefined. */ -/* PORT_OPC2_bp Predefined. */ - -/* PORT_ISC_gm Predefined. */ -/* PORT_ISC_gp Predefined. */ -/* PORT_ISC0_bm Predefined. */ -/* PORT_ISC0_bp Predefined. */ -/* PORT_ISC1_bm Predefined. */ -/* PORT_ISC1_bp Predefined. */ -/* PORT_ISC2_bm Predefined. */ -/* PORT_ISC2_bp Predefined. */ - - -/* PORT.PIN6CTRL bit masks and bit positions */ -/* PORT_SRLEN_bm Predefined. */ -/* PORT_SRLEN_bp Predefined. */ - -/* PORT_INVEN_bm Predefined. */ -/* PORT_INVEN_bp Predefined. */ - -/* PORT_OPC_gm Predefined. */ -/* PORT_OPC_gp Predefined. */ -/* PORT_OPC0_bm Predefined. */ -/* PORT_OPC0_bp Predefined. */ -/* PORT_OPC1_bm Predefined. */ -/* PORT_OPC1_bp Predefined. */ -/* PORT_OPC2_bm Predefined. */ -/* PORT_OPC2_bp Predefined. */ - -/* PORT_ISC_gm Predefined. */ -/* PORT_ISC_gp Predefined. */ -/* PORT_ISC0_bm Predefined. */ -/* PORT_ISC0_bp Predefined. */ -/* PORT_ISC1_bm Predefined. */ -/* PORT_ISC1_bp Predefined. */ -/* PORT_ISC2_bm Predefined. */ -/* PORT_ISC2_bp Predefined. */ - - -/* PORT.PIN7CTRL bit masks and bit positions */ -/* PORT_SRLEN_bm Predefined. */ -/* PORT_SRLEN_bp Predefined. */ - -/* PORT_INVEN_bm Predefined. */ -/* PORT_INVEN_bp Predefined. */ - -/* PORT_OPC_gm Predefined. */ -/* PORT_OPC_gp Predefined. */ -/* PORT_OPC0_bm Predefined. */ -/* PORT_OPC0_bp Predefined. */ -/* PORT_OPC1_bm Predefined. */ -/* PORT_OPC1_bp Predefined. */ -/* PORT_OPC2_bm Predefined. */ -/* PORT_OPC2_bp Predefined. */ - -/* PORT_ISC_gm Predefined. */ -/* PORT_ISC_gp Predefined. */ -/* PORT_ISC0_bm Predefined. */ -/* PORT_ISC0_bp Predefined. */ -/* PORT_ISC1_bm Predefined. */ -/* PORT_ISC1_bp Predefined. */ -/* PORT_ISC2_bm Predefined. */ -/* PORT_ISC2_bp Predefined. */ - - -/* TC - 16-bit Timer/Counter With PWM */ -/* TC0.CTRLA bit masks and bit positions */ -#define TC0_CLKSEL_gm 0x0F /* Clock Selection group mask. */ -#define TC0_CLKSEL_gp 0 /* Clock Selection group position. */ -#define TC0_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ -#define TC0_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ -#define TC0_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ -#define TC0_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ -#define TC0_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ -#define TC0_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ -#define TC0_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ -#define TC0_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ - - -/* TC0.CTRLB bit masks and bit positions */ -#define TC0_CCDEN_bm 0x80 /* Compare or Capture D Enable bit mask. */ -#define TC0_CCDEN_bp 7 /* Compare or Capture D Enable bit position. */ - -#define TC0_CCCEN_bm 0x40 /* Compare or Capture C Enable bit mask. */ -#define TC0_CCCEN_bp 6 /* Compare or Capture C Enable bit position. */ - -#define TC0_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ -#define TC0_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ - -#define TC0_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ -#define TC0_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ - -#define TC0_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ -#define TC0_WGMODE_gp 0 /* Waveform generation mode group position. */ -#define TC0_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ -#define TC0_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ -#define TC0_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ -#define TC0_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ -#define TC0_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ -#define TC0_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ - - -/* TC0.CTRLC bit masks and bit positions */ -#define TC0_CMPD_bm 0x08 /* Compare D Output Value bit mask. */ -#define TC0_CMPD_bp 3 /* Compare D Output Value bit position. */ - -#define TC0_CMPC_bm 0x04 /* Compare C Output Value bit mask. */ -#define TC0_CMPC_bp 2 /* Compare C Output Value bit position. */ - -#define TC0_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ -#define TC0_CMPB_bp 1 /* Compare B Output Value bit position. */ - -#define TC0_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ -#define TC0_CMPA_bp 0 /* Compare A Output Value bit position. */ - - -/* TC0.CTRLD bit masks and bit positions */ -#define TC0_EVACT_gm 0xE0 /* Event Action group mask. */ -#define TC0_EVACT_gp 5 /* Event Action group position. */ -#define TC0_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ -#define TC0_EVACT0_bp 5 /* Event Action bit 0 position. */ -#define TC0_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ -#define TC0_EVACT1_bp 6 /* Event Action bit 1 position. */ -#define TC0_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ -#define TC0_EVACT2_bp 7 /* Event Action bit 2 position. */ - -#define TC0_EVDLY_bm 0x10 /* Event Delay bit mask. */ -#define TC0_EVDLY_bp 4 /* Event Delay bit position. */ - -#define TC0_EVSEL_gm 0x0F /* Event Source Select group mask. */ -#define TC0_EVSEL_gp 0 /* Event Source Select group position. */ -#define TC0_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ -#define TC0_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ -#define TC0_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ -#define TC0_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ -#define TC0_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ -#define TC0_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ -#define TC0_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ -#define TC0_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ - - -/* TC0.CTRLE bit masks and bit positions */ -#define TC0_DTHM_bm 0x02 /* Dead Time Hold Mode bit mask. */ -#define TC0_DTHM_bp 1 /* Dead Time Hold Mode bit position. */ - -#define TC0_BYTEM_bm 0x01 /* Byte Mode bit mask. */ -#define TC0_BYTEM_bp 0 /* Byte Mode bit position. */ - - -/* TC0.INTCTRLA bit masks and bit positions */ -#define TC0_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ -#define TC0_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ -#define TC0_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ -#define TC0_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ -#define TC0_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ -#define TC0_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ - -#define TC0_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ -#define TC0_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ -#define TC0_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ -#define TC0_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ -#define TC0_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ -#define TC0_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ - - -/* TC0.INTCTRLB bit masks and bit positions */ -#define TC0_CCDINTLVL_gm 0xC0 /* Compare or Capture D Interrupt Level group mask. */ -#define TC0_CCDINTLVL_gp 6 /* Compare or Capture D Interrupt Level group position. */ -#define TC0_CCDINTLVL0_bm (1<<6) /* Compare or Capture D Interrupt Level bit 0 mask. */ -#define TC0_CCDINTLVL0_bp 6 /* Compare or Capture D Interrupt Level bit 0 position. */ -#define TC0_CCDINTLVL1_bm (1<<7) /* Compare or Capture D Interrupt Level bit 1 mask. */ -#define TC0_CCDINTLVL1_bp 7 /* Compare or Capture D Interrupt Level bit 1 position. */ - -#define TC0_CCCINTLVL_gm 0x30 /* Compare or Capture C Interrupt Level group mask. */ -#define TC0_CCCINTLVL_gp 4 /* Compare or Capture C Interrupt Level group position. */ -#define TC0_CCCINTLVL0_bm (1<<4) /* Compare or Capture C Interrupt Level bit 0 mask. */ -#define TC0_CCCINTLVL0_bp 4 /* Compare or Capture C Interrupt Level bit 0 position. */ -#define TC0_CCCINTLVL1_bm (1<<5) /* Compare or Capture C Interrupt Level bit 1 mask. */ -#define TC0_CCCINTLVL1_bp 5 /* Compare or Capture C Interrupt Level bit 1 position. */ - -#define TC0_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ -#define TC0_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ -#define TC0_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ -#define TC0_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ -#define TC0_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ -#define TC0_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ - -#define TC0_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ -#define TC0_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ -#define TC0_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ -#define TC0_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ -#define TC0_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ -#define TC0_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ - - -/* TC0.CTRLFCLR bit masks and bit positions */ -#define TC0_CMD_gm 0x0C /* Command group mask. */ -#define TC0_CMD_gp 2 /* Command group position. */ -#define TC0_CMD0_bm (1<<2) /* Command bit 0 mask. */ -#define TC0_CMD0_bp 2 /* Command bit 0 position. */ -#define TC0_CMD1_bm (1<<3) /* Command bit 1 mask. */ -#define TC0_CMD1_bp 3 /* Command bit 1 position. */ - -#define TC0_LUPD_bm 0x02 /* Lock Update bit mask. */ -#define TC0_LUPD_bp 1 /* Lock Update bit position. */ - -#define TC0_DIR_bm 0x01 /* Direction bit mask. */ -#define TC0_DIR_bp 0 /* Direction bit position. */ - - -/* TC0.CTRLFSET bit masks and bit positions */ -/* TC0_CMD_gm Predefined. */ -/* TC0_CMD_gp Predefined. */ -/* TC0_CMD0_bm Predefined. */ -/* TC0_CMD0_bp Predefined. */ -/* TC0_CMD1_bm Predefined. */ -/* TC0_CMD1_bp Predefined. */ - -/* TC0_LUPD_bm Predefined. */ -/* TC0_LUPD_bp Predefined. */ - -/* TC0_DIR_bm Predefined. */ -/* TC0_DIR_bp Predefined. */ - - -/* TC0.CTRLGCLR bit masks and bit positions */ -#define TC0_CCDBV_bm 0x10 /* Compare or Capture D Buffer Valid bit mask. */ -#define TC0_CCDBV_bp 4 /* Compare or Capture D Buffer Valid bit position. */ - -#define TC0_CCCBV_bm 0x08 /* Compare or Capture C Buffer Valid bit mask. */ -#define TC0_CCCBV_bp 3 /* Compare or Capture C Buffer Valid bit position. */ - -#define TC0_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ -#define TC0_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ - -#define TC0_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ -#define TC0_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ - -#define TC0_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ -#define TC0_PERBV_bp 0 /* Period Buffer Valid bit position. */ - - -/* TC0.CTRLGSET bit masks and bit positions */ -/* TC0_CCDBV_bm Predefined. */ -/* TC0_CCDBV_bp Predefined. */ - -/* TC0_CCCBV_bm Predefined. */ -/* TC0_CCCBV_bp Predefined. */ - -/* TC0_CCBBV_bm Predefined. */ -/* TC0_CCBBV_bp Predefined. */ - -/* TC0_CCABV_bm Predefined. */ -/* TC0_CCABV_bp Predefined. */ - -/* TC0_PERBV_bm Predefined. */ -/* TC0_PERBV_bp Predefined. */ - - -/* TC0.INTFLAGS bit masks and bit positions */ -#define TC0_CCDIF_bm 0x80 /* Compare or Capture D Interrupt Flag bit mask. */ -#define TC0_CCDIF_bp 7 /* Compare or Capture D Interrupt Flag bit position. */ - -#define TC0_CCCIF_bm 0x40 /* Compare or Capture C Interrupt Flag bit mask. */ -#define TC0_CCCIF_bp 6 /* Compare or Capture C Interrupt Flag bit position. */ - -#define TC0_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ -#define TC0_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ - -#define TC0_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ -#define TC0_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ - -#define TC0_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ -#define TC0_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ - -#define TC0_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ -#define TC0_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ - - -/* TC1.CTRLA bit masks and bit positions */ -#define TC1_CLKSEL_gm 0x0F /* Clock Selection group mask. */ -#define TC1_CLKSEL_gp 0 /* Clock Selection group position. */ -#define TC1_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ -#define TC1_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ -#define TC1_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ -#define TC1_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ -#define TC1_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ -#define TC1_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ -#define TC1_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ -#define TC1_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ - - -/* TC1.CTRLB bit masks and bit positions */ -#define TC1_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ -#define TC1_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ - -#define TC1_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ -#define TC1_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ - -#define TC1_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ -#define TC1_WGMODE_gp 0 /* Waveform generation mode group position. */ -#define TC1_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ -#define TC1_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ -#define TC1_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ -#define TC1_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ -#define TC1_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ -#define TC1_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ - - -/* TC1.CTRLC bit masks and bit positions */ -#define TC1_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ -#define TC1_CMPB_bp 1 /* Compare B Output Value bit position. */ - -#define TC1_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ -#define TC1_CMPA_bp 0 /* Compare A Output Value bit position. */ - - -/* TC1.CTRLD bit masks and bit positions */ -#define TC1_EVACT_gm 0xE0 /* Event Action group mask. */ -#define TC1_EVACT_gp 5 /* Event Action group position. */ -#define TC1_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ -#define TC1_EVACT0_bp 5 /* Event Action bit 0 position. */ -#define TC1_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ -#define TC1_EVACT1_bp 6 /* Event Action bit 1 position. */ -#define TC1_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ -#define TC1_EVACT2_bp 7 /* Event Action bit 2 position. */ - -#define TC1_EVDLY_bm 0x10 /* Event Delay bit mask. */ -#define TC1_EVDLY_bp 4 /* Event Delay bit position. */ - -#define TC1_EVSEL_gm 0x0F /* Event Source Select group mask. */ -#define TC1_EVSEL_gp 0 /* Event Source Select group position. */ -#define TC1_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ -#define TC1_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ -#define TC1_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ -#define TC1_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ -#define TC1_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ -#define TC1_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ -#define TC1_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ -#define TC1_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ - - -/* TC1.CTRLE bit masks and bit positions */ -#define TC1_DTHM_bm 0x02 /* Dead Time Hold Mode bit mask. */ -#define TC1_DTHM_bp 1 /* Dead Time Hold Mode bit position. */ - -#define TC1_BYTEM_bm 0x01 /* Byte Mode bit mask. */ -#define TC1_BYTEM_bp 0 /* Byte Mode bit position. */ - - -/* TC1.INTCTRLA bit masks and bit positions */ -#define TC1_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ -#define TC1_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ -#define TC1_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ -#define TC1_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ -#define TC1_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ -#define TC1_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ - -#define TC1_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ -#define TC1_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ -#define TC1_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ -#define TC1_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ -#define TC1_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ -#define TC1_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ - - -/* TC1.INTCTRLB bit masks and bit positions */ -#define TC1_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ -#define TC1_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ -#define TC1_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ -#define TC1_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ -#define TC1_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ -#define TC1_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ - -#define TC1_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ -#define TC1_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ -#define TC1_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ -#define TC1_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ -#define TC1_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ -#define TC1_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ - - -/* TC1.CTRLFCLR bit masks and bit positions */ -#define TC1_CMD_gm 0x0C /* Command group mask. */ -#define TC1_CMD_gp 2 /* Command group position. */ -#define TC1_CMD0_bm (1<<2) /* Command bit 0 mask. */ -#define TC1_CMD0_bp 2 /* Command bit 0 position. */ -#define TC1_CMD1_bm (1<<3) /* Command bit 1 mask. */ -#define TC1_CMD1_bp 3 /* Command bit 1 position. */ - -#define TC1_LUPD_bm 0x02 /* Lock Update bit mask. */ -#define TC1_LUPD_bp 1 /* Lock Update bit position. */ - -#define TC1_DIR_bm 0x01 /* Direction bit mask. */ -#define TC1_DIR_bp 0 /* Direction bit position. */ - - -/* TC1.CTRLFSET bit masks and bit positions */ -/* TC1_CMD_gm Predefined. */ -/* TC1_CMD_gp Predefined. */ -/* TC1_CMD0_bm Predefined. */ -/* TC1_CMD0_bp Predefined. */ -/* TC1_CMD1_bm Predefined. */ -/* TC1_CMD1_bp Predefined. */ - -/* TC1_LUPD_bm Predefined. */ -/* TC1_LUPD_bp Predefined. */ - -/* TC1_DIR_bm Predefined. */ -/* TC1_DIR_bp Predefined. */ - - -/* TC1.CTRLGCLR bit masks and bit positions */ -#define TC1_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ -#define TC1_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ - -#define TC1_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ -#define TC1_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ - -#define TC1_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ -#define TC1_PERBV_bp 0 /* Period Buffer Valid bit position. */ - - -/* TC1.CTRLGSET bit masks and bit positions */ -/* TC1_CCBBV_bm Predefined. */ -/* TC1_CCBBV_bp Predefined. */ - -/* TC1_CCABV_bm Predefined. */ -/* TC1_CCABV_bp Predefined. */ - -/* TC1_PERBV_bm Predefined. */ -/* TC1_PERBV_bp Predefined. */ - - -/* TC1.INTFLAGS bit masks and bit positions */ -#define TC1_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ -#define TC1_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ - -#define TC1_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ -#define TC1_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ - -#define TC1_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ -#define TC1_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ - -#define TC1_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ -#define TC1_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ - - -/* AWEX.CTRL bit masks and bit positions */ -#define AWEX_PGM_bm 0x20 /* Pattern Generation Mode bit mask. */ -#define AWEX_PGM_bp 5 /* Pattern Generation Mode bit position. */ - -#define AWEX_CWCM_bm 0x10 /* Common Waveform Channel Mode bit mask. */ -#define AWEX_CWCM_bp 4 /* Common Waveform Channel Mode bit position. */ - -#define AWEX_DTICCDEN_bm 0x08 /* Dead Time Insertion Compare Channel D Enable bit mask. */ -#define AWEX_DTICCDEN_bp 3 /* Dead Time Insertion Compare Channel D Enable bit position. */ - -#define AWEX_DTICCCEN_bm 0x04 /* Dead Time Insertion Compare Channel C Enable bit mask. */ -#define AWEX_DTICCCEN_bp 2 /* Dead Time Insertion Compare Channel C Enable bit position. */ - -#define AWEX_DTICCBEN_bm 0x02 /* Dead Time Insertion Compare Channel B Enable bit mask. */ -#define AWEX_DTICCBEN_bp 1 /* Dead Time Insertion Compare Channel B Enable bit position. */ - -#define AWEX_DTICCAEN_bm 0x01 /* Dead Time Insertion Compare Channel A Enable bit mask. */ -#define AWEX_DTICCAEN_bp 0 /* Dead Time Insertion Compare Channel A Enable bit position. */ - - -/* AWEX.FDCTRL bit masks and bit positions */ -#define AWEX_FDDBD_bm 0x10 /* Fault Detect on Disable Break Disable bit mask. */ -#define AWEX_FDDBD_bp 4 /* Fault Detect on Disable Break Disable bit position. */ - -#define AWEX_FDMODE_bm 0x04 /* Fault Detect Mode bit mask. */ -#define AWEX_FDMODE_bp 2 /* Fault Detect Mode bit position. */ - -#define AWEX_FDACT_gm 0x03 /* Fault Detect Action group mask. */ -#define AWEX_FDACT_gp 0 /* Fault Detect Action group position. */ -#define AWEX_FDACT0_bm (1<<0) /* Fault Detect Action bit 0 mask. */ -#define AWEX_FDACT0_bp 0 /* Fault Detect Action bit 0 position. */ -#define AWEX_FDACT1_bm (1<<1) /* Fault Detect Action bit 1 mask. */ -#define AWEX_FDACT1_bp 1 /* Fault Detect Action bit 1 position. */ - - -/* AWEX.STATUS bit masks and bit positions */ -#define AWEX_FDF_bm 0x04 /* Fault Detect Flag bit mask. */ -#define AWEX_FDF_bp 2 /* Fault Detect Flag bit position. */ - -#define AWEX_DTHSBUFV_bm 0x02 /* Dead Time High Side Buffer Valid bit mask. */ -#define AWEX_DTHSBUFV_bp 1 /* Dead Time High Side Buffer Valid bit position. */ - -#define AWEX_DTLSBUFV_bm 0x01 /* Dead Time Low Side Buffer Valid bit mask. */ -#define AWEX_DTLSBUFV_bp 0 /* Dead Time Low Side Buffer Valid bit position. */ - - -/* HIRES.CTRL bit masks and bit positions */ -#define HIRES_HREN_gm 0x03 /* High Resolution Enable group mask. */ -#define HIRES_HREN_gp 0 /* High Resolution Enable group position. */ -#define HIRES_HREN0_bm (1<<0) /* High Resolution Enable bit 0 mask. */ -#define HIRES_HREN0_bp 0 /* High Resolution Enable bit 0 position. */ -#define HIRES_HREN1_bm (1<<1) /* High Resolution Enable bit 1 mask. */ -#define HIRES_HREN1_bp 1 /* High Resolution Enable bit 1 position. */ - - -/* USART - Universal Asynchronous Receiver-Transmitter */ -/* USART.STATUS bit masks and bit positions */ -#define USART_RXCIF_bm 0x80 /* Receive Interrupt Flag bit mask. */ -#define USART_RXCIF_bp 7 /* Receive Interrupt Flag bit position. */ - -#define USART_TXCIF_bm 0x40 /* Transmit Interrupt Flag bit mask. */ -#define USART_TXCIF_bp 6 /* Transmit Interrupt Flag bit position. */ - -#define USART_DREIF_bm 0x20 /* Data Register Empty Flag bit mask. */ -#define USART_DREIF_bp 5 /* Data Register Empty Flag bit position. */ - -#define USART_FERR_bm 0x10 /* Frame Error bit mask. */ -#define USART_FERR_bp 4 /* Frame Error bit position. */ - -#define USART_BUFOVF_bm 0x08 /* Buffer Overflow bit mask. */ -#define USART_BUFOVF_bp 3 /* Buffer Overflow bit position. */ - -#define USART_PERR_bm 0x04 /* Parity Error bit mask. */ -#define USART_PERR_bp 2 /* Parity Error bit position. */ - -#define USART_RXB8_bm 0x01 /* Receive Bit 8 bit mask. */ -#define USART_RXB8_bp 0 /* Receive Bit 8 bit position. */ - - -/* USART.CTRLA bit masks and bit positions */ -#define USART_RXCINTLVL_gm 0x30 /* Receive Interrupt Level group mask. */ -#define USART_RXCINTLVL_gp 4 /* Receive Interrupt Level group position. */ -#define USART_RXCINTLVL0_bm (1<<4) /* Receive Interrupt Level bit 0 mask. */ -#define USART_RXCINTLVL0_bp 4 /* Receive Interrupt Level bit 0 position. */ -#define USART_RXCINTLVL1_bm (1<<5) /* Receive Interrupt Level bit 1 mask. */ -#define USART_RXCINTLVL1_bp 5 /* Receive Interrupt Level bit 1 position. */ - -#define USART_TXCINTLVL_gm 0x0C /* Transmit Interrupt Level group mask. */ -#define USART_TXCINTLVL_gp 2 /* Transmit Interrupt Level group position. */ -#define USART_TXCINTLVL0_bm (1<<2) /* Transmit Interrupt Level bit 0 mask. */ -#define USART_TXCINTLVL0_bp 2 /* Transmit Interrupt Level bit 0 position. */ -#define USART_TXCINTLVL1_bm (1<<3) /* Transmit Interrupt Level bit 1 mask. */ -#define USART_TXCINTLVL1_bp 3 /* Transmit Interrupt Level bit 1 position. */ - -#define USART_DREINTLVL_gm 0x03 /* Data Register Empty Interrupt Level group mask. */ -#define USART_DREINTLVL_gp 0 /* Data Register Empty Interrupt Level group position. */ -#define USART_DREINTLVL0_bm (1<<0) /* Data Register Empty Interrupt Level bit 0 mask. */ -#define USART_DREINTLVL0_bp 0 /* Data Register Empty Interrupt Level bit 0 position. */ -#define USART_DREINTLVL1_bm (1<<1) /* Data Register Empty Interrupt Level bit 1 mask. */ -#define USART_DREINTLVL1_bp 1 /* Data Register Empty Interrupt Level bit 1 position. */ - - -/* USART.CTRLB bit masks and bit positions */ -#define USART_RXEN_bm 0x10 /* Receiver Enable bit mask. */ -#define USART_RXEN_bp 4 /* Receiver Enable bit position. */ - -#define USART_TXEN_bm 0x08 /* Transmitter Enable bit mask. */ -#define USART_TXEN_bp 3 /* Transmitter Enable bit position. */ - -#define USART_CLK2X_bm 0x04 /* Double transmission speed bit mask. */ -#define USART_CLK2X_bp 2 /* Double transmission speed bit position. */ - -#define USART_MPCM_bm 0x02 /* Multi-processor Communication Mode bit mask. */ -#define USART_MPCM_bp 1 /* Multi-processor Communication Mode bit position. */ - -#define USART_TXB8_bm 0x01 /* Transmit bit 8 bit mask. */ -#define USART_TXB8_bp 0 /* Transmit bit 8 bit position. */ - - -/* USART.CTRLC bit masks and bit positions */ -#define USART_CMODE_gm 0xC0 /* Communication Mode group mask. */ -#define USART_CMODE_gp 6 /* Communication Mode group position. */ -#define USART_CMODE0_bm (1<<6) /* Communication Mode bit 0 mask. */ -#define USART_CMODE0_bp 6 /* Communication Mode bit 0 position. */ -#define USART_CMODE1_bm (1<<7) /* Communication Mode bit 1 mask. */ -#define USART_CMODE1_bp 7 /* Communication Mode bit 1 position. */ - -#define USART_PMODE_gm 0x30 /* Parity Mode group mask. */ -#define USART_PMODE_gp 4 /* Parity Mode group position. */ -#define USART_PMODE0_bm (1<<4) /* Parity Mode bit 0 mask. */ -#define USART_PMODE0_bp 4 /* Parity Mode bit 0 position. */ -#define USART_PMODE1_bm (1<<5) /* Parity Mode bit 1 mask. */ -#define USART_PMODE1_bp 5 /* Parity Mode bit 1 position. */ - -#define USART_SBMODE_bm 0x08 /* Stop Bit Mode bit mask. */ -#define USART_SBMODE_bp 3 /* Stop Bit Mode bit position. */ - -#define USART_CHSIZE_gm 0x07 /* Character Size group mask. */ -#define USART_CHSIZE_gp 0 /* Character Size group position. */ -#define USART_CHSIZE0_bm (1<<0) /* Character Size bit 0 mask. */ -#define USART_CHSIZE0_bp 0 /* Character Size bit 0 position. */ -#define USART_CHSIZE1_bm (1<<1) /* Character Size bit 1 mask. */ -#define USART_CHSIZE1_bp 1 /* Character Size bit 1 position. */ -#define USART_CHSIZE2_bm (1<<2) /* Character Size bit 2 mask. */ -#define USART_CHSIZE2_bp 2 /* Character Size bit 2 position. */ - - -/* USART.BAUDCTRLA bit masks and bit positions */ -#define USART_BSEL_gm 0xFF /* Baud Rate Selection Bits [7:0] group mask. */ -#define USART_BSEL_gp 0 /* Baud Rate Selection Bits [7:0] group position. */ -#define USART_BSEL0_bm (1<<0) /* Baud Rate Selection Bits [7:0] bit 0 mask. */ -#define USART_BSEL0_bp 0 /* Baud Rate Selection Bits [7:0] bit 0 position. */ -#define USART_BSEL1_bm (1<<1) /* Baud Rate Selection Bits [7:0] bit 1 mask. */ -#define USART_BSEL1_bp 1 /* Baud Rate Selection Bits [7:0] bit 1 position. */ -#define USART_BSEL2_bm (1<<2) /* Baud Rate Selection Bits [7:0] bit 2 mask. */ -#define USART_BSEL2_bp 2 /* Baud Rate Selection Bits [7:0] bit 2 position. */ -#define USART_BSEL3_bm (1<<3) /* Baud Rate Selection Bits [7:0] bit 3 mask. */ -#define USART_BSEL3_bp 3 /* Baud Rate Selection Bits [7:0] bit 3 position. */ -#define USART_BSEL4_bm (1<<4) /* Baud Rate Selection Bits [7:0] bit 4 mask. */ -#define USART_BSEL4_bp 4 /* Baud Rate Selection Bits [7:0] bit 4 position. */ -#define USART_BSEL5_bm (1<<5) /* Baud Rate Selection Bits [7:0] bit 5 mask. */ -#define USART_BSEL5_bp 5 /* Baud Rate Selection Bits [7:0] bit 5 position. */ -#define USART_BSEL6_bm (1<<6) /* Baud Rate Selection Bits [7:0] bit 6 mask. */ -#define USART_BSEL6_bp 6 /* Baud Rate Selection Bits [7:0] bit 6 position. */ -#define USART_BSEL7_bm (1<<7) /* Baud Rate Selection Bits [7:0] bit 7 mask. */ -#define USART_BSEL7_bp 7 /* Baud Rate Selection Bits [7:0] bit 7 position. */ - - -/* USART.BAUDCTRLB bit masks and bit positions */ -#define USART_BSCALE_gm 0xF0 /* Baud Rate Scale group mask. */ -#define USART_BSCALE_gp 4 /* Baud Rate Scale group position. */ -#define USART_BSCALE0_bm (1<<4) /* Baud Rate Scale bit 0 mask. */ -#define USART_BSCALE0_bp 4 /* Baud Rate Scale bit 0 position. */ -#define USART_BSCALE1_bm (1<<5) /* Baud Rate Scale bit 1 mask. */ -#define USART_BSCALE1_bp 5 /* Baud Rate Scale bit 1 position. */ -#define USART_BSCALE2_bm (1<<6) /* Baud Rate Scale bit 2 mask. */ -#define USART_BSCALE2_bp 6 /* Baud Rate Scale bit 2 position. */ -#define USART_BSCALE3_bm (1<<7) /* Baud Rate Scale bit 3 mask. */ -#define USART_BSCALE3_bp 7 /* Baud Rate Scale bit 3 position. */ - -/* USART_BSEL_gm Predefined. */ -/* USART_BSEL_gp Predefined. */ -/* USART_BSEL0_bm Predefined. */ -/* USART_BSEL0_bp Predefined. */ -/* USART_BSEL1_bm Predefined. */ -/* USART_BSEL1_bp Predefined. */ -/* USART_BSEL2_bm Predefined. */ -/* USART_BSEL2_bp Predefined. */ -/* USART_BSEL3_bm Predefined. */ -/* USART_BSEL3_bp Predefined. */ - - -/* SPI - Serial Peripheral Interface */ -/* SPI.CTRL bit masks and bit positions */ -#define SPI_CLK2X_bm 0x80 /* Enable Double Speed bit mask. */ -#define SPI_CLK2X_bp 7 /* Enable Double Speed bit position. */ - -#define SPI_ENABLE_bm 0x40 /* Enable Module bit mask. */ -#define SPI_ENABLE_bp 6 /* Enable Module bit position. */ - -#define SPI_DORD_bm 0x20 /* Data Order Setting bit mask. */ -#define SPI_DORD_bp 5 /* Data Order Setting bit position. */ - -#define SPI_MASTER_bm 0x10 /* Master Operation Enable bit mask. */ -#define SPI_MASTER_bp 4 /* Master Operation Enable bit position. */ - -#define SPI_MODE_gm 0x0C /* SPI Mode group mask. */ -#define SPI_MODE_gp 2 /* SPI Mode group position. */ -#define SPI_MODE0_bm (1<<2) /* SPI Mode bit 0 mask. */ -#define SPI_MODE0_bp 2 /* SPI Mode bit 0 position. */ -#define SPI_MODE1_bm (1<<3) /* SPI Mode bit 1 mask. */ -#define SPI_MODE1_bp 3 /* SPI Mode bit 1 position. */ - -#define SPI_PRESCALER_gm 0x03 /* Prescaler group mask. */ -#define SPI_PRESCALER_gp 0 /* Prescaler group position. */ -#define SPI_PRESCALER0_bm (1<<0) /* Prescaler bit 0 mask. */ -#define SPI_PRESCALER0_bp 0 /* Prescaler bit 0 position. */ -#define SPI_PRESCALER1_bm (1<<1) /* Prescaler bit 1 mask. */ -#define SPI_PRESCALER1_bp 1 /* Prescaler bit 1 position. */ - - -/* SPI.INTCTRL bit masks and bit positions */ -#define SPI_INTLVL_gm 0x03 /* Interrupt level group mask. */ -#define SPI_INTLVL_gp 0 /* Interrupt level group position. */ -#define SPI_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */ -#define SPI_INTLVL0_bp 0 /* Interrupt level bit 0 position. */ -#define SPI_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */ -#define SPI_INTLVL1_bp 1 /* Interrupt level bit 1 position. */ - - -/* SPI.STATUS bit masks and bit positions */ -#define SPI_IF_bm 0x80 /* Interrupt Flag bit mask. */ -#define SPI_IF_bp 7 /* Interrupt Flag bit position. */ - -#define SPI_WRCOL_bm 0x40 /* Write Collision bit mask. */ -#define SPI_WRCOL_bp 6 /* Write Collision bit position. */ - - -/* IRCOM - IR Communication Module */ -/* IRCOM.CTRL bit masks and bit positions */ -#define IRCOM_EVSEL_gm 0x0F /* Event Channel Select group mask. */ -#define IRCOM_EVSEL_gp 0 /* Event Channel Select group position. */ -#define IRCOM_EVSEL0_bm (1<<0) /* Event Channel Select bit 0 mask. */ -#define IRCOM_EVSEL0_bp 0 /* Event Channel Select bit 0 position. */ -#define IRCOM_EVSEL1_bm (1<<1) /* Event Channel Select bit 1 mask. */ -#define IRCOM_EVSEL1_bp 1 /* Event Channel Select bit 1 position. */ -#define IRCOM_EVSEL2_bm (1<<2) /* Event Channel Select bit 2 mask. */ -#define IRCOM_EVSEL2_bp 2 /* Event Channel Select bit 2 position. */ -#define IRCOM_EVSEL3_bm (1<<3) /* Event Channel Select bit 3 mask. */ -#define IRCOM_EVSEL3_bp 3 /* Event Channel Select bit 3 position. */ - - -/* AES - AES Module */ -/* AES.CTRL bit masks and bit positions */ -#define AES_START_bm 0x80 /* Start/Run bit mask. */ -#define AES_START_bp 7 /* Start/Run bit position. */ - -#define AES_AUTO_bm 0x40 /* Auto Start Trigger bit mask. */ -#define AES_AUTO_bp 6 /* Auto Start Trigger bit position. */ - -#define AES_RESET_bm 0x20 /* AES Software Reset bit mask. */ -#define AES_RESET_bp 5 /* AES Software Reset bit position. */ - -#define AES_DECRYPT_bm 0x10 /* Decryption / Direction bit mask. */ -#define AES_DECRYPT_bp 4 /* Decryption / Direction bit position. */ - -#define AES_XOR_bm 0x04 /* State XOR Load Enable bit mask. */ -#define AES_XOR_bp 2 /* State XOR Load Enable bit position. */ - - -/* AES.STATUS bit masks and bit positions */ -#define AES_ERROR_bm 0x80 /* AES Error bit mask. */ -#define AES_ERROR_bp 7 /* AES Error bit position. */ - -#define AES_SRIF_bm 0x01 /* State Ready Interrupt Flag bit mask. */ -#define AES_SRIF_bp 0 /* State Ready Interrupt Flag bit position. */ - - -/* AES.INTCTRL bit masks and bit positions */ -#define AES_INTLVL_gm 0x03 /* Interrupt level group mask. */ -#define AES_INTLVL_gp 0 /* Interrupt level group position. */ -#define AES_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */ -#define AES_INTLVL0_bp 0 /* Interrupt level bit 0 position. */ -#define AES_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */ -#define AES_INTLVL1_bp 1 /* Interrupt level bit 1 position. */ - - - -// Generic Port Pins - -#define PIN0_bm 0x01 -#define PIN0_bp 0 -#define PIN1_bm 0x02 -#define PIN1_bp 1 -#define PIN2_bm 0x04 -#define PIN2_bp 2 -#define PIN3_bm 0x08 -#define PIN3_bp 3 -#define PIN4_bm 0x10 -#define PIN4_bp 4 -#define PIN5_bm 0x20 -#define PIN5_bp 5 -#define PIN6_bm 0x40 -#define PIN6_bp 6 -#define PIN7_bm 0x80 -#define PIN7_bp 7 - - -/* ========== Interrupt Vector Definitions ========== */ -/* Vector 0 is the reset vector */ - -/* OSC interrupt vectors */ -#define OSC_XOSCF_vect_num 1 -#define OSC_XOSCF_vect _VECTOR(1) /* External Oscillator Failure Interrupt (NMI) */ - -/* PORTC interrupt vectors */ -#define PORTC_INT0_vect_num 2 -#define PORTC_INT0_vect _VECTOR(2) /* External Interrupt 0 */ -#define PORTC_INT1_vect_num 3 -#define PORTC_INT1_vect _VECTOR(3) /* External Interrupt 1 */ - -/* PORTR interrupt vectors */ -#define PORTR_INT0_vect_num 4 -#define PORTR_INT0_vect _VECTOR(4) /* External Interrupt 0 */ -#define PORTR_INT1_vect_num 5 -#define PORTR_INT1_vect _VECTOR(5) /* External Interrupt 1 */ - -/* DMA interrupt vectors */ -#define DMA_CH0_vect_num 6 -#define DMA_CH0_vect _VECTOR(6) /* Channel 0 Interrupt */ -#define DMA_CH1_vect_num 7 -#define DMA_CH1_vect _VECTOR(7) /* Channel 1 Interrupt */ -#define DMA_CH2_vect_num 8 -#define DMA_CH2_vect _VECTOR(8) /* Channel 2 Interrupt */ -#define DMA_CH3_vect_num 9 -#define DMA_CH3_vect _VECTOR(9) /* Channel 3 Interrupt */ - -/* RTC interrupt vectors */ -#define RTC_OVF_vect_num 10 -#define RTC_OVF_vect _VECTOR(10) /* Overflow Interrupt */ -#define RTC_COMP_vect_num 11 -#define RTC_COMP_vect _VECTOR(11) /* Compare Interrupt */ - -/* TWIC interrupt vectors */ -#define TWIC_TWIS_vect_num 12 -#define TWIC_TWIS_vect _VECTOR(12) /* TWI Slave Interrupt */ -#define TWIC_TWIM_vect_num 13 -#define TWIC_TWIM_vect _VECTOR(13) /* TWI Master Interrupt */ - -/* TCC0 interrupt vectors */ -#define TCC0_OVF_vect_num 14 -#define TCC0_OVF_vect _VECTOR(14) /* Overflow Interrupt */ -#define TCC0_ERR_vect_num 15 -#define TCC0_ERR_vect _VECTOR(15) /* Error Interrupt */ -#define TCC0_CCA_vect_num 16 -#define TCC0_CCA_vect _VECTOR(16) /* Compare or Capture A Interrupt */ -#define TCC0_CCB_vect_num 17 -#define TCC0_CCB_vect _VECTOR(17) /* Compare or Capture B Interrupt */ -#define TCC0_CCC_vect_num 18 -#define TCC0_CCC_vect _VECTOR(18) /* Compare or Capture C Interrupt */ -#define TCC0_CCD_vect_num 19 -#define TCC0_CCD_vect _VECTOR(19) /* Compare or Capture D Interrupt */ - -/* TCC1 interrupt vectors */ -#define TCC1_OVF_vect_num 20 -#define TCC1_OVF_vect _VECTOR(20) /* Overflow Interrupt */ -#define TCC1_ERR_vect_num 21 -#define TCC1_ERR_vect _VECTOR(21) /* Error Interrupt */ -#define TCC1_CCA_vect_num 22 -#define TCC1_CCA_vect _VECTOR(22) /* Compare or Capture A Interrupt */ -#define TCC1_CCB_vect_num 23 -#define TCC1_CCB_vect _VECTOR(23) /* Compare or Capture B Interrupt */ - -/* SPIC interrupt vectors */ -#define SPIC_INT_vect_num 24 -#define SPIC_INT_vect _VECTOR(24) /* SPI Interrupt */ - -/* USARTC0 interrupt vectors */ -#define USARTC0_RXC_vect_num 25 -#define USARTC0_RXC_vect _VECTOR(25) /* Reception Complete Interrupt */ -#define USARTC0_DRE_vect_num 26 -#define USARTC0_DRE_vect _VECTOR(26) /* Data Register Empty Interrupt */ -#define USARTC0_TXC_vect_num 27 -#define USARTC0_TXC_vect _VECTOR(27) /* Transmission Complete Interrupt */ - -/* USARTC1 interrupt vectors */ -#define USARTC1_RXC_vect_num 28 -#define USARTC1_RXC_vect _VECTOR(28) /* Reception Complete Interrupt */ -#define USARTC1_DRE_vect_num 29 -#define USARTC1_DRE_vect _VECTOR(29) /* Data Register Empty Interrupt */ -#define USARTC1_TXC_vect_num 30 -#define USARTC1_TXC_vect _VECTOR(30) /* Transmission Complete Interrupt */ - -/* AES interrupt vectors */ -#define AES_INT_vect_num 31 -#define AES_INT_vect _VECTOR(31) /* AES Interrupt */ - -/* NVM interrupt vectors */ -#define NVM_EE_vect_num 32 -#define NVM_EE_vect _VECTOR(32) /* EE Interrupt */ -#define NVM_SPM_vect_num 33 -#define NVM_SPM_vect _VECTOR(33) /* SPM Interrupt */ - -/* PORTB interrupt vectors */ -#define PORTB_INT0_vect_num 34 -#define PORTB_INT0_vect _VECTOR(34) /* External Interrupt 0 */ -#define PORTB_INT1_vect_num 35 -#define PORTB_INT1_vect _VECTOR(35) /* External Interrupt 1 */ - -/* ACB interrupt vectors */ -#define ACB_AC0_vect_num 36 -#define ACB_AC0_vect _VECTOR(36) /* AC0 Interrupt */ -#define ACB_AC1_vect_num 37 -#define ACB_AC1_vect _VECTOR(37) /* AC1 Interrupt */ -#define ACB_ACW_vect_num 38 -#define ACB_ACW_vect _VECTOR(38) /* ACW Window Mode Interrupt */ - -/* ADCB interrupt vectors */ -#define ADCB_CH0_vect_num 39 -#define ADCB_CH0_vect _VECTOR(39) /* Interrupt 0 */ -#define ADCB_CH1_vect_num 40 -#define ADCB_CH1_vect _VECTOR(40) /* Interrupt 1 */ -#define ADCB_CH2_vect_num 41 -#define ADCB_CH2_vect _VECTOR(41) /* Interrupt 2 */ -#define ADCB_CH3_vect_num 42 -#define ADCB_CH3_vect _VECTOR(42) /* Interrupt 3 */ - -/* PORTE interrupt vectors */ -#define PORTE_INT0_vect_num 43 -#define PORTE_INT0_vect _VECTOR(43) /* External Interrupt 0 */ -#define PORTE_INT1_vect_num 44 -#define PORTE_INT1_vect _VECTOR(44) /* External Interrupt 1 */ - -/* TWIE interrupt vectors */ -#define TWIE_TWIS_vect_num 45 -#define TWIE_TWIS_vect _VECTOR(45) /* TWI Slave Interrupt */ -#define TWIE_TWIM_vect_num 46 -#define TWIE_TWIM_vect _VECTOR(46) /* TWI Master Interrupt */ - -/* TCE0 interrupt vectors */ -#define TCE0_OVF_vect_num 47 -#define TCE0_OVF_vect _VECTOR(47) /* Overflow Interrupt */ -#define TCE0_ERR_vect_num 48 -#define TCE0_ERR_vect _VECTOR(48) /* Error Interrupt */ -#define TCE0_CCA_vect_num 49 -#define TCE0_CCA_vect _VECTOR(49) /* Compare or Capture A Interrupt */ -#define TCE0_CCB_vect_num 50 -#define TCE0_CCB_vect _VECTOR(50) /* Compare or Capture B Interrupt */ -#define TCE0_CCC_vect_num 51 -#define TCE0_CCC_vect _VECTOR(51) /* Compare or Capture C Interrupt */ -#define TCE0_CCD_vect_num 52 -#define TCE0_CCD_vect _VECTOR(52) /* Compare or Capture D Interrupt */ - -/* TCE1 interrupt vectors */ -#define TCE1_OVF_vect_num 53 -#define TCE1_OVF_vect _VECTOR(53) /* Overflow Interrupt */ -#define TCE1_ERR_vect_num 54 -#define TCE1_ERR_vect _VECTOR(54) /* Error Interrupt */ -#define TCE1_CCA_vect_num 55 -#define TCE1_CCA_vect _VECTOR(55) /* Compare or Capture A Interrupt */ -#define TCE1_CCB_vect_num 56 -#define TCE1_CCB_vect _VECTOR(56) /* Compare or Capture B Interrupt */ - -/* SPIE interrupt vectors */ -#define SPIE_INT_vect_num 57 -#define SPIE_INT_vect _VECTOR(57) /* SPI Interrupt */ - -/* USARTE0 interrupt vectors */ -#define USARTE0_RXC_vect_num 58 -#define USARTE0_RXC_vect _VECTOR(58) /* Reception Complete Interrupt */ -#define USARTE0_DRE_vect_num 59 -#define USARTE0_DRE_vect _VECTOR(59) /* Data Register Empty Interrupt */ -#define USARTE0_TXC_vect_num 60 -#define USARTE0_TXC_vect _VECTOR(60) /* Transmission Complete Interrupt */ - -/* USARTE1 interrupt vectors */ -#define USARTE1_RXC_vect_num 61 -#define USARTE1_RXC_vect _VECTOR(61) /* Reception Complete Interrupt */ -#define USARTE1_DRE_vect_num 62 -#define USARTE1_DRE_vect _VECTOR(62) /* Data Register Empty Interrupt */ -#define USARTE1_TXC_vect_num 63 -#define USARTE1_TXC_vect _VECTOR(63) /* Transmission Complete Interrupt */ - -/* PORTD interrupt vectors */ -#define PORTD_INT0_vect_num 64 -#define PORTD_INT0_vect _VECTOR(64) /* External Interrupt 0 */ -#define PORTD_INT1_vect_num 65 -#define PORTD_INT1_vect _VECTOR(65) /* External Interrupt 1 */ - -/* PORTA interrupt vectors */ -#define PORTA_INT0_vect_num 66 -#define PORTA_INT0_vect _VECTOR(66) /* External Interrupt 0 */ -#define PORTA_INT1_vect_num 67 -#define PORTA_INT1_vect _VECTOR(67) /* External Interrupt 1 */ - -/* ACA interrupt vectors */ -#define ACA_AC0_vect_num 68 -#define ACA_AC0_vect _VECTOR(68) /* AC0 Interrupt */ -#define ACA_AC1_vect_num 69 -#define ACA_AC1_vect _VECTOR(69) /* AC1 Interrupt */ -#define ACA_ACW_vect_num 70 -#define ACA_ACW_vect _VECTOR(70) /* ACW Window Mode Interrupt */ - -/* ADCA interrupt vectors */ -#define ADCA_CH0_vect_num 71 -#define ADCA_CH0_vect _VECTOR(71) /* Interrupt 0 */ -#define ADCA_CH1_vect_num 72 -#define ADCA_CH1_vect _VECTOR(72) /* Interrupt 1 */ -#define ADCA_CH2_vect_num 73 -#define ADCA_CH2_vect _VECTOR(73) /* Interrupt 2 */ -#define ADCA_CH3_vect_num 74 -#define ADCA_CH3_vect _VECTOR(74) /* Interrupt 3 */ - -/* TCD0 interrupt vectors */ -#define TCD0_OVF_vect_num 77 -#define TCD0_OVF_vect _VECTOR(77) /* Overflow Interrupt */ -#define TCD0_ERR_vect_num 78 -#define TCD0_ERR_vect _VECTOR(78) /* Error Interrupt */ -#define TCD0_CCA_vect_num 79 -#define TCD0_CCA_vect _VECTOR(79) /* Compare or Capture A Interrupt */ -#define TCD0_CCB_vect_num 80 -#define TCD0_CCB_vect _VECTOR(80) /* Compare or Capture B Interrupt */ -#define TCD0_CCC_vect_num 81 -#define TCD0_CCC_vect _VECTOR(81) /* Compare or Capture C Interrupt */ -#define TCD0_CCD_vect_num 82 -#define TCD0_CCD_vect _VECTOR(82) /* Compare or Capture D Interrupt */ - -/* TCD1 interrupt vectors */ -#define TCD1_OVF_vect_num 83 -#define TCD1_OVF_vect _VECTOR(83) /* Overflow Interrupt */ -#define TCD1_ERR_vect_num 84 -#define TCD1_ERR_vect _VECTOR(84) /* Error Interrupt */ -#define TCD1_CCA_vect_num 85 -#define TCD1_CCA_vect _VECTOR(85) /* Compare or Capture A Interrupt */ -#define TCD1_CCB_vect_num 86 -#define TCD1_CCB_vect _VECTOR(86) /* Compare or Capture B Interrupt */ - -/* SPID interrupt vectors */ -#define SPID_INT_vect_num 87 -#define SPID_INT_vect _VECTOR(87) /* SPI Interrupt */ - -/* USARTD0 interrupt vectors */ -#define USARTD0_RXC_vect_num 88 -#define USARTD0_RXC_vect _VECTOR(88) /* Reception Complete Interrupt */ -#define USARTD0_DRE_vect_num 89 -#define USARTD0_DRE_vect _VECTOR(89) /* Data Register Empty Interrupt */ -#define USARTD0_TXC_vect_num 90 -#define USARTD0_TXC_vect _VECTOR(90) /* Transmission Complete Interrupt */ - -/* USARTD1 interrupt vectors */ -#define USARTD1_RXC_vect_num 91 -#define USARTD1_RXC_vect _VECTOR(91) /* Reception Complete Interrupt */ -#define USARTD1_DRE_vect_num 92 -#define USARTD1_DRE_vect _VECTOR(92) /* Data Register Empty Interrupt */ -#define USARTD1_TXC_vect_num 93 -#define USARTD1_TXC_vect _VECTOR(93) /* Transmission Complete Interrupt */ - -/* PORTF interrupt vectors */ -#define PORTF_INT0_vect_num 104 -#define PORTF_INT0_vect _VECTOR(104) /* External Interrupt 0 */ -#define PORTF_INT1_vect_num 105 -#define PORTF_INT1_vect _VECTOR(105) /* External Interrupt 1 */ - -/* TCF0 interrupt vectors */ -#define TCF0_OVF_vect_num 108 -#define TCF0_OVF_vect _VECTOR(108) /* Overflow Interrupt */ -#define TCF0_ERR_vect_num 109 -#define TCF0_ERR_vect _VECTOR(109) /* Error Interrupt */ -#define TCF0_CCA_vect_num 110 -#define TCF0_CCA_vect _VECTOR(110) /* Compare or Capture A Interrupt */ -#define TCF0_CCB_vect_num 111 -#define TCF0_CCB_vect _VECTOR(111) /* Compare or Capture B Interrupt */ -#define TCF0_CCC_vect_num 112 -#define TCF0_CCC_vect _VECTOR(112) /* Compare or Capture C Interrupt */ -#define TCF0_CCD_vect_num 113 -#define TCF0_CCD_vect _VECTOR(113) /* Compare or Capture D Interrupt */ - -/* USARTF0 interrupt vectors */ -#define USARTF0_RXC_vect_num 119 -#define USARTF0_RXC_vect _VECTOR(119) /* Reception Complete Interrupt */ -#define USARTF0_DRE_vect_num 120 -#define USARTF0_DRE_vect _VECTOR(120) /* Data Register Empty Interrupt */ -#define USARTF0_TXC_vect_num 121 -#define USARTF0_TXC_vect _VECTOR(121) /* Transmission Complete Interrupt */ - - -#define _VECTOR_SIZE 4 /* Size of individual vector. */ -#define _VECTORS_SIZE (122 * _VECTOR_SIZE) - - -/* ========== Constants ========== */ - -#define PROGMEM_START (0x0000) -#define PROGMEM_SIZE (204800) -#define PROGMEM_PAGE_SIZE (512) -#define PROGMEM_END (PROGMEM_START + PROGMEM_SIZE - 1) - -#define APP_SECTION_START (0x0000) -#define APP_SECTION_SIZE (196608) -#define APP_SECTION_PAGE_SIZE (512) -#define APP_SECTION_END (APP_SECTION_START + APP_SECTION_SIZE - 1) - -#define APPTABLE_SECTION_START (0x2E000) -#define APPTABLE_SECTION_SIZE (8192) -#define APPTABLE_SECTION_PAGE_SIZE (512) -#define APPTABLE_SECTION_END (APPTABLE_SECTION_START + APPTABLE_SECTION_SIZE - 1) - -#define BOOT_SECTION_START (0x30000) -#define BOOT_SECTION_SIZE (8192) -#define BOOT_SECTION_PAGE_SIZE (512) -#define BOOT_SECTION_END (BOOT_SECTION_START + BOOT_SECTION_SIZE - 1) - -#define DATAMEM_START (0x0000) -#define DATAMEM_SIZE (16777216) -#define DATAMEM_PAGE_SIZE (0) -#define DATAMEM_END (DATAMEM_START + DATAMEM_SIZE - 1) - -#define IO_START (0x0000) -#define IO_SIZE (4096) -#define IO_PAGE_SIZE (0) -#define IO_END (IO_START + IO_SIZE - 1) - -#define MAPPED_EEPROM_START (0x1000) -#define MAPPED_EEPROM_SIZE (2048) -#define MAPPED_EEPROM_PAGE_SIZE (0) -#define MAPPED_EEPROM_END (MAPPED_EEPROM_START + MAPPED_EEPROM_SIZE - 1) - -#define INTERNAL_SRAM_START (0x2000) -#define INTERNAL_SRAM_SIZE (16384) -#define INTERNAL_SRAM_PAGE_SIZE (0) -#define INTERNAL_SRAM_END (INTERNAL_SRAM_START + INTERNAL_SRAM_SIZE - 1) - -#define EEPROM_START (0x0000) -#define EEPROM_SIZE (2048) -#define EEPROM_PAGE_SIZE (32) -#define EEPROM_END (EEPROM_START + EEPROM_SIZE - 1) - -#define FUSE_START (0x0000) -#define FUSE_SIZE (6) -#define FUSE_PAGE_SIZE (0) -#define FUSE_END (FUSE_START + FUSE_SIZE - 1) - -#define LOCKBIT_START (0x0000) -#define LOCKBIT_SIZE (1) -#define LOCKBIT_PAGE_SIZE (0) -#define LOCKBIT_END (LOCKBIT_START + LOCKBIT_SIZE - 1) - -#define SIGNATURES_START (0x0000) -#define SIGNATURES_SIZE (3) -#define SIGNATURES_PAGE_SIZE (0) -#define SIGNATURES_END (SIGNATURES_START + SIGNATURES_SIZE - 1) - -#define USER_SIGNATURES_START (0x0000) -#define USER_SIGNATURES_SIZE (512) -#define USER_SIGNATURES_PAGE_SIZE (0) -#define USER_SIGNATURES_END (USER_SIGNATURES_START + USER_SIGNATURES_SIZE - 1) - -#define PROD_SIGNATURES_START (0x0000) -#define PROD_SIGNATURES_SIZE (52) -#define PROD_SIGNATURES_PAGE_SIZE (0) -#define PROD_SIGNATURES_END (PROD_SIGNATURES_START + PROD_SIGNATURES_SIZE - 1) - -#define FLASHEND PROGMEM_END -#define SPM_PAGESIZE PROGMEM_PAGE_SIZE -#define RAMSTART INTERNAL_SRAM_START -#define RAMSIZE INTERNAL_SRAM_SIZE -#define RAMEND INTERNAL_SRAM_END -#define XRAMSTART EXTERNAL_SRAM_START -#define XRAMSIZE EXTERNAL_SRAM_SIZE -#define XRAMEND INTERNAL_SRAM_END -#define E2END EEPROM_END -#define E2PAGESIZE EEPROM_PAGE_SIZE - - -/* ========== Fuses ========== */ -#define FUSE_MEMORY_SIZE 6 - -/* Fuse Byte 0 */ -#define FUSE_JTAGUSERID0 (unsigned char)~_BV(0) /* JTAG User ID Bit 0 */ -#define FUSE_JTAGUSERID1 (unsigned char)~_BV(1) /* JTAG User ID Bit 1 */ -#define FUSE_JTAGUSERID2 (unsigned char)~_BV(2) /* JTAG User ID Bit 2 */ -#define FUSE_JTAGUSERID3 (unsigned char)~_BV(3) /* JTAG User ID Bit 3 */ -#define FUSE_JTAGUSERID4 (unsigned char)~_BV(4) /* JTAG User ID Bit 4 */ -#define FUSE_JTAGUSERID5 (unsigned char)~_BV(5) /* JTAG User ID Bit 5 */ -#define FUSE_JTAGUSERID6 (unsigned char)~_BV(6) /* JTAG User ID Bit 6 */ -#define FUSE_JTAGUSERID7 (unsigned char)~_BV(7) /* JTAG User ID Bit 7 */ -#define FUSE0_DEFAULT (0xFF) - -/* Fuse Byte 1 */ -#define FUSE_WDP0 (unsigned char)~_BV(0) /* Watchdog Timeout Period Bit 0 */ -#define FUSE_WDP1 (unsigned char)~_BV(1) /* Watchdog Timeout Period Bit 1 */ -#define FUSE_WDP2 (unsigned char)~_BV(2) /* Watchdog Timeout Period Bit 2 */ -#define FUSE_WDP3 (unsigned char)~_BV(3) /* Watchdog Timeout Period Bit 3 */ -#define FUSE_WDWP0 (unsigned char)~_BV(4) /* Watchdog Window Timeout Period Bit 0 */ -#define FUSE_WDWP1 (unsigned char)~_BV(5) /* Watchdog Window Timeout Period Bit 1 */ -#define FUSE_WDWP2 (unsigned char)~_BV(6) /* Watchdog Window Timeout Period Bit 2 */ -#define FUSE_WDWP3 (unsigned char)~_BV(7) /* Watchdog Window Timeout Period Bit 3 */ -#define FUSE1_DEFAULT (0xFF) - -/* Fuse Byte 2 */ -#define FUSE_BODPD0 (unsigned char)~_BV(0) /* BOD Operation in Power-Down Mode Bit 0 */ -#define FUSE_BODPD1 (unsigned char)~_BV(1) /* BOD Operation in Power-Down Mode Bit 1 */ -#define FUSE_BOOTRST (unsigned char)~_BV(6) /* Boot Loader Section Reset Vector */ -#define FUSE_DVSDON (unsigned char)~_BV(7) /* Spike Detector Enable */ -#define FUSE2_DEFAULT (0xFF) - -/* Fuse Byte 3 Reserved */ - -/* Fuse Byte 4 */ -#define FUSE_JTAGEN (unsigned char)~_BV(0) /* JTAG Interface Enable */ -#define FUSE_WDLOCK (unsigned char)~_BV(1) /* Watchdog Timer Lock */ -#define FUSE_SUT0 (unsigned char)~_BV(2) /* Start-up Time Bit 0 */ -#define FUSE_SUT1 (unsigned char)~_BV(3) /* Start-up Time Bit 1 */ -#define FUSE4_DEFAULT (0xFF) - -/* Fuse Byte 5 */ -#define FUSE_BODLVL0 (unsigned char)~_BV(0) /* Brown Out Detection Voltage Level Bit 0 */ -#define FUSE_BODLVL1 (unsigned char)~_BV(1) /* Brown Out Detection Voltage Level Bit 1 */ -#define FUSE_BODLVL2 (unsigned char)~_BV(2) /* Brown Out Detection Voltage Level Bit 2 */ -#define FUSE_EESAVE (unsigned char)~_BV(3) /* Preserve EEPROM Through Chip Erase */ -#define FUSE_BODACT0 (unsigned char)~_BV(4) /* BOD Operation in Active Mode Bit 0 */ -#define FUSE_BODACT1 (unsigned char)~_BV(5) /* BOD Operation in Active Mode Bit 1 */ -#define FUSE5_DEFAULT (0xFF) - - -/* ========== Lock Bits ========== */ -#define __LOCK_BITS_EXIST -#define __BOOT_LOCK_APPLICATION_TABLE_BITS_EXIST -#define __BOOT_LOCK_APPLICATION_BITS_EXIST -#define __BOOT_LOCK_BOOT_BITS_EXIST - - -/* ========== Signature ========== */ -#define SIGNATURE_0 0x1E -#define SIGNATURE_1 0x97 -#define SIGNATURE_2 0x44 - -/* ========== Power Reduction Condition Definitions ========== */ - -/* PR.PRGEN */ -#define __AVR_HAVE_PRGEN (PR_AES_bm|PR_EBI_bm|PR_RTC_bm|PR_EVSYS_bm|PR_DMA_bm) -#define __AVR_HAVE_PRGEN_AES -#define __AVR_HAVE_PRGEN_EBI -#define __AVR_HAVE_PRGEN_RTC -#define __AVR_HAVE_PRGEN_EVSYS -#define __AVR_HAVE_PRGEN_DMA - -/* PR.PRPA */ -#define __AVR_HAVE_PRPA (PR_DAC_bm|PR_ADC_bm|PR_AC_bm) -#define __AVR_HAVE_PRPA_DAC -#define __AVR_HAVE_PRPA_ADC -#define __AVR_HAVE_PRPA_AC - -/* PR.PRPB */ -#define __AVR_HAVE_PRPB (PR_DAC_bm|PR_ADC_bm|PR_AC_bm) -#define __AVR_HAVE_PRPB_DAC -#define __AVR_HAVE_PRPB_ADC -#define __AVR_HAVE_PRPB_AC - -/* PR.PRPC */ -#define __AVR_HAVE_PRPC (PR_TWI_bm|PR_USART1_bm|PR_USART0_bm|PR_SPI_bm|PR_HIRES_bm|PR_TC1_bm|PR_TC0_bm) -#define __AVR_HAVE_PRPC_TWI -#define __AVR_HAVE_PRPC_USART1 -#define __AVR_HAVE_PRPC_USART0 -#define __AVR_HAVE_PRPC_SPI -#define __AVR_HAVE_PRPC_HIRES -#define __AVR_HAVE_PRPC_TC1 -#define __AVR_HAVE_PRPC_TC0 - -/* PR.PRPD */ -#define __AVR_HAVE_PRPD (PR_TWI_bm|PR_USART1_bm|PR_USART0_bm|PR_SPI_bm|PR_HIRES_bm|PR_TC1_bm|PR_TC0_bm) -#define __AVR_HAVE_PRPD_TWI -#define __AVR_HAVE_PRPD_USART1 -#define __AVR_HAVE_PRPD_USART0 -#define __AVR_HAVE_PRPD_SPI -#define __AVR_HAVE_PRPD_HIRES -#define __AVR_HAVE_PRPD_TC1 -#define __AVR_HAVE_PRPD_TC0 - -/* PR.PRPE */ -#define __AVR_HAVE_PRPE (PR_TWI_bm|PR_USART1_bm|PR_USART0_bm|PR_SPI_bm|PR_HIRES_bm|PR_TC1_bm|PR_TC0_bm) -#define __AVR_HAVE_PRPE_TWI -#define __AVR_HAVE_PRPE_USART1 -#define __AVR_HAVE_PRPE_USART0 -#define __AVR_HAVE_PRPE_SPI -#define __AVR_HAVE_PRPE_HIRES -#define __AVR_HAVE_PRPE_TC1 -#define __AVR_HAVE_PRPE_TC0 - -/* PR.PRPF */ -#define __AVR_HAVE_PRPF (PR_TWI_bm|PR_USART1_bm|PR_USART0_bm|PR_SPI_bm|PR_HIRES_bm|PR_TC1_bm|PR_TC0_bm) -#define __AVR_HAVE_PRPF_TWI -#define __AVR_HAVE_PRPF_USART1 -#define __AVR_HAVE_PRPF_USART0 -#define __AVR_HAVE_PRPF_SPI -#define __AVR_HAVE_PRPF_HIRES -#define __AVR_HAVE_PRPF_TC1 -#define __AVR_HAVE_PRPF_TC0 - - -#endif /* _AVR_ATxmega192A3_H_ */ - diff --git a/arduino/hardware/tools/avr/avr/include/avr/iox192a3u.h b/arduino/hardware/tools/avr/avr/include/avr/iox192a3u.h deleted file mode 100644 index bd53330..0000000 --- a/arduino/hardware/tools/avr/avr/include/avr/iox192a3u.h +++ /dev/null @@ -1,7697 +0,0 @@ -/***************************************************************************** - * - * Copyright (C) 2015 Atmel Corporation - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * - * * Neither the name of the copyright holders nor the names of - * contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - ****************************************************************************/ - - -#ifndef _AVR_IO_H_ -# error "Include instead of this file." -#endif - -#ifndef _AVR_IOXXX_H_ -# define _AVR_IOXXX_H_ "iox192a3u.h" -#else -# error "Attempt to include more than one file." -#endif - -#ifndef _AVR_ATXMEGA192A3U_H_INCLUDED -#define _AVR_ATXMEGA192A3U_H_INCLUDED - -/* Ungrouped common registers */ -#define GPIOR0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ -#define GPIOR1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ -#define GPIOR2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ -#define GPIOR3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ -#define GPIOR4 _SFR_MEM8(0x0004) /* General Purpose IO Register 4 */ -#define GPIOR5 _SFR_MEM8(0x0005) /* General Purpose IO Register 5 */ -#define GPIOR6 _SFR_MEM8(0x0006) /* General Purpose IO Register 6 */ -#define GPIOR7 _SFR_MEM8(0x0007) /* General Purpose IO Register 7 */ -#define GPIOR8 _SFR_MEM8(0x0008) /* General Purpose IO Register 8 */ -#define GPIOR9 _SFR_MEM8(0x0009) /* General Purpose IO Register 9 */ -#define GPIORA _SFR_MEM8(0x000A) /* General Purpose IO Register 10 */ -#define GPIORB _SFR_MEM8(0x000B) /* General Purpose IO Register 11 */ -#define GPIORC _SFR_MEM8(0x000C) /* General Purpose IO Register 12 */ -#define GPIORD _SFR_MEM8(0x000D) /* General Purpose IO Register 13 */ -#define GPIORE _SFR_MEM8(0x000E) /* General Purpose IO Register 14 */ -#define GPIORF _SFR_MEM8(0x000F) /* General Purpose IO Register 15 */ - -/* Deprecated */ -#define GPIO0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ -#define GPIO1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ -#define GPIO2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ -#define GPIO3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ -#define GPIO4 _SFR_MEM8(0x0004) /* General Purpose IO Register 4 */ -#define GPIO5 _SFR_MEM8(0x0005) /* General Purpose IO Register 5 */ -#define GPIO6 _SFR_MEM8(0x0006) /* General Purpose IO Register 6 */ -#define GPIO7 _SFR_MEM8(0x0007) /* General Purpose IO Register 7 */ -#define GPIO8 _SFR_MEM8(0x0008) /* General Purpose IO Register 8 */ -#define GPIO9 _SFR_MEM8(0x0009) /* General Purpose IO Register 9 */ -#define GPIOA _SFR_MEM8(0x000A) /* General Purpose IO Register 10 */ -#define GPIOB _SFR_MEM8(0x000B) /* General Purpose IO Register 11 */ -#define GPIOC _SFR_MEM8(0x000C) /* General Purpose IO Register 12 */ -#define GPIOD _SFR_MEM8(0x000D) /* General Purpose IO Register 13 */ -#define GPIOE _SFR_MEM8(0x000E) /* General Purpose IO Register 14 */ -#define GPIOF _SFR_MEM8(0x000F) /* General Purpose IO Register 15 */ - -#define CCP _SFR_MEM8(0x0034) /* Configuration Change Protection */ -#define RAMPD _SFR_MEM8(0x0038) /* Ramp D */ -#define RAMPX _SFR_MEM8(0x0039) /* Ramp X */ -#define RAMPY _SFR_MEM8(0x003A) /* Ramp Y */ -#define RAMPZ _SFR_MEM8(0x003B) /* Ramp Z */ -#define EIND _SFR_MEM8(0x003C) /* Extended Indirect Jump */ -#define SPL _SFR_MEM8(0x003D) /* Stack Pointer Low */ -#define SPH _SFR_MEM8(0x003E) /* Stack Pointer High */ -#define SREG _SFR_MEM8(0x003F) /* Status Register */ - -/* C Language Only */ -#if !defined (__ASSEMBLER__) - -#include - -typedef volatile uint8_t register8_t; -typedef volatile uint16_t register16_t; -typedef volatile uint32_t register32_t; - - -#ifdef _WORDREGISTER -#undef _WORDREGISTER -#endif -#define _WORDREGISTER(regname) \ - __extension__ union \ - { \ - register16_t regname; \ - struct \ - { \ - register8_t regname ## L; \ - register8_t regname ## H; \ - }; \ - } - -#ifdef _DWORDREGISTER -#undef _DWORDREGISTER -#endif -#define _DWORDREGISTER(regname) \ - __extension__ union \ - { \ - register32_t regname; \ - struct \ - { \ - register8_t regname ## 0; \ - register8_t regname ## 1; \ - register8_t regname ## 2; \ - register8_t regname ## 3; \ - }; \ - } - - -/* -========================================================================== -IO Module Structures -========================================================================== -*/ - - -/* --------------------------------------------------------------------------- -VPORT - Virtual Ports --------------------------------------------------------------------------- -*/ - -/* Virtual Port */ -typedef struct VPORT_struct -{ - register8_t DIR; /* I/O Port Data Direction */ - register8_t OUT; /* I/O Port Output */ - register8_t IN; /* I/O Port Input */ - register8_t INTFLAGS; /* Interrupt Flag Register */ -} VPORT_t; - - -/* --------------------------------------------------------------------------- -XOCD - On-Chip Debug System --------------------------------------------------------------------------- -*/ - -/* On-Chip Debug System */ -typedef struct OCD_struct -{ - register8_t OCDR0; /* OCD Register 0 */ - register8_t OCDR1; /* OCD Register 1 */ -} OCD_t; - - -/* --------------------------------------------------------------------------- -CPU - CPU --------------------------------------------------------------------------- -*/ - -/* CCP signatures */ -typedef enum CCP_enum -{ - CCP_SPM_gc = (0x9D<<0), /* SPM Instruction Protection */ - CCP_IOREG_gc = (0xD8<<0), /* IO Register Protection */ -} CCP_t; - - -/* --------------------------------------------------------------------------- -CLK - Clock System --------------------------------------------------------------------------- -*/ - -/* Clock System */ -typedef struct CLK_struct -{ - register8_t CTRL; /* Control Register */ - register8_t PSCTRL; /* Prescaler Control Register */ - register8_t LOCK; /* Lock register */ - register8_t RTCCTRL; /* RTC Control Register */ - register8_t USBCTRL; /* USB Control Register */ -} CLK_t; - - -/* Power Reduction */ -typedef struct PR_struct -{ - register8_t PRGEN; /* General Power Reduction */ - register8_t PRPA; /* Power Reduction Port A */ - register8_t PRPB; /* Power Reduction Port B */ - register8_t PRPC; /* Power Reduction Port C */ - register8_t PRPD; /* Power Reduction Port D */ - register8_t PRPE; /* Power Reduction Port E */ - register8_t PRPF; /* Power Reduction Port F */ -} PR_t; - -/* System Clock Selection */ -typedef enum CLK_SCLKSEL_enum -{ - CLK_SCLKSEL_RC2M_gc = (0x00<<0), /* Internal 2 MHz RC Oscillator */ - CLK_SCLKSEL_RC32M_gc = (0x01<<0), /* Internal 32 MHz RC Oscillator */ - CLK_SCLKSEL_RC32K_gc = (0x02<<0), /* Internal 32.768 kHz RC Oscillator */ - CLK_SCLKSEL_XOSC_gc = (0x03<<0), /* External Crystal Oscillator or Clock */ - CLK_SCLKSEL_PLL_gc = (0x04<<0), /* Phase Locked Loop */ -} CLK_SCLKSEL_t; - -/* Prescaler A Division Factor */ -typedef enum CLK_PSADIV_enum -{ - CLK_PSADIV_1_gc = (0x00<<2), /* Divide by 1 */ - CLK_PSADIV_2_gc = (0x01<<2), /* Divide by 2 */ - CLK_PSADIV_4_gc = (0x03<<2), /* Divide by 4 */ - CLK_PSADIV_8_gc = (0x05<<2), /* Divide by 8 */ - CLK_PSADIV_16_gc = (0x07<<2), /* Divide by 16 */ - CLK_PSADIV_32_gc = (0x09<<2), /* Divide by 32 */ - CLK_PSADIV_64_gc = (0x0B<<2), /* Divide by 64 */ - CLK_PSADIV_128_gc = (0x0D<<2), /* Divide by 128 */ - CLK_PSADIV_256_gc = (0x0F<<2), /* Divide by 256 */ - CLK_PSADIV_512_gc = (0x11<<2), /* Divide by 512 */ -} CLK_PSADIV_t; - -/* Prescaler B and C Division Factor */ -typedef enum CLK_PSBCDIV_enum -{ - CLK_PSBCDIV_1_1_gc = (0x00<<0), /* Divide B by 1 and C by 1 */ - CLK_PSBCDIV_1_2_gc = (0x01<<0), /* Divide B by 1 and C by 2 */ - CLK_PSBCDIV_4_1_gc = (0x02<<0), /* Divide B by 4 and C by 1 */ - CLK_PSBCDIV_2_2_gc = (0x03<<0), /* Divide B by 2 and C by 2 */ -} CLK_PSBCDIV_t; - -/* RTC Clock Source */ -typedef enum CLK_RTCSRC_enum -{ - CLK_RTCSRC_ULP_gc = (0x00<<1), /* 1.024 kHz from internal 32kHz ULP */ - CLK_RTCSRC_TOSC_gc = (0x01<<1), /* 1.024 kHz from 32.768 kHz crystal oscillator on TOSC */ - CLK_RTCSRC_RCOSC_gc = (0x02<<1), /* 1.024 kHz from internal 32.768 kHz RC oscillator */ - CLK_RTCSRC_TOSC32_gc = (0x05<<1), /* 32.768 kHz from 32.768 kHz crystal oscillator on TOSC */ - CLK_RTCSRC_RCOSC32_gc = (0x06<<1), /* 32.768 kHz from internal 32.768 kHz RC oscillator */ - CLK_RTCSRC_EXTCLK_gc = (0x07<<1), /* External Clock from TOSC1 */ -} CLK_RTCSRC_t; - -/* USB Prescaler Division Factor */ -typedef enum CLK_USBPSDIV_enum -{ - CLK_USBPSDIV_1_gc = (0x00<<3), /* Divide by 1 */ - CLK_USBPSDIV_2_gc = (0x01<<3), /* Divide by 2 */ - CLK_USBPSDIV_4_gc = (0x02<<3), /* Divide by 4 */ - CLK_USBPSDIV_8_gc = (0x03<<3), /* Divide by 8 */ - CLK_USBPSDIV_16_gc = (0x04<<3), /* Divide by 16 */ - CLK_USBPSDIV_32_gc = (0x05<<3), /* Divide by 32 */ -} CLK_USBPSDIV_t; - -/* USB Clock Source */ -typedef enum CLK_USBSRC_enum -{ - CLK_USBSRC_PLL_gc = (0x00<<1), /* PLL */ - CLK_USBSRC_RC32M_gc = (0x01<<1), /* Internal 32 MHz RC Oscillator */ -} CLK_USBSRC_t; - - -/* --------------------------------------------------------------------------- -SLEEP - Sleep Controller --------------------------------------------------------------------------- -*/ - -/* Sleep Controller */ -typedef struct SLEEP_struct -{ - register8_t CTRL; /* Control Register */ -} SLEEP_t; - -/* Sleep Mode */ -typedef enum SLEEP_SMODE_enum -{ - SLEEP_SMODE_IDLE_gc = (0x00<<1), /* Idle mode */ - SLEEP_SMODE_PDOWN_gc = (0x02<<1), /* Power-down Mode */ - SLEEP_SMODE_PSAVE_gc = (0x03<<1), /* Power-save Mode */ - SLEEP_SMODE_STDBY_gc = (0x06<<1), /* Standby Mode */ - SLEEP_SMODE_ESTDBY_gc = (0x07<<1), /* Extended Standby Mode */ -} SLEEP_SMODE_t; - - - -#define SLEEP_MODE_IDLE (0x00<<1) -#define SLEEP_MODE_PWR_DOWN (0x02<<1) -#define SLEEP_MODE_PWR_SAVE (0x03<<1) -#define SLEEP_MODE_STANDBY (0x06<<1) -#define SLEEP_MODE_EXT_STANDBY (0x07<<1) -/* --------------------------------------------------------------------------- -OSC - Oscillator --------------------------------------------------------------------------- -*/ - -/* Oscillator */ -typedef struct OSC_struct -{ - register8_t CTRL; /* Control Register */ - register8_t STATUS; /* Status Register */ - register8_t XOSCCTRL; /* External Oscillator Control Register */ - register8_t XOSCFAIL; /* Oscillator Failure Detection Register */ - register8_t RC32KCAL; /* 32.768 kHz Internal Oscillator Calibration Register */ - register8_t PLLCTRL; /* PLL Control Register */ - register8_t DFLLCTRL; /* DFLL Control Register */ -} OSC_t; - -/* Oscillator Frequency Range */ -typedef enum OSC_FRQRANGE_enum -{ - OSC_FRQRANGE_04TO2_gc = (0x00<<6), /* 0.4 - 2 MHz */ - OSC_FRQRANGE_2TO9_gc = (0x01<<6), /* 2 - 9 MHz */ - OSC_FRQRANGE_9TO12_gc = (0x02<<6), /* 9 - 12 MHz */ - OSC_FRQRANGE_12TO16_gc = (0x03<<6), /* 12 - 16 MHz */ -} OSC_FRQRANGE_t; - -/* External Oscillator Selection and Startup Time */ -typedef enum OSC_XOSCSEL_enum -{ - OSC_XOSCSEL_EXTCLK_gc = (0x00<<0), /* External Clock - 6 CLK */ - OSC_XOSCSEL_32KHz_gc = (0x02<<0), /* 32.768 kHz TOSC - 32K CLK */ - OSC_XOSCSEL_XTAL_256CLK_gc = (0x03<<0), /* 0.4-16 MHz XTAL - 256 CLK */ - OSC_XOSCSEL_XTAL_1KCLK_gc = (0x07<<0), /* 0.4-16 MHz XTAL - 1K CLK */ - OSC_XOSCSEL_XTAL_16KCLK_gc = (0x0B<<0), /* 0.4-16 MHz XTAL - 16K CLK */ -} OSC_XOSCSEL_t; - -/* PLL Clock Source */ -typedef enum OSC_PLLSRC_enum -{ - OSC_PLLSRC_RC2M_gc = (0x00<<6), /* Internal 2 MHz RC Oscillator */ - OSC_PLLSRC_RC32M_gc = (0x02<<6), /* Internal 32 MHz RC Oscillator */ - OSC_PLLSRC_XOSC_gc = (0x03<<6), /* External Oscillator */ -} OSC_PLLSRC_t; - -/* 2 MHz DFLL Calibration Reference */ -typedef enum OSC_RC2MCREF_enum -{ - OSC_RC2MCREF_RC32K_gc = (0x00<<0), /* Internal 32.768 kHz RC Oscillator */ - OSC_RC2MCREF_XOSC32K_gc = (0x01<<0), /* External 32.768 kHz Crystal Oscillator */ -} OSC_RC2MCREF_t; - -/* 32 MHz DFLL Calibration Reference */ -typedef enum OSC_RC32MCREF_enum -{ - OSC_RC32MCREF_RC32K_gc = (0x00<<1), /* Internal 32.768 kHz RC Oscillator */ - OSC_RC32MCREF_XOSC32K_gc = (0x01<<1), /* External 32.768 kHz Crystal Oscillator */ - OSC_RC32MCREF_USBSOF_gc = (0x02<<1), /* USB Start of Frame */ -} OSC_RC32MCREF_t; - - -/* --------------------------------------------------------------------------- -DFLL - DFLL --------------------------------------------------------------------------- -*/ - -/* DFLL */ -typedef struct DFLL_struct -{ - register8_t CTRL; /* Control Register */ - register8_t reserved_0x01; - register8_t CALA; /* Calibration Register A */ - register8_t CALB; /* Calibration Register B */ - register8_t COMP0; /* Oscillator Compare Register 0 */ - register8_t COMP1; /* Oscillator Compare Register 1 */ - register8_t COMP2; /* Oscillator Compare Register 2 */ - register8_t reserved_0x07; -} DFLL_t; - - -/* --------------------------------------------------------------------------- -RST - Reset --------------------------------------------------------------------------- -*/ - -/* Reset */ -typedef struct RST_struct -{ - register8_t STATUS; /* Status Register */ - register8_t CTRL; /* Control Register */ -} RST_t; - - -/* --------------------------------------------------------------------------- -WDT - Watch-Dog Timer --------------------------------------------------------------------------- -*/ - -/* Watch-Dog Timer */ -typedef struct WDT_struct -{ - register8_t CTRL; /* Control */ - register8_t WINCTRL; /* Windowed Mode Control */ - register8_t STATUS; /* Status */ -} WDT_t; - -/* Period setting */ -typedef enum WDT_PER_enum -{ - WDT_PER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ - WDT_PER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ - WDT_PER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ - WDT_PER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ - WDT_PER_128CLK_gc = (0x04<<2), /* 128 cycles (0.128s @ 3.3V) */ - WDT_PER_256CLK_gc = (0x05<<2), /* 256 cycles (0.256s @ 3.3V) */ - WDT_PER_512CLK_gc = (0x06<<2), /* 512 cycles (0.512s @ 3.3V) */ - WDT_PER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ - WDT_PER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ - WDT_PER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ - WDT_PER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ -} WDT_PER_t; - -/* Closed window period */ -typedef enum WDT_WPER_enum -{ - WDT_WPER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ - WDT_WPER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ - WDT_WPER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ - WDT_WPER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ - WDT_WPER_128CLK_gc = (0x04<<2), /* 128 cycles (0.128s @ 3.3V) */ - WDT_WPER_256CLK_gc = (0x05<<2), /* 256 cycles (0.256s @ 3.3V) */ - WDT_WPER_512CLK_gc = (0x06<<2), /* 512 cycles (0.512s @ 3.3V) */ - WDT_WPER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ - WDT_WPER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ - WDT_WPER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ - WDT_WPER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ -} WDT_WPER_t; - - -/* --------------------------------------------------------------------------- -MCU - MCU Control --------------------------------------------------------------------------- -*/ - -/* MCU Control */ -typedef struct MCU_struct -{ - register8_t DEVID0; /* Device ID byte 0 */ - register8_t DEVID1; /* Device ID byte 1 */ - register8_t DEVID2; /* Device ID byte 2 */ - register8_t REVID; /* Revision ID */ - register8_t JTAGUID; /* JTAG User ID */ - register8_t reserved_0x05; - register8_t MCUCR; /* MCU Control */ - register8_t ANAINIT; /* Analog Startup Delay */ - register8_t EVSYSLOCK; /* Event System Lock */ - register8_t AWEXLOCK; /* AWEX Lock */ - register8_t reserved_0x0A; - register8_t reserved_0x0B; -} MCU_t; - - -/* --------------------------------------------------------------------------- -PMIC - Programmable Multi-level Interrupt Controller --------------------------------------------------------------------------- -*/ - -/* Programmable Multi-level Interrupt Controller */ -typedef struct PMIC_struct -{ - register8_t STATUS; /* Status Register */ - register8_t INTPRI; /* Interrupt Priority */ - register8_t CTRL; /* Control Register */ - register8_t reserved_0x03; - register8_t reserved_0x04; - register8_t reserved_0x05; - register8_t reserved_0x06; - register8_t reserved_0x07; - register8_t reserved_0x08; - register8_t reserved_0x09; - register8_t reserved_0x0A; - register8_t reserved_0x0B; - register8_t reserved_0x0C; - register8_t reserved_0x0D; - register8_t reserved_0x0E; - register8_t reserved_0x0F; -} PMIC_t; - - -/* --------------------------------------------------------------------------- -PORTCFG - Port Configuration --------------------------------------------------------------------------- -*/ - -/* I/O port Configuration */ -typedef struct PORTCFG_struct -{ - register8_t MPCMASK; /* Multi-pin Configuration Mask */ - register8_t reserved_0x01; - register8_t VPCTRLA; /* Virtual Port Control Register A */ - register8_t VPCTRLB; /* Virtual Port Control Register B */ - register8_t CLKEVOUT; /* Clock and Event Out Register */ - register8_t EBIOUT; /* EBI Output register */ - register8_t EVOUTSEL; /* Event Output Select */ -} PORTCFG_t; - -/* Virtual Port Mapping */ -typedef enum PORTCFG_VP02MAP_enum -{ - PORTCFG_VP02MAP_PORTA_gc = (0x00<<0), /* Mapped To PORTA */ - PORTCFG_VP02MAP_PORTB_gc = (0x01<<0), /* Mapped To PORTB */ - PORTCFG_VP02MAP_PORTC_gc = (0x02<<0), /* Mapped To PORTC */ - PORTCFG_VP02MAP_PORTD_gc = (0x03<<0), /* Mapped To PORTD */ - PORTCFG_VP02MAP_PORTE_gc = (0x04<<0), /* Mapped To PORTE */ - PORTCFG_VP02MAP_PORTF_gc = (0x05<<0), /* Mapped To PORTF */ - PORTCFG_VP02MAP_PORTG_gc = (0x06<<0), /* Mapped To PORTG */ - PORTCFG_VP02MAP_PORTH_gc = (0x07<<0), /* Mapped To PORTH */ - PORTCFG_VP02MAP_PORTJ_gc = (0x08<<0), /* Mapped To PORTJ */ - PORTCFG_VP02MAP_PORTK_gc = (0x09<<0), /* Mapped To PORTK */ - PORTCFG_VP02MAP_PORTL_gc = (0x0A<<0), /* Mapped To PORTL */ - PORTCFG_VP02MAP_PORTM_gc = (0x0B<<0), /* Mapped To PORTM */ - PORTCFG_VP02MAP_PORTN_gc = (0x0C<<0), /* Mapped To PORTN */ - PORTCFG_VP02MAP_PORTP_gc = (0x0D<<0), /* Mapped To PORTP */ - PORTCFG_VP02MAP_PORTQ_gc = (0x0E<<0), /* Mapped To PORTQ */ - PORTCFG_VP02MAP_PORTR_gc = (0x0F<<0), /* Mapped To PORTR */ -} PORTCFG_VP02MAP_t; - -/* Virtual Port Mapping */ -typedef enum PORTCFG_VP13MAP_enum -{ - PORTCFG_VP13MAP_PORTA_gc = (0x00<<4), /* Mapped To PORTA */ - PORTCFG_VP13MAP_PORTB_gc = (0x01<<4), /* Mapped To PORTB */ - PORTCFG_VP13MAP_PORTC_gc = (0x02<<4), /* Mapped To PORTC */ - PORTCFG_VP13MAP_PORTD_gc = (0x03<<4), /* Mapped To PORTD */ - PORTCFG_VP13MAP_PORTE_gc = (0x04<<4), /* Mapped To PORTE */ - PORTCFG_VP13MAP_PORTF_gc = (0x05<<4), /* Mapped To PORTF */ - PORTCFG_VP13MAP_PORTG_gc = (0x06<<4), /* Mapped To PORTG */ - PORTCFG_VP13MAP_PORTH_gc = (0x07<<4), /* Mapped To PORTH */ - PORTCFG_VP13MAP_PORTJ_gc = (0x08<<4), /* Mapped To PORTJ */ - PORTCFG_VP13MAP_PORTK_gc = (0x09<<4), /* Mapped To PORTK */ - PORTCFG_VP13MAP_PORTL_gc = (0x0A<<4), /* Mapped To PORTL */ - PORTCFG_VP13MAP_PORTM_gc = (0x0B<<4), /* Mapped To PORTM */ - PORTCFG_VP13MAP_PORTN_gc = (0x0C<<4), /* Mapped To PORTN */ - PORTCFG_VP13MAP_PORTP_gc = (0x0D<<4), /* Mapped To PORTP */ - PORTCFG_VP13MAP_PORTQ_gc = (0x0E<<4), /* Mapped To PORTQ */ - PORTCFG_VP13MAP_PORTR_gc = (0x0F<<4), /* Mapped To PORTR */ -} PORTCFG_VP13MAP_t; - -/* System Clock Output Port */ -typedef enum PORTCFG_CLKOUT_enum -{ - PORTCFG_CLKOUT_OFF_gc = (0x00<<0), /* System Clock Output Disabled */ - PORTCFG_CLKOUT_PC7_gc = (0x01<<0), /* System Clock Output on Port C pin 7 */ - PORTCFG_CLKOUT_PD7_gc = (0x02<<0), /* System Clock Output on Port D pin 7 */ - PORTCFG_CLKOUT_PE7_gc = (0x03<<0), /* System Clock Output on Port E pin 7 */ -} PORTCFG_CLKOUT_t; - -/* Peripheral Clock Output Select */ -typedef enum PORTCFG_CLKOUTSEL_enum -{ - PORTCFG_CLKOUTSEL_CLK1X_gc = (0x00<<2), /* 1x Peripheral Clock Output to pin */ - PORTCFG_CLKOUTSEL_CLK2X_gc = (0x01<<2), /* 2x Peripheral Clock Output to pin */ - PORTCFG_CLKOUTSEL_CLK4X_gc = (0x02<<2), /* 4x Peripheral Clock Output to pin */ -} PORTCFG_CLKOUTSEL_t; - -/* Event Output Port */ -typedef enum PORTCFG_EVOUT_enum -{ - PORTCFG_EVOUT_OFF_gc = (0x00<<4), /* Event Output Disabled */ - PORTCFG_EVOUT_PC7_gc = (0x01<<4), /* Event Channel 7 Output on Port C pin 7 */ - PORTCFG_EVOUT_PD7_gc = (0x02<<4), /* Event Channel 7 Output on Port D pin 7 */ - PORTCFG_EVOUT_PE7_gc = (0x03<<4), /* Event Channel 7 Output on Port E pin 7 */ -} PORTCFG_EVOUT_t; - -/* Clock and Event Output Port */ -typedef enum PORTCFG_CLKEVPIN_enum -{ - PORTCFG_CLKEVPIN_PIN7_gc = (0x00<<7), /* Clock and Event Ouput on PIN 7 */ - PORTCFG_CLKEVPIN_PIN4_gc = (0x01<<7), /* Clock and Event Ouput on PIN 4 */ -} PORTCFG_CLKEVPIN_t; - -/* EBI Address Output Port */ -typedef enum PORTCFG_EBIADROUT_enum -{ - PORTCFG_EBIADROUT_PF_gc = (0x00<<2), /* EBI port 3 address output on PORTF pins 0 to 7 */ - PORTCFG_EBIADROUT_PE_gc = (0x01<<2), /* EBI port 3 address output on PORTE pins 0 to 7 */ - PORTCFG_EBIADROUT_PFH_gc = (0x02<<2), /* EBI port 3 address output on PORTF pins 4 to 7 */ - PORTCFG_EBIADROUT_PEH_gc = (0x03<<2), /* EBI port 3 address output on PORTE pins 4 to 7 */ -} PORTCFG_EBIADROUT_t; - -/* EBI Chip Select Output Port */ -typedef enum PORTCFG_EBICSOUT_enum -{ - PORTCFG_EBICSOUT_PH_gc = (0x00<<0), /* EBI chip select output to PORTH pin 4 to 7 */ - PORTCFG_EBICSOUT_PL_gc = (0x01<<0), /* EBI chip select output to PORTL pin 4 to 7 */ - PORTCFG_EBICSOUT_PF_gc = (0x02<<0), /* EBI chip select output to PORTF pin 4 to 7 */ - PORTCFG_EBICSOUT_PE_gc = (0x03<<0), /* EBI chip select output to PORTE pin 4 to 7 */ -} PORTCFG_EBICSOUT_t; - -/* Event Output Select */ -typedef enum PORTCFG_EVOUTSEL_enum -{ - PORTCFG_EVOUTSEL_0_gc = (0x00<<0), /* Event Channel 0 output to pin */ - PORTCFG_EVOUTSEL_1_gc = (0x01<<0), /* Event Channel 1 output to pin */ - PORTCFG_EVOUTSEL_2_gc = (0x02<<0), /* Event Channel 2 output to pin */ - PORTCFG_EVOUTSEL_3_gc = (0x03<<0), /* Event Channel 3 output to pin */ - PORTCFG_EVOUTSEL_4_gc = (0x04<<0), /* Event Channel 4 output to pin */ - PORTCFG_EVOUTSEL_5_gc = (0x05<<0), /* Event Channel 5 output to pin */ - PORTCFG_EVOUTSEL_6_gc = (0x06<<0), /* Event Channel 6 output to pin */ - PORTCFG_EVOUTSEL_7_gc = (0x07<<0), /* Event Channel 7 output to pin */ -} PORTCFG_EVOUTSEL_t; - - -/* --------------------------------------------------------------------------- -AES - AES Module --------------------------------------------------------------------------- -*/ - -/* AES Module */ -typedef struct AES_struct -{ - register8_t CTRL; /* AES Control Register */ - register8_t STATUS; /* AES Status Register */ - register8_t STATE; /* AES State Register */ - register8_t KEY; /* AES Key Register */ - register8_t INTCTRL; /* AES Interrupt Control Register */ -} AES_t; - -/* Interrupt level */ -typedef enum AES_INTLVL_enum -{ - AES_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - AES_INTLVL_LO_gc = (0x01<<0), /* Low Level */ - AES_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ - AES_INTLVL_HI_gc = (0x03<<0), /* High Level */ -} AES_INTLVL_t; - - -/* --------------------------------------------------------------------------- -CRC - Cyclic Redundancy Checker --------------------------------------------------------------------------- -*/ - -/* Cyclic Redundancy Checker */ -typedef struct CRC_struct -{ - register8_t CTRL; /* Control Register */ - register8_t STATUS; /* Status Register */ - register8_t reserved_0x02; - register8_t DATAIN; /* Data Input */ - register8_t CHECKSUM0; /* Checksum byte 0 */ - register8_t CHECKSUM1; /* Checksum byte 1 */ - register8_t CHECKSUM2; /* Checksum byte 2 */ - register8_t CHECKSUM3; /* Checksum byte 3 */ -} CRC_t; - -/* Reset */ -typedef enum CRC_RESET_enum -{ - CRC_RESET_NO_gc = (0x00<<6), /* No Reset */ - CRC_RESET_RESET0_gc = (0x02<<6), /* Reset CRC with CHECKSUM to all zeros */ - CRC_RESET_RESET1_gc = (0x03<<6), /* Reset CRC with CHECKSUM to all ones */ -} CRC_RESET_t; - -/* Input Source */ -typedef enum CRC_SOURCE_enum -{ - CRC_SOURCE_DISABLE_gc = (0x00<<0), /* Disabled */ - CRC_SOURCE_IO_gc = (0x01<<0), /* I/O Interface */ - CRC_SOURCE_FLASH_gc = (0x02<<0), /* Flash */ - CRC_SOURCE_DMAC0_gc = (0x04<<0), /* DMAC Channel 0 */ - CRC_SOURCE_DMAC1_gc = (0x05<<0), /* DMAC Channel 1 */ - CRC_SOURCE_DMAC2_gc = (0x06<<0), /* DMAC Channel 2 */ - CRC_SOURCE_DMAC3_gc = (0x07<<0), /* DMAC Channel 3 */ -} CRC_SOURCE_t; - - -/* --------------------------------------------------------------------------- -DMA - DMA Controller --------------------------------------------------------------------------- -*/ - -/* DMA Channel */ -typedef struct DMA_CH_struct -{ - register8_t CTRLA; /* Channel Control */ - register8_t CTRLB; /* Channel Control */ - register8_t ADDRCTRL; /* Address Control */ - register8_t TRIGSRC; /* Channel Trigger Source */ - _WORDREGISTER(TRFCNT); /* Channel Block Transfer Count */ - register8_t REPCNT; /* Channel Repeat Count */ - register8_t reserved_0x07; - register8_t SRCADDR0; /* Channel Source Address 0 */ - register8_t SRCADDR1; /* Channel Source Address 1 */ - register8_t SRCADDR2; /* Channel Source Address 2 */ - register8_t reserved_0x0B; - register8_t DESTADDR0; /* Channel Destination Address 0 */ - register8_t DESTADDR1; /* Channel Destination Address 1 */ - register8_t DESTADDR2; /* Channel Destination Address 2 */ - register8_t reserved_0x0F; -} DMA_CH_t; - - -/* DMA Controller */ -typedef struct DMA_struct -{ - register8_t CTRL; /* Control */ - register8_t reserved_0x01; - register8_t reserved_0x02; - register8_t INTFLAGS; /* Transfer Interrupt Status */ - register8_t STATUS; /* Status */ - register8_t reserved_0x05; - _WORDREGISTER(TEMP); /* Temporary Register For 16/24-bit Access */ - register8_t reserved_0x08; - register8_t reserved_0x09; - register8_t reserved_0x0A; - register8_t reserved_0x0B; - register8_t reserved_0x0C; - register8_t reserved_0x0D; - register8_t reserved_0x0E; - register8_t reserved_0x0F; - DMA_CH_t CH0; /* DMA Channel 0 */ - DMA_CH_t CH1; /* DMA Channel 1 */ - DMA_CH_t CH2; /* DMA Channel 2 */ - DMA_CH_t CH3; /* DMA Channel 3 */ -} DMA_t; - -/* Burst mode */ -typedef enum DMA_CH_BURSTLEN_enum -{ - DMA_CH_BURSTLEN_1BYTE_gc = (0x00<<0), /* 1-byte burst mode */ - DMA_CH_BURSTLEN_2BYTE_gc = (0x01<<0), /* 2-byte burst mode */ - DMA_CH_BURSTLEN_4BYTE_gc = (0x02<<0), /* 4-byte burst mode */ - DMA_CH_BURSTLEN_8BYTE_gc = (0x03<<0), /* 8-byte burst mode */ -} DMA_CH_BURSTLEN_t; - -/* Source address reload mode */ -typedef enum DMA_CH_SRCRELOAD_enum -{ - DMA_CH_SRCRELOAD_NONE_gc = (0x00<<6), /* No reload */ - DMA_CH_SRCRELOAD_BLOCK_gc = (0x01<<6), /* Reload at end of block */ - DMA_CH_SRCRELOAD_BURST_gc = (0x02<<6), /* Reload at end of burst */ - DMA_CH_SRCRELOAD_TRANSACTION_gc = (0x03<<6), /* Reload at end of transaction */ -} DMA_CH_SRCRELOAD_t; - -/* Source addressing mode */ -typedef enum DMA_CH_SRCDIR_enum -{ - DMA_CH_SRCDIR_FIXED_gc = (0x00<<4), /* Fixed */ - DMA_CH_SRCDIR_INC_gc = (0x01<<4), /* Increment */ - DMA_CH_SRCDIR_DEC_gc = (0x02<<4), /* Decrement */ -} DMA_CH_SRCDIR_t; - -/* Destination adress reload mode */ -typedef enum DMA_CH_DESTRELOAD_enum -{ - DMA_CH_DESTRELOAD_NONE_gc = (0x00<<2), /* No reload */ - DMA_CH_DESTRELOAD_BLOCK_gc = (0x01<<2), /* Reload at end of block */ - DMA_CH_DESTRELOAD_BURST_gc = (0x02<<2), /* Reload at end of burst */ - DMA_CH_DESTRELOAD_TRANSACTION_gc = (0x03<<2), /* Reload at end of transaction */ -} DMA_CH_DESTRELOAD_t; - -/* Destination adressing mode */ -typedef enum DMA_CH_DESTDIR_enum -{ - DMA_CH_DESTDIR_FIXED_gc = (0x00<<0), /* Fixed */ - DMA_CH_DESTDIR_INC_gc = (0x01<<0), /* Increment */ - DMA_CH_DESTDIR_DEC_gc = (0x02<<0), /* Decrement */ -} DMA_CH_DESTDIR_t; - -/* Transfer trigger source */ -typedef enum DMA_CH_TRIGSRC_enum -{ - DMA_CH_TRIGSRC_OFF_gc = (0x00<<0), /* Off software triggers only */ - DMA_CH_TRIGSRC_EVSYS_CH0_gc = (0x01<<0), /* Event System Channel 0 */ - DMA_CH_TRIGSRC_EVSYS_CH1_gc = (0x02<<0), /* Event System Channel 1 */ - DMA_CH_TRIGSRC_EVSYS_CH2_gc = (0x03<<0), /* Event System Channel 2 */ - DMA_CH_TRIGSRC_ADCA_CH0_gc = (0x10<<0), /* ADCA Channel 0 */ - DMA_CH_TRIGSRC_ADCA_CH1_gc = (0x11<<0), /* ADCA Channel 1 */ - DMA_CH_TRIGSRC_ADCA_CH2_gc = (0x12<<0), /* ADCA Channel 2 */ - DMA_CH_TRIGSRC_ADCA_CH3_gc = (0x13<<0), /* ADCA Channel 3 */ - DMA_CH_TRIGSRC_ADCA_CH4_gc = (0x14<<0), /* ADCA Channel 0,1,2,3 combined */ - DMA_CH_TRIGSRC_DACA_CH0_gc = (0x15<<0), /* DACA Channel 0 */ - DMA_CH_TRIGSRC_DACA_CH1_gc = (0x16<<0), /* DACA Channel 1 */ - DMA_CH_TRIGSRC_ADCB_CH0_gc = (0x20<<0), /* ADCB Channel 0 */ - DMA_CH_TRIGSRC_ADCB_CH1_gc = (0x21<<0), /* ADCB Channel 1 */ - DMA_CH_TRIGSRC_ADCB_CH2_gc = (0x22<<0), /* ADCB Channel 2 */ - DMA_CH_TRIGSRC_ADCB_CH3_gc = (0x23<<0), /* ADCB Channel 3 */ - DMA_CH_TRIGSRC_ADCB_CH4_gc = (0x24<<0), /* ADCB Channel 0,1,2,3 combined */ - DMA_CH_TRIGSRC_DACB_CH0_gc = (0x25<<0), /* DACB Channel 0 */ - DMA_CH_TRIGSRC_DACB_CH1_gc = (0x26<<0), /* DACB Channel 1 */ - DMA_CH_TRIGSRC_TCC0_OVF_gc = (0x40<<0), /* Timer/Counter C0 Overflow */ - DMA_CH_TRIGSRC_TCC0_ERR_gc = (0x41<<0), /* Timer/Counter C0 Error */ - DMA_CH_TRIGSRC_TCC0_CCA_gc = (0x42<<0), /* Timer/Counter C0 Compare or Capture A */ - DMA_CH_TRIGSRC_TCC0_CCB_gc = (0x43<<0), /* Timer/Counter C0 Compare or Capture B */ - DMA_CH_TRIGSRC_TCC0_CCC_gc = (0x44<<0), /* Timer/Counter C0 Compare or Capture C */ - DMA_CH_TRIGSRC_TCC0_CCD_gc = (0x45<<0), /* Timer/Counter C0 Compare or Capture D */ - DMA_CH_TRIGSRC_TCC1_OVF_gc = (0x46<<0), /* Timer/Counter C1 Overflow */ - DMA_CH_TRIGSRC_TCC1_ERR_gc = (0x47<<0), /* Timer/Counter C1 Error */ - DMA_CH_TRIGSRC_TCC1_CCA_gc = (0x48<<0), /* Timer/Counter C1 Compare or Capture A */ - DMA_CH_TRIGSRC_TCC1_CCB_gc = (0x49<<0), /* Timer/Counter C1 Compare or Capture B */ - DMA_CH_TRIGSRC_SPIC_gc = (0x4A<<0), /* SPI C Transfer Complete */ - DMA_CH_TRIGSRC_USARTC0_RXC_gc = (0x4B<<0), /* USART C0 Receive Complete */ - DMA_CH_TRIGSRC_USARTC0_DRE_gc = (0x4C<<0), /* USART C0 Data Register Empty */ - DMA_CH_TRIGSRC_USARTC1_RXC_gc = (0x4E<<0), /* USART C1 Receive Complete */ - DMA_CH_TRIGSRC_USARTC1_DRE_gc = (0x4F<<0), /* USART C1 Data Register Empty */ - DMA_CH_TRIGSRC_TCD0_OVF_gc = (0x60<<0), /* Timer/Counter D0 Overflow */ - DMA_CH_TRIGSRC_TCD0_ERR_gc = (0x61<<0), /* Timer/Counter D0 Error */ - DMA_CH_TRIGSRC_TCD0_CCA_gc = (0x62<<0), /* Timer/Counter D0 Compare or Capture A */ - DMA_CH_TRIGSRC_TCD0_CCB_gc = (0x63<<0), /* Timer/Counter D0 Compare or Capture B */ - DMA_CH_TRIGSRC_TCD0_CCC_gc = (0x64<<0), /* Timer/Counter D0 Compare or Capture C */ - DMA_CH_TRIGSRC_TCD0_CCD_gc = (0x65<<0), /* Timer/Counter D0 Compare or Capture D */ - DMA_CH_TRIGSRC_TCD1_OVF_gc = (0x66<<0), /* Timer/Counter D1 Overflow */ - DMA_CH_TRIGSRC_TCD1_ERR_gc = (0x67<<0), /* Timer/Counter D1 Error */ - DMA_CH_TRIGSRC_TCD1_CCA_gc = (0x68<<0), /* Timer/Counter D1 Compare or Capture A */ - DMA_CH_TRIGSRC_TCD1_CCB_gc = (0x69<<0), /* Timer/Counter D1 Compare or Capture B */ - DMA_CH_TRIGSRC_SPID_gc = (0x6A<<0), /* SPI D Transfer Complete */ - DMA_CH_TRIGSRC_USARTD0_RXC_gc = (0x6B<<0), /* USART D0 Receive Complete */ - DMA_CH_TRIGSRC_USARTD0_DRE_gc = (0x6C<<0), /* USART D0 Data Register Empty */ - DMA_CH_TRIGSRC_USARTD1_RXC_gc = (0x6E<<0), /* USART D1 Receive Complete */ - DMA_CH_TRIGSRC_USARTD1_DRE_gc = (0x6F<<0), /* USART D1 Data Register Empty */ - DMA_CH_TRIGSRC_TCE0_OVF_gc = (0x80<<0), /* Timer/Counter E0 Overflow */ - DMA_CH_TRIGSRC_TCE0_ERR_gc = (0x81<<0), /* Timer/Counter E0 Error */ - DMA_CH_TRIGSRC_TCE0_CCA_gc = (0x82<<0), /* Timer/Counter E0 Compare or Capture A */ - DMA_CH_TRIGSRC_TCE0_CCB_gc = (0x83<<0), /* Timer/Counter E0 Compare or Capture B */ - DMA_CH_TRIGSRC_TCE0_CCC_gc = (0x84<<0), /* Timer/Counter E0 Compare or Capture C */ - DMA_CH_TRIGSRC_TCE0_CCD_gc = (0x85<<0), /* Timer/Counter E0 Compare or Capture D */ - DMA_CH_TRIGSRC_TCE1_OVF_gc = (0x86<<0), /* Timer/Counter E1 Overflow */ - DMA_CH_TRIGSRC_TCE1_ERR_gc = (0x87<<0), /* Timer/Counter E1 Error */ - DMA_CH_TRIGSRC_TCE1_CCA_gc = (0x88<<0), /* Timer/Counter E1 Compare or Capture A */ - DMA_CH_TRIGSRC_TCE1_CCB_gc = (0x89<<0), /* Timer/Counter E1 Compare or Capture B */ - DMA_CH_TRIGSRC_SPIE_gc = (0x8A<<0), /* SPI E Transfer Complete */ - DMA_CH_TRIGSRC_USARTE0_RXC_gc = (0x8B<<0), /* USART E0 Receive Complete */ - DMA_CH_TRIGSRC_USARTE0_DRE_gc = (0x8C<<0), /* USART E0 Data Register Empty */ - DMA_CH_TRIGSRC_USARTE1_RXC_gc = (0x8E<<0), /* USART E1 Receive Complete */ - DMA_CH_TRIGSRC_USARTE1_DRE_gc = (0x8F<<0), /* USART E1 Data Register Empty */ - DMA_CH_TRIGSRC_TCF0_OVF_gc = (0xA0<<0), /* Timer/Counter F0 Overflow */ - DMA_CH_TRIGSRC_TCF0_ERR_gc = (0xA1<<0), /* Timer/Counter F0 Error */ - DMA_CH_TRIGSRC_TCF0_CCA_gc = (0xA2<<0), /* Timer/Counter F0 Compare or Capture A */ - DMA_CH_TRIGSRC_TCF0_CCB_gc = (0xA3<<0), /* Timer/Counter F0 Compare or Capture B */ - DMA_CH_TRIGSRC_TCF0_CCC_gc = (0xA4<<0), /* Timer/Counter F0 Compare or Capture C */ - DMA_CH_TRIGSRC_TCF0_CCD_gc = (0xA5<<0), /* Timer/Counter F0 Compare or Capture D */ - DMA_CH_TRIGSRC_TCF1_OVF_gc = (0xA6<<0), /* Timer/Counter F1 Overflow */ - DMA_CH_TRIGSRC_TCF1_ERR_gc = (0xA7<<0), /* Timer/Counter F1 Error */ - DMA_CH_TRIGSRC_TCF1_CCA_gc = (0xA8<<0), /* Timer/Counter F1 Compare or Capture A */ - DMA_CH_TRIGSRC_TCF1_CCB_gc = (0xA9<<0), /* Timer/Counter F1 Compare or Capture B */ - DMA_CH_TRIGSRC_SPIF_gc = (0xAA<<0), /* SPI F Transfer Complete */ - DMA_CH_TRIGSRC_USARTF0_RXC_gc = (0xAB<<0), /* USART F0 Receive Complete */ - DMA_CH_TRIGSRC_USARTF0_DRE_gc = (0xAC<<0), /* USART F0 Data Register Empty */ - DMA_CH_TRIGSRC_USARTF1_RXC_gc = (0xAE<<0), /* USART F1 Receive Complete */ - DMA_CH_TRIGSRC_USARTF1_DRE_gc = (0xAF<<0), /* USART F1 Data Register Empty */ -} DMA_CH_TRIGSRC_t; - -/* Double buffering mode */ -typedef enum DMA_DBUFMODE_enum -{ - DMA_DBUFMODE_DISABLED_gc = (0x00<<2), /* Double buffering disabled */ - DMA_DBUFMODE_CH01_gc = (0x01<<2), /* Double buffering enabled on channel 0/1 */ - DMA_DBUFMODE_CH23_gc = (0x02<<2), /* Double buffering enabled on channel 2/3 */ - DMA_DBUFMODE_CH01CH23_gc = (0x03<<2), /* Double buffering enabled on ch. 0/1 and ch. 2/3 */ -} DMA_DBUFMODE_t; - -/* Priority mode */ -typedef enum DMA_PRIMODE_enum -{ - DMA_PRIMODE_RR0123_gc = (0x00<<0), /* Round Robin */ - DMA_PRIMODE_CH0RR123_gc = (0x01<<0), /* Channel 0 > Round Robin on channel 1/2/3 */ - DMA_PRIMODE_CH01RR23_gc = (0x02<<0), /* Channel 0 > channel 1 > Round Robin on channel 2/3 */ - DMA_PRIMODE_CH0123_gc = (0x03<<0), /* Channel 0 > channel 1 > channel 2 > channel 3 */ -} DMA_PRIMODE_t; - -/* Interrupt level */ -typedef enum DMA_CH_ERRINTLVL_enum -{ - DMA_CH_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ - DMA_CH_ERRINTLVL_LO_gc = (0x01<<2), /* Low level */ - DMA_CH_ERRINTLVL_MED_gc = (0x02<<2), /* Medium level */ - DMA_CH_ERRINTLVL_HI_gc = (0x03<<2), /* High level */ -} DMA_CH_ERRINTLVL_t; - -/* Interrupt level */ -typedef enum DMA_CH_TRNINTLVL_enum -{ - DMA_CH_TRNINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ - DMA_CH_TRNINTLVL_LO_gc = (0x01<<0), /* Low level */ - DMA_CH_TRNINTLVL_MED_gc = (0x02<<0), /* Medium level */ - DMA_CH_TRNINTLVL_HI_gc = (0x03<<0), /* High level */ -} DMA_CH_TRNINTLVL_t; - - -/* --------------------------------------------------------------------------- -EVSYS - Event System --------------------------------------------------------------------------- -*/ - -/* Event System */ -typedef struct EVSYS_struct -{ - register8_t CH0MUX; /* Event Channel 0 Multiplexer */ - register8_t CH1MUX; /* Event Channel 1 Multiplexer */ - register8_t CH2MUX; /* Event Channel 2 Multiplexer */ - register8_t CH3MUX; /* Event Channel 3 Multiplexer */ - register8_t CH4MUX; /* Event Channel 4 Multiplexer */ - register8_t CH5MUX; /* Event Channel 5 Multiplexer */ - register8_t CH6MUX; /* Event Channel 6 Multiplexer */ - register8_t CH7MUX; /* Event Channel 7 Multiplexer */ - register8_t CH0CTRL; /* Channel 0 Control Register */ - register8_t CH1CTRL; /* Channel 1 Control Register */ - register8_t CH2CTRL; /* Channel 2 Control Register */ - register8_t CH3CTRL; /* Channel 3 Control Register */ - register8_t CH4CTRL; /* Channel 4 Control Register */ - register8_t CH5CTRL; /* Channel 5 Control Register */ - register8_t CH6CTRL; /* Channel 6 Control Register */ - register8_t CH7CTRL; /* Channel 7 Control Register */ - register8_t STROBE; /* Event Strobe */ - register8_t DATA; /* Event Data */ -} EVSYS_t; - -/* Quadrature Decoder Index Recognition Mode */ -typedef enum EVSYS_QDIRM_enum -{ - EVSYS_QDIRM_00_gc = (0x00<<5), /* QDPH0 = 0, QDPH90 = 0 */ - EVSYS_QDIRM_01_gc = (0x01<<5), /* QDPH0 = 0, QDPH90 = 1 */ - EVSYS_QDIRM_10_gc = (0x02<<5), /* QDPH0 = 1, QDPH90 = 0 */ - EVSYS_QDIRM_11_gc = (0x03<<5), /* QDPH0 = 1, QDPH90 = 1 */ -} EVSYS_QDIRM_t; - -/* Digital filter coefficient */ -typedef enum EVSYS_DIGFILT_enum -{ - EVSYS_DIGFILT_1SAMPLE_gc = (0x00<<0), /* 1 SAMPLE */ - EVSYS_DIGFILT_2SAMPLES_gc = (0x01<<0), /* 2 SAMPLES */ - EVSYS_DIGFILT_3SAMPLES_gc = (0x02<<0), /* 3 SAMPLES */ - EVSYS_DIGFILT_4SAMPLES_gc = (0x03<<0), /* 4 SAMPLES */ - EVSYS_DIGFILT_5SAMPLES_gc = (0x04<<0), /* 5 SAMPLES */ - EVSYS_DIGFILT_6SAMPLES_gc = (0x05<<0), /* 6 SAMPLES */ - EVSYS_DIGFILT_7SAMPLES_gc = (0x06<<0), /* 7 SAMPLES */ - EVSYS_DIGFILT_8SAMPLES_gc = (0x07<<0), /* 8 SAMPLES */ -} EVSYS_DIGFILT_t; - -/* Event Channel multiplexer input selection */ -typedef enum EVSYS_CHMUX_enum -{ - EVSYS_CHMUX_OFF_gc = (0x00<<0), /* Off */ - EVSYS_CHMUX_RTC_OVF_gc = (0x08<<0), /* RTC Overflow */ - EVSYS_CHMUX_RTC_CMP_gc = (0x09<<0), /* RTC Compare Match */ - EVSYS_CHMUX_USB_gc = (0x0A<<0), /* USB Setup, SOF, CRC error and UNF/OVF */ - EVSYS_CHMUX_ACA_CH0_gc = (0x10<<0), /* Analog Comparator A Channel 0 */ - EVSYS_CHMUX_ACA_CH1_gc = (0x11<<0), /* Analog Comparator A Channel 1 */ - EVSYS_CHMUX_ACA_WIN_gc = (0x12<<0), /* Analog Comparator A Window */ - EVSYS_CHMUX_ACB_CH0_gc = (0x13<<0), /* Analog Comparator B Channel 0 */ - EVSYS_CHMUX_ACB_CH1_gc = (0x14<<0), /* Analog Comparator B Channel 1 */ - EVSYS_CHMUX_ACB_WIN_gc = (0x15<<0), /* Analog Comparator B Window */ - EVSYS_CHMUX_ADCA_CH0_gc = (0x20<<0), /* ADC A Channel 0 */ - EVSYS_CHMUX_ADCA_CH1_gc = (0x21<<0), /* ADC A Channel 1 */ - EVSYS_CHMUX_ADCA_CH2_gc = (0x22<<0), /* ADC A Channel 2 */ - EVSYS_CHMUX_ADCA_CH3_gc = (0x23<<0), /* ADC A Channel 3 */ - EVSYS_CHMUX_ADCB_CH0_gc = (0x24<<0), /* ADC B Channel 0 */ - EVSYS_CHMUX_ADCB_CH1_gc = (0x25<<0), /* ADC B Channel 1 */ - EVSYS_CHMUX_ADCB_CH2_gc = (0x26<<0), /* ADC B Channel 2 */ - EVSYS_CHMUX_ADCB_CH3_gc = (0x27<<0), /* ADC B Channel 3 */ - EVSYS_CHMUX_PORTA_PIN0_gc = (0x50<<0), /* Port A, Pin0 */ - EVSYS_CHMUX_PORTA_PIN1_gc = (0x51<<0), /* Port A, Pin1 */ - EVSYS_CHMUX_PORTA_PIN2_gc = (0x52<<0), /* Port A, Pin2 */ - EVSYS_CHMUX_PORTA_PIN3_gc = (0x53<<0), /* Port A, Pin3 */ - EVSYS_CHMUX_PORTA_PIN4_gc = (0x54<<0), /* Port A, Pin4 */ - EVSYS_CHMUX_PORTA_PIN5_gc = (0x55<<0), /* Port A, Pin5 */ - EVSYS_CHMUX_PORTA_PIN6_gc = (0x56<<0), /* Port A, Pin6 */ - EVSYS_CHMUX_PORTA_PIN7_gc = (0x57<<0), /* Port A, Pin7 */ - EVSYS_CHMUX_PORTB_PIN0_gc = (0x58<<0), /* Port B, Pin0 */ - EVSYS_CHMUX_PORTB_PIN1_gc = (0x59<<0), /* Port B, Pin1 */ - EVSYS_CHMUX_PORTB_PIN2_gc = (0x5A<<0), /* Port B, Pin2 */ - EVSYS_CHMUX_PORTB_PIN3_gc = (0x5B<<0), /* Port B, Pin3 */ - EVSYS_CHMUX_PORTB_PIN4_gc = (0x5C<<0), /* Port B, Pin4 */ - EVSYS_CHMUX_PORTB_PIN5_gc = (0x5D<<0), /* Port B, Pin5 */ - EVSYS_CHMUX_PORTB_PIN6_gc = (0x5E<<0), /* Port B, Pin6 */ - EVSYS_CHMUX_PORTB_PIN7_gc = (0x5F<<0), /* Port B, Pin7 */ - EVSYS_CHMUX_PORTC_PIN0_gc = (0x60<<0), /* Port C, Pin0 */ - EVSYS_CHMUX_PORTC_PIN1_gc = (0x61<<0), /* Port C, Pin1 */ - EVSYS_CHMUX_PORTC_PIN2_gc = (0x62<<0), /* Port C, Pin2 */ - EVSYS_CHMUX_PORTC_PIN3_gc = (0x63<<0), /* Port C, Pin3 */ - EVSYS_CHMUX_PORTC_PIN4_gc = (0x64<<0), /* Port C, Pin4 */ - EVSYS_CHMUX_PORTC_PIN5_gc = (0x65<<0), /* Port C, Pin5 */ - EVSYS_CHMUX_PORTC_PIN6_gc = (0x66<<0), /* Port C, Pin6 */ - EVSYS_CHMUX_PORTC_PIN7_gc = (0x67<<0), /* Port C, Pin7 */ - EVSYS_CHMUX_PORTD_PIN0_gc = (0x68<<0), /* Port D, Pin0 */ - EVSYS_CHMUX_PORTD_PIN1_gc = (0x69<<0), /* Port D, Pin1 */ - EVSYS_CHMUX_PORTD_PIN2_gc = (0x6A<<0), /* Port D, Pin2 */ - EVSYS_CHMUX_PORTD_PIN3_gc = (0x6B<<0), /* Port D, Pin3 */ - EVSYS_CHMUX_PORTD_PIN4_gc = (0x6C<<0), /* Port D, Pin4 */ - EVSYS_CHMUX_PORTD_PIN5_gc = (0x6D<<0), /* Port D, Pin5 */ - EVSYS_CHMUX_PORTD_PIN6_gc = (0x6E<<0), /* Port D, Pin6 */ - EVSYS_CHMUX_PORTD_PIN7_gc = (0x6F<<0), /* Port D, Pin7 */ - EVSYS_CHMUX_PORTE_PIN0_gc = (0x70<<0), /* Port E, Pin0 */ - EVSYS_CHMUX_PORTE_PIN1_gc = (0x71<<0), /* Port E, Pin1 */ - EVSYS_CHMUX_PORTE_PIN2_gc = (0x72<<0), /* Port E, Pin2 */ - EVSYS_CHMUX_PORTE_PIN3_gc = (0x73<<0), /* Port E, Pin3 */ - EVSYS_CHMUX_PORTE_PIN4_gc = (0x74<<0), /* Port E, Pin4 */ - EVSYS_CHMUX_PORTE_PIN5_gc = (0x75<<0), /* Port E, Pin5 */ - EVSYS_CHMUX_PORTE_PIN6_gc = (0x76<<0), /* Port E, Pin6 */ - EVSYS_CHMUX_PORTE_PIN7_gc = (0x77<<0), /* Port E, Pin7 */ - EVSYS_CHMUX_PORTF_PIN0_gc = (0x78<<0), /* Port F, Pin0 */ - EVSYS_CHMUX_PORTF_PIN1_gc = (0x79<<0), /* Port F, Pin1 */ - EVSYS_CHMUX_PORTF_PIN2_gc = (0x7A<<0), /* Port F, Pin2 */ - EVSYS_CHMUX_PORTF_PIN3_gc = (0x7B<<0), /* Port F, Pin3 */ - EVSYS_CHMUX_PORTF_PIN4_gc = (0x7C<<0), /* Port F, Pin4 */ - EVSYS_CHMUX_PORTF_PIN5_gc = (0x7D<<0), /* Port F, Pin5 */ - EVSYS_CHMUX_PORTF_PIN6_gc = (0x7E<<0), /* Port F, Pin6 */ - EVSYS_CHMUX_PORTF_PIN7_gc = (0x7F<<0), /* Port F, Pin7 */ - EVSYS_CHMUX_PRESCALER_1_gc = (0x80<<0), /* Prescaler, divide by 1 */ - EVSYS_CHMUX_PRESCALER_2_gc = (0x81<<0), /* Prescaler, divide by 2 */ - EVSYS_CHMUX_PRESCALER_4_gc = (0x82<<0), /* Prescaler, divide by 4 */ - EVSYS_CHMUX_PRESCALER_8_gc = (0x83<<0), /* Prescaler, divide by 8 */ - EVSYS_CHMUX_PRESCALER_16_gc = (0x84<<0), /* Prescaler, divide by 16 */ - EVSYS_CHMUX_PRESCALER_32_gc = (0x85<<0), /* Prescaler, divide by 32 */ - EVSYS_CHMUX_PRESCALER_64_gc = (0x86<<0), /* Prescaler, divide by 64 */ - EVSYS_CHMUX_PRESCALER_128_gc = (0x87<<0), /* Prescaler, divide by 128 */ - EVSYS_CHMUX_PRESCALER_256_gc = (0x88<<0), /* Prescaler, divide by 256 */ - EVSYS_CHMUX_PRESCALER_512_gc = (0x89<<0), /* Prescaler, divide by 512 */ - EVSYS_CHMUX_PRESCALER_1024_gc = (0x8A<<0), /* Prescaler, divide by 1024 */ - EVSYS_CHMUX_PRESCALER_2048_gc = (0x8B<<0), /* Prescaler, divide by 2048 */ - EVSYS_CHMUX_PRESCALER_4096_gc = (0x8C<<0), /* Prescaler, divide by 4096 */ - EVSYS_CHMUX_PRESCALER_8192_gc = (0x8D<<0), /* Prescaler, divide by 8192 */ - EVSYS_CHMUX_PRESCALER_16384_gc = (0x8E<<0), /* Prescaler, divide by 16384 */ - EVSYS_CHMUX_PRESCALER_32768_gc = (0x8F<<0), /* Prescaler, divide by 32768 */ - EVSYS_CHMUX_TCC0_OVF_gc = (0xC0<<0), /* Timer/Counter C0 Overflow */ - EVSYS_CHMUX_TCC0_ERR_gc = (0xC1<<0), /* Timer/Counter C0 Error */ - EVSYS_CHMUX_TCC0_CCA_gc = (0xC4<<0), /* Timer/Counter C0 Compare or Capture A */ - EVSYS_CHMUX_TCC0_CCB_gc = (0xC5<<0), /* Timer/Counter C0 Compare or Capture B */ - EVSYS_CHMUX_TCC0_CCC_gc = (0xC6<<0), /* Timer/Counter C0 Compare or Capture C */ - EVSYS_CHMUX_TCC0_CCD_gc = (0xC7<<0), /* Timer/Counter C0 Compare or Capture D */ - EVSYS_CHMUX_TCC1_OVF_gc = (0xC8<<0), /* Timer/Counter C1 Overflow */ - EVSYS_CHMUX_TCC1_ERR_gc = (0xC9<<0), /* Timer/Counter C1 Error */ - EVSYS_CHMUX_TCC1_CCA_gc = (0xCC<<0), /* Timer/Counter C1 Compare or Capture A */ - EVSYS_CHMUX_TCC1_CCB_gc = (0xCD<<0), /* Timer/Counter C1 Compare or Capture B */ - EVSYS_CHMUX_TCD0_OVF_gc = (0xD0<<0), /* Timer/Counter D0 Overflow */ - EVSYS_CHMUX_TCD0_ERR_gc = (0xD1<<0), /* Timer/Counter D0 Error */ - EVSYS_CHMUX_TCD0_CCA_gc = (0xD4<<0), /* Timer/Counter D0 Compare or Capture A */ - EVSYS_CHMUX_TCD0_CCB_gc = (0xD5<<0), /* Timer/Counter D0 Compare or Capture B */ - EVSYS_CHMUX_TCD0_CCC_gc = (0xD6<<0), /* Timer/Counter D0 Compare or Capture C */ - EVSYS_CHMUX_TCD0_CCD_gc = (0xD7<<0), /* Timer/Counter D0 Compare or Capture D */ - EVSYS_CHMUX_TCD1_OVF_gc = (0xD8<<0), /* Timer/Counter D1 Overflow */ - EVSYS_CHMUX_TCD1_ERR_gc = (0xD9<<0), /* Timer/Counter D1 Error */ - EVSYS_CHMUX_TCD1_CCA_gc = (0xDC<<0), /* Timer/Counter D1 Compare or Capture A */ - EVSYS_CHMUX_TCD1_CCB_gc = (0xDD<<0), /* Timer/Counter D1 Compare or Capture B */ - EVSYS_CHMUX_TCE0_OVF_gc = (0xE0<<0), /* Timer/Counter E0 Overflow */ - EVSYS_CHMUX_TCE0_ERR_gc = (0xE1<<0), /* Timer/Counter E0 Error */ - EVSYS_CHMUX_TCE0_CCA_gc = (0xE4<<0), /* Timer/Counter E0 Compare or Capture A */ - EVSYS_CHMUX_TCE0_CCB_gc = (0xE5<<0), /* Timer/Counter E0 Compare or Capture B */ - EVSYS_CHMUX_TCE0_CCC_gc = (0xE6<<0), /* Timer/Counter E0 Compare or Capture C */ - EVSYS_CHMUX_TCE0_CCD_gc = (0xE7<<0), /* Timer/Counter E0 Compare or Capture D */ - EVSYS_CHMUX_TCE1_OVF_gc = (0xE8<<0), /* Timer/Counter E1 Overflow */ - EVSYS_CHMUX_TCE1_ERR_gc = (0xE9<<0), /* Timer/Counter E1 Error */ - EVSYS_CHMUX_TCE1_CCA_gc = (0xEC<<0), /* Timer/Counter E1 Compare or Capture A */ - EVSYS_CHMUX_TCE1_CCB_gc = (0xED<<0), /* Timer/Counter E1 Compare or Capture B */ - EVSYS_CHMUX_TCF0_OVF_gc = (0xF0<<0), /* Timer/Counter F0 Overflow */ - EVSYS_CHMUX_TCF0_ERR_gc = (0xF1<<0), /* Timer/Counter F0 Error */ - EVSYS_CHMUX_TCF0_CCA_gc = (0xF4<<0), /* Timer/Counter F0 Compare or Capture A */ - EVSYS_CHMUX_TCF0_CCB_gc = (0xF5<<0), /* Timer/Counter F0 Compare or Capture B */ - EVSYS_CHMUX_TCF0_CCC_gc = (0xF6<<0), /* Timer/Counter F0 Compare or Capture C */ - EVSYS_CHMUX_TCF0_CCD_gc = (0xF7<<0), /* Timer/Counter F0 Compare or Capture D */ - EVSYS_CHMUX_TCF1_OVF_gc = (0xF8<<0), /* Timer/Counter F1 Overflow */ - EVSYS_CHMUX_TCF1_ERR_gc = (0xF9<<0), /* Timer/Counter F1 Error */ - EVSYS_CHMUX_TCF1_CCA_gc = (0xFC<<0), /* Timer/Counter F1 Compare or Capture A */ - EVSYS_CHMUX_TCF1_CCB_gc = (0xFD<<0), /* Timer/Counter F1 Compare or Capture B */ -} EVSYS_CHMUX_t; - - -/* --------------------------------------------------------------------------- -NVM - Non Volatile Memory Controller --------------------------------------------------------------------------- -*/ - -/* Non-volatile Memory Controller */ -typedef struct NVM_struct -{ - register8_t ADDR0; /* Address Register 0 */ - register8_t ADDR1; /* Address Register 1 */ - register8_t ADDR2; /* Address Register 2 */ - register8_t reserved_0x03; - register8_t DATA0; /* Data Register 0 */ - register8_t DATA1; /* Data Register 1 */ - register8_t DATA2; /* Data Register 2 */ - register8_t reserved_0x07; - register8_t reserved_0x08; - register8_t reserved_0x09; - register8_t CMD; /* Command */ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t INTCTRL; /* Interrupt Control */ - register8_t reserved_0x0E; - register8_t STATUS; /* Status */ - register8_t LOCK_BITS; /* Lock Bits (Changed from LOCKBITS to avoid avr-libc collision) */ -} NVM_t; - -/* NVM Command */ -typedef enum NVM_CMD_enum -{ - NVM_CMD_NO_OPERATION_gc = (0x00<<0), /* Noop/Ordinary LPM */ - NVM_CMD_READ_USER_SIG_ROW_gc = (0x01<<0), /* Read user signature row */ - NVM_CMD_READ_CALIB_ROW_gc = (0x02<<0), /* Read calibration row */ - NVM_CMD_READ_EEPROM_gc = (0x06<<0), /* Read EEPROM */ - NVM_CMD_READ_FUSES_gc = (0x07<<0), /* Read fuse byte */ - NVM_CMD_WRITE_LOCK_BITS_gc = (0x08<<0), /* Write lock bits */ - NVM_CMD_ERASE_USER_SIG_ROW_gc = (0x18<<0), /* Erase user signature row */ - NVM_CMD_WRITE_USER_SIG_ROW_gc = (0x1A<<0), /* Write user signature row */ - NVM_CMD_ERASE_APP_gc = (0x20<<0), /* Erase Application Section */ - NVM_CMD_ERASE_APP_PAGE_gc = (0x22<<0), /* Erase Application Section page */ - NVM_CMD_LOAD_FLASH_BUFFER_gc = (0x23<<0), /* Load Flash page buffer */ - NVM_CMD_WRITE_APP_PAGE_gc = (0x24<<0), /* Write Application Section page */ - NVM_CMD_ERASE_WRITE_APP_PAGE_gc = (0x25<<0), /* Erase-and-write Application Section page */ - NVM_CMD_ERASE_FLASH_BUFFER_gc = (0x26<<0), /* Erase/flush Flash page buffer */ - NVM_CMD_ERASE_BOOT_PAGE_gc = (0x2A<<0), /* Erase Boot Section page */ - NVM_CMD_ERASE_FLASH_PAGE_gc = (0x2B<<0), /* Erase Flash Page */ - NVM_CMD_WRITE_BOOT_PAGE_gc = (0x2C<<0), /* Write Boot Section page */ - NVM_CMD_ERASE_WRITE_BOOT_PAGE_gc = (0x2D<<0), /* Erase-and-write Boot Section page */ - NVM_CMD_WRITE_FLASH_PAGE_gc = (0x2E<<0), /* Write Flash Page */ - NVM_CMD_ERASE_WRITE_FLASH_PAGE_gc = (0x2F<<0), /* Erase-and-write Flash Page */ - NVM_CMD_ERASE_EEPROM_gc = (0x30<<0), /* Erase EEPROM */ - NVM_CMD_ERASE_EEPROM_PAGE_gc = (0x32<<0), /* Erase EEPROM page */ - NVM_CMD_LOAD_EEPROM_BUFFER_gc = (0x33<<0), /* Load EEPROM page buffer */ - NVM_CMD_WRITE_EEPROM_PAGE_gc = (0x34<<0), /* Write EEPROM page */ - NVM_CMD_ERASE_WRITE_EEPROM_PAGE_gc = (0x35<<0), /* Erase-and-write EEPROM page */ - NVM_CMD_ERASE_EEPROM_BUFFER_gc = (0x36<<0), /* Erase/flush EEPROM page buffer */ - NVM_CMD_APP_CRC_gc = (0x38<<0), /* Application section CRC */ - NVM_CMD_BOOT_CRC_gc = (0x39<<0), /* Boot Section CRC */ - NVM_CMD_FLASH_RANGE_CRC_gc = (0x3A<<0), /* Flash Range CRC */ - NVM_CMD_CHIP_ERASE_gc = (0x40<<0), /* Erase Chip */ - NVM_CMD_READ_NVM_gc = (0x43<<0), /* Read NVM */ - NVM_CMD_WRITE_FUSE_gc = (0x4C<<0), /* Write Fuse byte */ - NVM_CMD_ERASE_BOOT_gc = (0x68<<0), /* Erase Boot Section */ - NVM_CMD_FLASH_CRC_gc = (0x78<<0), /* Flash CRC */ -} NVM_CMD_t; - -/* SPM ready interrupt level */ -typedef enum NVM_SPMLVL_enum -{ - NVM_SPMLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ - NVM_SPMLVL_LO_gc = (0x01<<2), /* Low level */ - NVM_SPMLVL_MED_gc = (0x02<<2), /* Medium level */ - NVM_SPMLVL_HI_gc = (0x03<<2), /* High level */ -} NVM_SPMLVL_t; - -/* EEPROM ready interrupt level */ -typedef enum NVM_EELVL_enum -{ - NVM_EELVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ - NVM_EELVL_LO_gc = (0x01<<0), /* Low level */ - NVM_EELVL_MED_gc = (0x02<<0), /* Medium level */ - NVM_EELVL_HI_gc = (0x03<<0), /* High level */ -} NVM_EELVL_t; - -/* Boot lock bits - boot setcion */ -typedef enum NVM_BLBB_enum -{ - NVM_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ - NVM_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ - NVM_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ - NVM_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ -} NVM_BLBB_t; - -/* Boot lock bits - application section */ -typedef enum NVM_BLBA_enum -{ - NVM_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ - NVM_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ - NVM_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ - NVM_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ -} NVM_BLBA_t; - -/* Boot lock bits - application table section */ -typedef enum NVM_BLBAT_enum -{ - NVM_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ - NVM_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ - NVM_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ - NVM_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ -} NVM_BLBAT_t; - -/* Lock bits */ -typedef enum NVM_LB_enum -{ - NVM_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ - NVM_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ - NVM_LB_NOLOCK_gc = (0x03<<0), /* No locks */ -} NVM_LB_t; - - -/* --------------------------------------------------------------------------- -AC - Analog Comparator --------------------------------------------------------------------------- -*/ - -/* Analog Comparator */ -typedef struct AC_struct -{ - register8_t AC0CTRL; /* Analog Comparator 0 Control */ - register8_t AC1CTRL; /* Analog Comparator 1 Control */ - register8_t AC0MUXCTRL; /* Analog Comparator 0 MUX Control */ - register8_t AC1MUXCTRL; /* Analog Comparator 1 MUX Control */ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t WINCTRL; /* Window Mode Control */ - register8_t STATUS; /* Status */ -} AC_t; - -/* Interrupt mode */ -typedef enum AC_INTMODE_enum -{ - AC_INTMODE_BOTHEDGES_gc = (0x00<<6), /* Interrupt on both edges */ - AC_INTMODE_FALLING_gc = (0x02<<6), /* Interrupt on falling edge */ - AC_INTMODE_RISING_gc = (0x03<<6), /* Interrupt on rising edge */ -} AC_INTMODE_t; - -/* Interrupt level */ -typedef enum AC_INTLVL_enum -{ - AC_INTLVL_OFF_gc = (0x00<<4), /* Interrupt disabled */ - AC_INTLVL_LO_gc = (0x01<<4), /* Low level */ - AC_INTLVL_MED_gc = (0x02<<4), /* Medium level */ - AC_INTLVL_HI_gc = (0x03<<4), /* High level */ -} AC_INTLVL_t; - -/* Hysteresis mode selection */ -typedef enum AC_HYSMODE_enum -{ - AC_HYSMODE_NO_gc = (0x00<<1), /* No hysteresis */ - AC_HYSMODE_SMALL_gc = (0x01<<1), /* Small hysteresis */ - AC_HYSMODE_LARGE_gc = (0x02<<1), /* Large hysteresis */ -} AC_HYSMODE_t; - -/* Positive input multiplexer selection */ -typedef enum AC_MUXPOS_enum -{ - AC_MUXPOS_PIN0_gc = (0x00<<3), /* Pin 0 */ - AC_MUXPOS_PIN1_gc = (0x01<<3), /* Pin 1 */ - AC_MUXPOS_PIN2_gc = (0x02<<3), /* Pin 2 */ - AC_MUXPOS_PIN3_gc = (0x03<<3), /* Pin 3 */ - AC_MUXPOS_PIN4_gc = (0x04<<3), /* Pin 4 */ - AC_MUXPOS_PIN5_gc = (0x05<<3), /* Pin 5 */ - AC_MUXPOS_PIN6_gc = (0x06<<3), /* Pin 6 */ - AC_MUXPOS_DAC_gc = (0x07<<3), /* DAC output */ -} AC_MUXPOS_t; - -/* Negative input multiplexer selection */ -typedef enum AC_MUXNEG_enum -{ - AC_MUXNEG_PIN0_gc = (0x00<<0), /* Pin 0 */ - AC_MUXNEG_PIN1_gc = (0x01<<0), /* Pin 1 */ - AC_MUXNEG_PIN3_gc = (0x02<<0), /* Pin 3 */ - AC_MUXNEG_PIN5_gc = (0x03<<0), /* Pin 5 */ - AC_MUXNEG_PIN7_gc = (0x04<<0), /* Pin 7 */ - AC_MUXNEG_DAC_gc = (0x05<<0), /* DAC output */ - AC_MUXNEG_BANDGAP_gc = (0x06<<0), /* Bandgap Reference */ - AC_MUXNEG_SCALER_gc = (0x07<<0), /* Internal voltage scaler */ -} AC_MUXNEG_t; - -/* Windows interrupt mode */ -typedef enum AC_WINTMODE_enum -{ - AC_WINTMODE_ABOVE_gc = (0x00<<2), /* Interrupt on above window */ - AC_WINTMODE_INSIDE_gc = (0x01<<2), /* Interrupt on inside window */ - AC_WINTMODE_BELOW_gc = (0x02<<2), /* Interrupt on below window */ - AC_WINTMODE_OUTSIDE_gc = (0x03<<2), /* Interrupt on outside window */ -} AC_WINTMODE_t; - -/* Window interrupt level */ -typedef enum AC_WINTLVL_enum -{ - AC_WINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ - AC_WINTLVL_LO_gc = (0x01<<0), /* Low priority */ - AC_WINTLVL_MED_gc = (0x02<<0), /* Medium priority */ - AC_WINTLVL_HI_gc = (0x03<<0), /* High priority */ -} AC_WINTLVL_t; - -/* Window mode state */ -typedef enum AC_WSTATE_enum -{ - AC_WSTATE_ABOVE_gc = (0x00<<6), /* Signal above window */ - AC_WSTATE_INSIDE_gc = (0x01<<6), /* Signal inside window */ - AC_WSTATE_BELOW_gc = (0x02<<6), /* Signal below window */ -} AC_WSTATE_t; - - -/* --------------------------------------------------------------------------- -ADC - Analog/Digital Converter --------------------------------------------------------------------------- -*/ - -/* ADC Channel */ -typedef struct ADC_CH_struct -{ - register8_t CTRL; /* Control Register */ - register8_t MUXCTRL; /* MUX Control */ - register8_t INTCTRL; /* Channel Interrupt Control Register */ - register8_t INTFLAGS; /* Interrupt Flags */ - _WORDREGISTER(RES); /* Channel Result */ - register8_t SCAN; /* Input Channel Scan */ - register8_t reserved_0x07; -} ADC_CH_t; - - -/* Analog-to-Digital Converter */ -typedef struct ADC_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t REFCTRL; /* Reference Control */ - register8_t EVCTRL; /* Event Control */ - register8_t PRESCALER; /* Clock Prescaler */ - register8_t reserved_0x05; - register8_t INTFLAGS; /* Interrupt Flags */ - register8_t TEMP; /* Temporary Register */ - register8_t reserved_0x08; - register8_t reserved_0x09; - register8_t reserved_0x0A; - register8_t reserved_0x0B; - _WORDREGISTER(CAL); /* Calibration Value */ - register8_t reserved_0x0E; - register8_t reserved_0x0F; - _WORDREGISTER(CH0RES); /* Channel 0 Result */ - _WORDREGISTER(CH1RES); /* Channel 1 Result */ - _WORDREGISTER(CH2RES); /* Channel 2 Result */ - _WORDREGISTER(CH3RES); /* Channel 3 Result */ - _WORDREGISTER(CMP); /* Compare Value */ - register8_t reserved_0x1A; - register8_t reserved_0x1B; - register8_t reserved_0x1C; - register8_t reserved_0x1D; - register8_t reserved_0x1E; - register8_t reserved_0x1F; - ADC_CH_t CH0; /* ADC Channel 0 */ - ADC_CH_t CH1; /* ADC Channel 1 */ - ADC_CH_t CH2; /* ADC Channel 2 */ - ADC_CH_t CH3; /* ADC Channel 3 */ -} ADC_t; - -/* Positive input multiplexer selection */ -typedef enum ADC_CH_MUXPOS_enum -{ - ADC_CH_MUXPOS_PIN0_gc = (0x00<<3), /* Input pin 0 */ - ADC_CH_MUXPOS_PIN1_gc = (0x01<<3), /* Input pin 1 */ - ADC_CH_MUXPOS_PIN2_gc = (0x02<<3), /* Input pin 2 */ - ADC_CH_MUXPOS_PIN3_gc = (0x03<<3), /* Input pin 3 */ - ADC_CH_MUXPOS_PIN4_gc = (0x04<<3), /* Input pin 4 */ - ADC_CH_MUXPOS_PIN5_gc = (0x05<<3), /* Input pin 5 */ - ADC_CH_MUXPOS_PIN6_gc = (0x06<<3), /* Input pin 6 */ - ADC_CH_MUXPOS_PIN7_gc = (0x07<<3), /* Input pin 7 */ - ADC_CH_MUXPOS_PIN8_gc = (0x08<<3), /* Input pin 8 */ - ADC_CH_MUXPOS_PIN9_gc = (0x09<<3), /* Input pin 9 */ - ADC_CH_MUXPOS_PIN10_gc = (0x0A<<3), /* Input pin 10 */ - ADC_CH_MUXPOS_PIN11_gc = (0x0B<<3), /* Input pin 11 */ - ADC_CH_MUXPOS_PIN12_gc = (0x0C<<3), /* Input pin 12 */ - ADC_CH_MUXPOS_PIN13_gc = (0x0D<<3), /* Input pin 13 */ - ADC_CH_MUXPOS_PIN14_gc = (0x0E<<3), /* Input pin 14 */ - ADC_CH_MUXPOS_PIN15_gc = (0x0F<<3), /* Input pin 15 */ -} ADC_CH_MUXPOS_t; - -/* Internal input multiplexer selections */ -typedef enum ADC_CH_MUXINT_enum -{ - ADC_CH_MUXINT_TEMP_gc = (0x00<<3), /* Temperature Reference */ - ADC_CH_MUXINT_BANDGAP_gc = (0x01<<3), /* Bandgap Reference */ - ADC_CH_MUXINT_SCALEDVCC_gc = (0x02<<3), /* 1/10 scaled VCC */ - ADC_CH_MUXINT_DAC_gc = (0x03<<3), /* DAC output */ -} ADC_CH_MUXINT_t; - -/* Negative input multiplexer selection */ -typedef enum ADC_CH_MUXNEG_enum -{ - ADC_CH_MUXNEG_PIN0_gc = (0x00<<0), /* Input pin 0 (Input Mode = 2) */ - ADC_CH_MUXNEG_PIN1_gc = (0x01<<0), /* Input pin 1 (Input Mode = 2) */ - ADC_CH_MUXNEG_PIN2_gc = (0x02<<0), /* Input pin 2 (Input Mode = 2) */ - ADC_CH_MUXNEG_PIN3_gc = (0x03<<0), /* Input pin 3 (Input Mode = 2) */ - ADC_CH_MUXNEG_PIN4_gc = (0x00<<0), /* Input pin 4 (Input Mode = 3) */ - ADC_CH_MUXNEG_PIN5_gc = (0x01<<0), /* Input pin 5 (Input Mode = 3) */ - ADC_CH_MUXNEG_PIN6_gc = (0x02<<0), /* Input pin 6 (Input Mode = 3) */ - ADC_CH_MUXNEG_PIN7_gc = (0x03<<0), /* Input pin 7 (Input Mode = 3) */ - ADC_CH_MUXNEG_GND_MODE3_gc = (0x05<<0), /* PAD Ground (Input Mode = 2) */ - ADC_CH_MUXNEG_INTGND_MODE3_gc = (0x07<<0), /* Internal Ground (Input Mode = 2) */ - ADC_CH_MUXNEG_INTGND_MODE4_gc = (0x04<<0), /* Internal Ground (Input Mode = 3) */ - ADC_CH_MUXNEG_GND_MODE4_gc = (0x07<<0), /* PAD Ground (Input Mode = 3) */ -} ADC_CH_MUXNEG_t; - -/* Input mode */ -typedef enum ADC_CH_INPUTMODE_enum -{ - ADC_CH_INPUTMODE_INTERNAL_gc = (0x00<<0), /* Internal inputs, no gain */ - ADC_CH_INPUTMODE_SINGLEENDED_gc = (0x01<<0), /* Single-ended input, no gain */ - ADC_CH_INPUTMODE_DIFF_gc = (0x02<<0), /* Differential input, no gain */ - ADC_CH_INPUTMODE_DIFFWGAIN_gc = (0x03<<0), /* Differential input, with gain */ -} ADC_CH_INPUTMODE_t; - -/* Gain factor */ -typedef enum ADC_CH_GAIN_enum -{ - ADC_CH_GAIN_1X_gc = (0x00<<2), /* 1x gain */ - ADC_CH_GAIN_2X_gc = (0x01<<2), /* 2x gain */ - ADC_CH_GAIN_4X_gc = (0x02<<2), /* 4x gain */ - ADC_CH_GAIN_8X_gc = (0x03<<2), /* 8x gain */ - ADC_CH_GAIN_16X_gc = (0x04<<2), /* 16x gain */ - ADC_CH_GAIN_32X_gc = (0x05<<2), /* 32x gain */ - ADC_CH_GAIN_64X_gc = (0x06<<2), /* 64x gain */ - ADC_CH_GAIN_DIV2_gc = (0x07<<2), /* x/2 gain */ -} ADC_CH_GAIN_t; - -/* Conversion result resolution */ -typedef enum ADC_RESOLUTION_enum -{ - ADC_RESOLUTION_12BIT_gc = (0x00<<1), /* 12-bit right-adjusted result */ - ADC_RESOLUTION_8BIT_gc = (0x02<<1), /* 8-bit right-adjusted result */ - ADC_RESOLUTION_LEFT12BIT_gc = (0x03<<1), /* 12-bit left-adjusted result */ -} ADC_RESOLUTION_t; - -/* Current Limitation Mode */ -typedef enum ADC_CURRLIMIT_enum -{ - ADC_CURRLIMIT_NO_gc = (0x00<<5), /* No limit */ - ADC_CURRLIMIT_LOW_gc = (0x01<<5), /* Low current limit, max. sampling rate 1.5MSPS */ - ADC_CURRLIMIT_MED_gc = (0x02<<5), /* Medium current limit, max. sampling rate 1MSPS */ - ADC_CURRLIMIT_HIGH_gc = (0x03<<5), /* High current limit, max. sampling rate 0.5MSPS */ -} ADC_CURRLIMIT_t; - -/* Voltage reference selection */ -typedef enum ADC_REFSEL_enum -{ - ADC_REFSEL_INT1V_gc = (0x00<<4), /* Internal 1V */ - ADC_REFSEL_INTVCC_gc = (0x01<<4), /* Internal VCC / 1.6 */ - ADC_REFSEL_AREFA_gc = (0x02<<4), /* External reference on PORT A */ - ADC_REFSEL_AREFB_gc = (0x03<<4), /* External reference on PORT B */ - ADC_REFSEL_INTVCC2_gc = (0x04<<4), /* Internal VCC / 2 */ -} ADC_REFSEL_t; - -/* Channel sweep selection */ -typedef enum ADC_SWEEP_enum -{ - ADC_SWEEP_0_gc = (0x00<<6), /* ADC Channel 0 */ - ADC_SWEEP_01_gc = (0x01<<6), /* ADC Channel 0,1 */ - ADC_SWEEP_012_gc = (0x02<<6), /* ADC Channel 0,1,2 */ - ADC_SWEEP_0123_gc = (0x03<<6), /* ADC Channel 0,1,2,3 */ -} ADC_SWEEP_t; - -/* Event channel input selection */ -typedef enum ADC_EVSEL_enum -{ - ADC_EVSEL_0123_gc = (0x00<<3), /* Event Channel 0,1,2,3 */ - ADC_EVSEL_1234_gc = (0x01<<3), /* Event Channel 1,2,3,4 */ - ADC_EVSEL_2345_gc = (0x02<<3), /* Event Channel 2,3,4,5 */ - ADC_EVSEL_3456_gc = (0x03<<3), /* Event Channel 3,4,5,6 */ - ADC_EVSEL_4567_gc = (0x04<<3), /* Event Channel 4,5,6,7 */ - ADC_EVSEL_567_gc = (0x05<<3), /* Event Channel 5,6,7 */ - ADC_EVSEL_67_gc = (0x06<<3), /* Event Channel 6,7 */ - ADC_EVSEL_7_gc = (0x07<<3), /* Event Channel 7 */ -} ADC_EVSEL_t; - -/* Event action selection */ -typedef enum ADC_EVACT_enum -{ - ADC_EVACT_NONE_gc = (0x00<<0), /* No event action */ - ADC_EVACT_CH0_gc = (0x01<<0), /* First event triggers channel 0 */ - ADC_EVACT_CH01_gc = (0x02<<0), /* First two events trigger channel 0,1 */ - ADC_EVACT_CH012_gc = (0x03<<0), /* First three events trigger channel 0,1,2 */ - ADC_EVACT_CH0123_gc = (0x04<<0), /* Events trigger channel 0,1,2,3 */ - ADC_EVACT_SWEEP_gc = (0x05<<0), /* First event triggers sweep */ - ADC_EVACT_SYNCSWEEP_gc = (0x06<<0), /* The ADC is flushed and restarted for accurate timing */ -} ADC_EVACT_t; - -/* Interupt mode */ -typedef enum ADC_CH_INTMODE_enum -{ - ADC_CH_INTMODE_COMPLETE_gc = (0x00<<2), /* Interrupt on conversion complete */ - ADC_CH_INTMODE_BELOW_gc = (0x01<<2), /* Interrupt on result below compare value */ - ADC_CH_INTMODE_ABOVE_gc = (0x03<<2), /* Interrupt on result above compare value */ -} ADC_CH_INTMODE_t; - -/* Interrupt level */ -typedef enum ADC_CH_INTLVL_enum -{ - ADC_CH_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ - ADC_CH_INTLVL_LO_gc = (0x01<<0), /* Low level */ - ADC_CH_INTLVL_MED_gc = (0x02<<0), /* Medium level */ - ADC_CH_INTLVL_HI_gc = (0x03<<0), /* High level */ -} ADC_CH_INTLVL_t; - -/* DMA request selection */ -typedef enum ADC_DMASEL_enum -{ - ADC_DMASEL_OFF_gc = (0x00<<6), /* Combined DMA request OFF */ - ADC_DMASEL_CH01_gc = (0x01<<6), /* ADC Channel 0 or 1 */ - ADC_DMASEL_CH012_gc = (0x02<<6), /* ADC Channel 0 or 1 or 2 */ - ADC_DMASEL_CH0123_gc = (0x03<<6), /* ADC Channel 0 or 1 or 2 or 3 */ -} ADC_DMASEL_t; - -/* Clock prescaler */ -typedef enum ADC_PRESCALER_enum -{ - ADC_PRESCALER_DIV4_gc = (0x00<<0), /* Divide clock by 4 */ - ADC_PRESCALER_DIV8_gc = (0x01<<0), /* Divide clock by 8 */ - ADC_PRESCALER_DIV16_gc = (0x02<<0), /* Divide clock by 16 */ - ADC_PRESCALER_DIV32_gc = (0x03<<0), /* Divide clock by 32 */ - ADC_PRESCALER_DIV64_gc = (0x04<<0), /* Divide clock by 64 */ - ADC_PRESCALER_DIV128_gc = (0x05<<0), /* Divide clock by 128 */ - ADC_PRESCALER_DIV256_gc = (0x06<<0), /* Divide clock by 256 */ - ADC_PRESCALER_DIV512_gc = (0x07<<0), /* Divide clock by 512 */ -} ADC_PRESCALER_t; - - -/* --------------------------------------------------------------------------- -DAC - Digital/Analog Converter --------------------------------------------------------------------------- -*/ - -/* Digital-to-Analog Converter */ -typedef struct DAC_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t CTRLC; /* Control Register C */ - register8_t EVCTRL; /* Event Input Control */ - register8_t reserved_0x04; - register8_t STATUS; /* Status */ - register8_t reserved_0x06; - register8_t reserved_0x07; - register8_t CH0GAINCAL; /* Gain Calibration */ - register8_t CH0OFFSETCAL; /* Offset Calibration */ - register8_t CH1GAINCAL; /* Gain Calibration */ - register8_t CH1OFFSETCAL; /* Offset Calibration */ - register8_t reserved_0x0C; - register8_t reserved_0x0D; - register8_t reserved_0x0E; - register8_t reserved_0x0F; - register8_t reserved_0x10; - register8_t reserved_0x11; - register8_t reserved_0x12; - register8_t reserved_0x13; - register8_t reserved_0x14; - register8_t reserved_0x15; - register8_t reserved_0x16; - register8_t reserved_0x17; - _WORDREGISTER(CH0DATA); /* Channel 0 Data */ - _WORDREGISTER(CH1DATA); /* Channel 1 Data */ -} DAC_t; - -/* Output channel selection */ -typedef enum DAC_CHSEL_enum -{ - DAC_CHSEL_SINGLE_gc = (0x00<<5), /* Single channel operation (Channel 0 only) */ - DAC_CHSEL_SINGLE1_gc = (0x01<<5), /* Single channel operation (Channel 1 only) */ - DAC_CHSEL_DUAL_gc = (0x02<<5), /* Dual channel operation (Channel 0 and channel 1) */ -} DAC_CHSEL_t; - -/* Reference voltage selection */ -typedef enum DAC_REFSEL_enum -{ - DAC_REFSEL_INT1V_gc = (0x00<<3), /* Internal 1V */ - DAC_REFSEL_AVCC_gc = (0x01<<3), /* Analog supply voltage */ - DAC_REFSEL_AREFA_gc = (0x02<<3), /* External reference on AREF on PORTA */ - DAC_REFSEL_AREFB_gc = (0x03<<3), /* External reference on AREF on PORTB */ -} DAC_REFSEL_t; - -/* Event channel selection */ -typedef enum DAC_EVSEL_enum -{ - DAC_EVSEL_0_gc = (0x00<<0), /* Event Channel 0 */ - DAC_EVSEL_1_gc = (0x01<<0), /* Event Channel 1 */ - DAC_EVSEL_2_gc = (0x02<<0), /* Event Channel 2 */ - DAC_EVSEL_3_gc = (0x03<<0), /* Event Channel 3 */ - DAC_EVSEL_4_gc = (0x04<<0), /* Event Channel 4 */ - DAC_EVSEL_5_gc = (0x05<<0), /* Event Channel 5 */ - DAC_EVSEL_6_gc = (0x06<<0), /* Event Channel 6 */ - DAC_EVSEL_7_gc = (0x07<<0), /* Event Channel 7 */ -} DAC_EVSEL_t; - - -/* --------------------------------------------------------------------------- -RTC - Real-Time Counter --------------------------------------------------------------------------- -*/ - -/* Real-Time Counter */ -typedef struct RTC_struct -{ - register8_t CTRL; /* Control Register */ - register8_t STATUS; /* Status Register */ - register8_t INTCTRL; /* Interrupt Control Register */ - register8_t INTFLAGS; /* Interrupt Flags */ - register8_t TEMP; /* Temporary register */ - register8_t reserved_0x05; - register8_t reserved_0x06; - register8_t reserved_0x07; - _WORDREGISTER(CNT); /* Count Register */ - _WORDREGISTER(PER); /* Period Register */ - _WORDREGISTER(COMP); /* Compare Register */ -} RTC_t; - -/* Prescaler Factor */ -typedef enum RTC_PRESCALER_enum -{ - RTC_PRESCALER_OFF_gc = (0x00<<0), /* RTC Off */ - RTC_PRESCALER_DIV1_gc = (0x01<<0), /* RTC Clock */ - RTC_PRESCALER_DIV2_gc = (0x02<<0), /* RTC Clock / 2 */ - RTC_PRESCALER_DIV8_gc = (0x03<<0), /* RTC Clock / 8 */ - RTC_PRESCALER_DIV16_gc = (0x04<<0), /* RTC Clock / 16 */ - RTC_PRESCALER_DIV64_gc = (0x05<<0), /* RTC Clock / 64 */ - RTC_PRESCALER_DIV256_gc = (0x06<<0), /* RTC Clock / 256 */ - RTC_PRESCALER_DIV1024_gc = (0x07<<0), /* RTC Clock / 1024 */ -} RTC_PRESCALER_t; - -/* Compare Interrupt level */ -typedef enum RTC_COMPINTLVL_enum -{ - RTC_COMPINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ - RTC_COMPINTLVL_LO_gc = (0x01<<2), /* Low Level */ - RTC_COMPINTLVL_MED_gc = (0x02<<2), /* Medium Level */ - RTC_COMPINTLVL_HI_gc = (0x03<<2), /* High Level */ -} RTC_COMPINTLVL_t; - -/* Overflow Interrupt level */ -typedef enum RTC_OVFINTLVL_enum -{ - RTC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - RTC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ - RTC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ - RTC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ -} RTC_OVFINTLVL_t; - - -/* --------------------------------------------------------------------------- -TWI - Two-Wire Interface --------------------------------------------------------------------------- -*/ - -/* */ -typedef struct TWI_MASTER_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t CTRLC; /* Control Register C */ - register8_t STATUS; /* Status Register */ - register8_t BAUD; /* Baurd Rate Control Register */ - register8_t ADDR; /* Address Register */ - register8_t DATA; /* Data Register */ -} TWI_MASTER_t; - - -/* */ -typedef struct TWI_SLAVE_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t STATUS; /* Status Register */ - register8_t ADDR; /* Address Register */ - register8_t DATA; /* Data Register */ - register8_t ADDRMASK; /* Address Mask Register */ -} TWI_SLAVE_t; - - -/* Two-Wire Interface */ -typedef struct TWI_struct -{ - register8_t CTRL; /* TWI Common Control Register */ - TWI_MASTER_t MASTER; /* TWI master module */ - TWI_SLAVE_t SLAVE; /* TWI slave module */ -} TWI_t; - -/* SDA Hold Time */ -typedef enum TWI_SDAHOLD_enum -{ - TWI_SDAHOLD_OFF_gc = (0x00<<1), /* SDA Hold Time off */ - TWI_SDAHOLD_50NS_gc = (0x01<<1), /* SDA Hold Time 50 ns */ - TWI_SDAHOLD_300NS_gc = (0x02<<1), /* SDA Hold Time 300 ns */ - TWI_SDAHOLD_400NS_gc = (0x03<<1), /* SDA Hold Time 400 ns */ -} TWI_SDAHOLD_t; - -/* Master Interrupt Level */ -typedef enum TWI_MASTER_INTLVL_enum -{ - TWI_MASTER_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ - TWI_MASTER_INTLVL_LO_gc = (0x01<<6), /* Low Level */ - TWI_MASTER_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ - TWI_MASTER_INTLVL_HI_gc = (0x03<<6), /* High Level */ -} TWI_MASTER_INTLVL_t; - -/* Inactive Timeout */ -typedef enum TWI_MASTER_TIMEOUT_enum -{ - TWI_MASTER_TIMEOUT_DISABLED_gc = (0x00<<2), /* Bus Timeout Disabled */ - TWI_MASTER_TIMEOUT_50US_gc = (0x01<<2), /* 50 Microseconds */ - TWI_MASTER_TIMEOUT_100US_gc = (0x02<<2), /* 100 Microseconds */ - TWI_MASTER_TIMEOUT_200US_gc = (0x03<<2), /* 200 Microseconds */ -} TWI_MASTER_TIMEOUT_t; - -/* Master Command */ -typedef enum TWI_MASTER_CMD_enum -{ - TWI_MASTER_CMD_NOACT_gc = (0x00<<0), /* No Action */ - TWI_MASTER_CMD_REPSTART_gc = (0x01<<0), /* Issue Repeated Start Condition */ - TWI_MASTER_CMD_RECVTRANS_gc = (0x02<<0), /* Receive or Transmit Data */ - TWI_MASTER_CMD_STOP_gc = (0x03<<0), /* Issue Stop Condition */ -} TWI_MASTER_CMD_t; - -/* Master Bus State */ -typedef enum TWI_MASTER_BUSSTATE_enum -{ - TWI_MASTER_BUSSTATE_UNKNOWN_gc = (0x00<<0), /* Unknown Bus State */ - TWI_MASTER_BUSSTATE_IDLE_gc = (0x01<<0), /* Bus is Idle */ - TWI_MASTER_BUSSTATE_OWNER_gc = (0x02<<0), /* This Module Controls The Bus */ - TWI_MASTER_BUSSTATE_BUSY_gc = (0x03<<0), /* The Bus is Busy */ -} TWI_MASTER_BUSSTATE_t; - -/* Slave Interrupt Level */ -typedef enum TWI_SLAVE_INTLVL_enum -{ - TWI_SLAVE_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ - TWI_SLAVE_INTLVL_LO_gc = (0x01<<6), /* Low Level */ - TWI_SLAVE_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ - TWI_SLAVE_INTLVL_HI_gc = (0x03<<6), /* High Level */ -} TWI_SLAVE_INTLVL_t; - -/* Slave Command */ -typedef enum TWI_SLAVE_CMD_enum -{ - TWI_SLAVE_CMD_NOACT_gc = (0x00<<0), /* No Action */ - TWI_SLAVE_CMD_COMPTRANS_gc = (0x02<<0), /* Used To Complete a Transaction */ - TWI_SLAVE_CMD_RESPONSE_gc = (0x03<<0), /* Used in Response to Address/Data Interrupt */ -} TWI_SLAVE_CMD_t; - - -/* --------------------------------------------------------------------------- -USB - USB --------------------------------------------------------------------------- -*/ - -/* USB Endpoint */ -typedef struct USB_EP_struct -{ - register8_t STATUS; /* Endpoint Status */ - register8_t CTRL; /* Endpoint Control */ - _WORDREGISTER(CNT); /* USB Endpoint Counter */ - _WORDREGISTER(DATAPTR); /* Data Pointer */ - _WORDREGISTER(AUXDATA); /* Auxiliary Data */ -} USB_EP_t; - - -/* Universal Serial Bus */ -typedef struct USB_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t STATUS; /* Status Register */ - register8_t ADDR; /* Address Register */ - register8_t FIFOWP; /* FIFO Write Pointer Register */ - register8_t FIFORP; /* FIFO Read Pointer Register */ - _WORDREGISTER(EPPTR); /* Endpoint Configuration Table Pointer */ - register8_t INTCTRLA; /* Interrupt Control Register A */ - register8_t INTCTRLB; /* Interrupt Control Register B */ - register8_t INTFLAGSACLR; /* Clear Interrupt Flag Register A */ - register8_t INTFLAGSASET; /* Set Interrupt Flag Register A */ - register8_t INTFLAGSBCLR; /* Clear Interrupt Flag Register B */ - register8_t INTFLAGSBSET; /* Set Interrupt Flag Register B */ - register8_t reserved_0x0E; - register8_t reserved_0x0F; - register8_t reserved_0x10; - register8_t reserved_0x11; - register8_t reserved_0x12; - register8_t reserved_0x13; - register8_t reserved_0x14; - register8_t reserved_0x15; - register8_t reserved_0x16; - register8_t reserved_0x17; - register8_t reserved_0x18; - register8_t reserved_0x19; - register8_t reserved_0x1A; - register8_t reserved_0x1B; - register8_t reserved_0x1C; - register8_t reserved_0x1D; - register8_t reserved_0x1E; - register8_t reserved_0x1F; - register8_t reserved_0x20; - register8_t reserved_0x21; - register8_t reserved_0x22; - register8_t reserved_0x23; - register8_t reserved_0x24; - register8_t reserved_0x25; - register8_t reserved_0x26; - register8_t reserved_0x27; - register8_t reserved_0x28; - register8_t reserved_0x29; - register8_t reserved_0x2A; - register8_t reserved_0x2B; - register8_t reserved_0x2C; - register8_t reserved_0x2D; - register8_t reserved_0x2E; - register8_t reserved_0x2F; - register8_t reserved_0x30; - register8_t reserved_0x31; - register8_t reserved_0x32; - register8_t reserved_0x33; - register8_t reserved_0x34; - register8_t reserved_0x35; - register8_t reserved_0x36; - register8_t reserved_0x37; - register8_t reserved_0x38; - register8_t reserved_0x39; - register8_t CAL0; /* Calibration Byte 0 */ - register8_t CAL1; /* Calibration Byte 1 */ -} USB_t; - - -/* USB Endpoint Table */ -typedef struct USB_EP_TABLE_struct -{ - USB_EP_t EP0OUT; /* Endpoint 0 */ - USB_EP_t EP0IN; /* Endpoint 0 */ - USB_EP_t EP1OUT; /* Endpoint 1 */ - USB_EP_t EP1IN; /* Endpoint 1 */ - USB_EP_t EP2OUT; /* Endpoint 2 */ - USB_EP_t EP2IN; /* Endpoint 2 */ - USB_EP_t EP3OUT; /* Endpoint 3 */ - USB_EP_t EP3IN; /* Endpoint 3 */ - USB_EP_t EP4OUT; /* Endpoint 4 */ - USB_EP_t EP4IN; /* Endpoint 4 */ - USB_EP_t EP5OUT; /* Endpoint 5 */ - USB_EP_t EP5IN; /* Endpoint 5 */ - USB_EP_t EP6OUT; /* Endpoint 6 */ - USB_EP_t EP6IN; /* Endpoint 6 */ - USB_EP_t EP7OUT; /* Endpoint 7 */ - USB_EP_t EP7IN; /* Endpoint 7 */ - USB_EP_t EP8OUT; /* Endpoint 8 */ - USB_EP_t EP8IN; /* Endpoint 8 */ - USB_EP_t EP9OUT; /* Endpoint 9 */ - USB_EP_t EP9IN; /* Endpoint 9 */ - USB_EP_t EP10OUT; /* Endpoint 10 */ - USB_EP_t EP10IN; /* Endpoint 10 */ - USB_EP_t EP11OUT; /* Endpoint 11 */ - USB_EP_t EP11IN; /* Endpoint 11 */ - USB_EP_t EP12OUT; /* Endpoint 12 */ - USB_EP_t EP12IN; /* Endpoint 12 */ - USB_EP_t EP13OUT; /* Endpoint 13 */ - USB_EP_t EP13IN; /* Endpoint 13 */ - USB_EP_t EP14OUT; /* Endpoint 14 */ - USB_EP_t EP14IN; /* Endpoint 14 */ - USB_EP_t EP15OUT; /* Endpoint 15 */ - USB_EP_t EP15IN; /* Endpoint 15 */ - register8_t reserved_0x100; - register8_t reserved_0x101; - register8_t reserved_0x102; - register8_t reserved_0x103; - register8_t reserved_0x104; - register8_t reserved_0x105; - register8_t reserved_0x106; - register8_t reserved_0x107; - register8_t reserved_0x108; - register8_t reserved_0x109; - register8_t reserved_0x10A; - register8_t reserved_0x10B; - register8_t reserved_0x10C; - register8_t reserved_0x10D; - register8_t reserved_0x10E; - register8_t reserved_0x10F; - register8_t FRAMENUML; /* Frame Number Low Byte */ - register8_t FRAMENUMH; /* Frame Number High Byte */ -} USB_EP_TABLE_t; - -/* Interrupt level */ -typedef enum USB_INTLVL_enum -{ - USB_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ - USB_INTLVL_LO_gc = (0x01<<0), /* Low level */ - USB_INTLVL_MED_gc = (0x02<<0), /* Medium level */ - USB_INTLVL_HI_gc = (0x03<<0), /* High level */ -} USB_INTLVL_t; - -/* USB Endpoint Type */ -typedef enum USB_EP_TYPE_enum -{ - USB_EP_TYPE_DISABLE_gc = (0x00<<6), /* Endpoint Disabled */ - USB_EP_TYPE_CONTROL_gc = (0x01<<6), /* Control */ - USB_EP_TYPE_BULK_gc = (0x02<<6), /* Bulk/Interrupt */ - USB_EP_TYPE_ISOCHRONOUS_gc = (0x03<<6), /* Isochronous */ -} USB_EP_TYPE_t; - -/* USB Endpoint Buffersize */ -typedef enum USB_EP_BUFSIZE_enum -{ - USB_EP_BUFSIZE_8_gc = (0x00<<0), /* 8 bytes buffer size */ - USB_EP_BUFSIZE_16_gc = (0x01<<0), /* 16 bytes buffer size */ - USB_EP_BUFSIZE_32_gc = (0x02<<0), /* 32 bytes buffer size */ - USB_EP_BUFSIZE_64_gc = (0x03<<0), /* 64 bytes buffer size */ - USB_EP_BUFSIZE_128_gc = (0x04<<0), /* 128 bytes buffer size */ - USB_EP_BUFSIZE_256_gc = (0x05<<0), /* 256 bytes buffer size */ - USB_EP_BUFSIZE_512_gc = (0x06<<0), /* 512 bytes buffer size */ - USB_EP_BUFSIZE_1023_gc = (0x07<<0), /* 1023 bytes buffer size */ -} USB_EP_BUFSIZE_t; - - -/* --------------------------------------------------------------------------- -PORT - I/O Port Configuration --------------------------------------------------------------------------- -*/ - -/* I/O Ports */ -typedef struct PORT_struct -{ - register8_t DIR; /* I/O Port Data Direction */ - register8_t DIRSET; /* I/O Port Data Direction Set */ - register8_t DIRCLR; /* I/O Port Data Direction Clear */ - register8_t DIRTGL; /* I/O Port Data Direction Toggle */ - register8_t OUT; /* I/O Port Output */ - register8_t OUTSET; /* I/O Port Output Set */ - register8_t OUTCLR; /* I/O Port Output Clear */ - register8_t OUTTGL; /* I/O Port Output Toggle */ - register8_t IN; /* I/O port Input */ - register8_t INTCTRL; /* Interrupt Control Register */ - register8_t INT0MASK; /* Port Interrupt 0 Mask */ - register8_t INT1MASK; /* Port Interrupt 1 Mask */ - register8_t INTFLAGS; /* Interrupt Flag Register */ - register8_t reserved_0x0D; - register8_t REMAP; /* I/O Port Pin Remap Register */ - register8_t reserved_0x0F; - register8_t PIN0CTRL; /* Pin 0 Control Register */ - register8_t PIN1CTRL; /* Pin 1 Control Register */ - register8_t PIN2CTRL; /* Pin 2 Control Register */ - register8_t PIN3CTRL; /* Pin 3 Control Register */ - register8_t PIN4CTRL; /* Pin 4 Control Register */ - register8_t PIN5CTRL; /* Pin 5 Control Register */ - register8_t PIN6CTRL; /* Pin 6 Control Register */ - register8_t PIN7CTRL; /* Pin 7 Control Register */ -} PORT_t; - -/* Port Interrupt 0 Level */ -typedef enum PORT_INT0LVL_enum -{ - PORT_INT0LVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - PORT_INT0LVL_LO_gc = (0x01<<0), /* Low Level */ - PORT_INT0LVL_MED_gc = (0x02<<0), /* Medium Level */ - PORT_INT0LVL_HI_gc = (0x03<<0), /* High Level */ -} PORT_INT0LVL_t; - -/* Port Interrupt 1 Level */ -typedef enum PORT_INT1LVL_enum -{ - PORT_INT1LVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ - PORT_INT1LVL_LO_gc = (0x01<<2), /* Low Level */ - PORT_INT1LVL_MED_gc = (0x02<<2), /* Medium Level */ - PORT_INT1LVL_HI_gc = (0x03<<2), /* High Level */ -} PORT_INT1LVL_t; - -/* Output/Pull Configuration */ -typedef enum PORT_OPC_enum -{ - PORT_OPC_TOTEM_gc = (0x00<<3), /* Totempole */ - PORT_OPC_BUSKEEPER_gc = (0x01<<3), /* Totempole w/ Bus keeper on Input and Output */ - PORT_OPC_PULLDOWN_gc = (0x02<<3), /* Totempole w/ Pull-down on Input */ - PORT_OPC_PULLUP_gc = (0x03<<3), /* Totempole w/ Pull-up on Input */ - PORT_OPC_WIREDOR_gc = (0x04<<3), /* Wired OR */ - PORT_OPC_WIREDAND_gc = (0x05<<3), /* Wired AND */ - PORT_OPC_WIREDORPULL_gc = (0x06<<3), /* Wired OR w/ Pull-down */ - PORT_OPC_WIREDANDPULL_gc = (0x07<<3), /* Wired AND w/ Pull-up */ -} PORT_OPC_t; - -/* Input/Sense Configuration */ -typedef enum PORT_ISC_enum -{ - PORT_ISC_BOTHEDGES_gc = (0x00<<0), /* Sense Both Edges */ - PORT_ISC_RISING_gc = (0x01<<0), /* Sense Rising Edge */ - PORT_ISC_FALLING_gc = (0x02<<0), /* Sense Falling Edge */ - PORT_ISC_LEVEL_gc = (0x03<<0), /* Sense Level (Transparent For Events) */ - PORT_ISC_INPUT_DISABLE_gc = (0x07<<0), /* Disable Digital Input Buffer */ -} PORT_ISC_t; - - -/* --------------------------------------------------------------------------- -TC - 16-bit Timer/Counter With PWM --------------------------------------------------------------------------- -*/ - -/* 16-bit Timer/Counter 0 */ -typedef struct TC0_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t CTRLC; /* Control register C */ - register8_t CTRLD; /* Control Register D */ - register8_t CTRLE; /* Control Register E */ - register8_t reserved_0x05; - register8_t INTCTRLA; /* Interrupt Control Register A */ - register8_t INTCTRLB; /* Interrupt Control Register B */ - register8_t CTRLFCLR; /* Control Register F Clear */ - register8_t CTRLFSET; /* Control Register F Set */ - register8_t CTRLGCLR; /* Control Register G Clear */ - register8_t CTRLGSET; /* Control Register G Set */ - register8_t INTFLAGS; /* Interrupt Flag Register */ - register8_t reserved_0x0D; - register8_t reserved_0x0E; - register8_t TEMP; /* Temporary Register For 16-bit Access */ - register8_t reserved_0x10; - register8_t reserved_0x11; - register8_t reserved_0x12; - register8_t reserved_0x13; - register8_t reserved_0x14; - register8_t reserved_0x15; - register8_t reserved_0x16; - register8_t reserved_0x17; - register8_t reserved_0x18; - register8_t reserved_0x19; - register8_t reserved_0x1A; - register8_t reserved_0x1B; - register8_t reserved_0x1C; - register8_t reserved_0x1D; - register8_t reserved_0x1E; - register8_t reserved_0x1F; - _WORDREGISTER(CNT); /* Count */ - register8_t reserved_0x22; - register8_t reserved_0x23; - register8_t reserved_0x24; - register8_t reserved_0x25; - _WORDREGISTER(PER); /* Period */ - _WORDREGISTER(CCA); /* Compare or Capture A */ - _WORDREGISTER(CCB); /* Compare or Capture B */ - _WORDREGISTER(CCC); /* Compare or Capture C */ - _WORDREGISTER(CCD); /* Compare or Capture D */ - register8_t reserved_0x30; - register8_t reserved_0x31; - register8_t reserved_0x32; - register8_t reserved_0x33; - register8_t reserved_0x34; - register8_t reserved_0x35; - _WORDREGISTER(PERBUF); /* Period Buffer */ - _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ - _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ - _WORDREGISTER(CCCBUF); /* Compare Or Capture C Buffer */ - _WORDREGISTER(CCDBUF); /* Compare Or Capture D Buffer */ -} TC0_t; - - -/* 16-bit Timer/Counter 1 */ -typedef struct TC1_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t CTRLC; /* Control register C */ - register8_t CTRLD; /* Control Register D */ - register8_t CTRLE; /* Control Register E */ - register8_t reserved_0x05; - register8_t INTCTRLA; /* Interrupt Control Register A */ - register8_t INTCTRLB; /* Interrupt Control Register B */ - register8_t CTRLFCLR; /* Control Register F Clear */ - register8_t CTRLFSET; /* Control Register F Set */ - register8_t CTRLGCLR; /* Control Register G Clear */ - register8_t CTRLGSET; /* Control Register G Set */ - register8_t INTFLAGS; /* Interrupt Flag Register */ - register8_t reserved_0x0D; - register8_t reserved_0x0E; - register8_t TEMP; /* Temporary Register For 16-bit Access */ - register8_t reserved_0x10; - register8_t reserved_0x11; - register8_t reserved_0x12; - register8_t reserved_0x13; - register8_t reserved_0x14; - register8_t reserved_0x15; - register8_t reserved_0x16; - register8_t reserved_0x17; - register8_t reserved_0x18; - register8_t reserved_0x19; - register8_t reserved_0x1A; - register8_t reserved_0x1B; - register8_t reserved_0x1C; - register8_t reserved_0x1D; - register8_t reserved_0x1E; - register8_t reserved_0x1F; - _WORDREGISTER(CNT); /* Count */ - register8_t reserved_0x22; - register8_t reserved_0x23; - register8_t reserved_0x24; - register8_t reserved_0x25; - _WORDREGISTER(PER); /* Period */ - _WORDREGISTER(CCA); /* Compare or Capture A */ - _WORDREGISTER(CCB); /* Compare or Capture B */ - register8_t reserved_0x2C; - register8_t reserved_0x2D; - register8_t reserved_0x2E; - register8_t reserved_0x2F; - register8_t reserved_0x30; - register8_t reserved_0x31; - register8_t reserved_0x32; - register8_t reserved_0x33; - register8_t reserved_0x34; - register8_t reserved_0x35; - _WORDREGISTER(PERBUF); /* Period Buffer */ - _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ - _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ -} TC1_t; - -/* Clock Selection */ -typedef enum TC_CLKSEL_enum -{ - TC_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */ - TC_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */ - TC_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */ - TC_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */ - TC_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */ - TC_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */ - TC_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */ - TC_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */ - TC_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */ - TC_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */ - TC_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */ - TC_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */ - TC_CLKSEL_EVCH4_gc = (0x0C<<0), /* Event Channel 4 */ - TC_CLKSEL_EVCH5_gc = (0x0D<<0), /* Event Channel 5 */ - TC_CLKSEL_EVCH6_gc = (0x0E<<0), /* Event Channel 6 */ - TC_CLKSEL_EVCH7_gc = (0x0F<<0), /* Event Channel 7 */ -} TC_CLKSEL_t; - -/* Waveform Generation Mode */ -typedef enum TC_WGMODE_enum -{ - TC_WGMODE_NORMAL_gc = (0x00<<0), /* Normal Mode */ - TC_WGMODE_FRQ_gc = (0x01<<0), /* Frequency Generation Mode */ - TC_WGMODE_SINGLESLOPE_gc = (0x03<<0), /* Single Slope */ - TC_WGMODE_SS_gc = (0x03<<0), /* Single Slope */ - TC_WGMODE_DSTOP_gc = (0x05<<0), /* Dual Slope, Update on TOP */ - TC_WGMODE_DS_T_gc = (0x05<<0), /* Dual Slope, Update on TOP */ - TC_WGMODE_DSBOTH_gc = (0x06<<0), /* Dual Slope, Update on both TOP and BOTTOM */ - TC_WGMODE_DS_TB_gc = (0x06<<0), /* Dual Slope, Update on both TOP and BOTTOM */ - TC_WGMODE_DSBOTTOM_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */ - TC_WGMODE_DS_B_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */ -} TC_WGMODE_t; - -/* Byte Mode */ -typedef enum TC_BYTEM_enum -{ - TC_BYTEM_NORMAL_gc = (0x00<<0), /* 16-bit mode */ - TC_BYTEM_BYTEMODE_gc = (0x01<<0), /* Timer/Counter operating in byte mode only */ - TC_BYTEM_SPLITMODE_gc = (0x02<<0), /* Timer/Counter split into two 8-bit Counters (TC2) */ -} TC_BYTEM_t; - -/* Event Action */ -typedef enum TC_EVACT_enum -{ - TC_EVACT_OFF_gc = (0x00<<5), /* No Event Action */ - TC_EVACT_CAPT_gc = (0x01<<5), /* Input Capture */ - TC_EVACT_UPDOWN_gc = (0x02<<5), /* Externally Controlled Up/Down Count */ - TC_EVACT_QDEC_gc = (0x03<<5), /* Quadrature Decode */ - TC_EVACT_RESTART_gc = (0x04<<5), /* Restart */ - TC_EVACT_FRQ_gc = (0x05<<5), /* Frequency Capture */ - TC_EVACT_PW_gc = (0x06<<5), /* Pulse-width Capture */ -} TC_EVACT_t; - -/* Event Selection */ -typedef enum TC_EVSEL_enum -{ - TC_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ - TC_EVSEL_CH0_gc = (0x08<<0), /* Event Channel 0 */ - TC_EVSEL_CH1_gc = (0x09<<0), /* Event Channel 1 */ - TC_EVSEL_CH2_gc = (0x0A<<0), /* Event Channel 2 */ - TC_EVSEL_CH3_gc = (0x0B<<0), /* Event Channel 3 */ - TC_EVSEL_CH4_gc = (0x0C<<0), /* Event Channel 4 */ - TC_EVSEL_CH5_gc = (0x0D<<0), /* Event Channel 5 */ - TC_EVSEL_CH6_gc = (0x0E<<0), /* Event Channel 6 */ - TC_EVSEL_CH7_gc = (0x0F<<0), /* Event Channel 7 */ -} TC_EVSEL_t; - -/* Error Interrupt Level */ -typedef enum TC_ERRINTLVL_enum -{ - TC_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ - TC_ERRINTLVL_LO_gc = (0x01<<2), /* Low Level */ - TC_ERRINTLVL_MED_gc = (0x02<<2), /* Medium Level */ - TC_ERRINTLVL_HI_gc = (0x03<<2), /* High Level */ -} TC_ERRINTLVL_t; - -/* Overflow Interrupt Level */ -typedef enum TC_OVFINTLVL_enum -{ - TC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - TC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ - TC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ - TC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ -} TC_OVFINTLVL_t; - -/* Compare or Capture D Interrupt Level */ -typedef enum TC_CCDINTLVL_enum -{ - TC_CCDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ - TC_CCDINTLVL_LO_gc = (0x01<<6), /* Low Level */ - TC_CCDINTLVL_MED_gc = (0x02<<6), /* Medium Level */ - TC_CCDINTLVL_HI_gc = (0x03<<6), /* High Level */ -} TC_CCDINTLVL_t; - -/* Compare or Capture C Interrupt Level */ -typedef enum TC_CCCINTLVL_enum -{ - TC_CCCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ - TC_CCCINTLVL_LO_gc = (0x01<<4), /* Low Level */ - TC_CCCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ - TC_CCCINTLVL_HI_gc = (0x03<<4), /* High Level */ -} TC_CCCINTLVL_t; - -/* Compare or Capture B Interrupt Level */ -typedef enum TC_CCBINTLVL_enum -{ - TC_CCBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ - TC_CCBINTLVL_LO_gc = (0x01<<2), /* Low Level */ - TC_CCBINTLVL_MED_gc = (0x02<<2), /* Medium Level */ - TC_CCBINTLVL_HI_gc = (0x03<<2), /* High Level */ -} TC_CCBINTLVL_t; - -/* Compare or Capture A Interrupt Level */ -typedef enum TC_CCAINTLVL_enum -{ - TC_CCAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - TC_CCAINTLVL_LO_gc = (0x01<<0), /* Low Level */ - TC_CCAINTLVL_MED_gc = (0x02<<0), /* Medium Level */ - TC_CCAINTLVL_HI_gc = (0x03<<0), /* High Level */ -} TC_CCAINTLVL_t; - -/* Timer/Counter Command */ -typedef enum TC_CMD_enum -{ - TC_CMD_NONE_gc = (0x00<<2), /* No Command */ - TC_CMD_UPDATE_gc = (0x01<<2), /* Force Update */ - TC_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ - TC_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ -} TC_CMD_t; - - -/* --------------------------------------------------------------------------- -TC2 - 16-bit Timer/Counter type 2 --------------------------------------------------------------------------- -*/ - -/* 16-bit Timer/Counter type 2 */ -typedef struct TC2_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t CTRLC; /* Control register C */ - register8_t reserved_0x03; - register8_t CTRLE; /* Control Register E */ - register8_t reserved_0x05; - register8_t INTCTRLA; /* Interrupt Control Register A */ - register8_t INTCTRLB; /* Interrupt Control Register B */ - register8_t reserved_0x08; - register8_t CTRLF; /* Control Register F */ - register8_t reserved_0x0A; - register8_t reserved_0x0B; - register8_t INTFLAGS; /* Interrupt Flag Register */ - register8_t reserved_0x0D; - register8_t reserved_0x0E; - register8_t reserved_0x0F; - register8_t reserved_0x10; - register8_t reserved_0x11; - register8_t reserved_0x12; - register8_t reserved_0x13; - register8_t reserved_0x14; - register8_t reserved_0x15; - register8_t reserved_0x16; - register8_t reserved_0x17; - register8_t reserved_0x18; - register8_t reserved_0x19; - register8_t reserved_0x1A; - register8_t reserved_0x1B; - register8_t reserved_0x1C; - register8_t reserved_0x1D; - register8_t reserved_0x1E; - register8_t reserved_0x1F; - register8_t LCNT; /* Low Byte Count */ - register8_t HCNT; /* High Byte Count */ - register8_t reserved_0x22; - register8_t reserved_0x23; - register8_t reserved_0x24; - register8_t reserved_0x25; - register8_t LPER; /* Low Byte Period */ - register8_t HPER; /* High Byte Period */ - register8_t LCMPA; /* Low Byte Compare A */ - register8_t HCMPA; /* High Byte Compare A */ - register8_t LCMPB; /* Low Byte Compare B */ - register8_t HCMPB; /* High Byte Compare B */ - register8_t LCMPC; /* Low Byte Compare C */ - register8_t HCMPC; /* High Byte Compare C */ - register8_t LCMPD; /* Low Byte Compare D */ - register8_t HCMPD; /* High Byte Compare D */ -} TC2_t; - -/* Clock Selection */ -typedef enum TC2_CLKSEL_enum -{ - TC2_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */ - TC2_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */ - TC2_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */ - TC2_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */ - TC2_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */ - TC2_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */ - TC2_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */ - TC2_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */ - TC2_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */ - TC2_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */ - TC2_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */ - TC2_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */ - TC2_CLKSEL_EVCH4_gc = (0x0C<<0), /* Event Channel 4 */ - TC2_CLKSEL_EVCH5_gc = (0x0D<<0), /* Event Channel 5 */ - TC2_CLKSEL_EVCH6_gc = (0x0E<<0), /* Event Channel 6 */ - TC2_CLKSEL_EVCH7_gc = (0x0F<<0), /* Event Channel 7 */ -} TC2_CLKSEL_t; - -/* Byte Mode */ -typedef enum TC2_BYTEM_enum -{ - TC2_BYTEM_NORMAL_gc = (0x00<<0), /* 16-bit mode */ - TC2_BYTEM_BYTEMODE_gc = (0x01<<0), /* Timer/Counter operating in byte mode only (TC2) */ - TC2_BYTEM_SPLITMODE_gc = (0x02<<0), /* Timer/Counter split into two 8-bit Counters */ -} TC2_BYTEM_t; - -/* High Byte Underflow Interrupt Level */ -typedef enum TC2_HUNFINTLVL_enum -{ - TC2_HUNFINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ - TC2_HUNFINTLVL_LO_gc = (0x01<<2), /* Low Level */ - TC2_HUNFINTLVL_MED_gc = (0x02<<2), /* Medium Level */ - TC2_HUNFINTLVL_HI_gc = (0x03<<2), /* High Level */ -} TC2_HUNFINTLVL_t; - -/* Low Byte Underflow Interrupt Level */ -typedef enum TC2_LUNFINTLVL_enum -{ - TC2_LUNFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - TC2_LUNFINTLVL_LO_gc = (0x01<<0), /* Low Level */ - TC2_LUNFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ - TC2_LUNFINTLVL_HI_gc = (0x03<<0), /* High Level */ -} TC2_LUNFINTLVL_t; - -/* Low Byte Compare D Interrupt Level */ -typedef enum TC2_LCMPDINTLVL_enum -{ - TC2_LCMPDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ - TC2_LCMPDINTLVL_LO_gc = (0x01<<6), /* Low Level */ - TC2_LCMPDINTLVL_MED_gc = (0x02<<6), /* Medium Level */ - TC2_LCMPDINTLVL_HI_gc = (0x03<<6), /* High Level */ -} TC2_LCMPDINTLVL_t; - -/* Low Byte Compare C Interrupt Level */ -typedef enum TC2_LCMPCINTLVL_enum -{ - TC2_LCMPCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ - TC2_LCMPCINTLVL_LO_gc = (0x01<<4), /* Low Level */ - TC2_LCMPCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ - TC2_LCMPCINTLVL_HI_gc = (0x03<<4), /* High Level */ -} TC2_LCMPCINTLVL_t; - -/* Low Byte Compare B Interrupt Level */ -typedef enum TC2_LCMPBINTLVL_enum -{ - TC2_LCMPBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ - TC2_LCMPBINTLVL_LO_gc = (0x01<<2), /* Low Level */ - TC2_LCMPBINTLVL_MED_gc = (0x02<<2), /* Medium Level */ - TC2_LCMPBINTLVL_HI_gc = (0x03<<2), /* High Level */ -} TC2_LCMPBINTLVL_t; - -/* Low Byte Compare A Interrupt Level */ -typedef enum TC2_LCMPAINTLVL_enum -{ - TC2_LCMPAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - TC2_LCMPAINTLVL_LO_gc = (0x01<<0), /* Low Level */ - TC2_LCMPAINTLVL_MED_gc = (0x02<<0), /* Medium Level */ - TC2_LCMPAINTLVL_HI_gc = (0x03<<0), /* High Level */ -} TC2_LCMPAINTLVL_t; - -/* Timer/Counter Command */ -typedef enum TC2_CMD_enum -{ - TC2_CMD_NONE_gc = (0x00<<2), /* No Command */ - TC2_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ - TC2_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ -} TC2_CMD_t; - -/* Timer/Counter Command */ -typedef enum TC2_CMDEN_enum -{ - TC2_CMDEN_LOW_gc = (0x01<<0), /* Low Byte Timer/Counter */ - TC2_CMDEN_HIGH_gc = (0x02<<0), /* High Byte Timer/Counter */ - TC2_CMDEN_BOTH_gc = (0x03<<0), /* Both Low Byte and High Byte Timer/Counters */ -} TC2_CMDEN_t; - - -/* --------------------------------------------------------------------------- -AWEX - Timer/Counter Advanced Waveform Extension --------------------------------------------------------------------------- -*/ - -/* Advanced Waveform Extension */ -typedef struct AWEX_struct -{ - register8_t CTRL; /* Control Register */ - register8_t reserved_0x01; - register8_t FDEMASK; /* Fault Detection Event Mask */ - register8_t FDCTRL; /* Fault Detection Control Register */ - register8_t STATUS; /* Status Register */ - register8_t STATUSSET; /* Status Set Register */ - register8_t DTBOTH; /* Dead Time Both Sides */ - register8_t DTBOTHBUF; /* Dead Time Both Sides Buffer */ - register8_t DTLS; /* Dead Time Low Side */ - register8_t DTHS; /* Dead Time High Side */ - register8_t DTLSBUF; /* Dead Time Low Side Buffer */ - register8_t DTHSBUF; /* Dead Time High Side Buffer */ - register8_t OUTOVEN; /* Output Override Enable */ -} AWEX_t; - -/* Fault Detect Action */ -typedef enum AWEX_FDACT_enum -{ - AWEX_FDACT_NONE_gc = (0x00<<0), /* No Fault Protection */ - AWEX_FDACT_CLEAROE_gc = (0x01<<0), /* Clear Output Enable Bits */ - AWEX_FDACT_CLEARDIR_gc = (0x03<<0), /* Clear I/O Port Direction Bits */ -} AWEX_FDACT_t; - - -/* --------------------------------------------------------------------------- -HIRES - Timer/Counter High-Resolution Extension --------------------------------------------------------------------------- -*/ - -/* High-Resolution Extension */ -typedef struct HIRES_struct -{ - register8_t CTRLA; /* Control Register */ -} HIRES_t; - -/* High Resolution Enable */ -typedef enum HIRES_HREN_enum -{ - HIRES_HREN_NONE_gc = (0x00<<0), /* No Fault Protection */ - HIRES_HREN_TC0_gc = (0x01<<0), /* Enable High Resolution on Timer/Counter 0 */ - HIRES_HREN_TC1_gc = (0x02<<0), /* Enable High Resolution on Timer/Counter 1 */ - HIRES_HREN_BOTH_gc = (0x03<<0), /* Enable High Resolution both Timer/Counters */ -} HIRES_HREN_t; - - -/* --------------------------------------------------------------------------- -USART - Universal Asynchronous Receiver-Transmitter --------------------------------------------------------------------------- -*/ - -/* Universal Synchronous/Asynchronous Receiver/Transmitter */ -typedef struct USART_struct -{ - register8_t DATA; /* Data Register */ - register8_t STATUS; /* Status Register */ - register8_t reserved_0x02; - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t CTRLC; /* Control Register C */ - register8_t BAUDCTRLA; /* Baud Rate Control Register A */ - register8_t BAUDCTRLB; /* Baud Rate Control Register B */ -} USART_t; - -/* Receive Complete Interrupt level */ -typedef enum USART_RXCINTLVL_enum -{ - USART_RXCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ - USART_RXCINTLVL_LO_gc = (0x01<<4), /* Low Level */ - USART_RXCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ - USART_RXCINTLVL_HI_gc = (0x03<<4), /* High Level */ -} USART_RXCINTLVL_t; - -/* Transmit Complete Interrupt level */ -typedef enum USART_TXCINTLVL_enum -{ - USART_TXCINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ - USART_TXCINTLVL_LO_gc = (0x01<<2), /* Low Level */ - USART_TXCINTLVL_MED_gc = (0x02<<2), /* Medium Level */ - USART_TXCINTLVL_HI_gc = (0x03<<2), /* High Level */ -} USART_TXCINTLVL_t; - -/* Data Register Empty Interrupt level */ -typedef enum USART_DREINTLVL_enum -{ - USART_DREINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - USART_DREINTLVL_LO_gc = (0x01<<0), /* Low Level */ - USART_DREINTLVL_MED_gc = (0x02<<0), /* Medium Level */ - USART_DREINTLVL_HI_gc = (0x03<<0), /* High Level */ -} USART_DREINTLVL_t; - -/* Character Size */ -typedef enum USART_CHSIZE_enum -{ - USART_CHSIZE_5BIT_gc = (0x00<<0), /* Character size: 5 bit */ - USART_CHSIZE_6BIT_gc = (0x01<<0), /* Character size: 6 bit */ - USART_CHSIZE_7BIT_gc = (0x02<<0), /* Character size: 7 bit */ - USART_CHSIZE_8BIT_gc = (0x03<<0), /* Character size: 8 bit */ - USART_CHSIZE_9BIT_gc = (0x07<<0), /* Character size: 9 bit */ -} USART_CHSIZE_t; - -/* Communication Mode */ -typedef enum USART_CMODE_enum -{ - USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6), /* Asynchronous Mode */ - USART_CMODE_SYNCHRONOUS_gc = (0x01<<6), /* Synchronous Mode */ - USART_CMODE_IRDA_gc = (0x02<<6), /* IrDA Mode */ - USART_CMODE_MSPI_gc = (0x03<<6), /* Master SPI Mode */ -} USART_CMODE_t; - -/* Parity Mode */ -typedef enum USART_PMODE_enum -{ - USART_PMODE_DISABLED_gc = (0x00<<4), /* No Parity */ - USART_PMODE_EVEN_gc = (0x02<<4), /* Even Parity */ - USART_PMODE_ODD_gc = (0x03<<4), /* Odd Parity */ -} USART_PMODE_t; - - -/* --------------------------------------------------------------------------- -SPI - Serial Peripheral Interface --------------------------------------------------------------------------- -*/ - -/* Serial Peripheral Interface */ -typedef struct SPI_struct -{ - register8_t CTRL; /* Control Register */ - register8_t INTCTRL; /* Interrupt Control Register */ - register8_t STATUS; /* Status Register */ - register8_t DATA; /* Data Register */ -} SPI_t; - -/* SPI Mode */ -typedef enum SPI_MODE_enum -{ - SPI_MODE_0_gc = (0x00<<2), /* SPI Mode 0 */ - SPI_MODE_1_gc = (0x01<<2), /* SPI Mode 1 */ - SPI_MODE_2_gc = (0x02<<2), /* SPI Mode 2 */ - SPI_MODE_3_gc = (0x03<<2), /* SPI Mode 3 */ -} SPI_MODE_t; - -/* Prescaler setting */ -typedef enum SPI_PRESCALER_enum -{ - SPI_PRESCALER_DIV4_gc = (0x00<<0), /* System Clock / 4 */ - SPI_PRESCALER_DIV16_gc = (0x01<<0), /* System Clock / 16 */ - SPI_PRESCALER_DIV64_gc = (0x02<<0), /* System Clock / 64 */ - SPI_PRESCALER_DIV128_gc = (0x03<<0), /* System Clock / 128 */ -} SPI_PRESCALER_t; - -/* Interrupt level */ -typedef enum SPI_INTLVL_enum -{ - SPI_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - SPI_INTLVL_LO_gc = (0x01<<0), /* Low Level */ - SPI_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ - SPI_INTLVL_HI_gc = (0x03<<0), /* High Level */ -} SPI_INTLVL_t; - - -/* --------------------------------------------------------------------------- -IRCOM - IR Communication Module --------------------------------------------------------------------------- -*/ - -/* IR Communication Module */ -typedef struct IRCOM_struct -{ - register8_t CTRL; /* Control Register */ - register8_t TXPLCTRL; /* IrDA Transmitter Pulse Length Control Register */ - register8_t RXPLCTRL; /* IrDA Receiver Pulse Length Control Register */ -} IRCOM_t; - -/* Event channel selection */ -typedef enum IRDA_EVSEL_enum -{ - IRDA_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ - IRDA_EVSEL_0_gc = (0x08<<0), /* Event Channel 0 */ - IRDA_EVSEL_1_gc = (0x09<<0), /* Event Channel 1 */ - IRDA_EVSEL_2_gc = (0x0A<<0), /* Event Channel 2 */ - IRDA_EVSEL_3_gc = (0x0B<<0), /* Event Channel 3 */ - IRDA_EVSEL_4_gc = (0x0C<<0), /* Event Channel 4 */ - IRDA_EVSEL_5_gc = (0x0D<<0), /* Event Channel 5 */ - IRDA_EVSEL_6_gc = (0x0E<<0), /* Event Channel 6 */ - IRDA_EVSEL_7_gc = (0x0F<<0), /* Event Channel 7 */ -} IRDA_EVSEL_t; - - -/* --------------------------------------------------------------------------- -FUSE - Fuses and Lockbits --------------------------------------------------------------------------- -*/ - -/* Fuses */ -typedef struct NVM_FUSES_struct -{ - register8_t FUSEBYTE0; /* JTAG User ID */ - register8_t FUSEBYTE1; /* Watchdog Configuration */ - register8_t FUSEBYTE2; /* Reset Configuration */ - register8_t reserved_0x03; - register8_t FUSEBYTE4; /* Start-up Configuration */ - register8_t FUSEBYTE5; /* EESAVE and BOD Level */ -} NVM_FUSES_t; - -/* Boot Loader Section Reset Vector */ -typedef enum BOOTRST_enum -{ - BOOTRST_BOOTLDR_gc = (0x00<<6), /* Boot Loader Reset */ - BOOTRST_APPLICATION_gc = (0x01<<6), /* Application Reset */ -} BOOTRST_t; - -/* Timer Oscillator pin location */ -typedef enum TOSCSEL_enum -{ - TOSCSEL_ALTERNATE_gc = (0x00<<5), /* TOSC1 / TOSC2 on separate pins */ - TOSCSEL_XTAL_gc = (0x01<<5), /* TOSC1 / TOSC2 shared with XTAL1 / XTAL2 */ -} TOSCSEL_t; - -/* BOD operation */ -typedef enum BOD_enum -{ - BOD_SAMPLED_gc = (0x01<<0), /* BOD enabled in sampled mode */ - BOD_CONTINUOUS_gc = (0x02<<0), /* BOD enabled continuously */ - BOD_DISABLED_gc = (0x03<<0), /* BOD Disabled */ -} BOD_t; - -/* BOD operation */ -typedef enum BODACT_enum -{ - BODACT_SAMPLED_gc = (0x01<<4), /* BOD enabled in sampled mode */ - BODACT_CONTINUOUS_gc = (0x02<<4), /* BOD enabled continuously */ - BODACT_DISABLED_gc = (0x03<<4), /* BOD Disabled */ -} BODACT_t; - -/* Watchdog (Window) Timeout Period */ -typedef enum WD_enum -{ - WD_8CLK_gc = (0x00<<4), /* 8 cycles (8ms @ 3.3V) */ - WD_16CLK_gc = (0x01<<4), /* 16 cycles (16ms @ 3.3V) */ - WD_32CLK_gc = (0x02<<4), /* 32 cycles (32ms @ 3.3V) */ - WD_64CLK_gc = (0x03<<4), /* 64 cycles (64ms @ 3.3V) */ - WD_128CLK_gc = (0x04<<4), /* 128 cycles (0.125s @ 3.3V) */ - WD_256CLK_gc = (0x05<<4), /* 256 cycles (0.25s @ 3.3V) */ - WD_512CLK_gc = (0x06<<4), /* 512 cycles (0.5s @ 3.3V) */ - WD_1KCLK_gc = (0x07<<4), /* 1K cycles (1s @ 3.3V) */ - WD_2KCLK_gc = (0x08<<4), /* 2K cycles (2s @ 3.3V) */ - WD_4KCLK_gc = (0x09<<4), /* 4K cycles (4s @ 3.3V) */ - WD_8KCLK_gc = (0x0A<<4), /* 8K cycles (8s @ 3.3V) */ -} WD_t; - -/* Watchdog (Window) Timeout Period */ -typedef enum WDP_enum -{ - WDP_8CLK_gc = (0x00<<0), /* 8 cycles (8ms @ 3.3V) */ - WDP_16CLK_gc = (0x01<<0), /* 16 cycles (16ms @ 3.3V) */ - WDP_32CLK_gc = (0x02<<0), /* 32 cycles (32ms @ 3.3V) */ - WDP_64CLK_gc = (0x03<<0), /* 64 cycles (64ms @ 3.3V) */ - WDP_128CLK_gc = (0x04<<0), /* 128 cycles (0.125s @ 3.3V) */ - WDP_256CLK_gc = (0x05<<0), /* 256 cycles (0.25s @ 3.3V) */ - WDP_512CLK_gc = (0x06<<0), /* 512 cycles (0.5s @ 3.3V) */ - WDP_1KCLK_gc = (0x07<<0), /* 1K cycles (1s @ 3.3V) */ - WDP_2KCLK_gc = (0x08<<0), /* 2K cycles (2s @ 3.3V) */ - WDP_4KCLK_gc = (0x09<<0), /* 4K cycles (4s @ 3.3V) */ - WDP_8KCLK_gc = (0x0A<<0), /* 8K cycles (8s @ 3.3V) */ -} WDP_t; - -/* Start-up Time */ -typedef enum SUT_enum -{ - SUT_0MS_gc = (0x03<<2), /* 0 ms */ - SUT_4MS_gc = (0x01<<2), /* 4 ms */ - SUT_64MS_gc = (0x00<<2), /* 64 ms */ -} SUT_t; - -/* Brownout Detection Voltage Level */ -typedef enum BODLVL_enum -{ - BODLVL_1V6_gc = (0x07<<0), /* 1.6 V */ - BODLVL_1V8_gc = (0x06<<0), /* 1.8 V */ - BODLVL_2V0_gc = (0x05<<0), /* 2.0 V */ - BODLVL_2V2_gc = (0x04<<0), /* 2.2 V */ - BODLVL_2V4_gc = (0x03<<0), /* 2.4 V */ - BODLVL_2V6_gc = (0x02<<0), /* 2.6 V */ - BODLVL_2V8_gc = (0x01<<0), /* 2.8 V */ - BODLVL_3V0_gc = (0x00<<0), /* 3.0 V */ -} BODLVL_t; - - -/* --------------------------------------------------------------------------- -LOCKBIT - Fuses and Lockbits --------------------------------------------------------------------------- -*/ - -/* Lock Bits */ -typedef struct NVM_LOCKBITS_struct -{ - register8_t LOCK_BITS; /* Lock Bits (Changed from LOCKBITS to avoid avr-libc collision) */ -} NVM_LOCKBITS_t; - -/* Boot lock bits - boot setcion */ -typedef enum FUSE_BLBB_enum -{ - FUSE_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ - FUSE_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ - FUSE_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ - FUSE_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ -} FUSE_BLBB_t; - -/* Boot lock bits - application section */ -typedef enum FUSE_BLBA_enum -{ - FUSE_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ - FUSE_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ - FUSE_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ - FUSE_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ -} FUSE_BLBA_t; - -/* Boot lock bits - application table section */ -typedef enum FUSE_BLBAT_enum -{ - FUSE_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ - FUSE_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ - FUSE_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ - FUSE_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ -} FUSE_BLBAT_t; - -/* Lock bits */ -typedef enum FUSE_LB_enum -{ - FUSE_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ - FUSE_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ - FUSE_LB_NOLOCK_gc = (0x03<<0), /* No locks */ -} FUSE_LB_t; - - -/* --------------------------------------------------------------------------- -SIGROW - Signature Row --------------------------------------------------------------------------- -*/ - -/* Production Signatures */ -typedef struct NVM_PROD_SIGNATURES_struct -{ - register8_t RCOSC2M; /* RCOSC 2 MHz Calibration Value B */ - register8_t RCOSC2MA; /* RCOSC 2 MHz Calibration Value A */ - register8_t RCOSC32K; /* RCOSC 32.768 kHz Calibration Value */ - register8_t RCOSC32M; /* RCOSC 32 MHz Calibration Value B */ - register8_t RCOSC32MA; /* RCOSC 32 MHz Calibration Value A */ - register8_t reserved_0x05; - register8_t reserved_0x06; - register8_t reserved_0x07; - register8_t LOTNUM0; /* Lot Number Byte 0, ASCII */ - register8_t LOTNUM1; /* Lot Number Byte 1, ASCII */ - register8_t LOTNUM2; /* Lot Number Byte 2, ASCII */ - register8_t LOTNUM3; /* Lot Number Byte 3, ASCII */ - register8_t LOTNUM4; /* Lot Number Byte 4, ASCII */ - register8_t LOTNUM5; /* Lot Number Byte 5, ASCII */ - register8_t reserved_0x0E; - register8_t reserved_0x0F; - register8_t WAFNUM; /* Wafer Number */ - register8_t reserved_0x11; - register8_t COORDX0; /* Wafer Coordinate X Byte 0 */ - register8_t COORDX1; /* Wafer Coordinate X Byte 1 */ - register8_t COORDY0; /* Wafer Coordinate Y Byte 0 */ - register8_t COORDY1; /* Wafer Coordinate Y Byte 1 */ - register8_t reserved_0x16; - register8_t reserved_0x17; - register8_t reserved_0x18; - register8_t reserved_0x19; - register8_t USBCAL0; /* USB Calibration Byte 0 */ - register8_t USBCAL1; /* USB Calibration Byte 1 */ - register8_t USBRCOSC; /* USB RCOSC Calibration Value B */ - register8_t USBRCOSCA; /* USB RCOSC Calibration Value A */ - register8_t reserved_0x1E; - register8_t reserved_0x1F; - register8_t ADCACAL0; /* ADCA Calibration Byte 0 */ - register8_t ADCACAL1; /* ADCA Calibration Byte 1 */ - register8_t reserved_0x22; - register8_t reserved_0x23; - register8_t ADCBCAL0; /* ADCB Calibration Byte 0 */ - register8_t ADCBCAL1; /* ADCB Calibration Byte 1 */ - register8_t reserved_0x26; - register8_t reserved_0x27; - register8_t reserved_0x28; - register8_t reserved_0x29; - register8_t reserved_0x2A; - register8_t reserved_0x2B; - register8_t reserved_0x2C; - register8_t reserved_0x2D; - register8_t TEMPSENSE0; /* Temperature Sensor Calibration Byte 0 */ - register8_t TEMPSENSE1; /* Temperature Sensor Calibration Byte 1 */ - register8_t DACA0OFFCAL; /* DACA0 Calibration Byte 0 */ - register8_t DACA0GAINCAL; /* DACA0 Calibration Byte 1 */ - register8_t DACB0OFFCAL; /* DACB0 Calibration Byte 0 */ - register8_t DACB0GAINCAL; /* DACB0 Calibration Byte 1 */ - register8_t DACA1OFFCAL; /* DACA1 Calibration Byte 0 */ - register8_t DACA1GAINCAL; /* DACA1 Calibration Byte 1 */ - register8_t DACB1OFFCAL; /* DACB1 Calibration Byte 0 */ - register8_t DACB1GAINCAL; /* DACB1 Calibration Byte 1 */ - register8_t reserved_0x38; - register8_t reserved_0x39; - register8_t reserved_0x3A; - register8_t reserved_0x3B; - register8_t reserved_0x3C; - register8_t reserved_0x3D; - register8_t reserved_0x3E; - register8_t reserved_0x3F; - register8_t reserved_0x40; - register8_t reserved_0x41; - register8_t reserved_0x42; - register8_t reserved_0x43; - register8_t reserved_0x44; - register8_t reserved_0x45; - register8_t reserved_0x46; - register8_t reserved_0x47; -} NVM_PROD_SIGNATURES_t; - -/* -========================================================================== -IO Module Instances. Mapped to memory. -========================================================================== -*/ - -#define VPORT0 (*(VPORT_t *) 0x0010) /* Virtual Port */ -#define VPORT1 (*(VPORT_t *) 0x0014) /* Virtual Port */ -#define VPORT2 (*(VPORT_t *) 0x0018) /* Virtual Port */ -#define VPORT3 (*(VPORT_t *) 0x001C) /* Virtual Port */ -#define OCD (*(OCD_t *) 0x002E) /* On-Chip Debug System */ -#define CLK (*(CLK_t *) 0x0040) /* Clock System */ -#define SLEEP (*(SLEEP_t *) 0x0048) /* Sleep Controller */ -#define OSC (*(OSC_t *) 0x0050) /* Oscillator */ -#define DFLLRC32M (*(DFLL_t *) 0x0060) /* DFLL */ -#define DFLLRC2M (*(DFLL_t *) 0x0068) /* DFLL */ -#define PR (*(PR_t *) 0x0070) /* Power Reduction */ -#define RST (*(RST_t *) 0x0078) /* Reset */ -#define WDT (*(WDT_t *) 0x0080) /* Watch-Dog Timer */ -#define MCU (*(MCU_t *) 0x0090) /* MCU Control */ -#define PMIC (*(PMIC_t *) 0x00A0) /* Programmable Multi-level Interrupt Controller */ -#define PORTCFG (*(PORTCFG_t *) 0x00B0) /* I/O port Configuration */ -#define AES (*(AES_t *) 0x00C0) /* AES Module */ -#define CRC (*(CRC_t *) 0x00D0) /* Cyclic Redundancy Checker */ -#define DMA (*(DMA_t *) 0x0100) /* DMA Controller */ -#define EVSYS (*(EVSYS_t *) 0x0180) /* Event System */ -#define NVM (*(NVM_t *) 0x01C0) /* Non-volatile Memory Controller */ -#define ADCA (*(ADC_t *) 0x0200) /* Analog-to-Digital Converter */ -#define ADCB (*(ADC_t *) 0x0240) /* Analog-to-Digital Converter */ -#define DACB (*(DAC_t *) 0x0320) /* Digital-to-Analog Converter */ -#define ACA (*(AC_t *) 0x0380) /* Analog Comparator */ -#define ACB (*(AC_t *) 0x0390) /* Analog Comparator */ -#define RTC (*(RTC_t *) 0x0400) /* Real-Time Counter */ -#define TWIC (*(TWI_t *) 0x0480) /* Two-Wire Interface */ -#define TWIE (*(TWI_t *) 0x04A0) /* Two-Wire Interface */ -#define USB (*(USB_t *) 0x04C0) /* Universal Serial Bus */ -#define PORTA (*(PORT_t *) 0x0600) /* I/O Ports */ -#define PORTB (*(PORT_t *) 0x0620) /* I/O Ports */ -#define PORTC (*(PORT_t *) 0x0640) /* I/O Ports */ -#define PORTD (*(PORT_t *) 0x0660) /* I/O Ports */ -#define PORTE (*(PORT_t *) 0x0680) /* I/O Ports */ -#define PORTF (*(PORT_t *) 0x06A0) /* I/O Ports */ -#define PORTR (*(PORT_t *) 0x07E0) /* I/O Ports */ -#define TCC0 (*(TC0_t *) 0x0800) /* 16-bit Timer/Counter 0 */ -#define TCC2 (*(TC2_t *) 0x0800) /* 16-bit Timer/Counter type 2 */ -#define TCC1 (*(TC1_t *) 0x0840) /* 16-bit Timer/Counter 1 */ -#define AWEXC (*(AWEX_t *) 0x0880) /* Advanced Waveform Extension */ -#define HIRESC (*(HIRES_t *) 0x0890) /* High-Resolution Extension */ -#define USARTC0 (*(USART_t *) 0x08A0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ -#define USARTC1 (*(USART_t *) 0x08B0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ -#define SPIC (*(SPI_t *) 0x08C0) /* Serial Peripheral Interface */ -#define IRCOM (*(IRCOM_t *) 0x08F8) /* IR Communication Module */ -#define TCD0 (*(TC0_t *) 0x0900) /* 16-bit Timer/Counter 0 */ -#define TCD2 (*(TC2_t *) 0x0900) /* 16-bit Timer/Counter type 2 */ -#define TCD1 (*(TC1_t *) 0x0940) /* 16-bit Timer/Counter 1 */ -#define HIRESD (*(HIRES_t *) 0x0990) /* High-Resolution Extension */ -#define USARTD0 (*(USART_t *) 0x09A0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ -#define USARTD1 (*(USART_t *) 0x09B0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ -#define SPID (*(SPI_t *) 0x09C0) /* Serial Peripheral Interface */ -#define TCE0 (*(TC0_t *) 0x0A00) /* 16-bit Timer/Counter 0 */ -#define TCE2 (*(TC2_t *) 0x0A00) /* 16-bit Timer/Counter type 2 */ -#define TCE1 (*(TC1_t *) 0x0A40) /* 16-bit Timer/Counter 1 */ -#define AWEXE (*(AWEX_t *) 0x0A80) /* Advanced Waveform Extension */ -#define HIRESE (*(HIRES_t *) 0x0A90) /* High-Resolution Extension */ -#define USARTE0 (*(USART_t *) 0x0AA0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ -#define USARTE1 (*(USART_t *) 0x0AB0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ -#define SPIE (*(SPI_t *) 0x0AC0) /* Serial Peripheral Interface */ -#define TCF0 (*(TC0_t *) 0x0B00) /* 16-bit Timer/Counter 0 */ -#define TCF2 (*(TC2_t *) 0x0B00) /* 16-bit Timer/Counter type 2 */ -#define HIRESF (*(HIRES_t *) 0x0B90) /* High-Resolution Extension */ -#define USARTF0 (*(USART_t *) 0x0BA0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ - - -#endif /* !defined (__ASSEMBLER__) */ - - -/* ========== Flattened fully qualified IO register names ========== */ - -/* GPIO - General Purpose IO Registers */ -#define GPIO_GPIOR0 _SFR_MEM8(0x0000) -#define GPIO_GPIOR1 _SFR_MEM8(0x0001) -#define GPIO_GPIOR2 _SFR_MEM8(0x0002) -#define GPIO_GPIOR3 _SFR_MEM8(0x0003) -#define GPIO_GPIOR4 _SFR_MEM8(0x0004) -#define GPIO_GPIOR5 _SFR_MEM8(0x0005) -#define GPIO_GPIOR6 _SFR_MEM8(0x0006) -#define GPIO_GPIOR7 _SFR_MEM8(0x0007) -#define GPIO_GPIOR8 _SFR_MEM8(0x0008) -#define GPIO_GPIOR9 _SFR_MEM8(0x0009) -#define GPIO_GPIORA _SFR_MEM8(0x000A) -#define GPIO_GPIORB _SFR_MEM8(0x000B) -#define GPIO_GPIORC _SFR_MEM8(0x000C) -#define GPIO_GPIORD _SFR_MEM8(0x000D) -#define GPIO_GPIORE _SFR_MEM8(0x000E) -#define GPIO_GPIORF _SFR_MEM8(0x000F) - -/* Deprecated */ -#define GPIO_GPIO0 _SFR_MEM8(0x0000) -#define GPIO_GPIO1 _SFR_MEM8(0x0001) -#define GPIO_GPIO2 _SFR_MEM8(0x0002) -#define GPIO_GPIO3 _SFR_MEM8(0x0003) -#define GPIO_GPIO4 _SFR_MEM8(0x0004) -#define GPIO_GPIO5 _SFR_MEM8(0x0005) -#define GPIO_GPIO6 _SFR_MEM8(0x0006) -#define GPIO_GPIO7 _SFR_MEM8(0x0007) -#define GPIO_GPIO8 _SFR_MEM8(0x0008) -#define GPIO_GPIO9 _SFR_MEM8(0x0009) -#define GPIO_GPIOA _SFR_MEM8(0x000A) -#define GPIO_GPIOB _SFR_MEM8(0x000B) -#define GPIO_GPIOC _SFR_MEM8(0x000C) -#define GPIO_GPIOD _SFR_MEM8(0x000D) -#define GPIO_GPIOE _SFR_MEM8(0x000E) -#define GPIO_GPIOF _SFR_MEM8(0x000F) - -/* NVM_FUSES - Fuses */ -#define FUSE_FUSEBYTE0 _SFR_MEM8(0x0000) -#define FUSE_FUSEBYTE1 _SFR_MEM8(0x0001) -#define FUSE_FUSEBYTE2 _SFR_MEM8(0x0002) -#define FUSE_FUSEBYTE4 _SFR_MEM8(0x0004) -#define FUSE_FUSEBYTE5 _SFR_MEM8(0x0005) - -/* NVM_LOCKBITS - Lock Bits */ -#define LOCKBIT_LOCKBITS _SFR_MEM8(0x0000) - -/* NVM_PROD_SIGNATURES - Production Signatures */ -#define PRODSIGNATURES_RCOSC2M _SFR_MEM8(0x0000) -#define PRODSIGNATURES_RCOSC2MA _SFR_MEM8(0x0001) -#define PRODSIGNATURES_RCOSC32K _SFR_MEM8(0x0002) -#define PRODSIGNATURES_RCOSC32M _SFR_MEM8(0x0003) -#define PRODSIGNATURES_RCOSC32MA _SFR_MEM8(0x0004) -#define PRODSIGNATURES_LOTNUM0 _SFR_MEM8(0x0008) -#define PRODSIGNATURES_LOTNUM1 _SFR_MEM8(0x0009) -#define PRODSIGNATURES_LOTNUM2 _SFR_MEM8(0x000A) -#define PRODSIGNATURES_LOTNUM3 _SFR_MEM8(0x000B) -#define PRODSIGNATURES_LOTNUM4 _SFR_MEM8(0x000C) -#define PRODSIGNATURES_LOTNUM5 _SFR_MEM8(0x000D) -#define PRODSIGNATURES_WAFNUM _SFR_MEM8(0x0010) -#define PRODSIGNATURES_COORDX0 _SFR_MEM8(0x0012) -#define PRODSIGNATURES_COORDX1 _SFR_MEM8(0x0013) -#define PRODSIGNATURES_COORDY0 _SFR_MEM8(0x0014) -#define PRODSIGNATURES_COORDY1 _SFR_MEM8(0x0015) -#define PRODSIGNATURES_USBCAL0 _SFR_MEM8(0x001A) -#define PRODSIGNATURES_USBCAL1 _SFR_MEM8(0x001B) -#define PRODSIGNATURES_USBRCOSC _SFR_MEM8(0x001C) -#define PRODSIGNATURES_USBRCOSCA _SFR_MEM8(0x001D) -#define PRODSIGNATURES_ADCACAL0 _SFR_MEM8(0x0020) -#define PRODSIGNATURES_ADCACAL1 _SFR_MEM8(0x0021) -#define PRODSIGNATURES_ADCBCAL0 _SFR_MEM8(0x0024) -#define PRODSIGNATURES_ADCBCAL1 _SFR_MEM8(0x0025) -#define PRODSIGNATURES_TEMPSENSE0 _SFR_MEM8(0x002E) -#define PRODSIGNATURES_TEMPSENSE1 _SFR_MEM8(0x002F) -#define PRODSIGNATURES_DACA0OFFCAL _SFR_MEM8(0x0030) -#define PRODSIGNATURES_DACA0GAINCAL _SFR_MEM8(0x0031) -#define PRODSIGNATURES_DACB0OFFCAL _SFR_MEM8(0x0032) -#define PRODSIGNATURES_DACB0GAINCAL _SFR_MEM8(0x0033) -#define PRODSIGNATURES_DACA1OFFCAL _SFR_MEM8(0x0034) -#define PRODSIGNATURES_DACA1GAINCAL _SFR_MEM8(0x0035) -#define PRODSIGNATURES_DACB1OFFCAL _SFR_MEM8(0x0036) -#define PRODSIGNATURES_DACB1GAINCAL _SFR_MEM8(0x0037) - -/* VPORT - Virtual Port */ -#define VPORT0_DIR _SFR_MEM8(0x0010) -#define VPORT0_OUT _SFR_MEM8(0x0011) -#define VPORT0_IN _SFR_MEM8(0x0012) -#define VPORT0_INTFLAGS _SFR_MEM8(0x0013) - -/* VPORT - Virtual Port */ -#define VPORT1_DIR _SFR_MEM8(0x0014) -#define VPORT1_OUT _SFR_MEM8(0x0015) -#define VPORT1_IN _SFR_MEM8(0x0016) -#define VPORT1_INTFLAGS _SFR_MEM8(0x0017) - -/* VPORT - Virtual Port */ -#define VPORT2_DIR _SFR_MEM8(0x0018) -#define VPORT2_OUT _SFR_MEM8(0x0019) -#define VPORT2_IN _SFR_MEM8(0x001A) -#define VPORT2_INTFLAGS _SFR_MEM8(0x001B) - -/* VPORT - Virtual Port */ -#define VPORT3_DIR _SFR_MEM8(0x001C) -#define VPORT3_OUT _SFR_MEM8(0x001D) -#define VPORT3_IN _SFR_MEM8(0x001E) -#define VPORT3_INTFLAGS _SFR_MEM8(0x001F) - -/* OCD - On-Chip Debug System */ -#define OCD_OCDR0 _SFR_MEM8(0x002E) -#define OCD_OCDR1 _SFR_MEM8(0x002F) - -/* CPU - CPU registers */ -#define CPU_CCP _SFR_MEM8(0x0034) -#define CPU_RAMPD _SFR_MEM8(0x0038) -#define CPU_RAMPX _SFR_MEM8(0x0039) -#define CPU_RAMPY _SFR_MEM8(0x003A) -#define CPU_RAMPZ _SFR_MEM8(0x003B) -#define CPU_EIND _SFR_MEM8(0x003C) -#define CPU_SPL _SFR_MEM8(0x003D) -#define CPU_SPH _SFR_MEM8(0x003E) -#define CPU_SREG _SFR_MEM8(0x003F) - -/* CLK - Clock System */ -#define CLK_CTRL _SFR_MEM8(0x0040) -#define CLK_PSCTRL _SFR_MEM8(0x0041) -#define CLK_LOCK _SFR_MEM8(0x0042) -#define CLK_RTCCTRL _SFR_MEM8(0x0043) -#define CLK_USBCTRL _SFR_MEM8(0x0044) - -/* SLEEP - Sleep Controller */ -#define SLEEP_CTRL _SFR_MEM8(0x0048) - -/* OSC - Oscillator */ -#define OSC_CTRL _SFR_MEM8(0x0050) -#define OSC_STATUS _SFR_MEM8(0x0051) -#define OSC_XOSCCTRL _SFR_MEM8(0x0052) -#define OSC_XOSCFAIL _SFR_MEM8(0x0053) -#define OSC_RC32KCAL _SFR_MEM8(0x0054) -#define OSC_PLLCTRL _SFR_MEM8(0x0055) -#define OSC_DFLLCTRL _SFR_MEM8(0x0056) - -/* DFLL - DFLL */ -#define DFLLRC32M_CTRL _SFR_MEM8(0x0060) -#define DFLLRC32M_CALA _SFR_MEM8(0x0062) -#define DFLLRC32M_CALB _SFR_MEM8(0x0063) -#define DFLLRC32M_COMP0 _SFR_MEM8(0x0064) -#define DFLLRC32M_COMP1 _SFR_MEM8(0x0065) -#define DFLLRC32M_COMP2 _SFR_MEM8(0x0066) - -/* DFLL - DFLL */ -#define DFLLRC2M_CTRL _SFR_MEM8(0x0068) -#define DFLLRC2M_CALA _SFR_MEM8(0x006A) -#define DFLLRC2M_CALB _SFR_MEM8(0x006B) -#define DFLLRC2M_COMP0 _SFR_MEM8(0x006C) -#define DFLLRC2M_COMP1 _SFR_MEM8(0x006D) -#define DFLLRC2M_COMP2 _SFR_MEM8(0x006E) - -/* PR - Power Reduction */ -#define PR_PRGEN _SFR_MEM8(0x0070) -#define PR_PRPA _SFR_MEM8(0x0071) -#define PR_PRPB _SFR_MEM8(0x0072) -#define PR_PRPC _SFR_MEM8(0x0073) -#define PR_PRPD _SFR_MEM8(0x0074) -#define PR_PRPE _SFR_MEM8(0x0075) -#define PR_PRPF _SFR_MEM8(0x0076) - -/* RST - Reset */ -#define RST_STATUS _SFR_MEM8(0x0078) -#define RST_CTRL _SFR_MEM8(0x0079) - -/* WDT - Watch-Dog Timer */ -#define WDT_CTRL _SFR_MEM8(0x0080) -#define WDT_WINCTRL _SFR_MEM8(0x0081) -#define WDT_STATUS _SFR_MEM8(0x0082) - -/* MCU - MCU Control */ -#define MCU_DEVID0 _SFR_MEM8(0x0090) -#define MCU_DEVID1 _SFR_MEM8(0x0091) -#define MCU_DEVID2 _SFR_MEM8(0x0092) -#define MCU_REVID _SFR_MEM8(0x0093) -#define MCU_JTAGUID _SFR_MEM8(0x0094) -#define MCU_MCUCR _SFR_MEM8(0x0096) -#define MCU_ANAINIT _SFR_MEM8(0x0097) -#define MCU_EVSYSLOCK _SFR_MEM8(0x0098) -#define MCU_AWEXLOCK _SFR_MEM8(0x0099) - -/* PMIC - Programmable Multi-level Interrupt Controller */ -#define PMIC_STATUS _SFR_MEM8(0x00A0) -#define PMIC_INTPRI _SFR_MEM8(0x00A1) -#define PMIC_CTRL _SFR_MEM8(0x00A2) - -/* PORTCFG - I/O port Configuration */ -#define PORTCFG_MPCMASK _SFR_MEM8(0x00B0) -#define PORTCFG_VPCTRLA _SFR_MEM8(0x00B2) -#define PORTCFG_VPCTRLB _SFR_MEM8(0x00B3) -#define PORTCFG_CLKEVOUT _SFR_MEM8(0x00B4) -#define PORTCFG_EBIOUT _SFR_MEM8(0x00B5) -#define PORTCFG_EVOUTSEL _SFR_MEM8(0x00B6) - -/* AES - AES Module */ -#define AES_CTRL _SFR_MEM8(0x00C0) -#define AES_STATUS _SFR_MEM8(0x00C1) -#define AES_STATE _SFR_MEM8(0x00C2) -#define AES_KEY _SFR_MEM8(0x00C3) -#define AES_INTCTRL _SFR_MEM8(0x00C4) - -/* CRC - Cyclic Redundancy Checker */ -#define CRC_CTRL _SFR_MEM8(0x00D0) -#define CRC_STATUS _SFR_MEM8(0x00D1) -#define CRC_DATAIN _SFR_MEM8(0x00D3) -#define CRC_CHECKSUM0 _SFR_MEM8(0x00D4) -#define CRC_CHECKSUM1 _SFR_MEM8(0x00D5) -#define CRC_CHECKSUM2 _SFR_MEM8(0x00D6) -#define CRC_CHECKSUM3 _SFR_MEM8(0x00D7) - -/* DMA - DMA Controller */ -#define DMA_CTRL _SFR_MEM8(0x0100) -#define DMA_INTFLAGS _SFR_MEM8(0x0103) -#define DMA_STATUS _SFR_MEM8(0x0104) -#define DMA_TEMP _SFR_MEM16(0x0106) -#define DMA_CH0_CTRLA _SFR_MEM8(0x0110) -#define DMA_CH0_CTRLB _SFR_MEM8(0x0111) -#define DMA_CH0_ADDRCTRL _SFR_MEM8(0x0112) -#define DMA_CH0_TRIGSRC _SFR_MEM8(0x0113) -#define DMA_CH0_TRFCNT _SFR_MEM16(0x0114) -#define DMA_CH0_REPCNT _SFR_MEM8(0x0116) -#define DMA_CH0_SRCADDR0 _SFR_MEM8(0x0118) -#define DMA_CH0_SRCADDR1 _SFR_MEM8(0x0119) -#define DMA_CH0_SRCADDR2 _SFR_MEM8(0x011A) -#define DMA_CH0_DESTADDR0 _SFR_MEM8(0x011C) -#define DMA_CH0_DESTADDR1 _SFR_MEM8(0x011D) -#define DMA_CH0_DESTADDR2 _SFR_MEM8(0x011E) -#define DMA_CH1_CTRLA _SFR_MEM8(0x0120) -#define DMA_CH1_CTRLB _SFR_MEM8(0x0121) -#define DMA_CH1_ADDRCTRL _SFR_MEM8(0x0122) -#define DMA_CH1_TRIGSRC _SFR_MEM8(0x0123) -#define DMA_CH1_TRFCNT _SFR_MEM16(0x0124) -#define DMA_CH1_REPCNT _SFR_MEM8(0x0126) -#define DMA_CH1_SRCADDR0 _SFR_MEM8(0x0128) -#define DMA_CH1_SRCADDR1 _SFR_MEM8(0x0129) -#define DMA_CH1_SRCADDR2 _SFR_MEM8(0x012A) -#define DMA_CH1_DESTADDR0 _SFR_MEM8(0x012C) -#define DMA_CH1_DESTADDR1 _SFR_MEM8(0x012D) -#define DMA_CH1_DESTADDR2 _SFR_MEM8(0x012E) -#define DMA_CH2_CTRLA _SFR_MEM8(0x0130) -#define DMA_CH2_CTRLB _SFR_MEM8(0x0131) -#define DMA_CH2_ADDRCTRL _SFR_MEM8(0x0132) -#define DMA_CH2_TRIGSRC _SFR_MEM8(0x0133) -#define DMA_CH2_TRFCNT _SFR_MEM16(0x0134) -#define DMA_CH2_REPCNT _SFR_MEM8(0x0136) -#define DMA_CH2_SRCADDR0 _SFR_MEM8(0x0138) -#define DMA_CH2_SRCADDR1 _SFR_MEM8(0x0139) -#define DMA_CH2_SRCADDR2 _SFR_MEM8(0x013A) -#define DMA_CH2_DESTADDR0 _SFR_MEM8(0x013C) -#define DMA_CH2_DESTADDR1 _SFR_MEM8(0x013D) -#define DMA_CH2_DESTADDR2 _SFR_MEM8(0x013E) -#define DMA_CH3_CTRLA _SFR_MEM8(0x0140) -#define DMA_CH3_CTRLB _SFR_MEM8(0x0141) -#define DMA_CH3_ADDRCTRL _SFR_MEM8(0x0142) -#define DMA_CH3_TRIGSRC _SFR_MEM8(0x0143) -#define DMA_CH3_TRFCNT _SFR_MEM16(0x0144) -#define DMA_CH3_REPCNT _SFR_MEM8(0x0146) -#define DMA_CH3_SRCADDR0 _SFR_MEM8(0x0148) -#define DMA_CH3_SRCADDR1 _SFR_MEM8(0x0149) -#define DMA_CH3_SRCADDR2 _SFR_MEM8(0x014A) -#define DMA_CH3_DESTADDR0 _SFR_MEM8(0x014C) -#define DMA_CH3_DESTADDR1 _SFR_MEM8(0x014D) -#define DMA_CH3_DESTADDR2 _SFR_MEM8(0x014E) - -/* EVSYS - Event System */ -#define EVSYS_CH0MUX _SFR_MEM8(0x0180) -#define EVSYS_CH1MUX _SFR_MEM8(0x0181) -#define EVSYS_CH2MUX _SFR_MEM8(0x0182) -#define EVSYS_CH3MUX _SFR_MEM8(0x0183) -#define EVSYS_CH4MUX _SFR_MEM8(0x0184) -#define EVSYS_CH5MUX _SFR_MEM8(0x0185) -#define EVSYS_CH6MUX _SFR_MEM8(0x0186) -#define EVSYS_CH7MUX _SFR_MEM8(0x0187) -#define EVSYS_CH0CTRL _SFR_MEM8(0x0188) -#define EVSYS_CH1CTRL _SFR_MEM8(0x0189) -#define EVSYS_CH2CTRL _SFR_MEM8(0x018A) -#define EVSYS_CH3CTRL _SFR_MEM8(0x018B) -#define EVSYS_CH4CTRL _SFR_MEM8(0x018C) -#define EVSYS_CH5CTRL _SFR_MEM8(0x018D) -#define EVSYS_CH6CTRL _SFR_MEM8(0x018E) -#define EVSYS_CH7CTRL _SFR_MEM8(0x018F) -#define EVSYS_STROBE _SFR_MEM8(0x0190) -#define EVSYS_DATA _SFR_MEM8(0x0191) - -/* NVM - Non-volatile Memory Controller */ -#define NVM_ADDR0 _SFR_MEM8(0x01C0) -#define NVM_ADDR1 _SFR_MEM8(0x01C1) -#define NVM_ADDR2 _SFR_MEM8(0x01C2) -#define NVM_DATA0 _SFR_MEM8(0x01C4) -#define NVM_DATA1 _SFR_MEM8(0x01C5) -#define NVM_DATA2 _SFR_MEM8(0x01C6) -#define NVM_CMD _SFR_MEM8(0x01CA) -#define NVM_CTRLA _SFR_MEM8(0x01CB) -#define NVM_CTRLB _SFR_MEM8(0x01CC) -#define NVM_INTCTRL _SFR_MEM8(0x01CD) -#define NVM_STATUS _SFR_MEM8(0x01CF) -#define NVM_LOCKBITS _SFR_MEM8(0x01D0) - -/* ADC - Analog-to-Digital Converter */ -#define ADCA_CTRLA _SFR_MEM8(0x0200) -#define ADCA_CTRLB _SFR_MEM8(0x0201) -#define ADCA_REFCTRL _SFR_MEM8(0x0202) -#define ADCA_EVCTRL _SFR_MEM8(0x0203) -#define ADCA_PRESCALER _SFR_MEM8(0x0204) -#define ADCA_INTFLAGS _SFR_MEM8(0x0206) -#define ADCA_TEMP _SFR_MEM8(0x0207) -#define ADCA_CAL _SFR_MEM16(0x020C) -#define ADCA_CH0RES _SFR_MEM16(0x0210) -#define ADCA_CH1RES _SFR_MEM16(0x0212) -#define ADCA_CH2RES _SFR_MEM16(0x0214) -#define ADCA_CH3RES _SFR_MEM16(0x0216) -#define ADCA_CMP _SFR_MEM16(0x0218) -#define ADCA_CH0_CTRL _SFR_MEM8(0x0220) -#define ADCA_CH0_MUXCTRL _SFR_MEM8(0x0221) -#define ADCA_CH0_INTCTRL _SFR_MEM8(0x0222) -#define ADCA_CH0_INTFLAGS _SFR_MEM8(0x0223) -#define ADCA_CH0_RES _SFR_MEM16(0x0224) -#define ADCA_CH0_SCAN _SFR_MEM8(0x0226) -#define ADCA_CH1_CTRL _SFR_MEM8(0x0228) -#define ADCA_CH1_MUXCTRL _SFR_MEM8(0x0229) -#define ADCA_CH1_INTCTRL _SFR_MEM8(0x022A) -#define ADCA_CH1_INTFLAGS _SFR_MEM8(0x022B) -#define ADCA_CH1_RES _SFR_MEM16(0x022C) -#define ADCA_CH1_SCAN _SFR_MEM8(0x022E) -#define ADCA_CH2_CTRL _SFR_MEM8(0x0230) -#define ADCA_CH2_MUXCTRL _SFR_MEM8(0x0231) -#define ADCA_CH2_INTCTRL _SFR_MEM8(0x0232) -#define ADCA_CH2_INTFLAGS _SFR_MEM8(0x0233) -#define ADCA_CH2_RES _SFR_MEM16(0x0234) -#define ADCA_CH2_SCAN _SFR_MEM8(0x0236) -#define ADCA_CH3_CTRL _SFR_MEM8(0x0238) -#define ADCA_CH3_MUXCTRL _SFR_MEM8(0x0239) -#define ADCA_CH3_INTCTRL _SFR_MEM8(0x023A) -#define ADCA_CH3_INTFLAGS _SFR_MEM8(0x023B) -#define ADCA_CH3_RES _SFR_MEM16(0x023C) -#define ADCA_CH3_SCAN _SFR_MEM8(0x023E) - -/* ADC - Analog-to-Digital Converter */ -#define ADCB_CTRLA _SFR_MEM8(0x0240) -#define ADCB_CTRLB _SFR_MEM8(0x0241) -#define ADCB_REFCTRL _SFR_MEM8(0x0242) -#define ADCB_EVCTRL _SFR_MEM8(0x0243) -#define ADCB_PRESCALER _SFR_MEM8(0x0244) -#define ADCB_INTFLAGS _SFR_MEM8(0x0246) -#define ADCB_TEMP _SFR_MEM8(0x0247) -#define ADCB_CAL _SFR_MEM16(0x024C) -#define ADCB_CH0RES _SFR_MEM16(0x0250) -#define ADCB_CH1RES _SFR_MEM16(0x0252) -#define ADCB_CH2RES _SFR_MEM16(0x0254) -#define ADCB_CH3RES _SFR_MEM16(0x0256) -#define ADCB_CMP _SFR_MEM16(0x0258) -#define ADCB_CH0_CTRL _SFR_MEM8(0x0260) -#define ADCB_CH0_MUXCTRL _SFR_MEM8(0x0261) -#define ADCB_CH0_INTCTRL _SFR_MEM8(0x0262) -#define ADCB_CH0_INTFLAGS _SFR_MEM8(0x0263) -#define ADCB_CH0_RES _SFR_MEM16(0x0264) -#define ADCB_CH0_SCAN _SFR_MEM8(0x0266) -#define ADCB_CH1_CTRL _SFR_MEM8(0x0268) -#define ADCB_CH1_MUXCTRL _SFR_MEM8(0x0269) -#define ADCB_CH1_INTCTRL _SFR_MEM8(0x026A) -#define ADCB_CH1_INTFLAGS _SFR_MEM8(0x026B) -#define ADCB_CH1_RES _SFR_MEM16(0x026C) -#define ADCB_CH1_SCAN _SFR_MEM8(0x026E) -#define ADCB_CH2_CTRL _SFR_MEM8(0x0270) -#define ADCB_CH2_MUXCTRL _SFR_MEM8(0x0271) -#define ADCB_CH2_INTCTRL _SFR_MEM8(0x0272) -#define ADCB_CH2_INTFLAGS _SFR_MEM8(0x0273) -#define ADCB_CH2_RES _SFR_MEM16(0x0274) -#define ADCB_CH2_SCAN _SFR_MEM8(0x0276) -#define ADCB_CH3_CTRL _SFR_MEM8(0x0278) -#define ADCB_CH3_MUXCTRL _SFR_MEM8(0x0279) -#define ADCB_CH3_INTCTRL _SFR_MEM8(0x027A) -#define ADCB_CH3_INTFLAGS _SFR_MEM8(0x027B) -#define ADCB_CH3_RES _SFR_MEM16(0x027C) -#define ADCB_CH3_SCAN _SFR_MEM8(0x027E) - -/* DAC - Digital-to-Analog Converter */ -#define DACB_CTRLA _SFR_MEM8(0x0320) -#define DACB_CTRLB _SFR_MEM8(0x0321) -#define DACB_CTRLC _SFR_MEM8(0x0322) -#define DACB_EVCTRL _SFR_MEM8(0x0323) -#define DACB_STATUS _SFR_MEM8(0x0325) -#define DACB_CH0GAINCAL _SFR_MEM8(0x0328) -#define DACB_CH0OFFSETCAL _SFR_MEM8(0x0329) -#define DACB_CH1GAINCAL _SFR_MEM8(0x032A) -#define DACB_CH1OFFSETCAL _SFR_MEM8(0x032B) -#define DACB_CH0DATA _SFR_MEM16(0x0338) -#define DACB_CH1DATA _SFR_MEM16(0x033A) - -/* AC - Analog Comparator */ -#define ACA_AC0CTRL _SFR_MEM8(0x0380) -#define ACA_AC1CTRL _SFR_MEM8(0x0381) -#define ACA_AC0MUXCTRL _SFR_MEM8(0x0382) -#define ACA_AC1MUXCTRL _SFR_MEM8(0x0383) -#define ACA_CTRLA _SFR_MEM8(0x0384) -#define ACA_CTRLB _SFR_MEM8(0x0385) -#define ACA_WINCTRL _SFR_MEM8(0x0386) -#define ACA_STATUS _SFR_MEM8(0x0387) - -/* AC - Analog Comparator */ -#define ACB_AC0CTRL _SFR_MEM8(0x0390) -#define ACB_AC1CTRL _SFR_MEM8(0x0391) -#define ACB_AC0MUXCTRL _SFR_MEM8(0x0392) -#define ACB_AC1MUXCTRL _SFR_MEM8(0x0393) -#define ACB_CTRLA _SFR_MEM8(0x0394) -#define ACB_CTRLB _SFR_MEM8(0x0395) -#define ACB_WINCTRL _SFR_MEM8(0x0396) -#define ACB_STATUS _SFR_MEM8(0x0397) - -/* RTC - Real-Time Counter */ -#define RTC_CTRL _SFR_MEM8(0x0400) -#define RTC_STATUS _SFR_MEM8(0x0401) -#define RTC_INTCTRL _SFR_MEM8(0x0402) -#define RTC_INTFLAGS _SFR_MEM8(0x0403) -#define RTC_TEMP _SFR_MEM8(0x0404) -#define RTC_CNT _SFR_MEM16(0x0408) -#define RTC_PER _SFR_MEM16(0x040A) -#define RTC_COMP _SFR_MEM16(0x040C) - -/* TWI - Two-Wire Interface */ -#define TWIC_CTRL _SFR_MEM8(0x0480) -#define TWIC_MASTER_CTRLA _SFR_MEM8(0x0481) -#define TWIC_MASTER_CTRLB _SFR_MEM8(0x0482) -#define TWIC_MASTER_CTRLC _SFR_MEM8(0x0483) -#define TWIC_MASTER_STATUS _SFR_MEM8(0x0484) -#define TWIC_MASTER_BAUD _SFR_MEM8(0x0485) -#define TWIC_MASTER_ADDR _SFR_MEM8(0x0486) -#define TWIC_MASTER_DATA _SFR_MEM8(0x0487) -#define TWIC_SLAVE_CTRLA _SFR_MEM8(0x0488) -#define TWIC_SLAVE_CTRLB _SFR_MEM8(0x0489) -#define TWIC_SLAVE_STATUS _SFR_MEM8(0x048A) -#define TWIC_SLAVE_ADDR _SFR_MEM8(0x048B) -#define TWIC_SLAVE_DATA _SFR_MEM8(0x048C) -#define TWIC_SLAVE_ADDRMASK _SFR_MEM8(0x048D) - -/* TWI - Two-Wire Interface */ -#define TWIE_CTRL _SFR_MEM8(0x04A0) -#define TWIE_MASTER_CTRLA _SFR_MEM8(0x04A1) -#define TWIE_MASTER_CTRLB _SFR_MEM8(0x04A2) -#define TWIE_MASTER_CTRLC _SFR_MEM8(0x04A3) -#define TWIE_MASTER_STATUS _SFR_MEM8(0x04A4) -#define TWIE_MASTER_BAUD _SFR_MEM8(0x04A5) -#define TWIE_MASTER_ADDR _SFR_MEM8(0x04A6) -#define TWIE_MASTER_DATA _SFR_MEM8(0x04A7) -#define TWIE_SLAVE_CTRLA _SFR_MEM8(0x04A8) -#define TWIE_SLAVE_CTRLB _SFR_MEM8(0x04A9) -#define TWIE_SLAVE_STATUS _SFR_MEM8(0x04AA) -#define TWIE_SLAVE_ADDR _SFR_MEM8(0x04AB) -#define TWIE_SLAVE_DATA _SFR_MEM8(0x04AC) -#define TWIE_SLAVE_ADDRMASK _SFR_MEM8(0x04AD) - -/* USB - Universal Serial Bus */ -#define USB_CTRLA _SFR_MEM8(0x04C0) -#define USB_CTRLB _SFR_MEM8(0x04C1) -#define USB_STATUS _SFR_MEM8(0x04C2) -#define USB_ADDR _SFR_MEM8(0x04C3) -#define USB_FIFOWP _SFR_MEM8(0x04C4) -#define USB_FIFORP _SFR_MEM8(0x04C5) -#define USB_EPPTR _SFR_MEM16(0x04C6) -#define USB_INTCTRLA _SFR_MEM8(0x04C8) -#define USB_INTCTRLB _SFR_MEM8(0x04C9) -#define USB_INTFLAGSACLR _SFR_MEM8(0x04CA) -#define USB_INTFLAGSASET _SFR_MEM8(0x04CB) -#define USB_INTFLAGSBCLR _SFR_MEM8(0x04CC) -#define USB_INTFLAGSBSET _SFR_MEM8(0x04CD) -#define USB_CAL0 _SFR_MEM8(0x04FA) -#define USB_CAL1 _SFR_MEM8(0x04FB) - -/* PORT - I/O Ports */ -#define PORTA_DIR _SFR_MEM8(0x0600) -#define PORTA_DIRSET _SFR_MEM8(0x0601) -#define PORTA_DIRCLR _SFR_MEM8(0x0602) -#define PORTA_DIRTGL _SFR_MEM8(0x0603) -#define PORTA_OUT _SFR_MEM8(0x0604) -#define PORTA_OUTSET _SFR_MEM8(0x0605) -#define PORTA_OUTCLR _SFR_MEM8(0x0606) -#define PORTA_OUTTGL _SFR_MEM8(0x0607) -#define PORTA_IN _SFR_MEM8(0x0608) -#define PORTA_INTCTRL _SFR_MEM8(0x0609) -#define PORTA_INT0MASK _SFR_MEM8(0x060A) -#define PORTA_INT1MASK _SFR_MEM8(0x060B) -#define PORTA_INTFLAGS _SFR_MEM8(0x060C) -#define PORTA_REMAP _SFR_MEM8(0x060E) -#define PORTA_PIN0CTRL _SFR_MEM8(0x0610) -#define PORTA_PIN1CTRL _SFR_MEM8(0x0611) -#define PORTA_PIN2CTRL _SFR_MEM8(0x0612) -#define PORTA_PIN3CTRL _SFR_MEM8(0x0613) -#define PORTA_PIN4CTRL _SFR_MEM8(0x0614) -#define PORTA_PIN5CTRL _SFR_MEM8(0x0615) -#define PORTA_PIN6CTRL _SFR_MEM8(0x0616) -#define PORTA_PIN7CTRL _SFR_MEM8(0x0617) - -/* PORT - I/O Ports */ -#define PORTB_DIR _SFR_MEM8(0x0620) -#define PORTB_DIRSET _SFR_MEM8(0x0621) -#define PORTB_DIRCLR _SFR_MEM8(0x0622) -#define PORTB_DIRTGL _SFR_MEM8(0x0623) -#define PORTB_OUT _SFR_MEM8(0x0624) -#define PORTB_OUTSET _SFR_MEM8(0x0625) -#define PORTB_OUTCLR _SFR_MEM8(0x0626) -#define PORTB_OUTTGL _SFR_MEM8(0x0627) -#define PORTB_IN _SFR_MEM8(0x0628) -#define PORTB_INTCTRL _SFR_MEM8(0x0629) -#define PORTB_INT0MASK _SFR_MEM8(0x062A) -#define PORTB_INT1MASK _SFR_MEM8(0x062B) -#define PORTB_INTFLAGS _SFR_MEM8(0x062C) -#define PORTB_REMAP _SFR_MEM8(0x062E) -#define PORTB_PIN0CTRL _SFR_MEM8(0x0630) -#define PORTB_PIN1CTRL _SFR_MEM8(0x0631) -#define PORTB_PIN2CTRL _SFR_MEM8(0x0632) -#define PORTB_PIN3CTRL _SFR_MEM8(0x0633) -#define PORTB_PIN4CTRL _SFR_MEM8(0x0634) -#define PORTB_PIN5CTRL _SFR_MEM8(0x0635) -#define PORTB_PIN6CTRL _SFR_MEM8(0x0636) -#define PORTB_PIN7CTRL _SFR_MEM8(0x0637) - -/* PORT - I/O Ports */ -#define PORTC_DIR _SFR_MEM8(0x0640) -#define PORTC_DIRSET _SFR_MEM8(0x0641) -#define PORTC_DIRCLR _SFR_MEM8(0x0642) -#define PORTC_DIRTGL _SFR_MEM8(0x0643) -#define PORTC_OUT _SFR_MEM8(0x0644) -#define PORTC_OUTSET _SFR_MEM8(0x0645) -#define PORTC_OUTCLR _SFR_MEM8(0x0646) -#define PORTC_OUTTGL _SFR_MEM8(0x0647) -#define PORTC_IN _SFR_MEM8(0x0648) -#define PORTC_INTCTRL _SFR_MEM8(0x0649) -#define PORTC_INT0MASK _SFR_MEM8(0x064A) -#define PORTC_INT1MASK _SFR_MEM8(0x064B) -#define PORTC_INTFLAGS _SFR_MEM8(0x064C) -#define PORTC_REMAP _SFR_MEM8(0x064E) -#define PORTC_PIN0CTRL _SFR_MEM8(0x0650) -#define PORTC_PIN1CTRL _SFR_MEM8(0x0651) -#define PORTC_PIN2CTRL _SFR_MEM8(0x0652) -#define PORTC_PIN3CTRL _SFR_MEM8(0x0653) -#define PORTC_PIN4CTRL _SFR_MEM8(0x0654) -#define PORTC_PIN5CTRL _SFR_MEM8(0x0655) -#define PORTC_PIN6CTRL _SFR_MEM8(0x0656) -#define PORTC_PIN7CTRL _SFR_MEM8(0x0657) - -/* PORT - I/O Ports */ -#define PORTD_DIR _SFR_MEM8(0x0660) -#define PORTD_DIRSET _SFR_MEM8(0x0661) -#define PORTD_DIRCLR _SFR_MEM8(0x0662) -#define PORTD_DIRTGL _SFR_MEM8(0x0663) -#define PORTD_OUT _SFR_MEM8(0x0664) -#define PORTD_OUTSET _SFR_MEM8(0x0665) -#define PORTD_OUTCLR _SFR_MEM8(0x0666) -#define PORTD_OUTTGL _SFR_MEM8(0x0667) -#define PORTD_IN _SFR_MEM8(0x0668) -#define PORTD_INTCTRL _SFR_MEM8(0x0669) -#define PORTD_INT0MASK _SFR_MEM8(0x066A) -#define PORTD_INT1MASK _SFR_MEM8(0x066B) -#define PORTD_INTFLAGS _SFR_MEM8(0x066C) -#define PORTD_REMAP _SFR_MEM8(0x066E) -#define PORTD_PIN0CTRL _SFR_MEM8(0x0670) -#define PORTD_PIN1CTRL _SFR_MEM8(0x0671) -#define PORTD_PIN2CTRL _SFR_MEM8(0x0672) -#define PORTD_PIN3CTRL _SFR_MEM8(0x0673) -#define PORTD_PIN4CTRL _SFR_MEM8(0x0674) -#define PORTD_PIN5CTRL _SFR_MEM8(0x0675) -#define PORTD_PIN6CTRL _SFR_MEM8(0x0676) -#define PORTD_PIN7CTRL _SFR_MEM8(0x0677) - -/* PORT - I/O Ports */ -#define PORTE_DIR _SFR_MEM8(0x0680) -#define PORTE_DIRSET _SFR_MEM8(0x0681) -#define PORTE_DIRCLR _SFR_MEM8(0x0682) -#define PORTE_DIRTGL _SFR_MEM8(0x0683) -#define PORTE_OUT _SFR_MEM8(0x0684) -#define PORTE_OUTSET _SFR_MEM8(0x0685) -#define PORTE_OUTCLR _SFR_MEM8(0x0686) -#define PORTE_OUTTGL _SFR_MEM8(0x0687) -#define PORTE_IN _SFR_MEM8(0x0688) -#define PORTE_INTCTRL _SFR_MEM8(0x0689) -#define PORTE_INT0MASK _SFR_MEM8(0x068A) -#define PORTE_INT1MASK _SFR_MEM8(0x068B) -#define PORTE_INTFLAGS _SFR_MEM8(0x068C) -#define PORTE_REMAP _SFR_MEM8(0x068E) -#define PORTE_PIN0CTRL _SFR_MEM8(0x0690) -#define PORTE_PIN1CTRL _SFR_MEM8(0x0691) -#define PORTE_PIN2CTRL _SFR_MEM8(0x0692) -#define PORTE_PIN3CTRL _SFR_MEM8(0x0693) -#define PORTE_PIN4CTRL _SFR_MEM8(0x0694) -#define PORTE_PIN5CTRL _SFR_MEM8(0x0695) -#define PORTE_PIN6CTRL _SFR_MEM8(0x0696) -#define PORTE_PIN7CTRL _SFR_MEM8(0x0697) - -/* PORT - I/O Ports */ -#define PORTF_DIR _SFR_MEM8(0x06A0) -#define PORTF_DIRSET _SFR_MEM8(0x06A1) -#define PORTF_DIRCLR _SFR_MEM8(0x06A2) -#define PORTF_DIRTGL _SFR_MEM8(0x06A3) -#define PORTF_OUT _SFR_MEM8(0x06A4) -#define PORTF_OUTSET _SFR_MEM8(0x06A5) -#define PORTF_OUTCLR _SFR_MEM8(0x06A6) -#define PORTF_OUTTGL _SFR_MEM8(0x06A7) -#define PORTF_IN _SFR_MEM8(0x06A8) -#define PORTF_INTCTRL _SFR_MEM8(0x06A9) -#define PORTF_INT0MASK _SFR_MEM8(0x06AA) -#define PORTF_INT1MASK _SFR_MEM8(0x06AB) -#define PORTF_INTFLAGS _SFR_MEM8(0x06AC) -#define PORTF_REMAP _SFR_MEM8(0x06AE) -#define PORTF_PIN0CTRL _SFR_MEM8(0x06B0) -#define PORTF_PIN1CTRL _SFR_MEM8(0x06B1) -#define PORTF_PIN2CTRL _SFR_MEM8(0x06B2) -#define PORTF_PIN3CTRL _SFR_MEM8(0x06B3) -#define PORTF_PIN4CTRL _SFR_MEM8(0x06B4) -#define PORTF_PIN5CTRL _SFR_MEM8(0x06B5) -#define PORTF_PIN6CTRL _SFR_MEM8(0x06B6) -#define PORTF_PIN7CTRL _SFR_MEM8(0x06B7) - -/* PORT - I/O Ports */ -#define PORTR_DIR _SFR_MEM8(0x07E0) -#define PORTR_DIRSET _SFR_MEM8(0x07E1) -#define PORTR_DIRCLR _SFR_MEM8(0x07E2) -#define PORTR_DIRTGL _SFR_MEM8(0x07E3) -#define PORTR_OUT _SFR_MEM8(0x07E4) -#define PORTR_OUTSET _SFR_MEM8(0x07E5) -#define PORTR_OUTCLR _SFR_MEM8(0x07E6) -#define PORTR_OUTTGL _SFR_MEM8(0x07E7) -#define PORTR_IN _SFR_MEM8(0x07E8) -#define PORTR_INTCTRL _SFR_MEM8(0x07E9) -#define PORTR_INT0MASK _SFR_MEM8(0x07EA) -#define PORTR_INT1MASK _SFR_MEM8(0x07EB) -#define PORTR_INTFLAGS _SFR_MEM8(0x07EC) -#define PORTR_REMAP _SFR_MEM8(0x07EE) -#define PORTR_PIN0CTRL _SFR_MEM8(0x07F0) -#define PORTR_PIN1CTRL _SFR_MEM8(0x07F1) -#define PORTR_PIN2CTRL _SFR_MEM8(0x07F2) -#define PORTR_PIN3CTRL _SFR_MEM8(0x07F3) -#define PORTR_PIN4CTRL _SFR_MEM8(0x07F4) -#define PORTR_PIN5CTRL _SFR_MEM8(0x07F5) -#define PORTR_PIN6CTRL _SFR_MEM8(0x07F6) -#define PORTR_PIN7CTRL _SFR_MEM8(0x07F7) - -/* TC0 - 16-bit Timer/Counter 0 */ -#define TCC0_CTRLA _SFR_MEM8(0x0800) -#define TCC0_CTRLB _SFR_MEM8(0x0801) -#define TCC0_CTRLC _SFR_MEM8(0x0802) -#define TCC0_CTRLD _SFR_MEM8(0x0803) -#define TCC0_CTRLE _SFR_MEM8(0x0804) -#define TCC0_INTCTRLA _SFR_MEM8(0x0806) -#define TCC0_INTCTRLB _SFR_MEM8(0x0807) -#define TCC0_CTRLFCLR _SFR_MEM8(0x0808) -#define TCC0_CTRLFSET _SFR_MEM8(0x0809) -#define TCC0_CTRLGCLR _SFR_MEM8(0x080A) -#define TCC0_CTRLGSET _SFR_MEM8(0x080B) -#define TCC0_INTFLAGS _SFR_MEM8(0x080C) -#define TCC0_TEMP _SFR_MEM8(0x080F) -#define TCC0_CNT _SFR_MEM16(0x0820) -#define TCC0_PER _SFR_MEM16(0x0826) -#define TCC0_CCA _SFR_MEM16(0x0828) -#define TCC0_CCB _SFR_MEM16(0x082A) -#define TCC0_CCC _SFR_MEM16(0x082C) -#define TCC0_CCD _SFR_MEM16(0x082E) -#define TCC0_PERBUF _SFR_MEM16(0x0836) -#define TCC0_CCABUF _SFR_MEM16(0x0838) -#define TCC0_CCBBUF _SFR_MEM16(0x083A) -#define TCC0_CCCBUF _SFR_MEM16(0x083C) -#define TCC0_CCDBUF _SFR_MEM16(0x083E) - -/* TC2 - 16-bit Timer/Counter type 2 */ -#define TCC2_CTRLA _SFR_MEM8(0x0800) -#define TCC2_CTRLB _SFR_MEM8(0x0801) -#define TCC2_CTRLC _SFR_MEM8(0x0802) -#define TCC2_CTRLE _SFR_MEM8(0x0804) -#define TCC2_INTCTRLA _SFR_MEM8(0x0806) -#define TCC2_INTCTRLB _SFR_MEM8(0x0807) -#define TCC2_CTRLF _SFR_MEM8(0x0809) -#define TCC2_INTFLAGS _SFR_MEM8(0x080C) -#define TCC2_LCNT _SFR_MEM8(0x0820) -#define TCC2_HCNT _SFR_MEM8(0x0821) -#define TCC2_LPER _SFR_MEM8(0x0826) -#define TCC2_HPER _SFR_MEM8(0x0827) -#define TCC2_LCMPA _SFR_MEM8(0x0828) -#define TCC2_HCMPA _SFR_MEM8(0x0829) -#define TCC2_LCMPB _SFR_MEM8(0x082A) -#define TCC2_HCMPB _SFR_MEM8(0x082B) -#define TCC2_LCMPC _SFR_MEM8(0x082C) -#define TCC2_HCMPC _SFR_MEM8(0x082D) -#define TCC2_LCMPD _SFR_MEM8(0x082E) -#define TCC2_HCMPD _SFR_MEM8(0x082F) - -/* TC1 - 16-bit Timer/Counter 1 */ -#define TCC1_CTRLA _SFR_MEM8(0x0840) -#define TCC1_CTRLB _SFR_MEM8(0x0841) -#define TCC1_CTRLC _SFR_MEM8(0x0842) -#define TCC1_CTRLD _SFR_MEM8(0x0843) -#define TCC1_CTRLE _SFR_MEM8(0x0844) -#define TCC1_INTCTRLA _SFR_MEM8(0x0846) -#define TCC1_INTCTRLB _SFR_MEM8(0x0847) -#define TCC1_CTRLFCLR _SFR_MEM8(0x0848) -#define TCC1_CTRLFSET _SFR_MEM8(0x0849) -#define TCC1_CTRLGCLR _SFR_MEM8(0x084A) -#define TCC1_CTRLGSET _SFR_MEM8(0x084B) -#define TCC1_INTFLAGS _SFR_MEM8(0x084C) -#define TCC1_TEMP _SFR_MEM8(0x084F) -#define TCC1_CNT _SFR_MEM16(0x0860) -#define TCC1_PER _SFR_MEM16(0x0866) -#define TCC1_CCA _SFR_MEM16(0x0868) -#define TCC1_CCB _SFR_MEM16(0x086A) -#define TCC1_PERBUF _SFR_MEM16(0x0876) -#define TCC1_CCABUF _SFR_MEM16(0x0878) -#define TCC1_CCBBUF _SFR_MEM16(0x087A) - -/* AWEX - Advanced Waveform Extension */ -#define AWEXC_CTRL _SFR_MEM8(0x0880) -#define AWEXC_FDEMASK _SFR_MEM8(0x0882) -#define AWEXC_FDCTRL _SFR_MEM8(0x0883) -#define AWEXC_STATUS _SFR_MEM8(0x0884) -#define AWEXC_STATUSSET _SFR_MEM8(0x0885) -#define AWEXC_DTBOTH _SFR_MEM8(0x0886) -#define AWEXC_DTBOTHBUF _SFR_MEM8(0x0887) -#define AWEXC_DTLS _SFR_MEM8(0x0888) -#define AWEXC_DTHS _SFR_MEM8(0x0889) -#define AWEXC_DTLSBUF _SFR_MEM8(0x088A) -#define AWEXC_DTHSBUF _SFR_MEM8(0x088B) -#define AWEXC_OUTOVEN _SFR_MEM8(0x088C) - -/* HIRES - High-Resolution Extension */ -#define HIRESC_CTRLA _SFR_MEM8(0x0890) - -/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ -#define USARTC0_DATA _SFR_MEM8(0x08A0) -#define USARTC0_STATUS _SFR_MEM8(0x08A1) -#define USARTC0_CTRLA _SFR_MEM8(0x08A3) -#define USARTC0_CTRLB _SFR_MEM8(0x08A4) -#define USARTC0_CTRLC _SFR_MEM8(0x08A5) -#define USARTC0_BAUDCTRLA _SFR_MEM8(0x08A6) -#define USARTC0_BAUDCTRLB _SFR_MEM8(0x08A7) - -/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ -#define USARTC1_DATA _SFR_MEM8(0x08B0) -#define USARTC1_STATUS _SFR_MEM8(0x08B1) -#define USARTC1_CTRLA _SFR_MEM8(0x08B3) -#define USARTC1_CTRLB _SFR_MEM8(0x08B4) -#define USARTC1_CTRLC _SFR_MEM8(0x08B5) -#define USARTC1_BAUDCTRLA _SFR_MEM8(0x08B6) -#define USARTC1_BAUDCTRLB _SFR_MEM8(0x08B7) - -/* SPI - Serial Peripheral Interface */ -#define SPIC_CTRL _SFR_MEM8(0x08C0) -#define SPIC_INTCTRL _SFR_MEM8(0x08C1) -#define SPIC_STATUS _SFR_MEM8(0x08C2) -#define SPIC_DATA _SFR_MEM8(0x08C3) - -/* IRCOM - IR Communication Module */ -#define IRCOM_CTRL _SFR_MEM8(0x08F8) -#define IRCOM_TXPLCTRL _SFR_MEM8(0x08F9) -#define IRCOM_RXPLCTRL _SFR_MEM8(0x08FA) - -/* TC0 - 16-bit Timer/Counter 0 */ -#define TCD0_CTRLA _SFR_MEM8(0x0900) -#define TCD0_CTRLB _SFR_MEM8(0x0901) -#define TCD0_CTRLC _SFR_MEM8(0x0902) -#define TCD0_CTRLD _SFR_MEM8(0x0903) -#define TCD0_CTRLE _SFR_MEM8(0x0904) -#define TCD0_INTCTRLA _SFR_MEM8(0x0906) -#define TCD0_INTCTRLB _SFR_MEM8(0x0907) -#define TCD0_CTRLFCLR _SFR_MEM8(0x0908) -#define TCD0_CTRLFSET _SFR_MEM8(0x0909) -#define TCD0_CTRLGCLR _SFR_MEM8(0x090A) -#define TCD0_CTRLGSET _SFR_MEM8(0x090B) -#define TCD0_INTFLAGS _SFR_MEM8(0x090C) -#define TCD0_TEMP _SFR_MEM8(0x090F) -#define TCD0_CNT _SFR_MEM16(0x0920) -#define TCD0_PER _SFR_MEM16(0x0926) -#define TCD0_CCA _SFR_MEM16(0x0928) -#define TCD0_CCB _SFR_MEM16(0x092A) -#define TCD0_CCC _SFR_MEM16(0x092C) -#define TCD0_CCD _SFR_MEM16(0x092E) -#define TCD0_PERBUF _SFR_MEM16(0x0936) -#define TCD0_CCABUF _SFR_MEM16(0x0938) -#define TCD0_CCBBUF _SFR_MEM16(0x093A) -#define TCD0_CCCBUF _SFR_MEM16(0x093C) -#define TCD0_CCDBUF _SFR_MEM16(0x093E) - -/* TC2 - 16-bit Timer/Counter type 2 */ -#define TCD2_CTRLA _SFR_MEM8(0x0900) -#define TCD2_CTRLB _SFR_MEM8(0x0901) -#define TCD2_CTRLC _SFR_MEM8(0x0902) -#define TCD2_CTRLE _SFR_MEM8(0x0904) -#define TCD2_INTCTRLA _SFR_MEM8(0x0906) -#define TCD2_INTCTRLB _SFR_MEM8(0x0907) -#define TCD2_CTRLF _SFR_MEM8(0x0909) -#define TCD2_INTFLAGS _SFR_MEM8(0x090C) -#define TCD2_LCNT _SFR_MEM8(0x0920) -#define TCD2_HCNT _SFR_MEM8(0x0921) -#define TCD2_LPER _SFR_MEM8(0x0926) -#define TCD2_HPER _SFR_MEM8(0x0927) -#define TCD2_LCMPA _SFR_MEM8(0x0928) -#define TCD2_HCMPA _SFR_MEM8(0x0929) -#define TCD2_LCMPB _SFR_MEM8(0x092A) -#define TCD2_HCMPB _SFR_MEM8(0x092B) -#define TCD2_LCMPC _SFR_MEM8(0x092C) -#define TCD2_HCMPC _SFR_MEM8(0x092D) -#define TCD2_LCMPD _SFR_MEM8(0x092E) -#define TCD2_HCMPD _SFR_MEM8(0x092F) - -/* TC1 - 16-bit Timer/Counter 1 */ -#define TCD1_CTRLA _SFR_MEM8(0x0940) -#define TCD1_CTRLB _SFR_MEM8(0x0941) -#define TCD1_CTRLC _SFR_MEM8(0x0942) -#define TCD1_CTRLD _SFR_MEM8(0x0943) -#define TCD1_CTRLE _SFR_MEM8(0x0944) -#define TCD1_INTCTRLA _SFR_MEM8(0x0946) -#define TCD1_INTCTRLB _SFR_MEM8(0x0947) -#define TCD1_CTRLFCLR _SFR_MEM8(0x0948) -#define TCD1_CTRLFSET _SFR_MEM8(0x0949) -#define TCD1_CTRLGCLR _SFR_MEM8(0x094A) -#define TCD1_CTRLGSET _SFR_MEM8(0x094B) -#define TCD1_INTFLAGS _SFR_MEM8(0x094C) -#define TCD1_TEMP _SFR_MEM8(0x094F) -#define TCD1_CNT _SFR_MEM16(0x0960) -#define TCD1_PER _SFR_MEM16(0x0966) -#define TCD1_CCA _SFR_MEM16(0x0968) -#define TCD1_CCB _SFR_MEM16(0x096A) -#define TCD1_PERBUF _SFR_MEM16(0x0976) -#define TCD1_CCABUF _SFR_MEM16(0x0978) -#define TCD1_CCBBUF _SFR_MEM16(0x097A) - -/* HIRES - High-Resolution Extension */ -#define HIRESD_CTRLA _SFR_MEM8(0x0990) - -/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ -#define USARTD0_DATA _SFR_MEM8(0x09A0) -#define USARTD0_STATUS _SFR_MEM8(0x09A1) -#define USARTD0_CTRLA _SFR_MEM8(0x09A3) -#define USARTD0_CTRLB _SFR_MEM8(0x09A4) -#define USARTD0_CTRLC _SFR_MEM8(0x09A5) -#define USARTD0_BAUDCTRLA _SFR_MEM8(0x09A6) -#define USARTD0_BAUDCTRLB _SFR_MEM8(0x09A7) - -/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ -#define USARTD1_DATA _SFR_MEM8(0x09B0) -#define USARTD1_STATUS _SFR_MEM8(0x09B1) -#define USARTD1_CTRLA _SFR_MEM8(0x09B3) -#define USARTD1_CTRLB _SFR_MEM8(0x09B4) -#define USARTD1_CTRLC _SFR_MEM8(0x09B5) -#define USARTD1_BAUDCTRLA _SFR_MEM8(0x09B6) -#define USARTD1_BAUDCTRLB _SFR_MEM8(0x09B7) - -/* SPI - Serial Peripheral Interface */ -#define SPID_CTRL _SFR_MEM8(0x09C0) -#define SPID_INTCTRL _SFR_MEM8(0x09C1) -#define SPID_STATUS _SFR_MEM8(0x09C2) -#define SPID_DATA _SFR_MEM8(0x09C3) - -/* TC0 - 16-bit Timer/Counter 0 */ -#define TCE0_CTRLA _SFR_MEM8(0x0A00) -#define TCE0_CTRLB _SFR_MEM8(0x0A01) -#define TCE0_CTRLC _SFR_MEM8(0x0A02) -#define TCE0_CTRLD _SFR_MEM8(0x0A03) -#define TCE0_CTRLE _SFR_MEM8(0x0A04) -#define TCE0_INTCTRLA _SFR_MEM8(0x0A06) -#define TCE0_INTCTRLB _SFR_MEM8(0x0A07) -#define TCE0_CTRLFCLR _SFR_MEM8(0x0A08) -#define TCE0_CTRLFSET _SFR_MEM8(0x0A09) -#define TCE0_CTRLGCLR _SFR_MEM8(0x0A0A) -#define TCE0_CTRLGSET _SFR_MEM8(0x0A0B) -#define TCE0_INTFLAGS _SFR_MEM8(0x0A0C) -#define TCE0_TEMP _SFR_MEM8(0x0A0F) -#define TCE0_CNT _SFR_MEM16(0x0A20) -#define TCE0_PER _SFR_MEM16(0x0A26) -#define TCE0_CCA _SFR_MEM16(0x0A28) -#define TCE0_CCB _SFR_MEM16(0x0A2A) -#define TCE0_CCC _SFR_MEM16(0x0A2C) -#define TCE0_CCD _SFR_MEM16(0x0A2E) -#define TCE0_PERBUF _SFR_MEM16(0x0A36) -#define TCE0_CCABUF _SFR_MEM16(0x0A38) -#define TCE0_CCBBUF _SFR_MEM16(0x0A3A) -#define TCE0_CCCBUF _SFR_MEM16(0x0A3C) -#define TCE0_CCDBUF _SFR_MEM16(0x0A3E) - -/* TC2 - 16-bit Timer/Counter type 2 */ -#define TCE2_CTRLA _SFR_MEM8(0x0A00) -#define TCE2_CTRLB _SFR_MEM8(0x0A01) -#define TCE2_CTRLC _SFR_MEM8(0x0A02) -#define TCE2_CTRLE _SFR_MEM8(0x0A04) -#define TCE2_INTCTRLA _SFR_MEM8(0x0A06) -#define TCE2_INTCTRLB _SFR_MEM8(0x0A07) -#define TCE2_CTRLF _SFR_MEM8(0x0A09) -#define TCE2_INTFLAGS _SFR_MEM8(0x0A0C) -#define TCE2_LCNT _SFR_MEM8(0x0A20) -#define TCE2_HCNT _SFR_MEM8(0x0A21) -#define TCE2_LPER _SFR_MEM8(0x0A26) -#define TCE2_HPER _SFR_MEM8(0x0A27) -#define TCE2_LCMPA _SFR_MEM8(0x0A28) -#define TCE2_HCMPA _SFR_MEM8(0x0A29) -#define TCE2_LCMPB _SFR_MEM8(0x0A2A) -#define TCE2_HCMPB _SFR_MEM8(0x0A2B) -#define TCE2_LCMPC _SFR_MEM8(0x0A2C) -#define TCE2_HCMPC _SFR_MEM8(0x0A2D) -#define TCE2_LCMPD _SFR_MEM8(0x0A2E) -#define TCE2_HCMPD _SFR_MEM8(0x0A2F) - -/* TC1 - 16-bit Timer/Counter 1 */ -#define TCE1_CTRLA _SFR_MEM8(0x0A40) -#define TCE1_CTRLB _SFR_MEM8(0x0A41) -#define TCE1_CTRLC _SFR_MEM8(0x0A42) -#define TCE1_CTRLD _SFR_MEM8(0x0A43) -#define TCE1_CTRLE _SFR_MEM8(0x0A44) -#define TCE1_INTCTRLA _SFR_MEM8(0x0A46) -#define TCE1_INTCTRLB _SFR_MEM8(0x0A47) -#define TCE1_CTRLFCLR _SFR_MEM8(0x0A48) -#define TCE1_CTRLFSET _SFR_MEM8(0x0A49) -#define TCE1_CTRLGCLR _SFR_MEM8(0x0A4A) -#define TCE1_CTRLGSET _SFR_MEM8(0x0A4B) -#define TCE1_INTFLAGS _SFR_MEM8(0x0A4C) -#define TCE1_TEMP _SFR_MEM8(0x0A4F) -#define TCE1_CNT _SFR_MEM16(0x0A60) -#define TCE1_PER _SFR_MEM16(0x0A66) -#define TCE1_CCA _SFR_MEM16(0x0A68) -#define TCE1_CCB _SFR_MEM16(0x0A6A) -#define TCE1_PERBUF _SFR_MEM16(0x0A76) -#define TCE1_CCABUF _SFR_MEM16(0x0A78) -#define TCE1_CCBBUF _SFR_MEM16(0x0A7A) - -/* AWEX - Advanced Waveform Extension */ -#define AWEXE_CTRL _SFR_MEM8(0x0A80) -#define AWEXE_FDEMASK _SFR_MEM8(0x0A82) -#define AWEXE_FDCTRL _SFR_MEM8(0x0A83) -#define AWEXE_STATUS _SFR_MEM8(0x0A84) -#define AWEXE_STATUSSET _SFR_MEM8(0x0A85) -#define AWEXE_DTBOTH _SFR_MEM8(0x0A86) -#define AWEXE_DTBOTHBUF _SFR_MEM8(0x0A87) -#define AWEXE_DTLS _SFR_MEM8(0x0A88) -#define AWEXE_DTHS _SFR_MEM8(0x0A89) -#define AWEXE_DTLSBUF _SFR_MEM8(0x0A8A) -#define AWEXE_DTHSBUF _SFR_MEM8(0x0A8B) -#define AWEXE_OUTOVEN _SFR_MEM8(0x0A8C) - -/* HIRES - High-Resolution Extension */ -#define HIRESE_CTRLA _SFR_MEM8(0x0A90) - -/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ -#define USARTE0_DATA _SFR_MEM8(0x0AA0) -#define USARTE0_STATUS _SFR_MEM8(0x0AA1) -#define USARTE0_CTRLA _SFR_MEM8(0x0AA3) -#define USARTE0_CTRLB _SFR_MEM8(0x0AA4) -#define USARTE0_CTRLC _SFR_MEM8(0x0AA5) -#define USARTE0_BAUDCTRLA _SFR_MEM8(0x0AA6) -#define USARTE0_BAUDCTRLB _SFR_MEM8(0x0AA7) - -/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ -#define USARTE1_DATA _SFR_MEM8(0x0AB0) -#define USARTE1_STATUS _SFR_MEM8(0x0AB1) -#define USARTE1_CTRLA _SFR_MEM8(0x0AB3) -#define USARTE1_CTRLB _SFR_MEM8(0x0AB4) -#define USARTE1_CTRLC _SFR_MEM8(0x0AB5) -#define USARTE1_BAUDCTRLA _SFR_MEM8(0x0AB6) -#define USARTE1_BAUDCTRLB _SFR_MEM8(0x0AB7) - -/* SPI - Serial Peripheral Interface */ -#define SPIE_CTRL _SFR_MEM8(0x0AC0) -#define SPIE_INTCTRL _SFR_MEM8(0x0AC1) -#define SPIE_STATUS _SFR_MEM8(0x0AC2) -#define SPIE_DATA _SFR_MEM8(0x0AC3) - -/* TC0 - 16-bit Timer/Counter 0 */ -#define TCF0_CTRLA _SFR_MEM8(0x0B00) -#define TCF0_CTRLB _SFR_MEM8(0x0B01) -#define TCF0_CTRLC _SFR_MEM8(0x0B02) -#define TCF0_CTRLD _SFR_MEM8(0x0B03) -#define TCF0_CTRLE _SFR_MEM8(0x0B04) -#define TCF0_INTCTRLA _SFR_MEM8(0x0B06) -#define TCF0_INTCTRLB _SFR_MEM8(0x0B07) -#define TCF0_CTRLFCLR _SFR_MEM8(0x0B08) -#define TCF0_CTRLFSET _SFR_MEM8(0x0B09) -#define TCF0_CTRLGCLR _SFR_MEM8(0x0B0A) -#define TCF0_CTRLGSET _SFR_MEM8(0x0B0B) -#define TCF0_INTFLAGS _SFR_MEM8(0x0B0C) -#define TCF0_TEMP _SFR_MEM8(0x0B0F) -#define TCF0_CNT _SFR_MEM16(0x0B20) -#define TCF0_PER _SFR_MEM16(0x0B26) -#define TCF0_CCA _SFR_MEM16(0x0B28) -#define TCF0_CCB _SFR_MEM16(0x0B2A) -#define TCF0_CCC _SFR_MEM16(0x0B2C) -#define TCF0_CCD _SFR_MEM16(0x0B2E) -#define TCF0_PERBUF _SFR_MEM16(0x0B36) -#define TCF0_CCABUF _SFR_MEM16(0x0B38) -#define TCF0_CCBBUF _SFR_MEM16(0x0B3A) -#define TCF0_CCCBUF _SFR_MEM16(0x0B3C) -#define TCF0_CCDBUF _SFR_MEM16(0x0B3E) - -/* TC2 - 16-bit Timer/Counter type 2 */ -#define TCF2_CTRLA _SFR_MEM8(0x0B00) -#define TCF2_CTRLB _SFR_MEM8(0x0B01) -#define TCF2_CTRLC _SFR_MEM8(0x0B02) -#define TCF2_CTRLE _SFR_MEM8(0x0B04) -#define TCF2_INTCTRLA _SFR_MEM8(0x0B06) -#define TCF2_INTCTRLB _SFR_MEM8(0x0B07) -#define TCF2_CTRLF _SFR_MEM8(0x0B09) -#define TCF2_INTFLAGS _SFR_MEM8(0x0B0C) -#define TCF2_LCNT _SFR_MEM8(0x0B20) -#define TCF2_HCNT _SFR_MEM8(0x0B21) -#define TCF2_LPER _SFR_MEM8(0x0B26) -#define TCF2_HPER _SFR_MEM8(0x0B27) -#define TCF2_LCMPA _SFR_MEM8(0x0B28) -#define TCF2_HCMPA _SFR_MEM8(0x0B29) -#define TCF2_LCMPB _SFR_MEM8(0x0B2A) -#define TCF2_HCMPB _SFR_MEM8(0x0B2B) -#define TCF2_LCMPC _SFR_MEM8(0x0B2C) -#define TCF2_HCMPC _SFR_MEM8(0x0B2D) -#define TCF2_LCMPD _SFR_MEM8(0x0B2E) -#define TCF2_HCMPD _SFR_MEM8(0x0B2F) - -/* HIRES - High-Resolution Extension */ -#define HIRESF_CTRLA _SFR_MEM8(0x0B90) - -/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ -#define USARTF0_DATA _SFR_MEM8(0x0BA0) -#define USARTF0_STATUS _SFR_MEM8(0x0BA1) -#define USARTF0_CTRLA _SFR_MEM8(0x0BA3) -#define USARTF0_CTRLB _SFR_MEM8(0x0BA4) -#define USARTF0_CTRLC _SFR_MEM8(0x0BA5) -#define USARTF0_BAUDCTRLA _SFR_MEM8(0x0BA6) -#define USARTF0_BAUDCTRLB _SFR_MEM8(0x0BA7) - - - -/*================== Bitfield Definitions ================== */ - -/* VPORT - Virtual Ports */ -/* VPORT.INTFLAGS bit masks and bit positions */ -#define VPORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ -#define VPORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ - -#define VPORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ -#define VPORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ - -/* XOCD - On-Chip Debug System */ -/* OCD.OCDR0 bit masks and bit positions */ -#define OCD_OCDRD_gm 0xFF /* OCDR Dirty group mask. */ -#define OCD_OCDRD_gp 0 /* OCDR Dirty group position. */ -#define OCD_OCDRD0_bm (1<<0) /* OCDR Dirty bit 0 mask. */ -#define OCD_OCDRD0_bp 0 /* OCDR Dirty bit 0 position. */ -#define OCD_OCDRD1_bm (1<<1) /* OCDR Dirty bit 1 mask. */ -#define OCD_OCDRD1_bp 1 /* OCDR Dirty bit 1 position. */ -#define OCD_OCDRD2_bm (1<<2) /* OCDR Dirty bit 2 mask. */ -#define OCD_OCDRD2_bp 2 /* OCDR Dirty bit 2 position. */ -#define OCD_OCDRD3_bm (1<<3) /* OCDR Dirty bit 3 mask. */ -#define OCD_OCDRD3_bp 3 /* OCDR Dirty bit 3 position. */ -#define OCD_OCDRD4_bm (1<<4) /* OCDR Dirty bit 4 mask. */ -#define OCD_OCDRD4_bp 4 /* OCDR Dirty bit 4 position. */ -#define OCD_OCDRD5_bm (1<<5) /* OCDR Dirty bit 5 mask. */ -#define OCD_OCDRD5_bp 5 /* OCDR Dirty bit 5 position. */ -#define OCD_OCDRD6_bm (1<<6) /* OCDR Dirty bit 6 mask. */ -#define OCD_OCDRD6_bp 6 /* OCDR Dirty bit 6 position. */ -#define OCD_OCDRD7_bm (1<<7) /* OCDR Dirty bit 7 mask. */ -#define OCD_OCDRD7_bp 7 /* OCDR Dirty bit 7 position. */ - -/* OCD.OCDR1 bit masks and bit positions */ -/* OCD_OCDRD Predefined. */ -/* OCD_OCDRD Predefined. */ - -/* CPU - CPU */ -/* CPU.CCP bit masks and bit positions */ -#define CPU_CCP_gm 0xFF /* CCP signature group mask. */ -#define CPU_CCP_gp 0 /* CCP signature group position. */ -#define CPU_CCP0_bm (1<<0) /* CCP signature bit 0 mask. */ -#define CPU_CCP0_bp 0 /* CCP signature bit 0 position. */ -#define CPU_CCP1_bm (1<<1) /* CCP signature bit 1 mask. */ -#define CPU_CCP1_bp 1 /* CCP signature bit 1 position. */ -#define CPU_CCP2_bm (1<<2) /* CCP signature bit 2 mask. */ -#define CPU_CCP2_bp 2 /* CCP signature bit 2 position. */ -#define CPU_CCP3_bm (1<<3) /* CCP signature bit 3 mask. */ -#define CPU_CCP3_bp 3 /* CCP signature bit 3 position. */ -#define CPU_CCP4_bm (1<<4) /* CCP signature bit 4 mask. */ -#define CPU_CCP4_bp 4 /* CCP signature bit 4 position. */ -#define CPU_CCP5_bm (1<<5) /* CCP signature bit 5 mask. */ -#define CPU_CCP5_bp 5 /* CCP signature bit 5 position. */ -#define CPU_CCP6_bm (1<<6) /* CCP signature bit 6 mask. */ -#define CPU_CCP6_bp 6 /* CCP signature bit 6 position. */ -#define CPU_CCP7_bm (1<<7) /* CCP signature bit 7 mask. */ -#define CPU_CCP7_bp 7 /* CCP signature bit 7 position. */ - -/* CPU.SREG bit masks and bit positions */ -#define CPU_I_bm 0x80 /* Global Interrupt Enable Flag bit mask. */ -#define CPU_I_bp 7 /* Global Interrupt Enable Flag bit position. */ - -#define CPU_T_bm 0x40 /* Transfer Bit bit mask. */ -#define CPU_T_bp 6 /* Transfer Bit bit position. */ - -#define CPU_H_bm 0x20 /* Half Carry Flag bit mask. */ -#define CPU_H_bp 5 /* Half Carry Flag bit position. */ - -#define CPU_S_bm 0x10 /* N Exclusive Or V Flag bit mask. */ -#define CPU_S_bp 4 /* N Exclusive Or V Flag bit position. */ - -#define CPU_V_bm 0x08 /* Two's Complement Overflow Flag bit mask. */ -#define CPU_V_bp 3 /* Two's Complement Overflow Flag bit position. */ - -#define CPU_N_bm 0x04 /* Negative Flag bit mask. */ -#define CPU_N_bp 2 /* Negative Flag bit position. */ - -#define CPU_Z_bm 0x02 /* Zero Flag bit mask. */ -#define CPU_Z_bp 1 /* Zero Flag bit position. */ - -#define CPU_C_bm 0x01 /* Carry Flag bit mask. */ -#define CPU_C_bp 0 /* Carry Flag bit position. */ - -/* CLK - Clock System */ -/* CLK.CTRL bit masks and bit positions */ -#define CLK_SCLKSEL_gm 0x07 /* System Clock Selection group mask. */ -#define CLK_SCLKSEL_gp 0 /* System Clock Selection group position. */ -#define CLK_SCLKSEL0_bm (1<<0) /* System Clock Selection bit 0 mask. */ -#define CLK_SCLKSEL0_bp 0 /* System Clock Selection bit 0 position. */ -#define CLK_SCLKSEL1_bm (1<<1) /* System Clock Selection bit 1 mask. */ -#define CLK_SCLKSEL1_bp 1 /* System Clock Selection bit 1 position. */ -#define CLK_SCLKSEL2_bm (1<<2) /* System Clock Selection bit 2 mask. */ -#define CLK_SCLKSEL2_bp 2 /* System Clock Selection bit 2 position. */ - -/* CLK.PSCTRL bit masks and bit positions */ -#define CLK_PSADIV_gm 0x7C /* Prescaler A Division Factor group mask. */ -#define CLK_PSADIV_gp 2 /* Prescaler A Division Factor group position. */ -#define CLK_PSADIV0_bm (1<<2) /* Prescaler A Division Factor bit 0 mask. */ -#define CLK_PSADIV0_bp 2 /* Prescaler A Division Factor bit 0 position. */ -#define CLK_PSADIV1_bm (1<<3) /* Prescaler A Division Factor bit 1 mask. */ -#define CLK_PSADIV1_bp 3 /* Prescaler A Division Factor bit 1 position. */ -#define CLK_PSADIV2_bm (1<<4) /* Prescaler A Division Factor bit 2 mask. */ -#define CLK_PSADIV2_bp 4 /* Prescaler A Division Factor bit 2 position. */ -#define CLK_PSADIV3_bm (1<<5) /* Prescaler A Division Factor bit 3 mask. */ -#define CLK_PSADIV3_bp 5 /* Prescaler A Division Factor bit 3 position. */ -#define CLK_PSADIV4_bm (1<<6) /* Prescaler A Division Factor bit 4 mask. */ -#define CLK_PSADIV4_bp 6 /* Prescaler A Division Factor bit 4 position. */ - -#define CLK_PSBCDIV_gm 0x03 /* Prescaler B and C Division factor group mask. */ -#define CLK_PSBCDIV_gp 0 /* Prescaler B and C Division factor group position. */ -#define CLK_PSBCDIV0_bm (1<<0) /* Prescaler B and C Division factor bit 0 mask. */ -#define CLK_PSBCDIV0_bp 0 /* Prescaler B and C Division factor bit 0 position. */ -#define CLK_PSBCDIV1_bm (1<<1) /* Prescaler B and C Division factor bit 1 mask. */ -#define CLK_PSBCDIV1_bp 1 /* Prescaler B and C Division factor bit 1 position. */ - -/* CLK.LOCK bit masks and bit positions */ -#define CLK_LOCK_bm 0x01 /* Clock System Lock bit mask. */ -#define CLK_LOCK_bp 0 /* Clock System Lock bit position. */ - -/* CLK.RTCCTRL bit masks and bit positions */ -#define CLK_RTCSRC_gm 0x0E /* Clock Source group mask. */ -#define CLK_RTCSRC_gp 1 /* Clock Source group position. */ -#define CLK_RTCSRC0_bm (1<<1) /* Clock Source bit 0 mask. */ -#define CLK_RTCSRC0_bp 1 /* Clock Source bit 0 position. */ -#define CLK_RTCSRC1_bm (1<<2) /* Clock Source bit 1 mask. */ -#define CLK_RTCSRC1_bp 2 /* Clock Source bit 1 position. */ -#define CLK_RTCSRC2_bm (1<<3) /* Clock Source bit 2 mask. */ -#define CLK_RTCSRC2_bp 3 /* Clock Source bit 2 position. */ - -#define CLK_RTCEN_bm 0x01 /* Clock Source Enable bit mask. */ -#define CLK_RTCEN_bp 0 /* Clock Source Enable bit position. */ - -/* CLK.USBCTRL bit masks and bit positions */ -#define CLK_USBPSDIV_gm 0x38 /* Prescaler Division Factor group mask. */ -#define CLK_USBPSDIV_gp 3 /* Prescaler Division Factor group position. */ -#define CLK_USBPSDIV0_bm (1<<3) /* Prescaler Division Factor bit 0 mask. */ -#define CLK_USBPSDIV0_bp 3 /* Prescaler Division Factor bit 0 position. */ -#define CLK_USBPSDIV1_bm (1<<4) /* Prescaler Division Factor bit 1 mask. */ -#define CLK_USBPSDIV1_bp 4 /* Prescaler Division Factor bit 1 position. */ -#define CLK_USBPSDIV2_bm (1<<5) /* Prescaler Division Factor bit 2 mask. */ -#define CLK_USBPSDIV2_bp 5 /* Prescaler Division Factor bit 2 position. */ - -#define CLK_USBSRC_gm 0x06 /* Clock Source group mask. */ -#define CLK_USBSRC_gp 1 /* Clock Source group position. */ -#define CLK_USBSRC0_bm (1<<1) /* Clock Source bit 0 mask. */ -#define CLK_USBSRC0_bp 1 /* Clock Source bit 0 position. */ -#define CLK_USBSRC1_bm (1<<2) /* Clock Source bit 1 mask. */ -#define CLK_USBSRC1_bp 2 /* Clock Source bit 1 position. */ - -#define CLK_USBSEN_bm 0x01 /* Clock Source Enable bit mask. */ -#define CLK_USBSEN_bp 0 /* Clock Source Enable bit position. */ - -/* PR.PRGEN bit masks and bit positions */ -#define PR_USB_bm 0x40 /* USB bit mask. */ -#define PR_USB_bp 6 /* USB bit position. */ - -#define PR_AES_bm 0x10 /* AES bit mask. */ -#define PR_AES_bp 4 /* AES bit position. */ - -#define PR_EBI_bm 0x08 /* External Bus Interface bit mask. */ -#define PR_EBI_bp 3 /* External Bus Interface bit position. */ - -#define PR_RTC_bm 0x04 /* Real-time Counter bit mask. */ -#define PR_RTC_bp 2 /* Real-time Counter bit position. */ - -#define PR_EVSYS_bm 0x02 /* Event System bit mask. */ -#define PR_EVSYS_bp 1 /* Event System bit position. */ - -#define PR_DMA_bm 0x01 /* DMA-Controller bit mask. */ -#define PR_DMA_bp 0 /* DMA-Controller bit position. */ - -/* PR.PRPA bit masks and bit positions */ -#define PR_DAC_bm 0x04 /* Port A DAC bit mask. */ -#define PR_DAC_bp 2 /* Port A DAC bit position. */ - -#define PR_ADC_bm 0x02 /* Port A ADC bit mask. */ -#define PR_ADC_bp 1 /* Port A ADC bit position. */ - -#define PR_AC_bm 0x01 /* Port A Analog Comparator bit mask. */ -#define PR_AC_bp 0 /* Port A Analog Comparator bit position. */ - -/* PR.PRPB bit masks and bit positions */ -/* PR_DAC Predefined. */ -/* PR_DAC Predefined. */ - -/* PR_ADC Predefined. */ -/* PR_ADC Predefined. */ - -/* PR_AC Predefined. */ -/* PR_AC Predefined. */ - -/* PR.PRPC bit masks and bit positions */ -#define PR_TWI_bm 0x40 /* Port C Two-wire Interface bit mask. */ -#define PR_TWI_bp 6 /* Port C Two-wire Interface bit position. */ - -#define PR_USART1_bm 0x20 /* Port C USART1 bit mask. */ -#define PR_USART1_bp 5 /* Port C USART1 bit position. */ - -#define PR_USART0_bm 0x10 /* Port C USART0 bit mask. */ -#define PR_USART0_bp 4 /* Port C USART0 bit position. */ - -#define PR_SPI_bm 0x08 /* Port C SPI bit mask. */ -#define PR_SPI_bp 3 /* Port C SPI bit position. */ - -#define PR_HIRES_bm 0x04 /* Port C AWEX bit mask. */ -#define PR_HIRES_bp 2 /* Port C AWEX bit position. */ - -#define PR_TC1_bm 0x02 /* Port C Timer/Counter1 bit mask. */ -#define PR_TC1_bp 1 /* Port C Timer/Counter1 bit position. */ - -#define PR_TC0_bm 0x01 /* Port C Timer/Counter0 bit mask. */ -#define PR_TC0_bp 0 /* Port C Timer/Counter0 bit position. */ - -/* PR.PRPD bit masks and bit positions */ -/* PR_TWI Predefined. */ -/* PR_TWI Predefined. */ - -/* PR_USART1 Predefined. */ -/* PR_USART1 Predefined. */ - -/* PR_USART0 Predefined. */ -/* PR_USART0 Predefined. */ - -/* PR_SPI Predefined. */ -/* PR_SPI Predefined. */ - -/* PR_HIRES Predefined. */ -/* PR_HIRES Predefined. */ - -/* PR_TC1 Predefined. */ -/* PR_TC1 Predefined. */ - -/* PR_TC0 Predefined. */ -/* PR_TC0 Predefined. */ - -/* PR.PRPE bit masks and bit positions */ -/* PR_TWI Predefined. */ -/* PR_TWI Predefined. */ - -/* PR_USART1 Predefined. */ -/* PR_USART1 Predefined. */ - -/* PR_USART0 Predefined. */ -/* PR_USART0 Predefined. */ - -/* PR_SPI Predefined. */ -/* PR_SPI Predefined. */ - -/* PR_HIRES Predefined. */ -/* PR_HIRES Predefined. */ - -/* PR_TC1 Predefined. */ -/* PR_TC1 Predefined. */ - -/* PR_TC0 Predefined. */ -/* PR_TC0 Predefined. */ - -/* PR.PRPF bit masks and bit positions */ -/* PR_TWI Predefined. */ -/* PR_TWI Predefined. */ - -/* PR_USART1 Predefined. */ -/* PR_USART1 Predefined. */ - -/* PR_USART0 Predefined. */ -/* PR_USART0 Predefined. */ - -/* PR_SPI Predefined. */ -/* PR_SPI Predefined. */ - -/* PR_HIRES Predefined. */ -/* PR_HIRES Predefined. */ - -/* PR_TC1 Predefined. */ -/* PR_TC1 Predefined. */ - -/* PR_TC0 Predefined. */ -/* PR_TC0 Predefined. */ - -/* SLEEP - Sleep Controller */ -/* SLEEP.CTRL bit masks and bit positions */ -#define SLEEP_SMODE_gm 0x0E /* Sleep Mode group mask. */ -#define SLEEP_SMODE_gp 1 /* Sleep Mode group position. */ -#define SLEEP_SMODE0_bm (1<<1) /* Sleep Mode bit 0 mask. */ -#define SLEEP_SMODE0_bp 1 /* Sleep Mode bit 0 position. */ -#define SLEEP_SMODE1_bm (1<<2) /* Sleep Mode bit 1 mask. */ -#define SLEEP_SMODE1_bp 2 /* Sleep Mode bit 1 position. */ -#define SLEEP_SMODE2_bm (1<<3) /* Sleep Mode bit 2 mask. */ -#define SLEEP_SMODE2_bp 3 /* Sleep Mode bit 2 position. */ - -#define SLEEP_SEN_bm 0x01 /* Sleep Enable bit mask. */ -#define SLEEP_SEN_bp 0 /* Sleep Enable bit position. */ - -/* OSC - Oscillator */ -/* OSC.CTRL bit masks and bit positions */ -#define OSC_PLLEN_bm 0x10 /* PLL Enable bit mask. */ -#define OSC_PLLEN_bp 4 /* PLL Enable bit position. */ - -#define OSC_XOSCEN_bm 0x08 /* External Oscillator Enable bit mask. */ -#define OSC_XOSCEN_bp 3 /* External Oscillator Enable bit position. */ - -#define OSC_RC32KEN_bm 0x04 /* Internal 32.768 kHz RC Oscillator Enable bit mask. */ -#define OSC_RC32KEN_bp 2 /* Internal 32.768 kHz RC Oscillator Enable bit position. */ - -#define OSC_RC32MEN_bm 0x02 /* Internal 32 MHz RC Oscillator Enable bit mask. */ -#define OSC_RC32MEN_bp 1 /* Internal 32 MHz RC Oscillator Enable bit position. */ - -#define OSC_RC2MEN_bm 0x01 /* Internal 2 MHz RC Oscillator Enable bit mask. */ -#define OSC_RC2MEN_bp 0 /* Internal 2 MHz RC Oscillator Enable bit position. */ - -/* OSC.STATUS bit masks and bit positions */ -#define OSC_PLLRDY_bm 0x10 /* PLL Ready bit mask. */ -#define OSC_PLLRDY_bp 4 /* PLL Ready bit position. */ - -#define OSC_XOSCRDY_bm 0x08 /* External Oscillator Ready bit mask. */ -#define OSC_XOSCRDY_bp 3 /* External Oscillator Ready bit position. */ - -#define OSC_RC32KRDY_bm 0x04 /* Internal 32.768 kHz RC Oscillator Ready bit mask. */ -#define OSC_RC32KRDY_bp 2 /* Internal 32.768 kHz RC Oscillator Ready bit position. */ - -#define OSC_RC32MRDY_bm 0x02 /* Internal 32 MHz RC Oscillator Ready bit mask. */ -#define OSC_RC32MRDY_bp 1 /* Internal 32 MHz RC Oscillator Ready bit position. */ - -#define OSC_RC2MRDY_bm 0x01 /* Internal 2 MHz RC Oscillator Ready bit mask. */ -#define OSC_RC2MRDY_bp 0 /* Internal 2 MHz RC Oscillator Ready bit position. */ - -/* OSC.XOSCCTRL bit masks and bit positions */ -#define OSC_FRQRANGE_gm 0xC0 /* Frequency Range group mask. */ -#define OSC_FRQRANGE_gp 6 /* Frequency Range group position. */ -#define OSC_FRQRANGE0_bm (1<<6) /* Frequency Range bit 0 mask. */ -#define OSC_FRQRANGE0_bp 6 /* Frequency Range bit 0 position. */ -#define OSC_FRQRANGE1_bm (1<<7) /* Frequency Range bit 1 mask. */ -#define OSC_FRQRANGE1_bp 7 /* Frequency Range bit 1 position. */ - -#define OSC_X32KLPM_bm 0x20 /* 32.768 kHz XTAL OSC Low-power Mode bit mask. */ -#define OSC_X32KLPM_bp 5 /* 32.768 kHz XTAL OSC Low-power Mode bit position. */ - -#define OSC_XOSCPWR_bm 0x10 /* 16 MHz Crystal Oscillator High Power mode bit mask. */ -#define OSC_XOSCPWR_bp 4 /* 16 MHz Crystal Oscillator High Power mode bit position. */ - -#define OSC_XOSCSEL_gm 0x0F /* External Oscillator Selection and Startup Time group mask. */ -#define OSC_XOSCSEL_gp 0 /* External Oscillator Selection and Startup Time group position. */ -#define OSC_XOSCSEL0_bm (1<<0) /* External Oscillator Selection and Startup Time bit 0 mask. */ -#define OSC_XOSCSEL0_bp 0 /* External Oscillator Selection and Startup Time bit 0 position. */ -#define OSC_XOSCSEL1_bm (1<<1) /* External Oscillator Selection and Startup Time bit 1 mask. */ -#define OSC_XOSCSEL1_bp 1 /* External Oscillator Selection and Startup Time bit 1 position. */ -#define OSC_XOSCSEL2_bm (1<<2) /* External Oscillator Selection and Startup Time bit 2 mask. */ -#define OSC_XOSCSEL2_bp 2 /* External Oscillator Selection and Startup Time bit 2 position. */ -#define OSC_XOSCSEL3_bm (1<<3) /* External Oscillator Selection and Startup Time bit 3 mask. */ -#define OSC_XOSCSEL3_bp 3 /* External Oscillator Selection and Startup Time bit 3 position. */ - -/* OSC.XOSCFAIL bit masks and bit positions */ -#define OSC_PLLFDIF_bm 0x08 /* PLL Failure Detection Interrupt Flag bit mask. */ -#define OSC_PLLFDIF_bp 3 /* PLL Failure Detection Interrupt Flag bit position. */ - -#define OSC_PLLFDEN_bm 0x04 /* PLL Failure Detection Enable bit mask. */ -#define OSC_PLLFDEN_bp 2 /* PLL Failure Detection Enable bit position. */ - -#define OSC_XOSCFDIF_bm 0x02 /* XOSC Failure Detection Interrupt Flag bit mask. */ -#define OSC_XOSCFDIF_bp 1 /* XOSC Failure Detection Interrupt Flag bit position. */ - -#define OSC_XOSCFDEN_bm 0x01 /* XOSC Failure Detection Enable bit mask. */ -#define OSC_XOSCFDEN_bp 0 /* XOSC Failure Detection Enable bit position. */ - -/* OSC.PLLCTRL bit masks and bit positions */ -#define OSC_PLLSRC_gm 0xC0 /* Clock Source group mask. */ -#define OSC_PLLSRC_gp 6 /* Clock Source group position. */ -#define OSC_PLLSRC0_bm (1<<6) /* Clock Source bit 0 mask. */ -#define OSC_PLLSRC0_bp 6 /* Clock Source bit 0 position. */ -#define OSC_PLLSRC1_bm (1<<7) /* Clock Source bit 1 mask. */ -#define OSC_PLLSRC1_bp 7 /* Clock Source bit 1 position. */ - -#define OSC_PLLDIV_bm 0x20 /* Divide by 2 bit mask. */ -#define OSC_PLLDIV_bp 5 /* Divide by 2 bit position. */ - -#define OSC_PLLFAC_gm 0x1F /* Multiplication Factor group mask. */ -#define OSC_PLLFAC_gp 0 /* Multiplication Factor group position. */ -#define OSC_PLLFAC0_bm (1<<0) /* Multiplication Factor bit 0 mask. */ -#define OSC_PLLFAC0_bp 0 /* Multiplication Factor bit 0 position. */ -#define OSC_PLLFAC1_bm (1<<1) /* Multiplication Factor bit 1 mask. */ -#define OSC_PLLFAC1_bp 1 /* Multiplication Factor bit 1 position. */ -#define OSC_PLLFAC2_bm (1<<2) /* Multiplication Factor bit 2 mask. */ -#define OSC_PLLFAC2_bp 2 /* Multiplication Factor bit 2 position. */ -#define OSC_PLLFAC3_bm (1<<3) /* Multiplication Factor bit 3 mask. */ -#define OSC_PLLFAC3_bp 3 /* Multiplication Factor bit 3 position. */ -#define OSC_PLLFAC4_bm (1<<4) /* Multiplication Factor bit 4 mask. */ -#define OSC_PLLFAC4_bp 4 /* Multiplication Factor bit 4 position. */ - -/* OSC.DFLLCTRL bit masks and bit positions */ -#define OSC_RC32MCREF_gm 0x06 /* 32 MHz DFLL Calibration Reference group mask. */ -#define OSC_RC32MCREF_gp 1 /* 32 MHz DFLL Calibration Reference group position. */ -#define OSC_RC32MCREF0_bm (1<<1) /* 32 MHz DFLL Calibration Reference bit 0 mask. */ -#define OSC_RC32MCREF0_bp 1 /* 32 MHz DFLL Calibration Reference bit 0 position. */ -#define OSC_RC32MCREF1_bm (1<<2) /* 32 MHz DFLL Calibration Reference bit 1 mask. */ -#define OSC_RC32MCREF1_bp 2 /* 32 MHz DFLL Calibration Reference bit 1 position. */ - -#define OSC_RC2MCREF_bm 0x01 /* 2 MHz DFLL Calibration Reference bit mask. */ -#define OSC_RC2MCREF_bp 0 /* 2 MHz DFLL Calibration Reference bit position. */ - -/* DFLL - DFLL */ -/* DFLL.CTRL bit masks and bit positions */ -#define DFLL_ENABLE_bm 0x01 /* DFLL Enable bit mask. */ -#define DFLL_ENABLE_bp 0 /* DFLL Enable bit position. */ - -/* DFLL.CALA bit masks and bit positions */ -#define DFLL_CALL_gm 0x7F /* DFLL Calibration Value A group mask. */ -#define DFLL_CALL_gp 0 /* DFLL Calibration Value A group position. */ -#define DFLL_CALL0_bm (1<<0) /* DFLL Calibration Value A bit 0 mask. */ -#define DFLL_CALL0_bp 0 /* DFLL Calibration Value A bit 0 position. */ -#define DFLL_CALL1_bm (1<<1) /* DFLL Calibration Value A bit 1 mask. */ -#define DFLL_CALL1_bp 1 /* DFLL Calibration Value A bit 1 position. */ -#define DFLL_CALL2_bm (1<<2) /* DFLL Calibration Value A bit 2 mask. */ -#define DFLL_CALL2_bp 2 /* DFLL Calibration Value A bit 2 position. */ -#define DFLL_CALL3_bm (1<<3) /* DFLL Calibration Value A bit 3 mask. */ -#define DFLL_CALL3_bp 3 /* DFLL Calibration Value A bit 3 position. */ -#define DFLL_CALL4_bm (1<<4) /* DFLL Calibration Value A bit 4 mask. */ -#define DFLL_CALL4_bp 4 /* DFLL Calibration Value A bit 4 position. */ -#define DFLL_CALL5_bm (1<<5) /* DFLL Calibration Value A bit 5 mask. */ -#define DFLL_CALL5_bp 5 /* DFLL Calibration Value A bit 5 position. */ -#define DFLL_CALL6_bm (1<<6) /* DFLL Calibration Value A bit 6 mask. */ -#define DFLL_CALL6_bp 6 /* DFLL Calibration Value A bit 6 position. */ - -/* DFLL.CALB bit masks and bit positions */ -#define DFLL_CALH_gm 0x3F /* DFLL Calibration Value B group mask. */ -#define DFLL_CALH_gp 0 /* DFLL Calibration Value B group position. */ -#define DFLL_CALH0_bm (1<<0) /* DFLL Calibration Value B bit 0 mask. */ -#define DFLL_CALH0_bp 0 /* DFLL Calibration Value B bit 0 position. */ -#define DFLL_CALH1_bm (1<<1) /* DFLL Calibration Value B bit 1 mask. */ -#define DFLL_CALH1_bp 1 /* DFLL Calibration Value B bit 1 position. */ -#define DFLL_CALH2_bm (1<<2) /* DFLL Calibration Value B bit 2 mask. */ -#define DFLL_CALH2_bp 2 /* DFLL Calibration Value B bit 2 position. */ -#define DFLL_CALH3_bm (1<<3) /* DFLL Calibration Value B bit 3 mask. */ -#define DFLL_CALH3_bp 3 /* DFLL Calibration Value B bit 3 position. */ -#define DFLL_CALH4_bm (1<<4) /* DFLL Calibration Value B bit 4 mask. */ -#define DFLL_CALH4_bp 4 /* DFLL Calibration Value B bit 4 position. */ -#define DFLL_CALH5_bm (1<<5) /* DFLL Calibration Value B bit 5 mask. */ -#define DFLL_CALH5_bp 5 /* DFLL Calibration Value B bit 5 position. */ - -/* RST - Reset */ -/* RST.STATUS bit masks and bit positions */ -#define RST_SDRF_bm 0x40 /* Spike Detection Reset Flag bit mask. */ -#define RST_SDRF_bp 6 /* Spike Detection Reset Flag bit position. */ - -#define RST_SRF_bm 0x20 /* Software Reset Flag bit mask. */ -#define RST_SRF_bp 5 /* Software Reset Flag bit position. */ - -#define RST_PDIRF_bm 0x10 /* Programming and Debug Interface Interface Reset Flag bit mask. */ -#define RST_PDIRF_bp 4 /* Programming and Debug Interface Interface Reset Flag bit position. */ - -#define RST_WDRF_bm 0x08 /* Watchdog Reset Flag bit mask. */ -#define RST_WDRF_bp 3 /* Watchdog Reset Flag bit position. */ - -#define RST_BORF_bm 0x04 /* Brown-out Reset Flag bit mask. */ -#define RST_BORF_bp 2 /* Brown-out Reset Flag bit position. */ - -#define RST_EXTRF_bm 0x02 /* External Reset Flag bit mask. */ -#define RST_EXTRF_bp 1 /* External Reset Flag bit position. */ - -#define RST_PORF_bm 0x01 /* Power-on Reset Flag bit mask. */ -#define RST_PORF_bp 0 /* Power-on Reset Flag bit position. */ - -/* RST.CTRL bit masks and bit positions */ -#define RST_SWRST_bm 0x01 /* Software Reset bit mask. */ -#define RST_SWRST_bp 0 /* Software Reset bit position. */ - -/* WDT - Watch-Dog Timer */ -/* WDT.CTRL bit masks and bit positions */ -#define WDT_PER_gm 0x3C /* Period group mask. */ -#define WDT_PER_gp 2 /* Period group position. */ -#define WDT_PER0_bm (1<<2) /* Period bit 0 mask. */ -#define WDT_PER0_bp 2 /* Period bit 0 position. */ -#define WDT_PER1_bm (1<<3) /* Period bit 1 mask. */ -#define WDT_PER1_bp 3 /* Period bit 1 position. */ -#define WDT_PER2_bm (1<<4) /* Period bit 2 mask. */ -#define WDT_PER2_bp 4 /* Period bit 2 position. */ -#define WDT_PER3_bm (1<<5) /* Period bit 3 mask. */ -#define WDT_PER3_bp 5 /* Period bit 3 position. */ - -#define WDT_ENABLE_bm 0x02 /* Enable bit mask. */ -#define WDT_ENABLE_bp 1 /* Enable bit position. */ - -#define WDT_CEN_bm 0x01 /* Change Enable bit mask. */ -#define WDT_CEN_bp 0 /* Change Enable bit position. */ - -/* WDT.WINCTRL bit masks and bit positions */ -#define WDT_WPER_gm 0x3C /* Windowed Mode Period group mask. */ -#define WDT_WPER_gp 2 /* Windowed Mode Period group position. */ -#define WDT_WPER0_bm (1<<2) /* Windowed Mode Period bit 0 mask. */ -#define WDT_WPER0_bp 2 /* Windowed Mode Period bit 0 position. */ -#define WDT_WPER1_bm (1<<3) /* Windowed Mode Period bit 1 mask. */ -#define WDT_WPER1_bp 3 /* Windowed Mode Period bit 1 position. */ -#define WDT_WPER2_bm (1<<4) /* Windowed Mode Period bit 2 mask. */ -#define WDT_WPER2_bp 4 /* Windowed Mode Period bit 2 position. */ -#define WDT_WPER3_bm (1<<5) /* Windowed Mode Period bit 3 mask. */ -#define WDT_WPER3_bp 5 /* Windowed Mode Period bit 3 position. */ - -#define WDT_WEN_bm 0x02 /* Windowed Mode Enable bit mask. */ -#define WDT_WEN_bp 1 /* Windowed Mode Enable bit position. */ - -#define WDT_WCEN_bm 0x01 /* Windowed Mode Change Enable bit mask. */ -#define WDT_WCEN_bp 0 /* Windowed Mode Change Enable bit position. */ - -/* WDT.STATUS bit masks and bit positions */ -#define WDT_SYNCBUSY_bm 0x01 /* Syncronization busy bit mask. */ -#define WDT_SYNCBUSY_bp 0 /* Syncronization busy bit position. */ - -/* MCU - MCU Control */ -/* MCU.MCUCR bit masks and bit positions */ -#define MCU_JTAGD_bm 0x01 /* JTAG Disable bit mask. */ -#define MCU_JTAGD_bp 0 /* JTAG Disable bit position. */ - -/* MCU.ANAINIT bit masks and bit positions */ -#define MCU_STARTUPDLYB_gm 0x0C /* Analog startup delay Port B group mask. */ -#define MCU_STARTUPDLYB_gp 2 /* Analog startup delay Port B group position. */ -#define MCU_STARTUPDLYB0_bm (1<<2) /* Analog startup delay Port B bit 0 mask. */ -#define MCU_STARTUPDLYB0_bp 2 /* Analog startup delay Port B bit 0 position. */ -#define MCU_STARTUPDLYB1_bm (1<<3) /* Analog startup delay Port B bit 1 mask. */ -#define MCU_STARTUPDLYB1_bp 3 /* Analog startup delay Port B bit 1 position. */ - -#define MCU_STARTUPDLYA_gm 0x03 /* Analog startup delay Port A group mask. */ -#define MCU_STARTUPDLYA_gp 0 /* Analog startup delay Port A group position. */ -#define MCU_STARTUPDLYA0_bm (1<<0) /* Analog startup delay Port A bit 0 mask. */ -#define MCU_STARTUPDLYA0_bp 0 /* Analog startup delay Port A bit 0 position. */ -#define MCU_STARTUPDLYA1_bm (1<<1) /* Analog startup delay Port A bit 1 mask. */ -#define MCU_STARTUPDLYA1_bp 1 /* Analog startup delay Port A bit 1 position. */ - -/* MCU.EVSYSLOCK bit masks and bit positions */ -#define MCU_EVSYS1LOCK_bm 0x10 /* Event Channel 4-7 Lock bit mask. */ -#define MCU_EVSYS1LOCK_bp 4 /* Event Channel 4-7 Lock bit position. */ - -#define MCU_EVSYS0LOCK_bm 0x01 /* Event Channel 0-3 Lock bit mask. */ -#define MCU_EVSYS0LOCK_bp 0 /* Event Channel 0-3 Lock bit position. */ - -/* MCU.AWEXLOCK bit masks and bit positions */ -#define MCU_AWEXFLOCK_bm 0x08 /* AWeX on T/C F0 Lock bit mask. */ -#define MCU_AWEXFLOCK_bp 3 /* AWeX on T/C F0 Lock bit position. */ - -#define MCU_AWEXELOCK_bm 0x04 /* AWeX on T/C E0 Lock bit mask. */ -#define MCU_AWEXELOCK_bp 2 /* AWeX on T/C E0 Lock bit position. */ - -#define MCU_AWEXDLOCK_bm 0x02 /* AWeX on T/C D0 Lock bit mask. */ -#define MCU_AWEXDLOCK_bp 1 /* AWeX on T/C D0 Lock bit position. */ - -#define MCU_AWEXCLOCK_bm 0x01 /* AWeX on T/C C0 Lock bit mask. */ -#define MCU_AWEXCLOCK_bp 0 /* AWeX on T/C C0 Lock bit position. */ - -/* PMIC - Programmable Multi-level Interrupt Controller */ -/* PMIC.STATUS bit masks and bit positions */ -#define PMIC_NMIEX_bm 0x80 /* Non-maskable Interrupt Executing bit mask. */ -#define PMIC_NMIEX_bp 7 /* Non-maskable Interrupt Executing bit position. */ - -#define PMIC_HILVLEX_bm 0x04 /* High Level Interrupt Executing bit mask. */ -#define PMIC_HILVLEX_bp 2 /* High Level Interrupt Executing bit position. */ - -#define PMIC_MEDLVLEX_bm 0x02 /* Medium Level Interrupt Executing bit mask. */ -#define PMIC_MEDLVLEX_bp 1 /* Medium Level Interrupt Executing bit position. */ - -#define PMIC_LOLVLEX_bm 0x01 /* Low Level Interrupt Executing bit mask. */ -#define PMIC_LOLVLEX_bp 0 /* Low Level Interrupt Executing bit position. */ - -/* PMIC.INTPRI bit masks and bit positions */ -#define PMIC_INTPRI_gm 0xFF /* Interrupt Priority group mask. */ -#define PMIC_INTPRI_gp 0 /* Interrupt Priority group position. */ -#define PMIC_INTPRI0_bm (1<<0) /* Interrupt Priority bit 0 mask. */ -#define PMIC_INTPRI0_bp 0 /* Interrupt Priority bit 0 position. */ -#define PMIC_INTPRI1_bm (1<<1) /* Interrupt Priority bit 1 mask. */ -#define PMIC_INTPRI1_bp 1 /* Interrupt Priority bit 1 position. */ -#define PMIC_INTPRI2_bm (1<<2) /* Interrupt Priority bit 2 mask. */ -#define PMIC_INTPRI2_bp 2 /* Interrupt Priority bit 2 position. */ -#define PMIC_INTPRI3_bm (1<<3) /* Interrupt Priority bit 3 mask. */ -#define PMIC_INTPRI3_bp 3 /* Interrupt Priority bit 3 position. */ -#define PMIC_INTPRI4_bm (1<<4) /* Interrupt Priority bit 4 mask. */ -#define PMIC_INTPRI4_bp 4 /* Interrupt Priority bit 4 position. */ -#define PMIC_INTPRI5_bm (1<<5) /* Interrupt Priority bit 5 mask. */ -#define PMIC_INTPRI5_bp 5 /* Interrupt Priority bit 5 position. */ -#define PMIC_INTPRI6_bm (1<<6) /* Interrupt Priority bit 6 mask. */ -#define PMIC_INTPRI6_bp 6 /* Interrupt Priority bit 6 position. */ -#define PMIC_INTPRI7_bm (1<<7) /* Interrupt Priority bit 7 mask. */ -#define PMIC_INTPRI7_bp 7 /* Interrupt Priority bit 7 position. */ - -/* PMIC.CTRL bit masks and bit positions */ -#define PMIC_RREN_bm 0x80 /* Round-Robin Priority Enable bit mask. */ -#define PMIC_RREN_bp 7 /* Round-Robin Priority Enable bit position. */ - -#define PMIC_IVSEL_bm 0x40 /* Interrupt Vector Select bit mask. */ -#define PMIC_IVSEL_bp 6 /* Interrupt Vector Select bit position. */ - -#define PMIC_HILVLEN_bm 0x04 /* High Level Enable bit mask. */ -#define PMIC_HILVLEN_bp 2 /* High Level Enable bit position. */ - -#define PMIC_MEDLVLEN_bm 0x02 /* Medium Level Enable bit mask. */ -#define PMIC_MEDLVLEN_bp 1 /* Medium Level Enable bit position. */ - -#define PMIC_LOLVLEN_bm 0x01 /* Low Level Enable bit mask. */ -#define PMIC_LOLVLEN_bp 0 /* Low Level Enable bit position. */ - -/* PORTCFG - Port Configuration */ -/* PORTCFG.VPCTRLA bit masks and bit positions */ -#define PORTCFG_VP1MAP_gm 0xF0 /* Virtual Port 1 Mapping group mask. */ -#define PORTCFG_VP1MAP_gp 4 /* Virtual Port 1 Mapping group position. */ -#define PORTCFG_VP1MAP0_bm (1<<4) /* Virtual Port 1 Mapping bit 0 mask. */ -#define PORTCFG_VP1MAP0_bp 4 /* Virtual Port 1 Mapping bit 0 position. */ -#define PORTCFG_VP1MAP1_bm (1<<5) /* Virtual Port 1 Mapping bit 1 mask. */ -#define PORTCFG_VP1MAP1_bp 5 /* Virtual Port 1 Mapping bit 1 position. */ -#define PORTCFG_VP1MAP2_bm (1<<6) /* Virtual Port 1 Mapping bit 2 mask. */ -#define PORTCFG_VP1MAP2_bp 6 /* Virtual Port 1 Mapping bit 2 position. */ -#define PORTCFG_VP1MAP3_bm (1<<7) /* Virtual Port 1 Mapping bit 3 mask. */ -#define PORTCFG_VP1MAP3_bp 7 /* Virtual Port 1 Mapping bit 3 position. */ - -#define PORTCFG_VP0MAP_gm 0x0F /* Virtual Port 0 Mapping group mask. */ -#define PORTCFG_VP0MAP_gp 0 /* Virtual Port 0 Mapping group position. */ -#define PORTCFG_VP0MAP0_bm (1<<0) /* Virtual Port 0 Mapping bit 0 mask. */ -#define PORTCFG_VP0MAP0_bp 0 /* Virtual Port 0 Mapping bit 0 position. */ -#define PORTCFG_VP0MAP1_bm (1<<1) /* Virtual Port 0 Mapping bit 1 mask. */ -#define PORTCFG_VP0MAP1_bp 1 /* Virtual Port 0 Mapping bit 1 position. */ -#define PORTCFG_VP0MAP2_bm (1<<2) /* Virtual Port 0 Mapping bit 2 mask. */ -#define PORTCFG_VP0MAP2_bp 2 /* Virtual Port 0 Mapping bit 2 position. */ -#define PORTCFG_VP0MAP3_bm (1<<3) /* Virtual Port 0 Mapping bit 3 mask. */ -#define PORTCFG_VP0MAP3_bp 3 /* Virtual Port 0 Mapping bit 3 position. */ - -/* PORTCFG.VPCTRLB bit masks and bit positions */ -#define PORTCFG_VP3MAP_gm 0xF0 /* Virtual Port 3 Mapping group mask. */ -#define PORTCFG_VP3MAP_gp 4 /* Virtual Port 3 Mapping group position. */ -#define PORTCFG_VP3MAP0_bm (1<<4) /* Virtual Port 3 Mapping bit 0 mask. */ -#define PORTCFG_VP3MAP0_bp 4 /* Virtual Port 3 Mapping bit 0 position. */ -#define PORTCFG_VP3MAP1_bm (1<<5) /* Virtual Port 3 Mapping bit 1 mask. */ -#define PORTCFG_VP3MAP1_bp 5 /* Virtual Port 3 Mapping bit 1 position. */ -#define PORTCFG_VP3MAP2_bm (1<<6) /* Virtual Port 3 Mapping bit 2 mask. */ -#define PORTCFG_VP3MAP2_bp 6 /* Virtual Port 3 Mapping bit 2 position. */ -#define PORTCFG_VP3MAP3_bm (1<<7) /* Virtual Port 3 Mapping bit 3 mask. */ -#define PORTCFG_VP3MAP3_bp 7 /* Virtual Port 3 Mapping bit 3 position. */ - -#define PORTCFG_VP2MAP_gm 0x0F /* Virtual Port 2 Mapping group mask. */ -#define PORTCFG_VP2MAP_gp 0 /* Virtual Port 2 Mapping group position. */ -#define PORTCFG_VP2MAP0_bm (1<<0) /* Virtual Port 2 Mapping bit 0 mask. */ -#define PORTCFG_VP2MAP0_bp 0 /* Virtual Port 2 Mapping bit 0 position. */ -#define PORTCFG_VP2MAP1_bm (1<<1) /* Virtual Port 2 Mapping bit 1 mask. */ -#define PORTCFG_VP2MAP1_bp 1 /* Virtual Port 2 Mapping bit 1 position. */ -#define PORTCFG_VP2MAP2_bm (1<<2) /* Virtual Port 2 Mapping bit 2 mask. */ -#define PORTCFG_VP2MAP2_bp 2 /* Virtual Port 2 Mapping bit 2 position. */ -#define PORTCFG_VP2MAP3_bm (1<<3) /* Virtual Port 2 Mapping bit 3 mask. */ -#define PORTCFG_VP2MAP3_bp 3 /* Virtual Port 2 Mapping bit 3 position. */ - -/* PORTCFG.CLKEVOUT bit masks and bit positions */ -#define PORTCFG_CLKOUT_gm 0x03 /* Peripheral Clock Output Port group mask. */ -#define PORTCFG_CLKOUT_gp 0 /* Peripheral Clock Output Port group position. */ -#define PORTCFG_CLKOUT0_bm (1<<0) /* Peripheral Clock Output Port bit 0 mask. */ -#define PORTCFG_CLKOUT0_bp 0 /* Peripheral Clock Output Port bit 0 position. */ -#define PORTCFG_CLKOUT1_bm (1<<1) /* Peripheral Clock Output Port bit 1 mask. */ -#define PORTCFG_CLKOUT1_bp 1 /* Peripheral Clock Output Port bit 1 position. */ - -#define PORTCFG_CLKOUTSEL_gm 0x0C /* Peripheral Clock Output Select group mask. */ -#define PORTCFG_CLKOUTSEL_gp 2 /* Peripheral Clock Output Select group position. */ -#define PORTCFG_CLKOUTSEL0_bm (1<<2) /* Peripheral Clock Output Select bit 0 mask. */ -#define PORTCFG_CLKOUTSEL0_bp 2 /* Peripheral Clock Output Select bit 0 position. */ -#define PORTCFG_CLKOUTSEL1_bm (1<<3) /* Peripheral Clock Output Select bit 1 mask. */ -#define PORTCFG_CLKOUTSEL1_bp 3 /* Peripheral Clock Output Select bit 1 position. */ - -#define PORTCFG_EVOUT_gm 0x30 /* Event Output Port group mask. */ -#define PORTCFG_EVOUT_gp 4 /* Event Output Port group position. */ -#define PORTCFG_EVOUT0_bm (1<<4) /* Event Output Port bit 0 mask. */ -#define PORTCFG_EVOUT0_bp 4 /* Event Output Port bit 0 position. */ -#define PORTCFG_EVOUT1_bm (1<<5) /* Event Output Port bit 1 mask. */ -#define PORTCFG_EVOUT1_bp 5 /* Event Output Port bit 1 position. */ - -#define PORTCFG_RTCOUT_bm 0x40 /* RTC Clock Output bit mask. */ -#define PORTCFG_RTCOUT_bp 6 /* RTC Clock Output bit position. */ - -#define PORTCFG_CLKEVPIN_bm 0x80 /* Peripheral Clock and Event Output pin Select bit mask. */ -#define PORTCFG_CLKEVPIN_bp 7 /* Peripheral Clock and Event Output pin Select bit position. */ - -/* PORTCFG.EBIOUT bit masks and bit positions */ -#define PORTCFG_EBICSOUT_gm 0x03 /* EBI Chip Select Output group mask. */ -#define PORTCFG_EBICSOUT_gp 0 /* EBI Chip Select Output group position. */ -#define PORTCFG_EBICSOUT0_bm (1<<0) /* EBI Chip Select Output bit 0 mask. */ -#define PORTCFG_EBICSOUT0_bp 0 /* EBI Chip Select Output bit 0 position. */ -#define PORTCFG_EBICSOUT1_bm (1<<1) /* EBI Chip Select Output bit 1 mask. */ -#define PORTCFG_EBICSOUT1_bp 1 /* EBI Chip Select Output bit 1 position. */ - -#define PORTCFG_EBIADROUT_gm 0x0C /* EBI Address Output group mask. */ -#define PORTCFG_EBIADROUT_gp 2 /* EBI Address Output group position. */ -#define PORTCFG_EBIADROUT0_bm (1<<2) /* EBI Address Output bit 0 mask. */ -#define PORTCFG_EBIADROUT0_bp 2 /* EBI Address Output bit 0 position. */ -#define PORTCFG_EBIADROUT1_bm (1<<3) /* EBI Address Output bit 1 mask. */ -#define PORTCFG_EBIADROUT1_bp 3 /* EBI Address Output bit 1 position. */ - -/* PORTCFG.EVOUTSEL bit masks and bit positions */ -#define PORTCFG_EVOUTSEL_gm 0x07 /* Event Output Select group mask. */ -#define PORTCFG_EVOUTSEL_gp 0 /* Event Output Select group position. */ -#define PORTCFG_EVOUTSEL0_bm (1<<0) /* Event Output Select bit 0 mask. */ -#define PORTCFG_EVOUTSEL0_bp 0 /* Event Output Select bit 0 position. */ -#define PORTCFG_EVOUTSEL1_bm (1<<1) /* Event Output Select bit 1 mask. */ -#define PORTCFG_EVOUTSEL1_bp 1 /* Event Output Select bit 1 position. */ -#define PORTCFG_EVOUTSEL2_bm (1<<2) /* Event Output Select bit 2 mask. */ -#define PORTCFG_EVOUTSEL2_bp 2 /* Event Output Select bit 2 position. */ - -/* AES - AES Module */ -/* AES.CTRL bit masks and bit positions */ -#define AES_START_bm 0x80 /* Start/Run bit mask. */ -#define AES_START_bp 7 /* Start/Run bit position. */ - -#define AES_AUTO_bm 0x40 /* Auto Start Trigger bit mask. */ -#define AES_AUTO_bp 6 /* Auto Start Trigger bit position. */ - -#define AES_RESET_bm 0x20 /* AES Software Reset bit mask. */ -#define AES_RESET_bp 5 /* AES Software Reset bit position. */ - -#define AES_DECRYPT_bm 0x10 /* Decryption / Direction bit mask. */ -#define AES_DECRYPT_bp 4 /* Decryption / Direction bit position. */ - -#define AES_XOR_bm 0x04 /* State XOR Load Enable bit mask. */ -#define AES_XOR_bp 2 /* State XOR Load Enable bit position. */ - -/* AES.STATUS bit masks and bit positions */ -#define AES_ERROR_bm 0x80 /* AES Error bit mask. */ -#define AES_ERROR_bp 7 /* AES Error bit position. */ - -#define AES_SRIF_bm 0x01 /* State Ready Interrupt Flag bit mask. */ -#define AES_SRIF_bp 0 /* State Ready Interrupt Flag bit position. */ - -/* AES.INTCTRL bit masks and bit positions */ -#define AES_INTLVL_gm 0x03 /* Interrupt level group mask. */ -#define AES_INTLVL_gp 0 /* Interrupt level group position. */ -#define AES_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */ -#define AES_INTLVL0_bp 0 /* Interrupt level bit 0 position. */ -#define AES_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */ -#define AES_INTLVL1_bp 1 /* Interrupt level bit 1 position. */ - -/* CRC - Cyclic Redundancy Checker */ -/* CRC.CTRL bit masks and bit positions */ -#define CRC_RESET_gm 0xC0 /* Reset group mask. */ -#define CRC_RESET_gp 6 /* Reset group position. */ -#define CRC_RESET0_bm (1<<6) /* Reset bit 0 mask. */ -#define CRC_RESET0_bp 6 /* Reset bit 0 position. */ -#define CRC_RESET1_bm (1<<7) /* Reset bit 1 mask. */ -#define CRC_RESET1_bp 7 /* Reset bit 1 position. */ - -#define CRC_CRC32_bm 0x20 /* CRC Mode bit mask. */ -#define CRC_CRC32_bp 5 /* CRC Mode bit position. */ - -#define CRC_SOURCE_gm 0x0F /* Input Source group mask. */ -#define CRC_SOURCE_gp 0 /* Input Source group position. */ -#define CRC_SOURCE0_bm (1<<0) /* Input Source bit 0 mask. */ -#define CRC_SOURCE0_bp 0 /* Input Source bit 0 position. */ -#define CRC_SOURCE1_bm (1<<1) /* Input Source bit 1 mask. */ -#define CRC_SOURCE1_bp 1 /* Input Source bit 1 position. */ -#define CRC_SOURCE2_bm (1<<2) /* Input Source bit 2 mask. */ -#define CRC_SOURCE2_bp 2 /* Input Source bit 2 position. */ -#define CRC_SOURCE3_bm (1<<3) /* Input Source bit 3 mask. */ -#define CRC_SOURCE3_bp 3 /* Input Source bit 3 position. */ - -/* CRC.STATUS bit masks and bit positions */ -#define CRC_ZERO_bm 0x02 /* Zero detection bit mask. */ -#define CRC_ZERO_bp 1 /* Zero detection bit position. */ - -#define CRC_BUSY_bm 0x01 /* Busy bit mask. */ -#define CRC_BUSY_bp 0 /* Busy bit position. */ - -/* DMA - DMA Controller */ -/* DMA_CH.CTRLA bit masks and bit positions */ -#define DMA_CH_ENABLE_bm 0x80 /* Channel Enable bit mask. */ -#define DMA_CH_ENABLE_bp 7 /* Channel Enable bit position. */ - -#define DMA_CH_RESET_bm 0x40 /* Channel Software Reset bit mask. */ -#define DMA_CH_RESET_bp 6 /* Channel Software Reset bit position. */ - -#define DMA_CH_REPEAT_bm 0x20 /* Channel Repeat Mode bit mask. */ -#define DMA_CH_REPEAT_bp 5 /* Channel Repeat Mode bit position. */ - -#define DMA_CH_TRFREQ_bm 0x10 /* Channel Transfer Request bit mask. */ -#define DMA_CH_TRFREQ_bp 4 /* Channel Transfer Request bit position. */ - -#define DMA_CH_SINGLE_bm 0x04 /* Channel Single Shot Data Transfer bit mask. */ -#define DMA_CH_SINGLE_bp 2 /* Channel Single Shot Data Transfer bit position. */ - -#define DMA_CH_BURSTLEN_gm 0x03 /* Channel Transfer Mode group mask. */ -#define DMA_CH_BURSTLEN_gp 0 /* Channel Transfer Mode group position. */ -#define DMA_CH_BURSTLEN0_bm (1<<0) /* Channel Transfer Mode bit 0 mask. */ -#define DMA_CH_BURSTLEN0_bp 0 /* Channel Transfer Mode bit 0 position. */ -#define DMA_CH_BURSTLEN1_bm (1<<1) /* Channel Transfer Mode bit 1 mask. */ -#define DMA_CH_BURSTLEN1_bp 1 /* Channel Transfer Mode bit 1 position. */ - -/* DMA_CH.CTRLB bit masks and bit positions */ -#define DMA_CH_CHBUSY_bm 0x80 /* Block Transfer Busy bit mask. */ -#define DMA_CH_CHBUSY_bp 7 /* Block Transfer Busy bit position. */ - -#define DMA_CH_CHPEND_bm 0x40 /* Block Transfer Pending bit mask. */ -#define DMA_CH_CHPEND_bp 6 /* Block Transfer Pending bit position. */ - -#define DMA_CH_ERRIF_bm 0x20 /* Block Transfer Error Interrupt Flag bit mask. */ -#define DMA_CH_ERRIF_bp 5 /* Block Transfer Error Interrupt Flag bit position. */ - -#define DMA_CH_TRNIF_bm 0x10 /* Transaction Complete Interrup Flag bit mask. */ -#define DMA_CH_TRNIF_bp 4 /* Transaction Complete Interrup Flag bit position. */ - -#define DMA_CH_ERRINTLVL_gm 0x0C /* Transfer Error Interrupt Level group mask. */ -#define DMA_CH_ERRINTLVL_gp 2 /* Transfer Error Interrupt Level group position. */ -#define DMA_CH_ERRINTLVL0_bm (1<<2) /* Transfer Error Interrupt Level bit 0 mask. */ -#define DMA_CH_ERRINTLVL0_bp 2 /* Transfer Error Interrupt Level bit 0 position. */ -#define DMA_CH_ERRINTLVL1_bm (1<<3) /* Transfer Error Interrupt Level bit 1 mask. */ -#define DMA_CH_ERRINTLVL1_bp 3 /* Transfer Error Interrupt Level bit 1 position. */ - -#define DMA_CH_TRNINTLVL_gm 0x03 /* Transaction Complete Interrupt Level group mask. */ -#define DMA_CH_TRNINTLVL_gp 0 /* Transaction Complete Interrupt Level group position. */ -#define DMA_CH_TRNINTLVL0_bm (1<<0) /* Transaction Complete Interrupt Level bit 0 mask. */ -#define DMA_CH_TRNINTLVL0_bp 0 /* Transaction Complete Interrupt Level bit 0 position. */ -#define DMA_CH_TRNINTLVL1_bm (1<<1) /* Transaction Complete Interrupt Level bit 1 mask. */ -#define DMA_CH_TRNINTLVL1_bp 1 /* Transaction Complete Interrupt Level bit 1 position. */ - -/* DMA_CH.ADDRCTRL bit masks and bit positions */ -#define DMA_CH_SRCRELOAD_gm 0xC0 /* Channel Source Address Reload group mask. */ -#define DMA_CH_SRCRELOAD_gp 6 /* Channel Source Address Reload group position. */ -#define DMA_CH_SRCRELOAD0_bm (1<<6) /* Channel Source Address Reload bit 0 mask. */ -#define DMA_CH_SRCRELOAD0_bp 6 /* Channel Source Address Reload bit 0 position. */ -#define DMA_CH_SRCRELOAD1_bm (1<<7) /* Channel Source Address Reload bit 1 mask. */ -#define DMA_CH_SRCRELOAD1_bp 7 /* Channel Source Address Reload bit 1 position. */ - -#define DMA_CH_SRCDIR_gm 0x30 /* Channel Source Address Mode group mask. */ -#define DMA_CH_SRCDIR_gp 4 /* Channel Source Address Mode group position. */ -#define DMA_CH_SRCDIR0_bm (1<<4) /* Channel Source Address Mode bit 0 mask. */ -#define DMA_CH_SRCDIR0_bp 4 /* Channel Source Address Mode bit 0 position. */ -#define DMA_CH_SRCDIR1_bm (1<<5) /* Channel Source Address Mode bit 1 mask. */ -#define DMA_CH_SRCDIR1_bp 5 /* Channel Source Address Mode bit 1 position. */ - -#define DMA_CH_DESTRELOAD_gm 0x0C /* Channel Destination Address Reload group mask. */ -#define DMA_CH_DESTRELOAD_gp 2 /* Channel Destination Address Reload group position. */ -#define DMA_CH_DESTRELOAD0_bm (1<<2) /* Channel Destination Address Reload bit 0 mask. */ -#define DMA_CH_DESTRELOAD0_bp 2 /* Channel Destination Address Reload bit 0 position. */ -#define DMA_CH_DESTRELOAD1_bm (1<<3) /* Channel Destination Address Reload bit 1 mask. */ -#define DMA_CH_DESTRELOAD1_bp 3 /* Channel Destination Address Reload bit 1 position. */ - -#define DMA_CH_DESTDIR_gm 0x03 /* Channel Destination Address Mode group mask. */ -#define DMA_CH_DESTDIR_gp 0 /* Channel Destination Address Mode group position. */ -#define DMA_CH_DESTDIR0_bm (1<<0) /* Channel Destination Address Mode bit 0 mask. */ -#define DMA_CH_DESTDIR0_bp 0 /* Channel Destination Address Mode bit 0 position. */ -#define DMA_CH_DESTDIR1_bm (1<<1) /* Channel Destination Address Mode bit 1 mask. */ -#define DMA_CH_DESTDIR1_bp 1 /* Channel Destination Address Mode bit 1 position. */ - -/* DMA_CH.TRIGSRC bit masks and bit positions */ -#define DMA_CH_TRIGSRC_gm 0xFF /* Channel Trigger Source group mask. */ -#define DMA_CH_TRIGSRC_gp 0 /* Channel Trigger Source group position. */ -#define DMA_CH_TRIGSRC0_bm (1<<0) /* Channel Trigger Source bit 0 mask. */ -#define DMA_CH_TRIGSRC0_bp 0 /* Channel Trigger Source bit 0 position. */ -#define DMA_CH_TRIGSRC1_bm (1<<1) /* Channel Trigger Source bit 1 mask. */ -#define DMA_CH_TRIGSRC1_bp 1 /* Channel Trigger Source bit 1 position. */ -#define DMA_CH_TRIGSRC2_bm (1<<2) /* Channel Trigger Source bit 2 mask. */ -#define DMA_CH_TRIGSRC2_bp 2 /* Channel Trigger Source bit 2 position. */ -#define DMA_CH_TRIGSRC3_bm (1<<3) /* Channel Trigger Source bit 3 mask. */ -#define DMA_CH_TRIGSRC3_bp 3 /* Channel Trigger Source bit 3 position. */ -#define DMA_CH_TRIGSRC4_bm (1<<4) /* Channel Trigger Source bit 4 mask. */ -#define DMA_CH_TRIGSRC4_bp 4 /* Channel Trigger Source bit 4 position. */ -#define DMA_CH_TRIGSRC5_bm (1<<5) /* Channel Trigger Source bit 5 mask. */ -#define DMA_CH_TRIGSRC5_bp 5 /* Channel Trigger Source bit 5 position. */ -#define DMA_CH_TRIGSRC6_bm (1<<6) /* Channel Trigger Source bit 6 mask. */ -#define DMA_CH_TRIGSRC6_bp 6 /* Channel Trigger Source bit 6 position. */ -#define DMA_CH_TRIGSRC7_bm (1<<7) /* Channel Trigger Source bit 7 mask. */ -#define DMA_CH_TRIGSRC7_bp 7 /* Channel Trigger Source bit 7 position. */ - -/* DMA.CTRL bit masks and bit positions */ -#define DMA_ENABLE_bm 0x80 /* Enable bit mask. */ -#define DMA_ENABLE_bp 7 /* Enable bit position. */ - -#define DMA_RESET_bm 0x40 /* Software Reset bit mask. */ -#define DMA_RESET_bp 6 /* Software Reset bit position. */ - -#define DMA_DBUFMODE_gm 0x0C /* Double Buffering Mode group mask. */ -#define DMA_DBUFMODE_gp 2 /* Double Buffering Mode group position. */ -#define DMA_DBUFMODE0_bm (1<<2) /* Double Buffering Mode bit 0 mask. */ -#define DMA_DBUFMODE0_bp 2 /* Double Buffering Mode bit 0 position. */ -#define DMA_DBUFMODE1_bm (1<<3) /* Double Buffering Mode bit 1 mask. */ -#define DMA_DBUFMODE1_bp 3 /* Double Buffering Mode bit 1 position. */ - -#define DMA_PRIMODE_gm 0x03 /* Channel Priority Mode group mask. */ -#define DMA_PRIMODE_gp 0 /* Channel Priority Mode group position. */ -#define DMA_PRIMODE0_bm (1<<0) /* Channel Priority Mode bit 0 mask. */ -#define DMA_PRIMODE0_bp 0 /* Channel Priority Mode bit 0 position. */ -#define DMA_PRIMODE1_bm (1<<1) /* Channel Priority Mode bit 1 mask. */ -#define DMA_PRIMODE1_bp 1 /* Channel Priority Mode bit 1 position. */ - -/* DMA.INTFLAGS bit masks and bit positions */ -#define DMA_CH3ERRIF_bm 0x80 /* Channel 3 Block Transfer Error Interrupt Flag bit mask. */ -#define DMA_CH3ERRIF_bp 7 /* Channel 3 Block Transfer Error Interrupt Flag bit position. */ - -#define DMA_CH2ERRIF_bm 0x40 /* Channel 2 Block Transfer Error Interrupt Flag bit mask. */ -#define DMA_CH2ERRIF_bp 6 /* Channel 2 Block Transfer Error Interrupt Flag bit position. */ - -#define DMA_CH1ERRIF_bm 0x20 /* Channel 1 Block Transfer Error Interrupt Flag bit mask. */ -#define DMA_CH1ERRIF_bp 5 /* Channel 1 Block Transfer Error Interrupt Flag bit position. */ - -#define DMA_CH0ERRIF_bm 0x10 /* Channel 0 Block Transfer Error Interrupt Flag bit mask. */ -#define DMA_CH0ERRIF_bp 4 /* Channel 0 Block Transfer Error Interrupt Flag bit position. */ - -#define DMA_CH3TRNIF_bm 0x08 /* Channel 3 Transaction Complete Interrupt Flag bit mask. */ -#define DMA_CH3TRNIF_bp 3 /* Channel 3 Transaction Complete Interrupt Flag bit position. */ - -#define DMA_CH2TRNIF_bm 0x04 /* Channel 2 Transaction Complete Interrupt Flag bit mask. */ -#define DMA_CH2TRNIF_bp 2 /* Channel 2 Transaction Complete Interrupt Flag bit position. */ - -#define DMA_CH1TRNIF_bm 0x02 /* Channel 1 Transaction Complete Interrupt Flag bit mask. */ -#define DMA_CH1TRNIF_bp 1 /* Channel 1 Transaction Complete Interrupt Flag bit position. */ - -#define DMA_CH0TRNIF_bm 0x01 /* Channel 0 Transaction Complete Interrupt Flag bit mask. */ -#define DMA_CH0TRNIF_bp 0 /* Channel 0 Transaction Complete Interrupt Flag bit position. */ - -/* DMA.STATUS bit masks and bit positions */ -#define DMA_CH3BUSY_bm 0x80 /* Channel 3 Block Transfer Busy bit mask. */ -#define DMA_CH3BUSY_bp 7 /* Channel 3 Block Transfer Busy bit position. */ - -#define DMA_CH2BUSY_bm 0x40 /* Channel 2 Block Transfer Busy bit mask. */ -#define DMA_CH2BUSY_bp 6 /* Channel 2 Block Transfer Busy bit position. */ - -#define DMA_CH1BUSY_bm 0x20 /* Channel 1 Block Transfer Busy bit mask. */ -#define DMA_CH1BUSY_bp 5 /* Channel 1 Block Transfer Busy bit position. */ - -#define DMA_CH0BUSY_bm 0x10 /* Channel 0 Block Transfer Busy bit mask. */ -#define DMA_CH0BUSY_bp 4 /* Channel 0 Block Transfer Busy bit position. */ - -#define DMA_CH3PEND_bm 0x08 /* Channel 3 Block Transfer Pending bit mask. */ -#define DMA_CH3PEND_bp 3 /* Channel 3 Block Transfer Pending bit position. */ - -#define DMA_CH2PEND_bm 0x04 /* Channel 2 Block Transfer Pending bit mask. */ -#define DMA_CH2PEND_bp 2 /* Channel 2 Block Transfer Pending bit position. */ - -#define DMA_CH1PEND_bm 0x02 /* Channel 1 Block Transfer Pending bit mask. */ -#define DMA_CH1PEND_bp 1 /* Channel 1 Block Transfer Pending bit position. */ - -#define DMA_CH0PEND_bm 0x01 /* Channel 0 Block Transfer Pending bit mask. */ -#define DMA_CH0PEND_bp 0 /* Channel 0 Block Transfer Pending bit position. */ - -/* EVSYS - Event System */ -/* EVSYS.CH0MUX bit masks and bit positions */ -#define EVSYS_CHMUX_gm 0xFF /* Event Channel 0 Multiplexer group mask. */ -#define EVSYS_CHMUX_gp 0 /* Event Channel 0 Multiplexer group position. */ -#define EVSYS_CHMUX0_bm (1<<0) /* Event Channel 0 Multiplexer bit 0 mask. */ -#define EVSYS_CHMUX0_bp 0 /* Event Channel 0 Multiplexer bit 0 position. */ -#define EVSYS_CHMUX1_bm (1<<1) /* Event Channel 0 Multiplexer bit 1 mask. */ -#define EVSYS_CHMUX1_bp 1 /* Event Channel 0 Multiplexer bit 1 position. */ -#define EVSYS_CHMUX2_bm (1<<2) /* Event Channel 0 Multiplexer bit 2 mask. */ -#define EVSYS_CHMUX2_bp 2 /* Event Channel 0 Multiplexer bit 2 position. */ -#define EVSYS_CHMUX3_bm (1<<3) /* Event Channel 0 Multiplexer bit 3 mask. */ -#define EVSYS_CHMUX3_bp 3 /* Event Channel 0 Multiplexer bit 3 position. */ -#define EVSYS_CHMUX4_bm (1<<4) /* Event Channel 0 Multiplexer bit 4 mask. */ -#define EVSYS_CHMUX4_bp 4 /* Event Channel 0 Multiplexer bit 4 position. */ -#define EVSYS_CHMUX5_bm (1<<5) /* Event Channel 0 Multiplexer bit 5 mask. */ -#define EVSYS_CHMUX5_bp 5 /* Event Channel 0 Multiplexer bit 5 position. */ -#define EVSYS_CHMUX6_bm (1<<6) /* Event Channel 0 Multiplexer bit 6 mask. */ -#define EVSYS_CHMUX6_bp 6 /* Event Channel 0 Multiplexer bit 6 position. */ -#define EVSYS_CHMUX7_bm (1<<7) /* Event Channel 0 Multiplexer bit 7 mask. */ -#define EVSYS_CHMUX7_bp 7 /* Event Channel 0 Multiplexer bit 7 position. */ - -/* EVSYS.CH1MUX bit masks and bit positions */ -/* EVSYS_CHMUX Predefined. */ -/* EVSYS_CHMUX Predefined. */ - -/* EVSYS.CH2MUX bit masks and bit positions */ -/* EVSYS_CHMUX Predefined. */ -/* EVSYS_CHMUX Predefined. */ - -/* EVSYS.CH3MUX bit masks and bit positions */ -/* EVSYS_CHMUX Predefined. */ -/* EVSYS_CHMUX Predefined. */ - -/* EVSYS.CH4MUX bit masks and bit positions */ -/* EVSYS_CHMUX Predefined. */ -/* EVSYS_CHMUX Predefined. */ - -/* EVSYS.CH5MUX bit masks and bit positions */ -/* EVSYS_CHMUX Predefined. */ -/* EVSYS_CHMUX Predefined. */ - -/* EVSYS.CH6MUX bit masks and bit positions */ -/* EVSYS_CHMUX Predefined. */ -/* EVSYS_CHMUX Predefined. */ - -/* EVSYS.CH7MUX bit masks and bit positions */ -/* EVSYS_CHMUX Predefined. */ -/* EVSYS_CHMUX Predefined. */ - -/* EVSYS.CH0CTRL bit masks and bit positions */ -#define EVSYS_QDIRM_gm 0x60 /* Quadrature Decoder Index Recognition Mode group mask. */ -#define EVSYS_QDIRM_gp 5 /* Quadrature Decoder Index Recognition Mode group position. */ -#define EVSYS_QDIRM0_bm (1<<5) /* Quadrature Decoder Index Recognition Mode bit 0 mask. */ -#define EVSYS_QDIRM0_bp 5 /* Quadrature Decoder Index Recognition Mode bit 0 position. */ -#define EVSYS_QDIRM1_bm (1<<6) /* Quadrature Decoder Index Recognition Mode bit 1 mask. */ -#define EVSYS_QDIRM1_bp 6 /* Quadrature Decoder Index Recognition Mode bit 1 position. */ - -#define EVSYS_QDIEN_bm 0x10 /* Quadrature Decoder Index Enable bit mask. */ -#define EVSYS_QDIEN_bp 4 /* Quadrature Decoder Index Enable bit position. */ - -#define EVSYS_QDEN_bm 0x08 /* Quadrature Decoder Enable bit mask. */ -#define EVSYS_QDEN_bp 3 /* Quadrature Decoder Enable bit position. */ - -#define EVSYS_DIGFILT_gm 0x07 /* Digital Filter group mask. */ -#define EVSYS_DIGFILT_gp 0 /* Digital Filter group position. */ -#define EVSYS_DIGFILT0_bm (1<<0) /* Digital Filter bit 0 mask. */ -#define EVSYS_DIGFILT0_bp 0 /* Digital Filter bit 0 position. */ -#define EVSYS_DIGFILT1_bm (1<<1) /* Digital Filter bit 1 mask. */ -#define EVSYS_DIGFILT1_bp 1 /* Digital Filter bit 1 position. */ -#define EVSYS_DIGFILT2_bm (1<<2) /* Digital Filter bit 2 mask. */ -#define EVSYS_DIGFILT2_bp 2 /* Digital Filter bit 2 position. */ - -/* EVSYS.CH1CTRL bit masks and bit positions */ -/* EVSYS_DIGFILT Predefined. */ -/* EVSYS_DIGFILT Predefined. */ - -/* EVSYS.CH2CTRL bit masks and bit positions */ -/* EVSYS_QDIRM Predefined. */ -/* EVSYS_QDIRM Predefined. */ - -/* EVSYS_QDIEN Predefined. */ -/* EVSYS_QDIEN Predefined. */ - -/* EVSYS_QDEN Predefined. */ -/* EVSYS_QDEN Predefined. */ - -/* EVSYS_DIGFILT Predefined. */ -/* EVSYS_DIGFILT Predefined. */ - -/* EVSYS.CH3CTRL bit masks and bit positions */ -/* EVSYS_DIGFILT Predefined. */ -/* EVSYS_DIGFILT Predefined. */ - -/* EVSYS.CH4CTRL bit masks and bit positions */ -/* EVSYS_QDIRM Predefined. */ -/* EVSYS_QDIRM Predefined. */ - -/* EVSYS_QDIEN Predefined. */ -/* EVSYS_QDIEN Predefined. */ - -/* EVSYS_QDEN Predefined. */ -/* EVSYS_QDEN Predefined. */ - -/* EVSYS_DIGFILT Predefined. */ -/* EVSYS_DIGFILT Predefined. */ - -/* EVSYS.CH5CTRL bit masks and bit positions */ -/* EVSYS_DIGFILT Predefined. */ -/* EVSYS_DIGFILT Predefined. */ - -/* EVSYS.CH6CTRL bit masks and bit positions */ -/* EVSYS_DIGFILT Predefined. */ -/* EVSYS_DIGFILT Predefined. */ - -/* EVSYS.CH7CTRL bit masks and bit positions */ -/* EVSYS_DIGFILT Predefined. */ -/* EVSYS_DIGFILT Predefined. */ - -/* NVM - Non Volatile Memory Controller */ -/* NVM.CMD bit masks and bit positions */ -#define NVM_CMD_gm 0x7F /* Command group mask. */ -#define NVM_CMD_gp 0 /* Command group position. */ -#define NVM_CMD0_bm (1<<0) /* Command bit 0 mask. */ -#define NVM_CMD0_bp 0 /* Command bit 0 position. */ -#define NVM_CMD1_bm (1<<1) /* Command bit 1 mask. */ -#define NVM_CMD1_bp 1 /* Command bit 1 position. */ -#define NVM_CMD2_bm (1<<2) /* Command bit 2 mask. */ -#define NVM_CMD2_bp 2 /* Command bit 2 position. */ -#define NVM_CMD3_bm (1<<3) /* Command bit 3 mask. */ -#define NVM_CMD3_bp 3 /* Command bit 3 position. */ -#define NVM_CMD4_bm (1<<4) /* Command bit 4 mask. */ -#define NVM_CMD4_bp 4 /* Command bit 4 position. */ -#define NVM_CMD5_bm (1<<5) /* Command bit 5 mask. */ -#define NVM_CMD5_bp 5 /* Command bit 5 position. */ -#define NVM_CMD6_bm (1<<6) /* Command bit 6 mask. */ -#define NVM_CMD6_bp 6 /* Command bit 6 position. */ - -/* NVM.CTRLA bit masks and bit positions */ -#define NVM_CMDEX_bm 0x01 /* Command Execute bit mask. */ -#define NVM_CMDEX_bp 0 /* Command Execute bit position. */ - -/* NVM.CTRLB bit masks and bit positions */ -#define NVM_EEMAPEN_bm 0x08 /* EEPROM Mapping Enable bit mask. */ -#define NVM_EEMAPEN_bp 3 /* EEPROM Mapping Enable bit position. */ - -#define NVM_FPRM_bm 0x04 /* Flash Power Reduction Enable bit mask. */ -#define NVM_FPRM_bp 2 /* Flash Power Reduction Enable bit position. */ - -#define NVM_EPRM_bm 0x02 /* EEPROM Power Reduction Enable bit mask. */ -#define NVM_EPRM_bp 1 /* EEPROM Power Reduction Enable bit position. */ - -#define NVM_SPMLOCK_bm 0x01 /* SPM Lock bit mask. */ -#define NVM_SPMLOCK_bp 0 /* SPM Lock bit position. */ - -/* NVM.INTCTRL bit masks and bit positions */ -#define NVM_SPMLVL_gm 0x0C /* SPM Interrupt Level group mask. */ -#define NVM_SPMLVL_gp 2 /* SPM Interrupt Level group position. */ -#define NVM_SPMLVL0_bm (1<<2) /* SPM Interrupt Level bit 0 mask. */ -#define NVM_SPMLVL0_bp 2 /* SPM Interrupt Level bit 0 position. */ -#define NVM_SPMLVL1_bm (1<<3) /* SPM Interrupt Level bit 1 mask. */ -#define NVM_SPMLVL1_bp 3 /* SPM Interrupt Level bit 1 position. */ - -#define NVM_EELVL_gm 0x03 /* EEPROM Interrupt Level group mask. */ -#define NVM_EELVL_gp 0 /* EEPROM Interrupt Level group position. */ -#define NVM_EELVL0_bm (1<<0) /* EEPROM Interrupt Level bit 0 mask. */ -#define NVM_EELVL0_bp 0 /* EEPROM Interrupt Level bit 0 position. */ -#define NVM_EELVL1_bm (1<<1) /* EEPROM Interrupt Level bit 1 mask. */ -#define NVM_EELVL1_bp 1 /* EEPROM Interrupt Level bit 1 position. */ - -/* NVM.STATUS bit masks and bit positions */ -#define NVM_NVMBUSY_bm 0x80 /* Non-volatile Memory Busy bit mask. */ -#define NVM_NVMBUSY_bp 7 /* Non-volatile Memory Busy bit position. */ - -#define NVM_FBUSY_bm 0x40 /* Flash Memory Busy bit mask. */ -#define NVM_FBUSY_bp 6 /* Flash Memory Busy bit position. */ - -#define NVM_EELOAD_bm 0x02 /* EEPROM Page Buffer Active Loading bit mask. */ -#define NVM_EELOAD_bp 1 /* EEPROM Page Buffer Active Loading bit position. */ - -#define NVM_FLOAD_bm 0x01 /* Flash Page Buffer Active Loading bit mask. */ -#define NVM_FLOAD_bp 0 /* Flash Page Buffer Active Loading bit position. */ - -/* NVM.LOCKBITS bit masks and bit positions */ -#define NVM_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ -#define NVM_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ -#define NVM_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ -#define NVM_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ -#define NVM_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ -#define NVM_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ - -#define NVM_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ -#define NVM_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ -#define NVM_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ -#define NVM_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ -#define NVM_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ -#define NVM_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ - -#define NVM_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ -#define NVM_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ -#define NVM_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ -#define NVM_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ -#define NVM_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ -#define NVM_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ - -#define NVM_LB_gm 0x03 /* Lock Bits group mask. */ -#define NVM_LB_gp 0 /* Lock Bits group position. */ -#define NVM_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ -#define NVM_LB0_bp 0 /* Lock Bits bit 0 position. */ -#define NVM_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ -#define NVM_LB1_bp 1 /* Lock Bits bit 1 position. */ - -/* AC - Analog Comparator */ -/* AC.AC0CTRL bit masks and bit positions */ -#define AC_INTMODE_gm 0xC0 /* Interrupt Mode group mask. */ -#define AC_INTMODE_gp 6 /* Interrupt Mode group position. */ -#define AC_INTMODE0_bm (1<<6) /* Interrupt Mode bit 0 mask. */ -#define AC_INTMODE0_bp 6 /* Interrupt Mode bit 0 position. */ -#define AC_INTMODE1_bm (1<<7) /* Interrupt Mode bit 1 mask. */ -#define AC_INTMODE1_bp 7 /* Interrupt Mode bit 1 position. */ - -#define AC_INTLVL_gm 0x30 /* Interrupt Level group mask. */ -#define AC_INTLVL_gp 4 /* Interrupt Level group position. */ -#define AC_INTLVL0_bm (1<<4) /* Interrupt Level bit 0 mask. */ -#define AC_INTLVL0_bp 4 /* Interrupt Level bit 0 position. */ -#define AC_INTLVL1_bm (1<<5) /* Interrupt Level bit 1 mask. */ -#define AC_INTLVL1_bp 5 /* Interrupt Level bit 1 position. */ - -#define AC_HSMODE_bm 0x08 /* High-speed Mode bit mask. */ -#define AC_HSMODE_bp 3 /* High-speed Mode bit position. */ - -#define AC_HYSMODE_gm 0x06 /* Hysteresis Mode group mask. */ -#define AC_HYSMODE_gp 1 /* Hysteresis Mode group position. */ -#define AC_HYSMODE0_bm (1<<1) /* Hysteresis Mode bit 0 mask. */ -#define AC_HYSMODE0_bp 1 /* Hysteresis Mode bit 0 position. */ -#define AC_HYSMODE1_bm (1<<2) /* Hysteresis Mode bit 1 mask. */ -#define AC_HYSMODE1_bp 2 /* Hysteresis Mode bit 1 position. */ - -#define AC_ENABLE_bm 0x01 /* Enable bit mask. */ -#define AC_ENABLE_bp 0 /* Enable bit position. */ - -/* AC.AC1CTRL bit masks and bit positions */ -/* AC_INTMODE Predefined. */ -/* AC_INTMODE Predefined. */ - -/* AC_INTLVL Predefined. */ -/* AC_INTLVL Predefined. */ - -/* AC_HSMODE Predefined. */ -/* AC_HSMODE Predefined. */ - -/* AC_HYSMODE Predefined. */ -/* AC_HYSMODE Predefined. */ - -/* AC_ENABLE Predefined. */ -/* AC_ENABLE Predefined. */ - -/* AC.AC0MUXCTRL bit masks and bit positions */ -#define AC_MUXPOS_gm 0x38 /* MUX Positive Input group mask. */ -#define AC_MUXPOS_gp 3 /* MUX Positive Input group position. */ -#define AC_MUXPOS0_bm (1<<3) /* MUX Positive Input bit 0 mask. */ -#define AC_MUXPOS0_bp 3 /* MUX Positive Input bit 0 position. */ -#define AC_MUXPOS1_bm (1<<4) /* MUX Positive Input bit 1 mask. */ -#define AC_MUXPOS1_bp 4 /* MUX Positive Input bit 1 position. */ -#define AC_MUXPOS2_bm (1<<5) /* MUX Positive Input bit 2 mask. */ -#define AC_MUXPOS2_bp 5 /* MUX Positive Input bit 2 position. */ - -#define AC_MUXNEG_gm 0x07 /* MUX Negative Input group mask. */ -#define AC_MUXNEG_gp 0 /* MUX Negative Input group position. */ -#define AC_MUXNEG0_bm (1<<0) /* MUX Negative Input bit 0 mask. */ -#define AC_MUXNEG0_bp 0 /* MUX Negative Input bit 0 position. */ -#define AC_MUXNEG1_bm (1<<1) /* MUX Negative Input bit 1 mask. */ -#define AC_MUXNEG1_bp 1 /* MUX Negative Input bit 1 position. */ -#define AC_MUXNEG2_bm (1<<2) /* MUX Negative Input bit 2 mask. */ -#define AC_MUXNEG2_bp 2 /* MUX Negative Input bit 2 position. */ - -/* AC.AC1MUXCTRL bit masks and bit positions */ -/* AC_MUXPOS Predefined. */ -/* AC_MUXPOS Predefined. */ - -/* AC_MUXNEG Predefined. */ -/* AC_MUXNEG Predefined. */ - -/* AC.CTRLA bit masks and bit positions */ -#define AC_AC1OUT_bm 0x02 /* Analog Comparator 1 Output Enable bit mask. */ -#define AC_AC1OUT_bp 1 /* Analog Comparator 1 Output Enable bit position. */ - -#define AC_AC0OUT_bm 0x01 /* Analog Comparator 0 Output Enable bit mask. */ -#define AC_AC0OUT_bp 0 /* Analog Comparator 0 Output Enable bit position. */ - -/* AC.CTRLB bit masks and bit positions */ -#define AC_SCALEFAC_gm 0x3F /* VCC Voltage Scaler Factor group mask. */ -#define AC_SCALEFAC_gp 0 /* VCC Voltage Scaler Factor group position. */ -#define AC_SCALEFAC0_bm (1<<0) /* VCC Voltage Scaler Factor bit 0 mask. */ -#define AC_SCALEFAC0_bp 0 /* VCC Voltage Scaler Factor bit 0 position. */ -#define AC_SCALEFAC1_bm (1<<1) /* VCC Voltage Scaler Factor bit 1 mask. */ -#define AC_SCALEFAC1_bp 1 /* VCC Voltage Scaler Factor bit 1 position. */ -#define AC_SCALEFAC2_bm (1<<2) /* VCC Voltage Scaler Factor bit 2 mask. */ -#define AC_SCALEFAC2_bp 2 /* VCC Voltage Scaler Factor bit 2 position. */ -#define AC_SCALEFAC3_bm (1<<3) /* VCC Voltage Scaler Factor bit 3 mask. */ -#define AC_SCALEFAC3_bp 3 /* VCC Voltage Scaler Factor bit 3 position. */ -#define AC_SCALEFAC4_bm (1<<4) /* VCC Voltage Scaler Factor bit 4 mask. */ -#define AC_SCALEFAC4_bp 4 /* VCC Voltage Scaler Factor bit 4 position. */ -#define AC_SCALEFAC5_bm (1<<5) /* VCC Voltage Scaler Factor bit 5 mask. */ -#define AC_SCALEFAC5_bp 5 /* VCC Voltage Scaler Factor bit 5 position. */ - -/* AC.WINCTRL bit masks and bit positions */ -#define AC_WEN_bm 0x10 /* Window Mode Enable bit mask. */ -#define AC_WEN_bp 4 /* Window Mode Enable bit position. */ - -#define AC_WINTMODE_gm 0x0C /* Window Interrupt Mode group mask. */ -#define AC_WINTMODE_gp 2 /* Window Interrupt Mode group position. */ -#define AC_WINTMODE0_bm (1<<2) /* Window Interrupt Mode bit 0 mask. */ -#define AC_WINTMODE0_bp 2 /* Window Interrupt Mode bit 0 position. */ -#define AC_WINTMODE1_bm (1<<3) /* Window Interrupt Mode bit 1 mask. */ -#define AC_WINTMODE1_bp 3 /* Window Interrupt Mode bit 1 position. */ - -#define AC_WINTLVL_gm 0x03 /* Window Interrupt Level group mask. */ -#define AC_WINTLVL_gp 0 /* Window Interrupt Level group position. */ -#define AC_WINTLVL0_bm (1<<0) /* Window Interrupt Level bit 0 mask. */ -#define AC_WINTLVL0_bp 0 /* Window Interrupt Level bit 0 position. */ -#define AC_WINTLVL1_bm (1<<1) /* Window Interrupt Level bit 1 mask. */ -#define AC_WINTLVL1_bp 1 /* Window Interrupt Level bit 1 position. */ - -/* AC.STATUS bit masks and bit positions */ -#define AC_WSTATE_gm 0xC0 /* Window Mode State group mask. */ -#define AC_WSTATE_gp 6 /* Window Mode State group position. */ -#define AC_WSTATE0_bm (1<<6) /* Window Mode State bit 0 mask. */ -#define AC_WSTATE0_bp 6 /* Window Mode State bit 0 position. */ -#define AC_WSTATE1_bm (1<<7) /* Window Mode State bit 1 mask. */ -#define AC_WSTATE1_bp 7 /* Window Mode State bit 1 position. */ - -#define AC_AC1STATE_bm 0x20 /* Analog Comparator 1 State bit mask. */ -#define AC_AC1STATE_bp 5 /* Analog Comparator 1 State bit position. */ - -#define AC_AC0STATE_bm 0x10 /* Analog Comparator 0 State bit mask. */ -#define AC_AC0STATE_bp 4 /* Analog Comparator 0 State bit position. */ - -#define AC_WIF_bm 0x04 /* Window Mode Interrupt Flag bit mask. */ -#define AC_WIF_bp 2 /* Window Mode Interrupt Flag bit position. */ - -#define AC_AC1IF_bm 0x02 /* Analog Comparator 1 Interrupt Flag bit mask. */ -#define AC_AC1IF_bp 1 /* Analog Comparator 1 Interrupt Flag bit position. */ - -#define AC_AC0IF_bm 0x01 /* Analog Comparator 0 Interrupt Flag bit mask. */ -#define AC_AC0IF_bp 0 /* Analog Comparator 0 Interrupt Flag bit position. */ - -/* ADC - Analog/Digital Converter */ -/* ADC_CH.CTRL bit masks and bit positions */ -#define ADC_CH_START_bm 0x80 /* Channel Start Conversion bit mask. */ -#define ADC_CH_START_bp 7 /* Channel Start Conversion bit position. */ - -#define ADC_CH_GAIN_gm 0x1C /* Gain Factor group mask. */ -#define ADC_CH_GAIN_gp 2 /* Gain Factor group position. */ -#define ADC_CH_GAIN0_bm (1<<2) /* Gain Factor bit 0 mask. */ -#define ADC_CH_GAIN0_bp 2 /* Gain Factor bit 0 position. */ -#define ADC_CH_GAIN1_bm (1<<3) /* Gain Factor bit 1 mask. */ -#define ADC_CH_GAIN1_bp 3 /* Gain Factor bit 1 position. */ -#define ADC_CH_GAIN2_bm (1<<4) /* Gain Factor bit 2 mask. */ -#define ADC_CH_GAIN2_bp 4 /* Gain Factor bit 2 position. */ - -#define ADC_CH_INPUTMODE_gm 0x03 /* Input Mode Select group mask. */ -#define ADC_CH_INPUTMODE_gp 0 /* Input Mode Select group position. */ -#define ADC_CH_INPUTMODE0_bm (1<<0) /* Input Mode Select bit 0 mask. */ -#define ADC_CH_INPUTMODE0_bp 0 /* Input Mode Select bit 0 position. */ -#define ADC_CH_INPUTMODE1_bm (1<<1) /* Input Mode Select bit 1 mask. */ -#define ADC_CH_INPUTMODE1_bp 1 /* Input Mode Select bit 1 position. */ - -/* ADC_CH.MUXCTRL bit masks and bit positions */ -#define ADC_CH_MUXPOS_gm 0x78 /* MUX selection on Positive ADC input group mask. */ -#define ADC_CH_MUXPOS_gp 3 /* MUX selection on Positive ADC input group position. */ -#define ADC_CH_MUXPOS0_bm (1<<3) /* MUX selection on Positive ADC input bit 0 mask. */ -#define ADC_CH_MUXPOS0_bp 3 /* MUX selection on Positive ADC input bit 0 position. */ -#define ADC_CH_MUXPOS1_bm (1<<4) /* MUX selection on Positive ADC input bit 1 mask. */ -#define ADC_CH_MUXPOS1_bp 4 /* MUX selection on Positive ADC input bit 1 position. */ -#define ADC_CH_MUXPOS2_bm (1<<5) /* MUX selection on Positive ADC input bit 2 mask. */ -#define ADC_CH_MUXPOS2_bp 5 /* MUX selection on Positive ADC input bit 2 position. */ -#define ADC_CH_MUXPOS3_bm (1<<6) /* MUX selection on Positive ADC input bit 3 mask. */ -#define ADC_CH_MUXPOS3_bp 6 /* MUX selection on Positive ADC input bit 3 position. */ - -#define ADC_CH_MUXINT_gm 0x78 /* MUX selection on Internal ADC input group mask. */ -#define ADC_CH_MUXINT_gp 3 /* MUX selection on Internal ADC input group position. */ -#define ADC_CH_MUXINT0_bm (1<<3) /* MUX selection on Internal ADC input bit 0 mask. */ -#define ADC_CH_MUXINT0_bp 3 /* MUX selection on Internal ADC input bit 0 position. */ -#define ADC_CH_MUXINT1_bm (1<<4) /* MUX selection on Internal ADC input bit 1 mask. */ -#define ADC_CH_MUXINT1_bp 4 /* MUX selection on Internal ADC input bit 1 position. */ -#define ADC_CH_MUXINT2_bm (1<<5) /* MUX selection on Internal ADC input bit 2 mask. */ -#define ADC_CH_MUXINT2_bp 5 /* MUX selection on Internal ADC input bit 2 position. */ -#define ADC_CH_MUXINT3_bm (1<<6) /* MUX selection on Internal ADC input bit 3 mask. */ -#define ADC_CH_MUXINT3_bp 6 /* MUX selection on Internal ADC input bit 3 position. */ - -#define ADC_CH_MUXNEG_gm 0x07 /* MUX selection on Negative ADC input group mask. */ -#define ADC_CH_MUXNEG_gp 0 /* MUX selection on Negative ADC input group position. */ -#define ADC_CH_MUXNEG0_bm (1<<0) /* MUX selection on Negative ADC input bit 0 mask. */ -#define ADC_CH_MUXNEG0_bp 0 /* MUX selection on Negative ADC input bit 0 position. */ -#define ADC_CH_MUXNEG1_bm (1<<1) /* MUX selection on Negative ADC input bit 1 mask. */ -#define ADC_CH_MUXNEG1_bp 1 /* MUX selection on Negative ADC input bit 1 position. */ -#define ADC_CH_MUXNEG2_bm (1<<2) /* MUX selection on Negative ADC input bit 2 mask. */ -#define ADC_CH_MUXNEG2_bp 2 /* MUX selection on Negative ADC input bit 2 position. */ - -/* ADC_CH.INTCTRL bit masks and bit positions */ -#define ADC_CH_INTMODE_gm 0x0C /* Interrupt Mode group mask. */ -#define ADC_CH_INTMODE_gp 2 /* Interrupt Mode group position. */ -#define ADC_CH_INTMODE0_bm (1<<2) /* Interrupt Mode bit 0 mask. */ -#define ADC_CH_INTMODE0_bp 2 /* Interrupt Mode bit 0 position. */ -#define ADC_CH_INTMODE1_bm (1<<3) /* Interrupt Mode bit 1 mask. */ -#define ADC_CH_INTMODE1_bp 3 /* Interrupt Mode bit 1 position. */ - -#define ADC_CH_INTLVL_gm 0x03 /* Interrupt Level group mask. */ -#define ADC_CH_INTLVL_gp 0 /* Interrupt Level group position. */ -#define ADC_CH_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */ -#define ADC_CH_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */ -#define ADC_CH_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ -#define ADC_CH_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */ - -/* ADC_CH.INTFLAGS bit masks and bit positions */ -#define ADC_CH_CHIF_bm 0x01 /* Channel Interrupt Flag bit mask. */ -#define ADC_CH_CHIF_bp 0 /* Channel Interrupt Flag bit position. */ - -/* ADC_CH.SCAN bit masks and bit positions */ -#define ADC_CH_OFFSET_gm 0xF0 /* Positive MUX setting offset group mask. */ -#define ADC_CH_OFFSET_gp 4 /* Positive MUX setting offset group position. */ -#define ADC_CH_OFFSET0_bm (1<<4) /* Positive MUX setting offset bit 0 mask. */ -#define ADC_CH_OFFSET0_bp 4 /* Positive MUX setting offset bit 0 position. */ -#define ADC_CH_OFFSET1_bm (1<<5) /* Positive MUX setting offset bit 1 mask. */ -#define ADC_CH_OFFSET1_bp 5 /* Positive MUX setting offset bit 1 position. */ -#define ADC_CH_OFFSET2_bm (1<<6) /* Positive MUX setting offset bit 2 mask. */ -#define ADC_CH_OFFSET2_bp 6 /* Positive MUX setting offset bit 2 position. */ -#define ADC_CH_OFFSET3_bm (1<<7) /* Positive MUX setting offset bit 3 mask. */ -#define ADC_CH_OFFSET3_bp 7 /* Positive MUX setting offset bit 3 position. */ - -#define ADC_CH_SCANNUM_gm 0x0F /* Number of Channels included in scan group mask. */ -#define ADC_CH_SCANNUM_gp 0 /* Number of Channels included in scan group position. */ -#define ADC_CH_SCANNUM0_bm (1<<0) /* Number of Channels included in scan bit 0 mask. */ -#define ADC_CH_SCANNUM0_bp 0 /* Number of Channels included in scan bit 0 position. */ -#define ADC_CH_SCANNUM1_bm (1<<1) /* Number of Channels included in scan bit 1 mask. */ -#define ADC_CH_SCANNUM1_bp 1 /* Number of Channels included in scan bit 1 position. */ -#define ADC_CH_SCANNUM2_bm (1<<2) /* Number of Channels included in scan bit 2 mask. */ -#define ADC_CH_SCANNUM2_bp 2 /* Number of Channels included in scan bit 2 position. */ -#define ADC_CH_SCANNUM3_bm (1<<3) /* Number of Channels included in scan bit 3 mask. */ -#define ADC_CH_SCANNUM3_bp 3 /* Number of Channels included in scan bit 3 position. */ - -/* ADC.CTRLA bit masks and bit positions */ -#define ADC_DMASEL_gm 0xC0 /* DMA Selection group mask. */ -#define ADC_DMASEL_gp 6 /* DMA Selection group position. */ -#define ADC_DMASEL0_bm (1<<6) /* DMA Selection bit 0 mask. */ -#define ADC_DMASEL0_bp 6 /* DMA Selection bit 0 position. */ -#define ADC_DMASEL1_bm (1<<7) /* DMA Selection bit 1 mask. */ -#define ADC_DMASEL1_bp 7 /* DMA Selection bit 1 position. */ - -#define ADC_CH3START_bm 0x20 /* Channel 3 Start Conversion bit mask. */ -#define ADC_CH3START_bp 5 /* Channel 3 Start Conversion bit position. */ - -#define ADC_CH2START_bm 0x10 /* Channel 2 Start Conversion bit mask. */ -#define ADC_CH2START_bp 4 /* Channel 2 Start Conversion bit position. */ - -#define ADC_CH1START_bm 0x08 /* Channel 1 Start Conversion bit mask. */ -#define ADC_CH1START_bp 3 /* Channel 1 Start Conversion bit position. */ - -#define ADC_CH0START_bm 0x04 /* Channel 0 Start Conversion bit mask. */ -#define ADC_CH0START_bp 2 /* Channel 0 Start Conversion bit position. */ - -#define ADC_FLUSH_bm 0x02 /* Flush Pipeline bit mask. */ -#define ADC_FLUSH_bp 1 /* Flush Pipeline bit position. */ - -#define ADC_ENABLE_bm 0x01 /* Enable ADC bit mask. */ -#define ADC_ENABLE_bp 0 /* Enable ADC bit position. */ - -/* ADC.CTRLB bit masks and bit positions */ -#define ADC_IMPMODE_bm 0x80 /* Gain Stage Impedance Mode bit mask. */ -#define ADC_IMPMODE_bp 7 /* Gain Stage Impedance Mode bit position. */ - -#define ADC_CURRLIMIT_gm 0x60 /* Current Limitation group mask. */ -#define ADC_CURRLIMIT_gp 5 /* Current Limitation group position. */ -#define ADC_CURRLIMIT0_bm (1<<5) /* Current Limitation bit 0 mask. */ -#define ADC_CURRLIMIT0_bp 5 /* Current Limitation bit 0 position. */ -#define ADC_CURRLIMIT1_bm (1<<6) /* Current Limitation bit 1 mask. */ -#define ADC_CURRLIMIT1_bp 6 /* Current Limitation bit 1 position. */ - -#define ADC_CONMODE_bm 0x10 /* Conversion Mode bit mask. */ -#define ADC_CONMODE_bp 4 /* Conversion Mode bit position. */ - -#define ADC_FREERUN_bm 0x08 /* Free Running Mode Enable bit mask. */ -#define ADC_FREERUN_bp 3 /* Free Running Mode Enable bit position. */ - -#define ADC_RESOLUTION_gm 0x06 /* Result Resolution group mask. */ -#define ADC_RESOLUTION_gp 1 /* Result Resolution group position. */ -#define ADC_RESOLUTION0_bm (1<<1) /* Result Resolution bit 0 mask. */ -#define ADC_RESOLUTION0_bp 1 /* Result Resolution bit 0 position. */ -#define ADC_RESOLUTION1_bm (1<<2) /* Result Resolution bit 1 mask. */ -#define ADC_RESOLUTION1_bp 2 /* Result Resolution bit 1 position. */ - -/* ADC.REFCTRL bit masks and bit positions */ -#define ADC_REFSEL_gm 0x70 /* Reference Selection group mask. */ -#define ADC_REFSEL_gp 4 /* Reference Selection group position. */ -#define ADC_REFSEL0_bm (1<<4) /* Reference Selection bit 0 mask. */ -#define ADC_REFSEL0_bp 4 /* Reference Selection bit 0 position. */ -#define ADC_REFSEL1_bm (1<<5) /* Reference Selection bit 1 mask. */ -#define ADC_REFSEL1_bp 5 /* Reference Selection bit 1 position. */ -#define ADC_REFSEL2_bm (1<<6) /* Reference Selection bit 2 mask. */ -#define ADC_REFSEL2_bp 6 /* Reference Selection bit 2 position. */ - -#define ADC_BANDGAP_bm 0x02 /* Bandgap enable bit mask. */ -#define ADC_BANDGAP_bp 1 /* Bandgap enable bit position. */ - -#define ADC_TEMPREF_bm 0x01 /* Temperature Reference Enable bit mask. */ -#define ADC_TEMPREF_bp 0 /* Temperature Reference Enable bit position. */ - -/* ADC.EVCTRL bit masks and bit positions */ -#define ADC_SWEEP_gm 0xC0 /* Channel Sweep Selection group mask. */ -#define ADC_SWEEP_gp 6 /* Channel Sweep Selection group position. */ -#define ADC_SWEEP0_bm (1<<6) /* Channel Sweep Selection bit 0 mask. */ -#define ADC_SWEEP0_bp 6 /* Channel Sweep Selection bit 0 position. */ -#define ADC_SWEEP1_bm (1<<7) /* Channel Sweep Selection bit 1 mask. */ -#define ADC_SWEEP1_bp 7 /* Channel Sweep Selection bit 1 position. */ - -#define ADC_EVSEL_gm 0x38 /* Event Input Select group mask. */ -#define ADC_EVSEL_gp 3 /* Event Input Select group position. */ -#define ADC_EVSEL0_bm (1<<3) /* Event Input Select bit 0 mask. */ -#define ADC_EVSEL0_bp 3 /* Event Input Select bit 0 position. */ -#define ADC_EVSEL1_bm (1<<4) /* Event Input Select bit 1 mask. */ -#define ADC_EVSEL1_bp 4 /* Event Input Select bit 1 position. */ -#define ADC_EVSEL2_bm (1<<5) /* Event Input Select bit 2 mask. */ -#define ADC_EVSEL2_bp 5 /* Event Input Select bit 2 position. */ - -#define ADC_EVACT_gm 0x07 /* Event Action Select group mask. */ -#define ADC_EVACT_gp 0 /* Event Action Select group position. */ -#define ADC_EVACT0_bm (1<<0) /* Event Action Select bit 0 mask. */ -#define ADC_EVACT0_bp 0 /* Event Action Select bit 0 position. */ -#define ADC_EVACT1_bm (1<<1) /* Event Action Select bit 1 mask. */ -#define ADC_EVACT1_bp 1 /* Event Action Select bit 1 position. */ -#define ADC_EVACT2_bm (1<<2) /* Event Action Select bit 2 mask. */ -#define ADC_EVACT2_bp 2 /* Event Action Select bit 2 position. */ - -/* ADC.PRESCALER bit masks and bit positions */ -#define ADC_PRESCALER_gm 0x07 /* Clock Prescaler Selection group mask. */ -#define ADC_PRESCALER_gp 0 /* Clock Prescaler Selection group position. */ -#define ADC_PRESCALER0_bm (1<<0) /* Clock Prescaler Selection bit 0 mask. */ -#define ADC_PRESCALER0_bp 0 /* Clock Prescaler Selection bit 0 position. */ -#define ADC_PRESCALER1_bm (1<<1) /* Clock Prescaler Selection bit 1 mask. */ -#define ADC_PRESCALER1_bp 1 /* Clock Prescaler Selection bit 1 position. */ -#define ADC_PRESCALER2_bm (1<<2) /* Clock Prescaler Selection bit 2 mask. */ -#define ADC_PRESCALER2_bp 2 /* Clock Prescaler Selection bit 2 position. */ - -/* ADC.INTFLAGS bit masks and bit positions */ -#define ADC_CH3IF_bm 0x08 /* Channel 3 Interrupt Flag bit mask. */ -#define ADC_CH3IF_bp 3 /* Channel 3 Interrupt Flag bit position. */ - -#define ADC_CH2IF_bm 0x04 /* Channel 2 Interrupt Flag bit mask. */ -#define ADC_CH2IF_bp 2 /* Channel 2 Interrupt Flag bit position. */ - -#define ADC_CH1IF_bm 0x02 /* Channel 1 Interrupt Flag bit mask. */ -#define ADC_CH1IF_bp 1 /* Channel 1 Interrupt Flag bit position. */ - -#define ADC_CH0IF_bm 0x01 /* Channel 0 Interrupt Flag bit mask. */ -#define ADC_CH0IF_bp 0 /* Channel 0 Interrupt Flag bit position. */ - -/* DAC - Digital/Analog Converter */ -/* DAC.CTRLA bit masks and bit positions */ -#define DAC_IDOEN_bm 0x10 /* Internal Output Enable bit mask. */ -#define DAC_IDOEN_bp 4 /* Internal Output Enable bit position. */ - -#define DAC_CH1EN_bm 0x08 /* Channel 1 Output Enable bit mask. */ -#define DAC_CH1EN_bp 3 /* Channel 1 Output Enable bit position. */ - -#define DAC_CH0EN_bm 0x04 /* Channel 0 Output Enable bit mask. */ -#define DAC_CH0EN_bp 2 /* Channel 0 Output Enable bit position. */ - -#define DAC_LPMODE_bm 0x02 /* Low Power Mode bit mask. */ -#define DAC_LPMODE_bp 1 /* Low Power Mode bit position. */ - -#define DAC_ENABLE_bm 0x01 /* Enable bit mask. */ -#define DAC_ENABLE_bp 0 /* Enable bit position. */ - -/* DAC.CTRLB bit masks and bit positions */ -#define DAC_CHSEL_gm 0x60 /* Channel Select group mask. */ -#define DAC_CHSEL_gp 5 /* Channel Select group position. */ -#define DAC_CHSEL0_bm (1<<5) /* Channel Select bit 0 mask. */ -#define DAC_CHSEL0_bp 5 /* Channel Select bit 0 position. */ -#define DAC_CHSEL1_bm (1<<6) /* Channel Select bit 1 mask. */ -#define DAC_CHSEL1_bp 6 /* Channel Select bit 1 position. */ - -#define DAC_CH1TRIG_bm 0x02 /* Channel 1 Event Trig Enable bit mask. */ -#define DAC_CH1TRIG_bp 1 /* Channel 1 Event Trig Enable bit position. */ - -#define DAC_CH0TRIG_bm 0x01 /* Channel 0 Event Trig Enable bit mask. */ -#define DAC_CH0TRIG_bp 0 /* Channel 0 Event Trig Enable bit position. */ - -/* DAC.CTRLC bit masks and bit positions */ -#define DAC_REFSEL_gm 0x18 /* Reference Select group mask. */ -#define DAC_REFSEL_gp 3 /* Reference Select group position. */ -#define DAC_REFSEL0_bm (1<<3) /* Reference Select bit 0 mask. */ -#define DAC_REFSEL0_bp 3 /* Reference Select bit 0 position. */ -#define DAC_REFSEL1_bm (1<<4) /* Reference Select bit 1 mask. */ -#define DAC_REFSEL1_bp 4 /* Reference Select bit 1 position. */ - -#define DAC_LEFTADJ_bm 0x01 /* Left-adjust Result bit mask. */ -#define DAC_LEFTADJ_bp 0 /* Left-adjust Result bit position. */ - -/* DAC.EVCTRL bit masks and bit positions */ -#define DAC_EVSPLIT_bm 0x08 /* Separate Event Channel Input for Channel 1 bit mask. */ -#define DAC_EVSPLIT_bp 3 /* Separate Event Channel Input for Channel 1 bit position. */ - -#define DAC_EVSEL_gm 0x07 /* Event Input Selection group mask. */ -#define DAC_EVSEL_gp 0 /* Event Input Selection group position. */ -#define DAC_EVSEL0_bm (1<<0) /* Event Input Selection bit 0 mask. */ -#define DAC_EVSEL0_bp 0 /* Event Input Selection bit 0 position. */ -#define DAC_EVSEL1_bm (1<<1) /* Event Input Selection bit 1 mask. */ -#define DAC_EVSEL1_bp 1 /* Event Input Selection bit 1 position. */ -#define DAC_EVSEL2_bm (1<<2) /* Event Input Selection bit 2 mask. */ -#define DAC_EVSEL2_bp 2 /* Event Input Selection bit 2 position. */ - -/* DAC.STATUS bit masks and bit positions */ -#define DAC_CH1DRE_bm 0x02 /* Channel 1 Data Register Empty bit mask. */ -#define DAC_CH1DRE_bp 1 /* Channel 1 Data Register Empty bit position. */ - -#define DAC_CH0DRE_bm 0x01 /* Channel 0 Data Register Empty bit mask. */ -#define DAC_CH0DRE_bp 0 /* Channel 0 Data Register Empty bit position. */ - -/* DAC.CH0GAINCAL bit masks and bit positions */ -#define DAC_CH0GAINCAL_gm 0x7F /* Gain Calibration group mask. */ -#define DAC_CH0GAINCAL_gp 0 /* Gain Calibration group position. */ -#define DAC_CH0GAINCAL0_bm (1<<0) /* Gain Calibration bit 0 mask. */ -#define DAC_CH0GAINCAL0_bp 0 /* Gain Calibration bit 0 position. */ -#define DAC_CH0GAINCAL1_bm (1<<1) /* Gain Calibration bit 1 mask. */ -#define DAC_CH0GAINCAL1_bp 1 /* Gain Calibration bit 1 position. */ -#define DAC_CH0GAINCAL2_bm (1<<2) /* Gain Calibration bit 2 mask. */ -#define DAC_CH0GAINCAL2_bp 2 /* Gain Calibration bit 2 position. */ -#define DAC_CH0GAINCAL3_bm (1<<3) /* Gain Calibration bit 3 mask. */ -#define DAC_CH0GAINCAL3_bp 3 /* Gain Calibration bit 3 position. */ -#define DAC_CH0GAINCAL4_bm (1<<4) /* Gain Calibration bit 4 mask. */ -#define DAC_CH0GAINCAL4_bp 4 /* Gain Calibration bit 4 position. */ -#define DAC_CH0GAINCAL5_bm (1<<5) /* Gain Calibration bit 5 mask. */ -#define DAC_CH0GAINCAL5_bp 5 /* Gain Calibration bit 5 position. */ -#define DAC_CH0GAINCAL6_bm (1<<6) /* Gain Calibration bit 6 mask. */ -#define DAC_CH0GAINCAL6_bp 6 /* Gain Calibration bit 6 position. */ - -/* DAC.CH0OFFSETCAL bit masks and bit positions */ -#define DAC_CH0OFFSETCAL_gm 0x7F /* Offset Calibration group mask. */ -#define DAC_CH0OFFSETCAL_gp 0 /* Offset Calibration group position. */ -#define DAC_CH0OFFSETCAL0_bm (1<<0) /* Offset Calibration bit 0 mask. */ -#define DAC_CH0OFFSETCAL0_bp 0 /* Offset Calibration bit 0 position. */ -#define DAC_CH0OFFSETCAL1_bm (1<<1) /* Offset Calibration bit 1 mask. */ -#define DAC_CH0OFFSETCAL1_bp 1 /* Offset Calibration bit 1 position. */ -#define DAC_CH0OFFSETCAL2_bm (1<<2) /* Offset Calibration bit 2 mask. */ -#define DAC_CH0OFFSETCAL2_bp 2 /* Offset Calibration bit 2 position. */ -#define DAC_CH0OFFSETCAL3_bm (1<<3) /* Offset Calibration bit 3 mask. */ -#define DAC_CH0OFFSETCAL3_bp 3 /* Offset Calibration bit 3 position. */ -#define DAC_CH0OFFSETCAL4_bm (1<<4) /* Offset Calibration bit 4 mask. */ -#define DAC_CH0OFFSETCAL4_bp 4 /* Offset Calibration bit 4 position. */ -#define DAC_CH0OFFSETCAL5_bm (1<<5) /* Offset Calibration bit 5 mask. */ -#define DAC_CH0OFFSETCAL5_bp 5 /* Offset Calibration bit 5 position. */ -#define DAC_CH0OFFSETCAL6_bm (1<<6) /* Offset Calibration bit 6 mask. */ -#define DAC_CH0OFFSETCAL6_bp 6 /* Offset Calibration bit 6 position. */ - -/* DAC.CH1GAINCAL bit masks and bit positions */ -#define DAC_CH1GAINCAL_gm 0x7F /* Gain Calibration group mask. */ -#define DAC_CH1GAINCAL_gp 0 /* Gain Calibration group position. */ -#define DAC_CH1GAINCAL0_bm (1<<0) /* Gain Calibration bit 0 mask. */ -#define DAC_CH1GAINCAL0_bp 0 /* Gain Calibration bit 0 position. */ -#define DAC_CH1GAINCAL1_bm (1<<1) /* Gain Calibration bit 1 mask. */ -#define DAC_CH1GAINCAL1_bp 1 /* Gain Calibration bit 1 position. */ -#define DAC_CH1GAINCAL2_bm (1<<2) /* Gain Calibration bit 2 mask. */ -#define DAC_CH1GAINCAL2_bp 2 /* Gain Calibration bit 2 position. */ -#define DAC_CH1GAINCAL3_bm (1<<3) /* Gain Calibration bit 3 mask. */ -#define DAC_CH1GAINCAL3_bp 3 /* Gain Calibration bit 3 position. */ -#define DAC_CH1GAINCAL4_bm (1<<4) /* Gain Calibration bit 4 mask. */ -#define DAC_CH1GAINCAL4_bp 4 /* Gain Calibration bit 4 position. */ -#define DAC_CH1GAINCAL5_bm (1<<5) /* Gain Calibration bit 5 mask. */ -#define DAC_CH1GAINCAL5_bp 5 /* Gain Calibration bit 5 position. */ -#define DAC_CH1GAINCAL6_bm (1<<6) /* Gain Calibration bit 6 mask. */ -#define DAC_CH1GAINCAL6_bp 6 /* Gain Calibration bit 6 position. */ - -/* DAC.CH1OFFSETCAL bit masks and bit positions */ -#define DAC_CH1OFFSETCAL_gm 0x7F /* Offset Calibration group mask. */ -#define DAC_CH1OFFSETCAL_gp 0 /* Offset Calibration group position. */ -#define DAC_CH1OFFSETCAL0_bm (1<<0) /* Offset Calibration bit 0 mask. */ -#define DAC_CH1OFFSETCAL0_bp 0 /* Offset Calibration bit 0 position. */ -#define DAC_CH1OFFSETCAL1_bm (1<<1) /* Offset Calibration bit 1 mask. */ -#define DAC_CH1OFFSETCAL1_bp 1 /* Offset Calibration bit 1 position. */ -#define DAC_CH1OFFSETCAL2_bm (1<<2) /* Offset Calibration bit 2 mask. */ -#define DAC_CH1OFFSETCAL2_bp 2 /* Offset Calibration bit 2 position. */ -#define DAC_CH1OFFSETCAL3_bm (1<<3) /* Offset Calibration bit 3 mask. */ -#define DAC_CH1OFFSETCAL3_bp 3 /* Offset Calibration bit 3 position. */ -#define DAC_CH1OFFSETCAL4_bm (1<<4) /* Offset Calibration bit 4 mask. */ -#define DAC_CH1OFFSETCAL4_bp 4 /* Offset Calibration bit 4 position. */ -#define DAC_CH1OFFSETCAL5_bm (1<<5) /* Offset Calibration bit 5 mask. */ -#define DAC_CH1OFFSETCAL5_bp 5 /* Offset Calibration bit 5 position. */ -#define DAC_CH1OFFSETCAL6_bm (1<<6) /* Offset Calibration bit 6 mask. */ -#define DAC_CH1OFFSETCAL6_bp 6 /* Offset Calibration bit 6 position. */ - -/* RTC - Real-Time Counter */ -/* RTC.CTRL bit masks and bit positions */ -#define RTC_PRESCALER_gm 0x07 /* Prescaling Factor group mask. */ -#define RTC_PRESCALER_gp 0 /* Prescaling Factor group position. */ -#define RTC_PRESCALER0_bm (1<<0) /* Prescaling Factor bit 0 mask. */ -#define RTC_PRESCALER0_bp 0 /* Prescaling Factor bit 0 position. */ -#define RTC_PRESCALER1_bm (1<<1) /* Prescaling Factor bit 1 mask. */ -#define RTC_PRESCALER1_bp 1 /* Prescaling Factor bit 1 position. */ -#define RTC_PRESCALER2_bm (1<<2) /* Prescaling Factor bit 2 mask. */ -#define RTC_PRESCALER2_bp 2 /* Prescaling Factor bit 2 position. */ - -/* RTC.STATUS bit masks and bit positions */ -#define RTC_SYNCBUSY_bm 0x01 /* Synchronization Busy Flag bit mask. */ -#define RTC_SYNCBUSY_bp 0 /* Synchronization Busy Flag bit position. */ - -/* RTC.INTCTRL bit masks and bit positions */ -#define RTC_COMPINTLVL_gm 0x0C /* Compare Match Interrupt Level group mask. */ -#define RTC_COMPINTLVL_gp 2 /* Compare Match Interrupt Level group position. */ -#define RTC_COMPINTLVL0_bm (1<<2) /* Compare Match Interrupt Level bit 0 mask. */ -#define RTC_COMPINTLVL0_bp 2 /* Compare Match Interrupt Level bit 0 position. */ -#define RTC_COMPINTLVL1_bm (1<<3) /* Compare Match Interrupt Level bit 1 mask. */ -#define RTC_COMPINTLVL1_bp 3 /* Compare Match Interrupt Level bit 1 position. */ - -#define RTC_OVFINTLVL_gm 0x03 /* Overflow Interrupt Level group mask. */ -#define RTC_OVFINTLVL_gp 0 /* Overflow Interrupt Level group position. */ -#define RTC_OVFINTLVL0_bm (1<<0) /* Overflow Interrupt Level bit 0 mask. */ -#define RTC_OVFINTLVL0_bp 0 /* Overflow Interrupt Level bit 0 position. */ -#define RTC_OVFINTLVL1_bm (1<<1) /* Overflow Interrupt Level bit 1 mask. */ -#define RTC_OVFINTLVL1_bp 1 /* Overflow Interrupt Level bit 1 position. */ - -/* RTC.INTFLAGS bit masks and bit positions */ -#define RTC_COMPIF_bm 0x02 /* Compare Match Interrupt Flag bit mask. */ -#define RTC_COMPIF_bp 1 /* Compare Match Interrupt Flag bit position. */ - -#define RTC_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ -#define RTC_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ - -/* TWI - Two-Wire Interface */ -/* TWI_MASTER.CTRLA bit masks and bit positions */ -#define TWI_MASTER_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ -#define TWI_MASTER_INTLVL_gp 6 /* Interrupt Level group position. */ -#define TWI_MASTER_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ -#define TWI_MASTER_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ -#define TWI_MASTER_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ -#define TWI_MASTER_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ - -#define TWI_MASTER_RIEN_bm 0x20 /* Read Interrupt Enable bit mask. */ -#define TWI_MASTER_RIEN_bp 5 /* Read Interrupt Enable bit position. */ - -#define TWI_MASTER_WIEN_bm 0x10 /* Write Interrupt Enable bit mask. */ -#define TWI_MASTER_WIEN_bp 4 /* Write Interrupt Enable bit position. */ - -#define TWI_MASTER_ENABLE_bm 0x08 /* Enable TWI Master bit mask. */ -#define TWI_MASTER_ENABLE_bp 3 /* Enable TWI Master bit position. */ - -/* TWI_MASTER.CTRLB bit masks and bit positions */ -#define TWI_MASTER_TIMEOUT_gm 0x0C /* Inactive Bus Timeout group mask. */ -#define TWI_MASTER_TIMEOUT_gp 2 /* Inactive Bus Timeout group position. */ -#define TWI_MASTER_TIMEOUT0_bm (1<<2) /* Inactive Bus Timeout bit 0 mask. */ -#define TWI_MASTER_TIMEOUT0_bp 2 /* Inactive Bus Timeout bit 0 position. */ -#define TWI_MASTER_TIMEOUT1_bm (1<<3) /* Inactive Bus Timeout bit 1 mask. */ -#define TWI_MASTER_TIMEOUT1_bp 3 /* Inactive Bus Timeout bit 1 position. */ - -#define TWI_MASTER_QCEN_bm 0x02 /* Quick Command Enable bit mask. */ -#define TWI_MASTER_QCEN_bp 1 /* Quick Command Enable bit position. */ - -#define TWI_MASTER_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ -#define TWI_MASTER_SMEN_bp 0 /* Smart Mode Enable bit position. */ - -/* TWI_MASTER.CTRLC bit masks and bit positions */ -#define TWI_MASTER_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ -#define TWI_MASTER_ACKACT_bp 2 /* Acknowledge Action bit position. */ - -#define TWI_MASTER_CMD_gm 0x03 /* Command group mask. */ -#define TWI_MASTER_CMD_gp 0 /* Command group position. */ -#define TWI_MASTER_CMD0_bm (1<<0) /* Command bit 0 mask. */ -#define TWI_MASTER_CMD0_bp 0 /* Command bit 0 position. */ -#define TWI_MASTER_CMD1_bm (1<<1) /* Command bit 1 mask. */ -#define TWI_MASTER_CMD1_bp 1 /* Command bit 1 position. */ - -/* TWI_MASTER.STATUS bit masks and bit positions */ -#define TWI_MASTER_RIF_bm 0x80 /* Read Interrupt Flag bit mask. */ -#define TWI_MASTER_RIF_bp 7 /* Read Interrupt Flag bit position. */ - -#define TWI_MASTER_WIF_bm 0x40 /* Write Interrupt Flag bit mask. */ -#define TWI_MASTER_WIF_bp 6 /* Write Interrupt Flag bit position. */ - -#define TWI_MASTER_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ -#define TWI_MASTER_CLKHOLD_bp 5 /* Clock Hold bit position. */ - -#define TWI_MASTER_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ -#define TWI_MASTER_RXACK_bp 4 /* Received Acknowledge bit position. */ - -#define TWI_MASTER_ARBLOST_bm 0x08 /* Arbitration Lost bit mask. */ -#define TWI_MASTER_ARBLOST_bp 3 /* Arbitration Lost bit position. */ - -#define TWI_MASTER_BUSERR_bm 0x04 /* Bus Error bit mask. */ -#define TWI_MASTER_BUSERR_bp 2 /* Bus Error bit position. */ - -#define TWI_MASTER_BUSSTATE_gm 0x03 /* Bus State group mask. */ -#define TWI_MASTER_BUSSTATE_gp 0 /* Bus State group position. */ -#define TWI_MASTER_BUSSTATE0_bm (1<<0) /* Bus State bit 0 mask. */ -#define TWI_MASTER_BUSSTATE0_bp 0 /* Bus State bit 0 position. */ -#define TWI_MASTER_BUSSTATE1_bm (1<<1) /* Bus State bit 1 mask. */ -#define TWI_MASTER_BUSSTATE1_bp 1 /* Bus State bit 1 position. */ - -/* TWI_SLAVE.CTRLA bit masks and bit positions */ -#define TWI_SLAVE_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ -#define TWI_SLAVE_INTLVL_gp 6 /* Interrupt Level group position. */ -#define TWI_SLAVE_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ -#define TWI_SLAVE_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ -#define TWI_SLAVE_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ -#define TWI_SLAVE_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ - -#define TWI_SLAVE_DIEN_bm 0x20 /* Data Interrupt Enable bit mask. */ -#define TWI_SLAVE_DIEN_bp 5 /* Data Interrupt Enable bit position. */ - -#define TWI_SLAVE_APIEN_bm 0x10 /* Address/Stop Interrupt Enable bit mask. */ -#define TWI_SLAVE_APIEN_bp 4 /* Address/Stop Interrupt Enable bit position. */ - -#define TWI_SLAVE_ENABLE_bm 0x08 /* Enable TWI Slave bit mask. */ -#define TWI_SLAVE_ENABLE_bp 3 /* Enable TWI Slave bit position. */ - -#define TWI_SLAVE_PIEN_bm 0x04 /* Stop Interrupt Enable bit mask. */ -#define TWI_SLAVE_PIEN_bp 2 /* Stop Interrupt Enable bit position. */ - -#define TWI_SLAVE_PMEN_bm 0x02 /* Promiscuous Mode Enable bit mask. */ -#define TWI_SLAVE_PMEN_bp 1 /* Promiscuous Mode Enable bit position. */ - -#define TWI_SLAVE_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ -#define TWI_SLAVE_SMEN_bp 0 /* Smart Mode Enable bit position. */ - -/* TWI_SLAVE.CTRLB bit masks and bit positions */ -#define TWI_SLAVE_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ -#define TWI_SLAVE_ACKACT_bp 2 /* Acknowledge Action bit position. */ - -#define TWI_SLAVE_CMD_gm 0x03 /* Command group mask. */ -#define TWI_SLAVE_CMD_gp 0 /* Command group position. */ -#define TWI_SLAVE_CMD0_bm (1<<0) /* Command bit 0 mask. */ -#define TWI_SLAVE_CMD0_bp 0 /* Command bit 0 position. */ -#define TWI_SLAVE_CMD1_bm (1<<1) /* Command bit 1 mask. */ -#define TWI_SLAVE_CMD1_bp 1 /* Command bit 1 position. */ - -/* TWI_SLAVE.STATUS bit masks and bit positions */ -#define TWI_SLAVE_DIF_bm 0x80 /* Data Interrupt Flag bit mask. */ -#define TWI_SLAVE_DIF_bp 7 /* Data Interrupt Flag bit position. */ - -#define TWI_SLAVE_APIF_bm 0x40 /* Address/Stop Interrupt Flag bit mask. */ -#define TWI_SLAVE_APIF_bp 6 /* Address/Stop Interrupt Flag bit position. */ - -#define TWI_SLAVE_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ -#define TWI_SLAVE_CLKHOLD_bp 5 /* Clock Hold bit position. */ - -#define TWI_SLAVE_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ -#define TWI_SLAVE_RXACK_bp 4 /* Received Acknowledge bit position. */ - -#define TWI_SLAVE_COLL_bm 0x08 /* Collision bit mask. */ -#define TWI_SLAVE_COLL_bp 3 /* Collision bit position. */ - -#define TWI_SLAVE_BUSERR_bm 0x04 /* Bus Error bit mask. */ -#define TWI_SLAVE_BUSERR_bp 2 /* Bus Error bit position. */ - -#define TWI_SLAVE_DIR_bm 0x02 /* Read/Write Direction bit mask. */ -#define TWI_SLAVE_DIR_bp 1 /* Read/Write Direction bit position. */ - -#define TWI_SLAVE_AP_bm 0x01 /* Slave Address or Stop bit mask. */ -#define TWI_SLAVE_AP_bp 0 /* Slave Address or Stop bit position. */ - -/* TWI_SLAVE.ADDRMASK bit masks and bit positions */ -#define TWI_SLAVE_ADDRMASK_gm 0xFE /* Address Mask group mask. */ -#define TWI_SLAVE_ADDRMASK_gp 1 /* Address Mask group position. */ -#define TWI_SLAVE_ADDRMASK0_bm (1<<1) /* Address Mask bit 0 mask. */ -#define TWI_SLAVE_ADDRMASK0_bp 1 /* Address Mask bit 0 position. */ -#define TWI_SLAVE_ADDRMASK1_bm (1<<2) /* Address Mask bit 1 mask. */ -#define TWI_SLAVE_ADDRMASK1_bp 2 /* Address Mask bit 1 position. */ -#define TWI_SLAVE_ADDRMASK2_bm (1<<3) /* Address Mask bit 2 mask. */ -#define TWI_SLAVE_ADDRMASK2_bp 3 /* Address Mask bit 2 position. */ -#define TWI_SLAVE_ADDRMASK3_bm (1<<4) /* Address Mask bit 3 mask. */ -#define TWI_SLAVE_ADDRMASK3_bp 4 /* Address Mask bit 3 position. */ -#define TWI_SLAVE_ADDRMASK4_bm (1<<5) /* Address Mask bit 4 mask. */ -#define TWI_SLAVE_ADDRMASK4_bp 5 /* Address Mask bit 4 position. */ -#define TWI_SLAVE_ADDRMASK5_bm (1<<6) /* Address Mask bit 5 mask. */ -#define TWI_SLAVE_ADDRMASK5_bp 6 /* Address Mask bit 5 position. */ -#define TWI_SLAVE_ADDRMASK6_bm (1<<7) /* Address Mask bit 6 mask. */ -#define TWI_SLAVE_ADDRMASK6_bp 7 /* Address Mask bit 6 position. */ - -#define TWI_SLAVE_ADDREN_bm 0x01 /* Address Enable bit mask. */ -#define TWI_SLAVE_ADDREN_bp 0 /* Address Enable bit position. */ - -/* TWI.CTRL bit masks and bit positions */ -#define TWI_SDAHOLD_gm 0x06 /* SDA Hold Time Enable group mask. */ -#define TWI_SDAHOLD_gp 1 /* SDA Hold Time Enable group position. */ -#define TWI_SDAHOLD0_bm (1<<1) /* SDA Hold Time Enable bit 0 mask. */ -#define TWI_SDAHOLD0_bp 1 /* SDA Hold Time Enable bit 0 position. */ -#define TWI_SDAHOLD1_bm (1<<2) /* SDA Hold Time Enable bit 1 mask. */ -#define TWI_SDAHOLD1_bp 2 /* SDA Hold Time Enable bit 1 position. */ - -#define TWI_EDIEN_bm 0x01 /* External Driver Interface Enable bit mask. */ -#define TWI_EDIEN_bp 0 /* External Driver Interface Enable bit position. */ - -/* USB - USB */ -/* USB_EP.STATUS bit masks and bit positions */ -#define USB_EP_STALLF_bm 0x80 /* Endpoint Stall Flag bit mask. */ -#define USB_EP_STALLF_bp 7 /* Endpoint Stall Flag bit position. */ - -#define USB_EP_CRC_bm 0x80 /* CRC Error Flag bit mask. */ -#define USB_EP_CRC_bp 7 /* CRC Error Flag bit position. */ - -#define USB_EP_UNF_bm 0x40 /* Underflow Enpoint FLag bit mask. */ -#define USB_EP_UNF_bp 6 /* Underflow Enpoint FLag bit position. */ - -#define USB_EP_OVF_bm 0x40 /* Overflow Enpoint Flag for Output Endpoints bit mask. */ -#define USB_EP_OVF_bp 6 /* Overflow Enpoint Flag for Output Endpoints bit position. */ - -#define USB_EP_TRNCOMPL0_bm 0x20 /* Transaction Complete 0 Flag bit mask. */ -#define USB_EP_TRNCOMPL0_bp 5 /* Transaction Complete 0 Flag bit position. */ - -#define USB_EP_TRNCOMPL1_bm 0x10 /* Transaction Complete 1 Flag bit mask. */ -#define USB_EP_TRNCOMPL1_bp 4 /* Transaction Complete 1 Flag bit position. */ - -#define USB_EP_SETUP_bm 0x10 /* SETUP Transaction Complete Flag bit mask. */ -#define USB_EP_SETUP_bp 4 /* SETUP Transaction Complete Flag bit position. */ - -#define USB_EP_BANK_bm 0x08 /* Bank Select bit mask. */ -#define USB_EP_BANK_bp 3 /* Bank Select bit position. */ - -#define USB_EP_BUSNACK1_bm 0x04 /* Data Buffer 1 Not Acknowledge bit mask. */ -#define USB_EP_BUSNACK1_bp 2 /* Data Buffer 1 Not Acknowledge bit position. */ - -#define USB_EP_BUSNACK0_bm 0x02 /* Data Buffer 0 Not Acknowledge bit mask. */ -#define USB_EP_BUSNACK0_bp 1 /* Data Buffer 0 Not Acknowledge bit position. */ - -#define USB_EP_TOGGLE_bm 0x01 /* Data Toggle bit mask. */ -#define USB_EP_TOGGLE_bp 0 /* Data Toggle bit position. */ - -/* USB_EP.CTRL bit masks and bit positions */ -#define USB_EP_TYPE_gm 0xC0 /* Endpoint Type group mask. */ -#define USB_EP_TYPE_gp 6 /* Endpoint Type group position. */ -#define USB_EP_TYPE0_bm (1<<6) /* Endpoint Type bit 0 mask. */ -#define USB_EP_TYPE0_bp 6 /* Endpoint Type bit 0 position. */ -#define USB_EP_TYPE1_bm (1<<7) /* Endpoint Type bit 1 mask. */ -#define USB_EP_TYPE1_bp 7 /* Endpoint Type bit 1 position. */ - -#define USB_EP_MULTIPKT_bm 0x20 /* Multi Packet Transfer Enable bit mask. */ -#define USB_EP_MULTIPKT_bp 5 /* Multi Packet Transfer Enable bit position. */ - -#define USB_EP_PINGPONG_bm 0x10 /* Ping-Pong Enable bit mask. */ -#define USB_EP_PINGPONG_bp 4 /* Ping-Pong Enable bit position. */ - -#define USB_EP_INTDSBL_bm 0x08 /* Interrupt Disable bit mask. */ -#define USB_EP_INTDSBL_bp 3 /* Interrupt Disable bit position. */ - -#define USB_EP_STALL_bm 0x04 /* Data Stall bit mask. */ -#define USB_EP_STALL_bp 2 /* Data Stall bit position. */ - -#define USB_EP_BUFSIZE_gm 0x07 /* Data Buffer Size group mask. */ -#define USB_EP_BUFSIZE_gp 0 /* Data Buffer Size group position. */ -#define USB_EP_BUFSIZE0_bm (1<<0) /* Data Buffer Size bit 0 mask. */ -#define USB_EP_BUFSIZE0_bp 0 /* Data Buffer Size bit 0 position. */ -#define USB_EP_BUFSIZE1_bm (1<<1) /* Data Buffer Size bit 1 mask. */ -#define USB_EP_BUFSIZE1_bp 1 /* Data Buffer Size bit 1 position. */ -#define USB_EP_BUFSIZE2_bm (1<<2) /* Data Buffer Size bit 2 mask. */ -#define USB_EP_BUFSIZE2_bp 2 /* Data Buffer Size bit 2 position. */ - -/* USB_EP.CNT bit masks and bit positions */ -#define USB_EP_ZLP_bm 0x8000 /* Zero Length Packet bit mask. */ -#define USB_EP_ZLP_bp 15 /* Zero Length Packet bit position. */ - -/* USB.CTRLA bit masks and bit positions */ -#define USB_ENABLE_bm 0x80 /* USB Enable bit mask. */ -#define USB_ENABLE_bp 7 /* USB Enable bit position. */ - -#define USB_SPEED_bm 0x40 /* Speed Select bit mask. */ -#define USB_SPEED_bp 6 /* Speed Select bit position. */ - -#define USB_FIFOEN_bm 0x20 /* USB FIFO Enable bit mask. */ -#define USB_FIFOEN_bp 5 /* USB FIFO Enable bit position. */ - -#define USB_STFRNUM_bm 0x10 /* Store Frame Number Enable bit mask. */ -#define USB_STFRNUM_bp 4 /* Store Frame Number Enable bit position. */ - -#define USB_MAXEP_gm 0x0F /* Maximum Endpoint Addresses group mask. */ -#define USB_MAXEP_gp 0 /* Maximum Endpoint Addresses group position. */ -#define USB_MAXEP0_bm (1<<0) /* Maximum Endpoint Addresses bit 0 mask. */ -#define USB_MAXEP0_bp 0 /* Maximum Endpoint Addresses bit 0 position. */ -#define USB_MAXEP1_bm (1<<1) /* Maximum Endpoint Addresses bit 1 mask. */ -#define USB_MAXEP1_bp 1 /* Maximum Endpoint Addresses bit 1 position. */ -#define USB_MAXEP2_bm (1<<2) /* Maximum Endpoint Addresses bit 2 mask. */ -#define USB_MAXEP2_bp 2 /* Maximum Endpoint Addresses bit 2 position. */ -#define USB_MAXEP3_bm (1<<3) /* Maximum Endpoint Addresses bit 3 mask. */ -#define USB_MAXEP3_bp 3 /* Maximum Endpoint Addresses bit 3 position. */ - -/* USB.CTRLB bit masks and bit positions */ -#define USB_PULLRST_bm 0x10 /* Pull during Reset bit mask. */ -#define USB_PULLRST_bp 4 /* Pull during Reset bit position. */ - -#define USB_RWAKEUP_bm 0x04 /* Remote Wake-up bit mask. */ -#define USB_RWAKEUP_bp 2 /* Remote Wake-up bit position. */ - -#define USB_GNACK_bm 0x02 /* Global NACK bit mask. */ -#define USB_GNACK_bp 1 /* Global NACK bit position. */ - -#define USB_ATTACH_bm 0x01 /* Attach bit mask. */ -#define USB_ATTACH_bp 0 /* Attach bit position. */ - -/* USB.STATUS bit masks and bit positions */ -#define USB_URESUME_bm 0x08 /* Upstream Resume bit mask. */ -#define USB_URESUME_bp 3 /* Upstream Resume bit position. */ - -#define USB_RESUME_bm 0x04 /* Resume bit mask. */ -#define USB_RESUME_bp 2 /* Resume bit position. */ - -#define USB_SUSPEND_bm 0x02 /* Bus Suspended bit mask. */ -#define USB_SUSPEND_bp 1 /* Bus Suspended bit position. */ - -#define USB_BUSRST_bm 0x01 /* Bus Reset bit mask. */ -#define USB_BUSRST_bp 0 /* Bus Reset bit position. */ - -/* USB.ADDR bit masks and bit positions */ -#define USB_ADDR_gm 0x7F /* Device Address group mask. */ -#define USB_ADDR_gp 0 /* Device Address group position. */ -#define USB_ADDR0_bm (1<<0) /* Device Address bit 0 mask. */ -#define USB_ADDR0_bp 0 /* Device Address bit 0 position. */ -#define USB_ADDR1_bm (1<<1) /* Device Address bit 1 mask. */ -#define USB_ADDR1_bp 1 /* Device Address bit 1 position. */ -#define USB_ADDR2_bm (1<<2) /* Device Address bit 2 mask. */ -#define USB_ADDR2_bp 2 /* Device Address bit 2 position. */ -#define USB_ADDR3_bm (1<<3) /* Device Address bit 3 mask. */ -#define USB_ADDR3_bp 3 /* Device Address bit 3 position. */ -#define USB_ADDR4_bm (1<<4) /* Device Address bit 4 mask. */ -#define USB_ADDR4_bp 4 /* Device Address bit 4 position. */ -#define USB_ADDR5_bm (1<<5) /* Device Address bit 5 mask. */ -#define USB_ADDR5_bp 5 /* Device Address bit 5 position. */ -#define USB_ADDR6_bm (1<<6) /* Device Address bit 6 mask. */ -#define USB_ADDR6_bp 6 /* Device Address bit 6 position. */ - -/* USB.FIFOWP bit masks and bit positions */ -#define USB_FIFOWP_gm 0x1F /* FIFO Write Pointer group mask. */ -#define USB_FIFOWP_gp 0 /* FIFO Write Pointer group position. */ -#define USB_FIFOWP0_bm (1<<0) /* FIFO Write Pointer bit 0 mask. */ -#define USB_FIFOWP0_bp 0 /* FIFO Write Pointer bit 0 position. */ -#define USB_FIFOWP1_bm (1<<1) /* FIFO Write Pointer bit 1 mask. */ -#define USB_FIFOWP1_bp 1 /* FIFO Write Pointer bit 1 position. */ -#define USB_FIFOWP2_bm (1<<2) /* FIFO Write Pointer bit 2 mask. */ -#define USB_FIFOWP2_bp 2 /* FIFO Write Pointer bit 2 position. */ -#define USB_FIFOWP3_bm (1<<3) /* FIFO Write Pointer bit 3 mask. */ -#define USB_FIFOWP3_bp 3 /* FIFO Write Pointer bit 3 position. */ -#define USB_FIFOWP4_bm (1<<4) /* FIFO Write Pointer bit 4 mask. */ -#define USB_FIFOWP4_bp 4 /* FIFO Write Pointer bit 4 position. */ - -/* USB.FIFORP bit masks and bit positions */ -#define USB_FIFORP_gm 0x1F /* FIFO Read Pointer group mask. */ -#define USB_FIFORP_gp 0 /* FIFO Read Pointer group position. */ -#define USB_FIFORP0_bm (1<<0) /* FIFO Read Pointer bit 0 mask. */ -#define USB_FIFORP0_bp 0 /* FIFO Read Pointer bit 0 position. */ -#define USB_FIFORP1_bm (1<<1) /* FIFO Read Pointer bit 1 mask. */ -#define USB_FIFORP1_bp 1 /* FIFO Read Pointer bit 1 position. */ -#define USB_FIFORP2_bm (1<<2) /* FIFO Read Pointer bit 2 mask. */ -#define USB_FIFORP2_bp 2 /* FIFO Read Pointer bit 2 position. */ -#define USB_FIFORP3_bm (1<<3) /* FIFO Read Pointer bit 3 mask. */ -#define USB_FIFORP3_bp 3 /* FIFO Read Pointer bit 3 position. */ -#define USB_FIFORP4_bm (1<<4) /* FIFO Read Pointer bit 4 mask. */ -#define USB_FIFORP4_bp 4 /* FIFO Read Pointer bit 4 position. */ - -/* USB.INTCTRLA bit masks and bit positions */ -#define USB_SOFIE_bm 0x80 /* Start Of Frame Interrupt Enable bit mask. */ -#define USB_SOFIE_bp 7 /* Start Of Frame Interrupt Enable bit position. */ - -#define USB_BUSEVIE_bm 0x40 /* Bus Event Interrupt Enable bit mask. */ -#define USB_BUSEVIE_bp 6 /* Bus Event Interrupt Enable bit position. */ - -#define USB_BUSERRIE_bm 0x20 /* Bus Error Interrupt Enable bit mask. */ -#define USB_BUSERRIE_bp 5 /* Bus Error Interrupt Enable bit position. */ - -#define USB_STALLIE_bm 0x10 /* STALL Interrupt Enable bit mask. */ -#define USB_STALLIE_bp 4 /* STALL Interrupt Enable bit position. */ - -#define USB_INTLVL_gm 0x03 /* Interrupt Level group mask. */ -#define USB_INTLVL_gp 0 /* Interrupt Level group position. */ -#define USB_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */ -#define USB_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */ -#define USB_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ -#define USB_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */ - -/* USB.INTCTRLB bit masks and bit positions */ -#define USB_TRNIE_bm 0x02 /* Transaction Complete Interrupt Enable bit mask. */ -#define USB_TRNIE_bp 1 /* Transaction Complete Interrupt Enable bit position. */ - -#define USB_SETUPIE_bm 0x01 /* SETUP Transaction Complete Interrupt Enable bit mask. */ -#define USB_SETUPIE_bp 0 /* SETUP Transaction Complete Interrupt Enable bit position. */ - -/* USB.INTFLAGSACLR bit masks and bit positions */ -#define USB_SOFIF_bm 0x80 /* Start Of Frame Interrupt Flag bit mask. */ -#define USB_SOFIF_bp 7 /* Start Of Frame Interrupt Flag bit position. */ - -#define USB_SUSPENDIF_bm 0x40 /* Suspend Interrupt Flag bit mask. */ -#define USB_SUSPENDIF_bp 6 /* Suspend Interrupt Flag bit position. */ - -#define USB_RESUMEIF_bm 0x20 /* Resume Interrupt Flag bit mask. */ -#define USB_RESUMEIF_bp 5 /* Resume Interrupt Flag bit position. */ - -#define USB_RSTIF_bm 0x10 /* Reset Interrupt Flag bit mask. */ -#define USB_RSTIF_bp 4 /* Reset Interrupt Flag bit position. */ - -#define USB_CRCIF_bm 0x08 /* Isochronous CRC Error Interrupt Flag bit mask. */ -#define USB_CRCIF_bp 3 /* Isochronous CRC Error Interrupt Flag bit position. */ - -#define USB_UNFIF_bm 0x04 /* Underflow Interrupt Flag bit mask. */ -#define USB_UNFIF_bp 2 /* Underflow Interrupt Flag bit position. */ - -#define USB_OVFIF_bm 0x02 /* Overflow Interrupt Flag bit mask. */ -#define USB_OVFIF_bp 1 /* Overflow Interrupt Flag bit position. */ - -#define USB_STALLIF_bm 0x01 /* STALL Interrupt Flag bit mask. */ -#define USB_STALLIF_bp 0 /* STALL Interrupt Flag bit position. */ - -/* USB.INTFLAGSASET bit masks and bit positions */ -/* USB_SOFIF Predefined. */ -/* USB_SOFIF Predefined. */ - -/* USB_SUSPENDIF Predefined. */ -/* USB_SUSPENDIF Predefined. */ - -/* USB_RESUMEIF Predefined. */ -/* USB_RESUMEIF Predefined. */ - -/* USB_RSTIF Predefined. */ -/* USB_RSTIF Predefined. */ - -/* USB_CRCIF Predefined. */ -/* USB_CRCIF Predefined. */ - -/* USB_UNFIF Predefined. */ -/* USB_UNFIF Predefined. */ - -/* USB_OVFIF Predefined. */ -/* USB_OVFIF Predefined. */ - -/* USB_STALLIF Predefined. */ -/* USB_STALLIF Predefined. */ - -/* USB.INTFLAGSBCLR bit masks and bit positions */ -#define USB_TRNIF_bm 0x02 /* Transaction Complete Interrupt Flag bit mask. */ -#define USB_TRNIF_bp 1 /* Transaction Complete Interrupt Flag bit position. */ - -#define USB_SETUPIF_bm 0x01 /* SETUP Transaction Complete Interrupt Flag bit mask. */ -#define USB_SETUPIF_bp 0 /* SETUP Transaction Complete Interrupt Flag bit position. */ - -/* USB.INTFLAGSBSET bit masks and bit positions */ -/* USB_TRNIF Predefined. */ -/* USB_TRNIF Predefined. */ - -/* USB_SETUPIF Predefined. */ -/* USB_SETUPIF Predefined. */ - -/* PORT - I/O Port Configuration */ -/* PORT.INTCTRL bit masks and bit positions */ -#define PORT_INT1LVL_gm 0x0C /* Port Interrupt 1 Level group mask. */ -#define PORT_INT1LVL_gp 2 /* Port Interrupt 1 Level group position. */ -#define PORT_INT1LVL0_bm (1<<2) /* Port Interrupt 1 Level bit 0 mask. */ -#define PORT_INT1LVL0_bp 2 /* Port Interrupt 1 Level bit 0 position. */ -#define PORT_INT1LVL1_bm (1<<3) /* Port Interrupt 1 Level bit 1 mask. */ -#define PORT_INT1LVL1_bp 3 /* Port Interrupt 1 Level bit 1 position. */ - -#define PORT_INT0LVL_gm 0x03 /* Port Interrupt 0 Level group mask. */ -#define PORT_INT0LVL_gp 0 /* Port Interrupt 0 Level group position. */ -#define PORT_INT0LVL0_bm (1<<0) /* Port Interrupt 0 Level bit 0 mask. */ -#define PORT_INT0LVL0_bp 0 /* Port Interrupt 0 Level bit 0 position. */ -#define PORT_INT0LVL1_bm (1<<1) /* Port Interrupt 0 Level bit 1 mask. */ -#define PORT_INT0LVL1_bp 1 /* Port Interrupt 0 Level bit 1 position. */ - -/* PORT.INTFLAGS bit masks and bit positions */ -#define PORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ -#define PORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ - -#define PORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ -#define PORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ - -/* PORT.REMAP bit masks and bit positions */ -#define PORT_SPI_bm 0x20 /* SPI bit mask. */ -#define PORT_SPI_bp 5 /* SPI bit position. */ - -#define PORT_USART0_bm 0x10 /* USART0 bit mask. */ -#define PORT_USART0_bp 4 /* USART0 bit position. */ - -#define PORT_TC0D_bm 0x08 /* Timer/Counter 0 Output Compare D bit mask. */ -#define PORT_TC0D_bp 3 /* Timer/Counter 0 Output Compare D bit position. */ - -#define PORT_TC0C_bm 0x04 /* Timer/Counter 0 Output Compare C bit mask. */ -#define PORT_TC0C_bp 2 /* Timer/Counter 0 Output Compare C bit position. */ - -#define PORT_TC0B_bm 0x02 /* Timer/Counter 0 Output Compare B bit mask. */ -#define PORT_TC0B_bp 1 /* Timer/Counter 0 Output Compare B bit position. */ - -#define PORT_TC0A_bm 0x01 /* Timer/Counter 0 Output Compare A bit mask. */ -#define PORT_TC0A_bp 0 /* Timer/Counter 0 Output Compare A bit position. */ - -/* PORT.PIN0CTRL bit masks and bit positions */ -#define PORT_SRLEN_bm 0x80 /* Slew Rate Enable bit mask. */ -#define PORT_SRLEN_bp 7 /* Slew Rate Enable bit position. */ - -#define PORT_INVEN_bm 0x40 /* Inverted I/O Enable bit mask. */ -#define PORT_INVEN_bp 6 /* Inverted I/O Enable bit position. */ - -#define PORT_OPC_gm 0x38 /* Output/Pull Configuration group mask. */ -#define PORT_OPC_gp 3 /* Output/Pull Configuration group position. */ -#define PORT_OPC0_bm (1<<3) /* Output/Pull Configuration bit 0 mask. */ -#define PORT_OPC0_bp 3 /* Output/Pull Configuration bit 0 position. */ -#define PORT_OPC1_bm (1<<4) /* Output/Pull Configuration bit 1 mask. */ -#define PORT_OPC1_bp 4 /* Output/Pull Configuration bit 1 position. */ -#define PORT_OPC2_bm (1<<5) /* Output/Pull Configuration bit 2 mask. */ -#define PORT_OPC2_bp 5 /* Output/Pull Configuration bit 2 position. */ - -#define PORT_ISC_gm 0x07 /* Input/Sense Configuration group mask. */ -#define PORT_ISC_gp 0 /* Input/Sense Configuration group position. */ -#define PORT_ISC0_bm (1<<0) /* Input/Sense Configuration bit 0 mask. */ -#define PORT_ISC0_bp 0 /* Input/Sense Configuration bit 0 position. */ -#define PORT_ISC1_bm (1<<1) /* Input/Sense Configuration bit 1 mask. */ -#define PORT_ISC1_bp 1 /* Input/Sense Configuration bit 1 position. */ -#define PORT_ISC2_bm (1<<2) /* Input/Sense Configuration bit 2 mask. */ -#define PORT_ISC2_bp 2 /* Input/Sense Configuration bit 2 position. */ - -/* PORT.PIN1CTRL bit masks and bit positions */ -/* PORT_SRLEN Predefined. */ -/* PORT_SRLEN Predefined. */ - -/* PORT_INVEN Predefined. */ -/* PORT_INVEN Predefined. */ - -/* PORT_OPC Predefined. */ -/* PORT_OPC Predefined. */ - -/* PORT_ISC Predefined. */ -/* PORT_ISC Predefined. */ - -/* PORT.PIN2CTRL bit masks and bit positions */ -/* PORT_SRLEN Predefined. */ -/* PORT_SRLEN Predefined. */ - -/* PORT_INVEN Predefined. */ -/* PORT_INVEN Predefined. */ - -/* PORT_OPC Predefined. */ -/* PORT_OPC Predefined. */ - -/* PORT_ISC Predefined. */ -/* PORT_ISC Predefined. */ - -/* PORT.PIN3CTRL bit masks and bit positions */ -/* PORT_SRLEN Predefined. */ -/* PORT_SRLEN Predefined. */ - -/* PORT_INVEN Predefined. */ -/* PORT_INVEN Predefined. */ - -/* PORT_OPC Predefined. */ -/* PORT_OPC Predefined. */ - -/* PORT_ISC Predefined. */ -/* PORT_ISC Predefined. */ - -/* PORT.PIN4CTRL bit masks and bit positions */ -/* PORT_SRLEN Predefined. */ -/* PORT_SRLEN Predefined. */ - -/* PORT_INVEN Predefined. */ -/* PORT_INVEN Predefined. */ - -/* PORT_OPC Predefined. */ -/* PORT_OPC Predefined. */ - -/* PORT_ISC Predefined. */ -/* PORT_ISC Predefined. */ - -/* PORT.PIN5CTRL bit masks and bit positions */ -/* PORT_SRLEN Predefined. */ -/* PORT_SRLEN Predefined. */ - -/* PORT_INVEN Predefined. */ -/* PORT_INVEN Predefined. */ - -/* PORT_OPC Predefined. */ -/* PORT_OPC Predefined. */ - -/* PORT_ISC Predefined. */ -/* PORT_ISC Predefined. */ - -/* PORT.PIN6CTRL bit masks and bit positions */ -/* PORT_SRLEN Predefined. */ -/* PORT_SRLEN Predefined. */ - -/* PORT_INVEN Predefined. */ -/* PORT_INVEN Predefined. */ - -/* PORT_OPC Predefined. */ -/* PORT_OPC Predefined. */ - -/* PORT_ISC Predefined. */ -/* PORT_ISC Predefined. */ - -/* PORT.PIN7CTRL bit masks and bit positions */ -/* PORT_SRLEN Predefined. */ -/* PORT_SRLEN Predefined. */ - -/* PORT_INVEN Predefined. */ -/* PORT_INVEN Predefined. */ - -/* PORT_OPC Predefined. */ -/* PORT_OPC Predefined. */ - -/* PORT_ISC Predefined. */ -/* PORT_ISC Predefined. */ - -/* TC - 16-bit Timer/Counter With PWM */ -/* TC0.CTRLA bit masks and bit positions */ -#define TC0_CLKSEL_gm 0x0F /* Clock Selection group mask. */ -#define TC0_CLKSEL_gp 0 /* Clock Selection group position. */ -#define TC0_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ -#define TC0_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ -#define TC0_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ -#define TC0_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ -#define TC0_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ -#define TC0_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ -#define TC0_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ -#define TC0_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ - -/* TC0.CTRLB bit masks and bit positions */ -#define TC0_CCDEN_bm 0x80 /* Compare or Capture D Enable bit mask. */ -#define TC0_CCDEN_bp 7 /* Compare or Capture D Enable bit position. */ - -#define TC0_CCCEN_bm 0x40 /* Compare or Capture C Enable bit mask. */ -#define TC0_CCCEN_bp 6 /* Compare or Capture C Enable bit position. */ - -#define TC0_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ -#define TC0_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ - -#define TC0_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ -#define TC0_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ - -#define TC0_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ -#define TC0_WGMODE_gp 0 /* Waveform generation mode group position. */ -#define TC0_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ -#define TC0_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ -#define TC0_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ -#define TC0_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ -#define TC0_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ -#define TC0_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ - -/* TC0.CTRLC bit masks and bit positions */ -#define TC0_CMPD_bm 0x08 /* Compare D Output Value bit mask. */ -#define TC0_CMPD_bp 3 /* Compare D Output Value bit position. */ - -#define TC0_CMPC_bm 0x04 /* Compare C Output Value bit mask. */ -#define TC0_CMPC_bp 2 /* Compare C Output Value bit position. */ - -#define TC0_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ -#define TC0_CMPB_bp 1 /* Compare B Output Value bit position. */ - -#define TC0_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ -#define TC0_CMPA_bp 0 /* Compare A Output Value bit position. */ - -/* TC0.CTRLD bit masks and bit positions */ -#define TC0_EVACT_gm 0xE0 /* Event Action group mask. */ -#define TC0_EVACT_gp 5 /* Event Action group position. */ -#define TC0_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ -#define TC0_EVACT0_bp 5 /* Event Action bit 0 position. */ -#define TC0_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ -#define TC0_EVACT1_bp 6 /* Event Action bit 1 position. */ -#define TC0_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ -#define TC0_EVACT2_bp 7 /* Event Action bit 2 position. */ - -#define TC0_EVDLY_bm 0x10 /* Event Delay bit mask. */ -#define TC0_EVDLY_bp 4 /* Event Delay bit position. */ - -#define TC0_EVSEL_gm 0x0F /* Event Source Select group mask. */ -#define TC0_EVSEL_gp 0 /* Event Source Select group position. */ -#define TC0_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ -#define TC0_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ -#define TC0_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ -#define TC0_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ -#define TC0_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ -#define TC0_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ -#define TC0_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ -#define TC0_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ - -/* TC0.CTRLE bit masks and bit positions */ -#define TC0_BYTEM_gm 0x03 /* Byte Mode group mask. */ -#define TC0_BYTEM_gp 0 /* Byte Mode group position. */ -#define TC0_BYTEM0_bm (1<<0) /* Byte Mode bit 0 mask. */ -#define TC0_BYTEM0_bp 0 /* Byte Mode bit 0 position. */ -#define TC0_BYTEM1_bm (1<<1) /* Byte Mode bit 1 mask. */ -#define TC0_BYTEM1_bp 1 /* Byte Mode bit 1 position. */ - -/* TC0.INTCTRLA bit masks and bit positions */ -#define TC0_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ -#define TC0_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ -#define TC0_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ -#define TC0_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ -#define TC0_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ -#define TC0_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ - -#define TC0_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ -#define TC0_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ -#define TC0_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ -#define TC0_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ -#define TC0_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ -#define TC0_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ - -/* TC0.INTCTRLB bit masks and bit positions */ -#define TC0_CCDINTLVL_gm 0xC0 /* Compare or Capture D Interrupt Level group mask. */ -#define TC0_CCDINTLVL_gp 6 /* Compare or Capture D Interrupt Level group position. */ -#define TC0_CCDINTLVL0_bm (1<<6) /* Compare or Capture D Interrupt Level bit 0 mask. */ -#define TC0_CCDINTLVL0_bp 6 /* Compare or Capture D Interrupt Level bit 0 position. */ -#define TC0_CCDINTLVL1_bm (1<<7) /* Compare or Capture D Interrupt Level bit 1 mask. */ -#define TC0_CCDINTLVL1_bp 7 /* Compare or Capture D Interrupt Level bit 1 position. */ - -#define TC0_CCCINTLVL_gm 0x30 /* Compare or Capture C Interrupt Level group mask. */ -#define TC0_CCCINTLVL_gp 4 /* Compare or Capture C Interrupt Level group position. */ -#define TC0_CCCINTLVL0_bm (1<<4) /* Compare or Capture C Interrupt Level bit 0 mask. */ -#define TC0_CCCINTLVL0_bp 4 /* Compare or Capture C Interrupt Level bit 0 position. */ -#define TC0_CCCINTLVL1_bm (1<<5) /* Compare or Capture C Interrupt Level bit 1 mask. */ -#define TC0_CCCINTLVL1_bp 5 /* Compare or Capture C Interrupt Level bit 1 position. */ - -#define TC0_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ -#define TC0_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ -#define TC0_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ -#define TC0_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ -#define TC0_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ -#define TC0_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ - -#define TC0_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ -#define TC0_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ -#define TC0_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ -#define TC0_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ -#define TC0_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ -#define TC0_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ - -/* TC0.CTRLFCLR bit masks and bit positions */ -#define TC0_CMD_gm 0x0C /* Command group mask. */ -#define TC0_CMD_gp 2 /* Command group position. */ -#define TC0_CMD0_bm (1<<2) /* Command bit 0 mask. */ -#define TC0_CMD0_bp 2 /* Command bit 0 position. */ -#define TC0_CMD1_bm (1<<3) /* Command bit 1 mask. */ -#define TC0_CMD1_bp 3 /* Command bit 1 position. */ - -#define TC0_LUPD_bm 0x02 /* Lock Update bit mask. */ -#define TC0_LUPD_bp 1 /* Lock Update bit position. */ - -#define TC0_DIR_bm 0x01 /* Direction bit mask. */ -#define TC0_DIR_bp 0 /* Direction bit position. */ - -/* TC0.CTRLFSET bit masks and bit positions */ -/* TC0_CMD Predefined. */ -/* TC0_CMD Predefined. */ - -/* TC0_LUPD Predefined. */ -/* TC0_LUPD Predefined. */ - -/* TC0_DIR Predefined. */ -/* TC0_DIR Predefined. */ - -/* TC0.CTRLGCLR bit masks and bit positions */ -#define TC0_CCDBV_bm 0x10 /* Compare or Capture D Buffer Valid bit mask. */ -#define TC0_CCDBV_bp 4 /* Compare or Capture D Buffer Valid bit position. */ - -#define TC0_CCCBV_bm 0x08 /* Compare or Capture C Buffer Valid bit mask. */ -#define TC0_CCCBV_bp 3 /* Compare or Capture C Buffer Valid bit position. */ - -#define TC0_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ -#define TC0_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ - -#define TC0_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ -#define TC0_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ - -#define TC0_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ -#define TC0_PERBV_bp 0 /* Period Buffer Valid bit position. */ - -/* TC0.CTRLGSET bit masks and bit positions */ -/* TC0_CCDBV Predefined. */ -/* TC0_CCDBV Predefined. */ - -/* TC0_CCCBV Predefined. */ -/* TC0_CCCBV Predefined. */ - -/* TC0_CCBBV Predefined. */ -/* TC0_CCBBV Predefined. */ - -/* TC0_CCABV Predefined. */ -/* TC0_CCABV Predefined. */ - -/* TC0_PERBV Predefined. */ -/* TC0_PERBV Predefined. */ - -/* TC0.INTFLAGS bit masks and bit positions */ -#define TC0_CCDIF_bm 0x80 /* Compare or Capture D Interrupt Flag bit mask. */ -#define TC0_CCDIF_bp 7 /* Compare or Capture D Interrupt Flag bit position. */ - -#define TC0_CCCIF_bm 0x40 /* Compare or Capture C Interrupt Flag bit mask. */ -#define TC0_CCCIF_bp 6 /* Compare or Capture C Interrupt Flag bit position. */ - -#define TC0_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ -#define TC0_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ - -#define TC0_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ -#define TC0_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ - -#define TC0_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ -#define TC0_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ - -#define TC0_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ -#define TC0_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ - -/* TC1.CTRLA bit masks and bit positions */ -#define TC1_CLKSEL_gm 0x0F /* Clock Selection group mask. */ -#define TC1_CLKSEL_gp 0 /* Clock Selection group position. */ -#define TC1_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ -#define TC1_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ -#define TC1_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ -#define TC1_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ -#define TC1_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ -#define TC1_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ -#define TC1_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ -#define TC1_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ - -/* TC1.CTRLB bit masks and bit positions */ -#define TC1_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ -#define TC1_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ - -#define TC1_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ -#define TC1_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ - -#define TC1_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ -#define TC1_WGMODE_gp 0 /* Waveform generation mode group position. */ -#define TC1_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ -#define TC1_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ -#define TC1_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ -#define TC1_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ -#define TC1_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ -#define TC1_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ - -/* TC1.CTRLC bit masks and bit positions */ -#define TC1_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ -#define TC1_CMPB_bp 1 /* Compare B Output Value bit position. */ - -#define TC1_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ -#define TC1_CMPA_bp 0 /* Compare A Output Value bit position. */ - -/* TC1.CTRLD bit masks and bit positions */ -#define TC1_EVACT_gm 0xE0 /* Event Action group mask. */ -#define TC1_EVACT_gp 5 /* Event Action group position. */ -#define TC1_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ -#define TC1_EVACT0_bp 5 /* Event Action bit 0 position. */ -#define TC1_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ -#define TC1_EVACT1_bp 6 /* Event Action bit 1 position. */ -#define TC1_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ -#define TC1_EVACT2_bp 7 /* Event Action bit 2 position. */ - -#define TC1_EVDLY_bm 0x10 /* Event Delay bit mask. */ -#define TC1_EVDLY_bp 4 /* Event Delay bit position. */ - -#define TC1_EVSEL_gm 0x0F /* Event Source Select group mask. */ -#define TC1_EVSEL_gp 0 /* Event Source Select group position. */ -#define TC1_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ -#define TC1_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ -#define TC1_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ -#define TC1_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ -#define TC1_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ -#define TC1_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ -#define TC1_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ -#define TC1_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ - -/* TC1.CTRLE bit masks and bit positions */ -#define TC1_BYTEM_bm 0x01 /* Byte Mode bit mask. */ -#define TC1_BYTEM_bp 0 /* Byte Mode bit position. */ - -/* TC1.INTCTRLA bit masks and bit positions */ -#define TC1_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ -#define TC1_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ -#define TC1_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ -#define TC1_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ -#define TC1_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ -#define TC1_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ - -#define TC1_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ -#define TC1_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ -#define TC1_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ -#define TC1_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ -#define TC1_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ -#define TC1_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ - -/* TC1.INTCTRLB bit masks and bit positions */ -#define TC1_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ -#define TC1_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ -#define TC1_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ -#define TC1_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ -#define TC1_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ -#define TC1_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ - -#define TC1_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ -#define TC1_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ -#define TC1_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ -#define TC1_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ -#define TC1_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ -#define TC1_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ - -/* TC1.CTRLFCLR bit masks and bit positions */ -#define TC1_CMD_gm 0x0C /* Command group mask. */ -#define TC1_CMD_gp 2 /* Command group position. */ -#define TC1_CMD0_bm (1<<2) /* Command bit 0 mask. */ -#define TC1_CMD0_bp 2 /* Command bit 0 position. */ -#define TC1_CMD1_bm (1<<3) /* Command bit 1 mask. */ -#define TC1_CMD1_bp 3 /* Command bit 1 position. */ - -#define TC1_LUPD_bm 0x02 /* Lock Update bit mask. */ -#define TC1_LUPD_bp 1 /* Lock Update bit position. */ - -#define TC1_DIR_bm 0x01 /* Direction bit mask. */ -#define TC1_DIR_bp 0 /* Direction bit position. */ - -/* TC1.CTRLFSET bit masks and bit positions */ -/* TC1_CMD Predefined. */ -/* TC1_CMD Predefined. */ - -/* TC1_LUPD Predefined. */ -/* TC1_LUPD Predefined. */ - -/* TC1_DIR Predefined. */ -/* TC1_DIR Predefined. */ - -/* TC1.CTRLGCLR bit masks and bit positions */ -#define TC1_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ -#define TC1_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ - -#define TC1_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ -#define TC1_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ - -#define TC1_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ -#define TC1_PERBV_bp 0 /* Period Buffer Valid bit position. */ - -/* TC1.CTRLGSET bit masks and bit positions */ -/* TC1_CCBBV Predefined. */ -/* TC1_CCBBV Predefined. */ - -/* TC1_CCABV Predefined. */ -/* TC1_CCABV Predefined. */ - -/* TC1_PERBV Predefined. */ -/* TC1_PERBV Predefined. */ - -/* TC1.INTFLAGS bit masks and bit positions */ -#define TC1_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ -#define TC1_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ - -#define TC1_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ -#define TC1_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ - -#define TC1_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ -#define TC1_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ - -#define TC1_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ -#define TC1_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ - -/* TC2 - 16-bit Timer/Counter type 2 */ -/* TC2.CTRLA bit masks and bit positions */ -#define TC2_CLKSEL_gm 0x0F /* Clock Selection group mask. */ -#define TC2_CLKSEL_gp 0 /* Clock Selection group position. */ -#define TC2_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ -#define TC2_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ -#define TC2_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ -#define TC2_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ -#define TC2_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ -#define TC2_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ -#define TC2_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ -#define TC2_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ - -/* TC2.CTRLB bit masks and bit positions */ -#define TC2_HCMPDEN_bm 0x80 /* High Byte Compare D Enable bit mask. */ -#define TC2_HCMPDEN_bp 7 /* High Byte Compare D Enable bit position. */ - -#define TC2_HCMPCEN_bm 0x40 /* High Byte Compare C Enable bit mask. */ -#define TC2_HCMPCEN_bp 6 /* High Byte Compare C Enable bit position. */ - -#define TC2_HCMPBEN_bm 0x20 /* High Byte Compare B Enable bit mask. */ -#define TC2_HCMPBEN_bp 5 /* High Byte Compare B Enable bit position. */ - -#define TC2_HCMPAEN_bm 0x10 /* High Byte Compare A Enable bit mask. */ -#define TC2_HCMPAEN_bp 4 /* High Byte Compare A Enable bit position. */ - -#define TC2_LCMPDEN_bm 0x08 /* Low Byte Compare D Enable bit mask. */ -#define TC2_LCMPDEN_bp 3 /* Low Byte Compare D Enable bit position. */ - -#define TC2_LCMPCEN_bm 0x04 /* Low Byte Compare C Enable bit mask. */ -#define TC2_LCMPCEN_bp 2 /* Low Byte Compare C Enable bit position. */ - -#define TC2_LCMPBEN_bm 0x02 /* Low Byte Compare B Enable bit mask. */ -#define TC2_LCMPBEN_bp 1 /* Low Byte Compare B Enable bit position. */ - -#define TC2_LCMPAEN_bm 0x01 /* Low Byte Compare A Enable bit mask. */ -#define TC2_LCMPAEN_bp 0 /* Low Byte Compare A Enable bit position. */ - -/* TC2.CTRLC bit masks and bit positions */ -#define TC2_HCMPD_bm 0x80 /* High Byte Compare D Output Value bit mask. */ -#define TC2_HCMPD_bp 7 /* High Byte Compare D Output Value bit position. */ - -#define TC2_HCMPC_bm 0x40 /* High Byte Compare C Output Value bit mask. */ -#define TC2_HCMPC_bp 6 /* High Byte Compare C Output Value bit position. */ - -#define TC2_HCMPB_bm 0x20 /* High Byte Compare B Output Value bit mask. */ -#define TC2_HCMPB_bp 5 /* High Byte Compare B Output Value bit position. */ - -#define TC2_HCMPA_bm 0x10 /* High Byte Compare A Output Value bit mask. */ -#define TC2_HCMPA_bp 4 /* High Byte Compare A Output Value bit position. */ - -#define TC2_LCMPD_bm 0x08 /* Low Byte Compare D Output Value bit mask. */ -#define TC2_LCMPD_bp 3 /* Low Byte Compare D Output Value bit position. */ - -#define TC2_LCMPC_bm 0x04 /* Low Byte Compare C Output Value bit mask. */ -#define TC2_LCMPC_bp 2 /* Low Byte Compare C Output Value bit position. */ - -#define TC2_LCMPB_bm 0x02 /* Low Byte Compare B Output Value bit mask. */ -#define TC2_LCMPB_bp 1 /* Low Byte Compare B Output Value bit position. */ - -#define TC2_LCMPA_bm 0x01 /* Low Byte Compare A Output Value bit mask. */ -#define TC2_LCMPA_bp 0 /* Low Byte Compare A Output Value bit position. */ - -/* TC2.CTRLE bit masks and bit positions */ -#define TC2_BYTEM_gm 0x03 /* Byte Mode group mask. */ -#define TC2_BYTEM_gp 0 /* Byte Mode group position. */ -#define TC2_BYTEM0_bm (1<<0) /* Byte Mode bit 0 mask. */ -#define TC2_BYTEM0_bp 0 /* Byte Mode bit 0 position. */ -#define TC2_BYTEM1_bm (1<<1) /* Byte Mode bit 1 mask. */ -#define TC2_BYTEM1_bp 1 /* Byte Mode bit 1 position. */ - -/* TC2.INTCTRLA bit masks and bit positions */ -#define TC2_HUNFINTLVL_gm 0x0C /* High Byte Underflow Interrupt Level group mask. */ -#define TC2_HUNFINTLVL_gp 2 /* High Byte Underflow Interrupt Level group position. */ -#define TC2_HUNFINTLVL0_bm (1<<2) /* High Byte Underflow Interrupt Level bit 0 mask. */ -#define TC2_HUNFINTLVL0_bp 2 /* High Byte Underflow Interrupt Level bit 0 position. */ -#define TC2_HUNFINTLVL1_bm (1<<3) /* High Byte Underflow Interrupt Level bit 1 mask. */ -#define TC2_HUNFINTLVL1_bp 3 /* High Byte Underflow Interrupt Level bit 1 position. */ - -#define TC2_LUNFINTLVL_gm 0x03 /* Low Byte Underflow interrupt level group mask. */ -#define TC2_LUNFINTLVL_gp 0 /* Low Byte Underflow interrupt level group position. */ -#define TC2_LUNFINTLVL0_bm (1<<0) /* Low Byte Underflow interrupt level bit 0 mask. */ -#define TC2_LUNFINTLVL0_bp 0 /* Low Byte Underflow interrupt level bit 0 position. */ -#define TC2_LUNFINTLVL1_bm (1<<1) /* Low Byte Underflow interrupt level bit 1 mask. */ -#define TC2_LUNFINTLVL1_bp 1 /* Low Byte Underflow interrupt level bit 1 position. */ - -/* TC2.INTCTRLB bit masks and bit positions */ -#define TC2_LCMPDINTLVL_gm 0xC0 /* Low Byte Compare D Interrupt Level group mask. */ -#define TC2_LCMPDINTLVL_gp 6 /* Low Byte Compare D Interrupt Level group position. */ -#define TC2_LCMPDINTLVL0_bm (1<<6) /* Low Byte Compare D Interrupt Level bit 0 mask. */ -#define TC2_LCMPDINTLVL0_bp 6 /* Low Byte Compare D Interrupt Level bit 0 position. */ -#define TC2_LCMPDINTLVL1_bm (1<<7) /* Low Byte Compare D Interrupt Level bit 1 mask. */ -#define TC2_LCMPDINTLVL1_bp 7 /* Low Byte Compare D Interrupt Level bit 1 position. */ - -#define TC2_LCMPCINTLVL_gm 0x30 /* Low Byte Compare C Interrupt Level group mask. */ -#define TC2_LCMPCINTLVL_gp 4 /* Low Byte Compare C Interrupt Level group position. */ -#define TC2_LCMPCINTLVL0_bm (1<<4) /* Low Byte Compare C Interrupt Level bit 0 mask. */ -#define TC2_LCMPCINTLVL0_bp 4 /* Low Byte Compare C Interrupt Level bit 0 position. */ -#define TC2_LCMPCINTLVL1_bm (1<<5) /* Low Byte Compare C Interrupt Level bit 1 mask. */ -#define TC2_LCMPCINTLVL1_bp 5 /* Low Byte Compare C Interrupt Level bit 1 position. */ - -#define TC2_LCMPBINTLVL_gm 0x0C /* Low Byte Compare B Interrupt Level group mask. */ -#define TC2_LCMPBINTLVL_gp 2 /* Low Byte Compare B Interrupt Level group position. */ -#define TC2_LCMPBINTLVL0_bm (1<<2) /* Low Byte Compare B Interrupt Level bit 0 mask. */ -#define TC2_LCMPBINTLVL0_bp 2 /* Low Byte Compare B Interrupt Level bit 0 position. */ -#define TC2_LCMPBINTLVL1_bm (1<<3) /* Low Byte Compare B Interrupt Level bit 1 mask. */ -#define TC2_LCMPBINTLVL1_bp 3 /* Low Byte Compare B Interrupt Level bit 1 position. */ - -#define TC2_LCMPAINTLVL_gm 0x03 /* Low Byte Compare A Interrupt Level group mask. */ -#define TC2_LCMPAINTLVL_gp 0 /* Low Byte Compare A Interrupt Level group position. */ -#define TC2_LCMPAINTLVL0_bm (1<<0) /* Low Byte Compare A Interrupt Level bit 0 mask. */ -#define TC2_LCMPAINTLVL0_bp 0 /* Low Byte Compare A Interrupt Level bit 0 position. */ -#define TC2_LCMPAINTLVL1_bm (1<<1) /* Low Byte Compare A Interrupt Level bit 1 mask. */ -#define TC2_LCMPAINTLVL1_bp 1 /* Low Byte Compare A Interrupt Level bit 1 position. */ - -/* TC2.CTRLF bit masks and bit positions */ -#define TC2_CMD_gm 0x0C /* Command group mask. */ -#define TC2_CMD_gp 2 /* Command group position. */ -#define TC2_CMD0_bm (1<<2) /* Command bit 0 mask. */ -#define TC2_CMD0_bp 2 /* Command bit 0 position. */ -#define TC2_CMD1_bm (1<<3) /* Command bit 1 mask. */ -#define TC2_CMD1_bp 3 /* Command bit 1 position. */ - -#define TC2_CMDEN_gm 0x03 /* Command Enable group mask. */ -#define TC2_CMDEN_gp 0 /* Command Enable group position. */ -#define TC2_CMDEN0_bm (1<<0) /* Command Enable bit 0 mask. */ -#define TC2_CMDEN0_bp 0 /* Command Enable bit 0 position. */ -#define TC2_CMDEN1_bm (1<<1) /* Command Enable bit 1 mask. */ -#define TC2_CMDEN1_bp 1 /* Command Enable bit 1 position. */ - -/* TC2.INTFLAGS bit masks and bit positions */ -#define TC2_LCMPDIF_bm 0x80 /* Low Byte Compare D Interrupt Flag bit mask. */ -#define TC2_LCMPDIF_bp 7 /* Low Byte Compare D Interrupt Flag bit position. */ - -#define TC2_LCMPCIF_bm 0x40 /* Low Byte Compare C Interrupt Flag bit mask. */ -#define TC2_LCMPCIF_bp 6 /* Low Byte Compare C Interrupt Flag bit position. */ - -#define TC2_LCMPBIF_bm 0x20 /* Low Byte Compare B Interrupt Flag bit mask. */ -#define TC2_LCMPBIF_bp 5 /* Low Byte Compare B Interrupt Flag bit position. */ - -#define TC2_LCMPAIF_bm 0x10 /* Low Byte Compare A Interrupt Flag bit mask. */ -#define TC2_LCMPAIF_bp 4 /* Low Byte Compare A Interrupt Flag bit position. */ - -#define TC2_HUNFIF_bm 0x02 /* High Byte Underflow Interrupt Flag bit mask. */ -#define TC2_HUNFIF_bp 1 /* High Byte Underflow Interrupt Flag bit position. */ - -#define TC2_LUNFIF_bm 0x01 /* Low Byte Underflow Interrupt Flag bit mask. */ -#define TC2_LUNFIF_bp 0 /* Low Byte Underflow Interrupt Flag bit position. */ - -/* AWEX - Timer/Counter Advanced Waveform Extension */ -/* AWEX.CTRL bit masks and bit positions */ -#define AWEX_PGM_bm 0x20 /* Pattern Generation Mode bit mask. */ -#define AWEX_PGM_bp 5 /* Pattern Generation Mode bit position. */ - -#define AWEX_CWCM_bm 0x10 /* Common Waveform Channel Mode bit mask. */ -#define AWEX_CWCM_bp 4 /* Common Waveform Channel Mode bit position. */ - -#define AWEX_DTICCDEN_bm 0x08 /* Dead Time Insertion Compare Channel D Enable bit mask. */ -#define AWEX_DTICCDEN_bp 3 /* Dead Time Insertion Compare Channel D Enable bit position. */ - -#define AWEX_DTICCCEN_bm 0x04 /* Dead Time Insertion Compare Channel C Enable bit mask. */ -#define AWEX_DTICCCEN_bp 2 /* Dead Time Insertion Compare Channel C Enable bit position. */ - -#define AWEX_DTICCBEN_bm 0x02 /* Dead Time Insertion Compare Channel B Enable bit mask. */ -#define AWEX_DTICCBEN_bp 1 /* Dead Time Insertion Compare Channel B Enable bit position. */ - -#define AWEX_DTICCAEN_bm 0x01 /* Dead Time Insertion Compare Channel A Enable bit mask. */ -#define AWEX_DTICCAEN_bp 0 /* Dead Time Insertion Compare Channel A Enable bit position. */ - -/* AWEX.FDCTRL bit masks and bit positions */ -#define AWEX_FDDBD_bm 0x10 /* Fault Detect on Disable Break Disable bit mask. */ -#define AWEX_FDDBD_bp 4 /* Fault Detect on Disable Break Disable bit position. */ - -#define AWEX_FDMODE_bm 0x04 /* Fault Detect Mode bit mask. */ -#define AWEX_FDMODE_bp 2 /* Fault Detect Mode bit position. */ - -#define AWEX_FDACT_gm 0x03 /* Fault Detect Action group mask. */ -#define AWEX_FDACT_gp 0 /* Fault Detect Action group position. */ -#define AWEX_FDACT0_bm (1<<0) /* Fault Detect Action bit 0 mask. */ -#define AWEX_FDACT0_bp 0 /* Fault Detect Action bit 0 position. */ -#define AWEX_FDACT1_bm (1<<1) /* Fault Detect Action bit 1 mask. */ -#define AWEX_FDACT1_bp 1 /* Fault Detect Action bit 1 position. */ - -/* AWEX.STATUS bit masks and bit positions */ -#define AWEX_FDF_bm 0x04 /* Fault Detect Flag bit mask. */ -#define AWEX_FDF_bp 2 /* Fault Detect Flag bit position. */ - -#define AWEX_DTHSBUFV_bm 0x02 /* Dead Time High Side Buffer Valid bit mask. */ -#define AWEX_DTHSBUFV_bp 1 /* Dead Time High Side Buffer Valid bit position. */ - -#define AWEX_DTLSBUFV_bm 0x01 /* Dead Time Low Side Buffer Valid bit mask. */ -#define AWEX_DTLSBUFV_bp 0 /* Dead Time Low Side Buffer Valid bit position. */ - -/* AWEX.STATUSSET bit masks and bit positions */ -/* AWEX_FDF Predefined. */ -/* AWEX_FDF Predefined. */ - -/* AWEX_DTHSBUFV Predefined. */ -/* AWEX_DTHSBUFV Predefined. */ - -/* AWEX_DTLSBUFV Predefined. */ -/* AWEX_DTLSBUFV Predefined. */ - -/* HIRES - Timer/Counter High-Resolution Extension */ -/* HIRES.CTRLA bit masks and bit positions */ -#define HIRES_HREN_gm 0x03 /* High Resolution Enable group mask. */ -#define HIRES_HREN_gp 0 /* High Resolution Enable group position. */ -#define HIRES_HREN0_bm (1<<0) /* High Resolution Enable bit 0 mask. */ -#define HIRES_HREN0_bp 0 /* High Resolution Enable bit 0 position. */ -#define HIRES_HREN1_bm (1<<1) /* High Resolution Enable bit 1 mask. */ -#define HIRES_HREN1_bp 1 /* High Resolution Enable bit 1 position. */ - -/* USART - Universal Asynchronous Receiver-Transmitter */ -/* USART.STATUS bit masks and bit positions */ -#define USART_RXCIF_bm 0x80 /* Receive Interrupt Flag bit mask. */ -#define USART_RXCIF_bp 7 /* Receive Interrupt Flag bit position. */ - -#define USART_TXCIF_bm 0x40 /* Transmit Interrupt Flag bit mask. */ -#define USART_TXCIF_bp 6 /* Transmit Interrupt Flag bit position. */ - -#define USART_DREIF_bm 0x20 /* Data Register Empty Flag bit mask. */ -#define USART_DREIF_bp 5 /* Data Register Empty Flag bit position. */ - -#define USART_FERR_bm 0x10 /* Frame Error bit mask. */ -#define USART_FERR_bp 4 /* Frame Error bit position. */ - -#define USART_BUFOVF_bm 0x08 /* Buffer Overflow bit mask. */ -#define USART_BUFOVF_bp 3 /* Buffer Overflow bit position. */ - -#define USART_PERR_bm 0x04 /* Parity Error bit mask. */ -#define USART_PERR_bp 2 /* Parity Error bit position. */ - -#define USART_RXB8_bm 0x01 /* Receive Bit 8 bit mask. */ -#define USART_RXB8_bp 0 /* Receive Bit 8 bit position. */ - -/* USART.CTRLA bit masks and bit positions */ -#define USART_RXCINTLVL_gm 0x30 /* Receive Interrupt Level group mask. */ -#define USART_RXCINTLVL_gp 4 /* Receive Interrupt Level group position. */ -#define USART_RXCINTLVL0_bm (1<<4) /* Receive Interrupt Level bit 0 mask. */ -#define USART_RXCINTLVL0_bp 4 /* Receive Interrupt Level bit 0 position. */ -#define USART_RXCINTLVL1_bm (1<<5) /* Receive Interrupt Level bit 1 mask. */ -#define USART_RXCINTLVL1_bp 5 /* Receive Interrupt Level bit 1 position. */ - -#define USART_TXCINTLVL_gm 0x0C /* Transmit Interrupt Level group mask. */ -#define USART_TXCINTLVL_gp 2 /* Transmit Interrupt Level group position. */ -#define USART_TXCINTLVL0_bm (1<<2) /* Transmit Interrupt Level bit 0 mask. */ -#define USART_TXCINTLVL0_bp 2 /* Transmit Interrupt Level bit 0 position. */ -#define USART_TXCINTLVL1_bm (1<<3) /* Transmit Interrupt Level bit 1 mask. */ -#define USART_TXCINTLVL1_bp 3 /* Transmit Interrupt Level bit 1 position. */ - -#define USART_DREINTLVL_gm 0x03 /* Data Register Empty Interrupt Level group mask. */ -#define USART_DREINTLVL_gp 0 /* Data Register Empty Interrupt Level group position. */ -#define USART_DREINTLVL0_bm (1<<0) /* Data Register Empty Interrupt Level bit 0 mask. */ -#define USART_DREINTLVL0_bp 0 /* Data Register Empty Interrupt Level bit 0 position. */ -#define USART_DREINTLVL1_bm (1<<1) /* Data Register Empty Interrupt Level bit 1 mask. */ -#define USART_DREINTLVL1_bp 1 /* Data Register Empty Interrupt Level bit 1 position. */ - -/* USART.CTRLB bit masks and bit positions */ -#define USART_RXEN_bm 0x10 /* Receiver Enable bit mask. */ -#define USART_RXEN_bp 4 /* Receiver Enable bit position. */ - -#define USART_TXEN_bm 0x08 /* Transmitter Enable bit mask. */ -#define USART_TXEN_bp 3 /* Transmitter Enable bit position. */ - -#define USART_CLK2X_bm 0x04 /* Double transmission speed bit mask. */ -#define USART_CLK2X_bp 2 /* Double transmission speed bit position. */ - -#define USART_MPCM_bm 0x02 /* Multi-processor Communication Mode bit mask. */ -#define USART_MPCM_bp 1 /* Multi-processor Communication Mode bit position. */ - -#define USART_TXB8_bm 0x01 /* Transmit bit 8 bit mask. */ -#define USART_TXB8_bp 0 /* Transmit bit 8 bit position. */ - -/* USART.CTRLC bit masks and bit positions */ -#define USART_CMODE_gm 0xC0 /* Communication Mode group mask. */ -#define USART_CMODE_gp 6 /* Communication Mode group position. */ -#define USART_CMODE0_bm (1<<6) /* Communication Mode bit 0 mask. */ -#define USART_CMODE0_bp 6 /* Communication Mode bit 0 position. */ -#define USART_CMODE1_bm (1<<7) /* Communication Mode bit 1 mask. */ -#define USART_CMODE1_bp 7 /* Communication Mode bit 1 position. */ - -#define USART_PMODE_gm 0x30 /* Parity Mode group mask. */ -#define USART_PMODE_gp 4 /* Parity Mode group position. */ -#define USART_PMODE0_bm (1<<4) /* Parity Mode bit 0 mask. */ -#define USART_PMODE0_bp 4 /* Parity Mode bit 0 position. */ -#define USART_PMODE1_bm (1<<5) /* Parity Mode bit 1 mask. */ -#define USART_PMODE1_bp 5 /* Parity Mode bit 1 position. */ - -#define USART_SBMODE_bm 0x08 /* Stop Bit Mode bit mask. */ -#define USART_SBMODE_bp 3 /* Stop Bit Mode bit position. */ - -#define USART_CHSIZE_gm 0x07 /* Character Size group mask. */ -#define USART_CHSIZE_gp 0 /* Character Size group position. */ -#define USART_CHSIZE0_bm (1<<0) /* Character Size bit 0 mask. */ -#define USART_CHSIZE0_bp 0 /* Character Size bit 0 position. */ -#define USART_CHSIZE1_bm (1<<1) /* Character Size bit 1 mask. */ -#define USART_CHSIZE1_bp 1 /* Character Size bit 1 position. */ -#define USART_CHSIZE2_bm (1<<2) /* Character Size bit 2 mask. */ -#define USART_CHSIZE2_bp 2 /* Character Size bit 2 position. */ - -/* USART.BAUDCTRLA bit masks and bit positions */ -#define USART_BSEL_gm 0xFF /* Baud Rate Selection Bits [7:0] group mask. */ -#define USART_BSEL_gp 0 /* Baud Rate Selection Bits [7:0] group position. */ -#define USART_BSEL0_bm (1<<0) /* Baud Rate Selection Bits [7:0] bit 0 mask. */ -#define USART_BSEL0_bp 0 /* Baud Rate Selection Bits [7:0] bit 0 position. */ -#define USART_BSEL1_bm (1<<1) /* Baud Rate Selection Bits [7:0] bit 1 mask. */ -#define USART_BSEL1_bp 1 /* Baud Rate Selection Bits [7:0] bit 1 position. */ -#define USART_BSEL2_bm (1<<2) /* Baud Rate Selection Bits [7:0] bit 2 mask. */ -#define USART_BSEL2_bp 2 /* Baud Rate Selection Bits [7:0] bit 2 position. */ -#define USART_BSEL3_bm (1<<3) /* Baud Rate Selection Bits [7:0] bit 3 mask. */ -#define USART_BSEL3_bp 3 /* Baud Rate Selection Bits [7:0] bit 3 position. */ -#define USART_BSEL4_bm (1<<4) /* Baud Rate Selection Bits [7:0] bit 4 mask. */ -#define USART_BSEL4_bp 4 /* Baud Rate Selection Bits [7:0] bit 4 position. */ -#define USART_BSEL5_bm (1<<5) /* Baud Rate Selection Bits [7:0] bit 5 mask. */ -#define USART_BSEL5_bp 5 /* Baud Rate Selection Bits [7:0] bit 5 position. */ -#define USART_BSEL6_bm (1<<6) /* Baud Rate Selection Bits [7:0] bit 6 mask. */ -#define USART_BSEL6_bp 6 /* Baud Rate Selection Bits [7:0] bit 6 position. */ -#define USART_BSEL7_bm (1<<7) /* Baud Rate Selection Bits [7:0] bit 7 mask. */ -#define USART_BSEL7_bp 7 /* Baud Rate Selection Bits [7:0] bit 7 position. */ - -/* USART.BAUDCTRLB bit masks and bit positions */ -#define USART_BSCALE_gm 0xF0 /* Baud Rate Scale group mask. */ -#define USART_BSCALE_gp 4 /* Baud Rate Scale group position. */ -#define USART_BSCALE0_bm (1<<4) /* Baud Rate Scale bit 0 mask. */ -#define USART_BSCALE0_bp 4 /* Baud Rate Scale bit 0 position. */ -#define USART_BSCALE1_bm (1<<5) /* Baud Rate Scale bit 1 mask. */ -#define USART_BSCALE1_bp 5 /* Baud Rate Scale bit 1 position. */ -#define USART_BSCALE2_bm (1<<6) /* Baud Rate Scale bit 2 mask. */ -#define USART_BSCALE2_bp 6 /* Baud Rate Scale bit 2 position. */ -#define USART_BSCALE3_bm (1<<7) /* Baud Rate Scale bit 3 mask. */ -#define USART_BSCALE3_bp 7 /* Baud Rate Scale bit 3 position. */ - -/* USART_BSEL Predefined. */ -/* USART_BSEL Predefined. */ - -/* SPI - Serial Peripheral Interface */ -/* SPI.CTRL bit masks and bit positions */ -#define SPI_CLK2X_bm 0x80 /* Enable Double Speed bit mask. */ -#define SPI_CLK2X_bp 7 /* Enable Double Speed bit position. */ - -#define SPI_ENABLE_bm 0x40 /* Enable Module bit mask. */ -#define SPI_ENABLE_bp 6 /* Enable Module bit position. */ - -#define SPI_DORD_bm 0x20 /* Data Order Setting bit mask. */ -#define SPI_DORD_bp 5 /* Data Order Setting bit position. */ - -#define SPI_MASTER_bm 0x10 /* Master Operation Enable bit mask. */ -#define SPI_MASTER_bp 4 /* Master Operation Enable bit position. */ - -#define SPI_MODE_gm 0x0C /* SPI Mode group mask. */ -#define SPI_MODE_gp 2 /* SPI Mode group position. */ -#define SPI_MODE0_bm (1<<2) /* SPI Mode bit 0 mask. */ -#define SPI_MODE0_bp 2 /* SPI Mode bit 0 position. */ -#define SPI_MODE1_bm (1<<3) /* SPI Mode bit 1 mask. */ -#define SPI_MODE1_bp 3 /* SPI Mode bit 1 position. */ - -#define SPI_PRESCALER_gm 0x03 /* Prescaler group mask. */ -#define SPI_PRESCALER_gp 0 /* Prescaler group position. */ -#define SPI_PRESCALER0_bm (1<<0) /* Prescaler bit 0 mask. */ -#define SPI_PRESCALER0_bp 0 /* Prescaler bit 0 position. */ -#define SPI_PRESCALER1_bm (1<<1) /* Prescaler bit 1 mask. */ -#define SPI_PRESCALER1_bp 1 /* Prescaler bit 1 position. */ - -/* SPI.INTCTRL bit masks and bit positions */ -#define SPI_INTLVL_gm 0x03 /* Interrupt level group mask. */ -#define SPI_INTLVL_gp 0 /* Interrupt level group position. */ -#define SPI_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */ -#define SPI_INTLVL0_bp 0 /* Interrupt level bit 0 position. */ -#define SPI_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */ -#define SPI_INTLVL1_bp 1 /* Interrupt level bit 1 position. */ - -/* SPI.STATUS bit masks and bit positions */ -#define SPI_IF_bm 0x80 /* Interrupt Flag bit mask. */ -#define SPI_IF_bp 7 /* Interrupt Flag bit position. */ - -#define SPI_WRCOL_bm 0x40 /* Write Collision bit mask. */ -#define SPI_WRCOL_bp 6 /* Write Collision bit position. */ - -/* IRCOM - IR Communication Module */ -/* IRCOM.CTRL bit masks and bit positions */ -#define IRCOM_EVSEL_gm 0x0F /* Event Channel Select group mask. */ -#define IRCOM_EVSEL_gp 0 /* Event Channel Select group position. */ -#define IRCOM_EVSEL0_bm (1<<0) /* Event Channel Select bit 0 mask. */ -#define IRCOM_EVSEL0_bp 0 /* Event Channel Select bit 0 position. */ -#define IRCOM_EVSEL1_bm (1<<1) /* Event Channel Select bit 1 mask. */ -#define IRCOM_EVSEL1_bp 1 /* Event Channel Select bit 1 position. */ -#define IRCOM_EVSEL2_bm (1<<2) /* Event Channel Select bit 2 mask. */ -#define IRCOM_EVSEL2_bp 2 /* Event Channel Select bit 2 position. */ -#define IRCOM_EVSEL3_bm (1<<3) /* Event Channel Select bit 3 mask. */ -#define IRCOM_EVSEL3_bp 3 /* Event Channel Select bit 3 position. */ - -/* FUSE - Fuses and Lockbits */ -/* NVM_FUSES.FUSEBYTE0 bit masks and bit positions */ -#define NVM_FUSES_JTAGUSERID_gm 0xFF /* JTAG User ID group mask. */ -#define NVM_FUSES_JTAGUSERID_gp 0 /* JTAG User ID group position. */ -#define NVM_FUSES_JTAGUSERID0_bm (1<<0) /* JTAG User ID bit 0 mask. */ -#define NVM_FUSES_JTAGUSERID0_bp 0 /* JTAG User ID bit 0 position. */ -#define NVM_FUSES_JTAGUSERID1_bm (1<<1) /* JTAG User ID bit 1 mask. */ -#define NVM_FUSES_JTAGUSERID1_bp 1 /* JTAG User ID bit 1 position. */ -#define NVM_FUSES_JTAGUSERID2_bm (1<<2) /* JTAG User ID bit 2 mask. */ -#define NVM_FUSES_JTAGUSERID2_bp 2 /* JTAG User ID bit 2 position. */ -#define NVM_FUSES_JTAGUSERID3_bm (1<<3) /* JTAG User ID bit 3 mask. */ -#define NVM_FUSES_JTAGUSERID3_bp 3 /* JTAG User ID bit 3 position. */ -#define NVM_FUSES_JTAGUSERID4_bm (1<<4) /* JTAG User ID bit 4 mask. */ -#define NVM_FUSES_JTAGUSERID4_bp 4 /* JTAG User ID bit 4 position. */ -#define NVM_FUSES_JTAGUSERID5_bm (1<<5) /* JTAG User ID bit 5 mask. */ -#define NVM_FUSES_JTAGUSERID5_bp 5 /* JTAG User ID bit 5 position. */ -#define NVM_FUSES_JTAGUSERID6_bm (1<<6) /* JTAG User ID bit 6 mask. */ -#define NVM_FUSES_JTAGUSERID6_bp 6 /* JTAG User ID bit 6 position. */ -#define NVM_FUSES_JTAGUSERID7_bm (1<<7) /* JTAG User ID bit 7 mask. */ -#define NVM_FUSES_JTAGUSERID7_bp 7 /* JTAG User ID bit 7 position. */ - -/* NVM_FUSES.FUSEBYTE1 bit masks and bit positions */ -#define NVM_FUSES_WDWP_gm 0xF0 /* Watchdog Window Timeout Period group mask. */ -#define NVM_FUSES_WDWP_gp 4 /* Watchdog Window Timeout Period group position. */ -#define NVM_FUSES_WDWP0_bm (1<<4) /* Watchdog Window Timeout Period bit 0 mask. */ -#define NVM_FUSES_WDWP0_bp 4 /* Watchdog Window Timeout Period bit 0 position. */ -#define NVM_FUSES_WDWP1_bm (1<<5) /* Watchdog Window Timeout Period bit 1 mask. */ -#define NVM_FUSES_WDWP1_bp 5 /* Watchdog Window Timeout Period bit 1 position. */ -#define NVM_FUSES_WDWP2_bm (1<<6) /* Watchdog Window Timeout Period bit 2 mask. */ -#define NVM_FUSES_WDWP2_bp 6 /* Watchdog Window Timeout Period bit 2 position. */ -#define NVM_FUSES_WDWP3_bm (1<<7) /* Watchdog Window Timeout Period bit 3 mask. */ -#define NVM_FUSES_WDWP3_bp 7 /* Watchdog Window Timeout Period bit 3 position. */ - -#define NVM_FUSES_WDP_gm 0x0F /* Watchdog Timeout Period group mask. */ -#define NVM_FUSES_WDP_gp 0 /* Watchdog Timeout Period group position. */ -#define NVM_FUSES_WDP0_bm (1<<0) /* Watchdog Timeout Period bit 0 mask. */ -#define NVM_FUSES_WDP0_bp 0 /* Watchdog Timeout Period bit 0 position. */ -#define NVM_FUSES_WDP1_bm (1<<1) /* Watchdog Timeout Period bit 1 mask. */ -#define NVM_FUSES_WDP1_bp 1 /* Watchdog Timeout Period bit 1 position. */ -#define NVM_FUSES_WDP2_bm (1<<2) /* Watchdog Timeout Period bit 2 mask. */ -#define NVM_FUSES_WDP2_bp 2 /* Watchdog Timeout Period bit 2 position. */ -#define NVM_FUSES_WDP3_bm (1<<3) /* Watchdog Timeout Period bit 3 mask. */ -#define NVM_FUSES_WDP3_bp 3 /* Watchdog Timeout Period bit 3 position. */ - -/* NVM_FUSES.FUSEBYTE2 bit masks and bit positions */ -#define NVM_FUSES_BOOTRST_bm 0x40 /* Boot Loader Section Reset Vector bit mask. */ -#define NVM_FUSES_BOOTRST_bp 6 /* Boot Loader Section Reset Vector bit position. */ - -#define NVM_FUSES_TOSCSEL_bm 0x20 /* Timer Oscillator pin location bit mask. */ -#define NVM_FUSES_TOSCSEL_bp 5 /* Timer Oscillator pin location bit position. */ - -#define NVM_FUSES_BODPD_gm 0x03 /* BOD Operation in Power-Down Mode group mask. */ -#define NVM_FUSES_BODPD_gp 0 /* BOD Operation in Power-Down Mode group position. */ -#define NVM_FUSES_BODPD0_bm (1<<0) /* BOD Operation in Power-Down Mode bit 0 mask. */ -#define NVM_FUSES_BODPD0_bp 0 /* BOD Operation in Power-Down Mode bit 0 position. */ -#define NVM_FUSES_BODPD1_bm (1<<1) /* BOD Operation in Power-Down Mode bit 1 mask. */ -#define NVM_FUSES_BODPD1_bp 1 /* BOD Operation in Power-Down Mode bit 1 position. */ - -/* NVM_FUSES.FUSEBYTE4 bit masks and bit positions */ -#define NVM_FUSES_RSTDISBL_bm 0x10 /* External Reset Disable bit mask. */ -#define NVM_FUSES_RSTDISBL_bp 4 /* External Reset Disable bit position. */ - -#define NVM_FUSES_SUT_gm 0x0C /* Start-up Time group mask. */ -#define NVM_FUSES_SUT_gp 2 /* Start-up Time group position. */ -#define NVM_FUSES_SUT0_bm (1<<2) /* Start-up Time bit 0 mask. */ -#define NVM_FUSES_SUT0_bp 2 /* Start-up Time bit 0 position. */ -#define NVM_FUSES_SUT1_bm (1<<3) /* Start-up Time bit 1 mask. */ -#define NVM_FUSES_SUT1_bp 3 /* Start-up Time bit 1 position. */ - -#define NVM_FUSES_WDLOCK_bm 0x02 /* Watchdog Timer Lock bit mask. */ -#define NVM_FUSES_WDLOCK_bp 1 /* Watchdog Timer Lock bit position. */ - -#define NVM_FUSES_JTAGEN_bm 0x01 /* JTAG Interface Enable bit mask. */ -#define NVM_FUSES_JTAGEN_bp 0 /* JTAG Interface Enable bit position. */ - -/* NVM_FUSES.FUSEBYTE5 bit masks and bit positions */ -#define NVM_FUSES_BODACT_gm 0x30 /* BOD Operation in Active Mode group mask. */ -#define NVM_FUSES_BODACT_gp 4 /* BOD Operation in Active Mode group position. */ -#define NVM_FUSES_BODACT0_bm (1<<4) /* BOD Operation in Active Mode bit 0 mask. */ -#define NVM_FUSES_BODACT0_bp 4 /* BOD Operation in Active Mode bit 0 position. */ -#define NVM_FUSES_BODACT1_bm (1<<5) /* BOD Operation in Active Mode bit 1 mask. */ -#define NVM_FUSES_BODACT1_bp 5 /* BOD Operation in Active Mode bit 1 position. */ - -#define NVM_FUSES_EESAVE_bm 0x08 /* Preserve EEPROM Through Chip Erase bit mask. */ -#define NVM_FUSES_EESAVE_bp 3 /* Preserve EEPROM Through Chip Erase bit position. */ - -#define NVM_FUSES_BODLVL_gm 0x07 /* Brownout Detection Voltage Level group mask. */ -#define NVM_FUSES_BODLVL_gp 0 /* Brownout Detection Voltage Level group position. */ -#define NVM_FUSES_BODLVL0_bm (1<<0) /* Brownout Detection Voltage Level bit 0 mask. */ -#define NVM_FUSES_BODLVL0_bp 0 /* Brownout Detection Voltage Level bit 0 position. */ -#define NVM_FUSES_BODLVL1_bm (1<<1) /* Brownout Detection Voltage Level bit 1 mask. */ -#define NVM_FUSES_BODLVL1_bp 1 /* Brownout Detection Voltage Level bit 1 position. */ -#define NVM_FUSES_BODLVL2_bm (1<<2) /* Brownout Detection Voltage Level bit 2 mask. */ -#define NVM_FUSES_BODLVL2_bp 2 /* Brownout Detection Voltage Level bit 2 position. */ - -/* LOCKBIT - Fuses and Lockbits */ -/* NVM_LOCKBITS.LOCKBITS bit masks and bit positions */ -#define NVM_LOCKBITS_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ -#define NVM_LOCKBITS_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ -#define NVM_LOCKBITS_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ -#define NVM_LOCKBITS_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ -#define NVM_LOCKBITS_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ -#define NVM_LOCKBITS_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ - -#define NVM_LOCKBITS_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ -#define NVM_LOCKBITS_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ -#define NVM_LOCKBITS_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ -#define NVM_LOCKBITS_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ -#define NVM_LOCKBITS_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ -#define NVM_LOCKBITS_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ - -#define NVM_LOCKBITS_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ -#define NVM_LOCKBITS_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ -#define NVM_LOCKBITS_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ -#define NVM_LOCKBITS_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ -#define NVM_LOCKBITS_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ -#define NVM_LOCKBITS_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ - -#define NVM_LOCKBITS_LB_gm 0x03 /* Lock Bits group mask. */ -#define NVM_LOCKBITS_LB_gp 0 /* Lock Bits group position. */ -#define NVM_LOCKBITS_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ -#define NVM_LOCKBITS_LB0_bp 0 /* Lock Bits bit 0 position. */ -#define NVM_LOCKBITS_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ -#define NVM_LOCKBITS_LB1_bp 1 /* Lock Bits bit 1 position. */ - - - -// Generic Port Pins - -#define PIN0_bm 0x01 -#define PIN0_bp 0 -#define PIN1_bm 0x02 -#define PIN1_bp 1 -#define PIN2_bm 0x04 -#define PIN2_bp 2 -#define PIN3_bm 0x08 -#define PIN3_bp 3 -#define PIN4_bm 0x10 -#define PIN4_bp 4 -#define PIN5_bm 0x20 -#define PIN5_bp 5 -#define PIN6_bm 0x40 -#define PIN6_bp 6 -#define PIN7_bm 0x80 -#define PIN7_bp 7 - -/* ========== Interrupt Vector Definitions ========== */ -/* Vector 0 is the reset vector */ - -/* OSC interrupt vectors */ -#define OSC_OSCF_vect_num 1 -#define OSC_OSCF_vect _VECTOR(1) /* Oscillator Failure Interrupt (NMI) */ - -/* PORTC interrupt vectors */ -#define PORTC_INT0_vect_num 2 -#define PORTC_INT0_vect _VECTOR(2) /* External Interrupt 0 */ -#define PORTC_INT1_vect_num 3 -#define PORTC_INT1_vect _VECTOR(3) /* External Interrupt 1 */ - -/* PORTR interrupt vectors */ -#define PORTR_INT0_vect_num 4 -#define PORTR_INT0_vect _VECTOR(4) /* External Interrupt 0 */ -#define PORTR_INT1_vect_num 5 -#define PORTR_INT1_vect _VECTOR(5) /* External Interrupt 1 */ - -/* DMA interrupt vectors */ -#define DMA_CH0_vect_num 6 -#define DMA_CH0_vect _VECTOR(6) /* Channel 0 Interrupt */ -#define DMA_CH1_vect_num 7 -#define DMA_CH1_vect _VECTOR(7) /* Channel 1 Interrupt */ -#define DMA_CH2_vect_num 8 -#define DMA_CH2_vect _VECTOR(8) /* Channel 2 Interrupt */ -#define DMA_CH3_vect_num 9 -#define DMA_CH3_vect _VECTOR(9) /* Channel 3 Interrupt */ - -/* RTC interrupt vectors */ -#define RTC_OVF_vect_num 10 -#define RTC_OVF_vect _VECTOR(10) /* Overflow Interrupt */ -#define RTC_COMP_vect_num 11 -#define RTC_COMP_vect _VECTOR(11) /* Compare Interrupt */ - -/* TWIC interrupt vectors */ -#define TWIC_TWIS_vect_num 12 -#define TWIC_TWIS_vect _VECTOR(12) /* TWI Slave Interrupt */ -#define TWIC_TWIM_vect_num 13 -#define TWIC_TWIM_vect _VECTOR(13) /* TWI Master Interrupt */ - -/* TCC0 interrupt vectors */ -#define TCC0_OVF_vect_num 14 -#define TCC0_OVF_vect _VECTOR(14) /* Overflow Interrupt */ - -/* TCC2 interrupt vectors */ -#define TCC2_LUNF_vect_num 14 -#define TCC2_LUNF_vect _VECTOR(14) /* Low Byte Underflow Interrupt */ - -/* TCC0 interrupt vectors */ -#define TCC0_ERR_vect_num 15 -#define TCC0_ERR_vect _VECTOR(15) /* Error Interrupt */ - -/* TCC2 interrupt vectors */ -#define TCC2_HUNF_vect_num 15 -#define TCC2_HUNF_vect _VECTOR(15) /* High Byte Underflow Interrupt */ - -/* TCC0 interrupt vectors */ -#define TCC0_CCA_vect_num 16 -#define TCC0_CCA_vect _VECTOR(16) /* Compare or Capture A Interrupt */ - -/* TCC2 interrupt vectors */ -#define TCC2_LCMPA_vect_num 16 -#define TCC2_LCMPA_vect _VECTOR(16) /* Low Byte Compare A Interrupt */ - -/* TCC0 interrupt vectors */ -#define TCC0_CCB_vect_num 17 -#define TCC0_CCB_vect _VECTOR(17) /* Compare or Capture B Interrupt */ - -/* TCC2 interrupt vectors */ -#define TCC2_LCMPB_vect_num 17 -#define TCC2_LCMPB_vect _VECTOR(17) /* Low Byte Compare B Interrupt */ - -/* TCC0 interrupt vectors */ -#define TCC0_CCC_vect_num 18 -#define TCC0_CCC_vect _VECTOR(18) /* Compare or Capture C Interrupt */ - -/* TCC2 interrupt vectors */ -#define TCC2_LCMPC_vect_num 18 -#define TCC2_LCMPC_vect _VECTOR(18) /* Low Byte Compare C Interrupt */ - -/* TCC0 interrupt vectors */ -#define TCC0_CCD_vect_num 19 -#define TCC0_CCD_vect _VECTOR(19) /* Compare or Capture D Interrupt */ - -/* TCC2 interrupt vectors */ -#define TCC2_LCMPD_vect_num 19 -#define TCC2_LCMPD_vect _VECTOR(19) /* Low Byte Compare D Interrupt */ - -/* TCC1 interrupt vectors */ -#define TCC1_OVF_vect_num 20 -#define TCC1_OVF_vect _VECTOR(20) /* Overflow Interrupt */ -#define TCC1_ERR_vect_num 21 -#define TCC1_ERR_vect _VECTOR(21) /* Error Interrupt */ -#define TCC1_CCA_vect_num 22 -#define TCC1_CCA_vect _VECTOR(22) /* Compare or Capture A Interrupt */ -#define TCC1_CCB_vect_num 23 -#define TCC1_CCB_vect _VECTOR(23) /* Compare or Capture B Interrupt */ - -/* SPIC interrupt vectors */ -#define SPIC_INT_vect_num 24 -#define SPIC_INT_vect _VECTOR(24) /* SPI Interrupt */ - -/* USARTC0 interrupt vectors */ -#define USARTC0_RXC_vect_num 25 -#define USARTC0_RXC_vect _VECTOR(25) /* Reception Complete Interrupt */ -#define USARTC0_DRE_vect_num 26 -#define USARTC0_DRE_vect _VECTOR(26) /* Data Register Empty Interrupt */ -#define USARTC0_TXC_vect_num 27 -#define USARTC0_TXC_vect _VECTOR(27) /* Transmission Complete Interrupt */ - -/* USARTC1 interrupt vectors */ -#define USARTC1_RXC_vect_num 28 -#define USARTC1_RXC_vect _VECTOR(28) /* Reception Complete Interrupt */ -#define USARTC1_DRE_vect_num 29 -#define USARTC1_DRE_vect _VECTOR(29) /* Data Register Empty Interrupt */ -#define USARTC1_TXC_vect_num 30 -#define USARTC1_TXC_vect _VECTOR(30) /* Transmission Complete Interrupt */ - -/* AES interrupt vectors */ -#define AES_INT_vect_num 31 -#define AES_INT_vect _VECTOR(31) /* AES Interrupt */ - -/* NVM interrupt vectors */ -#define NVM_EE_vect_num 32 -#define NVM_EE_vect _VECTOR(32) /* EE Interrupt */ -#define NVM_SPM_vect_num 33 -#define NVM_SPM_vect _VECTOR(33) /* SPM Interrupt */ - -/* PORTB interrupt vectors */ -#define PORTB_INT0_vect_num 34 -#define PORTB_INT0_vect _VECTOR(34) /* External Interrupt 0 */ -#define PORTB_INT1_vect_num 35 -#define PORTB_INT1_vect _VECTOR(35) /* External Interrupt 1 */ - -/* ACB interrupt vectors */ -#define ACB_AC0_vect_num 36 -#define ACB_AC0_vect _VECTOR(36) /* AC0 Interrupt */ -#define ACB_AC1_vect_num 37 -#define ACB_AC1_vect _VECTOR(37) /* AC1 Interrupt */ -#define ACB_ACW_vect_num 38 -#define ACB_ACW_vect _VECTOR(38) /* ACW Window Mode Interrupt */ - -/* ADCB interrupt vectors */ -#define ADCB_CH0_vect_num 39 -#define ADCB_CH0_vect _VECTOR(39) /* Interrupt 0 */ -#define ADCB_CH1_vect_num 40 -#define ADCB_CH1_vect _VECTOR(40) /* Interrupt 1 */ -#define ADCB_CH2_vect_num 41 -#define ADCB_CH2_vect _VECTOR(41) /* Interrupt 2 */ -#define ADCB_CH3_vect_num 42 -#define ADCB_CH3_vect _VECTOR(42) /* Interrupt 3 */ - -/* PORTE interrupt vectors */ -#define PORTE_INT0_vect_num 43 -#define PORTE_INT0_vect _VECTOR(43) /* External Interrupt 0 */ -#define PORTE_INT1_vect_num 44 -#define PORTE_INT1_vect _VECTOR(44) /* External Interrupt 1 */ - -/* TWIE interrupt vectors */ -#define TWIE_TWIS_vect_num 45 -#define TWIE_TWIS_vect _VECTOR(45) /* TWI Slave Interrupt */ -#define TWIE_TWIM_vect_num 46 -#define TWIE_TWIM_vect _VECTOR(46) /* TWI Master Interrupt */ - -/* TCE0 interrupt vectors */ -#define TCE0_OVF_vect_num 47 -#define TCE0_OVF_vect _VECTOR(47) /* Overflow Interrupt */ - -/* TCE2 interrupt vectors */ -#define TCE2_LUNF_vect_num 47 -#define TCE2_LUNF_vect _VECTOR(47) /* Low Byte Underflow Interrupt */ - -/* TCE0 interrupt vectors */ -#define TCE0_ERR_vect_num 48 -#define TCE0_ERR_vect _VECTOR(48) /* Error Interrupt */ - -/* TCE2 interrupt vectors */ -#define TCE2_HUNF_vect_num 48 -#define TCE2_HUNF_vect _VECTOR(48) /* High Byte Underflow Interrupt */ - -/* TCE0 interrupt vectors */ -#define TCE0_CCA_vect_num 49 -#define TCE0_CCA_vect _VECTOR(49) /* Compare or Capture A Interrupt */ - -/* TCE2 interrupt vectors */ -#define TCE2_LCMPA_vect_num 49 -#define TCE2_LCMPA_vect _VECTOR(49) /* Low Byte Compare A Interrupt */ - -/* TCE0 interrupt vectors */ -#define TCE0_CCB_vect_num 50 -#define TCE0_CCB_vect _VECTOR(50) /* Compare or Capture B Interrupt */ - -/* TCE2 interrupt vectors */ -#define TCE2_LCMPB_vect_num 50 -#define TCE2_LCMPB_vect _VECTOR(50) /* Low Byte Compare B Interrupt */ - -/* TCE0 interrupt vectors */ -#define TCE0_CCC_vect_num 51 -#define TCE0_CCC_vect _VECTOR(51) /* Compare or Capture C Interrupt */ - -/* TCE2 interrupt vectors */ -#define TCE2_LCMPC_vect_num 51 -#define TCE2_LCMPC_vect _VECTOR(51) /* Low Byte Compare C Interrupt */ - -/* TCE0 interrupt vectors */ -#define TCE0_CCD_vect_num 52 -#define TCE0_CCD_vect _VECTOR(52) /* Compare or Capture D Interrupt */ - -/* TCE2 interrupt vectors */ -#define TCE2_LCMPD_vect_num 52 -#define TCE2_LCMPD_vect _VECTOR(52) /* Low Byte Compare D Interrupt */ - -/* TCE1 interrupt vectors */ -#define TCE1_OVF_vect_num 53 -#define TCE1_OVF_vect _VECTOR(53) /* Overflow Interrupt */ -#define TCE1_ERR_vect_num 54 -#define TCE1_ERR_vect _VECTOR(54) /* Error Interrupt */ -#define TCE1_CCA_vect_num 55 -#define TCE1_CCA_vect _VECTOR(55) /* Compare or Capture A Interrupt */ -#define TCE1_CCB_vect_num 56 -#define TCE1_CCB_vect _VECTOR(56) /* Compare or Capture B Interrupt */ - -/* SPIE interrupt vectors */ -#define SPIE_INT_vect_num 57 -#define SPIE_INT_vect _VECTOR(57) /* SPI Interrupt */ - -/* USARTE0 interrupt vectors */ -#define USARTE0_RXC_vect_num 58 -#define USARTE0_RXC_vect _VECTOR(58) /* Reception Complete Interrupt */ -#define USARTE0_DRE_vect_num 59 -#define USARTE0_DRE_vect _VECTOR(59) /* Data Register Empty Interrupt */ -#define USARTE0_TXC_vect_num 60 -#define USARTE0_TXC_vect _VECTOR(60) /* Transmission Complete Interrupt */ - -/* USARTE1 interrupt vectors */ -#define USARTE1_RXC_vect_num 61 -#define USARTE1_RXC_vect _VECTOR(61) /* Reception Complete Interrupt */ -#define USARTE1_DRE_vect_num 62 -#define USARTE1_DRE_vect _VECTOR(62) /* Data Register Empty Interrupt */ -#define USARTE1_TXC_vect_num 63 -#define USARTE1_TXC_vect _VECTOR(63) /* Transmission Complete Interrupt */ - -/* PORTD interrupt vectors */ -#define PORTD_INT0_vect_num 64 -#define PORTD_INT0_vect _VECTOR(64) /* External Interrupt 0 */ -#define PORTD_INT1_vect_num 65 -#define PORTD_INT1_vect _VECTOR(65) /* External Interrupt 1 */ - -/* PORTA interrupt vectors */ -#define PORTA_INT0_vect_num 66 -#define PORTA_INT0_vect _VECTOR(66) /* External Interrupt 0 */ -#define PORTA_INT1_vect_num 67 -#define PORTA_INT1_vect _VECTOR(67) /* External Interrupt 1 */ - -/* ACA interrupt vectors */ -#define ACA_AC0_vect_num 68 -#define ACA_AC0_vect _VECTOR(68) /* AC0 Interrupt */ -#define ACA_AC1_vect_num 69 -#define ACA_AC1_vect _VECTOR(69) /* AC1 Interrupt */ -#define ACA_ACW_vect_num 70 -#define ACA_ACW_vect _VECTOR(70) /* ACW Window Mode Interrupt */ - -/* ADCA interrupt vectors */ -#define ADCA_CH0_vect_num 71 -#define ADCA_CH0_vect _VECTOR(71) /* Interrupt 0 */ -#define ADCA_CH1_vect_num 72 -#define ADCA_CH1_vect _VECTOR(72) /* Interrupt 1 */ -#define ADCA_CH2_vect_num 73 -#define ADCA_CH2_vect _VECTOR(73) /* Interrupt 2 */ -#define ADCA_CH3_vect_num 74 -#define ADCA_CH3_vect _VECTOR(74) /* Interrupt 3 */ - -/* TCD0 interrupt vectors */ -#define TCD0_OVF_vect_num 77 -#define TCD0_OVF_vect _VECTOR(77) /* Overflow Interrupt */ - -/* TCD2 interrupt vectors */ -#define TCD2_LUNF_vect_num 77 -#define TCD2_LUNF_vect _VECTOR(77) /* Low Byte Underflow Interrupt */ - -/* TCD0 interrupt vectors */ -#define TCD0_ERR_vect_num 78 -#define TCD0_ERR_vect _VECTOR(78) /* Error Interrupt */ - -/* TCD2 interrupt vectors */ -#define TCD2_HUNF_vect_num 78 -#define TCD2_HUNF_vect _VECTOR(78) /* High Byte Underflow Interrupt */ - -/* TCD0 interrupt vectors */ -#define TCD0_CCA_vect_num 79 -#define TCD0_CCA_vect _VECTOR(79) /* Compare or Capture A Interrupt */ - -/* TCD2 interrupt vectors */ -#define TCD2_LCMPA_vect_num 79 -#define TCD2_LCMPA_vect _VECTOR(79) /* Low Byte Compare A Interrupt */ - -/* TCD0 interrupt vectors */ -#define TCD0_CCB_vect_num 80 -#define TCD0_CCB_vect _VECTOR(80) /* Compare or Capture B Interrupt */ - -/* TCD2 interrupt vectors */ -#define TCD2_LCMPB_vect_num 80 -#define TCD2_LCMPB_vect _VECTOR(80) /* Low Byte Compare B Interrupt */ - -/* TCD0 interrupt vectors */ -#define TCD0_CCC_vect_num 81 -#define TCD0_CCC_vect _VECTOR(81) /* Compare or Capture C Interrupt */ - -/* TCD2 interrupt vectors */ -#define TCD2_LCMPC_vect_num 81 -#define TCD2_LCMPC_vect _VECTOR(81) /* Low Byte Compare C Interrupt */ - -/* TCD0 interrupt vectors */ -#define TCD0_CCD_vect_num 82 -#define TCD0_CCD_vect _VECTOR(82) /* Compare or Capture D Interrupt */ - -/* TCD2 interrupt vectors */ -#define TCD2_LCMPD_vect_num 82 -#define TCD2_LCMPD_vect _VECTOR(82) /* Low Byte Compare D Interrupt */ - -/* TCD1 interrupt vectors */ -#define TCD1_OVF_vect_num 83 -#define TCD1_OVF_vect _VECTOR(83) /* Overflow Interrupt */ -#define TCD1_ERR_vect_num 84 -#define TCD1_ERR_vect _VECTOR(84) /* Error Interrupt */ -#define TCD1_CCA_vect_num 85 -#define TCD1_CCA_vect _VECTOR(85) /* Compare or Capture A Interrupt */ -#define TCD1_CCB_vect_num 86 -#define TCD1_CCB_vect _VECTOR(86) /* Compare or Capture B Interrupt */ - -/* SPID interrupt vectors */ -#define SPID_INT_vect_num 87 -#define SPID_INT_vect _VECTOR(87) /* SPI Interrupt */ - -/* USARTD0 interrupt vectors */ -#define USARTD0_RXC_vect_num 88 -#define USARTD0_RXC_vect _VECTOR(88) /* Reception Complete Interrupt */ -#define USARTD0_DRE_vect_num 89 -#define USARTD0_DRE_vect _VECTOR(89) /* Data Register Empty Interrupt */ -#define USARTD0_TXC_vect_num 90 -#define USARTD0_TXC_vect _VECTOR(90) /* Transmission Complete Interrupt */ - -/* USARTD1 interrupt vectors */ -#define USARTD1_RXC_vect_num 91 -#define USARTD1_RXC_vect _VECTOR(91) /* Reception Complete Interrupt */ -#define USARTD1_DRE_vect_num 92 -#define USARTD1_DRE_vect _VECTOR(92) /* Data Register Empty Interrupt */ -#define USARTD1_TXC_vect_num 93 -#define USARTD1_TXC_vect _VECTOR(93) /* Transmission Complete Interrupt */ - -/* PORTF interrupt vectors */ -#define PORTF_INT0_vect_num 104 -#define PORTF_INT0_vect _VECTOR(104) /* External Interrupt 0 */ -#define PORTF_INT1_vect_num 105 -#define PORTF_INT1_vect _VECTOR(105) /* External Interrupt 1 */ - -/* TCF0 interrupt vectors */ -#define TCF0_OVF_vect_num 108 -#define TCF0_OVF_vect _VECTOR(108) /* Overflow Interrupt */ - -/* TCF2 interrupt vectors */ -#define TCF2_LUNF_vect_num 108 -#define TCF2_LUNF_vect _VECTOR(108) /* Low Byte Underflow Interrupt */ - -/* TCF0 interrupt vectors */ -#define TCF0_ERR_vect_num 109 -#define TCF0_ERR_vect _VECTOR(109) /* Error Interrupt */ - -/* TCF2 interrupt vectors */ -#define TCF2_HUNF_vect_num 109 -#define TCF2_HUNF_vect _VECTOR(109) /* High Byte Underflow Interrupt */ - -/* TCF0 interrupt vectors */ -#define TCF0_CCA_vect_num 110 -#define TCF0_CCA_vect _VECTOR(110) /* Compare or Capture A Interrupt */ - -/* TCF2 interrupt vectors */ -#define TCF2_LCMPA_vect_num 110 -#define TCF2_LCMPA_vect _VECTOR(110) /* Low Byte Compare A Interrupt */ - -/* TCF0 interrupt vectors */ -#define TCF0_CCB_vect_num 111 -#define TCF0_CCB_vect _VECTOR(111) /* Compare or Capture B Interrupt */ - -/* TCF2 interrupt vectors */ -#define TCF2_LCMPB_vect_num 111 -#define TCF2_LCMPB_vect _VECTOR(111) /* Low Byte Compare B Interrupt */ - -/* TCF0 interrupt vectors */ -#define TCF0_CCC_vect_num 112 -#define TCF0_CCC_vect _VECTOR(112) /* Compare or Capture C Interrupt */ - -/* TCF2 interrupt vectors */ -#define TCF2_LCMPC_vect_num 112 -#define TCF2_LCMPC_vect _VECTOR(112) /* Low Byte Compare C Interrupt */ - -/* TCF0 interrupt vectors */ -#define TCF0_CCD_vect_num 113 -#define TCF0_CCD_vect _VECTOR(113) /* Compare or Capture D Interrupt */ - -/* TCF2 interrupt vectors */ -#define TCF2_LCMPD_vect_num 113 -#define TCF2_LCMPD_vect _VECTOR(113) /* Low Byte Compare D Interrupt */ - -/* USARTF0 interrupt vectors */ -#define USARTF0_RXC_vect_num 119 -#define USARTF0_RXC_vect _VECTOR(119) /* Reception Complete Interrupt */ -#define USARTF0_DRE_vect_num 120 -#define USARTF0_DRE_vect _VECTOR(120) /* Data Register Empty Interrupt */ -#define USARTF0_TXC_vect_num 121 -#define USARTF0_TXC_vect _VECTOR(121) /* Transmission Complete Interrupt */ - -/* USB interrupt vectors */ -#define USB_BUSEVENT_vect_num 125 -#define USB_BUSEVENT_vect _VECTOR(125) /* SOF, suspend, resume, reset bus event interrupts, crc, underflow, overflow and stall error interrupts */ -#define USB_TRNCOMPL_vect_num 126 -#define USB_TRNCOMPL_vect _VECTOR(126) /* Transaction complete interrupt */ - -#define _VECTOR_SIZE 4 /* Size of individual vector. */ -#define _VECTORS_SIZE (127 * _VECTOR_SIZE) - - -/* ========== Constants ========== */ - -#define PROGMEM_START (0x0000) -#define PROGMEM_SIZE (204800) -#define PROGMEM_END (PROGMEM_START + PROGMEM_SIZE - 1) - -#define APP_SECTION_START (0x0000) -#define APP_SECTION_SIZE (196608) -#define APP_SECTION_PAGE_SIZE (512) -#define APP_SECTION_END (APP_SECTION_START + APP_SECTION_SIZE - 1) - -#define APPTABLE_SECTION_START (0x2E000) -#define APPTABLE_SECTION_SIZE (8192) -#define APPTABLE_SECTION_PAGE_SIZE (512) -#define APPTABLE_SECTION_END (APPTABLE_SECTION_START + APPTABLE_SECTION_SIZE - 1) - -#define BOOT_SECTION_START (0x30000) -#define BOOT_SECTION_SIZE (8192) -#define BOOT_SECTION_PAGE_SIZE (512) -#define BOOT_SECTION_END (BOOT_SECTION_START + BOOT_SECTION_SIZE - 1) - -#define DATAMEM_START (0x0000) -#define DATAMEM_SIZE (24576) -#define DATAMEM_END (DATAMEM_START + DATAMEM_SIZE - 1) - -#define IO_START (0x0000) -#define IO_SIZE (4096) -#define IO_PAGE_SIZE (0) -#define IO_END (IO_START + IO_SIZE - 1) - -#define MAPPED_EEPROM_START (0x1000) -#define MAPPED_EEPROM_SIZE (2048) -#define MAPPED_EEPROM_PAGE_SIZE (0) -#define MAPPED_EEPROM_END (MAPPED_EEPROM_START + MAPPED_EEPROM_SIZE - 1) - -#define INTERNAL_SRAM_START (0x2000) -#define INTERNAL_SRAM_SIZE (16384) -#define INTERNAL_SRAM_PAGE_SIZE (0) -#define INTERNAL_SRAM_END (INTERNAL_SRAM_START + INTERNAL_SRAM_SIZE - 1) - -#define EEPROM_START (0x0000) -#define EEPROM_SIZE (2048) -#define EEPROM_PAGE_SIZE (32) -#define EEPROM_END (EEPROM_START + EEPROM_SIZE - 1) - -#define SIGNATURES_START (0x0000) -#define SIGNATURES_SIZE (3) -#define SIGNATURES_PAGE_SIZE (0) -#define SIGNATURES_END (SIGNATURES_START + SIGNATURES_SIZE - 1) - -#define FUSES_START (0x0000) -#define FUSES_SIZE (6) -#define FUSES_PAGE_SIZE (0) -#define FUSES_END (FUSES_START + FUSES_SIZE - 1) - -#define LOCKBITS_START (0x0000) -#define LOCKBITS_SIZE (1) -#define LOCKBITS_PAGE_SIZE (0) -#define LOCKBITS_END (LOCKBITS_START + LOCKBITS_SIZE - 1) - -#define USER_SIGNATURES_START (0x0000) -#define USER_SIGNATURES_SIZE (512) -#define USER_SIGNATURES_PAGE_SIZE (512) -#define USER_SIGNATURES_END (USER_SIGNATURES_START + USER_SIGNATURES_SIZE - 1) - -#define PROD_SIGNATURES_START (0x0000) -#define PROD_SIGNATURES_SIZE (52) -#define PROD_SIGNATURES_PAGE_SIZE (512) -#define PROD_SIGNATURES_END (PROD_SIGNATURES_START + PROD_SIGNATURES_SIZE - 1) - -#define FLASHSTART PROGMEM_START -#define FLASHEND PROGMEM_END -#define SPM_PAGESIZE 512 -#define RAMSTART INTERNAL_SRAM_START -#define RAMSIZE INTERNAL_SRAM_SIZE -#define RAMEND INTERNAL_SRAM_END -#define E2END EEPROM_END -#define E2PAGESIZE EEPROM_PAGE_SIZE - - -/* ========== Fuses ========== */ -#define FUSE_MEMORY_SIZE 6 - -/* Fuse Byte 0 */ -#define FUSE_JTAGUSERID0 (unsigned char)~_BV(0) /* JTAG User ID Bit 0 */ -#define FUSE_JTAGUSERID1 (unsigned char)~_BV(1) /* JTAG User ID Bit 1 */ -#define FUSE_JTAGUSERID2 (unsigned char)~_BV(2) /* JTAG User ID Bit 2 */ -#define FUSE_JTAGUSERID3 (unsigned char)~_BV(3) /* JTAG User ID Bit 3 */ -#define FUSE_JTAGUSERID4 (unsigned char)~_BV(4) /* JTAG User ID Bit 4 */ -#define FUSE_JTAGUSERID5 (unsigned char)~_BV(5) /* JTAG User ID Bit 5 */ -#define FUSE_JTAGUSERID6 (unsigned char)~_BV(6) /* JTAG User ID Bit 6 */ -#define FUSE_JTAGUSERID7 (unsigned char)~_BV(7) /* JTAG User ID Bit 7 */ -#define FUSE0_DEFAULT (0xFF) - -/* Fuse Byte 1 */ -#define FUSE_WDP0 (unsigned char)~_BV(0) /* Watchdog Timeout Period Bit 0 */ -#define FUSE_WDP1 (unsigned char)~_BV(1) /* Watchdog Timeout Period Bit 1 */ -#define FUSE_WDP2 (unsigned char)~_BV(2) /* Watchdog Timeout Period Bit 2 */ -#define FUSE_WDP3 (unsigned char)~_BV(3) /* Watchdog Timeout Period Bit 3 */ -#define FUSE_WDWP0 (unsigned char)~_BV(4) /* Watchdog Window Timeout Period Bit 0 */ -#define FUSE_WDWP1 (unsigned char)~_BV(5) /* Watchdog Window Timeout Period Bit 1 */ -#define FUSE_WDWP2 (unsigned char)~_BV(6) /* Watchdog Window Timeout Period Bit 2 */ -#define FUSE_WDWP3 (unsigned char)~_BV(7) /* Watchdog Window Timeout Period Bit 3 */ -#define FUSE1_DEFAULT (0xFF) - -/* Fuse Byte 2 */ -#define FUSE_BODPD0 (unsigned char)~_BV(0) /* BOD Operation in Power-Down Mode Bit 0 */ -#define FUSE_BODPD1 (unsigned char)~_BV(1) /* BOD Operation in Power-Down Mode Bit 1 */ -#define FUSE_TOSCSEL (unsigned char)~_BV(5) /* Timer Oscillator pin location */ -#define FUSE_BOOTRST (unsigned char)~_BV(6) /* Boot Loader Section Reset Vector */ -#define FUSE2_DEFAULT (0xFF) - -/* Fuse Byte 3 Reserved */ - -/* Fuse Byte 4 */ -#define FUSE_JTAGEN (unsigned char)~_BV(0) /* JTAG Interface Enable */ -#define FUSE_WDLOCK (unsigned char)~_BV(1) /* Watchdog Timer Lock */ -#define FUSE_SUT0 (unsigned char)~_BV(2) /* Start-up Time Bit 0 */ -#define FUSE_SUT1 (unsigned char)~_BV(3) /* Start-up Time Bit 1 */ -#define FUSE_RSTDISBL (unsigned char)~_BV(4) /* External Reset Disable */ -#define FUSE4_DEFAULT (0xFF) - -/* Fuse Byte 5 */ -#define FUSE_BODLVL0 (unsigned char)~_BV(0) /* Brownout Detection Voltage Level Bit 0 */ -#define FUSE_BODLVL1 (unsigned char)~_BV(1) /* Brownout Detection Voltage Level Bit 1 */ -#define FUSE_BODLVL2 (unsigned char)~_BV(2) /* Brownout Detection Voltage Level Bit 2 */ -#define FUSE_EESAVE (unsigned char)~_BV(3) /* Preserve EEPROM Through Chip Erase */ -#define FUSE_BODACT0 (unsigned char)~_BV(4) /* BOD Operation in Active Mode Bit 0 */ -#define FUSE_BODACT1 (unsigned char)~_BV(5) /* BOD Operation in Active Mode Bit 1 */ -#define FUSE5_DEFAULT (0xFF) - -/* ========== Lock Bits ========== */ -#define __LOCK_BITS_EXIST -#define __BOOT_LOCK_APPLICATION_TABLE_BITS_EXIST -#define __BOOT_LOCK_APPLICATION_BITS_EXIST -#define __BOOT_LOCK_BOOT_BITS_EXIST - -/* ========== Signature ========== */ -#define SIGNATURE_0 0x1E -#define SIGNATURE_1 0x97 -#define SIGNATURE_2 0x44 - -/* ========== Power Reduction Condition Definitions ========== */ - -/* PR.PRGEN */ -#define __AVR_HAVE_PRGEN (PR_USB_bm|PR_AES_bm|PR_EBI_bm|PR_RTC_bm|PR_EVSYS_bm|PR_DMA_bm) -#define __AVR_HAVE_PRGEN_USB -#define __AVR_HAVE_PRGEN_AES -#define __AVR_HAVE_PRGEN_EBI -#define __AVR_HAVE_PRGEN_RTC -#define __AVR_HAVE_PRGEN_EVSYS -#define __AVR_HAVE_PRGEN_DMA - -/* PR.PRPA */ -#define __AVR_HAVE_PRPA (PR_DAC_bm|PR_ADC_bm|PR_AC_bm) -#define __AVR_HAVE_PRPA_DAC -#define __AVR_HAVE_PRPA_ADC -#define __AVR_HAVE_PRPA_AC - -/* PR.PRPB */ -#define __AVR_HAVE_PRPB (PR_DAC_bm|PR_ADC_bm|PR_AC_bm) -#define __AVR_HAVE_PRPB_DAC -#define __AVR_HAVE_PRPB_ADC -#define __AVR_HAVE_PRPB_AC - -/* PR.PRPC */ -#define __AVR_HAVE_PRPC (PR_TWI_bm|PR_USART1_bm|PR_USART0_bm|PR_SPI_bm|PR_HIRES_bm|PR_TC1_bm|PR_TC0_bm) -#define __AVR_HAVE_PRPC_TWI -#define __AVR_HAVE_PRPC_USART1 -#define __AVR_HAVE_PRPC_USART0 -#define __AVR_HAVE_PRPC_SPI -#define __AVR_HAVE_PRPC_HIRES -#define __AVR_HAVE_PRPC_TC1 -#define __AVR_HAVE_PRPC_TC0 - -/* PR.PRPD */ -#define __AVR_HAVE_PRPD (PR_TWI_bm|PR_USART1_bm|PR_USART0_bm|PR_SPI_bm|PR_HIRES_bm|PR_TC1_bm|PR_TC0_bm) -#define __AVR_HAVE_PRPD_TWI -#define __AVR_HAVE_PRPD_USART1 -#define __AVR_HAVE_PRPD_USART0 -#define __AVR_HAVE_PRPD_SPI -#define __AVR_HAVE_PRPD_HIRES -#define __AVR_HAVE_PRPD_TC1 -#define __AVR_HAVE_PRPD_TC0 - -/* PR.PRPE */ -#define __AVR_HAVE_PRPE (PR_TWI_bm|PR_USART1_bm|PR_USART0_bm|PR_SPI_bm|PR_HIRES_bm|PR_TC1_bm|PR_TC0_bm) -#define __AVR_HAVE_PRPE_TWI -#define __AVR_HAVE_PRPE_USART1 -#define __AVR_HAVE_PRPE_USART0 -#define __AVR_HAVE_PRPE_SPI -#define __AVR_HAVE_PRPE_HIRES -#define __AVR_HAVE_PRPE_TC1 -#define __AVR_HAVE_PRPE_TC0 - -/* PR.PRPF */ -#define __AVR_HAVE_PRPF (PR_TWI_bm|PR_USART1_bm|PR_USART0_bm|PR_SPI_bm|PR_HIRES_bm|PR_TC1_bm|PR_TC0_bm) -#define __AVR_HAVE_PRPF_TWI -#define __AVR_HAVE_PRPF_USART1 -#define __AVR_HAVE_PRPF_USART0 -#define __AVR_HAVE_PRPF_SPI -#define __AVR_HAVE_PRPF_HIRES -#define __AVR_HAVE_PRPF_TC1 -#define __AVR_HAVE_PRPF_TC0 - - -#endif /* #ifdef _AVR_ATXMEGA192A3U_H_INCLUDED */ - diff --git a/arduino/hardware/tools/avr/avr/include/avr/iox192c3.h b/arduino/hardware/tools/avr/avr/include/avr/iox192c3.h deleted file mode 100644 index fc61ec4..0000000 --- a/arduino/hardware/tools/avr/avr/include/avr/iox192c3.h +++ /dev/null @@ -1,6264 +0,0 @@ -/***************************************************************************** - * - * Copyright (C) 2015 Atmel Corporation - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * - * * Neither the name of the copyright holders nor the names of - * contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - ****************************************************************************/ - - -#ifndef _AVR_IO_H_ -# error "Include instead of this file." -#endif - -#ifndef _AVR_IOXXX_H_ -# define _AVR_IOXXX_H_ "iox192c3.h" -#else -# error "Attempt to include more than one file." -#endif - -#ifndef _AVR_ATXMEGA192C3_H_INCLUDED -#define _AVR_ATXMEGA192C3_H_INCLUDED - -/* Ungrouped common registers */ -#define GPIOR0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ -#define GPIOR1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ -#define GPIOR2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ -#define GPIOR3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ - -/* Deprecated */ -#define GPIO0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ -#define GPIO1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ -#define GPIO2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ -#define GPIO3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ - -#define CCP _SFR_MEM8(0x0034) /* Configuration Change Protection */ -#define RAMPD _SFR_MEM8(0x0038) /* Ramp D */ -#define RAMPX _SFR_MEM8(0x0039) /* Ramp X */ -#define RAMPY _SFR_MEM8(0x003A) /* Ramp Y */ -#define RAMPZ _SFR_MEM8(0x003B) /* Ramp Z */ -#define EIND _SFR_MEM8(0x003C) /* Extended Indirect Jump */ -#define SPL _SFR_MEM8(0x003D) /* Stack Pointer Low */ -#define SPH _SFR_MEM8(0x003E) /* Stack Pointer High */ -#define SREG _SFR_MEM8(0x003F) /* Status Register */ - -/* C Language Only */ -#if !defined (__ASSEMBLER__) - -#include - -typedef volatile uint8_t register8_t; -typedef volatile uint16_t register16_t; -typedef volatile uint32_t register32_t; - - -#ifdef _WORDREGISTER -#undef _WORDREGISTER -#endif -#define _WORDREGISTER(regname) \ - __extension__ union \ - { \ - register16_t regname; \ - struct \ - { \ - register8_t regname ## L; \ - register8_t regname ## H; \ - }; \ - } - -#ifdef _DWORDREGISTER -#undef _DWORDREGISTER -#endif -#define _DWORDREGISTER(regname) \ - __extension__ union \ - { \ - register32_t regname; \ - struct \ - { \ - register8_t regname ## 0; \ - register8_t regname ## 1; \ - register8_t regname ## 2; \ - register8_t regname ## 3; \ - }; \ - } - - -/* -========================================================================== -IO Module Structures -========================================================================== -*/ - - -/* --------------------------------------------------------------------------- -VPORT - Virtual Ports --------------------------------------------------------------------------- -*/ - -/* Virtual Port */ -typedef struct VPORT_struct -{ - register8_t DIR; /* I/O Port Data Direction */ - register8_t OUT; /* I/O Port Output */ - register8_t IN; /* I/O Port Input */ - register8_t INTFLAGS; /* Interrupt Flag Register */ -} VPORT_t; - - -/* --------------------------------------------------------------------------- -XOCD - On-Chip Debug System --------------------------------------------------------------------------- -*/ - -/* On-Chip Debug System */ -typedef struct OCD_struct -{ - register8_t OCDR0; /* OCD Register 0 */ - register8_t OCDR1; /* OCD Register 1 */ -} OCD_t; - - -/* --------------------------------------------------------------------------- -CPU - CPU --------------------------------------------------------------------------- -*/ - -/* CCP signatures */ -typedef enum CCP_enum -{ - CCP_SPM_gc = (0x9D<<0), /* SPM Instruction Protection */ - CCP_IOREG_gc = (0xD8<<0), /* IO Register Protection */ -} CCP_t; - - -/* --------------------------------------------------------------------------- -CLK - Clock System --------------------------------------------------------------------------- -*/ - -/* Clock System */ -typedef struct CLK_struct -{ - register8_t CTRL; /* Control Register */ - register8_t PSCTRL; /* Prescaler Control Register */ - register8_t LOCK; /* Lock register */ - register8_t RTCCTRL; /* RTC Control Register */ - register8_t USBCTRL; /* USB Control Register */ -} CLK_t; - - -/* Power Reduction */ -typedef struct PR_struct -{ - register8_t PRGEN; /* General Power Reduction */ - register8_t PRPA; /* Power Reduction Port A */ - register8_t reserved_0x02; - register8_t PRPC; /* Power Reduction Port C */ - register8_t PRPD; /* Power Reduction Port D */ - register8_t PRPE; /* Power Reduction Port E */ - register8_t PRPF; /* Power Reduction Port F */ -} PR_t; - -/* System Clock Selection */ -typedef enum CLK_SCLKSEL_enum -{ - CLK_SCLKSEL_RC2M_gc = (0x00<<0), /* Internal 2 MHz RC Oscillator */ - CLK_SCLKSEL_RC32M_gc = (0x01<<0), /* Internal 32 MHz RC Oscillator */ - CLK_SCLKSEL_RC32K_gc = (0x02<<0), /* Internal 32.768 kHz RC Oscillator */ - CLK_SCLKSEL_XOSC_gc = (0x03<<0), /* External Crystal Oscillator or Clock */ - CLK_SCLKSEL_PLL_gc = (0x04<<0), /* Phase Locked Loop */ -} CLK_SCLKSEL_t; - -/* Prescaler A Division Factor */ -typedef enum CLK_PSADIV_enum -{ - CLK_PSADIV_1_gc = (0x00<<2), /* Divide by 1 */ - CLK_PSADIV_2_gc = (0x01<<2), /* Divide by 2 */ - CLK_PSADIV_4_gc = (0x03<<2), /* Divide by 4 */ - CLK_PSADIV_8_gc = (0x05<<2), /* Divide by 8 */ - CLK_PSADIV_16_gc = (0x07<<2), /* Divide by 16 */ - CLK_PSADIV_32_gc = (0x09<<2), /* Divide by 32 */ - CLK_PSADIV_64_gc = (0x0B<<2), /* Divide by 64 */ - CLK_PSADIV_128_gc = (0x0D<<2), /* Divide by 128 */ - CLK_PSADIV_256_gc = (0x0F<<2), /* Divide by 256 */ - CLK_PSADIV_512_gc = (0x11<<2), /* Divide by 512 */ -} CLK_PSADIV_t; - -/* Prescaler B and C Division Factor */ -typedef enum CLK_PSBCDIV_enum -{ - CLK_PSBCDIV_1_1_gc = (0x00<<0), /* Divide B by 1 and C by 1 */ - CLK_PSBCDIV_1_2_gc = (0x01<<0), /* Divide B by 1 and C by 2 */ - CLK_PSBCDIV_4_1_gc = (0x02<<0), /* Divide B by 4 and C by 1 */ - CLK_PSBCDIV_2_2_gc = (0x03<<0), /* Divide B by 2 and C by 2 */ -} CLK_PSBCDIV_t; - -/* RTC Clock Source */ -typedef enum CLK_RTCSRC_enum -{ - CLK_RTCSRC_ULP_gc = (0x00<<1), /* 1.024 kHz from internal 32kHz ULP */ - CLK_RTCSRC_TOSC_gc = (0x01<<1), /* 1.024 kHz from 32.768 kHz crystal oscillator on TOSC */ - CLK_RTCSRC_RCOSC_gc = (0x02<<1), /* 1.024 kHz from internal 32.768 kHz RC oscillator */ - CLK_RTCSRC_TOSC32_gc = (0x05<<1), /* 32.768 kHz from 32.768 kHz crystal oscillator on TOSC */ - CLK_RTCSRC_RCOSC32_gc = (0x06<<1), /* 32.768 kHz from internal 32.768 kHz RC oscillator */ - CLK_RTCSRC_EXTCLK_gc = (0x07<<1), /* External Clock from TOSC1 */ -} CLK_RTCSRC_t; - -/* USB Prescaler Division Factor */ -typedef enum CLK_USBPSDIV_enum -{ - CLK_USBPSDIV_1_gc = (0x00<<3), /* Divide by 1 */ - CLK_USBPSDIV_2_gc = (0x01<<3), /* Divide by 2 */ - CLK_USBPSDIV_4_gc = (0x02<<3), /* Divide by 4 */ - CLK_USBPSDIV_8_gc = (0x03<<3), /* Divide by 8 */ - CLK_USBPSDIV_16_gc = (0x04<<3), /* Divide by 16 */ - CLK_USBPSDIV_32_gc = (0x05<<3), /* Divide by 32 */ -} CLK_USBPSDIV_t; - -/* USB Clock Source */ -typedef enum CLK_USBSRC_enum -{ - CLK_USBSRC_PLL_gc = (0x00<<1), /* PLL */ - CLK_USBSRC_RC32M_gc = (0x01<<1), /* Internal 32 MHz RC Oscillator */ -} CLK_USBSRC_t; - - -/* --------------------------------------------------------------------------- -SLEEP - Sleep Controller --------------------------------------------------------------------------- -*/ - -/* Sleep Controller */ -typedef struct SLEEP_struct -{ - register8_t CTRL; /* Control Register */ -} SLEEP_t; - -/* Sleep Mode */ -typedef enum SLEEP_SMODE_enum -{ - SLEEP_SMODE_IDLE_gc = (0x00<<1), /* Idle mode */ - SLEEP_SMODE_PDOWN_gc = (0x02<<1), /* Power-down Mode */ - SLEEP_SMODE_PSAVE_gc = (0x03<<1), /* Power-save Mode */ - SLEEP_SMODE_STDBY_gc = (0x06<<1), /* Standby Mode */ - SLEEP_SMODE_ESTDBY_gc = (0x07<<1), /* Extended Standby Mode */ -} SLEEP_SMODE_t; - - - -#define SLEEP_MODE_IDLE (0x00<<1) -#define SLEEP_MODE_PWR_DOWN (0x02<<1) -#define SLEEP_MODE_PWR_SAVE (0x03<<1) -#define SLEEP_MODE_STANDBY (0x06<<1) -#define SLEEP_MODE_EXT_STANDBY (0x07<<1) -/* --------------------------------------------------------------------------- -OSC - Oscillator --------------------------------------------------------------------------- -*/ - -/* Oscillator */ -typedef struct OSC_struct -{ - register8_t CTRL; /* Control Register */ - register8_t STATUS; /* Status Register */ - register8_t XOSCCTRL; /* External Oscillator Control Register */ - register8_t XOSCFAIL; /* Oscillator Failure Detection Register */ - register8_t RC32KCAL; /* 32.768 kHz Internal Oscillator Calibration Register */ - register8_t PLLCTRL; /* PLL Control Register */ - register8_t DFLLCTRL; /* DFLL Control Register */ -} OSC_t; - -/* Oscillator Frequency Range */ -typedef enum OSC_FRQRANGE_enum -{ - OSC_FRQRANGE_04TO2_gc = (0x00<<6), /* 0.4 - 2 MHz */ - OSC_FRQRANGE_2TO9_gc = (0x01<<6), /* 2 - 9 MHz */ - OSC_FRQRANGE_9TO12_gc = (0x02<<6), /* 9 - 12 MHz */ - OSC_FRQRANGE_12TO16_gc = (0x03<<6), /* 12 - 16 MHz */ -} OSC_FRQRANGE_t; - -/* External Oscillator Selection and Startup Time */ -typedef enum OSC_XOSCSEL_enum -{ - OSC_XOSCSEL_EXTCLK_gc = (0x00<<0), /* External Clock - 6 CLK */ - OSC_XOSCSEL_32KHz_gc = (0x02<<0), /* 32.768 kHz TOSC - 32K CLK */ - OSC_XOSCSEL_XTAL_256CLK_gc = (0x03<<0), /* 0.4-16 MHz XTAL - 256 CLK */ - OSC_XOSCSEL_XTAL_1KCLK_gc = (0x07<<0), /* 0.4-16 MHz XTAL - 1K CLK */ - OSC_XOSCSEL_XTAL_16KCLK_gc = (0x0B<<0), /* 0.4-16 MHz XTAL - 16K CLK */ -} OSC_XOSCSEL_t; - -/* PLL Clock Source */ -typedef enum OSC_PLLSRC_enum -{ - OSC_PLLSRC_RC2M_gc = (0x00<<6), /* Internal 2 MHz RC Oscillator */ - OSC_PLLSRC_RC32M_gc = (0x02<<6), /* Internal 32 MHz RC Oscillator */ - OSC_PLLSRC_XOSC_gc = (0x03<<6), /* External Oscillator */ -} OSC_PLLSRC_t; - -/* 2 MHz DFLL Calibration Reference */ -typedef enum OSC_RC2MCREF_enum -{ - OSC_RC2MCREF_RC32K_gc = (0x00<<0), /* Internal 32.768 kHz RC Oscillator */ - OSC_RC2MCREF_XOSC32K_gc = (0x01<<0), /* External 32.768 kHz Crystal Oscillator */ -} OSC_RC2MCREF_t; - -/* 32 MHz DFLL Calibration Reference */ -typedef enum OSC_RC32MCREF_enum -{ - OSC_RC32MCREF_RC32K_gc = (0x00<<1), /* Internal 32.768 kHz RC Oscillator */ - OSC_RC32MCREF_XOSC32K_gc = (0x01<<1), /* External 32.768 kHz Crystal Oscillator */ - OSC_RC32MCREF_USBSOF_gc = (0x02<<1), /* USB Start of Frame */ -} OSC_RC32MCREF_t; - - -/* --------------------------------------------------------------------------- -DFLL - DFLL --------------------------------------------------------------------------- -*/ - -/* DFLL */ -typedef struct DFLL_struct -{ - register8_t CTRL; /* Control Register */ - register8_t reserved_0x01; - register8_t CALA; /* Calibration Register A */ - register8_t CALB; /* Calibration Register B */ - register8_t COMP0; /* Oscillator Compare Register 0 */ - register8_t COMP1; /* Oscillator Compare Register 1 */ - register8_t COMP2; /* Oscillator Compare Register 2 */ - register8_t reserved_0x07; -} DFLL_t; - - -/* --------------------------------------------------------------------------- -RST - Reset --------------------------------------------------------------------------- -*/ - -/* Reset */ -typedef struct RST_struct -{ - register8_t STATUS; /* Status Register */ - register8_t CTRL; /* Control Register */ -} RST_t; - - -/* --------------------------------------------------------------------------- -WDT - Watch-Dog Timer --------------------------------------------------------------------------- -*/ - -/* Watch-Dog Timer */ -typedef struct WDT_struct -{ - register8_t CTRL; /* Control */ - register8_t WINCTRL; /* Windowed Mode Control */ - register8_t STATUS; /* Status */ -} WDT_t; - -/* Period setting */ -typedef enum WDT_PER_enum -{ - WDT_PER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ - WDT_PER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ - WDT_PER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ - WDT_PER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ - WDT_PER_128CLK_gc = (0x04<<2), /* 128 cycles (0.128s @ 3.3V) */ - WDT_PER_256CLK_gc = (0x05<<2), /* 256 cycles (0.256s @ 3.3V) */ - WDT_PER_512CLK_gc = (0x06<<2), /* 512 cycles (0.512s @ 3.3V) */ - WDT_PER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ - WDT_PER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ - WDT_PER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ - WDT_PER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ -} WDT_PER_t; - -/* Closed window period */ -typedef enum WDT_WPER_enum -{ - WDT_WPER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ - WDT_WPER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ - WDT_WPER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ - WDT_WPER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ - WDT_WPER_128CLK_gc = (0x04<<2), /* 128 cycles (0.128s @ 3.3V) */ - WDT_WPER_256CLK_gc = (0x05<<2), /* 256 cycles (0.256s @ 3.3V) */ - WDT_WPER_512CLK_gc = (0x06<<2), /* 512 cycles (0.512s @ 3.3V) */ - WDT_WPER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ - WDT_WPER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ - WDT_WPER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ - WDT_WPER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ -} WDT_WPER_t; - - -/* --------------------------------------------------------------------------- -MCU - MCU Control --------------------------------------------------------------------------- -*/ - -/* MCU Control */ -typedef struct MCU_struct -{ - register8_t DEVID0; /* Device ID byte 0 */ - register8_t DEVID1; /* Device ID byte 1 */ - register8_t DEVID2; /* Device ID byte 2 */ - register8_t REVID; /* Revision ID */ - register8_t reserved_0x04; - register8_t reserved_0x05; - register8_t reserved_0x06; - register8_t ANAINIT; /* Analog Startup Delay */ - register8_t EVSYSLOCK; /* Event System Lock */ - register8_t AWEXLOCK; /* AWEX Lock */ - register8_t reserved_0x0A; - register8_t reserved_0x0B; -} MCU_t; - - -/* --------------------------------------------------------------------------- -PMIC - Programmable Multi-level Interrupt Controller --------------------------------------------------------------------------- -*/ - -/* Programmable Multi-level Interrupt Controller */ -typedef struct PMIC_struct -{ - register8_t STATUS; /* Status Register */ - register8_t INTPRI; /* Interrupt Priority */ - register8_t CTRL; /* Control Register */ - register8_t reserved_0x03; - register8_t reserved_0x04; - register8_t reserved_0x05; - register8_t reserved_0x06; - register8_t reserved_0x07; - register8_t reserved_0x08; - register8_t reserved_0x09; - register8_t reserved_0x0A; - register8_t reserved_0x0B; - register8_t reserved_0x0C; - register8_t reserved_0x0D; - register8_t reserved_0x0E; - register8_t reserved_0x0F; -} PMIC_t; - - -/* --------------------------------------------------------------------------- -PORTCFG - Port Configuration --------------------------------------------------------------------------- -*/ - -/* I/O port Configuration */ -typedef struct PORTCFG_struct -{ - register8_t MPCMASK; /* Multi-pin Configuration Mask */ - register8_t reserved_0x01; - register8_t VPCTRLA; /* Virtual Port Control Register A */ - register8_t VPCTRLB; /* Virtual Port Control Register B */ - register8_t CLKEVOUT; /* Clock and Event Out Register */ - register8_t reserved_0x05; - register8_t EVOUTSEL; /* Event Output Select */ -} PORTCFG_t; - -/* Virtual Port Mapping */ -typedef enum PORTCFG_VP02MAP_enum -{ - PORTCFG_VP02MAP_PORTA_gc = (0x00<<0), /* Mapped To PORTA */ - PORTCFG_VP02MAP_PORTB_gc = (0x01<<0), /* Mapped To PORTB */ - PORTCFG_VP02MAP_PORTC_gc = (0x02<<0), /* Mapped To PORTC */ - PORTCFG_VP02MAP_PORTD_gc = (0x03<<0), /* Mapped To PORTD */ - PORTCFG_VP02MAP_PORTE_gc = (0x04<<0), /* Mapped To PORTE */ - PORTCFG_VP02MAP_PORTF_gc = (0x05<<0), /* Mapped To PORTF */ - PORTCFG_VP02MAP_PORTG_gc = (0x06<<0), /* Mapped To PORTG */ - PORTCFG_VP02MAP_PORTH_gc = (0x07<<0), /* Mapped To PORTH */ - PORTCFG_VP02MAP_PORTJ_gc = (0x08<<0), /* Mapped To PORTJ */ - PORTCFG_VP02MAP_PORTK_gc = (0x09<<0), /* Mapped To PORTK */ - PORTCFG_VP02MAP_PORTL_gc = (0x0A<<0), /* Mapped To PORTL */ - PORTCFG_VP02MAP_PORTM_gc = (0x0B<<0), /* Mapped To PORTM */ - PORTCFG_VP02MAP_PORTN_gc = (0x0C<<0), /* Mapped To PORTN */ - PORTCFG_VP02MAP_PORTP_gc = (0x0D<<0), /* Mapped To PORTP */ - PORTCFG_VP02MAP_PORTQ_gc = (0x0E<<0), /* Mapped To PORTQ */ - PORTCFG_VP02MAP_PORTR_gc = (0x0F<<0), /* Mapped To PORTR */ -} PORTCFG_VP02MAP_t; - -/* Virtual Port Mapping */ -typedef enum PORTCFG_VP13MAP_enum -{ - PORTCFG_VP13MAP_PORTA_gc = (0x00<<4), /* Mapped To PORTA */ - PORTCFG_VP13MAP_PORTB_gc = (0x01<<4), /* Mapped To PORTB */ - PORTCFG_VP13MAP_PORTC_gc = (0x02<<4), /* Mapped To PORTC */ - PORTCFG_VP13MAP_PORTD_gc = (0x03<<4), /* Mapped To PORTD */ - PORTCFG_VP13MAP_PORTE_gc = (0x04<<4), /* Mapped To PORTE */ - PORTCFG_VP13MAP_PORTF_gc = (0x05<<4), /* Mapped To PORTF */ - PORTCFG_VP13MAP_PORTG_gc = (0x06<<4), /* Mapped To PORTG */ - PORTCFG_VP13MAP_PORTH_gc = (0x07<<4), /* Mapped To PORTH */ - PORTCFG_VP13MAP_PORTJ_gc = (0x08<<4), /* Mapped To PORTJ */ - PORTCFG_VP13MAP_PORTK_gc = (0x09<<4), /* Mapped To PORTK */ - PORTCFG_VP13MAP_PORTL_gc = (0x0A<<4), /* Mapped To PORTL */ - PORTCFG_VP13MAP_PORTM_gc = (0x0B<<4), /* Mapped To PORTM */ - PORTCFG_VP13MAP_PORTN_gc = (0x0C<<4), /* Mapped To PORTN */ - PORTCFG_VP13MAP_PORTP_gc = (0x0D<<4), /* Mapped To PORTP */ - PORTCFG_VP13MAP_PORTQ_gc = (0x0E<<4), /* Mapped To PORTQ */ - PORTCFG_VP13MAP_PORTR_gc = (0x0F<<4), /* Mapped To PORTR */ -} PORTCFG_VP13MAP_t; - -/* System Clock Output Port */ -typedef enum PORTCFG_CLKOUT_enum -{ - PORTCFG_CLKOUT_OFF_gc = (0x00<<0), /* System Clock Output Disabled */ - PORTCFG_CLKOUT_PC7_gc = (0x01<<0), /* System Clock Output on Port C pin 7 */ - PORTCFG_CLKOUT_PD7_gc = (0x02<<0), /* System Clock Output on Port D pin 7 */ - PORTCFG_CLKOUT_PE7_gc = (0x03<<0), /* System Clock Output on Port E pin 7 */ -} PORTCFG_CLKOUT_t; - -/* Peripheral Clock Output Select */ -typedef enum PORTCFG_CLKOUTSEL_enum -{ - PORTCFG_CLKOUTSEL_CLK1X_gc = (0x00<<2), /* 1x Peripheral Clock Output to pin */ - PORTCFG_CLKOUTSEL_CLK2X_gc = (0x01<<2), /* 2x Peripheral Clock Output to pin */ - PORTCFG_CLKOUTSEL_CLK4X_gc = (0x02<<2), /* 4x Peripheral Clock Output to pin */ -} PORTCFG_CLKOUTSEL_t; - -/* Event Output Port */ -typedef enum PORTCFG_EVOUT_enum -{ - PORTCFG_EVOUT_OFF_gc = (0x00<<4), /* Event Output Disabled */ - PORTCFG_EVOUT_PC7_gc = (0x01<<4), /* Event Channel 7 Output on Port C pin 7 */ - PORTCFG_EVOUT_PD7_gc = (0x02<<4), /* Event Channel 7 Output on Port D pin 7 */ - PORTCFG_EVOUT_PE7_gc = (0x03<<4), /* Event Channel 7 Output on Port E pin 7 */ -} PORTCFG_EVOUT_t; - -/* Event Output Select */ -typedef enum PORTCFG_EVOUTSEL_enum -{ - PORTCFG_EVOUTSEL_0_gc = (0x00<<0), /* Event Channel 0 output to pin */ - PORTCFG_EVOUTSEL_1_gc = (0x01<<0), /* Event Channel 1 output to pin */ - PORTCFG_EVOUTSEL_2_gc = (0x02<<0), /* Event Channel 2 output to pin */ - PORTCFG_EVOUTSEL_3_gc = (0x03<<0), /* Event Channel 3 output to pin */ -} PORTCFG_EVOUTSEL_t; - - -/* --------------------------------------------------------------------------- -CRC - Cyclic Redundancy Checker --------------------------------------------------------------------------- -*/ - -/* Cyclic Redundancy Checker */ -typedef struct CRC_struct -{ - register8_t CTRL; /* Control Register */ - register8_t STATUS; /* Status Register */ - register8_t reserved_0x02; - register8_t DATAIN; /* Data Input */ - register8_t CHECKSUM0; /* Checksum byte 0 */ - register8_t CHECKSUM1; /* Checksum byte 1 */ - register8_t CHECKSUM2; /* Checksum byte 2 */ - register8_t CHECKSUM3; /* Checksum byte 3 */ -} CRC_t; - -/* Reset */ -typedef enum CRC_RESET_enum -{ - CRC_RESET_NO_gc = (0x00<<6), /* No Reset */ - CRC_RESET_RESET0_gc = (0x02<<6), /* Reset CRC with CHECKSUM to all zeros */ - CRC_RESET_RESET1_gc = (0x03<<6), /* Reset CRC with CHECKSUM to all ones */ -} CRC_RESET_t; - -/* Input Source */ -typedef enum CRC_SOURCE_enum -{ - CRC_SOURCE_DISABLE_gc = (0x00<<0), /* Disabled */ - CRC_SOURCE_IO_gc = (0x01<<0), /* I/O Interface */ - CRC_SOURCE_FLASH_gc = (0x02<<0), /* Flash */ -} CRC_SOURCE_t; - - -/* --------------------------------------------------------------------------- -EVSYS - Event System --------------------------------------------------------------------------- -*/ - -/* Event System */ -typedef struct EVSYS_struct -{ - register8_t CH0MUX; /* Event Channel 0 Multiplexer */ - register8_t CH1MUX; /* Event Channel 1 Multiplexer */ - register8_t CH2MUX; /* Event Channel 2 Multiplexer */ - register8_t CH3MUX; /* Event Channel 3 Multiplexer */ - register8_t reserved_0x04; - register8_t reserved_0x05; - register8_t reserved_0x06; - register8_t reserved_0x07; - register8_t CH0CTRL; /* Channel 0 Control Register */ - register8_t CH1CTRL; /* Channel 1 Control Register */ - register8_t CH2CTRL; /* Channel 2 Control Register */ - register8_t CH3CTRL; /* Channel 3 Control Register */ - register8_t reserved_0x0C; - register8_t reserved_0x0D; - register8_t reserved_0x0E; - register8_t reserved_0x0F; - register8_t STROBE; /* Event Strobe */ - register8_t DATA; /* Event Data */ -} EVSYS_t; - -/* Quadrature Decoder Index Recognition Mode */ -typedef enum EVSYS_QDIRM_enum -{ - EVSYS_QDIRM_00_gc = (0x00<<5), /* QDPH0 = 0, QDPH90 = 0 */ - EVSYS_QDIRM_01_gc = (0x01<<5), /* QDPH0 = 0, QDPH90 = 1 */ - EVSYS_QDIRM_10_gc = (0x02<<5), /* QDPH0 = 1, QDPH90 = 0 */ - EVSYS_QDIRM_11_gc = (0x03<<5), /* QDPH0 = 1, QDPH90 = 1 */ -} EVSYS_QDIRM_t; - -/* Digital filter coefficient */ -typedef enum EVSYS_DIGFILT_enum -{ - EVSYS_DIGFILT_1SAMPLE_gc = (0x00<<0), /* 1 SAMPLE */ - EVSYS_DIGFILT_2SAMPLES_gc = (0x01<<0), /* 2 SAMPLES */ - EVSYS_DIGFILT_3SAMPLES_gc = (0x02<<0), /* 3 SAMPLES */ - EVSYS_DIGFILT_4SAMPLES_gc = (0x03<<0), /* 4 SAMPLES */ - EVSYS_DIGFILT_5SAMPLES_gc = (0x04<<0), /* 5 SAMPLES */ - EVSYS_DIGFILT_6SAMPLES_gc = (0x05<<0), /* 6 SAMPLES */ - EVSYS_DIGFILT_7SAMPLES_gc = (0x06<<0), /* 7 SAMPLES */ - EVSYS_DIGFILT_8SAMPLES_gc = (0x07<<0), /* 8 SAMPLES */ -} EVSYS_DIGFILT_t; - -/* Event Channel multiplexer input selection */ -typedef enum EVSYS_CHMUX_enum -{ - EVSYS_CHMUX_OFF_gc = (0x00<<0), /* Off */ - EVSYS_CHMUX_RTC_OVF_gc = (0x08<<0), /* RTC Overflow */ - EVSYS_CHMUX_RTC_CMP_gc = (0x09<<0), /* RTC Compare Match */ - EVSYS_CHMUX_USB_gc = (0x0A<<0), /* USB Setup, SOF, CRC error and UNF/OVF */ - EVSYS_CHMUX_ACA_CH0_gc = (0x10<<0), /* Analog Comparator A Channel 0 */ - EVSYS_CHMUX_ACA_CH1_gc = (0x11<<0), /* Analog Comparator A Channel 1 */ - EVSYS_CHMUX_ACA_WIN_gc = (0x12<<0), /* Analog Comparator A Window */ - EVSYS_CHMUX_ADCA_CH0_gc = (0x20<<0), /* ADC A Channel */ - EVSYS_CHMUX_PORTA_PIN0_gc = (0x50<<0), /* Port A, Pin0 */ - EVSYS_CHMUX_PORTA_PIN1_gc = (0x51<<0), /* Port A, Pin1 */ - EVSYS_CHMUX_PORTA_PIN2_gc = (0x52<<0), /* Port A, Pin2 */ - EVSYS_CHMUX_PORTA_PIN3_gc = (0x53<<0), /* Port A, Pin3 */ - EVSYS_CHMUX_PORTA_PIN4_gc = (0x54<<0), /* Port A, Pin4 */ - EVSYS_CHMUX_PORTA_PIN5_gc = (0x55<<0), /* Port A, Pin5 */ - EVSYS_CHMUX_PORTA_PIN6_gc = (0x56<<0), /* Port A, Pin6 */ - EVSYS_CHMUX_PORTA_PIN7_gc = (0x57<<0), /* Port A, Pin7 */ - EVSYS_CHMUX_PORTB_PIN0_gc = (0x58<<0), /* Port B, Pin0 */ - EVSYS_CHMUX_PORTB_PIN1_gc = (0x59<<0), /* Port B, Pin1 */ - EVSYS_CHMUX_PORTB_PIN2_gc = (0x5A<<0), /* Port B, Pin2 */ - EVSYS_CHMUX_PORTB_PIN3_gc = (0x5B<<0), /* Port B, Pin3 */ - EVSYS_CHMUX_PORTB_PIN4_gc = (0x5C<<0), /* Port B, Pin4 */ - EVSYS_CHMUX_PORTB_PIN5_gc = (0x5D<<0), /* Port B, Pin5 */ - EVSYS_CHMUX_PORTB_PIN6_gc = (0x5E<<0), /* Port B, Pin6 */ - EVSYS_CHMUX_PORTB_PIN7_gc = (0x5F<<0), /* Port B, Pin7 */ - EVSYS_CHMUX_PORTC_PIN0_gc = (0x60<<0), /* Port C, Pin0 */ - EVSYS_CHMUX_PORTC_PIN1_gc = (0x61<<0), /* Port C, Pin1 */ - EVSYS_CHMUX_PORTC_PIN2_gc = (0x62<<0), /* Port C, Pin2 */ - EVSYS_CHMUX_PORTC_PIN3_gc = (0x63<<0), /* Port C, Pin3 */ - EVSYS_CHMUX_PORTC_PIN4_gc = (0x64<<0), /* Port C, Pin4 */ - EVSYS_CHMUX_PORTC_PIN5_gc = (0x65<<0), /* Port C, Pin5 */ - EVSYS_CHMUX_PORTC_PIN6_gc = (0x66<<0), /* Port C, Pin6 */ - EVSYS_CHMUX_PORTC_PIN7_gc = (0x67<<0), /* Port C, Pin7 */ - EVSYS_CHMUX_PORTD_PIN0_gc = (0x68<<0), /* Port D, Pin0 */ - EVSYS_CHMUX_PORTD_PIN1_gc = (0x69<<0), /* Port D, Pin1 */ - EVSYS_CHMUX_PORTD_PIN2_gc = (0x6A<<0), /* Port D, Pin2 */ - EVSYS_CHMUX_PORTD_PIN3_gc = (0x6B<<0), /* Port D, Pin3 */ - EVSYS_CHMUX_PORTD_PIN4_gc = (0x6C<<0), /* Port D, Pin4 */ - EVSYS_CHMUX_PORTD_PIN5_gc = (0x6D<<0), /* Port D, Pin5 */ - EVSYS_CHMUX_PORTD_PIN6_gc = (0x6E<<0), /* Port D, Pin6 */ - EVSYS_CHMUX_PORTD_PIN7_gc = (0x6F<<0), /* Port D, Pin7 */ - EVSYS_CHMUX_PORTE_PIN0_gc = (0x70<<0), /* Port E, Pin0 */ - EVSYS_CHMUX_PORTE_PIN1_gc = (0x71<<0), /* Port E, Pin1 */ - EVSYS_CHMUX_PORTE_PIN2_gc = (0x72<<0), /* Port E, Pin2 */ - EVSYS_CHMUX_PORTE_PIN3_gc = (0x73<<0), /* Port E, Pin3 */ - EVSYS_CHMUX_PORTE_PIN4_gc = (0x74<<0), /* Port E, Pin4 */ - EVSYS_CHMUX_PORTE_PIN5_gc = (0x75<<0), /* Port E, Pin5 */ - EVSYS_CHMUX_PORTE_PIN6_gc = (0x76<<0), /* Port E, Pin6 */ - EVSYS_CHMUX_PORTE_PIN7_gc = (0x77<<0), /* Port E, Pin7 */ - EVSYS_CHMUX_PORTF_PIN0_gc = (0x78<<0), /* Port F, Pin0 */ - EVSYS_CHMUX_PORTF_PIN1_gc = (0x79<<0), /* Port F, Pin1 */ - EVSYS_CHMUX_PORTF_PIN2_gc = (0x7A<<0), /* Port F, Pin2 */ - EVSYS_CHMUX_PORTF_PIN3_gc = (0x7B<<0), /* Port F, Pin3 */ - EVSYS_CHMUX_PORTF_PIN4_gc = (0x7C<<0), /* Port F, Pin4 */ - EVSYS_CHMUX_PORTF_PIN5_gc = (0x7D<<0), /* Port F, Pin5 */ - EVSYS_CHMUX_PORTF_PIN6_gc = (0x7E<<0), /* Port F, Pin6 */ - EVSYS_CHMUX_PORTF_PIN7_gc = (0x7F<<0), /* Port F, Pin7 */ - EVSYS_CHMUX_PRESCALER_1_gc = (0x80<<0), /* Prescaler, divide by 1 */ - EVSYS_CHMUX_PRESCALER_2_gc = (0x81<<0), /* Prescaler, divide by 2 */ - EVSYS_CHMUX_PRESCALER_4_gc = (0x82<<0), /* Prescaler, divide by 4 */ - EVSYS_CHMUX_PRESCALER_8_gc = (0x83<<0), /* Prescaler, divide by 8 */ - EVSYS_CHMUX_PRESCALER_16_gc = (0x84<<0), /* Prescaler, divide by 16 */ - EVSYS_CHMUX_PRESCALER_32_gc = (0x85<<0), /* Prescaler, divide by 32 */ - EVSYS_CHMUX_PRESCALER_64_gc = (0x86<<0), /* Prescaler, divide by 64 */ - EVSYS_CHMUX_PRESCALER_128_gc = (0x87<<0), /* Prescaler, divide by 128 */ - EVSYS_CHMUX_PRESCALER_256_gc = (0x88<<0), /* Prescaler, divide by 256 */ - EVSYS_CHMUX_PRESCALER_512_gc = (0x89<<0), /* Prescaler, divide by 512 */ - EVSYS_CHMUX_PRESCALER_1024_gc = (0x8A<<0), /* Prescaler, divide by 1024 */ - EVSYS_CHMUX_PRESCALER_2048_gc = (0x8B<<0), /* Prescaler, divide by 2048 */ - EVSYS_CHMUX_PRESCALER_4096_gc = (0x8C<<0), /* Prescaler, divide by 4096 */ - EVSYS_CHMUX_PRESCALER_8192_gc = (0x8D<<0), /* Prescaler, divide by 8192 */ - EVSYS_CHMUX_PRESCALER_16384_gc = (0x8E<<0), /* Prescaler, divide by 16384 */ - EVSYS_CHMUX_PRESCALER_32768_gc = (0x8F<<0), /* Prescaler, divide by 32768 */ - EVSYS_CHMUX_TCC0_OVF_gc = (0xC0<<0), /* Timer/Counter C0 Overflow */ - EVSYS_CHMUX_TCC0_ERR_gc = (0xC1<<0), /* Timer/Counter C0 Error */ - EVSYS_CHMUX_TCC0_CCA_gc = (0xC4<<0), /* Timer/Counter C0 Compare or Capture A */ - EVSYS_CHMUX_TCC0_CCB_gc = (0xC5<<0), /* Timer/Counter C0 Compare or Capture B */ - EVSYS_CHMUX_TCC0_CCC_gc = (0xC6<<0), /* Timer/Counter C0 Compare or Capture C */ - EVSYS_CHMUX_TCC0_CCD_gc = (0xC7<<0), /* Timer/Counter C0 Compare or Capture D */ - EVSYS_CHMUX_TCC1_OVF_gc = (0xC8<<0), /* Timer/Counter C1 Overflow */ - EVSYS_CHMUX_TCC1_ERR_gc = (0xC9<<0), /* Timer/Counter C1 Error */ - EVSYS_CHMUX_TCC1_CCA_gc = (0xCC<<0), /* Timer/Counter C1 Compare or Capture A */ - EVSYS_CHMUX_TCC1_CCB_gc = (0xCD<<0), /* Timer/Counter C1 Compare or Capture B */ - EVSYS_CHMUX_TCD0_OVF_gc = (0xD0<<0), /* Timer/Counter D0 Overflow */ - EVSYS_CHMUX_TCD0_ERR_gc = (0xD1<<0), /* Timer/Counter D0 Error */ - EVSYS_CHMUX_TCD0_CCA_gc = (0xD4<<0), /* Timer/Counter D0 Compare or Capture A */ - EVSYS_CHMUX_TCD0_CCB_gc = (0xD5<<0), /* Timer/Counter D0 Compare or Capture B */ - EVSYS_CHMUX_TCD0_CCC_gc = (0xD6<<0), /* Timer/Counter D0 Compare or Capture C */ - EVSYS_CHMUX_TCD0_CCD_gc = (0xD7<<0), /* Timer/Counter D0 Compare or Capture D */ - EVSYS_CHMUX_TCE0_OVF_gc = (0xE0<<0), /* Timer/Counter E0 Overflow */ - EVSYS_CHMUX_TCE0_ERR_gc = (0xE1<<0), /* Timer/Counter E0 Error */ - EVSYS_CHMUX_TCE0_CCA_gc = (0xE4<<0), /* Timer/Counter E0 Compare or Capture A */ - EVSYS_CHMUX_TCE0_CCB_gc = (0xE5<<0), /* Timer/Counter E0 Compare or Capture B */ - EVSYS_CHMUX_TCE0_CCC_gc = (0xE6<<0), /* Timer/Counter E0 Compare or Capture C */ - EVSYS_CHMUX_TCE0_CCD_gc = (0xE7<<0), /* Timer/Counter E0 Compare or Capture D */ - EVSYS_CHMUX_TCF0_OVF_gc = (0xF0<<0), /* Timer/Counter F0 Overflow */ - EVSYS_CHMUX_TCF0_ERR_gc = (0xF1<<0), /* Timer/Counter F0 Error */ - EVSYS_CHMUX_TCF0_CCA_gc = (0xF4<<0), /* Timer/Counter F0 Compare or Capture A */ - EVSYS_CHMUX_TCF0_CCB_gc = (0xF5<<0), /* Timer/Counter F0 Compare or Capture B */ - EVSYS_CHMUX_TCF0_CCC_gc = (0xF6<<0), /* Timer/Counter F0 Compare or Capture C */ - EVSYS_CHMUX_TCF0_CCD_gc = (0xF7<<0), /* Timer/Counter F0 Compare or Capture D */ -} EVSYS_CHMUX_t; - - -/* --------------------------------------------------------------------------- -NVM - Non Volatile Memory Controller --------------------------------------------------------------------------- -*/ - -/* Non-volatile Memory Controller */ -typedef struct NVM_struct -{ - register8_t ADDR0; /* Address Register 0 */ - register8_t ADDR1; /* Address Register 1 */ - register8_t ADDR2; /* Address Register 2 */ - register8_t reserved_0x03; - register8_t DATA0; /* Data Register 0 */ - register8_t DATA1; /* Data Register 1 */ - register8_t DATA2; /* Data Register 2 */ - register8_t reserved_0x07; - register8_t reserved_0x08; - register8_t reserved_0x09; - register8_t CMD; /* Command */ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t INTCTRL; /* Interrupt Control */ - register8_t reserved_0x0E; - register8_t STATUS; /* Status */ - register8_t LOCK_BITS; /* Lock Bits (Changed from LOCKBITS to avoid avr-libc collision) */ -} NVM_t; - -/* NVM Command */ -typedef enum NVM_CMD_enum -{ - NVM_CMD_NO_OPERATION_gc = (0x00<<0), /* Noop/Ordinary LPM */ - NVM_CMD_READ_USER_SIG_ROW_gc = (0x01<<0), /* Read user signature row */ - NVM_CMD_READ_CALIB_ROW_gc = (0x02<<0), /* Read calibration row */ - NVM_CMD_READ_EEPROM_gc = (0x06<<0), /* Read EEPROM */ - NVM_CMD_READ_FUSES_gc = (0x07<<0), /* Read fuse byte */ - NVM_CMD_WRITE_LOCK_BITS_gc = (0x08<<0), /* Write lock bits */ - NVM_CMD_ERASE_USER_SIG_ROW_gc = (0x18<<0), /* Erase user signature row */ - NVM_CMD_WRITE_USER_SIG_ROW_gc = (0x1A<<0), /* Write user signature row */ - NVM_CMD_ERASE_APP_gc = (0x20<<0), /* Erase Application Section */ - NVM_CMD_ERASE_APP_PAGE_gc = (0x22<<0), /* Erase Application Section page */ - NVM_CMD_LOAD_FLASH_BUFFER_gc = (0x23<<0), /* Load Flash page buffer */ - NVM_CMD_WRITE_APP_PAGE_gc = (0x24<<0), /* Write Application Section page */ - NVM_CMD_ERASE_WRITE_APP_PAGE_gc = (0x25<<0), /* Erase-and-write Application Section page */ - NVM_CMD_ERASE_FLASH_BUFFER_gc = (0x26<<0), /* Erase/flush Flash page buffer */ - NVM_CMD_ERASE_BOOT_PAGE_gc = (0x2A<<0), /* Erase Boot Section page */ - NVM_CMD_ERASE_FLASH_PAGE_gc = (0x2B<<0), /* Erase Flash Page */ - NVM_CMD_WRITE_BOOT_PAGE_gc = (0x2C<<0), /* Write Boot Section page */ - NVM_CMD_ERASE_WRITE_BOOT_PAGE_gc = (0x2D<<0), /* Erase-and-write Boot Section page */ - NVM_CMD_WRITE_FLASH_PAGE_gc = (0x2E<<0), /* Write Flash Page */ - NVM_CMD_ERASE_WRITE_FLASH_PAGE_gc = (0x2F<<0), /* Erase-and-write Flash Page */ - NVM_CMD_ERASE_EEPROM_gc = (0x30<<0), /* Erase EEPROM */ - NVM_CMD_ERASE_EEPROM_PAGE_gc = (0x32<<0), /* Erase EEPROM page */ - NVM_CMD_LOAD_EEPROM_BUFFER_gc = (0x33<<0), /* Load EEPROM page buffer */ - NVM_CMD_WRITE_EEPROM_PAGE_gc = (0x34<<0), /* Write EEPROM page */ - NVM_CMD_ERASE_WRITE_EEPROM_PAGE_gc = (0x35<<0), /* Erase-and-write EEPROM page */ - NVM_CMD_ERASE_EEPROM_BUFFER_gc = (0x36<<0), /* Erase/flush EEPROM page buffer */ - NVM_CMD_APP_CRC_gc = (0x38<<0), /* Application section CRC */ - NVM_CMD_BOOT_CRC_gc = (0x39<<0), /* Boot Section CRC */ - NVM_CMD_FLASH_RANGE_CRC_gc = (0x3A<<0), /* Flash Range CRC */ - NVM_CMD_CHIP_ERASE_gc = (0x40<<0), /* Erase Chip */ - NVM_CMD_READ_NVM_gc = (0x43<<0), /* Read NVM */ - NVM_CMD_WRITE_FUSE_gc = (0x4C<<0), /* Write Fuse byte */ - NVM_CMD_ERASE_BOOT_gc = (0x68<<0), /* Erase Boot Section */ - NVM_CMD_FLASH_CRC_gc = (0x78<<0), /* Flash CRC */ -} NVM_CMD_t; - -/* SPM ready interrupt level */ -typedef enum NVM_SPMLVL_enum -{ - NVM_SPMLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ - NVM_SPMLVL_LO_gc = (0x01<<2), /* Low level */ - NVM_SPMLVL_MED_gc = (0x02<<2), /* Medium level */ - NVM_SPMLVL_HI_gc = (0x03<<2), /* High level */ -} NVM_SPMLVL_t; - -/* EEPROM ready interrupt level */ -typedef enum NVM_EELVL_enum -{ - NVM_EELVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ - NVM_EELVL_LO_gc = (0x01<<0), /* Low level */ - NVM_EELVL_MED_gc = (0x02<<0), /* Medium level */ - NVM_EELVL_HI_gc = (0x03<<0), /* High level */ -} NVM_EELVL_t; - -/* Boot lock bits - boot setcion */ -typedef enum NVM_BLBB_enum -{ - NVM_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ - NVM_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ - NVM_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ - NVM_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ -} NVM_BLBB_t; - -/* Boot lock bits - application section */ -typedef enum NVM_BLBA_enum -{ - NVM_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ - NVM_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ - NVM_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ - NVM_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ -} NVM_BLBA_t; - -/* Boot lock bits - application table section */ -typedef enum NVM_BLBAT_enum -{ - NVM_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ - NVM_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ - NVM_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ - NVM_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ -} NVM_BLBAT_t; - -/* Lock bits */ -typedef enum NVM_LB_enum -{ - NVM_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ - NVM_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ - NVM_LB_NOLOCK_gc = (0x03<<0), /* No locks */ -} NVM_LB_t; - - -/* --------------------------------------------------------------------------- -ADC - Analog/Digital Converter --------------------------------------------------------------------------- -*/ - -/* ADC Channel */ -typedef struct ADC_CH_struct -{ - register8_t CTRL; /* Control Register */ - register8_t MUXCTRL; /* MUX Control */ - register8_t INTCTRL; /* Channel Interrupt Control Register */ - register8_t INTFLAGS; /* Interrupt Flags */ - _WORDREGISTER(RES); /* Channel Result */ - register8_t SCAN; /* Input Channel Scan */ - register8_t reserved_0x07; -} ADC_CH_t; - - -/* Analog-to-Digital Converter */ -typedef struct ADC_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t REFCTRL; /* Reference Control */ - register8_t EVCTRL; /* Event Control */ - register8_t PRESCALER; /* Clock Prescaler */ - register8_t reserved_0x05; - register8_t INTFLAGS; /* Interrupt Flags */ - register8_t TEMP; /* Temporary Register */ - register8_t reserved_0x08; - register8_t reserved_0x09; - register8_t reserved_0x0A; - register8_t reserved_0x0B; - _WORDREGISTER(CAL); /* Calibration Value */ - register8_t reserved_0x0E; - register8_t reserved_0x0F; - _WORDREGISTER(CH0RES); /* Channel 0 Result */ - register8_t reserved_0x12; - register8_t reserved_0x13; - register8_t reserved_0x14; - register8_t reserved_0x15; - register8_t reserved_0x16; - register8_t reserved_0x17; - _WORDREGISTER(CMP); /* Compare Value */ - register8_t reserved_0x1A; - register8_t reserved_0x1B; - register8_t reserved_0x1C; - register8_t reserved_0x1D; - register8_t reserved_0x1E; - register8_t reserved_0x1F; - ADC_CH_t CH0; /* ADC Channel 0 */ -} ADC_t; - -/* Current Limitation */ -typedef enum ADC_CURRLIMIT_enum -{ - ADC_CURRLIMIT_NO_gc = (0x00<<5), /* No current limit, 300ksps max sampling rate */ - ADC_CURRLIMIT_LOW_gc = (0x01<<5), /* Low current limit, 250ksps max sampling rate */ - ADC_CURRLIMIT_MED_gc = (0x02<<5), /* Medium current limit, 150ksps max sampling rate */ - ADC_CURRLIMIT_HIGH_gc = (0x03<<5), /* High current limit, 50ksps max sampling rate */ -} ADC_CURRLIMIT_t; - -/* Positive input multiplexer selection */ -typedef enum ADC_CH_MUXPOS_enum -{ - ADC_CH_MUXPOS_PIN0_gc = (0x00<<3), /* Input pin 0 */ - ADC_CH_MUXPOS_PIN1_gc = (0x01<<3), /* Input pin 1 */ - ADC_CH_MUXPOS_PIN2_gc = (0x02<<3), /* Input pin 2 */ - ADC_CH_MUXPOS_PIN3_gc = (0x03<<3), /* Input pin 3 */ - ADC_CH_MUXPOS_PIN4_gc = (0x04<<3), /* Input pin 4 */ - ADC_CH_MUXPOS_PIN5_gc = (0x05<<3), /* Input pin 5 */ - ADC_CH_MUXPOS_PIN6_gc = (0x06<<3), /* Input pin 6 */ - ADC_CH_MUXPOS_PIN7_gc = (0x07<<3), /* Input pin 7 */ - ADC_CH_MUXPOS_PIN8_gc = (0x08<<3), /* Input pin 8 */ - ADC_CH_MUXPOS_PIN9_gc = (0x09<<3), /* Input pin 9 */ - ADC_CH_MUXPOS_PIN10_gc = (0x0A<<3), /* Input pin 10 */ - ADC_CH_MUXPOS_PIN11_gc = (0x0B<<3), /* Input pin 11 */ - ADC_CH_MUXPOS_PIN12_gc = (0x0C<<3), /* Input pin 12 */ - ADC_CH_MUXPOS_PIN13_gc = (0x0D<<3), /* Input pin 13 */ - ADC_CH_MUXPOS_PIN14_gc = (0x0E<<3), /* Input pin 14 */ - ADC_CH_MUXPOS_PIN15_gc = (0x0F<<3), /* Input pin 15 */ -} ADC_CH_MUXPOS_t; - -/* Internal input multiplexer selections */ -typedef enum ADC_CH_MUXINT_enum -{ - ADC_CH_MUXINT_TEMP_gc = (0x00<<3), /* Temperature Reference */ - ADC_CH_MUXINT_BANDGAP_gc = (0x01<<3), /* Bandgap Reference */ - ADC_CH_MUXINT_SCALEDVCC_gc = (0x02<<3), /* 1/10 scaled VCC */ -} ADC_CH_MUXINT_t; - -/* Negative input multiplexer selection */ -typedef enum ADC_CH_MUXNEG_enum -{ - ADC_CH_MUXNEG_PIN0_gc = (0x00<<0), /* Input pin 0 */ - ADC_CH_MUXNEG_PIN1_gc = (0x01<<0), /* Input pin 1 */ - ADC_CH_MUXNEG_PIN2_gc = (0x02<<0), /* Input pin 2 */ - ADC_CH_MUXNEG_PIN3_gc = (0x03<<0), /* Input pin 3 */ - ADC_CH_MUXNEG_PIN4_gc = (0x00<<0), /* Input pin 4 */ - ADC_CH_MUXNEG_PIN5_gc = (0x01<<0), /* Input pin 5 */ - ADC_CH_MUXNEG_PIN6_gc = (0x02<<0), /* Input pin 6 */ - ADC_CH_MUXNEG_PIN7_gc = (0x03<<0), /* Input pin 7 */ -} ADC_CH_MUXNEG_t; - -/* Input mode */ -typedef enum ADC_CH_INPUTMODE_enum -{ - ADC_CH_INPUTMODE_INTERNAL_gc = (0x00<<0), /* Internal inputs, no gain */ - ADC_CH_INPUTMODE_SINGLEENDED_gc = (0x01<<0), /* Single-ended input, no gain */ - ADC_CH_INPUTMODE_DIFF_gc = (0x02<<0), /* Differential input, no gain */ - ADC_CH_INPUTMODE_DIFFWGAIN_gc = (0x03<<0), /* Differential input, with gain */ -} ADC_CH_INPUTMODE_t; - -/* Gain factor */ -typedef enum ADC_CH_GAIN_enum -{ - ADC_CH_GAIN_1X_gc = (0x00<<2), /* 1x gain */ - ADC_CH_GAIN_2X_gc = (0x01<<2), /* 2x gain */ - ADC_CH_GAIN_4X_gc = (0x02<<2), /* 4x gain */ - ADC_CH_GAIN_8X_gc = (0x03<<2), /* 8x gain */ - ADC_CH_GAIN_16X_gc = (0x04<<2), /* 16x gain */ - ADC_CH_GAIN_32X_gc = (0x05<<2), /* 32x gain */ - ADC_CH_GAIN_64X_gc = (0x06<<2), /* 64x gain */ - ADC_CH_GAIN_DIV2_gc = (0x07<<2), /* x/2 gain */ -} ADC_CH_GAIN_t; - -/* Conversion result resolution */ -typedef enum ADC_RESOLUTION_enum -{ - ADC_RESOLUTION_12BIT_gc = (0x00<<1), /* 12-bit right-adjusted result */ - ADC_RESOLUTION_8BIT_gc = (0x02<<1), /* 8-bit right-adjusted result */ - ADC_RESOLUTION_LEFT12BIT_gc = (0x03<<1), /* 12-bit left-adjusted result */ -} ADC_RESOLUTION_t; - -/* Voltage reference selection */ -typedef enum ADC_REFSEL_enum -{ - ADC_REFSEL_INT1V_gc = (0x00<<4), /* Internal 1V */ - ADC_REFSEL_INTVCC_gc = (0x01<<4), /* Internal VCC / 1.6 */ - ADC_REFSEL_AREFA_gc = (0x02<<4), /* External reference on PORT A */ - ADC_REFSEL_AREFB_gc = (0x03<<4), /* External reference on PORT B */ - ADC_REFSEL_INTVCC2_gc = (0x04<<4), /* Internal VCC / 2 */ -} ADC_REFSEL_t; - -/* Event channel input selection */ -typedef enum ADC_EVSEL_enum -{ - ADC_EVSEL_0_gc = (0x00<<3), /* Event Channel 0 */ - ADC_EVSEL_1_gc = (0x01<<3), /* Event Channel 1 */ - ADC_EVSEL_2_gc = (0x02<<3), /* Event Channel 2 */ - ADC_EVSEL_3_gc = (0x03<<3), /* Event Channel 3 */ -} ADC_EVSEL_t; - -/* Event action selection */ -typedef enum ADC_EVACT_enum -{ - ADC_EVACT_NONE_gc = (0x00<<0), /* No event action */ - ADC_EVACT_CH0_gc = (0x01<<0), /* First event triggers channel 0 */ - ADC_EVACT_SYNCSWEEP_gc = (0x06<<0), /* The ADC is flushed and restarted for accurate timing */ -} ADC_EVACT_t; - -/* Interupt mode */ -typedef enum ADC_CH_INTMODE_enum -{ - ADC_CH_INTMODE_COMPLETE_gc = (0x00<<2), /* Interrupt on conversion complete */ - ADC_CH_INTMODE_BELOW_gc = (0x01<<2), /* Interrupt on result below compare value */ - ADC_CH_INTMODE_ABOVE_gc = (0x03<<2), /* Interrupt on result above compare value */ -} ADC_CH_INTMODE_t; - -/* Interrupt level */ -typedef enum ADC_CH_INTLVL_enum -{ - ADC_CH_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ - ADC_CH_INTLVL_LO_gc = (0x01<<0), /* Low level */ - ADC_CH_INTLVL_MED_gc = (0x02<<0), /* Medium level */ - ADC_CH_INTLVL_HI_gc = (0x03<<0), /* High level */ -} ADC_CH_INTLVL_t; - -/* Clock prescaler */ -typedef enum ADC_PRESCALER_enum -{ - ADC_PRESCALER_DIV4_gc = (0x00<<0), /* Divide clock by 4 */ - ADC_PRESCALER_DIV8_gc = (0x01<<0), /* Divide clock by 8 */ - ADC_PRESCALER_DIV16_gc = (0x02<<0), /* Divide clock by 16 */ - ADC_PRESCALER_DIV32_gc = (0x03<<0), /* Divide clock by 32 */ - ADC_PRESCALER_DIV64_gc = (0x04<<0), /* Divide clock by 64 */ - ADC_PRESCALER_DIV128_gc = (0x05<<0), /* Divide clock by 128 */ - ADC_PRESCALER_DIV256_gc = (0x06<<0), /* Divide clock by 256 */ - ADC_PRESCALER_DIV512_gc = (0x07<<0), /* Divide clock by 512 */ -} ADC_PRESCALER_t; - - -/* --------------------------------------------------------------------------- -AC - Analog Comparator --------------------------------------------------------------------------- -*/ - -/* Analog Comparator */ -typedef struct AC_struct -{ - register8_t AC0CTRL; /* Analog Comparator 0 Control */ - register8_t AC1CTRL; /* Analog Comparator 1 Control */ - register8_t AC0MUXCTRL; /* Analog Comparator 0 MUX Control */ - register8_t AC1MUXCTRL; /* Analog Comparator 1 MUX Control */ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t WINCTRL; /* Window Mode Control */ - register8_t STATUS; /* Status */ -} AC_t; - -/* Interrupt mode */ -typedef enum AC_INTMODE_enum -{ - AC_INTMODE_BOTHEDGES_gc = (0x00<<6), /* Interrupt on both edges */ - AC_INTMODE_FALLING_gc = (0x02<<6), /* Interrupt on falling edge */ - AC_INTMODE_RISING_gc = (0x03<<6), /* Interrupt on rising edge */ -} AC_INTMODE_t; - -/* Interrupt level */ -typedef enum AC_INTLVL_enum -{ - AC_INTLVL_OFF_gc = (0x00<<4), /* Interrupt disabled */ - AC_INTLVL_LO_gc = (0x01<<4), /* Low level */ - AC_INTLVL_MED_gc = (0x02<<4), /* Medium level */ - AC_INTLVL_HI_gc = (0x03<<4), /* High level */ -} AC_INTLVL_t; - -/* Hysteresis mode selection */ -typedef enum AC_HYSMODE_enum -{ - AC_HYSMODE_NO_gc = (0x00<<1), /* No hysteresis */ - AC_HYSMODE_SMALL_gc = (0x01<<1), /* Small hysteresis */ - AC_HYSMODE_LARGE_gc = (0x02<<1), /* Large hysteresis */ -} AC_HYSMODE_t; - -/* Positive input multiplexer selection */ -typedef enum AC_MUXPOS_enum -{ - AC_MUXPOS_PIN0_gc = (0x00<<3), /* Pin 0 */ - AC_MUXPOS_PIN1_gc = (0x01<<3), /* Pin 1 */ - AC_MUXPOS_PIN2_gc = (0x02<<3), /* Pin 2 */ - AC_MUXPOS_PIN3_gc = (0x03<<3), /* Pin 3 */ - AC_MUXPOS_PIN4_gc = (0x04<<3), /* Pin 4 */ - AC_MUXPOS_PIN5_gc = (0x05<<3), /* Pin 5 */ - AC_MUXPOS_PIN6_gc = (0x06<<3), /* Pin 6 */ -} AC_MUXPOS_t; - -/* Negative input multiplexer selection */ -typedef enum AC_MUXNEG_enum -{ - AC_MUXNEG_PIN0_gc = (0x00<<0), /* Pin 0 */ - AC_MUXNEG_PIN1_gc = (0x01<<0), /* Pin 1 */ - AC_MUXNEG_PIN3_gc = (0x02<<0), /* Pin 3 */ - AC_MUXNEG_PIN5_gc = (0x03<<0), /* Pin 5 */ - AC_MUXNEG_PIN7_gc = (0x04<<0), /* Pin 7 */ - AC_MUXNEG_BANDGAP_gc = (0x06<<0), /* Bandgap Reference */ - AC_MUXNEG_SCALER_gc = (0x07<<0), /* Internal voltage scaler */ -} AC_MUXNEG_t; - -/* Windows interrupt mode */ -typedef enum AC_WINTMODE_enum -{ - AC_WINTMODE_ABOVE_gc = (0x00<<2), /* Interrupt on above window */ - AC_WINTMODE_INSIDE_gc = (0x01<<2), /* Interrupt on inside window */ - AC_WINTMODE_BELOW_gc = (0x02<<2), /* Interrupt on below window */ - AC_WINTMODE_OUTSIDE_gc = (0x03<<2), /* Interrupt on outside window */ -} AC_WINTMODE_t; - -/* Window interrupt level */ -typedef enum AC_WINTLVL_enum -{ - AC_WINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ - AC_WINTLVL_LO_gc = (0x01<<0), /* Low priority */ - AC_WINTLVL_MED_gc = (0x02<<0), /* Medium priority */ - AC_WINTLVL_HI_gc = (0x03<<0), /* High priority */ -} AC_WINTLVL_t; - -/* Window mode state */ -typedef enum AC_WSTATE_enum -{ - AC_WSTATE_ABOVE_gc = (0x00<<6), /* Signal above window */ - AC_WSTATE_INSIDE_gc = (0x01<<6), /* Signal inside window */ - AC_WSTATE_BELOW_gc = (0x02<<6), /* Signal below window */ -} AC_WSTATE_t; - - -/* --------------------------------------------------------------------------- -RTC - Real-Time Counter --------------------------------------------------------------------------- -*/ - -/* Real-Time Counter */ -typedef struct RTC_struct -{ - register8_t CTRL; /* Control Register */ - register8_t STATUS; /* Status Register */ - register8_t INTCTRL; /* Interrupt Control Register */ - register8_t INTFLAGS; /* Interrupt Flags */ - register8_t TEMP; /* Temporary register */ - register8_t reserved_0x05; - register8_t reserved_0x06; - register8_t reserved_0x07; - _WORDREGISTER(CNT); /* Count Register */ - _WORDREGISTER(PER); /* Period Register */ - _WORDREGISTER(COMP); /* Compare Register */ -} RTC_t; - -/* Prescaler Factor */ -typedef enum RTC_PRESCALER_enum -{ - RTC_PRESCALER_OFF_gc = (0x00<<0), /* RTC Off */ - RTC_PRESCALER_DIV1_gc = (0x01<<0), /* RTC Clock */ - RTC_PRESCALER_DIV2_gc = (0x02<<0), /* RTC Clock / 2 */ - RTC_PRESCALER_DIV8_gc = (0x03<<0), /* RTC Clock / 8 */ - RTC_PRESCALER_DIV16_gc = (0x04<<0), /* RTC Clock / 16 */ - RTC_PRESCALER_DIV64_gc = (0x05<<0), /* RTC Clock / 64 */ - RTC_PRESCALER_DIV256_gc = (0x06<<0), /* RTC Clock / 256 */ - RTC_PRESCALER_DIV1024_gc = (0x07<<0), /* RTC Clock / 1024 */ -} RTC_PRESCALER_t; - -/* Compare Interrupt level */ -typedef enum RTC_COMPINTLVL_enum -{ - RTC_COMPINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ - RTC_COMPINTLVL_LO_gc = (0x01<<2), /* Low Level */ - RTC_COMPINTLVL_MED_gc = (0x02<<2), /* Medium Level */ - RTC_COMPINTLVL_HI_gc = (0x03<<2), /* High Level */ -} RTC_COMPINTLVL_t; - -/* Overflow Interrupt level */ -typedef enum RTC_OVFINTLVL_enum -{ - RTC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - RTC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ - RTC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ - RTC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ -} RTC_OVFINTLVL_t; - - -/* --------------------------------------------------------------------------- -TWI - Two-Wire Interface --------------------------------------------------------------------------- -*/ - -/* */ -typedef struct TWI_MASTER_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t CTRLC; /* Control Register C */ - register8_t STATUS; /* Status Register */ - register8_t BAUD; /* Baurd Rate Control Register */ - register8_t ADDR; /* Address Register */ - register8_t DATA; /* Data Register */ -} TWI_MASTER_t; - - -/* */ -typedef struct TWI_SLAVE_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t STATUS; /* Status Register */ - register8_t ADDR; /* Address Register */ - register8_t DATA; /* Data Register */ - register8_t ADDRMASK; /* Address Mask Register */ -} TWI_SLAVE_t; - - -/* Two-Wire Interface */ -typedef struct TWI_struct -{ - register8_t CTRL; /* TWI Common Control Register */ - TWI_MASTER_t MASTER; /* TWI master module */ - TWI_SLAVE_t SLAVE; /* TWI slave module */ -} TWI_t; - -/* SDA Hold Time */ -typedef enum TWI_SDAHOLD_enum -{ - TWI_SDAHOLD_OFF_gc = (0x00<<1), /* SDA Hold Time off */ - TWI_SDAHOLD_50NS_gc = (0x01<<1), /* SDA Hold Time 50 ns */ - TWI_SDAHOLD_300NS_gc = (0x02<<1), /* SDA Hold Time 300 ns */ - TWI_SDAHOLD_400NS_gc = (0x03<<1), /* SDA Hold Time 400 ns */ -} TWI_SDAHOLD_t; - -/* Master Interrupt Level */ -typedef enum TWI_MASTER_INTLVL_enum -{ - TWI_MASTER_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ - TWI_MASTER_INTLVL_LO_gc = (0x01<<6), /* Low Level */ - TWI_MASTER_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ - TWI_MASTER_INTLVL_HI_gc = (0x03<<6), /* High Level */ -} TWI_MASTER_INTLVL_t; - -/* Inactive Timeout */ -typedef enum TWI_MASTER_TIMEOUT_enum -{ - TWI_MASTER_TIMEOUT_DISABLED_gc = (0x00<<2), /* Bus Timeout Disabled */ - TWI_MASTER_TIMEOUT_50US_gc = (0x01<<2), /* 50 Microseconds */ - TWI_MASTER_TIMEOUT_100US_gc = (0x02<<2), /* 100 Microseconds */ - TWI_MASTER_TIMEOUT_200US_gc = (0x03<<2), /* 200 Microseconds */ -} TWI_MASTER_TIMEOUT_t; - -/* Master Command */ -typedef enum TWI_MASTER_CMD_enum -{ - TWI_MASTER_CMD_NOACT_gc = (0x00<<0), /* No Action */ - TWI_MASTER_CMD_REPSTART_gc = (0x01<<0), /* Issue Repeated Start Condition */ - TWI_MASTER_CMD_RECVTRANS_gc = (0x02<<0), /* Receive or Transmit Data */ - TWI_MASTER_CMD_STOP_gc = (0x03<<0), /* Issue Stop Condition */ -} TWI_MASTER_CMD_t; - -/* Master Bus State */ -typedef enum TWI_MASTER_BUSSTATE_enum -{ - TWI_MASTER_BUSSTATE_UNKNOWN_gc = (0x00<<0), /* Unknown Bus State */ - TWI_MASTER_BUSSTATE_IDLE_gc = (0x01<<0), /* Bus is Idle */ - TWI_MASTER_BUSSTATE_OWNER_gc = (0x02<<0), /* This Module Controls The Bus */ - TWI_MASTER_BUSSTATE_BUSY_gc = (0x03<<0), /* The Bus is Busy */ -} TWI_MASTER_BUSSTATE_t; - -/* Slave Interrupt Level */ -typedef enum TWI_SLAVE_INTLVL_enum -{ - TWI_SLAVE_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ - TWI_SLAVE_INTLVL_LO_gc = (0x01<<6), /* Low Level */ - TWI_SLAVE_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ - TWI_SLAVE_INTLVL_HI_gc = (0x03<<6), /* High Level */ -} TWI_SLAVE_INTLVL_t; - -/* Slave Command */ -typedef enum TWI_SLAVE_CMD_enum -{ - TWI_SLAVE_CMD_NOACT_gc = (0x00<<0), /* No Action */ - TWI_SLAVE_CMD_COMPTRANS_gc = (0x02<<0), /* Used To Complete a Transaction */ - TWI_SLAVE_CMD_RESPONSE_gc = (0x03<<0), /* Used in Response to Address/Data Interrupt */ -} TWI_SLAVE_CMD_t; - - -/* --------------------------------------------------------------------------- -USB - USB --------------------------------------------------------------------------- -*/ - -/* USB Endpoint */ -typedef struct USB_EP_struct -{ - register8_t STATUS; /* Endpoint Status */ - register8_t CTRL; /* Endpoint Control */ - _WORDREGISTER(CNT); /* USB Endpoint Counter */ - _WORDREGISTER(DATAPTR); /* Data Pointer */ - _WORDREGISTER(AUXDATA); /* Auxiliary Data */ -} USB_EP_t; - - -/* Universal Serial Bus */ -typedef struct USB_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t STATUS; /* Status Register */ - register8_t ADDR; /* Address Register */ - register8_t FIFOWP; /* FIFO Write Pointer Register */ - register8_t FIFORP; /* FIFO Read Pointer Register */ - _WORDREGISTER(EPPTR); /* Endpoint Configuration Table Pointer */ - register8_t INTCTRLA; /* Interrupt Control Register A */ - register8_t INTCTRLB; /* Interrupt Control Register B */ - register8_t INTFLAGSACLR; /* Clear Interrupt Flag Register A */ - register8_t INTFLAGSASET; /* Set Interrupt Flag Register A */ - register8_t INTFLAGSBCLR; /* Clear Interrupt Flag Register B */ - register8_t INTFLAGSBSET; /* Set Interrupt Flag Register B */ - register8_t reserved_0x0E; - register8_t reserved_0x0F; - register8_t reserved_0x10; - register8_t reserved_0x11; - register8_t reserved_0x12; - register8_t reserved_0x13; - register8_t reserved_0x14; - register8_t reserved_0x15; - register8_t reserved_0x16; - register8_t reserved_0x17; - register8_t reserved_0x18; - register8_t reserved_0x19; - register8_t reserved_0x1A; - register8_t reserved_0x1B; - register8_t reserved_0x1C; - register8_t reserved_0x1D; - register8_t reserved_0x1E; - register8_t reserved_0x1F; - register8_t reserved_0x20; - register8_t reserved_0x21; - register8_t reserved_0x22; - register8_t reserved_0x23; - register8_t reserved_0x24; - register8_t reserved_0x25; - register8_t reserved_0x26; - register8_t reserved_0x27; - register8_t reserved_0x28; - register8_t reserved_0x29; - register8_t reserved_0x2A; - register8_t reserved_0x2B; - register8_t reserved_0x2C; - register8_t reserved_0x2D; - register8_t reserved_0x2E; - register8_t reserved_0x2F; - register8_t reserved_0x30; - register8_t reserved_0x31; - register8_t reserved_0x32; - register8_t reserved_0x33; - register8_t reserved_0x34; - register8_t reserved_0x35; - register8_t reserved_0x36; - register8_t reserved_0x37; - register8_t reserved_0x38; - register8_t reserved_0x39; - register8_t CAL0; /* Calibration Byte 0 */ - register8_t CAL1; /* Calibration Byte 1 */ -} USB_t; - - -/* USB Endpoint Table */ -typedef struct USB_EP_TABLE_struct -{ - USB_EP_t EP0OUT; /* Endpoint 0 */ - USB_EP_t EP0IN; /* Endpoint 0 */ - USB_EP_t EP1OUT; /* Endpoint 1 */ - USB_EP_t EP1IN; /* Endpoint 1 */ - USB_EP_t EP2OUT; /* Endpoint 2 */ - USB_EP_t EP2IN; /* Endpoint 2 */ - USB_EP_t EP3OUT; /* Endpoint 3 */ - USB_EP_t EP3IN; /* Endpoint 3 */ - USB_EP_t EP4OUT; /* Endpoint 4 */ - USB_EP_t EP4IN; /* Endpoint 4 */ - USB_EP_t EP5OUT; /* Endpoint 5 */ - USB_EP_t EP5IN; /* Endpoint 5 */ - USB_EP_t EP6OUT; /* Endpoint 6 */ - USB_EP_t EP6IN; /* Endpoint 6 */ - USB_EP_t EP7OUT; /* Endpoint 7 */ - USB_EP_t EP7IN; /* Endpoint 7 */ - USB_EP_t EP8OUT; /* Endpoint 8 */ - USB_EP_t EP8IN; /* Endpoint 8 */ - USB_EP_t EP9OUT; /* Endpoint 9 */ - USB_EP_t EP9IN; /* Endpoint 9 */ - USB_EP_t EP10OUT; /* Endpoint 10 */ - USB_EP_t EP10IN; /* Endpoint 10 */ - USB_EP_t EP11OUT; /* Endpoint 11 */ - USB_EP_t EP11IN; /* Endpoint 11 */ - USB_EP_t EP12OUT; /* Endpoint 12 */ - USB_EP_t EP12IN; /* Endpoint 12 */ - USB_EP_t EP13OUT; /* Endpoint 13 */ - USB_EP_t EP13IN; /* Endpoint 13 */ - USB_EP_t EP14OUT; /* Endpoint 14 */ - USB_EP_t EP14IN; /* Endpoint 14 */ - USB_EP_t EP15OUT; /* Endpoint 15 */ - USB_EP_t EP15IN; /* Endpoint 15 */ - register8_t reserved_0x100; - register8_t reserved_0x101; - register8_t reserved_0x102; - register8_t reserved_0x103; - register8_t reserved_0x104; - register8_t reserved_0x105; - register8_t reserved_0x106; - register8_t reserved_0x107; - register8_t reserved_0x108; - register8_t reserved_0x109; - register8_t reserved_0x10A; - register8_t reserved_0x10B; - register8_t reserved_0x10C; - register8_t reserved_0x10D; - register8_t reserved_0x10E; - register8_t reserved_0x10F; - register8_t FRAMENUML; /* Frame Number Low Byte */ - register8_t FRAMENUMH; /* Frame Number High Byte */ -} USB_EP_TABLE_t; - -/* Interrupt level */ -typedef enum USB_INTLVL_enum -{ - USB_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ - USB_INTLVL_LO_gc = (0x01<<0), /* Low level */ - USB_INTLVL_MED_gc = (0x02<<0), /* Medium level */ - USB_INTLVL_HI_gc = (0x03<<0), /* High level */ -} USB_INTLVL_t; - -/* USB Endpoint Type */ -typedef enum USB_EP_TYPE_enum -{ - USB_EP_TYPE_DISABLE_gc = (0x00<<6), /* Endpoint Disabled */ - USB_EP_TYPE_CONTROL_gc = (0x01<<6), /* Control */ - USB_EP_TYPE_BULK_gc = (0x02<<6), /* Bulk/Interrupt */ - USB_EP_TYPE_ISOCHRONOUS_gc = (0x03<<6), /* Isochronous */ -} USB_EP_TYPE_t; - -/* USB Endpoint Buffersize */ -typedef enum USB_EP_BUFSIZE_enum -{ - USB_EP_BUFSIZE_8_gc = (0x00<<0), /* 8 bytes buffer size */ - USB_EP_BUFSIZE_16_gc = (0x01<<0), /* 16 bytes buffer size */ - USB_EP_BUFSIZE_32_gc = (0x02<<0), /* 32 bytes buffer size */ - USB_EP_BUFSIZE_64_gc = (0x03<<0), /* 64 bytes buffer size */ - USB_EP_BUFSIZE_128_gc = (0x04<<0), /* 128 bytes buffer size */ - USB_EP_BUFSIZE_256_gc = (0x05<<0), /* 256 bytes buffer size */ - USB_EP_BUFSIZE_512_gc = (0x06<<0), /* 512 bytes buffer size */ - USB_EP_BUFSIZE_1023_gc = (0x07<<0), /* 1023 bytes buffer size */ -} USB_EP_BUFSIZE_t; - - -/* --------------------------------------------------------------------------- -PORT - I/O Port Configuration --------------------------------------------------------------------------- -*/ - -/* I/O Ports */ -typedef struct PORT_struct -{ - register8_t DIR; /* I/O Port Data Direction */ - register8_t DIRSET; /* I/O Port Data Direction Set */ - register8_t DIRCLR; /* I/O Port Data Direction Clear */ - register8_t DIRTGL; /* I/O Port Data Direction Toggle */ - register8_t OUT; /* I/O Port Output */ - register8_t OUTSET; /* I/O Port Output Set */ - register8_t OUTCLR; /* I/O Port Output Clear */ - register8_t OUTTGL; /* I/O Port Output Toggle */ - register8_t IN; /* I/O port Input */ - register8_t INTCTRL; /* Interrupt Control Register */ - register8_t INT0MASK; /* Port Interrupt 0 Mask */ - register8_t INT1MASK; /* Port Interrupt 1 Mask */ - register8_t INTFLAGS; /* Interrupt Flag Register */ - register8_t reserved_0x0D; - register8_t REMAP; /* I/O Port Pin Remap Register */ - register8_t reserved_0x0F; - register8_t PIN0CTRL; /* Pin 0 Control Register */ - register8_t PIN1CTRL; /* Pin 1 Control Register */ - register8_t PIN2CTRL; /* Pin 2 Control Register */ - register8_t PIN3CTRL; /* Pin 3 Control Register */ - register8_t PIN4CTRL; /* Pin 4 Control Register */ - register8_t PIN5CTRL; /* Pin 5 Control Register */ - register8_t PIN6CTRL; /* Pin 6 Control Register */ - register8_t PIN7CTRL; /* Pin 7 Control Register */ -} PORT_t; - -/* Port Interrupt 0 Level */ -typedef enum PORT_INT0LVL_enum -{ - PORT_INT0LVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - PORT_INT0LVL_LO_gc = (0x01<<0), /* Low Level */ - PORT_INT0LVL_MED_gc = (0x02<<0), /* Medium Level */ - PORT_INT0LVL_HI_gc = (0x03<<0), /* High Level */ -} PORT_INT0LVL_t; - -/* Port Interrupt 1 Level */ -typedef enum PORT_INT1LVL_enum -{ - PORT_INT1LVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ - PORT_INT1LVL_LO_gc = (0x01<<2), /* Low Level */ - PORT_INT1LVL_MED_gc = (0x02<<2), /* Medium Level */ - PORT_INT1LVL_HI_gc = (0x03<<2), /* High Level */ -} PORT_INT1LVL_t; - -/* Output/Pull Configuration */ -typedef enum PORT_OPC_enum -{ - PORT_OPC_TOTEM_gc = (0x00<<3), /* Totempole */ - PORT_OPC_BUSKEEPER_gc = (0x01<<3), /* Totempole w/ Bus keeper on Input and Output */ - PORT_OPC_PULLDOWN_gc = (0x02<<3), /* Totempole w/ Pull-down on Input */ - PORT_OPC_PULLUP_gc = (0x03<<3), /* Totempole w/ Pull-up on Input */ - PORT_OPC_WIREDOR_gc = (0x04<<3), /* Wired OR */ - PORT_OPC_WIREDAND_gc = (0x05<<3), /* Wired AND */ - PORT_OPC_WIREDORPULL_gc = (0x06<<3), /* Wired OR w/ Pull-down */ - PORT_OPC_WIREDANDPULL_gc = (0x07<<3), /* Wired AND w/ Pull-up */ -} PORT_OPC_t; - -/* Input/Sense Configuration */ -typedef enum PORT_ISC_enum -{ - PORT_ISC_BOTHEDGES_gc = (0x00<<0), /* Sense Both Edges */ - PORT_ISC_RISING_gc = (0x01<<0), /* Sense Rising Edge */ - PORT_ISC_FALLING_gc = (0x02<<0), /* Sense Falling Edge */ - PORT_ISC_LEVEL_gc = (0x03<<0), /* Sense Level (Transparent For Events) */ - PORT_ISC_INPUT_DISABLE_gc = (0x07<<0), /* Disable Digital Input Buffer */ -} PORT_ISC_t; - - -/* --------------------------------------------------------------------------- -TC - 16-bit Timer/Counter With PWM --------------------------------------------------------------------------- -*/ - -/* 16-bit Timer/Counter 0 */ -typedef struct TC0_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t CTRLC; /* Control register C */ - register8_t CTRLD; /* Control Register D */ - register8_t CTRLE; /* Control Register E */ - register8_t reserved_0x05; - register8_t INTCTRLA; /* Interrupt Control Register A */ - register8_t INTCTRLB; /* Interrupt Control Register B */ - register8_t CTRLFCLR; /* Control Register F Clear */ - register8_t CTRLFSET; /* Control Register F Set */ - register8_t CTRLGCLR; /* Control Register G Clear */ - register8_t CTRLGSET; /* Control Register G Set */ - register8_t INTFLAGS; /* Interrupt Flag Register */ - register8_t reserved_0x0D; - register8_t reserved_0x0E; - register8_t TEMP; /* Temporary Register For 16-bit Access */ - register8_t reserved_0x10; - register8_t reserved_0x11; - register8_t reserved_0x12; - register8_t reserved_0x13; - register8_t reserved_0x14; - register8_t reserved_0x15; - register8_t reserved_0x16; - register8_t reserved_0x17; - register8_t reserved_0x18; - register8_t reserved_0x19; - register8_t reserved_0x1A; - register8_t reserved_0x1B; - register8_t reserved_0x1C; - register8_t reserved_0x1D; - register8_t reserved_0x1E; - register8_t reserved_0x1F; - _WORDREGISTER(CNT); /* Count */ - register8_t reserved_0x22; - register8_t reserved_0x23; - register8_t reserved_0x24; - register8_t reserved_0x25; - _WORDREGISTER(PER); /* Period */ - _WORDREGISTER(CCA); /* Compare or Capture A */ - _WORDREGISTER(CCB); /* Compare or Capture B */ - _WORDREGISTER(CCC); /* Compare or Capture C */ - _WORDREGISTER(CCD); /* Compare or Capture D */ - register8_t reserved_0x30; - register8_t reserved_0x31; - register8_t reserved_0x32; - register8_t reserved_0x33; - register8_t reserved_0x34; - register8_t reserved_0x35; - _WORDREGISTER(PERBUF); /* Period Buffer */ - _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ - _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ - _WORDREGISTER(CCCBUF); /* Compare Or Capture C Buffer */ - _WORDREGISTER(CCDBUF); /* Compare Or Capture D Buffer */ -} TC0_t; - - -/* 16-bit Timer/Counter 1 */ -typedef struct TC1_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t CTRLC; /* Control register C */ - register8_t CTRLD; /* Control Register D */ - register8_t CTRLE; /* Control Register E */ - register8_t reserved_0x05; - register8_t INTCTRLA; /* Interrupt Control Register A */ - register8_t INTCTRLB; /* Interrupt Control Register B */ - register8_t CTRLFCLR; /* Control Register F Clear */ - register8_t CTRLFSET; /* Control Register F Set */ - register8_t CTRLGCLR; /* Control Register G Clear */ - register8_t CTRLGSET; /* Control Register G Set */ - register8_t INTFLAGS; /* Interrupt Flag Register */ - register8_t reserved_0x0D; - register8_t reserved_0x0E; - register8_t TEMP; /* Temporary Register For 16-bit Access */ - register8_t reserved_0x10; - register8_t reserved_0x11; - register8_t reserved_0x12; - register8_t reserved_0x13; - register8_t reserved_0x14; - register8_t reserved_0x15; - register8_t reserved_0x16; - register8_t reserved_0x17; - register8_t reserved_0x18; - register8_t reserved_0x19; - register8_t reserved_0x1A; - register8_t reserved_0x1B; - register8_t reserved_0x1C; - register8_t reserved_0x1D; - register8_t reserved_0x1E; - register8_t reserved_0x1F; - _WORDREGISTER(CNT); /* Count */ - register8_t reserved_0x22; - register8_t reserved_0x23; - register8_t reserved_0x24; - register8_t reserved_0x25; - _WORDREGISTER(PER); /* Period */ - _WORDREGISTER(CCA); /* Compare or Capture A */ - _WORDREGISTER(CCB); /* Compare or Capture B */ - register8_t reserved_0x2C; - register8_t reserved_0x2D; - register8_t reserved_0x2E; - register8_t reserved_0x2F; - register8_t reserved_0x30; - register8_t reserved_0x31; - register8_t reserved_0x32; - register8_t reserved_0x33; - register8_t reserved_0x34; - register8_t reserved_0x35; - _WORDREGISTER(PERBUF); /* Period Buffer */ - _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ - _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ -} TC1_t; - -/* Clock Selection */ -typedef enum TC_CLKSEL_enum -{ - TC_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */ - TC_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */ - TC_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */ - TC_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */ - TC_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */ - TC_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */ - TC_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */ - TC_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */ - TC_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */ - TC_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */ - TC_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */ - TC_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */ -} TC_CLKSEL_t; - -/* Waveform Generation Mode */ -typedef enum TC_WGMODE_enum -{ - TC_WGMODE_NORMAL_gc = (0x00<<0), /* Normal Mode */ - TC_WGMODE_FRQ_gc = (0x01<<0), /* Frequency Generation Mode */ - TC_WGMODE_SINGLESLOPE_gc = (0x03<<0), /* Single Slope */ - TC_WGMODE_SS_gc = (0x03<<0), /* Single Slope */ - TC_WGMODE_DSTOP_gc = (0x05<<0), /* Dual Slope, Update on TOP */ - TC_WGMODE_DS_T_gc = (0x05<<0), /* Dual Slope, Update on TOP */ - TC_WGMODE_DSBOTH_gc = (0x06<<0), /* Dual Slope, Update on both TOP and BOTTOM */ - TC_WGMODE_DS_TB_gc = (0x06<<0), /* Dual Slope, Update on both TOP and BOTTOM */ - TC_WGMODE_DSBOTTOM_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */ - TC_WGMODE_DS_B_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */ -} TC_WGMODE_t; - -/* Byte Mode */ -typedef enum TC_BYTEM_enum -{ - TC_BYTEM_NORMAL_gc = (0x00<<0), /* 16-bit mode */ - TC_BYTEM_BYTEMODE_gc = (0x01<<0), /* Timer/Counter operating in byte mode only */ - TC_BYTEM_SPLITMODE_gc = (0x02<<0), /* Timer/Counter split into two 8-bit Counters (TC2) */ -} TC_BYTEM_t; - -/* Event Action */ -typedef enum TC_EVACT_enum -{ - TC_EVACT_OFF_gc = (0x00<<5), /* No Event Action */ - TC_EVACT_CAPT_gc = (0x01<<5), /* Input Capture */ - TC_EVACT_UPDOWN_gc = (0x02<<5), /* Externally Controlled Up/Down Count */ - TC_EVACT_QDEC_gc = (0x03<<5), /* Quadrature Decode */ - TC_EVACT_RESTART_gc = (0x04<<5), /* Restart */ - TC_EVACT_FRQ_gc = (0x05<<5), /* Frequency Capture */ - TC_EVACT_PW_gc = (0x06<<5), /* Pulse-width Capture */ -} TC_EVACT_t; - -/* Event Selection */ -typedef enum TC_EVSEL_enum -{ - TC_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ - TC_EVSEL_CH0_gc = (0x08<<0), /* Event Channel 0 */ - TC_EVSEL_CH1_gc = (0x09<<0), /* Event Channel 1 */ - TC_EVSEL_CH2_gc = (0x0A<<0), /* Event Channel 2 */ - TC_EVSEL_CH3_gc = (0x0B<<0), /* Event Channel 3 */ -} TC_EVSEL_t; - -/* Error Interrupt Level */ -typedef enum TC_ERRINTLVL_enum -{ - TC_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ - TC_ERRINTLVL_LO_gc = (0x01<<2), /* Low Level */ - TC_ERRINTLVL_MED_gc = (0x02<<2), /* Medium Level */ - TC_ERRINTLVL_HI_gc = (0x03<<2), /* High Level */ -} TC_ERRINTLVL_t; - -/* Overflow Interrupt Level */ -typedef enum TC_OVFINTLVL_enum -{ - TC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - TC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ - TC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ - TC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ -} TC_OVFINTLVL_t; - -/* Compare or Capture D Interrupt Level */ -typedef enum TC_CCDINTLVL_enum -{ - TC_CCDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ - TC_CCDINTLVL_LO_gc = (0x01<<6), /* Low Level */ - TC_CCDINTLVL_MED_gc = (0x02<<6), /* Medium Level */ - TC_CCDINTLVL_HI_gc = (0x03<<6), /* High Level */ -} TC_CCDINTLVL_t; - -/* Compare or Capture C Interrupt Level */ -typedef enum TC_CCCINTLVL_enum -{ - TC_CCCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ - TC_CCCINTLVL_LO_gc = (0x01<<4), /* Low Level */ - TC_CCCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ - TC_CCCINTLVL_HI_gc = (0x03<<4), /* High Level */ -} TC_CCCINTLVL_t; - -/* Compare or Capture B Interrupt Level */ -typedef enum TC_CCBINTLVL_enum -{ - TC_CCBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ - TC_CCBINTLVL_LO_gc = (0x01<<2), /* Low Level */ - TC_CCBINTLVL_MED_gc = (0x02<<2), /* Medium Level */ - TC_CCBINTLVL_HI_gc = (0x03<<2), /* High Level */ -} TC_CCBINTLVL_t; - -/* Compare or Capture A Interrupt Level */ -typedef enum TC_CCAINTLVL_enum -{ - TC_CCAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - TC_CCAINTLVL_LO_gc = (0x01<<0), /* Low Level */ - TC_CCAINTLVL_MED_gc = (0x02<<0), /* Medium Level */ - TC_CCAINTLVL_HI_gc = (0x03<<0), /* High Level */ -} TC_CCAINTLVL_t; - -/* Timer/Counter Command */ -typedef enum TC_CMD_enum -{ - TC_CMD_NONE_gc = (0x00<<2), /* No Command */ - TC_CMD_UPDATE_gc = (0x01<<2), /* Force Update */ - TC_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ - TC_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ -} TC_CMD_t; - - -/* --------------------------------------------------------------------------- -TC2 - 16-bit Timer/Counter type 2 --------------------------------------------------------------------------- -*/ - -/* 16-bit Timer/Counter type 2 */ -typedef struct TC2_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t CTRLC; /* Control register C */ - register8_t reserved_0x03; - register8_t CTRLE; /* Control Register E */ - register8_t reserved_0x05; - register8_t INTCTRLA; /* Interrupt Control Register A */ - register8_t INTCTRLB; /* Interrupt Control Register B */ - register8_t reserved_0x08; - register8_t CTRLF; /* Control Register F */ - register8_t reserved_0x0A; - register8_t reserved_0x0B; - register8_t INTFLAGS; /* Interrupt Flag Register */ - register8_t reserved_0x0D; - register8_t reserved_0x0E; - register8_t reserved_0x0F; - register8_t reserved_0x10; - register8_t reserved_0x11; - register8_t reserved_0x12; - register8_t reserved_0x13; - register8_t reserved_0x14; - register8_t reserved_0x15; - register8_t reserved_0x16; - register8_t reserved_0x17; - register8_t reserved_0x18; - register8_t reserved_0x19; - register8_t reserved_0x1A; - register8_t reserved_0x1B; - register8_t reserved_0x1C; - register8_t reserved_0x1D; - register8_t reserved_0x1E; - register8_t reserved_0x1F; - register8_t LCNT; /* Low Byte Count */ - register8_t HCNT; /* High Byte Count */ - register8_t reserved_0x22; - register8_t reserved_0x23; - register8_t reserved_0x24; - register8_t reserved_0x25; - register8_t LPER; /* Low Byte Period */ - register8_t HPER; /* High Byte Period */ - register8_t LCMPA; /* Low Byte Compare A */ - register8_t HCMPA; /* High Byte Compare A */ - register8_t LCMPB; /* Low Byte Compare B */ - register8_t HCMPB; /* High Byte Compare B */ - register8_t LCMPC; /* Low Byte Compare C */ - register8_t HCMPC; /* High Byte Compare C */ - register8_t LCMPD; /* Low Byte Compare D */ - register8_t HCMPD; /* High Byte Compare D */ -} TC2_t; - -/* Clock Selection */ -typedef enum TC2_CLKSEL_enum -{ - TC2_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */ - TC2_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */ - TC2_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */ - TC2_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */ - TC2_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */ - TC2_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */ - TC2_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */ - TC2_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */ - TC2_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */ - TC2_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */ - TC2_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */ - TC2_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */ -} TC2_CLKSEL_t; - -/* Byte Mode */ -typedef enum TC2_BYTEM_enum -{ - TC2_BYTEM_NORMAL_gc = (0x00<<0), /* 16-bit mode */ - TC2_BYTEM_BYTEMODE_gc = (0x01<<0), /* Timer/Counter operating in byte mode only (TC2) */ - TC2_BYTEM_SPLITMODE_gc = (0x02<<0), /* Timer/Counter split into two 8-bit Counters */ -} TC2_BYTEM_t; - -/* High Byte Underflow Interrupt Level */ -typedef enum TC2_HUNFINTLVL_enum -{ - TC2_HUNFINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ - TC2_HUNFINTLVL_LO_gc = (0x01<<2), /* Low Level */ - TC2_HUNFINTLVL_MED_gc = (0x02<<2), /* Medium Level */ - TC2_HUNFINTLVL_HI_gc = (0x03<<2), /* High Level */ -} TC2_HUNFINTLVL_t; - -/* Low Byte Underflow Interrupt Level */ -typedef enum TC2_LUNFINTLVL_enum -{ - TC2_LUNFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - TC2_LUNFINTLVL_LO_gc = (0x01<<0), /* Low Level */ - TC2_LUNFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ - TC2_LUNFINTLVL_HI_gc = (0x03<<0), /* High Level */ -} TC2_LUNFINTLVL_t; - -/* Low Byte Compare D Interrupt Level */ -typedef enum TC2_LCMPDINTLVL_enum -{ - TC2_LCMPDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ - TC2_LCMPDINTLVL_LO_gc = (0x01<<6), /* Low Level */ - TC2_LCMPDINTLVL_MED_gc = (0x02<<6), /* Medium Level */ - TC2_LCMPDINTLVL_HI_gc = (0x03<<6), /* High Level */ -} TC2_LCMPDINTLVL_t; - -/* Low Byte Compare C Interrupt Level */ -typedef enum TC2_LCMPCINTLVL_enum -{ - TC2_LCMPCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ - TC2_LCMPCINTLVL_LO_gc = (0x01<<4), /* Low Level */ - TC2_LCMPCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ - TC2_LCMPCINTLVL_HI_gc = (0x03<<4), /* High Level */ -} TC2_LCMPCINTLVL_t; - -/* Low Byte Compare B Interrupt Level */ -typedef enum TC2_LCMPBINTLVL_enum -{ - TC2_LCMPBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ - TC2_LCMPBINTLVL_LO_gc = (0x01<<2), /* Low Level */ - TC2_LCMPBINTLVL_MED_gc = (0x02<<2), /* Medium Level */ - TC2_LCMPBINTLVL_HI_gc = (0x03<<2), /* High Level */ -} TC2_LCMPBINTLVL_t; - -/* Low Byte Compare A Interrupt Level */ -typedef enum TC2_LCMPAINTLVL_enum -{ - TC2_LCMPAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - TC2_LCMPAINTLVL_LO_gc = (0x01<<0), /* Low Level */ - TC2_LCMPAINTLVL_MED_gc = (0x02<<0), /* Medium Level */ - TC2_LCMPAINTLVL_HI_gc = (0x03<<0), /* High Level */ -} TC2_LCMPAINTLVL_t; - -/* Timer/Counter Command */ -typedef enum TC2_CMD_enum -{ - TC2_CMD_NONE_gc = (0x00<<2), /* No Command */ - TC2_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ - TC2_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ -} TC2_CMD_t; - -/* Timer/Counter Command */ -typedef enum TC2_CMDEN_enum -{ - TC2_CMDEN_LOW_gc = (0x01<<0), /* Low Byte Timer/Counter */ - TC2_CMDEN_HIGH_gc = (0x02<<0), /* High Byte Timer/Counter */ - TC2_CMDEN_BOTH_gc = (0x03<<0), /* Both Low Byte and High Byte Timer/Counters */ -} TC2_CMDEN_t; - - -/* --------------------------------------------------------------------------- -AWEX - Timer/Counter Advanced Waveform Extension --------------------------------------------------------------------------- -*/ - -/* Advanced Waveform Extension */ -typedef struct AWEX_struct -{ - register8_t CTRL; /* Control Register */ - register8_t reserved_0x01; - register8_t FDEMASK; /* Fault Detection Event Mask */ - register8_t FDCTRL; /* Fault Detection Control Register */ - register8_t STATUS; /* Status Register */ - register8_t STATUSSET; /* Status Set Register */ - register8_t DTBOTH; /* Dead Time Both Sides */ - register8_t DTBOTHBUF; /* Dead Time Both Sides Buffer */ - register8_t DTLS; /* Dead Time Low Side */ - register8_t DTHS; /* Dead Time High Side */ - register8_t DTLSBUF; /* Dead Time Low Side Buffer */ - register8_t DTHSBUF; /* Dead Time High Side Buffer */ - register8_t OUTOVEN; /* Output Override Enable */ -} AWEX_t; - -/* Fault Detect Action */ -typedef enum AWEX_FDACT_enum -{ - AWEX_FDACT_NONE_gc = (0x00<<0), /* No Fault Protection */ - AWEX_FDACT_CLEAROE_gc = (0x01<<0), /* Clear Output Enable Bits */ - AWEX_FDACT_CLEARDIR_gc = (0x03<<0), /* Clear I/O Port Direction Bits */ -} AWEX_FDACT_t; - - -/* --------------------------------------------------------------------------- -HIRES - Timer/Counter High-Resolution Extension --------------------------------------------------------------------------- -*/ - -/* High-Resolution Extension */ -typedef struct HIRES_struct -{ - register8_t CTRLA; /* Control Register */ -} HIRES_t; - -/* High Resolution Enable */ -typedef enum HIRES_HREN_enum -{ - HIRES_HREN_NONE_gc = (0x00<<0), /* No Fault Protection */ - HIRES_HREN_TC0_gc = (0x01<<0), /* Enable High Resolution on Timer/Counter 0 */ - HIRES_HREN_TC1_gc = (0x02<<0), /* Enable High Resolution on Timer/Counter 1 */ - HIRES_HREN_BOTH_gc = (0x03<<0), /* Enable High Resolution both Timer/Counters */ -} HIRES_HREN_t; - - -/* --------------------------------------------------------------------------- -USART - Universal Asynchronous Receiver-Transmitter --------------------------------------------------------------------------- -*/ - -/* Universal Synchronous/Asynchronous Receiver/Transmitter */ -typedef struct USART_struct -{ - register8_t DATA; /* Data Register */ - register8_t STATUS; /* Status Register */ - register8_t reserved_0x02; - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t CTRLC; /* Control Register C */ - register8_t BAUDCTRLA; /* Baud Rate Control Register A */ - register8_t BAUDCTRLB; /* Baud Rate Control Register B */ -} USART_t; - -/* Receive Complete Interrupt level */ -typedef enum USART_RXCINTLVL_enum -{ - USART_RXCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ - USART_RXCINTLVL_LO_gc = (0x01<<4), /* Low Level */ - USART_RXCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ - USART_RXCINTLVL_HI_gc = (0x03<<4), /* High Level */ -} USART_RXCINTLVL_t; - -/* Transmit Complete Interrupt level */ -typedef enum USART_TXCINTLVL_enum -{ - USART_TXCINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ - USART_TXCINTLVL_LO_gc = (0x01<<2), /* Low Level */ - USART_TXCINTLVL_MED_gc = (0x02<<2), /* Medium Level */ - USART_TXCINTLVL_HI_gc = (0x03<<2), /* High Level */ -} USART_TXCINTLVL_t; - -/* Data Register Empty Interrupt level */ -typedef enum USART_DREINTLVL_enum -{ - USART_DREINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - USART_DREINTLVL_LO_gc = (0x01<<0), /* Low Level */ - USART_DREINTLVL_MED_gc = (0x02<<0), /* Medium Level */ - USART_DREINTLVL_HI_gc = (0x03<<0), /* High Level */ -} USART_DREINTLVL_t; - -/* Character Size */ -typedef enum USART_CHSIZE_enum -{ - USART_CHSIZE_5BIT_gc = (0x00<<0), /* Character size: 5 bit */ - USART_CHSIZE_6BIT_gc = (0x01<<0), /* Character size: 6 bit */ - USART_CHSIZE_7BIT_gc = (0x02<<0), /* Character size: 7 bit */ - USART_CHSIZE_8BIT_gc = (0x03<<0), /* Character size: 8 bit */ - USART_CHSIZE_9BIT_gc = (0x07<<0), /* Character size: 9 bit */ -} USART_CHSIZE_t; - -/* Communication Mode */ -typedef enum USART_CMODE_enum -{ - USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6), /* Asynchronous Mode */ - USART_CMODE_SYNCHRONOUS_gc = (0x01<<6), /* Synchronous Mode */ - USART_CMODE_IRDA_gc = (0x02<<6), /* IrDA Mode */ - USART_CMODE_MSPI_gc = (0x03<<6), /* Master SPI Mode */ -} USART_CMODE_t; - -/* Parity Mode */ -typedef enum USART_PMODE_enum -{ - USART_PMODE_DISABLED_gc = (0x00<<4), /* No Parity */ - USART_PMODE_EVEN_gc = (0x02<<4), /* Even Parity */ - USART_PMODE_ODD_gc = (0x03<<4), /* Odd Parity */ -} USART_PMODE_t; - - -/* --------------------------------------------------------------------------- -SPI - Serial Peripheral Interface --------------------------------------------------------------------------- -*/ - -/* Serial Peripheral Interface */ -typedef struct SPI_struct -{ - register8_t CTRL; /* Control Register */ - register8_t INTCTRL; /* Interrupt Control Register */ - register8_t STATUS; /* Status Register */ - register8_t DATA; /* Data Register */ -} SPI_t; - -/* SPI Mode */ -typedef enum SPI_MODE_enum -{ - SPI_MODE_0_gc = (0x00<<2), /* SPI Mode 0 */ - SPI_MODE_1_gc = (0x01<<2), /* SPI Mode 1 */ - SPI_MODE_2_gc = (0x02<<2), /* SPI Mode 2 */ - SPI_MODE_3_gc = (0x03<<2), /* SPI Mode 3 */ -} SPI_MODE_t; - -/* Prescaler setting */ -typedef enum SPI_PRESCALER_enum -{ - SPI_PRESCALER_DIV4_gc = (0x00<<0), /* System Clock / 4 */ - SPI_PRESCALER_DIV16_gc = (0x01<<0), /* System Clock / 16 */ - SPI_PRESCALER_DIV64_gc = (0x02<<0), /* System Clock / 64 */ - SPI_PRESCALER_DIV128_gc = (0x03<<0), /* System Clock / 128 */ -} SPI_PRESCALER_t; - -/* Interrupt level */ -typedef enum SPI_INTLVL_enum -{ - SPI_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - SPI_INTLVL_LO_gc = (0x01<<0), /* Low Level */ - SPI_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ - SPI_INTLVL_HI_gc = (0x03<<0), /* High Level */ -} SPI_INTLVL_t; - - -/* --------------------------------------------------------------------------- -IRCOM - IR Communication Module --------------------------------------------------------------------------- -*/ - -/* IR Communication Module */ -typedef struct IRCOM_struct -{ - register8_t CTRL; /* Control Register */ - register8_t TXPLCTRL; /* IrDA Transmitter Pulse Length Control Register */ - register8_t RXPLCTRL; /* IrDA Receiver Pulse Length Control Register */ -} IRCOM_t; - -/* Event channel selection */ -typedef enum IRDA_EVSEL_enum -{ - IRDA_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ - IRDA_EVSEL_0_gc = (0x08<<0), /* Event Channel 0 */ - IRDA_EVSEL_1_gc = (0x09<<0), /* Event Channel 1 */ - IRDA_EVSEL_2_gc = (0x0A<<0), /* Event Channel 2 */ - IRDA_EVSEL_3_gc = (0x0B<<0), /* Event Channel 3 */ -} IRDA_EVSEL_t; - - -/* --------------------------------------------------------------------------- -FUSE - Fuses and Lockbits --------------------------------------------------------------------------- -*/ - -/* Fuses */ -typedef struct NVM_FUSES_struct -{ - register8_t reserved_0x00; - register8_t FUSEBYTE1; /* Watchdog Configuration */ - register8_t FUSEBYTE2; /* Reset Configuration */ - register8_t reserved_0x03; - register8_t FUSEBYTE4; /* Start-up Configuration */ - register8_t FUSEBYTE5; /* EESAVE and BOD Level */ -} NVM_FUSES_t; - -/* Boot Loader Section Reset Vector */ -typedef enum BOOTRST_enum -{ - BOOTRST_BOOTLDR_gc = (0x00<<6), /* Boot Loader Reset */ - BOOTRST_APPLICATION_gc = (0x01<<6), /* Application Reset */ -} BOOTRST_t; - -/* Timer Oscillator pin location */ -typedef enum TOSCSEL_enum -{ - TOSCSEL_ALTERNATE_gc = (0x00<<5), /* TOSC1 / TOSC2 on separate pins */ - TOSCSEL_XTAL_gc = (0x01<<5), /* TOSC1 / TOSC2 shared with XTAL1 / XTAL2 */ -} TOSCSEL_t; - -/* BOD operation */ -typedef enum BOD_enum -{ - BOD_SAMPLED_gc = (0x01<<0), /* BOD enabled in sampled mode */ - BOD_CONTINUOUS_gc = (0x02<<0), /* BOD enabled continuously */ - BOD_DISABLED_gc = (0x03<<0), /* BOD Disabled */ -} BOD_t; - -/* BOD operation */ -typedef enum BODACT_enum -{ - BODACT_SAMPLED_gc = (0x01<<4), /* BOD enabled in sampled mode */ - BODACT_CONTINUOUS_gc = (0x02<<4), /* BOD enabled continuously */ - BODACT_DISABLED_gc = (0x03<<4), /* BOD Disabled */ -} BODACT_t; - -/* Watchdog (Window) Timeout Period */ -typedef enum WD_enum -{ - WD_8CLK_gc = (0x00<<4), /* 8 cycles (8ms @ 3.3V) */ - WD_16CLK_gc = (0x01<<4), /* 16 cycles (16ms @ 3.3V) */ - WD_32CLK_gc = (0x02<<4), /* 32 cycles (32ms @ 3.3V) */ - WD_64CLK_gc = (0x03<<4), /* 64 cycles (64ms @ 3.3V) */ - WD_128CLK_gc = (0x04<<4), /* 128 cycles (0.125s @ 3.3V) */ - WD_256CLK_gc = (0x05<<4), /* 256 cycles (0.25s @ 3.3V) */ - WD_512CLK_gc = (0x06<<4), /* 512 cycles (0.5s @ 3.3V) */ - WD_1KCLK_gc = (0x07<<4), /* 1K cycles (1s @ 3.3V) */ - WD_2KCLK_gc = (0x08<<4), /* 2K cycles (2s @ 3.3V) */ - WD_4KCLK_gc = (0x09<<4), /* 4K cycles (4s @ 3.3V) */ - WD_8KCLK_gc = (0x0A<<4), /* 8K cycles (8s @ 3.3V) */ -} WD_t; - -/* Watchdog (Window) Timeout Period */ -typedef enum WDP_enum -{ - WDP_8CLK_gc = (0x00<<0), /* 8 cycles (8ms @ 3.3V) */ - WDP_16CLK_gc = (0x01<<0), /* 16 cycles (16ms @ 3.3V) */ - WDP_32CLK_gc = (0x02<<0), /* 32 cycles (32ms @ 3.3V) */ - WDP_64CLK_gc = (0x03<<0), /* 64 cycles (64ms @ 3.3V) */ - WDP_128CLK_gc = (0x04<<0), /* 128 cycles (0.125s @ 3.3V) */ - WDP_256CLK_gc = (0x05<<0), /* 256 cycles (0.25s @ 3.3V) */ - WDP_512CLK_gc = (0x06<<0), /* 512 cycles (0.5s @ 3.3V) */ - WDP_1KCLK_gc = (0x07<<0), /* 1K cycles (1s @ 3.3V) */ - WDP_2KCLK_gc = (0x08<<0), /* 2K cycles (2s @ 3.3V) */ - WDP_4KCLK_gc = (0x09<<0), /* 4K cycles (4s @ 3.3V) */ - WDP_8KCLK_gc = (0x0A<<0), /* 8K cycles (8s @ 3.3V) */ -} WDP_t; - -/* Start-up Time */ -typedef enum SUT_enum -{ - SUT_0MS_gc = (0x03<<2), /* 0 ms */ - SUT_4MS_gc = (0x01<<2), /* 4 ms */ - SUT_64MS_gc = (0x00<<2), /* 64 ms */ -} SUT_t; - -/* Brownout Detection Voltage Level */ -typedef enum BODLVL_enum -{ - BODLVL_1V6_gc = (0x07<<0), /* 1.6 V */ - BODLVL_1V8_gc = (0x06<<0), /* 1.8 V */ - BODLVL_2V0_gc = (0x05<<0), /* 2.0 V */ - BODLVL_2V2_gc = (0x04<<0), /* 2.2 V */ - BODLVL_2V4_gc = (0x03<<0), /* 2.4 V */ - BODLVL_2V6_gc = (0x02<<0), /* 2.6 V */ - BODLVL_2V8_gc = (0x01<<0), /* 2.8 V */ - BODLVL_3V0_gc = (0x00<<0), /* 3.0 V */ -} BODLVL_t; - - -/* --------------------------------------------------------------------------- -LOCKBIT - Fuses and Lockbits --------------------------------------------------------------------------- -*/ - -/* Lock Bits */ -typedef struct NVM_LOCKBITS_struct -{ - register8_t LOCK_BITS; /* Lock Bits (Changed from LOCKBITS to avoid avr-libc collision) */ -} NVM_LOCKBITS_t; - -/* Boot lock bits - boot setcion */ -typedef enum FUSE_BLBB_enum -{ - FUSE_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ - FUSE_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ - FUSE_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ - FUSE_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ -} FUSE_BLBB_t; - -/* Boot lock bits - application section */ -typedef enum FUSE_BLBA_enum -{ - FUSE_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ - FUSE_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ - FUSE_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ - FUSE_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ -} FUSE_BLBA_t; - -/* Boot lock bits - application table section */ -typedef enum FUSE_BLBAT_enum -{ - FUSE_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ - FUSE_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ - FUSE_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ - FUSE_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ -} FUSE_BLBAT_t; - -/* Lock bits */ -typedef enum FUSE_LB_enum -{ - FUSE_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ - FUSE_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ - FUSE_LB_NOLOCK_gc = (0x03<<0), /* No locks */ -} FUSE_LB_t; - - -/* --------------------------------------------------------------------------- -SIGROW - Signature Row --------------------------------------------------------------------------- -*/ - -/* Production Signatures */ -typedef struct NVM_PROD_SIGNATURES_struct -{ - register8_t RCOSC2M; /* RCOSC 2 MHz Calibration Value B */ - register8_t RCOSC2MA; /* RCOSC 2 MHz Calibration Value A */ - register8_t RCOSC32K; /* RCOSC 32.768 kHz Calibration Value */ - register8_t RCOSC32M; /* RCOSC 32 MHz Calibration Value B */ - register8_t RCOSC32MA; /* RCOSC 32 MHz Calibration Value A */ - register8_t reserved_0x05; - register8_t reserved_0x06; - register8_t reserved_0x07; - register8_t LOTNUM0; /* Lot Number Byte 0, ASCII */ - register8_t LOTNUM1; /* Lot Number Byte 1, ASCII */ - register8_t LOTNUM2; /* Lot Number Byte 2, ASCII */ - register8_t LOTNUM3; /* Lot Number Byte 3, ASCII */ - register8_t LOTNUM4; /* Lot Number Byte 4, ASCII */ - register8_t LOTNUM5; /* Lot Number Byte 5, ASCII */ - register8_t reserved_0x0E; - register8_t reserved_0x0F; - register8_t WAFNUM; /* Wafer Number */ - register8_t reserved_0x11; - register8_t COORDX0; /* Wafer Coordinate X Byte 0 */ - register8_t COORDX1; /* Wafer Coordinate X Byte 1 */ - register8_t COORDY0; /* Wafer Coordinate Y Byte 0 */ - register8_t COORDY1; /* Wafer Coordinate Y Byte 1 */ - register8_t reserved_0x16; - register8_t reserved_0x17; - register8_t reserved_0x18; - register8_t reserved_0x19; - register8_t USBCAL0; /* USB Calibration Byte 0 */ - register8_t USBCAL1; /* USB Calibration Byte 1 */ - register8_t USBRCOSC; /* USB RCOSC Calibration Value B */ - register8_t USBRCOSCA; /* USB RCOSC Calibration Value A */ - register8_t reserved_0x1E; - register8_t reserved_0x1F; - register8_t ADCACAL0; /* ADCA Calibration Byte 0 */ - register8_t ADCACAL1; /* ADCA Calibration Byte 1 */ - register8_t reserved_0x22; - register8_t reserved_0x23; - register8_t reserved_0x24; - register8_t reserved_0x25; - register8_t reserved_0x26; - register8_t reserved_0x27; - register8_t reserved_0x28; - register8_t reserved_0x29; - register8_t reserved_0x2A; - register8_t reserved_0x2B; - register8_t reserved_0x2C; - register8_t reserved_0x2D; - register8_t TEMPSENSE0; /* Temperature Sensor Calibration Byte 0 */ - register8_t TEMPSENSE1; /* Temperature Sensor Calibration Byte 1 */ - register8_t reserved_0x30; - register8_t reserved_0x31; - register8_t reserved_0x32; - register8_t reserved_0x33; - register8_t reserved_0x34; - register8_t reserved_0x35; - register8_t reserved_0x36; - register8_t reserved_0x37; - register8_t reserved_0x38; - register8_t reserved_0x39; - register8_t reserved_0x3A; - register8_t reserved_0x3B; - register8_t reserved_0x3C; - register8_t reserved_0x3D; - register8_t reserved_0x3E; - register8_t reserved_0x3F; -} NVM_PROD_SIGNATURES_t; - -/* -========================================================================== -IO Module Instances. Mapped to memory. -========================================================================== -*/ - -#define VPORT0 (*(VPORT_t *) 0x0010) /* Virtual Port */ -#define VPORT1 (*(VPORT_t *) 0x0014) /* Virtual Port */ -#define VPORT2 (*(VPORT_t *) 0x0018) /* Virtual Port */ -#define VPORT3 (*(VPORT_t *) 0x001C) /* Virtual Port */ -#define OCD (*(OCD_t *) 0x002E) /* On-Chip Debug System */ -#define CLK (*(CLK_t *) 0x0040) /* Clock System */ -#define SLEEP (*(SLEEP_t *) 0x0048) /* Sleep Controller */ -#define OSC (*(OSC_t *) 0x0050) /* Oscillator */ -#define DFLLRC32M (*(DFLL_t *) 0x0060) /* DFLL */ -#define DFLLRC2M (*(DFLL_t *) 0x0068) /* DFLL */ -#define PR (*(PR_t *) 0x0070) /* Power Reduction */ -#define RST (*(RST_t *) 0x0078) /* Reset */ -#define WDT (*(WDT_t *) 0x0080) /* Watch-Dog Timer */ -#define MCU (*(MCU_t *) 0x0090) /* MCU Control */ -#define PMIC (*(PMIC_t *) 0x00A0) /* Programmable Multi-level Interrupt Controller */ -#define PORTCFG (*(PORTCFG_t *) 0x00B0) /* I/O port Configuration */ -#define CRC (*(CRC_t *) 0x00D0) /* Cyclic Redundancy Checker */ -#define EVSYS (*(EVSYS_t *) 0x0180) /* Event System */ -#define NVM (*(NVM_t *) 0x01C0) /* Non-volatile Memory Controller */ -#define ADCA (*(ADC_t *) 0x0200) /* Analog-to-Digital Converter */ -#define ACA (*(AC_t *) 0x0380) /* Analog Comparator */ -#define RTC (*(RTC_t *) 0x0400) /* Real-Time Counter */ -#define TWIC (*(TWI_t *) 0x0480) /* Two-Wire Interface */ -#define TWIE (*(TWI_t *) 0x04A0) /* Two-Wire Interface */ -#define USB (*(USB_t *) 0x04C0) /* Universal Serial Bus */ -#define PORTA (*(PORT_t *) 0x0600) /* I/O Ports */ -#define PORTB (*(PORT_t *) 0x0620) /* I/O Ports */ -#define PORTC (*(PORT_t *) 0x0640) /* I/O Ports */ -#define PORTD (*(PORT_t *) 0x0660) /* I/O Ports */ -#define PORTE (*(PORT_t *) 0x0680) /* I/O Ports */ -#define PORTF (*(PORT_t *) 0x06A0) /* I/O Ports */ -#define PORTR (*(PORT_t *) 0x07E0) /* I/O Ports */ -#define TCC0 (*(TC0_t *) 0x0800) /* 16-bit Timer/Counter 0 */ -#define TCC2 (*(TC2_t *) 0x0800) /* 16-bit Timer/Counter type 2 */ -#define TCC1 (*(TC1_t *) 0x0840) /* 16-bit Timer/Counter 1 */ -#define AWEXC (*(AWEX_t *) 0x0880) /* Advanced Waveform Extension */ -#define HIRESC (*(HIRES_t *) 0x0890) /* High-Resolution Extension */ -#define USARTC0 (*(USART_t *) 0x08A0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ -#define SPIC (*(SPI_t *) 0x08C0) /* Serial Peripheral Interface */ -#define IRCOM (*(IRCOM_t *) 0x08F8) /* IR Communication Module */ -#define TCD0 (*(TC0_t *) 0x0900) /* 16-bit Timer/Counter 0 */ -#define TCD2 (*(TC2_t *) 0x0900) /* 16-bit Timer/Counter type 2 */ -#define USARTD0 (*(USART_t *) 0x09A0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ -#define SPID (*(SPI_t *) 0x09C0) /* Serial Peripheral Interface */ -#define TCE0 (*(TC0_t *) 0x0A00) /* 16-bit Timer/Counter 0 */ -#define TCE2 (*(TC2_t *) 0x0A00) /* 16-bit Timer/Counter type 2 */ -#define USARTE0 (*(USART_t *) 0x0AA0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ -#define TCF0 (*(TC0_t *) 0x0B00) /* 16-bit Timer/Counter 0 */ -#define TCF2 (*(TC2_t *) 0x0B00) /* 16-bit Timer/Counter type 2 */ - - -#endif /* !defined (__ASSEMBLER__) */ - - -/* ========== Flattened fully qualified IO register names ========== */ - -/* GPIO - General Purpose IO Registers */ -#define GPIO_GPIOR0 _SFR_MEM8(0x0000) -#define GPIO_GPIOR1 _SFR_MEM8(0x0001) -#define GPIO_GPIOR2 _SFR_MEM8(0x0002) -#define GPIO_GPIOR3 _SFR_MEM8(0x0003) - -/* Deprecated */ -#define GPIO_GPIO0 _SFR_MEM8(0x0000) -#define GPIO_GPIO1 _SFR_MEM8(0x0001) -#define GPIO_GPIO2 _SFR_MEM8(0x0002) -#define GPIO_GPIO3 _SFR_MEM8(0x0003) - -/* NVM_FUSES - Fuses */ -#define FUSE_FUSEBYTE1 _SFR_MEM8(0x0001) -#define FUSE_FUSEBYTE2 _SFR_MEM8(0x0002) -#define FUSE_FUSEBYTE4 _SFR_MEM8(0x0004) -#define FUSE_FUSEBYTE5 _SFR_MEM8(0x0005) - -/* NVM_LOCKBITS - Lock Bits */ -#define LOCKBIT_LOCKBITS _SFR_MEM8(0x0000) - -/* NVM_PROD_SIGNATURES - Production Signatures */ -#define PRODSIGNATURES_RCOSC2M _SFR_MEM8(0x0000) -#define PRODSIGNATURES_RCOSC2MA _SFR_MEM8(0x0001) -#define PRODSIGNATURES_RCOSC32K _SFR_MEM8(0x0002) -#define PRODSIGNATURES_RCOSC32M _SFR_MEM8(0x0003) -#define PRODSIGNATURES_RCOSC32MA _SFR_MEM8(0x0004) -#define PRODSIGNATURES_LOTNUM0 _SFR_MEM8(0x0008) -#define PRODSIGNATURES_LOTNUM1 _SFR_MEM8(0x0009) -#define PRODSIGNATURES_LOTNUM2 _SFR_MEM8(0x000A) -#define PRODSIGNATURES_LOTNUM3 _SFR_MEM8(0x000B) -#define PRODSIGNATURES_LOTNUM4 _SFR_MEM8(0x000C) -#define PRODSIGNATURES_LOTNUM5 _SFR_MEM8(0x000D) -#define PRODSIGNATURES_WAFNUM _SFR_MEM8(0x0010) -#define PRODSIGNATURES_COORDX0 _SFR_MEM8(0x0012) -#define PRODSIGNATURES_COORDX1 _SFR_MEM8(0x0013) -#define PRODSIGNATURES_COORDY0 _SFR_MEM8(0x0014) -#define PRODSIGNATURES_COORDY1 _SFR_MEM8(0x0015) -#define PRODSIGNATURES_USBCAL0 _SFR_MEM8(0x001A) -#define PRODSIGNATURES_USBCAL1 _SFR_MEM8(0x001B) -#define PRODSIGNATURES_USBRCOSC _SFR_MEM8(0x001C) -#define PRODSIGNATURES_USBRCOSCA _SFR_MEM8(0x001D) -#define PRODSIGNATURES_ADCACAL0 _SFR_MEM8(0x0020) -#define PRODSIGNATURES_ADCACAL1 _SFR_MEM8(0x0021) -#define PRODSIGNATURES_TEMPSENSE0 _SFR_MEM8(0x002E) -#define PRODSIGNATURES_TEMPSENSE1 _SFR_MEM8(0x002F) - -/* VPORT - Virtual Port */ -#define VPORT0_DIR _SFR_MEM8(0x0010) -#define VPORT0_OUT _SFR_MEM8(0x0011) -#define VPORT0_IN _SFR_MEM8(0x0012) -#define VPORT0_INTFLAGS _SFR_MEM8(0x0013) - -/* VPORT - Virtual Port */ -#define VPORT1_DIR _SFR_MEM8(0x0014) -#define VPORT1_OUT _SFR_MEM8(0x0015) -#define VPORT1_IN _SFR_MEM8(0x0016) -#define VPORT1_INTFLAGS _SFR_MEM8(0x0017) - -/* VPORT - Virtual Port */ -#define VPORT2_DIR _SFR_MEM8(0x0018) -#define VPORT2_OUT _SFR_MEM8(0x0019) -#define VPORT2_IN _SFR_MEM8(0x001A) -#define VPORT2_INTFLAGS _SFR_MEM8(0x001B) - -/* VPORT - Virtual Port */ -#define VPORT3_DIR _SFR_MEM8(0x001C) -#define VPORT3_OUT _SFR_MEM8(0x001D) -#define VPORT3_IN _SFR_MEM8(0x001E) -#define VPORT3_INTFLAGS _SFR_MEM8(0x001F) - -/* OCD - On-Chip Debug System */ -#define OCD_OCDR0 _SFR_MEM8(0x002E) -#define OCD_OCDR1 _SFR_MEM8(0x002F) - -/* CPU - CPU registers */ -#define CPU_CCP _SFR_MEM8(0x0034) -#define CPU_RAMPD _SFR_MEM8(0x0038) -#define CPU_RAMPX _SFR_MEM8(0x0039) -#define CPU_RAMPY _SFR_MEM8(0x003A) -#define CPU_RAMPZ _SFR_MEM8(0x003B) -#define CPU_EIND _SFR_MEM8(0x003C) -#define CPU_SPL _SFR_MEM8(0x003D) -#define CPU_SPH _SFR_MEM8(0x003E) -#define CPU_SREG _SFR_MEM8(0x003F) - -/* CLK - Clock System */ -#define CLK_CTRL _SFR_MEM8(0x0040) -#define CLK_PSCTRL _SFR_MEM8(0x0041) -#define CLK_LOCK _SFR_MEM8(0x0042) -#define CLK_RTCCTRL _SFR_MEM8(0x0043) -#define CLK_USBCTRL _SFR_MEM8(0x0044) - -/* SLEEP - Sleep Controller */ -#define SLEEP_CTRL _SFR_MEM8(0x0048) - -/* OSC - Oscillator */ -#define OSC_CTRL _SFR_MEM8(0x0050) -#define OSC_STATUS _SFR_MEM8(0x0051) -#define OSC_XOSCCTRL _SFR_MEM8(0x0052) -#define OSC_XOSCFAIL _SFR_MEM8(0x0053) -#define OSC_RC32KCAL _SFR_MEM8(0x0054) -#define OSC_PLLCTRL _SFR_MEM8(0x0055) -#define OSC_DFLLCTRL _SFR_MEM8(0x0056) - -/* DFLL - DFLL */ -#define DFLLRC32M_CTRL _SFR_MEM8(0x0060) -#define DFLLRC32M_CALA _SFR_MEM8(0x0062) -#define DFLLRC32M_CALB _SFR_MEM8(0x0063) -#define DFLLRC32M_COMP0 _SFR_MEM8(0x0064) -#define DFLLRC32M_COMP1 _SFR_MEM8(0x0065) -#define DFLLRC32M_COMP2 _SFR_MEM8(0x0066) - -/* DFLL - DFLL */ -#define DFLLRC2M_CTRL _SFR_MEM8(0x0068) -#define DFLLRC2M_CALA _SFR_MEM8(0x006A) -#define DFLLRC2M_CALB _SFR_MEM8(0x006B) -#define DFLLRC2M_COMP0 _SFR_MEM8(0x006C) -#define DFLLRC2M_COMP1 _SFR_MEM8(0x006D) -#define DFLLRC2M_COMP2 _SFR_MEM8(0x006E) - -/* PR - Power Reduction */ -#define PR_PRGEN _SFR_MEM8(0x0070) -#define PR_PRPA _SFR_MEM8(0x0071) -#define PR_PRPC _SFR_MEM8(0x0073) -#define PR_PRPD _SFR_MEM8(0x0074) -#define PR_PRPE _SFR_MEM8(0x0075) -#define PR_PRPF _SFR_MEM8(0x0076) - -/* RST - Reset */ -#define RST_STATUS _SFR_MEM8(0x0078) -#define RST_CTRL _SFR_MEM8(0x0079) - -/* WDT - Watch-Dog Timer */ -#define WDT_CTRL _SFR_MEM8(0x0080) -#define WDT_WINCTRL _SFR_MEM8(0x0081) -#define WDT_STATUS _SFR_MEM8(0x0082) - -/* MCU - MCU Control */ -#define MCU_DEVID0 _SFR_MEM8(0x0090) -#define MCU_DEVID1 _SFR_MEM8(0x0091) -#define MCU_DEVID2 _SFR_MEM8(0x0092) -#define MCU_REVID _SFR_MEM8(0x0093) -#define MCU_ANAINIT _SFR_MEM8(0x0097) -#define MCU_EVSYSLOCK _SFR_MEM8(0x0098) -#define MCU_AWEXLOCK _SFR_MEM8(0x0099) - -/* PMIC - Programmable Multi-level Interrupt Controller */ -#define PMIC_STATUS _SFR_MEM8(0x00A0) -#define PMIC_INTPRI _SFR_MEM8(0x00A1) -#define PMIC_CTRL _SFR_MEM8(0x00A2) - -/* PORTCFG - I/O port Configuration */ -#define PORTCFG_MPCMASK _SFR_MEM8(0x00B0) -#define PORTCFG_VPCTRLA _SFR_MEM8(0x00B2) -#define PORTCFG_VPCTRLB _SFR_MEM8(0x00B3) -#define PORTCFG_CLKEVOUT _SFR_MEM8(0x00B4) -#define PORTCFG_EVOUTSEL _SFR_MEM8(0x00B6) - -/* CRC - Cyclic Redundancy Checker */ -#define CRC_CTRL _SFR_MEM8(0x00D0) -#define CRC_STATUS _SFR_MEM8(0x00D1) -#define CRC_DATAIN _SFR_MEM8(0x00D3) -#define CRC_CHECKSUM0 _SFR_MEM8(0x00D4) -#define CRC_CHECKSUM1 _SFR_MEM8(0x00D5) -#define CRC_CHECKSUM2 _SFR_MEM8(0x00D6) -#define CRC_CHECKSUM3 _SFR_MEM8(0x00D7) - -/* EVSYS - Event System */ -#define EVSYS_CH0MUX _SFR_MEM8(0x0180) -#define EVSYS_CH1MUX _SFR_MEM8(0x0181) -#define EVSYS_CH2MUX _SFR_MEM8(0x0182) -#define EVSYS_CH3MUX _SFR_MEM8(0x0183) -#define EVSYS_CH0CTRL _SFR_MEM8(0x0188) -#define EVSYS_CH1CTRL _SFR_MEM8(0x0189) -#define EVSYS_CH2CTRL _SFR_MEM8(0x018A) -#define EVSYS_CH3CTRL _SFR_MEM8(0x018B) -#define EVSYS_STROBE _SFR_MEM8(0x0190) -#define EVSYS_DATA _SFR_MEM8(0x0191) - -/* NVM - Non-volatile Memory Controller */ -#define NVM_ADDR0 _SFR_MEM8(0x01C0) -#define NVM_ADDR1 _SFR_MEM8(0x01C1) -#define NVM_ADDR2 _SFR_MEM8(0x01C2) -#define NVM_DATA0 _SFR_MEM8(0x01C4) -#define NVM_DATA1 _SFR_MEM8(0x01C5) -#define NVM_DATA2 _SFR_MEM8(0x01C6) -#define NVM_CMD _SFR_MEM8(0x01CA) -#define NVM_CTRLA _SFR_MEM8(0x01CB) -#define NVM_CTRLB _SFR_MEM8(0x01CC) -#define NVM_INTCTRL _SFR_MEM8(0x01CD) -#define NVM_STATUS _SFR_MEM8(0x01CF) -#define NVM_LOCKBITS _SFR_MEM8(0x01D0) - -/* ADC - Analog-to-Digital Converter */ -#define ADCA_CTRLA _SFR_MEM8(0x0200) -#define ADCA_CTRLB _SFR_MEM8(0x0201) -#define ADCA_REFCTRL _SFR_MEM8(0x0202) -#define ADCA_EVCTRL _SFR_MEM8(0x0203) -#define ADCA_PRESCALER _SFR_MEM8(0x0204) -#define ADCA_INTFLAGS _SFR_MEM8(0x0206) -#define ADCA_TEMP _SFR_MEM8(0x0207) -#define ADCA_CAL _SFR_MEM16(0x020C) -#define ADCA_CH0RES _SFR_MEM16(0x0210) -#define ADCA_CMP _SFR_MEM16(0x0218) -#define ADCA_CH0_CTRL _SFR_MEM8(0x0220) -#define ADCA_CH0_MUXCTRL _SFR_MEM8(0x0221) -#define ADCA_CH0_INTCTRL _SFR_MEM8(0x0222) -#define ADCA_CH0_INTFLAGS _SFR_MEM8(0x0223) -#define ADCA_CH0_RES _SFR_MEM16(0x0224) -#define ADCA_CH0_SCAN _SFR_MEM8(0x0226) - -/* AC - Analog Comparator */ -#define ACA_AC0CTRL _SFR_MEM8(0x0380) -#define ACA_AC1CTRL _SFR_MEM8(0x0381) -#define ACA_AC0MUXCTRL _SFR_MEM8(0x0382) -#define ACA_AC1MUXCTRL _SFR_MEM8(0x0383) -#define ACA_CTRLA _SFR_MEM8(0x0384) -#define ACA_CTRLB _SFR_MEM8(0x0385) -#define ACA_WINCTRL _SFR_MEM8(0x0386) -#define ACA_STATUS _SFR_MEM8(0x0387) - -/* RTC - Real-Time Counter */ -#define RTC_CTRL _SFR_MEM8(0x0400) -#define RTC_STATUS _SFR_MEM8(0x0401) -#define RTC_INTCTRL _SFR_MEM8(0x0402) -#define RTC_INTFLAGS _SFR_MEM8(0x0403) -#define RTC_TEMP _SFR_MEM8(0x0404) -#define RTC_CNT _SFR_MEM16(0x0408) -#define RTC_PER _SFR_MEM16(0x040A) -#define RTC_COMP _SFR_MEM16(0x040C) - -/* TWI - Two-Wire Interface */ -#define TWIC_CTRL _SFR_MEM8(0x0480) -#define TWIC_MASTER_CTRLA _SFR_MEM8(0x0481) -#define TWIC_MASTER_CTRLB _SFR_MEM8(0x0482) -#define TWIC_MASTER_CTRLC _SFR_MEM8(0x0483) -#define TWIC_MASTER_STATUS _SFR_MEM8(0x0484) -#define TWIC_MASTER_BAUD _SFR_MEM8(0x0485) -#define TWIC_MASTER_ADDR _SFR_MEM8(0x0486) -#define TWIC_MASTER_DATA _SFR_MEM8(0x0487) -#define TWIC_SLAVE_CTRLA _SFR_MEM8(0x0488) -#define TWIC_SLAVE_CTRLB _SFR_MEM8(0x0489) -#define TWIC_SLAVE_STATUS _SFR_MEM8(0x048A) -#define TWIC_SLAVE_ADDR _SFR_MEM8(0x048B) -#define TWIC_SLAVE_DATA _SFR_MEM8(0x048C) -#define TWIC_SLAVE_ADDRMASK _SFR_MEM8(0x048D) - -/* TWI - Two-Wire Interface */ -#define TWIE_CTRL _SFR_MEM8(0x04A0) -#define TWIE_MASTER_CTRLA _SFR_MEM8(0x04A1) -#define TWIE_MASTER_CTRLB _SFR_MEM8(0x04A2) -#define TWIE_MASTER_CTRLC _SFR_MEM8(0x04A3) -#define TWIE_MASTER_STATUS _SFR_MEM8(0x04A4) -#define TWIE_MASTER_BAUD _SFR_MEM8(0x04A5) -#define TWIE_MASTER_ADDR _SFR_MEM8(0x04A6) -#define TWIE_MASTER_DATA _SFR_MEM8(0x04A7) -#define TWIE_SLAVE_CTRLA _SFR_MEM8(0x04A8) -#define TWIE_SLAVE_CTRLB _SFR_MEM8(0x04A9) -#define TWIE_SLAVE_STATUS _SFR_MEM8(0x04AA) -#define TWIE_SLAVE_ADDR _SFR_MEM8(0x04AB) -#define TWIE_SLAVE_DATA _SFR_MEM8(0x04AC) -#define TWIE_SLAVE_ADDRMASK _SFR_MEM8(0x04AD) - -/* USB - Universal Serial Bus */ -#define USB_CTRLA _SFR_MEM8(0x04C0) -#define USB_CTRLB _SFR_MEM8(0x04C1) -#define USB_STATUS _SFR_MEM8(0x04C2) -#define USB_ADDR _SFR_MEM8(0x04C3) -#define USB_FIFOWP _SFR_MEM8(0x04C4) -#define USB_FIFORP _SFR_MEM8(0x04C5) -#define USB_EPPTR _SFR_MEM16(0x04C6) -#define USB_INTCTRLA _SFR_MEM8(0x04C8) -#define USB_INTCTRLB _SFR_MEM8(0x04C9) -#define USB_INTFLAGSACLR _SFR_MEM8(0x04CA) -#define USB_INTFLAGSASET _SFR_MEM8(0x04CB) -#define USB_INTFLAGSBCLR _SFR_MEM8(0x04CC) -#define USB_INTFLAGSBSET _SFR_MEM8(0x04CD) -#define USB_CAL0 _SFR_MEM8(0x04FA) -#define USB_CAL1 _SFR_MEM8(0x04FB) - -/* PORT - I/O Ports */ -#define PORTA_DIR _SFR_MEM8(0x0600) -#define PORTA_DIRSET _SFR_MEM8(0x0601) -#define PORTA_DIRCLR _SFR_MEM8(0x0602) -#define PORTA_DIRTGL _SFR_MEM8(0x0603) -#define PORTA_OUT _SFR_MEM8(0x0604) -#define PORTA_OUTSET _SFR_MEM8(0x0605) -#define PORTA_OUTCLR _SFR_MEM8(0x0606) -#define PORTA_OUTTGL _SFR_MEM8(0x0607) -#define PORTA_IN _SFR_MEM8(0x0608) -#define PORTA_INTCTRL _SFR_MEM8(0x0609) -#define PORTA_INT0MASK _SFR_MEM8(0x060A) -#define PORTA_INT1MASK _SFR_MEM8(0x060B) -#define PORTA_INTFLAGS _SFR_MEM8(0x060C) -#define PORTA_REMAP _SFR_MEM8(0x060E) -#define PORTA_PIN0CTRL _SFR_MEM8(0x0610) -#define PORTA_PIN1CTRL _SFR_MEM8(0x0611) -#define PORTA_PIN2CTRL _SFR_MEM8(0x0612) -#define PORTA_PIN3CTRL _SFR_MEM8(0x0613) -#define PORTA_PIN4CTRL _SFR_MEM8(0x0614) -#define PORTA_PIN5CTRL _SFR_MEM8(0x0615) -#define PORTA_PIN6CTRL _SFR_MEM8(0x0616) -#define PORTA_PIN7CTRL _SFR_MEM8(0x0617) - -/* PORT - I/O Ports */ -#define PORTB_DIR _SFR_MEM8(0x0620) -#define PORTB_DIRSET _SFR_MEM8(0x0621) -#define PORTB_DIRCLR _SFR_MEM8(0x0622) -#define PORTB_DIRTGL _SFR_MEM8(0x0623) -#define PORTB_OUT _SFR_MEM8(0x0624) -#define PORTB_OUTSET _SFR_MEM8(0x0625) -#define PORTB_OUTCLR _SFR_MEM8(0x0626) -#define PORTB_OUTTGL _SFR_MEM8(0x0627) -#define PORTB_IN _SFR_MEM8(0x0628) -#define PORTB_INTCTRL _SFR_MEM8(0x0629) -#define PORTB_INT0MASK _SFR_MEM8(0x062A) -#define PORTB_INT1MASK _SFR_MEM8(0x062B) -#define PORTB_INTFLAGS _SFR_MEM8(0x062C) -#define PORTB_REMAP _SFR_MEM8(0x062E) -#define PORTB_PIN0CTRL _SFR_MEM8(0x0630) -#define PORTB_PIN1CTRL _SFR_MEM8(0x0631) -#define PORTB_PIN2CTRL _SFR_MEM8(0x0632) -#define PORTB_PIN3CTRL _SFR_MEM8(0x0633) -#define PORTB_PIN4CTRL _SFR_MEM8(0x0634) -#define PORTB_PIN5CTRL _SFR_MEM8(0x0635) -#define PORTB_PIN6CTRL _SFR_MEM8(0x0636) -#define PORTB_PIN7CTRL _SFR_MEM8(0x0637) - -/* PORT - I/O Ports */ -#define PORTC_DIR _SFR_MEM8(0x0640) -#define PORTC_DIRSET _SFR_MEM8(0x0641) -#define PORTC_DIRCLR _SFR_MEM8(0x0642) -#define PORTC_DIRTGL _SFR_MEM8(0x0643) -#define PORTC_OUT _SFR_MEM8(0x0644) -#define PORTC_OUTSET _SFR_MEM8(0x0645) -#define PORTC_OUTCLR _SFR_MEM8(0x0646) -#define PORTC_OUTTGL _SFR_MEM8(0x0647) -#define PORTC_IN _SFR_MEM8(0x0648) -#define PORTC_INTCTRL _SFR_MEM8(0x0649) -#define PORTC_INT0MASK _SFR_MEM8(0x064A) -#define PORTC_INT1MASK _SFR_MEM8(0x064B) -#define PORTC_INTFLAGS _SFR_MEM8(0x064C) -#define PORTC_REMAP _SFR_MEM8(0x064E) -#define PORTC_PIN0CTRL _SFR_MEM8(0x0650) -#define PORTC_PIN1CTRL _SFR_MEM8(0x0651) -#define PORTC_PIN2CTRL _SFR_MEM8(0x0652) -#define PORTC_PIN3CTRL _SFR_MEM8(0x0653) -#define PORTC_PIN4CTRL _SFR_MEM8(0x0654) -#define PORTC_PIN5CTRL _SFR_MEM8(0x0655) -#define PORTC_PIN6CTRL _SFR_MEM8(0x0656) -#define PORTC_PIN7CTRL _SFR_MEM8(0x0657) - -/* PORT - I/O Ports */ -#define PORTD_DIR _SFR_MEM8(0x0660) -#define PORTD_DIRSET _SFR_MEM8(0x0661) -#define PORTD_DIRCLR _SFR_MEM8(0x0662) -#define PORTD_DIRTGL _SFR_MEM8(0x0663) -#define PORTD_OUT _SFR_MEM8(0x0664) -#define PORTD_OUTSET _SFR_MEM8(0x0665) -#define PORTD_OUTCLR _SFR_MEM8(0x0666) -#define PORTD_OUTTGL _SFR_MEM8(0x0667) -#define PORTD_IN _SFR_MEM8(0x0668) -#define PORTD_INTCTRL _SFR_MEM8(0x0669) -#define PORTD_INT0MASK _SFR_MEM8(0x066A) -#define PORTD_INT1MASK _SFR_MEM8(0x066B) -#define PORTD_INTFLAGS _SFR_MEM8(0x066C) -#define PORTD_REMAP _SFR_MEM8(0x066E) -#define PORTD_PIN0CTRL _SFR_MEM8(0x0670) -#define PORTD_PIN1CTRL _SFR_MEM8(0x0671) -#define PORTD_PIN2CTRL _SFR_MEM8(0x0672) -#define PORTD_PIN3CTRL _SFR_MEM8(0x0673) -#define PORTD_PIN4CTRL _SFR_MEM8(0x0674) -#define PORTD_PIN5CTRL _SFR_MEM8(0x0675) -#define PORTD_PIN6CTRL _SFR_MEM8(0x0676) -#define PORTD_PIN7CTRL _SFR_MEM8(0x0677) - -/* PORT - I/O Ports */ -#define PORTE_DIR _SFR_MEM8(0x0680) -#define PORTE_DIRSET _SFR_MEM8(0x0681) -#define PORTE_DIRCLR _SFR_MEM8(0x0682) -#define PORTE_DIRTGL _SFR_MEM8(0x0683) -#define PORTE_OUT _SFR_MEM8(0x0684) -#define PORTE_OUTSET _SFR_MEM8(0x0685) -#define PORTE_OUTCLR _SFR_MEM8(0x0686) -#define PORTE_OUTTGL _SFR_MEM8(0x0687) -#define PORTE_IN _SFR_MEM8(0x0688) -#define PORTE_INTCTRL _SFR_MEM8(0x0689) -#define PORTE_INT0MASK _SFR_MEM8(0x068A) -#define PORTE_INT1MASK _SFR_MEM8(0x068B) -#define PORTE_INTFLAGS _SFR_MEM8(0x068C) -#define PORTE_REMAP _SFR_MEM8(0x068E) -#define PORTE_PIN0CTRL _SFR_MEM8(0x0690) -#define PORTE_PIN1CTRL _SFR_MEM8(0x0691) -#define PORTE_PIN2CTRL _SFR_MEM8(0x0692) -#define PORTE_PIN3CTRL _SFR_MEM8(0x0693) -#define PORTE_PIN4CTRL _SFR_MEM8(0x0694) -#define PORTE_PIN5CTRL _SFR_MEM8(0x0695) -#define PORTE_PIN6CTRL _SFR_MEM8(0x0696) -#define PORTE_PIN7CTRL _SFR_MEM8(0x0697) - -/* PORT - I/O Ports */ -#define PORTF_DIR _SFR_MEM8(0x06A0) -#define PORTF_DIRSET _SFR_MEM8(0x06A1) -#define PORTF_DIRCLR _SFR_MEM8(0x06A2) -#define PORTF_DIRTGL _SFR_MEM8(0x06A3) -#define PORTF_OUT _SFR_MEM8(0x06A4) -#define PORTF_OUTSET _SFR_MEM8(0x06A5) -#define PORTF_OUTCLR _SFR_MEM8(0x06A6) -#define PORTF_OUTTGL _SFR_MEM8(0x06A7) -#define PORTF_IN _SFR_MEM8(0x06A8) -#define PORTF_INTCTRL _SFR_MEM8(0x06A9) -#define PORTF_INT0MASK _SFR_MEM8(0x06AA) -#define PORTF_INT1MASK _SFR_MEM8(0x06AB) -#define PORTF_INTFLAGS _SFR_MEM8(0x06AC) -#define PORTF_REMAP _SFR_MEM8(0x06AE) -#define PORTF_PIN0CTRL _SFR_MEM8(0x06B0) -#define PORTF_PIN1CTRL _SFR_MEM8(0x06B1) -#define PORTF_PIN2CTRL _SFR_MEM8(0x06B2) -#define PORTF_PIN3CTRL _SFR_MEM8(0x06B3) -#define PORTF_PIN4CTRL _SFR_MEM8(0x06B4) -#define PORTF_PIN5CTRL _SFR_MEM8(0x06B5) -#define PORTF_PIN6CTRL _SFR_MEM8(0x06B6) -#define PORTF_PIN7CTRL _SFR_MEM8(0x06B7) - -/* PORT - I/O Ports */ -#define PORTR_DIR _SFR_MEM8(0x07E0) -#define PORTR_DIRSET _SFR_MEM8(0x07E1) -#define PORTR_DIRCLR _SFR_MEM8(0x07E2) -#define PORTR_DIRTGL _SFR_MEM8(0x07E3) -#define PORTR_OUT _SFR_MEM8(0x07E4) -#define PORTR_OUTSET _SFR_MEM8(0x07E5) -#define PORTR_OUTCLR _SFR_MEM8(0x07E6) -#define PORTR_OUTTGL _SFR_MEM8(0x07E7) -#define PORTR_IN _SFR_MEM8(0x07E8) -#define PORTR_INTCTRL _SFR_MEM8(0x07E9) -#define PORTR_INT0MASK _SFR_MEM8(0x07EA) -#define PORTR_INT1MASK _SFR_MEM8(0x07EB) -#define PORTR_INTFLAGS _SFR_MEM8(0x07EC) -#define PORTR_REMAP _SFR_MEM8(0x07EE) -#define PORTR_PIN0CTRL _SFR_MEM8(0x07F0) -#define PORTR_PIN1CTRL _SFR_MEM8(0x07F1) -#define PORTR_PIN2CTRL _SFR_MEM8(0x07F2) -#define PORTR_PIN3CTRL _SFR_MEM8(0x07F3) -#define PORTR_PIN4CTRL _SFR_MEM8(0x07F4) -#define PORTR_PIN5CTRL _SFR_MEM8(0x07F5) -#define PORTR_PIN6CTRL _SFR_MEM8(0x07F6) -#define PORTR_PIN7CTRL _SFR_MEM8(0x07F7) - -/* TC0 - 16-bit Timer/Counter 0 */ -#define TCC0_CTRLA _SFR_MEM8(0x0800) -#define TCC0_CTRLB _SFR_MEM8(0x0801) -#define TCC0_CTRLC _SFR_MEM8(0x0802) -#define TCC0_CTRLD _SFR_MEM8(0x0803) -#define TCC0_CTRLE _SFR_MEM8(0x0804) -#define TCC0_INTCTRLA _SFR_MEM8(0x0806) -#define TCC0_INTCTRLB _SFR_MEM8(0x0807) -#define TCC0_CTRLFCLR _SFR_MEM8(0x0808) -#define TCC0_CTRLFSET _SFR_MEM8(0x0809) -#define TCC0_CTRLGCLR _SFR_MEM8(0x080A) -#define TCC0_CTRLGSET _SFR_MEM8(0x080B) -#define TCC0_INTFLAGS _SFR_MEM8(0x080C) -#define TCC0_TEMP _SFR_MEM8(0x080F) -#define TCC0_CNT _SFR_MEM16(0x0820) -#define TCC0_PER _SFR_MEM16(0x0826) -#define TCC0_CCA _SFR_MEM16(0x0828) -#define TCC0_CCB _SFR_MEM16(0x082A) -#define TCC0_CCC _SFR_MEM16(0x082C) -#define TCC0_CCD _SFR_MEM16(0x082E) -#define TCC0_PERBUF _SFR_MEM16(0x0836) -#define TCC0_CCABUF _SFR_MEM16(0x0838) -#define TCC0_CCBBUF _SFR_MEM16(0x083A) -#define TCC0_CCCBUF _SFR_MEM16(0x083C) -#define TCC0_CCDBUF _SFR_MEM16(0x083E) - -/* TC2 - 16-bit Timer/Counter type 2 */ -#define TCC2_CTRLA _SFR_MEM8(0x0800) -#define TCC2_CTRLB _SFR_MEM8(0x0801) -#define TCC2_CTRLC _SFR_MEM8(0x0802) -#define TCC2_CTRLE _SFR_MEM8(0x0804) -#define TCC2_INTCTRLA _SFR_MEM8(0x0806) -#define TCC2_INTCTRLB _SFR_MEM8(0x0807) -#define TCC2_CTRLF _SFR_MEM8(0x0809) -#define TCC2_INTFLAGS _SFR_MEM8(0x080C) -#define TCC2_LCNT _SFR_MEM8(0x0820) -#define TCC2_HCNT _SFR_MEM8(0x0821) -#define TCC2_LPER _SFR_MEM8(0x0826) -#define TCC2_HPER _SFR_MEM8(0x0827) -#define TCC2_LCMPA _SFR_MEM8(0x0828) -#define TCC2_HCMPA _SFR_MEM8(0x0829) -#define TCC2_LCMPB _SFR_MEM8(0x082A) -#define TCC2_HCMPB _SFR_MEM8(0x082B) -#define TCC2_LCMPC _SFR_MEM8(0x082C) -#define TCC2_HCMPC _SFR_MEM8(0x082D) -#define TCC2_LCMPD _SFR_MEM8(0x082E) -#define TCC2_HCMPD _SFR_MEM8(0x082F) - -/* TC1 - 16-bit Timer/Counter 1 */ -#define TCC1_CTRLA _SFR_MEM8(0x0840) -#define TCC1_CTRLB _SFR_MEM8(0x0841) -#define TCC1_CTRLC _SFR_MEM8(0x0842) -#define TCC1_CTRLD _SFR_MEM8(0x0843) -#define TCC1_CTRLE _SFR_MEM8(0x0844) -#define TCC1_INTCTRLA _SFR_MEM8(0x0846) -#define TCC1_INTCTRLB _SFR_MEM8(0x0847) -#define TCC1_CTRLFCLR _SFR_MEM8(0x0848) -#define TCC1_CTRLFSET _SFR_MEM8(0x0849) -#define TCC1_CTRLGCLR _SFR_MEM8(0x084A) -#define TCC1_CTRLGSET _SFR_MEM8(0x084B) -#define TCC1_INTFLAGS _SFR_MEM8(0x084C) -#define TCC1_TEMP _SFR_MEM8(0x084F) -#define TCC1_CNT _SFR_MEM16(0x0860) -#define TCC1_PER _SFR_MEM16(0x0866) -#define TCC1_CCA _SFR_MEM16(0x0868) -#define TCC1_CCB _SFR_MEM16(0x086A) -#define TCC1_PERBUF _SFR_MEM16(0x0876) -#define TCC1_CCABUF _SFR_MEM16(0x0878) -#define TCC1_CCBBUF _SFR_MEM16(0x087A) - -/* AWEX - Advanced Waveform Extension */ -#define AWEXC_CTRL _SFR_MEM8(0x0880) -#define AWEXC_FDEMASK _SFR_MEM8(0x0882) -#define AWEXC_FDCTRL _SFR_MEM8(0x0883) -#define AWEXC_STATUS _SFR_MEM8(0x0884) -#define AWEXC_STATUSSET _SFR_MEM8(0x0885) -#define AWEXC_DTBOTH _SFR_MEM8(0x0886) -#define AWEXC_DTBOTHBUF _SFR_MEM8(0x0887) -#define AWEXC_DTLS _SFR_MEM8(0x0888) -#define AWEXC_DTHS _SFR_MEM8(0x0889) -#define AWEXC_DTLSBUF _SFR_MEM8(0x088A) -#define AWEXC_DTHSBUF _SFR_MEM8(0x088B) -#define AWEXC_OUTOVEN _SFR_MEM8(0x088C) - -/* HIRES - High-Resolution Extension */ -#define HIRESC_CTRLA _SFR_MEM8(0x0890) - -/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ -#define USARTC0_DATA _SFR_MEM8(0x08A0) -#define USARTC0_STATUS _SFR_MEM8(0x08A1) -#define USARTC0_CTRLA _SFR_MEM8(0x08A3) -#define USARTC0_CTRLB _SFR_MEM8(0x08A4) -#define USARTC0_CTRLC _SFR_MEM8(0x08A5) -#define USARTC0_BAUDCTRLA _SFR_MEM8(0x08A6) -#define USARTC0_BAUDCTRLB _SFR_MEM8(0x08A7) - -/* SPI - Serial Peripheral Interface */ -#define SPIC_CTRL _SFR_MEM8(0x08C0) -#define SPIC_INTCTRL _SFR_MEM8(0x08C1) -#define SPIC_STATUS _SFR_MEM8(0x08C2) -#define SPIC_DATA _SFR_MEM8(0x08C3) - -/* IRCOM - IR Communication Module */ -#define IRCOM_CTRL _SFR_MEM8(0x08F8) -#define IRCOM_TXPLCTRL _SFR_MEM8(0x08F9) -#define IRCOM_RXPLCTRL _SFR_MEM8(0x08FA) - -/* TC0 - 16-bit Timer/Counter 0 */ -#define TCD0_CTRLA _SFR_MEM8(0x0900) -#define TCD0_CTRLB _SFR_MEM8(0x0901) -#define TCD0_CTRLC _SFR_MEM8(0x0902) -#define TCD0_CTRLD _SFR_MEM8(0x0903) -#define TCD0_CTRLE _SFR_MEM8(0x0904) -#define TCD0_INTCTRLA _SFR_MEM8(0x0906) -#define TCD0_INTCTRLB _SFR_MEM8(0x0907) -#define TCD0_CTRLFCLR _SFR_MEM8(0x0908) -#define TCD0_CTRLFSET _SFR_MEM8(0x0909) -#define TCD0_CTRLGCLR _SFR_MEM8(0x090A) -#define TCD0_CTRLGSET _SFR_MEM8(0x090B) -#define TCD0_INTFLAGS _SFR_MEM8(0x090C) -#define TCD0_TEMP _SFR_MEM8(0x090F) -#define TCD0_CNT _SFR_MEM16(0x0920) -#define TCD0_PER _SFR_MEM16(0x0926) -#define TCD0_CCA _SFR_MEM16(0x0928) -#define TCD0_CCB _SFR_MEM16(0x092A) -#define TCD0_CCC _SFR_MEM16(0x092C) -#define TCD0_CCD _SFR_MEM16(0x092E) -#define TCD0_PERBUF _SFR_MEM16(0x0936) -#define TCD0_CCABUF _SFR_MEM16(0x0938) -#define TCD0_CCBBUF _SFR_MEM16(0x093A) -#define TCD0_CCCBUF _SFR_MEM16(0x093C) -#define TCD0_CCDBUF _SFR_MEM16(0x093E) - -/* TC2 - 16-bit Timer/Counter type 2 */ -#define TCD2_CTRLA _SFR_MEM8(0x0900) -#define TCD2_CTRLB _SFR_MEM8(0x0901) -#define TCD2_CTRLC _SFR_MEM8(0x0902) -#define TCD2_CTRLE _SFR_MEM8(0x0904) -#define TCD2_INTCTRLA _SFR_MEM8(0x0906) -#define TCD2_INTCTRLB _SFR_MEM8(0x0907) -#define TCD2_CTRLF _SFR_MEM8(0x0909) -#define TCD2_INTFLAGS _SFR_MEM8(0x090C) -#define TCD2_LCNT _SFR_MEM8(0x0920) -#define TCD2_HCNT _SFR_MEM8(0x0921) -#define TCD2_LPER _SFR_MEM8(0x0926) -#define TCD2_HPER _SFR_MEM8(0x0927) -#define TCD2_LCMPA _SFR_MEM8(0x0928) -#define TCD2_HCMPA _SFR_MEM8(0x0929) -#define TCD2_LCMPB _SFR_MEM8(0x092A) -#define TCD2_HCMPB _SFR_MEM8(0x092B) -#define TCD2_LCMPC _SFR_MEM8(0x092C) -#define TCD2_HCMPC _SFR_MEM8(0x092D) -#define TCD2_LCMPD _SFR_MEM8(0x092E) -#define TCD2_HCMPD _SFR_MEM8(0x092F) - -/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ -#define USARTD0_DATA _SFR_MEM8(0x09A0) -#define USARTD0_STATUS _SFR_MEM8(0x09A1) -#define USARTD0_CTRLA _SFR_MEM8(0x09A3) -#define USARTD0_CTRLB _SFR_MEM8(0x09A4) -#define USARTD0_CTRLC _SFR_MEM8(0x09A5) -#define USARTD0_BAUDCTRLA _SFR_MEM8(0x09A6) -#define USARTD0_BAUDCTRLB _SFR_MEM8(0x09A7) - -/* SPI - Serial Peripheral Interface */ -#define SPID_CTRL _SFR_MEM8(0x09C0) -#define SPID_INTCTRL _SFR_MEM8(0x09C1) -#define SPID_STATUS _SFR_MEM8(0x09C2) -#define SPID_DATA _SFR_MEM8(0x09C3) - -/* TC0 - 16-bit Timer/Counter 0 */ -#define TCE0_CTRLA _SFR_MEM8(0x0A00) -#define TCE0_CTRLB _SFR_MEM8(0x0A01) -#define TCE0_CTRLC _SFR_MEM8(0x0A02) -#define TCE0_CTRLD _SFR_MEM8(0x0A03) -#define TCE0_CTRLE _SFR_MEM8(0x0A04) -#define TCE0_INTCTRLA _SFR_MEM8(0x0A06) -#define TCE0_INTCTRLB _SFR_MEM8(0x0A07) -#define TCE0_CTRLFCLR _SFR_MEM8(0x0A08) -#define TCE0_CTRLFSET _SFR_MEM8(0x0A09) -#define TCE0_CTRLGCLR _SFR_MEM8(0x0A0A) -#define TCE0_CTRLGSET _SFR_MEM8(0x0A0B) -#define TCE0_INTFLAGS _SFR_MEM8(0x0A0C) -#define TCE0_TEMP _SFR_MEM8(0x0A0F) -#define TCE0_CNT _SFR_MEM16(0x0A20) -#define TCE0_PER _SFR_MEM16(0x0A26) -#define TCE0_CCA _SFR_MEM16(0x0A28) -#define TCE0_CCB _SFR_MEM16(0x0A2A) -#define TCE0_CCC _SFR_MEM16(0x0A2C) -#define TCE0_CCD _SFR_MEM16(0x0A2E) -#define TCE0_PERBUF _SFR_MEM16(0x0A36) -#define TCE0_CCABUF _SFR_MEM16(0x0A38) -#define TCE0_CCBBUF _SFR_MEM16(0x0A3A) -#define TCE0_CCCBUF _SFR_MEM16(0x0A3C) -#define TCE0_CCDBUF _SFR_MEM16(0x0A3E) - -/* TC2 - 16-bit Timer/Counter type 2 */ -#define TCE2_CTRLA _SFR_MEM8(0x0A00) -#define TCE2_CTRLB _SFR_MEM8(0x0A01) -#define TCE2_CTRLC _SFR_MEM8(0x0A02) -#define TCE2_CTRLE _SFR_MEM8(0x0A04) -#define TCE2_INTCTRLA _SFR_MEM8(0x0A06) -#define TCE2_INTCTRLB _SFR_MEM8(0x0A07) -#define TCE2_CTRLF _SFR_MEM8(0x0A09) -#define TCE2_INTFLAGS _SFR_MEM8(0x0A0C) -#define TCE2_LCNT _SFR_MEM8(0x0A20) -#define TCE2_HCNT _SFR_MEM8(0x0A21) -#define TCE2_LPER _SFR_MEM8(0x0A26) -#define TCE2_HPER _SFR_MEM8(0x0A27) -#define TCE2_LCMPA _SFR_MEM8(0x0A28) -#define TCE2_HCMPA _SFR_MEM8(0x0A29) -#define TCE2_LCMPB _SFR_MEM8(0x0A2A) -#define TCE2_HCMPB _SFR_MEM8(0x0A2B) -#define TCE2_LCMPC _SFR_MEM8(0x0A2C) -#define TCE2_HCMPC _SFR_MEM8(0x0A2D) -#define TCE2_LCMPD _SFR_MEM8(0x0A2E) -#define TCE2_HCMPD _SFR_MEM8(0x0A2F) - -/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ -#define USARTE0_DATA _SFR_MEM8(0x0AA0) -#define USARTE0_STATUS _SFR_MEM8(0x0AA1) -#define USARTE0_CTRLA _SFR_MEM8(0x0AA3) -#define USARTE0_CTRLB _SFR_MEM8(0x0AA4) -#define USARTE0_CTRLC _SFR_MEM8(0x0AA5) -#define USARTE0_BAUDCTRLA _SFR_MEM8(0x0AA6) -#define USARTE0_BAUDCTRLB _SFR_MEM8(0x0AA7) - -/* TC0 - 16-bit Timer/Counter 0 */ -#define TCF0_CTRLA _SFR_MEM8(0x0B00) -#define TCF0_CTRLB _SFR_MEM8(0x0B01) -#define TCF0_CTRLC _SFR_MEM8(0x0B02) -#define TCF0_CTRLD _SFR_MEM8(0x0B03) -#define TCF0_CTRLE _SFR_MEM8(0x0B04) -#define TCF0_INTCTRLA _SFR_MEM8(0x0B06) -#define TCF0_INTCTRLB _SFR_MEM8(0x0B07) -#define TCF0_CTRLFCLR _SFR_MEM8(0x0B08) -#define TCF0_CTRLFSET _SFR_MEM8(0x0B09) -#define TCF0_CTRLGCLR _SFR_MEM8(0x0B0A) -#define TCF0_CTRLGSET _SFR_MEM8(0x0B0B) -#define TCF0_INTFLAGS _SFR_MEM8(0x0B0C) -#define TCF0_TEMP _SFR_MEM8(0x0B0F) -#define TCF0_CNT _SFR_MEM16(0x0B20) -#define TCF0_PER _SFR_MEM16(0x0B26) -#define TCF0_CCA _SFR_MEM16(0x0B28) -#define TCF0_CCB _SFR_MEM16(0x0B2A) -#define TCF0_CCC _SFR_MEM16(0x0B2C) -#define TCF0_CCD _SFR_MEM16(0x0B2E) -#define TCF0_PERBUF _SFR_MEM16(0x0B36) -#define TCF0_CCABUF _SFR_MEM16(0x0B38) -#define TCF0_CCBBUF _SFR_MEM16(0x0B3A) -#define TCF0_CCCBUF _SFR_MEM16(0x0B3C) -#define TCF0_CCDBUF _SFR_MEM16(0x0B3E) - -/* TC2 - 16-bit Timer/Counter type 2 */ -#define TCF2_CTRLA _SFR_MEM8(0x0B00) -#define TCF2_CTRLB _SFR_MEM8(0x0B01) -#define TCF2_CTRLC _SFR_MEM8(0x0B02) -#define TCF2_CTRLE _SFR_MEM8(0x0B04) -#define TCF2_INTCTRLA _SFR_MEM8(0x0B06) -#define TCF2_INTCTRLB _SFR_MEM8(0x0B07) -#define TCF2_CTRLF _SFR_MEM8(0x0B09) -#define TCF2_INTFLAGS _SFR_MEM8(0x0B0C) -#define TCF2_LCNT _SFR_MEM8(0x0B20) -#define TCF2_HCNT _SFR_MEM8(0x0B21) -#define TCF2_LPER _SFR_MEM8(0x0B26) -#define TCF2_HPER _SFR_MEM8(0x0B27) -#define TCF2_LCMPA _SFR_MEM8(0x0B28) -#define TCF2_HCMPA _SFR_MEM8(0x0B29) -#define TCF2_LCMPB _SFR_MEM8(0x0B2A) -#define TCF2_HCMPB _SFR_MEM8(0x0B2B) -#define TCF2_LCMPC _SFR_MEM8(0x0B2C) -#define TCF2_HCMPC _SFR_MEM8(0x0B2D) -#define TCF2_LCMPD _SFR_MEM8(0x0B2E) -#define TCF2_HCMPD _SFR_MEM8(0x0B2F) - - - -/*================== Bitfield Definitions ================== */ - -/* VPORT - Virtual Ports */ -/* VPORT.INTFLAGS bit masks and bit positions */ -#define VPORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ -#define VPORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ - -#define VPORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ -#define VPORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ - -/* XOCD - On-Chip Debug System */ -/* OCD.OCDR0 bit masks and bit positions */ -#define OCD_OCDRD_gm 0xFF /* OCDR Dirty group mask. */ -#define OCD_OCDRD_gp 0 /* OCDR Dirty group position. */ -#define OCD_OCDRD0_bm (1<<0) /* OCDR Dirty bit 0 mask. */ -#define OCD_OCDRD0_bp 0 /* OCDR Dirty bit 0 position. */ -#define OCD_OCDRD1_bm (1<<1) /* OCDR Dirty bit 1 mask. */ -#define OCD_OCDRD1_bp 1 /* OCDR Dirty bit 1 position. */ -#define OCD_OCDRD2_bm (1<<2) /* OCDR Dirty bit 2 mask. */ -#define OCD_OCDRD2_bp 2 /* OCDR Dirty bit 2 position. */ -#define OCD_OCDRD3_bm (1<<3) /* OCDR Dirty bit 3 mask. */ -#define OCD_OCDRD3_bp 3 /* OCDR Dirty bit 3 position. */ -#define OCD_OCDRD4_bm (1<<4) /* OCDR Dirty bit 4 mask. */ -#define OCD_OCDRD4_bp 4 /* OCDR Dirty bit 4 position. */ -#define OCD_OCDRD5_bm (1<<5) /* OCDR Dirty bit 5 mask. */ -#define OCD_OCDRD5_bp 5 /* OCDR Dirty bit 5 position. */ -#define OCD_OCDRD6_bm (1<<6) /* OCDR Dirty bit 6 mask. */ -#define OCD_OCDRD6_bp 6 /* OCDR Dirty bit 6 position. */ -#define OCD_OCDRD7_bm (1<<7) /* OCDR Dirty bit 7 mask. */ -#define OCD_OCDRD7_bp 7 /* OCDR Dirty bit 7 position. */ - -/* OCD.OCDR1 bit masks and bit positions */ -/* OCD_OCDRD Predefined. */ -/* OCD_OCDRD Predefined. */ - -/* CPU - CPU */ -/* CPU.CCP bit masks and bit positions */ -#define CPU_CCP_gm 0xFF /* CCP signature group mask. */ -#define CPU_CCP_gp 0 /* CCP signature group position. */ -#define CPU_CCP0_bm (1<<0) /* CCP signature bit 0 mask. */ -#define CPU_CCP0_bp 0 /* CCP signature bit 0 position. */ -#define CPU_CCP1_bm (1<<1) /* CCP signature bit 1 mask. */ -#define CPU_CCP1_bp 1 /* CCP signature bit 1 position. */ -#define CPU_CCP2_bm (1<<2) /* CCP signature bit 2 mask. */ -#define CPU_CCP2_bp 2 /* CCP signature bit 2 position. */ -#define CPU_CCP3_bm (1<<3) /* CCP signature bit 3 mask. */ -#define CPU_CCP3_bp 3 /* CCP signature bit 3 position. */ -#define CPU_CCP4_bm (1<<4) /* CCP signature bit 4 mask. */ -#define CPU_CCP4_bp 4 /* CCP signature bit 4 position. */ -#define CPU_CCP5_bm (1<<5) /* CCP signature bit 5 mask. */ -#define CPU_CCP5_bp 5 /* CCP signature bit 5 position. */ -#define CPU_CCP6_bm (1<<6) /* CCP signature bit 6 mask. */ -#define CPU_CCP6_bp 6 /* CCP signature bit 6 position. */ -#define CPU_CCP7_bm (1<<7) /* CCP signature bit 7 mask. */ -#define CPU_CCP7_bp 7 /* CCP signature bit 7 position. */ - -/* CPU.SREG bit masks and bit positions */ -#define CPU_I_bm 0x80 /* Global Interrupt Enable Flag bit mask. */ -#define CPU_I_bp 7 /* Global Interrupt Enable Flag bit position. */ - -#define CPU_T_bm 0x40 /* Transfer Bit bit mask. */ -#define CPU_T_bp 6 /* Transfer Bit bit position. */ - -#define CPU_H_bm 0x20 /* Half Carry Flag bit mask. */ -#define CPU_H_bp 5 /* Half Carry Flag bit position. */ - -#define CPU_S_bm 0x10 /* N Exclusive Or V Flag bit mask. */ -#define CPU_S_bp 4 /* N Exclusive Or V Flag bit position. */ - -#define CPU_V_bm 0x08 /* Two's Complement Overflow Flag bit mask. */ -#define CPU_V_bp 3 /* Two's Complement Overflow Flag bit position. */ - -#define CPU_N_bm 0x04 /* Negative Flag bit mask. */ -#define CPU_N_bp 2 /* Negative Flag bit position. */ - -#define CPU_Z_bm 0x02 /* Zero Flag bit mask. */ -#define CPU_Z_bp 1 /* Zero Flag bit position. */ - -#define CPU_C_bm 0x01 /* Carry Flag bit mask. */ -#define CPU_C_bp 0 /* Carry Flag bit position. */ - -/* CLK - Clock System */ -/* CLK.CTRL bit masks and bit positions */ -#define CLK_SCLKSEL_gm 0x07 /* System Clock Selection group mask. */ -#define CLK_SCLKSEL_gp 0 /* System Clock Selection group position. */ -#define CLK_SCLKSEL0_bm (1<<0) /* System Clock Selection bit 0 mask. */ -#define CLK_SCLKSEL0_bp 0 /* System Clock Selection bit 0 position. */ -#define CLK_SCLKSEL1_bm (1<<1) /* System Clock Selection bit 1 mask. */ -#define CLK_SCLKSEL1_bp 1 /* System Clock Selection bit 1 position. */ -#define CLK_SCLKSEL2_bm (1<<2) /* System Clock Selection bit 2 mask. */ -#define CLK_SCLKSEL2_bp 2 /* System Clock Selection bit 2 position. */ - -/* CLK.PSCTRL bit masks and bit positions */ -#define CLK_PSADIV_gm 0x7C /* Prescaler A Division Factor group mask. */ -#define CLK_PSADIV_gp 2 /* Prescaler A Division Factor group position. */ -#define CLK_PSADIV0_bm (1<<2) /* Prescaler A Division Factor bit 0 mask. */ -#define CLK_PSADIV0_bp 2 /* Prescaler A Division Factor bit 0 position. */ -#define CLK_PSADIV1_bm (1<<3) /* Prescaler A Division Factor bit 1 mask. */ -#define CLK_PSADIV1_bp 3 /* Prescaler A Division Factor bit 1 position. */ -#define CLK_PSADIV2_bm (1<<4) /* Prescaler A Division Factor bit 2 mask. */ -#define CLK_PSADIV2_bp 4 /* Prescaler A Division Factor bit 2 position. */ -#define CLK_PSADIV3_bm (1<<5) /* Prescaler A Division Factor bit 3 mask. */ -#define CLK_PSADIV3_bp 5 /* Prescaler A Division Factor bit 3 position. */ -#define CLK_PSADIV4_bm (1<<6) /* Prescaler A Division Factor bit 4 mask. */ -#define CLK_PSADIV4_bp 6 /* Prescaler A Division Factor bit 4 position. */ - -#define CLK_PSBCDIV_gm 0x03 /* Prescaler B and C Division factor group mask. */ -#define CLK_PSBCDIV_gp 0 /* Prescaler B and C Division factor group position. */ -#define CLK_PSBCDIV0_bm (1<<0) /* Prescaler B and C Division factor bit 0 mask. */ -#define CLK_PSBCDIV0_bp 0 /* Prescaler B and C Division factor bit 0 position. */ -#define CLK_PSBCDIV1_bm (1<<1) /* Prescaler B and C Division factor bit 1 mask. */ -#define CLK_PSBCDIV1_bp 1 /* Prescaler B and C Division factor bit 1 position. */ - -/* CLK.LOCK bit masks and bit positions */ -#define CLK_LOCK_bm 0x01 /* Clock System Lock bit mask. */ -#define CLK_LOCK_bp 0 /* Clock System Lock bit position. */ - -/* CLK.RTCCTRL bit masks and bit positions */ -#define CLK_RTCSRC_gm 0x0E /* Clock Source group mask. */ -#define CLK_RTCSRC_gp 1 /* Clock Source group position. */ -#define CLK_RTCSRC0_bm (1<<1) /* Clock Source bit 0 mask. */ -#define CLK_RTCSRC0_bp 1 /* Clock Source bit 0 position. */ -#define CLK_RTCSRC1_bm (1<<2) /* Clock Source bit 1 mask. */ -#define CLK_RTCSRC1_bp 2 /* Clock Source bit 1 position. */ -#define CLK_RTCSRC2_bm (1<<3) /* Clock Source bit 2 mask. */ -#define CLK_RTCSRC2_bp 3 /* Clock Source bit 2 position. */ - -#define CLK_RTCEN_bm 0x01 /* Clock Source Enable bit mask. */ -#define CLK_RTCEN_bp 0 /* Clock Source Enable bit position. */ - -/* CLK.USBCTRL bit masks and bit positions */ -#define CLK_USBPSDIV_gm 0x38 /* Prescaler Division Factor group mask. */ -#define CLK_USBPSDIV_gp 3 /* Prescaler Division Factor group position. */ -#define CLK_USBPSDIV0_bm (1<<3) /* Prescaler Division Factor bit 0 mask. */ -#define CLK_USBPSDIV0_bp 3 /* Prescaler Division Factor bit 0 position. */ -#define CLK_USBPSDIV1_bm (1<<4) /* Prescaler Division Factor bit 1 mask. */ -#define CLK_USBPSDIV1_bp 4 /* Prescaler Division Factor bit 1 position. */ -#define CLK_USBPSDIV2_bm (1<<5) /* Prescaler Division Factor bit 2 mask. */ -#define CLK_USBPSDIV2_bp 5 /* Prescaler Division Factor bit 2 position. */ - -#define CLK_USBSRC_gm 0x06 /* Clock Source group mask. */ -#define CLK_USBSRC_gp 1 /* Clock Source group position. */ -#define CLK_USBSRC0_bm (1<<1) /* Clock Source bit 0 mask. */ -#define CLK_USBSRC0_bp 1 /* Clock Source bit 0 position. */ -#define CLK_USBSRC1_bm (1<<2) /* Clock Source bit 1 mask. */ -#define CLK_USBSRC1_bp 2 /* Clock Source bit 1 position. */ - -#define CLK_USBSEN_bm 0x01 /* Clock Source Enable bit mask. */ -#define CLK_USBSEN_bp 0 /* Clock Source Enable bit position. */ - -/* PR.PRGEN bit masks and bit positions */ -#define PR_USB_bm 0x40 /* USB bit mask. */ -#define PR_USB_bp 6 /* USB bit position. */ - -#define PR_AES_bm 0x10 /* AES bit mask. */ -#define PR_AES_bp 4 /* AES bit position. */ - -#define PR_RTC_bm 0x04 /* Real-time Counter bit mask. */ -#define PR_RTC_bp 2 /* Real-time Counter bit position. */ - -#define PR_EVSYS_bm 0x02 /* Event System bit mask. */ -#define PR_EVSYS_bp 1 /* Event System bit position. */ - -#define PR_DMA_bm 0x01 /* DMA-Controller bit mask. */ -#define PR_DMA_bp 0 /* DMA-Controller bit position. */ - -/* PR.PRPA bit masks and bit positions */ -#define PR_ADC_bm 0x02 /* Port A ADC bit mask. */ -#define PR_ADC_bp 1 /* Port A ADC bit position. */ - -#define PR_AC_bm 0x01 /* Port A Analog Comparator bit mask. */ -#define PR_AC_bp 0 /* Port A Analog Comparator bit position. */ - -/* PR.PRPC bit masks and bit positions */ -#define PR_TWI_bm 0x40 /* Port C Two-wire Interface bit mask. */ -#define PR_TWI_bp 6 /* Port C Two-wire Interface bit position. */ - -#define PR_USART1_bm 0x20 /* Port C USART1 bit mask. */ -#define PR_USART1_bp 5 /* Port C USART1 bit position. */ - -#define PR_USART0_bm 0x10 /* Port C USART0 bit mask. */ -#define PR_USART0_bp 4 /* Port C USART0 bit position. */ - -#define PR_SPI_bm 0x08 /* Port C SPI bit mask. */ -#define PR_SPI_bp 3 /* Port C SPI bit position. */ - -#define PR_HIRES_bm 0x04 /* Port C AWEX bit mask. */ -#define PR_HIRES_bp 2 /* Port C AWEX bit position. */ - -#define PR_TC1_bm 0x02 /* Port C Timer/Counter1 bit mask. */ -#define PR_TC1_bp 1 /* Port C Timer/Counter1 bit position. */ - -#define PR_TC0_bm 0x01 /* Port C Timer/Counter0 bit mask. */ -#define PR_TC0_bp 0 /* Port C Timer/Counter0 bit position. */ - -/* PR.PRPD bit masks and bit positions */ -/* PR_USART0 Predefined. */ -/* PR_USART0 Predefined. */ - -/* PR_SPI Predefined. */ -/* PR_SPI Predefined. */ - -/* PR_TC0 Predefined. */ -/* PR_TC0 Predefined. */ - -/* PR.PRPE bit masks and bit positions */ -/* PR_TWI Predefined. */ -/* PR_TWI Predefined. */ - -/* PR_USART0 Predefined. */ -/* PR_USART0 Predefined. */ - -/* PR_TC0 Predefined. */ -/* PR_TC0 Predefined. */ - -/* PR.PRPF bit masks and bit positions */ -/* PR_USART0 Predefined. */ -/* PR_USART0 Predefined. */ - -/* PR_TC0 Predefined. */ -/* PR_TC0 Predefined. */ - -/* SLEEP - Sleep Controller */ -/* SLEEP.CTRL bit masks and bit positions */ -#define SLEEP_SMODE_gm 0x0E /* Sleep Mode group mask. */ -#define SLEEP_SMODE_gp 1 /* Sleep Mode group position. */ -#define SLEEP_SMODE0_bm (1<<1) /* Sleep Mode bit 0 mask. */ -#define SLEEP_SMODE0_bp 1 /* Sleep Mode bit 0 position. */ -#define SLEEP_SMODE1_bm (1<<2) /* Sleep Mode bit 1 mask. */ -#define SLEEP_SMODE1_bp 2 /* Sleep Mode bit 1 position. */ -#define SLEEP_SMODE2_bm (1<<3) /* Sleep Mode bit 2 mask. */ -#define SLEEP_SMODE2_bp 3 /* Sleep Mode bit 2 position. */ - -#define SLEEP_SEN_bm 0x01 /* Sleep Enable bit mask. */ -#define SLEEP_SEN_bp 0 /* Sleep Enable bit position. */ - -/* OSC - Oscillator */ -/* OSC.CTRL bit masks and bit positions */ -#define OSC_PLLEN_bm 0x10 /* PLL Enable bit mask. */ -#define OSC_PLLEN_bp 4 /* PLL Enable bit position. */ - -#define OSC_XOSCEN_bm 0x08 /* External Oscillator Enable bit mask. */ -#define OSC_XOSCEN_bp 3 /* External Oscillator Enable bit position. */ - -#define OSC_RC32KEN_bm 0x04 /* Internal 32.768 kHz RC Oscillator Enable bit mask. */ -#define OSC_RC32KEN_bp 2 /* Internal 32.768 kHz RC Oscillator Enable bit position. */ - -#define OSC_RC32MEN_bm 0x02 /* Internal 32 MHz RC Oscillator Enable bit mask. */ -#define OSC_RC32MEN_bp 1 /* Internal 32 MHz RC Oscillator Enable bit position. */ - -#define OSC_RC2MEN_bm 0x01 /* Internal 2 MHz RC Oscillator Enable bit mask. */ -#define OSC_RC2MEN_bp 0 /* Internal 2 MHz RC Oscillator Enable bit position. */ - -/* OSC.STATUS bit masks and bit positions */ -#define OSC_PLLRDY_bm 0x10 /* PLL Ready bit mask. */ -#define OSC_PLLRDY_bp 4 /* PLL Ready bit position. */ - -#define OSC_XOSCRDY_bm 0x08 /* External Oscillator Ready bit mask. */ -#define OSC_XOSCRDY_bp 3 /* External Oscillator Ready bit position. */ - -#define OSC_RC32KRDY_bm 0x04 /* Internal 32.768 kHz RC Oscillator Ready bit mask. */ -#define OSC_RC32KRDY_bp 2 /* Internal 32.768 kHz RC Oscillator Ready bit position. */ - -#define OSC_RC32MRDY_bm 0x02 /* Internal 32 MHz RC Oscillator Ready bit mask. */ -#define OSC_RC32MRDY_bp 1 /* Internal 32 MHz RC Oscillator Ready bit position. */ - -#define OSC_RC2MRDY_bm 0x01 /* Internal 2 MHz RC Oscillator Ready bit mask. */ -#define OSC_RC2MRDY_bp 0 /* Internal 2 MHz RC Oscillator Ready bit position. */ - -/* OSC.XOSCCTRL bit masks and bit positions */ -#define OSC_FRQRANGE_gm 0xC0 /* Frequency Range group mask. */ -#define OSC_FRQRANGE_gp 6 /* Frequency Range group position. */ -#define OSC_FRQRANGE0_bm (1<<6) /* Frequency Range bit 0 mask. */ -#define OSC_FRQRANGE0_bp 6 /* Frequency Range bit 0 position. */ -#define OSC_FRQRANGE1_bm (1<<7) /* Frequency Range bit 1 mask. */ -#define OSC_FRQRANGE1_bp 7 /* Frequency Range bit 1 position. */ - -#define OSC_X32KLPM_bm 0x20 /* 32.768 kHz XTAL OSC Low-power Mode bit mask. */ -#define OSC_X32KLPM_bp 5 /* 32.768 kHz XTAL OSC Low-power Mode bit position. */ - -#define OSC_XOSCPWR_bm 0x10 /* 16 MHz Crystal Oscillator High Power mode bit mask. */ -#define OSC_XOSCPWR_bp 4 /* 16 MHz Crystal Oscillator High Power mode bit position. */ - -#define OSC_XOSCSEL_gm 0x0F /* External Oscillator Selection and Startup Time group mask. */ -#define OSC_XOSCSEL_gp 0 /* External Oscillator Selection and Startup Time group position. */ -#define OSC_XOSCSEL0_bm (1<<0) /* External Oscillator Selection and Startup Time bit 0 mask. */ -#define OSC_XOSCSEL0_bp 0 /* External Oscillator Selection and Startup Time bit 0 position. */ -#define OSC_XOSCSEL1_bm (1<<1) /* External Oscillator Selection and Startup Time bit 1 mask. */ -#define OSC_XOSCSEL1_bp 1 /* External Oscillator Selection and Startup Time bit 1 position. */ -#define OSC_XOSCSEL2_bm (1<<2) /* External Oscillator Selection and Startup Time bit 2 mask. */ -#define OSC_XOSCSEL2_bp 2 /* External Oscillator Selection and Startup Time bit 2 position. */ -#define OSC_XOSCSEL3_bm (1<<3) /* External Oscillator Selection and Startup Time bit 3 mask. */ -#define OSC_XOSCSEL3_bp 3 /* External Oscillator Selection and Startup Time bit 3 position. */ - -/* OSC.XOSCFAIL bit masks and bit positions */ -#define OSC_PLLFDIF_bm 0x08 /* PLL Failure Detection Interrupt Flag bit mask. */ -#define OSC_PLLFDIF_bp 3 /* PLL Failure Detection Interrupt Flag bit position. */ - -#define OSC_PLLFDEN_bm 0x04 /* PLL Failure Detection Enable bit mask. */ -#define OSC_PLLFDEN_bp 2 /* PLL Failure Detection Enable bit position. */ - -#define OSC_XOSCFDIF_bm 0x02 /* XOSC Failure Detection Interrupt Flag bit mask. */ -#define OSC_XOSCFDIF_bp 1 /* XOSC Failure Detection Interrupt Flag bit position. */ - -#define OSC_XOSCFDEN_bm 0x01 /* XOSC Failure Detection Enable bit mask. */ -#define OSC_XOSCFDEN_bp 0 /* XOSC Failure Detection Enable bit position. */ - -/* OSC.PLLCTRL bit masks and bit positions */ -#define OSC_PLLSRC_gm 0xC0 /* Clock Source group mask. */ -#define OSC_PLLSRC_gp 6 /* Clock Source group position. */ -#define OSC_PLLSRC0_bm (1<<6) /* Clock Source bit 0 mask. */ -#define OSC_PLLSRC0_bp 6 /* Clock Source bit 0 position. */ -#define OSC_PLLSRC1_bm (1<<7) /* Clock Source bit 1 mask. */ -#define OSC_PLLSRC1_bp 7 /* Clock Source bit 1 position. */ - -#define OSC_PLLDIV_bm 0x20 /* Divide by 2 bit mask. */ -#define OSC_PLLDIV_bp 5 /* Divide by 2 bit position. */ - -#define OSC_PLLFAC_gm 0x1F /* Multiplication Factor group mask. */ -#define OSC_PLLFAC_gp 0 /* Multiplication Factor group position. */ -#define OSC_PLLFAC0_bm (1<<0) /* Multiplication Factor bit 0 mask. */ -#define OSC_PLLFAC0_bp 0 /* Multiplication Factor bit 0 position. */ -#define OSC_PLLFAC1_bm (1<<1) /* Multiplication Factor bit 1 mask. */ -#define OSC_PLLFAC1_bp 1 /* Multiplication Factor bit 1 position. */ -#define OSC_PLLFAC2_bm (1<<2) /* Multiplication Factor bit 2 mask. */ -#define OSC_PLLFAC2_bp 2 /* Multiplication Factor bit 2 position. */ -#define OSC_PLLFAC3_bm (1<<3) /* Multiplication Factor bit 3 mask. */ -#define OSC_PLLFAC3_bp 3 /* Multiplication Factor bit 3 position. */ -#define OSC_PLLFAC4_bm (1<<4) /* Multiplication Factor bit 4 mask. */ -#define OSC_PLLFAC4_bp 4 /* Multiplication Factor bit 4 position. */ - -/* OSC.DFLLCTRL bit masks and bit positions */ -#define OSC_RC32MCREF_gm 0x06 /* 32 MHz DFLL Calibration Reference group mask. */ -#define OSC_RC32MCREF_gp 1 /* 32 MHz DFLL Calibration Reference group position. */ -#define OSC_RC32MCREF0_bm (1<<1) /* 32 MHz DFLL Calibration Reference bit 0 mask. */ -#define OSC_RC32MCREF0_bp 1 /* 32 MHz DFLL Calibration Reference bit 0 position. */ -#define OSC_RC32MCREF1_bm (1<<2) /* 32 MHz DFLL Calibration Reference bit 1 mask. */ -#define OSC_RC32MCREF1_bp 2 /* 32 MHz DFLL Calibration Reference bit 1 position. */ - -#define OSC_RC2MCREF_bm 0x01 /* 2 MHz DFLL Calibration Reference bit mask. */ -#define OSC_RC2MCREF_bp 0 /* 2 MHz DFLL Calibration Reference bit position. */ - -/* DFLL - DFLL */ -/* DFLL.CTRL bit masks and bit positions */ -#define DFLL_ENABLE_bm 0x01 /* DFLL Enable bit mask. */ -#define DFLL_ENABLE_bp 0 /* DFLL Enable bit position. */ - -/* DFLL.CALA bit masks and bit positions */ -#define DFLL_CALL_gm 0x7F /* DFLL Calibration Value A group mask. */ -#define DFLL_CALL_gp 0 /* DFLL Calibration Value A group position. */ -#define DFLL_CALL0_bm (1<<0) /* DFLL Calibration Value A bit 0 mask. */ -#define DFLL_CALL0_bp 0 /* DFLL Calibration Value A bit 0 position. */ -#define DFLL_CALL1_bm (1<<1) /* DFLL Calibration Value A bit 1 mask. */ -#define DFLL_CALL1_bp 1 /* DFLL Calibration Value A bit 1 position. */ -#define DFLL_CALL2_bm (1<<2) /* DFLL Calibration Value A bit 2 mask. */ -#define DFLL_CALL2_bp 2 /* DFLL Calibration Value A bit 2 position. */ -#define DFLL_CALL3_bm (1<<3) /* DFLL Calibration Value A bit 3 mask. */ -#define DFLL_CALL3_bp 3 /* DFLL Calibration Value A bit 3 position. */ -#define DFLL_CALL4_bm (1<<4) /* DFLL Calibration Value A bit 4 mask. */ -#define DFLL_CALL4_bp 4 /* DFLL Calibration Value A bit 4 position. */ -#define DFLL_CALL5_bm (1<<5) /* DFLL Calibration Value A bit 5 mask. */ -#define DFLL_CALL5_bp 5 /* DFLL Calibration Value A bit 5 position. */ -#define DFLL_CALL6_bm (1<<6) /* DFLL Calibration Value A bit 6 mask. */ -#define DFLL_CALL6_bp 6 /* DFLL Calibration Value A bit 6 position. */ - -/* DFLL.CALB bit masks and bit positions */ -#define DFLL_CALH_gm 0x3F /* DFLL Calibration Value B group mask. */ -#define DFLL_CALH_gp 0 /* DFLL Calibration Value B group position. */ -#define DFLL_CALH0_bm (1<<0) /* DFLL Calibration Value B bit 0 mask. */ -#define DFLL_CALH0_bp 0 /* DFLL Calibration Value B bit 0 position. */ -#define DFLL_CALH1_bm (1<<1) /* DFLL Calibration Value B bit 1 mask. */ -#define DFLL_CALH1_bp 1 /* DFLL Calibration Value B bit 1 position. */ -#define DFLL_CALH2_bm (1<<2) /* DFLL Calibration Value B bit 2 mask. */ -#define DFLL_CALH2_bp 2 /* DFLL Calibration Value B bit 2 position. */ -#define DFLL_CALH3_bm (1<<3) /* DFLL Calibration Value B bit 3 mask. */ -#define DFLL_CALH3_bp 3 /* DFLL Calibration Value B bit 3 position. */ -#define DFLL_CALH4_bm (1<<4) /* DFLL Calibration Value B bit 4 mask. */ -#define DFLL_CALH4_bp 4 /* DFLL Calibration Value B bit 4 position. */ -#define DFLL_CALH5_bm (1<<5) /* DFLL Calibration Value B bit 5 mask. */ -#define DFLL_CALH5_bp 5 /* DFLL Calibration Value B bit 5 position. */ - -/* RST - Reset */ -/* RST.STATUS bit masks and bit positions */ -#define RST_SDRF_bm 0x40 /* Spike Detection Reset Flag bit mask. */ -#define RST_SDRF_bp 6 /* Spike Detection Reset Flag bit position. */ - -#define RST_SRF_bm 0x20 /* Software Reset Flag bit mask. */ -#define RST_SRF_bp 5 /* Software Reset Flag bit position. */ - -#define RST_PDIRF_bm 0x10 /* Programming and Debug Interface Interface Reset Flag bit mask. */ -#define RST_PDIRF_bp 4 /* Programming and Debug Interface Interface Reset Flag bit position. */ - -#define RST_WDRF_bm 0x08 /* Watchdog Reset Flag bit mask. */ -#define RST_WDRF_bp 3 /* Watchdog Reset Flag bit position. */ - -#define RST_BORF_bm 0x04 /* Brown-out Reset Flag bit mask. */ -#define RST_BORF_bp 2 /* Brown-out Reset Flag bit position. */ - -#define RST_EXTRF_bm 0x02 /* External Reset Flag bit mask. */ -#define RST_EXTRF_bp 1 /* External Reset Flag bit position. */ - -#define RST_PORF_bm 0x01 /* Power-on Reset Flag bit mask. */ -#define RST_PORF_bp 0 /* Power-on Reset Flag bit position. */ - -/* RST.CTRL bit masks and bit positions */ -#define RST_SWRST_bm 0x01 /* Software Reset bit mask. */ -#define RST_SWRST_bp 0 /* Software Reset bit position. */ - -/* WDT - Watch-Dog Timer */ -/* WDT.CTRL bit masks and bit positions */ -#define WDT_PER_gm 0x3C /* Period group mask. */ -#define WDT_PER_gp 2 /* Period group position. */ -#define WDT_PER0_bm (1<<2) /* Period bit 0 mask. */ -#define WDT_PER0_bp 2 /* Period bit 0 position. */ -#define WDT_PER1_bm (1<<3) /* Period bit 1 mask. */ -#define WDT_PER1_bp 3 /* Period bit 1 position. */ -#define WDT_PER2_bm (1<<4) /* Period bit 2 mask. */ -#define WDT_PER2_bp 4 /* Period bit 2 position. */ -#define WDT_PER3_bm (1<<5) /* Period bit 3 mask. */ -#define WDT_PER3_bp 5 /* Period bit 3 position. */ - -#define WDT_ENABLE_bm 0x02 /* Enable bit mask. */ -#define WDT_ENABLE_bp 1 /* Enable bit position. */ - -#define WDT_CEN_bm 0x01 /* Change Enable bit mask. */ -#define WDT_CEN_bp 0 /* Change Enable bit position. */ - -/* WDT.WINCTRL bit masks and bit positions */ -#define WDT_WPER_gm 0x3C /* Windowed Mode Period group mask. */ -#define WDT_WPER_gp 2 /* Windowed Mode Period group position. */ -#define WDT_WPER0_bm (1<<2) /* Windowed Mode Period bit 0 mask. */ -#define WDT_WPER0_bp 2 /* Windowed Mode Period bit 0 position. */ -#define WDT_WPER1_bm (1<<3) /* Windowed Mode Period bit 1 mask. */ -#define WDT_WPER1_bp 3 /* Windowed Mode Period bit 1 position. */ -#define WDT_WPER2_bm (1<<4) /* Windowed Mode Period bit 2 mask. */ -#define WDT_WPER2_bp 4 /* Windowed Mode Period bit 2 position. */ -#define WDT_WPER3_bm (1<<5) /* Windowed Mode Period bit 3 mask. */ -#define WDT_WPER3_bp 5 /* Windowed Mode Period bit 3 position. */ - -#define WDT_WEN_bm 0x02 /* Windowed Mode Enable bit mask. */ -#define WDT_WEN_bp 1 /* Windowed Mode Enable bit position. */ - -#define WDT_WCEN_bm 0x01 /* Windowed Mode Change Enable bit mask. */ -#define WDT_WCEN_bp 0 /* Windowed Mode Change Enable bit position. */ - -/* WDT.STATUS bit masks and bit positions */ -#define WDT_SYNCBUSY_bm 0x01 /* Syncronization busy bit mask. */ -#define WDT_SYNCBUSY_bp 0 /* Syncronization busy bit position. */ - -/* MCU - MCU Control */ -/* MCU.ANAINIT bit masks and bit positions */ -#define MCU_STARTUPDLYA_gm 0x03 /* Analog startup delay Port A group mask. */ -#define MCU_STARTUPDLYA_gp 0 /* Analog startup delay Port A group position. */ -#define MCU_STARTUPDLYA0_bm (1<<0) /* Analog startup delay Port A bit 0 mask. */ -#define MCU_STARTUPDLYA0_bp 0 /* Analog startup delay Port A bit 0 position. */ -#define MCU_STARTUPDLYA1_bm (1<<1) /* Analog startup delay Port A bit 1 mask. */ -#define MCU_STARTUPDLYA1_bp 1 /* Analog startup delay Port A bit 1 position. */ - -/* MCU.EVSYSLOCK bit masks and bit positions */ -#define MCU_EVSYS0LOCK_bm 0x01 /* Event Channel 0-3 Lock bit mask. */ -#define MCU_EVSYS0LOCK_bp 0 /* Event Channel 0-3 Lock bit position. */ - -/* MCU.AWEXLOCK bit masks and bit positions */ -#define MCU_AWEXCLOCK_bm 0x01 /* AWeX on T/C C0 Lock bit mask. */ -#define MCU_AWEXCLOCK_bp 0 /* AWeX on T/C C0 Lock bit position. */ - -/* PMIC - Programmable Multi-level Interrupt Controller */ -/* PMIC.STATUS bit masks and bit positions */ -#define PMIC_NMIEX_bm 0x80 /* Non-maskable Interrupt Executing bit mask. */ -#define PMIC_NMIEX_bp 7 /* Non-maskable Interrupt Executing bit position. */ - -#define PMIC_HILVLEX_bm 0x04 /* High Level Interrupt Executing bit mask. */ -#define PMIC_HILVLEX_bp 2 /* High Level Interrupt Executing bit position. */ - -#define PMIC_MEDLVLEX_bm 0x02 /* Medium Level Interrupt Executing bit mask. */ -#define PMIC_MEDLVLEX_bp 1 /* Medium Level Interrupt Executing bit position. */ - -#define PMIC_LOLVLEX_bm 0x01 /* Low Level Interrupt Executing bit mask. */ -#define PMIC_LOLVLEX_bp 0 /* Low Level Interrupt Executing bit position. */ - -/* PMIC.INTPRI bit masks and bit positions */ -#define PMIC_INTPRI_gm 0xFF /* Interrupt Priority group mask. */ -#define PMIC_INTPRI_gp 0 /* Interrupt Priority group position. */ -#define PMIC_INTPRI0_bm (1<<0) /* Interrupt Priority bit 0 mask. */ -#define PMIC_INTPRI0_bp 0 /* Interrupt Priority bit 0 position. */ -#define PMIC_INTPRI1_bm (1<<1) /* Interrupt Priority bit 1 mask. */ -#define PMIC_INTPRI1_bp 1 /* Interrupt Priority bit 1 position. */ -#define PMIC_INTPRI2_bm (1<<2) /* Interrupt Priority bit 2 mask. */ -#define PMIC_INTPRI2_bp 2 /* Interrupt Priority bit 2 position. */ -#define PMIC_INTPRI3_bm (1<<3) /* Interrupt Priority bit 3 mask. */ -#define PMIC_INTPRI3_bp 3 /* Interrupt Priority bit 3 position. */ -#define PMIC_INTPRI4_bm (1<<4) /* Interrupt Priority bit 4 mask. */ -#define PMIC_INTPRI4_bp 4 /* Interrupt Priority bit 4 position. */ -#define PMIC_INTPRI5_bm (1<<5) /* Interrupt Priority bit 5 mask. */ -#define PMIC_INTPRI5_bp 5 /* Interrupt Priority bit 5 position. */ -#define PMIC_INTPRI6_bm (1<<6) /* Interrupt Priority bit 6 mask. */ -#define PMIC_INTPRI6_bp 6 /* Interrupt Priority bit 6 position. */ -#define PMIC_INTPRI7_bm (1<<7) /* Interrupt Priority bit 7 mask. */ -#define PMIC_INTPRI7_bp 7 /* Interrupt Priority bit 7 position. */ - -/* PMIC.CTRL bit masks and bit positions */ -#define PMIC_RREN_bm 0x80 /* Round-Robin Priority Enable bit mask. */ -#define PMIC_RREN_bp 7 /* Round-Robin Priority Enable bit position. */ - -#define PMIC_IVSEL_bm 0x40 /* Interrupt Vector Select bit mask. */ -#define PMIC_IVSEL_bp 6 /* Interrupt Vector Select bit position. */ - -#define PMIC_HILVLEN_bm 0x04 /* High Level Enable bit mask. */ -#define PMIC_HILVLEN_bp 2 /* High Level Enable bit position. */ - -#define PMIC_MEDLVLEN_bm 0x02 /* Medium Level Enable bit mask. */ -#define PMIC_MEDLVLEN_bp 1 /* Medium Level Enable bit position. */ - -#define PMIC_LOLVLEN_bm 0x01 /* Low Level Enable bit mask. */ -#define PMIC_LOLVLEN_bp 0 /* Low Level Enable bit position. */ - -/* PORTCFG - Port Configuration */ -/* PORTCFG.VPCTRLA bit masks and bit positions */ -#define PORTCFG_VP1MAP_gm 0xF0 /* Virtual Port 1 Mapping group mask. */ -#define PORTCFG_VP1MAP_gp 4 /* Virtual Port 1 Mapping group position. */ -#define PORTCFG_VP1MAP0_bm (1<<4) /* Virtual Port 1 Mapping bit 0 mask. */ -#define PORTCFG_VP1MAP0_bp 4 /* Virtual Port 1 Mapping bit 0 position. */ -#define PORTCFG_VP1MAP1_bm (1<<5) /* Virtual Port 1 Mapping bit 1 mask. */ -#define PORTCFG_VP1MAP1_bp 5 /* Virtual Port 1 Mapping bit 1 position. */ -#define PORTCFG_VP1MAP2_bm (1<<6) /* Virtual Port 1 Mapping bit 2 mask. */ -#define PORTCFG_VP1MAP2_bp 6 /* Virtual Port 1 Mapping bit 2 position. */ -#define PORTCFG_VP1MAP3_bm (1<<7) /* Virtual Port 1 Mapping bit 3 mask. */ -#define PORTCFG_VP1MAP3_bp 7 /* Virtual Port 1 Mapping bit 3 position. */ - -#define PORTCFG_VP0MAP_gm 0x0F /* Virtual Port 0 Mapping group mask. */ -#define PORTCFG_VP0MAP_gp 0 /* Virtual Port 0 Mapping group position. */ -#define PORTCFG_VP0MAP0_bm (1<<0) /* Virtual Port 0 Mapping bit 0 mask. */ -#define PORTCFG_VP0MAP0_bp 0 /* Virtual Port 0 Mapping bit 0 position. */ -#define PORTCFG_VP0MAP1_bm (1<<1) /* Virtual Port 0 Mapping bit 1 mask. */ -#define PORTCFG_VP0MAP1_bp 1 /* Virtual Port 0 Mapping bit 1 position. */ -#define PORTCFG_VP0MAP2_bm (1<<2) /* Virtual Port 0 Mapping bit 2 mask. */ -#define PORTCFG_VP0MAP2_bp 2 /* Virtual Port 0 Mapping bit 2 position. */ -#define PORTCFG_VP0MAP3_bm (1<<3) /* Virtual Port 0 Mapping bit 3 mask. */ -#define PORTCFG_VP0MAP3_bp 3 /* Virtual Port 0 Mapping bit 3 position. */ - -/* PORTCFG.VPCTRLB bit masks and bit positions */ -#define PORTCFG_VP3MAP_gm 0xF0 /* Virtual Port 3 Mapping group mask. */ -#define PORTCFG_VP3MAP_gp 4 /* Virtual Port 3 Mapping group position. */ -#define PORTCFG_VP3MAP0_bm (1<<4) /* Virtual Port 3 Mapping bit 0 mask. */ -#define PORTCFG_VP3MAP0_bp 4 /* Virtual Port 3 Mapping bit 0 position. */ -#define PORTCFG_VP3MAP1_bm (1<<5) /* Virtual Port 3 Mapping bit 1 mask. */ -#define PORTCFG_VP3MAP1_bp 5 /* Virtual Port 3 Mapping bit 1 position. */ -#define PORTCFG_VP3MAP2_bm (1<<6) /* Virtual Port 3 Mapping bit 2 mask. */ -#define PORTCFG_VP3MAP2_bp 6 /* Virtual Port 3 Mapping bit 2 position. */ -#define PORTCFG_VP3MAP3_bm (1<<7) /* Virtual Port 3 Mapping bit 3 mask. */ -#define PORTCFG_VP3MAP3_bp 7 /* Virtual Port 3 Mapping bit 3 position. */ - -#define PORTCFG_VP2MAP_gm 0x0F /* Virtual Port 2 Mapping group mask. */ -#define PORTCFG_VP2MAP_gp 0 /* Virtual Port 2 Mapping group position. */ -#define PORTCFG_VP2MAP0_bm (1<<0) /* Virtual Port 2 Mapping bit 0 mask. */ -#define PORTCFG_VP2MAP0_bp 0 /* Virtual Port 2 Mapping bit 0 position. */ -#define PORTCFG_VP2MAP1_bm (1<<1) /* Virtual Port 2 Mapping bit 1 mask. */ -#define PORTCFG_VP2MAP1_bp 1 /* Virtual Port 2 Mapping bit 1 position. */ -#define PORTCFG_VP2MAP2_bm (1<<2) /* Virtual Port 2 Mapping bit 2 mask. */ -#define PORTCFG_VP2MAP2_bp 2 /* Virtual Port 2 Mapping bit 2 position. */ -#define PORTCFG_VP2MAP3_bm (1<<3) /* Virtual Port 2 Mapping bit 3 mask. */ -#define PORTCFG_VP2MAP3_bp 3 /* Virtual Port 2 Mapping bit 3 position. */ - -/* PORTCFG.CLKEVOUT bit masks and bit positions */ -#define PORTCFG_CLKOUT_gm 0x03 /* Peripheral Clock Output Port group mask. */ -#define PORTCFG_CLKOUT_gp 0 /* Peripheral Clock Output Port group position. */ -#define PORTCFG_CLKOUT0_bm (1<<0) /* Peripheral Clock Output Port bit 0 mask. */ -#define PORTCFG_CLKOUT0_bp 0 /* Peripheral Clock Output Port bit 0 position. */ -#define PORTCFG_CLKOUT1_bm (1<<1) /* Peripheral Clock Output Port bit 1 mask. */ -#define PORTCFG_CLKOUT1_bp 1 /* Peripheral Clock Output Port bit 1 position. */ - -#define PORTCFG_CLKOUTSEL_gm 0x0C /* Peripheral Clock Output Select group mask. */ -#define PORTCFG_CLKOUTSEL_gp 2 /* Peripheral Clock Output Select group position. */ -#define PORTCFG_CLKOUTSEL0_bm (1<<2) /* Peripheral Clock Output Select bit 0 mask. */ -#define PORTCFG_CLKOUTSEL0_bp 2 /* Peripheral Clock Output Select bit 0 position. */ -#define PORTCFG_CLKOUTSEL1_bm (1<<3) /* Peripheral Clock Output Select bit 1 mask. */ -#define PORTCFG_CLKOUTSEL1_bp 3 /* Peripheral Clock Output Select bit 1 position. */ - -#define PORTCFG_EVOUT_gm 0x30 /* Event Output Port group mask. */ -#define PORTCFG_EVOUT_gp 4 /* Event Output Port group position. */ -#define PORTCFG_EVOUT0_bm (1<<4) /* Event Output Port bit 0 mask. */ -#define PORTCFG_EVOUT0_bp 4 /* Event Output Port bit 0 position. */ -#define PORTCFG_EVOUT1_bm (1<<5) /* Event Output Port bit 1 mask. */ -#define PORTCFG_EVOUT1_bp 5 /* Event Output Port bit 1 position. */ - -#define PORTCFG_RTCOUT_bm 0x40 /* RTC Clock Output bit mask. */ -#define PORTCFG_RTCOUT_bp 6 /* RTC Clock Output bit position. */ - -#define PORTCFG_CLKEVPIN_bm 0x80 /* Peripheral Clock and Event Output pin Select bit mask. */ -#define PORTCFG_CLKEVPIN_bp 7 /* Peripheral Clock and Event Output pin Select bit position. */ - -/* PORTCFG.EVOUTSEL bit masks and bit positions */ -#define PORTCFG_EVOUTSEL_gm 0x07 /* Event Output Select group mask. */ -#define PORTCFG_EVOUTSEL_gp 0 /* Event Output Select group position. */ -#define PORTCFG_EVOUTSEL0_bm (1<<0) /* Event Output Select bit 0 mask. */ -#define PORTCFG_EVOUTSEL0_bp 0 /* Event Output Select bit 0 position. */ -#define PORTCFG_EVOUTSEL1_bm (1<<1) /* Event Output Select bit 1 mask. */ -#define PORTCFG_EVOUTSEL1_bp 1 /* Event Output Select bit 1 position. */ -#define PORTCFG_EVOUTSEL2_bm (1<<2) /* Event Output Select bit 2 mask. */ -#define PORTCFG_EVOUTSEL2_bp 2 /* Event Output Select bit 2 position. */ - -/* CRC - Cyclic Redundancy Checker */ -/* CRC.CTRL bit masks and bit positions */ -#define CRC_RESET_gm 0xC0 /* Reset group mask. */ -#define CRC_RESET_gp 6 /* Reset group position. */ -#define CRC_RESET0_bm (1<<6) /* Reset bit 0 mask. */ -#define CRC_RESET0_bp 6 /* Reset bit 0 position. */ -#define CRC_RESET1_bm (1<<7) /* Reset bit 1 mask. */ -#define CRC_RESET1_bp 7 /* Reset bit 1 position. */ - -#define CRC_CRC32_bm 0x20 /* CRC Mode bit mask. */ -#define CRC_CRC32_bp 5 /* CRC Mode bit position. */ - -#define CRC_SOURCE_gm 0x0F /* Input Source group mask. */ -#define CRC_SOURCE_gp 0 /* Input Source group position. */ -#define CRC_SOURCE0_bm (1<<0) /* Input Source bit 0 mask. */ -#define CRC_SOURCE0_bp 0 /* Input Source bit 0 position. */ -#define CRC_SOURCE1_bm (1<<1) /* Input Source bit 1 mask. */ -#define CRC_SOURCE1_bp 1 /* Input Source bit 1 position. */ -#define CRC_SOURCE2_bm (1<<2) /* Input Source bit 2 mask. */ -#define CRC_SOURCE2_bp 2 /* Input Source bit 2 position. */ -#define CRC_SOURCE3_bm (1<<3) /* Input Source bit 3 mask. */ -#define CRC_SOURCE3_bp 3 /* Input Source bit 3 position. */ - -/* CRC.STATUS bit masks and bit positions */ -#define CRC_ZERO_bm 0x02 /* Zero detection bit mask. */ -#define CRC_ZERO_bp 1 /* Zero detection bit position. */ - -#define CRC_BUSY_bm 0x01 /* Busy bit mask. */ -#define CRC_BUSY_bp 0 /* Busy bit position. */ - -/* EVSYS - Event System */ -/* EVSYS.CH0MUX bit masks and bit positions */ -#define EVSYS_CHMUX_gm 0xFF /* Event Channel 0 Multiplexer group mask. */ -#define EVSYS_CHMUX_gp 0 /* Event Channel 0 Multiplexer group position. */ -#define EVSYS_CHMUX0_bm (1<<0) /* Event Channel 0 Multiplexer bit 0 mask. */ -#define EVSYS_CHMUX0_bp 0 /* Event Channel 0 Multiplexer bit 0 position. */ -#define EVSYS_CHMUX1_bm (1<<1) /* Event Channel 0 Multiplexer bit 1 mask. */ -#define EVSYS_CHMUX1_bp 1 /* Event Channel 0 Multiplexer bit 1 position. */ -#define EVSYS_CHMUX2_bm (1<<2) /* Event Channel 0 Multiplexer bit 2 mask. */ -#define EVSYS_CHMUX2_bp 2 /* Event Channel 0 Multiplexer bit 2 position. */ -#define EVSYS_CHMUX3_bm (1<<3) /* Event Channel 0 Multiplexer bit 3 mask. */ -#define EVSYS_CHMUX3_bp 3 /* Event Channel 0 Multiplexer bit 3 position. */ -#define EVSYS_CHMUX4_bm (1<<4) /* Event Channel 0 Multiplexer bit 4 mask. */ -#define EVSYS_CHMUX4_bp 4 /* Event Channel 0 Multiplexer bit 4 position. */ -#define EVSYS_CHMUX5_bm (1<<5) /* Event Channel 0 Multiplexer bit 5 mask. */ -#define EVSYS_CHMUX5_bp 5 /* Event Channel 0 Multiplexer bit 5 position. */ -#define EVSYS_CHMUX6_bm (1<<6) /* Event Channel 0 Multiplexer bit 6 mask. */ -#define EVSYS_CHMUX6_bp 6 /* Event Channel 0 Multiplexer bit 6 position. */ -#define EVSYS_CHMUX7_bm (1<<7) /* Event Channel 0 Multiplexer bit 7 mask. */ -#define EVSYS_CHMUX7_bp 7 /* Event Channel 0 Multiplexer bit 7 position. */ - -/* EVSYS.CH1MUX bit masks and bit positions */ -/* EVSYS_CHMUX Predefined. */ -/* EVSYS_CHMUX Predefined. */ - -/* EVSYS.CH2MUX bit masks and bit positions */ -/* EVSYS_CHMUX Predefined. */ -/* EVSYS_CHMUX Predefined. */ - -/* EVSYS.CH3MUX bit masks and bit positions */ -/* EVSYS_CHMUX Predefined. */ -/* EVSYS_CHMUX Predefined. */ - -/* EVSYS.CH0CTRL bit masks and bit positions */ -#define EVSYS_QDIRM_gm 0x60 /* Quadrature Decoder Index Recognition Mode group mask. */ -#define EVSYS_QDIRM_gp 5 /* Quadrature Decoder Index Recognition Mode group position. */ -#define EVSYS_QDIRM0_bm (1<<5) /* Quadrature Decoder Index Recognition Mode bit 0 mask. */ -#define EVSYS_QDIRM0_bp 5 /* Quadrature Decoder Index Recognition Mode bit 0 position. */ -#define EVSYS_QDIRM1_bm (1<<6) /* Quadrature Decoder Index Recognition Mode bit 1 mask. */ -#define EVSYS_QDIRM1_bp 6 /* Quadrature Decoder Index Recognition Mode bit 1 position. */ - -#define EVSYS_QDIEN_bm 0x10 /* Quadrature Decoder Index Enable bit mask. */ -#define EVSYS_QDIEN_bp 4 /* Quadrature Decoder Index Enable bit position. */ - -#define EVSYS_QDEN_bm 0x08 /* Quadrature Decoder Enable bit mask. */ -#define EVSYS_QDEN_bp 3 /* Quadrature Decoder Enable bit position. */ - -#define EVSYS_DIGFILT_gm 0x07 /* Digital Filter group mask. */ -#define EVSYS_DIGFILT_gp 0 /* Digital Filter group position. */ -#define EVSYS_DIGFILT0_bm (1<<0) /* Digital Filter bit 0 mask. */ -#define EVSYS_DIGFILT0_bp 0 /* Digital Filter bit 0 position. */ -#define EVSYS_DIGFILT1_bm (1<<1) /* Digital Filter bit 1 mask. */ -#define EVSYS_DIGFILT1_bp 1 /* Digital Filter bit 1 position. */ -#define EVSYS_DIGFILT2_bm (1<<2) /* Digital Filter bit 2 mask. */ -#define EVSYS_DIGFILT2_bp 2 /* Digital Filter bit 2 position. */ - -/* EVSYS.CH1CTRL bit masks and bit positions */ -/* EVSYS_DIGFILT Predefined. */ -/* EVSYS_DIGFILT Predefined. */ - -/* EVSYS.CH2CTRL bit masks and bit positions */ -/* EVSYS_DIGFILT Predefined. */ -/* EVSYS_DIGFILT Predefined. */ - -/* EVSYS.CH3CTRL bit masks and bit positions */ -/* EVSYS_DIGFILT Predefined. */ -/* EVSYS_DIGFILT Predefined. */ - -/* NVM - Non Volatile Memory Controller */ -/* NVM.CMD bit masks and bit positions */ -#define NVM_CMD_gm 0x7F /* Command group mask. */ -#define NVM_CMD_gp 0 /* Command group position. */ -#define NVM_CMD0_bm (1<<0) /* Command bit 0 mask. */ -#define NVM_CMD0_bp 0 /* Command bit 0 position. */ -#define NVM_CMD1_bm (1<<1) /* Command bit 1 mask. */ -#define NVM_CMD1_bp 1 /* Command bit 1 position. */ -#define NVM_CMD2_bm (1<<2) /* Command bit 2 mask. */ -#define NVM_CMD2_bp 2 /* Command bit 2 position. */ -#define NVM_CMD3_bm (1<<3) /* Command bit 3 mask. */ -#define NVM_CMD3_bp 3 /* Command bit 3 position. */ -#define NVM_CMD4_bm (1<<4) /* Command bit 4 mask. */ -#define NVM_CMD4_bp 4 /* Command bit 4 position. */ -#define NVM_CMD5_bm (1<<5) /* Command bit 5 mask. */ -#define NVM_CMD5_bp 5 /* Command bit 5 position. */ -#define NVM_CMD6_bm (1<<6) /* Command bit 6 mask. */ -#define NVM_CMD6_bp 6 /* Command bit 6 position. */ - -/* NVM.CTRLA bit masks and bit positions */ -#define NVM_CMDEX_bm 0x01 /* Command Execute bit mask. */ -#define NVM_CMDEX_bp 0 /* Command Execute bit position. */ - -/* NVM.CTRLB bit masks and bit positions */ -#define NVM_EEMAPEN_bm 0x08 /* EEPROM Mapping Enable bit mask. */ -#define NVM_EEMAPEN_bp 3 /* EEPROM Mapping Enable bit position. */ - -#define NVM_FPRM_bm 0x04 /* Flash Power Reduction Enable bit mask. */ -#define NVM_FPRM_bp 2 /* Flash Power Reduction Enable bit position. */ - -#define NVM_EPRM_bm 0x02 /* EEPROM Power Reduction Enable bit mask. */ -#define NVM_EPRM_bp 1 /* EEPROM Power Reduction Enable bit position. */ - -#define NVM_SPMLOCK_bm 0x01 /* SPM Lock bit mask. */ -#define NVM_SPMLOCK_bp 0 /* SPM Lock bit position. */ - -/* NVM.INTCTRL bit masks and bit positions */ -#define NVM_SPMLVL_gm 0x0C /* SPM Interrupt Level group mask. */ -#define NVM_SPMLVL_gp 2 /* SPM Interrupt Level group position. */ -#define NVM_SPMLVL0_bm (1<<2) /* SPM Interrupt Level bit 0 mask. */ -#define NVM_SPMLVL0_bp 2 /* SPM Interrupt Level bit 0 position. */ -#define NVM_SPMLVL1_bm (1<<3) /* SPM Interrupt Level bit 1 mask. */ -#define NVM_SPMLVL1_bp 3 /* SPM Interrupt Level bit 1 position. */ - -#define NVM_EELVL_gm 0x03 /* EEPROM Interrupt Level group mask. */ -#define NVM_EELVL_gp 0 /* EEPROM Interrupt Level group position. */ -#define NVM_EELVL0_bm (1<<0) /* EEPROM Interrupt Level bit 0 mask. */ -#define NVM_EELVL0_bp 0 /* EEPROM Interrupt Level bit 0 position. */ -#define NVM_EELVL1_bm (1<<1) /* EEPROM Interrupt Level bit 1 mask. */ -#define NVM_EELVL1_bp 1 /* EEPROM Interrupt Level bit 1 position. */ - -/* NVM.STATUS bit masks and bit positions */ -#define NVM_NVMBUSY_bm 0x80 /* Non-volatile Memory Busy bit mask. */ -#define NVM_NVMBUSY_bp 7 /* Non-volatile Memory Busy bit position. */ - -#define NVM_FBUSY_bm 0x40 /* Flash Memory Busy bit mask. */ -#define NVM_FBUSY_bp 6 /* Flash Memory Busy bit position. */ - -#define NVM_EELOAD_bm 0x02 /* EEPROM Page Buffer Active Loading bit mask. */ -#define NVM_EELOAD_bp 1 /* EEPROM Page Buffer Active Loading bit position. */ - -#define NVM_FLOAD_bm 0x01 /* Flash Page Buffer Active Loading bit mask. */ -#define NVM_FLOAD_bp 0 /* Flash Page Buffer Active Loading bit position. */ - -/* NVM.LOCKBITS bit masks and bit positions */ -#define NVM_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ -#define NVM_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ -#define NVM_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ -#define NVM_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ -#define NVM_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ -#define NVM_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ - -#define NVM_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ -#define NVM_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ -#define NVM_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ -#define NVM_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ -#define NVM_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ -#define NVM_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ - -#define NVM_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ -#define NVM_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ -#define NVM_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ -#define NVM_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ -#define NVM_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ -#define NVM_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ - -#define NVM_LB_gm 0x03 /* Lock Bits group mask. */ -#define NVM_LB_gp 0 /* Lock Bits group position. */ -#define NVM_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ -#define NVM_LB0_bp 0 /* Lock Bits bit 0 position. */ -#define NVM_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ -#define NVM_LB1_bp 1 /* Lock Bits bit 1 position. */ - -/* ADC - Analog/Digital Converter */ -/* ADC_CH.CTRL bit masks and bit positions */ -#define ADC_CH_START_bm 0x80 /* Channel Start Conversion bit mask. */ -#define ADC_CH_START_bp 7 /* Channel Start Conversion bit position. */ - -#define ADC_CH_GAIN_gm 0x1C /* Gain Factor group mask. */ -#define ADC_CH_GAIN_gp 2 /* Gain Factor group position. */ -#define ADC_CH_GAIN0_bm (1<<2) /* Gain Factor bit 0 mask. */ -#define ADC_CH_GAIN0_bp 2 /* Gain Factor bit 0 position. */ -#define ADC_CH_GAIN1_bm (1<<3) /* Gain Factor bit 1 mask. */ -#define ADC_CH_GAIN1_bp 3 /* Gain Factor bit 1 position. */ -#define ADC_CH_GAIN2_bm (1<<4) /* Gain Factor bit 2 mask. */ -#define ADC_CH_GAIN2_bp 4 /* Gain Factor bit 2 position. */ - -#define ADC_CH_INPUTMODE_gm 0x03 /* Input Mode Select group mask. */ -#define ADC_CH_INPUTMODE_gp 0 /* Input Mode Select group position. */ -#define ADC_CH_INPUTMODE0_bm (1<<0) /* Input Mode Select bit 0 mask. */ -#define ADC_CH_INPUTMODE0_bp 0 /* Input Mode Select bit 0 position. */ -#define ADC_CH_INPUTMODE1_bm (1<<1) /* Input Mode Select bit 1 mask. */ -#define ADC_CH_INPUTMODE1_bp 1 /* Input Mode Select bit 1 position. */ - -/* ADC_CH.MUXCTRL bit masks and bit positions */ -#define ADC_CH_MUXPOS_gm 0x78 /* MUX selection on Positive ADC input group mask. */ -#define ADC_CH_MUXPOS_gp 3 /* MUX selection on Positive ADC input group position. */ -#define ADC_CH_MUXPOS0_bm (1<<3) /* MUX selection on Positive ADC input bit 0 mask. */ -#define ADC_CH_MUXPOS0_bp 3 /* MUX selection on Positive ADC input bit 0 position. */ -#define ADC_CH_MUXPOS1_bm (1<<4) /* MUX selection on Positive ADC input bit 1 mask. */ -#define ADC_CH_MUXPOS1_bp 4 /* MUX selection on Positive ADC input bit 1 position. */ -#define ADC_CH_MUXPOS2_bm (1<<5) /* MUX selection on Positive ADC input bit 2 mask. */ -#define ADC_CH_MUXPOS2_bp 5 /* MUX selection on Positive ADC input bit 2 position. */ -#define ADC_CH_MUXPOS3_bm (1<<6) /* MUX selection on Positive ADC input bit 3 mask. */ -#define ADC_CH_MUXPOS3_bp 6 /* MUX selection on Positive ADC input bit 3 position. */ - -#define ADC_CH_MUXINT_gm 0x78 /* MUX selection on Internal ADC input group mask. */ -#define ADC_CH_MUXINT_gp 3 /* MUX selection on Internal ADC input group position. */ -#define ADC_CH_MUXINT0_bm (1<<3) /* MUX selection on Internal ADC input bit 0 mask. */ -#define ADC_CH_MUXINT0_bp 3 /* MUX selection on Internal ADC input bit 0 position. */ -#define ADC_CH_MUXINT1_bm (1<<4) /* MUX selection on Internal ADC input bit 1 mask. */ -#define ADC_CH_MUXINT1_bp 4 /* MUX selection on Internal ADC input bit 1 position. */ -#define ADC_CH_MUXINT2_bm (1<<5) /* MUX selection on Internal ADC input bit 2 mask. */ -#define ADC_CH_MUXINT2_bp 5 /* MUX selection on Internal ADC input bit 2 position. */ -#define ADC_CH_MUXINT3_bm (1<<6) /* MUX selection on Internal ADC input bit 3 mask. */ -#define ADC_CH_MUXINT3_bp 6 /* MUX selection on Internal ADC input bit 3 position. */ - -#define ADC_CH_MUXNEG_gm 0x03 /* MUX selection on Negative ADC input group mask. */ -#define ADC_CH_MUXNEG_gp 0 /* MUX selection on Negative ADC input group position. */ -#define ADC_CH_MUXNEG0_bm (1<<0) /* MUX selection on Negative ADC input bit 0 mask. */ -#define ADC_CH_MUXNEG0_bp 0 /* MUX selection on Negative ADC input bit 0 position. */ -#define ADC_CH_MUXNEG1_bm (1<<1) /* MUX selection on Negative ADC input bit 1 mask. */ -#define ADC_CH_MUXNEG1_bp 1 /* MUX selection on Negative ADC input bit 1 position. */ - -/* ADC_CH.INTCTRL bit masks and bit positions */ -#define ADC_CH_INTMODE_gm 0x0C /* Interrupt Mode group mask. */ -#define ADC_CH_INTMODE_gp 2 /* Interrupt Mode group position. */ -#define ADC_CH_INTMODE0_bm (1<<2) /* Interrupt Mode bit 0 mask. */ -#define ADC_CH_INTMODE0_bp 2 /* Interrupt Mode bit 0 position. */ -#define ADC_CH_INTMODE1_bm (1<<3) /* Interrupt Mode bit 1 mask. */ -#define ADC_CH_INTMODE1_bp 3 /* Interrupt Mode bit 1 position. */ - -#define ADC_CH_INTLVL_gm 0x03 /* Interrupt Level group mask. */ -#define ADC_CH_INTLVL_gp 0 /* Interrupt Level group position. */ -#define ADC_CH_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */ -#define ADC_CH_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */ -#define ADC_CH_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ -#define ADC_CH_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */ - -/* ADC_CH.INTFLAGS bit masks and bit positions */ -#define ADC_CH_CHIF_bm 0x01 /* Channel Interrupt Flag bit mask. */ -#define ADC_CH_CHIF_bp 0 /* Channel Interrupt Flag bit position. */ - -/* ADC_CH.SCAN bit masks and bit positions */ -#define ADC_CH_OFFSET_gm 0xF0 /* Positive MUX setting offset group mask. */ -#define ADC_CH_OFFSET_gp 4 /* Positive MUX setting offset group position. */ -#define ADC_CH_OFFSET0_bm (1<<4) /* Positive MUX setting offset bit 0 mask. */ -#define ADC_CH_OFFSET0_bp 4 /* Positive MUX setting offset bit 0 position. */ -#define ADC_CH_OFFSET1_bm (1<<5) /* Positive MUX setting offset bit 1 mask. */ -#define ADC_CH_OFFSET1_bp 5 /* Positive MUX setting offset bit 1 position. */ -#define ADC_CH_OFFSET2_bm (1<<6) /* Positive MUX setting offset bit 2 mask. */ -#define ADC_CH_OFFSET2_bp 6 /* Positive MUX setting offset bit 2 position. */ -#define ADC_CH_OFFSET3_bm (1<<7) /* Positive MUX setting offset bit 3 mask. */ -#define ADC_CH_OFFSET3_bp 7 /* Positive MUX setting offset bit 3 position. */ - -#define ADC_CH_SCANNUM_gm 0x0F /* Number of Channels included in scan group mask. */ -#define ADC_CH_SCANNUM_gp 0 /* Number of Channels included in scan group position. */ -#define ADC_CH_SCANNUM0_bm (1<<0) /* Number of Channels included in scan bit 0 mask. */ -#define ADC_CH_SCANNUM0_bp 0 /* Number of Channels included in scan bit 0 position. */ -#define ADC_CH_SCANNUM1_bm (1<<1) /* Number of Channels included in scan bit 1 mask. */ -#define ADC_CH_SCANNUM1_bp 1 /* Number of Channels included in scan bit 1 position. */ -#define ADC_CH_SCANNUM2_bm (1<<2) /* Number of Channels included in scan bit 2 mask. */ -#define ADC_CH_SCANNUM2_bp 2 /* Number of Channels included in scan bit 2 position. */ -#define ADC_CH_SCANNUM3_bm (1<<3) /* Number of Channels included in scan bit 3 mask. */ -#define ADC_CH_SCANNUM3_bp 3 /* Number of Channels included in scan bit 3 position. */ - -/* ADC.CTRLA bit masks and bit positions */ -#define ADC_CH0START_bm 0x04 /* Channel 0 Start Conversion bit mask. */ -#define ADC_CH0START_bp 2 /* Channel 0 Start Conversion bit position. */ - -#define ADC_FLUSH_bm 0x02 /* ADC Flush bit mask. */ -#define ADC_FLUSH_bp 1 /* ADC Flush bit position. */ - -#define ADC_ENABLE_bm 0x01 /* Enable ADC bit mask. */ -#define ADC_ENABLE_bp 0 /* Enable ADC bit position. */ - -/* ADC.CTRLB bit masks and bit positions */ -#define ADC_CURRLIMIT_gm 0x60 /* Current Limitation group mask. */ -#define ADC_CURRLIMIT_gp 5 /* Current Limitation group position. */ -#define ADC_CURRLIMIT0_bm (1<<5) /* Current Limitation bit 0 mask. */ -#define ADC_CURRLIMIT0_bp 5 /* Current Limitation bit 0 position. */ -#define ADC_CURRLIMIT1_bm (1<<6) /* Current Limitation bit 1 mask. */ -#define ADC_CURRLIMIT1_bp 6 /* Current Limitation bit 1 position. */ - -#define ADC_CONMODE_bm 0x10 /* Conversion Mode bit mask. */ -#define ADC_CONMODE_bp 4 /* Conversion Mode bit position. */ - -#define ADC_FREERUN_bm 0x08 /* Free Running Mode Enable bit mask. */ -#define ADC_FREERUN_bp 3 /* Free Running Mode Enable bit position. */ - -#define ADC_RESOLUTION_gm 0x06 /* Result Resolution group mask. */ -#define ADC_RESOLUTION_gp 1 /* Result Resolution group position. */ -#define ADC_RESOLUTION0_bm (1<<1) /* Result Resolution bit 0 mask. */ -#define ADC_RESOLUTION0_bp 1 /* Result Resolution bit 0 position. */ -#define ADC_RESOLUTION1_bm (1<<2) /* Result Resolution bit 1 mask. */ -#define ADC_RESOLUTION1_bp 2 /* Result Resolution bit 1 position. */ - -/* ADC.REFCTRL bit masks and bit positions */ -#define ADC_REFSEL_gm 0x70 /* Reference Selection group mask. */ -#define ADC_REFSEL_gp 4 /* Reference Selection group position. */ -#define ADC_REFSEL0_bm (1<<4) /* Reference Selection bit 0 mask. */ -#define ADC_REFSEL0_bp 4 /* Reference Selection bit 0 position. */ -#define ADC_REFSEL1_bm (1<<5) /* Reference Selection bit 1 mask. */ -#define ADC_REFSEL1_bp 5 /* Reference Selection bit 1 position. */ -#define ADC_REFSEL2_bm (1<<6) /* Reference Selection bit 2 mask. */ -#define ADC_REFSEL2_bp 6 /* Reference Selection bit 2 position. */ - -#define ADC_BANDGAP_bm 0x02 /* Bandgap enable bit mask. */ -#define ADC_BANDGAP_bp 1 /* Bandgap enable bit position. */ - -#define ADC_TEMPREF_bm 0x01 /* Temperature Reference Enable bit mask. */ -#define ADC_TEMPREF_bp 0 /* Temperature Reference Enable bit position. */ - -/* ADC.EVCTRL bit masks and bit positions */ -#define ADC_EVSEL_gm 0x18 /* Event Input Select group mask. */ -#define ADC_EVSEL_gp 3 /* Event Input Select group position. */ -#define ADC_EVSEL0_bm (1<<3) /* Event Input Select bit 0 mask. */ -#define ADC_EVSEL0_bp 3 /* Event Input Select bit 0 position. */ -#define ADC_EVSEL1_bm (1<<4) /* Event Input Select bit 1 mask. */ -#define ADC_EVSEL1_bp 4 /* Event Input Select bit 1 position. */ - -#define ADC_EVACT_gm 0x07 /* Event Action Select group mask. */ -#define ADC_EVACT_gp 0 /* Event Action Select group position. */ -#define ADC_EVACT0_bm (1<<0) /* Event Action Select bit 0 mask. */ -#define ADC_EVACT0_bp 0 /* Event Action Select bit 0 position. */ -#define ADC_EVACT1_bm (1<<1) /* Event Action Select bit 1 mask. */ -#define ADC_EVACT1_bp 1 /* Event Action Select bit 1 position. */ -#define ADC_EVACT2_bm (1<<2) /* Event Action Select bit 2 mask. */ -#define ADC_EVACT2_bp 2 /* Event Action Select bit 2 position. */ - -/* ADC.PRESCALER bit masks and bit positions */ -#define ADC_PRESCALER_gm 0x07 /* Clock Prescaler Selection group mask. */ -#define ADC_PRESCALER_gp 0 /* Clock Prescaler Selection group position. */ -#define ADC_PRESCALER0_bm (1<<0) /* Clock Prescaler Selection bit 0 mask. */ -#define ADC_PRESCALER0_bp 0 /* Clock Prescaler Selection bit 0 position. */ -#define ADC_PRESCALER1_bm (1<<1) /* Clock Prescaler Selection bit 1 mask. */ -#define ADC_PRESCALER1_bp 1 /* Clock Prescaler Selection bit 1 position. */ -#define ADC_PRESCALER2_bm (1<<2) /* Clock Prescaler Selection bit 2 mask. */ -#define ADC_PRESCALER2_bp 2 /* Clock Prescaler Selection bit 2 position. */ - -/* ADC.INTFLAGS bit masks and bit positions */ -#define ADC_CH0IF_bm 0x01 /* Channel 0 Interrupt Flag bit mask. */ -#define ADC_CH0IF_bp 0 /* Channel 0 Interrupt Flag bit position. */ - -/* AC - Analog Comparator */ -/* AC.AC0CTRL bit masks and bit positions */ -#define AC_INTMODE_gm 0xC0 /* Interrupt Mode group mask. */ -#define AC_INTMODE_gp 6 /* Interrupt Mode group position. */ -#define AC_INTMODE0_bm (1<<6) /* Interrupt Mode bit 0 mask. */ -#define AC_INTMODE0_bp 6 /* Interrupt Mode bit 0 position. */ -#define AC_INTMODE1_bm (1<<7) /* Interrupt Mode bit 1 mask. */ -#define AC_INTMODE1_bp 7 /* Interrupt Mode bit 1 position. */ - -#define AC_INTLVL_gm 0x30 /* Interrupt Level group mask. */ -#define AC_INTLVL_gp 4 /* Interrupt Level group position. */ -#define AC_INTLVL0_bm (1<<4) /* Interrupt Level bit 0 mask. */ -#define AC_INTLVL0_bp 4 /* Interrupt Level bit 0 position. */ -#define AC_INTLVL1_bm (1<<5) /* Interrupt Level bit 1 mask. */ -#define AC_INTLVL1_bp 5 /* Interrupt Level bit 1 position. */ - -#define AC_HYSMODE_gm 0x06 /* Hysteresis Mode group mask. */ -#define AC_HYSMODE_gp 1 /* Hysteresis Mode group position. */ -#define AC_HYSMODE0_bm (1<<1) /* Hysteresis Mode bit 0 mask. */ -#define AC_HYSMODE0_bp 1 /* Hysteresis Mode bit 0 position. */ -#define AC_HYSMODE1_bm (1<<2) /* Hysteresis Mode bit 1 mask. */ -#define AC_HYSMODE1_bp 2 /* Hysteresis Mode bit 1 position. */ - -#define AC_ENABLE_bm 0x01 /* Enable bit mask. */ -#define AC_ENABLE_bp 0 /* Enable bit position. */ - -/* AC.AC1CTRL bit masks and bit positions */ -/* AC_INTMODE Predefined. */ -/* AC_INTMODE Predefined. */ - -/* AC_INTLVL Predefined. */ -/* AC_INTLVL Predefined. */ - -/* AC_HYSMODE Predefined. */ -/* AC_HYSMODE Predefined. */ - -/* AC_ENABLE Predefined. */ -/* AC_ENABLE Predefined. */ - -/* AC.AC0MUXCTRL bit masks and bit positions */ -#define AC_MUXPOS_gm 0x38 /* MUX Positive Input group mask. */ -#define AC_MUXPOS_gp 3 /* MUX Positive Input group position. */ -#define AC_MUXPOS0_bm (1<<3) /* MUX Positive Input bit 0 mask. */ -#define AC_MUXPOS0_bp 3 /* MUX Positive Input bit 0 position. */ -#define AC_MUXPOS1_bm (1<<4) /* MUX Positive Input bit 1 mask. */ -#define AC_MUXPOS1_bp 4 /* MUX Positive Input bit 1 position. */ -#define AC_MUXPOS2_bm (1<<5) /* MUX Positive Input bit 2 mask. */ -#define AC_MUXPOS2_bp 5 /* MUX Positive Input bit 2 position. */ - -#define AC_MUXNEG_gm 0x07 /* MUX Negative Input group mask. */ -#define AC_MUXNEG_gp 0 /* MUX Negative Input group position. */ -#define AC_MUXNEG0_bm (1<<0) /* MUX Negative Input bit 0 mask. */ -#define AC_MUXNEG0_bp 0 /* MUX Negative Input bit 0 position. */ -#define AC_MUXNEG1_bm (1<<1) /* MUX Negative Input bit 1 mask. */ -#define AC_MUXNEG1_bp 1 /* MUX Negative Input bit 1 position. */ -#define AC_MUXNEG2_bm (1<<2) /* MUX Negative Input bit 2 mask. */ -#define AC_MUXNEG2_bp 2 /* MUX Negative Input bit 2 position. */ - -/* AC.AC1MUXCTRL bit masks and bit positions */ -/* AC_MUXPOS Predefined. */ -/* AC_MUXPOS Predefined. */ - -/* AC_MUXNEG Predefined. */ -/* AC_MUXNEG Predefined. */ - -/* AC.CTRLA bit masks and bit positions */ -#define AC_AC1OUT_bm 0x02 /* Analog Comparator 1 Output Enable bit mask. */ -#define AC_AC1OUT_bp 1 /* Analog Comparator 1 Output Enable bit position. */ - -#define AC_AC0OUT_bm 0x01 /* Analog Comparator 0 Output Enable bit mask. */ -#define AC_AC0OUT_bp 0 /* Analog Comparator 0 Output Enable bit position. */ - -/* AC.CTRLB bit masks and bit positions */ -#define AC_SCALEFAC_gm 0x3F /* VCC Voltage Scaler Factor group mask. */ -#define AC_SCALEFAC_gp 0 /* VCC Voltage Scaler Factor group position. */ -#define AC_SCALEFAC0_bm (1<<0) /* VCC Voltage Scaler Factor bit 0 mask. */ -#define AC_SCALEFAC0_bp 0 /* VCC Voltage Scaler Factor bit 0 position. */ -#define AC_SCALEFAC1_bm (1<<1) /* VCC Voltage Scaler Factor bit 1 mask. */ -#define AC_SCALEFAC1_bp 1 /* VCC Voltage Scaler Factor bit 1 position. */ -#define AC_SCALEFAC2_bm (1<<2) /* VCC Voltage Scaler Factor bit 2 mask. */ -#define AC_SCALEFAC2_bp 2 /* VCC Voltage Scaler Factor bit 2 position. */ -#define AC_SCALEFAC3_bm (1<<3) /* VCC Voltage Scaler Factor bit 3 mask. */ -#define AC_SCALEFAC3_bp 3 /* VCC Voltage Scaler Factor bit 3 position. */ -#define AC_SCALEFAC4_bm (1<<4) /* VCC Voltage Scaler Factor bit 4 mask. */ -#define AC_SCALEFAC4_bp 4 /* VCC Voltage Scaler Factor bit 4 position. */ -#define AC_SCALEFAC5_bm (1<<5) /* VCC Voltage Scaler Factor bit 5 mask. */ -#define AC_SCALEFAC5_bp 5 /* VCC Voltage Scaler Factor bit 5 position. */ - -/* AC.WINCTRL bit masks and bit positions */ -#define AC_WEN_bm 0x10 /* Window Mode Enable bit mask. */ -#define AC_WEN_bp 4 /* Window Mode Enable bit position. */ - -#define AC_WINTMODE_gm 0x0C /* Window Interrupt Mode group mask. */ -#define AC_WINTMODE_gp 2 /* Window Interrupt Mode group position. */ -#define AC_WINTMODE0_bm (1<<2) /* Window Interrupt Mode bit 0 mask. */ -#define AC_WINTMODE0_bp 2 /* Window Interrupt Mode bit 0 position. */ -#define AC_WINTMODE1_bm (1<<3) /* Window Interrupt Mode bit 1 mask. */ -#define AC_WINTMODE1_bp 3 /* Window Interrupt Mode bit 1 position. */ - -#define AC_WINTLVL_gm 0x03 /* Window Interrupt Level group mask. */ -#define AC_WINTLVL_gp 0 /* Window Interrupt Level group position. */ -#define AC_WINTLVL0_bm (1<<0) /* Window Interrupt Level bit 0 mask. */ -#define AC_WINTLVL0_bp 0 /* Window Interrupt Level bit 0 position. */ -#define AC_WINTLVL1_bm (1<<1) /* Window Interrupt Level bit 1 mask. */ -#define AC_WINTLVL1_bp 1 /* Window Interrupt Level bit 1 position. */ - -/* AC.STATUS bit masks and bit positions */ -#define AC_WSTATE_gm 0xC0 /* Window Mode State group mask. */ -#define AC_WSTATE_gp 6 /* Window Mode State group position. */ -#define AC_WSTATE0_bm (1<<6) /* Window Mode State bit 0 mask. */ -#define AC_WSTATE0_bp 6 /* Window Mode State bit 0 position. */ -#define AC_WSTATE1_bm (1<<7) /* Window Mode State bit 1 mask. */ -#define AC_WSTATE1_bp 7 /* Window Mode State bit 1 position. */ - -#define AC_AC1STATE_bm 0x20 /* Analog Comparator 1 State bit mask. */ -#define AC_AC1STATE_bp 5 /* Analog Comparator 1 State bit position. */ - -#define AC_AC0STATE_bm 0x10 /* Analog Comparator 0 State bit mask. */ -#define AC_AC0STATE_bp 4 /* Analog Comparator 0 State bit position. */ - -#define AC_WIF_bm 0x04 /* Window Mode Interrupt Flag bit mask. */ -#define AC_WIF_bp 2 /* Window Mode Interrupt Flag bit position. */ - -#define AC_AC1IF_bm 0x02 /* Analog Comparator 1 Interrupt Flag bit mask. */ -#define AC_AC1IF_bp 1 /* Analog Comparator 1 Interrupt Flag bit position. */ - -#define AC_AC0IF_bm 0x01 /* Analog Comparator 0 Interrupt Flag bit mask. */ -#define AC_AC0IF_bp 0 /* Analog Comparator 0 Interrupt Flag bit position. */ - -/* RTC - Real-Time Counter */ -/* RTC.CTRL bit masks and bit positions */ -#define RTC_PRESCALER_gm 0x07 /* Prescaling Factor group mask. */ -#define RTC_PRESCALER_gp 0 /* Prescaling Factor group position. */ -#define RTC_PRESCALER0_bm (1<<0) /* Prescaling Factor bit 0 mask. */ -#define RTC_PRESCALER0_bp 0 /* Prescaling Factor bit 0 position. */ -#define RTC_PRESCALER1_bm (1<<1) /* Prescaling Factor bit 1 mask. */ -#define RTC_PRESCALER1_bp 1 /* Prescaling Factor bit 1 position. */ -#define RTC_PRESCALER2_bm (1<<2) /* Prescaling Factor bit 2 mask. */ -#define RTC_PRESCALER2_bp 2 /* Prescaling Factor bit 2 position. */ - -/* RTC.STATUS bit masks and bit positions */ -#define RTC_SYNCBUSY_bm 0x01 /* Synchronization Busy Flag bit mask. */ -#define RTC_SYNCBUSY_bp 0 /* Synchronization Busy Flag bit position. */ - -/* RTC.INTCTRL bit masks and bit positions */ -#define RTC_COMPINTLVL_gm 0x0C /* Compare Match Interrupt Level group mask. */ -#define RTC_COMPINTLVL_gp 2 /* Compare Match Interrupt Level group position. */ -#define RTC_COMPINTLVL0_bm (1<<2) /* Compare Match Interrupt Level bit 0 mask. */ -#define RTC_COMPINTLVL0_bp 2 /* Compare Match Interrupt Level bit 0 position. */ -#define RTC_COMPINTLVL1_bm (1<<3) /* Compare Match Interrupt Level bit 1 mask. */ -#define RTC_COMPINTLVL1_bp 3 /* Compare Match Interrupt Level bit 1 position. */ - -#define RTC_OVFINTLVL_gm 0x03 /* Overflow Interrupt Level group mask. */ -#define RTC_OVFINTLVL_gp 0 /* Overflow Interrupt Level group position. */ -#define RTC_OVFINTLVL0_bm (1<<0) /* Overflow Interrupt Level bit 0 mask. */ -#define RTC_OVFINTLVL0_bp 0 /* Overflow Interrupt Level bit 0 position. */ -#define RTC_OVFINTLVL1_bm (1<<1) /* Overflow Interrupt Level bit 1 mask. */ -#define RTC_OVFINTLVL1_bp 1 /* Overflow Interrupt Level bit 1 position. */ - -/* RTC.INTFLAGS bit masks and bit positions */ -#define RTC_COMPIF_bm 0x02 /* Compare Match Interrupt Flag bit mask. */ -#define RTC_COMPIF_bp 1 /* Compare Match Interrupt Flag bit position. */ - -#define RTC_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ -#define RTC_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ - -/* TWI - Two-Wire Interface */ -/* TWI_MASTER.CTRLA bit masks and bit positions */ -#define TWI_MASTER_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ -#define TWI_MASTER_INTLVL_gp 6 /* Interrupt Level group position. */ -#define TWI_MASTER_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ -#define TWI_MASTER_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ -#define TWI_MASTER_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ -#define TWI_MASTER_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ - -#define TWI_MASTER_RIEN_bm 0x20 /* Read Interrupt Enable bit mask. */ -#define TWI_MASTER_RIEN_bp 5 /* Read Interrupt Enable bit position. */ - -#define TWI_MASTER_WIEN_bm 0x10 /* Write Interrupt Enable bit mask. */ -#define TWI_MASTER_WIEN_bp 4 /* Write Interrupt Enable bit position. */ - -#define TWI_MASTER_ENABLE_bm 0x08 /* Enable TWI Master bit mask. */ -#define TWI_MASTER_ENABLE_bp 3 /* Enable TWI Master bit position. */ - -/* TWI_MASTER.CTRLB bit masks and bit positions */ -#define TWI_MASTER_TIMEOUT_gm 0x0C /* Inactive Bus Timeout group mask. */ -#define TWI_MASTER_TIMEOUT_gp 2 /* Inactive Bus Timeout group position. */ -#define TWI_MASTER_TIMEOUT0_bm (1<<2) /* Inactive Bus Timeout bit 0 mask. */ -#define TWI_MASTER_TIMEOUT0_bp 2 /* Inactive Bus Timeout bit 0 position. */ -#define TWI_MASTER_TIMEOUT1_bm (1<<3) /* Inactive Bus Timeout bit 1 mask. */ -#define TWI_MASTER_TIMEOUT1_bp 3 /* Inactive Bus Timeout bit 1 position. */ - -#define TWI_MASTER_QCEN_bm 0x02 /* Quick Command Enable bit mask. */ -#define TWI_MASTER_QCEN_bp 1 /* Quick Command Enable bit position. */ - -#define TWI_MASTER_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ -#define TWI_MASTER_SMEN_bp 0 /* Smart Mode Enable bit position. */ - -/* TWI_MASTER.CTRLC bit masks and bit positions */ -#define TWI_MASTER_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ -#define TWI_MASTER_ACKACT_bp 2 /* Acknowledge Action bit position. */ - -#define TWI_MASTER_CMD_gm 0x03 /* Command group mask. */ -#define TWI_MASTER_CMD_gp 0 /* Command group position. */ -#define TWI_MASTER_CMD0_bm (1<<0) /* Command bit 0 mask. */ -#define TWI_MASTER_CMD0_bp 0 /* Command bit 0 position. */ -#define TWI_MASTER_CMD1_bm (1<<1) /* Command bit 1 mask. */ -#define TWI_MASTER_CMD1_bp 1 /* Command bit 1 position. */ - -/* TWI_MASTER.STATUS bit masks and bit positions */ -#define TWI_MASTER_RIF_bm 0x80 /* Read Interrupt Flag bit mask. */ -#define TWI_MASTER_RIF_bp 7 /* Read Interrupt Flag bit position. */ - -#define TWI_MASTER_WIF_bm 0x40 /* Write Interrupt Flag bit mask. */ -#define TWI_MASTER_WIF_bp 6 /* Write Interrupt Flag bit position. */ - -#define TWI_MASTER_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ -#define TWI_MASTER_CLKHOLD_bp 5 /* Clock Hold bit position. */ - -#define TWI_MASTER_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ -#define TWI_MASTER_RXACK_bp 4 /* Received Acknowledge bit position. */ - -#define TWI_MASTER_ARBLOST_bm 0x08 /* Arbitration Lost bit mask. */ -#define TWI_MASTER_ARBLOST_bp 3 /* Arbitration Lost bit position. */ - -#define TWI_MASTER_BUSERR_bm 0x04 /* Bus Error bit mask. */ -#define TWI_MASTER_BUSERR_bp 2 /* Bus Error bit position. */ - -#define TWI_MASTER_BUSSTATE_gm 0x03 /* Bus State group mask. */ -#define TWI_MASTER_BUSSTATE_gp 0 /* Bus State group position. */ -#define TWI_MASTER_BUSSTATE0_bm (1<<0) /* Bus State bit 0 mask. */ -#define TWI_MASTER_BUSSTATE0_bp 0 /* Bus State bit 0 position. */ -#define TWI_MASTER_BUSSTATE1_bm (1<<1) /* Bus State bit 1 mask. */ -#define TWI_MASTER_BUSSTATE1_bp 1 /* Bus State bit 1 position. */ - -/* TWI_SLAVE.CTRLA bit masks and bit positions */ -#define TWI_SLAVE_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ -#define TWI_SLAVE_INTLVL_gp 6 /* Interrupt Level group position. */ -#define TWI_SLAVE_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ -#define TWI_SLAVE_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ -#define TWI_SLAVE_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ -#define TWI_SLAVE_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ - -#define TWI_SLAVE_DIEN_bm 0x20 /* Data Interrupt Enable bit mask. */ -#define TWI_SLAVE_DIEN_bp 5 /* Data Interrupt Enable bit position. */ - -#define TWI_SLAVE_APIEN_bm 0x10 /* Address/Stop Interrupt Enable bit mask. */ -#define TWI_SLAVE_APIEN_bp 4 /* Address/Stop Interrupt Enable bit position. */ - -#define TWI_SLAVE_ENABLE_bm 0x08 /* Enable TWI Slave bit mask. */ -#define TWI_SLAVE_ENABLE_bp 3 /* Enable TWI Slave bit position. */ - -#define TWI_SLAVE_PIEN_bm 0x04 /* Stop Interrupt Enable bit mask. */ -#define TWI_SLAVE_PIEN_bp 2 /* Stop Interrupt Enable bit position. */ - -#define TWI_SLAVE_PMEN_bm 0x02 /* Promiscuous Mode Enable bit mask. */ -#define TWI_SLAVE_PMEN_bp 1 /* Promiscuous Mode Enable bit position. */ - -#define TWI_SLAVE_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ -#define TWI_SLAVE_SMEN_bp 0 /* Smart Mode Enable bit position. */ - -/* TWI_SLAVE.CTRLB bit masks and bit positions */ -#define TWI_SLAVE_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ -#define TWI_SLAVE_ACKACT_bp 2 /* Acknowledge Action bit position. */ - -#define TWI_SLAVE_CMD_gm 0x03 /* Command group mask. */ -#define TWI_SLAVE_CMD_gp 0 /* Command group position. */ -#define TWI_SLAVE_CMD0_bm (1<<0) /* Command bit 0 mask. */ -#define TWI_SLAVE_CMD0_bp 0 /* Command bit 0 position. */ -#define TWI_SLAVE_CMD1_bm (1<<1) /* Command bit 1 mask. */ -#define TWI_SLAVE_CMD1_bp 1 /* Command bit 1 position. */ - -/* TWI_SLAVE.STATUS bit masks and bit positions */ -#define TWI_SLAVE_DIF_bm 0x80 /* Data Interrupt Flag bit mask. */ -#define TWI_SLAVE_DIF_bp 7 /* Data Interrupt Flag bit position. */ - -#define TWI_SLAVE_APIF_bm 0x40 /* Address/Stop Interrupt Flag bit mask. */ -#define TWI_SLAVE_APIF_bp 6 /* Address/Stop Interrupt Flag bit position. */ - -#define TWI_SLAVE_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ -#define TWI_SLAVE_CLKHOLD_bp 5 /* Clock Hold bit position. */ - -#define TWI_SLAVE_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ -#define TWI_SLAVE_RXACK_bp 4 /* Received Acknowledge bit position. */ - -#define TWI_SLAVE_COLL_bm 0x08 /* Collision bit mask. */ -#define TWI_SLAVE_COLL_bp 3 /* Collision bit position. */ - -#define TWI_SLAVE_BUSERR_bm 0x04 /* Bus Error bit mask. */ -#define TWI_SLAVE_BUSERR_bp 2 /* Bus Error bit position. */ - -#define TWI_SLAVE_DIR_bm 0x02 /* Read/Write Direction bit mask. */ -#define TWI_SLAVE_DIR_bp 1 /* Read/Write Direction bit position. */ - -#define TWI_SLAVE_AP_bm 0x01 /* Slave Address or Stop bit mask. */ -#define TWI_SLAVE_AP_bp 0 /* Slave Address or Stop bit position. */ - -/* TWI_SLAVE.ADDRMASK bit masks and bit positions */ -#define TWI_SLAVE_ADDRMASK_gm 0xFE /* Address Mask group mask. */ -#define TWI_SLAVE_ADDRMASK_gp 1 /* Address Mask group position. */ -#define TWI_SLAVE_ADDRMASK0_bm (1<<1) /* Address Mask bit 0 mask. */ -#define TWI_SLAVE_ADDRMASK0_bp 1 /* Address Mask bit 0 position. */ -#define TWI_SLAVE_ADDRMASK1_bm (1<<2) /* Address Mask bit 1 mask. */ -#define TWI_SLAVE_ADDRMASK1_bp 2 /* Address Mask bit 1 position. */ -#define TWI_SLAVE_ADDRMASK2_bm (1<<3) /* Address Mask bit 2 mask. */ -#define TWI_SLAVE_ADDRMASK2_bp 3 /* Address Mask bit 2 position. */ -#define TWI_SLAVE_ADDRMASK3_bm (1<<4) /* Address Mask bit 3 mask. */ -#define TWI_SLAVE_ADDRMASK3_bp 4 /* Address Mask bit 3 position. */ -#define TWI_SLAVE_ADDRMASK4_bm (1<<5) /* Address Mask bit 4 mask. */ -#define TWI_SLAVE_ADDRMASK4_bp 5 /* Address Mask bit 4 position. */ -#define TWI_SLAVE_ADDRMASK5_bm (1<<6) /* Address Mask bit 5 mask. */ -#define TWI_SLAVE_ADDRMASK5_bp 6 /* Address Mask bit 5 position. */ -#define TWI_SLAVE_ADDRMASK6_bm (1<<7) /* Address Mask bit 6 mask. */ -#define TWI_SLAVE_ADDRMASK6_bp 7 /* Address Mask bit 6 position. */ - -#define TWI_SLAVE_ADDREN_bm 0x01 /* Address Enable bit mask. */ -#define TWI_SLAVE_ADDREN_bp 0 /* Address Enable bit position. */ - -/* TWI.CTRL bit masks and bit positions */ -#define TWI_SDAHOLD_gm 0x06 /* SDA Hold Time Enable group mask. */ -#define TWI_SDAHOLD_gp 1 /* SDA Hold Time Enable group position. */ -#define TWI_SDAHOLD0_bm (1<<1) /* SDA Hold Time Enable bit 0 mask. */ -#define TWI_SDAHOLD0_bp 1 /* SDA Hold Time Enable bit 0 position. */ -#define TWI_SDAHOLD1_bm (1<<2) /* SDA Hold Time Enable bit 1 mask. */ -#define TWI_SDAHOLD1_bp 2 /* SDA Hold Time Enable bit 1 position. */ - -#define TWI_EDIEN_bm 0x01 /* External Driver Interface Enable bit mask. */ -#define TWI_EDIEN_bp 0 /* External Driver Interface Enable bit position. */ - -/* USB - USB */ -/* USB_EP.STATUS bit masks and bit positions */ -#define USB_EP_STALLF_bm 0x80 /* Endpoint Stall Flag bit mask. */ -#define USB_EP_STALLF_bp 7 /* Endpoint Stall Flag bit position. */ - -#define USB_EP_CRC_bm 0x80 /* CRC Error Flag bit mask. */ -#define USB_EP_CRC_bp 7 /* CRC Error Flag bit position. */ - -#define USB_EP_UNF_bm 0x40 /* Underflow Enpoint FLag bit mask. */ -#define USB_EP_UNF_bp 6 /* Underflow Enpoint FLag bit position. */ - -#define USB_EP_OVF_bm 0x40 /* Overflow Enpoint Flag for Output Endpoints bit mask. */ -#define USB_EP_OVF_bp 6 /* Overflow Enpoint Flag for Output Endpoints bit position. */ - -#define USB_EP_TRNCOMPL0_bm 0x20 /* Transaction Complete 0 Flag bit mask. */ -#define USB_EP_TRNCOMPL0_bp 5 /* Transaction Complete 0 Flag bit position. */ - -#define USB_EP_TRNCOMPL1_bm 0x10 /* Transaction Complete 1 Flag bit mask. */ -#define USB_EP_TRNCOMPL1_bp 4 /* Transaction Complete 1 Flag bit position. */ - -#define USB_EP_SETUP_bm 0x10 /* SETUP Transaction Complete Flag bit mask. */ -#define USB_EP_SETUP_bp 4 /* SETUP Transaction Complete Flag bit position. */ - -#define USB_EP_BANK_bm 0x08 /* Bank Select bit mask. */ -#define USB_EP_BANK_bp 3 /* Bank Select bit position. */ - -#define USB_EP_BUSNACK1_bm 0x04 /* Data Buffer 1 Not Acknowledge bit mask. */ -#define USB_EP_BUSNACK1_bp 2 /* Data Buffer 1 Not Acknowledge bit position. */ - -#define USB_EP_BUSNACK0_bm 0x02 /* Data Buffer 0 Not Acknowledge bit mask. */ -#define USB_EP_BUSNACK0_bp 1 /* Data Buffer 0 Not Acknowledge bit position. */ - -#define USB_EP_TOGGLE_bm 0x01 /* Data Toggle bit mask. */ -#define USB_EP_TOGGLE_bp 0 /* Data Toggle bit position. */ - -/* USB_EP.CTRL bit masks and bit positions */ -#define USB_EP_TYPE_gm 0xC0 /* Endpoint Type group mask. */ -#define USB_EP_TYPE_gp 6 /* Endpoint Type group position. */ -#define USB_EP_TYPE0_bm (1<<6) /* Endpoint Type bit 0 mask. */ -#define USB_EP_TYPE0_bp 6 /* Endpoint Type bit 0 position. */ -#define USB_EP_TYPE1_bm (1<<7) /* Endpoint Type bit 1 mask. */ -#define USB_EP_TYPE1_bp 7 /* Endpoint Type bit 1 position. */ - -#define USB_EP_MULTIPKT_bm 0x20 /* Multi Packet Transfer Enable bit mask. */ -#define USB_EP_MULTIPKT_bp 5 /* Multi Packet Transfer Enable bit position. */ - -#define USB_EP_PINGPONG_bm 0x10 /* Ping-Pong Enable bit mask. */ -#define USB_EP_PINGPONG_bp 4 /* Ping-Pong Enable bit position. */ - -#define USB_EP_INTDSBL_bm 0x08 /* Interrupt Disable bit mask. */ -#define USB_EP_INTDSBL_bp 3 /* Interrupt Disable bit position. */ - -#define USB_EP_STALL_bm 0x04 /* Data Stall bit mask. */ -#define USB_EP_STALL_bp 2 /* Data Stall bit position. */ - -#define USB_EP_BUFSIZE_gm 0x07 /* Data Buffer Size group mask. */ -#define USB_EP_BUFSIZE_gp 0 /* Data Buffer Size group position. */ -#define USB_EP_BUFSIZE0_bm (1<<0) /* Data Buffer Size bit 0 mask. */ -#define USB_EP_BUFSIZE0_bp 0 /* Data Buffer Size bit 0 position. */ -#define USB_EP_BUFSIZE1_bm (1<<1) /* Data Buffer Size bit 1 mask. */ -#define USB_EP_BUFSIZE1_bp 1 /* Data Buffer Size bit 1 position. */ -#define USB_EP_BUFSIZE2_bm (1<<2) /* Data Buffer Size bit 2 mask. */ -#define USB_EP_BUFSIZE2_bp 2 /* Data Buffer Size bit 2 position. */ - -/* USB_EP.CNT bit masks and bit positions */ -#define USB_EP_ZLP_bm 0x8000 /* Zero Length Packet bit mask. */ -#define USB_EP_ZLP_bp 15 /* Zero Length Packet bit position. */ - -/* USB.CTRLA bit masks and bit positions */ -#define USB_ENABLE_bm 0x80 /* USB Enable bit mask. */ -#define USB_ENABLE_bp 7 /* USB Enable bit position. */ - -#define USB_SPEED_bm 0x40 /* Speed Select bit mask. */ -#define USB_SPEED_bp 6 /* Speed Select bit position. */ - -#define USB_FIFOEN_bm 0x20 /* USB FIFO Enable bit mask. */ -#define USB_FIFOEN_bp 5 /* USB FIFO Enable bit position. */ - -#define USB_STFRNUM_bm 0x10 /* Store Frame Number Enable bit mask. */ -#define USB_STFRNUM_bp 4 /* Store Frame Number Enable bit position. */ - -#define USB_MAXEP_gm 0x0F /* Maximum Endpoint Addresses group mask. */ -#define USB_MAXEP_gp 0 /* Maximum Endpoint Addresses group position. */ -#define USB_MAXEP0_bm (1<<0) /* Maximum Endpoint Addresses bit 0 mask. */ -#define USB_MAXEP0_bp 0 /* Maximum Endpoint Addresses bit 0 position. */ -#define USB_MAXEP1_bm (1<<1) /* Maximum Endpoint Addresses bit 1 mask. */ -#define USB_MAXEP1_bp 1 /* Maximum Endpoint Addresses bit 1 position. */ -#define USB_MAXEP2_bm (1<<2) /* Maximum Endpoint Addresses bit 2 mask. */ -#define USB_MAXEP2_bp 2 /* Maximum Endpoint Addresses bit 2 position. */ -#define USB_MAXEP3_bm (1<<3) /* Maximum Endpoint Addresses bit 3 mask. */ -#define USB_MAXEP3_bp 3 /* Maximum Endpoint Addresses bit 3 position. */ - -/* USB.CTRLB bit masks and bit positions */ -#define USB_PULLRST_bm 0x10 /* Pull during Reset bit mask. */ -#define USB_PULLRST_bp 4 /* Pull during Reset bit position. */ - -#define USB_RWAKEUP_bm 0x04 /* Remote Wake-up bit mask. */ -#define USB_RWAKEUP_bp 2 /* Remote Wake-up bit position. */ - -#define USB_GNACK_bm 0x02 /* Global NACK bit mask. */ -#define USB_GNACK_bp 1 /* Global NACK bit position. */ - -#define USB_ATTACH_bm 0x01 /* Attach bit mask. */ -#define USB_ATTACH_bp 0 /* Attach bit position. */ - -/* USB.STATUS bit masks and bit positions */ -#define USB_URESUME_bm 0x08 /* Upstream Resume bit mask. */ -#define USB_URESUME_bp 3 /* Upstream Resume bit position. */ - -#define USB_RESUME_bm 0x04 /* Resume bit mask. */ -#define USB_RESUME_bp 2 /* Resume bit position. */ - -#define USB_SUSPEND_bm 0x02 /* Bus Suspended bit mask. */ -#define USB_SUSPEND_bp 1 /* Bus Suspended bit position. */ - -#define USB_BUSRST_bm 0x01 /* Bus Reset bit mask. */ -#define USB_BUSRST_bp 0 /* Bus Reset bit position. */ - -/* USB.ADDR bit masks and bit positions */ -#define USB_ADDR_gm 0x7F /* Device Address group mask. */ -#define USB_ADDR_gp 0 /* Device Address group position. */ -#define USB_ADDR0_bm (1<<0) /* Device Address bit 0 mask. */ -#define USB_ADDR0_bp 0 /* Device Address bit 0 position. */ -#define USB_ADDR1_bm (1<<1) /* Device Address bit 1 mask. */ -#define USB_ADDR1_bp 1 /* Device Address bit 1 position. */ -#define USB_ADDR2_bm (1<<2) /* Device Address bit 2 mask. */ -#define USB_ADDR2_bp 2 /* Device Address bit 2 position. */ -#define USB_ADDR3_bm (1<<3) /* Device Address bit 3 mask. */ -#define USB_ADDR3_bp 3 /* Device Address bit 3 position. */ -#define USB_ADDR4_bm (1<<4) /* Device Address bit 4 mask. */ -#define USB_ADDR4_bp 4 /* Device Address bit 4 position. */ -#define USB_ADDR5_bm (1<<5) /* Device Address bit 5 mask. */ -#define USB_ADDR5_bp 5 /* Device Address bit 5 position. */ -#define USB_ADDR6_bm (1<<6) /* Device Address bit 6 mask. */ -#define USB_ADDR6_bp 6 /* Device Address bit 6 position. */ - -/* USB.FIFOWP bit masks and bit positions */ -#define USB_FIFOWP_gm 0x1F /* FIFO Write Pointer group mask. */ -#define USB_FIFOWP_gp 0 /* FIFO Write Pointer group position. */ -#define USB_FIFOWP0_bm (1<<0) /* FIFO Write Pointer bit 0 mask. */ -#define USB_FIFOWP0_bp 0 /* FIFO Write Pointer bit 0 position. */ -#define USB_FIFOWP1_bm (1<<1) /* FIFO Write Pointer bit 1 mask. */ -#define USB_FIFOWP1_bp 1 /* FIFO Write Pointer bit 1 position. */ -#define USB_FIFOWP2_bm (1<<2) /* FIFO Write Pointer bit 2 mask. */ -#define USB_FIFOWP2_bp 2 /* FIFO Write Pointer bit 2 position. */ -#define USB_FIFOWP3_bm (1<<3) /* FIFO Write Pointer bit 3 mask. */ -#define USB_FIFOWP3_bp 3 /* FIFO Write Pointer bit 3 position. */ -#define USB_FIFOWP4_bm (1<<4) /* FIFO Write Pointer bit 4 mask. */ -#define USB_FIFOWP4_bp 4 /* FIFO Write Pointer bit 4 position. */ - -/* USB.FIFORP bit masks and bit positions */ -#define USB_FIFORP_gm 0x1F /* FIFO Read Pointer group mask. */ -#define USB_FIFORP_gp 0 /* FIFO Read Pointer group position. */ -#define USB_FIFORP0_bm (1<<0) /* FIFO Read Pointer bit 0 mask. */ -#define USB_FIFORP0_bp 0 /* FIFO Read Pointer bit 0 position. */ -#define USB_FIFORP1_bm (1<<1) /* FIFO Read Pointer bit 1 mask. */ -#define USB_FIFORP1_bp 1 /* FIFO Read Pointer bit 1 position. */ -#define USB_FIFORP2_bm (1<<2) /* FIFO Read Pointer bit 2 mask. */ -#define USB_FIFORP2_bp 2 /* FIFO Read Pointer bit 2 position. */ -#define USB_FIFORP3_bm (1<<3) /* FIFO Read Pointer bit 3 mask. */ -#define USB_FIFORP3_bp 3 /* FIFO Read Pointer bit 3 position. */ -#define USB_FIFORP4_bm (1<<4) /* FIFO Read Pointer bit 4 mask. */ -#define USB_FIFORP4_bp 4 /* FIFO Read Pointer bit 4 position. */ - -/* USB.INTCTRLA bit masks and bit positions */ -#define USB_SOFIE_bm 0x80 /* Start Of Frame Interrupt Enable bit mask. */ -#define USB_SOFIE_bp 7 /* Start Of Frame Interrupt Enable bit position. */ - -#define USB_BUSEVIE_bm 0x40 /* Bus Event Interrupt Enable bit mask. */ -#define USB_BUSEVIE_bp 6 /* Bus Event Interrupt Enable bit position. */ - -#define USB_BUSERRIE_bm 0x20 /* Bus Error Interrupt Enable bit mask. */ -#define USB_BUSERRIE_bp 5 /* Bus Error Interrupt Enable bit position. */ - -#define USB_STALLIE_bm 0x10 /* STALL Interrupt Enable bit mask. */ -#define USB_STALLIE_bp 4 /* STALL Interrupt Enable bit position. */ - -#define USB_INTLVL_gm 0x03 /* Interrupt Level group mask. */ -#define USB_INTLVL_gp 0 /* Interrupt Level group position. */ -#define USB_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */ -#define USB_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */ -#define USB_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ -#define USB_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */ - -/* USB.INTCTRLB bit masks and bit positions */ -#define USB_TRNIE_bm 0x02 /* Transaction Complete Interrupt Enable bit mask. */ -#define USB_TRNIE_bp 1 /* Transaction Complete Interrupt Enable bit position. */ - -#define USB_SETUPIE_bm 0x01 /* SETUP Transaction Complete Interrupt Enable bit mask. */ -#define USB_SETUPIE_bp 0 /* SETUP Transaction Complete Interrupt Enable bit position. */ - -/* USB.INTFLAGSACLR bit masks and bit positions */ -#define USB_SOFIF_bm 0x80 /* Start Of Frame Interrupt Flag bit mask. */ -#define USB_SOFIF_bp 7 /* Start Of Frame Interrupt Flag bit position. */ - -#define USB_SUSPENDIF_bm 0x40 /* Suspend Interrupt Flag bit mask. */ -#define USB_SUSPENDIF_bp 6 /* Suspend Interrupt Flag bit position. */ - -#define USB_RESUMEIF_bm 0x20 /* Resume Interrupt Flag bit mask. */ -#define USB_RESUMEIF_bp 5 /* Resume Interrupt Flag bit position. */ - -#define USB_RSTIF_bm 0x10 /* Reset Interrupt Flag bit mask. */ -#define USB_RSTIF_bp 4 /* Reset Interrupt Flag bit position. */ - -#define USB_CRCIF_bm 0x08 /* Isochronous CRC Error Interrupt Flag bit mask. */ -#define USB_CRCIF_bp 3 /* Isochronous CRC Error Interrupt Flag bit position. */ - -#define USB_UNFIF_bm 0x04 /* Underflow Interrupt Flag bit mask. */ -#define USB_UNFIF_bp 2 /* Underflow Interrupt Flag bit position. */ - -#define USB_OVFIF_bm 0x02 /* Overflow Interrupt Flag bit mask. */ -#define USB_OVFIF_bp 1 /* Overflow Interrupt Flag bit position. */ - -#define USB_STALLIF_bm 0x01 /* STALL Interrupt Flag bit mask. */ -#define USB_STALLIF_bp 0 /* STALL Interrupt Flag bit position. */ - -/* USB.INTFLAGSASET bit masks and bit positions */ -/* USB_SOFIF Predefined. */ -/* USB_SOFIF Predefined. */ - -/* USB_SUSPENDIF Predefined. */ -/* USB_SUSPENDIF Predefined. */ - -/* USB_RESUMEIF Predefined. */ -/* USB_RESUMEIF Predefined. */ - -/* USB_RSTIF Predefined. */ -/* USB_RSTIF Predefined. */ - -/* USB_CRCIF Predefined. */ -/* USB_CRCIF Predefined. */ - -/* USB_UNFIF Predefined. */ -/* USB_UNFIF Predefined. */ - -/* USB_OVFIF Predefined. */ -/* USB_OVFIF Predefined. */ - -/* USB_STALLIF Predefined. */ -/* USB_STALLIF Predefined. */ - -/* USB.INTFLAGSBCLR bit masks and bit positions */ -#define USB_TRNIF_bm 0x02 /* Transaction Complete Interrupt Flag bit mask. */ -#define USB_TRNIF_bp 1 /* Transaction Complete Interrupt Flag bit position. */ - -#define USB_SETUPIF_bm 0x01 /* SETUP Transaction Complete Interrupt Flag bit mask. */ -#define USB_SETUPIF_bp 0 /* SETUP Transaction Complete Interrupt Flag bit position. */ - -/* USB.INTFLAGSBSET bit masks and bit positions */ -/* USB_TRNIF Predefined. */ -/* USB_TRNIF Predefined. */ - -/* USB_SETUPIF Predefined. */ -/* USB_SETUPIF Predefined. */ - -/* PORT - I/O Port Configuration */ -/* PORT.INTCTRL bit masks and bit positions */ -#define PORT_INT1LVL_gm 0x0C /* Port Interrupt 1 Level group mask. */ -#define PORT_INT1LVL_gp 2 /* Port Interrupt 1 Level group position. */ -#define PORT_INT1LVL0_bm (1<<2) /* Port Interrupt 1 Level bit 0 mask. */ -#define PORT_INT1LVL0_bp 2 /* Port Interrupt 1 Level bit 0 position. */ -#define PORT_INT1LVL1_bm (1<<3) /* Port Interrupt 1 Level bit 1 mask. */ -#define PORT_INT1LVL1_bp 3 /* Port Interrupt 1 Level bit 1 position. */ - -#define PORT_INT0LVL_gm 0x03 /* Port Interrupt 0 Level group mask. */ -#define PORT_INT0LVL_gp 0 /* Port Interrupt 0 Level group position. */ -#define PORT_INT0LVL0_bm (1<<0) /* Port Interrupt 0 Level bit 0 mask. */ -#define PORT_INT0LVL0_bp 0 /* Port Interrupt 0 Level bit 0 position. */ -#define PORT_INT0LVL1_bm (1<<1) /* Port Interrupt 0 Level bit 1 mask. */ -#define PORT_INT0LVL1_bp 1 /* Port Interrupt 0 Level bit 1 position. */ - -/* PORT.INTFLAGS bit masks and bit positions */ -#define PORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ -#define PORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ - -#define PORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ -#define PORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ - -/* PORT.REMAP bit masks and bit positions */ -#define PORT_SPI_bm 0x20 /* SPI bit mask. */ -#define PORT_SPI_bp 5 /* SPI bit position. */ - -#define PORT_USART0_bm 0x10 /* USART0 bit mask. */ -#define PORT_USART0_bp 4 /* USART0 bit position. */ - -#define PORT_TC0D_bm 0x08 /* Timer/Counter 0 Output Compare D bit mask. */ -#define PORT_TC0D_bp 3 /* Timer/Counter 0 Output Compare D bit position. */ - -#define PORT_TC0C_bm 0x04 /* Timer/Counter 0 Output Compare C bit mask. */ -#define PORT_TC0C_bp 2 /* Timer/Counter 0 Output Compare C bit position. */ - -#define PORT_TC0B_bm 0x02 /* Timer/Counter 0 Output Compare B bit mask. */ -#define PORT_TC0B_bp 1 /* Timer/Counter 0 Output Compare B bit position. */ - -#define PORT_TC0A_bm 0x01 /* Timer/Counter 0 Output Compare A bit mask. */ -#define PORT_TC0A_bp 0 /* Timer/Counter 0 Output Compare A bit position. */ - -/* PORT.PIN0CTRL bit masks and bit positions */ -#define PORT_SRLEN_bm 0x80 /* Slew Rate Enable bit mask. */ -#define PORT_SRLEN_bp 7 /* Slew Rate Enable bit position. */ - -#define PORT_INVEN_bm 0x40 /* Inverted I/O Enable bit mask. */ -#define PORT_INVEN_bp 6 /* Inverted I/O Enable bit position. */ - -#define PORT_OPC_gm 0x38 /* Output/Pull Configuration group mask. */ -#define PORT_OPC_gp 3 /* Output/Pull Configuration group position. */ -#define PORT_OPC0_bm (1<<3) /* Output/Pull Configuration bit 0 mask. */ -#define PORT_OPC0_bp 3 /* Output/Pull Configuration bit 0 position. */ -#define PORT_OPC1_bm (1<<4) /* Output/Pull Configuration bit 1 mask. */ -#define PORT_OPC1_bp 4 /* Output/Pull Configuration bit 1 position. */ -#define PORT_OPC2_bm (1<<5) /* Output/Pull Configuration bit 2 mask. */ -#define PORT_OPC2_bp 5 /* Output/Pull Configuration bit 2 position. */ - -#define PORT_ISC_gm 0x07 /* Input/Sense Configuration group mask. */ -#define PORT_ISC_gp 0 /* Input/Sense Configuration group position. */ -#define PORT_ISC0_bm (1<<0) /* Input/Sense Configuration bit 0 mask. */ -#define PORT_ISC0_bp 0 /* Input/Sense Configuration bit 0 position. */ -#define PORT_ISC1_bm (1<<1) /* Input/Sense Configuration bit 1 mask. */ -#define PORT_ISC1_bp 1 /* Input/Sense Configuration bit 1 position. */ -#define PORT_ISC2_bm (1<<2) /* Input/Sense Configuration bit 2 mask. */ -#define PORT_ISC2_bp 2 /* Input/Sense Configuration bit 2 position. */ - -/* PORT.PIN1CTRL bit masks and bit positions */ -/* PORT_SRLEN Predefined. */ -/* PORT_SRLEN Predefined. */ - -/* PORT_INVEN Predefined. */ -/* PORT_INVEN Predefined. */ - -/* PORT_OPC Predefined. */ -/* PORT_OPC Predefined. */ - -/* PORT_ISC Predefined. */ -/* PORT_ISC Predefined. */ - -/* PORT.PIN2CTRL bit masks and bit positions */ -/* PORT_SRLEN Predefined. */ -/* PORT_SRLEN Predefined. */ - -/* PORT_INVEN Predefined. */ -/* PORT_INVEN Predefined. */ - -/* PORT_OPC Predefined. */ -/* PORT_OPC Predefined. */ - -/* PORT_ISC Predefined. */ -/* PORT_ISC Predefined. */ - -/* PORT.PIN3CTRL bit masks and bit positions */ -/* PORT_SRLEN Predefined. */ -/* PORT_SRLEN Predefined. */ - -/* PORT_INVEN Predefined. */ -/* PORT_INVEN Predefined. */ - -/* PORT_OPC Predefined. */ -/* PORT_OPC Predefined. */ - -/* PORT_ISC Predefined. */ -/* PORT_ISC Predefined. */ - -/* PORT.PIN4CTRL bit masks and bit positions */ -/* PORT_SRLEN Predefined. */ -/* PORT_SRLEN Predefined. */ - -/* PORT_INVEN Predefined. */ -/* PORT_INVEN Predefined. */ - -/* PORT_OPC Predefined. */ -/* PORT_OPC Predefined. */ - -/* PORT_ISC Predefined. */ -/* PORT_ISC Predefined. */ - -/* PORT.PIN5CTRL bit masks and bit positions */ -/* PORT_SRLEN Predefined. */ -/* PORT_SRLEN Predefined. */ - -/* PORT_INVEN Predefined. */ -/* PORT_INVEN Predefined. */ - -/* PORT_OPC Predefined. */ -/* PORT_OPC Predefined. */ - -/* PORT_ISC Predefined. */ -/* PORT_ISC Predefined. */ - -/* PORT.PIN6CTRL bit masks and bit positions */ -/* PORT_SRLEN Predefined. */ -/* PORT_SRLEN Predefined. */ - -/* PORT_INVEN Predefined. */ -/* PORT_INVEN Predefined. */ - -/* PORT_OPC Predefined. */ -/* PORT_OPC Predefined. */ - -/* PORT_ISC Predefined. */ -/* PORT_ISC Predefined. */ - -/* PORT.PIN7CTRL bit masks and bit positions */ -/* PORT_SRLEN Predefined. */ -/* PORT_SRLEN Predefined. */ - -/* PORT_INVEN Predefined. */ -/* PORT_INVEN Predefined. */ - -/* PORT_OPC Predefined. */ -/* PORT_OPC Predefined. */ - -/* PORT_ISC Predefined. */ -/* PORT_ISC Predefined. */ - -/* TC - 16-bit Timer/Counter With PWM */ -/* TC0.CTRLA bit masks and bit positions */ -#define TC0_CLKSEL_gm 0x0F /* Clock Selection group mask. */ -#define TC0_CLKSEL_gp 0 /* Clock Selection group position. */ -#define TC0_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ -#define TC0_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ -#define TC0_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ -#define TC0_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ -#define TC0_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ -#define TC0_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ -#define TC0_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ -#define TC0_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ - -/* TC0.CTRLB bit masks and bit positions */ -#define TC0_CCDEN_bm 0x80 /* Compare or Capture D Enable bit mask. */ -#define TC0_CCDEN_bp 7 /* Compare or Capture D Enable bit position. */ - -#define TC0_CCCEN_bm 0x40 /* Compare or Capture C Enable bit mask. */ -#define TC0_CCCEN_bp 6 /* Compare or Capture C Enable bit position. */ - -#define TC0_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ -#define TC0_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ - -#define TC0_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ -#define TC0_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ - -#define TC0_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ -#define TC0_WGMODE_gp 0 /* Waveform generation mode group position. */ -#define TC0_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ -#define TC0_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ -#define TC0_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ -#define TC0_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ -#define TC0_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ -#define TC0_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ - -/* TC0.CTRLC bit masks and bit positions */ -#define TC0_CMPD_bm 0x08 /* Compare D Output Value bit mask. */ -#define TC0_CMPD_bp 3 /* Compare D Output Value bit position. */ - -#define TC0_CMPC_bm 0x04 /* Compare C Output Value bit mask. */ -#define TC0_CMPC_bp 2 /* Compare C Output Value bit position. */ - -#define TC0_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ -#define TC0_CMPB_bp 1 /* Compare B Output Value bit position. */ - -#define TC0_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ -#define TC0_CMPA_bp 0 /* Compare A Output Value bit position. */ - -/* TC0.CTRLD bit masks and bit positions */ -#define TC0_EVACT_gm 0xE0 /* Event Action group mask. */ -#define TC0_EVACT_gp 5 /* Event Action group position. */ -#define TC0_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ -#define TC0_EVACT0_bp 5 /* Event Action bit 0 position. */ -#define TC0_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ -#define TC0_EVACT1_bp 6 /* Event Action bit 1 position. */ -#define TC0_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ -#define TC0_EVACT2_bp 7 /* Event Action bit 2 position. */ - -#define TC0_EVDLY_bm 0x10 /* Event Delay bit mask. */ -#define TC0_EVDLY_bp 4 /* Event Delay bit position. */ - -#define TC0_EVSEL_gm 0x0F /* Event Source Select group mask. */ -#define TC0_EVSEL_gp 0 /* Event Source Select group position. */ -#define TC0_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ -#define TC0_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ -#define TC0_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ -#define TC0_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ -#define TC0_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ -#define TC0_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ -#define TC0_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ -#define TC0_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ - -/* TC0.CTRLE bit masks and bit positions */ -#define TC0_BYTEM_gm 0x03 /* Byte Mode group mask. */ -#define TC0_BYTEM_gp 0 /* Byte Mode group position. */ -#define TC0_BYTEM0_bm (1<<0) /* Byte Mode bit 0 mask. */ -#define TC0_BYTEM0_bp 0 /* Byte Mode bit 0 position. */ -#define TC0_BYTEM1_bm (1<<1) /* Byte Mode bit 1 mask. */ -#define TC0_BYTEM1_bp 1 /* Byte Mode bit 1 position. */ - -/* TC0.INTCTRLA bit masks and bit positions */ -#define TC0_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ -#define TC0_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ -#define TC0_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ -#define TC0_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ -#define TC0_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ -#define TC0_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ - -#define TC0_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ -#define TC0_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ -#define TC0_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ -#define TC0_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ -#define TC0_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ -#define TC0_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ - -/* TC0.INTCTRLB bit masks and bit positions */ -#define TC0_CCDINTLVL_gm 0xC0 /* Compare or Capture D Interrupt Level group mask. */ -#define TC0_CCDINTLVL_gp 6 /* Compare or Capture D Interrupt Level group position. */ -#define TC0_CCDINTLVL0_bm (1<<6) /* Compare or Capture D Interrupt Level bit 0 mask. */ -#define TC0_CCDINTLVL0_bp 6 /* Compare or Capture D Interrupt Level bit 0 position. */ -#define TC0_CCDINTLVL1_bm (1<<7) /* Compare or Capture D Interrupt Level bit 1 mask. */ -#define TC0_CCDINTLVL1_bp 7 /* Compare or Capture D Interrupt Level bit 1 position. */ - -#define TC0_CCCINTLVL_gm 0x30 /* Compare or Capture C Interrupt Level group mask. */ -#define TC0_CCCINTLVL_gp 4 /* Compare or Capture C Interrupt Level group position. */ -#define TC0_CCCINTLVL0_bm (1<<4) /* Compare or Capture C Interrupt Level bit 0 mask. */ -#define TC0_CCCINTLVL0_bp 4 /* Compare or Capture C Interrupt Level bit 0 position. */ -#define TC0_CCCINTLVL1_bm (1<<5) /* Compare or Capture C Interrupt Level bit 1 mask. */ -#define TC0_CCCINTLVL1_bp 5 /* Compare or Capture C Interrupt Level bit 1 position. */ - -#define TC0_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ -#define TC0_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ -#define TC0_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ -#define TC0_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ -#define TC0_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ -#define TC0_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ - -#define TC0_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ -#define TC0_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ -#define TC0_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ -#define TC0_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ -#define TC0_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ -#define TC0_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ - -/* TC0.CTRLFCLR bit masks and bit positions */ -#define TC0_CMD_gm 0x0C /* Command group mask. */ -#define TC0_CMD_gp 2 /* Command group position. */ -#define TC0_CMD0_bm (1<<2) /* Command bit 0 mask. */ -#define TC0_CMD0_bp 2 /* Command bit 0 position. */ -#define TC0_CMD1_bm (1<<3) /* Command bit 1 mask. */ -#define TC0_CMD1_bp 3 /* Command bit 1 position. */ - -#define TC0_LUPD_bm 0x02 /* Lock Update bit mask. */ -#define TC0_LUPD_bp 1 /* Lock Update bit position. */ - -#define TC0_DIR_bm 0x01 /* Direction bit mask. */ -#define TC0_DIR_bp 0 /* Direction bit position. */ - -/* TC0.CTRLFSET bit masks and bit positions */ -/* TC0_CMD Predefined. */ -/* TC0_CMD Predefined. */ - -/* TC0_LUPD Predefined. */ -/* TC0_LUPD Predefined. */ - -/* TC0_DIR Predefined. */ -/* TC0_DIR Predefined. */ - -/* TC0.CTRLGCLR bit masks and bit positions */ -#define TC0_CCDBV_bm 0x10 /* Compare or Capture D Buffer Valid bit mask. */ -#define TC0_CCDBV_bp 4 /* Compare or Capture D Buffer Valid bit position. */ - -#define TC0_CCCBV_bm 0x08 /* Compare or Capture C Buffer Valid bit mask. */ -#define TC0_CCCBV_bp 3 /* Compare or Capture C Buffer Valid bit position. */ - -#define TC0_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ -#define TC0_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ - -#define TC0_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ -#define TC0_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ - -#define TC0_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ -#define TC0_PERBV_bp 0 /* Period Buffer Valid bit position. */ - -/* TC0.CTRLGSET bit masks and bit positions */ -/* TC0_CCDBV Predefined. */ -/* TC0_CCDBV Predefined. */ - -/* TC0_CCCBV Predefined. */ -/* TC0_CCCBV Predefined. */ - -/* TC0_CCBBV Predefined. */ -/* TC0_CCBBV Predefined. */ - -/* TC0_CCABV Predefined. */ -/* TC0_CCABV Predefined. */ - -/* TC0_PERBV Predefined. */ -/* TC0_PERBV Predefined. */ - -/* TC0.INTFLAGS bit masks and bit positions */ -#define TC0_CCDIF_bm 0x80 /* Compare or Capture D Interrupt Flag bit mask. */ -#define TC0_CCDIF_bp 7 /* Compare or Capture D Interrupt Flag bit position. */ - -#define TC0_CCCIF_bm 0x40 /* Compare or Capture C Interrupt Flag bit mask. */ -#define TC0_CCCIF_bp 6 /* Compare or Capture C Interrupt Flag bit position. */ - -#define TC0_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ -#define TC0_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ - -#define TC0_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ -#define TC0_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ - -#define TC0_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ -#define TC0_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ - -#define TC0_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ -#define TC0_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ - -/* TC1.CTRLA bit masks and bit positions */ -#define TC1_CLKSEL_gm 0x0F /* Clock Selection group mask. */ -#define TC1_CLKSEL_gp 0 /* Clock Selection group position. */ -#define TC1_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ -#define TC1_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ -#define TC1_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ -#define TC1_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ -#define TC1_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ -#define TC1_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ -#define TC1_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ -#define TC1_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ - -/* TC1.CTRLB bit masks and bit positions */ -#define TC1_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ -#define TC1_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ - -#define TC1_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ -#define TC1_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ - -#define TC1_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ -#define TC1_WGMODE_gp 0 /* Waveform generation mode group position. */ -#define TC1_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ -#define TC1_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ -#define TC1_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ -#define TC1_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ -#define TC1_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ -#define TC1_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ - -/* TC1.CTRLC bit masks and bit positions */ -#define TC1_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ -#define TC1_CMPB_bp 1 /* Compare B Output Value bit position. */ - -#define TC1_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ -#define TC1_CMPA_bp 0 /* Compare A Output Value bit position. */ - -/* TC1.CTRLD bit masks and bit positions */ -#define TC1_EVACT_gm 0xE0 /* Event Action group mask. */ -#define TC1_EVACT_gp 5 /* Event Action group position. */ -#define TC1_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ -#define TC1_EVACT0_bp 5 /* Event Action bit 0 position. */ -#define TC1_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ -#define TC1_EVACT1_bp 6 /* Event Action bit 1 position. */ -#define TC1_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ -#define TC1_EVACT2_bp 7 /* Event Action bit 2 position. */ - -#define TC1_EVDLY_bm 0x10 /* Event Delay bit mask. */ -#define TC1_EVDLY_bp 4 /* Event Delay bit position. */ - -#define TC1_EVSEL_gm 0x0F /* Event Source Select group mask. */ -#define TC1_EVSEL_gp 0 /* Event Source Select group position. */ -#define TC1_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ -#define TC1_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ -#define TC1_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ -#define TC1_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ -#define TC1_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ -#define TC1_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ -#define TC1_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ -#define TC1_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ - -/* TC1.CTRLE bit masks and bit positions */ -#define TC1_BYTEM_bm 0x01 /* Byte Mode bit mask. */ -#define TC1_BYTEM_bp 0 /* Byte Mode bit position. */ - -/* TC1.INTCTRLA bit masks and bit positions */ -#define TC1_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ -#define TC1_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ -#define TC1_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ -#define TC1_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ -#define TC1_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ -#define TC1_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ - -#define TC1_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ -#define TC1_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ -#define TC1_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ -#define TC1_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ -#define TC1_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ -#define TC1_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ - -/* TC1.INTCTRLB bit masks and bit positions */ -#define TC1_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ -#define TC1_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ -#define TC1_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ -#define TC1_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ -#define TC1_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ -#define TC1_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ - -#define TC1_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ -#define TC1_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ -#define TC1_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ -#define TC1_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ -#define TC1_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ -#define TC1_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ - -/* TC1.CTRLFCLR bit masks and bit positions */ -#define TC1_CMD_gm 0x0C /* Command group mask. */ -#define TC1_CMD_gp 2 /* Command group position. */ -#define TC1_CMD0_bm (1<<2) /* Command bit 0 mask. */ -#define TC1_CMD0_bp 2 /* Command bit 0 position. */ -#define TC1_CMD1_bm (1<<3) /* Command bit 1 mask. */ -#define TC1_CMD1_bp 3 /* Command bit 1 position. */ - -#define TC1_LUPD_bm 0x02 /* Lock Update bit mask. */ -#define TC1_LUPD_bp 1 /* Lock Update bit position. */ - -#define TC1_DIR_bm 0x01 /* Direction bit mask. */ -#define TC1_DIR_bp 0 /* Direction bit position. */ - -/* TC1.CTRLFSET bit masks and bit positions */ -/* TC1_CMD Predefined. */ -/* TC1_CMD Predefined. */ - -/* TC1_LUPD Predefined. */ -/* TC1_LUPD Predefined. */ - -/* TC1_DIR Predefined. */ -/* TC1_DIR Predefined. */ - -/* TC1.CTRLGCLR bit masks and bit positions */ -#define TC1_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ -#define TC1_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ - -#define TC1_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ -#define TC1_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ - -#define TC1_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ -#define TC1_PERBV_bp 0 /* Period Buffer Valid bit position. */ - -/* TC1.CTRLGSET bit masks and bit positions */ -/* TC1_CCBBV Predefined. */ -/* TC1_CCBBV Predefined. */ - -/* TC1_CCABV Predefined. */ -/* TC1_CCABV Predefined. */ - -/* TC1_PERBV Predefined. */ -/* TC1_PERBV Predefined. */ - -/* TC1.INTFLAGS bit masks and bit positions */ -#define TC1_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ -#define TC1_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ - -#define TC1_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ -#define TC1_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ - -#define TC1_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ -#define TC1_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ - -#define TC1_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ -#define TC1_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ - -/* TC2 - 16-bit Timer/Counter type 2 */ -/* TC2.CTRLA bit masks and bit positions */ -#define TC2_CLKSEL_gm 0x0F /* Clock Selection group mask. */ -#define TC2_CLKSEL_gp 0 /* Clock Selection group position. */ -#define TC2_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ -#define TC2_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ -#define TC2_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ -#define TC2_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ -#define TC2_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ -#define TC2_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ -#define TC2_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ -#define TC2_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ - -/* TC2.CTRLB bit masks and bit positions */ -#define TC2_HCMPDEN_bm 0x80 /* High Byte Compare D Enable bit mask. */ -#define TC2_HCMPDEN_bp 7 /* High Byte Compare D Enable bit position. */ - -#define TC2_HCMPCEN_bm 0x40 /* High Byte Compare C Enable bit mask. */ -#define TC2_HCMPCEN_bp 6 /* High Byte Compare C Enable bit position. */ - -#define TC2_HCMPBEN_bm 0x20 /* High Byte Compare B Enable bit mask. */ -#define TC2_HCMPBEN_bp 5 /* High Byte Compare B Enable bit position. */ - -#define TC2_HCMPAEN_bm 0x10 /* High Byte Compare A Enable bit mask. */ -#define TC2_HCMPAEN_bp 4 /* High Byte Compare A Enable bit position. */ - -#define TC2_LCMPDEN_bm 0x08 /* Low Byte Compare D Enable bit mask. */ -#define TC2_LCMPDEN_bp 3 /* Low Byte Compare D Enable bit position. */ - -#define TC2_LCMPCEN_bm 0x04 /* Low Byte Compare C Enable bit mask. */ -#define TC2_LCMPCEN_bp 2 /* Low Byte Compare C Enable bit position. */ - -#define TC2_LCMPBEN_bm 0x02 /* Low Byte Compare B Enable bit mask. */ -#define TC2_LCMPBEN_bp 1 /* Low Byte Compare B Enable bit position. */ - -#define TC2_LCMPAEN_bm 0x01 /* Low Byte Compare A Enable bit mask. */ -#define TC2_LCMPAEN_bp 0 /* Low Byte Compare A Enable bit position. */ - -/* TC2.CTRLC bit masks and bit positions */ -#define TC2_HCMPD_bm 0x80 /* High Byte Compare D Output Value bit mask. */ -#define TC2_HCMPD_bp 7 /* High Byte Compare D Output Value bit position. */ - -#define TC2_HCMPC_bm 0x40 /* High Byte Compare C Output Value bit mask. */ -#define TC2_HCMPC_bp 6 /* High Byte Compare C Output Value bit position. */ - -#define TC2_HCMPB_bm 0x20 /* High Byte Compare B Output Value bit mask. */ -#define TC2_HCMPB_bp 5 /* High Byte Compare B Output Value bit position. */ - -#define TC2_HCMPA_bm 0x10 /* High Byte Compare A Output Value bit mask. */ -#define TC2_HCMPA_bp 4 /* High Byte Compare A Output Value bit position. */ - -#define TC2_LCMPD_bm 0x08 /* Low Byte Compare D Output Value bit mask. */ -#define TC2_LCMPD_bp 3 /* Low Byte Compare D Output Value bit position. */ - -#define TC2_LCMPC_bm 0x04 /* Low Byte Compare C Output Value bit mask. */ -#define TC2_LCMPC_bp 2 /* Low Byte Compare C Output Value bit position. */ - -#define TC2_LCMPB_bm 0x02 /* Low Byte Compare B Output Value bit mask. */ -#define TC2_LCMPB_bp 1 /* Low Byte Compare B Output Value bit position. */ - -#define TC2_LCMPA_bm 0x01 /* Low Byte Compare A Output Value bit mask. */ -#define TC2_LCMPA_bp 0 /* Low Byte Compare A Output Value bit position. */ - -/* TC2.CTRLE bit masks and bit positions */ -#define TC2_BYTEM_gm 0x03 /* Byte Mode group mask. */ -#define TC2_BYTEM_gp 0 /* Byte Mode group position. */ -#define TC2_BYTEM0_bm (1<<0) /* Byte Mode bit 0 mask. */ -#define TC2_BYTEM0_bp 0 /* Byte Mode bit 0 position. */ -#define TC2_BYTEM1_bm (1<<1) /* Byte Mode bit 1 mask. */ -#define TC2_BYTEM1_bp 1 /* Byte Mode bit 1 position. */ - -/* TC2.INTCTRLA bit masks and bit positions */ -#define TC2_HUNFINTLVL_gm 0x0C /* High Byte Underflow Interrupt Level group mask. */ -#define TC2_HUNFINTLVL_gp 2 /* High Byte Underflow Interrupt Level group position. */ -#define TC2_HUNFINTLVL0_bm (1<<2) /* High Byte Underflow Interrupt Level bit 0 mask. */ -#define TC2_HUNFINTLVL0_bp 2 /* High Byte Underflow Interrupt Level bit 0 position. */ -#define TC2_HUNFINTLVL1_bm (1<<3) /* High Byte Underflow Interrupt Level bit 1 mask. */ -#define TC2_HUNFINTLVL1_bp 3 /* High Byte Underflow Interrupt Level bit 1 position. */ - -#define TC2_LUNFINTLVL_gm 0x03 /* Low Byte Underflow interrupt level group mask. */ -#define TC2_LUNFINTLVL_gp 0 /* Low Byte Underflow interrupt level group position. */ -#define TC2_LUNFINTLVL0_bm (1<<0) /* Low Byte Underflow interrupt level bit 0 mask. */ -#define TC2_LUNFINTLVL0_bp 0 /* Low Byte Underflow interrupt level bit 0 position. */ -#define TC2_LUNFINTLVL1_bm (1<<1) /* Low Byte Underflow interrupt level bit 1 mask. */ -#define TC2_LUNFINTLVL1_bp 1 /* Low Byte Underflow interrupt level bit 1 position. */ - -/* TC2.INTCTRLB bit masks and bit positions */ -#define TC2_LCMPDINTLVL_gm 0xC0 /* Low Byte Compare D Interrupt Level group mask. */ -#define TC2_LCMPDINTLVL_gp 6 /* Low Byte Compare D Interrupt Level group position. */ -#define TC2_LCMPDINTLVL0_bm (1<<6) /* Low Byte Compare D Interrupt Level bit 0 mask. */ -#define TC2_LCMPDINTLVL0_bp 6 /* Low Byte Compare D Interrupt Level bit 0 position. */ -#define TC2_LCMPDINTLVL1_bm (1<<7) /* Low Byte Compare D Interrupt Level bit 1 mask. */ -#define TC2_LCMPDINTLVL1_bp 7 /* Low Byte Compare D Interrupt Level bit 1 position. */ - -#define TC2_LCMPCINTLVL_gm 0x30 /* Low Byte Compare C Interrupt Level group mask. */ -#define TC2_LCMPCINTLVL_gp 4 /* Low Byte Compare C Interrupt Level group position. */ -#define TC2_LCMPCINTLVL0_bm (1<<4) /* Low Byte Compare C Interrupt Level bit 0 mask. */ -#define TC2_LCMPCINTLVL0_bp 4 /* Low Byte Compare C Interrupt Level bit 0 position. */ -#define TC2_LCMPCINTLVL1_bm (1<<5) /* Low Byte Compare C Interrupt Level bit 1 mask. */ -#define TC2_LCMPCINTLVL1_bp 5 /* Low Byte Compare C Interrupt Level bit 1 position. */ - -#define TC2_LCMPBINTLVL_gm 0x0C /* Low Byte Compare B Interrupt Level group mask. */ -#define TC2_LCMPBINTLVL_gp 2 /* Low Byte Compare B Interrupt Level group position. */ -#define TC2_LCMPBINTLVL0_bm (1<<2) /* Low Byte Compare B Interrupt Level bit 0 mask. */ -#define TC2_LCMPBINTLVL0_bp 2 /* Low Byte Compare B Interrupt Level bit 0 position. */ -#define TC2_LCMPBINTLVL1_bm (1<<3) /* Low Byte Compare B Interrupt Level bit 1 mask. */ -#define TC2_LCMPBINTLVL1_bp 3 /* Low Byte Compare B Interrupt Level bit 1 position. */ - -#define TC2_LCMPAINTLVL_gm 0x03 /* Low Byte Compare A Interrupt Level group mask. */ -#define TC2_LCMPAINTLVL_gp 0 /* Low Byte Compare A Interrupt Level group position. */ -#define TC2_LCMPAINTLVL0_bm (1<<0) /* Low Byte Compare A Interrupt Level bit 0 mask. */ -#define TC2_LCMPAINTLVL0_bp 0 /* Low Byte Compare A Interrupt Level bit 0 position. */ -#define TC2_LCMPAINTLVL1_bm (1<<1) /* Low Byte Compare A Interrupt Level bit 1 mask. */ -#define TC2_LCMPAINTLVL1_bp 1 /* Low Byte Compare A Interrupt Level bit 1 position. */ - -/* TC2.CTRLF bit masks and bit positions */ -#define TC2_CMD_gm 0x0C /* Command group mask. */ -#define TC2_CMD_gp 2 /* Command group position. */ -#define TC2_CMD0_bm (1<<2) /* Command bit 0 mask. */ -#define TC2_CMD0_bp 2 /* Command bit 0 position. */ -#define TC2_CMD1_bm (1<<3) /* Command bit 1 mask. */ -#define TC2_CMD1_bp 3 /* Command bit 1 position. */ - -#define TC2_CMDEN_gm 0x03 /* Command Enable group mask. */ -#define TC2_CMDEN_gp 0 /* Command Enable group position. */ -#define TC2_CMDEN0_bm (1<<0) /* Command Enable bit 0 mask. */ -#define TC2_CMDEN0_bp 0 /* Command Enable bit 0 position. */ -#define TC2_CMDEN1_bm (1<<1) /* Command Enable bit 1 mask. */ -#define TC2_CMDEN1_bp 1 /* Command Enable bit 1 position. */ - -/* TC2.INTFLAGS bit masks and bit positions */ -#define TC2_LCMPDIF_bm 0x80 /* Low Byte Compare D Interrupt Flag bit mask. */ -#define TC2_LCMPDIF_bp 7 /* Low Byte Compare D Interrupt Flag bit position. */ - -#define TC2_LCMPCIF_bm 0x40 /* Low Byte Compare C Interrupt Flag bit mask. */ -#define TC2_LCMPCIF_bp 6 /* Low Byte Compare C Interrupt Flag bit position. */ - -#define TC2_LCMPBIF_bm 0x20 /* Low Byte Compare B Interrupt Flag bit mask. */ -#define TC2_LCMPBIF_bp 5 /* Low Byte Compare B Interrupt Flag bit position. */ - -#define TC2_LCMPAIF_bm 0x10 /* Low Byte Compare A Interrupt Flag bit mask. */ -#define TC2_LCMPAIF_bp 4 /* Low Byte Compare A Interrupt Flag bit position. */ - -#define TC2_HUNFIF_bm 0x02 /* High Byte Underflow Interrupt Flag bit mask. */ -#define TC2_HUNFIF_bp 1 /* High Byte Underflow Interrupt Flag bit position. */ - -#define TC2_LUNFIF_bm 0x01 /* Low Byte Underflow Interrupt Flag bit mask. */ -#define TC2_LUNFIF_bp 0 /* Low Byte Underflow Interrupt Flag bit position. */ - -/* AWEX - Timer/Counter Advanced Waveform Extension */ -/* AWEX.CTRL bit masks and bit positions */ -#define AWEX_PGM_bm 0x20 /* Pattern Generation Mode bit mask. */ -#define AWEX_PGM_bp 5 /* Pattern Generation Mode bit position. */ - -#define AWEX_CWCM_bm 0x10 /* Common Waveform Channel Mode bit mask. */ -#define AWEX_CWCM_bp 4 /* Common Waveform Channel Mode bit position. */ - -#define AWEX_DTICCDEN_bm 0x08 /* Dead Time Insertion Compare Channel D Enable bit mask. */ -#define AWEX_DTICCDEN_bp 3 /* Dead Time Insertion Compare Channel D Enable bit position. */ - -#define AWEX_DTICCCEN_bm 0x04 /* Dead Time Insertion Compare Channel C Enable bit mask. */ -#define AWEX_DTICCCEN_bp 2 /* Dead Time Insertion Compare Channel C Enable bit position. */ - -#define AWEX_DTICCBEN_bm 0x02 /* Dead Time Insertion Compare Channel B Enable bit mask. */ -#define AWEX_DTICCBEN_bp 1 /* Dead Time Insertion Compare Channel B Enable bit position. */ - -#define AWEX_DTICCAEN_bm 0x01 /* Dead Time Insertion Compare Channel A Enable bit mask. */ -#define AWEX_DTICCAEN_bp 0 /* Dead Time Insertion Compare Channel A Enable bit position. */ - -/* AWEX.FDCTRL bit masks and bit positions */ -#define AWEX_FDDBD_bm 0x10 /* Fault Detect on Disable Break Disable bit mask. */ -#define AWEX_FDDBD_bp 4 /* Fault Detect on Disable Break Disable bit position. */ - -#define AWEX_FDMODE_bm 0x04 /* Fault Detect Mode bit mask. */ -#define AWEX_FDMODE_bp 2 /* Fault Detect Mode bit position. */ - -#define AWEX_FDACT_gm 0x03 /* Fault Detect Action group mask. */ -#define AWEX_FDACT_gp 0 /* Fault Detect Action group position. */ -#define AWEX_FDACT0_bm (1<<0) /* Fault Detect Action bit 0 mask. */ -#define AWEX_FDACT0_bp 0 /* Fault Detect Action bit 0 position. */ -#define AWEX_FDACT1_bm (1<<1) /* Fault Detect Action bit 1 mask. */ -#define AWEX_FDACT1_bp 1 /* Fault Detect Action bit 1 position. */ - -/* AWEX.STATUS bit masks and bit positions */ -#define AWEX_FDF_bm 0x04 /* Fault Detect Flag bit mask. */ -#define AWEX_FDF_bp 2 /* Fault Detect Flag bit position. */ - -#define AWEX_DTHSBUFV_bm 0x02 /* Dead Time High Side Buffer Valid bit mask. */ -#define AWEX_DTHSBUFV_bp 1 /* Dead Time High Side Buffer Valid bit position. */ - -#define AWEX_DTLSBUFV_bm 0x01 /* Dead Time Low Side Buffer Valid bit mask. */ -#define AWEX_DTLSBUFV_bp 0 /* Dead Time Low Side Buffer Valid bit position. */ - -/* AWEX.STATUSSET bit masks and bit positions */ -/* AWEX_FDF Predefined. */ -/* AWEX_FDF Predefined. */ - -/* AWEX_DTHSBUFV Predefined. */ -/* AWEX_DTHSBUFV Predefined. */ - -/* AWEX_DTLSBUFV Predefined. */ -/* AWEX_DTLSBUFV Predefined. */ - -/* HIRES - Timer/Counter High-Resolution Extension */ -/* HIRES.CTRLA bit masks and bit positions */ -#define HIRES_HREN_gm 0x03 /* High Resolution Enable group mask. */ -#define HIRES_HREN_gp 0 /* High Resolution Enable group position. */ -#define HIRES_HREN0_bm (1<<0) /* High Resolution Enable bit 0 mask. */ -#define HIRES_HREN0_bp 0 /* High Resolution Enable bit 0 position. */ -#define HIRES_HREN1_bm (1<<1) /* High Resolution Enable bit 1 mask. */ -#define HIRES_HREN1_bp 1 /* High Resolution Enable bit 1 position. */ - -/* USART - Universal Asynchronous Receiver-Transmitter */ -/* USART.STATUS bit masks and bit positions */ -#define USART_RXCIF_bm 0x80 /* Receive Interrupt Flag bit mask. */ -#define USART_RXCIF_bp 7 /* Receive Interrupt Flag bit position. */ - -#define USART_TXCIF_bm 0x40 /* Transmit Interrupt Flag bit mask. */ -#define USART_TXCIF_bp 6 /* Transmit Interrupt Flag bit position. */ - -#define USART_DREIF_bm 0x20 /* Data Register Empty Flag bit mask. */ -#define USART_DREIF_bp 5 /* Data Register Empty Flag bit position. */ - -#define USART_FERR_bm 0x10 /* Frame Error bit mask. */ -#define USART_FERR_bp 4 /* Frame Error bit position. */ - -#define USART_BUFOVF_bm 0x08 /* Buffer Overflow bit mask. */ -#define USART_BUFOVF_bp 3 /* Buffer Overflow bit position. */ - -#define USART_PERR_bm 0x04 /* Parity Error bit mask. */ -#define USART_PERR_bp 2 /* Parity Error bit position. */ - -#define USART_RXB8_bm 0x01 /* Receive Bit 8 bit mask. */ -#define USART_RXB8_bp 0 /* Receive Bit 8 bit position. */ - -/* USART.CTRLA bit masks and bit positions */ -#define USART_RXCINTLVL_gm 0x30 /* Receive Interrupt Level group mask. */ -#define USART_RXCINTLVL_gp 4 /* Receive Interrupt Level group position. */ -#define USART_RXCINTLVL0_bm (1<<4) /* Receive Interrupt Level bit 0 mask. */ -#define USART_RXCINTLVL0_bp 4 /* Receive Interrupt Level bit 0 position. */ -#define USART_RXCINTLVL1_bm (1<<5) /* Receive Interrupt Level bit 1 mask. */ -#define USART_RXCINTLVL1_bp 5 /* Receive Interrupt Level bit 1 position. */ - -#define USART_TXCINTLVL_gm 0x0C /* Transmit Interrupt Level group mask. */ -#define USART_TXCINTLVL_gp 2 /* Transmit Interrupt Level group position. */ -#define USART_TXCINTLVL0_bm (1<<2) /* Transmit Interrupt Level bit 0 mask. */ -#define USART_TXCINTLVL0_bp 2 /* Transmit Interrupt Level bit 0 position. */ -#define USART_TXCINTLVL1_bm (1<<3) /* Transmit Interrupt Level bit 1 mask. */ -#define USART_TXCINTLVL1_bp 3 /* Transmit Interrupt Level bit 1 position. */ - -#define USART_DREINTLVL_gm 0x03 /* Data Register Empty Interrupt Level group mask. */ -#define USART_DREINTLVL_gp 0 /* Data Register Empty Interrupt Level group position. */ -#define USART_DREINTLVL0_bm (1<<0) /* Data Register Empty Interrupt Level bit 0 mask. */ -#define USART_DREINTLVL0_bp 0 /* Data Register Empty Interrupt Level bit 0 position. */ -#define USART_DREINTLVL1_bm (1<<1) /* Data Register Empty Interrupt Level bit 1 mask. */ -#define USART_DREINTLVL1_bp 1 /* Data Register Empty Interrupt Level bit 1 position. */ - -/* USART.CTRLB bit masks and bit positions */ -#define USART_RXEN_bm 0x10 /* Receiver Enable bit mask. */ -#define USART_RXEN_bp 4 /* Receiver Enable bit position. */ - -#define USART_TXEN_bm 0x08 /* Transmitter Enable bit mask. */ -#define USART_TXEN_bp 3 /* Transmitter Enable bit position. */ - -#define USART_CLK2X_bm 0x04 /* Double transmission speed bit mask. */ -#define USART_CLK2X_bp 2 /* Double transmission speed bit position. */ - -#define USART_MPCM_bm 0x02 /* Multi-processor Communication Mode bit mask. */ -#define USART_MPCM_bp 1 /* Multi-processor Communication Mode bit position. */ - -#define USART_TXB8_bm 0x01 /* Transmit bit 8 bit mask. */ -#define USART_TXB8_bp 0 /* Transmit bit 8 bit position. */ - -/* USART.CTRLC bit masks and bit positions */ -#define USART_CMODE_gm 0xC0 /* Communication Mode group mask. */ -#define USART_CMODE_gp 6 /* Communication Mode group position. */ -#define USART_CMODE0_bm (1<<6) /* Communication Mode bit 0 mask. */ -#define USART_CMODE0_bp 6 /* Communication Mode bit 0 position. */ -#define USART_CMODE1_bm (1<<7) /* Communication Mode bit 1 mask. */ -#define USART_CMODE1_bp 7 /* Communication Mode bit 1 position. */ - -#define USART_PMODE_gm 0x30 /* Parity Mode group mask. */ -#define USART_PMODE_gp 4 /* Parity Mode group position. */ -#define USART_PMODE0_bm (1<<4) /* Parity Mode bit 0 mask. */ -#define USART_PMODE0_bp 4 /* Parity Mode bit 0 position. */ -#define USART_PMODE1_bm (1<<5) /* Parity Mode bit 1 mask. */ -#define USART_PMODE1_bp 5 /* Parity Mode bit 1 position. */ - -#define USART_SBMODE_bm 0x08 /* Stop Bit Mode bit mask. */ -#define USART_SBMODE_bp 3 /* Stop Bit Mode bit position. */ - -#define USART_CHSIZE_gm 0x07 /* Character Size group mask. */ -#define USART_CHSIZE_gp 0 /* Character Size group position. */ -#define USART_CHSIZE0_bm (1<<0) /* Character Size bit 0 mask. */ -#define USART_CHSIZE0_bp 0 /* Character Size bit 0 position. */ -#define USART_CHSIZE1_bm (1<<1) /* Character Size bit 1 mask. */ -#define USART_CHSIZE1_bp 1 /* Character Size bit 1 position. */ -#define USART_CHSIZE2_bm (1<<2) /* Character Size bit 2 mask. */ -#define USART_CHSIZE2_bp 2 /* Character Size bit 2 position. */ - -/* USART.BAUDCTRLA bit masks and bit positions */ -#define USART_BSEL_gm 0xFF /* Baud Rate Selection Bits [7:0] group mask. */ -#define USART_BSEL_gp 0 /* Baud Rate Selection Bits [7:0] group position. */ -#define USART_BSEL0_bm (1<<0) /* Baud Rate Selection Bits [7:0] bit 0 mask. */ -#define USART_BSEL0_bp 0 /* Baud Rate Selection Bits [7:0] bit 0 position. */ -#define USART_BSEL1_bm (1<<1) /* Baud Rate Selection Bits [7:0] bit 1 mask. */ -#define USART_BSEL1_bp 1 /* Baud Rate Selection Bits [7:0] bit 1 position. */ -#define USART_BSEL2_bm (1<<2) /* Baud Rate Selection Bits [7:0] bit 2 mask. */ -#define USART_BSEL2_bp 2 /* Baud Rate Selection Bits [7:0] bit 2 position. */ -#define USART_BSEL3_bm (1<<3) /* Baud Rate Selection Bits [7:0] bit 3 mask. */ -#define USART_BSEL3_bp 3 /* Baud Rate Selection Bits [7:0] bit 3 position. */ -#define USART_BSEL4_bm (1<<4) /* Baud Rate Selection Bits [7:0] bit 4 mask. */ -#define USART_BSEL4_bp 4 /* Baud Rate Selection Bits [7:0] bit 4 position. */ -#define USART_BSEL5_bm (1<<5) /* Baud Rate Selection Bits [7:0] bit 5 mask. */ -#define USART_BSEL5_bp 5 /* Baud Rate Selection Bits [7:0] bit 5 position. */ -#define USART_BSEL6_bm (1<<6) /* Baud Rate Selection Bits [7:0] bit 6 mask. */ -#define USART_BSEL6_bp 6 /* Baud Rate Selection Bits [7:0] bit 6 position. */ -#define USART_BSEL7_bm (1<<7) /* Baud Rate Selection Bits [7:0] bit 7 mask. */ -#define USART_BSEL7_bp 7 /* Baud Rate Selection Bits [7:0] bit 7 position. */ - -/* USART.BAUDCTRLB bit masks and bit positions */ -#define USART_BSCALE_gm 0xF0 /* Baud Rate Scale group mask. */ -#define USART_BSCALE_gp 4 /* Baud Rate Scale group position. */ -#define USART_BSCALE0_bm (1<<4) /* Baud Rate Scale bit 0 mask. */ -#define USART_BSCALE0_bp 4 /* Baud Rate Scale bit 0 position. */ -#define USART_BSCALE1_bm (1<<5) /* Baud Rate Scale bit 1 mask. */ -#define USART_BSCALE1_bp 5 /* Baud Rate Scale bit 1 position. */ -#define USART_BSCALE2_bm (1<<6) /* Baud Rate Scale bit 2 mask. */ -#define USART_BSCALE2_bp 6 /* Baud Rate Scale bit 2 position. */ -#define USART_BSCALE3_bm (1<<7) /* Baud Rate Scale bit 3 mask. */ -#define USART_BSCALE3_bp 7 /* Baud Rate Scale bit 3 position. */ - -/* USART_BSEL Predefined. */ -/* USART_BSEL Predefined. */ - -/* SPI - Serial Peripheral Interface */ -/* SPI.CTRL bit masks and bit positions */ -#define SPI_CLK2X_bm 0x80 /* Enable Double Speed bit mask. */ -#define SPI_CLK2X_bp 7 /* Enable Double Speed bit position. */ - -#define SPI_ENABLE_bm 0x40 /* Enable Module bit mask. */ -#define SPI_ENABLE_bp 6 /* Enable Module bit position. */ - -#define SPI_DORD_bm 0x20 /* Data Order Setting bit mask. */ -#define SPI_DORD_bp 5 /* Data Order Setting bit position. */ - -#define SPI_MASTER_bm 0x10 /* Master Operation Enable bit mask. */ -#define SPI_MASTER_bp 4 /* Master Operation Enable bit position. */ - -#define SPI_MODE_gm 0x0C /* SPI Mode group mask. */ -#define SPI_MODE_gp 2 /* SPI Mode group position. */ -#define SPI_MODE0_bm (1<<2) /* SPI Mode bit 0 mask. */ -#define SPI_MODE0_bp 2 /* SPI Mode bit 0 position. */ -#define SPI_MODE1_bm (1<<3) /* SPI Mode bit 1 mask. */ -#define SPI_MODE1_bp 3 /* SPI Mode bit 1 position. */ - -#define SPI_PRESCALER_gm 0x03 /* Prescaler group mask. */ -#define SPI_PRESCALER_gp 0 /* Prescaler group position. */ -#define SPI_PRESCALER0_bm (1<<0) /* Prescaler bit 0 mask. */ -#define SPI_PRESCALER0_bp 0 /* Prescaler bit 0 position. */ -#define SPI_PRESCALER1_bm (1<<1) /* Prescaler bit 1 mask. */ -#define SPI_PRESCALER1_bp 1 /* Prescaler bit 1 position. */ - -/* SPI.INTCTRL bit masks and bit positions */ -#define SPI_INTLVL_gm 0x03 /* Interrupt level group mask. */ -#define SPI_INTLVL_gp 0 /* Interrupt level group position. */ -#define SPI_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */ -#define SPI_INTLVL0_bp 0 /* Interrupt level bit 0 position. */ -#define SPI_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */ -#define SPI_INTLVL1_bp 1 /* Interrupt level bit 1 position. */ - -/* SPI.STATUS bit masks and bit positions */ -#define SPI_IF_bm 0x80 /* Interrupt Flag bit mask. */ -#define SPI_IF_bp 7 /* Interrupt Flag bit position. */ - -#define SPI_WRCOL_bm 0x40 /* Write Collision bit mask. */ -#define SPI_WRCOL_bp 6 /* Write Collision bit position. */ - -/* IRCOM - IR Communication Module */ -/* IRCOM.CTRL bit masks and bit positions */ -#define IRCOM_EVSEL_gm 0x0F /* Event Channel Select group mask. */ -#define IRCOM_EVSEL_gp 0 /* Event Channel Select group position. */ -#define IRCOM_EVSEL0_bm (1<<0) /* Event Channel Select bit 0 mask. */ -#define IRCOM_EVSEL0_bp 0 /* Event Channel Select bit 0 position. */ -#define IRCOM_EVSEL1_bm (1<<1) /* Event Channel Select bit 1 mask. */ -#define IRCOM_EVSEL1_bp 1 /* Event Channel Select bit 1 position. */ -#define IRCOM_EVSEL2_bm (1<<2) /* Event Channel Select bit 2 mask. */ -#define IRCOM_EVSEL2_bp 2 /* Event Channel Select bit 2 position. */ -#define IRCOM_EVSEL3_bm (1<<3) /* Event Channel Select bit 3 mask. */ -#define IRCOM_EVSEL3_bp 3 /* Event Channel Select bit 3 position. */ - -/* FUSE - Fuses and Lockbits */ -/* NVM_FUSES.FUSEBYTE1 bit masks and bit positions */ -#define NVM_FUSES_WDWP_gm 0xF0 /* Watchdog Window Timeout Period group mask. */ -#define NVM_FUSES_WDWP_gp 4 /* Watchdog Window Timeout Period group position. */ -#define NVM_FUSES_WDWP0_bm (1<<4) /* Watchdog Window Timeout Period bit 0 mask. */ -#define NVM_FUSES_WDWP0_bp 4 /* Watchdog Window Timeout Period bit 0 position. */ -#define NVM_FUSES_WDWP1_bm (1<<5) /* Watchdog Window Timeout Period bit 1 mask. */ -#define NVM_FUSES_WDWP1_bp 5 /* Watchdog Window Timeout Period bit 1 position. */ -#define NVM_FUSES_WDWP2_bm (1<<6) /* Watchdog Window Timeout Period bit 2 mask. */ -#define NVM_FUSES_WDWP2_bp 6 /* Watchdog Window Timeout Period bit 2 position. */ -#define NVM_FUSES_WDWP3_bm (1<<7) /* Watchdog Window Timeout Period bit 3 mask. */ -#define NVM_FUSES_WDWP3_bp 7 /* Watchdog Window Timeout Period bit 3 position. */ - -#define NVM_FUSES_WDP_gm 0x0F /* Watchdog Timeout Period group mask. */ -#define NVM_FUSES_WDP_gp 0 /* Watchdog Timeout Period group position. */ -#define NVM_FUSES_WDP0_bm (1<<0) /* Watchdog Timeout Period bit 0 mask. */ -#define NVM_FUSES_WDP0_bp 0 /* Watchdog Timeout Period bit 0 position. */ -#define NVM_FUSES_WDP1_bm (1<<1) /* Watchdog Timeout Period bit 1 mask. */ -#define NVM_FUSES_WDP1_bp 1 /* Watchdog Timeout Period bit 1 position. */ -#define NVM_FUSES_WDP2_bm (1<<2) /* Watchdog Timeout Period bit 2 mask. */ -#define NVM_FUSES_WDP2_bp 2 /* Watchdog Timeout Period bit 2 position. */ -#define NVM_FUSES_WDP3_bm (1<<3) /* Watchdog Timeout Period bit 3 mask. */ -#define NVM_FUSES_WDP3_bp 3 /* Watchdog Timeout Period bit 3 position. */ - -/* NVM_FUSES.FUSEBYTE2 bit masks and bit positions */ -#define NVM_FUSES_BOOTRST_bm 0x40 /* Boot Loader Section Reset Vector bit mask. */ -#define NVM_FUSES_BOOTRST_bp 6 /* Boot Loader Section Reset Vector bit position. */ - -#define NVM_FUSES_TOSCSEL_bm 0x20 /* Timer Oscillator pin location bit mask. */ -#define NVM_FUSES_TOSCSEL_bp 5 /* Timer Oscillator pin location bit position. */ - -#define NVM_FUSES_BODPD_gm 0x03 /* BOD Operation in Power-Down Mode group mask. */ -#define NVM_FUSES_BODPD_gp 0 /* BOD Operation in Power-Down Mode group position. */ -#define NVM_FUSES_BODPD0_bm (1<<0) /* BOD Operation in Power-Down Mode bit 0 mask. */ -#define NVM_FUSES_BODPD0_bp 0 /* BOD Operation in Power-Down Mode bit 0 position. */ -#define NVM_FUSES_BODPD1_bm (1<<1) /* BOD Operation in Power-Down Mode bit 1 mask. */ -#define NVM_FUSES_BODPD1_bp 1 /* BOD Operation in Power-Down Mode bit 1 position. */ - -/* NVM_FUSES.FUSEBYTE4 bit masks and bit positions */ -#define NVM_FUSES_RSTDISBL_bm 0x10 /* External Reset Disable bit mask. */ -#define NVM_FUSES_RSTDISBL_bp 4 /* External Reset Disable bit position. */ - -#define NVM_FUSES_SUT_gm 0x0C /* Start-up Time group mask. */ -#define NVM_FUSES_SUT_gp 2 /* Start-up Time group position. */ -#define NVM_FUSES_SUT0_bm (1<<2) /* Start-up Time bit 0 mask. */ -#define NVM_FUSES_SUT0_bp 2 /* Start-up Time bit 0 position. */ -#define NVM_FUSES_SUT1_bm (1<<3) /* Start-up Time bit 1 mask. */ -#define NVM_FUSES_SUT1_bp 3 /* Start-up Time bit 1 position. */ - -#define NVM_FUSES_WDLOCK_bm 0x02 /* Watchdog Timer Lock bit mask. */ -#define NVM_FUSES_WDLOCK_bp 1 /* Watchdog Timer Lock bit position. */ - -/* NVM_FUSES.FUSEBYTE5 bit masks and bit positions */ -#define NVM_FUSES_BODACT_gm 0x30 /* BOD Operation in Active Mode group mask. */ -#define NVM_FUSES_BODACT_gp 4 /* BOD Operation in Active Mode group position. */ -#define NVM_FUSES_BODACT0_bm (1<<4) /* BOD Operation in Active Mode bit 0 mask. */ -#define NVM_FUSES_BODACT0_bp 4 /* BOD Operation in Active Mode bit 0 position. */ -#define NVM_FUSES_BODACT1_bm (1<<5) /* BOD Operation in Active Mode bit 1 mask. */ -#define NVM_FUSES_BODACT1_bp 5 /* BOD Operation in Active Mode bit 1 position. */ - -#define NVM_FUSES_EESAVE_bm 0x08 /* Preserve EEPROM Through Chip Erase bit mask. */ -#define NVM_FUSES_EESAVE_bp 3 /* Preserve EEPROM Through Chip Erase bit position. */ - -#define NVM_FUSES_BODLVL_gm 0x07 /* Brownout Detection Voltage Level group mask. */ -#define NVM_FUSES_BODLVL_gp 0 /* Brownout Detection Voltage Level group position. */ -#define NVM_FUSES_BODLVL0_bm (1<<0) /* Brownout Detection Voltage Level bit 0 mask. */ -#define NVM_FUSES_BODLVL0_bp 0 /* Brownout Detection Voltage Level bit 0 position. */ -#define NVM_FUSES_BODLVL1_bm (1<<1) /* Brownout Detection Voltage Level bit 1 mask. */ -#define NVM_FUSES_BODLVL1_bp 1 /* Brownout Detection Voltage Level bit 1 position. */ -#define NVM_FUSES_BODLVL2_bm (1<<2) /* Brownout Detection Voltage Level bit 2 mask. */ -#define NVM_FUSES_BODLVL2_bp 2 /* Brownout Detection Voltage Level bit 2 position. */ - -/* LOCKBIT - Fuses and Lockbits */ -/* NVM_LOCKBITS.LOCKBITS bit masks and bit positions */ -#define NVM_LOCKBITS_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ -#define NVM_LOCKBITS_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ -#define NVM_LOCKBITS_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ -#define NVM_LOCKBITS_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ -#define NVM_LOCKBITS_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ -#define NVM_LOCKBITS_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ - -#define NVM_LOCKBITS_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ -#define NVM_LOCKBITS_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ -#define NVM_LOCKBITS_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ -#define NVM_LOCKBITS_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ -#define NVM_LOCKBITS_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ -#define NVM_LOCKBITS_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ - -#define NVM_LOCKBITS_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ -#define NVM_LOCKBITS_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ -#define NVM_LOCKBITS_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ -#define NVM_LOCKBITS_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ -#define NVM_LOCKBITS_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ -#define NVM_LOCKBITS_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ - -#define NVM_LOCKBITS_LB_gm 0x03 /* Lock Bits group mask. */ -#define NVM_LOCKBITS_LB_gp 0 /* Lock Bits group position. */ -#define NVM_LOCKBITS_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ -#define NVM_LOCKBITS_LB0_bp 0 /* Lock Bits bit 0 position. */ -#define NVM_LOCKBITS_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ -#define NVM_LOCKBITS_LB1_bp 1 /* Lock Bits bit 1 position. */ - - - -// Generic Port Pins - -#define PIN0_bm 0x01 -#define PIN0_bp 0 -#define PIN1_bm 0x02 -#define PIN1_bp 1 -#define PIN2_bm 0x04 -#define PIN2_bp 2 -#define PIN3_bm 0x08 -#define PIN3_bp 3 -#define PIN4_bm 0x10 -#define PIN4_bp 4 -#define PIN5_bm 0x20 -#define PIN5_bp 5 -#define PIN6_bm 0x40 -#define PIN6_bp 6 -#define PIN7_bm 0x80 -#define PIN7_bp 7 - -/* ========== Interrupt Vector Definitions ========== */ -/* Vector 0 is the reset vector */ - -/* OSC interrupt vectors */ -#define OSC_OSCF_vect_num 1 -#define OSC_OSCF_vect _VECTOR(1) /* Oscillator Failure Interrupt (NMI) */ - -/* PORTC interrupt vectors */ -#define PORTC_INT0_vect_num 2 -#define PORTC_INT0_vect _VECTOR(2) /* External Interrupt 0 */ -#define PORTC_INT1_vect_num 3 -#define PORTC_INT1_vect _VECTOR(3) /* External Interrupt 1 */ - -/* PORTR interrupt vectors */ -#define PORTR_INT0_vect_num 4 -#define PORTR_INT0_vect _VECTOR(4) /* External Interrupt 0 */ -#define PORTR_INT1_vect_num 5 -#define PORTR_INT1_vect _VECTOR(5) /* External Interrupt 1 */ - -/* RTC interrupt vectors */ -#define RTC_OVF_vect_num 10 -#define RTC_OVF_vect _VECTOR(10) /* Overflow Interrupt */ -#define RTC_COMP_vect_num 11 -#define RTC_COMP_vect _VECTOR(11) /* Compare Interrupt */ - -/* TWIC interrupt vectors */ -#define TWIC_TWIS_vect_num 12 -#define TWIC_TWIS_vect _VECTOR(12) /* TWI Slave Interrupt */ -#define TWIC_TWIM_vect_num 13 -#define TWIC_TWIM_vect _VECTOR(13) /* TWI Master Interrupt */ - -/* TCC0 interrupt vectors */ -#define TCC0_OVF_vect_num 14 -#define TCC0_OVF_vect _VECTOR(14) /* Overflow Interrupt */ - -/* TCC2 interrupt vectors */ -#define TCC2_LUNF_vect_num 14 -#define TCC2_LUNF_vect _VECTOR(14) /* Low Byte Underflow Interrupt */ - -/* TCC0 interrupt vectors */ -#define TCC0_ERR_vect_num 15 -#define TCC0_ERR_vect _VECTOR(15) /* Error Interrupt */ - -/* TCC2 interrupt vectors */ -#define TCC2_HUNF_vect_num 15 -#define TCC2_HUNF_vect _VECTOR(15) /* High Byte Underflow Interrupt */ - -/* TCC0 interrupt vectors */ -#define TCC0_CCA_vect_num 16 -#define TCC0_CCA_vect _VECTOR(16) /* Compare or Capture A Interrupt */ - -/* TCC2 interrupt vectors */ -#define TCC2_LCMPA_vect_num 16 -#define TCC2_LCMPA_vect _VECTOR(16) /* Low Byte Compare A Interrupt */ - -/* TCC0 interrupt vectors */ -#define TCC0_CCB_vect_num 17 -#define TCC0_CCB_vect _VECTOR(17) /* Compare or Capture B Interrupt */ - -/* TCC2 interrupt vectors */ -#define TCC2_LCMPB_vect_num 17 -#define TCC2_LCMPB_vect _VECTOR(17) /* Low Byte Compare B Interrupt */ - -/* TCC0 interrupt vectors */ -#define TCC0_CCC_vect_num 18 -#define TCC0_CCC_vect _VECTOR(18) /* Compare or Capture C Interrupt */ - -/* TCC2 interrupt vectors */ -#define TCC2_LCMPC_vect_num 18 -#define TCC2_LCMPC_vect _VECTOR(18) /* Low Byte Compare C Interrupt */ - -/* TCC0 interrupt vectors */ -#define TCC0_CCD_vect_num 19 -#define TCC0_CCD_vect _VECTOR(19) /* Compare or Capture D Interrupt */ - -/* TCC2 interrupt vectors */ -#define TCC2_LCMPD_vect_num 19 -#define TCC2_LCMPD_vect _VECTOR(19) /* Low Byte Compare D Interrupt */ - -/* TCC1 interrupt vectors */ -#define TCC1_OVF_vect_num 20 -#define TCC1_OVF_vect _VECTOR(20) /* Overflow Interrupt */ -#define TCC1_ERR_vect_num 21 -#define TCC1_ERR_vect _VECTOR(21) /* Error Interrupt */ -#define TCC1_CCA_vect_num 22 -#define TCC1_CCA_vect _VECTOR(22) /* Compare or Capture A Interrupt */ -#define TCC1_CCB_vect_num 23 -#define TCC1_CCB_vect _VECTOR(23) /* Compare or Capture B Interrupt */ - -/* SPIC interrupt vectors */ -#define SPIC_INT_vect_num 24 -#define SPIC_INT_vect _VECTOR(24) /* SPI Interrupt */ - -/* USARTC0 interrupt vectors */ -#define USARTC0_RXC_vect_num 25 -#define USARTC0_RXC_vect _VECTOR(25) /* Reception Complete Interrupt */ -#define USARTC0_DRE_vect_num 26 -#define USARTC0_DRE_vect _VECTOR(26) /* Data Register Empty Interrupt */ -#define USARTC0_TXC_vect_num 27 -#define USARTC0_TXC_vect _VECTOR(27) /* Transmission Complete Interrupt */ - -/* NVM interrupt vectors */ -#define NVM_EE_vect_num 32 -#define NVM_EE_vect _VECTOR(32) /* EE Interrupt */ -#define NVM_SPM_vect_num 33 -#define NVM_SPM_vect _VECTOR(33) /* SPM Interrupt */ - -/* PORTB interrupt vectors */ -#define PORTB_INT0_vect_num 34 -#define PORTB_INT0_vect _VECTOR(34) /* External Interrupt 0 */ -#define PORTB_INT1_vect_num 35 -#define PORTB_INT1_vect _VECTOR(35) /* External Interrupt 1 */ - -/* PORTE interrupt vectors */ -#define PORTE_INT0_vect_num 43 -#define PORTE_INT0_vect _VECTOR(43) /* External Interrupt 0 */ -#define PORTE_INT1_vect_num 44 -#define PORTE_INT1_vect _VECTOR(44) /* External Interrupt 1 */ - -/* TWIE interrupt vectors */ -#define TWIE_TWIS_vect_num 45 -#define TWIE_TWIS_vect _VECTOR(45) /* TWI Slave Interrupt */ -#define TWIE_TWIM_vect_num 46 -#define TWIE_TWIM_vect _VECTOR(46) /* TWI Master Interrupt */ - -/* TCE0 interrupt vectors */ -#define TCE0_OVF_vect_num 47 -#define TCE0_OVF_vect _VECTOR(47) /* Overflow Interrupt */ - -/* TCE2 interrupt vectors */ -#define TCE2_LUNF_vect_num 47 -#define TCE2_LUNF_vect _VECTOR(47) /* Low Byte Underflow Interrupt */ - -/* TCE0 interrupt vectors */ -#define TCE0_ERR_vect_num 48 -#define TCE0_ERR_vect _VECTOR(48) /* Error Interrupt */ - -/* TCE2 interrupt vectors */ -#define TCE2_HUNF_vect_num 48 -#define TCE2_HUNF_vect _VECTOR(48) /* High Byte Underflow Interrupt */ - -/* TCE0 interrupt vectors */ -#define TCE0_CCA_vect_num 49 -#define TCE0_CCA_vect _VECTOR(49) /* Compare or Capture A Interrupt */ - -/* TCE2 interrupt vectors */ -#define TCE2_LCMPA_vect_num 49 -#define TCE2_LCMPA_vect _VECTOR(49) /* Low Byte Compare A Interrupt */ - -/* TCE0 interrupt vectors */ -#define TCE0_CCB_vect_num 50 -#define TCE0_CCB_vect _VECTOR(50) /* Compare or Capture B Interrupt */ - -/* TCE2 interrupt vectors */ -#define TCE2_LCMPB_vect_num 50 -#define TCE2_LCMPB_vect _VECTOR(50) /* Low Byte Compare B Interrupt */ - -/* TCE0 interrupt vectors */ -#define TCE0_CCC_vect_num 51 -#define TCE0_CCC_vect _VECTOR(51) /* Compare or Capture C Interrupt */ - -/* TCE2 interrupt vectors */ -#define TCE2_LCMPC_vect_num 51 -#define TCE2_LCMPC_vect _VECTOR(51) /* Low Byte Compare C Interrupt */ - -/* TCE0 interrupt vectors */ -#define TCE0_CCD_vect_num 52 -#define TCE0_CCD_vect _VECTOR(52) /* Compare or Capture D Interrupt */ - -/* TCE2 interrupt vectors */ -#define TCE2_LCMPD_vect_num 52 -#define TCE2_LCMPD_vect _VECTOR(52) /* Low Byte Compare D Interrupt */ - -/* USARTE0 interrupt vectors */ -#define USARTE0_RXC_vect_num 58 -#define USARTE0_RXC_vect _VECTOR(58) /* Reception Complete Interrupt */ -#define USARTE0_DRE_vect_num 59 -#define USARTE0_DRE_vect _VECTOR(59) /* Data Register Empty Interrupt */ -#define USARTE0_TXC_vect_num 60 -#define USARTE0_TXC_vect _VECTOR(60) /* Transmission Complete Interrupt */ - -/* PORTD interrupt vectors */ -#define PORTD_INT0_vect_num 64 -#define PORTD_INT0_vect _VECTOR(64) /* External Interrupt 0 */ -#define PORTD_INT1_vect_num 65 -#define PORTD_INT1_vect _VECTOR(65) /* External Interrupt 1 */ - -/* PORTA interrupt vectors */ -#define PORTA_INT0_vect_num 66 -#define PORTA_INT0_vect _VECTOR(66) /* External Interrupt 0 */ -#define PORTA_INT1_vect_num 67 -#define PORTA_INT1_vect _VECTOR(67) /* External Interrupt 1 */ - -/* ACA interrupt vectors */ -#define ACA_AC0_vect_num 68 -#define ACA_AC0_vect _VECTOR(68) /* AC0 Interrupt */ -#define ACA_AC1_vect_num 69 -#define ACA_AC1_vect _VECTOR(69) /* AC1 Interrupt */ -#define ACA_ACW_vect_num 70 -#define ACA_ACW_vect _VECTOR(70) /* ACW Window Mode Interrupt */ - -/* ADCA interrupt vectors */ -#define ADCA_CH0_vect_num 71 -#define ADCA_CH0_vect _VECTOR(71) /* Interrupt 0 */ - -/* TCD0 interrupt vectors */ -#define TCD0_OVF_vect_num 77 -#define TCD0_OVF_vect _VECTOR(77) /* Overflow Interrupt */ - -/* TCD2 interrupt vectors */ -#define TCD2_LUNF_vect_num 77 -#define TCD2_LUNF_vect _VECTOR(77) /* Low Byte Underflow Interrupt */ - -/* TCD0 interrupt vectors */ -#define TCD0_ERR_vect_num 78 -#define TCD0_ERR_vect _VECTOR(78) /* Error Interrupt */ - -/* TCD2 interrupt vectors */ -#define TCD2_HUNF_vect_num 78 -#define TCD2_HUNF_vect _VECTOR(78) /* High Byte Underflow Interrupt */ - -/* TCD0 interrupt vectors */ -#define TCD0_CCA_vect_num 79 -#define TCD0_CCA_vect _VECTOR(79) /* Compare or Capture A Interrupt */ - -/* TCD2 interrupt vectors */ -#define TCD2_LCMPA_vect_num 79 -#define TCD2_LCMPA_vect _VECTOR(79) /* Low Byte Compare A Interrupt */ - -/* TCD0 interrupt vectors */ -#define TCD0_CCB_vect_num 80 -#define TCD0_CCB_vect _VECTOR(80) /* Compare or Capture B Interrupt */ - -/* TCD2 interrupt vectors */ -#define TCD2_LCMPB_vect_num 80 -#define TCD2_LCMPB_vect _VECTOR(80) /* Low Byte Compare B Interrupt */ - -/* TCD0 interrupt vectors */ -#define TCD0_CCC_vect_num 81 -#define TCD0_CCC_vect _VECTOR(81) /* Compare or Capture C Interrupt */ - -/* TCD2 interrupt vectors */ -#define TCD2_LCMPC_vect_num 81 -#define TCD2_LCMPC_vect _VECTOR(81) /* Low Byte Compare C Interrupt */ - -/* TCD0 interrupt vectors */ -#define TCD0_CCD_vect_num 82 -#define TCD0_CCD_vect _VECTOR(82) /* Compare or Capture D Interrupt */ - -/* TCD2 interrupt vectors */ -#define TCD2_LCMPD_vect_num 82 -#define TCD2_LCMPD_vect _VECTOR(82) /* Low Byte Compare D Interrupt */ - -/* SPID interrupt vectors */ -#define SPID_INT_vect_num 87 -#define SPID_INT_vect _VECTOR(87) /* SPI Interrupt */ - -/* USARTD0 interrupt vectors */ -#define USARTD0_RXC_vect_num 88 -#define USARTD0_RXC_vect _VECTOR(88) /* Reception Complete Interrupt */ -#define USARTD0_DRE_vect_num 89 -#define USARTD0_DRE_vect _VECTOR(89) /* Data Register Empty Interrupt */ -#define USARTD0_TXC_vect_num 90 -#define USARTD0_TXC_vect _VECTOR(90) /* Transmission Complete Interrupt */ - -/* PORTF interrupt vectors */ -#define PORTF_INT0_vect_num 104 -#define PORTF_INT0_vect _VECTOR(104) /* External Interrupt 0 */ -#define PORTF_INT1_vect_num 105 -#define PORTF_INT1_vect _VECTOR(105) /* External Interrupt 1 */ - -/* TCF0 interrupt vectors */ -#define TCF0_OVF_vect_num 108 -#define TCF0_OVF_vect _VECTOR(108) /* Overflow Interrupt */ - -/* TCF2 interrupt vectors */ -#define TCF2_LUNF_vect_num 108 -#define TCF2_LUNF_vect _VECTOR(108) /* Low Byte Underflow Interrupt */ - -/* TCF0 interrupt vectors */ -#define TCF0_ERR_vect_num 109 -#define TCF0_ERR_vect _VECTOR(109) /* Error Interrupt */ - -/* TCF2 interrupt vectors */ -#define TCF2_HUNF_vect_num 109 -#define TCF2_HUNF_vect _VECTOR(109) /* High Byte Underflow Interrupt */ - -/* TCF0 interrupt vectors */ -#define TCF0_CCA_vect_num 110 -#define TCF0_CCA_vect _VECTOR(110) /* Compare or Capture A Interrupt */ - -/* TCF2 interrupt vectors */ -#define TCF2_LCMPA_vect_num 110 -#define TCF2_LCMPA_vect _VECTOR(110) /* Low Byte Compare A Interrupt */ - -/* TCF0 interrupt vectors */ -#define TCF0_CCB_vect_num 111 -#define TCF0_CCB_vect _VECTOR(111) /* Compare or Capture B Interrupt */ - -/* TCF2 interrupt vectors */ -#define TCF2_LCMPB_vect_num 111 -#define TCF2_LCMPB_vect _VECTOR(111) /* Low Byte Compare B Interrupt */ - -/* TCF0 interrupt vectors */ -#define TCF0_CCC_vect_num 112 -#define TCF0_CCC_vect _VECTOR(112) /* Compare or Capture C Interrupt */ - -/* TCF2 interrupt vectors */ -#define TCF2_LCMPC_vect_num 112 -#define TCF2_LCMPC_vect _VECTOR(112) /* Low Byte Compare C Interrupt */ - -/* TCF0 interrupt vectors */ -#define TCF0_CCD_vect_num 113 -#define TCF0_CCD_vect _VECTOR(113) /* Compare or Capture D Interrupt */ - -/* TCF2 interrupt vectors */ -#define TCF2_LCMPD_vect_num 113 -#define TCF2_LCMPD_vect _VECTOR(113) /* Low Byte Compare D Interrupt */ - -/* USB interrupt vectors */ -#define USB_BUSEVENT_vect_num 125 -#define USB_BUSEVENT_vect _VECTOR(125) /* SOF, suspend, resume, reset bus event interrupts, crc, underflow, overflow and stall error interrupts */ -#define USB_TRNCOMPL_vect_num 126 -#define USB_TRNCOMPL_vect _VECTOR(126) /* Transaction complete interrupt */ - -#define _VECTOR_SIZE 4 /* Size of individual vector. */ -#define _VECTORS_SIZE (127 * _VECTOR_SIZE) - - -/* ========== Constants ========== */ - -#define PROGMEM_START (0x0000) -#define PROGMEM_SIZE (204800) -#define PROGMEM_END (PROGMEM_START + PROGMEM_SIZE - 1) - -#define APP_SECTION_START (0x0000) -#define APP_SECTION_SIZE (196608) -#define APP_SECTION_PAGE_SIZE (512) -#define APP_SECTION_END (APP_SECTION_START + APP_SECTION_SIZE - 1) - -#define APPTABLE_SECTION_START (0x2E000) -#define APPTABLE_SECTION_SIZE (8192) -#define APPTABLE_SECTION_PAGE_SIZE (512) -#define APPTABLE_SECTION_END (APPTABLE_SECTION_START + APPTABLE_SECTION_SIZE - 1) - -#define BOOT_SECTION_START (0x30000) -#define BOOT_SECTION_SIZE (8192) -#define BOOT_SECTION_PAGE_SIZE (512) -#define BOOT_SECTION_END (BOOT_SECTION_START + BOOT_SECTION_SIZE - 1) - -#define DATAMEM_START (0x0000) -#define DATAMEM_SIZE (16384) -#define DATAMEM_END (DATAMEM_START + DATAMEM_SIZE - 1) - -#define IO_START (0x0000) -#define IO_SIZE (4096) -#define IO_PAGE_SIZE (0) -#define IO_END (IO_START + IO_SIZE - 1) - -#define MAPPED_EEPROM_START (0x1000) -#define MAPPED_EEPROM_SIZE (2048) -#define MAPPED_EEPROM_PAGE_SIZE (0) -#define MAPPED_EEPROM_END (MAPPED_EEPROM_START + MAPPED_EEPROM_SIZE - 1) - -#define INTERNAL_SRAM_START (0x2000) -#define INTERNAL_SRAM_SIZE (16384) -#define INTERNAL_SRAM_PAGE_SIZE (0) -#define INTERNAL_SRAM_END (INTERNAL_SRAM_START + INTERNAL_SRAM_SIZE - 1) - -#define EEPROM_START (0x0000) -#define EEPROM_SIZE (2048) -#define EEPROM_PAGE_SIZE (32) -#define EEPROM_END (EEPROM_START + EEPROM_SIZE - 1) - -#define SIGNATURES_START (0x0000) -#define SIGNATURES_SIZE (3) -#define SIGNATURES_PAGE_SIZE (0) -#define SIGNATURES_END (SIGNATURES_START + SIGNATURES_SIZE - 1) - -#define FUSES_START (0x0000) -#define FUSES_SIZE (6) -#define FUSES_PAGE_SIZE (0) -#define FUSES_END (FUSES_START + FUSES_SIZE - 1) - -#define LOCKBITS_START (0x0000) -#define LOCKBITS_SIZE (1) -#define LOCKBITS_PAGE_SIZE (0) -#define LOCKBITS_END (LOCKBITS_START + LOCKBITS_SIZE - 1) - -#define USER_SIGNATURES_START (0x0000) -#define USER_SIGNATURES_SIZE (512) -#define USER_SIGNATURES_PAGE_SIZE (512) -#define USER_SIGNATURES_END (USER_SIGNATURES_START + USER_SIGNATURES_SIZE - 1) - -#define PROD_SIGNATURES_START (0x0000) -#define PROD_SIGNATURES_SIZE (64) -#define PROD_SIGNATURES_PAGE_SIZE (512) -#define PROD_SIGNATURES_END (PROD_SIGNATURES_START + PROD_SIGNATURES_SIZE - 1) - -#define FLASHSTART PROGMEM_START -#define FLASHEND PROGMEM_END -#define SPM_PAGESIZE 512 -#define RAMSTART INTERNAL_SRAM_START -#define RAMSIZE INTERNAL_SRAM_SIZE -#define RAMEND INTERNAL_SRAM_END -#define E2END EEPROM_END -#define E2PAGESIZE EEPROM_PAGE_SIZE - - -/* ========== Fuses ========== */ -#define FUSE_MEMORY_SIZE 6 - -/* Fuse Byte 0 Reserved */ - -/* Fuse Byte 1 */ -#define FUSE_WDP0 (unsigned char)~_BV(0) /* Watchdog Timeout Period Bit 0 */ -#define FUSE_WDP1 (unsigned char)~_BV(1) /* Watchdog Timeout Period Bit 1 */ -#define FUSE_WDP2 (unsigned char)~_BV(2) /* Watchdog Timeout Period Bit 2 */ -#define FUSE_WDP3 (unsigned char)~_BV(3) /* Watchdog Timeout Period Bit 3 */ -#define FUSE_WDWP0 (unsigned char)~_BV(4) /* Watchdog Window Timeout Period Bit 0 */ -#define FUSE_WDWP1 (unsigned char)~_BV(5) /* Watchdog Window Timeout Period Bit 1 */ -#define FUSE_WDWP2 (unsigned char)~_BV(6) /* Watchdog Window Timeout Period Bit 2 */ -#define FUSE_WDWP3 (unsigned char)~_BV(7) /* Watchdog Window Timeout Period Bit 3 */ -#define FUSE1_DEFAULT (0xFF) - -/* Fuse Byte 2 */ -#define FUSE_BODPD0 (unsigned char)~_BV(0) /* BOD Operation in Power-Down Mode Bit 0 */ -#define FUSE_BODPD1 (unsigned char)~_BV(1) /* BOD Operation in Power-Down Mode Bit 1 */ -#define FUSE_TOSCSEL (unsigned char)~_BV(5) /* Timer Oscillator pin location */ -#define FUSE_BOOTRST (unsigned char)~_BV(6) /* Boot Loader Section Reset Vector */ -#define FUSE2_DEFAULT (0xFF) - -/* Fuse Byte 3 Reserved */ - -/* Fuse Byte 4 */ -#define FUSE_WDLOCK (unsigned char)~_BV(1) /* Watchdog Timer Lock */ -#define FUSE_SUT0 (unsigned char)~_BV(2) /* Start-up Time Bit 0 */ -#define FUSE_SUT1 (unsigned char)~_BV(3) /* Start-up Time Bit 1 */ -#define FUSE_RSTDISBL (unsigned char)~_BV(4) /* External Reset Disable */ -#define FUSE4_DEFAULT (0xFF) - -/* Fuse Byte 5 */ -#define FUSE_BODLVL0 (unsigned char)~_BV(0) /* Brownout Detection Voltage Level Bit 0 */ -#define FUSE_BODLVL1 (unsigned char)~_BV(1) /* Brownout Detection Voltage Level Bit 1 */ -#define FUSE_BODLVL2 (unsigned char)~_BV(2) /* Brownout Detection Voltage Level Bit 2 */ -#define FUSE_EESAVE (unsigned char)~_BV(3) /* Preserve EEPROM Through Chip Erase */ -#define FUSE_BODACT0 (unsigned char)~_BV(4) /* BOD Operation in Active Mode Bit 0 */ -#define FUSE_BODACT1 (unsigned char)~_BV(5) /* BOD Operation in Active Mode Bit 1 */ -#define FUSE5_DEFAULT (0xFF) - -/* ========== Lock Bits ========== */ -#define __LOCK_BITS_EXIST -#define __BOOT_LOCK_APPLICATION_TABLE_BITS_EXIST -#define __BOOT_LOCK_APPLICATION_BITS_EXIST -#define __BOOT_LOCK_BOOT_BITS_EXIST - -/* ========== Signature ========== */ -#define SIGNATURE_0 0x1E -#define SIGNATURE_1 0x97 -#define SIGNATURE_2 0x51 - -/* ========== Power Reduction Condition Definitions ========== */ - -/* PR.PRGEN */ -#define __AVR_HAVE_PRGEN (PR_USB_bm|PR_AES_bm|PR_RTC_bm|PR_EVSYS_bm|PR_DMA_bm) -#define __AVR_HAVE_PRGEN_USB -#define __AVR_HAVE_PRGEN_AES -#define __AVR_HAVE_PRGEN_RTC -#define __AVR_HAVE_PRGEN_EVSYS -#define __AVR_HAVE_PRGEN_DMA - -/* PR.PRPA */ -#define __AVR_HAVE_PRPA (PR_ADC_bm|PR_AC_bm) -#define __AVR_HAVE_PRPA_ADC -#define __AVR_HAVE_PRPA_AC - -/* PR.PRPC */ -#define __AVR_HAVE_PRPC (PR_TWI_bm|PR_USART1_bm|PR_USART0_bm|PR_SPI_bm|PR_HIRES_bm|PR_TC1_bm|PR_TC0_bm) -#define __AVR_HAVE_PRPC_TWI -#define __AVR_HAVE_PRPC_USART1 -#define __AVR_HAVE_PRPC_USART0 -#define __AVR_HAVE_PRPC_SPI -#define __AVR_HAVE_PRPC_HIRES -#define __AVR_HAVE_PRPC_TC1 -#define __AVR_HAVE_PRPC_TC0 - -/* PR.PRPD */ -#define __AVR_HAVE_PRPD (PR_USART0_bm|PR_SPI_bm|PR_TC0_bm) -#define __AVR_HAVE_PRPD_USART0 -#define __AVR_HAVE_PRPD_SPI -#define __AVR_HAVE_PRPD_TC0 - -/* PR.PRPE */ -#define __AVR_HAVE_PRPE (PR_TWI_bm|PR_USART0_bm|PR_TC0_bm) -#define __AVR_HAVE_PRPE_TWI -#define __AVR_HAVE_PRPE_USART0 -#define __AVR_HAVE_PRPE_TC0 - -/* PR.PRPF */ -#define __AVR_HAVE_PRPF (PR_USART0_bm|PR_TC0_bm) -#define __AVR_HAVE_PRPF_USART0 -#define __AVR_HAVE_PRPF_TC0 - - -#endif /* #ifdef _AVR_ATXMEGA192C3_H_INCLUDED */ - diff --git a/arduino/hardware/tools/avr/avr/include/avr/iox192d3.h b/arduino/hardware/tools/avr/avr/include/avr/iox192d3.h deleted file mode 100644 index 4f5c8bb..0000000 --- a/arduino/hardware/tools/avr/avr/include/avr/iox192d3.h +++ /dev/null @@ -1,5749 +0,0 @@ -/* Copyright (c) 2009-2010 Atmel Corporation - All rights reserved. - - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - * Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - * Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in - the documentation and/or other materials provided with the - distribution. - - * Neither the name of the copyright holders nor the names of - contributors may be used to endorse or promote products derived - from this software without specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. */ - -/* $Id: iox192d3.h 2194 2010-11-16 15:10:51Z arcanum $ */ - -/* avr/iox192d3.h - definitions for ATxmega192D3 */ - -/* This file should only be included from , never directly. */ - -#ifndef _AVR_IO_H_ -# error "Include instead of this file." -#endif - -#ifndef _AVR_IOXXX_H_ -# define _AVR_IOXXX_H_ "iox192d3.h" -#else -# error "Attempt to include more than one file." -#endif - - -#ifndef _AVR_ATxmega192D3_H_ -#define _AVR_ATxmega192D3_H_ 1 - - -/* Ungrouped common registers */ -#define GPIOR0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ -#define GPIOR1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ -#define GPIOR2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ -#define GPIOR3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ -#define GPIOR4 _SFR_MEM8(0x0004) /* General Purpose IO Register 4 */ -#define GPIOR5 _SFR_MEM8(0x0005) /* General Purpose IO Register 5 */ -#define GPIOR6 _SFR_MEM8(0x0006) /* General Purpose IO Register 6 */ -#define GPIOR7 _SFR_MEM8(0x0007) /* General Purpose IO Register 7 */ -#define GPIOR8 _SFR_MEM8(0x0008) /* General Purpose IO Register 8 */ -#define GPIOR9 _SFR_MEM8(0x0009) /* General Purpose IO Register 9 */ -#define GPIORA _SFR_MEM8(0x000A) /* General Purpose IO Register 10 */ -#define GPIORB _SFR_MEM8(0x000B) /* General Purpose IO Register 11 */ -#define GPIORC _SFR_MEM8(0x000C) /* General Purpose IO Register 12 */ -#define GPIORD _SFR_MEM8(0x000D) /* General Purpose IO Register 13 */ -#define GPIORE _SFR_MEM8(0x000E) /* General Purpose IO Register 14 */ -#define GPIORF _SFR_MEM8(0x000F) /* General Purpose IO Register 15 */ - -#define CCP _SFR_MEM8(0x0034) /* Configuration Change Protection */ -#define RAMPD _SFR_MEM8(0x0038) /* Ramp D */ -#define RAMPX _SFR_MEM8(0x0039) /* Ramp X */ -#define RAMPY _SFR_MEM8(0x003A) /* Ramp Y */ -#define RAMPZ _SFR_MEM8(0x003B) /* Ramp Z */ -#define EIND _SFR_MEM8(0x003C) /* Extended Indirect Jump */ -#define SPL _SFR_MEM8(0x003D) /* Stack Pointer Low */ -#define SPH _SFR_MEM8(0x003E) /* Stack Pointer High */ -#define SREG _SFR_MEM8(0x003F) /* Status Register */ - - -/* C Language Only */ -#if !defined (__ASSEMBLER__) - -#include - -typedef volatile uint8_t register8_t; -typedef volatile uint16_t register16_t; -typedef volatile uint32_t register32_t; - - -#ifdef _WORDREGISTER -#undef _WORDREGISTER -#endif -#define _WORDREGISTER(regname) \ - __extension__ union \ - { \ - register16_t regname; \ - struct \ - { \ - register8_t regname ## L; \ - register8_t regname ## H; \ - }; \ - } - -#ifdef _DWORDREGISTER -#undef _DWORDREGISTER -#endif -#define _DWORDREGISTER(regname) \ - __extension__ union \ - { \ - register32_t regname; \ - struct \ - { \ - register8_t regname ## 0; \ - register8_t regname ## 1; \ - register8_t regname ## 2; \ - register8_t regname ## 3; \ - }; \ - } - - -/* -========================================================================== -IO Module Structures -========================================================================== -*/ - - -/* --------------------------------------------------------------------------- -XOCD - On-Chip Debug System --------------------------------------------------------------------------- -*/ - -/* On-Chip Debug System */ -typedef struct OCD_struct -{ - register8_t OCDR0; /* OCD Register 0 */ - register8_t OCDR1; /* OCD Register 1 */ -} OCD_t; - - -/* CCP signatures */ -typedef enum CCP_enum -{ - CCP_SPM_gc = (0x9D<<0), /* SPM Instruction Protection */ - CCP_IOREG_gc = (0xD8<<0), /* IO Register Protection */ -} CCP_t; - - -/* --------------------------------------------------------------------------- -CLK - Clock System --------------------------------------------------------------------------- -*/ - -/* Clock System */ -typedef struct CLK_struct -{ - register8_t CTRL; /* Control Register */ - register8_t PSCTRL; /* Prescaler Control Register */ - register8_t LOCK; /* Lock register */ - register8_t RTCCTRL; /* RTC Control Register */ -} CLK_t; - -/* --------------------------------------------------------------------------- -CLK - Clock System --------------------------------------------------------------------------- -*/ - -/* Power Reduction */ -typedef struct PR_struct -{ - register8_t PRGEN; /* General Power Reduction */ - register8_t PRPA; /* Power Reduction Port A */ - register8_t reserved_0x02; - register8_t PRPC; /* Power Reduction Port C */ - register8_t PRPD; /* Power Reduction Port D */ - register8_t PRPE; /* Power Reduction Port E */ - register8_t PRPF; /* Power Reduction Port F */ -} PR_t; - -/* System Clock Selection */ -typedef enum CLK_SCLKSEL_enum -{ - CLK_SCLKSEL_RC2M_gc = (0x00<<0), /* Internal 2MHz RC Oscillator */ - CLK_SCLKSEL_RC32M_gc = (0x01<<0), /* Internal 32MHz RC Oscillator */ - CLK_SCLKSEL_RC32K_gc = (0x02<<0), /* Internal 32kHz RC Oscillator */ - CLK_SCLKSEL_XOSC_gc = (0x03<<0), /* External Crystal Oscillator or Clock */ - CLK_SCLKSEL_PLL_gc = (0x04<<0), /* Phase Locked Loop */ -} CLK_SCLKSEL_t; - -/* Prescaler A Division Factor */ -typedef enum CLK_PSADIV_enum -{ - CLK_PSADIV_1_gc = (0x00<<2), /* Divide by 1 */ - CLK_PSADIV_2_gc = (0x01<<2), /* Divide by 2 */ - CLK_PSADIV_4_gc = (0x03<<2), /* Divide by 4 */ - CLK_PSADIV_8_gc = (0x05<<2), /* Divide by 8 */ - CLK_PSADIV_16_gc = (0x07<<2), /* Divide by 16 */ - CLK_PSADIV_32_gc = (0x09<<2), /* Divide by 32 */ - CLK_PSADIV_64_gc = (0x0B<<2), /* Divide by 64 */ - CLK_PSADIV_128_gc = (0x0D<<2), /* Divide by 128 */ - CLK_PSADIV_256_gc = (0x0F<<2), /* Divide by 256 */ - CLK_PSADIV_512_gc = (0x11<<2), /* Divide by 512 */ -} CLK_PSADIV_t; - -/* Prescaler B and C Division Factor */ -typedef enum CLK_PSBCDIV_enum -{ - CLK_PSBCDIV_1_1_gc = (0x00<<0), /* Divide B by 1 and C by 1 */ - CLK_PSBCDIV_1_2_gc = (0x01<<0), /* Divide B by 1 and C by 2 */ - CLK_PSBCDIV_4_1_gc = (0x02<<0), /* Divide B by 4 and C by 1 */ - CLK_PSBCDIV_2_2_gc = (0x03<<0), /* Divide B by 2 and C by 2 */ -} CLK_PSBCDIV_t; - -/* RTC Clock Source */ -typedef enum CLK_RTCSRC_enum -{ - CLK_RTCSRC_ULP_gc = (0x00<<1), /* 1kHz from internal 32kHz ULP */ - CLK_RTCSRC_TOSC_gc = (0x01<<1), /* 1kHz from 32kHz crystal oscillator on TOSC */ - CLK_RTCSRC_RCOSC_gc = (0x02<<1), /* 1kHz from internal 32kHz RC oscillator */ - CLK_RTCSRC_TOSC32_gc = (0x05<<1), /* 32kHz from 32kHz crystal oscillator on TOSC */ -} CLK_RTCSRC_t; - - -/* --------------------------------------------------------------------------- -SLEEP - Sleep Controller --------------------------------------------------------------------------- -*/ - -/* Sleep Controller */ -typedef struct SLEEP_struct -{ - register8_t CTRL; /* Control Register */ -} SLEEP_t; - -/* Sleep Mode */ -typedef enum SLEEP_SMODE_enum -{ - SLEEP_SMODE_IDLE_gc = (0x00<<1), /* Idle mode */ - SLEEP_SMODE_PDOWN_gc = (0x02<<1), /* Power-down Mode */ - SLEEP_SMODE_PSAVE_gc = (0x03<<1), /* Power-save Mode */ - SLEEP_SMODE_STDBY_gc = (0x06<<1), /* Standby Mode */ - SLEEP_SMODE_ESTDBY_gc = (0x07<<1), /* Extended Standby Mode */ -} SLEEP_SMODE_t; - - -#define SLEEP_MODE_IDLE (0x00<<1) -#define SLEEP_MODE_PWR_DOWN (0x02<<1) -#define SLEEP_MODE_PWR_SAVE (0x03<<1) -#define SLEEP_MODE_STANDBY (0x06<<1) -#define SLEEP_MODE_EXT_STANDBY (0x07<<1) - - -/* --------------------------------------------------------------------------- -OSC - Oscillator --------------------------------------------------------------------------- -*/ - -/* Oscillator */ -typedef struct OSC_struct -{ - register8_t CTRL; /* Control Register */ - register8_t STATUS; /* Status Register */ - register8_t XOSCCTRL; /* External Oscillator Control Register */ - register8_t XOSCFAIL; /* External Oscillator Failure Detection Register */ - register8_t RC32KCAL; /* 32kHz Internal Oscillator Calibration Register */ - register8_t PLLCTRL; /* PLL Control REgister */ - register8_t DFLLCTRL; /* DFLL Control Register */ -} OSC_t; - -/* Oscillator Frequency Range */ -typedef enum OSC_FRQRANGE_enum -{ - OSC_FRQRANGE_04TO2_gc = (0x00<<6), /* 0.4 - 2 MHz */ - OSC_FRQRANGE_2TO9_gc = (0x01<<6), /* 2 - 9 MHz */ - OSC_FRQRANGE_9TO12_gc = (0x02<<6), /* 9 - 12 MHz */ - OSC_FRQRANGE_12TO16_gc = (0x03<<6), /* 12 - 16 MHz */ -} OSC_FRQRANGE_t; - -/* External Oscillator Selection and Startup Time */ -typedef enum OSC_XOSCSEL_enum -{ - OSC_XOSCSEL_EXTCLK_gc = (0x00<<0), /* External Clock - 6 CLK */ - OSC_XOSCSEL_32KHz_gc = (0x02<<0), /* 32kHz TOSC - 32K CLK */ - OSC_XOSCSEL_XTAL_256CLK_gc = (0x03<<0), /* 0.4-16MHz XTAL - 256 CLK */ - OSC_XOSCSEL_XTAL_1KCLK_gc = (0x07<<0), /* 0.4-16MHz XTAL - 1K CLK */ - OSC_XOSCSEL_XTAL_16KCLK_gc = (0x0B<<0), /* 0.4-16MHz XTAL - 16K CLK */ -} OSC_XOSCSEL_t; - -/* PLL Clock Source */ -typedef enum OSC_PLLSRC_enum -{ - OSC_PLLSRC_RC2M_gc = (0x00<<6), /* Internal 2MHz RC Oscillator */ - OSC_PLLSRC_RC32M_gc = (0x02<<6), /* Internal 32MHz RC Oscillator */ - OSC_PLLSRC_XOSC_gc = (0x03<<6), /* External Oscillator */ -} OSC_PLLSRC_t; - - -/* --------------------------------------------------------------------------- -DFLL - DFLL --------------------------------------------------------------------------- -*/ - -/* DFLL */ -typedef struct DFLL_struct -{ - register8_t CTRL; /* Control Register */ - register8_t reserved_0x01; - register8_t CALA; /* Calibration Register A */ - register8_t CALB; /* Calibration Register B */ - register8_t COMP0; /* Oscillator Compare Register 0 */ - register8_t COMP1; /* Oscillator Compare Register 1 */ - register8_t COMP2; /* Oscillator Compare Register 2 */ - register8_t reserved_0x07; -} DFLL_t; - - -/* --------------------------------------------------------------------------- -RST - Reset --------------------------------------------------------------------------- -*/ - -/* Reset */ -typedef struct RST_struct -{ - register8_t STATUS; /* Status Register */ - register8_t CTRL; /* Control Register */ -} RST_t; - - -/* --------------------------------------------------------------------------- -WDT - Watch-Dog Timer --------------------------------------------------------------------------- -*/ - -/* Watch-Dog Timer */ -typedef struct WDT_struct -{ - register8_t CTRL; /* Control */ - register8_t WINCTRL; /* Windowed Mode Control */ - register8_t STATUS; /* Status */ -} WDT_t; - -/* Period setting */ -typedef enum WDT_PER_enum -{ - WDT_PER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ - WDT_PER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ - WDT_PER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ - WDT_PER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ - WDT_PER_125CLK_gc = (0x04<<2), /* 125 cycles (0.125s @ 3.3V) */ - WDT_PER_250CLK_gc = (0x05<<2), /* 250 cycles (0.25s @ 3.3V) */ - WDT_PER_500CLK_gc = (0x06<<2), /* 500 cycles (0.5s @ 3.3V) */ - WDT_PER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ - WDT_PER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ - WDT_PER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ - WDT_PER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ -} WDT_PER_t; - -/* Closed window period */ -typedef enum WDT_WPER_enum -{ - WDT_WPER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ - WDT_WPER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ - WDT_WPER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ - WDT_WPER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ - WDT_WPER_125CLK_gc = (0x04<<2), /* 125 cycles (0.125s @ 3.3V) */ - WDT_WPER_250CLK_gc = (0x05<<2), /* 250 cycles (0.25s @ 3.3V) */ - WDT_WPER_500CLK_gc = (0x06<<2), /* 500 cycles (0.5s @ 3.3V) */ - WDT_WPER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ - WDT_WPER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ - WDT_WPER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ - WDT_WPER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ -} WDT_WPER_t; - - -/* --------------------------------------------------------------------------- -MCU - MCU Control --------------------------------------------------------------------------- -*/ - -/* MCU Control */ -typedef struct MCU_struct -{ - register8_t DEVID0; /* Device ID byte 0 */ - register8_t DEVID1; /* Device ID byte 1 */ - register8_t DEVID2; /* Device ID byte 2 */ - register8_t REVID; /* Revision ID */ - register8_t JTAGUID; /* JTAG User ID */ - register8_t reserved_0x05; - register8_t MCUCR; /* MCU Control */ - register8_t reserved_0x07; - register8_t EVSYSLOCK; /* Event System Lock */ - register8_t AWEXLOCK; /* AWEX Lock */ - register8_t reserved_0x0A; - register8_t reserved_0x0B; -} MCU_t; - - -/* --------------------------------------------------------------------------- -PMIC - Programmable Multi-level Interrupt Controller --------------------------------------------------------------------------- -*/ - -/* Programmable Multi-level Interrupt Controller */ -typedef struct PMIC_struct -{ - register8_t STATUS; /* Status Register */ - register8_t INTPRI; /* Interrupt Priority */ - register8_t CTRL; /* Control Register */ -} PMIC_t; - - -/* --------------------------------------------------------------------------- -CRC - Cyclic Redundancy Checker --------------------------------------------------------------------------- -*/ - -/* Cyclic Redundancy Checker */ -typedef struct CRC_struct -{ - register8_t CTRL; /* Control Register */ - register8_t STATUS; /* Status Register */ - register8_t reserved_0x02; - register8_t DATAIN; /* Data Input */ - register8_t CHECKSUM0; /* Checksum byte 0 */ - register8_t CHECKSUM1; /* Checksum byte 1 */ - register8_t CHECKSUM2; /* Checksum byte 2 */ - register8_t CHECKSUM3; /* Checksum byte 3 */ -} CRC_t; - -/* Reset */ -typedef enum CRC_RESET_enum -{ - CRC_RESET_NO_gc = (0x00<<6), /* No Reset */ - CRC_RESET_RESET0_gc = (0x02<<6), /* Reset CRC with CHECKSUM to all zeros */ - CRC_RESET_RESET1_gc = (0x03<<6), /* Reset CRC with CHECKSUM to all ones */ -} CRC_RESET_t; - -/* Input Source */ -typedef enum CRC_SOURCE_enum -{ - CRC_SOURCE_DISABLE_gc = (0x00<<0), /* Disabled */ - CRC_SOURCE_IO_gc = (0x01<<0), /* I/O Interface */ - CRC_SOURCE_FLASH_gc = (0x02<<0), /* Flash */ - CRC_SOURCE_DMAC0_gc = (0x04<<0), /* DMAC Channel 0 */ - CRC_SOURCE_DMAC1_gc = (0x05<<0), /* DMAC Channel 1 */ - CRC_SOURCE_DMAC2_gc = (0x06<<0), /* DMAC Channel 2 */ - CRC_SOURCE_DMAC3_gc = (0x07<<0), /* DMAC Channel 3 */ -} CRC_SOURCE_t; - - -/* --------------------------------------------------------------------------- -EVSYS - Event System --------------------------------------------------------------------------- -*/ - -/* Event System */ -typedef struct EVSYS_struct -{ - register8_t CH0MUX; /* Event Channel 0 Multiplexer */ - register8_t CH1MUX; /* Event Channel 1 Multiplexer */ - register8_t CH2MUX; /* Event Channel 2 Multiplexer */ - register8_t CH3MUX; /* Event Channel 3 Multiplexer */ - register8_t reserved_0x04; - register8_t reserved_0x05; - register8_t reserved_0x06; - register8_t reserved_0x07; - register8_t CH0CTRL; /* Channel 0 Control Register */ - register8_t CH1CTRL; /* Channel 1 Control Register */ - register8_t CH2CTRL; /* Channel 2 Control Register */ - register8_t CH3CTRL; /* Channel 3 Control Register */ - register8_t reserved_0x0C; - register8_t reserved_0x0D; - register8_t reserved_0x0E; - register8_t reserved_0x0F; - register8_t STROBE; /* Event Strobe */ - register8_t DATA; /* Event Data */ -} EVSYS_t; - -/* Quadrature Decoder Index Recognition Mode */ -typedef enum EVSYS_QDIRM_enum -{ - EVSYS_QDIRM_00_gc = (0x00<<5), /* QDPH0 = 0, QDPH90 = 0 */ - EVSYS_QDIRM_01_gc = (0x01<<5), /* QDPH0 = 0, QDPH90 = 1 */ - EVSYS_QDIRM_10_gc = (0x02<<5), /* QDPH0 = 1, QDPH90 = 0 */ - EVSYS_QDIRM_11_gc = (0x03<<5), /* QDPH0 = 1, QDPH90 = 1 */ -} EVSYS_QDIRM_t; - -/* Digital filter coefficient */ -typedef enum EVSYS_DIGFILT_enum -{ - EVSYS_DIGFILT_1SAMPLE_gc = (0x00<<0), /* 1 SAMPLE */ - EVSYS_DIGFILT_2SAMPLES_gc = (0x01<<0), /* 2 SAMPLES */ - EVSYS_DIGFILT_3SAMPLES_gc = (0x02<<0), /* 3 SAMPLES */ - EVSYS_DIGFILT_4SAMPLES_gc = (0x03<<0), /* 4 SAMPLES */ - EVSYS_DIGFILT_5SAMPLES_gc = (0x04<<0), /* 5 SAMPLES */ - EVSYS_DIGFILT_6SAMPLES_gc = (0x05<<0), /* 6 SAMPLES */ - EVSYS_DIGFILT_7SAMPLES_gc = (0x06<<0), /* 7 SAMPLES */ - EVSYS_DIGFILT_8SAMPLES_gc = (0x07<<0), /* 8 SAMPLES */ -} EVSYS_DIGFILT_t; - -/* Event Channel multiplexer input selection */ -typedef enum EVSYS_CHMUX_enum -{ - EVSYS_CHMUX_OFF_gc = (0x00<<0), /* Off */ - EVSYS_CHMUX_RTC_OVF_gc = (0x08<<0), /* RTC Overflow */ - EVSYS_CHMUX_RTC_CMP_gc = (0x09<<0), /* RTC Compare Match */ - EVSYS_CHMUX_ACA_CH0_gc = (0x10<<0), /* Analog Comparator A Channel 0 */ - EVSYS_CHMUX_ACA_CH1_gc = (0x11<<0), /* Analog Comparator A Channel 1 */ - EVSYS_CHMUX_ACA_WIN_gc = (0x12<<0), /* Analog Comparator A Window */ - EVSYS_CHMUX_ADCA_CH0_gc = (0x20<<0), /* ADC A Channel 0 */ - EVSYS_CHMUX_PORTA_PIN0_gc = (0x50<<0), /* Port A, Pin0 */ - EVSYS_CHMUX_PORTA_PIN1_gc = (0x51<<0), /* Port A, Pin1 */ - EVSYS_CHMUX_PORTA_PIN2_gc = (0x52<<0), /* Port A, Pin2 */ - EVSYS_CHMUX_PORTA_PIN3_gc = (0x53<<0), /* Port A, Pin3 */ - EVSYS_CHMUX_PORTA_PIN4_gc = (0x54<<0), /* Port A, Pin4 */ - EVSYS_CHMUX_PORTA_PIN5_gc = (0x55<<0), /* Port A, Pin5 */ - EVSYS_CHMUX_PORTA_PIN6_gc = (0x56<<0), /* Port A, Pin6 */ - EVSYS_CHMUX_PORTA_PIN7_gc = (0x57<<0), /* Port A, Pin7 */ - EVSYS_CHMUX_PORTB_PIN0_gc = (0x58<<0), /* Port B, Pin0 */ - EVSYS_CHMUX_PORTB_PIN1_gc = (0x59<<0), /* Port B, Pin1 */ - EVSYS_CHMUX_PORTB_PIN2_gc = (0x5A<<0), /* Port B, Pin2 */ - EVSYS_CHMUX_PORTB_PIN3_gc = (0x5B<<0), /* Port B, Pin3 */ - EVSYS_CHMUX_PORTB_PIN4_gc = (0x5C<<0), /* Port B, Pin4 */ - EVSYS_CHMUX_PORTB_PIN5_gc = (0x5D<<0), /* Port B, Pin5 */ - EVSYS_CHMUX_PORTB_PIN6_gc = (0x5E<<0), /* Port B, Pin6 */ - EVSYS_CHMUX_PORTB_PIN7_gc = (0x5F<<0), /* Port B, Pin7 */ - EVSYS_CHMUX_PORTC_PIN0_gc = (0x60<<0), /* Port C, Pin0 */ - EVSYS_CHMUX_PORTC_PIN1_gc = (0x61<<0), /* Port C, Pin1 */ - EVSYS_CHMUX_PORTC_PIN2_gc = (0x62<<0), /* Port C, Pin2 */ - EVSYS_CHMUX_PORTC_PIN3_gc = (0x63<<0), /* Port C, Pin3 */ - EVSYS_CHMUX_PORTC_PIN4_gc = (0x64<<0), /* Port C, Pin4 */ - EVSYS_CHMUX_PORTC_PIN5_gc = (0x65<<0), /* Port C, Pin5 */ - EVSYS_CHMUX_PORTC_PIN6_gc = (0x66<<0), /* Port C, Pin6 */ - EVSYS_CHMUX_PORTC_PIN7_gc = (0x67<<0), /* Port C, Pin7 */ - EVSYS_CHMUX_PORTD_PIN0_gc = (0x68<<0), /* Port D, Pin0 */ - EVSYS_CHMUX_PORTD_PIN1_gc = (0x69<<0), /* Port D, Pin1 */ - EVSYS_CHMUX_PORTD_PIN2_gc = (0x6A<<0), /* Port D, Pin2 */ - EVSYS_CHMUX_PORTD_PIN3_gc = (0x6B<<0), /* Port D, Pin3 */ - EVSYS_CHMUX_PORTD_PIN4_gc = (0x6C<<0), /* Port D, Pin4 */ - EVSYS_CHMUX_PORTD_PIN5_gc = (0x6D<<0), /* Port D, Pin5 */ - EVSYS_CHMUX_PORTD_PIN6_gc = (0x6E<<0), /* Port D, Pin6 */ - EVSYS_CHMUX_PORTD_PIN7_gc = (0x6F<<0), /* Port D, Pin7 */ - EVSYS_CHMUX_PORTE_PIN0_gc = (0x70<<0), /* Port E, Pin0 */ - EVSYS_CHMUX_PORTE_PIN1_gc = (0x71<<0), /* Port E, Pin1 */ - EVSYS_CHMUX_PORTE_PIN2_gc = (0x72<<0), /* Port E, Pin2 */ - EVSYS_CHMUX_PORTE_PIN3_gc = (0x73<<0), /* Port E, Pin3 */ - EVSYS_CHMUX_PORTE_PIN4_gc = (0x74<<0), /* Port E, Pin4 */ - EVSYS_CHMUX_PORTE_PIN5_gc = (0x75<<0), /* Port E, Pin5 */ - EVSYS_CHMUX_PORTE_PIN6_gc = (0x76<<0), /* Port E, Pin6 */ - EVSYS_CHMUX_PORTE_PIN7_gc = (0x77<<0), /* Port E, Pin7 */ - EVSYS_CHMUX_PORTF_PIN0_gc = (0x78<<0), /* Port F, Pin0 */ - EVSYS_CHMUX_PORTF_PIN1_gc = (0x79<<0), /* Port F, Pin1 */ - EVSYS_CHMUX_PORTF_PIN2_gc = (0x7A<<0), /* Port F, Pin2 */ - EVSYS_CHMUX_PORTF_PIN3_gc = (0x7B<<0), /* Port F, Pin3 */ - EVSYS_CHMUX_PORTF_PIN4_gc = (0x7C<<0), /* Port F, Pin4 */ - EVSYS_CHMUX_PORTF_PIN5_gc = (0x7D<<0), /* Port F, Pin5 */ - EVSYS_CHMUX_PORTF_PIN6_gc = (0x7E<<0), /* Port F, Pin6 */ - EVSYS_CHMUX_PORTF_PIN7_gc = (0x7F<<0), /* Port F, Pin7 */ - EVSYS_CHMUX_PRESCALER_1_gc = (0x80<<0), /* Prescaler, divide by 1 */ - EVSYS_CHMUX_PRESCALER_2_gc = (0x81<<0), /* Prescaler, divide by 2 */ - EVSYS_CHMUX_PRESCALER_4_gc = (0x82<<0), /* Prescaler, divide by 4 */ - EVSYS_CHMUX_PRESCALER_8_gc = (0x83<<0), /* Prescaler, divide by 8 */ - EVSYS_CHMUX_PRESCALER_16_gc = (0x84<<0), /* Prescaler, divide by 16 */ - EVSYS_CHMUX_PRESCALER_32_gc = (0x85<<0), /* Prescaler, divide by 32 */ - EVSYS_CHMUX_PRESCALER_64_gc = (0x86<<0), /* Prescaler, divide by 64 */ - EVSYS_CHMUX_PRESCALER_128_gc = (0x87<<0), /* Prescaler, divide by 128 */ - EVSYS_CHMUX_PRESCALER_256_gc = (0x88<<0), /* Prescaler, divide by 256 */ - EVSYS_CHMUX_PRESCALER_512_gc = (0x89<<0), /* Prescaler, divide by 512 */ - EVSYS_CHMUX_PRESCALER_1024_gc = (0x8A<<0), /* Prescaler, divide by 1024 */ - EVSYS_CHMUX_PRESCALER_2048_gc = (0x8B<<0), /* Prescaler, divide by 2048 */ - EVSYS_CHMUX_PRESCALER_4096_gc = (0x8C<<0), /* Prescaler, divide by 4096 */ - EVSYS_CHMUX_PRESCALER_8192_gc = (0x8D<<0), /* Prescaler, divide by 8192 */ - EVSYS_CHMUX_PRESCALER_16384_gc = (0x8E<<0), /* Prescaler, divide by 16384 */ - EVSYS_CHMUX_PRESCALER_32768_gc = (0x8F<<0), /* Prescaler, divide by 32768 */ - EVSYS_CHMUX_TCC0_OVF_gc = (0xC0<<0), /* Timer/Counter C0 Overflow */ - EVSYS_CHMUX_TCC0_ERR_gc = (0xC1<<0), /* Timer/Counter C0 Error */ - EVSYS_CHMUX_TCC0_CCA_gc = (0xC4<<0), /* Timer/Counter C0 Compare or Capture A */ - EVSYS_CHMUX_TCC0_CCB_gc = (0xC5<<0), /* Timer/Counter C0 Compare or Capture B */ - EVSYS_CHMUX_TCC0_CCC_gc = (0xC6<<0), /* Timer/Counter C0 Compare or Capture C */ - EVSYS_CHMUX_TCC0_CCD_gc = (0xC7<<0), /* Timer/Counter C0 Compare or Capture D */ - EVSYS_CHMUX_TCC1_OVF_gc = (0xC8<<0), /* Timer/Counter C1 Overflow */ - EVSYS_CHMUX_TCC1_ERR_gc = (0xC9<<0), /* Timer/Counter C1 Error */ - EVSYS_CHMUX_TCC1_CCA_gc = (0xCC<<0), /* Timer/Counter C1 Compare or Capture A */ - EVSYS_CHMUX_TCC1_CCB_gc = (0xCD<<0), /* Timer/Counter C1 Compare or Capture B */ - EVSYS_CHMUX_TCD0_OVF_gc = (0xD0<<0), /* Timer/Counter D0 Overflow */ - EVSYS_CHMUX_TCD0_ERR_gc = (0xD1<<0), /* Timer/Counter D0 Error */ - EVSYS_CHMUX_TCD0_CCA_gc = (0xD4<<0), /* Timer/Counter D0 Compare or Capture A */ - EVSYS_CHMUX_TCD0_CCB_gc = (0xD5<<0), /* Timer/Counter D0 Compare or Capture B */ - EVSYS_CHMUX_TCD0_CCC_gc = (0xD6<<0), /* Timer/Counter D0 Compare or Capture C */ - EVSYS_CHMUX_TCD0_CCD_gc = (0xD7<<0), /* Timer/Counter D0 Compare or Capture D */ - EVSYS_CHMUX_TCD1_OVF_gc = (0xD8<<0), /* Timer/Counter D1 Overflow */ - EVSYS_CHMUX_TCD1_ERR_gc = (0xD9<<0), /* Timer/Counter D1 Error */ - EVSYS_CHMUX_TCD1_CCA_gc = (0xDC<<0), /* Timer/Counter D1 Compare or Capture A */ - EVSYS_CHMUX_TCD1_CCB_gc = (0xDD<<0), /* Timer/Counter D1 Compare or Capture B */ - EVSYS_CHMUX_TCE0_OVF_gc = (0xE0<<0), /* Timer/Counter E0 Overflow */ - EVSYS_CHMUX_TCE0_ERR_gc = (0xE1<<0), /* Timer/Counter E0 Error */ - EVSYS_CHMUX_TCE0_CCA_gc = (0xE4<<0), /* Timer/Counter E0 Compare or Capture A */ - EVSYS_CHMUX_TCE0_CCB_gc = (0xE5<<0), /* Timer/Counter E0 Compare or Capture B */ - EVSYS_CHMUX_TCE0_CCC_gc = (0xE6<<0), /* Timer/Counter E0 Compare or Capture C */ - EVSYS_CHMUX_TCE0_CCD_gc = (0xE7<<0), /* Timer/Counter E0 Compare or Capture D */ - EVSYS_CHMUX_TCE1_OVF_gc = (0xE8<<0), /* Timer/Counter E1 Overflow */ - EVSYS_CHMUX_TCE1_ERR_gc = (0xE9<<0), /* Timer/Counter E1 Error */ - EVSYS_CHMUX_TCE1_CCA_gc = (0xEC<<0), /* Timer/Counter E1 Compare or Capture A */ - EVSYS_CHMUX_TCE1_CCB_gc = (0xED<<0), /* Timer/Counter E1 Compare or Capture B */ - EVSYS_CHMUX_TCF0_OVF_gc = (0xF0<<0), /* Timer/Counter F0 Overflow */ - EVSYS_CHMUX_TCF0_ERR_gc = (0xF1<<0), /* Timer/Counter F0 Error */ - EVSYS_CHMUX_TCF0_CCA_gc = (0xF4<<0), /* Timer/Counter F0 Compare or Capture A */ - EVSYS_CHMUX_TCF0_CCB_gc = (0xF5<<0), /* Timer/Counter F0 Compare or Capture B */ - EVSYS_CHMUX_TCF0_CCC_gc = (0xF6<<0), /* Timer/Counter F0 Compare or Capture C */ - EVSYS_CHMUX_TCF0_CCD_gc = (0xF7<<0), /* Timer/Counter F0 Compare or Capture D */ - EVSYS_CHMUX_TCF1_OVF_gc = (0xF8<<0), /* Timer/Counter F1 Overflow */ - EVSYS_CHMUX_TCF1_ERR_gc = (0xF9<<0), /* Timer/Counter F1 Error */ - EVSYS_CHMUX_TCF1_CCA_gc = (0xFC<<0), /* Timer/Counter F1 Compare or Capture A */ - EVSYS_CHMUX_TCF1_CCB_gc = (0xFD<<0), /* Timer/Counter F1 Compare or Capture B */ -} EVSYS_CHMUX_t; - - -/* --------------------------------------------------------------------------- -NVM - Non Volatile Memory Controller --------------------------------------------------------------------------- -*/ - -/* Non-volatile Memory Controller */ -typedef struct NVM_struct -{ - register8_t ADDR0; /* Address Register 0 */ - register8_t ADDR1; /* Address Register 1 */ - register8_t ADDR2; /* Address Register 2 */ - register8_t reserved_0x03; - register8_t DATA0; /* Data Register 0 */ - register8_t DATA1; /* Data Register 1 */ - register8_t DATA2; /* Data Register 2 */ - register8_t reserved_0x07; - register8_t reserved_0x08; - register8_t reserved_0x09; - register8_t CMD; /* Command */ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t INTCTRL; /* Interrupt Control */ - register8_t reserved_0x0E; - register8_t STATUS; /* Status */ - register8_t LOCK_BITS; /* Lock Bits */ -} NVM_t; - -/* --------------------------------------------------------------------------- -NVM - Non Volatile Memory Controller --------------------------------------------------------------------------- -*/ - -/* Lock Bits */ -typedef struct NVM_LOCKBITS_struct -{ - register8_t LOCKBITS; /* Lock Bits */ -} NVM_LOCKBITS_t; - -/* --------------------------------------------------------------------------- -NVM - Non Volatile Memory Controller --------------------------------------------------------------------------- -*/ - -/* Fuses */ -typedef struct NVM_FUSES_struct -{ - register8_t FUSEBYTE0; /* User ID */ - register8_t FUSEBYTE1; /* Watchdog Configuration */ - register8_t FUSEBYTE2; /* Reset Configuration */ - register8_t reserved_0x03; - register8_t FUSEBYTE4; /* Start-up Configuration */ - register8_t FUSEBYTE5; /* EESAVE and BOD Level */ -} NVM_FUSES_t; - -/* --------------------------------------------------------------------------- -NVM - Non Volatile Memory Controller --------------------------------------------------------------------------- -*/ - -/* Production Signatures */ -typedef struct NVM_PROD_SIGNATURES_struct -{ - register8_t RCOSC2M; /* RCOSC 2MHz Calibration Value */ - register8_t reserved_0x01; - register8_t RCOSC32K; /* RCOSC 32kHz Calibration Value */ - register8_t RCOSC32M; /* RCOSC 32MHz Calibration Value */ - register8_t reserved_0x04; - register8_t reserved_0x05; - register8_t reserved_0x06; - register8_t reserved_0x07; - register8_t LOTNUM0; /* Lot Number Byte 0, ASCII */ - register8_t LOTNUM1; /* Lot Number Byte 1, ASCII */ - register8_t LOTNUM2; /* Lot Number Byte 2, ASCII */ - register8_t LOTNUM3; /* Lot Number Byte 3, ASCII */ - register8_t LOTNUM4; /* Lot Number Byte 4, ASCII */ - register8_t LOTNUM5; /* Lot Number Byte 5, ASCII */ - register8_t reserved_0x0E; - register8_t reserved_0x0F; - register8_t WAFNUM; /* Wafer Number */ - register8_t reserved_0x11; - register8_t COORDX0; /* Wafer Coordinate X Byte 0 */ - register8_t COORDX1; /* Wafer Coordinate X Byte 1 */ - register8_t COORDY0; /* Wafer Coordinate Y Byte 0 */ - register8_t COORDY1; /* Wafer Coordinate Y Byte 1 */ - register8_t reserved_0x16; - register8_t reserved_0x17; - register8_t reserved_0x18; - register8_t reserved_0x19; - register8_t reserved_0x1A; - register8_t reserved_0x1B; - register8_t reserved_0x1C; - register8_t reserved_0x1D; - register8_t reserved_0x1E; - register8_t reserved_0x1F; - register8_t ADCACAL0; /* ADCA Calibration Byte 0 */ - register8_t ADCACAL1; /* ADCA Calibration Byte 1 */ - register8_t reserved_0x22; - register8_t reserved_0x23; - register8_t ADCBCAL0; /* ADCB Calibration Byte 0 */ - register8_t ADCBCAL1; /* ADCB Calibration Byte 1 */ - register8_t reserved_0x26; - register8_t reserved_0x27; - register8_t reserved_0x28; - register8_t reserved_0x29; - register8_t reserved_0x2A; - register8_t reserved_0x2B; - register8_t reserved_0x2C; - register8_t reserved_0x2D; - register8_t TEMPSENSE0; /* Temperature Sensor Calibration Byte 0 */ - register8_t TEMPSENSE1; /* Temperature Sensor Calibration Byte 0 */ - register8_t DACAOFFCAL; /* DACA Calibration Byte 0 */ - register8_t DACAGAINCAL; /* DACA Calibration Byte 1 */ - register8_t DACBOFFCAL; /* DACB Calibration Byte 0 */ - register8_t DACBGAINCAL; /* DACB Calibration Byte 1 */ - register8_t reserved_0x34; - register8_t reserved_0x35; - register8_t reserved_0x36; - register8_t reserved_0x37; - register8_t reserved_0x38; - register8_t reserved_0x39; - register8_t reserved_0x3A; - register8_t reserved_0x3B; - register8_t reserved_0x3C; - register8_t reserved_0x3D; - register8_t reserved_0x3E; -} NVM_PROD_SIGNATURES_t; - -/* NVM Command */ -typedef enum NVM_CMD_enum -{ - NVM_CMD_NO_OPERATION_gc = (0x00<<0), /* Noop/Ordinary LPM */ - NVM_CMD_READ_CALIB_ROW_gc = (0x02<<0), /* Read calibration row */ - NVM_CMD_READ_USER_SIG_ROW_gc = (0x01<<0), /* Read user signature row */ - NVM_CMD_READ_EEPROM_gc = (0x06<<0), /* Read EEPROM */ - NVM_CMD_READ_FUSES_gc = (0x07<<0), /* Read fuse byte */ - NVM_CMD_WRITE_LOCK_BITS_gc = (0x08<<0), /* Write lock bits */ - NVM_CMD_ERASE_USER_SIG_ROW_gc = (0x18<<0), /* Erase user signature row */ - NVM_CMD_WRITE_USER_SIG_ROW_gc = (0x1A<<0), /* Write user signature row */ - NVM_CMD_ERASE_APP_gc = (0x20<<0), /* Erase Application Section */ - NVM_CMD_ERASE_APP_PAGE_gc = (0x22<<0), /* Erase Application Section page */ - NVM_CMD_LOAD_FLASH_BUFFER_gc = (0x23<<0), /* Load Flash page buffer */ - NVM_CMD_WRITE_APP_PAGE_gc = (0x24<<0), /* Write Application Section page */ - NVM_CMD_ERASE_WRITE_APP_PAGE_gc = (0x25<<0), /* Erase-and-write Application Section page */ - NVM_CMD_ERASE_FLASH_BUFFER_gc = (0x26<<0), /* Erase/flush Flash page buffer */ - NVM_CMD_ERASE_BOOT_PAGE_gc = (0x2A<<0), /* Erase Boot Section page */ - NVM_CMD_WRITE_BOOT_PAGE_gc = (0x2C<<0), /* Write Boot Section page */ - NVM_CMD_ERASE_WRITE_BOOT_PAGE_gc = (0x2D<<0), /* Erase-and-write Boot Section page */ - NVM_CMD_ERASE_EEPROM_gc = (0x30<<0), /* Erase EEPROM */ - NVM_CMD_ERASE_EEPROM_PAGE_gc = (0x32<<0), /* Erase EEPROM page */ - NVM_CMD_LOAD_EEPROM_BUFFER_gc = (0x33<<0), /* Load EEPROM page buffer */ - NVM_CMD_WRITE_EEPROM_PAGE_gc = (0x34<<0), /* Write EEPROM page */ - NVM_CMD_ERASE_WRITE_EEPROM_PAGE_gc = (0x35<<0), /* Erase-and-write EEPROM page */ - NVM_CMD_ERASE_EEPROM_BUFFER_gc = (0x36<<0), /* Erase/flush EEPROM page buffer */ - NVM_CMD_APP_CRC_gc = (0x38<<0), /* Generate Application section CRC */ - NVM_CMD_BOOT_CRC_gc = (0x39<<0), /* Generate Boot Section CRC */ - NVM_CMD_FLASH_RANGE_CRC_gc = (0x3A<<0), /* Generate Flash Range CRC */ -} NVM_CMD_t; - -/* SPM ready interrupt level */ -typedef enum NVM_SPMLVL_enum -{ - NVM_SPMLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ - NVM_SPMLVL_LO_gc = (0x01<<2), /* Low level */ - NVM_SPMLVL_MED_gc = (0x02<<2), /* Medium level */ - NVM_SPMLVL_HI_gc = (0x03<<2), /* High level */ -} NVM_SPMLVL_t; - -/* EEPROM ready interrupt level */ -typedef enum NVM_EELVL_enum -{ - NVM_EELVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ - NVM_EELVL_LO_gc = (0x01<<0), /* Low level */ - NVM_EELVL_MED_gc = (0x02<<0), /* Medium level */ - NVM_EELVL_HI_gc = (0x03<<0), /* High level */ -} NVM_EELVL_t; - -/* Boot lock bits - boot setcion */ -typedef enum NVM_BLBB_enum -{ - NVM_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ - NVM_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ - NVM_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ - NVM_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ -} NVM_BLBB_t; - -/* Boot lock bits - application section */ -typedef enum NVM_BLBA_enum -{ - NVM_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ - NVM_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ - NVM_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ - NVM_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ -} NVM_BLBA_t; - -/* Boot lock bits - application table section */ -typedef enum NVM_BLBAT_enum -{ - NVM_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ - NVM_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ - NVM_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ - NVM_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ -} NVM_BLBAT_t; - -/* Lock bits */ -typedef enum NVM_LB_enum -{ - NVM_LB_NOLOCK_gc = (0x03<<0), /* No locks */ - NVM_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ - NVM_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ -} NVM_LB_t; - -/* Boot Loader Section Reset Vector */ -typedef enum BOOTRST_enum -{ - BOOTRST_BOOTLDR_gc = (0x00<<6), /* Boot Loader Reset */ - BOOTRST_APPLICATION_gc = (0x01<<6), /* Application Reset */ -} BOOTRST_t; - -/* BOD operation */ -typedef enum BOD_enum -{ - BOD_INSAMPLEDMODE_gc = (0x01<<0), /* BOD enabled in sampled mode */ - BOD_CONTINOUSLY_gc = (0x02<<0), /* BOD enabled continuously */ - BOD_DISABLED_gc = (0x03<<0), /* BOD Disabled */ -} BOD_t; - -/* Watchdog (Window) Timeout Period */ -typedef enum WD_enum -{ - WD_8CLK_gc = (0x00<<4), /* 8 cycles (8ms @ 3.3V) */ - WD_16CLK_gc = (0x01<<4), /* 16 cycles (16ms @ 3.3V) */ - WD_32CLK_gc = (0x02<<4), /* 32 cycles (32ms @ 3.3V) */ - WD_64CLK_gc = (0x03<<4), /* 64 cycles (64ms @ 3.3V) */ - WD_128CLK_gc = (0x04<<4), /* 128 cycles (0.125s @ 3.3V) */ - WD_256CLK_gc = (0x05<<4), /* 256 cycles (0.25s @ 3.3V) */ - WD_512CLK_gc = (0x06<<4), /* 512 cycles (0.5s @ 3.3V) */ - WD_1KCLK_gc = (0x07<<4), /* 1K cycles (1s @ 3.3V) */ - WD_2KCLK_gc = (0x08<<4), /* 2K cycles (2s @ 3.3V) */ - WD_4KCLK_gc = (0x09<<4), /* 4K cycles (4s @ 3.3V) */ - WD_8KCLK_gc = (0x0A<<4), /* 8K cycles (8s @ 3.3V) */ -} WD_t; - -/* Start-up Time */ -typedef enum SUT_enum -{ - SUT_0MS_gc = (0x03<<2), /* 0 ms */ - SUT_4MS_gc = (0x01<<2), /* 4 ms */ - SUT_64MS_gc = (0x00<<2), /* 64 ms */ -} SUT_t; - -/* Brown Out Detection Voltage Level */ -typedef enum BODLVL_enum -{ - BODLVL_1V6_gc = (0x07<<0), /* 1.6 V */ - BODLVL_1V8_gc = (0x06<<0), /* 1.8 V */ - BODLVL_2V0_gc = (0x05<<0), /* 2.0 V */ - BODLVL_2V2_gc = (0x04<<0), /* 2.2 V */ - BODLVL_2V4_gc = (0x03<<0), /* 2.4 V */ - BODLVL_2V6_gc = (0x02<<0), /* 2.6 V */ - BODLVL_2V8_gc = (0x01<<0), /* 2.8 V */ - BODLVL_3V0_gc = (0x00<<0), /* 3.0 V */ -} BODLVL_t; - -/* --------------------------------------------------------------------------- -AC - Analog Comparator --------------------------------------------------------------------------- -*/ - -/* Analog Comparator */ -typedef struct AC_struct -{ - register8_t AC0CTRL; /* Comparator 0 Control */ - register8_t AC1CTRL; /* Comparator 1 Control */ - register8_t AC0MUXCTRL; /* Comparator 0 MUX Control */ - register8_t AC1MUXCTRL; /* Comparator 1 MUX Control */ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t WINCTRL; /* Window Mode Control */ - register8_t STATUS; /* Status */ -} AC_t; - -/* Interrupt mode */ -typedef enum AC_INTMODE_enum -{ - AC_INTMODE_BOTHEDGES_gc = (0x00<<6), /* Interrupt on both edges */ - AC_INTMODE_FALLING_gc = (0x02<<6), /* Interrupt on falling edge */ - AC_INTMODE_RISING_gc = (0x03<<6), /* Interrupt on rising edge */ -} AC_INTMODE_t; - -/* Interrupt level */ -typedef enum AC_INTLVL_enum -{ - AC_INTLVL_OFF_gc = (0x00<<4), /* Interrupt disabled */ - AC_INTLVL_LO_gc = (0x01<<4), /* Low level */ - AC_INTLVL_MED_gc = (0x02<<4), /* Medium level */ - AC_INTLVL_HI_gc = (0x03<<4), /* High level */ -} AC_INTLVL_t; - -/* Hysteresis mode selection */ -typedef enum AC_HYSMODE_enum -{ - AC_HYSMODE_NO_gc = (0x00<<1), /* No hysteresis */ - AC_HYSMODE_SMALL_gc = (0x01<<1), /* Small hysteresis */ - AC_HYSMODE_LARGE_gc = (0x02<<1), /* Large hysteresis */ -} AC_HYSMODE_t; - -/* Positive input multiplexer selection */ -typedef enum AC_MUXPOS_enum -{ - AC_MUXPOS_PIN0_gc = (0x00<<3), /* Pin 0 */ - AC_MUXPOS_PIN1_gc = (0x01<<3), /* Pin 1 */ - AC_MUXPOS_PIN2_gc = (0x02<<3), /* Pin 2 */ - AC_MUXPOS_PIN3_gc = (0x03<<3), /* Pin 3 */ - AC_MUXPOS_PIN4_gc = (0x04<<3), /* Pin 4 */ - AC_MUXPOS_PIN5_gc = (0x05<<3), /* Pin 5 */ - AC_MUXPOS_PIN6_gc = (0x06<<3), /* Pin 6 */ - AC_MUXPOS_DAC_gc = (0x07<<3), /* DAC output */ -} AC_MUXPOS_t; - -/* Negative input multiplexer selection */ -typedef enum AC_MUXNEG_enum -{ - AC_MUXNEG_PIN0_gc = (0x00<<0), /* Pin 0 */ - AC_MUXNEG_PIN1_gc = (0x01<<0), /* Pin 1 */ - AC_MUXNEG_PIN3_gc = (0x02<<0), /* Pin 3 */ - AC_MUXNEG_PIN5_gc = (0x03<<0), /* Pin 5 */ - AC_MUXNEG_PIN7_gc = (0x04<<0), /* Pin 7 */ - AC_MUXNEG_DAC_gc = (0x05<<0), /* DAC output */ - AC_MUXNEG_BANDGAP_gc = (0x06<<0), /* Bandgap Reference */ - AC_MUXNEG_SCALER_gc = (0x07<<0), /* Internal voltage scaler */ -} AC_MUXNEG_t; - -/* Windows interrupt mode */ -typedef enum AC_WINTMODE_enum -{ - AC_WINTMODE_ABOVE_gc = (0x00<<2), /* Interrupt on above window */ - AC_WINTMODE_INSIDE_gc = (0x01<<2), /* Interrupt on inside window */ - AC_WINTMODE_BELOW_gc = (0x02<<2), /* Interrupt on below window */ - AC_WINTMODE_OUTSIDE_gc = (0x03<<2), /* Interrupt on outside window */ -} AC_WINTMODE_t; - -/* Window interrupt level */ -typedef enum AC_WINTLVL_enum -{ - AC_WINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ - AC_WINTLVL_LO_gc = (0x01<<0), /* Low priority */ - AC_WINTLVL_MED_gc = (0x02<<0), /* Medium priority */ - AC_WINTLVL_HI_gc = (0x03<<0), /* High priority */ -} AC_WINTLVL_t; - -/* Window mode state */ -typedef enum AC_WSTATE_enum -{ - AC_WSTATE_ABOVE_gc = (0x00<<6), /* Signal above window */ - AC_WSTATE_INSIDE_gc = (0x01<<6), /* Signal inside window */ - AC_WSTATE_BELOW_gc = (0x02<<6), /* Signal below window */ -} AC_WSTATE_t; - - -/* --------------------------------------------------------------------------- -ADC - Analog/Digital Converter --------------------------------------------------------------------------- -*/ - -/* ADC Channel */ -typedef struct ADC_CH_struct -{ - register8_t CTRL; /* Control Register */ - register8_t MUXCTRL; /* MUX Control */ - register8_t INTCTRL; /* Channel Interrupt Control */ - register8_t INTFLAGS; /* Interrupt Flags */ - _WORDREGISTER(RES); /* Channel Result */ - register8_t reserved_0x6; - register8_t reserved_0x7; -} ADC_CH_t; - -/* --------------------------------------------------------------------------- -ADC - Analog/Digital Converter --------------------------------------------------------------------------- -*/ - -/* Analog-to-Digital Converter */ -typedef struct ADC_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t REFCTRL; /* Reference Control */ - register8_t EVCTRL; /* Event Control */ - register8_t PRESCALER; /* Clock Prescaler */ - register8_t reserved_0x05; - register8_t INTFLAGS; /* Interrupt Flags */ - register8_t reserved_0x07; - register8_t reserved_0x08; - register8_t reserved_0x09; - register8_t reserved_0x0A; - register8_t reserved_0x0B; - _WORDREGISTER(CAL); /* Calibration Value */ - register8_t reserved_0x0E; - register8_t reserved_0x0F; - _WORDREGISTER(CH0RES); /* Channel 0 Result */ - register8_t reserved_0x12; - register8_t reserved_0x13; - register8_t reserved_0x14; - register8_t reserved_0x15; - register8_t reserved_0x16; - register8_t reserved_0x17; - _WORDREGISTER(CMP); /* Compare Value */ - register8_t reserved_0x1A; - register8_t reserved_0x1B; - register8_t reserved_0x1C; - register8_t reserved_0x1D; - register8_t reserved_0x1E; - register8_t reserved_0x1F; - ADC_CH_t CH0; /* ADC Channel 0 */ -} ADC_t; - -/* Current Limitation */ -typedef enum ADC_CURRLIMIT_enum -{ - ADC_CURRLIMIT_NO_gc = (0x00<<5), /* No current limit, 300ksps max sampling rate */ - ADC_CURRLIMIT_LOW_gc = (0x01<<5), /* Low current limit, 225ksps max sampling rate */ - ADC_CURRLIMIT_MED_gc = (0x02<<5), /* Medium current limit, 150ksps max sampling rate */ - ADC_CURRLIMIT_HIGH_gc = (0x03<<5), /* High current limit, 75ksps max sampling rate */ -} ADC_CURRLIMIT_t; - -/* Positive input multiplexer selection */ -typedef enum ADC_CH_MUXPOS_enum -{ - ADC_CH_MUXPOS_PIN0_gc = (0x00<<3), /* Input pin 0 */ - ADC_CH_MUXPOS_PIN1_gc = (0x01<<3), /* Input pin 1 */ - ADC_CH_MUXPOS_PIN2_gc = (0x02<<3), /* Input pin 2 */ - ADC_CH_MUXPOS_PIN3_gc = (0x03<<3), /* Input pin 3 */ - ADC_CH_MUXPOS_PIN4_gc = (0x04<<3), /* Input pin 4 */ - ADC_CH_MUXPOS_PIN5_gc = (0x05<<3), /* Input pin 5 */ - ADC_CH_MUXPOS_PIN6_gc = (0x06<<3), /* Input pin 6 */ - ADC_CH_MUXPOS_PIN7_gc = (0x07<<3), /* Input pin 7 */ -} ADC_CH_MUXPOS_t; - -/* Internal input multiplexer selections */ -typedef enum ADC_CH_MUXINT_enum -{ - ADC_CH_MUXINT_TEMP_gc = (0x00<<3), /* Temperature Reference */ - ADC_CH_MUXINT_BANDGAP_gc = (0x01<<3), /* Bandgap Reference */ - ADC_CH_MUXINT_SCALEDVCC_gc = (0x02<<3), /* 1/10 scaled VCC */ - ADC_CH_MUXINT_DAC_gc = (0x03<<3), /* DAC output */ -} ADC_CH_MUXINT_t; - -/* Negative input multiplexer selection */ -typedef enum ADC_CH_MUXNEG_enum -{ - ADC_CH_MUXNEG_PIN0_gc = (0x00<<0), /* Input pin 0 */ - ADC_CH_MUXNEG_PIN1_gc = (0x01<<0), /* Input pin 1 */ - ADC_CH_MUXNEG_PIN2_gc = (0x02<<0), /* Input pin 2 */ - ADC_CH_MUXNEG_PIN3_gc = (0x03<<0), /* Input pin 3 */ - ADC_CH_MUXNEG_PIN4_gc = (0x04<<0), /* Input pin 4 */ - ADC_CH_MUXNEG_PIN5_gc = (0x05<<0), /* Input pin 5 */ - ADC_CH_MUXNEG_PIN6_gc = (0x06<<0), /* Input pin 6 */ - ADC_CH_MUXNEG_PIN7_gc = (0x07<<0), /* Input pin 7 */ -} ADC_CH_MUXNEG_t; - -/* Input mode */ -typedef enum ADC_CH_INPUTMODE_enum -{ - ADC_CH_INPUTMODE_INTERNAL_gc = (0x00<<0), /* Internal inputs, no gain */ - ADC_CH_INPUTMODE_SINGLEENDED_gc = (0x01<<0), /* Single-ended input, no gain */ - ADC_CH_INPUTMODE_DIFF_gc = (0x02<<0), /* Differential input, no gain */ - ADC_CH_INPUTMODE_DIFFWGAIN_gc = (0x03<<0), /* Differential input, with gain */ -} ADC_CH_INPUTMODE_t; - -/* Gain factor */ -typedef enum ADC_CH_GAIN_enum -{ - ADC_CH_GAIN_1X_gc = (0x00<<2), /* 1x gain */ - ADC_CH_GAIN_2X_gc = (0x01<<2), /* 2x gain */ - ADC_CH_GAIN_4X_gc = (0x02<<2), /* 4x gain */ - ADC_CH_GAIN_8X_gc = (0x03<<2), /* 8x gain */ - ADC_CH_GAIN_16X_gc = (0x04<<2), /* 16x gain */ - ADC_CH_GAIN_32X_gc = (0x05<<2), /* 32x gain */ - ADC_CH_GAIN_64X_gc = (0x06<<2), /* 64x gain */ - ADC_CH_GAIN_DIV2_gc = (0x07<<2), /* x/2 gain */ -} ADC_CH_GAIN_t; - -/* Conversion result resolution */ -typedef enum ADC_RESOLUTION_enum -{ - ADC_RESOLUTION_12BIT_gc = (0x00<<1), /* 12-bit right-adjusted result */ - ADC_RESOLUTION_8BIT_gc = (0x02<<1), /* 8-bit right-adjusted result */ - ADC_RESOLUTION_LEFT12BIT_gc = (0x03<<1), /* 12-bit left-adjusted result */ -} ADC_RESOLUTION_t; - -/* Voltage reference selection */ -typedef enum ADC_REFSEL_enum -{ - ADC_REFSEL_INT1V_gc = (0x00<<4), /* Internal 1V */ - ADC_REFSEL_VCC_gc = (0x01<<4), /* Internal VCC/1.6V */ - ADC_REFSEL_AREFA_gc = (0x02<<4), /* External reference on PORT A */ - ADC_REFSEL_AREFB_gc = (0x03<<4), /* External reference on PORT B */ -} ADC_REFSEL_t; - -/* Channel sweep selection */ -typedef enum ADC_SWEEP_enum -{ - ADC_SWEEP_0_gc = (0x00<<6), /* ADC Channel 0 */ -} ADC_SWEEP_t; - -/* Event channel input selection */ -typedef enum ADC_EVSEL_enum -{ - ADC_EVSEL_0123_gc = (0x00<<3), /* Event Channel 0,1,2,3 */ - ADC_EVSEL_1234_gc = (0x01<<3), /* Event Channel 1,2,3,4 */ - ADC_EVSEL_2345_gc = (0x02<<3), /* Event Channel 2,3,4,5 */ - ADC_EVSEL_3456_gc = (0x03<<3), /* Event Channel 3,4,5,6 */ - ADC_EVSEL_4567_gc = (0x04<<3), /* Event Channel 4,5,6,7 */ - ADC_EVSEL_567_gc = (0x05<<3), /* Event Channel 5,6,7 */ - ADC_EVSEL_67_gc = (0x06<<3), /* Event Channel 6,7 */ - ADC_EVSEL_7_gc = (0x07<<3), /* Event Channel 7 */ -} ADC_EVSEL_t; - -/* Event action selection */ -typedef enum ADC_EVACT_enum -{ - ADC_EVACT_NONE_gc = (0x00<<0), /* No event action */ - ADC_EVACT_CH0_gc = (0x01<<0), /* First event triggers channel 0 */ -} ADC_EVACT_t; - -/* Interupt mode */ -typedef enum ADC_CH_INTMODE_enum -{ - ADC_CH_INTMODE_COMPLETE_gc = (0x00<<2), /* Interrupt on conversion complete */ - ADC_CH_INTMODE_BELOW_gc = (0x01<<2), /* Interrupt on result below compare value */ - ADC_CH_INTMODE_ABOVE_gc = (0x03<<2), /* Interrupt on result above compare value */ -} ADC_CH_INTMODE_t; - -/* Interrupt level */ -typedef enum ADC_CH_INTLVL_enum -{ - ADC_CH_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ - ADC_CH_INTLVL_LO_gc = (0x01<<0), /* Low level */ - ADC_CH_INTLVL_MED_gc = (0x02<<0), /* Medium level */ - ADC_CH_INTLVL_HI_gc = (0x03<<0), /* High level */ -} ADC_CH_INTLVL_t; - -/* Clock prescaler */ -typedef enum ADC_PRESCALER_enum -{ - ADC_PRESCALER_DIV4_gc = (0x00<<0), /* Divide clock by 4 */ - ADC_PRESCALER_DIV8_gc = (0x01<<0), /* Divide clock by 8 */ - ADC_PRESCALER_DIV16_gc = (0x02<<0), /* Divide clock by 16 */ - ADC_PRESCALER_DIV32_gc = (0x03<<0), /* Divide clock by 32 */ - ADC_PRESCALER_DIV64_gc = (0x04<<0), /* Divide clock by 64 */ - ADC_PRESCALER_DIV128_gc = (0x05<<0), /* Divide clock by 128 */ - ADC_PRESCALER_DIV256_gc = (0x06<<0), /* Divide clock by 256 */ - ADC_PRESCALER_DIV512_gc = (0x07<<0), /* Divide clock by 512 */ -} ADC_PRESCALER_t; - - -/* --------------------------------------------------------------------------- -RTC - Real-Time Clounter --------------------------------------------------------------------------- -*/ - -/* Real-Time Counter */ -typedef struct RTC_struct -{ - register8_t CTRL; /* Control Register */ - register8_t STATUS; /* Status Register */ - register8_t INTCTRL; /* Interrupt Control Register */ - register8_t INTFLAGS; /* Interrupt Flags */ - register8_t TEMP; /* Temporary register */ - register8_t reserved_0x05; - register8_t reserved_0x06; - register8_t reserved_0x07; - _WORDREGISTER(CNT); /* Count Register */ - _WORDREGISTER(PER); /* Period Register */ - _WORDREGISTER(COMP); /* Compare Register */ -} RTC_t; - -/* Prescaler Factor */ -typedef enum RTC_PRESCALER_enum -{ - RTC_PRESCALER_OFF_gc = (0x00<<0), /* RTC Off */ - RTC_PRESCALER_DIV1_gc = (0x01<<0), /* RTC Clock */ - RTC_PRESCALER_DIV2_gc = (0x02<<0), /* RTC Clock / 2 */ - RTC_PRESCALER_DIV8_gc = (0x03<<0), /* RTC Clock / 8 */ - RTC_PRESCALER_DIV16_gc = (0x04<<0), /* RTC Clock / 16 */ - RTC_PRESCALER_DIV64_gc = (0x05<<0), /* RTC Clock / 64 */ - RTC_PRESCALER_DIV256_gc = (0x06<<0), /* RTC Clock / 256 */ - RTC_PRESCALER_DIV1024_gc = (0x07<<0), /* RTC Clock / 1024 */ -} RTC_PRESCALER_t; - -/* Compare Interrupt level */ -typedef enum RTC_COMPINTLVL_enum -{ - RTC_COMPINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ - RTC_COMPINTLVL_LO_gc = (0x01<<2), /* Low Level */ - RTC_COMPINTLVL_MED_gc = (0x02<<2), /* Medium Level */ - RTC_COMPINTLVL_HI_gc = (0x03<<2), /* High Level */ -} RTC_COMPINTLVL_t; - -/* Overflow Interrupt level */ -typedef enum RTC_OVFINTLVL_enum -{ - RTC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - RTC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ - RTC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ - RTC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ -} RTC_OVFINTLVL_t; - - -/* --------------------------------------------------------------------------- -EBI - External Bus Interface --------------------------------------------------------------------------- -*/ - -/* EBI Chip Select Module */ -typedef struct EBI_CS_struct -{ - register8_t CTRLA; /* Chip Select Control Register A */ - register8_t CTRLB; /* Chip Select Control Register B */ - _WORDREGISTER(BASEADDR); /* Chip Select Base Address */ -} EBI_CS_t; - -/* --------------------------------------------------------------------------- -EBI - External Bus Interface --------------------------------------------------------------------------- -*/ - -/* External Bus Interface */ -typedef struct EBI_struct -{ - register8_t CTRL; /* Control */ - register8_t SDRAMCTRLA; /* SDRAM Control Register A */ - register8_t reserved_0x02; - register8_t reserved_0x03; - _WORDREGISTER(REFRESH); /* SDRAM Refresh Period */ - _WORDREGISTER(INITDLY); /* SDRAM Initialization Delay */ - register8_t SDRAMCTRLB; /* SDRAM Control Register B */ - register8_t SDRAMCTRLC; /* SDRAM Control Register C */ - register8_t reserved_0x0A; - register8_t reserved_0x0B; - register8_t reserved_0x0C; - register8_t reserved_0x0D; - register8_t reserved_0x0E; - register8_t reserved_0x0F; - EBI_CS_t CS0; /* Chip Select 0 */ - EBI_CS_t CS1; /* Chip Select 1 */ - EBI_CS_t CS2; /* Chip Select 2 */ - EBI_CS_t CS3; /* Chip Select 3 */ -} EBI_t; - -/* Chip Select adress space */ -typedef enum EBI_CS_ASIZE_enum -{ - EBI_CS_ASIZE_256B_gc = (0x00<<2), /* 256 bytes */ - EBI_CS_ASIZE_512B_gc = (0x01<<2), /* 512 bytes */ - EBI_CS_ASIZE_1KB_gc = (0x02<<2), /* 1K bytes */ - EBI_CS_ASIZE_2KB_gc = (0x03<<2), /* 2K bytes */ - EBI_CS_ASIZE_4KB_gc = (0x04<<2), /* 4K bytes */ - EBI_CS_ASIZE_8KB_gc = (0x05<<2), /* 8K bytes */ - EBI_CS_ASIZE_16KB_gc = (0x06<<2), /* 16K bytes */ - EBI_CS_ASIZE_32KB_gc = (0x07<<2), /* 32K bytes */ - EBI_CS_ASIZE_64KB_gc = (0x08<<2), /* 64K bytes */ - EBI_CS_ASIZE_128KB_gc = (0x09<<2), /* 128K bytes */ - EBI_CS_ASIZE_256KB_gc = (0x0A<<2), /* 256K bytes */ - EBI_CS_ASIZE_512KB_gc = (0x0B<<2), /* 512K bytes */ - EBI_CS_ASIZE_1MB_gc = (0x0C<<2), /* 1M bytes */ - EBI_CS_ASIZE_2MB_gc = (0x0D<<2), /* 2M bytes */ - EBI_CS_ASIZE_4MB_gc = (0x0E<<2), /* 4M bytes */ - EBI_CS_ASIZE_8MB_gc = (0x0F<<2), /* 8M bytes */ - EBI_CS_ASIZE_16M_gc = (0x10<<2), /* 16M bytes */ -} EBI_CS_ASIZE_t; - -/* */ -typedef enum EBI_CS_SRWS_enum -{ - EBI_CS_SRWS_0CLK_gc = (0x00<<0), /* 0 cycles */ - EBI_CS_SRWS_1CLK_gc = (0x01<<0), /* 1 cycle */ - EBI_CS_SRWS_2CLK_gc = (0x02<<0), /* 2 cycles */ - EBI_CS_SRWS_3CLK_gc = (0x03<<0), /* 3 cycles */ - EBI_CS_SRWS_4CLK_gc = (0x04<<0), /* 4 cycles */ - EBI_CS_SRWS_5CLK_gc = (0x05<<0), /* 5 cycle */ - EBI_CS_SRWS_6CLK_gc = (0x06<<0), /* 6 cycles */ - EBI_CS_SRWS_7CLK_gc = (0x07<<0), /* 7 cycles */ -} EBI_CS_SRWS_t; - -/* Chip Select address mode */ -typedef enum EBI_CS_MODE_enum -{ - EBI_CS_MODE_DISABLED_gc = (0x00<<0), /* Chip Select Disabled */ - EBI_CS_MODE_SRAM_gc = (0x01<<0), /* Chip Select in SRAM mode */ - EBI_CS_MODE_LPC_gc = (0x02<<0), /* Chip Select in SRAM LPC mode */ - EBI_CS_MODE_SDRAM_gc = (0x03<<0), /* Chip Select in SDRAM mode */ -} EBI_CS_MODE_t; - -/* Chip Select SDRAM mode */ -typedef enum EBI_CS_SDMODE_enum -{ - EBI_CS_SDMODE_NORMAL_gc = (0x00<<0), /* Normal mode */ - EBI_CS_SDMODE_LOAD_gc = (0x01<<0), /* Load Mode Register command mode */ -} EBI_CS_SDMODE_t; - -/* */ -typedef enum EBI_SDDATAW_enum -{ - EBI_SDDATAW_4BIT_gc = (0x00<<6), /* 4-bit data bus */ - EBI_SDDATAW_8BIT_gc = (0x01<<6), /* 8-bit data bus */ -} EBI_SDDATAW_t; - -/* */ -typedef enum EBI_LPCMODE_enum -{ - EBI_LPCMODE_ALE1_gc = (0x00<<4), /* Data muxed with addr byte 0 */ - EBI_LPCMODE_ALE12_gc = (0x02<<4), /* Data muxed with addr byte 0 and 1 */ -} EBI_LPCMODE_t; - -/* */ -typedef enum EBI_SRMODE_enum -{ - EBI_SRMODE_ALE1_gc = (0x00<<2), /* Addr byte 0 muxed with 1 */ - EBI_SRMODE_ALE2_gc = (0x01<<2), /* Addr byte 0 muxed with 2 */ - EBI_SRMODE_ALE12_gc = (0x02<<2), /* Addr byte 0 muxed with 1 and 2 */ - EBI_SRMODE_NOALE_gc = (0x03<<2), /* No addr muxing */ -} EBI_SRMODE_t; - -/* */ -typedef enum EBI_IFMODE_enum -{ - EBI_IFMODE_DISABLED_gc = (0x00<<0), /* EBI Disabled */ - EBI_IFMODE_3PORT_gc = (0x01<<0), /* 3-port mode */ - EBI_IFMODE_4PORT_gc = (0x02<<0), /* 4-port mode */ - EBI_IFMODE_2PORT_gc = (0x03<<0), /* 2-port mode */ -} EBI_IFMODE_t; - -/* */ -typedef enum EBI_SDCOL_enum -{ - EBI_SDCOL_8BIT_gc = (0x00<<0), /* 8 column bits */ - EBI_SDCOL_9BIT_gc = (0x01<<0), /* 9 column bits */ - EBI_SDCOL_10BIT_gc = (0x02<<0), /* 10 column bits */ - EBI_SDCOL_11BIT_gc = (0x03<<0), /* 11 column bits */ -} EBI_SDCOL_t; - -/* */ -typedef enum EBI_MRDLY_enum -{ - EBI_MRDLY_0CLK_gc = (0x00<<6), /* 0 cycles */ - EBI_MRDLY_1CLK_gc = (0x01<<6), /* 1 cycle */ - EBI_MRDLY_2CLK_gc = (0x02<<6), /* 2 cycles */ - EBI_MRDLY_3CLK_gc = (0x03<<6), /* 3 cycles */ -} EBI_MRDLY_t; - -/* */ -typedef enum EBI_ROWCYCDLY_enum -{ - EBI_ROWCYCDLY_0CLK_gc = (0x00<<3), /* 0 cycles */ - EBI_ROWCYCDLY_1CLK_gc = (0x01<<3), /* 1 cycle */ - EBI_ROWCYCDLY_2CLK_gc = (0x02<<3), /* 2 cycles */ - EBI_ROWCYCDLY_3CLK_gc = (0x03<<3), /* 3 cycles */ - EBI_ROWCYCDLY_4CLK_gc = (0x04<<3), /* 4 cycles */ - EBI_ROWCYCDLY_5CLK_gc = (0x05<<3), /* 5 cycle */ - EBI_ROWCYCDLY_6CLK_gc = (0x06<<3), /* 6 cycles */ - EBI_ROWCYCDLY_7CLK_gc = (0x07<<3), /* 7 cycles */ -} EBI_ROWCYCDLY_t; - -/* */ -typedef enum EBI_RPDLY_enum -{ - EBI_RPDLY_0CLK_gc = (0x00<<0), /* 0 cycles */ - EBI_RPDLY_1CLK_gc = (0x01<<0), /* 1 cycle */ - EBI_RPDLY_2CLK_gc = (0x02<<0), /* 2 cycles */ - EBI_RPDLY_3CLK_gc = (0x03<<0), /* 3 cycles */ - EBI_RPDLY_4CLK_gc = (0x04<<0), /* 4 cycles */ - EBI_RPDLY_5CLK_gc = (0x05<<0), /* 5 cycle */ - EBI_RPDLY_6CLK_gc = (0x06<<0), /* 6 cycles */ - EBI_RPDLY_7CLK_gc = (0x07<<0), /* 7 cycles */ -} EBI_RPDLY_t; - -/* */ -typedef enum EBI_WRDLY_enum -{ - EBI_WRDLY_0CLK_gc = (0x00<<6), /* 0 cycles */ - EBI_WRDLY_1CLK_gc = (0x01<<6), /* 1 cycle */ - EBI_WRDLY_2CLK_gc = (0x02<<6), /* 2 cycles */ - EBI_WRDLY_3CLK_gc = (0x03<<6), /* 3 cycles */ -} EBI_WRDLY_t; - -/* */ -typedef enum EBI_ESRDLY_enum -{ - EBI_ESRDLY_0CLK_gc = (0x00<<3), /* 0 cycles */ - EBI_ESRDLY_1CLK_gc = (0x01<<3), /* 1 cycle */ - EBI_ESRDLY_2CLK_gc = (0x02<<3), /* 2 cycles */ - EBI_ESRDLY_3CLK_gc = (0x03<<3), /* 3 cycles */ - EBI_ESRDLY_4CLK_gc = (0x04<<3), /* 4 cycles */ - EBI_ESRDLY_5CLK_gc = (0x05<<3), /* 5 cycle */ - EBI_ESRDLY_6CLK_gc = (0x06<<3), /* 6 cycles */ - EBI_ESRDLY_7CLK_gc = (0x07<<3), /* 7 cycles */ -} EBI_ESRDLY_t; - -/* */ -typedef enum EBI_ROWCOLDLY_enum -{ - EBI_ROWCOLDLY_0CLK_gc = (0x00<<0), /* 0 cycles */ - EBI_ROWCOLDLY_1CLK_gc = (0x01<<0), /* 1 cycle */ - EBI_ROWCOLDLY_2CLK_gc = (0x02<<0), /* 2 cycles */ - EBI_ROWCOLDLY_3CLK_gc = (0x03<<0), /* 3 cycles */ - EBI_ROWCOLDLY_4CLK_gc = (0x04<<0), /* 4 cycles */ - EBI_ROWCOLDLY_5CLK_gc = (0x05<<0), /* 5 cycle */ - EBI_ROWCOLDLY_6CLK_gc = (0x06<<0), /* 6 cycles */ - EBI_ROWCOLDLY_7CLK_gc = (0x07<<0), /* 7 cycles */ -} EBI_ROWCOLDLY_t; - - -/* --------------------------------------------------------------------------- -TWI - Two-Wire Interface --------------------------------------------------------------------------- -*/ - -/* */ -typedef struct TWI_MASTER_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t CTRLC; /* Control Register C */ - register8_t STATUS; /* Status Register */ - register8_t BAUD; /* Baurd Rate Control Register */ - register8_t ADDR; /* Address Register */ - register8_t DATA; /* Data Register */ -} TWI_MASTER_t; - -/* --------------------------------------------------------------------------- -TWI - Two-Wire Interface --------------------------------------------------------------------------- -*/ - -/* */ -typedef struct TWI_SLAVE_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t STATUS; /* Status Register */ - register8_t ADDR; /* Address Register */ - register8_t DATA; /* Data Register */ - register8_t ADDRMASK; /* Address Mask Register */ -} TWI_SLAVE_t; - -/* --------------------------------------------------------------------------- -TWI - Two-Wire Interface --------------------------------------------------------------------------- -*/ - -/* Two-Wire Interface */ -typedef struct TWI_struct -{ - register8_t CTRL; /* TWI Common Control Register */ - TWI_MASTER_t MASTER; /* TWI master module */ - TWI_SLAVE_t SLAVE; /* TWI slave module */ -} TWI_t; - -/* Master Interrupt Level */ -typedef enum TWI_MASTER_INTLVL_enum -{ - TWI_MASTER_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ - TWI_MASTER_INTLVL_LO_gc = (0x01<<6), /* Low Level */ - TWI_MASTER_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ - TWI_MASTER_INTLVL_HI_gc = (0x03<<6), /* High Level */ -} TWI_MASTER_INTLVL_t; - -/* Inactive Timeout */ -typedef enum TWI_MASTER_TIMEOUT_enum -{ - TWI_MASTER_TIMEOUT_DISABLED_gc = (0x00<<2), /* Bus Timeout Disabled */ - TWI_MASTER_TIMEOUT_50US_gc = (0x01<<2), /* 50 Microseconds */ - TWI_MASTER_TIMEOUT_100US_gc = (0x02<<2), /* 100 Microseconds */ - TWI_MASTER_TIMEOUT_200US_gc = (0x03<<2), /* 200 Microseconds */ -} TWI_MASTER_TIMEOUT_t; - -/* Master Command */ -typedef enum TWI_MASTER_CMD_enum -{ - TWI_MASTER_CMD_NOACT_gc = (0x00<<0), /* No Action */ - TWI_MASTER_CMD_REPSTART_gc = (0x01<<0), /* Issue Repeated Start Condition */ - TWI_MASTER_CMD_RECVTRANS_gc = (0x02<<0), /* Receive or Transmit Data */ - TWI_MASTER_CMD_STOP_gc = (0x03<<0), /* Issue Stop Condition */ -} TWI_MASTER_CMD_t; - -/* Master Bus State */ -typedef enum TWI_MASTER_BUSSTATE_enum -{ - TWI_MASTER_BUSSTATE_UNKNOWN_gc = (0x00<<0), /* Unknown Bus State */ - TWI_MASTER_BUSSTATE_IDLE_gc = (0x01<<0), /* Bus is Idle */ - TWI_MASTER_BUSSTATE_OWNER_gc = (0x02<<0), /* This Module Controls The Bus */ - TWI_MASTER_BUSSTATE_BUSY_gc = (0x03<<0), /* The Bus is Busy */ -} TWI_MASTER_BUSSTATE_t; - -/* Slave Interrupt Level */ -typedef enum TWI_SLAVE_INTLVL_enum -{ - TWI_SLAVE_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ - TWI_SLAVE_INTLVL_LO_gc = (0x01<<6), /* Low Level */ - TWI_SLAVE_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ - TWI_SLAVE_INTLVL_HI_gc = (0x03<<6), /* High Level */ -} TWI_SLAVE_INTLVL_t; - -/* Slave Command */ -typedef enum TWI_SLAVE_CMD_enum -{ - TWI_SLAVE_CMD_NOACT_gc = (0x00<<0), /* No Action */ - TWI_SLAVE_CMD_COMPTRANS_gc = (0x02<<0), /* Used To Complete a Transaction */ - TWI_SLAVE_CMD_RESPONSE_gc = (0x03<<0), /* Used in Response to Address/Data Interrupt */ -} TWI_SLAVE_CMD_t; - - -/* --------------------------------------------------------------------------- -PORT - Port Configuration --------------------------------------------------------------------------- -*/ - -/* I/O port Configuration */ -typedef struct PORTCFG_struct -{ - register8_t MPCMASK; /* Multi-pin Configuration Mask */ - register8_t reserved_0x01; - register8_t VPCTRLA; /* Virtual Port Control Register A */ - register8_t VPCTRLB; /* Virtual Port Control Register B */ - register8_t CLKEVOUT; /* Clock and Event Out Register */ -} PORTCFG_t; - -/* --------------------------------------------------------------------------- -PORT - Port Configuration --------------------------------------------------------------------------- -*/ - -/* Virtual Port */ -typedef struct VPORT_struct -{ - register8_t DIR; /* I/O Port Data Direction */ - register8_t OUT; /* I/O Port Output */ - register8_t IN; /* I/O Port Input */ - register8_t INTFLAGS; /* Interrupt Flag Register */ -} VPORT_t; - -/* --------------------------------------------------------------------------- -PORT - Port Configuration --------------------------------------------------------------------------- -*/ - -/* I/O Ports */ -typedef struct PORT_struct -{ - register8_t DIR; /* I/O Port Data Direction */ - register8_t DIRSET; /* I/O Port Data Direction Set */ - register8_t DIRCLR; /* I/O Port Data Direction Clear */ - register8_t DIRTGL; /* I/O Port Data Direction Toggle */ - register8_t OUT; /* I/O Port Output */ - register8_t OUTSET; /* I/O Port Output Set */ - register8_t OUTCLR; /* I/O Port Output Clear */ - register8_t OUTTGL; /* I/O Port Output Toggle */ - register8_t IN; /* I/O port Input */ - register8_t INTCTRL; /* Interrupt Control Register */ - register8_t INT0MASK; /* Port Interrupt 0 Mask */ - register8_t INT1MASK; /* Port Interrupt 1 Mask */ - register8_t INTFLAGS; /* Interrupt Flag Register */ - register8_t reserved_0x0D; - register8_t reserved_0x0E; - register8_t reserved_0x0F; - register8_t PIN0CTRL; /* Pin 0 Control Register */ - register8_t PIN1CTRL; /* Pin 1 Control Register */ - register8_t PIN2CTRL; /* Pin 2 Control Register */ - register8_t PIN3CTRL; /* Pin 3 Control Register */ - register8_t PIN4CTRL; /* Pin 4 Control Register */ - register8_t PIN5CTRL; /* Pin 5 Control Register */ - register8_t PIN6CTRL; /* Pin 6 Control Register */ - register8_t PIN7CTRL; /* Pin 7 Control Register */ -} PORT_t; - -/* Virtual Port 0 Mapping */ -typedef enum PORTCFG_VP0MAP_enum -{ - PORTCFG_VP0MAP_PORTA_gc = (0x00<<0), /* Mapped To PORTA */ - PORTCFG_VP0MAP_PORTB_gc = (0x01<<0), /* Mapped To PORTB */ - PORTCFG_VP0MAP_PORTC_gc = (0x02<<0), /* Mapped To PORTC */ - PORTCFG_VP0MAP_PORTD_gc = (0x03<<0), /* Mapped To PORTD */ - PORTCFG_VP0MAP_PORTE_gc = (0x04<<0), /* Mapped To PORTE */ - PORTCFG_VP0MAP_PORTF_gc = (0x05<<0), /* Mapped To PORTF */ - PORTCFG_VP0MAP_PORTG_gc = (0x06<<0), /* Mapped To PORTG */ - PORTCFG_VP0MAP_PORTH_gc = (0x07<<0), /* Mapped To PORTH */ - PORTCFG_VP0MAP_PORTJ_gc = (0x08<<0), /* Mapped To PORTJ */ - PORTCFG_VP0MAP_PORTK_gc = (0x09<<0), /* Mapped To PORTK */ - PORTCFG_VP0MAP_PORTL_gc = (0x0A<<0), /* Mapped To PORTL */ - PORTCFG_VP0MAP_PORTM_gc = (0x0B<<0), /* Mapped To PORTM */ - PORTCFG_VP0MAP_PORTN_gc = (0x0C<<0), /* Mapped To PORTN */ - PORTCFG_VP0MAP_PORTP_gc = (0x0D<<0), /* Mapped To PORTP */ - PORTCFG_VP0MAP_PORTQ_gc = (0x0E<<0), /* Mapped To PORTQ */ - PORTCFG_VP0MAP_PORTR_gc = (0x0F<<0), /* Mapped To PORTR */ -} PORTCFG_VP0MAP_t; - -/* Virtual Port 1 Mapping */ -typedef enum PORTCFG_VP1MAP_enum -{ - PORTCFG_VP1MAP_PORTA_gc = (0x00<<4), /* Mapped To PORTA */ - PORTCFG_VP1MAP_PORTB_gc = (0x01<<4), /* Mapped To PORTB */ - PORTCFG_VP1MAP_PORTC_gc = (0x02<<4), /* Mapped To PORTC */ - PORTCFG_VP1MAP_PORTD_gc = (0x03<<4), /* Mapped To PORTD */ - PORTCFG_VP1MAP_PORTE_gc = (0x04<<4), /* Mapped To PORTE */ - PORTCFG_VP1MAP_PORTF_gc = (0x05<<4), /* Mapped To PORTF */ - PORTCFG_VP1MAP_PORTG_gc = (0x06<<4), /* Mapped To PORTG */ - PORTCFG_VP1MAP_PORTH_gc = (0x07<<4), /* Mapped To PORTH */ - PORTCFG_VP1MAP_PORTJ_gc = (0x08<<4), /* Mapped To PORTJ */ - PORTCFG_VP1MAP_PORTK_gc = (0x09<<4), /* Mapped To PORTK */ - PORTCFG_VP1MAP_PORTL_gc = (0x0A<<4), /* Mapped To PORTL */ - PORTCFG_VP1MAP_PORTM_gc = (0x0B<<4), /* Mapped To PORTM */ - PORTCFG_VP1MAP_PORTN_gc = (0x0C<<4), /* Mapped To PORTN */ - PORTCFG_VP1MAP_PORTP_gc = (0x0D<<4), /* Mapped To PORTP */ - PORTCFG_VP1MAP_PORTQ_gc = (0x0E<<4), /* Mapped To PORTQ */ - PORTCFG_VP1MAP_PORTR_gc = (0x0F<<4), /* Mapped To PORTR */ -} PORTCFG_VP1MAP_t; - -/* Virtual Port 2 Mapping */ -typedef enum PORTCFG_VP2MAP_enum -{ - PORTCFG_VP2MAP_PORTA_gc = (0x00<<0), /* Mapped To PORTA */ - PORTCFG_VP2MAP_PORTB_gc = (0x01<<0), /* Mapped To PORTB */ - PORTCFG_VP2MAP_PORTC_gc = (0x02<<0), /* Mapped To PORTC */ - PORTCFG_VP2MAP_PORTD_gc = (0x03<<0), /* Mapped To PORTD */ - PORTCFG_VP2MAP_PORTE_gc = (0x04<<0), /* Mapped To PORTE */ - PORTCFG_VP2MAP_PORTF_gc = (0x05<<0), /* Mapped To PORTF */ - PORTCFG_VP2MAP_PORTG_gc = (0x06<<0), /* Mapped To PORTG */ - PORTCFG_VP2MAP_PORTH_gc = (0x07<<0), /* Mapped To PORTH */ - PORTCFG_VP2MAP_PORTJ_gc = (0x08<<0), /* Mapped To PORTJ */ - PORTCFG_VP2MAP_PORTK_gc = (0x09<<0), /* Mapped To PORTK */ - PORTCFG_VP2MAP_PORTL_gc = (0x0A<<0), /* Mapped To PORTL */ - PORTCFG_VP2MAP_PORTM_gc = (0x0B<<0), /* Mapped To PORTM */ - PORTCFG_VP2MAP_PORTN_gc = (0x0C<<0), /* Mapped To PORTN */ - PORTCFG_VP2MAP_PORTP_gc = (0x0D<<0), /* Mapped To PORTP */ - PORTCFG_VP2MAP_PORTQ_gc = (0x0E<<0), /* Mapped To PORTQ */ - PORTCFG_VP2MAP_PORTR_gc = (0x0F<<0), /* Mapped To PORTR */ -} PORTCFG_VP2MAP_t; - -/* Virtual Port 3 Mapping */ -typedef enum PORTCFG_VP3MAP_enum -{ - PORTCFG_VP3MAP_PORTA_gc = (0x00<<4), /* Mapped To PORTA */ - PORTCFG_VP3MAP_PORTB_gc = (0x01<<4), /* Mapped To PORTB */ - PORTCFG_VP3MAP_PORTC_gc = (0x02<<4), /* Mapped To PORTC */ - PORTCFG_VP3MAP_PORTD_gc = (0x03<<4), /* Mapped To PORTD */ - PORTCFG_VP3MAP_PORTE_gc = (0x04<<4), /* Mapped To PORTE */ - PORTCFG_VP3MAP_PORTF_gc = (0x05<<4), /* Mapped To PORTF */ - PORTCFG_VP3MAP_PORTG_gc = (0x06<<4), /* Mapped To PORTG */ - PORTCFG_VP3MAP_PORTH_gc = (0x07<<4), /* Mapped To PORTH */ - PORTCFG_VP3MAP_PORTJ_gc = (0x08<<4), /* Mapped To PORTJ */ - PORTCFG_VP3MAP_PORTK_gc = (0x09<<4), /* Mapped To PORTK */ - PORTCFG_VP3MAP_PORTL_gc = (0x0A<<4), /* Mapped To PORTL */ - PORTCFG_VP3MAP_PORTM_gc = (0x0B<<4), /* Mapped To PORTM */ - PORTCFG_VP3MAP_PORTN_gc = (0x0C<<4), /* Mapped To PORTN */ - PORTCFG_VP3MAP_PORTP_gc = (0x0D<<4), /* Mapped To PORTP */ - PORTCFG_VP3MAP_PORTQ_gc = (0x0E<<4), /* Mapped To PORTQ */ - PORTCFG_VP3MAP_PORTR_gc = (0x0F<<4), /* Mapped To PORTR */ -} PORTCFG_VP3MAP_t; - -/* Clock Output Port */ -typedef enum PORTCFG_CLKOUT_enum -{ - PORTCFG_CLKOUT_OFF_gc = (0x00<<0), /* Clock Output Disabled */ - PORTCFG_CLKOUT_PC7_gc = (0x01<<0), /* Clock Output on Port C pin 7 */ - PORTCFG_CLKOUT_PD7_gc = (0x02<<0), /* Clock Output on Port D pin 7 */ - PORTCFG_CLKOUT_PE7_gc = (0x03<<0), /* Clock Output on Port E pin 7 */ -} PORTCFG_CLKOUT_t; - -/* Event Output Port */ -typedef enum PORTCFG_EVOUT_enum -{ - PORTCFG_EVOUT_OFF_gc = (0x00<<4), /* Event Output Disabled */ - PORTCFG_EVOUT_PC7_gc = (0x01<<4), /* Event Channel 7 Output on Port C pin 7 */ - PORTCFG_EVOUT_PD7_gc = (0x02<<4), /* Event Channel 7 Output on Port D pin 7 */ - PORTCFG_EVOUT_PE7_gc = (0x03<<4), /* Event Channel 7 Output on Port E pin 7 */ -} PORTCFG_EVOUT_t; - -/* Port Interrupt 0 Level */ -typedef enum PORT_INT0LVL_enum -{ - PORT_INT0LVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - PORT_INT0LVL_LO_gc = (0x01<<0), /* Low Level */ - PORT_INT0LVL_MED_gc = (0x02<<0), /* Medium Level */ - PORT_INT0LVL_HI_gc = (0x03<<0), /* High Level */ -} PORT_INT0LVL_t; - -/* Port Interrupt 1 Level */ -typedef enum PORT_INT1LVL_enum -{ - PORT_INT1LVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ - PORT_INT1LVL_LO_gc = (0x01<<2), /* Low Level */ - PORT_INT1LVL_MED_gc = (0x02<<2), /* Medium Level */ - PORT_INT1LVL_HI_gc = (0x03<<2), /* High Level */ -} PORT_INT1LVL_t; - -/* Output/Pull Configuration */ -typedef enum PORT_OPC_enum -{ - PORT_OPC_TOTEM_gc = (0x00<<3), /* Totempole */ - PORT_OPC_BUSKEEPER_gc = (0x01<<3), /* Totempole w/ Bus keeper on Input and Output */ - PORT_OPC_PULLDOWN_gc = (0x02<<3), /* Totempole w/ Pull-down on Input */ - PORT_OPC_PULLUP_gc = (0x03<<3), /* Totempole w/ Pull-up on Input */ - PORT_OPC_WIREDOR_gc = (0x04<<3), /* Wired OR */ - PORT_OPC_WIREDAND_gc = (0x05<<3), /* Wired AND */ - PORT_OPC_WIREDORPULL_gc = (0x06<<3), /* Wired OR w/ Pull-down */ - PORT_OPC_WIREDANDPULL_gc = (0x07<<3), /* Wired AND w/ Pull-up */ -} PORT_OPC_t; - -/* Input/Sense Configuration */ -typedef enum PORT_ISC_enum -{ - PORT_ISC_BOTHEDGES_gc = (0x00<<0), /* Sense Both Edges */ - PORT_ISC_RISING_gc = (0x01<<0), /* Sense Rising Edge */ - PORT_ISC_FALLING_gc = (0x02<<0), /* Sense Falling Edge */ - PORT_ISC_LEVEL_gc = (0x03<<0), /* Sense Level (Transparent For Events) */ - PORT_ISC_INPUT_DISABLE_gc = (0x07<<0), /* Disable Digital Input Buffer */ -} PORT_ISC_t; - - -/* --------------------------------------------------------------------------- -TC - 16-bit Timer/Counter With PWM --------------------------------------------------------------------------- -*/ - -/* 16-bit Timer/Counter 0 */ -typedef struct TC0_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t CTRLC; /* Control register C */ - register8_t CTRLD; /* Control Register D */ - register8_t CTRLE; /* Control Register E */ - register8_t reserved_0x05; - register8_t INTCTRLA; /* Interrupt Control Register A */ - register8_t INTCTRLB; /* Interrupt Control Register B */ - register8_t CTRLFCLR; /* Control Register F Clear */ - register8_t CTRLFSET; /* Control Register F Set */ - register8_t CTRLGCLR; /* Control Register G Clear */ - register8_t CTRLGSET; /* Control Register G Set */ - register8_t INTFLAGS; /* Interrupt Flag Register */ - register8_t reserved_0x0D; - register8_t reserved_0x0E; - register8_t TEMP; /* Temporary Register For 16-bit Access */ - register8_t reserved_0x10; - register8_t reserved_0x11; - register8_t reserved_0x12; - register8_t reserved_0x13; - register8_t reserved_0x14; - register8_t reserved_0x15; - register8_t reserved_0x16; - register8_t reserved_0x17; - register8_t reserved_0x18; - register8_t reserved_0x19; - register8_t reserved_0x1A; - register8_t reserved_0x1B; - register8_t reserved_0x1C; - register8_t reserved_0x1D; - register8_t reserved_0x1E; - register8_t reserved_0x1F; - _WORDREGISTER(CNT); /* Count */ - register8_t reserved_0x22; - register8_t reserved_0x23; - register8_t reserved_0x24; - register8_t reserved_0x25; - _WORDREGISTER(PER); /* Period */ - _WORDREGISTER(CCA); /* Compare or Capture A */ - _WORDREGISTER(CCB); /* Compare or Capture B */ - _WORDREGISTER(CCC); /* Compare or Capture C */ - _WORDREGISTER(CCD); /* Compare or Capture D */ - register8_t reserved_0x30; - register8_t reserved_0x31; - register8_t reserved_0x32; - register8_t reserved_0x33; - register8_t reserved_0x34; - register8_t reserved_0x35; - _WORDREGISTER(PERBUF); /* Period Buffer */ - _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ - _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ - _WORDREGISTER(CCCBUF); /* Compare Or Capture C Buffer */ - _WORDREGISTER(CCDBUF); /* Compare Or Capture D Buffer */ -} TC0_t; - -/* --------------------------------------------------------------------------- -TC - 16-bit Timer/Counter With PWM --------------------------------------------------------------------------- -*/ - -/* 16-bit Timer/Counter 1 */ -typedef struct TC1_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t CTRLC; /* Control register C */ - register8_t CTRLD; /* Control Register D */ - register8_t CTRLE; /* Control Register E */ - register8_t reserved_0x05; - register8_t INTCTRLA; /* Interrupt Control Register A */ - register8_t INTCTRLB; /* Interrupt Control Register B */ - register8_t CTRLFCLR; /* Control Register F Clear */ - register8_t CTRLFSET; /* Control Register F Set */ - register8_t CTRLGCLR; /* Control Register G Clear */ - register8_t CTRLGSET; /* Control Register G Set */ - register8_t INTFLAGS; /* Interrupt Flag Register */ - register8_t reserved_0x0D; - register8_t reserved_0x0E; - register8_t TEMP; /* Temporary Register For 16-bit Access */ - register8_t reserved_0x10; - register8_t reserved_0x11; - register8_t reserved_0x12; - register8_t reserved_0x13; - register8_t reserved_0x14; - register8_t reserved_0x15; - register8_t reserved_0x16; - register8_t reserved_0x17; - register8_t reserved_0x18; - register8_t reserved_0x19; - register8_t reserved_0x1A; - register8_t reserved_0x1B; - register8_t reserved_0x1C; - register8_t reserved_0x1D; - register8_t reserved_0x1E; - register8_t reserved_0x1F; - _WORDREGISTER(CNT); /* Count */ - register8_t reserved_0x22; - register8_t reserved_0x23; - register8_t reserved_0x24; - register8_t reserved_0x25; - _WORDREGISTER(PER); /* Period */ - _WORDREGISTER(CCA); /* Compare or Capture A */ - _WORDREGISTER(CCB); /* Compare or Capture B */ - register8_t reserved_0x2C; - register8_t reserved_0x2D; - register8_t reserved_0x2E; - register8_t reserved_0x2F; - register8_t reserved_0x30; - register8_t reserved_0x31; - register8_t reserved_0x32; - register8_t reserved_0x33; - register8_t reserved_0x34; - register8_t reserved_0x35; - _WORDREGISTER(PERBUF); /* Period Buffer */ - _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ - _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ -} TC1_t; - -/* --------------------------------------------------------------------------- -TC - 16-bit Timer/Counter With PWM --------------------------------------------------------------------------- -*/ - -/* Advanced Waveform Extension */ -typedef struct AWEX_struct -{ - register8_t CTRL; /* Control Register */ - register8_t reserved_0x01; - register8_t FDEMASK; /* Fault Detection Event Mask */ - register8_t FDCTRL; /* Fault Detection Control Register */ - register8_t STATUS; /* Status Register */ - register8_t reserved_0x05; - register8_t DTBOTH; /* Dead Time Both Sides */ - register8_t DTBOTHBUF; /* Dead Time Both Sides Buffer */ - register8_t DTLS; /* Dead Time Low Side */ - register8_t DTHS; /* Dead Time High Side */ - register8_t DTLSBUF; /* Dead Time Low Side Buffer */ - register8_t DTHSBUF; /* Dead Time High Side Buffer */ - register8_t OUTOVEN; /* Output Override Enable */ -} AWEX_t; - -/* --------------------------------------------------------------------------- -TC - 16-bit Timer/Counter With PWM --------------------------------------------------------------------------- -*/ - -/* High-Resolution Extension */ -typedef struct HIRES_struct -{ - register8_t CTRLA; /* Control Register */ -} HIRES_t; - -/* Clock Selection */ -typedef enum TC_CLKSEL_enum -{ - TC_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */ - TC_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */ - TC_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */ - TC_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */ - TC_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */ - TC_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */ - TC_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */ - TC_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */ - TC_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */ - TC_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */ - TC_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */ - TC_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */ - TC_CLKSEL_EVCH4_gc = (0x0C<<0), /* Event Channel 4 */ - TC_CLKSEL_EVCH5_gc = (0x0D<<0), /* Event Channel 5 */ - TC_CLKSEL_EVCH6_gc = (0x0E<<0), /* Event Channel 6 */ - TC_CLKSEL_EVCH7_gc = (0x0F<<0), /* Event Channel 7 */ -} TC_CLKSEL_t; - -/* Waveform Generation Mode */ -typedef enum TC_WGMODE_enum -{ - TC_WGMODE_NORMAL_gc = (0x00<<0), /* Normal Mode */ - TC_WGMODE_FRQ_gc = (0x01<<0), /* Frequency Generation Mode */ - TC_WGMODE_SS_gc = (0x03<<0), /* Single Slope */ - TC_WGMODE_DS_T_gc = (0x05<<0), /* Dual Slope, Update on TOP */ - TC_WGMODE_DS_TB_gc = (0x06<<0), /* Dual Slope, Update on TOP and BOTTOM */ - TC_WGMODE_DS_B_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */ -} TC_WGMODE_t; - -/* Event Action */ -typedef enum TC_EVACT_enum -{ - TC_EVACT_OFF_gc = (0x00<<5), /* No Event Action */ - TC_EVACT_CAPT_gc = (0x01<<5), /* Input Capture */ - TC_EVACT_UPDOWN_gc = (0x02<<5), /* Externally Controlled Up/Down Count */ - TC_EVACT_QDEC_gc = (0x03<<5), /* Quadrature Decode */ - TC_EVACT_RESTART_gc = (0x04<<5), /* Restart */ - TC_EVACT_FRQ_gc = (0x05<<5), /* Frequency Capture */ - TC_EVACT_PW_gc = (0x06<<5), /* Pulse-width Capture */ -} TC_EVACT_t; - -/* Event Selection */ -typedef enum TC_EVSEL_enum -{ - TC_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ - TC_EVSEL_CH0_gc = (0x08<<0), /* Event Channel 0 */ - TC_EVSEL_CH1_gc = (0x09<<0), /* Event Channel 1 */ - TC_EVSEL_CH2_gc = (0x0A<<0), /* Event Channel 2 */ - TC_EVSEL_CH3_gc = (0x0B<<0), /* Event Channel 3 */ - TC_EVSEL_CH4_gc = (0x0C<<0), /* Event Channel 4 */ - TC_EVSEL_CH5_gc = (0x0D<<0), /* Event Channel 5 */ - TC_EVSEL_CH6_gc = (0x0E<<0), /* Event Channel 6 */ - TC_EVSEL_CH7_gc = (0x0F<<0), /* Event Channel 7 */ -} TC_EVSEL_t; - -/* Error Interrupt Level */ -typedef enum TC_ERRINTLVL_enum -{ - TC_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ - TC_ERRINTLVL_LO_gc = (0x01<<2), /* Low Level */ - TC_ERRINTLVL_MED_gc = (0x02<<2), /* Medium Level */ - TC_ERRINTLVL_HI_gc = (0x03<<2), /* High Level */ -} TC_ERRINTLVL_t; - -/* Overflow Interrupt Level */ -typedef enum TC_OVFINTLVL_enum -{ - TC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - TC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ - TC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ - TC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ -} TC_OVFINTLVL_t; - -/* Compare or Capture D Interrupt Level */ -typedef enum TC_CCDINTLVL_enum -{ - TC_CCDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ - TC_CCDINTLVL_LO_gc = (0x01<<6), /* Low Level */ - TC_CCDINTLVL_MED_gc = (0x02<<6), /* Medium Level */ - TC_CCDINTLVL_HI_gc = (0x03<<6), /* High Level */ -} TC_CCDINTLVL_t; - -/* Compare or Capture C Interrupt Level */ -typedef enum TC_CCCINTLVL_enum -{ - TC_CCCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ - TC_CCCINTLVL_LO_gc = (0x01<<4), /* Low Level */ - TC_CCCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ - TC_CCCINTLVL_HI_gc = (0x03<<4), /* High Level */ -} TC_CCCINTLVL_t; - -/* Compare or Capture B Interrupt Level */ -typedef enum TC_CCBINTLVL_enum -{ - TC_CCBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ - TC_CCBINTLVL_LO_gc = (0x01<<2), /* Low Level */ - TC_CCBINTLVL_MED_gc = (0x02<<2), /* Medium Level */ - TC_CCBINTLVL_HI_gc = (0x03<<2), /* High Level */ -} TC_CCBINTLVL_t; - -/* Compare or Capture A Interrupt Level */ -typedef enum TC_CCAINTLVL_enum -{ - TC_CCAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - TC_CCAINTLVL_LO_gc = (0x01<<0), /* Low Level */ - TC_CCAINTLVL_MED_gc = (0x02<<0), /* Medium Level */ - TC_CCAINTLVL_HI_gc = (0x03<<0), /* High Level */ -} TC_CCAINTLVL_t; - -/* Timer/Counter Command */ -typedef enum TC_CMD_enum -{ - TC_CMD_NONE_gc = (0x00<<2), /* No Command */ - TC_CMD_UPDATE_gc = (0x01<<2), /* Force Update */ - TC_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ - TC_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ -} TC_CMD_t; - -/* Fault Detect Action */ -typedef enum AWEX_FDACT_enum -{ - AWEX_FDACT_NONE_gc = (0x00<<0), /* No Fault Protection */ - AWEX_FDACT_CLEAROE_gc = (0x01<<0), /* Clear Output Enable Bits */ - AWEX_FDACT_CLEARDIR_gc = (0x03<<0), /* Clear I/O Port Direction Bits */ -} AWEX_FDACT_t; - -/* High Resolution Enable */ -typedef enum HIRES_HREN_enum -{ - HIRES_HREN_NONE_gc = (0x00<<0), /* No Fault Protection */ - HIRES_HREN_TC0_gc = (0x01<<0), /* Enable High Resolution on Timer/Counter 0 */ - HIRES_HREN_TC1_gc = (0x02<<0), /* Enable High Resolution on Timer/Counter 1 */ - HIRES_HREN_BOTH_gc = (0x03<<0), /* Enable High Resolution both Timer/Counters */ -} HIRES_HREN_t; - - -/* --------------------------------------------------------------------------- -USART - Universal Asynchronous Receiver-Transmitter --------------------------------------------------------------------------- -*/ - -/* Universal Synchronous/Asynchronous Receiver/Transmitter */ -typedef struct USART_struct -{ - register8_t DATA; /* Data Register */ - register8_t STATUS; /* Status Register */ - register8_t reserved_0x02; - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t CTRLC; /* Control Register C */ - register8_t BAUDCTRLA; /* Baud Rate Control Register A */ - register8_t BAUDCTRLB; /* Baud Rate Control Register B */ -} USART_t; - -/* Receive Complete Interrupt level */ -typedef enum USART_RXCINTLVL_enum -{ - USART_RXCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ - USART_RXCINTLVL_LO_gc = (0x01<<4), /* Low Level */ - USART_RXCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ - USART_RXCINTLVL_HI_gc = (0x03<<4), /* High Level */ -} USART_RXCINTLVL_t; - -/* Transmit Complete Interrupt level */ -typedef enum USART_TXCINTLVL_enum -{ - USART_TXCINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ - USART_TXCINTLVL_LO_gc = (0x01<<2), /* Low Level */ - USART_TXCINTLVL_MED_gc = (0x02<<2), /* Medium Level */ - USART_TXCINTLVL_HI_gc = (0x03<<2), /* High Level */ -} USART_TXCINTLVL_t; - -/* Data Register Empty Interrupt level */ -typedef enum USART_DREINTLVL_enum -{ - USART_DREINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - USART_DREINTLVL_LO_gc = (0x01<<0), /* Low Level */ - USART_DREINTLVL_MED_gc = (0x02<<0), /* Medium Level */ - USART_DREINTLVL_HI_gc = (0x03<<0), /* High Level */ -} USART_DREINTLVL_t; - -/* Character Size */ -typedef enum USART_CHSIZE_enum -{ - USART_CHSIZE_5BIT_gc = (0x00<<0), /* Character size: 5 bit */ - USART_CHSIZE_6BIT_gc = (0x01<<0), /* Character size: 6 bit */ - USART_CHSIZE_7BIT_gc = (0x02<<0), /* Character size: 7 bit */ - USART_CHSIZE_8BIT_gc = (0x03<<0), /* Character size: 8 bit */ - USART_CHSIZE_9BIT_gc = (0x07<<0), /* Character size: 9 bit */ -} USART_CHSIZE_t; - -/* Communication Mode */ -typedef enum USART_CMODE_enum -{ - USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6), /* Asynchronous Mode */ - USART_CMODE_SYNCHRONOUS_gc = (0x01<<6), /* Synchronous Mode */ - USART_CMODE_IRDA_gc = (0x02<<6), /* IrDA Mode */ - USART_CMODE_MSPI_gc = (0x03<<6), /* Master SPI Mode */ -} USART_CMODE_t; - -/* Parity Mode */ -typedef enum USART_PMODE_enum -{ - USART_PMODE_DISABLED_gc = (0x00<<4), /* No Parity */ - USART_PMODE_EVEN_gc = (0x02<<4), /* Even Parity */ - USART_PMODE_ODD_gc = (0x03<<4), /* Odd Parity */ -} USART_PMODE_t; - - -/* --------------------------------------------------------------------------- -SPI - Serial Peripheral Interface --------------------------------------------------------------------------- -*/ - -/* Serial Peripheral Interface */ -typedef struct SPI_struct -{ - register8_t CTRL; /* Control Register */ - register8_t INTCTRL; /* Interrupt Control Register */ - register8_t STATUS; /* Status Register */ - register8_t DATA; /* Data Register */ -} SPI_t; - -/* SPI Mode */ -typedef enum SPI_MODE_enum -{ - SPI_MODE_0_gc = (0x00<<2), /* SPI Mode 0 */ - SPI_MODE_1_gc = (0x01<<2), /* SPI Mode 1 */ - SPI_MODE_2_gc = (0x02<<2), /* SPI Mode 2 */ - SPI_MODE_3_gc = (0x03<<2), /* SPI Mode 3 */ -} SPI_MODE_t; - -/* Prescaler setting */ -typedef enum SPI_PRESCALER_enum -{ - SPI_PRESCALER_DIV4_gc = (0x00<<0), /* System Clock / 4 */ - SPI_PRESCALER_DIV16_gc = (0x01<<0), /* System Clock / 16 */ - SPI_PRESCALER_DIV64_gc = (0x02<<0), /* System Clock / 64 */ - SPI_PRESCALER_DIV128_gc = (0x03<<0), /* System Clock / 128 */ -} SPI_PRESCALER_t; - -/* Interrupt level */ -typedef enum SPI_INTLVL_enum -{ - SPI_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - SPI_INTLVL_LO_gc = (0x01<<0), /* Low Level */ - SPI_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ - SPI_INTLVL_HI_gc = (0x03<<0), /* High Level */ -} SPI_INTLVL_t; - - -/* --------------------------------------------------------------------------- -IRCOM - IR Communication Module --------------------------------------------------------------------------- -*/ - -/* IR Communication Module */ -typedef struct IRCOM_struct -{ - register8_t CTRL; /* Control Register */ - register8_t TXPLCTRL; /* IrDA Transmitter Pulse Length Control Register */ - register8_t RXPLCTRL; /* IrDA Receiver Pulse Length Control Register */ -} IRCOM_t; - -/* Event channel selection */ -typedef enum IRDA_EVSEL_enum -{ - IRDA_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ - IRDA_EVSEL_0_gc = (0x08<<0), /* Event Channel 0 */ - IRDA_EVSEL_1_gc = (0x09<<0), /* Event Channel 1 */ - IRDA_EVSEL_2_gc = (0x0A<<0), /* Event Channel 2 */ - IRDA_EVSEL_3_gc = (0x0B<<0), /* Event Channel 3 */ - IRDA_EVSEL_4_gc = (0x0C<<0), /* Event Channel 4 */ - IRDA_EVSEL_5_gc = (0x0D<<0), /* Event Channel 5 */ - IRDA_EVSEL_6_gc = (0x0E<<0), /* Event Channel 6 */ - IRDA_EVSEL_7_gc = (0x0F<<0), /* Event Channel 7 */ -} IRDA_EVSEL_t; - - - -/* -========================================================================== -IO Module Instances. Mapped to memory. -========================================================================== -*/ - -#define VPORT0 (*(VPORT_t *) 0x0010) /* Virtual Port 0 */ -#define VPORT1 (*(VPORT_t *) 0x0014) /* Virtual Port 1 */ -#define VPORT2 (*(VPORT_t *) 0x0018) /* Virtual Port 2 */ -#define VPORT3 (*(VPORT_t *) 0x001C) /* Virtual Port 3 */ -#define OCD (*(OCD_t *) 0x002E) /* On-Chip Debug System */ -#define CLK (*(CLK_t *) 0x0040) /* Clock System */ -#define SLEEP (*(SLEEP_t *) 0x0048) /* Sleep Controller */ -#define OSC (*(OSC_t *) 0x0050) /* Oscillator Control */ -#define DFLLRC32M (*(DFLL_t *) 0x0060) /* DFLL for 32MHz RC Oscillator */ -#define DFLLRC2M (*(DFLL_t *) 0x0068) /* DFLL for 2MHz RC Oscillator */ -#define PR (*(PR_t *) 0x0070) /* Power Reduction */ -#define RST (*(RST_t *) 0x0078) /* Reset Controller */ -#define WDT (*(WDT_t *) 0x0080) /* Watch-Dog Timer */ -#define MCU (*(MCU_t *) 0x0090) /* MCU Control */ -#define PMIC (*(PMIC_t *) 0x00A0) /* Programmable Interrupt Controller */ -#define PORTCFG (*(PORTCFG_t *) 0x00B0) /* Port Configuration */ -#define CRC (*(CRC_t *) 0x00D0) /* Cyclic Redundancy Checker */ -#define EVSYS (*(EVSYS_t *) 0x0180) /* Event System */ -#define NVM (*(NVM_t *) 0x01C0) /* Non Volatile Memory Controller */ -#define ADCA (*(ADC_t *) 0x0200) /* Analog to Digital Converter A */ -#define ACA (*(AC_t *) 0x0380) /* Analog Comparator A */ -#define RTC (*(RTC_t *) 0x0400) /* Real-Time Counter */ -#define TWIC (*(TWI_t *) 0x0480) /* Two-Wire Interface C */ -#define TWIE (*(TWI_t *) 0x04A0) /* Two-Wire Interface E */ -#define PORTA (*(PORT_t *) 0x0600) /* Port A */ -#define PORTB (*(PORT_t *) 0x0620) /* Port B */ -#define PORTC (*(PORT_t *) 0x0640) /* Port C */ -#define PORTD (*(PORT_t *) 0x0660) /* Port D */ -#define PORTE (*(PORT_t *) 0x0680) /* Port E */ -#define PORTF (*(PORT_t *) 0x06A0) /* Port F */ -#define PORTR (*(PORT_t *) 0x07E0) /* Port R */ -#define TCC0 (*(TC0_t *) 0x0800) /* Timer/Counter C0 */ -#define TCC1 (*(TC1_t *) 0x0840) /* Timer/Counter C1 */ -#define AWEXC (*(AWEX_t *) 0x0880) /* Advanced Waveform Extension C */ -#define HIRESC (*(HIRES_t *) 0x0890) /* High-Resolution Extension C */ -#define USARTC0 (*(USART_t *) 0x08A0) /* Universal Asynchronous Receiver-Transmitter C0 */ -#define SPIC (*(SPI_t *) 0x08C0) /* Serial Peripheral Interface C */ -#define IRCOM (*(IRCOM_t *) 0x08F8) /* IR Communication Module */ -#define TCD0 (*(TC0_t *) 0x0900) /* Timer/Counter D0 */ -#define USARTD0 (*(USART_t *) 0x09A0) /* Universal Asynchronous Receiver-Transmitter D0 */ -#define SPID (*(SPI_t *) 0x09C0) /* Serial Peripheral Interface D */ -#define TCE0 (*(TC0_t *) 0x0A00) /* Timer/Counter E0 */ -#define AWEXE (*(AWEX_t *) 0x0A80) /* Advanced Waveform Extension E */ -#define USARTE0 (*(USART_t *) 0x0AA0) /* Universal Asynchronous Receiver-Transmitter E0 */ -#define SPIE (*(SPI_t *) 0x0AC0) /* Serial Peripheral Interface E */ -#define TCF0 (*(TC0_t *) 0x0B00) /* Timer/Counter F0 */ - - -#endif /* !defined (__ASSEMBLER__) */ - - -/* ========== Flattened fully qualified IO register names ========== */ - -/* GPIO - General Purpose IO Registers */ -#define GPIO_GPIOR0 _SFR_MEM8(0x0000) -#define GPIO_GPIOR1 _SFR_MEM8(0x0001) -#define GPIO_GPIOR2 _SFR_MEM8(0x0002) -#define GPIO_GPIOR3 _SFR_MEM8(0x0003) -#define GPIO_GPIOR4 _SFR_MEM8(0x0004) -#define GPIO_GPIOR5 _SFR_MEM8(0x0005) -#define GPIO_GPIOR6 _SFR_MEM8(0x0006) -#define GPIO_GPIOR7 _SFR_MEM8(0x0007) -#define GPIO_GPIOR8 _SFR_MEM8(0x0008) -#define GPIO_GPIOR9 _SFR_MEM8(0x0009) -#define GPIO_GPIORA _SFR_MEM8(0x000A) -#define GPIO_GPIORB _SFR_MEM8(0x000B) -#define GPIO_GPIORC _SFR_MEM8(0x000C) -#define GPIO_GPIORD _SFR_MEM8(0x000D) -#define GPIO_GPIORE _SFR_MEM8(0x000E) -#define GPIO_GPIORF _SFR_MEM8(0x000F) - -/* VPORT0 - Virtual Port 0 */ -#define VPORT0_DIR _SFR_MEM8(0x0010) -#define VPORT0_OUT _SFR_MEM8(0x0011) -#define VPORT0_IN _SFR_MEM8(0x0012) -#define VPORT0_INTFLAGS _SFR_MEM8(0x0013) - -/* VPORT1 - Virtual Port 1 */ -#define VPORT1_DIR _SFR_MEM8(0x0014) -#define VPORT1_OUT _SFR_MEM8(0x0015) -#define VPORT1_IN _SFR_MEM8(0x0016) -#define VPORT1_INTFLAGS _SFR_MEM8(0x0017) - -/* VPORT2 - Virtual Port 2 */ -#define VPORT2_DIR _SFR_MEM8(0x0018) -#define VPORT2_OUT _SFR_MEM8(0x0019) -#define VPORT2_IN _SFR_MEM8(0x001A) -#define VPORT2_INTFLAGS _SFR_MEM8(0x001B) - -/* VPORT3 - Virtual Port 3 */ -#define VPORT3_DIR _SFR_MEM8(0x001C) -#define VPORT3_OUT _SFR_MEM8(0x001D) -#define VPORT3_IN _SFR_MEM8(0x001E) -#define VPORT3_INTFLAGS _SFR_MEM8(0x001F) - -/* OCD - On-Chip Debug System */ -#define OCD_OCDR0 _SFR_MEM8(0x002E) -#define OCD_OCDR1 _SFR_MEM8(0x002F) - -/* CPU - CPU Registers */ -#define CPU_CCP _SFR_MEM8(0x0034) -#define CPU_RAMPD _SFR_MEM8(0x0038) -#define CPU_RAMPX _SFR_MEM8(0x0039) -#define CPU_RAMPY _SFR_MEM8(0x003A) -#define CPU_RAMPZ _SFR_MEM8(0x003B) -#define CPU_EIND _SFR_MEM8(0x003C) -#define CPU_SPL _SFR_MEM8(0x003D) -#define CPU_SPH _SFR_MEM8(0x003E) -#define CPU_SREG _SFR_MEM8(0x003F) - -/* CLK - Clock System */ -#define CLK_CTRL _SFR_MEM8(0x0040) -#define CLK_PSCTRL _SFR_MEM8(0x0041) -#define CLK_LOCK _SFR_MEM8(0x0042) -#define CLK_RTCCTRL _SFR_MEM8(0x0043) - -/* SLEEP - Sleep Controller */ -#define SLEEP_CTRL _SFR_MEM8(0x0048) - -/* OSC - Oscillator Control */ -#define OSC_CTRL _SFR_MEM8(0x0050) -#define OSC_STATUS _SFR_MEM8(0x0051) -#define OSC_XOSCCTRL _SFR_MEM8(0x0052) -#define OSC_XOSCFAIL _SFR_MEM8(0x0053) -#define OSC_RC32KCAL _SFR_MEM8(0x0054) -#define OSC_PLLCTRL _SFR_MEM8(0x0055) -#define OSC_DFLLCTRL _SFR_MEM8(0x0056) - -/* DFLLRC32M - DFLL for 32MHz RC Oscillator */ -#define DFLLRC32M_CTRL _SFR_MEM8(0x0060) -#define DFLLRC32M_CALA _SFR_MEM8(0x0062) -#define DFLLRC32M_CALB _SFR_MEM8(0x0063) -#define DFLLRC32M_COMP0 _SFR_MEM8(0x0064) -#define DFLLRC32M_COMP1 _SFR_MEM8(0x0065) -#define DFLLRC32M_COMP2 _SFR_MEM8(0x0066) - -/* DFLLRC2M - DFLL for 2MHz RC Oscillator */ -#define DFLLRC2M_CTRL _SFR_MEM8(0x0068) -#define DFLLRC2M_CALA _SFR_MEM8(0x006A) -#define DFLLRC2M_CALB _SFR_MEM8(0x006B) -#define DFLLRC2M_COMP0 _SFR_MEM8(0x006C) -#define DFLLRC2M_COMP1 _SFR_MEM8(0x006D) -#define DFLLRC2M_COMP2 _SFR_MEM8(0x006E) - -/* PR - Power Reduction */ -#define PR_PRGEN _SFR_MEM8(0x0070) -#define PR_PRPA _SFR_MEM8(0x0071) -#define PR_PRPC _SFR_MEM8(0x0073) -#define PR_PRPD _SFR_MEM8(0x0074) -#define PR_PRPE _SFR_MEM8(0x0075) -#define PR_PRPF _SFR_MEM8(0x0076) - -/* RST - Reset Controller */ -#define RST_STATUS _SFR_MEM8(0x0078) -#define RST_CTRL _SFR_MEM8(0x0079) - -/* WDT - Watch-Dog Timer */ -#define WDT_CTRL _SFR_MEM8(0x0080) -#define WDT_WINCTRL _SFR_MEM8(0x0081) -#define WDT_STATUS _SFR_MEM8(0x0082) - -/* MCU - MCU Control */ -#define MCU_DEVID0 _SFR_MEM8(0x0090) -#define MCU_DEVID1 _SFR_MEM8(0x0091) -#define MCU_DEVID2 _SFR_MEM8(0x0092) -#define MCU_REVID _SFR_MEM8(0x0093) -#define MCU_JTAGUID _SFR_MEM8(0x0094) -#define MCU_MCUCR _SFR_MEM8(0x0096) -#define MCU_EVSYSLOCK _SFR_MEM8(0x0098) -#define MCU_AWEXLOCK _SFR_MEM8(0x0099) - -/* PMIC - Programmable Interrupt Controller */ -#define PMIC_STATUS _SFR_MEM8(0x00A0) -#define PMIC_INTPRI _SFR_MEM8(0x00A1) -#define PMIC_CTRL _SFR_MEM8(0x00A2) - -/* PORTCFG - Port Configuration */ -#define PORTCFG_MPCMASK _SFR_MEM8(0x00B0) -#define PORTCFG_VPCTRLA _SFR_MEM8(0x00B2) -#define PORTCFG_VPCTRLB _SFR_MEM8(0x00B3) -#define PORTCFG_CLKEVOUT _SFR_MEM8(0x00B4) - -/* CRC - Cyclic Redundancy Checker */ -#define CRC_CTRL _SFR_MEM8(0x00D0) -#define CRC_STATUS _SFR_MEM8(0x00D1) -#define CRC_DATAIN _SFR_MEM8(0x00D3) -#define CRC_CHECKSUM0 _SFR_MEM8(0x00D4) -#define CRC_CHECKSUM1 _SFR_MEM8(0x00D5) -#define CRC_CHECKSUM2 _SFR_MEM8(0x00D6) -#define CRC_CHECKSUM3 _SFR_MEM8(0x00D7) - -/* EVSYS - Event System */ -#define EVSYS_CH0MUX _SFR_MEM8(0x0180) -#define EVSYS_CH1MUX _SFR_MEM8(0x0181) -#define EVSYS_CH2MUX _SFR_MEM8(0x0182) -#define EVSYS_CH3MUX _SFR_MEM8(0x0183) -#define EVSYS_CH0CTRL _SFR_MEM8(0x0188) -#define EVSYS_CH1CTRL _SFR_MEM8(0x0189) -#define EVSYS_CH2CTRL _SFR_MEM8(0x018A) -#define EVSYS_CH3CTRL _SFR_MEM8(0x018B) -#define EVSYS_STROBE _SFR_MEM8(0x0190) -#define EVSYS_DATA _SFR_MEM8(0x0191) - -/* NVM - Non Volatile Memory Controller */ -#define NVM_ADDR0 _SFR_MEM8(0x01C0) -#define NVM_ADDR1 _SFR_MEM8(0x01C1) -#define NVM_ADDR2 _SFR_MEM8(0x01C2) -#define NVM_DATA0 _SFR_MEM8(0x01C4) -#define NVM_DATA1 _SFR_MEM8(0x01C5) -#define NVM_DATA2 _SFR_MEM8(0x01C6) -#define NVM_CMD _SFR_MEM8(0x01CA) -#define NVM_CTRLA _SFR_MEM8(0x01CB) -#define NVM_CTRLB _SFR_MEM8(0x01CC) -#define NVM_INTCTRL _SFR_MEM8(0x01CD) -#define NVM_STATUS _SFR_MEM8(0x01CF) -#define NVM_LOCKBITS _SFR_MEM8(0x01D0) - -/* ADCA - Analog to Digital Converter A */ -#define ADCA_CTRLA _SFR_MEM8(0x0200) -#define ADCA_CTRLB _SFR_MEM8(0x0201) -#define ADCA_REFCTRL _SFR_MEM8(0x0202) -#define ADCA_EVCTRL _SFR_MEM8(0x0203) -#define ADCA_PRESCALER _SFR_MEM8(0x0204) -#define ADCA_INTFLAGS _SFR_MEM8(0x0206) -#define ADCA_CAL _SFR_MEM16(0x020C) -#define ADCA_CH0RES _SFR_MEM16(0x0210) -#define ADCA_CMP _SFR_MEM16(0x0218) -#define ADCA_CH0_CTRL _SFR_MEM8(0x0220) -#define ADCA_CH0_MUXCTRL _SFR_MEM8(0x0221) -#define ADCA_CH0_INTCTRL _SFR_MEM8(0x0222) -#define ADCA_CH0_INTFLAGS _SFR_MEM8(0x0223) -#define ADCA_CH0_RES _SFR_MEM16(0x0224) - -/* ACA - Analog Comparator A */ -#define ACA_AC0CTRL _SFR_MEM8(0x0380) -#define ACA_AC1CTRL _SFR_MEM8(0x0381) -#define ACA_AC0MUXCTRL _SFR_MEM8(0x0382) -#define ACA_AC1MUXCTRL _SFR_MEM8(0x0383) -#define ACA_CTRLA _SFR_MEM8(0x0384) -#define ACA_CTRLB _SFR_MEM8(0x0385) -#define ACA_WINCTRL _SFR_MEM8(0x0386) -#define ACA_STATUS _SFR_MEM8(0x0387) - -/* RTC - Real-Time Counter */ -#define RTC_CTRL _SFR_MEM8(0x0400) -#define RTC_STATUS _SFR_MEM8(0x0401) -#define RTC_INTCTRL _SFR_MEM8(0x0402) -#define RTC_INTFLAGS _SFR_MEM8(0x0403) -#define RTC_TEMP _SFR_MEM8(0x0404) -#define RTC_CNT _SFR_MEM16(0x0408) -#define RTC_PER _SFR_MEM16(0x040A) -#define RTC_COMP _SFR_MEM16(0x040C) - -/* TWIC - Two-Wire Interface C */ -#define TWIC_CTRL _SFR_MEM8(0x0480) -#define TWIC_MASTER_CTRLA _SFR_MEM8(0x0482) -#define TWIC_MASTER_CTRLB _SFR_MEM8(0x0483) -#define TWIC_MASTER_CTRLC _SFR_MEM8(0x0484) -#define TWIC_MASTER_STATUS _SFR_MEM8(0x0485) -#define TWIC_MASTER_BAUD _SFR_MEM8(0x0486) -#define TWIC_MASTER_ADDR _SFR_MEM8(0x0487) -#define TWIC_MASTER_DATA _SFR_MEM8(0x0488) -#define TWIC_SLAVE_CTRLA _SFR_MEM8(0x0488) -#define TWIC_SLAVE_CTRLB _SFR_MEM8(0x0489) -#define TWIC_SLAVE_STATUS _SFR_MEM8(0x048A) -#define TWIC_SLAVE_ADDR _SFR_MEM8(0x048B) -#define TWIC_SLAVE_DATA _SFR_MEM8(0x048C) -#define TWIC_SLAVE_ADDRMASK _SFR_MEM8(0x048D) - -/* TWIE - Two-Wire Interface E */ -#define TWIE_CTRL _SFR_MEM8(0x04A0) -#define TWIE_MASTER_CTRLA _SFR_MEM8(0x04A1) -#define TWIE_MASTER_CTRLB _SFR_MEM8(0x04A2) -#define TWIE_MASTER_CTRLC _SFR_MEM8(0x04A3) -#define TWIE_MASTER_STATUS _SFR_MEM8(0x04A4) -#define TWIE_MASTER_BAUD _SFR_MEM8(0x04A5) -#define TWIE_MASTER_ADDR _SFR_MEM8(0x04A6) -#define TWIE_MASTER_DATA _SFR_MEM8(0x04A7) -#define TWIE_SLAVE_CTRLA _SFR_MEM8(0x04A8) -#define TWIE_SLAVE_CTRLB _SFR_MEM8(0x04A9) -#define TWIE_SLAVE_STATUS _SFR_MEM8(0x04AA) -#define TWIE_SLAVE_ADDR _SFR_MEM8(0x04AB) -#define TWIE_SLAVE_DATA _SFR_MEM8(0x04AC) -#define TWIE_SLAVE_ADDRMASK _SFR_MEM8(0x04AD) - -/* PORTA - Port A */ -#define PORTA_DIR _SFR_MEM8(0x0600) -#define PORTA_DIRSET _SFR_MEM8(0x0601) -#define PORTA_DIRCLR _SFR_MEM8(0x0602) -#define PORTA_DIRTGL _SFR_MEM8(0x0603) -#define PORTA_OUT _SFR_MEM8(0x0604) -#define PORTA_OUTSET _SFR_MEM8(0x0605) -#define PORTA_OUTCLR _SFR_MEM8(0x0606) -#define PORTA_OUTTGL _SFR_MEM8(0x0607) -#define PORTA_IN _SFR_MEM8(0x0608) -#define PORTA_INTCTRL _SFR_MEM8(0x0609) -#define PORTA_INT0MASK _SFR_MEM8(0x060A) -#define PORTA_INT1MASK _SFR_MEM8(0x060B) -#define PORTA_INTFLAGS _SFR_MEM8(0x060C) -#define PORTA_PIN0CTRL _SFR_MEM8(0x0610) -#define PORTA_PIN1CTRL _SFR_MEM8(0x0611) -#define PORTA_PIN2CTRL _SFR_MEM8(0x0612) -#define PORTA_PIN3CTRL _SFR_MEM8(0x0613) -#define PORTA_PIN4CTRL _SFR_MEM8(0x0614) -#define PORTA_PIN5CTRL _SFR_MEM8(0x0615) -#define PORTA_PIN6CTRL _SFR_MEM8(0x0616) -#define PORTA_PIN7CTRL _SFR_MEM8(0x0617) - -/* PORTB - Port B */ -#define PORTB_DIR _SFR_MEM8(0x0620) -#define PORTB_DIRSET _SFR_MEM8(0x0621) -#define PORTB_DIRCLR _SFR_MEM8(0x0622) -#define PORTB_DIRTGL _SFR_MEM8(0x0623) -#define PORTB_OUT _SFR_MEM8(0x0624) -#define PORTB_OUTSET _SFR_MEM8(0x0625) -#define PORTB_OUTCLR _SFR_MEM8(0x0626) -#define PORTB_OUTTGL _SFR_MEM8(0x0627) -#define PORTB_IN _SFR_MEM8(0x0628) -#define PORTB_INTCTRL _SFR_MEM8(0x0629) -#define PORTB_INT0MASK _SFR_MEM8(0x062A) -#define PORTB_INT1MASK _SFR_MEM8(0x062B) -#define PORTB_INTFLAGS _SFR_MEM8(0x062C) -#define PORTB_PIN0CTRL _SFR_MEM8(0x0630) -#define PORTB_PIN1CTRL _SFR_MEM8(0x0631) -#define PORTB_PIN2CTRL _SFR_MEM8(0x0632) -#define PORTB_PIN3CTRL _SFR_MEM8(0x0633) -#define PORTB_PIN4CTRL _SFR_MEM8(0x0634) -#define PORTB_PIN5CTRL _SFR_MEM8(0x0635) -#define PORTB_PIN6CTRL _SFR_MEM8(0x0636) -#define PORTB_PIN7CTRL _SFR_MEM8(0x0637) - -/* PORTC - Port C */ -#define PORTC_DIR _SFR_MEM8(0x0640) -#define PORTC_DIRSET _SFR_MEM8(0x0641) -#define PORTC_DIRCLR _SFR_MEM8(0x0642) -#define PORTC_DIRTGL _SFR_MEM8(0x0643) -#define PORTC_OUT _SFR_MEM8(0x0644) -#define PORTC_OUTSET _SFR_MEM8(0x0645) -#define PORTC_OUTCLR _SFR_MEM8(0x0646) -#define PORTC_OUTTGL _SFR_MEM8(0x0647) -#define PORTC_IN _SFR_MEM8(0x0648) -#define PORTC_INTCTRL _SFR_MEM8(0x0649) -#define PORTC_INT0MASK _SFR_MEM8(0x064A) -#define PORTC_INT1MASK _SFR_MEM8(0x064B) -#define PORTC_INTFLAGS _SFR_MEM8(0x064C) -#define PORTC_PIN0CTRL _SFR_MEM8(0x0650) -#define PORTC_PIN1CTRL _SFR_MEM8(0x0651) -#define PORTC_PIN2CTRL _SFR_MEM8(0x0652) -#define PORTC_PIN3CTRL _SFR_MEM8(0x0653) -#define PORTC_PIN4CTRL _SFR_MEM8(0x0654) -#define PORTC_PIN5CTRL _SFR_MEM8(0x0655) -#define PORTC_PIN6CTRL _SFR_MEM8(0x0656) -#define PORTC_PIN7CTRL _SFR_MEM8(0x0657) - -/* PORTD - Port D */ -#define PORTD_DIR _SFR_MEM8(0x0660) -#define PORTD_DIRSET _SFR_MEM8(0x0661) -#define PORTD_DIRCLR _SFR_MEM8(0x0662) -#define PORTD_DIRTGL _SFR_MEM8(0x0663) -#define PORTD_OUT _SFR_MEM8(0x0664) -#define PORTD_OUTSET _SFR_MEM8(0x0665) -#define PORTD_OUTCLR _SFR_MEM8(0x0666) -#define PORTD_OUTTGL _SFR_MEM8(0x0667) -#define PORTD_IN _SFR_MEM8(0x0668) -#define PORTD_INTCTRL _SFR_MEM8(0x0669) -#define PORTD_INT0MASK _SFR_MEM8(0x066A) -#define PORTD_INT1MASK _SFR_MEM8(0x066B) -#define PORTD_INTFLAGS _SFR_MEM8(0x066C) -#define PORTD_PIN0CTRL _SFR_MEM8(0x0670) -#define PORTD_PIN1CTRL _SFR_MEM8(0x0671) -#define PORTD_PIN2CTRL _SFR_MEM8(0x0672) -#define PORTD_PIN3CTRL _SFR_MEM8(0x0673) -#define PORTD_PIN4CTRL _SFR_MEM8(0x0674) -#define PORTD_PIN5CTRL _SFR_MEM8(0x0675) -#define PORTD_PIN6CTRL _SFR_MEM8(0x0676) -#define PORTD_PIN7CTRL _SFR_MEM8(0x0677) - -/* PORTE - Port E */ -#define PORTE_DIR _SFR_MEM8(0x0680) -#define PORTE_DIRSET _SFR_MEM8(0x0681) -#define PORTE_DIRCLR _SFR_MEM8(0x0682) -#define PORTE_DIRTGL _SFR_MEM8(0x0683) -#define PORTE_OUT _SFR_MEM8(0x0684) -#define PORTE_OUTSET _SFR_MEM8(0x0685) -#define PORTE_OUTCLR _SFR_MEM8(0x0686) -#define PORTE_OUTTGL _SFR_MEM8(0x0687) -#define PORTE_IN _SFR_MEM8(0x0688) -#define PORTE_INTCTRL _SFR_MEM8(0x0689) -#define PORTE_INT0MASK _SFR_MEM8(0x068A) -#define PORTE_INT1MASK _SFR_MEM8(0x068B) -#define PORTE_INTFLAGS _SFR_MEM8(0x068C) -#define PORTE_PIN0CTRL _SFR_MEM8(0x0690) -#define PORTE_PIN1CTRL _SFR_MEM8(0x0691) -#define PORTE_PIN2CTRL _SFR_MEM8(0x0692) -#define PORTE_PIN3CTRL _SFR_MEM8(0x0693) -#define PORTE_PIN4CTRL _SFR_MEM8(0x0694) -#define PORTE_PIN5CTRL _SFR_MEM8(0x0695) -#define PORTE_PIN6CTRL _SFR_MEM8(0x0696) -#define PORTE_PIN7CTRL _SFR_MEM8(0x0697) - -/* PORTF - Port F */ -#define PORTF_DIR _SFR_MEM8(0x06A0) -#define PORTF_DIRSET _SFR_MEM8(0x06A1) -#define PORTF_DIRCLR _SFR_MEM8(0x06A2) -#define PORTF_DIRTGL _SFR_MEM8(0x06A3) -#define PORTF_OUT _SFR_MEM8(0x06A4) -#define PORTF_OUTSET _SFR_MEM8(0x06A5) -#define PORTF_OUTCLR _SFR_MEM8(0x06A6) -#define PORTF_OUTTGL _SFR_MEM8(0x06A7) -#define PORTF_IN _SFR_MEM8(0x06A8) -#define PORTF_INTCTRL _SFR_MEM8(0x06A9) -#define PORTF_INT0MASK _SFR_MEM8(0x06AA) -#define PORTF_INT1MASK _SFR_MEM8(0x06AB) -#define PORTF_INTFLAGS _SFR_MEM8(0x06AC) -#define PORTF_PIN0CTRL _SFR_MEM8(0x06B0) -#define PORTF_PIN1CTRL _SFR_MEM8(0x06B1) -#define PORTF_PIN2CTRL _SFR_MEM8(0x06B2) -#define PORTF_PIN3CTRL _SFR_MEM8(0x06B3) -#define PORTF_PIN4CTRL _SFR_MEM8(0x06B4) -#define PORTF_PIN5CTRL _SFR_MEM8(0x06B5) -#define PORTF_PIN6CTRL _SFR_MEM8(0x06B6) -#define PORTF_PIN7CTRL _SFR_MEM8(0x06B7) - -/* PORTR - Port R */ -#define PORTR_DIR _SFR_MEM8(0x07E0) -#define PORTR_DIRSET _SFR_MEM8(0x07E1) -#define PORTR_DIRCLR _SFR_MEM8(0x07E2) -#define PORTR_DIRTGL _SFR_MEM8(0x07E3) -#define PORTR_OUT _SFR_MEM8(0x07E4) -#define PORTR_OUTSET _SFR_MEM8(0x07E5) -#define PORTR_OUTCLR _SFR_MEM8(0x07E6) -#define PORTR_OUTTGL _SFR_MEM8(0x07E7) -#define PORTR_IN _SFR_MEM8(0x07E8) -#define PORTR_INTCTRL _SFR_MEM8(0x07E9) -#define PORTR_INT0MASK _SFR_MEM8(0x07EA) -#define PORTR_INT1MASK _SFR_MEM8(0x07EB) -#define PORTR_INTFLAGS _SFR_MEM8(0x07EC) -#define PORTR_PIN0CTRL _SFR_MEM8(0x07F0) -#define PORTR_PIN1CTRL _SFR_MEM8(0x07F1) -#define PORTR_PIN2CTRL _SFR_MEM8(0x07F2) -#define PORTR_PIN3CTRL _SFR_MEM8(0x07F3) -#define PORTR_PIN4CTRL _SFR_MEM8(0x07F4) -#define PORTR_PIN5CTRL _SFR_MEM8(0x07F5) -#define PORTR_PIN6CTRL _SFR_MEM8(0x07F6) -#define PORTR_PIN7CTRL _SFR_MEM8(0x07F7) - -/* TCC0 - Timer/Counter C0 */ -#define TCC0_CTRLA _SFR_MEM8(0x0800) -#define TCC0_CTRLB _SFR_MEM8(0x0801) -#define TCC0_CTRLC _SFR_MEM8(0x0802) -#define TCC0_CTRLD _SFR_MEM8(0x0803) -#define TCC0_CTRLE _SFR_MEM8(0x0804) -#define TCC0_INTCTRLA _SFR_MEM8(0x0806) -#define TCC0_INTCTRLB _SFR_MEM8(0x0807) -#define TCC0_CTRLFCLR _SFR_MEM8(0x0808) -#define TCC0_CTRLFSET _SFR_MEM8(0x0809) -#define TCC0_CTRLGCLR _SFR_MEM8(0x080A) -#define TCC0_CTRLGSET _SFR_MEM8(0x080B) -#define TCC0_INTFLAGS _SFR_MEM8(0x080C) -#define TCC0_TEMP _SFR_MEM8(0x080F) -#define TCC0_CNT _SFR_MEM16(0x0820) -#define TCC0_PER _SFR_MEM16(0x0826) -#define TCC0_CCA _SFR_MEM16(0x0828) -#define TCC0_CCB _SFR_MEM16(0x082A) -#define TCC0_CCC _SFR_MEM16(0x082C) -#define TCC0_CCD _SFR_MEM16(0x082E) -#define TCC0_PERBUF _SFR_MEM16(0x0836) -#define TCC0_CCABUF _SFR_MEM16(0x0838) -#define TCC0_CCBBUF _SFR_MEM16(0x083A) -#define TCC0_CCCBUF _SFR_MEM16(0x083C) -#define TCC0_CCDBUF _SFR_MEM16(0x083E) - -/* TCC1 - Timer/Counter C1 */ -#define TCC1_CTRLA _SFR_MEM8(0x0840) -#define TCC1_CTRLB _SFR_MEM8(0x0841) -#define TCC1_CTRLC _SFR_MEM8(0x0842) -#define TCC1_CTRLD _SFR_MEM8(0x0843) -#define TCC1_CTRLE _SFR_MEM8(0x0844) -#define TCC1_INTCTRLA _SFR_MEM8(0x0846) -#define TCC1_INTCTRLB _SFR_MEM8(0x0847) -#define TCC1_CTRLFCLR _SFR_MEM8(0x0848) -#define TCC1_CTRLFSET _SFR_MEM8(0x0849) -#define TCC1_CTRLGCLR _SFR_MEM8(0x084A) -#define TCC1_CTRLGSET _SFR_MEM8(0x084B) -#define TCC1_INTFLAGS _SFR_MEM8(0x084C) -#define TCC1_TEMP _SFR_MEM8(0x084F) -#define TCC1_CNT _SFR_MEM16(0x0860) -#define TCC1_PER _SFR_MEM16(0x0866) -#define TCC1_CCA _SFR_MEM16(0x0868) -#define TCC1_CCB _SFR_MEM16(0x086A) -#define TCC1_PERBUF _SFR_MEM16(0x0876) -#define TCC1_CCABUF _SFR_MEM16(0x0878) -#define TCC1_CCBBUF _SFR_MEM16(0x087A) - -/* AWEXC - Advanced Waveform Extension C */ -#define AWEXC_CTRL _SFR_MEM8(0x0880) -#define AWEXC_FDEMASK _SFR_MEM8(0x0882) -#define AWEXC_FDCTRL _SFR_MEM8(0x0883) -#define AWEXC_STATUS _SFR_MEM8(0x0884) -#define AWEXC_DTBOTH _SFR_MEM8(0x0886) -#define AWEXC_DTBOTHBUF _SFR_MEM8(0x0887) -#define AWEXC_DTLS _SFR_MEM8(0x0888) -#define AWEXC_DTHS _SFR_MEM8(0x0889) -#define AWEXC_DTLSBUF _SFR_MEM8(0x088A) -#define AWEXC_DTHSBUF _SFR_MEM8(0x088B) -#define AWEXC_OUTOVEN _SFR_MEM8(0x088C) - -/* HIRESC - High-Resolution Extension C */ -#define HIRESC_CTRLA _SFR_MEM8(0x0890) - -/* USARTC0 - Universal Asynchronous Receiver-Transmitter C0 */ -#define USARTC0_DATA _SFR_MEM8(0x08A0) -#define USARTC0_STATUS _SFR_MEM8(0x08A1) -#define USARTC0_CTRLA _SFR_MEM8(0x08A3) -#define USARTC0_CTRLB _SFR_MEM8(0x08A4) -#define USARTC0_CTRLC _SFR_MEM8(0x08A5) -#define USARTC0_BAUDCTRLA _SFR_MEM8(0x08A6) -#define USARTC0_BAUDCTRLB _SFR_MEM8(0x08A7) - -/* SPIC - Serial Peripheral Interface C */ -#define SPIC_CTRL _SFR_MEM8(0x08C0) -#define SPIC_INTCTRL _SFR_MEM8(0x08C1) -#define SPIC_STATUS _SFR_MEM8(0x08C2) -#define SPIC_DATA _SFR_MEM8(0x08C3) - -/* IRCOM - IR Communication Module */ -#define IRCOM_CTRL _SFR_MEM8(0x08F8) -#define IRCOM_TXPLCTRL _SFR_MEM8(0x08F9) -#define IRCOM_RXPLCTRL _SFR_MEM8(0x08FA) - -/* TCD0 - Timer/Counter D0 */ -#define TCD0_CTRLA _SFR_MEM8(0x0900) -#define TCD0_CTRLB _SFR_MEM8(0x0901) -#define TCD0_CTRLC _SFR_MEM8(0x0902) -#define TCD0_CTRLD _SFR_MEM8(0x0903) -#define TCD0_CTRLE _SFR_MEM8(0x0904) -#define TCD0_INTCTRLA _SFR_MEM8(0x0906) -#define TCD0_INTCTRLB _SFR_MEM8(0x0907) -#define TCD0_CTRLFCLR _SFR_MEM8(0x0908) -#define TCD0_CTRLFSET _SFR_MEM8(0x0909) -#define TCD0_CTRLGCLR _SFR_MEM8(0x090A) -#define TCD0_CTRLGSET _SFR_MEM8(0x090B) -#define TCD0_INTFLAGS _SFR_MEM8(0x090C) -#define TCD0_TEMP _SFR_MEM8(0x090F) -#define TCD0_CNT _SFR_MEM16(0x0920) -#define TCD0_PER _SFR_MEM16(0x0926) -#define TCD0_CCA _SFR_MEM16(0x0928) -#define TCD0_CCB _SFR_MEM16(0x092A) -#define TCD0_CCC _SFR_MEM16(0x092C) -#define TCD0_CCD _SFR_MEM16(0x092E) -#define TCD0_PERBUF _SFR_MEM16(0x0936) -#define TCD0_CCABUF _SFR_MEM16(0x0938) -#define TCD0_CCBBUF _SFR_MEM16(0x093A) -#define TCD0_CCCBUF _SFR_MEM16(0x093C) -#define TCD0_CCDBUF _SFR_MEM16(0x093E) - -/* USARTD0 - Universal Asynchronous Receiver-Transmitter D0 */ -#define USARTD0_DATA _SFR_MEM8(0x09A0) -#define USARTD0_STATUS _SFR_MEM8(0x09A1) -#define USARTD0_CTRLA _SFR_MEM8(0x09A3) -#define USARTD0_CTRLB _SFR_MEM8(0x09A4) -#define USARTD0_CTRLC _SFR_MEM8(0x09A5) -#define USARTD0_BAUDCTRLA _SFR_MEM8(0x09A6) -#define USARTD0_BAUDCTRLB _SFR_MEM8(0x09A7) - -/* SPID - Serial Peripheral Interface D */ -#define SPID_CTRL _SFR_MEM8(0x09C0) -#define SPID_INTCTRL _SFR_MEM8(0x09C1) -#define SPID_STATUS _SFR_MEM8(0x09C2) -#define SPID_DATA _SFR_MEM8(0x09C3) - -/* TCE0 - Timer/Counter E0 */ -#define TCE0_CTRLA _SFR_MEM8(0x0A00) -#define TCE0_CTRLB _SFR_MEM8(0x0A01) -#define TCE0_CTRLC _SFR_MEM8(0x0A02) -#define TCE0_CTRLD _SFR_MEM8(0x0A03) -#define TCE0_CTRLE _SFR_MEM8(0x0A04) -#define TCE0_INTCTRLA _SFR_MEM8(0x0A06) -#define TCE0_INTCTRLB _SFR_MEM8(0x0A07) -#define TCE0_CTRLFCLR _SFR_MEM8(0x0A08) -#define TCE0_CTRLFSET _SFR_MEM8(0x0A09) -#define TCE0_CTRLGCLR _SFR_MEM8(0x0A0A) -#define TCE0_CTRLGSET _SFR_MEM8(0x0A0B) -#define TCE0_INTFLAGS _SFR_MEM8(0x0A0C) -#define TCE0_TEMP _SFR_MEM8(0x0A0F) -#define TCE0_CNT _SFR_MEM16(0x0A20) -#define TCE0_PER _SFR_MEM16(0x0A26) -#define TCE0_CCA _SFR_MEM16(0x0A28) -#define TCE0_CCB _SFR_MEM16(0x0A2A) -#define TCE0_CCC _SFR_MEM16(0x0A2C) -#define TCE0_CCD _SFR_MEM16(0x0A2E) -#define TCE0_PERBUF _SFR_MEM16(0x0A36) -#define TCE0_CCABUF _SFR_MEM16(0x0A38) -#define TCE0_CCBBUF _SFR_MEM16(0x0A3A) -#define TCE0_CCCBUF _SFR_MEM16(0x0A3C) -#define TCE0_CCDBUF _SFR_MEM16(0x0A3E) - -/* AWEXE - Advanced Waveform Extension E */ -#define AWEXE_CTRL _SFR_MEM8(0x0A80) -#define AWEXE_FDEMASK _SFR_MEM8(0x0A82) -#define AWEXE_FDCTRL _SFR_MEM8(0x0A83) -#define AWEXE_STATUS _SFR_MEM8(0x0A84) -#define AWEXE_DTBOTH _SFR_MEM8(0x0A86) -#define AWEXE_DTBOTHBUF _SFR_MEM8(0x0A87) -#define AWEXE_DTLS _SFR_MEM8(0x0A88) -#define AWEXE_DTHS _SFR_MEM8(0x0A89) -#define AWEXE_DTLSBUF _SFR_MEM8(0x0A8A) -#define AWEXE_DTHSBUF _SFR_MEM8(0x0A8B) -#define AWEXE_OUTOVEN _SFR_MEM8(0x0A8C) - -/* USARTE0 - Universal Asynchronous Receiver-Transmitter E0 */ -#define USARTE0_DATA _SFR_MEM8(0x0AA0) -#define USARTE0_STATUS _SFR_MEM8(0x0AA1) -#define USARTE0_CTRLA _SFR_MEM8(0x0AA3) -#define USARTE0_CTRLB _SFR_MEM8(0x0AA4) -#define USARTE0_CTRLC _SFR_MEM8(0x0AA5) -#define USARTE0_BAUDCTRLA _SFR_MEM8(0x0AA6) -#define USARTE0_BAUDCTRLB _SFR_MEM8(0x0AA7) - -/* SPIE - Serial Peripheral Interface E */ -#define SPIE_CTRL _SFR_MEM8(0x0AC0) -#define SPIE_INTCTRL _SFR_MEM8(0x0AC1) -#define SPIE_STATUS _SFR_MEM8(0x0AC2) -#define SPIE_DATA _SFR_MEM8(0x0AC3) - -/* TCF0 - Timer/Counter F0 */ -#define TCF0_CTRLA _SFR_MEM8(0x0B00) -#define TCF0_CTRLB _SFR_MEM8(0x0B01) -#define TCF0_CTRLC _SFR_MEM8(0x0B02) -#define TCF0_CTRLD _SFR_MEM8(0x0B03) -#define TCF0_CTRLE _SFR_MEM8(0x0B04) -#define TCF0_INTCTRLA _SFR_MEM8(0x0B06) -#define TCF0_INTCTRLB _SFR_MEM8(0x0B07) -#define TCF0_CTRLFCLR _SFR_MEM8(0x0B08) -#define TCF0_CTRLFSET _SFR_MEM8(0x0B09) -#define TCF0_CTRLGCLR _SFR_MEM8(0x0B0A) -#define TCF0_CTRLGSET _SFR_MEM8(0x0B0B) -#define TCF0_INTFLAGS _SFR_MEM8(0x0B0C) -#define TCF0_TEMP _SFR_MEM8(0x0B0F) -#define TCF0_CNT _SFR_MEM16(0x0B20) -#define TCF0_PER _SFR_MEM16(0x0B26) -#define TCF0_CCA _SFR_MEM16(0x0B28) -#define TCF0_CCB _SFR_MEM16(0x0B2A) -#define TCF0_CCC _SFR_MEM16(0x0B2C) -#define TCF0_CCD _SFR_MEM16(0x0B2E) -#define TCF0_PERBUF _SFR_MEM16(0x0B36) -#define TCF0_CCABUF _SFR_MEM16(0x0B38) -#define TCF0_CCBBUF _SFR_MEM16(0x0B3A) -#define TCF0_CCCBUF _SFR_MEM16(0x0B3C) -#define TCF0_CCDBUF _SFR_MEM16(0x0B3E) - - - -/*================== Bitfield Definitions ================== */ - -/* XOCD - On-Chip Debug System */ -/* OCD.OCDR1 bit masks and bit positions */ -#define OCD_OCDRD_bm 0x01 /* OCDR Dirty bit mask. */ -#define OCD_OCDRD_bp 0 /* OCDR Dirty bit position. */ - - -/* CPU - CPU */ -/* CPU.CCP bit masks and bit positions */ -#define CPU_CCP_gm 0xFF /* CCP signature group mask. */ -#define CPU_CCP_gp 0 /* CCP signature group position. */ -#define CPU_CCP0_bm (1<<0) /* CCP signature bit 0 mask. */ -#define CPU_CCP0_bp 0 /* CCP signature bit 0 position. */ -#define CPU_CCP1_bm (1<<1) /* CCP signature bit 1 mask. */ -#define CPU_CCP1_bp 1 /* CCP signature bit 1 position. */ -#define CPU_CCP2_bm (1<<2) /* CCP signature bit 2 mask. */ -#define CPU_CCP2_bp 2 /* CCP signature bit 2 position. */ -#define CPU_CCP3_bm (1<<3) /* CCP signature bit 3 mask. */ -#define CPU_CCP3_bp 3 /* CCP signature bit 3 position. */ -#define CPU_CCP4_bm (1<<4) /* CCP signature bit 4 mask. */ -#define CPU_CCP4_bp 4 /* CCP signature bit 4 position. */ -#define CPU_CCP5_bm (1<<5) /* CCP signature bit 5 mask. */ -#define CPU_CCP5_bp 5 /* CCP signature bit 5 position. */ -#define CPU_CCP6_bm (1<<6) /* CCP signature bit 6 mask. */ -#define CPU_CCP6_bp 6 /* CCP signature bit 6 position. */ -#define CPU_CCP7_bm (1<<7) /* CCP signature bit 7 mask. */ -#define CPU_CCP7_bp 7 /* CCP signature bit 7 position. */ - - -/* CPU.SREG bit masks and bit positions */ -#define CPU_I_bm 0x80 /* Global Interrupt Enable Flag bit mask. */ -#define CPU_I_bp 7 /* Global Interrupt Enable Flag bit position. */ - -#define CPU_T_bm 0x40 /* Transfer Bit bit mask. */ -#define CPU_T_bp 6 /* Transfer Bit bit position. */ - -#define CPU_H_bm 0x20 /* Half Carry Flag bit mask. */ -#define CPU_H_bp 5 /* Half Carry Flag bit position. */ - -#define CPU_S_bm 0x10 /* N Exclusive Or V Flag bit mask. */ -#define CPU_S_bp 4 /* N Exclusive Or V Flag bit position. */ - -#define CPU_V_bm 0x08 /* Two's Complement Overflow Flag bit mask. */ -#define CPU_V_bp 3 /* Two's Complement Overflow Flag bit position. */ - -#define CPU_N_bm 0x04 /* Negative Flag bit mask. */ -#define CPU_N_bp 2 /* Negative Flag bit position. */ - -#define CPU_Z_bm 0x02 /* Zero Flag bit mask. */ -#define CPU_Z_bp 1 /* Zero Flag bit position. */ - -#define CPU_C_bm 0x01 /* Carry Flag bit mask. */ -#define CPU_C_bp 0 /* Carry Flag bit position. */ - - -/* CLK - Clock System */ -/* CLK.CTRL bit masks and bit positions */ -#define CLK_SCLKSEL_gm 0x07 /* System Clock Selection group mask. */ -#define CLK_SCLKSEL_gp 0 /* System Clock Selection group position. */ -#define CLK_SCLKSEL0_bm (1<<0) /* System Clock Selection bit 0 mask. */ -#define CLK_SCLKSEL0_bp 0 /* System Clock Selection bit 0 position. */ -#define CLK_SCLKSEL1_bm (1<<1) /* System Clock Selection bit 1 mask. */ -#define CLK_SCLKSEL1_bp 1 /* System Clock Selection bit 1 position. */ -#define CLK_SCLKSEL2_bm (1<<2) /* System Clock Selection bit 2 mask. */ -#define CLK_SCLKSEL2_bp 2 /* System Clock Selection bit 2 position. */ - - -/* CLK.PSCTRL bit masks and bit positions */ -#define CLK_PSADIV_gm 0x7C /* Prescaler A Division Factor group mask. */ -#define CLK_PSADIV_gp 2 /* Prescaler A Division Factor group position. */ -#define CLK_PSADIV0_bm (1<<2) /* Prescaler A Division Factor bit 0 mask. */ -#define CLK_PSADIV0_bp 2 /* Prescaler A Division Factor bit 0 position. */ -#define CLK_PSADIV1_bm (1<<3) /* Prescaler A Division Factor bit 1 mask. */ -#define CLK_PSADIV1_bp 3 /* Prescaler A Division Factor bit 1 position. */ -#define CLK_PSADIV2_bm (1<<4) /* Prescaler A Division Factor bit 2 mask. */ -#define CLK_PSADIV2_bp 4 /* Prescaler A Division Factor bit 2 position. */ -#define CLK_PSADIV3_bm (1<<5) /* Prescaler A Division Factor bit 3 mask. */ -#define CLK_PSADIV3_bp 5 /* Prescaler A Division Factor bit 3 position. */ -#define CLK_PSADIV4_bm (1<<6) /* Prescaler A Division Factor bit 4 mask. */ -#define CLK_PSADIV4_bp 6 /* Prescaler A Division Factor bit 4 position. */ - -#define CLK_PSBCDIV_gm 0x03 /* Prescaler B and C Division factor group mask. */ -#define CLK_PSBCDIV_gp 0 /* Prescaler B and C Division factor group position. */ -#define CLK_PSBCDIV0_bm (1<<0) /* Prescaler B and C Division factor bit 0 mask. */ -#define CLK_PSBCDIV0_bp 0 /* Prescaler B and C Division factor bit 0 position. */ -#define CLK_PSBCDIV1_bm (1<<1) /* Prescaler B and C Division factor bit 1 mask. */ -#define CLK_PSBCDIV1_bp 1 /* Prescaler B and C Division factor bit 1 position. */ - - -/* CLK.LOCK bit masks and bit positions */ -#define CLK_LOCK_bm 0x01 /* Clock System Lock bit mask. */ -#define CLK_LOCK_bp 0 /* Clock System Lock bit position. */ - - -/* CLK.RTCCTRL bit masks and bit positions */ -#define CLK_RTCSRC_gm 0x0E /* Clock Source group mask. */ -#define CLK_RTCSRC_gp 1 /* Clock Source group position. */ -#define CLK_RTCSRC0_bm (1<<1) /* Clock Source bit 0 mask. */ -#define CLK_RTCSRC0_bp 1 /* Clock Source bit 0 position. */ -#define CLK_RTCSRC1_bm (1<<2) /* Clock Source bit 1 mask. */ -#define CLK_RTCSRC1_bp 2 /* Clock Source bit 1 position. */ -#define CLK_RTCSRC2_bm (1<<3) /* Clock Source bit 2 mask. */ -#define CLK_RTCSRC2_bp 3 /* Clock Source bit 2 position. */ - -#define CLK_RTCEN_bm 0x01 /* RTC Clock Source Enable bit mask. */ -#define CLK_RTCEN_bp 0 /* RTC Clock Source Enable bit position. */ - - -/* PR.PRGEN bit masks and bit positions */ -#define PR_RTC_bm 0x04 /* Real-time Counter bit mask. */ -#define PR_RTC_bp 2 /* Real-time Counter bit position. */ - -#define PR_EVSYS_bm 0x02 /* Event System bit mask. */ -#define PR_EVSYS_bp 1 /* Event System bit position. */ - -/* PR.PRPA bit masks and bit positions */ -#define PR_ADC_bm 0x02 /* Port A ADC bit mask. */ -#define PR_ADC_bp 1 /* Port A ADC bit position. */ - -#define PR_AC_bm 0x01 /* Port A Analog Comparator bit mask. */ -#define PR_AC_bp 0 /* Port A Analog Comparator bit position. */ - -/* PR.PRPC bit masks and bit positions */ -#define PR_TWI_bm 0x40 /* Port C Two-wire Interface bit mask. */ -#define PR_TWI_bp 6 /* Port C Two-wire Interface bit position. */ - -#define PR_USART0_bm 0x10 /* Port C USART0 bit mask. */ -#define PR_USART0_bp 4 /* Port C USART0 bit position. */ - -#define PR_SPI_bm 0x08 /* Port C SPI bit mask. */ -#define PR_SPI_bp 3 /* Port C SPI bit position. */ - -#define PR_HIRES_bm 0x04 /* Port C HIRES bit mask. */ -#define PR_HIRES_bp 2 /* Port C HIRES bit position. */ - -#define PR_TC1_bm 0x02 /* Port C Timer/Counter1 bit mask. */ -#define PR_TC1_bp 1 /* Port C Timer/Counter1 bit position. */ - -#define PR_TC0_bm 0x01 /* Port C Timer/Counter0 bit mask. */ -#define PR_TC0_bp 0 /* Port C Timer/Counter0 bit position. */ - -/* PR.PRPD bit masks and bit positions */ -/* PR_USART0_bm Predefined. */ -/* PR_USART0_bp Predefined. */ - -/* PR_SPI_bm Predefined. */ -/* PR_SPI_bp Predefined. */ - -/* PR_TC0_bm Predefined. */ -/* PR_TC0_bp Predefined. */ - -/* PR.PRPE bit masks and bit positions */ -/* PR_TWI_bm Predefined. */ -/* PR_TWI_bp Predefined. */ - -/* PR_USART0_bm Predefined. */ -/* PR_USART0_bp Predefined. */ - -/* PR_TC0_bm Predefined. */ -/* PR_TC0_bp Predefined. */ - -/* PR.PRPF bit masks and bit positions */ -/* PR_USART0_bm Predefined. */ -/* PR_USART0_bp Predefined. */ - -/* PR_TC0_bm Predefined. */ -/* PR_TC0_bp Predefined. */ - -/* SLEEP - Sleep Controller */ -/* SLEEP.CTRL bit masks and bit positions */ -#define SLEEP_SMODE_gm 0x0E /* Sleep Mode group mask. */ -#define SLEEP_SMODE_gp 1 /* Sleep Mode group position. */ -#define SLEEP_SMODE0_bm (1<<1) /* Sleep Mode bit 0 mask. */ -#define SLEEP_SMODE0_bp 1 /* Sleep Mode bit 0 position. */ -#define SLEEP_SMODE1_bm (1<<2) /* Sleep Mode bit 1 mask. */ -#define SLEEP_SMODE1_bp 2 /* Sleep Mode bit 1 position. */ -#define SLEEP_SMODE2_bm (1<<3) /* Sleep Mode bit 2 mask. */ -#define SLEEP_SMODE2_bp 3 /* Sleep Mode bit 2 position. */ - -#define SLEEP_SEN_bm 0x01 /* Sleep Enable bit mask. */ -#define SLEEP_SEN_bp 0 /* Sleep Enable bit position. */ - - -/* OSC - Oscillator */ -/* OSC.CTRL bit masks and bit positions */ -#define OSC_PLLEN_bm 0x10 /* PLL Enable bit mask. */ -#define OSC_PLLEN_bp 4 /* PLL Enable bit position. */ - -#define OSC_XOSCEN_bm 0x08 /* External Oscillator Enable bit mask. */ -#define OSC_XOSCEN_bp 3 /* External Oscillator Enable bit position. */ - -#define OSC_RC32KEN_bm 0x04 /* Internal 32kHz RC Oscillator Enable bit mask. */ -#define OSC_RC32KEN_bp 2 /* Internal 32kHz RC Oscillator Enable bit position. */ - -#define OSC_RC32MEN_bm 0x02 /* Internal 32MHz RC Oscillator Enable bit mask. */ -#define OSC_RC32MEN_bp 1 /* Internal 32MHz RC Oscillator Enable bit position. */ - -#define OSC_RC2MEN_bm 0x01 /* Internal 2MHz RC Oscillator Enable bit mask. */ -#define OSC_RC2MEN_bp 0 /* Internal 2MHz RC Oscillator Enable bit position. */ - - -/* OSC.STATUS bit masks and bit positions */ -#define OSC_PLLRDY_bm 0x10 /* PLL Ready bit mask. */ -#define OSC_PLLRDY_bp 4 /* PLL Ready bit position. */ - -#define OSC_XOSCRDY_bm 0x08 /* External Oscillator Ready bit mask. */ -#define OSC_XOSCRDY_bp 3 /* External Oscillator Ready bit position. */ - -#define OSC_RC32KRDY_bm 0x04 /* Internal 32kHz RC Oscillator Ready bit mask. */ -#define OSC_RC32KRDY_bp 2 /* Internal 32kHz RC Oscillator Ready bit position. */ - -#define OSC_RC32MRDY_bm 0x02 /* Internal 32MHz RC Oscillator Ready bit mask. */ -#define OSC_RC32MRDY_bp 1 /* Internal 32MHz RC Oscillator Ready bit position. */ - -#define OSC_RC2MRDY_bm 0x01 /* Internal 2MHz RC Oscillator Ready bit mask. */ -#define OSC_RC2MRDY_bp 0 /* Internal 2MHz RC Oscillator Ready bit position. */ - - -/* OSC.XOSCCTRL bit masks and bit positions */ -#define OSC_FRQRANGE_gm 0xC0 /* Frequency Range group mask. */ -#define OSC_FRQRANGE_gp 6 /* Frequency Range group position. */ -#define OSC_FRQRANGE0_bm (1<<6) /* Frequency Range bit 0 mask. */ -#define OSC_FRQRANGE0_bp 6 /* Frequency Range bit 0 position. */ -#define OSC_FRQRANGE1_bm (1<<7) /* Frequency Range bit 1 mask. */ -#define OSC_FRQRANGE1_bp 7 /* Frequency Range bit 1 position. */ - -#define OSC_X32KLPM_bm 0x20 /* 32kHz XTAL OSC Low-power Mode bit mask. */ -#define OSC_X32KLPM_bp 5 /* 32kHz XTAL OSC Low-power Mode bit position. */ - -#define OSC_XOSCSEL_gm 0x0F /* External Oscillator Selection and Startup Time group mask. */ -#define OSC_XOSCSEL_gp 0 /* External Oscillator Selection and Startup Time group position. */ -#define OSC_XOSCSEL0_bm (1<<0) /* External Oscillator Selection and Startup Time bit 0 mask. */ -#define OSC_XOSCSEL0_bp 0 /* External Oscillator Selection and Startup Time bit 0 position. */ -#define OSC_XOSCSEL1_bm (1<<1) /* External Oscillator Selection and Startup Time bit 1 mask. */ -#define OSC_XOSCSEL1_bp 1 /* External Oscillator Selection and Startup Time bit 1 position. */ -#define OSC_XOSCSEL2_bm (1<<2) /* External Oscillator Selection and Startup Time bit 2 mask. */ -#define OSC_XOSCSEL2_bp 2 /* External Oscillator Selection and Startup Time bit 2 position. */ -#define OSC_XOSCSEL3_bm (1<<3) /* External Oscillator Selection and Startup Time bit 3 mask. */ -#define OSC_XOSCSEL3_bp 3 /* External Oscillator Selection and Startup Time bit 3 position. */ - - -/* OSC.XOSCFAIL bit masks and bit positions */ -#define OSC_XOSCFDIF_bm 0x02 /* Failure Detection Interrupt Flag bit mask. */ -#define OSC_XOSCFDIF_bp 1 /* Failure Detection Interrupt Flag bit position. */ - -#define OSC_XOSCFDEN_bm 0x01 /* Failure Detection Enable bit mask. */ -#define OSC_XOSCFDEN_bp 0 /* Failure Detection Enable bit position. */ - - -/* OSC.PLLCTRL bit masks and bit positions */ -#define OSC_PLLSRC_gm 0xC0 /* Clock Source group mask. */ -#define OSC_PLLSRC_gp 6 /* Clock Source group position. */ -#define OSC_PLLSRC0_bm (1<<6) /* Clock Source bit 0 mask. */ -#define OSC_PLLSRC0_bp 6 /* Clock Source bit 0 position. */ -#define OSC_PLLSRC1_bm (1<<7) /* Clock Source bit 1 mask. */ -#define OSC_PLLSRC1_bp 7 /* Clock Source bit 1 position. */ - -#define OSC_PLLFAC_gm 0x1F /* Multiplication Factor group mask. */ -#define OSC_PLLFAC_gp 0 /* Multiplication Factor group position. */ -#define OSC_PLLFAC0_bm (1<<0) /* Multiplication Factor bit 0 mask. */ -#define OSC_PLLFAC0_bp 0 /* Multiplication Factor bit 0 position. */ -#define OSC_PLLFAC1_bm (1<<1) /* Multiplication Factor bit 1 mask. */ -#define OSC_PLLFAC1_bp 1 /* Multiplication Factor bit 1 position. */ -#define OSC_PLLFAC2_bm (1<<2) /* Multiplication Factor bit 2 mask. */ -#define OSC_PLLFAC2_bp 2 /* Multiplication Factor bit 2 position. */ -#define OSC_PLLFAC3_bm (1<<3) /* Multiplication Factor bit 3 mask. */ -#define OSC_PLLFAC3_bp 3 /* Multiplication Factor bit 3 position. */ -#define OSC_PLLFAC4_bm (1<<4) /* Multiplication Factor bit 4 mask. */ -#define OSC_PLLFAC4_bp 4 /* Multiplication Factor bit 4 position. */ - - -/* OSC.DFLLCTRL bit masks and bit positions */ -#define OSC_RC32MCREF_bm 0x02 /* 32MHz Calibration Reference bit mask. */ -#define OSC_RC32MCREF_bp 1 /* 32MHz Calibration Reference bit position. */ - -#define OSC_RC2MCREF_bm 0x01 /* 2MHz Calibration Reference bit mask. */ -#define OSC_RC2MCREF_bp 0 /* 2MHz Calibration Reference bit position. */ - - -/* DFLL - DFLL */ -/* DFLL.CTRL bit masks and bit positions */ -#define DFLL_ENABLE_bm 0x01 /* DFLL Enable bit mask. */ -#define DFLL_ENABLE_bp 0 /* DFLL Enable bit position. */ - - -/* DFLL.CALA bit masks and bit positions */ -#define DFLL_CALL_gm 0x7F /* DFLL Calibration bits [6:0] group mask. */ -#define DFLL_CALL_gp 0 /* DFLL Calibration bits [6:0] group position. */ -#define DFLL_CALL0_bm (1<<0) /* DFLL Calibration bits [6:0] bit 0 mask. */ -#define DFLL_CALL0_bp 0 /* DFLL Calibration bits [6:0] bit 0 position. */ -#define DFLL_CALL1_bm (1<<1) /* DFLL Calibration bits [6:0] bit 1 mask. */ -#define DFLL_CALL1_bp 1 /* DFLL Calibration bits [6:0] bit 1 position. */ -#define DFLL_CALL2_bm (1<<2) /* DFLL Calibration bits [6:0] bit 2 mask. */ -#define DFLL_CALL2_bp 2 /* DFLL Calibration bits [6:0] bit 2 position. */ -#define DFLL_CALL3_bm (1<<3) /* DFLL Calibration bits [6:0] bit 3 mask. */ -#define DFLL_CALL3_bp 3 /* DFLL Calibration bits [6:0] bit 3 position. */ -#define DFLL_CALL4_bm (1<<4) /* DFLL Calibration bits [6:0] bit 4 mask. */ -#define DFLL_CALL4_bp 4 /* DFLL Calibration bits [6:0] bit 4 position. */ -#define DFLL_CALL5_bm (1<<5) /* DFLL Calibration bits [6:0] bit 5 mask. */ -#define DFLL_CALL5_bp 5 /* DFLL Calibration bits [6:0] bit 5 position. */ -#define DFLL_CALL6_bm (1<<6) /* DFLL Calibration bits [6:0] bit 6 mask. */ -#define DFLL_CALL6_bp 6 /* DFLL Calibration bits [6:0] bit 6 position. */ - - -/* DFLL.CALB bit masks and bit positions */ -#define DFLL_CALH_gm 0x3F /* DFLL Calibration bits [12:7] group mask. */ -#define DFLL_CALH_gp 0 /* DFLL Calibration bits [12:7] group position. */ -#define DFLL_CALH0_bm (1<<0) /* DFLL Calibration bits [12:7] bit 0 mask. */ -#define DFLL_CALH0_bp 0 /* DFLL Calibration bits [12:7] bit 0 position. */ -#define DFLL_CALH1_bm (1<<1) /* DFLL Calibration bits [12:7] bit 1 mask. */ -#define DFLL_CALH1_bp 1 /* DFLL Calibration bits [12:7] bit 1 position. */ -#define DFLL_CALH2_bm (1<<2) /* DFLL Calibration bits [12:7] bit 2 mask. */ -#define DFLL_CALH2_bp 2 /* DFLL Calibration bits [12:7] bit 2 position. */ -#define DFLL_CALH3_bm (1<<3) /* DFLL Calibration bits [12:7] bit 3 mask. */ -#define DFLL_CALH3_bp 3 /* DFLL Calibration bits [12:7] bit 3 position. */ -#define DFLL_CALH4_bm (1<<4) /* DFLL Calibration bits [12:7] bit 4 mask. */ -#define DFLL_CALH4_bp 4 /* DFLL Calibration bits [12:7] bit 4 position. */ -#define DFLL_CALH5_bm (1<<5) /* DFLL Calibration bits [12:7] bit 5 mask. */ -#define DFLL_CALH5_bp 5 /* DFLL Calibration bits [12:7] bit 5 position. */ - - -/* RST - Reset */ -/* RST.STATUS bit masks and bit positions */ -#define RST_SDRF_bm 0x40 /* Spike Detection Reset Flag bit mask. */ -#define RST_SDRF_bp 6 /* Spike Detection Reset Flag bit position. */ - -#define RST_SRF_bm 0x20 /* Software Reset Flag bit mask. */ -#define RST_SRF_bp 5 /* Software Reset Flag bit position. */ - -#define RST_PDIRF_bm 0x10 /* Programming and Debug Interface Interface Reset Flag bit mask. */ -#define RST_PDIRF_bp 4 /* Programming and Debug Interface Interface Reset Flag bit position. */ - -#define RST_WDRF_bm 0x08 /* Watchdog Reset Flag bit mask. */ -#define RST_WDRF_bp 3 /* Watchdog Reset Flag bit position. */ - -#define RST_BORF_bm 0x04 /* Brown-out Reset Flag bit mask. */ -#define RST_BORF_bp 2 /* Brown-out Reset Flag bit position. */ - -#define RST_EXTRF_bm 0x02 /* External Reset Flag bit mask. */ -#define RST_EXTRF_bp 1 /* External Reset Flag bit position. */ - -#define RST_PORF_bm 0x01 /* Power-on Reset Flag bit mask. */ -#define RST_PORF_bp 0 /* Power-on Reset Flag bit position. */ - - -/* RST.CTRL bit masks and bit positions */ -#define RST_SWRST_bm 0x01 /* Software Reset bit mask. */ -#define RST_SWRST_bp 0 /* Software Reset bit position. */ - - -/* WDT - Watch-Dog Timer */ -/* WDT.CTRL bit masks and bit positions */ -#define WDT_PER_gm 0x3C /* Period group mask. */ -#define WDT_PER_gp 2 /* Period group position. */ -#define WDT_PER0_bm (1<<2) /* Period bit 0 mask. */ -#define WDT_PER0_bp 2 /* Period bit 0 position. */ -#define WDT_PER1_bm (1<<3) /* Period bit 1 mask. */ -#define WDT_PER1_bp 3 /* Period bit 1 position. */ -#define WDT_PER2_bm (1<<4) /* Period bit 2 mask. */ -#define WDT_PER2_bp 4 /* Period bit 2 position. */ -#define WDT_PER3_bm (1<<5) /* Period bit 3 mask. */ -#define WDT_PER3_bp 5 /* Period bit 3 position. */ - -#define WDT_ENABLE_bm 0x02 /* Enable bit mask. */ -#define WDT_ENABLE_bp 1 /* Enable bit position. */ - -#define WDT_CEN_bm 0x01 /* Change Enable bit mask. */ -#define WDT_CEN_bp 0 /* Change Enable bit position. */ - - -/* WDT.WINCTRL bit masks and bit positions */ -#define WDT_WPER_gm 0x3C /* Windowed Mode Period group mask. */ -#define WDT_WPER_gp 2 /* Windowed Mode Period group position. */ -#define WDT_WPER0_bm (1<<2) /* Windowed Mode Period bit 0 mask. */ -#define WDT_WPER0_bp 2 /* Windowed Mode Period bit 0 position. */ -#define WDT_WPER1_bm (1<<3) /* Windowed Mode Period bit 1 mask. */ -#define WDT_WPER1_bp 3 /* Windowed Mode Period bit 1 position. */ -#define WDT_WPER2_bm (1<<4) /* Windowed Mode Period bit 2 mask. */ -#define WDT_WPER2_bp 4 /* Windowed Mode Period bit 2 position. */ -#define WDT_WPER3_bm (1<<5) /* Windowed Mode Period bit 3 mask. */ -#define WDT_WPER3_bp 5 /* Windowed Mode Period bit 3 position. */ - -#define WDT_WEN_bm 0x02 /* Windowed Mode Enable bit mask. */ -#define WDT_WEN_bp 1 /* Windowed Mode Enable bit position. */ - -#define WDT_WCEN_bm 0x01 /* Windowed Mode Change Enable bit mask. */ -#define WDT_WCEN_bp 0 /* Windowed Mode Change Enable bit position. */ - - -/* WDT.STATUS bit masks and bit positions */ -#define WDT_SYNCBUSY_bm 0x01 /* Syncronization busy bit mask. */ -#define WDT_SYNCBUSY_bp 0 /* Syncronization busy bit position. */ - - -/* MCU - MCU Control */ -/* MCU.MCUCR bit masks and bit positions */ -#define MCU_JTAGD_bm 0x01 /* JTAG Disable bit mask. */ -#define MCU_JTAGD_bp 0 /* JTAG Disable bit position. */ - - -/* MCU.EVSYSLOCK bit masks and bit positions */ -#define MCU_EVSYS1LOCK_bm 0x10 /* Event Channel 4-7 Lock bit mask. */ -#define MCU_EVSYS1LOCK_bp 4 /* Event Channel 4-7 Lock bit position. */ - -#define MCU_EVSYS0LOCK_bm 0x01 /* Event Channel 0-3 Lock bit mask. */ -#define MCU_EVSYS0LOCK_bp 0 /* Event Channel 0-3 Lock bit position. */ - - -/* MCU.AWEXLOCK bit masks and bit positions */ -#define MCU_AWEXELOCK_bm 0x04 /* AWeX on T/C E0 Lock bit mask. */ -#define MCU_AWEXELOCK_bp 2 /* AWeX on T/C E0 Lock bit position. */ - -#define MCU_AWEXCLOCK_bm 0x01 /* AWeX on T/C C0 Lock bit mask. */ -#define MCU_AWEXCLOCK_bp 0 /* AWeX on T/C C0 Lock bit position. */ - - -/* PMIC - Programmable Multi-level Interrupt Controller */ -/* PMIC.STATUS bit masks and bit positions */ -#define PMIC_NMIEX_bm 0x80 /* Non-maskable Interrupt Executing bit mask. */ -#define PMIC_NMIEX_bp 7 /* Non-maskable Interrupt Executing bit position. */ - -#define PMIC_HILVLEX_bm 0x04 /* High Level Interrupt Executing bit mask. */ -#define PMIC_HILVLEX_bp 2 /* High Level Interrupt Executing bit position. */ - -#define PMIC_MEDLVLEX_bm 0x02 /* Medium Level Interrupt Executing bit mask. */ -#define PMIC_MEDLVLEX_bp 1 /* Medium Level Interrupt Executing bit position. */ - -#define PMIC_LOLVLEX_bm 0x01 /* Low Level Interrupt Executing bit mask. */ -#define PMIC_LOLVLEX_bp 0 /* Low Level Interrupt Executing bit position. */ - - -/* PMIC.CTRL bit masks and bit positions */ -#define PMIC_RREN_bm 0x80 /* Round-Robin Priority Enable bit mask. */ -#define PMIC_RREN_bp 7 /* Round-Robin Priority Enable bit position. */ - -#define PMIC_IVSEL_bm 0x40 /* Interrupt Vector Select bit mask. */ -#define PMIC_IVSEL_bp 6 /* Interrupt Vector Select bit position. */ - -#define PMIC_HILVLEN_bm 0x04 /* High Level Enable bit mask. */ -#define PMIC_HILVLEN_bp 2 /* High Level Enable bit position. */ - -#define PMIC_MEDLVLEN_bm 0x02 /* Medium Level Enable bit mask. */ -#define PMIC_MEDLVLEN_bp 1 /* Medium Level Enable bit position. */ - -#define PMIC_LOLVLEN_bm 0x01 /* Low Level Enable bit mask. */ -#define PMIC_LOLVLEN_bp 0 /* Low Level Enable bit position. */ - - -/* CRC - Cyclic Redundancy Checker */ -/* CRC.CTRL bit masks and bit positions */ -#define CRC_RESET_gm 0xC0 /* Reset group mask. */ -#define CRC_RESET_gp 6 /* Reset group position. */ -#define CRC_RESET0_bm (1<<6) /* Reset bit 0 mask. */ -#define CRC_RESET0_bp 6 /* Reset bit 0 position. */ -#define CRC_RESET1_bm (1<<7) /* Reset bit 1 mask. */ -#define CRC_RESET1_bp 7 /* Reset bit 1 position. */ - -#define CRC_CRC32_bm 0x20 /* CRC Mode bit mask. */ -#define CRC_CRC32_bp 5 /* CRC Mode bit position. */ - -#define CRC_SOURCE_gm 0x0F /* Input Source group mask. */ -#define CRC_SOURCE_gp 0 /* Input Source group position. */ -#define CRC_SOURCE0_bm (1<<0) /* Input Source bit 0 mask. */ -#define CRC_SOURCE0_bp 0 /* Input Source bit 0 position. */ -#define CRC_SOURCE1_bm (1<<1) /* Input Source bit 1 mask. */ -#define CRC_SOURCE1_bp 1 /* Input Source bit 1 position. */ -#define CRC_SOURCE2_bm (1<<2) /* Input Source bit 2 mask. */ -#define CRC_SOURCE2_bp 2 /* Input Source bit 2 position. */ -#define CRC_SOURCE3_bm (1<<3) /* Input Source bit 3 mask. */ -#define CRC_SOURCE3_bp 3 /* Input Source bit 3 position. */ - -/* CRC.STATUS bit masks and bit positions */ -#define CRC_ZERO_bm 0x02 /* Zero detection bit mask. */ -#define CRC_ZERO_bp 1 /* Zero detection bit position. */ - -#define CRC_BUSY_bm 0x01 /* Busy bit mask. */ -#define CRC_BUSY_bp 0 /* Busy bit position. */ - - -/* EVSYS - Event System */ -/* EVSYS.CH0MUX bit masks and bit positions */ -#define EVSYS_CHMUX_gm 0xFF /* Event Channel 0 Multiplexer group mask. */ -#define EVSYS_CHMUX_gp 0 /* Event Channel 0 Multiplexer group position. */ -#define EVSYS_CHMUX0_bm (1<<0) /* Event Channel 0 Multiplexer bit 0 mask. */ -#define EVSYS_CHMUX0_bp 0 /* Event Channel 0 Multiplexer bit 0 position. */ -#define EVSYS_CHMUX1_bm (1<<1) /* Event Channel 0 Multiplexer bit 1 mask. */ -#define EVSYS_CHMUX1_bp 1 /* Event Channel 0 Multiplexer bit 1 position. */ -#define EVSYS_CHMUX2_bm (1<<2) /* Event Channel 0 Multiplexer bit 2 mask. */ -#define EVSYS_CHMUX2_bp 2 /* Event Channel 0 Multiplexer bit 2 position. */ -#define EVSYS_CHMUX3_bm (1<<3) /* Event Channel 0 Multiplexer bit 3 mask. */ -#define EVSYS_CHMUX3_bp 3 /* Event Channel 0 Multiplexer bit 3 position. */ -#define EVSYS_CHMUX4_bm (1<<4) /* Event Channel 0 Multiplexer bit 4 mask. */ -#define EVSYS_CHMUX4_bp 4 /* Event Channel 0 Multiplexer bit 4 position. */ -#define EVSYS_CHMUX5_bm (1<<5) /* Event Channel 0 Multiplexer bit 5 mask. */ -#define EVSYS_CHMUX5_bp 5 /* Event Channel 0 Multiplexer bit 5 position. */ -#define EVSYS_CHMUX6_bm (1<<6) /* Event Channel 0 Multiplexer bit 6 mask. */ -#define EVSYS_CHMUX6_bp 6 /* Event Channel 0 Multiplexer bit 6 position. */ -#define EVSYS_CHMUX7_bm (1<<7) /* Event Channel 0 Multiplexer bit 7 mask. */ -#define EVSYS_CHMUX7_bp 7 /* Event Channel 0 Multiplexer bit 7 position. */ - - -/* EVSYS.CH1MUX bit masks and bit positions */ -/* EVSYS_CHMUX_gm Predefined. */ -/* EVSYS_CHMUX_gp Predefined. */ -/* EVSYS_CHMUX0_bm Predefined. */ -/* EVSYS_CHMUX0_bp Predefined. */ -/* EVSYS_CHMUX1_bm Predefined. */ -/* EVSYS_CHMUX1_bp Predefined. */ -/* EVSYS_CHMUX2_bm Predefined. */ -/* EVSYS_CHMUX2_bp Predefined. */ -/* EVSYS_CHMUX3_bm Predefined. */ -/* EVSYS_CHMUX3_bp Predefined. */ -/* EVSYS_CHMUX4_bm Predefined. */ -/* EVSYS_CHMUX4_bp Predefined. */ -/* EVSYS_CHMUX5_bm Predefined. */ -/* EVSYS_CHMUX5_bp Predefined. */ -/* EVSYS_CHMUX6_bm Predefined. */ -/* EVSYS_CHMUX6_bp Predefined. */ -/* EVSYS_CHMUX7_bm Predefined. */ -/* EVSYS_CHMUX7_bp Predefined. */ - - -/* EVSYS.CH2MUX bit masks and bit positions */ -/* EVSYS_CHMUX_gm Predefined. */ -/* EVSYS_CHMUX_gp Predefined. */ -/* EVSYS_CHMUX0_bm Predefined. */ -/* EVSYS_CHMUX0_bp Predefined. */ -/* EVSYS_CHMUX1_bm Predefined. */ -/* EVSYS_CHMUX1_bp Predefined. */ -/* EVSYS_CHMUX2_bm Predefined. */ -/* EVSYS_CHMUX2_bp Predefined. */ -/* EVSYS_CHMUX3_bm Predefined. */ -/* EVSYS_CHMUX3_bp Predefined. */ -/* EVSYS_CHMUX4_bm Predefined. */ -/* EVSYS_CHMUX4_bp Predefined. */ -/* EVSYS_CHMUX5_bm Predefined. */ -/* EVSYS_CHMUX5_bp Predefined. */ -/* EVSYS_CHMUX6_bm Predefined. */ -/* EVSYS_CHMUX6_bp Predefined. */ -/* EVSYS_CHMUX7_bm Predefined. */ -/* EVSYS_CHMUX7_bp Predefined. */ - - -/* EVSYS.CH3MUX bit masks and bit positions */ -/* EVSYS_CHMUX_gm Predefined. */ -/* EVSYS_CHMUX_gp Predefined. */ -/* EVSYS_CHMUX0_bm Predefined. */ -/* EVSYS_CHMUX0_bp Predefined. */ -/* EVSYS_CHMUX1_bm Predefined. */ -/* EVSYS_CHMUX1_bp Predefined. */ -/* EVSYS_CHMUX2_bm Predefined. */ -/* EVSYS_CHMUX2_bp Predefined. */ -/* EVSYS_CHMUX3_bm Predefined. */ -/* EVSYS_CHMUX3_bp Predefined. */ -/* EVSYS_CHMUX4_bm Predefined. */ -/* EVSYS_CHMUX4_bp Predefined. */ -/* EVSYS_CHMUX5_bm Predefined. */ -/* EVSYS_CHMUX5_bp Predefined. */ -/* EVSYS_CHMUX6_bm Predefined. */ -/* EVSYS_CHMUX6_bp Predefined. */ -/* EVSYS_CHMUX7_bm Predefined. */ -/* EVSYS_CHMUX7_bp Predefined. */ - - -/* EVSYS.CH0CTRL bit masks and bit positions */ -#define EVSYS_QDIRM_gm 0x60 /* Quadrature Decoder Index Recognition Mode group mask. */ -#define EVSYS_QDIRM_gp 5 /* Quadrature Decoder Index Recognition Mode group position. */ -#define EVSYS_QDIRM0_bm (1<<5) /* Quadrature Decoder Index Recognition Mode bit 0 mask. */ -#define EVSYS_QDIRM0_bp 5 /* Quadrature Decoder Index Recognition Mode bit 0 position. */ -#define EVSYS_QDIRM1_bm (1<<6) /* Quadrature Decoder Index Recognition Mode bit 1 mask. */ -#define EVSYS_QDIRM1_bp 6 /* Quadrature Decoder Index Recognition Mode bit 1 position. */ - -#define EVSYS_QDIEN_bm 0x10 /* Quadrature Decoder Index Enable bit mask. */ -#define EVSYS_QDIEN_bp 4 /* Quadrature Decoder Index Enable bit position. */ - -#define EVSYS_QDEN_bm 0x08 /* Quadrature Decoder Enable bit mask. */ -#define EVSYS_QDEN_bp 3 /* Quadrature Decoder Enable bit position. */ - -#define EVSYS_DIGFILT_gm 0x07 /* Digital Filter group mask. */ -#define EVSYS_DIGFILT_gp 0 /* Digital Filter group position. */ -#define EVSYS_DIGFILT0_bm (1<<0) /* Digital Filter bit 0 mask. */ -#define EVSYS_DIGFILT0_bp 0 /* Digital Filter bit 0 position. */ -#define EVSYS_DIGFILT1_bm (1<<1) /* Digital Filter bit 1 mask. */ -#define EVSYS_DIGFILT1_bp 1 /* Digital Filter bit 1 position. */ -#define EVSYS_DIGFILT2_bm (1<<2) /* Digital Filter bit 2 mask. */ -#define EVSYS_DIGFILT2_bp 2 /* Digital Filter bit 2 position. */ - - -/* EVSYS.CH1CTRL bit masks and bit positions */ -/* EVSYS_DIGFILT_gm Predefined. */ -/* EVSYS_DIGFILT_gp Predefined. */ -/* EVSYS_DIGFILT0_bm Predefined. */ -/* EVSYS_DIGFILT0_bp Predefined. */ -/* EVSYS_DIGFILT1_bm Predefined. */ -/* EVSYS_DIGFILT1_bp Predefined. */ -/* EVSYS_DIGFILT2_bm Predefined. */ -/* EVSYS_DIGFILT2_bp Predefined. */ - - -/* EVSYS.CH2CTRL bit masks and bit positions */ -/* EVSYS_QDIRM_gm Predefined. */ -/* EVSYS_QDIRM_gp Predefined. */ -/* EVSYS_QDIRM0_bm Predefined. */ -/* EVSYS_QDIRM0_bp Predefined. */ -/* EVSYS_QDIRM1_bm Predefined. */ -/* EVSYS_QDIRM1_bp Predefined. */ - -/* EVSYS_QDIEN_bm Predefined. */ -/* EVSYS_QDIEN_bp Predefined. */ - -/* EVSYS_QDEN_bm Predefined. */ -/* EVSYS_QDEN_bp Predefined. */ - -/* EVSYS_DIGFILT_gm Predefined. */ -/* EVSYS_DIGFILT_gp Predefined. */ -/* EVSYS_DIGFILT0_bm Predefined. */ -/* EVSYS_DIGFILT0_bp Predefined. */ -/* EVSYS_DIGFILT1_bm Predefined. */ -/* EVSYS_DIGFILT1_bp Predefined. */ -/* EVSYS_DIGFILT2_bm Predefined. */ -/* EVSYS_DIGFILT2_bp Predefined. */ - - -/* EVSYS.CH3CTRL bit masks and bit positions */ -/* EVSYS_DIGFILT_gm Predefined. */ -/* EVSYS_DIGFILT_gp Predefined. */ -/* EVSYS_DIGFILT0_bm Predefined. */ -/* EVSYS_DIGFILT0_bp Predefined. */ -/* EVSYS_DIGFILT1_bm Predefined. */ -/* EVSYS_DIGFILT1_bp Predefined. */ -/* EVSYS_DIGFILT2_bm Predefined. */ -/* EVSYS_DIGFILT2_bp Predefined. */ - - -/* NVM - Non Volatile Memory Controller */ -/* NVM.CMD bit masks and bit positions */ -#define NVM_CMD_gm 0xFF /* Command group mask. */ -#define NVM_CMD_gp 0 /* Command group position. */ -#define NVM_CMD0_bm (1<<0) /* Command bit 0 mask. */ -#define NVM_CMD0_bp 0 /* Command bit 0 position. */ -#define NVM_CMD1_bm (1<<1) /* Command bit 1 mask. */ -#define NVM_CMD1_bp 1 /* Command bit 1 position. */ -#define NVM_CMD2_bm (1<<2) /* Command bit 2 mask. */ -#define NVM_CMD2_bp 2 /* Command bit 2 position. */ -#define NVM_CMD3_bm (1<<3) /* Command bit 3 mask. */ -#define NVM_CMD3_bp 3 /* Command bit 3 position. */ -#define NVM_CMD4_bm (1<<4) /* Command bit 4 mask. */ -#define NVM_CMD4_bp 4 /* Command bit 4 position. */ -#define NVM_CMD5_bm (1<<5) /* Command bit 5 mask. */ -#define NVM_CMD5_bp 5 /* Command bit 5 position. */ -#define NVM_CMD6_bm (1<<6) /* Command bit 6 mask. */ -#define NVM_CMD6_bp 6 /* Command bit 6 position. */ -#define NVM_CMD7_bm (1<<7) /* Command bit 7 mask. */ -#define NVM_CMD7_bp 7 /* Command bit 7 position. */ - - -/* NVM.CTRLA bit masks and bit positions */ -#define NVM_CMDEX_bm 0x01 /* Command Execute bit mask. */ -#define NVM_CMDEX_bp 0 /* Command Execute bit position. */ - - -/* NVM.CTRLB bit masks and bit positions */ -#define NVM_EEMAPEN_bm 0x08 /* EEPROM Mapping Enable bit mask. */ -#define NVM_EEMAPEN_bp 3 /* EEPROM Mapping Enable bit position. */ - -#define NVM_FPRM_bm 0x04 /* Flash Power Reduction Enable bit mask. */ -#define NVM_FPRM_bp 2 /* Flash Power Reduction Enable bit position. */ - -#define NVM_EPRM_bm 0x02 /* EEPROM Power Reduction Enable bit mask. */ -#define NVM_EPRM_bp 1 /* EEPROM Power Reduction Enable bit position. */ - -#define NVM_SPMLOCK_bm 0x01 /* SPM Lock bit mask. */ -#define NVM_SPMLOCK_bp 0 /* SPM Lock bit position. */ - - -/* NVM.INTCTRL bit masks and bit positions */ -#define NVM_SPMLVL_gm 0x0C /* SPM Interrupt Level group mask. */ -#define NVM_SPMLVL_gp 2 /* SPM Interrupt Level group position. */ -#define NVM_SPMLVL0_bm (1<<2) /* SPM Interrupt Level bit 0 mask. */ -#define NVM_SPMLVL0_bp 2 /* SPM Interrupt Level bit 0 position. */ -#define NVM_SPMLVL1_bm (1<<3) /* SPM Interrupt Level bit 1 mask. */ -#define NVM_SPMLVL1_bp 3 /* SPM Interrupt Level bit 1 position. */ - -#define NVM_EELVL_gm 0x03 /* EEPROM Interrupt Level group mask. */ -#define NVM_EELVL_gp 0 /* EEPROM Interrupt Level group position. */ -#define NVM_EELVL0_bm (1<<0) /* EEPROM Interrupt Level bit 0 mask. */ -#define NVM_EELVL0_bp 0 /* EEPROM Interrupt Level bit 0 position. */ -#define NVM_EELVL1_bm (1<<1) /* EEPROM Interrupt Level bit 1 mask. */ -#define NVM_EELVL1_bp 1 /* EEPROM Interrupt Level bit 1 position. */ - - -/* NVM.STATUS bit masks and bit positions */ -#define NVM_NVMBUSY_bm 0x80 /* Non-volatile Memory Busy bit mask. */ -#define NVM_NVMBUSY_bp 7 /* Non-volatile Memory Busy bit position. */ - -#define NVM_FBUSY_bm 0x40 /* Flash Memory Busy bit mask. */ -#define NVM_FBUSY_bp 6 /* Flash Memory Busy bit position. */ - -#define NVM_EELOAD_bm 0x02 /* EEPROM Page Buffer Active Loading bit mask. */ -#define NVM_EELOAD_bp 1 /* EEPROM Page Buffer Active Loading bit position. */ - -#define NVM_FLOAD_bm 0x01 /* Flash Page Buffer Active Loading bit mask. */ -#define NVM_FLOAD_bp 0 /* Flash Page Buffer Active Loading bit position. */ - - -/* NVM.LOCKBITS bit masks and bit positions */ -#define NVM_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ -#define NVM_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ -#define NVM_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ -#define NVM_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ -#define NVM_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ -#define NVM_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ - -#define NVM_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ -#define NVM_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ -#define NVM_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ -#define NVM_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ -#define NVM_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ -#define NVM_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ - -#define NVM_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ -#define NVM_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ -#define NVM_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ -#define NVM_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ -#define NVM_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ -#define NVM_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ - -#define NVM_LB_gm 0x03 /* Lock Bits group mask. */ -#define NVM_LB_gp 0 /* Lock Bits group position. */ -#define NVM_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ -#define NVM_LB0_bp 0 /* Lock Bits bit 0 position. */ -#define NVM_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ -#define NVM_LB1_bp 1 /* Lock Bits bit 1 position. */ - - -/* NVM_LOCKBITS.LOCKBITS bit masks and bit positions */ -#define NVM_LOCKBITS_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ -#define NVM_LOCKBITS_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ -#define NVM_LOCKBITS_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ -#define NVM_LOCKBITS_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ -#define NVM_LOCKBITS_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ -#define NVM_LOCKBITS_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ - -#define NVM_LOCKBITS_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ -#define NVM_LOCKBITS_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ -#define NVM_LOCKBITS_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ -#define NVM_LOCKBITS_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ -#define NVM_LOCKBITS_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ -#define NVM_LOCKBITS_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ - -#define NVM_LOCKBITS_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ -#define NVM_LOCKBITS_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ -#define NVM_LOCKBITS_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ -#define NVM_LOCKBITS_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ -#define NVM_LOCKBITS_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ -#define NVM_LOCKBITS_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ - -#define NVM_LOCKBITS_LB_gm 0x03 /* Lock Bits group mask. */ -#define NVM_LOCKBITS_LB_gp 0 /* Lock Bits group position. */ -#define NVM_LOCKBITS_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ -#define NVM_LOCKBITS_LB0_bp 0 /* Lock Bits bit 0 position. */ -#define NVM_LOCKBITS_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ -#define NVM_LOCKBITS_LB1_bp 1 /* Lock Bits bit 1 position. */ - - -/* NVM_FUSES.FUSEBYTE0 bit masks and bit positions */ -#define NVM_FUSES_USERID_gm 0xFF /* User ID group mask. */ -#define NVM_FUSES_USERID_gp 0 /* User ID group position. */ -#define NVM_FUSES_USERID0_bm (1<<0) /* User ID bit 0 mask. */ -#define NVM_FUSES_USERID0_bp 0 /* User ID bit 0 position. */ -#define NVM_FUSES_USERID1_bm (1<<1) /* User ID bit 1 mask. */ -#define NVM_FUSES_USERID1_bp 1 /* User ID bit 1 position. */ -#define NVM_FUSES_USERID2_bm (1<<2) /* User ID bit 2 mask. */ -#define NVM_FUSES_USERID2_bp 2 /* User ID bit 2 position. */ -#define NVM_FUSES_USERID3_bm (1<<3) /* User ID bit 3 mask. */ -#define NVM_FUSES_USERID3_bp 3 /* User ID bit 3 position. */ -#define NVM_FUSES_USERID4_bm (1<<4) /* User ID bit 4 mask. */ -#define NVM_FUSES_USERID4_bp 4 /* User ID bit 4 position. */ -#define NVM_FUSES_USERID5_bm (1<<5) /* User ID bit 5 mask. */ -#define NVM_FUSES_USERID5_bp 5 /* User ID bit 5 position. */ -#define NVM_FUSES_USERID6_bm (1<<6) /* User ID bit 6 mask. */ -#define NVM_FUSES_USERID6_bp 6 /* User ID bit 6 position. */ -#define NVM_FUSES_USERID7_bm (1<<7) /* User ID bit 7 mask. */ -#define NVM_FUSES_USERID7_bp 7 /* User ID bit 7 position. */ - - -/* NVM_FUSES.FUSEBYTE1 bit masks and bit positions */ -#define NVM_FUSES_WDWP_gm 0xF0 /* Watchdog Window Timeout Period group mask. */ -#define NVM_FUSES_WDWP_gp 4 /* Watchdog Window Timeout Period group position. */ -#define NVM_FUSES_WDWP0_bm (1<<4) /* Watchdog Window Timeout Period bit 0 mask. */ -#define NVM_FUSES_WDWP0_bp 4 /* Watchdog Window Timeout Period bit 0 position. */ -#define NVM_FUSES_WDWP1_bm (1<<5) /* Watchdog Window Timeout Period bit 1 mask. */ -#define NVM_FUSES_WDWP1_bp 5 /* Watchdog Window Timeout Period bit 1 position. */ -#define NVM_FUSES_WDWP2_bm (1<<6) /* Watchdog Window Timeout Period bit 2 mask. */ -#define NVM_FUSES_WDWP2_bp 6 /* Watchdog Window Timeout Period bit 2 position. */ -#define NVM_FUSES_WDWP3_bm (1<<7) /* Watchdog Window Timeout Period bit 3 mask. */ -#define NVM_FUSES_WDWP3_bp 7 /* Watchdog Window Timeout Period bit 3 position. */ - -#define NVM_FUSES_WDP_gm 0x0F /* Watchdog Timeout Period group mask. */ -#define NVM_FUSES_WDP_gp 0 /* Watchdog Timeout Period group position. */ -#define NVM_FUSES_WDP0_bm (1<<0) /* Watchdog Timeout Period bit 0 mask. */ -#define NVM_FUSES_WDP0_bp 0 /* Watchdog Timeout Period bit 0 position. */ -#define NVM_FUSES_WDP1_bm (1<<1) /* Watchdog Timeout Period bit 1 mask. */ -#define NVM_FUSES_WDP1_bp 1 /* Watchdog Timeout Period bit 1 position. */ -#define NVM_FUSES_WDP2_bm (1<<2) /* Watchdog Timeout Period bit 2 mask. */ -#define NVM_FUSES_WDP2_bp 2 /* Watchdog Timeout Period bit 2 position. */ -#define NVM_FUSES_WDP3_bm (1<<3) /* Watchdog Timeout Period bit 3 mask. */ -#define NVM_FUSES_WDP3_bp 3 /* Watchdog Timeout Period bit 3 position. */ - - -/* NVM_FUSES.FUSEBYTE2 bit masks and bit positions */ -#define NVM_FUSES_DVSDON_bm 0x80 /* Spike Detector Enable bit mask. */ -#define NVM_FUSES_DVSDON_bp 7 /* Spike Detector Enable bit position. */ - -#define NVM_FUSES_BOOTRST_bm 0x40 /* Boot Loader Section Reset Vector bit mask. */ -#define NVM_FUSES_BOOTRST_bp 6 /* Boot Loader Section Reset Vector bit position. */ - -#define NVM_FUSES_BODPD_gm 0x03 /* BOD Operation in Power-Down Mode group mask. */ -#define NVM_FUSES_BODPD_gp 0 /* BOD Operation in Power-Down Mode group position. */ -#define NVM_FUSES_BODPD0_bm (1<<0) /* BOD Operation in Power-Down Mode bit 0 mask. */ -#define NVM_FUSES_BODPD0_bp 0 /* BOD Operation in Power-Down Mode bit 0 position. */ -#define NVM_FUSES_BODPD1_bm (1<<1) /* BOD Operation in Power-Down Mode bit 1 mask. */ -#define NVM_FUSES_BODPD1_bp 1 /* BOD Operation in Power-Down Mode bit 1 position. */ - - -/* NVM_FUSES.FUSEBYTE4 bit masks and bit positions */ -#define NVM_FUSES_SUT_gm 0x0C /* Start-up Time group mask. */ -#define NVM_FUSES_SUT_gp 2 /* Start-up Time group position. */ -#define NVM_FUSES_SUT0_bm (1<<2) /* Start-up Time bit 0 mask. */ -#define NVM_FUSES_SUT0_bp 2 /* Start-up Time bit 0 position. */ -#define NVM_FUSES_SUT1_bm (1<<3) /* Start-up Time bit 1 mask. */ -#define NVM_FUSES_SUT1_bp 3 /* Start-up Time bit 1 position. */ - -#define NVM_FUSES_WDLOCK_bm 0x02 /* Watchdog Timer Lock bit mask. */ -#define NVM_FUSES_WDLOCK_bp 1 /* Watchdog Timer Lock bit position. */ - - -/* NVM_FUSES.FUSEBYTE5 bit masks and bit positions */ -#define NVM_FUSES_BODACT_gm 0x30 /* BOD Operation in Active Mode group mask. */ -#define NVM_FUSES_BODACT_gp 4 /* BOD Operation in Active Mode group position. */ -#define NVM_FUSES_BODACT0_bm (1<<4) /* BOD Operation in Active Mode bit 0 mask. */ -#define NVM_FUSES_BODACT0_bp 4 /* BOD Operation in Active Mode bit 0 position. */ -#define NVM_FUSES_BODACT1_bm (1<<5) /* BOD Operation in Active Mode bit 1 mask. */ -#define NVM_FUSES_BODACT1_bp 5 /* BOD Operation in Active Mode bit 1 position. */ - -#define NVM_FUSES_EESAVE_bm 0x08 /* Preserve EEPROM Through Chip Erase bit mask. */ -#define NVM_FUSES_EESAVE_bp 3 /* Preserve EEPROM Through Chip Erase bit position. */ - -#define NVM_FUSES_BODLVL_gm 0x07 /* Brown Out Detection Voltage Level group mask. */ -#define NVM_FUSES_BODLVL_gp 0 /* Brown Out Detection Voltage Level group position. */ -#define NVM_FUSES_BODLVL0_bm (1<<0) /* Brown Out Detection Voltage Level bit 0 mask. */ -#define NVM_FUSES_BODLVL0_bp 0 /* Brown Out Detection Voltage Level bit 0 position. */ -#define NVM_FUSES_BODLVL1_bm (1<<1) /* Brown Out Detection Voltage Level bit 1 mask. */ -#define NVM_FUSES_BODLVL1_bp 1 /* Brown Out Detection Voltage Level bit 1 position. */ -#define NVM_FUSES_BODLVL2_bm (1<<2) /* Brown Out Detection Voltage Level bit 2 mask. */ -#define NVM_FUSES_BODLVL2_bp 2 /* Brown Out Detection Voltage Level bit 2 position. */ - - -/* AC - Analog Comparator */ -/* AC.AC0CTRL bit masks and bit positions */ -#define AC_INTMODE_gm 0xC0 /* Interrupt Mode group mask. */ -#define AC_INTMODE_gp 6 /* Interrupt Mode group position. */ -#define AC_INTMODE0_bm (1<<6) /* Interrupt Mode bit 0 mask. */ -#define AC_INTMODE0_bp 6 /* Interrupt Mode bit 0 position. */ -#define AC_INTMODE1_bm (1<<7) /* Interrupt Mode bit 1 mask. */ -#define AC_INTMODE1_bp 7 /* Interrupt Mode bit 1 position. */ - -#define AC_INTLVL_gm 0x30 /* Interrupt Level group mask. */ -#define AC_INTLVL_gp 4 /* Interrupt Level group position. */ -#define AC_INTLVL0_bm (1<<4) /* Interrupt Level bit 0 mask. */ -#define AC_INTLVL0_bp 4 /* Interrupt Level bit 0 position. */ -#define AC_INTLVL1_bm (1<<5) /* Interrupt Level bit 1 mask. */ -#define AC_INTLVL1_bp 5 /* Interrupt Level bit 1 position. */ - -#define AC_HSMODE_bm 0x08 /* High-speed Mode bit mask. */ -#define AC_HSMODE_bp 3 /* High-speed Mode bit position. */ - -#define AC_HYSMODE_gm 0x06 /* Hysteresis Mode group mask. */ -#define AC_HYSMODE_gp 1 /* Hysteresis Mode group position. */ -#define AC_HYSMODE0_bm (1<<1) /* Hysteresis Mode bit 0 mask. */ -#define AC_HYSMODE0_bp 1 /* Hysteresis Mode bit 0 position. */ -#define AC_HYSMODE1_bm (1<<2) /* Hysteresis Mode bit 1 mask. */ -#define AC_HYSMODE1_bp 2 /* Hysteresis Mode bit 1 position. */ - -#define AC_ENABLE_bm 0x01 /* Enable bit mask. */ -#define AC_ENABLE_bp 0 /* Enable bit position. */ - - -/* AC.AC1CTRL bit masks and bit positions */ -/* AC_INTMODE_gm Predefined. */ -/* AC_INTMODE_gp Predefined. */ -/* AC_INTMODE0_bm Predefined. */ -/* AC_INTMODE0_bp Predefined. */ -/* AC_INTMODE1_bm Predefined. */ -/* AC_INTMODE1_bp Predefined. */ - -/* AC_INTLVL_gm Predefined. */ -/* AC_INTLVL_gp Predefined. */ -/* AC_INTLVL0_bm Predefined. */ -/* AC_INTLVL0_bp Predefined. */ -/* AC_INTLVL1_bm Predefined. */ -/* AC_INTLVL1_bp Predefined. */ - -/* AC_HSMODE_bm Predefined. */ -/* AC_HSMODE_bp Predefined. */ - -/* AC_HYSMODE_gm Predefined. */ -/* AC_HYSMODE_gp Predefined. */ -/* AC_HYSMODE0_bm Predefined. */ -/* AC_HYSMODE0_bp Predefined. */ -/* AC_HYSMODE1_bm Predefined. */ -/* AC_HYSMODE1_bp Predefined. */ - -/* AC_ENABLE_bm Predefined. */ -/* AC_ENABLE_bp Predefined. */ - - -/* AC.AC0MUXCTRL bit masks and bit positions */ -#define AC_MUXPOS_gm 0x38 /* MUX Positive Input group mask. */ -#define AC_MUXPOS_gp 3 /* MUX Positive Input group position. */ -#define AC_MUXPOS0_bm (1<<3) /* MUX Positive Input bit 0 mask. */ -#define AC_MUXPOS0_bp 3 /* MUX Positive Input bit 0 position. */ -#define AC_MUXPOS1_bm (1<<4) /* MUX Positive Input bit 1 mask. */ -#define AC_MUXPOS1_bp 4 /* MUX Positive Input bit 1 position. */ -#define AC_MUXPOS2_bm (1<<5) /* MUX Positive Input bit 2 mask. */ -#define AC_MUXPOS2_bp 5 /* MUX Positive Input bit 2 position. */ - -#define AC_MUXNEG_gm 0x07 /* MUX Negative Input group mask. */ -#define AC_MUXNEG_gp 0 /* MUX Negative Input group position. */ -#define AC_MUXNEG0_bm (1<<0) /* MUX Negative Input bit 0 mask. */ -#define AC_MUXNEG0_bp 0 /* MUX Negative Input bit 0 position. */ -#define AC_MUXNEG1_bm (1<<1) /* MUX Negative Input bit 1 mask. */ -#define AC_MUXNEG1_bp 1 /* MUX Negative Input bit 1 position. */ -#define AC_MUXNEG2_bm (1<<2) /* MUX Negative Input bit 2 mask. */ -#define AC_MUXNEG2_bp 2 /* MUX Negative Input bit 2 position. */ - - -/* AC.AC1MUXCTRL bit masks and bit positions */ -/* AC_MUXPOS_gm Predefined. */ -/* AC_MUXPOS_gp Predefined. */ -/* AC_MUXPOS0_bm Predefined. */ -/* AC_MUXPOS0_bp Predefined. */ -/* AC_MUXPOS1_bm Predefined. */ -/* AC_MUXPOS1_bp Predefined. */ -/* AC_MUXPOS2_bm Predefined. */ -/* AC_MUXPOS2_bp Predefined. */ - -/* AC_MUXNEG_gm Predefined. */ -/* AC_MUXNEG_gp Predefined. */ -/* AC_MUXNEG0_bm Predefined. */ -/* AC_MUXNEG0_bp Predefined. */ -/* AC_MUXNEG1_bm Predefined. */ -/* AC_MUXNEG1_bp Predefined. */ -/* AC_MUXNEG2_bm Predefined. */ -/* AC_MUXNEG2_bp Predefined. */ - - -/* AC.CTRLA bit masks and bit positions */ -#define AC_AC0OUT_bm 0x01 /* Comparator 0 Output Enable bit mask. */ -#define AC_AC0OUT_bp 0 /* Comparator 0 Output Enable bit position. */ - - -/* AC.CTRLB bit masks and bit positions */ -#define AC_SCALEFAC_gm 0x3F /* VCC Voltage Scaler Factor group mask. */ -#define AC_SCALEFAC_gp 0 /* VCC Voltage Scaler Factor group position. */ -#define AC_SCALEFAC0_bm (1<<0) /* VCC Voltage Scaler Factor bit 0 mask. */ -#define AC_SCALEFAC0_bp 0 /* VCC Voltage Scaler Factor bit 0 position. */ -#define AC_SCALEFAC1_bm (1<<1) /* VCC Voltage Scaler Factor bit 1 mask. */ -#define AC_SCALEFAC1_bp 1 /* VCC Voltage Scaler Factor bit 1 position. */ -#define AC_SCALEFAC2_bm (1<<2) /* VCC Voltage Scaler Factor bit 2 mask. */ -#define AC_SCALEFAC2_bp 2 /* VCC Voltage Scaler Factor bit 2 position. */ -#define AC_SCALEFAC3_bm (1<<3) /* VCC Voltage Scaler Factor bit 3 mask. */ -#define AC_SCALEFAC3_bp 3 /* VCC Voltage Scaler Factor bit 3 position. */ -#define AC_SCALEFAC4_bm (1<<4) /* VCC Voltage Scaler Factor bit 4 mask. */ -#define AC_SCALEFAC4_bp 4 /* VCC Voltage Scaler Factor bit 4 position. */ -#define AC_SCALEFAC5_bm (1<<5) /* VCC Voltage Scaler Factor bit 5 mask. */ -#define AC_SCALEFAC5_bp 5 /* VCC Voltage Scaler Factor bit 5 position. */ - - -/* AC.WINCTRL bit masks and bit positions */ -#define AC_WEN_bm 0x10 /* Window Mode Enable bit mask. */ -#define AC_WEN_bp 4 /* Window Mode Enable bit position. */ - -#define AC_WINTMODE_gm 0x0C /* Window Interrupt Mode group mask. */ -#define AC_WINTMODE_gp 2 /* Window Interrupt Mode group position. */ -#define AC_WINTMODE0_bm (1<<2) /* Window Interrupt Mode bit 0 mask. */ -#define AC_WINTMODE0_bp 2 /* Window Interrupt Mode bit 0 position. */ -#define AC_WINTMODE1_bm (1<<3) /* Window Interrupt Mode bit 1 mask. */ -#define AC_WINTMODE1_bp 3 /* Window Interrupt Mode bit 1 position. */ - -#define AC_WINTLVL_gm 0x03 /* Window Interrupt Level group mask. */ -#define AC_WINTLVL_gp 0 /* Window Interrupt Level group position. */ -#define AC_WINTLVL0_bm (1<<0) /* Window Interrupt Level bit 0 mask. */ -#define AC_WINTLVL0_bp 0 /* Window Interrupt Level bit 0 position. */ -#define AC_WINTLVL1_bm (1<<1) /* Window Interrupt Level bit 1 mask. */ -#define AC_WINTLVL1_bp 1 /* Window Interrupt Level bit 1 position. */ - - -/* AC.STATUS bit masks and bit positions */ -#define AC_WSTATE_gm 0xC0 /* Window Mode State group mask. */ -#define AC_WSTATE_gp 6 /* Window Mode State group position. */ -#define AC_WSTATE0_bm (1<<6) /* Window Mode State bit 0 mask. */ -#define AC_WSTATE0_bp 6 /* Window Mode State bit 0 position. */ -#define AC_WSTATE1_bm (1<<7) /* Window Mode State bit 1 mask. */ -#define AC_WSTATE1_bp 7 /* Window Mode State bit 1 position. */ - -#define AC_AC1STATE_bm 0x20 /* Comparator 1 State bit mask. */ -#define AC_AC1STATE_bp 5 /* Comparator 1 State bit position. */ - -#define AC_AC0STATE_bm 0x10 /* Comparator 0 State bit mask. */ -#define AC_AC0STATE_bp 4 /* Comparator 0 State bit position. */ - -#define AC_WIF_bm 0x04 /* Window Mode Interrupt Flag bit mask. */ -#define AC_WIF_bp 2 /* Window Mode Interrupt Flag bit position. */ - -#define AC_AC1IF_bm 0x02 /* Comparator 1 Interrupt Flag bit mask. */ -#define AC_AC1IF_bp 1 /* Comparator 1 Interrupt Flag bit position. */ - -#define AC_AC0IF_bm 0x01 /* Comparator 0 Interrupt Flag bit mask. */ -#define AC_AC0IF_bp 0 /* Comparator 0 Interrupt Flag bit position. */ - - -/* ADC - Analog/Digital Converter */ -/* ADC_CH.CTRL bit masks and bit positions */ -#define ADC_CH_START_bm 0x80 /* Channel Start Conversion bit mask. */ -#define ADC_CH_START_bp 7 /* Channel Start Conversion bit position. */ - -#define ADC_CH_GAINFAC_gm 0x1C /* Gain Factor group mask. */ -#define ADC_CH_GAINFAC_gp 2 /* Gain Factor group position. */ -#define ADC_CH_GAINFAC0_bm (1<<2) /* Gain Factor bit 0 mask. */ -#define ADC_CH_GAINFAC0_bp 2 /* Gain Factor bit 0 position. */ -#define ADC_CH_GAINFAC1_bm (1<<3) /* Gain Factor bit 1 mask. */ -#define ADC_CH_GAINFAC1_bp 3 /* Gain Factor bit 1 position. */ -#define ADC_CH_GAINFAC2_bm (1<<4) /* Gain Factor bit 2 mask. */ -#define ADC_CH_GAINFAC2_bp 4 /* Gain Factor bit 2 position. */ - -#define ADC_CH_INPUTMODE_gm 0x03 /* Input Mode Select group mask. */ -#define ADC_CH_INPUTMODE_gp 0 /* Input Mode Select group position. */ -#define ADC_CH_INPUTMODE0_bm (1<<0) /* Input Mode Select bit 0 mask. */ -#define ADC_CH_INPUTMODE0_bp 0 /* Input Mode Select bit 0 position. */ -#define ADC_CH_INPUTMODE1_bm (1<<1) /* Input Mode Select bit 1 mask. */ -#define ADC_CH_INPUTMODE1_bp 1 /* Input Mode Select bit 1 position. */ - - -/* ADC_CH.MUXCTRL bit masks and bit positions */ -#define ADC_CH_MUXPOS_gm 0x78 /* Positive Input Select group mask. */ -#define ADC_CH_MUXPOS_gp 3 /* Positive Input Select group position. */ -#define ADC_CH_MUXPOS0_bm (1<<3) /* Positive Input Select bit 0 mask. */ -#define ADC_CH_MUXPOS0_bp 3 /* Positive Input Select bit 0 position. */ -#define ADC_CH_MUXPOS1_bm (1<<4) /* Positive Input Select bit 1 mask. */ -#define ADC_CH_MUXPOS1_bp 4 /* Positive Input Select bit 1 position. */ -#define ADC_CH_MUXPOS2_bm (1<<5) /* Positive Input Select bit 2 mask. */ -#define ADC_CH_MUXPOS2_bp 5 /* Positive Input Select bit 2 position. */ -#define ADC_CH_MUXPOS3_bm (1<<6) /* Positive Input Select bit 3 mask. */ -#define ADC_CH_MUXPOS3_bp 6 /* Positive Input Select bit 3 position. */ - -#define ADC_CH_MUXINT_gm 0x78 /* Internal Input Select group mask. */ -#define ADC_CH_MUXINT_gp 3 /* Internal Input Select group position. */ -#define ADC_CH_MUXINT0_bm (1<<3) /* Internal Input Select bit 0 mask. */ -#define ADC_CH_MUXINT0_bp 3 /* Internal Input Select bit 0 position. */ -#define ADC_CH_MUXINT1_bm (1<<4) /* Internal Input Select bit 1 mask. */ -#define ADC_CH_MUXINT1_bp 4 /* Internal Input Select bit 1 position. */ -#define ADC_CH_MUXINT2_bm (1<<5) /* Internal Input Select bit 2 mask. */ -#define ADC_CH_MUXINT2_bp 5 /* Internal Input Select bit 2 position. */ -#define ADC_CH_MUXINT3_bm (1<<6) /* Internal Input Select bit 3 mask. */ -#define ADC_CH_MUXINT3_bp 6 /* Internal Input Select bit 3 position. */ - -#define ADC_CH_MUXNEG_gm 0x03 /* Negative Input Select group mask. */ -#define ADC_CH_MUXNEG_gp 0 /* Negative Input Select group position. */ -#define ADC_CH_MUXNEG0_bm (1<<0) /* Negative Input Select bit 0 mask. */ -#define ADC_CH_MUXNEG0_bp 0 /* Negative Input Select bit 0 position. */ -#define ADC_CH_MUXNEG1_bm (1<<1) /* Negative Input Select bit 1 mask. */ -#define ADC_CH_MUXNEG1_bp 1 /* Negative Input Select bit 1 position. */ - - -/* ADC_CH.INTCTRL bit masks and bit positions */ -#define ADC_CH_INTMODE_gm 0x0C /* Interrupt Mode group mask. */ -#define ADC_CH_INTMODE_gp 2 /* Interrupt Mode group position. */ -#define ADC_CH_INTMODE0_bm (1<<2) /* Interrupt Mode bit 0 mask. */ -#define ADC_CH_INTMODE0_bp 2 /* Interrupt Mode bit 0 position. */ -#define ADC_CH_INTMODE1_bm (1<<3) /* Interrupt Mode bit 1 mask. */ -#define ADC_CH_INTMODE1_bp 3 /* Interrupt Mode bit 1 position. */ - -#define ADC_CH_INTLVL_gm 0x03 /* Interrupt Level group mask. */ -#define ADC_CH_INTLVL_gp 0 /* Interrupt Level group position. */ -#define ADC_CH_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */ -#define ADC_CH_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */ -#define ADC_CH_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ -#define ADC_CH_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */ - - -/* ADC_CH.INTFLAGS bit masks and bit positions */ -#define ADC_CH_CHIF_bm 0x01 /* Channel Interrupt Flag bit mask. */ -#define ADC_CH_CHIF_bp 0 /* Channel Interrupt Flag bit position. */ - - -/* ADC.CTRLA bit masks and bit positions */ -#define ADC_CH0START_bm 0x04 /* Channel 0 Start Conversion bit mask. */ -#define ADC_CH0START_bp 2 /* Channel 0 Start Conversion bit position. */ - -#define ADC_FLUSH_bm 0x02 /* ADC Flush bit mask. */ -#define ADC_FLUSH_bp 1 /* ADC Flush bit position. */ - -#define ADC_ENABLE_bm 0x01 /* Enable ADC bit mask. */ -#define ADC_ENABLE_bp 0 /* Enable ADC bit position. */ - - -/* ADC.CTRLB bit masks and bit positions */ -#define ADC_CURRLIMIT_gm 0x60 /* Current Limitation group mask. */ -#define ADC_CURRLIMIT_gp 5 /* Current Limitation group position. */ -#define ADC_CURRLIMIT0_bm (1<<5) /* Current Limitation bit 0 mask. */ -#define ADC_CURRLIMIT0_bp 5 /* Current Limitation bit 0 position. */ -#define ADC_CURRLIMIT1_bm (1<<6) /* Current Limitation bit 1 mask. */ -#define ADC_CURRLIMIT1_bp 6 /* Current Limitation bit 1 position. */ - -#define ADC_CONMODE_bm 0x10 /* Conversion Mode bit mask. */ -#define ADC_CONMODE_bp 4 /* Conversion Mode bit position. */ - -#define ADC_FREERUN_bm 0x08 /* Free Running Mode Enable bit mask. */ -#define ADC_FREERUN_bp 3 /* Free Running Mode Enable bit position. */ - -#define ADC_RESOLUTION_gm 0x06 /* Result Resolution group mask. */ -#define ADC_RESOLUTION_gp 1 /* Result Resolution group position. */ -#define ADC_RESOLUTION0_bm (1<<1) /* Result Resolution bit 0 mask. */ -#define ADC_RESOLUTION0_bp 1 /* Result Resolution bit 0 position. */ -#define ADC_RESOLUTION1_bm (1<<2) /* Result Resolution bit 1 mask. */ -#define ADC_RESOLUTION1_bp 2 /* Result Resolution bit 1 position. */ - - -/* ADC.REFCTRL bit masks and bit positions */ -#define ADC_REFSEL_gm 0x30 /* Reference Selection group mask. */ -#define ADC_REFSEL_gp 4 /* Reference Selection group position. */ -#define ADC_REFSEL0_bm (1<<4) /* Reference Selection bit 0 mask. */ -#define ADC_REFSEL0_bp 4 /* Reference Selection bit 0 position. */ -#define ADC_REFSEL1_bm (1<<5) /* Reference Selection bit 1 mask. */ -#define ADC_REFSEL1_bp 5 /* Reference Selection bit 1 position. */ - -#define ADC_BANDGAP_bm 0x02 /* Bandgap enable bit mask. */ -#define ADC_BANDGAP_bp 1 /* Bandgap enable bit position. */ - -#define ADC_TEMPREF_bm 0x01 /* Temperature Reference Enable bit mask. */ -#define ADC_TEMPREF_bp 0 /* Temperature Reference Enable bit position. */ - - -/* ADC.EVCTRL bit masks and bit positions */ -#define ADC_SWEEP_gm 0xC0 /* Channel Sweep Selection group mask. */ -#define ADC_SWEEP_gp 6 /* Channel Sweep Selection group position. */ -#define ADC_SWEEP0_bm (1<<6) /* Channel Sweep Selection bit 0 mask. */ -#define ADC_SWEEP0_bp 6 /* Channel Sweep Selection bit 0 position. */ -#define ADC_SWEEP1_bm (1<<7) /* Channel Sweep Selection bit 1 mask. */ -#define ADC_SWEEP1_bp 7 /* Channel Sweep Selection bit 1 position. */ - -#define ADC_EVSEL_gm 0x38 /* Event Input Select group mask. */ -#define ADC_EVSEL_gp 3 /* Event Input Select group position. */ -#define ADC_EVSEL0_bm (1<<3) /* Event Input Select bit 0 mask. */ -#define ADC_EVSEL0_bp 3 /* Event Input Select bit 0 position. */ -#define ADC_EVSEL1_bm (1<<4) /* Event Input Select bit 1 mask. */ -#define ADC_EVSEL1_bp 4 /* Event Input Select bit 1 position. */ -#define ADC_EVSEL2_bm (1<<5) /* Event Input Select bit 2 mask. */ -#define ADC_EVSEL2_bp 5 /* Event Input Select bit 2 position. */ - -#define ADC_EVACT_gm 0x07 /* Event Action Select group mask. */ -#define ADC_EVACT_gp 0 /* Event Action Select group position. */ -#define ADC_EVACT0_bm (1<<0) /* Event Action Select bit 0 mask. */ -#define ADC_EVACT0_bp 0 /* Event Action Select bit 0 position. */ -#define ADC_EVACT1_bm (1<<1) /* Event Action Select bit 1 mask. */ -#define ADC_EVACT1_bp 1 /* Event Action Select bit 1 position. */ -#define ADC_EVACT2_bm (1<<2) /* Event Action Select bit 2 mask. */ -#define ADC_EVACT2_bp 2 /* Event Action Select bit 2 position. */ - - -/* ADC.PRESCALER bit masks and bit positions */ -#define ADC_PRESCALER_gm 0x07 /* Clock Prescaler Selection group mask. */ -#define ADC_PRESCALER_gp 0 /* Clock Prescaler Selection group position. */ -#define ADC_PRESCALER0_bm (1<<0) /* Clock Prescaler Selection bit 0 mask. */ -#define ADC_PRESCALER0_bp 0 /* Clock Prescaler Selection bit 0 position. */ -#define ADC_PRESCALER1_bm (1<<1) /* Clock Prescaler Selection bit 1 mask. */ -#define ADC_PRESCALER1_bp 1 /* Clock Prescaler Selection bit 1 position. */ -#define ADC_PRESCALER2_bm (1<<2) /* Clock Prescaler Selection bit 2 mask. */ -#define ADC_PRESCALER2_bp 2 /* Clock Prescaler Selection bit 2 position. */ - - -/* ADC.INTFLAGS bit masks and bit positions */ -#define ADC_CH0IF_bm 0x01 /* Channel 0 Interrupt Flag bit mask. */ -#define ADC_CH0IF_bp 0 /* Channel 0 Interrupt Flag bit position. */ - - -/* RTC - Real-Time Clounter */ -/* RTC.CTRL bit masks and bit positions */ -#define RTC_PRESCALER_gm 0x07 /* Prescaling Factor group mask. */ -#define RTC_PRESCALER_gp 0 /* Prescaling Factor group position. */ -#define RTC_PRESCALER0_bm (1<<0) /* Prescaling Factor bit 0 mask. */ -#define RTC_PRESCALER0_bp 0 /* Prescaling Factor bit 0 position. */ -#define RTC_PRESCALER1_bm (1<<1) /* Prescaling Factor bit 1 mask. */ -#define RTC_PRESCALER1_bp 1 /* Prescaling Factor bit 1 position. */ -#define RTC_PRESCALER2_bm (1<<2) /* Prescaling Factor bit 2 mask. */ -#define RTC_PRESCALER2_bp 2 /* Prescaling Factor bit 2 position. */ - - -/* RTC.STATUS bit masks and bit positions */ -#define RTC_SYNCBUSY_bm 0x01 /* Synchronization Busy Flag bit mask. */ -#define RTC_SYNCBUSY_bp 0 /* Synchronization Busy Flag bit position. */ - - -/* RTC.INTCTRL bit masks and bit positions */ -#define RTC_COMPINTLVL_gm 0x0C /* Compare Match Interrupt Level group mask. */ -#define RTC_COMPINTLVL_gp 2 /* Compare Match Interrupt Level group position. */ -#define RTC_COMPINTLVL0_bm (1<<2) /* Compare Match Interrupt Level bit 0 mask. */ -#define RTC_COMPINTLVL0_bp 2 /* Compare Match Interrupt Level bit 0 position. */ -#define RTC_COMPINTLVL1_bm (1<<3) /* Compare Match Interrupt Level bit 1 mask. */ -#define RTC_COMPINTLVL1_bp 3 /* Compare Match Interrupt Level bit 1 position. */ - -#define RTC_OVFINTLVL_gm 0x03 /* Overflow Interrupt Level group mask. */ -#define RTC_OVFINTLVL_gp 0 /* Overflow Interrupt Level group position. */ -#define RTC_OVFINTLVL0_bm (1<<0) /* Overflow Interrupt Level bit 0 mask. */ -#define RTC_OVFINTLVL0_bp 0 /* Overflow Interrupt Level bit 0 position. */ -#define RTC_OVFINTLVL1_bm (1<<1) /* Overflow Interrupt Level bit 1 mask. */ -#define RTC_OVFINTLVL1_bp 1 /* Overflow Interrupt Level bit 1 position. */ - - -/* RTC.INTFLAGS bit masks and bit positions */ -#define RTC_COMPIF_bm 0x02 /* Compare Match Interrupt Flag bit mask. */ -#define RTC_COMPIF_bp 1 /* Compare Match Interrupt Flag bit position. */ - -#define RTC_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ -#define RTC_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ - - -/* EBI - External Bus Interface */ -/* EBI_CS.CTRLA bit masks and bit positions */ -#define EBI_CS_ASIZE_gm 0x7C /* Address Size group mask. */ -#define EBI_CS_ASIZE_gp 2 /* Address Size group position. */ -#define EBI_CS_ASIZE0_bm (1<<2) /* Address Size bit 0 mask. */ -#define EBI_CS_ASIZE0_bp 2 /* Address Size bit 0 position. */ -#define EBI_CS_ASIZE1_bm (1<<3) /* Address Size bit 1 mask. */ -#define EBI_CS_ASIZE1_bp 3 /* Address Size bit 1 position. */ -#define EBI_CS_ASIZE2_bm (1<<4) /* Address Size bit 2 mask. */ -#define EBI_CS_ASIZE2_bp 4 /* Address Size bit 2 position. */ -#define EBI_CS_ASIZE3_bm (1<<5) /* Address Size bit 3 mask. */ -#define EBI_CS_ASIZE3_bp 5 /* Address Size bit 3 position. */ -#define EBI_CS_ASIZE4_bm (1<<6) /* Address Size bit 4 mask. */ -#define EBI_CS_ASIZE4_bp 6 /* Address Size bit 4 position. */ - -#define EBI_CS_MODE_gm 0x03 /* Memory Mode group mask. */ -#define EBI_CS_MODE_gp 0 /* Memory Mode group position. */ -#define EBI_CS_MODE0_bm (1<<0) /* Memory Mode bit 0 mask. */ -#define EBI_CS_MODE0_bp 0 /* Memory Mode bit 0 position. */ -#define EBI_CS_MODE1_bm (1<<1) /* Memory Mode bit 1 mask. */ -#define EBI_CS_MODE1_bp 1 /* Memory Mode bit 1 position. */ - - -/* EBI_CS.CTRLB bit masks and bit positions */ -#define EBI_CS_SRWS_gm 0x07 /* SRAM Wait State Cycles group mask. */ -#define EBI_CS_SRWS_gp 0 /* SRAM Wait State Cycles group position. */ -#define EBI_CS_SRWS0_bm (1<<0) /* SRAM Wait State Cycles bit 0 mask. */ -#define EBI_CS_SRWS0_bp 0 /* SRAM Wait State Cycles bit 0 position. */ -#define EBI_CS_SRWS1_bm (1<<1) /* SRAM Wait State Cycles bit 1 mask. */ -#define EBI_CS_SRWS1_bp 1 /* SRAM Wait State Cycles bit 1 position. */ -#define EBI_CS_SRWS2_bm (1<<2) /* SRAM Wait State Cycles bit 2 mask. */ -#define EBI_CS_SRWS2_bp 2 /* SRAM Wait State Cycles bit 2 position. */ - -#define EBI_CS_SDINITDONE_bm 0x80 /* SDRAM Initialization Done bit mask. */ -#define EBI_CS_SDINITDONE_bp 7 /* SDRAM Initialization Done bit position. */ - -#define EBI_CS_SDSREN_bm 0x04 /* SDRAM Self-refresh Enable bit mask. */ -#define EBI_CS_SDSREN_bp 2 /* SDRAM Self-refresh Enable bit position. */ - -#define EBI_CS_SDMODE_gm 0x03 /* SDRAM Mode group mask. */ -#define EBI_CS_SDMODE_gp 0 /* SDRAM Mode group position. */ -#define EBI_CS_SDMODE0_bm (1<<0) /* SDRAM Mode bit 0 mask. */ -#define EBI_CS_SDMODE0_bp 0 /* SDRAM Mode bit 0 position. */ -#define EBI_CS_SDMODE1_bm (1<<1) /* SDRAM Mode bit 1 mask. */ -#define EBI_CS_SDMODE1_bp 1 /* SDRAM Mode bit 1 position. */ - - -/* EBI.CTRL bit masks and bit positions */ -#define EBI_SDDATAW_gm 0xC0 /* SDRAM Data Width Setting group mask. */ -#define EBI_SDDATAW_gp 6 /* SDRAM Data Width Setting group position. */ -#define EBI_SDDATAW0_bm (1<<6) /* SDRAM Data Width Setting bit 0 mask. */ -#define EBI_SDDATAW0_bp 6 /* SDRAM Data Width Setting bit 0 position. */ -#define EBI_SDDATAW1_bm (1<<7) /* SDRAM Data Width Setting bit 1 mask. */ -#define EBI_SDDATAW1_bp 7 /* SDRAM Data Width Setting bit 1 position. */ - -#define EBI_LPCMODE_gm 0x30 /* SRAM LPC Mode group mask. */ -#define EBI_LPCMODE_gp 4 /* SRAM LPC Mode group position. */ -#define EBI_LPCMODE0_bm (1<<4) /* SRAM LPC Mode bit 0 mask. */ -#define EBI_LPCMODE0_bp 4 /* SRAM LPC Mode bit 0 position. */ -#define EBI_LPCMODE1_bm (1<<5) /* SRAM LPC Mode bit 1 mask. */ -#define EBI_LPCMODE1_bp 5 /* SRAM LPC Mode bit 1 position. */ - -#define EBI_SRMODE_gm 0x0C /* SRAM Mode group mask. */ -#define EBI_SRMODE_gp 2 /* SRAM Mode group position. */ -#define EBI_SRMODE0_bm (1<<2) /* SRAM Mode bit 0 mask. */ -#define EBI_SRMODE0_bp 2 /* SRAM Mode bit 0 position. */ -#define EBI_SRMODE1_bm (1<<3) /* SRAM Mode bit 1 mask. */ -#define EBI_SRMODE1_bp 3 /* SRAM Mode bit 1 position. */ - -#define EBI_IFMODE_gm 0x03 /* Interface Mode group mask. */ -#define EBI_IFMODE_gp 0 /* Interface Mode group position. */ -#define EBI_IFMODE0_bm (1<<0) /* Interface Mode bit 0 mask. */ -#define EBI_IFMODE0_bp 0 /* Interface Mode bit 0 position. */ -#define EBI_IFMODE1_bm (1<<1) /* Interface Mode bit 1 mask. */ -#define EBI_IFMODE1_bp 1 /* Interface Mode bit 1 position. */ - - -/* EBI.SDRAMCTRLA bit masks and bit positions */ -#define EBI_SDCAS_bm 0x08 /* SDRAM CAS Latency Setting bit mask. */ -#define EBI_SDCAS_bp 3 /* SDRAM CAS Latency Setting bit position. */ - -#define EBI_SDROW_bm 0x04 /* SDRAM ROW Bits Setting bit mask. */ -#define EBI_SDROW_bp 2 /* SDRAM ROW Bits Setting bit position. */ - -#define EBI_SDCOL_gm 0x03 /* SDRAM Column Bits Setting group mask. */ -#define EBI_SDCOL_gp 0 /* SDRAM Column Bits Setting group position. */ -#define EBI_SDCOL0_bm (1<<0) /* SDRAM Column Bits Setting bit 0 mask. */ -#define EBI_SDCOL0_bp 0 /* SDRAM Column Bits Setting bit 0 position. */ -#define EBI_SDCOL1_bm (1<<1) /* SDRAM Column Bits Setting bit 1 mask. */ -#define EBI_SDCOL1_bp 1 /* SDRAM Column Bits Setting bit 1 position. */ - - -/* EBI.SDRAMCTRLB bit masks and bit positions */ -#define EBI_MRDLY_gm 0xC0 /* SDRAM Mode Register Delay group mask. */ -#define EBI_MRDLY_gp 6 /* SDRAM Mode Register Delay group position. */ -#define EBI_MRDLY0_bm (1<<6) /* SDRAM Mode Register Delay bit 0 mask. */ -#define EBI_MRDLY0_bp 6 /* SDRAM Mode Register Delay bit 0 position. */ -#define EBI_MRDLY1_bm (1<<7) /* SDRAM Mode Register Delay bit 1 mask. */ -#define EBI_MRDLY1_bp 7 /* SDRAM Mode Register Delay bit 1 position. */ - -#define EBI_ROWCYCDLY_gm 0x38 /* SDRAM Row Cycle Delay group mask. */ -#define EBI_ROWCYCDLY_gp 3 /* SDRAM Row Cycle Delay group position. */ -#define EBI_ROWCYCDLY0_bm (1<<3) /* SDRAM Row Cycle Delay bit 0 mask. */ -#define EBI_ROWCYCDLY0_bp 3 /* SDRAM Row Cycle Delay bit 0 position. */ -#define EBI_ROWCYCDLY1_bm (1<<4) /* SDRAM Row Cycle Delay bit 1 mask. */ -#define EBI_ROWCYCDLY1_bp 4 /* SDRAM Row Cycle Delay bit 1 position. */ -#define EBI_ROWCYCDLY2_bm (1<<5) /* SDRAM Row Cycle Delay bit 2 mask. */ -#define EBI_ROWCYCDLY2_bp 5 /* SDRAM Row Cycle Delay bit 2 position. */ - -#define EBI_RPDLY_gm 0x07 /* SDRAM Row-to-Precharge Delay group mask. */ -#define EBI_RPDLY_gp 0 /* SDRAM Row-to-Precharge Delay group position. */ -#define EBI_RPDLY0_bm (1<<0) /* SDRAM Row-to-Precharge Delay bit 0 mask. */ -#define EBI_RPDLY0_bp 0 /* SDRAM Row-to-Precharge Delay bit 0 position. */ -#define EBI_RPDLY1_bm (1<<1) /* SDRAM Row-to-Precharge Delay bit 1 mask. */ -#define EBI_RPDLY1_bp 1 /* SDRAM Row-to-Precharge Delay bit 1 position. */ -#define EBI_RPDLY2_bm (1<<2) /* SDRAM Row-to-Precharge Delay bit 2 mask. */ -#define EBI_RPDLY2_bp 2 /* SDRAM Row-to-Precharge Delay bit 2 position. */ - - -/* EBI.SDRAMCTRLC bit masks and bit positions */ -#define EBI_WRDLY_gm 0xC0 /* SDRAM Write Recovery Delay group mask. */ -#define EBI_WRDLY_gp 6 /* SDRAM Write Recovery Delay group position. */ -#define EBI_WRDLY0_bm (1<<6) /* SDRAM Write Recovery Delay bit 0 mask. */ -#define EBI_WRDLY0_bp 6 /* SDRAM Write Recovery Delay bit 0 position. */ -#define EBI_WRDLY1_bm (1<<7) /* SDRAM Write Recovery Delay bit 1 mask. */ -#define EBI_WRDLY1_bp 7 /* SDRAM Write Recovery Delay bit 1 position. */ - -#define EBI_ESRDLY_gm 0x38 /* SDRAM Exit-Self-refresh-to-Active Delay group mask. */ -#define EBI_ESRDLY_gp 3 /* SDRAM Exit-Self-refresh-to-Active Delay group position. */ -#define EBI_ESRDLY0_bm (1<<3) /* SDRAM Exit-Self-refresh-to-Active Delay bit 0 mask. */ -#define EBI_ESRDLY0_bp 3 /* SDRAM Exit-Self-refresh-to-Active Delay bit 0 position. */ -#define EBI_ESRDLY1_bm (1<<4) /* SDRAM Exit-Self-refresh-to-Active Delay bit 1 mask. */ -#define EBI_ESRDLY1_bp 4 /* SDRAM Exit-Self-refresh-to-Active Delay bit 1 position. */ -#define EBI_ESRDLY2_bm (1<<5) /* SDRAM Exit-Self-refresh-to-Active Delay bit 2 mask. */ -#define EBI_ESRDLY2_bp 5 /* SDRAM Exit-Self-refresh-to-Active Delay bit 2 position. */ - -#define EBI_ROWCOLDLY_gm 0x07 /* SDRAM Row-to-Column Delay group mask. */ -#define EBI_ROWCOLDLY_gp 0 /* SDRAM Row-to-Column Delay group position. */ -#define EBI_ROWCOLDLY0_bm (1<<0) /* SDRAM Row-to-Column Delay bit 0 mask. */ -#define EBI_ROWCOLDLY0_bp 0 /* SDRAM Row-to-Column Delay bit 0 position. */ -#define EBI_ROWCOLDLY1_bm (1<<1) /* SDRAM Row-to-Column Delay bit 1 mask. */ -#define EBI_ROWCOLDLY1_bp 1 /* SDRAM Row-to-Column Delay bit 1 position. */ -#define EBI_ROWCOLDLY2_bm (1<<2) /* SDRAM Row-to-Column Delay bit 2 mask. */ -#define EBI_ROWCOLDLY2_bp 2 /* SDRAM Row-to-Column Delay bit 2 position. */ - - -/* TWI - Two-Wire Interface */ -/* TWI_MASTER.CTRLA bit masks and bit positions */ -#define TWI_MASTER_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ -#define TWI_MASTER_INTLVL_gp 6 /* Interrupt Level group position. */ -#define TWI_MASTER_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ -#define TWI_MASTER_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ -#define TWI_MASTER_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ -#define TWI_MASTER_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ - -#define TWI_MASTER_RIEN_bm 0x20 /* Read Interrupt Enable bit mask. */ -#define TWI_MASTER_RIEN_bp 5 /* Read Interrupt Enable bit position. */ - -#define TWI_MASTER_WIEN_bm 0x10 /* Write Interrupt Enable bit mask. */ -#define TWI_MASTER_WIEN_bp 4 /* Write Interrupt Enable bit position. */ - -#define TWI_MASTER_ENABLE_bm 0x08 /* Enable TWI Master bit mask. */ -#define TWI_MASTER_ENABLE_bp 3 /* Enable TWI Master bit position. */ - - -/* TWI_MASTER.CTRLB bit masks and bit positions */ -#define TWI_MASTER_TIMEOUT_gm 0x0C /* Inactive Bus Timeout group mask. */ -#define TWI_MASTER_TIMEOUT_gp 2 /* Inactive Bus Timeout group position. */ -#define TWI_MASTER_TIMEOUT0_bm (1<<2) /* Inactive Bus Timeout bit 0 mask. */ -#define TWI_MASTER_TIMEOUT0_bp 2 /* Inactive Bus Timeout bit 0 position. */ -#define TWI_MASTER_TIMEOUT1_bm (1<<3) /* Inactive Bus Timeout bit 1 mask. */ -#define TWI_MASTER_TIMEOUT1_bp 3 /* Inactive Bus Timeout bit 1 position. */ - -#define TWI_MASTER_QCEN_bm 0x02 /* Quick Command Enable bit mask. */ -#define TWI_MASTER_QCEN_bp 1 /* Quick Command Enable bit position. */ - -#define TWI_MASTER_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ -#define TWI_MASTER_SMEN_bp 0 /* Smart Mode Enable bit position. */ - - -/* TWI_MASTER.CTRLC bit masks and bit positions */ -#define TWI_MASTER_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ -#define TWI_MASTER_ACKACT_bp 2 /* Acknowledge Action bit position. */ - -#define TWI_MASTER_CMD_gm 0x03 /* Command group mask. */ -#define TWI_MASTER_CMD_gp 0 /* Command group position. */ -#define TWI_MASTER_CMD0_bm (1<<0) /* Command bit 0 mask. */ -#define TWI_MASTER_CMD0_bp 0 /* Command bit 0 position. */ -#define TWI_MASTER_CMD1_bm (1<<1) /* Command bit 1 mask. */ -#define TWI_MASTER_CMD1_bp 1 /* Command bit 1 position. */ - - -/* TWI_MASTER.STATUS bit masks and bit positions */ -#define TWI_MASTER_RIF_bm 0x80 /* Read Interrupt Flag bit mask. */ -#define TWI_MASTER_RIF_bp 7 /* Read Interrupt Flag bit position. */ - -#define TWI_MASTER_WIF_bm 0x40 /* Write Interrupt Flag bit mask. */ -#define TWI_MASTER_WIF_bp 6 /* Write Interrupt Flag bit position. */ - -#define TWI_MASTER_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ -#define TWI_MASTER_CLKHOLD_bp 5 /* Clock Hold bit position. */ - -#define TWI_MASTER_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ -#define TWI_MASTER_RXACK_bp 4 /* Received Acknowledge bit position. */ - -#define TWI_MASTER_ARBLOST_bm 0x08 /* Arbitration Lost bit mask. */ -#define TWI_MASTER_ARBLOST_bp 3 /* Arbitration Lost bit position. */ - -#define TWI_MASTER_BUSERR_bm 0x04 /* Bus Error bit mask. */ -#define TWI_MASTER_BUSERR_bp 2 /* Bus Error bit position. */ - -#define TWI_MASTER_BUSSTATE_gm 0x03 /* Bus State group mask. */ -#define TWI_MASTER_BUSSTATE_gp 0 /* Bus State group position. */ -#define TWI_MASTER_BUSSTATE0_bm (1<<0) /* Bus State bit 0 mask. */ -#define TWI_MASTER_BUSSTATE0_bp 0 /* Bus State bit 0 position. */ -#define TWI_MASTER_BUSSTATE1_bm (1<<1) /* Bus State bit 1 mask. */ -#define TWI_MASTER_BUSSTATE1_bp 1 /* Bus State bit 1 position. */ - - -/* TWI_SLAVE.CTRLA bit masks and bit positions */ -#define TWI_SLAVE_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ -#define TWI_SLAVE_INTLVL_gp 6 /* Interrupt Level group position. */ -#define TWI_SLAVE_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ -#define TWI_SLAVE_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ -#define TWI_SLAVE_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ -#define TWI_SLAVE_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ - -#define TWI_SLAVE_DIEN_bm 0x20 /* Data Interrupt Enable bit mask. */ -#define TWI_SLAVE_DIEN_bp 5 /* Data Interrupt Enable bit position. */ - -#define TWI_SLAVE_APIEN_bm 0x10 /* Address/Stop Interrupt Enable bit mask. */ -#define TWI_SLAVE_APIEN_bp 4 /* Address/Stop Interrupt Enable bit position. */ - -#define TWI_SLAVE_ENABLE_bm 0x08 /* Enable TWI Slave bit mask. */ -#define TWI_SLAVE_ENABLE_bp 3 /* Enable TWI Slave bit position. */ - -#define TWI_SLAVE_PIEN_bm 0x04 /* Stop Interrupt Enable bit mask. */ -#define TWI_SLAVE_PIEN_bp 2 /* Stop Interrupt Enable bit position. */ - -#define TWI_SLAVE_PMEN_bm 0x02 /* Promiscuous Mode Enable bit mask. */ -#define TWI_SLAVE_PMEN_bp 1 /* Promiscuous Mode Enable bit position. */ - -#define TWI_SLAVE_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ -#define TWI_SLAVE_SMEN_bp 0 /* Smart Mode Enable bit position. */ - - -/* TWI_SLAVE.CTRLB bit masks and bit positions */ -#define TWI_SLAVE_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ -#define TWI_SLAVE_ACKACT_bp 2 /* Acknowledge Action bit position. */ - -#define TWI_SLAVE_CMD_gm 0x03 /* Command group mask. */ -#define TWI_SLAVE_CMD_gp 0 /* Command group position. */ -#define TWI_SLAVE_CMD0_bm (1<<0) /* Command bit 0 mask. */ -#define TWI_SLAVE_CMD0_bp 0 /* Command bit 0 position. */ -#define TWI_SLAVE_CMD1_bm (1<<1) /* Command bit 1 mask. */ -#define TWI_SLAVE_CMD1_bp 1 /* Command bit 1 position. */ - - -/* TWI_SLAVE.STATUS bit masks and bit positions */ -#define TWI_SLAVE_DIF_bm 0x80 /* Data Interrupt Flag bit mask. */ -#define TWI_SLAVE_DIF_bp 7 /* Data Interrupt Flag bit position. */ - -#define TWI_SLAVE_APIF_bm 0x40 /* Address/Stop Interrupt Flag bit mask. */ -#define TWI_SLAVE_APIF_bp 6 /* Address/Stop Interrupt Flag bit position. */ - -#define TWI_SLAVE_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ -#define TWI_SLAVE_CLKHOLD_bp 5 /* Clock Hold bit position. */ - -#define TWI_SLAVE_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ -#define TWI_SLAVE_RXACK_bp 4 /* Received Acknowledge bit position. */ - -#define TWI_SLAVE_COLL_bm 0x08 /* Collision bit mask. */ -#define TWI_SLAVE_COLL_bp 3 /* Collision bit position. */ - -#define TWI_SLAVE_BUSERR_bm 0x04 /* Bus Error bit mask. */ -#define TWI_SLAVE_BUSERR_bp 2 /* Bus Error bit position. */ - -#define TWI_SLAVE_DIR_bm 0x02 /* Read/Write Direction bit mask. */ -#define TWI_SLAVE_DIR_bp 1 /* Read/Write Direction bit position. */ - -#define TWI_SLAVE_AP_bm 0x01 /* Slave Address or Stop bit mask. */ -#define TWI_SLAVE_AP_bp 0 /* Slave Address or Stop bit position. */ - - -/* TWI_SLAVE.ADDRMASK bit masks and bit positions */ -#define TWI_SLAVE_ADDRMASK_gm 0xFE /* Address Mask group mask. */ -#define TWI_SLAVE_ADDRMASK_gp 1 /* Address Mask group position. */ -#define TWI_SLAVE_ADDRMASK0_bm (1<<1) /* Address Mask bit 0 mask. */ -#define TWI_SLAVE_ADDRMASK0_bp 1 /* Address Mask bit 0 position. */ -#define TWI_SLAVE_ADDRMASK1_bm (1<<2) /* Address Mask bit 1 mask. */ -#define TWI_SLAVE_ADDRMASK1_bp 2 /* Address Mask bit 1 position. */ -#define TWI_SLAVE_ADDRMASK2_bm (1<<3) /* Address Mask bit 2 mask. */ -#define TWI_SLAVE_ADDRMASK2_bp 3 /* Address Mask bit 2 position. */ -#define TWI_SLAVE_ADDRMASK3_bm (1<<4) /* Address Mask bit 3 mask. */ -#define TWI_SLAVE_ADDRMASK3_bp 4 /* Address Mask bit 3 position. */ -#define TWI_SLAVE_ADDRMASK4_bm (1<<5) /* Address Mask bit 4 mask. */ -#define TWI_SLAVE_ADDRMASK4_bp 5 /* Address Mask bit 4 position. */ -#define TWI_SLAVE_ADDRMASK5_bm (1<<6) /* Address Mask bit 5 mask. */ -#define TWI_SLAVE_ADDRMASK5_bp 6 /* Address Mask bit 5 position. */ -#define TWI_SLAVE_ADDRMASK6_bm (1<<7) /* Address Mask bit 6 mask. */ -#define TWI_SLAVE_ADDRMASK6_bp 7 /* Address Mask bit 6 position. */ - -#define TWI_SLAVE_ADDREN_bm 0x01 /* Address Enable bit mask. */ -#define TWI_SLAVE_ADDREN_bp 0 /* Address Enable bit position. */ - - -/* TWI.CTRL bit masks and bit positions */ -#define TWI_SDAHOLD_bm 0x02 /* SDA Hold Time Enable bit mask. */ -#define TWI_SDAHOLD_bp 1 /* SDA Hold Time Enable bit position. */ - -#define TWI_EDIEN_bm 0x01 /* External Driver Interface Enable bit mask. */ -#define TWI_EDIEN_bp 0 /* External Driver Interface Enable bit position. */ - - -/* PORT - Port Configuration */ -/* PORTCFG.VPCTRLA bit masks and bit positions */ -#define PORTCFG_VP1MAP_gm 0xF0 /* Virtual Port 1 Mapping group mask. */ -#define PORTCFG_VP1MAP_gp 4 /* Virtual Port 1 Mapping group position. */ -#define PORTCFG_VP1MAP0_bm (1<<4) /* Virtual Port 1 Mapping bit 0 mask. */ -#define PORTCFG_VP1MAP0_bp 4 /* Virtual Port 1 Mapping bit 0 position. */ -#define PORTCFG_VP1MAP1_bm (1<<5) /* Virtual Port 1 Mapping bit 1 mask. */ -#define PORTCFG_VP1MAP1_bp 5 /* Virtual Port 1 Mapping bit 1 position. */ -#define PORTCFG_VP1MAP2_bm (1<<6) /* Virtual Port 1 Mapping bit 2 mask. */ -#define PORTCFG_VP1MAP2_bp 6 /* Virtual Port 1 Mapping bit 2 position. */ -#define PORTCFG_VP1MAP3_bm (1<<7) /* Virtual Port 1 Mapping bit 3 mask. */ -#define PORTCFG_VP1MAP3_bp 7 /* Virtual Port 1 Mapping bit 3 position. */ - -#define PORTCFG_VP0MAP_gm 0x0F /* Virtual Port 0 Mapping group mask. */ -#define PORTCFG_VP0MAP_gp 0 /* Virtual Port 0 Mapping group position. */ -#define PORTCFG_VP0MAP0_bm (1<<0) /* Virtual Port 0 Mapping bit 0 mask. */ -#define PORTCFG_VP0MAP0_bp 0 /* Virtual Port 0 Mapping bit 0 position. */ -#define PORTCFG_VP0MAP1_bm (1<<1) /* Virtual Port 0 Mapping bit 1 mask. */ -#define PORTCFG_VP0MAP1_bp 1 /* Virtual Port 0 Mapping bit 1 position. */ -#define PORTCFG_VP0MAP2_bm (1<<2) /* Virtual Port 0 Mapping bit 2 mask. */ -#define PORTCFG_VP0MAP2_bp 2 /* Virtual Port 0 Mapping bit 2 position. */ -#define PORTCFG_VP0MAP3_bm (1<<3) /* Virtual Port 0 Mapping bit 3 mask. */ -#define PORTCFG_VP0MAP3_bp 3 /* Virtual Port 0 Mapping bit 3 position. */ - - -/* PORTCFG.VPCTRLB bit masks and bit positions */ -#define PORTCFG_VP3MAP_gm 0xF0 /* Virtual Port 3 Mapping group mask. */ -#define PORTCFG_VP3MAP_gp 4 /* Virtual Port 3 Mapping group position. */ -#define PORTCFG_VP3MAP0_bm (1<<4) /* Virtual Port 3 Mapping bit 0 mask. */ -#define PORTCFG_VP3MAP0_bp 4 /* Virtual Port 3 Mapping bit 0 position. */ -#define PORTCFG_VP3MAP1_bm (1<<5) /* Virtual Port 3 Mapping bit 1 mask. */ -#define PORTCFG_VP3MAP1_bp 5 /* Virtual Port 3 Mapping bit 1 position. */ -#define PORTCFG_VP3MAP2_bm (1<<6) /* Virtual Port 3 Mapping bit 2 mask. */ -#define PORTCFG_VP3MAP2_bp 6 /* Virtual Port 3 Mapping bit 2 position. */ -#define PORTCFG_VP3MAP3_bm (1<<7) /* Virtual Port 3 Mapping bit 3 mask. */ -#define PORTCFG_VP3MAP3_bp 7 /* Virtual Port 3 Mapping bit 3 position. */ - -#define PORTCFG_VP2MAP_gm 0x0F /* Virtual Port 2 Mapping group mask. */ -#define PORTCFG_VP2MAP_gp 0 /* Virtual Port 2 Mapping group position. */ -#define PORTCFG_VP2MAP0_bm (1<<0) /* Virtual Port 2 Mapping bit 0 mask. */ -#define PORTCFG_VP2MAP0_bp 0 /* Virtual Port 2 Mapping bit 0 position. */ -#define PORTCFG_VP2MAP1_bm (1<<1) /* Virtual Port 2 Mapping bit 1 mask. */ -#define PORTCFG_VP2MAP1_bp 1 /* Virtual Port 2 Mapping bit 1 position. */ -#define PORTCFG_VP2MAP2_bm (1<<2) /* Virtual Port 2 Mapping bit 2 mask. */ -#define PORTCFG_VP2MAP2_bp 2 /* Virtual Port 2 Mapping bit 2 position. */ -#define PORTCFG_VP2MAP3_bm (1<<3) /* Virtual Port 2 Mapping bit 3 mask. */ -#define PORTCFG_VP2MAP3_bp 3 /* Virtual Port 2 Mapping bit 3 position. */ - - -/* PORTCFG.CLKEVOUT bit masks and bit positions */ -#define PORTCFG_CLKOUT_gm 0x03 /* Clock Output Port group mask. */ -#define PORTCFG_CLKOUT_gp 0 /* Clock Output Port group position. */ -#define PORTCFG_CLKOUT0_bm (1<<0) /* Clock Output Port bit 0 mask. */ -#define PORTCFG_CLKOUT0_bp 0 /* Clock Output Port bit 0 position. */ -#define PORTCFG_CLKOUT1_bm (1<<1) /* Clock Output Port bit 1 mask. */ -#define PORTCFG_CLKOUT1_bp 1 /* Clock Output Port bit 1 position. */ - -#define PORTCFG_EVOUT_gm 0x30 /* Event Output Port group mask. */ -#define PORTCFG_EVOUT_gp 4 /* Event Output Port group position. */ -#define PORTCFG_EVOUT0_bm (1<<4) /* Event Output Port bit 0 mask. */ -#define PORTCFG_EVOUT0_bp 4 /* Event Output Port bit 0 position. */ -#define PORTCFG_EVOUT1_bm (1<<5) /* Event Output Port bit 1 mask. */ -#define PORTCFG_EVOUT1_bp 5 /* Event Output Port bit 1 position. */ - - -/* VPORT.INTFLAGS bit masks and bit positions */ -#define VPORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ -#define VPORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ - -#define VPORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ -#define VPORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ - - -/* PORT.INTCTRL bit masks and bit positions */ -#define PORT_INT1LVL_gm 0x0C /* Port Interrupt 1 Level group mask. */ -#define PORT_INT1LVL_gp 2 /* Port Interrupt 1 Level group position. */ -#define PORT_INT1LVL0_bm (1<<2) /* Port Interrupt 1 Level bit 0 mask. */ -#define PORT_INT1LVL0_bp 2 /* Port Interrupt 1 Level bit 0 position. */ -#define PORT_INT1LVL1_bm (1<<3) /* Port Interrupt 1 Level bit 1 mask. */ -#define PORT_INT1LVL1_bp 3 /* Port Interrupt 1 Level bit 1 position. */ - -#define PORT_INT0LVL_gm 0x03 /* Port Interrupt 0 Level group mask. */ -#define PORT_INT0LVL_gp 0 /* Port Interrupt 0 Level group position. */ -#define PORT_INT0LVL0_bm (1<<0) /* Port Interrupt 0 Level bit 0 mask. */ -#define PORT_INT0LVL0_bp 0 /* Port Interrupt 0 Level bit 0 position. */ -#define PORT_INT0LVL1_bm (1<<1) /* Port Interrupt 0 Level bit 1 mask. */ -#define PORT_INT0LVL1_bp 1 /* Port Interrupt 0 Level bit 1 position. */ - - -/* PORT.INTFLAGS bit masks and bit positions */ -#define PORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ -#define PORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ - -#define PORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ -#define PORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ - - -/* PORT.PIN0CTRL bit masks and bit positions */ -#define PORT_SRLEN_bm 0x80 /* Slew Rate Enable bit mask. */ -#define PORT_SRLEN_bp 7 /* Slew Rate Enable bit position. */ - -#define PORT_INVEN_bm 0x40 /* Inverted I/O Enable bit mask. */ -#define PORT_INVEN_bp 6 /* Inverted I/O Enable bit position. */ - -#define PORT_OPC_gm 0x38 /* Output/Pull Configuration group mask. */ -#define PORT_OPC_gp 3 /* Output/Pull Configuration group position. */ -#define PORT_OPC0_bm (1<<3) /* Output/Pull Configuration bit 0 mask. */ -#define PORT_OPC0_bp 3 /* Output/Pull Configuration bit 0 position. */ -#define PORT_OPC1_bm (1<<4) /* Output/Pull Configuration bit 1 mask. */ -#define PORT_OPC1_bp 4 /* Output/Pull Configuration bit 1 position. */ -#define PORT_OPC2_bm (1<<5) /* Output/Pull Configuration bit 2 mask. */ -#define PORT_OPC2_bp 5 /* Output/Pull Configuration bit 2 position. */ - -#define PORT_ISC_gm 0x07 /* Input/Sense Configuration group mask. */ -#define PORT_ISC_gp 0 /* Input/Sense Configuration group position. */ -#define PORT_ISC0_bm (1<<0) /* Input/Sense Configuration bit 0 mask. */ -#define PORT_ISC0_bp 0 /* Input/Sense Configuration bit 0 position. */ -#define PORT_ISC1_bm (1<<1) /* Input/Sense Configuration bit 1 mask. */ -#define PORT_ISC1_bp 1 /* Input/Sense Configuration bit 1 position. */ -#define PORT_ISC2_bm (1<<2) /* Input/Sense Configuration bit 2 mask. */ -#define PORT_ISC2_bp 2 /* Input/Sense Configuration bit 2 position. */ - - -/* PORT.PIN1CTRL bit masks and bit positions */ -/* PORT_SRLEN_bm Predefined. */ -/* PORT_SRLEN_bp Predefined. */ - -/* PORT_INVEN_bm Predefined. */ -/* PORT_INVEN_bp Predefined. */ - -/* PORT_OPC_gm Predefined. */ -/* PORT_OPC_gp Predefined. */ -/* PORT_OPC0_bm Predefined. */ -/* PORT_OPC0_bp Predefined. */ -/* PORT_OPC1_bm Predefined. */ -/* PORT_OPC1_bp Predefined. */ -/* PORT_OPC2_bm Predefined. */ -/* PORT_OPC2_bp Predefined. */ - -/* PORT_ISC_gm Predefined. */ -/* PORT_ISC_gp Predefined. */ -/* PORT_ISC0_bm Predefined. */ -/* PORT_ISC0_bp Predefined. */ -/* PORT_ISC1_bm Predefined. */ -/* PORT_ISC1_bp Predefined. */ -/* PORT_ISC2_bm Predefined. */ -/* PORT_ISC2_bp Predefined. */ - - -/* PORT.PIN2CTRL bit masks and bit positions */ -/* PORT_SRLEN_bm Predefined. */ -/* PORT_SRLEN_bp Predefined. */ - -/* PORT_INVEN_bm Predefined. */ -/* PORT_INVEN_bp Predefined. */ - -/* PORT_OPC_gm Predefined. */ -/* PORT_OPC_gp Predefined. */ -/* PORT_OPC0_bm Predefined. */ -/* PORT_OPC0_bp Predefined. */ -/* PORT_OPC1_bm Predefined. */ -/* PORT_OPC1_bp Predefined. */ -/* PORT_OPC2_bm Predefined. */ -/* PORT_OPC2_bp Predefined. */ - -/* PORT_ISC_gm Predefined. */ -/* PORT_ISC_gp Predefined. */ -/* PORT_ISC0_bm Predefined. */ -/* PORT_ISC0_bp Predefined. */ -/* PORT_ISC1_bm Predefined. */ -/* PORT_ISC1_bp Predefined. */ -/* PORT_ISC2_bm Predefined. */ -/* PORT_ISC2_bp Predefined. */ - - -/* PORT.PIN3CTRL bit masks and bit positions */ -/* PORT_SRLEN_bm Predefined. */ -/* PORT_SRLEN_bp Predefined. */ - -/* PORT_INVEN_bm Predefined. */ -/* PORT_INVEN_bp Predefined. */ - -/* PORT_OPC_gm Predefined. */ -/* PORT_OPC_gp Predefined. */ -/* PORT_OPC0_bm Predefined. */ -/* PORT_OPC0_bp Predefined. */ -/* PORT_OPC1_bm Predefined. */ -/* PORT_OPC1_bp Predefined. */ -/* PORT_OPC2_bm Predefined. */ -/* PORT_OPC2_bp Predefined. */ - -/* PORT_ISC_gm Predefined. */ -/* PORT_ISC_gp Predefined. */ -/* PORT_ISC0_bm Predefined. */ -/* PORT_ISC0_bp Predefined. */ -/* PORT_ISC1_bm Predefined. */ -/* PORT_ISC1_bp Predefined. */ -/* PORT_ISC2_bm Predefined. */ -/* PORT_ISC2_bp Predefined. */ - - -/* PORT.PIN4CTRL bit masks and bit positions */ -/* PORT_SRLEN_bm Predefined. */ -/* PORT_SRLEN_bp Predefined. */ - -/* PORT_INVEN_bm Predefined. */ -/* PORT_INVEN_bp Predefined. */ - -/* PORT_OPC_gm Predefined. */ -/* PORT_OPC_gp Predefined. */ -/* PORT_OPC0_bm Predefined. */ -/* PORT_OPC0_bp Predefined. */ -/* PORT_OPC1_bm Predefined. */ -/* PORT_OPC1_bp Predefined. */ -/* PORT_OPC2_bm Predefined. */ -/* PORT_OPC2_bp Predefined. */ - -/* PORT_ISC_gm Predefined. */ -/* PORT_ISC_gp Predefined. */ -/* PORT_ISC0_bm Predefined. */ -/* PORT_ISC0_bp Predefined. */ -/* PORT_ISC1_bm Predefined. */ -/* PORT_ISC1_bp Predefined. */ -/* PORT_ISC2_bm Predefined. */ -/* PORT_ISC2_bp Predefined. */ - - -/* PORT.PIN5CTRL bit masks and bit positions */ -/* PORT_SRLEN_bm Predefined. */ -/* PORT_SRLEN_bp Predefined. */ - -/* PORT_INVEN_bm Predefined. */ -/* PORT_INVEN_bp Predefined. */ - -/* PORT_OPC_gm Predefined. */ -/* PORT_OPC_gp Predefined. */ -/* PORT_OPC0_bm Predefined. */ -/* PORT_OPC0_bp Predefined. */ -/* PORT_OPC1_bm Predefined. */ -/* PORT_OPC1_bp Predefined. */ -/* PORT_OPC2_bm Predefined. */ -/* PORT_OPC2_bp Predefined. */ - -/* PORT_ISC_gm Predefined. */ -/* PORT_ISC_gp Predefined. */ -/* PORT_ISC0_bm Predefined. */ -/* PORT_ISC0_bp Predefined. */ -/* PORT_ISC1_bm Predefined. */ -/* PORT_ISC1_bp Predefined. */ -/* PORT_ISC2_bm Predefined. */ -/* PORT_ISC2_bp Predefined. */ - - -/* PORT.PIN6CTRL bit masks and bit positions */ -/* PORT_SRLEN_bm Predefined. */ -/* PORT_SRLEN_bp Predefined. */ - -/* PORT_INVEN_bm Predefined. */ -/* PORT_INVEN_bp Predefined. */ - -/* PORT_OPC_gm Predefined. */ -/* PORT_OPC_gp Predefined. */ -/* PORT_OPC0_bm Predefined. */ -/* PORT_OPC0_bp Predefined. */ -/* PORT_OPC1_bm Predefined. */ -/* PORT_OPC1_bp Predefined. */ -/* PORT_OPC2_bm Predefined. */ -/* PORT_OPC2_bp Predefined. */ - -/* PORT_ISC_gm Predefined. */ -/* PORT_ISC_gp Predefined. */ -/* PORT_ISC0_bm Predefined. */ -/* PORT_ISC0_bp Predefined. */ -/* PORT_ISC1_bm Predefined. */ -/* PORT_ISC1_bp Predefined. */ -/* PORT_ISC2_bm Predefined. */ -/* PORT_ISC2_bp Predefined. */ - - -/* PORT.PIN7CTRL bit masks and bit positions */ -/* PORT_SRLEN_bm Predefined. */ -/* PORT_SRLEN_bp Predefined. */ - -/* PORT_INVEN_bm Predefined. */ -/* PORT_INVEN_bp Predefined. */ - -/* PORT_OPC_gm Predefined. */ -/* PORT_OPC_gp Predefined. */ -/* PORT_OPC0_bm Predefined. */ -/* PORT_OPC0_bp Predefined. */ -/* PORT_OPC1_bm Predefined. */ -/* PORT_OPC1_bp Predefined. */ -/* PORT_OPC2_bm Predefined. */ -/* PORT_OPC2_bp Predefined. */ - -/* PORT_ISC_gm Predefined. */ -/* PORT_ISC_gp Predefined. */ -/* PORT_ISC0_bm Predefined. */ -/* PORT_ISC0_bp Predefined. */ -/* PORT_ISC1_bm Predefined. */ -/* PORT_ISC1_bp Predefined. */ -/* PORT_ISC2_bm Predefined. */ -/* PORT_ISC2_bp Predefined. */ - - -/* TC - 16-bit Timer/Counter With PWM */ -/* TC0.CTRLA bit masks and bit positions */ -#define TC0_CLKSEL_gm 0x0F /* Clock Selection group mask. */ -#define TC0_CLKSEL_gp 0 /* Clock Selection group position. */ -#define TC0_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ -#define TC0_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ -#define TC0_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ -#define TC0_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ -#define TC0_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ -#define TC0_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ -#define TC0_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ -#define TC0_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ - - -/* TC0.CTRLB bit masks and bit positions */ -#define TC0_CCDEN_bm 0x80 /* Compare or Capture D Enable bit mask. */ -#define TC0_CCDEN_bp 7 /* Compare or Capture D Enable bit position. */ - -#define TC0_CCCEN_bm 0x40 /* Compare or Capture C Enable bit mask. */ -#define TC0_CCCEN_bp 6 /* Compare or Capture C Enable bit position. */ - -#define TC0_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ -#define TC0_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ - -#define TC0_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ -#define TC0_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ - -#define TC0_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ -#define TC0_WGMODE_gp 0 /* Waveform generation mode group position. */ -#define TC0_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ -#define TC0_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ -#define TC0_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ -#define TC0_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ -#define TC0_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ -#define TC0_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ - - -/* TC0.CTRLC bit masks and bit positions */ -#define TC0_CMPD_bm 0x08 /* Compare D Output Value bit mask. */ -#define TC0_CMPD_bp 3 /* Compare D Output Value bit position. */ - -#define TC0_CMPC_bm 0x04 /* Compare C Output Value bit mask. */ -#define TC0_CMPC_bp 2 /* Compare C Output Value bit position. */ - -#define TC0_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ -#define TC0_CMPB_bp 1 /* Compare B Output Value bit position. */ - -#define TC0_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ -#define TC0_CMPA_bp 0 /* Compare A Output Value bit position. */ - - -/* TC0.CTRLD bit masks and bit positions */ -#define TC0_EVACT_gm 0xE0 /* Event Action group mask. */ -#define TC0_EVACT_gp 5 /* Event Action group position. */ -#define TC0_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ -#define TC0_EVACT0_bp 5 /* Event Action bit 0 position. */ -#define TC0_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ -#define TC0_EVACT1_bp 6 /* Event Action bit 1 position. */ -#define TC0_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ -#define TC0_EVACT2_bp 7 /* Event Action bit 2 position. */ - -#define TC0_EVDLY_bm 0x10 /* Event Delay bit mask. */ -#define TC0_EVDLY_bp 4 /* Event Delay bit position. */ - -#define TC0_EVSEL_gm 0x0F /* Event Source Select group mask. */ -#define TC0_EVSEL_gp 0 /* Event Source Select group position. */ -#define TC0_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ -#define TC0_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ -#define TC0_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ -#define TC0_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ -#define TC0_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ -#define TC0_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ -#define TC0_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ -#define TC0_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ - - -/* TC0.CTRLE bit masks and bit positions */ -#define TC0_BYTEM_bm 0x01 /* Byte Mode bit mask. */ -#define TC0_BYTEM_bp 0 /* Byte Mode bit position. */ - - -/* TC0.INTCTRLA bit masks and bit positions */ -#define TC0_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ -#define TC0_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ -#define TC0_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ -#define TC0_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ -#define TC0_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ -#define TC0_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ - -#define TC0_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ -#define TC0_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ -#define TC0_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ -#define TC0_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ -#define TC0_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ -#define TC0_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ - - -/* TC0.INTCTRLB bit masks and bit positions */ -#define TC0_CCDINTLVL_gm 0xC0 /* Compare or Capture D Interrupt Level group mask. */ -#define TC0_CCDINTLVL_gp 6 /* Compare or Capture D Interrupt Level group position. */ -#define TC0_CCDINTLVL0_bm (1<<6) /* Compare or Capture D Interrupt Level bit 0 mask. */ -#define TC0_CCDINTLVL0_bp 6 /* Compare or Capture D Interrupt Level bit 0 position. */ -#define TC0_CCDINTLVL1_bm (1<<7) /* Compare or Capture D Interrupt Level bit 1 mask. */ -#define TC0_CCDINTLVL1_bp 7 /* Compare or Capture D Interrupt Level bit 1 position. */ - -#define TC0_CCCINTLVL_gm 0x30 /* Compare or Capture C Interrupt Level group mask. */ -#define TC0_CCCINTLVL_gp 4 /* Compare or Capture C Interrupt Level group position. */ -#define TC0_CCCINTLVL0_bm (1<<4) /* Compare or Capture C Interrupt Level bit 0 mask. */ -#define TC0_CCCINTLVL0_bp 4 /* Compare or Capture C Interrupt Level bit 0 position. */ -#define TC0_CCCINTLVL1_bm (1<<5) /* Compare or Capture C Interrupt Level bit 1 mask. */ -#define TC0_CCCINTLVL1_bp 5 /* Compare or Capture C Interrupt Level bit 1 position. */ - -#define TC0_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ -#define TC0_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ -#define TC0_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ -#define TC0_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ -#define TC0_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ -#define TC0_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ - -#define TC0_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ -#define TC0_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ -#define TC0_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ -#define TC0_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ -#define TC0_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ -#define TC0_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ - - -/* TC0.CTRLFCLR bit masks and bit positions */ -#define TC0_CMD_gm 0x0C /* Command group mask. */ -#define TC0_CMD_gp 2 /* Command group position. */ -#define TC0_CMD0_bm (1<<2) /* Command bit 0 mask. */ -#define TC0_CMD0_bp 2 /* Command bit 0 position. */ -#define TC0_CMD1_bm (1<<3) /* Command bit 1 mask. */ -#define TC0_CMD1_bp 3 /* Command bit 1 position. */ - -#define TC0_LUPD_bm 0x02 /* Lock Update bit mask. */ -#define TC0_LUPD_bp 1 /* Lock Update bit position. */ - -#define TC0_DIR_bm 0x01 /* Direction bit mask. */ -#define TC0_DIR_bp 0 /* Direction bit position. */ - - -/* TC0.CTRLFSET bit masks and bit positions */ -/* TC0_CMD_gm Predefined. */ -/* TC0_CMD_gp Predefined. */ -/* TC0_CMD0_bm Predefined. */ -/* TC0_CMD0_bp Predefined. */ -/* TC0_CMD1_bm Predefined. */ -/* TC0_CMD1_bp Predefined. */ - -/* TC0_LUPD_bm Predefined. */ -/* TC0_LUPD_bp Predefined. */ - -/* TC0_DIR_bm Predefined. */ -/* TC0_DIR_bp Predefined. */ - - -/* TC0.CTRLGCLR bit masks and bit positions */ -#define TC0_CCDBV_bm 0x10 /* Compare or Capture D Buffer Valid bit mask. */ -#define TC0_CCDBV_bp 4 /* Compare or Capture D Buffer Valid bit position. */ - -#define TC0_CCCBV_bm 0x08 /* Compare or Capture C Buffer Valid bit mask. */ -#define TC0_CCCBV_bp 3 /* Compare or Capture C Buffer Valid bit position. */ - -#define TC0_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ -#define TC0_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ - -#define TC0_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ -#define TC0_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ - -#define TC0_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ -#define TC0_PERBV_bp 0 /* Period Buffer Valid bit position. */ - - -/* TC0.CTRLGSET bit masks and bit positions */ -/* TC0_CCDBV_bm Predefined. */ -/* TC0_CCDBV_bp Predefined. */ - -/* TC0_CCCBV_bm Predefined. */ -/* TC0_CCCBV_bp Predefined. */ - -/* TC0_CCBBV_bm Predefined. */ -/* TC0_CCBBV_bp Predefined. */ - -/* TC0_CCABV_bm Predefined. */ -/* TC0_CCABV_bp Predefined. */ - -/* TC0_PERBV_bm Predefined. */ -/* TC0_PERBV_bp Predefined. */ - - -/* TC0.INTFLAGS bit masks and bit positions */ -#define TC0_CCDIF_bm 0x80 /* Compare or Capture D Interrupt Flag bit mask. */ -#define TC0_CCDIF_bp 7 /* Compare or Capture D Interrupt Flag bit position. */ - -#define TC0_CCCIF_bm 0x40 /* Compare or Capture C Interrupt Flag bit mask. */ -#define TC0_CCCIF_bp 6 /* Compare or Capture C Interrupt Flag bit position. */ - -#define TC0_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ -#define TC0_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ - -#define TC0_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ -#define TC0_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ - -#define TC0_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ -#define TC0_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ - -#define TC0_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ -#define TC0_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ - - -/* TC1.CTRLA bit masks and bit positions */ -#define TC1_CLKSEL_gm 0x0F /* Clock Selection group mask. */ -#define TC1_CLKSEL_gp 0 /* Clock Selection group position. */ -#define TC1_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ -#define TC1_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ -#define TC1_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ -#define TC1_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ -#define TC1_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ -#define TC1_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ -#define TC1_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ -#define TC1_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ - - -/* TC1.CTRLB bit masks and bit positions */ -#define TC1_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ -#define TC1_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ - -#define TC1_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ -#define TC1_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ - -#define TC1_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ -#define TC1_WGMODE_gp 0 /* Waveform generation mode group position. */ -#define TC1_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ -#define TC1_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ -#define TC1_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ -#define TC1_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ -#define TC1_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ -#define TC1_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ - - -/* TC1.CTRLC bit masks and bit positions */ -#define TC1_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ -#define TC1_CMPB_bp 1 /* Compare B Output Value bit position. */ - -#define TC1_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ -#define TC1_CMPA_bp 0 /* Compare A Output Value bit position. */ - - -/* TC1.CTRLD bit masks and bit positions */ -#define TC1_EVACT_gm 0xE0 /* Event Action group mask. */ -#define TC1_EVACT_gp 5 /* Event Action group position. */ -#define TC1_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ -#define TC1_EVACT0_bp 5 /* Event Action bit 0 position. */ -#define TC1_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ -#define TC1_EVACT1_bp 6 /* Event Action bit 1 position. */ -#define TC1_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ -#define TC1_EVACT2_bp 7 /* Event Action bit 2 position. */ - -#define TC1_EVDLY_bm 0x10 /* Event Delay bit mask. */ -#define TC1_EVDLY_bp 4 /* Event Delay bit position. */ - -#define TC1_EVSEL_gm 0x0F /* Event Source Select group mask. */ -#define TC1_EVSEL_gp 0 /* Event Source Select group position. */ -#define TC1_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ -#define TC1_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ -#define TC1_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ -#define TC1_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ -#define TC1_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ -#define TC1_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ -#define TC1_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ -#define TC1_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ - - -/* TC1.CTRLE bit masks and bit positions */ -#define TC1_BYTEM_bm 0x01 /* Byte Mode bit mask. */ -#define TC1_BYTEM_bp 0 /* Byte Mode bit position. */ - - -/* TC1.INTCTRLA bit masks and bit positions */ -#define TC1_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ -#define TC1_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ -#define TC1_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ -#define TC1_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ -#define TC1_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ -#define TC1_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ - -#define TC1_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ -#define TC1_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ -#define TC1_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ -#define TC1_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ -#define TC1_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ -#define TC1_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ - - -/* TC1.INTCTRLB bit masks and bit positions */ -#define TC1_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ -#define TC1_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ -#define TC1_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ -#define TC1_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ -#define TC1_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ -#define TC1_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ - -#define TC1_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ -#define TC1_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ -#define TC1_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ -#define TC1_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ -#define TC1_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ -#define TC1_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ - - -/* TC1.CTRLFCLR bit masks and bit positions */ -#define TC1_CMD_gm 0x0C /* Command group mask. */ -#define TC1_CMD_gp 2 /* Command group position. */ -#define TC1_CMD0_bm (1<<2) /* Command bit 0 mask. */ -#define TC1_CMD0_bp 2 /* Command bit 0 position. */ -#define TC1_CMD1_bm (1<<3) /* Command bit 1 mask. */ -#define TC1_CMD1_bp 3 /* Command bit 1 position. */ - -#define TC1_LUPD_bm 0x02 /* Lock Update bit mask. */ -#define TC1_LUPD_bp 1 /* Lock Update bit position. */ - -#define TC1_DIR_bm 0x01 /* Direction bit mask. */ -#define TC1_DIR_bp 0 /* Direction bit position. */ - - -/* TC1.CTRLFSET bit masks and bit positions */ -/* TC1_CMD_gm Predefined. */ -/* TC1_CMD_gp Predefined. */ -/* TC1_CMD0_bm Predefined. */ -/* TC1_CMD0_bp Predefined. */ -/* TC1_CMD1_bm Predefined. */ -/* TC1_CMD1_bp Predefined. */ - -/* TC1_LUPD_bm Predefined. */ -/* TC1_LUPD_bp Predefined. */ - -/* TC1_DIR_bm Predefined. */ -/* TC1_DIR_bp Predefined. */ - - -/* TC1.CTRLGCLR bit masks and bit positions */ -#define TC1_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ -#define TC1_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ - -#define TC1_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ -#define TC1_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ - -#define TC1_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ -#define TC1_PERBV_bp 0 /* Period Buffer Valid bit position. */ - - -/* TC1.CTRLGSET bit masks and bit positions */ -/* TC1_CCBBV_bm Predefined. */ -/* TC1_CCBBV_bp Predefined. */ - -/* TC1_CCABV_bm Predefined. */ -/* TC1_CCABV_bp Predefined. */ - -/* TC1_PERBV_bm Predefined. */ -/* TC1_PERBV_bp Predefined. */ - - -/* TC1.INTFLAGS bit masks and bit positions */ -#define TC1_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ -#define TC1_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ - -#define TC1_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ -#define TC1_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ - -#define TC1_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ -#define TC1_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ - -#define TC1_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ -#define TC1_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ - - -/* AWEX.CTRL bit masks and bit positions */ -#define AWEX_PGM_bm 0x20 /* Pattern Generation Mode bit mask. */ -#define AWEX_PGM_bp 5 /* Pattern Generation Mode bit position. */ - -#define AWEX_CWCM_bm 0x10 /* Common Waveform Channel Mode bit mask. */ -#define AWEX_CWCM_bp 4 /* Common Waveform Channel Mode bit position. */ - -#define AWEX_DTICCDEN_bm 0x08 /* Dead Time Insertion Compare Channel D Enable bit mask. */ -#define AWEX_DTICCDEN_bp 3 /* Dead Time Insertion Compare Channel D Enable bit position. */ - -#define AWEX_DTICCCEN_bm 0x04 /* Dead Time Insertion Compare Channel C Enable bit mask. */ -#define AWEX_DTICCCEN_bp 2 /* Dead Time Insertion Compare Channel C Enable bit position. */ - -#define AWEX_DTICCBEN_bm 0x02 /* Dead Time Insertion Compare Channel B Enable bit mask. */ -#define AWEX_DTICCBEN_bp 1 /* Dead Time Insertion Compare Channel B Enable bit position. */ - -#define AWEX_DTICCAEN_bm 0x01 /* Dead Time Insertion Compare Channel A Enable bit mask. */ -#define AWEX_DTICCAEN_bp 0 /* Dead Time Insertion Compare Channel A Enable bit position. */ - - -/* AWEX.FDCTRL bit masks and bit positions */ -#define AWEX_FDDBD_bm 0x10 /* Fault Detect on Disable Break Disable bit mask. */ -#define AWEX_FDDBD_bp 4 /* Fault Detect on Disable Break Disable bit position. */ - -#define AWEX_FDMODE_bm 0x04 /* Fault Detect Mode bit mask. */ -#define AWEX_FDMODE_bp 2 /* Fault Detect Mode bit position. */ - -#define AWEX_FDACT_gm 0x03 /* Fault Detect Action group mask. */ -#define AWEX_FDACT_gp 0 /* Fault Detect Action group position. */ -#define AWEX_FDACT0_bm (1<<0) /* Fault Detect Action bit 0 mask. */ -#define AWEX_FDACT0_bp 0 /* Fault Detect Action bit 0 position. */ -#define AWEX_FDACT1_bm (1<<1) /* Fault Detect Action bit 1 mask. */ -#define AWEX_FDACT1_bp 1 /* Fault Detect Action bit 1 position. */ - - -/* AWEX.STATUS bit masks and bit positions */ -#define AWEX_FDF_bm 0x04 /* Fault Detect Flag bit mask. */ -#define AWEX_FDF_bp 2 /* Fault Detect Flag bit position. */ - -#define AWEX_DTHSBUFV_bm 0x02 /* Dead Time High Side Buffer Valid bit mask. */ -#define AWEX_DTHSBUFV_bp 1 /* Dead Time High Side Buffer Valid bit position. */ - -#define AWEX_DTLSBUFV_bm 0x01 /* Dead Time Low Side Buffer Valid bit mask. */ -#define AWEX_DTLSBUFV_bp 0 /* Dead Time Low Side Buffer Valid bit position. */ - - -/* HIRES.CTRLA bit masks and bit positions */ -#define HIRES_HREN_gm 0x03 /* High Resolution Enable group mask. */ -#define HIRES_HREN_gp 0 /* High Resolution Enable group position. */ -#define HIRES_HREN0_bm (1<<0) /* High Resolution Enable bit 0 mask. */ -#define HIRES_HREN0_bp 0 /* High Resolution Enable bit 0 position. */ -#define HIRES_HREN1_bm (1<<1) /* High Resolution Enable bit 1 mask. */ -#define HIRES_HREN1_bp 1 /* High Resolution Enable bit 1 position. */ - - -/* USART - Universal Asynchronous Receiver-Transmitter */ -/* USART.STATUS bit masks and bit positions */ -#define USART_RXCIF_bm 0x80 /* Receive Interrupt Flag bit mask. */ -#define USART_RXCIF_bp 7 /* Receive Interrupt Flag bit position. */ - -#define USART_TXCIF_bm 0x40 /* Transmit Interrupt Flag bit mask. */ -#define USART_TXCIF_bp 6 /* Transmit Interrupt Flag bit position. */ - -#define USART_DREIF_bm 0x20 /* Data Register Empty Flag bit mask. */ -#define USART_DREIF_bp 5 /* Data Register Empty Flag bit position. */ - -#define USART_FERR_bm 0x10 /* Frame Error bit mask. */ -#define USART_FERR_bp 4 /* Frame Error bit position. */ - -#define USART_BUFOVF_bm 0x08 /* Buffer Overflow bit mask. */ -#define USART_BUFOVF_bp 3 /* Buffer Overflow bit position. */ - -#define USART_PERR_bm 0x04 /* Parity Error bit mask. */ -#define USART_PERR_bp 2 /* Parity Error bit position. */ - -#define USART_RXB8_bm 0x01 /* Receive Bit 8 bit mask. */ -#define USART_RXB8_bp 0 /* Receive Bit 8 bit position. */ - - -/* USART.CTRLA bit masks and bit positions */ -#define USART_RXCINTLVL_gm 0x30 /* Receive Interrupt Level group mask. */ -#define USART_RXCINTLVL_gp 4 /* Receive Interrupt Level group position. */ -#define USART_RXCINTLVL0_bm (1<<4) /* Receive Interrupt Level bit 0 mask. */ -#define USART_RXCINTLVL0_bp 4 /* Receive Interrupt Level bit 0 position. */ -#define USART_RXCINTLVL1_bm (1<<5) /* Receive Interrupt Level bit 1 mask. */ -#define USART_RXCINTLVL1_bp 5 /* Receive Interrupt Level bit 1 position. */ - -#define USART_TXCINTLVL_gm 0x0C /* Transmit Interrupt Level group mask. */ -#define USART_TXCINTLVL_gp 2 /* Transmit Interrupt Level group position. */ -#define USART_TXCINTLVL0_bm (1<<2) /* Transmit Interrupt Level bit 0 mask. */ -#define USART_TXCINTLVL0_bp 2 /* Transmit Interrupt Level bit 0 position. */ -#define USART_TXCINTLVL1_bm (1<<3) /* Transmit Interrupt Level bit 1 mask. */ -#define USART_TXCINTLVL1_bp 3 /* Transmit Interrupt Level bit 1 position. */ - -#define USART_DREINTLVL_gm 0x03 /* Data Register Empty Interrupt Level group mask. */ -#define USART_DREINTLVL_gp 0 /* Data Register Empty Interrupt Level group position. */ -#define USART_DREINTLVL0_bm (1<<0) /* Data Register Empty Interrupt Level bit 0 mask. */ -#define USART_DREINTLVL0_bp 0 /* Data Register Empty Interrupt Level bit 0 position. */ -#define USART_DREINTLVL1_bm (1<<1) /* Data Register Empty Interrupt Level bit 1 mask. */ -#define USART_DREINTLVL1_bp 1 /* Data Register Empty Interrupt Level bit 1 position. */ - - -/* USART.CTRLB bit masks and bit positions */ -#define USART_RXEN_bm 0x10 /* Receiver Enable bit mask. */ -#define USART_RXEN_bp 4 /* Receiver Enable bit position. */ - -#define USART_TXEN_bm 0x08 /* Transmitter Enable bit mask. */ -#define USART_TXEN_bp 3 /* Transmitter Enable bit position. */ - -#define USART_CLK2X_bm 0x04 /* Double transmission speed bit mask. */ -#define USART_CLK2X_bp 2 /* Double transmission speed bit position. */ - -#define USART_MPCM_bm 0x02 /* Multi-processor Communication Mode bit mask. */ -#define USART_MPCM_bp 1 /* Multi-processor Communication Mode bit position. */ - -#define USART_TXB8_bm 0x01 /* Transmit bit 8 bit mask. */ -#define USART_TXB8_bp 0 /* Transmit bit 8 bit position. */ - - -/* USART.CTRLC bit masks and bit positions */ -#define USART_CMODE_gm 0xC0 /* Communication Mode group mask. */ -#define USART_CMODE_gp 6 /* Communication Mode group position. */ -#define USART_CMODE0_bm (1<<6) /* Communication Mode bit 0 mask. */ -#define USART_CMODE0_bp 6 /* Communication Mode bit 0 position. */ -#define USART_CMODE1_bm (1<<7) /* Communication Mode bit 1 mask. */ -#define USART_CMODE1_bp 7 /* Communication Mode bit 1 position. */ - -#define USART_PMODE_gm 0x30 /* Parity Mode group mask. */ -#define USART_PMODE_gp 4 /* Parity Mode group position. */ -#define USART_PMODE0_bm (1<<4) /* Parity Mode bit 0 mask. */ -#define USART_PMODE0_bp 4 /* Parity Mode bit 0 position. */ -#define USART_PMODE1_bm (1<<5) /* Parity Mode bit 1 mask. */ -#define USART_PMODE1_bp 5 /* Parity Mode bit 1 position. */ - -#define USART_SBMODE_bm 0x08 /* Stop Bit Mode bit mask. */ -#define USART_SBMODE_bp 3 /* Stop Bit Mode bit position. */ - -#define USART_CHSIZE_gm 0x07 /* Character Size group mask. */ -#define USART_CHSIZE_gp 0 /* Character Size group position. */ -#define USART_CHSIZE0_bm (1<<0) /* Character Size bit 0 mask. */ -#define USART_CHSIZE0_bp 0 /* Character Size bit 0 position. */ -#define USART_CHSIZE1_bm (1<<1) /* Character Size bit 1 mask. */ -#define USART_CHSIZE1_bp 1 /* Character Size bit 1 position. */ -#define USART_CHSIZE2_bm (1<<2) /* Character Size bit 2 mask. */ -#define USART_CHSIZE2_bp 2 /* Character Size bit 2 position. */ - - -/* USART.BAUDCTRLA bit masks and bit positions */ -#define USART_BSEL_gm 0xFF /* Baud Rate Selection Bits [7:0] group mask. */ -#define USART_BSEL_gp 0 /* Baud Rate Selection Bits [7:0] group position. */ -#define USART_BSEL0_bm (1<<0) /* Baud Rate Selection Bits [7:0] bit 0 mask. */ -#define USART_BSEL0_bp 0 /* Baud Rate Selection Bits [7:0] bit 0 position. */ -#define USART_BSEL1_bm (1<<1) /* Baud Rate Selection Bits [7:0] bit 1 mask. */ -#define USART_BSEL1_bp 1 /* Baud Rate Selection Bits [7:0] bit 1 position. */ -#define USART_BSEL2_bm (1<<2) /* Baud Rate Selection Bits [7:0] bit 2 mask. */ -#define USART_BSEL2_bp 2 /* Baud Rate Selection Bits [7:0] bit 2 position. */ -#define USART_BSEL3_bm (1<<3) /* Baud Rate Selection Bits [7:0] bit 3 mask. */ -#define USART_BSEL3_bp 3 /* Baud Rate Selection Bits [7:0] bit 3 position. */ -#define USART_BSEL4_bm (1<<4) /* Baud Rate Selection Bits [7:0] bit 4 mask. */ -#define USART_BSEL4_bp 4 /* Baud Rate Selection Bits [7:0] bit 4 position. */ -#define USART_BSEL5_bm (1<<5) /* Baud Rate Selection Bits [7:0] bit 5 mask. */ -#define USART_BSEL5_bp 5 /* Baud Rate Selection Bits [7:0] bit 5 position. */ -#define USART_BSEL6_bm (1<<6) /* Baud Rate Selection Bits [7:0] bit 6 mask. */ -#define USART_BSEL6_bp 6 /* Baud Rate Selection Bits [7:0] bit 6 position. */ -#define USART_BSEL7_bm (1<<7) /* Baud Rate Selection Bits [7:0] bit 7 mask. */ -#define USART_BSEL7_bp 7 /* Baud Rate Selection Bits [7:0] bit 7 position. */ - - -/* USART.BAUDCTRLB bit masks and bit positions */ -#define USART_BSCALE_gm 0xF0 /* Baud Rate Scale group mask. */ -#define USART_BSCALE_gp 4 /* Baud Rate Scale group position. */ -#define USART_BSCALE0_bm (1<<4) /* Baud Rate Scale bit 0 mask. */ -#define USART_BSCALE0_bp 4 /* Baud Rate Scale bit 0 position. */ -#define USART_BSCALE1_bm (1<<5) /* Baud Rate Scale bit 1 mask. */ -#define USART_BSCALE1_bp 5 /* Baud Rate Scale bit 1 position. */ -#define USART_BSCALE2_bm (1<<6) /* Baud Rate Scale bit 2 mask. */ -#define USART_BSCALE2_bp 6 /* Baud Rate Scale bit 2 position. */ -#define USART_BSCALE3_bm (1<<7) /* Baud Rate Scale bit 3 mask. */ -#define USART_BSCALE3_bp 7 /* Baud Rate Scale bit 3 position. */ - -/* USART_BSEL_gm Predefined. */ -/* USART_BSEL_gp Predefined. */ -/* USART_BSEL0_bm Predefined. */ -/* USART_BSEL0_bp Predefined. */ -/* USART_BSEL1_bm Predefined. */ -/* USART_BSEL1_bp Predefined. */ -/* USART_BSEL2_bm Predefined. */ -/* USART_BSEL2_bp Predefined. */ -/* USART_BSEL3_bm Predefined. */ -/* USART_BSEL3_bp Predefined. */ - - -/* SPI - Serial Peripheral Interface */ -/* SPI.CTRL bit masks and bit positions */ -#define SPI_CLK2X_bm 0x80 /* Enable Double Speed bit mask. */ -#define SPI_CLK2X_bp 7 /* Enable Double Speed bit position. */ - -#define SPI_ENABLE_bm 0x40 /* Enable Module bit mask. */ -#define SPI_ENABLE_bp 6 /* Enable Module bit position. */ - -#define SPI_DORD_bm 0x20 /* Data Order Setting bit mask. */ -#define SPI_DORD_bp 5 /* Data Order Setting bit position. */ - -#define SPI_MASTER_bm 0x10 /* Master Operation Enable bit mask. */ -#define SPI_MASTER_bp 4 /* Master Operation Enable bit position. */ - -#define SPI_MODE_gm 0x0C /* SPI Mode group mask. */ -#define SPI_MODE_gp 2 /* SPI Mode group position. */ -#define SPI_MODE0_bm (1<<2) /* SPI Mode bit 0 mask. */ -#define SPI_MODE0_bp 2 /* SPI Mode bit 0 position. */ -#define SPI_MODE1_bm (1<<3) /* SPI Mode bit 1 mask. */ -#define SPI_MODE1_bp 3 /* SPI Mode bit 1 position. */ - -#define SPI_PRESCALER_gm 0x03 /* Prescaler group mask. */ -#define SPI_PRESCALER_gp 0 /* Prescaler group position. */ -#define SPI_PRESCALER0_bm (1<<0) /* Prescaler bit 0 mask. */ -#define SPI_PRESCALER0_bp 0 /* Prescaler bit 0 position. */ -#define SPI_PRESCALER1_bm (1<<1) /* Prescaler bit 1 mask. */ -#define SPI_PRESCALER1_bp 1 /* Prescaler bit 1 position. */ - - -/* SPI.INTCTRL bit masks and bit positions */ -#define SPI_INTLVL_gm 0x03 /* Interrupt level group mask. */ -#define SPI_INTLVL_gp 0 /* Interrupt level group position. */ -#define SPI_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */ -#define SPI_INTLVL0_bp 0 /* Interrupt level bit 0 position. */ -#define SPI_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */ -#define SPI_INTLVL1_bp 1 /* Interrupt level bit 1 position. */ - - -/* SPI.STATUS bit masks and bit positions */ -#define SPI_IF_bm 0x80 /* Interrupt Flag bit mask. */ -#define SPI_IF_bp 7 /* Interrupt Flag bit position. */ - -#define SPI_WRCOL_bm 0x40 /* Write Collision bit mask. */ -#define SPI_WRCOL_bp 6 /* Write Collision bit position. */ - - -/* IRCOM - IR Communication Module */ -/* IRCOM.CTRL bit masks and bit positions */ -#define IRCOM_EVSEL_gm 0x0F /* Event Channel Select group mask. */ -#define IRCOM_EVSEL_gp 0 /* Event Channel Select group position. */ -#define IRCOM_EVSEL0_bm (1<<0) /* Event Channel Select bit 0 mask. */ -#define IRCOM_EVSEL0_bp 0 /* Event Channel Select bit 0 position. */ -#define IRCOM_EVSEL1_bm (1<<1) /* Event Channel Select bit 1 mask. */ -#define IRCOM_EVSEL1_bp 1 /* Event Channel Select bit 1 position. */ -#define IRCOM_EVSEL2_bm (1<<2) /* Event Channel Select bit 2 mask. */ -#define IRCOM_EVSEL2_bp 2 /* Event Channel Select bit 2 position. */ -#define IRCOM_EVSEL3_bm (1<<3) /* Event Channel Select bit 3 mask. */ -#define IRCOM_EVSEL3_bp 3 /* Event Channel Select bit 3 position. */ - - - -// Generic Port Pins - -#define PIN0_bm 0x01 -#define PIN0_bp 0 -#define PIN1_bm 0x02 -#define PIN1_bp 1 -#define PIN2_bm 0x04 -#define PIN2_bp 2 -#define PIN3_bm 0x08 -#define PIN3_bp 3 -#define PIN4_bm 0x10 -#define PIN4_bp 4 -#define PIN5_bm 0x20 -#define PIN5_bp 5 -#define PIN6_bm 0x40 -#define PIN6_bp 6 -#define PIN7_bm 0x80 -#define PIN7_bp 7 - - -/* ========== Interrupt Vector Definitions ========== */ -/* Vector 0 is the reset vector */ - -/* OSC interrupt vectors */ -#define OSC_XOSCF_vect_num 1 -#define OSC_XOSCF_vect _VECTOR(1) /* External Oscillator Failure Interrupt (NMI) */ - -/* PORTC interrupt vectors */ -#define PORTC_INT0_vect_num 2 -#define PORTC_INT0_vect _VECTOR(2) /* External Interrupt 0 */ -#define PORTC_INT1_vect_num 3 -#define PORTC_INT1_vect _VECTOR(3) /* External Interrupt 1 */ - -/* PORTR interrupt vectors */ -#define PORTR_INT0_vect_num 4 -#define PORTR_INT0_vect _VECTOR(4) /* External Interrupt 0 */ -#define PORTR_INT1_vect_num 5 -#define PORTR_INT1_vect _VECTOR(5) /* External Interrupt 1 */ - -/* RTC interrupt vectors */ -#define RTC_OVF_vect_num 10 -#define RTC_OVF_vect _VECTOR(10) /* Overflow Interrupt */ -#define RTC_COMP_vect_num 11 -#define RTC_COMP_vect _VECTOR(11) /* Compare Interrupt */ - -/* TWIC interrupt vectors */ -#define TWIC_TWIS_vect_num 12 -#define TWIC_TWIS_vect _VECTOR(12) /* TWI Slave Interrupt */ -#define TWIC_TWIM_vect_num 13 -#define TWIC_TWIM_vect _VECTOR(13) /* TWI Master Interrupt */ - -/* TCC0 interrupt vectors */ -#define TCC0_OVF_vect_num 14 -#define TCC0_OVF_vect _VECTOR(14) /* Overflow Interrupt */ -#define TCC0_ERR_vect_num 15 -#define TCC0_ERR_vect _VECTOR(15) /* Error Interrupt */ -#define TCC0_CCA_vect_num 16 -#define TCC0_CCA_vect _VECTOR(16) /* Compare or Capture A Interrupt */ -#define TCC0_CCB_vect_num 17 -#define TCC0_CCB_vect _VECTOR(17) /* Compare or Capture B Interrupt */ -#define TCC0_CCC_vect_num 18 -#define TCC0_CCC_vect _VECTOR(18) /* Compare or Capture C Interrupt */ -#define TCC0_CCD_vect_num 19 -#define TCC0_CCD_vect _VECTOR(19) /* Compare or Capture D Interrupt */ - -/* TCC1 interrupt vectors */ -#define TCC1_OVF_vect_num 20 -#define TCC1_OVF_vect _VECTOR(20) /* Overflow Interrupt */ -#define TCC1_ERR_vect_num 21 -#define TCC1_ERR_vect _VECTOR(21) /* Error Interrupt */ -#define TCC1_CCA_vect_num 22 -#define TCC1_CCA_vect _VECTOR(22) /* Compare or Capture A Interrupt */ -#define TCC1_CCB_vect_num 23 -#define TCC1_CCB_vect _VECTOR(23) /* Compare or Capture B Interrupt */ - -/* SPIC interrupt vectors */ -#define SPIC_INT_vect_num 24 -#define SPIC_INT_vect _VECTOR(24) /* SPI Interrupt */ - -/* USARTC0 interrupt vectors */ -#define USARTC0_RXC_vect_num 25 -#define USARTC0_RXC_vect _VECTOR(25) /* Reception Complete Interrupt */ -#define USARTC0_DRE_vect_num 26 -#define USARTC0_DRE_vect _VECTOR(26) /* Data Register Empty Interrupt */ -#define USARTC0_TXC_vect_num 27 -#define USARTC0_TXC_vect _VECTOR(27) /* Transmission Complete Interrupt */ - -/* NVM interrupt vectors */ -#define NVM_EE_vect_num 32 -#define NVM_EE_vect _VECTOR(32) /* EE Interrupt */ -#define NVM_SPM_vect_num 33 -#define NVM_SPM_vect _VECTOR(33) /* SPM Interrupt */ - -/* PORTB interrupt vectors */ -#define PORTB_INT0_vect_num 34 -#define PORTB_INT0_vect _VECTOR(34) /* External Interrupt 0 */ -#define PORTB_INT1_vect_num 35 -#define PORTB_INT1_vect _VECTOR(35) /* External Interrupt 1 */ - -/* PORTE interrupt vectors */ -#define PORTE_INT0_vect_num 43 -#define PORTE_INT0_vect _VECTOR(43) /* External Interrupt 0 */ -#define PORTE_INT1_vect_num 44 -#define PORTE_INT1_vect _VECTOR(44) /* External Interrupt 1 */ - -/* TWIE interrupt vectors */ -#define TWIE_TWIS_vect_num 45 -#define TWIE_TWIS_vect _VECTOR(45) /* TWI Slave Interrupt */ -#define TWIE_TWIM_vect_num 46 -#define TWIE_TWIM_vect _VECTOR(46) /* TWI Master Interrupt */ - -/* TCE0 interrupt vectors */ -#define TCE0_OVF_vect_num 47 -#define TCE0_OVF_vect _VECTOR(47) /* Overflow Interrupt */ -#define TCE0_ERR_vect_num 48 -#define TCE0_ERR_vect _VECTOR(48) /* Error Interrupt */ -#define TCE0_CCA_vect_num 49 -#define TCE0_CCA_vect _VECTOR(49) /* Compare or Capture A Interrupt */ -#define TCE0_CCB_vect_num 50 -#define TCE0_CCB_vect _VECTOR(50) /* Compare or Capture B Interrupt */ -#define TCE0_CCC_vect_num 51 -#define TCE0_CCC_vect _VECTOR(51) /* Compare or Capture C Interrupt */ -#define TCE0_CCD_vect_num 52 -#define TCE0_CCD_vect _VECTOR(52) /* Compare or Capture D Interrupt */ - -/* USARTE0 interrupt vectors */ -#define USARTE0_RXC_vect_num 58 -#define USARTE0_RXC_vect _VECTOR(58) /* Reception Complete Interrupt */ -#define USARTE0_DRE_vect_num 59 -#define USARTE0_DRE_vect _VECTOR(59) /* Data Register Empty Interrupt */ -#define USARTE0_TXC_vect_num 60 -#define USARTE0_TXC_vect _VECTOR(60) /* Transmission Complete Interrupt */ - -/* PORTD interrupt vectors */ -#define PORTD_INT0_vect_num 64 -#define PORTD_INT0_vect _VECTOR(64) /* External Interrupt 0 */ -#define PORTD_INT1_vect_num 65 -#define PORTD_INT1_vect _VECTOR(65) /* External Interrupt 1 */ - -/* PORTA interrupt vectors */ -#define PORTA_INT0_vect_num 66 -#define PORTA_INT0_vect _VECTOR(66) /* External Interrupt 0 */ -#define PORTA_INT1_vect_num 67 -#define PORTA_INT1_vect _VECTOR(67) /* External Interrupt 1 */ - -/* ACA interrupt vectors */ -#define ACA_AC0_vect_num 68 -#define ACA_AC0_vect _VECTOR(68) /* AC0 Interrupt */ -#define ACA_AC1_vect_num 69 -#define ACA_AC1_vect _VECTOR(69) /* AC1 Interrupt */ -#define ACA_ACW_vect_num 70 -#define ACA_ACW_vect _VECTOR(70) /* ACW Window Mode Interrupt */ - -/* ADCA interrupt vectors */ -#define ADCA_CH0_vect_num 71 -#define ADCA_CH0_vect _VECTOR(71) /* Interrupt 0 */ - -/* TCD0 interrupt vectors */ -#define TCD0_OVF_vect_num 77 -#define TCD0_OVF_vect _VECTOR(77) /* Overflow Interrupt */ -#define TCD0_ERR_vect_num 78 -#define TCD0_ERR_vect _VECTOR(78) /* Error Interrupt */ -#define TCD0_CCA_vect_num 79 -#define TCD0_CCA_vect _VECTOR(79) /* Compare or Capture A Interrupt */ -#define TCD0_CCB_vect_num 80 -#define TCD0_CCB_vect _VECTOR(80) /* Compare or Capture B Interrupt */ -#define TCD0_CCC_vect_num 81 -#define TCD0_CCC_vect _VECTOR(81) /* Compare or Capture C Interrupt */ -#define TCD0_CCD_vect_num 82 -#define TCD0_CCD_vect _VECTOR(82) /* Compare or Capture D Interrupt */ - -/* SPID interrupt vectors */ -#define SPID_INT_vect_num 87 -#define SPID_INT_vect _VECTOR(87) /* SPI Interrupt */ - -/* USARTD0 interrupt vectors */ -#define USARTD0_RXC_vect_num 88 -#define USARTD0_RXC_vect _VECTOR(88) /* Reception Complete Interrupt */ -#define USARTD0_DRE_vect_num 89 -#define USARTD0_DRE_vect _VECTOR(89) /* Data Register Empty Interrupt */ -#define USARTD0_TXC_vect_num 90 -#define USARTD0_TXC_vect _VECTOR(90) /* Transmission Complete Interrupt */ - -/* PORTF interrupt vectors */ -#define PORTF_INT0_vect_num 104 -#define PORTF_INT0_vect _VECTOR(104) /* External Interrupt 0 */ -#define PORTF_INT1_vect_num 105 -#define PORTF_INT1_vect _VECTOR(105) /* External Interrupt 1 */ - -/* TCF0 interrupt vectors */ -#define TCF0_OVF_vect_num 108 -#define TCF0_OVF_vect _VECTOR(108) /* Overflow Interrupt */ -#define TCF0_ERR_vect_num 109 -#define TCF0_ERR_vect _VECTOR(109) /* Error Interrupt */ -#define TCF0_CCA_vect_num 110 -#define TCF0_CCA_vect _VECTOR(110) /* Compare or Capture A Interrupt */ -#define TCF0_CCB_vect_num 111 -#define TCF0_CCB_vect _VECTOR(111) /* Compare or Capture B Interrupt */ -#define TCF0_CCC_vect_num 112 -#define TCF0_CCC_vect _VECTOR(112) /* Compare or Capture C Interrupt */ -#define TCF0_CCD_vect_num 113 -#define TCF0_CCD_vect _VECTOR(113) /* Compare or Capture D Interrupt */ - - -#define _VECTOR_SIZE 4 /* Size of individual vector. */ -#define _VECTORS_SIZE (114 * _VECTOR_SIZE) - - -/* ========== Constants ========== */ - -#define PROGMEM_START (0x0000) -#define PROGMEM_SIZE (204800) -#define PROGMEM_PAGE_SIZE (512) -#define PROGMEM_END (PROGMEM_START + PROGMEM_SIZE - 1) - -#define APP_SECTION_START (0x0000) -#define APP_SECTION_SIZE (196608) -#define APP_SECTION_PAGE_SIZE (512) -#define APP_SECTION_END (APP_SECTION_START + APP_SECTION_SIZE - 1) - -#define APPTABLE_SECTION_START (0x2E000) -#define APPTABLE_SECTION_SIZE (8192) -#define APPTABLE_SECTION_PAGE_SIZE (512) -#define APPTABLE_SECTION_END (APPTABLE_SECTION_START + APPTABLE_SECTION_SIZE - 1) - -#define BOOT_SECTION_START (0x30000) -#define BOOT_SECTION_SIZE (8192) -#define BOOT_SECTION_PAGE_SIZE (512) -#define BOOT_SECTION_END (BOOT_SECTION_START + BOOT_SECTION_SIZE - 1) - -#define DATAMEM_START (0x0000) -#define DATAMEM_SIZE (24576) -#define DATAMEM_PAGE_SIZE (0) -#define DATAMEM_END (DATAMEM_START + DATAMEM_SIZE - 1) - -#define IO_START (0x0000) -#define IO_SIZE (4096) -#define IO_PAGE_SIZE (0) -#define IO_END (IO_START + IO_SIZE - 1) - -#define MAPPED_EEPROM_START (0x1000) -#define MAPPED_EEPROM_SIZE (2048) -#define MAPPED_EEPROM_PAGE_SIZE (0) -#define MAPPED_EEPROM_END (MAPPED_EEPROM_START + MAPPED_EEPROM_SIZE - 1) - -#define INTERNAL_SRAM_START (0x2000) -#define INTERNAL_SRAM_SIZE (16384) -#define INTERNAL_SRAM_PAGE_SIZE (0) -#define INTERNAL_SRAM_END (INTERNAL_SRAM_START + INTERNAL_SRAM_SIZE - 1) - -#define EEPROM_START (0x0000) -#define EEPROM_SIZE (2048) -#define EEPROM_PAGE_SIZE (32) -#define EEPROM_END (EEPROM_START + EEPROM_SIZE - 1) - -#define FUSE_START (0x0000) -#define FUSE_SIZE (6) -#define FUSE_PAGE_SIZE (0) -#define FUSE_END (FUSE_START + FUSE_SIZE - 1) - -#define LOCKBIT_START (0x0000) -#define LOCKBIT_SIZE (1) -#define LOCKBIT_PAGE_SIZE (0) -#define LOCKBIT_END (LOCKBIT_START + LOCKBIT_SIZE - 1) - -#define SIGNATURES_START (0x0000) -#define SIGNATURES_SIZE (3) -#define SIGNATURES_PAGE_SIZE (0) -#define SIGNATURES_END (SIGNATURES_START + SIGNATURES_SIZE - 1) - -#define USER_SIGNATURES_START (0x0000) -#define USER_SIGNATURES_SIZE (512) -#define USER_SIGNATURES_PAGE_SIZE (0) -#define USER_SIGNATURES_END (USER_SIGNATURES_START + USER_SIGNATURES_SIZE - 1) - -#define PROD_SIGNATURES_START (0x0000) -#define PROD_SIGNATURES_SIZE (52) -#define PROD_SIGNATURES_PAGE_SIZE (0) -#define PROD_SIGNATURES_END (PROD_SIGNATURES_START + PROD_SIGNATURES_SIZE - 1) - -#define FLASHEND PROGMEM_END -#define SPM_PAGESIZE PROGMEM_PAGE_SIZE -#define RAMSTART INTERNAL_SRAM_START -#define RAMSIZE INTERNAL_SRAM_SIZE -#define RAMEND INTERNAL_SRAM_END -#define XRAMSTART EXTERNAL_SRAM_START -#define XRAMSIZE EXTERNAL_SRAM_SIZE -#define XRAMEND INTERNAL_SRAM_END -#define E2END EEPROM_END -#define E2PAGESIZE EEPROM_PAGE_SIZE - - -/* ========== Fuses ========== */ -#define FUSE_MEMORY_SIZE 6 - -/* Fuse Byte 0 */ -#define FUSE_USERID0 (unsigned char)~_BV(0) /* User ID Bit 0 */ -#define FUSE_USERID1 (unsigned char)~_BV(1) /* User ID Bit 1 */ -#define FUSE_USERID2 (unsigned char)~_BV(2) /* User ID Bit 2 */ -#define FUSE_USERID3 (unsigned char)~_BV(3) /* User ID Bit 3 */ -#define FUSE_USERID4 (unsigned char)~_BV(4) /* User ID Bit 4 */ -#define FUSE_USERID5 (unsigned char)~_BV(5) /* User ID Bit 5 */ -#define FUSE_USERID6 (unsigned char)~_BV(6) /* User ID Bit 6 */ -#define FUSE_USERID7 (unsigned char)~_BV(7) /* User ID Bit 7 */ -#define FUSE0_DEFAULT (0xFF) - -/* Fuse Byte 1 */ -#define FUSE_WDP0 (unsigned char)~_BV(0) /* Watchdog Timeout Period Bit 0 */ -#define FUSE_WDP1 (unsigned char)~_BV(1) /* Watchdog Timeout Period Bit 1 */ -#define FUSE_WDP2 (unsigned char)~_BV(2) /* Watchdog Timeout Period Bit 2 */ -#define FUSE_WDP3 (unsigned char)~_BV(3) /* Watchdog Timeout Period Bit 3 */ -#define FUSE_WDWP0 (unsigned char)~_BV(4) /* Watchdog Window Timeout Period Bit 0 */ -#define FUSE_WDWP1 (unsigned char)~_BV(5) /* Watchdog Window Timeout Period Bit 1 */ -#define FUSE_WDWP2 (unsigned char)~_BV(6) /* Watchdog Window Timeout Period Bit 2 */ -#define FUSE_WDWP3 (unsigned char)~_BV(7) /* Watchdog Window Timeout Period Bit 3 */ -#define FUSE1_DEFAULT (0xFF) - -/* Fuse Byte 2 */ -#define FUSE_BODPD0 (unsigned char)~_BV(0) /* BOD Operation in Power-Down Mode Bit 0 */ -#define FUSE_BODPD1 (unsigned char)~_BV(1) /* BOD Operation in Power-Down Mode Bit 1 */ -#define FUSE_BOOTRST (unsigned char)~_BV(6) /* Boot Loader Section Reset Vector */ -#define FUSE_DVSDON (unsigned char)~_BV(7) /* Spike Detector Enable */ -#define FUSE2_DEFAULT (0xFF) - -/* Fuse Byte 3 Reserved */ - -/* Fuse Byte 4 */ -#define FUSE_WDLOCK (unsigned char)~_BV(1) /* Watchdog Timer Lock */ -#define FUSE_SUT0 (unsigned char)~_BV(2) /* Start-up Time Bit 0 */ -#define FUSE_SUT1 (unsigned char)~_BV(3) /* Start-up Time Bit 1 */ -#define FUSE4_DEFAULT (0xFF) - -/* Fuse Byte 5 */ -#define FUSE_BODLVL0 (unsigned char)~_BV(0) /* Brown Out Detection Voltage Level Bit 0 */ -#define FUSE_BODLVL1 (unsigned char)~_BV(1) /* Brown Out Detection Voltage Level Bit 1 */ -#define FUSE_BODLVL2 (unsigned char)~_BV(2) /* Brown Out Detection Voltage Level Bit 2 */ -#define FUSE_EESAVE (unsigned char)~_BV(3) /* Preserve EEPROM Through Chip Erase */ -#define FUSE_BODACT0 (unsigned char)~_BV(4) /* BOD Operation in Active Mode Bit 0 */ -#define FUSE_BODACT1 (unsigned char)~_BV(5) /* BOD Operation in Active Mode Bit 1 */ -#define FUSE5_DEFAULT (0xFF) - - -/* ========== Lock Bits ========== */ -#define __LOCK_BITS_EXIST -#define __BOOT_LOCK_APPLICATION_TABLE_BITS_EXIST -#define __BOOT_LOCK_APPLICATION_BITS_EXIST -#define __BOOT_LOCK_BOOT_BITS_EXIST - - -/* ========== Signature ========== */ -#define SIGNATURE_0 0x1E -#define SIGNATURE_1 0x97 -#define SIGNATURE_2 0x49 - -/* ========== Power Reduction Condition Definitions ========== */ - -/* PR.PRGEN */ -#define __AVR_HAVE_PRGEN (PR_RTC_bm|PR_EVSYS_bm) -#define __AVR_HAVE_PRGEN_RTC -#define __AVR_HAVE_PRGEN_EVSYS - -/* PR.PRPA */ -#define __AVR_HAVE_PRPA (PR_ADC_bm|PR_AC_bm) -#define __AVR_HAVE_PRPA_ADC -#define __AVR_HAVE_PRPA_AC - -/* PR.PRPC */ -#define __AVR_HAVE_PRPC (PR_TWI_bm|PR_USART0_bm|PR_SPI_bm|PR_HIRES_bm|PR_TC1_bm|PR_TC0_bm) -#define __AVR_HAVE_PRPC_TWI -#define __AVR_HAVE_PRPC_USART0 -#define __AVR_HAVE_PRPC_SPI -#define __AVR_HAVE_PRPC_HIRES -#define __AVR_HAVE_PRPC_TC1 -#define __AVR_HAVE_PRPC_TC0 - -/* PR.PRPD */ -#define __AVR_HAVE_PRPD (PR_USART0_bm|PR_SPI_bm|PR_TC0_bm) -#define __AVR_HAVE_PRPD_USART0 -#define __AVR_HAVE_PRPD_SPI -#define __AVR_HAVE_PRPD_TC0 - -/* PR.PRPE */ -#define __AVR_HAVE_PRPE (PR_TWI_bm|PR_USART0_bm|PR_TC0_bm) -#define __AVR_HAVE_PRPE_TWI -#define __AVR_HAVE_PRPE_USART0 -#define __AVR_HAVE_PRPE_TC0 - -/* PR.PRPF */ -#define __AVR_HAVE_PRPF (PR_USART0_bm|PR_TC0_bm) -#define __AVR_HAVE_PRPF_USART0 -#define __AVR_HAVE_PRPF_TC0 - - -#endif /* _AVR_ATxmega192D3_H_ */ - diff --git a/arduino/hardware/tools/avr/avr/include/avr/iox256a3.h b/arduino/hardware/tools/avr/avr/include/avr/iox256a3.h deleted file mode 100644 index 9fd58f7..0000000 --- a/arduino/hardware/tools/avr/avr/include/avr/iox256a3.h +++ /dev/null @@ -1,6987 +0,0 @@ -/* Copyright (c) 2009-2010 Atmel Corporation - All rights reserved. - - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - * Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - * Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in - the documentation and/or other materials provided with the - distribution. - - * Neither the name of the copyright holders nor the names of - contributors may be used to endorse or promote products derived - from this software without specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. */ - -/* $Id: iox256a3.h 2200 2010-12-14 04:24:24Z arcanum $ */ - -/* avr/iox256a3.h - definitions for ATxmega256A3 */ - -/* This file should only be included from , never directly. */ - -#ifndef _AVR_IO_H_ -# error "Include instead of this file." -#endif - -#ifndef _AVR_IOXXX_H_ -# define _AVR_IOXXX_H_ "iox256a3.h" -#else -# error "Attempt to include more than one file." -#endif - - -#ifndef _AVR_ATxmega256A3_H_ -#define _AVR_ATxmega256A3_H_ 1 - - -/* Ungrouped common registers */ -#define GPIOR0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ -#define GPIOR1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ -#define GPIOR2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ -#define GPIOR3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ -#define GPIOR4 _SFR_MEM8(0x0004) /* General Purpose IO Register 4 */ -#define GPIOR5 _SFR_MEM8(0x0005) /* General Purpose IO Register 5 */ -#define GPIOR6 _SFR_MEM8(0x0006) /* General Purpose IO Register 6 */ -#define GPIOR7 _SFR_MEM8(0x0007) /* General Purpose IO Register 7 */ -#define GPIOR8 _SFR_MEM8(0x0008) /* General Purpose IO Register 8 */ -#define GPIOR9 _SFR_MEM8(0x0009) /* General Purpose IO Register 9 */ -#define GPIORA _SFR_MEM8(0x000A) /* General Purpose IO Register 10 */ -#define GPIORB _SFR_MEM8(0x000B) /* General Purpose IO Register 11 */ -#define GPIORC _SFR_MEM8(0x000C) /* General Purpose IO Register 12 */ -#define GPIORD _SFR_MEM8(0x000D) /* General Purpose IO Register 13 */ -#define GPIORE _SFR_MEM8(0x000E) /* General Purpose IO Register 14 */ -#define GPIORF _SFR_MEM8(0x000F) /* General Purpose IO Register 15 */ - -/* Deprecated */ -#define GPIO0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ -#define GPIO1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ -#define GPIO2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ -#define GPIO3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ -#define GPIO4 _SFR_MEM8(0x0004) /* General Purpose IO Register 4 */ -#define GPIO5 _SFR_MEM8(0x0005) /* General Purpose IO Register 5 */ -#define GPIO6 _SFR_MEM8(0x0006) /* General Purpose IO Register 6 */ -#define GPIO7 _SFR_MEM8(0x0007) /* General Purpose IO Register 7 */ -#define GPIO8 _SFR_MEM8(0x0008) /* General Purpose IO Register 8 */ -#define GPIO9 _SFR_MEM8(0x0009) /* General Purpose IO Register 9 */ -#define GPIOA _SFR_MEM8(0x000A) /* General Purpose IO Register 10 */ -#define GPIOB _SFR_MEM8(0x000B) /* General Purpose IO Register 11 */ -#define GPIOC _SFR_MEM8(0x000C) /* General Purpose IO Register 12 */ -#define GPIOD _SFR_MEM8(0x000D) /* General Purpose IO Register 13 */ -#define GPIOE _SFR_MEM8(0x000E) /* General Purpose IO Register 14 */ -#define GPIOF _SFR_MEM8(0x000F) /* General Purpose IO Register 15 */ - -#define CCP _SFR_MEM8(0x0034) /* Configuration Change Protection */ -#define RAMPD _SFR_MEM8(0x0038) /* Ramp D */ -#define RAMPX _SFR_MEM8(0x0039) /* Ramp X */ -#define RAMPY _SFR_MEM8(0x003A) /* Ramp Y */ -#define RAMPZ _SFR_MEM8(0x003B) /* Ramp Z */ -#define EIND _SFR_MEM8(0x003C) /* Extended Indirect Jump */ -#define SPL _SFR_MEM8(0x003D) /* Stack Pointer Low */ -#define SPH _SFR_MEM8(0x003E) /* Stack Pointer High */ -#define SREG _SFR_MEM8(0x003F) /* Status Register */ - - -/* C Language Only */ -#if !defined (__ASSEMBLER__) - -#include - -typedef volatile uint8_t register8_t; -typedef volatile uint16_t register16_t; -typedef volatile uint32_t register32_t; - - -#ifdef _WORDREGISTER -#undef _WORDREGISTER -#endif -#define _WORDREGISTER(regname) \ - __extension__ union \ - { \ - register16_t regname; \ - struct \ - { \ - register8_t regname ## L; \ - register8_t regname ## H; \ - }; \ - } - -#ifdef _DWORDREGISTER -#undef _DWORDREGISTER -#endif -#define _DWORDREGISTER(regname) \ - __extension__ union \ - { \ - register32_t regname; \ - struct \ - { \ - register8_t regname ## 0; \ - register8_t regname ## 1; \ - register8_t regname ## 2; \ - register8_t regname ## 3; \ - }; \ - } - - -/* -========================================================================== -IO Module Structures -========================================================================== -*/ - - -/* --------------------------------------------------------------------------- -XOCD - On-Chip Debug System --------------------------------------------------------------------------- -*/ - -/* On-Chip Debug System */ -typedef struct OCD_struct -{ - register8_t OCDR0; /* OCD Register 0 */ - register8_t OCDR1; /* OCD Register 1 */ -} OCD_t; - - -/* CCP signatures */ -typedef enum CCP_enum -{ - CCP_SPM_gc = (0x9D<<0), /* SPM Instruction Protection */ - CCP_IOREG_gc = (0xD8<<0), /* IO Register Protection */ -} CCP_t; - - -/* --------------------------------------------------------------------------- -CLK - Clock System --------------------------------------------------------------------------- -*/ - -/* Clock System */ -typedef struct CLK_struct -{ - register8_t CTRL; /* Control Register */ - register8_t PSCTRL; /* Prescaler Control Register */ - register8_t LOCK; /* Lock register */ - register8_t RTCCTRL; /* RTC Control Register */ -} CLK_t; - -/* --------------------------------------------------------------------------- -CLK - Clock System --------------------------------------------------------------------------- -*/ - -/* Power Reduction */ -typedef struct PR_struct -{ - register8_t PRGEN; /* General Power Reduction */ - register8_t PRPA; /* Power Reduction Port A */ - register8_t PRPB; /* Power Reduction Port B */ - register8_t PRPC; /* Power Reduction Port C */ - register8_t PRPD; /* Power Reduction Port D */ - register8_t PRPE; /* Power Reduction Port E */ - register8_t PRPF; /* Power Reduction Port F */ -} PR_t; - -/* System Clock Selection */ -typedef enum CLK_SCLKSEL_enum -{ - CLK_SCLKSEL_RC2M_gc = (0x00<<0), /* Internal 2MHz RC Oscillator */ - CLK_SCLKSEL_RC32M_gc = (0x01<<0), /* Internal 32MHz RC Oscillator */ - CLK_SCLKSEL_RC32K_gc = (0x02<<0), /* Internal 32kHz RC Oscillator */ - CLK_SCLKSEL_XOSC_gc = (0x03<<0), /* External Crystal Oscillator or Clock */ - CLK_SCLKSEL_PLL_gc = (0x04<<0), /* Phase Locked Loop */ -} CLK_SCLKSEL_t; - -/* Prescaler A Division Factor */ -typedef enum CLK_PSADIV_enum -{ - CLK_PSADIV_1_gc = (0x00<<2), /* Divide by 1 */ - CLK_PSADIV_2_gc = (0x01<<2), /* Divide by 2 */ - CLK_PSADIV_4_gc = (0x03<<2), /* Divide by 4 */ - CLK_PSADIV_8_gc = (0x05<<2), /* Divide by 8 */ - CLK_PSADIV_16_gc = (0x07<<2), /* Divide by 16 */ - CLK_PSADIV_32_gc = (0x09<<2), /* Divide by 32 */ - CLK_PSADIV_64_gc = (0x0B<<2), /* Divide by 64 */ - CLK_PSADIV_128_gc = (0x0D<<2), /* Divide by 128 */ - CLK_PSADIV_256_gc = (0x0F<<2), /* Divide by 256 */ - CLK_PSADIV_512_gc = (0x11<<2), /* Divide by 512 */ -} CLK_PSADIV_t; - -/* Prescaler B and C Division Factor */ -typedef enum CLK_PSBCDIV_enum -{ - CLK_PSBCDIV_1_1_gc = (0x00<<0), /* Divide B by 1 and C by 1 */ - CLK_PSBCDIV_1_2_gc = (0x01<<0), /* Divide B by 1 and C by 2 */ - CLK_PSBCDIV_4_1_gc = (0x02<<0), /* Divide B by 4 and C by 1 */ - CLK_PSBCDIV_2_2_gc = (0x03<<0), /* Divide B by 2 and C by 2 */ -} CLK_PSBCDIV_t; - -/* RTC Clock Source */ -typedef enum CLK_RTCSRC_enum -{ - CLK_RTCSRC_ULP_gc = (0x00<<1), /* 1kHz from internal 32kHz ULP */ - CLK_RTCSRC_TOSC_gc = (0x01<<1), /* 1kHz from 32kHz crystal oscillator on TOSC */ - CLK_RTCSRC_RCOSC_gc = (0x02<<1), /* 1kHz from internal 32kHz RC oscillator */ - CLK_RTCSRC_TOSC32_gc = (0x05<<1), /* 32kHz from 32kHz crystal oscillator on TOSC */ -} CLK_RTCSRC_t; - - -/* --------------------------------------------------------------------------- -SLEEP - Sleep Controller --------------------------------------------------------------------------- -*/ - -/* Sleep Controller */ -typedef struct SLEEP_struct -{ - register8_t CTRL; /* Control Register */ -} SLEEP_t; - -/* Sleep Mode */ -typedef enum SLEEP_SMODE_enum -{ - SLEEP_SMODE_IDLE_gc = (0x00<<1), /* Idle mode */ - SLEEP_SMODE_PDOWN_gc = (0x02<<1), /* Power-down Mode */ - SLEEP_SMODE_PSAVE_gc = (0x03<<1), /* Power-save Mode */ - SLEEP_SMODE_STDBY_gc = (0x06<<1), /* Standby Mode */ - SLEEP_SMODE_ESTDBY_gc = (0x07<<1), /* Extended Standby Mode */ -} SLEEP_SMODE_t; - - -#define SLEEP_MODE_IDLE (0x00<<1) -#define SLEEP_MODE_PWR_DOWN (0x02<<1) -#define SLEEP_MODE_PWR_SAVE (0x03<<1) -#define SLEEP_MODE_STANDBY (0x06<<1) -#define SLEEP_MODE_EXT_STANDBY (0x07<<1) - - -/* --------------------------------------------------------------------------- -OSC - Oscillator --------------------------------------------------------------------------- -*/ - -/* Oscillator */ -typedef struct OSC_struct -{ - register8_t CTRL; /* Control Register */ - register8_t STATUS; /* Status Register */ - register8_t XOSCCTRL; /* External Oscillator Control Register */ - register8_t XOSCFAIL; /* External Oscillator Failure Detection Register */ - register8_t RC32KCAL; /* 32kHz Internal Oscillator Calibration Register */ - register8_t PLLCTRL; /* PLL Control REgister */ - register8_t DFLLCTRL; /* DFLL Control Register */ -} OSC_t; - -/* Oscillator Frequency Range */ -typedef enum OSC_FRQRANGE_enum -{ - OSC_FRQRANGE_04TO2_gc = (0x00<<6), /* 0.4 - 2 MHz */ - OSC_FRQRANGE_2TO9_gc = (0x01<<6), /* 2 - 9 MHz */ - OSC_FRQRANGE_9TO12_gc = (0x02<<6), /* 9 - 12 MHz */ - OSC_FRQRANGE_12TO16_gc = (0x03<<6), /* 12 - 16 MHz */ -} OSC_FRQRANGE_t; - -/* External Oscillator Selection and Startup Time */ -typedef enum OSC_XOSCSEL_enum -{ - OSC_XOSCSEL_EXTCLK_gc = (0x00<<0), /* External Clock - 6 CLK */ - OSC_XOSCSEL_32KHz_gc = (0x02<<0), /* 32kHz TOSC - 32K CLK */ - OSC_XOSCSEL_XTAL_256CLK_gc = (0x03<<0), /* 0.4-16MHz XTAL - 256 CLK */ - OSC_XOSCSEL_XTAL_1KCLK_gc = (0x07<<0), /* 0.4-16MHz XTAL - 1K CLK */ - OSC_XOSCSEL_XTAL_16KCLK_gc = (0x0B<<0), /* 0.4-16MHz XTAL - 16K CLK */ -} OSC_XOSCSEL_t; - -/* PLL Clock Source */ -typedef enum OSC_PLLSRC_enum -{ - OSC_PLLSRC_RC2M_gc = (0x00<<6), /* Internal 2MHz RC Oscillator */ - OSC_PLLSRC_RC32M_gc = (0x02<<6), /* Internal 32MHz RC Oscillator */ - OSC_PLLSRC_XOSC_gc = (0x03<<6), /* External Oscillator */ -} OSC_PLLSRC_t; - - -/* --------------------------------------------------------------------------- -DFLL - DFLL --------------------------------------------------------------------------- -*/ - -/* DFLL */ -typedef struct DFLL_struct -{ - register8_t CTRL; /* Control Register */ - register8_t reserved_0x01; - register8_t CALA; /* Calibration Register A */ - register8_t CALB; /* Calibration Register B */ - register8_t COMP0; /* Oscillator Compare Register 0 */ - register8_t COMP1; /* Oscillator Compare Register 1 */ - register8_t COMP2; /* Oscillator Compare Register 2 */ - register8_t reserved_0x07; -} DFLL_t; - - -/* --------------------------------------------------------------------------- -RST - Reset --------------------------------------------------------------------------- -*/ - -/* Reset */ -typedef struct RST_struct -{ - register8_t STATUS; /* Status Register */ - register8_t CTRL; /* Control Register */ -} RST_t; - - -/* --------------------------------------------------------------------------- -WDT - Watch-Dog Timer --------------------------------------------------------------------------- -*/ - -/* Watch-Dog Timer */ -typedef struct WDT_struct -{ - register8_t CTRL; /* Control */ - register8_t WINCTRL; /* Windowed Mode Control */ - register8_t STATUS; /* Status */ -} WDT_t; - -/* Period setting */ -typedef enum WDT_PER_enum -{ - WDT_PER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ - WDT_PER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ - WDT_PER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ - WDT_PER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ - WDT_PER_128CLK_gc = (0x04<<2), /* 128 cycles (0.125s @ 3.3V) */ - WDT_PER_256CLK_gc = (0x05<<2), /* 256 cycles (0.25s @ 3.3V) */ - WDT_PER_512CLK_gc = (0x06<<2), /* 512 cycles (0.5s @ 3.3V) */ - WDT_PER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ - WDT_PER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ - WDT_PER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ - WDT_PER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ -} WDT_PER_t; - -/* Closed window period */ -typedef enum WDT_WPER_enum -{ - WDT_WPER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ - WDT_WPER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ - WDT_WPER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ - WDT_WPER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ - WDT_WPER_128CLK_gc = (0x04<<2), /* 128 cycles (0.125s @ 3.3V) */ - WDT_WPER_256CLK_gc = (0x05<<2), /* 256 cycles (0.25s @ 3.3V) */ - WDT_WPER_512CLK_gc = (0x06<<2), /* 512 cycles (0.5s @ 3.3V) */ - WDT_WPER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ - WDT_WPER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ - WDT_WPER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ - WDT_WPER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ -} WDT_WPER_t; - - -/* --------------------------------------------------------------------------- -MCU - MCU Control --------------------------------------------------------------------------- -*/ - -/* MCU Control */ -typedef struct MCU_struct -{ - register8_t DEVID0; /* Device ID byte 0 */ - register8_t DEVID1; /* Device ID byte 1 */ - register8_t DEVID2; /* Device ID byte 2 */ - register8_t REVID; /* Revision ID */ - register8_t JTAGUID; /* JTAG User ID */ - register8_t reserved_0x05; - register8_t MCUCR; /* MCU Control */ - register8_t reserved_0x07; - register8_t EVSYSLOCK; /* Event System Lock */ - register8_t AWEXLOCK; /* AWEX Lock */ - register8_t reserved_0x0A; - register8_t reserved_0x0B; -} MCU_t; - - -/* --------------------------------------------------------------------------- -PMIC - Programmable Multi-level Interrupt Controller --------------------------------------------------------------------------- -*/ - -/* Programmable Multi-level Interrupt Controller */ -typedef struct PMIC_struct -{ - register8_t STATUS; /* Status Register */ - register8_t INTPRI; /* Interrupt Priority */ - register8_t CTRL; /* Control Register */ -} PMIC_t; - - -/* --------------------------------------------------------------------------- -DMA - DMA Controller --------------------------------------------------------------------------- -*/ - -/* DMA Channel */ -typedef struct DMA_CH_struct -{ - register8_t CTRLA; /* Channel Control */ - register8_t CTRLB; /* Channel Control */ - register8_t ADDRCTRL; /* Address Control */ - register8_t TRIGSRC; /* Channel Trigger Source */ - _WORDREGISTER(TRFCNT); /* Channel Block Transfer Count */ - register8_t REPCNT; /* Channel Repeat Count */ - register8_t reserved_0x07; - register8_t SRCADDR0; /* Channel Source Address 0 */ - register8_t SRCADDR1; /* Channel Source Address 1 */ - register8_t SRCADDR2; /* Channel Source Address 2 */ - register8_t reserved_0x0B; - register8_t DESTADDR0; /* Channel Destination Address 0 */ - register8_t DESTADDR1; /* Channel Destination Address 1 */ - register8_t DESTADDR2; /* Channel Destination Address 2 */ - register8_t reserved_0x0F; -} DMA_CH_t; - -/* --------------------------------------------------------------------------- -DMA - DMA Controller --------------------------------------------------------------------------- -*/ - -/* DMA Controller */ -typedef struct DMA_struct -{ - register8_t CTRL; /* Control */ - register8_t reserved_0x01; - register8_t reserved_0x02; - register8_t INTFLAGS; /* Transfer Interrupt Status */ - register8_t STATUS; /* Status */ - register8_t reserved_0x05; - _WORDREGISTER(TEMP); /* Temporary Register For 16/24-bit Access */ - register8_t reserved_0x08; - register8_t reserved_0x09; - register8_t reserved_0x0A; - register8_t reserved_0x0B; - register8_t reserved_0x0C; - register8_t reserved_0x0D; - register8_t reserved_0x0E; - register8_t reserved_0x0F; - DMA_CH_t CH0; /* DMA Channel 0 */ - DMA_CH_t CH1; /* DMA Channel 1 */ - DMA_CH_t CH2; /* DMA Channel 2 */ - DMA_CH_t CH3; /* DMA Channel 3 */ -} DMA_t; - -/* Burst mode */ -typedef enum DMA_CH_BURSTLEN_enum -{ - DMA_CH_BURSTLEN_1BYTE_gc = (0x00<<0), /* 1-byte burst mode */ - DMA_CH_BURSTLEN_2BYTE_gc = (0x01<<0), /* 2-byte burst mode */ - DMA_CH_BURSTLEN_4BYTE_gc = (0x02<<0), /* 4-byte burst mode */ - DMA_CH_BURSTLEN_8BYTE_gc = (0x03<<0), /* 8-byte burst mode */ -} DMA_CH_BURSTLEN_t; - -/* Source address reload mode */ -typedef enum DMA_CH_SRCRELOAD_enum -{ - DMA_CH_SRCRELOAD_NONE_gc = (0x00<<6), /* No reload */ - DMA_CH_SRCRELOAD_BLOCK_gc = (0x01<<6), /* Reload at end of block */ - DMA_CH_SRCRELOAD_BURST_gc = (0x02<<6), /* Reload at end of burst */ - DMA_CH_SRCRELOAD_TRANSACTION_gc = (0x03<<6), /* Reload at end of transaction */ -} DMA_CH_SRCRELOAD_t; - -/* Source addressing mode */ -typedef enum DMA_CH_SRCDIR_enum -{ - DMA_CH_SRCDIR_FIXED_gc = (0x00<<4), /* Fixed */ - DMA_CH_SRCDIR_INC_gc = (0x01<<4), /* Increment */ - DMA_CH_SRCDIR_DEC_gc = (0x02<<4), /* Decrement */ -} DMA_CH_SRCDIR_t; - -/* Destination adress reload mode */ -typedef enum DMA_CH_DESTRELOAD_enum -{ - DMA_CH_DESTRELOAD_NONE_gc = (0x00<<2), /* No reload */ - DMA_CH_DESTRELOAD_BLOCK_gc = (0x01<<2), /* Reload at end of block */ - DMA_CH_DESTRELOAD_BURST_gc = (0x02<<2), /* Reload at end of burst */ - DMA_CH_DESTRELOAD_TRANSACTION_gc = (0x03<<2), /* Reload at end of transaction */ -} DMA_CH_DESTRELOAD_t; - -/* Destination adressing mode */ -typedef enum DMA_CH_DESTDIR_enum -{ - DMA_CH_DESTDIR_FIXED_gc = (0x00<<0), /* Fixed */ - DMA_CH_DESTDIR_INC_gc = (0x01<<0), /* Increment */ - DMA_CH_DESTDIR_DEC_gc = (0x02<<0), /* Decrement */ -} DMA_CH_DESTDIR_t; - -/* Transfer trigger source */ -typedef enum DMA_CH_TRIGSRC_enum -{ - DMA_CH_TRIGSRC_OFF_gc = (0x00<<0), /* Off software triggers only */ - DMA_CH_TRIGSRC_EVSYS_CH0_gc = (0x01<<0), /* Event System Channel 0 */ - DMA_CH_TRIGSRC_EVSYS_CH1_gc = (0x02<<0), /* Event System Channel 1 */ - DMA_CH_TRIGSRC_EVSYS_CH2_gc = (0x03<<0), /* Event System Channel 2 */ - DMA_CH_TRIGSRC_ADCA_CH0_gc = (0x10<<0), /* ADCA Channel 0 */ - DMA_CH_TRIGSRC_ADCA_CH1_gc = (0x11<<0), /* ADCA Channel 1 */ - DMA_CH_TRIGSRC_ADCA_CH2_gc = (0x12<<0), /* ADCA Channel 2 */ - DMA_CH_TRIGSRC_ADCA_CH3_gc = (0x13<<0), /* ADCA Channel 3 */ - DMA_CH_TRIGSRC_ADCA_CH4_gc = (0x14<<0), /* ADCA Channel 0,1,2,3 combined */ - DMA_CH_TRIGSRC_DACA_CH0_gc = (0x15<<0), /* DACA Channel 0 */ - DMA_CH_TRIGSRC_DACA_CH1_gc = (0x16<<0), /* DACA Channel 1 */ - DMA_CH_TRIGSRC_ADCB_CH0_gc = (0x20<<0), /* ADCB Channel 0 */ - DMA_CH_TRIGSRC_ADCB_CH1_gc = (0x21<<0), /* ADCB Channel 1 */ - DMA_CH_TRIGSRC_ADCB_CH2_gc = (0x22<<0), /* ADCB Channel 2 */ - DMA_CH_TRIGSRC_ADCB_CH3_gc = (0x23<<0), /* ADCB Channel 3 */ - DMA_CH_TRIGSRC_ADCB_CH4_gc = (0x24<<0), /* ADCB Channel 0,1,2,3 combined */ - DMA_CH_TRIGSRC_DACB_CH0_gc = (0x25<<0), /* DACB Channel 0 */ - DMA_CH_TRIGSRC_DACB_CH1_gc = (0x26<<0), /* DACB Channel 1 */ - DMA_CH_TRIGSRC_TCC0_OVF_gc = (0x40<<0), /* Timer/Counter C0 Overflow */ - DMA_CH_TRIGSRC_TCC0_ERR_gc = (0x41<<0), /* Timer/Counter C0 Error */ - DMA_CH_TRIGSRC_TCC0_CCA_gc = (0x42<<0), /* Timer/Counter C0 Compare or Capture A */ - DMA_CH_TRIGSRC_TCC0_CCB_gc = (0x43<<0), /* Timer/Counter C0 Compare or Capture B */ - DMA_CH_TRIGSRC_TCC0_CCC_gc = (0x44<<0), /* Timer/Counter C0 Compare or Capture C */ - DMA_CH_TRIGSRC_TCC0_CCD_gc = (0x45<<0), /* Timer/Counter C0 Compare or Capture D */ - DMA_CH_TRIGSRC_TCC1_OVF_gc = (0x46<<0), /* Timer/Counter C1 Overflow */ - DMA_CH_TRIGSRC_TCC1_ERR_gc = (0x47<<0), /* Timer/Counter C1 Error */ - DMA_CH_TRIGSRC_TCC1_CCA_gc = (0x48<<0), /* Timer/Counter C1 Compare or Capture A */ - DMA_CH_TRIGSRC_TCC1_CCB_gc = (0x49<<0), /* Timer/Counter C1 Compare or Capture B */ - DMA_CH_TRIGSRC_SPIC_gc = (0x4A<<0), /* SPI C Transfer Complete */ - DMA_CH_TRIGSRC_USARTC0_RXC_gc = (0x4B<<0), /* USART C0 Receive Complete */ - DMA_CH_TRIGSRC_USARTC0_DRE_gc = (0x4C<<0), /* USART C0 Data Register Empty */ - DMA_CH_TRIGSRC_USARTC1_RXC_gc = (0x4E<<0), /* USART C1 Receive Complete */ - DMA_CH_TRIGSRC_USARTC1_DRE_gc = (0x4F<<0), /* USART C1 Data Register Empty */ - DMA_CH_TRIGSRC_TCD0_OVF_gc = (0x60<<0), /* Timer/Counter D0 Overflow */ - DMA_CH_TRIGSRC_TCD0_ERR_gc = (0x61<<0), /* Timer/Counter D0 Error */ - DMA_CH_TRIGSRC_TCD0_CCA_gc = (0x62<<0), /* Timer/Counter D0 Compare or Capture A */ - DMA_CH_TRIGSRC_TCD0_CCB_gc = (0x63<<0), /* Timer/Counter D0 Compare or Capture B */ - DMA_CH_TRIGSRC_TCD0_CCC_gc = (0x64<<0), /* Timer/Counter D0 Compare or Capture C */ - DMA_CH_TRIGSRC_TCD0_CCD_gc = (0x65<<0), /* Timer/Counter D0 Compare or Capture D */ - DMA_CH_TRIGSRC_TCD1_OVF_gc = (0x66<<0), /* Timer/Counter D1 Overflow */ - DMA_CH_TRIGSRC_TCD1_ERR_gc = (0x67<<0), /* Timer/Counter D1 Error */ - DMA_CH_TRIGSRC_TCD1_CCA_gc = (0x68<<0), /* Timer/Counter D1 Compare or Capture A */ - DMA_CH_TRIGSRC_TCD1_CCB_gc = (0x69<<0), /* Timer/Counter D1 Compare or Capture B */ - DMA_CH_TRIGSRC_SPID_gc = (0x6A<<0), /* SPI D Transfer Complete */ - DMA_CH_TRIGSRC_USARTD0_RXC_gc = (0x6B<<0), /* USART D0 Receive Complete */ - DMA_CH_TRIGSRC_USARTD0_DRE_gc = (0x6C<<0), /* USART D0 Data Register Empty */ - DMA_CH_TRIGSRC_USARTD1_RXC_gc = (0x6E<<0), /* USART D1 Receive Complete */ - DMA_CH_TRIGSRC_USARTD1_DRE_gc = (0x6F<<0), /* USART D1 Data Register Empty */ - DMA_CH_TRIGSRC_TCE0_OVF_gc = (0x80<<0), /* Timer/Counter E0 Overflow */ - DMA_CH_TRIGSRC_TCE0_ERR_gc = (0x81<<0), /* Timer/Counter E0 Error */ - DMA_CH_TRIGSRC_TCE0_CCA_gc = (0x82<<0), /* Timer/Counter E0 Compare or Capture A */ - DMA_CH_TRIGSRC_TCE0_CCB_gc = (0x83<<0), /* Timer/Counter E0 Compare or Capture B */ - DMA_CH_TRIGSRC_TCE0_CCC_gc = (0x84<<0), /* Timer/Counter E0 Compare or Capture C */ - DMA_CH_TRIGSRC_TCE0_CCD_gc = (0x85<<0), /* Timer/Counter E0 Compare or Capture D */ - DMA_CH_TRIGSRC_TCE1_OVF_gc = (0x86<<0), /* Timer/Counter E1 Overflow */ - DMA_CH_TRIGSRC_TCE1_ERR_gc = (0x87<<0), /* Timer/Counter E1 Error */ - DMA_CH_TRIGSRC_TCE1_CCA_gc = (0x88<<0), /* Timer/Counter E1 Compare or Capture A */ - DMA_CH_TRIGSRC_TCE1_CCB_gc = (0x89<<0), /* Timer/Counter E1 Compare or Capture B */ - DMA_CH_TRIGSRC_SPIE_gc = (0x8A<<0), /* SPI E Transfer Complete */ - DMA_CH_TRIGSRC_USARTE0_RXC_gc = (0x8B<<0), /* USART E0 Receive Complete */ - DMA_CH_TRIGSRC_USARTE0_DRE_gc = (0x8C<<0), /* USART E0 Data Register Empty */ - DMA_CH_TRIGSRC_USARTE1_RXC_gc = (0x8E<<0), /* USART E1 Receive Complete */ - DMA_CH_TRIGSRC_USARTE1_DRE_gc = (0x8F<<0), /* USART E1 Data Register Empty */ - DMA_CH_TRIGSRC_TCF0_OVF_gc = (0xA0<<0), /* Timer/Counter F0 Overflow */ - DMA_CH_TRIGSRC_TCF0_ERR_gc = (0xA1<<0), /* Timer/Counter F0 Error */ - DMA_CH_TRIGSRC_TCF0_CCA_gc = (0xA2<<0), /* Timer/Counter F0 Compare or Capture A */ - DMA_CH_TRIGSRC_TCF0_CCB_gc = (0xA3<<0), /* Timer/Counter F0 Compare or Capture B */ - DMA_CH_TRIGSRC_TCF0_CCC_gc = (0xA4<<0), /* Timer/Counter F0 Compare or Capture C */ - DMA_CH_TRIGSRC_TCF0_CCD_gc = (0xA5<<0), /* Timer/Counter F0 Compare or Capture D */ - DMA_CH_TRIGSRC_TCF1_OVF_gc = (0xA6<<0), /* Timer/Counter F1 Overflow */ - DMA_CH_TRIGSRC_TCF1_ERR_gc = (0xA7<<0), /* Timer/Counter F1 Error */ - DMA_CH_TRIGSRC_TCF1_CCA_gc = (0xA8<<0), /* Timer/Counter F1 Compare or Capture A */ - DMA_CH_TRIGSRC_TCF1_CCB_gc = (0xA9<<0), /* Timer/Counter F1 Compare or Capture B */ - DMA_CH_TRIGSRC_SPIF_gc = (0xAA<<0), /* SPI F Transfer Complete */ - DMA_CH_TRIGSRC_USARTF0_RXC_gc = (0xAB<<0), /* USART F0 Receive Complete */ - DMA_CH_TRIGSRC_USARTF0_DRE_gc = (0xAC<<0), /* USART F0 Data Register Empty */ - DMA_CH_TRIGSRC_USARTF1_RXC_gc = (0xAE<<0), /* USART F1 Receive Complete */ - DMA_CH_TRIGSRC_USARTF1_DRE_gc = (0xAF<<0), /* USART F1 Data Register Empty */ -} DMA_CH_TRIGSRC_t; - -/* Double buffering mode */ -typedef enum DMA_DBUFMODE_enum -{ - DMA_DBUFMODE_DISABLED_gc = (0x00<<2), /* Double buffering disabled */ - DMA_DBUFMODE_CH01_gc = (0x01<<2), /* Double buffering enabled on channel 0/1 */ - DMA_DBUFMODE_CH23_gc = (0x02<<2), /* Double buffering enabled on channel 2/3 */ - DMA_DBUFMODE_CH01CH23_gc = (0x03<<2), /* Double buffering enabled on ch. 0/1 and ch. 2/3 */ -} DMA_DBUFMODE_t; - -/* Priority mode */ -typedef enum DMA_PRIMODE_enum -{ - DMA_PRIMODE_RR0123_gc = (0x00<<0), /* Round Robin */ - DMA_PRIMODE_CH0RR123_gc = (0x01<<0), /* Channel 0 > Round Robin on channel 1/2/3 */ - DMA_PRIMODE_CH01RR23_gc = (0x02<<0), /* Channel 0 > channel 1 > Round Robin on channel 2/3 */ - DMA_PRIMODE_CH0123_gc = (0x03<<0), /* Channel 0 > channel 1 > channel 2 > channel 3 */ -} DMA_PRIMODE_t; - -/* Interrupt level */ -typedef enum DMA_CH_ERRINTLVL_enum -{ - DMA_CH_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ - DMA_CH_ERRINTLVL_LO_gc = (0x01<<2), /* Low level */ - DMA_CH_ERRINTLVL_MED_gc = (0x02<<2), /* Medium level */ - DMA_CH_ERRINTLVL_HI_gc = (0x03<<2), /* High level */ -} DMA_CH_ERRINTLVL_t; - -/* Interrupt level */ -typedef enum DMA_CH_TRNINTLVL_enum -{ - DMA_CH_TRNINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ - DMA_CH_TRNINTLVL_LO_gc = (0x01<<0), /* Low level */ - DMA_CH_TRNINTLVL_MED_gc = (0x02<<0), /* Medium level */ - DMA_CH_TRNINTLVL_HI_gc = (0x03<<0), /* High level */ -} DMA_CH_TRNINTLVL_t; - - -/* --------------------------------------------------------------------------- -EVSYS - Event System --------------------------------------------------------------------------- -*/ - -/* Event System */ -typedef struct EVSYS_struct -{ - register8_t CH0MUX; /* Event Channel 0 Multiplexer */ - register8_t CH1MUX; /* Event Channel 1 Multiplexer */ - register8_t CH2MUX; /* Event Channel 2 Multiplexer */ - register8_t CH3MUX; /* Event Channel 3 Multiplexer */ - register8_t CH4MUX; /* Event Channel 4 Multiplexer */ - register8_t CH5MUX; /* Event Channel 5 Multiplexer */ - register8_t CH6MUX; /* Event Channel 6 Multiplexer */ - register8_t CH7MUX; /* Event Channel 7 Multiplexer */ - register8_t CH0CTRL; /* Channel 0 Control Register */ - register8_t CH1CTRL; /* Channel 1 Control Register */ - register8_t CH2CTRL; /* Channel 2 Control Register */ - register8_t CH3CTRL; /* Channel 3 Control Register */ - register8_t CH4CTRL; /* Channel 4 Control Register */ - register8_t CH5CTRL; /* Channel 5 Control Register */ - register8_t CH6CTRL; /* Channel 6 Control Register */ - register8_t CH7CTRL; /* Channel 7 Control Register */ - register8_t STROBE; /* Event Strobe */ - register8_t DATA; /* Event Data */ -} EVSYS_t; - -/* Quadrature Decoder Index Recognition Mode */ -typedef enum EVSYS_QDIRM_enum -{ - EVSYS_QDIRM_00_gc = (0x00<<5), /* QDPH0 = 0, QDPH90 = 0 */ - EVSYS_QDIRM_01_gc = (0x01<<5), /* QDPH0 = 0, QDPH90 = 1 */ - EVSYS_QDIRM_10_gc = (0x02<<5), /* QDPH0 = 1, QDPH90 = 0 */ - EVSYS_QDIRM_11_gc = (0x03<<5), /* QDPH0 = 1, QDPH90 = 1 */ -} EVSYS_QDIRM_t; - -/* Digital filter coefficient */ -typedef enum EVSYS_DIGFILT_enum -{ - EVSYS_DIGFILT_1SAMPLE_gc = (0x00<<0), /* 1 SAMPLE */ - EVSYS_DIGFILT_2SAMPLES_gc = (0x01<<0), /* 2 SAMPLES */ - EVSYS_DIGFILT_3SAMPLES_gc = (0x02<<0), /* 3 SAMPLES */ - EVSYS_DIGFILT_4SAMPLES_gc = (0x03<<0), /* 4 SAMPLES */ - EVSYS_DIGFILT_5SAMPLES_gc = (0x04<<0), /* 5 SAMPLES */ - EVSYS_DIGFILT_6SAMPLES_gc = (0x05<<0), /* 6 SAMPLES */ - EVSYS_DIGFILT_7SAMPLES_gc = (0x06<<0), /* 7 SAMPLES */ - EVSYS_DIGFILT_8SAMPLES_gc = (0x07<<0), /* 8 SAMPLES */ -} EVSYS_DIGFILT_t; - -/* Event Channel multiplexer input selection */ -typedef enum EVSYS_CHMUX_enum -{ - EVSYS_CHMUX_OFF_gc = (0x00<<0), /* Off */ - EVSYS_CHMUX_RTC_OVF_gc = (0x08<<0), /* RTC Overflow */ - EVSYS_CHMUX_RTC_CMP_gc = (0x09<<0), /* RTC Compare Match */ - EVSYS_CHMUX_ACA_CH0_gc = (0x10<<0), /* Analog Comparator A Channel 0 */ - EVSYS_CHMUX_ACA_CH1_gc = (0x11<<0), /* Analog Comparator A Channel 1 */ - EVSYS_CHMUX_ACA_WIN_gc = (0x12<<0), /* Analog Comparator A Window */ - EVSYS_CHMUX_ACB_CH0_gc = (0x13<<0), /* Analog Comparator B Channel 0 */ - EVSYS_CHMUX_ACB_CH1_gc = (0x14<<0), /* Analog Comparator B Channel 1 */ - EVSYS_CHMUX_ACB_WIN_gc = (0x15<<0), /* Analog Comparator B Window */ - EVSYS_CHMUX_ADCA_CH0_gc = (0x20<<0), /* ADC A Channel 0 */ - EVSYS_CHMUX_ADCA_CH1_gc = (0x21<<0), /* ADC A Channel 1 */ - EVSYS_CHMUX_ADCA_CH2_gc = (0x22<<0), /* ADC A Channel 2 */ - EVSYS_CHMUX_ADCA_CH3_gc = (0x23<<0), /* ADC A Channel 3 */ - EVSYS_CHMUX_ADCB_CH0_gc = (0x24<<0), /* ADC B Channel 0 */ - EVSYS_CHMUX_ADCB_CH1_gc = (0x25<<0), /* ADC B Channel 1 */ - EVSYS_CHMUX_ADCB_CH2_gc = (0x26<<0), /* ADC B Channel 2 */ - EVSYS_CHMUX_ADCB_CH3_gc = (0x27<<0), /* ADC B Channel 3 */ - EVSYS_CHMUX_PORTA_PIN0_gc = (0x50<<0), /* Port A, Pin0 */ - EVSYS_CHMUX_PORTA_PIN1_gc = (0x51<<0), /* Port A, Pin1 */ - EVSYS_CHMUX_PORTA_PIN2_gc = (0x52<<0), /* Port A, Pin2 */ - EVSYS_CHMUX_PORTA_PIN3_gc = (0x53<<0), /* Port A, Pin3 */ - EVSYS_CHMUX_PORTA_PIN4_gc = (0x54<<0), /* Port A, Pin4 */ - EVSYS_CHMUX_PORTA_PIN5_gc = (0x55<<0), /* Port A, Pin5 */ - EVSYS_CHMUX_PORTA_PIN6_gc = (0x56<<0), /* Port A, Pin6 */ - EVSYS_CHMUX_PORTA_PIN7_gc = (0x57<<0), /* Port A, Pin7 */ - EVSYS_CHMUX_PORTB_PIN0_gc = (0x58<<0), /* Port B, Pin0 */ - EVSYS_CHMUX_PORTB_PIN1_gc = (0x59<<0), /* Port B, Pin1 */ - EVSYS_CHMUX_PORTB_PIN2_gc = (0x5A<<0), /* Port B, Pin2 */ - EVSYS_CHMUX_PORTB_PIN3_gc = (0x5B<<0), /* Port B, Pin3 */ - EVSYS_CHMUX_PORTB_PIN4_gc = (0x5C<<0), /* Port B, Pin4 */ - EVSYS_CHMUX_PORTB_PIN5_gc = (0x5D<<0), /* Port B, Pin5 */ - EVSYS_CHMUX_PORTB_PIN6_gc = (0x5E<<0), /* Port B, Pin6 */ - EVSYS_CHMUX_PORTB_PIN7_gc = (0x5F<<0), /* Port B, Pin7 */ - EVSYS_CHMUX_PORTC_PIN0_gc = (0x60<<0), /* Port C, Pin0 */ - EVSYS_CHMUX_PORTC_PIN1_gc = (0x61<<0), /* Port C, Pin1 */ - EVSYS_CHMUX_PORTC_PIN2_gc = (0x62<<0), /* Port C, Pin2 */ - EVSYS_CHMUX_PORTC_PIN3_gc = (0x63<<0), /* Port C, Pin3 */ - EVSYS_CHMUX_PORTC_PIN4_gc = (0x64<<0), /* Port C, Pin4 */ - EVSYS_CHMUX_PORTC_PIN5_gc = (0x65<<0), /* Port C, Pin5 */ - EVSYS_CHMUX_PORTC_PIN6_gc = (0x66<<0), /* Port C, Pin6 */ - EVSYS_CHMUX_PORTC_PIN7_gc = (0x67<<0), /* Port C, Pin7 */ - EVSYS_CHMUX_PORTD_PIN0_gc = (0x68<<0), /* Port D, Pin0 */ - EVSYS_CHMUX_PORTD_PIN1_gc = (0x69<<0), /* Port D, Pin1 */ - EVSYS_CHMUX_PORTD_PIN2_gc = (0x6A<<0), /* Port D, Pin2 */ - EVSYS_CHMUX_PORTD_PIN3_gc = (0x6B<<0), /* Port D, Pin3 */ - EVSYS_CHMUX_PORTD_PIN4_gc = (0x6C<<0), /* Port D, Pin4 */ - EVSYS_CHMUX_PORTD_PIN5_gc = (0x6D<<0), /* Port D, Pin5 */ - EVSYS_CHMUX_PORTD_PIN6_gc = (0x6E<<0), /* Port D, Pin6 */ - EVSYS_CHMUX_PORTD_PIN7_gc = (0x6F<<0), /* Port D, Pin7 */ - EVSYS_CHMUX_PORTE_PIN0_gc = (0x70<<0), /* Port E, Pin0 */ - EVSYS_CHMUX_PORTE_PIN1_gc = (0x71<<0), /* Port E, Pin1 */ - EVSYS_CHMUX_PORTE_PIN2_gc = (0x72<<0), /* Port E, Pin2 */ - EVSYS_CHMUX_PORTE_PIN3_gc = (0x73<<0), /* Port E, Pin3 */ - EVSYS_CHMUX_PORTE_PIN4_gc = (0x74<<0), /* Port E, Pin4 */ - EVSYS_CHMUX_PORTE_PIN5_gc = (0x75<<0), /* Port E, Pin5 */ - EVSYS_CHMUX_PORTE_PIN6_gc = (0x76<<0), /* Port E, Pin6 */ - EVSYS_CHMUX_PORTE_PIN7_gc = (0x77<<0), /* Port E, Pin7 */ - EVSYS_CHMUX_PORTF_PIN0_gc = (0x78<<0), /* Port F, Pin0 */ - EVSYS_CHMUX_PORTF_PIN1_gc = (0x79<<0), /* Port F, Pin1 */ - EVSYS_CHMUX_PORTF_PIN2_gc = (0x7A<<0), /* Port F, Pin2 */ - EVSYS_CHMUX_PORTF_PIN3_gc = (0x7B<<0), /* Port F, Pin3 */ - EVSYS_CHMUX_PORTF_PIN4_gc = (0x7C<<0), /* Port F, Pin4 */ - EVSYS_CHMUX_PORTF_PIN5_gc = (0x7D<<0), /* Port F, Pin5 */ - EVSYS_CHMUX_PORTF_PIN6_gc = (0x7E<<0), /* Port F, Pin6 */ - EVSYS_CHMUX_PORTF_PIN7_gc = (0x7F<<0), /* Port F, Pin7 */ - EVSYS_CHMUX_PRESCALER_1_gc = (0x80<<0), /* Prescaler, divide by 1 */ - EVSYS_CHMUX_PRESCALER_2_gc = (0x81<<0), /* Prescaler, divide by 2 */ - EVSYS_CHMUX_PRESCALER_4_gc = (0x82<<0), /* Prescaler, divide by 4 */ - EVSYS_CHMUX_PRESCALER_8_gc = (0x83<<0), /* Prescaler, divide by 8 */ - EVSYS_CHMUX_PRESCALER_16_gc = (0x84<<0), /* Prescaler, divide by 16 */ - EVSYS_CHMUX_PRESCALER_32_gc = (0x85<<0), /* Prescaler, divide by 32 */ - EVSYS_CHMUX_PRESCALER_64_gc = (0x86<<0), /* Prescaler, divide by 64 */ - EVSYS_CHMUX_PRESCALER_128_gc = (0x87<<0), /* Prescaler, divide by 128 */ - EVSYS_CHMUX_PRESCALER_256_gc = (0x88<<0), /* Prescaler, divide by 256 */ - EVSYS_CHMUX_PRESCALER_512_gc = (0x89<<0), /* Prescaler, divide by 512 */ - EVSYS_CHMUX_PRESCALER_1024_gc = (0x8A<<0), /* Prescaler, divide by 1024 */ - EVSYS_CHMUX_PRESCALER_2048_gc = (0x8B<<0), /* Prescaler, divide by 2048 */ - EVSYS_CHMUX_PRESCALER_4096_gc = (0x8C<<0), /* Prescaler, divide by 4096 */ - EVSYS_CHMUX_PRESCALER_8192_gc = (0x8D<<0), /* Prescaler, divide by 8192 */ - EVSYS_CHMUX_PRESCALER_16384_gc = (0x8E<<0), /* Prescaler, divide by 16384 */ - EVSYS_CHMUX_PRESCALER_32768_gc = (0x8F<<0), /* Prescaler, divide by 32768 */ - EVSYS_CHMUX_TCC0_OVF_gc = (0xC0<<0), /* Timer/Counter C0 Overflow */ - EVSYS_CHMUX_TCC0_ERR_gc = (0xC1<<0), /* Timer/Counter C0 Error */ - EVSYS_CHMUX_TCC0_CCA_gc = (0xC4<<0), /* Timer/Counter C0 Compare or Capture A */ - EVSYS_CHMUX_TCC0_CCB_gc = (0xC5<<0), /* Timer/Counter C0 Compare or Capture B */ - EVSYS_CHMUX_TCC0_CCC_gc = (0xC6<<0), /* Timer/Counter C0 Compare or Capture C */ - EVSYS_CHMUX_TCC0_CCD_gc = (0xC7<<0), /* Timer/Counter C0 Compare or Capture D */ - EVSYS_CHMUX_TCC1_OVF_gc = (0xC8<<0), /* Timer/Counter C1 Overflow */ - EVSYS_CHMUX_TCC1_ERR_gc = (0xC9<<0), /* Timer/Counter C1 Error */ - EVSYS_CHMUX_TCC1_CCA_gc = (0xCC<<0), /* Timer/Counter C1 Compare or Capture A */ - EVSYS_CHMUX_TCC1_CCB_gc = (0xCD<<0), /* Timer/Counter C1 Compare or Capture B */ - EVSYS_CHMUX_TCD0_OVF_gc = (0xD0<<0), /* Timer/Counter D0 Overflow */ - EVSYS_CHMUX_TCD0_ERR_gc = (0xD1<<0), /* Timer/Counter D0 Error */ - EVSYS_CHMUX_TCD0_CCA_gc = (0xD4<<0), /* Timer/Counter D0 Compare or Capture A */ - EVSYS_CHMUX_TCD0_CCB_gc = (0xD5<<0), /* Timer/Counter D0 Compare or Capture B */ - EVSYS_CHMUX_TCD0_CCC_gc = (0xD6<<0), /* Timer/Counter D0 Compare or Capture C */ - EVSYS_CHMUX_TCD0_CCD_gc = (0xD7<<0), /* Timer/Counter D0 Compare or Capture D */ - EVSYS_CHMUX_TCD1_OVF_gc = (0xD8<<0), /* Timer/Counter D1 Overflow */ - EVSYS_CHMUX_TCD1_ERR_gc = (0xD9<<0), /* Timer/Counter D1 Error */ - EVSYS_CHMUX_TCD1_CCA_gc = (0xDC<<0), /* Timer/Counter D1 Compare or Capture A */ - EVSYS_CHMUX_TCD1_CCB_gc = (0xDD<<0), /* Timer/Counter D1 Compare or Capture B */ - EVSYS_CHMUX_TCE0_OVF_gc = (0xE0<<0), /* Timer/Counter E0 Overflow */ - EVSYS_CHMUX_TCE0_ERR_gc = (0xE1<<0), /* Timer/Counter E0 Error */ - EVSYS_CHMUX_TCE0_CCA_gc = (0xE4<<0), /* Timer/Counter E0 Compare or Capture A */ - EVSYS_CHMUX_TCE0_CCB_gc = (0xE5<<0), /* Timer/Counter E0 Compare or Capture B */ - EVSYS_CHMUX_TCE0_CCC_gc = (0xE6<<0), /* Timer/Counter E0 Compare or Capture C */ - EVSYS_CHMUX_TCE0_CCD_gc = (0xE7<<0), /* Timer/Counter E0 Compare or Capture D */ - EVSYS_CHMUX_TCE1_OVF_gc = (0xE8<<0), /* Timer/Counter E1 Overflow */ - EVSYS_CHMUX_TCE1_ERR_gc = (0xE9<<0), /* Timer/Counter E1 Error */ - EVSYS_CHMUX_TCE1_CCA_gc = (0xEC<<0), /* Timer/Counter E1 Compare or Capture A */ - EVSYS_CHMUX_TCE1_CCB_gc = (0xED<<0), /* Timer/Counter E1 Compare or Capture B */ - EVSYS_CHMUX_TCF0_OVF_gc = (0xF0<<0), /* Timer/Counter F0 Overflow */ - EVSYS_CHMUX_TCF0_ERR_gc = (0xF1<<0), /* Timer/Counter F0 Error */ - EVSYS_CHMUX_TCF0_CCA_gc = (0xF4<<0), /* Timer/Counter F0 Compare or Capture A */ - EVSYS_CHMUX_TCF0_CCB_gc = (0xF5<<0), /* Timer/Counter F0 Compare or Capture B */ - EVSYS_CHMUX_TCF0_CCC_gc = (0xF6<<0), /* Timer/Counter F0 Compare or Capture C */ - EVSYS_CHMUX_TCF0_CCD_gc = (0xF7<<0), /* Timer/Counter F0 Compare or Capture D */ - EVSYS_CHMUX_TCF1_OVF_gc = (0xF8<<0), /* Timer/Counter F1 Overflow */ - EVSYS_CHMUX_TCF1_ERR_gc = (0xF9<<0), /* Timer/Counter F1 Error */ - EVSYS_CHMUX_TCF1_CCA_gc = (0xFC<<0), /* Timer/Counter F1 Compare or Capture A */ - EVSYS_CHMUX_TCF1_CCB_gc = (0xFD<<0), /* Timer/Counter F1 Compare or Capture B */ -} EVSYS_CHMUX_t; - - -/* --------------------------------------------------------------------------- -NVM - Non Volatile Memory Controller --------------------------------------------------------------------------- -*/ - -/* Non-volatile Memory Controller */ -typedef struct NVM_struct -{ - register8_t ADDR0; /* Address Register 0 */ - register8_t ADDR1; /* Address Register 1 */ - register8_t ADDR2; /* Address Register 2 */ - register8_t reserved_0x03; - register8_t DATA0; /* Data Register 0 */ - register8_t DATA1; /* Data Register 1 */ - register8_t DATA2; /* Data Register 2 */ - register8_t reserved_0x07; - register8_t reserved_0x08; - register8_t reserved_0x09; - register8_t CMD; /* Command */ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t INTCTRL; /* Interrupt Control */ - register8_t reserved_0x0E; - register8_t STATUS; /* Status */ - register8_t LOCK_BITS; /* Lock Bits */ -} NVM_t; - -/* --------------------------------------------------------------------------- -NVM - Non Volatile Memory Controller --------------------------------------------------------------------------- -*/ - -/* Lock Bits */ -typedef struct NVM_LOCKBITS_struct -{ - register8_t LOCKBITS; /* Lock Bits */ -} NVM_LOCKBITS_t; - -/* --------------------------------------------------------------------------- -NVM - Non Volatile Memory Controller --------------------------------------------------------------------------- -*/ - -/* Fuses */ -typedef struct NVM_FUSES_struct -{ - register8_t FUSEBYTE0; /* JTAG User ID */ - register8_t FUSEBYTE1; /* Watchdog Configuration */ - register8_t FUSEBYTE2; /* Reset Configuration */ - register8_t reserved_0x03; - register8_t FUSEBYTE4; /* Start-up Configuration */ - register8_t FUSEBYTE5; /* EESAVE and BOD Level */ -} NVM_FUSES_t; - -/* --------------------------------------------------------------------------- -NVM - Non Volatile Memory Controller --------------------------------------------------------------------------- -*/ - -/* Production Signatures */ -typedef struct NVM_PROD_SIGNATURES_struct -{ - register8_t RCOSC2M; /* RCOSC 2MHz Calibration Value */ - register8_t reserved_0x01; - register8_t RCOSC32K; /* RCOSC 32kHz Calibration Value */ - register8_t RCOSC32M; /* RCOSC 32MHz Calibration Value */ - register8_t reserved_0x04; - register8_t reserved_0x05; - register8_t reserved_0x06; - register8_t reserved_0x07; - register8_t LOTNUM0; /* Lot Number Byte 0, ASCII */ - register8_t LOTNUM1; /* Lot Number Byte 1, ASCII */ - register8_t LOTNUM2; /* Lot Number Byte 2, ASCII */ - register8_t LOTNUM3; /* Lot Number Byte 3, ASCII */ - register8_t LOTNUM4; /* Lot Number Byte 4, ASCII */ - register8_t LOTNUM5; /* Lot Number Byte 5, ASCII */ - register8_t reserved_0x0E; - register8_t reserved_0x0F; - register8_t WAFNUM; /* Wafer Number */ - register8_t reserved_0x11; - register8_t COORDX0; /* Wafer Coordinate X Byte 0 */ - register8_t COORDX1; /* Wafer Coordinate X Byte 1 */ - register8_t COORDY0; /* Wafer Coordinate Y Byte 0 */ - register8_t COORDY1; /* Wafer Coordinate Y Byte 1 */ - register8_t reserved_0x16; - register8_t reserved_0x17; - register8_t reserved_0x18; - register8_t reserved_0x19; - register8_t reserved_0x1A; - register8_t reserved_0x1B; - register8_t reserved_0x1C; - register8_t reserved_0x1D; - register8_t reserved_0x1E; - register8_t reserved_0x1F; - register8_t ADCACAL0; /* ADCA Calibration Byte 0 */ - register8_t ADCACAL1; /* ADCA Calibration Byte 1 */ - register8_t reserved_0x22; - register8_t reserved_0x23; - register8_t ADCBCAL0; /* ADCB Calibration Byte 0 */ - register8_t ADCBCAL1; /* ADCB Calibration Byte 1 */ - register8_t reserved_0x26; - register8_t reserved_0x27; - register8_t reserved_0x28; - register8_t reserved_0x29; - register8_t reserved_0x2A; - register8_t reserved_0x2B; - register8_t reserved_0x2C; - register8_t reserved_0x2D; - register8_t TEMPSENSE0; /* Temperature Sensor Calibration Byte 0 */ - register8_t TEMPSENSE1; /* Temperature Sensor Calibration Byte 0 */ - register8_t DACAOFFCAL; /* DACA Calibration Byte 0 */ - register8_t DACAGAINCAL; /* DACA Calibration Byte 1 */ - register8_t DACBOFFCAL; /* DACB Calibration Byte 0 */ - register8_t DACBGAINCAL; /* DACB Calibration Byte 1 */ - register8_t reserved_0x34; - register8_t reserved_0x35; - register8_t reserved_0x36; - register8_t reserved_0x37; - register8_t reserved_0x38; - register8_t reserved_0x39; - register8_t reserved_0x3A; - register8_t reserved_0x3B; - register8_t reserved_0x3C; - register8_t reserved_0x3D; - register8_t reserved_0x3E; -} NVM_PROD_SIGNATURES_t; - -/* NVM Command */ -typedef enum NVM_CMD_enum -{ - NVM_CMD_NO_OPERATION_gc = (0x00<<0), /* Noop/Ordinary LPM */ - NVM_CMD_READ_CALIB_ROW_gc = (0x02<<0), /* Read calibration row */ - NVM_CMD_READ_USER_SIG_ROW_gc = (0x01<<0), /* Read user signature row */ - NVM_CMD_READ_EEPROM_gc = (0x06<<0), /* Read EEPROM */ - NVM_CMD_READ_FUSES_gc = (0x07<<0), /* Read fuse byte */ - NVM_CMD_WRITE_LOCK_BITS_gc = (0x08<<0), /* Write lock bits */ - NVM_CMD_ERASE_USER_SIG_ROW_gc = (0x18<<0), /* Erase user signature row */ - NVM_CMD_WRITE_USER_SIG_ROW_gc = (0x1A<<0), /* Write user signature row */ - NVM_CMD_ERASE_APP_gc = (0x20<<0), /* Erase Application Section */ - NVM_CMD_ERASE_APP_PAGE_gc = (0x22<<0), /* Erase Application Section page */ - NVM_CMD_LOAD_FLASH_BUFFER_gc = (0x23<<0), /* Load Flash page buffer */ - NVM_CMD_WRITE_APP_PAGE_gc = (0x24<<0), /* Write Application Section page */ - NVM_CMD_ERASE_WRITE_APP_PAGE_gc = (0x25<<0), /* Erase-and-write Application Section page */ - NVM_CMD_ERASE_FLASH_BUFFER_gc = (0x26<<0), /* Erase/flush Flash page buffer */ - NVM_CMD_ERASE_BOOT_PAGE_gc = (0x2A<<0), /* Erase Boot Section page */ - NVM_CMD_WRITE_BOOT_PAGE_gc = (0x2C<<0), /* Write Boot Section page */ - NVM_CMD_ERASE_WRITE_BOOT_PAGE_gc = (0x2D<<0), /* Erase-and-write Boot Section page */ - NVM_CMD_ERASE_EEPROM_gc = (0x30<<0), /* Erase EEPROM */ - NVM_CMD_ERASE_EEPROM_PAGE_gc = (0x32<<0), /* Erase EEPROM page */ - NVM_CMD_LOAD_EEPROM_BUFFER_gc = (0x33<<0), /* Load EEPROM page buffer */ - NVM_CMD_WRITE_EEPROM_PAGE_gc = (0x34<<0), /* Write EEPROM page */ - NVM_CMD_ERASE_WRITE_EEPROM_PAGE_gc = (0x35<<0), /* Erase-and-write EEPROM page */ - NVM_CMD_ERASE_EEPROM_BUFFER_gc = (0x36<<0), /* Erase/flush EEPROM page buffer */ - NVM_CMD_APP_CRC_gc = (0x38<<0), /* Generate Application section CRC */ - NVM_CMD_BOOT_CRC_gc = (0x39<<0), /* Generate Boot Section CRC */ - NVM_CMD_FLASH_RANGE_CRC_gc = (0x3A<<0), /* Generate Flash Range CRC */ -} NVM_CMD_t; - -/* SPM ready interrupt level */ -typedef enum NVM_SPMLVL_enum -{ - NVM_SPMLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ - NVM_SPMLVL_LO_gc = (0x01<<2), /* Low level */ - NVM_SPMLVL_MED_gc = (0x02<<2), /* Medium level */ - NVM_SPMLVL_HI_gc = (0x03<<2), /* High level */ -} NVM_SPMLVL_t; - -/* EEPROM ready interrupt level */ -typedef enum NVM_EELVL_enum -{ - NVM_EELVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ - NVM_EELVL_LO_gc = (0x01<<0), /* Low level */ - NVM_EELVL_MED_gc = (0x02<<0), /* Medium level */ - NVM_EELVL_HI_gc = (0x03<<0), /* High level */ -} NVM_EELVL_t; - -/* Boot lock bits - boot setcion */ -typedef enum NVM_BLBB_enum -{ - NVM_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ - NVM_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ - NVM_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ - NVM_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ -} NVM_BLBB_t; - -/* Boot lock bits - application section */ -typedef enum NVM_BLBA_enum -{ - NVM_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ - NVM_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ - NVM_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ - NVM_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ -} NVM_BLBA_t; - -/* Boot lock bits - application table section */ -typedef enum NVM_BLBAT_enum -{ - NVM_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ - NVM_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ - NVM_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ - NVM_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ -} NVM_BLBAT_t; - -/* Lock bits */ -typedef enum NVM_LB_enum -{ - NVM_LB_NOLOCK_gc = (0x03<<0), /* No locks */ - NVM_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ - NVM_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ -} NVM_LB_t; - -/* Boot Loader Section Reset Vector */ -typedef enum BOOTRST_enum -{ - BOOTRST_BOOTLDR_gc = (0x00<<6), /* Boot Loader Reset */ - BOOTRST_APPLICATION_gc = (0x01<<6), /* Application Reset */ -} BOOTRST_t; - -/* BOD operation */ -typedef enum BOD_enum -{ - BOD_INSAMPLEDMODE_gc = (0x01<<0), /* BOD enabled in sampled mode */ - BOD_CONTINOUSLY_gc = (0x02<<0), /* BOD enabled continuously */ - BOD_DISABLED_gc = (0x03<<0), /* BOD Disabled */ -} BOD_t; - -/* Watchdog (Window) Timeout Period */ -typedef enum WD_enum -{ - WD_8CLK_gc = (0x00<<4), /* 8 cycles (8ms @ 3.3V) */ - WD_16CLK_gc = (0x01<<4), /* 16 cycles (16ms @ 3.3V) */ - WD_32CLK_gc = (0x02<<4), /* 32 cycles (32ms @ 3.3V) */ - WD_64CLK_gc = (0x03<<4), /* 64 cycles (64ms @ 3.3V) */ - WD_128CLK_gc = (0x04<<4), /* 128 cycles (0.125s @ 3.3V) */ - WD_256CLK_gc = (0x05<<4), /* 256 cycles (0.25s @ 3.3V) */ - WD_512CLK_gc = (0x06<<4), /* 512 cycles (0.5s @ 3.3V) */ - WD_1KCLK_gc = (0x07<<4), /* 1K cycles (1s @ 3.3V) */ - WD_2KCLK_gc = (0x08<<4), /* 2K cycles (2s @ 3.3V) */ - WD_4KCLK_gc = (0x09<<4), /* 4K cycles (4s @ 3.3V) */ - WD_8KCLK_gc = (0x0A<<4), /* 8K cycles (8s @ 3.3V) */ -} WD_t; - -/* Start-up Time */ -typedef enum SUT_enum -{ - SUT_0MS_gc = (0x03<<2), /* 0 ms */ - SUT_4MS_gc = (0x01<<2), /* 4 ms */ - SUT_64MS_gc = (0x00<<2), /* 64 ms */ -} SUT_t; - -/* Brown Out Detection Voltage Level */ -typedef enum BODLVL_enum -{ - BODLVL_1V6_gc = (0x07<<0), /* 1.6 V */ - BODLVL_1V9_gc = (0x06<<0), /* 1.8 V */ - BODLVL_2V1_gc = (0x05<<0), /* 2.0 V */ - BODLVL_2V4_gc = (0x04<<0), /* 2.2 V */ - BODLVL_2V6_gc = (0x03<<0), /* 2.4 V */ - BODLVL_2V9_gc = (0x02<<0), /* 2.7 V */ - BODLVL_3V2_gc = (0x01<<0), /* 2.9 V */ -} BODLVL_t; - - -/* --------------------------------------------------------------------------- -AC - Analog Comparator --------------------------------------------------------------------------- -*/ - -/* Analog Comparator */ -typedef struct AC_struct -{ - register8_t AC0CTRL; /* Comparator 0 Control */ - register8_t AC1CTRL; /* Comparator 1 Control */ - register8_t AC0MUXCTRL; /* Comparator 0 MUX Control */ - register8_t AC1MUXCTRL; /* Comparator 1 MUX Control */ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t WINCTRL; /* Window Mode Control */ - register8_t STATUS; /* Status */ -} AC_t; - -/* Interrupt mode */ -typedef enum AC_INTMODE_enum -{ - AC_INTMODE_BOTHEDGES_gc = (0x00<<6), /* Interrupt on both edges */ - AC_INTMODE_FALLING_gc = (0x02<<6), /* Interrupt on falling edge */ - AC_INTMODE_RISING_gc = (0x03<<6), /* Interrupt on rising edge */ -} AC_INTMODE_t; - -/* Interrupt level */ -typedef enum AC_INTLVL_enum -{ - AC_INTLVL_OFF_gc = (0x00<<4), /* Interrupt disabled */ - AC_INTLVL_LO_gc = (0x01<<4), /* Low level */ - AC_INTLVL_MED_gc = (0x02<<4), /* Medium level */ - AC_INTLVL_HI_gc = (0x03<<4), /* High level */ -} AC_INTLVL_t; - -/* Hysteresis mode selection */ -typedef enum AC_HYSMODE_enum -{ - AC_HYSMODE_NO_gc = (0x00<<1), /* No hysteresis */ - AC_HYSMODE_SMALL_gc = (0x01<<1), /* Small hysteresis */ - AC_HYSMODE_LARGE_gc = (0x02<<1), /* Large hysteresis */ -} AC_HYSMODE_t; - -/* Positive input multiplexer selection */ -typedef enum AC_MUXPOS_enum -{ - AC_MUXPOS_PIN0_gc = (0x00<<3), /* Pin 0 */ - AC_MUXPOS_PIN1_gc = (0x01<<3), /* Pin 1 */ - AC_MUXPOS_PIN2_gc = (0x02<<3), /* Pin 2 */ - AC_MUXPOS_PIN3_gc = (0x03<<3), /* Pin 3 */ - AC_MUXPOS_PIN4_gc = (0x04<<3), /* Pin 4 */ - AC_MUXPOS_PIN5_gc = (0x05<<3), /* Pin 5 */ - AC_MUXPOS_PIN6_gc = (0x06<<3), /* Pin 6 */ - AC_MUXPOS_DAC_gc = (0x07<<3), /* DAC output */ -} AC_MUXPOS_t; - -/* Negative input multiplexer selection */ -typedef enum AC_MUXNEG_enum -{ - AC_MUXNEG_PIN0_gc = (0x00<<0), /* Pin 0 */ - AC_MUXNEG_PIN1_gc = (0x01<<0), /* Pin 1 */ - AC_MUXNEG_PIN3_gc = (0x02<<0), /* Pin 3 */ - AC_MUXNEG_PIN5_gc = (0x03<<0), /* Pin 5 */ - AC_MUXNEG_PIN7_gc = (0x04<<0), /* Pin 7 */ - AC_MUXNEG_DAC_gc = (0x05<<0), /* DAC output */ - AC_MUXNEG_BANDGAP_gc = (0x06<<0), /* Bandgap Reference */ - AC_MUXNEG_SCALER_gc = (0x07<<0), /* Internal voltage scaler */ -} AC_MUXNEG_t; - -/* Windows interrupt mode */ -typedef enum AC_WINTMODE_enum -{ - AC_WINTMODE_ABOVE_gc = (0x00<<2), /* Interrupt on above window */ - AC_WINTMODE_INSIDE_gc = (0x01<<2), /* Interrupt on inside window */ - AC_WINTMODE_BELOW_gc = (0x02<<2), /* Interrupt on below window */ - AC_WINTMODE_OUTSIDE_gc = (0x03<<2), /* Interrupt on outside window */ -} AC_WINTMODE_t; - -/* Window interrupt level */ -typedef enum AC_WINTLVL_enum -{ - AC_WINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ - AC_WINTLVL_LO_gc = (0x01<<0), /* Low priority */ - AC_WINTLVL_MED_gc = (0x02<<0), /* Medium priority */ - AC_WINTLVL_HI_gc = (0x03<<0), /* High priority */ -} AC_WINTLVL_t; - -/* Window mode state */ -typedef enum AC_WSTATE_enum -{ - AC_WSTATE_ABOVE_gc = (0x00<<6), /* Signal above window */ - AC_WSTATE_INSIDE_gc = (0x01<<6), /* Signal inside window */ - AC_WSTATE_BELOW_gc = (0x02<<6), /* Signal below window */ -} AC_WSTATE_t; - - -/* --------------------------------------------------------------------------- -ADC - Analog/Digital Converter --------------------------------------------------------------------------- -*/ - -/* ADC Channel */ -typedef struct ADC_CH_struct -{ - register8_t CTRL; /* Control Register */ - register8_t MUXCTRL; /* MUX Control */ - register8_t INTCTRL; /* Channel Interrupt Control */ - register8_t INTFLAGS; /* Interrupt Flags */ - _WORDREGISTER(RES); /* Channel Result */ - register8_t reserved_0x6; - register8_t reserved_0x7; -} ADC_CH_t; - -/* --------------------------------------------------------------------------- -ADC - Analog/Digital Converter --------------------------------------------------------------------------- -*/ - -/* Analog-to-Digital Converter */ -typedef struct ADC_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t REFCTRL; /* Reference Control */ - register8_t EVCTRL; /* Event Control */ - register8_t PRESCALER; /* Clock Prescaler */ - register8_t reserved_0x05; - register8_t INTFLAGS; /* Interrupt Flags */ - register8_t reserved_0x07; - register8_t reserved_0x08; - register8_t reserved_0x09; - register8_t reserved_0x0A; - register8_t reserved_0x0B; - _WORDREGISTER(CAL); /* Calibration Value */ - register8_t reserved_0x0E; - register8_t reserved_0x0F; - _WORDREGISTER(CH0RES); /* Channel 0 Result */ - _WORDREGISTER(CH1RES); /* Channel 1 Result */ - _WORDREGISTER(CH2RES); /* Channel 2 Result */ - _WORDREGISTER(CH3RES); /* Channel 3 Result */ - _WORDREGISTER(CMP); /* Compare Value */ - register8_t reserved_0x1A; - register8_t reserved_0x1B; - register8_t reserved_0x1C; - register8_t reserved_0x1D; - register8_t reserved_0x1E; - register8_t reserved_0x1F; - ADC_CH_t CH0; /* ADC Channel 0 */ - ADC_CH_t CH1; /* ADC Channel 1 */ - ADC_CH_t CH2; /* ADC Channel 2 */ - ADC_CH_t CH3; /* ADC Channel 3 */ -} ADC_t; - -/* Positive input multiplexer selection */ -typedef enum ADC_CH_MUXPOS_enum -{ - ADC_CH_MUXPOS_PIN0_gc = (0x00<<3), /* Input pin 0 */ - ADC_CH_MUXPOS_PIN1_gc = (0x01<<3), /* Input pin 1 */ - ADC_CH_MUXPOS_PIN2_gc = (0x02<<3), /* Input pin 2 */ - ADC_CH_MUXPOS_PIN3_gc = (0x03<<3), /* Input pin 3 */ - ADC_CH_MUXPOS_PIN4_gc = (0x04<<3), /* Input pin 4 */ - ADC_CH_MUXPOS_PIN5_gc = (0x05<<3), /* Input pin 5 */ - ADC_CH_MUXPOS_PIN6_gc = (0x06<<3), /* Input pin 6 */ - ADC_CH_MUXPOS_PIN7_gc = (0x07<<3), /* Input pin 7 */ -} ADC_CH_MUXPOS_t; - -/* Internal input multiplexer selections */ -typedef enum ADC_CH_MUXINT_enum -{ - ADC_CH_MUXINT_TEMP_gc = (0x00<<3), /* Temperature Reference */ - ADC_CH_MUXINT_BANDGAP_gc = (0x01<<3), /* Bandgap Reference */ - ADC_CH_MUXINT_SCALEDVCC_gc = (0x02<<3), /* 1/10 scaled VCC */ - ADC_CH_MUXINT_DAC_gc = (0x03<<3), /* DAC output */ -} ADC_CH_MUXINT_t; - -/* Negative input multiplexer selection */ -typedef enum ADC_CH_MUXNEG_enum -{ - ADC_CH_MUXNEG_PIN0_gc = (0x00<<0), /* Input pin 0 */ - ADC_CH_MUXNEG_PIN1_gc = (0x01<<0), /* Input pin 1 */ - ADC_CH_MUXNEG_PIN2_gc = (0x02<<0), /* Input pin 2 */ - ADC_CH_MUXNEG_PIN3_gc = (0x03<<0), /* Input pin 3 */ - ADC_CH_MUXNEG_PIN4_gc = (0x04<<0), /* Input pin 4 */ - ADC_CH_MUXNEG_PIN5_gc = (0x05<<0), /* Input pin 5 */ - ADC_CH_MUXNEG_PIN6_gc = (0x06<<0), /* Input pin 6 */ - ADC_CH_MUXNEG_PIN7_gc = (0x07<<0), /* Input pin 7 */ -} ADC_CH_MUXNEG_t; - -/* Input mode */ -typedef enum ADC_CH_INPUTMODE_enum -{ - ADC_CH_INPUTMODE_INTERNAL_gc = (0x00<<0), /* Internal inputs, no gain */ - ADC_CH_INPUTMODE_SINGLEENDED_gc = (0x01<<0), /* Single-ended input, no gain */ - ADC_CH_INPUTMODE_DIFF_gc = (0x02<<0), /* Differential input, no gain */ - ADC_CH_INPUTMODE_DIFFWGAIN_gc = (0x03<<0), /* Differential input, with gain */ -} ADC_CH_INPUTMODE_t; - -/* Gain factor */ -typedef enum ADC_CH_GAIN_enum -{ - ADC_CH_GAIN_1X_gc = (0x00<<2), /* 1x gain */ - ADC_CH_GAIN_2X_gc = (0x01<<2), /* 2x gain */ - ADC_CH_GAIN_4X_gc = (0x02<<2), /* 4x gain */ - ADC_CH_GAIN_8X_gc = (0x03<<2), /* 8x gain */ - ADC_CH_GAIN_16X_gc = (0x04<<2), /* 16x gain */ - ADC_CH_GAIN_32X_gc = (0x05<<2), /* 32x gain */ - ADC_CH_GAIN_64X_gc = (0x06<<2), /* 64x gain */ -} ADC_CH_GAIN_t; - -/* Conversion result resolution */ -typedef enum ADC_RESOLUTION_enum -{ - ADC_RESOLUTION_12BIT_gc = (0x00<<1), /* 12-bit right-adjusted result */ - ADC_RESOLUTION_8BIT_gc = (0x02<<1), /* 8-bit right-adjusted result */ - ADC_RESOLUTION_LEFT12BIT_gc = (0x03<<1), /* 12-bit left-adjusted result */ -} ADC_RESOLUTION_t; - -/* Voltage reference selection */ -typedef enum ADC_REFSEL_enum -{ - ADC_REFSEL_INT1V_gc = (0x00<<4), /* Internal 1V */ - ADC_REFSEL_VCC_gc = (0x01<<4), /* Internal VCC / 1.6V */ - ADC_REFSEL_AREFA_gc = (0x02<<4), /* External reference on PORT A */ - ADC_REFSEL_AREFB_gc = (0x03<<4), /* External reference on PORT B */ -} ADC_REFSEL_t; - -/* Channel sweep selection */ -typedef enum ADC_SWEEP_enum -{ - ADC_SWEEP_0_gc = (0x00<<6), /* ADC Channel 0 */ - ADC_SWEEP_01_gc = (0x01<<6), /* ADC Channel 0,1 */ - ADC_SWEEP_012_gc = (0x02<<6), /* ADC Channel 0,1,2 */ - ADC_SWEEP_0123_gc = (0x03<<6), /* ADC Channel 0,1,2,3 */ -} ADC_SWEEP_t; - -/* Event channel input selection */ -typedef enum ADC_EVSEL_enum -{ - ADC_EVSEL_0123_gc = (0x00<<3), /* Event Channel 0,1,2,3 */ - ADC_EVSEL_1234_gc = (0x01<<3), /* Event Channel 1,2,3,4 */ - ADC_EVSEL_2345_gc = (0x02<<3), /* Event Channel 2,3,4,5 */ - ADC_EVSEL_3456_gc = (0x03<<3), /* Event Channel 3,4,5,6 */ - ADC_EVSEL_4567_gc = (0x04<<3), /* Event Channel 4,5,6,7 */ - ADC_EVSEL_567_gc = (0x05<<3), /* Event Channel 5,6,7 */ - ADC_EVSEL_67_gc = (0x06<<3), /* Event Channel 6,7 */ - ADC_EVSEL_7_gc = (0x07<<3), /* Event Channel 7 */ -} ADC_EVSEL_t; - -/* Event action selection */ -typedef enum ADC_EVACT_enum -{ - ADC_EVACT_NONE_gc = (0x00<<0), /* No event action */ - ADC_EVACT_CH0_gc = (0x01<<0), /* First event triggers channel 0 */ - ADC_EVACT_CH01_gc = (0x02<<0), /* First two events trigger channel 0,1 */ - ADC_EVACT_CH012_gc = (0x03<<0), /* First three events trigger channel 0,1,2 */ - ADC_EVACT_CH0123_gc = (0x04<<0), /* Events trigger channel 0,1,2,3 */ - ADC_EVACT_SWEEP_gc = (0x05<<0), /* First event triggers sweep */ - ADC_EVACT_SYNCHSWEEP_gc = (0x06<<0), /* First event triggers synchronized sweep */ -} ADC_EVACT_t; - -/* Interupt mode */ -typedef enum ADC_CH_INTMODE_enum -{ - ADC_CH_INTMODE_COMPLETE_gc = (0x00<<2), /* Interrupt on conversion complete */ - ADC_CH_INTMODE_BELOW_gc = (0x01<<2), /* Interrupt on result below compare value */ - ADC_CH_INTMODE_ABOVE_gc = (0x03<<2), /* Interrupt on result above compare value */ -} ADC_CH_INTMODE_t; - -/* Interrupt level */ -typedef enum ADC_CH_INTLVL_enum -{ - ADC_CH_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ - ADC_CH_INTLVL_LO_gc = (0x01<<0), /* Low level */ - ADC_CH_INTLVL_MED_gc = (0x02<<0), /* Medium level */ - ADC_CH_INTLVL_HI_gc = (0x03<<0), /* High level */ -} ADC_CH_INTLVL_t; - -/* DMA request selection */ -typedef enum ADC_DMASEL_enum -{ - ADC_DMASEL_OFF_gc = (0x00<<6), /* Combined DMA request OFF */ - ADC_DMASEL_CH01_gc = (0x01<<6), /* ADC Channel 0 or 1 */ - ADC_DMASEL_CH012_gc = (0x02<<6), /* ADC Channel 0 or 1 or 2 */ - ADC_DMASEL_CH0123_gc = (0x03<<6), /* ADC Channel 0 or 1 or 2 or 3 */ -} ADC_DMASEL_t; - -/* Clock prescaler */ -typedef enum ADC_PRESCALER_enum -{ - ADC_PRESCALER_DIV4_gc = (0x00<<0), /* Divide clock by 4 */ - ADC_PRESCALER_DIV8_gc = (0x01<<0), /* Divide clock by 8 */ - ADC_PRESCALER_DIV16_gc = (0x02<<0), /* Divide clock by 16 */ - ADC_PRESCALER_DIV32_gc = (0x03<<0), /* Divide clock by 32 */ - ADC_PRESCALER_DIV64_gc = (0x04<<0), /* Divide clock by 64 */ - ADC_PRESCALER_DIV128_gc = (0x05<<0), /* Divide clock by 128 */ - ADC_PRESCALER_DIV256_gc = (0x06<<0), /* Divide clock by 256 */ - ADC_PRESCALER_DIV512_gc = (0x07<<0), /* Divide clock by 512 */ -} ADC_PRESCALER_t; - - -/* --------------------------------------------------------------------------- -DAC - Digital/Analog Converter --------------------------------------------------------------------------- -*/ - -/* Digital-to-Analog Converter */ -typedef struct DAC_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t CTRLC; /* Control Register C */ - register8_t EVCTRL; /* Event Input Control */ - register8_t TIMCTRL; /* Timing Control */ - register8_t STATUS; /* Status */ - register8_t reserved_0x06; - register8_t reserved_0x07; - register8_t GAINCAL; /* Gain Calibration */ - register8_t OFFSETCAL; /* Offset Calibration */ - register8_t reserved_0x0A; - register8_t reserved_0x0B; - register8_t reserved_0x0C; - register8_t reserved_0x0D; - register8_t reserved_0x0E; - register8_t reserved_0x0F; - register8_t reserved_0x10; - register8_t reserved_0x11; - register8_t reserved_0x12; - register8_t reserved_0x13; - register8_t reserved_0x14; - register8_t reserved_0x15; - register8_t reserved_0x16; - register8_t reserved_0x17; - _WORDREGISTER(CH0DATA); /* Channel 0 Data */ - _WORDREGISTER(CH1DATA); /* Channel 1 Data */ -} DAC_t; - -/* Output channel selection */ -typedef enum DAC_CHSEL_enum -{ - DAC_CHSEL_SINGLE_gc = (0x00<<5), /* Single channel operation (Channel A only) */ - DAC_CHSEL_DUAL_gc = (0x02<<5), /* Dual channel operation (S/H on both channels) */ -} DAC_CHSEL_t; - -/* Reference voltage selection */ -typedef enum DAC_REFSEL_enum -{ - DAC_REFSEL_INT1V_gc = (0x00<<3), /* Internal 1V */ - DAC_REFSEL_AVCC_gc = (0x01<<3), /* Analog supply voltage */ - DAC_REFSEL_AREFA_gc = (0x02<<3), /* External reference on AREF on PORTA */ - DAC_REFSEL_AREFB_gc = (0x03<<3), /* External reference on AREF on PORTB */ -} DAC_REFSEL_t; - -/* Event channel selection */ -typedef enum DAC_EVSEL_enum -{ - DAC_EVSEL_0_gc = (0x00<<0), /* Event Channel 0 */ - DAC_EVSEL_1_gc = (0x01<<0), /* Event Channel 1 */ - DAC_EVSEL_2_gc = (0x02<<0), /* Event Channel 2 */ - DAC_EVSEL_3_gc = (0x03<<0), /* Event Channel 3 */ - DAC_EVSEL_4_gc = (0x04<<0), /* Event Channel 4 */ - DAC_EVSEL_5_gc = (0x05<<0), /* Event Channel 5 */ - DAC_EVSEL_6_gc = (0x06<<0), /* Event Channel 6 */ - DAC_EVSEL_7_gc = (0x07<<0), /* Event Channel 7 */ -} DAC_EVSEL_t; - -/* Conversion interval */ -typedef enum DAC_CONINTVAL_enum -{ - DAC_CONINTVAL_1CLK_gc = (0x00<<4), /* 1 CLK / 2 CLK in S/H mode */ - DAC_CONINTVAL_2CLK_gc = (0x01<<4), /* 2 CLK / 3 CLK in S/H mode */ - DAC_CONINTVAL_4CLK_gc = (0x02<<4), /* 4 CLK / 6 CLK in S/H mode */ - DAC_CONINTVAL_8CLK_gc = (0x03<<4), /* 8 CLK / 12 CLK in S/H mode */ - DAC_CONINTVAL_16CLK_gc = (0x04<<4), /* 16 CLK / 24 CLK in S/H mode */ - DAC_CONINTVAL_32CLK_gc = (0x05<<4), /* 32 CLK / 48 CLK in S/H mode */ - DAC_CONINTVAL_64CLK_gc = (0x06<<4), /* 64 CLK / 96 CLK in S/H mode */ - DAC_CONINTVAL_128CLK_gc = (0x07<<4), /* 128 CLK / 192 CLK in S/H mode */ -} DAC_CONINTVAL_t; - -/* Refresh rate */ -typedef enum DAC_REFRESH_enum -{ - DAC_REFRESH_16CLK_gc = (0x00<<0), /* 16 CLK */ - DAC_REFRESH_32CLK_gc = (0x01<<0), /* 32 CLK */ - DAC_REFRESH_64CLK_gc = (0x02<<0), /* 64 CLK */ - DAC_REFRESH_128CLK_gc = (0x03<<0), /* 128 CLK */ - DAC_REFRESH_256CLK_gc = (0x04<<0), /* 256 CLK */ - DAC_REFRESH_512CLK_gc = (0x05<<0), /* 512 CLK */ - DAC_REFRESH_1024CLK_gc = (0x06<<0), /* 1024 CLK */ - DAC_REFRESH_2048CLK_gc = (0x07<<0), /* 2048 CLK */ - DAC_REFRESH_4096CLK_gc = (0x08<<0), /* 4096 CLK */ - DAC_REFRESH_8192CLK_gc = (0x09<<0), /* 8192 CLK */ - DAC_REFRESH_16384CLK_gc = (0x0A<<0), /* 16384 CLK */ - DAC_REFRESH_32768CLK_gc = (0x0B<<0), /* 32768 CLK */ - DAC_REFRESH_65536CLK_gc = (0x0C<<0), /* 65536 CLK */ - DAC_REFRESH_OFF_gc = (0x0F<<0), /* Auto refresh OFF */ -} DAC_REFRESH_t; - - -/* --------------------------------------------------------------------------- -RTC - Real-Time Clounter --------------------------------------------------------------------------- -*/ - -/* Real-Time Counter */ -typedef struct RTC_struct -{ - register8_t CTRL; /* Control Register */ - register8_t STATUS; /* Status Register */ - register8_t INTCTRL; /* Interrupt Control Register */ - register8_t INTFLAGS; /* Interrupt Flags */ - register8_t TEMP; /* Temporary register */ - register8_t reserved_0x05; - register8_t reserved_0x06; - register8_t reserved_0x07; - _WORDREGISTER(CNT); /* Count Register */ - _WORDREGISTER(PER); /* Period Register */ - _WORDREGISTER(COMP); /* Compare Register */ -} RTC_t; - -/* Prescaler Factor */ -typedef enum RTC_PRESCALER_enum -{ - RTC_PRESCALER_OFF_gc = (0x00<<0), /* RTC Off */ - RTC_PRESCALER_DIV1_gc = (0x01<<0), /* RTC Clock */ - RTC_PRESCALER_DIV2_gc = (0x02<<0), /* RTC Clock / 2 */ - RTC_PRESCALER_DIV8_gc = (0x03<<0), /* RTC Clock / 8 */ - RTC_PRESCALER_DIV16_gc = (0x04<<0), /* RTC Clock / 16 */ - RTC_PRESCALER_DIV64_gc = (0x05<<0), /* RTC Clock / 64 */ - RTC_PRESCALER_DIV256_gc = (0x06<<0), /* RTC Clock / 256 */ - RTC_PRESCALER_DIV1024_gc = (0x07<<0), /* RTC Clock / 1024 */ -} RTC_PRESCALER_t; - -/* Compare Interrupt level */ -typedef enum RTC_COMPINTLVL_enum -{ - RTC_COMPINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ - RTC_COMPINTLVL_LO_gc = (0x01<<2), /* Low Level */ - RTC_COMPINTLVL_MED_gc = (0x02<<2), /* Medium Level */ - RTC_COMPINTLVL_HI_gc = (0x03<<2), /* High Level */ -} RTC_COMPINTLVL_t; - -/* Overflow Interrupt level */ -typedef enum RTC_OVFINTLVL_enum -{ - RTC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - RTC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ - RTC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ - RTC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ -} RTC_OVFINTLVL_t; - - -/* --------------------------------------------------------------------------- -EBI - External Bus Interface --------------------------------------------------------------------------- -*/ - -/* EBI Chip Select Module */ -typedef struct EBI_CS_struct -{ - register8_t CTRLA; /* Chip Select Control Register A */ - register8_t CTRLB; /* Chip Select Control Register B */ - _WORDREGISTER(BASEADDR); /* Chip Select Base Address */ -} EBI_CS_t; - -/* --------------------------------------------------------------------------- -EBI - External Bus Interface --------------------------------------------------------------------------- -*/ - -/* External Bus Interface */ -typedef struct EBI_struct -{ - register8_t CTRL; /* Control */ - register8_t SDRAMCTRLA; /* SDRAM Control Register A */ - register8_t reserved_0x02; - register8_t reserved_0x03; - _WORDREGISTER(REFRESH); /* SDRAM Refresh Period */ - _WORDREGISTER(INITDLY); /* SDRAM Initialization Delay */ - register8_t SDRAMCTRLB; /* SDRAM Control Register B */ - register8_t SDRAMCTRLC; /* SDRAM Control Register C */ - register8_t reserved_0x0A; - register8_t reserved_0x0B; - register8_t reserved_0x0C; - register8_t reserved_0x0D; - register8_t reserved_0x0E; - register8_t reserved_0x0F; - EBI_CS_t CS0; /* Chip Select 0 */ - EBI_CS_t CS1; /* Chip Select 1 */ - EBI_CS_t CS2; /* Chip Select 2 */ - EBI_CS_t CS3; /* Chip Select 3 */ -} EBI_t; - -/* Chip Select adress space */ -typedef enum EBI_CS_ASIZE_enum -{ - EBI_CS_ASIZE_256B_gc = (0x00<<2), /* 256 bytes */ - EBI_CS_ASIZE_512B_gc = (0x01<<2), /* 512 bytes */ - EBI_CS_ASIZE_1KB_gc = (0x02<<2), /* 1K bytes */ - EBI_CS_ASIZE_2KB_gc = (0x03<<2), /* 2K bytes */ - EBI_CS_ASIZE_4KB_gc = (0x04<<2), /* 4K bytes */ - EBI_CS_ASIZE_8KB_gc = (0x05<<2), /* 8K bytes */ - EBI_CS_ASIZE_16KB_gc = (0x06<<2), /* 16K bytes */ - EBI_CS_ASIZE_32KB_gc = (0x07<<2), /* 32K bytes */ - EBI_CS_ASIZE_64KB_gc = (0x08<<2), /* 64K bytes */ - EBI_CS_ASIZE_128KB_gc = (0x09<<2), /* 128K bytes */ - EBI_CS_ASIZE_256KB_gc = (0x0A<<2), /* 256K bytes */ - EBI_CS_ASIZE_512KB_gc = (0x0B<<2), /* 512K bytes */ - EBI_CS_ASIZE_1MB_gc = (0x0C<<2), /* 1M bytes */ - EBI_CS_ASIZE_2MB_gc = (0x0D<<2), /* 2M bytes */ - EBI_CS_ASIZE_4MB_gc = (0x0E<<2), /* 4M bytes */ - EBI_CS_ASIZE_8MB_gc = (0x0F<<2), /* 8M bytes */ - EBI_CS_ASIZE_16M_gc = (0x10<<2), /* 16M bytes */ -} EBI_CS_ASIZE_t; - -/* */ -typedef enum EBI_CS_SRWS_enum -{ - EBI_CS_SRWS_0CLK_gc = (0x00<<0), /* 0 cycles */ - EBI_CS_SRWS_1CLK_gc = (0x01<<0), /* 1 cycle */ - EBI_CS_SRWS_2CLK_gc = (0x02<<0), /* 2 cycles */ - EBI_CS_SRWS_3CLK_gc = (0x03<<0), /* 3 cycles */ - EBI_CS_SRWS_4CLK_gc = (0x04<<0), /* 4 cycles */ - EBI_CS_SRWS_5CLK_gc = (0x05<<0), /* 5 cycle */ - EBI_CS_SRWS_6CLK_gc = (0x06<<0), /* 6 cycles */ - EBI_CS_SRWS_7CLK_gc = (0x07<<0), /* 7 cycles */ -} EBI_CS_SRWS_t; - -/* Chip Select address mode */ -typedef enum EBI_CS_MODE_enum -{ - EBI_CS_MODE_DISABLED_gc = (0x00<<0), /* Chip Select Disabled */ - EBI_CS_MODE_SRAM_gc = (0x01<<0), /* Chip Select in SRAM mode */ - EBI_CS_MODE_LPC_gc = (0x02<<0), /* Chip Select in SRAM LPC mode */ - EBI_CS_MODE_SDRAM_gc = (0x03<<0), /* Chip Select in SDRAM mode */ -} EBI_CS_MODE_t; - -/* Chip Select SDRAM mode */ -typedef enum EBI_CS_SDMODE_enum -{ - EBI_CS_SDMODE_NORMAL_gc = (0x00<<0), /* Normal mode */ - EBI_CS_SDMODE_LOAD_gc = (0x01<<0), /* Load Mode Register command mode */ -} EBI_CS_SDMODE_t; - -/* */ -typedef enum EBI_SDDATAW_enum -{ - EBI_SDDATAW_4BIT_gc = (0x00<<6), /* 4-bit data bus */ - EBI_SDDATAW_8BIT_gc = (0x01<<6), /* 8-bit data bus */ -} EBI_SDDATAW_t; - -/* */ -typedef enum EBI_LPCMODE_enum -{ - EBI_LPCMODE_ALE1_gc = (0x00<<4), /* Data muxed with addr byte 0 */ - EBI_LPCMODE_ALE12_gc = (0x02<<4), /* Data muxed with addr byte 0 and 1 */ -} EBI_LPCMODE_t; - -/* */ -typedef enum EBI_SRMODE_enum -{ - EBI_SRMODE_ALE1_gc = (0x00<<2), /* Addr byte 0 muxed with 1 */ - EBI_SRMODE_ALE2_gc = (0x01<<2), /* Addr byte 0 muxed with 2 */ - EBI_SRMODE_ALE12_gc = (0x02<<2), /* Addr byte 0 muxed with 1 and 2 */ - EBI_SRMODE_NOALE_gc = (0x03<<2), /* No addr muxing */ -} EBI_SRMODE_t; - -/* */ -typedef enum EBI_IFMODE_enum -{ - EBI_IFMODE_DISABLED_gc = (0x00<<0), /* EBI Disabled */ - EBI_IFMODE_3PORT_gc = (0x01<<0), /* 3-port mode */ - EBI_IFMODE_4PORT_gc = (0x02<<0), /* 4-port mode */ - EBI_IFMODE_2PORT_gc = (0x03<<0), /* 2-port mode */ -} EBI_IFMODE_t; - -/* */ -typedef enum EBI_SDCOL_enum -{ - EBI_SDCOL_8BIT_gc = (0x00<<0), /* 8 column bits */ - EBI_SDCOL_9BIT_gc = (0x01<<0), /* 9 column bits */ - EBI_SDCOL_10BIT_gc = (0x02<<0), /* 10 column bits */ - EBI_SDCOL_11BIT_gc = (0x03<<0), /* 11 column bits */ -} EBI_SDCOL_t; - -/* */ -typedef enum EBI_MRDLY_enum -{ - EBI_MRDLY_0CLK_gc = (0x00<<6), /* 0 cycles */ - EBI_MRDLY_1CLK_gc = (0x01<<6), /* 1 cycle */ - EBI_MRDLY_2CLK_gc = (0x02<<6), /* 2 cycles */ - EBI_MRDLY_3CLK_gc = (0x03<<6), /* 3 cycles */ -} EBI_MRDLY_t; - -/* */ -typedef enum EBI_ROWCYCDLY_enum -{ - EBI_ROWCYCDLY_0CLK_gc = (0x00<<3), /* 0 cycles */ - EBI_ROWCYCDLY_1CLK_gc = (0x01<<3), /* 1 cycle */ - EBI_ROWCYCDLY_2CLK_gc = (0x02<<3), /* 2 cycles */ - EBI_ROWCYCDLY_3CLK_gc = (0x03<<3), /* 3 cycles */ - EBI_ROWCYCDLY_4CLK_gc = (0x04<<3), /* 4 cycles */ - EBI_ROWCYCDLY_5CLK_gc = (0x05<<3), /* 5 cycle */ - EBI_ROWCYCDLY_6CLK_gc = (0x06<<3), /* 6 cycles */ - EBI_ROWCYCDLY_7CLK_gc = (0x07<<3), /* 7 cycles */ -} EBI_ROWCYCDLY_t; - -/* */ -typedef enum EBI_RPDLY_enum -{ - EBI_RPDLY_0CLK_gc = (0x00<<0), /* 0 cycles */ - EBI_RPDLY_1CLK_gc = (0x01<<0), /* 1 cycle */ - EBI_RPDLY_2CLK_gc = (0x02<<0), /* 2 cycles */ - EBI_RPDLY_3CLK_gc = (0x03<<0), /* 3 cycles */ - EBI_RPDLY_4CLK_gc = (0x04<<0), /* 4 cycles */ - EBI_RPDLY_5CLK_gc = (0x05<<0), /* 5 cycle */ - EBI_RPDLY_6CLK_gc = (0x06<<0), /* 6 cycles */ - EBI_RPDLY_7CLK_gc = (0x07<<0), /* 7 cycles */ -} EBI_RPDLY_t; - -/* */ -typedef enum EBI_WRDLY_enum -{ - EBI_WRDLY_0CLK_gc = (0x00<<6), /* 0 cycles */ - EBI_WRDLY_1CLK_gc = (0x01<<6), /* 1 cycle */ - EBI_WRDLY_2CLK_gc = (0x02<<6), /* 2 cycles */ - EBI_WRDLY_3CLK_gc = (0x03<<6), /* 3 cycles */ -} EBI_WRDLY_t; - -/* */ -typedef enum EBI_ESRDLY_enum -{ - EBI_ESRDLY_0CLK_gc = (0x00<<3), /* 0 cycles */ - EBI_ESRDLY_1CLK_gc = (0x01<<3), /* 1 cycle */ - EBI_ESRDLY_2CLK_gc = (0x02<<3), /* 2 cycles */ - EBI_ESRDLY_3CLK_gc = (0x03<<3), /* 3 cycles */ - EBI_ESRDLY_4CLK_gc = (0x04<<3), /* 4 cycles */ - EBI_ESRDLY_5CLK_gc = (0x05<<3), /* 5 cycle */ - EBI_ESRDLY_6CLK_gc = (0x06<<3), /* 6 cycles */ - EBI_ESRDLY_7CLK_gc = (0x07<<3), /* 7 cycles */ -} EBI_ESRDLY_t; - -/* */ -typedef enum EBI_ROWCOLDLY_enum -{ - EBI_ROWCOLDLY_0CLK_gc = (0x00<<0), /* 0 cycles */ - EBI_ROWCOLDLY_1CLK_gc = (0x01<<0), /* 1 cycle */ - EBI_ROWCOLDLY_2CLK_gc = (0x02<<0), /* 2 cycles */ - EBI_ROWCOLDLY_3CLK_gc = (0x03<<0), /* 3 cycles */ - EBI_ROWCOLDLY_4CLK_gc = (0x04<<0), /* 4 cycles */ - EBI_ROWCOLDLY_5CLK_gc = (0x05<<0), /* 5 cycle */ - EBI_ROWCOLDLY_6CLK_gc = (0x06<<0), /* 6 cycles */ - EBI_ROWCOLDLY_7CLK_gc = (0x07<<0), /* 7 cycles */ -} EBI_ROWCOLDLY_t; - - -/* --------------------------------------------------------------------------- -TWI - Two-Wire Interface --------------------------------------------------------------------------- -*/ - -/* */ -typedef struct TWI_MASTER_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t CTRLC; /* Control Register C */ - register8_t STATUS; /* Status Register */ - register8_t BAUD; /* Baurd Rate Control Register */ - register8_t ADDR; /* Address Register */ - register8_t DATA; /* Data Register */ -} TWI_MASTER_t; - -/* --------------------------------------------------------------------------- -TWI - Two-Wire Interface --------------------------------------------------------------------------- -*/ - -/* */ -typedef struct TWI_SLAVE_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t STATUS; /* Status Register */ - register8_t ADDR; /* Address Register */ - register8_t DATA; /* Data Register */ - register8_t ADDRMASK; /* Address Mask Register */ -} TWI_SLAVE_t; - -/* --------------------------------------------------------------------------- -TWI - Two-Wire Interface --------------------------------------------------------------------------- -*/ - -/* Two-Wire Interface */ -typedef struct TWI_struct -{ - register8_t CTRL; /* TWI Common Control Register */ - TWI_MASTER_t MASTER; /* TWI master module */ - TWI_SLAVE_t SLAVE; /* TWI slave module */ -} TWI_t; - -/* Master Interrupt Level */ -typedef enum TWI_MASTER_INTLVL_enum -{ - TWI_MASTER_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ - TWI_MASTER_INTLVL_LO_gc = (0x01<<6), /* Low Level */ - TWI_MASTER_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ - TWI_MASTER_INTLVL_HI_gc = (0x03<<6), /* High Level */ -} TWI_MASTER_INTLVL_t; - -/* Inactive Timeout */ -typedef enum TWI_MASTER_TIMEOUT_enum -{ - TWI_MASTER_TIMEOUT_DISABLED_gc = (0x00<<2), /* Bus Timeout Disabled */ - TWI_MASTER_TIMEOUT_50US_gc = (0x01<<2), /* 50 Microseconds */ - TWI_MASTER_TIMEOUT_100US_gc = (0x02<<2), /* 100 Microseconds */ - TWI_MASTER_TIMEOUT_200US_gc = (0x03<<2), /* 200 Microseconds */ -} TWI_MASTER_TIMEOUT_t; - -/* Master Command */ -typedef enum TWI_MASTER_CMD_enum -{ - TWI_MASTER_CMD_NOACT_gc = (0x00<<0), /* No Action */ - TWI_MASTER_CMD_REPSTART_gc = (0x01<<0), /* Issue Repeated Start Condition */ - TWI_MASTER_CMD_RECVTRANS_gc = (0x02<<0), /* Receive or Transmit Data */ - TWI_MASTER_CMD_STOP_gc = (0x03<<0), /* Issue Stop Condition */ -} TWI_MASTER_CMD_t; - -/* Master Bus State */ -typedef enum TWI_MASTER_BUSSTATE_enum -{ - TWI_MASTER_BUSSTATE_UNKNOWN_gc = (0x00<<0), /* Unknown Bus State */ - TWI_MASTER_BUSSTATE_IDLE_gc = (0x01<<0), /* Bus is Idle */ - TWI_MASTER_BUSSTATE_OWNER_gc = (0x02<<0), /* This Module Controls The Bus */ - TWI_MASTER_BUSSTATE_BUSY_gc = (0x03<<0), /* The Bus is Busy */ -} TWI_MASTER_BUSSTATE_t; - -/* Slave Interrupt Level */ -typedef enum TWI_SLAVE_INTLVL_enum -{ - TWI_SLAVE_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ - TWI_SLAVE_INTLVL_LO_gc = (0x01<<6), /* Low Level */ - TWI_SLAVE_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ - TWI_SLAVE_INTLVL_HI_gc = (0x03<<6), /* High Level */ -} TWI_SLAVE_INTLVL_t; - -/* Slave Command */ -typedef enum TWI_SLAVE_CMD_enum -{ - TWI_SLAVE_CMD_NOACT_gc = (0x00<<0), /* No Action */ - TWI_SLAVE_CMD_COMPTRANS_gc = (0x02<<0), /* Used To Complete a Transaction */ - TWI_SLAVE_CMD_RESPONSE_gc = (0x03<<0), /* Used in Response to Address/Data Interrupt */ -} TWI_SLAVE_CMD_t; - - -/* --------------------------------------------------------------------------- -PORT - Port Configuration --------------------------------------------------------------------------- -*/ - -/* I/O port Configuration */ -typedef struct PORTCFG_struct -{ - register8_t MPCMASK; /* Multi-pin Configuration Mask */ - register8_t reserved_0x01; - register8_t VPCTRLA; /* Virtual Port Control Register A */ - register8_t VPCTRLB; /* Virtual Port Control Register B */ - register8_t CLKEVOUT; /* Clock and Event Out Register */ -} PORTCFG_t; - -/* --------------------------------------------------------------------------- -PORT - Port Configuration --------------------------------------------------------------------------- -*/ - -/* Virtual Port */ -typedef struct VPORT_struct -{ - register8_t DIR; /* I/O Port Data Direction */ - register8_t OUT; /* I/O Port Output */ - register8_t IN; /* I/O Port Input */ - register8_t INTFLAGS; /* Interrupt Flag Register */ -} VPORT_t; - -/* --------------------------------------------------------------------------- -PORT - Port Configuration --------------------------------------------------------------------------- -*/ - -/* I/O Ports */ -typedef struct PORT_struct -{ - register8_t DIR; /* I/O Port Data Direction */ - register8_t DIRSET; /* I/O Port Data Direction Set */ - register8_t DIRCLR; /* I/O Port Data Direction Clear */ - register8_t DIRTGL; /* I/O Port Data Direction Toggle */ - register8_t OUT; /* I/O Port Output */ - register8_t OUTSET; /* I/O Port Output Set */ - register8_t OUTCLR; /* I/O Port Output Clear */ - register8_t OUTTGL; /* I/O Port Output Toggle */ - register8_t IN; /* I/O port Input */ - register8_t INTCTRL; /* Interrupt Control Register */ - register8_t INT0MASK; /* Port Interrupt 0 Mask */ - register8_t INT1MASK; /* Port Interrupt 1 Mask */ - register8_t INTFLAGS; /* Interrupt Flag Register */ - register8_t reserved_0x0D; - register8_t reserved_0x0E; - register8_t reserved_0x0F; - register8_t PIN0CTRL; /* Pin 0 Control Register */ - register8_t PIN1CTRL; /* Pin 1 Control Register */ - register8_t PIN2CTRL; /* Pin 2 Control Register */ - register8_t PIN3CTRL; /* Pin 3 Control Register */ - register8_t PIN4CTRL; /* Pin 4 Control Register */ - register8_t PIN5CTRL; /* Pin 5 Control Register */ - register8_t PIN6CTRL; /* Pin 6 Control Register */ - register8_t PIN7CTRL; /* Pin 7 Control Register */ -} PORT_t; - -/* Virtual Port 0 Mapping */ -typedef enum PORTCFG_VP0MAP_enum -{ - PORTCFG_VP0MAP_PORTA_gc = (0x00<<0), /* Mapped To PORTA */ - PORTCFG_VP0MAP_PORTB_gc = (0x01<<0), /* Mapped To PORTB */ - PORTCFG_VP0MAP_PORTC_gc = (0x02<<0), /* Mapped To PORTC */ - PORTCFG_VP0MAP_PORTD_gc = (0x03<<0), /* Mapped To PORTD */ - PORTCFG_VP0MAP_PORTE_gc = (0x04<<0), /* Mapped To PORTE */ - PORTCFG_VP0MAP_PORTF_gc = (0x05<<0), /* Mapped To PORTF */ - PORTCFG_VP0MAP_PORTG_gc = (0x06<<0), /* Mapped To PORTG */ - PORTCFG_VP0MAP_PORTH_gc = (0x07<<0), /* Mapped To PORTH */ - PORTCFG_VP0MAP_PORTJ_gc = (0x08<<0), /* Mapped To PORTJ */ - PORTCFG_VP0MAP_PORTK_gc = (0x09<<0), /* Mapped To PORTK */ - PORTCFG_VP0MAP_PORTL_gc = (0x0A<<0), /* Mapped To PORTL */ - PORTCFG_VP0MAP_PORTM_gc = (0x0B<<0), /* Mapped To PORTM */ - PORTCFG_VP0MAP_PORTN_gc = (0x0C<<0), /* Mapped To PORTN */ - PORTCFG_VP0MAP_PORTP_gc = (0x0D<<0), /* Mapped To PORTP */ - PORTCFG_VP0MAP_PORTQ_gc = (0x0E<<0), /* Mapped To PORTQ */ - PORTCFG_VP0MAP_PORTR_gc = (0x0F<<0), /* Mapped To PORTR */ -} PORTCFG_VP0MAP_t; - -/* Virtual Port 1 Mapping */ -typedef enum PORTCFG_VP1MAP_enum -{ - PORTCFG_VP1MAP_PORTA_gc = (0x00<<4), /* Mapped To PORTA */ - PORTCFG_VP1MAP_PORTB_gc = (0x01<<4), /* Mapped To PORTB */ - PORTCFG_VP1MAP_PORTC_gc = (0x02<<4), /* Mapped To PORTC */ - PORTCFG_VP1MAP_PORTD_gc = (0x03<<4), /* Mapped To PORTD */ - PORTCFG_VP1MAP_PORTE_gc = (0x04<<4), /* Mapped To PORTE */ - PORTCFG_VP1MAP_PORTF_gc = (0x05<<4), /* Mapped To PORTF */ - PORTCFG_VP1MAP_PORTG_gc = (0x06<<4), /* Mapped To PORTG */ - PORTCFG_VP1MAP_PORTH_gc = (0x07<<4), /* Mapped To PORTH */ - PORTCFG_VP1MAP_PORTJ_gc = (0x08<<4), /* Mapped To PORTJ */ - PORTCFG_VP1MAP_PORTK_gc = (0x09<<4), /* Mapped To PORTK */ - PORTCFG_VP1MAP_PORTL_gc = (0x0A<<4), /* Mapped To PORTL */ - PORTCFG_VP1MAP_PORTM_gc = (0x0B<<4), /* Mapped To PORTM */ - PORTCFG_VP1MAP_PORTN_gc = (0x0C<<4), /* Mapped To PORTN */ - PORTCFG_VP1MAP_PORTP_gc = (0x0D<<4), /* Mapped To PORTP */ - PORTCFG_VP1MAP_PORTQ_gc = (0x0E<<4), /* Mapped To PORTQ */ - PORTCFG_VP1MAP_PORTR_gc = (0x0F<<4), /* Mapped To PORTR */ -} PORTCFG_VP1MAP_t; - -/* Virtual Port 2 Mapping */ -typedef enum PORTCFG_VP2MAP_enum -{ - PORTCFG_VP2MAP_PORTA_gc = (0x00<<0), /* Mapped To PORTA */ - PORTCFG_VP2MAP_PORTB_gc = (0x01<<0), /* Mapped To PORTB */ - PORTCFG_VP2MAP_PORTC_gc = (0x02<<0), /* Mapped To PORTC */ - PORTCFG_VP2MAP_PORTD_gc = (0x03<<0), /* Mapped To PORTD */ - PORTCFG_VP2MAP_PORTE_gc = (0x04<<0), /* Mapped To PORTE */ - PORTCFG_VP2MAP_PORTF_gc = (0x05<<0), /* Mapped To PORTF */ - PORTCFG_VP2MAP_PORTG_gc = (0x06<<0), /* Mapped To PORTG */ - PORTCFG_VP2MAP_PORTH_gc = (0x07<<0), /* Mapped To PORTH */ - PORTCFG_VP2MAP_PORTJ_gc = (0x08<<0), /* Mapped To PORTJ */ - PORTCFG_VP2MAP_PORTK_gc = (0x09<<0), /* Mapped To PORTK */ - PORTCFG_VP2MAP_PORTL_gc = (0x0A<<0), /* Mapped To PORTL */ - PORTCFG_VP2MAP_PORTM_gc = (0x0B<<0), /* Mapped To PORTM */ - PORTCFG_VP2MAP_PORTN_gc = (0x0C<<0), /* Mapped To PORTN */ - PORTCFG_VP2MAP_PORTP_gc = (0x0D<<0), /* Mapped To PORTP */ - PORTCFG_VP2MAP_PORTQ_gc = (0x0E<<0), /* Mapped To PORTQ */ - PORTCFG_VP2MAP_PORTR_gc = (0x0F<<0), /* Mapped To PORTR */ -} PORTCFG_VP2MAP_t; - -/* Virtual Port 3 Mapping */ -typedef enum PORTCFG_VP3MAP_enum -{ - PORTCFG_VP3MAP_PORTA_gc = (0x00<<4), /* Mapped To PORTA */ - PORTCFG_VP3MAP_PORTB_gc = (0x01<<4), /* Mapped To PORTB */ - PORTCFG_VP3MAP_PORTC_gc = (0x02<<4), /* Mapped To PORTC */ - PORTCFG_VP3MAP_PORTD_gc = (0x03<<4), /* Mapped To PORTD */ - PORTCFG_VP3MAP_PORTE_gc = (0x04<<4), /* Mapped To PORTE */ - PORTCFG_VP3MAP_PORTF_gc = (0x05<<4), /* Mapped To PORTF */ - PORTCFG_VP3MAP_PORTG_gc = (0x06<<4), /* Mapped To PORTG */ - PORTCFG_VP3MAP_PORTH_gc = (0x07<<4), /* Mapped To PORTH */ - PORTCFG_VP3MAP_PORTJ_gc = (0x08<<4), /* Mapped To PORTJ */ - PORTCFG_VP3MAP_PORTK_gc = (0x09<<4), /* Mapped To PORTK */ - PORTCFG_VP3MAP_PORTL_gc = (0x0A<<4), /* Mapped To PORTL */ - PORTCFG_VP3MAP_PORTM_gc = (0x0B<<4), /* Mapped To PORTM */ - PORTCFG_VP3MAP_PORTN_gc = (0x0C<<4), /* Mapped To PORTN */ - PORTCFG_VP3MAP_PORTP_gc = (0x0D<<4), /* Mapped To PORTP */ - PORTCFG_VP3MAP_PORTQ_gc = (0x0E<<4), /* Mapped To PORTQ */ - PORTCFG_VP3MAP_PORTR_gc = (0x0F<<4), /* Mapped To PORTR */ -} PORTCFG_VP3MAP_t; - -/* Clock Output Port */ -typedef enum PORTCFG_CLKOUT_enum -{ - PORTCFG_CLKOUT_OFF_gc = (0x00<<0), /* Clock Output Disabled */ - PORTCFG_CLKOUT_PC7_gc = (0x01<<0), /* Clock Output on Port C pin 7 */ - PORTCFG_CLKOUT_PD7_gc = (0x02<<0), /* Clock Output on Port D pin 7 */ - PORTCFG_CLKOUT_PE7_gc = (0x03<<0), /* Clock Output on Port E pin 7 */ -} PORTCFG_CLKOUT_t; - -/* Event Output Port */ -typedef enum PORTCFG_EVOUT_enum -{ - PORTCFG_EVOUT_OFF_gc = (0x00<<4), /* Event Output Disabled */ - PORTCFG_EVOUT_PC7_gc = (0x01<<4), /* Event Channel 7 Output on Port C pin 7 */ - PORTCFG_EVOUT_PD7_gc = (0x02<<4), /* Event Channel 7 Output on Port D pin 7 */ - PORTCFG_EVOUT_PE7_gc = (0x03<<4), /* Event Channel 7 Output on Port E pin 7 */ -} PORTCFG_EVOUT_t; - -/* Port Interrupt 0 Level */ -typedef enum PORT_INT0LVL_enum -{ - PORT_INT0LVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - PORT_INT0LVL_LO_gc = (0x01<<0), /* Low Level */ - PORT_INT0LVL_MED_gc = (0x02<<0), /* Medium Level */ - PORT_INT0LVL_HI_gc = (0x03<<0), /* High Level */ -} PORT_INT0LVL_t; - -/* Port Interrupt 1 Level */ -typedef enum PORT_INT1LVL_enum -{ - PORT_INT1LVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ - PORT_INT1LVL_LO_gc = (0x01<<2), /* Low Level */ - PORT_INT1LVL_MED_gc = (0x02<<2), /* Medium Level */ - PORT_INT1LVL_HI_gc = (0x03<<2), /* High Level */ -} PORT_INT1LVL_t; - -/* Output/Pull Configuration */ -typedef enum PORT_OPC_enum -{ - PORT_OPC_TOTEM_gc = (0x00<<3), /* Totempole */ - PORT_OPC_BUSKEEPER_gc = (0x01<<3), /* Totempole w/ Bus keeper on Input and Output */ - PORT_OPC_PULLDOWN_gc = (0x02<<3), /* Totempole w/ Pull-down on Input */ - PORT_OPC_PULLUP_gc = (0x03<<3), /* Totempole w/ Pull-up on Input */ - PORT_OPC_WIREDOR_gc = (0x04<<3), /* Wired OR */ - PORT_OPC_WIREDAND_gc = (0x05<<3), /* Wired AND */ - PORT_OPC_WIREDORPULL_gc = (0x06<<3), /* Wired OR w/ Pull-down */ - PORT_OPC_WIREDANDPULL_gc = (0x07<<3), /* Wired AND w/ Pull-up */ -} PORT_OPC_t; - -/* Input/Sense Configuration */ -typedef enum PORT_ISC_enum -{ - PORT_ISC_BOTHEDGES_gc = (0x00<<0), /* Sense Both Edges */ - PORT_ISC_RISING_gc = (0x01<<0), /* Sense Rising Edge */ - PORT_ISC_FALLING_gc = (0x02<<0), /* Sense Falling Edge */ - PORT_ISC_LEVEL_gc = (0x03<<0), /* Sense Level (Transparent For Events) */ - PORT_ISC_INPUT_DISABLE_gc = (0x07<<0), /* Disable Digital Input Buffer */ -} PORT_ISC_t; - - -/* --------------------------------------------------------------------------- -TC - 16-bit Timer/Counter With PWM --------------------------------------------------------------------------- -*/ - -/* 16-bit Timer/Counter 0 */ -typedef struct TC0_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t CTRLC; /* Control register C */ - register8_t CTRLD; /* Control Register D */ - register8_t CTRLE; /* Control Register E */ - register8_t reserved_0x05; - register8_t INTCTRLA; /* Interrupt Control Register A */ - register8_t INTCTRLB; /* Interrupt Control Register B */ - register8_t CTRLFCLR; /* Control Register F Clear */ - register8_t CTRLFSET; /* Control Register F Set */ - register8_t CTRLGCLR; /* Control Register G Clear */ - register8_t CTRLGSET; /* Control Register G Set */ - register8_t INTFLAGS; /* Interrupt Flag Register */ - register8_t reserved_0x0D; - register8_t reserved_0x0E; - register8_t TEMP; /* Temporary Register For 16-bit Access */ - register8_t reserved_0x10; - register8_t reserved_0x11; - register8_t reserved_0x12; - register8_t reserved_0x13; - register8_t reserved_0x14; - register8_t reserved_0x15; - register8_t reserved_0x16; - register8_t reserved_0x17; - register8_t reserved_0x18; - register8_t reserved_0x19; - register8_t reserved_0x1A; - register8_t reserved_0x1B; - register8_t reserved_0x1C; - register8_t reserved_0x1D; - register8_t reserved_0x1E; - register8_t reserved_0x1F; - _WORDREGISTER(CNT); /* Count */ - register8_t reserved_0x22; - register8_t reserved_0x23; - register8_t reserved_0x24; - register8_t reserved_0x25; - _WORDREGISTER(PER); /* Period */ - _WORDREGISTER(CCA); /* Compare or Capture A */ - _WORDREGISTER(CCB); /* Compare or Capture B */ - _WORDREGISTER(CCC); /* Compare or Capture C */ - _WORDREGISTER(CCD); /* Compare or Capture D */ - register8_t reserved_0x30; - register8_t reserved_0x31; - register8_t reserved_0x32; - register8_t reserved_0x33; - register8_t reserved_0x34; - register8_t reserved_0x35; - _WORDREGISTER(PERBUF); /* Period Buffer */ - _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ - _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ - _WORDREGISTER(CCCBUF); /* Compare Or Capture C Buffer */ - _WORDREGISTER(CCDBUF); /* Compare Or Capture D Buffer */ -} TC0_t; - -/* --------------------------------------------------------------------------- -TC - 16-bit Timer/Counter With PWM --------------------------------------------------------------------------- -*/ - -/* 16-bit Timer/Counter 1 */ -typedef struct TC1_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t CTRLC; /* Control register C */ - register8_t CTRLD; /* Control Register D */ - register8_t CTRLE; /* Control Register E */ - register8_t reserved_0x05; - register8_t INTCTRLA; /* Interrupt Control Register A */ - register8_t INTCTRLB; /* Interrupt Control Register B */ - register8_t CTRLFCLR; /* Control Register F Clear */ - register8_t CTRLFSET; /* Control Register F Set */ - register8_t CTRLGCLR; /* Control Register G Clear */ - register8_t CTRLGSET; /* Control Register G Set */ - register8_t INTFLAGS; /* Interrupt Flag Register */ - register8_t reserved_0x0D; - register8_t reserved_0x0E; - register8_t TEMP; /* Temporary Register For 16-bit Access */ - register8_t reserved_0x10; - register8_t reserved_0x11; - register8_t reserved_0x12; - register8_t reserved_0x13; - register8_t reserved_0x14; - register8_t reserved_0x15; - register8_t reserved_0x16; - register8_t reserved_0x17; - register8_t reserved_0x18; - register8_t reserved_0x19; - register8_t reserved_0x1A; - register8_t reserved_0x1B; - register8_t reserved_0x1C; - register8_t reserved_0x1D; - register8_t reserved_0x1E; - register8_t reserved_0x1F; - _WORDREGISTER(CNT); /* Count */ - register8_t reserved_0x22; - register8_t reserved_0x23; - register8_t reserved_0x24; - register8_t reserved_0x25; - _WORDREGISTER(PER); /* Period */ - _WORDREGISTER(CCA); /* Compare or Capture A */ - _WORDREGISTER(CCB); /* Compare or Capture B */ - register8_t reserved_0x2C; - register8_t reserved_0x2D; - register8_t reserved_0x2E; - register8_t reserved_0x2F; - register8_t reserved_0x30; - register8_t reserved_0x31; - register8_t reserved_0x32; - register8_t reserved_0x33; - register8_t reserved_0x34; - register8_t reserved_0x35; - _WORDREGISTER(PERBUF); /* Period Buffer */ - _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ - _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ -} TC1_t; - -/* --------------------------------------------------------------------------- -TC - 16-bit Timer/Counter With PWM --------------------------------------------------------------------------- -*/ - -/* Advanced Waveform Extension */ -typedef struct AWEX_struct -{ - register8_t CTRL; /* Control Register */ - register8_t reserved_0x01; - register8_t FDEMASK; /* Fault Detection Event Mask */ - register8_t FDCTRL; /* Fault Detection Control Register */ - register8_t STATUS; /* Status Register */ - register8_t reserved_0x05; - register8_t DTBOTH; /* Dead Time Both Sides */ - register8_t DTBOTHBUF; /* Dead Time Both Sides Buffer */ - register8_t DTLS; /* Dead Time Low Side */ - register8_t DTHS; /* Dead Time High Side */ - register8_t DTLSBUF; /* Dead Time Low Side Buffer */ - register8_t DTHSBUF; /* Dead Time High Side Buffer */ - register8_t OUTOVEN; /* Output Override Enable */ -} AWEX_t; - -/* --------------------------------------------------------------------------- -TC - 16-bit Timer/Counter With PWM --------------------------------------------------------------------------- -*/ - -/* High-Resolution Extension */ -typedef struct HIRES_struct -{ - register8_t CTRLA; /* Control Register */ -} HIRES_t; - -/* Clock Selection */ -typedef enum TC_CLKSEL_enum -{ - TC_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */ - TC_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */ - TC_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */ - TC_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */ - TC_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */ - TC_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */ - TC_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */ - TC_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */ - TC_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */ - TC_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */ - TC_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */ - TC_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */ - TC_CLKSEL_EVCH4_gc = (0x0C<<0), /* Event Channel 4 */ - TC_CLKSEL_EVCH5_gc = (0x0D<<0), /* Event Channel 5 */ - TC_CLKSEL_EVCH6_gc = (0x0E<<0), /* Event Channel 6 */ - TC_CLKSEL_EVCH7_gc = (0x0F<<0), /* Event Channel 7 */ -} TC_CLKSEL_t; - -/* Waveform Generation Mode */ -typedef enum TC_WGMODE_enum -{ - TC_WGMODE_NORMAL_gc = (0x00<<0), /* Normal Mode */ - TC_WGMODE_FRQ_gc = (0x01<<0), /* Frequency Generation Mode */ - TC_WGMODE_SS_gc = (0x03<<0), /* Single Slope */ - TC_WGMODE_DS_T_gc = (0x05<<0), /* Dual Slope, Update on TOP */ - TC_WGMODE_DS_TB_gc = (0x06<<0), /* Dual Slope, Update on TOP and BOTTOM */ - TC_WGMODE_DS_B_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */ -} TC_WGMODE_t; - -/* Event Action */ -typedef enum TC_EVACT_enum -{ - TC_EVACT_OFF_gc = (0x00<<5), /* No Event Action */ - TC_EVACT_CAPT_gc = (0x01<<5), /* Input Capture */ - TC_EVACT_UPDOWN_gc = (0x02<<5), /* Externally Controlled Up/Down Count */ - TC_EVACT_QDEC_gc = (0x03<<5), /* Quadrature Decode */ - TC_EVACT_RESTART_gc = (0x04<<5), /* Restart */ - TC_EVACT_FRQ_gc = (0x05<<5), /* Frequency Capture */ - TC_EVACT_FRW_gc = (0x05<<5), /* Frequency Capture (typo in earlier header file) */ - TC_EVACT_PW_gc = (0x06<<5), /* Pulse-width Capture */ -} TC_EVACT_t; - -/* Event Selection */ -typedef enum TC_EVSEL_enum -{ - TC_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ - TC_EVSEL_CH0_gc = (0x08<<0), /* Event Channel 0 */ - TC_EVSEL_CH1_gc = (0x09<<0), /* Event Channel 1 */ - TC_EVSEL_CH2_gc = (0x0A<<0), /* Event Channel 2 */ - TC_EVSEL_CH3_gc = (0x0B<<0), /* Event Channel 3 */ - TC_EVSEL_CH4_gc = (0x0C<<0), /* Event Channel 4 */ - TC_EVSEL_CH5_gc = (0x0D<<0), /* Event Channel 5 */ - TC_EVSEL_CH6_gc = (0x0E<<0), /* Event Channel 6 */ - TC_EVSEL_CH7_gc = (0x0F<<0), /* Event Channel 7 */ -} TC_EVSEL_t; - -/* Error Interrupt Level */ -typedef enum TC_ERRINTLVL_enum -{ - TC_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ - TC_ERRINTLVL_LO_gc = (0x01<<2), /* Low Level */ - TC_ERRINTLVL_MED_gc = (0x02<<2), /* Medium Level */ - TC_ERRINTLVL_HI_gc = (0x03<<2), /* High Level */ -} TC_ERRINTLVL_t; - -/* Overflow Interrupt Level */ -typedef enum TC_OVFINTLVL_enum -{ - TC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - TC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ - TC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ - TC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ -} TC_OVFINTLVL_t; - -/* Compare or Capture D Interrupt Level */ -typedef enum TC_CCDINTLVL_enum -{ - TC_CCDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ - TC_CCDINTLVL_LO_gc = (0x01<<6), /* Low Level */ - TC_CCDINTLVL_MED_gc = (0x02<<6), /* Medium Level */ - TC_CCDINTLVL_HI_gc = (0x03<<6), /* High Level */ -} TC_CCDINTLVL_t; - -/* Compare or Capture C Interrupt Level */ -typedef enum TC_CCCINTLVL_enum -{ - TC_CCCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ - TC_CCCINTLVL_LO_gc = (0x01<<4), /* Low Level */ - TC_CCCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ - TC_CCCINTLVL_HI_gc = (0x03<<4), /* High Level */ -} TC_CCCINTLVL_t; - -/* Compare or Capture B Interrupt Level */ -typedef enum TC_CCBINTLVL_enum -{ - TC_CCBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ - TC_CCBINTLVL_LO_gc = (0x01<<2), /* Low Level */ - TC_CCBINTLVL_MED_gc = (0x02<<2), /* Medium Level */ - TC_CCBINTLVL_HI_gc = (0x03<<2), /* High Level */ -} TC_CCBINTLVL_t; - -/* Compare or Capture A Interrupt Level */ -typedef enum TC_CCAINTLVL_enum -{ - TC_CCAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - TC_CCAINTLVL_LO_gc = (0x01<<0), /* Low Level */ - TC_CCAINTLVL_MED_gc = (0x02<<0), /* Medium Level */ - TC_CCAINTLVL_HI_gc = (0x03<<0), /* High Level */ -} TC_CCAINTLVL_t; - -/* Timer/Counter Command */ -typedef enum TC_CMD_enum -{ - TC_CMD_NONE_gc = (0x00<<2), /* No Command */ - TC_CMD_UPDATE_gc = (0x01<<2), /* Force Update */ - TC_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ - TC_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ -} TC_CMD_t; - -/* Fault Detect Action */ -typedef enum AWEX_FDACT_enum -{ - AWEX_FDACT_NONE_gc = (0x00<<0), /* No Fault Protection */ - AWEX_FDACT_CLEAROE_gc = (0x01<<0), /* Clear Output Enable Bits */ - AWEX_FDACT_CLEARDIR_gc = (0x03<<0), /* Clear I/O Port Direction Bits */ -} AWEX_FDACT_t; - -/* High Resolution Enable */ -typedef enum HIRES_HREN_enum -{ - HIRES_HREN_NONE_gc = (0x00<<0), /* No Fault Protection */ - HIRES_HREN_TC0_gc = (0x01<<0), /* Enable High Resolution on Timer/Counter 0 */ - HIRES_HREN_TC1_gc = (0x02<<0), /* Enable High Resolution on Timer/Counter 1 */ - HIRES_HREN_BOTH_gc = (0x03<<0), /* Enable High Resolution both Timer/Counters */ -} HIRES_HREN_t; - - -/* --------------------------------------------------------------------------- -USART - Universal Asynchronous Receiver-Transmitter --------------------------------------------------------------------------- -*/ - -/* Universal Synchronous/Asynchronous Receiver/Transmitter */ -typedef struct USART_struct -{ - register8_t DATA; /* Data Register */ - register8_t STATUS; /* Status Register */ - register8_t reserved_0x02; - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t CTRLC; /* Control Register C */ - register8_t BAUDCTRLA; /* Baud Rate Control Register A */ - register8_t BAUDCTRLB; /* Baud Rate Control Register B */ -} USART_t; - -/* Receive Complete Interrupt level */ -typedef enum USART_RXCINTLVL_enum -{ - USART_RXCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ - USART_RXCINTLVL_LO_gc = (0x01<<4), /* Low Level */ - USART_RXCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ - USART_RXCINTLVL_HI_gc = (0x03<<4), /* High Level */ -} USART_RXCINTLVL_t; - -/* Transmit Complete Interrupt level */ -typedef enum USART_TXCINTLVL_enum -{ - USART_TXCINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ - USART_TXCINTLVL_LO_gc = (0x01<<2), /* Low Level */ - USART_TXCINTLVL_MED_gc = (0x02<<2), /* Medium Level */ - USART_TXCINTLVL_HI_gc = (0x03<<2), /* High Level */ -} USART_TXCINTLVL_t; - -/* Data Register Empty Interrupt level */ -typedef enum USART_DREINTLVL_enum -{ - USART_DREINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - USART_DREINTLVL_LO_gc = (0x01<<0), /* Low Level */ - USART_DREINTLVL_MED_gc = (0x02<<0), /* Medium Level */ - USART_DREINTLVL_HI_gc = (0x03<<0), /* High Level */ -} USART_DREINTLVL_t; - -/* Character Size */ -typedef enum USART_CHSIZE_enum -{ - USART_CHSIZE_5BIT_gc = (0x00<<0), /* Character size: 5 bit */ - USART_CHSIZE_6BIT_gc = (0x01<<0), /* Character size: 6 bit */ - USART_CHSIZE_7BIT_gc = (0x02<<0), /* Character size: 7 bit */ - USART_CHSIZE_8BIT_gc = (0x03<<0), /* Character size: 8 bit */ - USART_CHSIZE_9BIT_gc = (0x07<<0), /* Character size: 9 bit */ -} USART_CHSIZE_t; - -/* Communication Mode */ -typedef enum USART_CMODE_enum -{ - USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6), /* Asynchronous Mode */ - USART_CMODE_SYNCHRONOUS_gc = (0x01<<6), /* Synchronous Mode */ - USART_CMODE_IRDA_gc = (0x02<<6), /* IrDA Mode */ - USART_CMODE_MSPI_gc = (0x03<<6), /* Master SPI Mode */ -} USART_CMODE_t; - -/* Parity Mode */ -typedef enum USART_PMODE_enum -{ - USART_PMODE_DISABLED_gc = (0x00<<4), /* No Parity */ - USART_PMODE_EVEN_gc = (0x02<<4), /* Even Parity */ - USART_PMODE_ODD_gc = (0x03<<4), /* Odd Parity */ -} USART_PMODE_t; - - -/* --------------------------------------------------------------------------- -SPI - Serial Peripheral Interface --------------------------------------------------------------------------- -*/ - -/* Serial Peripheral Interface */ -typedef struct SPI_struct -{ - register8_t CTRL; /* Control Register */ - register8_t INTCTRL; /* Interrupt Control Register */ - register8_t STATUS; /* Status Register */ - register8_t DATA; /* Data Register */ -} SPI_t; - -/* SPI Mode */ -typedef enum SPI_MODE_enum -{ - SPI_MODE_0_gc = (0x00<<2), /* SPI Mode 0 */ - SPI_MODE_1_gc = (0x01<<2), /* SPI Mode 1 */ - SPI_MODE_2_gc = (0x02<<2), /* SPI Mode 2 */ - SPI_MODE_3_gc = (0x03<<2), /* SPI Mode 3 */ -} SPI_MODE_t; - -/* Prescaler setting */ -typedef enum SPI_PRESCALER_enum -{ - SPI_PRESCALER_DIV4_gc = (0x00<<0), /* System Clock / 4 */ - SPI_PRESCALER_DIV16_gc = (0x01<<0), /* System Clock / 16 */ - SPI_PRESCALER_DIV64_gc = (0x02<<0), /* System Clock / 64 */ - SPI_PRESCALER_DIV128_gc = (0x03<<0), /* System Clock / 128 */ -} SPI_PRESCALER_t; - -/* Interrupt level */ -typedef enum SPI_INTLVL_enum -{ - SPI_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - SPI_INTLVL_LO_gc = (0x01<<0), /* Low Level */ - SPI_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ - SPI_INTLVL_HI_gc = (0x03<<0), /* High Level */ -} SPI_INTLVL_t; - - -/* --------------------------------------------------------------------------- -IRCOM - IR Communication Module --------------------------------------------------------------------------- -*/ - -/* IR Communication Module */ -typedef struct IRCOM_struct -{ - register8_t CTRL; /* Control Register */ - register8_t TXPLCTRL; /* IrDA Transmitter Pulse Length Control Register */ - register8_t RXPLCTRL; /* IrDA Receiver Pulse Length Control Register */ -} IRCOM_t; - -/* Event channel selection */ -typedef enum IRDA_EVSEL_enum -{ - IRDA_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ - IRDA_EVSEL_0_gc = (0x08<<0), /* Event Channel 0 */ - IRDA_EVSEL_1_gc = (0x09<<0), /* Event Channel 1 */ - IRDA_EVSEL_2_gc = (0x0A<<0), /* Event Channel 2 */ - IRDA_EVSEL_3_gc = (0x0B<<0), /* Event Channel 3 */ - IRDA_EVSEL_4_gc = (0x0C<<0), /* Event Channel 4 */ - IRDA_EVSEL_5_gc = (0x0D<<0), /* Event Channel 5 */ - IRDA_EVSEL_6_gc = (0x0E<<0), /* Event Channel 6 */ - IRDA_EVSEL_7_gc = (0x0F<<0), /* Event Channel 7 */ -} IRDA_EVSEL_t; - - -/* --------------------------------------------------------------------------- -AES - AES Module --------------------------------------------------------------------------- -*/ - -/* AES Module */ -typedef struct AES_struct -{ - register8_t CTRL; /* AES Control Register */ - register8_t STATUS; /* AES Status Register */ - register8_t STATE; /* AES State Register */ - register8_t KEY; /* AES Key Register */ - register8_t INTCTRL; /* AES Interrupt Control Register */ -} AES_t; - -/* Interrupt level */ -typedef enum AES_INTLVL_enum -{ - AES_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - AES_INTLVL_LO_gc = (0x01<<0), /* Low Level */ - AES_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ - AES_INTLVL_HI_gc = (0x03<<0), /* High Level */ -} AES_INTLVL_t; - - - -/* -========================================================================== -IO Module Instances. Mapped to memory. -========================================================================== -*/ - -#define VPORT0 (*(VPORT_t *) 0x0010) /* Virtual Port 0 */ -#define VPORT1 (*(VPORT_t *) 0x0014) /* Virtual Port 1 */ -#define VPORT2 (*(VPORT_t *) 0x0018) /* Virtual Port 2 */ -#define VPORT3 (*(VPORT_t *) 0x001C) /* Virtual Port 3 */ -#define OCD (*(OCD_t *) 0x002E) /* On-Chip Debug System */ -#define CLK (*(CLK_t *) 0x0040) /* Clock System */ -#define SLEEP (*(SLEEP_t *) 0x0048) /* Sleep Controller */ -#define OSC (*(OSC_t *) 0x0050) /* Oscillator Control */ -#define DFLLRC32M (*(DFLL_t *) 0x0060) /* DFLL for 32MHz RC Oscillator */ -#define DFLLRC2M (*(DFLL_t *) 0x0068) /* DFLL for 2MHz RC Oscillator */ -#define PR (*(PR_t *) 0x0070) /* Power Reduction */ -#define RST (*(RST_t *) 0x0078) /* Reset Controller */ -#define WDT (*(WDT_t *) 0x0080) /* Watch-Dog Timer */ -#define MCU (*(MCU_t *) 0x0090) /* MCU Control */ -#define PMIC (*(PMIC_t *) 0x00A0) /* Programmable Interrupt Controller */ -#define PORTCFG (*(PORTCFG_t *) 0x00B0) /* Port Configuration */ -#define AES (*(AES_t *) 0x00C0) /* AES Crypto Module */ -#define DMA (*(DMA_t *) 0x0100) /* DMA Controller */ -#define EVSYS (*(EVSYS_t *) 0x0180) /* Event System */ -#define NVM (*(NVM_t *) 0x01C0) /* Non Volatile Memory Controller */ -#define ADCA (*(ADC_t *) 0x0200) /* Analog to Digital Converter A */ -#define ADCB (*(ADC_t *) 0x0240) /* Analog to Digital Converter B */ -#define DACB (*(DAC_t *) 0x0320) /* Digital to Analog Converter B */ -#define ACA (*(AC_t *) 0x0380) /* Analog Comparator A */ -#define ACB (*(AC_t *) 0x0390) /* Analog Comparator B */ -#define RTC (*(RTC_t *) 0x0400) /* Real-Time Counter */ -#define TWIC (*(TWI_t *) 0x0480) /* Two-Wire Interface C */ -#define TWIE (*(TWI_t *) 0x04A0) /* Two-Wire Interface E */ -#define PORTA (*(PORT_t *) 0x0600) /* Port A */ -#define PORTB (*(PORT_t *) 0x0620) /* Port B */ -#define PORTC (*(PORT_t *) 0x0640) /* Port C */ -#define PORTD (*(PORT_t *) 0x0660) /* Port D */ -#define PORTE (*(PORT_t *) 0x0680) /* Port E */ -#define PORTF (*(PORT_t *) 0x06A0) /* Port F */ -#define PORTR (*(PORT_t *) 0x07E0) /* Port R */ -#define TCC0 (*(TC0_t *) 0x0800) /* Timer/Counter C0 */ -#define TCC1 (*(TC1_t *) 0x0840) /* Timer/Counter C1 */ -#define AWEXC (*(AWEX_t *) 0x0880) /* Advanced Waveform Extension C */ -#define HIRESC (*(HIRES_t *) 0x0890) /* High-Resolution Extension C */ -#define USARTC0 (*(USART_t *) 0x08A0) /* Universal Asynchronous Receiver-Transmitter C0 */ -#define USARTC1 (*(USART_t *) 0x08B0) /* Universal Asynchronous Receiver-Transmitter C1 */ -#define SPIC (*(SPI_t *) 0x08C0) /* Serial Peripheral Interface C */ -#define IRCOM (*(IRCOM_t *) 0x08F8) /* IR Communication Module */ -#define TCD0 (*(TC0_t *) 0x0900) /* Timer/Counter D0 */ -#define TCD1 (*(TC1_t *) 0x0940) /* Timer/Counter D1 */ -#define HIRESD (*(HIRES_t *) 0x0990) /* High-Resolution Extension D */ -#define USARTD0 (*(USART_t *) 0x09A0) /* Universal Asynchronous Receiver-Transmitter D0 */ -#define USARTD1 (*(USART_t *) 0x09B0) /* Universal Asynchronous Receiver-Transmitter D1 */ -#define SPID (*(SPI_t *) 0x09C0) /* Serial Peripheral Interface D */ -#define TCE0 (*(TC0_t *) 0x0A00) /* Timer/Counter E0 */ -#define TCE1 (*(TC1_t *) 0x0A40) /* Timer/Counter E1 */ -#define AWEXE (*(AWEX_t *) 0x0A80) /* Advanced Waveform Extension E */ -#define HIRESE (*(HIRES_t *) 0x0A90) /* High-Resolution Extension E */ -#define USARTE0 (*(USART_t *) 0x0AA0) /* Universal Asynchronous Receiver-Transmitter E0 */ -#define USARTE1 (*(USART_t *) 0x0AB0) /* Universal Asynchronous Receiver-Transmitter E1 */ -#define SPIE (*(SPI_t *) 0x0AC0) /* Serial Peripheral Interface E */ -#define TCF0 (*(TC0_t *) 0x0B00) /* Timer/Counter F0 */ -#define HIRESF (*(HIRES_t *) 0x0B90) /* High-Resolution Extension F */ -#define USARTF0 (*(USART_t *) 0x0BA0) /* Universal Asynchronous Receiver-Transmitter F0 */ -#define USARTF1 (*(USART_t *) 0x0BB0) /* Universal Asynchronous Receiver-Transmitter F1 */ -#define SPIF (*(SPI_t *) 0x0BC0) /* Serial Peripheral Interface F */ - - -#endif /* !defined (__ASSEMBLER__) */ - - -/* ========== Flattened fully qualified IO register names ========== */ - -/* GPIO - General Purpose IO Registers */ -#define GPIO_GPIOR0 _SFR_MEM8(0x0000) -#define GPIO_GPIOR1 _SFR_MEM8(0x0001) -#define GPIO_GPIOR2 _SFR_MEM8(0x0002) -#define GPIO_GPIOR3 _SFR_MEM8(0x0003) -#define GPIO_GPIOR4 _SFR_MEM8(0x0004) -#define GPIO_GPIOR5 _SFR_MEM8(0x0005) -#define GPIO_GPIOR6 _SFR_MEM8(0x0006) -#define GPIO_GPIOR7 _SFR_MEM8(0x0007) -#define GPIO_GPIOR8 _SFR_MEM8(0x0008) -#define GPIO_GPIOR9 _SFR_MEM8(0x0009) -#define GPIO_GPIORA _SFR_MEM8(0x000A) -#define GPIO_GPIORB _SFR_MEM8(0x000B) -#define GPIO_GPIORC _SFR_MEM8(0x000C) -#define GPIO_GPIORD _SFR_MEM8(0x000D) -#define GPIO_GPIORE _SFR_MEM8(0x000E) -#define GPIO_GPIORF _SFR_MEM8(0x000F) - -/* Deprecated */ -#define GPIO_GPIO0 _SFR_MEM8(0x0000) -#define GPIO_GPIO1 _SFR_MEM8(0x0001) -#define GPIO_GPIO2 _SFR_MEM8(0x0002) -#define GPIO_GPIO3 _SFR_MEM8(0x0003) -#define GPIO_GPIO4 _SFR_MEM8(0x0004) -#define GPIO_GPIO5 _SFR_MEM8(0x0005) -#define GPIO_GPIO6 _SFR_MEM8(0x0006) -#define GPIO_GPIO7 _SFR_MEM8(0x0007) -#define GPIO_GPIO8 _SFR_MEM8(0x0008) -#define GPIO_GPIO9 _SFR_MEM8(0x0009) -#define GPIO_GPIOA _SFR_MEM8(0x000A) -#define GPIO_GPIOB _SFR_MEM8(0x000B) -#define GPIO_GPIOC _SFR_MEM8(0x000C) -#define GPIO_GPIOD _SFR_MEM8(0x000D) -#define GPIO_GPIOE _SFR_MEM8(0x000E) -#define GPIO_GPIOF _SFR_MEM8(0x000F) - -/* VPORT0 - Virtual Port 0 */ -#define VPORT0_DIR _SFR_MEM8(0x0010) -#define VPORT0_OUT _SFR_MEM8(0x0011) -#define VPORT0_IN _SFR_MEM8(0x0012) -#define VPORT0_INTFLAGS _SFR_MEM8(0x0013) - -/* VPORT1 - Virtual Port 1 */ -#define VPORT1_DIR _SFR_MEM8(0x0014) -#define VPORT1_OUT _SFR_MEM8(0x0015) -#define VPORT1_IN _SFR_MEM8(0x0016) -#define VPORT1_INTFLAGS _SFR_MEM8(0x0017) - -/* VPORT2 - Virtual Port 2 */ -#define VPORT2_DIR _SFR_MEM8(0x0018) -#define VPORT2_OUT _SFR_MEM8(0x0019) -#define VPORT2_IN _SFR_MEM8(0x001A) -#define VPORT2_INTFLAGS _SFR_MEM8(0x001B) - -/* VPORT3 - Virtual Port 3 */ -#define VPORT3_DIR _SFR_MEM8(0x001C) -#define VPORT3_OUT _SFR_MEM8(0x001D) -#define VPORT3_IN _SFR_MEM8(0x001E) -#define VPORT3_INTFLAGS _SFR_MEM8(0x001F) - -/* OCD - On-Chip Debug System */ -#define OCD_OCDR0 _SFR_MEM8(0x002E) -#define OCD_OCDR1 _SFR_MEM8(0x002F) - -/* CPU - CPU Registers */ -#define CPU_CCP _SFR_MEM8(0x0034) -#define CPU_RAMPD _SFR_MEM8(0x0038) -#define CPU_RAMPX _SFR_MEM8(0x0039) -#define CPU_RAMPY _SFR_MEM8(0x003A) -#define CPU_RAMPZ _SFR_MEM8(0x003B) -#define CPU_EIND _SFR_MEM8(0x003C) -#define CPU_SPL _SFR_MEM8(0x003D) -#define CPU_SPH _SFR_MEM8(0x003E) -#define CPU_SREG _SFR_MEM8(0x003F) - -/* CLK - Clock System */ -#define CLK_CTRL _SFR_MEM8(0x0040) -#define CLK_PSCTRL _SFR_MEM8(0x0041) -#define CLK_LOCK _SFR_MEM8(0x0042) -#define CLK_RTCCTRL _SFR_MEM8(0x0043) - -/* SLEEP - Sleep Controller */ -#define SLEEP_CTRL _SFR_MEM8(0x0048) - -/* OSC - Oscillator Control */ -#define OSC_CTRL _SFR_MEM8(0x0050) -#define OSC_STATUS _SFR_MEM8(0x0051) -#define OSC_XOSCCTRL _SFR_MEM8(0x0052) -#define OSC_XOSCFAIL _SFR_MEM8(0x0053) -#define OSC_RC32KCAL _SFR_MEM8(0x0054) -#define OSC_PLLCTRL _SFR_MEM8(0x0055) -#define OSC_DFLLCTRL _SFR_MEM8(0x0056) - -/* DFLLRC32M - DFLL for 32MHz RC Oscillator */ -#define DFLLRC32M_CTRL _SFR_MEM8(0x0060) -#define DFLLRC32M_CALA _SFR_MEM8(0x0062) -#define DFLLRC32M_CALB _SFR_MEM8(0x0063) -#define DFLLRC32M_COMP0 _SFR_MEM8(0x0064) -#define DFLLRC32M_COMP1 _SFR_MEM8(0x0065) -#define DFLLRC32M_COMP2 _SFR_MEM8(0x0066) - -/* DFLLRC2M - DFLL for 2MHz RC Oscillator */ -#define DFLLRC2M_CTRL _SFR_MEM8(0x0068) -#define DFLLRC2M_CALA _SFR_MEM8(0x006A) -#define DFLLRC2M_CALB _SFR_MEM8(0x006B) -#define DFLLRC2M_COMP0 _SFR_MEM8(0x006C) -#define DFLLRC2M_COMP1 _SFR_MEM8(0x006D) -#define DFLLRC2M_COMP2 _SFR_MEM8(0x006E) - -/* PR - Power Reduction */ -#define PR_PRGEN _SFR_MEM8(0x0070) -#define PR_PRPA _SFR_MEM8(0x0071) -#define PR_PRPB _SFR_MEM8(0x0072) -#define PR_PRPC _SFR_MEM8(0x0073) -#define PR_PRPD _SFR_MEM8(0x0074) -#define PR_PRPE _SFR_MEM8(0x0075) -#define PR_PRPF _SFR_MEM8(0x0076) - -/* RST - Reset Controller */ -#define RST_STATUS _SFR_MEM8(0x0078) -#define RST_CTRL _SFR_MEM8(0x0079) - -/* WDT - Watch-Dog Timer */ -#define WDT_CTRL _SFR_MEM8(0x0080) -#define WDT_WINCTRL _SFR_MEM8(0x0081) -#define WDT_STATUS _SFR_MEM8(0x0082) - -/* MCU - MCU Control */ -#define MCU_DEVID0 _SFR_MEM8(0x0090) -#define MCU_DEVID1 _SFR_MEM8(0x0091) -#define MCU_DEVID2 _SFR_MEM8(0x0092) -#define MCU_REVID _SFR_MEM8(0x0093) -#define MCU_JTAGUID _SFR_MEM8(0x0094) -#define MCU_MCUCR _SFR_MEM8(0x0096) -#define MCU_EVSYSLOCK _SFR_MEM8(0x0098) -#define MCU_AWEXLOCK _SFR_MEM8(0x0099) - -/* PMIC - Programmable Interrupt Controller */ -#define PMIC_STATUS _SFR_MEM8(0x00A0) -#define PMIC_INTPRI _SFR_MEM8(0x00A1) -#define PMIC_CTRL _SFR_MEM8(0x00A2) - -/* PORTCFG - Port Configuration */ -#define PORTCFG_MPCMASK _SFR_MEM8(0x00B0) -#define PORTCFG_VPCTRLA _SFR_MEM8(0x00B2) -#define PORTCFG_VPCTRLB _SFR_MEM8(0x00B3) -#define PORTCFG_CLKEVOUT _SFR_MEM8(0x00B4) - -/* AES - AES Crypto Module */ -#define AES_CTRL _SFR_MEM8(0x00C0) -#define AES_STATUS _SFR_MEM8(0x00C1) -#define AES_STATE _SFR_MEM8(0x00C2) -#define AES_KEY _SFR_MEM8(0x00C3) -#define AES_INTCTRL _SFR_MEM8(0x00C4) - -/* DMA - DMA Controller */ -#define DMA_CTRL _SFR_MEM8(0x0100) -#define DMA_INTFLAGS _SFR_MEM8(0x0103) -#define DMA_STATUS _SFR_MEM8(0x0104) -#define DMA_TEMP _SFR_MEM16(0x0106) -#define DMA_CH0_CTRLA _SFR_MEM8(0x0110) -#define DMA_CH0_CTRLB _SFR_MEM8(0x0111) -#define DMA_CH0_ADDRCTRL _SFR_MEM8(0x0112) -#define DMA_CH0_TRIGSRC _SFR_MEM8(0x0113) -#define DMA_CH0_TRFCNT _SFR_MEM16(0x0114) -#define DMA_CH0_REPCNT _SFR_MEM8(0x0116) -#define DMA_CH0_SRCADDR0 _SFR_MEM8(0x0118) -#define DMA_CH0_SRCADDR1 _SFR_MEM8(0x0119) -#define DMA_CH0_SRCADDR2 _SFR_MEM8(0x011A) -#define DMA_CH0_DESTADDR0 _SFR_MEM8(0x011C) -#define DMA_CH0_DESTADDR1 _SFR_MEM8(0x011D) -#define DMA_CH0_DESTADDR2 _SFR_MEM8(0x011E) -#define DMA_CH1_CTRLA _SFR_MEM8(0x0120) -#define DMA_CH1_CTRLB _SFR_MEM8(0x0121) -#define DMA_CH1_ADDRCTRL _SFR_MEM8(0x0122) -#define DMA_CH1_TRIGSRC _SFR_MEM8(0x0123) -#define DMA_CH1_TRFCNT _SFR_MEM16(0x0124) -#define DMA_CH1_REPCNT _SFR_MEM8(0x0126) -#define DMA_CH1_SRCADDR0 _SFR_MEM8(0x0128) -#define DMA_CH1_SRCADDR1 _SFR_MEM8(0x0129) -#define DMA_CH1_SRCADDR2 _SFR_MEM8(0x012A) -#define DMA_CH1_DESTADDR0 _SFR_MEM8(0x012C) -#define DMA_CH1_DESTADDR1 _SFR_MEM8(0x012D) -#define DMA_CH1_DESTADDR2 _SFR_MEM8(0x012E) -#define DMA_CH2_CTRLA _SFR_MEM8(0x0130) -#define DMA_CH2_CTRLB _SFR_MEM8(0x0131) -#define DMA_CH2_ADDRCTRL _SFR_MEM8(0x0132) -#define DMA_CH2_TRIGSRC _SFR_MEM8(0x0133) -#define DMA_CH2_TRFCNT _SFR_MEM16(0x0134) -#define DMA_CH2_REPCNT _SFR_MEM8(0x0136) -#define DMA_CH2_SRCADDR0 _SFR_MEM8(0x0138) -#define DMA_CH2_SRCADDR1 _SFR_MEM8(0x0139) -#define DMA_CH2_SRCADDR2 _SFR_MEM8(0x013A) -#define DMA_CH2_DESTADDR0 _SFR_MEM8(0x013C) -#define DMA_CH2_DESTADDR1 _SFR_MEM8(0x013D) -#define DMA_CH2_DESTADDR2 _SFR_MEM8(0x013E) -#define DMA_CH3_CTRLA _SFR_MEM8(0x0140) -#define DMA_CH3_CTRLB _SFR_MEM8(0x0141) -#define DMA_CH3_ADDRCTRL _SFR_MEM8(0x0142) -#define DMA_CH3_TRIGSRC _SFR_MEM8(0x0143) -#define DMA_CH3_TRFCNT _SFR_MEM16(0x0144) -#define DMA_CH3_REPCNT _SFR_MEM8(0x0146) -#define DMA_CH3_SRCADDR0 _SFR_MEM8(0x0148) -#define DMA_CH3_SRCADDR1 _SFR_MEM8(0x0149) -#define DMA_CH3_SRCADDR2 _SFR_MEM8(0x014A) -#define DMA_CH3_DESTADDR0 _SFR_MEM8(0x014C) -#define DMA_CH3_DESTADDR1 _SFR_MEM8(0x014D) -#define DMA_CH3_DESTADDR2 _SFR_MEM8(0x014E) - -/* EVSYS - Event System */ -#define EVSYS_CH0MUX _SFR_MEM8(0x0180) -#define EVSYS_CH1MUX _SFR_MEM8(0x0181) -#define EVSYS_CH2MUX _SFR_MEM8(0x0182) -#define EVSYS_CH3MUX _SFR_MEM8(0x0183) -#define EVSYS_CH4MUX _SFR_MEM8(0x0184) -#define EVSYS_CH5MUX _SFR_MEM8(0x0185) -#define EVSYS_CH6MUX _SFR_MEM8(0x0186) -#define EVSYS_CH7MUX _SFR_MEM8(0x0187) -#define EVSYS_CH0CTRL _SFR_MEM8(0x0188) -#define EVSYS_CH1CTRL _SFR_MEM8(0x0189) -#define EVSYS_CH2CTRL _SFR_MEM8(0x018A) -#define EVSYS_CH3CTRL _SFR_MEM8(0x018B) -#define EVSYS_CH4CTRL _SFR_MEM8(0x018C) -#define EVSYS_CH5CTRL _SFR_MEM8(0x018D) -#define EVSYS_CH6CTRL _SFR_MEM8(0x018E) -#define EVSYS_CH7CTRL _SFR_MEM8(0x018F) -#define EVSYS_STROBE _SFR_MEM8(0x0190) -#define EVSYS_DATA _SFR_MEM8(0x0191) - -/* NVM - Non Volatile Memory Controller */ -#define NVM_ADDR0 _SFR_MEM8(0x01C0) -#define NVM_ADDR1 _SFR_MEM8(0x01C1) -#define NVM_ADDR2 _SFR_MEM8(0x01C2) -#define NVM_DATA0 _SFR_MEM8(0x01C4) -#define NVM_DATA1 _SFR_MEM8(0x01C5) -#define NVM_DATA2 _SFR_MEM8(0x01C6) -#define NVM_CMD _SFR_MEM8(0x01CA) -#define NVM_CTRLA _SFR_MEM8(0x01CB) -#define NVM_CTRLB _SFR_MEM8(0x01CC) -#define NVM_INTCTRL _SFR_MEM8(0x01CD) -#define NVM_STATUS _SFR_MEM8(0x01CF) -#define NVM_LOCKBITS _SFR_MEM8(0x01D0) - -/* ADCA - Analog to Digital Converter A */ -#define ADCA_CTRLA _SFR_MEM8(0x0200) -#define ADCA_CTRLB _SFR_MEM8(0x0201) -#define ADCA_REFCTRL _SFR_MEM8(0x0202) -#define ADCA_EVCTRL _SFR_MEM8(0x0203) -#define ADCA_PRESCALER _SFR_MEM8(0x0204) -#define ADCA_INTFLAGS _SFR_MEM8(0x0206) -#define ADCA_CAL _SFR_MEM16(0x020C) -#define ADCA_CH0RES _SFR_MEM16(0x0210) -#define ADCA_CH1RES _SFR_MEM16(0x0212) -#define ADCA_CH2RES _SFR_MEM16(0x0214) -#define ADCA_CH3RES _SFR_MEM16(0x0216) -#define ADCA_CMP _SFR_MEM16(0x0218) -#define ADCA_CH0_CTRL _SFR_MEM8(0x0220) -#define ADCA_CH0_MUXCTRL _SFR_MEM8(0x0221) -#define ADCA_CH0_INTCTRL _SFR_MEM8(0x0222) -#define ADCA_CH0_INTFLAGS _SFR_MEM8(0x0223) -#define ADCA_CH0_RES _SFR_MEM16(0x0224) -#define ADCA_CH1_CTRL _SFR_MEM8(0x0228) -#define ADCA_CH1_MUXCTRL _SFR_MEM8(0x0229) -#define ADCA_CH1_INTCTRL _SFR_MEM8(0x022A) -#define ADCA_CH1_INTFLAGS _SFR_MEM8(0x022B) -#define ADCA_CH1_RES _SFR_MEM16(0x022C) -#define ADCA_CH2_CTRL _SFR_MEM8(0x0230) -#define ADCA_CH2_MUXCTRL _SFR_MEM8(0x0231) -#define ADCA_CH2_INTCTRL _SFR_MEM8(0x0232) -#define ADCA_CH2_INTFLAGS _SFR_MEM8(0x0233) -#define ADCA_CH2_RES _SFR_MEM16(0x0234) -#define ADCA_CH3_CTRL _SFR_MEM8(0x0238) -#define ADCA_CH3_MUXCTRL _SFR_MEM8(0x0239) -#define ADCA_CH3_INTCTRL _SFR_MEM8(0x023A) -#define ADCA_CH3_INTFLAGS _SFR_MEM8(0x023B) -#define ADCA_CH3_RES _SFR_MEM16(0x023C) - -/* ADCB - Analog to Digital Converter B */ -#define ADCB_CTRLA _SFR_MEM8(0x0240) -#define ADCB_CTRLB _SFR_MEM8(0x0241) -#define ADCB_REFCTRL _SFR_MEM8(0x0242) -#define ADCB_EVCTRL _SFR_MEM8(0x0243) -#define ADCB_PRESCALER _SFR_MEM8(0x0244) -#define ADCB_INTFLAGS _SFR_MEM8(0x0246) -#define ADCB_CAL _SFR_MEM16(0x024C) -#define ADCB_CH0RES _SFR_MEM16(0x0250) -#define ADCB_CH1RES _SFR_MEM16(0x0252) -#define ADCB_CH2RES _SFR_MEM16(0x0254) -#define ADCB_CH3RES _SFR_MEM16(0x0256) -#define ADCB_CMP _SFR_MEM16(0x0258) -#define ADCB_CH0_CTRL _SFR_MEM8(0x0260) -#define ADCB_CH0_MUXCTRL _SFR_MEM8(0x0261) -#define ADCB_CH0_INTCTRL _SFR_MEM8(0x0262) -#define ADCB_CH0_INTFLAGS _SFR_MEM8(0x0263) -#define ADCB_CH0_RES _SFR_MEM16(0x0264) -#define ADCB_CH1_CTRL _SFR_MEM8(0x0268) -#define ADCB_CH1_MUXCTRL _SFR_MEM8(0x0269) -#define ADCB_CH1_INTCTRL _SFR_MEM8(0x026A) -#define ADCB_CH1_INTFLAGS _SFR_MEM8(0x026B) -#define ADCB_CH1_RES _SFR_MEM16(0x026C) -#define ADCB_CH2_CTRL _SFR_MEM8(0x0270) -#define ADCB_CH2_MUXCTRL _SFR_MEM8(0x0271) -#define ADCB_CH2_INTCTRL _SFR_MEM8(0x0272) -#define ADCB_CH2_INTFLAGS _SFR_MEM8(0x0273) -#define ADCB_CH2_RES _SFR_MEM16(0x0274) -#define ADCB_CH3_CTRL _SFR_MEM8(0x0278) -#define ADCB_CH3_MUXCTRL _SFR_MEM8(0x0279) -#define ADCB_CH3_INTCTRL _SFR_MEM8(0x027A) -#define ADCB_CH3_INTFLAGS _SFR_MEM8(0x027B) -#define ADCB_CH3_RES _SFR_MEM16(0x027C) - -/* DACB - Digital to Analog Converter B */ -#define DACB_CTRLA _SFR_MEM8(0x0320) -#define DACB_CTRLB _SFR_MEM8(0x0321) -#define DACB_CTRLC _SFR_MEM8(0x0322) -#define DACB_EVCTRL _SFR_MEM8(0x0323) -#define DACB_TIMCTRL _SFR_MEM8(0x0324) -#define DACB_STATUS _SFR_MEM8(0x0325) -#define DACB_GAINCAL _SFR_MEM8(0x0328) -#define DACB_OFFSETCAL _SFR_MEM8(0x0329) -#define DACB_CH0DATA _SFR_MEM16(0x0338) -#define DACB_CH1DATA _SFR_MEM16(0x033A) - -/* ACA - Analog Comparator A */ -#define ACA_AC0CTRL _SFR_MEM8(0x0380) -#define ACA_AC1CTRL _SFR_MEM8(0x0381) -#define ACA_AC0MUXCTRL _SFR_MEM8(0x0382) -#define ACA_AC1MUXCTRL _SFR_MEM8(0x0383) -#define ACA_CTRLA _SFR_MEM8(0x0384) -#define ACA_CTRLB _SFR_MEM8(0x0385) -#define ACA_WINCTRL _SFR_MEM8(0x0386) -#define ACA_STATUS _SFR_MEM8(0x0387) - -/* ACB - Analog Comparator B */ -#define ACB_AC0CTRL _SFR_MEM8(0x0390) -#define ACB_AC1CTRL _SFR_MEM8(0x0391) -#define ACB_AC0MUXCTRL _SFR_MEM8(0x0392) -#define ACB_AC1MUXCTRL _SFR_MEM8(0x0393) -#define ACB_CTRLA _SFR_MEM8(0x0394) -#define ACB_CTRLB _SFR_MEM8(0x0395) -#define ACB_WINCTRL _SFR_MEM8(0x0396) -#define ACB_STATUS _SFR_MEM8(0x0397) - -/* RTC - Real-Time Counter */ -#define RTC_CTRL _SFR_MEM8(0x0400) -#define RTC_STATUS _SFR_MEM8(0x0401) -#define RTC_INTCTRL _SFR_MEM8(0x0402) -#define RTC_INTFLAGS _SFR_MEM8(0x0403) -#define RTC_TEMP _SFR_MEM8(0x0404) -#define RTC_CNT _SFR_MEM16(0x0408) -#define RTC_PER _SFR_MEM16(0x040A) -#define RTC_COMP _SFR_MEM16(0x040C) - -/* TWIC - Two-Wire Interface C */ -#define TWIC_CTRL _SFR_MEM8(0x0480) -#define TWIC_MASTER_CTRLA _SFR_MEM8(0x0481) -#define TWIC_MASTER_CTRLB _SFR_MEM8(0x0482) -#define TWIC_MASTER_CTRLC _SFR_MEM8(0x0483) -#define TWIC_MASTER_STATUS _SFR_MEM8(0x0484) -#define TWIC_MASTER_BAUD _SFR_MEM8(0x0485) -#define TWIC_MASTER_ADDR _SFR_MEM8(0x0486) -#define TWIC_MASTER_DATA _SFR_MEM8(0x0487) -#define TWIC_SLAVE_CTRLA _SFR_MEM8(0x0488) -#define TWIC_SLAVE_CTRLB _SFR_MEM8(0x0489) -#define TWIC_SLAVE_STATUS _SFR_MEM8(0x048A) -#define TWIC_SLAVE_ADDR _SFR_MEM8(0x048B) -#define TWIC_SLAVE_DATA _SFR_MEM8(0x048C) -#define TWIC_SLAVE_ADDRMASK _SFR_MEM8(0x048D) - -/* TWIE - Two-Wire Interface E */ -#define TWIE_CTRL _SFR_MEM8(0x04A0) -#define TWIE_MASTER_CTRLA _SFR_MEM8(0x04A1) -#define TWIE_MASTER_CTRLB _SFR_MEM8(0x04A2) -#define TWIE_MASTER_CTRLC _SFR_MEM8(0x04A3) -#define TWIE_MASTER_STATUS _SFR_MEM8(0x04A4) -#define TWIE_MASTER_BAUD _SFR_MEM8(0x04A5) -#define TWIE_MASTER_ADDR _SFR_MEM8(0x04A6) -#define TWIE_MASTER_DATA _SFR_MEM8(0x04A7) -#define TWIE_SLAVE_CTRLA _SFR_MEM8(0x04A8) -#define TWIE_SLAVE_CTRLB _SFR_MEM8(0x04A9) -#define TWIE_SLAVE_STATUS _SFR_MEM8(0x04AA) -#define TWIE_SLAVE_ADDR _SFR_MEM8(0x04AB) -#define TWIE_SLAVE_DATA _SFR_MEM8(0x04AC) -#define TWIE_SLAVE_ADDRMASK _SFR_MEM8(0x04AD) - -/* PORTA - Port A */ -#define PORTA_DIR _SFR_MEM8(0x0600) -#define PORTA_DIRSET _SFR_MEM8(0x0601) -#define PORTA_DIRCLR _SFR_MEM8(0x0602) -#define PORTA_DIRTGL _SFR_MEM8(0x0603) -#define PORTA_OUT _SFR_MEM8(0x0604) -#define PORTA_OUTSET _SFR_MEM8(0x0605) -#define PORTA_OUTCLR _SFR_MEM8(0x0606) -#define PORTA_OUTTGL _SFR_MEM8(0x0607) -#define PORTA_IN _SFR_MEM8(0x0608) -#define PORTA_INTCTRL _SFR_MEM8(0x0609) -#define PORTA_INT0MASK _SFR_MEM8(0x060A) -#define PORTA_INT1MASK _SFR_MEM8(0x060B) -#define PORTA_INTFLAGS _SFR_MEM8(0x060C) -#define PORTA_PIN0CTRL _SFR_MEM8(0x0610) -#define PORTA_PIN1CTRL _SFR_MEM8(0x0611) -#define PORTA_PIN2CTRL _SFR_MEM8(0x0612) -#define PORTA_PIN3CTRL _SFR_MEM8(0x0613) -#define PORTA_PIN4CTRL _SFR_MEM8(0x0614) -#define PORTA_PIN5CTRL _SFR_MEM8(0x0615) -#define PORTA_PIN6CTRL _SFR_MEM8(0x0616) -#define PORTA_PIN7CTRL _SFR_MEM8(0x0617) - -/* PORTB - Port B */ -#define PORTB_DIR _SFR_MEM8(0x0620) -#define PORTB_DIRSET _SFR_MEM8(0x0621) -#define PORTB_DIRCLR _SFR_MEM8(0x0622) -#define PORTB_DIRTGL _SFR_MEM8(0x0623) -#define PORTB_OUT _SFR_MEM8(0x0624) -#define PORTB_OUTSET _SFR_MEM8(0x0625) -#define PORTB_OUTCLR _SFR_MEM8(0x0626) -#define PORTB_OUTTGL _SFR_MEM8(0x0627) -#define PORTB_IN _SFR_MEM8(0x0628) -#define PORTB_INTCTRL _SFR_MEM8(0x0629) -#define PORTB_INT0MASK _SFR_MEM8(0x062A) -#define PORTB_INT1MASK _SFR_MEM8(0x062B) -#define PORTB_INTFLAGS _SFR_MEM8(0x062C) -#define PORTB_PIN0CTRL _SFR_MEM8(0x0630) -#define PORTB_PIN1CTRL _SFR_MEM8(0x0631) -#define PORTB_PIN2CTRL _SFR_MEM8(0x0632) -#define PORTB_PIN3CTRL _SFR_MEM8(0x0633) -#define PORTB_PIN4CTRL _SFR_MEM8(0x0634) -#define PORTB_PIN5CTRL _SFR_MEM8(0x0635) -#define PORTB_PIN6CTRL _SFR_MEM8(0x0636) -#define PORTB_PIN7CTRL _SFR_MEM8(0x0637) - -/* PORTC - Port C */ -#define PORTC_DIR _SFR_MEM8(0x0640) -#define PORTC_DIRSET _SFR_MEM8(0x0641) -#define PORTC_DIRCLR _SFR_MEM8(0x0642) -#define PORTC_DIRTGL _SFR_MEM8(0x0643) -#define PORTC_OUT _SFR_MEM8(0x0644) -#define PORTC_OUTSET _SFR_MEM8(0x0645) -#define PORTC_OUTCLR _SFR_MEM8(0x0646) -#define PORTC_OUTTGL _SFR_MEM8(0x0647) -#define PORTC_IN _SFR_MEM8(0x0648) -#define PORTC_INTCTRL _SFR_MEM8(0x0649) -#define PORTC_INT0MASK _SFR_MEM8(0x064A) -#define PORTC_INT1MASK _SFR_MEM8(0x064B) -#define PORTC_INTFLAGS _SFR_MEM8(0x064C) -#define PORTC_PIN0CTRL _SFR_MEM8(0x0650) -#define PORTC_PIN1CTRL _SFR_MEM8(0x0651) -#define PORTC_PIN2CTRL _SFR_MEM8(0x0652) -#define PORTC_PIN3CTRL _SFR_MEM8(0x0653) -#define PORTC_PIN4CTRL _SFR_MEM8(0x0654) -#define PORTC_PIN5CTRL _SFR_MEM8(0x0655) -#define PORTC_PIN6CTRL _SFR_MEM8(0x0656) -#define PORTC_PIN7CTRL _SFR_MEM8(0x0657) - -/* PORTD - Port D */ -#define PORTD_DIR _SFR_MEM8(0x0660) -#define PORTD_DIRSET _SFR_MEM8(0x0661) -#define PORTD_DIRCLR _SFR_MEM8(0x0662) -#define PORTD_DIRTGL _SFR_MEM8(0x0663) -#define PORTD_OUT _SFR_MEM8(0x0664) -#define PORTD_OUTSET _SFR_MEM8(0x0665) -#define PORTD_OUTCLR _SFR_MEM8(0x0666) -#define PORTD_OUTTGL _SFR_MEM8(0x0667) -#define PORTD_IN _SFR_MEM8(0x0668) -#define PORTD_INTCTRL _SFR_MEM8(0x0669) -#define PORTD_INT0MASK _SFR_MEM8(0x066A) -#define PORTD_INT1MASK _SFR_MEM8(0x066B) -#define PORTD_INTFLAGS _SFR_MEM8(0x066C) -#define PORTD_PIN0CTRL _SFR_MEM8(0x0670) -#define PORTD_PIN1CTRL _SFR_MEM8(0x0671) -#define PORTD_PIN2CTRL _SFR_MEM8(0x0672) -#define PORTD_PIN3CTRL _SFR_MEM8(0x0673) -#define PORTD_PIN4CTRL _SFR_MEM8(0x0674) -#define PORTD_PIN5CTRL _SFR_MEM8(0x0675) -#define PORTD_PIN6CTRL _SFR_MEM8(0x0676) -#define PORTD_PIN7CTRL _SFR_MEM8(0x0677) - -/* PORTE - Port E */ -#define PORTE_DIR _SFR_MEM8(0x0680) -#define PORTE_DIRSET _SFR_MEM8(0x0681) -#define PORTE_DIRCLR _SFR_MEM8(0x0682) -#define PORTE_DIRTGL _SFR_MEM8(0x0683) -#define PORTE_OUT _SFR_MEM8(0x0684) -#define PORTE_OUTSET _SFR_MEM8(0x0685) -#define PORTE_OUTCLR _SFR_MEM8(0x0686) -#define PORTE_OUTTGL _SFR_MEM8(0x0687) -#define PORTE_IN _SFR_MEM8(0x0688) -#define PORTE_INTCTRL _SFR_MEM8(0x0689) -#define PORTE_INT0MASK _SFR_MEM8(0x068A) -#define PORTE_INT1MASK _SFR_MEM8(0x068B) -#define PORTE_INTFLAGS _SFR_MEM8(0x068C) -#define PORTE_PIN0CTRL _SFR_MEM8(0x0690) -#define PORTE_PIN1CTRL _SFR_MEM8(0x0691) -#define PORTE_PIN2CTRL _SFR_MEM8(0x0692) -#define PORTE_PIN3CTRL _SFR_MEM8(0x0693) -#define PORTE_PIN4CTRL _SFR_MEM8(0x0694) -#define PORTE_PIN5CTRL _SFR_MEM8(0x0695) -#define PORTE_PIN6CTRL _SFR_MEM8(0x0696) -#define PORTE_PIN7CTRL _SFR_MEM8(0x0697) - -/* PORTF - Port F */ -#define PORTF_DIR _SFR_MEM8(0x06A0) -#define PORTF_DIRSET _SFR_MEM8(0x06A1) -#define PORTF_DIRCLR _SFR_MEM8(0x06A2) -#define PORTF_DIRTGL _SFR_MEM8(0x06A3) -#define PORTF_OUT _SFR_MEM8(0x06A4) -#define PORTF_OUTSET _SFR_MEM8(0x06A5) -#define PORTF_OUTCLR _SFR_MEM8(0x06A6) -#define PORTF_OUTTGL _SFR_MEM8(0x06A7) -#define PORTF_IN _SFR_MEM8(0x06A8) -#define PORTF_INTCTRL _SFR_MEM8(0x06A9) -#define PORTF_INT0MASK _SFR_MEM8(0x06AA) -#define PORTF_INT1MASK _SFR_MEM8(0x06AB) -#define PORTF_INTFLAGS _SFR_MEM8(0x06AC) -#define PORTF_PIN0CTRL _SFR_MEM8(0x06B0) -#define PORTF_PIN1CTRL _SFR_MEM8(0x06B1) -#define PORTF_PIN2CTRL _SFR_MEM8(0x06B2) -#define PORTF_PIN3CTRL _SFR_MEM8(0x06B3) -#define PORTF_PIN4CTRL _SFR_MEM8(0x06B4) -#define PORTF_PIN5CTRL _SFR_MEM8(0x06B5) -#define PORTF_PIN6CTRL _SFR_MEM8(0x06B6) -#define PORTF_PIN7CTRL _SFR_MEM8(0x06B7) - -/* PORTR - Port R */ -#define PORTR_DIR _SFR_MEM8(0x07E0) -#define PORTR_DIRSET _SFR_MEM8(0x07E1) -#define PORTR_DIRCLR _SFR_MEM8(0x07E2) -#define PORTR_DIRTGL _SFR_MEM8(0x07E3) -#define PORTR_OUT _SFR_MEM8(0x07E4) -#define PORTR_OUTSET _SFR_MEM8(0x07E5) -#define PORTR_OUTCLR _SFR_MEM8(0x07E6) -#define PORTR_OUTTGL _SFR_MEM8(0x07E7) -#define PORTR_IN _SFR_MEM8(0x07E8) -#define PORTR_INTCTRL _SFR_MEM8(0x07E9) -#define PORTR_INT0MASK _SFR_MEM8(0x07EA) -#define PORTR_INT1MASK _SFR_MEM8(0x07EB) -#define PORTR_INTFLAGS _SFR_MEM8(0x07EC) -#define PORTR_PIN0CTRL _SFR_MEM8(0x07F0) -#define PORTR_PIN1CTRL _SFR_MEM8(0x07F1) -#define PORTR_PIN2CTRL _SFR_MEM8(0x07F2) -#define PORTR_PIN3CTRL _SFR_MEM8(0x07F3) -#define PORTR_PIN4CTRL _SFR_MEM8(0x07F4) -#define PORTR_PIN5CTRL _SFR_MEM8(0x07F5) -#define PORTR_PIN6CTRL _SFR_MEM8(0x07F6) -#define PORTR_PIN7CTRL _SFR_MEM8(0x07F7) - -/* TCC0 - Timer/Counter C0 */ -#define TCC0_CTRLA _SFR_MEM8(0x0800) -#define TCC0_CTRLB _SFR_MEM8(0x0801) -#define TCC0_CTRLC _SFR_MEM8(0x0802) -#define TCC0_CTRLD _SFR_MEM8(0x0803) -#define TCC0_CTRLE _SFR_MEM8(0x0804) -#define TCC0_INTCTRLA _SFR_MEM8(0x0806) -#define TCC0_INTCTRLB _SFR_MEM8(0x0807) -#define TCC0_CTRLFCLR _SFR_MEM8(0x0808) -#define TCC0_CTRLFSET _SFR_MEM8(0x0809) -#define TCC0_CTRLGCLR _SFR_MEM8(0x080A) -#define TCC0_CTRLGSET _SFR_MEM8(0x080B) -#define TCC0_INTFLAGS _SFR_MEM8(0x080C) -#define TCC0_TEMP _SFR_MEM8(0x080F) -#define TCC0_CNT _SFR_MEM16(0x0820) -#define TCC0_PER _SFR_MEM16(0x0826) -#define TCC0_CCA _SFR_MEM16(0x0828) -#define TCC0_CCB _SFR_MEM16(0x082A) -#define TCC0_CCC _SFR_MEM16(0x082C) -#define TCC0_CCD _SFR_MEM16(0x082E) -#define TCC0_PERBUF _SFR_MEM16(0x0836) -#define TCC0_CCABUF _SFR_MEM16(0x0838) -#define TCC0_CCBBUF _SFR_MEM16(0x083A) -#define TCC0_CCCBUF _SFR_MEM16(0x083C) -#define TCC0_CCDBUF _SFR_MEM16(0x083E) - -/* TCC1 - Timer/Counter C1 */ -#define TCC1_CTRLA _SFR_MEM8(0x0840) -#define TCC1_CTRLB _SFR_MEM8(0x0841) -#define TCC1_CTRLC _SFR_MEM8(0x0842) -#define TCC1_CTRLD _SFR_MEM8(0x0843) -#define TCC1_CTRLE _SFR_MEM8(0x0844) -#define TCC1_INTCTRLA _SFR_MEM8(0x0846) -#define TCC1_INTCTRLB _SFR_MEM8(0x0847) -#define TCC1_CTRLFCLR _SFR_MEM8(0x0848) -#define TCC1_CTRLFSET _SFR_MEM8(0x0849) -#define TCC1_CTRLGCLR _SFR_MEM8(0x084A) -#define TCC1_CTRLGSET _SFR_MEM8(0x084B) -#define TCC1_INTFLAGS _SFR_MEM8(0x084C) -#define TCC1_TEMP _SFR_MEM8(0x084F) -#define TCC1_CNT _SFR_MEM16(0x0860) -#define TCC1_PER _SFR_MEM16(0x0866) -#define TCC1_CCA _SFR_MEM16(0x0868) -#define TCC1_CCB _SFR_MEM16(0x086A) -#define TCC1_PERBUF _SFR_MEM16(0x0876) -#define TCC1_CCABUF _SFR_MEM16(0x0878) -#define TCC1_CCBBUF _SFR_MEM16(0x087A) - -/* AWEXC - Advanced Waveform Extension C */ -#define AWEXC_CTRL _SFR_MEM8(0x0880) -#define AWEXC_FDEMASK _SFR_MEM8(0x0882) -#define AWEXC_FDCTRL _SFR_MEM8(0x0883) -#define AWEXC_STATUS _SFR_MEM8(0x0884) -#define AWEXC_DTBOTH _SFR_MEM8(0x0886) -#define AWEXC_DTBOTHBUF _SFR_MEM8(0x0887) -#define AWEXC_DTLS _SFR_MEM8(0x0888) -#define AWEXC_DTHS _SFR_MEM8(0x0889) -#define AWEXC_DTLSBUF _SFR_MEM8(0x088A) -#define AWEXC_DTHSBUF _SFR_MEM8(0x088B) -#define AWEXC_OUTOVEN _SFR_MEM8(0x088C) - -/* HIRESC - High-Resolution Extension C */ -#define HIRESC_CTRLA _SFR_MEM8(0x0890) - -/* USARTC0 - Universal Asynchronous Receiver-Transmitter C0 */ -#define USARTC0_DATA _SFR_MEM8(0x08A0) -#define USARTC0_STATUS _SFR_MEM8(0x08A1) -#define USARTC0_CTRLA _SFR_MEM8(0x08A3) -#define USARTC0_CTRLB _SFR_MEM8(0x08A4) -#define USARTC0_CTRLC _SFR_MEM8(0x08A5) -#define USARTC0_BAUDCTRLA _SFR_MEM8(0x08A6) -#define USARTC0_BAUDCTRLB _SFR_MEM8(0x08A7) - -/* USARTC1 - Universal Asynchronous Receiver-Transmitter C1 */ -#define USARTC1_DATA _SFR_MEM8(0x08B0) -#define USARTC1_STATUS _SFR_MEM8(0x08B1) -#define USARTC1_CTRLA _SFR_MEM8(0x08B3) -#define USARTC1_CTRLB _SFR_MEM8(0x08B4) -#define USARTC1_CTRLC _SFR_MEM8(0x08B5) -#define USARTC1_BAUDCTRLA _SFR_MEM8(0x08B6) -#define USARTC1_BAUDCTRLB _SFR_MEM8(0x08B7) - -/* SPIC - Serial Peripheral Interface C */ -#define SPIC_CTRL _SFR_MEM8(0x08C0) -#define SPIC_INTCTRL _SFR_MEM8(0x08C1) -#define SPIC_STATUS _SFR_MEM8(0x08C2) -#define SPIC_DATA _SFR_MEM8(0x08C3) - -/* IRCOM - IR Communication Module */ -#define IRCOM_CTRL _SFR_MEM8(0x08F8) -#define IRCOM_TXPLCTRL _SFR_MEM8(0x08F9) -#define IRCOM_RXPLCTRL _SFR_MEM8(0x08FA) - -/* TCD0 - Timer/Counter D0 */ -#define TCD0_CTRLA _SFR_MEM8(0x0900) -#define TCD0_CTRLB _SFR_MEM8(0x0901) -#define TCD0_CTRLC _SFR_MEM8(0x0902) -#define TCD0_CTRLD _SFR_MEM8(0x0903) -#define TCD0_CTRLE _SFR_MEM8(0x0904) -#define TCD0_INTCTRLA _SFR_MEM8(0x0906) -#define TCD0_INTCTRLB _SFR_MEM8(0x0907) -#define TCD0_CTRLFCLR _SFR_MEM8(0x0908) -#define TCD0_CTRLFSET _SFR_MEM8(0x0909) -#define TCD0_CTRLGCLR _SFR_MEM8(0x090A) -#define TCD0_CTRLGSET _SFR_MEM8(0x090B) -#define TCD0_INTFLAGS _SFR_MEM8(0x090C) -#define TCD0_TEMP _SFR_MEM8(0x090F) -#define TCD0_CNT _SFR_MEM16(0x0920) -#define TCD0_PER _SFR_MEM16(0x0926) -#define TCD0_CCA _SFR_MEM16(0x0928) -#define TCD0_CCB _SFR_MEM16(0x092A) -#define TCD0_CCC _SFR_MEM16(0x092C) -#define TCD0_CCD _SFR_MEM16(0x092E) -#define TCD0_PERBUF _SFR_MEM16(0x0936) -#define TCD0_CCABUF _SFR_MEM16(0x0938) -#define TCD0_CCBBUF _SFR_MEM16(0x093A) -#define TCD0_CCCBUF _SFR_MEM16(0x093C) -#define TCD0_CCDBUF _SFR_MEM16(0x093E) - -/* TCD1 - Timer/Counter D1 */ -#define TCD1_CTRLA _SFR_MEM8(0x0940) -#define TCD1_CTRLB _SFR_MEM8(0x0941) -#define TCD1_CTRLC _SFR_MEM8(0x0942) -#define TCD1_CTRLD _SFR_MEM8(0x0943) -#define TCD1_CTRLE _SFR_MEM8(0x0944) -#define TCD1_INTCTRLA _SFR_MEM8(0x0946) -#define TCD1_INTCTRLB _SFR_MEM8(0x0947) -#define TCD1_CTRLFCLR _SFR_MEM8(0x0948) -#define TCD1_CTRLFSET _SFR_MEM8(0x0949) -#define TCD1_CTRLGCLR _SFR_MEM8(0x094A) -#define TCD1_CTRLGSET _SFR_MEM8(0x094B) -#define TCD1_INTFLAGS _SFR_MEM8(0x094C) -#define TCD1_TEMP _SFR_MEM8(0x094F) -#define TCD1_CNT _SFR_MEM16(0x0960) -#define TCD1_PER _SFR_MEM16(0x0966) -#define TCD1_CCA _SFR_MEM16(0x0968) -#define TCD1_CCB _SFR_MEM16(0x096A) -#define TCD1_PERBUF _SFR_MEM16(0x0976) -#define TCD1_CCABUF _SFR_MEM16(0x0978) -#define TCD1_CCBBUF _SFR_MEM16(0x097A) - -/* HIRESD - High-Resolution Extension D */ -#define HIRESD_CTRLA _SFR_MEM8(0x0990) - -/* USARTD0 - Universal Asynchronous Receiver-Transmitter D0 */ -#define USARTD0_DATA _SFR_MEM8(0x09A0) -#define USARTD0_STATUS _SFR_MEM8(0x09A1) -#define USARTD0_CTRLA _SFR_MEM8(0x09A3) -#define USARTD0_CTRLB _SFR_MEM8(0x09A4) -#define USARTD0_CTRLC _SFR_MEM8(0x09A5) -#define USARTD0_BAUDCTRLA _SFR_MEM8(0x09A6) -#define USARTD0_BAUDCTRLB _SFR_MEM8(0x09A7) - -/* USARTD1 - Universal Asynchronous Receiver-Transmitter D1 */ -#define USARTD1_DATA _SFR_MEM8(0x09B0) -#define USARTD1_STATUS _SFR_MEM8(0x09B1) -#define USARTD1_CTRLA _SFR_MEM8(0x09B3) -#define USARTD1_CTRLB _SFR_MEM8(0x09B4) -#define USARTD1_CTRLC _SFR_MEM8(0x09B5) -#define USARTD1_BAUDCTRLA _SFR_MEM8(0x09B6) -#define USARTD1_BAUDCTRLB _SFR_MEM8(0x09B7) - -/* SPID - Serial Peripheral Interface D */ -#define SPID_CTRL _SFR_MEM8(0x09C0) -#define SPID_INTCTRL _SFR_MEM8(0x09C1) -#define SPID_STATUS _SFR_MEM8(0x09C2) -#define SPID_DATA _SFR_MEM8(0x09C3) - -/* TCE0 - Timer/Counter E0 */ -#define TCE0_CTRLA _SFR_MEM8(0x0A00) -#define TCE0_CTRLB _SFR_MEM8(0x0A01) -#define TCE0_CTRLC _SFR_MEM8(0x0A02) -#define TCE0_CTRLD _SFR_MEM8(0x0A03) -#define TCE0_CTRLE _SFR_MEM8(0x0A04) -#define TCE0_INTCTRLA _SFR_MEM8(0x0A06) -#define TCE0_INTCTRLB _SFR_MEM8(0x0A07) -#define TCE0_CTRLFCLR _SFR_MEM8(0x0A08) -#define TCE0_CTRLFSET _SFR_MEM8(0x0A09) -#define TCE0_CTRLGCLR _SFR_MEM8(0x0A0A) -#define TCE0_CTRLGSET _SFR_MEM8(0x0A0B) -#define TCE0_INTFLAGS _SFR_MEM8(0x0A0C) -#define TCE0_TEMP _SFR_MEM8(0x0A0F) -#define TCE0_CNT _SFR_MEM16(0x0A20) -#define TCE0_PER _SFR_MEM16(0x0A26) -#define TCE0_CCA _SFR_MEM16(0x0A28) -#define TCE0_CCB _SFR_MEM16(0x0A2A) -#define TCE0_CCC _SFR_MEM16(0x0A2C) -#define TCE0_CCD _SFR_MEM16(0x0A2E) -#define TCE0_PERBUF _SFR_MEM16(0x0A36) -#define TCE0_CCABUF _SFR_MEM16(0x0A38) -#define TCE0_CCBBUF _SFR_MEM16(0x0A3A) -#define TCE0_CCCBUF _SFR_MEM16(0x0A3C) -#define TCE0_CCDBUF _SFR_MEM16(0x0A3E) - -/* TCE1 - Timer/Counter E1 */ -#define TCE1_CTRLA _SFR_MEM8(0x0A40) -#define TCE1_CTRLB _SFR_MEM8(0x0A41) -#define TCE1_CTRLC _SFR_MEM8(0x0A42) -#define TCE1_CTRLD _SFR_MEM8(0x0A43) -#define TCE1_CTRLE _SFR_MEM8(0x0A44) -#define TCE1_INTCTRLA _SFR_MEM8(0x0A46) -#define TCE1_INTCTRLB _SFR_MEM8(0x0A47) -#define TCE1_CTRLFCLR _SFR_MEM8(0x0A48) -#define TCE1_CTRLFSET _SFR_MEM8(0x0A49) -#define TCE1_CTRLGCLR _SFR_MEM8(0x0A4A) -#define TCE1_CTRLGSET _SFR_MEM8(0x0A4B) -#define TCE1_INTFLAGS _SFR_MEM8(0x0A4C) -#define TCE1_TEMP _SFR_MEM8(0x0A4F) -#define TCE1_CNT _SFR_MEM16(0x0A60) -#define TCE1_PER _SFR_MEM16(0x0A66) -#define TCE1_CCA _SFR_MEM16(0x0A68) -#define TCE1_CCB _SFR_MEM16(0x0A6A) -#define TCE1_PERBUF _SFR_MEM16(0x0A76) -#define TCE1_CCABUF _SFR_MEM16(0x0A78) -#define TCE1_CCBBUF _SFR_MEM16(0x0A7A) - -/* AWEXE - Advanced Waveform Extension E */ -#define AWEXE_CTRL _SFR_MEM8(0x0A80) -#define AWEXE_FDEMASK _SFR_MEM8(0x0A82) -#define AWEXE_FDCTRL _SFR_MEM8(0x0A83) -#define AWEXE_STATUS _SFR_MEM8(0x0A84) -#define AWEXE_DTBOTH _SFR_MEM8(0x0A86) -#define AWEXE_DTBOTHBUF _SFR_MEM8(0x0A87) -#define AWEXE_DTLS _SFR_MEM8(0x0A88) -#define AWEXE_DTHS _SFR_MEM8(0x0A89) -#define AWEXE_DTLSBUF _SFR_MEM8(0x0A8A) -#define AWEXE_DTHSBUF _SFR_MEM8(0x0A8B) -#define AWEXE_OUTOVEN _SFR_MEM8(0x0A8C) - -/* HIRESE - High-Resolution Extension E */ -#define HIRESE_CTRLA _SFR_MEM8(0x0A90) - -/* USARTE0 - Universal Asynchronous Receiver-Transmitter E0 */ -#define USARTE0_DATA _SFR_MEM8(0x0AA0) -#define USARTE0_STATUS _SFR_MEM8(0x0AA1) -#define USARTE0_CTRLA _SFR_MEM8(0x0AA3) -#define USARTE0_CTRLB _SFR_MEM8(0x0AA4) -#define USARTE0_CTRLC _SFR_MEM8(0x0AA5) -#define USARTE0_BAUDCTRLA _SFR_MEM8(0x0AA6) -#define USARTE0_BAUDCTRLB _SFR_MEM8(0x0AA7) - -/* USARTE1 - Universal Asynchronous Receiver-Transmitter E1 */ -#define USARTE1_DATA _SFR_MEM8(0x0AB0) -#define USARTE1_STATUS _SFR_MEM8(0x0AB1) -#define USARTE1_CTRLA _SFR_MEM8(0x0AB3) -#define USARTE1_CTRLB _SFR_MEM8(0x0AB4) -#define USARTE1_CTRLC _SFR_MEM8(0x0AB5) -#define USARTE1_BAUDCTRLA _SFR_MEM8(0x0AB6) -#define USARTE1_BAUDCTRLB _SFR_MEM8(0x0AB7) - -/* SPIE - Serial Peripheral Interface E */ -#define SPIE_CTRL _SFR_MEM8(0x0AC0) -#define SPIE_INTCTRL _SFR_MEM8(0x0AC1) -#define SPIE_STATUS _SFR_MEM8(0x0AC2) -#define SPIE_DATA _SFR_MEM8(0x0AC3) - -/* TCF0 - Timer/Counter F0 */ -#define TCF0_CTRLA _SFR_MEM8(0x0B00) -#define TCF0_CTRLB _SFR_MEM8(0x0B01) -#define TCF0_CTRLC _SFR_MEM8(0x0B02) -#define TCF0_CTRLD _SFR_MEM8(0x0B03) -#define TCF0_CTRLE _SFR_MEM8(0x0B04) -#define TCF0_INTCTRLA _SFR_MEM8(0x0B06) -#define TCF0_INTCTRLB _SFR_MEM8(0x0B07) -#define TCF0_CTRLFCLR _SFR_MEM8(0x0B08) -#define TCF0_CTRLFSET _SFR_MEM8(0x0B09) -#define TCF0_CTRLGCLR _SFR_MEM8(0x0B0A) -#define TCF0_CTRLGSET _SFR_MEM8(0x0B0B) -#define TCF0_INTFLAGS _SFR_MEM8(0x0B0C) -#define TCF0_TEMP _SFR_MEM8(0x0B0F) -#define TCF0_CNT _SFR_MEM16(0x0B20) -#define TCF0_PER _SFR_MEM16(0x0B26) -#define TCF0_CCA _SFR_MEM16(0x0B28) -#define TCF0_CCB _SFR_MEM16(0x0B2A) -#define TCF0_CCC _SFR_MEM16(0x0B2C) -#define TCF0_CCD _SFR_MEM16(0x0B2E) -#define TCF0_PERBUF _SFR_MEM16(0x0B36) -#define TCF0_CCABUF _SFR_MEM16(0x0B38) -#define TCF0_CCBBUF _SFR_MEM16(0x0B3A) -#define TCF0_CCCBUF _SFR_MEM16(0x0B3C) -#define TCF0_CCDBUF _SFR_MEM16(0x0B3E) - -/* HIRESF - High-Resolution Extension F */ -#define HIRESF_CTRLA _SFR_MEM8(0x0B90) - -/* USARTF0 - Universal Asynchronous Receiver-Transmitter F0 */ -#define USARTF0_DATA _SFR_MEM8(0x0BA0) -#define USARTF0_STATUS _SFR_MEM8(0x0BA1) -#define USARTF0_CTRLA _SFR_MEM8(0x0BA3) -#define USARTF0_CTRLB _SFR_MEM8(0x0BA4) -#define USARTF0_CTRLC _SFR_MEM8(0x0BA5) -#define USARTF0_BAUDCTRLA _SFR_MEM8(0x0BA6) -#define USARTF0_BAUDCTRLB _SFR_MEM8(0x0BA7) - -/* USARTF1 - Universal Asynchronous Receiver-Transmitter F1 */ -#define USARTF1_DATA _SFR_MEM8(0x0BB0) -#define USARTF1_STATUS _SFR_MEM8(0x0BB1) -#define USARTF1_CTRLA _SFR_MEM8(0x0BB3) -#define USARTF1_CTRLB _SFR_MEM8(0x0BB4) -#define USARTF1_CTRLC _SFR_MEM8(0x0BB5) -#define USARTF1_BAUDCTRLA _SFR_MEM8(0x0BB6) -#define USARTF1_BAUDCTRLB _SFR_MEM8(0x0BB7) - -/* SPIF - Serial Peripheral Interface F */ -#define SPIF_CTRL _SFR_MEM8(0x0BC0) -#define SPIF_INTCTRL _SFR_MEM8(0x0BC1) -#define SPIF_STATUS _SFR_MEM8(0x0BC2) -#define SPIF_DATA _SFR_MEM8(0x0BC3) - - - -/*================== Bitfield Definitions ================== */ - -/* XOCD - On-Chip Debug System */ -/* OCD.OCDR1 bit masks and bit positions */ -#define OCD_OCDRD_bm 0x01 /* OCDR Dirty bit mask. */ -#define OCD_OCDRD_bp 0 /* OCDR Dirty bit position. */ - - -/* CPU - CPU */ -/* CPU.CCP bit masks and bit positions */ -#define CPU_CCP_gm 0xFF /* CCP signature group mask. */ -#define CPU_CCP_gp 0 /* CCP signature group position. */ -#define CPU_CCP0_bm (1<<0) /* CCP signature bit 0 mask. */ -#define CPU_CCP0_bp 0 /* CCP signature bit 0 position. */ -#define CPU_CCP1_bm (1<<1) /* CCP signature bit 1 mask. */ -#define CPU_CCP1_bp 1 /* CCP signature bit 1 position. */ -#define CPU_CCP2_bm (1<<2) /* CCP signature bit 2 mask. */ -#define CPU_CCP2_bp 2 /* CCP signature bit 2 position. */ -#define CPU_CCP3_bm (1<<3) /* CCP signature bit 3 mask. */ -#define CPU_CCP3_bp 3 /* CCP signature bit 3 position. */ -#define CPU_CCP4_bm (1<<4) /* CCP signature bit 4 mask. */ -#define CPU_CCP4_bp 4 /* CCP signature bit 4 position. */ -#define CPU_CCP5_bm (1<<5) /* CCP signature bit 5 mask. */ -#define CPU_CCP5_bp 5 /* CCP signature bit 5 position. */ -#define CPU_CCP6_bm (1<<6) /* CCP signature bit 6 mask. */ -#define CPU_CCP6_bp 6 /* CCP signature bit 6 position. */ -#define CPU_CCP7_bm (1<<7) /* CCP signature bit 7 mask. */ -#define CPU_CCP7_bp 7 /* CCP signature bit 7 position. */ - - -/* CPU.SREG bit masks and bit positions */ -#define CPU_I_bm 0x80 /* Global Interrupt Enable Flag bit mask. */ -#define CPU_I_bp 7 /* Global Interrupt Enable Flag bit position. */ - -#define CPU_T_bm 0x40 /* Transfer Bit bit mask. */ -#define CPU_T_bp 6 /* Transfer Bit bit position. */ - -#define CPU_H_bm 0x20 /* Half Carry Flag bit mask. */ -#define CPU_H_bp 5 /* Half Carry Flag bit position. */ - -#define CPU_S_bm 0x10 /* N Exclusive Or V Flag bit mask. */ -#define CPU_S_bp 4 /* N Exclusive Or V Flag bit position. */ - -#define CPU_V_bm 0x08 /* Two's Complement Overflow Flag bit mask. */ -#define CPU_V_bp 3 /* Two's Complement Overflow Flag bit position. */ - -#define CPU_N_bm 0x04 /* Negative Flag bit mask. */ -#define CPU_N_bp 2 /* Negative Flag bit position. */ - -#define CPU_Z_bm 0x02 /* Zero Flag bit mask. */ -#define CPU_Z_bp 1 /* Zero Flag bit position. */ - -#define CPU_C_bm 0x01 /* Carry Flag bit mask. */ -#define CPU_C_bp 0 /* Carry Flag bit position. */ - - -/* CLK - Clock System */ -/* CLK.CTRL bit masks and bit positions */ -#define CLK_SCLKSEL_gm 0x07 /* System Clock Selection group mask. */ -#define CLK_SCLKSEL_gp 0 /* System Clock Selection group position. */ -#define CLK_SCLKSEL0_bm (1<<0) /* System Clock Selection bit 0 mask. */ -#define CLK_SCLKSEL0_bp 0 /* System Clock Selection bit 0 position. */ -#define CLK_SCLKSEL1_bm (1<<1) /* System Clock Selection bit 1 mask. */ -#define CLK_SCLKSEL1_bp 1 /* System Clock Selection bit 1 position. */ -#define CLK_SCLKSEL2_bm (1<<2) /* System Clock Selection bit 2 mask. */ -#define CLK_SCLKSEL2_bp 2 /* System Clock Selection bit 2 position. */ - - -/* CLK.PSCTRL bit masks and bit positions */ -#define CLK_PSADIV_gm 0x7C /* Prescaler A Division Factor group mask. */ -#define CLK_PSADIV_gp 2 /* Prescaler A Division Factor group position. */ -#define CLK_PSADIV0_bm (1<<2) /* Prescaler A Division Factor bit 0 mask. */ -#define CLK_PSADIV0_bp 2 /* Prescaler A Division Factor bit 0 position. */ -#define CLK_PSADIV1_bm (1<<3) /* Prescaler A Division Factor bit 1 mask. */ -#define CLK_PSADIV1_bp 3 /* Prescaler A Division Factor bit 1 position. */ -#define CLK_PSADIV2_bm (1<<4) /* Prescaler A Division Factor bit 2 mask. */ -#define CLK_PSADIV2_bp 4 /* Prescaler A Division Factor bit 2 position. */ -#define CLK_PSADIV3_bm (1<<5) /* Prescaler A Division Factor bit 3 mask. */ -#define CLK_PSADIV3_bp 5 /* Prescaler A Division Factor bit 3 position. */ -#define CLK_PSADIV4_bm (1<<6) /* Prescaler A Division Factor bit 4 mask. */ -#define CLK_PSADIV4_bp 6 /* Prescaler A Division Factor bit 4 position. */ - -#define CLK_PSBCDIV_gm 0x03 /* Prescaler B and C Division factor group mask. */ -#define CLK_PSBCDIV_gp 0 /* Prescaler B and C Division factor group position. */ -#define CLK_PSBCDIV0_bm (1<<0) /* Prescaler B and C Division factor bit 0 mask. */ -#define CLK_PSBCDIV0_bp 0 /* Prescaler B and C Division factor bit 0 position. */ -#define CLK_PSBCDIV1_bm (1<<1) /* Prescaler B and C Division factor bit 1 mask. */ -#define CLK_PSBCDIV1_bp 1 /* Prescaler B and C Division factor bit 1 position. */ - - -/* CLK.LOCK bit masks and bit positions */ -#define CLK_LOCK_bm 0x01 /* Clock System Lock bit mask. */ -#define CLK_LOCK_bp 0 /* Clock System Lock bit position. */ - - -/* CLK.RTCCTRL bit masks and bit positions */ -#define CLK_RTCSRC_gm 0x0E /* Clock Source group mask. */ -#define CLK_RTCSRC_gp 1 /* Clock Source group position. */ -#define CLK_RTCSRC0_bm (1<<1) /* Clock Source bit 0 mask. */ -#define CLK_RTCSRC0_bp 1 /* Clock Source bit 0 position. */ -#define CLK_RTCSRC1_bm (1<<2) /* Clock Source bit 1 mask. */ -#define CLK_RTCSRC1_bp 2 /* Clock Source bit 1 position. */ -#define CLK_RTCSRC2_bm (1<<3) /* Clock Source bit 2 mask. */ -#define CLK_RTCSRC2_bp 3 /* Clock Source bit 2 position. */ - -#define CLK_RTCEN_bm 0x01 /* RTC Clock Source Enable bit mask. */ -#define CLK_RTCEN_bp 0 /* RTC Clock Source Enable bit position. */ - - -/* PR.PRGEN bit masks and bit positions */ -#define PR_AES_bm 0x10 /* AES bit mask. */ -#define PR_AES_bp 4 /* AES bit position. */ - -#define PR_EBI_bm 0x08 /* External Bus Interface bit mask. */ -#define PR_EBI_bp 3 /* External Bus Interface bit position. */ - -#define PR_RTC_bm 0x04 /* Real-time Counter bit mask. */ -#define PR_RTC_bp 2 /* Real-time Counter bit position. */ - -#define PR_EVSYS_bm 0x02 /* Event System bit mask. */ -#define PR_EVSYS_bp 1 /* Event System bit position. */ - -#define PR_DMA_bm 0x01 /* DMA-Controller bit mask. */ -#define PR_DMA_bp 0 /* DMA-Controller bit position. */ - - -/* PR.PRPA bit masks and bit positions */ -#define PR_DAC_bm 0x04 /* Port A DAC bit mask. */ -#define PR_DAC_bp 2 /* Port A DAC bit position. */ - -#define PR_ADC_bm 0x02 /* Port A ADC bit mask. */ -#define PR_ADC_bp 1 /* Port A ADC bit position. */ - -#define PR_AC_bm 0x01 /* Port A Analog Comparator bit mask. */ -#define PR_AC_bp 0 /* Port A Analog Comparator bit position. */ - - -/* PR.PRPB bit masks and bit positions */ -/* PR_DAC_bm Predefined. */ -/* PR_DAC_bp Predefined. */ - -/* PR_ADC_bm Predefined. */ -/* PR_ADC_bp Predefined. */ - -/* PR_AC_bm Predefined. */ -/* PR_AC_bp Predefined. */ - - -/* PR.PRPC bit masks and bit positions */ -#define PR_TWI_bm 0x40 /* Port C Two-wire Interface bit mask. */ -#define PR_TWI_bp 6 /* Port C Two-wire Interface bit position. */ - -#define PR_USART1_bm 0x20 /* Port C USART1 bit mask. */ -#define PR_USART1_bp 5 /* Port C USART1 bit position. */ - -#define PR_USART0_bm 0x10 /* Port C USART0 bit mask. */ -#define PR_USART0_bp 4 /* Port C USART0 bit position. */ - -#define PR_SPI_bm 0x08 /* Port C SPI bit mask. */ -#define PR_SPI_bp 3 /* Port C SPI bit position. */ - -#define PR_HIRES_bm 0x04 /* Port C AWEX bit mask. */ -#define PR_HIRES_bp 2 /* Port C AWEX bit position. */ - -#define PR_TC1_bm 0x02 /* Port C Timer/Counter1 bit mask. */ -#define PR_TC1_bp 1 /* Port C Timer/Counter1 bit position. */ - -#define PR_TC0_bm 0x01 /* Port C Timer/Counter0 bit mask. */ -#define PR_TC0_bp 0 /* Port C Timer/Counter0 bit position. */ - - -/* PR.PRPD bit masks and bit positions */ -/* PR_TWI_bm Predefined. */ -/* PR_TWI_bp Predefined. */ - -/* PR_USART1_bm Predefined. */ -/* PR_USART1_bp Predefined. */ - -/* PR_USART0_bm Predefined. */ -/* PR_USART0_bp Predefined. */ - -/* PR_SPI_bm Predefined. */ -/* PR_SPI_bp Predefined. */ - -/* PR_HIRES_bm Predefined. */ -/* PR_HIRES_bp Predefined. */ - -/* PR_TC1_bm Predefined. */ -/* PR_TC1_bp Predefined. */ - -/* PR_TC0_bm Predefined. */ -/* PR_TC0_bp Predefined. */ - - -/* PR.PRPE bit masks and bit positions */ -/* PR_TWI_bm Predefined. */ -/* PR_TWI_bp Predefined. */ - -/* PR_USART1_bm Predefined. */ -/* PR_USART1_bp Predefined. */ - -/* PR_USART0_bm Predefined. */ -/* PR_USART0_bp Predefined. */ - -/* PR_SPI_bm Predefined. */ -/* PR_SPI_bp Predefined. */ - -/* PR_HIRES_bm Predefined. */ -/* PR_HIRES_bp Predefined. */ - -/* PR_TC1_bm Predefined. */ -/* PR_TC1_bp Predefined. */ - -/* PR_TC0_bm Predefined. */ -/* PR_TC0_bp Predefined. */ - - -/* PR.PRPF bit masks and bit positions */ -/* PR_TWI_bm Predefined. */ -/* PR_TWI_bp Predefined. */ - -/* PR_USART1_bm Predefined. */ -/* PR_USART1_bp Predefined. */ - -/* PR_USART0_bm Predefined. */ -/* PR_USART0_bp Predefined. */ - -/* PR_SPI_bm Predefined. */ -/* PR_SPI_bp Predefined. */ - -/* PR_HIRES_bm Predefined. */ -/* PR_HIRES_bp Predefined. */ - -/* PR_TC1_bm Predefined. */ -/* PR_TC1_bp Predefined. */ - -/* PR_TC0_bm Predefined. */ -/* PR_TC0_bp Predefined. */ - - -/* SLEEP - Sleep Controller */ -/* SLEEP.CTRL bit masks and bit positions */ -#define SLEEP_SMODE_gm 0x0E /* Sleep Mode group mask. */ -#define SLEEP_SMODE_gp 1 /* Sleep Mode group position. */ -#define SLEEP_SMODE0_bm (1<<1) /* Sleep Mode bit 0 mask. */ -#define SLEEP_SMODE0_bp 1 /* Sleep Mode bit 0 position. */ -#define SLEEP_SMODE1_bm (1<<2) /* Sleep Mode bit 1 mask. */ -#define SLEEP_SMODE1_bp 2 /* Sleep Mode bit 1 position. */ -#define SLEEP_SMODE2_bm (1<<3) /* Sleep Mode bit 2 mask. */ -#define SLEEP_SMODE2_bp 3 /* Sleep Mode bit 2 position. */ - -#define SLEEP_SEN_bm 0x01 /* Sleep Enable bit mask. */ -#define SLEEP_SEN_bp 0 /* Sleep Enable bit position. */ - - -/* OSC - Oscillator */ -/* OSC.CTRL bit masks and bit positions */ -#define OSC_PLLEN_bm 0x10 /* PLL Enable bit mask. */ -#define OSC_PLLEN_bp 4 /* PLL Enable bit position. */ - -#define OSC_XOSCEN_bm 0x08 /* External Oscillator Enable bit mask. */ -#define OSC_XOSCEN_bp 3 /* External Oscillator Enable bit position. */ - -#define OSC_RC32KEN_bm 0x04 /* Internal 32kHz RC Oscillator Enable bit mask. */ -#define OSC_RC32KEN_bp 2 /* Internal 32kHz RC Oscillator Enable bit position. */ - -#define OSC_RC32MEN_bm 0x02 /* Internal 32MHz RC Oscillator Enable bit mask. */ -#define OSC_RC32MEN_bp 1 /* Internal 32MHz RC Oscillator Enable bit position. */ - -#define OSC_RC2MEN_bm 0x01 /* Internal 2MHz RC Oscillator Enable bit mask. */ -#define OSC_RC2MEN_bp 0 /* Internal 2MHz RC Oscillator Enable bit position. */ - - -/* OSC.STATUS bit masks and bit positions */ -#define OSC_PLLRDY_bm 0x10 /* PLL Ready bit mask. */ -#define OSC_PLLRDY_bp 4 /* PLL Ready bit position. */ - -#define OSC_XOSCRDY_bm 0x08 /* External Oscillator Ready bit mask. */ -#define OSC_XOSCRDY_bp 3 /* External Oscillator Ready bit position. */ - -#define OSC_RC32KRDY_bm 0x04 /* Internal 32kHz RC Oscillator Ready bit mask. */ -#define OSC_RC32KRDY_bp 2 /* Internal 32kHz RC Oscillator Ready bit position. */ - -#define OSC_RC32MRDY_bm 0x02 /* Internal 32MHz RC Oscillator Ready bit mask. */ -#define OSC_RC32MRDY_bp 1 /* Internal 32MHz RC Oscillator Ready bit position. */ - -#define OSC_RC2MRDY_bm 0x01 /* Internal 2MHz RC Oscillator Ready bit mask. */ -#define OSC_RC2MRDY_bp 0 /* Internal 2MHz RC Oscillator Ready bit position. */ - - -/* OSC.XOSCCTRL bit masks and bit positions */ -#define OSC_FRQRANGE_gm 0xC0 /* Frequency Range group mask. */ -#define OSC_FRQRANGE_gp 6 /* Frequency Range group position. */ -#define OSC_FRQRANGE0_bm (1<<6) /* Frequency Range bit 0 mask. */ -#define OSC_FRQRANGE0_bp 6 /* Frequency Range bit 0 position. */ -#define OSC_FRQRANGE1_bm (1<<7) /* Frequency Range bit 1 mask. */ -#define OSC_FRQRANGE1_bp 7 /* Frequency Range bit 1 position. */ - -#define OSC_X32KLPM_bm 0x20 /* 32kHz XTAL OSC Low-power Mode bit mask. */ -#define OSC_X32KLPM_bp 5 /* 32kHz XTAL OSC Low-power Mode bit position. */ - -#define OSC_XOSCSEL_gm 0x0F /* External Oscillator Selection and Startup Time group mask. */ -#define OSC_XOSCSEL_gp 0 /* External Oscillator Selection and Startup Time group position. */ -#define OSC_XOSCSEL0_bm (1<<0) /* External Oscillator Selection and Startup Time bit 0 mask. */ -#define OSC_XOSCSEL0_bp 0 /* External Oscillator Selection and Startup Time bit 0 position. */ -#define OSC_XOSCSEL1_bm (1<<1) /* External Oscillator Selection and Startup Time bit 1 mask. */ -#define OSC_XOSCSEL1_bp 1 /* External Oscillator Selection and Startup Time bit 1 position. */ -#define OSC_XOSCSEL2_bm (1<<2) /* External Oscillator Selection and Startup Time bit 2 mask. */ -#define OSC_XOSCSEL2_bp 2 /* External Oscillator Selection and Startup Time bit 2 position. */ -#define OSC_XOSCSEL3_bm (1<<3) /* External Oscillator Selection and Startup Time bit 3 mask. */ -#define OSC_XOSCSEL3_bp 3 /* External Oscillator Selection and Startup Time bit 3 position. */ - - -/* OSC.XOSCFAIL bit masks and bit positions */ -#define OSC_XOSCFDIF_bm 0x02 /* Failure Detection Interrupt Flag bit mask. */ -#define OSC_XOSCFDIF_bp 1 /* Failure Detection Interrupt Flag bit position. */ - -#define OSC_XOSCFDEN_bm 0x01 /* Failure Detection Enable bit mask. */ -#define OSC_XOSCFDEN_bp 0 /* Failure Detection Enable bit position. */ - - -/* OSC.PLLCTRL bit masks and bit positions */ -#define OSC_PLLSRC_gm 0xC0 /* Clock Source group mask. */ -#define OSC_PLLSRC_gp 6 /* Clock Source group position. */ -#define OSC_PLLSRC0_bm (1<<6) /* Clock Source bit 0 mask. */ -#define OSC_PLLSRC0_bp 6 /* Clock Source bit 0 position. */ -#define OSC_PLLSRC1_bm (1<<7) /* Clock Source bit 1 mask. */ -#define OSC_PLLSRC1_bp 7 /* Clock Source bit 1 position. */ - -#define OSC_PLLFAC_gm 0x1F /* Multiplication Factor group mask. */ -#define OSC_PLLFAC_gp 0 /* Multiplication Factor group position. */ -#define OSC_PLLFAC0_bm (1<<0) /* Multiplication Factor bit 0 mask. */ -#define OSC_PLLFAC0_bp 0 /* Multiplication Factor bit 0 position. */ -#define OSC_PLLFAC1_bm (1<<1) /* Multiplication Factor bit 1 mask. */ -#define OSC_PLLFAC1_bp 1 /* Multiplication Factor bit 1 position. */ -#define OSC_PLLFAC2_bm (1<<2) /* Multiplication Factor bit 2 mask. */ -#define OSC_PLLFAC2_bp 2 /* Multiplication Factor bit 2 position. */ -#define OSC_PLLFAC3_bm (1<<3) /* Multiplication Factor bit 3 mask. */ -#define OSC_PLLFAC3_bp 3 /* Multiplication Factor bit 3 position. */ -#define OSC_PLLFAC4_bm (1<<4) /* Multiplication Factor bit 4 mask. */ -#define OSC_PLLFAC4_bp 4 /* Multiplication Factor bit 4 position. */ - - -/* OSC.DFLLCTRL bit masks and bit positions */ -#define OSC_RC32MCREF_bm 0x02 /* 32MHz Calibration Reference bit mask. */ -#define OSC_RC32MCREF_bp 1 /* 32MHz Calibration Reference bit position. */ - -#define OSC_RC2MCREF_bm 0x01 /* 2MHz Calibration Reference bit mask. */ -#define OSC_RC2MCREF_bp 0 /* 2MHz Calibration Reference bit position. */ - - -/* DFLL - DFLL */ -/* DFLL.CTRL bit masks and bit positions */ -#define DFLL_ENABLE_bm 0x01 /* DFLL Enable bit mask. */ -#define DFLL_ENABLE_bp 0 /* DFLL Enable bit position. */ - - -/* DFLL.CALA bit masks and bit positions */ -#define DFLL_CALL_gm 0x7F /* DFLL Calibration bits [6:0] group mask. */ -#define DFLL_CALL_gp 0 /* DFLL Calibration bits [6:0] group position. */ -#define DFLL_CALL0_bm (1<<0) /* DFLL Calibration bits [6:0] bit 0 mask. */ -#define DFLL_CALL0_bp 0 /* DFLL Calibration bits [6:0] bit 0 position. */ -#define DFLL_CALL1_bm (1<<1) /* DFLL Calibration bits [6:0] bit 1 mask. */ -#define DFLL_CALL1_bp 1 /* DFLL Calibration bits [6:0] bit 1 position. */ -#define DFLL_CALL2_bm (1<<2) /* DFLL Calibration bits [6:0] bit 2 mask. */ -#define DFLL_CALL2_bp 2 /* DFLL Calibration bits [6:0] bit 2 position. */ -#define DFLL_CALL3_bm (1<<3) /* DFLL Calibration bits [6:0] bit 3 mask. */ -#define DFLL_CALL3_bp 3 /* DFLL Calibration bits [6:0] bit 3 position. */ -#define DFLL_CALL4_bm (1<<4) /* DFLL Calibration bits [6:0] bit 4 mask. */ -#define DFLL_CALL4_bp 4 /* DFLL Calibration bits [6:0] bit 4 position. */ -#define DFLL_CALL5_bm (1<<5) /* DFLL Calibration bits [6:0] bit 5 mask. */ -#define DFLL_CALL5_bp 5 /* DFLL Calibration bits [6:0] bit 5 position. */ -#define DFLL_CALL6_bm (1<<6) /* DFLL Calibration bits [6:0] bit 6 mask. */ -#define DFLL_CALL6_bp 6 /* DFLL Calibration bits [6:0] bit 6 position. */ - - -/* DFLL.CALB bit masks and bit positions */ -#define DFLL_CALH_gm 0x3F /* DFLL Calibration bits [12:7] group mask. */ -#define DFLL_CALH_gp 0 /* DFLL Calibration bits [12:7] group position. */ -#define DFLL_CALH0_bm (1<<0) /* DFLL Calibration bits [12:7] bit 0 mask. */ -#define DFLL_CALH0_bp 0 /* DFLL Calibration bits [12:7] bit 0 position. */ -#define DFLL_CALH1_bm (1<<1) /* DFLL Calibration bits [12:7] bit 1 mask. */ -#define DFLL_CALH1_bp 1 /* DFLL Calibration bits [12:7] bit 1 position. */ -#define DFLL_CALH2_bm (1<<2) /* DFLL Calibration bits [12:7] bit 2 mask. */ -#define DFLL_CALH2_bp 2 /* DFLL Calibration bits [12:7] bit 2 position. */ -#define DFLL_CALH3_bm (1<<3) /* DFLL Calibration bits [12:7] bit 3 mask. */ -#define DFLL_CALH3_bp 3 /* DFLL Calibration bits [12:7] bit 3 position. */ -#define DFLL_CALH4_bm (1<<4) /* DFLL Calibration bits [12:7] bit 4 mask. */ -#define DFLL_CALH4_bp 4 /* DFLL Calibration bits [12:7] bit 4 position. */ -#define DFLL_CALH5_bm (1<<5) /* DFLL Calibration bits [12:7] bit 5 mask. */ -#define DFLL_CALH5_bp 5 /* DFLL Calibration bits [12:7] bit 5 position. */ - - -/* RST - Reset */ -/* RST.STATUS bit masks and bit positions */ -#define RST_SDRF_bm 0x40 /* Spike Detection Reset Flag bit mask. */ -#define RST_SDRF_bp 6 /* Spike Detection Reset Flag bit position. */ - -#define RST_SRF_bm 0x20 /* Software Reset Flag bit mask. */ -#define RST_SRF_bp 5 /* Software Reset Flag bit position. */ - -#define RST_PDIRF_bm 0x10 /* Programming and Debug Interface Interface Reset Flag bit mask. */ -#define RST_PDIRF_bp 4 /* Programming and Debug Interface Interface Reset Flag bit position. */ - -#define RST_WDRF_bm 0x08 /* Watchdog Reset Flag bit mask. */ -#define RST_WDRF_bp 3 /* Watchdog Reset Flag bit position. */ - -#define RST_BORF_bm 0x04 /* Brown-out Reset Flag bit mask. */ -#define RST_BORF_bp 2 /* Brown-out Reset Flag bit position. */ - -#define RST_EXTRF_bm 0x02 /* External Reset Flag bit mask. */ -#define RST_EXTRF_bp 1 /* External Reset Flag bit position. */ - -#define RST_PORF_bm 0x01 /* Power-on Reset Flag bit mask. */ -#define RST_PORF_bp 0 /* Power-on Reset Flag bit position. */ - - -/* RST.CTRL bit masks and bit positions */ -#define RST_SWRST_bm 0x01 /* Software Reset bit mask. */ -#define RST_SWRST_bp 0 /* Software Reset bit position. */ - - -/* WDT - Watch-Dog Timer */ -/* WDT.CTRL bit masks and bit positions */ -#define WDT_PER_gm 0x3C /* Period group mask. */ -#define WDT_PER_gp 2 /* Period group position. */ -#define WDT_PER0_bm (1<<2) /* Period bit 0 mask. */ -#define WDT_PER0_bp 2 /* Period bit 0 position. */ -#define WDT_PER1_bm (1<<3) /* Period bit 1 mask. */ -#define WDT_PER1_bp 3 /* Period bit 1 position. */ -#define WDT_PER2_bm (1<<4) /* Period bit 2 mask. */ -#define WDT_PER2_bp 4 /* Period bit 2 position. */ -#define WDT_PER3_bm (1<<5) /* Period bit 3 mask. */ -#define WDT_PER3_bp 5 /* Period bit 3 position. */ - -#define WDT_ENABLE_bm 0x02 /* Enable bit mask. */ -#define WDT_ENABLE_bp 1 /* Enable bit position. */ - -#define WDT_CEN_bm 0x01 /* Change Enable bit mask. */ -#define WDT_CEN_bp 0 /* Change Enable bit position. */ - - -/* WDT.WINCTRL bit masks and bit positions */ -#define WDT_WPER_gm 0x3C /* Windowed Mode Period group mask. */ -#define WDT_WPER_gp 2 /* Windowed Mode Period group position. */ -#define WDT_WPER0_bm (1<<2) /* Windowed Mode Period bit 0 mask. */ -#define WDT_WPER0_bp 2 /* Windowed Mode Period bit 0 position. */ -#define WDT_WPER1_bm (1<<3) /* Windowed Mode Period bit 1 mask. */ -#define WDT_WPER1_bp 3 /* Windowed Mode Period bit 1 position. */ -#define WDT_WPER2_bm (1<<4) /* Windowed Mode Period bit 2 mask. */ -#define WDT_WPER2_bp 4 /* Windowed Mode Period bit 2 position. */ -#define WDT_WPER3_bm (1<<5) /* Windowed Mode Period bit 3 mask. */ -#define WDT_WPER3_bp 5 /* Windowed Mode Period bit 3 position. */ - -#define WDT_WEN_bm 0x02 /* Windowed Mode Enable bit mask. */ -#define WDT_WEN_bp 1 /* Windowed Mode Enable bit position. */ - -#define WDT_WCEN_bm 0x01 /* Windowed Mode Change Enable bit mask. */ -#define WDT_WCEN_bp 0 /* Windowed Mode Change Enable bit position. */ - - -/* WDT.STATUS bit masks and bit positions */ -#define WDT_SYNCBUSY_bm 0x01 /* Syncronization busy bit mask. */ -#define WDT_SYNCBUSY_bp 0 /* Syncronization busy bit position. */ - - -/* MCU - MCU Control */ -/* MCU.MCUCR bit masks and bit positions */ -#define MCU_JTAGD_bm 0x01 /* JTAG Disable bit mask. */ -#define MCU_JTAGD_bp 0 /* JTAG Disable bit position. */ - - -/* MCU.EVSYSLOCK bit masks and bit positions */ -#define MCU_EVSYS1LOCK_bm 0x10 /* Event Channel 4-7 Lock bit mask. */ -#define MCU_EVSYS1LOCK_bp 4 /* Event Channel 4-7 Lock bit position. */ - -#define MCU_EVSYS0LOCK_bm 0x01 /* Event Channel 0-3 Lock bit mask. */ -#define MCU_EVSYS0LOCK_bp 0 /* Event Channel 0-3 Lock bit position. */ - - -/* MCU.AWEXLOCK bit masks and bit positions */ -#define MCU_AWEXELOCK_bm 0x04 /* AWeX on T/C E0 Lock bit mask. */ -#define MCU_AWEXELOCK_bp 2 /* AWeX on T/C E0 Lock bit position. */ - -#define MCU_AWEXCLOCK_bm 0x01 /* AWeX on T/C C0 Lock bit mask. */ -#define MCU_AWEXCLOCK_bp 0 /* AWeX on T/C C0 Lock bit position. */ - - -/* PMIC - Programmable Multi-level Interrupt Controller */ -/* PMIC.STATUS bit masks and bit positions */ -#define PMIC_NMIEX_bm 0x80 /* Non-maskable Interrupt Executing bit mask. */ -#define PMIC_NMIEX_bp 7 /* Non-maskable Interrupt Executing bit position. */ - -#define PMIC_HILVLEX_bm 0x04 /* High Level Interrupt Executing bit mask. */ -#define PMIC_HILVLEX_bp 2 /* High Level Interrupt Executing bit position. */ - -#define PMIC_MEDLVLEX_bm 0x02 /* Medium Level Interrupt Executing bit mask. */ -#define PMIC_MEDLVLEX_bp 1 /* Medium Level Interrupt Executing bit position. */ - -#define PMIC_LOLVLEX_bm 0x01 /* Low Level Interrupt Executing bit mask. */ -#define PMIC_LOLVLEX_bp 0 /* Low Level Interrupt Executing bit position. */ - - -/* PMIC.CTRL bit masks and bit positions */ -#define PMIC_RREN_bm 0x80 /* Round-Robin Priority Enable bit mask. */ -#define PMIC_RREN_bp 7 /* Round-Robin Priority Enable bit position. */ - -#define PMIC_IVSEL_bm 0x40 /* Interrupt Vector Select bit mask. */ -#define PMIC_IVSEL_bp 6 /* Interrupt Vector Select bit position. */ - -#define PMIC_HILVLEN_bm 0x04 /* High Level Enable bit mask. */ -#define PMIC_HILVLEN_bp 2 /* High Level Enable bit position. */ - -#define PMIC_MEDLVLEN_bm 0x02 /* Medium Level Enable bit mask. */ -#define PMIC_MEDLVLEN_bp 1 /* Medium Level Enable bit position. */ - -#define PMIC_LOLVLEN_bm 0x01 /* Low Level Enable bit mask. */ -#define PMIC_LOLVLEN_bp 0 /* Low Level Enable bit position. */ - - -/* DMA - DMA Controller */ -/* DMA_CH.CTRLA bit masks and bit positions */ -#define DMA_CH_ENABLE_bm 0x80 /* Channel Enable bit mask. */ -#define DMA_CH_ENABLE_bp 7 /* Channel Enable bit position. */ - -#define DMA_CH_RESET_bm 0x40 /* Channel Software Reset bit mask. */ -#define DMA_CH_RESET_bp 6 /* Channel Software Reset bit position. */ - -#define DMA_CH_REPEAT_bm 0x20 /* Channel Repeat Mode bit mask. */ -#define DMA_CH_REPEAT_bp 5 /* Channel Repeat Mode bit position. */ - -#define DMA_CH_TRFREQ_bm 0x10 /* Channel Transfer Request bit mask. */ -#define DMA_CH_TRFREQ_bp 4 /* Channel Transfer Request bit position. */ - -#define DMA_CH_SINGLE_bm 0x04 /* Channel Single Shot Data Transfer bit mask. */ -#define DMA_CH_SINGLE_bp 2 /* Channel Single Shot Data Transfer bit position. */ - -#define DMA_CH_BURSTLEN_gm 0x03 /* Channel Transfer Mode group mask. */ -#define DMA_CH_BURSTLEN_gp 0 /* Channel Transfer Mode group position. */ -#define DMA_CH_BURSTLEN0_bm (1<<0) /* Channel Transfer Mode bit 0 mask. */ -#define DMA_CH_BURSTLEN0_bp 0 /* Channel Transfer Mode bit 0 position. */ -#define DMA_CH_BURSTLEN1_bm (1<<1) /* Channel Transfer Mode bit 1 mask. */ -#define DMA_CH_BURSTLEN1_bp 1 /* Channel Transfer Mode bit 1 position. */ - - -/* DMA_CH.CTRLB bit masks and bit positions */ -#define DMA_CH_CHBUSY_bm 0x80 /* Block Transfer Busy bit mask. */ -#define DMA_CH_CHBUSY_bp 7 /* Block Transfer Busy bit position. */ - -#define DMA_CH_CHPEND_bm 0x40 /* Block Transfer Pending bit mask. */ -#define DMA_CH_CHPEND_bp 6 /* Block Transfer Pending bit position. */ - -#define DMA_CH_ERRIF_bm 0x20 /* Block Transfer Error Interrupt Flag bit mask. */ -#define DMA_CH_ERRIF_bp 5 /* Block Transfer Error Interrupt Flag bit position. */ - -#define DMA_CH_TRNIF_bm 0x10 /* Transaction Complete Interrup Flag bit mask. */ -#define DMA_CH_TRNIF_bp 4 /* Transaction Complete Interrup Flag bit position. */ - -#define DMA_CH_ERRINTLVL_gm 0x0C /* Transfer Error Interrupt Level group mask. */ -#define DMA_CH_ERRINTLVL_gp 2 /* Transfer Error Interrupt Level group position. */ -#define DMA_CH_ERRINTLVL0_bm (1<<2) /* Transfer Error Interrupt Level bit 0 mask. */ -#define DMA_CH_ERRINTLVL0_bp 2 /* Transfer Error Interrupt Level bit 0 position. */ -#define DMA_CH_ERRINTLVL1_bm (1<<3) /* Transfer Error Interrupt Level bit 1 mask. */ -#define DMA_CH_ERRINTLVL1_bp 3 /* Transfer Error Interrupt Level bit 1 position. */ - -#define DMA_CH_TRNINTLVL_gm 0x03 /* Transaction Complete Interrupt Level group mask. */ -#define DMA_CH_TRNINTLVL_gp 0 /* Transaction Complete Interrupt Level group position. */ -#define DMA_CH_TRNINTLVL0_bm (1<<0) /* Transaction Complete Interrupt Level bit 0 mask. */ -#define DMA_CH_TRNINTLVL0_bp 0 /* Transaction Complete Interrupt Level bit 0 position. */ -#define DMA_CH_TRNINTLVL1_bm (1<<1) /* Transaction Complete Interrupt Level bit 1 mask. */ -#define DMA_CH_TRNINTLVL1_bp 1 /* Transaction Complete Interrupt Level bit 1 position. */ - - -/* DMA_CH.ADDRCTRL bit masks and bit positions */ -#define DMA_CH_SRCRELOAD_gm 0xC0 /* Channel Source Address Reload group mask. */ -#define DMA_CH_SRCRELOAD_gp 6 /* Channel Source Address Reload group position. */ -#define DMA_CH_SRCRELOAD0_bm (1<<6) /* Channel Source Address Reload bit 0 mask. */ -#define DMA_CH_SRCRELOAD0_bp 6 /* Channel Source Address Reload bit 0 position. */ -#define DMA_CH_SRCRELOAD1_bm (1<<7) /* Channel Source Address Reload bit 1 mask. */ -#define DMA_CH_SRCRELOAD1_bp 7 /* Channel Source Address Reload bit 1 position. */ - -#define DMA_CH_SRCDIR_gm 0x30 /* Channel Source Address Mode group mask. */ -#define DMA_CH_SRCDIR_gp 4 /* Channel Source Address Mode group position. */ -#define DMA_CH_SRCDIR0_bm (1<<4) /* Channel Source Address Mode bit 0 mask. */ -#define DMA_CH_SRCDIR0_bp 4 /* Channel Source Address Mode bit 0 position. */ -#define DMA_CH_SRCDIR1_bm (1<<5) /* Channel Source Address Mode bit 1 mask. */ -#define DMA_CH_SRCDIR1_bp 5 /* Channel Source Address Mode bit 1 position. */ - -#define DMA_CH_DESTRELOAD_gm 0x0C /* Channel Destination Address Reload group mask. */ -#define DMA_CH_DESTRELOAD_gp 2 /* Channel Destination Address Reload group position. */ -#define DMA_CH_DESTRELOAD0_bm (1<<2) /* Channel Destination Address Reload bit 0 mask. */ -#define DMA_CH_DESTRELOAD0_bp 2 /* Channel Destination Address Reload bit 0 position. */ -#define DMA_CH_DESTRELOAD1_bm (1<<3) /* Channel Destination Address Reload bit 1 mask. */ -#define DMA_CH_DESTRELOAD1_bp 3 /* Channel Destination Address Reload bit 1 position. */ - -#define DMA_CH_DESTDIR_gm 0x03 /* Channel Destination Address Mode group mask. */ -#define DMA_CH_DESTDIR_gp 0 /* Channel Destination Address Mode group position. */ -#define DMA_CH_DESTDIR0_bm (1<<0) /* Channel Destination Address Mode bit 0 mask. */ -#define DMA_CH_DESTDIR0_bp 0 /* Channel Destination Address Mode bit 0 position. */ -#define DMA_CH_DESTDIR1_bm (1<<1) /* Channel Destination Address Mode bit 1 mask. */ -#define DMA_CH_DESTDIR1_bp 1 /* Channel Destination Address Mode bit 1 position. */ - - -/* DMA_CH.TRIGSRC bit masks and bit positions */ -#define DMA_CH_TRIGSRC_gm 0xFF /* Channel Trigger Source group mask. */ -#define DMA_CH_TRIGSRC_gp 0 /* Channel Trigger Source group position. */ -#define DMA_CH_TRIGSRC0_bm (1<<0) /* Channel Trigger Source bit 0 mask. */ -#define DMA_CH_TRIGSRC0_bp 0 /* Channel Trigger Source bit 0 position. */ -#define DMA_CH_TRIGSRC1_bm (1<<1) /* Channel Trigger Source bit 1 mask. */ -#define DMA_CH_TRIGSRC1_bp 1 /* Channel Trigger Source bit 1 position. */ -#define DMA_CH_TRIGSRC2_bm (1<<2) /* Channel Trigger Source bit 2 mask. */ -#define DMA_CH_TRIGSRC2_bp 2 /* Channel Trigger Source bit 2 position. */ -#define DMA_CH_TRIGSRC3_bm (1<<3) /* Channel Trigger Source bit 3 mask. */ -#define DMA_CH_TRIGSRC3_bp 3 /* Channel Trigger Source bit 3 position. */ -#define DMA_CH_TRIGSRC4_bm (1<<4) /* Channel Trigger Source bit 4 mask. */ -#define DMA_CH_TRIGSRC4_bp 4 /* Channel Trigger Source bit 4 position. */ -#define DMA_CH_TRIGSRC5_bm (1<<5) /* Channel Trigger Source bit 5 mask. */ -#define DMA_CH_TRIGSRC5_bp 5 /* Channel Trigger Source bit 5 position. */ -#define DMA_CH_TRIGSRC6_bm (1<<6) /* Channel Trigger Source bit 6 mask. */ -#define DMA_CH_TRIGSRC6_bp 6 /* Channel Trigger Source bit 6 position. */ -#define DMA_CH_TRIGSRC7_bm (1<<7) /* Channel Trigger Source bit 7 mask. */ -#define DMA_CH_TRIGSRC7_bp 7 /* Channel Trigger Source bit 7 position. */ - - -/* DMA.CTRL bit masks and bit positions */ -#define DMA_ENABLE_bm 0x80 /* Enable bit mask. */ -#define DMA_ENABLE_bp 7 /* Enable bit position. */ - -#define DMA_RESET_bm 0x40 /* Software Reset bit mask. */ -#define DMA_RESET_bp 6 /* Software Reset bit position. */ - -#define DMA_DBUFMODE_gm 0x0C /* Double Buffering Mode group mask. */ -#define DMA_DBUFMODE_gp 2 /* Double Buffering Mode group position. */ -#define DMA_DBUFMODE0_bm (1<<2) /* Double Buffering Mode bit 0 mask. */ -#define DMA_DBUFMODE0_bp 2 /* Double Buffering Mode bit 0 position. */ -#define DMA_DBUFMODE1_bm (1<<3) /* Double Buffering Mode bit 1 mask. */ -#define DMA_DBUFMODE1_bp 3 /* Double Buffering Mode bit 1 position. */ - -#define DMA_PRIMODE_gm 0x03 /* Channel Priority Mode group mask. */ -#define DMA_PRIMODE_gp 0 /* Channel Priority Mode group position. */ -#define DMA_PRIMODE0_bm (1<<0) /* Channel Priority Mode bit 0 mask. */ -#define DMA_PRIMODE0_bp 0 /* Channel Priority Mode bit 0 position. */ -#define DMA_PRIMODE1_bm (1<<1) /* Channel Priority Mode bit 1 mask. */ -#define DMA_PRIMODE1_bp 1 /* Channel Priority Mode bit 1 position. */ - - -/* DMA.INTFLAGS bit masks and bit positions */ -#define DMA_CH3ERRIF_bm 0x80 /* Channel 3 Block Transfer Error Interrupt Flag bit mask. */ -#define DMA_CH3ERRIF_bp 7 /* Channel 3 Block Transfer Error Interrupt Flag bit position. */ - -#define DMA_CH2ERRIF_bm 0x40 /* Channel 2 Block Transfer Error Interrupt Flag bit mask. */ -#define DMA_CH2ERRIF_bp 6 /* Channel 2 Block Transfer Error Interrupt Flag bit position. */ - -#define DMA_CH1ERRIF_bm 0x20 /* Channel 1 Block Transfer Error Interrupt Flag bit mask. */ -#define DMA_CH1ERRIF_bp 5 /* Channel 1 Block Transfer Error Interrupt Flag bit position. */ - -#define DMA_CH0ERRIF_bm 0x10 /* Channel 0 Block Transfer Error Interrupt Flag bit mask. */ -#define DMA_CH0ERRIF_bp 4 /* Channel 0 Block Transfer Error Interrupt Flag bit position. */ - -#define DMA_CH3TRNIF_bm 0x08 /* Channel 3 Transaction Complete Interrupt Flag bit mask. */ -#define DMA_CH3TRNIF_bp 3 /* Channel 3 Transaction Complete Interrupt Flag bit position. */ - -#define DMA_CH2TRNIF_bm 0x04 /* Channel 2 Transaction Complete Interrupt Flag bit mask. */ -#define DMA_CH2TRNIF_bp 2 /* Channel 2 Transaction Complete Interrupt Flag bit position. */ - -#define DMA_CH1TRNIF_bm 0x02 /* Channel 1 Transaction Complete Interrupt Flag bit mask. */ -#define DMA_CH1TRNIF_bp 1 /* Channel 1 Transaction Complete Interrupt Flag bit position. */ - -#define DMA_CH0TRNIF_bm 0x01 /* Channel 0 Transaction Complete Interrupt Flag bit mask. */ -#define DMA_CH0TRNIF_bp 0 /* Channel 0 Transaction Complete Interrupt Flag bit position. */ - - -/* DMA.STATUS bit masks and bit positions */ -#define DMA_CH3BUSY_bm 0x80 /* Channel 3 Block Transfer Busy bit mask. */ -#define DMA_CH3BUSY_bp 7 /* Channel 3 Block Transfer Busy bit position. */ - -#define DMA_CH2BUSY_bm 0x40 /* Channel 2 Block Transfer Busy bit mask. */ -#define DMA_CH2BUSY_bp 6 /* Channel 2 Block Transfer Busy bit position. */ - -#define DMA_CH1BUSY_bm 0x20 /* Channel 1 Block Transfer Busy bit mask. */ -#define DMA_CH1BUSY_bp 5 /* Channel 1 Block Transfer Busy bit position. */ - -#define DMA_CH0BUSY_bm 0x10 /* Channel 0 Block Transfer Busy bit mask. */ -#define DMA_CH0BUSY_bp 4 /* Channel 0 Block Transfer Busy bit position. */ - -#define DMA_CH3PEND_bm 0x08 /* Channel 3 Block Transfer Pending bit mask. */ -#define DMA_CH3PEND_bp 3 /* Channel 3 Block Transfer Pending bit position. */ - -#define DMA_CH2PEND_bm 0x04 /* Channel 2 Block Transfer Pending bit mask. */ -#define DMA_CH2PEND_bp 2 /* Channel 2 Block Transfer Pending bit position. */ - -#define DMA_CH1PEND_bm 0x02 /* Channel 1 Block Transfer Pending bit mask. */ -#define DMA_CH1PEND_bp 1 /* Channel 1 Block Transfer Pending bit position. */ - -#define DMA_CH0PEND_bm 0x01 /* Channel 0 Block Transfer Pending bit mask. */ -#define DMA_CH0PEND_bp 0 /* Channel 0 Block Transfer Pending bit position. */ - - -/* EVSYS - Event System */ -/* EVSYS.CH0MUX bit masks and bit positions */ -#define EVSYS_CHMUX_gm 0xFF /* Event Channel 0 Multiplexer group mask. */ -#define EVSYS_CHMUX_gp 0 /* Event Channel 0 Multiplexer group position. */ -#define EVSYS_CHMUX0_bm (1<<0) /* Event Channel 0 Multiplexer bit 0 mask. */ -#define EVSYS_CHMUX0_bp 0 /* Event Channel 0 Multiplexer bit 0 position. */ -#define EVSYS_CHMUX1_bm (1<<1) /* Event Channel 0 Multiplexer bit 1 mask. */ -#define EVSYS_CHMUX1_bp 1 /* Event Channel 0 Multiplexer bit 1 position. */ -#define EVSYS_CHMUX2_bm (1<<2) /* Event Channel 0 Multiplexer bit 2 mask. */ -#define EVSYS_CHMUX2_bp 2 /* Event Channel 0 Multiplexer bit 2 position. */ -#define EVSYS_CHMUX3_bm (1<<3) /* Event Channel 0 Multiplexer bit 3 mask. */ -#define EVSYS_CHMUX3_bp 3 /* Event Channel 0 Multiplexer bit 3 position. */ -#define EVSYS_CHMUX4_bm (1<<4) /* Event Channel 0 Multiplexer bit 4 mask. */ -#define EVSYS_CHMUX4_bp 4 /* Event Channel 0 Multiplexer bit 4 position. */ -#define EVSYS_CHMUX5_bm (1<<5) /* Event Channel 0 Multiplexer bit 5 mask. */ -#define EVSYS_CHMUX5_bp 5 /* Event Channel 0 Multiplexer bit 5 position. */ -#define EVSYS_CHMUX6_bm (1<<6) /* Event Channel 0 Multiplexer bit 6 mask. */ -#define EVSYS_CHMUX6_bp 6 /* Event Channel 0 Multiplexer bit 6 position. */ -#define EVSYS_CHMUX7_bm (1<<7) /* Event Channel 0 Multiplexer bit 7 mask. */ -#define EVSYS_CHMUX7_bp 7 /* Event Channel 0 Multiplexer bit 7 position. */ - - -/* EVSYS.CH1MUX bit masks and bit positions */ -/* EVSYS_CHMUX_gm Predefined. */ -/* EVSYS_CHMUX_gp Predefined. */ -/* EVSYS_CHMUX0_bm Predefined. */ -/* EVSYS_CHMUX0_bp Predefined. */ -/* EVSYS_CHMUX1_bm Predefined. */ -/* EVSYS_CHMUX1_bp Predefined. */ -/* EVSYS_CHMUX2_bm Predefined. */ -/* EVSYS_CHMUX2_bp Predefined. */ -/* EVSYS_CHMUX3_bm Predefined. */ -/* EVSYS_CHMUX3_bp Predefined. */ -/* EVSYS_CHMUX4_bm Predefined. */ -/* EVSYS_CHMUX4_bp Predefined. */ -/* EVSYS_CHMUX5_bm Predefined. */ -/* EVSYS_CHMUX5_bp Predefined. */ -/* EVSYS_CHMUX6_bm Predefined. */ -/* EVSYS_CHMUX6_bp Predefined. */ -/* EVSYS_CHMUX7_bm Predefined. */ -/* EVSYS_CHMUX7_bp Predefined. */ - - -/* EVSYS.CH2MUX bit masks and bit positions */ -/* EVSYS_CHMUX_gm Predefined. */ -/* EVSYS_CHMUX_gp Predefined. */ -/* EVSYS_CHMUX0_bm Predefined. */ -/* EVSYS_CHMUX0_bp Predefined. */ -/* EVSYS_CHMUX1_bm Predefined. */ -/* EVSYS_CHMUX1_bp Predefined. */ -/* EVSYS_CHMUX2_bm Predefined. */ -/* EVSYS_CHMUX2_bp Predefined. */ -/* EVSYS_CHMUX3_bm Predefined. */ -/* EVSYS_CHMUX3_bp Predefined. */ -/* EVSYS_CHMUX4_bm Predefined. */ -/* EVSYS_CHMUX4_bp Predefined. */ -/* EVSYS_CHMUX5_bm Predefined. */ -/* EVSYS_CHMUX5_bp Predefined. */ -/* EVSYS_CHMUX6_bm Predefined. */ -/* EVSYS_CHMUX6_bp Predefined. */ -/* EVSYS_CHMUX7_bm Predefined. */ -/* EVSYS_CHMUX7_bp Predefined. */ - - -/* EVSYS.CH3MUX bit masks and bit positions */ -/* EVSYS_CHMUX_gm Predefined. */ -/* EVSYS_CHMUX_gp Predefined. */ -/* EVSYS_CHMUX0_bm Predefined. */ -/* EVSYS_CHMUX0_bp Predefined. */ -/* EVSYS_CHMUX1_bm Predefined. */ -/* EVSYS_CHMUX1_bp Predefined. */ -/* EVSYS_CHMUX2_bm Predefined. */ -/* EVSYS_CHMUX2_bp Predefined. */ -/* EVSYS_CHMUX3_bm Predefined. */ -/* EVSYS_CHMUX3_bp Predefined. */ -/* EVSYS_CHMUX4_bm Predefined. */ -/* EVSYS_CHMUX4_bp Predefined. */ -/* EVSYS_CHMUX5_bm Predefined. */ -/* EVSYS_CHMUX5_bp Predefined. */ -/* EVSYS_CHMUX6_bm Predefined. */ -/* EVSYS_CHMUX6_bp Predefined. */ -/* EVSYS_CHMUX7_bm Predefined. */ -/* EVSYS_CHMUX7_bp Predefined. */ - - -/* EVSYS.CH4MUX bit masks and bit positions */ -/* EVSYS_CHMUX_gm Predefined. */ -/* EVSYS_CHMUX_gp Predefined. */ -/* EVSYS_CHMUX0_bm Predefined. */ -/* EVSYS_CHMUX0_bp Predefined. */ -/* EVSYS_CHMUX1_bm Predefined. */ -/* EVSYS_CHMUX1_bp Predefined. */ -/* EVSYS_CHMUX2_bm Predefined. */ -/* EVSYS_CHMUX2_bp Predefined. */ -/* EVSYS_CHMUX3_bm Predefined. */ -/* EVSYS_CHMUX3_bp Predefined. */ -/* EVSYS_CHMUX4_bm Predefined. */ -/* EVSYS_CHMUX4_bp Predefined. */ -/* EVSYS_CHMUX5_bm Predefined. */ -/* EVSYS_CHMUX5_bp Predefined. */ -/* EVSYS_CHMUX6_bm Predefined. */ -/* EVSYS_CHMUX6_bp Predefined. */ -/* EVSYS_CHMUX7_bm Predefined. */ -/* EVSYS_CHMUX7_bp Predefined. */ - - -/* EVSYS.CH5MUX bit masks and bit positions */ -/* EVSYS_CHMUX_gm Predefined. */ -/* EVSYS_CHMUX_gp Predefined. */ -/* EVSYS_CHMUX0_bm Predefined. */ -/* EVSYS_CHMUX0_bp Predefined. */ -/* EVSYS_CHMUX1_bm Predefined. */ -/* EVSYS_CHMUX1_bp Predefined. */ -/* EVSYS_CHMUX2_bm Predefined. */ -/* EVSYS_CHMUX2_bp Predefined. */ -/* EVSYS_CHMUX3_bm Predefined. */ -/* EVSYS_CHMUX3_bp Predefined. */ -/* EVSYS_CHMUX4_bm Predefined. */ -/* EVSYS_CHMUX4_bp Predefined. */ -/* EVSYS_CHMUX5_bm Predefined. */ -/* EVSYS_CHMUX5_bp Predefined. */ -/* EVSYS_CHMUX6_bm Predefined. */ -/* EVSYS_CHMUX6_bp Predefined. */ -/* EVSYS_CHMUX7_bm Predefined. */ -/* EVSYS_CHMUX7_bp Predefined. */ - - -/* EVSYS.CH6MUX bit masks and bit positions */ -/* EVSYS_CHMUX_gm Predefined. */ -/* EVSYS_CHMUX_gp Predefined. */ -/* EVSYS_CHMUX0_bm Predefined. */ -/* EVSYS_CHMUX0_bp Predefined. */ -/* EVSYS_CHMUX1_bm Predefined. */ -/* EVSYS_CHMUX1_bp Predefined. */ -/* EVSYS_CHMUX2_bm Predefined. */ -/* EVSYS_CHMUX2_bp Predefined. */ -/* EVSYS_CHMUX3_bm Predefined. */ -/* EVSYS_CHMUX3_bp Predefined. */ -/* EVSYS_CHMUX4_bm Predefined. */ -/* EVSYS_CHMUX4_bp Predefined. */ -/* EVSYS_CHMUX5_bm Predefined. */ -/* EVSYS_CHMUX5_bp Predefined. */ -/* EVSYS_CHMUX6_bm Predefined. */ -/* EVSYS_CHMUX6_bp Predefined. */ -/* EVSYS_CHMUX7_bm Predefined. */ -/* EVSYS_CHMUX7_bp Predefined. */ - - -/* EVSYS.CH7MUX bit masks and bit positions */ -/* EVSYS_CHMUX_gm Predefined. */ -/* EVSYS_CHMUX_gp Predefined. */ -/* EVSYS_CHMUX0_bm Predefined. */ -/* EVSYS_CHMUX0_bp Predefined. */ -/* EVSYS_CHMUX1_bm Predefined. */ -/* EVSYS_CHMUX1_bp Predefined. */ -/* EVSYS_CHMUX2_bm Predefined. */ -/* EVSYS_CHMUX2_bp Predefined. */ -/* EVSYS_CHMUX3_bm Predefined. */ -/* EVSYS_CHMUX3_bp Predefined. */ -/* EVSYS_CHMUX4_bm Predefined. */ -/* EVSYS_CHMUX4_bp Predefined. */ -/* EVSYS_CHMUX5_bm Predefined. */ -/* EVSYS_CHMUX5_bp Predefined. */ -/* EVSYS_CHMUX6_bm Predefined. */ -/* EVSYS_CHMUX6_bp Predefined. */ -/* EVSYS_CHMUX7_bm Predefined. */ -/* EVSYS_CHMUX7_bp Predefined. */ - - -/* EVSYS.CH0CTRL bit masks and bit positions */ -#define EVSYS_QDIRM_gm 0x60 /* Quadrature Decoder Index Recognition Mode group mask. */ -#define EVSYS_QDIRM_gp 5 /* Quadrature Decoder Index Recognition Mode group position. */ -#define EVSYS_QDIRM0_bm (1<<5) /* Quadrature Decoder Index Recognition Mode bit 0 mask. */ -#define EVSYS_QDIRM0_bp 5 /* Quadrature Decoder Index Recognition Mode bit 0 position. */ -#define EVSYS_QDIRM1_bm (1<<6) /* Quadrature Decoder Index Recognition Mode bit 1 mask. */ -#define EVSYS_QDIRM1_bp 6 /* Quadrature Decoder Index Recognition Mode bit 1 position. */ - -#define EVSYS_QDIEN_bm 0x10 /* Quadrature Decoder Index Enable bit mask. */ -#define EVSYS_QDIEN_bp 4 /* Quadrature Decoder Index Enable bit position. */ - -#define EVSYS_QDEN_bm 0x08 /* Quadrature Decoder Enable bit mask. */ -#define EVSYS_QDEN_bp 3 /* Quadrature Decoder Enable bit position. */ - -#define EVSYS_DIGFILT_gm 0x07 /* Digital Filter group mask. */ -#define EVSYS_DIGFILT_gp 0 /* Digital Filter group position. */ -#define EVSYS_DIGFILT0_bm (1<<0) /* Digital Filter bit 0 mask. */ -#define EVSYS_DIGFILT0_bp 0 /* Digital Filter bit 0 position. */ -#define EVSYS_DIGFILT1_bm (1<<1) /* Digital Filter bit 1 mask. */ -#define EVSYS_DIGFILT1_bp 1 /* Digital Filter bit 1 position. */ -#define EVSYS_DIGFILT2_bm (1<<2) /* Digital Filter bit 2 mask. */ -#define EVSYS_DIGFILT2_bp 2 /* Digital Filter bit 2 position. */ - - -/* EVSYS.CH1CTRL bit masks and bit positions */ -/* EVSYS_DIGFILT_gm Predefined. */ -/* EVSYS_DIGFILT_gp Predefined. */ -/* EVSYS_DIGFILT0_bm Predefined. */ -/* EVSYS_DIGFILT0_bp Predefined. */ -/* EVSYS_DIGFILT1_bm Predefined. */ -/* EVSYS_DIGFILT1_bp Predefined. */ -/* EVSYS_DIGFILT2_bm Predefined. */ -/* EVSYS_DIGFILT2_bp Predefined. */ - - -/* EVSYS.CH2CTRL bit masks and bit positions */ -/* EVSYS_QDIRM_gm Predefined. */ -/* EVSYS_QDIRM_gp Predefined. */ -/* EVSYS_QDIRM0_bm Predefined. */ -/* EVSYS_QDIRM0_bp Predefined. */ -/* EVSYS_QDIRM1_bm Predefined. */ -/* EVSYS_QDIRM1_bp Predefined. */ - -/* EVSYS_QDIEN_bm Predefined. */ -/* EVSYS_QDIEN_bp Predefined. */ - -/* EVSYS_QDEN_bm Predefined. */ -/* EVSYS_QDEN_bp Predefined. */ - -/* EVSYS_DIGFILT_gm Predefined. */ -/* EVSYS_DIGFILT_gp Predefined. */ -/* EVSYS_DIGFILT0_bm Predefined. */ -/* EVSYS_DIGFILT0_bp Predefined. */ -/* EVSYS_DIGFILT1_bm Predefined. */ -/* EVSYS_DIGFILT1_bp Predefined. */ -/* EVSYS_DIGFILT2_bm Predefined. */ -/* EVSYS_DIGFILT2_bp Predefined. */ - - -/* EVSYS.CH3CTRL bit masks and bit positions */ -/* EVSYS_DIGFILT_gm Predefined. */ -/* EVSYS_DIGFILT_gp Predefined. */ -/* EVSYS_DIGFILT0_bm Predefined. */ -/* EVSYS_DIGFILT0_bp Predefined. */ -/* EVSYS_DIGFILT1_bm Predefined. */ -/* EVSYS_DIGFILT1_bp Predefined. */ -/* EVSYS_DIGFILT2_bm Predefined. */ -/* EVSYS_DIGFILT2_bp Predefined. */ - - -/* EVSYS.CH4CTRL bit masks and bit positions */ -/* EVSYS_QDIRM_gm Predefined. */ -/* EVSYS_QDIRM_gp Predefined. */ -/* EVSYS_QDIRM0_bm Predefined. */ -/* EVSYS_QDIRM0_bp Predefined. */ -/* EVSYS_QDIRM1_bm Predefined. */ -/* EVSYS_QDIRM1_bp Predefined. */ - -/* EVSYS_QDIEN_bm Predefined. */ -/* EVSYS_QDIEN_bp Predefined. */ - -/* EVSYS_QDEN_bm Predefined. */ -/* EVSYS_QDEN_bp Predefined. */ - -/* EVSYS_DIGFILT_gm Predefined. */ -/* EVSYS_DIGFILT_gp Predefined. */ -/* EVSYS_DIGFILT0_bm Predefined. */ -/* EVSYS_DIGFILT0_bp Predefined. */ -/* EVSYS_DIGFILT1_bm Predefined. */ -/* EVSYS_DIGFILT1_bp Predefined. */ -/* EVSYS_DIGFILT2_bm Predefined. */ -/* EVSYS_DIGFILT2_bp Predefined. */ - - -/* EVSYS.CH5CTRL bit masks and bit positions */ -/* EVSYS_DIGFILT_gm Predefined. */ -/* EVSYS_DIGFILT_gp Predefined. */ -/* EVSYS_DIGFILT0_bm Predefined. */ -/* EVSYS_DIGFILT0_bp Predefined. */ -/* EVSYS_DIGFILT1_bm Predefined. */ -/* EVSYS_DIGFILT1_bp Predefined. */ -/* EVSYS_DIGFILT2_bm Predefined. */ -/* EVSYS_DIGFILT2_bp Predefined. */ - - -/* EVSYS.CH6CTRL bit masks and bit positions */ -/* EVSYS_DIGFILT_gm Predefined. */ -/* EVSYS_DIGFILT_gp Predefined. */ -/* EVSYS_DIGFILT0_bm Predefined. */ -/* EVSYS_DIGFILT0_bp Predefined. */ -/* EVSYS_DIGFILT1_bm Predefined. */ -/* EVSYS_DIGFILT1_bp Predefined. */ -/* EVSYS_DIGFILT2_bm Predefined. */ -/* EVSYS_DIGFILT2_bp Predefined. */ - - -/* EVSYS.CH7CTRL bit masks and bit positions */ -/* EVSYS_DIGFILT_gm Predefined. */ -/* EVSYS_DIGFILT_gp Predefined. */ -/* EVSYS_DIGFILT0_bm Predefined. */ -/* EVSYS_DIGFILT0_bp Predefined. */ -/* EVSYS_DIGFILT1_bm Predefined. */ -/* EVSYS_DIGFILT1_bp Predefined. */ -/* EVSYS_DIGFILT2_bm Predefined. */ -/* EVSYS_DIGFILT2_bp Predefined. */ - - -/* NVM - Non Volatile Memory Controller */ -/* NVM.CMD bit masks and bit positions */ -#define NVM_CMD_gm 0xFF /* Command group mask. */ -#define NVM_CMD_gp 0 /* Command group position. */ -#define NVM_CMD0_bm (1<<0) /* Command bit 0 mask. */ -#define NVM_CMD0_bp 0 /* Command bit 0 position. */ -#define NVM_CMD1_bm (1<<1) /* Command bit 1 mask. */ -#define NVM_CMD1_bp 1 /* Command bit 1 position. */ -#define NVM_CMD2_bm (1<<2) /* Command bit 2 mask. */ -#define NVM_CMD2_bp 2 /* Command bit 2 position. */ -#define NVM_CMD3_bm (1<<3) /* Command bit 3 mask. */ -#define NVM_CMD3_bp 3 /* Command bit 3 position. */ -#define NVM_CMD4_bm (1<<4) /* Command bit 4 mask. */ -#define NVM_CMD4_bp 4 /* Command bit 4 position. */ -#define NVM_CMD5_bm (1<<5) /* Command bit 5 mask. */ -#define NVM_CMD5_bp 5 /* Command bit 5 position. */ -#define NVM_CMD6_bm (1<<6) /* Command bit 6 mask. */ -#define NVM_CMD6_bp 6 /* Command bit 6 position. */ -#define NVM_CMD7_bm (1<<7) /* Command bit 7 mask. */ -#define NVM_CMD7_bp 7 /* Command bit 7 position. */ - - -/* NVM.CTRLA bit masks and bit positions */ -#define NVM_CMDEX_bm 0x01 /* Command Execute bit mask. */ -#define NVM_CMDEX_bp 0 /* Command Execute bit position. */ - - -/* NVM.CTRLB bit masks and bit positions */ -#define NVM_EEMAPEN_bm 0x08 /* EEPROM Mapping Enable bit mask. */ -#define NVM_EEMAPEN_bp 3 /* EEPROM Mapping Enable bit position. */ - -#define NVM_FPRM_bm 0x04 /* Flash Power Reduction Enable bit mask. */ -#define NVM_FPRM_bp 2 /* Flash Power Reduction Enable bit position. */ - -#define NVM_EPRM_bm 0x02 /* EEPROM Power Reduction Enable bit mask. */ -#define NVM_EPRM_bp 1 /* EEPROM Power Reduction Enable bit position. */ - -#define NVM_SPMLOCK_bm 0x01 /* SPM Lock bit mask. */ -#define NVM_SPMLOCK_bp 0 /* SPM Lock bit position. */ - - -/* NVM.INTCTRL bit masks and bit positions */ -#define NVM_SPMLVL_gm 0x0C /* SPM Interrupt Level group mask. */ -#define NVM_SPMLVL_gp 2 /* SPM Interrupt Level group position. */ -#define NVM_SPMLVL0_bm (1<<2) /* SPM Interrupt Level bit 0 mask. */ -#define NVM_SPMLVL0_bp 2 /* SPM Interrupt Level bit 0 position. */ -#define NVM_SPMLVL1_bm (1<<3) /* SPM Interrupt Level bit 1 mask. */ -#define NVM_SPMLVL1_bp 3 /* SPM Interrupt Level bit 1 position. */ - -#define NVM_EELVL_gm 0x03 /* EEPROM Interrupt Level group mask. */ -#define NVM_EELVL_gp 0 /* EEPROM Interrupt Level group position. */ -#define NVM_EELVL0_bm (1<<0) /* EEPROM Interrupt Level bit 0 mask. */ -#define NVM_EELVL0_bp 0 /* EEPROM Interrupt Level bit 0 position. */ -#define NVM_EELVL1_bm (1<<1) /* EEPROM Interrupt Level bit 1 mask. */ -#define NVM_EELVL1_bp 1 /* EEPROM Interrupt Level bit 1 position. */ - - -/* NVM.STATUS bit masks and bit positions */ -#define NVM_NVMBUSY_bm 0x80 /* Non-volatile Memory Busy bit mask. */ -#define NVM_NVMBUSY_bp 7 /* Non-volatile Memory Busy bit position. */ - -#define NVM_FBUSY_bm 0x40 /* Flash Memory Busy bit mask. */ -#define NVM_FBUSY_bp 6 /* Flash Memory Busy bit position. */ - -#define NVM_EELOAD_bm 0x02 /* EEPROM Page Buffer Active Loading bit mask. */ -#define NVM_EELOAD_bp 1 /* EEPROM Page Buffer Active Loading bit position. */ - -#define NVM_FLOAD_bm 0x01 /* Flash Page Buffer Active Loading bit mask. */ -#define NVM_FLOAD_bp 0 /* Flash Page Buffer Active Loading bit position. */ - - -/* NVM.LOCKBITS bit masks and bit positions */ -#define NVM_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ -#define NVM_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ -#define NVM_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ -#define NVM_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ -#define NVM_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ -#define NVM_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ - -#define NVM_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ -#define NVM_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ -#define NVM_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ -#define NVM_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ -#define NVM_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ -#define NVM_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ - -#define NVM_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ -#define NVM_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ -#define NVM_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ -#define NVM_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ -#define NVM_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ -#define NVM_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ - -#define NVM_LB_gm 0x03 /* Lock Bits group mask. */ -#define NVM_LB_gp 0 /* Lock Bits group position. */ -#define NVM_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ -#define NVM_LB0_bp 0 /* Lock Bits bit 0 position. */ -#define NVM_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ -#define NVM_LB1_bp 1 /* Lock Bits bit 1 position. */ - - -/* NVM_LOCKBITS.LOCKBITS bit masks and bit positions */ -#define NVM_LOCKBITS_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ -#define NVM_LOCKBITS_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ -#define NVM_LOCKBITS_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ -#define NVM_LOCKBITS_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ -#define NVM_LOCKBITS_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ -#define NVM_LOCKBITS_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ - -#define NVM_LOCKBITS_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ -#define NVM_LOCKBITS_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ -#define NVM_LOCKBITS_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ -#define NVM_LOCKBITS_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ -#define NVM_LOCKBITS_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ -#define NVM_LOCKBITS_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ - -#define NVM_LOCKBITS_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ -#define NVM_LOCKBITS_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ -#define NVM_LOCKBITS_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ -#define NVM_LOCKBITS_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ -#define NVM_LOCKBITS_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ -#define NVM_LOCKBITS_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ - -#define NVM_LOCKBITS_LB_gm 0x03 /* Lock Bits group mask. */ -#define NVM_LOCKBITS_LB_gp 0 /* Lock Bits group position. */ -#define NVM_LOCKBITS_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ -#define NVM_LOCKBITS_LB0_bp 0 /* Lock Bits bit 0 position. */ -#define NVM_LOCKBITS_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ -#define NVM_LOCKBITS_LB1_bp 1 /* Lock Bits bit 1 position. */ - - -/* NVM_FUSES.FUSEBYTE0 bit masks and bit positions */ -#define NVM_FUSES_JTAGUSERID_gm 0xFF /* JTAG User ID group mask. */ -#define NVM_FUSES_JTAGUSERID_gp 0 /* JTAG User ID group position. */ -#define NVM_FUSES_JTAGUSERID0_bm (1<<0) /* JTAG User ID bit 0 mask. */ -#define NVM_FUSES_JTAGUSERID0_bp 0 /* JTAG User ID bit 0 position. */ -#define NVM_FUSES_JTAGUSERID1_bm (1<<1) /* JTAG User ID bit 1 mask. */ -#define NVM_FUSES_JTAGUSERID1_bp 1 /* JTAG User ID bit 1 position. */ -#define NVM_FUSES_JTAGUSERID2_bm (1<<2) /* JTAG User ID bit 2 mask. */ -#define NVM_FUSES_JTAGUSERID2_bp 2 /* JTAG User ID bit 2 position. */ -#define NVM_FUSES_JTAGUSERID3_bm (1<<3) /* JTAG User ID bit 3 mask. */ -#define NVM_FUSES_JTAGUSERID3_bp 3 /* JTAG User ID bit 3 position. */ -#define NVM_FUSES_JTAGUSERID4_bm (1<<4) /* JTAG User ID bit 4 mask. */ -#define NVM_FUSES_JTAGUSERID4_bp 4 /* JTAG User ID bit 4 position. */ -#define NVM_FUSES_JTAGUSERID5_bm (1<<5) /* JTAG User ID bit 5 mask. */ -#define NVM_FUSES_JTAGUSERID5_bp 5 /* JTAG User ID bit 5 position. */ -#define NVM_FUSES_JTAGUSERID6_bm (1<<6) /* JTAG User ID bit 6 mask. */ -#define NVM_FUSES_JTAGUSERID6_bp 6 /* JTAG User ID bit 6 position. */ -#define NVM_FUSES_JTAGUSERID7_bm (1<<7) /* JTAG User ID bit 7 mask. */ -#define NVM_FUSES_JTAGUSERID7_bp 7 /* JTAG User ID bit 7 position. */ - - -/* NVM_FUSES.FUSEBYTE1 bit masks and bit positions */ -#define NVM_FUSES_WDWP_gm 0xF0 /* Watchdog Window Timeout Period group mask. */ -#define NVM_FUSES_WDWP_gp 4 /* Watchdog Window Timeout Period group position. */ -#define NVM_FUSES_WDWP0_bm (1<<4) /* Watchdog Window Timeout Period bit 0 mask. */ -#define NVM_FUSES_WDWP0_bp 4 /* Watchdog Window Timeout Period bit 0 position. */ -#define NVM_FUSES_WDWP1_bm (1<<5) /* Watchdog Window Timeout Period bit 1 mask. */ -#define NVM_FUSES_WDWP1_bp 5 /* Watchdog Window Timeout Period bit 1 position. */ -#define NVM_FUSES_WDWP2_bm (1<<6) /* Watchdog Window Timeout Period bit 2 mask. */ -#define NVM_FUSES_WDWP2_bp 6 /* Watchdog Window Timeout Period bit 2 position. */ -#define NVM_FUSES_WDWP3_bm (1<<7) /* Watchdog Window Timeout Period bit 3 mask. */ -#define NVM_FUSES_WDWP3_bp 7 /* Watchdog Window Timeout Period bit 3 position. */ - -#define NVM_FUSES_WDP_gm 0x0F /* Watchdog Timeout Period group mask. */ -#define NVM_FUSES_WDP_gp 0 /* Watchdog Timeout Period group position. */ -#define NVM_FUSES_WDP0_bm (1<<0) /* Watchdog Timeout Period bit 0 mask. */ -#define NVM_FUSES_WDP0_bp 0 /* Watchdog Timeout Period bit 0 position. */ -#define NVM_FUSES_WDP1_bm (1<<1) /* Watchdog Timeout Period bit 1 mask. */ -#define NVM_FUSES_WDP1_bp 1 /* Watchdog Timeout Period bit 1 position. */ -#define NVM_FUSES_WDP2_bm (1<<2) /* Watchdog Timeout Period bit 2 mask. */ -#define NVM_FUSES_WDP2_bp 2 /* Watchdog Timeout Period bit 2 position. */ -#define NVM_FUSES_WDP3_bm (1<<3) /* Watchdog Timeout Period bit 3 mask. */ -#define NVM_FUSES_WDP3_bp 3 /* Watchdog Timeout Period bit 3 position. */ - - -/* NVM_FUSES.FUSEBYTE2 bit masks and bit positions */ -#define NVM_FUSES_DVSDON_bm 0x80 /* Spike Detector Enable bit mask. */ -#define NVM_FUSES_DVSDON_bp 7 /* Spike Detector Enable bit position. */ - -#define NVM_FUSES_BOOTRST_bm 0x40 /* Boot Loader Section Reset Vector bit mask. */ -#define NVM_FUSES_BOOTRST_bp 6 /* Boot Loader Section Reset Vector bit position. */ - -#define NVM_FUSES_BODPD_gm 0x03 /* BOD Operation in Power-Down Mode group mask. */ -#define NVM_FUSES_BODPD_gp 0 /* BOD Operation in Power-Down Mode group position. */ -#define NVM_FUSES_BODPD0_bm (1<<0) /* BOD Operation in Power-Down Mode bit 0 mask. */ -#define NVM_FUSES_BODPD0_bp 0 /* BOD Operation in Power-Down Mode bit 0 position. */ -#define NVM_FUSES_BODPD1_bm (1<<1) /* BOD Operation in Power-Down Mode bit 1 mask. */ -#define NVM_FUSES_BODPD1_bp 1 /* BOD Operation in Power-Down Mode bit 1 position. */ - - -/* NVM_FUSES.FUSEBYTE4 bit masks and bit positions */ -#define NVM_FUSES_SUT_gm 0x0C /* Start-up Time group mask. */ -#define NVM_FUSES_SUT_gp 2 /* Start-up Time group position. */ -#define NVM_FUSES_SUT0_bm (1<<2) /* Start-up Time bit 0 mask. */ -#define NVM_FUSES_SUT0_bp 2 /* Start-up Time bit 0 position. */ -#define NVM_FUSES_SUT1_bm (1<<3) /* Start-up Time bit 1 mask. */ -#define NVM_FUSES_SUT1_bp 3 /* Start-up Time bit 1 position. */ - -#define NVM_FUSES_WDLOCK_bm 0x02 /* Watchdog Timer Lock bit mask. */ -#define NVM_FUSES_WDLOCK_bp 1 /* Watchdog Timer Lock bit position. */ - -#define NVM_FUSES_JTAGEN_bm 0x01 /* JTAG Interface Enable bit mask. */ -#define NVM_FUSES_JTAGEN_bp 0 /* JTAG Interface Enable bit position. */ - - -/* NVM_FUSES.FUSEBYTE5 bit masks and bit positions */ -#define NVM_FUSES_BODACT_gm 0x30 /* BOD Operation in Active Mode group mask. */ -#define NVM_FUSES_BODACT_gp 4 /* BOD Operation in Active Mode group position. */ -#define NVM_FUSES_BODACT0_bm (1<<4) /* BOD Operation in Active Mode bit 0 mask. */ -#define NVM_FUSES_BODACT0_bp 4 /* BOD Operation in Active Mode bit 0 position. */ -#define NVM_FUSES_BODACT1_bm (1<<5) /* BOD Operation in Active Mode bit 1 mask. */ -#define NVM_FUSES_BODACT1_bp 5 /* BOD Operation in Active Mode bit 1 position. */ - -#define NVM_FUSES_EESAVE_bm 0x08 /* Preserve EEPROM Through Chip Erase bit mask. */ -#define NVM_FUSES_EESAVE_bp 3 /* Preserve EEPROM Through Chip Erase bit position. */ - -#define NVM_FUSES_BODLVL_gm 0x07 /* Brown Out Detection Voltage Level group mask. */ -#define NVM_FUSES_BODLVL_gp 0 /* Brown Out Detection Voltage Level group position. */ -#define NVM_FUSES_BODLVL0_bm (1<<0) /* Brown Out Detection Voltage Level bit 0 mask. */ -#define NVM_FUSES_BODLVL0_bp 0 /* Brown Out Detection Voltage Level bit 0 position. */ -#define NVM_FUSES_BODLVL1_bm (1<<1) /* Brown Out Detection Voltage Level bit 1 mask. */ -#define NVM_FUSES_BODLVL1_bp 1 /* Brown Out Detection Voltage Level bit 1 position. */ -#define NVM_FUSES_BODLVL2_bm (1<<2) /* Brown Out Detection Voltage Level bit 2 mask. */ -#define NVM_FUSES_BODLVL2_bp 2 /* Brown Out Detection Voltage Level bit 2 position. */ - - -/* AC - Analog Comparator */ -/* AC.AC0CTRL bit masks and bit positions */ -#define AC_INTMODE_gm 0xC0 /* Interrupt Mode group mask. */ -#define AC_INTMODE_gp 6 /* Interrupt Mode group position. */ -#define AC_INTMODE0_bm (1<<6) /* Interrupt Mode bit 0 mask. */ -#define AC_INTMODE0_bp 6 /* Interrupt Mode bit 0 position. */ -#define AC_INTMODE1_bm (1<<7) /* Interrupt Mode bit 1 mask. */ -#define AC_INTMODE1_bp 7 /* Interrupt Mode bit 1 position. */ - -#define AC_INTLVL_gm 0x30 /* Interrupt Level group mask. */ -#define AC_INTLVL_gp 4 /* Interrupt Level group position. */ -#define AC_INTLVL0_bm (1<<4) /* Interrupt Level bit 0 mask. */ -#define AC_INTLVL0_bp 4 /* Interrupt Level bit 0 position. */ -#define AC_INTLVL1_bm (1<<5) /* Interrupt Level bit 1 mask. */ -#define AC_INTLVL1_bp 5 /* Interrupt Level bit 1 position. */ - -#define AC_HSMODE_bm 0x08 /* High-speed Mode bit mask. */ -#define AC_HSMODE_bp 3 /* High-speed Mode bit position. */ - -#define AC_HYSMODE_gm 0x06 /* Hysteresis Mode group mask. */ -#define AC_HYSMODE_gp 1 /* Hysteresis Mode group position. */ -#define AC_HYSMODE0_bm (1<<1) /* Hysteresis Mode bit 0 mask. */ -#define AC_HYSMODE0_bp 1 /* Hysteresis Mode bit 0 position. */ -#define AC_HYSMODE1_bm (1<<2) /* Hysteresis Mode bit 1 mask. */ -#define AC_HYSMODE1_bp 2 /* Hysteresis Mode bit 1 position. */ - -#define AC_ENABLE_bm 0x01 /* Enable bit mask. */ -#define AC_ENABLE_bp 0 /* Enable bit position. */ - - -/* AC.AC1CTRL bit masks and bit positions */ -/* AC_INTMODE_gm Predefined. */ -/* AC_INTMODE_gp Predefined. */ -/* AC_INTMODE0_bm Predefined. */ -/* AC_INTMODE0_bp Predefined. */ -/* AC_INTMODE1_bm Predefined. */ -/* AC_INTMODE1_bp Predefined. */ - -/* AC_INTLVL_gm Predefined. */ -/* AC_INTLVL_gp Predefined. */ -/* AC_INTLVL0_bm Predefined. */ -/* AC_INTLVL0_bp Predefined. */ -/* AC_INTLVL1_bm Predefined. */ -/* AC_INTLVL1_bp Predefined. */ - -/* AC_HSMODE_bm Predefined. */ -/* AC_HSMODE_bp Predefined. */ - -/* AC_HYSMODE_gm Predefined. */ -/* AC_HYSMODE_gp Predefined. */ -/* AC_HYSMODE0_bm Predefined. */ -/* AC_HYSMODE0_bp Predefined. */ -/* AC_HYSMODE1_bm Predefined. */ -/* AC_HYSMODE1_bp Predefined. */ - -/* AC_ENABLE_bm Predefined. */ -/* AC_ENABLE_bp Predefined. */ - - -/* AC.AC0MUXCTRL bit masks and bit positions */ -#define AC_MUXPOS_gm 0x38 /* MUX Positive Input group mask. */ -#define AC_MUXPOS_gp 3 /* MUX Positive Input group position. */ -#define AC_MUXPOS0_bm (1<<3) /* MUX Positive Input bit 0 mask. */ -#define AC_MUXPOS0_bp 3 /* MUX Positive Input bit 0 position. */ -#define AC_MUXPOS1_bm (1<<4) /* MUX Positive Input bit 1 mask. */ -#define AC_MUXPOS1_bp 4 /* MUX Positive Input bit 1 position. */ -#define AC_MUXPOS2_bm (1<<5) /* MUX Positive Input bit 2 mask. */ -#define AC_MUXPOS2_bp 5 /* MUX Positive Input bit 2 position. */ - -#define AC_MUXNEG_gm 0x07 /* MUX Negative Input group mask. */ -#define AC_MUXNEG_gp 0 /* MUX Negative Input group position. */ -#define AC_MUXNEG0_bm (1<<0) /* MUX Negative Input bit 0 mask. */ -#define AC_MUXNEG0_bp 0 /* MUX Negative Input bit 0 position. */ -#define AC_MUXNEG1_bm (1<<1) /* MUX Negative Input bit 1 mask. */ -#define AC_MUXNEG1_bp 1 /* MUX Negative Input bit 1 position. */ -#define AC_MUXNEG2_bm (1<<2) /* MUX Negative Input bit 2 mask. */ -#define AC_MUXNEG2_bp 2 /* MUX Negative Input bit 2 position. */ - - -/* AC.AC1MUXCTRL bit masks and bit positions */ -/* AC_MUXPOS_gm Predefined. */ -/* AC_MUXPOS_gp Predefined. */ -/* AC_MUXPOS0_bm Predefined. */ -/* AC_MUXPOS0_bp Predefined. */ -/* AC_MUXPOS1_bm Predefined. */ -/* AC_MUXPOS1_bp Predefined. */ -/* AC_MUXPOS2_bm Predefined. */ -/* AC_MUXPOS2_bp Predefined. */ - -/* AC_MUXNEG_gm Predefined. */ -/* AC_MUXNEG_gp Predefined. */ -/* AC_MUXNEG0_bm Predefined. */ -/* AC_MUXNEG0_bp Predefined. */ -/* AC_MUXNEG1_bm Predefined. */ -/* AC_MUXNEG1_bp Predefined. */ -/* AC_MUXNEG2_bm Predefined. */ -/* AC_MUXNEG2_bp Predefined. */ - - -/* AC.CTRLA bit masks and bit positions */ -#define AC_AC0OUT_bm 0x01 /* Comparator 0 Output Enable bit mask. */ -#define AC_AC0OUT_bp 0 /* Comparator 0 Output Enable bit position. */ - - -/* AC.CTRLB bit masks and bit positions */ -#define AC_SCALEFAC_gm 0x3F /* VCC Voltage Scaler Factor group mask. */ -#define AC_SCALEFAC_gp 0 /* VCC Voltage Scaler Factor group position. */ -#define AC_SCALEFAC0_bm (1<<0) /* VCC Voltage Scaler Factor bit 0 mask. */ -#define AC_SCALEFAC0_bp 0 /* VCC Voltage Scaler Factor bit 0 position. */ -#define AC_SCALEFAC1_bm (1<<1) /* VCC Voltage Scaler Factor bit 1 mask. */ -#define AC_SCALEFAC1_bp 1 /* VCC Voltage Scaler Factor bit 1 position. */ -#define AC_SCALEFAC2_bm (1<<2) /* VCC Voltage Scaler Factor bit 2 mask. */ -#define AC_SCALEFAC2_bp 2 /* VCC Voltage Scaler Factor bit 2 position. */ -#define AC_SCALEFAC3_bm (1<<3) /* VCC Voltage Scaler Factor bit 3 mask. */ -#define AC_SCALEFAC3_bp 3 /* VCC Voltage Scaler Factor bit 3 position. */ -#define AC_SCALEFAC4_bm (1<<4) /* VCC Voltage Scaler Factor bit 4 mask. */ -#define AC_SCALEFAC4_bp 4 /* VCC Voltage Scaler Factor bit 4 position. */ -#define AC_SCALEFAC5_bm (1<<5) /* VCC Voltage Scaler Factor bit 5 mask. */ -#define AC_SCALEFAC5_bp 5 /* VCC Voltage Scaler Factor bit 5 position. */ - - -/* AC.WINCTRL bit masks and bit positions */ -#define AC_WEN_bm 0x10 /* Window Mode Enable bit mask. */ -#define AC_WEN_bp 4 /* Window Mode Enable bit position. */ - -#define AC_WINTMODE_gm 0x0C /* Window Interrupt Mode group mask. */ -#define AC_WINTMODE_gp 2 /* Window Interrupt Mode group position. */ -#define AC_WINTMODE0_bm (1<<2) /* Window Interrupt Mode bit 0 mask. */ -#define AC_WINTMODE0_bp 2 /* Window Interrupt Mode bit 0 position. */ -#define AC_WINTMODE1_bm (1<<3) /* Window Interrupt Mode bit 1 mask. */ -#define AC_WINTMODE1_bp 3 /* Window Interrupt Mode bit 1 position. */ - -#define AC_WINTLVL_gm 0x03 /* Window Interrupt Level group mask. */ -#define AC_WINTLVL_gp 0 /* Window Interrupt Level group position. */ -#define AC_WINTLVL0_bm (1<<0) /* Window Interrupt Level bit 0 mask. */ -#define AC_WINTLVL0_bp 0 /* Window Interrupt Level bit 0 position. */ -#define AC_WINTLVL1_bm (1<<1) /* Window Interrupt Level bit 1 mask. */ -#define AC_WINTLVL1_bp 1 /* Window Interrupt Level bit 1 position. */ - - -/* AC.STATUS bit masks and bit positions */ -#define AC_WSTATE_gm 0xC0 /* Window Mode State group mask. */ -#define AC_WSTATE_gp 6 /* Window Mode State group position. */ -#define AC_WSTATE0_bm (1<<6) /* Window Mode State bit 0 mask. */ -#define AC_WSTATE0_bp 6 /* Window Mode State bit 0 position. */ -#define AC_WSTATE1_bm (1<<7) /* Window Mode State bit 1 mask. */ -#define AC_WSTATE1_bp 7 /* Window Mode State bit 1 position. */ - -#define AC_AC1STATE_bm 0x20 /* Comparator 1 State bit mask. */ -#define AC_AC1STATE_bp 5 /* Comparator 1 State bit position. */ - -#define AC_AC0STATE_bm 0x10 /* Comparator 0 State bit mask. */ -#define AC_AC0STATE_bp 4 /* Comparator 0 State bit position. */ - -#define AC_WIF_bm 0x04 /* Window Mode Interrupt Flag bit mask. */ -#define AC_WIF_bp 2 /* Window Mode Interrupt Flag bit position. */ - -#define AC_AC1IF_bm 0x02 /* Comparator 1 Interrupt Flag bit mask. */ -#define AC_AC1IF_bp 1 /* Comparator 1 Interrupt Flag bit position. */ - -#define AC_AC0IF_bm 0x01 /* Comparator 0 Interrupt Flag bit mask. */ -#define AC_AC0IF_bp 0 /* Comparator 0 Interrupt Flag bit position. */ - - -/* ADC - Analog/Digital Converter */ -/* ADC_CH.CTRL bit masks and bit positions */ -#define ADC_CH_START_bm 0x80 /* Channel Start Conversion bit mask. */ -#define ADC_CH_START_bp 7 /* Channel Start Conversion bit position. */ - -#define ADC_CH_GAINFAC_gm 0x1C /* Gain Factor group mask. */ -#define ADC_CH_GAINFAC_gp 2 /* Gain Factor group position. */ -#define ADC_CH_GAINFAC0_bm (1<<2) /* Gain Factor bit 0 mask. */ -#define ADC_CH_GAINFAC0_bp 2 /* Gain Factor bit 0 position. */ -#define ADC_CH_GAINFAC1_bm (1<<3) /* Gain Factor bit 1 mask. */ -#define ADC_CH_GAINFAC1_bp 3 /* Gain Factor bit 1 position. */ -#define ADC_CH_GAINFAC2_bm (1<<4) /* Gain Factor bit 2 mask. */ -#define ADC_CH_GAINFAC2_bp 4 /* Gain Factor bit 2 position. */ - -#define ADC_CH_INPUTMODE_gm 0x03 /* Input Mode Select group mask. */ -#define ADC_CH_INPUTMODE_gp 0 /* Input Mode Select group position. */ -#define ADC_CH_INPUTMODE0_bm (1<<0) /* Input Mode Select bit 0 mask. */ -#define ADC_CH_INPUTMODE0_bp 0 /* Input Mode Select bit 0 position. */ -#define ADC_CH_INPUTMODE1_bm (1<<1) /* Input Mode Select bit 1 mask. */ -#define ADC_CH_INPUTMODE1_bp 1 /* Input Mode Select bit 1 position. */ - - -/* ADC_CH.MUXCTRL bit masks and bit positions */ -#define ADC_CH_MUXPOS_gm 0x78 /* Positive Input Select group mask. */ -#define ADC_CH_MUXPOS_gp 3 /* Positive Input Select group position. */ -#define ADC_CH_MUXPOS0_bm (1<<3) /* Positive Input Select bit 0 mask. */ -#define ADC_CH_MUXPOS0_bp 3 /* Positive Input Select bit 0 position. */ -#define ADC_CH_MUXPOS1_bm (1<<4) /* Positive Input Select bit 1 mask. */ -#define ADC_CH_MUXPOS1_bp 4 /* Positive Input Select bit 1 position. */ -#define ADC_CH_MUXPOS2_bm (1<<5) /* Positive Input Select bit 2 mask. */ -#define ADC_CH_MUXPOS2_bp 5 /* Positive Input Select bit 2 position. */ -#define ADC_CH_MUXPOS3_bm (1<<6) /* Positive Input Select bit 3 mask. */ -#define ADC_CH_MUXPOS3_bp 6 /* Positive Input Select bit 3 position. */ - -#define ADC_CH_MUXINT_gm 0x78 /* Internal Input Select group mask. */ -#define ADC_CH_MUXINT_gp 3 /* Internal Input Select group position. */ -#define ADC_CH_MUXINT0_bm (1<<3) /* Internal Input Select bit 0 mask. */ -#define ADC_CH_MUXINT0_bp 3 /* Internal Input Select bit 0 position. */ -#define ADC_CH_MUXINT1_bm (1<<4) /* Internal Input Select bit 1 mask. */ -#define ADC_CH_MUXINT1_bp 4 /* Internal Input Select bit 1 position. */ -#define ADC_CH_MUXINT2_bm (1<<5) /* Internal Input Select bit 2 mask. */ -#define ADC_CH_MUXINT2_bp 5 /* Internal Input Select bit 2 position. */ -#define ADC_CH_MUXINT3_bm (1<<6) /* Internal Input Select bit 3 mask. */ -#define ADC_CH_MUXINT3_bp 6 /* Internal Input Select bit 3 position. */ - -#define ADC_CH_MUXNEG_gm 0x03 /* Negative Input Select group mask. */ -#define ADC_CH_MUXNEG_gp 0 /* Negative Input Select group position. */ -#define ADC_CH_MUXNEG0_bm (1<<0) /* Negative Input Select bit 0 mask. */ -#define ADC_CH_MUXNEG0_bp 0 /* Negative Input Select bit 0 position. */ -#define ADC_CH_MUXNEG1_bm (1<<1) /* Negative Input Select bit 1 mask. */ -#define ADC_CH_MUXNEG1_bp 1 /* Negative Input Select bit 1 position. */ - - -/* ADC_CH.INTCTRL bit masks and bit positions */ -#define ADC_CH_INTMODE_gm 0x0C /* Interrupt Mode group mask. */ -#define ADC_CH_INTMODE_gp 2 /* Interrupt Mode group position. */ -#define ADC_CH_INTMODE0_bm (1<<2) /* Interrupt Mode bit 0 mask. */ -#define ADC_CH_INTMODE0_bp 2 /* Interrupt Mode bit 0 position. */ -#define ADC_CH_INTMODE1_bm (1<<3) /* Interrupt Mode bit 1 mask. */ -#define ADC_CH_INTMODE1_bp 3 /* Interrupt Mode bit 1 position. */ - -#define ADC_CH_INTLVL_gm 0x03 /* Interrupt Level group mask. */ -#define ADC_CH_INTLVL_gp 0 /* Interrupt Level group position. */ -#define ADC_CH_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */ -#define ADC_CH_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */ -#define ADC_CH_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ -#define ADC_CH_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */ - - -/* ADC_CH.INTFLAGS bit masks and bit positions */ -#define ADC_CH_CHIF_bm 0x01 /* Channel Interrupt Flag bit mask. */ -#define ADC_CH_CHIF_bp 0 /* Channel Interrupt Flag bit position. */ - - -/* ADC.CTRLA bit masks and bit positions */ -#define ADC_DMASEL_gm 0xC0 /* DMA Selection group mask. */ -#define ADC_DMASEL_gp 6 /* DMA Selection group position. */ -#define ADC_DMASEL0_bm (1<<6) /* DMA Selection bit 0 mask. */ -#define ADC_DMASEL0_bp 6 /* DMA Selection bit 0 position. */ -#define ADC_DMASEL1_bm (1<<7) /* DMA Selection bit 1 mask. */ -#define ADC_DMASEL1_bp 7 /* DMA Selection bit 1 position. */ - -#define ADC_CH3START_bm 0x20 /* Channel 3 Start Conversion bit mask. */ -#define ADC_CH3START_bp 5 /* Channel 3 Start Conversion bit position. */ - -#define ADC_CH2START_bm 0x10 /* Channel 2 Start Conversion bit mask. */ -#define ADC_CH2START_bp 4 /* Channel 2 Start Conversion bit position. */ - -#define ADC_CH1START_bm 0x08 /* Channel 1 Start Conversion bit mask. */ -#define ADC_CH1START_bp 3 /* Channel 1 Start Conversion bit position. */ - -#define ADC_CH0START_bm 0x04 /* Channel 0 Start Conversion bit mask. */ -#define ADC_CH0START_bp 2 /* Channel 0 Start Conversion bit position. */ - -#define ADC_FLUSH_bm 0x02 /* Flush Pipeline bit mask. */ -#define ADC_FLUSH_bp 1 /* Flush Pipeline bit position. */ - -#define ADC_ENABLE_bm 0x01 /* Enable ADC bit mask. */ -#define ADC_ENABLE_bp 0 /* Enable ADC bit position. */ - - -/* ADC.CTRLB bit masks and bit positions */ -#define ADC_CONMODE_bm 0x10 /* Conversion Mode bit mask. */ -#define ADC_CONMODE_bp 4 /* Conversion Mode bit position. */ - -#define ADC_FREERUN_bm 0x08 /* Free Running Mode Enable bit mask. */ -#define ADC_FREERUN_bp 3 /* Free Running Mode Enable bit position. */ - -#define ADC_RESOLUTION_gm 0x06 /* Result Resolution group mask. */ -#define ADC_RESOLUTION_gp 1 /* Result Resolution group position. */ -#define ADC_RESOLUTION0_bm (1<<1) /* Result Resolution bit 0 mask. */ -#define ADC_RESOLUTION0_bp 1 /* Result Resolution bit 0 position. */ -#define ADC_RESOLUTION1_bm (1<<2) /* Result Resolution bit 1 mask. */ -#define ADC_RESOLUTION1_bp 2 /* Result Resolution bit 1 position. */ - - -/* ADC.REFCTRL bit masks and bit positions */ -#define ADC_REFSEL_gm 0x30 /* Reference Selection group mask. */ -#define ADC_REFSEL_gp 4 /* Reference Selection group position. */ -#define ADC_REFSEL0_bm (1<<4) /* Reference Selection bit 0 mask. */ -#define ADC_REFSEL0_bp 4 /* Reference Selection bit 0 position. */ -#define ADC_REFSEL1_bm (1<<5) /* Reference Selection bit 1 mask. */ -#define ADC_REFSEL1_bp 5 /* Reference Selection bit 1 position. */ - -#define ADC_BANDGAP_bm 0x02 /* Bandgap enable bit mask. */ -#define ADC_BANDGAP_bp 1 /* Bandgap enable bit position. */ - -#define ADC_TEMPREF_bm 0x01 /* Temperature Reference Enable bit mask. */ -#define ADC_TEMPREF_bp 0 /* Temperature Reference Enable bit position. */ - - -/* ADC.EVCTRL bit masks and bit positions */ -#define ADC_SWEEP_gm 0xC0 /* Channel Sweep Selection group mask. */ -#define ADC_SWEEP_gp 6 /* Channel Sweep Selection group position. */ -#define ADC_SWEEP0_bm (1<<6) /* Channel Sweep Selection bit 0 mask. */ -#define ADC_SWEEP0_bp 6 /* Channel Sweep Selection bit 0 position. */ -#define ADC_SWEEP1_bm (1<<7) /* Channel Sweep Selection bit 1 mask. */ -#define ADC_SWEEP1_bp 7 /* Channel Sweep Selection bit 1 position. */ - -#define ADC_EVSEL_gm 0x38 /* Event Input Select group mask. */ -#define ADC_EVSEL_gp 3 /* Event Input Select group position. */ -#define ADC_EVSEL0_bm (1<<3) /* Event Input Select bit 0 mask. */ -#define ADC_EVSEL0_bp 3 /* Event Input Select bit 0 position. */ -#define ADC_EVSEL1_bm (1<<4) /* Event Input Select bit 1 mask. */ -#define ADC_EVSEL1_bp 4 /* Event Input Select bit 1 position. */ -#define ADC_EVSEL2_bm (1<<5) /* Event Input Select bit 2 mask. */ -#define ADC_EVSEL2_bp 5 /* Event Input Select bit 2 position. */ - -#define ADC_EVACT_gm 0x07 /* Event Action Select group mask. */ -#define ADC_EVACT_gp 0 /* Event Action Select group position. */ -#define ADC_EVACT0_bm (1<<0) /* Event Action Select bit 0 mask. */ -#define ADC_EVACT0_bp 0 /* Event Action Select bit 0 position. */ -#define ADC_EVACT1_bm (1<<1) /* Event Action Select bit 1 mask. */ -#define ADC_EVACT1_bp 1 /* Event Action Select bit 1 position. */ -#define ADC_EVACT2_bm (1<<2) /* Event Action Select bit 2 mask. */ -#define ADC_EVACT2_bp 2 /* Event Action Select bit 2 position. */ - - -/* ADC.PRESCALER bit masks and bit positions */ -#define ADC_PRESCALER_gm 0x07 /* Clock Prescaler Selection group mask. */ -#define ADC_PRESCALER_gp 0 /* Clock Prescaler Selection group position. */ -#define ADC_PRESCALER0_bm (1<<0) /* Clock Prescaler Selection bit 0 mask. */ -#define ADC_PRESCALER0_bp 0 /* Clock Prescaler Selection bit 0 position. */ -#define ADC_PRESCALER1_bm (1<<1) /* Clock Prescaler Selection bit 1 mask. */ -#define ADC_PRESCALER1_bp 1 /* Clock Prescaler Selection bit 1 position. */ -#define ADC_PRESCALER2_bm (1<<2) /* Clock Prescaler Selection bit 2 mask. */ -#define ADC_PRESCALER2_bp 2 /* Clock Prescaler Selection bit 2 position. */ - - -/* ADC.INTFLAGS bit masks and bit positions */ -#define ADC_CH3IF_bm 0x08 /* Channel 3 Interrupt Flag bit mask. */ -#define ADC_CH3IF_bp 3 /* Channel 3 Interrupt Flag bit position. */ - -#define ADC_CH2IF_bm 0x04 /* Channel 2 Interrupt Flag bit mask. */ -#define ADC_CH2IF_bp 2 /* Channel 2 Interrupt Flag bit position. */ - -#define ADC_CH1IF_bm 0x02 /* Channel 1 Interrupt Flag bit mask. */ -#define ADC_CH1IF_bp 1 /* Channel 1 Interrupt Flag bit position. */ - -#define ADC_CH0IF_bm 0x01 /* Channel 0 Interrupt Flag bit mask. */ -#define ADC_CH0IF_bp 0 /* Channel 0 Interrupt Flag bit position. */ - - -/* DAC - Digital/Analog Converter */ -/* DAC.CTRLA bit masks and bit positions */ -#define DAC_IDOEN_bm 0x10 /* Internal Output Enable bit mask. */ -#define DAC_IDOEN_bp 4 /* Internal Output Enable bit position. */ - -#define DAC_CH1EN_bm 0x08 /* Channel 1 Output Enable bit mask. */ -#define DAC_CH1EN_bp 3 /* Channel 1 Output Enable bit position. */ - -#define DAC_CH0EN_bm 0x04 /* Channel 0 Output Enable bit mask. */ -#define DAC_CH0EN_bp 2 /* Channel 0 Output Enable bit position. */ - -#define DAC_LPMODE_bm 0x02 /* Low Power Mode bit mask. */ -#define DAC_LPMODE_bp 1 /* Low Power Mode bit position. */ - -#define DAC_ENABLE_bm 0x01 /* Enable bit mask. */ -#define DAC_ENABLE_bp 0 /* Enable bit position. */ - - -/* DAC.CTRLB bit masks and bit positions */ -#define DAC_CHSEL_gm 0x60 /* Channel Select group mask. */ -#define DAC_CHSEL_gp 5 /* Channel Select group position. */ -#define DAC_CHSEL0_bm (1<<5) /* Channel Select bit 0 mask. */ -#define DAC_CHSEL0_bp 5 /* Channel Select bit 0 position. */ -#define DAC_CHSEL1_bm (1<<6) /* Channel Select bit 1 mask. */ -#define DAC_CHSEL1_bp 6 /* Channel Select bit 1 position. */ - -#define DAC_CH1TRIG_bm 0x02 /* Channel 1 Event Trig Enable bit mask. */ -#define DAC_CH1TRIG_bp 1 /* Channel 1 Event Trig Enable bit position. */ - -#define DAC_CH0TRIG_bm 0x01 /* Channel 0 Event Trig Enable bit mask. */ -#define DAC_CH0TRIG_bp 0 /* Channel 0 Event Trig Enable bit position. */ - - -/* DAC.CTRLC bit masks and bit positions */ -#define DAC_REFSEL_gm 0x18 /* Reference Select group mask. */ -#define DAC_REFSEL_gp 3 /* Reference Select group position. */ -#define DAC_REFSEL0_bm (1<<3) /* Reference Select bit 0 mask. */ -#define DAC_REFSEL0_bp 3 /* Reference Select bit 0 position. */ -#define DAC_REFSEL1_bm (1<<4) /* Reference Select bit 1 mask. */ -#define DAC_REFSEL1_bp 4 /* Reference Select bit 1 position. */ - -#define DAC_LEFTADJ_bm 0x01 /* Left-adjust Result bit mask. */ -#define DAC_LEFTADJ_bp 0 /* Left-adjust Result bit position. */ - - -/* DAC.EVCTRL bit masks and bit positions */ -#define DAC_EVSEL_gm 0x07 /* Event Input Selection group mask. */ -#define DAC_EVSEL_gp 0 /* Event Input Selection group position. */ -#define DAC_EVSEL0_bm (1<<0) /* Event Input Selection bit 0 mask. */ -#define DAC_EVSEL0_bp 0 /* Event Input Selection bit 0 position. */ -#define DAC_EVSEL1_bm (1<<1) /* Event Input Selection bit 1 mask. */ -#define DAC_EVSEL1_bp 1 /* Event Input Selection bit 1 position. */ -#define DAC_EVSEL2_bm (1<<2) /* Event Input Selection bit 2 mask. */ -#define DAC_EVSEL2_bp 2 /* Event Input Selection bit 2 position. */ - - -/* DAC.TIMCTRL bit masks and bit positions */ -#define DAC_CONINTVAL_gm 0x70 /* Conversion Intercal group mask. */ -#define DAC_CONINTVAL_gp 4 /* Conversion Intercal group position. */ -#define DAC_CONINTVAL0_bm (1<<4) /* Conversion Intercal bit 0 mask. */ -#define DAC_CONINTVAL0_bp 4 /* Conversion Intercal bit 0 position. */ -#define DAC_CONINTVAL1_bm (1<<5) /* Conversion Intercal bit 1 mask. */ -#define DAC_CONINTVAL1_bp 5 /* Conversion Intercal bit 1 position. */ -#define DAC_CONINTVAL2_bm (1<<6) /* Conversion Intercal bit 2 mask. */ -#define DAC_CONINTVAL2_bp 6 /* Conversion Intercal bit 2 position. */ - -#define DAC_REFRESH_gm 0x0F /* Refresh Timing Control group mask. */ -#define DAC_REFRESH_gp 0 /* Refresh Timing Control group position. */ -#define DAC_REFRESH0_bm (1<<0) /* Refresh Timing Control bit 0 mask. */ -#define DAC_REFRESH0_bp 0 /* Refresh Timing Control bit 0 position. */ -#define DAC_REFRESH1_bm (1<<1) /* Refresh Timing Control bit 1 mask. */ -#define DAC_REFRESH1_bp 1 /* Refresh Timing Control bit 1 position. */ -#define DAC_REFRESH2_bm (1<<2) /* Refresh Timing Control bit 2 mask. */ -#define DAC_REFRESH2_bp 2 /* Refresh Timing Control bit 2 position. */ -#define DAC_REFRESH3_bm (1<<3) /* Refresh Timing Control bit 3 mask. */ -#define DAC_REFRESH3_bp 3 /* Refresh Timing Control bit 3 position. */ - - -/* DAC.STATUS bit masks and bit positions */ -#define DAC_CH1DRE_bm 0x02 /* Channel 1 Data Register Empty bit mask. */ -#define DAC_CH1DRE_bp 1 /* Channel 1 Data Register Empty bit position. */ - -#define DAC_CH0DRE_bm 0x01 /* Channel 0 Data Register Empty bit mask. */ -#define DAC_CH0DRE_bp 0 /* Channel 0 Data Register Empty bit position. */ - - -/* RTC - Real-Time Clounter */ -/* RTC.CTRL bit masks and bit positions */ -#define RTC_PRESCALER_gm 0x07 /* Prescaling Factor group mask. */ -#define RTC_PRESCALER_gp 0 /* Prescaling Factor group position. */ -#define RTC_PRESCALER0_bm (1<<0) /* Prescaling Factor bit 0 mask. */ -#define RTC_PRESCALER0_bp 0 /* Prescaling Factor bit 0 position. */ -#define RTC_PRESCALER1_bm (1<<1) /* Prescaling Factor bit 1 mask. */ -#define RTC_PRESCALER1_bp 1 /* Prescaling Factor bit 1 position. */ -#define RTC_PRESCALER2_bm (1<<2) /* Prescaling Factor bit 2 mask. */ -#define RTC_PRESCALER2_bp 2 /* Prescaling Factor bit 2 position. */ - - -/* RTC.STATUS bit masks and bit positions */ -#define RTC_SYNCBUSY_bm 0x01 /* Synchronization Busy Flag bit mask. */ -#define RTC_SYNCBUSY_bp 0 /* Synchronization Busy Flag bit position. */ - - -/* RTC.INTCTRL bit masks and bit positions */ -#define RTC_COMPINTLVL_gm 0x0C /* Compare Match Interrupt Level group mask. */ -#define RTC_COMPINTLVL_gp 2 /* Compare Match Interrupt Level group position. */ -#define RTC_COMPINTLVL0_bm (1<<2) /* Compare Match Interrupt Level bit 0 mask. */ -#define RTC_COMPINTLVL0_bp 2 /* Compare Match Interrupt Level bit 0 position. */ -#define RTC_COMPINTLVL1_bm (1<<3) /* Compare Match Interrupt Level bit 1 mask. */ -#define RTC_COMPINTLVL1_bp 3 /* Compare Match Interrupt Level bit 1 position. */ - -#define RTC_OVFINTLVL_gm 0x03 /* Overflow Interrupt Level group mask. */ -#define RTC_OVFINTLVL_gp 0 /* Overflow Interrupt Level group position. */ -#define RTC_OVFINTLVL0_bm (1<<0) /* Overflow Interrupt Level bit 0 mask. */ -#define RTC_OVFINTLVL0_bp 0 /* Overflow Interrupt Level bit 0 position. */ -#define RTC_OVFINTLVL1_bm (1<<1) /* Overflow Interrupt Level bit 1 mask. */ -#define RTC_OVFINTLVL1_bp 1 /* Overflow Interrupt Level bit 1 position. */ - - -/* RTC.INTFLAGS bit masks and bit positions */ -#define RTC_COMPIF_bm 0x02 /* Compare Match Interrupt Flag bit mask. */ -#define RTC_COMPIF_bp 1 /* Compare Match Interrupt Flag bit position. */ - -#define RTC_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ -#define RTC_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ - - -/* EBI - External Bus Interface */ -/* EBI_CS.CTRLA bit masks and bit positions */ -#define EBI_CS_ASIZE_gm 0x7C /* Address Size group mask. */ -#define EBI_CS_ASIZE_gp 2 /* Address Size group position. */ -#define EBI_CS_ASIZE0_bm (1<<2) /* Address Size bit 0 mask. */ -#define EBI_CS_ASIZE0_bp 2 /* Address Size bit 0 position. */ -#define EBI_CS_ASIZE1_bm (1<<3) /* Address Size bit 1 mask. */ -#define EBI_CS_ASIZE1_bp 3 /* Address Size bit 1 position. */ -#define EBI_CS_ASIZE2_bm (1<<4) /* Address Size bit 2 mask. */ -#define EBI_CS_ASIZE2_bp 4 /* Address Size bit 2 position. */ -#define EBI_CS_ASIZE3_bm (1<<5) /* Address Size bit 3 mask. */ -#define EBI_CS_ASIZE3_bp 5 /* Address Size bit 3 position. */ -#define EBI_CS_ASIZE4_bm (1<<6) /* Address Size bit 4 mask. */ -#define EBI_CS_ASIZE4_bp 6 /* Address Size bit 4 position. */ - -#define EBI_CS_MODE_gm 0x03 /* Memory Mode group mask. */ -#define EBI_CS_MODE_gp 0 /* Memory Mode group position. */ -#define EBI_CS_MODE0_bm (1<<0) /* Memory Mode bit 0 mask. */ -#define EBI_CS_MODE0_bp 0 /* Memory Mode bit 0 position. */ -#define EBI_CS_MODE1_bm (1<<1) /* Memory Mode bit 1 mask. */ -#define EBI_CS_MODE1_bp 1 /* Memory Mode bit 1 position. */ - - -/* EBI_CS.CTRLB bit masks and bit positions */ -#define EBI_CS_SRWS_gm 0x07 /* SRAM Wait State Cycles group mask. */ -#define EBI_CS_SRWS_gp 0 /* SRAM Wait State Cycles group position. */ -#define EBI_CS_SRWS0_bm (1<<0) /* SRAM Wait State Cycles bit 0 mask. */ -#define EBI_CS_SRWS0_bp 0 /* SRAM Wait State Cycles bit 0 position. */ -#define EBI_CS_SRWS1_bm (1<<1) /* SRAM Wait State Cycles bit 1 mask. */ -#define EBI_CS_SRWS1_bp 1 /* SRAM Wait State Cycles bit 1 position. */ -#define EBI_CS_SRWS2_bm (1<<2) /* SRAM Wait State Cycles bit 2 mask. */ -#define EBI_CS_SRWS2_bp 2 /* SRAM Wait State Cycles bit 2 position. */ - -#define EBI_CS_SDINITDONE_bm 0x80 /* SDRAM Initialization Done bit mask. */ -#define EBI_CS_SDINITDONE_bp 7 /* SDRAM Initialization Done bit position. */ - -#define EBI_CS_SDSREN_bm 0x04 /* SDRAM Self-refresh Enable bit mask. */ -#define EBI_CS_SDSREN_bp 2 /* SDRAM Self-refresh Enable bit position. */ - -#define EBI_CS_SDMODE_gm 0x03 /* SDRAM Mode group mask. */ -#define EBI_CS_SDMODE_gp 0 /* SDRAM Mode group position. */ -#define EBI_CS_SDMODE0_bm (1<<0) /* SDRAM Mode bit 0 mask. */ -#define EBI_CS_SDMODE0_bp 0 /* SDRAM Mode bit 0 position. */ -#define EBI_CS_SDMODE1_bm (1<<1) /* SDRAM Mode bit 1 mask. */ -#define EBI_CS_SDMODE1_bp 1 /* SDRAM Mode bit 1 position. */ - - -/* EBI.CTRL bit masks and bit positions */ -#define EBI_SDDATAW_gm 0xC0 /* SDRAM Data Width Setting group mask. */ -#define EBI_SDDATAW_gp 6 /* SDRAM Data Width Setting group position. */ -#define EBI_SDDATAW0_bm (1<<6) /* SDRAM Data Width Setting bit 0 mask. */ -#define EBI_SDDATAW0_bp 6 /* SDRAM Data Width Setting bit 0 position. */ -#define EBI_SDDATAW1_bm (1<<7) /* SDRAM Data Width Setting bit 1 mask. */ -#define EBI_SDDATAW1_bp 7 /* SDRAM Data Width Setting bit 1 position. */ - -#define EBI_LPCMODE_gm 0x30 /* SRAM LPC Mode group mask. */ -#define EBI_LPCMODE_gp 4 /* SRAM LPC Mode group position. */ -#define EBI_LPCMODE0_bm (1<<4) /* SRAM LPC Mode bit 0 mask. */ -#define EBI_LPCMODE0_bp 4 /* SRAM LPC Mode bit 0 position. */ -#define EBI_LPCMODE1_bm (1<<5) /* SRAM LPC Mode bit 1 mask. */ -#define EBI_LPCMODE1_bp 5 /* SRAM LPC Mode bit 1 position. */ - -#define EBI_SRMODE_gm 0x0C /* SRAM Mode group mask. */ -#define EBI_SRMODE_gp 2 /* SRAM Mode group position. */ -#define EBI_SRMODE0_bm (1<<2) /* SRAM Mode bit 0 mask. */ -#define EBI_SRMODE0_bp 2 /* SRAM Mode bit 0 position. */ -#define EBI_SRMODE1_bm (1<<3) /* SRAM Mode bit 1 mask. */ -#define EBI_SRMODE1_bp 3 /* SRAM Mode bit 1 position. */ - -#define EBI_IFMODE_gm 0x03 /* Interface Mode group mask. */ -#define EBI_IFMODE_gp 0 /* Interface Mode group position. */ -#define EBI_IFMODE0_bm (1<<0) /* Interface Mode bit 0 mask. */ -#define EBI_IFMODE0_bp 0 /* Interface Mode bit 0 position. */ -#define EBI_IFMODE1_bm (1<<1) /* Interface Mode bit 1 mask. */ -#define EBI_IFMODE1_bp 1 /* Interface Mode bit 1 position. */ - - -/* EBI.SDRAMCTRLA bit masks and bit positions */ -#define EBI_SDCAS_bm 0x08 /* SDRAM CAS Latency Setting bit mask. */ -#define EBI_SDCAS_bp 3 /* SDRAM CAS Latency Setting bit position. */ - -#define EBI_SDROW_bm 0x04 /* SDRAM ROW Bits Setting bit mask. */ -#define EBI_SDROW_bp 2 /* SDRAM ROW Bits Setting bit position. */ - -#define EBI_SDCOL_gm 0x03 /* SDRAM Column Bits Setting group mask. */ -#define EBI_SDCOL_gp 0 /* SDRAM Column Bits Setting group position. */ -#define EBI_SDCOL0_bm (1<<0) /* SDRAM Column Bits Setting bit 0 mask. */ -#define EBI_SDCOL0_bp 0 /* SDRAM Column Bits Setting bit 0 position. */ -#define EBI_SDCOL1_bm (1<<1) /* SDRAM Column Bits Setting bit 1 mask. */ -#define EBI_SDCOL1_bp 1 /* SDRAM Column Bits Setting bit 1 position. */ - - -/* EBI.SDRAMCTRLB bit masks and bit positions */ -#define EBI_MRDLY_gm 0xC0 /* SDRAM Mode Register Delay group mask. */ -#define EBI_MRDLY_gp 6 /* SDRAM Mode Register Delay group position. */ -#define EBI_MRDLY0_bm (1<<6) /* SDRAM Mode Register Delay bit 0 mask. */ -#define EBI_MRDLY0_bp 6 /* SDRAM Mode Register Delay bit 0 position. */ -#define EBI_MRDLY1_bm (1<<7) /* SDRAM Mode Register Delay bit 1 mask. */ -#define EBI_MRDLY1_bp 7 /* SDRAM Mode Register Delay bit 1 position. */ - -#define EBI_ROWCYCDLY_gm 0x38 /* SDRAM Row Cycle Delay group mask. */ -#define EBI_ROWCYCDLY_gp 3 /* SDRAM Row Cycle Delay group position. */ -#define EBI_ROWCYCDLY0_bm (1<<3) /* SDRAM Row Cycle Delay bit 0 mask. */ -#define EBI_ROWCYCDLY0_bp 3 /* SDRAM Row Cycle Delay bit 0 position. */ -#define EBI_ROWCYCDLY1_bm (1<<4) /* SDRAM Row Cycle Delay bit 1 mask. */ -#define EBI_ROWCYCDLY1_bp 4 /* SDRAM Row Cycle Delay bit 1 position. */ -#define EBI_ROWCYCDLY2_bm (1<<5) /* SDRAM Row Cycle Delay bit 2 mask. */ -#define EBI_ROWCYCDLY2_bp 5 /* SDRAM Row Cycle Delay bit 2 position. */ - -#define EBI_RPDLY_gm 0x07 /* SDRAM Row-to-Precharge Delay group mask. */ -#define EBI_RPDLY_gp 0 /* SDRAM Row-to-Precharge Delay group position. */ -#define EBI_RPDLY0_bm (1<<0) /* SDRAM Row-to-Precharge Delay bit 0 mask. */ -#define EBI_RPDLY0_bp 0 /* SDRAM Row-to-Precharge Delay bit 0 position. */ -#define EBI_RPDLY1_bm (1<<1) /* SDRAM Row-to-Precharge Delay bit 1 mask. */ -#define EBI_RPDLY1_bp 1 /* SDRAM Row-to-Precharge Delay bit 1 position. */ -#define EBI_RPDLY2_bm (1<<2) /* SDRAM Row-to-Precharge Delay bit 2 mask. */ -#define EBI_RPDLY2_bp 2 /* SDRAM Row-to-Precharge Delay bit 2 position. */ - - -/* EBI.SDRAMCTRLC bit masks and bit positions */ -#define EBI_WRDLY_gm 0xC0 /* SDRAM Write Recovery Delay group mask. */ -#define EBI_WRDLY_gp 6 /* SDRAM Write Recovery Delay group position. */ -#define EBI_WRDLY0_bm (1<<6) /* SDRAM Write Recovery Delay bit 0 mask. */ -#define EBI_WRDLY0_bp 6 /* SDRAM Write Recovery Delay bit 0 position. */ -#define EBI_WRDLY1_bm (1<<7) /* SDRAM Write Recovery Delay bit 1 mask. */ -#define EBI_WRDLY1_bp 7 /* SDRAM Write Recovery Delay bit 1 position. */ - -#define EBI_ESRDLY_gm 0x38 /* SDRAM Exit-Self-refresh-to-Active Delay group mask. */ -#define EBI_ESRDLY_gp 3 /* SDRAM Exit-Self-refresh-to-Active Delay group position. */ -#define EBI_ESRDLY0_bm (1<<3) /* SDRAM Exit-Self-refresh-to-Active Delay bit 0 mask. */ -#define EBI_ESRDLY0_bp 3 /* SDRAM Exit-Self-refresh-to-Active Delay bit 0 position. */ -#define EBI_ESRDLY1_bm (1<<4) /* SDRAM Exit-Self-refresh-to-Active Delay bit 1 mask. */ -#define EBI_ESRDLY1_bp 4 /* SDRAM Exit-Self-refresh-to-Active Delay bit 1 position. */ -#define EBI_ESRDLY2_bm (1<<5) /* SDRAM Exit-Self-refresh-to-Active Delay bit 2 mask. */ -#define EBI_ESRDLY2_bp 5 /* SDRAM Exit-Self-refresh-to-Active Delay bit 2 position. */ - -#define EBI_ROWCOLDLY_gm 0x07 /* SDRAM Row-to-Column Delay group mask. */ -#define EBI_ROWCOLDLY_gp 0 /* SDRAM Row-to-Column Delay group position. */ -#define EBI_ROWCOLDLY0_bm (1<<0) /* SDRAM Row-to-Column Delay bit 0 mask. */ -#define EBI_ROWCOLDLY0_bp 0 /* SDRAM Row-to-Column Delay bit 0 position. */ -#define EBI_ROWCOLDLY1_bm (1<<1) /* SDRAM Row-to-Column Delay bit 1 mask. */ -#define EBI_ROWCOLDLY1_bp 1 /* SDRAM Row-to-Column Delay bit 1 position. */ -#define EBI_ROWCOLDLY2_bm (1<<2) /* SDRAM Row-to-Column Delay bit 2 mask. */ -#define EBI_ROWCOLDLY2_bp 2 /* SDRAM Row-to-Column Delay bit 2 position. */ - - -/* TWI - Two-Wire Interface */ -/* TWI_MASTER.CTRLA bit masks and bit positions */ -#define TWI_MASTER_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ -#define TWI_MASTER_INTLVL_gp 6 /* Interrupt Level group position. */ -#define TWI_MASTER_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ -#define TWI_MASTER_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ -#define TWI_MASTER_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ -#define TWI_MASTER_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ - -#define TWI_MASTER_RIEN_bm 0x20 /* Read Interrupt Enable bit mask. */ -#define TWI_MASTER_RIEN_bp 5 /* Read Interrupt Enable bit position. */ - -#define TWI_MASTER_WIEN_bm 0x10 /* Write Interrupt Enable bit mask. */ -#define TWI_MASTER_WIEN_bp 4 /* Write Interrupt Enable bit position. */ - -#define TWI_MASTER_ENABLE_bm 0x08 /* Enable TWI Master bit mask. */ -#define TWI_MASTER_ENABLE_bp 3 /* Enable TWI Master bit position. */ - - -/* TWI_MASTER.CTRLB bit masks and bit positions */ -#define TWI_MASTER_TIMEOUT_gm 0x0C /* Inactive Bus Timeout group mask. */ -#define TWI_MASTER_TIMEOUT_gp 2 /* Inactive Bus Timeout group position. */ -#define TWI_MASTER_TIMEOUT0_bm (1<<2) /* Inactive Bus Timeout bit 0 mask. */ -#define TWI_MASTER_TIMEOUT0_bp 2 /* Inactive Bus Timeout bit 0 position. */ -#define TWI_MASTER_TIMEOUT1_bm (1<<3) /* Inactive Bus Timeout bit 1 mask. */ -#define TWI_MASTER_TIMEOUT1_bp 3 /* Inactive Bus Timeout bit 1 position. */ - -#define TWI_MASTER_QCEN_bm 0x02 /* Quick Command Enable bit mask. */ -#define TWI_MASTER_QCEN_bp 1 /* Quick Command Enable bit position. */ - -#define TWI_MASTER_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ -#define TWI_MASTER_SMEN_bp 0 /* Smart Mode Enable bit position. */ - - -/* TWI_MASTER.CTRLC bit masks and bit positions */ -#define TWI_MASTER_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ -#define TWI_MASTER_ACKACT_bp 2 /* Acknowledge Action bit position. */ - -#define TWI_MASTER_CMD_gm 0x03 /* Command group mask. */ -#define TWI_MASTER_CMD_gp 0 /* Command group position. */ -#define TWI_MASTER_CMD0_bm (1<<0) /* Command bit 0 mask. */ -#define TWI_MASTER_CMD0_bp 0 /* Command bit 0 position. */ -#define TWI_MASTER_CMD1_bm (1<<1) /* Command bit 1 mask. */ -#define TWI_MASTER_CMD1_bp 1 /* Command bit 1 position. */ - - -/* TWI_MASTER.STATUS bit masks and bit positions */ -#define TWI_MASTER_RIF_bm 0x80 /* Read Interrupt Flag bit mask. */ -#define TWI_MASTER_RIF_bp 7 /* Read Interrupt Flag bit position. */ - -#define TWI_MASTER_WIF_bm 0x40 /* Write Interrupt Flag bit mask. */ -#define TWI_MASTER_WIF_bp 6 /* Write Interrupt Flag bit position. */ - -#define TWI_MASTER_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ -#define TWI_MASTER_CLKHOLD_bp 5 /* Clock Hold bit position. */ - -#define TWI_MASTER_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ -#define TWI_MASTER_RXACK_bp 4 /* Received Acknowledge bit position. */ - -#define TWI_MASTER_ARBLOST_bm 0x08 /* Arbitration Lost bit mask. */ -#define TWI_MASTER_ARBLOST_bp 3 /* Arbitration Lost bit position. */ - -#define TWI_MASTER_BUSERR_bm 0x04 /* Bus Error bit mask. */ -#define TWI_MASTER_BUSERR_bp 2 /* Bus Error bit position. */ - -#define TWI_MASTER_BUSSTATE_gm 0x03 /* Bus State group mask. */ -#define TWI_MASTER_BUSSTATE_gp 0 /* Bus State group position. */ -#define TWI_MASTER_BUSSTATE0_bm (1<<0) /* Bus State bit 0 mask. */ -#define TWI_MASTER_BUSSTATE0_bp 0 /* Bus State bit 0 position. */ -#define TWI_MASTER_BUSSTATE1_bm (1<<1) /* Bus State bit 1 mask. */ -#define TWI_MASTER_BUSSTATE1_bp 1 /* Bus State bit 1 position. */ - - -/* TWI_SLAVE.CTRLA bit masks and bit positions */ -#define TWI_SLAVE_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ -#define TWI_SLAVE_INTLVL_gp 6 /* Interrupt Level group position. */ -#define TWI_SLAVE_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ -#define TWI_SLAVE_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ -#define TWI_SLAVE_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ -#define TWI_SLAVE_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ - -#define TWI_SLAVE_DIEN_bm 0x20 /* Data Interrupt Enable bit mask. */ -#define TWI_SLAVE_DIEN_bp 5 /* Data Interrupt Enable bit position. */ - -#define TWI_SLAVE_APIEN_bm 0x10 /* Address/Stop Interrupt Enable bit mask. */ -#define TWI_SLAVE_APIEN_bp 4 /* Address/Stop Interrupt Enable bit position. */ - -#define TWI_SLAVE_ENABLE_bm 0x08 /* Enable TWI Slave bit mask. */ -#define TWI_SLAVE_ENABLE_bp 3 /* Enable TWI Slave bit position. */ - -#define TWI_SLAVE_PIEN_bm 0x04 /* Stop Interrupt Enable bit mask. */ -#define TWI_SLAVE_PIEN_bp 2 /* Stop Interrupt Enable bit position. */ - -#define TWI_SLAVE_PMEN_bm 0x02 /* Promiscuous Mode Enable bit mask. */ -#define TWI_SLAVE_PMEN_bp 1 /* Promiscuous Mode Enable bit position. */ - -#define TWI_SLAVE_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ -#define TWI_SLAVE_SMEN_bp 0 /* Smart Mode Enable bit position. */ - - -/* TWI_SLAVE.CTRLB bit masks and bit positions */ -#define TWI_SLAVE_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ -#define TWI_SLAVE_ACKACT_bp 2 /* Acknowledge Action bit position. */ - -#define TWI_SLAVE_CMD_gm 0x03 /* Command group mask. */ -#define TWI_SLAVE_CMD_gp 0 /* Command group position. */ -#define TWI_SLAVE_CMD0_bm (1<<0) /* Command bit 0 mask. */ -#define TWI_SLAVE_CMD0_bp 0 /* Command bit 0 position. */ -#define TWI_SLAVE_CMD1_bm (1<<1) /* Command bit 1 mask. */ -#define TWI_SLAVE_CMD1_bp 1 /* Command bit 1 position. */ - - -/* TWI_SLAVE.STATUS bit masks and bit positions */ -#define TWI_SLAVE_DIF_bm 0x80 /* Data Interrupt Flag bit mask. */ -#define TWI_SLAVE_DIF_bp 7 /* Data Interrupt Flag bit position. */ - -#define TWI_SLAVE_APIF_bm 0x40 /* Address/Stop Interrupt Flag bit mask. */ -#define TWI_SLAVE_APIF_bp 6 /* Address/Stop Interrupt Flag bit position. */ - -#define TWI_SLAVE_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ -#define TWI_SLAVE_CLKHOLD_bp 5 /* Clock Hold bit position. */ - -#define TWI_SLAVE_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ -#define TWI_SLAVE_RXACK_bp 4 /* Received Acknowledge bit position. */ - -#define TWI_SLAVE_COLL_bm 0x08 /* Collision bit mask. */ -#define TWI_SLAVE_COLL_bp 3 /* Collision bit position. */ - -#define TWI_SLAVE_BUSERR_bm 0x04 /* Bus Error bit mask. */ -#define TWI_SLAVE_BUSERR_bp 2 /* Bus Error bit position. */ - -#define TWI_SLAVE_DIR_bm 0x02 /* Read/Write Direction bit mask. */ -#define TWI_SLAVE_DIR_bp 1 /* Read/Write Direction bit position. */ - -#define TWI_SLAVE_AP_bm 0x01 /* Slave Address or Stop bit mask. */ -#define TWI_SLAVE_AP_bp 0 /* Slave Address or Stop bit position. */ - - -/* TWI_SLAVE.ADDRMASK bit masks and bit positions */ -#define TWI_SLAVE_ADDRMASK_gm 0xFE /* Address Mask group mask. */ -#define TWI_SLAVE_ADDRMASK_gp 1 /* Address Mask group position. */ -#define TWI_SLAVE_ADDRMASK0_bm (1<<1) /* Address Mask bit 0 mask. */ -#define TWI_SLAVE_ADDRMASK0_bp 1 /* Address Mask bit 0 position. */ -#define TWI_SLAVE_ADDRMASK1_bm (1<<2) /* Address Mask bit 1 mask. */ -#define TWI_SLAVE_ADDRMASK1_bp 2 /* Address Mask bit 1 position. */ -#define TWI_SLAVE_ADDRMASK2_bm (1<<3) /* Address Mask bit 2 mask. */ -#define TWI_SLAVE_ADDRMASK2_bp 3 /* Address Mask bit 2 position. */ -#define TWI_SLAVE_ADDRMASK3_bm (1<<4) /* Address Mask bit 3 mask. */ -#define TWI_SLAVE_ADDRMASK3_bp 4 /* Address Mask bit 3 position. */ -#define TWI_SLAVE_ADDRMASK4_bm (1<<5) /* Address Mask bit 4 mask. */ -#define TWI_SLAVE_ADDRMASK4_bp 5 /* Address Mask bit 4 position. */ -#define TWI_SLAVE_ADDRMASK5_bm (1<<6) /* Address Mask bit 5 mask. */ -#define TWI_SLAVE_ADDRMASK5_bp 6 /* Address Mask bit 5 position. */ -#define TWI_SLAVE_ADDRMASK6_bm (1<<7) /* Address Mask bit 6 mask. */ -#define TWI_SLAVE_ADDRMASK6_bp 7 /* Address Mask bit 6 position. */ - -#define TWI_SLAVE_ADDREN_bm 0x01 /* Address Enable bit mask. */ -#define TWI_SLAVE_ADDREN_bp 0 /* Address Enable bit position. */ - - -/* TWI.CTRL bit masks and bit positions */ -#define TWI_SDAHOLD_bm 0x02 /* SDA Hold Time Enable bit mask. */ -#define TWI_SDAHOLD_bp 1 /* SDA Hold Time Enable bit position. */ - -#define TWI_EDIEN_bm 0x01 /* External Driver Interface Enable bit mask. */ -#define TWI_EDIEN_bp 0 /* External Driver Interface Enable bit position. */ - - -/* PORT - Port Configuration */ -/* PORTCFG.VPCTRLA bit masks and bit positions */ -#define PORTCFG_VP1MAP_gm 0xF0 /* Virtual Port 1 Mapping group mask. */ -#define PORTCFG_VP1MAP_gp 4 /* Virtual Port 1 Mapping group position. */ -#define PORTCFG_VP1MAP0_bm (1<<4) /* Virtual Port 1 Mapping bit 0 mask. */ -#define PORTCFG_VP1MAP0_bp 4 /* Virtual Port 1 Mapping bit 0 position. */ -#define PORTCFG_VP1MAP1_bm (1<<5) /* Virtual Port 1 Mapping bit 1 mask. */ -#define PORTCFG_VP1MAP1_bp 5 /* Virtual Port 1 Mapping bit 1 position. */ -#define PORTCFG_VP1MAP2_bm (1<<6) /* Virtual Port 1 Mapping bit 2 mask. */ -#define PORTCFG_VP1MAP2_bp 6 /* Virtual Port 1 Mapping bit 2 position. */ -#define PORTCFG_VP1MAP3_bm (1<<7) /* Virtual Port 1 Mapping bit 3 mask. */ -#define PORTCFG_VP1MAP3_bp 7 /* Virtual Port 1 Mapping bit 3 position. */ - -#define PORTCFG_VP0MAP_gm 0x0F /* Virtual Port 0 Mapping group mask. */ -#define PORTCFG_VP0MAP_gp 0 /* Virtual Port 0 Mapping group position. */ -#define PORTCFG_VP0MAP0_bm (1<<0) /* Virtual Port 0 Mapping bit 0 mask. */ -#define PORTCFG_VP0MAP0_bp 0 /* Virtual Port 0 Mapping bit 0 position. */ -#define PORTCFG_VP0MAP1_bm (1<<1) /* Virtual Port 0 Mapping bit 1 mask. */ -#define PORTCFG_VP0MAP1_bp 1 /* Virtual Port 0 Mapping bit 1 position. */ -#define PORTCFG_VP0MAP2_bm (1<<2) /* Virtual Port 0 Mapping bit 2 mask. */ -#define PORTCFG_VP0MAP2_bp 2 /* Virtual Port 0 Mapping bit 2 position. */ -#define PORTCFG_VP0MAP3_bm (1<<3) /* Virtual Port 0 Mapping bit 3 mask. */ -#define PORTCFG_VP0MAP3_bp 3 /* Virtual Port 0 Mapping bit 3 position. */ - - -/* PORTCFG.VPCTRLB bit masks and bit positions */ -#define PORTCFG_VP3MAP_gm 0xF0 /* Virtual Port 3 Mapping group mask. */ -#define PORTCFG_VP3MAP_gp 4 /* Virtual Port 3 Mapping group position. */ -#define PORTCFG_VP3MAP0_bm (1<<4) /* Virtual Port 3 Mapping bit 0 mask. */ -#define PORTCFG_VP3MAP0_bp 4 /* Virtual Port 3 Mapping bit 0 position. */ -#define PORTCFG_VP3MAP1_bm (1<<5) /* Virtual Port 3 Mapping bit 1 mask. */ -#define PORTCFG_VP3MAP1_bp 5 /* Virtual Port 3 Mapping bit 1 position. */ -#define PORTCFG_VP3MAP2_bm (1<<6) /* Virtual Port 3 Mapping bit 2 mask. */ -#define PORTCFG_VP3MAP2_bp 6 /* Virtual Port 3 Mapping bit 2 position. */ -#define PORTCFG_VP3MAP3_bm (1<<7) /* Virtual Port 3 Mapping bit 3 mask. */ -#define PORTCFG_VP3MAP3_bp 7 /* Virtual Port 3 Mapping bit 3 position. */ - -#define PORTCFG_VP2MAP_gm 0x0F /* Virtual Port 2 Mapping group mask. */ -#define PORTCFG_VP2MAP_gp 0 /* Virtual Port 2 Mapping group position. */ -#define PORTCFG_VP2MAP0_bm (1<<0) /* Virtual Port 2 Mapping bit 0 mask. */ -#define PORTCFG_VP2MAP0_bp 0 /* Virtual Port 2 Mapping bit 0 position. */ -#define PORTCFG_VP2MAP1_bm (1<<1) /* Virtual Port 2 Mapping bit 1 mask. */ -#define PORTCFG_VP2MAP1_bp 1 /* Virtual Port 2 Mapping bit 1 position. */ -#define PORTCFG_VP2MAP2_bm (1<<2) /* Virtual Port 2 Mapping bit 2 mask. */ -#define PORTCFG_VP2MAP2_bp 2 /* Virtual Port 2 Mapping bit 2 position. */ -#define PORTCFG_VP2MAP3_bm (1<<3) /* Virtual Port 2 Mapping bit 3 mask. */ -#define PORTCFG_VP2MAP3_bp 3 /* Virtual Port 2 Mapping bit 3 position. */ - - -/* PORTCFG.CLKEVOUT bit masks and bit positions */ -#define PORTCFG_CLKOUT_gm 0x03 /* Clock Output Port group mask. */ -#define PORTCFG_CLKOUT_gp 0 /* Clock Output Port group position. */ -#define PORTCFG_CLKOUT0_bm (1<<0) /* Clock Output Port bit 0 mask. */ -#define PORTCFG_CLKOUT0_bp 0 /* Clock Output Port bit 0 position. */ -#define PORTCFG_CLKOUT1_bm (1<<1) /* Clock Output Port bit 1 mask. */ -#define PORTCFG_CLKOUT1_bp 1 /* Clock Output Port bit 1 position. */ - -#define PORTCFG_EVOUT_gm 0x30 /* Event Output Port group mask. */ -#define PORTCFG_EVOUT_gp 4 /* Event Output Port group position. */ -#define PORTCFG_EVOUT0_bm (1<<4) /* Event Output Port bit 0 mask. */ -#define PORTCFG_EVOUT0_bp 4 /* Event Output Port bit 0 position. */ -#define PORTCFG_EVOUT1_bm (1<<5) /* Event Output Port bit 1 mask. */ -#define PORTCFG_EVOUT1_bp 5 /* Event Output Port bit 1 position. */ - - -/* VPORT.INTFLAGS bit masks and bit positions */ -#define VPORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ -#define VPORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ - -#define VPORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ -#define VPORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ - - -/* PORT.INTCTRL bit masks and bit positions */ -#define PORT_INT1LVL_gm 0x0C /* Port Interrupt 1 Level group mask. */ -#define PORT_INT1LVL_gp 2 /* Port Interrupt 1 Level group position. */ -#define PORT_INT1LVL0_bm (1<<2) /* Port Interrupt 1 Level bit 0 mask. */ -#define PORT_INT1LVL0_bp 2 /* Port Interrupt 1 Level bit 0 position. */ -#define PORT_INT1LVL1_bm (1<<3) /* Port Interrupt 1 Level bit 1 mask. */ -#define PORT_INT1LVL1_bp 3 /* Port Interrupt 1 Level bit 1 position. */ - -#define PORT_INT0LVL_gm 0x03 /* Port Interrupt 0 Level group mask. */ -#define PORT_INT0LVL_gp 0 /* Port Interrupt 0 Level group position. */ -#define PORT_INT0LVL0_bm (1<<0) /* Port Interrupt 0 Level bit 0 mask. */ -#define PORT_INT0LVL0_bp 0 /* Port Interrupt 0 Level bit 0 position. */ -#define PORT_INT0LVL1_bm (1<<1) /* Port Interrupt 0 Level bit 1 mask. */ -#define PORT_INT0LVL1_bp 1 /* Port Interrupt 0 Level bit 1 position. */ - - -/* PORT.INTFLAGS bit masks and bit positions */ -#define PORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ -#define PORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ - -#define PORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ -#define PORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ - - -/* PORT.PIN0CTRL bit masks and bit positions */ -#define PORT_SRLEN_bm 0x80 /* Slew Rate Enable bit mask. */ -#define PORT_SRLEN_bp 7 /* Slew Rate Enable bit position. */ - -#define PORT_INVEN_bm 0x40 /* Inverted I/O Enable bit mask. */ -#define PORT_INVEN_bp 6 /* Inverted I/O Enable bit position. */ - -#define PORT_OPC_gm 0x38 /* Output/Pull Configuration group mask. */ -#define PORT_OPC_gp 3 /* Output/Pull Configuration group position. */ -#define PORT_OPC0_bm (1<<3) /* Output/Pull Configuration bit 0 mask. */ -#define PORT_OPC0_bp 3 /* Output/Pull Configuration bit 0 position. */ -#define PORT_OPC1_bm (1<<4) /* Output/Pull Configuration bit 1 mask. */ -#define PORT_OPC1_bp 4 /* Output/Pull Configuration bit 1 position. */ -#define PORT_OPC2_bm (1<<5) /* Output/Pull Configuration bit 2 mask. */ -#define PORT_OPC2_bp 5 /* Output/Pull Configuration bit 2 position. */ - -#define PORT_ISC_gm 0x07 /* Input/Sense Configuration group mask. */ -#define PORT_ISC_gp 0 /* Input/Sense Configuration group position. */ -#define PORT_ISC0_bm (1<<0) /* Input/Sense Configuration bit 0 mask. */ -#define PORT_ISC0_bp 0 /* Input/Sense Configuration bit 0 position. */ -#define PORT_ISC1_bm (1<<1) /* Input/Sense Configuration bit 1 mask. */ -#define PORT_ISC1_bp 1 /* Input/Sense Configuration bit 1 position. */ -#define PORT_ISC2_bm (1<<2) /* Input/Sense Configuration bit 2 mask. */ -#define PORT_ISC2_bp 2 /* Input/Sense Configuration bit 2 position. */ - - -/* PORT.PIN1CTRL bit masks and bit positions */ -/* PORT_SRLEN_bm Predefined. */ -/* PORT_SRLEN_bp Predefined. */ - -/* PORT_INVEN_bm Predefined. */ -/* PORT_INVEN_bp Predefined. */ - -/* PORT_OPC_gm Predefined. */ -/* PORT_OPC_gp Predefined. */ -/* PORT_OPC0_bm Predefined. */ -/* PORT_OPC0_bp Predefined. */ -/* PORT_OPC1_bm Predefined. */ -/* PORT_OPC1_bp Predefined. */ -/* PORT_OPC2_bm Predefined. */ -/* PORT_OPC2_bp Predefined. */ - -/* PORT_ISC_gm Predefined. */ -/* PORT_ISC_gp Predefined. */ -/* PORT_ISC0_bm Predefined. */ -/* PORT_ISC0_bp Predefined. */ -/* PORT_ISC1_bm Predefined. */ -/* PORT_ISC1_bp Predefined. */ -/* PORT_ISC2_bm Predefined. */ -/* PORT_ISC2_bp Predefined. */ - - -/* PORT.PIN2CTRL bit masks and bit positions */ -/* PORT_SRLEN_bm Predefined. */ -/* PORT_SRLEN_bp Predefined. */ - -/* PORT_INVEN_bm Predefined. */ -/* PORT_INVEN_bp Predefined. */ - -/* PORT_OPC_gm Predefined. */ -/* PORT_OPC_gp Predefined. */ -/* PORT_OPC0_bm Predefined. */ -/* PORT_OPC0_bp Predefined. */ -/* PORT_OPC1_bm Predefined. */ -/* PORT_OPC1_bp Predefined. */ -/* PORT_OPC2_bm Predefined. */ -/* PORT_OPC2_bp Predefined. */ - -/* PORT_ISC_gm Predefined. */ -/* PORT_ISC_gp Predefined. */ -/* PORT_ISC0_bm Predefined. */ -/* PORT_ISC0_bp Predefined. */ -/* PORT_ISC1_bm Predefined. */ -/* PORT_ISC1_bp Predefined. */ -/* PORT_ISC2_bm Predefined. */ -/* PORT_ISC2_bp Predefined. */ - - -/* PORT.PIN3CTRL bit masks and bit positions */ -/* PORT_SRLEN_bm Predefined. */ -/* PORT_SRLEN_bp Predefined. */ - -/* PORT_INVEN_bm Predefined. */ -/* PORT_INVEN_bp Predefined. */ - -/* PORT_OPC_gm Predefined. */ -/* PORT_OPC_gp Predefined. */ -/* PORT_OPC0_bm Predefined. */ -/* PORT_OPC0_bp Predefined. */ -/* PORT_OPC1_bm Predefined. */ -/* PORT_OPC1_bp Predefined. */ -/* PORT_OPC2_bm Predefined. */ -/* PORT_OPC2_bp Predefined. */ - -/* PORT_ISC_gm Predefined. */ -/* PORT_ISC_gp Predefined. */ -/* PORT_ISC0_bm Predefined. */ -/* PORT_ISC0_bp Predefined. */ -/* PORT_ISC1_bm Predefined. */ -/* PORT_ISC1_bp Predefined. */ -/* PORT_ISC2_bm Predefined. */ -/* PORT_ISC2_bp Predefined. */ - - -/* PORT.PIN4CTRL bit masks and bit positions */ -/* PORT_SRLEN_bm Predefined. */ -/* PORT_SRLEN_bp Predefined. */ - -/* PORT_INVEN_bm Predefined. */ -/* PORT_INVEN_bp Predefined. */ - -/* PORT_OPC_gm Predefined. */ -/* PORT_OPC_gp Predefined. */ -/* PORT_OPC0_bm Predefined. */ -/* PORT_OPC0_bp Predefined. */ -/* PORT_OPC1_bm Predefined. */ -/* PORT_OPC1_bp Predefined. */ -/* PORT_OPC2_bm Predefined. */ -/* PORT_OPC2_bp Predefined. */ - -/* PORT_ISC_gm Predefined. */ -/* PORT_ISC_gp Predefined. */ -/* PORT_ISC0_bm Predefined. */ -/* PORT_ISC0_bp Predefined. */ -/* PORT_ISC1_bm Predefined. */ -/* PORT_ISC1_bp Predefined. */ -/* PORT_ISC2_bm Predefined. */ -/* PORT_ISC2_bp Predefined. */ - - -/* PORT.PIN5CTRL bit masks and bit positions */ -/* PORT_SRLEN_bm Predefined. */ -/* PORT_SRLEN_bp Predefined. */ - -/* PORT_INVEN_bm Predefined. */ -/* PORT_INVEN_bp Predefined. */ - -/* PORT_OPC_gm Predefined. */ -/* PORT_OPC_gp Predefined. */ -/* PORT_OPC0_bm Predefined. */ -/* PORT_OPC0_bp Predefined. */ -/* PORT_OPC1_bm Predefined. */ -/* PORT_OPC1_bp Predefined. */ -/* PORT_OPC2_bm Predefined. */ -/* PORT_OPC2_bp Predefined. */ - -/* PORT_ISC_gm Predefined. */ -/* PORT_ISC_gp Predefined. */ -/* PORT_ISC0_bm Predefined. */ -/* PORT_ISC0_bp Predefined. */ -/* PORT_ISC1_bm Predefined. */ -/* PORT_ISC1_bp Predefined. */ -/* PORT_ISC2_bm Predefined. */ -/* PORT_ISC2_bp Predefined. */ - - -/* PORT.PIN6CTRL bit masks and bit positions */ -/* PORT_SRLEN_bm Predefined. */ -/* PORT_SRLEN_bp Predefined. */ - -/* PORT_INVEN_bm Predefined. */ -/* PORT_INVEN_bp Predefined. */ - -/* PORT_OPC_gm Predefined. */ -/* PORT_OPC_gp Predefined. */ -/* PORT_OPC0_bm Predefined. */ -/* PORT_OPC0_bp Predefined. */ -/* PORT_OPC1_bm Predefined. */ -/* PORT_OPC1_bp Predefined. */ -/* PORT_OPC2_bm Predefined. */ -/* PORT_OPC2_bp Predefined. */ - -/* PORT_ISC_gm Predefined. */ -/* PORT_ISC_gp Predefined. */ -/* PORT_ISC0_bm Predefined. */ -/* PORT_ISC0_bp Predefined. */ -/* PORT_ISC1_bm Predefined. */ -/* PORT_ISC1_bp Predefined. */ -/* PORT_ISC2_bm Predefined. */ -/* PORT_ISC2_bp Predefined. */ - - -/* PORT.PIN7CTRL bit masks and bit positions */ -/* PORT_SRLEN_bm Predefined. */ -/* PORT_SRLEN_bp Predefined. */ - -/* PORT_INVEN_bm Predefined. */ -/* PORT_INVEN_bp Predefined. */ - -/* PORT_OPC_gm Predefined. */ -/* PORT_OPC_gp Predefined. */ -/* PORT_OPC0_bm Predefined. */ -/* PORT_OPC0_bp Predefined. */ -/* PORT_OPC1_bm Predefined. */ -/* PORT_OPC1_bp Predefined. */ -/* PORT_OPC2_bm Predefined. */ -/* PORT_OPC2_bp Predefined. */ - -/* PORT_ISC_gm Predefined. */ -/* PORT_ISC_gp Predefined. */ -/* PORT_ISC0_bm Predefined. */ -/* PORT_ISC0_bp Predefined. */ -/* PORT_ISC1_bm Predefined. */ -/* PORT_ISC1_bp Predefined. */ -/* PORT_ISC2_bm Predefined. */ -/* PORT_ISC2_bp Predefined. */ - - -/* TC - 16-bit Timer/Counter With PWM */ -/* TC0.CTRLA bit masks and bit positions */ -#define TC0_CLKSEL_gm 0x0F /* Clock Selection group mask. */ -#define TC0_CLKSEL_gp 0 /* Clock Selection group position. */ -#define TC0_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ -#define TC0_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ -#define TC0_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ -#define TC0_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ -#define TC0_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ -#define TC0_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ -#define TC0_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ -#define TC0_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ - - -/* TC0.CTRLB bit masks and bit positions */ -#define TC0_CCDEN_bm 0x80 /* Compare or Capture D Enable bit mask. */ -#define TC0_CCDEN_bp 7 /* Compare or Capture D Enable bit position. */ - -#define TC0_CCCEN_bm 0x40 /* Compare or Capture C Enable bit mask. */ -#define TC0_CCCEN_bp 6 /* Compare or Capture C Enable bit position. */ - -#define TC0_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ -#define TC0_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ - -#define TC0_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ -#define TC0_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ - -#define TC0_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ -#define TC0_WGMODE_gp 0 /* Waveform generation mode group position. */ -#define TC0_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ -#define TC0_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ -#define TC0_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ -#define TC0_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ -#define TC0_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ -#define TC0_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ - - -/* TC0.CTRLC bit masks and bit positions */ -#define TC0_CMPD_bm 0x08 /* Compare D Output Value bit mask. */ -#define TC0_CMPD_bp 3 /* Compare D Output Value bit position. */ - -#define TC0_CMPC_bm 0x04 /* Compare C Output Value bit mask. */ -#define TC0_CMPC_bp 2 /* Compare C Output Value bit position. */ - -#define TC0_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ -#define TC0_CMPB_bp 1 /* Compare B Output Value bit position. */ - -#define TC0_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ -#define TC0_CMPA_bp 0 /* Compare A Output Value bit position. */ - - -/* TC0.CTRLD bit masks and bit positions */ -#define TC0_EVACT_gm 0xE0 /* Event Action group mask. */ -#define TC0_EVACT_gp 5 /* Event Action group position. */ -#define TC0_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ -#define TC0_EVACT0_bp 5 /* Event Action bit 0 position. */ -#define TC0_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ -#define TC0_EVACT1_bp 6 /* Event Action bit 1 position. */ -#define TC0_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ -#define TC0_EVACT2_bp 7 /* Event Action bit 2 position. */ - -#define TC0_EVDLY_bm 0x10 /* Event Delay bit mask. */ -#define TC0_EVDLY_bp 4 /* Event Delay bit position. */ - -#define TC0_EVSEL_gm 0x0F /* Event Source Select group mask. */ -#define TC0_EVSEL_gp 0 /* Event Source Select group position. */ -#define TC0_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ -#define TC0_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ -#define TC0_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ -#define TC0_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ -#define TC0_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ -#define TC0_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ -#define TC0_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ -#define TC0_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ - - -/* TC0.CTRLE bit masks and bit positions */ -#define TC0_DTHM_bm 0x02 /* Dead Time Hold Mode bit mask. */ -#define TC0_DTHM_bp 1 /* Dead Time Hold Mode bit position. */ - -#define TC0_BYTEM_bm 0x01 /* Byte Mode bit mask. */ -#define TC0_BYTEM_bp 0 /* Byte Mode bit position. */ - - -/* TC0.INTCTRLA bit masks and bit positions */ -#define TC0_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ -#define TC0_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ -#define TC0_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ -#define TC0_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ -#define TC0_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ -#define TC0_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ - -#define TC0_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ -#define TC0_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ -#define TC0_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ -#define TC0_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ -#define TC0_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ -#define TC0_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ - - -/* TC0.INTCTRLB bit masks and bit positions */ -#define TC0_CCDINTLVL_gm 0xC0 /* Compare or Capture D Interrupt Level group mask. */ -#define TC0_CCDINTLVL_gp 6 /* Compare or Capture D Interrupt Level group position. */ -#define TC0_CCDINTLVL0_bm (1<<6) /* Compare or Capture D Interrupt Level bit 0 mask. */ -#define TC0_CCDINTLVL0_bp 6 /* Compare or Capture D Interrupt Level bit 0 position. */ -#define TC0_CCDINTLVL1_bm (1<<7) /* Compare or Capture D Interrupt Level bit 1 mask. */ -#define TC0_CCDINTLVL1_bp 7 /* Compare or Capture D Interrupt Level bit 1 position. */ - -#define TC0_CCCINTLVL_gm 0x30 /* Compare or Capture C Interrupt Level group mask. */ -#define TC0_CCCINTLVL_gp 4 /* Compare or Capture C Interrupt Level group position. */ -#define TC0_CCCINTLVL0_bm (1<<4) /* Compare or Capture C Interrupt Level bit 0 mask. */ -#define TC0_CCCINTLVL0_bp 4 /* Compare or Capture C Interrupt Level bit 0 position. */ -#define TC0_CCCINTLVL1_bm (1<<5) /* Compare or Capture C Interrupt Level bit 1 mask. */ -#define TC0_CCCINTLVL1_bp 5 /* Compare or Capture C Interrupt Level bit 1 position. */ - -#define TC0_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ -#define TC0_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ -#define TC0_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ -#define TC0_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ -#define TC0_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ -#define TC0_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ - -#define TC0_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ -#define TC0_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ -#define TC0_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ -#define TC0_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ -#define TC0_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ -#define TC0_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ - - -/* TC0.CTRLFCLR bit masks and bit positions */ -#define TC0_CMD_gm 0x0C /* Command group mask. */ -#define TC0_CMD_gp 2 /* Command group position. */ -#define TC0_CMD0_bm (1<<2) /* Command bit 0 mask. */ -#define TC0_CMD0_bp 2 /* Command bit 0 position. */ -#define TC0_CMD1_bm (1<<3) /* Command bit 1 mask. */ -#define TC0_CMD1_bp 3 /* Command bit 1 position. */ - -#define TC0_LUPD_bm 0x02 /* Lock Update bit mask. */ -#define TC0_LUPD_bp 1 /* Lock Update bit position. */ - -#define TC0_DIR_bm 0x01 /* Direction bit mask. */ -#define TC0_DIR_bp 0 /* Direction bit position. */ - - -/* TC0.CTRLFSET bit masks and bit positions */ -/* TC0_CMD_gm Predefined. */ -/* TC0_CMD_gp Predefined. */ -/* TC0_CMD0_bm Predefined. */ -/* TC0_CMD0_bp Predefined. */ -/* TC0_CMD1_bm Predefined. */ -/* TC0_CMD1_bp Predefined. */ - -/* TC0_LUPD_bm Predefined. */ -/* TC0_LUPD_bp Predefined. */ - -/* TC0_DIR_bm Predefined. */ -/* TC0_DIR_bp Predefined. */ - - -/* TC0.CTRLGCLR bit masks and bit positions */ -#define TC0_CCDBV_bm 0x10 /* Compare or Capture D Buffer Valid bit mask. */ -#define TC0_CCDBV_bp 4 /* Compare or Capture D Buffer Valid bit position. */ - -#define TC0_CCCBV_bm 0x08 /* Compare or Capture C Buffer Valid bit mask. */ -#define TC0_CCCBV_bp 3 /* Compare or Capture C Buffer Valid bit position. */ - -#define TC0_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ -#define TC0_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ - -#define TC0_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ -#define TC0_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ - -#define TC0_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ -#define TC0_PERBV_bp 0 /* Period Buffer Valid bit position. */ - - -/* TC0.CTRLGSET bit masks and bit positions */ -/* TC0_CCDBV_bm Predefined. */ -/* TC0_CCDBV_bp Predefined. */ - -/* TC0_CCCBV_bm Predefined. */ -/* TC0_CCCBV_bp Predefined. */ - -/* TC0_CCBBV_bm Predefined. */ -/* TC0_CCBBV_bp Predefined. */ - -/* TC0_CCABV_bm Predefined. */ -/* TC0_CCABV_bp Predefined. */ - -/* TC0_PERBV_bm Predefined. */ -/* TC0_PERBV_bp Predefined. */ - - -/* TC0.INTFLAGS bit masks and bit positions */ -#define TC0_CCDIF_bm 0x80 /* Compare or Capture D Interrupt Flag bit mask. */ -#define TC0_CCDIF_bp 7 /* Compare or Capture D Interrupt Flag bit position. */ - -#define TC0_CCCIF_bm 0x40 /* Compare or Capture C Interrupt Flag bit mask. */ -#define TC0_CCCIF_bp 6 /* Compare or Capture C Interrupt Flag bit position. */ - -#define TC0_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ -#define TC0_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ - -#define TC0_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ -#define TC0_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ - -#define TC0_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ -#define TC0_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ - -#define TC0_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ -#define TC0_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ - - -/* TC1.CTRLA bit masks and bit positions */ -#define TC1_CLKSEL_gm 0x0F /* Clock Selection group mask. */ -#define TC1_CLKSEL_gp 0 /* Clock Selection group position. */ -#define TC1_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ -#define TC1_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ -#define TC1_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ -#define TC1_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ -#define TC1_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ -#define TC1_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ -#define TC1_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ -#define TC1_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ - - -/* TC1.CTRLB bit masks and bit positions */ -#define TC1_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ -#define TC1_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ - -#define TC1_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ -#define TC1_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ - -#define TC1_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ -#define TC1_WGMODE_gp 0 /* Waveform generation mode group position. */ -#define TC1_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ -#define TC1_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ -#define TC1_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ -#define TC1_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ -#define TC1_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ -#define TC1_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ - - -/* TC1.CTRLC bit masks and bit positions */ -#define TC1_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ -#define TC1_CMPB_bp 1 /* Compare B Output Value bit position. */ - -#define TC1_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ -#define TC1_CMPA_bp 0 /* Compare A Output Value bit position. */ - - -/* TC1.CTRLD bit masks and bit positions */ -#define TC1_EVACT_gm 0xE0 /* Event Action group mask. */ -#define TC1_EVACT_gp 5 /* Event Action group position. */ -#define TC1_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ -#define TC1_EVACT0_bp 5 /* Event Action bit 0 position. */ -#define TC1_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ -#define TC1_EVACT1_bp 6 /* Event Action bit 1 position. */ -#define TC1_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ -#define TC1_EVACT2_bp 7 /* Event Action bit 2 position. */ - -#define TC1_EVDLY_bm 0x10 /* Event Delay bit mask. */ -#define TC1_EVDLY_bp 4 /* Event Delay bit position. */ - -#define TC1_EVSEL_gm 0x0F /* Event Source Select group mask. */ -#define TC1_EVSEL_gp 0 /* Event Source Select group position. */ -#define TC1_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ -#define TC1_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ -#define TC1_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ -#define TC1_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ -#define TC1_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ -#define TC1_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ -#define TC1_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ -#define TC1_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ - - -/* TC1.CTRLE bit masks and bit positions */ -#define TC1_DTHM_bm 0x02 /* Dead Time Hold Mode bit mask. */ -#define TC1_DTHM_bp 1 /* Dead Time Hold Mode bit position. */ - -#define TC1_BYTEM_bm 0x01 /* Byte Mode bit mask. */ -#define TC1_BYTEM_bp 0 /* Byte Mode bit position. */ - - -/* TC1.INTCTRLA bit masks and bit positions */ -#define TC1_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ -#define TC1_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ -#define TC1_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ -#define TC1_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ -#define TC1_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ -#define TC1_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ - -#define TC1_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ -#define TC1_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ -#define TC1_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ -#define TC1_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ -#define TC1_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ -#define TC1_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ - - -/* TC1.INTCTRLB bit masks and bit positions */ -#define TC1_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ -#define TC1_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ -#define TC1_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ -#define TC1_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ -#define TC1_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ -#define TC1_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ - -#define TC1_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ -#define TC1_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ -#define TC1_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ -#define TC1_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ -#define TC1_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ -#define TC1_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ - - -/* TC1.CTRLFCLR bit masks and bit positions */ -#define TC1_CMD_gm 0x0C /* Command group mask. */ -#define TC1_CMD_gp 2 /* Command group position. */ -#define TC1_CMD0_bm (1<<2) /* Command bit 0 mask. */ -#define TC1_CMD0_bp 2 /* Command bit 0 position. */ -#define TC1_CMD1_bm (1<<3) /* Command bit 1 mask. */ -#define TC1_CMD1_bp 3 /* Command bit 1 position. */ - -#define TC1_LUPD_bm 0x02 /* Lock Update bit mask. */ -#define TC1_LUPD_bp 1 /* Lock Update bit position. */ - -#define TC1_DIR_bm 0x01 /* Direction bit mask. */ -#define TC1_DIR_bp 0 /* Direction bit position. */ - - -/* TC1.CTRLFSET bit masks and bit positions */ -/* TC1_CMD_gm Predefined. */ -/* TC1_CMD_gp Predefined. */ -/* TC1_CMD0_bm Predefined. */ -/* TC1_CMD0_bp Predefined. */ -/* TC1_CMD1_bm Predefined. */ -/* TC1_CMD1_bp Predefined. */ - -/* TC1_LUPD_bm Predefined. */ -/* TC1_LUPD_bp Predefined. */ - -/* TC1_DIR_bm Predefined. */ -/* TC1_DIR_bp Predefined. */ - - -/* TC1.CTRLGCLR bit masks and bit positions */ -#define TC1_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ -#define TC1_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ - -#define TC1_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ -#define TC1_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ - -#define TC1_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ -#define TC1_PERBV_bp 0 /* Period Buffer Valid bit position. */ - - -/* TC1.CTRLGSET bit masks and bit positions */ -/* TC1_CCBBV_bm Predefined. */ -/* TC1_CCBBV_bp Predefined. */ - -/* TC1_CCABV_bm Predefined. */ -/* TC1_CCABV_bp Predefined. */ - -/* TC1_PERBV_bm Predefined. */ -/* TC1_PERBV_bp Predefined. */ - - -/* TC1.INTFLAGS bit masks and bit positions */ -#define TC1_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ -#define TC1_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ - -#define TC1_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ -#define TC1_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ - -#define TC1_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ -#define TC1_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ - -#define TC1_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ -#define TC1_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ - - -/* AWEX.CTRL bit masks and bit positions */ -#define AWEX_PGM_bm 0x20 /* Pattern Generation Mode bit mask. */ -#define AWEX_PGM_bp 5 /* Pattern Generation Mode bit position. */ - -#define AWEX_CWCM_bm 0x10 /* Common Waveform Channel Mode bit mask. */ -#define AWEX_CWCM_bp 4 /* Common Waveform Channel Mode bit position. */ - -#define AWEX_DTICCDEN_bm 0x08 /* Dead Time Insertion Compare Channel D Enable bit mask. */ -#define AWEX_DTICCDEN_bp 3 /* Dead Time Insertion Compare Channel D Enable bit position. */ - -#define AWEX_DTICCCEN_bm 0x04 /* Dead Time Insertion Compare Channel C Enable bit mask. */ -#define AWEX_DTICCCEN_bp 2 /* Dead Time Insertion Compare Channel C Enable bit position. */ - -#define AWEX_DTICCBEN_bm 0x02 /* Dead Time Insertion Compare Channel B Enable bit mask. */ -#define AWEX_DTICCBEN_bp 1 /* Dead Time Insertion Compare Channel B Enable bit position. */ - -#define AWEX_DTICCAEN_bm 0x01 /* Dead Time Insertion Compare Channel A Enable bit mask. */ -#define AWEX_DTICCAEN_bp 0 /* Dead Time Insertion Compare Channel A Enable bit position. */ - - -/* AWEX.FDCTRL bit masks and bit positions */ -#define AWEX_FDDBD_bm 0x10 /* Fault Detect on Disable Break Disable bit mask. */ -#define AWEX_FDDBD_bp 4 /* Fault Detect on Disable Break Disable bit position. */ - -#define AWEX_FDMODE_bm 0x04 /* Fault Detect Mode bit mask. */ -#define AWEX_FDMODE_bp 2 /* Fault Detect Mode bit position. */ - -#define AWEX_FDACT_gm 0x03 /* Fault Detect Action group mask. */ -#define AWEX_FDACT_gp 0 /* Fault Detect Action group position. */ -#define AWEX_FDACT0_bm (1<<0) /* Fault Detect Action bit 0 mask. */ -#define AWEX_FDACT0_bp 0 /* Fault Detect Action bit 0 position. */ -#define AWEX_FDACT1_bm (1<<1) /* Fault Detect Action bit 1 mask. */ -#define AWEX_FDACT1_bp 1 /* Fault Detect Action bit 1 position. */ - - -/* AWEX.STATUS bit masks and bit positions */ -#define AWEX_FDF_bm 0x04 /* Fault Detect Flag bit mask. */ -#define AWEX_FDF_bp 2 /* Fault Detect Flag bit position. */ - -#define AWEX_DTHSBUFV_bm 0x02 /* Dead Time High Side Buffer Valid bit mask. */ -#define AWEX_DTHSBUFV_bp 1 /* Dead Time High Side Buffer Valid bit position. */ - -#define AWEX_DTLSBUFV_bm 0x01 /* Dead Time Low Side Buffer Valid bit mask. */ -#define AWEX_DTLSBUFV_bp 0 /* Dead Time Low Side Buffer Valid bit position. */ - - -/* HIRES.CTRL bit masks and bit positions */ -#define HIRES_HREN_gm 0x03 /* High Resolution Enable group mask. */ -#define HIRES_HREN_gp 0 /* High Resolution Enable group position. */ -#define HIRES_HREN0_bm (1<<0) /* High Resolution Enable bit 0 mask. */ -#define HIRES_HREN0_bp 0 /* High Resolution Enable bit 0 position. */ -#define HIRES_HREN1_bm (1<<1) /* High Resolution Enable bit 1 mask. */ -#define HIRES_HREN1_bp 1 /* High Resolution Enable bit 1 position. */ - - -/* USART - Universal Asynchronous Receiver-Transmitter */ -/* USART.STATUS bit masks and bit positions */ -#define USART_RXCIF_bm 0x80 /* Receive Interrupt Flag bit mask. */ -#define USART_RXCIF_bp 7 /* Receive Interrupt Flag bit position. */ - -#define USART_TXCIF_bm 0x40 /* Transmit Interrupt Flag bit mask. */ -#define USART_TXCIF_bp 6 /* Transmit Interrupt Flag bit position. */ - -#define USART_DREIF_bm 0x20 /* Data Register Empty Flag bit mask. */ -#define USART_DREIF_bp 5 /* Data Register Empty Flag bit position. */ - -#define USART_FERR_bm 0x10 /* Frame Error bit mask. */ -#define USART_FERR_bp 4 /* Frame Error bit position. */ - -#define USART_BUFOVF_bm 0x08 /* Buffer Overflow bit mask. */ -#define USART_BUFOVF_bp 3 /* Buffer Overflow bit position. */ - -#define USART_PERR_bm 0x04 /* Parity Error bit mask. */ -#define USART_PERR_bp 2 /* Parity Error bit position. */ - -#define USART_RXB8_bm 0x01 /* Receive Bit 8 bit mask. */ -#define USART_RXB8_bp 0 /* Receive Bit 8 bit position. */ - - -/* USART.CTRLA bit masks and bit positions */ -#define USART_RXCINTLVL_gm 0x30 /* Receive Interrupt Level group mask. */ -#define USART_RXCINTLVL_gp 4 /* Receive Interrupt Level group position. */ -#define USART_RXCINTLVL0_bm (1<<4) /* Receive Interrupt Level bit 0 mask. */ -#define USART_RXCINTLVL0_bp 4 /* Receive Interrupt Level bit 0 position. */ -#define USART_RXCINTLVL1_bm (1<<5) /* Receive Interrupt Level bit 1 mask. */ -#define USART_RXCINTLVL1_bp 5 /* Receive Interrupt Level bit 1 position. */ - -#define USART_TXCINTLVL_gm 0x0C /* Transmit Interrupt Level group mask. */ -#define USART_TXCINTLVL_gp 2 /* Transmit Interrupt Level group position. */ -#define USART_TXCINTLVL0_bm (1<<2) /* Transmit Interrupt Level bit 0 mask. */ -#define USART_TXCINTLVL0_bp 2 /* Transmit Interrupt Level bit 0 position. */ -#define USART_TXCINTLVL1_bm (1<<3) /* Transmit Interrupt Level bit 1 mask. */ -#define USART_TXCINTLVL1_bp 3 /* Transmit Interrupt Level bit 1 position. */ - -#define USART_DREINTLVL_gm 0x03 /* Data Register Empty Interrupt Level group mask. */ -#define USART_DREINTLVL_gp 0 /* Data Register Empty Interrupt Level group position. */ -#define USART_DREINTLVL0_bm (1<<0) /* Data Register Empty Interrupt Level bit 0 mask. */ -#define USART_DREINTLVL0_bp 0 /* Data Register Empty Interrupt Level bit 0 position. */ -#define USART_DREINTLVL1_bm (1<<1) /* Data Register Empty Interrupt Level bit 1 mask. */ -#define USART_DREINTLVL1_bp 1 /* Data Register Empty Interrupt Level bit 1 position. */ - - -/* USART.CTRLB bit masks and bit positions */ -#define USART_RXEN_bm 0x10 /* Receiver Enable bit mask. */ -#define USART_RXEN_bp 4 /* Receiver Enable bit position. */ - -#define USART_TXEN_bm 0x08 /* Transmitter Enable bit mask. */ -#define USART_TXEN_bp 3 /* Transmitter Enable bit position. */ - -#define USART_CLK2X_bm 0x04 /* Double transmission speed bit mask. */ -#define USART_CLK2X_bp 2 /* Double transmission speed bit position. */ - -#define USART_MPCM_bm 0x02 /* Multi-processor Communication Mode bit mask. */ -#define USART_MPCM_bp 1 /* Multi-processor Communication Mode bit position. */ - -#define USART_TXB8_bm 0x01 /* Transmit bit 8 bit mask. */ -#define USART_TXB8_bp 0 /* Transmit bit 8 bit position. */ - - -/* USART.CTRLC bit masks and bit positions */ -#define USART_CMODE_gm 0xC0 /* Communication Mode group mask. */ -#define USART_CMODE_gp 6 /* Communication Mode group position. */ -#define USART_CMODE0_bm (1<<6) /* Communication Mode bit 0 mask. */ -#define USART_CMODE0_bp 6 /* Communication Mode bit 0 position. */ -#define USART_CMODE1_bm (1<<7) /* Communication Mode bit 1 mask. */ -#define USART_CMODE1_bp 7 /* Communication Mode bit 1 position. */ - -#define USART_PMODE_gm 0x30 /* Parity Mode group mask. */ -#define USART_PMODE_gp 4 /* Parity Mode group position. */ -#define USART_PMODE0_bm (1<<4) /* Parity Mode bit 0 mask. */ -#define USART_PMODE0_bp 4 /* Parity Mode bit 0 position. */ -#define USART_PMODE1_bm (1<<5) /* Parity Mode bit 1 mask. */ -#define USART_PMODE1_bp 5 /* Parity Mode bit 1 position. */ - -#define USART_SBMODE_bm 0x08 /* Stop Bit Mode bit mask. */ -#define USART_SBMODE_bp 3 /* Stop Bit Mode bit position. */ - -#define USART_CHSIZE_gm 0x07 /* Character Size group mask. */ -#define USART_CHSIZE_gp 0 /* Character Size group position. */ -#define USART_CHSIZE0_bm (1<<0) /* Character Size bit 0 mask. */ -#define USART_CHSIZE0_bp 0 /* Character Size bit 0 position. */ -#define USART_CHSIZE1_bm (1<<1) /* Character Size bit 1 mask. */ -#define USART_CHSIZE1_bp 1 /* Character Size bit 1 position. */ -#define USART_CHSIZE2_bm (1<<2) /* Character Size bit 2 mask. */ -#define USART_CHSIZE2_bp 2 /* Character Size bit 2 position. */ - - -/* USART.BAUDCTRLA bit masks and bit positions */ -#define USART_BSEL_gm 0xFF /* Baud Rate Selection Bits [7:0] group mask. */ -#define USART_BSEL_gp 0 /* Baud Rate Selection Bits [7:0] group position. */ -#define USART_BSEL0_bm (1<<0) /* Baud Rate Selection Bits [7:0] bit 0 mask. */ -#define USART_BSEL0_bp 0 /* Baud Rate Selection Bits [7:0] bit 0 position. */ -#define USART_BSEL1_bm (1<<1) /* Baud Rate Selection Bits [7:0] bit 1 mask. */ -#define USART_BSEL1_bp 1 /* Baud Rate Selection Bits [7:0] bit 1 position. */ -#define USART_BSEL2_bm (1<<2) /* Baud Rate Selection Bits [7:0] bit 2 mask. */ -#define USART_BSEL2_bp 2 /* Baud Rate Selection Bits [7:0] bit 2 position. */ -#define USART_BSEL3_bm (1<<3) /* Baud Rate Selection Bits [7:0] bit 3 mask. */ -#define USART_BSEL3_bp 3 /* Baud Rate Selection Bits [7:0] bit 3 position. */ -#define USART_BSEL4_bm (1<<4) /* Baud Rate Selection Bits [7:0] bit 4 mask. */ -#define USART_BSEL4_bp 4 /* Baud Rate Selection Bits [7:0] bit 4 position. */ -#define USART_BSEL5_bm (1<<5) /* Baud Rate Selection Bits [7:0] bit 5 mask. */ -#define USART_BSEL5_bp 5 /* Baud Rate Selection Bits [7:0] bit 5 position. */ -#define USART_BSEL6_bm (1<<6) /* Baud Rate Selection Bits [7:0] bit 6 mask. */ -#define USART_BSEL6_bp 6 /* Baud Rate Selection Bits [7:0] bit 6 position. */ -#define USART_BSEL7_bm (1<<7) /* Baud Rate Selection Bits [7:0] bit 7 mask. */ -#define USART_BSEL7_bp 7 /* Baud Rate Selection Bits [7:0] bit 7 position. */ - - -/* USART.BAUDCTRLB bit masks and bit positions */ -#define USART_BSCALE_gm 0xF0 /* Baud Rate Scale group mask. */ -#define USART_BSCALE_gp 4 /* Baud Rate Scale group position. */ -#define USART_BSCALE0_bm (1<<4) /* Baud Rate Scale bit 0 mask. */ -#define USART_BSCALE0_bp 4 /* Baud Rate Scale bit 0 position. */ -#define USART_BSCALE1_bm (1<<5) /* Baud Rate Scale bit 1 mask. */ -#define USART_BSCALE1_bp 5 /* Baud Rate Scale bit 1 position. */ -#define USART_BSCALE2_bm (1<<6) /* Baud Rate Scale bit 2 mask. */ -#define USART_BSCALE2_bp 6 /* Baud Rate Scale bit 2 position. */ -#define USART_BSCALE3_bm (1<<7) /* Baud Rate Scale bit 3 mask. */ -#define USART_BSCALE3_bp 7 /* Baud Rate Scale bit 3 position. */ - -/* USART_BSEL_gm Predefined. */ -/* USART_BSEL_gp Predefined. */ -/* USART_BSEL0_bm Predefined. */ -/* USART_BSEL0_bp Predefined. */ -/* USART_BSEL1_bm Predefined. */ -/* USART_BSEL1_bp Predefined. */ -/* USART_BSEL2_bm Predefined. */ -/* USART_BSEL2_bp Predefined. */ -/* USART_BSEL3_bm Predefined. */ -/* USART_BSEL3_bp Predefined. */ - - -/* SPI - Serial Peripheral Interface */ -/* SPI.CTRL bit masks and bit positions */ -#define SPI_CLK2X_bm 0x80 /* Enable Double Speed bit mask. */ -#define SPI_CLK2X_bp 7 /* Enable Double Speed bit position. */ - -#define SPI_ENABLE_bm 0x40 /* Enable Module bit mask. */ -#define SPI_ENABLE_bp 6 /* Enable Module bit position. */ - -#define SPI_DORD_bm 0x20 /* Data Order Setting bit mask. */ -#define SPI_DORD_bp 5 /* Data Order Setting bit position. */ - -#define SPI_MASTER_bm 0x10 /* Master Operation Enable bit mask. */ -#define SPI_MASTER_bp 4 /* Master Operation Enable bit position. */ - -#define SPI_MODE_gm 0x0C /* SPI Mode group mask. */ -#define SPI_MODE_gp 2 /* SPI Mode group position. */ -#define SPI_MODE0_bm (1<<2) /* SPI Mode bit 0 mask. */ -#define SPI_MODE0_bp 2 /* SPI Mode bit 0 position. */ -#define SPI_MODE1_bm (1<<3) /* SPI Mode bit 1 mask. */ -#define SPI_MODE1_bp 3 /* SPI Mode bit 1 position. */ - -#define SPI_PRESCALER_gm 0x03 /* Prescaler group mask. */ -#define SPI_PRESCALER_gp 0 /* Prescaler group position. */ -#define SPI_PRESCALER0_bm (1<<0) /* Prescaler bit 0 mask. */ -#define SPI_PRESCALER0_bp 0 /* Prescaler bit 0 position. */ -#define SPI_PRESCALER1_bm (1<<1) /* Prescaler bit 1 mask. */ -#define SPI_PRESCALER1_bp 1 /* Prescaler bit 1 position. */ - - -/* SPI.INTCTRL bit masks and bit positions */ -#define SPI_INTLVL_gm 0x03 /* Interrupt level group mask. */ -#define SPI_INTLVL_gp 0 /* Interrupt level group position. */ -#define SPI_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */ -#define SPI_INTLVL0_bp 0 /* Interrupt level bit 0 position. */ -#define SPI_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */ -#define SPI_INTLVL1_bp 1 /* Interrupt level bit 1 position. */ - - -/* SPI.STATUS bit masks and bit positions */ -#define SPI_IF_bm 0x80 /* Interrupt Flag bit mask. */ -#define SPI_IF_bp 7 /* Interrupt Flag bit position. */ - -#define SPI_WRCOL_bm 0x40 /* Write Collision bit mask. */ -#define SPI_WRCOL_bp 6 /* Write Collision bit position. */ - - -/* IRCOM - IR Communication Module */ -/* IRCOM.CTRL bit masks and bit positions */ -#define IRCOM_EVSEL_gm 0x0F /* Event Channel Select group mask. */ -#define IRCOM_EVSEL_gp 0 /* Event Channel Select group position. */ -#define IRCOM_EVSEL0_bm (1<<0) /* Event Channel Select bit 0 mask. */ -#define IRCOM_EVSEL0_bp 0 /* Event Channel Select bit 0 position. */ -#define IRCOM_EVSEL1_bm (1<<1) /* Event Channel Select bit 1 mask. */ -#define IRCOM_EVSEL1_bp 1 /* Event Channel Select bit 1 position. */ -#define IRCOM_EVSEL2_bm (1<<2) /* Event Channel Select bit 2 mask. */ -#define IRCOM_EVSEL2_bp 2 /* Event Channel Select bit 2 position. */ -#define IRCOM_EVSEL3_bm (1<<3) /* Event Channel Select bit 3 mask. */ -#define IRCOM_EVSEL3_bp 3 /* Event Channel Select bit 3 position. */ - - -/* AES - AES Module */ -/* AES.CTRL bit masks and bit positions */ -#define AES_START_bm 0x80 /* Start/Run bit mask. */ -#define AES_START_bp 7 /* Start/Run bit position. */ - -#define AES_AUTO_bm 0x40 /* Auto Start Trigger bit mask. */ -#define AES_AUTO_bp 6 /* Auto Start Trigger bit position. */ - -#define AES_RESET_bm 0x20 /* AES Software Reset bit mask. */ -#define AES_RESET_bp 5 /* AES Software Reset bit position. */ - -#define AES_DECRYPT_bm 0x10 /* Decryption / Direction bit mask. */ -#define AES_DECRYPT_bp 4 /* Decryption / Direction bit position. */ - -#define AES_XOR_bm 0x04 /* State XOR Load Enable bit mask. */ -#define AES_XOR_bp 2 /* State XOR Load Enable bit position. */ - - -/* AES.STATUS bit masks and bit positions */ -#define AES_ERROR_bm 0x80 /* AES Error bit mask. */ -#define AES_ERROR_bp 7 /* AES Error bit position. */ - -#define AES_SRIF_bm 0x01 /* State Ready Interrupt Flag bit mask. */ -#define AES_SRIF_bp 0 /* State Ready Interrupt Flag bit position. */ - - -/* AES.INTCTRL bit masks and bit positions */ -#define AES_INTLVL_gm 0x03 /* Interrupt level group mask. */ -#define AES_INTLVL_gp 0 /* Interrupt level group position. */ -#define AES_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */ -#define AES_INTLVL0_bp 0 /* Interrupt level bit 0 position. */ -#define AES_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */ -#define AES_INTLVL1_bp 1 /* Interrupt level bit 1 position. */ - - - -// Generic Port Pins - -#define PIN0_bm 0x01 -#define PIN0_bp 0 -#define PIN1_bm 0x02 -#define PIN1_bp 1 -#define PIN2_bm 0x04 -#define PIN2_bp 2 -#define PIN3_bm 0x08 -#define PIN3_bp 3 -#define PIN4_bm 0x10 -#define PIN4_bp 4 -#define PIN5_bm 0x20 -#define PIN5_bp 5 -#define PIN6_bm 0x40 -#define PIN6_bp 6 -#define PIN7_bm 0x80 -#define PIN7_bp 7 - - -/* ========== Interrupt Vector Definitions ========== */ -/* Vector 0 is the reset vector */ - -/* OSC interrupt vectors */ -#define OSC_XOSCF_vect_num 1 -#define OSC_XOSCF_vect _VECTOR(1) /* External Oscillator Failure Interrupt (NMI) */ - -/* PORTC interrupt vectors */ -#define PORTC_INT0_vect_num 2 -#define PORTC_INT0_vect _VECTOR(2) /* External Interrupt 0 */ -#define PORTC_INT1_vect_num 3 -#define PORTC_INT1_vect _VECTOR(3) /* External Interrupt 1 */ - -/* PORTR interrupt vectors */ -#define PORTR_INT0_vect_num 4 -#define PORTR_INT0_vect _VECTOR(4) /* External Interrupt 0 */ -#define PORTR_INT1_vect_num 5 -#define PORTR_INT1_vect _VECTOR(5) /* External Interrupt 1 */ - -/* DMA interrupt vectors */ -#define DMA_CH0_vect_num 6 -#define DMA_CH0_vect _VECTOR(6) /* Channel 0 Interrupt */ -#define DMA_CH1_vect_num 7 -#define DMA_CH1_vect _VECTOR(7) /* Channel 1 Interrupt */ -#define DMA_CH2_vect_num 8 -#define DMA_CH2_vect _VECTOR(8) /* Channel 2 Interrupt */ -#define DMA_CH3_vect_num 9 -#define DMA_CH3_vect _VECTOR(9) /* Channel 3 Interrupt */ - -/* RTC interrupt vectors */ -#define RTC_OVF_vect_num 10 -#define RTC_OVF_vect _VECTOR(10) /* Overflow Interrupt */ -#define RTC_COMP_vect_num 11 -#define RTC_COMP_vect _VECTOR(11) /* Compare Interrupt */ - -/* TWIC interrupt vectors */ -#define TWIC_TWIS_vect_num 12 -#define TWIC_TWIS_vect _VECTOR(12) /* TWI Slave Interrupt */ -#define TWIC_TWIM_vect_num 13 -#define TWIC_TWIM_vect _VECTOR(13) /* TWI Master Interrupt */ - -/* TCC0 interrupt vectors */ -#define TCC0_OVF_vect_num 14 -#define TCC0_OVF_vect _VECTOR(14) /* Overflow Interrupt */ -#define TCC0_ERR_vect_num 15 -#define TCC0_ERR_vect _VECTOR(15) /* Error Interrupt */ -#define TCC0_CCA_vect_num 16 -#define TCC0_CCA_vect _VECTOR(16) /* Compare or Capture A Interrupt */ -#define TCC0_CCB_vect_num 17 -#define TCC0_CCB_vect _VECTOR(17) /* Compare or Capture B Interrupt */ -#define TCC0_CCC_vect_num 18 -#define TCC0_CCC_vect _VECTOR(18) /* Compare or Capture C Interrupt */ -#define TCC0_CCD_vect_num 19 -#define TCC0_CCD_vect _VECTOR(19) /* Compare or Capture D Interrupt */ - -/* TCC1 interrupt vectors */ -#define TCC1_OVF_vect_num 20 -#define TCC1_OVF_vect _VECTOR(20) /* Overflow Interrupt */ -#define TCC1_ERR_vect_num 21 -#define TCC1_ERR_vect _VECTOR(21) /* Error Interrupt */ -#define TCC1_CCA_vect_num 22 -#define TCC1_CCA_vect _VECTOR(22) /* Compare or Capture A Interrupt */ -#define TCC1_CCB_vect_num 23 -#define TCC1_CCB_vect _VECTOR(23) /* Compare or Capture B Interrupt */ - -/* SPIC interrupt vectors */ -#define SPIC_INT_vect_num 24 -#define SPIC_INT_vect _VECTOR(24) /* SPI Interrupt */ - -/* USARTC0 interrupt vectors */ -#define USARTC0_RXC_vect_num 25 -#define USARTC0_RXC_vect _VECTOR(25) /* Reception Complete Interrupt */ -#define USARTC0_DRE_vect_num 26 -#define USARTC0_DRE_vect _VECTOR(26) /* Data Register Empty Interrupt */ -#define USARTC0_TXC_vect_num 27 -#define USARTC0_TXC_vect _VECTOR(27) /* Transmission Complete Interrupt */ - -/* USARTC1 interrupt vectors */ -#define USARTC1_RXC_vect_num 28 -#define USARTC1_RXC_vect _VECTOR(28) /* Reception Complete Interrupt */ -#define USARTC1_DRE_vect_num 29 -#define USARTC1_DRE_vect _VECTOR(29) /* Data Register Empty Interrupt */ -#define USARTC1_TXC_vect_num 30 -#define USARTC1_TXC_vect _VECTOR(30) /* Transmission Complete Interrupt */ - -/* AES interrupt vectors */ -#define AES_INT_vect_num 31 -#define AES_INT_vect _VECTOR(31) /* AES Interrupt */ - -/* NVM interrupt vectors */ -#define NVM_EE_vect_num 32 -#define NVM_EE_vect _VECTOR(32) /* EE Interrupt */ -#define NVM_SPM_vect_num 33 -#define NVM_SPM_vect _VECTOR(33) /* SPM Interrupt */ - -/* PORTB interrupt vectors */ -#define PORTB_INT0_vect_num 34 -#define PORTB_INT0_vect _VECTOR(34) /* External Interrupt 0 */ -#define PORTB_INT1_vect_num 35 -#define PORTB_INT1_vect _VECTOR(35) /* External Interrupt 1 */ - -/* ACB interrupt vectors */ -#define ACB_AC0_vect_num 36 -#define ACB_AC0_vect _VECTOR(36) /* AC0 Interrupt */ -#define ACB_AC1_vect_num 37 -#define ACB_AC1_vect _VECTOR(37) /* AC1 Interrupt */ -#define ACB_ACW_vect_num 38 -#define ACB_ACW_vect _VECTOR(38) /* ACW Window Mode Interrupt */ - -/* ADCB interrupt vectors */ -#define ADCB_CH0_vect_num 39 -#define ADCB_CH0_vect _VECTOR(39) /* Interrupt 0 */ -#define ADCB_CH1_vect_num 40 -#define ADCB_CH1_vect _VECTOR(40) /* Interrupt 1 */ -#define ADCB_CH2_vect_num 41 -#define ADCB_CH2_vect _VECTOR(41) /* Interrupt 2 */ -#define ADCB_CH3_vect_num 42 -#define ADCB_CH3_vect _VECTOR(42) /* Interrupt 3 */ - -/* PORTE interrupt vectors */ -#define PORTE_INT0_vect_num 43 -#define PORTE_INT0_vect _VECTOR(43) /* External Interrupt 0 */ -#define PORTE_INT1_vect_num 44 -#define PORTE_INT1_vect _VECTOR(44) /* External Interrupt 1 */ - -/* TWIE interrupt vectors */ -#define TWIE_TWIS_vect_num 45 -#define TWIE_TWIS_vect _VECTOR(45) /* TWI Slave Interrupt */ -#define TWIE_TWIM_vect_num 46 -#define TWIE_TWIM_vect _VECTOR(46) /* TWI Master Interrupt */ - -/* TCE0 interrupt vectors */ -#define TCE0_OVF_vect_num 47 -#define TCE0_OVF_vect _VECTOR(47) /* Overflow Interrupt */ -#define TCE0_ERR_vect_num 48 -#define TCE0_ERR_vect _VECTOR(48) /* Error Interrupt */ -#define TCE0_CCA_vect_num 49 -#define TCE0_CCA_vect _VECTOR(49) /* Compare or Capture A Interrupt */ -#define TCE0_CCB_vect_num 50 -#define TCE0_CCB_vect _VECTOR(50) /* Compare or Capture B Interrupt */ -#define TCE0_CCC_vect_num 51 -#define TCE0_CCC_vect _VECTOR(51) /* Compare or Capture C Interrupt */ -#define TCE0_CCD_vect_num 52 -#define TCE0_CCD_vect _VECTOR(52) /* Compare or Capture D Interrupt */ - -/* TCE1 interrupt vectors */ -#define TCE1_OVF_vect_num 53 -#define TCE1_OVF_vect _VECTOR(53) /* Overflow Interrupt */ -#define TCE1_ERR_vect_num 54 -#define TCE1_ERR_vect _VECTOR(54) /* Error Interrupt */ -#define TCE1_CCA_vect_num 55 -#define TCE1_CCA_vect _VECTOR(55) /* Compare or Capture A Interrupt */ -#define TCE1_CCB_vect_num 56 -#define TCE1_CCB_vect _VECTOR(56) /* Compare or Capture B Interrupt */ - -/* SPIE interrupt vectors */ -#define SPIE_INT_vect_num 57 -#define SPIE_INT_vect _VECTOR(57) /* SPI Interrupt */ - -/* USARTE0 interrupt vectors */ -#define USARTE0_RXC_vect_num 58 -#define USARTE0_RXC_vect _VECTOR(58) /* Reception Complete Interrupt */ -#define USARTE0_DRE_vect_num 59 -#define USARTE0_DRE_vect _VECTOR(59) /* Data Register Empty Interrupt */ -#define USARTE0_TXC_vect_num 60 -#define USARTE0_TXC_vect _VECTOR(60) /* Transmission Complete Interrupt */ - -/* USARTE1 interrupt vectors */ -#define USARTE1_RXC_vect_num 61 -#define USARTE1_RXC_vect _VECTOR(61) /* Reception Complete Interrupt */ -#define USARTE1_DRE_vect_num 62 -#define USARTE1_DRE_vect _VECTOR(62) /* Data Register Empty Interrupt */ -#define USARTE1_TXC_vect_num 63 -#define USARTE1_TXC_vect _VECTOR(63) /* Transmission Complete Interrupt */ - -/* PORTD interrupt vectors */ -#define PORTD_INT0_vect_num 64 -#define PORTD_INT0_vect _VECTOR(64) /* External Interrupt 0 */ -#define PORTD_INT1_vect_num 65 -#define PORTD_INT1_vect _VECTOR(65) /* External Interrupt 1 */ - -/* PORTA interrupt vectors */ -#define PORTA_INT0_vect_num 66 -#define PORTA_INT0_vect _VECTOR(66) /* External Interrupt 0 */ -#define PORTA_INT1_vect_num 67 -#define PORTA_INT1_vect _VECTOR(67) /* External Interrupt 1 */ - -/* ACA interrupt vectors */ -#define ACA_AC0_vect_num 68 -#define ACA_AC0_vect _VECTOR(68) /* AC0 Interrupt */ -#define ACA_AC1_vect_num 69 -#define ACA_AC1_vect _VECTOR(69) /* AC1 Interrupt */ -#define ACA_ACW_vect_num 70 -#define ACA_ACW_vect _VECTOR(70) /* ACW Window Mode Interrupt */ - -/* ADCA interrupt vectors */ -#define ADCA_CH0_vect_num 71 -#define ADCA_CH0_vect _VECTOR(71) /* Interrupt 0 */ -#define ADCA_CH1_vect_num 72 -#define ADCA_CH1_vect _VECTOR(72) /* Interrupt 1 */ -#define ADCA_CH2_vect_num 73 -#define ADCA_CH2_vect _VECTOR(73) /* Interrupt 2 */ -#define ADCA_CH3_vect_num 74 -#define ADCA_CH3_vect _VECTOR(74) /* Interrupt 3 */ - -/* TCD0 interrupt vectors */ -#define TCD0_OVF_vect_num 77 -#define TCD0_OVF_vect _VECTOR(77) /* Overflow Interrupt */ -#define TCD0_ERR_vect_num 78 -#define TCD0_ERR_vect _VECTOR(78) /* Error Interrupt */ -#define TCD0_CCA_vect_num 79 -#define TCD0_CCA_vect _VECTOR(79) /* Compare or Capture A Interrupt */ -#define TCD0_CCB_vect_num 80 -#define TCD0_CCB_vect _VECTOR(80) /* Compare or Capture B Interrupt */ -#define TCD0_CCC_vect_num 81 -#define TCD0_CCC_vect _VECTOR(81) /* Compare or Capture C Interrupt */ -#define TCD0_CCD_vect_num 82 -#define TCD0_CCD_vect _VECTOR(82) /* Compare or Capture D Interrupt */ - -/* TCD1 interrupt vectors */ -#define TCD1_OVF_vect_num 83 -#define TCD1_OVF_vect _VECTOR(83) /* Overflow Interrupt */ -#define TCD1_ERR_vect_num 84 -#define TCD1_ERR_vect _VECTOR(84) /* Error Interrupt */ -#define TCD1_CCA_vect_num 85 -#define TCD1_CCA_vect _VECTOR(85) /* Compare or Capture A Interrupt */ -#define TCD1_CCB_vect_num 86 -#define TCD1_CCB_vect _VECTOR(86) /* Compare or Capture B Interrupt */ - -/* SPID interrupt vectors */ -#define SPID_INT_vect_num 87 -#define SPID_INT_vect _VECTOR(87) /* SPI Interrupt */ - -/* USARTD0 interrupt vectors */ -#define USARTD0_RXC_vect_num 88 -#define USARTD0_RXC_vect _VECTOR(88) /* Reception Complete Interrupt */ -#define USARTD0_DRE_vect_num 89 -#define USARTD0_DRE_vect _VECTOR(89) /* Data Register Empty Interrupt */ -#define USARTD0_TXC_vect_num 90 -#define USARTD0_TXC_vect _VECTOR(90) /* Transmission Complete Interrupt */ - -/* USARTD1 interrupt vectors */ -#define USARTD1_RXC_vect_num 91 -#define USARTD1_RXC_vect _VECTOR(91) /* Reception Complete Interrupt */ -#define USARTD1_DRE_vect_num 92 -#define USARTD1_DRE_vect _VECTOR(92) /* Data Register Empty Interrupt */ -#define USARTD1_TXC_vect_num 93 -#define USARTD1_TXC_vect _VECTOR(93) /* Transmission Complete Interrupt */ - -/* PORTF interrupt vectors */ -#define PORTF_INT0_vect_num 104 -#define PORTF_INT0_vect _VECTOR(104) /* External Interrupt 0 */ -#define PORTF_INT1_vect_num 105 -#define PORTF_INT1_vect _VECTOR(105) /* External Interrupt 1 */ - -/* TCF0 interrupt vectors */ -#define TCF0_OVF_vect_num 108 -#define TCF0_OVF_vect _VECTOR(108) /* Overflow Interrupt */ -#define TCF0_ERR_vect_num 109 -#define TCF0_ERR_vect _VECTOR(109) /* Error Interrupt */ -#define TCF0_CCA_vect_num 110 -#define TCF0_CCA_vect _VECTOR(110) /* Compare or Capture A Interrupt */ -#define TCF0_CCB_vect_num 111 -#define TCF0_CCB_vect _VECTOR(111) /* Compare or Capture B Interrupt */ -#define TCF0_CCC_vect_num 112 -#define TCF0_CCC_vect _VECTOR(112) /* Compare or Capture C Interrupt */ -#define TCF0_CCD_vect_num 113 -#define TCF0_CCD_vect _VECTOR(113) /* Compare or Capture D Interrupt */ - -/* USARTF0 interrupt vectors */ -#define USARTF0_RXC_vect_num 119 -#define USARTF0_RXC_vect _VECTOR(119) /* Reception Complete Interrupt */ -#define USARTF0_DRE_vect_num 120 -#define USARTF0_DRE_vect _VECTOR(120) /* Data Register Empty Interrupt */ -#define USARTF0_TXC_vect_num 121 -#define USARTF0_TXC_vect _VECTOR(121) /* Transmission Complete Interrupt */ - - -#define _VECTOR_SIZE 4 /* Size of individual vector. */ -#define _VECTORS_SIZE (122 * _VECTOR_SIZE) - - -/* ========== Constants ========== */ - -#define PROGMEM_START (0x0000) -#define PROGMEM_SIZE (270336) -#define PROGMEM_PAGE_SIZE (512) -#define PROGMEM_END (PROGMEM_START + PROGMEM_SIZE - 1) - -#define APP_SECTION_START (0x0000) -#define APP_SECTION_SIZE (262144) -#define APP_SECTION_PAGE_SIZE (512) -#define APP_SECTION_END (APP_SECTION_START + APP_SECTION_SIZE - 1) - -#define APPTABLE_SECTION_START (0x3E000) -#define APPTABLE_SECTION_SIZE (8192) -#define APPTABLE_SECTION_PAGE_SIZE (512) -#define APPTABLE_SECTION_END (APPTABLE_SECTION_START + APPTABLE_SECTION_SIZE - 1) - -#define BOOT_SECTION_START (0x40000) -#define BOOT_SECTION_SIZE (8192) -#define BOOT_SECTION_PAGE_SIZE (512) -#define BOOT_SECTION_END (BOOT_SECTION_START + BOOT_SECTION_SIZE - 1) - -#define DATAMEM_START (0x0000) -#define DATAMEM_SIZE (24576) -#define DATAMEM_PAGE_SIZE (0) -#define DATAMEM_END (DATAMEM_START + DATAMEM_SIZE - 1) - -#define IO_START (0x0000) -#define IO_SIZE (4096) -#define IO_PAGE_SIZE (0) -#define IO_END (IO_START + IO_SIZE - 1) - -#define MAPPED_EEPROM_START (0x1000) -#define MAPPED_EEPROM_SIZE (4096) -#define MAPPED_EEPROM_PAGE_SIZE (0) -#define MAPPED_EEPROM_END (MAPPED_EEPROM_START + MAPPED_EEPROM_SIZE - 1) - -#define INTERNAL_SRAM_START (0x2000) -#define INTERNAL_SRAM_SIZE (16384) -#define INTERNAL_SRAM_PAGE_SIZE (0) -#define INTERNAL_SRAM_END (INTERNAL_SRAM_START + INTERNAL_SRAM_SIZE - 1) - -#define EEPROM_START (0x0000) -#define EEPROM_SIZE (4096) -#define EEPROM_PAGE_SIZE (32) -#define EEPROM_END (EEPROM_START + EEPROM_SIZE - 1) - -#define FUSE_START (0x0000) -#define FUSE_SIZE (6) -#define FUSE_PAGE_SIZE (0) -#define FUSE_END (FUSE_START + FUSE_SIZE - 1) - -#define LOCKBIT_START (0x0000) -#define LOCKBIT_SIZE (1) -#define LOCKBIT_PAGE_SIZE (0) -#define LOCKBIT_END (LOCKBIT_START + LOCKBIT_SIZE - 1) - -#define SIGNATURES_START (0x0000) -#define SIGNATURES_SIZE (3) -#define SIGNATURES_PAGE_SIZE (0) -#define SIGNATURES_END (SIGNATURES_START + SIGNATURES_SIZE - 1) - -#define USER_SIGNATURES_START (0x0000) -#define USER_SIGNATURES_SIZE (512) -#define USER_SIGNATURES_PAGE_SIZE (0) -#define USER_SIGNATURES_END (USER_SIGNATURES_START + USER_SIGNATURES_SIZE - 1) - -#define PROD_SIGNATURES_START (0x0000) -#define PROD_SIGNATURES_SIZE (52) -#define PROD_SIGNATURES_PAGE_SIZE (0) -#define PROD_SIGNATURES_END (PROD_SIGNATURES_START + PROD_SIGNATURES_SIZE - 1) - -#define FLASHEND PROGMEM_END -#define SPM_PAGESIZE PROGMEM_PAGE_SIZE -#define RAMSTART INTERNAL_SRAM_START -#define RAMSIZE INTERNAL_SRAM_SIZE -#define RAMEND INTERNAL_SRAM_END -#define XRAMSTART EXTERNAL_SRAM_START -#define XRAMSIZE EXTERNAL_SRAM_SIZE -#define XRAMEND INTERNAL_SRAM_END -#define E2END EEPROM_END -#define E2PAGESIZE EEPROM_PAGE_SIZE - - -/* ========== Fuses ========== */ -#define FUSE_MEMORY_SIZE 6 - -/* Fuse Byte 0 */ -#define FUSE_JTAGUSERID0 (unsigned char)~_BV(0) /* JTAG User ID Bit 0 */ -#define FUSE_JTAGUSERID1 (unsigned char)~_BV(1) /* JTAG User ID Bit 1 */ -#define FUSE_JTAGUSERID2 (unsigned char)~_BV(2) /* JTAG User ID Bit 2 */ -#define FUSE_JTAGUSERID3 (unsigned char)~_BV(3) /* JTAG User ID Bit 3 */ -#define FUSE_JTAGUSERID4 (unsigned char)~_BV(4) /* JTAG User ID Bit 4 */ -#define FUSE_JTAGUSERID5 (unsigned char)~_BV(5) /* JTAG User ID Bit 5 */ -#define FUSE_JTAGUSERID6 (unsigned char)~_BV(6) /* JTAG User ID Bit 6 */ -#define FUSE_JTAGUSERID7 (unsigned char)~_BV(7) /* JTAG User ID Bit 7 */ -#define FUSE0_DEFAULT (0xFF) - -/* Fuse Byte 1 */ -#define FUSE_WDP0 (unsigned char)~_BV(0) /* Watchdog Timeout Period Bit 0 */ -#define FUSE_WDP1 (unsigned char)~_BV(1) /* Watchdog Timeout Period Bit 1 */ -#define FUSE_WDP2 (unsigned char)~_BV(2) /* Watchdog Timeout Period Bit 2 */ -#define FUSE_WDP3 (unsigned char)~_BV(3) /* Watchdog Timeout Period Bit 3 */ -#define FUSE_WDWP0 (unsigned char)~_BV(4) /* Watchdog Window Timeout Period Bit 0 */ -#define FUSE_WDWP1 (unsigned char)~_BV(5) /* Watchdog Window Timeout Period Bit 1 */ -#define FUSE_WDWP2 (unsigned char)~_BV(6) /* Watchdog Window Timeout Period Bit 2 */ -#define FUSE_WDWP3 (unsigned char)~_BV(7) /* Watchdog Window Timeout Period Bit 3 */ -#define FUSE1_DEFAULT (0xFF) - -/* Fuse Byte 2 */ -#define FUSE_BODPD0 (unsigned char)~_BV(0) /* BOD Operation in Power-Down Mode Bit 0 */ -#define FUSE_BODPD1 (unsigned char)~_BV(1) /* BOD Operation in Power-Down Mode Bit 1 */ -#define FUSE_BOOTRST (unsigned char)~_BV(6) /* Boot Loader Section Reset Vector */ -#define FUSE_DVSDON (unsigned char)~_BV(7) /* Spike Detector Enable */ -#define FUSE2_DEFAULT (0xFF) - -/* Fuse Byte 3 Reserved */ - -/* Fuse Byte 4 */ -#define FUSE_JTAGEN (unsigned char)~_BV(0) /* JTAG Interface Enable */ -#define FUSE_WDLOCK (unsigned char)~_BV(1) /* Watchdog Timer Lock */ -#define FUSE_SUT0 (unsigned char)~_BV(2) /* Start-up Time Bit 0 */ -#define FUSE_SUT1 (unsigned char)~_BV(3) /* Start-up Time Bit 1 */ -#define FUSE4_DEFAULT (0xFF) - -/* Fuse Byte 5 */ -#define FUSE_BODLVL0 (unsigned char)~_BV(0) /* Brown Out Detection Voltage Level Bit 0 */ -#define FUSE_BODLVL1 (unsigned char)~_BV(1) /* Brown Out Detection Voltage Level Bit 1 */ -#define FUSE_BODLVL2 (unsigned char)~_BV(2) /* Brown Out Detection Voltage Level Bit 2 */ -#define FUSE_EESAVE (unsigned char)~_BV(3) /* Preserve EEPROM Through Chip Erase */ -#define FUSE_BODACT0 (unsigned char)~_BV(4) /* BOD Operation in Active Mode Bit 0 */ -#define FUSE_BODACT1 (unsigned char)~_BV(5) /* BOD Operation in Active Mode Bit 1 */ -#define FUSE5_DEFAULT (0xFF) - - -/* ========== Lock Bits ========== */ -#define __LOCK_BITS_EXIST -#define __BOOT_LOCK_APPLICATION_TABLE_BITS_EXIST -#define __BOOT_LOCK_APPLICATION_BITS_EXIST -#define __BOOT_LOCK_BOOT_BITS_EXIST - - -/* ========== Signature ========== */ -#define SIGNATURE_0 0x1E -#define SIGNATURE_1 0x98 -#define SIGNATURE_2 0x42 - -/* ========== Power Reduction Condition Definitions ========== */ - -/* PR.PRGEN */ -#define __AVR_HAVE_PRGEN (PR_AES_bm|PR_EBI_bm|PR_RTC_bm|PR_EVSYS_bm|PR_DMA_bm) -#define __AVR_HAVE_PRGEN_AES -#define __AVR_HAVE_PRGEN_EBI -#define __AVR_HAVE_PRGEN_RTC -#define __AVR_HAVE_PRGEN_EVSYS -#define __AVR_HAVE_PRGEN_DMA - -/* PR.PRPA */ -#define __AVR_HAVE_PRPA (PR_DAC_bm|PR_ADC_bm|PR_AC_bm) -#define __AVR_HAVE_PRPA_DAC -#define __AVR_HAVE_PRPA_ADC -#define __AVR_HAVE_PRPA_AC - -/* PR.PRPB */ -#define __AVR_HAVE_PRPB (PR_DAC_bm|PR_ADC_bm|PR_AC_bm) -#define __AVR_HAVE_PRPB_DAC -#define __AVR_HAVE_PRPB_ADC -#define __AVR_HAVE_PRPB_AC - -/* PR.PRPC */ -#define __AVR_HAVE_PRPC (PR_TWI_bm|PR_USART1_bm|PR_USART0_bm|PR_SPI_bm|PR_HIRES_bm|PR_TC1_bm|PR_TC0_bm) -#define __AVR_HAVE_PRPC_TWI -#define __AVR_HAVE_PRPC_USART1 -#define __AVR_HAVE_PRPC_USART0 -#define __AVR_HAVE_PRPC_SPI -#define __AVR_HAVE_PRPC_HIRES -#define __AVR_HAVE_PRPC_TC1 -#define __AVR_HAVE_PRPC_TC0 - -/* PR.PRPD */ -#define __AVR_HAVE_PRPD (PR_TWI_bm|PR_USART1_bm|PR_USART0_bm|PR_SPI_bm|PR_HIRES_bm|PR_TC1_bm|PR_TC0_bm) -#define __AVR_HAVE_PRPD_TWI -#define __AVR_HAVE_PRPD_USART1 -#define __AVR_HAVE_PRPD_USART0 -#define __AVR_HAVE_PRPD_SPI -#define __AVR_HAVE_PRPD_HIRES -#define __AVR_HAVE_PRPD_TC1 -#define __AVR_HAVE_PRPD_TC0 - -/* PR.PRPE */ -#define __AVR_HAVE_PRPE (PR_TWI_bm|PR_USART1_bm|PR_USART0_bm|PR_SPI_bm|PR_HIRES_bm|PR_TC1_bm|PR_TC0_bm) -#define __AVR_HAVE_PRPE_TWI -#define __AVR_HAVE_PRPE_USART1 -#define __AVR_HAVE_PRPE_USART0 -#define __AVR_HAVE_PRPE_SPI -#define __AVR_HAVE_PRPE_HIRES -#define __AVR_HAVE_PRPE_TC1 -#define __AVR_HAVE_PRPE_TC0 - -/* PR.PRPF */ -#define __AVR_HAVE_PRPF (PR_TWI_bm|PR_USART1_bm|PR_USART0_bm|PR_SPI_bm|PR_HIRES_bm|PR_TC1_bm|PR_TC0_bm) -#define __AVR_HAVE_PRPF_TWI -#define __AVR_HAVE_PRPF_USART1 -#define __AVR_HAVE_PRPF_USART0 -#define __AVR_HAVE_PRPF_SPI -#define __AVR_HAVE_PRPF_HIRES -#define __AVR_HAVE_PRPF_TC1 -#define __AVR_HAVE_PRPF_TC0 - - -#endif /* _AVR_ATxmega256A3_H_ */ - diff --git a/arduino/hardware/tools/avr/avr/include/avr/iox256a3b.h b/arduino/hardware/tools/avr/avr/include/avr/iox256a3b.h deleted file mode 100644 index f5a917e..0000000 --- a/arduino/hardware/tools/avr/avr/include/avr/iox256a3b.h +++ /dev/null @@ -1,6983 +0,0 @@ -/* Copyright (c) 2009-2010 Atmel Corporation - All rights reserved. - - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - * Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - * Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in - the documentation and/or other materials provided with the - distribution. - - * Neither the name of the copyright holders nor the names of - contributors may be used to endorse or promote products derived - from this software without specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. */ - -/* $Id: iox256a3b.h 2200 2010-12-14 04:24:24Z arcanum $ */ - -/* avr/iox256a3b.h - definitions for ATxmega256A3B */ - -/* This file should only be included from , never directly. */ - -#ifndef _AVR_IO_H_ -# error "Include instead of this file." -#endif - -#ifndef _AVR_IOXXX_H_ -# define _AVR_IOXXX_H_ "iox256a3b.h" -#else -# error "Attempt to include more than one file." -#endif - - -#ifndef _AVR_ATxmega256A3B_H_ -#define _AVR_ATxmega256A3B_H_ 1 - - -/* Ungrouped common registers */ -#define GPIOR0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ -#define GPIOR1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ -#define GPIOR2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ -#define GPIOR3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ -#define GPIOR4 _SFR_MEM8(0x0004) /* General Purpose IO Register 4 */ -#define GPIOR5 _SFR_MEM8(0x0005) /* General Purpose IO Register 5 */ -#define GPIOR6 _SFR_MEM8(0x0006) /* General Purpose IO Register 6 */ -#define GPIOR7 _SFR_MEM8(0x0007) /* General Purpose IO Register 7 */ -#define GPIOR8 _SFR_MEM8(0x0008) /* General Purpose IO Register 8 */ -#define GPIOR9 _SFR_MEM8(0x0009) /* General Purpose IO Register 9 */ -#define GPIORA _SFR_MEM8(0x000A) /* General Purpose IO Register 10 */ -#define GPIORB _SFR_MEM8(0x000B) /* General Purpose IO Register 11 */ -#define GPIORC _SFR_MEM8(0x000C) /* General Purpose IO Register 12 */ -#define GPIORD _SFR_MEM8(0x000D) /* General Purpose IO Register 13 */ -#define GPIORE _SFR_MEM8(0x000E) /* General Purpose IO Register 14 */ -#define GPIORF _SFR_MEM8(0x000F) /* General Purpose IO Register 15 */ - -/* Deprecated*/ -#define GPIO0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ -#define GPIO1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ -#define GPIO2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ -#define GPIO3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ -#define GPIO4 _SFR_MEM8(0x0004) /* General Purpose IO Register 4 */ -#define GPIO5 _SFR_MEM8(0x0005) /* General Purpose IO Register 5 */ -#define GPIO6 _SFR_MEM8(0x0006) /* General Purpose IO Register 6 */ -#define GPIO7 _SFR_MEM8(0x0007) /* General Purpose IO Register 7 */ -#define GPIO8 _SFR_MEM8(0x0008) /* General Purpose IO Register 8 */ -#define GPIO9 _SFR_MEM8(0x0009) /* General Purpose IO Register 9 */ -#define GPIOA _SFR_MEM8(0x000A) /* General Purpose IO Register 10 */ -#define GPIOB _SFR_MEM8(0x000B) /* General Purpose IO Register 11 */ -#define GPIOC _SFR_MEM8(0x000C) /* General Purpose IO Register 12 */ -#define GPIOD _SFR_MEM8(0x000D) /* General Purpose IO Register 13 */ -#define GPIOE _SFR_MEM8(0x000E) /* General Purpose IO Register 14 */ -#define GPIOF _SFR_MEM8(0x000F) /* General Purpose IO Register 15 */ - - -#define CCP _SFR_MEM8(0x0034) /* Configuration Change Protection */ -#define RAMPD _SFR_MEM8(0x0038) /* Ramp D */ -#define RAMPX _SFR_MEM8(0x0039) /* Ramp X */ -#define RAMPY _SFR_MEM8(0x003A) /* Ramp Y */ -#define RAMPZ _SFR_MEM8(0x003B) /* Ramp Z */ -#define EIND _SFR_MEM8(0x003C) /* Extended Indirect Jump */ -#define SPL _SFR_MEM8(0x003D) /* Stack Pointer Low */ -#define SPH _SFR_MEM8(0x003E) /* Stack Pointer High */ -#define SREG _SFR_MEM8(0x003F) /* Status Register */ - - -/* C Language Only */ -#if !defined (__ASSEMBLER__) - -#include - -typedef volatile uint8_t register8_t; -typedef volatile uint16_t register16_t; -typedef volatile uint32_t register32_t; - - -#ifdef _WORDREGISTER -#undef _WORDREGISTER -#endif -#define _WORDREGISTER(regname) \ - __extension__ union \ - { \ - register16_t regname; \ - struct \ - { \ - register8_t regname ## L; \ - register8_t regname ## H; \ - }; \ - } - -#ifdef _DWORDREGISTER -#undef _DWORDREGISTER -#endif -#define _DWORDREGISTER(regname) \ - __extension__ union \ - { \ - register32_t regname; \ - struct \ - { \ - register8_t regname ## 0; \ - register8_t regname ## 1; \ - register8_t regname ## 2; \ - register8_t regname ## 3; \ - }; \ - } - - -/* -========================================================================== -IO Module Structures -========================================================================== -*/ - - -/* --------------------------------------------------------------------------- -XOCD - On-Chip Debug System --------------------------------------------------------------------------- -*/ - -/* On-Chip Debug System */ -typedef struct OCD_struct -{ - register8_t OCDR0; /* OCD Register 0 */ - register8_t OCDR1; /* OCD Register 1 */ -} OCD_t; - - -/* CCP signatures */ -typedef enum CCP_enum -{ - CCP_SPM_gc = (0x9D<<0), /* SPM Instruction Protection */ - CCP_IOREG_gc = (0xD8<<0), /* IO Register Protection */ -} CCP_t; - - -/* --------------------------------------------------------------------------- -CLK - Clock System --------------------------------------------------------------------------- -*/ - -/* Clock System */ -typedef struct CLK_struct -{ - register8_t CTRL; /* Control Register */ - register8_t PSCTRL; /* Prescaler Control Register */ - register8_t LOCK; /* Lock register */ - register8_t RTCCTRL; /* RTC Control Register */ -} CLK_t; - -/* --------------------------------------------------------------------------- -CLK - Clock System --------------------------------------------------------------------------- -*/ - -/* Power Reduction */ -typedef struct PR_struct -{ - register8_t PRGEN; /* General Power Reduction */ - register8_t PRPA; /* Power Reduction Port A */ - register8_t PRPB; /* Power Reduction Port B */ - register8_t PRPC; /* Power Reduction Port C */ - register8_t PRPD; /* Power Reduction Port D */ - register8_t PRPE; /* Power Reduction Port E */ - register8_t PRPF; /* Power Reduction Port F */ -} PR_t; - -/* System Clock Selection */ -typedef enum CLK_SCLKSEL_enum -{ - CLK_SCLKSEL_RC2M_gc = (0x00<<0), /* Internal 2MHz RC Oscillator */ - CLK_SCLKSEL_RC32M_gc = (0x01<<0), /* Internal 32MHz RC Oscillator */ - CLK_SCLKSEL_RC32K_gc = (0x02<<0), /* Internal 32kHz RC Oscillator */ - CLK_SCLKSEL_XOSC_gc = (0x03<<0), /* External Crystal Oscillator or Clock */ - CLK_SCLKSEL_PLL_gc = (0x04<<0), /* Phase Locked Loop */ -} CLK_SCLKSEL_t; - -/* Prescaler A Division Factor */ -typedef enum CLK_PSADIV_enum -{ - CLK_PSADIV_1_gc = (0x00<<2), /* Divide by 1 */ - CLK_PSADIV_2_gc = (0x01<<2), /* Divide by 2 */ - CLK_PSADIV_4_gc = (0x03<<2), /* Divide by 4 */ - CLK_PSADIV_8_gc = (0x05<<2), /* Divide by 8 */ - CLK_PSADIV_16_gc = (0x07<<2), /* Divide by 16 */ - CLK_PSADIV_32_gc = (0x09<<2), /* Divide by 32 */ - CLK_PSADIV_64_gc = (0x0B<<2), /* Divide by 64 */ - CLK_PSADIV_128_gc = (0x0D<<2), /* Divide by 128 */ - CLK_PSADIV_256_gc = (0x0F<<2), /* Divide by 256 */ - CLK_PSADIV_512_gc = (0x11<<2), /* Divide by 512 */ -} CLK_PSADIV_t; - -/* Prescaler B and C Division Factor */ -typedef enum CLK_PSBCDIV_enum -{ - CLK_PSBCDIV_1_1_gc = (0x00<<0), /* Divide B by 1 and C by 1 */ - CLK_PSBCDIV_1_2_gc = (0x01<<0), /* Divide B by 1 and C by 2 */ - CLK_PSBCDIV_4_1_gc = (0x02<<0), /* Divide B by 4 and C by 1 */ - CLK_PSBCDIV_2_2_gc = (0x03<<0), /* Divide B by 2 and C by 2 */ -} CLK_PSBCDIV_t; - -/* RTC Clock Source */ -typedef enum CLK_RTCSRC_enum -{ - CLK_RTCSRC_ULP_gc = (0x00<<1), /* 1kHz from internal 32kHz ULP */ - CLK_RTCSRC_TOSC_gc = (0x01<<1), /* 1kHz from 32kHz crystal oscillator on TOSC */ - CLK_RTCSRC_RCOSC_gc = (0x02<<1), /* 1kHz from internal 32kHz RC oscillator */ - CLK_RTCSRC_TOSC32_gc = (0x05<<1), /* 32kHz from 32kHz crystal oscillator on TOSC */ -} CLK_RTCSRC_t; - - -/* --------------------------------------------------------------------------- -SLEEP - Sleep Controller --------------------------------------------------------------------------- -*/ - -/* Sleep Controller */ -typedef struct SLEEP_struct -{ - register8_t CTRL; /* Control Register */ -} SLEEP_t; - -/* Sleep Mode */ -typedef enum SLEEP_SMODE_enum -{ - SLEEP_SMODE_IDLE_gc = (0x00<<1), /* Idle mode */ - SLEEP_SMODE_PDOWN_gc = (0x02<<1), /* Power-down Mode */ - SLEEP_SMODE_PSAVE_gc = (0x03<<1), /* Power-save Mode */ - SLEEP_SMODE_STDBY_gc = (0x06<<1), /* Standby Mode */ - SLEEP_SMODE_ESTDBY_gc = (0x07<<1), /* Extended Standby Mode */ -} SLEEP_SMODE_t; - - -#define SLEEP_MODE_IDLE (0x00<<1) -#define SLEEP_MODE_PWR_DOWN (0x02<<1) -#define SLEEP_MODE_PWR_SAVE (0x03<<1) -#define SLEEP_MODE_STANDBY (0x06<<1) -#define SLEEP_MODE_EXT_STANDBY (0x07<<1) - -/* --------------------------------------------------------------------------- -OSC - Oscillator --------------------------------------------------------------------------- -*/ - -/* Oscillator */ -typedef struct OSC_struct -{ - register8_t CTRL; /* Control Register */ - register8_t STATUS; /* Status Register */ - register8_t XOSCCTRL; /* External Oscillator Control Register */ - register8_t XOSCFAIL; /* External Oscillator Failure Detection Register */ - register8_t RC32KCAL; /* 32kHz Internal Oscillator Calibration Register */ - register8_t PLLCTRL; /* PLL Control REgister */ - register8_t DFLLCTRL; /* DFLL Control Register */ -} OSC_t; - -/* Oscillator Frequency Range */ -typedef enum OSC_FRQRANGE_enum -{ - OSC_FRQRANGE_04TO2_gc = (0x00<<6), /* 0.4 - 2 MHz */ - OSC_FRQRANGE_2TO9_gc = (0x01<<6), /* 2 - 9 MHz */ - OSC_FRQRANGE_9TO12_gc = (0x02<<6), /* 9 - 12 MHz */ - OSC_FRQRANGE_12TO16_gc = (0x03<<6), /* 12 - 16 MHz */ -} OSC_FRQRANGE_t; - -/* External Oscillator Selection and Startup Time */ -typedef enum OSC_XOSCSEL_enum -{ - OSC_XOSCSEL_EXTCLK_gc = (0x00<<0), /* External Clock - 6 CLK */ - OSC_XOSCSEL_32KHz_gc = (0x02<<0), /* 32kHz TOSC - 32K CLK */ - OSC_XOSCSEL_XTAL_256CLK_gc = (0x03<<0), /* 0.4-16MHz XTAL - 256 CLK */ - OSC_XOSCSEL_XTAL_1KCLK_gc = (0x07<<0), /* 0.4-16MHz XTAL - 1K CLK */ - OSC_XOSCSEL_XTAL_16KCLK_gc = (0x0B<<0), /* 0.4-16MHz XTAL - 16K CLK */ -} OSC_XOSCSEL_t; - -/* PLL Clock Source */ -typedef enum OSC_PLLSRC_enum -{ - OSC_PLLSRC_RC2M_gc = (0x00<<6), /* Internal 2MHz RC Oscillator */ - OSC_PLLSRC_RC32M_gc = (0x02<<6), /* Internal 32MHz RC Oscillator */ - OSC_PLLSRC_XOSC_gc = (0x03<<6), /* External Oscillator */ -} OSC_PLLSRC_t; - - -/* --------------------------------------------------------------------------- -DFLL - DFLL --------------------------------------------------------------------------- -*/ - -/* DFLL */ -typedef struct DFLL_struct -{ - register8_t CTRL; /* Control Register */ - register8_t reserved_0x01; - register8_t CALA; /* Calibration Register A */ - register8_t CALB; /* Calibration Register B */ - register8_t COMP0; /* Oscillator Compare Register 0 */ - register8_t COMP1; /* Oscillator Compare Register 1 */ - register8_t COMP2; /* Oscillator Compare Register 2 */ - register8_t reserved_0x07; -} DFLL_t; - - -/* --------------------------------------------------------------------------- -RST - Reset --------------------------------------------------------------------------- -*/ - -/* Reset */ -typedef struct RST_struct -{ - register8_t STATUS; /* Status Register */ - register8_t CTRL; /* Control Register */ -} RST_t; - - -/* --------------------------------------------------------------------------- -WDT - Watch-Dog Timer --------------------------------------------------------------------------- -*/ - -/* Watch-Dog Timer */ -typedef struct WDT_struct -{ - register8_t CTRL; /* Control */ - register8_t WINCTRL; /* Windowed Mode Control */ - register8_t STATUS; /* Status */ -} WDT_t; - -/* Period setting */ -typedef enum WDT_PER_enum -{ - WDT_PER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ - WDT_PER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ - WDT_PER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ - WDT_PER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ - WDT_PER_128CLK_gc = (0x04<<2), /* 128 cycles (0.125s @ 3.3V) */ - WDT_PER_256CLK_gc = (0x05<<2), /* 256 cycles (0.25s @ 3.3V) */ - WDT_PER_512CLK_gc = (0x06<<2), /* 512 cycles (0.5s @ 3.3V) */ - WDT_PER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ - WDT_PER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ - WDT_PER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ - WDT_PER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ -} WDT_PER_t; - -/* Closed window period */ -typedef enum WDT_WPER_enum -{ - WDT_WPER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ - WDT_WPER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ - WDT_WPER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ - WDT_WPER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ - WDT_WPER_128CLK_gc = (0x04<<2), /* 128 cycles (0.125s @ 3.3V) */ - WDT_WPER_256CLK_gc = (0x05<<2), /* 256 cycles (0.25s @ 3.3V) */ - WDT_WPER_512CLK_gc = (0x06<<2), /* 512 cycles (0.5s @ 3.3V) */ - WDT_WPER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ - WDT_WPER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ - WDT_WPER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ - WDT_WPER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ -} WDT_WPER_t; - - -/* --------------------------------------------------------------------------- -MCU - MCU Control --------------------------------------------------------------------------- -*/ - -/* MCU Control */ -typedef struct MCU_struct -{ - register8_t DEVID0; /* Device ID byte 0 */ - register8_t DEVID1; /* Device ID byte 1 */ - register8_t DEVID2; /* Device ID byte 2 */ - register8_t REVID; /* Revision ID */ - register8_t JTAGUID; /* JTAG User ID */ - register8_t reserved_0x05; - register8_t MCUCR; /* MCU Control */ - register8_t reserved_0x07; - register8_t EVSYSLOCK; /* Event System Lock */ - register8_t AWEXLOCK; /* AWEX Lock */ - register8_t reserved_0x0A; - register8_t reserved_0x0B; -} MCU_t; - - -/* --------------------------------------------------------------------------- -PMIC - Programmable Multi-level Interrupt Controller --------------------------------------------------------------------------- -*/ - -/* Programmable Multi-level Interrupt Controller */ -typedef struct PMIC_struct -{ - register8_t STATUS; /* Status Register */ - register8_t INTPRI; /* Interrupt Priority */ - register8_t CTRL; /* Control Register */ -} PMIC_t; - - -/* --------------------------------------------------------------------------- -DMA - DMA Controller --------------------------------------------------------------------------- -*/ - -/* DMA Channel */ -typedef struct DMA_CH_struct -{ - register8_t CTRLA; /* Channel Control */ - register8_t CTRLB; /* Channel Control */ - register8_t ADDRCTRL; /* Address Control */ - register8_t TRIGSRC; /* Channel Trigger Source */ - _WORDREGISTER(TRFCNT); /* Channel Block Transfer Count */ - register8_t REPCNT; /* Channel Repeat Count */ - register8_t reserved_0x07; - register8_t SRCADDR0; /* Channel Source Address 0 */ - register8_t SRCADDR1; /* Channel Source Address 1 */ - register8_t SRCADDR2; /* Channel Source Address 2 */ - register8_t reserved_0x0B; - register8_t DESTADDR0; /* Channel Destination Address 0 */ - register8_t DESTADDR1; /* Channel Destination Address 1 */ - register8_t DESTADDR2; /* Channel Destination Address 2 */ - register8_t reserved_0x0F; -} DMA_CH_t; - -/* --------------------------------------------------------------------------- -DMA - DMA Controller --------------------------------------------------------------------------- -*/ - -/* DMA Controller */ -typedef struct DMA_struct -{ - register8_t CTRL; /* Control */ - register8_t reserved_0x01; - register8_t reserved_0x02; - register8_t INTFLAGS; /* Transfer Interrupt Status */ - register8_t STATUS; /* Status */ - register8_t reserved_0x05; - _WORDREGISTER(TEMP); /* Temporary Register For 16/24-bit Access */ - register8_t reserved_0x08; - register8_t reserved_0x09; - register8_t reserved_0x0A; - register8_t reserved_0x0B; - register8_t reserved_0x0C; - register8_t reserved_0x0D; - register8_t reserved_0x0E; - register8_t reserved_0x0F; - DMA_CH_t CH0; /* DMA Channel 0 */ - DMA_CH_t CH1; /* DMA Channel 1 */ - DMA_CH_t CH2; /* DMA Channel 2 */ - DMA_CH_t CH3; /* DMA Channel 3 */ -} DMA_t; - -/* Burst mode */ -typedef enum DMA_CH_BURSTLEN_enum -{ - DMA_CH_BURSTLEN_1BYTE_gc = (0x00<<0), /* 1-byte burst mode */ - DMA_CH_BURSTLEN_2BYTE_gc = (0x01<<0), /* 2-byte burst mode */ - DMA_CH_BURSTLEN_4BYTE_gc = (0x02<<0), /* 4-byte burst mode */ - DMA_CH_BURSTLEN_8BYTE_gc = (0x03<<0), /* 8-byte burst mode */ -} DMA_CH_BURSTLEN_t; - -/* Source address reload mode */ -typedef enum DMA_CH_SRCRELOAD_enum -{ - DMA_CH_SRCRELOAD_NONE_gc = (0x00<<6), /* No reload */ - DMA_CH_SRCRELOAD_BLOCK_gc = (0x01<<6), /* Reload at end of block */ - DMA_CH_SRCRELOAD_BURST_gc = (0x02<<6), /* Reload at end of burst */ - DMA_CH_SRCRELOAD_TRANSACTION_gc = (0x03<<6), /* Reload at end of transaction */ -} DMA_CH_SRCRELOAD_t; - -/* Source addressing mode */ -typedef enum DMA_CH_SRCDIR_enum -{ - DMA_CH_SRCDIR_FIXED_gc = (0x00<<4), /* Fixed */ - DMA_CH_SRCDIR_INC_gc = (0x01<<4), /* Increment */ - DMA_CH_SRCDIR_DEC_gc = (0x02<<4), /* Decrement */ -} DMA_CH_SRCDIR_t; - -/* Destination adress reload mode */ -typedef enum DMA_CH_DESTRELOAD_enum -{ - DMA_CH_DESTRELOAD_NONE_gc = (0x00<<2), /* No reload */ - DMA_CH_DESTRELOAD_BLOCK_gc = (0x01<<2), /* Reload at end of block */ - DMA_CH_DESTRELOAD_BURST_gc = (0x02<<2), /* Reload at end of burst */ - DMA_CH_DESTRELOAD_TRANSACTION_gc = (0x03<<2), /* Reload at end of transaction */ -} DMA_CH_DESTRELOAD_t; - -/* Destination adressing mode */ -typedef enum DMA_CH_DESTDIR_enum -{ - DMA_CH_DESTDIR_FIXED_gc = (0x00<<0), /* Fixed */ - DMA_CH_DESTDIR_INC_gc = (0x01<<0), /* Increment */ - DMA_CH_DESTDIR_DEC_gc = (0x02<<0), /* Decrement */ -} DMA_CH_DESTDIR_t; - -/* Transfer trigger source */ -typedef enum DMA_CH_TRIGSRC_enum -{ - DMA_CH_TRIGSRC_OFF_gc = (0x00<<0), /* Off software triggers only */ - DMA_CH_TRIGSRC_EVSYS_CH0_gc = (0x01<<0), /* Event System Channel 0 */ - DMA_CH_TRIGSRC_EVSYS_CH1_gc = (0x02<<0), /* Event System Channel 1 */ - DMA_CH_TRIGSRC_EVSYS_CH2_gc = (0x03<<0), /* Event System Channel 2 */ - DMA_CH_TRIGSRC_ADCA_CH0_gc = (0x10<<0), /* ADCA Channel 0 */ - DMA_CH_TRIGSRC_ADCA_CH1_gc = (0x11<<0), /* ADCA Channel 1 */ - DMA_CH_TRIGSRC_ADCA_CH2_gc = (0x12<<0), /* ADCA Channel 2 */ - DMA_CH_TRIGSRC_ADCA_CH3_gc = (0x13<<0), /* ADCA Channel 3 */ - DMA_CH_TRIGSRC_ADCA_CH4_gc = (0x14<<0), /* ADCA Channel 0,1,2,3 combined */ - DMA_CH_TRIGSRC_DACA_CH0_gc = (0x15<<0), /* DACA Channel 0 */ - DMA_CH_TRIGSRC_DACA_CH1_gc = (0x16<<0), /* DACA Channel 1 */ - DMA_CH_TRIGSRC_ADCB_CH0_gc = (0x20<<0), /* ADCB Channel 0 */ - DMA_CH_TRIGSRC_ADCB_CH1_gc = (0x21<<0), /* ADCB Channel 1 */ - DMA_CH_TRIGSRC_ADCB_CH2_gc = (0x22<<0), /* ADCB Channel 2 */ - DMA_CH_TRIGSRC_ADCB_CH3_gc = (0x23<<0), /* ADCB Channel 3 */ - DMA_CH_TRIGSRC_ADCB_CH4_gc = (0x24<<0), /* ADCB Channel 0,1,2,3 combined */ - DMA_CH_TRIGSRC_DACB_CH0_gc = (0x25<<0), /* DACB Channel 0 */ - DMA_CH_TRIGSRC_DACB_CH1_gc = (0x26<<0), /* DACB Channel 1 */ - DMA_CH_TRIGSRC_TCC0_OVF_gc = (0x40<<0), /* Timer/Counter C0 Overflow */ - DMA_CH_TRIGSRC_TCC0_ERR_gc = (0x41<<0), /* Timer/Counter C0 Error */ - DMA_CH_TRIGSRC_TCC0_CCA_gc = (0x42<<0), /* Timer/Counter C0 Compare or Capture A */ - DMA_CH_TRIGSRC_TCC0_CCB_gc = (0x43<<0), /* Timer/Counter C0 Compare or Capture B */ - DMA_CH_TRIGSRC_TCC0_CCC_gc = (0x44<<0), /* Timer/Counter C0 Compare or Capture C */ - DMA_CH_TRIGSRC_TCC0_CCD_gc = (0x45<<0), /* Timer/Counter C0 Compare or Capture D */ - DMA_CH_TRIGSRC_TCC1_OVF_gc = (0x46<<0), /* Timer/Counter C1 Overflow */ - DMA_CH_TRIGSRC_TCC1_ERR_gc = (0x47<<0), /* Timer/Counter C1 Error */ - DMA_CH_TRIGSRC_TCC1_CCA_gc = (0x48<<0), /* Timer/Counter C1 Compare or Capture A */ - DMA_CH_TRIGSRC_TCC1_CCB_gc = (0x49<<0), /* Timer/Counter C1 Compare or Capture B */ - DMA_CH_TRIGSRC_SPIC_gc = (0x4A<<0), /* SPI C Transfer Complete */ - DMA_CH_TRIGSRC_USARTC0_RXC_gc = (0x4B<<0), /* USART C0 Receive Complete */ - DMA_CH_TRIGSRC_USARTC0_DRE_gc = (0x4C<<0), /* USART C0 Data Register Empty */ - DMA_CH_TRIGSRC_USARTC1_RXC_gc = (0x4E<<0), /* USART C1 Receive Complete */ - DMA_CH_TRIGSRC_USARTC1_DRE_gc = (0x4F<<0), /* USART C1 Data Register Empty */ - DMA_CH_TRIGSRC_TCD0_OVF_gc = (0x60<<0), /* Timer/Counter D0 Overflow */ - DMA_CH_TRIGSRC_TCD0_ERR_gc = (0x61<<0), /* Timer/Counter D0 Error */ - DMA_CH_TRIGSRC_TCD0_CCA_gc = (0x62<<0), /* Timer/Counter D0 Compare or Capture A */ - DMA_CH_TRIGSRC_TCD0_CCB_gc = (0x63<<0), /* Timer/Counter D0 Compare or Capture B */ - DMA_CH_TRIGSRC_TCD0_CCC_gc = (0x64<<0), /* Timer/Counter D0 Compare or Capture C */ - DMA_CH_TRIGSRC_TCD0_CCD_gc = (0x65<<0), /* Timer/Counter D0 Compare or Capture D */ - DMA_CH_TRIGSRC_TCD1_OVF_gc = (0x66<<0), /* Timer/Counter D1 Overflow */ - DMA_CH_TRIGSRC_TCD1_ERR_gc = (0x67<<0), /* Timer/Counter D1 Error */ - DMA_CH_TRIGSRC_TCD1_CCA_gc = (0x68<<0), /* Timer/Counter D1 Compare or Capture A */ - DMA_CH_TRIGSRC_TCD1_CCB_gc = (0x69<<0), /* Timer/Counter D1 Compare or Capture B */ - DMA_CH_TRIGSRC_SPID_gc = (0x6A<<0), /* SPI D Transfer Complete */ - DMA_CH_TRIGSRC_USARTD0_RXC_gc = (0x6B<<0), /* USART D0 Receive Complete */ - DMA_CH_TRIGSRC_USARTD0_DRE_gc = (0x6C<<0), /* USART D0 Data Register Empty */ - DMA_CH_TRIGSRC_USARTD1_RXC_gc = (0x6E<<0), /* USART D1 Receive Complete */ - DMA_CH_TRIGSRC_USARTD1_DRE_gc = (0x6F<<0), /* USART D1 Data Register Empty */ - DMA_CH_TRIGSRC_TCE0_OVF_gc = (0x80<<0), /* Timer/Counter E0 Overflow */ - DMA_CH_TRIGSRC_TCE0_ERR_gc = (0x81<<0), /* Timer/Counter E0 Error */ - DMA_CH_TRIGSRC_TCE0_CCA_gc = (0x82<<0), /* Timer/Counter E0 Compare or Capture A */ - DMA_CH_TRIGSRC_TCE0_CCB_gc = (0x83<<0), /* Timer/Counter E0 Compare or Capture B */ - DMA_CH_TRIGSRC_TCE0_CCC_gc = (0x84<<0), /* Timer/Counter E0 Compare or Capture C */ - DMA_CH_TRIGSRC_TCE0_CCD_gc = (0x85<<0), /* Timer/Counter E0 Compare or Capture D */ - DMA_CH_TRIGSRC_TCE1_OVF_gc = (0x86<<0), /* Timer/Counter E1 Overflow */ - DMA_CH_TRIGSRC_TCE1_ERR_gc = (0x87<<0), /* Timer/Counter E1 Error */ - DMA_CH_TRIGSRC_TCE1_CCA_gc = (0x88<<0), /* Timer/Counter E1 Compare or Capture A */ - DMA_CH_TRIGSRC_TCE1_CCB_gc = (0x89<<0), /* Timer/Counter E1 Compare or Capture B */ - DMA_CH_TRIGSRC_SPIE_gc = (0x8A<<0), /* SPI E Transfer Complete */ - DMA_CH_TRIGSRC_USARTE0_RXC_gc = (0x8B<<0), /* USART E0 Receive Complete */ - DMA_CH_TRIGSRC_USARTE0_DRE_gc = (0x8C<<0), /* USART E0 Data Register Empty */ - DMA_CH_TRIGSRC_USARTE1_RXC_gc = (0x8E<<0), /* USART E1 Receive Complete */ - DMA_CH_TRIGSRC_USARTE1_DRE_gc = (0x8F<<0), /* USART E1 Data Register Empty */ - DMA_CH_TRIGSRC_TCF0_OVF_gc = (0xA0<<0), /* Timer/Counter F0 Overflow */ - DMA_CH_TRIGSRC_TCF0_ERR_gc = (0xA1<<0), /* Timer/Counter F0 Error */ - DMA_CH_TRIGSRC_TCF0_CCA_gc = (0xA2<<0), /* Timer/Counter F0 Compare or Capture A */ - DMA_CH_TRIGSRC_TCF0_CCB_gc = (0xA3<<0), /* Timer/Counter F0 Compare or Capture B */ - DMA_CH_TRIGSRC_TCF0_CCC_gc = (0xA4<<0), /* Timer/Counter F0 Compare or Capture C */ - DMA_CH_TRIGSRC_TCF0_CCD_gc = (0xA5<<0), /* Timer/Counter F0 Compare or Capture D */ - DMA_CH_TRIGSRC_TCF1_OVF_gc = (0xA6<<0), /* Timer/Counter F1 Overflow */ - DMA_CH_TRIGSRC_TCF1_ERR_gc = (0xA7<<0), /* Timer/Counter F1 Error */ - DMA_CH_TRIGSRC_TCF1_CCA_gc = (0xA8<<0), /* Timer/Counter F1 Compare or Capture A */ - DMA_CH_TRIGSRC_TCF1_CCB_gc = (0xA9<<0), /* Timer/Counter F1 Compare or Capture B */ - DMA_CH_TRIGSRC_SPIF_gc = (0xAA<<0), /* SPI F Transfer Complete */ - DMA_CH_TRIGSRC_USARTF0_RXC_gc = (0xAB<<0), /* USART F0 Receive Complete */ - DMA_CH_TRIGSRC_USARTF0_DRE_gc = (0xAC<<0), /* USART F0 Data Register Empty */ - DMA_CH_TRIGSRC_USARTF1_RXC_gc = (0xAE<<0), /* USART F1 Receive Complete */ - DMA_CH_TRIGSRC_USARTF1_DRE_gc = (0xAF<<0), /* USART F1 Data Register Empty */ -} DMA_CH_TRIGSRC_t; - -/* Double buffering mode */ -typedef enum DMA_DBUFMODE_enum -{ - DMA_DBUFMODE_DISABLED_gc = (0x00<<2), /* Double buffering disabled */ - DMA_DBUFMODE_CH01_gc = (0x01<<2), /* Double buffering enabled on channel 0/1 */ - DMA_DBUFMODE_CH23_gc = (0x02<<2), /* Double buffering enabled on channel 2/3 */ - DMA_DBUFMODE_CH01CH23_gc = (0x03<<2), /* Double buffering enabled on ch. 0/1 and ch. 2/3 */ -} DMA_DBUFMODE_t; - -/* Priority mode */ -typedef enum DMA_PRIMODE_enum -{ - DMA_PRIMODE_RR0123_gc = (0x00<<0), /* Round Robin */ - DMA_PRIMODE_CH0RR123_gc = (0x01<<0), /* Channel 0 > Round Robin on channel 1/2/3 */ - DMA_PRIMODE_CH01RR23_gc = (0x02<<0), /* Channel 0 > channel 1 > Round Robin on channel 2/3 */ - DMA_PRIMODE_CH0123_gc = (0x03<<0), /* Channel 0 > channel 1 > channel 2 > channel 3 */ -} DMA_PRIMODE_t; - -/* Interrupt level */ -typedef enum DMA_CH_ERRINTLVL_enum -{ - DMA_CH_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ - DMA_CH_ERRINTLVL_LO_gc = (0x01<<2), /* Low level */ - DMA_CH_ERRINTLVL_MED_gc = (0x02<<2), /* Medium level */ - DMA_CH_ERRINTLVL_HI_gc = (0x03<<2), /* High level */ -} DMA_CH_ERRINTLVL_t; - -/* Interrupt level */ -typedef enum DMA_CH_TRNINTLVL_enum -{ - DMA_CH_TRNINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ - DMA_CH_TRNINTLVL_LO_gc = (0x01<<0), /* Low level */ - DMA_CH_TRNINTLVL_MED_gc = (0x02<<0), /* Medium level */ - DMA_CH_TRNINTLVL_HI_gc = (0x03<<0), /* High level */ -} DMA_CH_TRNINTLVL_t; - - -/* --------------------------------------------------------------------------- -EVSYS - Event System --------------------------------------------------------------------------- -*/ - -/* Event System */ -typedef struct EVSYS_struct -{ - register8_t CH0MUX; /* Event Channel 0 Multiplexer */ - register8_t CH1MUX; /* Event Channel 1 Multiplexer */ - register8_t CH2MUX; /* Event Channel 2 Multiplexer */ - register8_t CH3MUX; /* Event Channel 3 Multiplexer */ - register8_t CH4MUX; /* Event Channel 4 Multiplexer */ - register8_t CH5MUX; /* Event Channel 5 Multiplexer */ - register8_t CH6MUX; /* Event Channel 6 Multiplexer */ - register8_t CH7MUX; /* Event Channel 7 Multiplexer */ - register8_t CH0CTRL; /* Channel 0 Control Register */ - register8_t CH1CTRL; /* Channel 1 Control Register */ - register8_t CH2CTRL; /* Channel 2 Control Register */ - register8_t CH3CTRL; /* Channel 3 Control Register */ - register8_t CH4CTRL; /* Channel 4 Control Register */ - register8_t CH5CTRL; /* Channel 5 Control Register */ - register8_t CH6CTRL; /* Channel 6 Control Register */ - register8_t CH7CTRL; /* Channel 7 Control Register */ - register8_t STROBE; /* Event Strobe */ - register8_t DATA; /* Event Data */ -} EVSYS_t; - -/* Quadrature Decoder Index Recognition Mode */ -typedef enum EVSYS_QDIRM_enum -{ - EVSYS_QDIRM_00_gc = (0x00<<5), /* QDPH0 = 0, QDPH90 = 0 */ - EVSYS_QDIRM_01_gc = (0x01<<5), /* QDPH0 = 0, QDPH90 = 1 */ - EVSYS_QDIRM_10_gc = (0x02<<5), /* QDPH0 = 1, QDPH90 = 0 */ - EVSYS_QDIRM_11_gc = (0x03<<5), /* QDPH0 = 1, QDPH90 = 1 */ -} EVSYS_QDIRM_t; - -/* Digital filter coefficient */ -typedef enum EVSYS_DIGFILT_enum -{ - EVSYS_DIGFILT_1SAMPLE_gc = (0x00<<0), /* 1 SAMPLE */ - EVSYS_DIGFILT_2SAMPLES_gc = (0x01<<0), /* 2 SAMPLES */ - EVSYS_DIGFILT_3SAMPLES_gc = (0x02<<0), /* 3 SAMPLES */ - EVSYS_DIGFILT_4SAMPLES_gc = (0x03<<0), /* 4 SAMPLES */ - EVSYS_DIGFILT_5SAMPLES_gc = (0x04<<0), /* 5 SAMPLES */ - EVSYS_DIGFILT_6SAMPLES_gc = (0x05<<0), /* 6 SAMPLES */ - EVSYS_DIGFILT_7SAMPLES_gc = (0x06<<0), /* 7 SAMPLES */ - EVSYS_DIGFILT_8SAMPLES_gc = (0x07<<0), /* 8 SAMPLES */ -} EVSYS_DIGFILT_t; - -/* Event Channel multiplexer input selection */ -typedef enum EVSYS_CHMUX_enum -{ - EVSYS_CHMUX_OFF_gc = (0x00<<0), /* Off */ - EVSYS_CHMUX_RTC_OVF_gc = (0x08<<0), /* RTC Overflow */ - EVSYS_CHMUX_RTC_CMP_gc = (0x09<<0), /* RTC Compare Match */ - EVSYS_CHMUX_ACA_CH0_gc = (0x10<<0), /* Analog Comparator A Channel 0 */ - EVSYS_CHMUX_ACA_CH1_gc = (0x11<<0), /* Analog Comparator A Channel 1 */ - EVSYS_CHMUX_ACA_WIN_gc = (0x12<<0), /* Analog Comparator A Window */ - EVSYS_CHMUX_ACB_CH0_gc = (0x13<<0), /* Analog Comparator B Channel 0 */ - EVSYS_CHMUX_ACB_CH1_gc = (0x14<<0), /* Analog Comparator B Channel 1 */ - EVSYS_CHMUX_ACB_WIN_gc = (0x15<<0), /* Analog Comparator B Window */ - EVSYS_CHMUX_ADCA_CH0_gc = (0x20<<0), /* ADC A Channel 0 */ - EVSYS_CHMUX_ADCA_CH1_gc = (0x21<<0), /* ADC A Channel 1 */ - EVSYS_CHMUX_ADCA_CH2_gc = (0x22<<0), /* ADC A Channel 2 */ - EVSYS_CHMUX_ADCA_CH3_gc = (0x23<<0), /* ADC A Channel 3 */ - EVSYS_CHMUX_ADCB_CH0_gc = (0x24<<0), /* ADC B Channel 0 */ - EVSYS_CHMUX_ADCB_CH1_gc = (0x25<<0), /* ADC B Channel 1 */ - EVSYS_CHMUX_ADCB_CH2_gc = (0x26<<0), /* ADC B Channel 2 */ - EVSYS_CHMUX_ADCB_CH3_gc = (0x27<<0), /* ADC B Channel 3 */ - EVSYS_CHMUX_PORTA_PIN0_gc = (0x50<<0), /* Port A, Pin0 */ - EVSYS_CHMUX_PORTA_PIN1_gc = (0x51<<0), /* Port A, Pin1 */ - EVSYS_CHMUX_PORTA_PIN2_gc = (0x52<<0), /* Port A, Pin2 */ - EVSYS_CHMUX_PORTA_PIN3_gc = (0x53<<0), /* Port A, Pin3 */ - EVSYS_CHMUX_PORTA_PIN4_gc = (0x54<<0), /* Port A, Pin4 */ - EVSYS_CHMUX_PORTA_PIN5_gc = (0x55<<0), /* Port A, Pin5 */ - EVSYS_CHMUX_PORTA_PIN6_gc = (0x56<<0), /* Port A, Pin6 */ - EVSYS_CHMUX_PORTA_PIN7_gc = (0x57<<0), /* Port A, Pin7 */ - EVSYS_CHMUX_PORTB_PIN0_gc = (0x58<<0), /* Port B, Pin0 */ - EVSYS_CHMUX_PORTB_PIN1_gc = (0x59<<0), /* Port B, Pin1 */ - EVSYS_CHMUX_PORTB_PIN2_gc = (0x5A<<0), /* Port B, Pin2 */ - EVSYS_CHMUX_PORTB_PIN3_gc = (0x5B<<0), /* Port B, Pin3 */ - EVSYS_CHMUX_PORTB_PIN4_gc = (0x5C<<0), /* Port B, Pin4 */ - EVSYS_CHMUX_PORTB_PIN5_gc = (0x5D<<0), /* Port B, Pin5 */ - EVSYS_CHMUX_PORTB_PIN6_gc = (0x5E<<0), /* Port B, Pin6 */ - EVSYS_CHMUX_PORTB_PIN7_gc = (0x5F<<0), /* Port B, Pin7 */ - EVSYS_CHMUX_PORTC_PIN0_gc = (0x60<<0), /* Port C, Pin0 */ - EVSYS_CHMUX_PORTC_PIN1_gc = (0x61<<0), /* Port C, Pin1 */ - EVSYS_CHMUX_PORTC_PIN2_gc = (0x62<<0), /* Port C, Pin2 */ - EVSYS_CHMUX_PORTC_PIN3_gc = (0x63<<0), /* Port C, Pin3 */ - EVSYS_CHMUX_PORTC_PIN4_gc = (0x64<<0), /* Port C, Pin4 */ - EVSYS_CHMUX_PORTC_PIN5_gc = (0x65<<0), /* Port C, Pin5 */ - EVSYS_CHMUX_PORTC_PIN6_gc = (0x66<<0), /* Port C, Pin6 */ - EVSYS_CHMUX_PORTC_PIN7_gc = (0x67<<0), /* Port C, Pin7 */ - EVSYS_CHMUX_PORTD_PIN0_gc = (0x68<<0), /* Port D, Pin0 */ - EVSYS_CHMUX_PORTD_PIN1_gc = (0x69<<0), /* Port D, Pin1 */ - EVSYS_CHMUX_PORTD_PIN2_gc = (0x6A<<0), /* Port D, Pin2 */ - EVSYS_CHMUX_PORTD_PIN3_gc = (0x6B<<0), /* Port D, Pin3 */ - EVSYS_CHMUX_PORTD_PIN4_gc = (0x6C<<0), /* Port D, Pin4 */ - EVSYS_CHMUX_PORTD_PIN5_gc = (0x6D<<0), /* Port D, Pin5 */ - EVSYS_CHMUX_PORTD_PIN6_gc = (0x6E<<0), /* Port D, Pin6 */ - EVSYS_CHMUX_PORTD_PIN7_gc = (0x6F<<0), /* Port D, Pin7 */ - EVSYS_CHMUX_PORTE_PIN0_gc = (0x70<<0), /* Port E, Pin0 */ - EVSYS_CHMUX_PORTE_PIN1_gc = (0x71<<0), /* Port E, Pin1 */ - EVSYS_CHMUX_PORTE_PIN2_gc = (0x72<<0), /* Port E, Pin2 */ - EVSYS_CHMUX_PORTE_PIN3_gc = (0x73<<0), /* Port E, Pin3 */ - EVSYS_CHMUX_PORTE_PIN4_gc = (0x74<<0), /* Port E, Pin4 */ - EVSYS_CHMUX_PORTE_PIN5_gc = (0x75<<0), /* Port E, Pin5 */ - EVSYS_CHMUX_PORTE_PIN6_gc = (0x76<<0), /* Port E, Pin6 */ - EVSYS_CHMUX_PORTE_PIN7_gc = (0x77<<0), /* Port E, Pin7 */ - EVSYS_CHMUX_PORTF_PIN0_gc = (0x78<<0), /* Port F, Pin0 */ - EVSYS_CHMUX_PORTF_PIN1_gc = (0x79<<0), /* Port F, Pin1 */ - EVSYS_CHMUX_PORTF_PIN2_gc = (0x7A<<0), /* Port F, Pin2 */ - EVSYS_CHMUX_PORTF_PIN3_gc = (0x7B<<0), /* Port F, Pin3 */ - EVSYS_CHMUX_PORTF_PIN4_gc = (0x7C<<0), /* Port F, Pin4 */ - EVSYS_CHMUX_PORTF_PIN5_gc = (0x7D<<0), /* Port F, Pin5 */ - EVSYS_CHMUX_PORTF_PIN6_gc = (0x7E<<0), /* Port F, Pin6 */ - EVSYS_CHMUX_PORTF_PIN7_gc = (0x7F<<0), /* Port F, Pin7 */ - EVSYS_CHMUX_PRESCALER_1_gc = (0x80<<0), /* Prescaler, divide by 1 */ - EVSYS_CHMUX_PRESCALER_2_gc = (0x81<<0), /* Prescaler, divide by 2 */ - EVSYS_CHMUX_PRESCALER_4_gc = (0x82<<0), /* Prescaler, divide by 4 */ - EVSYS_CHMUX_PRESCALER_8_gc = (0x83<<0), /* Prescaler, divide by 8 */ - EVSYS_CHMUX_PRESCALER_16_gc = (0x84<<0), /* Prescaler, divide by 16 */ - EVSYS_CHMUX_PRESCALER_32_gc = (0x85<<0), /* Prescaler, divide by 32 */ - EVSYS_CHMUX_PRESCALER_64_gc = (0x86<<0), /* Prescaler, divide by 64 */ - EVSYS_CHMUX_PRESCALER_128_gc = (0x87<<0), /* Prescaler, divide by 128 */ - EVSYS_CHMUX_PRESCALER_256_gc = (0x88<<0), /* Prescaler, divide by 256 */ - EVSYS_CHMUX_PRESCALER_512_gc = (0x89<<0), /* Prescaler, divide by 512 */ - EVSYS_CHMUX_PRESCALER_1024_gc = (0x8A<<0), /* Prescaler, divide by 1024 */ - EVSYS_CHMUX_PRESCALER_2048_gc = (0x8B<<0), /* Prescaler, divide by 2048 */ - EVSYS_CHMUX_PRESCALER_4096_gc = (0x8C<<0), /* Prescaler, divide by 4096 */ - EVSYS_CHMUX_PRESCALER_8192_gc = (0x8D<<0), /* Prescaler, divide by 8192 */ - EVSYS_CHMUX_PRESCALER_16384_gc = (0x8E<<0), /* Prescaler, divide by 16384 */ - EVSYS_CHMUX_PRESCALER_32768_gc = (0x8F<<0), /* Prescaler, divide by 32768 */ - EVSYS_CHMUX_TCC0_OVF_gc = (0xC0<<0), /* Timer/Counter C0 Overflow */ - EVSYS_CHMUX_TCC0_ERR_gc = (0xC1<<0), /* Timer/Counter C0 Error */ - EVSYS_CHMUX_TCC0_CCA_gc = (0xC4<<0), /* Timer/Counter C0 Compare or Capture A */ - EVSYS_CHMUX_TCC0_CCB_gc = (0xC5<<0), /* Timer/Counter C0 Compare or Capture B */ - EVSYS_CHMUX_TCC0_CCC_gc = (0xC6<<0), /* Timer/Counter C0 Compare or Capture C */ - EVSYS_CHMUX_TCC0_CCD_gc = (0xC7<<0), /* Timer/Counter C0 Compare or Capture D */ - EVSYS_CHMUX_TCC1_OVF_gc = (0xC8<<0), /* Timer/Counter C1 Overflow */ - EVSYS_CHMUX_TCC1_ERR_gc = (0xC9<<0), /* Timer/Counter C1 Error */ - EVSYS_CHMUX_TCC1_CCA_gc = (0xCC<<0), /* Timer/Counter C1 Compare or Capture A */ - EVSYS_CHMUX_TCC1_CCB_gc = (0xCD<<0), /* Timer/Counter C1 Compare or Capture B */ - EVSYS_CHMUX_TCD0_OVF_gc = (0xD0<<0), /* Timer/Counter D0 Overflow */ - EVSYS_CHMUX_TCD0_ERR_gc = (0xD1<<0), /* Timer/Counter D0 Error */ - EVSYS_CHMUX_TCD0_CCA_gc = (0xD4<<0), /* Timer/Counter D0 Compare or Capture A */ - EVSYS_CHMUX_TCD0_CCB_gc = (0xD5<<0), /* Timer/Counter D0 Compare or Capture B */ - EVSYS_CHMUX_TCD0_CCC_gc = (0xD6<<0), /* Timer/Counter D0 Compare or Capture C */ - EVSYS_CHMUX_TCD0_CCD_gc = (0xD7<<0), /* Timer/Counter D0 Compare or Capture D */ - EVSYS_CHMUX_TCD1_OVF_gc = (0xD8<<0), /* Timer/Counter D1 Overflow */ - EVSYS_CHMUX_TCD1_ERR_gc = (0xD9<<0), /* Timer/Counter D1 Error */ - EVSYS_CHMUX_TCD1_CCA_gc = (0xDC<<0), /* Timer/Counter D1 Compare or Capture A */ - EVSYS_CHMUX_TCD1_CCB_gc = (0xDD<<0), /* Timer/Counter D1 Compare or Capture B */ - EVSYS_CHMUX_TCE0_OVF_gc = (0xE0<<0), /* Timer/Counter E0 Overflow */ - EVSYS_CHMUX_TCE0_ERR_gc = (0xE1<<0), /* Timer/Counter E0 Error */ - EVSYS_CHMUX_TCE0_CCA_gc = (0xE4<<0), /* Timer/Counter E0 Compare or Capture A */ - EVSYS_CHMUX_TCE0_CCB_gc = (0xE5<<0), /* Timer/Counter E0 Compare or Capture B */ - EVSYS_CHMUX_TCE0_CCC_gc = (0xE6<<0), /* Timer/Counter E0 Compare or Capture C */ - EVSYS_CHMUX_TCE0_CCD_gc = (0xE7<<0), /* Timer/Counter E0 Compare or Capture D */ - EVSYS_CHMUX_TCE1_OVF_gc = (0xE8<<0), /* Timer/Counter E1 Overflow */ - EVSYS_CHMUX_TCE1_ERR_gc = (0xE9<<0), /* Timer/Counter E1 Error */ - EVSYS_CHMUX_TCE1_CCA_gc = (0xEC<<0), /* Timer/Counter E1 Compare or Capture A */ - EVSYS_CHMUX_TCE1_CCB_gc = (0xED<<0), /* Timer/Counter E1 Compare or Capture B */ - EVSYS_CHMUX_TCF0_OVF_gc = (0xF0<<0), /* Timer/Counter F0 Overflow */ - EVSYS_CHMUX_TCF0_ERR_gc = (0xF1<<0), /* Timer/Counter F0 Error */ - EVSYS_CHMUX_TCF0_CCA_gc = (0xF4<<0), /* Timer/Counter F0 Compare or Capture A */ - EVSYS_CHMUX_TCF0_CCB_gc = (0xF5<<0), /* Timer/Counter F0 Compare or Capture B */ - EVSYS_CHMUX_TCF0_CCC_gc = (0xF6<<0), /* Timer/Counter F0 Compare or Capture C */ - EVSYS_CHMUX_TCF0_CCD_gc = (0xF7<<0), /* Timer/Counter F0 Compare or Capture D */ - EVSYS_CHMUX_TCF1_OVF_gc = (0xF8<<0), /* Timer/Counter F1 Overflow */ - EVSYS_CHMUX_TCF1_ERR_gc = (0xF9<<0), /* Timer/Counter F1 Error */ - EVSYS_CHMUX_TCF1_CCA_gc = (0xFC<<0), /* Timer/Counter F1 Compare or Capture A */ - EVSYS_CHMUX_TCF1_CCB_gc = (0xFD<<0), /* Timer/Counter F1 Compare or Capture B */ -} EVSYS_CHMUX_t; - - -/* --------------------------------------------------------------------------- -NVM - Non Volatile Memory Controller --------------------------------------------------------------------------- -*/ - -/* Non-volatile Memory Controller */ -typedef struct NVM_struct -{ - register8_t ADDR0; /* Address Register 0 */ - register8_t ADDR1; /* Address Register 1 */ - register8_t ADDR2; /* Address Register 2 */ - register8_t reserved_0x03; - register8_t DATA0; /* Data Register 0 */ - register8_t DATA1; /* Data Register 1 */ - register8_t DATA2; /* Data Register 2 */ - register8_t reserved_0x07; - register8_t reserved_0x08; - register8_t reserved_0x09; - register8_t CMD; /* Command */ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t INTCTRL; /* Interrupt Control */ - register8_t reserved_0x0E; - register8_t STATUS; /* Status */ - register8_t LOCK_BITS; /* Lock Bits */ -} NVM_t; - -/* --------------------------------------------------------------------------- -NVM - Non Volatile Memory Controller --------------------------------------------------------------------------- -*/ - -/* Lock Bits */ -typedef struct NVM_LOCKBITS_struct -{ - register8_t LOCKBITS; /* Lock Bits */ -} NVM_LOCKBITS_t; - -/* --------------------------------------------------------------------------- -NVM - Non Volatile Memory Controller --------------------------------------------------------------------------- -*/ - -/* Fuses */ -typedef struct NVM_FUSES_struct -{ - register8_t FUSEBYTE0; /* JTAG User ID */ - register8_t FUSEBYTE1; /* Watchdog Configuration */ - register8_t FUSEBYTE2; /* Reset Configuration */ - register8_t reserved_0x03; - register8_t FUSEBYTE4; /* Start-up Configuration */ - register8_t FUSEBYTE5; /* EESAVE and BOD Level */ -} NVM_FUSES_t; - -/* --------------------------------------------------------------------------- -NVM - Non Volatile Memory Controller --------------------------------------------------------------------------- -*/ - -/* Production Signatures */ -typedef struct NVM_PROD_SIGNATURES_struct -{ - register8_t RCOSC2M; /* RCOSC 2MHz Calibration Value */ - register8_t reserved_0x01; - register8_t RCOSC32K; /* RCOSC 32kHz Calibration Value */ - register8_t RCOSC32M; /* RCOSC 32MHz Calibration Value */ - register8_t reserved_0x04; - register8_t reserved_0x05; - register8_t reserved_0x06; - register8_t reserved_0x07; - register8_t LOTNUM0; /* Lot Number Byte 0, ASCII */ - register8_t LOTNUM1; /* Lot Number Byte 1, ASCII */ - register8_t LOTNUM2; /* Lot Number Byte 2, ASCII */ - register8_t LOTNUM3; /* Lot Number Byte 3, ASCII */ - register8_t LOTNUM4; /* Lot Number Byte 4, ASCII */ - register8_t LOTNUM5; /* Lot Number Byte 5, ASCII */ - register8_t reserved_0x0E; - register8_t reserved_0x0F; - register8_t WAFNUM; /* Wafer Number */ - register8_t reserved_0x11; - register8_t COORDX0; /* Wafer Coordinate X Byte 0 */ - register8_t COORDX1; /* Wafer Coordinate X Byte 1 */ - register8_t COORDY0; /* Wafer Coordinate Y Byte 0 */ - register8_t COORDY1; /* Wafer Coordinate Y Byte 1 */ - register8_t reserved_0x16; - register8_t reserved_0x17; - register8_t reserved_0x18; - register8_t reserved_0x19; - register8_t reserved_0x1A; - register8_t reserved_0x1B; - register8_t reserved_0x1C; - register8_t reserved_0x1D; - register8_t reserved_0x1E; - register8_t reserved_0x1F; - register8_t ADCACAL0; /* ADCA Calibration Byte 0 */ - register8_t ADCACAL1; /* ADCA Calibration Byte 1 */ - register8_t reserved_0x22; - register8_t reserved_0x23; - register8_t ADCBCAL0; /* ADCB Calibration Byte 0 */ - register8_t ADCBCAL1; /* ADCB Calibration Byte 1 */ - register8_t reserved_0x26; - register8_t reserved_0x27; - register8_t reserved_0x28; - register8_t reserved_0x29; - register8_t reserved_0x2A; - register8_t reserved_0x2B; - register8_t reserved_0x2C; - register8_t reserved_0x2D; - register8_t TEMPSENSE0; /* Temperature Sensor Calibration Byte 0 */ - register8_t TEMPSENSE1; /* Temperature Sensor Calibration Byte 0 */ - register8_t DACAOFFCAL; /* DACA Calibration Byte 0 */ - register8_t DACAGAINCAL; /* DACA Calibration Byte 1 */ - register8_t DACBOFFCAL; /* DACB Calibration Byte 0 */ - register8_t DACBGAINCAL; /* DACB Calibration Byte 1 */ - register8_t reserved_0x34; - register8_t reserved_0x35; - register8_t reserved_0x36; - register8_t reserved_0x37; - register8_t reserved_0x38; - register8_t reserved_0x39; - register8_t reserved_0x3A; - register8_t reserved_0x3B; - register8_t reserved_0x3C; - register8_t reserved_0x3D; - register8_t reserved_0x3E; -} NVM_PROD_SIGNATURES_t; - -/* NVM Command */ -typedef enum NVM_CMD_enum -{ - NVM_CMD_NO_OPERATION_gc = (0x00<<0), /* Noop/Ordinary LPM */ - NVM_CMD_READ_CALIB_ROW_gc = (0x02<<0), /* Read calibration row */ - NVM_CMD_READ_USER_SIG_ROW_gc = (0x01<<0), /* Read user signature row */ - NVM_CMD_READ_EEPROM_gc = (0x06<<0), /* Read EEPROM */ - NVM_CMD_READ_FUSES_gc = (0x07<<0), /* Read fuse byte */ - NVM_CMD_WRITE_LOCK_BITS_gc = (0x08<<0), /* Write lock bits */ - NVM_CMD_ERASE_USER_SIG_ROW_gc = (0x18<<0), /* Erase user signature row */ - NVM_CMD_WRITE_USER_SIG_ROW_gc = (0x1A<<0), /* Write user signature row */ - NVM_CMD_ERASE_APP_gc = (0x20<<0), /* Erase Application Section */ - NVM_CMD_ERASE_APP_PAGE_gc = (0x22<<0), /* Erase Application Section page */ - NVM_CMD_LOAD_FLASH_BUFFER_gc = (0x23<<0), /* Load Flash page buffer */ - NVM_CMD_WRITE_APP_PAGE_gc = (0x24<<0), /* Write Application Section page */ - NVM_CMD_ERASE_WRITE_APP_PAGE_gc = (0x25<<0), /* Erase-and-write Application Section page */ - NVM_CMD_ERASE_FLASH_BUFFER_gc = (0x26<<0), /* Erase/flush Flash page buffer */ - NVM_CMD_ERASE_BOOT_PAGE_gc = (0x2A<<0), /* Erase Boot Section page */ - NVM_CMD_WRITE_BOOT_PAGE_gc = (0x2C<<0), /* Write Boot Section page */ - NVM_CMD_ERASE_WRITE_BOOT_PAGE_gc = (0x2D<<0), /* Erase-and-write Boot Section page */ - NVM_CMD_ERASE_EEPROM_gc = (0x30<<0), /* Erase EEPROM */ - NVM_CMD_ERASE_EEPROM_PAGE_gc = (0x32<<0), /* Erase EEPROM page */ - NVM_CMD_LOAD_EEPROM_BUFFER_gc = (0x33<<0), /* Load EEPROM page buffer */ - NVM_CMD_WRITE_EEPROM_PAGE_gc = (0x34<<0), /* Write EEPROM page */ - NVM_CMD_ERASE_WRITE_EEPROM_PAGE_gc = (0x35<<0), /* Erase-and-write EEPROM page */ - NVM_CMD_ERASE_EEPROM_BUFFER_gc = (0x36<<0), /* Erase/flush EEPROM page buffer */ - NVM_CMD_APP_CRC_gc = (0x38<<0), /* Generate Application section CRC */ - NVM_CMD_BOOT_CRC_gc = (0x39<<0), /* Generate Boot Section CRC */ - NVM_CMD_FLASH_RANGE_CRC_gc = (0x3A<<0), /* Generate Flash Range CRC */ -} NVM_CMD_t; - -/* SPM ready interrupt level */ -typedef enum NVM_SPMLVL_enum -{ - NVM_SPMLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ - NVM_SPMLVL_LO_gc = (0x01<<2), /* Low level */ - NVM_SPMLVL_MED_gc = (0x02<<2), /* Medium level */ - NVM_SPMLVL_HI_gc = (0x03<<2), /* High level */ -} NVM_SPMLVL_t; - -/* EEPROM ready interrupt level */ -typedef enum NVM_EELVL_enum -{ - NVM_EELVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ - NVM_EELVL_LO_gc = (0x01<<0), /* Low level */ - NVM_EELVL_MED_gc = (0x02<<0), /* Medium level */ - NVM_EELVL_HI_gc = (0x03<<0), /* High level */ -} NVM_EELVL_t; - -/* Boot lock bits - boot setcion */ -typedef enum NVM_BLBB_enum -{ - NVM_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ - NVM_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ - NVM_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ - NVM_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ -} NVM_BLBB_t; - -/* Boot lock bits - application section */ -typedef enum NVM_BLBA_enum -{ - NVM_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ - NVM_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ - NVM_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ - NVM_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ -} NVM_BLBA_t; - -/* Boot lock bits - application table section */ -typedef enum NVM_BLBAT_enum -{ - NVM_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ - NVM_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ - NVM_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ - NVM_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ -} NVM_BLBAT_t; - -/* Lock bits */ -typedef enum NVM_LB_enum -{ - NVM_LB_NOLOCK_gc = (0x03<<0), /* No locks */ - NVM_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ - NVM_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ -} NVM_LB_t; - -/* Boot Loader Section Reset Vector */ -typedef enum BOOTRST_enum -{ - BOOTRST_BOOTLDR_gc = (0x00<<6), /* Boot Loader Reset */ - BOOTRST_APPLICATION_gc = (0x01<<6), /* Application Reset */ -} BOOTRST_t; - -/* BOD operation */ -typedef enum BOD_enum -{ - BOD_INSAMPLEDMODE_gc = (0x01<<0), /* BOD enabled in sampled mode */ - BOD_CONTINOUSLY_gc = (0x02<<0), /* BOD enabled continuously */ - BOD_DISABLED_gc = (0x03<<0), /* BOD Disabled */ -} BOD_t; - -/* Watchdog (Window) Timeout Period */ -typedef enum WD_enum -{ - WD_8CLK_gc = (0x00<<4), /* 8 cycles (8ms @ 3.3V) */ - WD_16CLK_gc = (0x01<<4), /* 16 cycles (16ms @ 3.3V) */ - WD_32CLK_gc = (0x02<<4), /* 32 cycles (32ms @ 3.3V) */ - WD_64CLK_gc = (0x03<<4), /* 64 cycles (64ms @ 3.3V) */ - WD_128CLK_gc = (0x04<<4), /* 128 cycles (0.125s @ 3.3V) */ - WD_256CLK_gc = (0x05<<4), /* 256 cycles (0.25s @ 3.3V) */ - WD_512CLK_gc = (0x06<<4), /* 512 cycles (0.5s @ 3.3V) */ - WD_1KCLK_gc = (0x07<<4), /* 1K cycles (1s @ 3.3V) */ - WD_2KCLK_gc = (0x08<<4), /* 2K cycles (2s @ 3.3V) */ - WD_4KCLK_gc = (0x09<<4), /* 4K cycles (4s @ 3.3V) */ - WD_8KCLK_gc = (0x0A<<4), /* 8K cycles (8s @ 3.3V) */ -} WD_t; - -/* Start-up Time */ -typedef enum SUT_enum -{ - SUT_0MS_gc = (0x03<<2), /* 0 ms */ - SUT_4MS_gc = (0x01<<2), /* 4 ms */ - SUT_64MS_gc = (0x00<<2), /* 64 ms */ -} SUT_t; - -/* Brown Out Detection Voltage Level */ -typedef enum BODLVL_enum -{ - BODLVL_1V6_gc = (0x07<<0), /* 1.6 V */ - BODLVL_1V9_gc = (0x06<<0), /* 1.8 V */ - BODLVL_2V1_gc = (0x05<<0), /* 2.0 V */ - BODLVL_2V4_gc = (0x04<<0), /* 2.2 V */ - BODLVL_2V6_gc = (0x03<<0), /* 2.4 V */ - BODLVL_2V9_gc = (0x02<<0), /* 2.7 V */ - BODLVL_3V2_gc = (0x01<<0), /* 2.9 V */ -} BODLVL_t; - - -/* --------------------------------------------------------------------------- -AC - Analog Comparator --------------------------------------------------------------------------- -*/ - -/* Analog Comparator */ -typedef struct AC_struct -{ - register8_t AC0CTRL; /* Comparator 0 Control */ - register8_t AC1CTRL; /* Comparator 1 Control */ - register8_t AC0MUXCTRL; /* Comparator 0 MUX Control */ - register8_t AC1MUXCTRL; /* Comparator 1 MUX Control */ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t WINCTRL; /* Window Mode Control */ - register8_t STATUS; /* Status */ -} AC_t; - -/* Interrupt mode */ -typedef enum AC_INTMODE_enum -{ - AC_INTMODE_BOTHEDGES_gc = (0x00<<6), /* Interrupt on both edges */ - AC_INTMODE_FALLING_gc = (0x02<<6), /* Interrupt on falling edge */ - AC_INTMODE_RISING_gc = (0x03<<6), /* Interrupt on rising edge */ -} AC_INTMODE_t; - -/* Interrupt level */ -typedef enum AC_INTLVL_enum -{ - AC_INTLVL_OFF_gc = (0x00<<4), /* Interrupt disabled */ - AC_INTLVL_LO_gc = (0x01<<4), /* Low level */ - AC_INTLVL_MED_gc = (0x02<<4), /* Medium level */ - AC_INTLVL_HI_gc = (0x03<<4), /* High level */ -} AC_INTLVL_t; - -/* Hysteresis mode selection */ -typedef enum AC_HYSMODE_enum -{ - AC_HYSMODE_NO_gc = (0x00<<1), /* No hysteresis */ - AC_HYSMODE_SMALL_gc = (0x01<<1), /* Small hysteresis */ - AC_HYSMODE_LARGE_gc = (0x02<<1), /* Large hysteresis */ -} AC_HYSMODE_t; - -/* Positive input multiplexer selection */ -typedef enum AC_MUXPOS_enum -{ - AC_MUXPOS_PIN0_gc = (0x00<<3), /* Pin 0 */ - AC_MUXPOS_PIN1_gc = (0x01<<3), /* Pin 1 */ - AC_MUXPOS_PIN2_gc = (0x02<<3), /* Pin 2 */ - AC_MUXPOS_PIN3_gc = (0x03<<3), /* Pin 3 */ - AC_MUXPOS_PIN4_gc = (0x04<<3), /* Pin 4 */ - AC_MUXPOS_PIN5_gc = (0x05<<3), /* Pin 5 */ - AC_MUXPOS_PIN6_gc = (0x06<<3), /* Pin 6 */ - AC_MUXPOS_DAC_gc = (0x07<<3), /* DAC output */ -} AC_MUXPOS_t; - -/* Negative input multiplexer selection */ -typedef enum AC_MUXNEG_enum -{ - AC_MUXNEG_PIN0_gc = (0x00<<0), /* Pin 0 */ - AC_MUXNEG_PIN1_gc = (0x01<<0), /* Pin 1 */ - AC_MUXNEG_PIN3_gc = (0x02<<0), /* Pin 3 */ - AC_MUXNEG_PIN5_gc = (0x03<<0), /* Pin 5 */ - AC_MUXNEG_PIN7_gc = (0x04<<0), /* Pin 7 */ - AC_MUXNEG_DAC_gc = (0x05<<0), /* DAC output */ - AC_MUXNEG_BANDGAP_gc = (0x06<<0), /* Bandgap Reference */ - AC_MUXNEG_SCALER_gc = (0x07<<0), /* Internal voltage scaler */ -} AC_MUXNEG_t; - -/* Windows interrupt mode */ -typedef enum AC_WINTMODE_enum -{ - AC_WINTMODE_ABOVE_gc = (0x00<<2), /* Interrupt on above window */ - AC_WINTMODE_INSIDE_gc = (0x01<<2), /* Interrupt on inside window */ - AC_WINTMODE_BELOW_gc = (0x02<<2), /* Interrupt on below window */ - AC_WINTMODE_OUTSIDE_gc = (0x03<<2), /* Interrupt on outside window */ -} AC_WINTMODE_t; - -/* Window interrupt level */ -typedef enum AC_WINTLVL_enum -{ - AC_WINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ - AC_WINTLVL_LO_gc = (0x01<<0), /* Low priority */ - AC_WINTLVL_MED_gc = (0x02<<0), /* Medium priority */ - AC_WINTLVL_HI_gc = (0x03<<0), /* High priority */ -} AC_WINTLVL_t; - -/* Window mode state */ -typedef enum AC_WSTATE_enum -{ - AC_WSTATE_ABOVE_gc = (0x00<<6), /* Signal above window */ - AC_WSTATE_INSIDE_gc = (0x01<<6), /* Signal inside window */ - AC_WSTATE_BELOW_gc = (0x02<<6), /* Signal below window */ -} AC_WSTATE_t; - - -/* --------------------------------------------------------------------------- -ADC - Analog/Digital Converter --------------------------------------------------------------------------- -*/ - -/* ADC Channel */ -typedef struct ADC_CH_struct -{ - register8_t CTRL; /* Control Register */ - register8_t MUXCTRL; /* MUX Control */ - register8_t INTCTRL; /* Channel Interrupt Control */ - register8_t INTFLAGS; /* Interrupt Flags */ - _WORDREGISTER(RES); /* Channel Result */ - register8_t reserved_0x6; - register8_t reserved_0x7; -} ADC_CH_t; - -/* --------------------------------------------------------------------------- -ADC - Analog/Digital Converter --------------------------------------------------------------------------- -*/ - -/* Analog-to-Digital Converter */ -typedef struct ADC_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t REFCTRL; /* Reference Control */ - register8_t EVCTRL; /* Event Control */ - register8_t PRESCALER; /* Clock Prescaler */ - register8_t reserved_0x05; - register8_t INTFLAGS; /* Interrupt Flags */ - register8_t reserved_0x07; - register8_t reserved_0x08; - register8_t reserved_0x09; - register8_t reserved_0x0A; - register8_t reserved_0x0B; - _WORDREGISTER(CAL); /* Calibration Value */ - register8_t reserved_0x0E; - register8_t reserved_0x0F; - _WORDREGISTER(CH0RES); /* Channel 0 Result */ - _WORDREGISTER(CH1RES); /* Channel 1 Result */ - _WORDREGISTER(CH2RES); /* Channel 2 Result */ - _WORDREGISTER(CH3RES); /* Channel 3 Result */ - _WORDREGISTER(CMP); /* Compare Value */ - register8_t reserved_0x1A; - register8_t reserved_0x1B; - register8_t reserved_0x1C; - register8_t reserved_0x1D; - register8_t reserved_0x1E; - register8_t reserved_0x1F; - ADC_CH_t CH0; /* ADC Channel 0 */ - ADC_CH_t CH1; /* ADC Channel 1 */ - ADC_CH_t CH2; /* ADC Channel 2 */ - ADC_CH_t CH3; /* ADC Channel 3 */ -} ADC_t; - -/* Positive input multiplexer selection */ -typedef enum ADC_CH_MUXPOS_enum -{ - ADC_CH_MUXPOS_PIN0_gc = (0x00<<3), /* Input pin 0 */ - ADC_CH_MUXPOS_PIN1_gc = (0x01<<3), /* Input pin 1 */ - ADC_CH_MUXPOS_PIN2_gc = (0x02<<3), /* Input pin 2 */ - ADC_CH_MUXPOS_PIN3_gc = (0x03<<3), /* Input pin 3 */ - ADC_CH_MUXPOS_PIN4_gc = (0x04<<3), /* Input pin 4 */ - ADC_CH_MUXPOS_PIN5_gc = (0x05<<3), /* Input pin 5 */ - ADC_CH_MUXPOS_PIN6_gc = (0x06<<3), /* Input pin 6 */ - ADC_CH_MUXPOS_PIN7_gc = (0x07<<3), /* Input pin 7 */ -} ADC_CH_MUXPOS_t; - -/* Internal input multiplexer selections */ -typedef enum ADC_CH_MUXINT_enum -{ - ADC_CH_MUXINT_TEMP_gc = (0x00<<3), /* Temperature Reference */ - ADC_CH_MUXINT_BANDGAP_gc = (0x01<<3), /* Bandgap Reference */ - ADC_CH_MUXINT_SCALEDVCC_gc = (0x02<<3), /* 1/10 scaled VCC */ - ADC_CH_MUXINT_DAC_gc = (0x03<<3), /* DAC output */ -} ADC_CH_MUXINT_t; - -/* Negative input multiplexer selection */ -typedef enum ADC_CH_MUXNEG_enum -{ - ADC_CH_MUXNEG_PIN0_gc = (0x00<<0), /* Input pin 0 */ - ADC_CH_MUXNEG_PIN1_gc = (0x01<<0), /* Input pin 1 */ - ADC_CH_MUXNEG_PIN2_gc = (0x02<<0), /* Input pin 2 */ - ADC_CH_MUXNEG_PIN3_gc = (0x03<<0), /* Input pin 3 */ - ADC_CH_MUXNEG_PIN4_gc = (0x04<<0), /* Input pin 4 */ - ADC_CH_MUXNEG_PIN5_gc = (0x05<<0), /* Input pin 5 */ - ADC_CH_MUXNEG_PIN6_gc = (0x06<<0), /* Input pin 6 */ - ADC_CH_MUXNEG_PIN7_gc = (0x07<<0), /* Input pin 7 */ -} ADC_CH_MUXNEG_t; - -/* Input mode */ -typedef enum ADC_CH_INPUTMODE_enum -{ - ADC_CH_INPUTMODE_INTERNAL_gc = (0x00<<0), /* Internal inputs, no gain */ - ADC_CH_INPUTMODE_SINGLEENDED_gc = (0x01<<0), /* Single-ended input, no gain */ - ADC_CH_INPUTMODE_DIFF_gc = (0x02<<0), /* Differential input, no gain */ - ADC_CH_INPUTMODE_DIFFWGAIN_gc = (0x03<<0), /* Differential input, with gain */ -} ADC_CH_INPUTMODE_t; - -/* Gain factor */ -typedef enum ADC_CH_GAIN_enum -{ - ADC_CH_GAIN_1X_gc = (0x00<<2), /* 1x gain */ - ADC_CH_GAIN_2X_gc = (0x01<<2), /* 2x gain */ - ADC_CH_GAIN_4X_gc = (0x02<<2), /* 4x gain */ - ADC_CH_GAIN_8X_gc = (0x03<<2), /* 8x gain */ - ADC_CH_GAIN_16X_gc = (0x04<<2), /* 16x gain */ - ADC_CH_GAIN_32X_gc = (0x05<<2), /* 32x gain */ - ADC_CH_GAIN_64X_gc = (0x06<<2), /* 64x gain */ -} ADC_CH_GAIN_t; - -/* Conversion result resolution */ -typedef enum ADC_RESOLUTION_enum -{ - ADC_RESOLUTION_12BIT_gc = (0x00<<1), /* 12-bit right-adjusted result */ - ADC_RESOLUTION_8BIT_gc = (0x02<<1), /* 8-bit right-adjusted result */ - ADC_RESOLUTION_LEFT12BIT_gc = (0x03<<1), /* 12-bit left-adjusted result */ -} ADC_RESOLUTION_t; - -/* Voltage reference selection */ -typedef enum ADC_REFSEL_enum -{ - ADC_REFSEL_INT1V_gc = (0x00<<4), /* Internal 1V */ - ADC_REFSEL_VCC_gc = (0x01<<4), /* Internal VCC / 1.6V */ - ADC_REFSEL_AREFA_gc = (0x02<<4), /* External reference on PORT A */ - ADC_REFSEL_AREFB_gc = (0x03<<4), /* External reference on PORT B */ -} ADC_REFSEL_t; - -/* Channel sweep selection */ -typedef enum ADC_SWEEP_enum -{ - ADC_SWEEP_0_gc = (0x00<<6), /* ADC Channel 0 */ - ADC_SWEEP_01_gc = (0x01<<6), /* ADC Channel 0,1 */ - ADC_SWEEP_012_gc = (0x02<<6), /* ADC Channel 0,1,2 */ - ADC_SWEEP_0123_gc = (0x03<<6), /* ADC Channel 0,1,2,3 */ -} ADC_SWEEP_t; - -/* Event channel input selection */ -typedef enum ADC_EVSEL_enum -{ - ADC_EVSEL_0123_gc = (0x00<<3), /* Event Channel 0,1,2,3 */ - ADC_EVSEL_1234_gc = (0x01<<3), /* Event Channel 1,2,3,4 */ - ADC_EVSEL_2345_gc = (0x02<<3), /* Event Channel 2,3,4,5 */ - ADC_EVSEL_3456_gc = (0x03<<3), /* Event Channel 3,4,5,6 */ - ADC_EVSEL_4567_gc = (0x04<<3), /* Event Channel 4,5,6,7 */ - ADC_EVSEL_567_gc = (0x05<<3), /* Event Channel 5,6,7 */ - ADC_EVSEL_67_gc = (0x06<<3), /* Event Channel 6,7 */ - ADC_EVSEL_7_gc = (0x07<<3), /* Event Channel 7 */ -} ADC_EVSEL_t; - -/* Event action selection */ -typedef enum ADC_EVACT_enum -{ - ADC_EVACT_NONE_gc = (0x00<<0), /* No event action */ - ADC_EVACT_CH0_gc = (0x01<<0), /* First event triggers channel 0 */ - ADC_EVACT_CH01_gc = (0x02<<0), /* First two events trigger channel 0,1 */ - ADC_EVACT_CH012_gc = (0x03<<0), /* First three events trigger channel 0,1,2 */ - ADC_EVACT_CH0123_gc = (0x04<<0), /* Events trigger channel 0,1,2,3 */ - ADC_EVACT_SWEEP_gc = (0x05<<0), /* First event triggers sweep */ - ADC_EVACT_SYNCHSWEEP_gc = (0x06<<0), /* First event triggers synchronized sweep */ -} ADC_EVACT_t; - -/* Interupt mode */ -typedef enum ADC_CH_INTMODE_enum -{ - ADC_CH_INTMODE_COMPLETE_gc = (0x00<<2), /* Interrupt on conversion complete */ - ADC_CH_INTMODE_BELOW_gc = (0x01<<2), /* Interrupt on result below compare value */ - ADC_CH_INTMODE_ABOVE_gc = (0x03<<2), /* Interrupt on result above compare value */ -} ADC_CH_INTMODE_t; - -/* Interrupt level */ -typedef enum ADC_CH_INTLVL_enum -{ - ADC_CH_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ - ADC_CH_INTLVL_LO_gc = (0x01<<0), /* Low level */ - ADC_CH_INTLVL_MED_gc = (0x02<<0), /* Medium level */ - ADC_CH_INTLVL_HI_gc = (0x03<<0), /* High level */ -} ADC_CH_INTLVL_t; - -/* DMA request selection */ -typedef enum ADC_DMASEL_enum -{ - ADC_DMASEL_OFF_gc = (0x00<<6), /* Combined DMA request OFF */ - ADC_DMASEL_CH01_gc = (0x01<<6), /* ADC Channel 0 or 1 */ - ADC_DMASEL_CH012_gc = (0x02<<6), /* ADC Channel 0 or 1 or 2 */ - ADC_DMASEL_CH0123_gc = (0x03<<6), /* ADC Channel 0 or 1 or 2 or 3 */ -} ADC_DMASEL_t; - -/* Clock prescaler */ -typedef enum ADC_PRESCALER_enum -{ - ADC_PRESCALER_DIV4_gc = (0x00<<0), /* Divide clock by 4 */ - ADC_PRESCALER_DIV8_gc = (0x01<<0), /* Divide clock by 8 */ - ADC_PRESCALER_DIV16_gc = (0x02<<0), /* Divide clock by 16 */ - ADC_PRESCALER_DIV32_gc = (0x03<<0), /* Divide clock by 32 */ - ADC_PRESCALER_DIV64_gc = (0x04<<0), /* Divide clock by 64 */ - ADC_PRESCALER_DIV128_gc = (0x05<<0), /* Divide clock by 128 */ - ADC_PRESCALER_DIV256_gc = (0x06<<0), /* Divide clock by 256 */ - ADC_PRESCALER_DIV512_gc = (0x07<<0), /* Divide clock by 512 */ -} ADC_PRESCALER_t; - - -/* --------------------------------------------------------------------------- -DAC - Digital/Analog Converter --------------------------------------------------------------------------- -*/ - -/* Digital-to-Analog Converter */ -typedef struct DAC_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t CTRLC; /* Control Register C */ - register8_t EVCTRL; /* Event Input Control */ - register8_t TIMCTRL; /* Timing Control */ - register8_t STATUS; /* Status */ - register8_t reserved_0x06; - register8_t reserved_0x07; - register8_t GAINCAL; /* Gain Calibration */ - register8_t OFFSETCAL; /* Offset Calibration */ - register8_t reserved_0x0A; - register8_t reserved_0x0B; - register8_t reserved_0x0C; - register8_t reserved_0x0D; - register8_t reserved_0x0E; - register8_t reserved_0x0F; - register8_t reserved_0x10; - register8_t reserved_0x11; - register8_t reserved_0x12; - register8_t reserved_0x13; - register8_t reserved_0x14; - register8_t reserved_0x15; - register8_t reserved_0x16; - register8_t reserved_0x17; - _WORDREGISTER(CH0DATA); /* Channel 0 Data */ - _WORDREGISTER(CH1DATA); /* Channel 1 Data */ -} DAC_t; - -/* Output channel selection */ -typedef enum DAC_CHSEL_enum -{ - DAC_CHSEL_SINGLE_gc = (0x00<<5), /* Single channel operation (Channel A only) */ - DAC_CHSEL_DUAL_gc = (0x02<<5), /* Dual channel operation (S/H on both channels) */ -} DAC_CHSEL_t; - -/* Reference voltage selection */ -typedef enum DAC_REFSEL_enum -{ - DAC_REFSEL_INT1V_gc = (0x00<<3), /* Internal 1V */ - DAC_REFSEL_AVCC_gc = (0x01<<3), /* Analog supply voltage */ - DAC_REFSEL_AREFA_gc = (0x02<<3), /* External reference on AREF on PORTA */ - DAC_REFSEL_AREFB_gc = (0x03<<3), /* External reference on AREF on PORTB */ -} DAC_REFSEL_t; - -/* Event channel selection */ -typedef enum DAC_EVSEL_enum -{ - DAC_EVSEL_0_gc = (0x00<<0), /* Event Channel 0 */ - DAC_EVSEL_1_gc = (0x01<<0), /* Event Channel 1 */ - DAC_EVSEL_2_gc = (0x02<<0), /* Event Channel 2 */ - DAC_EVSEL_3_gc = (0x03<<0), /* Event Channel 3 */ - DAC_EVSEL_4_gc = (0x04<<0), /* Event Channel 4 */ - DAC_EVSEL_5_gc = (0x05<<0), /* Event Channel 5 */ - DAC_EVSEL_6_gc = (0x06<<0), /* Event Channel 6 */ - DAC_EVSEL_7_gc = (0x07<<0), /* Event Channel 7 */ -} DAC_EVSEL_t; - -/* Conversion interval */ -typedef enum DAC_CONINTVAL_enum -{ - DAC_CONINTVAL_1CLK_gc = (0x00<<4), /* 1 CLK / 2 CLK in S/H mode */ - DAC_CONINTVAL_2CLK_gc = (0x01<<4), /* 2 CLK / 3 CLK in S/H mode */ - DAC_CONINTVAL_4CLK_gc = (0x02<<4), /* 4 CLK / 6 CLK in S/H mode */ - DAC_CONINTVAL_8CLK_gc = (0x03<<4), /* 8 CLK / 12 CLK in S/H mode */ - DAC_CONINTVAL_16CLK_gc = (0x04<<4), /* 16 CLK / 24 CLK in S/H mode */ - DAC_CONINTVAL_32CLK_gc = (0x05<<4), /* 32 CLK / 48 CLK in S/H mode */ - DAC_CONINTVAL_64CLK_gc = (0x06<<4), /* 64 CLK / 96 CLK in S/H mode */ - DAC_CONINTVAL_128CLK_gc = (0x07<<4), /* 128 CLK / 192 CLK in S/H mode */ -} DAC_CONINTVAL_t; - -/* Refresh rate */ -typedef enum DAC_REFRESH_enum -{ - DAC_REFRESH_16CLK_gc = (0x00<<0), /* 16 CLK */ - DAC_REFRESH_32CLK_gc = (0x01<<0), /* 32 CLK */ - DAC_REFRESH_64CLK_gc = (0x02<<0), /* 64 CLK */ - DAC_REFRESH_128CLK_gc = (0x03<<0), /* 128 CLK */ - DAC_REFRESH_256CLK_gc = (0x04<<0), /* 256 CLK */ - DAC_REFRESH_512CLK_gc = (0x05<<0), /* 512 CLK */ - DAC_REFRESH_1024CLK_gc = (0x06<<0), /* 1024 CLK */ - DAC_REFRESH_2048CLK_gc = (0x07<<0), /* 2048 CLK */ - DAC_REFRESH_4096CLK_gc = (0x08<<0), /* 4096 CLK */ - DAC_REFRESH_8192CLK_gc = (0x09<<0), /* 8192 CLK */ - DAC_REFRESH_16384CLK_gc = (0x0A<<0), /* 16384 CLK */ - DAC_REFRESH_32768CLK_gc = (0x0B<<0), /* 32768 CLK */ - DAC_REFRESH_65536CLK_gc = (0x0C<<0), /* 65536 CLK */ - DAC_REFRESH_OFF_gc = (0x0F<<0), /* Auto refresh OFF */ -} DAC_REFRESH_t; - - -/* --------------------------------------------------------------------------- -RTC32 - 32-bit Real-Time Counter --------------------------------------------------------------------------- -*/ - -/* 32-bit Real-Time Clounter */ -typedef struct RTC32_struct -{ - register8_t CTRL; /* Control Register */ - register8_t SYNCCTRL; /* Synchronization Control/Status Register */ - register8_t INTCTRL; /* Interrupt Control Register */ - register8_t INTFLAGS; /* Interrupt Flags */ - _DWORDREGISTER(CNT); /* Count Register */ - _DWORDREGISTER(PER); /* Period Register */ - _DWORDREGISTER(COMP); /* Compare Register */ -} RTC32_t; - -/* Compare Interrupt level */ -typedef enum RTC32_COMPINTLVL_enum -{ - RTC32_COMPINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ - RTC32_COMPINTLVL_LO_gc = (0x01<<2), /* Low Level */ - RTC32_COMPINTLVL_MED_gc = (0x02<<2), /* Medium Level */ - RTC32_COMPINTLVL_HI_gc = (0x03<<2), /* High Level */ -} RTC32_COMPINTLVL_t; - -/* Overflow Interrupt level */ -typedef enum RTC32_OVFINTLVL_enum -{ - RTC32_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - RTC32_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ - RTC32_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ - RTC32_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ -} RTC32_OVFINTLVL_t; - - -/* --------------------------------------------------------------------------- -EBI - External Bus Interface --------------------------------------------------------------------------- -*/ - -/* EBI Chip Select Module */ -typedef struct EBI_CS_struct -{ - register8_t CTRLA; /* Chip Select Control Register A */ - register8_t CTRLB; /* Chip Select Control Register B */ - _WORDREGISTER(BASEADDR); /* Chip Select Base Address */ -} EBI_CS_t; - -/* --------------------------------------------------------------------------- -EBI - External Bus Interface --------------------------------------------------------------------------- -*/ - -/* External Bus Interface */ -typedef struct EBI_struct -{ - register8_t CTRL; /* Control */ - register8_t SDRAMCTRLA; /* SDRAM Control Register A */ - register8_t reserved_0x02; - register8_t reserved_0x03; - _WORDREGISTER(REFRESH); /* SDRAM Refresh Period */ - _WORDREGISTER(INITDLY); /* SDRAM Initialization Delay */ - register8_t SDRAMCTRLB; /* SDRAM Control Register B */ - register8_t SDRAMCTRLC; /* SDRAM Control Register C */ - register8_t reserved_0x0A; - register8_t reserved_0x0B; - register8_t reserved_0x0C; - register8_t reserved_0x0D; - register8_t reserved_0x0E; - register8_t reserved_0x0F; - EBI_CS_t CS0; /* Chip Select 0 */ - EBI_CS_t CS1; /* Chip Select 1 */ - EBI_CS_t CS2; /* Chip Select 2 */ - EBI_CS_t CS3; /* Chip Select 3 */ -} EBI_t; - -/* Chip Select adress space */ -typedef enum EBI_CS_ASIZE_enum -{ - EBI_CS_ASIZE_256B_gc = (0x00<<2), /* 256 bytes */ - EBI_CS_ASIZE_512B_gc = (0x01<<2), /* 512 bytes */ - EBI_CS_ASIZE_1KB_gc = (0x02<<2), /* 1K bytes */ - EBI_CS_ASIZE_2KB_gc = (0x03<<2), /* 2K bytes */ - EBI_CS_ASIZE_4KB_gc = (0x04<<2), /* 4K bytes */ - EBI_CS_ASIZE_8KB_gc = (0x05<<2), /* 8K bytes */ - EBI_CS_ASIZE_16KB_gc = (0x06<<2), /* 16K bytes */ - EBI_CS_ASIZE_32KB_gc = (0x07<<2), /* 32K bytes */ - EBI_CS_ASIZE_64KB_gc = (0x08<<2), /* 64K bytes */ - EBI_CS_ASIZE_128KB_gc = (0x09<<2), /* 128K bytes */ - EBI_CS_ASIZE_256KB_gc = (0x0A<<2), /* 256K bytes */ - EBI_CS_ASIZE_512KB_gc = (0x0B<<2), /* 512K bytes */ - EBI_CS_ASIZE_1MB_gc = (0x0C<<2), /* 1M bytes */ - EBI_CS_ASIZE_2MB_gc = (0x0D<<2), /* 2M bytes */ - EBI_CS_ASIZE_4MB_gc = (0x0E<<2), /* 4M bytes */ - EBI_CS_ASIZE_8MB_gc = (0x0F<<2), /* 8M bytes */ - EBI_CS_ASIZE_16M_gc = (0x10<<2), /* 16M bytes */ -} EBI_CS_ASIZE_t; - -/* */ -typedef enum EBI_CS_SRWS_enum -{ - EBI_CS_SRWS_0CLK_gc = (0x00<<0), /* 0 cycles */ - EBI_CS_SRWS_1CLK_gc = (0x01<<0), /* 1 cycle */ - EBI_CS_SRWS_2CLK_gc = (0x02<<0), /* 2 cycles */ - EBI_CS_SRWS_3CLK_gc = (0x03<<0), /* 3 cycles */ - EBI_CS_SRWS_4CLK_gc = (0x04<<0), /* 4 cycles */ - EBI_CS_SRWS_5CLK_gc = (0x05<<0), /* 5 cycle */ - EBI_CS_SRWS_6CLK_gc = (0x06<<0), /* 6 cycles */ - EBI_CS_SRWS_7CLK_gc = (0x07<<0), /* 7 cycles */ -} EBI_CS_SRWS_t; - -/* Chip Select address mode */ -typedef enum EBI_CS_MODE_enum -{ - EBI_CS_MODE_DISABLED_gc = (0x00<<0), /* Chip Select Disabled */ - EBI_CS_MODE_SRAM_gc = (0x01<<0), /* Chip Select in SRAM mode */ - EBI_CS_MODE_LPC_gc = (0x02<<0), /* Chip Select in SRAM LPC mode */ - EBI_CS_MODE_SDRAM_gc = (0x03<<0), /* Chip Select in SDRAM mode */ -} EBI_CS_MODE_t; - -/* Chip Select SDRAM mode */ -typedef enum EBI_CS_SDMODE_enum -{ - EBI_CS_SDMODE_NORMAL_gc = (0x00<<0), /* Normal mode */ - EBI_CS_SDMODE_LOAD_gc = (0x01<<0), /* Load Mode Register command mode */ -} EBI_CS_SDMODE_t; - -/* */ -typedef enum EBI_SDDATAW_enum -{ - EBI_SDDATAW_4BIT_gc = (0x00<<6), /* 4-bit data bus */ - EBI_SDDATAW_8BIT_gc = (0x01<<6), /* 8-bit data bus */ -} EBI_SDDATAW_t; - -/* */ -typedef enum EBI_LPCMODE_enum -{ - EBI_LPCMODE_ALE1_gc = (0x00<<4), /* Data muxed with addr byte 0 */ - EBI_LPCMODE_ALE12_gc = (0x02<<4), /* Data muxed with addr byte 0 and 1 */ -} EBI_LPCMODE_t; - -/* */ -typedef enum EBI_SRMODE_enum -{ - EBI_SRMODE_ALE1_gc = (0x00<<2), /* Addr byte 0 muxed with 1 */ - EBI_SRMODE_ALE2_gc = (0x01<<2), /* Addr byte 0 muxed with 2 */ - EBI_SRMODE_ALE12_gc = (0x02<<2), /* Addr byte 0 muxed with 1 and 2 */ - EBI_SRMODE_NOALE_gc = (0x03<<2), /* No addr muxing */ -} EBI_SRMODE_t; - -/* */ -typedef enum EBI_IFMODE_enum -{ - EBI_IFMODE_DISABLED_gc = (0x00<<0), /* EBI Disabled */ - EBI_IFMODE_3PORT_gc = (0x01<<0), /* 3-port mode */ - EBI_IFMODE_4PORT_gc = (0x02<<0), /* 4-port mode */ - EBI_IFMODE_2PORT_gc = (0x03<<0), /* 2-port mode */ -} EBI_IFMODE_t; - -/* */ -typedef enum EBI_SDCOL_enum -{ - EBI_SDCOL_8BIT_gc = (0x00<<0), /* 8 column bits */ - EBI_SDCOL_9BIT_gc = (0x01<<0), /* 9 column bits */ - EBI_SDCOL_10BIT_gc = (0x02<<0), /* 10 column bits */ - EBI_SDCOL_11BIT_gc = (0x03<<0), /* 11 column bits */ -} EBI_SDCOL_t; - -/* */ -typedef enum EBI_MRDLY_enum -{ - EBI_MRDLY_0CLK_gc = (0x00<<6), /* 0 cycles */ - EBI_MRDLY_1CLK_gc = (0x01<<6), /* 1 cycle */ - EBI_MRDLY_2CLK_gc = (0x02<<6), /* 2 cycles */ - EBI_MRDLY_3CLK_gc = (0x03<<6), /* 3 cycles */ -} EBI_MRDLY_t; - -/* */ -typedef enum EBI_ROWCYCDLY_enum -{ - EBI_ROWCYCDLY_0CLK_gc = (0x00<<3), /* 0 cycles */ - EBI_ROWCYCDLY_1CLK_gc = (0x01<<3), /* 1 cycle */ - EBI_ROWCYCDLY_2CLK_gc = (0x02<<3), /* 2 cycles */ - EBI_ROWCYCDLY_3CLK_gc = (0x03<<3), /* 3 cycles */ - EBI_ROWCYCDLY_4CLK_gc = (0x04<<3), /* 4 cycles */ - EBI_ROWCYCDLY_5CLK_gc = (0x05<<3), /* 5 cycle */ - EBI_ROWCYCDLY_6CLK_gc = (0x06<<3), /* 6 cycles */ - EBI_ROWCYCDLY_7CLK_gc = (0x07<<3), /* 7 cycles */ -} EBI_ROWCYCDLY_t; - -/* */ -typedef enum EBI_RPDLY_enum -{ - EBI_RPDLY_0CLK_gc = (0x00<<0), /* 0 cycles */ - EBI_RPDLY_1CLK_gc = (0x01<<0), /* 1 cycle */ - EBI_RPDLY_2CLK_gc = (0x02<<0), /* 2 cycles */ - EBI_RPDLY_3CLK_gc = (0x03<<0), /* 3 cycles */ - EBI_RPDLY_4CLK_gc = (0x04<<0), /* 4 cycles */ - EBI_RPDLY_5CLK_gc = (0x05<<0), /* 5 cycle */ - EBI_RPDLY_6CLK_gc = (0x06<<0), /* 6 cycles */ - EBI_RPDLY_7CLK_gc = (0x07<<0), /* 7 cycles */ -} EBI_RPDLY_t; - -/* */ -typedef enum EBI_WRDLY_enum -{ - EBI_WRDLY_0CLK_gc = (0x00<<6), /* 0 cycles */ - EBI_WRDLY_1CLK_gc = (0x01<<6), /* 1 cycle */ - EBI_WRDLY_2CLK_gc = (0x02<<6), /* 2 cycles */ - EBI_WRDLY_3CLK_gc = (0x03<<6), /* 3 cycles */ -} EBI_WRDLY_t; - -/* */ -typedef enum EBI_ESRDLY_enum -{ - EBI_ESRDLY_0CLK_gc = (0x00<<3), /* 0 cycles */ - EBI_ESRDLY_1CLK_gc = (0x01<<3), /* 1 cycle */ - EBI_ESRDLY_2CLK_gc = (0x02<<3), /* 2 cycles */ - EBI_ESRDLY_3CLK_gc = (0x03<<3), /* 3 cycles */ - EBI_ESRDLY_4CLK_gc = (0x04<<3), /* 4 cycles */ - EBI_ESRDLY_5CLK_gc = (0x05<<3), /* 5 cycle */ - EBI_ESRDLY_6CLK_gc = (0x06<<3), /* 6 cycles */ - EBI_ESRDLY_7CLK_gc = (0x07<<3), /* 7 cycles */ -} EBI_ESRDLY_t; - -/* */ -typedef enum EBI_ROWCOLDLY_enum -{ - EBI_ROWCOLDLY_0CLK_gc = (0x00<<0), /* 0 cycles */ - EBI_ROWCOLDLY_1CLK_gc = (0x01<<0), /* 1 cycle */ - EBI_ROWCOLDLY_2CLK_gc = (0x02<<0), /* 2 cycles */ - EBI_ROWCOLDLY_3CLK_gc = (0x03<<0), /* 3 cycles */ - EBI_ROWCOLDLY_4CLK_gc = (0x04<<0), /* 4 cycles */ - EBI_ROWCOLDLY_5CLK_gc = (0x05<<0), /* 5 cycle */ - EBI_ROWCOLDLY_6CLK_gc = (0x06<<0), /* 6 cycles */ - EBI_ROWCOLDLY_7CLK_gc = (0x07<<0), /* 7 cycles */ -} EBI_ROWCOLDLY_t; - - -/* --------------------------------------------------------------------------- -TWI - Two-Wire Interface --------------------------------------------------------------------------- -*/ - -/* */ -typedef struct TWI_MASTER_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t CTRLC; /* Control Register C */ - register8_t STATUS; /* Status Register */ - register8_t BAUD; /* Baurd Rate Control Register */ - register8_t ADDR; /* Address Register */ - register8_t DATA; /* Data Register */ -} TWI_MASTER_t; - -/* --------------------------------------------------------------------------- -TWI - Two-Wire Interface --------------------------------------------------------------------------- -*/ - -/* */ -typedef struct TWI_SLAVE_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t STATUS; /* Status Register */ - register8_t ADDR; /* Address Register */ - register8_t DATA; /* Data Register */ - register8_t ADDRMASK; /* Address Mask Register */ -} TWI_SLAVE_t; - -/* --------------------------------------------------------------------------- -TWI - Two-Wire Interface --------------------------------------------------------------------------- -*/ - -/* Two-Wire Interface */ -typedef struct TWI_struct -{ - register8_t CTRL; /* TWI Common Control Register */ - TWI_MASTER_t MASTER; /* TWI master module */ - TWI_SLAVE_t SLAVE; /* TWI slave module */ -} TWI_t; - -/* Master Interrupt Level */ -typedef enum TWI_MASTER_INTLVL_enum -{ - TWI_MASTER_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ - TWI_MASTER_INTLVL_LO_gc = (0x01<<6), /* Low Level */ - TWI_MASTER_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ - TWI_MASTER_INTLVL_HI_gc = (0x03<<6), /* High Level */ -} TWI_MASTER_INTLVL_t; - -/* Inactive Timeout */ -typedef enum TWI_MASTER_TIMEOUT_enum -{ - TWI_MASTER_TIMEOUT_DISABLED_gc = (0x00<<2), /* Bus Timeout Disabled */ - TWI_MASTER_TIMEOUT_50US_gc = (0x01<<2), /* 50 Microseconds */ - TWI_MASTER_TIMEOUT_100US_gc = (0x02<<2), /* 100 Microseconds */ - TWI_MASTER_TIMEOUT_200US_gc = (0x03<<2), /* 200 Microseconds */ -} TWI_MASTER_TIMEOUT_t; - -/* Master Command */ -typedef enum TWI_MASTER_CMD_enum -{ - TWI_MASTER_CMD_NOACT_gc = (0x00<<0), /* No Action */ - TWI_MASTER_CMD_REPSTART_gc = (0x01<<0), /* Issue Repeated Start Condition */ - TWI_MASTER_CMD_RECVTRANS_gc = (0x02<<0), /* Receive or Transmit Data */ - TWI_MASTER_CMD_STOP_gc = (0x03<<0), /* Issue Stop Condition */ -} TWI_MASTER_CMD_t; - -/* Master Bus State */ -typedef enum TWI_MASTER_BUSSTATE_enum -{ - TWI_MASTER_BUSSTATE_UNKNOWN_gc = (0x00<<0), /* Unknown Bus State */ - TWI_MASTER_BUSSTATE_IDLE_gc = (0x01<<0), /* Bus is Idle */ - TWI_MASTER_BUSSTATE_OWNER_gc = (0x02<<0), /* This Module Controls The Bus */ - TWI_MASTER_BUSSTATE_BUSY_gc = (0x03<<0), /* The Bus is Busy */ -} TWI_MASTER_BUSSTATE_t; - -/* Slave Interrupt Level */ -typedef enum TWI_SLAVE_INTLVL_enum -{ - TWI_SLAVE_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ - TWI_SLAVE_INTLVL_LO_gc = (0x01<<6), /* Low Level */ - TWI_SLAVE_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ - TWI_SLAVE_INTLVL_HI_gc = (0x03<<6), /* High Level */ -} TWI_SLAVE_INTLVL_t; - -/* Slave Command */ -typedef enum TWI_SLAVE_CMD_enum -{ - TWI_SLAVE_CMD_NOACT_gc = (0x00<<0), /* No Action */ - TWI_SLAVE_CMD_COMPTRANS_gc = (0x02<<0), /* Used To Complete a Transaction */ - TWI_SLAVE_CMD_RESPONSE_gc = (0x03<<0), /* Used in Response to Address/Data Interrupt */ -} TWI_SLAVE_CMD_t; - - -/* --------------------------------------------------------------------------- -PORT - Port Configuration --------------------------------------------------------------------------- -*/ - -/* I/O port Configuration */ -typedef struct PORTCFG_struct -{ - register8_t MPCMASK; /* Multi-pin Configuration Mask */ - register8_t reserved_0x01; - register8_t VPCTRLA; /* Virtual Port Control Register A */ - register8_t VPCTRLB; /* Virtual Port Control Register B */ - register8_t CLKEVOUT; /* Clock and Event Out Register */ -} PORTCFG_t; - -/* --------------------------------------------------------------------------- -PORT - Port Configuration --------------------------------------------------------------------------- -*/ - -/* Virtual Port */ -typedef struct VPORT_struct -{ - register8_t DIR; /* I/O Port Data Direction */ - register8_t OUT; /* I/O Port Output */ - register8_t IN; /* I/O Port Input */ - register8_t INTFLAGS; /* Interrupt Flag Register */ -} VPORT_t; - -/* --------------------------------------------------------------------------- -PORT - Port Configuration --------------------------------------------------------------------------- -*/ - -/* I/O Ports */ -typedef struct PORT_struct -{ - register8_t DIR; /* I/O Port Data Direction */ - register8_t DIRSET; /* I/O Port Data Direction Set */ - register8_t DIRCLR; /* I/O Port Data Direction Clear */ - register8_t DIRTGL; /* I/O Port Data Direction Toggle */ - register8_t OUT; /* I/O Port Output */ - register8_t OUTSET; /* I/O Port Output Set */ - register8_t OUTCLR; /* I/O Port Output Clear */ - register8_t OUTTGL; /* I/O Port Output Toggle */ - register8_t IN; /* I/O port Input */ - register8_t INTCTRL; /* Interrupt Control Register */ - register8_t INT0MASK; /* Port Interrupt 0 Mask */ - register8_t INT1MASK; /* Port Interrupt 1 Mask */ - register8_t INTFLAGS; /* Interrupt Flag Register */ - register8_t reserved_0x0D; - register8_t reserved_0x0E; - register8_t reserved_0x0F; - register8_t PIN0CTRL; /* Pin 0 Control Register */ - register8_t PIN1CTRL; /* Pin 1 Control Register */ - register8_t PIN2CTRL; /* Pin 2 Control Register */ - register8_t PIN3CTRL; /* Pin 3 Control Register */ - register8_t PIN4CTRL; /* Pin 4 Control Register */ - register8_t PIN5CTRL; /* Pin 5 Control Register */ - register8_t PIN6CTRL; /* Pin 6 Control Register */ - register8_t PIN7CTRL; /* Pin 7 Control Register */ -} PORT_t; - -/* Virtual Port 0 Mapping */ -typedef enum PORTCFG_VP0MAP_enum -{ - PORTCFG_VP0MAP_PORTA_gc = (0x00<<0), /* Mapped To PORTA */ - PORTCFG_VP0MAP_PORTB_gc = (0x01<<0), /* Mapped To PORTB */ - PORTCFG_VP0MAP_PORTC_gc = (0x02<<0), /* Mapped To PORTC */ - PORTCFG_VP0MAP_PORTD_gc = (0x03<<0), /* Mapped To PORTD */ - PORTCFG_VP0MAP_PORTE_gc = (0x04<<0), /* Mapped To PORTE */ - PORTCFG_VP0MAP_PORTF_gc = (0x05<<0), /* Mapped To PORTF */ - PORTCFG_VP0MAP_PORTG_gc = (0x06<<0), /* Mapped To PORTG */ - PORTCFG_VP0MAP_PORTH_gc = (0x07<<0), /* Mapped To PORTH */ - PORTCFG_VP0MAP_PORTJ_gc = (0x08<<0), /* Mapped To PORTJ */ - PORTCFG_VP0MAP_PORTK_gc = (0x09<<0), /* Mapped To PORTK */ - PORTCFG_VP0MAP_PORTL_gc = (0x0A<<0), /* Mapped To PORTL */ - PORTCFG_VP0MAP_PORTM_gc = (0x0B<<0), /* Mapped To PORTM */ - PORTCFG_VP0MAP_PORTN_gc = (0x0C<<0), /* Mapped To PORTN */ - PORTCFG_VP0MAP_PORTP_gc = (0x0D<<0), /* Mapped To PORTP */ - PORTCFG_VP0MAP_PORTQ_gc = (0x0E<<0), /* Mapped To PORTQ */ - PORTCFG_VP0MAP_PORTR_gc = (0x0F<<0), /* Mapped To PORTR */ -} PORTCFG_VP0MAP_t; - -/* Virtual Port 1 Mapping */ -typedef enum PORTCFG_VP1MAP_enum -{ - PORTCFG_VP1MAP_PORTA_gc = (0x00<<4), /* Mapped To PORTA */ - PORTCFG_VP1MAP_PORTB_gc = (0x01<<4), /* Mapped To PORTB */ - PORTCFG_VP1MAP_PORTC_gc = (0x02<<4), /* Mapped To PORTC */ - PORTCFG_VP1MAP_PORTD_gc = (0x03<<4), /* Mapped To PORTD */ - PORTCFG_VP1MAP_PORTE_gc = (0x04<<4), /* Mapped To PORTE */ - PORTCFG_VP1MAP_PORTF_gc = (0x05<<4), /* Mapped To PORTF */ - PORTCFG_VP1MAP_PORTG_gc = (0x06<<4), /* Mapped To PORTG */ - PORTCFG_VP1MAP_PORTH_gc = (0x07<<4), /* Mapped To PORTH */ - PORTCFG_VP1MAP_PORTJ_gc = (0x08<<4), /* Mapped To PORTJ */ - PORTCFG_VP1MAP_PORTK_gc = (0x09<<4), /* Mapped To PORTK */ - PORTCFG_VP1MAP_PORTL_gc = (0x0A<<4), /* Mapped To PORTL */ - PORTCFG_VP1MAP_PORTM_gc = (0x0B<<4), /* Mapped To PORTM */ - PORTCFG_VP1MAP_PORTN_gc = (0x0C<<4), /* Mapped To PORTN */ - PORTCFG_VP1MAP_PORTP_gc = (0x0D<<4), /* Mapped To PORTP */ - PORTCFG_VP1MAP_PORTQ_gc = (0x0E<<4), /* Mapped To PORTQ */ - PORTCFG_VP1MAP_PORTR_gc = (0x0F<<4), /* Mapped To PORTR */ -} PORTCFG_VP1MAP_t; - -/* Virtual Port 2 Mapping */ -typedef enum PORTCFG_VP2MAP_enum -{ - PORTCFG_VP2MAP_PORTA_gc = (0x00<<0), /* Mapped To PORTA */ - PORTCFG_VP2MAP_PORTB_gc = (0x01<<0), /* Mapped To PORTB */ - PORTCFG_VP2MAP_PORTC_gc = (0x02<<0), /* Mapped To PORTC */ - PORTCFG_VP2MAP_PORTD_gc = (0x03<<0), /* Mapped To PORTD */ - PORTCFG_VP2MAP_PORTE_gc = (0x04<<0), /* Mapped To PORTE */ - PORTCFG_VP2MAP_PORTF_gc = (0x05<<0), /* Mapped To PORTF */ - PORTCFG_VP2MAP_PORTG_gc = (0x06<<0), /* Mapped To PORTG */ - PORTCFG_VP2MAP_PORTH_gc = (0x07<<0), /* Mapped To PORTH */ - PORTCFG_VP2MAP_PORTJ_gc = (0x08<<0), /* Mapped To PORTJ */ - PORTCFG_VP2MAP_PORTK_gc = (0x09<<0), /* Mapped To PORTK */ - PORTCFG_VP2MAP_PORTL_gc = (0x0A<<0), /* Mapped To PORTL */ - PORTCFG_VP2MAP_PORTM_gc = (0x0B<<0), /* Mapped To PORTM */ - PORTCFG_VP2MAP_PORTN_gc = (0x0C<<0), /* Mapped To PORTN */ - PORTCFG_VP2MAP_PORTP_gc = (0x0D<<0), /* Mapped To PORTP */ - PORTCFG_VP2MAP_PORTQ_gc = (0x0E<<0), /* Mapped To PORTQ */ - PORTCFG_VP2MAP_PORTR_gc = (0x0F<<0), /* Mapped To PORTR */ -} PORTCFG_VP2MAP_t; - -/* Virtual Port 3 Mapping */ -typedef enum PORTCFG_VP3MAP_enum -{ - PORTCFG_VP3MAP_PORTA_gc = (0x00<<4), /* Mapped To PORTA */ - PORTCFG_VP3MAP_PORTB_gc = (0x01<<4), /* Mapped To PORTB */ - PORTCFG_VP3MAP_PORTC_gc = (0x02<<4), /* Mapped To PORTC */ - PORTCFG_VP3MAP_PORTD_gc = (0x03<<4), /* Mapped To PORTD */ - PORTCFG_VP3MAP_PORTE_gc = (0x04<<4), /* Mapped To PORTE */ - PORTCFG_VP3MAP_PORTF_gc = (0x05<<4), /* Mapped To PORTF */ - PORTCFG_VP3MAP_PORTG_gc = (0x06<<4), /* Mapped To PORTG */ - PORTCFG_VP3MAP_PORTH_gc = (0x07<<4), /* Mapped To PORTH */ - PORTCFG_VP3MAP_PORTJ_gc = (0x08<<4), /* Mapped To PORTJ */ - PORTCFG_VP3MAP_PORTK_gc = (0x09<<4), /* Mapped To PORTK */ - PORTCFG_VP3MAP_PORTL_gc = (0x0A<<4), /* Mapped To PORTL */ - PORTCFG_VP3MAP_PORTM_gc = (0x0B<<4), /* Mapped To PORTM */ - PORTCFG_VP3MAP_PORTN_gc = (0x0C<<4), /* Mapped To PORTN */ - PORTCFG_VP3MAP_PORTP_gc = (0x0D<<4), /* Mapped To PORTP */ - PORTCFG_VP3MAP_PORTQ_gc = (0x0E<<4), /* Mapped To PORTQ */ - PORTCFG_VP3MAP_PORTR_gc = (0x0F<<4), /* Mapped To PORTR */ -} PORTCFG_VP3MAP_t; - -/* Clock Output Port */ -typedef enum PORTCFG_CLKOUT_enum -{ - PORTCFG_CLKOUT_OFF_gc = (0x00<<0), /* Clock Output Disabled */ - PORTCFG_CLKOUT_PC7_gc = (0x01<<0), /* Clock Output on Port C pin 7 */ - PORTCFG_CLKOUT_PD7_gc = (0x02<<0), /* Clock Output on Port D pin 7 */ - PORTCFG_CLKOUT_PE7_gc = (0x03<<0), /* Clock Output on Port E pin 7 */ -} PORTCFG_CLKOUT_t; - -/* Event Output Port */ -typedef enum PORTCFG_EVOUT_enum -{ - PORTCFG_EVOUT_OFF_gc = (0x00<<4), /* Event Output Disabled */ - PORTCFG_EVOUT_PC7_gc = (0x01<<4), /* Event Channel 7 Output on Port C pin 7 */ - PORTCFG_EVOUT_PD7_gc = (0x02<<4), /* Event Channel 7 Output on Port D pin 7 */ - PORTCFG_EVOUT_PE7_gc = (0x03<<4), /* Event Channel 7 Output on Port E pin 7 */ -} PORTCFG_EVOUT_t; - -/* Port Interrupt 0 Level */ -typedef enum PORT_INT0LVL_enum -{ - PORT_INT0LVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - PORT_INT0LVL_LO_gc = (0x01<<0), /* Low Level */ - PORT_INT0LVL_MED_gc = (0x02<<0), /* Medium Level */ - PORT_INT0LVL_HI_gc = (0x03<<0), /* High Level */ -} PORT_INT0LVL_t; - -/* Port Interrupt 1 Level */ -typedef enum PORT_INT1LVL_enum -{ - PORT_INT1LVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ - PORT_INT1LVL_LO_gc = (0x01<<2), /* Low Level */ - PORT_INT1LVL_MED_gc = (0x02<<2), /* Medium Level */ - PORT_INT1LVL_HI_gc = (0x03<<2), /* High Level */ -} PORT_INT1LVL_t; - -/* Output/Pull Configuration */ -typedef enum PORT_OPC_enum -{ - PORT_OPC_TOTEM_gc = (0x00<<3), /* Totempole */ - PORT_OPC_BUSKEEPER_gc = (0x01<<3), /* Totempole w/ Bus keeper on Input and Output */ - PORT_OPC_PULLDOWN_gc = (0x02<<3), /* Totempole w/ Pull-down on Input */ - PORT_OPC_PULLUP_gc = (0x03<<3), /* Totempole w/ Pull-up on Input */ - PORT_OPC_WIREDOR_gc = (0x04<<3), /* Wired OR */ - PORT_OPC_WIREDAND_gc = (0x05<<3), /* Wired AND */ - PORT_OPC_WIREDORPULL_gc = (0x06<<3), /* Wired OR w/ Pull-down */ - PORT_OPC_WIREDANDPULL_gc = (0x07<<3), /* Wired AND w/ Pull-up */ -} PORT_OPC_t; - -/* Input/Sense Configuration */ -typedef enum PORT_ISC_enum -{ - PORT_ISC_BOTHEDGES_gc = (0x00<<0), /* Sense Both Edges */ - PORT_ISC_RISING_gc = (0x01<<0), /* Sense Rising Edge */ - PORT_ISC_FALLING_gc = (0x02<<0), /* Sense Falling Edge */ - PORT_ISC_LEVEL_gc = (0x03<<0), /* Sense Level (Transparent For Events) */ - PORT_ISC_INPUT_DISABLE_gc = (0x07<<0), /* Disable Digital Input Buffer */ -} PORT_ISC_t; - - -/* --------------------------------------------------------------------------- -TC - 16-bit Timer/Counter With PWM --------------------------------------------------------------------------- -*/ - -/* 16-bit Timer/Counter 0 */ -typedef struct TC0_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t CTRLC; /* Control register C */ - register8_t CTRLD; /* Control Register D */ - register8_t CTRLE; /* Control Register E */ - register8_t reserved_0x05; - register8_t INTCTRLA; /* Interrupt Control Register A */ - register8_t INTCTRLB; /* Interrupt Control Register B */ - register8_t CTRLFCLR; /* Control Register F Clear */ - register8_t CTRLFSET; /* Control Register F Set */ - register8_t CTRLGCLR; /* Control Register G Clear */ - register8_t CTRLGSET; /* Control Register G Set */ - register8_t INTFLAGS; /* Interrupt Flag Register */ - register8_t reserved_0x0D; - register8_t reserved_0x0E; - register8_t TEMP; /* Temporary Register For 16-bit Access */ - register8_t reserved_0x10; - register8_t reserved_0x11; - register8_t reserved_0x12; - register8_t reserved_0x13; - register8_t reserved_0x14; - register8_t reserved_0x15; - register8_t reserved_0x16; - register8_t reserved_0x17; - register8_t reserved_0x18; - register8_t reserved_0x19; - register8_t reserved_0x1A; - register8_t reserved_0x1B; - register8_t reserved_0x1C; - register8_t reserved_0x1D; - register8_t reserved_0x1E; - register8_t reserved_0x1F; - _WORDREGISTER(CNT); /* Count */ - register8_t reserved_0x22; - register8_t reserved_0x23; - register8_t reserved_0x24; - register8_t reserved_0x25; - _WORDREGISTER(PER); /* Period */ - _WORDREGISTER(CCA); /* Compare or Capture A */ - _WORDREGISTER(CCB); /* Compare or Capture B */ - _WORDREGISTER(CCC); /* Compare or Capture C */ - _WORDREGISTER(CCD); /* Compare or Capture D */ - register8_t reserved_0x30; - register8_t reserved_0x31; - register8_t reserved_0x32; - register8_t reserved_0x33; - register8_t reserved_0x34; - register8_t reserved_0x35; - _WORDREGISTER(PERBUF); /* Period Buffer */ - _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ - _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ - _WORDREGISTER(CCCBUF); /* Compare Or Capture C Buffer */ - _WORDREGISTER(CCDBUF); /* Compare Or Capture D Buffer */ -} TC0_t; - -/* --------------------------------------------------------------------------- -TC - 16-bit Timer/Counter With PWM --------------------------------------------------------------------------- -*/ - -/* 16-bit Timer/Counter 1 */ -typedef struct TC1_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t CTRLC; /* Control register C */ - register8_t CTRLD; /* Control Register D */ - register8_t CTRLE; /* Control Register E */ - register8_t reserved_0x05; - register8_t INTCTRLA; /* Interrupt Control Register A */ - register8_t INTCTRLB; /* Interrupt Control Register B */ - register8_t CTRLFCLR; /* Control Register F Clear */ - register8_t CTRLFSET; /* Control Register F Set */ - register8_t CTRLGCLR; /* Control Register G Clear */ - register8_t CTRLGSET; /* Control Register G Set */ - register8_t INTFLAGS; /* Interrupt Flag Register */ - register8_t reserved_0x0D; - register8_t reserved_0x0E; - register8_t TEMP; /* Temporary Register For 16-bit Access */ - register8_t reserved_0x10; - register8_t reserved_0x11; - register8_t reserved_0x12; - register8_t reserved_0x13; - register8_t reserved_0x14; - register8_t reserved_0x15; - register8_t reserved_0x16; - register8_t reserved_0x17; - register8_t reserved_0x18; - register8_t reserved_0x19; - register8_t reserved_0x1A; - register8_t reserved_0x1B; - register8_t reserved_0x1C; - register8_t reserved_0x1D; - register8_t reserved_0x1E; - register8_t reserved_0x1F; - _WORDREGISTER(CNT); /* Count */ - register8_t reserved_0x22; - register8_t reserved_0x23; - register8_t reserved_0x24; - register8_t reserved_0x25; - _WORDREGISTER(PER); /* Period */ - _WORDREGISTER(CCA); /* Compare or Capture A */ - _WORDREGISTER(CCB); /* Compare or Capture B */ - register8_t reserved_0x2C; - register8_t reserved_0x2D; - register8_t reserved_0x2E; - register8_t reserved_0x2F; - register8_t reserved_0x30; - register8_t reserved_0x31; - register8_t reserved_0x32; - register8_t reserved_0x33; - register8_t reserved_0x34; - register8_t reserved_0x35; - _WORDREGISTER(PERBUF); /* Period Buffer */ - _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ - _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ -} TC1_t; - -/* --------------------------------------------------------------------------- -TC - 16-bit Timer/Counter With PWM --------------------------------------------------------------------------- -*/ - -/* Advanced Waveform Extension */ -typedef struct AWEX_struct -{ - register8_t CTRL; /* Control Register */ - register8_t reserved_0x01; - register8_t FDEMASK; /* Fault Detection Event Mask */ - register8_t FDCTRL; /* Fault Detection Control Register */ - register8_t STATUS; /* Status Register */ - register8_t reserved_0x05; - register8_t DTBOTH; /* Dead Time Both Sides */ - register8_t DTBOTHBUF; /* Dead Time Both Sides Buffer */ - register8_t DTLS; /* Dead Time Low Side */ - register8_t DTHS; /* Dead Time High Side */ - register8_t DTLSBUF; /* Dead Time Low Side Buffer */ - register8_t DTHSBUF; /* Dead Time High Side Buffer */ - register8_t OUTOVEN; /* Output Override Enable */ -} AWEX_t; - -/* --------------------------------------------------------------------------- -TC - 16-bit Timer/Counter With PWM --------------------------------------------------------------------------- -*/ - -/* High-Resolution Extension */ -typedef struct HIRES_struct -{ - register8_t CTRLA; /* Control Register */ -} HIRES_t; - -/* Clock Selection */ -typedef enum TC_CLKSEL_enum -{ - TC_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */ - TC_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */ - TC_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */ - TC_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */ - TC_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */ - TC_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */ - TC_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */ - TC_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */ - TC_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */ - TC_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */ - TC_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */ - TC_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */ - TC_CLKSEL_EVCH4_gc = (0x0C<<0), /* Event Channel 4 */ - TC_CLKSEL_EVCH5_gc = (0x0D<<0), /* Event Channel 5 */ - TC_CLKSEL_EVCH6_gc = (0x0E<<0), /* Event Channel 6 */ - TC_CLKSEL_EVCH7_gc = (0x0F<<0), /* Event Channel 7 */ -} TC_CLKSEL_t; - -/* Waveform Generation Mode */ -typedef enum TC_WGMODE_enum -{ - TC_WGMODE_NORMAL_gc = (0x00<<0), /* Normal Mode */ - TC_WGMODE_FRQ_gc = (0x01<<0), /* Frequency Generation Mode */ - TC_WGMODE_SS_gc = (0x03<<0), /* Single Slope */ - TC_WGMODE_DS_T_gc = (0x05<<0), /* Dual Slope, Update on TOP */ - TC_WGMODE_DS_TB_gc = (0x06<<0), /* Dual Slope, Update on TOP and BOTTOM */ - TC_WGMODE_DS_B_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */ -} TC_WGMODE_t; - -/* Event Action */ -typedef enum TC_EVACT_enum -{ - TC_EVACT_OFF_gc = (0x00<<5), /* No Event Action */ - TC_EVACT_CAPT_gc = (0x01<<5), /* Input Capture */ - TC_EVACT_UPDOWN_gc = (0x02<<5), /* Externally Controlled Up/Down Count */ - TC_EVACT_QDEC_gc = (0x03<<5), /* Quadrature Decode */ - TC_EVACT_RESTART_gc = (0x04<<5), /* Restart */ - TC_EVACT_FRQ_gc = (0x05<<5), /* Frequency Capture */ - TC_EVACT_FRW_gc = (0x05<<5), /* Frequency Capture (typo in earlier header file) */ - TC_EVACT_PW_gc = (0x06<<5), /* Pulse-width Capture */ -} TC_EVACT_t; - -/* Event Selection */ -typedef enum TC_EVSEL_enum -{ - TC_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ - TC_EVSEL_CH0_gc = (0x08<<0), /* Event Channel 0 */ - TC_EVSEL_CH1_gc = (0x09<<0), /* Event Channel 1 */ - TC_EVSEL_CH2_gc = (0x0A<<0), /* Event Channel 2 */ - TC_EVSEL_CH3_gc = (0x0B<<0), /* Event Channel 3 */ - TC_EVSEL_CH4_gc = (0x0C<<0), /* Event Channel 4 */ - TC_EVSEL_CH5_gc = (0x0D<<0), /* Event Channel 5 */ - TC_EVSEL_CH6_gc = (0x0E<<0), /* Event Channel 6 */ - TC_EVSEL_CH7_gc = (0x0F<<0), /* Event Channel 7 */ -} TC_EVSEL_t; - -/* Error Interrupt Level */ -typedef enum TC_ERRINTLVL_enum -{ - TC_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ - TC_ERRINTLVL_LO_gc = (0x01<<2), /* Low Level */ - TC_ERRINTLVL_MED_gc = (0x02<<2), /* Medium Level */ - TC_ERRINTLVL_HI_gc = (0x03<<2), /* High Level */ -} TC_ERRINTLVL_t; - -/* Overflow Interrupt Level */ -typedef enum TC_OVFINTLVL_enum -{ - TC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - TC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ - TC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ - TC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ -} TC_OVFINTLVL_t; - -/* Compare or Capture D Interrupt Level */ -typedef enum TC_CCDINTLVL_enum -{ - TC_CCDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ - TC_CCDINTLVL_LO_gc = (0x01<<6), /* Low Level */ - TC_CCDINTLVL_MED_gc = (0x02<<6), /* Medium Level */ - TC_CCDINTLVL_HI_gc = (0x03<<6), /* High Level */ -} TC_CCDINTLVL_t; - -/* Compare or Capture C Interrupt Level */ -typedef enum TC_CCCINTLVL_enum -{ - TC_CCCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ - TC_CCCINTLVL_LO_gc = (0x01<<4), /* Low Level */ - TC_CCCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ - TC_CCCINTLVL_HI_gc = (0x03<<4), /* High Level */ -} TC_CCCINTLVL_t; - -/* Compare or Capture B Interrupt Level */ -typedef enum TC_CCBINTLVL_enum -{ - TC_CCBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ - TC_CCBINTLVL_LO_gc = (0x01<<2), /* Low Level */ - TC_CCBINTLVL_MED_gc = (0x02<<2), /* Medium Level */ - TC_CCBINTLVL_HI_gc = (0x03<<2), /* High Level */ -} TC_CCBINTLVL_t; - -/* Compare or Capture A Interrupt Level */ -typedef enum TC_CCAINTLVL_enum -{ - TC_CCAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - TC_CCAINTLVL_LO_gc = (0x01<<0), /* Low Level */ - TC_CCAINTLVL_MED_gc = (0x02<<0), /* Medium Level */ - TC_CCAINTLVL_HI_gc = (0x03<<0), /* High Level */ -} TC_CCAINTLVL_t; - -/* Timer/Counter Command */ -typedef enum TC_CMD_enum -{ - TC_CMD_NONE_gc = (0x00<<2), /* No Command */ - TC_CMD_UPDATE_gc = (0x01<<2), /* Force Update */ - TC_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ - TC_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ -} TC_CMD_t; - -/* Fault Detect Action */ -typedef enum AWEX_FDACT_enum -{ - AWEX_FDACT_NONE_gc = (0x00<<0), /* No Fault Protection */ - AWEX_FDACT_CLEAROE_gc = (0x01<<0), /* Clear Output Enable Bits */ - AWEX_FDACT_CLEARDIR_gc = (0x03<<0), /* Clear I/O Port Direction Bits */ -} AWEX_FDACT_t; - -/* High Resolution Enable */ -typedef enum HIRES_HREN_enum -{ - HIRES_HREN_NONE_gc = (0x00<<0), /* No Fault Protection */ - HIRES_HREN_TC0_gc = (0x01<<0), /* Enable High Resolution on Timer/Counter 0 */ - HIRES_HREN_TC1_gc = (0x02<<0), /* Enable High Resolution on Timer/Counter 1 */ - HIRES_HREN_BOTH_gc = (0x03<<0), /* Enable High Resolution both Timer/Counters */ -} HIRES_HREN_t; - - -/* --------------------------------------------------------------------------- -USART - Universal Asynchronous Receiver-Transmitter --------------------------------------------------------------------------- -*/ - -/* Universal Synchronous/Asynchronous Receiver/Transmitter */ -typedef struct USART_struct -{ - register8_t DATA; /* Data Register */ - register8_t STATUS; /* Status Register */ - register8_t reserved_0x02; - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t CTRLC; /* Control Register C */ - register8_t BAUDCTRLA; /* Baud Rate Control Register A */ - register8_t BAUDCTRLB; /* Baud Rate Control Register B */ -} USART_t; - -/* Receive Complete Interrupt level */ -typedef enum USART_RXCINTLVL_enum -{ - USART_RXCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ - USART_RXCINTLVL_LO_gc = (0x01<<4), /* Low Level */ - USART_RXCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ - USART_RXCINTLVL_HI_gc = (0x03<<4), /* High Level */ -} USART_RXCINTLVL_t; - -/* Transmit Complete Interrupt level */ -typedef enum USART_TXCINTLVL_enum -{ - USART_TXCINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ - USART_TXCINTLVL_LO_gc = (0x01<<2), /* Low Level */ - USART_TXCINTLVL_MED_gc = (0x02<<2), /* Medium Level */ - USART_TXCINTLVL_HI_gc = (0x03<<2), /* High Level */ -} USART_TXCINTLVL_t; - -/* Data Register Empty Interrupt level */ -typedef enum USART_DREINTLVL_enum -{ - USART_DREINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - USART_DREINTLVL_LO_gc = (0x01<<0), /* Low Level */ - USART_DREINTLVL_MED_gc = (0x02<<0), /* Medium Level */ - USART_DREINTLVL_HI_gc = (0x03<<0), /* High Level */ -} USART_DREINTLVL_t; - -/* Character Size */ -typedef enum USART_CHSIZE_enum -{ - USART_CHSIZE_5BIT_gc = (0x00<<0), /* Character size: 5 bit */ - USART_CHSIZE_6BIT_gc = (0x01<<0), /* Character size: 6 bit */ - USART_CHSIZE_7BIT_gc = (0x02<<0), /* Character size: 7 bit */ - USART_CHSIZE_8BIT_gc = (0x03<<0), /* Character size: 8 bit */ - USART_CHSIZE_9BIT_gc = (0x07<<0), /* Character size: 9 bit */ -} USART_CHSIZE_t; - -/* Communication Mode */ -typedef enum USART_CMODE_enum -{ - USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6), /* Asynchronous Mode */ - USART_CMODE_SYNCHRONOUS_gc = (0x01<<6), /* Synchronous Mode */ - USART_CMODE_IRDA_gc = (0x02<<6), /* IrDA Mode */ - USART_CMODE_MSPI_gc = (0x03<<6), /* Master SPI Mode */ -} USART_CMODE_t; - -/* Parity Mode */ -typedef enum USART_PMODE_enum -{ - USART_PMODE_DISABLED_gc = (0x00<<4), /* No Parity */ - USART_PMODE_EVEN_gc = (0x02<<4), /* Even Parity */ - USART_PMODE_ODD_gc = (0x03<<4), /* Odd Parity */ -} USART_PMODE_t; - - -/* --------------------------------------------------------------------------- -SPI - Serial Peripheral Interface --------------------------------------------------------------------------- -*/ - -/* Serial Peripheral Interface */ -typedef struct SPI_struct -{ - register8_t CTRL; /* Control Register */ - register8_t INTCTRL; /* Interrupt Control Register */ - register8_t STATUS; /* Status Register */ - register8_t DATA; /* Data Register */ -} SPI_t; - -/* SPI Mode */ -typedef enum SPI_MODE_enum -{ - SPI_MODE_0_gc = (0x00<<2), /* SPI Mode 0 */ - SPI_MODE_1_gc = (0x01<<2), /* SPI Mode 1 */ - SPI_MODE_2_gc = (0x02<<2), /* SPI Mode 2 */ - SPI_MODE_3_gc = (0x03<<2), /* SPI Mode 3 */ -} SPI_MODE_t; - -/* Prescaler setting */ -typedef enum SPI_PRESCALER_enum -{ - SPI_PRESCALER_DIV4_gc = (0x00<<0), /* System Clock / 4 */ - SPI_PRESCALER_DIV16_gc = (0x01<<0), /* System Clock / 16 */ - SPI_PRESCALER_DIV64_gc = (0x02<<0), /* System Clock / 64 */ - SPI_PRESCALER_DIV128_gc = (0x03<<0), /* System Clock / 128 */ -} SPI_PRESCALER_t; - -/* Interrupt level */ -typedef enum SPI_INTLVL_enum -{ - SPI_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - SPI_INTLVL_LO_gc = (0x01<<0), /* Low Level */ - SPI_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ - SPI_INTLVL_HI_gc = (0x03<<0), /* High Level */ -} SPI_INTLVL_t; - - -/* --------------------------------------------------------------------------- -IRCOM - IR Communication Module --------------------------------------------------------------------------- -*/ - -/* IR Communication Module */ -typedef struct IRCOM_struct -{ - register8_t CTRL; /* Control Register */ - register8_t TXPLCTRL; /* IrDA Transmitter Pulse Length Control Register */ - register8_t RXPLCTRL; /* IrDA Receiver Pulse Length Control Register */ -} IRCOM_t; - -/* Event channel selection */ -typedef enum IRDA_EVSEL_enum -{ - IRDA_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ - IRDA_EVSEL_0_gc = (0x08<<0), /* Event Channel 0 */ - IRDA_EVSEL_1_gc = (0x09<<0), /* Event Channel 1 */ - IRDA_EVSEL_2_gc = (0x0A<<0), /* Event Channel 2 */ - IRDA_EVSEL_3_gc = (0x0B<<0), /* Event Channel 3 */ - IRDA_EVSEL_4_gc = (0x0C<<0), /* Event Channel 4 */ - IRDA_EVSEL_5_gc = (0x0D<<0), /* Event Channel 5 */ - IRDA_EVSEL_6_gc = (0x0E<<0), /* Event Channel 6 */ - IRDA_EVSEL_7_gc = (0x0F<<0), /* Event Channel 7 */ -} IRDA_EVSEL_t; - - -/* --------------------------------------------------------------------------- -AES - AES Module --------------------------------------------------------------------------- -*/ - -/* AES Module */ -typedef struct AES_struct -{ - register8_t CTRL; /* AES Control Register */ - register8_t STATUS; /* AES Status Register */ - register8_t STATE; /* AES State Register */ - register8_t KEY; /* AES Key Register */ - register8_t INTCTRL; /* AES Interrupt Control Register */ -} AES_t; - -/* Interrupt level */ -typedef enum AES_INTLVL_enum -{ - AES_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - AES_INTLVL_LO_gc = (0x01<<0), /* Low Level */ - AES_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ - AES_INTLVL_HI_gc = (0x03<<0), /* High Level */ -} AES_INTLVL_t; - - -/* --------------------------------------------------------------------------- -VBAT - VBAT Battery Backup Module --------------------------------------------------------------------------- -*/ - -/* VBAT Battery Backup Module */ -typedef struct VBAT_struct -{ - register8_t CTRL; /* Control Register */ - register8_t STATUS; /* Status Register */ - register8_t BACKUP0; /* Battery Bacup Register 0 */ - register8_t BACKUP1; /* Battery Backup Register 1 */ -} VBAT_t; - - - -/* -========================================================================== -IO Module Instances. Mapped to memory. -========================================================================== -*/ - -#define VPORT0 (*(VPORT_t *) 0x0010) /* Virtual Port 0 */ -#define VPORT1 (*(VPORT_t *) 0x0014) /* Virtual Port 1 */ -#define VPORT2 (*(VPORT_t *) 0x0018) /* Virtual Port 2 */ -#define VPORT3 (*(VPORT_t *) 0x001C) /* Virtual Port 3 */ -#define OCD (*(OCD_t *) 0x002E) /* On-Chip Debug System */ -#define CLK (*(CLK_t *) 0x0040) /* Clock System */ -#define SLEEP (*(SLEEP_t *) 0x0048) /* Sleep Controller */ -#define OSC (*(OSC_t *) 0x0050) /* Oscillator Control */ -#define DFLLRC32M (*(DFLL_t *) 0x0060) /* DFLL for 32MHz RC Oscillator */ -#define DFLLRC2M (*(DFLL_t *) 0x0068) /* DFLL for 2MHz RC Oscillator */ -#define PR (*(PR_t *) 0x0070) /* Power Reduction */ -#define RST (*(RST_t *) 0x0078) /* Reset Controller */ -#define WDT (*(WDT_t *) 0x0080) /* Watch-Dog Timer */ -#define MCU (*(MCU_t *) 0x0090) /* MCU Control */ -#define PMIC (*(PMIC_t *) 0x00A0) /* Programmable Interrupt Controller */ -#define PORTCFG (*(PORTCFG_t *) 0x00B0) /* Port Configuration */ -#define AES (*(AES_t *) 0x00C0) /* AES Crypto Module */ -#define VBAT (*(VBAT_t *) 0x00F0) /* VBAT Battery Backup Module */ -#define DMA (*(DMA_t *) 0x0100) /* DMA Controller */ -#define EVSYS (*(EVSYS_t *) 0x0180) /* Event System */ -#define NVM (*(NVM_t *) 0x01C0) /* Non Volatile Memory Controller */ -#define ADCA (*(ADC_t *) 0x0200) /* Analog to Digital Converter A */ -#define ADCB (*(ADC_t *) 0x0240) /* Analog to Digital Converter B */ -#define DACB (*(DAC_t *) 0x0320) /* Digital to Analog Converter B */ -#define ACA (*(AC_t *) 0x0380) /* Analog Comparator A */ -#define ACB (*(AC_t *) 0x0390) /* Analog Comparator B */ -#define RTC32 (*(RTC32_t *) 0x0420) /* 32-bit Real-Time Counter */ -#define TWIC (*(TWI_t *) 0x0480) /* Two-Wire Interface C */ -#define TWIE (*(TWI_t *) 0x04A0) /* Two-Wire Interface E */ -#define PORTA (*(PORT_t *) 0x0600) /* Port A */ -#define PORTB (*(PORT_t *) 0x0620) /* Port B */ -#define PORTC (*(PORT_t *) 0x0640) /* Port C */ -#define PORTD (*(PORT_t *) 0x0660) /* Port D */ -#define PORTE (*(PORT_t *) 0x0680) /* Port E */ -#define PORTF (*(PORT_t *) 0x06A0) /* Port F */ -#define PORTR (*(PORT_t *) 0x07E0) /* Port R */ -#define TCC0 (*(TC0_t *) 0x0800) /* Timer/Counter C0 */ -#define TCC1 (*(TC1_t *) 0x0840) /* Timer/Counter C1 */ -#define AWEXC (*(AWEX_t *) 0x0880) /* Advanced Waveform Extension C */ -#define HIRESC (*(HIRES_t *) 0x0890) /* High-Resolution Extension C */ -#define USARTC0 (*(USART_t *) 0x08A0) /* Universal Asynchronous Receiver-Transmitter C0 */ -#define USARTC1 (*(USART_t *) 0x08B0) /* Universal Asynchronous Receiver-Transmitter C1 */ -#define SPIC (*(SPI_t *) 0x08C0) /* Serial Peripheral Interface C */ -#define IRCOM (*(IRCOM_t *) 0x08F8) /* IR Communication Module */ -#define TCD0 (*(TC0_t *) 0x0900) /* Timer/Counter D0 */ -#define TCD1 (*(TC1_t *) 0x0940) /* Timer/Counter D1 */ -#define HIRESD (*(HIRES_t *) 0x0990) /* High-Resolution Extension D */ -#define USARTD0 (*(USART_t *) 0x09A0) /* Universal Asynchronous Receiver-Transmitter D0 */ -#define USARTD1 (*(USART_t *) 0x09B0) /* Universal Asynchronous Receiver-Transmitter D1 */ -#define SPID (*(SPI_t *) 0x09C0) /* Serial Peripheral Interface D */ -#define TCE0 (*(TC0_t *) 0x0A00) /* Timer/Counter E0 */ -#define TCE1 (*(TC1_t *) 0x0A40) /* Timer/Counter E1 */ -#define AWEXE (*(AWEX_t *) 0x0A80) /* Advanced Waveform Extension E */ -#define HIRESE (*(HIRES_t *) 0x0A90) /* High-Resolution Extension E */ -#define USARTE0 (*(USART_t *) 0x0AA0) /* Universal Asynchronous Receiver-Transmitter E0 */ -#define TCF0 (*(TC0_t *) 0x0B00) /* Timer/Counter F0 */ -#define HIRESF (*(HIRES_t *) 0x0B90) /* High-Resolution Extension F */ -#define USARTF0 (*(USART_t *) 0x0BA0) /* Universal Asynchronous Receiver-Transmitter F0 */ -#define SPIF (*(SPI_t *) 0x0BC0) /* Serial Peripheral Interface F */ - - -#endif /* !defined (__ASSEMBLER__) */ - - -/* ========== Flattened fully qualified IO register names ========== */ - -/* GPIO - General Purpose IO Registers */ -#define GPIO_GPIOR0 _SFR_MEM8(0x0000) -#define GPIO_GPIOR1 _SFR_MEM8(0x0001) -#define GPIO_GPIOR2 _SFR_MEM8(0x0002) -#define GPIO_GPIOR3 _SFR_MEM8(0x0003) -#define GPIO_GPIOR4 _SFR_MEM8(0x0004) -#define GPIO_GPIOR5 _SFR_MEM8(0x0005) -#define GPIO_GPIOR6 _SFR_MEM8(0x0006) -#define GPIO_GPIOR7 _SFR_MEM8(0x0007) -#define GPIO_GPIOR8 _SFR_MEM8(0x0008) -#define GPIO_GPIOR9 _SFR_MEM8(0x0009) -#define GPIO_GPIORA _SFR_MEM8(0x000A) -#define GPIO_GPIORB _SFR_MEM8(0x000B) -#define GPIO_GPIORC _SFR_MEM8(0x000C) -#define GPIO_GPIORD _SFR_MEM8(0x000D) -#define GPIO_GPIORE _SFR_MEM8(0x000E) -#define GPIO_GPIORF _SFR_MEM8(0x000F) - -/* Deprecated */ -#define GPIO_GPIO0 _SFR_MEM8(0x0000) -#define GPIO_GPIO1 _SFR_MEM8(0x0001) -#define GPIO_GPIO2 _SFR_MEM8(0x0002) -#define GPIO_GPIO3 _SFR_MEM8(0x0003) -#define GPIO_GPIO4 _SFR_MEM8(0x0004) -#define GPIO_GPIO5 _SFR_MEM8(0x0005) -#define GPIO_GPIO6 _SFR_MEM8(0x0006) -#define GPIO_GPIO7 _SFR_MEM8(0x0007) -#define GPIO_GPIO8 _SFR_MEM8(0x0008) -#define GPIO_GPIO9 _SFR_MEM8(0x0009) -#define GPIO_GPIOA _SFR_MEM8(0x000A) -#define GPIO_GPIOB _SFR_MEM8(0x000B) -#define GPIO_GPIOC _SFR_MEM8(0x000C) -#define GPIO_GPIOD _SFR_MEM8(0x000D) -#define GPIO_GPIOE _SFR_MEM8(0x000E) -#define GPIO_GPIOF _SFR_MEM8(0x000F) - - -/* VPORT0 - Virtual Port 0 */ -#define VPORT0_DIR _SFR_MEM8(0x0010) -#define VPORT0_OUT _SFR_MEM8(0x0011) -#define VPORT0_IN _SFR_MEM8(0x0012) -#define VPORT0_INTFLAGS _SFR_MEM8(0x0013) - -/* VPORT1 - Virtual Port 1 */ -#define VPORT1_DIR _SFR_MEM8(0x0014) -#define VPORT1_OUT _SFR_MEM8(0x0015) -#define VPORT1_IN _SFR_MEM8(0x0016) -#define VPORT1_INTFLAGS _SFR_MEM8(0x0017) - -/* VPORT2 - Virtual Port 2 */ -#define VPORT2_DIR _SFR_MEM8(0x0018) -#define VPORT2_OUT _SFR_MEM8(0x0019) -#define VPORT2_IN _SFR_MEM8(0x001A) -#define VPORT2_INTFLAGS _SFR_MEM8(0x001B) - -/* VPORT3 - Virtual Port 3 */ -#define VPORT3_DIR _SFR_MEM8(0x001C) -#define VPORT3_OUT _SFR_MEM8(0x001D) -#define VPORT3_IN _SFR_MEM8(0x001E) -#define VPORT3_INTFLAGS _SFR_MEM8(0x001F) - -/* OCD - On-Chip Debug System */ -#define OCD_OCDR0 _SFR_MEM8(0x002E) -#define OCD_OCDR1 _SFR_MEM8(0x002F) - -/* CPU - CPU Registers */ -#define CPU_CCP _SFR_MEM8(0x0034) -#define CPU_RAMPD _SFR_MEM8(0x0038) -#define CPU_RAMPX _SFR_MEM8(0x0039) -#define CPU_RAMPY _SFR_MEM8(0x003A) -#define CPU_RAMPZ _SFR_MEM8(0x003B) -#define CPU_EIND _SFR_MEM8(0x003C) -#define CPU_SPL _SFR_MEM8(0x003D) -#define CPU_SPH _SFR_MEM8(0x003E) -#define CPU_SREG _SFR_MEM8(0x003F) - -/* CLK - Clock System */ -#define CLK_CTRL _SFR_MEM8(0x0040) -#define CLK_PSCTRL _SFR_MEM8(0x0041) -#define CLK_LOCK _SFR_MEM8(0x0042) -#define CLK_RTCCTRL _SFR_MEM8(0x0043) - -/* SLEEP - Sleep Controller */ -#define SLEEP_CTRL _SFR_MEM8(0x0048) - -/* OSC - Oscillator Control */ -#define OSC_CTRL _SFR_MEM8(0x0050) -#define OSC_STATUS _SFR_MEM8(0x0051) -#define OSC_XOSCCTRL _SFR_MEM8(0x0052) -#define OSC_XOSCFAIL _SFR_MEM8(0x0053) -#define OSC_RC32KCAL _SFR_MEM8(0x0054) -#define OSC_PLLCTRL _SFR_MEM8(0x0055) -#define OSC_DFLLCTRL _SFR_MEM8(0x0056) - -/* DFLLRC32M - DFLL for 32MHz RC Oscillator */ -#define DFLLRC32M_CTRL _SFR_MEM8(0x0060) -#define DFLLRC32M_CALA _SFR_MEM8(0x0062) -#define DFLLRC32M_CALB _SFR_MEM8(0x0063) -#define DFLLRC32M_COMP0 _SFR_MEM8(0x0064) -#define DFLLRC32M_COMP1 _SFR_MEM8(0x0065) -#define DFLLRC32M_COMP2 _SFR_MEM8(0x0066) - -/* DFLLRC2M - DFLL for 2MHz RC Oscillator */ -#define DFLLRC2M_CTRL _SFR_MEM8(0x0068) -#define DFLLRC2M_CALA _SFR_MEM8(0x006A) -#define DFLLRC2M_CALB _SFR_MEM8(0x006B) -#define DFLLRC2M_COMP0 _SFR_MEM8(0x006C) -#define DFLLRC2M_COMP1 _SFR_MEM8(0x006D) -#define DFLLRC2M_COMP2 _SFR_MEM8(0x006E) - -/* PR - Power Reduction */ -#define PR_PRGEN _SFR_MEM8(0x0070) -#define PR_PRPA _SFR_MEM8(0x0071) -#define PR_PRPB _SFR_MEM8(0x0072) -#define PR_PRPC _SFR_MEM8(0x0073) -#define PR_PRPD _SFR_MEM8(0x0074) -#define PR_PRPE _SFR_MEM8(0x0075) -#define PR_PRPF _SFR_MEM8(0x0076) - -/* RST - Reset Controller */ -#define RST_STATUS _SFR_MEM8(0x0078) -#define RST_CTRL _SFR_MEM8(0x0079) - -/* WDT - Watch-Dog Timer */ -#define WDT_CTRL _SFR_MEM8(0x0080) -#define WDT_WINCTRL _SFR_MEM8(0x0081) -#define WDT_STATUS _SFR_MEM8(0x0082) - -/* MCU - MCU Control */ -#define MCU_DEVID0 _SFR_MEM8(0x0090) -#define MCU_DEVID1 _SFR_MEM8(0x0091) -#define MCU_DEVID2 _SFR_MEM8(0x0092) -#define MCU_REVID _SFR_MEM8(0x0093) -#define MCU_JTAGUID _SFR_MEM8(0x0094) -#define MCU_MCUCR _SFR_MEM8(0x0096) -#define MCU_EVSYSLOCK _SFR_MEM8(0x0098) -#define MCU_AWEXLOCK _SFR_MEM8(0x0099) - -/* PMIC - Programmable Interrupt Controller */ -#define PMIC_STATUS _SFR_MEM8(0x00A0) -#define PMIC_INTPRI _SFR_MEM8(0x00A1) -#define PMIC_CTRL _SFR_MEM8(0x00A2) - -/* PORTCFG - Port Configuration */ -#define PORTCFG_MPCMASK _SFR_MEM8(0x00B0) -#define PORTCFG_VPCTRLA _SFR_MEM8(0x00B2) -#define PORTCFG_VPCTRLB _SFR_MEM8(0x00B3) -#define PORTCFG_CLKEVOUT _SFR_MEM8(0x00B4) - -/* AES - AES Crypto Module */ -#define AES_CTRL _SFR_MEM8(0x00C0) -#define AES_STATUS _SFR_MEM8(0x00C1) -#define AES_STATE _SFR_MEM8(0x00C2) -#define AES_KEY _SFR_MEM8(0x00C3) -#define AES_INTCTRL _SFR_MEM8(0x00C4) - -/* VBAT - VBAT Battery Backup Module */ -#define VBAT_CTRL _SFR_MEM8(0x00F0) -#define VBAT_STATUS _SFR_MEM8(0x00F1) -#define VBAT_BACKUP0 _SFR_MEM8(0x00F2) -#define VBAT_BACKUP1 _SFR_MEM8(0x00F3) - -/* DMA - DMA Controller */ -#define DMA_CTRL _SFR_MEM8(0x0100) -#define DMA_INTFLAGS _SFR_MEM8(0x0103) -#define DMA_STATUS _SFR_MEM8(0x0104) -#define DMA_TEMP _SFR_MEM16(0x0106) -#define DMA_CH0_CTRLA _SFR_MEM8(0x0110) -#define DMA_CH0_CTRLB _SFR_MEM8(0x0111) -#define DMA_CH0_ADDRCTRL _SFR_MEM8(0x0112) -#define DMA_CH0_TRIGSRC _SFR_MEM8(0x0113) -#define DMA_CH0_TRFCNT _SFR_MEM16(0x0114) -#define DMA_CH0_REPCNT _SFR_MEM8(0x0116) -#define DMA_CH0_SRCADDR0 _SFR_MEM8(0x0118) -#define DMA_CH0_SRCADDR1 _SFR_MEM8(0x0119) -#define DMA_CH0_SRCADDR2 _SFR_MEM8(0x011A) -#define DMA_CH0_DESTADDR0 _SFR_MEM8(0x011C) -#define DMA_CH0_DESTADDR1 _SFR_MEM8(0x011D) -#define DMA_CH0_DESTADDR2 _SFR_MEM8(0x011E) -#define DMA_CH1_CTRLA _SFR_MEM8(0x0120) -#define DMA_CH1_CTRLB _SFR_MEM8(0x0121) -#define DMA_CH1_ADDRCTRL _SFR_MEM8(0x0122) -#define DMA_CH1_TRIGSRC _SFR_MEM8(0x0123) -#define DMA_CH1_TRFCNT _SFR_MEM16(0x0124) -#define DMA_CH1_REPCNT _SFR_MEM8(0x0126) -#define DMA_CH1_SRCADDR0 _SFR_MEM8(0x0128) -#define DMA_CH1_SRCADDR1 _SFR_MEM8(0x0129) -#define DMA_CH1_SRCADDR2 _SFR_MEM8(0x012A) -#define DMA_CH1_DESTADDR0 _SFR_MEM8(0x012C) -#define DMA_CH1_DESTADDR1 _SFR_MEM8(0x012D) -#define DMA_CH1_DESTADDR2 _SFR_MEM8(0x012E) -#define DMA_CH2_CTRLA _SFR_MEM8(0x0130) -#define DMA_CH2_CTRLB _SFR_MEM8(0x0131) -#define DMA_CH2_ADDRCTRL _SFR_MEM8(0x0132) -#define DMA_CH2_TRIGSRC _SFR_MEM8(0x0133) -#define DMA_CH2_TRFCNT _SFR_MEM16(0x0134) -#define DMA_CH2_REPCNT _SFR_MEM8(0x0136) -#define DMA_CH2_SRCADDR0 _SFR_MEM8(0x0138) -#define DMA_CH2_SRCADDR1 _SFR_MEM8(0x0139) -#define DMA_CH2_SRCADDR2 _SFR_MEM8(0x013A) -#define DMA_CH2_DESTADDR0 _SFR_MEM8(0x013C) -#define DMA_CH2_DESTADDR1 _SFR_MEM8(0x013D) -#define DMA_CH2_DESTADDR2 _SFR_MEM8(0x013E) -#define DMA_CH3_CTRLA _SFR_MEM8(0x0140) -#define DMA_CH3_CTRLB _SFR_MEM8(0x0141) -#define DMA_CH3_ADDRCTRL _SFR_MEM8(0x0142) -#define DMA_CH3_TRIGSRC _SFR_MEM8(0x0143) -#define DMA_CH3_TRFCNT _SFR_MEM16(0x0144) -#define DMA_CH3_REPCNT _SFR_MEM8(0x0146) -#define DMA_CH3_SRCADDR0 _SFR_MEM8(0x0148) -#define DMA_CH3_SRCADDR1 _SFR_MEM8(0x0149) -#define DMA_CH3_SRCADDR2 _SFR_MEM8(0x014A) -#define DMA_CH3_DESTADDR0 _SFR_MEM8(0x014C) -#define DMA_CH3_DESTADDR1 _SFR_MEM8(0x014D) -#define DMA_CH3_DESTADDR2 _SFR_MEM8(0x014E) - -/* EVSYS - Event System */ -#define EVSYS_CH0MUX _SFR_MEM8(0x0180) -#define EVSYS_CH1MUX _SFR_MEM8(0x0181) -#define EVSYS_CH2MUX _SFR_MEM8(0x0182) -#define EVSYS_CH3MUX _SFR_MEM8(0x0183) -#define EVSYS_CH4MUX _SFR_MEM8(0x0184) -#define EVSYS_CH5MUX _SFR_MEM8(0x0185) -#define EVSYS_CH6MUX _SFR_MEM8(0x0186) -#define EVSYS_CH7MUX _SFR_MEM8(0x0187) -#define EVSYS_CH0CTRL _SFR_MEM8(0x0188) -#define EVSYS_CH1CTRL _SFR_MEM8(0x0189) -#define EVSYS_CH2CTRL _SFR_MEM8(0x018A) -#define EVSYS_CH3CTRL _SFR_MEM8(0x018B) -#define EVSYS_CH4CTRL _SFR_MEM8(0x018C) -#define EVSYS_CH5CTRL _SFR_MEM8(0x018D) -#define EVSYS_CH6CTRL _SFR_MEM8(0x018E) -#define EVSYS_CH7CTRL _SFR_MEM8(0x018F) -#define EVSYS_STROBE _SFR_MEM8(0x0190) -#define EVSYS_DATA _SFR_MEM8(0x0191) - -/* NVM - Non Volatile Memory Controller */ -#define NVM_ADDR0 _SFR_MEM8(0x01C0) -#define NVM_ADDR1 _SFR_MEM8(0x01C1) -#define NVM_ADDR2 _SFR_MEM8(0x01C2) -#define NVM_DATA0 _SFR_MEM8(0x01C4) -#define NVM_DATA1 _SFR_MEM8(0x01C5) -#define NVM_DATA2 _SFR_MEM8(0x01C6) -#define NVM_CMD _SFR_MEM8(0x01CA) -#define NVM_CTRLA _SFR_MEM8(0x01CB) -#define NVM_CTRLB _SFR_MEM8(0x01CC) -#define NVM_INTCTRL _SFR_MEM8(0x01CD) -#define NVM_STATUS _SFR_MEM8(0x01CF) -#define NVM_LOCKBITS _SFR_MEM8(0x01D0) - -/* ADCA - Analog to Digital Converter A */ -#define ADCA_CTRLA _SFR_MEM8(0x0200) -#define ADCA_CTRLB _SFR_MEM8(0x0201) -#define ADCA_REFCTRL _SFR_MEM8(0x0202) -#define ADCA_EVCTRL _SFR_MEM8(0x0203) -#define ADCA_PRESCALER _SFR_MEM8(0x0204) -#define ADCA_INTFLAGS _SFR_MEM8(0x0206) -#define ADCA_CAL _SFR_MEM16(0x020C) -#define ADCA_CH0RES _SFR_MEM16(0x0210) -#define ADCA_CH1RES _SFR_MEM16(0x0212) -#define ADCA_CH2RES _SFR_MEM16(0x0214) -#define ADCA_CH3RES _SFR_MEM16(0x0216) -#define ADCA_CMP _SFR_MEM16(0x0218) -#define ADCA_CH0_CTRL _SFR_MEM8(0x0220) -#define ADCA_CH0_MUXCTRL _SFR_MEM8(0x0221) -#define ADCA_CH0_INTCTRL _SFR_MEM8(0x0222) -#define ADCA_CH0_INTFLAGS _SFR_MEM8(0x0223) -#define ADCA_CH0_RES _SFR_MEM16(0x0224) -#define ADCA_CH1_CTRL _SFR_MEM8(0x0228) -#define ADCA_CH1_MUXCTRL _SFR_MEM8(0x0229) -#define ADCA_CH1_INTCTRL _SFR_MEM8(0x022A) -#define ADCA_CH1_INTFLAGS _SFR_MEM8(0x022B) -#define ADCA_CH1_RES _SFR_MEM16(0x022C) -#define ADCA_CH2_CTRL _SFR_MEM8(0x0230) -#define ADCA_CH2_MUXCTRL _SFR_MEM8(0x0231) -#define ADCA_CH2_INTCTRL _SFR_MEM8(0x0232) -#define ADCA_CH2_INTFLAGS _SFR_MEM8(0x0233) -#define ADCA_CH2_RES _SFR_MEM16(0x0234) -#define ADCA_CH3_CTRL _SFR_MEM8(0x0238) -#define ADCA_CH3_MUXCTRL _SFR_MEM8(0x0239) -#define ADCA_CH3_INTCTRL _SFR_MEM8(0x023A) -#define ADCA_CH3_INTFLAGS _SFR_MEM8(0x023B) -#define ADCA_CH3_RES _SFR_MEM16(0x023C) - -/* ADCB - Analog to Digital Converter B */ -#define ADCB_CTRLA _SFR_MEM8(0x0240) -#define ADCB_CTRLB _SFR_MEM8(0x0241) -#define ADCB_REFCTRL _SFR_MEM8(0x0242) -#define ADCB_EVCTRL _SFR_MEM8(0x0243) -#define ADCB_PRESCALER _SFR_MEM8(0x0244) -#define ADCB_INTFLAGS _SFR_MEM8(0x0246) -#define ADCB_CAL _SFR_MEM16(0x024C) -#define ADCB_CH0RES _SFR_MEM16(0x0250) -#define ADCB_CH1RES _SFR_MEM16(0x0252) -#define ADCB_CH2RES _SFR_MEM16(0x0254) -#define ADCB_CH3RES _SFR_MEM16(0x0256) -#define ADCB_CMP _SFR_MEM16(0x0258) -#define ADCB_CH0_CTRL _SFR_MEM8(0x0260) -#define ADCB_CH0_MUXCTRL _SFR_MEM8(0x0261) -#define ADCB_CH0_INTCTRL _SFR_MEM8(0x0262) -#define ADCB_CH0_INTFLAGS _SFR_MEM8(0x0263) -#define ADCB_CH0_RES _SFR_MEM16(0x0264) -#define ADCB_CH1_CTRL _SFR_MEM8(0x0268) -#define ADCB_CH1_MUXCTRL _SFR_MEM8(0x0269) -#define ADCB_CH1_INTCTRL _SFR_MEM8(0x026A) -#define ADCB_CH1_INTFLAGS _SFR_MEM8(0x026B) -#define ADCB_CH1_RES _SFR_MEM16(0x026C) -#define ADCB_CH2_CTRL _SFR_MEM8(0x0270) -#define ADCB_CH2_MUXCTRL _SFR_MEM8(0x0271) -#define ADCB_CH2_INTCTRL _SFR_MEM8(0x0272) -#define ADCB_CH2_INTFLAGS _SFR_MEM8(0x0273) -#define ADCB_CH2_RES _SFR_MEM16(0x0274) -#define ADCB_CH3_CTRL _SFR_MEM8(0x0278) -#define ADCB_CH3_MUXCTRL _SFR_MEM8(0x0279) -#define ADCB_CH3_INTCTRL _SFR_MEM8(0x027A) -#define ADCB_CH3_INTFLAGS _SFR_MEM8(0x027B) -#define ADCB_CH3_RES _SFR_MEM16(0x027C) - -/* DACB - Digital to Analog Converter B */ -#define DACB_CTRLA _SFR_MEM8(0x0320) -#define DACB_CTRLB _SFR_MEM8(0x0321) -#define DACB_CTRLC _SFR_MEM8(0x0322) -#define DACB_EVCTRL _SFR_MEM8(0x0323) -#define DACB_TIMCTRL _SFR_MEM8(0x0324) -#define DACB_STATUS _SFR_MEM8(0x0325) -#define DACB_GAINCAL _SFR_MEM8(0x0328) -#define DACB_OFFSETCAL _SFR_MEM8(0x0329) -#define DACB_CH0DATA _SFR_MEM16(0x0338) -#define DACB_CH1DATA _SFR_MEM16(0x033A) - -/* ACA - Analog Comparator A */ -#define ACA_AC0CTRL _SFR_MEM8(0x0380) -#define ACA_AC1CTRL _SFR_MEM8(0x0381) -#define ACA_AC0MUXCTRL _SFR_MEM8(0x0382) -#define ACA_AC1MUXCTRL _SFR_MEM8(0x0383) -#define ACA_CTRLA _SFR_MEM8(0x0384) -#define ACA_CTRLB _SFR_MEM8(0x0385) -#define ACA_WINCTRL _SFR_MEM8(0x0386) -#define ACA_STATUS _SFR_MEM8(0x0387) - -/* ACB - Analog Comparator B */ -#define ACB_AC0CTRL _SFR_MEM8(0x0390) -#define ACB_AC1CTRL _SFR_MEM8(0x0391) -#define ACB_AC0MUXCTRL _SFR_MEM8(0x0392) -#define ACB_AC1MUXCTRL _SFR_MEM8(0x0393) -#define ACB_CTRLA _SFR_MEM8(0x0394) -#define ACB_CTRLB _SFR_MEM8(0x0395) -#define ACB_WINCTRL _SFR_MEM8(0x0396) -#define ACB_STATUS _SFR_MEM8(0x0397) - -/* RTC32 - 32-bit Real-Time Counter */ -#define RTC32_CTRL _SFR_MEM8(0x0420) -#define RTC32_SYNCCTRL _SFR_MEM8(0x0421) -#define RTC32_INTCTRL _SFR_MEM8(0x0422) -#define RTC32_INTFLAGS _SFR_MEM8(0x0423) - -/* TWIC - Two-Wire Interface C */ -#define TWIC_CTRL _SFR_MEM8(0x0480) -#define TWIC_MASTER_CTRLA _SFR_MEM8(0x0481) -#define TWIC_MASTER_CTRLB _SFR_MEM8(0x0482) -#define TWIC_MASTER_CTRLC _SFR_MEM8(0x0483) -#define TWIC_MASTER_STATUS _SFR_MEM8(0x0484) -#define TWIC_MASTER_BAUD _SFR_MEM8(0x0485) -#define TWIC_MASTER_ADDR _SFR_MEM8(0x0486) -#define TWIC_MASTER_DATA _SFR_MEM8(0x0487) -#define TWIC_SLAVE_CTRLA _SFR_MEM8(0x0488) -#define TWIC_SLAVE_CTRLB _SFR_MEM8(0x0489) -#define TWIC_SLAVE_STATUS _SFR_MEM8(0x048A) -#define TWIC_SLAVE_ADDR _SFR_MEM8(0x048B) -#define TWIC_SLAVE_DATA _SFR_MEM8(0x048C) -#define TWIC_SLAVE_ADDRMASK _SFR_MEM8(0x048D) - -/* TWIE - Two-Wire Interface E */ -#define TWIE_CTRL _SFR_MEM8(0x04A0) -#define TWIE_MASTER_CTRLA _SFR_MEM8(0x04A1) -#define TWIE_MASTER_CTRLB _SFR_MEM8(0x04A2) -#define TWIE_MASTER_CTRLC _SFR_MEM8(0x04A3) -#define TWIE_MASTER_STATUS _SFR_MEM8(0x04A4) -#define TWIE_MASTER_BAUD _SFR_MEM8(0x04A5) -#define TWIE_MASTER_ADDR _SFR_MEM8(0x04A6) -#define TWIE_MASTER_DATA _SFR_MEM8(0x04A7) -#define TWIE_SLAVE_CTRLA _SFR_MEM8(0x04A8) -#define TWIE_SLAVE_CTRLB _SFR_MEM8(0x04A9) -#define TWIE_SLAVE_STATUS _SFR_MEM8(0x04AA) -#define TWIE_SLAVE_ADDR _SFR_MEM8(0x04AB) -#define TWIE_SLAVE_DATA _SFR_MEM8(0x04AC) -#define TWIE_SLAVE_ADDRMASK _SFR_MEM8(0x04AD) - -/* PORTA - Port A */ -#define PORTA_DIR _SFR_MEM8(0x0600) -#define PORTA_DIRSET _SFR_MEM8(0x0601) -#define PORTA_DIRCLR _SFR_MEM8(0x0602) -#define PORTA_DIRTGL _SFR_MEM8(0x0603) -#define PORTA_OUT _SFR_MEM8(0x0604) -#define PORTA_OUTSET _SFR_MEM8(0x0605) -#define PORTA_OUTCLR _SFR_MEM8(0x0606) -#define PORTA_OUTTGL _SFR_MEM8(0x0607) -#define PORTA_IN _SFR_MEM8(0x0608) -#define PORTA_INTCTRL _SFR_MEM8(0x0609) -#define PORTA_INT0MASK _SFR_MEM8(0x060A) -#define PORTA_INT1MASK _SFR_MEM8(0x060B) -#define PORTA_INTFLAGS _SFR_MEM8(0x060C) -#define PORTA_PIN0CTRL _SFR_MEM8(0x0610) -#define PORTA_PIN1CTRL _SFR_MEM8(0x0611) -#define PORTA_PIN2CTRL _SFR_MEM8(0x0612) -#define PORTA_PIN3CTRL _SFR_MEM8(0x0613) -#define PORTA_PIN4CTRL _SFR_MEM8(0x0614) -#define PORTA_PIN5CTRL _SFR_MEM8(0x0615) -#define PORTA_PIN6CTRL _SFR_MEM8(0x0616) -#define PORTA_PIN7CTRL _SFR_MEM8(0x0617) - -/* PORTB - Port B */ -#define PORTB_DIR _SFR_MEM8(0x0620) -#define PORTB_DIRSET _SFR_MEM8(0x0621) -#define PORTB_DIRCLR _SFR_MEM8(0x0622) -#define PORTB_DIRTGL _SFR_MEM8(0x0623) -#define PORTB_OUT _SFR_MEM8(0x0624) -#define PORTB_OUTSET _SFR_MEM8(0x0625) -#define PORTB_OUTCLR _SFR_MEM8(0x0626) -#define PORTB_OUTTGL _SFR_MEM8(0x0627) -#define PORTB_IN _SFR_MEM8(0x0628) -#define PORTB_INTCTRL _SFR_MEM8(0x0629) -#define PORTB_INT0MASK _SFR_MEM8(0x062A) -#define PORTB_INT1MASK _SFR_MEM8(0x062B) -#define PORTB_INTFLAGS _SFR_MEM8(0x062C) -#define PORTB_PIN0CTRL _SFR_MEM8(0x0630) -#define PORTB_PIN1CTRL _SFR_MEM8(0x0631) -#define PORTB_PIN2CTRL _SFR_MEM8(0x0632) -#define PORTB_PIN3CTRL _SFR_MEM8(0x0633) -#define PORTB_PIN4CTRL _SFR_MEM8(0x0634) -#define PORTB_PIN5CTRL _SFR_MEM8(0x0635) -#define PORTB_PIN6CTRL _SFR_MEM8(0x0636) -#define PORTB_PIN7CTRL _SFR_MEM8(0x0637) - -/* PORTC - Port C */ -#define PORTC_DIR _SFR_MEM8(0x0640) -#define PORTC_DIRSET _SFR_MEM8(0x0641) -#define PORTC_DIRCLR _SFR_MEM8(0x0642) -#define PORTC_DIRTGL _SFR_MEM8(0x0643) -#define PORTC_OUT _SFR_MEM8(0x0644) -#define PORTC_OUTSET _SFR_MEM8(0x0645) -#define PORTC_OUTCLR _SFR_MEM8(0x0646) -#define PORTC_OUTTGL _SFR_MEM8(0x0647) -#define PORTC_IN _SFR_MEM8(0x0648) -#define PORTC_INTCTRL _SFR_MEM8(0x0649) -#define PORTC_INT0MASK _SFR_MEM8(0x064A) -#define PORTC_INT1MASK _SFR_MEM8(0x064B) -#define PORTC_INTFLAGS _SFR_MEM8(0x064C) -#define PORTC_PIN0CTRL _SFR_MEM8(0x0650) -#define PORTC_PIN1CTRL _SFR_MEM8(0x0651) -#define PORTC_PIN2CTRL _SFR_MEM8(0x0652) -#define PORTC_PIN3CTRL _SFR_MEM8(0x0653) -#define PORTC_PIN4CTRL _SFR_MEM8(0x0654) -#define PORTC_PIN5CTRL _SFR_MEM8(0x0655) -#define PORTC_PIN6CTRL _SFR_MEM8(0x0656) -#define PORTC_PIN7CTRL _SFR_MEM8(0x0657) - -/* PORTD - Port D */ -#define PORTD_DIR _SFR_MEM8(0x0660) -#define PORTD_DIRSET _SFR_MEM8(0x0661) -#define PORTD_DIRCLR _SFR_MEM8(0x0662) -#define PORTD_DIRTGL _SFR_MEM8(0x0663) -#define PORTD_OUT _SFR_MEM8(0x0664) -#define PORTD_OUTSET _SFR_MEM8(0x0665) -#define PORTD_OUTCLR _SFR_MEM8(0x0666) -#define PORTD_OUTTGL _SFR_MEM8(0x0667) -#define PORTD_IN _SFR_MEM8(0x0668) -#define PORTD_INTCTRL _SFR_MEM8(0x0669) -#define PORTD_INT0MASK _SFR_MEM8(0x066A) -#define PORTD_INT1MASK _SFR_MEM8(0x066B) -#define PORTD_INTFLAGS _SFR_MEM8(0x066C) -#define PORTD_PIN0CTRL _SFR_MEM8(0x0670) -#define PORTD_PIN1CTRL _SFR_MEM8(0x0671) -#define PORTD_PIN2CTRL _SFR_MEM8(0x0672) -#define PORTD_PIN3CTRL _SFR_MEM8(0x0673) -#define PORTD_PIN4CTRL _SFR_MEM8(0x0674) -#define PORTD_PIN5CTRL _SFR_MEM8(0x0675) -#define PORTD_PIN6CTRL _SFR_MEM8(0x0676) -#define PORTD_PIN7CTRL _SFR_MEM8(0x0677) - -/* PORTE - Port E */ -#define PORTE_DIR _SFR_MEM8(0x0680) -#define PORTE_DIRSET _SFR_MEM8(0x0681) -#define PORTE_DIRCLR _SFR_MEM8(0x0682) -#define PORTE_DIRTGL _SFR_MEM8(0x0683) -#define PORTE_OUT _SFR_MEM8(0x0684) -#define PORTE_OUTSET _SFR_MEM8(0x0685) -#define PORTE_OUTCLR _SFR_MEM8(0x0686) -#define PORTE_OUTTGL _SFR_MEM8(0x0687) -#define PORTE_IN _SFR_MEM8(0x0688) -#define PORTE_INTCTRL _SFR_MEM8(0x0689) -#define PORTE_INT0MASK _SFR_MEM8(0x068A) -#define PORTE_INT1MASK _SFR_MEM8(0x068B) -#define PORTE_INTFLAGS _SFR_MEM8(0x068C) -#define PORTE_PIN0CTRL _SFR_MEM8(0x0690) -#define PORTE_PIN1CTRL _SFR_MEM8(0x0691) -#define PORTE_PIN2CTRL _SFR_MEM8(0x0692) -#define PORTE_PIN3CTRL _SFR_MEM8(0x0693) -#define PORTE_PIN4CTRL _SFR_MEM8(0x0694) -#define PORTE_PIN5CTRL _SFR_MEM8(0x0695) -#define PORTE_PIN6CTRL _SFR_MEM8(0x0696) -#define PORTE_PIN7CTRL _SFR_MEM8(0x0697) - -/* PORTF - Port F */ -#define PORTF_DIR _SFR_MEM8(0x06A0) -#define PORTF_DIRSET _SFR_MEM8(0x06A1) -#define PORTF_DIRCLR _SFR_MEM8(0x06A2) -#define PORTF_DIRTGL _SFR_MEM8(0x06A3) -#define PORTF_OUT _SFR_MEM8(0x06A4) -#define PORTF_OUTSET _SFR_MEM8(0x06A5) -#define PORTF_OUTCLR _SFR_MEM8(0x06A6) -#define PORTF_OUTTGL _SFR_MEM8(0x06A7) -#define PORTF_IN _SFR_MEM8(0x06A8) -#define PORTF_INTCTRL _SFR_MEM8(0x06A9) -#define PORTF_INT0MASK _SFR_MEM8(0x06AA) -#define PORTF_INT1MASK _SFR_MEM8(0x06AB) -#define PORTF_INTFLAGS _SFR_MEM8(0x06AC) -#define PORTF_PIN0CTRL _SFR_MEM8(0x06B0) -#define PORTF_PIN1CTRL _SFR_MEM8(0x06B1) -#define PORTF_PIN2CTRL _SFR_MEM8(0x06B2) -#define PORTF_PIN3CTRL _SFR_MEM8(0x06B3) -#define PORTF_PIN4CTRL _SFR_MEM8(0x06B4) -#define PORTF_PIN5CTRL _SFR_MEM8(0x06B5) -#define PORTF_PIN6CTRL _SFR_MEM8(0x06B6) -#define PORTF_PIN7CTRL _SFR_MEM8(0x06B7) - -/* PORTR - Port R */ -#define PORTR_DIR _SFR_MEM8(0x07E0) -#define PORTR_DIRSET _SFR_MEM8(0x07E1) -#define PORTR_DIRCLR _SFR_MEM8(0x07E2) -#define PORTR_DIRTGL _SFR_MEM8(0x07E3) -#define PORTR_OUT _SFR_MEM8(0x07E4) -#define PORTR_OUTSET _SFR_MEM8(0x07E5) -#define PORTR_OUTCLR _SFR_MEM8(0x07E6) -#define PORTR_OUTTGL _SFR_MEM8(0x07E7) -#define PORTR_IN _SFR_MEM8(0x07E8) -#define PORTR_INTCTRL _SFR_MEM8(0x07E9) -#define PORTR_INT0MASK _SFR_MEM8(0x07EA) -#define PORTR_INT1MASK _SFR_MEM8(0x07EB) -#define PORTR_INTFLAGS _SFR_MEM8(0x07EC) -#define PORTR_PIN0CTRL _SFR_MEM8(0x07F0) -#define PORTR_PIN1CTRL _SFR_MEM8(0x07F1) -#define PORTR_PIN2CTRL _SFR_MEM8(0x07F2) -#define PORTR_PIN3CTRL _SFR_MEM8(0x07F3) -#define PORTR_PIN4CTRL _SFR_MEM8(0x07F4) -#define PORTR_PIN5CTRL _SFR_MEM8(0x07F5) -#define PORTR_PIN6CTRL _SFR_MEM8(0x07F6) -#define PORTR_PIN7CTRL _SFR_MEM8(0x07F7) - -/* TCC0 - Timer/Counter C0 */ -#define TCC0_CTRLA _SFR_MEM8(0x0800) -#define TCC0_CTRLB _SFR_MEM8(0x0801) -#define TCC0_CTRLC _SFR_MEM8(0x0802) -#define TCC0_CTRLD _SFR_MEM8(0x0803) -#define TCC0_CTRLE _SFR_MEM8(0x0804) -#define TCC0_INTCTRLA _SFR_MEM8(0x0806) -#define TCC0_INTCTRLB _SFR_MEM8(0x0807) -#define TCC0_CTRLFCLR _SFR_MEM8(0x0808) -#define TCC0_CTRLFSET _SFR_MEM8(0x0809) -#define TCC0_CTRLGCLR _SFR_MEM8(0x080A) -#define TCC0_CTRLGSET _SFR_MEM8(0x080B) -#define TCC0_INTFLAGS _SFR_MEM8(0x080C) -#define TCC0_TEMP _SFR_MEM8(0x080F) -#define TCC0_CNT _SFR_MEM16(0x0820) -#define TCC0_PER _SFR_MEM16(0x0826) -#define TCC0_CCA _SFR_MEM16(0x0828) -#define TCC0_CCB _SFR_MEM16(0x082A) -#define TCC0_CCC _SFR_MEM16(0x082C) -#define TCC0_CCD _SFR_MEM16(0x082E) -#define TCC0_PERBUF _SFR_MEM16(0x0836) -#define TCC0_CCABUF _SFR_MEM16(0x0838) -#define TCC0_CCBBUF _SFR_MEM16(0x083A) -#define TCC0_CCCBUF _SFR_MEM16(0x083C) -#define TCC0_CCDBUF _SFR_MEM16(0x083E) - -/* TCC1 - Timer/Counter C1 */ -#define TCC1_CTRLA _SFR_MEM8(0x0840) -#define TCC1_CTRLB _SFR_MEM8(0x0841) -#define TCC1_CTRLC _SFR_MEM8(0x0842) -#define TCC1_CTRLD _SFR_MEM8(0x0843) -#define TCC1_CTRLE _SFR_MEM8(0x0844) -#define TCC1_INTCTRLA _SFR_MEM8(0x0846) -#define TCC1_INTCTRLB _SFR_MEM8(0x0847) -#define TCC1_CTRLFCLR _SFR_MEM8(0x0848) -#define TCC1_CTRLFSET _SFR_MEM8(0x0849) -#define TCC1_CTRLGCLR _SFR_MEM8(0x084A) -#define TCC1_CTRLGSET _SFR_MEM8(0x084B) -#define TCC1_INTFLAGS _SFR_MEM8(0x084C) -#define TCC1_TEMP _SFR_MEM8(0x084F) -#define TCC1_CNT _SFR_MEM16(0x0860) -#define TCC1_PER _SFR_MEM16(0x0866) -#define TCC1_CCA _SFR_MEM16(0x0868) -#define TCC1_CCB _SFR_MEM16(0x086A) -#define TCC1_PERBUF _SFR_MEM16(0x0876) -#define TCC1_CCABUF _SFR_MEM16(0x0878) -#define TCC1_CCBBUF _SFR_MEM16(0x087A) - -/* AWEXC - Advanced Waveform Extension C */ -#define AWEXC_CTRL _SFR_MEM8(0x0880) -#define AWEXC_FDEMASK _SFR_MEM8(0x0882) -#define AWEXC_FDCTRL _SFR_MEM8(0x0883) -#define AWEXC_STATUS _SFR_MEM8(0x0884) -#define AWEXC_DTBOTH _SFR_MEM8(0x0886) -#define AWEXC_DTBOTHBUF _SFR_MEM8(0x0887) -#define AWEXC_DTLS _SFR_MEM8(0x0888) -#define AWEXC_DTHS _SFR_MEM8(0x0889) -#define AWEXC_DTLSBUF _SFR_MEM8(0x088A) -#define AWEXC_DTHSBUF _SFR_MEM8(0x088B) -#define AWEXC_OUTOVEN _SFR_MEM8(0x088C) - -/* HIRESC - High-Resolution Extension C */ -#define HIRESC_CTRLA _SFR_MEM8(0x0890) - -/* USARTC0 - Universal Asynchronous Receiver-Transmitter C0 */ -#define USARTC0_DATA _SFR_MEM8(0x08A0) -#define USARTC0_STATUS _SFR_MEM8(0x08A1) -#define USARTC0_CTRLA _SFR_MEM8(0x08A3) -#define USARTC0_CTRLB _SFR_MEM8(0x08A4) -#define USARTC0_CTRLC _SFR_MEM8(0x08A5) -#define USARTC0_BAUDCTRLA _SFR_MEM8(0x08A6) -#define USARTC0_BAUDCTRLB _SFR_MEM8(0x08A7) - -/* USARTC1 - Universal Asynchronous Receiver-Transmitter C1 */ -#define USARTC1_DATA _SFR_MEM8(0x08B0) -#define USARTC1_STATUS _SFR_MEM8(0x08B1) -#define USARTC1_CTRLA _SFR_MEM8(0x08B3) -#define USARTC1_CTRLB _SFR_MEM8(0x08B4) -#define USARTC1_CTRLC _SFR_MEM8(0x08B5) -#define USARTC1_BAUDCTRLA _SFR_MEM8(0x08B6) -#define USARTC1_BAUDCTRLB _SFR_MEM8(0x08B7) - -/* SPIC - Serial Peripheral Interface C */ -#define SPIC_CTRL _SFR_MEM8(0x08C0) -#define SPIC_INTCTRL _SFR_MEM8(0x08C1) -#define SPIC_STATUS _SFR_MEM8(0x08C2) -#define SPIC_DATA _SFR_MEM8(0x08C3) - -/* IRCOM - IR Communication Module */ -#define IRCOM_CTRL _SFR_MEM8(0x08F8) -#define IRCOM_TXPLCTRL _SFR_MEM8(0x08F9) -#define IRCOM_RXPLCTRL _SFR_MEM8(0x08FA) - -/* TCD0 - Timer/Counter D0 */ -#define TCD0_CTRLA _SFR_MEM8(0x0900) -#define TCD0_CTRLB _SFR_MEM8(0x0901) -#define TCD0_CTRLC _SFR_MEM8(0x0902) -#define TCD0_CTRLD _SFR_MEM8(0x0903) -#define TCD0_CTRLE _SFR_MEM8(0x0904) -#define TCD0_INTCTRLA _SFR_MEM8(0x0906) -#define TCD0_INTCTRLB _SFR_MEM8(0x0907) -#define TCD0_CTRLFCLR _SFR_MEM8(0x0908) -#define TCD0_CTRLFSET _SFR_MEM8(0x0909) -#define TCD0_CTRLGCLR _SFR_MEM8(0x090A) -#define TCD0_CTRLGSET _SFR_MEM8(0x090B) -#define TCD0_INTFLAGS _SFR_MEM8(0x090C) -#define TCD0_TEMP _SFR_MEM8(0x090F) -#define TCD0_CNT _SFR_MEM16(0x0920) -#define TCD0_PER _SFR_MEM16(0x0926) -#define TCD0_CCA _SFR_MEM16(0x0928) -#define TCD0_CCB _SFR_MEM16(0x092A) -#define TCD0_CCC _SFR_MEM16(0x092C) -#define TCD0_CCD _SFR_MEM16(0x092E) -#define TCD0_PERBUF _SFR_MEM16(0x0936) -#define TCD0_CCABUF _SFR_MEM16(0x0938) -#define TCD0_CCBBUF _SFR_MEM16(0x093A) -#define TCD0_CCCBUF _SFR_MEM16(0x093C) -#define TCD0_CCDBUF _SFR_MEM16(0x093E) - -/* TCD1 - Timer/Counter D1 */ -#define TCD1_CTRLA _SFR_MEM8(0x0940) -#define TCD1_CTRLB _SFR_MEM8(0x0941) -#define TCD1_CTRLC _SFR_MEM8(0x0942) -#define TCD1_CTRLD _SFR_MEM8(0x0943) -#define TCD1_CTRLE _SFR_MEM8(0x0944) -#define TCD1_INTCTRLA _SFR_MEM8(0x0946) -#define TCD1_INTCTRLB _SFR_MEM8(0x0947) -#define TCD1_CTRLFCLR _SFR_MEM8(0x0948) -#define TCD1_CTRLFSET _SFR_MEM8(0x0949) -#define TCD1_CTRLGCLR _SFR_MEM8(0x094A) -#define TCD1_CTRLGSET _SFR_MEM8(0x094B) -#define TCD1_INTFLAGS _SFR_MEM8(0x094C) -#define TCD1_TEMP _SFR_MEM8(0x094F) -#define TCD1_CNT _SFR_MEM16(0x0960) -#define TCD1_PER _SFR_MEM16(0x0966) -#define TCD1_CCA _SFR_MEM16(0x0968) -#define TCD1_CCB _SFR_MEM16(0x096A) -#define TCD1_PERBUF _SFR_MEM16(0x0976) -#define TCD1_CCABUF _SFR_MEM16(0x0978) -#define TCD1_CCBBUF _SFR_MEM16(0x097A) - -/* HIRESD - High-Resolution Extension D */ -#define HIRESD_CTRLA _SFR_MEM8(0x0990) - -/* USARTD0 - Universal Asynchronous Receiver-Transmitter D0 */ -#define USARTD0_DATA _SFR_MEM8(0x09A0) -#define USARTD0_STATUS _SFR_MEM8(0x09A1) -#define USARTD0_CTRLA _SFR_MEM8(0x09A3) -#define USARTD0_CTRLB _SFR_MEM8(0x09A4) -#define USARTD0_CTRLC _SFR_MEM8(0x09A5) -#define USARTD0_BAUDCTRLA _SFR_MEM8(0x09A6) -#define USARTD0_BAUDCTRLB _SFR_MEM8(0x09A7) - -/* USARTD1 - Universal Asynchronous Receiver-Transmitter D1 */ -#define USARTD1_DATA _SFR_MEM8(0x09B0) -#define USARTD1_STATUS _SFR_MEM8(0x09B1) -#define USARTD1_CTRLA _SFR_MEM8(0x09B3) -#define USARTD1_CTRLB _SFR_MEM8(0x09B4) -#define USARTD1_CTRLC _SFR_MEM8(0x09B5) -#define USARTD1_BAUDCTRLA _SFR_MEM8(0x09B6) -#define USARTD1_BAUDCTRLB _SFR_MEM8(0x09B7) - -/* SPID - Serial Peripheral Interface D */ -#define SPID_CTRL _SFR_MEM8(0x09C0) -#define SPID_INTCTRL _SFR_MEM8(0x09C1) -#define SPID_STATUS _SFR_MEM8(0x09C2) -#define SPID_DATA _SFR_MEM8(0x09C3) - -/* TCE0 - Timer/Counter E0 */ -#define TCE0_CTRLA _SFR_MEM8(0x0A00) -#define TCE0_CTRLB _SFR_MEM8(0x0A01) -#define TCE0_CTRLC _SFR_MEM8(0x0A02) -#define TCE0_CTRLD _SFR_MEM8(0x0A03) -#define TCE0_CTRLE _SFR_MEM8(0x0A04) -#define TCE0_INTCTRLA _SFR_MEM8(0x0A06) -#define TCE0_INTCTRLB _SFR_MEM8(0x0A07) -#define TCE0_CTRLFCLR _SFR_MEM8(0x0A08) -#define TCE0_CTRLFSET _SFR_MEM8(0x0A09) -#define TCE0_CTRLGCLR _SFR_MEM8(0x0A0A) -#define TCE0_CTRLGSET _SFR_MEM8(0x0A0B) -#define TCE0_INTFLAGS _SFR_MEM8(0x0A0C) -#define TCE0_TEMP _SFR_MEM8(0x0A0F) -#define TCE0_CNT _SFR_MEM16(0x0A20) -#define TCE0_PER _SFR_MEM16(0x0A26) -#define TCE0_CCA _SFR_MEM16(0x0A28) -#define TCE0_CCB _SFR_MEM16(0x0A2A) -#define TCE0_CCC _SFR_MEM16(0x0A2C) -#define TCE0_CCD _SFR_MEM16(0x0A2E) -#define TCE0_PERBUF _SFR_MEM16(0x0A36) -#define TCE0_CCABUF _SFR_MEM16(0x0A38) -#define TCE0_CCBBUF _SFR_MEM16(0x0A3A) -#define TCE0_CCCBUF _SFR_MEM16(0x0A3C) -#define TCE0_CCDBUF _SFR_MEM16(0x0A3E) - -/* TCE1 - Timer/Counter E1 */ -#define TCE1_CTRLA _SFR_MEM8(0x0A40) -#define TCE1_CTRLB _SFR_MEM8(0x0A41) -#define TCE1_CTRLC _SFR_MEM8(0x0A42) -#define TCE1_CTRLD _SFR_MEM8(0x0A43) -#define TCE1_CTRLE _SFR_MEM8(0x0A44) -#define TCE1_INTCTRLA _SFR_MEM8(0x0A46) -#define TCE1_INTCTRLB _SFR_MEM8(0x0A47) -#define TCE1_CTRLFCLR _SFR_MEM8(0x0A48) -#define TCE1_CTRLFSET _SFR_MEM8(0x0A49) -#define TCE1_CTRLGCLR _SFR_MEM8(0x0A4A) -#define TCE1_CTRLGSET _SFR_MEM8(0x0A4B) -#define TCE1_INTFLAGS _SFR_MEM8(0x0A4C) -#define TCE1_TEMP _SFR_MEM8(0x0A4F) -#define TCE1_CNT _SFR_MEM16(0x0A60) -#define TCE1_PER _SFR_MEM16(0x0A66) -#define TCE1_CCA _SFR_MEM16(0x0A68) -#define TCE1_CCB _SFR_MEM16(0x0A6A) -#define TCE1_PERBUF _SFR_MEM16(0x0A76) -#define TCE1_CCABUF _SFR_MEM16(0x0A78) -#define TCE1_CCBBUF _SFR_MEM16(0x0A7A) - -/* AWEXE - Advanced Waveform Extension E */ -#define AWEXE_CTRL _SFR_MEM8(0x0A80) -#define AWEXE_FDEMASK _SFR_MEM8(0x0A82) -#define AWEXE_FDCTRL _SFR_MEM8(0x0A83) -#define AWEXE_STATUS _SFR_MEM8(0x0A84) -#define AWEXE_DTBOTH _SFR_MEM8(0x0A86) -#define AWEXE_DTBOTHBUF _SFR_MEM8(0x0A87) -#define AWEXE_DTLS _SFR_MEM8(0x0A88) -#define AWEXE_DTHS _SFR_MEM8(0x0A89) -#define AWEXE_DTLSBUF _SFR_MEM8(0x0A8A) -#define AWEXE_DTHSBUF _SFR_MEM8(0x0A8B) -#define AWEXE_OUTOVEN _SFR_MEM8(0x0A8C) - -/* HIRESE - High-Resolution Extension E */ -#define HIRESE_CTRLA _SFR_MEM8(0x0A90) - -/* USARTE0 - Universal Asynchronous Receiver-Transmitter E0 */ -#define USARTE0_DATA _SFR_MEM8(0x0AA0) -#define USARTE0_STATUS _SFR_MEM8(0x0AA1) -#define USARTE0_CTRLA _SFR_MEM8(0x0AA3) -#define USARTE0_CTRLB _SFR_MEM8(0x0AA4) -#define USARTE0_CTRLC _SFR_MEM8(0x0AA5) -#define USARTE0_BAUDCTRLA _SFR_MEM8(0x0AA6) -#define USARTE0_BAUDCTRLB _SFR_MEM8(0x0AA7) - -/* TCF0 - Timer/Counter F0 */ -#define TCF0_CTRLA _SFR_MEM8(0x0B00) -#define TCF0_CTRLB _SFR_MEM8(0x0B01) -#define TCF0_CTRLC _SFR_MEM8(0x0B02) -#define TCF0_CTRLD _SFR_MEM8(0x0B03) -#define TCF0_CTRLE _SFR_MEM8(0x0B04) -#define TCF0_INTCTRLA _SFR_MEM8(0x0B06) -#define TCF0_INTCTRLB _SFR_MEM8(0x0B07) -#define TCF0_CTRLFCLR _SFR_MEM8(0x0B08) -#define TCF0_CTRLFSET _SFR_MEM8(0x0B09) -#define TCF0_CTRLGCLR _SFR_MEM8(0x0B0A) -#define TCF0_CTRLGSET _SFR_MEM8(0x0B0B) -#define TCF0_INTFLAGS _SFR_MEM8(0x0B0C) -#define TCF0_TEMP _SFR_MEM8(0x0B0F) -#define TCF0_CNT _SFR_MEM16(0x0B20) -#define TCF0_PER _SFR_MEM16(0x0B26) -#define TCF0_CCA _SFR_MEM16(0x0B28) -#define TCF0_CCB _SFR_MEM16(0x0B2A) -#define TCF0_CCC _SFR_MEM16(0x0B2C) -#define TCF0_CCD _SFR_MEM16(0x0B2E) -#define TCF0_PERBUF _SFR_MEM16(0x0B36) -#define TCF0_CCABUF _SFR_MEM16(0x0B38) -#define TCF0_CCBBUF _SFR_MEM16(0x0B3A) -#define TCF0_CCCBUF _SFR_MEM16(0x0B3C) -#define TCF0_CCDBUF _SFR_MEM16(0x0B3E) - -/* HIRESF - High-Resolution Extension F */ -#define HIRESF_CTRLA _SFR_MEM8(0x0B90) - -/* USARTF0 - Universal Asynchronous Receiver-Transmitter F0 */ -#define USARTF0_DATA _SFR_MEM8(0x0BA0) -#define USARTF0_STATUS _SFR_MEM8(0x0BA1) -#define USARTF0_CTRLA _SFR_MEM8(0x0BA3) -#define USARTF0_CTRLB _SFR_MEM8(0x0BA4) -#define USARTF0_CTRLC _SFR_MEM8(0x0BA5) -#define USARTF0_BAUDCTRLA _SFR_MEM8(0x0BA6) -#define USARTF0_BAUDCTRLB _SFR_MEM8(0x0BA7) - -/* SPIF - Serial Peripheral Interface F */ -#define SPIF_CTRL _SFR_MEM8(0x0BC0) -#define SPIF_INTCTRL _SFR_MEM8(0x0BC1) -#define SPIF_STATUS _SFR_MEM8(0x0BC2) -#define SPIF_DATA _SFR_MEM8(0x0BC3) - - - -/*================== Bitfield Definitions ================== */ - -/* XOCD - On-Chip Debug System */ -/* OCD.OCDR1 bit masks and bit positions */ -#define OCD_OCDRD_bm 0x01 /* OCDR Dirty bit mask. */ -#define OCD_OCDRD_bp 0 /* OCDR Dirty bit position. */ - - -/* CPU - CPU */ -/* CPU.CCP bit masks and bit positions */ -#define CPU_CCP_gm 0xFF /* CCP signature group mask. */ -#define CPU_CCP_gp 0 /* CCP signature group position. */ -#define CPU_CCP0_bm (1<<0) /* CCP signature bit 0 mask. */ -#define CPU_CCP0_bp 0 /* CCP signature bit 0 position. */ -#define CPU_CCP1_bm (1<<1) /* CCP signature bit 1 mask. */ -#define CPU_CCP1_bp 1 /* CCP signature bit 1 position. */ -#define CPU_CCP2_bm (1<<2) /* CCP signature bit 2 mask. */ -#define CPU_CCP2_bp 2 /* CCP signature bit 2 position. */ -#define CPU_CCP3_bm (1<<3) /* CCP signature bit 3 mask. */ -#define CPU_CCP3_bp 3 /* CCP signature bit 3 position. */ -#define CPU_CCP4_bm (1<<4) /* CCP signature bit 4 mask. */ -#define CPU_CCP4_bp 4 /* CCP signature bit 4 position. */ -#define CPU_CCP5_bm (1<<5) /* CCP signature bit 5 mask. */ -#define CPU_CCP5_bp 5 /* CCP signature bit 5 position. */ -#define CPU_CCP6_bm (1<<6) /* CCP signature bit 6 mask. */ -#define CPU_CCP6_bp 6 /* CCP signature bit 6 position. */ -#define CPU_CCP7_bm (1<<7) /* CCP signature bit 7 mask. */ -#define CPU_CCP7_bp 7 /* CCP signature bit 7 position. */ - - -/* CPU.SREG bit masks and bit positions */ -#define CPU_I_bm 0x80 /* Global Interrupt Enable Flag bit mask. */ -#define CPU_I_bp 7 /* Global Interrupt Enable Flag bit position. */ - -#define CPU_T_bm 0x40 /* Transfer Bit bit mask. */ -#define CPU_T_bp 6 /* Transfer Bit bit position. */ - -#define CPU_H_bm 0x20 /* Half Carry Flag bit mask. */ -#define CPU_H_bp 5 /* Half Carry Flag bit position. */ - -#define CPU_S_bm 0x10 /* N Exclusive Or V Flag bit mask. */ -#define CPU_S_bp 4 /* N Exclusive Or V Flag bit position. */ - -#define CPU_V_bm 0x08 /* Two's Complement Overflow Flag bit mask. */ -#define CPU_V_bp 3 /* Two's Complement Overflow Flag bit position. */ - -#define CPU_N_bm 0x04 /* Negative Flag bit mask. */ -#define CPU_N_bp 2 /* Negative Flag bit position. */ - -#define CPU_Z_bm 0x02 /* Zero Flag bit mask. */ -#define CPU_Z_bp 1 /* Zero Flag bit position. */ - -#define CPU_C_bm 0x01 /* Carry Flag bit mask. */ -#define CPU_C_bp 0 /* Carry Flag bit position. */ - - -/* CLK - Clock System */ -/* CLK.CTRL bit masks and bit positions */ -#define CLK_SCLKSEL_gm 0x07 /* System Clock Selection group mask. */ -#define CLK_SCLKSEL_gp 0 /* System Clock Selection group position. */ -#define CLK_SCLKSEL0_bm (1<<0) /* System Clock Selection bit 0 mask. */ -#define CLK_SCLKSEL0_bp 0 /* System Clock Selection bit 0 position. */ -#define CLK_SCLKSEL1_bm (1<<1) /* System Clock Selection bit 1 mask. */ -#define CLK_SCLKSEL1_bp 1 /* System Clock Selection bit 1 position. */ -#define CLK_SCLKSEL2_bm (1<<2) /* System Clock Selection bit 2 mask. */ -#define CLK_SCLKSEL2_bp 2 /* System Clock Selection bit 2 position. */ - - -/* CLK.PSCTRL bit masks and bit positions */ -#define CLK_PSADIV_gm 0x7C /* Prescaler A Division Factor group mask. */ -#define CLK_PSADIV_gp 2 /* Prescaler A Division Factor group position. */ -#define CLK_PSADIV0_bm (1<<2) /* Prescaler A Division Factor bit 0 mask. */ -#define CLK_PSADIV0_bp 2 /* Prescaler A Division Factor bit 0 position. */ -#define CLK_PSADIV1_bm (1<<3) /* Prescaler A Division Factor bit 1 mask. */ -#define CLK_PSADIV1_bp 3 /* Prescaler A Division Factor bit 1 position. */ -#define CLK_PSADIV2_bm (1<<4) /* Prescaler A Division Factor bit 2 mask. */ -#define CLK_PSADIV2_bp 4 /* Prescaler A Division Factor bit 2 position. */ -#define CLK_PSADIV3_bm (1<<5) /* Prescaler A Division Factor bit 3 mask. */ -#define CLK_PSADIV3_bp 5 /* Prescaler A Division Factor bit 3 position. */ -#define CLK_PSADIV4_bm (1<<6) /* Prescaler A Division Factor bit 4 mask. */ -#define CLK_PSADIV4_bp 6 /* Prescaler A Division Factor bit 4 position. */ - -#define CLK_PSBCDIV_gm 0x03 /* Prescaler B and C Division factor group mask. */ -#define CLK_PSBCDIV_gp 0 /* Prescaler B and C Division factor group position. */ -#define CLK_PSBCDIV0_bm (1<<0) /* Prescaler B and C Division factor bit 0 mask. */ -#define CLK_PSBCDIV0_bp 0 /* Prescaler B and C Division factor bit 0 position. */ -#define CLK_PSBCDIV1_bm (1<<1) /* Prescaler B and C Division factor bit 1 mask. */ -#define CLK_PSBCDIV1_bp 1 /* Prescaler B and C Division factor bit 1 position. */ - - -/* CLK.LOCK bit masks and bit positions */ -#define CLK_LOCK_bm 0x01 /* Clock System Lock bit mask. */ -#define CLK_LOCK_bp 0 /* Clock System Lock bit position. */ - - -/* CLK.RTCCTRL bit masks and bit positions */ -#define CLK_RTCSRC_gm 0x0E /* Clock Source group mask. */ -#define CLK_RTCSRC_gp 1 /* Clock Source group position. */ -#define CLK_RTCSRC0_bm (1<<1) /* Clock Source bit 0 mask. */ -#define CLK_RTCSRC0_bp 1 /* Clock Source bit 0 position. */ -#define CLK_RTCSRC1_bm (1<<2) /* Clock Source bit 1 mask. */ -#define CLK_RTCSRC1_bp 2 /* Clock Source bit 1 position. */ -#define CLK_RTCSRC2_bm (1<<3) /* Clock Source bit 2 mask. */ -#define CLK_RTCSRC2_bp 3 /* Clock Source bit 2 position. */ - -#define CLK_RTCEN_bm 0x01 /* RTC Clock Source Enable bit mask. */ -#define CLK_RTCEN_bp 0 /* RTC Clock Source Enable bit position. */ - - -/* PR.PRGEN bit masks and bit positions */ -#define PR_AES_bm 0x10 /* AES bit mask. */ -#define PR_AES_bp 4 /* AES bit position. */ - -#define PR_EBI_bm 0x08 /* External Bus Interface bit mask. */ -#define PR_EBI_bp 3 /* External Bus Interface bit position. */ - -#define PR_RTC_bm 0x04 /* Real-time Counter bit mask. */ -#define PR_RTC_bp 2 /* Real-time Counter bit position. */ - -#define PR_EVSYS_bm 0x02 /* Event System bit mask. */ -#define PR_EVSYS_bp 1 /* Event System bit position. */ - -#define PR_DMA_bm 0x01 /* DMA-Controller bit mask. */ -#define PR_DMA_bp 0 /* DMA-Controller bit position. */ - - -/* PR.PRPA bit masks and bit positions */ -#define PR_DAC_bm 0x04 /* Port A DAC bit mask. */ -#define PR_DAC_bp 2 /* Port A DAC bit position. */ - -#define PR_ADC_bm 0x02 /* Port A ADC bit mask. */ -#define PR_ADC_bp 1 /* Port A ADC bit position. */ - -#define PR_AC_bm 0x01 /* Port A Analog Comparator bit mask. */ -#define PR_AC_bp 0 /* Port A Analog Comparator bit position. */ - - -/* PR.PRPB bit masks and bit positions */ -/* PR_DAC_bm Predefined. */ -/* PR_DAC_bp Predefined. */ - -/* PR_ADC_bm Predefined. */ -/* PR_ADC_bp Predefined. */ - -/* PR_AC_bm Predefined. */ -/* PR_AC_bp Predefined. */ - - -/* PR.PRPC bit masks and bit positions */ -#define PR_TWI_bm 0x40 /* Port C Two-wire Interface bit mask. */ -#define PR_TWI_bp 6 /* Port C Two-wire Interface bit position. */ - -#define PR_USART1_bm 0x20 /* Port C USART1 bit mask. */ -#define PR_USART1_bp 5 /* Port C USART1 bit position. */ - -#define PR_USART0_bm 0x10 /* Port C USART0 bit mask. */ -#define PR_USART0_bp 4 /* Port C USART0 bit position. */ - -#define PR_SPI_bm 0x08 /* Port C SPI bit mask. */ -#define PR_SPI_bp 3 /* Port C SPI bit position. */ - -#define PR_HIRES_bm 0x04 /* Port C AWEX bit mask. */ -#define PR_HIRES_bp 2 /* Port C AWEX bit position. */ - -#define PR_TC1_bm 0x02 /* Port C Timer/Counter1 bit mask. */ -#define PR_TC1_bp 1 /* Port C Timer/Counter1 bit position. */ - -#define PR_TC0_bm 0x01 /* Port C Timer/Counter0 bit mask. */ -#define PR_TC0_bp 0 /* Port C Timer/Counter0 bit position. */ - - -/* PR.PRPD bit masks and bit positions */ -/* PR_TWI_bm Predefined. */ -/* PR_TWI_bp Predefined. */ - -/* PR_USART1_bm Predefined. */ -/* PR_USART1_bp Predefined. */ - -/* PR_USART0_bm Predefined. */ -/* PR_USART0_bp Predefined. */ - -/* PR_SPI_bm Predefined. */ -/* PR_SPI_bp Predefined. */ - -/* PR_HIRES_bm Predefined. */ -/* PR_HIRES_bp Predefined. */ - -/* PR_TC1_bm Predefined. */ -/* PR_TC1_bp Predefined. */ - -/* PR_TC0_bm Predefined. */ -/* PR_TC0_bp Predefined. */ - - -/* PR.PRPE bit masks and bit positions */ -/* PR_TWI_bm Predefined. */ -/* PR_TWI_bp Predefined. */ - -/* PR_USART1_bm Predefined. */ -/* PR_USART1_bp Predefined. */ - -/* PR_USART0_bm Predefined. */ -/* PR_USART0_bp Predefined. */ - -/* PR_SPI_bm Predefined. */ -/* PR_SPI_bp Predefined. */ - -/* PR_HIRES_bm Predefined. */ -/* PR_HIRES_bp Predefined. */ - -/* PR_TC1_bm Predefined. */ -/* PR_TC1_bp Predefined. */ - -/* PR_TC0_bm Predefined. */ -/* PR_TC0_bp Predefined. */ - - -/* PR.PRPF bit masks and bit positions */ -/* PR_TWI_bm Predefined. */ -/* PR_TWI_bp Predefined. */ - -/* PR_USART1_bm Predefined. */ -/* PR_USART1_bp Predefined. */ - -/* PR_USART0_bm Predefined. */ -/* PR_USART0_bp Predefined. */ - -/* PR_SPI_bm Predefined. */ -/* PR_SPI_bp Predefined. */ - -/* PR_HIRES_bm Predefined. */ -/* PR_HIRES_bp Predefined. */ - -/* PR_TC1_bm Predefined. */ -/* PR_TC1_bp Predefined. */ - -/* PR_TC0_bm Predefined. */ -/* PR_TC0_bp Predefined. */ - - -/* SLEEP - Sleep Controller */ -/* SLEEP.CTRL bit masks and bit positions */ -#define SLEEP_SMODE_gm 0x0E /* Sleep Mode group mask. */ -#define SLEEP_SMODE_gp 1 /* Sleep Mode group position. */ -#define SLEEP_SMODE0_bm (1<<1) /* Sleep Mode bit 0 mask. */ -#define SLEEP_SMODE0_bp 1 /* Sleep Mode bit 0 position. */ -#define SLEEP_SMODE1_bm (1<<2) /* Sleep Mode bit 1 mask. */ -#define SLEEP_SMODE1_bp 2 /* Sleep Mode bit 1 position. */ -#define SLEEP_SMODE2_bm (1<<3) /* Sleep Mode bit 2 mask. */ -#define SLEEP_SMODE2_bp 3 /* Sleep Mode bit 2 position. */ - -#define SLEEP_SEN_bm 0x01 /* Sleep Enable bit mask. */ -#define SLEEP_SEN_bp 0 /* Sleep Enable bit position. */ - - -/* OSC - Oscillator */ -/* OSC.CTRL bit masks and bit positions */ -#define OSC_PLLEN_bm 0x10 /* PLL Enable bit mask. */ -#define OSC_PLLEN_bp 4 /* PLL Enable bit position. */ - -#define OSC_XOSCEN_bm 0x08 /* External Oscillator Enable bit mask. */ -#define OSC_XOSCEN_bp 3 /* External Oscillator Enable bit position. */ - -#define OSC_RC32KEN_bm 0x04 /* Internal 32kHz RC Oscillator Enable bit mask. */ -#define OSC_RC32KEN_bp 2 /* Internal 32kHz RC Oscillator Enable bit position. */ - -#define OSC_RC32MEN_bm 0x02 /* Internal 32MHz RC Oscillator Enable bit mask. */ -#define OSC_RC32MEN_bp 1 /* Internal 32MHz RC Oscillator Enable bit position. */ - -#define OSC_RC2MEN_bm 0x01 /* Internal 2MHz RC Oscillator Enable bit mask. */ -#define OSC_RC2MEN_bp 0 /* Internal 2MHz RC Oscillator Enable bit position. */ - - -/* OSC.STATUS bit masks and bit positions */ -#define OSC_PLLRDY_bm 0x10 /* PLL Ready bit mask. */ -#define OSC_PLLRDY_bp 4 /* PLL Ready bit position. */ - -#define OSC_XOSCRDY_bm 0x08 /* External Oscillator Ready bit mask. */ -#define OSC_XOSCRDY_bp 3 /* External Oscillator Ready bit position. */ - -#define OSC_RC32KRDY_bm 0x04 /* Internal 32kHz RC Oscillator Ready bit mask. */ -#define OSC_RC32KRDY_bp 2 /* Internal 32kHz RC Oscillator Ready bit position. */ - -#define OSC_RC32MRDY_bm 0x02 /* Internal 32MHz RC Oscillator Ready bit mask. */ -#define OSC_RC32MRDY_bp 1 /* Internal 32MHz RC Oscillator Ready bit position. */ - -#define OSC_RC2MRDY_bm 0x01 /* Internal 2MHz RC Oscillator Ready bit mask. */ -#define OSC_RC2MRDY_bp 0 /* Internal 2MHz RC Oscillator Ready bit position. */ - - -/* OSC.XOSCCTRL bit masks and bit positions */ -#define OSC_FRQRANGE_gm 0xC0 /* Frequency Range group mask. */ -#define OSC_FRQRANGE_gp 6 /* Frequency Range group position. */ -#define OSC_FRQRANGE0_bm (1<<6) /* Frequency Range bit 0 mask. */ -#define OSC_FRQRANGE0_bp 6 /* Frequency Range bit 0 position. */ -#define OSC_FRQRANGE1_bm (1<<7) /* Frequency Range bit 1 mask. */ -#define OSC_FRQRANGE1_bp 7 /* Frequency Range bit 1 position. */ - -#define OSC_X32KLPM_bm 0x20 /* 32kHz XTAL OSC Low-power Mode bit mask. */ -#define OSC_X32KLPM_bp 5 /* 32kHz XTAL OSC Low-power Mode bit position. */ - -#define OSC_XOSCSEL_gm 0x0F /* External Oscillator Selection and Startup Time group mask. */ -#define OSC_XOSCSEL_gp 0 /* External Oscillator Selection and Startup Time group position. */ -#define OSC_XOSCSEL0_bm (1<<0) /* External Oscillator Selection and Startup Time bit 0 mask. */ -#define OSC_XOSCSEL0_bp 0 /* External Oscillator Selection and Startup Time bit 0 position. */ -#define OSC_XOSCSEL1_bm (1<<1) /* External Oscillator Selection and Startup Time bit 1 mask. */ -#define OSC_XOSCSEL1_bp 1 /* External Oscillator Selection and Startup Time bit 1 position. */ -#define OSC_XOSCSEL2_bm (1<<2) /* External Oscillator Selection and Startup Time bit 2 mask. */ -#define OSC_XOSCSEL2_bp 2 /* External Oscillator Selection and Startup Time bit 2 position. */ -#define OSC_XOSCSEL3_bm (1<<3) /* External Oscillator Selection and Startup Time bit 3 mask. */ -#define OSC_XOSCSEL3_bp 3 /* External Oscillator Selection and Startup Time bit 3 position. */ - - -/* OSC.XOSCFAIL bit masks and bit positions */ -#define OSC_XOSCFDIF_bm 0x02 /* Failure Detection Interrupt Flag bit mask. */ -#define OSC_XOSCFDIF_bp 1 /* Failure Detection Interrupt Flag bit position. */ - -#define OSC_XOSCFDEN_bm 0x01 /* Failure Detection Enable bit mask. */ -#define OSC_XOSCFDEN_bp 0 /* Failure Detection Enable bit position. */ - - -/* OSC.PLLCTRL bit masks and bit positions */ -#define OSC_PLLSRC_gm 0xC0 /* Clock Source group mask. */ -#define OSC_PLLSRC_gp 6 /* Clock Source group position. */ -#define OSC_PLLSRC0_bm (1<<6) /* Clock Source bit 0 mask. */ -#define OSC_PLLSRC0_bp 6 /* Clock Source bit 0 position. */ -#define OSC_PLLSRC1_bm (1<<7) /* Clock Source bit 1 mask. */ -#define OSC_PLLSRC1_bp 7 /* Clock Source bit 1 position. */ - -#define OSC_PLLFAC_gm 0x1F /* Multiplication Factor group mask. */ -#define OSC_PLLFAC_gp 0 /* Multiplication Factor group position. */ -#define OSC_PLLFAC0_bm (1<<0) /* Multiplication Factor bit 0 mask. */ -#define OSC_PLLFAC0_bp 0 /* Multiplication Factor bit 0 position. */ -#define OSC_PLLFAC1_bm (1<<1) /* Multiplication Factor bit 1 mask. */ -#define OSC_PLLFAC1_bp 1 /* Multiplication Factor bit 1 position. */ -#define OSC_PLLFAC2_bm (1<<2) /* Multiplication Factor bit 2 mask. */ -#define OSC_PLLFAC2_bp 2 /* Multiplication Factor bit 2 position. */ -#define OSC_PLLFAC3_bm (1<<3) /* Multiplication Factor bit 3 mask. */ -#define OSC_PLLFAC3_bp 3 /* Multiplication Factor bit 3 position. */ -#define OSC_PLLFAC4_bm (1<<4) /* Multiplication Factor bit 4 mask. */ -#define OSC_PLLFAC4_bp 4 /* Multiplication Factor bit 4 position. */ - - -/* OSC.DFLLCTRL bit masks and bit positions */ -#define OSC_RC32MCREF_bm 0x02 /* 32MHz Calibration Reference bit mask. */ -#define OSC_RC32MCREF_bp 1 /* 32MHz Calibration Reference bit position. */ - -#define OSC_RC2MCREF_bm 0x01 /* 2MHz Calibration Reference bit mask. */ -#define OSC_RC2MCREF_bp 0 /* 2MHz Calibration Reference bit position. */ - - -/* DFLL - DFLL */ -/* DFLL.CTRL bit masks and bit positions */ -#define DFLL_ENABLE_bm 0x01 /* DFLL Enable bit mask. */ -#define DFLL_ENABLE_bp 0 /* DFLL Enable bit position. */ - - -/* DFLL.CALA bit masks and bit positions */ -#define DFLL_CALL_gm 0x7F /* DFLL Calibration bits [6:0] group mask. */ -#define DFLL_CALL_gp 0 /* DFLL Calibration bits [6:0] group position. */ -#define DFLL_CALL0_bm (1<<0) /* DFLL Calibration bits [6:0] bit 0 mask. */ -#define DFLL_CALL0_bp 0 /* DFLL Calibration bits [6:0] bit 0 position. */ -#define DFLL_CALL1_bm (1<<1) /* DFLL Calibration bits [6:0] bit 1 mask. */ -#define DFLL_CALL1_bp 1 /* DFLL Calibration bits [6:0] bit 1 position. */ -#define DFLL_CALL2_bm (1<<2) /* DFLL Calibration bits [6:0] bit 2 mask. */ -#define DFLL_CALL2_bp 2 /* DFLL Calibration bits [6:0] bit 2 position. */ -#define DFLL_CALL3_bm (1<<3) /* DFLL Calibration bits [6:0] bit 3 mask. */ -#define DFLL_CALL3_bp 3 /* DFLL Calibration bits [6:0] bit 3 position. */ -#define DFLL_CALL4_bm (1<<4) /* DFLL Calibration bits [6:0] bit 4 mask. */ -#define DFLL_CALL4_bp 4 /* DFLL Calibration bits [6:0] bit 4 position. */ -#define DFLL_CALL5_bm (1<<5) /* DFLL Calibration bits [6:0] bit 5 mask. */ -#define DFLL_CALL5_bp 5 /* DFLL Calibration bits [6:0] bit 5 position. */ -#define DFLL_CALL6_bm (1<<6) /* DFLL Calibration bits [6:0] bit 6 mask. */ -#define DFLL_CALL6_bp 6 /* DFLL Calibration bits [6:0] bit 6 position. */ - - -/* DFLL.CALB bit masks and bit positions */ -#define DFLL_CALH_gm 0x3F /* DFLL Calibration bits [12:7] group mask. */ -#define DFLL_CALH_gp 0 /* DFLL Calibration bits [12:7] group position. */ -#define DFLL_CALH0_bm (1<<0) /* DFLL Calibration bits [12:7] bit 0 mask. */ -#define DFLL_CALH0_bp 0 /* DFLL Calibration bits [12:7] bit 0 position. */ -#define DFLL_CALH1_bm (1<<1) /* DFLL Calibration bits [12:7] bit 1 mask. */ -#define DFLL_CALH1_bp 1 /* DFLL Calibration bits [12:7] bit 1 position. */ -#define DFLL_CALH2_bm (1<<2) /* DFLL Calibration bits [12:7] bit 2 mask. */ -#define DFLL_CALH2_bp 2 /* DFLL Calibration bits [12:7] bit 2 position. */ -#define DFLL_CALH3_bm (1<<3) /* DFLL Calibration bits [12:7] bit 3 mask. */ -#define DFLL_CALH3_bp 3 /* DFLL Calibration bits [12:7] bit 3 position. */ -#define DFLL_CALH4_bm (1<<4) /* DFLL Calibration bits [12:7] bit 4 mask. */ -#define DFLL_CALH4_bp 4 /* DFLL Calibration bits [12:7] bit 4 position. */ -#define DFLL_CALH5_bm (1<<5) /* DFLL Calibration bits [12:7] bit 5 mask. */ -#define DFLL_CALH5_bp 5 /* DFLL Calibration bits [12:7] bit 5 position. */ - - -/* RST - Reset */ -/* RST.STATUS bit masks and bit positions */ -#define RST_SDRF_bm 0x40 /* Spike Detection Reset Flag bit mask. */ -#define RST_SDRF_bp 6 /* Spike Detection Reset Flag bit position. */ - -#define RST_SRF_bm 0x20 /* Software Reset Flag bit mask. */ -#define RST_SRF_bp 5 /* Software Reset Flag bit position. */ - -#define RST_PDIRF_bm 0x10 /* Programming and Debug Interface Interface Reset Flag bit mask. */ -#define RST_PDIRF_bp 4 /* Programming and Debug Interface Interface Reset Flag bit position. */ - -#define RST_WDRF_bm 0x08 /* Watchdog Reset Flag bit mask. */ -#define RST_WDRF_bp 3 /* Watchdog Reset Flag bit position. */ - -#define RST_BORF_bm 0x04 /* Brown-out Reset Flag bit mask. */ -#define RST_BORF_bp 2 /* Brown-out Reset Flag bit position. */ - -#define RST_EXTRF_bm 0x02 /* External Reset Flag bit mask. */ -#define RST_EXTRF_bp 1 /* External Reset Flag bit position. */ - -#define RST_PORF_bm 0x01 /* Power-on Reset Flag bit mask. */ -#define RST_PORF_bp 0 /* Power-on Reset Flag bit position. */ - - -/* RST.CTRL bit masks and bit positions */ -#define RST_SWRST_bm 0x01 /* Software Reset bit mask. */ -#define RST_SWRST_bp 0 /* Software Reset bit position. */ - - -/* WDT - Watch-Dog Timer */ -/* WDT.CTRL bit masks and bit positions */ -#define WDT_PER_gm 0x3C /* Period group mask. */ -#define WDT_PER_gp 2 /* Period group position. */ -#define WDT_PER0_bm (1<<2) /* Period bit 0 mask. */ -#define WDT_PER0_bp 2 /* Period bit 0 position. */ -#define WDT_PER1_bm (1<<3) /* Period bit 1 mask. */ -#define WDT_PER1_bp 3 /* Period bit 1 position. */ -#define WDT_PER2_bm (1<<4) /* Period bit 2 mask. */ -#define WDT_PER2_bp 4 /* Period bit 2 position. */ -#define WDT_PER3_bm (1<<5) /* Period bit 3 mask. */ -#define WDT_PER3_bp 5 /* Period bit 3 position. */ - -#define WDT_ENABLE_bm 0x02 /* Enable bit mask. */ -#define WDT_ENABLE_bp 1 /* Enable bit position. */ - -#define WDT_CEN_bm 0x01 /* Change Enable bit mask. */ -#define WDT_CEN_bp 0 /* Change Enable bit position. */ - - -/* WDT.WINCTRL bit masks and bit positions */ -#define WDT_WPER_gm 0x3C /* Windowed Mode Period group mask. */ -#define WDT_WPER_gp 2 /* Windowed Mode Period group position. */ -#define WDT_WPER0_bm (1<<2) /* Windowed Mode Period bit 0 mask. */ -#define WDT_WPER0_bp 2 /* Windowed Mode Period bit 0 position. */ -#define WDT_WPER1_bm (1<<3) /* Windowed Mode Period bit 1 mask. */ -#define WDT_WPER1_bp 3 /* Windowed Mode Period bit 1 position. */ -#define WDT_WPER2_bm (1<<4) /* Windowed Mode Period bit 2 mask. */ -#define WDT_WPER2_bp 4 /* Windowed Mode Period bit 2 position. */ -#define WDT_WPER3_bm (1<<5) /* Windowed Mode Period bit 3 mask. */ -#define WDT_WPER3_bp 5 /* Windowed Mode Period bit 3 position. */ - -#define WDT_WEN_bm 0x02 /* Windowed Mode Enable bit mask. */ -#define WDT_WEN_bp 1 /* Windowed Mode Enable bit position. */ - -#define WDT_WCEN_bm 0x01 /* Windowed Mode Change Enable bit mask. */ -#define WDT_WCEN_bp 0 /* Windowed Mode Change Enable bit position. */ - - -/* WDT.STATUS bit masks and bit positions */ -#define WDT_SYNCBUSY_bm 0x01 /* Syncronization busy bit mask. */ -#define WDT_SYNCBUSY_bp 0 /* Syncronization busy bit position. */ - - -/* MCU - MCU Control */ -/* MCU.MCUCR bit masks and bit positions */ -#define MCU_JTAGD_bm 0x01 /* JTAG Disable bit mask. */ -#define MCU_JTAGD_bp 0 /* JTAG Disable bit position. */ - - -/* MCU.EVSYSLOCK bit masks and bit positions */ -#define MCU_EVSYS1LOCK_bm 0x10 /* Event Channel 4-7 Lock bit mask. */ -#define MCU_EVSYS1LOCK_bp 4 /* Event Channel 4-7 Lock bit position. */ - -#define MCU_EVSYS0LOCK_bm 0x01 /* Event Channel 0-3 Lock bit mask. */ -#define MCU_EVSYS0LOCK_bp 0 /* Event Channel 0-3 Lock bit position. */ - - -/* MCU.AWEXLOCK bit masks and bit positions */ -#define MCU_AWEXELOCK_bm 0x04 /* AWeX on T/C E0 Lock bit mask. */ -#define MCU_AWEXELOCK_bp 2 /* AWeX on T/C E0 Lock bit position. */ - -#define MCU_AWEXCLOCK_bm 0x01 /* AWeX on T/C C0 Lock bit mask. */ -#define MCU_AWEXCLOCK_bp 0 /* AWeX on T/C C0 Lock bit position. */ - - -/* PMIC - Programmable Multi-level Interrupt Controller */ -/* PMIC.STATUS bit masks and bit positions */ -#define PMIC_NMIEX_bm 0x80 /* Non-maskable Interrupt Executing bit mask. */ -#define PMIC_NMIEX_bp 7 /* Non-maskable Interrupt Executing bit position. */ - -#define PMIC_HILVLEX_bm 0x04 /* High Level Interrupt Executing bit mask. */ -#define PMIC_HILVLEX_bp 2 /* High Level Interrupt Executing bit position. */ - -#define PMIC_MEDLVLEX_bm 0x02 /* Medium Level Interrupt Executing bit mask. */ -#define PMIC_MEDLVLEX_bp 1 /* Medium Level Interrupt Executing bit position. */ - -#define PMIC_LOLVLEX_bm 0x01 /* Low Level Interrupt Executing bit mask. */ -#define PMIC_LOLVLEX_bp 0 /* Low Level Interrupt Executing bit position. */ - - -/* PMIC.CTRL bit masks and bit positions */ -#define PMIC_RREN_bm 0x80 /* Round-Robin Priority Enable bit mask. */ -#define PMIC_RREN_bp 7 /* Round-Robin Priority Enable bit position. */ - -#define PMIC_IVSEL_bm 0x40 /* Interrupt Vector Select bit mask. */ -#define PMIC_IVSEL_bp 6 /* Interrupt Vector Select bit position. */ - -#define PMIC_HILVLEN_bm 0x04 /* High Level Enable bit mask. */ -#define PMIC_HILVLEN_bp 2 /* High Level Enable bit position. */ - -#define PMIC_MEDLVLEN_bm 0x02 /* Medium Level Enable bit mask. */ -#define PMIC_MEDLVLEN_bp 1 /* Medium Level Enable bit position. */ - -#define PMIC_LOLVLEN_bm 0x01 /* Low Level Enable bit mask. */ -#define PMIC_LOLVLEN_bp 0 /* Low Level Enable bit position. */ - - -/* DMA - DMA Controller */ -/* DMA_CH.CTRLA bit masks and bit positions */ -#define DMA_CH_ENABLE_bm 0x80 /* Channel Enable bit mask. */ -#define DMA_CH_ENABLE_bp 7 /* Channel Enable bit position. */ - -#define DMA_CH_RESET_bm 0x40 /* Channel Software Reset bit mask. */ -#define DMA_CH_RESET_bp 6 /* Channel Software Reset bit position. */ - -#define DMA_CH_REPEAT_bm 0x20 /* Channel Repeat Mode bit mask. */ -#define DMA_CH_REPEAT_bp 5 /* Channel Repeat Mode bit position. */ - -#define DMA_CH_TRFREQ_bm 0x10 /* Channel Transfer Request bit mask. */ -#define DMA_CH_TRFREQ_bp 4 /* Channel Transfer Request bit position. */ - -#define DMA_CH_SINGLE_bm 0x04 /* Channel Single Shot Data Transfer bit mask. */ -#define DMA_CH_SINGLE_bp 2 /* Channel Single Shot Data Transfer bit position. */ - -#define DMA_CH_BURSTLEN_gm 0x03 /* Channel Transfer Mode group mask. */ -#define DMA_CH_BURSTLEN_gp 0 /* Channel Transfer Mode group position. */ -#define DMA_CH_BURSTLEN0_bm (1<<0) /* Channel Transfer Mode bit 0 mask. */ -#define DMA_CH_BURSTLEN0_bp 0 /* Channel Transfer Mode bit 0 position. */ -#define DMA_CH_BURSTLEN1_bm (1<<1) /* Channel Transfer Mode bit 1 mask. */ -#define DMA_CH_BURSTLEN1_bp 1 /* Channel Transfer Mode bit 1 position. */ - - -/* DMA_CH.CTRLB bit masks and bit positions */ -#define DMA_CH_CHBUSY_bm 0x80 /* Block Transfer Busy bit mask. */ -#define DMA_CH_CHBUSY_bp 7 /* Block Transfer Busy bit position. */ - -#define DMA_CH_CHPEND_bm 0x40 /* Block Transfer Pending bit mask. */ -#define DMA_CH_CHPEND_bp 6 /* Block Transfer Pending bit position. */ - -#define DMA_CH_ERRIF_bm 0x20 /* Block Transfer Error Interrupt Flag bit mask. */ -#define DMA_CH_ERRIF_bp 5 /* Block Transfer Error Interrupt Flag bit position. */ - -#define DMA_CH_TRNIF_bm 0x10 /* Transaction Complete Interrup Flag bit mask. */ -#define DMA_CH_TRNIF_bp 4 /* Transaction Complete Interrup Flag bit position. */ - -#define DMA_CH_ERRINTLVL_gm 0x0C /* Transfer Error Interrupt Level group mask. */ -#define DMA_CH_ERRINTLVL_gp 2 /* Transfer Error Interrupt Level group position. */ -#define DMA_CH_ERRINTLVL0_bm (1<<2) /* Transfer Error Interrupt Level bit 0 mask. */ -#define DMA_CH_ERRINTLVL0_bp 2 /* Transfer Error Interrupt Level bit 0 position. */ -#define DMA_CH_ERRINTLVL1_bm (1<<3) /* Transfer Error Interrupt Level bit 1 mask. */ -#define DMA_CH_ERRINTLVL1_bp 3 /* Transfer Error Interrupt Level bit 1 position. */ - -#define DMA_CH_TRNINTLVL_gm 0x03 /* Transaction Complete Interrupt Level group mask. */ -#define DMA_CH_TRNINTLVL_gp 0 /* Transaction Complete Interrupt Level group position. */ -#define DMA_CH_TRNINTLVL0_bm (1<<0) /* Transaction Complete Interrupt Level bit 0 mask. */ -#define DMA_CH_TRNINTLVL0_bp 0 /* Transaction Complete Interrupt Level bit 0 position. */ -#define DMA_CH_TRNINTLVL1_bm (1<<1) /* Transaction Complete Interrupt Level bit 1 mask. */ -#define DMA_CH_TRNINTLVL1_bp 1 /* Transaction Complete Interrupt Level bit 1 position. */ - - -/* DMA_CH.ADDRCTRL bit masks and bit positions */ -#define DMA_CH_SRCRELOAD_gm 0xC0 /* Channel Source Address Reload group mask. */ -#define DMA_CH_SRCRELOAD_gp 6 /* Channel Source Address Reload group position. */ -#define DMA_CH_SRCRELOAD0_bm (1<<6) /* Channel Source Address Reload bit 0 mask. */ -#define DMA_CH_SRCRELOAD0_bp 6 /* Channel Source Address Reload bit 0 position. */ -#define DMA_CH_SRCRELOAD1_bm (1<<7) /* Channel Source Address Reload bit 1 mask. */ -#define DMA_CH_SRCRELOAD1_bp 7 /* Channel Source Address Reload bit 1 position. */ - -#define DMA_CH_SRCDIR_gm 0x30 /* Channel Source Address Mode group mask. */ -#define DMA_CH_SRCDIR_gp 4 /* Channel Source Address Mode group position. */ -#define DMA_CH_SRCDIR0_bm (1<<4) /* Channel Source Address Mode bit 0 mask. */ -#define DMA_CH_SRCDIR0_bp 4 /* Channel Source Address Mode bit 0 position. */ -#define DMA_CH_SRCDIR1_bm (1<<5) /* Channel Source Address Mode bit 1 mask. */ -#define DMA_CH_SRCDIR1_bp 5 /* Channel Source Address Mode bit 1 position. */ - -#define DMA_CH_DESTRELOAD_gm 0x0C /* Channel Destination Address Reload group mask. */ -#define DMA_CH_DESTRELOAD_gp 2 /* Channel Destination Address Reload group position. */ -#define DMA_CH_DESTRELOAD0_bm (1<<2) /* Channel Destination Address Reload bit 0 mask. */ -#define DMA_CH_DESTRELOAD0_bp 2 /* Channel Destination Address Reload bit 0 position. */ -#define DMA_CH_DESTRELOAD1_bm (1<<3) /* Channel Destination Address Reload bit 1 mask. */ -#define DMA_CH_DESTRELOAD1_bp 3 /* Channel Destination Address Reload bit 1 position. */ - -#define DMA_CH_DESTDIR_gm 0x03 /* Channel Destination Address Mode group mask. */ -#define DMA_CH_DESTDIR_gp 0 /* Channel Destination Address Mode group position. */ -#define DMA_CH_DESTDIR0_bm (1<<0) /* Channel Destination Address Mode bit 0 mask. */ -#define DMA_CH_DESTDIR0_bp 0 /* Channel Destination Address Mode bit 0 position. */ -#define DMA_CH_DESTDIR1_bm (1<<1) /* Channel Destination Address Mode bit 1 mask. */ -#define DMA_CH_DESTDIR1_bp 1 /* Channel Destination Address Mode bit 1 position. */ - - -/* DMA_CH.TRIGSRC bit masks and bit positions */ -#define DMA_CH_TRIGSRC_gm 0xFF /* Channel Trigger Source group mask. */ -#define DMA_CH_TRIGSRC_gp 0 /* Channel Trigger Source group position. */ -#define DMA_CH_TRIGSRC0_bm (1<<0) /* Channel Trigger Source bit 0 mask. */ -#define DMA_CH_TRIGSRC0_bp 0 /* Channel Trigger Source bit 0 position. */ -#define DMA_CH_TRIGSRC1_bm (1<<1) /* Channel Trigger Source bit 1 mask. */ -#define DMA_CH_TRIGSRC1_bp 1 /* Channel Trigger Source bit 1 position. */ -#define DMA_CH_TRIGSRC2_bm (1<<2) /* Channel Trigger Source bit 2 mask. */ -#define DMA_CH_TRIGSRC2_bp 2 /* Channel Trigger Source bit 2 position. */ -#define DMA_CH_TRIGSRC3_bm (1<<3) /* Channel Trigger Source bit 3 mask. */ -#define DMA_CH_TRIGSRC3_bp 3 /* Channel Trigger Source bit 3 position. */ -#define DMA_CH_TRIGSRC4_bm (1<<4) /* Channel Trigger Source bit 4 mask. */ -#define DMA_CH_TRIGSRC4_bp 4 /* Channel Trigger Source bit 4 position. */ -#define DMA_CH_TRIGSRC5_bm (1<<5) /* Channel Trigger Source bit 5 mask. */ -#define DMA_CH_TRIGSRC5_bp 5 /* Channel Trigger Source bit 5 position. */ -#define DMA_CH_TRIGSRC6_bm (1<<6) /* Channel Trigger Source bit 6 mask. */ -#define DMA_CH_TRIGSRC6_bp 6 /* Channel Trigger Source bit 6 position. */ -#define DMA_CH_TRIGSRC7_bm (1<<7) /* Channel Trigger Source bit 7 mask. */ -#define DMA_CH_TRIGSRC7_bp 7 /* Channel Trigger Source bit 7 position. */ - - -/* DMA.CTRL bit masks and bit positions */ -#define DMA_ENABLE_bm 0x80 /* Enable bit mask. */ -#define DMA_ENABLE_bp 7 /* Enable bit position. */ - -#define DMA_RESET_bm 0x40 /* Software Reset bit mask. */ -#define DMA_RESET_bp 6 /* Software Reset bit position. */ - -#define DMA_DBUFMODE_gm 0x0C /* Double Buffering Mode group mask. */ -#define DMA_DBUFMODE_gp 2 /* Double Buffering Mode group position. */ -#define DMA_DBUFMODE0_bm (1<<2) /* Double Buffering Mode bit 0 mask. */ -#define DMA_DBUFMODE0_bp 2 /* Double Buffering Mode bit 0 position. */ -#define DMA_DBUFMODE1_bm (1<<3) /* Double Buffering Mode bit 1 mask. */ -#define DMA_DBUFMODE1_bp 3 /* Double Buffering Mode bit 1 position. */ - -#define DMA_PRIMODE_gm 0x03 /* Channel Priority Mode group mask. */ -#define DMA_PRIMODE_gp 0 /* Channel Priority Mode group position. */ -#define DMA_PRIMODE0_bm (1<<0) /* Channel Priority Mode bit 0 mask. */ -#define DMA_PRIMODE0_bp 0 /* Channel Priority Mode bit 0 position. */ -#define DMA_PRIMODE1_bm (1<<1) /* Channel Priority Mode bit 1 mask. */ -#define DMA_PRIMODE1_bp 1 /* Channel Priority Mode bit 1 position. */ - - -/* DMA.INTFLAGS bit masks and bit positions */ -#define DMA_CH3ERRIF_bm 0x80 /* Channel 3 Block Transfer Error Interrupt Flag bit mask. */ -#define DMA_CH3ERRIF_bp 7 /* Channel 3 Block Transfer Error Interrupt Flag bit position. */ - -#define DMA_CH2ERRIF_bm 0x40 /* Channel 2 Block Transfer Error Interrupt Flag bit mask. */ -#define DMA_CH2ERRIF_bp 6 /* Channel 2 Block Transfer Error Interrupt Flag bit position. */ - -#define DMA_CH1ERRIF_bm 0x20 /* Channel 1 Block Transfer Error Interrupt Flag bit mask. */ -#define DMA_CH1ERRIF_bp 5 /* Channel 1 Block Transfer Error Interrupt Flag bit position. */ - -#define DMA_CH0ERRIF_bm 0x10 /* Channel 0 Block Transfer Error Interrupt Flag bit mask. */ -#define DMA_CH0ERRIF_bp 4 /* Channel 0 Block Transfer Error Interrupt Flag bit position. */ - -#define DMA_CH3TRNIF_bm 0x08 /* Channel 3 Transaction Complete Interrupt Flag bit mask. */ -#define DMA_CH3TRNIF_bp 3 /* Channel 3 Transaction Complete Interrupt Flag bit position. */ - -#define DMA_CH2TRNIF_bm 0x04 /* Channel 2 Transaction Complete Interrupt Flag bit mask. */ -#define DMA_CH2TRNIF_bp 2 /* Channel 2 Transaction Complete Interrupt Flag bit position. */ - -#define DMA_CH1TRNIF_bm 0x02 /* Channel 1 Transaction Complete Interrupt Flag bit mask. */ -#define DMA_CH1TRNIF_bp 1 /* Channel 1 Transaction Complete Interrupt Flag bit position. */ - -#define DMA_CH0TRNIF_bm 0x01 /* Channel 0 Transaction Complete Interrupt Flag bit mask. */ -#define DMA_CH0TRNIF_bp 0 /* Channel 0 Transaction Complete Interrupt Flag bit position. */ - - -/* DMA.STATUS bit masks and bit positions */ -#define DMA_CH3BUSY_bm 0x80 /* Channel 3 Block Transfer Busy bit mask. */ -#define DMA_CH3BUSY_bp 7 /* Channel 3 Block Transfer Busy bit position. */ - -#define DMA_CH2BUSY_bm 0x40 /* Channel 2 Block Transfer Busy bit mask. */ -#define DMA_CH2BUSY_bp 6 /* Channel 2 Block Transfer Busy bit position. */ - -#define DMA_CH1BUSY_bm 0x20 /* Channel 1 Block Transfer Busy bit mask. */ -#define DMA_CH1BUSY_bp 5 /* Channel 1 Block Transfer Busy bit position. */ - -#define DMA_CH0BUSY_bm 0x10 /* Channel 0 Block Transfer Busy bit mask. */ -#define DMA_CH0BUSY_bp 4 /* Channel 0 Block Transfer Busy bit position. */ - -#define DMA_CH3PEND_bm 0x08 /* Channel 3 Block Transfer Pending bit mask. */ -#define DMA_CH3PEND_bp 3 /* Channel 3 Block Transfer Pending bit position. */ - -#define DMA_CH2PEND_bm 0x04 /* Channel 2 Block Transfer Pending bit mask. */ -#define DMA_CH2PEND_bp 2 /* Channel 2 Block Transfer Pending bit position. */ - -#define DMA_CH1PEND_bm 0x02 /* Channel 1 Block Transfer Pending bit mask. */ -#define DMA_CH1PEND_bp 1 /* Channel 1 Block Transfer Pending bit position. */ - -#define DMA_CH0PEND_bm 0x01 /* Channel 0 Block Transfer Pending bit mask. */ -#define DMA_CH0PEND_bp 0 /* Channel 0 Block Transfer Pending bit position. */ - - -/* EVSYS - Event System */ -/* EVSYS.CH0MUX bit masks and bit positions */ -#define EVSYS_CHMUX_gm 0xFF /* Event Channel 0 Multiplexer group mask. */ -#define EVSYS_CHMUX_gp 0 /* Event Channel 0 Multiplexer group position. */ -#define EVSYS_CHMUX0_bm (1<<0) /* Event Channel 0 Multiplexer bit 0 mask. */ -#define EVSYS_CHMUX0_bp 0 /* Event Channel 0 Multiplexer bit 0 position. */ -#define EVSYS_CHMUX1_bm (1<<1) /* Event Channel 0 Multiplexer bit 1 mask. */ -#define EVSYS_CHMUX1_bp 1 /* Event Channel 0 Multiplexer bit 1 position. */ -#define EVSYS_CHMUX2_bm (1<<2) /* Event Channel 0 Multiplexer bit 2 mask. */ -#define EVSYS_CHMUX2_bp 2 /* Event Channel 0 Multiplexer bit 2 position. */ -#define EVSYS_CHMUX3_bm (1<<3) /* Event Channel 0 Multiplexer bit 3 mask. */ -#define EVSYS_CHMUX3_bp 3 /* Event Channel 0 Multiplexer bit 3 position. */ -#define EVSYS_CHMUX4_bm (1<<4) /* Event Channel 0 Multiplexer bit 4 mask. */ -#define EVSYS_CHMUX4_bp 4 /* Event Channel 0 Multiplexer bit 4 position. */ -#define EVSYS_CHMUX5_bm (1<<5) /* Event Channel 0 Multiplexer bit 5 mask. */ -#define EVSYS_CHMUX5_bp 5 /* Event Channel 0 Multiplexer bit 5 position. */ -#define EVSYS_CHMUX6_bm (1<<6) /* Event Channel 0 Multiplexer bit 6 mask. */ -#define EVSYS_CHMUX6_bp 6 /* Event Channel 0 Multiplexer bit 6 position. */ -#define EVSYS_CHMUX7_bm (1<<7) /* Event Channel 0 Multiplexer bit 7 mask. */ -#define EVSYS_CHMUX7_bp 7 /* Event Channel 0 Multiplexer bit 7 position. */ - - -/* EVSYS.CH1MUX bit masks and bit positions */ -/* EVSYS_CHMUX_gm Predefined. */ -/* EVSYS_CHMUX_gp Predefined. */ -/* EVSYS_CHMUX0_bm Predefined. */ -/* EVSYS_CHMUX0_bp Predefined. */ -/* EVSYS_CHMUX1_bm Predefined. */ -/* EVSYS_CHMUX1_bp Predefined. */ -/* EVSYS_CHMUX2_bm Predefined. */ -/* EVSYS_CHMUX2_bp Predefined. */ -/* EVSYS_CHMUX3_bm Predefined. */ -/* EVSYS_CHMUX3_bp Predefined. */ -/* EVSYS_CHMUX4_bm Predefined. */ -/* EVSYS_CHMUX4_bp Predefined. */ -/* EVSYS_CHMUX5_bm Predefined. */ -/* EVSYS_CHMUX5_bp Predefined. */ -/* EVSYS_CHMUX6_bm Predefined. */ -/* EVSYS_CHMUX6_bp Predefined. */ -/* EVSYS_CHMUX7_bm Predefined. */ -/* EVSYS_CHMUX7_bp Predefined. */ - - -/* EVSYS.CH2MUX bit masks and bit positions */ -/* EVSYS_CHMUX_gm Predefined. */ -/* EVSYS_CHMUX_gp Predefined. */ -/* EVSYS_CHMUX0_bm Predefined. */ -/* EVSYS_CHMUX0_bp Predefined. */ -/* EVSYS_CHMUX1_bm Predefined. */ -/* EVSYS_CHMUX1_bp Predefined. */ -/* EVSYS_CHMUX2_bm Predefined. */ -/* EVSYS_CHMUX2_bp Predefined. */ -/* EVSYS_CHMUX3_bm Predefined. */ -/* EVSYS_CHMUX3_bp Predefined. */ -/* EVSYS_CHMUX4_bm Predefined. */ -/* EVSYS_CHMUX4_bp Predefined. */ -/* EVSYS_CHMUX5_bm Predefined. */ -/* EVSYS_CHMUX5_bp Predefined. */ -/* EVSYS_CHMUX6_bm Predefined. */ -/* EVSYS_CHMUX6_bp Predefined. */ -/* EVSYS_CHMUX7_bm Predefined. */ -/* EVSYS_CHMUX7_bp Predefined. */ - - -/* EVSYS.CH3MUX bit masks and bit positions */ -/* EVSYS_CHMUX_gm Predefined. */ -/* EVSYS_CHMUX_gp Predefined. */ -/* EVSYS_CHMUX0_bm Predefined. */ -/* EVSYS_CHMUX0_bp Predefined. */ -/* EVSYS_CHMUX1_bm Predefined. */ -/* EVSYS_CHMUX1_bp Predefined. */ -/* EVSYS_CHMUX2_bm Predefined. */ -/* EVSYS_CHMUX2_bp Predefined. */ -/* EVSYS_CHMUX3_bm Predefined. */ -/* EVSYS_CHMUX3_bp Predefined. */ -/* EVSYS_CHMUX4_bm Predefined. */ -/* EVSYS_CHMUX4_bp Predefined. */ -/* EVSYS_CHMUX5_bm Predefined. */ -/* EVSYS_CHMUX5_bp Predefined. */ -/* EVSYS_CHMUX6_bm Predefined. */ -/* EVSYS_CHMUX6_bp Predefined. */ -/* EVSYS_CHMUX7_bm Predefined. */ -/* EVSYS_CHMUX7_bp Predefined. */ - - -/* EVSYS.CH4MUX bit masks and bit positions */ -/* EVSYS_CHMUX_gm Predefined. */ -/* EVSYS_CHMUX_gp Predefined. */ -/* EVSYS_CHMUX0_bm Predefined. */ -/* EVSYS_CHMUX0_bp Predefined. */ -/* EVSYS_CHMUX1_bm Predefined. */ -/* EVSYS_CHMUX1_bp Predefined. */ -/* EVSYS_CHMUX2_bm Predefined. */ -/* EVSYS_CHMUX2_bp Predefined. */ -/* EVSYS_CHMUX3_bm Predefined. */ -/* EVSYS_CHMUX3_bp Predefined. */ -/* EVSYS_CHMUX4_bm Predefined. */ -/* EVSYS_CHMUX4_bp Predefined. */ -/* EVSYS_CHMUX5_bm Predefined. */ -/* EVSYS_CHMUX5_bp Predefined. */ -/* EVSYS_CHMUX6_bm Predefined. */ -/* EVSYS_CHMUX6_bp Predefined. */ -/* EVSYS_CHMUX7_bm Predefined. */ -/* EVSYS_CHMUX7_bp Predefined. */ - - -/* EVSYS.CH5MUX bit masks and bit positions */ -/* EVSYS_CHMUX_gm Predefined. */ -/* EVSYS_CHMUX_gp Predefined. */ -/* EVSYS_CHMUX0_bm Predefined. */ -/* EVSYS_CHMUX0_bp Predefined. */ -/* EVSYS_CHMUX1_bm Predefined. */ -/* EVSYS_CHMUX1_bp Predefined. */ -/* EVSYS_CHMUX2_bm Predefined. */ -/* EVSYS_CHMUX2_bp Predefined. */ -/* EVSYS_CHMUX3_bm Predefined. */ -/* EVSYS_CHMUX3_bp Predefined. */ -/* EVSYS_CHMUX4_bm Predefined. */ -/* EVSYS_CHMUX4_bp Predefined. */ -/* EVSYS_CHMUX5_bm Predefined. */ -/* EVSYS_CHMUX5_bp Predefined. */ -/* EVSYS_CHMUX6_bm Predefined. */ -/* EVSYS_CHMUX6_bp Predefined. */ -/* EVSYS_CHMUX7_bm Predefined. */ -/* EVSYS_CHMUX7_bp Predefined. */ - - -/* EVSYS.CH6MUX bit masks and bit positions */ -/* EVSYS_CHMUX_gm Predefined. */ -/* EVSYS_CHMUX_gp Predefined. */ -/* EVSYS_CHMUX0_bm Predefined. */ -/* EVSYS_CHMUX0_bp Predefined. */ -/* EVSYS_CHMUX1_bm Predefined. */ -/* EVSYS_CHMUX1_bp Predefined. */ -/* EVSYS_CHMUX2_bm Predefined. */ -/* EVSYS_CHMUX2_bp Predefined. */ -/* EVSYS_CHMUX3_bm Predefined. */ -/* EVSYS_CHMUX3_bp Predefined. */ -/* EVSYS_CHMUX4_bm Predefined. */ -/* EVSYS_CHMUX4_bp Predefined. */ -/* EVSYS_CHMUX5_bm Predefined. */ -/* EVSYS_CHMUX5_bp Predefined. */ -/* EVSYS_CHMUX6_bm Predefined. */ -/* EVSYS_CHMUX6_bp Predefined. */ -/* EVSYS_CHMUX7_bm Predefined. */ -/* EVSYS_CHMUX7_bp Predefined. */ - - -/* EVSYS.CH7MUX bit masks and bit positions */ -/* EVSYS_CHMUX_gm Predefined. */ -/* EVSYS_CHMUX_gp Predefined. */ -/* EVSYS_CHMUX0_bm Predefined. */ -/* EVSYS_CHMUX0_bp Predefined. */ -/* EVSYS_CHMUX1_bm Predefined. */ -/* EVSYS_CHMUX1_bp Predefined. */ -/* EVSYS_CHMUX2_bm Predefined. */ -/* EVSYS_CHMUX2_bp Predefined. */ -/* EVSYS_CHMUX3_bm Predefined. */ -/* EVSYS_CHMUX3_bp Predefined. */ -/* EVSYS_CHMUX4_bm Predefined. */ -/* EVSYS_CHMUX4_bp Predefined. */ -/* EVSYS_CHMUX5_bm Predefined. */ -/* EVSYS_CHMUX5_bp Predefined. */ -/* EVSYS_CHMUX6_bm Predefined. */ -/* EVSYS_CHMUX6_bp Predefined. */ -/* EVSYS_CHMUX7_bm Predefined. */ -/* EVSYS_CHMUX7_bp Predefined. */ - - -/* EVSYS.CH0CTRL bit masks and bit positions */ -#define EVSYS_QDIRM_gm 0x60 /* Quadrature Decoder Index Recognition Mode group mask. */ -#define EVSYS_QDIRM_gp 5 /* Quadrature Decoder Index Recognition Mode group position. */ -#define EVSYS_QDIRM0_bm (1<<5) /* Quadrature Decoder Index Recognition Mode bit 0 mask. */ -#define EVSYS_QDIRM0_bp 5 /* Quadrature Decoder Index Recognition Mode bit 0 position. */ -#define EVSYS_QDIRM1_bm (1<<6) /* Quadrature Decoder Index Recognition Mode bit 1 mask. */ -#define EVSYS_QDIRM1_bp 6 /* Quadrature Decoder Index Recognition Mode bit 1 position. */ - -#define EVSYS_QDIEN_bm 0x10 /* Quadrature Decoder Index Enable bit mask. */ -#define EVSYS_QDIEN_bp 4 /* Quadrature Decoder Index Enable bit position. */ - -#define EVSYS_QDEN_bm 0x08 /* Quadrature Decoder Enable bit mask. */ -#define EVSYS_QDEN_bp 3 /* Quadrature Decoder Enable bit position. */ - -#define EVSYS_DIGFILT_gm 0x07 /* Digital Filter group mask. */ -#define EVSYS_DIGFILT_gp 0 /* Digital Filter group position. */ -#define EVSYS_DIGFILT0_bm (1<<0) /* Digital Filter bit 0 mask. */ -#define EVSYS_DIGFILT0_bp 0 /* Digital Filter bit 0 position. */ -#define EVSYS_DIGFILT1_bm (1<<1) /* Digital Filter bit 1 mask. */ -#define EVSYS_DIGFILT1_bp 1 /* Digital Filter bit 1 position. */ -#define EVSYS_DIGFILT2_bm (1<<2) /* Digital Filter bit 2 mask. */ -#define EVSYS_DIGFILT2_bp 2 /* Digital Filter bit 2 position. */ - - -/* EVSYS.CH1CTRL bit masks and bit positions */ -/* EVSYS_DIGFILT_gm Predefined. */ -/* EVSYS_DIGFILT_gp Predefined. */ -/* EVSYS_DIGFILT0_bm Predefined. */ -/* EVSYS_DIGFILT0_bp Predefined. */ -/* EVSYS_DIGFILT1_bm Predefined. */ -/* EVSYS_DIGFILT1_bp Predefined. */ -/* EVSYS_DIGFILT2_bm Predefined. */ -/* EVSYS_DIGFILT2_bp Predefined. */ - - -/* EVSYS.CH2CTRL bit masks and bit positions */ -/* EVSYS_QDIRM_gm Predefined. */ -/* EVSYS_QDIRM_gp Predefined. */ -/* EVSYS_QDIRM0_bm Predefined. */ -/* EVSYS_QDIRM0_bp Predefined. */ -/* EVSYS_QDIRM1_bm Predefined. */ -/* EVSYS_QDIRM1_bp Predefined. */ - -/* EVSYS_QDIEN_bm Predefined. */ -/* EVSYS_QDIEN_bp Predefined. */ - -/* EVSYS_QDEN_bm Predefined. */ -/* EVSYS_QDEN_bp Predefined. */ - -/* EVSYS_DIGFILT_gm Predefined. */ -/* EVSYS_DIGFILT_gp Predefined. */ -/* EVSYS_DIGFILT0_bm Predefined. */ -/* EVSYS_DIGFILT0_bp Predefined. */ -/* EVSYS_DIGFILT1_bm Predefined. */ -/* EVSYS_DIGFILT1_bp Predefined. */ -/* EVSYS_DIGFILT2_bm Predefined. */ -/* EVSYS_DIGFILT2_bp Predefined. */ - - -/* EVSYS.CH3CTRL bit masks and bit positions */ -/* EVSYS_DIGFILT_gm Predefined. */ -/* EVSYS_DIGFILT_gp Predefined. */ -/* EVSYS_DIGFILT0_bm Predefined. */ -/* EVSYS_DIGFILT0_bp Predefined. */ -/* EVSYS_DIGFILT1_bm Predefined. */ -/* EVSYS_DIGFILT1_bp Predefined. */ -/* EVSYS_DIGFILT2_bm Predefined. */ -/* EVSYS_DIGFILT2_bp Predefined. */ - - -/* EVSYS.CH4CTRL bit masks and bit positions */ -/* EVSYS_QDIRM_gm Predefined. */ -/* EVSYS_QDIRM_gp Predefined. */ -/* EVSYS_QDIRM0_bm Predefined. */ -/* EVSYS_QDIRM0_bp Predefined. */ -/* EVSYS_QDIRM1_bm Predefined. */ -/* EVSYS_QDIRM1_bp Predefined. */ - -/* EVSYS_QDIEN_bm Predefined. */ -/* EVSYS_QDIEN_bp Predefined. */ - -/* EVSYS_QDEN_bm Predefined. */ -/* EVSYS_QDEN_bp Predefined. */ - -/* EVSYS_DIGFILT_gm Predefined. */ -/* EVSYS_DIGFILT_gp Predefined. */ -/* EVSYS_DIGFILT0_bm Predefined. */ -/* EVSYS_DIGFILT0_bp Predefined. */ -/* EVSYS_DIGFILT1_bm Predefined. */ -/* EVSYS_DIGFILT1_bp Predefined. */ -/* EVSYS_DIGFILT2_bm Predefined. */ -/* EVSYS_DIGFILT2_bp Predefined. */ - - -/* EVSYS.CH5CTRL bit masks and bit positions */ -/* EVSYS_DIGFILT_gm Predefined. */ -/* EVSYS_DIGFILT_gp Predefined. */ -/* EVSYS_DIGFILT0_bm Predefined. */ -/* EVSYS_DIGFILT0_bp Predefined. */ -/* EVSYS_DIGFILT1_bm Predefined. */ -/* EVSYS_DIGFILT1_bp Predefined. */ -/* EVSYS_DIGFILT2_bm Predefined. */ -/* EVSYS_DIGFILT2_bp Predefined. */ - - -/* EVSYS.CH6CTRL bit masks and bit positions */ -/* EVSYS_DIGFILT_gm Predefined. */ -/* EVSYS_DIGFILT_gp Predefined. */ -/* EVSYS_DIGFILT0_bm Predefined. */ -/* EVSYS_DIGFILT0_bp Predefined. */ -/* EVSYS_DIGFILT1_bm Predefined. */ -/* EVSYS_DIGFILT1_bp Predefined. */ -/* EVSYS_DIGFILT2_bm Predefined. */ -/* EVSYS_DIGFILT2_bp Predefined. */ - - -/* EVSYS.CH7CTRL bit masks and bit positions */ -/* EVSYS_DIGFILT_gm Predefined. */ -/* EVSYS_DIGFILT_gp Predefined. */ -/* EVSYS_DIGFILT0_bm Predefined. */ -/* EVSYS_DIGFILT0_bp Predefined. */ -/* EVSYS_DIGFILT1_bm Predefined. */ -/* EVSYS_DIGFILT1_bp Predefined. */ -/* EVSYS_DIGFILT2_bm Predefined. */ -/* EVSYS_DIGFILT2_bp Predefined. */ - - -/* NVM - Non Volatile Memory Controller */ -/* NVM.CMD bit masks and bit positions */ -#define NVM_CMD_gm 0xFF /* Command group mask. */ -#define NVM_CMD_gp 0 /* Command group position. */ -#define NVM_CMD0_bm (1<<0) /* Command bit 0 mask. */ -#define NVM_CMD0_bp 0 /* Command bit 0 position. */ -#define NVM_CMD1_bm (1<<1) /* Command bit 1 mask. */ -#define NVM_CMD1_bp 1 /* Command bit 1 position. */ -#define NVM_CMD2_bm (1<<2) /* Command bit 2 mask. */ -#define NVM_CMD2_bp 2 /* Command bit 2 position. */ -#define NVM_CMD3_bm (1<<3) /* Command bit 3 mask. */ -#define NVM_CMD3_bp 3 /* Command bit 3 position. */ -#define NVM_CMD4_bm (1<<4) /* Command bit 4 mask. */ -#define NVM_CMD4_bp 4 /* Command bit 4 position. */ -#define NVM_CMD5_bm (1<<5) /* Command bit 5 mask. */ -#define NVM_CMD5_bp 5 /* Command bit 5 position. */ -#define NVM_CMD6_bm (1<<6) /* Command bit 6 mask. */ -#define NVM_CMD6_bp 6 /* Command bit 6 position. */ -#define NVM_CMD7_bm (1<<7) /* Command bit 7 mask. */ -#define NVM_CMD7_bp 7 /* Command bit 7 position. */ - - -/* NVM.CTRLA bit masks and bit positions */ -#define NVM_CMDEX_bm 0x01 /* Command Execute bit mask. */ -#define NVM_CMDEX_bp 0 /* Command Execute bit position. */ - - -/* NVM.CTRLB bit masks and bit positions */ -#define NVM_EEMAPEN_bm 0x08 /* EEPROM Mapping Enable bit mask. */ -#define NVM_EEMAPEN_bp 3 /* EEPROM Mapping Enable bit position. */ - -#define NVM_FPRM_bm 0x04 /* Flash Power Reduction Enable bit mask. */ -#define NVM_FPRM_bp 2 /* Flash Power Reduction Enable bit position. */ - -#define NVM_EPRM_bm 0x02 /* EEPROM Power Reduction Enable bit mask. */ -#define NVM_EPRM_bp 1 /* EEPROM Power Reduction Enable bit position. */ - -#define NVM_SPMLOCK_bm 0x01 /* SPM Lock bit mask. */ -#define NVM_SPMLOCK_bp 0 /* SPM Lock bit position. */ - - -/* NVM.INTCTRL bit masks and bit positions */ -#define NVM_SPMLVL_gm 0x0C /* SPM Interrupt Level group mask. */ -#define NVM_SPMLVL_gp 2 /* SPM Interrupt Level group position. */ -#define NVM_SPMLVL0_bm (1<<2) /* SPM Interrupt Level bit 0 mask. */ -#define NVM_SPMLVL0_bp 2 /* SPM Interrupt Level bit 0 position. */ -#define NVM_SPMLVL1_bm (1<<3) /* SPM Interrupt Level bit 1 mask. */ -#define NVM_SPMLVL1_bp 3 /* SPM Interrupt Level bit 1 position. */ - -#define NVM_EELVL_gm 0x03 /* EEPROM Interrupt Level group mask. */ -#define NVM_EELVL_gp 0 /* EEPROM Interrupt Level group position. */ -#define NVM_EELVL0_bm (1<<0) /* EEPROM Interrupt Level bit 0 mask. */ -#define NVM_EELVL0_bp 0 /* EEPROM Interrupt Level bit 0 position. */ -#define NVM_EELVL1_bm (1<<1) /* EEPROM Interrupt Level bit 1 mask. */ -#define NVM_EELVL1_bp 1 /* EEPROM Interrupt Level bit 1 position. */ - - -/* NVM.STATUS bit masks and bit positions */ -#define NVM_NVMBUSY_bm 0x80 /* Non-volatile Memory Busy bit mask. */ -#define NVM_NVMBUSY_bp 7 /* Non-volatile Memory Busy bit position. */ - -#define NVM_FBUSY_bm 0x40 /* Flash Memory Busy bit mask. */ -#define NVM_FBUSY_bp 6 /* Flash Memory Busy bit position. */ - -#define NVM_EELOAD_bm 0x02 /* EEPROM Page Buffer Active Loading bit mask. */ -#define NVM_EELOAD_bp 1 /* EEPROM Page Buffer Active Loading bit position. */ - -#define NVM_FLOAD_bm 0x01 /* Flash Page Buffer Active Loading bit mask. */ -#define NVM_FLOAD_bp 0 /* Flash Page Buffer Active Loading bit position. */ - - -/* NVM.LOCKBITS bit masks and bit positions */ -#define NVM_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ -#define NVM_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ -#define NVM_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ -#define NVM_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ -#define NVM_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ -#define NVM_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ - -#define NVM_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ -#define NVM_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ -#define NVM_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ -#define NVM_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ -#define NVM_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ -#define NVM_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ - -#define NVM_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ -#define NVM_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ -#define NVM_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ -#define NVM_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ -#define NVM_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ -#define NVM_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ - -#define NVM_LB_gm 0x03 /* Lock Bits group mask. */ -#define NVM_LB_gp 0 /* Lock Bits group position. */ -#define NVM_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ -#define NVM_LB0_bp 0 /* Lock Bits bit 0 position. */ -#define NVM_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ -#define NVM_LB1_bp 1 /* Lock Bits bit 1 position. */ - - -/* NVM_LOCKBITS.LOCKBITS bit masks and bit positions */ -#define NVM_LOCKBITS_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ -#define NVM_LOCKBITS_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ -#define NVM_LOCKBITS_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ -#define NVM_LOCKBITS_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ -#define NVM_LOCKBITS_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ -#define NVM_LOCKBITS_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ - -#define NVM_LOCKBITS_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ -#define NVM_LOCKBITS_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ -#define NVM_LOCKBITS_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ -#define NVM_LOCKBITS_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ -#define NVM_LOCKBITS_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ -#define NVM_LOCKBITS_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ - -#define NVM_LOCKBITS_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ -#define NVM_LOCKBITS_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ -#define NVM_LOCKBITS_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ -#define NVM_LOCKBITS_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ -#define NVM_LOCKBITS_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ -#define NVM_LOCKBITS_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ - -#define NVM_LOCKBITS_LB_gm 0x03 /* Lock Bits group mask. */ -#define NVM_LOCKBITS_LB_gp 0 /* Lock Bits group position. */ -#define NVM_LOCKBITS_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ -#define NVM_LOCKBITS_LB0_bp 0 /* Lock Bits bit 0 position. */ -#define NVM_LOCKBITS_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ -#define NVM_LOCKBITS_LB1_bp 1 /* Lock Bits bit 1 position. */ - - -/* NVM_FUSES.FUSEBYTE0 bit masks and bit positions */ -#define NVM_FUSES_JTAGUSERID_gm 0xFF /* JTAG User ID group mask. */ -#define NVM_FUSES_JTAGUSERID_gp 0 /* JTAG User ID group position. */ -#define NVM_FUSES_JTAGUSERID0_bm (1<<0) /* JTAG User ID bit 0 mask. */ -#define NVM_FUSES_JTAGUSERID0_bp 0 /* JTAG User ID bit 0 position. */ -#define NVM_FUSES_JTAGUSERID1_bm (1<<1) /* JTAG User ID bit 1 mask. */ -#define NVM_FUSES_JTAGUSERID1_bp 1 /* JTAG User ID bit 1 position. */ -#define NVM_FUSES_JTAGUSERID2_bm (1<<2) /* JTAG User ID bit 2 mask. */ -#define NVM_FUSES_JTAGUSERID2_bp 2 /* JTAG User ID bit 2 position. */ -#define NVM_FUSES_JTAGUSERID3_bm (1<<3) /* JTAG User ID bit 3 mask. */ -#define NVM_FUSES_JTAGUSERID3_bp 3 /* JTAG User ID bit 3 position. */ -#define NVM_FUSES_JTAGUSERID4_bm (1<<4) /* JTAG User ID bit 4 mask. */ -#define NVM_FUSES_JTAGUSERID4_bp 4 /* JTAG User ID bit 4 position. */ -#define NVM_FUSES_JTAGUSERID5_bm (1<<5) /* JTAG User ID bit 5 mask. */ -#define NVM_FUSES_JTAGUSERID5_bp 5 /* JTAG User ID bit 5 position. */ -#define NVM_FUSES_JTAGUSERID6_bm (1<<6) /* JTAG User ID bit 6 mask. */ -#define NVM_FUSES_JTAGUSERID6_bp 6 /* JTAG User ID bit 6 position. */ -#define NVM_FUSES_JTAGUSERID7_bm (1<<7) /* JTAG User ID bit 7 mask. */ -#define NVM_FUSES_JTAGUSERID7_bp 7 /* JTAG User ID bit 7 position. */ - - -/* NVM_FUSES.FUSEBYTE1 bit masks and bit positions */ -#define NVM_FUSES_WDWP_gm 0xF0 /* Watchdog Window Timeout Period group mask. */ -#define NVM_FUSES_WDWP_gp 4 /* Watchdog Window Timeout Period group position. */ -#define NVM_FUSES_WDWP0_bm (1<<4) /* Watchdog Window Timeout Period bit 0 mask. */ -#define NVM_FUSES_WDWP0_bp 4 /* Watchdog Window Timeout Period bit 0 position. */ -#define NVM_FUSES_WDWP1_bm (1<<5) /* Watchdog Window Timeout Period bit 1 mask. */ -#define NVM_FUSES_WDWP1_bp 5 /* Watchdog Window Timeout Period bit 1 position. */ -#define NVM_FUSES_WDWP2_bm (1<<6) /* Watchdog Window Timeout Period bit 2 mask. */ -#define NVM_FUSES_WDWP2_bp 6 /* Watchdog Window Timeout Period bit 2 position. */ -#define NVM_FUSES_WDWP3_bm (1<<7) /* Watchdog Window Timeout Period bit 3 mask. */ -#define NVM_FUSES_WDWP3_bp 7 /* Watchdog Window Timeout Period bit 3 position. */ - -#define NVM_FUSES_WDP_gm 0x0F /* Watchdog Timeout Period group mask. */ -#define NVM_FUSES_WDP_gp 0 /* Watchdog Timeout Period group position. */ -#define NVM_FUSES_WDP0_bm (1<<0) /* Watchdog Timeout Period bit 0 mask. */ -#define NVM_FUSES_WDP0_bp 0 /* Watchdog Timeout Period bit 0 position. */ -#define NVM_FUSES_WDP1_bm (1<<1) /* Watchdog Timeout Period bit 1 mask. */ -#define NVM_FUSES_WDP1_bp 1 /* Watchdog Timeout Period bit 1 position. */ -#define NVM_FUSES_WDP2_bm (1<<2) /* Watchdog Timeout Period bit 2 mask. */ -#define NVM_FUSES_WDP2_bp 2 /* Watchdog Timeout Period bit 2 position. */ -#define NVM_FUSES_WDP3_bm (1<<3) /* Watchdog Timeout Period bit 3 mask. */ -#define NVM_FUSES_WDP3_bp 3 /* Watchdog Timeout Period bit 3 position. */ - - -/* NVM_FUSES.FUSEBYTE2 bit masks and bit positions */ -#define NVM_FUSES_DVSDON_bm 0x80 /* Spike Detector Enable bit mask. */ -#define NVM_FUSES_DVSDON_bp 7 /* Spike Detector Enable bit position. */ - -#define NVM_FUSES_BOOTRST_bm 0x40 /* Boot Loader Section Reset Vector bit mask. */ -#define NVM_FUSES_BOOTRST_bp 6 /* Boot Loader Section Reset Vector bit position. */ - -#define NVM_FUSES_BODPD_gm 0x03 /* BOD Operation in Power-Down Mode group mask. */ -#define NVM_FUSES_BODPD_gp 0 /* BOD Operation in Power-Down Mode group position. */ -#define NVM_FUSES_BODPD0_bm (1<<0) /* BOD Operation in Power-Down Mode bit 0 mask. */ -#define NVM_FUSES_BODPD0_bp 0 /* BOD Operation in Power-Down Mode bit 0 position. */ -#define NVM_FUSES_BODPD1_bm (1<<1) /* BOD Operation in Power-Down Mode bit 1 mask. */ -#define NVM_FUSES_BODPD1_bp 1 /* BOD Operation in Power-Down Mode bit 1 position. */ - - -/* NVM_FUSES.FUSEBYTE4 bit masks and bit positions */ -#define NVM_FUSES_SUT_gm 0x0C /* Start-up Time group mask. */ -#define NVM_FUSES_SUT_gp 2 /* Start-up Time group position. */ -#define NVM_FUSES_SUT0_bm (1<<2) /* Start-up Time bit 0 mask. */ -#define NVM_FUSES_SUT0_bp 2 /* Start-up Time bit 0 position. */ -#define NVM_FUSES_SUT1_bm (1<<3) /* Start-up Time bit 1 mask. */ -#define NVM_FUSES_SUT1_bp 3 /* Start-up Time bit 1 position. */ - -#define NVM_FUSES_WDLOCK_bm 0x02 /* Watchdog Timer Lock bit mask. */ -#define NVM_FUSES_WDLOCK_bp 1 /* Watchdog Timer Lock bit position. */ - -#define NVM_FUSES_JTAGEN_bm 0x01 /* JTAG Interface Enable bit mask. */ -#define NVM_FUSES_JTAGEN_bp 0 /* JTAG Interface Enable bit position. */ - - -/* NVM_FUSES.FUSEBYTE5 bit masks and bit positions */ -#define NVM_FUSES_BODACT_gm 0x30 /* BOD Operation in Active Mode group mask. */ -#define NVM_FUSES_BODACT_gp 4 /* BOD Operation in Active Mode group position. */ -#define NVM_FUSES_BODACT0_bm (1<<4) /* BOD Operation in Active Mode bit 0 mask. */ -#define NVM_FUSES_BODACT0_bp 4 /* BOD Operation in Active Mode bit 0 position. */ -#define NVM_FUSES_BODACT1_bm (1<<5) /* BOD Operation in Active Mode bit 1 mask. */ -#define NVM_FUSES_BODACT1_bp 5 /* BOD Operation in Active Mode bit 1 position. */ - -#define NVM_FUSES_EESAVE_bm 0x08 /* Preserve EEPROM Through Chip Erase bit mask. */ -#define NVM_FUSES_EESAVE_bp 3 /* Preserve EEPROM Through Chip Erase bit position. */ - -#define NVM_FUSES_BODLVL_gm 0x07 /* Brown Out Detection Voltage Level group mask. */ -#define NVM_FUSES_BODLVL_gp 0 /* Brown Out Detection Voltage Level group position. */ -#define NVM_FUSES_BODLVL0_bm (1<<0) /* Brown Out Detection Voltage Level bit 0 mask. */ -#define NVM_FUSES_BODLVL0_bp 0 /* Brown Out Detection Voltage Level bit 0 position. */ -#define NVM_FUSES_BODLVL1_bm (1<<1) /* Brown Out Detection Voltage Level bit 1 mask. */ -#define NVM_FUSES_BODLVL1_bp 1 /* Brown Out Detection Voltage Level bit 1 position. */ -#define NVM_FUSES_BODLVL2_bm (1<<2) /* Brown Out Detection Voltage Level bit 2 mask. */ -#define NVM_FUSES_BODLVL2_bp 2 /* Brown Out Detection Voltage Level bit 2 position. */ - - -/* AC - Analog Comparator */ -/* AC.AC0CTRL bit masks and bit positions */ -#define AC_INTMODE_gm 0xC0 /* Interrupt Mode group mask. */ -#define AC_INTMODE_gp 6 /* Interrupt Mode group position. */ -#define AC_INTMODE0_bm (1<<6) /* Interrupt Mode bit 0 mask. */ -#define AC_INTMODE0_bp 6 /* Interrupt Mode bit 0 position. */ -#define AC_INTMODE1_bm (1<<7) /* Interrupt Mode bit 1 mask. */ -#define AC_INTMODE1_bp 7 /* Interrupt Mode bit 1 position. */ - -#define AC_INTLVL_gm 0x30 /* Interrupt Level group mask. */ -#define AC_INTLVL_gp 4 /* Interrupt Level group position. */ -#define AC_INTLVL0_bm (1<<4) /* Interrupt Level bit 0 mask. */ -#define AC_INTLVL0_bp 4 /* Interrupt Level bit 0 position. */ -#define AC_INTLVL1_bm (1<<5) /* Interrupt Level bit 1 mask. */ -#define AC_INTLVL1_bp 5 /* Interrupt Level bit 1 position. */ - -#define AC_HSMODE_bm 0x08 /* High-speed Mode bit mask. */ -#define AC_HSMODE_bp 3 /* High-speed Mode bit position. */ - -#define AC_HYSMODE_gm 0x06 /* Hysteresis Mode group mask. */ -#define AC_HYSMODE_gp 1 /* Hysteresis Mode group position. */ -#define AC_HYSMODE0_bm (1<<1) /* Hysteresis Mode bit 0 mask. */ -#define AC_HYSMODE0_bp 1 /* Hysteresis Mode bit 0 position. */ -#define AC_HYSMODE1_bm (1<<2) /* Hysteresis Mode bit 1 mask. */ -#define AC_HYSMODE1_bp 2 /* Hysteresis Mode bit 1 position. */ - -#define AC_ENABLE_bm 0x01 /* Enable bit mask. */ -#define AC_ENABLE_bp 0 /* Enable bit position. */ - - -/* AC.AC1CTRL bit masks and bit positions */ -/* AC_INTMODE_gm Predefined. */ -/* AC_INTMODE_gp Predefined. */ -/* AC_INTMODE0_bm Predefined. */ -/* AC_INTMODE0_bp Predefined. */ -/* AC_INTMODE1_bm Predefined. */ -/* AC_INTMODE1_bp Predefined. */ - -/* AC_INTLVL_gm Predefined. */ -/* AC_INTLVL_gp Predefined. */ -/* AC_INTLVL0_bm Predefined. */ -/* AC_INTLVL0_bp Predefined. */ -/* AC_INTLVL1_bm Predefined. */ -/* AC_INTLVL1_bp Predefined. */ - -/* AC_HSMODE_bm Predefined. */ -/* AC_HSMODE_bp Predefined. */ - -/* AC_HYSMODE_gm Predefined. */ -/* AC_HYSMODE_gp Predefined. */ -/* AC_HYSMODE0_bm Predefined. */ -/* AC_HYSMODE0_bp Predefined. */ -/* AC_HYSMODE1_bm Predefined. */ -/* AC_HYSMODE1_bp Predefined. */ - -/* AC_ENABLE_bm Predefined. */ -/* AC_ENABLE_bp Predefined. */ - - -/* AC.AC0MUXCTRL bit masks and bit positions */ -#define AC_MUXPOS_gm 0x38 /* MUX Positive Input group mask. */ -#define AC_MUXPOS_gp 3 /* MUX Positive Input group position. */ -#define AC_MUXPOS0_bm (1<<3) /* MUX Positive Input bit 0 mask. */ -#define AC_MUXPOS0_bp 3 /* MUX Positive Input bit 0 position. */ -#define AC_MUXPOS1_bm (1<<4) /* MUX Positive Input bit 1 mask. */ -#define AC_MUXPOS1_bp 4 /* MUX Positive Input bit 1 position. */ -#define AC_MUXPOS2_bm (1<<5) /* MUX Positive Input bit 2 mask. */ -#define AC_MUXPOS2_bp 5 /* MUX Positive Input bit 2 position. */ - -#define AC_MUXNEG_gm 0x07 /* MUX Negative Input group mask. */ -#define AC_MUXNEG_gp 0 /* MUX Negative Input group position. */ -#define AC_MUXNEG0_bm (1<<0) /* MUX Negative Input bit 0 mask. */ -#define AC_MUXNEG0_bp 0 /* MUX Negative Input bit 0 position. */ -#define AC_MUXNEG1_bm (1<<1) /* MUX Negative Input bit 1 mask. */ -#define AC_MUXNEG1_bp 1 /* MUX Negative Input bit 1 position. */ -#define AC_MUXNEG2_bm (1<<2) /* MUX Negative Input bit 2 mask. */ -#define AC_MUXNEG2_bp 2 /* MUX Negative Input bit 2 position. */ - - -/* AC.AC1MUXCTRL bit masks and bit positions */ -/* AC_MUXPOS_gm Predefined. */ -/* AC_MUXPOS_gp Predefined. */ -/* AC_MUXPOS0_bm Predefined. */ -/* AC_MUXPOS0_bp Predefined. */ -/* AC_MUXPOS1_bm Predefined. */ -/* AC_MUXPOS1_bp Predefined. */ -/* AC_MUXPOS2_bm Predefined. */ -/* AC_MUXPOS2_bp Predefined. */ - -/* AC_MUXNEG_gm Predefined. */ -/* AC_MUXNEG_gp Predefined. */ -/* AC_MUXNEG0_bm Predefined. */ -/* AC_MUXNEG0_bp Predefined. */ -/* AC_MUXNEG1_bm Predefined. */ -/* AC_MUXNEG1_bp Predefined. */ -/* AC_MUXNEG2_bm Predefined. */ -/* AC_MUXNEG2_bp Predefined. */ - - -/* AC.CTRLA bit masks and bit positions */ -#define AC_AC0OUT_bm 0x01 /* Comparator 0 Output Enable bit mask. */ -#define AC_AC0OUT_bp 0 /* Comparator 0 Output Enable bit position. */ - - -/* AC.CTRLB bit masks and bit positions */ -#define AC_SCALEFAC_gm 0x3F /* VCC Voltage Scaler Factor group mask. */ -#define AC_SCALEFAC_gp 0 /* VCC Voltage Scaler Factor group position. */ -#define AC_SCALEFAC0_bm (1<<0) /* VCC Voltage Scaler Factor bit 0 mask. */ -#define AC_SCALEFAC0_bp 0 /* VCC Voltage Scaler Factor bit 0 position. */ -#define AC_SCALEFAC1_bm (1<<1) /* VCC Voltage Scaler Factor bit 1 mask. */ -#define AC_SCALEFAC1_bp 1 /* VCC Voltage Scaler Factor bit 1 position. */ -#define AC_SCALEFAC2_bm (1<<2) /* VCC Voltage Scaler Factor bit 2 mask. */ -#define AC_SCALEFAC2_bp 2 /* VCC Voltage Scaler Factor bit 2 position. */ -#define AC_SCALEFAC3_bm (1<<3) /* VCC Voltage Scaler Factor bit 3 mask. */ -#define AC_SCALEFAC3_bp 3 /* VCC Voltage Scaler Factor bit 3 position. */ -#define AC_SCALEFAC4_bm (1<<4) /* VCC Voltage Scaler Factor bit 4 mask. */ -#define AC_SCALEFAC4_bp 4 /* VCC Voltage Scaler Factor bit 4 position. */ -#define AC_SCALEFAC5_bm (1<<5) /* VCC Voltage Scaler Factor bit 5 mask. */ -#define AC_SCALEFAC5_bp 5 /* VCC Voltage Scaler Factor bit 5 position. */ - - -/* AC.WINCTRL bit masks and bit positions */ -#define AC_WEN_bm 0x10 /* Window Mode Enable bit mask. */ -#define AC_WEN_bp 4 /* Window Mode Enable bit position. */ - -#define AC_WINTMODE_gm 0x0C /* Window Interrupt Mode group mask. */ -#define AC_WINTMODE_gp 2 /* Window Interrupt Mode group position. */ -#define AC_WINTMODE0_bm (1<<2) /* Window Interrupt Mode bit 0 mask. */ -#define AC_WINTMODE0_bp 2 /* Window Interrupt Mode bit 0 position. */ -#define AC_WINTMODE1_bm (1<<3) /* Window Interrupt Mode bit 1 mask. */ -#define AC_WINTMODE1_bp 3 /* Window Interrupt Mode bit 1 position. */ - -#define AC_WINTLVL_gm 0x03 /* Window Interrupt Level group mask. */ -#define AC_WINTLVL_gp 0 /* Window Interrupt Level group position. */ -#define AC_WINTLVL0_bm (1<<0) /* Window Interrupt Level bit 0 mask. */ -#define AC_WINTLVL0_bp 0 /* Window Interrupt Level bit 0 position. */ -#define AC_WINTLVL1_bm (1<<1) /* Window Interrupt Level bit 1 mask. */ -#define AC_WINTLVL1_bp 1 /* Window Interrupt Level bit 1 position. */ - - -/* AC.STATUS bit masks and bit positions */ -#define AC_WSTATE_gm 0xC0 /* Window Mode State group mask. */ -#define AC_WSTATE_gp 6 /* Window Mode State group position. */ -#define AC_WSTATE0_bm (1<<6) /* Window Mode State bit 0 mask. */ -#define AC_WSTATE0_bp 6 /* Window Mode State bit 0 position. */ -#define AC_WSTATE1_bm (1<<7) /* Window Mode State bit 1 mask. */ -#define AC_WSTATE1_bp 7 /* Window Mode State bit 1 position. */ - -#define AC_AC1STATE_bm 0x20 /* Comparator 1 State bit mask. */ -#define AC_AC1STATE_bp 5 /* Comparator 1 State bit position. */ - -#define AC_AC0STATE_bm 0x10 /* Comparator 0 State bit mask. */ -#define AC_AC0STATE_bp 4 /* Comparator 0 State bit position. */ - -#define AC_WIF_bm 0x04 /* Window Mode Interrupt Flag bit mask. */ -#define AC_WIF_bp 2 /* Window Mode Interrupt Flag bit position. */ - -#define AC_AC1IF_bm 0x02 /* Comparator 1 Interrupt Flag bit mask. */ -#define AC_AC1IF_bp 1 /* Comparator 1 Interrupt Flag bit position. */ - -#define AC_AC0IF_bm 0x01 /* Comparator 0 Interrupt Flag bit mask. */ -#define AC_AC0IF_bp 0 /* Comparator 0 Interrupt Flag bit position. */ - - -/* ADC - Analog/Digital Converter */ -/* ADC_CH.CTRL bit masks and bit positions */ -#define ADC_CH_START_bm 0x80 /* Channel Start Conversion bit mask. */ -#define ADC_CH_START_bp 7 /* Channel Start Conversion bit position. */ - -#define ADC_CH_GAINFAC_gm 0x1C /* Gain Factor group mask. */ -#define ADC_CH_GAINFAC_gp 2 /* Gain Factor group position. */ -#define ADC_CH_GAINFAC0_bm (1<<2) /* Gain Factor bit 0 mask. */ -#define ADC_CH_GAINFAC0_bp 2 /* Gain Factor bit 0 position. */ -#define ADC_CH_GAINFAC1_bm (1<<3) /* Gain Factor bit 1 mask. */ -#define ADC_CH_GAINFAC1_bp 3 /* Gain Factor bit 1 position. */ -#define ADC_CH_GAINFAC2_bm (1<<4) /* Gain Factor bit 2 mask. */ -#define ADC_CH_GAINFAC2_bp 4 /* Gain Factor bit 2 position. */ - -#define ADC_CH_INPUTMODE_gm 0x03 /* Input Mode Select group mask. */ -#define ADC_CH_INPUTMODE_gp 0 /* Input Mode Select group position. */ -#define ADC_CH_INPUTMODE0_bm (1<<0) /* Input Mode Select bit 0 mask. */ -#define ADC_CH_INPUTMODE0_bp 0 /* Input Mode Select bit 0 position. */ -#define ADC_CH_INPUTMODE1_bm (1<<1) /* Input Mode Select bit 1 mask. */ -#define ADC_CH_INPUTMODE1_bp 1 /* Input Mode Select bit 1 position. */ - - -/* ADC_CH.MUXCTRL bit masks and bit positions */ -#define ADC_CH_MUXPOS_gm 0x78 /* Positive Input Select group mask. */ -#define ADC_CH_MUXPOS_gp 3 /* Positive Input Select group position. */ -#define ADC_CH_MUXPOS0_bm (1<<3) /* Positive Input Select bit 0 mask. */ -#define ADC_CH_MUXPOS0_bp 3 /* Positive Input Select bit 0 position. */ -#define ADC_CH_MUXPOS1_bm (1<<4) /* Positive Input Select bit 1 mask. */ -#define ADC_CH_MUXPOS1_bp 4 /* Positive Input Select bit 1 position. */ -#define ADC_CH_MUXPOS2_bm (1<<5) /* Positive Input Select bit 2 mask. */ -#define ADC_CH_MUXPOS2_bp 5 /* Positive Input Select bit 2 position. */ -#define ADC_CH_MUXPOS3_bm (1<<6) /* Positive Input Select bit 3 mask. */ -#define ADC_CH_MUXPOS3_bp 6 /* Positive Input Select bit 3 position. */ - -#define ADC_CH_MUXINT_gm 0x78 /* Internal Input Select group mask. */ -#define ADC_CH_MUXINT_gp 3 /* Internal Input Select group position. */ -#define ADC_CH_MUXINT0_bm (1<<3) /* Internal Input Select bit 0 mask. */ -#define ADC_CH_MUXINT0_bp 3 /* Internal Input Select bit 0 position. */ -#define ADC_CH_MUXINT1_bm (1<<4) /* Internal Input Select bit 1 mask. */ -#define ADC_CH_MUXINT1_bp 4 /* Internal Input Select bit 1 position. */ -#define ADC_CH_MUXINT2_bm (1<<5) /* Internal Input Select bit 2 mask. */ -#define ADC_CH_MUXINT2_bp 5 /* Internal Input Select bit 2 position. */ -#define ADC_CH_MUXINT3_bm (1<<6) /* Internal Input Select bit 3 mask. */ -#define ADC_CH_MUXINT3_bp 6 /* Internal Input Select bit 3 position. */ - -#define ADC_CH_MUXNEG_gm 0x03 /* Negative Input Select group mask. */ -#define ADC_CH_MUXNEG_gp 0 /* Negative Input Select group position. */ -#define ADC_CH_MUXNEG0_bm (1<<0) /* Negative Input Select bit 0 mask. */ -#define ADC_CH_MUXNEG0_bp 0 /* Negative Input Select bit 0 position. */ -#define ADC_CH_MUXNEG1_bm (1<<1) /* Negative Input Select bit 1 mask. */ -#define ADC_CH_MUXNEG1_bp 1 /* Negative Input Select bit 1 position. */ - - -/* ADC_CH.INTCTRL bit masks and bit positions */ -#define ADC_CH_INTMODE_gm 0x0C /* Interrupt Mode group mask. */ -#define ADC_CH_INTMODE_gp 2 /* Interrupt Mode group position. */ -#define ADC_CH_INTMODE0_bm (1<<2) /* Interrupt Mode bit 0 mask. */ -#define ADC_CH_INTMODE0_bp 2 /* Interrupt Mode bit 0 position. */ -#define ADC_CH_INTMODE1_bm (1<<3) /* Interrupt Mode bit 1 mask. */ -#define ADC_CH_INTMODE1_bp 3 /* Interrupt Mode bit 1 position. */ - -#define ADC_CH_INTLVL_gm 0x03 /* Interrupt Level group mask. */ -#define ADC_CH_INTLVL_gp 0 /* Interrupt Level group position. */ -#define ADC_CH_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */ -#define ADC_CH_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */ -#define ADC_CH_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ -#define ADC_CH_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */ - - -/* ADC_CH.INTFLAGS bit masks and bit positions */ -#define ADC_CH_CHIF_bm 0x01 /* Channel Interrupt Flag bit mask. */ -#define ADC_CH_CHIF_bp 0 /* Channel Interrupt Flag bit position. */ - - -/* ADC.CTRLA bit masks and bit positions */ -#define ADC_DMASEL_gm 0xC0 /* DMA Selection group mask. */ -#define ADC_DMASEL_gp 6 /* DMA Selection group position. */ -#define ADC_DMASEL0_bm (1<<6) /* DMA Selection bit 0 mask. */ -#define ADC_DMASEL0_bp 6 /* DMA Selection bit 0 position. */ -#define ADC_DMASEL1_bm (1<<7) /* DMA Selection bit 1 mask. */ -#define ADC_DMASEL1_bp 7 /* DMA Selection bit 1 position. */ - -#define ADC_CH3START_bm 0x20 /* Channel 3 Start Conversion bit mask. */ -#define ADC_CH3START_bp 5 /* Channel 3 Start Conversion bit position. */ - -#define ADC_CH2START_bm 0x10 /* Channel 2 Start Conversion bit mask. */ -#define ADC_CH2START_bp 4 /* Channel 2 Start Conversion bit position. */ - -#define ADC_CH1START_bm 0x08 /* Channel 1 Start Conversion bit mask. */ -#define ADC_CH1START_bp 3 /* Channel 1 Start Conversion bit position. */ - -#define ADC_CH0START_bm 0x04 /* Channel 0 Start Conversion bit mask. */ -#define ADC_CH0START_bp 2 /* Channel 0 Start Conversion bit position. */ - -#define ADC_FLUSH_bm 0x02 /* Flush Pipeline bit mask. */ -#define ADC_FLUSH_bp 1 /* Flush Pipeline bit position. */ - -#define ADC_ENABLE_bm 0x01 /* Enable ADC bit mask. */ -#define ADC_ENABLE_bp 0 /* Enable ADC bit position. */ - - -/* ADC.CTRLB bit masks and bit positions */ -#define ADC_CONMODE_bm 0x10 /* Conversion Mode bit mask. */ -#define ADC_CONMODE_bp 4 /* Conversion Mode bit position. */ - -#define ADC_FREERUN_bm 0x08 /* Free Running Mode Enable bit mask. */ -#define ADC_FREERUN_bp 3 /* Free Running Mode Enable bit position. */ - -#define ADC_RESOLUTION_gm 0x06 /* Result Resolution group mask. */ -#define ADC_RESOLUTION_gp 1 /* Result Resolution group position. */ -#define ADC_RESOLUTION0_bm (1<<1) /* Result Resolution bit 0 mask. */ -#define ADC_RESOLUTION0_bp 1 /* Result Resolution bit 0 position. */ -#define ADC_RESOLUTION1_bm (1<<2) /* Result Resolution bit 1 mask. */ -#define ADC_RESOLUTION1_bp 2 /* Result Resolution bit 1 position. */ - - -/* ADC.REFCTRL bit masks and bit positions */ -#define ADC_REFSEL_gm 0x30 /* Reference Selection group mask. */ -#define ADC_REFSEL_gp 4 /* Reference Selection group position. */ -#define ADC_REFSEL0_bm (1<<4) /* Reference Selection bit 0 mask. */ -#define ADC_REFSEL0_bp 4 /* Reference Selection bit 0 position. */ -#define ADC_REFSEL1_bm (1<<5) /* Reference Selection bit 1 mask. */ -#define ADC_REFSEL1_bp 5 /* Reference Selection bit 1 position. */ - -#define ADC_BANDGAP_bm 0x02 /* Bandgap enable bit mask. */ -#define ADC_BANDGAP_bp 1 /* Bandgap enable bit position. */ - -#define ADC_TEMPREF_bm 0x01 /* Temperature Reference Enable bit mask. */ -#define ADC_TEMPREF_bp 0 /* Temperature Reference Enable bit position. */ - - -/* ADC.EVCTRL bit masks and bit positions */ -#define ADC_SWEEP_gm 0xC0 /* Channel Sweep Selection group mask. */ -#define ADC_SWEEP_gp 6 /* Channel Sweep Selection group position. */ -#define ADC_SWEEP0_bm (1<<6) /* Channel Sweep Selection bit 0 mask. */ -#define ADC_SWEEP0_bp 6 /* Channel Sweep Selection bit 0 position. */ -#define ADC_SWEEP1_bm (1<<7) /* Channel Sweep Selection bit 1 mask. */ -#define ADC_SWEEP1_bp 7 /* Channel Sweep Selection bit 1 position. */ - -#define ADC_EVSEL_gm 0x38 /* Event Input Select group mask. */ -#define ADC_EVSEL_gp 3 /* Event Input Select group position. */ -#define ADC_EVSEL0_bm (1<<3) /* Event Input Select bit 0 mask. */ -#define ADC_EVSEL0_bp 3 /* Event Input Select bit 0 position. */ -#define ADC_EVSEL1_bm (1<<4) /* Event Input Select bit 1 mask. */ -#define ADC_EVSEL1_bp 4 /* Event Input Select bit 1 position. */ -#define ADC_EVSEL2_bm (1<<5) /* Event Input Select bit 2 mask. */ -#define ADC_EVSEL2_bp 5 /* Event Input Select bit 2 position. */ - -#define ADC_EVACT_gm 0x07 /* Event Action Select group mask. */ -#define ADC_EVACT_gp 0 /* Event Action Select group position. */ -#define ADC_EVACT0_bm (1<<0) /* Event Action Select bit 0 mask. */ -#define ADC_EVACT0_bp 0 /* Event Action Select bit 0 position. */ -#define ADC_EVACT1_bm (1<<1) /* Event Action Select bit 1 mask. */ -#define ADC_EVACT1_bp 1 /* Event Action Select bit 1 position. */ -#define ADC_EVACT2_bm (1<<2) /* Event Action Select bit 2 mask. */ -#define ADC_EVACT2_bp 2 /* Event Action Select bit 2 position. */ - - -/* ADC.PRESCALER bit masks and bit positions */ -#define ADC_PRESCALER_gm 0x07 /* Clock Prescaler Selection group mask. */ -#define ADC_PRESCALER_gp 0 /* Clock Prescaler Selection group position. */ -#define ADC_PRESCALER0_bm (1<<0) /* Clock Prescaler Selection bit 0 mask. */ -#define ADC_PRESCALER0_bp 0 /* Clock Prescaler Selection bit 0 position. */ -#define ADC_PRESCALER1_bm (1<<1) /* Clock Prescaler Selection bit 1 mask. */ -#define ADC_PRESCALER1_bp 1 /* Clock Prescaler Selection bit 1 position. */ -#define ADC_PRESCALER2_bm (1<<2) /* Clock Prescaler Selection bit 2 mask. */ -#define ADC_PRESCALER2_bp 2 /* Clock Prescaler Selection bit 2 position. */ - - -/* ADC.INTFLAGS bit masks and bit positions */ -#define ADC_CH3IF_bm 0x08 /* Channel 3 Interrupt Flag bit mask. */ -#define ADC_CH3IF_bp 3 /* Channel 3 Interrupt Flag bit position. */ - -#define ADC_CH2IF_bm 0x04 /* Channel 2 Interrupt Flag bit mask. */ -#define ADC_CH2IF_bp 2 /* Channel 2 Interrupt Flag bit position. */ - -#define ADC_CH1IF_bm 0x02 /* Channel 1 Interrupt Flag bit mask. */ -#define ADC_CH1IF_bp 1 /* Channel 1 Interrupt Flag bit position. */ - -#define ADC_CH0IF_bm 0x01 /* Channel 0 Interrupt Flag bit mask. */ -#define ADC_CH0IF_bp 0 /* Channel 0 Interrupt Flag bit position. */ - - -/* DAC - Digital/Analog Converter */ -/* DAC.CTRLA bit masks and bit positions */ -#define DAC_IDOEN_bm 0x10 /* Internal Output Enable bit mask. */ -#define DAC_IDOEN_bp 4 /* Internal Output Enable bit position. */ - -#define DAC_CH1EN_bm 0x08 /* Channel 1 Output Enable bit mask. */ -#define DAC_CH1EN_bp 3 /* Channel 1 Output Enable bit position. */ - -#define DAC_CH0EN_bm 0x04 /* Channel 0 Output Enable bit mask. */ -#define DAC_CH0EN_bp 2 /* Channel 0 Output Enable bit position. */ - -#define DAC_LPMODE_bm 0x02 /* Low Power Mode bit mask. */ -#define DAC_LPMODE_bp 1 /* Low Power Mode bit position. */ - -#define DAC_ENABLE_bm 0x01 /* Enable bit mask. */ -#define DAC_ENABLE_bp 0 /* Enable bit position. */ - - -/* DAC.CTRLB bit masks and bit positions */ -#define DAC_CHSEL_gm 0x60 /* Channel Select group mask. */ -#define DAC_CHSEL_gp 5 /* Channel Select group position. */ -#define DAC_CHSEL0_bm (1<<5) /* Channel Select bit 0 mask. */ -#define DAC_CHSEL0_bp 5 /* Channel Select bit 0 position. */ -#define DAC_CHSEL1_bm (1<<6) /* Channel Select bit 1 mask. */ -#define DAC_CHSEL1_bp 6 /* Channel Select bit 1 position. */ - -#define DAC_CH1TRIG_bm 0x02 /* Channel 1 Event Trig Enable bit mask. */ -#define DAC_CH1TRIG_bp 1 /* Channel 1 Event Trig Enable bit position. */ - -#define DAC_CH0TRIG_bm 0x01 /* Channel 0 Event Trig Enable bit mask. */ -#define DAC_CH0TRIG_bp 0 /* Channel 0 Event Trig Enable bit position. */ - - -/* DAC.CTRLC bit masks and bit positions */ -#define DAC_REFSEL_gm 0x18 /* Reference Select group mask. */ -#define DAC_REFSEL_gp 3 /* Reference Select group position. */ -#define DAC_REFSEL0_bm (1<<3) /* Reference Select bit 0 mask. */ -#define DAC_REFSEL0_bp 3 /* Reference Select bit 0 position. */ -#define DAC_REFSEL1_bm (1<<4) /* Reference Select bit 1 mask. */ -#define DAC_REFSEL1_bp 4 /* Reference Select bit 1 position. */ - -#define DAC_LEFTADJ_bm 0x01 /* Left-adjust Result bit mask. */ -#define DAC_LEFTADJ_bp 0 /* Left-adjust Result bit position. */ - - -/* DAC.EVCTRL bit masks and bit positions */ -#define DAC_EVSEL_gm 0x07 /* Event Input Selection group mask. */ -#define DAC_EVSEL_gp 0 /* Event Input Selection group position. */ -#define DAC_EVSEL0_bm (1<<0) /* Event Input Selection bit 0 mask. */ -#define DAC_EVSEL0_bp 0 /* Event Input Selection bit 0 position. */ -#define DAC_EVSEL1_bm (1<<1) /* Event Input Selection bit 1 mask. */ -#define DAC_EVSEL1_bp 1 /* Event Input Selection bit 1 position. */ -#define DAC_EVSEL2_bm (1<<2) /* Event Input Selection bit 2 mask. */ -#define DAC_EVSEL2_bp 2 /* Event Input Selection bit 2 position. */ - - -/* DAC.TIMCTRL bit masks and bit positions */ -#define DAC_CONINTVAL_gm 0x70 /* Conversion Intercal group mask. */ -#define DAC_CONINTVAL_gp 4 /* Conversion Intercal group position. */ -#define DAC_CONINTVAL0_bm (1<<4) /* Conversion Intercal bit 0 mask. */ -#define DAC_CONINTVAL0_bp 4 /* Conversion Intercal bit 0 position. */ -#define DAC_CONINTVAL1_bm (1<<5) /* Conversion Intercal bit 1 mask. */ -#define DAC_CONINTVAL1_bp 5 /* Conversion Intercal bit 1 position. */ -#define DAC_CONINTVAL2_bm (1<<6) /* Conversion Intercal bit 2 mask. */ -#define DAC_CONINTVAL2_bp 6 /* Conversion Intercal bit 2 position. */ - -#define DAC_REFRESH_gm 0x0F /* Refresh Timing Control group mask. */ -#define DAC_REFRESH_gp 0 /* Refresh Timing Control group position. */ -#define DAC_REFRESH0_bm (1<<0) /* Refresh Timing Control bit 0 mask. */ -#define DAC_REFRESH0_bp 0 /* Refresh Timing Control bit 0 position. */ -#define DAC_REFRESH1_bm (1<<1) /* Refresh Timing Control bit 1 mask. */ -#define DAC_REFRESH1_bp 1 /* Refresh Timing Control bit 1 position. */ -#define DAC_REFRESH2_bm (1<<2) /* Refresh Timing Control bit 2 mask. */ -#define DAC_REFRESH2_bp 2 /* Refresh Timing Control bit 2 position. */ -#define DAC_REFRESH3_bm (1<<3) /* Refresh Timing Control bit 3 mask. */ -#define DAC_REFRESH3_bp 3 /* Refresh Timing Control bit 3 position. */ - - -/* DAC.STATUS bit masks and bit positions */ -#define DAC_CH1DRE_bm 0x02 /* Channel 1 Data Register Empty bit mask. */ -#define DAC_CH1DRE_bp 1 /* Channel 1 Data Register Empty bit position. */ - -#define DAC_CH0DRE_bm 0x01 /* Channel 0 Data Register Empty bit mask. */ -#define DAC_CH0DRE_bp 0 /* Channel 0 Data Register Empty bit position. */ - - -/* RTC32 - 32-bit Real-Time Counter */ -/* RTC32.CTRL bit masks and bit positions */ -#define RTC32_ENABLE_bm 0x01 /* RTC enable bit mask. */ -#define RTC32_ENABLE_bp 0 /* RTC enable bit position. */ - - -/* RTC32.SYNCCTRL bit masks and bit positions */ -#define RTC32_SYNCCNT_bm 0x10 /* Synchronization Busy Flag bit mask. */ -#define RTC32_SYNCCNT_bp 4 /* Synchronization Busy Flag bit position. */ - -#define RTC32_SYNCBUSY_bm 0x01 /* Synchronization Busy Flag bit mask. */ -#define RTC32_SYNCBUSY_bp 0 /* Synchronization Busy Flag bit position. */ - - -/* RTC32.INTCTRL bit masks and bit positions */ -#define RTC32_COMPINTLVL_gm 0x0C /* Compare Match Interrupt Level group mask. */ -#define RTC32_COMPINTLVL_gp 2 /* Compare Match Interrupt Level group position. */ -#define RTC32_COMPINTLVL0_bm (1<<2) /* Compare Match Interrupt Level bit 0 mask. */ -#define RTC32_COMPINTLVL0_bp 2 /* Compare Match Interrupt Level bit 0 position. */ -#define RTC32_COMPINTLVL1_bm (1<<3) /* Compare Match Interrupt Level bit 1 mask. */ -#define RTC32_COMPINTLVL1_bp 3 /* Compare Match Interrupt Level bit 1 position. */ - -#define RTC32_OVFINTLVL_gm 0x03 /* Overflow Interrupt Level group mask. */ -#define RTC32_OVFINTLVL_gp 0 /* Overflow Interrupt Level group position. */ -#define RTC32_OVFINTLVL0_bm (1<<0) /* Overflow Interrupt Level bit 0 mask. */ -#define RTC32_OVFINTLVL0_bp 0 /* Overflow Interrupt Level bit 0 position. */ -#define RTC32_OVFINTLVL1_bm (1<<1) /* Overflow Interrupt Level bit 1 mask. */ -#define RTC32_OVFINTLVL1_bp 1 /* Overflow Interrupt Level bit 1 position. */ - - -/* RTC32.INTFLAGS bit masks and bit positions */ -#define RTC32_COMPIF_bm 0x02 /* Compare Match Interrupt Flag bit mask. */ -#define RTC32_COMPIF_bp 1 /* Compare Match Interrupt Flag bit position. */ - -#define RTC32_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ -#define RTC32_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ - - -/* EBI - External Bus Interface */ -/* EBI_CS.CTRLA bit masks and bit positions */ -#define EBI_CS_ASIZE_gm 0x7C /* Address Size group mask. */ -#define EBI_CS_ASIZE_gp 2 /* Address Size group position. */ -#define EBI_CS_ASIZE0_bm (1<<2) /* Address Size bit 0 mask. */ -#define EBI_CS_ASIZE0_bp 2 /* Address Size bit 0 position. */ -#define EBI_CS_ASIZE1_bm (1<<3) /* Address Size bit 1 mask. */ -#define EBI_CS_ASIZE1_bp 3 /* Address Size bit 1 position. */ -#define EBI_CS_ASIZE2_bm (1<<4) /* Address Size bit 2 mask. */ -#define EBI_CS_ASIZE2_bp 4 /* Address Size bit 2 position. */ -#define EBI_CS_ASIZE3_bm (1<<5) /* Address Size bit 3 mask. */ -#define EBI_CS_ASIZE3_bp 5 /* Address Size bit 3 position. */ -#define EBI_CS_ASIZE4_bm (1<<6) /* Address Size bit 4 mask. */ -#define EBI_CS_ASIZE4_bp 6 /* Address Size bit 4 position. */ - -#define EBI_CS_MODE_gm 0x03 /* Memory Mode group mask. */ -#define EBI_CS_MODE_gp 0 /* Memory Mode group position. */ -#define EBI_CS_MODE0_bm (1<<0) /* Memory Mode bit 0 mask. */ -#define EBI_CS_MODE0_bp 0 /* Memory Mode bit 0 position. */ -#define EBI_CS_MODE1_bm (1<<1) /* Memory Mode bit 1 mask. */ -#define EBI_CS_MODE1_bp 1 /* Memory Mode bit 1 position. */ - - -/* EBI_CS.CTRLB bit masks and bit positions */ -#define EBI_CS_SRWS_gm 0x07 /* SRAM Wait State Cycles group mask. */ -#define EBI_CS_SRWS_gp 0 /* SRAM Wait State Cycles group position. */ -#define EBI_CS_SRWS0_bm (1<<0) /* SRAM Wait State Cycles bit 0 mask. */ -#define EBI_CS_SRWS0_bp 0 /* SRAM Wait State Cycles bit 0 position. */ -#define EBI_CS_SRWS1_bm (1<<1) /* SRAM Wait State Cycles bit 1 mask. */ -#define EBI_CS_SRWS1_bp 1 /* SRAM Wait State Cycles bit 1 position. */ -#define EBI_CS_SRWS2_bm (1<<2) /* SRAM Wait State Cycles bit 2 mask. */ -#define EBI_CS_SRWS2_bp 2 /* SRAM Wait State Cycles bit 2 position. */ - -#define EBI_CS_SDINITDONE_bm 0x80 /* SDRAM Initialization Done bit mask. */ -#define EBI_CS_SDINITDONE_bp 7 /* SDRAM Initialization Done bit position. */ - -#define EBI_CS_SDSREN_bm 0x04 /* SDRAM Self-refresh Enable bit mask. */ -#define EBI_CS_SDSREN_bp 2 /* SDRAM Self-refresh Enable bit position. */ - -#define EBI_CS_SDMODE_gm 0x03 /* SDRAM Mode group mask. */ -#define EBI_CS_SDMODE_gp 0 /* SDRAM Mode group position. */ -#define EBI_CS_SDMODE0_bm (1<<0) /* SDRAM Mode bit 0 mask. */ -#define EBI_CS_SDMODE0_bp 0 /* SDRAM Mode bit 0 position. */ -#define EBI_CS_SDMODE1_bm (1<<1) /* SDRAM Mode bit 1 mask. */ -#define EBI_CS_SDMODE1_bp 1 /* SDRAM Mode bit 1 position. */ - - -/* EBI.CTRL bit masks and bit positions */ -#define EBI_SDDATAW_gm 0xC0 /* SDRAM Data Width Setting group mask. */ -#define EBI_SDDATAW_gp 6 /* SDRAM Data Width Setting group position. */ -#define EBI_SDDATAW0_bm (1<<6) /* SDRAM Data Width Setting bit 0 mask. */ -#define EBI_SDDATAW0_bp 6 /* SDRAM Data Width Setting bit 0 position. */ -#define EBI_SDDATAW1_bm (1<<7) /* SDRAM Data Width Setting bit 1 mask. */ -#define EBI_SDDATAW1_bp 7 /* SDRAM Data Width Setting bit 1 position. */ - -#define EBI_LPCMODE_gm 0x30 /* SRAM LPC Mode group mask. */ -#define EBI_LPCMODE_gp 4 /* SRAM LPC Mode group position. */ -#define EBI_LPCMODE0_bm (1<<4) /* SRAM LPC Mode bit 0 mask. */ -#define EBI_LPCMODE0_bp 4 /* SRAM LPC Mode bit 0 position. */ -#define EBI_LPCMODE1_bm (1<<5) /* SRAM LPC Mode bit 1 mask. */ -#define EBI_LPCMODE1_bp 5 /* SRAM LPC Mode bit 1 position. */ - -#define EBI_SRMODE_gm 0x0C /* SRAM Mode group mask. */ -#define EBI_SRMODE_gp 2 /* SRAM Mode group position. */ -#define EBI_SRMODE0_bm (1<<2) /* SRAM Mode bit 0 mask. */ -#define EBI_SRMODE0_bp 2 /* SRAM Mode bit 0 position. */ -#define EBI_SRMODE1_bm (1<<3) /* SRAM Mode bit 1 mask. */ -#define EBI_SRMODE1_bp 3 /* SRAM Mode bit 1 position. */ - -#define EBI_IFMODE_gm 0x03 /* Interface Mode group mask. */ -#define EBI_IFMODE_gp 0 /* Interface Mode group position. */ -#define EBI_IFMODE0_bm (1<<0) /* Interface Mode bit 0 mask. */ -#define EBI_IFMODE0_bp 0 /* Interface Mode bit 0 position. */ -#define EBI_IFMODE1_bm (1<<1) /* Interface Mode bit 1 mask. */ -#define EBI_IFMODE1_bp 1 /* Interface Mode bit 1 position. */ - - -/* EBI.SDRAMCTRLA bit masks and bit positions */ -#define EBI_SDCAS_bm 0x08 /* SDRAM CAS Latency Setting bit mask. */ -#define EBI_SDCAS_bp 3 /* SDRAM CAS Latency Setting bit position. */ - -#define EBI_SDROW_bm 0x04 /* SDRAM ROW Bits Setting bit mask. */ -#define EBI_SDROW_bp 2 /* SDRAM ROW Bits Setting bit position. */ - -#define EBI_SDCOL_gm 0x03 /* SDRAM Column Bits Setting group mask. */ -#define EBI_SDCOL_gp 0 /* SDRAM Column Bits Setting group position. */ -#define EBI_SDCOL0_bm (1<<0) /* SDRAM Column Bits Setting bit 0 mask. */ -#define EBI_SDCOL0_bp 0 /* SDRAM Column Bits Setting bit 0 position. */ -#define EBI_SDCOL1_bm (1<<1) /* SDRAM Column Bits Setting bit 1 mask. */ -#define EBI_SDCOL1_bp 1 /* SDRAM Column Bits Setting bit 1 position. */ - - -/* EBI.SDRAMCTRLB bit masks and bit positions */ -#define EBI_MRDLY_gm 0xC0 /* SDRAM Mode Register Delay group mask. */ -#define EBI_MRDLY_gp 6 /* SDRAM Mode Register Delay group position. */ -#define EBI_MRDLY0_bm (1<<6) /* SDRAM Mode Register Delay bit 0 mask. */ -#define EBI_MRDLY0_bp 6 /* SDRAM Mode Register Delay bit 0 position. */ -#define EBI_MRDLY1_bm (1<<7) /* SDRAM Mode Register Delay bit 1 mask. */ -#define EBI_MRDLY1_bp 7 /* SDRAM Mode Register Delay bit 1 position. */ - -#define EBI_ROWCYCDLY_gm 0x38 /* SDRAM Row Cycle Delay group mask. */ -#define EBI_ROWCYCDLY_gp 3 /* SDRAM Row Cycle Delay group position. */ -#define EBI_ROWCYCDLY0_bm (1<<3) /* SDRAM Row Cycle Delay bit 0 mask. */ -#define EBI_ROWCYCDLY0_bp 3 /* SDRAM Row Cycle Delay bit 0 position. */ -#define EBI_ROWCYCDLY1_bm (1<<4) /* SDRAM Row Cycle Delay bit 1 mask. */ -#define EBI_ROWCYCDLY1_bp 4 /* SDRAM Row Cycle Delay bit 1 position. */ -#define EBI_ROWCYCDLY2_bm (1<<5) /* SDRAM Row Cycle Delay bit 2 mask. */ -#define EBI_ROWCYCDLY2_bp 5 /* SDRAM Row Cycle Delay bit 2 position. */ - -#define EBI_RPDLY_gm 0x07 /* SDRAM Row-to-Precharge Delay group mask. */ -#define EBI_RPDLY_gp 0 /* SDRAM Row-to-Precharge Delay group position. */ -#define EBI_RPDLY0_bm (1<<0) /* SDRAM Row-to-Precharge Delay bit 0 mask. */ -#define EBI_RPDLY0_bp 0 /* SDRAM Row-to-Precharge Delay bit 0 position. */ -#define EBI_RPDLY1_bm (1<<1) /* SDRAM Row-to-Precharge Delay bit 1 mask. */ -#define EBI_RPDLY1_bp 1 /* SDRAM Row-to-Precharge Delay bit 1 position. */ -#define EBI_RPDLY2_bm (1<<2) /* SDRAM Row-to-Precharge Delay bit 2 mask. */ -#define EBI_RPDLY2_bp 2 /* SDRAM Row-to-Precharge Delay bit 2 position. */ - - -/* EBI.SDRAMCTRLC bit masks and bit positions */ -#define EBI_WRDLY_gm 0xC0 /* SDRAM Write Recovery Delay group mask. */ -#define EBI_WRDLY_gp 6 /* SDRAM Write Recovery Delay group position. */ -#define EBI_WRDLY0_bm (1<<6) /* SDRAM Write Recovery Delay bit 0 mask. */ -#define EBI_WRDLY0_bp 6 /* SDRAM Write Recovery Delay bit 0 position. */ -#define EBI_WRDLY1_bm (1<<7) /* SDRAM Write Recovery Delay bit 1 mask. */ -#define EBI_WRDLY1_bp 7 /* SDRAM Write Recovery Delay bit 1 position. */ - -#define EBI_ESRDLY_gm 0x38 /* SDRAM Exit-Self-refresh-to-Active Delay group mask. */ -#define EBI_ESRDLY_gp 3 /* SDRAM Exit-Self-refresh-to-Active Delay group position. */ -#define EBI_ESRDLY0_bm (1<<3) /* SDRAM Exit-Self-refresh-to-Active Delay bit 0 mask. */ -#define EBI_ESRDLY0_bp 3 /* SDRAM Exit-Self-refresh-to-Active Delay bit 0 position. */ -#define EBI_ESRDLY1_bm (1<<4) /* SDRAM Exit-Self-refresh-to-Active Delay bit 1 mask. */ -#define EBI_ESRDLY1_bp 4 /* SDRAM Exit-Self-refresh-to-Active Delay bit 1 position. */ -#define EBI_ESRDLY2_bm (1<<5) /* SDRAM Exit-Self-refresh-to-Active Delay bit 2 mask. */ -#define EBI_ESRDLY2_bp 5 /* SDRAM Exit-Self-refresh-to-Active Delay bit 2 position. */ - -#define EBI_ROWCOLDLY_gm 0x07 /* SDRAM Row-to-Column Delay group mask. */ -#define EBI_ROWCOLDLY_gp 0 /* SDRAM Row-to-Column Delay group position. */ -#define EBI_ROWCOLDLY0_bm (1<<0) /* SDRAM Row-to-Column Delay bit 0 mask. */ -#define EBI_ROWCOLDLY0_bp 0 /* SDRAM Row-to-Column Delay bit 0 position. */ -#define EBI_ROWCOLDLY1_bm (1<<1) /* SDRAM Row-to-Column Delay bit 1 mask. */ -#define EBI_ROWCOLDLY1_bp 1 /* SDRAM Row-to-Column Delay bit 1 position. */ -#define EBI_ROWCOLDLY2_bm (1<<2) /* SDRAM Row-to-Column Delay bit 2 mask. */ -#define EBI_ROWCOLDLY2_bp 2 /* SDRAM Row-to-Column Delay bit 2 position. */ - - -/* TWI - Two-Wire Interface */ -/* TWI_MASTER.CTRLA bit masks and bit positions */ -#define TWI_MASTER_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ -#define TWI_MASTER_INTLVL_gp 6 /* Interrupt Level group position. */ -#define TWI_MASTER_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ -#define TWI_MASTER_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ -#define TWI_MASTER_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ -#define TWI_MASTER_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ - -#define TWI_MASTER_RIEN_bm 0x20 /* Read Interrupt Enable bit mask. */ -#define TWI_MASTER_RIEN_bp 5 /* Read Interrupt Enable bit position. */ - -#define TWI_MASTER_WIEN_bm 0x10 /* Write Interrupt Enable bit mask. */ -#define TWI_MASTER_WIEN_bp 4 /* Write Interrupt Enable bit position. */ - -#define TWI_MASTER_ENABLE_bm 0x08 /* Enable TWI Master bit mask. */ -#define TWI_MASTER_ENABLE_bp 3 /* Enable TWI Master bit position. */ - - -/* TWI_MASTER.CTRLB bit masks and bit positions */ -#define TWI_MASTER_TIMEOUT_gm 0x0C /* Inactive Bus Timeout group mask. */ -#define TWI_MASTER_TIMEOUT_gp 2 /* Inactive Bus Timeout group position. */ -#define TWI_MASTER_TIMEOUT0_bm (1<<2) /* Inactive Bus Timeout bit 0 mask. */ -#define TWI_MASTER_TIMEOUT0_bp 2 /* Inactive Bus Timeout bit 0 position. */ -#define TWI_MASTER_TIMEOUT1_bm (1<<3) /* Inactive Bus Timeout bit 1 mask. */ -#define TWI_MASTER_TIMEOUT1_bp 3 /* Inactive Bus Timeout bit 1 position. */ - -#define TWI_MASTER_QCEN_bm 0x02 /* Quick Command Enable bit mask. */ -#define TWI_MASTER_QCEN_bp 1 /* Quick Command Enable bit position. */ - -#define TWI_MASTER_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ -#define TWI_MASTER_SMEN_bp 0 /* Smart Mode Enable bit position. */ - - -/* TWI_MASTER.CTRLC bit masks and bit positions */ -#define TWI_MASTER_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ -#define TWI_MASTER_ACKACT_bp 2 /* Acknowledge Action bit position. */ - -#define TWI_MASTER_CMD_gm 0x03 /* Command group mask. */ -#define TWI_MASTER_CMD_gp 0 /* Command group position. */ -#define TWI_MASTER_CMD0_bm (1<<0) /* Command bit 0 mask. */ -#define TWI_MASTER_CMD0_bp 0 /* Command bit 0 position. */ -#define TWI_MASTER_CMD1_bm (1<<1) /* Command bit 1 mask. */ -#define TWI_MASTER_CMD1_bp 1 /* Command bit 1 position. */ - - -/* TWI_MASTER.STATUS bit masks and bit positions */ -#define TWI_MASTER_RIF_bm 0x80 /* Read Interrupt Flag bit mask. */ -#define TWI_MASTER_RIF_bp 7 /* Read Interrupt Flag bit position. */ - -#define TWI_MASTER_WIF_bm 0x40 /* Write Interrupt Flag bit mask. */ -#define TWI_MASTER_WIF_bp 6 /* Write Interrupt Flag bit position. */ - -#define TWI_MASTER_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ -#define TWI_MASTER_CLKHOLD_bp 5 /* Clock Hold bit position. */ - -#define TWI_MASTER_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ -#define TWI_MASTER_RXACK_bp 4 /* Received Acknowledge bit position. */ - -#define TWI_MASTER_ARBLOST_bm 0x08 /* Arbitration Lost bit mask. */ -#define TWI_MASTER_ARBLOST_bp 3 /* Arbitration Lost bit position. */ - -#define TWI_MASTER_BUSERR_bm 0x04 /* Bus Error bit mask. */ -#define TWI_MASTER_BUSERR_bp 2 /* Bus Error bit position. */ - -#define TWI_MASTER_BUSSTATE_gm 0x03 /* Bus State group mask. */ -#define TWI_MASTER_BUSSTATE_gp 0 /* Bus State group position. */ -#define TWI_MASTER_BUSSTATE0_bm (1<<0) /* Bus State bit 0 mask. */ -#define TWI_MASTER_BUSSTATE0_bp 0 /* Bus State bit 0 position. */ -#define TWI_MASTER_BUSSTATE1_bm (1<<1) /* Bus State bit 1 mask. */ -#define TWI_MASTER_BUSSTATE1_bp 1 /* Bus State bit 1 position. */ - - -/* TWI_SLAVE.CTRLA bit masks and bit positions */ -#define TWI_SLAVE_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ -#define TWI_SLAVE_INTLVL_gp 6 /* Interrupt Level group position. */ -#define TWI_SLAVE_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ -#define TWI_SLAVE_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ -#define TWI_SLAVE_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ -#define TWI_SLAVE_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ - -#define TWI_SLAVE_DIEN_bm 0x20 /* Data Interrupt Enable bit mask. */ -#define TWI_SLAVE_DIEN_bp 5 /* Data Interrupt Enable bit position. */ - -#define TWI_SLAVE_APIEN_bm 0x10 /* Address/Stop Interrupt Enable bit mask. */ -#define TWI_SLAVE_APIEN_bp 4 /* Address/Stop Interrupt Enable bit position. */ - -#define TWI_SLAVE_ENABLE_bm 0x08 /* Enable TWI Slave bit mask. */ -#define TWI_SLAVE_ENABLE_bp 3 /* Enable TWI Slave bit position. */ - -#define TWI_SLAVE_PIEN_bm 0x04 /* Stop Interrupt Enable bit mask. */ -#define TWI_SLAVE_PIEN_bp 2 /* Stop Interrupt Enable bit position. */ - -#define TWI_SLAVE_PMEN_bm 0x02 /* Promiscuous Mode Enable bit mask. */ -#define TWI_SLAVE_PMEN_bp 1 /* Promiscuous Mode Enable bit position. */ - -#define TWI_SLAVE_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ -#define TWI_SLAVE_SMEN_bp 0 /* Smart Mode Enable bit position. */ - - -/* TWI_SLAVE.CTRLB bit masks and bit positions */ -#define TWI_SLAVE_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ -#define TWI_SLAVE_ACKACT_bp 2 /* Acknowledge Action bit position. */ - -#define TWI_SLAVE_CMD_gm 0x03 /* Command group mask. */ -#define TWI_SLAVE_CMD_gp 0 /* Command group position. */ -#define TWI_SLAVE_CMD0_bm (1<<0) /* Command bit 0 mask. */ -#define TWI_SLAVE_CMD0_bp 0 /* Command bit 0 position. */ -#define TWI_SLAVE_CMD1_bm (1<<1) /* Command bit 1 mask. */ -#define TWI_SLAVE_CMD1_bp 1 /* Command bit 1 position. */ - - -/* TWI_SLAVE.STATUS bit masks and bit positions */ -#define TWI_SLAVE_DIF_bm 0x80 /* Data Interrupt Flag bit mask. */ -#define TWI_SLAVE_DIF_bp 7 /* Data Interrupt Flag bit position. */ - -#define TWI_SLAVE_APIF_bm 0x40 /* Address/Stop Interrupt Flag bit mask. */ -#define TWI_SLAVE_APIF_bp 6 /* Address/Stop Interrupt Flag bit position. */ - -#define TWI_SLAVE_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ -#define TWI_SLAVE_CLKHOLD_bp 5 /* Clock Hold bit position. */ - -#define TWI_SLAVE_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ -#define TWI_SLAVE_RXACK_bp 4 /* Received Acknowledge bit position. */ - -#define TWI_SLAVE_COLL_bm 0x08 /* Collision bit mask. */ -#define TWI_SLAVE_COLL_bp 3 /* Collision bit position. */ - -#define TWI_SLAVE_BUSERR_bm 0x04 /* Bus Error bit mask. */ -#define TWI_SLAVE_BUSERR_bp 2 /* Bus Error bit position. */ - -#define TWI_SLAVE_DIR_bm 0x02 /* Read/Write Direction bit mask. */ -#define TWI_SLAVE_DIR_bp 1 /* Read/Write Direction bit position. */ - -#define TWI_SLAVE_AP_bm 0x01 /* Slave Address or Stop bit mask. */ -#define TWI_SLAVE_AP_bp 0 /* Slave Address or Stop bit position. */ - - -/* TWI_SLAVE.ADDRMASK bit masks and bit positions */ -#define TWI_SLAVE_ADDRMASK_gm 0xFE /* Address Mask group mask. */ -#define TWI_SLAVE_ADDRMASK_gp 1 /* Address Mask group position. */ -#define TWI_SLAVE_ADDRMASK0_bm (1<<1) /* Address Mask bit 0 mask. */ -#define TWI_SLAVE_ADDRMASK0_bp 1 /* Address Mask bit 0 position. */ -#define TWI_SLAVE_ADDRMASK1_bm (1<<2) /* Address Mask bit 1 mask. */ -#define TWI_SLAVE_ADDRMASK1_bp 2 /* Address Mask bit 1 position. */ -#define TWI_SLAVE_ADDRMASK2_bm (1<<3) /* Address Mask bit 2 mask. */ -#define TWI_SLAVE_ADDRMASK2_bp 3 /* Address Mask bit 2 position. */ -#define TWI_SLAVE_ADDRMASK3_bm (1<<4) /* Address Mask bit 3 mask. */ -#define TWI_SLAVE_ADDRMASK3_bp 4 /* Address Mask bit 3 position. */ -#define TWI_SLAVE_ADDRMASK4_bm (1<<5) /* Address Mask bit 4 mask. */ -#define TWI_SLAVE_ADDRMASK4_bp 5 /* Address Mask bit 4 position. */ -#define TWI_SLAVE_ADDRMASK5_bm (1<<6) /* Address Mask bit 5 mask. */ -#define TWI_SLAVE_ADDRMASK5_bp 6 /* Address Mask bit 5 position. */ -#define TWI_SLAVE_ADDRMASK6_bm (1<<7) /* Address Mask bit 6 mask. */ -#define TWI_SLAVE_ADDRMASK6_bp 7 /* Address Mask bit 6 position. */ - -#define TWI_SLAVE_ADDREN_bm 0x01 /* Address Enable bit mask. */ -#define TWI_SLAVE_ADDREN_bp 0 /* Address Enable bit position. */ - - -/* TWI.CTRL bit masks and bit positions */ -#define TWI_SDAHOLD_bm 0x02 /* SDA Hold Time Enable bit mask. */ -#define TWI_SDAHOLD_bp 1 /* SDA Hold Time Enable bit position. */ - -#define TWI_EDIEN_bm 0x01 /* External Driver Interface Enable bit mask. */ -#define TWI_EDIEN_bp 0 /* External Driver Interface Enable bit position. */ - - -/* PORT - Port Configuration */ -/* PORTCFG.VPCTRLA bit masks and bit positions */ -#define PORTCFG_VP1MAP_gm 0xF0 /* Virtual Port 1 Mapping group mask. */ -#define PORTCFG_VP1MAP_gp 4 /* Virtual Port 1 Mapping group position. */ -#define PORTCFG_VP1MAP0_bm (1<<4) /* Virtual Port 1 Mapping bit 0 mask. */ -#define PORTCFG_VP1MAP0_bp 4 /* Virtual Port 1 Mapping bit 0 position. */ -#define PORTCFG_VP1MAP1_bm (1<<5) /* Virtual Port 1 Mapping bit 1 mask. */ -#define PORTCFG_VP1MAP1_bp 5 /* Virtual Port 1 Mapping bit 1 position. */ -#define PORTCFG_VP1MAP2_bm (1<<6) /* Virtual Port 1 Mapping bit 2 mask. */ -#define PORTCFG_VP1MAP2_bp 6 /* Virtual Port 1 Mapping bit 2 position. */ -#define PORTCFG_VP1MAP3_bm (1<<7) /* Virtual Port 1 Mapping bit 3 mask. */ -#define PORTCFG_VP1MAP3_bp 7 /* Virtual Port 1 Mapping bit 3 position. */ - -#define PORTCFG_VP0MAP_gm 0x0F /* Virtual Port 0 Mapping group mask. */ -#define PORTCFG_VP0MAP_gp 0 /* Virtual Port 0 Mapping group position. */ -#define PORTCFG_VP0MAP0_bm (1<<0) /* Virtual Port 0 Mapping bit 0 mask. */ -#define PORTCFG_VP0MAP0_bp 0 /* Virtual Port 0 Mapping bit 0 position. */ -#define PORTCFG_VP0MAP1_bm (1<<1) /* Virtual Port 0 Mapping bit 1 mask. */ -#define PORTCFG_VP0MAP1_bp 1 /* Virtual Port 0 Mapping bit 1 position. */ -#define PORTCFG_VP0MAP2_bm (1<<2) /* Virtual Port 0 Mapping bit 2 mask. */ -#define PORTCFG_VP0MAP2_bp 2 /* Virtual Port 0 Mapping bit 2 position. */ -#define PORTCFG_VP0MAP3_bm (1<<3) /* Virtual Port 0 Mapping bit 3 mask. */ -#define PORTCFG_VP0MAP3_bp 3 /* Virtual Port 0 Mapping bit 3 position. */ - - -/* PORTCFG.VPCTRLB bit masks and bit positions */ -#define PORTCFG_VP3MAP_gm 0xF0 /* Virtual Port 3 Mapping group mask. */ -#define PORTCFG_VP3MAP_gp 4 /* Virtual Port 3 Mapping group position. */ -#define PORTCFG_VP3MAP0_bm (1<<4) /* Virtual Port 3 Mapping bit 0 mask. */ -#define PORTCFG_VP3MAP0_bp 4 /* Virtual Port 3 Mapping bit 0 position. */ -#define PORTCFG_VP3MAP1_bm (1<<5) /* Virtual Port 3 Mapping bit 1 mask. */ -#define PORTCFG_VP3MAP1_bp 5 /* Virtual Port 3 Mapping bit 1 position. */ -#define PORTCFG_VP3MAP2_bm (1<<6) /* Virtual Port 3 Mapping bit 2 mask. */ -#define PORTCFG_VP3MAP2_bp 6 /* Virtual Port 3 Mapping bit 2 position. */ -#define PORTCFG_VP3MAP3_bm (1<<7) /* Virtual Port 3 Mapping bit 3 mask. */ -#define PORTCFG_VP3MAP3_bp 7 /* Virtual Port 3 Mapping bit 3 position. */ - -#define PORTCFG_VP2MAP_gm 0x0F /* Virtual Port 2 Mapping group mask. */ -#define PORTCFG_VP2MAP_gp 0 /* Virtual Port 2 Mapping group position. */ -#define PORTCFG_VP2MAP0_bm (1<<0) /* Virtual Port 2 Mapping bit 0 mask. */ -#define PORTCFG_VP2MAP0_bp 0 /* Virtual Port 2 Mapping bit 0 position. */ -#define PORTCFG_VP2MAP1_bm (1<<1) /* Virtual Port 2 Mapping bit 1 mask. */ -#define PORTCFG_VP2MAP1_bp 1 /* Virtual Port 2 Mapping bit 1 position. */ -#define PORTCFG_VP2MAP2_bm (1<<2) /* Virtual Port 2 Mapping bit 2 mask. */ -#define PORTCFG_VP2MAP2_bp 2 /* Virtual Port 2 Mapping bit 2 position. */ -#define PORTCFG_VP2MAP3_bm (1<<3) /* Virtual Port 2 Mapping bit 3 mask. */ -#define PORTCFG_VP2MAP3_bp 3 /* Virtual Port 2 Mapping bit 3 position. */ - - -/* PORTCFG.CLKEVOUT bit masks and bit positions */ -#define PORTCFG_CLKOUT_gm 0x03 /* Clock Output Port group mask. */ -#define PORTCFG_CLKOUT_gp 0 /* Clock Output Port group position. */ -#define PORTCFG_CLKOUT0_bm (1<<0) /* Clock Output Port bit 0 mask. */ -#define PORTCFG_CLKOUT0_bp 0 /* Clock Output Port bit 0 position. */ -#define PORTCFG_CLKOUT1_bm (1<<1) /* Clock Output Port bit 1 mask. */ -#define PORTCFG_CLKOUT1_bp 1 /* Clock Output Port bit 1 position. */ - -#define PORTCFG_EVOUT_gm 0x30 /* Event Output Port group mask. */ -#define PORTCFG_EVOUT_gp 4 /* Event Output Port group position. */ -#define PORTCFG_EVOUT0_bm (1<<4) /* Event Output Port bit 0 mask. */ -#define PORTCFG_EVOUT0_bp 4 /* Event Output Port bit 0 position. */ -#define PORTCFG_EVOUT1_bm (1<<5) /* Event Output Port bit 1 mask. */ -#define PORTCFG_EVOUT1_bp 5 /* Event Output Port bit 1 position. */ - - -/* VPORT.INTFLAGS bit masks and bit positions */ -#define VPORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ -#define VPORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ - -#define VPORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ -#define VPORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ - - -/* PORT.INTCTRL bit masks and bit positions */ -#define PORT_INT1LVL_gm 0x0C /* Port Interrupt 1 Level group mask. */ -#define PORT_INT1LVL_gp 2 /* Port Interrupt 1 Level group position. */ -#define PORT_INT1LVL0_bm (1<<2) /* Port Interrupt 1 Level bit 0 mask. */ -#define PORT_INT1LVL0_bp 2 /* Port Interrupt 1 Level bit 0 position. */ -#define PORT_INT1LVL1_bm (1<<3) /* Port Interrupt 1 Level bit 1 mask. */ -#define PORT_INT1LVL1_bp 3 /* Port Interrupt 1 Level bit 1 position. */ - -#define PORT_INT0LVL_gm 0x03 /* Port Interrupt 0 Level group mask. */ -#define PORT_INT0LVL_gp 0 /* Port Interrupt 0 Level group position. */ -#define PORT_INT0LVL0_bm (1<<0) /* Port Interrupt 0 Level bit 0 mask. */ -#define PORT_INT0LVL0_bp 0 /* Port Interrupt 0 Level bit 0 position. */ -#define PORT_INT0LVL1_bm (1<<1) /* Port Interrupt 0 Level bit 1 mask. */ -#define PORT_INT0LVL1_bp 1 /* Port Interrupt 0 Level bit 1 position. */ - - -/* PORT.INTFLAGS bit masks and bit positions */ -#define PORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ -#define PORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ - -#define PORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ -#define PORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ - - -/* PORT.PIN0CTRL bit masks and bit positions */ -#define PORT_SRLEN_bm 0x80 /* Slew Rate Enable bit mask. */ -#define PORT_SRLEN_bp 7 /* Slew Rate Enable bit position. */ - -#define PORT_INVEN_bm 0x40 /* Inverted I/O Enable bit mask. */ -#define PORT_INVEN_bp 6 /* Inverted I/O Enable bit position. */ - -#define PORT_OPC_gm 0x38 /* Output/Pull Configuration group mask. */ -#define PORT_OPC_gp 3 /* Output/Pull Configuration group position. */ -#define PORT_OPC0_bm (1<<3) /* Output/Pull Configuration bit 0 mask. */ -#define PORT_OPC0_bp 3 /* Output/Pull Configuration bit 0 position. */ -#define PORT_OPC1_bm (1<<4) /* Output/Pull Configuration bit 1 mask. */ -#define PORT_OPC1_bp 4 /* Output/Pull Configuration bit 1 position. */ -#define PORT_OPC2_bm (1<<5) /* Output/Pull Configuration bit 2 mask. */ -#define PORT_OPC2_bp 5 /* Output/Pull Configuration bit 2 position. */ - -#define PORT_ISC_gm 0x07 /* Input/Sense Configuration group mask. */ -#define PORT_ISC_gp 0 /* Input/Sense Configuration group position. */ -#define PORT_ISC0_bm (1<<0) /* Input/Sense Configuration bit 0 mask. */ -#define PORT_ISC0_bp 0 /* Input/Sense Configuration bit 0 position. */ -#define PORT_ISC1_bm (1<<1) /* Input/Sense Configuration bit 1 mask. */ -#define PORT_ISC1_bp 1 /* Input/Sense Configuration bit 1 position. */ -#define PORT_ISC2_bm (1<<2) /* Input/Sense Configuration bit 2 mask. */ -#define PORT_ISC2_bp 2 /* Input/Sense Configuration bit 2 position. */ - - -/* PORT.PIN1CTRL bit masks and bit positions */ -/* PORT_SRLEN_bm Predefined. */ -/* PORT_SRLEN_bp Predefined. */ - -/* PORT_INVEN_bm Predefined. */ -/* PORT_INVEN_bp Predefined. */ - -/* PORT_OPC_gm Predefined. */ -/* PORT_OPC_gp Predefined. */ -/* PORT_OPC0_bm Predefined. */ -/* PORT_OPC0_bp Predefined. */ -/* PORT_OPC1_bm Predefined. */ -/* PORT_OPC1_bp Predefined. */ -/* PORT_OPC2_bm Predefined. */ -/* PORT_OPC2_bp Predefined. */ - -/* PORT_ISC_gm Predefined. */ -/* PORT_ISC_gp Predefined. */ -/* PORT_ISC0_bm Predefined. */ -/* PORT_ISC0_bp Predefined. */ -/* PORT_ISC1_bm Predefined. */ -/* PORT_ISC1_bp Predefined. */ -/* PORT_ISC2_bm Predefined. */ -/* PORT_ISC2_bp Predefined. */ - - -/* PORT.PIN2CTRL bit masks and bit positions */ -/* PORT_SRLEN_bm Predefined. */ -/* PORT_SRLEN_bp Predefined. */ - -/* PORT_INVEN_bm Predefined. */ -/* PORT_INVEN_bp Predefined. */ - -/* PORT_OPC_gm Predefined. */ -/* PORT_OPC_gp Predefined. */ -/* PORT_OPC0_bm Predefined. */ -/* PORT_OPC0_bp Predefined. */ -/* PORT_OPC1_bm Predefined. */ -/* PORT_OPC1_bp Predefined. */ -/* PORT_OPC2_bm Predefined. */ -/* PORT_OPC2_bp Predefined. */ - -/* PORT_ISC_gm Predefined. */ -/* PORT_ISC_gp Predefined. */ -/* PORT_ISC0_bm Predefined. */ -/* PORT_ISC0_bp Predefined. */ -/* PORT_ISC1_bm Predefined. */ -/* PORT_ISC1_bp Predefined. */ -/* PORT_ISC2_bm Predefined. */ -/* PORT_ISC2_bp Predefined. */ - - -/* PORT.PIN3CTRL bit masks and bit positions */ -/* PORT_SRLEN_bm Predefined. */ -/* PORT_SRLEN_bp Predefined. */ - -/* PORT_INVEN_bm Predefined. */ -/* PORT_INVEN_bp Predefined. */ - -/* PORT_OPC_gm Predefined. */ -/* PORT_OPC_gp Predefined. */ -/* PORT_OPC0_bm Predefined. */ -/* PORT_OPC0_bp Predefined. */ -/* PORT_OPC1_bm Predefined. */ -/* PORT_OPC1_bp Predefined. */ -/* PORT_OPC2_bm Predefined. */ -/* PORT_OPC2_bp Predefined. */ - -/* PORT_ISC_gm Predefined. */ -/* PORT_ISC_gp Predefined. */ -/* PORT_ISC0_bm Predefined. */ -/* PORT_ISC0_bp Predefined. */ -/* PORT_ISC1_bm Predefined. */ -/* PORT_ISC1_bp Predefined. */ -/* PORT_ISC2_bm Predefined. */ -/* PORT_ISC2_bp Predefined. */ - - -/* PORT.PIN4CTRL bit masks and bit positions */ -/* PORT_SRLEN_bm Predefined. */ -/* PORT_SRLEN_bp Predefined. */ - -/* PORT_INVEN_bm Predefined. */ -/* PORT_INVEN_bp Predefined. */ - -/* PORT_OPC_gm Predefined. */ -/* PORT_OPC_gp Predefined. */ -/* PORT_OPC0_bm Predefined. */ -/* PORT_OPC0_bp Predefined. */ -/* PORT_OPC1_bm Predefined. */ -/* PORT_OPC1_bp Predefined. */ -/* PORT_OPC2_bm Predefined. */ -/* PORT_OPC2_bp Predefined. */ - -/* PORT_ISC_gm Predefined. */ -/* PORT_ISC_gp Predefined. */ -/* PORT_ISC0_bm Predefined. */ -/* PORT_ISC0_bp Predefined. */ -/* PORT_ISC1_bm Predefined. */ -/* PORT_ISC1_bp Predefined. */ -/* PORT_ISC2_bm Predefined. */ -/* PORT_ISC2_bp Predefined. */ - - -/* PORT.PIN5CTRL bit masks and bit positions */ -/* PORT_SRLEN_bm Predefined. */ -/* PORT_SRLEN_bp Predefined. */ - -/* PORT_INVEN_bm Predefined. */ -/* PORT_INVEN_bp Predefined. */ - -/* PORT_OPC_gm Predefined. */ -/* PORT_OPC_gp Predefined. */ -/* PORT_OPC0_bm Predefined. */ -/* PORT_OPC0_bp Predefined. */ -/* PORT_OPC1_bm Predefined. */ -/* PORT_OPC1_bp Predefined. */ -/* PORT_OPC2_bm Predefined. */ -/* PORT_OPC2_bp Predefined. */ - -/* PORT_ISC_gm Predefined. */ -/* PORT_ISC_gp Predefined. */ -/* PORT_ISC0_bm Predefined. */ -/* PORT_ISC0_bp Predefined. */ -/* PORT_ISC1_bm Predefined. */ -/* PORT_ISC1_bp Predefined. */ -/* PORT_ISC2_bm Predefined. */ -/* PORT_ISC2_bp Predefined. */ - - -/* PORT.PIN6CTRL bit masks and bit positions */ -/* PORT_SRLEN_bm Predefined. */ -/* PORT_SRLEN_bp Predefined. */ - -/* PORT_INVEN_bm Predefined. */ -/* PORT_INVEN_bp Predefined. */ - -/* PORT_OPC_gm Predefined. */ -/* PORT_OPC_gp Predefined. */ -/* PORT_OPC0_bm Predefined. */ -/* PORT_OPC0_bp Predefined. */ -/* PORT_OPC1_bm Predefined. */ -/* PORT_OPC1_bp Predefined. */ -/* PORT_OPC2_bm Predefined. */ -/* PORT_OPC2_bp Predefined. */ - -/* PORT_ISC_gm Predefined. */ -/* PORT_ISC_gp Predefined. */ -/* PORT_ISC0_bm Predefined. */ -/* PORT_ISC0_bp Predefined. */ -/* PORT_ISC1_bm Predefined. */ -/* PORT_ISC1_bp Predefined. */ -/* PORT_ISC2_bm Predefined. */ -/* PORT_ISC2_bp Predefined. */ - - -/* PORT.PIN7CTRL bit masks and bit positions */ -/* PORT_SRLEN_bm Predefined. */ -/* PORT_SRLEN_bp Predefined. */ - -/* PORT_INVEN_bm Predefined. */ -/* PORT_INVEN_bp Predefined. */ - -/* PORT_OPC_gm Predefined. */ -/* PORT_OPC_gp Predefined. */ -/* PORT_OPC0_bm Predefined. */ -/* PORT_OPC0_bp Predefined. */ -/* PORT_OPC1_bm Predefined. */ -/* PORT_OPC1_bp Predefined. */ -/* PORT_OPC2_bm Predefined. */ -/* PORT_OPC2_bp Predefined. */ - -/* PORT_ISC_gm Predefined. */ -/* PORT_ISC_gp Predefined. */ -/* PORT_ISC0_bm Predefined. */ -/* PORT_ISC0_bp Predefined. */ -/* PORT_ISC1_bm Predefined. */ -/* PORT_ISC1_bp Predefined. */ -/* PORT_ISC2_bm Predefined. */ -/* PORT_ISC2_bp Predefined. */ - - -/* TC - 16-bit Timer/Counter With PWM */ -/* TC0.CTRLA bit masks and bit positions */ -#define TC0_CLKSEL_gm 0x0F /* Clock Selection group mask. */ -#define TC0_CLKSEL_gp 0 /* Clock Selection group position. */ -#define TC0_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ -#define TC0_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ -#define TC0_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ -#define TC0_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ -#define TC0_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ -#define TC0_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ -#define TC0_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ -#define TC0_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ - - -/* TC0.CTRLB bit masks and bit positions */ -#define TC0_CCDEN_bm 0x80 /* Compare or Capture D Enable bit mask. */ -#define TC0_CCDEN_bp 7 /* Compare or Capture D Enable bit position. */ - -#define TC0_CCCEN_bm 0x40 /* Compare or Capture C Enable bit mask. */ -#define TC0_CCCEN_bp 6 /* Compare or Capture C Enable bit position. */ - -#define TC0_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ -#define TC0_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ - -#define TC0_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ -#define TC0_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ - -#define TC0_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ -#define TC0_WGMODE_gp 0 /* Waveform generation mode group position. */ -#define TC0_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ -#define TC0_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ -#define TC0_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ -#define TC0_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ -#define TC0_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ -#define TC0_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ - - -/* TC0.CTRLC bit masks and bit positions */ -#define TC0_CMPD_bm 0x08 /* Compare D Output Value bit mask. */ -#define TC0_CMPD_bp 3 /* Compare D Output Value bit position. */ - -#define TC0_CMPC_bm 0x04 /* Compare C Output Value bit mask. */ -#define TC0_CMPC_bp 2 /* Compare C Output Value bit position. */ - -#define TC0_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ -#define TC0_CMPB_bp 1 /* Compare B Output Value bit position. */ - -#define TC0_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ -#define TC0_CMPA_bp 0 /* Compare A Output Value bit position. */ - - -/* TC0.CTRLD bit masks and bit positions */ -#define TC0_EVACT_gm 0xE0 /* Event Action group mask. */ -#define TC0_EVACT_gp 5 /* Event Action group position. */ -#define TC0_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ -#define TC0_EVACT0_bp 5 /* Event Action bit 0 position. */ -#define TC0_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ -#define TC0_EVACT1_bp 6 /* Event Action bit 1 position. */ -#define TC0_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ -#define TC0_EVACT2_bp 7 /* Event Action bit 2 position. */ - -#define TC0_EVDLY_bm 0x10 /* Event Delay bit mask. */ -#define TC0_EVDLY_bp 4 /* Event Delay bit position. */ - -#define TC0_EVSEL_gm 0x0F /* Event Source Select group mask. */ -#define TC0_EVSEL_gp 0 /* Event Source Select group position. */ -#define TC0_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ -#define TC0_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ -#define TC0_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ -#define TC0_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ -#define TC0_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ -#define TC0_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ -#define TC0_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ -#define TC0_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ - - -/* TC0.CTRLE bit masks and bit positions */ -#define TC0_DTHM_bm 0x02 /* Dead Time Hold Mode bit mask. */ -#define TC0_DTHM_bp 1 /* Dead Time Hold Mode bit position. */ - -#define TC0_BYTEM_bm 0x01 /* Byte Mode bit mask. */ -#define TC0_BYTEM_bp 0 /* Byte Mode bit position. */ - - -/* TC0.INTCTRLA bit masks and bit positions */ -#define TC0_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ -#define TC0_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ -#define TC0_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ -#define TC0_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ -#define TC0_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ -#define TC0_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ - -#define TC0_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ -#define TC0_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ -#define TC0_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ -#define TC0_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ -#define TC0_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ -#define TC0_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ - - -/* TC0.INTCTRLB bit masks and bit positions */ -#define TC0_CCDINTLVL_gm 0xC0 /* Compare or Capture D Interrupt Level group mask. */ -#define TC0_CCDINTLVL_gp 6 /* Compare or Capture D Interrupt Level group position. */ -#define TC0_CCDINTLVL0_bm (1<<6) /* Compare or Capture D Interrupt Level bit 0 mask. */ -#define TC0_CCDINTLVL0_bp 6 /* Compare or Capture D Interrupt Level bit 0 position. */ -#define TC0_CCDINTLVL1_bm (1<<7) /* Compare or Capture D Interrupt Level bit 1 mask. */ -#define TC0_CCDINTLVL1_bp 7 /* Compare or Capture D Interrupt Level bit 1 position. */ - -#define TC0_CCCINTLVL_gm 0x30 /* Compare or Capture C Interrupt Level group mask. */ -#define TC0_CCCINTLVL_gp 4 /* Compare or Capture C Interrupt Level group position. */ -#define TC0_CCCINTLVL0_bm (1<<4) /* Compare or Capture C Interrupt Level bit 0 mask. */ -#define TC0_CCCINTLVL0_bp 4 /* Compare or Capture C Interrupt Level bit 0 position. */ -#define TC0_CCCINTLVL1_bm (1<<5) /* Compare or Capture C Interrupt Level bit 1 mask. */ -#define TC0_CCCINTLVL1_bp 5 /* Compare or Capture C Interrupt Level bit 1 position. */ - -#define TC0_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ -#define TC0_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ -#define TC0_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ -#define TC0_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ -#define TC0_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ -#define TC0_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ - -#define TC0_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ -#define TC0_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ -#define TC0_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ -#define TC0_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ -#define TC0_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ -#define TC0_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ - - -/* TC0.CTRLFCLR bit masks and bit positions */ -#define TC0_CMD_gm 0x0C /* Command group mask. */ -#define TC0_CMD_gp 2 /* Command group position. */ -#define TC0_CMD0_bm (1<<2) /* Command bit 0 mask. */ -#define TC0_CMD0_bp 2 /* Command bit 0 position. */ -#define TC0_CMD1_bm (1<<3) /* Command bit 1 mask. */ -#define TC0_CMD1_bp 3 /* Command bit 1 position. */ - -#define TC0_LUPD_bm 0x02 /* Lock Update bit mask. */ -#define TC0_LUPD_bp 1 /* Lock Update bit position. */ - -#define TC0_DIR_bm 0x01 /* Direction bit mask. */ -#define TC0_DIR_bp 0 /* Direction bit position. */ - - -/* TC0.CTRLFSET bit masks and bit positions */ -/* TC0_CMD_gm Predefined. */ -/* TC0_CMD_gp Predefined. */ -/* TC0_CMD0_bm Predefined. */ -/* TC0_CMD0_bp Predefined. */ -/* TC0_CMD1_bm Predefined. */ -/* TC0_CMD1_bp Predefined. */ - -/* TC0_LUPD_bm Predefined. */ -/* TC0_LUPD_bp Predefined. */ - -/* TC0_DIR_bm Predefined. */ -/* TC0_DIR_bp Predefined. */ - - -/* TC0.CTRLGCLR bit masks and bit positions */ -#define TC0_CCDBV_bm 0x10 /* Compare or Capture D Buffer Valid bit mask. */ -#define TC0_CCDBV_bp 4 /* Compare or Capture D Buffer Valid bit position. */ - -#define TC0_CCCBV_bm 0x08 /* Compare or Capture C Buffer Valid bit mask. */ -#define TC0_CCCBV_bp 3 /* Compare or Capture C Buffer Valid bit position. */ - -#define TC0_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ -#define TC0_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ - -#define TC0_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ -#define TC0_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ - -#define TC0_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ -#define TC0_PERBV_bp 0 /* Period Buffer Valid bit position. */ - - -/* TC0.CTRLGSET bit masks and bit positions */ -/* TC0_CCDBV_bm Predefined. */ -/* TC0_CCDBV_bp Predefined. */ - -/* TC0_CCCBV_bm Predefined. */ -/* TC0_CCCBV_bp Predefined. */ - -/* TC0_CCBBV_bm Predefined. */ -/* TC0_CCBBV_bp Predefined. */ - -/* TC0_CCABV_bm Predefined. */ -/* TC0_CCABV_bp Predefined. */ - -/* TC0_PERBV_bm Predefined. */ -/* TC0_PERBV_bp Predefined. */ - - -/* TC0.INTFLAGS bit masks and bit positions */ -#define TC0_CCDIF_bm 0x80 /* Compare or Capture D Interrupt Flag bit mask. */ -#define TC0_CCDIF_bp 7 /* Compare or Capture D Interrupt Flag bit position. */ - -#define TC0_CCCIF_bm 0x40 /* Compare or Capture C Interrupt Flag bit mask. */ -#define TC0_CCCIF_bp 6 /* Compare or Capture C Interrupt Flag bit position. */ - -#define TC0_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ -#define TC0_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ - -#define TC0_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ -#define TC0_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ - -#define TC0_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ -#define TC0_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ - -#define TC0_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ -#define TC0_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ - - -/* TC1.CTRLA bit masks and bit positions */ -#define TC1_CLKSEL_gm 0x0F /* Clock Selection group mask. */ -#define TC1_CLKSEL_gp 0 /* Clock Selection group position. */ -#define TC1_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ -#define TC1_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ -#define TC1_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ -#define TC1_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ -#define TC1_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ -#define TC1_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ -#define TC1_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ -#define TC1_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ - - -/* TC1.CTRLB bit masks and bit positions */ -#define TC1_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ -#define TC1_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ - -#define TC1_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ -#define TC1_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ - -#define TC1_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ -#define TC1_WGMODE_gp 0 /* Waveform generation mode group position. */ -#define TC1_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ -#define TC1_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ -#define TC1_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ -#define TC1_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ -#define TC1_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ -#define TC1_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ - - -/* TC1.CTRLC bit masks and bit positions */ -#define TC1_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ -#define TC1_CMPB_bp 1 /* Compare B Output Value bit position. */ - -#define TC1_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ -#define TC1_CMPA_bp 0 /* Compare A Output Value bit position. */ - - -/* TC1.CTRLD bit masks and bit positions */ -#define TC1_EVACT_gm 0xE0 /* Event Action group mask. */ -#define TC1_EVACT_gp 5 /* Event Action group position. */ -#define TC1_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ -#define TC1_EVACT0_bp 5 /* Event Action bit 0 position. */ -#define TC1_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ -#define TC1_EVACT1_bp 6 /* Event Action bit 1 position. */ -#define TC1_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ -#define TC1_EVACT2_bp 7 /* Event Action bit 2 position. */ - -#define TC1_EVDLY_bm 0x10 /* Event Delay bit mask. */ -#define TC1_EVDLY_bp 4 /* Event Delay bit position. */ - -#define TC1_EVSEL_gm 0x0F /* Event Source Select group mask. */ -#define TC1_EVSEL_gp 0 /* Event Source Select group position. */ -#define TC1_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ -#define TC1_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ -#define TC1_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ -#define TC1_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ -#define TC1_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ -#define TC1_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ -#define TC1_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ -#define TC1_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ - - -/* TC1.CTRLE bit masks and bit positions */ -#define TC1_DTHM_bm 0x02 /* Dead Time Hold Mode bit mask. */ -#define TC1_DTHM_bp 1 /* Dead Time Hold Mode bit position. */ - -#define TC1_BYTEM_bm 0x01 /* Byte Mode bit mask. */ -#define TC1_BYTEM_bp 0 /* Byte Mode bit position. */ - - -/* TC1.INTCTRLA bit masks and bit positions */ -#define TC1_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ -#define TC1_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ -#define TC1_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ -#define TC1_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ -#define TC1_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ -#define TC1_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ - -#define TC1_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ -#define TC1_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ -#define TC1_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ -#define TC1_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ -#define TC1_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ -#define TC1_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ - - -/* TC1.INTCTRLB bit masks and bit positions */ -#define TC1_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ -#define TC1_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ -#define TC1_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ -#define TC1_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ -#define TC1_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ -#define TC1_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ - -#define TC1_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ -#define TC1_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ -#define TC1_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ -#define TC1_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ -#define TC1_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ -#define TC1_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ - - -/* TC1.CTRLFCLR bit masks and bit positions */ -#define TC1_CMD_gm 0x0C /* Command group mask. */ -#define TC1_CMD_gp 2 /* Command group position. */ -#define TC1_CMD0_bm (1<<2) /* Command bit 0 mask. */ -#define TC1_CMD0_bp 2 /* Command bit 0 position. */ -#define TC1_CMD1_bm (1<<3) /* Command bit 1 mask. */ -#define TC1_CMD1_bp 3 /* Command bit 1 position. */ - -#define TC1_LUPD_bm 0x02 /* Lock Update bit mask. */ -#define TC1_LUPD_bp 1 /* Lock Update bit position. */ - -#define TC1_DIR_bm 0x01 /* Direction bit mask. */ -#define TC1_DIR_bp 0 /* Direction bit position. */ - - -/* TC1.CTRLFSET bit masks and bit positions */ -/* TC1_CMD_gm Predefined. */ -/* TC1_CMD_gp Predefined. */ -/* TC1_CMD0_bm Predefined. */ -/* TC1_CMD0_bp Predefined. */ -/* TC1_CMD1_bm Predefined. */ -/* TC1_CMD1_bp Predefined. */ - -/* TC1_LUPD_bm Predefined. */ -/* TC1_LUPD_bp Predefined. */ - -/* TC1_DIR_bm Predefined. */ -/* TC1_DIR_bp Predefined. */ - - -/* TC1.CTRLGCLR bit masks and bit positions */ -#define TC1_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ -#define TC1_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ - -#define TC1_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ -#define TC1_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ - -#define TC1_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ -#define TC1_PERBV_bp 0 /* Period Buffer Valid bit position. */ - - -/* TC1.CTRLGSET bit masks and bit positions */ -/* TC1_CCBBV_bm Predefined. */ -/* TC1_CCBBV_bp Predefined. */ - -/* TC1_CCABV_bm Predefined. */ -/* TC1_CCABV_bp Predefined. */ - -/* TC1_PERBV_bm Predefined. */ -/* TC1_PERBV_bp Predefined. */ - - -/* TC1.INTFLAGS bit masks and bit positions */ -#define TC1_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ -#define TC1_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ - -#define TC1_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ -#define TC1_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ - -#define TC1_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ -#define TC1_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ - -#define TC1_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ -#define TC1_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ - - -/* AWEX.CTRL bit masks and bit positions */ -#define AWEX_PGM_bm 0x20 /* Pattern Generation Mode bit mask. */ -#define AWEX_PGM_bp 5 /* Pattern Generation Mode bit position. */ - -#define AWEX_CWCM_bm 0x10 /* Common Waveform Channel Mode bit mask. */ -#define AWEX_CWCM_bp 4 /* Common Waveform Channel Mode bit position. */ - -#define AWEX_DTICCDEN_bm 0x08 /* Dead Time Insertion Compare Channel D Enable bit mask. */ -#define AWEX_DTICCDEN_bp 3 /* Dead Time Insertion Compare Channel D Enable bit position. */ - -#define AWEX_DTICCCEN_bm 0x04 /* Dead Time Insertion Compare Channel C Enable bit mask. */ -#define AWEX_DTICCCEN_bp 2 /* Dead Time Insertion Compare Channel C Enable bit position. */ - -#define AWEX_DTICCBEN_bm 0x02 /* Dead Time Insertion Compare Channel B Enable bit mask. */ -#define AWEX_DTICCBEN_bp 1 /* Dead Time Insertion Compare Channel B Enable bit position. */ - -#define AWEX_DTICCAEN_bm 0x01 /* Dead Time Insertion Compare Channel A Enable bit mask. */ -#define AWEX_DTICCAEN_bp 0 /* Dead Time Insertion Compare Channel A Enable bit position. */ - - -/* AWEX.FDCTRL bit masks and bit positions */ -#define AWEX_FDDBD_bm 0x10 /* Fault Detect on Disable Break Disable bit mask. */ -#define AWEX_FDDBD_bp 4 /* Fault Detect on Disable Break Disable bit position. */ - -#define AWEX_FDMODE_bm 0x04 /* Fault Detect Mode bit mask. */ -#define AWEX_FDMODE_bp 2 /* Fault Detect Mode bit position. */ - -#define AWEX_FDACT_gm 0x03 /* Fault Detect Action group mask. */ -#define AWEX_FDACT_gp 0 /* Fault Detect Action group position. */ -#define AWEX_FDACT0_bm (1<<0) /* Fault Detect Action bit 0 mask. */ -#define AWEX_FDACT0_bp 0 /* Fault Detect Action bit 0 position. */ -#define AWEX_FDACT1_bm (1<<1) /* Fault Detect Action bit 1 mask. */ -#define AWEX_FDACT1_bp 1 /* Fault Detect Action bit 1 position. */ - - -/* AWEX.STATUS bit masks and bit positions */ -#define AWEX_FDF_bm 0x04 /* Fault Detect Flag bit mask. */ -#define AWEX_FDF_bp 2 /* Fault Detect Flag bit position. */ - -#define AWEX_DTHSBUFV_bm 0x02 /* Dead Time High Side Buffer Valid bit mask. */ -#define AWEX_DTHSBUFV_bp 1 /* Dead Time High Side Buffer Valid bit position. */ - -#define AWEX_DTLSBUFV_bm 0x01 /* Dead Time Low Side Buffer Valid bit mask. */ -#define AWEX_DTLSBUFV_bp 0 /* Dead Time Low Side Buffer Valid bit position. */ - - -/* HIRES.CTRL bit masks and bit positions */ -#define HIRES_HREN_gm 0x03 /* High Resolution Enable group mask. */ -#define HIRES_HREN_gp 0 /* High Resolution Enable group position. */ -#define HIRES_HREN0_bm (1<<0) /* High Resolution Enable bit 0 mask. */ -#define HIRES_HREN0_bp 0 /* High Resolution Enable bit 0 position. */ -#define HIRES_HREN1_bm (1<<1) /* High Resolution Enable bit 1 mask. */ -#define HIRES_HREN1_bp 1 /* High Resolution Enable bit 1 position. */ - - -/* USART - Universal Asynchronous Receiver-Transmitter */ -/* USART.STATUS bit masks and bit positions */ -#define USART_RXCIF_bm 0x80 /* Receive Interrupt Flag bit mask. */ -#define USART_RXCIF_bp 7 /* Receive Interrupt Flag bit position. */ - -#define USART_TXCIF_bm 0x40 /* Transmit Interrupt Flag bit mask. */ -#define USART_TXCIF_bp 6 /* Transmit Interrupt Flag bit position. */ - -#define USART_DREIF_bm 0x20 /* Data Register Empty Flag bit mask. */ -#define USART_DREIF_bp 5 /* Data Register Empty Flag bit position. */ - -#define USART_FERR_bm 0x10 /* Frame Error bit mask. */ -#define USART_FERR_bp 4 /* Frame Error bit position. */ - -#define USART_BUFOVF_bm 0x08 /* Buffer Overflow bit mask. */ -#define USART_BUFOVF_bp 3 /* Buffer Overflow bit position. */ - -#define USART_PERR_bm 0x04 /* Parity Error bit mask. */ -#define USART_PERR_bp 2 /* Parity Error bit position. */ - -#define USART_RXB8_bm 0x01 /* Receive Bit 8 bit mask. */ -#define USART_RXB8_bp 0 /* Receive Bit 8 bit position. */ - - -/* USART.CTRLA bit masks and bit positions */ -#define USART_RXCINTLVL_gm 0x30 /* Receive Interrupt Level group mask. */ -#define USART_RXCINTLVL_gp 4 /* Receive Interrupt Level group position. */ -#define USART_RXCINTLVL0_bm (1<<4) /* Receive Interrupt Level bit 0 mask. */ -#define USART_RXCINTLVL0_bp 4 /* Receive Interrupt Level bit 0 position. */ -#define USART_RXCINTLVL1_bm (1<<5) /* Receive Interrupt Level bit 1 mask. */ -#define USART_RXCINTLVL1_bp 5 /* Receive Interrupt Level bit 1 position. */ - -#define USART_TXCINTLVL_gm 0x0C /* Transmit Interrupt Level group mask. */ -#define USART_TXCINTLVL_gp 2 /* Transmit Interrupt Level group position. */ -#define USART_TXCINTLVL0_bm (1<<2) /* Transmit Interrupt Level bit 0 mask. */ -#define USART_TXCINTLVL0_bp 2 /* Transmit Interrupt Level bit 0 position. */ -#define USART_TXCINTLVL1_bm (1<<3) /* Transmit Interrupt Level bit 1 mask. */ -#define USART_TXCINTLVL1_bp 3 /* Transmit Interrupt Level bit 1 position. */ - -#define USART_DREINTLVL_gm 0x03 /* Data Register Empty Interrupt Level group mask. */ -#define USART_DREINTLVL_gp 0 /* Data Register Empty Interrupt Level group position. */ -#define USART_DREINTLVL0_bm (1<<0) /* Data Register Empty Interrupt Level bit 0 mask. */ -#define USART_DREINTLVL0_bp 0 /* Data Register Empty Interrupt Level bit 0 position. */ -#define USART_DREINTLVL1_bm (1<<1) /* Data Register Empty Interrupt Level bit 1 mask. */ -#define USART_DREINTLVL1_bp 1 /* Data Register Empty Interrupt Level bit 1 position. */ - - -/* USART.CTRLB bit masks and bit positions */ -#define USART_RXEN_bm 0x10 /* Receiver Enable bit mask. */ -#define USART_RXEN_bp 4 /* Receiver Enable bit position. */ - -#define USART_TXEN_bm 0x08 /* Transmitter Enable bit mask. */ -#define USART_TXEN_bp 3 /* Transmitter Enable bit position. */ - -#define USART_CLK2X_bm 0x04 /* Double transmission speed bit mask. */ -#define USART_CLK2X_bp 2 /* Double transmission speed bit position. */ - -#define USART_MPCM_bm 0x02 /* Multi-processor Communication Mode bit mask. */ -#define USART_MPCM_bp 1 /* Multi-processor Communication Mode bit position. */ - -#define USART_TXB8_bm 0x01 /* Transmit bit 8 bit mask. */ -#define USART_TXB8_bp 0 /* Transmit bit 8 bit position. */ - - -/* USART.CTRLC bit masks and bit positions */ -#define USART_CMODE_gm 0xC0 /* Communication Mode group mask. */ -#define USART_CMODE_gp 6 /* Communication Mode group position. */ -#define USART_CMODE0_bm (1<<6) /* Communication Mode bit 0 mask. */ -#define USART_CMODE0_bp 6 /* Communication Mode bit 0 position. */ -#define USART_CMODE1_bm (1<<7) /* Communication Mode bit 1 mask. */ -#define USART_CMODE1_bp 7 /* Communication Mode bit 1 position. */ - -#define USART_PMODE_gm 0x30 /* Parity Mode group mask. */ -#define USART_PMODE_gp 4 /* Parity Mode group position. */ -#define USART_PMODE0_bm (1<<4) /* Parity Mode bit 0 mask. */ -#define USART_PMODE0_bp 4 /* Parity Mode bit 0 position. */ -#define USART_PMODE1_bm (1<<5) /* Parity Mode bit 1 mask. */ -#define USART_PMODE1_bp 5 /* Parity Mode bit 1 position. */ - -#define USART_SBMODE_bm 0x08 /* Stop Bit Mode bit mask. */ -#define USART_SBMODE_bp 3 /* Stop Bit Mode bit position. */ - -#define USART_CHSIZE_gm 0x07 /* Character Size group mask. */ -#define USART_CHSIZE_gp 0 /* Character Size group position. */ -#define USART_CHSIZE0_bm (1<<0) /* Character Size bit 0 mask. */ -#define USART_CHSIZE0_bp 0 /* Character Size bit 0 position. */ -#define USART_CHSIZE1_bm (1<<1) /* Character Size bit 1 mask. */ -#define USART_CHSIZE1_bp 1 /* Character Size bit 1 position. */ -#define USART_CHSIZE2_bm (1<<2) /* Character Size bit 2 mask. */ -#define USART_CHSIZE2_bp 2 /* Character Size bit 2 position. */ - - -/* USART.BAUDCTRLA bit masks and bit positions */ -#define USART_BSEL_gm 0xFF /* Baud Rate Selection Bits [7:0] group mask. */ -#define USART_BSEL_gp 0 /* Baud Rate Selection Bits [7:0] group position. */ -#define USART_BSEL0_bm (1<<0) /* Baud Rate Selection Bits [7:0] bit 0 mask. */ -#define USART_BSEL0_bp 0 /* Baud Rate Selection Bits [7:0] bit 0 position. */ -#define USART_BSEL1_bm (1<<1) /* Baud Rate Selection Bits [7:0] bit 1 mask. */ -#define USART_BSEL1_bp 1 /* Baud Rate Selection Bits [7:0] bit 1 position. */ -#define USART_BSEL2_bm (1<<2) /* Baud Rate Selection Bits [7:0] bit 2 mask. */ -#define USART_BSEL2_bp 2 /* Baud Rate Selection Bits [7:0] bit 2 position. */ -#define USART_BSEL3_bm (1<<3) /* Baud Rate Selection Bits [7:0] bit 3 mask. */ -#define USART_BSEL3_bp 3 /* Baud Rate Selection Bits [7:0] bit 3 position. */ -#define USART_BSEL4_bm (1<<4) /* Baud Rate Selection Bits [7:0] bit 4 mask. */ -#define USART_BSEL4_bp 4 /* Baud Rate Selection Bits [7:0] bit 4 position. */ -#define USART_BSEL5_bm (1<<5) /* Baud Rate Selection Bits [7:0] bit 5 mask. */ -#define USART_BSEL5_bp 5 /* Baud Rate Selection Bits [7:0] bit 5 position. */ -#define USART_BSEL6_bm (1<<6) /* Baud Rate Selection Bits [7:0] bit 6 mask. */ -#define USART_BSEL6_bp 6 /* Baud Rate Selection Bits [7:0] bit 6 position. */ -#define USART_BSEL7_bm (1<<7) /* Baud Rate Selection Bits [7:0] bit 7 mask. */ -#define USART_BSEL7_bp 7 /* Baud Rate Selection Bits [7:0] bit 7 position. */ - - -/* USART.BAUDCTRLB bit masks and bit positions */ -#define USART_BSCALE_gm 0xF0 /* Baud Rate Scale group mask. */ -#define USART_BSCALE_gp 4 /* Baud Rate Scale group position. */ -#define USART_BSCALE0_bm (1<<4) /* Baud Rate Scale bit 0 mask. */ -#define USART_BSCALE0_bp 4 /* Baud Rate Scale bit 0 position. */ -#define USART_BSCALE1_bm (1<<5) /* Baud Rate Scale bit 1 mask. */ -#define USART_BSCALE1_bp 5 /* Baud Rate Scale bit 1 position. */ -#define USART_BSCALE2_bm (1<<6) /* Baud Rate Scale bit 2 mask. */ -#define USART_BSCALE2_bp 6 /* Baud Rate Scale bit 2 position. */ -#define USART_BSCALE3_bm (1<<7) /* Baud Rate Scale bit 3 mask. */ -#define USART_BSCALE3_bp 7 /* Baud Rate Scale bit 3 position. */ - -/* USART_BSEL_gm Predefined. */ -/* USART_BSEL_gp Predefined. */ -/* USART_BSEL0_bm Predefined. */ -/* USART_BSEL0_bp Predefined. */ -/* USART_BSEL1_bm Predefined. */ -/* USART_BSEL1_bp Predefined. */ -/* USART_BSEL2_bm Predefined. */ -/* USART_BSEL2_bp Predefined. */ -/* USART_BSEL3_bm Predefined. */ -/* USART_BSEL3_bp Predefined. */ - - -/* SPI - Serial Peripheral Interface */ -/* SPI.CTRL bit masks and bit positions */ -#define SPI_CLK2X_bm 0x80 /* Enable Double Speed bit mask. */ -#define SPI_CLK2X_bp 7 /* Enable Double Speed bit position. */ - -#define SPI_ENABLE_bm 0x40 /* Enable Module bit mask. */ -#define SPI_ENABLE_bp 6 /* Enable Module bit position. */ - -#define SPI_DORD_bm 0x20 /* Data Order Setting bit mask. */ -#define SPI_DORD_bp 5 /* Data Order Setting bit position. */ - -#define SPI_MASTER_bm 0x10 /* Master Operation Enable bit mask. */ -#define SPI_MASTER_bp 4 /* Master Operation Enable bit position. */ - -#define SPI_MODE_gm 0x0C /* SPI Mode group mask. */ -#define SPI_MODE_gp 2 /* SPI Mode group position. */ -#define SPI_MODE0_bm (1<<2) /* SPI Mode bit 0 mask. */ -#define SPI_MODE0_bp 2 /* SPI Mode bit 0 position. */ -#define SPI_MODE1_bm (1<<3) /* SPI Mode bit 1 mask. */ -#define SPI_MODE1_bp 3 /* SPI Mode bit 1 position. */ - -#define SPI_PRESCALER_gm 0x03 /* Prescaler group mask. */ -#define SPI_PRESCALER_gp 0 /* Prescaler group position. */ -#define SPI_PRESCALER0_bm (1<<0) /* Prescaler bit 0 mask. */ -#define SPI_PRESCALER0_bp 0 /* Prescaler bit 0 position. */ -#define SPI_PRESCALER1_bm (1<<1) /* Prescaler bit 1 mask. */ -#define SPI_PRESCALER1_bp 1 /* Prescaler bit 1 position. */ - - -/* SPI.INTCTRL bit masks and bit positions */ -#define SPI_INTLVL_gm 0x03 /* Interrupt level group mask. */ -#define SPI_INTLVL_gp 0 /* Interrupt level group position. */ -#define SPI_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */ -#define SPI_INTLVL0_bp 0 /* Interrupt level bit 0 position. */ -#define SPI_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */ -#define SPI_INTLVL1_bp 1 /* Interrupt level bit 1 position. */ - - -/* SPI.STATUS bit masks and bit positions */ -#define SPI_IF_bm 0x80 /* Interrupt Flag bit mask. */ -#define SPI_IF_bp 7 /* Interrupt Flag bit position. */ - -#define SPI_WRCOL_bm 0x40 /* Write Collision bit mask. */ -#define SPI_WRCOL_bp 6 /* Write Collision bit position. */ - - -/* IRCOM - IR Communication Module */ -/* IRCOM.CTRL bit masks and bit positions */ -#define IRCOM_EVSEL_gm 0x0F /* Event Channel Select group mask. */ -#define IRCOM_EVSEL_gp 0 /* Event Channel Select group position. */ -#define IRCOM_EVSEL0_bm (1<<0) /* Event Channel Select bit 0 mask. */ -#define IRCOM_EVSEL0_bp 0 /* Event Channel Select bit 0 position. */ -#define IRCOM_EVSEL1_bm (1<<1) /* Event Channel Select bit 1 mask. */ -#define IRCOM_EVSEL1_bp 1 /* Event Channel Select bit 1 position. */ -#define IRCOM_EVSEL2_bm (1<<2) /* Event Channel Select bit 2 mask. */ -#define IRCOM_EVSEL2_bp 2 /* Event Channel Select bit 2 position. */ -#define IRCOM_EVSEL3_bm (1<<3) /* Event Channel Select bit 3 mask. */ -#define IRCOM_EVSEL3_bp 3 /* Event Channel Select bit 3 position. */ - - -/* AES - AES Module */ -/* AES.CTRL bit masks and bit positions */ -#define AES_START_bm 0x80 /* Start/Run bit mask. */ -#define AES_START_bp 7 /* Start/Run bit position. */ - -#define AES_AUTO_bm 0x40 /* Auto Start Trigger bit mask. */ -#define AES_AUTO_bp 6 /* Auto Start Trigger bit position. */ - -#define AES_RESET_bm 0x20 /* AES Software Reset bit mask. */ -#define AES_RESET_bp 5 /* AES Software Reset bit position. */ - -#define AES_DECRYPT_bm 0x10 /* Decryption / Direction bit mask. */ -#define AES_DECRYPT_bp 4 /* Decryption / Direction bit position. */ - -#define AES_XOR_bm 0x04 /* State XOR Load Enable bit mask. */ -#define AES_XOR_bp 2 /* State XOR Load Enable bit position. */ - - -/* AES.STATUS bit masks and bit positions */ -#define AES_ERROR_bm 0x80 /* AES Error bit mask. */ -#define AES_ERROR_bp 7 /* AES Error bit position. */ - -#define AES_SRIF_bm 0x01 /* State Ready Interrupt Flag bit mask. */ -#define AES_SRIF_bp 0 /* State Ready Interrupt Flag bit position. */ - - -/* AES.INTCTRL bit masks and bit positions */ -#define AES_INTLVL_gm 0x03 /* Interrupt level group mask. */ -#define AES_INTLVL_gp 0 /* Interrupt level group position. */ -#define AES_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */ -#define AES_INTLVL0_bp 0 /* Interrupt level bit 0 position. */ -#define AES_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */ -#define AES_INTLVL1_bp 1 /* Interrupt level bit 1 position. */ - - -/* VBAT - VBAT Battery Backup Module */ -/* VBAT.CTRL bit masks and bit positions */ -#define VBAT_XOSCSEL_bm 0x10 /* 32-kHz Crystal Oscillator Output Selection bit mask. */ -#define VBAT_XOSCSEL_bp 4 /* 32-kHz Crystal Oscillator Output Selection bit position. */ - -#define VBAT_XOSCEN_bm 0x08 /* Crystal Oscillator Enable bit mask. */ -#define VBAT_XOSCEN_bp 3 /* Crystal Oscillator Enable bit position. */ - -#define VBAT_XOSCFDEN_bm 0x04 /* Crystal Oscillator Failure Detection Monitor Enable bit mask. */ -#define VBAT_XOSCFDEN_bp 2 /* Crystal Oscillator Failure Detection Monitor Enable bit position. */ - -#define VBAT_ACCEN_bm 0x02 /* Battery Backup Access Enable bit mask. */ -#define VBAT_ACCEN_bp 1 /* Battery Backup Access Enable bit position. */ - -#define VBAT_RESET_bm 0x01 /* Battery Backup Reset bit mask. */ -#define VBAT_RESET_bp 0 /* Battery Backup Reset bit position. */ - - -/* VBAT.STATUS bit masks and bit positions */ -#define VBAT_BBPWR_bm 0x80 /* Battery backup Power bit mask. */ -#define VBAT_BBPWR_bp 7 /* Battery backup Power bit position. */ - -#define VBAT_XOSCRDY_bm 0x08 /* Crystal Oscillator Ready bit mask. */ -#define VBAT_XOSCRDY_bp 3 /* Crystal Oscillator Ready bit position. */ - -#define VBAT_XOSCFAIL_bm 0x04 /* Crystal Oscillator Failure bit mask. */ -#define VBAT_XOSCFAIL_bp 2 /* Crystal Oscillator Failure bit position. */ - -#define VBAT_BBBORF_bm 0x02 /* Battery Backup Brown-Out Reset Flag bit mask. */ -#define VBAT_BBBORF_bp 1 /* Battery Backup Brown-Out Reset Flag bit position. */ - -#define VBAT_BBPORF_bm 0x01 /* Battery Backup Power-On Reset Flag bit mask. */ -#define VBAT_BBPORF_bp 0 /* Battery Backup Power-On Reset Flag bit position. */ - - - -// Generic Port Pins - -#define PIN0_bm 0x01 -#define PIN0_bp 0 -#define PIN1_bm 0x02 -#define PIN1_bp 1 -#define PIN2_bm 0x04 -#define PIN2_bp 2 -#define PIN3_bm 0x08 -#define PIN3_bp 3 -#define PIN4_bm 0x10 -#define PIN4_bp 4 -#define PIN5_bm 0x20 -#define PIN5_bp 5 -#define PIN6_bm 0x40 -#define PIN6_bp 6 -#define PIN7_bm 0x80 -#define PIN7_bp 7 - - -/* ========== Interrupt Vector Definitions ========== */ -/* Vector 0 is the reset vector */ - -/* OSC interrupt vectors */ -#define OSC_XOSCF_vect_num 1 -#define OSC_XOSCF_vect _VECTOR(1) /* External Oscillator Failure Interrupt (NMI) */ - -/* PORTC interrupt vectors */ -#define PORTC_INT0_vect_num 2 -#define PORTC_INT0_vect _VECTOR(2) /* External Interrupt 0 */ -#define PORTC_INT1_vect_num 3 -#define PORTC_INT1_vect _VECTOR(3) /* External Interrupt 1 */ - -/* PORTR interrupt vectors */ -#define PORTR_INT0_vect_num 4 -#define PORTR_INT0_vect _VECTOR(4) /* External Interrupt 0 */ -#define PORTR_INT1_vect_num 5 -#define PORTR_INT1_vect _VECTOR(5) /* External Interrupt 1 */ - -/* DMA interrupt vectors */ -#define DMA_CH0_vect_num 6 -#define DMA_CH0_vect _VECTOR(6) /* Channel 0 Interrupt */ -#define DMA_CH1_vect_num 7 -#define DMA_CH1_vect _VECTOR(7) /* Channel 1 Interrupt */ -#define DMA_CH2_vect_num 8 -#define DMA_CH2_vect _VECTOR(8) /* Channel 2 Interrupt */ -#define DMA_CH3_vect_num 9 -#define DMA_CH3_vect _VECTOR(9) /* Channel 3 Interrupt */ - -/* RTC32 interrupt vectors */ -#define RTC32_OVF_vect_num 10 -#define RTC32_OVF_vect _VECTOR(10) /* Overflow Interrupt */ -#define RTC32_COMP_vect_num 11 -#define RTC32_COMP_vect _VECTOR(11) /* Compare Interrupt */ - -/* TWIC interrupt vectors */ -#define TWIC_TWIS_vect_num 12 -#define TWIC_TWIS_vect _VECTOR(12) /* TWI Slave Interrupt */ -#define TWIC_TWIM_vect_num 13 -#define TWIC_TWIM_vect _VECTOR(13) /* TWI Master Interrupt */ - -/* TCC0 interrupt vectors */ -#define TCC0_OVF_vect_num 14 -#define TCC0_OVF_vect _VECTOR(14) /* Overflow Interrupt */ -#define TCC0_ERR_vect_num 15 -#define TCC0_ERR_vect _VECTOR(15) /* Error Interrupt */ -#define TCC0_CCA_vect_num 16 -#define TCC0_CCA_vect _VECTOR(16) /* Compare or Capture A Interrupt */ -#define TCC0_CCB_vect_num 17 -#define TCC0_CCB_vect _VECTOR(17) /* Compare or Capture B Interrupt */ -#define TCC0_CCC_vect_num 18 -#define TCC0_CCC_vect _VECTOR(18) /* Compare or Capture C Interrupt */ -#define TCC0_CCD_vect_num 19 -#define TCC0_CCD_vect _VECTOR(19) /* Compare or Capture D Interrupt */ - -/* TCC1 interrupt vectors */ -#define TCC1_OVF_vect_num 20 -#define TCC1_OVF_vect _VECTOR(20) /* Overflow Interrupt */ -#define TCC1_ERR_vect_num 21 -#define TCC1_ERR_vect _VECTOR(21) /* Error Interrupt */ -#define TCC1_CCA_vect_num 22 -#define TCC1_CCA_vect _VECTOR(22) /* Compare or Capture A Interrupt */ -#define TCC1_CCB_vect_num 23 -#define TCC1_CCB_vect _VECTOR(23) /* Compare or Capture B Interrupt */ - -/* SPIC interrupt vectors */ -#define SPIC_INT_vect_num 24 -#define SPIC_INT_vect _VECTOR(24) /* SPI Interrupt */ - -/* USARTC0 interrupt vectors */ -#define USARTC0_RXC_vect_num 25 -#define USARTC0_RXC_vect _VECTOR(25) /* Reception Complete Interrupt */ -#define USARTC0_DRE_vect_num 26 -#define USARTC0_DRE_vect _VECTOR(26) /* Data Register Empty Interrupt */ -#define USARTC0_TXC_vect_num 27 -#define USARTC0_TXC_vect _VECTOR(27) /* Transmission Complete Interrupt */ - -/* USARTC1 interrupt vectors */ -#define USARTC1_RXC_vect_num 28 -#define USARTC1_RXC_vect _VECTOR(28) /* Reception Complete Interrupt */ -#define USARTC1_DRE_vect_num 29 -#define USARTC1_DRE_vect _VECTOR(29) /* Data Register Empty Interrupt */ -#define USARTC1_TXC_vect_num 30 -#define USARTC1_TXC_vect _VECTOR(30) /* Transmission Complete Interrupt */ - -/* AES interrupt vectors */ -#define AES_INT_vect_num 31 -#define AES_INT_vect _VECTOR(31) /* AES Interrupt */ - -/* NVM interrupt vectors */ -#define NVM_EE_vect_num 32 -#define NVM_EE_vect _VECTOR(32) /* EE Interrupt */ -#define NVM_SPM_vect_num 33 -#define NVM_SPM_vect _VECTOR(33) /* SPM Interrupt */ - -/* PORTB interrupt vectors */ -#define PORTB_INT0_vect_num 34 -#define PORTB_INT0_vect _VECTOR(34) /* External Interrupt 0 */ -#define PORTB_INT1_vect_num 35 -#define PORTB_INT1_vect _VECTOR(35) /* External Interrupt 1 */ - -/* ACB interrupt vectors */ -#define ACB_AC0_vect_num 36 -#define ACB_AC0_vect _VECTOR(36) /* AC0 Interrupt */ -#define ACB_AC1_vect_num 37 -#define ACB_AC1_vect _VECTOR(37) /* AC1 Interrupt */ -#define ACB_ACW_vect_num 38 -#define ACB_ACW_vect _VECTOR(38) /* ACW Window Mode Interrupt */ - -/* ADCB interrupt vectors */ -#define ADCB_CH0_vect_num 39 -#define ADCB_CH0_vect _VECTOR(39) /* Interrupt 0 */ -#define ADCB_CH1_vect_num 40 -#define ADCB_CH1_vect _VECTOR(40) /* Interrupt 1 */ -#define ADCB_CH2_vect_num 41 -#define ADCB_CH2_vect _VECTOR(41) /* Interrupt 2 */ -#define ADCB_CH3_vect_num 42 -#define ADCB_CH3_vect _VECTOR(42) /* Interrupt 3 */ - -/* PORTE interrupt vectors */ -#define PORTE_INT0_vect_num 43 -#define PORTE_INT0_vect _VECTOR(43) /* External Interrupt 0 */ -#define PORTE_INT1_vect_num 44 -#define PORTE_INT1_vect _VECTOR(44) /* External Interrupt 1 */ - -/* TWIE interrupt vectors */ -#define TWIE_TWIS_vect_num 45 -#define TWIE_TWIS_vect _VECTOR(45) /* TWI Slave Interrupt */ -#define TWIE_TWIM_vect_num 46 -#define TWIE_TWIM_vect _VECTOR(46) /* TWI Master Interrupt */ - -/* TCE0 interrupt vectors */ -#define TCE0_OVF_vect_num 47 -#define TCE0_OVF_vect _VECTOR(47) /* Overflow Interrupt */ -#define TCE0_ERR_vect_num 48 -#define TCE0_ERR_vect _VECTOR(48) /* Error Interrupt */ -#define TCE0_CCA_vect_num 49 -#define TCE0_CCA_vect _VECTOR(49) /* Compare or Capture A Interrupt */ -#define TCE0_CCB_vect_num 50 -#define TCE0_CCB_vect _VECTOR(50) /* Compare or Capture B Interrupt */ -#define TCE0_CCC_vect_num 51 -#define TCE0_CCC_vect _VECTOR(51) /* Compare or Capture C Interrupt */ -#define TCE0_CCD_vect_num 52 -#define TCE0_CCD_vect _VECTOR(52) /* Compare or Capture D Interrupt */ - -/* TCE1 interrupt vectors */ -#define TCE1_OVF_vect_num 53 -#define TCE1_OVF_vect _VECTOR(53) /* Overflow Interrupt */ -#define TCE1_ERR_vect_num 54 -#define TCE1_ERR_vect _VECTOR(54) /* Error Interrupt */ -#define TCE1_CCA_vect_num 55 -#define TCE1_CCA_vect _VECTOR(55) /* Compare or Capture A Interrupt */ -#define TCE1_CCB_vect_num 56 -#define TCE1_CCB_vect _VECTOR(56) /* Compare or Capture B Interrupt */ - -/* USARTE0 interrupt vectors */ -#define USARTE0_RXC_vect_num 58 -#define USARTE0_RXC_vect _VECTOR(58) /* Reception Complete Interrupt */ -#define USARTE0_DRE_vect_num 59 -#define USARTE0_DRE_vect _VECTOR(59) /* Data Register Empty Interrupt */ -#define USARTE0_TXC_vect_num 60 -#define USARTE0_TXC_vect _VECTOR(60) /* Transmission Complete Interrupt */ - -/* PORTD interrupt vectors */ -#define PORTD_INT0_vect_num 64 -#define PORTD_INT0_vect _VECTOR(64) /* External Interrupt 0 */ -#define PORTD_INT1_vect_num 65 -#define PORTD_INT1_vect _VECTOR(65) /* External Interrupt 1 */ - -/* PORTA interrupt vectors */ -#define PORTA_INT0_vect_num 66 -#define PORTA_INT0_vect _VECTOR(66) /* External Interrupt 0 */ -#define PORTA_INT1_vect_num 67 -#define PORTA_INT1_vect _VECTOR(67) /* External Interrupt 1 */ - -/* ACA interrupt vectors */ -#define ACA_AC0_vect_num 68 -#define ACA_AC0_vect _VECTOR(68) /* AC0 Interrupt */ -#define ACA_AC1_vect_num 69 -#define ACA_AC1_vect _VECTOR(69) /* AC1 Interrupt */ -#define ACA_ACW_vect_num 70 -#define ACA_ACW_vect _VECTOR(70) /* ACW Window Mode Interrupt */ - -/* ADCA interrupt vectors */ -#define ADCA_CH0_vect_num 71 -#define ADCA_CH0_vect _VECTOR(71) /* Interrupt 0 */ -#define ADCA_CH1_vect_num 72 -#define ADCA_CH1_vect _VECTOR(72) /* Interrupt 1 */ -#define ADCA_CH2_vect_num 73 -#define ADCA_CH2_vect _VECTOR(73) /* Interrupt 2 */ -#define ADCA_CH3_vect_num 74 -#define ADCA_CH3_vect _VECTOR(74) /* Interrupt 3 */ - -/* TCD0 interrupt vectors */ -#define TCD0_OVF_vect_num 77 -#define TCD0_OVF_vect _VECTOR(77) /* Overflow Interrupt */ -#define TCD0_ERR_vect_num 78 -#define TCD0_ERR_vect _VECTOR(78) /* Error Interrupt */ -#define TCD0_CCA_vect_num 79 -#define TCD0_CCA_vect _VECTOR(79) /* Compare or Capture A Interrupt */ -#define TCD0_CCB_vect_num 80 -#define TCD0_CCB_vect _VECTOR(80) /* Compare or Capture B Interrupt */ -#define TCD0_CCC_vect_num 81 -#define TCD0_CCC_vect _VECTOR(81) /* Compare or Capture C Interrupt */ -#define TCD0_CCD_vect_num 82 -#define TCD0_CCD_vect _VECTOR(82) /* Compare or Capture D Interrupt */ - -/* TCD1 interrupt vectors */ -#define TCD1_OVF_vect_num 83 -#define TCD1_OVF_vect _VECTOR(83) /* Overflow Interrupt */ -#define TCD1_ERR_vect_num 84 -#define TCD1_ERR_vect _VECTOR(84) /* Error Interrupt */ -#define TCD1_CCA_vect_num 85 -#define TCD1_CCA_vect _VECTOR(85) /* Compare or Capture A Interrupt */ -#define TCD1_CCB_vect_num 86 -#define TCD1_CCB_vect _VECTOR(86) /* Compare or Capture B Interrupt */ - -/* SPID interrupt vectors */ -#define SPID_INT_vect_num 87 -#define SPID_INT_vect _VECTOR(87) /* SPI Interrupt */ - -/* USARTD0 interrupt vectors */ -#define USARTD0_RXC_vect_num 88 -#define USARTD0_RXC_vect _VECTOR(88) /* Reception Complete Interrupt */ -#define USARTD0_DRE_vect_num 89 -#define USARTD0_DRE_vect _VECTOR(89) /* Data Register Empty Interrupt */ -#define USARTD0_TXC_vect_num 90 -#define USARTD0_TXC_vect _VECTOR(90) /* Transmission Complete Interrupt */ - -/* USARTD1 interrupt vectors */ -#define USARTD1_RXC_vect_num 91 -#define USARTD1_RXC_vect _VECTOR(91) /* Reception Complete Interrupt */ -#define USARTD1_DRE_vect_num 92 -#define USARTD1_DRE_vect _VECTOR(92) /* Data Register Empty Interrupt */ -#define USARTD1_TXC_vect_num 93 -#define USARTD1_TXC_vect _VECTOR(93) /* Transmission Complete Interrupt */ - -/* PORTF interrupt vectors */ -#define PORTF_INT0_vect_num 104 -#define PORTF_INT0_vect _VECTOR(104) /* External Interrupt 0 */ -#define PORTF_INT1_vect_num 105 -#define PORTF_INT1_vect _VECTOR(105) /* External Interrupt 1 */ - -/* TCF0 interrupt vectors */ -#define TCF0_OVF_vect_num 108 -#define TCF0_OVF_vect _VECTOR(108) /* Overflow Interrupt */ -#define TCF0_ERR_vect_num 109 -#define TCF0_ERR_vect _VECTOR(109) /* Error Interrupt */ -#define TCF0_CCA_vect_num 110 -#define TCF0_CCA_vect _VECTOR(110) /* Compare or Capture A Interrupt */ -#define TCF0_CCB_vect_num 111 -#define TCF0_CCB_vect _VECTOR(111) /* Compare or Capture B Interrupt */ -#define TCF0_CCC_vect_num 112 -#define TCF0_CCC_vect _VECTOR(112) /* Compare or Capture C Interrupt */ -#define TCF0_CCD_vect_num 113 -#define TCF0_CCD_vect _VECTOR(113) /* Compare or Capture D Interrupt */ - -/* USARTF0 interrupt vectors */ -#define USARTF0_RXC_vect_num 119 -#define USARTF0_RXC_vect _VECTOR(119) /* Reception Complete Interrupt */ -#define USARTF0_DRE_vect_num 120 -#define USARTF0_DRE_vect _VECTOR(120) /* Data Register Empty Interrupt */ -#define USARTF0_TXC_vect_num 121 -#define USARTF0_TXC_vect _VECTOR(121) /* Transmission Complete Interrupt */ - - -#define _VECTOR_SIZE 4 /* Size of individual vector. */ -#define _VECTORS_SIZE (122 * _VECTOR_SIZE) - - -/* ========== Constants ========== */ - -#define PROGMEM_START (0x0000) -#define PROGMEM_SIZE (270336) -#define PROGMEM_PAGE_SIZE (512) -#define PROGMEM_END (PROGMEM_START + PROGMEM_SIZE - 1) - -#define APP_SECTION_START (0x0000) -#define APP_SECTION_SIZE (262144) -#define APP_SECTION_PAGE_SIZE (512) -#define APP_SECTION_END (APP_SECTION_START + APP_SECTION_SIZE - 1) - -#define APPTABLE_SECTION_START (0x3E000) -#define APPTABLE_SECTION_SIZE (8192) -#define APPTABLE_SECTION_PAGE_SIZE (512) -#define APPTABLE_SECTION_END (APPTABLE_SECTION_START + APPTABLE_SECTION_SIZE - 1) - -#define BOOT_SECTION_START (0x40000) -#define BOOT_SECTION_SIZE (8192) -#define BOOT_SECTION_PAGE_SIZE (512) -#define BOOT_SECTION_END (BOOT_SECTION_START + BOOT_SECTION_SIZE - 1) - -#define DATAMEM_START (0x0000) -#define DATAMEM_SIZE (24576) -#define DATAMEM_PAGE_SIZE (0) -#define DATAMEM_END (DATAMEM_START + DATAMEM_SIZE - 1) - -#define IO_START (0x0000) -#define IO_SIZE (4096) -#define IO_PAGE_SIZE (0) -#define IO_END (IO_START + IO_SIZE - 1) - -#define MAPPED_EEPROM_START (0x1000) -#define MAPPED_EEPROM_SIZE (4096) -#define MAPPED_EEPROM_PAGE_SIZE (0) -#define MAPPED_EEPROM_END (MAPPED_EEPROM_START + MAPPED_EEPROM_SIZE - 1) - -#define INTERNAL_SRAM_START (0x2000) -#define INTERNAL_SRAM_SIZE (16384) -#define INTERNAL_SRAM_PAGE_SIZE (0) -#define INTERNAL_SRAM_END (INTERNAL_SRAM_START + INTERNAL_SRAM_SIZE - 1) - -#define EEPROM_START (0x0000) -#define EEPROM_SIZE (4096) -#define EEPROM_PAGE_SIZE (32) -#define EEPROM_END (EEPROM_START + EEPROM_SIZE - 1) - -#define FUSE_START (0x0000) -#define FUSE_SIZE (6) -#define FUSE_PAGE_SIZE (0) -#define FUSE_END (FUSE_START + FUSE_SIZE - 1) - -#define LOCKBIT_START (0x0000) -#define LOCKBIT_SIZE (1) -#define LOCKBIT_PAGE_SIZE (0) -#define LOCKBIT_END (LOCKBIT_START + LOCKBIT_SIZE - 1) - -#define SIGNATURES_START (0x0000) -#define SIGNATURES_SIZE (3) -#define SIGNATURES_PAGE_SIZE (0) -#define SIGNATURES_END (SIGNATURES_START + SIGNATURES_SIZE - 1) - -#define USER_SIGNATURES_START (0x0000) -#define USER_SIGNATURES_SIZE (512) -#define USER_SIGNATURES_PAGE_SIZE (0) -#define USER_SIGNATURES_END (USER_SIGNATURES_START + USER_SIGNATURES_SIZE - 1) - -#define PROD_SIGNATURES_START (0x0000) -#define PROD_SIGNATURES_SIZE (52) -#define PROD_SIGNATURES_PAGE_SIZE (0) -#define PROD_SIGNATURES_END (PROD_SIGNATURES_START + PROD_SIGNATURES_SIZE - 1) - -#define FLASHEND PROGMEM_END -#define SPM_PAGESIZE PROGMEM_PAGE_SIZE -#define RAMSTART INTERNAL_SRAM_START -#define RAMSIZE INTERNAL_SRAM_SIZE -#define RAMEND INTERNAL_SRAM_END -#define XRAMSTART EXTERNAL_SRAM_START -#define XRAMSIZE EXTERNAL_SRAM_SIZE -#define XRAMEND INTERNAL_SRAM_END -#define E2END EEPROM_END -#define E2PAGESIZE EEPROM_PAGE_SIZE - - -/* ========== Fuses ========== */ -#define FUSE_MEMORY_SIZE 6 - -/* Fuse Byte 0 */ -#define FUSE_JTAGUSERID0 (unsigned char)~_BV(0) /* JTAG User ID Bit 0 */ -#define FUSE_JTAGUSERID1 (unsigned char)~_BV(1) /* JTAG User ID Bit 1 */ -#define FUSE_JTAGUSERID2 (unsigned char)~_BV(2) /* JTAG User ID Bit 2 */ -#define FUSE_JTAGUSERID3 (unsigned char)~_BV(3) /* JTAG User ID Bit 3 */ -#define FUSE_JTAGUSERID4 (unsigned char)~_BV(4) /* JTAG User ID Bit 4 */ -#define FUSE_JTAGUSERID5 (unsigned char)~_BV(5) /* JTAG User ID Bit 5 */ -#define FUSE_JTAGUSERID6 (unsigned char)~_BV(6) /* JTAG User ID Bit 6 */ -#define FUSE_JTAGUSERID7 (unsigned char)~_BV(7) /* JTAG User ID Bit 7 */ -#define FUSE0_DEFAULT (0xFF) - -/* Fuse Byte 1 */ -#define FUSE_WDP0 (unsigned char)~_BV(0) /* Watchdog Timeout Period Bit 0 */ -#define FUSE_WDP1 (unsigned char)~_BV(1) /* Watchdog Timeout Period Bit 1 */ -#define FUSE_WDP2 (unsigned char)~_BV(2) /* Watchdog Timeout Period Bit 2 */ -#define FUSE_WDP3 (unsigned char)~_BV(3) /* Watchdog Timeout Period Bit 3 */ -#define FUSE_WDWP0 (unsigned char)~_BV(4) /* Watchdog Window Timeout Period Bit 0 */ -#define FUSE_WDWP1 (unsigned char)~_BV(5) /* Watchdog Window Timeout Period Bit 1 */ -#define FUSE_WDWP2 (unsigned char)~_BV(6) /* Watchdog Window Timeout Period Bit 2 */ -#define FUSE_WDWP3 (unsigned char)~_BV(7) /* Watchdog Window Timeout Period Bit 3 */ -#define FUSE1_DEFAULT (0xFF) - -/* Fuse Byte 2 */ -#define FUSE_BODPD0 (unsigned char)~_BV(0) /* BOD Operation in Power-Down Mode Bit 0 */ -#define FUSE_BODPD1 (unsigned char)~_BV(1) /* BOD Operation in Power-Down Mode Bit 1 */ -#define FUSE_BOOTRST (unsigned char)~_BV(6) /* Boot Loader Section Reset Vector */ -#define FUSE_DVSDON (unsigned char)~_BV(7) /* Spike Detector Enable */ -#define FUSE2_DEFAULT (0xFF) - -/* Fuse Byte 3 Reserved */ - -/* Fuse Byte 4 */ -#define FUSE_JTAGEN (unsigned char)~_BV(0) /* JTAG Interface Enable */ -#define FUSE_WDLOCK (unsigned char)~_BV(1) /* Watchdog Timer Lock */ -#define FUSE_SUT0 (unsigned char)~_BV(2) /* Start-up Time Bit 0 */ -#define FUSE_SUT1 (unsigned char)~_BV(3) /* Start-up Time Bit 1 */ -#define FUSE4_DEFAULT (0xFF) - -/* Fuse Byte 5 */ -#define FUSE_BODLVL0 (unsigned char)~_BV(0) /* Brown Out Detection Voltage Level Bit 0 */ -#define FUSE_BODLVL1 (unsigned char)~_BV(1) /* Brown Out Detection Voltage Level Bit 1 */ -#define FUSE_BODLVL2 (unsigned char)~_BV(2) /* Brown Out Detection Voltage Level Bit 2 */ -#define FUSE_EESAVE (unsigned char)~_BV(3) /* Preserve EEPROM Through Chip Erase */ -#define FUSE_BODACT0 (unsigned char)~_BV(4) /* BOD Operation in Active Mode Bit 0 */ -#define FUSE_BODACT1 (unsigned char)~_BV(5) /* BOD Operation in Active Mode Bit 1 */ -#define FUSE5_DEFAULT (0xFF) - - -/* ========== Lock Bits ========== */ -#define __LOCK_BITS_EXIST -#define __BOOT_LOCK_APPLICATION_TABLE_BITS_EXIST -#define __BOOT_LOCK_APPLICATION_BITS_EXIST -#define __BOOT_LOCK_BOOT_BITS_EXIST - - -/* ========== Signature ========== */ -#define SIGNATURE_0 0x1E -#define SIGNATURE_1 0x98 -#define SIGNATURE_2 0x43 - -/* ========== Power Reduction Condition Definitions ========== */ - -/* PR.PRGEN */ -#define __AVR_HAVE_PRGEN (PR_AES_bm|PR_EBI_bm|PR_RTC_bm|PR_EVSYS_bm|PR_DMA_bm) -#define __AVR_HAVE_PRGEN_AES -#define __AVR_HAVE_PRGEN_EBI -#define __AVR_HAVE_PRGEN_RTC -#define __AVR_HAVE_PRGEN_EVSYS -#define __AVR_HAVE_PRGEN_DMA - -/* PR.PRPA */ -#define __AVR_HAVE_PRPA (PR_DAC_bm|PR_ADC_bm|PR_AC_bm) -#define __AVR_HAVE_PRPA_DAC -#define __AVR_HAVE_PRPA_ADC -#define __AVR_HAVE_PRPA_AC - -/* PR.PRPB */ -#define __AVR_HAVE_PRPB (PR_DAC_bm|PR_ADC_bm|PR_AC_bm) -#define __AVR_HAVE_PRPB_DAC -#define __AVR_HAVE_PRPB_ADC -#define __AVR_HAVE_PRPB_AC - -/* PR.PRPC */ -#define __AVR_HAVE_PRPC (PR_TWI_bm|PR_USART1_bm|PR_USART0_bm|PR_SPI_bm|PR_HIRES_bm|PR_TC1_bm|PR_TC0_bm) -#define __AVR_HAVE_PRPC_TWI -#define __AVR_HAVE_PRPC_USART1 -#define __AVR_HAVE_PRPC_USART0 -#define __AVR_HAVE_PRPC_SPI -#define __AVR_HAVE_PRPC_HIRES -#define __AVR_HAVE_PRPC_TC1 -#define __AVR_HAVE_PRPC_TC0 - -/* PR.PRPD */ -#define __AVR_HAVE_PRPD (PR_TWI_bm|PR_USART1_bm|PR_USART0_bm|PR_SPI_bm|PR_HIRES_bm|PR_TC1_bm|PR_TC0_bm) -#define __AVR_HAVE_PRPD_TWI -#define __AVR_HAVE_PRPD_USART1 -#define __AVR_HAVE_PRPD_USART0 -#define __AVR_HAVE_PRPD_SPI -#define __AVR_HAVE_PRPD_HIRES -#define __AVR_HAVE_PRPD_TC1 -#define __AVR_HAVE_PRPD_TC0 - -/* PR.PRPE */ -#define __AVR_HAVE_PRPE (PR_TWI_bm|PR_USART1_bm|PR_USART0_bm|PR_SPI_bm|PR_HIRES_bm|PR_TC1_bm|PR_TC0_bm) -#define __AVR_HAVE_PRPE_TWI -#define __AVR_HAVE_PRPE_USART1 -#define __AVR_HAVE_PRPE_USART0 -#define __AVR_HAVE_PRPE_SPI -#define __AVR_HAVE_PRPE_HIRES -#define __AVR_HAVE_PRPE_TC1 -#define __AVR_HAVE_PRPE_TC0 - -/* PR.PRPF */ -#define __AVR_HAVE_PRPF (PR_TWI_bm|PR_USART1_bm|PR_USART0_bm|PR_SPI_bm|PR_HIRES_bm|PR_TC1_bm|PR_TC0_bm) -#define __AVR_HAVE_PRPF_TWI -#define __AVR_HAVE_PRPF_USART1 -#define __AVR_HAVE_PRPF_USART0 -#define __AVR_HAVE_PRPF_SPI -#define __AVR_HAVE_PRPF_HIRES -#define __AVR_HAVE_PRPF_TC1 -#define __AVR_HAVE_PRPF_TC0 - - -#endif /* _AVR_ATxmega256A3B_H_ */ - diff --git a/arduino/hardware/tools/avr/avr/include/avr/iox256a3bu.h b/arduino/hardware/tools/avr/avr/include/avr/iox256a3bu.h deleted file mode 100644 index 12a3fa4..0000000 --- a/arduino/hardware/tools/avr/avr/include/avr/iox256a3bu.h +++ /dev/null @@ -1,7706 +0,0 @@ -/***************************************************************************** - * - * Copyright (C) 2015 Atmel Corporation - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * - * * Neither the name of the copyright holders nor the names of - * contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - ****************************************************************************/ - - -#ifndef _AVR_IO_H_ -# error "Include instead of this file." -#endif - -#ifndef _AVR_IOXXX_H_ -# define _AVR_IOXXX_H_ "iox256a3bu.h" -#else -# error "Attempt to include more than one file." -#endif - -#ifndef _AVR_ATXMEGA256A3BU_H_INCLUDED -#define _AVR_ATXMEGA256A3BU_H_INCLUDED - -/* Ungrouped common registers */ -#define GPIOR0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ -#define GPIOR1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ -#define GPIOR2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ -#define GPIOR3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ -#define GPIOR4 _SFR_MEM8(0x0004) /* General Purpose IO Register 4 */ -#define GPIOR5 _SFR_MEM8(0x0005) /* General Purpose IO Register 5 */ -#define GPIOR6 _SFR_MEM8(0x0006) /* General Purpose IO Register 6 */ -#define GPIOR7 _SFR_MEM8(0x0007) /* General Purpose IO Register 7 */ -#define GPIOR8 _SFR_MEM8(0x0008) /* General Purpose IO Register 8 */ -#define GPIOR9 _SFR_MEM8(0x0009) /* General Purpose IO Register 9 */ -#define GPIORA _SFR_MEM8(0x000A) /* General Purpose IO Register 10 */ -#define GPIORB _SFR_MEM8(0x000B) /* General Purpose IO Register 11 */ -#define GPIORC _SFR_MEM8(0x000C) /* General Purpose IO Register 12 */ -#define GPIORD _SFR_MEM8(0x000D) /* General Purpose IO Register 13 */ -#define GPIORE _SFR_MEM8(0x000E) /* General Purpose IO Register 14 */ -#define GPIORF _SFR_MEM8(0x000F) /* General Purpose IO Register 15 */ - -/* Deprecated */ -#define GPIO0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ -#define GPIO1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ -#define GPIO2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ -#define GPIO3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ -#define GPIO4 _SFR_MEM8(0x0004) /* General Purpose IO Register 4 */ -#define GPIO5 _SFR_MEM8(0x0005) /* General Purpose IO Register 5 */ -#define GPIO6 _SFR_MEM8(0x0006) /* General Purpose IO Register 6 */ -#define GPIO7 _SFR_MEM8(0x0007) /* General Purpose IO Register 7 */ -#define GPIO8 _SFR_MEM8(0x0008) /* General Purpose IO Register 8 */ -#define GPIO9 _SFR_MEM8(0x0009) /* General Purpose IO Register 9 */ -#define GPIOA _SFR_MEM8(0x000A) /* General Purpose IO Register 10 */ -#define GPIOB _SFR_MEM8(0x000B) /* General Purpose IO Register 11 */ -#define GPIOC _SFR_MEM8(0x000C) /* General Purpose IO Register 12 */ -#define GPIOD _SFR_MEM8(0x000D) /* General Purpose IO Register 13 */ -#define GPIOE _SFR_MEM8(0x000E) /* General Purpose IO Register 14 */ -#define GPIOF _SFR_MEM8(0x000F) /* General Purpose IO Register 15 */ - -#define CCP _SFR_MEM8(0x0034) /* Configuration Change Protection */ -#define RAMPD _SFR_MEM8(0x0038) /* Ramp D */ -#define RAMPX _SFR_MEM8(0x0039) /* Ramp X */ -#define RAMPY _SFR_MEM8(0x003A) /* Ramp Y */ -#define RAMPZ _SFR_MEM8(0x003B) /* Ramp Z */ -#define EIND _SFR_MEM8(0x003C) /* Extended Indirect Jump */ -#define SPL _SFR_MEM8(0x003D) /* Stack Pointer Low */ -#define SPH _SFR_MEM8(0x003E) /* Stack Pointer High */ -#define SREG _SFR_MEM8(0x003F) /* Status Register */ - -/* C Language Only */ -#if !defined (__ASSEMBLER__) - -#include - -typedef volatile uint8_t register8_t; -typedef volatile uint16_t register16_t; -typedef volatile uint32_t register32_t; - - -#ifdef _WORDREGISTER -#undef _WORDREGISTER -#endif -#define _WORDREGISTER(regname) \ - __extension__ union \ - { \ - register16_t regname; \ - struct \ - { \ - register8_t regname ## L; \ - register8_t regname ## H; \ - }; \ - } - -#ifdef _DWORDREGISTER -#undef _DWORDREGISTER -#endif -#define _DWORDREGISTER(regname) \ - __extension__ union \ - { \ - register32_t regname; \ - struct \ - { \ - register8_t regname ## 0; \ - register8_t regname ## 1; \ - register8_t regname ## 2; \ - register8_t regname ## 3; \ - }; \ - } - - -/* -========================================================================== -IO Module Structures -========================================================================== -*/ - - -/* --------------------------------------------------------------------------- -VPORT - Virtual Ports --------------------------------------------------------------------------- -*/ - -/* Virtual Port */ -typedef struct VPORT_struct -{ - register8_t DIR; /* I/O Port Data Direction */ - register8_t OUT; /* I/O Port Output */ - register8_t IN; /* I/O Port Input */ - register8_t INTFLAGS; /* Interrupt Flag Register */ -} VPORT_t; - - -/* --------------------------------------------------------------------------- -XOCD - On-Chip Debug System --------------------------------------------------------------------------- -*/ - -/* On-Chip Debug System */ -typedef struct OCD_struct -{ - register8_t OCDR0; /* OCD Register 0 */ - register8_t OCDR1; /* OCD Register 1 */ -} OCD_t; - - -/* --------------------------------------------------------------------------- -CPU - CPU --------------------------------------------------------------------------- -*/ - -/* CCP signatures */ -typedef enum CCP_enum -{ - CCP_SPM_gc = (0x9D<<0), /* SPM Instruction Protection */ - CCP_IOREG_gc = (0xD8<<0), /* IO Register Protection */ -} CCP_t; - - -/* --------------------------------------------------------------------------- -CLK - Clock System --------------------------------------------------------------------------- -*/ - -/* Clock System */ -typedef struct CLK_struct -{ - register8_t CTRL; /* Control Register */ - register8_t PSCTRL; /* Prescaler Control Register */ - register8_t LOCK; /* Lock register */ - register8_t RTCCTRL; /* RTC Control Register */ - register8_t USBCTRL; /* USB Control Register */ -} CLK_t; - - -/* Power Reduction */ -typedef struct PR_struct -{ - register8_t PRGEN; /* General Power Reduction */ - register8_t PRPA; /* Power Reduction Port A */ - register8_t PRPB; /* Power Reduction Port B */ - register8_t PRPC; /* Power Reduction Port C */ - register8_t PRPD; /* Power Reduction Port D */ - register8_t PRPE; /* Power Reduction Port E */ - register8_t PRPF; /* Power Reduction Port F */ -} PR_t; - -/* System Clock Selection */ -typedef enum CLK_SCLKSEL_enum -{ - CLK_SCLKSEL_RC2M_gc = (0x00<<0), /* Internal 2 MHz RC Oscillator */ - CLK_SCLKSEL_RC32M_gc = (0x01<<0), /* Internal 32 MHz RC Oscillator */ - CLK_SCLKSEL_RC32K_gc = (0x02<<0), /* Internal 32.768 kHz RC Oscillator */ - CLK_SCLKSEL_XOSC_gc = (0x03<<0), /* External Crystal Oscillator or Clock */ - CLK_SCLKSEL_PLL_gc = (0x04<<0), /* Phase Locked Loop */ -} CLK_SCLKSEL_t; - -/* Prescaler A Division Factor */ -typedef enum CLK_PSADIV_enum -{ - CLK_PSADIV_1_gc = (0x00<<2), /* Divide by 1 */ - CLK_PSADIV_2_gc = (0x01<<2), /* Divide by 2 */ - CLK_PSADIV_4_gc = (0x03<<2), /* Divide by 4 */ - CLK_PSADIV_8_gc = (0x05<<2), /* Divide by 8 */ - CLK_PSADIV_16_gc = (0x07<<2), /* Divide by 16 */ - CLK_PSADIV_32_gc = (0x09<<2), /* Divide by 32 */ - CLK_PSADIV_64_gc = (0x0B<<2), /* Divide by 64 */ - CLK_PSADIV_128_gc = (0x0D<<2), /* Divide by 128 */ - CLK_PSADIV_256_gc = (0x0F<<2), /* Divide by 256 */ - CLK_PSADIV_512_gc = (0x11<<2), /* Divide by 512 */ -} CLK_PSADIV_t; - -/* Prescaler B and C Division Factor */ -typedef enum CLK_PSBCDIV_enum -{ - CLK_PSBCDIV_1_1_gc = (0x00<<0), /* Divide B by 1 and C by 1 */ - CLK_PSBCDIV_1_2_gc = (0x01<<0), /* Divide B by 1 and C by 2 */ - CLK_PSBCDIV_4_1_gc = (0x02<<0), /* Divide B by 4 and C by 1 */ - CLK_PSBCDIV_2_2_gc = (0x03<<0), /* Divide B by 2 and C by 2 */ -} CLK_PSBCDIV_t; - -/* RTC Clock Source */ -typedef enum CLK_RTCSRC_enum -{ - CLK_RTCSRC_ULP_gc = (0x00<<1), /* 1.024 kHz from internal 32kHz ULP */ - CLK_RTCSRC_TOSC_gc = (0x01<<1), /* 1.024 kHz from 32.768 kHz crystal oscillator on TOSC */ - CLK_RTCSRC_RCOSC_gc = (0x02<<1), /* 1.024 kHz from internal 32.768 kHz RC oscillator */ - CLK_RTCSRC_TOSC32_gc = (0x05<<1), /* 32.768 kHz from 32.768 kHz crystal oscillator on TOSC */ - CLK_RTCSRC_RCOSC32_gc = (0x06<<1), /* 32.768 kHz from internal 32.768 kHz RC oscillator */ - CLK_RTCSRC_EXTCLK_gc = (0x07<<1), /* External Clock from TOSC1 */ -} CLK_RTCSRC_t; - -/* USB Prescaler Division Factor */ -typedef enum CLK_USBPSDIV_enum -{ - CLK_USBPSDIV_1_gc = (0x00<<3), /* Divide by 1 */ - CLK_USBPSDIV_2_gc = (0x01<<3), /* Divide by 2 */ - CLK_USBPSDIV_4_gc = (0x02<<3), /* Divide by 4 */ - CLK_USBPSDIV_8_gc = (0x03<<3), /* Divide by 8 */ - CLK_USBPSDIV_16_gc = (0x04<<3), /* Divide by 16 */ - CLK_USBPSDIV_32_gc = (0x05<<3), /* Divide by 32 */ -} CLK_USBPSDIV_t; - -/* USB Clock Source */ -typedef enum CLK_USBSRC_enum -{ - CLK_USBSRC_PLL_gc = (0x00<<1), /* PLL */ - CLK_USBSRC_RC32M_gc = (0x01<<1), /* Internal 32 MHz RC Oscillator */ -} CLK_USBSRC_t; - - -/* --------------------------------------------------------------------------- -SLEEP - Sleep Controller --------------------------------------------------------------------------- -*/ - -/* Sleep Controller */ -typedef struct SLEEP_struct -{ - register8_t CTRL; /* Control Register */ -} SLEEP_t; - -/* Sleep Mode */ -typedef enum SLEEP_SMODE_enum -{ - SLEEP_SMODE_IDLE_gc = (0x00<<1), /* Idle mode */ - SLEEP_SMODE_PDOWN_gc = (0x02<<1), /* Power-down Mode */ - SLEEP_SMODE_PSAVE_gc = (0x03<<1), /* Power-save Mode */ - SLEEP_SMODE_STDBY_gc = (0x06<<1), /* Standby Mode */ - SLEEP_SMODE_ESTDBY_gc = (0x07<<1), /* Extended Standby Mode */ -} SLEEP_SMODE_t; - - - -#define SLEEP_MODE_IDLE (0x00<<1) -#define SLEEP_MODE_PWR_DOWN (0x02<<1) -#define SLEEP_MODE_PWR_SAVE (0x03<<1) -#define SLEEP_MODE_STANDBY (0x06<<1) -#define SLEEP_MODE_EXT_STANDBY (0x07<<1) -/* --------------------------------------------------------------------------- -OSC - Oscillator --------------------------------------------------------------------------- -*/ - -/* Oscillator */ -typedef struct OSC_struct -{ - register8_t CTRL; /* Control Register */ - register8_t STATUS; /* Status Register */ - register8_t XOSCCTRL; /* External Oscillator Control Register */ - register8_t XOSCFAIL; /* Oscillator Failure Detection Register */ - register8_t RC32KCAL; /* 32.768 kHz Internal Oscillator Calibration Register */ - register8_t PLLCTRL; /* PLL Control Register */ - register8_t DFLLCTRL; /* DFLL Control Register */ -} OSC_t; - -/* Oscillator Frequency Range */ -typedef enum OSC_FRQRANGE_enum -{ - OSC_FRQRANGE_04TO2_gc = (0x00<<6), /* 0.4 - 2 MHz */ - OSC_FRQRANGE_2TO9_gc = (0x01<<6), /* 2 - 9 MHz */ - OSC_FRQRANGE_9TO12_gc = (0x02<<6), /* 9 - 12 MHz */ - OSC_FRQRANGE_12TO16_gc = (0x03<<6), /* 12 - 16 MHz */ -} OSC_FRQRANGE_t; - -/* External Oscillator Selection and Startup Time */ -typedef enum OSC_XOSCSEL_enum -{ - OSC_XOSCSEL_EXTCLK_gc = (0x00<<0), /* External Clock - 6 CLK */ - OSC_XOSCSEL_32KHz_gc = (0x02<<0), /* 32.768 kHz TOSC - 32K CLK */ - OSC_XOSCSEL_XTAL_256CLK_gc = (0x03<<0), /* 0.4-16 MHz XTAL - 256 CLK */ - OSC_XOSCSEL_XTAL_1KCLK_gc = (0x07<<0), /* 0.4-16 MHz XTAL - 1K CLK */ - OSC_XOSCSEL_XTAL_16KCLK_gc = (0x0B<<0), /* 0.4-16 MHz XTAL - 16K CLK */ -} OSC_XOSCSEL_t; - -/* PLL Clock Source */ -typedef enum OSC_PLLSRC_enum -{ - OSC_PLLSRC_RC2M_gc = (0x00<<6), /* Internal 2 MHz RC Oscillator */ - OSC_PLLSRC_RC32M_gc = (0x02<<6), /* Internal 32 MHz RC Oscillator */ - OSC_PLLSRC_XOSC_gc = (0x03<<6), /* External Oscillator */ -} OSC_PLLSRC_t; - -/* 2 MHz DFLL Calibration Reference */ -typedef enum OSC_RC2MCREF_enum -{ - OSC_RC2MCREF_RC32K_gc = (0x00<<0), /* Internal 32.768 kHz RC Oscillator */ - OSC_RC2MCREF_XOSC32K_gc = (0x01<<0), /* External 32.768 kHz Crystal Oscillator */ -} OSC_RC2MCREF_t; - -/* 32 MHz DFLL Calibration Reference */ -typedef enum OSC_RC32MCREF_enum -{ - OSC_RC32MCREF_RC32K_gc = (0x00<<1), /* Internal 32.768 kHz RC Oscillator */ - OSC_RC32MCREF_XOSC32K_gc = (0x01<<1), /* External 32.768 kHz Crystal Oscillator */ - OSC_RC32MCREF_USBSOF_gc = (0x02<<1), /* USB Start of Frame */ -} OSC_RC32MCREF_t; - - -/* --------------------------------------------------------------------------- -DFLL - DFLL --------------------------------------------------------------------------- -*/ - -/* DFLL */ -typedef struct DFLL_struct -{ - register8_t CTRL; /* Control Register */ - register8_t reserved_0x01; - register8_t CALA; /* Calibration Register A */ - register8_t CALB; /* Calibration Register B */ - register8_t COMP0; /* Oscillator Compare Register 0 */ - register8_t COMP1; /* Oscillator Compare Register 1 */ - register8_t COMP2; /* Oscillator Compare Register 2 */ - register8_t reserved_0x07; -} DFLL_t; - - -/* --------------------------------------------------------------------------- -RST - Reset --------------------------------------------------------------------------- -*/ - -/* Reset */ -typedef struct RST_struct -{ - register8_t STATUS; /* Status Register */ - register8_t CTRL; /* Control Register */ -} RST_t; - - -/* --------------------------------------------------------------------------- -WDT - Watch-Dog Timer --------------------------------------------------------------------------- -*/ - -/* Watch-Dog Timer */ -typedef struct WDT_struct -{ - register8_t CTRL; /* Control */ - register8_t WINCTRL; /* Windowed Mode Control */ - register8_t STATUS; /* Status */ -} WDT_t; - -/* Period setting */ -typedef enum WDT_PER_enum -{ - WDT_PER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ - WDT_PER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ - WDT_PER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ - WDT_PER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ - WDT_PER_128CLK_gc = (0x04<<2), /* 128 cycles (0.128s @ 3.3V) */ - WDT_PER_256CLK_gc = (0x05<<2), /* 256 cycles (0.256s @ 3.3V) */ - WDT_PER_512CLK_gc = (0x06<<2), /* 512 cycles (0.512s @ 3.3V) */ - WDT_PER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ - WDT_PER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ - WDT_PER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ - WDT_PER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ -} WDT_PER_t; - -/* Closed window period */ -typedef enum WDT_WPER_enum -{ - WDT_WPER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ - WDT_WPER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ - WDT_WPER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ - WDT_WPER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ - WDT_WPER_128CLK_gc = (0x04<<2), /* 128 cycles (0.128s @ 3.3V) */ - WDT_WPER_256CLK_gc = (0x05<<2), /* 256 cycles (0.256s @ 3.3V) */ - WDT_WPER_512CLK_gc = (0x06<<2), /* 512 cycles (0.512s @ 3.3V) */ - WDT_WPER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ - WDT_WPER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ - WDT_WPER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ - WDT_WPER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ -} WDT_WPER_t; - - -/* --------------------------------------------------------------------------- -MCU - MCU Control --------------------------------------------------------------------------- -*/ - -/* MCU Control */ -typedef struct MCU_struct -{ - register8_t DEVID0; /* Device ID byte 0 */ - register8_t DEVID1; /* Device ID byte 1 */ - register8_t DEVID2; /* Device ID byte 2 */ - register8_t REVID; /* Revision ID */ - register8_t JTAGUID; /* JTAG User ID */ - register8_t reserved_0x05; - register8_t MCUCR; /* MCU Control */ - register8_t ANAINIT; /* Analog Startup Delay */ - register8_t EVSYSLOCK; /* Event System Lock */ - register8_t AWEXLOCK; /* AWEX Lock */ - register8_t reserved_0x0A; - register8_t reserved_0x0B; -} MCU_t; - - -/* --------------------------------------------------------------------------- -PMIC - Programmable Multi-level Interrupt Controller --------------------------------------------------------------------------- -*/ - -/* Programmable Multi-level Interrupt Controller */ -typedef struct PMIC_struct -{ - register8_t STATUS; /* Status Register */ - register8_t INTPRI; /* Interrupt Priority */ - register8_t CTRL; /* Control Register */ - register8_t reserved_0x03; - register8_t reserved_0x04; - register8_t reserved_0x05; - register8_t reserved_0x06; - register8_t reserved_0x07; - register8_t reserved_0x08; - register8_t reserved_0x09; - register8_t reserved_0x0A; - register8_t reserved_0x0B; - register8_t reserved_0x0C; - register8_t reserved_0x0D; - register8_t reserved_0x0E; - register8_t reserved_0x0F; -} PMIC_t; - - -/* --------------------------------------------------------------------------- -PORTCFG - Port Configuration --------------------------------------------------------------------------- -*/ - -/* I/O port Configuration */ -typedef struct PORTCFG_struct -{ - register8_t MPCMASK; /* Multi-pin Configuration Mask */ - register8_t reserved_0x01; - register8_t VPCTRLA; /* Virtual Port Control Register A */ - register8_t VPCTRLB; /* Virtual Port Control Register B */ - register8_t CLKEVOUT; /* Clock and Event Out Register */ - register8_t EBIOUT; /* EBI Output register */ - register8_t EVOUTSEL; /* Event Output Select */ -} PORTCFG_t; - -/* Virtual Port Mapping */ -typedef enum PORTCFG_VP02MAP_enum -{ - PORTCFG_VP02MAP_PORTA_gc = (0x00<<0), /* Mapped To PORTA */ - PORTCFG_VP02MAP_PORTB_gc = (0x01<<0), /* Mapped To PORTB */ - PORTCFG_VP02MAP_PORTC_gc = (0x02<<0), /* Mapped To PORTC */ - PORTCFG_VP02MAP_PORTD_gc = (0x03<<0), /* Mapped To PORTD */ - PORTCFG_VP02MAP_PORTE_gc = (0x04<<0), /* Mapped To PORTE */ - PORTCFG_VP02MAP_PORTF_gc = (0x05<<0), /* Mapped To PORTF */ - PORTCFG_VP02MAP_PORTG_gc = (0x06<<0), /* Mapped To PORTG */ - PORTCFG_VP02MAP_PORTH_gc = (0x07<<0), /* Mapped To PORTH */ - PORTCFG_VP02MAP_PORTJ_gc = (0x08<<0), /* Mapped To PORTJ */ - PORTCFG_VP02MAP_PORTK_gc = (0x09<<0), /* Mapped To PORTK */ - PORTCFG_VP02MAP_PORTL_gc = (0x0A<<0), /* Mapped To PORTL */ - PORTCFG_VP02MAP_PORTM_gc = (0x0B<<0), /* Mapped To PORTM */ - PORTCFG_VP02MAP_PORTN_gc = (0x0C<<0), /* Mapped To PORTN */ - PORTCFG_VP02MAP_PORTP_gc = (0x0D<<0), /* Mapped To PORTP */ - PORTCFG_VP02MAP_PORTQ_gc = (0x0E<<0), /* Mapped To PORTQ */ - PORTCFG_VP02MAP_PORTR_gc = (0x0F<<0), /* Mapped To PORTR */ -} PORTCFG_VP02MAP_t; - -/* Virtual Port Mapping */ -typedef enum PORTCFG_VP13MAP_enum -{ - PORTCFG_VP13MAP_PORTA_gc = (0x00<<4), /* Mapped To PORTA */ - PORTCFG_VP13MAP_PORTB_gc = (0x01<<4), /* Mapped To PORTB */ - PORTCFG_VP13MAP_PORTC_gc = (0x02<<4), /* Mapped To PORTC */ - PORTCFG_VP13MAP_PORTD_gc = (0x03<<4), /* Mapped To PORTD */ - PORTCFG_VP13MAP_PORTE_gc = (0x04<<4), /* Mapped To PORTE */ - PORTCFG_VP13MAP_PORTF_gc = (0x05<<4), /* Mapped To PORTF */ - PORTCFG_VP13MAP_PORTG_gc = (0x06<<4), /* Mapped To PORTG */ - PORTCFG_VP13MAP_PORTH_gc = (0x07<<4), /* Mapped To PORTH */ - PORTCFG_VP13MAP_PORTJ_gc = (0x08<<4), /* Mapped To PORTJ */ - PORTCFG_VP13MAP_PORTK_gc = (0x09<<4), /* Mapped To PORTK */ - PORTCFG_VP13MAP_PORTL_gc = (0x0A<<4), /* Mapped To PORTL */ - PORTCFG_VP13MAP_PORTM_gc = (0x0B<<4), /* Mapped To PORTM */ - PORTCFG_VP13MAP_PORTN_gc = (0x0C<<4), /* Mapped To PORTN */ - PORTCFG_VP13MAP_PORTP_gc = (0x0D<<4), /* Mapped To PORTP */ - PORTCFG_VP13MAP_PORTQ_gc = (0x0E<<4), /* Mapped To PORTQ */ - PORTCFG_VP13MAP_PORTR_gc = (0x0F<<4), /* Mapped To PORTR */ -} PORTCFG_VP13MAP_t; - -/* System Clock Output Port */ -typedef enum PORTCFG_CLKOUT_enum -{ - PORTCFG_CLKOUT_OFF_gc = (0x00<<0), /* System Clock Output Disabled */ - PORTCFG_CLKOUT_PC7_gc = (0x01<<0), /* System Clock Output on Port C pin 7 */ - PORTCFG_CLKOUT_PD7_gc = (0x02<<0), /* System Clock Output on Port D pin 7 */ - PORTCFG_CLKOUT_PE7_gc = (0x03<<0), /* System Clock Output on Port E pin 7 */ -} PORTCFG_CLKOUT_t; - -/* Peripheral Clock Output Select */ -typedef enum PORTCFG_CLKOUTSEL_enum -{ - PORTCFG_CLKOUTSEL_CLK1X_gc = (0x00<<2), /* 1x Peripheral Clock Output to pin */ - PORTCFG_CLKOUTSEL_CLK2X_gc = (0x01<<2), /* 2x Peripheral Clock Output to pin */ - PORTCFG_CLKOUTSEL_CLK4X_gc = (0x02<<2), /* 4x Peripheral Clock Output to pin */ -} PORTCFG_CLKOUTSEL_t; - -/* Event Output Port */ -typedef enum PORTCFG_EVOUT_enum -{ - PORTCFG_EVOUT_OFF_gc = (0x00<<4), /* Event Output Disabled */ - PORTCFG_EVOUT_PC7_gc = (0x01<<4), /* Event Channel 7 Output on Port C pin 7 */ - PORTCFG_EVOUT_PD7_gc = (0x02<<4), /* Event Channel 7 Output on Port D pin 7 */ - PORTCFG_EVOUT_PE7_gc = (0x03<<4), /* Event Channel 7 Output on Port E pin 7 */ -} PORTCFG_EVOUT_t; - -/* Clock and Event Output Port */ -typedef enum PORTCFG_CLKEVPIN_enum -{ - PORTCFG_CLKEVPIN_PIN7_gc = (0x00<<7), /* Clock and Event Ouput on PIN 7 */ - PORTCFG_CLKEVPIN_PIN4_gc = (0x01<<7), /* Clock and Event Ouput on PIN 4 */ -} PORTCFG_CLKEVPIN_t; - -/* EBI Address Output Port */ -typedef enum PORTCFG_EBIADROUT_enum -{ - PORTCFG_EBIADROUT_PF_gc = (0x00<<2), /* EBI port 3 address output on PORTF pins 0 to 7 */ - PORTCFG_EBIADROUT_PE_gc = (0x01<<2), /* EBI port 3 address output on PORTE pins 0 to 7 */ - PORTCFG_EBIADROUT_PFH_gc = (0x02<<2), /* EBI port 3 address output on PORTF pins 4 to 7 */ - PORTCFG_EBIADROUT_PEH_gc = (0x03<<2), /* EBI port 3 address output on PORTE pins 4 to 7 */ -} PORTCFG_EBIADROUT_t; - -/* EBI Chip Select Output Port */ -typedef enum PORTCFG_EBICSOUT_enum -{ - PORTCFG_EBICSOUT_PH_gc = (0x00<<0), /* EBI chip select output to PORTH pin 4 to 7 */ - PORTCFG_EBICSOUT_PL_gc = (0x01<<0), /* EBI chip select output to PORTL pin 4 to 7 */ - PORTCFG_EBICSOUT_PF_gc = (0x02<<0), /* EBI chip select output to PORTF pin 4 to 7 */ - PORTCFG_EBICSOUT_PE_gc = (0x03<<0), /* EBI chip select output to PORTE pin 4 to 7 */ -} PORTCFG_EBICSOUT_t; - -/* Event Output Select */ -typedef enum PORTCFG_EVOUTSEL_enum -{ - PORTCFG_EVOUTSEL_0_gc = (0x00<<0), /* Event Channel 0 output to pin */ - PORTCFG_EVOUTSEL_1_gc = (0x01<<0), /* Event Channel 1 output to pin */ - PORTCFG_EVOUTSEL_2_gc = (0x02<<0), /* Event Channel 2 output to pin */ - PORTCFG_EVOUTSEL_3_gc = (0x03<<0), /* Event Channel 3 output to pin */ - PORTCFG_EVOUTSEL_4_gc = (0x04<<0), /* Event Channel 4 output to pin */ - PORTCFG_EVOUTSEL_5_gc = (0x05<<0), /* Event Channel 5 output to pin */ - PORTCFG_EVOUTSEL_6_gc = (0x06<<0), /* Event Channel 6 output to pin */ - PORTCFG_EVOUTSEL_7_gc = (0x07<<0), /* Event Channel 7 output to pin */ -} PORTCFG_EVOUTSEL_t; - - -/* --------------------------------------------------------------------------- -AES - AES Module --------------------------------------------------------------------------- -*/ - -/* AES Module */ -typedef struct AES_struct -{ - register8_t CTRL; /* AES Control Register */ - register8_t STATUS; /* AES Status Register */ - register8_t STATE; /* AES State Register */ - register8_t KEY; /* AES Key Register */ - register8_t INTCTRL; /* AES Interrupt Control Register */ -} AES_t; - -/* Interrupt level */ -typedef enum AES_INTLVL_enum -{ - AES_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - AES_INTLVL_LO_gc = (0x01<<0), /* Low Level */ - AES_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ - AES_INTLVL_HI_gc = (0x03<<0), /* High Level */ -} AES_INTLVL_t; - - -/* --------------------------------------------------------------------------- -CRC - Cyclic Redundancy Checker --------------------------------------------------------------------------- -*/ - -/* Cyclic Redundancy Checker */ -typedef struct CRC_struct -{ - register8_t CTRL; /* Control Register */ - register8_t STATUS; /* Status Register */ - register8_t reserved_0x02; - register8_t DATAIN; /* Data Input */ - register8_t CHECKSUM0; /* Checksum byte 0 */ - register8_t CHECKSUM1; /* Checksum byte 1 */ - register8_t CHECKSUM2; /* Checksum byte 2 */ - register8_t CHECKSUM3; /* Checksum byte 3 */ -} CRC_t; - -/* Reset */ -typedef enum CRC_RESET_enum -{ - CRC_RESET_NO_gc = (0x00<<6), /* No Reset */ - CRC_RESET_RESET0_gc = (0x02<<6), /* Reset CRC with CHECKSUM to all zeros */ - CRC_RESET_RESET1_gc = (0x03<<6), /* Reset CRC with CHECKSUM to all ones */ -} CRC_RESET_t; - -/* Input Source */ -typedef enum CRC_SOURCE_enum -{ - CRC_SOURCE_DISABLE_gc = (0x00<<0), /* Disabled */ - CRC_SOURCE_IO_gc = (0x01<<0), /* I/O Interface */ - CRC_SOURCE_FLASH_gc = (0x02<<0), /* Flash */ - CRC_SOURCE_DMAC0_gc = (0x04<<0), /* DMAC Channel 0 */ - CRC_SOURCE_DMAC1_gc = (0x05<<0), /* DMAC Channel 1 */ - CRC_SOURCE_DMAC2_gc = (0x06<<0), /* DMAC Channel 2 */ - CRC_SOURCE_DMAC3_gc = (0x07<<0), /* DMAC Channel 3 */ -} CRC_SOURCE_t; - - -/* --------------------------------------------------------------------------- -VBAT - Battery Backup Module --------------------------------------------------------------------------- -*/ - -/* Battery Backup Module */ -typedef struct VBAT_struct -{ - register8_t CTRL; /* Control Register */ - register8_t STATUS; /* Status Register */ - register8_t BACKUP0; /* Backup Register 0 */ - register8_t BACKUP1; /* Backup Register 1 */ -} VBAT_t; - - -/* --------------------------------------------------------------------------- -DMA - DMA Controller --------------------------------------------------------------------------- -*/ - -/* DMA Channel */ -typedef struct DMA_CH_struct -{ - register8_t CTRLA; /* Channel Control */ - register8_t CTRLB; /* Channel Control */ - register8_t ADDRCTRL; /* Address Control */ - register8_t TRIGSRC; /* Channel Trigger Source */ - _WORDREGISTER(TRFCNT); /* Channel Block Transfer Count */ - register8_t REPCNT; /* Channel Repeat Count */ - register8_t reserved_0x07; - register8_t SRCADDR0; /* Channel Source Address 0 */ - register8_t SRCADDR1; /* Channel Source Address 1 */ - register8_t SRCADDR2; /* Channel Source Address 2 */ - register8_t reserved_0x0B; - register8_t DESTADDR0; /* Channel Destination Address 0 */ - register8_t DESTADDR1; /* Channel Destination Address 1 */ - register8_t DESTADDR2; /* Channel Destination Address 2 */ - register8_t reserved_0x0F; -} DMA_CH_t; - - -/* DMA Controller */ -typedef struct DMA_struct -{ - register8_t CTRL; /* Control */ - register8_t reserved_0x01; - register8_t reserved_0x02; - register8_t INTFLAGS; /* Transfer Interrupt Status */ - register8_t STATUS; /* Status */ - register8_t reserved_0x05; - _WORDREGISTER(TEMP); /* Temporary Register For 16/24-bit Access */ - register8_t reserved_0x08; - register8_t reserved_0x09; - register8_t reserved_0x0A; - register8_t reserved_0x0B; - register8_t reserved_0x0C; - register8_t reserved_0x0D; - register8_t reserved_0x0E; - register8_t reserved_0x0F; - DMA_CH_t CH0; /* DMA Channel 0 */ - DMA_CH_t CH1; /* DMA Channel 1 */ - DMA_CH_t CH2; /* DMA Channel 2 */ - DMA_CH_t CH3; /* DMA Channel 3 */ -} DMA_t; - -/* Burst mode */ -typedef enum DMA_CH_BURSTLEN_enum -{ - DMA_CH_BURSTLEN_1BYTE_gc = (0x00<<0), /* 1-byte burst mode */ - DMA_CH_BURSTLEN_2BYTE_gc = (0x01<<0), /* 2-byte burst mode */ - DMA_CH_BURSTLEN_4BYTE_gc = (0x02<<0), /* 4-byte burst mode */ - DMA_CH_BURSTLEN_8BYTE_gc = (0x03<<0), /* 8-byte burst mode */ -} DMA_CH_BURSTLEN_t; - -/* Source address reload mode */ -typedef enum DMA_CH_SRCRELOAD_enum -{ - DMA_CH_SRCRELOAD_NONE_gc = (0x00<<6), /* No reload */ - DMA_CH_SRCRELOAD_BLOCK_gc = (0x01<<6), /* Reload at end of block */ - DMA_CH_SRCRELOAD_BURST_gc = (0x02<<6), /* Reload at end of burst */ - DMA_CH_SRCRELOAD_TRANSACTION_gc = (0x03<<6), /* Reload at end of transaction */ -} DMA_CH_SRCRELOAD_t; - -/* Source addressing mode */ -typedef enum DMA_CH_SRCDIR_enum -{ - DMA_CH_SRCDIR_FIXED_gc = (0x00<<4), /* Fixed */ - DMA_CH_SRCDIR_INC_gc = (0x01<<4), /* Increment */ - DMA_CH_SRCDIR_DEC_gc = (0x02<<4), /* Decrement */ -} DMA_CH_SRCDIR_t; - -/* Destination adress reload mode */ -typedef enum DMA_CH_DESTRELOAD_enum -{ - DMA_CH_DESTRELOAD_NONE_gc = (0x00<<2), /* No reload */ - DMA_CH_DESTRELOAD_BLOCK_gc = (0x01<<2), /* Reload at end of block */ - DMA_CH_DESTRELOAD_BURST_gc = (0x02<<2), /* Reload at end of burst */ - DMA_CH_DESTRELOAD_TRANSACTION_gc = (0x03<<2), /* Reload at end of transaction */ -} DMA_CH_DESTRELOAD_t; - -/* Destination adressing mode */ -typedef enum DMA_CH_DESTDIR_enum -{ - DMA_CH_DESTDIR_FIXED_gc = (0x00<<0), /* Fixed */ - DMA_CH_DESTDIR_INC_gc = (0x01<<0), /* Increment */ - DMA_CH_DESTDIR_DEC_gc = (0x02<<0), /* Decrement */ -} DMA_CH_DESTDIR_t; - -/* Transfer trigger source */ -typedef enum DMA_CH_TRIGSRC_enum -{ - DMA_CH_TRIGSRC_OFF_gc = (0x00<<0), /* Off software triggers only */ - DMA_CH_TRIGSRC_EVSYS_CH0_gc = (0x01<<0), /* Event System Channel 0 */ - DMA_CH_TRIGSRC_EVSYS_CH1_gc = (0x02<<0), /* Event System Channel 1 */ - DMA_CH_TRIGSRC_EVSYS_CH2_gc = (0x03<<0), /* Event System Channel 2 */ - DMA_CH_TRIGSRC_ADCA_CH0_gc = (0x10<<0), /* ADCA Channel 0 */ - DMA_CH_TRIGSRC_ADCA_CH1_gc = (0x11<<0), /* ADCA Channel 1 */ - DMA_CH_TRIGSRC_ADCA_CH2_gc = (0x12<<0), /* ADCA Channel 2 */ - DMA_CH_TRIGSRC_ADCA_CH3_gc = (0x13<<0), /* ADCA Channel 3 */ - DMA_CH_TRIGSRC_ADCA_CH4_gc = (0x14<<0), /* ADCA Channel 0,1,2,3 combined */ - DMA_CH_TRIGSRC_DACA_CH0_gc = (0x15<<0), /* DACA Channel 0 */ - DMA_CH_TRIGSRC_DACA_CH1_gc = (0x16<<0), /* DACA Channel 1 */ - DMA_CH_TRIGSRC_ADCB_CH0_gc = (0x20<<0), /* ADCB Channel 0 */ - DMA_CH_TRIGSRC_ADCB_CH1_gc = (0x21<<0), /* ADCB Channel 1 */ - DMA_CH_TRIGSRC_ADCB_CH2_gc = (0x22<<0), /* ADCB Channel 2 */ - DMA_CH_TRIGSRC_ADCB_CH3_gc = (0x23<<0), /* ADCB Channel 3 */ - DMA_CH_TRIGSRC_ADCB_CH4_gc = (0x24<<0), /* ADCB Channel 0,1,2,3 combined */ - DMA_CH_TRIGSRC_DACB_CH0_gc = (0x25<<0), /* DACB Channel 0 */ - DMA_CH_TRIGSRC_DACB_CH1_gc = (0x26<<0), /* DACB Channel 1 */ - DMA_CH_TRIGSRC_TCC0_OVF_gc = (0x40<<0), /* Timer/Counter C0 Overflow */ - DMA_CH_TRIGSRC_TCC0_ERR_gc = (0x41<<0), /* Timer/Counter C0 Error */ - DMA_CH_TRIGSRC_TCC0_CCA_gc = (0x42<<0), /* Timer/Counter C0 Compare or Capture A */ - DMA_CH_TRIGSRC_TCC0_CCB_gc = (0x43<<0), /* Timer/Counter C0 Compare or Capture B */ - DMA_CH_TRIGSRC_TCC0_CCC_gc = (0x44<<0), /* Timer/Counter C0 Compare or Capture C */ - DMA_CH_TRIGSRC_TCC0_CCD_gc = (0x45<<0), /* Timer/Counter C0 Compare or Capture D */ - DMA_CH_TRIGSRC_TCC1_OVF_gc = (0x46<<0), /* Timer/Counter C1 Overflow */ - DMA_CH_TRIGSRC_TCC1_ERR_gc = (0x47<<0), /* Timer/Counter C1 Error */ - DMA_CH_TRIGSRC_TCC1_CCA_gc = (0x48<<0), /* Timer/Counter C1 Compare or Capture A */ - DMA_CH_TRIGSRC_TCC1_CCB_gc = (0x49<<0), /* Timer/Counter C1 Compare or Capture B */ - DMA_CH_TRIGSRC_SPIC_gc = (0x4A<<0), /* SPI C Transfer Complete */ - DMA_CH_TRIGSRC_USARTC0_RXC_gc = (0x4B<<0), /* USART C0 Receive Complete */ - DMA_CH_TRIGSRC_USARTC0_DRE_gc = (0x4C<<0), /* USART C0 Data Register Empty */ - DMA_CH_TRIGSRC_USARTC1_RXC_gc = (0x4E<<0), /* USART C1 Receive Complete */ - DMA_CH_TRIGSRC_USARTC1_DRE_gc = (0x4F<<0), /* USART C1 Data Register Empty */ - DMA_CH_TRIGSRC_TCD0_OVF_gc = (0x60<<0), /* Timer/Counter D0 Overflow */ - DMA_CH_TRIGSRC_TCD0_ERR_gc = (0x61<<0), /* Timer/Counter D0 Error */ - DMA_CH_TRIGSRC_TCD0_CCA_gc = (0x62<<0), /* Timer/Counter D0 Compare or Capture A */ - DMA_CH_TRIGSRC_TCD0_CCB_gc = (0x63<<0), /* Timer/Counter D0 Compare or Capture B */ - DMA_CH_TRIGSRC_TCD0_CCC_gc = (0x64<<0), /* Timer/Counter D0 Compare or Capture C */ - DMA_CH_TRIGSRC_TCD0_CCD_gc = (0x65<<0), /* Timer/Counter D0 Compare or Capture D */ - DMA_CH_TRIGSRC_TCD1_OVF_gc = (0x66<<0), /* Timer/Counter D1 Overflow */ - DMA_CH_TRIGSRC_TCD1_ERR_gc = (0x67<<0), /* Timer/Counter D1 Error */ - DMA_CH_TRIGSRC_TCD1_CCA_gc = (0x68<<0), /* Timer/Counter D1 Compare or Capture A */ - DMA_CH_TRIGSRC_TCD1_CCB_gc = (0x69<<0), /* Timer/Counter D1 Compare or Capture B */ - DMA_CH_TRIGSRC_SPID_gc = (0x6A<<0), /* SPI D Transfer Complete */ - DMA_CH_TRIGSRC_USARTD0_RXC_gc = (0x6B<<0), /* USART D0 Receive Complete */ - DMA_CH_TRIGSRC_USARTD0_DRE_gc = (0x6C<<0), /* USART D0 Data Register Empty */ - DMA_CH_TRIGSRC_USARTD1_RXC_gc = (0x6E<<0), /* USART D1 Receive Complete */ - DMA_CH_TRIGSRC_USARTD1_DRE_gc = (0x6F<<0), /* USART D1 Data Register Empty */ - DMA_CH_TRIGSRC_TCE0_OVF_gc = (0x80<<0), /* Timer/Counter E0 Overflow */ - DMA_CH_TRIGSRC_TCE0_ERR_gc = (0x81<<0), /* Timer/Counter E0 Error */ - DMA_CH_TRIGSRC_TCE0_CCA_gc = (0x82<<0), /* Timer/Counter E0 Compare or Capture A */ - DMA_CH_TRIGSRC_TCE0_CCB_gc = (0x83<<0), /* Timer/Counter E0 Compare or Capture B */ - DMA_CH_TRIGSRC_TCE0_CCC_gc = (0x84<<0), /* Timer/Counter E0 Compare or Capture C */ - DMA_CH_TRIGSRC_TCE0_CCD_gc = (0x85<<0), /* Timer/Counter E0 Compare or Capture D */ - DMA_CH_TRIGSRC_TCE1_OVF_gc = (0x86<<0), /* Timer/Counter E1 Overflow */ - DMA_CH_TRIGSRC_TCE1_ERR_gc = (0x87<<0), /* Timer/Counter E1 Error */ - DMA_CH_TRIGSRC_TCE1_CCA_gc = (0x88<<0), /* Timer/Counter E1 Compare or Capture A */ - DMA_CH_TRIGSRC_TCE1_CCB_gc = (0x89<<0), /* Timer/Counter E1 Compare or Capture B */ - DMA_CH_TRIGSRC_SPIE_gc = (0x8A<<0), /* SPI E Transfer Complete */ - DMA_CH_TRIGSRC_USARTE0_RXC_gc = (0x8B<<0), /* USART E0 Receive Complete */ - DMA_CH_TRIGSRC_USARTE0_DRE_gc = (0x8C<<0), /* USART E0 Data Register Empty */ - DMA_CH_TRIGSRC_USARTE1_RXC_gc = (0x8E<<0), /* USART E1 Receive Complete */ - DMA_CH_TRIGSRC_USARTE1_DRE_gc = (0x8F<<0), /* USART E1 Data Register Empty */ - DMA_CH_TRIGSRC_TCF0_OVF_gc = (0xA0<<0), /* Timer/Counter F0 Overflow */ - DMA_CH_TRIGSRC_TCF0_ERR_gc = (0xA1<<0), /* Timer/Counter F0 Error */ - DMA_CH_TRIGSRC_TCF0_CCA_gc = (0xA2<<0), /* Timer/Counter F0 Compare or Capture A */ - DMA_CH_TRIGSRC_TCF0_CCB_gc = (0xA3<<0), /* Timer/Counter F0 Compare or Capture B */ - DMA_CH_TRIGSRC_TCF0_CCC_gc = (0xA4<<0), /* Timer/Counter F0 Compare or Capture C */ - DMA_CH_TRIGSRC_TCF0_CCD_gc = (0xA5<<0), /* Timer/Counter F0 Compare or Capture D */ - DMA_CH_TRIGSRC_TCF1_OVF_gc = (0xA6<<0), /* Timer/Counter F1 Overflow */ - DMA_CH_TRIGSRC_TCF1_ERR_gc = (0xA7<<0), /* Timer/Counter F1 Error */ - DMA_CH_TRIGSRC_TCF1_CCA_gc = (0xA8<<0), /* Timer/Counter F1 Compare or Capture A */ - DMA_CH_TRIGSRC_TCF1_CCB_gc = (0xA9<<0), /* Timer/Counter F1 Compare or Capture B */ - DMA_CH_TRIGSRC_SPIF_gc = (0xAA<<0), /* SPI F Transfer Complete */ - DMA_CH_TRIGSRC_USARTF0_RXC_gc = (0xAB<<0), /* USART F0 Receive Complete */ - DMA_CH_TRIGSRC_USARTF0_DRE_gc = (0xAC<<0), /* USART F0 Data Register Empty */ - DMA_CH_TRIGSRC_USARTF1_RXC_gc = (0xAE<<0), /* USART F1 Receive Complete */ - DMA_CH_TRIGSRC_USARTF1_DRE_gc = (0xAF<<0), /* USART F1 Data Register Empty */ -} DMA_CH_TRIGSRC_t; - -/* Double buffering mode */ -typedef enum DMA_DBUFMODE_enum -{ - DMA_DBUFMODE_DISABLED_gc = (0x00<<2), /* Double buffering disabled */ - DMA_DBUFMODE_CH01_gc = (0x01<<2), /* Double buffering enabled on channel 0/1 */ - DMA_DBUFMODE_CH23_gc = (0x02<<2), /* Double buffering enabled on channel 2/3 */ - DMA_DBUFMODE_CH01CH23_gc = (0x03<<2), /* Double buffering enabled on ch. 0/1 and ch. 2/3 */ -} DMA_DBUFMODE_t; - -/* Priority mode */ -typedef enum DMA_PRIMODE_enum -{ - DMA_PRIMODE_RR0123_gc = (0x00<<0), /* Round Robin */ - DMA_PRIMODE_CH0RR123_gc = (0x01<<0), /* Channel 0 > Round Robin on channel 1/2/3 */ - DMA_PRIMODE_CH01RR23_gc = (0x02<<0), /* Channel 0 > channel 1 > Round Robin on channel 2/3 */ - DMA_PRIMODE_CH0123_gc = (0x03<<0), /* Channel 0 > channel 1 > channel 2 > channel 3 */ -} DMA_PRIMODE_t; - -/* Interrupt level */ -typedef enum DMA_CH_ERRINTLVL_enum -{ - DMA_CH_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ - DMA_CH_ERRINTLVL_LO_gc = (0x01<<2), /* Low level */ - DMA_CH_ERRINTLVL_MED_gc = (0x02<<2), /* Medium level */ - DMA_CH_ERRINTLVL_HI_gc = (0x03<<2), /* High level */ -} DMA_CH_ERRINTLVL_t; - -/* Interrupt level */ -typedef enum DMA_CH_TRNINTLVL_enum -{ - DMA_CH_TRNINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ - DMA_CH_TRNINTLVL_LO_gc = (0x01<<0), /* Low level */ - DMA_CH_TRNINTLVL_MED_gc = (0x02<<0), /* Medium level */ - DMA_CH_TRNINTLVL_HI_gc = (0x03<<0), /* High level */ -} DMA_CH_TRNINTLVL_t; - - -/* --------------------------------------------------------------------------- -EVSYS - Event System --------------------------------------------------------------------------- -*/ - -/* Event System */ -typedef struct EVSYS_struct -{ - register8_t CH0MUX; /* Event Channel 0 Multiplexer */ - register8_t CH1MUX; /* Event Channel 1 Multiplexer */ - register8_t CH2MUX; /* Event Channel 2 Multiplexer */ - register8_t CH3MUX; /* Event Channel 3 Multiplexer */ - register8_t CH4MUX; /* Event Channel 4 Multiplexer */ - register8_t CH5MUX; /* Event Channel 5 Multiplexer */ - register8_t CH6MUX; /* Event Channel 6 Multiplexer */ - register8_t CH7MUX; /* Event Channel 7 Multiplexer */ - register8_t CH0CTRL; /* Channel 0 Control Register */ - register8_t CH1CTRL; /* Channel 1 Control Register */ - register8_t CH2CTRL; /* Channel 2 Control Register */ - register8_t CH3CTRL; /* Channel 3 Control Register */ - register8_t CH4CTRL; /* Channel 4 Control Register */ - register8_t CH5CTRL; /* Channel 5 Control Register */ - register8_t CH6CTRL; /* Channel 6 Control Register */ - register8_t CH7CTRL; /* Channel 7 Control Register */ - register8_t STROBE; /* Event Strobe */ - register8_t DATA; /* Event Data */ -} EVSYS_t; - -/* Quadrature Decoder Index Recognition Mode */ -typedef enum EVSYS_QDIRM_enum -{ - EVSYS_QDIRM_00_gc = (0x00<<5), /* QDPH0 = 0, QDPH90 = 0 */ - EVSYS_QDIRM_01_gc = (0x01<<5), /* QDPH0 = 0, QDPH90 = 1 */ - EVSYS_QDIRM_10_gc = (0x02<<5), /* QDPH0 = 1, QDPH90 = 0 */ - EVSYS_QDIRM_11_gc = (0x03<<5), /* QDPH0 = 1, QDPH90 = 1 */ -} EVSYS_QDIRM_t; - -/* Digital filter coefficient */ -typedef enum EVSYS_DIGFILT_enum -{ - EVSYS_DIGFILT_1SAMPLE_gc = (0x00<<0), /* 1 SAMPLE */ - EVSYS_DIGFILT_2SAMPLES_gc = (0x01<<0), /* 2 SAMPLES */ - EVSYS_DIGFILT_3SAMPLES_gc = (0x02<<0), /* 3 SAMPLES */ - EVSYS_DIGFILT_4SAMPLES_gc = (0x03<<0), /* 4 SAMPLES */ - EVSYS_DIGFILT_5SAMPLES_gc = (0x04<<0), /* 5 SAMPLES */ - EVSYS_DIGFILT_6SAMPLES_gc = (0x05<<0), /* 6 SAMPLES */ - EVSYS_DIGFILT_7SAMPLES_gc = (0x06<<0), /* 7 SAMPLES */ - EVSYS_DIGFILT_8SAMPLES_gc = (0x07<<0), /* 8 SAMPLES */ -} EVSYS_DIGFILT_t; - -/* Event Channel multiplexer input selection */ -typedef enum EVSYS_CHMUX_enum -{ - EVSYS_CHMUX_OFF_gc = (0x00<<0), /* Off */ - EVSYS_CHMUX_RTC_OVF_gc = (0x08<<0), /* RTC Overflow */ - EVSYS_CHMUX_RTC_CMP_gc = (0x09<<0), /* RTC Compare Match */ - EVSYS_CHMUX_USB_gc = (0x0A<<0), /* USB Setup, SOF, CRC error and UNF/OVF */ - EVSYS_CHMUX_ACA_CH0_gc = (0x10<<0), /* Analog Comparator A Channel 0 */ - EVSYS_CHMUX_ACA_CH1_gc = (0x11<<0), /* Analog Comparator A Channel 1 */ - EVSYS_CHMUX_ACA_WIN_gc = (0x12<<0), /* Analog Comparator A Window */ - EVSYS_CHMUX_ACB_CH0_gc = (0x13<<0), /* Analog Comparator B Channel 0 */ - EVSYS_CHMUX_ACB_CH1_gc = (0x14<<0), /* Analog Comparator B Channel 1 */ - EVSYS_CHMUX_ACB_WIN_gc = (0x15<<0), /* Analog Comparator B Window */ - EVSYS_CHMUX_ADCA_CH0_gc = (0x20<<0), /* ADC A Channel 0 */ - EVSYS_CHMUX_ADCA_CH1_gc = (0x21<<0), /* ADC A Channel 1 */ - EVSYS_CHMUX_ADCA_CH2_gc = (0x22<<0), /* ADC A Channel 2 */ - EVSYS_CHMUX_ADCA_CH3_gc = (0x23<<0), /* ADC A Channel 3 */ - EVSYS_CHMUX_ADCB_CH0_gc = (0x24<<0), /* ADC B Channel 0 */ - EVSYS_CHMUX_ADCB_CH1_gc = (0x25<<0), /* ADC B Channel 1 */ - EVSYS_CHMUX_ADCB_CH2_gc = (0x26<<0), /* ADC B Channel 2 */ - EVSYS_CHMUX_ADCB_CH3_gc = (0x27<<0), /* ADC B Channel 3 */ - EVSYS_CHMUX_PORTA_PIN0_gc = (0x50<<0), /* Port A, Pin0 */ - EVSYS_CHMUX_PORTA_PIN1_gc = (0x51<<0), /* Port A, Pin1 */ - EVSYS_CHMUX_PORTA_PIN2_gc = (0x52<<0), /* Port A, Pin2 */ - EVSYS_CHMUX_PORTA_PIN3_gc = (0x53<<0), /* Port A, Pin3 */ - EVSYS_CHMUX_PORTA_PIN4_gc = (0x54<<0), /* Port A, Pin4 */ - EVSYS_CHMUX_PORTA_PIN5_gc = (0x55<<0), /* Port A, Pin5 */ - EVSYS_CHMUX_PORTA_PIN6_gc = (0x56<<0), /* Port A, Pin6 */ - EVSYS_CHMUX_PORTA_PIN7_gc = (0x57<<0), /* Port A, Pin7 */ - EVSYS_CHMUX_PORTB_PIN0_gc = (0x58<<0), /* Port B, Pin0 */ - EVSYS_CHMUX_PORTB_PIN1_gc = (0x59<<0), /* Port B, Pin1 */ - EVSYS_CHMUX_PORTB_PIN2_gc = (0x5A<<0), /* Port B, Pin2 */ - EVSYS_CHMUX_PORTB_PIN3_gc = (0x5B<<0), /* Port B, Pin3 */ - EVSYS_CHMUX_PORTB_PIN4_gc = (0x5C<<0), /* Port B, Pin4 */ - EVSYS_CHMUX_PORTB_PIN5_gc = (0x5D<<0), /* Port B, Pin5 */ - EVSYS_CHMUX_PORTB_PIN6_gc = (0x5E<<0), /* Port B, Pin6 */ - EVSYS_CHMUX_PORTB_PIN7_gc = (0x5F<<0), /* Port B, Pin7 */ - EVSYS_CHMUX_PORTC_PIN0_gc = (0x60<<0), /* Port C, Pin0 */ - EVSYS_CHMUX_PORTC_PIN1_gc = (0x61<<0), /* Port C, Pin1 */ - EVSYS_CHMUX_PORTC_PIN2_gc = (0x62<<0), /* Port C, Pin2 */ - EVSYS_CHMUX_PORTC_PIN3_gc = (0x63<<0), /* Port C, Pin3 */ - EVSYS_CHMUX_PORTC_PIN4_gc = (0x64<<0), /* Port C, Pin4 */ - EVSYS_CHMUX_PORTC_PIN5_gc = (0x65<<0), /* Port C, Pin5 */ - EVSYS_CHMUX_PORTC_PIN6_gc = (0x66<<0), /* Port C, Pin6 */ - EVSYS_CHMUX_PORTC_PIN7_gc = (0x67<<0), /* Port C, Pin7 */ - EVSYS_CHMUX_PORTD_PIN0_gc = (0x68<<0), /* Port D, Pin0 */ - EVSYS_CHMUX_PORTD_PIN1_gc = (0x69<<0), /* Port D, Pin1 */ - EVSYS_CHMUX_PORTD_PIN2_gc = (0x6A<<0), /* Port D, Pin2 */ - EVSYS_CHMUX_PORTD_PIN3_gc = (0x6B<<0), /* Port D, Pin3 */ - EVSYS_CHMUX_PORTD_PIN4_gc = (0x6C<<0), /* Port D, Pin4 */ - EVSYS_CHMUX_PORTD_PIN5_gc = (0x6D<<0), /* Port D, Pin5 */ - EVSYS_CHMUX_PORTD_PIN6_gc = (0x6E<<0), /* Port D, Pin6 */ - EVSYS_CHMUX_PORTD_PIN7_gc = (0x6F<<0), /* Port D, Pin7 */ - EVSYS_CHMUX_PORTE_PIN0_gc = (0x70<<0), /* Port E, Pin0 */ - EVSYS_CHMUX_PORTE_PIN1_gc = (0x71<<0), /* Port E, Pin1 */ - EVSYS_CHMUX_PORTE_PIN2_gc = (0x72<<0), /* Port E, Pin2 */ - EVSYS_CHMUX_PORTE_PIN3_gc = (0x73<<0), /* Port E, Pin3 */ - EVSYS_CHMUX_PORTE_PIN4_gc = (0x74<<0), /* Port E, Pin4 */ - EVSYS_CHMUX_PORTE_PIN5_gc = (0x75<<0), /* Port E, Pin5 */ - EVSYS_CHMUX_PORTE_PIN6_gc = (0x76<<0), /* Port E, Pin6 */ - EVSYS_CHMUX_PORTE_PIN7_gc = (0x77<<0), /* Port E, Pin7 */ - EVSYS_CHMUX_PORTF_PIN0_gc = (0x78<<0), /* Port F, Pin0 */ - EVSYS_CHMUX_PORTF_PIN1_gc = (0x79<<0), /* Port F, Pin1 */ - EVSYS_CHMUX_PORTF_PIN2_gc = (0x7A<<0), /* Port F, Pin2 */ - EVSYS_CHMUX_PORTF_PIN3_gc = (0x7B<<0), /* Port F, Pin3 */ - EVSYS_CHMUX_PORTF_PIN4_gc = (0x7C<<0), /* Port F, Pin4 */ - EVSYS_CHMUX_PORTF_PIN5_gc = (0x7D<<0), /* Port F, Pin5 */ - EVSYS_CHMUX_PORTF_PIN6_gc = (0x7E<<0), /* Port F, Pin6 */ - EVSYS_CHMUX_PORTF_PIN7_gc = (0x7F<<0), /* Port F, Pin7 */ - EVSYS_CHMUX_PRESCALER_1_gc = (0x80<<0), /* Prescaler, divide by 1 */ - EVSYS_CHMUX_PRESCALER_2_gc = (0x81<<0), /* Prescaler, divide by 2 */ - EVSYS_CHMUX_PRESCALER_4_gc = (0x82<<0), /* Prescaler, divide by 4 */ - EVSYS_CHMUX_PRESCALER_8_gc = (0x83<<0), /* Prescaler, divide by 8 */ - EVSYS_CHMUX_PRESCALER_16_gc = (0x84<<0), /* Prescaler, divide by 16 */ - EVSYS_CHMUX_PRESCALER_32_gc = (0x85<<0), /* Prescaler, divide by 32 */ - EVSYS_CHMUX_PRESCALER_64_gc = (0x86<<0), /* Prescaler, divide by 64 */ - EVSYS_CHMUX_PRESCALER_128_gc = (0x87<<0), /* Prescaler, divide by 128 */ - EVSYS_CHMUX_PRESCALER_256_gc = (0x88<<0), /* Prescaler, divide by 256 */ - EVSYS_CHMUX_PRESCALER_512_gc = (0x89<<0), /* Prescaler, divide by 512 */ - EVSYS_CHMUX_PRESCALER_1024_gc = (0x8A<<0), /* Prescaler, divide by 1024 */ - EVSYS_CHMUX_PRESCALER_2048_gc = (0x8B<<0), /* Prescaler, divide by 2048 */ - EVSYS_CHMUX_PRESCALER_4096_gc = (0x8C<<0), /* Prescaler, divide by 4096 */ - EVSYS_CHMUX_PRESCALER_8192_gc = (0x8D<<0), /* Prescaler, divide by 8192 */ - EVSYS_CHMUX_PRESCALER_16384_gc = (0x8E<<0), /* Prescaler, divide by 16384 */ - EVSYS_CHMUX_PRESCALER_32768_gc = (0x8F<<0), /* Prescaler, divide by 32768 */ - EVSYS_CHMUX_TCC0_OVF_gc = (0xC0<<0), /* Timer/Counter C0 Overflow */ - EVSYS_CHMUX_TCC0_ERR_gc = (0xC1<<0), /* Timer/Counter C0 Error */ - EVSYS_CHMUX_TCC0_CCA_gc = (0xC4<<0), /* Timer/Counter C0 Compare or Capture A */ - EVSYS_CHMUX_TCC0_CCB_gc = (0xC5<<0), /* Timer/Counter C0 Compare or Capture B */ - EVSYS_CHMUX_TCC0_CCC_gc = (0xC6<<0), /* Timer/Counter C0 Compare or Capture C */ - EVSYS_CHMUX_TCC0_CCD_gc = (0xC7<<0), /* Timer/Counter C0 Compare or Capture D */ - EVSYS_CHMUX_TCC1_OVF_gc = (0xC8<<0), /* Timer/Counter C1 Overflow */ - EVSYS_CHMUX_TCC1_ERR_gc = (0xC9<<0), /* Timer/Counter C1 Error */ - EVSYS_CHMUX_TCC1_CCA_gc = (0xCC<<0), /* Timer/Counter C1 Compare or Capture A */ - EVSYS_CHMUX_TCC1_CCB_gc = (0xCD<<0), /* Timer/Counter C1 Compare or Capture B */ - EVSYS_CHMUX_TCD0_OVF_gc = (0xD0<<0), /* Timer/Counter D0 Overflow */ - EVSYS_CHMUX_TCD0_ERR_gc = (0xD1<<0), /* Timer/Counter D0 Error */ - EVSYS_CHMUX_TCD0_CCA_gc = (0xD4<<0), /* Timer/Counter D0 Compare or Capture A */ - EVSYS_CHMUX_TCD0_CCB_gc = (0xD5<<0), /* Timer/Counter D0 Compare or Capture B */ - EVSYS_CHMUX_TCD0_CCC_gc = (0xD6<<0), /* Timer/Counter D0 Compare or Capture C */ - EVSYS_CHMUX_TCD0_CCD_gc = (0xD7<<0), /* Timer/Counter D0 Compare or Capture D */ - EVSYS_CHMUX_TCD1_OVF_gc = (0xD8<<0), /* Timer/Counter D1 Overflow */ - EVSYS_CHMUX_TCD1_ERR_gc = (0xD9<<0), /* Timer/Counter D1 Error */ - EVSYS_CHMUX_TCD1_CCA_gc = (0xDC<<0), /* Timer/Counter D1 Compare or Capture A */ - EVSYS_CHMUX_TCD1_CCB_gc = (0xDD<<0), /* Timer/Counter D1 Compare or Capture B */ - EVSYS_CHMUX_TCE0_OVF_gc = (0xE0<<0), /* Timer/Counter E0 Overflow */ - EVSYS_CHMUX_TCE0_ERR_gc = (0xE1<<0), /* Timer/Counter E0 Error */ - EVSYS_CHMUX_TCE0_CCA_gc = (0xE4<<0), /* Timer/Counter E0 Compare or Capture A */ - EVSYS_CHMUX_TCE0_CCB_gc = (0xE5<<0), /* Timer/Counter E0 Compare or Capture B */ - EVSYS_CHMUX_TCE0_CCC_gc = (0xE6<<0), /* Timer/Counter E0 Compare or Capture C */ - EVSYS_CHMUX_TCE0_CCD_gc = (0xE7<<0), /* Timer/Counter E0 Compare or Capture D */ - EVSYS_CHMUX_TCE1_OVF_gc = (0xE8<<0), /* Timer/Counter E1 Overflow */ - EVSYS_CHMUX_TCE1_ERR_gc = (0xE9<<0), /* Timer/Counter E1 Error */ - EVSYS_CHMUX_TCE1_CCA_gc = (0xEC<<0), /* Timer/Counter E1 Compare or Capture A */ - EVSYS_CHMUX_TCE1_CCB_gc = (0xED<<0), /* Timer/Counter E1 Compare or Capture B */ - EVSYS_CHMUX_TCF0_OVF_gc = (0xF0<<0), /* Timer/Counter F0 Overflow */ - EVSYS_CHMUX_TCF0_ERR_gc = (0xF1<<0), /* Timer/Counter F0 Error */ - EVSYS_CHMUX_TCF0_CCA_gc = (0xF4<<0), /* Timer/Counter F0 Compare or Capture A */ - EVSYS_CHMUX_TCF0_CCB_gc = (0xF5<<0), /* Timer/Counter F0 Compare or Capture B */ - EVSYS_CHMUX_TCF0_CCC_gc = (0xF6<<0), /* Timer/Counter F0 Compare or Capture C */ - EVSYS_CHMUX_TCF0_CCD_gc = (0xF7<<0), /* Timer/Counter F0 Compare or Capture D */ - EVSYS_CHMUX_TCF1_OVF_gc = (0xF8<<0), /* Timer/Counter F1 Overflow */ - EVSYS_CHMUX_TCF1_ERR_gc = (0xF9<<0), /* Timer/Counter F1 Error */ - EVSYS_CHMUX_TCF1_CCA_gc = (0xFC<<0), /* Timer/Counter F1 Compare or Capture A */ - EVSYS_CHMUX_TCF1_CCB_gc = (0xFD<<0), /* Timer/Counter F1 Compare or Capture B */ -} EVSYS_CHMUX_t; - - -/* --------------------------------------------------------------------------- -NVM - Non Volatile Memory Controller --------------------------------------------------------------------------- -*/ - -/* Non-volatile Memory Controller */ -typedef struct NVM_struct -{ - register8_t ADDR0; /* Address Register 0 */ - register8_t ADDR1; /* Address Register 1 */ - register8_t ADDR2; /* Address Register 2 */ - register8_t reserved_0x03; - register8_t DATA0; /* Data Register 0 */ - register8_t DATA1; /* Data Register 1 */ - register8_t DATA2; /* Data Register 2 */ - register8_t reserved_0x07; - register8_t reserved_0x08; - register8_t reserved_0x09; - register8_t CMD; /* Command */ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t INTCTRL; /* Interrupt Control */ - register8_t reserved_0x0E; - register8_t STATUS; /* Status */ - register8_t LOCK_BITS; /* Lock Bits (Changed from LOCKBITS to avoid avr-libc collision) */ -} NVM_t; - -/* NVM Command */ -typedef enum NVM_CMD_enum -{ - NVM_CMD_NO_OPERATION_gc = (0x00<<0), /* Noop/Ordinary LPM */ - NVM_CMD_READ_USER_SIG_ROW_gc = (0x01<<0), /* Read user signature row */ - NVM_CMD_READ_CALIB_ROW_gc = (0x02<<0), /* Read calibration row */ - NVM_CMD_READ_EEPROM_gc = (0x06<<0), /* Read EEPROM */ - NVM_CMD_READ_FUSES_gc = (0x07<<0), /* Read fuse byte */ - NVM_CMD_WRITE_LOCK_BITS_gc = (0x08<<0), /* Write lock bits */ - NVM_CMD_ERASE_USER_SIG_ROW_gc = (0x18<<0), /* Erase user signature row */ - NVM_CMD_WRITE_USER_SIG_ROW_gc = (0x1A<<0), /* Write user signature row */ - NVM_CMD_ERASE_APP_gc = (0x20<<0), /* Erase Application Section */ - NVM_CMD_ERASE_APP_PAGE_gc = (0x22<<0), /* Erase Application Section page */ - NVM_CMD_LOAD_FLASH_BUFFER_gc = (0x23<<0), /* Load Flash page buffer */ - NVM_CMD_WRITE_APP_PAGE_gc = (0x24<<0), /* Write Application Section page */ - NVM_CMD_ERASE_WRITE_APP_PAGE_gc = (0x25<<0), /* Erase-and-write Application Section page */ - NVM_CMD_ERASE_FLASH_BUFFER_gc = (0x26<<0), /* Erase/flush Flash page buffer */ - NVM_CMD_ERASE_BOOT_PAGE_gc = (0x2A<<0), /* Erase Boot Section page */ - NVM_CMD_ERASE_FLASH_PAGE_gc = (0x2B<<0), /* Erase Flash Page */ - NVM_CMD_WRITE_BOOT_PAGE_gc = (0x2C<<0), /* Write Boot Section page */ - NVM_CMD_ERASE_WRITE_BOOT_PAGE_gc = (0x2D<<0), /* Erase-and-write Boot Section page */ - NVM_CMD_WRITE_FLASH_PAGE_gc = (0x2E<<0), /* Write Flash Page */ - NVM_CMD_ERASE_WRITE_FLASH_PAGE_gc = (0x2F<<0), /* Erase-and-write Flash Page */ - NVM_CMD_ERASE_EEPROM_gc = (0x30<<0), /* Erase EEPROM */ - NVM_CMD_ERASE_EEPROM_PAGE_gc = (0x32<<0), /* Erase EEPROM page */ - NVM_CMD_LOAD_EEPROM_BUFFER_gc = (0x33<<0), /* Load EEPROM page buffer */ - NVM_CMD_WRITE_EEPROM_PAGE_gc = (0x34<<0), /* Write EEPROM page */ - NVM_CMD_ERASE_WRITE_EEPROM_PAGE_gc = (0x35<<0), /* Erase-and-write EEPROM page */ - NVM_CMD_ERASE_EEPROM_BUFFER_gc = (0x36<<0), /* Erase/flush EEPROM page buffer */ - NVM_CMD_APP_CRC_gc = (0x38<<0), /* Application section CRC */ - NVM_CMD_BOOT_CRC_gc = (0x39<<0), /* Boot Section CRC */ - NVM_CMD_FLASH_RANGE_CRC_gc = (0x3A<<0), /* Flash Range CRC */ - NVM_CMD_CHIP_ERASE_gc = (0x40<<0), /* Erase Chip */ - NVM_CMD_READ_NVM_gc = (0x43<<0), /* Read NVM */ - NVM_CMD_WRITE_FUSE_gc = (0x4C<<0), /* Write Fuse byte */ - NVM_CMD_ERASE_BOOT_gc = (0x68<<0), /* Erase Boot Section */ - NVM_CMD_FLASH_CRC_gc = (0x78<<0), /* Flash CRC */ -} NVM_CMD_t; - -/* SPM ready interrupt level */ -typedef enum NVM_SPMLVL_enum -{ - NVM_SPMLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ - NVM_SPMLVL_LO_gc = (0x01<<2), /* Low level */ - NVM_SPMLVL_MED_gc = (0x02<<2), /* Medium level */ - NVM_SPMLVL_HI_gc = (0x03<<2), /* High level */ -} NVM_SPMLVL_t; - -/* EEPROM ready interrupt level */ -typedef enum NVM_EELVL_enum -{ - NVM_EELVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ - NVM_EELVL_LO_gc = (0x01<<0), /* Low level */ - NVM_EELVL_MED_gc = (0x02<<0), /* Medium level */ - NVM_EELVL_HI_gc = (0x03<<0), /* High level */ -} NVM_EELVL_t; - -/* Boot lock bits - boot setcion */ -typedef enum NVM_BLBB_enum -{ - NVM_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ - NVM_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ - NVM_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ - NVM_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ -} NVM_BLBB_t; - -/* Boot lock bits - application section */ -typedef enum NVM_BLBA_enum -{ - NVM_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ - NVM_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ - NVM_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ - NVM_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ -} NVM_BLBA_t; - -/* Boot lock bits - application table section */ -typedef enum NVM_BLBAT_enum -{ - NVM_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ - NVM_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ - NVM_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ - NVM_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ -} NVM_BLBAT_t; - -/* Lock bits */ -typedef enum NVM_LB_enum -{ - NVM_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ - NVM_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ - NVM_LB_NOLOCK_gc = (0x03<<0), /* No locks */ -} NVM_LB_t; - - -/* --------------------------------------------------------------------------- -ADC - Analog/Digital Converter --------------------------------------------------------------------------- -*/ - -/* ADC Channel */ -typedef struct ADC_CH_struct -{ - register8_t CTRL; /* Control Register */ - register8_t MUXCTRL; /* MUX Control */ - register8_t INTCTRL; /* Channel Interrupt Control Register */ - register8_t INTFLAGS; /* Interrupt Flags */ - _WORDREGISTER(RES); /* Channel Result */ - register8_t SCAN; /* Input Channel Scan */ - register8_t reserved_0x07; -} ADC_CH_t; - - -/* Analog-to-Digital Converter */ -typedef struct ADC_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t REFCTRL; /* Reference Control */ - register8_t EVCTRL; /* Event Control */ - register8_t PRESCALER; /* Clock Prescaler */ - register8_t reserved_0x05; - register8_t INTFLAGS; /* Interrupt Flags */ - register8_t TEMP; /* Temporary Register */ - register8_t reserved_0x08; - register8_t reserved_0x09; - register8_t reserved_0x0A; - register8_t reserved_0x0B; - _WORDREGISTER(CAL); /* Calibration Value */ - register8_t reserved_0x0E; - register8_t reserved_0x0F; - _WORDREGISTER(CH0RES); /* Channel 0 Result */ - _WORDREGISTER(CH1RES); /* Channel 1 Result */ - _WORDREGISTER(CH2RES); /* Channel 2 Result */ - _WORDREGISTER(CH3RES); /* Channel 3 Result */ - _WORDREGISTER(CMP); /* Compare Value */ - register8_t reserved_0x1A; - register8_t reserved_0x1B; - register8_t reserved_0x1C; - register8_t reserved_0x1D; - register8_t reserved_0x1E; - register8_t reserved_0x1F; - ADC_CH_t CH0; /* ADC Channel 0 */ - ADC_CH_t CH1; /* ADC Channel 1 */ - ADC_CH_t CH2; /* ADC Channel 2 */ - ADC_CH_t CH3; /* ADC Channel 3 */ -} ADC_t; - -/* Positive input multiplexer selection */ -typedef enum ADC_CH_MUXPOS_enum -{ - ADC_CH_MUXPOS_PIN0_gc = (0x00<<3), /* Input pin 0 */ - ADC_CH_MUXPOS_PIN1_gc = (0x01<<3), /* Input pin 1 */ - ADC_CH_MUXPOS_PIN2_gc = (0x02<<3), /* Input pin 2 */ - ADC_CH_MUXPOS_PIN3_gc = (0x03<<3), /* Input pin 3 */ - ADC_CH_MUXPOS_PIN4_gc = (0x04<<3), /* Input pin 4 */ - ADC_CH_MUXPOS_PIN5_gc = (0x05<<3), /* Input pin 5 */ - ADC_CH_MUXPOS_PIN6_gc = (0x06<<3), /* Input pin 6 */ - ADC_CH_MUXPOS_PIN7_gc = (0x07<<3), /* Input pin 7 */ - ADC_CH_MUXPOS_PIN8_gc = (0x08<<3), /* Input pin 8 */ - ADC_CH_MUXPOS_PIN9_gc = (0x09<<3), /* Input pin 9 */ - ADC_CH_MUXPOS_PIN10_gc = (0x0A<<3), /* Input pin 10 */ - ADC_CH_MUXPOS_PIN11_gc = (0x0B<<3), /* Input pin 11 */ - ADC_CH_MUXPOS_PIN12_gc = (0x0C<<3), /* Input pin 12 */ - ADC_CH_MUXPOS_PIN13_gc = (0x0D<<3), /* Input pin 13 */ - ADC_CH_MUXPOS_PIN14_gc = (0x0E<<3), /* Input pin 14 */ - ADC_CH_MUXPOS_PIN15_gc = (0x0F<<3), /* Input pin 15 */ -} ADC_CH_MUXPOS_t; - -/* Internal input multiplexer selections */ -typedef enum ADC_CH_MUXINT_enum -{ - ADC_CH_MUXINT_TEMP_gc = (0x00<<3), /* Temperature Reference */ - ADC_CH_MUXINT_BANDGAP_gc = (0x01<<3), /* Bandgap Reference */ - ADC_CH_MUXINT_SCALEDVCC_gc = (0x02<<3), /* 1/10 scaled VCC */ - ADC_CH_MUXINT_DAC_gc = (0x03<<3), /* DAC output */ -} ADC_CH_MUXINT_t; - -/* Negative input multiplexer selection */ -typedef enum ADC_CH_MUXNEG_enum -{ - ADC_CH_MUXNEG_PIN0_gc = (0x00<<0), /* Input pin 0 (Input Mode = 2) */ - ADC_CH_MUXNEG_PIN1_gc = (0x01<<0), /* Input pin 1 (Input Mode = 2) */ - ADC_CH_MUXNEG_PIN2_gc = (0x02<<0), /* Input pin 2 (Input Mode = 2) */ - ADC_CH_MUXNEG_PIN3_gc = (0x03<<0), /* Input pin 3 (Input Mode = 2) */ - ADC_CH_MUXNEG_PIN4_gc = (0x00<<0), /* Input pin 4 (Input Mode = 3) */ - ADC_CH_MUXNEG_PIN5_gc = (0x01<<0), /* Input pin 5 (Input Mode = 3) */ - ADC_CH_MUXNEG_PIN6_gc = (0x02<<0), /* Input pin 6 (Input Mode = 3) */ - ADC_CH_MUXNEG_PIN7_gc = (0x03<<0), /* Input pin 7 (Input Mode = 3) */ - ADC_CH_MUXNEG_GND_MODE3_gc = (0x05<<0), /* PAD Ground (Input Mode = 2) */ - ADC_CH_MUXNEG_INTGND_MODE3_gc = (0x07<<0), /* Internal Ground (Input Mode = 2) */ - ADC_CH_MUXNEG_INTGND_MODE4_gc = (0x04<<0), /* Internal Ground (Input Mode = 3) */ - ADC_CH_MUXNEG_GND_MODE4_gc = (0x07<<0), /* PAD Ground (Input Mode = 3) */ -} ADC_CH_MUXNEG_t; - -/* Input mode */ -typedef enum ADC_CH_INPUTMODE_enum -{ - ADC_CH_INPUTMODE_INTERNAL_gc = (0x00<<0), /* Internal inputs, no gain */ - ADC_CH_INPUTMODE_SINGLEENDED_gc = (0x01<<0), /* Single-ended input, no gain */ - ADC_CH_INPUTMODE_DIFF_gc = (0x02<<0), /* Differential input, no gain */ - ADC_CH_INPUTMODE_DIFFWGAIN_gc = (0x03<<0), /* Differential input, with gain */ -} ADC_CH_INPUTMODE_t; - -/* Gain factor */ -typedef enum ADC_CH_GAIN_enum -{ - ADC_CH_GAIN_1X_gc = (0x00<<2), /* 1x gain */ - ADC_CH_GAIN_2X_gc = (0x01<<2), /* 2x gain */ - ADC_CH_GAIN_4X_gc = (0x02<<2), /* 4x gain */ - ADC_CH_GAIN_8X_gc = (0x03<<2), /* 8x gain */ - ADC_CH_GAIN_16X_gc = (0x04<<2), /* 16x gain */ - ADC_CH_GAIN_32X_gc = (0x05<<2), /* 32x gain */ - ADC_CH_GAIN_64X_gc = (0x06<<2), /* 64x gain */ - ADC_CH_GAIN_DIV2_gc = (0x07<<2), /* x/2 gain */ -} ADC_CH_GAIN_t; - -/* Conversion result resolution */ -typedef enum ADC_RESOLUTION_enum -{ - ADC_RESOLUTION_12BIT_gc = (0x00<<1), /* 12-bit right-adjusted result */ - ADC_RESOLUTION_8BIT_gc = (0x02<<1), /* 8-bit right-adjusted result */ - ADC_RESOLUTION_LEFT12BIT_gc = (0x03<<1), /* 12-bit left-adjusted result */ -} ADC_RESOLUTION_t; - -/* Current Limitation Mode */ -typedef enum ADC_CURRLIMIT_enum -{ - ADC_CURRLIMIT_NO_gc = (0x00<<5), /* No limit */ - ADC_CURRLIMIT_LOW_gc = (0x01<<5), /* Low current limit, max. sampling rate 1.5MSPS */ - ADC_CURRLIMIT_MED_gc = (0x02<<5), /* Medium current limit, max. sampling rate 1MSPS */ - ADC_CURRLIMIT_HIGH_gc = (0x03<<5), /* High current limit, max. sampling rate 0.5MSPS */ -} ADC_CURRLIMIT_t; - -/* Voltage reference selection */ -typedef enum ADC_REFSEL_enum -{ - ADC_REFSEL_INT1V_gc = (0x00<<4), /* Internal 1V */ - ADC_REFSEL_INTVCC_gc = (0x01<<4), /* Internal VCC / 1.6 */ - ADC_REFSEL_AREFA_gc = (0x02<<4), /* External reference on PORT A */ - ADC_REFSEL_AREFB_gc = (0x03<<4), /* External reference on PORT B */ - ADC_REFSEL_INTVCC2_gc = (0x04<<4), /* Internal VCC / 2 */ -} ADC_REFSEL_t; - -/* Channel sweep selection */ -typedef enum ADC_SWEEP_enum -{ - ADC_SWEEP_0_gc = (0x00<<6), /* ADC Channel 0 */ - ADC_SWEEP_01_gc = (0x01<<6), /* ADC Channel 0,1 */ - ADC_SWEEP_012_gc = (0x02<<6), /* ADC Channel 0,1,2 */ - ADC_SWEEP_0123_gc = (0x03<<6), /* ADC Channel 0,1,2,3 */ -} ADC_SWEEP_t; - -/* Event channel input selection */ -typedef enum ADC_EVSEL_enum -{ - ADC_EVSEL_0123_gc = (0x00<<3), /* Event Channel 0,1,2,3 */ - ADC_EVSEL_1234_gc = (0x01<<3), /* Event Channel 1,2,3,4 */ - ADC_EVSEL_2345_gc = (0x02<<3), /* Event Channel 2,3,4,5 */ - ADC_EVSEL_3456_gc = (0x03<<3), /* Event Channel 3,4,5,6 */ - ADC_EVSEL_4567_gc = (0x04<<3), /* Event Channel 4,5,6,7 */ - ADC_EVSEL_567_gc = (0x05<<3), /* Event Channel 5,6,7 */ - ADC_EVSEL_67_gc = (0x06<<3), /* Event Channel 6,7 */ - ADC_EVSEL_7_gc = (0x07<<3), /* Event Channel 7 */ -} ADC_EVSEL_t; - -/* Event action selection */ -typedef enum ADC_EVACT_enum -{ - ADC_EVACT_NONE_gc = (0x00<<0), /* No event action */ - ADC_EVACT_CH0_gc = (0x01<<0), /* First event triggers channel 0 */ - ADC_EVACT_CH01_gc = (0x02<<0), /* First two events trigger channel 0,1 */ - ADC_EVACT_CH012_gc = (0x03<<0), /* First three events trigger channel 0,1,2 */ - ADC_EVACT_CH0123_gc = (0x04<<0), /* Events trigger channel 0,1,2,3 */ - ADC_EVACT_SWEEP_gc = (0x05<<0), /* First event triggers sweep */ - ADC_EVACT_SYNCSWEEP_gc = (0x06<<0), /* The ADC is flushed and restarted for accurate timing */ -} ADC_EVACT_t; - -/* Interupt mode */ -typedef enum ADC_CH_INTMODE_enum -{ - ADC_CH_INTMODE_COMPLETE_gc = (0x00<<2), /* Interrupt on conversion complete */ - ADC_CH_INTMODE_BELOW_gc = (0x01<<2), /* Interrupt on result below compare value */ - ADC_CH_INTMODE_ABOVE_gc = (0x03<<2), /* Interrupt on result above compare value */ -} ADC_CH_INTMODE_t; - -/* Interrupt level */ -typedef enum ADC_CH_INTLVL_enum -{ - ADC_CH_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ - ADC_CH_INTLVL_LO_gc = (0x01<<0), /* Low level */ - ADC_CH_INTLVL_MED_gc = (0x02<<0), /* Medium level */ - ADC_CH_INTLVL_HI_gc = (0x03<<0), /* High level */ -} ADC_CH_INTLVL_t; - -/* DMA request selection */ -typedef enum ADC_DMASEL_enum -{ - ADC_DMASEL_OFF_gc = (0x00<<6), /* Combined DMA request OFF */ - ADC_DMASEL_CH01_gc = (0x01<<6), /* ADC Channel 0 or 1 */ - ADC_DMASEL_CH012_gc = (0x02<<6), /* ADC Channel 0 or 1 or 2 */ - ADC_DMASEL_CH0123_gc = (0x03<<6), /* ADC Channel 0 or 1 or 2 or 3 */ -} ADC_DMASEL_t; - -/* Clock prescaler */ -typedef enum ADC_PRESCALER_enum -{ - ADC_PRESCALER_DIV4_gc = (0x00<<0), /* Divide clock by 4 */ - ADC_PRESCALER_DIV8_gc = (0x01<<0), /* Divide clock by 8 */ - ADC_PRESCALER_DIV16_gc = (0x02<<0), /* Divide clock by 16 */ - ADC_PRESCALER_DIV32_gc = (0x03<<0), /* Divide clock by 32 */ - ADC_PRESCALER_DIV64_gc = (0x04<<0), /* Divide clock by 64 */ - ADC_PRESCALER_DIV128_gc = (0x05<<0), /* Divide clock by 128 */ - ADC_PRESCALER_DIV256_gc = (0x06<<0), /* Divide clock by 256 */ - ADC_PRESCALER_DIV512_gc = (0x07<<0), /* Divide clock by 512 */ -} ADC_PRESCALER_t; - - -/* --------------------------------------------------------------------------- -DAC - Digital/Analog Converter --------------------------------------------------------------------------- -*/ - -/* Digital-to-Analog Converter */ -typedef struct DAC_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t CTRLC; /* Control Register C */ - register8_t EVCTRL; /* Event Input Control */ - register8_t reserved_0x04; - register8_t STATUS; /* Status */ - register8_t reserved_0x06; - register8_t reserved_0x07; - register8_t CH0GAINCAL; /* Gain Calibration */ - register8_t CH0OFFSETCAL; /* Offset Calibration */ - register8_t CH1GAINCAL; /* Gain Calibration */ - register8_t CH1OFFSETCAL; /* Offset Calibration */ - register8_t reserved_0x0C; - register8_t reserved_0x0D; - register8_t reserved_0x0E; - register8_t reserved_0x0F; - register8_t reserved_0x10; - register8_t reserved_0x11; - register8_t reserved_0x12; - register8_t reserved_0x13; - register8_t reserved_0x14; - register8_t reserved_0x15; - register8_t reserved_0x16; - register8_t reserved_0x17; - _WORDREGISTER(CH0DATA); /* Channel 0 Data */ - _WORDREGISTER(CH1DATA); /* Channel 1 Data */ -} DAC_t; - -/* Output channel selection */ -typedef enum DAC_CHSEL_enum -{ - DAC_CHSEL_SINGLE_gc = (0x00<<5), /* Single channel operation (Channel 0 only) */ - DAC_CHSEL_SINGLE1_gc = (0x01<<5), /* Single channel operation (Channel 1 only) */ - DAC_CHSEL_DUAL_gc = (0x02<<5), /* Dual channel operation (Channel 0 and channel 1) */ -} DAC_CHSEL_t; - -/* Reference voltage selection */ -typedef enum DAC_REFSEL_enum -{ - DAC_REFSEL_INT1V_gc = (0x00<<3), /* Internal 1V */ - DAC_REFSEL_AVCC_gc = (0x01<<3), /* Analog supply voltage */ - DAC_REFSEL_AREFA_gc = (0x02<<3), /* External reference on AREF on PORTA */ - DAC_REFSEL_AREFB_gc = (0x03<<3), /* External reference on AREF on PORTB */ -} DAC_REFSEL_t; - -/* Event channel selection */ -typedef enum DAC_EVSEL_enum -{ - DAC_EVSEL_0_gc = (0x00<<0), /* Event Channel 0 */ - DAC_EVSEL_1_gc = (0x01<<0), /* Event Channel 1 */ - DAC_EVSEL_2_gc = (0x02<<0), /* Event Channel 2 */ - DAC_EVSEL_3_gc = (0x03<<0), /* Event Channel 3 */ - DAC_EVSEL_4_gc = (0x04<<0), /* Event Channel 4 */ - DAC_EVSEL_5_gc = (0x05<<0), /* Event Channel 5 */ - DAC_EVSEL_6_gc = (0x06<<0), /* Event Channel 6 */ - DAC_EVSEL_7_gc = (0x07<<0), /* Event Channel 7 */ -} DAC_EVSEL_t; - - -/* --------------------------------------------------------------------------- -AC - Analog Comparator --------------------------------------------------------------------------- -*/ - -/* Analog Comparator */ -typedef struct AC_struct -{ - register8_t AC0CTRL; /* Analog Comparator 0 Control */ - register8_t AC1CTRL; /* Analog Comparator 1 Control */ - register8_t AC0MUXCTRL; /* Analog Comparator 0 MUX Control */ - register8_t AC1MUXCTRL; /* Analog Comparator 1 MUX Control */ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t WINCTRL; /* Window Mode Control */ - register8_t STATUS; /* Status */ -} AC_t; - -/* Interrupt mode */ -typedef enum AC_INTMODE_enum -{ - AC_INTMODE_BOTHEDGES_gc = (0x00<<6), /* Interrupt on both edges */ - AC_INTMODE_FALLING_gc = (0x02<<6), /* Interrupt on falling edge */ - AC_INTMODE_RISING_gc = (0x03<<6), /* Interrupt on rising edge */ -} AC_INTMODE_t; - -/* Interrupt level */ -typedef enum AC_INTLVL_enum -{ - AC_INTLVL_OFF_gc = (0x00<<4), /* Interrupt disabled */ - AC_INTLVL_LO_gc = (0x01<<4), /* Low level */ - AC_INTLVL_MED_gc = (0x02<<4), /* Medium level */ - AC_INTLVL_HI_gc = (0x03<<4), /* High level */ -} AC_INTLVL_t; - -/* Hysteresis mode selection */ -typedef enum AC_HYSMODE_enum -{ - AC_HYSMODE_NO_gc = (0x00<<1), /* No hysteresis */ - AC_HYSMODE_SMALL_gc = (0x01<<1), /* Small hysteresis */ - AC_HYSMODE_LARGE_gc = (0x02<<1), /* Large hysteresis */ -} AC_HYSMODE_t; - -/* Positive input multiplexer selection */ -typedef enum AC_MUXPOS_enum -{ - AC_MUXPOS_PIN0_gc = (0x00<<3), /* Pin 0 */ - AC_MUXPOS_PIN1_gc = (0x01<<3), /* Pin 1 */ - AC_MUXPOS_PIN2_gc = (0x02<<3), /* Pin 2 */ - AC_MUXPOS_PIN3_gc = (0x03<<3), /* Pin 3 */ - AC_MUXPOS_PIN4_gc = (0x04<<3), /* Pin 4 */ - AC_MUXPOS_PIN5_gc = (0x05<<3), /* Pin 5 */ - AC_MUXPOS_PIN6_gc = (0x06<<3), /* Pin 6 */ - AC_MUXPOS_DAC_gc = (0x07<<3), /* DAC output */ -} AC_MUXPOS_t; - -/* Negative input multiplexer selection */ -typedef enum AC_MUXNEG_enum -{ - AC_MUXNEG_PIN0_gc = (0x00<<0), /* Pin 0 */ - AC_MUXNEG_PIN1_gc = (0x01<<0), /* Pin 1 */ - AC_MUXNEG_PIN3_gc = (0x02<<0), /* Pin 3 */ - AC_MUXNEG_PIN5_gc = (0x03<<0), /* Pin 5 */ - AC_MUXNEG_PIN7_gc = (0x04<<0), /* Pin 7 */ - AC_MUXNEG_DAC_gc = (0x05<<0), /* DAC output */ - AC_MUXNEG_BANDGAP_gc = (0x06<<0), /* Bandgap Reference */ - AC_MUXNEG_SCALER_gc = (0x07<<0), /* Internal voltage scaler */ -} AC_MUXNEG_t; - -/* Windows interrupt mode */ -typedef enum AC_WINTMODE_enum -{ - AC_WINTMODE_ABOVE_gc = (0x00<<2), /* Interrupt on above window */ - AC_WINTMODE_INSIDE_gc = (0x01<<2), /* Interrupt on inside window */ - AC_WINTMODE_BELOW_gc = (0x02<<2), /* Interrupt on below window */ - AC_WINTMODE_OUTSIDE_gc = (0x03<<2), /* Interrupt on outside window */ -} AC_WINTMODE_t; - -/* Window interrupt level */ -typedef enum AC_WINTLVL_enum -{ - AC_WINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ - AC_WINTLVL_LO_gc = (0x01<<0), /* Low priority */ - AC_WINTLVL_MED_gc = (0x02<<0), /* Medium priority */ - AC_WINTLVL_HI_gc = (0x03<<0), /* High priority */ -} AC_WINTLVL_t; - -/* Window mode state */ -typedef enum AC_WSTATE_enum -{ - AC_WSTATE_ABOVE_gc = (0x00<<6), /* Signal above window */ - AC_WSTATE_INSIDE_gc = (0x01<<6), /* Signal inside window */ - AC_WSTATE_BELOW_gc = (0x02<<6), /* Signal below window */ -} AC_WSTATE_t; - - -/* --------------------------------------------------------------------------- -RTC32 - 32-bit Real-Time Counter --------------------------------------------------------------------------- -*/ - -/* 32-bit Real-Time Counter */ -typedef struct RTC32_struct -{ - register8_t CTRL; /* Control Register */ - register8_t SYNCCTRL; /* Synchronization Control/Status Register */ - register8_t INTCTRL; /* Interrupt Control Register */ - register8_t INTFLAGS; /* Interrupt Flags */ - _DWORDREGISTER(CNT); /* Count Register */ - _DWORDREGISTER(PER); /* Period Register */ - _DWORDREGISTER(COMP); /* Compare Register */ -} RTC32_t; - -/* Compare Interrupt level */ -typedef enum RTC32_COMPINTLVL_enum -{ - RTC32_COMPINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ - RTC32_COMPINTLVL_LO_gc = (0x01<<2), /* Low Level */ - RTC32_COMPINTLVL_MED_gc = (0x02<<2), /* Medium Level */ - RTC32_COMPINTLVL_HI_gc = (0x03<<2), /* High Level */ -} RTC32_COMPINTLVL_t; - -/* Overflow Interrupt level */ -typedef enum RTC32_OVFINTLVL_enum -{ - RTC32_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - RTC32_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ - RTC32_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ - RTC32_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ -} RTC32_OVFINTLVL_t; - - -/* --------------------------------------------------------------------------- -TWI - Two-Wire Interface --------------------------------------------------------------------------- -*/ - -/* */ -typedef struct TWI_MASTER_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t CTRLC; /* Control Register C */ - register8_t STATUS; /* Status Register */ - register8_t BAUD; /* Baurd Rate Control Register */ - register8_t ADDR; /* Address Register */ - register8_t DATA; /* Data Register */ -} TWI_MASTER_t; - - -/* */ -typedef struct TWI_SLAVE_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t STATUS; /* Status Register */ - register8_t ADDR; /* Address Register */ - register8_t DATA; /* Data Register */ - register8_t ADDRMASK; /* Address Mask Register */ -} TWI_SLAVE_t; - - -/* Two-Wire Interface */ -typedef struct TWI_struct -{ - register8_t CTRL; /* TWI Common Control Register */ - TWI_MASTER_t MASTER; /* TWI master module */ - TWI_SLAVE_t SLAVE; /* TWI slave module */ -} TWI_t; - -/* SDA Hold Time */ -typedef enum TWI_SDAHOLD_enum -{ - TWI_SDAHOLD_OFF_gc = (0x00<<1), /* SDA Hold Time off */ - TWI_SDAHOLD_50NS_gc = (0x01<<1), /* SDA Hold Time 50 ns */ - TWI_SDAHOLD_300NS_gc = (0x02<<1), /* SDA Hold Time 300 ns */ - TWI_SDAHOLD_400NS_gc = (0x03<<1), /* SDA Hold Time 400 ns */ -} TWI_SDAHOLD_t; - -/* Master Interrupt Level */ -typedef enum TWI_MASTER_INTLVL_enum -{ - TWI_MASTER_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ - TWI_MASTER_INTLVL_LO_gc = (0x01<<6), /* Low Level */ - TWI_MASTER_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ - TWI_MASTER_INTLVL_HI_gc = (0x03<<6), /* High Level */ -} TWI_MASTER_INTLVL_t; - -/* Inactive Timeout */ -typedef enum TWI_MASTER_TIMEOUT_enum -{ - TWI_MASTER_TIMEOUT_DISABLED_gc = (0x00<<2), /* Bus Timeout Disabled */ - TWI_MASTER_TIMEOUT_50US_gc = (0x01<<2), /* 50 Microseconds */ - TWI_MASTER_TIMEOUT_100US_gc = (0x02<<2), /* 100 Microseconds */ - TWI_MASTER_TIMEOUT_200US_gc = (0x03<<2), /* 200 Microseconds */ -} TWI_MASTER_TIMEOUT_t; - -/* Master Command */ -typedef enum TWI_MASTER_CMD_enum -{ - TWI_MASTER_CMD_NOACT_gc = (0x00<<0), /* No Action */ - TWI_MASTER_CMD_REPSTART_gc = (0x01<<0), /* Issue Repeated Start Condition */ - TWI_MASTER_CMD_RECVTRANS_gc = (0x02<<0), /* Receive or Transmit Data */ - TWI_MASTER_CMD_STOP_gc = (0x03<<0), /* Issue Stop Condition */ -} TWI_MASTER_CMD_t; - -/* Master Bus State */ -typedef enum TWI_MASTER_BUSSTATE_enum -{ - TWI_MASTER_BUSSTATE_UNKNOWN_gc = (0x00<<0), /* Unknown Bus State */ - TWI_MASTER_BUSSTATE_IDLE_gc = (0x01<<0), /* Bus is Idle */ - TWI_MASTER_BUSSTATE_OWNER_gc = (0x02<<0), /* This Module Controls The Bus */ - TWI_MASTER_BUSSTATE_BUSY_gc = (0x03<<0), /* The Bus is Busy */ -} TWI_MASTER_BUSSTATE_t; - -/* Slave Interrupt Level */ -typedef enum TWI_SLAVE_INTLVL_enum -{ - TWI_SLAVE_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ - TWI_SLAVE_INTLVL_LO_gc = (0x01<<6), /* Low Level */ - TWI_SLAVE_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ - TWI_SLAVE_INTLVL_HI_gc = (0x03<<6), /* High Level */ -} TWI_SLAVE_INTLVL_t; - -/* Slave Command */ -typedef enum TWI_SLAVE_CMD_enum -{ - TWI_SLAVE_CMD_NOACT_gc = (0x00<<0), /* No Action */ - TWI_SLAVE_CMD_COMPTRANS_gc = (0x02<<0), /* Used To Complete a Transaction */ - TWI_SLAVE_CMD_RESPONSE_gc = (0x03<<0), /* Used in Response to Address/Data Interrupt */ -} TWI_SLAVE_CMD_t; - - -/* --------------------------------------------------------------------------- -USB - USB --------------------------------------------------------------------------- -*/ - -/* USB Endpoint */ -typedef struct USB_EP_struct -{ - register8_t STATUS; /* Endpoint Status */ - register8_t CTRL; /* Endpoint Control */ - _WORDREGISTER(CNT); /* USB Endpoint Counter */ - _WORDREGISTER(DATAPTR); /* Data Pointer */ - _WORDREGISTER(AUXDATA); /* Auxiliary Data */ -} USB_EP_t; - - -/* Universal Serial Bus */ -typedef struct USB_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t STATUS; /* Status Register */ - register8_t ADDR; /* Address Register */ - register8_t FIFOWP; /* FIFO Write Pointer Register */ - register8_t FIFORP; /* FIFO Read Pointer Register */ - _WORDREGISTER(EPPTR); /* Endpoint Configuration Table Pointer */ - register8_t INTCTRLA; /* Interrupt Control Register A */ - register8_t INTCTRLB; /* Interrupt Control Register B */ - register8_t INTFLAGSACLR; /* Clear Interrupt Flag Register A */ - register8_t INTFLAGSASET; /* Set Interrupt Flag Register A */ - register8_t INTFLAGSBCLR; /* Clear Interrupt Flag Register B */ - register8_t INTFLAGSBSET; /* Set Interrupt Flag Register B */ - register8_t reserved_0x0E; - register8_t reserved_0x0F; - register8_t reserved_0x10; - register8_t reserved_0x11; - register8_t reserved_0x12; - register8_t reserved_0x13; - register8_t reserved_0x14; - register8_t reserved_0x15; - register8_t reserved_0x16; - register8_t reserved_0x17; - register8_t reserved_0x18; - register8_t reserved_0x19; - register8_t reserved_0x1A; - register8_t reserved_0x1B; - register8_t reserved_0x1C; - register8_t reserved_0x1D; - register8_t reserved_0x1E; - register8_t reserved_0x1F; - register8_t reserved_0x20; - register8_t reserved_0x21; - register8_t reserved_0x22; - register8_t reserved_0x23; - register8_t reserved_0x24; - register8_t reserved_0x25; - register8_t reserved_0x26; - register8_t reserved_0x27; - register8_t reserved_0x28; - register8_t reserved_0x29; - register8_t reserved_0x2A; - register8_t reserved_0x2B; - register8_t reserved_0x2C; - register8_t reserved_0x2D; - register8_t reserved_0x2E; - register8_t reserved_0x2F; - register8_t reserved_0x30; - register8_t reserved_0x31; - register8_t reserved_0x32; - register8_t reserved_0x33; - register8_t reserved_0x34; - register8_t reserved_0x35; - register8_t reserved_0x36; - register8_t reserved_0x37; - register8_t reserved_0x38; - register8_t reserved_0x39; - register8_t CAL0; /* Calibration Byte 0 */ - register8_t CAL1; /* Calibration Byte 1 */ -} USB_t; - - -/* USB Endpoint Table */ -typedef struct USB_EP_TABLE_struct -{ - USB_EP_t EP0OUT; /* Endpoint 0 */ - USB_EP_t EP0IN; /* Endpoint 0 */ - USB_EP_t EP1OUT; /* Endpoint 1 */ - USB_EP_t EP1IN; /* Endpoint 1 */ - USB_EP_t EP2OUT; /* Endpoint 2 */ - USB_EP_t EP2IN; /* Endpoint 2 */ - USB_EP_t EP3OUT; /* Endpoint 3 */ - USB_EP_t EP3IN; /* Endpoint 3 */ - USB_EP_t EP4OUT; /* Endpoint 4 */ - USB_EP_t EP4IN; /* Endpoint 4 */ - USB_EP_t EP5OUT; /* Endpoint 5 */ - USB_EP_t EP5IN; /* Endpoint 5 */ - USB_EP_t EP6OUT; /* Endpoint 6 */ - USB_EP_t EP6IN; /* Endpoint 6 */ - USB_EP_t EP7OUT; /* Endpoint 7 */ - USB_EP_t EP7IN; /* Endpoint 7 */ - USB_EP_t EP8OUT; /* Endpoint 8 */ - USB_EP_t EP8IN; /* Endpoint 8 */ - USB_EP_t EP9OUT; /* Endpoint 9 */ - USB_EP_t EP9IN; /* Endpoint 9 */ - USB_EP_t EP10OUT; /* Endpoint 10 */ - USB_EP_t EP10IN; /* Endpoint 10 */ - USB_EP_t EP11OUT; /* Endpoint 11 */ - USB_EP_t EP11IN; /* Endpoint 11 */ - USB_EP_t EP12OUT; /* Endpoint 12 */ - USB_EP_t EP12IN; /* Endpoint 12 */ - USB_EP_t EP13OUT; /* Endpoint 13 */ - USB_EP_t EP13IN; /* Endpoint 13 */ - USB_EP_t EP14OUT; /* Endpoint 14 */ - USB_EP_t EP14IN; /* Endpoint 14 */ - USB_EP_t EP15OUT; /* Endpoint 15 */ - USB_EP_t EP15IN; /* Endpoint 15 */ - register8_t reserved_0x100; - register8_t reserved_0x101; - register8_t reserved_0x102; - register8_t reserved_0x103; - register8_t reserved_0x104; - register8_t reserved_0x105; - register8_t reserved_0x106; - register8_t reserved_0x107; - register8_t reserved_0x108; - register8_t reserved_0x109; - register8_t reserved_0x10A; - register8_t reserved_0x10B; - register8_t reserved_0x10C; - register8_t reserved_0x10D; - register8_t reserved_0x10E; - register8_t reserved_0x10F; - register8_t FRAMENUML; /* Frame Number Low Byte */ - register8_t FRAMENUMH; /* Frame Number High Byte */ -} USB_EP_TABLE_t; - -/* Interrupt level */ -typedef enum USB_INTLVL_enum -{ - USB_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ - USB_INTLVL_LO_gc = (0x01<<0), /* Low level */ - USB_INTLVL_MED_gc = (0x02<<0), /* Medium level */ - USB_INTLVL_HI_gc = (0x03<<0), /* High level */ -} USB_INTLVL_t; - -/* USB Endpoint Type */ -typedef enum USB_EP_TYPE_enum -{ - USB_EP_TYPE_DISABLE_gc = (0x00<<6), /* Endpoint Disabled */ - USB_EP_TYPE_CONTROL_gc = (0x01<<6), /* Control */ - USB_EP_TYPE_BULK_gc = (0x02<<6), /* Bulk/Interrupt */ - USB_EP_TYPE_ISOCHRONOUS_gc = (0x03<<6), /* Isochronous */ -} USB_EP_TYPE_t; - -/* USB Endpoint Buffersize */ -typedef enum USB_EP_BUFSIZE_enum -{ - USB_EP_BUFSIZE_8_gc = (0x00<<0), /* 8 bytes buffer size */ - USB_EP_BUFSIZE_16_gc = (0x01<<0), /* 16 bytes buffer size */ - USB_EP_BUFSIZE_32_gc = (0x02<<0), /* 32 bytes buffer size */ - USB_EP_BUFSIZE_64_gc = (0x03<<0), /* 64 bytes buffer size */ - USB_EP_BUFSIZE_128_gc = (0x04<<0), /* 128 bytes buffer size */ - USB_EP_BUFSIZE_256_gc = (0x05<<0), /* 256 bytes buffer size */ - USB_EP_BUFSIZE_512_gc = (0x06<<0), /* 512 bytes buffer size */ - USB_EP_BUFSIZE_1023_gc = (0x07<<0), /* 1023 bytes buffer size */ -} USB_EP_BUFSIZE_t; - - -/* --------------------------------------------------------------------------- -PORT - I/O Port Configuration --------------------------------------------------------------------------- -*/ - -/* I/O Ports */ -typedef struct PORT_struct -{ - register8_t DIR; /* I/O Port Data Direction */ - register8_t DIRSET; /* I/O Port Data Direction Set */ - register8_t DIRCLR; /* I/O Port Data Direction Clear */ - register8_t DIRTGL; /* I/O Port Data Direction Toggle */ - register8_t OUT; /* I/O Port Output */ - register8_t OUTSET; /* I/O Port Output Set */ - register8_t OUTCLR; /* I/O Port Output Clear */ - register8_t OUTTGL; /* I/O Port Output Toggle */ - register8_t IN; /* I/O port Input */ - register8_t INTCTRL; /* Interrupt Control Register */ - register8_t INT0MASK; /* Port Interrupt 0 Mask */ - register8_t INT1MASK; /* Port Interrupt 1 Mask */ - register8_t INTFLAGS; /* Interrupt Flag Register */ - register8_t reserved_0x0D; - register8_t REMAP; /* I/O Port Pin Remap Register */ - register8_t reserved_0x0F; - register8_t PIN0CTRL; /* Pin 0 Control Register */ - register8_t PIN1CTRL; /* Pin 1 Control Register */ - register8_t PIN2CTRL; /* Pin 2 Control Register */ - register8_t PIN3CTRL; /* Pin 3 Control Register */ - register8_t PIN4CTRL; /* Pin 4 Control Register */ - register8_t PIN5CTRL; /* Pin 5 Control Register */ - register8_t PIN6CTRL; /* Pin 6 Control Register */ - register8_t PIN7CTRL; /* Pin 7 Control Register */ -} PORT_t; - -/* Port Interrupt 0 Level */ -typedef enum PORT_INT0LVL_enum -{ - PORT_INT0LVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - PORT_INT0LVL_LO_gc = (0x01<<0), /* Low Level */ - PORT_INT0LVL_MED_gc = (0x02<<0), /* Medium Level */ - PORT_INT0LVL_HI_gc = (0x03<<0), /* High Level */ -} PORT_INT0LVL_t; - -/* Port Interrupt 1 Level */ -typedef enum PORT_INT1LVL_enum -{ - PORT_INT1LVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ - PORT_INT1LVL_LO_gc = (0x01<<2), /* Low Level */ - PORT_INT1LVL_MED_gc = (0x02<<2), /* Medium Level */ - PORT_INT1LVL_HI_gc = (0x03<<2), /* High Level */ -} PORT_INT1LVL_t; - -/* Output/Pull Configuration */ -typedef enum PORT_OPC_enum -{ - PORT_OPC_TOTEM_gc = (0x00<<3), /* Totempole */ - PORT_OPC_BUSKEEPER_gc = (0x01<<3), /* Totempole w/ Bus keeper on Input and Output */ - PORT_OPC_PULLDOWN_gc = (0x02<<3), /* Totempole w/ Pull-down on Input */ - PORT_OPC_PULLUP_gc = (0x03<<3), /* Totempole w/ Pull-up on Input */ - PORT_OPC_WIREDOR_gc = (0x04<<3), /* Wired OR */ - PORT_OPC_WIREDAND_gc = (0x05<<3), /* Wired AND */ - PORT_OPC_WIREDORPULL_gc = (0x06<<3), /* Wired OR w/ Pull-down */ - PORT_OPC_WIREDANDPULL_gc = (0x07<<3), /* Wired AND w/ Pull-up */ -} PORT_OPC_t; - -/* Input/Sense Configuration */ -typedef enum PORT_ISC_enum -{ - PORT_ISC_BOTHEDGES_gc = (0x00<<0), /* Sense Both Edges */ - PORT_ISC_RISING_gc = (0x01<<0), /* Sense Rising Edge */ - PORT_ISC_FALLING_gc = (0x02<<0), /* Sense Falling Edge */ - PORT_ISC_LEVEL_gc = (0x03<<0), /* Sense Level (Transparent For Events) */ - PORT_ISC_INPUT_DISABLE_gc = (0x07<<0), /* Disable Digital Input Buffer */ -} PORT_ISC_t; - - -/* --------------------------------------------------------------------------- -TC - 16-bit Timer/Counter With PWM --------------------------------------------------------------------------- -*/ - -/* 16-bit Timer/Counter 0 */ -typedef struct TC0_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t CTRLC; /* Control register C */ - register8_t CTRLD; /* Control Register D */ - register8_t CTRLE; /* Control Register E */ - register8_t reserved_0x05; - register8_t INTCTRLA; /* Interrupt Control Register A */ - register8_t INTCTRLB; /* Interrupt Control Register B */ - register8_t CTRLFCLR; /* Control Register F Clear */ - register8_t CTRLFSET; /* Control Register F Set */ - register8_t CTRLGCLR; /* Control Register G Clear */ - register8_t CTRLGSET; /* Control Register G Set */ - register8_t INTFLAGS; /* Interrupt Flag Register */ - register8_t reserved_0x0D; - register8_t reserved_0x0E; - register8_t TEMP; /* Temporary Register For 16-bit Access */ - register8_t reserved_0x10; - register8_t reserved_0x11; - register8_t reserved_0x12; - register8_t reserved_0x13; - register8_t reserved_0x14; - register8_t reserved_0x15; - register8_t reserved_0x16; - register8_t reserved_0x17; - register8_t reserved_0x18; - register8_t reserved_0x19; - register8_t reserved_0x1A; - register8_t reserved_0x1B; - register8_t reserved_0x1C; - register8_t reserved_0x1D; - register8_t reserved_0x1E; - register8_t reserved_0x1F; - _WORDREGISTER(CNT); /* Count */ - register8_t reserved_0x22; - register8_t reserved_0x23; - register8_t reserved_0x24; - register8_t reserved_0x25; - _WORDREGISTER(PER); /* Period */ - _WORDREGISTER(CCA); /* Compare or Capture A */ - _WORDREGISTER(CCB); /* Compare or Capture B */ - _WORDREGISTER(CCC); /* Compare or Capture C */ - _WORDREGISTER(CCD); /* Compare or Capture D */ - register8_t reserved_0x30; - register8_t reserved_0x31; - register8_t reserved_0x32; - register8_t reserved_0x33; - register8_t reserved_0x34; - register8_t reserved_0x35; - _WORDREGISTER(PERBUF); /* Period Buffer */ - _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ - _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ - _WORDREGISTER(CCCBUF); /* Compare Or Capture C Buffer */ - _WORDREGISTER(CCDBUF); /* Compare Or Capture D Buffer */ -} TC0_t; - - -/* 16-bit Timer/Counter 1 */ -typedef struct TC1_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t CTRLC; /* Control register C */ - register8_t CTRLD; /* Control Register D */ - register8_t CTRLE; /* Control Register E */ - register8_t reserved_0x05; - register8_t INTCTRLA; /* Interrupt Control Register A */ - register8_t INTCTRLB; /* Interrupt Control Register B */ - register8_t CTRLFCLR; /* Control Register F Clear */ - register8_t CTRLFSET; /* Control Register F Set */ - register8_t CTRLGCLR; /* Control Register G Clear */ - register8_t CTRLGSET; /* Control Register G Set */ - register8_t INTFLAGS; /* Interrupt Flag Register */ - register8_t reserved_0x0D; - register8_t reserved_0x0E; - register8_t TEMP; /* Temporary Register For 16-bit Access */ - register8_t reserved_0x10; - register8_t reserved_0x11; - register8_t reserved_0x12; - register8_t reserved_0x13; - register8_t reserved_0x14; - register8_t reserved_0x15; - register8_t reserved_0x16; - register8_t reserved_0x17; - register8_t reserved_0x18; - register8_t reserved_0x19; - register8_t reserved_0x1A; - register8_t reserved_0x1B; - register8_t reserved_0x1C; - register8_t reserved_0x1D; - register8_t reserved_0x1E; - register8_t reserved_0x1F; - _WORDREGISTER(CNT); /* Count */ - register8_t reserved_0x22; - register8_t reserved_0x23; - register8_t reserved_0x24; - register8_t reserved_0x25; - _WORDREGISTER(PER); /* Period */ - _WORDREGISTER(CCA); /* Compare or Capture A */ - _WORDREGISTER(CCB); /* Compare or Capture B */ - register8_t reserved_0x2C; - register8_t reserved_0x2D; - register8_t reserved_0x2E; - register8_t reserved_0x2F; - register8_t reserved_0x30; - register8_t reserved_0x31; - register8_t reserved_0x32; - register8_t reserved_0x33; - register8_t reserved_0x34; - register8_t reserved_0x35; - _WORDREGISTER(PERBUF); /* Period Buffer */ - _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ - _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ -} TC1_t; - -/* Clock Selection */ -typedef enum TC_CLKSEL_enum -{ - TC_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */ - TC_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */ - TC_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */ - TC_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */ - TC_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */ - TC_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */ - TC_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */ - TC_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */ - TC_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */ - TC_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */ - TC_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */ - TC_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */ - TC_CLKSEL_EVCH4_gc = (0x0C<<0), /* Event Channel 4 */ - TC_CLKSEL_EVCH5_gc = (0x0D<<0), /* Event Channel 5 */ - TC_CLKSEL_EVCH6_gc = (0x0E<<0), /* Event Channel 6 */ - TC_CLKSEL_EVCH7_gc = (0x0F<<0), /* Event Channel 7 */ -} TC_CLKSEL_t; - -/* Waveform Generation Mode */ -typedef enum TC_WGMODE_enum -{ - TC_WGMODE_NORMAL_gc = (0x00<<0), /* Normal Mode */ - TC_WGMODE_FRQ_gc = (0x01<<0), /* Frequency Generation Mode */ - TC_WGMODE_SINGLESLOPE_gc = (0x03<<0), /* Single Slope */ - TC_WGMODE_SS_gc = (0x03<<0), /* Single Slope */ - TC_WGMODE_DSTOP_gc = (0x05<<0), /* Dual Slope, Update on TOP */ - TC_WGMODE_DS_T_gc = (0x05<<0), /* Dual Slope, Update on TOP */ - TC_WGMODE_DSBOTH_gc = (0x06<<0), /* Dual Slope, Update on both TOP and BOTTOM */ - TC_WGMODE_DS_TB_gc = (0x06<<0), /* Dual Slope, Update on both TOP and BOTTOM */ - TC_WGMODE_DSBOTTOM_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */ - TC_WGMODE_DS_B_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */ -} TC_WGMODE_t; - -/* Byte Mode */ -typedef enum TC_BYTEM_enum -{ - TC_BYTEM_NORMAL_gc = (0x00<<0), /* 16-bit mode */ - TC_BYTEM_BYTEMODE_gc = (0x01<<0), /* Timer/Counter operating in byte mode only */ - TC_BYTEM_SPLITMODE_gc = (0x02<<0), /* Timer/Counter split into two 8-bit Counters (TC2) */ -} TC_BYTEM_t; - -/* Event Action */ -typedef enum TC_EVACT_enum -{ - TC_EVACT_OFF_gc = (0x00<<5), /* No Event Action */ - TC_EVACT_CAPT_gc = (0x01<<5), /* Input Capture */ - TC_EVACT_UPDOWN_gc = (0x02<<5), /* Externally Controlled Up/Down Count */ - TC_EVACT_QDEC_gc = (0x03<<5), /* Quadrature Decode */ - TC_EVACT_RESTART_gc = (0x04<<5), /* Restart */ - TC_EVACT_FRQ_gc = (0x05<<5), /* Frequency Capture */ - TC_EVACT_PW_gc = (0x06<<5), /* Pulse-width Capture */ -} TC_EVACT_t; - -/* Event Selection */ -typedef enum TC_EVSEL_enum -{ - TC_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ - TC_EVSEL_CH0_gc = (0x08<<0), /* Event Channel 0 */ - TC_EVSEL_CH1_gc = (0x09<<0), /* Event Channel 1 */ - TC_EVSEL_CH2_gc = (0x0A<<0), /* Event Channel 2 */ - TC_EVSEL_CH3_gc = (0x0B<<0), /* Event Channel 3 */ - TC_EVSEL_CH4_gc = (0x0C<<0), /* Event Channel 4 */ - TC_EVSEL_CH5_gc = (0x0D<<0), /* Event Channel 5 */ - TC_EVSEL_CH6_gc = (0x0E<<0), /* Event Channel 6 */ - TC_EVSEL_CH7_gc = (0x0F<<0), /* Event Channel 7 */ -} TC_EVSEL_t; - -/* Error Interrupt Level */ -typedef enum TC_ERRINTLVL_enum -{ - TC_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ - TC_ERRINTLVL_LO_gc = (0x01<<2), /* Low Level */ - TC_ERRINTLVL_MED_gc = (0x02<<2), /* Medium Level */ - TC_ERRINTLVL_HI_gc = (0x03<<2), /* High Level */ -} TC_ERRINTLVL_t; - -/* Overflow Interrupt Level */ -typedef enum TC_OVFINTLVL_enum -{ - TC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - TC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ - TC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ - TC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ -} TC_OVFINTLVL_t; - -/* Compare or Capture D Interrupt Level */ -typedef enum TC_CCDINTLVL_enum -{ - TC_CCDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ - TC_CCDINTLVL_LO_gc = (0x01<<6), /* Low Level */ - TC_CCDINTLVL_MED_gc = (0x02<<6), /* Medium Level */ - TC_CCDINTLVL_HI_gc = (0x03<<6), /* High Level */ -} TC_CCDINTLVL_t; - -/* Compare or Capture C Interrupt Level */ -typedef enum TC_CCCINTLVL_enum -{ - TC_CCCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ - TC_CCCINTLVL_LO_gc = (0x01<<4), /* Low Level */ - TC_CCCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ - TC_CCCINTLVL_HI_gc = (0x03<<4), /* High Level */ -} TC_CCCINTLVL_t; - -/* Compare or Capture B Interrupt Level */ -typedef enum TC_CCBINTLVL_enum -{ - TC_CCBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ - TC_CCBINTLVL_LO_gc = (0x01<<2), /* Low Level */ - TC_CCBINTLVL_MED_gc = (0x02<<2), /* Medium Level */ - TC_CCBINTLVL_HI_gc = (0x03<<2), /* High Level */ -} TC_CCBINTLVL_t; - -/* Compare or Capture A Interrupt Level */ -typedef enum TC_CCAINTLVL_enum -{ - TC_CCAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - TC_CCAINTLVL_LO_gc = (0x01<<0), /* Low Level */ - TC_CCAINTLVL_MED_gc = (0x02<<0), /* Medium Level */ - TC_CCAINTLVL_HI_gc = (0x03<<0), /* High Level */ -} TC_CCAINTLVL_t; - -/* Timer/Counter Command */ -typedef enum TC_CMD_enum -{ - TC_CMD_NONE_gc = (0x00<<2), /* No Command */ - TC_CMD_UPDATE_gc = (0x01<<2), /* Force Update */ - TC_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ - TC_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ -} TC_CMD_t; - - -/* --------------------------------------------------------------------------- -TC2 - 16-bit Timer/Counter type 2 --------------------------------------------------------------------------- -*/ - -/* 16-bit Timer/Counter type 2 */ -typedef struct TC2_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t CTRLC; /* Control register C */ - register8_t reserved_0x03; - register8_t CTRLE; /* Control Register E */ - register8_t reserved_0x05; - register8_t INTCTRLA; /* Interrupt Control Register A */ - register8_t INTCTRLB; /* Interrupt Control Register B */ - register8_t reserved_0x08; - register8_t CTRLF; /* Control Register F */ - register8_t reserved_0x0A; - register8_t reserved_0x0B; - register8_t INTFLAGS; /* Interrupt Flag Register */ - register8_t reserved_0x0D; - register8_t reserved_0x0E; - register8_t reserved_0x0F; - register8_t reserved_0x10; - register8_t reserved_0x11; - register8_t reserved_0x12; - register8_t reserved_0x13; - register8_t reserved_0x14; - register8_t reserved_0x15; - register8_t reserved_0x16; - register8_t reserved_0x17; - register8_t reserved_0x18; - register8_t reserved_0x19; - register8_t reserved_0x1A; - register8_t reserved_0x1B; - register8_t reserved_0x1C; - register8_t reserved_0x1D; - register8_t reserved_0x1E; - register8_t reserved_0x1F; - register8_t LCNT; /* Low Byte Count */ - register8_t HCNT; /* High Byte Count */ - register8_t reserved_0x22; - register8_t reserved_0x23; - register8_t reserved_0x24; - register8_t reserved_0x25; - register8_t LPER; /* Low Byte Period */ - register8_t HPER; /* High Byte Period */ - register8_t LCMPA; /* Low Byte Compare A */ - register8_t HCMPA; /* High Byte Compare A */ - register8_t LCMPB; /* Low Byte Compare B */ - register8_t HCMPB; /* High Byte Compare B */ - register8_t LCMPC; /* Low Byte Compare C */ - register8_t HCMPC; /* High Byte Compare C */ - register8_t LCMPD; /* Low Byte Compare D */ - register8_t HCMPD; /* High Byte Compare D */ -} TC2_t; - -/* Clock Selection */ -typedef enum TC2_CLKSEL_enum -{ - TC2_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */ - TC2_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */ - TC2_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */ - TC2_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */ - TC2_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */ - TC2_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */ - TC2_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */ - TC2_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */ - TC2_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */ - TC2_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */ - TC2_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */ - TC2_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */ - TC2_CLKSEL_EVCH4_gc = (0x0C<<0), /* Event Channel 4 */ - TC2_CLKSEL_EVCH5_gc = (0x0D<<0), /* Event Channel 5 */ - TC2_CLKSEL_EVCH6_gc = (0x0E<<0), /* Event Channel 6 */ - TC2_CLKSEL_EVCH7_gc = (0x0F<<0), /* Event Channel 7 */ -} TC2_CLKSEL_t; - -/* Byte Mode */ -typedef enum TC2_BYTEM_enum -{ - TC2_BYTEM_NORMAL_gc = (0x00<<0), /* 16-bit mode */ - TC2_BYTEM_BYTEMODE_gc = (0x01<<0), /* Timer/Counter operating in byte mode only (TC2) */ - TC2_BYTEM_SPLITMODE_gc = (0x02<<0), /* Timer/Counter split into two 8-bit Counters */ -} TC2_BYTEM_t; - -/* High Byte Underflow Interrupt Level */ -typedef enum TC2_HUNFINTLVL_enum -{ - TC2_HUNFINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ - TC2_HUNFINTLVL_LO_gc = (0x01<<2), /* Low Level */ - TC2_HUNFINTLVL_MED_gc = (0x02<<2), /* Medium Level */ - TC2_HUNFINTLVL_HI_gc = (0x03<<2), /* High Level */ -} TC2_HUNFINTLVL_t; - -/* Low Byte Underflow Interrupt Level */ -typedef enum TC2_LUNFINTLVL_enum -{ - TC2_LUNFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - TC2_LUNFINTLVL_LO_gc = (0x01<<0), /* Low Level */ - TC2_LUNFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ - TC2_LUNFINTLVL_HI_gc = (0x03<<0), /* High Level */ -} TC2_LUNFINTLVL_t; - -/* Low Byte Compare D Interrupt Level */ -typedef enum TC2_LCMPDINTLVL_enum -{ - TC2_LCMPDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ - TC2_LCMPDINTLVL_LO_gc = (0x01<<6), /* Low Level */ - TC2_LCMPDINTLVL_MED_gc = (0x02<<6), /* Medium Level */ - TC2_LCMPDINTLVL_HI_gc = (0x03<<6), /* High Level */ -} TC2_LCMPDINTLVL_t; - -/* Low Byte Compare C Interrupt Level */ -typedef enum TC2_LCMPCINTLVL_enum -{ - TC2_LCMPCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ - TC2_LCMPCINTLVL_LO_gc = (0x01<<4), /* Low Level */ - TC2_LCMPCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ - TC2_LCMPCINTLVL_HI_gc = (0x03<<4), /* High Level */ -} TC2_LCMPCINTLVL_t; - -/* Low Byte Compare B Interrupt Level */ -typedef enum TC2_LCMPBINTLVL_enum -{ - TC2_LCMPBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ - TC2_LCMPBINTLVL_LO_gc = (0x01<<2), /* Low Level */ - TC2_LCMPBINTLVL_MED_gc = (0x02<<2), /* Medium Level */ - TC2_LCMPBINTLVL_HI_gc = (0x03<<2), /* High Level */ -} TC2_LCMPBINTLVL_t; - -/* Low Byte Compare A Interrupt Level */ -typedef enum TC2_LCMPAINTLVL_enum -{ - TC2_LCMPAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - TC2_LCMPAINTLVL_LO_gc = (0x01<<0), /* Low Level */ - TC2_LCMPAINTLVL_MED_gc = (0x02<<0), /* Medium Level */ - TC2_LCMPAINTLVL_HI_gc = (0x03<<0), /* High Level */ -} TC2_LCMPAINTLVL_t; - -/* Timer/Counter Command */ -typedef enum TC2_CMD_enum -{ - TC2_CMD_NONE_gc = (0x00<<2), /* No Command */ - TC2_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ - TC2_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ -} TC2_CMD_t; - -/* Timer/Counter Command */ -typedef enum TC2_CMDEN_enum -{ - TC2_CMDEN_LOW_gc = (0x01<<0), /* Low Byte Timer/Counter */ - TC2_CMDEN_HIGH_gc = (0x02<<0), /* High Byte Timer/Counter */ - TC2_CMDEN_BOTH_gc = (0x03<<0), /* Both Low Byte and High Byte Timer/Counters */ -} TC2_CMDEN_t; - - -/* --------------------------------------------------------------------------- -AWEX - Timer/Counter Advanced Waveform Extension --------------------------------------------------------------------------- -*/ - -/* Advanced Waveform Extension */ -typedef struct AWEX_struct -{ - register8_t CTRL; /* Control Register */ - register8_t reserved_0x01; - register8_t FDEMASK; /* Fault Detection Event Mask */ - register8_t FDCTRL; /* Fault Detection Control Register */ - register8_t STATUS; /* Status Register */ - register8_t STATUSSET; /* Status Set Register */ - register8_t DTBOTH; /* Dead Time Both Sides */ - register8_t DTBOTHBUF; /* Dead Time Both Sides Buffer */ - register8_t DTLS; /* Dead Time Low Side */ - register8_t DTHS; /* Dead Time High Side */ - register8_t DTLSBUF; /* Dead Time Low Side Buffer */ - register8_t DTHSBUF; /* Dead Time High Side Buffer */ - register8_t OUTOVEN; /* Output Override Enable */ -} AWEX_t; - -/* Fault Detect Action */ -typedef enum AWEX_FDACT_enum -{ - AWEX_FDACT_NONE_gc = (0x00<<0), /* No Fault Protection */ - AWEX_FDACT_CLEAROE_gc = (0x01<<0), /* Clear Output Enable Bits */ - AWEX_FDACT_CLEARDIR_gc = (0x03<<0), /* Clear I/O Port Direction Bits */ -} AWEX_FDACT_t; - - -/* --------------------------------------------------------------------------- -HIRES - Timer/Counter High-Resolution Extension --------------------------------------------------------------------------- -*/ - -/* High-Resolution Extension */ -typedef struct HIRES_struct -{ - register8_t CTRLA; /* Control Register */ -} HIRES_t; - -/* High Resolution Enable */ -typedef enum HIRES_HREN_enum -{ - HIRES_HREN_NONE_gc = (0x00<<0), /* No Fault Protection */ - HIRES_HREN_TC0_gc = (0x01<<0), /* Enable High Resolution on Timer/Counter 0 */ - HIRES_HREN_TC1_gc = (0x02<<0), /* Enable High Resolution on Timer/Counter 1 */ - HIRES_HREN_BOTH_gc = (0x03<<0), /* Enable High Resolution both Timer/Counters */ -} HIRES_HREN_t; - - -/* --------------------------------------------------------------------------- -USART - Universal Asynchronous Receiver-Transmitter --------------------------------------------------------------------------- -*/ - -/* Universal Synchronous/Asynchronous Receiver/Transmitter */ -typedef struct USART_struct -{ - register8_t DATA; /* Data Register */ - register8_t STATUS; /* Status Register */ - register8_t reserved_0x02; - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t CTRLC; /* Control Register C */ - register8_t BAUDCTRLA; /* Baud Rate Control Register A */ - register8_t BAUDCTRLB; /* Baud Rate Control Register B */ -} USART_t; - -/* Receive Complete Interrupt level */ -typedef enum USART_RXCINTLVL_enum -{ - USART_RXCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ - USART_RXCINTLVL_LO_gc = (0x01<<4), /* Low Level */ - USART_RXCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ - USART_RXCINTLVL_HI_gc = (0x03<<4), /* High Level */ -} USART_RXCINTLVL_t; - -/* Transmit Complete Interrupt level */ -typedef enum USART_TXCINTLVL_enum -{ - USART_TXCINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ - USART_TXCINTLVL_LO_gc = (0x01<<2), /* Low Level */ - USART_TXCINTLVL_MED_gc = (0x02<<2), /* Medium Level */ - USART_TXCINTLVL_HI_gc = (0x03<<2), /* High Level */ -} USART_TXCINTLVL_t; - -/* Data Register Empty Interrupt level */ -typedef enum USART_DREINTLVL_enum -{ - USART_DREINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - USART_DREINTLVL_LO_gc = (0x01<<0), /* Low Level */ - USART_DREINTLVL_MED_gc = (0x02<<0), /* Medium Level */ - USART_DREINTLVL_HI_gc = (0x03<<0), /* High Level */ -} USART_DREINTLVL_t; - -/* Character Size */ -typedef enum USART_CHSIZE_enum -{ - USART_CHSIZE_5BIT_gc = (0x00<<0), /* Character size: 5 bit */ - USART_CHSIZE_6BIT_gc = (0x01<<0), /* Character size: 6 bit */ - USART_CHSIZE_7BIT_gc = (0x02<<0), /* Character size: 7 bit */ - USART_CHSIZE_8BIT_gc = (0x03<<0), /* Character size: 8 bit */ - USART_CHSIZE_9BIT_gc = (0x07<<0), /* Character size: 9 bit */ -} USART_CHSIZE_t; - -/* Communication Mode */ -typedef enum USART_CMODE_enum -{ - USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6), /* Asynchronous Mode */ - USART_CMODE_SYNCHRONOUS_gc = (0x01<<6), /* Synchronous Mode */ - USART_CMODE_IRDA_gc = (0x02<<6), /* IrDA Mode */ - USART_CMODE_MSPI_gc = (0x03<<6), /* Master SPI Mode */ -} USART_CMODE_t; - -/* Parity Mode */ -typedef enum USART_PMODE_enum -{ - USART_PMODE_DISABLED_gc = (0x00<<4), /* No Parity */ - USART_PMODE_EVEN_gc = (0x02<<4), /* Even Parity */ - USART_PMODE_ODD_gc = (0x03<<4), /* Odd Parity */ -} USART_PMODE_t; - - -/* --------------------------------------------------------------------------- -SPI - Serial Peripheral Interface --------------------------------------------------------------------------- -*/ - -/* Serial Peripheral Interface */ -typedef struct SPI_struct -{ - register8_t CTRL; /* Control Register */ - register8_t INTCTRL; /* Interrupt Control Register */ - register8_t STATUS; /* Status Register */ - register8_t DATA; /* Data Register */ -} SPI_t; - -/* SPI Mode */ -typedef enum SPI_MODE_enum -{ - SPI_MODE_0_gc = (0x00<<2), /* SPI Mode 0 */ - SPI_MODE_1_gc = (0x01<<2), /* SPI Mode 1 */ - SPI_MODE_2_gc = (0x02<<2), /* SPI Mode 2 */ - SPI_MODE_3_gc = (0x03<<2), /* SPI Mode 3 */ -} SPI_MODE_t; - -/* Prescaler setting */ -typedef enum SPI_PRESCALER_enum -{ - SPI_PRESCALER_DIV4_gc = (0x00<<0), /* System Clock / 4 */ - SPI_PRESCALER_DIV16_gc = (0x01<<0), /* System Clock / 16 */ - SPI_PRESCALER_DIV64_gc = (0x02<<0), /* System Clock / 64 */ - SPI_PRESCALER_DIV128_gc = (0x03<<0), /* System Clock / 128 */ -} SPI_PRESCALER_t; - -/* Interrupt level */ -typedef enum SPI_INTLVL_enum -{ - SPI_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - SPI_INTLVL_LO_gc = (0x01<<0), /* Low Level */ - SPI_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ - SPI_INTLVL_HI_gc = (0x03<<0), /* High Level */ -} SPI_INTLVL_t; - - -/* --------------------------------------------------------------------------- -IRCOM - IR Communication Module --------------------------------------------------------------------------- -*/ - -/* IR Communication Module */ -typedef struct IRCOM_struct -{ - register8_t CTRL; /* Control Register */ - register8_t TXPLCTRL; /* IrDA Transmitter Pulse Length Control Register */ - register8_t RXPLCTRL; /* IrDA Receiver Pulse Length Control Register */ -} IRCOM_t; - -/* Event channel selection */ -typedef enum IRDA_EVSEL_enum -{ - IRDA_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ - IRDA_EVSEL_0_gc = (0x08<<0), /* Event Channel 0 */ - IRDA_EVSEL_1_gc = (0x09<<0), /* Event Channel 1 */ - IRDA_EVSEL_2_gc = (0x0A<<0), /* Event Channel 2 */ - IRDA_EVSEL_3_gc = (0x0B<<0), /* Event Channel 3 */ - IRDA_EVSEL_4_gc = (0x0C<<0), /* Event Channel 4 */ - IRDA_EVSEL_5_gc = (0x0D<<0), /* Event Channel 5 */ - IRDA_EVSEL_6_gc = (0x0E<<0), /* Event Channel 6 */ - IRDA_EVSEL_7_gc = (0x0F<<0), /* Event Channel 7 */ -} IRDA_EVSEL_t; - - -/* --------------------------------------------------------------------------- -FUSE - Fuses and Lockbits --------------------------------------------------------------------------- -*/ - -/* Fuses */ -typedef struct NVM_FUSES_struct -{ - register8_t FUSEBYTE0; /* JTAG User ID */ - register8_t FUSEBYTE1; /* Watchdog Configuration */ - register8_t FUSEBYTE2; /* Reset Configuration */ - register8_t reserved_0x03; - register8_t FUSEBYTE4; /* Start-up Configuration */ - register8_t FUSEBYTE5; /* EESAVE and BOD Level */ -} NVM_FUSES_t; - -/* Boot Loader Section Reset Vector */ -typedef enum BOOTRST_enum -{ - BOOTRST_BOOTLDR_gc = (0x00<<6), /* Boot Loader Reset */ - BOOTRST_APPLICATION_gc = (0x01<<6), /* Application Reset */ -} BOOTRST_t; - -/* Timer Oscillator pin location */ -typedef enum TOSCSEL_enum -{ - TOSCSEL_ALTERNATE_gc = (0x00<<5), /* TOSC1 / TOSC2 on separate pins */ - TOSCSEL_XTAL_gc = (0x01<<5), /* TOSC1 / TOSC2 shared with XTAL1 / XTAL2 */ -} TOSCSEL_t; - -/* BOD operation */ -typedef enum BOD_enum -{ - BOD_SAMPLED_gc = (0x01<<0), /* BOD enabled in sampled mode */ - BOD_CONTINUOUS_gc = (0x02<<0), /* BOD enabled continuously */ - BOD_DISABLED_gc = (0x03<<0), /* BOD Disabled */ -} BOD_t; - -/* BOD operation */ -typedef enum BODACT_enum -{ - BODACT_SAMPLED_gc = (0x01<<4), /* BOD enabled in sampled mode */ - BODACT_CONTINUOUS_gc = (0x02<<4), /* BOD enabled continuously */ - BODACT_DISABLED_gc = (0x03<<4), /* BOD Disabled */ -} BODACT_t; - -/* Watchdog (Window) Timeout Period */ -typedef enum WD_enum -{ - WD_8CLK_gc = (0x00<<4), /* 8 cycles (8ms @ 3.3V) */ - WD_16CLK_gc = (0x01<<4), /* 16 cycles (16ms @ 3.3V) */ - WD_32CLK_gc = (0x02<<4), /* 32 cycles (32ms @ 3.3V) */ - WD_64CLK_gc = (0x03<<4), /* 64 cycles (64ms @ 3.3V) */ - WD_128CLK_gc = (0x04<<4), /* 128 cycles (0.125s @ 3.3V) */ - WD_256CLK_gc = (0x05<<4), /* 256 cycles (0.25s @ 3.3V) */ - WD_512CLK_gc = (0x06<<4), /* 512 cycles (0.5s @ 3.3V) */ - WD_1KCLK_gc = (0x07<<4), /* 1K cycles (1s @ 3.3V) */ - WD_2KCLK_gc = (0x08<<4), /* 2K cycles (2s @ 3.3V) */ - WD_4KCLK_gc = (0x09<<4), /* 4K cycles (4s @ 3.3V) */ - WD_8KCLK_gc = (0x0A<<4), /* 8K cycles (8s @ 3.3V) */ -} WD_t; - -/* Watchdog (Window) Timeout Period */ -typedef enum WDP_enum -{ - WDP_8CLK_gc = (0x00<<0), /* 8 cycles (8ms @ 3.3V) */ - WDP_16CLK_gc = (0x01<<0), /* 16 cycles (16ms @ 3.3V) */ - WDP_32CLK_gc = (0x02<<0), /* 32 cycles (32ms @ 3.3V) */ - WDP_64CLK_gc = (0x03<<0), /* 64 cycles (64ms @ 3.3V) */ - WDP_128CLK_gc = (0x04<<0), /* 128 cycles (0.125s @ 3.3V) */ - WDP_256CLK_gc = (0x05<<0), /* 256 cycles (0.25s @ 3.3V) */ - WDP_512CLK_gc = (0x06<<0), /* 512 cycles (0.5s @ 3.3V) */ - WDP_1KCLK_gc = (0x07<<0), /* 1K cycles (1s @ 3.3V) */ - WDP_2KCLK_gc = (0x08<<0), /* 2K cycles (2s @ 3.3V) */ - WDP_4KCLK_gc = (0x09<<0), /* 4K cycles (4s @ 3.3V) */ - WDP_8KCLK_gc = (0x0A<<0), /* 8K cycles (8s @ 3.3V) */ -} WDP_t; - -/* Start-up Time */ -typedef enum SUT_enum -{ - SUT_0MS_gc = (0x03<<2), /* 0 ms */ - SUT_4MS_gc = (0x01<<2), /* 4 ms */ - SUT_64MS_gc = (0x00<<2), /* 64 ms */ -} SUT_t; - -/* Brownout Detection Voltage Level */ -typedef enum BODLVL_enum -{ - BODLVL_1V6_gc = (0x07<<0), /* 1.6 V */ - BODLVL_1V8_gc = (0x06<<0), /* 1.8 V */ - BODLVL_2V0_gc = (0x05<<0), /* 2.0 V */ - BODLVL_2V2_gc = (0x04<<0), /* 2.2 V */ - BODLVL_2V4_gc = (0x03<<0), /* 2.4 V */ - BODLVL_2V6_gc = (0x02<<0), /* 2.6 V */ - BODLVL_2V8_gc = (0x01<<0), /* 2.8 V */ - BODLVL_3V0_gc = (0x00<<0), /* 3.0 V */ -} BODLVL_t; - - -/* --------------------------------------------------------------------------- -LOCKBIT - Fuses and Lockbits --------------------------------------------------------------------------- -*/ - -/* Lock Bits */ -typedef struct NVM_LOCKBITS_struct -{ - register8_t LOCK_BITS; /* Lock Bits (Changed from LOCKBITS to avoid avr-libc collision) */ -} NVM_LOCKBITS_t; - -/* Boot lock bits - boot setcion */ -typedef enum FUSE_BLBB_enum -{ - FUSE_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ - FUSE_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ - FUSE_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ - FUSE_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ -} FUSE_BLBB_t; - -/* Boot lock bits - application section */ -typedef enum FUSE_BLBA_enum -{ - FUSE_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ - FUSE_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ - FUSE_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ - FUSE_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ -} FUSE_BLBA_t; - -/* Boot lock bits - application table section */ -typedef enum FUSE_BLBAT_enum -{ - FUSE_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ - FUSE_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ - FUSE_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ - FUSE_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ -} FUSE_BLBAT_t; - -/* Lock bits */ -typedef enum FUSE_LB_enum -{ - FUSE_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ - FUSE_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ - FUSE_LB_NOLOCK_gc = (0x03<<0), /* No locks */ -} FUSE_LB_t; - - -/* --------------------------------------------------------------------------- -SIGROW - Signature Row --------------------------------------------------------------------------- -*/ - -/* Production Signatures */ -typedef struct NVM_PROD_SIGNATURES_struct -{ - register8_t RCOSC2M; /* RCOSC 2 MHz Calibration Value B */ - register8_t RCOSC2MA; /* RCOSC 2 MHz Calibration Value A */ - register8_t RCOSC32K; /* RCOSC 32.768 kHz Calibration Value */ - register8_t RCOSC32M; /* RCOSC 32 MHz Calibration Value B */ - register8_t RCOSC32MA; /* RCOSC 32 MHz Calibration Value A */ - register8_t reserved_0x05; - register8_t reserved_0x06; - register8_t reserved_0x07; - register8_t LOTNUM0; /* Lot Number Byte 0, ASCII */ - register8_t LOTNUM1; /* Lot Number Byte 1, ASCII */ - register8_t LOTNUM2; /* Lot Number Byte 2, ASCII */ - register8_t LOTNUM3; /* Lot Number Byte 3, ASCII */ - register8_t LOTNUM4; /* Lot Number Byte 4, ASCII */ - register8_t LOTNUM5; /* Lot Number Byte 5, ASCII */ - register8_t reserved_0x0E; - register8_t reserved_0x0F; - register8_t WAFNUM; /* Wafer Number */ - register8_t reserved_0x11; - register8_t COORDX0; /* Wafer Coordinate X Byte 0 */ - register8_t COORDX1; /* Wafer Coordinate X Byte 1 */ - register8_t COORDY0; /* Wafer Coordinate Y Byte 0 */ - register8_t COORDY1; /* Wafer Coordinate Y Byte 1 */ - register8_t reserved_0x16; - register8_t reserved_0x17; - register8_t reserved_0x18; - register8_t reserved_0x19; - register8_t USBCAL0; /* USB Calibration Byte 0 */ - register8_t USBCAL1; /* USB Calibration Byte 1 */ - register8_t USBRCOSC; /* USB RCOSC Calibration Value B */ - register8_t USBRCOSCA; /* USB RCOSC Calibration Value A */ - register8_t reserved_0x1E; - register8_t reserved_0x1F; - register8_t ADCACAL0; /* ADCA Calibration Byte 0 */ - register8_t ADCACAL1; /* ADCA Calibration Byte 1 */ - register8_t reserved_0x22; - register8_t reserved_0x23; - register8_t ADCBCAL0; /* ADCB Calibration Byte 0 */ - register8_t ADCBCAL1; /* ADCB Calibration Byte 1 */ - register8_t reserved_0x26; - register8_t reserved_0x27; - register8_t reserved_0x28; - register8_t reserved_0x29; - register8_t reserved_0x2A; - register8_t reserved_0x2B; - register8_t reserved_0x2C; - register8_t reserved_0x2D; - register8_t TEMPSENSE0; /* Temperature Sensor Calibration Byte 0 */ - register8_t TEMPSENSE1; /* Temperature Sensor Calibration Byte 1 */ - register8_t DACA0OFFCAL; /* DACA0 Calibration Byte 0 */ - register8_t DACA0GAINCAL; /* DACA0 Calibration Byte 1 */ - register8_t DACB0OFFCAL; /* DACB0 Calibration Byte 0 */ - register8_t DACB0GAINCAL; /* DACB0 Calibration Byte 1 */ - register8_t DACA1OFFCAL; /* DACA1 Calibration Byte 0 */ - register8_t DACA1GAINCAL; /* DACA1 Calibration Byte 1 */ - register8_t DACB1OFFCAL; /* DACB1 Calibration Byte 0 */ - register8_t DACB1GAINCAL; /* DACB1 Calibration Byte 1 */ - register8_t reserved_0x38; - register8_t reserved_0x39; - register8_t reserved_0x3A; - register8_t reserved_0x3B; - register8_t reserved_0x3C; - register8_t reserved_0x3D; - register8_t reserved_0x3E; - register8_t reserved_0x3F; - register8_t reserved_0x40; - register8_t reserved_0x41; - register8_t reserved_0x42; - register8_t reserved_0x43; - register8_t reserved_0x44; - register8_t reserved_0x45; - register8_t reserved_0x46; - register8_t reserved_0x47; -} NVM_PROD_SIGNATURES_t; - -/* -========================================================================== -IO Module Instances. Mapped to memory. -========================================================================== -*/ - -#define VPORT0 (*(VPORT_t *) 0x0010) /* Virtual Port */ -#define VPORT1 (*(VPORT_t *) 0x0014) /* Virtual Port */ -#define VPORT2 (*(VPORT_t *) 0x0018) /* Virtual Port */ -#define VPORT3 (*(VPORT_t *) 0x001C) /* Virtual Port */ -#define OCD (*(OCD_t *) 0x002E) /* On-Chip Debug System */ -#define CLK (*(CLK_t *) 0x0040) /* Clock System */ -#define SLEEP (*(SLEEP_t *) 0x0048) /* Sleep Controller */ -#define OSC (*(OSC_t *) 0x0050) /* Oscillator */ -#define DFLLRC32M (*(DFLL_t *) 0x0060) /* DFLL */ -#define DFLLRC2M (*(DFLL_t *) 0x0068) /* DFLL */ -#define PR (*(PR_t *) 0x0070) /* Power Reduction */ -#define RST (*(RST_t *) 0x0078) /* Reset */ -#define WDT (*(WDT_t *) 0x0080) /* Watch-Dog Timer */ -#define MCU (*(MCU_t *) 0x0090) /* MCU Control */ -#define PMIC (*(PMIC_t *) 0x00A0) /* Programmable Multi-level Interrupt Controller */ -#define PORTCFG (*(PORTCFG_t *) 0x00B0) /* I/O port Configuration */ -#define AES (*(AES_t *) 0x00C0) /* AES Module */ -#define CRC (*(CRC_t *) 0x00D0) /* Cyclic Redundancy Checker */ -#define VBAT (*(VBAT_t *) 0x00F0) /* Battery Backup Module */ -#define DMA (*(DMA_t *) 0x0100) /* DMA Controller */ -#define EVSYS (*(EVSYS_t *) 0x0180) /* Event System */ -#define NVM (*(NVM_t *) 0x01C0) /* Non-volatile Memory Controller */ -#define ADCA (*(ADC_t *) 0x0200) /* Analog-to-Digital Converter */ -#define ADCB (*(ADC_t *) 0x0240) /* Analog-to-Digital Converter */ -#define DACB (*(DAC_t *) 0x0320) /* Digital-to-Analog Converter */ -#define ACA (*(AC_t *) 0x0380) /* Analog Comparator */ -#define ACB (*(AC_t *) 0x0390) /* Analog Comparator */ -#define RTC32 (*(RTC32_t *) 0x0420) /* 32-bit Real-Time Counter */ -#define TWIC (*(TWI_t *) 0x0480) /* Two-Wire Interface */ -#define TWIE (*(TWI_t *) 0x04A0) /* Two-Wire Interface */ -#define USB (*(USB_t *) 0x04C0) /* Universal Serial Bus */ -#define PORTA (*(PORT_t *) 0x0600) /* I/O Ports */ -#define PORTB (*(PORT_t *) 0x0620) /* I/O Ports */ -#define PORTC (*(PORT_t *) 0x0640) /* I/O Ports */ -#define PORTD (*(PORT_t *) 0x0660) /* I/O Ports */ -#define PORTE (*(PORT_t *) 0x0680) /* I/O Ports */ -#define PORTF (*(PORT_t *) 0x06A0) /* I/O Ports */ -#define PORTR (*(PORT_t *) 0x07E0) /* I/O Ports */ -#define TCC0 (*(TC0_t *) 0x0800) /* 16-bit Timer/Counter 0 */ -#define TCC2 (*(TC2_t *) 0x0800) /* 16-bit Timer/Counter type 2 */ -#define TCC1 (*(TC1_t *) 0x0840) /* 16-bit Timer/Counter 1 */ -#define AWEXC (*(AWEX_t *) 0x0880) /* Advanced Waveform Extension */ -#define HIRESC (*(HIRES_t *) 0x0890) /* High-Resolution Extension */ -#define USARTC0 (*(USART_t *) 0x08A0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ -#define USARTC1 (*(USART_t *) 0x08B0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ -#define SPIC (*(SPI_t *) 0x08C0) /* Serial Peripheral Interface */ -#define IRCOM (*(IRCOM_t *) 0x08F8) /* IR Communication Module */ -#define TCD0 (*(TC0_t *) 0x0900) /* 16-bit Timer/Counter 0 */ -#define TCD2 (*(TC2_t *) 0x0900) /* 16-bit Timer/Counter type 2 */ -#define TCD1 (*(TC1_t *) 0x0940) /* 16-bit Timer/Counter 1 */ -#define HIRESD (*(HIRES_t *) 0x0990) /* High-Resolution Extension */ -#define USARTD0 (*(USART_t *) 0x09A0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ -#define USARTD1 (*(USART_t *) 0x09B0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ -#define SPID (*(SPI_t *) 0x09C0) /* Serial Peripheral Interface */ -#define TCE0 (*(TC0_t *) 0x0A00) /* 16-bit Timer/Counter 0 */ -#define TCE2 (*(TC2_t *) 0x0A00) /* 16-bit Timer/Counter type 2 */ -#define TCE1 (*(TC1_t *) 0x0A40) /* 16-bit Timer/Counter 1 */ -#define AWEXE (*(AWEX_t *) 0x0A80) /* Advanced Waveform Extension */ -#define HIRESE (*(HIRES_t *) 0x0A90) /* High-Resolution Extension */ -#define USARTE0 (*(USART_t *) 0x0AA0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ -#define TCF0 (*(TC0_t *) 0x0B00) /* 16-bit Timer/Counter 0 */ -#define TCF2 (*(TC2_t *) 0x0B00) /* 16-bit Timer/Counter type 2 */ -#define HIRESF (*(HIRES_t *) 0x0B90) /* High-Resolution Extension */ -#define USARTF0 (*(USART_t *) 0x0BA0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ - - -#endif /* !defined (__ASSEMBLER__) */ - - -/* ========== Flattened fully qualified IO register names ========== */ - -/* GPIO - General Purpose IO Registers */ -#define GPIO_GPIOR0 _SFR_MEM8(0x0000) -#define GPIO_GPIOR1 _SFR_MEM8(0x0001) -#define GPIO_GPIOR2 _SFR_MEM8(0x0002) -#define GPIO_GPIOR3 _SFR_MEM8(0x0003) -#define GPIO_GPIOR4 _SFR_MEM8(0x0004) -#define GPIO_GPIOR5 _SFR_MEM8(0x0005) -#define GPIO_GPIOR6 _SFR_MEM8(0x0006) -#define GPIO_GPIOR7 _SFR_MEM8(0x0007) -#define GPIO_GPIOR8 _SFR_MEM8(0x0008) -#define GPIO_GPIOR9 _SFR_MEM8(0x0009) -#define GPIO_GPIORA _SFR_MEM8(0x000A) -#define GPIO_GPIORB _SFR_MEM8(0x000B) -#define GPIO_GPIORC _SFR_MEM8(0x000C) -#define GPIO_GPIORD _SFR_MEM8(0x000D) -#define GPIO_GPIORE _SFR_MEM8(0x000E) -#define GPIO_GPIORF _SFR_MEM8(0x000F) - -/* Deprecated */ -#define GPIO_GPIO0 _SFR_MEM8(0x0000) -#define GPIO_GPIO1 _SFR_MEM8(0x0001) -#define GPIO_GPIO2 _SFR_MEM8(0x0002) -#define GPIO_GPIO3 _SFR_MEM8(0x0003) -#define GPIO_GPIO4 _SFR_MEM8(0x0004) -#define GPIO_GPIO5 _SFR_MEM8(0x0005) -#define GPIO_GPIO6 _SFR_MEM8(0x0006) -#define GPIO_GPIO7 _SFR_MEM8(0x0007) -#define GPIO_GPIO8 _SFR_MEM8(0x0008) -#define GPIO_GPIO9 _SFR_MEM8(0x0009) -#define GPIO_GPIOA _SFR_MEM8(0x000A) -#define GPIO_GPIOB _SFR_MEM8(0x000B) -#define GPIO_GPIOC _SFR_MEM8(0x000C) -#define GPIO_GPIOD _SFR_MEM8(0x000D) -#define GPIO_GPIOE _SFR_MEM8(0x000E) -#define GPIO_GPIOF _SFR_MEM8(0x000F) - -/* NVM_FUSES - Fuses */ -#define FUSE_FUSEBYTE0 _SFR_MEM8(0x0000) -#define FUSE_FUSEBYTE1 _SFR_MEM8(0x0001) -#define FUSE_FUSEBYTE2 _SFR_MEM8(0x0002) -#define FUSE_FUSEBYTE4 _SFR_MEM8(0x0004) -#define FUSE_FUSEBYTE5 _SFR_MEM8(0x0005) - -/* NVM_LOCKBITS - Lock Bits */ -#define LOCKBIT_LOCKBITS _SFR_MEM8(0x0000) - -/* NVM_PROD_SIGNATURES - Production Signatures */ -#define PRODSIGNATURES_RCOSC2M _SFR_MEM8(0x0000) -#define PRODSIGNATURES_RCOSC2MA _SFR_MEM8(0x0001) -#define PRODSIGNATURES_RCOSC32K _SFR_MEM8(0x0002) -#define PRODSIGNATURES_RCOSC32M _SFR_MEM8(0x0003) -#define PRODSIGNATURES_RCOSC32MA _SFR_MEM8(0x0004) -#define PRODSIGNATURES_LOTNUM0 _SFR_MEM8(0x0008) -#define PRODSIGNATURES_LOTNUM1 _SFR_MEM8(0x0009) -#define PRODSIGNATURES_LOTNUM2 _SFR_MEM8(0x000A) -#define PRODSIGNATURES_LOTNUM3 _SFR_MEM8(0x000B) -#define PRODSIGNATURES_LOTNUM4 _SFR_MEM8(0x000C) -#define PRODSIGNATURES_LOTNUM5 _SFR_MEM8(0x000D) -#define PRODSIGNATURES_WAFNUM _SFR_MEM8(0x0010) -#define PRODSIGNATURES_COORDX0 _SFR_MEM8(0x0012) -#define PRODSIGNATURES_COORDX1 _SFR_MEM8(0x0013) -#define PRODSIGNATURES_COORDY0 _SFR_MEM8(0x0014) -#define PRODSIGNATURES_COORDY1 _SFR_MEM8(0x0015) -#define PRODSIGNATURES_USBCAL0 _SFR_MEM8(0x001A) -#define PRODSIGNATURES_USBCAL1 _SFR_MEM8(0x001B) -#define PRODSIGNATURES_USBRCOSC _SFR_MEM8(0x001C) -#define PRODSIGNATURES_USBRCOSCA _SFR_MEM8(0x001D) -#define PRODSIGNATURES_ADCACAL0 _SFR_MEM8(0x0020) -#define PRODSIGNATURES_ADCACAL1 _SFR_MEM8(0x0021) -#define PRODSIGNATURES_ADCBCAL0 _SFR_MEM8(0x0024) -#define PRODSIGNATURES_ADCBCAL1 _SFR_MEM8(0x0025) -#define PRODSIGNATURES_TEMPSENSE0 _SFR_MEM8(0x002E) -#define PRODSIGNATURES_TEMPSENSE1 _SFR_MEM8(0x002F) -#define PRODSIGNATURES_DACA0OFFCAL _SFR_MEM8(0x0030) -#define PRODSIGNATURES_DACA0GAINCAL _SFR_MEM8(0x0031) -#define PRODSIGNATURES_DACB0OFFCAL _SFR_MEM8(0x0032) -#define PRODSIGNATURES_DACB0GAINCAL _SFR_MEM8(0x0033) -#define PRODSIGNATURES_DACA1OFFCAL _SFR_MEM8(0x0034) -#define PRODSIGNATURES_DACA1GAINCAL _SFR_MEM8(0x0035) -#define PRODSIGNATURES_DACB1OFFCAL _SFR_MEM8(0x0036) -#define PRODSIGNATURES_DACB1GAINCAL _SFR_MEM8(0x0037) - -/* VPORT - Virtual Port */ -#define VPORT0_DIR _SFR_MEM8(0x0010) -#define VPORT0_OUT _SFR_MEM8(0x0011) -#define VPORT0_IN _SFR_MEM8(0x0012) -#define VPORT0_INTFLAGS _SFR_MEM8(0x0013) - -/* VPORT - Virtual Port */ -#define VPORT1_DIR _SFR_MEM8(0x0014) -#define VPORT1_OUT _SFR_MEM8(0x0015) -#define VPORT1_IN _SFR_MEM8(0x0016) -#define VPORT1_INTFLAGS _SFR_MEM8(0x0017) - -/* VPORT - Virtual Port */ -#define VPORT2_DIR _SFR_MEM8(0x0018) -#define VPORT2_OUT _SFR_MEM8(0x0019) -#define VPORT2_IN _SFR_MEM8(0x001A) -#define VPORT2_INTFLAGS _SFR_MEM8(0x001B) - -/* VPORT - Virtual Port */ -#define VPORT3_DIR _SFR_MEM8(0x001C) -#define VPORT3_OUT _SFR_MEM8(0x001D) -#define VPORT3_IN _SFR_MEM8(0x001E) -#define VPORT3_INTFLAGS _SFR_MEM8(0x001F) - -/* OCD - On-Chip Debug System */ -#define OCD_OCDR0 _SFR_MEM8(0x002E) -#define OCD_OCDR1 _SFR_MEM8(0x002F) - -/* CPU - CPU registers */ -#define CPU_CCP _SFR_MEM8(0x0034) -#define CPU_RAMPD _SFR_MEM8(0x0038) -#define CPU_RAMPX _SFR_MEM8(0x0039) -#define CPU_RAMPY _SFR_MEM8(0x003A) -#define CPU_RAMPZ _SFR_MEM8(0x003B) -#define CPU_EIND _SFR_MEM8(0x003C) -#define CPU_SPL _SFR_MEM8(0x003D) -#define CPU_SPH _SFR_MEM8(0x003E) -#define CPU_SREG _SFR_MEM8(0x003F) - -/* CLK - Clock System */ -#define CLK_CTRL _SFR_MEM8(0x0040) -#define CLK_PSCTRL _SFR_MEM8(0x0041) -#define CLK_LOCK _SFR_MEM8(0x0042) -#define CLK_RTCCTRL _SFR_MEM8(0x0043) -#define CLK_USBCTRL _SFR_MEM8(0x0044) - -/* SLEEP - Sleep Controller */ -#define SLEEP_CTRL _SFR_MEM8(0x0048) - -/* OSC - Oscillator */ -#define OSC_CTRL _SFR_MEM8(0x0050) -#define OSC_STATUS _SFR_MEM8(0x0051) -#define OSC_XOSCCTRL _SFR_MEM8(0x0052) -#define OSC_XOSCFAIL _SFR_MEM8(0x0053) -#define OSC_RC32KCAL _SFR_MEM8(0x0054) -#define OSC_PLLCTRL _SFR_MEM8(0x0055) -#define OSC_DFLLCTRL _SFR_MEM8(0x0056) - -/* DFLL - DFLL */ -#define DFLLRC32M_CTRL _SFR_MEM8(0x0060) -#define DFLLRC32M_CALA _SFR_MEM8(0x0062) -#define DFLLRC32M_CALB _SFR_MEM8(0x0063) -#define DFLLRC32M_COMP0 _SFR_MEM8(0x0064) -#define DFLLRC32M_COMP1 _SFR_MEM8(0x0065) -#define DFLLRC32M_COMP2 _SFR_MEM8(0x0066) - -/* DFLL - DFLL */ -#define DFLLRC2M_CTRL _SFR_MEM8(0x0068) -#define DFLLRC2M_CALA _SFR_MEM8(0x006A) -#define DFLLRC2M_CALB _SFR_MEM8(0x006B) -#define DFLLRC2M_COMP0 _SFR_MEM8(0x006C) -#define DFLLRC2M_COMP1 _SFR_MEM8(0x006D) -#define DFLLRC2M_COMP2 _SFR_MEM8(0x006E) - -/* PR - Power Reduction */ -#define PR_PRGEN _SFR_MEM8(0x0070) -#define PR_PRPA _SFR_MEM8(0x0071) -#define PR_PRPB _SFR_MEM8(0x0072) -#define PR_PRPC _SFR_MEM8(0x0073) -#define PR_PRPD _SFR_MEM8(0x0074) -#define PR_PRPE _SFR_MEM8(0x0075) -#define PR_PRPF _SFR_MEM8(0x0076) - -/* RST - Reset */ -#define RST_STATUS _SFR_MEM8(0x0078) -#define RST_CTRL _SFR_MEM8(0x0079) - -/* WDT - Watch-Dog Timer */ -#define WDT_CTRL _SFR_MEM8(0x0080) -#define WDT_WINCTRL _SFR_MEM8(0x0081) -#define WDT_STATUS _SFR_MEM8(0x0082) - -/* MCU - MCU Control */ -#define MCU_DEVID0 _SFR_MEM8(0x0090) -#define MCU_DEVID1 _SFR_MEM8(0x0091) -#define MCU_DEVID2 _SFR_MEM8(0x0092) -#define MCU_REVID _SFR_MEM8(0x0093) -#define MCU_JTAGUID _SFR_MEM8(0x0094) -#define MCU_MCUCR _SFR_MEM8(0x0096) -#define MCU_ANAINIT _SFR_MEM8(0x0097) -#define MCU_EVSYSLOCK _SFR_MEM8(0x0098) -#define MCU_AWEXLOCK _SFR_MEM8(0x0099) - -/* PMIC - Programmable Multi-level Interrupt Controller */ -#define PMIC_STATUS _SFR_MEM8(0x00A0) -#define PMIC_INTPRI _SFR_MEM8(0x00A1) -#define PMIC_CTRL _SFR_MEM8(0x00A2) - -/* PORTCFG - I/O port Configuration */ -#define PORTCFG_MPCMASK _SFR_MEM8(0x00B0) -#define PORTCFG_VPCTRLA _SFR_MEM8(0x00B2) -#define PORTCFG_VPCTRLB _SFR_MEM8(0x00B3) -#define PORTCFG_CLKEVOUT _SFR_MEM8(0x00B4) -#define PORTCFG_EBIOUT _SFR_MEM8(0x00B5) -#define PORTCFG_EVOUTSEL _SFR_MEM8(0x00B6) - -/* AES - AES Module */ -#define AES_CTRL _SFR_MEM8(0x00C0) -#define AES_STATUS _SFR_MEM8(0x00C1) -#define AES_STATE _SFR_MEM8(0x00C2) -#define AES_KEY _SFR_MEM8(0x00C3) -#define AES_INTCTRL _SFR_MEM8(0x00C4) - -/* CRC - Cyclic Redundancy Checker */ -#define CRC_CTRL _SFR_MEM8(0x00D0) -#define CRC_STATUS _SFR_MEM8(0x00D1) -#define CRC_DATAIN _SFR_MEM8(0x00D3) -#define CRC_CHECKSUM0 _SFR_MEM8(0x00D4) -#define CRC_CHECKSUM1 _SFR_MEM8(0x00D5) -#define CRC_CHECKSUM2 _SFR_MEM8(0x00D6) -#define CRC_CHECKSUM3 _SFR_MEM8(0x00D7) - -/* VBAT - Battery Backup Module */ -#define VBAT_CTRL _SFR_MEM8(0x00F0) -#define VBAT_STATUS _SFR_MEM8(0x00F1) -#define VBAT_BACKUP0 _SFR_MEM8(0x00F2) -#define VBAT_BACKUP1 _SFR_MEM8(0x00F3) - -/* DMA - DMA Controller */ -#define DMA_CTRL _SFR_MEM8(0x0100) -#define DMA_INTFLAGS _SFR_MEM8(0x0103) -#define DMA_STATUS _SFR_MEM8(0x0104) -#define DMA_TEMP _SFR_MEM16(0x0106) -#define DMA_CH0_CTRLA _SFR_MEM8(0x0110) -#define DMA_CH0_CTRLB _SFR_MEM8(0x0111) -#define DMA_CH0_ADDRCTRL _SFR_MEM8(0x0112) -#define DMA_CH0_TRIGSRC _SFR_MEM8(0x0113) -#define DMA_CH0_TRFCNT _SFR_MEM16(0x0114) -#define DMA_CH0_REPCNT _SFR_MEM8(0x0116) -#define DMA_CH0_SRCADDR0 _SFR_MEM8(0x0118) -#define DMA_CH0_SRCADDR1 _SFR_MEM8(0x0119) -#define DMA_CH0_SRCADDR2 _SFR_MEM8(0x011A) -#define DMA_CH0_DESTADDR0 _SFR_MEM8(0x011C) -#define DMA_CH0_DESTADDR1 _SFR_MEM8(0x011D) -#define DMA_CH0_DESTADDR2 _SFR_MEM8(0x011E) -#define DMA_CH1_CTRLA _SFR_MEM8(0x0120) -#define DMA_CH1_CTRLB _SFR_MEM8(0x0121) -#define DMA_CH1_ADDRCTRL _SFR_MEM8(0x0122) -#define DMA_CH1_TRIGSRC _SFR_MEM8(0x0123) -#define DMA_CH1_TRFCNT _SFR_MEM16(0x0124) -#define DMA_CH1_REPCNT _SFR_MEM8(0x0126) -#define DMA_CH1_SRCADDR0 _SFR_MEM8(0x0128) -#define DMA_CH1_SRCADDR1 _SFR_MEM8(0x0129) -#define DMA_CH1_SRCADDR2 _SFR_MEM8(0x012A) -#define DMA_CH1_DESTADDR0 _SFR_MEM8(0x012C) -#define DMA_CH1_DESTADDR1 _SFR_MEM8(0x012D) -#define DMA_CH1_DESTADDR2 _SFR_MEM8(0x012E) -#define DMA_CH2_CTRLA _SFR_MEM8(0x0130) -#define DMA_CH2_CTRLB _SFR_MEM8(0x0131) -#define DMA_CH2_ADDRCTRL _SFR_MEM8(0x0132) -#define DMA_CH2_TRIGSRC _SFR_MEM8(0x0133) -#define DMA_CH2_TRFCNT _SFR_MEM16(0x0134) -#define DMA_CH2_REPCNT _SFR_MEM8(0x0136) -#define DMA_CH2_SRCADDR0 _SFR_MEM8(0x0138) -#define DMA_CH2_SRCADDR1 _SFR_MEM8(0x0139) -#define DMA_CH2_SRCADDR2 _SFR_MEM8(0x013A) -#define DMA_CH2_DESTADDR0 _SFR_MEM8(0x013C) -#define DMA_CH2_DESTADDR1 _SFR_MEM8(0x013D) -#define DMA_CH2_DESTADDR2 _SFR_MEM8(0x013E) -#define DMA_CH3_CTRLA _SFR_MEM8(0x0140) -#define DMA_CH3_CTRLB _SFR_MEM8(0x0141) -#define DMA_CH3_ADDRCTRL _SFR_MEM8(0x0142) -#define DMA_CH3_TRIGSRC _SFR_MEM8(0x0143) -#define DMA_CH3_TRFCNT _SFR_MEM16(0x0144) -#define DMA_CH3_REPCNT _SFR_MEM8(0x0146) -#define DMA_CH3_SRCADDR0 _SFR_MEM8(0x0148) -#define DMA_CH3_SRCADDR1 _SFR_MEM8(0x0149) -#define DMA_CH3_SRCADDR2 _SFR_MEM8(0x014A) -#define DMA_CH3_DESTADDR0 _SFR_MEM8(0x014C) -#define DMA_CH3_DESTADDR1 _SFR_MEM8(0x014D) -#define DMA_CH3_DESTADDR2 _SFR_MEM8(0x014E) - -/* EVSYS - Event System */ -#define EVSYS_CH0MUX _SFR_MEM8(0x0180) -#define EVSYS_CH1MUX _SFR_MEM8(0x0181) -#define EVSYS_CH2MUX _SFR_MEM8(0x0182) -#define EVSYS_CH3MUX _SFR_MEM8(0x0183) -#define EVSYS_CH4MUX _SFR_MEM8(0x0184) -#define EVSYS_CH5MUX _SFR_MEM8(0x0185) -#define EVSYS_CH6MUX _SFR_MEM8(0x0186) -#define EVSYS_CH7MUX _SFR_MEM8(0x0187) -#define EVSYS_CH0CTRL _SFR_MEM8(0x0188) -#define EVSYS_CH1CTRL _SFR_MEM8(0x0189) -#define EVSYS_CH2CTRL _SFR_MEM8(0x018A) -#define EVSYS_CH3CTRL _SFR_MEM8(0x018B) -#define EVSYS_CH4CTRL _SFR_MEM8(0x018C) -#define EVSYS_CH5CTRL _SFR_MEM8(0x018D) -#define EVSYS_CH6CTRL _SFR_MEM8(0x018E) -#define EVSYS_CH7CTRL _SFR_MEM8(0x018F) -#define EVSYS_STROBE _SFR_MEM8(0x0190) -#define EVSYS_DATA _SFR_MEM8(0x0191) - -/* NVM - Non-volatile Memory Controller */ -#define NVM_ADDR0 _SFR_MEM8(0x01C0) -#define NVM_ADDR1 _SFR_MEM8(0x01C1) -#define NVM_ADDR2 _SFR_MEM8(0x01C2) -#define NVM_DATA0 _SFR_MEM8(0x01C4) -#define NVM_DATA1 _SFR_MEM8(0x01C5) -#define NVM_DATA2 _SFR_MEM8(0x01C6) -#define NVM_CMD _SFR_MEM8(0x01CA) -#define NVM_CTRLA _SFR_MEM8(0x01CB) -#define NVM_CTRLB _SFR_MEM8(0x01CC) -#define NVM_INTCTRL _SFR_MEM8(0x01CD) -#define NVM_STATUS _SFR_MEM8(0x01CF) -#define NVM_LOCKBITS _SFR_MEM8(0x01D0) - -/* ADC - Analog-to-Digital Converter */ -#define ADCA_CTRLA _SFR_MEM8(0x0200) -#define ADCA_CTRLB _SFR_MEM8(0x0201) -#define ADCA_REFCTRL _SFR_MEM8(0x0202) -#define ADCA_EVCTRL _SFR_MEM8(0x0203) -#define ADCA_PRESCALER _SFR_MEM8(0x0204) -#define ADCA_INTFLAGS _SFR_MEM8(0x0206) -#define ADCA_TEMP _SFR_MEM8(0x0207) -#define ADCA_CAL _SFR_MEM16(0x020C) -#define ADCA_CH0RES _SFR_MEM16(0x0210) -#define ADCA_CH1RES _SFR_MEM16(0x0212) -#define ADCA_CH2RES _SFR_MEM16(0x0214) -#define ADCA_CH3RES _SFR_MEM16(0x0216) -#define ADCA_CMP _SFR_MEM16(0x0218) -#define ADCA_CH0_CTRL _SFR_MEM8(0x0220) -#define ADCA_CH0_MUXCTRL _SFR_MEM8(0x0221) -#define ADCA_CH0_INTCTRL _SFR_MEM8(0x0222) -#define ADCA_CH0_INTFLAGS _SFR_MEM8(0x0223) -#define ADCA_CH0_RES _SFR_MEM16(0x0224) -#define ADCA_CH0_SCAN _SFR_MEM8(0x0226) -#define ADCA_CH1_CTRL _SFR_MEM8(0x0228) -#define ADCA_CH1_MUXCTRL _SFR_MEM8(0x0229) -#define ADCA_CH1_INTCTRL _SFR_MEM8(0x022A) -#define ADCA_CH1_INTFLAGS _SFR_MEM8(0x022B) -#define ADCA_CH1_RES _SFR_MEM16(0x022C) -#define ADCA_CH1_SCAN _SFR_MEM8(0x022E) -#define ADCA_CH2_CTRL _SFR_MEM8(0x0230) -#define ADCA_CH2_MUXCTRL _SFR_MEM8(0x0231) -#define ADCA_CH2_INTCTRL _SFR_MEM8(0x0232) -#define ADCA_CH2_INTFLAGS _SFR_MEM8(0x0233) -#define ADCA_CH2_RES _SFR_MEM16(0x0234) -#define ADCA_CH2_SCAN _SFR_MEM8(0x0236) -#define ADCA_CH3_CTRL _SFR_MEM8(0x0238) -#define ADCA_CH3_MUXCTRL _SFR_MEM8(0x0239) -#define ADCA_CH3_INTCTRL _SFR_MEM8(0x023A) -#define ADCA_CH3_INTFLAGS _SFR_MEM8(0x023B) -#define ADCA_CH3_RES _SFR_MEM16(0x023C) -#define ADCA_CH3_SCAN _SFR_MEM8(0x023E) - -/* ADC - Analog-to-Digital Converter */ -#define ADCB_CTRLA _SFR_MEM8(0x0240) -#define ADCB_CTRLB _SFR_MEM8(0x0241) -#define ADCB_REFCTRL _SFR_MEM8(0x0242) -#define ADCB_EVCTRL _SFR_MEM8(0x0243) -#define ADCB_PRESCALER _SFR_MEM8(0x0244) -#define ADCB_INTFLAGS _SFR_MEM8(0x0246) -#define ADCB_TEMP _SFR_MEM8(0x0247) -#define ADCB_CAL _SFR_MEM16(0x024C) -#define ADCB_CH0RES _SFR_MEM16(0x0250) -#define ADCB_CH1RES _SFR_MEM16(0x0252) -#define ADCB_CH2RES _SFR_MEM16(0x0254) -#define ADCB_CH3RES _SFR_MEM16(0x0256) -#define ADCB_CMP _SFR_MEM16(0x0258) -#define ADCB_CH0_CTRL _SFR_MEM8(0x0260) -#define ADCB_CH0_MUXCTRL _SFR_MEM8(0x0261) -#define ADCB_CH0_INTCTRL _SFR_MEM8(0x0262) -#define ADCB_CH0_INTFLAGS _SFR_MEM8(0x0263) -#define ADCB_CH0_RES _SFR_MEM16(0x0264) -#define ADCB_CH0_SCAN _SFR_MEM8(0x0266) -#define ADCB_CH1_CTRL _SFR_MEM8(0x0268) -#define ADCB_CH1_MUXCTRL _SFR_MEM8(0x0269) -#define ADCB_CH1_INTCTRL _SFR_MEM8(0x026A) -#define ADCB_CH1_INTFLAGS _SFR_MEM8(0x026B) -#define ADCB_CH1_RES _SFR_MEM16(0x026C) -#define ADCB_CH1_SCAN _SFR_MEM8(0x026E) -#define ADCB_CH2_CTRL _SFR_MEM8(0x0270) -#define ADCB_CH2_MUXCTRL _SFR_MEM8(0x0271) -#define ADCB_CH2_INTCTRL _SFR_MEM8(0x0272) -#define ADCB_CH2_INTFLAGS _SFR_MEM8(0x0273) -#define ADCB_CH2_RES _SFR_MEM16(0x0274) -#define ADCB_CH2_SCAN _SFR_MEM8(0x0276) -#define ADCB_CH3_CTRL _SFR_MEM8(0x0278) -#define ADCB_CH3_MUXCTRL _SFR_MEM8(0x0279) -#define ADCB_CH3_INTCTRL _SFR_MEM8(0x027A) -#define ADCB_CH3_INTFLAGS _SFR_MEM8(0x027B) -#define ADCB_CH3_RES _SFR_MEM16(0x027C) -#define ADCB_CH3_SCAN _SFR_MEM8(0x027E) - -/* DAC - Digital-to-Analog Converter */ -#define DACB_CTRLA _SFR_MEM8(0x0320) -#define DACB_CTRLB _SFR_MEM8(0x0321) -#define DACB_CTRLC _SFR_MEM8(0x0322) -#define DACB_EVCTRL _SFR_MEM8(0x0323) -#define DACB_STATUS _SFR_MEM8(0x0325) -#define DACB_CH0GAINCAL _SFR_MEM8(0x0328) -#define DACB_CH0OFFSETCAL _SFR_MEM8(0x0329) -#define DACB_CH1GAINCAL _SFR_MEM8(0x032A) -#define DACB_CH1OFFSETCAL _SFR_MEM8(0x032B) -#define DACB_CH0DATA _SFR_MEM16(0x0338) -#define DACB_CH1DATA _SFR_MEM16(0x033A) - -/* AC - Analog Comparator */ -#define ACA_AC0CTRL _SFR_MEM8(0x0380) -#define ACA_AC1CTRL _SFR_MEM8(0x0381) -#define ACA_AC0MUXCTRL _SFR_MEM8(0x0382) -#define ACA_AC1MUXCTRL _SFR_MEM8(0x0383) -#define ACA_CTRLA _SFR_MEM8(0x0384) -#define ACA_CTRLB _SFR_MEM8(0x0385) -#define ACA_WINCTRL _SFR_MEM8(0x0386) -#define ACA_STATUS _SFR_MEM8(0x0387) - -/* AC - Analog Comparator */ -#define ACB_AC0CTRL _SFR_MEM8(0x0390) -#define ACB_AC1CTRL _SFR_MEM8(0x0391) -#define ACB_AC0MUXCTRL _SFR_MEM8(0x0392) -#define ACB_AC1MUXCTRL _SFR_MEM8(0x0393) -#define ACB_CTRLA _SFR_MEM8(0x0394) -#define ACB_CTRLB _SFR_MEM8(0x0395) -#define ACB_WINCTRL _SFR_MEM8(0x0396) -#define ACB_STATUS _SFR_MEM8(0x0397) - -/* RTC32 - 32-bit Real-Time Counter */ -#define RTC32_CTRL _SFR_MEM8(0x0420) -#define RTC32_SYNCCTRL _SFR_MEM8(0x0421) -#define RTC32_INTCTRL _SFR_MEM8(0x0422) -#define RTC32_INTFLAGS _SFR_MEM8(0x0423) -#define RTC32_CNT _SFR_MEM32(0x0424) -#define RTC32_PER _SFR_MEM32(0x0428) -#define RTC32_COMP _SFR_MEM32(0x042C) - -/* TWI - Two-Wire Interface */ -#define TWIC_CTRL _SFR_MEM8(0x0480) -#define TWIC_MASTER_CTRLA _SFR_MEM8(0x0481) -#define TWIC_MASTER_CTRLB _SFR_MEM8(0x0482) -#define TWIC_MASTER_CTRLC _SFR_MEM8(0x0483) -#define TWIC_MASTER_STATUS _SFR_MEM8(0x0484) -#define TWIC_MASTER_BAUD _SFR_MEM8(0x0485) -#define TWIC_MASTER_ADDR _SFR_MEM8(0x0486) -#define TWIC_MASTER_DATA _SFR_MEM8(0x0487) -#define TWIC_SLAVE_CTRLA _SFR_MEM8(0x0488) -#define TWIC_SLAVE_CTRLB _SFR_MEM8(0x0489) -#define TWIC_SLAVE_STATUS _SFR_MEM8(0x048A) -#define TWIC_SLAVE_ADDR _SFR_MEM8(0x048B) -#define TWIC_SLAVE_DATA _SFR_MEM8(0x048C) -#define TWIC_SLAVE_ADDRMASK _SFR_MEM8(0x048D) - -/* TWI - Two-Wire Interface */ -#define TWIE_CTRL _SFR_MEM8(0x04A0) -#define TWIE_MASTER_CTRLA _SFR_MEM8(0x04A1) -#define TWIE_MASTER_CTRLB _SFR_MEM8(0x04A2) -#define TWIE_MASTER_CTRLC _SFR_MEM8(0x04A3) -#define TWIE_MASTER_STATUS _SFR_MEM8(0x04A4) -#define TWIE_MASTER_BAUD _SFR_MEM8(0x04A5) -#define TWIE_MASTER_ADDR _SFR_MEM8(0x04A6) -#define TWIE_MASTER_DATA _SFR_MEM8(0x04A7) -#define TWIE_SLAVE_CTRLA _SFR_MEM8(0x04A8) -#define TWIE_SLAVE_CTRLB _SFR_MEM8(0x04A9) -#define TWIE_SLAVE_STATUS _SFR_MEM8(0x04AA) -#define TWIE_SLAVE_ADDR _SFR_MEM8(0x04AB) -#define TWIE_SLAVE_DATA _SFR_MEM8(0x04AC) -#define TWIE_SLAVE_ADDRMASK _SFR_MEM8(0x04AD) - -/* USB - Universal Serial Bus */ -#define USB_CTRLA _SFR_MEM8(0x04C0) -#define USB_CTRLB _SFR_MEM8(0x04C1) -#define USB_STATUS _SFR_MEM8(0x04C2) -#define USB_ADDR _SFR_MEM8(0x04C3) -#define USB_FIFOWP _SFR_MEM8(0x04C4) -#define USB_FIFORP _SFR_MEM8(0x04C5) -#define USB_EPPTR _SFR_MEM16(0x04C6) -#define USB_INTCTRLA _SFR_MEM8(0x04C8) -#define USB_INTCTRLB _SFR_MEM8(0x04C9) -#define USB_INTFLAGSACLR _SFR_MEM8(0x04CA) -#define USB_INTFLAGSASET _SFR_MEM8(0x04CB) -#define USB_INTFLAGSBCLR _SFR_MEM8(0x04CC) -#define USB_INTFLAGSBSET _SFR_MEM8(0x04CD) -#define USB_CAL0 _SFR_MEM8(0x04FA) -#define USB_CAL1 _SFR_MEM8(0x04FB) - -/* PORT - I/O Ports */ -#define PORTA_DIR _SFR_MEM8(0x0600) -#define PORTA_DIRSET _SFR_MEM8(0x0601) -#define PORTA_DIRCLR _SFR_MEM8(0x0602) -#define PORTA_DIRTGL _SFR_MEM8(0x0603) -#define PORTA_OUT _SFR_MEM8(0x0604) -#define PORTA_OUTSET _SFR_MEM8(0x0605) -#define PORTA_OUTCLR _SFR_MEM8(0x0606) -#define PORTA_OUTTGL _SFR_MEM8(0x0607) -#define PORTA_IN _SFR_MEM8(0x0608) -#define PORTA_INTCTRL _SFR_MEM8(0x0609) -#define PORTA_INT0MASK _SFR_MEM8(0x060A) -#define PORTA_INT1MASK _SFR_MEM8(0x060B) -#define PORTA_INTFLAGS _SFR_MEM8(0x060C) -#define PORTA_REMAP _SFR_MEM8(0x060E) -#define PORTA_PIN0CTRL _SFR_MEM8(0x0610) -#define PORTA_PIN1CTRL _SFR_MEM8(0x0611) -#define PORTA_PIN2CTRL _SFR_MEM8(0x0612) -#define PORTA_PIN3CTRL _SFR_MEM8(0x0613) -#define PORTA_PIN4CTRL _SFR_MEM8(0x0614) -#define PORTA_PIN5CTRL _SFR_MEM8(0x0615) -#define PORTA_PIN6CTRL _SFR_MEM8(0x0616) -#define PORTA_PIN7CTRL _SFR_MEM8(0x0617) - -/* PORT - I/O Ports */ -#define PORTB_DIR _SFR_MEM8(0x0620) -#define PORTB_DIRSET _SFR_MEM8(0x0621) -#define PORTB_DIRCLR _SFR_MEM8(0x0622) -#define PORTB_DIRTGL _SFR_MEM8(0x0623) -#define PORTB_OUT _SFR_MEM8(0x0624) -#define PORTB_OUTSET _SFR_MEM8(0x0625) -#define PORTB_OUTCLR _SFR_MEM8(0x0626) -#define PORTB_OUTTGL _SFR_MEM8(0x0627) -#define PORTB_IN _SFR_MEM8(0x0628) -#define PORTB_INTCTRL _SFR_MEM8(0x0629) -#define PORTB_INT0MASK _SFR_MEM8(0x062A) -#define PORTB_INT1MASK _SFR_MEM8(0x062B) -#define PORTB_INTFLAGS _SFR_MEM8(0x062C) -#define PORTB_REMAP _SFR_MEM8(0x062E) -#define PORTB_PIN0CTRL _SFR_MEM8(0x0630) -#define PORTB_PIN1CTRL _SFR_MEM8(0x0631) -#define PORTB_PIN2CTRL _SFR_MEM8(0x0632) -#define PORTB_PIN3CTRL _SFR_MEM8(0x0633) -#define PORTB_PIN4CTRL _SFR_MEM8(0x0634) -#define PORTB_PIN5CTRL _SFR_MEM8(0x0635) -#define PORTB_PIN6CTRL _SFR_MEM8(0x0636) -#define PORTB_PIN7CTRL _SFR_MEM8(0x0637) - -/* PORT - I/O Ports */ -#define PORTC_DIR _SFR_MEM8(0x0640) -#define PORTC_DIRSET _SFR_MEM8(0x0641) -#define PORTC_DIRCLR _SFR_MEM8(0x0642) -#define PORTC_DIRTGL _SFR_MEM8(0x0643) -#define PORTC_OUT _SFR_MEM8(0x0644) -#define PORTC_OUTSET _SFR_MEM8(0x0645) -#define PORTC_OUTCLR _SFR_MEM8(0x0646) -#define PORTC_OUTTGL _SFR_MEM8(0x0647) -#define PORTC_IN _SFR_MEM8(0x0648) -#define PORTC_INTCTRL _SFR_MEM8(0x0649) -#define PORTC_INT0MASK _SFR_MEM8(0x064A) -#define PORTC_INT1MASK _SFR_MEM8(0x064B) -#define PORTC_INTFLAGS _SFR_MEM8(0x064C) -#define PORTC_REMAP _SFR_MEM8(0x064E) -#define PORTC_PIN0CTRL _SFR_MEM8(0x0650) -#define PORTC_PIN1CTRL _SFR_MEM8(0x0651) -#define PORTC_PIN2CTRL _SFR_MEM8(0x0652) -#define PORTC_PIN3CTRL _SFR_MEM8(0x0653) -#define PORTC_PIN4CTRL _SFR_MEM8(0x0654) -#define PORTC_PIN5CTRL _SFR_MEM8(0x0655) -#define PORTC_PIN6CTRL _SFR_MEM8(0x0656) -#define PORTC_PIN7CTRL _SFR_MEM8(0x0657) - -/* PORT - I/O Ports */ -#define PORTD_DIR _SFR_MEM8(0x0660) -#define PORTD_DIRSET _SFR_MEM8(0x0661) -#define PORTD_DIRCLR _SFR_MEM8(0x0662) -#define PORTD_DIRTGL _SFR_MEM8(0x0663) -#define PORTD_OUT _SFR_MEM8(0x0664) -#define PORTD_OUTSET _SFR_MEM8(0x0665) -#define PORTD_OUTCLR _SFR_MEM8(0x0666) -#define PORTD_OUTTGL _SFR_MEM8(0x0667) -#define PORTD_IN _SFR_MEM8(0x0668) -#define PORTD_INTCTRL _SFR_MEM8(0x0669) -#define PORTD_INT0MASK _SFR_MEM8(0x066A) -#define PORTD_INT1MASK _SFR_MEM8(0x066B) -#define PORTD_INTFLAGS _SFR_MEM8(0x066C) -#define PORTD_REMAP _SFR_MEM8(0x066E) -#define PORTD_PIN0CTRL _SFR_MEM8(0x0670) -#define PORTD_PIN1CTRL _SFR_MEM8(0x0671) -#define PORTD_PIN2CTRL _SFR_MEM8(0x0672) -#define PORTD_PIN3CTRL _SFR_MEM8(0x0673) -#define PORTD_PIN4CTRL _SFR_MEM8(0x0674) -#define PORTD_PIN5CTRL _SFR_MEM8(0x0675) -#define PORTD_PIN6CTRL _SFR_MEM8(0x0676) -#define PORTD_PIN7CTRL _SFR_MEM8(0x0677) - -/* PORT - I/O Ports */ -#define PORTE_DIR _SFR_MEM8(0x0680) -#define PORTE_DIRSET _SFR_MEM8(0x0681) -#define PORTE_DIRCLR _SFR_MEM8(0x0682) -#define PORTE_DIRTGL _SFR_MEM8(0x0683) -#define PORTE_OUT _SFR_MEM8(0x0684) -#define PORTE_OUTSET _SFR_MEM8(0x0685) -#define PORTE_OUTCLR _SFR_MEM8(0x0686) -#define PORTE_OUTTGL _SFR_MEM8(0x0687) -#define PORTE_IN _SFR_MEM8(0x0688) -#define PORTE_INTCTRL _SFR_MEM8(0x0689) -#define PORTE_INT0MASK _SFR_MEM8(0x068A) -#define PORTE_INT1MASK _SFR_MEM8(0x068B) -#define PORTE_INTFLAGS _SFR_MEM8(0x068C) -#define PORTE_REMAP _SFR_MEM8(0x068E) -#define PORTE_PIN0CTRL _SFR_MEM8(0x0690) -#define PORTE_PIN1CTRL _SFR_MEM8(0x0691) -#define PORTE_PIN2CTRL _SFR_MEM8(0x0692) -#define PORTE_PIN3CTRL _SFR_MEM8(0x0693) -#define PORTE_PIN4CTRL _SFR_MEM8(0x0694) -#define PORTE_PIN5CTRL _SFR_MEM8(0x0695) -#define PORTE_PIN6CTRL _SFR_MEM8(0x0696) -#define PORTE_PIN7CTRL _SFR_MEM8(0x0697) - -/* PORT - I/O Ports */ -#define PORTF_DIR _SFR_MEM8(0x06A0) -#define PORTF_DIRSET _SFR_MEM8(0x06A1) -#define PORTF_DIRCLR _SFR_MEM8(0x06A2) -#define PORTF_DIRTGL _SFR_MEM8(0x06A3) -#define PORTF_OUT _SFR_MEM8(0x06A4) -#define PORTF_OUTSET _SFR_MEM8(0x06A5) -#define PORTF_OUTCLR _SFR_MEM8(0x06A6) -#define PORTF_OUTTGL _SFR_MEM8(0x06A7) -#define PORTF_IN _SFR_MEM8(0x06A8) -#define PORTF_INTCTRL _SFR_MEM8(0x06A9) -#define PORTF_INT0MASK _SFR_MEM8(0x06AA) -#define PORTF_INT1MASK _SFR_MEM8(0x06AB) -#define PORTF_INTFLAGS _SFR_MEM8(0x06AC) -#define PORTF_REMAP _SFR_MEM8(0x06AE) -#define PORTF_PIN0CTRL _SFR_MEM8(0x06B0) -#define PORTF_PIN1CTRL _SFR_MEM8(0x06B1) -#define PORTF_PIN2CTRL _SFR_MEM8(0x06B2) -#define PORTF_PIN3CTRL _SFR_MEM8(0x06B3) -#define PORTF_PIN4CTRL _SFR_MEM8(0x06B4) -#define PORTF_PIN5CTRL _SFR_MEM8(0x06B5) -#define PORTF_PIN6CTRL _SFR_MEM8(0x06B6) -#define PORTF_PIN7CTRL _SFR_MEM8(0x06B7) - -/* PORT - I/O Ports */ -#define PORTR_DIR _SFR_MEM8(0x07E0) -#define PORTR_DIRSET _SFR_MEM8(0x07E1) -#define PORTR_DIRCLR _SFR_MEM8(0x07E2) -#define PORTR_DIRTGL _SFR_MEM8(0x07E3) -#define PORTR_OUT _SFR_MEM8(0x07E4) -#define PORTR_OUTSET _SFR_MEM8(0x07E5) -#define PORTR_OUTCLR _SFR_MEM8(0x07E6) -#define PORTR_OUTTGL _SFR_MEM8(0x07E7) -#define PORTR_IN _SFR_MEM8(0x07E8) -#define PORTR_INTCTRL _SFR_MEM8(0x07E9) -#define PORTR_INT0MASK _SFR_MEM8(0x07EA) -#define PORTR_INT1MASK _SFR_MEM8(0x07EB) -#define PORTR_INTFLAGS _SFR_MEM8(0x07EC) -#define PORTR_REMAP _SFR_MEM8(0x07EE) -#define PORTR_PIN0CTRL _SFR_MEM8(0x07F0) -#define PORTR_PIN1CTRL _SFR_MEM8(0x07F1) -#define PORTR_PIN2CTRL _SFR_MEM8(0x07F2) -#define PORTR_PIN3CTRL _SFR_MEM8(0x07F3) -#define PORTR_PIN4CTRL _SFR_MEM8(0x07F4) -#define PORTR_PIN5CTRL _SFR_MEM8(0x07F5) -#define PORTR_PIN6CTRL _SFR_MEM8(0x07F6) -#define PORTR_PIN7CTRL _SFR_MEM8(0x07F7) - -/* TC0 - 16-bit Timer/Counter 0 */ -#define TCC0_CTRLA _SFR_MEM8(0x0800) -#define TCC0_CTRLB _SFR_MEM8(0x0801) -#define TCC0_CTRLC _SFR_MEM8(0x0802) -#define TCC0_CTRLD _SFR_MEM8(0x0803) -#define TCC0_CTRLE _SFR_MEM8(0x0804) -#define TCC0_INTCTRLA _SFR_MEM8(0x0806) -#define TCC0_INTCTRLB _SFR_MEM8(0x0807) -#define TCC0_CTRLFCLR _SFR_MEM8(0x0808) -#define TCC0_CTRLFSET _SFR_MEM8(0x0809) -#define TCC0_CTRLGCLR _SFR_MEM8(0x080A) -#define TCC0_CTRLGSET _SFR_MEM8(0x080B) -#define TCC0_INTFLAGS _SFR_MEM8(0x080C) -#define TCC0_TEMP _SFR_MEM8(0x080F) -#define TCC0_CNT _SFR_MEM16(0x0820) -#define TCC0_PER _SFR_MEM16(0x0826) -#define TCC0_CCA _SFR_MEM16(0x0828) -#define TCC0_CCB _SFR_MEM16(0x082A) -#define TCC0_CCC _SFR_MEM16(0x082C) -#define TCC0_CCD _SFR_MEM16(0x082E) -#define TCC0_PERBUF _SFR_MEM16(0x0836) -#define TCC0_CCABUF _SFR_MEM16(0x0838) -#define TCC0_CCBBUF _SFR_MEM16(0x083A) -#define TCC0_CCCBUF _SFR_MEM16(0x083C) -#define TCC0_CCDBUF _SFR_MEM16(0x083E) - -/* TC2 - 16-bit Timer/Counter type 2 */ -#define TCC2_CTRLA _SFR_MEM8(0x0800) -#define TCC2_CTRLB _SFR_MEM8(0x0801) -#define TCC2_CTRLC _SFR_MEM8(0x0802) -#define TCC2_CTRLE _SFR_MEM8(0x0804) -#define TCC2_INTCTRLA _SFR_MEM8(0x0806) -#define TCC2_INTCTRLB _SFR_MEM8(0x0807) -#define TCC2_CTRLF _SFR_MEM8(0x0809) -#define TCC2_INTFLAGS _SFR_MEM8(0x080C) -#define TCC2_LCNT _SFR_MEM8(0x0820) -#define TCC2_HCNT _SFR_MEM8(0x0821) -#define TCC2_LPER _SFR_MEM8(0x0826) -#define TCC2_HPER _SFR_MEM8(0x0827) -#define TCC2_LCMPA _SFR_MEM8(0x0828) -#define TCC2_HCMPA _SFR_MEM8(0x0829) -#define TCC2_LCMPB _SFR_MEM8(0x082A) -#define TCC2_HCMPB _SFR_MEM8(0x082B) -#define TCC2_LCMPC _SFR_MEM8(0x082C) -#define TCC2_HCMPC _SFR_MEM8(0x082D) -#define TCC2_LCMPD _SFR_MEM8(0x082E) -#define TCC2_HCMPD _SFR_MEM8(0x082F) - -/* TC1 - 16-bit Timer/Counter 1 */ -#define TCC1_CTRLA _SFR_MEM8(0x0840) -#define TCC1_CTRLB _SFR_MEM8(0x0841) -#define TCC1_CTRLC _SFR_MEM8(0x0842) -#define TCC1_CTRLD _SFR_MEM8(0x0843) -#define TCC1_CTRLE _SFR_MEM8(0x0844) -#define TCC1_INTCTRLA _SFR_MEM8(0x0846) -#define TCC1_INTCTRLB _SFR_MEM8(0x0847) -#define TCC1_CTRLFCLR _SFR_MEM8(0x0848) -#define TCC1_CTRLFSET _SFR_MEM8(0x0849) -#define TCC1_CTRLGCLR _SFR_MEM8(0x084A) -#define TCC1_CTRLGSET _SFR_MEM8(0x084B) -#define TCC1_INTFLAGS _SFR_MEM8(0x084C) -#define TCC1_TEMP _SFR_MEM8(0x084F) -#define TCC1_CNT _SFR_MEM16(0x0860) -#define TCC1_PER _SFR_MEM16(0x0866) -#define TCC1_CCA _SFR_MEM16(0x0868) -#define TCC1_CCB _SFR_MEM16(0x086A) -#define TCC1_PERBUF _SFR_MEM16(0x0876) -#define TCC1_CCABUF _SFR_MEM16(0x0878) -#define TCC1_CCBBUF _SFR_MEM16(0x087A) - -/* AWEX - Advanced Waveform Extension */ -#define AWEXC_CTRL _SFR_MEM8(0x0880) -#define AWEXC_FDEMASK _SFR_MEM8(0x0882) -#define AWEXC_FDCTRL _SFR_MEM8(0x0883) -#define AWEXC_STATUS _SFR_MEM8(0x0884) -#define AWEXC_STATUSSET _SFR_MEM8(0x0885) -#define AWEXC_DTBOTH _SFR_MEM8(0x0886) -#define AWEXC_DTBOTHBUF _SFR_MEM8(0x0887) -#define AWEXC_DTLS _SFR_MEM8(0x0888) -#define AWEXC_DTHS _SFR_MEM8(0x0889) -#define AWEXC_DTLSBUF _SFR_MEM8(0x088A) -#define AWEXC_DTHSBUF _SFR_MEM8(0x088B) -#define AWEXC_OUTOVEN _SFR_MEM8(0x088C) - -/* HIRES - High-Resolution Extension */ -#define HIRESC_CTRLA _SFR_MEM8(0x0890) - -/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ -#define USARTC0_DATA _SFR_MEM8(0x08A0) -#define USARTC0_STATUS _SFR_MEM8(0x08A1) -#define USARTC0_CTRLA _SFR_MEM8(0x08A3) -#define USARTC0_CTRLB _SFR_MEM8(0x08A4) -#define USARTC0_CTRLC _SFR_MEM8(0x08A5) -#define USARTC0_BAUDCTRLA _SFR_MEM8(0x08A6) -#define USARTC0_BAUDCTRLB _SFR_MEM8(0x08A7) - -/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ -#define USARTC1_DATA _SFR_MEM8(0x08B0) -#define USARTC1_STATUS _SFR_MEM8(0x08B1) -#define USARTC1_CTRLA _SFR_MEM8(0x08B3) -#define USARTC1_CTRLB _SFR_MEM8(0x08B4) -#define USARTC1_CTRLC _SFR_MEM8(0x08B5) -#define USARTC1_BAUDCTRLA _SFR_MEM8(0x08B6) -#define USARTC1_BAUDCTRLB _SFR_MEM8(0x08B7) - -/* SPI - Serial Peripheral Interface */ -#define SPIC_CTRL _SFR_MEM8(0x08C0) -#define SPIC_INTCTRL _SFR_MEM8(0x08C1) -#define SPIC_STATUS _SFR_MEM8(0x08C2) -#define SPIC_DATA _SFR_MEM8(0x08C3) - -/* IRCOM - IR Communication Module */ -#define IRCOM_CTRL _SFR_MEM8(0x08F8) -#define IRCOM_TXPLCTRL _SFR_MEM8(0x08F9) -#define IRCOM_RXPLCTRL _SFR_MEM8(0x08FA) - -/* TC0 - 16-bit Timer/Counter 0 */ -#define TCD0_CTRLA _SFR_MEM8(0x0900) -#define TCD0_CTRLB _SFR_MEM8(0x0901) -#define TCD0_CTRLC _SFR_MEM8(0x0902) -#define TCD0_CTRLD _SFR_MEM8(0x0903) -#define TCD0_CTRLE _SFR_MEM8(0x0904) -#define TCD0_INTCTRLA _SFR_MEM8(0x0906) -#define TCD0_INTCTRLB _SFR_MEM8(0x0907) -#define TCD0_CTRLFCLR _SFR_MEM8(0x0908) -#define TCD0_CTRLFSET _SFR_MEM8(0x0909) -#define TCD0_CTRLGCLR _SFR_MEM8(0x090A) -#define TCD0_CTRLGSET _SFR_MEM8(0x090B) -#define TCD0_INTFLAGS _SFR_MEM8(0x090C) -#define TCD0_TEMP _SFR_MEM8(0x090F) -#define TCD0_CNT _SFR_MEM16(0x0920) -#define TCD0_PER _SFR_MEM16(0x0926) -#define TCD0_CCA _SFR_MEM16(0x0928) -#define TCD0_CCB _SFR_MEM16(0x092A) -#define TCD0_CCC _SFR_MEM16(0x092C) -#define TCD0_CCD _SFR_MEM16(0x092E) -#define TCD0_PERBUF _SFR_MEM16(0x0936) -#define TCD0_CCABUF _SFR_MEM16(0x0938) -#define TCD0_CCBBUF _SFR_MEM16(0x093A) -#define TCD0_CCCBUF _SFR_MEM16(0x093C) -#define TCD0_CCDBUF _SFR_MEM16(0x093E) - -/* TC2 - 16-bit Timer/Counter type 2 */ -#define TCD2_CTRLA _SFR_MEM8(0x0900) -#define TCD2_CTRLB _SFR_MEM8(0x0901) -#define TCD2_CTRLC _SFR_MEM8(0x0902) -#define TCD2_CTRLE _SFR_MEM8(0x0904) -#define TCD2_INTCTRLA _SFR_MEM8(0x0906) -#define TCD2_INTCTRLB _SFR_MEM8(0x0907) -#define TCD2_CTRLF _SFR_MEM8(0x0909) -#define TCD2_INTFLAGS _SFR_MEM8(0x090C) -#define TCD2_LCNT _SFR_MEM8(0x0920) -#define TCD2_HCNT _SFR_MEM8(0x0921) -#define TCD2_LPER _SFR_MEM8(0x0926) -#define TCD2_HPER _SFR_MEM8(0x0927) -#define TCD2_LCMPA _SFR_MEM8(0x0928) -#define TCD2_HCMPA _SFR_MEM8(0x0929) -#define TCD2_LCMPB _SFR_MEM8(0x092A) -#define TCD2_HCMPB _SFR_MEM8(0x092B) -#define TCD2_LCMPC _SFR_MEM8(0x092C) -#define TCD2_HCMPC _SFR_MEM8(0x092D) -#define TCD2_LCMPD _SFR_MEM8(0x092E) -#define TCD2_HCMPD _SFR_MEM8(0x092F) - -/* TC1 - 16-bit Timer/Counter 1 */ -#define TCD1_CTRLA _SFR_MEM8(0x0940) -#define TCD1_CTRLB _SFR_MEM8(0x0941) -#define TCD1_CTRLC _SFR_MEM8(0x0942) -#define TCD1_CTRLD _SFR_MEM8(0x0943) -#define TCD1_CTRLE _SFR_MEM8(0x0944) -#define TCD1_INTCTRLA _SFR_MEM8(0x0946) -#define TCD1_INTCTRLB _SFR_MEM8(0x0947) -#define TCD1_CTRLFCLR _SFR_MEM8(0x0948) -#define TCD1_CTRLFSET _SFR_MEM8(0x0949) -#define TCD1_CTRLGCLR _SFR_MEM8(0x094A) -#define TCD1_CTRLGSET _SFR_MEM8(0x094B) -#define TCD1_INTFLAGS _SFR_MEM8(0x094C) -#define TCD1_TEMP _SFR_MEM8(0x094F) -#define TCD1_CNT _SFR_MEM16(0x0960) -#define TCD1_PER _SFR_MEM16(0x0966) -#define TCD1_CCA _SFR_MEM16(0x0968) -#define TCD1_CCB _SFR_MEM16(0x096A) -#define TCD1_PERBUF _SFR_MEM16(0x0976) -#define TCD1_CCABUF _SFR_MEM16(0x0978) -#define TCD1_CCBBUF _SFR_MEM16(0x097A) - -/* HIRES - High-Resolution Extension */ -#define HIRESD_CTRLA _SFR_MEM8(0x0990) - -/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ -#define USARTD0_DATA _SFR_MEM8(0x09A0) -#define USARTD0_STATUS _SFR_MEM8(0x09A1) -#define USARTD0_CTRLA _SFR_MEM8(0x09A3) -#define USARTD0_CTRLB _SFR_MEM8(0x09A4) -#define USARTD0_CTRLC _SFR_MEM8(0x09A5) -#define USARTD0_BAUDCTRLA _SFR_MEM8(0x09A6) -#define USARTD0_BAUDCTRLB _SFR_MEM8(0x09A7) - -/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ -#define USARTD1_DATA _SFR_MEM8(0x09B0) -#define USARTD1_STATUS _SFR_MEM8(0x09B1) -#define USARTD1_CTRLA _SFR_MEM8(0x09B3) -#define USARTD1_CTRLB _SFR_MEM8(0x09B4) -#define USARTD1_CTRLC _SFR_MEM8(0x09B5) -#define USARTD1_BAUDCTRLA _SFR_MEM8(0x09B6) -#define USARTD1_BAUDCTRLB _SFR_MEM8(0x09B7) - -/* SPI - Serial Peripheral Interface */ -#define SPID_CTRL _SFR_MEM8(0x09C0) -#define SPID_INTCTRL _SFR_MEM8(0x09C1) -#define SPID_STATUS _SFR_MEM8(0x09C2) -#define SPID_DATA _SFR_MEM8(0x09C3) - -/* TC0 - 16-bit Timer/Counter 0 */ -#define TCE0_CTRLA _SFR_MEM8(0x0A00) -#define TCE0_CTRLB _SFR_MEM8(0x0A01) -#define TCE0_CTRLC _SFR_MEM8(0x0A02) -#define TCE0_CTRLD _SFR_MEM8(0x0A03) -#define TCE0_CTRLE _SFR_MEM8(0x0A04) -#define TCE0_INTCTRLA _SFR_MEM8(0x0A06) -#define TCE0_INTCTRLB _SFR_MEM8(0x0A07) -#define TCE0_CTRLFCLR _SFR_MEM8(0x0A08) -#define TCE0_CTRLFSET _SFR_MEM8(0x0A09) -#define TCE0_CTRLGCLR _SFR_MEM8(0x0A0A) -#define TCE0_CTRLGSET _SFR_MEM8(0x0A0B) -#define TCE0_INTFLAGS _SFR_MEM8(0x0A0C) -#define TCE0_TEMP _SFR_MEM8(0x0A0F) -#define TCE0_CNT _SFR_MEM16(0x0A20) -#define TCE0_PER _SFR_MEM16(0x0A26) -#define TCE0_CCA _SFR_MEM16(0x0A28) -#define TCE0_CCB _SFR_MEM16(0x0A2A) -#define TCE0_CCC _SFR_MEM16(0x0A2C) -#define TCE0_CCD _SFR_MEM16(0x0A2E) -#define TCE0_PERBUF _SFR_MEM16(0x0A36) -#define TCE0_CCABUF _SFR_MEM16(0x0A38) -#define TCE0_CCBBUF _SFR_MEM16(0x0A3A) -#define TCE0_CCCBUF _SFR_MEM16(0x0A3C) -#define TCE0_CCDBUF _SFR_MEM16(0x0A3E) - -/* TC2 - 16-bit Timer/Counter type 2 */ -#define TCE2_CTRLA _SFR_MEM8(0x0A00) -#define TCE2_CTRLB _SFR_MEM8(0x0A01) -#define TCE2_CTRLC _SFR_MEM8(0x0A02) -#define TCE2_CTRLE _SFR_MEM8(0x0A04) -#define TCE2_INTCTRLA _SFR_MEM8(0x0A06) -#define TCE2_INTCTRLB _SFR_MEM8(0x0A07) -#define TCE2_CTRLF _SFR_MEM8(0x0A09) -#define TCE2_INTFLAGS _SFR_MEM8(0x0A0C) -#define TCE2_LCNT _SFR_MEM8(0x0A20) -#define TCE2_HCNT _SFR_MEM8(0x0A21) -#define TCE2_LPER _SFR_MEM8(0x0A26) -#define TCE2_HPER _SFR_MEM8(0x0A27) -#define TCE2_LCMPA _SFR_MEM8(0x0A28) -#define TCE2_HCMPA _SFR_MEM8(0x0A29) -#define TCE2_LCMPB _SFR_MEM8(0x0A2A) -#define TCE2_HCMPB _SFR_MEM8(0x0A2B) -#define TCE2_LCMPC _SFR_MEM8(0x0A2C) -#define TCE2_HCMPC _SFR_MEM8(0x0A2D) -#define TCE2_LCMPD _SFR_MEM8(0x0A2E) -#define TCE2_HCMPD _SFR_MEM8(0x0A2F) - -/* TC1 - 16-bit Timer/Counter 1 */ -#define TCE1_CTRLA _SFR_MEM8(0x0A40) -#define TCE1_CTRLB _SFR_MEM8(0x0A41) -#define TCE1_CTRLC _SFR_MEM8(0x0A42) -#define TCE1_CTRLD _SFR_MEM8(0x0A43) -#define TCE1_CTRLE _SFR_MEM8(0x0A44) -#define TCE1_INTCTRLA _SFR_MEM8(0x0A46) -#define TCE1_INTCTRLB _SFR_MEM8(0x0A47) -#define TCE1_CTRLFCLR _SFR_MEM8(0x0A48) -#define TCE1_CTRLFSET _SFR_MEM8(0x0A49) -#define TCE1_CTRLGCLR _SFR_MEM8(0x0A4A) -#define TCE1_CTRLGSET _SFR_MEM8(0x0A4B) -#define TCE1_INTFLAGS _SFR_MEM8(0x0A4C) -#define TCE1_TEMP _SFR_MEM8(0x0A4F) -#define TCE1_CNT _SFR_MEM16(0x0A60) -#define TCE1_PER _SFR_MEM16(0x0A66) -#define TCE1_CCA _SFR_MEM16(0x0A68) -#define TCE1_CCB _SFR_MEM16(0x0A6A) -#define TCE1_PERBUF _SFR_MEM16(0x0A76) -#define TCE1_CCABUF _SFR_MEM16(0x0A78) -#define TCE1_CCBBUF _SFR_MEM16(0x0A7A) - -/* AWEX - Advanced Waveform Extension */ -#define AWEXE_CTRL _SFR_MEM8(0x0A80) -#define AWEXE_FDEMASK _SFR_MEM8(0x0A82) -#define AWEXE_FDCTRL _SFR_MEM8(0x0A83) -#define AWEXE_STATUS _SFR_MEM8(0x0A84) -#define AWEXE_STATUSSET _SFR_MEM8(0x0A85) -#define AWEXE_DTBOTH _SFR_MEM8(0x0A86) -#define AWEXE_DTBOTHBUF _SFR_MEM8(0x0A87) -#define AWEXE_DTLS _SFR_MEM8(0x0A88) -#define AWEXE_DTHS _SFR_MEM8(0x0A89) -#define AWEXE_DTLSBUF _SFR_MEM8(0x0A8A) -#define AWEXE_DTHSBUF _SFR_MEM8(0x0A8B) -#define AWEXE_OUTOVEN _SFR_MEM8(0x0A8C) - -/* HIRES - High-Resolution Extension */ -#define HIRESE_CTRLA _SFR_MEM8(0x0A90) - -/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ -#define USARTE0_DATA _SFR_MEM8(0x0AA0) -#define USARTE0_STATUS _SFR_MEM8(0x0AA1) -#define USARTE0_CTRLA _SFR_MEM8(0x0AA3) -#define USARTE0_CTRLB _SFR_MEM8(0x0AA4) -#define USARTE0_CTRLC _SFR_MEM8(0x0AA5) -#define USARTE0_BAUDCTRLA _SFR_MEM8(0x0AA6) -#define USARTE0_BAUDCTRLB _SFR_MEM8(0x0AA7) - -/* TC0 - 16-bit Timer/Counter 0 */ -#define TCF0_CTRLA _SFR_MEM8(0x0B00) -#define TCF0_CTRLB _SFR_MEM8(0x0B01) -#define TCF0_CTRLC _SFR_MEM8(0x0B02) -#define TCF0_CTRLD _SFR_MEM8(0x0B03) -#define TCF0_CTRLE _SFR_MEM8(0x0B04) -#define TCF0_INTCTRLA _SFR_MEM8(0x0B06) -#define TCF0_INTCTRLB _SFR_MEM8(0x0B07) -#define TCF0_CTRLFCLR _SFR_MEM8(0x0B08) -#define TCF0_CTRLFSET _SFR_MEM8(0x0B09) -#define TCF0_CTRLGCLR _SFR_MEM8(0x0B0A) -#define TCF0_CTRLGSET _SFR_MEM8(0x0B0B) -#define TCF0_INTFLAGS _SFR_MEM8(0x0B0C) -#define TCF0_TEMP _SFR_MEM8(0x0B0F) -#define TCF0_CNT _SFR_MEM16(0x0B20) -#define TCF0_PER _SFR_MEM16(0x0B26) -#define TCF0_CCA _SFR_MEM16(0x0B28) -#define TCF0_CCB _SFR_MEM16(0x0B2A) -#define TCF0_CCC _SFR_MEM16(0x0B2C) -#define TCF0_CCD _SFR_MEM16(0x0B2E) -#define TCF0_PERBUF _SFR_MEM16(0x0B36) -#define TCF0_CCABUF _SFR_MEM16(0x0B38) -#define TCF0_CCBBUF _SFR_MEM16(0x0B3A) -#define TCF0_CCCBUF _SFR_MEM16(0x0B3C) -#define TCF0_CCDBUF _SFR_MEM16(0x0B3E) - -/* TC2 - 16-bit Timer/Counter type 2 */ -#define TCF2_CTRLA _SFR_MEM8(0x0B00) -#define TCF2_CTRLB _SFR_MEM8(0x0B01) -#define TCF2_CTRLC _SFR_MEM8(0x0B02) -#define TCF2_CTRLE _SFR_MEM8(0x0B04) -#define TCF2_INTCTRLA _SFR_MEM8(0x0B06) -#define TCF2_INTCTRLB _SFR_MEM8(0x0B07) -#define TCF2_CTRLF _SFR_MEM8(0x0B09) -#define TCF2_INTFLAGS _SFR_MEM8(0x0B0C) -#define TCF2_LCNT _SFR_MEM8(0x0B20) -#define TCF2_HCNT _SFR_MEM8(0x0B21) -#define TCF2_LPER _SFR_MEM8(0x0B26) -#define TCF2_HPER _SFR_MEM8(0x0B27) -#define TCF2_LCMPA _SFR_MEM8(0x0B28) -#define TCF2_HCMPA _SFR_MEM8(0x0B29) -#define TCF2_LCMPB _SFR_MEM8(0x0B2A) -#define TCF2_HCMPB _SFR_MEM8(0x0B2B) -#define TCF2_LCMPC _SFR_MEM8(0x0B2C) -#define TCF2_HCMPC _SFR_MEM8(0x0B2D) -#define TCF2_LCMPD _SFR_MEM8(0x0B2E) -#define TCF2_HCMPD _SFR_MEM8(0x0B2F) - -/* HIRES - High-Resolution Extension */ -#define HIRESF_CTRLA _SFR_MEM8(0x0B90) - -/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ -#define USARTF0_DATA _SFR_MEM8(0x0BA0) -#define USARTF0_STATUS _SFR_MEM8(0x0BA1) -#define USARTF0_CTRLA _SFR_MEM8(0x0BA3) -#define USARTF0_CTRLB _SFR_MEM8(0x0BA4) -#define USARTF0_CTRLC _SFR_MEM8(0x0BA5) -#define USARTF0_BAUDCTRLA _SFR_MEM8(0x0BA6) -#define USARTF0_BAUDCTRLB _SFR_MEM8(0x0BA7) - - - -/*================== Bitfield Definitions ================== */ - -/* VPORT - Virtual Ports */ -/* VPORT.INTFLAGS bit masks and bit positions */ -#define VPORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ -#define VPORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ - -#define VPORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ -#define VPORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ - -/* XOCD - On-Chip Debug System */ -/* OCD.OCDR0 bit masks and bit positions */ -#define OCD_OCDRD_gm 0xFF /* OCDR Dirty group mask. */ -#define OCD_OCDRD_gp 0 /* OCDR Dirty group position. */ -#define OCD_OCDRD0_bm (1<<0) /* OCDR Dirty bit 0 mask. */ -#define OCD_OCDRD0_bp 0 /* OCDR Dirty bit 0 position. */ -#define OCD_OCDRD1_bm (1<<1) /* OCDR Dirty bit 1 mask. */ -#define OCD_OCDRD1_bp 1 /* OCDR Dirty bit 1 position. */ -#define OCD_OCDRD2_bm (1<<2) /* OCDR Dirty bit 2 mask. */ -#define OCD_OCDRD2_bp 2 /* OCDR Dirty bit 2 position. */ -#define OCD_OCDRD3_bm (1<<3) /* OCDR Dirty bit 3 mask. */ -#define OCD_OCDRD3_bp 3 /* OCDR Dirty bit 3 position. */ -#define OCD_OCDRD4_bm (1<<4) /* OCDR Dirty bit 4 mask. */ -#define OCD_OCDRD4_bp 4 /* OCDR Dirty bit 4 position. */ -#define OCD_OCDRD5_bm (1<<5) /* OCDR Dirty bit 5 mask. */ -#define OCD_OCDRD5_bp 5 /* OCDR Dirty bit 5 position. */ -#define OCD_OCDRD6_bm (1<<6) /* OCDR Dirty bit 6 mask. */ -#define OCD_OCDRD6_bp 6 /* OCDR Dirty bit 6 position. */ -#define OCD_OCDRD7_bm (1<<7) /* OCDR Dirty bit 7 mask. */ -#define OCD_OCDRD7_bp 7 /* OCDR Dirty bit 7 position. */ - -/* OCD.OCDR1 bit masks and bit positions */ -/* OCD_OCDRD Predefined. */ -/* OCD_OCDRD Predefined. */ - -/* CPU - CPU */ -/* CPU.CCP bit masks and bit positions */ -#define CPU_CCP_gm 0xFF /* CCP signature group mask. */ -#define CPU_CCP_gp 0 /* CCP signature group position. */ -#define CPU_CCP0_bm (1<<0) /* CCP signature bit 0 mask. */ -#define CPU_CCP0_bp 0 /* CCP signature bit 0 position. */ -#define CPU_CCP1_bm (1<<1) /* CCP signature bit 1 mask. */ -#define CPU_CCP1_bp 1 /* CCP signature bit 1 position. */ -#define CPU_CCP2_bm (1<<2) /* CCP signature bit 2 mask. */ -#define CPU_CCP2_bp 2 /* CCP signature bit 2 position. */ -#define CPU_CCP3_bm (1<<3) /* CCP signature bit 3 mask. */ -#define CPU_CCP3_bp 3 /* CCP signature bit 3 position. */ -#define CPU_CCP4_bm (1<<4) /* CCP signature bit 4 mask. */ -#define CPU_CCP4_bp 4 /* CCP signature bit 4 position. */ -#define CPU_CCP5_bm (1<<5) /* CCP signature bit 5 mask. */ -#define CPU_CCP5_bp 5 /* CCP signature bit 5 position. */ -#define CPU_CCP6_bm (1<<6) /* CCP signature bit 6 mask. */ -#define CPU_CCP6_bp 6 /* CCP signature bit 6 position. */ -#define CPU_CCP7_bm (1<<7) /* CCP signature bit 7 mask. */ -#define CPU_CCP7_bp 7 /* CCP signature bit 7 position. */ - -/* CPU.SREG bit masks and bit positions */ -#define CPU_I_bm 0x80 /* Global Interrupt Enable Flag bit mask. */ -#define CPU_I_bp 7 /* Global Interrupt Enable Flag bit position. */ - -#define CPU_T_bm 0x40 /* Transfer Bit bit mask. */ -#define CPU_T_bp 6 /* Transfer Bit bit position. */ - -#define CPU_H_bm 0x20 /* Half Carry Flag bit mask. */ -#define CPU_H_bp 5 /* Half Carry Flag bit position. */ - -#define CPU_S_bm 0x10 /* N Exclusive Or V Flag bit mask. */ -#define CPU_S_bp 4 /* N Exclusive Or V Flag bit position. */ - -#define CPU_V_bm 0x08 /* Two's Complement Overflow Flag bit mask. */ -#define CPU_V_bp 3 /* Two's Complement Overflow Flag bit position. */ - -#define CPU_N_bm 0x04 /* Negative Flag bit mask. */ -#define CPU_N_bp 2 /* Negative Flag bit position. */ - -#define CPU_Z_bm 0x02 /* Zero Flag bit mask. */ -#define CPU_Z_bp 1 /* Zero Flag bit position. */ - -#define CPU_C_bm 0x01 /* Carry Flag bit mask. */ -#define CPU_C_bp 0 /* Carry Flag bit position. */ - -/* CLK - Clock System */ -/* CLK.CTRL bit masks and bit positions */ -#define CLK_SCLKSEL_gm 0x07 /* System Clock Selection group mask. */ -#define CLK_SCLKSEL_gp 0 /* System Clock Selection group position. */ -#define CLK_SCLKSEL0_bm (1<<0) /* System Clock Selection bit 0 mask. */ -#define CLK_SCLKSEL0_bp 0 /* System Clock Selection bit 0 position. */ -#define CLK_SCLKSEL1_bm (1<<1) /* System Clock Selection bit 1 mask. */ -#define CLK_SCLKSEL1_bp 1 /* System Clock Selection bit 1 position. */ -#define CLK_SCLKSEL2_bm (1<<2) /* System Clock Selection bit 2 mask. */ -#define CLK_SCLKSEL2_bp 2 /* System Clock Selection bit 2 position. */ - -/* CLK.PSCTRL bit masks and bit positions */ -#define CLK_PSADIV_gm 0x7C /* Prescaler A Division Factor group mask. */ -#define CLK_PSADIV_gp 2 /* Prescaler A Division Factor group position. */ -#define CLK_PSADIV0_bm (1<<2) /* Prescaler A Division Factor bit 0 mask. */ -#define CLK_PSADIV0_bp 2 /* Prescaler A Division Factor bit 0 position. */ -#define CLK_PSADIV1_bm (1<<3) /* Prescaler A Division Factor bit 1 mask. */ -#define CLK_PSADIV1_bp 3 /* Prescaler A Division Factor bit 1 position. */ -#define CLK_PSADIV2_bm (1<<4) /* Prescaler A Division Factor bit 2 mask. */ -#define CLK_PSADIV2_bp 4 /* Prescaler A Division Factor bit 2 position. */ -#define CLK_PSADIV3_bm (1<<5) /* Prescaler A Division Factor bit 3 mask. */ -#define CLK_PSADIV3_bp 5 /* Prescaler A Division Factor bit 3 position. */ -#define CLK_PSADIV4_bm (1<<6) /* Prescaler A Division Factor bit 4 mask. */ -#define CLK_PSADIV4_bp 6 /* Prescaler A Division Factor bit 4 position. */ - -#define CLK_PSBCDIV_gm 0x03 /* Prescaler B and C Division factor group mask. */ -#define CLK_PSBCDIV_gp 0 /* Prescaler B and C Division factor group position. */ -#define CLK_PSBCDIV0_bm (1<<0) /* Prescaler B and C Division factor bit 0 mask. */ -#define CLK_PSBCDIV0_bp 0 /* Prescaler B and C Division factor bit 0 position. */ -#define CLK_PSBCDIV1_bm (1<<1) /* Prescaler B and C Division factor bit 1 mask. */ -#define CLK_PSBCDIV1_bp 1 /* Prescaler B and C Division factor bit 1 position. */ - -/* CLK.LOCK bit masks and bit positions */ -#define CLK_LOCK_bm 0x01 /* Clock System Lock bit mask. */ -#define CLK_LOCK_bp 0 /* Clock System Lock bit position. */ - -/* CLK.RTCCTRL bit masks and bit positions */ -#define CLK_RTCSRC_gm 0x0E /* Clock Source group mask. */ -#define CLK_RTCSRC_gp 1 /* Clock Source group position. */ -#define CLK_RTCSRC0_bm (1<<1) /* Clock Source bit 0 mask. */ -#define CLK_RTCSRC0_bp 1 /* Clock Source bit 0 position. */ -#define CLK_RTCSRC1_bm (1<<2) /* Clock Source bit 1 mask. */ -#define CLK_RTCSRC1_bp 2 /* Clock Source bit 1 position. */ -#define CLK_RTCSRC2_bm (1<<3) /* Clock Source bit 2 mask. */ -#define CLK_RTCSRC2_bp 3 /* Clock Source bit 2 position. */ - -#define CLK_RTCEN_bm 0x01 /* Clock Source Enable bit mask. */ -#define CLK_RTCEN_bp 0 /* Clock Source Enable bit position. */ - -/* CLK.USBCTRL bit masks and bit positions */ -#define CLK_USBPSDIV_gm 0x38 /* Prescaler Division Factor group mask. */ -#define CLK_USBPSDIV_gp 3 /* Prescaler Division Factor group position. */ -#define CLK_USBPSDIV0_bm (1<<3) /* Prescaler Division Factor bit 0 mask. */ -#define CLK_USBPSDIV0_bp 3 /* Prescaler Division Factor bit 0 position. */ -#define CLK_USBPSDIV1_bm (1<<4) /* Prescaler Division Factor bit 1 mask. */ -#define CLK_USBPSDIV1_bp 4 /* Prescaler Division Factor bit 1 position. */ -#define CLK_USBPSDIV2_bm (1<<5) /* Prescaler Division Factor bit 2 mask. */ -#define CLK_USBPSDIV2_bp 5 /* Prescaler Division Factor bit 2 position. */ - -#define CLK_USBSRC_gm 0x06 /* Clock Source group mask. */ -#define CLK_USBSRC_gp 1 /* Clock Source group position. */ -#define CLK_USBSRC0_bm (1<<1) /* Clock Source bit 0 mask. */ -#define CLK_USBSRC0_bp 1 /* Clock Source bit 0 position. */ -#define CLK_USBSRC1_bm (1<<2) /* Clock Source bit 1 mask. */ -#define CLK_USBSRC1_bp 2 /* Clock Source bit 1 position. */ - -#define CLK_USBSEN_bm 0x01 /* Clock Source Enable bit mask. */ -#define CLK_USBSEN_bp 0 /* Clock Source Enable bit position. */ - -/* PR.PRGEN bit masks and bit positions */ -#define PR_USB_bm 0x40 /* USB bit mask. */ -#define PR_USB_bp 6 /* USB bit position. */ - -#define PR_AES_bm 0x10 /* AES bit mask. */ -#define PR_AES_bp 4 /* AES bit position. */ - -#define PR_EBI_bm 0x08 /* External Bus Interface bit mask. */ -#define PR_EBI_bp 3 /* External Bus Interface bit position. */ - -#define PR_RTC_bm 0x04 /* Real-time Counter bit mask. */ -#define PR_RTC_bp 2 /* Real-time Counter bit position. */ - -#define PR_EVSYS_bm 0x02 /* Event System bit mask. */ -#define PR_EVSYS_bp 1 /* Event System bit position. */ - -#define PR_DMA_bm 0x01 /* DMA-Controller bit mask. */ -#define PR_DMA_bp 0 /* DMA-Controller bit position. */ - -/* PR.PRPA bit masks and bit positions */ -#define PR_DAC_bm 0x04 /* Port A DAC bit mask. */ -#define PR_DAC_bp 2 /* Port A DAC bit position. */ - -#define PR_ADC_bm 0x02 /* Port A ADC bit mask. */ -#define PR_ADC_bp 1 /* Port A ADC bit position. */ - -#define PR_AC_bm 0x01 /* Port A Analog Comparator bit mask. */ -#define PR_AC_bp 0 /* Port A Analog Comparator bit position. */ - -/* PR.PRPB bit masks and bit positions */ -/* PR_DAC Predefined. */ -/* PR_DAC Predefined. */ - -/* PR_ADC Predefined. */ -/* PR_ADC Predefined. */ - -/* PR_AC Predefined. */ -/* PR_AC Predefined. */ - -/* PR.PRPC bit masks and bit positions */ -#define PR_TWI_bm 0x40 /* Port C Two-wire Interface bit mask. */ -#define PR_TWI_bp 6 /* Port C Two-wire Interface bit position. */ - -#define PR_USART1_bm 0x20 /* Port C USART1 bit mask. */ -#define PR_USART1_bp 5 /* Port C USART1 bit position. */ - -#define PR_USART0_bm 0x10 /* Port C USART0 bit mask. */ -#define PR_USART0_bp 4 /* Port C USART0 bit position. */ - -#define PR_SPI_bm 0x08 /* Port C SPI bit mask. */ -#define PR_SPI_bp 3 /* Port C SPI bit position. */ - -#define PR_HIRES_bm 0x04 /* Port C AWEX bit mask. */ -#define PR_HIRES_bp 2 /* Port C AWEX bit position. */ - -#define PR_TC1_bm 0x02 /* Port C Timer/Counter1 bit mask. */ -#define PR_TC1_bp 1 /* Port C Timer/Counter1 bit position. */ - -#define PR_TC0_bm 0x01 /* Port C Timer/Counter0 bit mask. */ -#define PR_TC0_bp 0 /* Port C Timer/Counter0 bit position. */ - -/* PR.PRPD bit masks and bit positions */ -/* PR_TWI Predefined. */ -/* PR_TWI Predefined. */ - -/* PR_USART1 Predefined. */ -/* PR_USART1 Predefined. */ - -/* PR_USART0 Predefined. */ -/* PR_USART0 Predefined. */ - -/* PR_SPI Predefined. */ -/* PR_SPI Predefined. */ - -/* PR_HIRES Predefined. */ -/* PR_HIRES Predefined. */ - -/* PR_TC1 Predefined. */ -/* PR_TC1 Predefined. */ - -/* PR_TC0 Predefined. */ -/* PR_TC0 Predefined. */ - -/* PR.PRPE bit masks and bit positions */ -/* PR_TWI Predefined. */ -/* PR_TWI Predefined. */ - -/* PR_USART1 Predefined. */ -/* PR_USART1 Predefined. */ - -/* PR_USART0 Predefined. */ -/* PR_USART0 Predefined. */ - -/* PR_SPI Predefined. */ -/* PR_SPI Predefined. */ - -/* PR_HIRES Predefined. */ -/* PR_HIRES Predefined. */ - -/* PR_TC1 Predefined. */ -/* PR_TC1 Predefined. */ - -/* PR_TC0 Predefined. */ -/* PR_TC0 Predefined. */ - -/* PR.PRPF bit masks and bit positions */ -/* PR_TWI Predefined. */ -/* PR_TWI Predefined. */ - -/* PR_USART1 Predefined. */ -/* PR_USART1 Predefined. */ - -/* PR_USART0 Predefined. */ -/* PR_USART0 Predefined. */ - -/* PR_SPI Predefined. */ -/* PR_SPI Predefined. */ - -/* PR_HIRES Predefined. */ -/* PR_HIRES Predefined. */ - -/* PR_TC1 Predefined. */ -/* PR_TC1 Predefined. */ - -/* PR_TC0 Predefined. */ -/* PR_TC0 Predefined. */ - -/* SLEEP - Sleep Controller */ -/* SLEEP.CTRL bit masks and bit positions */ -#define SLEEP_SMODE_gm 0x0E /* Sleep Mode group mask. */ -#define SLEEP_SMODE_gp 1 /* Sleep Mode group position. */ -#define SLEEP_SMODE0_bm (1<<1) /* Sleep Mode bit 0 mask. */ -#define SLEEP_SMODE0_bp 1 /* Sleep Mode bit 0 position. */ -#define SLEEP_SMODE1_bm (1<<2) /* Sleep Mode bit 1 mask. */ -#define SLEEP_SMODE1_bp 2 /* Sleep Mode bit 1 position. */ -#define SLEEP_SMODE2_bm (1<<3) /* Sleep Mode bit 2 mask. */ -#define SLEEP_SMODE2_bp 3 /* Sleep Mode bit 2 position. */ - -#define SLEEP_SEN_bm 0x01 /* Sleep Enable bit mask. */ -#define SLEEP_SEN_bp 0 /* Sleep Enable bit position. */ - -/* OSC - Oscillator */ -/* OSC.CTRL bit masks and bit positions */ -#define OSC_PLLEN_bm 0x10 /* PLL Enable bit mask. */ -#define OSC_PLLEN_bp 4 /* PLL Enable bit position. */ - -#define OSC_XOSCEN_bm 0x08 /* External Oscillator Enable bit mask. */ -#define OSC_XOSCEN_bp 3 /* External Oscillator Enable bit position. */ - -#define OSC_RC32KEN_bm 0x04 /* Internal 32.768 kHz RC Oscillator Enable bit mask. */ -#define OSC_RC32KEN_bp 2 /* Internal 32.768 kHz RC Oscillator Enable bit position. */ - -#define OSC_RC32MEN_bm 0x02 /* Internal 32 MHz RC Oscillator Enable bit mask. */ -#define OSC_RC32MEN_bp 1 /* Internal 32 MHz RC Oscillator Enable bit position. */ - -#define OSC_RC2MEN_bm 0x01 /* Internal 2 MHz RC Oscillator Enable bit mask. */ -#define OSC_RC2MEN_bp 0 /* Internal 2 MHz RC Oscillator Enable bit position. */ - -/* OSC.STATUS bit masks and bit positions */ -#define OSC_PLLRDY_bm 0x10 /* PLL Ready bit mask. */ -#define OSC_PLLRDY_bp 4 /* PLL Ready bit position. */ - -#define OSC_XOSCRDY_bm 0x08 /* External Oscillator Ready bit mask. */ -#define OSC_XOSCRDY_bp 3 /* External Oscillator Ready bit position. */ - -#define OSC_RC32KRDY_bm 0x04 /* Internal 32.768 kHz RC Oscillator Ready bit mask. */ -#define OSC_RC32KRDY_bp 2 /* Internal 32.768 kHz RC Oscillator Ready bit position. */ - -#define OSC_RC32MRDY_bm 0x02 /* Internal 32 MHz RC Oscillator Ready bit mask. */ -#define OSC_RC32MRDY_bp 1 /* Internal 32 MHz RC Oscillator Ready bit position. */ - -#define OSC_RC2MRDY_bm 0x01 /* Internal 2 MHz RC Oscillator Ready bit mask. */ -#define OSC_RC2MRDY_bp 0 /* Internal 2 MHz RC Oscillator Ready bit position. */ - -/* OSC.XOSCCTRL bit masks and bit positions */ -#define OSC_FRQRANGE_gm 0xC0 /* Frequency Range group mask. */ -#define OSC_FRQRANGE_gp 6 /* Frequency Range group position. */ -#define OSC_FRQRANGE0_bm (1<<6) /* Frequency Range bit 0 mask. */ -#define OSC_FRQRANGE0_bp 6 /* Frequency Range bit 0 position. */ -#define OSC_FRQRANGE1_bm (1<<7) /* Frequency Range bit 1 mask. */ -#define OSC_FRQRANGE1_bp 7 /* Frequency Range bit 1 position. */ - -#define OSC_X32KLPM_bm 0x20 /* 32.768 kHz XTAL OSC Low-power Mode bit mask. */ -#define OSC_X32KLPM_bp 5 /* 32.768 kHz XTAL OSC Low-power Mode bit position. */ - -#define OSC_XOSCPWR_bm 0x10 /* 16 MHz Crystal Oscillator High Power mode bit mask. */ -#define OSC_XOSCPWR_bp 4 /* 16 MHz Crystal Oscillator High Power mode bit position. */ - -#define OSC_XOSCSEL_gm 0x0F /* External Oscillator Selection and Startup Time group mask. */ -#define OSC_XOSCSEL_gp 0 /* External Oscillator Selection and Startup Time group position. */ -#define OSC_XOSCSEL0_bm (1<<0) /* External Oscillator Selection and Startup Time bit 0 mask. */ -#define OSC_XOSCSEL0_bp 0 /* External Oscillator Selection and Startup Time bit 0 position. */ -#define OSC_XOSCSEL1_bm (1<<1) /* External Oscillator Selection and Startup Time bit 1 mask. */ -#define OSC_XOSCSEL1_bp 1 /* External Oscillator Selection and Startup Time bit 1 position. */ -#define OSC_XOSCSEL2_bm (1<<2) /* External Oscillator Selection and Startup Time bit 2 mask. */ -#define OSC_XOSCSEL2_bp 2 /* External Oscillator Selection and Startup Time bit 2 position. */ -#define OSC_XOSCSEL3_bm (1<<3) /* External Oscillator Selection and Startup Time bit 3 mask. */ -#define OSC_XOSCSEL3_bp 3 /* External Oscillator Selection and Startup Time bit 3 position. */ - -/* OSC.XOSCFAIL bit masks and bit positions */ -#define OSC_PLLFDIF_bm 0x08 /* PLL Failure Detection Interrupt Flag bit mask. */ -#define OSC_PLLFDIF_bp 3 /* PLL Failure Detection Interrupt Flag bit position. */ - -#define OSC_PLLFDEN_bm 0x04 /* PLL Failure Detection Enable bit mask. */ -#define OSC_PLLFDEN_bp 2 /* PLL Failure Detection Enable bit position. */ - -#define OSC_XOSCFDIF_bm 0x02 /* XOSC Failure Detection Interrupt Flag bit mask. */ -#define OSC_XOSCFDIF_bp 1 /* XOSC Failure Detection Interrupt Flag bit position. */ - -#define OSC_XOSCFDEN_bm 0x01 /* XOSC Failure Detection Enable bit mask. */ -#define OSC_XOSCFDEN_bp 0 /* XOSC Failure Detection Enable bit position. */ - -/* OSC.PLLCTRL bit masks and bit positions */ -#define OSC_PLLSRC_gm 0xC0 /* Clock Source group mask. */ -#define OSC_PLLSRC_gp 6 /* Clock Source group position. */ -#define OSC_PLLSRC0_bm (1<<6) /* Clock Source bit 0 mask. */ -#define OSC_PLLSRC0_bp 6 /* Clock Source bit 0 position. */ -#define OSC_PLLSRC1_bm (1<<7) /* Clock Source bit 1 mask. */ -#define OSC_PLLSRC1_bp 7 /* Clock Source bit 1 position. */ - -#define OSC_PLLDIV_bm 0x20 /* Divide by 2 bit mask. */ -#define OSC_PLLDIV_bp 5 /* Divide by 2 bit position. */ - -#define OSC_PLLFAC_gm 0x1F /* Multiplication Factor group mask. */ -#define OSC_PLLFAC_gp 0 /* Multiplication Factor group position. */ -#define OSC_PLLFAC0_bm (1<<0) /* Multiplication Factor bit 0 mask. */ -#define OSC_PLLFAC0_bp 0 /* Multiplication Factor bit 0 position. */ -#define OSC_PLLFAC1_bm (1<<1) /* Multiplication Factor bit 1 mask. */ -#define OSC_PLLFAC1_bp 1 /* Multiplication Factor bit 1 position. */ -#define OSC_PLLFAC2_bm (1<<2) /* Multiplication Factor bit 2 mask. */ -#define OSC_PLLFAC2_bp 2 /* Multiplication Factor bit 2 position. */ -#define OSC_PLLFAC3_bm (1<<3) /* Multiplication Factor bit 3 mask. */ -#define OSC_PLLFAC3_bp 3 /* Multiplication Factor bit 3 position. */ -#define OSC_PLLFAC4_bm (1<<4) /* Multiplication Factor bit 4 mask. */ -#define OSC_PLLFAC4_bp 4 /* Multiplication Factor bit 4 position. */ - -/* OSC.DFLLCTRL bit masks and bit positions */ -#define OSC_RC32MCREF_gm 0x06 /* 32 MHz DFLL Calibration Reference group mask. */ -#define OSC_RC32MCREF_gp 1 /* 32 MHz DFLL Calibration Reference group position. */ -#define OSC_RC32MCREF0_bm (1<<1) /* 32 MHz DFLL Calibration Reference bit 0 mask. */ -#define OSC_RC32MCREF0_bp 1 /* 32 MHz DFLL Calibration Reference bit 0 position. */ -#define OSC_RC32MCREF1_bm (1<<2) /* 32 MHz DFLL Calibration Reference bit 1 mask. */ -#define OSC_RC32MCREF1_bp 2 /* 32 MHz DFLL Calibration Reference bit 1 position. */ - -#define OSC_RC2MCREF_bm 0x01 /* 2 MHz DFLL Calibration Reference bit mask. */ -#define OSC_RC2MCREF_bp 0 /* 2 MHz DFLL Calibration Reference bit position. */ - -/* DFLL - DFLL */ -/* DFLL.CTRL bit masks and bit positions */ -#define DFLL_ENABLE_bm 0x01 /* DFLL Enable bit mask. */ -#define DFLL_ENABLE_bp 0 /* DFLL Enable bit position. */ - -/* DFLL.CALA bit masks and bit positions */ -#define DFLL_CALL_gm 0x7F /* DFLL Calibration Value A group mask. */ -#define DFLL_CALL_gp 0 /* DFLL Calibration Value A group position. */ -#define DFLL_CALL0_bm (1<<0) /* DFLL Calibration Value A bit 0 mask. */ -#define DFLL_CALL0_bp 0 /* DFLL Calibration Value A bit 0 position. */ -#define DFLL_CALL1_bm (1<<1) /* DFLL Calibration Value A bit 1 mask. */ -#define DFLL_CALL1_bp 1 /* DFLL Calibration Value A bit 1 position. */ -#define DFLL_CALL2_bm (1<<2) /* DFLL Calibration Value A bit 2 mask. */ -#define DFLL_CALL2_bp 2 /* DFLL Calibration Value A bit 2 position. */ -#define DFLL_CALL3_bm (1<<3) /* DFLL Calibration Value A bit 3 mask. */ -#define DFLL_CALL3_bp 3 /* DFLL Calibration Value A bit 3 position. */ -#define DFLL_CALL4_bm (1<<4) /* DFLL Calibration Value A bit 4 mask. */ -#define DFLL_CALL4_bp 4 /* DFLL Calibration Value A bit 4 position. */ -#define DFLL_CALL5_bm (1<<5) /* DFLL Calibration Value A bit 5 mask. */ -#define DFLL_CALL5_bp 5 /* DFLL Calibration Value A bit 5 position. */ -#define DFLL_CALL6_bm (1<<6) /* DFLL Calibration Value A bit 6 mask. */ -#define DFLL_CALL6_bp 6 /* DFLL Calibration Value A bit 6 position. */ - -/* DFLL.CALB bit masks and bit positions */ -#define DFLL_CALH_gm 0x3F /* DFLL Calibration Value B group mask. */ -#define DFLL_CALH_gp 0 /* DFLL Calibration Value B group position. */ -#define DFLL_CALH0_bm (1<<0) /* DFLL Calibration Value B bit 0 mask. */ -#define DFLL_CALH0_bp 0 /* DFLL Calibration Value B bit 0 position. */ -#define DFLL_CALH1_bm (1<<1) /* DFLL Calibration Value B bit 1 mask. */ -#define DFLL_CALH1_bp 1 /* DFLL Calibration Value B bit 1 position. */ -#define DFLL_CALH2_bm (1<<2) /* DFLL Calibration Value B bit 2 mask. */ -#define DFLL_CALH2_bp 2 /* DFLL Calibration Value B bit 2 position. */ -#define DFLL_CALH3_bm (1<<3) /* DFLL Calibration Value B bit 3 mask. */ -#define DFLL_CALH3_bp 3 /* DFLL Calibration Value B bit 3 position. */ -#define DFLL_CALH4_bm (1<<4) /* DFLL Calibration Value B bit 4 mask. */ -#define DFLL_CALH4_bp 4 /* DFLL Calibration Value B bit 4 position. */ -#define DFLL_CALH5_bm (1<<5) /* DFLL Calibration Value B bit 5 mask. */ -#define DFLL_CALH5_bp 5 /* DFLL Calibration Value B bit 5 position. */ - -/* RST - Reset */ -/* RST.STATUS bit masks and bit positions */ -#define RST_SDRF_bm 0x40 /* Spike Detection Reset Flag bit mask. */ -#define RST_SDRF_bp 6 /* Spike Detection Reset Flag bit position. */ - -#define RST_SRF_bm 0x20 /* Software Reset Flag bit mask. */ -#define RST_SRF_bp 5 /* Software Reset Flag bit position. */ - -#define RST_PDIRF_bm 0x10 /* Programming and Debug Interface Interface Reset Flag bit mask. */ -#define RST_PDIRF_bp 4 /* Programming and Debug Interface Interface Reset Flag bit position. */ - -#define RST_WDRF_bm 0x08 /* Watchdog Reset Flag bit mask. */ -#define RST_WDRF_bp 3 /* Watchdog Reset Flag bit position. */ - -#define RST_BORF_bm 0x04 /* Brown-out Reset Flag bit mask. */ -#define RST_BORF_bp 2 /* Brown-out Reset Flag bit position. */ - -#define RST_EXTRF_bm 0x02 /* External Reset Flag bit mask. */ -#define RST_EXTRF_bp 1 /* External Reset Flag bit position. */ - -#define RST_PORF_bm 0x01 /* Power-on Reset Flag bit mask. */ -#define RST_PORF_bp 0 /* Power-on Reset Flag bit position. */ - -/* RST.CTRL bit masks and bit positions */ -#define RST_SWRST_bm 0x01 /* Software Reset bit mask. */ -#define RST_SWRST_bp 0 /* Software Reset bit position. */ - -/* WDT - Watch-Dog Timer */ -/* WDT.CTRL bit masks and bit positions */ -#define WDT_PER_gm 0x3C /* Period group mask. */ -#define WDT_PER_gp 2 /* Period group position. */ -#define WDT_PER0_bm (1<<2) /* Period bit 0 mask. */ -#define WDT_PER0_bp 2 /* Period bit 0 position. */ -#define WDT_PER1_bm (1<<3) /* Period bit 1 mask. */ -#define WDT_PER1_bp 3 /* Period bit 1 position. */ -#define WDT_PER2_bm (1<<4) /* Period bit 2 mask. */ -#define WDT_PER2_bp 4 /* Period bit 2 position. */ -#define WDT_PER3_bm (1<<5) /* Period bit 3 mask. */ -#define WDT_PER3_bp 5 /* Period bit 3 position. */ - -#define WDT_ENABLE_bm 0x02 /* Enable bit mask. */ -#define WDT_ENABLE_bp 1 /* Enable bit position. */ - -#define WDT_CEN_bm 0x01 /* Change Enable bit mask. */ -#define WDT_CEN_bp 0 /* Change Enable bit position. */ - -/* WDT.WINCTRL bit masks and bit positions */ -#define WDT_WPER_gm 0x3C /* Windowed Mode Period group mask. */ -#define WDT_WPER_gp 2 /* Windowed Mode Period group position. */ -#define WDT_WPER0_bm (1<<2) /* Windowed Mode Period bit 0 mask. */ -#define WDT_WPER0_bp 2 /* Windowed Mode Period bit 0 position. */ -#define WDT_WPER1_bm (1<<3) /* Windowed Mode Period bit 1 mask. */ -#define WDT_WPER1_bp 3 /* Windowed Mode Period bit 1 position. */ -#define WDT_WPER2_bm (1<<4) /* Windowed Mode Period bit 2 mask. */ -#define WDT_WPER2_bp 4 /* Windowed Mode Period bit 2 position. */ -#define WDT_WPER3_bm (1<<5) /* Windowed Mode Period bit 3 mask. */ -#define WDT_WPER3_bp 5 /* Windowed Mode Period bit 3 position. */ - -#define WDT_WEN_bm 0x02 /* Windowed Mode Enable bit mask. */ -#define WDT_WEN_bp 1 /* Windowed Mode Enable bit position. */ - -#define WDT_WCEN_bm 0x01 /* Windowed Mode Change Enable bit mask. */ -#define WDT_WCEN_bp 0 /* Windowed Mode Change Enable bit position. */ - -/* WDT.STATUS bit masks and bit positions */ -#define WDT_SYNCBUSY_bm 0x01 /* Syncronization busy bit mask. */ -#define WDT_SYNCBUSY_bp 0 /* Syncronization busy bit position. */ - -/* MCU - MCU Control */ -/* MCU.MCUCR bit masks and bit positions */ -#define MCU_JTAGD_bm 0x01 /* JTAG Disable bit mask. */ -#define MCU_JTAGD_bp 0 /* JTAG Disable bit position. */ - -/* MCU.ANAINIT bit masks and bit positions */ -#define MCU_STARTUPDLYB_gm 0x0C /* Analog startup delay Port B group mask. */ -#define MCU_STARTUPDLYB_gp 2 /* Analog startup delay Port B group position. */ -#define MCU_STARTUPDLYB0_bm (1<<2) /* Analog startup delay Port B bit 0 mask. */ -#define MCU_STARTUPDLYB0_bp 2 /* Analog startup delay Port B bit 0 position. */ -#define MCU_STARTUPDLYB1_bm (1<<3) /* Analog startup delay Port B bit 1 mask. */ -#define MCU_STARTUPDLYB1_bp 3 /* Analog startup delay Port B bit 1 position. */ - -#define MCU_STARTUPDLYA_gm 0x03 /* Analog startup delay Port A group mask. */ -#define MCU_STARTUPDLYA_gp 0 /* Analog startup delay Port A group position. */ -#define MCU_STARTUPDLYA0_bm (1<<0) /* Analog startup delay Port A bit 0 mask. */ -#define MCU_STARTUPDLYA0_bp 0 /* Analog startup delay Port A bit 0 position. */ -#define MCU_STARTUPDLYA1_bm (1<<1) /* Analog startup delay Port A bit 1 mask. */ -#define MCU_STARTUPDLYA1_bp 1 /* Analog startup delay Port A bit 1 position. */ - -/* MCU.EVSYSLOCK bit masks and bit positions */ -#define MCU_EVSYS1LOCK_bm 0x10 /* Event Channel 4-7 Lock bit mask. */ -#define MCU_EVSYS1LOCK_bp 4 /* Event Channel 4-7 Lock bit position. */ - -#define MCU_EVSYS0LOCK_bm 0x01 /* Event Channel 0-3 Lock bit mask. */ -#define MCU_EVSYS0LOCK_bp 0 /* Event Channel 0-3 Lock bit position. */ - -/* MCU.AWEXLOCK bit masks and bit positions */ -#define MCU_AWEXFLOCK_bm 0x08 /* AWeX on T/C F0 Lock bit mask. */ -#define MCU_AWEXFLOCK_bp 3 /* AWeX on T/C F0 Lock bit position. */ - -#define MCU_AWEXELOCK_bm 0x04 /* AWeX on T/C E0 Lock bit mask. */ -#define MCU_AWEXELOCK_bp 2 /* AWeX on T/C E0 Lock bit position. */ - -#define MCU_AWEXDLOCK_bm 0x02 /* AWeX on T/C D0 Lock bit mask. */ -#define MCU_AWEXDLOCK_bp 1 /* AWeX on T/C D0 Lock bit position. */ - -#define MCU_AWEXCLOCK_bm 0x01 /* AWeX on T/C C0 Lock bit mask. */ -#define MCU_AWEXCLOCK_bp 0 /* AWeX on T/C C0 Lock bit position. */ - -/* PMIC - Programmable Multi-level Interrupt Controller */ -/* PMIC.STATUS bit masks and bit positions */ -#define PMIC_NMIEX_bm 0x80 /* Non-maskable Interrupt Executing bit mask. */ -#define PMIC_NMIEX_bp 7 /* Non-maskable Interrupt Executing bit position. */ - -#define PMIC_HILVLEX_bm 0x04 /* High Level Interrupt Executing bit mask. */ -#define PMIC_HILVLEX_bp 2 /* High Level Interrupt Executing bit position. */ - -#define PMIC_MEDLVLEX_bm 0x02 /* Medium Level Interrupt Executing bit mask. */ -#define PMIC_MEDLVLEX_bp 1 /* Medium Level Interrupt Executing bit position. */ - -#define PMIC_LOLVLEX_bm 0x01 /* Low Level Interrupt Executing bit mask. */ -#define PMIC_LOLVLEX_bp 0 /* Low Level Interrupt Executing bit position. */ - -/* PMIC.INTPRI bit masks and bit positions */ -#define PMIC_INTPRI_gm 0xFF /* Interrupt Priority group mask. */ -#define PMIC_INTPRI_gp 0 /* Interrupt Priority group position. */ -#define PMIC_INTPRI0_bm (1<<0) /* Interrupt Priority bit 0 mask. */ -#define PMIC_INTPRI0_bp 0 /* Interrupt Priority bit 0 position. */ -#define PMIC_INTPRI1_bm (1<<1) /* Interrupt Priority bit 1 mask. */ -#define PMIC_INTPRI1_bp 1 /* Interrupt Priority bit 1 position. */ -#define PMIC_INTPRI2_bm (1<<2) /* Interrupt Priority bit 2 mask. */ -#define PMIC_INTPRI2_bp 2 /* Interrupt Priority bit 2 position. */ -#define PMIC_INTPRI3_bm (1<<3) /* Interrupt Priority bit 3 mask. */ -#define PMIC_INTPRI3_bp 3 /* Interrupt Priority bit 3 position. */ -#define PMIC_INTPRI4_bm (1<<4) /* Interrupt Priority bit 4 mask. */ -#define PMIC_INTPRI4_bp 4 /* Interrupt Priority bit 4 position. */ -#define PMIC_INTPRI5_bm (1<<5) /* Interrupt Priority bit 5 mask. */ -#define PMIC_INTPRI5_bp 5 /* Interrupt Priority bit 5 position. */ -#define PMIC_INTPRI6_bm (1<<6) /* Interrupt Priority bit 6 mask. */ -#define PMIC_INTPRI6_bp 6 /* Interrupt Priority bit 6 position. */ -#define PMIC_INTPRI7_bm (1<<7) /* Interrupt Priority bit 7 mask. */ -#define PMIC_INTPRI7_bp 7 /* Interrupt Priority bit 7 position. */ - -/* PMIC.CTRL bit masks and bit positions */ -#define PMIC_RREN_bm 0x80 /* Round-Robin Priority Enable bit mask. */ -#define PMIC_RREN_bp 7 /* Round-Robin Priority Enable bit position. */ - -#define PMIC_IVSEL_bm 0x40 /* Interrupt Vector Select bit mask. */ -#define PMIC_IVSEL_bp 6 /* Interrupt Vector Select bit position. */ - -#define PMIC_HILVLEN_bm 0x04 /* High Level Enable bit mask. */ -#define PMIC_HILVLEN_bp 2 /* High Level Enable bit position. */ - -#define PMIC_MEDLVLEN_bm 0x02 /* Medium Level Enable bit mask. */ -#define PMIC_MEDLVLEN_bp 1 /* Medium Level Enable bit position. */ - -#define PMIC_LOLVLEN_bm 0x01 /* Low Level Enable bit mask. */ -#define PMIC_LOLVLEN_bp 0 /* Low Level Enable bit position. */ - -/* PORTCFG - Port Configuration */ -/* PORTCFG.VPCTRLA bit masks and bit positions */ -#define PORTCFG_VP1MAP_gm 0xF0 /* Virtual Port 1 Mapping group mask. */ -#define PORTCFG_VP1MAP_gp 4 /* Virtual Port 1 Mapping group position. */ -#define PORTCFG_VP1MAP0_bm (1<<4) /* Virtual Port 1 Mapping bit 0 mask. */ -#define PORTCFG_VP1MAP0_bp 4 /* Virtual Port 1 Mapping bit 0 position. */ -#define PORTCFG_VP1MAP1_bm (1<<5) /* Virtual Port 1 Mapping bit 1 mask. */ -#define PORTCFG_VP1MAP1_bp 5 /* Virtual Port 1 Mapping bit 1 position. */ -#define PORTCFG_VP1MAP2_bm (1<<6) /* Virtual Port 1 Mapping bit 2 mask. */ -#define PORTCFG_VP1MAP2_bp 6 /* Virtual Port 1 Mapping bit 2 position. */ -#define PORTCFG_VP1MAP3_bm (1<<7) /* Virtual Port 1 Mapping bit 3 mask. */ -#define PORTCFG_VP1MAP3_bp 7 /* Virtual Port 1 Mapping bit 3 position. */ - -#define PORTCFG_VP0MAP_gm 0x0F /* Virtual Port 0 Mapping group mask. */ -#define PORTCFG_VP0MAP_gp 0 /* Virtual Port 0 Mapping group position. */ -#define PORTCFG_VP0MAP0_bm (1<<0) /* Virtual Port 0 Mapping bit 0 mask. */ -#define PORTCFG_VP0MAP0_bp 0 /* Virtual Port 0 Mapping bit 0 position. */ -#define PORTCFG_VP0MAP1_bm (1<<1) /* Virtual Port 0 Mapping bit 1 mask. */ -#define PORTCFG_VP0MAP1_bp 1 /* Virtual Port 0 Mapping bit 1 position. */ -#define PORTCFG_VP0MAP2_bm (1<<2) /* Virtual Port 0 Mapping bit 2 mask. */ -#define PORTCFG_VP0MAP2_bp 2 /* Virtual Port 0 Mapping bit 2 position. */ -#define PORTCFG_VP0MAP3_bm (1<<3) /* Virtual Port 0 Mapping bit 3 mask. */ -#define PORTCFG_VP0MAP3_bp 3 /* Virtual Port 0 Mapping bit 3 position. */ - -/* PORTCFG.VPCTRLB bit masks and bit positions */ -#define PORTCFG_VP3MAP_gm 0xF0 /* Virtual Port 3 Mapping group mask. */ -#define PORTCFG_VP3MAP_gp 4 /* Virtual Port 3 Mapping group position. */ -#define PORTCFG_VP3MAP0_bm (1<<4) /* Virtual Port 3 Mapping bit 0 mask. */ -#define PORTCFG_VP3MAP0_bp 4 /* Virtual Port 3 Mapping bit 0 position. */ -#define PORTCFG_VP3MAP1_bm (1<<5) /* Virtual Port 3 Mapping bit 1 mask. */ -#define PORTCFG_VP3MAP1_bp 5 /* Virtual Port 3 Mapping bit 1 position. */ -#define PORTCFG_VP3MAP2_bm (1<<6) /* Virtual Port 3 Mapping bit 2 mask. */ -#define PORTCFG_VP3MAP2_bp 6 /* Virtual Port 3 Mapping bit 2 position. */ -#define PORTCFG_VP3MAP3_bm (1<<7) /* Virtual Port 3 Mapping bit 3 mask. */ -#define PORTCFG_VP3MAP3_bp 7 /* Virtual Port 3 Mapping bit 3 position. */ - -#define PORTCFG_VP2MAP_gm 0x0F /* Virtual Port 2 Mapping group mask. */ -#define PORTCFG_VP2MAP_gp 0 /* Virtual Port 2 Mapping group position. */ -#define PORTCFG_VP2MAP0_bm (1<<0) /* Virtual Port 2 Mapping bit 0 mask. */ -#define PORTCFG_VP2MAP0_bp 0 /* Virtual Port 2 Mapping bit 0 position. */ -#define PORTCFG_VP2MAP1_bm (1<<1) /* Virtual Port 2 Mapping bit 1 mask. */ -#define PORTCFG_VP2MAP1_bp 1 /* Virtual Port 2 Mapping bit 1 position. */ -#define PORTCFG_VP2MAP2_bm (1<<2) /* Virtual Port 2 Mapping bit 2 mask. */ -#define PORTCFG_VP2MAP2_bp 2 /* Virtual Port 2 Mapping bit 2 position. */ -#define PORTCFG_VP2MAP3_bm (1<<3) /* Virtual Port 2 Mapping bit 3 mask. */ -#define PORTCFG_VP2MAP3_bp 3 /* Virtual Port 2 Mapping bit 3 position. */ - -/* PORTCFG.CLKEVOUT bit masks and bit positions */ -#define PORTCFG_CLKOUT_gm 0x03 /* Peripheral Clock Output Port group mask. */ -#define PORTCFG_CLKOUT_gp 0 /* Peripheral Clock Output Port group position. */ -#define PORTCFG_CLKOUT0_bm (1<<0) /* Peripheral Clock Output Port bit 0 mask. */ -#define PORTCFG_CLKOUT0_bp 0 /* Peripheral Clock Output Port bit 0 position. */ -#define PORTCFG_CLKOUT1_bm (1<<1) /* Peripheral Clock Output Port bit 1 mask. */ -#define PORTCFG_CLKOUT1_bp 1 /* Peripheral Clock Output Port bit 1 position. */ - -#define PORTCFG_CLKOUTSEL_gm 0x0C /* Peripheral Clock Output Select group mask. */ -#define PORTCFG_CLKOUTSEL_gp 2 /* Peripheral Clock Output Select group position. */ -#define PORTCFG_CLKOUTSEL0_bm (1<<2) /* Peripheral Clock Output Select bit 0 mask. */ -#define PORTCFG_CLKOUTSEL0_bp 2 /* Peripheral Clock Output Select bit 0 position. */ -#define PORTCFG_CLKOUTSEL1_bm (1<<3) /* Peripheral Clock Output Select bit 1 mask. */ -#define PORTCFG_CLKOUTSEL1_bp 3 /* Peripheral Clock Output Select bit 1 position. */ - -#define PORTCFG_EVOUT_gm 0x30 /* Event Output Port group mask. */ -#define PORTCFG_EVOUT_gp 4 /* Event Output Port group position. */ -#define PORTCFG_EVOUT0_bm (1<<4) /* Event Output Port bit 0 mask. */ -#define PORTCFG_EVOUT0_bp 4 /* Event Output Port bit 0 position. */ -#define PORTCFG_EVOUT1_bm (1<<5) /* Event Output Port bit 1 mask. */ -#define PORTCFG_EVOUT1_bp 5 /* Event Output Port bit 1 position. */ - -#define PORTCFG_RTCOUT_bm 0x40 /* RTC Clock Output bit mask. */ -#define PORTCFG_RTCOUT_bp 6 /* RTC Clock Output bit position. */ - -#define PORTCFG_CLKEVPIN_bm 0x80 /* Peripheral Clock and Event Output pin Select bit mask. */ -#define PORTCFG_CLKEVPIN_bp 7 /* Peripheral Clock and Event Output pin Select bit position. */ - -/* PORTCFG.EBIOUT bit masks and bit positions */ -#define PORTCFG_EBICSOUT_gm 0x03 /* EBI Chip Select Output group mask. */ -#define PORTCFG_EBICSOUT_gp 0 /* EBI Chip Select Output group position. */ -#define PORTCFG_EBICSOUT0_bm (1<<0) /* EBI Chip Select Output bit 0 mask. */ -#define PORTCFG_EBICSOUT0_bp 0 /* EBI Chip Select Output bit 0 position. */ -#define PORTCFG_EBICSOUT1_bm (1<<1) /* EBI Chip Select Output bit 1 mask. */ -#define PORTCFG_EBICSOUT1_bp 1 /* EBI Chip Select Output bit 1 position. */ - -#define PORTCFG_EBIADROUT_gm 0x0C /* EBI Address Output group mask. */ -#define PORTCFG_EBIADROUT_gp 2 /* EBI Address Output group position. */ -#define PORTCFG_EBIADROUT0_bm (1<<2) /* EBI Address Output bit 0 mask. */ -#define PORTCFG_EBIADROUT0_bp 2 /* EBI Address Output bit 0 position. */ -#define PORTCFG_EBIADROUT1_bm (1<<3) /* EBI Address Output bit 1 mask. */ -#define PORTCFG_EBIADROUT1_bp 3 /* EBI Address Output bit 1 position. */ - -/* PORTCFG.EVOUTSEL bit masks and bit positions */ -#define PORTCFG_EVOUTSEL_gm 0x07 /* Event Output Select group mask. */ -#define PORTCFG_EVOUTSEL_gp 0 /* Event Output Select group position. */ -#define PORTCFG_EVOUTSEL0_bm (1<<0) /* Event Output Select bit 0 mask. */ -#define PORTCFG_EVOUTSEL0_bp 0 /* Event Output Select bit 0 position. */ -#define PORTCFG_EVOUTSEL1_bm (1<<1) /* Event Output Select bit 1 mask. */ -#define PORTCFG_EVOUTSEL1_bp 1 /* Event Output Select bit 1 position. */ -#define PORTCFG_EVOUTSEL2_bm (1<<2) /* Event Output Select bit 2 mask. */ -#define PORTCFG_EVOUTSEL2_bp 2 /* Event Output Select bit 2 position. */ - -/* AES - AES Module */ -/* AES.CTRL bit masks and bit positions */ -#define AES_START_bm 0x80 /* Start/Run bit mask. */ -#define AES_START_bp 7 /* Start/Run bit position. */ - -#define AES_AUTO_bm 0x40 /* Auto Start Trigger bit mask. */ -#define AES_AUTO_bp 6 /* Auto Start Trigger bit position. */ - -#define AES_RESET_bm 0x20 /* AES Software Reset bit mask. */ -#define AES_RESET_bp 5 /* AES Software Reset bit position. */ - -#define AES_DECRYPT_bm 0x10 /* Decryption / Direction bit mask. */ -#define AES_DECRYPT_bp 4 /* Decryption / Direction bit position. */ - -#define AES_XOR_bm 0x04 /* State XOR Load Enable bit mask. */ -#define AES_XOR_bp 2 /* State XOR Load Enable bit position. */ - -/* AES.STATUS bit masks and bit positions */ -#define AES_ERROR_bm 0x80 /* AES Error bit mask. */ -#define AES_ERROR_bp 7 /* AES Error bit position. */ - -#define AES_SRIF_bm 0x01 /* State Ready Interrupt Flag bit mask. */ -#define AES_SRIF_bp 0 /* State Ready Interrupt Flag bit position. */ - -/* AES.INTCTRL bit masks and bit positions */ -#define AES_INTLVL_gm 0x03 /* Interrupt level group mask. */ -#define AES_INTLVL_gp 0 /* Interrupt level group position. */ -#define AES_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */ -#define AES_INTLVL0_bp 0 /* Interrupt level bit 0 position. */ -#define AES_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */ -#define AES_INTLVL1_bp 1 /* Interrupt level bit 1 position. */ - -/* CRC - Cyclic Redundancy Checker */ -/* CRC.CTRL bit masks and bit positions */ -#define CRC_RESET_gm 0xC0 /* Reset group mask. */ -#define CRC_RESET_gp 6 /* Reset group position. */ -#define CRC_RESET0_bm (1<<6) /* Reset bit 0 mask. */ -#define CRC_RESET0_bp 6 /* Reset bit 0 position. */ -#define CRC_RESET1_bm (1<<7) /* Reset bit 1 mask. */ -#define CRC_RESET1_bp 7 /* Reset bit 1 position. */ - -#define CRC_CRC32_bm 0x20 /* CRC Mode bit mask. */ -#define CRC_CRC32_bp 5 /* CRC Mode bit position. */ - -#define CRC_SOURCE_gm 0x0F /* Input Source group mask. */ -#define CRC_SOURCE_gp 0 /* Input Source group position. */ -#define CRC_SOURCE0_bm (1<<0) /* Input Source bit 0 mask. */ -#define CRC_SOURCE0_bp 0 /* Input Source bit 0 position. */ -#define CRC_SOURCE1_bm (1<<1) /* Input Source bit 1 mask. */ -#define CRC_SOURCE1_bp 1 /* Input Source bit 1 position. */ -#define CRC_SOURCE2_bm (1<<2) /* Input Source bit 2 mask. */ -#define CRC_SOURCE2_bp 2 /* Input Source bit 2 position. */ -#define CRC_SOURCE3_bm (1<<3) /* Input Source bit 3 mask. */ -#define CRC_SOURCE3_bp 3 /* Input Source bit 3 position. */ - -/* CRC.STATUS bit masks and bit positions */ -#define CRC_ZERO_bm 0x02 /* Zero detection bit mask. */ -#define CRC_ZERO_bp 1 /* Zero detection bit position. */ - -#define CRC_BUSY_bm 0x01 /* Busy bit mask. */ -#define CRC_BUSY_bp 0 /* Busy bit position. */ - -/* VBAT - Battery Backup Module */ -/* VBAT.CTRL bit masks and bit positions */ -#define VBAT_HIGHESR_bm 0x20 /* 32-kHz Crystal Oscillator High Power Mode bit mask. */ -#define VBAT_HIGHESR_bp 5 /* 32-kHz Crystal Oscillator High Power Mode bit position. */ - -#define VBAT_XOSCSEL_bm 0x10 /* 32-kHz Crystal Oscillator Output Selection bit mask. */ -#define VBAT_XOSCSEL_bp 4 /* 32-kHz Crystal Oscillator Output Selection bit position. */ - -#define VBAT_XOSCEN_bm 0x08 /* Crystal Oscillator Enable bit mask. */ -#define VBAT_XOSCEN_bp 3 /* Crystal Oscillator Enable bit position. */ - -#define VBAT_XOSCFDEN_bm 0x04 /* Crystal Oscillator Failure Detection Monitor Enable bit mask. */ -#define VBAT_XOSCFDEN_bp 2 /* Crystal Oscillator Failure Detection Monitor Enable bit position. */ - -#define VBAT_ACCEN_bm 0x02 /* Access Enable bit mask. */ -#define VBAT_ACCEN_bp 1 /* Access Enable bit position. */ - -#define VBAT_RESET_bm 0x01 /* Reset bit mask. */ -#define VBAT_RESET_bp 0 /* Reset bit position. */ - -/* VBAT.STATUS bit masks and bit positions */ -#define VBAT_BBPWR_bm 0x80 /* Battery backup Power bit mask. */ -#define VBAT_BBPWR_bp 7 /* Battery backup Power bit position. */ - -#define VBAT_XOSCRDY_bm 0x08 /* Crystal Oscillator Ready bit mask. */ -#define VBAT_XOSCRDY_bp 3 /* Crystal Oscillator Ready bit position. */ - -#define VBAT_XOSCFAIL_bm 0x04 /* Crystal Oscillator Failure bit mask. */ -#define VBAT_XOSCFAIL_bp 2 /* Crystal Oscillator Failure bit position. */ - -#define VBAT_BBBORF_bm 0x02 /* Battery Backup Brown-Out Reset Flag bit mask. */ -#define VBAT_BBBORF_bp 1 /* Battery Backup Brown-Out Reset Flag bit position. */ - -#define VBAT_BBPORF_bm 0x01 /* Battery Backup Power-On Reset Flag bit mask. */ -#define VBAT_BBPORF_bp 0 /* Battery Backup Power-On Reset Flag bit position. */ - -/* DMA - DMA Controller */ -/* DMA_CH.CTRLA bit masks and bit positions */ -#define DMA_CH_ENABLE_bm 0x80 /* Channel Enable bit mask. */ -#define DMA_CH_ENABLE_bp 7 /* Channel Enable bit position. */ - -#define DMA_CH_RESET_bm 0x40 /* Channel Software Reset bit mask. */ -#define DMA_CH_RESET_bp 6 /* Channel Software Reset bit position. */ - -#define DMA_CH_REPEAT_bm 0x20 /* Channel Repeat Mode bit mask. */ -#define DMA_CH_REPEAT_bp 5 /* Channel Repeat Mode bit position. */ - -#define DMA_CH_TRFREQ_bm 0x10 /* Channel Transfer Request bit mask. */ -#define DMA_CH_TRFREQ_bp 4 /* Channel Transfer Request bit position. */ - -#define DMA_CH_SINGLE_bm 0x04 /* Channel Single Shot Data Transfer bit mask. */ -#define DMA_CH_SINGLE_bp 2 /* Channel Single Shot Data Transfer bit position. */ - -#define DMA_CH_BURSTLEN_gm 0x03 /* Channel Transfer Mode group mask. */ -#define DMA_CH_BURSTLEN_gp 0 /* Channel Transfer Mode group position. */ -#define DMA_CH_BURSTLEN0_bm (1<<0) /* Channel Transfer Mode bit 0 mask. */ -#define DMA_CH_BURSTLEN0_bp 0 /* Channel Transfer Mode bit 0 position. */ -#define DMA_CH_BURSTLEN1_bm (1<<1) /* Channel Transfer Mode bit 1 mask. */ -#define DMA_CH_BURSTLEN1_bp 1 /* Channel Transfer Mode bit 1 position. */ - -/* DMA_CH.CTRLB bit masks and bit positions */ -#define DMA_CH_CHBUSY_bm 0x80 /* Block Transfer Busy bit mask. */ -#define DMA_CH_CHBUSY_bp 7 /* Block Transfer Busy bit position. */ - -#define DMA_CH_CHPEND_bm 0x40 /* Block Transfer Pending bit mask. */ -#define DMA_CH_CHPEND_bp 6 /* Block Transfer Pending bit position. */ - -#define DMA_CH_ERRIF_bm 0x20 /* Block Transfer Error Interrupt Flag bit mask. */ -#define DMA_CH_ERRIF_bp 5 /* Block Transfer Error Interrupt Flag bit position. */ - -#define DMA_CH_TRNIF_bm 0x10 /* Transaction Complete Interrup Flag bit mask. */ -#define DMA_CH_TRNIF_bp 4 /* Transaction Complete Interrup Flag bit position. */ - -#define DMA_CH_ERRINTLVL_gm 0x0C /* Transfer Error Interrupt Level group mask. */ -#define DMA_CH_ERRINTLVL_gp 2 /* Transfer Error Interrupt Level group position. */ -#define DMA_CH_ERRINTLVL0_bm (1<<2) /* Transfer Error Interrupt Level bit 0 mask. */ -#define DMA_CH_ERRINTLVL0_bp 2 /* Transfer Error Interrupt Level bit 0 position. */ -#define DMA_CH_ERRINTLVL1_bm (1<<3) /* Transfer Error Interrupt Level bit 1 mask. */ -#define DMA_CH_ERRINTLVL1_bp 3 /* Transfer Error Interrupt Level bit 1 position. */ - -#define DMA_CH_TRNINTLVL_gm 0x03 /* Transaction Complete Interrupt Level group mask. */ -#define DMA_CH_TRNINTLVL_gp 0 /* Transaction Complete Interrupt Level group position. */ -#define DMA_CH_TRNINTLVL0_bm (1<<0) /* Transaction Complete Interrupt Level bit 0 mask. */ -#define DMA_CH_TRNINTLVL0_bp 0 /* Transaction Complete Interrupt Level bit 0 position. */ -#define DMA_CH_TRNINTLVL1_bm (1<<1) /* Transaction Complete Interrupt Level bit 1 mask. */ -#define DMA_CH_TRNINTLVL1_bp 1 /* Transaction Complete Interrupt Level bit 1 position. */ - -/* DMA_CH.ADDRCTRL bit masks and bit positions */ -#define DMA_CH_SRCRELOAD_gm 0xC0 /* Channel Source Address Reload group mask. */ -#define DMA_CH_SRCRELOAD_gp 6 /* Channel Source Address Reload group position. */ -#define DMA_CH_SRCRELOAD0_bm (1<<6) /* Channel Source Address Reload bit 0 mask. */ -#define DMA_CH_SRCRELOAD0_bp 6 /* Channel Source Address Reload bit 0 position. */ -#define DMA_CH_SRCRELOAD1_bm (1<<7) /* Channel Source Address Reload bit 1 mask. */ -#define DMA_CH_SRCRELOAD1_bp 7 /* Channel Source Address Reload bit 1 position. */ - -#define DMA_CH_SRCDIR_gm 0x30 /* Channel Source Address Mode group mask. */ -#define DMA_CH_SRCDIR_gp 4 /* Channel Source Address Mode group position. */ -#define DMA_CH_SRCDIR0_bm (1<<4) /* Channel Source Address Mode bit 0 mask. */ -#define DMA_CH_SRCDIR0_bp 4 /* Channel Source Address Mode bit 0 position. */ -#define DMA_CH_SRCDIR1_bm (1<<5) /* Channel Source Address Mode bit 1 mask. */ -#define DMA_CH_SRCDIR1_bp 5 /* Channel Source Address Mode bit 1 position. */ - -#define DMA_CH_DESTRELOAD_gm 0x0C /* Channel Destination Address Reload group mask. */ -#define DMA_CH_DESTRELOAD_gp 2 /* Channel Destination Address Reload group position. */ -#define DMA_CH_DESTRELOAD0_bm (1<<2) /* Channel Destination Address Reload bit 0 mask. */ -#define DMA_CH_DESTRELOAD0_bp 2 /* Channel Destination Address Reload bit 0 position. */ -#define DMA_CH_DESTRELOAD1_bm (1<<3) /* Channel Destination Address Reload bit 1 mask. */ -#define DMA_CH_DESTRELOAD1_bp 3 /* Channel Destination Address Reload bit 1 position. */ - -#define DMA_CH_DESTDIR_gm 0x03 /* Channel Destination Address Mode group mask. */ -#define DMA_CH_DESTDIR_gp 0 /* Channel Destination Address Mode group position. */ -#define DMA_CH_DESTDIR0_bm (1<<0) /* Channel Destination Address Mode bit 0 mask. */ -#define DMA_CH_DESTDIR0_bp 0 /* Channel Destination Address Mode bit 0 position. */ -#define DMA_CH_DESTDIR1_bm (1<<1) /* Channel Destination Address Mode bit 1 mask. */ -#define DMA_CH_DESTDIR1_bp 1 /* Channel Destination Address Mode bit 1 position. */ - -/* DMA_CH.TRIGSRC bit masks and bit positions */ -#define DMA_CH_TRIGSRC_gm 0xFF /* Channel Trigger Source group mask. */ -#define DMA_CH_TRIGSRC_gp 0 /* Channel Trigger Source group position. */ -#define DMA_CH_TRIGSRC0_bm (1<<0) /* Channel Trigger Source bit 0 mask. */ -#define DMA_CH_TRIGSRC0_bp 0 /* Channel Trigger Source bit 0 position. */ -#define DMA_CH_TRIGSRC1_bm (1<<1) /* Channel Trigger Source bit 1 mask. */ -#define DMA_CH_TRIGSRC1_bp 1 /* Channel Trigger Source bit 1 position. */ -#define DMA_CH_TRIGSRC2_bm (1<<2) /* Channel Trigger Source bit 2 mask. */ -#define DMA_CH_TRIGSRC2_bp 2 /* Channel Trigger Source bit 2 position. */ -#define DMA_CH_TRIGSRC3_bm (1<<3) /* Channel Trigger Source bit 3 mask. */ -#define DMA_CH_TRIGSRC3_bp 3 /* Channel Trigger Source bit 3 position. */ -#define DMA_CH_TRIGSRC4_bm (1<<4) /* Channel Trigger Source bit 4 mask. */ -#define DMA_CH_TRIGSRC4_bp 4 /* Channel Trigger Source bit 4 position. */ -#define DMA_CH_TRIGSRC5_bm (1<<5) /* Channel Trigger Source bit 5 mask. */ -#define DMA_CH_TRIGSRC5_bp 5 /* Channel Trigger Source bit 5 position. */ -#define DMA_CH_TRIGSRC6_bm (1<<6) /* Channel Trigger Source bit 6 mask. */ -#define DMA_CH_TRIGSRC6_bp 6 /* Channel Trigger Source bit 6 position. */ -#define DMA_CH_TRIGSRC7_bm (1<<7) /* Channel Trigger Source bit 7 mask. */ -#define DMA_CH_TRIGSRC7_bp 7 /* Channel Trigger Source bit 7 position. */ - -/* DMA.CTRL bit masks and bit positions */ -#define DMA_ENABLE_bm 0x80 /* Enable bit mask. */ -#define DMA_ENABLE_bp 7 /* Enable bit position. */ - -#define DMA_RESET_bm 0x40 /* Software Reset bit mask. */ -#define DMA_RESET_bp 6 /* Software Reset bit position. */ - -#define DMA_DBUFMODE_gm 0x0C /* Double Buffering Mode group mask. */ -#define DMA_DBUFMODE_gp 2 /* Double Buffering Mode group position. */ -#define DMA_DBUFMODE0_bm (1<<2) /* Double Buffering Mode bit 0 mask. */ -#define DMA_DBUFMODE0_bp 2 /* Double Buffering Mode bit 0 position. */ -#define DMA_DBUFMODE1_bm (1<<3) /* Double Buffering Mode bit 1 mask. */ -#define DMA_DBUFMODE1_bp 3 /* Double Buffering Mode bit 1 position. */ - -#define DMA_PRIMODE_gm 0x03 /* Channel Priority Mode group mask. */ -#define DMA_PRIMODE_gp 0 /* Channel Priority Mode group position. */ -#define DMA_PRIMODE0_bm (1<<0) /* Channel Priority Mode bit 0 mask. */ -#define DMA_PRIMODE0_bp 0 /* Channel Priority Mode bit 0 position. */ -#define DMA_PRIMODE1_bm (1<<1) /* Channel Priority Mode bit 1 mask. */ -#define DMA_PRIMODE1_bp 1 /* Channel Priority Mode bit 1 position. */ - -/* DMA.INTFLAGS bit masks and bit positions */ -#define DMA_CH3ERRIF_bm 0x80 /* Channel 3 Block Transfer Error Interrupt Flag bit mask. */ -#define DMA_CH3ERRIF_bp 7 /* Channel 3 Block Transfer Error Interrupt Flag bit position. */ - -#define DMA_CH2ERRIF_bm 0x40 /* Channel 2 Block Transfer Error Interrupt Flag bit mask. */ -#define DMA_CH2ERRIF_bp 6 /* Channel 2 Block Transfer Error Interrupt Flag bit position. */ - -#define DMA_CH1ERRIF_bm 0x20 /* Channel 1 Block Transfer Error Interrupt Flag bit mask. */ -#define DMA_CH1ERRIF_bp 5 /* Channel 1 Block Transfer Error Interrupt Flag bit position. */ - -#define DMA_CH0ERRIF_bm 0x10 /* Channel 0 Block Transfer Error Interrupt Flag bit mask. */ -#define DMA_CH0ERRIF_bp 4 /* Channel 0 Block Transfer Error Interrupt Flag bit position. */ - -#define DMA_CH3TRNIF_bm 0x08 /* Channel 3 Transaction Complete Interrupt Flag bit mask. */ -#define DMA_CH3TRNIF_bp 3 /* Channel 3 Transaction Complete Interrupt Flag bit position. */ - -#define DMA_CH2TRNIF_bm 0x04 /* Channel 2 Transaction Complete Interrupt Flag bit mask. */ -#define DMA_CH2TRNIF_bp 2 /* Channel 2 Transaction Complete Interrupt Flag bit position. */ - -#define DMA_CH1TRNIF_bm 0x02 /* Channel 1 Transaction Complete Interrupt Flag bit mask. */ -#define DMA_CH1TRNIF_bp 1 /* Channel 1 Transaction Complete Interrupt Flag bit position. */ - -#define DMA_CH0TRNIF_bm 0x01 /* Channel 0 Transaction Complete Interrupt Flag bit mask. */ -#define DMA_CH0TRNIF_bp 0 /* Channel 0 Transaction Complete Interrupt Flag bit position. */ - -/* DMA.STATUS bit masks and bit positions */ -#define DMA_CH3BUSY_bm 0x80 /* Channel 3 Block Transfer Busy bit mask. */ -#define DMA_CH3BUSY_bp 7 /* Channel 3 Block Transfer Busy bit position. */ - -#define DMA_CH2BUSY_bm 0x40 /* Channel 2 Block Transfer Busy bit mask. */ -#define DMA_CH2BUSY_bp 6 /* Channel 2 Block Transfer Busy bit position. */ - -#define DMA_CH1BUSY_bm 0x20 /* Channel 1 Block Transfer Busy bit mask. */ -#define DMA_CH1BUSY_bp 5 /* Channel 1 Block Transfer Busy bit position. */ - -#define DMA_CH0BUSY_bm 0x10 /* Channel 0 Block Transfer Busy bit mask. */ -#define DMA_CH0BUSY_bp 4 /* Channel 0 Block Transfer Busy bit position. */ - -#define DMA_CH3PEND_bm 0x08 /* Channel 3 Block Transfer Pending bit mask. */ -#define DMA_CH3PEND_bp 3 /* Channel 3 Block Transfer Pending bit position. */ - -#define DMA_CH2PEND_bm 0x04 /* Channel 2 Block Transfer Pending bit mask. */ -#define DMA_CH2PEND_bp 2 /* Channel 2 Block Transfer Pending bit position. */ - -#define DMA_CH1PEND_bm 0x02 /* Channel 1 Block Transfer Pending bit mask. */ -#define DMA_CH1PEND_bp 1 /* Channel 1 Block Transfer Pending bit position. */ - -#define DMA_CH0PEND_bm 0x01 /* Channel 0 Block Transfer Pending bit mask. */ -#define DMA_CH0PEND_bp 0 /* Channel 0 Block Transfer Pending bit position. */ - -/* EVSYS - Event System */ -/* EVSYS.CH0MUX bit masks and bit positions */ -#define EVSYS_CHMUX_gm 0xFF /* Event Channel 0 Multiplexer group mask. */ -#define EVSYS_CHMUX_gp 0 /* Event Channel 0 Multiplexer group position. */ -#define EVSYS_CHMUX0_bm (1<<0) /* Event Channel 0 Multiplexer bit 0 mask. */ -#define EVSYS_CHMUX0_bp 0 /* Event Channel 0 Multiplexer bit 0 position. */ -#define EVSYS_CHMUX1_bm (1<<1) /* Event Channel 0 Multiplexer bit 1 mask. */ -#define EVSYS_CHMUX1_bp 1 /* Event Channel 0 Multiplexer bit 1 position. */ -#define EVSYS_CHMUX2_bm (1<<2) /* Event Channel 0 Multiplexer bit 2 mask. */ -#define EVSYS_CHMUX2_bp 2 /* Event Channel 0 Multiplexer bit 2 position. */ -#define EVSYS_CHMUX3_bm (1<<3) /* Event Channel 0 Multiplexer bit 3 mask. */ -#define EVSYS_CHMUX3_bp 3 /* Event Channel 0 Multiplexer bit 3 position. */ -#define EVSYS_CHMUX4_bm (1<<4) /* Event Channel 0 Multiplexer bit 4 mask. */ -#define EVSYS_CHMUX4_bp 4 /* Event Channel 0 Multiplexer bit 4 position. */ -#define EVSYS_CHMUX5_bm (1<<5) /* Event Channel 0 Multiplexer bit 5 mask. */ -#define EVSYS_CHMUX5_bp 5 /* Event Channel 0 Multiplexer bit 5 position. */ -#define EVSYS_CHMUX6_bm (1<<6) /* Event Channel 0 Multiplexer bit 6 mask. */ -#define EVSYS_CHMUX6_bp 6 /* Event Channel 0 Multiplexer bit 6 position. */ -#define EVSYS_CHMUX7_bm (1<<7) /* Event Channel 0 Multiplexer bit 7 mask. */ -#define EVSYS_CHMUX7_bp 7 /* Event Channel 0 Multiplexer bit 7 position. */ - -/* EVSYS.CH1MUX bit masks and bit positions */ -/* EVSYS_CHMUX Predefined. */ -/* EVSYS_CHMUX Predefined. */ - -/* EVSYS.CH2MUX bit masks and bit positions */ -/* EVSYS_CHMUX Predefined. */ -/* EVSYS_CHMUX Predefined. */ - -/* EVSYS.CH3MUX bit masks and bit positions */ -/* EVSYS_CHMUX Predefined. */ -/* EVSYS_CHMUX Predefined. */ - -/* EVSYS.CH4MUX bit masks and bit positions */ -/* EVSYS_CHMUX Predefined. */ -/* EVSYS_CHMUX Predefined. */ - -/* EVSYS.CH5MUX bit masks and bit positions */ -/* EVSYS_CHMUX Predefined. */ -/* EVSYS_CHMUX Predefined. */ - -/* EVSYS.CH6MUX bit masks and bit positions */ -/* EVSYS_CHMUX Predefined. */ -/* EVSYS_CHMUX Predefined. */ - -/* EVSYS.CH7MUX bit masks and bit positions */ -/* EVSYS_CHMUX Predefined. */ -/* EVSYS_CHMUX Predefined. */ - -/* EVSYS.CH0CTRL bit masks and bit positions */ -#define EVSYS_QDIRM_gm 0x60 /* Quadrature Decoder Index Recognition Mode group mask. */ -#define EVSYS_QDIRM_gp 5 /* Quadrature Decoder Index Recognition Mode group position. */ -#define EVSYS_QDIRM0_bm (1<<5) /* Quadrature Decoder Index Recognition Mode bit 0 mask. */ -#define EVSYS_QDIRM0_bp 5 /* Quadrature Decoder Index Recognition Mode bit 0 position. */ -#define EVSYS_QDIRM1_bm (1<<6) /* Quadrature Decoder Index Recognition Mode bit 1 mask. */ -#define EVSYS_QDIRM1_bp 6 /* Quadrature Decoder Index Recognition Mode bit 1 position. */ - -#define EVSYS_QDIEN_bm 0x10 /* Quadrature Decoder Index Enable bit mask. */ -#define EVSYS_QDIEN_bp 4 /* Quadrature Decoder Index Enable bit position. */ - -#define EVSYS_QDEN_bm 0x08 /* Quadrature Decoder Enable bit mask. */ -#define EVSYS_QDEN_bp 3 /* Quadrature Decoder Enable bit position. */ - -#define EVSYS_DIGFILT_gm 0x07 /* Digital Filter group mask. */ -#define EVSYS_DIGFILT_gp 0 /* Digital Filter group position. */ -#define EVSYS_DIGFILT0_bm (1<<0) /* Digital Filter bit 0 mask. */ -#define EVSYS_DIGFILT0_bp 0 /* Digital Filter bit 0 position. */ -#define EVSYS_DIGFILT1_bm (1<<1) /* Digital Filter bit 1 mask. */ -#define EVSYS_DIGFILT1_bp 1 /* Digital Filter bit 1 position. */ -#define EVSYS_DIGFILT2_bm (1<<2) /* Digital Filter bit 2 mask. */ -#define EVSYS_DIGFILT2_bp 2 /* Digital Filter bit 2 position. */ - -/* EVSYS.CH1CTRL bit masks and bit positions */ -/* EVSYS_DIGFILT Predefined. */ -/* EVSYS_DIGFILT Predefined. */ - -/* EVSYS.CH2CTRL bit masks and bit positions */ -/* EVSYS_QDIRM Predefined. */ -/* EVSYS_QDIRM Predefined. */ - -/* EVSYS_QDIEN Predefined. */ -/* EVSYS_QDIEN Predefined. */ - -/* EVSYS_QDEN Predefined. */ -/* EVSYS_QDEN Predefined. */ - -/* EVSYS_DIGFILT Predefined. */ -/* EVSYS_DIGFILT Predefined. */ - -/* EVSYS.CH3CTRL bit masks and bit positions */ -/* EVSYS_DIGFILT Predefined. */ -/* EVSYS_DIGFILT Predefined. */ - -/* EVSYS.CH4CTRL bit masks and bit positions */ -/* EVSYS_QDIRM Predefined. */ -/* EVSYS_QDIRM Predefined. */ - -/* EVSYS_QDIEN Predefined. */ -/* EVSYS_QDIEN Predefined. */ - -/* EVSYS_QDEN Predefined. */ -/* EVSYS_QDEN Predefined. */ - -/* EVSYS_DIGFILT Predefined. */ -/* EVSYS_DIGFILT Predefined. */ - -/* EVSYS.CH5CTRL bit masks and bit positions */ -/* EVSYS_DIGFILT Predefined. */ -/* EVSYS_DIGFILT Predefined. */ - -/* EVSYS.CH6CTRL bit masks and bit positions */ -/* EVSYS_DIGFILT Predefined. */ -/* EVSYS_DIGFILT Predefined. */ - -/* EVSYS.CH7CTRL bit masks and bit positions */ -/* EVSYS_DIGFILT Predefined. */ -/* EVSYS_DIGFILT Predefined. */ - -/* NVM - Non Volatile Memory Controller */ -/* NVM.CMD bit masks and bit positions */ -#define NVM_CMD_gm 0x7F /* Command group mask. */ -#define NVM_CMD_gp 0 /* Command group position. */ -#define NVM_CMD0_bm (1<<0) /* Command bit 0 mask. */ -#define NVM_CMD0_bp 0 /* Command bit 0 position. */ -#define NVM_CMD1_bm (1<<1) /* Command bit 1 mask. */ -#define NVM_CMD1_bp 1 /* Command bit 1 position. */ -#define NVM_CMD2_bm (1<<2) /* Command bit 2 mask. */ -#define NVM_CMD2_bp 2 /* Command bit 2 position. */ -#define NVM_CMD3_bm (1<<3) /* Command bit 3 mask. */ -#define NVM_CMD3_bp 3 /* Command bit 3 position. */ -#define NVM_CMD4_bm (1<<4) /* Command bit 4 mask. */ -#define NVM_CMD4_bp 4 /* Command bit 4 position. */ -#define NVM_CMD5_bm (1<<5) /* Command bit 5 mask. */ -#define NVM_CMD5_bp 5 /* Command bit 5 position. */ -#define NVM_CMD6_bm (1<<6) /* Command bit 6 mask. */ -#define NVM_CMD6_bp 6 /* Command bit 6 position. */ - -/* NVM.CTRLA bit masks and bit positions */ -#define NVM_CMDEX_bm 0x01 /* Command Execute bit mask. */ -#define NVM_CMDEX_bp 0 /* Command Execute bit position. */ - -/* NVM.CTRLB bit masks and bit positions */ -#define NVM_EEMAPEN_bm 0x08 /* EEPROM Mapping Enable bit mask. */ -#define NVM_EEMAPEN_bp 3 /* EEPROM Mapping Enable bit position. */ - -#define NVM_FPRM_bm 0x04 /* Flash Power Reduction Enable bit mask. */ -#define NVM_FPRM_bp 2 /* Flash Power Reduction Enable bit position. */ - -#define NVM_EPRM_bm 0x02 /* EEPROM Power Reduction Enable bit mask. */ -#define NVM_EPRM_bp 1 /* EEPROM Power Reduction Enable bit position. */ - -#define NVM_SPMLOCK_bm 0x01 /* SPM Lock bit mask. */ -#define NVM_SPMLOCK_bp 0 /* SPM Lock bit position. */ - -/* NVM.INTCTRL bit masks and bit positions */ -#define NVM_SPMLVL_gm 0x0C /* SPM Interrupt Level group mask. */ -#define NVM_SPMLVL_gp 2 /* SPM Interrupt Level group position. */ -#define NVM_SPMLVL0_bm (1<<2) /* SPM Interrupt Level bit 0 mask. */ -#define NVM_SPMLVL0_bp 2 /* SPM Interrupt Level bit 0 position. */ -#define NVM_SPMLVL1_bm (1<<3) /* SPM Interrupt Level bit 1 mask. */ -#define NVM_SPMLVL1_bp 3 /* SPM Interrupt Level bit 1 position. */ - -#define NVM_EELVL_gm 0x03 /* EEPROM Interrupt Level group mask. */ -#define NVM_EELVL_gp 0 /* EEPROM Interrupt Level group position. */ -#define NVM_EELVL0_bm (1<<0) /* EEPROM Interrupt Level bit 0 mask. */ -#define NVM_EELVL0_bp 0 /* EEPROM Interrupt Level bit 0 position. */ -#define NVM_EELVL1_bm (1<<1) /* EEPROM Interrupt Level bit 1 mask. */ -#define NVM_EELVL1_bp 1 /* EEPROM Interrupt Level bit 1 position. */ - -/* NVM.STATUS bit masks and bit positions */ -#define NVM_NVMBUSY_bm 0x80 /* Non-volatile Memory Busy bit mask. */ -#define NVM_NVMBUSY_bp 7 /* Non-volatile Memory Busy bit position. */ - -#define NVM_FBUSY_bm 0x40 /* Flash Memory Busy bit mask. */ -#define NVM_FBUSY_bp 6 /* Flash Memory Busy bit position. */ - -#define NVM_EELOAD_bm 0x02 /* EEPROM Page Buffer Active Loading bit mask. */ -#define NVM_EELOAD_bp 1 /* EEPROM Page Buffer Active Loading bit position. */ - -#define NVM_FLOAD_bm 0x01 /* Flash Page Buffer Active Loading bit mask. */ -#define NVM_FLOAD_bp 0 /* Flash Page Buffer Active Loading bit position. */ - -/* NVM.LOCKBITS bit masks and bit positions */ -#define NVM_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ -#define NVM_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ -#define NVM_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ -#define NVM_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ -#define NVM_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ -#define NVM_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ - -#define NVM_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ -#define NVM_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ -#define NVM_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ -#define NVM_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ -#define NVM_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ -#define NVM_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ - -#define NVM_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ -#define NVM_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ -#define NVM_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ -#define NVM_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ -#define NVM_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ -#define NVM_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ - -#define NVM_LB_gm 0x03 /* Lock Bits group mask. */ -#define NVM_LB_gp 0 /* Lock Bits group position. */ -#define NVM_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ -#define NVM_LB0_bp 0 /* Lock Bits bit 0 position. */ -#define NVM_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ -#define NVM_LB1_bp 1 /* Lock Bits bit 1 position. */ - -/* ADC - Analog/Digital Converter */ -/* ADC_CH.CTRL bit masks and bit positions */ -#define ADC_CH_START_bm 0x80 /* Channel Start Conversion bit mask. */ -#define ADC_CH_START_bp 7 /* Channel Start Conversion bit position. */ - -#define ADC_CH_GAIN_gm 0x1C /* Gain Factor group mask. */ -#define ADC_CH_GAIN_gp 2 /* Gain Factor group position. */ -#define ADC_CH_GAIN0_bm (1<<2) /* Gain Factor bit 0 mask. */ -#define ADC_CH_GAIN0_bp 2 /* Gain Factor bit 0 position. */ -#define ADC_CH_GAIN1_bm (1<<3) /* Gain Factor bit 1 mask. */ -#define ADC_CH_GAIN1_bp 3 /* Gain Factor bit 1 position. */ -#define ADC_CH_GAIN2_bm (1<<4) /* Gain Factor bit 2 mask. */ -#define ADC_CH_GAIN2_bp 4 /* Gain Factor bit 2 position. */ - -#define ADC_CH_INPUTMODE_gm 0x03 /* Input Mode Select group mask. */ -#define ADC_CH_INPUTMODE_gp 0 /* Input Mode Select group position. */ -#define ADC_CH_INPUTMODE0_bm (1<<0) /* Input Mode Select bit 0 mask. */ -#define ADC_CH_INPUTMODE0_bp 0 /* Input Mode Select bit 0 position. */ -#define ADC_CH_INPUTMODE1_bm (1<<1) /* Input Mode Select bit 1 mask. */ -#define ADC_CH_INPUTMODE1_bp 1 /* Input Mode Select bit 1 position. */ - -/* ADC_CH.MUXCTRL bit masks and bit positions */ -#define ADC_CH_MUXPOS_gm 0x78 /* MUX selection on Positive ADC input group mask. */ -#define ADC_CH_MUXPOS_gp 3 /* MUX selection on Positive ADC input group position. */ -#define ADC_CH_MUXPOS0_bm (1<<3) /* MUX selection on Positive ADC input bit 0 mask. */ -#define ADC_CH_MUXPOS0_bp 3 /* MUX selection on Positive ADC input bit 0 position. */ -#define ADC_CH_MUXPOS1_bm (1<<4) /* MUX selection on Positive ADC input bit 1 mask. */ -#define ADC_CH_MUXPOS1_bp 4 /* MUX selection on Positive ADC input bit 1 position. */ -#define ADC_CH_MUXPOS2_bm (1<<5) /* MUX selection on Positive ADC input bit 2 mask. */ -#define ADC_CH_MUXPOS2_bp 5 /* MUX selection on Positive ADC input bit 2 position. */ -#define ADC_CH_MUXPOS3_bm (1<<6) /* MUX selection on Positive ADC input bit 3 mask. */ -#define ADC_CH_MUXPOS3_bp 6 /* MUX selection on Positive ADC input bit 3 position. */ - -#define ADC_CH_MUXINT_gm 0x78 /* MUX selection on Internal ADC input group mask. */ -#define ADC_CH_MUXINT_gp 3 /* MUX selection on Internal ADC input group position. */ -#define ADC_CH_MUXINT0_bm (1<<3) /* MUX selection on Internal ADC input bit 0 mask. */ -#define ADC_CH_MUXINT0_bp 3 /* MUX selection on Internal ADC input bit 0 position. */ -#define ADC_CH_MUXINT1_bm (1<<4) /* MUX selection on Internal ADC input bit 1 mask. */ -#define ADC_CH_MUXINT1_bp 4 /* MUX selection on Internal ADC input bit 1 position. */ -#define ADC_CH_MUXINT2_bm (1<<5) /* MUX selection on Internal ADC input bit 2 mask. */ -#define ADC_CH_MUXINT2_bp 5 /* MUX selection on Internal ADC input bit 2 position. */ -#define ADC_CH_MUXINT3_bm (1<<6) /* MUX selection on Internal ADC input bit 3 mask. */ -#define ADC_CH_MUXINT3_bp 6 /* MUX selection on Internal ADC input bit 3 position. */ - -#define ADC_CH_MUXNEG_gm 0x07 /* MUX selection on Negative ADC input group mask. */ -#define ADC_CH_MUXNEG_gp 0 /* MUX selection on Negative ADC input group position. */ -#define ADC_CH_MUXNEG0_bm (1<<0) /* MUX selection on Negative ADC input bit 0 mask. */ -#define ADC_CH_MUXNEG0_bp 0 /* MUX selection on Negative ADC input bit 0 position. */ -#define ADC_CH_MUXNEG1_bm (1<<1) /* MUX selection on Negative ADC input bit 1 mask. */ -#define ADC_CH_MUXNEG1_bp 1 /* MUX selection on Negative ADC input bit 1 position. */ -#define ADC_CH_MUXNEG2_bm (1<<2) /* MUX selection on Negative ADC input bit 2 mask. */ -#define ADC_CH_MUXNEG2_bp 2 /* MUX selection on Negative ADC input bit 2 position. */ - -/* ADC_CH.INTCTRL bit masks and bit positions */ -#define ADC_CH_INTMODE_gm 0x0C /* Interrupt Mode group mask. */ -#define ADC_CH_INTMODE_gp 2 /* Interrupt Mode group position. */ -#define ADC_CH_INTMODE0_bm (1<<2) /* Interrupt Mode bit 0 mask. */ -#define ADC_CH_INTMODE0_bp 2 /* Interrupt Mode bit 0 position. */ -#define ADC_CH_INTMODE1_bm (1<<3) /* Interrupt Mode bit 1 mask. */ -#define ADC_CH_INTMODE1_bp 3 /* Interrupt Mode bit 1 position. */ - -#define ADC_CH_INTLVL_gm 0x03 /* Interrupt Level group mask. */ -#define ADC_CH_INTLVL_gp 0 /* Interrupt Level group position. */ -#define ADC_CH_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */ -#define ADC_CH_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */ -#define ADC_CH_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ -#define ADC_CH_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */ - -/* ADC_CH.INTFLAGS bit masks and bit positions */ -#define ADC_CH_CHIF_bm 0x01 /* Channel Interrupt Flag bit mask. */ -#define ADC_CH_CHIF_bp 0 /* Channel Interrupt Flag bit position. */ - -/* ADC_CH.SCAN bit masks and bit positions */ -#define ADC_CH_OFFSET_gm 0xF0 /* Positive MUX setting offset group mask. */ -#define ADC_CH_OFFSET_gp 4 /* Positive MUX setting offset group position. */ -#define ADC_CH_OFFSET0_bm (1<<4) /* Positive MUX setting offset bit 0 mask. */ -#define ADC_CH_OFFSET0_bp 4 /* Positive MUX setting offset bit 0 position. */ -#define ADC_CH_OFFSET1_bm (1<<5) /* Positive MUX setting offset bit 1 mask. */ -#define ADC_CH_OFFSET1_bp 5 /* Positive MUX setting offset bit 1 position. */ -#define ADC_CH_OFFSET2_bm (1<<6) /* Positive MUX setting offset bit 2 mask. */ -#define ADC_CH_OFFSET2_bp 6 /* Positive MUX setting offset bit 2 position. */ -#define ADC_CH_OFFSET3_bm (1<<7) /* Positive MUX setting offset bit 3 mask. */ -#define ADC_CH_OFFSET3_bp 7 /* Positive MUX setting offset bit 3 position. */ - -#define ADC_CH_SCANNUM_gm 0x0F /* Number of Channels included in scan group mask. */ -#define ADC_CH_SCANNUM_gp 0 /* Number of Channels included in scan group position. */ -#define ADC_CH_SCANNUM0_bm (1<<0) /* Number of Channels included in scan bit 0 mask. */ -#define ADC_CH_SCANNUM0_bp 0 /* Number of Channels included in scan bit 0 position. */ -#define ADC_CH_SCANNUM1_bm (1<<1) /* Number of Channels included in scan bit 1 mask. */ -#define ADC_CH_SCANNUM1_bp 1 /* Number of Channels included in scan bit 1 position. */ -#define ADC_CH_SCANNUM2_bm (1<<2) /* Number of Channels included in scan bit 2 mask. */ -#define ADC_CH_SCANNUM2_bp 2 /* Number of Channels included in scan bit 2 position. */ -#define ADC_CH_SCANNUM3_bm (1<<3) /* Number of Channels included in scan bit 3 mask. */ -#define ADC_CH_SCANNUM3_bp 3 /* Number of Channels included in scan bit 3 position. */ - -/* ADC.CTRLA bit masks and bit positions */ -#define ADC_DMASEL_gm 0xC0 /* DMA Selection group mask. */ -#define ADC_DMASEL_gp 6 /* DMA Selection group position. */ -#define ADC_DMASEL0_bm (1<<6) /* DMA Selection bit 0 mask. */ -#define ADC_DMASEL0_bp 6 /* DMA Selection bit 0 position. */ -#define ADC_DMASEL1_bm (1<<7) /* DMA Selection bit 1 mask. */ -#define ADC_DMASEL1_bp 7 /* DMA Selection bit 1 position. */ - -#define ADC_CH3START_bm 0x20 /* Channel 3 Start Conversion bit mask. */ -#define ADC_CH3START_bp 5 /* Channel 3 Start Conversion bit position. */ - -#define ADC_CH2START_bm 0x10 /* Channel 2 Start Conversion bit mask. */ -#define ADC_CH2START_bp 4 /* Channel 2 Start Conversion bit position. */ - -#define ADC_CH1START_bm 0x08 /* Channel 1 Start Conversion bit mask. */ -#define ADC_CH1START_bp 3 /* Channel 1 Start Conversion bit position. */ - -#define ADC_CH0START_bm 0x04 /* Channel 0 Start Conversion bit mask. */ -#define ADC_CH0START_bp 2 /* Channel 0 Start Conversion bit position. */ - -#define ADC_FLUSH_bm 0x02 /* Flush Pipeline bit mask. */ -#define ADC_FLUSH_bp 1 /* Flush Pipeline bit position. */ - -#define ADC_ENABLE_bm 0x01 /* Enable ADC bit mask. */ -#define ADC_ENABLE_bp 0 /* Enable ADC bit position. */ - -/* ADC.CTRLB bit masks and bit positions */ -#define ADC_IMPMODE_bm 0x80 /* Gain Stage Impedance Mode bit mask. */ -#define ADC_IMPMODE_bp 7 /* Gain Stage Impedance Mode bit position. */ - -#define ADC_CURRLIMIT_gm 0x60 /* Current Limitation group mask. */ -#define ADC_CURRLIMIT_gp 5 /* Current Limitation group position. */ -#define ADC_CURRLIMIT0_bm (1<<5) /* Current Limitation bit 0 mask. */ -#define ADC_CURRLIMIT0_bp 5 /* Current Limitation bit 0 position. */ -#define ADC_CURRLIMIT1_bm (1<<6) /* Current Limitation bit 1 mask. */ -#define ADC_CURRLIMIT1_bp 6 /* Current Limitation bit 1 position. */ - -#define ADC_CONMODE_bm 0x10 /* Conversion Mode bit mask. */ -#define ADC_CONMODE_bp 4 /* Conversion Mode bit position. */ - -#define ADC_FREERUN_bm 0x08 /* Free Running Mode Enable bit mask. */ -#define ADC_FREERUN_bp 3 /* Free Running Mode Enable bit position. */ - -#define ADC_RESOLUTION_gm 0x06 /* Result Resolution group mask. */ -#define ADC_RESOLUTION_gp 1 /* Result Resolution group position. */ -#define ADC_RESOLUTION0_bm (1<<1) /* Result Resolution bit 0 mask. */ -#define ADC_RESOLUTION0_bp 1 /* Result Resolution bit 0 position. */ -#define ADC_RESOLUTION1_bm (1<<2) /* Result Resolution bit 1 mask. */ -#define ADC_RESOLUTION1_bp 2 /* Result Resolution bit 1 position. */ - -/* ADC.REFCTRL bit masks and bit positions */ -#define ADC_REFSEL_gm 0x70 /* Reference Selection group mask. */ -#define ADC_REFSEL_gp 4 /* Reference Selection group position. */ -#define ADC_REFSEL0_bm (1<<4) /* Reference Selection bit 0 mask. */ -#define ADC_REFSEL0_bp 4 /* Reference Selection bit 0 position. */ -#define ADC_REFSEL1_bm (1<<5) /* Reference Selection bit 1 mask. */ -#define ADC_REFSEL1_bp 5 /* Reference Selection bit 1 position. */ -#define ADC_REFSEL2_bm (1<<6) /* Reference Selection bit 2 mask. */ -#define ADC_REFSEL2_bp 6 /* Reference Selection bit 2 position. */ - -#define ADC_BANDGAP_bm 0x02 /* Bandgap enable bit mask. */ -#define ADC_BANDGAP_bp 1 /* Bandgap enable bit position. */ - -#define ADC_TEMPREF_bm 0x01 /* Temperature Reference Enable bit mask. */ -#define ADC_TEMPREF_bp 0 /* Temperature Reference Enable bit position. */ - -/* ADC.EVCTRL bit masks and bit positions */ -#define ADC_SWEEP_gm 0xC0 /* Channel Sweep Selection group mask. */ -#define ADC_SWEEP_gp 6 /* Channel Sweep Selection group position. */ -#define ADC_SWEEP0_bm (1<<6) /* Channel Sweep Selection bit 0 mask. */ -#define ADC_SWEEP0_bp 6 /* Channel Sweep Selection bit 0 position. */ -#define ADC_SWEEP1_bm (1<<7) /* Channel Sweep Selection bit 1 mask. */ -#define ADC_SWEEP1_bp 7 /* Channel Sweep Selection bit 1 position. */ - -#define ADC_EVSEL_gm 0x38 /* Event Input Select group mask. */ -#define ADC_EVSEL_gp 3 /* Event Input Select group position. */ -#define ADC_EVSEL0_bm (1<<3) /* Event Input Select bit 0 mask. */ -#define ADC_EVSEL0_bp 3 /* Event Input Select bit 0 position. */ -#define ADC_EVSEL1_bm (1<<4) /* Event Input Select bit 1 mask. */ -#define ADC_EVSEL1_bp 4 /* Event Input Select bit 1 position. */ -#define ADC_EVSEL2_bm (1<<5) /* Event Input Select bit 2 mask. */ -#define ADC_EVSEL2_bp 5 /* Event Input Select bit 2 position. */ - -#define ADC_EVACT_gm 0x07 /* Event Action Select group mask. */ -#define ADC_EVACT_gp 0 /* Event Action Select group position. */ -#define ADC_EVACT0_bm (1<<0) /* Event Action Select bit 0 mask. */ -#define ADC_EVACT0_bp 0 /* Event Action Select bit 0 position. */ -#define ADC_EVACT1_bm (1<<1) /* Event Action Select bit 1 mask. */ -#define ADC_EVACT1_bp 1 /* Event Action Select bit 1 position. */ -#define ADC_EVACT2_bm (1<<2) /* Event Action Select bit 2 mask. */ -#define ADC_EVACT2_bp 2 /* Event Action Select bit 2 position. */ - -/* ADC.PRESCALER bit masks and bit positions */ -#define ADC_PRESCALER_gm 0x07 /* Clock Prescaler Selection group mask. */ -#define ADC_PRESCALER_gp 0 /* Clock Prescaler Selection group position. */ -#define ADC_PRESCALER0_bm (1<<0) /* Clock Prescaler Selection bit 0 mask. */ -#define ADC_PRESCALER0_bp 0 /* Clock Prescaler Selection bit 0 position. */ -#define ADC_PRESCALER1_bm (1<<1) /* Clock Prescaler Selection bit 1 mask. */ -#define ADC_PRESCALER1_bp 1 /* Clock Prescaler Selection bit 1 position. */ -#define ADC_PRESCALER2_bm (1<<2) /* Clock Prescaler Selection bit 2 mask. */ -#define ADC_PRESCALER2_bp 2 /* Clock Prescaler Selection bit 2 position. */ - -/* ADC.INTFLAGS bit masks and bit positions */ -#define ADC_CH3IF_bm 0x08 /* Channel 3 Interrupt Flag bit mask. */ -#define ADC_CH3IF_bp 3 /* Channel 3 Interrupt Flag bit position. */ - -#define ADC_CH2IF_bm 0x04 /* Channel 2 Interrupt Flag bit mask. */ -#define ADC_CH2IF_bp 2 /* Channel 2 Interrupt Flag bit position. */ - -#define ADC_CH1IF_bm 0x02 /* Channel 1 Interrupt Flag bit mask. */ -#define ADC_CH1IF_bp 1 /* Channel 1 Interrupt Flag bit position. */ - -#define ADC_CH0IF_bm 0x01 /* Channel 0 Interrupt Flag bit mask. */ -#define ADC_CH0IF_bp 0 /* Channel 0 Interrupt Flag bit position. */ - -/* DAC - Digital/Analog Converter */ -/* DAC.CTRLA bit masks and bit positions */ -#define DAC_IDOEN_bm 0x10 /* Internal Output Enable bit mask. */ -#define DAC_IDOEN_bp 4 /* Internal Output Enable bit position. */ - -#define DAC_CH1EN_bm 0x08 /* Channel 1 Output Enable bit mask. */ -#define DAC_CH1EN_bp 3 /* Channel 1 Output Enable bit position. */ - -#define DAC_CH0EN_bm 0x04 /* Channel 0 Output Enable bit mask. */ -#define DAC_CH0EN_bp 2 /* Channel 0 Output Enable bit position. */ - -#define DAC_LPMODE_bm 0x02 /* Low Power Mode bit mask. */ -#define DAC_LPMODE_bp 1 /* Low Power Mode bit position. */ - -#define DAC_ENABLE_bm 0x01 /* Enable bit mask. */ -#define DAC_ENABLE_bp 0 /* Enable bit position. */ - -/* DAC.CTRLB bit masks and bit positions */ -#define DAC_CHSEL_gm 0x60 /* Channel Select group mask. */ -#define DAC_CHSEL_gp 5 /* Channel Select group position. */ -#define DAC_CHSEL0_bm (1<<5) /* Channel Select bit 0 mask. */ -#define DAC_CHSEL0_bp 5 /* Channel Select bit 0 position. */ -#define DAC_CHSEL1_bm (1<<6) /* Channel Select bit 1 mask. */ -#define DAC_CHSEL1_bp 6 /* Channel Select bit 1 position. */ - -#define DAC_CH1TRIG_bm 0x02 /* Channel 1 Event Trig Enable bit mask. */ -#define DAC_CH1TRIG_bp 1 /* Channel 1 Event Trig Enable bit position. */ - -#define DAC_CH0TRIG_bm 0x01 /* Channel 0 Event Trig Enable bit mask. */ -#define DAC_CH0TRIG_bp 0 /* Channel 0 Event Trig Enable bit position. */ - -/* DAC.CTRLC bit masks and bit positions */ -#define DAC_REFSEL_gm 0x18 /* Reference Select group mask. */ -#define DAC_REFSEL_gp 3 /* Reference Select group position. */ -#define DAC_REFSEL0_bm (1<<3) /* Reference Select bit 0 mask. */ -#define DAC_REFSEL0_bp 3 /* Reference Select bit 0 position. */ -#define DAC_REFSEL1_bm (1<<4) /* Reference Select bit 1 mask. */ -#define DAC_REFSEL1_bp 4 /* Reference Select bit 1 position. */ - -#define DAC_LEFTADJ_bm 0x01 /* Left-adjust Result bit mask. */ -#define DAC_LEFTADJ_bp 0 /* Left-adjust Result bit position. */ - -/* DAC.EVCTRL bit masks and bit positions */ -#define DAC_EVSPLIT_bm 0x08 /* Separate Event Channel Input for Channel 1 bit mask. */ -#define DAC_EVSPLIT_bp 3 /* Separate Event Channel Input for Channel 1 bit position. */ - -#define DAC_EVSEL_gm 0x07 /* Event Input Selection group mask. */ -#define DAC_EVSEL_gp 0 /* Event Input Selection group position. */ -#define DAC_EVSEL0_bm (1<<0) /* Event Input Selection bit 0 mask. */ -#define DAC_EVSEL0_bp 0 /* Event Input Selection bit 0 position. */ -#define DAC_EVSEL1_bm (1<<1) /* Event Input Selection bit 1 mask. */ -#define DAC_EVSEL1_bp 1 /* Event Input Selection bit 1 position. */ -#define DAC_EVSEL2_bm (1<<2) /* Event Input Selection bit 2 mask. */ -#define DAC_EVSEL2_bp 2 /* Event Input Selection bit 2 position. */ - -/* DAC.STATUS bit masks and bit positions */ -#define DAC_CH1DRE_bm 0x02 /* Channel 1 Data Register Empty bit mask. */ -#define DAC_CH1DRE_bp 1 /* Channel 1 Data Register Empty bit position. */ - -#define DAC_CH0DRE_bm 0x01 /* Channel 0 Data Register Empty bit mask. */ -#define DAC_CH0DRE_bp 0 /* Channel 0 Data Register Empty bit position. */ - -/* DAC.CH0GAINCAL bit masks and bit positions */ -#define DAC_CH0GAINCAL_gm 0x7F /* Gain Calibration group mask. */ -#define DAC_CH0GAINCAL_gp 0 /* Gain Calibration group position. */ -#define DAC_CH0GAINCAL0_bm (1<<0) /* Gain Calibration bit 0 mask. */ -#define DAC_CH0GAINCAL0_bp 0 /* Gain Calibration bit 0 position. */ -#define DAC_CH0GAINCAL1_bm (1<<1) /* Gain Calibration bit 1 mask. */ -#define DAC_CH0GAINCAL1_bp 1 /* Gain Calibration bit 1 position. */ -#define DAC_CH0GAINCAL2_bm (1<<2) /* Gain Calibration bit 2 mask. */ -#define DAC_CH0GAINCAL2_bp 2 /* Gain Calibration bit 2 position. */ -#define DAC_CH0GAINCAL3_bm (1<<3) /* Gain Calibration bit 3 mask. */ -#define DAC_CH0GAINCAL3_bp 3 /* Gain Calibration bit 3 position. */ -#define DAC_CH0GAINCAL4_bm (1<<4) /* Gain Calibration bit 4 mask. */ -#define DAC_CH0GAINCAL4_bp 4 /* Gain Calibration bit 4 position. */ -#define DAC_CH0GAINCAL5_bm (1<<5) /* Gain Calibration bit 5 mask. */ -#define DAC_CH0GAINCAL5_bp 5 /* Gain Calibration bit 5 position. */ -#define DAC_CH0GAINCAL6_bm (1<<6) /* Gain Calibration bit 6 mask. */ -#define DAC_CH0GAINCAL6_bp 6 /* Gain Calibration bit 6 position. */ - -/* DAC.CH0OFFSETCAL bit masks and bit positions */ -#define DAC_CH0OFFSETCAL_gm 0x7F /* Offset Calibration group mask. */ -#define DAC_CH0OFFSETCAL_gp 0 /* Offset Calibration group position. */ -#define DAC_CH0OFFSETCAL0_bm (1<<0) /* Offset Calibration bit 0 mask. */ -#define DAC_CH0OFFSETCAL0_bp 0 /* Offset Calibration bit 0 position. */ -#define DAC_CH0OFFSETCAL1_bm (1<<1) /* Offset Calibration bit 1 mask. */ -#define DAC_CH0OFFSETCAL1_bp 1 /* Offset Calibration bit 1 position. */ -#define DAC_CH0OFFSETCAL2_bm (1<<2) /* Offset Calibration bit 2 mask. */ -#define DAC_CH0OFFSETCAL2_bp 2 /* Offset Calibration bit 2 position. */ -#define DAC_CH0OFFSETCAL3_bm (1<<3) /* Offset Calibration bit 3 mask. */ -#define DAC_CH0OFFSETCAL3_bp 3 /* Offset Calibration bit 3 position. */ -#define DAC_CH0OFFSETCAL4_bm (1<<4) /* Offset Calibration bit 4 mask. */ -#define DAC_CH0OFFSETCAL4_bp 4 /* Offset Calibration bit 4 position. */ -#define DAC_CH0OFFSETCAL5_bm (1<<5) /* Offset Calibration bit 5 mask. */ -#define DAC_CH0OFFSETCAL5_bp 5 /* Offset Calibration bit 5 position. */ -#define DAC_CH0OFFSETCAL6_bm (1<<6) /* Offset Calibration bit 6 mask. */ -#define DAC_CH0OFFSETCAL6_bp 6 /* Offset Calibration bit 6 position. */ - -/* DAC.CH1GAINCAL bit masks and bit positions */ -#define DAC_CH1GAINCAL_gm 0x7F /* Gain Calibration group mask. */ -#define DAC_CH1GAINCAL_gp 0 /* Gain Calibration group position. */ -#define DAC_CH1GAINCAL0_bm (1<<0) /* Gain Calibration bit 0 mask. */ -#define DAC_CH1GAINCAL0_bp 0 /* Gain Calibration bit 0 position. */ -#define DAC_CH1GAINCAL1_bm (1<<1) /* Gain Calibration bit 1 mask. */ -#define DAC_CH1GAINCAL1_bp 1 /* Gain Calibration bit 1 position. */ -#define DAC_CH1GAINCAL2_bm (1<<2) /* Gain Calibration bit 2 mask. */ -#define DAC_CH1GAINCAL2_bp 2 /* Gain Calibration bit 2 position. */ -#define DAC_CH1GAINCAL3_bm (1<<3) /* Gain Calibration bit 3 mask. */ -#define DAC_CH1GAINCAL3_bp 3 /* Gain Calibration bit 3 position. */ -#define DAC_CH1GAINCAL4_bm (1<<4) /* Gain Calibration bit 4 mask. */ -#define DAC_CH1GAINCAL4_bp 4 /* Gain Calibration bit 4 position. */ -#define DAC_CH1GAINCAL5_bm (1<<5) /* Gain Calibration bit 5 mask. */ -#define DAC_CH1GAINCAL5_bp 5 /* Gain Calibration bit 5 position. */ -#define DAC_CH1GAINCAL6_bm (1<<6) /* Gain Calibration bit 6 mask. */ -#define DAC_CH1GAINCAL6_bp 6 /* Gain Calibration bit 6 position. */ - -/* DAC.CH1OFFSETCAL bit masks and bit positions */ -#define DAC_CH1OFFSETCAL_gm 0x7F /* Offset Calibration group mask. */ -#define DAC_CH1OFFSETCAL_gp 0 /* Offset Calibration group position. */ -#define DAC_CH1OFFSETCAL0_bm (1<<0) /* Offset Calibration bit 0 mask. */ -#define DAC_CH1OFFSETCAL0_bp 0 /* Offset Calibration bit 0 position. */ -#define DAC_CH1OFFSETCAL1_bm (1<<1) /* Offset Calibration bit 1 mask. */ -#define DAC_CH1OFFSETCAL1_bp 1 /* Offset Calibration bit 1 position. */ -#define DAC_CH1OFFSETCAL2_bm (1<<2) /* Offset Calibration bit 2 mask. */ -#define DAC_CH1OFFSETCAL2_bp 2 /* Offset Calibration bit 2 position. */ -#define DAC_CH1OFFSETCAL3_bm (1<<3) /* Offset Calibration bit 3 mask. */ -#define DAC_CH1OFFSETCAL3_bp 3 /* Offset Calibration bit 3 position. */ -#define DAC_CH1OFFSETCAL4_bm (1<<4) /* Offset Calibration bit 4 mask. */ -#define DAC_CH1OFFSETCAL4_bp 4 /* Offset Calibration bit 4 position. */ -#define DAC_CH1OFFSETCAL5_bm (1<<5) /* Offset Calibration bit 5 mask. */ -#define DAC_CH1OFFSETCAL5_bp 5 /* Offset Calibration bit 5 position. */ -#define DAC_CH1OFFSETCAL6_bm (1<<6) /* Offset Calibration bit 6 mask. */ -#define DAC_CH1OFFSETCAL6_bp 6 /* Offset Calibration bit 6 position. */ - -/* AC - Analog Comparator */ -/* AC.AC0CTRL bit masks and bit positions */ -#define AC_INTMODE_gm 0xC0 /* Interrupt Mode group mask. */ -#define AC_INTMODE_gp 6 /* Interrupt Mode group position. */ -#define AC_INTMODE0_bm (1<<6) /* Interrupt Mode bit 0 mask. */ -#define AC_INTMODE0_bp 6 /* Interrupt Mode bit 0 position. */ -#define AC_INTMODE1_bm (1<<7) /* Interrupt Mode bit 1 mask. */ -#define AC_INTMODE1_bp 7 /* Interrupt Mode bit 1 position. */ - -#define AC_INTLVL_gm 0x30 /* Interrupt Level group mask. */ -#define AC_INTLVL_gp 4 /* Interrupt Level group position. */ -#define AC_INTLVL0_bm (1<<4) /* Interrupt Level bit 0 mask. */ -#define AC_INTLVL0_bp 4 /* Interrupt Level bit 0 position. */ -#define AC_INTLVL1_bm (1<<5) /* Interrupt Level bit 1 mask. */ -#define AC_INTLVL1_bp 5 /* Interrupt Level bit 1 position. */ - -#define AC_HSMODE_bm 0x08 /* High-speed Mode bit mask. */ -#define AC_HSMODE_bp 3 /* High-speed Mode bit position. */ - -#define AC_HYSMODE_gm 0x06 /* Hysteresis Mode group mask. */ -#define AC_HYSMODE_gp 1 /* Hysteresis Mode group position. */ -#define AC_HYSMODE0_bm (1<<1) /* Hysteresis Mode bit 0 mask. */ -#define AC_HYSMODE0_bp 1 /* Hysteresis Mode bit 0 position. */ -#define AC_HYSMODE1_bm (1<<2) /* Hysteresis Mode bit 1 mask. */ -#define AC_HYSMODE1_bp 2 /* Hysteresis Mode bit 1 position. */ - -#define AC_ENABLE_bm 0x01 /* Enable bit mask. */ -#define AC_ENABLE_bp 0 /* Enable bit position. */ - -/* AC.AC1CTRL bit masks and bit positions */ -/* AC_INTMODE Predefined. */ -/* AC_INTMODE Predefined. */ - -/* AC_INTLVL Predefined. */ -/* AC_INTLVL Predefined. */ - -/* AC_HSMODE Predefined. */ -/* AC_HSMODE Predefined. */ - -/* AC_HYSMODE Predefined. */ -/* AC_HYSMODE Predefined. */ - -/* AC_ENABLE Predefined. */ -/* AC_ENABLE Predefined. */ - -/* AC.AC0MUXCTRL bit masks and bit positions */ -#define AC_MUXPOS_gm 0x38 /* MUX Positive Input group mask. */ -#define AC_MUXPOS_gp 3 /* MUX Positive Input group position. */ -#define AC_MUXPOS0_bm (1<<3) /* MUX Positive Input bit 0 mask. */ -#define AC_MUXPOS0_bp 3 /* MUX Positive Input bit 0 position. */ -#define AC_MUXPOS1_bm (1<<4) /* MUX Positive Input bit 1 mask. */ -#define AC_MUXPOS1_bp 4 /* MUX Positive Input bit 1 position. */ -#define AC_MUXPOS2_bm (1<<5) /* MUX Positive Input bit 2 mask. */ -#define AC_MUXPOS2_bp 5 /* MUX Positive Input bit 2 position. */ - -#define AC_MUXNEG_gm 0x07 /* MUX Negative Input group mask. */ -#define AC_MUXNEG_gp 0 /* MUX Negative Input group position. */ -#define AC_MUXNEG0_bm (1<<0) /* MUX Negative Input bit 0 mask. */ -#define AC_MUXNEG0_bp 0 /* MUX Negative Input bit 0 position. */ -#define AC_MUXNEG1_bm (1<<1) /* MUX Negative Input bit 1 mask. */ -#define AC_MUXNEG1_bp 1 /* MUX Negative Input bit 1 position. */ -#define AC_MUXNEG2_bm (1<<2) /* MUX Negative Input bit 2 mask. */ -#define AC_MUXNEG2_bp 2 /* MUX Negative Input bit 2 position. */ - -/* AC.AC1MUXCTRL bit masks and bit positions */ -/* AC_MUXPOS Predefined. */ -/* AC_MUXPOS Predefined. */ - -/* AC_MUXNEG Predefined. */ -/* AC_MUXNEG Predefined. */ - -/* AC.CTRLA bit masks and bit positions */ -#define AC_AC1OUT_bm 0x02 /* Analog Comparator 1 Output Enable bit mask. */ -#define AC_AC1OUT_bp 1 /* Analog Comparator 1 Output Enable bit position. */ - -#define AC_AC0OUT_bm 0x01 /* Analog Comparator 0 Output Enable bit mask. */ -#define AC_AC0OUT_bp 0 /* Analog Comparator 0 Output Enable bit position. */ - -/* AC.CTRLB bit masks and bit positions */ -#define AC_SCALEFAC_gm 0x3F /* VCC Voltage Scaler Factor group mask. */ -#define AC_SCALEFAC_gp 0 /* VCC Voltage Scaler Factor group position. */ -#define AC_SCALEFAC0_bm (1<<0) /* VCC Voltage Scaler Factor bit 0 mask. */ -#define AC_SCALEFAC0_bp 0 /* VCC Voltage Scaler Factor bit 0 position. */ -#define AC_SCALEFAC1_bm (1<<1) /* VCC Voltage Scaler Factor bit 1 mask. */ -#define AC_SCALEFAC1_bp 1 /* VCC Voltage Scaler Factor bit 1 position. */ -#define AC_SCALEFAC2_bm (1<<2) /* VCC Voltage Scaler Factor bit 2 mask. */ -#define AC_SCALEFAC2_bp 2 /* VCC Voltage Scaler Factor bit 2 position. */ -#define AC_SCALEFAC3_bm (1<<3) /* VCC Voltage Scaler Factor bit 3 mask. */ -#define AC_SCALEFAC3_bp 3 /* VCC Voltage Scaler Factor bit 3 position. */ -#define AC_SCALEFAC4_bm (1<<4) /* VCC Voltage Scaler Factor bit 4 mask. */ -#define AC_SCALEFAC4_bp 4 /* VCC Voltage Scaler Factor bit 4 position. */ -#define AC_SCALEFAC5_bm (1<<5) /* VCC Voltage Scaler Factor bit 5 mask. */ -#define AC_SCALEFAC5_bp 5 /* VCC Voltage Scaler Factor bit 5 position. */ - -/* AC.WINCTRL bit masks and bit positions */ -#define AC_WEN_bm 0x10 /* Window Mode Enable bit mask. */ -#define AC_WEN_bp 4 /* Window Mode Enable bit position. */ - -#define AC_WINTMODE_gm 0x0C /* Window Interrupt Mode group mask. */ -#define AC_WINTMODE_gp 2 /* Window Interrupt Mode group position. */ -#define AC_WINTMODE0_bm (1<<2) /* Window Interrupt Mode bit 0 mask. */ -#define AC_WINTMODE0_bp 2 /* Window Interrupt Mode bit 0 position. */ -#define AC_WINTMODE1_bm (1<<3) /* Window Interrupt Mode bit 1 mask. */ -#define AC_WINTMODE1_bp 3 /* Window Interrupt Mode bit 1 position. */ - -#define AC_WINTLVL_gm 0x03 /* Window Interrupt Level group mask. */ -#define AC_WINTLVL_gp 0 /* Window Interrupt Level group position. */ -#define AC_WINTLVL0_bm (1<<0) /* Window Interrupt Level bit 0 mask. */ -#define AC_WINTLVL0_bp 0 /* Window Interrupt Level bit 0 position. */ -#define AC_WINTLVL1_bm (1<<1) /* Window Interrupt Level bit 1 mask. */ -#define AC_WINTLVL1_bp 1 /* Window Interrupt Level bit 1 position. */ - -/* AC.STATUS bit masks and bit positions */ -#define AC_WSTATE_gm 0xC0 /* Window Mode State group mask. */ -#define AC_WSTATE_gp 6 /* Window Mode State group position. */ -#define AC_WSTATE0_bm (1<<6) /* Window Mode State bit 0 mask. */ -#define AC_WSTATE0_bp 6 /* Window Mode State bit 0 position. */ -#define AC_WSTATE1_bm (1<<7) /* Window Mode State bit 1 mask. */ -#define AC_WSTATE1_bp 7 /* Window Mode State bit 1 position. */ - -#define AC_AC1STATE_bm 0x20 /* Analog Comparator 1 State bit mask. */ -#define AC_AC1STATE_bp 5 /* Analog Comparator 1 State bit position. */ - -#define AC_AC0STATE_bm 0x10 /* Analog Comparator 0 State bit mask. */ -#define AC_AC0STATE_bp 4 /* Analog Comparator 0 State bit position. */ - -#define AC_WIF_bm 0x04 /* Window Mode Interrupt Flag bit mask. */ -#define AC_WIF_bp 2 /* Window Mode Interrupt Flag bit position. */ - -#define AC_AC1IF_bm 0x02 /* Analog Comparator 1 Interrupt Flag bit mask. */ -#define AC_AC1IF_bp 1 /* Analog Comparator 1 Interrupt Flag bit position. */ - -#define AC_AC0IF_bm 0x01 /* Analog Comparator 0 Interrupt Flag bit mask. */ -#define AC_AC0IF_bp 0 /* Analog Comparator 0 Interrupt Flag bit position. */ - -/* RTC32 - 32-bit Real-Time Counter */ -/* RTC32.CTRL bit masks and bit positions */ -#define RTC32_ENABLE_bm 0x01 /* RTC enable bit mask. */ -#define RTC32_ENABLE_bp 0 /* RTC enable bit position. */ - -/* RTC32.SYNCCTRL bit masks and bit positions */ -#define RTC32_SYNCCNT_bm 0x10 /* Synchronization Busy Flag bit mask. */ -#define RTC32_SYNCCNT_bp 4 /* Synchronization Busy Flag bit position. */ - -#define RTC32_SYNCBUSY_bm 0x01 /* Synchronization Busy Flag bit mask. */ -#define RTC32_SYNCBUSY_bp 0 /* Synchronization Busy Flag bit position. */ - -/* RTC32.INTCTRL bit masks and bit positions */ -#define RTC32_COMPINTLVL_gm 0x0C /* Compare Match Interrupt Level group mask. */ -#define RTC32_COMPINTLVL_gp 2 /* Compare Match Interrupt Level group position. */ -#define RTC32_COMPINTLVL0_bm (1<<2) /* Compare Match Interrupt Level bit 0 mask. */ -#define RTC32_COMPINTLVL0_bp 2 /* Compare Match Interrupt Level bit 0 position. */ -#define RTC32_COMPINTLVL1_bm (1<<3) /* Compare Match Interrupt Level bit 1 mask. */ -#define RTC32_COMPINTLVL1_bp 3 /* Compare Match Interrupt Level bit 1 position. */ - -#define RTC32_OVFINTLVL_gm 0x03 /* Overflow Interrupt Level group mask. */ -#define RTC32_OVFINTLVL_gp 0 /* Overflow Interrupt Level group position. */ -#define RTC32_OVFINTLVL0_bm (1<<0) /* Overflow Interrupt Level bit 0 mask. */ -#define RTC32_OVFINTLVL0_bp 0 /* Overflow Interrupt Level bit 0 position. */ -#define RTC32_OVFINTLVL1_bm (1<<1) /* Overflow Interrupt Level bit 1 mask. */ -#define RTC32_OVFINTLVL1_bp 1 /* Overflow Interrupt Level bit 1 position. */ - -/* RTC32.INTFLAGS bit masks and bit positions */ -#define RTC32_COMPIF_bm 0x02 /* Compare Match Interrupt Flag bit mask. */ -#define RTC32_COMPIF_bp 1 /* Compare Match Interrupt Flag bit position. */ - -#define RTC32_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ -#define RTC32_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ - -/* TWI - Two-Wire Interface */ -/* TWI_MASTER.CTRLA bit masks and bit positions */ -#define TWI_MASTER_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ -#define TWI_MASTER_INTLVL_gp 6 /* Interrupt Level group position. */ -#define TWI_MASTER_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ -#define TWI_MASTER_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ -#define TWI_MASTER_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ -#define TWI_MASTER_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ - -#define TWI_MASTER_RIEN_bm 0x20 /* Read Interrupt Enable bit mask. */ -#define TWI_MASTER_RIEN_bp 5 /* Read Interrupt Enable bit position. */ - -#define TWI_MASTER_WIEN_bm 0x10 /* Write Interrupt Enable bit mask. */ -#define TWI_MASTER_WIEN_bp 4 /* Write Interrupt Enable bit position. */ - -#define TWI_MASTER_ENABLE_bm 0x08 /* Enable TWI Master bit mask. */ -#define TWI_MASTER_ENABLE_bp 3 /* Enable TWI Master bit position. */ - -/* TWI_MASTER.CTRLB bit masks and bit positions */ -#define TWI_MASTER_TIMEOUT_gm 0x0C /* Inactive Bus Timeout group mask. */ -#define TWI_MASTER_TIMEOUT_gp 2 /* Inactive Bus Timeout group position. */ -#define TWI_MASTER_TIMEOUT0_bm (1<<2) /* Inactive Bus Timeout bit 0 mask. */ -#define TWI_MASTER_TIMEOUT0_bp 2 /* Inactive Bus Timeout bit 0 position. */ -#define TWI_MASTER_TIMEOUT1_bm (1<<3) /* Inactive Bus Timeout bit 1 mask. */ -#define TWI_MASTER_TIMEOUT1_bp 3 /* Inactive Bus Timeout bit 1 position. */ - -#define TWI_MASTER_QCEN_bm 0x02 /* Quick Command Enable bit mask. */ -#define TWI_MASTER_QCEN_bp 1 /* Quick Command Enable bit position. */ - -#define TWI_MASTER_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ -#define TWI_MASTER_SMEN_bp 0 /* Smart Mode Enable bit position. */ - -/* TWI_MASTER.CTRLC bit masks and bit positions */ -#define TWI_MASTER_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ -#define TWI_MASTER_ACKACT_bp 2 /* Acknowledge Action bit position. */ - -#define TWI_MASTER_CMD_gm 0x03 /* Command group mask. */ -#define TWI_MASTER_CMD_gp 0 /* Command group position. */ -#define TWI_MASTER_CMD0_bm (1<<0) /* Command bit 0 mask. */ -#define TWI_MASTER_CMD0_bp 0 /* Command bit 0 position. */ -#define TWI_MASTER_CMD1_bm (1<<1) /* Command bit 1 mask. */ -#define TWI_MASTER_CMD1_bp 1 /* Command bit 1 position. */ - -/* TWI_MASTER.STATUS bit masks and bit positions */ -#define TWI_MASTER_RIF_bm 0x80 /* Read Interrupt Flag bit mask. */ -#define TWI_MASTER_RIF_bp 7 /* Read Interrupt Flag bit position. */ - -#define TWI_MASTER_WIF_bm 0x40 /* Write Interrupt Flag bit mask. */ -#define TWI_MASTER_WIF_bp 6 /* Write Interrupt Flag bit position. */ - -#define TWI_MASTER_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ -#define TWI_MASTER_CLKHOLD_bp 5 /* Clock Hold bit position. */ - -#define TWI_MASTER_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ -#define TWI_MASTER_RXACK_bp 4 /* Received Acknowledge bit position. */ - -#define TWI_MASTER_ARBLOST_bm 0x08 /* Arbitration Lost bit mask. */ -#define TWI_MASTER_ARBLOST_bp 3 /* Arbitration Lost bit position. */ - -#define TWI_MASTER_BUSERR_bm 0x04 /* Bus Error bit mask. */ -#define TWI_MASTER_BUSERR_bp 2 /* Bus Error bit position. */ - -#define TWI_MASTER_BUSSTATE_gm 0x03 /* Bus State group mask. */ -#define TWI_MASTER_BUSSTATE_gp 0 /* Bus State group position. */ -#define TWI_MASTER_BUSSTATE0_bm (1<<0) /* Bus State bit 0 mask. */ -#define TWI_MASTER_BUSSTATE0_bp 0 /* Bus State bit 0 position. */ -#define TWI_MASTER_BUSSTATE1_bm (1<<1) /* Bus State bit 1 mask. */ -#define TWI_MASTER_BUSSTATE1_bp 1 /* Bus State bit 1 position. */ - -/* TWI_SLAVE.CTRLA bit masks and bit positions */ -#define TWI_SLAVE_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ -#define TWI_SLAVE_INTLVL_gp 6 /* Interrupt Level group position. */ -#define TWI_SLAVE_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ -#define TWI_SLAVE_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ -#define TWI_SLAVE_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ -#define TWI_SLAVE_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ - -#define TWI_SLAVE_DIEN_bm 0x20 /* Data Interrupt Enable bit mask. */ -#define TWI_SLAVE_DIEN_bp 5 /* Data Interrupt Enable bit position. */ - -#define TWI_SLAVE_APIEN_bm 0x10 /* Address/Stop Interrupt Enable bit mask. */ -#define TWI_SLAVE_APIEN_bp 4 /* Address/Stop Interrupt Enable bit position. */ - -#define TWI_SLAVE_ENABLE_bm 0x08 /* Enable TWI Slave bit mask. */ -#define TWI_SLAVE_ENABLE_bp 3 /* Enable TWI Slave bit position. */ - -#define TWI_SLAVE_PIEN_bm 0x04 /* Stop Interrupt Enable bit mask. */ -#define TWI_SLAVE_PIEN_bp 2 /* Stop Interrupt Enable bit position. */ - -#define TWI_SLAVE_PMEN_bm 0x02 /* Promiscuous Mode Enable bit mask. */ -#define TWI_SLAVE_PMEN_bp 1 /* Promiscuous Mode Enable bit position. */ - -#define TWI_SLAVE_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ -#define TWI_SLAVE_SMEN_bp 0 /* Smart Mode Enable bit position. */ - -/* TWI_SLAVE.CTRLB bit masks and bit positions */ -#define TWI_SLAVE_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ -#define TWI_SLAVE_ACKACT_bp 2 /* Acknowledge Action bit position. */ - -#define TWI_SLAVE_CMD_gm 0x03 /* Command group mask. */ -#define TWI_SLAVE_CMD_gp 0 /* Command group position. */ -#define TWI_SLAVE_CMD0_bm (1<<0) /* Command bit 0 mask. */ -#define TWI_SLAVE_CMD0_bp 0 /* Command bit 0 position. */ -#define TWI_SLAVE_CMD1_bm (1<<1) /* Command bit 1 mask. */ -#define TWI_SLAVE_CMD1_bp 1 /* Command bit 1 position. */ - -/* TWI_SLAVE.STATUS bit masks and bit positions */ -#define TWI_SLAVE_DIF_bm 0x80 /* Data Interrupt Flag bit mask. */ -#define TWI_SLAVE_DIF_bp 7 /* Data Interrupt Flag bit position. */ - -#define TWI_SLAVE_APIF_bm 0x40 /* Address/Stop Interrupt Flag bit mask. */ -#define TWI_SLAVE_APIF_bp 6 /* Address/Stop Interrupt Flag bit position. */ - -#define TWI_SLAVE_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ -#define TWI_SLAVE_CLKHOLD_bp 5 /* Clock Hold bit position. */ - -#define TWI_SLAVE_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ -#define TWI_SLAVE_RXACK_bp 4 /* Received Acknowledge bit position. */ - -#define TWI_SLAVE_COLL_bm 0x08 /* Collision bit mask. */ -#define TWI_SLAVE_COLL_bp 3 /* Collision bit position. */ - -#define TWI_SLAVE_BUSERR_bm 0x04 /* Bus Error bit mask. */ -#define TWI_SLAVE_BUSERR_bp 2 /* Bus Error bit position. */ - -#define TWI_SLAVE_DIR_bm 0x02 /* Read/Write Direction bit mask. */ -#define TWI_SLAVE_DIR_bp 1 /* Read/Write Direction bit position. */ - -#define TWI_SLAVE_AP_bm 0x01 /* Slave Address or Stop bit mask. */ -#define TWI_SLAVE_AP_bp 0 /* Slave Address or Stop bit position. */ - -/* TWI_SLAVE.ADDRMASK bit masks and bit positions */ -#define TWI_SLAVE_ADDRMASK_gm 0xFE /* Address Mask group mask. */ -#define TWI_SLAVE_ADDRMASK_gp 1 /* Address Mask group position. */ -#define TWI_SLAVE_ADDRMASK0_bm (1<<1) /* Address Mask bit 0 mask. */ -#define TWI_SLAVE_ADDRMASK0_bp 1 /* Address Mask bit 0 position. */ -#define TWI_SLAVE_ADDRMASK1_bm (1<<2) /* Address Mask bit 1 mask. */ -#define TWI_SLAVE_ADDRMASK1_bp 2 /* Address Mask bit 1 position. */ -#define TWI_SLAVE_ADDRMASK2_bm (1<<3) /* Address Mask bit 2 mask. */ -#define TWI_SLAVE_ADDRMASK2_bp 3 /* Address Mask bit 2 position. */ -#define TWI_SLAVE_ADDRMASK3_bm (1<<4) /* Address Mask bit 3 mask. */ -#define TWI_SLAVE_ADDRMASK3_bp 4 /* Address Mask bit 3 position. */ -#define TWI_SLAVE_ADDRMASK4_bm (1<<5) /* Address Mask bit 4 mask. */ -#define TWI_SLAVE_ADDRMASK4_bp 5 /* Address Mask bit 4 position. */ -#define TWI_SLAVE_ADDRMASK5_bm (1<<6) /* Address Mask bit 5 mask. */ -#define TWI_SLAVE_ADDRMASK5_bp 6 /* Address Mask bit 5 position. */ -#define TWI_SLAVE_ADDRMASK6_bm (1<<7) /* Address Mask bit 6 mask. */ -#define TWI_SLAVE_ADDRMASK6_bp 7 /* Address Mask bit 6 position. */ - -#define TWI_SLAVE_ADDREN_bm 0x01 /* Address Enable bit mask. */ -#define TWI_SLAVE_ADDREN_bp 0 /* Address Enable bit position. */ - -/* TWI.CTRL bit masks and bit positions */ -#define TWI_SDAHOLD_gm 0x06 /* SDA Hold Time Enable group mask. */ -#define TWI_SDAHOLD_gp 1 /* SDA Hold Time Enable group position. */ -#define TWI_SDAHOLD0_bm (1<<1) /* SDA Hold Time Enable bit 0 mask. */ -#define TWI_SDAHOLD0_bp 1 /* SDA Hold Time Enable bit 0 position. */ -#define TWI_SDAHOLD1_bm (1<<2) /* SDA Hold Time Enable bit 1 mask. */ -#define TWI_SDAHOLD1_bp 2 /* SDA Hold Time Enable bit 1 position. */ - -#define TWI_EDIEN_bm 0x01 /* External Driver Interface Enable bit mask. */ -#define TWI_EDIEN_bp 0 /* External Driver Interface Enable bit position. */ - -/* USB - USB */ -/* USB_EP.STATUS bit masks and bit positions */ -#define USB_EP_STALLF_bm 0x80 /* Endpoint Stall Flag bit mask. */ -#define USB_EP_STALLF_bp 7 /* Endpoint Stall Flag bit position. */ - -#define USB_EP_CRC_bm 0x80 /* CRC Error Flag bit mask. */ -#define USB_EP_CRC_bp 7 /* CRC Error Flag bit position. */ - -#define USB_EP_UNF_bm 0x40 /* Underflow Enpoint FLag bit mask. */ -#define USB_EP_UNF_bp 6 /* Underflow Enpoint FLag bit position. */ - -#define USB_EP_OVF_bm 0x40 /* Overflow Enpoint Flag for Output Endpoints bit mask. */ -#define USB_EP_OVF_bp 6 /* Overflow Enpoint Flag for Output Endpoints bit position. */ - -#define USB_EP_TRNCOMPL0_bm 0x20 /* Transaction Complete 0 Flag bit mask. */ -#define USB_EP_TRNCOMPL0_bp 5 /* Transaction Complete 0 Flag bit position. */ - -#define USB_EP_TRNCOMPL1_bm 0x10 /* Transaction Complete 1 Flag bit mask. */ -#define USB_EP_TRNCOMPL1_bp 4 /* Transaction Complete 1 Flag bit position. */ - -#define USB_EP_SETUP_bm 0x10 /* SETUP Transaction Complete Flag bit mask. */ -#define USB_EP_SETUP_bp 4 /* SETUP Transaction Complete Flag bit position. */ - -#define USB_EP_BANK_bm 0x08 /* Bank Select bit mask. */ -#define USB_EP_BANK_bp 3 /* Bank Select bit position. */ - -#define USB_EP_BUSNACK1_bm 0x04 /* Data Buffer 1 Not Acknowledge bit mask. */ -#define USB_EP_BUSNACK1_bp 2 /* Data Buffer 1 Not Acknowledge bit position. */ - -#define USB_EP_BUSNACK0_bm 0x02 /* Data Buffer 0 Not Acknowledge bit mask. */ -#define USB_EP_BUSNACK0_bp 1 /* Data Buffer 0 Not Acknowledge bit position. */ - -#define USB_EP_TOGGLE_bm 0x01 /* Data Toggle bit mask. */ -#define USB_EP_TOGGLE_bp 0 /* Data Toggle bit position. */ - -/* USB_EP.CTRL bit masks and bit positions */ -#define USB_EP_TYPE_gm 0xC0 /* Endpoint Type group mask. */ -#define USB_EP_TYPE_gp 6 /* Endpoint Type group position. */ -#define USB_EP_TYPE0_bm (1<<6) /* Endpoint Type bit 0 mask. */ -#define USB_EP_TYPE0_bp 6 /* Endpoint Type bit 0 position. */ -#define USB_EP_TYPE1_bm (1<<7) /* Endpoint Type bit 1 mask. */ -#define USB_EP_TYPE1_bp 7 /* Endpoint Type bit 1 position. */ - -#define USB_EP_MULTIPKT_bm 0x20 /* Multi Packet Transfer Enable bit mask. */ -#define USB_EP_MULTIPKT_bp 5 /* Multi Packet Transfer Enable bit position. */ - -#define USB_EP_PINGPONG_bm 0x10 /* Ping-Pong Enable bit mask. */ -#define USB_EP_PINGPONG_bp 4 /* Ping-Pong Enable bit position. */ - -#define USB_EP_INTDSBL_bm 0x08 /* Interrupt Disable bit mask. */ -#define USB_EP_INTDSBL_bp 3 /* Interrupt Disable bit position. */ - -#define USB_EP_STALL_bm 0x04 /* Data Stall bit mask. */ -#define USB_EP_STALL_bp 2 /* Data Stall bit position. */ - -#define USB_EP_BUFSIZE_gm 0x07 /* Data Buffer Size group mask. */ -#define USB_EP_BUFSIZE_gp 0 /* Data Buffer Size group position. */ -#define USB_EP_BUFSIZE0_bm (1<<0) /* Data Buffer Size bit 0 mask. */ -#define USB_EP_BUFSIZE0_bp 0 /* Data Buffer Size bit 0 position. */ -#define USB_EP_BUFSIZE1_bm (1<<1) /* Data Buffer Size bit 1 mask. */ -#define USB_EP_BUFSIZE1_bp 1 /* Data Buffer Size bit 1 position. */ -#define USB_EP_BUFSIZE2_bm (1<<2) /* Data Buffer Size bit 2 mask. */ -#define USB_EP_BUFSIZE2_bp 2 /* Data Buffer Size bit 2 position. */ - -/* USB_EP.CNT bit masks and bit positions */ -#define USB_EP_ZLP_bm 0x8000 /* Zero Length Packet bit mask. */ -#define USB_EP_ZLP_bp 15 /* Zero Length Packet bit position. */ - -/* USB.CTRLA bit masks and bit positions */ -#define USB_ENABLE_bm 0x80 /* USB Enable bit mask. */ -#define USB_ENABLE_bp 7 /* USB Enable bit position. */ - -#define USB_SPEED_bm 0x40 /* Speed Select bit mask. */ -#define USB_SPEED_bp 6 /* Speed Select bit position. */ - -#define USB_FIFOEN_bm 0x20 /* USB FIFO Enable bit mask. */ -#define USB_FIFOEN_bp 5 /* USB FIFO Enable bit position. */ - -#define USB_STFRNUM_bm 0x10 /* Store Frame Number Enable bit mask. */ -#define USB_STFRNUM_bp 4 /* Store Frame Number Enable bit position. */ - -#define USB_MAXEP_gm 0x0F /* Maximum Endpoint Addresses group mask. */ -#define USB_MAXEP_gp 0 /* Maximum Endpoint Addresses group position. */ -#define USB_MAXEP0_bm (1<<0) /* Maximum Endpoint Addresses bit 0 mask. */ -#define USB_MAXEP0_bp 0 /* Maximum Endpoint Addresses bit 0 position. */ -#define USB_MAXEP1_bm (1<<1) /* Maximum Endpoint Addresses bit 1 mask. */ -#define USB_MAXEP1_bp 1 /* Maximum Endpoint Addresses bit 1 position. */ -#define USB_MAXEP2_bm (1<<2) /* Maximum Endpoint Addresses bit 2 mask. */ -#define USB_MAXEP2_bp 2 /* Maximum Endpoint Addresses bit 2 position. */ -#define USB_MAXEP3_bm (1<<3) /* Maximum Endpoint Addresses bit 3 mask. */ -#define USB_MAXEP3_bp 3 /* Maximum Endpoint Addresses bit 3 position. */ - -/* USB.CTRLB bit masks and bit positions */ -#define USB_PULLRST_bm 0x10 /* Pull during Reset bit mask. */ -#define USB_PULLRST_bp 4 /* Pull during Reset bit position. */ - -#define USB_RWAKEUP_bm 0x04 /* Remote Wake-up bit mask. */ -#define USB_RWAKEUP_bp 2 /* Remote Wake-up bit position. */ - -#define USB_GNACK_bm 0x02 /* Global NACK bit mask. */ -#define USB_GNACK_bp 1 /* Global NACK bit position. */ - -#define USB_ATTACH_bm 0x01 /* Attach bit mask. */ -#define USB_ATTACH_bp 0 /* Attach bit position. */ - -/* USB.STATUS bit masks and bit positions */ -#define USB_URESUME_bm 0x08 /* Upstream Resume bit mask. */ -#define USB_URESUME_bp 3 /* Upstream Resume bit position. */ - -#define USB_RESUME_bm 0x04 /* Resume bit mask. */ -#define USB_RESUME_bp 2 /* Resume bit position. */ - -#define USB_SUSPEND_bm 0x02 /* Bus Suspended bit mask. */ -#define USB_SUSPEND_bp 1 /* Bus Suspended bit position. */ - -#define USB_BUSRST_bm 0x01 /* Bus Reset bit mask. */ -#define USB_BUSRST_bp 0 /* Bus Reset bit position. */ - -/* USB.ADDR bit masks and bit positions */ -#define USB_ADDR_gm 0x7F /* Device Address group mask. */ -#define USB_ADDR_gp 0 /* Device Address group position. */ -#define USB_ADDR0_bm (1<<0) /* Device Address bit 0 mask. */ -#define USB_ADDR0_bp 0 /* Device Address bit 0 position. */ -#define USB_ADDR1_bm (1<<1) /* Device Address bit 1 mask. */ -#define USB_ADDR1_bp 1 /* Device Address bit 1 position. */ -#define USB_ADDR2_bm (1<<2) /* Device Address bit 2 mask. */ -#define USB_ADDR2_bp 2 /* Device Address bit 2 position. */ -#define USB_ADDR3_bm (1<<3) /* Device Address bit 3 mask. */ -#define USB_ADDR3_bp 3 /* Device Address bit 3 position. */ -#define USB_ADDR4_bm (1<<4) /* Device Address bit 4 mask. */ -#define USB_ADDR4_bp 4 /* Device Address bit 4 position. */ -#define USB_ADDR5_bm (1<<5) /* Device Address bit 5 mask. */ -#define USB_ADDR5_bp 5 /* Device Address bit 5 position. */ -#define USB_ADDR6_bm (1<<6) /* Device Address bit 6 mask. */ -#define USB_ADDR6_bp 6 /* Device Address bit 6 position. */ - -/* USB.FIFOWP bit masks and bit positions */ -#define USB_FIFOWP_gm 0x1F /* FIFO Write Pointer group mask. */ -#define USB_FIFOWP_gp 0 /* FIFO Write Pointer group position. */ -#define USB_FIFOWP0_bm (1<<0) /* FIFO Write Pointer bit 0 mask. */ -#define USB_FIFOWP0_bp 0 /* FIFO Write Pointer bit 0 position. */ -#define USB_FIFOWP1_bm (1<<1) /* FIFO Write Pointer bit 1 mask. */ -#define USB_FIFOWP1_bp 1 /* FIFO Write Pointer bit 1 position. */ -#define USB_FIFOWP2_bm (1<<2) /* FIFO Write Pointer bit 2 mask. */ -#define USB_FIFOWP2_bp 2 /* FIFO Write Pointer bit 2 position. */ -#define USB_FIFOWP3_bm (1<<3) /* FIFO Write Pointer bit 3 mask. */ -#define USB_FIFOWP3_bp 3 /* FIFO Write Pointer bit 3 position. */ -#define USB_FIFOWP4_bm (1<<4) /* FIFO Write Pointer bit 4 mask. */ -#define USB_FIFOWP4_bp 4 /* FIFO Write Pointer bit 4 position. */ - -/* USB.FIFORP bit masks and bit positions */ -#define USB_FIFORP_gm 0x1F /* FIFO Read Pointer group mask. */ -#define USB_FIFORP_gp 0 /* FIFO Read Pointer group position. */ -#define USB_FIFORP0_bm (1<<0) /* FIFO Read Pointer bit 0 mask. */ -#define USB_FIFORP0_bp 0 /* FIFO Read Pointer bit 0 position. */ -#define USB_FIFORP1_bm (1<<1) /* FIFO Read Pointer bit 1 mask. */ -#define USB_FIFORP1_bp 1 /* FIFO Read Pointer bit 1 position. */ -#define USB_FIFORP2_bm (1<<2) /* FIFO Read Pointer bit 2 mask. */ -#define USB_FIFORP2_bp 2 /* FIFO Read Pointer bit 2 position. */ -#define USB_FIFORP3_bm (1<<3) /* FIFO Read Pointer bit 3 mask. */ -#define USB_FIFORP3_bp 3 /* FIFO Read Pointer bit 3 position. */ -#define USB_FIFORP4_bm (1<<4) /* FIFO Read Pointer bit 4 mask. */ -#define USB_FIFORP4_bp 4 /* FIFO Read Pointer bit 4 position. */ - -/* USB.INTCTRLA bit masks and bit positions */ -#define USB_SOFIE_bm 0x80 /* Start Of Frame Interrupt Enable bit mask. */ -#define USB_SOFIE_bp 7 /* Start Of Frame Interrupt Enable bit position. */ - -#define USB_BUSEVIE_bm 0x40 /* Bus Event Interrupt Enable bit mask. */ -#define USB_BUSEVIE_bp 6 /* Bus Event Interrupt Enable bit position. */ - -#define USB_BUSERRIE_bm 0x20 /* Bus Error Interrupt Enable bit mask. */ -#define USB_BUSERRIE_bp 5 /* Bus Error Interrupt Enable bit position. */ - -#define USB_STALLIE_bm 0x10 /* STALL Interrupt Enable bit mask. */ -#define USB_STALLIE_bp 4 /* STALL Interrupt Enable bit position. */ - -#define USB_INTLVL_gm 0x03 /* Interrupt Level group mask. */ -#define USB_INTLVL_gp 0 /* Interrupt Level group position. */ -#define USB_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */ -#define USB_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */ -#define USB_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ -#define USB_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */ - -/* USB.INTCTRLB bit masks and bit positions */ -#define USB_TRNIE_bm 0x02 /* Transaction Complete Interrupt Enable bit mask. */ -#define USB_TRNIE_bp 1 /* Transaction Complete Interrupt Enable bit position. */ - -#define USB_SETUPIE_bm 0x01 /* SETUP Transaction Complete Interrupt Enable bit mask. */ -#define USB_SETUPIE_bp 0 /* SETUP Transaction Complete Interrupt Enable bit position. */ - -/* USB.INTFLAGSACLR bit masks and bit positions */ -#define USB_SOFIF_bm 0x80 /* Start Of Frame Interrupt Flag bit mask. */ -#define USB_SOFIF_bp 7 /* Start Of Frame Interrupt Flag bit position. */ - -#define USB_SUSPENDIF_bm 0x40 /* Suspend Interrupt Flag bit mask. */ -#define USB_SUSPENDIF_bp 6 /* Suspend Interrupt Flag bit position. */ - -#define USB_RESUMEIF_bm 0x20 /* Resume Interrupt Flag bit mask. */ -#define USB_RESUMEIF_bp 5 /* Resume Interrupt Flag bit position. */ - -#define USB_RSTIF_bm 0x10 /* Reset Interrupt Flag bit mask. */ -#define USB_RSTIF_bp 4 /* Reset Interrupt Flag bit position. */ - -#define USB_CRCIF_bm 0x08 /* Isochronous CRC Error Interrupt Flag bit mask. */ -#define USB_CRCIF_bp 3 /* Isochronous CRC Error Interrupt Flag bit position. */ - -#define USB_UNFIF_bm 0x04 /* Underflow Interrupt Flag bit mask. */ -#define USB_UNFIF_bp 2 /* Underflow Interrupt Flag bit position. */ - -#define USB_OVFIF_bm 0x02 /* Overflow Interrupt Flag bit mask. */ -#define USB_OVFIF_bp 1 /* Overflow Interrupt Flag bit position. */ - -#define USB_STALLIF_bm 0x01 /* STALL Interrupt Flag bit mask. */ -#define USB_STALLIF_bp 0 /* STALL Interrupt Flag bit position. */ - -/* USB.INTFLAGSASET bit masks and bit positions */ -/* USB_SOFIF Predefined. */ -/* USB_SOFIF Predefined. */ - -/* USB_SUSPENDIF Predefined. */ -/* USB_SUSPENDIF Predefined. */ - -/* USB_RESUMEIF Predefined. */ -/* USB_RESUMEIF Predefined. */ - -/* USB_RSTIF Predefined. */ -/* USB_RSTIF Predefined. */ - -/* USB_CRCIF Predefined. */ -/* USB_CRCIF Predefined. */ - -/* USB_UNFIF Predefined. */ -/* USB_UNFIF Predefined. */ - -/* USB_OVFIF Predefined. */ -/* USB_OVFIF Predefined. */ - -/* USB_STALLIF Predefined. */ -/* USB_STALLIF Predefined. */ - -/* USB.INTFLAGSBCLR bit masks and bit positions */ -#define USB_TRNIF_bm 0x02 /* Transaction Complete Interrupt Flag bit mask. */ -#define USB_TRNIF_bp 1 /* Transaction Complete Interrupt Flag bit position. */ - -#define USB_SETUPIF_bm 0x01 /* SETUP Transaction Complete Interrupt Flag bit mask. */ -#define USB_SETUPIF_bp 0 /* SETUP Transaction Complete Interrupt Flag bit position. */ - -/* USB.INTFLAGSBSET bit masks and bit positions */ -/* USB_TRNIF Predefined. */ -/* USB_TRNIF Predefined. */ - -/* USB_SETUPIF Predefined. */ -/* USB_SETUPIF Predefined. */ - -/* PORT - I/O Port Configuration */ -/* PORT.INTCTRL bit masks and bit positions */ -#define PORT_INT1LVL_gm 0x0C /* Port Interrupt 1 Level group mask. */ -#define PORT_INT1LVL_gp 2 /* Port Interrupt 1 Level group position. */ -#define PORT_INT1LVL0_bm (1<<2) /* Port Interrupt 1 Level bit 0 mask. */ -#define PORT_INT1LVL0_bp 2 /* Port Interrupt 1 Level bit 0 position. */ -#define PORT_INT1LVL1_bm (1<<3) /* Port Interrupt 1 Level bit 1 mask. */ -#define PORT_INT1LVL1_bp 3 /* Port Interrupt 1 Level bit 1 position. */ - -#define PORT_INT0LVL_gm 0x03 /* Port Interrupt 0 Level group mask. */ -#define PORT_INT0LVL_gp 0 /* Port Interrupt 0 Level group position. */ -#define PORT_INT0LVL0_bm (1<<0) /* Port Interrupt 0 Level bit 0 mask. */ -#define PORT_INT0LVL0_bp 0 /* Port Interrupt 0 Level bit 0 position. */ -#define PORT_INT0LVL1_bm (1<<1) /* Port Interrupt 0 Level bit 1 mask. */ -#define PORT_INT0LVL1_bp 1 /* Port Interrupt 0 Level bit 1 position. */ - -/* PORT.INTFLAGS bit masks and bit positions */ -#define PORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ -#define PORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ - -#define PORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ -#define PORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ - -/* PORT.REMAP bit masks and bit positions */ -#define PORT_SPI_bm 0x20 /* SPI bit mask. */ -#define PORT_SPI_bp 5 /* SPI bit position. */ - -#define PORT_USART0_bm 0x10 /* USART0 bit mask. */ -#define PORT_USART0_bp 4 /* USART0 bit position. */ - -#define PORT_TC0D_bm 0x08 /* Timer/Counter 0 Output Compare D bit mask. */ -#define PORT_TC0D_bp 3 /* Timer/Counter 0 Output Compare D bit position. */ - -#define PORT_TC0C_bm 0x04 /* Timer/Counter 0 Output Compare C bit mask. */ -#define PORT_TC0C_bp 2 /* Timer/Counter 0 Output Compare C bit position. */ - -#define PORT_TC0B_bm 0x02 /* Timer/Counter 0 Output Compare B bit mask. */ -#define PORT_TC0B_bp 1 /* Timer/Counter 0 Output Compare B bit position. */ - -#define PORT_TC0A_bm 0x01 /* Timer/Counter 0 Output Compare A bit mask. */ -#define PORT_TC0A_bp 0 /* Timer/Counter 0 Output Compare A bit position. */ - -/* PORT.PIN0CTRL bit masks and bit positions */ -#define PORT_SRLEN_bm 0x80 /* Slew Rate Enable bit mask. */ -#define PORT_SRLEN_bp 7 /* Slew Rate Enable bit position. */ - -#define PORT_INVEN_bm 0x40 /* Inverted I/O Enable bit mask. */ -#define PORT_INVEN_bp 6 /* Inverted I/O Enable bit position. */ - -#define PORT_OPC_gm 0x38 /* Output/Pull Configuration group mask. */ -#define PORT_OPC_gp 3 /* Output/Pull Configuration group position. */ -#define PORT_OPC0_bm (1<<3) /* Output/Pull Configuration bit 0 mask. */ -#define PORT_OPC0_bp 3 /* Output/Pull Configuration bit 0 position. */ -#define PORT_OPC1_bm (1<<4) /* Output/Pull Configuration bit 1 mask. */ -#define PORT_OPC1_bp 4 /* Output/Pull Configuration bit 1 position. */ -#define PORT_OPC2_bm (1<<5) /* Output/Pull Configuration bit 2 mask. */ -#define PORT_OPC2_bp 5 /* Output/Pull Configuration bit 2 position. */ - -#define PORT_ISC_gm 0x07 /* Input/Sense Configuration group mask. */ -#define PORT_ISC_gp 0 /* Input/Sense Configuration group position. */ -#define PORT_ISC0_bm (1<<0) /* Input/Sense Configuration bit 0 mask. */ -#define PORT_ISC0_bp 0 /* Input/Sense Configuration bit 0 position. */ -#define PORT_ISC1_bm (1<<1) /* Input/Sense Configuration bit 1 mask. */ -#define PORT_ISC1_bp 1 /* Input/Sense Configuration bit 1 position. */ -#define PORT_ISC2_bm (1<<2) /* Input/Sense Configuration bit 2 mask. */ -#define PORT_ISC2_bp 2 /* Input/Sense Configuration bit 2 position. */ - -/* PORT.PIN1CTRL bit masks and bit positions */ -/* PORT_SRLEN Predefined. */ -/* PORT_SRLEN Predefined. */ - -/* PORT_INVEN Predefined. */ -/* PORT_INVEN Predefined. */ - -/* PORT_OPC Predefined. */ -/* PORT_OPC Predefined. */ - -/* PORT_ISC Predefined. */ -/* PORT_ISC Predefined. */ - -/* PORT.PIN2CTRL bit masks and bit positions */ -/* PORT_SRLEN Predefined. */ -/* PORT_SRLEN Predefined. */ - -/* PORT_INVEN Predefined. */ -/* PORT_INVEN Predefined. */ - -/* PORT_OPC Predefined. */ -/* PORT_OPC Predefined. */ - -/* PORT_ISC Predefined. */ -/* PORT_ISC Predefined. */ - -/* PORT.PIN3CTRL bit masks and bit positions */ -/* PORT_SRLEN Predefined. */ -/* PORT_SRLEN Predefined. */ - -/* PORT_INVEN Predefined. */ -/* PORT_INVEN Predefined. */ - -/* PORT_OPC Predefined. */ -/* PORT_OPC Predefined. */ - -/* PORT_ISC Predefined. */ -/* PORT_ISC Predefined. */ - -/* PORT.PIN4CTRL bit masks and bit positions */ -/* PORT_SRLEN Predefined. */ -/* PORT_SRLEN Predefined. */ - -/* PORT_INVEN Predefined. */ -/* PORT_INVEN Predefined. */ - -/* PORT_OPC Predefined. */ -/* PORT_OPC Predefined. */ - -/* PORT_ISC Predefined. */ -/* PORT_ISC Predefined. */ - -/* PORT.PIN5CTRL bit masks and bit positions */ -/* PORT_SRLEN Predefined. */ -/* PORT_SRLEN Predefined. */ - -/* PORT_INVEN Predefined. */ -/* PORT_INVEN Predefined. */ - -/* PORT_OPC Predefined. */ -/* PORT_OPC Predefined. */ - -/* PORT_ISC Predefined. */ -/* PORT_ISC Predefined. */ - -/* PORT.PIN6CTRL bit masks and bit positions */ -/* PORT_SRLEN Predefined. */ -/* PORT_SRLEN Predefined. */ - -/* PORT_INVEN Predefined. */ -/* PORT_INVEN Predefined. */ - -/* PORT_OPC Predefined. */ -/* PORT_OPC Predefined. */ - -/* PORT_ISC Predefined. */ -/* PORT_ISC Predefined. */ - -/* PORT.PIN7CTRL bit masks and bit positions */ -/* PORT_SRLEN Predefined. */ -/* PORT_SRLEN Predefined. */ - -/* PORT_INVEN Predefined. */ -/* PORT_INVEN Predefined. */ - -/* PORT_OPC Predefined. */ -/* PORT_OPC Predefined. */ - -/* PORT_ISC Predefined. */ -/* PORT_ISC Predefined. */ - -/* TC - 16-bit Timer/Counter With PWM */ -/* TC0.CTRLA bit masks and bit positions */ -#define TC0_CLKSEL_gm 0x0F /* Clock Selection group mask. */ -#define TC0_CLKSEL_gp 0 /* Clock Selection group position. */ -#define TC0_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ -#define TC0_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ -#define TC0_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ -#define TC0_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ -#define TC0_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ -#define TC0_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ -#define TC0_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ -#define TC0_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ - -/* TC0.CTRLB bit masks and bit positions */ -#define TC0_CCDEN_bm 0x80 /* Compare or Capture D Enable bit mask. */ -#define TC0_CCDEN_bp 7 /* Compare or Capture D Enable bit position. */ - -#define TC0_CCCEN_bm 0x40 /* Compare or Capture C Enable bit mask. */ -#define TC0_CCCEN_bp 6 /* Compare or Capture C Enable bit position. */ - -#define TC0_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ -#define TC0_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ - -#define TC0_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ -#define TC0_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ - -#define TC0_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ -#define TC0_WGMODE_gp 0 /* Waveform generation mode group position. */ -#define TC0_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ -#define TC0_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ -#define TC0_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ -#define TC0_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ -#define TC0_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ -#define TC0_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ - -/* TC0.CTRLC bit masks and bit positions */ -#define TC0_CMPD_bm 0x08 /* Compare D Output Value bit mask. */ -#define TC0_CMPD_bp 3 /* Compare D Output Value bit position. */ - -#define TC0_CMPC_bm 0x04 /* Compare C Output Value bit mask. */ -#define TC0_CMPC_bp 2 /* Compare C Output Value bit position. */ - -#define TC0_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ -#define TC0_CMPB_bp 1 /* Compare B Output Value bit position. */ - -#define TC0_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ -#define TC0_CMPA_bp 0 /* Compare A Output Value bit position. */ - -/* TC0.CTRLD bit masks and bit positions */ -#define TC0_EVACT_gm 0xE0 /* Event Action group mask. */ -#define TC0_EVACT_gp 5 /* Event Action group position. */ -#define TC0_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ -#define TC0_EVACT0_bp 5 /* Event Action bit 0 position. */ -#define TC0_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ -#define TC0_EVACT1_bp 6 /* Event Action bit 1 position. */ -#define TC0_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ -#define TC0_EVACT2_bp 7 /* Event Action bit 2 position. */ - -#define TC0_EVDLY_bm 0x10 /* Event Delay bit mask. */ -#define TC0_EVDLY_bp 4 /* Event Delay bit position. */ - -#define TC0_EVSEL_gm 0x0F /* Event Source Select group mask. */ -#define TC0_EVSEL_gp 0 /* Event Source Select group position. */ -#define TC0_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ -#define TC0_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ -#define TC0_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ -#define TC0_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ -#define TC0_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ -#define TC0_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ -#define TC0_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ -#define TC0_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ - -/* TC0.CTRLE bit masks and bit positions */ -#define TC0_BYTEM_gm 0x03 /* Byte Mode group mask. */ -#define TC0_BYTEM_gp 0 /* Byte Mode group position. */ -#define TC0_BYTEM0_bm (1<<0) /* Byte Mode bit 0 mask. */ -#define TC0_BYTEM0_bp 0 /* Byte Mode bit 0 position. */ -#define TC0_BYTEM1_bm (1<<1) /* Byte Mode bit 1 mask. */ -#define TC0_BYTEM1_bp 1 /* Byte Mode bit 1 position. */ - -/* TC0.INTCTRLA bit masks and bit positions */ -#define TC0_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ -#define TC0_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ -#define TC0_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ -#define TC0_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ -#define TC0_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ -#define TC0_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ - -#define TC0_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ -#define TC0_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ -#define TC0_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ -#define TC0_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ -#define TC0_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ -#define TC0_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ - -/* TC0.INTCTRLB bit masks and bit positions */ -#define TC0_CCDINTLVL_gm 0xC0 /* Compare or Capture D Interrupt Level group mask. */ -#define TC0_CCDINTLVL_gp 6 /* Compare or Capture D Interrupt Level group position. */ -#define TC0_CCDINTLVL0_bm (1<<6) /* Compare or Capture D Interrupt Level bit 0 mask. */ -#define TC0_CCDINTLVL0_bp 6 /* Compare or Capture D Interrupt Level bit 0 position. */ -#define TC0_CCDINTLVL1_bm (1<<7) /* Compare or Capture D Interrupt Level bit 1 mask. */ -#define TC0_CCDINTLVL1_bp 7 /* Compare or Capture D Interrupt Level bit 1 position. */ - -#define TC0_CCCINTLVL_gm 0x30 /* Compare or Capture C Interrupt Level group mask. */ -#define TC0_CCCINTLVL_gp 4 /* Compare or Capture C Interrupt Level group position. */ -#define TC0_CCCINTLVL0_bm (1<<4) /* Compare or Capture C Interrupt Level bit 0 mask. */ -#define TC0_CCCINTLVL0_bp 4 /* Compare or Capture C Interrupt Level bit 0 position. */ -#define TC0_CCCINTLVL1_bm (1<<5) /* Compare or Capture C Interrupt Level bit 1 mask. */ -#define TC0_CCCINTLVL1_bp 5 /* Compare or Capture C Interrupt Level bit 1 position. */ - -#define TC0_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ -#define TC0_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ -#define TC0_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ -#define TC0_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ -#define TC0_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ -#define TC0_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ - -#define TC0_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ -#define TC0_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ -#define TC0_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ -#define TC0_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ -#define TC0_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ -#define TC0_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ - -/* TC0.CTRLFCLR bit masks and bit positions */ -#define TC0_CMD_gm 0x0C /* Command group mask. */ -#define TC0_CMD_gp 2 /* Command group position. */ -#define TC0_CMD0_bm (1<<2) /* Command bit 0 mask. */ -#define TC0_CMD0_bp 2 /* Command bit 0 position. */ -#define TC0_CMD1_bm (1<<3) /* Command bit 1 mask. */ -#define TC0_CMD1_bp 3 /* Command bit 1 position. */ - -#define TC0_LUPD_bm 0x02 /* Lock Update bit mask. */ -#define TC0_LUPD_bp 1 /* Lock Update bit position. */ - -#define TC0_DIR_bm 0x01 /* Direction bit mask. */ -#define TC0_DIR_bp 0 /* Direction bit position. */ - -/* TC0.CTRLFSET bit masks and bit positions */ -/* TC0_CMD Predefined. */ -/* TC0_CMD Predefined. */ - -/* TC0_LUPD Predefined. */ -/* TC0_LUPD Predefined. */ - -/* TC0_DIR Predefined. */ -/* TC0_DIR Predefined. */ - -/* TC0.CTRLGCLR bit masks and bit positions */ -#define TC0_CCDBV_bm 0x10 /* Compare or Capture D Buffer Valid bit mask. */ -#define TC0_CCDBV_bp 4 /* Compare or Capture D Buffer Valid bit position. */ - -#define TC0_CCCBV_bm 0x08 /* Compare or Capture C Buffer Valid bit mask. */ -#define TC0_CCCBV_bp 3 /* Compare or Capture C Buffer Valid bit position. */ - -#define TC0_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ -#define TC0_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ - -#define TC0_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ -#define TC0_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ - -#define TC0_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ -#define TC0_PERBV_bp 0 /* Period Buffer Valid bit position. */ - -/* TC0.CTRLGSET bit masks and bit positions */ -/* TC0_CCDBV Predefined. */ -/* TC0_CCDBV Predefined. */ - -/* TC0_CCCBV Predefined. */ -/* TC0_CCCBV Predefined. */ - -/* TC0_CCBBV Predefined. */ -/* TC0_CCBBV Predefined. */ - -/* TC0_CCABV Predefined. */ -/* TC0_CCABV Predefined. */ - -/* TC0_PERBV Predefined. */ -/* TC0_PERBV Predefined. */ - -/* TC0.INTFLAGS bit masks and bit positions */ -#define TC0_CCDIF_bm 0x80 /* Compare or Capture D Interrupt Flag bit mask. */ -#define TC0_CCDIF_bp 7 /* Compare or Capture D Interrupt Flag bit position. */ - -#define TC0_CCCIF_bm 0x40 /* Compare or Capture C Interrupt Flag bit mask. */ -#define TC0_CCCIF_bp 6 /* Compare or Capture C Interrupt Flag bit position. */ - -#define TC0_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ -#define TC0_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ - -#define TC0_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ -#define TC0_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ - -#define TC0_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ -#define TC0_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ - -#define TC0_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ -#define TC0_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ - -/* TC1.CTRLA bit masks and bit positions */ -#define TC1_CLKSEL_gm 0x0F /* Clock Selection group mask. */ -#define TC1_CLKSEL_gp 0 /* Clock Selection group position. */ -#define TC1_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ -#define TC1_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ -#define TC1_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ -#define TC1_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ -#define TC1_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ -#define TC1_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ -#define TC1_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ -#define TC1_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ - -/* TC1.CTRLB bit masks and bit positions */ -#define TC1_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ -#define TC1_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ - -#define TC1_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ -#define TC1_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ - -#define TC1_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ -#define TC1_WGMODE_gp 0 /* Waveform generation mode group position. */ -#define TC1_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ -#define TC1_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ -#define TC1_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ -#define TC1_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ -#define TC1_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ -#define TC1_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ - -/* TC1.CTRLC bit masks and bit positions */ -#define TC1_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ -#define TC1_CMPB_bp 1 /* Compare B Output Value bit position. */ - -#define TC1_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ -#define TC1_CMPA_bp 0 /* Compare A Output Value bit position. */ - -/* TC1.CTRLD bit masks and bit positions */ -#define TC1_EVACT_gm 0xE0 /* Event Action group mask. */ -#define TC1_EVACT_gp 5 /* Event Action group position. */ -#define TC1_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ -#define TC1_EVACT0_bp 5 /* Event Action bit 0 position. */ -#define TC1_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ -#define TC1_EVACT1_bp 6 /* Event Action bit 1 position. */ -#define TC1_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ -#define TC1_EVACT2_bp 7 /* Event Action bit 2 position. */ - -#define TC1_EVDLY_bm 0x10 /* Event Delay bit mask. */ -#define TC1_EVDLY_bp 4 /* Event Delay bit position. */ - -#define TC1_EVSEL_gm 0x0F /* Event Source Select group mask. */ -#define TC1_EVSEL_gp 0 /* Event Source Select group position. */ -#define TC1_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ -#define TC1_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ -#define TC1_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ -#define TC1_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ -#define TC1_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ -#define TC1_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ -#define TC1_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ -#define TC1_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ - -/* TC1.CTRLE bit masks and bit positions */ -#define TC1_BYTEM_bm 0x01 /* Byte Mode bit mask. */ -#define TC1_BYTEM_bp 0 /* Byte Mode bit position. */ - -/* TC1.INTCTRLA bit masks and bit positions */ -#define TC1_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ -#define TC1_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ -#define TC1_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ -#define TC1_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ -#define TC1_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ -#define TC1_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ - -#define TC1_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ -#define TC1_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ -#define TC1_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ -#define TC1_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ -#define TC1_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ -#define TC1_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ - -/* TC1.INTCTRLB bit masks and bit positions */ -#define TC1_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ -#define TC1_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ -#define TC1_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ -#define TC1_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ -#define TC1_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ -#define TC1_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ - -#define TC1_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ -#define TC1_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ -#define TC1_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ -#define TC1_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ -#define TC1_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ -#define TC1_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ - -/* TC1.CTRLFCLR bit masks and bit positions */ -#define TC1_CMD_gm 0x0C /* Command group mask. */ -#define TC1_CMD_gp 2 /* Command group position. */ -#define TC1_CMD0_bm (1<<2) /* Command bit 0 mask. */ -#define TC1_CMD0_bp 2 /* Command bit 0 position. */ -#define TC1_CMD1_bm (1<<3) /* Command bit 1 mask. */ -#define TC1_CMD1_bp 3 /* Command bit 1 position. */ - -#define TC1_LUPD_bm 0x02 /* Lock Update bit mask. */ -#define TC1_LUPD_bp 1 /* Lock Update bit position. */ - -#define TC1_DIR_bm 0x01 /* Direction bit mask. */ -#define TC1_DIR_bp 0 /* Direction bit position. */ - -/* TC1.CTRLFSET bit masks and bit positions */ -/* TC1_CMD Predefined. */ -/* TC1_CMD Predefined. */ - -/* TC1_LUPD Predefined. */ -/* TC1_LUPD Predefined. */ - -/* TC1_DIR Predefined. */ -/* TC1_DIR Predefined. */ - -/* TC1.CTRLGCLR bit masks and bit positions */ -#define TC1_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ -#define TC1_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ - -#define TC1_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ -#define TC1_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ - -#define TC1_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ -#define TC1_PERBV_bp 0 /* Period Buffer Valid bit position. */ - -/* TC1.CTRLGSET bit masks and bit positions */ -/* TC1_CCBBV Predefined. */ -/* TC1_CCBBV Predefined. */ - -/* TC1_CCABV Predefined. */ -/* TC1_CCABV Predefined. */ - -/* TC1_PERBV Predefined. */ -/* TC1_PERBV Predefined. */ - -/* TC1.INTFLAGS bit masks and bit positions */ -#define TC1_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ -#define TC1_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ - -#define TC1_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ -#define TC1_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ - -#define TC1_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ -#define TC1_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ - -#define TC1_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ -#define TC1_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ - -/* TC2 - 16-bit Timer/Counter type 2 */ -/* TC2.CTRLA bit masks and bit positions */ -#define TC2_CLKSEL_gm 0x0F /* Clock Selection group mask. */ -#define TC2_CLKSEL_gp 0 /* Clock Selection group position. */ -#define TC2_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ -#define TC2_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ -#define TC2_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ -#define TC2_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ -#define TC2_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ -#define TC2_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ -#define TC2_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ -#define TC2_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ - -/* TC2.CTRLB bit masks and bit positions */ -#define TC2_HCMPDEN_bm 0x80 /* High Byte Compare D Enable bit mask. */ -#define TC2_HCMPDEN_bp 7 /* High Byte Compare D Enable bit position. */ - -#define TC2_HCMPCEN_bm 0x40 /* High Byte Compare C Enable bit mask. */ -#define TC2_HCMPCEN_bp 6 /* High Byte Compare C Enable bit position. */ - -#define TC2_HCMPBEN_bm 0x20 /* High Byte Compare B Enable bit mask. */ -#define TC2_HCMPBEN_bp 5 /* High Byte Compare B Enable bit position. */ - -#define TC2_HCMPAEN_bm 0x10 /* High Byte Compare A Enable bit mask. */ -#define TC2_HCMPAEN_bp 4 /* High Byte Compare A Enable bit position. */ - -#define TC2_LCMPDEN_bm 0x08 /* Low Byte Compare D Enable bit mask. */ -#define TC2_LCMPDEN_bp 3 /* Low Byte Compare D Enable bit position. */ - -#define TC2_LCMPCEN_bm 0x04 /* Low Byte Compare C Enable bit mask. */ -#define TC2_LCMPCEN_bp 2 /* Low Byte Compare C Enable bit position. */ - -#define TC2_LCMPBEN_bm 0x02 /* Low Byte Compare B Enable bit mask. */ -#define TC2_LCMPBEN_bp 1 /* Low Byte Compare B Enable bit position. */ - -#define TC2_LCMPAEN_bm 0x01 /* Low Byte Compare A Enable bit mask. */ -#define TC2_LCMPAEN_bp 0 /* Low Byte Compare A Enable bit position. */ - -/* TC2.CTRLC bit masks and bit positions */ -#define TC2_HCMPD_bm 0x80 /* High Byte Compare D Output Value bit mask. */ -#define TC2_HCMPD_bp 7 /* High Byte Compare D Output Value bit position. */ - -#define TC2_HCMPC_bm 0x40 /* High Byte Compare C Output Value bit mask. */ -#define TC2_HCMPC_bp 6 /* High Byte Compare C Output Value bit position. */ - -#define TC2_HCMPB_bm 0x20 /* High Byte Compare B Output Value bit mask. */ -#define TC2_HCMPB_bp 5 /* High Byte Compare B Output Value bit position. */ - -#define TC2_HCMPA_bm 0x10 /* High Byte Compare A Output Value bit mask. */ -#define TC2_HCMPA_bp 4 /* High Byte Compare A Output Value bit position. */ - -#define TC2_LCMPD_bm 0x08 /* Low Byte Compare D Output Value bit mask. */ -#define TC2_LCMPD_bp 3 /* Low Byte Compare D Output Value bit position. */ - -#define TC2_LCMPC_bm 0x04 /* Low Byte Compare C Output Value bit mask. */ -#define TC2_LCMPC_bp 2 /* Low Byte Compare C Output Value bit position. */ - -#define TC2_LCMPB_bm 0x02 /* Low Byte Compare B Output Value bit mask. */ -#define TC2_LCMPB_bp 1 /* Low Byte Compare B Output Value bit position. */ - -#define TC2_LCMPA_bm 0x01 /* Low Byte Compare A Output Value bit mask. */ -#define TC2_LCMPA_bp 0 /* Low Byte Compare A Output Value bit position. */ - -/* TC2.CTRLE bit masks and bit positions */ -#define TC2_BYTEM_gm 0x03 /* Byte Mode group mask. */ -#define TC2_BYTEM_gp 0 /* Byte Mode group position. */ -#define TC2_BYTEM0_bm (1<<0) /* Byte Mode bit 0 mask. */ -#define TC2_BYTEM0_bp 0 /* Byte Mode bit 0 position. */ -#define TC2_BYTEM1_bm (1<<1) /* Byte Mode bit 1 mask. */ -#define TC2_BYTEM1_bp 1 /* Byte Mode bit 1 position. */ - -/* TC2.INTCTRLA bit masks and bit positions */ -#define TC2_HUNFINTLVL_gm 0x0C /* High Byte Underflow Interrupt Level group mask. */ -#define TC2_HUNFINTLVL_gp 2 /* High Byte Underflow Interrupt Level group position. */ -#define TC2_HUNFINTLVL0_bm (1<<2) /* High Byte Underflow Interrupt Level bit 0 mask. */ -#define TC2_HUNFINTLVL0_bp 2 /* High Byte Underflow Interrupt Level bit 0 position. */ -#define TC2_HUNFINTLVL1_bm (1<<3) /* High Byte Underflow Interrupt Level bit 1 mask. */ -#define TC2_HUNFINTLVL1_bp 3 /* High Byte Underflow Interrupt Level bit 1 position. */ - -#define TC2_LUNFINTLVL_gm 0x03 /* Low Byte Underflow interrupt level group mask. */ -#define TC2_LUNFINTLVL_gp 0 /* Low Byte Underflow interrupt level group position. */ -#define TC2_LUNFINTLVL0_bm (1<<0) /* Low Byte Underflow interrupt level bit 0 mask. */ -#define TC2_LUNFINTLVL0_bp 0 /* Low Byte Underflow interrupt level bit 0 position. */ -#define TC2_LUNFINTLVL1_bm (1<<1) /* Low Byte Underflow interrupt level bit 1 mask. */ -#define TC2_LUNFINTLVL1_bp 1 /* Low Byte Underflow interrupt level bit 1 position. */ - -/* TC2.INTCTRLB bit masks and bit positions */ -#define TC2_LCMPDINTLVL_gm 0xC0 /* Low Byte Compare D Interrupt Level group mask. */ -#define TC2_LCMPDINTLVL_gp 6 /* Low Byte Compare D Interrupt Level group position. */ -#define TC2_LCMPDINTLVL0_bm (1<<6) /* Low Byte Compare D Interrupt Level bit 0 mask. */ -#define TC2_LCMPDINTLVL0_bp 6 /* Low Byte Compare D Interrupt Level bit 0 position. */ -#define TC2_LCMPDINTLVL1_bm (1<<7) /* Low Byte Compare D Interrupt Level bit 1 mask. */ -#define TC2_LCMPDINTLVL1_bp 7 /* Low Byte Compare D Interrupt Level bit 1 position. */ - -#define TC2_LCMPCINTLVL_gm 0x30 /* Low Byte Compare C Interrupt Level group mask. */ -#define TC2_LCMPCINTLVL_gp 4 /* Low Byte Compare C Interrupt Level group position. */ -#define TC2_LCMPCINTLVL0_bm (1<<4) /* Low Byte Compare C Interrupt Level bit 0 mask. */ -#define TC2_LCMPCINTLVL0_bp 4 /* Low Byte Compare C Interrupt Level bit 0 position. */ -#define TC2_LCMPCINTLVL1_bm (1<<5) /* Low Byte Compare C Interrupt Level bit 1 mask. */ -#define TC2_LCMPCINTLVL1_bp 5 /* Low Byte Compare C Interrupt Level bit 1 position. */ - -#define TC2_LCMPBINTLVL_gm 0x0C /* Low Byte Compare B Interrupt Level group mask. */ -#define TC2_LCMPBINTLVL_gp 2 /* Low Byte Compare B Interrupt Level group position. */ -#define TC2_LCMPBINTLVL0_bm (1<<2) /* Low Byte Compare B Interrupt Level bit 0 mask. */ -#define TC2_LCMPBINTLVL0_bp 2 /* Low Byte Compare B Interrupt Level bit 0 position. */ -#define TC2_LCMPBINTLVL1_bm (1<<3) /* Low Byte Compare B Interrupt Level bit 1 mask. */ -#define TC2_LCMPBINTLVL1_bp 3 /* Low Byte Compare B Interrupt Level bit 1 position. */ - -#define TC2_LCMPAINTLVL_gm 0x03 /* Low Byte Compare A Interrupt Level group mask. */ -#define TC2_LCMPAINTLVL_gp 0 /* Low Byte Compare A Interrupt Level group position. */ -#define TC2_LCMPAINTLVL0_bm (1<<0) /* Low Byte Compare A Interrupt Level bit 0 mask. */ -#define TC2_LCMPAINTLVL0_bp 0 /* Low Byte Compare A Interrupt Level bit 0 position. */ -#define TC2_LCMPAINTLVL1_bm (1<<1) /* Low Byte Compare A Interrupt Level bit 1 mask. */ -#define TC2_LCMPAINTLVL1_bp 1 /* Low Byte Compare A Interrupt Level bit 1 position. */ - -/* TC2.CTRLF bit masks and bit positions */ -#define TC2_CMD_gm 0x0C /* Command group mask. */ -#define TC2_CMD_gp 2 /* Command group position. */ -#define TC2_CMD0_bm (1<<2) /* Command bit 0 mask. */ -#define TC2_CMD0_bp 2 /* Command bit 0 position. */ -#define TC2_CMD1_bm (1<<3) /* Command bit 1 mask. */ -#define TC2_CMD1_bp 3 /* Command bit 1 position. */ - -#define TC2_CMDEN_gm 0x03 /* Command Enable group mask. */ -#define TC2_CMDEN_gp 0 /* Command Enable group position. */ -#define TC2_CMDEN0_bm (1<<0) /* Command Enable bit 0 mask. */ -#define TC2_CMDEN0_bp 0 /* Command Enable bit 0 position. */ -#define TC2_CMDEN1_bm (1<<1) /* Command Enable bit 1 mask. */ -#define TC2_CMDEN1_bp 1 /* Command Enable bit 1 position. */ - -/* TC2.INTFLAGS bit masks and bit positions */ -#define TC2_LCMPDIF_bm 0x80 /* Low Byte Compare D Interrupt Flag bit mask. */ -#define TC2_LCMPDIF_bp 7 /* Low Byte Compare D Interrupt Flag bit position. */ - -#define TC2_LCMPCIF_bm 0x40 /* Low Byte Compare C Interrupt Flag bit mask. */ -#define TC2_LCMPCIF_bp 6 /* Low Byte Compare C Interrupt Flag bit position. */ - -#define TC2_LCMPBIF_bm 0x20 /* Low Byte Compare B Interrupt Flag bit mask. */ -#define TC2_LCMPBIF_bp 5 /* Low Byte Compare B Interrupt Flag bit position. */ - -#define TC2_LCMPAIF_bm 0x10 /* Low Byte Compare A Interrupt Flag bit mask. */ -#define TC2_LCMPAIF_bp 4 /* Low Byte Compare A Interrupt Flag bit position. */ - -#define TC2_HUNFIF_bm 0x02 /* High Byte Underflow Interrupt Flag bit mask. */ -#define TC2_HUNFIF_bp 1 /* High Byte Underflow Interrupt Flag bit position. */ - -#define TC2_LUNFIF_bm 0x01 /* Low Byte Underflow Interrupt Flag bit mask. */ -#define TC2_LUNFIF_bp 0 /* Low Byte Underflow Interrupt Flag bit position. */ - -/* AWEX - Timer/Counter Advanced Waveform Extension */ -/* AWEX.CTRL bit masks and bit positions */ -#define AWEX_PGM_bm 0x20 /* Pattern Generation Mode bit mask. */ -#define AWEX_PGM_bp 5 /* Pattern Generation Mode bit position. */ - -#define AWEX_CWCM_bm 0x10 /* Common Waveform Channel Mode bit mask. */ -#define AWEX_CWCM_bp 4 /* Common Waveform Channel Mode bit position. */ - -#define AWEX_DTICCDEN_bm 0x08 /* Dead Time Insertion Compare Channel D Enable bit mask. */ -#define AWEX_DTICCDEN_bp 3 /* Dead Time Insertion Compare Channel D Enable bit position. */ - -#define AWEX_DTICCCEN_bm 0x04 /* Dead Time Insertion Compare Channel C Enable bit mask. */ -#define AWEX_DTICCCEN_bp 2 /* Dead Time Insertion Compare Channel C Enable bit position. */ - -#define AWEX_DTICCBEN_bm 0x02 /* Dead Time Insertion Compare Channel B Enable bit mask. */ -#define AWEX_DTICCBEN_bp 1 /* Dead Time Insertion Compare Channel B Enable bit position. */ - -#define AWEX_DTICCAEN_bm 0x01 /* Dead Time Insertion Compare Channel A Enable bit mask. */ -#define AWEX_DTICCAEN_bp 0 /* Dead Time Insertion Compare Channel A Enable bit position. */ - -/* AWEX.FDCTRL bit masks and bit positions */ -#define AWEX_FDDBD_bm 0x10 /* Fault Detect on Disable Break Disable bit mask. */ -#define AWEX_FDDBD_bp 4 /* Fault Detect on Disable Break Disable bit position. */ - -#define AWEX_FDMODE_bm 0x04 /* Fault Detect Mode bit mask. */ -#define AWEX_FDMODE_bp 2 /* Fault Detect Mode bit position. */ - -#define AWEX_FDACT_gm 0x03 /* Fault Detect Action group mask. */ -#define AWEX_FDACT_gp 0 /* Fault Detect Action group position. */ -#define AWEX_FDACT0_bm (1<<0) /* Fault Detect Action bit 0 mask. */ -#define AWEX_FDACT0_bp 0 /* Fault Detect Action bit 0 position. */ -#define AWEX_FDACT1_bm (1<<1) /* Fault Detect Action bit 1 mask. */ -#define AWEX_FDACT1_bp 1 /* Fault Detect Action bit 1 position. */ - -/* AWEX.STATUS bit masks and bit positions */ -#define AWEX_FDF_bm 0x04 /* Fault Detect Flag bit mask. */ -#define AWEX_FDF_bp 2 /* Fault Detect Flag bit position. */ - -#define AWEX_DTHSBUFV_bm 0x02 /* Dead Time High Side Buffer Valid bit mask. */ -#define AWEX_DTHSBUFV_bp 1 /* Dead Time High Side Buffer Valid bit position. */ - -#define AWEX_DTLSBUFV_bm 0x01 /* Dead Time Low Side Buffer Valid bit mask. */ -#define AWEX_DTLSBUFV_bp 0 /* Dead Time Low Side Buffer Valid bit position. */ - -/* AWEX.STATUSSET bit masks and bit positions */ -/* AWEX_FDF Predefined. */ -/* AWEX_FDF Predefined. */ - -/* AWEX_DTHSBUFV Predefined. */ -/* AWEX_DTHSBUFV Predefined. */ - -/* AWEX_DTLSBUFV Predefined. */ -/* AWEX_DTLSBUFV Predefined. */ - -/* HIRES - Timer/Counter High-Resolution Extension */ -/* HIRES.CTRLA bit masks and bit positions */ -#define HIRES_HREN_gm 0x03 /* High Resolution Enable group mask. */ -#define HIRES_HREN_gp 0 /* High Resolution Enable group position. */ -#define HIRES_HREN0_bm (1<<0) /* High Resolution Enable bit 0 mask. */ -#define HIRES_HREN0_bp 0 /* High Resolution Enable bit 0 position. */ -#define HIRES_HREN1_bm (1<<1) /* High Resolution Enable bit 1 mask. */ -#define HIRES_HREN1_bp 1 /* High Resolution Enable bit 1 position. */ - -/* USART - Universal Asynchronous Receiver-Transmitter */ -/* USART.STATUS bit masks and bit positions */ -#define USART_RXCIF_bm 0x80 /* Receive Interrupt Flag bit mask. */ -#define USART_RXCIF_bp 7 /* Receive Interrupt Flag bit position. */ - -#define USART_TXCIF_bm 0x40 /* Transmit Interrupt Flag bit mask. */ -#define USART_TXCIF_bp 6 /* Transmit Interrupt Flag bit position. */ - -#define USART_DREIF_bm 0x20 /* Data Register Empty Flag bit mask. */ -#define USART_DREIF_bp 5 /* Data Register Empty Flag bit position. */ - -#define USART_FERR_bm 0x10 /* Frame Error bit mask. */ -#define USART_FERR_bp 4 /* Frame Error bit position. */ - -#define USART_BUFOVF_bm 0x08 /* Buffer Overflow bit mask. */ -#define USART_BUFOVF_bp 3 /* Buffer Overflow bit position. */ - -#define USART_PERR_bm 0x04 /* Parity Error bit mask. */ -#define USART_PERR_bp 2 /* Parity Error bit position. */ - -#define USART_RXB8_bm 0x01 /* Receive Bit 8 bit mask. */ -#define USART_RXB8_bp 0 /* Receive Bit 8 bit position. */ - -/* USART.CTRLA bit masks and bit positions */ -#define USART_RXCINTLVL_gm 0x30 /* Receive Interrupt Level group mask. */ -#define USART_RXCINTLVL_gp 4 /* Receive Interrupt Level group position. */ -#define USART_RXCINTLVL0_bm (1<<4) /* Receive Interrupt Level bit 0 mask. */ -#define USART_RXCINTLVL0_bp 4 /* Receive Interrupt Level bit 0 position. */ -#define USART_RXCINTLVL1_bm (1<<5) /* Receive Interrupt Level bit 1 mask. */ -#define USART_RXCINTLVL1_bp 5 /* Receive Interrupt Level bit 1 position. */ - -#define USART_TXCINTLVL_gm 0x0C /* Transmit Interrupt Level group mask. */ -#define USART_TXCINTLVL_gp 2 /* Transmit Interrupt Level group position. */ -#define USART_TXCINTLVL0_bm (1<<2) /* Transmit Interrupt Level bit 0 mask. */ -#define USART_TXCINTLVL0_bp 2 /* Transmit Interrupt Level bit 0 position. */ -#define USART_TXCINTLVL1_bm (1<<3) /* Transmit Interrupt Level bit 1 mask. */ -#define USART_TXCINTLVL1_bp 3 /* Transmit Interrupt Level bit 1 position. */ - -#define USART_DREINTLVL_gm 0x03 /* Data Register Empty Interrupt Level group mask. */ -#define USART_DREINTLVL_gp 0 /* Data Register Empty Interrupt Level group position. */ -#define USART_DREINTLVL0_bm (1<<0) /* Data Register Empty Interrupt Level bit 0 mask. */ -#define USART_DREINTLVL0_bp 0 /* Data Register Empty Interrupt Level bit 0 position. */ -#define USART_DREINTLVL1_bm (1<<1) /* Data Register Empty Interrupt Level bit 1 mask. */ -#define USART_DREINTLVL1_bp 1 /* Data Register Empty Interrupt Level bit 1 position. */ - -/* USART.CTRLB bit masks and bit positions */ -#define USART_RXEN_bm 0x10 /* Receiver Enable bit mask. */ -#define USART_RXEN_bp 4 /* Receiver Enable bit position. */ - -#define USART_TXEN_bm 0x08 /* Transmitter Enable bit mask. */ -#define USART_TXEN_bp 3 /* Transmitter Enable bit position. */ - -#define USART_CLK2X_bm 0x04 /* Double transmission speed bit mask. */ -#define USART_CLK2X_bp 2 /* Double transmission speed bit position. */ - -#define USART_MPCM_bm 0x02 /* Multi-processor Communication Mode bit mask. */ -#define USART_MPCM_bp 1 /* Multi-processor Communication Mode bit position. */ - -#define USART_TXB8_bm 0x01 /* Transmit bit 8 bit mask. */ -#define USART_TXB8_bp 0 /* Transmit bit 8 bit position. */ - -/* USART.CTRLC bit masks and bit positions */ -#define USART_CMODE_gm 0xC0 /* Communication Mode group mask. */ -#define USART_CMODE_gp 6 /* Communication Mode group position. */ -#define USART_CMODE0_bm (1<<6) /* Communication Mode bit 0 mask. */ -#define USART_CMODE0_bp 6 /* Communication Mode bit 0 position. */ -#define USART_CMODE1_bm (1<<7) /* Communication Mode bit 1 mask. */ -#define USART_CMODE1_bp 7 /* Communication Mode bit 1 position. */ - -#define USART_PMODE_gm 0x30 /* Parity Mode group mask. */ -#define USART_PMODE_gp 4 /* Parity Mode group position. */ -#define USART_PMODE0_bm (1<<4) /* Parity Mode bit 0 mask. */ -#define USART_PMODE0_bp 4 /* Parity Mode bit 0 position. */ -#define USART_PMODE1_bm (1<<5) /* Parity Mode bit 1 mask. */ -#define USART_PMODE1_bp 5 /* Parity Mode bit 1 position. */ - -#define USART_SBMODE_bm 0x08 /* Stop Bit Mode bit mask. */ -#define USART_SBMODE_bp 3 /* Stop Bit Mode bit position. */ - -#define USART_CHSIZE_gm 0x07 /* Character Size group mask. */ -#define USART_CHSIZE_gp 0 /* Character Size group position. */ -#define USART_CHSIZE0_bm (1<<0) /* Character Size bit 0 mask. */ -#define USART_CHSIZE0_bp 0 /* Character Size bit 0 position. */ -#define USART_CHSIZE1_bm (1<<1) /* Character Size bit 1 mask. */ -#define USART_CHSIZE1_bp 1 /* Character Size bit 1 position. */ -#define USART_CHSIZE2_bm (1<<2) /* Character Size bit 2 mask. */ -#define USART_CHSIZE2_bp 2 /* Character Size bit 2 position. */ - -/* USART.BAUDCTRLA bit masks and bit positions */ -#define USART_BSEL_gm 0xFF /* Baud Rate Selection Bits [7:0] group mask. */ -#define USART_BSEL_gp 0 /* Baud Rate Selection Bits [7:0] group position. */ -#define USART_BSEL0_bm (1<<0) /* Baud Rate Selection Bits [7:0] bit 0 mask. */ -#define USART_BSEL0_bp 0 /* Baud Rate Selection Bits [7:0] bit 0 position. */ -#define USART_BSEL1_bm (1<<1) /* Baud Rate Selection Bits [7:0] bit 1 mask. */ -#define USART_BSEL1_bp 1 /* Baud Rate Selection Bits [7:0] bit 1 position. */ -#define USART_BSEL2_bm (1<<2) /* Baud Rate Selection Bits [7:0] bit 2 mask. */ -#define USART_BSEL2_bp 2 /* Baud Rate Selection Bits [7:0] bit 2 position. */ -#define USART_BSEL3_bm (1<<3) /* Baud Rate Selection Bits [7:0] bit 3 mask. */ -#define USART_BSEL3_bp 3 /* Baud Rate Selection Bits [7:0] bit 3 position. */ -#define USART_BSEL4_bm (1<<4) /* Baud Rate Selection Bits [7:0] bit 4 mask. */ -#define USART_BSEL4_bp 4 /* Baud Rate Selection Bits [7:0] bit 4 position. */ -#define USART_BSEL5_bm (1<<5) /* Baud Rate Selection Bits [7:0] bit 5 mask. */ -#define USART_BSEL5_bp 5 /* Baud Rate Selection Bits [7:0] bit 5 position. */ -#define USART_BSEL6_bm (1<<6) /* Baud Rate Selection Bits [7:0] bit 6 mask. */ -#define USART_BSEL6_bp 6 /* Baud Rate Selection Bits [7:0] bit 6 position. */ -#define USART_BSEL7_bm (1<<7) /* Baud Rate Selection Bits [7:0] bit 7 mask. */ -#define USART_BSEL7_bp 7 /* Baud Rate Selection Bits [7:0] bit 7 position. */ - -/* USART.BAUDCTRLB bit masks and bit positions */ -#define USART_BSCALE_gm 0xF0 /* Baud Rate Scale group mask. */ -#define USART_BSCALE_gp 4 /* Baud Rate Scale group position. */ -#define USART_BSCALE0_bm (1<<4) /* Baud Rate Scale bit 0 mask. */ -#define USART_BSCALE0_bp 4 /* Baud Rate Scale bit 0 position. */ -#define USART_BSCALE1_bm (1<<5) /* Baud Rate Scale bit 1 mask. */ -#define USART_BSCALE1_bp 5 /* Baud Rate Scale bit 1 position. */ -#define USART_BSCALE2_bm (1<<6) /* Baud Rate Scale bit 2 mask. */ -#define USART_BSCALE2_bp 6 /* Baud Rate Scale bit 2 position. */ -#define USART_BSCALE3_bm (1<<7) /* Baud Rate Scale bit 3 mask. */ -#define USART_BSCALE3_bp 7 /* Baud Rate Scale bit 3 position. */ - -/* USART_BSEL Predefined. */ -/* USART_BSEL Predefined. */ - -/* SPI - Serial Peripheral Interface */ -/* SPI.CTRL bit masks and bit positions */ -#define SPI_CLK2X_bm 0x80 /* Enable Double Speed bit mask. */ -#define SPI_CLK2X_bp 7 /* Enable Double Speed bit position. */ - -#define SPI_ENABLE_bm 0x40 /* Enable Module bit mask. */ -#define SPI_ENABLE_bp 6 /* Enable Module bit position. */ - -#define SPI_DORD_bm 0x20 /* Data Order Setting bit mask. */ -#define SPI_DORD_bp 5 /* Data Order Setting bit position. */ - -#define SPI_MASTER_bm 0x10 /* Master Operation Enable bit mask. */ -#define SPI_MASTER_bp 4 /* Master Operation Enable bit position. */ - -#define SPI_MODE_gm 0x0C /* SPI Mode group mask. */ -#define SPI_MODE_gp 2 /* SPI Mode group position. */ -#define SPI_MODE0_bm (1<<2) /* SPI Mode bit 0 mask. */ -#define SPI_MODE0_bp 2 /* SPI Mode bit 0 position. */ -#define SPI_MODE1_bm (1<<3) /* SPI Mode bit 1 mask. */ -#define SPI_MODE1_bp 3 /* SPI Mode bit 1 position. */ - -#define SPI_PRESCALER_gm 0x03 /* Prescaler group mask. */ -#define SPI_PRESCALER_gp 0 /* Prescaler group position. */ -#define SPI_PRESCALER0_bm (1<<0) /* Prescaler bit 0 mask. */ -#define SPI_PRESCALER0_bp 0 /* Prescaler bit 0 position. */ -#define SPI_PRESCALER1_bm (1<<1) /* Prescaler bit 1 mask. */ -#define SPI_PRESCALER1_bp 1 /* Prescaler bit 1 position. */ - -/* SPI.INTCTRL bit masks and bit positions */ -#define SPI_INTLVL_gm 0x03 /* Interrupt level group mask. */ -#define SPI_INTLVL_gp 0 /* Interrupt level group position. */ -#define SPI_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */ -#define SPI_INTLVL0_bp 0 /* Interrupt level bit 0 position. */ -#define SPI_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */ -#define SPI_INTLVL1_bp 1 /* Interrupt level bit 1 position. */ - -/* SPI.STATUS bit masks and bit positions */ -#define SPI_IF_bm 0x80 /* Interrupt Flag bit mask. */ -#define SPI_IF_bp 7 /* Interrupt Flag bit position. */ - -#define SPI_WRCOL_bm 0x40 /* Write Collision bit mask. */ -#define SPI_WRCOL_bp 6 /* Write Collision bit position. */ - -/* IRCOM - IR Communication Module */ -/* IRCOM.CTRL bit masks and bit positions */ -#define IRCOM_EVSEL_gm 0x0F /* Event Channel Select group mask. */ -#define IRCOM_EVSEL_gp 0 /* Event Channel Select group position. */ -#define IRCOM_EVSEL0_bm (1<<0) /* Event Channel Select bit 0 mask. */ -#define IRCOM_EVSEL0_bp 0 /* Event Channel Select bit 0 position. */ -#define IRCOM_EVSEL1_bm (1<<1) /* Event Channel Select bit 1 mask. */ -#define IRCOM_EVSEL1_bp 1 /* Event Channel Select bit 1 position. */ -#define IRCOM_EVSEL2_bm (1<<2) /* Event Channel Select bit 2 mask. */ -#define IRCOM_EVSEL2_bp 2 /* Event Channel Select bit 2 position. */ -#define IRCOM_EVSEL3_bm (1<<3) /* Event Channel Select bit 3 mask. */ -#define IRCOM_EVSEL3_bp 3 /* Event Channel Select bit 3 position. */ - -/* FUSE - Fuses and Lockbits */ -/* NVM_FUSES.FUSEBYTE0 bit masks and bit positions */ -#define NVM_FUSES_JTAGUSERID_gm 0xFF /* JTAG User ID group mask. */ -#define NVM_FUSES_JTAGUSERID_gp 0 /* JTAG User ID group position. */ -#define NVM_FUSES_JTAGUSERID0_bm (1<<0) /* JTAG User ID bit 0 mask. */ -#define NVM_FUSES_JTAGUSERID0_bp 0 /* JTAG User ID bit 0 position. */ -#define NVM_FUSES_JTAGUSERID1_bm (1<<1) /* JTAG User ID bit 1 mask. */ -#define NVM_FUSES_JTAGUSERID1_bp 1 /* JTAG User ID bit 1 position. */ -#define NVM_FUSES_JTAGUSERID2_bm (1<<2) /* JTAG User ID bit 2 mask. */ -#define NVM_FUSES_JTAGUSERID2_bp 2 /* JTAG User ID bit 2 position. */ -#define NVM_FUSES_JTAGUSERID3_bm (1<<3) /* JTAG User ID bit 3 mask. */ -#define NVM_FUSES_JTAGUSERID3_bp 3 /* JTAG User ID bit 3 position. */ -#define NVM_FUSES_JTAGUSERID4_bm (1<<4) /* JTAG User ID bit 4 mask. */ -#define NVM_FUSES_JTAGUSERID4_bp 4 /* JTAG User ID bit 4 position. */ -#define NVM_FUSES_JTAGUSERID5_bm (1<<5) /* JTAG User ID bit 5 mask. */ -#define NVM_FUSES_JTAGUSERID5_bp 5 /* JTAG User ID bit 5 position. */ -#define NVM_FUSES_JTAGUSERID6_bm (1<<6) /* JTAG User ID bit 6 mask. */ -#define NVM_FUSES_JTAGUSERID6_bp 6 /* JTAG User ID bit 6 position. */ -#define NVM_FUSES_JTAGUSERID7_bm (1<<7) /* JTAG User ID bit 7 mask. */ -#define NVM_FUSES_JTAGUSERID7_bp 7 /* JTAG User ID bit 7 position. */ - -/* NVM_FUSES.FUSEBYTE1 bit masks and bit positions */ -#define NVM_FUSES_WDWP_gm 0xF0 /* Watchdog Window Timeout Period group mask. */ -#define NVM_FUSES_WDWP_gp 4 /* Watchdog Window Timeout Period group position. */ -#define NVM_FUSES_WDWP0_bm (1<<4) /* Watchdog Window Timeout Period bit 0 mask. */ -#define NVM_FUSES_WDWP0_bp 4 /* Watchdog Window Timeout Period bit 0 position. */ -#define NVM_FUSES_WDWP1_bm (1<<5) /* Watchdog Window Timeout Period bit 1 mask. */ -#define NVM_FUSES_WDWP1_bp 5 /* Watchdog Window Timeout Period bit 1 position. */ -#define NVM_FUSES_WDWP2_bm (1<<6) /* Watchdog Window Timeout Period bit 2 mask. */ -#define NVM_FUSES_WDWP2_bp 6 /* Watchdog Window Timeout Period bit 2 position. */ -#define NVM_FUSES_WDWP3_bm (1<<7) /* Watchdog Window Timeout Period bit 3 mask. */ -#define NVM_FUSES_WDWP3_bp 7 /* Watchdog Window Timeout Period bit 3 position. */ - -#define NVM_FUSES_WDP_gm 0x0F /* Watchdog Timeout Period group mask. */ -#define NVM_FUSES_WDP_gp 0 /* Watchdog Timeout Period group position. */ -#define NVM_FUSES_WDP0_bm (1<<0) /* Watchdog Timeout Period bit 0 mask. */ -#define NVM_FUSES_WDP0_bp 0 /* Watchdog Timeout Period bit 0 position. */ -#define NVM_FUSES_WDP1_bm (1<<1) /* Watchdog Timeout Period bit 1 mask. */ -#define NVM_FUSES_WDP1_bp 1 /* Watchdog Timeout Period bit 1 position. */ -#define NVM_FUSES_WDP2_bm (1<<2) /* Watchdog Timeout Period bit 2 mask. */ -#define NVM_FUSES_WDP2_bp 2 /* Watchdog Timeout Period bit 2 position. */ -#define NVM_FUSES_WDP3_bm (1<<3) /* Watchdog Timeout Period bit 3 mask. */ -#define NVM_FUSES_WDP3_bp 3 /* Watchdog Timeout Period bit 3 position. */ - -/* NVM_FUSES.FUSEBYTE2 bit masks and bit positions */ -#define NVM_FUSES_BOOTRST_bm 0x40 /* Boot Loader Section Reset Vector bit mask. */ -#define NVM_FUSES_BOOTRST_bp 6 /* Boot Loader Section Reset Vector bit position. */ - -#define NVM_FUSES_TOSCSEL_bm 0x20 /* Timer Oscillator pin location bit mask. */ -#define NVM_FUSES_TOSCSEL_bp 5 /* Timer Oscillator pin location bit position. */ - -#define NVM_FUSES_BODPD_gm 0x03 /* BOD Operation in Power-Down Mode group mask. */ -#define NVM_FUSES_BODPD_gp 0 /* BOD Operation in Power-Down Mode group position. */ -#define NVM_FUSES_BODPD0_bm (1<<0) /* BOD Operation in Power-Down Mode bit 0 mask. */ -#define NVM_FUSES_BODPD0_bp 0 /* BOD Operation in Power-Down Mode bit 0 position. */ -#define NVM_FUSES_BODPD1_bm (1<<1) /* BOD Operation in Power-Down Mode bit 1 mask. */ -#define NVM_FUSES_BODPD1_bp 1 /* BOD Operation in Power-Down Mode bit 1 position. */ - -/* NVM_FUSES.FUSEBYTE4 bit masks and bit positions */ -#define NVM_FUSES_RSTDISBL_bm 0x10 /* External Reset Disable bit mask. */ -#define NVM_FUSES_RSTDISBL_bp 4 /* External Reset Disable bit position. */ - -#define NVM_FUSES_SUT_gm 0x0C /* Start-up Time group mask. */ -#define NVM_FUSES_SUT_gp 2 /* Start-up Time group position. */ -#define NVM_FUSES_SUT0_bm (1<<2) /* Start-up Time bit 0 mask. */ -#define NVM_FUSES_SUT0_bp 2 /* Start-up Time bit 0 position. */ -#define NVM_FUSES_SUT1_bm (1<<3) /* Start-up Time bit 1 mask. */ -#define NVM_FUSES_SUT1_bp 3 /* Start-up Time bit 1 position. */ - -#define NVM_FUSES_WDLOCK_bm 0x02 /* Watchdog Timer Lock bit mask. */ -#define NVM_FUSES_WDLOCK_bp 1 /* Watchdog Timer Lock bit position. */ - -#define NVM_FUSES_JTAGEN_bm 0x01 /* JTAG Interface Enable bit mask. */ -#define NVM_FUSES_JTAGEN_bp 0 /* JTAG Interface Enable bit position. */ - -/* NVM_FUSES.FUSEBYTE5 bit masks and bit positions */ -#define NVM_FUSES_BODACT_gm 0x30 /* BOD Operation in Active Mode group mask. */ -#define NVM_FUSES_BODACT_gp 4 /* BOD Operation in Active Mode group position. */ -#define NVM_FUSES_BODACT0_bm (1<<4) /* BOD Operation in Active Mode bit 0 mask. */ -#define NVM_FUSES_BODACT0_bp 4 /* BOD Operation in Active Mode bit 0 position. */ -#define NVM_FUSES_BODACT1_bm (1<<5) /* BOD Operation in Active Mode bit 1 mask. */ -#define NVM_FUSES_BODACT1_bp 5 /* BOD Operation in Active Mode bit 1 position. */ - -#define NVM_FUSES_EESAVE_bm 0x08 /* Preserve EEPROM Through Chip Erase bit mask. */ -#define NVM_FUSES_EESAVE_bp 3 /* Preserve EEPROM Through Chip Erase bit position. */ - -#define NVM_FUSES_BODLVL_gm 0x07 /* Brownout Detection Voltage Level group mask. */ -#define NVM_FUSES_BODLVL_gp 0 /* Brownout Detection Voltage Level group position. */ -#define NVM_FUSES_BODLVL0_bm (1<<0) /* Brownout Detection Voltage Level bit 0 mask. */ -#define NVM_FUSES_BODLVL0_bp 0 /* Brownout Detection Voltage Level bit 0 position. */ -#define NVM_FUSES_BODLVL1_bm (1<<1) /* Brownout Detection Voltage Level bit 1 mask. */ -#define NVM_FUSES_BODLVL1_bp 1 /* Brownout Detection Voltage Level bit 1 position. */ -#define NVM_FUSES_BODLVL2_bm (1<<2) /* Brownout Detection Voltage Level bit 2 mask. */ -#define NVM_FUSES_BODLVL2_bp 2 /* Brownout Detection Voltage Level bit 2 position. */ - -/* LOCKBIT - Fuses and Lockbits */ -/* NVM_LOCKBITS.LOCKBITS bit masks and bit positions */ -#define NVM_LOCKBITS_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ -#define NVM_LOCKBITS_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ -#define NVM_LOCKBITS_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ -#define NVM_LOCKBITS_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ -#define NVM_LOCKBITS_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ -#define NVM_LOCKBITS_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ - -#define NVM_LOCKBITS_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ -#define NVM_LOCKBITS_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ -#define NVM_LOCKBITS_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ -#define NVM_LOCKBITS_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ -#define NVM_LOCKBITS_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ -#define NVM_LOCKBITS_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ - -#define NVM_LOCKBITS_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ -#define NVM_LOCKBITS_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ -#define NVM_LOCKBITS_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ -#define NVM_LOCKBITS_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ -#define NVM_LOCKBITS_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ -#define NVM_LOCKBITS_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ - -#define NVM_LOCKBITS_LB_gm 0x03 /* Lock Bits group mask. */ -#define NVM_LOCKBITS_LB_gp 0 /* Lock Bits group position. */ -#define NVM_LOCKBITS_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ -#define NVM_LOCKBITS_LB0_bp 0 /* Lock Bits bit 0 position. */ -#define NVM_LOCKBITS_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ -#define NVM_LOCKBITS_LB1_bp 1 /* Lock Bits bit 1 position. */ - - - -// Generic Port Pins - -#define PIN0_bm 0x01 -#define PIN0_bp 0 -#define PIN1_bm 0x02 -#define PIN1_bp 1 -#define PIN2_bm 0x04 -#define PIN2_bp 2 -#define PIN3_bm 0x08 -#define PIN3_bp 3 -#define PIN4_bm 0x10 -#define PIN4_bp 4 -#define PIN5_bm 0x20 -#define PIN5_bp 5 -#define PIN6_bm 0x40 -#define PIN6_bp 6 -#define PIN7_bm 0x80 -#define PIN7_bp 7 - -/* ========== Interrupt Vector Definitions ========== */ -/* Vector 0 is the reset vector */ - -/* OSC interrupt vectors */ -#define OSC_OSCF_vect_num 1 -#define OSC_OSCF_vect _VECTOR(1) /* Oscillator Failure Interrupt (NMI) */ - -/* PORTC interrupt vectors */ -#define PORTC_INT0_vect_num 2 -#define PORTC_INT0_vect _VECTOR(2) /* External Interrupt 0 */ -#define PORTC_INT1_vect_num 3 -#define PORTC_INT1_vect _VECTOR(3) /* External Interrupt 1 */ - -/* PORTR interrupt vectors */ -#define PORTR_INT0_vect_num 4 -#define PORTR_INT0_vect _VECTOR(4) /* External Interrupt 0 */ -#define PORTR_INT1_vect_num 5 -#define PORTR_INT1_vect _VECTOR(5) /* External Interrupt 1 */ - -/* DMA interrupt vectors */ -#define DMA_CH0_vect_num 6 -#define DMA_CH0_vect _VECTOR(6) /* Channel 0 Interrupt */ -#define DMA_CH1_vect_num 7 -#define DMA_CH1_vect _VECTOR(7) /* Channel 1 Interrupt */ -#define DMA_CH2_vect_num 8 -#define DMA_CH2_vect _VECTOR(8) /* Channel 2 Interrupt */ -#define DMA_CH3_vect_num 9 -#define DMA_CH3_vect _VECTOR(9) /* Channel 3 Interrupt */ - -/* RTC32 interrupt vectors */ -#define RTC32_OVF_vect_num 10 -#define RTC32_OVF_vect _VECTOR(10) /* Overflow Interrupt */ -#define RTC32_COMP_vect_num 11 -#define RTC32_COMP_vect _VECTOR(11) /* Compare Interrupt */ - -/* TWIC interrupt vectors */ -#define TWIC_TWIS_vect_num 12 -#define TWIC_TWIS_vect _VECTOR(12) /* TWI Slave Interrupt */ -#define TWIC_TWIM_vect_num 13 -#define TWIC_TWIM_vect _VECTOR(13) /* TWI Master Interrupt */ - -/* TCC0 interrupt vectors */ -#define TCC0_OVF_vect_num 14 -#define TCC0_OVF_vect _VECTOR(14) /* Overflow Interrupt */ - -/* TCC2 interrupt vectors */ -#define TCC2_LUNF_vect_num 14 -#define TCC2_LUNF_vect _VECTOR(14) /* Low Byte Underflow Interrupt */ - -/* TCC0 interrupt vectors */ -#define TCC0_ERR_vect_num 15 -#define TCC0_ERR_vect _VECTOR(15) /* Error Interrupt */ - -/* TCC2 interrupt vectors */ -#define TCC2_HUNF_vect_num 15 -#define TCC2_HUNF_vect _VECTOR(15) /* High Byte Underflow Interrupt */ - -/* TCC0 interrupt vectors */ -#define TCC0_CCA_vect_num 16 -#define TCC0_CCA_vect _VECTOR(16) /* Compare or Capture A Interrupt */ - -/* TCC2 interrupt vectors */ -#define TCC2_LCMPA_vect_num 16 -#define TCC2_LCMPA_vect _VECTOR(16) /* Low Byte Compare A Interrupt */ - -/* TCC0 interrupt vectors */ -#define TCC0_CCB_vect_num 17 -#define TCC0_CCB_vect _VECTOR(17) /* Compare or Capture B Interrupt */ - -/* TCC2 interrupt vectors */ -#define TCC2_LCMPB_vect_num 17 -#define TCC2_LCMPB_vect _VECTOR(17) /* Low Byte Compare B Interrupt */ - -/* TCC0 interrupt vectors */ -#define TCC0_CCC_vect_num 18 -#define TCC0_CCC_vect _VECTOR(18) /* Compare or Capture C Interrupt */ - -/* TCC2 interrupt vectors */ -#define TCC2_LCMPC_vect_num 18 -#define TCC2_LCMPC_vect _VECTOR(18) /* Low Byte Compare C Interrupt */ - -/* TCC0 interrupt vectors */ -#define TCC0_CCD_vect_num 19 -#define TCC0_CCD_vect _VECTOR(19) /* Compare or Capture D Interrupt */ - -/* TCC2 interrupt vectors */ -#define TCC2_LCMPD_vect_num 19 -#define TCC2_LCMPD_vect _VECTOR(19) /* Low Byte Compare D Interrupt */ - -/* TCC1 interrupt vectors */ -#define TCC1_OVF_vect_num 20 -#define TCC1_OVF_vect _VECTOR(20) /* Overflow Interrupt */ -#define TCC1_ERR_vect_num 21 -#define TCC1_ERR_vect _VECTOR(21) /* Error Interrupt */ -#define TCC1_CCA_vect_num 22 -#define TCC1_CCA_vect _VECTOR(22) /* Compare or Capture A Interrupt */ -#define TCC1_CCB_vect_num 23 -#define TCC1_CCB_vect _VECTOR(23) /* Compare or Capture B Interrupt */ - -/* SPIC interrupt vectors */ -#define SPIC_INT_vect_num 24 -#define SPIC_INT_vect _VECTOR(24) /* SPI Interrupt */ - -/* USARTC0 interrupt vectors */ -#define USARTC0_RXC_vect_num 25 -#define USARTC0_RXC_vect _VECTOR(25) /* Reception Complete Interrupt */ -#define USARTC0_DRE_vect_num 26 -#define USARTC0_DRE_vect _VECTOR(26) /* Data Register Empty Interrupt */ -#define USARTC0_TXC_vect_num 27 -#define USARTC0_TXC_vect _VECTOR(27) /* Transmission Complete Interrupt */ - -/* USARTC1 interrupt vectors */ -#define USARTC1_RXC_vect_num 28 -#define USARTC1_RXC_vect _VECTOR(28) /* Reception Complete Interrupt */ -#define USARTC1_DRE_vect_num 29 -#define USARTC1_DRE_vect _VECTOR(29) /* Data Register Empty Interrupt */ -#define USARTC1_TXC_vect_num 30 -#define USARTC1_TXC_vect _VECTOR(30) /* Transmission Complete Interrupt */ - -/* AES interrupt vectors */ -#define AES_INT_vect_num 31 -#define AES_INT_vect _VECTOR(31) /* AES Interrupt */ - -/* NVM interrupt vectors */ -#define NVM_EE_vect_num 32 -#define NVM_EE_vect _VECTOR(32) /* EE Interrupt */ -#define NVM_SPM_vect_num 33 -#define NVM_SPM_vect _VECTOR(33) /* SPM Interrupt */ - -/* PORTB interrupt vectors */ -#define PORTB_INT0_vect_num 34 -#define PORTB_INT0_vect _VECTOR(34) /* External Interrupt 0 */ -#define PORTB_INT1_vect_num 35 -#define PORTB_INT1_vect _VECTOR(35) /* External Interrupt 1 */ - -/* ACB interrupt vectors */ -#define ACB_AC0_vect_num 36 -#define ACB_AC0_vect _VECTOR(36) /* AC0 Interrupt */ -#define ACB_AC1_vect_num 37 -#define ACB_AC1_vect _VECTOR(37) /* AC1 Interrupt */ -#define ACB_ACW_vect_num 38 -#define ACB_ACW_vect _VECTOR(38) /* ACW Window Mode Interrupt */ - -/* ADCB interrupt vectors */ -#define ADCB_CH0_vect_num 39 -#define ADCB_CH0_vect _VECTOR(39) /* Interrupt 0 */ -#define ADCB_CH1_vect_num 40 -#define ADCB_CH1_vect _VECTOR(40) /* Interrupt 1 */ -#define ADCB_CH2_vect_num 41 -#define ADCB_CH2_vect _VECTOR(41) /* Interrupt 2 */ -#define ADCB_CH3_vect_num 42 -#define ADCB_CH3_vect _VECTOR(42) /* Interrupt 3 */ - -/* PORTE interrupt vectors */ -#define PORTE_INT0_vect_num 43 -#define PORTE_INT0_vect _VECTOR(43) /* External Interrupt 0 */ -#define PORTE_INT1_vect_num 44 -#define PORTE_INT1_vect _VECTOR(44) /* External Interrupt 1 */ - -/* TWIE interrupt vectors */ -#define TWIE_TWIS_vect_num 45 -#define TWIE_TWIS_vect _VECTOR(45) /* TWI Slave Interrupt */ -#define TWIE_TWIM_vect_num 46 -#define TWIE_TWIM_vect _VECTOR(46) /* TWI Master Interrupt */ - -/* TCE0 interrupt vectors */ -#define TCE0_OVF_vect_num 47 -#define TCE0_OVF_vect _VECTOR(47) /* Overflow Interrupt */ - -/* TCE2 interrupt vectors */ -#define TCE2_LUNF_vect_num 47 -#define TCE2_LUNF_vect _VECTOR(47) /* Low Byte Underflow Interrupt */ - -/* TCE0 interrupt vectors */ -#define TCE0_ERR_vect_num 48 -#define TCE0_ERR_vect _VECTOR(48) /* Error Interrupt */ - -/* TCE2 interrupt vectors */ -#define TCE2_HUNF_vect_num 48 -#define TCE2_HUNF_vect _VECTOR(48) /* High Byte Underflow Interrupt */ - -/* TCE0 interrupt vectors */ -#define TCE0_CCA_vect_num 49 -#define TCE0_CCA_vect _VECTOR(49) /* Compare or Capture A Interrupt */ - -/* TCE2 interrupt vectors */ -#define TCE2_LCMPA_vect_num 49 -#define TCE2_LCMPA_vect _VECTOR(49) /* Low Byte Compare A Interrupt */ - -/* TCE0 interrupt vectors */ -#define TCE0_CCB_vect_num 50 -#define TCE0_CCB_vect _VECTOR(50) /* Compare or Capture B Interrupt */ - -/* TCE2 interrupt vectors */ -#define TCE2_LCMPB_vect_num 50 -#define TCE2_LCMPB_vect _VECTOR(50) /* Low Byte Compare B Interrupt */ - -/* TCE0 interrupt vectors */ -#define TCE0_CCC_vect_num 51 -#define TCE0_CCC_vect _VECTOR(51) /* Compare or Capture C Interrupt */ - -/* TCE2 interrupt vectors */ -#define TCE2_LCMPC_vect_num 51 -#define TCE2_LCMPC_vect _VECTOR(51) /* Low Byte Compare C Interrupt */ - -/* TCE0 interrupt vectors */ -#define TCE0_CCD_vect_num 52 -#define TCE0_CCD_vect _VECTOR(52) /* Compare or Capture D Interrupt */ - -/* TCE2 interrupt vectors */ -#define TCE2_LCMPD_vect_num 52 -#define TCE2_LCMPD_vect _VECTOR(52) /* Low Byte Compare D Interrupt */ - -/* TCE1 interrupt vectors */ -#define TCE1_OVF_vect_num 53 -#define TCE1_OVF_vect _VECTOR(53) /* Overflow Interrupt */ -#define TCE1_ERR_vect_num 54 -#define TCE1_ERR_vect _VECTOR(54) /* Error Interrupt */ -#define TCE1_CCA_vect_num 55 -#define TCE1_CCA_vect _VECTOR(55) /* Compare or Capture A Interrupt */ -#define TCE1_CCB_vect_num 56 -#define TCE1_CCB_vect _VECTOR(56) /* Compare or Capture B Interrupt */ - -/* USARTE0 interrupt vectors */ -#define USARTE0_RXC_vect_num 58 -#define USARTE0_RXC_vect _VECTOR(58) /* Reception Complete Interrupt */ -#define USARTE0_DRE_vect_num 59 -#define USARTE0_DRE_vect _VECTOR(59) /* Data Register Empty Interrupt */ -#define USARTE0_TXC_vect_num 60 -#define USARTE0_TXC_vect _VECTOR(60) /* Transmission Complete Interrupt */ - -/* PORTD interrupt vectors */ -#define PORTD_INT0_vect_num 64 -#define PORTD_INT0_vect _VECTOR(64) /* External Interrupt 0 */ -#define PORTD_INT1_vect_num 65 -#define PORTD_INT1_vect _VECTOR(65) /* External Interrupt 1 */ - -/* PORTA interrupt vectors */ -#define PORTA_INT0_vect_num 66 -#define PORTA_INT0_vect _VECTOR(66) /* External Interrupt 0 */ -#define PORTA_INT1_vect_num 67 -#define PORTA_INT1_vect _VECTOR(67) /* External Interrupt 1 */ - -/* ACA interrupt vectors */ -#define ACA_AC0_vect_num 68 -#define ACA_AC0_vect _VECTOR(68) /* AC0 Interrupt */ -#define ACA_AC1_vect_num 69 -#define ACA_AC1_vect _VECTOR(69) /* AC1 Interrupt */ -#define ACA_ACW_vect_num 70 -#define ACA_ACW_vect _VECTOR(70) /* ACW Window Mode Interrupt */ - -/* ADCA interrupt vectors */ -#define ADCA_CH0_vect_num 71 -#define ADCA_CH0_vect _VECTOR(71) /* Interrupt 0 */ -#define ADCA_CH1_vect_num 72 -#define ADCA_CH1_vect _VECTOR(72) /* Interrupt 1 */ -#define ADCA_CH2_vect_num 73 -#define ADCA_CH2_vect _VECTOR(73) /* Interrupt 2 */ -#define ADCA_CH3_vect_num 74 -#define ADCA_CH3_vect _VECTOR(74) /* Interrupt 3 */ - -/* TCD0 interrupt vectors */ -#define TCD0_OVF_vect_num 77 -#define TCD0_OVF_vect _VECTOR(77) /* Overflow Interrupt */ - -/* TCD2 interrupt vectors */ -#define TCD2_LUNF_vect_num 77 -#define TCD2_LUNF_vect _VECTOR(77) /* Low Byte Underflow Interrupt */ - -/* TCD0 interrupt vectors */ -#define TCD0_ERR_vect_num 78 -#define TCD0_ERR_vect _VECTOR(78) /* Error Interrupt */ - -/* TCD2 interrupt vectors */ -#define TCD2_HUNF_vect_num 78 -#define TCD2_HUNF_vect _VECTOR(78) /* High Byte Underflow Interrupt */ - -/* TCD0 interrupt vectors */ -#define TCD0_CCA_vect_num 79 -#define TCD0_CCA_vect _VECTOR(79) /* Compare or Capture A Interrupt */ - -/* TCD2 interrupt vectors */ -#define TCD2_LCMPA_vect_num 79 -#define TCD2_LCMPA_vect _VECTOR(79) /* Low Byte Compare A Interrupt */ - -/* TCD0 interrupt vectors */ -#define TCD0_CCB_vect_num 80 -#define TCD0_CCB_vect _VECTOR(80) /* Compare or Capture B Interrupt */ - -/* TCD2 interrupt vectors */ -#define TCD2_LCMPB_vect_num 80 -#define TCD2_LCMPB_vect _VECTOR(80) /* Low Byte Compare B Interrupt */ - -/* TCD0 interrupt vectors */ -#define TCD0_CCC_vect_num 81 -#define TCD0_CCC_vect _VECTOR(81) /* Compare or Capture C Interrupt */ - -/* TCD2 interrupt vectors */ -#define TCD2_LCMPC_vect_num 81 -#define TCD2_LCMPC_vect _VECTOR(81) /* Low Byte Compare C Interrupt */ - -/* TCD0 interrupt vectors */ -#define TCD0_CCD_vect_num 82 -#define TCD0_CCD_vect _VECTOR(82) /* Compare or Capture D Interrupt */ - -/* TCD2 interrupt vectors */ -#define TCD2_LCMPD_vect_num 82 -#define TCD2_LCMPD_vect _VECTOR(82) /* Low Byte Compare D Interrupt */ - -/* TCD1 interrupt vectors */ -#define TCD1_OVF_vect_num 83 -#define TCD1_OVF_vect _VECTOR(83) /* Overflow Interrupt */ -#define TCD1_ERR_vect_num 84 -#define TCD1_ERR_vect _VECTOR(84) /* Error Interrupt */ -#define TCD1_CCA_vect_num 85 -#define TCD1_CCA_vect _VECTOR(85) /* Compare or Capture A Interrupt */ -#define TCD1_CCB_vect_num 86 -#define TCD1_CCB_vect _VECTOR(86) /* Compare or Capture B Interrupt */ - -/* SPID interrupt vectors */ -#define SPID_INT_vect_num 87 -#define SPID_INT_vect _VECTOR(87) /* SPI Interrupt */ - -/* USARTD0 interrupt vectors */ -#define USARTD0_RXC_vect_num 88 -#define USARTD0_RXC_vect _VECTOR(88) /* Reception Complete Interrupt */ -#define USARTD0_DRE_vect_num 89 -#define USARTD0_DRE_vect _VECTOR(89) /* Data Register Empty Interrupt */ -#define USARTD0_TXC_vect_num 90 -#define USARTD0_TXC_vect _VECTOR(90) /* Transmission Complete Interrupt */ - -/* USARTD1 interrupt vectors */ -#define USARTD1_RXC_vect_num 91 -#define USARTD1_RXC_vect _VECTOR(91) /* Reception Complete Interrupt */ -#define USARTD1_DRE_vect_num 92 -#define USARTD1_DRE_vect _VECTOR(92) /* Data Register Empty Interrupt */ -#define USARTD1_TXC_vect_num 93 -#define USARTD1_TXC_vect _VECTOR(93) /* Transmission Complete Interrupt */ - -/* PORTF interrupt vectors */ -#define PORTF_INT0_vect_num 104 -#define PORTF_INT0_vect _VECTOR(104) /* External Interrupt 0 */ -#define PORTF_INT1_vect_num 105 -#define PORTF_INT1_vect _VECTOR(105) /* External Interrupt 1 */ - -/* TCF0 interrupt vectors */ -#define TCF0_OVF_vect_num 108 -#define TCF0_OVF_vect _VECTOR(108) /* Overflow Interrupt */ - -/* TCF2 interrupt vectors */ -#define TCF2_LUNF_vect_num 108 -#define TCF2_LUNF_vect _VECTOR(108) /* Low Byte Underflow Interrupt */ - -/* TCF0 interrupt vectors */ -#define TCF0_ERR_vect_num 109 -#define TCF0_ERR_vect _VECTOR(109) /* Error Interrupt */ - -/* TCF2 interrupt vectors */ -#define TCF2_HUNF_vect_num 109 -#define TCF2_HUNF_vect _VECTOR(109) /* High Byte Underflow Interrupt */ - -/* TCF0 interrupt vectors */ -#define TCF0_CCA_vect_num 110 -#define TCF0_CCA_vect _VECTOR(110) /* Compare or Capture A Interrupt */ - -/* TCF2 interrupt vectors */ -#define TCF2_LCMPA_vect_num 110 -#define TCF2_LCMPA_vect _VECTOR(110) /* Low Byte Compare A Interrupt */ - -/* TCF0 interrupt vectors */ -#define TCF0_CCB_vect_num 111 -#define TCF0_CCB_vect _VECTOR(111) /* Compare or Capture B Interrupt */ - -/* TCF2 interrupt vectors */ -#define TCF2_LCMPB_vect_num 111 -#define TCF2_LCMPB_vect _VECTOR(111) /* Low Byte Compare B Interrupt */ - -/* TCF0 interrupt vectors */ -#define TCF0_CCC_vect_num 112 -#define TCF0_CCC_vect _VECTOR(112) /* Compare or Capture C Interrupt */ - -/* TCF2 interrupt vectors */ -#define TCF2_LCMPC_vect_num 112 -#define TCF2_LCMPC_vect _VECTOR(112) /* Low Byte Compare C Interrupt */ - -/* TCF0 interrupt vectors */ -#define TCF0_CCD_vect_num 113 -#define TCF0_CCD_vect _VECTOR(113) /* Compare or Capture D Interrupt */ - -/* TCF2 interrupt vectors */ -#define TCF2_LCMPD_vect_num 113 -#define TCF2_LCMPD_vect _VECTOR(113) /* Low Byte Compare D Interrupt */ - -/* USARTF0 interrupt vectors */ -#define USARTF0_RXC_vect_num 119 -#define USARTF0_RXC_vect _VECTOR(119) /* Reception Complete Interrupt */ -#define USARTF0_DRE_vect_num 120 -#define USARTF0_DRE_vect _VECTOR(120) /* Data Register Empty Interrupt */ -#define USARTF0_TXC_vect_num 121 -#define USARTF0_TXC_vect _VECTOR(121) /* Transmission Complete Interrupt */ - -/* USB interrupt vectors */ -#define USB_BUSEVENT_vect_num 125 -#define USB_BUSEVENT_vect _VECTOR(125) /* SOF, suspend, resume, reset bus event interrupts, crc, underflow, overflow and stall error interrupts */ -#define USB_TRNCOMPL_vect_num 126 -#define USB_TRNCOMPL_vect _VECTOR(126) /* Transaction complete interrupt */ - -#define _VECTOR_SIZE 4 /* Size of individual vector. */ -#define _VECTORS_SIZE (127 * _VECTOR_SIZE) - - -/* ========== Constants ========== */ - -#define PROGMEM_START (0x0000) -#define PROGMEM_SIZE (270336) -#define PROGMEM_END (PROGMEM_START + PROGMEM_SIZE - 1) - -#define APP_SECTION_START (0x0000) -#define APP_SECTION_SIZE (262144) -#define APP_SECTION_PAGE_SIZE (512) -#define APP_SECTION_END (APP_SECTION_START + APP_SECTION_SIZE - 1) - -#define APPTABLE_SECTION_START (0x3E000) -#define APPTABLE_SECTION_SIZE (8192) -#define APPTABLE_SECTION_PAGE_SIZE (512) -#define APPTABLE_SECTION_END (APPTABLE_SECTION_START + APPTABLE_SECTION_SIZE - 1) - -#define BOOT_SECTION_START (0x40000) -#define BOOT_SECTION_SIZE (8192) -#define BOOT_SECTION_PAGE_SIZE (512) -#define BOOT_SECTION_END (BOOT_SECTION_START + BOOT_SECTION_SIZE - 1) - -#define DATAMEM_START (0x0000) -#define DATAMEM_SIZE (24576) -#define DATAMEM_END (DATAMEM_START + DATAMEM_SIZE - 1) - -#define IO_START (0x0000) -#define IO_SIZE (4096) -#define IO_PAGE_SIZE (0) -#define IO_END (IO_START + IO_SIZE - 1) - -#define MAPPED_EEPROM_START (0x1000) -#define MAPPED_EEPROM_SIZE (4096) -#define MAPPED_EEPROM_PAGE_SIZE (0) -#define MAPPED_EEPROM_END (MAPPED_EEPROM_START + MAPPED_EEPROM_SIZE - 1) - -#define INTERNAL_SRAM_START (0x2000) -#define INTERNAL_SRAM_SIZE (16384) -#define INTERNAL_SRAM_PAGE_SIZE (0) -#define INTERNAL_SRAM_END (INTERNAL_SRAM_START + INTERNAL_SRAM_SIZE - 1) - -#define EEPROM_START (0x0000) -#define EEPROM_SIZE (4096) -#define EEPROM_PAGE_SIZE (32) -#define EEPROM_END (EEPROM_START + EEPROM_SIZE - 1) - -#define SIGNATURES_START (0x0000) -#define SIGNATURES_SIZE (3) -#define SIGNATURES_PAGE_SIZE (0) -#define SIGNATURES_END (SIGNATURES_START + SIGNATURES_SIZE - 1) - -#define FUSES_START (0x0000) -#define FUSES_SIZE (6) -#define FUSES_PAGE_SIZE (0) -#define FUSES_END (FUSES_START + FUSES_SIZE - 1) - -#define LOCKBITS_START (0x0000) -#define LOCKBITS_SIZE (1) -#define LOCKBITS_PAGE_SIZE (0) -#define LOCKBITS_END (LOCKBITS_START + LOCKBITS_SIZE - 1) - -#define USER_SIGNATURES_START (0x0000) -#define USER_SIGNATURES_SIZE (512) -#define USER_SIGNATURES_PAGE_SIZE (512) -#define USER_SIGNATURES_END (USER_SIGNATURES_START + USER_SIGNATURES_SIZE - 1) - -#define PROD_SIGNATURES_START (0x0000) -#define PROD_SIGNATURES_SIZE (52) -#define PROD_SIGNATURES_PAGE_SIZE (512) -#define PROD_SIGNATURES_END (PROD_SIGNATURES_START + PROD_SIGNATURES_SIZE - 1) - -#define FLASHSTART PROGMEM_START -#define FLASHEND PROGMEM_END -#define SPM_PAGESIZE 512 -#define RAMSTART INTERNAL_SRAM_START -#define RAMSIZE INTERNAL_SRAM_SIZE -#define RAMEND INTERNAL_SRAM_END -#define E2END EEPROM_END -#define E2PAGESIZE EEPROM_PAGE_SIZE - - -/* ========== Fuses ========== */ -#define FUSE_MEMORY_SIZE 6 - -/* Fuse Byte 0 */ -#define FUSE_JTAGUSERID0 (unsigned char)~_BV(0) /* JTAG User ID Bit 0 */ -#define FUSE_JTAGUSERID1 (unsigned char)~_BV(1) /* JTAG User ID Bit 1 */ -#define FUSE_JTAGUSERID2 (unsigned char)~_BV(2) /* JTAG User ID Bit 2 */ -#define FUSE_JTAGUSERID3 (unsigned char)~_BV(3) /* JTAG User ID Bit 3 */ -#define FUSE_JTAGUSERID4 (unsigned char)~_BV(4) /* JTAG User ID Bit 4 */ -#define FUSE_JTAGUSERID5 (unsigned char)~_BV(5) /* JTAG User ID Bit 5 */ -#define FUSE_JTAGUSERID6 (unsigned char)~_BV(6) /* JTAG User ID Bit 6 */ -#define FUSE_JTAGUSERID7 (unsigned char)~_BV(7) /* JTAG User ID Bit 7 */ -#define FUSE0_DEFAULT (0xFF) - -/* Fuse Byte 1 */ -#define FUSE_WDP0 (unsigned char)~_BV(0) /* Watchdog Timeout Period Bit 0 */ -#define FUSE_WDP1 (unsigned char)~_BV(1) /* Watchdog Timeout Period Bit 1 */ -#define FUSE_WDP2 (unsigned char)~_BV(2) /* Watchdog Timeout Period Bit 2 */ -#define FUSE_WDP3 (unsigned char)~_BV(3) /* Watchdog Timeout Period Bit 3 */ -#define FUSE_WDWP0 (unsigned char)~_BV(4) /* Watchdog Window Timeout Period Bit 0 */ -#define FUSE_WDWP1 (unsigned char)~_BV(5) /* Watchdog Window Timeout Period Bit 1 */ -#define FUSE_WDWP2 (unsigned char)~_BV(6) /* Watchdog Window Timeout Period Bit 2 */ -#define FUSE_WDWP3 (unsigned char)~_BV(7) /* Watchdog Window Timeout Period Bit 3 */ -#define FUSE1_DEFAULT (0xFF) - -/* Fuse Byte 2 */ -#define FUSE_BODPD0 (unsigned char)~_BV(0) /* BOD Operation in Power-Down Mode Bit 0 */ -#define FUSE_BODPD1 (unsigned char)~_BV(1) /* BOD Operation in Power-Down Mode Bit 1 */ -#define FUSE_TOSCSEL (unsigned char)~_BV(5) /* Timer Oscillator pin location */ -#define FUSE_BOOTRST (unsigned char)~_BV(6) /* Boot Loader Section Reset Vector */ -#define FUSE2_DEFAULT (0xFF) - -/* Fuse Byte 3 Reserved */ - -/* Fuse Byte 4 */ -#define FUSE_JTAGEN (unsigned char)~_BV(0) /* JTAG Interface Enable */ -#define FUSE_WDLOCK (unsigned char)~_BV(1) /* Watchdog Timer Lock */ -#define FUSE_SUT0 (unsigned char)~_BV(2) /* Start-up Time Bit 0 */ -#define FUSE_SUT1 (unsigned char)~_BV(3) /* Start-up Time Bit 1 */ -#define FUSE_RSTDISBL (unsigned char)~_BV(4) /* External Reset Disable */ -#define FUSE4_DEFAULT (0xFF) - -/* Fuse Byte 5 */ -#define FUSE_BODLVL0 (unsigned char)~_BV(0) /* Brownout Detection Voltage Level Bit 0 */ -#define FUSE_BODLVL1 (unsigned char)~_BV(1) /* Brownout Detection Voltage Level Bit 1 */ -#define FUSE_BODLVL2 (unsigned char)~_BV(2) /* Brownout Detection Voltage Level Bit 2 */ -#define FUSE_EESAVE (unsigned char)~_BV(3) /* Preserve EEPROM Through Chip Erase */ -#define FUSE_BODACT0 (unsigned char)~_BV(4) /* BOD Operation in Active Mode Bit 0 */ -#define FUSE_BODACT1 (unsigned char)~_BV(5) /* BOD Operation in Active Mode Bit 1 */ -#define FUSE5_DEFAULT (0xFF) - -/* ========== Lock Bits ========== */ -#define __LOCK_BITS_EXIST -#define __BOOT_LOCK_APPLICATION_TABLE_BITS_EXIST -#define __BOOT_LOCK_APPLICATION_BITS_EXIST -#define __BOOT_LOCK_BOOT_BITS_EXIST - -/* ========== Signature ========== */ -#define SIGNATURE_0 0x1E -#define SIGNATURE_1 0x98 -#define SIGNATURE_2 0x43 - -/* ========== Power Reduction Condition Definitions ========== */ - -/* PR.PRGEN */ -#define __AVR_HAVE_PRGEN (PR_USB_bm|PR_AES_bm|PR_EBI_bm|PR_RTC_bm|PR_EVSYS_bm|PR_DMA_bm) -#define __AVR_HAVE_PRGEN_USB -#define __AVR_HAVE_PRGEN_AES -#define __AVR_HAVE_PRGEN_EBI -#define __AVR_HAVE_PRGEN_RTC -#define __AVR_HAVE_PRGEN_EVSYS -#define __AVR_HAVE_PRGEN_DMA - -/* PR.PRPA */ -#define __AVR_HAVE_PRPA (PR_DAC_bm|PR_ADC_bm|PR_AC_bm) -#define __AVR_HAVE_PRPA_DAC -#define __AVR_HAVE_PRPA_ADC -#define __AVR_HAVE_PRPA_AC - -/* PR.PRPB */ -#define __AVR_HAVE_PRPB (PR_DAC_bm|PR_ADC_bm|PR_AC_bm) -#define __AVR_HAVE_PRPB_DAC -#define __AVR_HAVE_PRPB_ADC -#define __AVR_HAVE_PRPB_AC - -/* PR.PRPC */ -#define __AVR_HAVE_PRPC (PR_TWI_bm|PR_USART1_bm|PR_USART0_bm|PR_SPI_bm|PR_HIRES_bm|PR_TC1_bm|PR_TC0_bm) -#define __AVR_HAVE_PRPC_TWI -#define __AVR_HAVE_PRPC_USART1 -#define __AVR_HAVE_PRPC_USART0 -#define __AVR_HAVE_PRPC_SPI -#define __AVR_HAVE_PRPC_HIRES -#define __AVR_HAVE_PRPC_TC1 -#define __AVR_HAVE_PRPC_TC0 - -/* PR.PRPD */ -#define __AVR_HAVE_PRPD (PR_TWI_bm|PR_USART1_bm|PR_USART0_bm|PR_SPI_bm|PR_HIRES_bm|PR_TC1_bm|PR_TC0_bm) -#define __AVR_HAVE_PRPD_TWI -#define __AVR_HAVE_PRPD_USART1 -#define __AVR_HAVE_PRPD_USART0 -#define __AVR_HAVE_PRPD_SPI -#define __AVR_HAVE_PRPD_HIRES -#define __AVR_HAVE_PRPD_TC1 -#define __AVR_HAVE_PRPD_TC0 - -/* PR.PRPE */ -#define __AVR_HAVE_PRPE (PR_TWI_bm|PR_USART1_bm|PR_USART0_bm|PR_SPI_bm|PR_HIRES_bm|PR_TC1_bm|PR_TC0_bm) -#define __AVR_HAVE_PRPE_TWI -#define __AVR_HAVE_PRPE_USART1 -#define __AVR_HAVE_PRPE_USART0 -#define __AVR_HAVE_PRPE_SPI -#define __AVR_HAVE_PRPE_HIRES -#define __AVR_HAVE_PRPE_TC1 -#define __AVR_HAVE_PRPE_TC0 - -/* PR.PRPF */ -#define __AVR_HAVE_PRPF (PR_TWI_bm|PR_USART1_bm|PR_USART0_bm|PR_SPI_bm|PR_HIRES_bm|PR_TC1_bm|PR_TC0_bm) -#define __AVR_HAVE_PRPF_TWI -#define __AVR_HAVE_PRPF_USART1 -#define __AVR_HAVE_PRPF_USART0 -#define __AVR_HAVE_PRPF_SPI -#define __AVR_HAVE_PRPF_HIRES -#define __AVR_HAVE_PRPF_TC1 -#define __AVR_HAVE_PRPF_TC0 - - -#endif /* #ifdef _AVR_ATXMEGA256A3BU_H_INCLUDED */ - diff --git a/arduino/hardware/tools/avr/avr/include/avr/iox256a3u.h b/arduino/hardware/tools/avr/avr/include/avr/iox256a3u.h deleted file mode 100644 index c7ee9a7..0000000 --- a/arduino/hardware/tools/avr/avr/include/avr/iox256a3u.h +++ /dev/null @@ -1,7697 +0,0 @@ -/***************************************************************************** - * - * Copyright (C) 2015 Atmel Corporation - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * - * * Neither the name of the copyright holders nor the names of - * contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - ****************************************************************************/ - - -#ifndef _AVR_IO_H_ -# error "Include instead of this file." -#endif - -#ifndef _AVR_IOXXX_H_ -# define _AVR_IOXXX_H_ "iox256a3u.h" -#else -# error "Attempt to include more than one file." -#endif - -#ifndef _AVR_ATXMEGA256A3U_H_INCLUDED -#define _AVR_ATXMEGA256A3U_H_INCLUDED - -/* Ungrouped common registers */ -#define GPIOR0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ -#define GPIOR1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ -#define GPIOR2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ -#define GPIOR3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ -#define GPIOR4 _SFR_MEM8(0x0004) /* General Purpose IO Register 4 */ -#define GPIOR5 _SFR_MEM8(0x0005) /* General Purpose IO Register 5 */ -#define GPIOR6 _SFR_MEM8(0x0006) /* General Purpose IO Register 6 */ -#define GPIOR7 _SFR_MEM8(0x0007) /* General Purpose IO Register 7 */ -#define GPIOR8 _SFR_MEM8(0x0008) /* General Purpose IO Register 8 */ -#define GPIOR9 _SFR_MEM8(0x0009) /* General Purpose IO Register 9 */ -#define GPIORA _SFR_MEM8(0x000A) /* General Purpose IO Register 10 */ -#define GPIORB _SFR_MEM8(0x000B) /* General Purpose IO Register 11 */ -#define GPIORC _SFR_MEM8(0x000C) /* General Purpose IO Register 12 */ -#define GPIORD _SFR_MEM8(0x000D) /* General Purpose IO Register 13 */ -#define GPIORE _SFR_MEM8(0x000E) /* General Purpose IO Register 14 */ -#define GPIORF _SFR_MEM8(0x000F) /* General Purpose IO Register 15 */ - -/* Deprecated */ -#define GPIO0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ -#define GPIO1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ -#define GPIO2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ -#define GPIO3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ -#define GPIO4 _SFR_MEM8(0x0004) /* General Purpose IO Register 4 */ -#define GPIO5 _SFR_MEM8(0x0005) /* General Purpose IO Register 5 */ -#define GPIO6 _SFR_MEM8(0x0006) /* General Purpose IO Register 6 */ -#define GPIO7 _SFR_MEM8(0x0007) /* General Purpose IO Register 7 */ -#define GPIO8 _SFR_MEM8(0x0008) /* General Purpose IO Register 8 */ -#define GPIO9 _SFR_MEM8(0x0009) /* General Purpose IO Register 9 */ -#define GPIOA _SFR_MEM8(0x000A) /* General Purpose IO Register 10 */ -#define GPIOB _SFR_MEM8(0x000B) /* General Purpose IO Register 11 */ -#define GPIOC _SFR_MEM8(0x000C) /* General Purpose IO Register 12 */ -#define GPIOD _SFR_MEM8(0x000D) /* General Purpose IO Register 13 */ -#define GPIOE _SFR_MEM8(0x000E) /* General Purpose IO Register 14 */ -#define GPIOF _SFR_MEM8(0x000F) /* General Purpose IO Register 15 */ - -#define CCP _SFR_MEM8(0x0034) /* Configuration Change Protection */ -#define RAMPD _SFR_MEM8(0x0038) /* Ramp D */ -#define RAMPX _SFR_MEM8(0x0039) /* Ramp X */ -#define RAMPY _SFR_MEM8(0x003A) /* Ramp Y */ -#define RAMPZ _SFR_MEM8(0x003B) /* Ramp Z */ -#define EIND _SFR_MEM8(0x003C) /* Extended Indirect Jump */ -#define SPL _SFR_MEM8(0x003D) /* Stack Pointer Low */ -#define SPH _SFR_MEM8(0x003E) /* Stack Pointer High */ -#define SREG _SFR_MEM8(0x003F) /* Status Register */ - -/* C Language Only */ -#if !defined (__ASSEMBLER__) - -#include - -typedef volatile uint8_t register8_t; -typedef volatile uint16_t register16_t; -typedef volatile uint32_t register32_t; - - -#ifdef _WORDREGISTER -#undef _WORDREGISTER -#endif -#define _WORDREGISTER(regname) \ - __extension__ union \ - { \ - register16_t regname; \ - struct \ - { \ - register8_t regname ## L; \ - register8_t regname ## H; \ - }; \ - } - -#ifdef _DWORDREGISTER -#undef _DWORDREGISTER -#endif -#define _DWORDREGISTER(regname) \ - __extension__ union \ - { \ - register32_t regname; \ - struct \ - { \ - register8_t regname ## 0; \ - register8_t regname ## 1; \ - register8_t regname ## 2; \ - register8_t regname ## 3; \ - }; \ - } - - -/* -========================================================================== -IO Module Structures -========================================================================== -*/ - - -/* --------------------------------------------------------------------------- -VPORT - Virtual Ports --------------------------------------------------------------------------- -*/ - -/* Virtual Port */ -typedef struct VPORT_struct -{ - register8_t DIR; /* I/O Port Data Direction */ - register8_t OUT; /* I/O Port Output */ - register8_t IN; /* I/O Port Input */ - register8_t INTFLAGS; /* Interrupt Flag Register */ -} VPORT_t; - - -/* --------------------------------------------------------------------------- -XOCD - On-Chip Debug System --------------------------------------------------------------------------- -*/ - -/* On-Chip Debug System */ -typedef struct OCD_struct -{ - register8_t OCDR0; /* OCD Register 0 */ - register8_t OCDR1; /* OCD Register 1 */ -} OCD_t; - - -/* --------------------------------------------------------------------------- -CPU - CPU --------------------------------------------------------------------------- -*/ - -/* CCP signatures */ -typedef enum CCP_enum -{ - CCP_SPM_gc = (0x9D<<0), /* SPM Instruction Protection */ - CCP_IOREG_gc = (0xD8<<0), /* IO Register Protection */ -} CCP_t; - - -/* --------------------------------------------------------------------------- -CLK - Clock System --------------------------------------------------------------------------- -*/ - -/* Clock System */ -typedef struct CLK_struct -{ - register8_t CTRL; /* Control Register */ - register8_t PSCTRL; /* Prescaler Control Register */ - register8_t LOCK; /* Lock register */ - register8_t RTCCTRL; /* RTC Control Register */ - register8_t USBCTRL; /* USB Control Register */ -} CLK_t; - - -/* Power Reduction */ -typedef struct PR_struct -{ - register8_t PRGEN; /* General Power Reduction */ - register8_t PRPA; /* Power Reduction Port A */ - register8_t PRPB; /* Power Reduction Port B */ - register8_t PRPC; /* Power Reduction Port C */ - register8_t PRPD; /* Power Reduction Port D */ - register8_t PRPE; /* Power Reduction Port E */ - register8_t PRPF; /* Power Reduction Port F */ -} PR_t; - -/* System Clock Selection */ -typedef enum CLK_SCLKSEL_enum -{ - CLK_SCLKSEL_RC2M_gc = (0x00<<0), /* Internal 2 MHz RC Oscillator */ - CLK_SCLKSEL_RC32M_gc = (0x01<<0), /* Internal 32 MHz RC Oscillator */ - CLK_SCLKSEL_RC32K_gc = (0x02<<0), /* Internal 32.768 kHz RC Oscillator */ - CLK_SCLKSEL_XOSC_gc = (0x03<<0), /* External Crystal Oscillator or Clock */ - CLK_SCLKSEL_PLL_gc = (0x04<<0), /* Phase Locked Loop */ -} CLK_SCLKSEL_t; - -/* Prescaler A Division Factor */ -typedef enum CLK_PSADIV_enum -{ - CLK_PSADIV_1_gc = (0x00<<2), /* Divide by 1 */ - CLK_PSADIV_2_gc = (0x01<<2), /* Divide by 2 */ - CLK_PSADIV_4_gc = (0x03<<2), /* Divide by 4 */ - CLK_PSADIV_8_gc = (0x05<<2), /* Divide by 8 */ - CLK_PSADIV_16_gc = (0x07<<2), /* Divide by 16 */ - CLK_PSADIV_32_gc = (0x09<<2), /* Divide by 32 */ - CLK_PSADIV_64_gc = (0x0B<<2), /* Divide by 64 */ - CLK_PSADIV_128_gc = (0x0D<<2), /* Divide by 128 */ - CLK_PSADIV_256_gc = (0x0F<<2), /* Divide by 256 */ - CLK_PSADIV_512_gc = (0x11<<2), /* Divide by 512 */ -} CLK_PSADIV_t; - -/* Prescaler B and C Division Factor */ -typedef enum CLK_PSBCDIV_enum -{ - CLK_PSBCDIV_1_1_gc = (0x00<<0), /* Divide B by 1 and C by 1 */ - CLK_PSBCDIV_1_2_gc = (0x01<<0), /* Divide B by 1 and C by 2 */ - CLK_PSBCDIV_4_1_gc = (0x02<<0), /* Divide B by 4 and C by 1 */ - CLK_PSBCDIV_2_2_gc = (0x03<<0), /* Divide B by 2 and C by 2 */ -} CLK_PSBCDIV_t; - -/* RTC Clock Source */ -typedef enum CLK_RTCSRC_enum -{ - CLK_RTCSRC_ULP_gc = (0x00<<1), /* 1.024 kHz from internal 32kHz ULP */ - CLK_RTCSRC_TOSC_gc = (0x01<<1), /* 1.024 kHz from 32.768 kHz crystal oscillator on TOSC */ - CLK_RTCSRC_RCOSC_gc = (0x02<<1), /* 1.024 kHz from internal 32.768 kHz RC oscillator */ - CLK_RTCSRC_TOSC32_gc = (0x05<<1), /* 32.768 kHz from 32.768 kHz crystal oscillator on TOSC */ - CLK_RTCSRC_RCOSC32_gc = (0x06<<1), /* 32.768 kHz from internal 32.768 kHz RC oscillator */ - CLK_RTCSRC_EXTCLK_gc = (0x07<<1), /* External Clock from TOSC1 */ -} CLK_RTCSRC_t; - -/* USB Prescaler Division Factor */ -typedef enum CLK_USBPSDIV_enum -{ - CLK_USBPSDIV_1_gc = (0x00<<3), /* Divide by 1 */ - CLK_USBPSDIV_2_gc = (0x01<<3), /* Divide by 2 */ - CLK_USBPSDIV_4_gc = (0x02<<3), /* Divide by 4 */ - CLK_USBPSDIV_8_gc = (0x03<<3), /* Divide by 8 */ - CLK_USBPSDIV_16_gc = (0x04<<3), /* Divide by 16 */ - CLK_USBPSDIV_32_gc = (0x05<<3), /* Divide by 32 */ -} CLK_USBPSDIV_t; - -/* USB Clock Source */ -typedef enum CLK_USBSRC_enum -{ - CLK_USBSRC_PLL_gc = (0x00<<1), /* PLL */ - CLK_USBSRC_RC32M_gc = (0x01<<1), /* Internal 32 MHz RC Oscillator */ -} CLK_USBSRC_t; - - -/* --------------------------------------------------------------------------- -SLEEP - Sleep Controller --------------------------------------------------------------------------- -*/ - -/* Sleep Controller */ -typedef struct SLEEP_struct -{ - register8_t CTRL; /* Control Register */ -} SLEEP_t; - -/* Sleep Mode */ -typedef enum SLEEP_SMODE_enum -{ - SLEEP_SMODE_IDLE_gc = (0x00<<1), /* Idle mode */ - SLEEP_SMODE_PDOWN_gc = (0x02<<1), /* Power-down Mode */ - SLEEP_SMODE_PSAVE_gc = (0x03<<1), /* Power-save Mode */ - SLEEP_SMODE_STDBY_gc = (0x06<<1), /* Standby Mode */ - SLEEP_SMODE_ESTDBY_gc = (0x07<<1), /* Extended Standby Mode */ -} SLEEP_SMODE_t; - - - -#define SLEEP_MODE_IDLE (0x00<<1) -#define SLEEP_MODE_PWR_DOWN (0x02<<1) -#define SLEEP_MODE_PWR_SAVE (0x03<<1) -#define SLEEP_MODE_STANDBY (0x06<<1) -#define SLEEP_MODE_EXT_STANDBY (0x07<<1) -/* --------------------------------------------------------------------------- -OSC - Oscillator --------------------------------------------------------------------------- -*/ - -/* Oscillator */ -typedef struct OSC_struct -{ - register8_t CTRL; /* Control Register */ - register8_t STATUS; /* Status Register */ - register8_t XOSCCTRL; /* External Oscillator Control Register */ - register8_t XOSCFAIL; /* Oscillator Failure Detection Register */ - register8_t RC32KCAL; /* 32.768 kHz Internal Oscillator Calibration Register */ - register8_t PLLCTRL; /* PLL Control Register */ - register8_t DFLLCTRL; /* DFLL Control Register */ -} OSC_t; - -/* Oscillator Frequency Range */ -typedef enum OSC_FRQRANGE_enum -{ - OSC_FRQRANGE_04TO2_gc = (0x00<<6), /* 0.4 - 2 MHz */ - OSC_FRQRANGE_2TO9_gc = (0x01<<6), /* 2 - 9 MHz */ - OSC_FRQRANGE_9TO12_gc = (0x02<<6), /* 9 - 12 MHz */ - OSC_FRQRANGE_12TO16_gc = (0x03<<6), /* 12 - 16 MHz */ -} OSC_FRQRANGE_t; - -/* External Oscillator Selection and Startup Time */ -typedef enum OSC_XOSCSEL_enum -{ - OSC_XOSCSEL_EXTCLK_gc = (0x00<<0), /* External Clock - 6 CLK */ - OSC_XOSCSEL_32KHz_gc = (0x02<<0), /* 32.768 kHz TOSC - 32K CLK */ - OSC_XOSCSEL_XTAL_256CLK_gc = (0x03<<0), /* 0.4-16 MHz XTAL - 256 CLK */ - OSC_XOSCSEL_XTAL_1KCLK_gc = (0x07<<0), /* 0.4-16 MHz XTAL - 1K CLK */ - OSC_XOSCSEL_XTAL_16KCLK_gc = (0x0B<<0), /* 0.4-16 MHz XTAL - 16K CLK */ -} OSC_XOSCSEL_t; - -/* PLL Clock Source */ -typedef enum OSC_PLLSRC_enum -{ - OSC_PLLSRC_RC2M_gc = (0x00<<6), /* Internal 2 MHz RC Oscillator */ - OSC_PLLSRC_RC32M_gc = (0x02<<6), /* Internal 32 MHz RC Oscillator */ - OSC_PLLSRC_XOSC_gc = (0x03<<6), /* External Oscillator */ -} OSC_PLLSRC_t; - -/* 2 MHz DFLL Calibration Reference */ -typedef enum OSC_RC2MCREF_enum -{ - OSC_RC2MCREF_RC32K_gc = (0x00<<0), /* Internal 32.768 kHz RC Oscillator */ - OSC_RC2MCREF_XOSC32K_gc = (0x01<<0), /* External 32.768 kHz Crystal Oscillator */ -} OSC_RC2MCREF_t; - -/* 32 MHz DFLL Calibration Reference */ -typedef enum OSC_RC32MCREF_enum -{ - OSC_RC32MCREF_RC32K_gc = (0x00<<1), /* Internal 32.768 kHz RC Oscillator */ - OSC_RC32MCREF_XOSC32K_gc = (0x01<<1), /* External 32.768 kHz Crystal Oscillator */ - OSC_RC32MCREF_USBSOF_gc = (0x02<<1), /* USB Start of Frame */ -} OSC_RC32MCREF_t; - - -/* --------------------------------------------------------------------------- -DFLL - DFLL --------------------------------------------------------------------------- -*/ - -/* DFLL */ -typedef struct DFLL_struct -{ - register8_t CTRL; /* Control Register */ - register8_t reserved_0x01; - register8_t CALA; /* Calibration Register A */ - register8_t CALB; /* Calibration Register B */ - register8_t COMP0; /* Oscillator Compare Register 0 */ - register8_t COMP1; /* Oscillator Compare Register 1 */ - register8_t COMP2; /* Oscillator Compare Register 2 */ - register8_t reserved_0x07; -} DFLL_t; - - -/* --------------------------------------------------------------------------- -RST - Reset --------------------------------------------------------------------------- -*/ - -/* Reset */ -typedef struct RST_struct -{ - register8_t STATUS; /* Status Register */ - register8_t CTRL; /* Control Register */ -} RST_t; - - -/* --------------------------------------------------------------------------- -WDT - Watch-Dog Timer --------------------------------------------------------------------------- -*/ - -/* Watch-Dog Timer */ -typedef struct WDT_struct -{ - register8_t CTRL; /* Control */ - register8_t WINCTRL; /* Windowed Mode Control */ - register8_t STATUS; /* Status */ -} WDT_t; - -/* Period setting */ -typedef enum WDT_PER_enum -{ - WDT_PER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ - WDT_PER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ - WDT_PER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ - WDT_PER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ - WDT_PER_128CLK_gc = (0x04<<2), /* 128 cycles (0.128s @ 3.3V) */ - WDT_PER_256CLK_gc = (0x05<<2), /* 256 cycles (0.256s @ 3.3V) */ - WDT_PER_512CLK_gc = (0x06<<2), /* 512 cycles (0.512s @ 3.3V) */ - WDT_PER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ - WDT_PER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ - WDT_PER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ - WDT_PER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ -} WDT_PER_t; - -/* Closed window period */ -typedef enum WDT_WPER_enum -{ - WDT_WPER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ - WDT_WPER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ - WDT_WPER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ - WDT_WPER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ - WDT_WPER_128CLK_gc = (0x04<<2), /* 128 cycles (0.128s @ 3.3V) */ - WDT_WPER_256CLK_gc = (0x05<<2), /* 256 cycles (0.256s @ 3.3V) */ - WDT_WPER_512CLK_gc = (0x06<<2), /* 512 cycles (0.512s @ 3.3V) */ - WDT_WPER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ - WDT_WPER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ - WDT_WPER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ - WDT_WPER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ -} WDT_WPER_t; - - -/* --------------------------------------------------------------------------- -MCU - MCU Control --------------------------------------------------------------------------- -*/ - -/* MCU Control */ -typedef struct MCU_struct -{ - register8_t DEVID0; /* Device ID byte 0 */ - register8_t DEVID1; /* Device ID byte 1 */ - register8_t DEVID2; /* Device ID byte 2 */ - register8_t REVID; /* Revision ID */ - register8_t JTAGUID; /* JTAG User ID */ - register8_t reserved_0x05; - register8_t MCUCR; /* MCU Control */ - register8_t ANAINIT; /* Analog Startup Delay */ - register8_t EVSYSLOCK; /* Event System Lock */ - register8_t AWEXLOCK; /* AWEX Lock */ - register8_t reserved_0x0A; - register8_t reserved_0x0B; -} MCU_t; - - -/* --------------------------------------------------------------------------- -PMIC - Programmable Multi-level Interrupt Controller --------------------------------------------------------------------------- -*/ - -/* Programmable Multi-level Interrupt Controller */ -typedef struct PMIC_struct -{ - register8_t STATUS; /* Status Register */ - register8_t INTPRI; /* Interrupt Priority */ - register8_t CTRL; /* Control Register */ - register8_t reserved_0x03; - register8_t reserved_0x04; - register8_t reserved_0x05; - register8_t reserved_0x06; - register8_t reserved_0x07; - register8_t reserved_0x08; - register8_t reserved_0x09; - register8_t reserved_0x0A; - register8_t reserved_0x0B; - register8_t reserved_0x0C; - register8_t reserved_0x0D; - register8_t reserved_0x0E; - register8_t reserved_0x0F; -} PMIC_t; - - -/* --------------------------------------------------------------------------- -PORTCFG - Port Configuration --------------------------------------------------------------------------- -*/ - -/* I/O port Configuration */ -typedef struct PORTCFG_struct -{ - register8_t MPCMASK; /* Multi-pin Configuration Mask */ - register8_t reserved_0x01; - register8_t VPCTRLA; /* Virtual Port Control Register A */ - register8_t VPCTRLB; /* Virtual Port Control Register B */ - register8_t CLKEVOUT; /* Clock and Event Out Register */ - register8_t EBIOUT; /* EBI Output register */ - register8_t EVOUTSEL; /* Event Output Select */ -} PORTCFG_t; - -/* Virtual Port Mapping */ -typedef enum PORTCFG_VP02MAP_enum -{ - PORTCFG_VP02MAP_PORTA_gc = (0x00<<0), /* Mapped To PORTA */ - PORTCFG_VP02MAP_PORTB_gc = (0x01<<0), /* Mapped To PORTB */ - PORTCFG_VP02MAP_PORTC_gc = (0x02<<0), /* Mapped To PORTC */ - PORTCFG_VP02MAP_PORTD_gc = (0x03<<0), /* Mapped To PORTD */ - PORTCFG_VP02MAP_PORTE_gc = (0x04<<0), /* Mapped To PORTE */ - PORTCFG_VP02MAP_PORTF_gc = (0x05<<0), /* Mapped To PORTF */ - PORTCFG_VP02MAP_PORTG_gc = (0x06<<0), /* Mapped To PORTG */ - PORTCFG_VP02MAP_PORTH_gc = (0x07<<0), /* Mapped To PORTH */ - PORTCFG_VP02MAP_PORTJ_gc = (0x08<<0), /* Mapped To PORTJ */ - PORTCFG_VP02MAP_PORTK_gc = (0x09<<0), /* Mapped To PORTK */ - PORTCFG_VP02MAP_PORTL_gc = (0x0A<<0), /* Mapped To PORTL */ - PORTCFG_VP02MAP_PORTM_gc = (0x0B<<0), /* Mapped To PORTM */ - PORTCFG_VP02MAP_PORTN_gc = (0x0C<<0), /* Mapped To PORTN */ - PORTCFG_VP02MAP_PORTP_gc = (0x0D<<0), /* Mapped To PORTP */ - PORTCFG_VP02MAP_PORTQ_gc = (0x0E<<0), /* Mapped To PORTQ */ - PORTCFG_VP02MAP_PORTR_gc = (0x0F<<0), /* Mapped To PORTR */ -} PORTCFG_VP02MAP_t; - -/* Virtual Port Mapping */ -typedef enum PORTCFG_VP13MAP_enum -{ - PORTCFG_VP13MAP_PORTA_gc = (0x00<<4), /* Mapped To PORTA */ - PORTCFG_VP13MAP_PORTB_gc = (0x01<<4), /* Mapped To PORTB */ - PORTCFG_VP13MAP_PORTC_gc = (0x02<<4), /* Mapped To PORTC */ - PORTCFG_VP13MAP_PORTD_gc = (0x03<<4), /* Mapped To PORTD */ - PORTCFG_VP13MAP_PORTE_gc = (0x04<<4), /* Mapped To PORTE */ - PORTCFG_VP13MAP_PORTF_gc = (0x05<<4), /* Mapped To PORTF */ - PORTCFG_VP13MAP_PORTG_gc = (0x06<<4), /* Mapped To PORTG */ - PORTCFG_VP13MAP_PORTH_gc = (0x07<<4), /* Mapped To PORTH */ - PORTCFG_VP13MAP_PORTJ_gc = (0x08<<4), /* Mapped To PORTJ */ - PORTCFG_VP13MAP_PORTK_gc = (0x09<<4), /* Mapped To PORTK */ - PORTCFG_VP13MAP_PORTL_gc = (0x0A<<4), /* Mapped To PORTL */ - PORTCFG_VP13MAP_PORTM_gc = (0x0B<<4), /* Mapped To PORTM */ - PORTCFG_VP13MAP_PORTN_gc = (0x0C<<4), /* Mapped To PORTN */ - PORTCFG_VP13MAP_PORTP_gc = (0x0D<<4), /* Mapped To PORTP */ - PORTCFG_VP13MAP_PORTQ_gc = (0x0E<<4), /* Mapped To PORTQ */ - PORTCFG_VP13MAP_PORTR_gc = (0x0F<<4), /* Mapped To PORTR */ -} PORTCFG_VP13MAP_t; - -/* System Clock Output Port */ -typedef enum PORTCFG_CLKOUT_enum -{ - PORTCFG_CLKOUT_OFF_gc = (0x00<<0), /* System Clock Output Disabled */ - PORTCFG_CLKOUT_PC7_gc = (0x01<<0), /* System Clock Output on Port C pin 7 */ - PORTCFG_CLKOUT_PD7_gc = (0x02<<0), /* System Clock Output on Port D pin 7 */ - PORTCFG_CLKOUT_PE7_gc = (0x03<<0), /* System Clock Output on Port E pin 7 */ -} PORTCFG_CLKOUT_t; - -/* Peripheral Clock Output Select */ -typedef enum PORTCFG_CLKOUTSEL_enum -{ - PORTCFG_CLKOUTSEL_CLK1X_gc = (0x00<<2), /* 1x Peripheral Clock Output to pin */ - PORTCFG_CLKOUTSEL_CLK2X_gc = (0x01<<2), /* 2x Peripheral Clock Output to pin */ - PORTCFG_CLKOUTSEL_CLK4X_gc = (0x02<<2), /* 4x Peripheral Clock Output to pin */ -} PORTCFG_CLKOUTSEL_t; - -/* Event Output Port */ -typedef enum PORTCFG_EVOUT_enum -{ - PORTCFG_EVOUT_OFF_gc = (0x00<<4), /* Event Output Disabled */ - PORTCFG_EVOUT_PC7_gc = (0x01<<4), /* Event Channel 7 Output on Port C pin 7 */ - PORTCFG_EVOUT_PD7_gc = (0x02<<4), /* Event Channel 7 Output on Port D pin 7 */ - PORTCFG_EVOUT_PE7_gc = (0x03<<4), /* Event Channel 7 Output on Port E pin 7 */ -} PORTCFG_EVOUT_t; - -/* Clock and Event Output Port */ -typedef enum PORTCFG_CLKEVPIN_enum -{ - PORTCFG_CLKEVPIN_PIN7_gc = (0x00<<7), /* Clock and Event Ouput on PIN 7 */ - PORTCFG_CLKEVPIN_PIN4_gc = (0x01<<7), /* Clock and Event Ouput on PIN 4 */ -} PORTCFG_CLKEVPIN_t; - -/* EBI Address Output Port */ -typedef enum PORTCFG_EBIADROUT_enum -{ - PORTCFG_EBIADROUT_PF_gc = (0x00<<2), /* EBI port 3 address output on PORTF pins 0 to 7 */ - PORTCFG_EBIADROUT_PE_gc = (0x01<<2), /* EBI port 3 address output on PORTE pins 0 to 7 */ - PORTCFG_EBIADROUT_PFH_gc = (0x02<<2), /* EBI port 3 address output on PORTF pins 4 to 7 */ - PORTCFG_EBIADROUT_PEH_gc = (0x03<<2), /* EBI port 3 address output on PORTE pins 4 to 7 */ -} PORTCFG_EBIADROUT_t; - -/* EBI Chip Select Output Port */ -typedef enum PORTCFG_EBICSOUT_enum -{ - PORTCFG_EBICSOUT_PH_gc = (0x00<<0), /* EBI chip select output to PORTH pin 4 to 7 */ - PORTCFG_EBICSOUT_PL_gc = (0x01<<0), /* EBI chip select output to PORTL pin 4 to 7 */ - PORTCFG_EBICSOUT_PF_gc = (0x02<<0), /* EBI chip select output to PORTF pin 4 to 7 */ - PORTCFG_EBICSOUT_PE_gc = (0x03<<0), /* EBI chip select output to PORTE pin 4 to 7 */ -} PORTCFG_EBICSOUT_t; - -/* Event Output Select */ -typedef enum PORTCFG_EVOUTSEL_enum -{ - PORTCFG_EVOUTSEL_0_gc = (0x00<<0), /* Event Channel 0 output to pin */ - PORTCFG_EVOUTSEL_1_gc = (0x01<<0), /* Event Channel 1 output to pin */ - PORTCFG_EVOUTSEL_2_gc = (0x02<<0), /* Event Channel 2 output to pin */ - PORTCFG_EVOUTSEL_3_gc = (0x03<<0), /* Event Channel 3 output to pin */ - PORTCFG_EVOUTSEL_4_gc = (0x04<<0), /* Event Channel 4 output to pin */ - PORTCFG_EVOUTSEL_5_gc = (0x05<<0), /* Event Channel 5 output to pin */ - PORTCFG_EVOUTSEL_6_gc = (0x06<<0), /* Event Channel 6 output to pin */ - PORTCFG_EVOUTSEL_7_gc = (0x07<<0), /* Event Channel 7 output to pin */ -} PORTCFG_EVOUTSEL_t; - - -/* --------------------------------------------------------------------------- -AES - AES Module --------------------------------------------------------------------------- -*/ - -/* AES Module */ -typedef struct AES_struct -{ - register8_t CTRL; /* AES Control Register */ - register8_t STATUS; /* AES Status Register */ - register8_t STATE; /* AES State Register */ - register8_t KEY; /* AES Key Register */ - register8_t INTCTRL; /* AES Interrupt Control Register */ -} AES_t; - -/* Interrupt level */ -typedef enum AES_INTLVL_enum -{ - AES_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - AES_INTLVL_LO_gc = (0x01<<0), /* Low Level */ - AES_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ - AES_INTLVL_HI_gc = (0x03<<0), /* High Level */ -} AES_INTLVL_t; - - -/* --------------------------------------------------------------------------- -CRC - Cyclic Redundancy Checker --------------------------------------------------------------------------- -*/ - -/* Cyclic Redundancy Checker */ -typedef struct CRC_struct -{ - register8_t CTRL; /* Control Register */ - register8_t STATUS; /* Status Register */ - register8_t reserved_0x02; - register8_t DATAIN; /* Data Input */ - register8_t CHECKSUM0; /* Checksum byte 0 */ - register8_t CHECKSUM1; /* Checksum byte 1 */ - register8_t CHECKSUM2; /* Checksum byte 2 */ - register8_t CHECKSUM3; /* Checksum byte 3 */ -} CRC_t; - -/* Reset */ -typedef enum CRC_RESET_enum -{ - CRC_RESET_NO_gc = (0x00<<6), /* No Reset */ - CRC_RESET_RESET0_gc = (0x02<<6), /* Reset CRC with CHECKSUM to all zeros */ - CRC_RESET_RESET1_gc = (0x03<<6), /* Reset CRC with CHECKSUM to all ones */ -} CRC_RESET_t; - -/* Input Source */ -typedef enum CRC_SOURCE_enum -{ - CRC_SOURCE_DISABLE_gc = (0x00<<0), /* Disabled */ - CRC_SOURCE_IO_gc = (0x01<<0), /* I/O Interface */ - CRC_SOURCE_FLASH_gc = (0x02<<0), /* Flash */ - CRC_SOURCE_DMAC0_gc = (0x04<<0), /* DMAC Channel 0 */ - CRC_SOURCE_DMAC1_gc = (0x05<<0), /* DMAC Channel 1 */ - CRC_SOURCE_DMAC2_gc = (0x06<<0), /* DMAC Channel 2 */ - CRC_SOURCE_DMAC3_gc = (0x07<<0), /* DMAC Channel 3 */ -} CRC_SOURCE_t; - - -/* --------------------------------------------------------------------------- -DMA - DMA Controller --------------------------------------------------------------------------- -*/ - -/* DMA Channel */ -typedef struct DMA_CH_struct -{ - register8_t CTRLA; /* Channel Control */ - register8_t CTRLB; /* Channel Control */ - register8_t ADDRCTRL; /* Address Control */ - register8_t TRIGSRC; /* Channel Trigger Source */ - _WORDREGISTER(TRFCNT); /* Channel Block Transfer Count */ - register8_t REPCNT; /* Channel Repeat Count */ - register8_t reserved_0x07; - register8_t SRCADDR0; /* Channel Source Address 0 */ - register8_t SRCADDR1; /* Channel Source Address 1 */ - register8_t SRCADDR2; /* Channel Source Address 2 */ - register8_t reserved_0x0B; - register8_t DESTADDR0; /* Channel Destination Address 0 */ - register8_t DESTADDR1; /* Channel Destination Address 1 */ - register8_t DESTADDR2; /* Channel Destination Address 2 */ - register8_t reserved_0x0F; -} DMA_CH_t; - - -/* DMA Controller */ -typedef struct DMA_struct -{ - register8_t CTRL; /* Control */ - register8_t reserved_0x01; - register8_t reserved_0x02; - register8_t INTFLAGS; /* Transfer Interrupt Status */ - register8_t STATUS; /* Status */ - register8_t reserved_0x05; - _WORDREGISTER(TEMP); /* Temporary Register For 16/24-bit Access */ - register8_t reserved_0x08; - register8_t reserved_0x09; - register8_t reserved_0x0A; - register8_t reserved_0x0B; - register8_t reserved_0x0C; - register8_t reserved_0x0D; - register8_t reserved_0x0E; - register8_t reserved_0x0F; - DMA_CH_t CH0; /* DMA Channel 0 */ - DMA_CH_t CH1; /* DMA Channel 1 */ - DMA_CH_t CH2; /* DMA Channel 2 */ - DMA_CH_t CH3; /* DMA Channel 3 */ -} DMA_t; - -/* Burst mode */ -typedef enum DMA_CH_BURSTLEN_enum -{ - DMA_CH_BURSTLEN_1BYTE_gc = (0x00<<0), /* 1-byte burst mode */ - DMA_CH_BURSTLEN_2BYTE_gc = (0x01<<0), /* 2-byte burst mode */ - DMA_CH_BURSTLEN_4BYTE_gc = (0x02<<0), /* 4-byte burst mode */ - DMA_CH_BURSTLEN_8BYTE_gc = (0x03<<0), /* 8-byte burst mode */ -} DMA_CH_BURSTLEN_t; - -/* Source address reload mode */ -typedef enum DMA_CH_SRCRELOAD_enum -{ - DMA_CH_SRCRELOAD_NONE_gc = (0x00<<6), /* No reload */ - DMA_CH_SRCRELOAD_BLOCK_gc = (0x01<<6), /* Reload at end of block */ - DMA_CH_SRCRELOAD_BURST_gc = (0x02<<6), /* Reload at end of burst */ - DMA_CH_SRCRELOAD_TRANSACTION_gc = (0x03<<6), /* Reload at end of transaction */ -} DMA_CH_SRCRELOAD_t; - -/* Source addressing mode */ -typedef enum DMA_CH_SRCDIR_enum -{ - DMA_CH_SRCDIR_FIXED_gc = (0x00<<4), /* Fixed */ - DMA_CH_SRCDIR_INC_gc = (0x01<<4), /* Increment */ - DMA_CH_SRCDIR_DEC_gc = (0x02<<4), /* Decrement */ -} DMA_CH_SRCDIR_t; - -/* Destination adress reload mode */ -typedef enum DMA_CH_DESTRELOAD_enum -{ - DMA_CH_DESTRELOAD_NONE_gc = (0x00<<2), /* No reload */ - DMA_CH_DESTRELOAD_BLOCK_gc = (0x01<<2), /* Reload at end of block */ - DMA_CH_DESTRELOAD_BURST_gc = (0x02<<2), /* Reload at end of burst */ - DMA_CH_DESTRELOAD_TRANSACTION_gc = (0x03<<2), /* Reload at end of transaction */ -} DMA_CH_DESTRELOAD_t; - -/* Destination adressing mode */ -typedef enum DMA_CH_DESTDIR_enum -{ - DMA_CH_DESTDIR_FIXED_gc = (0x00<<0), /* Fixed */ - DMA_CH_DESTDIR_INC_gc = (0x01<<0), /* Increment */ - DMA_CH_DESTDIR_DEC_gc = (0x02<<0), /* Decrement */ -} DMA_CH_DESTDIR_t; - -/* Transfer trigger source */ -typedef enum DMA_CH_TRIGSRC_enum -{ - DMA_CH_TRIGSRC_OFF_gc = (0x00<<0), /* Off software triggers only */ - DMA_CH_TRIGSRC_EVSYS_CH0_gc = (0x01<<0), /* Event System Channel 0 */ - DMA_CH_TRIGSRC_EVSYS_CH1_gc = (0x02<<0), /* Event System Channel 1 */ - DMA_CH_TRIGSRC_EVSYS_CH2_gc = (0x03<<0), /* Event System Channel 2 */ - DMA_CH_TRIGSRC_ADCA_CH0_gc = (0x10<<0), /* ADCA Channel 0 */ - DMA_CH_TRIGSRC_ADCA_CH1_gc = (0x11<<0), /* ADCA Channel 1 */ - DMA_CH_TRIGSRC_ADCA_CH2_gc = (0x12<<0), /* ADCA Channel 2 */ - DMA_CH_TRIGSRC_ADCA_CH3_gc = (0x13<<0), /* ADCA Channel 3 */ - DMA_CH_TRIGSRC_ADCA_CH4_gc = (0x14<<0), /* ADCA Channel 0,1,2,3 combined */ - DMA_CH_TRIGSRC_DACA_CH0_gc = (0x15<<0), /* DACA Channel 0 */ - DMA_CH_TRIGSRC_DACA_CH1_gc = (0x16<<0), /* DACA Channel 1 */ - DMA_CH_TRIGSRC_ADCB_CH0_gc = (0x20<<0), /* ADCB Channel 0 */ - DMA_CH_TRIGSRC_ADCB_CH1_gc = (0x21<<0), /* ADCB Channel 1 */ - DMA_CH_TRIGSRC_ADCB_CH2_gc = (0x22<<0), /* ADCB Channel 2 */ - DMA_CH_TRIGSRC_ADCB_CH3_gc = (0x23<<0), /* ADCB Channel 3 */ - DMA_CH_TRIGSRC_ADCB_CH4_gc = (0x24<<0), /* ADCB Channel 0,1,2,3 combined */ - DMA_CH_TRIGSRC_DACB_CH0_gc = (0x25<<0), /* DACB Channel 0 */ - DMA_CH_TRIGSRC_DACB_CH1_gc = (0x26<<0), /* DACB Channel 1 */ - DMA_CH_TRIGSRC_TCC0_OVF_gc = (0x40<<0), /* Timer/Counter C0 Overflow */ - DMA_CH_TRIGSRC_TCC0_ERR_gc = (0x41<<0), /* Timer/Counter C0 Error */ - DMA_CH_TRIGSRC_TCC0_CCA_gc = (0x42<<0), /* Timer/Counter C0 Compare or Capture A */ - DMA_CH_TRIGSRC_TCC0_CCB_gc = (0x43<<0), /* Timer/Counter C0 Compare or Capture B */ - DMA_CH_TRIGSRC_TCC0_CCC_gc = (0x44<<0), /* Timer/Counter C0 Compare or Capture C */ - DMA_CH_TRIGSRC_TCC0_CCD_gc = (0x45<<0), /* Timer/Counter C0 Compare or Capture D */ - DMA_CH_TRIGSRC_TCC1_OVF_gc = (0x46<<0), /* Timer/Counter C1 Overflow */ - DMA_CH_TRIGSRC_TCC1_ERR_gc = (0x47<<0), /* Timer/Counter C1 Error */ - DMA_CH_TRIGSRC_TCC1_CCA_gc = (0x48<<0), /* Timer/Counter C1 Compare or Capture A */ - DMA_CH_TRIGSRC_TCC1_CCB_gc = (0x49<<0), /* Timer/Counter C1 Compare or Capture B */ - DMA_CH_TRIGSRC_SPIC_gc = (0x4A<<0), /* SPI C Transfer Complete */ - DMA_CH_TRIGSRC_USARTC0_RXC_gc = (0x4B<<0), /* USART C0 Receive Complete */ - DMA_CH_TRIGSRC_USARTC0_DRE_gc = (0x4C<<0), /* USART C0 Data Register Empty */ - DMA_CH_TRIGSRC_USARTC1_RXC_gc = (0x4E<<0), /* USART C1 Receive Complete */ - DMA_CH_TRIGSRC_USARTC1_DRE_gc = (0x4F<<0), /* USART C1 Data Register Empty */ - DMA_CH_TRIGSRC_TCD0_OVF_gc = (0x60<<0), /* Timer/Counter D0 Overflow */ - DMA_CH_TRIGSRC_TCD0_ERR_gc = (0x61<<0), /* Timer/Counter D0 Error */ - DMA_CH_TRIGSRC_TCD0_CCA_gc = (0x62<<0), /* Timer/Counter D0 Compare or Capture A */ - DMA_CH_TRIGSRC_TCD0_CCB_gc = (0x63<<0), /* Timer/Counter D0 Compare or Capture B */ - DMA_CH_TRIGSRC_TCD0_CCC_gc = (0x64<<0), /* Timer/Counter D0 Compare or Capture C */ - DMA_CH_TRIGSRC_TCD0_CCD_gc = (0x65<<0), /* Timer/Counter D0 Compare or Capture D */ - DMA_CH_TRIGSRC_TCD1_OVF_gc = (0x66<<0), /* Timer/Counter D1 Overflow */ - DMA_CH_TRIGSRC_TCD1_ERR_gc = (0x67<<0), /* Timer/Counter D1 Error */ - DMA_CH_TRIGSRC_TCD1_CCA_gc = (0x68<<0), /* Timer/Counter D1 Compare or Capture A */ - DMA_CH_TRIGSRC_TCD1_CCB_gc = (0x69<<0), /* Timer/Counter D1 Compare or Capture B */ - DMA_CH_TRIGSRC_SPID_gc = (0x6A<<0), /* SPI D Transfer Complete */ - DMA_CH_TRIGSRC_USARTD0_RXC_gc = (0x6B<<0), /* USART D0 Receive Complete */ - DMA_CH_TRIGSRC_USARTD0_DRE_gc = (0x6C<<0), /* USART D0 Data Register Empty */ - DMA_CH_TRIGSRC_USARTD1_RXC_gc = (0x6E<<0), /* USART D1 Receive Complete */ - DMA_CH_TRIGSRC_USARTD1_DRE_gc = (0x6F<<0), /* USART D1 Data Register Empty */ - DMA_CH_TRIGSRC_TCE0_OVF_gc = (0x80<<0), /* Timer/Counter E0 Overflow */ - DMA_CH_TRIGSRC_TCE0_ERR_gc = (0x81<<0), /* Timer/Counter E0 Error */ - DMA_CH_TRIGSRC_TCE0_CCA_gc = (0x82<<0), /* Timer/Counter E0 Compare or Capture A */ - DMA_CH_TRIGSRC_TCE0_CCB_gc = (0x83<<0), /* Timer/Counter E0 Compare or Capture B */ - DMA_CH_TRIGSRC_TCE0_CCC_gc = (0x84<<0), /* Timer/Counter E0 Compare or Capture C */ - DMA_CH_TRIGSRC_TCE0_CCD_gc = (0x85<<0), /* Timer/Counter E0 Compare or Capture D */ - DMA_CH_TRIGSRC_TCE1_OVF_gc = (0x86<<0), /* Timer/Counter E1 Overflow */ - DMA_CH_TRIGSRC_TCE1_ERR_gc = (0x87<<0), /* Timer/Counter E1 Error */ - DMA_CH_TRIGSRC_TCE1_CCA_gc = (0x88<<0), /* Timer/Counter E1 Compare or Capture A */ - DMA_CH_TRIGSRC_TCE1_CCB_gc = (0x89<<0), /* Timer/Counter E1 Compare or Capture B */ - DMA_CH_TRIGSRC_SPIE_gc = (0x8A<<0), /* SPI E Transfer Complete */ - DMA_CH_TRIGSRC_USARTE0_RXC_gc = (0x8B<<0), /* USART E0 Receive Complete */ - DMA_CH_TRIGSRC_USARTE0_DRE_gc = (0x8C<<0), /* USART E0 Data Register Empty */ - DMA_CH_TRIGSRC_USARTE1_RXC_gc = (0x8E<<0), /* USART E1 Receive Complete */ - DMA_CH_TRIGSRC_USARTE1_DRE_gc = (0x8F<<0), /* USART E1 Data Register Empty */ - DMA_CH_TRIGSRC_TCF0_OVF_gc = (0xA0<<0), /* Timer/Counter F0 Overflow */ - DMA_CH_TRIGSRC_TCF0_ERR_gc = (0xA1<<0), /* Timer/Counter F0 Error */ - DMA_CH_TRIGSRC_TCF0_CCA_gc = (0xA2<<0), /* Timer/Counter F0 Compare or Capture A */ - DMA_CH_TRIGSRC_TCF0_CCB_gc = (0xA3<<0), /* Timer/Counter F0 Compare or Capture B */ - DMA_CH_TRIGSRC_TCF0_CCC_gc = (0xA4<<0), /* Timer/Counter F0 Compare or Capture C */ - DMA_CH_TRIGSRC_TCF0_CCD_gc = (0xA5<<0), /* Timer/Counter F0 Compare or Capture D */ - DMA_CH_TRIGSRC_TCF1_OVF_gc = (0xA6<<0), /* Timer/Counter F1 Overflow */ - DMA_CH_TRIGSRC_TCF1_ERR_gc = (0xA7<<0), /* Timer/Counter F1 Error */ - DMA_CH_TRIGSRC_TCF1_CCA_gc = (0xA8<<0), /* Timer/Counter F1 Compare or Capture A */ - DMA_CH_TRIGSRC_TCF1_CCB_gc = (0xA9<<0), /* Timer/Counter F1 Compare or Capture B */ - DMA_CH_TRIGSRC_SPIF_gc = (0xAA<<0), /* SPI F Transfer Complete */ - DMA_CH_TRIGSRC_USARTF0_RXC_gc = (0xAB<<0), /* USART F0 Receive Complete */ - DMA_CH_TRIGSRC_USARTF0_DRE_gc = (0xAC<<0), /* USART F0 Data Register Empty */ - DMA_CH_TRIGSRC_USARTF1_RXC_gc = (0xAE<<0), /* USART F1 Receive Complete */ - DMA_CH_TRIGSRC_USARTF1_DRE_gc = (0xAF<<0), /* USART F1 Data Register Empty */ -} DMA_CH_TRIGSRC_t; - -/* Double buffering mode */ -typedef enum DMA_DBUFMODE_enum -{ - DMA_DBUFMODE_DISABLED_gc = (0x00<<2), /* Double buffering disabled */ - DMA_DBUFMODE_CH01_gc = (0x01<<2), /* Double buffering enabled on channel 0/1 */ - DMA_DBUFMODE_CH23_gc = (0x02<<2), /* Double buffering enabled on channel 2/3 */ - DMA_DBUFMODE_CH01CH23_gc = (0x03<<2), /* Double buffering enabled on ch. 0/1 and ch. 2/3 */ -} DMA_DBUFMODE_t; - -/* Priority mode */ -typedef enum DMA_PRIMODE_enum -{ - DMA_PRIMODE_RR0123_gc = (0x00<<0), /* Round Robin */ - DMA_PRIMODE_CH0RR123_gc = (0x01<<0), /* Channel 0 > Round Robin on channel 1/2/3 */ - DMA_PRIMODE_CH01RR23_gc = (0x02<<0), /* Channel 0 > channel 1 > Round Robin on channel 2/3 */ - DMA_PRIMODE_CH0123_gc = (0x03<<0), /* Channel 0 > channel 1 > channel 2 > channel 3 */ -} DMA_PRIMODE_t; - -/* Interrupt level */ -typedef enum DMA_CH_ERRINTLVL_enum -{ - DMA_CH_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ - DMA_CH_ERRINTLVL_LO_gc = (0x01<<2), /* Low level */ - DMA_CH_ERRINTLVL_MED_gc = (0x02<<2), /* Medium level */ - DMA_CH_ERRINTLVL_HI_gc = (0x03<<2), /* High level */ -} DMA_CH_ERRINTLVL_t; - -/* Interrupt level */ -typedef enum DMA_CH_TRNINTLVL_enum -{ - DMA_CH_TRNINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ - DMA_CH_TRNINTLVL_LO_gc = (0x01<<0), /* Low level */ - DMA_CH_TRNINTLVL_MED_gc = (0x02<<0), /* Medium level */ - DMA_CH_TRNINTLVL_HI_gc = (0x03<<0), /* High level */ -} DMA_CH_TRNINTLVL_t; - - -/* --------------------------------------------------------------------------- -EVSYS - Event System --------------------------------------------------------------------------- -*/ - -/* Event System */ -typedef struct EVSYS_struct -{ - register8_t CH0MUX; /* Event Channel 0 Multiplexer */ - register8_t CH1MUX; /* Event Channel 1 Multiplexer */ - register8_t CH2MUX; /* Event Channel 2 Multiplexer */ - register8_t CH3MUX; /* Event Channel 3 Multiplexer */ - register8_t CH4MUX; /* Event Channel 4 Multiplexer */ - register8_t CH5MUX; /* Event Channel 5 Multiplexer */ - register8_t CH6MUX; /* Event Channel 6 Multiplexer */ - register8_t CH7MUX; /* Event Channel 7 Multiplexer */ - register8_t CH0CTRL; /* Channel 0 Control Register */ - register8_t CH1CTRL; /* Channel 1 Control Register */ - register8_t CH2CTRL; /* Channel 2 Control Register */ - register8_t CH3CTRL; /* Channel 3 Control Register */ - register8_t CH4CTRL; /* Channel 4 Control Register */ - register8_t CH5CTRL; /* Channel 5 Control Register */ - register8_t CH6CTRL; /* Channel 6 Control Register */ - register8_t CH7CTRL; /* Channel 7 Control Register */ - register8_t STROBE; /* Event Strobe */ - register8_t DATA; /* Event Data */ -} EVSYS_t; - -/* Quadrature Decoder Index Recognition Mode */ -typedef enum EVSYS_QDIRM_enum -{ - EVSYS_QDIRM_00_gc = (0x00<<5), /* QDPH0 = 0, QDPH90 = 0 */ - EVSYS_QDIRM_01_gc = (0x01<<5), /* QDPH0 = 0, QDPH90 = 1 */ - EVSYS_QDIRM_10_gc = (0x02<<5), /* QDPH0 = 1, QDPH90 = 0 */ - EVSYS_QDIRM_11_gc = (0x03<<5), /* QDPH0 = 1, QDPH90 = 1 */ -} EVSYS_QDIRM_t; - -/* Digital filter coefficient */ -typedef enum EVSYS_DIGFILT_enum -{ - EVSYS_DIGFILT_1SAMPLE_gc = (0x00<<0), /* 1 SAMPLE */ - EVSYS_DIGFILT_2SAMPLES_gc = (0x01<<0), /* 2 SAMPLES */ - EVSYS_DIGFILT_3SAMPLES_gc = (0x02<<0), /* 3 SAMPLES */ - EVSYS_DIGFILT_4SAMPLES_gc = (0x03<<0), /* 4 SAMPLES */ - EVSYS_DIGFILT_5SAMPLES_gc = (0x04<<0), /* 5 SAMPLES */ - EVSYS_DIGFILT_6SAMPLES_gc = (0x05<<0), /* 6 SAMPLES */ - EVSYS_DIGFILT_7SAMPLES_gc = (0x06<<0), /* 7 SAMPLES */ - EVSYS_DIGFILT_8SAMPLES_gc = (0x07<<0), /* 8 SAMPLES */ -} EVSYS_DIGFILT_t; - -/* Event Channel multiplexer input selection */ -typedef enum EVSYS_CHMUX_enum -{ - EVSYS_CHMUX_OFF_gc = (0x00<<0), /* Off */ - EVSYS_CHMUX_RTC_OVF_gc = (0x08<<0), /* RTC Overflow */ - EVSYS_CHMUX_RTC_CMP_gc = (0x09<<0), /* RTC Compare Match */ - EVSYS_CHMUX_USB_gc = (0x0A<<0), /* USB Setup, SOF, CRC error and UNF/OVF */ - EVSYS_CHMUX_ACA_CH0_gc = (0x10<<0), /* Analog Comparator A Channel 0 */ - EVSYS_CHMUX_ACA_CH1_gc = (0x11<<0), /* Analog Comparator A Channel 1 */ - EVSYS_CHMUX_ACA_WIN_gc = (0x12<<0), /* Analog Comparator A Window */ - EVSYS_CHMUX_ACB_CH0_gc = (0x13<<0), /* Analog Comparator B Channel 0 */ - EVSYS_CHMUX_ACB_CH1_gc = (0x14<<0), /* Analog Comparator B Channel 1 */ - EVSYS_CHMUX_ACB_WIN_gc = (0x15<<0), /* Analog Comparator B Window */ - EVSYS_CHMUX_ADCA_CH0_gc = (0x20<<0), /* ADC A Channel 0 */ - EVSYS_CHMUX_ADCA_CH1_gc = (0x21<<0), /* ADC A Channel 1 */ - EVSYS_CHMUX_ADCA_CH2_gc = (0x22<<0), /* ADC A Channel 2 */ - EVSYS_CHMUX_ADCA_CH3_gc = (0x23<<0), /* ADC A Channel 3 */ - EVSYS_CHMUX_ADCB_CH0_gc = (0x24<<0), /* ADC B Channel 0 */ - EVSYS_CHMUX_ADCB_CH1_gc = (0x25<<0), /* ADC B Channel 1 */ - EVSYS_CHMUX_ADCB_CH2_gc = (0x26<<0), /* ADC B Channel 2 */ - EVSYS_CHMUX_ADCB_CH3_gc = (0x27<<0), /* ADC B Channel 3 */ - EVSYS_CHMUX_PORTA_PIN0_gc = (0x50<<0), /* Port A, Pin0 */ - EVSYS_CHMUX_PORTA_PIN1_gc = (0x51<<0), /* Port A, Pin1 */ - EVSYS_CHMUX_PORTA_PIN2_gc = (0x52<<0), /* Port A, Pin2 */ - EVSYS_CHMUX_PORTA_PIN3_gc = (0x53<<0), /* Port A, Pin3 */ - EVSYS_CHMUX_PORTA_PIN4_gc = (0x54<<0), /* Port A, Pin4 */ - EVSYS_CHMUX_PORTA_PIN5_gc = (0x55<<0), /* Port A, Pin5 */ - EVSYS_CHMUX_PORTA_PIN6_gc = (0x56<<0), /* Port A, Pin6 */ - EVSYS_CHMUX_PORTA_PIN7_gc = (0x57<<0), /* Port A, Pin7 */ - EVSYS_CHMUX_PORTB_PIN0_gc = (0x58<<0), /* Port B, Pin0 */ - EVSYS_CHMUX_PORTB_PIN1_gc = (0x59<<0), /* Port B, Pin1 */ - EVSYS_CHMUX_PORTB_PIN2_gc = (0x5A<<0), /* Port B, Pin2 */ - EVSYS_CHMUX_PORTB_PIN3_gc = (0x5B<<0), /* Port B, Pin3 */ - EVSYS_CHMUX_PORTB_PIN4_gc = (0x5C<<0), /* Port B, Pin4 */ - EVSYS_CHMUX_PORTB_PIN5_gc = (0x5D<<0), /* Port B, Pin5 */ - EVSYS_CHMUX_PORTB_PIN6_gc = (0x5E<<0), /* Port B, Pin6 */ - EVSYS_CHMUX_PORTB_PIN7_gc = (0x5F<<0), /* Port B, Pin7 */ - EVSYS_CHMUX_PORTC_PIN0_gc = (0x60<<0), /* Port C, Pin0 */ - EVSYS_CHMUX_PORTC_PIN1_gc = (0x61<<0), /* Port C, Pin1 */ - EVSYS_CHMUX_PORTC_PIN2_gc = (0x62<<0), /* Port C, Pin2 */ - EVSYS_CHMUX_PORTC_PIN3_gc = (0x63<<0), /* Port C, Pin3 */ - EVSYS_CHMUX_PORTC_PIN4_gc = (0x64<<0), /* Port C, Pin4 */ - EVSYS_CHMUX_PORTC_PIN5_gc = (0x65<<0), /* Port C, Pin5 */ - EVSYS_CHMUX_PORTC_PIN6_gc = (0x66<<0), /* Port C, Pin6 */ - EVSYS_CHMUX_PORTC_PIN7_gc = (0x67<<0), /* Port C, Pin7 */ - EVSYS_CHMUX_PORTD_PIN0_gc = (0x68<<0), /* Port D, Pin0 */ - EVSYS_CHMUX_PORTD_PIN1_gc = (0x69<<0), /* Port D, Pin1 */ - EVSYS_CHMUX_PORTD_PIN2_gc = (0x6A<<0), /* Port D, Pin2 */ - EVSYS_CHMUX_PORTD_PIN3_gc = (0x6B<<0), /* Port D, Pin3 */ - EVSYS_CHMUX_PORTD_PIN4_gc = (0x6C<<0), /* Port D, Pin4 */ - EVSYS_CHMUX_PORTD_PIN5_gc = (0x6D<<0), /* Port D, Pin5 */ - EVSYS_CHMUX_PORTD_PIN6_gc = (0x6E<<0), /* Port D, Pin6 */ - EVSYS_CHMUX_PORTD_PIN7_gc = (0x6F<<0), /* Port D, Pin7 */ - EVSYS_CHMUX_PORTE_PIN0_gc = (0x70<<0), /* Port E, Pin0 */ - EVSYS_CHMUX_PORTE_PIN1_gc = (0x71<<0), /* Port E, Pin1 */ - EVSYS_CHMUX_PORTE_PIN2_gc = (0x72<<0), /* Port E, Pin2 */ - EVSYS_CHMUX_PORTE_PIN3_gc = (0x73<<0), /* Port E, Pin3 */ - EVSYS_CHMUX_PORTE_PIN4_gc = (0x74<<0), /* Port E, Pin4 */ - EVSYS_CHMUX_PORTE_PIN5_gc = (0x75<<0), /* Port E, Pin5 */ - EVSYS_CHMUX_PORTE_PIN6_gc = (0x76<<0), /* Port E, Pin6 */ - EVSYS_CHMUX_PORTE_PIN7_gc = (0x77<<0), /* Port E, Pin7 */ - EVSYS_CHMUX_PORTF_PIN0_gc = (0x78<<0), /* Port F, Pin0 */ - EVSYS_CHMUX_PORTF_PIN1_gc = (0x79<<0), /* Port F, Pin1 */ - EVSYS_CHMUX_PORTF_PIN2_gc = (0x7A<<0), /* Port F, Pin2 */ - EVSYS_CHMUX_PORTF_PIN3_gc = (0x7B<<0), /* Port F, Pin3 */ - EVSYS_CHMUX_PORTF_PIN4_gc = (0x7C<<0), /* Port F, Pin4 */ - EVSYS_CHMUX_PORTF_PIN5_gc = (0x7D<<0), /* Port F, Pin5 */ - EVSYS_CHMUX_PORTF_PIN6_gc = (0x7E<<0), /* Port F, Pin6 */ - EVSYS_CHMUX_PORTF_PIN7_gc = (0x7F<<0), /* Port F, Pin7 */ - EVSYS_CHMUX_PRESCALER_1_gc = (0x80<<0), /* Prescaler, divide by 1 */ - EVSYS_CHMUX_PRESCALER_2_gc = (0x81<<0), /* Prescaler, divide by 2 */ - EVSYS_CHMUX_PRESCALER_4_gc = (0x82<<0), /* Prescaler, divide by 4 */ - EVSYS_CHMUX_PRESCALER_8_gc = (0x83<<0), /* Prescaler, divide by 8 */ - EVSYS_CHMUX_PRESCALER_16_gc = (0x84<<0), /* Prescaler, divide by 16 */ - EVSYS_CHMUX_PRESCALER_32_gc = (0x85<<0), /* Prescaler, divide by 32 */ - EVSYS_CHMUX_PRESCALER_64_gc = (0x86<<0), /* Prescaler, divide by 64 */ - EVSYS_CHMUX_PRESCALER_128_gc = (0x87<<0), /* Prescaler, divide by 128 */ - EVSYS_CHMUX_PRESCALER_256_gc = (0x88<<0), /* Prescaler, divide by 256 */ - EVSYS_CHMUX_PRESCALER_512_gc = (0x89<<0), /* Prescaler, divide by 512 */ - EVSYS_CHMUX_PRESCALER_1024_gc = (0x8A<<0), /* Prescaler, divide by 1024 */ - EVSYS_CHMUX_PRESCALER_2048_gc = (0x8B<<0), /* Prescaler, divide by 2048 */ - EVSYS_CHMUX_PRESCALER_4096_gc = (0x8C<<0), /* Prescaler, divide by 4096 */ - EVSYS_CHMUX_PRESCALER_8192_gc = (0x8D<<0), /* Prescaler, divide by 8192 */ - EVSYS_CHMUX_PRESCALER_16384_gc = (0x8E<<0), /* Prescaler, divide by 16384 */ - EVSYS_CHMUX_PRESCALER_32768_gc = (0x8F<<0), /* Prescaler, divide by 32768 */ - EVSYS_CHMUX_TCC0_OVF_gc = (0xC0<<0), /* Timer/Counter C0 Overflow */ - EVSYS_CHMUX_TCC0_ERR_gc = (0xC1<<0), /* Timer/Counter C0 Error */ - EVSYS_CHMUX_TCC0_CCA_gc = (0xC4<<0), /* Timer/Counter C0 Compare or Capture A */ - EVSYS_CHMUX_TCC0_CCB_gc = (0xC5<<0), /* Timer/Counter C0 Compare or Capture B */ - EVSYS_CHMUX_TCC0_CCC_gc = (0xC6<<0), /* Timer/Counter C0 Compare or Capture C */ - EVSYS_CHMUX_TCC0_CCD_gc = (0xC7<<0), /* Timer/Counter C0 Compare or Capture D */ - EVSYS_CHMUX_TCC1_OVF_gc = (0xC8<<0), /* Timer/Counter C1 Overflow */ - EVSYS_CHMUX_TCC1_ERR_gc = (0xC9<<0), /* Timer/Counter C1 Error */ - EVSYS_CHMUX_TCC1_CCA_gc = (0xCC<<0), /* Timer/Counter C1 Compare or Capture A */ - EVSYS_CHMUX_TCC1_CCB_gc = (0xCD<<0), /* Timer/Counter C1 Compare or Capture B */ - EVSYS_CHMUX_TCD0_OVF_gc = (0xD0<<0), /* Timer/Counter D0 Overflow */ - EVSYS_CHMUX_TCD0_ERR_gc = (0xD1<<0), /* Timer/Counter D0 Error */ - EVSYS_CHMUX_TCD0_CCA_gc = (0xD4<<0), /* Timer/Counter D0 Compare or Capture A */ - EVSYS_CHMUX_TCD0_CCB_gc = (0xD5<<0), /* Timer/Counter D0 Compare or Capture B */ - EVSYS_CHMUX_TCD0_CCC_gc = (0xD6<<0), /* Timer/Counter D0 Compare or Capture C */ - EVSYS_CHMUX_TCD0_CCD_gc = (0xD7<<0), /* Timer/Counter D0 Compare or Capture D */ - EVSYS_CHMUX_TCD1_OVF_gc = (0xD8<<0), /* Timer/Counter D1 Overflow */ - EVSYS_CHMUX_TCD1_ERR_gc = (0xD9<<0), /* Timer/Counter D1 Error */ - EVSYS_CHMUX_TCD1_CCA_gc = (0xDC<<0), /* Timer/Counter D1 Compare or Capture A */ - EVSYS_CHMUX_TCD1_CCB_gc = (0xDD<<0), /* Timer/Counter D1 Compare or Capture B */ - EVSYS_CHMUX_TCE0_OVF_gc = (0xE0<<0), /* Timer/Counter E0 Overflow */ - EVSYS_CHMUX_TCE0_ERR_gc = (0xE1<<0), /* Timer/Counter E0 Error */ - EVSYS_CHMUX_TCE0_CCA_gc = (0xE4<<0), /* Timer/Counter E0 Compare or Capture A */ - EVSYS_CHMUX_TCE0_CCB_gc = (0xE5<<0), /* Timer/Counter E0 Compare or Capture B */ - EVSYS_CHMUX_TCE0_CCC_gc = (0xE6<<0), /* Timer/Counter E0 Compare or Capture C */ - EVSYS_CHMUX_TCE0_CCD_gc = (0xE7<<0), /* Timer/Counter E0 Compare or Capture D */ - EVSYS_CHMUX_TCE1_OVF_gc = (0xE8<<0), /* Timer/Counter E1 Overflow */ - EVSYS_CHMUX_TCE1_ERR_gc = (0xE9<<0), /* Timer/Counter E1 Error */ - EVSYS_CHMUX_TCE1_CCA_gc = (0xEC<<0), /* Timer/Counter E1 Compare or Capture A */ - EVSYS_CHMUX_TCE1_CCB_gc = (0xED<<0), /* Timer/Counter E1 Compare or Capture B */ - EVSYS_CHMUX_TCF0_OVF_gc = (0xF0<<0), /* Timer/Counter F0 Overflow */ - EVSYS_CHMUX_TCF0_ERR_gc = (0xF1<<0), /* Timer/Counter F0 Error */ - EVSYS_CHMUX_TCF0_CCA_gc = (0xF4<<0), /* Timer/Counter F0 Compare or Capture A */ - EVSYS_CHMUX_TCF0_CCB_gc = (0xF5<<0), /* Timer/Counter F0 Compare or Capture B */ - EVSYS_CHMUX_TCF0_CCC_gc = (0xF6<<0), /* Timer/Counter F0 Compare or Capture C */ - EVSYS_CHMUX_TCF0_CCD_gc = (0xF7<<0), /* Timer/Counter F0 Compare or Capture D */ - EVSYS_CHMUX_TCF1_OVF_gc = (0xF8<<0), /* Timer/Counter F1 Overflow */ - EVSYS_CHMUX_TCF1_ERR_gc = (0xF9<<0), /* Timer/Counter F1 Error */ - EVSYS_CHMUX_TCF1_CCA_gc = (0xFC<<0), /* Timer/Counter F1 Compare or Capture A */ - EVSYS_CHMUX_TCF1_CCB_gc = (0xFD<<0), /* Timer/Counter F1 Compare or Capture B */ -} EVSYS_CHMUX_t; - - -/* --------------------------------------------------------------------------- -NVM - Non Volatile Memory Controller --------------------------------------------------------------------------- -*/ - -/* Non-volatile Memory Controller */ -typedef struct NVM_struct -{ - register8_t ADDR0; /* Address Register 0 */ - register8_t ADDR1; /* Address Register 1 */ - register8_t ADDR2; /* Address Register 2 */ - register8_t reserved_0x03; - register8_t DATA0; /* Data Register 0 */ - register8_t DATA1; /* Data Register 1 */ - register8_t DATA2; /* Data Register 2 */ - register8_t reserved_0x07; - register8_t reserved_0x08; - register8_t reserved_0x09; - register8_t CMD; /* Command */ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t INTCTRL; /* Interrupt Control */ - register8_t reserved_0x0E; - register8_t STATUS; /* Status */ - register8_t LOCK_BITS; /* Lock Bits (Changed from LOCKBITS to avoid avr-libc collision) */ -} NVM_t; - -/* NVM Command */ -typedef enum NVM_CMD_enum -{ - NVM_CMD_NO_OPERATION_gc = (0x00<<0), /* Noop/Ordinary LPM */ - NVM_CMD_READ_USER_SIG_ROW_gc = (0x01<<0), /* Read user signature row */ - NVM_CMD_READ_CALIB_ROW_gc = (0x02<<0), /* Read calibration row */ - NVM_CMD_READ_EEPROM_gc = (0x06<<0), /* Read EEPROM */ - NVM_CMD_READ_FUSES_gc = (0x07<<0), /* Read fuse byte */ - NVM_CMD_WRITE_LOCK_BITS_gc = (0x08<<0), /* Write lock bits */ - NVM_CMD_ERASE_USER_SIG_ROW_gc = (0x18<<0), /* Erase user signature row */ - NVM_CMD_WRITE_USER_SIG_ROW_gc = (0x1A<<0), /* Write user signature row */ - NVM_CMD_ERASE_APP_gc = (0x20<<0), /* Erase Application Section */ - NVM_CMD_ERASE_APP_PAGE_gc = (0x22<<0), /* Erase Application Section page */ - NVM_CMD_LOAD_FLASH_BUFFER_gc = (0x23<<0), /* Load Flash page buffer */ - NVM_CMD_WRITE_APP_PAGE_gc = (0x24<<0), /* Write Application Section page */ - NVM_CMD_ERASE_WRITE_APP_PAGE_gc = (0x25<<0), /* Erase-and-write Application Section page */ - NVM_CMD_ERASE_FLASH_BUFFER_gc = (0x26<<0), /* Erase/flush Flash page buffer */ - NVM_CMD_ERASE_BOOT_PAGE_gc = (0x2A<<0), /* Erase Boot Section page */ - NVM_CMD_ERASE_FLASH_PAGE_gc = (0x2B<<0), /* Erase Flash Page */ - NVM_CMD_WRITE_BOOT_PAGE_gc = (0x2C<<0), /* Write Boot Section page */ - NVM_CMD_ERASE_WRITE_BOOT_PAGE_gc = (0x2D<<0), /* Erase-and-write Boot Section page */ - NVM_CMD_WRITE_FLASH_PAGE_gc = (0x2E<<0), /* Write Flash Page */ - NVM_CMD_ERASE_WRITE_FLASH_PAGE_gc = (0x2F<<0), /* Erase-and-write Flash Page */ - NVM_CMD_ERASE_EEPROM_gc = (0x30<<0), /* Erase EEPROM */ - NVM_CMD_ERASE_EEPROM_PAGE_gc = (0x32<<0), /* Erase EEPROM page */ - NVM_CMD_LOAD_EEPROM_BUFFER_gc = (0x33<<0), /* Load EEPROM page buffer */ - NVM_CMD_WRITE_EEPROM_PAGE_gc = (0x34<<0), /* Write EEPROM page */ - NVM_CMD_ERASE_WRITE_EEPROM_PAGE_gc = (0x35<<0), /* Erase-and-write EEPROM page */ - NVM_CMD_ERASE_EEPROM_BUFFER_gc = (0x36<<0), /* Erase/flush EEPROM page buffer */ - NVM_CMD_APP_CRC_gc = (0x38<<0), /* Application section CRC */ - NVM_CMD_BOOT_CRC_gc = (0x39<<0), /* Boot Section CRC */ - NVM_CMD_FLASH_RANGE_CRC_gc = (0x3A<<0), /* Flash Range CRC */ - NVM_CMD_CHIP_ERASE_gc = (0x40<<0), /* Erase Chip */ - NVM_CMD_READ_NVM_gc = (0x43<<0), /* Read NVM */ - NVM_CMD_WRITE_FUSE_gc = (0x4C<<0), /* Write Fuse byte */ - NVM_CMD_ERASE_BOOT_gc = (0x68<<0), /* Erase Boot Section */ - NVM_CMD_FLASH_CRC_gc = (0x78<<0), /* Flash CRC */ -} NVM_CMD_t; - -/* SPM ready interrupt level */ -typedef enum NVM_SPMLVL_enum -{ - NVM_SPMLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ - NVM_SPMLVL_LO_gc = (0x01<<2), /* Low level */ - NVM_SPMLVL_MED_gc = (0x02<<2), /* Medium level */ - NVM_SPMLVL_HI_gc = (0x03<<2), /* High level */ -} NVM_SPMLVL_t; - -/* EEPROM ready interrupt level */ -typedef enum NVM_EELVL_enum -{ - NVM_EELVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ - NVM_EELVL_LO_gc = (0x01<<0), /* Low level */ - NVM_EELVL_MED_gc = (0x02<<0), /* Medium level */ - NVM_EELVL_HI_gc = (0x03<<0), /* High level */ -} NVM_EELVL_t; - -/* Boot lock bits - boot setcion */ -typedef enum NVM_BLBB_enum -{ - NVM_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ - NVM_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ - NVM_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ - NVM_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ -} NVM_BLBB_t; - -/* Boot lock bits - application section */ -typedef enum NVM_BLBA_enum -{ - NVM_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ - NVM_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ - NVM_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ - NVM_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ -} NVM_BLBA_t; - -/* Boot lock bits - application table section */ -typedef enum NVM_BLBAT_enum -{ - NVM_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ - NVM_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ - NVM_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ - NVM_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ -} NVM_BLBAT_t; - -/* Lock bits */ -typedef enum NVM_LB_enum -{ - NVM_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ - NVM_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ - NVM_LB_NOLOCK_gc = (0x03<<0), /* No locks */ -} NVM_LB_t; - - -/* --------------------------------------------------------------------------- -ADC - Analog/Digital Converter --------------------------------------------------------------------------- -*/ - -/* ADC Channel */ -typedef struct ADC_CH_struct -{ - register8_t CTRL; /* Control Register */ - register8_t MUXCTRL; /* MUX Control */ - register8_t INTCTRL; /* Channel Interrupt Control Register */ - register8_t INTFLAGS; /* Interrupt Flags */ - _WORDREGISTER(RES); /* Channel Result */ - register8_t SCAN; /* Input Channel Scan */ - register8_t reserved_0x07; -} ADC_CH_t; - - -/* Analog-to-Digital Converter */ -typedef struct ADC_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t REFCTRL; /* Reference Control */ - register8_t EVCTRL; /* Event Control */ - register8_t PRESCALER; /* Clock Prescaler */ - register8_t reserved_0x05; - register8_t INTFLAGS; /* Interrupt Flags */ - register8_t TEMP; /* Temporary Register */ - register8_t reserved_0x08; - register8_t reserved_0x09; - register8_t reserved_0x0A; - register8_t reserved_0x0B; - _WORDREGISTER(CAL); /* Calibration Value */ - register8_t reserved_0x0E; - register8_t reserved_0x0F; - _WORDREGISTER(CH0RES); /* Channel 0 Result */ - _WORDREGISTER(CH1RES); /* Channel 1 Result */ - _WORDREGISTER(CH2RES); /* Channel 2 Result */ - _WORDREGISTER(CH3RES); /* Channel 3 Result */ - _WORDREGISTER(CMP); /* Compare Value */ - register8_t reserved_0x1A; - register8_t reserved_0x1B; - register8_t reserved_0x1C; - register8_t reserved_0x1D; - register8_t reserved_0x1E; - register8_t reserved_0x1F; - ADC_CH_t CH0; /* ADC Channel 0 */ - ADC_CH_t CH1; /* ADC Channel 1 */ - ADC_CH_t CH2; /* ADC Channel 2 */ - ADC_CH_t CH3; /* ADC Channel 3 */ -} ADC_t; - -/* Positive input multiplexer selection */ -typedef enum ADC_CH_MUXPOS_enum -{ - ADC_CH_MUXPOS_PIN0_gc = (0x00<<3), /* Input pin 0 */ - ADC_CH_MUXPOS_PIN1_gc = (0x01<<3), /* Input pin 1 */ - ADC_CH_MUXPOS_PIN2_gc = (0x02<<3), /* Input pin 2 */ - ADC_CH_MUXPOS_PIN3_gc = (0x03<<3), /* Input pin 3 */ - ADC_CH_MUXPOS_PIN4_gc = (0x04<<3), /* Input pin 4 */ - ADC_CH_MUXPOS_PIN5_gc = (0x05<<3), /* Input pin 5 */ - ADC_CH_MUXPOS_PIN6_gc = (0x06<<3), /* Input pin 6 */ - ADC_CH_MUXPOS_PIN7_gc = (0x07<<3), /* Input pin 7 */ - ADC_CH_MUXPOS_PIN8_gc = (0x08<<3), /* Input pin 8 */ - ADC_CH_MUXPOS_PIN9_gc = (0x09<<3), /* Input pin 9 */ - ADC_CH_MUXPOS_PIN10_gc = (0x0A<<3), /* Input pin 10 */ - ADC_CH_MUXPOS_PIN11_gc = (0x0B<<3), /* Input pin 11 */ - ADC_CH_MUXPOS_PIN12_gc = (0x0C<<3), /* Input pin 12 */ - ADC_CH_MUXPOS_PIN13_gc = (0x0D<<3), /* Input pin 13 */ - ADC_CH_MUXPOS_PIN14_gc = (0x0E<<3), /* Input pin 14 */ - ADC_CH_MUXPOS_PIN15_gc = (0x0F<<3), /* Input pin 15 */ -} ADC_CH_MUXPOS_t; - -/* Internal input multiplexer selections */ -typedef enum ADC_CH_MUXINT_enum -{ - ADC_CH_MUXINT_TEMP_gc = (0x00<<3), /* Temperature Reference */ - ADC_CH_MUXINT_BANDGAP_gc = (0x01<<3), /* Bandgap Reference */ - ADC_CH_MUXINT_SCALEDVCC_gc = (0x02<<3), /* 1/10 scaled VCC */ - ADC_CH_MUXINT_DAC_gc = (0x03<<3), /* DAC output */ -} ADC_CH_MUXINT_t; - -/* Negative input multiplexer selection */ -typedef enum ADC_CH_MUXNEG_enum -{ - ADC_CH_MUXNEG_PIN0_gc = (0x00<<0), /* Input pin 0 (Input Mode = 2) */ - ADC_CH_MUXNEG_PIN1_gc = (0x01<<0), /* Input pin 1 (Input Mode = 2) */ - ADC_CH_MUXNEG_PIN2_gc = (0x02<<0), /* Input pin 2 (Input Mode = 2) */ - ADC_CH_MUXNEG_PIN3_gc = (0x03<<0), /* Input pin 3 (Input Mode = 2) */ - ADC_CH_MUXNEG_PIN4_gc = (0x00<<0), /* Input pin 4 (Input Mode = 3) */ - ADC_CH_MUXNEG_PIN5_gc = (0x01<<0), /* Input pin 5 (Input Mode = 3) */ - ADC_CH_MUXNEG_PIN6_gc = (0x02<<0), /* Input pin 6 (Input Mode = 3) */ - ADC_CH_MUXNEG_PIN7_gc = (0x03<<0), /* Input pin 7 (Input Mode = 3) */ - ADC_CH_MUXNEG_GND_MODE3_gc = (0x05<<0), /* PAD Ground (Input Mode = 2) */ - ADC_CH_MUXNEG_INTGND_MODE3_gc = (0x07<<0), /* Internal Ground (Input Mode = 2) */ - ADC_CH_MUXNEG_INTGND_MODE4_gc = (0x04<<0), /* Internal Ground (Input Mode = 3) */ - ADC_CH_MUXNEG_GND_MODE4_gc = (0x07<<0), /* PAD Ground (Input Mode = 3) */ -} ADC_CH_MUXNEG_t; - -/* Input mode */ -typedef enum ADC_CH_INPUTMODE_enum -{ - ADC_CH_INPUTMODE_INTERNAL_gc = (0x00<<0), /* Internal inputs, no gain */ - ADC_CH_INPUTMODE_SINGLEENDED_gc = (0x01<<0), /* Single-ended input, no gain */ - ADC_CH_INPUTMODE_DIFF_gc = (0x02<<0), /* Differential input, no gain */ - ADC_CH_INPUTMODE_DIFFWGAIN_gc = (0x03<<0), /* Differential input, with gain */ -} ADC_CH_INPUTMODE_t; - -/* Gain factor */ -typedef enum ADC_CH_GAIN_enum -{ - ADC_CH_GAIN_1X_gc = (0x00<<2), /* 1x gain */ - ADC_CH_GAIN_2X_gc = (0x01<<2), /* 2x gain */ - ADC_CH_GAIN_4X_gc = (0x02<<2), /* 4x gain */ - ADC_CH_GAIN_8X_gc = (0x03<<2), /* 8x gain */ - ADC_CH_GAIN_16X_gc = (0x04<<2), /* 16x gain */ - ADC_CH_GAIN_32X_gc = (0x05<<2), /* 32x gain */ - ADC_CH_GAIN_64X_gc = (0x06<<2), /* 64x gain */ - ADC_CH_GAIN_DIV2_gc = (0x07<<2), /* x/2 gain */ -} ADC_CH_GAIN_t; - -/* Conversion result resolution */ -typedef enum ADC_RESOLUTION_enum -{ - ADC_RESOLUTION_12BIT_gc = (0x00<<1), /* 12-bit right-adjusted result */ - ADC_RESOLUTION_8BIT_gc = (0x02<<1), /* 8-bit right-adjusted result */ - ADC_RESOLUTION_LEFT12BIT_gc = (0x03<<1), /* 12-bit left-adjusted result */ -} ADC_RESOLUTION_t; - -/* Current Limitation Mode */ -typedef enum ADC_CURRLIMIT_enum -{ - ADC_CURRLIMIT_NO_gc = (0x00<<5), /* No limit */ - ADC_CURRLIMIT_LOW_gc = (0x01<<5), /* Low current limit, max. sampling rate 1.5MSPS */ - ADC_CURRLIMIT_MED_gc = (0x02<<5), /* Medium current limit, max. sampling rate 1MSPS */ - ADC_CURRLIMIT_HIGH_gc = (0x03<<5), /* High current limit, max. sampling rate 0.5MSPS */ -} ADC_CURRLIMIT_t; - -/* Voltage reference selection */ -typedef enum ADC_REFSEL_enum -{ - ADC_REFSEL_INT1V_gc = (0x00<<4), /* Internal 1V */ - ADC_REFSEL_INTVCC_gc = (0x01<<4), /* Internal VCC / 1.6 */ - ADC_REFSEL_AREFA_gc = (0x02<<4), /* External reference on PORT A */ - ADC_REFSEL_AREFB_gc = (0x03<<4), /* External reference on PORT B */ - ADC_REFSEL_INTVCC2_gc = (0x04<<4), /* Internal VCC / 2 */ -} ADC_REFSEL_t; - -/* Channel sweep selection */ -typedef enum ADC_SWEEP_enum -{ - ADC_SWEEP_0_gc = (0x00<<6), /* ADC Channel 0 */ - ADC_SWEEP_01_gc = (0x01<<6), /* ADC Channel 0,1 */ - ADC_SWEEP_012_gc = (0x02<<6), /* ADC Channel 0,1,2 */ - ADC_SWEEP_0123_gc = (0x03<<6), /* ADC Channel 0,1,2,3 */ -} ADC_SWEEP_t; - -/* Event channel input selection */ -typedef enum ADC_EVSEL_enum -{ - ADC_EVSEL_0123_gc = (0x00<<3), /* Event Channel 0,1,2,3 */ - ADC_EVSEL_1234_gc = (0x01<<3), /* Event Channel 1,2,3,4 */ - ADC_EVSEL_2345_gc = (0x02<<3), /* Event Channel 2,3,4,5 */ - ADC_EVSEL_3456_gc = (0x03<<3), /* Event Channel 3,4,5,6 */ - ADC_EVSEL_4567_gc = (0x04<<3), /* Event Channel 4,5,6,7 */ - ADC_EVSEL_567_gc = (0x05<<3), /* Event Channel 5,6,7 */ - ADC_EVSEL_67_gc = (0x06<<3), /* Event Channel 6,7 */ - ADC_EVSEL_7_gc = (0x07<<3), /* Event Channel 7 */ -} ADC_EVSEL_t; - -/* Event action selection */ -typedef enum ADC_EVACT_enum -{ - ADC_EVACT_NONE_gc = (0x00<<0), /* No event action */ - ADC_EVACT_CH0_gc = (0x01<<0), /* First event triggers channel 0 */ - ADC_EVACT_CH01_gc = (0x02<<0), /* First two events trigger channel 0,1 */ - ADC_EVACT_CH012_gc = (0x03<<0), /* First three events trigger channel 0,1,2 */ - ADC_EVACT_CH0123_gc = (0x04<<0), /* Events trigger channel 0,1,2,3 */ - ADC_EVACT_SWEEP_gc = (0x05<<0), /* First event triggers sweep */ - ADC_EVACT_SYNCSWEEP_gc = (0x06<<0), /* The ADC is flushed and restarted for accurate timing */ -} ADC_EVACT_t; - -/* Interupt mode */ -typedef enum ADC_CH_INTMODE_enum -{ - ADC_CH_INTMODE_COMPLETE_gc = (0x00<<2), /* Interrupt on conversion complete */ - ADC_CH_INTMODE_BELOW_gc = (0x01<<2), /* Interrupt on result below compare value */ - ADC_CH_INTMODE_ABOVE_gc = (0x03<<2), /* Interrupt on result above compare value */ -} ADC_CH_INTMODE_t; - -/* Interrupt level */ -typedef enum ADC_CH_INTLVL_enum -{ - ADC_CH_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ - ADC_CH_INTLVL_LO_gc = (0x01<<0), /* Low level */ - ADC_CH_INTLVL_MED_gc = (0x02<<0), /* Medium level */ - ADC_CH_INTLVL_HI_gc = (0x03<<0), /* High level */ -} ADC_CH_INTLVL_t; - -/* DMA request selection */ -typedef enum ADC_DMASEL_enum -{ - ADC_DMASEL_OFF_gc = (0x00<<6), /* Combined DMA request OFF */ - ADC_DMASEL_CH01_gc = (0x01<<6), /* ADC Channel 0 or 1 */ - ADC_DMASEL_CH012_gc = (0x02<<6), /* ADC Channel 0 or 1 or 2 */ - ADC_DMASEL_CH0123_gc = (0x03<<6), /* ADC Channel 0 or 1 or 2 or 3 */ -} ADC_DMASEL_t; - -/* Clock prescaler */ -typedef enum ADC_PRESCALER_enum -{ - ADC_PRESCALER_DIV4_gc = (0x00<<0), /* Divide clock by 4 */ - ADC_PRESCALER_DIV8_gc = (0x01<<0), /* Divide clock by 8 */ - ADC_PRESCALER_DIV16_gc = (0x02<<0), /* Divide clock by 16 */ - ADC_PRESCALER_DIV32_gc = (0x03<<0), /* Divide clock by 32 */ - ADC_PRESCALER_DIV64_gc = (0x04<<0), /* Divide clock by 64 */ - ADC_PRESCALER_DIV128_gc = (0x05<<0), /* Divide clock by 128 */ - ADC_PRESCALER_DIV256_gc = (0x06<<0), /* Divide clock by 256 */ - ADC_PRESCALER_DIV512_gc = (0x07<<0), /* Divide clock by 512 */ -} ADC_PRESCALER_t; - - -/* --------------------------------------------------------------------------- -DAC - Digital/Analog Converter --------------------------------------------------------------------------- -*/ - -/* Digital-to-Analog Converter */ -typedef struct DAC_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t CTRLC; /* Control Register C */ - register8_t EVCTRL; /* Event Input Control */ - register8_t reserved_0x04; - register8_t STATUS; /* Status */ - register8_t reserved_0x06; - register8_t reserved_0x07; - register8_t CH0GAINCAL; /* Gain Calibration */ - register8_t CH0OFFSETCAL; /* Offset Calibration */ - register8_t CH1GAINCAL; /* Gain Calibration */ - register8_t CH1OFFSETCAL; /* Offset Calibration */ - register8_t reserved_0x0C; - register8_t reserved_0x0D; - register8_t reserved_0x0E; - register8_t reserved_0x0F; - register8_t reserved_0x10; - register8_t reserved_0x11; - register8_t reserved_0x12; - register8_t reserved_0x13; - register8_t reserved_0x14; - register8_t reserved_0x15; - register8_t reserved_0x16; - register8_t reserved_0x17; - _WORDREGISTER(CH0DATA); /* Channel 0 Data */ - _WORDREGISTER(CH1DATA); /* Channel 1 Data */ -} DAC_t; - -/* Output channel selection */ -typedef enum DAC_CHSEL_enum -{ - DAC_CHSEL_SINGLE_gc = (0x00<<5), /* Single channel operation (Channel 0 only) */ - DAC_CHSEL_SINGLE1_gc = (0x01<<5), /* Single channel operation (Channel 1 only) */ - DAC_CHSEL_DUAL_gc = (0x02<<5), /* Dual channel operation (Channel 0 and channel 1) */ -} DAC_CHSEL_t; - -/* Reference voltage selection */ -typedef enum DAC_REFSEL_enum -{ - DAC_REFSEL_INT1V_gc = (0x00<<3), /* Internal 1V */ - DAC_REFSEL_AVCC_gc = (0x01<<3), /* Analog supply voltage */ - DAC_REFSEL_AREFA_gc = (0x02<<3), /* External reference on AREF on PORTA */ - DAC_REFSEL_AREFB_gc = (0x03<<3), /* External reference on AREF on PORTB */ -} DAC_REFSEL_t; - -/* Event channel selection */ -typedef enum DAC_EVSEL_enum -{ - DAC_EVSEL_0_gc = (0x00<<0), /* Event Channel 0 */ - DAC_EVSEL_1_gc = (0x01<<0), /* Event Channel 1 */ - DAC_EVSEL_2_gc = (0x02<<0), /* Event Channel 2 */ - DAC_EVSEL_3_gc = (0x03<<0), /* Event Channel 3 */ - DAC_EVSEL_4_gc = (0x04<<0), /* Event Channel 4 */ - DAC_EVSEL_5_gc = (0x05<<0), /* Event Channel 5 */ - DAC_EVSEL_6_gc = (0x06<<0), /* Event Channel 6 */ - DAC_EVSEL_7_gc = (0x07<<0), /* Event Channel 7 */ -} DAC_EVSEL_t; - - -/* --------------------------------------------------------------------------- -AC - Analog Comparator --------------------------------------------------------------------------- -*/ - -/* Analog Comparator */ -typedef struct AC_struct -{ - register8_t AC0CTRL; /* Analog Comparator 0 Control */ - register8_t AC1CTRL; /* Analog Comparator 1 Control */ - register8_t AC0MUXCTRL; /* Analog Comparator 0 MUX Control */ - register8_t AC1MUXCTRL; /* Analog Comparator 1 MUX Control */ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t WINCTRL; /* Window Mode Control */ - register8_t STATUS; /* Status */ -} AC_t; - -/* Interrupt mode */ -typedef enum AC_INTMODE_enum -{ - AC_INTMODE_BOTHEDGES_gc = (0x00<<6), /* Interrupt on both edges */ - AC_INTMODE_FALLING_gc = (0x02<<6), /* Interrupt on falling edge */ - AC_INTMODE_RISING_gc = (0x03<<6), /* Interrupt on rising edge */ -} AC_INTMODE_t; - -/* Interrupt level */ -typedef enum AC_INTLVL_enum -{ - AC_INTLVL_OFF_gc = (0x00<<4), /* Interrupt disabled */ - AC_INTLVL_LO_gc = (0x01<<4), /* Low level */ - AC_INTLVL_MED_gc = (0x02<<4), /* Medium level */ - AC_INTLVL_HI_gc = (0x03<<4), /* High level */ -} AC_INTLVL_t; - -/* Hysteresis mode selection */ -typedef enum AC_HYSMODE_enum -{ - AC_HYSMODE_NO_gc = (0x00<<1), /* No hysteresis */ - AC_HYSMODE_SMALL_gc = (0x01<<1), /* Small hysteresis */ - AC_HYSMODE_LARGE_gc = (0x02<<1), /* Large hysteresis */ -} AC_HYSMODE_t; - -/* Positive input multiplexer selection */ -typedef enum AC_MUXPOS_enum -{ - AC_MUXPOS_PIN0_gc = (0x00<<3), /* Pin 0 */ - AC_MUXPOS_PIN1_gc = (0x01<<3), /* Pin 1 */ - AC_MUXPOS_PIN2_gc = (0x02<<3), /* Pin 2 */ - AC_MUXPOS_PIN3_gc = (0x03<<3), /* Pin 3 */ - AC_MUXPOS_PIN4_gc = (0x04<<3), /* Pin 4 */ - AC_MUXPOS_PIN5_gc = (0x05<<3), /* Pin 5 */ - AC_MUXPOS_PIN6_gc = (0x06<<3), /* Pin 6 */ - AC_MUXPOS_DAC_gc = (0x07<<3), /* DAC output */ -} AC_MUXPOS_t; - -/* Negative input multiplexer selection */ -typedef enum AC_MUXNEG_enum -{ - AC_MUXNEG_PIN0_gc = (0x00<<0), /* Pin 0 */ - AC_MUXNEG_PIN1_gc = (0x01<<0), /* Pin 1 */ - AC_MUXNEG_PIN3_gc = (0x02<<0), /* Pin 3 */ - AC_MUXNEG_PIN5_gc = (0x03<<0), /* Pin 5 */ - AC_MUXNEG_PIN7_gc = (0x04<<0), /* Pin 7 */ - AC_MUXNEG_DAC_gc = (0x05<<0), /* DAC output */ - AC_MUXNEG_BANDGAP_gc = (0x06<<0), /* Bandgap Reference */ - AC_MUXNEG_SCALER_gc = (0x07<<0), /* Internal voltage scaler */ -} AC_MUXNEG_t; - -/* Windows interrupt mode */ -typedef enum AC_WINTMODE_enum -{ - AC_WINTMODE_ABOVE_gc = (0x00<<2), /* Interrupt on above window */ - AC_WINTMODE_INSIDE_gc = (0x01<<2), /* Interrupt on inside window */ - AC_WINTMODE_BELOW_gc = (0x02<<2), /* Interrupt on below window */ - AC_WINTMODE_OUTSIDE_gc = (0x03<<2), /* Interrupt on outside window */ -} AC_WINTMODE_t; - -/* Window interrupt level */ -typedef enum AC_WINTLVL_enum -{ - AC_WINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ - AC_WINTLVL_LO_gc = (0x01<<0), /* Low priority */ - AC_WINTLVL_MED_gc = (0x02<<0), /* Medium priority */ - AC_WINTLVL_HI_gc = (0x03<<0), /* High priority */ -} AC_WINTLVL_t; - -/* Window mode state */ -typedef enum AC_WSTATE_enum -{ - AC_WSTATE_ABOVE_gc = (0x00<<6), /* Signal above window */ - AC_WSTATE_INSIDE_gc = (0x01<<6), /* Signal inside window */ - AC_WSTATE_BELOW_gc = (0x02<<6), /* Signal below window */ -} AC_WSTATE_t; - - -/* --------------------------------------------------------------------------- -RTC - Real-Time Counter --------------------------------------------------------------------------- -*/ - -/* Real-Time Counter */ -typedef struct RTC_struct -{ - register8_t CTRL; /* Control Register */ - register8_t STATUS; /* Status Register */ - register8_t INTCTRL; /* Interrupt Control Register */ - register8_t INTFLAGS; /* Interrupt Flags */ - register8_t TEMP; /* Temporary register */ - register8_t reserved_0x05; - register8_t reserved_0x06; - register8_t reserved_0x07; - _WORDREGISTER(CNT); /* Count Register */ - _WORDREGISTER(PER); /* Period Register */ - _WORDREGISTER(COMP); /* Compare Register */ -} RTC_t; - -/* Prescaler Factor */ -typedef enum RTC_PRESCALER_enum -{ - RTC_PRESCALER_OFF_gc = (0x00<<0), /* RTC Off */ - RTC_PRESCALER_DIV1_gc = (0x01<<0), /* RTC Clock */ - RTC_PRESCALER_DIV2_gc = (0x02<<0), /* RTC Clock / 2 */ - RTC_PRESCALER_DIV8_gc = (0x03<<0), /* RTC Clock / 8 */ - RTC_PRESCALER_DIV16_gc = (0x04<<0), /* RTC Clock / 16 */ - RTC_PRESCALER_DIV64_gc = (0x05<<0), /* RTC Clock / 64 */ - RTC_PRESCALER_DIV256_gc = (0x06<<0), /* RTC Clock / 256 */ - RTC_PRESCALER_DIV1024_gc = (0x07<<0), /* RTC Clock / 1024 */ -} RTC_PRESCALER_t; - -/* Compare Interrupt level */ -typedef enum RTC_COMPINTLVL_enum -{ - RTC_COMPINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ - RTC_COMPINTLVL_LO_gc = (0x01<<2), /* Low Level */ - RTC_COMPINTLVL_MED_gc = (0x02<<2), /* Medium Level */ - RTC_COMPINTLVL_HI_gc = (0x03<<2), /* High Level */ -} RTC_COMPINTLVL_t; - -/* Overflow Interrupt level */ -typedef enum RTC_OVFINTLVL_enum -{ - RTC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - RTC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ - RTC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ - RTC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ -} RTC_OVFINTLVL_t; - - -/* --------------------------------------------------------------------------- -TWI - Two-Wire Interface --------------------------------------------------------------------------- -*/ - -/* */ -typedef struct TWI_MASTER_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t CTRLC; /* Control Register C */ - register8_t STATUS; /* Status Register */ - register8_t BAUD; /* Baurd Rate Control Register */ - register8_t ADDR; /* Address Register */ - register8_t DATA; /* Data Register */ -} TWI_MASTER_t; - - -/* */ -typedef struct TWI_SLAVE_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t STATUS; /* Status Register */ - register8_t ADDR; /* Address Register */ - register8_t DATA; /* Data Register */ - register8_t ADDRMASK; /* Address Mask Register */ -} TWI_SLAVE_t; - - -/* Two-Wire Interface */ -typedef struct TWI_struct -{ - register8_t CTRL; /* TWI Common Control Register */ - TWI_MASTER_t MASTER; /* TWI master module */ - TWI_SLAVE_t SLAVE; /* TWI slave module */ -} TWI_t; - -/* SDA Hold Time */ -typedef enum TWI_SDAHOLD_enum -{ - TWI_SDAHOLD_OFF_gc = (0x00<<1), /* SDA Hold Time off */ - TWI_SDAHOLD_50NS_gc = (0x01<<1), /* SDA Hold Time 50 ns */ - TWI_SDAHOLD_300NS_gc = (0x02<<1), /* SDA Hold Time 300 ns */ - TWI_SDAHOLD_400NS_gc = (0x03<<1), /* SDA Hold Time 400 ns */ -} TWI_SDAHOLD_t; - -/* Master Interrupt Level */ -typedef enum TWI_MASTER_INTLVL_enum -{ - TWI_MASTER_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ - TWI_MASTER_INTLVL_LO_gc = (0x01<<6), /* Low Level */ - TWI_MASTER_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ - TWI_MASTER_INTLVL_HI_gc = (0x03<<6), /* High Level */ -} TWI_MASTER_INTLVL_t; - -/* Inactive Timeout */ -typedef enum TWI_MASTER_TIMEOUT_enum -{ - TWI_MASTER_TIMEOUT_DISABLED_gc = (0x00<<2), /* Bus Timeout Disabled */ - TWI_MASTER_TIMEOUT_50US_gc = (0x01<<2), /* 50 Microseconds */ - TWI_MASTER_TIMEOUT_100US_gc = (0x02<<2), /* 100 Microseconds */ - TWI_MASTER_TIMEOUT_200US_gc = (0x03<<2), /* 200 Microseconds */ -} TWI_MASTER_TIMEOUT_t; - -/* Master Command */ -typedef enum TWI_MASTER_CMD_enum -{ - TWI_MASTER_CMD_NOACT_gc = (0x00<<0), /* No Action */ - TWI_MASTER_CMD_REPSTART_gc = (0x01<<0), /* Issue Repeated Start Condition */ - TWI_MASTER_CMD_RECVTRANS_gc = (0x02<<0), /* Receive or Transmit Data */ - TWI_MASTER_CMD_STOP_gc = (0x03<<0), /* Issue Stop Condition */ -} TWI_MASTER_CMD_t; - -/* Master Bus State */ -typedef enum TWI_MASTER_BUSSTATE_enum -{ - TWI_MASTER_BUSSTATE_UNKNOWN_gc = (0x00<<0), /* Unknown Bus State */ - TWI_MASTER_BUSSTATE_IDLE_gc = (0x01<<0), /* Bus is Idle */ - TWI_MASTER_BUSSTATE_OWNER_gc = (0x02<<0), /* This Module Controls The Bus */ - TWI_MASTER_BUSSTATE_BUSY_gc = (0x03<<0), /* The Bus is Busy */ -} TWI_MASTER_BUSSTATE_t; - -/* Slave Interrupt Level */ -typedef enum TWI_SLAVE_INTLVL_enum -{ - TWI_SLAVE_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ - TWI_SLAVE_INTLVL_LO_gc = (0x01<<6), /* Low Level */ - TWI_SLAVE_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ - TWI_SLAVE_INTLVL_HI_gc = (0x03<<6), /* High Level */ -} TWI_SLAVE_INTLVL_t; - -/* Slave Command */ -typedef enum TWI_SLAVE_CMD_enum -{ - TWI_SLAVE_CMD_NOACT_gc = (0x00<<0), /* No Action */ - TWI_SLAVE_CMD_COMPTRANS_gc = (0x02<<0), /* Used To Complete a Transaction */ - TWI_SLAVE_CMD_RESPONSE_gc = (0x03<<0), /* Used in Response to Address/Data Interrupt */ -} TWI_SLAVE_CMD_t; - - -/* --------------------------------------------------------------------------- -USB - USB --------------------------------------------------------------------------- -*/ - -/* USB Endpoint */ -typedef struct USB_EP_struct -{ - register8_t STATUS; /* Endpoint Status */ - register8_t CTRL; /* Endpoint Control */ - _WORDREGISTER(CNT); /* USB Endpoint Counter */ - _WORDREGISTER(DATAPTR); /* Data Pointer */ - _WORDREGISTER(AUXDATA); /* Auxiliary Data */ -} USB_EP_t; - - -/* Universal Serial Bus */ -typedef struct USB_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t STATUS; /* Status Register */ - register8_t ADDR; /* Address Register */ - register8_t FIFOWP; /* FIFO Write Pointer Register */ - register8_t FIFORP; /* FIFO Read Pointer Register */ - _WORDREGISTER(EPPTR); /* Endpoint Configuration Table Pointer */ - register8_t INTCTRLA; /* Interrupt Control Register A */ - register8_t INTCTRLB; /* Interrupt Control Register B */ - register8_t INTFLAGSACLR; /* Clear Interrupt Flag Register A */ - register8_t INTFLAGSASET; /* Set Interrupt Flag Register A */ - register8_t INTFLAGSBCLR; /* Clear Interrupt Flag Register B */ - register8_t INTFLAGSBSET; /* Set Interrupt Flag Register B */ - register8_t reserved_0x0E; - register8_t reserved_0x0F; - register8_t reserved_0x10; - register8_t reserved_0x11; - register8_t reserved_0x12; - register8_t reserved_0x13; - register8_t reserved_0x14; - register8_t reserved_0x15; - register8_t reserved_0x16; - register8_t reserved_0x17; - register8_t reserved_0x18; - register8_t reserved_0x19; - register8_t reserved_0x1A; - register8_t reserved_0x1B; - register8_t reserved_0x1C; - register8_t reserved_0x1D; - register8_t reserved_0x1E; - register8_t reserved_0x1F; - register8_t reserved_0x20; - register8_t reserved_0x21; - register8_t reserved_0x22; - register8_t reserved_0x23; - register8_t reserved_0x24; - register8_t reserved_0x25; - register8_t reserved_0x26; - register8_t reserved_0x27; - register8_t reserved_0x28; - register8_t reserved_0x29; - register8_t reserved_0x2A; - register8_t reserved_0x2B; - register8_t reserved_0x2C; - register8_t reserved_0x2D; - register8_t reserved_0x2E; - register8_t reserved_0x2F; - register8_t reserved_0x30; - register8_t reserved_0x31; - register8_t reserved_0x32; - register8_t reserved_0x33; - register8_t reserved_0x34; - register8_t reserved_0x35; - register8_t reserved_0x36; - register8_t reserved_0x37; - register8_t reserved_0x38; - register8_t reserved_0x39; - register8_t CAL0; /* Calibration Byte 0 */ - register8_t CAL1; /* Calibration Byte 1 */ -} USB_t; - - -/* USB Endpoint Table */ -typedef struct USB_EP_TABLE_struct -{ - USB_EP_t EP0OUT; /* Endpoint 0 */ - USB_EP_t EP0IN; /* Endpoint 0 */ - USB_EP_t EP1OUT; /* Endpoint 1 */ - USB_EP_t EP1IN; /* Endpoint 1 */ - USB_EP_t EP2OUT; /* Endpoint 2 */ - USB_EP_t EP2IN; /* Endpoint 2 */ - USB_EP_t EP3OUT; /* Endpoint 3 */ - USB_EP_t EP3IN; /* Endpoint 3 */ - USB_EP_t EP4OUT; /* Endpoint 4 */ - USB_EP_t EP4IN; /* Endpoint 4 */ - USB_EP_t EP5OUT; /* Endpoint 5 */ - USB_EP_t EP5IN; /* Endpoint 5 */ - USB_EP_t EP6OUT; /* Endpoint 6 */ - USB_EP_t EP6IN; /* Endpoint 6 */ - USB_EP_t EP7OUT; /* Endpoint 7 */ - USB_EP_t EP7IN; /* Endpoint 7 */ - USB_EP_t EP8OUT; /* Endpoint 8 */ - USB_EP_t EP8IN; /* Endpoint 8 */ - USB_EP_t EP9OUT; /* Endpoint 9 */ - USB_EP_t EP9IN; /* Endpoint 9 */ - USB_EP_t EP10OUT; /* Endpoint 10 */ - USB_EP_t EP10IN; /* Endpoint 10 */ - USB_EP_t EP11OUT; /* Endpoint 11 */ - USB_EP_t EP11IN; /* Endpoint 11 */ - USB_EP_t EP12OUT; /* Endpoint 12 */ - USB_EP_t EP12IN; /* Endpoint 12 */ - USB_EP_t EP13OUT; /* Endpoint 13 */ - USB_EP_t EP13IN; /* Endpoint 13 */ - USB_EP_t EP14OUT; /* Endpoint 14 */ - USB_EP_t EP14IN; /* Endpoint 14 */ - USB_EP_t EP15OUT; /* Endpoint 15 */ - USB_EP_t EP15IN; /* Endpoint 15 */ - register8_t reserved_0x100; - register8_t reserved_0x101; - register8_t reserved_0x102; - register8_t reserved_0x103; - register8_t reserved_0x104; - register8_t reserved_0x105; - register8_t reserved_0x106; - register8_t reserved_0x107; - register8_t reserved_0x108; - register8_t reserved_0x109; - register8_t reserved_0x10A; - register8_t reserved_0x10B; - register8_t reserved_0x10C; - register8_t reserved_0x10D; - register8_t reserved_0x10E; - register8_t reserved_0x10F; - register8_t FRAMENUML; /* Frame Number Low Byte */ - register8_t FRAMENUMH; /* Frame Number High Byte */ -} USB_EP_TABLE_t; - -/* Interrupt level */ -typedef enum USB_INTLVL_enum -{ - USB_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ - USB_INTLVL_LO_gc = (0x01<<0), /* Low level */ - USB_INTLVL_MED_gc = (0x02<<0), /* Medium level */ - USB_INTLVL_HI_gc = (0x03<<0), /* High level */ -} USB_INTLVL_t; - -/* USB Endpoint Type */ -typedef enum USB_EP_TYPE_enum -{ - USB_EP_TYPE_DISABLE_gc = (0x00<<6), /* Endpoint Disabled */ - USB_EP_TYPE_CONTROL_gc = (0x01<<6), /* Control */ - USB_EP_TYPE_BULK_gc = (0x02<<6), /* Bulk/Interrupt */ - USB_EP_TYPE_ISOCHRONOUS_gc = (0x03<<6), /* Isochronous */ -} USB_EP_TYPE_t; - -/* USB Endpoint Buffersize */ -typedef enum USB_EP_BUFSIZE_enum -{ - USB_EP_BUFSIZE_8_gc = (0x00<<0), /* 8 bytes buffer size */ - USB_EP_BUFSIZE_16_gc = (0x01<<0), /* 16 bytes buffer size */ - USB_EP_BUFSIZE_32_gc = (0x02<<0), /* 32 bytes buffer size */ - USB_EP_BUFSIZE_64_gc = (0x03<<0), /* 64 bytes buffer size */ - USB_EP_BUFSIZE_128_gc = (0x04<<0), /* 128 bytes buffer size */ - USB_EP_BUFSIZE_256_gc = (0x05<<0), /* 256 bytes buffer size */ - USB_EP_BUFSIZE_512_gc = (0x06<<0), /* 512 bytes buffer size */ - USB_EP_BUFSIZE_1023_gc = (0x07<<0), /* 1023 bytes buffer size */ -} USB_EP_BUFSIZE_t; - - -/* --------------------------------------------------------------------------- -PORT - I/O Port Configuration --------------------------------------------------------------------------- -*/ - -/* I/O Ports */ -typedef struct PORT_struct -{ - register8_t DIR; /* I/O Port Data Direction */ - register8_t DIRSET; /* I/O Port Data Direction Set */ - register8_t DIRCLR; /* I/O Port Data Direction Clear */ - register8_t DIRTGL; /* I/O Port Data Direction Toggle */ - register8_t OUT; /* I/O Port Output */ - register8_t OUTSET; /* I/O Port Output Set */ - register8_t OUTCLR; /* I/O Port Output Clear */ - register8_t OUTTGL; /* I/O Port Output Toggle */ - register8_t IN; /* I/O port Input */ - register8_t INTCTRL; /* Interrupt Control Register */ - register8_t INT0MASK; /* Port Interrupt 0 Mask */ - register8_t INT1MASK; /* Port Interrupt 1 Mask */ - register8_t INTFLAGS; /* Interrupt Flag Register */ - register8_t reserved_0x0D; - register8_t REMAP; /* I/O Port Pin Remap Register */ - register8_t reserved_0x0F; - register8_t PIN0CTRL; /* Pin 0 Control Register */ - register8_t PIN1CTRL; /* Pin 1 Control Register */ - register8_t PIN2CTRL; /* Pin 2 Control Register */ - register8_t PIN3CTRL; /* Pin 3 Control Register */ - register8_t PIN4CTRL; /* Pin 4 Control Register */ - register8_t PIN5CTRL; /* Pin 5 Control Register */ - register8_t PIN6CTRL; /* Pin 6 Control Register */ - register8_t PIN7CTRL; /* Pin 7 Control Register */ -} PORT_t; - -/* Port Interrupt 0 Level */ -typedef enum PORT_INT0LVL_enum -{ - PORT_INT0LVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - PORT_INT0LVL_LO_gc = (0x01<<0), /* Low Level */ - PORT_INT0LVL_MED_gc = (0x02<<0), /* Medium Level */ - PORT_INT0LVL_HI_gc = (0x03<<0), /* High Level */ -} PORT_INT0LVL_t; - -/* Port Interrupt 1 Level */ -typedef enum PORT_INT1LVL_enum -{ - PORT_INT1LVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ - PORT_INT1LVL_LO_gc = (0x01<<2), /* Low Level */ - PORT_INT1LVL_MED_gc = (0x02<<2), /* Medium Level */ - PORT_INT1LVL_HI_gc = (0x03<<2), /* High Level */ -} PORT_INT1LVL_t; - -/* Output/Pull Configuration */ -typedef enum PORT_OPC_enum -{ - PORT_OPC_TOTEM_gc = (0x00<<3), /* Totempole */ - PORT_OPC_BUSKEEPER_gc = (0x01<<3), /* Totempole w/ Bus keeper on Input and Output */ - PORT_OPC_PULLDOWN_gc = (0x02<<3), /* Totempole w/ Pull-down on Input */ - PORT_OPC_PULLUP_gc = (0x03<<3), /* Totempole w/ Pull-up on Input */ - PORT_OPC_WIREDOR_gc = (0x04<<3), /* Wired OR */ - PORT_OPC_WIREDAND_gc = (0x05<<3), /* Wired AND */ - PORT_OPC_WIREDORPULL_gc = (0x06<<3), /* Wired OR w/ Pull-down */ - PORT_OPC_WIREDANDPULL_gc = (0x07<<3), /* Wired AND w/ Pull-up */ -} PORT_OPC_t; - -/* Input/Sense Configuration */ -typedef enum PORT_ISC_enum -{ - PORT_ISC_BOTHEDGES_gc = (0x00<<0), /* Sense Both Edges */ - PORT_ISC_RISING_gc = (0x01<<0), /* Sense Rising Edge */ - PORT_ISC_FALLING_gc = (0x02<<0), /* Sense Falling Edge */ - PORT_ISC_LEVEL_gc = (0x03<<0), /* Sense Level (Transparent For Events) */ - PORT_ISC_INPUT_DISABLE_gc = (0x07<<0), /* Disable Digital Input Buffer */ -} PORT_ISC_t; - - -/* --------------------------------------------------------------------------- -TC - 16-bit Timer/Counter With PWM --------------------------------------------------------------------------- -*/ - -/* 16-bit Timer/Counter 0 */ -typedef struct TC0_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t CTRLC; /* Control register C */ - register8_t CTRLD; /* Control Register D */ - register8_t CTRLE; /* Control Register E */ - register8_t reserved_0x05; - register8_t INTCTRLA; /* Interrupt Control Register A */ - register8_t INTCTRLB; /* Interrupt Control Register B */ - register8_t CTRLFCLR; /* Control Register F Clear */ - register8_t CTRLFSET; /* Control Register F Set */ - register8_t CTRLGCLR; /* Control Register G Clear */ - register8_t CTRLGSET; /* Control Register G Set */ - register8_t INTFLAGS; /* Interrupt Flag Register */ - register8_t reserved_0x0D; - register8_t reserved_0x0E; - register8_t TEMP; /* Temporary Register For 16-bit Access */ - register8_t reserved_0x10; - register8_t reserved_0x11; - register8_t reserved_0x12; - register8_t reserved_0x13; - register8_t reserved_0x14; - register8_t reserved_0x15; - register8_t reserved_0x16; - register8_t reserved_0x17; - register8_t reserved_0x18; - register8_t reserved_0x19; - register8_t reserved_0x1A; - register8_t reserved_0x1B; - register8_t reserved_0x1C; - register8_t reserved_0x1D; - register8_t reserved_0x1E; - register8_t reserved_0x1F; - _WORDREGISTER(CNT); /* Count */ - register8_t reserved_0x22; - register8_t reserved_0x23; - register8_t reserved_0x24; - register8_t reserved_0x25; - _WORDREGISTER(PER); /* Period */ - _WORDREGISTER(CCA); /* Compare or Capture A */ - _WORDREGISTER(CCB); /* Compare or Capture B */ - _WORDREGISTER(CCC); /* Compare or Capture C */ - _WORDREGISTER(CCD); /* Compare or Capture D */ - register8_t reserved_0x30; - register8_t reserved_0x31; - register8_t reserved_0x32; - register8_t reserved_0x33; - register8_t reserved_0x34; - register8_t reserved_0x35; - _WORDREGISTER(PERBUF); /* Period Buffer */ - _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ - _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ - _WORDREGISTER(CCCBUF); /* Compare Or Capture C Buffer */ - _WORDREGISTER(CCDBUF); /* Compare Or Capture D Buffer */ -} TC0_t; - - -/* 16-bit Timer/Counter 1 */ -typedef struct TC1_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t CTRLC; /* Control register C */ - register8_t CTRLD; /* Control Register D */ - register8_t CTRLE; /* Control Register E */ - register8_t reserved_0x05; - register8_t INTCTRLA; /* Interrupt Control Register A */ - register8_t INTCTRLB; /* Interrupt Control Register B */ - register8_t CTRLFCLR; /* Control Register F Clear */ - register8_t CTRLFSET; /* Control Register F Set */ - register8_t CTRLGCLR; /* Control Register G Clear */ - register8_t CTRLGSET; /* Control Register G Set */ - register8_t INTFLAGS; /* Interrupt Flag Register */ - register8_t reserved_0x0D; - register8_t reserved_0x0E; - register8_t TEMP; /* Temporary Register For 16-bit Access */ - register8_t reserved_0x10; - register8_t reserved_0x11; - register8_t reserved_0x12; - register8_t reserved_0x13; - register8_t reserved_0x14; - register8_t reserved_0x15; - register8_t reserved_0x16; - register8_t reserved_0x17; - register8_t reserved_0x18; - register8_t reserved_0x19; - register8_t reserved_0x1A; - register8_t reserved_0x1B; - register8_t reserved_0x1C; - register8_t reserved_0x1D; - register8_t reserved_0x1E; - register8_t reserved_0x1F; - _WORDREGISTER(CNT); /* Count */ - register8_t reserved_0x22; - register8_t reserved_0x23; - register8_t reserved_0x24; - register8_t reserved_0x25; - _WORDREGISTER(PER); /* Period */ - _WORDREGISTER(CCA); /* Compare or Capture A */ - _WORDREGISTER(CCB); /* Compare or Capture B */ - register8_t reserved_0x2C; - register8_t reserved_0x2D; - register8_t reserved_0x2E; - register8_t reserved_0x2F; - register8_t reserved_0x30; - register8_t reserved_0x31; - register8_t reserved_0x32; - register8_t reserved_0x33; - register8_t reserved_0x34; - register8_t reserved_0x35; - _WORDREGISTER(PERBUF); /* Period Buffer */ - _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ - _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ -} TC1_t; - -/* Clock Selection */ -typedef enum TC_CLKSEL_enum -{ - TC_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */ - TC_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */ - TC_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */ - TC_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */ - TC_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */ - TC_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */ - TC_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */ - TC_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */ - TC_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */ - TC_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */ - TC_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */ - TC_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */ - TC_CLKSEL_EVCH4_gc = (0x0C<<0), /* Event Channel 4 */ - TC_CLKSEL_EVCH5_gc = (0x0D<<0), /* Event Channel 5 */ - TC_CLKSEL_EVCH6_gc = (0x0E<<0), /* Event Channel 6 */ - TC_CLKSEL_EVCH7_gc = (0x0F<<0), /* Event Channel 7 */ -} TC_CLKSEL_t; - -/* Waveform Generation Mode */ -typedef enum TC_WGMODE_enum -{ - TC_WGMODE_NORMAL_gc = (0x00<<0), /* Normal Mode */ - TC_WGMODE_FRQ_gc = (0x01<<0), /* Frequency Generation Mode */ - TC_WGMODE_SINGLESLOPE_gc = (0x03<<0), /* Single Slope */ - TC_WGMODE_SS_gc = (0x03<<0), /* Single Slope */ - TC_WGMODE_DSTOP_gc = (0x05<<0), /* Dual Slope, Update on TOP */ - TC_WGMODE_DS_T_gc = (0x05<<0), /* Dual Slope, Update on TOP */ - TC_WGMODE_DSBOTH_gc = (0x06<<0), /* Dual Slope, Update on both TOP and BOTTOM */ - TC_WGMODE_DS_TB_gc = (0x06<<0), /* Dual Slope, Update on both TOP and BOTTOM */ - TC_WGMODE_DSBOTTOM_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */ - TC_WGMODE_DS_B_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */ -} TC_WGMODE_t; - -/* Byte Mode */ -typedef enum TC_BYTEM_enum -{ - TC_BYTEM_NORMAL_gc = (0x00<<0), /* 16-bit mode */ - TC_BYTEM_BYTEMODE_gc = (0x01<<0), /* Timer/Counter operating in byte mode only */ - TC_BYTEM_SPLITMODE_gc = (0x02<<0), /* Timer/Counter split into two 8-bit Counters (TC2) */ -} TC_BYTEM_t; - -/* Event Action */ -typedef enum TC_EVACT_enum -{ - TC_EVACT_OFF_gc = (0x00<<5), /* No Event Action */ - TC_EVACT_CAPT_gc = (0x01<<5), /* Input Capture */ - TC_EVACT_UPDOWN_gc = (0x02<<5), /* Externally Controlled Up/Down Count */ - TC_EVACT_QDEC_gc = (0x03<<5), /* Quadrature Decode */ - TC_EVACT_RESTART_gc = (0x04<<5), /* Restart */ - TC_EVACT_FRQ_gc = (0x05<<5), /* Frequency Capture */ - TC_EVACT_PW_gc = (0x06<<5), /* Pulse-width Capture */ -} TC_EVACT_t; - -/* Event Selection */ -typedef enum TC_EVSEL_enum -{ - TC_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ - TC_EVSEL_CH0_gc = (0x08<<0), /* Event Channel 0 */ - TC_EVSEL_CH1_gc = (0x09<<0), /* Event Channel 1 */ - TC_EVSEL_CH2_gc = (0x0A<<0), /* Event Channel 2 */ - TC_EVSEL_CH3_gc = (0x0B<<0), /* Event Channel 3 */ - TC_EVSEL_CH4_gc = (0x0C<<0), /* Event Channel 4 */ - TC_EVSEL_CH5_gc = (0x0D<<0), /* Event Channel 5 */ - TC_EVSEL_CH6_gc = (0x0E<<0), /* Event Channel 6 */ - TC_EVSEL_CH7_gc = (0x0F<<0), /* Event Channel 7 */ -} TC_EVSEL_t; - -/* Error Interrupt Level */ -typedef enum TC_ERRINTLVL_enum -{ - TC_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ - TC_ERRINTLVL_LO_gc = (0x01<<2), /* Low Level */ - TC_ERRINTLVL_MED_gc = (0x02<<2), /* Medium Level */ - TC_ERRINTLVL_HI_gc = (0x03<<2), /* High Level */ -} TC_ERRINTLVL_t; - -/* Overflow Interrupt Level */ -typedef enum TC_OVFINTLVL_enum -{ - TC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - TC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ - TC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ - TC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ -} TC_OVFINTLVL_t; - -/* Compare or Capture D Interrupt Level */ -typedef enum TC_CCDINTLVL_enum -{ - TC_CCDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ - TC_CCDINTLVL_LO_gc = (0x01<<6), /* Low Level */ - TC_CCDINTLVL_MED_gc = (0x02<<6), /* Medium Level */ - TC_CCDINTLVL_HI_gc = (0x03<<6), /* High Level */ -} TC_CCDINTLVL_t; - -/* Compare or Capture C Interrupt Level */ -typedef enum TC_CCCINTLVL_enum -{ - TC_CCCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ - TC_CCCINTLVL_LO_gc = (0x01<<4), /* Low Level */ - TC_CCCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ - TC_CCCINTLVL_HI_gc = (0x03<<4), /* High Level */ -} TC_CCCINTLVL_t; - -/* Compare or Capture B Interrupt Level */ -typedef enum TC_CCBINTLVL_enum -{ - TC_CCBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ - TC_CCBINTLVL_LO_gc = (0x01<<2), /* Low Level */ - TC_CCBINTLVL_MED_gc = (0x02<<2), /* Medium Level */ - TC_CCBINTLVL_HI_gc = (0x03<<2), /* High Level */ -} TC_CCBINTLVL_t; - -/* Compare or Capture A Interrupt Level */ -typedef enum TC_CCAINTLVL_enum -{ - TC_CCAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - TC_CCAINTLVL_LO_gc = (0x01<<0), /* Low Level */ - TC_CCAINTLVL_MED_gc = (0x02<<0), /* Medium Level */ - TC_CCAINTLVL_HI_gc = (0x03<<0), /* High Level */ -} TC_CCAINTLVL_t; - -/* Timer/Counter Command */ -typedef enum TC_CMD_enum -{ - TC_CMD_NONE_gc = (0x00<<2), /* No Command */ - TC_CMD_UPDATE_gc = (0x01<<2), /* Force Update */ - TC_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ - TC_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ -} TC_CMD_t; - - -/* --------------------------------------------------------------------------- -TC2 - 16-bit Timer/Counter type 2 --------------------------------------------------------------------------- -*/ - -/* 16-bit Timer/Counter type 2 */ -typedef struct TC2_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t CTRLC; /* Control register C */ - register8_t reserved_0x03; - register8_t CTRLE; /* Control Register E */ - register8_t reserved_0x05; - register8_t INTCTRLA; /* Interrupt Control Register A */ - register8_t INTCTRLB; /* Interrupt Control Register B */ - register8_t reserved_0x08; - register8_t CTRLF; /* Control Register F */ - register8_t reserved_0x0A; - register8_t reserved_0x0B; - register8_t INTFLAGS; /* Interrupt Flag Register */ - register8_t reserved_0x0D; - register8_t reserved_0x0E; - register8_t reserved_0x0F; - register8_t reserved_0x10; - register8_t reserved_0x11; - register8_t reserved_0x12; - register8_t reserved_0x13; - register8_t reserved_0x14; - register8_t reserved_0x15; - register8_t reserved_0x16; - register8_t reserved_0x17; - register8_t reserved_0x18; - register8_t reserved_0x19; - register8_t reserved_0x1A; - register8_t reserved_0x1B; - register8_t reserved_0x1C; - register8_t reserved_0x1D; - register8_t reserved_0x1E; - register8_t reserved_0x1F; - register8_t LCNT; /* Low Byte Count */ - register8_t HCNT; /* High Byte Count */ - register8_t reserved_0x22; - register8_t reserved_0x23; - register8_t reserved_0x24; - register8_t reserved_0x25; - register8_t LPER; /* Low Byte Period */ - register8_t HPER; /* High Byte Period */ - register8_t LCMPA; /* Low Byte Compare A */ - register8_t HCMPA; /* High Byte Compare A */ - register8_t LCMPB; /* Low Byte Compare B */ - register8_t HCMPB; /* High Byte Compare B */ - register8_t LCMPC; /* Low Byte Compare C */ - register8_t HCMPC; /* High Byte Compare C */ - register8_t LCMPD; /* Low Byte Compare D */ - register8_t HCMPD; /* High Byte Compare D */ -} TC2_t; - -/* Clock Selection */ -typedef enum TC2_CLKSEL_enum -{ - TC2_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */ - TC2_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */ - TC2_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */ - TC2_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */ - TC2_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */ - TC2_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */ - TC2_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */ - TC2_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */ - TC2_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */ - TC2_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */ - TC2_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */ - TC2_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */ - TC2_CLKSEL_EVCH4_gc = (0x0C<<0), /* Event Channel 4 */ - TC2_CLKSEL_EVCH5_gc = (0x0D<<0), /* Event Channel 5 */ - TC2_CLKSEL_EVCH6_gc = (0x0E<<0), /* Event Channel 6 */ - TC2_CLKSEL_EVCH7_gc = (0x0F<<0), /* Event Channel 7 */ -} TC2_CLKSEL_t; - -/* Byte Mode */ -typedef enum TC2_BYTEM_enum -{ - TC2_BYTEM_NORMAL_gc = (0x00<<0), /* 16-bit mode */ - TC2_BYTEM_BYTEMODE_gc = (0x01<<0), /* Timer/Counter operating in byte mode only (TC2) */ - TC2_BYTEM_SPLITMODE_gc = (0x02<<0), /* Timer/Counter split into two 8-bit Counters */ -} TC2_BYTEM_t; - -/* High Byte Underflow Interrupt Level */ -typedef enum TC2_HUNFINTLVL_enum -{ - TC2_HUNFINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ - TC2_HUNFINTLVL_LO_gc = (0x01<<2), /* Low Level */ - TC2_HUNFINTLVL_MED_gc = (0x02<<2), /* Medium Level */ - TC2_HUNFINTLVL_HI_gc = (0x03<<2), /* High Level */ -} TC2_HUNFINTLVL_t; - -/* Low Byte Underflow Interrupt Level */ -typedef enum TC2_LUNFINTLVL_enum -{ - TC2_LUNFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - TC2_LUNFINTLVL_LO_gc = (0x01<<0), /* Low Level */ - TC2_LUNFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ - TC2_LUNFINTLVL_HI_gc = (0x03<<0), /* High Level */ -} TC2_LUNFINTLVL_t; - -/* Low Byte Compare D Interrupt Level */ -typedef enum TC2_LCMPDINTLVL_enum -{ - TC2_LCMPDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ - TC2_LCMPDINTLVL_LO_gc = (0x01<<6), /* Low Level */ - TC2_LCMPDINTLVL_MED_gc = (0x02<<6), /* Medium Level */ - TC2_LCMPDINTLVL_HI_gc = (0x03<<6), /* High Level */ -} TC2_LCMPDINTLVL_t; - -/* Low Byte Compare C Interrupt Level */ -typedef enum TC2_LCMPCINTLVL_enum -{ - TC2_LCMPCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ - TC2_LCMPCINTLVL_LO_gc = (0x01<<4), /* Low Level */ - TC2_LCMPCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ - TC2_LCMPCINTLVL_HI_gc = (0x03<<4), /* High Level */ -} TC2_LCMPCINTLVL_t; - -/* Low Byte Compare B Interrupt Level */ -typedef enum TC2_LCMPBINTLVL_enum -{ - TC2_LCMPBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ - TC2_LCMPBINTLVL_LO_gc = (0x01<<2), /* Low Level */ - TC2_LCMPBINTLVL_MED_gc = (0x02<<2), /* Medium Level */ - TC2_LCMPBINTLVL_HI_gc = (0x03<<2), /* High Level */ -} TC2_LCMPBINTLVL_t; - -/* Low Byte Compare A Interrupt Level */ -typedef enum TC2_LCMPAINTLVL_enum -{ - TC2_LCMPAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - TC2_LCMPAINTLVL_LO_gc = (0x01<<0), /* Low Level */ - TC2_LCMPAINTLVL_MED_gc = (0x02<<0), /* Medium Level */ - TC2_LCMPAINTLVL_HI_gc = (0x03<<0), /* High Level */ -} TC2_LCMPAINTLVL_t; - -/* Timer/Counter Command */ -typedef enum TC2_CMD_enum -{ - TC2_CMD_NONE_gc = (0x00<<2), /* No Command */ - TC2_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ - TC2_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ -} TC2_CMD_t; - -/* Timer/Counter Command */ -typedef enum TC2_CMDEN_enum -{ - TC2_CMDEN_LOW_gc = (0x01<<0), /* Low Byte Timer/Counter */ - TC2_CMDEN_HIGH_gc = (0x02<<0), /* High Byte Timer/Counter */ - TC2_CMDEN_BOTH_gc = (0x03<<0), /* Both Low Byte and High Byte Timer/Counters */ -} TC2_CMDEN_t; - - -/* --------------------------------------------------------------------------- -AWEX - Timer/Counter Advanced Waveform Extension --------------------------------------------------------------------------- -*/ - -/* Advanced Waveform Extension */ -typedef struct AWEX_struct -{ - register8_t CTRL; /* Control Register */ - register8_t reserved_0x01; - register8_t FDEMASK; /* Fault Detection Event Mask */ - register8_t FDCTRL; /* Fault Detection Control Register */ - register8_t STATUS; /* Status Register */ - register8_t STATUSSET; /* Status Set Register */ - register8_t DTBOTH; /* Dead Time Both Sides */ - register8_t DTBOTHBUF; /* Dead Time Both Sides Buffer */ - register8_t DTLS; /* Dead Time Low Side */ - register8_t DTHS; /* Dead Time High Side */ - register8_t DTLSBUF; /* Dead Time Low Side Buffer */ - register8_t DTHSBUF; /* Dead Time High Side Buffer */ - register8_t OUTOVEN; /* Output Override Enable */ -} AWEX_t; - -/* Fault Detect Action */ -typedef enum AWEX_FDACT_enum -{ - AWEX_FDACT_NONE_gc = (0x00<<0), /* No Fault Protection */ - AWEX_FDACT_CLEAROE_gc = (0x01<<0), /* Clear Output Enable Bits */ - AWEX_FDACT_CLEARDIR_gc = (0x03<<0), /* Clear I/O Port Direction Bits */ -} AWEX_FDACT_t; - - -/* --------------------------------------------------------------------------- -HIRES - Timer/Counter High-Resolution Extension --------------------------------------------------------------------------- -*/ - -/* High-Resolution Extension */ -typedef struct HIRES_struct -{ - register8_t CTRLA; /* Control Register */ -} HIRES_t; - -/* High Resolution Enable */ -typedef enum HIRES_HREN_enum -{ - HIRES_HREN_NONE_gc = (0x00<<0), /* No Fault Protection */ - HIRES_HREN_TC0_gc = (0x01<<0), /* Enable High Resolution on Timer/Counter 0 */ - HIRES_HREN_TC1_gc = (0x02<<0), /* Enable High Resolution on Timer/Counter 1 */ - HIRES_HREN_BOTH_gc = (0x03<<0), /* Enable High Resolution both Timer/Counters */ -} HIRES_HREN_t; - - -/* --------------------------------------------------------------------------- -USART - Universal Asynchronous Receiver-Transmitter --------------------------------------------------------------------------- -*/ - -/* Universal Synchronous/Asynchronous Receiver/Transmitter */ -typedef struct USART_struct -{ - register8_t DATA; /* Data Register */ - register8_t STATUS; /* Status Register */ - register8_t reserved_0x02; - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t CTRLC; /* Control Register C */ - register8_t BAUDCTRLA; /* Baud Rate Control Register A */ - register8_t BAUDCTRLB; /* Baud Rate Control Register B */ -} USART_t; - -/* Receive Complete Interrupt level */ -typedef enum USART_RXCINTLVL_enum -{ - USART_RXCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ - USART_RXCINTLVL_LO_gc = (0x01<<4), /* Low Level */ - USART_RXCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ - USART_RXCINTLVL_HI_gc = (0x03<<4), /* High Level */ -} USART_RXCINTLVL_t; - -/* Transmit Complete Interrupt level */ -typedef enum USART_TXCINTLVL_enum -{ - USART_TXCINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ - USART_TXCINTLVL_LO_gc = (0x01<<2), /* Low Level */ - USART_TXCINTLVL_MED_gc = (0x02<<2), /* Medium Level */ - USART_TXCINTLVL_HI_gc = (0x03<<2), /* High Level */ -} USART_TXCINTLVL_t; - -/* Data Register Empty Interrupt level */ -typedef enum USART_DREINTLVL_enum -{ - USART_DREINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - USART_DREINTLVL_LO_gc = (0x01<<0), /* Low Level */ - USART_DREINTLVL_MED_gc = (0x02<<0), /* Medium Level */ - USART_DREINTLVL_HI_gc = (0x03<<0), /* High Level */ -} USART_DREINTLVL_t; - -/* Character Size */ -typedef enum USART_CHSIZE_enum -{ - USART_CHSIZE_5BIT_gc = (0x00<<0), /* Character size: 5 bit */ - USART_CHSIZE_6BIT_gc = (0x01<<0), /* Character size: 6 bit */ - USART_CHSIZE_7BIT_gc = (0x02<<0), /* Character size: 7 bit */ - USART_CHSIZE_8BIT_gc = (0x03<<0), /* Character size: 8 bit */ - USART_CHSIZE_9BIT_gc = (0x07<<0), /* Character size: 9 bit */ -} USART_CHSIZE_t; - -/* Communication Mode */ -typedef enum USART_CMODE_enum -{ - USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6), /* Asynchronous Mode */ - USART_CMODE_SYNCHRONOUS_gc = (0x01<<6), /* Synchronous Mode */ - USART_CMODE_IRDA_gc = (0x02<<6), /* IrDA Mode */ - USART_CMODE_MSPI_gc = (0x03<<6), /* Master SPI Mode */ -} USART_CMODE_t; - -/* Parity Mode */ -typedef enum USART_PMODE_enum -{ - USART_PMODE_DISABLED_gc = (0x00<<4), /* No Parity */ - USART_PMODE_EVEN_gc = (0x02<<4), /* Even Parity */ - USART_PMODE_ODD_gc = (0x03<<4), /* Odd Parity */ -} USART_PMODE_t; - - -/* --------------------------------------------------------------------------- -SPI - Serial Peripheral Interface --------------------------------------------------------------------------- -*/ - -/* Serial Peripheral Interface */ -typedef struct SPI_struct -{ - register8_t CTRL; /* Control Register */ - register8_t INTCTRL; /* Interrupt Control Register */ - register8_t STATUS; /* Status Register */ - register8_t DATA; /* Data Register */ -} SPI_t; - -/* SPI Mode */ -typedef enum SPI_MODE_enum -{ - SPI_MODE_0_gc = (0x00<<2), /* SPI Mode 0 */ - SPI_MODE_1_gc = (0x01<<2), /* SPI Mode 1 */ - SPI_MODE_2_gc = (0x02<<2), /* SPI Mode 2 */ - SPI_MODE_3_gc = (0x03<<2), /* SPI Mode 3 */ -} SPI_MODE_t; - -/* Prescaler setting */ -typedef enum SPI_PRESCALER_enum -{ - SPI_PRESCALER_DIV4_gc = (0x00<<0), /* System Clock / 4 */ - SPI_PRESCALER_DIV16_gc = (0x01<<0), /* System Clock / 16 */ - SPI_PRESCALER_DIV64_gc = (0x02<<0), /* System Clock / 64 */ - SPI_PRESCALER_DIV128_gc = (0x03<<0), /* System Clock / 128 */ -} SPI_PRESCALER_t; - -/* Interrupt level */ -typedef enum SPI_INTLVL_enum -{ - SPI_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - SPI_INTLVL_LO_gc = (0x01<<0), /* Low Level */ - SPI_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ - SPI_INTLVL_HI_gc = (0x03<<0), /* High Level */ -} SPI_INTLVL_t; - - -/* --------------------------------------------------------------------------- -IRCOM - IR Communication Module --------------------------------------------------------------------------- -*/ - -/* IR Communication Module */ -typedef struct IRCOM_struct -{ - register8_t CTRL; /* Control Register */ - register8_t TXPLCTRL; /* IrDA Transmitter Pulse Length Control Register */ - register8_t RXPLCTRL; /* IrDA Receiver Pulse Length Control Register */ -} IRCOM_t; - -/* Event channel selection */ -typedef enum IRDA_EVSEL_enum -{ - IRDA_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ - IRDA_EVSEL_0_gc = (0x08<<0), /* Event Channel 0 */ - IRDA_EVSEL_1_gc = (0x09<<0), /* Event Channel 1 */ - IRDA_EVSEL_2_gc = (0x0A<<0), /* Event Channel 2 */ - IRDA_EVSEL_3_gc = (0x0B<<0), /* Event Channel 3 */ - IRDA_EVSEL_4_gc = (0x0C<<0), /* Event Channel 4 */ - IRDA_EVSEL_5_gc = (0x0D<<0), /* Event Channel 5 */ - IRDA_EVSEL_6_gc = (0x0E<<0), /* Event Channel 6 */ - IRDA_EVSEL_7_gc = (0x0F<<0), /* Event Channel 7 */ -} IRDA_EVSEL_t; - - -/* --------------------------------------------------------------------------- -FUSE - Fuses and Lockbits --------------------------------------------------------------------------- -*/ - -/* Fuses */ -typedef struct NVM_FUSES_struct -{ - register8_t FUSEBYTE0; /* JTAG User ID */ - register8_t FUSEBYTE1; /* Watchdog Configuration */ - register8_t FUSEBYTE2; /* Reset Configuration */ - register8_t reserved_0x03; - register8_t FUSEBYTE4; /* Start-up Configuration */ - register8_t FUSEBYTE5; /* EESAVE and BOD Level */ -} NVM_FUSES_t; - -/* Boot Loader Section Reset Vector */ -typedef enum BOOTRST_enum -{ - BOOTRST_BOOTLDR_gc = (0x00<<6), /* Boot Loader Reset */ - BOOTRST_APPLICATION_gc = (0x01<<6), /* Application Reset */ -} BOOTRST_t; - -/* Timer Oscillator pin location */ -typedef enum TOSCSEL_enum -{ - TOSCSEL_ALTERNATE_gc = (0x00<<5), /* TOSC1 / TOSC2 on separate pins */ - TOSCSEL_XTAL_gc = (0x01<<5), /* TOSC1 / TOSC2 shared with XTAL1 / XTAL2 */ -} TOSCSEL_t; - -/* BOD operation */ -typedef enum BOD_enum -{ - BOD_SAMPLED_gc = (0x01<<0), /* BOD enabled in sampled mode */ - BOD_CONTINUOUS_gc = (0x02<<0), /* BOD enabled continuously */ - BOD_DISABLED_gc = (0x03<<0), /* BOD Disabled */ -} BOD_t; - -/* BOD operation */ -typedef enum BODACT_enum -{ - BODACT_SAMPLED_gc = (0x01<<4), /* BOD enabled in sampled mode */ - BODACT_CONTINUOUS_gc = (0x02<<4), /* BOD enabled continuously */ - BODACT_DISABLED_gc = (0x03<<4), /* BOD Disabled */ -} BODACT_t; - -/* Watchdog (Window) Timeout Period */ -typedef enum WD_enum -{ - WD_8CLK_gc = (0x00<<4), /* 8 cycles (8ms @ 3.3V) */ - WD_16CLK_gc = (0x01<<4), /* 16 cycles (16ms @ 3.3V) */ - WD_32CLK_gc = (0x02<<4), /* 32 cycles (32ms @ 3.3V) */ - WD_64CLK_gc = (0x03<<4), /* 64 cycles (64ms @ 3.3V) */ - WD_128CLK_gc = (0x04<<4), /* 128 cycles (0.125s @ 3.3V) */ - WD_256CLK_gc = (0x05<<4), /* 256 cycles (0.25s @ 3.3V) */ - WD_512CLK_gc = (0x06<<4), /* 512 cycles (0.5s @ 3.3V) */ - WD_1KCLK_gc = (0x07<<4), /* 1K cycles (1s @ 3.3V) */ - WD_2KCLK_gc = (0x08<<4), /* 2K cycles (2s @ 3.3V) */ - WD_4KCLK_gc = (0x09<<4), /* 4K cycles (4s @ 3.3V) */ - WD_8KCLK_gc = (0x0A<<4), /* 8K cycles (8s @ 3.3V) */ -} WD_t; - -/* Watchdog (Window) Timeout Period */ -typedef enum WDP_enum -{ - WDP_8CLK_gc = (0x00<<0), /* 8 cycles (8ms @ 3.3V) */ - WDP_16CLK_gc = (0x01<<0), /* 16 cycles (16ms @ 3.3V) */ - WDP_32CLK_gc = (0x02<<0), /* 32 cycles (32ms @ 3.3V) */ - WDP_64CLK_gc = (0x03<<0), /* 64 cycles (64ms @ 3.3V) */ - WDP_128CLK_gc = (0x04<<0), /* 128 cycles (0.125s @ 3.3V) */ - WDP_256CLK_gc = (0x05<<0), /* 256 cycles (0.25s @ 3.3V) */ - WDP_512CLK_gc = (0x06<<0), /* 512 cycles (0.5s @ 3.3V) */ - WDP_1KCLK_gc = (0x07<<0), /* 1K cycles (1s @ 3.3V) */ - WDP_2KCLK_gc = (0x08<<0), /* 2K cycles (2s @ 3.3V) */ - WDP_4KCLK_gc = (0x09<<0), /* 4K cycles (4s @ 3.3V) */ - WDP_8KCLK_gc = (0x0A<<0), /* 8K cycles (8s @ 3.3V) */ -} WDP_t; - -/* Start-up Time */ -typedef enum SUT_enum -{ - SUT_0MS_gc = (0x03<<2), /* 0 ms */ - SUT_4MS_gc = (0x01<<2), /* 4 ms */ - SUT_64MS_gc = (0x00<<2), /* 64 ms */ -} SUT_t; - -/* Brownout Detection Voltage Level */ -typedef enum BODLVL_enum -{ - BODLVL_1V6_gc = (0x07<<0), /* 1.6 V */ - BODLVL_1V8_gc = (0x06<<0), /* 1.8 V */ - BODLVL_2V0_gc = (0x05<<0), /* 2.0 V */ - BODLVL_2V2_gc = (0x04<<0), /* 2.2 V */ - BODLVL_2V4_gc = (0x03<<0), /* 2.4 V */ - BODLVL_2V6_gc = (0x02<<0), /* 2.6 V */ - BODLVL_2V8_gc = (0x01<<0), /* 2.8 V */ - BODLVL_3V0_gc = (0x00<<0), /* 3.0 V */ -} BODLVL_t; - - -/* --------------------------------------------------------------------------- -LOCKBIT - Fuses and Lockbits --------------------------------------------------------------------------- -*/ - -/* Lock Bits */ -typedef struct NVM_LOCKBITS_struct -{ - register8_t LOCK_BITS; /* Lock Bits (Changed from LOCKBITS to avoid avr-libc collision) */ -} NVM_LOCKBITS_t; - -/* Boot lock bits - boot setcion */ -typedef enum FUSE_BLBB_enum -{ - FUSE_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ - FUSE_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ - FUSE_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ - FUSE_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ -} FUSE_BLBB_t; - -/* Boot lock bits - application section */ -typedef enum FUSE_BLBA_enum -{ - FUSE_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ - FUSE_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ - FUSE_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ - FUSE_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ -} FUSE_BLBA_t; - -/* Boot lock bits - application table section */ -typedef enum FUSE_BLBAT_enum -{ - FUSE_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ - FUSE_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ - FUSE_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ - FUSE_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ -} FUSE_BLBAT_t; - -/* Lock bits */ -typedef enum FUSE_LB_enum -{ - FUSE_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ - FUSE_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ - FUSE_LB_NOLOCK_gc = (0x03<<0), /* No locks */ -} FUSE_LB_t; - - -/* --------------------------------------------------------------------------- -SIGROW - Signature Row --------------------------------------------------------------------------- -*/ - -/* Production Signatures */ -typedef struct NVM_PROD_SIGNATURES_struct -{ - register8_t RCOSC2M; /* RCOSC 2 MHz Calibration Value B */ - register8_t RCOSC2MA; /* RCOSC 2 MHz Calibration Value A */ - register8_t RCOSC32K; /* RCOSC 32.768 kHz Calibration Value */ - register8_t RCOSC32M; /* RCOSC 32 MHz Calibration Value B */ - register8_t RCOSC32MA; /* RCOSC 32 MHz Calibration Value A */ - register8_t reserved_0x05; - register8_t reserved_0x06; - register8_t reserved_0x07; - register8_t LOTNUM0; /* Lot Number Byte 0, ASCII */ - register8_t LOTNUM1; /* Lot Number Byte 1, ASCII */ - register8_t LOTNUM2; /* Lot Number Byte 2, ASCII */ - register8_t LOTNUM3; /* Lot Number Byte 3, ASCII */ - register8_t LOTNUM4; /* Lot Number Byte 4, ASCII */ - register8_t LOTNUM5; /* Lot Number Byte 5, ASCII */ - register8_t reserved_0x0E; - register8_t reserved_0x0F; - register8_t WAFNUM; /* Wafer Number */ - register8_t reserved_0x11; - register8_t COORDX0; /* Wafer Coordinate X Byte 0 */ - register8_t COORDX1; /* Wafer Coordinate X Byte 1 */ - register8_t COORDY0; /* Wafer Coordinate Y Byte 0 */ - register8_t COORDY1; /* Wafer Coordinate Y Byte 1 */ - register8_t reserved_0x16; - register8_t reserved_0x17; - register8_t reserved_0x18; - register8_t reserved_0x19; - register8_t USBCAL0; /* USB Calibration Byte 0 */ - register8_t USBCAL1; /* USB Calibration Byte 1 */ - register8_t USBRCOSC; /* USB RCOSC Calibration Value B */ - register8_t USBRCOSCA; /* USB RCOSC Calibration Value A */ - register8_t reserved_0x1E; - register8_t reserved_0x1F; - register8_t ADCACAL0; /* ADCA Calibration Byte 0 */ - register8_t ADCACAL1; /* ADCA Calibration Byte 1 */ - register8_t reserved_0x22; - register8_t reserved_0x23; - register8_t ADCBCAL0; /* ADCB Calibration Byte 0 */ - register8_t ADCBCAL1; /* ADCB Calibration Byte 1 */ - register8_t reserved_0x26; - register8_t reserved_0x27; - register8_t reserved_0x28; - register8_t reserved_0x29; - register8_t reserved_0x2A; - register8_t reserved_0x2B; - register8_t reserved_0x2C; - register8_t reserved_0x2D; - register8_t TEMPSENSE0; /* Temperature Sensor Calibration Byte 0 */ - register8_t TEMPSENSE1; /* Temperature Sensor Calibration Byte 1 */ - register8_t DACA0OFFCAL; /* DACA0 Calibration Byte 0 */ - register8_t DACA0GAINCAL; /* DACA0 Calibration Byte 1 */ - register8_t DACB0OFFCAL; /* DACB0 Calibration Byte 0 */ - register8_t DACB0GAINCAL; /* DACB0 Calibration Byte 1 */ - register8_t DACA1OFFCAL; /* DACA1 Calibration Byte 0 */ - register8_t DACA1GAINCAL; /* DACA1 Calibration Byte 1 */ - register8_t DACB1OFFCAL; /* DACB1 Calibration Byte 0 */ - register8_t DACB1GAINCAL; /* DACB1 Calibration Byte 1 */ - register8_t reserved_0x38; - register8_t reserved_0x39; - register8_t reserved_0x3A; - register8_t reserved_0x3B; - register8_t reserved_0x3C; - register8_t reserved_0x3D; - register8_t reserved_0x3E; - register8_t reserved_0x3F; - register8_t reserved_0x40; - register8_t reserved_0x41; - register8_t reserved_0x42; - register8_t reserved_0x43; - register8_t reserved_0x44; - register8_t reserved_0x45; - register8_t reserved_0x46; - register8_t reserved_0x47; -} NVM_PROD_SIGNATURES_t; - -/* -========================================================================== -IO Module Instances. Mapped to memory. -========================================================================== -*/ - -#define VPORT0 (*(VPORT_t *) 0x0010) /* Virtual Port */ -#define VPORT1 (*(VPORT_t *) 0x0014) /* Virtual Port */ -#define VPORT2 (*(VPORT_t *) 0x0018) /* Virtual Port */ -#define VPORT3 (*(VPORT_t *) 0x001C) /* Virtual Port */ -#define OCD (*(OCD_t *) 0x002E) /* On-Chip Debug System */ -#define CLK (*(CLK_t *) 0x0040) /* Clock System */ -#define SLEEP (*(SLEEP_t *) 0x0048) /* Sleep Controller */ -#define OSC (*(OSC_t *) 0x0050) /* Oscillator */ -#define DFLLRC32M (*(DFLL_t *) 0x0060) /* DFLL */ -#define DFLLRC2M (*(DFLL_t *) 0x0068) /* DFLL */ -#define PR (*(PR_t *) 0x0070) /* Power Reduction */ -#define RST (*(RST_t *) 0x0078) /* Reset */ -#define WDT (*(WDT_t *) 0x0080) /* Watch-Dog Timer */ -#define MCU (*(MCU_t *) 0x0090) /* MCU Control */ -#define PMIC (*(PMIC_t *) 0x00A0) /* Programmable Multi-level Interrupt Controller */ -#define PORTCFG (*(PORTCFG_t *) 0x00B0) /* I/O port Configuration */ -#define AES (*(AES_t *) 0x00C0) /* AES Module */ -#define CRC (*(CRC_t *) 0x00D0) /* Cyclic Redundancy Checker */ -#define DMA (*(DMA_t *) 0x0100) /* DMA Controller */ -#define EVSYS (*(EVSYS_t *) 0x0180) /* Event System */ -#define NVM (*(NVM_t *) 0x01C0) /* Non-volatile Memory Controller */ -#define ADCA (*(ADC_t *) 0x0200) /* Analog-to-Digital Converter */ -#define ADCB (*(ADC_t *) 0x0240) /* Analog-to-Digital Converter */ -#define DACB (*(DAC_t *) 0x0320) /* Digital-to-Analog Converter */ -#define ACA (*(AC_t *) 0x0380) /* Analog Comparator */ -#define ACB (*(AC_t *) 0x0390) /* Analog Comparator */ -#define RTC (*(RTC_t *) 0x0400) /* Real-Time Counter */ -#define TWIC (*(TWI_t *) 0x0480) /* Two-Wire Interface */ -#define TWIE (*(TWI_t *) 0x04A0) /* Two-Wire Interface */ -#define USB (*(USB_t *) 0x04C0) /* Universal Serial Bus */ -#define PORTA (*(PORT_t *) 0x0600) /* I/O Ports */ -#define PORTB (*(PORT_t *) 0x0620) /* I/O Ports */ -#define PORTC (*(PORT_t *) 0x0640) /* I/O Ports */ -#define PORTD (*(PORT_t *) 0x0660) /* I/O Ports */ -#define PORTE (*(PORT_t *) 0x0680) /* I/O Ports */ -#define PORTF (*(PORT_t *) 0x06A0) /* I/O Ports */ -#define PORTR (*(PORT_t *) 0x07E0) /* I/O Ports */ -#define TCC0 (*(TC0_t *) 0x0800) /* 16-bit Timer/Counter 0 */ -#define TCC2 (*(TC2_t *) 0x0800) /* 16-bit Timer/Counter type 2 */ -#define TCC1 (*(TC1_t *) 0x0840) /* 16-bit Timer/Counter 1 */ -#define AWEXC (*(AWEX_t *) 0x0880) /* Advanced Waveform Extension */ -#define HIRESC (*(HIRES_t *) 0x0890) /* High-Resolution Extension */ -#define USARTC0 (*(USART_t *) 0x08A0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ -#define USARTC1 (*(USART_t *) 0x08B0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ -#define SPIC (*(SPI_t *) 0x08C0) /* Serial Peripheral Interface */ -#define IRCOM (*(IRCOM_t *) 0x08F8) /* IR Communication Module */ -#define TCD0 (*(TC0_t *) 0x0900) /* 16-bit Timer/Counter 0 */ -#define TCD2 (*(TC2_t *) 0x0900) /* 16-bit Timer/Counter type 2 */ -#define TCD1 (*(TC1_t *) 0x0940) /* 16-bit Timer/Counter 1 */ -#define HIRESD (*(HIRES_t *) 0x0990) /* High-Resolution Extension */ -#define USARTD0 (*(USART_t *) 0x09A0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ -#define USARTD1 (*(USART_t *) 0x09B0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ -#define SPID (*(SPI_t *) 0x09C0) /* Serial Peripheral Interface */ -#define TCE0 (*(TC0_t *) 0x0A00) /* 16-bit Timer/Counter 0 */ -#define TCE2 (*(TC2_t *) 0x0A00) /* 16-bit Timer/Counter type 2 */ -#define TCE1 (*(TC1_t *) 0x0A40) /* 16-bit Timer/Counter 1 */ -#define AWEXE (*(AWEX_t *) 0x0A80) /* Advanced Waveform Extension */ -#define HIRESE (*(HIRES_t *) 0x0A90) /* High-Resolution Extension */ -#define USARTE0 (*(USART_t *) 0x0AA0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ -#define USARTE1 (*(USART_t *) 0x0AB0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ -#define SPIE (*(SPI_t *) 0x0AC0) /* Serial Peripheral Interface */ -#define TCF0 (*(TC0_t *) 0x0B00) /* 16-bit Timer/Counter 0 */ -#define TCF2 (*(TC2_t *) 0x0B00) /* 16-bit Timer/Counter type 2 */ -#define HIRESF (*(HIRES_t *) 0x0B90) /* High-Resolution Extension */ -#define USARTF0 (*(USART_t *) 0x0BA0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ - - -#endif /* !defined (__ASSEMBLER__) */ - - -/* ========== Flattened fully qualified IO register names ========== */ - -/* GPIO - General Purpose IO Registers */ -#define GPIO_GPIOR0 _SFR_MEM8(0x0000) -#define GPIO_GPIOR1 _SFR_MEM8(0x0001) -#define GPIO_GPIOR2 _SFR_MEM8(0x0002) -#define GPIO_GPIOR3 _SFR_MEM8(0x0003) -#define GPIO_GPIOR4 _SFR_MEM8(0x0004) -#define GPIO_GPIOR5 _SFR_MEM8(0x0005) -#define GPIO_GPIOR6 _SFR_MEM8(0x0006) -#define GPIO_GPIOR7 _SFR_MEM8(0x0007) -#define GPIO_GPIOR8 _SFR_MEM8(0x0008) -#define GPIO_GPIOR9 _SFR_MEM8(0x0009) -#define GPIO_GPIORA _SFR_MEM8(0x000A) -#define GPIO_GPIORB _SFR_MEM8(0x000B) -#define GPIO_GPIORC _SFR_MEM8(0x000C) -#define GPIO_GPIORD _SFR_MEM8(0x000D) -#define GPIO_GPIORE _SFR_MEM8(0x000E) -#define GPIO_GPIORF _SFR_MEM8(0x000F) - -/* Deprecated */ -#define GPIO_GPIO0 _SFR_MEM8(0x0000) -#define GPIO_GPIO1 _SFR_MEM8(0x0001) -#define GPIO_GPIO2 _SFR_MEM8(0x0002) -#define GPIO_GPIO3 _SFR_MEM8(0x0003) -#define GPIO_GPIO4 _SFR_MEM8(0x0004) -#define GPIO_GPIO5 _SFR_MEM8(0x0005) -#define GPIO_GPIO6 _SFR_MEM8(0x0006) -#define GPIO_GPIO7 _SFR_MEM8(0x0007) -#define GPIO_GPIO8 _SFR_MEM8(0x0008) -#define GPIO_GPIO9 _SFR_MEM8(0x0009) -#define GPIO_GPIOA _SFR_MEM8(0x000A) -#define GPIO_GPIOB _SFR_MEM8(0x000B) -#define GPIO_GPIOC _SFR_MEM8(0x000C) -#define GPIO_GPIOD _SFR_MEM8(0x000D) -#define GPIO_GPIOE _SFR_MEM8(0x000E) -#define GPIO_GPIOF _SFR_MEM8(0x000F) - -/* NVM_FUSES - Fuses */ -#define FUSE_FUSEBYTE0 _SFR_MEM8(0x0000) -#define FUSE_FUSEBYTE1 _SFR_MEM8(0x0001) -#define FUSE_FUSEBYTE2 _SFR_MEM8(0x0002) -#define FUSE_FUSEBYTE4 _SFR_MEM8(0x0004) -#define FUSE_FUSEBYTE5 _SFR_MEM8(0x0005) - -/* NVM_LOCKBITS - Lock Bits */ -#define LOCKBIT_LOCKBITS _SFR_MEM8(0x0000) - -/* NVM_PROD_SIGNATURES - Production Signatures */ -#define PRODSIGNATURES_RCOSC2M _SFR_MEM8(0x0000) -#define PRODSIGNATURES_RCOSC2MA _SFR_MEM8(0x0001) -#define PRODSIGNATURES_RCOSC32K _SFR_MEM8(0x0002) -#define PRODSIGNATURES_RCOSC32M _SFR_MEM8(0x0003) -#define PRODSIGNATURES_RCOSC32MA _SFR_MEM8(0x0004) -#define PRODSIGNATURES_LOTNUM0 _SFR_MEM8(0x0008) -#define PRODSIGNATURES_LOTNUM1 _SFR_MEM8(0x0009) -#define PRODSIGNATURES_LOTNUM2 _SFR_MEM8(0x000A) -#define PRODSIGNATURES_LOTNUM3 _SFR_MEM8(0x000B) -#define PRODSIGNATURES_LOTNUM4 _SFR_MEM8(0x000C) -#define PRODSIGNATURES_LOTNUM5 _SFR_MEM8(0x000D) -#define PRODSIGNATURES_WAFNUM _SFR_MEM8(0x0010) -#define PRODSIGNATURES_COORDX0 _SFR_MEM8(0x0012) -#define PRODSIGNATURES_COORDX1 _SFR_MEM8(0x0013) -#define PRODSIGNATURES_COORDY0 _SFR_MEM8(0x0014) -#define PRODSIGNATURES_COORDY1 _SFR_MEM8(0x0015) -#define PRODSIGNATURES_USBCAL0 _SFR_MEM8(0x001A) -#define PRODSIGNATURES_USBCAL1 _SFR_MEM8(0x001B) -#define PRODSIGNATURES_USBRCOSC _SFR_MEM8(0x001C) -#define PRODSIGNATURES_USBRCOSCA _SFR_MEM8(0x001D) -#define PRODSIGNATURES_ADCACAL0 _SFR_MEM8(0x0020) -#define PRODSIGNATURES_ADCACAL1 _SFR_MEM8(0x0021) -#define PRODSIGNATURES_ADCBCAL0 _SFR_MEM8(0x0024) -#define PRODSIGNATURES_ADCBCAL1 _SFR_MEM8(0x0025) -#define PRODSIGNATURES_TEMPSENSE0 _SFR_MEM8(0x002E) -#define PRODSIGNATURES_TEMPSENSE1 _SFR_MEM8(0x002F) -#define PRODSIGNATURES_DACA0OFFCAL _SFR_MEM8(0x0030) -#define PRODSIGNATURES_DACA0GAINCAL _SFR_MEM8(0x0031) -#define PRODSIGNATURES_DACB0OFFCAL _SFR_MEM8(0x0032) -#define PRODSIGNATURES_DACB0GAINCAL _SFR_MEM8(0x0033) -#define PRODSIGNATURES_DACA1OFFCAL _SFR_MEM8(0x0034) -#define PRODSIGNATURES_DACA1GAINCAL _SFR_MEM8(0x0035) -#define PRODSIGNATURES_DACB1OFFCAL _SFR_MEM8(0x0036) -#define PRODSIGNATURES_DACB1GAINCAL _SFR_MEM8(0x0037) - -/* VPORT - Virtual Port */ -#define VPORT0_DIR _SFR_MEM8(0x0010) -#define VPORT0_OUT _SFR_MEM8(0x0011) -#define VPORT0_IN _SFR_MEM8(0x0012) -#define VPORT0_INTFLAGS _SFR_MEM8(0x0013) - -/* VPORT - Virtual Port */ -#define VPORT1_DIR _SFR_MEM8(0x0014) -#define VPORT1_OUT _SFR_MEM8(0x0015) -#define VPORT1_IN _SFR_MEM8(0x0016) -#define VPORT1_INTFLAGS _SFR_MEM8(0x0017) - -/* VPORT - Virtual Port */ -#define VPORT2_DIR _SFR_MEM8(0x0018) -#define VPORT2_OUT _SFR_MEM8(0x0019) -#define VPORT2_IN _SFR_MEM8(0x001A) -#define VPORT2_INTFLAGS _SFR_MEM8(0x001B) - -/* VPORT - Virtual Port */ -#define VPORT3_DIR _SFR_MEM8(0x001C) -#define VPORT3_OUT _SFR_MEM8(0x001D) -#define VPORT3_IN _SFR_MEM8(0x001E) -#define VPORT3_INTFLAGS _SFR_MEM8(0x001F) - -/* OCD - On-Chip Debug System */ -#define OCD_OCDR0 _SFR_MEM8(0x002E) -#define OCD_OCDR1 _SFR_MEM8(0x002F) - -/* CPU - CPU registers */ -#define CPU_CCP _SFR_MEM8(0x0034) -#define CPU_RAMPD _SFR_MEM8(0x0038) -#define CPU_RAMPX _SFR_MEM8(0x0039) -#define CPU_RAMPY _SFR_MEM8(0x003A) -#define CPU_RAMPZ _SFR_MEM8(0x003B) -#define CPU_EIND _SFR_MEM8(0x003C) -#define CPU_SPL _SFR_MEM8(0x003D) -#define CPU_SPH _SFR_MEM8(0x003E) -#define CPU_SREG _SFR_MEM8(0x003F) - -/* CLK - Clock System */ -#define CLK_CTRL _SFR_MEM8(0x0040) -#define CLK_PSCTRL _SFR_MEM8(0x0041) -#define CLK_LOCK _SFR_MEM8(0x0042) -#define CLK_RTCCTRL _SFR_MEM8(0x0043) -#define CLK_USBCTRL _SFR_MEM8(0x0044) - -/* SLEEP - Sleep Controller */ -#define SLEEP_CTRL _SFR_MEM8(0x0048) - -/* OSC - Oscillator */ -#define OSC_CTRL _SFR_MEM8(0x0050) -#define OSC_STATUS _SFR_MEM8(0x0051) -#define OSC_XOSCCTRL _SFR_MEM8(0x0052) -#define OSC_XOSCFAIL _SFR_MEM8(0x0053) -#define OSC_RC32KCAL _SFR_MEM8(0x0054) -#define OSC_PLLCTRL _SFR_MEM8(0x0055) -#define OSC_DFLLCTRL _SFR_MEM8(0x0056) - -/* DFLL - DFLL */ -#define DFLLRC32M_CTRL _SFR_MEM8(0x0060) -#define DFLLRC32M_CALA _SFR_MEM8(0x0062) -#define DFLLRC32M_CALB _SFR_MEM8(0x0063) -#define DFLLRC32M_COMP0 _SFR_MEM8(0x0064) -#define DFLLRC32M_COMP1 _SFR_MEM8(0x0065) -#define DFLLRC32M_COMP2 _SFR_MEM8(0x0066) - -/* DFLL - DFLL */ -#define DFLLRC2M_CTRL _SFR_MEM8(0x0068) -#define DFLLRC2M_CALA _SFR_MEM8(0x006A) -#define DFLLRC2M_CALB _SFR_MEM8(0x006B) -#define DFLLRC2M_COMP0 _SFR_MEM8(0x006C) -#define DFLLRC2M_COMP1 _SFR_MEM8(0x006D) -#define DFLLRC2M_COMP2 _SFR_MEM8(0x006E) - -/* PR - Power Reduction */ -#define PR_PRGEN _SFR_MEM8(0x0070) -#define PR_PRPA _SFR_MEM8(0x0071) -#define PR_PRPB _SFR_MEM8(0x0072) -#define PR_PRPC _SFR_MEM8(0x0073) -#define PR_PRPD _SFR_MEM8(0x0074) -#define PR_PRPE _SFR_MEM8(0x0075) -#define PR_PRPF _SFR_MEM8(0x0076) - -/* RST - Reset */ -#define RST_STATUS _SFR_MEM8(0x0078) -#define RST_CTRL _SFR_MEM8(0x0079) - -/* WDT - Watch-Dog Timer */ -#define WDT_CTRL _SFR_MEM8(0x0080) -#define WDT_WINCTRL _SFR_MEM8(0x0081) -#define WDT_STATUS _SFR_MEM8(0x0082) - -/* MCU - MCU Control */ -#define MCU_DEVID0 _SFR_MEM8(0x0090) -#define MCU_DEVID1 _SFR_MEM8(0x0091) -#define MCU_DEVID2 _SFR_MEM8(0x0092) -#define MCU_REVID _SFR_MEM8(0x0093) -#define MCU_JTAGUID _SFR_MEM8(0x0094) -#define MCU_MCUCR _SFR_MEM8(0x0096) -#define MCU_ANAINIT _SFR_MEM8(0x0097) -#define MCU_EVSYSLOCK _SFR_MEM8(0x0098) -#define MCU_AWEXLOCK _SFR_MEM8(0x0099) - -/* PMIC - Programmable Multi-level Interrupt Controller */ -#define PMIC_STATUS _SFR_MEM8(0x00A0) -#define PMIC_INTPRI _SFR_MEM8(0x00A1) -#define PMIC_CTRL _SFR_MEM8(0x00A2) - -/* PORTCFG - I/O port Configuration */ -#define PORTCFG_MPCMASK _SFR_MEM8(0x00B0) -#define PORTCFG_VPCTRLA _SFR_MEM8(0x00B2) -#define PORTCFG_VPCTRLB _SFR_MEM8(0x00B3) -#define PORTCFG_CLKEVOUT _SFR_MEM8(0x00B4) -#define PORTCFG_EBIOUT _SFR_MEM8(0x00B5) -#define PORTCFG_EVOUTSEL _SFR_MEM8(0x00B6) - -/* AES - AES Module */ -#define AES_CTRL _SFR_MEM8(0x00C0) -#define AES_STATUS _SFR_MEM8(0x00C1) -#define AES_STATE _SFR_MEM8(0x00C2) -#define AES_KEY _SFR_MEM8(0x00C3) -#define AES_INTCTRL _SFR_MEM8(0x00C4) - -/* CRC - Cyclic Redundancy Checker */ -#define CRC_CTRL _SFR_MEM8(0x00D0) -#define CRC_STATUS _SFR_MEM8(0x00D1) -#define CRC_DATAIN _SFR_MEM8(0x00D3) -#define CRC_CHECKSUM0 _SFR_MEM8(0x00D4) -#define CRC_CHECKSUM1 _SFR_MEM8(0x00D5) -#define CRC_CHECKSUM2 _SFR_MEM8(0x00D6) -#define CRC_CHECKSUM3 _SFR_MEM8(0x00D7) - -/* DMA - DMA Controller */ -#define DMA_CTRL _SFR_MEM8(0x0100) -#define DMA_INTFLAGS _SFR_MEM8(0x0103) -#define DMA_STATUS _SFR_MEM8(0x0104) -#define DMA_TEMP _SFR_MEM16(0x0106) -#define DMA_CH0_CTRLA _SFR_MEM8(0x0110) -#define DMA_CH0_CTRLB _SFR_MEM8(0x0111) -#define DMA_CH0_ADDRCTRL _SFR_MEM8(0x0112) -#define DMA_CH0_TRIGSRC _SFR_MEM8(0x0113) -#define DMA_CH0_TRFCNT _SFR_MEM16(0x0114) -#define DMA_CH0_REPCNT _SFR_MEM8(0x0116) -#define DMA_CH0_SRCADDR0 _SFR_MEM8(0x0118) -#define DMA_CH0_SRCADDR1 _SFR_MEM8(0x0119) -#define DMA_CH0_SRCADDR2 _SFR_MEM8(0x011A) -#define DMA_CH0_DESTADDR0 _SFR_MEM8(0x011C) -#define DMA_CH0_DESTADDR1 _SFR_MEM8(0x011D) -#define DMA_CH0_DESTADDR2 _SFR_MEM8(0x011E) -#define DMA_CH1_CTRLA _SFR_MEM8(0x0120) -#define DMA_CH1_CTRLB _SFR_MEM8(0x0121) -#define DMA_CH1_ADDRCTRL _SFR_MEM8(0x0122) -#define DMA_CH1_TRIGSRC _SFR_MEM8(0x0123) -#define DMA_CH1_TRFCNT _SFR_MEM16(0x0124) -#define DMA_CH1_REPCNT _SFR_MEM8(0x0126) -#define DMA_CH1_SRCADDR0 _SFR_MEM8(0x0128) -#define DMA_CH1_SRCADDR1 _SFR_MEM8(0x0129) -#define DMA_CH1_SRCADDR2 _SFR_MEM8(0x012A) -#define DMA_CH1_DESTADDR0 _SFR_MEM8(0x012C) -#define DMA_CH1_DESTADDR1 _SFR_MEM8(0x012D) -#define DMA_CH1_DESTADDR2 _SFR_MEM8(0x012E) -#define DMA_CH2_CTRLA _SFR_MEM8(0x0130) -#define DMA_CH2_CTRLB _SFR_MEM8(0x0131) -#define DMA_CH2_ADDRCTRL _SFR_MEM8(0x0132) -#define DMA_CH2_TRIGSRC _SFR_MEM8(0x0133) -#define DMA_CH2_TRFCNT _SFR_MEM16(0x0134) -#define DMA_CH2_REPCNT _SFR_MEM8(0x0136) -#define DMA_CH2_SRCADDR0 _SFR_MEM8(0x0138) -#define DMA_CH2_SRCADDR1 _SFR_MEM8(0x0139) -#define DMA_CH2_SRCADDR2 _SFR_MEM8(0x013A) -#define DMA_CH2_DESTADDR0 _SFR_MEM8(0x013C) -#define DMA_CH2_DESTADDR1 _SFR_MEM8(0x013D) -#define DMA_CH2_DESTADDR2 _SFR_MEM8(0x013E) -#define DMA_CH3_CTRLA _SFR_MEM8(0x0140) -#define DMA_CH3_CTRLB _SFR_MEM8(0x0141) -#define DMA_CH3_ADDRCTRL _SFR_MEM8(0x0142) -#define DMA_CH3_TRIGSRC _SFR_MEM8(0x0143) -#define DMA_CH3_TRFCNT _SFR_MEM16(0x0144) -#define DMA_CH3_REPCNT _SFR_MEM8(0x0146) -#define DMA_CH3_SRCADDR0 _SFR_MEM8(0x0148) -#define DMA_CH3_SRCADDR1 _SFR_MEM8(0x0149) -#define DMA_CH3_SRCADDR2 _SFR_MEM8(0x014A) -#define DMA_CH3_DESTADDR0 _SFR_MEM8(0x014C) -#define DMA_CH3_DESTADDR1 _SFR_MEM8(0x014D) -#define DMA_CH3_DESTADDR2 _SFR_MEM8(0x014E) - -/* EVSYS - Event System */ -#define EVSYS_CH0MUX _SFR_MEM8(0x0180) -#define EVSYS_CH1MUX _SFR_MEM8(0x0181) -#define EVSYS_CH2MUX _SFR_MEM8(0x0182) -#define EVSYS_CH3MUX _SFR_MEM8(0x0183) -#define EVSYS_CH4MUX _SFR_MEM8(0x0184) -#define EVSYS_CH5MUX _SFR_MEM8(0x0185) -#define EVSYS_CH6MUX _SFR_MEM8(0x0186) -#define EVSYS_CH7MUX _SFR_MEM8(0x0187) -#define EVSYS_CH0CTRL _SFR_MEM8(0x0188) -#define EVSYS_CH1CTRL _SFR_MEM8(0x0189) -#define EVSYS_CH2CTRL _SFR_MEM8(0x018A) -#define EVSYS_CH3CTRL _SFR_MEM8(0x018B) -#define EVSYS_CH4CTRL _SFR_MEM8(0x018C) -#define EVSYS_CH5CTRL _SFR_MEM8(0x018D) -#define EVSYS_CH6CTRL _SFR_MEM8(0x018E) -#define EVSYS_CH7CTRL _SFR_MEM8(0x018F) -#define EVSYS_STROBE _SFR_MEM8(0x0190) -#define EVSYS_DATA _SFR_MEM8(0x0191) - -/* NVM - Non-volatile Memory Controller */ -#define NVM_ADDR0 _SFR_MEM8(0x01C0) -#define NVM_ADDR1 _SFR_MEM8(0x01C1) -#define NVM_ADDR2 _SFR_MEM8(0x01C2) -#define NVM_DATA0 _SFR_MEM8(0x01C4) -#define NVM_DATA1 _SFR_MEM8(0x01C5) -#define NVM_DATA2 _SFR_MEM8(0x01C6) -#define NVM_CMD _SFR_MEM8(0x01CA) -#define NVM_CTRLA _SFR_MEM8(0x01CB) -#define NVM_CTRLB _SFR_MEM8(0x01CC) -#define NVM_INTCTRL _SFR_MEM8(0x01CD) -#define NVM_STATUS _SFR_MEM8(0x01CF) -#define NVM_LOCKBITS _SFR_MEM8(0x01D0) - -/* ADC - Analog-to-Digital Converter */ -#define ADCA_CTRLA _SFR_MEM8(0x0200) -#define ADCA_CTRLB _SFR_MEM8(0x0201) -#define ADCA_REFCTRL _SFR_MEM8(0x0202) -#define ADCA_EVCTRL _SFR_MEM8(0x0203) -#define ADCA_PRESCALER _SFR_MEM8(0x0204) -#define ADCA_INTFLAGS _SFR_MEM8(0x0206) -#define ADCA_TEMP _SFR_MEM8(0x0207) -#define ADCA_CAL _SFR_MEM16(0x020C) -#define ADCA_CH0RES _SFR_MEM16(0x0210) -#define ADCA_CH1RES _SFR_MEM16(0x0212) -#define ADCA_CH2RES _SFR_MEM16(0x0214) -#define ADCA_CH3RES _SFR_MEM16(0x0216) -#define ADCA_CMP _SFR_MEM16(0x0218) -#define ADCA_CH0_CTRL _SFR_MEM8(0x0220) -#define ADCA_CH0_MUXCTRL _SFR_MEM8(0x0221) -#define ADCA_CH0_INTCTRL _SFR_MEM8(0x0222) -#define ADCA_CH0_INTFLAGS _SFR_MEM8(0x0223) -#define ADCA_CH0_RES _SFR_MEM16(0x0224) -#define ADCA_CH0_SCAN _SFR_MEM8(0x0226) -#define ADCA_CH1_CTRL _SFR_MEM8(0x0228) -#define ADCA_CH1_MUXCTRL _SFR_MEM8(0x0229) -#define ADCA_CH1_INTCTRL _SFR_MEM8(0x022A) -#define ADCA_CH1_INTFLAGS _SFR_MEM8(0x022B) -#define ADCA_CH1_RES _SFR_MEM16(0x022C) -#define ADCA_CH1_SCAN _SFR_MEM8(0x022E) -#define ADCA_CH2_CTRL _SFR_MEM8(0x0230) -#define ADCA_CH2_MUXCTRL _SFR_MEM8(0x0231) -#define ADCA_CH2_INTCTRL _SFR_MEM8(0x0232) -#define ADCA_CH2_INTFLAGS _SFR_MEM8(0x0233) -#define ADCA_CH2_RES _SFR_MEM16(0x0234) -#define ADCA_CH2_SCAN _SFR_MEM8(0x0236) -#define ADCA_CH3_CTRL _SFR_MEM8(0x0238) -#define ADCA_CH3_MUXCTRL _SFR_MEM8(0x0239) -#define ADCA_CH3_INTCTRL _SFR_MEM8(0x023A) -#define ADCA_CH3_INTFLAGS _SFR_MEM8(0x023B) -#define ADCA_CH3_RES _SFR_MEM16(0x023C) -#define ADCA_CH3_SCAN _SFR_MEM8(0x023E) - -/* ADC - Analog-to-Digital Converter */ -#define ADCB_CTRLA _SFR_MEM8(0x0240) -#define ADCB_CTRLB _SFR_MEM8(0x0241) -#define ADCB_REFCTRL _SFR_MEM8(0x0242) -#define ADCB_EVCTRL _SFR_MEM8(0x0243) -#define ADCB_PRESCALER _SFR_MEM8(0x0244) -#define ADCB_INTFLAGS _SFR_MEM8(0x0246) -#define ADCB_TEMP _SFR_MEM8(0x0247) -#define ADCB_CAL _SFR_MEM16(0x024C) -#define ADCB_CH0RES _SFR_MEM16(0x0250) -#define ADCB_CH1RES _SFR_MEM16(0x0252) -#define ADCB_CH2RES _SFR_MEM16(0x0254) -#define ADCB_CH3RES _SFR_MEM16(0x0256) -#define ADCB_CMP _SFR_MEM16(0x0258) -#define ADCB_CH0_CTRL _SFR_MEM8(0x0260) -#define ADCB_CH0_MUXCTRL _SFR_MEM8(0x0261) -#define ADCB_CH0_INTCTRL _SFR_MEM8(0x0262) -#define ADCB_CH0_INTFLAGS _SFR_MEM8(0x0263) -#define ADCB_CH0_RES _SFR_MEM16(0x0264) -#define ADCB_CH0_SCAN _SFR_MEM8(0x0266) -#define ADCB_CH1_CTRL _SFR_MEM8(0x0268) -#define ADCB_CH1_MUXCTRL _SFR_MEM8(0x0269) -#define ADCB_CH1_INTCTRL _SFR_MEM8(0x026A) -#define ADCB_CH1_INTFLAGS _SFR_MEM8(0x026B) -#define ADCB_CH1_RES _SFR_MEM16(0x026C) -#define ADCB_CH1_SCAN _SFR_MEM8(0x026E) -#define ADCB_CH2_CTRL _SFR_MEM8(0x0270) -#define ADCB_CH2_MUXCTRL _SFR_MEM8(0x0271) -#define ADCB_CH2_INTCTRL _SFR_MEM8(0x0272) -#define ADCB_CH2_INTFLAGS _SFR_MEM8(0x0273) -#define ADCB_CH2_RES _SFR_MEM16(0x0274) -#define ADCB_CH2_SCAN _SFR_MEM8(0x0276) -#define ADCB_CH3_CTRL _SFR_MEM8(0x0278) -#define ADCB_CH3_MUXCTRL _SFR_MEM8(0x0279) -#define ADCB_CH3_INTCTRL _SFR_MEM8(0x027A) -#define ADCB_CH3_INTFLAGS _SFR_MEM8(0x027B) -#define ADCB_CH3_RES _SFR_MEM16(0x027C) -#define ADCB_CH3_SCAN _SFR_MEM8(0x027E) - -/* DAC - Digital-to-Analog Converter */ -#define DACB_CTRLA _SFR_MEM8(0x0320) -#define DACB_CTRLB _SFR_MEM8(0x0321) -#define DACB_CTRLC _SFR_MEM8(0x0322) -#define DACB_EVCTRL _SFR_MEM8(0x0323) -#define DACB_STATUS _SFR_MEM8(0x0325) -#define DACB_CH0GAINCAL _SFR_MEM8(0x0328) -#define DACB_CH0OFFSETCAL _SFR_MEM8(0x0329) -#define DACB_CH1GAINCAL _SFR_MEM8(0x032A) -#define DACB_CH1OFFSETCAL _SFR_MEM8(0x032B) -#define DACB_CH0DATA _SFR_MEM16(0x0338) -#define DACB_CH1DATA _SFR_MEM16(0x033A) - -/* AC - Analog Comparator */ -#define ACA_AC0CTRL _SFR_MEM8(0x0380) -#define ACA_AC1CTRL _SFR_MEM8(0x0381) -#define ACA_AC0MUXCTRL _SFR_MEM8(0x0382) -#define ACA_AC1MUXCTRL _SFR_MEM8(0x0383) -#define ACA_CTRLA _SFR_MEM8(0x0384) -#define ACA_CTRLB _SFR_MEM8(0x0385) -#define ACA_WINCTRL _SFR_MEM8(0x0386) -#define ACA_STATUS _SFR_MEM8(0x0387) - -/* AC - Analog Comparator */ -#define ACB_AC0CTRL _SFR_MEM8(0x0390) -#define ACB_AC1CTRL _SFR_MEM8(0x0391) -#define ACB_AC0MUXCTRL _SFR_MEM8(0x0392) -#define ACB_AC1MUXCTRL _SFR_MEM8(0x0393) -#define ACB_CTRLA _SFR_MEM8(0x0394) -#define ACB_CTRLB _SFR_MEM8(0x0395) -#define ACB_WINCTRL _SFR_MEM8(0x0396) -#define ACB_STATUS _SFR_MEM8(0x0397) - -/* RTC - Real-Time Counter */ -#define RTC_CTRL _SFR_MEM8(0x0400) -#define RTC_STATUS _SFR_MEM8(0x0401) -#define RTC_INTCTRL _SFR_MEM8(0x0402) -#define RTC_INTFLAGS _SFR_MEM8(0x0403) -#define RTC_TEMP _SFR_MEM8(0x0404) -#define RTC_CNT _SFR_MEM16(0x0408) -#define RTC_PER _SFR_MEM16(0x040A) -#define RTC_COMP _SFR_MEM16(0x040C) - -/* TWI - Two-Wire Interface */ -#define TWIC_CTRL _SFR_MEM8(0x0480) -#define TWIC_MASTER_CTRLA _SFR_MEM8(0x0481) -#define TWIC_MASTER_CTRLB _SFR_MEM8(0x0482) -#define TWIC_MASTER_CTRLC _SFR_MEM8(0x0483) -#define TWIC_MASTER_STATUS _SFR_MEM8(0x0484) -#define TWIC_MASTER_BAUD _SFR_MEM8(0x0485) -#define TWIC_MASTER_ADDR _SFR_MEM8(0x0486) -#define TWIC_MASTER_DATA _SFR_MEM8(0x0487) -#define TWIC_SLAVE_CTRLA _SFR_MEM8(0x0488) -#define TWIC_SLAVE_CTRLB _SFR_MEM8(0x0489) -#define TWIC_SLAVE_STATUS _SFR_MEM8(0x048A) -#define TWIC_SLAVE_ADDR _SFR_MEM8(0x048B) -#define TWIC_SLAVE_DATA _SFR_MEM8(0x048C) -#define TWIC_SLAVE_ADDRMASK _SFR_MEM8(0x048D) - -/* TWI - Two-Wire Interface */ -#define TWIE_CTRL _SFR_MEM8(0x04A0) -#define TWIE_MASTER_CTRLA _SFR_MEM8(0x04A1) -#define TWIE_MASTER_CTRLB _SFR_MEM8(0x04A2) -#define TWIE_MASTER_CTRLC _SFR_MEM8(0x04A3) -#define TWIE_MASTER_STATUS _SFR_MEM8(0x04A4) -#define TWIE_MASTER_BAUD _SFR_MEM8(0x04A5) -#define TWIE_MASTER_ADDR _SFR_MEM8(0x04A6) -#define TWIE_MASTER_DATA _SFR_MEM8(0x04A7) -#define TWIE_SLAVE_CTRLA _SFR_MEM8(0x04A8) -#define TWIE_SLAVE_CTRLB _SFR_MEM8(0x04A9) -#define TWIE_SLAVE_STATUS _SFR_MEM8(0x04AA) -#define TWIE_SLAVE_ADDR _SFR_MEM8(0x04AB) -#define TWIE_SLAVE_DATA _SFR_MEM8(0x04AC) -#define TWIE_SLAVE_ADDRMASK _SFR_MEM8(0x04AD) - -/* USB - Universal Serial Bus */ -#define USB_CTRLA _SFR_MEM8(0x04C0) -#define USB_CTRLB _SFR_MEM8(0x04C1) -#define USB_STATUS _SFR_MEM8(0x04C2) -#define USB_ADDR _SFR_MEM8(0x04C3) -#define USB_FIFOWP _SFR_MEM8(0x04C4) -#define USB_FIFORP _SFR_MEM8(0x04C5) -#define USB_EPPTR _SFR_MEM16(0x04C6) -#define USB_INTCTRLA _SFR_MEM8(0x04C8) -#define USB_INTCTRLB _SFR_MEM8(0x04C9) -#define USB_INTFLAGSACLR _SFR_MEM8(0x04CA) -#define USB_INTFLAGSASET _SFR_MEM8(0x04CB) -#define USB_INTFLAGSBCLR _SFR_MEM8(0x04CC) -#define USB_INTFLAGSBSET _SFR_MEM8(0x04CD) -#define USB_CAL0 _SFR_MEM8(0x04FA) -#define USB_CAL1 _SFR_MEM8(0x04FB) - -/* PORT - I/O Ports */ -#define PORTA_DIR _SFR_MEM8(0x0600) -#define PORTA_DIRSET _SFR_MEM8(0x0601) -#define PORTA_DIRCLR _SFR_MEM8(0x0602) -#define PORTA_DIRTGL _SFR_MEM8(0x0603) -#define PORTA_OUT _SFR_MEM8(0x0604) -#define PORTA_OUTSET _SFR_MEM8(0x0605) -#define PORTA_OUTCLR _SFR_MEM8(0x0606) -#define PORTA_OUTTGL _SFR_MEM8(0x0607) -#define PORTA_IN _SFR_MEM8(0x0608) -#define PORTA_INTCTRL _SFR_MEM8(0x0609) -#define PORTA_INT0MASK _SFR_MEM8(0x060A) -#define PORTA_INT1MASK _SFR_MEM8(0x060B) -#define PORTA_INTFLAGS _SFR_MEM8(0x060C) -#define PORTA_REMAP _SFR_MEM8(0x060E) -#define PORTA_PIN0CTRL _SFR_MEM8(0x0610) -#define PORTA_PIN1CTRL _SFR_MEM8(0x0611) -#define PORTA_PIN2CTRL _SFR_MEM8(0x0612) -#define PORTA_PIN3CTRL _SFR_MEM8(0x0613) -#define PORTA_PIN4CTRL _SFR_MEM8(0x0614) -#define PORTA_PIN5CTRL _SFR_MEM8(0x0615) -#define PORTA_PIN6CTRL _SFR_MEM8(0x0616) -#define PORTA_PIN7CTRL _SFR_MEM8(0x0617) - -/* PORT - I/O Ports */ -#define PORTB_DIR _SFR_MEM8(0x0620) -#define PORTB_DIRSET _SFR_MEM8(0x0621) -#define PORTB_DIRCLR _SFR_MEM8(0x0622) -#define PORTB_DIRTGL _SFR_MEM8(0x0623) -#define PORTB_OUT _SFR_MEM8(0x0624) -#define PORTB_OUTSET _SFR_MEM8(0x0625) -#define PORTB_OUTCLR _SFR_MEM8(0x0626) -#define PORTB_OUTTGL _SFR_MEM8(0x0627) -#define PORTB_IN _SFR_MEM8(0x0628) -#define PORTB_INTCTRL _SFR_MEM8(0x0629) -#define PORTB_INT0MASK _SFR_MEM8(0x062A) -#define PORTB_INT1MASK _SFR_MEM8(0x062B) -#define PORTB_INTFLAGS _SFR_MEM8(0x062C) -#define PORTB_REMAP _SFR_MEM8(0x062E) -#define PORTB_PIN0CTRL _SFR_MEM8(0x0630) -#define PORTB_PIN1CTRL _SFR_MEM8(0x0631) -#define PORTB_PIN2CTRL _SFR_MEM8(0x0632) -#define PORTB_PIN3CTRL _SFR_MEM8(0x0633) -#define PORTB_PIN4CTRL _SFR_MEM8(0x0634) -#define PORTB_PIN5CTRL _SFR_MEM8(0x0635) -#define PORTB_PIN6CTRL _SFR_MEM8(0x0636) -#define PORTB_PIN7CTRL _SFR_MEM8(0x0637) - -/* PORT - I/O Ports */ -#define PORTC_DIR _SFR_MEM8(0x0640) -#define PORTC_DIRSET _SFR_MEM8(0x0641) -#define PORTC_DIRCLR _SFR_MEM8(0x0642) -#define PORTC_DIRTGL _SFR_MEM8(0x0643) -#define PORTC_OUT _SFR_MEM8(0x0644) -#define PORTC_OUTSET _SFR_MEM8(0x0645) -#define PORTC_OUTCLR _SFR_MEM8(0x0646) -#define PORTC_OUTTGL _SFR_MEM8(0x0647) -#define PORTC_IN _SFR_MEM8(0x0648) -#define PORTC_INTCTRL _SFR_MEM8(0x0649) -#define PORTC_INT0MASK _SFR_MEM8(0x064A) -#define PORTC_INT1MASK _SFR_MEM8(0x064B) -#define PORTC_INTFLAGS _SFR_MEM8(0x064C) -#define PORTC_REMAP _SFR_MEM8(0x064E) -#define PORTC_PIN0CTRL _SFR_MEM8(0x0650) -#define PORTC_PIN1CTRL _SFR_MEM8(0x0651) -#define PORTC_PIN2CTRL _SFR_MEM8(0x0652) -#define PORTC_PIN3CTRL _SFR_MEM8(0x0653) -#define PORTC_PIN4CTRL _SFR_MEM8(0x0654) -#define PORTC_PIN5CTRL _SFR_MEM8(0x0655) -#define PORTC_PIN6CTRL _SFR_MEM8(0x0656) -#define PORTC_PIN7CTRL _SFR_MEM8(0x0657) - -/* PORT - I/O Ports */ -#define PORTD_DIR _SFR_MEM8(0x0660) -#define PORTD_DIRSET _SFR_MEM8(0x0661) -#define PORTD_DIRCLR _SFR_MEM8(0x0662) -#define PORTD_DIRTGL _SFR_MEM8(0x0663) -#define PORTD_OUT _SFR_MEM8(0x0664) -#define PORTD_OUTSET _SFR_MEM8(0x0665) -#define PORTD_OUTCLR _SFR_MEM8(0x0666) -#define PORTD_OUTTGL _SFR_MEM8(0x0667) -#define PORTD_IN _SFR_MEM8(0x0668) -#define PORTD_INTCTRL _SFR_MEM8(0x0669) -#define PORTD_INT0MASK _SFR_MEM8(0x066A) -#define PORTD_INT1MASK _SFR_MEM8(0x066B) -#define PORTD_INTFLAGS _SFR_MEM8(0x066C) -#define PORTD_REMAP _SFR_MEM8(0x066E) -#define PORTD_PIN0CTRL _SFR_MEM8(0x0670) -#define PORTD_PIN1CTRL _SFR_MEM8(0x0671) -#define PORTD_PIN2CTRL _SFR_MEM8(0x0672) -#define PORTD_PIN3CTRL _SFR_MEM8(0x0673) -#define PORTD_PIN4CTRL _SFR_MEM8(0x0674) -#define PORTD_PIN5CTRL _SFR_MEM8(0x0675) -#define PORTD_PIN6CTRL _SFR_MEM8(0x0676) -#define PORTD_PIN7CTRL _SFR_MEM8(0x0677) - -/* PORT - I/O Ports */ -#define PORTE_DIR _SFR_MEM8(0x0680) -#define PORTE_DIRSET _SFR_MEM8(0x0681) -#define PORTE_DIRCLR _SFR_MEM8(0x0682) -#define PORTE_DIRTGL _SFR_MEM8(0x0683) -#define PORTE_OUT _SFR_MEM8(0x0684) -#define PORTE_OUTSET _SFR_MEM8(0x0685) -#define PORTE_OUTCLR _SFR_MEM8(0x0686) -#define PORTE_OUTTGL _SFR_MEM8(0x0687) -#define PORTE_IN _SFR_MEM8(0x0688) -#define PORTE_INTCTRL _SFR_MEM8(0x0689) -#define PORTE_INT0MASK _SFR_MEM8(0x068A) -#define PORTE_INT1MASK _SFR_MEM8(0x068B) -#define PORTE_INTFLAGS _SFR_MEM8(0x068C) -#define PORTE_REMAP _SFR_MEM8(0x068E) -#define PORTE_PIN0CTRL _SFR_MEM8(0x0690) -#define PORTE_PIN1CTRL _SFR_MEM8(0x0691) -#define PORTE_PIN2CTRL _SFR_MEM8(0x0692) -#define PORTE_PIN3CTRL _SFR_MEM8(0x0693) -#define PORTE_PIN4CTRL _SFR_MEM8(0x0694) -#define PORTE_PIN5CTRL _SFR_MEM8(0x0695) -#define PORTE_PIN6CTRL _SFR_MEM8(0x0696) -#define PORTE_PIN7CTRL _SFR_MEM8(0x0697) - -/* PORT - I/O Ports */ -#define PORTF_DIR _SFR_MEM8(0x06A0) -#define PORTF_DIRSET _SFR_MEM8(0x06A1) -#define PORTF_DIRCLR _SFR_MEM8(0x06A2) -#define PORTF_DIRTGL _SFR_MEM8(0x06A3) -#define PORTF_OUT _SFR_MEM8(0x06A4) -#define PORTF_OUTSET _SFR_MEM8(0x06A5) -#define PORTF_OUTCLR _SFR_MEM8(0x06A6) -#define PORTF_OUTTGL _SFR_MEM8(0x06A7) -#define PORTF_IN _SFR_MEM8(0x06A8) -#define PORTF_INTCTRL _SFR_MEM8(0x06A9) -#define PORTF_INT0MASK _SFR_MEM8(0x06AA) -#define PORTF_INT1MASK _SFR_MEM8(0x06AB) -#define PORTF_INTFLAGS _SFR_MEM8(0x06AC) -#define PORTF_REMAP _SFR_MEM8(0x06AE) -#define PORTF_PIN0CTRL _SFR_MEM8(0x06B0) -#define PORTF_PIN1CTRL _SFR_MEM8(0x06B1) -#define PORTF_PIN2CTRL _SFR_MEM8(0x06B2) -#define PORTF_PIN3CTRL _SFR_MEM8(0x06B3) -#define PORTF_PIN4CTRL _SFR_MEM8(0x06B4) -#define PORTF_PIN5CTRL _SFR_MEM8(0x06B5) -#define PORTF_PIN6CTRL _SFR_MEM8(0x06B6) -#define PORTF_PIN7CTRL _SFR_MEM8(0x06B7) - -/* PORT - I/O Ports */ -#define PORTR_DIR _SFR_MEM8(0x07E0) -#define PORTR_DIRSET _SFR_MEM8(0x07E1) -#define PORTR_DIRCLR _SFR_MEM8(0x07E2) -#define PORTR_DIRTGL _SFR_MEM8(0x07E3) -#define PORTR_OUT _SFR_MEM8(0x07E4) -#define PORTR_OUTSET _SFR_MEM8(0x07E5) -#define PORTR_OUTCLR _SFR_MEM8(0x07E6) -#define PORTR_OUTTGL _SFR_MEM8(0x07E7) -#define PORTR_IN _SFR_MEM8(0x07E8) -#define PORTR_INTCTRL _SFR_MEM8(0x07E9) -#define PORTR_INT0MASK _SFR_MEM8(0x07EA) -#define PORTR_INT1MASK _SFR_MEM8(0x07EB) -#define PORTR_INTFLAGS _SFR_MEM8(0x07EC) -#define PORTR_REMAP _SFR_MEM8(0x07EE) -#define PORTR_PIN0CTRL _SFR_MEM8(0x07F0) -#define PORTR_PIN1CTRL _SFR_MEM8(0x07F1) -#define PORTR_PIN2CTRL _SFR_MEM8(0x07F2) -#define PORTR_PIN3CTRL _SFR_MEM8(0x07F3) -#define PORTR_PIN4CTRL _SFR_MEM8(0x07F4) -#define PORTR_PIN5CTRL _SFR_MEM8(0x07F5) -#define PORTR_PIN6CTRL _SFR_MEM8(0x07F6) -#define PORTR_PIN7CTRL _SFR_MEM8(0x07F7) - -/* TC0 - 16-bit Timer/Counter 0 */ -#define TCC0_CTRLA _SFR_MEM8(0x0800) -#define TCC0_CTRLB _SFR_MEM8(0x0801) -#define TCC0_CTRLC _SFR_MEM8(0x0802) -#define TCC0_CTRLD _SFR_MEM8(0x0803) -#define TCC0_CTRLE _SFR_MEM8(0x0804) -#define TCC0_INTCTRLA _SFR_MEM8(0x0806) -#define TCC0_INTCTRLB _SFR_MEM8(0x0807) -#define TCC0_CTRLFCLR _SFR_MEM8(0x0808) -#define TCC0_CTRLFSET _SFR_MEM8(0x0809) -#define TCC0_CTRLGCLR _SFR_MEM8(0x080A) -#define TCC0_CTRLGSET _SFR_MEM8(0x080B) -#define TCC0_INTFLAGS _SFR_MEM8(0x080C) -#define TCC0_TEMP _SFR_MEM8(0x080F) -#define TCC0_CNT _SFR_MEM16(0x0820) -#define TCC0_PER _SFR_MEM16(0x0826) -#define TCC0_CCA _SFR_MEM16(0x0828) -#define TCC0_CCB _SFR_MEM16(0x082A) -#define TCC0_CCC _SFR_MEM16(0x082C) -#define TCC0_CCD _SFR_MEM16(0x082E) -#define TCC0_PERBUF _SFR_MEM16(0x0836) -#define TCC0_CCABUF _SFR_MEM16(0x0838) -#define TCC0_CCBBUF _SFR_MEM16(0x083A) -#define TCC0_CCCBUF _SFR_MEM16(0x083C) -#define TCC0_CCDBUF _SFR_MEM16(0x083E) - -/* TC2 - 16-bit Timer/Counter type 2 */ -#define TCC2_CTRLA _SFR_MEM8(0x0800) -#define TCC2_CTRLB _SFR_MEM8(0x0801) -#define TCC2_CTRLC _SFR_MEM8(0x0802) -#define TCC2_CTRLE _SFR_MEM8(0x0804) -#define TCC2_INTCTRLA _SFR_MEM8(0x0806) -#define TCC2_INTCTRLB _SFR_MEM8(0x0807) -#define TCC2_CTRLF _SFR_MEM8(0x0809) -#define TCC2_INTFLAGS _SFR_MEM8(0x080C) -#define TCC2_LCNT _SFR_MEM8(0x0820) -#define TCC2_HCNT _SFR_MEM8(0x0821) -#define TCC2_LPER _SFR_MEM8(0x0826) -#define TCC2_HPER _SFR_MEM8(0x0827) -#define TCC2_LCMPA _SFR_MEM8(0x0828) -#define TCC2_HCMPA _SFR_MEM8(0x0829) -#define TCC2_LCMPB _SFR_MEM8(0x082A) -#define TCC2_HCMPB _SFR_MEM8(0x082B) -#define TCC2_LCMPC _SFR_MEM8(0x082C) -#define TCC2_HCMPC _SFR_MEM8(0x082D) -#define TCC2_LCMPD _SFR_MEM8(0x082E) -#define TCC2_HCMPD _SFR_MEM8(0x082F) - -/* TC1 - 16-bit Timer/Counter 1 */ -#define TCC1_CTRLA _SFR_MEM8(0x0840) -#define TCC1_CTRLB _SFR_MEM8(0x0841) -#define TCC1_CTRLC _SFR_MEM8(0x0842) -#define TCC1_CTRLD _SFR_MEM8(0x0843) -#define TCC1_CTRLE _SFR_MEM8(0x0844) -#define TCC1_INTCTRLA _SFR_MEM8(0x0846) -#define TCC1_INTCTRLB _SFR_MEM8(0x0847) -#define TCC1_CTRLFCLR _SFR_MEM8(0x0848) -#define TCC1_CTRLFSET _SFR_MEM8(0x0849) -#define TCC1_CTRLGCLR _SFR_MEM8(0x084A) -#define TCC1_CTRLGSET _SFR_MEM8(0x084B) -#define TCC1_INTFLAGS _SFR_MEM8(0x084C) -#define TCC1_TEMP _SFR_MEM8(0x084F) -#define TCC1_CNT _SFR_MEM16(0x0860) -#define TCC1_PER _SFR_MEM16(0x0866) -#define TCC1_CCA _SFR_MEM16(0x0868) -#define TCC1_CCB _SFR_MEM16(0x086A) -#define TCC1_PERBUF _SFR_MEM16(0x0876) -#define TCC1_CCABUF _SFR_MEM16(0x0878) -#define TCC1_CCBBUF _SFR_MEM16(0x087A) - -/* AWEX - Advanced Waveform Extension */ -#define AWEXC_CTRL _SFR_MEM8(0x0880) -#define AWEXC_FDEMASK _SFR_MEM8(0x0882) -#define AWEXC_FDCTRL _SFR_MEM8(0x0883) -#define AWEXC_STATUS _SFR_MEM8(0x0884) -#define AWEXC_STATUSSET _SFR_MEM8(0x0885) -#define AWEXC_DTBOTH _SFR_MEM8(0x0886) -#define AWEXC_DTBOTHBUF _SFR_MEM8(0x0887) -#define AWEXC_DTLS _SFR_MEM8(0x0888) -#define AWEXC_DTHS _SFR_MEM8(0x0889) -#define AWEXC_DTLSBUF _SFR_MEM8(0x088A) -#define AWEXC_DTHSBUF _SFR_MEM8(0x088B) -#define AWEXC_OUTOVEN _SFR_MEM8(0x088C) - -/* HIRES - High-Resolution Extension */ -#define HIRESC_CTRLA _SFR_MEM8(0x0890) - -/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ -#define USARTC0_DATA _SFR_MEM8(0x08A0) -#define USARTC0_STATUS _SFR_MEM8(0x08A1) -#define USARTC0_CTRLA _SFR_MEM8(0x08A3) -#define USARTC0_CTRLB _SFR_MEM8(0x08A4) -#define USARTC0_CTRLC _SFR_MEM8(0x08A5) -#define USARTC0_BAUDCTRLA _SFR_MEM8(0x08A6) -#define USARTC0_BAUDCTRLB _SFR_MEM8(0x08A7) - -/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ -#define USARTC1_DATA _SFR_MEM8(0x08B0) -#define USARTC1_STATUS _SFR_MEM8(0x08B1) -#define USARTC1_CTRLA _SFR_MEM8(0x08B3) -#define USARTC1_CTRLB _SFR_MEM8(0x08B4) -#define USARTC1_CTRLC _SFR_MEM8(0x08B5) -#define USARTC1_BAUDCTRLA _SFR_MEM8(0x08B6) -#define USARTC1_BAUDCTRLB _SFR_MEM8(0x08B7) - -/* SPI - Serial Peripheral Interface */ -#define SPIC_CTRL _SFR_MEM8(0x08C0) -#define SPIC_INTCTRL _SFR_MEM8(0x08C1) -#define SPIC_STATUS _SFR_MEM8(0x08C2) -#define SPIC_DATA _SFR_MEM8(0x08C3) - -/* IRCOM - IR Communication Module */ -#define IRCOM_CTRL _SFR_MEM8(0x08F8) -#define IRCOM_TXPLCTRL _SFR_MEM8(0x08F9) -#define IRCOM_RXPLCTRL _SFR_MEM8(0x08FA) - -/* TC0 - 16-bit Timer/Counter 0 */ -#define TCD0_CTRLA _SFR_MEM8(0x0900) -#define TCD0_CTRLB _SFR_MEM8(0x0901) -#define TCD0_CTRLC _SFR_MEM8(0x0902) -#define TCD0_CTRLD _SFR_MEM8(0x0903) -#define TCD0_CTRLE _SFR_MEM8(0x0904) -#define TCD0_INTCTRLA _SFR_MEM8(0x0906) -#define TCD0_INTCTRLB _SFR_MEM8(0x0907) -#define TCD0_CTRLFCLR _SFR_MEM8(0x0908) -#define TCD0_CTRLFSET _SFR_MEM8(0x0909) -#define TCD0_CTRLGCLR _SFR_MEM8(0x090A) -#define TCD0_CTRLGSET _SFR_MEM8(0x090B) -#define TCD0_INTFLAGS _SFR_MEM8(0x090C) -#define TCD0_TEMP _SFR_MEM8(0x090F) -#define TCD0_CNT _SFR_MEM16(0x0920) -#define TCD0_PER _SFR_MEM16(0x0926) -#define TCD0_CCA _SFR_MEM16(0x0928) -#define TCD0_CCB _SFR_MEM16(0x092A) -#define TCD0_CCC _SFR_MEM16(0x092C) -#define TCD0_CCD _SFR_MEM16(0x092E) -#define TCD0_PERBUF _SFR_MEM16(0x0936) -#define TCD0_CCABUF _SFR_MEM16(0x0938) -#define TCD0_CCBBUF _SFR_MEM16(0x093A) -#define TCD0_CCCBUF _SFR_MEM16(0x093C) -#define TCD0_CCDBUF _SFR_MEM16(0x093E) - -/* TC2 - 16-bit Timer/Counter type 2 */ -#define TCD2_CTRLA _SFR_MEM8(0x0900) -#define TCD2_CTRLB _SFR_MEM8(0x0901) -#define TCD2_CTRLC _SFR_MEM8(0x0902) -#define TCD2_CTRLE _SFR_MEM8(0x0904) -#define TCD2_INTCTRLA _SFR_MEM8(0x0906) -#define TCD2_INTCTRLB _SFR_MEM8(0x0907) -#define TCD2_CTRLF _SFR_MEM8(0x0909) -#define TCD2_INTFLAGS _SFR_MEM8(0x090C) -#define TCD2_LCNT _SFR_MEM8(0x0920) -#define TCD2_HCNT _SFR_MEM8(0x0921) -#define TCD2_LPER _SFR_MEM8(0x0926) -#define TCD2_HPER _SFR_MEM8(0x0927) -#define TCD2_LCMPA _SFR_MEM8(0x0928) -#define TCD2_HCMPA _SFR_MEM8(0x0929) -#define TCD2_LCMPB _SFR_MEM8(0x092A) -#define TCD2_HCMPB _SFR_MEM8(0x092B) -#define TCD2_LCMPC _SFR_MEM8(0x092C) -#define TCD2_HCMPC _SFR_MEM8(0x092D) -#define TCD2_LCMPD _SFR_MEM8(0x092E) -#define TCD2_HCMPD _SFR_MEM8(0x092F) - -/* TC1 - 16-bit Timer/Counter 1 */ -#define TCD1_CTRLA _SFR_MEM8(0x0940) -#define TCD1_CTRLB _SFR_MEM8(0x0941) -#define TCD1_CTRLC _SFR_MEM8(0x0942) -#define TCD1_CTRLD _SFR_MEM8(0x0943) -#define TCD1_CTRLE _SFR_MEM8(0x0944) -#define TCD1_INTCTRLA _SFR_MEM8(0x0946) -#define TCD1_INTCTRLB _SFR_MEM8(0x0947) -#define TCD1_CTRLFCLR _SFR_MEM8(0x0948) -#define TCD1_CTRLFSET _SFR_MEM8(0x0949) -#define TCD1_CTRLGCLR _SFR_MEM8(0x094A) -#define TCD1_CTRLGSET _SFR_MEM8(0x094B) -#define TCD1_INTFLAGS _SFR_MEM8(0x094C) -#define TCD1_TEMP _SFR_MEM8(0x094F) -#define TCD1_CNT _SFR_MEM16(0x0960) -#define TCD1_PER _SFR_MEM16(0x0966) -#define TCD1_CCA _SFR_MEM16(0x0968) -#define TCD1_CCB _SFR_MEM16(0x096A) -#define TCD1_PERBUF _SFR_MEM16(0x0976) -#define TCD1_CCABUF _SFR_MEM16(0x0978) -#define TCD1_CCBBUF _SFR_MEM16(0x097A) - -/* HIRES - High-Resolution Extension */ -#define HIRESD_CTRLA _SFR_MEM8(0x0990) - -/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ -#define USARTD0_DATA _SFR_MEM8(0x09A0) -#define USARTD0_STATUS _SFR_MEM8(0x09A1) -#define USARTD0_CTRLA _SFR_MEM8(0x09A3) -#define USARTD0_CTRLB _SFR_MEM8(0x09A4) -#define USARTD0_CTRLC _SFR_MEM8(0x09A5) -#define USARTD0_BAUDCTRLA _SFR_MEM8(0x09A6) -#define USARTD0_BAUDCTRLB _SFR_MEM8(0x09A7) - -/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ -#define USARTD1_DATA _SFR_MEM8(0x09B0) -#define USARTD1_STATUS _SFR_MEM8(0x09B1) -#define USARTD1_CTRLA _SFR_MEM8(0x09B3) -#define USARTD1_CTRLB _SFR_MEM8(0x09B4) -#define USARTD1_CTRLC _SFR_MEM8(0x09B5) -#define USARTD1_BAUDCTRLA _SFR_MEM8(0x09B6) -#define USARTD1_BAUDCTRLB _SFR_MEM8(0x09B7) - -/* SPI - Serial Peripheral Interface */ -#define SPID_CTRL _SFR_MEM8(0x09C0) -#define SPID_INTCTRL _SFR_MEM8(0x09C1) -#define SPID_STATUS _SFR_MEM8(0x09C2) -#define SPID_DATA _SFR_MEM8(0x09C3) - -/* TC0 - 16-bit Timer/Counter 0 */ -#define TCE0_CTRLA _SFR_MEM8(0x0A00) -#define TCE0_CTRLB _SFR_MEM8(0x0A01) -#define TCE0_CTRLC _SFR_MEM8(0x0A02) -#define TCE0_CTRLD _SFR_MEM8(0x0A03) -#define TCE0_CTRLE _SFR_MEM8(0x0A04) -#define TCE0_INTCTRLA _SFR_MEM8(0x0A06) -#define TCE0_INTCTRLB _SFR_MEM8(0x0A07) -#define TCE0_CTRLFCLR _SFR_MEM8(0x0A08) -#define TCE0_CTRLFSET _SFR_MEM8(0x0A09) -#define TCE0_CTRLGCLR _SFR_MEM8(0x0A0A) -#define TCE0_CTRLGSET _SFR_MEM8(0x0A0B) -#define TCE0_INTFLAGS _SFR_MEM8(0x0A0C) -#define TCE0_TEMP _SFR_MEM8(0x0A0F) -#define TCE0_CNT _SFR_MEM16(0x0A20) -#define TCE0_PER _SFR_MEM16(0x0A26) -#define TCE0_CCA _SFR_MEM16(0x0A28) -#define TCE0_CCB _SFR_MEM16(0x0A2A) -#define TCE0_CCC _SFR_MEM16(0x0A2C) -#define TCE0_CCD _SFR_MEM16(0x0A2E) -#define TCE0_PERBUF _SFR_MEM16(0x0A36) -#define TCE0_CCABUF _SFR_MEM16(0x0A38) -#define TCE0_CCBBUF _SFR_MEM16(0x0A3A) -#define TCE0_CCCBUF _SFR_MEM16(0x0A3C) -#define TCE0_CCDBUF _SFR_MEM16(0x0A3E) - -/* TC2 - 16-bit Timer/Counter type 2 */ -#define TCE2_CTRLA _SFR_MEM8(0x0A00) -#define TCE2_CTRLB _SFR_MEM8(0x0A01) -#define TCE2_CTRLC _SFR_MEM8(0x0A02) -#define TCE2_CTRLE _SFR_MEM8(0x0A04) -#define TCE2_INTCTRLA _SFR_MEM8(0x0A06) -#define TCE2_INTCTRLB _SFR_MEM8(0x0A07) -#define TCE2_CTRLF _SFR_MEM8(0x0A09) -#define TCE2_INTFLAGS _SFR_MEM8(0x0A0C) -#define TCE2_LCNT _SFR_MEM8(0x0A20) -#define TCE2_HCNT _SFR_MEM8(0x0A21) -#define TCE2_LPER _SFR_MEM8(0x0A26) -#define TCE2_HPER _SFR_MEM8(0x0A27) -#define TCE2_LCMPA _SFR_MEM8(0x0A28) -#define TCE2_HCMPA _SFR_MEM8(0x0A29) -#define TCE2_LCMPB _SFR_MEM8(0x0A2A) -#define TCE2_HCMPB _SFR_MEM8(0x0A2B) -#define TCE2_LCMPC _SFR_MEM8(0x0A2C) -#define TCE2_HCMPC _SFR_MEM8(0x0A2D) -#define TCE2_LCMPD _SFR_MEM8(0x0A2E) -#define TCE2_HCMPD _SFR_MEM8(0x0A2F) - -/* TC1 - 16-bit Timer/Counter 1 */ -#define TCE1_CTRLA _SFR_MEM8(0x0A40) -#define TCE1_CTRLB _SFR_MEM8(0x0A41) -#define TCE1_CTRLC _SFR_MEM8(0x0A42) -#define TCE1_CTRLD _SFR_MEM8(0x0A43) -#define TCE1_CTRLE _SFR_MEM8(0x0A44) -#define TCE1_INTCTRLA _SFR_MEM8(0x0A46) -#define TCE1_INTCTRLB _SFR_MEM8(0x0A47) -#define TCE1_CTRLFCLR _SFR_MEM8(0x0A48) -#define TCE1_CTRLFSET _SFR_MEM8(0x0A49) -#define TCE1_CTRLGCLR _SFR_MEM8(0x0A4A) -#define TCE1_CTRLGSET _SFR_MEM8(0x0A4B) -#define TCE1_INTFLAGS _SFR_MEM8(0x0A4C) -#define TCE1_TEMP _SFR_MEM8(0x0A4F) -#define TCE1_CNT _SFR_MEM16(0x0A60) -#define TCE1_PER _SFR_MEM16(0x0A66) -#define TCE1_CCA _SFR_MEM16(0x0A68) -#define TCE1_CCB _SFR_MEM16(0x0A6A) -#define TCE1_PERBUF _SFR_MEM16(0x0A76) -#define TCE1_CCABUF _SFR_MEM16(0x0A78) -#define TCE1_CCBBUF _SFR_MEM16(0x0A7A) - -/* AWEX - Advanced Waveform Extension */ -#define AWEXE_CTRL _SFR_MEM8(0x0A80) -#define AWEXE_FDEMASK _SFR_MEM8(0x0A82) -#define AWEXE_FDCTRL _SFR_MEM8(0x0A83) -#define AWEXE_STATUS _SFR_MEM8(0x0A84) -#define AWEXE_STATUSSET _SFR_MEM8(0x0A85) -#define AWEXE_DTBOTH _SFR_MEM8(0x0A86) -#define AWEXE_DTBOTHBUF _SFR_MEM8(0x0A87) -#define AWEXE_DTLS _SFR_MEM8(0x0A88) -#define AWEXE_DTHS _SFR_MEM8(0x0A89) -#define AWEXE_DTLSBUF _SFR_MEM8(0x0A8A) -#define AWEXE_DTHSBUF _SFR_MEM8(0x0A8B) -#define AWEXE_OUTOVEN _SFR_MEM8(0x0A8C) - -/* HIRES - High-Resolution Extension */ -#define HIRESE_CTRLA _SFR_MEM8(0x0A90) - -/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ -#define USARTE0_DATA _SFR_MEM8(0x0AA0) -#define USARTE0_STATUS _SFR_MEM8(0x0AA1) -#define USARTE0_CTRLA _SFR_MEM8(0x0AA3) -#define USARTE0_CTRLB _SFR_MEM8(0x0AA4) -#define USARTE0_CTRLC _SFR_MEM8(0x0AA5) -#define USARTE0_BAUDCTRLA _SFR_MEM8(0x0AA6) -#define USARTE0_BAUDCTRLB _SFR_MEM8(0x0AA7) - -/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ -#define USARTE1_DATA _SFR_MEM8(0x0AB0) -#define USARTE1_STATUS _SFR_MEM8(0x0AB1) -#define USARTE1_CTRLA _SFR_MEM8(0x0AB3) -#define USARTE1_CTRLB _SFR_MEM8(0x0AB4) -#define USARTE1_CTRLC _SFR_MEM8(0x0AB5) -#define USARTE1_BAUDCTRLA _SFR_MEM8(0x0AB6) -#define USARTE1_BAUDCTRLB _SFR_MEM8(0x0AB7) - -/* SPI - Serial Peripheral Interface */ -#define SPIE_CTRL _SFR_MEM8(0x0AC0) -#define SPIE_INTCTRL _SFR_MEM8(0x0AC1) -#define SPIE_STATUS _SFR_MEM8(0x0AC2) -#define SPIE_DATA _SFR_MEM8(0x0AC3) - -/* TC0 - 16-bit Timer/Counter 0 */ -#define TCF0_CTRLA _SFR_MEM8(0x0B00) -#define TCF0_CTRLB _SFR_MEM8(0x0B01) -#define TCF0_CTRLC _SFR_MEM8(0x0B02) -#define TCF0_CTRLD _SFR_MEM8(0x0B03) -#define TCF0_CTRLE _SFR_MEM8(0x0B04) -#define TCF0_INTCTRLA _SFR_MEM8(0x0B06) -#define TCF0_INTCTRLB _SFR_MEM8(0x0B07) -#define TCF0_CTRLFCLR _SFR_MEM8(0x0B08) -#define TCF0_CTRLFSET _SFR_MEM8(0x0B09) -#define TCF0_CTRLGCLR _SFR_MEM8(0x0B0A) -#define TCF0_CTRLGSET _SFR_MEM8(0x0B0B) -#define TCF0_INTFLAGS _SFR_MEM8(0x0B0C) -#define TCF0_TEMP _SFR_MEM8(0x0B0F) -#define TCF0_CNT _SFR_MEM16(0x0B20) -#define TCF0_PER _SFR_MEM16(0x0B26) -#define TCF0_CCA _SFR_MEM16(0x0B28) -#define TCF0_CCB _SFR_MEM16(0x0B2A) -#define TCF0_CCC _SFR_MEM16(0x0B2C) -#define TCF0_CCD _SFR_MEM16(0x0B2E) -#define TCF0_PERBUF _SFR_MEM16(0x0B36) -#define TCF0_CCABUF _SFR_MEM16(0x0B38) -#define TCF0_CCBBUF _SFR_MEM16(0x0B3A) -#define TCF0_CCCBUF _SFR_MEM16(0x0B3C) -#define TCF0_CCDBUF _SFR_MEM16(0x0B3E) - -/* TC2 - 16-bit Timer/Counter type 2 */ -#define TCF2_CTRLA _SFR_MEM8(0x0B00) -#define TCF2_CTRLB _SFR_MEM8(0x0B01) -#define TCF2_CTRLC _SFR_MEM8(0x0B02) -#define TCF2_CTRLE _SFR_MEM8(0x0B04) -#define TCF2_INTCTRLA _SFR_MEM8(0x0B06) -#define TCF2_INTCTRLB _SFR_MEM8(0x0B07) -#define TCF2_CTRLF _SFR_MEM8(0x0B09) -#define TCF2_INTFLAGS _SFR_MEM8(0x0B0C) -#define TCF2_LCNT _SFR_MEM8(0x0B20) -#define TCF2_HCNT _SFR_MEM8(0x0B21) -#define TCF2_LPER _SFR_MEM8(0x0B26) -#define TCF2_HPER _SFR_MEM8(0x0B27) -#define TCF2_LCMPA _SFR_MEM8(0x0B28) -#define TCF2_HCMPA _SFR_MEM8(0x0B29) -#define TCF2_LCMPB _SFR_MEM8(0x0B2A) -#define TCF2_HCMPB _SFR_MEM8(0x0B2B) -#define TCF2_LCMPC _SFR_MEM8(0x0B2C) -#define TCF2_HCMPC _SFR_MEM8(0x0B2D) -#define TCF2_LCMPD _SFR_MEM8(0x0B2E) -#define TCF2_HCMPD _SFR_MEM8(0x0B2F) - -/* HIRES - High-Resolution Extension */ -#define HIRESF_CTRLA _SFR_MEM8(0x0B90) - -/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ -#define USARTF0_DATA _SFR_MEM8(0x0BA0) -#define USARTF0_STATUS _SFR_MEM8(0x0BA1) -#define USARTF0_CTRLA _SFR_MEM8(0x0BA3) -#define USARTF0_CTRLB _SFR_MEM8(0x0BA4) -#define USARTF0_CTRLC _SFR_MEM8(0x0BA5) -#define USARTF0_BAUDCTRLA _SFR_MEM8(0x0BA6) -#define USARTF0_BAUDCTRLB _SFR_MEM8(0x0BA7) - - - -/*================== Bitfield Definitions ================== */ - -/* VPORT - Virtual Ports */ -/* VPORT.INTFLAGS bit masks and bit positions */ -#define VPORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ -#define VPORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ - -#define VPORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ -#define VPORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ - -/* XOCD - On-Chip Debug System */ -/* OCD.OCDR0 bit masks and bit positions */ -#define OCD_OCDRD_gm 0xFF /* OCDR Dirty group mask. */ -#define OCD_OCDRD_gp 0 /* OCDR Dirty group position. */ -#define OCD_OCDRD0_bm (1<<0) /* OCDR Dirty bit 0 mask. */ -#define OCD_OCDRD0_bp 0 /* OCDR Dirty bit 0 position. */ -#define OCD_OCDRD1_bm (1<<1) /* OCDR Dirty bit 1 mask. */ -#define OCD_OCDRD1_bp 1 /* OCDR Dirty bit 1 position. */ -#define OCD_OCDRD2_bm (1<<2) /* OCDR Dirty bit 2 mask. */ -#define OCD_OCDRD2_bp 2 /* OCDR Dirty bit 2 position. */ -#define OCD_OCDRD3_bm (1<<3) /* OCDR Dirty bit 3 mask. */ -#define OCD_OCDRD3_bp 3 /* OCDR Dirty bit 3 position. */ -#define OCD_OCDRD4_bm (1<<4) /* OCDR Dirty bit 4 mask. */ -#define OCD_OCDRD4_bp 4 /* OCDR Dirty bit 4 position. */ -#define OCD_OCDRD5_bm (1<<5) /* OCDR Dirty bit 5 mask. */ -#define OCD_OCDRD5_bp 5 /* OCDR Dirty bit 5 position. */ -#define OCD_OCDRD6_bm (1<<6) /* OCDR Dirty bit 6 mask. */ -#define OCD_OCDRD6_bp 6 /* OCDR Dirty bit 6 position. */ -#define OCD_OCDRD7_bm (1<<7) /* OCDR Dirty bit 7 mask. */ -#define OCD_OCDRD7_bp 7 /* OCDR Dirty bit 7 position. */ - -/* OCD.OCDR1 bit masks and bit positions */ -/* OCD_OCDRD Predefined. */ -/* OCD_OCDRD Predefined. */ - -/* CPU - CPU */ -/* CPU.CCP bit masks and bit positions */ -#define CPU_CCP_gm 0xFF /* CCP signature group mask. */ -#define CPU_CCP_gp 0 /* CCP signature group position. */ -#define CPU_CCP0_bm (1<<0) /* CCP signature bit 0 mask. */ -#define CPU_CCP0_bp 0 /* CCP signature bit 0 position. */ -#define CPU_CCP1_bm (1<<1) /* CCP signature bit 1 mask. */ -#define CPU_CCP1_bp 1 /* CCP signature bit 1 position. */ -#define CPU_CCP2_bm (1<<2) /* CCP signature bit 2 mask. */ -#define CPU_CCP2_bp 2 /* CCP signature bit 2 position. */ -#define CPU_CCP3_bm (1<<3) /* CCP signature bit 3 mask. */ -#define CPU_CCP3_bp 3 /* CCP signature bit 3 position. */ -#define CPU_CCP4_bm (1<<4) /* CCP signature bit 4 mask. */ -#define CPU_CCP4_bp 4 /* CCP signature bit 4 position. */ -#define CPU_CCP5_bm (1<<5) /* CCP signature bit 5 mask. */ -#define CPU_CCP5_bp 5 /* CCP signature bit 5 position. */ -#define CPU_CCP6_bm (1<<6) /* CCP signature bit 6 mask. */ -#define CPU_CCP6_bp 6 /* CCP signature bit 6 position. */ -#define CPU_CCP7_bm (1<<7) /* CCP signature bit 7 mask. */ -#define CPU_CCP7_bp 7 /* CCP signature bit 7 position. */ - -/* CPU.SREG bit masks and bit positions */ -#define CPU_I_bm 0x80 /* Global Interrupt Enable Flag bit mask. */ -#define CPU_I_bp 7 /* Global Interrupt Enable Flag bit position. */ - -#define CPU_T_bm 0x40 /* Transfer Bit bit mask. */ -#define CPU_T_bp 6 /* Transfer Bit bit position. */ - -#define CPU_H_bm 0x20 /* Half Carry Flag bit mask. */ -#define CPU_H_bp 5 /* Half Carry Flag bit position. */ - -#define CPU_S_bm 0x10 /* N Exclusive Or V Flag bit mask. */ -#define CPU_S_bp 4 /* N Exclusive Or V Flag bit position. */ - -#define CPU_V_bm 0x08 /* Two's Complement Overflow Flag bit mask. */ -#define CPU_V_bp 3 /* Two's Complement Overflow Flag bit position. */ - -#define CPU_N_bm 0x04 /* Negative Flag bit mask. */ -#define CPU_N_bp 2 /* Negative Flag bit position. */ - -#define CPU_Z_bm 0x02 /* Zero Flag bit mask. */ -#define CPU_Z_bp 1 /* Zero Flag bit position. */ - -#define CPU_C_bm 0x01 /* Carry Flag bit mask. */ -#define CPU_C_bp 0 /* Carry Flag bit position. */ - -/* CLK - Clock System */ -/* CLK.CTRL bit masks and bit positions */ -#define CLK_SCLKSEL_gm 0x07 /* System Clock Selection group mask. */ -#define CLK_SCLKSEL_gp 0 /* System Clock Selection group position. */ -#define CLK_SCLKSEL0_bm (1<<0) /* System Clock Selection bit 0 mask. */ -#define CLK_SCLKSEL0_bp 0 /* System Clock Selection bit 0 position. */ -#define CLK_SCLKSEL1_bm (1<<1) /* System Clock Selection bit 1 mask. */ -#define CLK_SCLKSEL1_bp 1 /* System Clock Selection bit 1 position. */ -#define CLK_SCLKSEL2_bm (1<<2) /* System Clock Selection bit 2 mask. */ -#define CLK_SCLKSEL2_bp 2 /* System Clock Selection bit 2 position. */ - -/* CLK.PSCTRL bit masks and bit positions */ -#define CLK_PSADIV_gm 0x7C /* Prescaler A Division Factor group mask. */ -#define CLK_PSADIV_gp 2 /* Prescaler A Division Factor group position. */ -#define CLK_PSADIV0_bm (1<<2) /* Prescaler A Division Factor bit 0 mask. */ -#define CLK_PSADIV0_bp 2 /* Prescaler A Division Factor bit 0 position. */ -#define CLK_PSADIV1_bm (1<<3) /* Prescaler A Division Factor bit 1 mask. */ -#define CLK_PSADIV1_bp 3 /* Prescaler A Division Factor bit 1 position. */ -#define CLK_PSADIV2_bm (1<<4) /* Prescaler A Division Factor bit 2 mask. */ -#define CLK_PSADIV2_bp 4 /* Prescaler A Division Factor bit 2 position. */ -#define CLK_PSADIV3_bm (1<<5) /* Prescaler A Division Factor bit 3 mask. */ -#define CLK_PSADIV3_bp 5 /* Prescaler A Division Factor bit 3 position. */ -#define CLK_PSADIV4_bm (1<<6) /* Prescaler A Division Factor bit 4 mask. */ -#define CLK_PSADIV4_bp 6 /* Prescaler A Division Factor bit 4 position. */ - -#define CLK_PSBCDIV_gm 0x03 /* Prescaler B and C Division factor group mask. */ -#define CLK_PSBCDIV_gp 0 /* Prescaler B and C Division factor group position. */ -#define CLK_PSBCDIV0_bm (1<<0) /* Prescaler B and C Division factor bit 0 mask. */ -#define CLK_PSBCDIV0_bp 0 /* Prescaler B and C Division factor bit 0 position. */ -#define CLK_PSBCDIV1_bm (1<<1) /* Prescaler B and C Division factor bit 1 mask. */ -#define CLK_PSBCDIV1_bp 1 /* Prescaler B and C Division factor bit 1 position. */ - -/* CLK.LOCK bit masks and bit positions */ -#define CLK_LOCK_bm 0x01 /* Clock System Lock bit mask. */ -#define CLK_LOCK_bp 0 /* Clock System Lock bit position. */ - -/* CLK.RTCCTRL bit masks and bit positions */ -#define CLK_RTCSRC_gm 0x0E /* Clock Source group mask. */ -#define CLK_RTCSRC_gp 1 /* Clock Source group position. */ -#define CLK_RTCSRC0_bm (1<<1) /* Clock Source bit 0 mask. */ -#define CLK_RTCSRC0_bp 1 /* Clock Source bit 0 position. */ -#define CLK_RTCSRC1_bm (1<<2) /* Clock Source bit 1 mask. */ -#define CLK_RTCSRC1_bp 2 /* Clock Source bit 1 position. */ -#define CLK_RTCSRC2_bm (1<<3) /* Clock Source bit 2 mask. */ -#define CLK_RTCSRC2_bp 3 /* Clock Source bit 2 position. */ - -#define CLK_RTCEN_bm 0x01 /* Clock Source Enable bit mask. */ -#define CLK_RTCEN_bp 0 /* Clock Source Enable bit position. */ - -/* CLK.USBCTRL bit masks and bit positions */ -#define CLK_USBPSDIV_gm 0x38 /* Prescaler Division Factor group mask. */ -#define CLK_USBPSDIV_gp 3 /* Prescaler Division Factor group position. */ -#define CLK_USBPSDIV0_bm (1<<3) /* Prescaler Division Factor bit 0 mask. */ -#define CLK_USBPSDIV0_bp 3 /* Prescaler Division Factor bit 0 position. */ -#define CLK_USBPSDIV1_bm (1<<4) /* Prescaler Division Factor bit 1 mask. */ -#define CLK_USBPSDIV1_bp 4 /* Prescaler Division Factor bit 1 position. */ -#define CLK_USBPSDIV2_bm (1<<5) /* Prescaler Division Factor bit 2 mask. */ -#define CLK_USBPSDIV2_bp 5 /* Prescaler Division Factor bit 2 position. */ - -#define CLK_USBSRC_gm 0x06 /* Clock Source group mask. */ -#define CLK_USBSRC_gp 1 /* Clock Source group position. */ -#define CLK_USBSRC0_bm (1<<1) /* Clock Source bit 0 mask. */ -#define CLK_USBSRC0_bp 1 /* Clock Source bit 0 position. */ -#define CLK_USBSRC1_bm (1<<2) /* Clock Source bit 1 mask. */ -#define CLK_USBSRC1_bp 2 /* Clock Source bit 1 position. */ - -#define CLK_USBSEN_bm 0x01 /* Clock Source Enable bit mask. */ -#define CLK_USBSEN_bp 0 /* Clock Source Enable bit position. */ - -/* PR.PRGEN bit masks and bit positions */ -#define PR_USB_bm 0x40 /* USB bit mask. */ -#define PR_USB_bp 6 /* USB bit position. */ - -#define PR_AES_bm 0x10 /* AES bit mask. */ -#define PR_AES_bp 4 /* AES bit position. */ - -#define PR_EBI_bm 0x08 /* External Bus Interface bit mask. */ -#define PR_EBI_bp 3 /* External Bus Interface bit position. */ - -#define PR_RTC_bm 0x04 /* Real-time Counter bit mask. */ -#define PR_RTC_bp 2 /* Real-time Counter bit position. */ - -#define PR_EVSYS_bm 0x02 /* Event System bit mask. */ -#define PR_EVSYS_bp 1 /* Event System bit position. */ - -#define PR_DMA_bm 0x01 /* DMA-Controller bit mask. */ -#define PR_DMA_bp 0 /* DMA-Controller bit position. */ - -/* PR.PRPA bit masks and bit positions */ -#define PR_DAC_bm 0x04 /* Port A DAC bit mask. */ -#define PR_DAC_bp 2 /* Port A DAC bit position. */ - -#define PR_ADC_bm 0x02 /* Port A ADC bit mask. */ -#define PR_ADC_bp 1 /* Port A ADC bit position. */ - -#define PR_AC_bm 0x01 /* Port A Analog Comparator bit mask. */ -#define PR_AC_bp 0 /* Port A Analog Comparator bit position. */ - -/* PR.PRPB bit masks and bit positions */ -/* PR_DAC Predefined. */ -/* PR_DAC Predefined. */ - -/* PR_ADC Predefined. */ -/* PR_ADC Predefined. */ - -/* PR_AC Predefined. */ -/* PR_AC Predefined. */ - -/* PR.PRPC bit masks and bit positions */ -#define PR_TWI_bm 0x40 /* Port C Two-wire Interface bit mask. */ -#define PR_TWI_bp 6 /* Port C Two-wire Interface bit position. */ - -#define PR_USART1_bm 0x20 /* Port C USART1 bit mask. */ -#define PR_USART1_bp 5 /* Port C USART1 bit position. */ - -#define PR_USART0_bm 0x10 /* Port C USART0 bit mask. */ -#define PR_USART0_bp 4 /* Port C USART0 bit position. */ - -#define PR_SPI_bm 0x08 /* Port C SPI bit mask. */ -#define PR_SPI_bp 3 /* Port C SPI bit position. */ - -#define PR_HIRES_bm 0x04 /* Port C AWEX bit mask. */ -#define PR_HIRES_bp 2 /* Port C AWEX bit position. */ - -#define PR_TC1_bm 0x02 /* Port C Timer/Counter1 bit mask. */ -#define PR_TC1_bp 1 /* Port C Timer/Counter1 bit position. */ - -#define PR_TC0_bm 0x01 /* Port C Timer/Counter0 bit mask. */ -#define PR_TC0_bp 0 /* Port C Timer/Counter0 bit position. */ - -/* PR.PRPD bit masks and bit positions */ -/* PR_TWI Predefined. */ -/* PR_TWI Predefined. */ - -/* PR_USART1 Predefined. */ -/* PR_USART1 Predefined. */ - -/* PR_USART0 Predefined. */ -/* PR_USART0 Predefined. */ - -/* PR_SPI Predefined. */ -/* PR_SPI Predefined. */ - -/* PR_HIRES Predefined. */ -/* PR_HIRES Predefined. */ - -/* PR_TC1 Predefined. */ -/* PR_TC1 Predefined. */ - -/* PR_TC0 Predefined. */ -/* PR_TC0 Predefined. */ - -/* PR.PRPE bit masks and bit positions */ -/* PR_TWI Predefined. */ -/* PR_TWI Predefined. */ - -/* PR_USART1 Predefined. */ -/* PR_USART1 Predefined. */ - -/* PR_USART0 Predefined. */ -/* PR_USART0 Predefined. */ - -/* PR_SPI Predefined. */ -/* PR_SPI Predefined. */ - -/* PR_HIRES Predefined. */ -/* PR_HIRES Predefined. */ - -/* PR_TC1 Predefined. */ -/* PR_TC1 Predefined. */ - -/* PR_TC0 Predefined. */ -/* PR_TC0 Predefined. */ - -/* PR.PRPF bit masks and bit positions */ -/* PR_TWI Predefined. */ -/* PR_TWI Predefined. */ - -/* PR_USART1 Predefined. */ -/* PR_USART1 Predefined. */ - -/* PR_USART0 Predefined. */ -/* PR_USART0 Predefined. */ - -/* PR_SPI Predefined. */ -/* PR_SPI Predefined. */ - -/* PR_HIRES Predefined. */ -/* PR_HIRES Predefined. */ - -/* PR_TC1 Predefined. */ -/* PR_TC1 Predefined. */ - -/* PR_TC0 Predefined. */ -/* PR_TC0 Predefined. */ - -/* SLEEP - Sleep Controller */ -/* SLEEP.CTRL bit masks and bit positions */ -#define SLEEP_SMODE_gm 0x0E /* Sleep Mode group mask. */ -#define SLEEP_SMODE_gp 1 /* Sleep Mode group position. */ -#define SLEEP_SMODE0_bm (1<<1) /* Sleep Mode bit 0 mask. */ -#define SLEEP_SMODE0_bp 1 /* Sleep Mode bit 0 position. */ -#define SLEEP_SMODE1_bm (1<<2) /* Sleep Mode bit 1 mask. */ -#define SLEEP_SMODE1_bp 2 /* Sleep Mode bit 1 position. */ -#define SLEEP_SMODE2_bm (1<<3) /* Sleep Mode bit 2 mask. */ -#define SLEEP_SMODE2_bp 3 /* Sleep Mode bit 2 position. */ - -#define SLEEP_SEN_bm 0x01 /* Sleep Enable bit mask. */ -#define SLEEP_SEN_bp 0 /* Sleep Enable bit position. */ - -/* OSC - Oscillator */ -/* OSC.CTRL bit masks and bit positions */ -#define OSC_PLLEN_bm 0x10 /* PLL Enable bit mask. */ -#define OSC_PLLEN_bp 4 /* PLL Enable bit position. */ - -#define OSC_XOSCEN_bm 0x08 /* External Oscillator Enable bit mask. */ -#define OSC_XOSCEN_bp 3 /* External Oscillator Enable bit position. */ - -#define OSC_RC32KEN_bm 0x04 /* Internal 32.768 kHz RC Oscillator Enable bit mask. */ -#define OSC_RC32KEN_bp 2 /* Internal 32.768 kHz RC Oscillator Enable bit position. */ - -#define OSC_RC32MEN_bm 0x02 /* Internal 32 MHz RC Oscillator Enable bit mask. */ -#define OSC_RC32MEN_bp 1 /* Internal 32 MHz RC Oscillator Enable bit position. */ - -#define OSC_RC2MEN_bm 0x01 /* Internal 2 MHz RC Oscillator Enable bit mask. */ -#define OSC_RC2MEN_bp 0 /* Internal 2 MHz RC Oscillator Enable bit position. */ - -/* OSC.STATUS bit masks and bit positions */ -#define OSC_PLLRDY_bm 0x10 /* PLL Ready bit mask. */ -#define OSC_PLLRDY_bp 4 /* PLL Ready bit position. */ - -#define OSC_XOSCRDY_bm 0x08 /* External Oscillator Ready bit mask. */ -#define OSC_XOSCRDY_bp 3 /* External Oscillator Ready bit position. */ - -#define OSC_RC32KRDY_bm 0x04 /* Internal 32.768 kHz RC Oscillator Ready bit mask. */ -#define OSC_RC32KRDY_bp 2 /* Internal 32.768 kHz RC Oscillator Ready bit position. */ - -#define OSC_RC32MRDY_bm 0x02 /* Internal 32 MHz RC Oscillator Ready bit mask. */ -#define OSC_RC32MRDY_bp 1 /* Internal 32 MHz RC Oscillator Ready bit position. */ - -#define OSC_RC2MRDY_bm 0x01 /* Internal 2 MHz RC Oscillator Ready bit mask. */ -#define OSC_RC2MRDY_bp 0 /* Internal 2 MHz RC Oscillator Ready bit position. */ - -/* OSC.XOSCCTRL bit masks and bit positions */ -#define OSC_FRQRANGE_gm 0xC0 /* Frequency Range group mask. */ -#define OSC_FRQRANGE_gp 6 /* Frequency Range group position. */ -#define OSC_FRQRANGE0_bm (1<<6) /* Frequency Range bit 0 mask. */ -#define OSC_FRQRANGE0_bp 6 /* Frequency Range bit 0 position. */ -#define OSC_FRQRANGE1_bm (1<<7) /* Frequency Range bit 1 mask. */ -#define OSC_FRQRANGE1_bp 7 /* Frequency Range bit 1 position. */ - -#define OSC_X32KLPM_bm 0x20 /* 32.768 kHz XTAL OSC Low-power Mode bit mask. */ -#define OSC_X32KLPM_bp 5 /* 32.768 kHz XTAL OSC Low-power Mode bit position. */ - -#define OSC_XOSCPWR_bm 0x10 /* 16 MHz Crystal Oscillator High Power mode bit mask. */ -#define OSC_XOSCPWR_bp 4 /* 16 MHz Crystal Oscillator High Power mode bit position. */ - -#define OSC_XOSCSEL_gm 0x0F /* External Oscillator Selection and Startup Time group mask. */ -#define OSC_XOSCSEL_gp 0 /* External Oscillator Selection and Startup Time group position. */ -#define OSC_XOSCSEL0_bm (1<<0) /* External Oscillator Selection and Startup Time bit 0 mask. */ -#define OSC_XOSCSEL0_bp 0 /* External Oscillator Selection and Startup Time bit 0 position. */ -#define OSC_XOSCSEL1_bm (1<<1) /* External Oscillator Selection and Startup Time bit 1 mask. */ -#define OSC_XOSCSEL1_bp 1 /* External Oscillator Selection and Startup Time bit 1 position. */ -#define OSC_XOSCSEL2_bm (1<<2) /* External Oscillator Selection and Startup Time bit 2 mask. */ -#define OSC_XOSCSEL2_bp 2 /* External Oscillator Selection and Startup Time bit 2 position. */ -#define OSC_XOSCSEL3_bm (1<<3) /* External Oscillator Selection and Startup Time bit 3 mask. */ -#define OSC_XOSCSEL3_bp 3 /* External Oscillator Selection and Startup Time bit 3 position. */ - -/* OSC.XOSCFAIL bit masks and bit positions */ -#define OSC_PLLFDIF_bm 0x08 /* PLL Failure Detection Interrupt Flag bit mask. */ -#define OSC_PLLFDIF_bp 3 /* PLL Failure Detection Interrupt Flag bit position. */ - -#define OSC_PLLFDEN_bm 0x04 /* PLL Failure Detection Enable bit mask. */ -#define OSC_PLLFDEN_bp 2 /* PLL Failure Detection Enable bit position. */ - -#define OSC_XOSCFDIF_bm 0x02 /* XOSC Failure Detection Interrupt Flag bit mask. */ -#define OSC_XOSCFDIF_bp 1 /* XOSC Failure Detection Interrupt Flag bit position. */ - -#define OSC_XOSCFDEN_bm 0x01 /* XOSC Failure Detection Enable bit mask. */ -#define OSC_XOSCFDEN_bp 0 /* XOSC Failure Detection Enable bit position. */ - -/* OSC.PLLCTRL bit masks and bit positions */ -#define OSC_PLLSRC_gm 0xC0 /* Clock Source group mask. */ -#define OSC_PLLSRC_gp 6 /* Clock Source group position. */ -#define OSC_PLLSRC0_bm (1<<6) /* Clock Source bit 0 mask. */ -#define OSC_PLLSRC0_bp 6 /* Clock Source bit 0 position. */ -#define OSC_PLLSRC1_bm (1<<7) /* Clock Source bit 1 mask. */ -#define OSC_PLLSRC1_bp 7 /* Clock Source bit 1 position. */ - -#define OSC_PLLDIV_bm 0x20 /* Divide by 2 bit mask. */ -#define OSC_PLLDIV_bp 5 /* Divide by 2 bit position. */ - -#define OSC_PLLFAC_gm 0x1F /* Multiplication Factor group mask. */ -#define OSC_PLLFAC_gp 0 /* Multiplication Factor group position. */ -#define OSC_PLLFAC0_bm (1<<0) /* Multiplication Factor bit 0 mask. */ -#define OSC_PLLFAC0_bp 0 /* Multiplication Factor bit 0 position. */ -#define OSC_PLLFAC1_bm (1<<1) /* Multiplication Factor bit 1 mask. */ -#define OSC_PLLFAC1_bp 1 /* Multiplication Factor bit 1 position. */ -#define OSC_PLLFAC2_bm (1<<2) /* Multiplication Factor bit 2 mask. */ -#define OSC_PLLFAC2_bp 2 /* Multiplication Factor bit 2 position. */ -#define OSC_PLLFAC3_bm (1<<3) /* Multiplication Factor bit 3 mask. */ -#define OSC_PLLFAC3_bp 3 /* Multiplication Factor bit 3 position. */ -#define OSC_PLLFAC4_bm (1<<4) /* Multiplication Factor bit 4 mask. */ -#define OSC_PLLFAC4_bp 4 /* Multiplication Factor bit 4 position. */ - -/* OSC.DFLLCTRL bit masks and bit positions */ -#define OSC_RC32MCREF_gm 0x06 /* 32 MHz DFLL Calibration Reference group mask. */ -#define OSC_RC32MCREF_gp 1 /* 32 MHz DFLL Calibration Reference group position. */ -#define OSC_RC32MCREF0_bm (1<<1) /* 32 MHz DFLL Calibration Reference bit 0 mask. */ -#define OSC_RC32MCREF0_bp 1 /* 32 MHz DFLL Calibration Reference bit 0 position. */ -#define OSC_RC32MCREF1_bm (1<<2) /* 32 MHz DFLL Calibration Reference bit 1 mask. */ -#define OSC_RC32MCREF1_bp 2 /* 32 MHz DFLL Calibration Reference bit 1 position. */ - -#define OSC_RC2MCREF_bm 0x01 /* 2 MHz DFLL Calibration Reference bit mask. */ -#define OSC_RC2MCREF_bp 0 /* 2 MHz DFLL Calibration Reference bit position. */ - -/* DFLL - DFLL */ -/* DFLL.CTRL bit masks and bit positions */ -#define DFLL_ENABLE_bm 0x01 /* DFLL Enable bit mask. */ -#define DFLL_ENABLE_bp 0 /* DFLL Enable bit position. */ - -/* DFLL.CALA bit masks and bit positions */ -#define DFLL_CALL_gm 0x7F /* DFLL Calibration Value A group mask. */ -#define DFLL_CALL_gp 0 /* DFLL Calibration Value A group position. */ -#define DFLL_CALL0_bm (1<<0) /* DFLL Calibration Value A bit 0 mask. */ -#define DFLL_CALL0_bp 0 /* DFLL Calibration Value A bit 0 position. */ -#define DFLL_CALL1_bm (1<<1) /* DFLL Calibration Value A bit 1 mask. */ -#define DFLL_CALL1_bp 1 /* DFLL Calibration Value A bit 1 position. */ -#define DFLL_CALL2_bm (1<<2) /* DFLL Calibration Value A bit 2 mask. */ -#define DFLL_CALL2_bp 2 /* DFLL Calibration Value A bit 2 position. */ -#define DFLL_CALL3_bm (1<<3) /* DFLL Calibration Value A bit 3 mask. */ -#define DFLL_CALL3_bp 3 /* DFLL Calibration Value A bit 3 position. */ -#define DFLL_CALL4_bm (1<<4) /* DFLL Calibration Value A bit 4 mask. */ -#define DFLL_CALL4_bp 4 /* DFLL Calibration Value A bit 4 position. */ -#define DFLL_CALL5_bm (1<<5) /* DFLL Calibration Value A bit 5 mask. */ -#define DFLL_CALL5_bp 5 /* DFLL Calibration Value A bit 5 position. */ -#define DFLL_CALL6_bm (1<<6) /* DFLL Calibration Value A bit 6 mask. */ -#define DFLL_CALL6_bp 6 /* DFLL Calibration Value A bit 6 position. */ - -/* DFLL.CALB bit masks and bit positions */ -#define DFLL_CALH_gm 0x3F /* DFLL Calibration Value B group mask. */ -#define DFLL_CALH_gp 0 /* DFLL Calibration Value B group position. */ -#define DFLL_CALH0_bm (1<<0) /* DFLL Calibration Value B bit 0 mask. */ -#define DFLL_CALH0_bp 0 /* DFLL Calibration Value B bit 0 position. */ -#define DFLL_CALH1_bm (1<<1) /* DFLL Calibration Value B bit 1 mask. */ -#define DFLL_CALH1_bp 1 /* DFLL Calibration Value B bit 1 position. */ -#define DFLL_CALH2_bm (1<<2) /* DFLL Calibration Value B bit 2 mask. */ -#define DFLL_CALH2_bp 2 /* DFLL Calibration Value B bit 2 position. */ -#define DFLL_CALH3_bm (1<<3) /* DFLL Calibration Value B bit 3 mask. */ -#define DFLL_CALH3_bp 3 /* DFLL Calibration Value B bit 3 position. */ -#define DFLL_CALH4_bm (1<<4) /* DFLL Calibration Value B bit 4 mask. */ -#define DFLL_CALH4_bp 4 /* DFLL Calibration Value B bit 4 position. */ -#define DFLL_CALH5_bm (1<<5) /* DFLL Calibration Value B bit 5 mask. */ -#define DFLL_CALH5_bp 5 /* DFLL Calibration Value B bit 5 position. */ - -/* RST - Reset */ -/* RST.STATUS bit masks and bit positions */ -#define RST_SDRF_bm 0x40 /* Spike Detection Reset Flag bit mask. */ -#define RST_SDRF_bp 6 /* Spike Detection Reset Flag bit position. */ - -#define RST_SRF_bm 0x20 /* Software Reset Flag bit mask. */ -#define RST_SRF_bp 5 /* Software Reset Flag bit position. */ - -#define RST_PDIRF_bm 0x10 /* Programming and Debug Interface Interface Reset Flag bit mask. */ -#define RST_PDIRF_bp 4 /* Programming and Debug Interface Interface Reset Flag bit position. */ - -#define RST_WDRF_bm 0x08 /* Watchdog Reset Flag bit mask. */ -#define RST_WDRF_bp 3 /* Watchdog Reset Flag bit position. */ - -#define RST_BORF_bm 0x04 /* Brown-out Reset Flag bit mask. */ -#define RST_BORF_bp 2 /* Brown-out Reset Flag bit position. */ - -#define RST_EXTRF_bm 0x02 /* External Reset Flag bit mask. */ -#define RST_EXTRF_bp 1 /* External Reset Flag bit position. */ - -#define RST_PORF_bm 0x01 /* Power-on Reset Flag bit mask. */ -#define RST_PORF_bp 0 /* Power-on Reset Flag bit position. */ - -/* RST.CTRL bit masks and bit positions */ -#define RST_SWRST_bm 0x01 /* Software Reset bit mask. */ -#define RST_SWRST_bp 0 /* Software Reset bit position. */ - -/* WDT - Watch-Dog Timer */ -/* WDT.CTRL bit masks and bit positions */ -#define WDT_PER_gm 0x3C /* Period group mask. */ -#define WDT_PER_gp 2 /* Period group position. */ -#define WDT_PER0_bm (1<<2) /* Period bit 0 mask. */ -#define WDT_PER0_bp 2 /* Period bit 0 position. */ -#define WDT_PER1_bm (1<<3) /* Period bit 1 mask. */ -#define WDT_PER1_bp 3 /* Period bit 1 position. */ -#define WDT_PER2_bm (1<<4) /* Period bit 2 mask. */ -#define WDT_PER2_bp 4 /* Period bit 2 position. */ -#define WDT_PER3_bm (1<<5) /* Period bit 3 mask. */ -#define WDT_PER3_bp 5 /* Period bit 3 position. */ - -#define WDT_ENABLE_bm 0x02 /* Enable bit mask. */ -#define WDT_ENABLE_bp 1 /* Enable bit position. */ - -#define WDT_CEN_bm 0x01 /* Change Enable bit mask. */ -#define WDT_CEN_bp 0 /* Change Enable bit position. */ - -/* WDT.WINCTRL bit masks and bit positions */ -#define WDT_WPER_gm 0x3C /* Windowed Mode Period group mask. */ -#define WDT_WPER_gp 2 /* Windowed Mode Period group position. */ -#define WDT_WPER0_bm (1<<2) /* Windowed Mode Period bit 0 mask. */ -#define WDT_WPER0_bp 2 /* Windowed Mode Period bit 0 position. */ -#define WDT_WPER1_bm (1<<3) /* Windowed Mode Period bit 1 mask. */ -#define WDT_WPER1_bp 3 /* Windowed Mode Period bit 1 position. */ -#define WDT_WPER2_bm (1<<4) /* Windowed Mode Period bit 2 mask. */ -#define WDT_WPER2_bp 4 /* Windowed Mode Period bit 2 position. */ -#define WDT_WPER3_bm (1<<5) /* Windowed Mode Period bit 3 mask. */ -#define WDT_WPER3_bp 5 /* Windowed Mode Period bit 3 position. */ - -#define WDT_WEN_bm 0x02 /* Windowed Mode Enable bit mask. */ -#define WDT_WEN_bp 1 /* Windowed Mode Enable bit position. */ - -#define WDT_WCEN_bm 0x01 /* Windowed Mode Change Enable bit mask. */ -#define WDT_WCEN_bp 0 /* Windowed Mode Change Enable bit position. */ - -/* WDT.STATUS bit masks and bit positions */ -#define WDT_SYNCBUSY_bm 0x01 /* Syncronization busy bit mask. */ -#define WDT_SYNCBUSY_bp 0 /* Syncronization busy bit position. */ - -/* MCU - MCU Control */ -/* MCU.MCUCR bit masks and bit positions */ -#define MCU_JTAGD_bm 0x01 /* JTAG Disable bit mask. */ -#define MCU_JTAGD_bp 0 /* JTAG Disable bit position. */ - -/* MCU.ANAINIT bit masks and bit positions */ -#define MCU_STARTUPDLYB_gm 0x0C /* Analog startup delay Port B group mask. */ -#define MCU_STARTUPDLYB_gp 2 /* Analog startup delay Port B group position. */ -#define MCU_STARTUPDLYB0_bm (1<<2) /* Analog startup delay Port B bit 0 mask. */ -#define MCU_STARTUPDLYB0_bp 2 /* Analog startup delay Port B bit 0 position. */ -#define MCU_STARTUPDLYB1_bm (1<<3) /* Analog startup delay Port B bit 1 mask. */ -#define MCU_STARTUPDLYB1_bp 3 /* Analog startup delay Port B bit 1 position. */ - -#define MCU_STARTUPDLYA_gm 0x03 /* Analog startup delay Port A group mask. */ -#define MCU_STARTUPDLYA_gp 0 /* Analog startup delay Port A group position. */ -#define MCU_STARTUPDLYA0_bm (1<<0) /* Analog startup delay Port A bit 0 mask. */ -#define MCU_STARTUPDLYA0_bp 0 /* Analog startup delay Port A bit 0 position. */ -#define MCU_STARTUPDLYA1_bm (1<<1) /* Analog startup delay Port A bit 1 mask. */ -#define MCU_STARTUPDLYA1_bp 1 /* Analog startup delay Port A bit 1 position. */ - -/* MCU.EVSYSLOCK bit masks and bit positions */ -#define MCU_EVSYS1LOCK_bm 0x10 /* Event Channel 4-7 Lock bit mask. */ -#define MCU_EVSYS1LOCK_bp 4 /* Event Channel 4-7 Lock bit position. */ - -#define MCU_EVSYS0LOCK_bm 0x01 /* Event Channel 0-3 Lock bit mask. */ -#define MCU_EVSYS0LOCK_bp 0 /* Event Channel 0-3 Lock bit position. */ - -/* MCU.AWEXLOCK bit masks and bit positions */ -#define MCU_AWEXFLOCK_bm 0x08 /* AWeX on T/C F0 Lock bit mask. */ -#define MCU_AWEXFLOCK_bp 3 /* AWeX on T/C F0 Lock bit position. */ - -#define MCU_AWEXELOCK_bm 0x04 /* AWeX on T/C E0 Lock bit mask. */ -#define MCU_AWEXELOCK_bp 2 /* AWeX on T/C E0 Lock bit position. */ - -#define MCU_AWEXDLOCK_bm 0x02 /* AWeX on T/C D0 Lock bit mask. */ -#define MCU_AWEXDLOCK_bp 1 /* AWeX on T/C D0 Lock bit position. */ - -#define MCU_AWEXCLOCK_bm 0x01 /* AWeX on T/C C0 Lock bit mask. */ -#define MCU_AWEXCLOCK_bp 0 /* AWeX on T/C C0 Lock bit position. */ - -/* PMIC - Programmable Multi-level Interrupt Controller */ -/* PMIC.STATUS bit masks and bit positions */ -#define PMIC_NMIEX_bm 0x80 /* Non-maskable Interrupt Executing bit mask. */ -#define PMIC_NMIEX_bp 7 /* Non-maskable Interrupt Executing bit position. */ - -#define PMIC_HILVLEX_bm 0x04 /* High Level Interrupt Executing bit mask. */ -#define PMIC_HILVLEX_bp 2 /* High Level Interrupt Executing bit position. */ - -#define PMIC_MEDLVLEX_bm 0x02 /* Medium Level Interrupt Executing bit mask. */ -#define PMIC_MEDLVLEX_bp 1 /* Medium Level Interrupt Executing bit position. */ - -#define PMIC_LOLVLEX_bm 0x01 /* Low Level Interrupt Executing bit mask. */ -#define PMIC_LOLVLEX_bp 0 /* Low Level Interrupt Executing bit position. */ - -/* PMIC.INTPRI bit masks and bit positions */ -#define PMIC_INTPRI_gm 0xFF /* Interrupt Priority group mask. */ -#define PMIC_INTPRI_gp 0 /* Interrupt Priority group position. */ -#define PMIC_INTPRI0_bm (1<<0) /* Interrupt Priority bit 0 mask. */ -#define PMIC_INTPRI0_bp 0 /* Interrupt Priority bit 0 position. */ -#define PMIC_INTPRI1_bm (1<<1) /* Interrupt Priority bit 1 mask. */ -#define PMIC_INTPRI1_bp 1 /* Interrupt Priority bit 1 position. */ -#define PMIC_INTPRI2_bm (1<<2) /* Interrupt Priority bit 2 mask. */ -#define PMIC_INTPRI2_bp 2 /* Interrupt Priority bit 2 position. */ -#define PMIC_INTPRI3_bm (1<<3) /* Interrupt Priority bit 3 mask. */ -#define PMIC_INTPRI3_bp 3 /* Interrupt Priority bit 3 position. */ -#define PMIC_INTPRI4_bm (1<<4) /* Interrupt Priority bit 4 mask. */ -#define PMIC_INTPRI4_bp 4 /* Interrupt Priority bit 4 position. */ -#define PMIC_INTPRI5_bm (1<<5) /* Interrupt Priority bit 5 mask. */ -#define PMIC_INTPRI5_bp 5 /* Interrupt Priority bit 5 position. */ -#define PMIC_INTPRI6_bm (1<<6) /* Interrupt Priority bit 6 mask. */ -#define PMIC_INTPRI6_bp 6 /* Interrupt Priority bit 6 position. */ -#define PMIC_INTPRI7_bm (1<<7) /* Interrupt Priority bit 7 mask. */ -#define PMIC_INTPRI7_bp 7 /* Interrupt Priority bit 7 position. */ - -/* PMIC.CTRL bit masks and bit positions */ -#define PMIC_RREN_bm 0x80 /* Round-Robin Priority Enable bit mask. */ -#define PMIC_RREN_bp 7 /* Round-Robin Priority Enable bit position. */ - -#define PMIC_IVSEL_bm 0x40 /* Interrupt Vector Select bit mask. */ -#define PMIC_IVSEL_bp 6 /* Interrupt Vector Select bit position. */ - -#define PMIC_HILVLEN_bm 0x04 /* High Level Enable bit mask. */ -#define PMIC_HILVLEN_bp 2 /* High Level Enable bit position. */ - -#define PMIC_MEDLVLEN_bm 0x02 /* Medium Level Enable bit mask. */ -#define PMIC_MEDLVLEN_bp 1 /* Medium Level Enable bit position. */ - -#define PMIC_LOLVLEN_bm 0x01 /* Low Level Enable bit mask. */ -#define PMIC_LOLVLEN_bp 0 /* Low Level Enable bit position. */ - -/* PORTCFG - Port Configuration */ -/* PORTCFG.VPCTRLA bit masks and bit positions */ -#define PORTCFG_VP1MAP_gm 0xF0 /* Virtual Port 1 Mapping group mask. */ -#define PORTCFG_VP1MAP_gp 4 /* Virtual Port 1 Mapping group position. */ -#define PORTCFG_VP1MAP0_bm (1<<4) /* Virtual Port 1 Mapping bit 0 mask. */ -#define PORTCFG_VP1MAP0_bp 4 /* Virtual Port 1 Mapping bit 0 position. */ -#define PORTCFG_VP1MAP1_bm (1<<5) /* Virtual Port 1 Mapping bit 1 mask. */ -#define PORTCFG_VP1MAP1_bp 5 /* Virtual Port 1 Mapping bit 1 position. */ -#define PORTCFG_VP1MAP2_bm (1<<6) /* Virtual Port 1 Mapping bit 2 mask. */ -#define PORTCFG_VP1MAP2_bp 6 /* Virtual Port 1 Mapping bit 2 position. */ -#define PORTCFG_VP1MAP3_bm (1<<7) /* Virtual Port 1 Mapping bit 3 mask. */ -#define PORTCFG_VP1MAP3_bp 7 /* Virtual Port 1 Mapping bit 3 position. */ - -#define PORTCFG_VP0MAP_gm 0x0F /* Virtual Port 0 Mapping group mask. */ -#define PORTCFG_VP0MAP_gp 0 /* Virtual Port 0 Mapping group position. */ -#define PORTCFG_VP0MAP0_bm (1<<0) /* Virtual Port 0 Mapping bit 0 mask. */ -#define PORTCFG_VP0MAP0_bp 0 /* Virtual Port 0 Mapping bit 0 position. */ -#define PORTCFG_VP0MAP1_bm (1<<1) /* Virtual Port 0 Mapping bit 1 mask. */ -#define PORTCFG_VP0MAP1_bp 1 /* Virtual Port 0 Mapping bit 1 position. */ -#define PORTCFG_VP0MAP2_bm (1<<2) /* Virtual Port 0 Mapping bit 2 mask. */ -#define PORTCFG_VP0MAP2_bp 2 /* Virtual Port 0 Mapping bit 2 position. */ -#define PORTCFG_VP0MAP3_bm (1<<3) /* Virtual Port 0 Mapping bit 3 mask. */ -#define PORTCFG_VP0MAP3_bp 3 /* Virtual Port 0 Mapping bit 3 position. */ - -/* PORTCFG.VPCTRLB bit masks and bit positions */ -#define PORTCFG_VP3MAP_gm 0xF0 /* Virtual Port 3 Mapping group mask. */ -#define PORTCFG_VP3MAP_gp 4 /* Virtual Port 3 Mapping group position. */ -#define PORTCFG_VP3MAP0_bm (1<<4) /* Virtual Port 3 Mapping bit 0 mask. */ -#define PORTCFG_VP3MAP0_bp 4 /* Virtual Port 3 Mapping bit 0 position. */ -#define PORTCFG_VP3MAP1_bm (1<<5) /* Virtual Port 3 Mapping bit 1 mask. */ -#define PORTCFG_VP3MAP1_bp 5 /* Virtual Port 3 Mapping bit 1 position. */ -#define PORTCFG_VP3MAP2_bm (1<<6) /* Virtual Port 3 Mapping bit 2 mask. */ -#define PORTCFG_VP3MAP2_bp 6 /* Virtual Port 3 Mapping bit 2 position. */ -#define PORTCFG_VP3MAP3_bm (1<<7) /* Virtual Port 3 Mapping bit 3 mask. */ -#define PORTCFG_VP3MAP3_bp 7 /* Virtual Port 3 Mapping bit 3 position. */ - -#define PORTCFG_VP2MAP_gm 0x0F /* Virtual Port 2 Mapping group mask. */ -#define PORTCFG_VP2MAP_gp 0 /* Virtual Port 2 Mapping group position. */ -#define PORTCFG_VP2MAP0_bm (1<<0) /* Virtual Port 2 Mapping bit 0 mask. */ -#define PORTCFG_VP2MAP0_bp 0 /* Virtual Port 2 Mapping bit 0 position. */ -#define PORTCFG_VP2MAP1_bm (1<<1) /* Virtual Port 2 Mapping bit 1 mask. */ -#define PORTCFG_VP2MAP1_bp 1 /* Virtual Port 2 Mapping bit 1 position. */ -#define PORTCFG_VP2MAP2_bm (1<<2) /* Virtual Port 2 Mapping bit 2 mask. */ -#define PORTCFG_VP2MAP2_bp 2 /* Virtual Port 2 Mapping bit 2 position. */ -#define PORTCFG_VP2MAP3_bm (1<<3) /* Virtual Port 2 Mapping bit 3 mask. */ -#define PORTCFG_VP2MAP3_bp 3 /* Virtual Port 2 Mapping bit 3 position. */ - -/* PORTCFG.CLKEVOUT bit masks and bit positions */ -#define PORTCFG_CLKOUT_gm 0x03 /* Peripheral Clock Output Port group mask. */ -#define PORTCFG_CLKOUT_gp 0 /* Peripheral Clock Output Port group position. */ -#define PORTCFG_CLKOUT0_bm (1<<0) /* Peripheral Clock Output Port bit 0 mask. */ -#define PORTCFG_CLKOUT0_bp 0 /* Peripheral Clock Output Port bit 0 position. */ -#define PORTCFG_CLKOUT1_bm (1<<1) /* Peripheral Clock Output Port bit 1 mask. */ -#define PORTCFG_CLKOUT1_bp 1 /* Peripheral Clock Output Port bit 1 position. */ - -#define PORTCFG_CLKOUTSEL_gm 0x0C /* Peripheral Clock Output Select group mask. */ -#define PORTCFG_CLKOUTSEL_gp 2 /* Peripheral Clock Output Select group position. */ -#define PORTCFG_CLKOUTSEL0_bm (1<<2) /* Peripheral Clock Output Select bit 0 mask. */ -#define PORTCFG_CLKOUTSEL0_bp 2 /* Peripheral Clock Output Select bit 0 position. */ -#define PORTCFG_CLKOUTSEL1_bm (1<<3) /* Peripheral Clock Output Select bit 1 mask. */ -#define PORTCFG_CLKOUTSEL1_bp 3 /* Peripheral Clock Output Select bit 1 position. */ - -#define PORTCFG_EVOUT_gm 0x30 /* Event Output Port group mask. */ -#define PORTCFG_EVOUT_gp 4 /* Event Output Port group position. */ -#define PORTCFG_EVOUT0_bm (1<<4) /* Event Output Port bit 0 mask. */ -#define PORTCFG_EVOUT0_bp 4 /* Event Output Port bit 0 position. */ -#define PORTCFG_EVOUT1_bm (1<<5) /* Event Output Port bit 1 mask. */ -#define PORTCFG_EVOUT1_bp 5 /* Event Output Port bit 1 position. */ - -#define PORTCFG_RTCOUT_bm 0x40 /* RTC Clock Output bit mask. */ -#define PORTCFG_RTCOUT_bp 6 /* RTC Clock Output bit position. */ - -#define PORTCFG_CLKEVPIN_bm 0x80 /* Peripheral Clock and Event Output pin Select bit mask. */ -#define PORTCFG_CLKEVPIN_bp 7 /* Peripheral Clock and Event Output pin Select bit position. */ - -/* PORTCFG.EBIOUT bit masks and bit positions */ -#define PORTCFG_EBICSOUT_gm 0x03 /* EBI Chip Select Output group mask. */ -#define PORTCFG_EBICSOUT_gp 0 /* EBI Chip Select Output group position. */ -#define PORTCFG_EBICSOUT0_bm (1<<0) /* EBI Chip Select Output bit 0 mask. */ -#define PORTCFG_EBICSOUT0_bp 0 /* EBI Chip Select Output bit 0 position. */ -#define PORTCFG_EBICSOUT1_bm (1<<1) /* EBI Chip Select Output bit 1 mask. */ -#define PORTCFG_EBICSOUT1_bp 1 /* EBI Chip Select Output bit 1 position. */ - -#define PORTCFG_EBIADROUT_gm 0x0C /* EBI Address Output group mask. */ -#define PORTCFG_EBIADROUT_gp 2 /* EBI Address Output group position. */ -#define PORTCFG_EBIADROUT0_bm (1<<2) /* EBI Address Output bit 0 mask. */ -#define PORTCFG_EBIADROUT0_bp 2 /* EBI Address Output bit 0 position. */ -#define PORTCFG_EBIADROUT1_bm (1<<3) /* EBI Address Output bit 1 mask. */ -#define PORTCFG_EBIADROUT1_bp 3 /* EBI Address Output bit 1 position. */ - -/* PORTCFG.EVOUTSEL bit masks and bit positions */ -#define PORTCFG_EVOUTSEL_gm 0x07 /* Event Output Select group mask. */ -#define PORTCFG_EVOUTSEL_gp 0 /* Event Output Select group position. */ -#define PORTCFG_EVOUTSEL0_bm (1<<0) /* Event Output Select bit 0 mask. */ -#define PORTCFG_EVOUTSEL0_bp 0 /* Event Output Select bit 0 position. */ -#define PORTCFG_EVOUTSEL1_bm (1<<1) /* Event Output Select bit 1 mask. */ -#define PORTCFG_EVOUTSEL1_bp 1 /* Event Output Select bit 1 position. */ -#define PORTCFG_EVOUTSEL2_bm (1<<2) /* Event Output Select bit 2 mask. */ -#define PORTCFG_EVOUTSEL2_bp 2 /* Event Output Select bit 2 position. */ - -/* AES - AES Module */ -/* AES.CTRL bit masks and bit positions */ -#define AES_START_bm 0x80 /* Start/Run bit mask. */ -#define AES_START_bp 7 /* Start/Run bit position. */ - -#define AES_AUTO_bm 0x40 /* Auto Start Trigger bit mask. */ -#define AES_AUTO_bp 6 /* Auto Start Trigger bit position. */ - -#define AES_RESET_bm 0x20 /* AES Software Reset bit mask. */ -#define AES_RESET_bp 5 /* AES Software Reset bit position. */ - -#define AES_DECRYPT_bm 0x10 /* Decryption / Direction bit mask. */ -#define AES_DECRYPT_bp 4 /* Decryption / Direction bit position. */ - -#define AES_XOR_bm 0x04 /* State XOR Load Enable bit mask. */ -#define AES_XOR_bp 2 /* State XOR Load Enable bit position. */ - -/* AES.STATUS bit masks and bit positions */ -#define AES_ERROR_bm 0x80 /* AES Error bit mask. */ -#define AES_ERROR_bp 7 /* AES Error bit position. */ - -#define AES_SRIF_bm 0x01 /* State Ready Interrupt Flag bit mask. */ -#define AES_SRIF_bp 0 /* State Ready Interrupt Flag bit position. */ - -/* AES.INTCTRL bit masks and bit positions */ -#define AES_INTLVL_gm 0x03 /* Interrupt level group mask. */ -#define AES_INTLVL_gp 0 /* Interrupt level group position. */ -#define AES_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */ -#define AES_INTLVL0_bp 0 /* Interrupt level bit 0 position. */ -#define AES_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */ -#define AES_INTLVL1_bp 1 /* Interrupt level bit 1 position. */ - -/* CRC - Cyclic Redundancy Checker */ -/* CRC.CTRL bit masks and bit positions */ -#define CRC_RESET_gm 0xC0 /* Reset group mask. */ -#define CRC_RESET_gp 6 /* Reset group position. */ -#define CRC_RESET0_bm (1<<6) /* Reset bit 0 mask. */ -#define CRC_RESET0_bp 6 /* Reset bit 0 position. */ -#define CRC_RESET1_bm (1<<7) /* Reset bit 1 mask. */ -#define CRC_RESET1_bp 7 /* Reset bit 1 position. */ - -#define CRC_CRC32_bm 0x20 /* CRC Mode bit mask. */ -#define CRC_CRC32_bp 5 /* CRC Mode bit position. */ - -#define CRC_SOURCE_gm 0x0F /* Input Source group mask. */ -#define CRC_SOURCE_gp 0 /* Input Source group position. */ -#define CRC_SOURCE0_bm (1<<0) /* Input Source bit 0 mask. */ -#define CRC_SOURCE0_bp 0 /* Input Source bit 0 position. */ -#define CRC_SOURCE1_bm (1<<1) /* Input Source bit 1 mask. */ -#define CRC_SOURCE1_bp 1 /* Input Source bit 1 position. */ -#define CRC_SOURCE2_bm (1<<2) /* Input Source bit 2 mask. */ -#define CRC_SOURCE2_bp 2 /* Input Source bit 2 position. */ -#define CRC_SOURCE3_bm (1<<3) /* Input Source bit 3 mask. */ -#define CRC_SOURCE3_bp 3 /* Input Source bit 3 position. */ - -/* CRC.STATUS bit masks and bit positions */ -#define CRC_ZERO_bm 0x02 /* Zero detection bit mask. */ -#define CRC_ZERO_bp 1 /* Zero detection bit position. */ - -#define CRC_BUSY_bm 0x01 /* Busy bit mask. */ -#define CRC_BUSY_bp 0 /* Busy bit position. */ - -/* DMA - DMA Controller */ -/* DMA_CH.CTRLA bit masks and bit positions */ -#define DMA_CH_ENABLE_bm 0x80 /* Channel Enable bit mask. */ -#define DMA_CH_ENABLE_bp 7 /* Channel Enable bit position. */ - -#define DMA_CH_RESET_bm 0x40 /* Channel Software Reset bit mask. */ -#define DMA_CH_RESET_bp 6 /* Channel Software Reset bit position. */ - -#define DMA_CH_REPEAT_bm 0x20 /* Channel Repeat Mode bit mask. */ -#define DMA_CH_REPEAT_bp 5 /* Channel Repeat Mode bit position. */ - -#define DMA_CH_TRFREQ_bm 0x10 /* Channel Transfer Request bit mask. */ -#define DMA_CH_TRFREQ_bp 4 /* Channel Transfer Request bit position. */ - -#define DMA_CH_SINGLE_bm 0x04 /* Channel Single Shot Data Transfer bit mask. */ -#define DMA_CH_SINGLE_bp 2 /* Channel Single Shot Data Transfer bit position. */ - -#define DMA_CH_BURSTLEN_gm 0x03 /* Channel Transfer Mode group mask. */ -#define DMA_CH_BURSTLEN_gp 0 /* Channel Transfer Mode group position. */ -#define DMA_CH_BURSTLEN0_bm (1<<0) /* Channel Transfer Mode bit 0 mask. */ -#define DMA_CH_BURSTLEN0_bp 0 /* Channel Transfer Mode bit 0 position. */ -#define DMA_CH_BURSTLEN1_bm (1<<1) /* Channel Transfer Mode bit 1 mask. */ -#define DMA_CH_BURSTLEN1_bp 1 /* Channel Transfer Mode bit 1 position. */ - -/* DMA_CH.CTRLB bit masks and bit positions */ -#define DMA_CH_CHBUSY_bm 0x80 /* Block Transfer Busy bit mask. */ -#define DMA_CH_CHBUSY_bp 7 /* Block Transfer Busy bit position. */ - -#define DMA_CH_CHPEND_bm 0x40 /* Block Transfer Pending bit mask. */ -#define DMA_CH_CHPEND_bp 6 /* Block Transfer Pending bit position. */ - -#define DMA_CH_ERRIF_bm 0x20 /* Block Transfer Error Interrupt Flag bit mask. */ -#define DMA_CH_ERRIF_bp 5 /* Block Transfer Error Interrupt Flag bit position. */ - -#define DMA_CH_TRNIF_bm 0x10 /* Transaction Complete Interrup Flag bit mask. */ -#define DMA_CH_TRNIF_bp 4 /* Transaction Complete Interrup Flag bit position. */ - -#define DMA_CH_ERRINTLVL_gm 0x0C /* Transfer Error Interrupt Level group mask. */ -#define DMA_CH_ERRINTLVL_gp 2 /* Transfer Error Interrupt Level group position. */ -#define DMA_CH_ERRINTLVL0_bm (1<<2) /* Transfer Error Interrupt Level bit 0 mask. */ -#define DMA_CH_ERRINTLVL0_bp 2 /* Transfer Error Interrupt Level bit 0 position. */ -#define DMA_CH_ERRINTLVL1_bm (1<<3) /* Transfer Error Interrupt Level bit 1 mask. */ -#define DMA_CH_ERRINTLVL1_bp 3 /* Transfer Error Interrupt Level bit 1 position. */ - -#define DMA_CH_TRNINTLVL_gm 0x03 /* Transaction Complete Interrupt Level group mask. */ -#define DMA_CH_TRNINTLVL_gp 0 /* Transaction Complete Interrupt Level group position. */ -#define DMA_CH_TRNINTLVL0_bm (1<<0) /* Transaction Complete Interrupt Level bit 0 mask. */ -#define DMA_CH_TRNINTLVL0_bp 0 /* Transaction Complete Interrupt Level bit 0 position. */ -#define DMA_CH_TRNINTLVL1_bm (1<<1) /* Transaction Complete Interrupt Level bit 1 mask. */ -#define DMA_CH_TRNINTLVL1_bp 1 /* Transaction Complete Interrupt Level bit 1 position. */ - -/* DMA_CH.ADDRCTRL bit masks and bit positions */ -#define DMA_CH_SRCRELOAD_gm 0xC0 /* Channel Source Address Reload group mask. */ -#define DMA_CH_SRCRELOAD_gp 6 /* Channel Source Address Reload group position. */ -#define DMA_CH_SRCRELOAD0_bm (1<<6) /* Channel Source Address Reload bit 0 mask. */ -#define DMA_CH_SRCRELOAD0_bp 6 /* Channel Source Address Reload bit 0 position. */ -#define DMA_CH_SRCRELOAD1_bm (1<<7) /* Channel Source Address Reload bit 1 mask. */ -#define DMA_CH_SRCRELOAD1_bp 7 /* Channel Source Address Reload bit 1 position. */ - -#define DMA_CH_SRCDIR_gm 0x30 /* Channel Source Address Mode group mask. */ -#define DMA_CH_SRCDIR_gp 4 /* Channel Source Address Mode group position. */ -#define DMA_CH_SRCDIR0_bm (1<<4) /* Channel Source Address Mode bit 0 mask. */ -#define DMA_CH_SRCDIR0_bp 4 /* Channel Source Address Mode bit 0 position. */ -#define DMA_CH_SRCDIR1_bm (1<<5) /* Channel Source Address Mode bit 1 mask. */ -#define DMA_CH_SRCDIR1_bp 5 /* Channel Source Address Mode bit 1 position. */ - -#define DMA_CH_DESTRELOAD_gm 0x0C /* Channel Destination Address Reload group mask. */ -#define DMA_CH_DESTRELOAD_gp 2 /* Channel Destination Address Reload group position. */ -#define DMA_CH_DESTRELOAD0_bm (1<<2) /* Channel Destination Address Reload bit 0 mask. */ -#define DMA_CH_DESTRELOAD0_bp 2 /* Channel Destination Address Reload bit 0 position. */ -#define DMA_CH_DESTRELOAD1_bm (1<<3) /* Channel Destination Address Reload bit 1 mask. */ -#define DMA_CH_DESTRELOAD1_bp 3 /* Channel Destination Address Reload bit 1 position. */ - -#define DMA_CH_DESTDIR_gm 0x03 /* Channel Destination Address Mode group mask. */ -#define DMA_CH_DESTDIR_gp 0 /* Channel Destination Address Mode group position. */ -#define DMA_CH_DESTDIR0_bm (1<<0) /* Channel Destination Address Mode bit 0 mask. */ -#define DMA_CH_DESTDIR0_bp 0 /* Channel Destination Address Mode bit 0 position. */ -#define DMA_CH_DESTDIR1_bm (1<<1) /* Channel Destination Address Mode bit 1 mask. */ -#define DMA_CH_DESTDIR1_bp 1 /* Channel Destination Address Mode bit 1 position. */ - -/* DMA_CH.TRIGSRC bit masks and bit positions */ -#define DMA_CH_TRIGSRC_gm 0xFF /* Channel Trigger Source group mask. */ -#define DMA_CH_TRIGSRC_gp 0 /* Channel Trigger Source group position. */ -#define DMA_CH_TRIGSRC0_bm (1<<0) /* Channel Trigger Source bit 0 mask. */ -#define DMA_CH_TRIGSRC0_bp 0 /* Channel Trigger Source bit 0 position. */ -#define DMA_CH_TRIGSRC1_bm (1<<1) /* Channel Trigger Source bit 1 mask. */ -#define DMA_CH_TRIGSRC1_bp 1 /* Channel Trigger Source bit 1 position. */ -#define DMA_CH_TRIGSRC2_bm (1<<2) /* Channel Trigger Source bit 2 mask. */ -#define DMA_CH_TRIGSRC2_bp 2 /* Channel Trigger Source bit 2 position. */ -#define DMA_CH_TRIGSRC3_bm (1<<3) /* Channel Trigger Source bit 3 mask. */ -#define DMA_CH_TRIGSRC3_bp 3 /* Channel Trigger Source bit 3 position. */ -#define DMA_CH_TRIGSRC4_bm (1<<4) /* Channel Trigger Source bit 4 mask. */ -#define DMA_CH_TRIGSRC4_bp 4 /* Channel Trigger Source bit 4 position. */ -#define DMA_CH_TRIGSRC5_bm (1<<5) /* Channel Trigger Source bit 5 mask. */ -#define DMA_CH_TRIGSRC5_bp 5 /* Channel Trigger Source bit 5 position. */ -#define DMA_CH_TRIGSRC6_bm (1<<6) /* Channel Trigger Source bit 6 mask. */ -#define DMA_CH_TRIGSRC6_bp 6 /* Channel Trigger Source bit 6 position. */ -#define DMA_CH_TRIGSRC7_bm (1<<7) /* Channel Trigger Source bit 7 mask. */ -#define DMA_CH_TRIGSRC7_bp 7 /* Channel Trigger Source bit 7 position. */ - -/* DMA.CTRL bit masks and bit positions */ -#define DMA_ENABLE_bm 0x80 /* Enable bit mask. */ -#define DMA_ENABLE_bp 7 /* Enable bit position. */ - -#define DMA_RESET_bm 0x40 /* Software Reset bit mask. */ -#define DMA_RESET_bp 6 /* Software Reset bit position. */ - -#define DMA_DBUFMODE_gm 0x0C /* Double Buffering Mode group mask. */ -#define DMA_DBUFMODE_gp 2 /* Double Buffering Mode group position. */ -#define DMA_DBUFMODE0_bm (1<<2) /* Double Buffering Mode bit 0 mask. */ -#define DMA_DBUFMODE0_bp 2 /* Double Buffering Mode bit 0 position. */ -#define DMA_DBUFMODE1_bm (1<<3) /* Double Buffering Mode bit 1 mask. */ -#define DMA_DBUFMODE1_bp 3 /* Double Buffering Mode bit 1 position. */ - -#define DMA_PRIMODE_gm 0x03 /* Channel Priority Mode group mask. */ -#define DMA_PRIMODE_gp 0 /* Channel Priority Mode group position. */ -#define DMA_PRIMODE0_bm (1<<0) /* Channel Priority Mode bit 0 mask. */ -#define DMA_PRIMODE0_bp 0 /* Channel Priority Mode bit 0 position. */ -#define DMA_PRIMODE1_bm (1<<1) /* Channel Priority Mode bit 1 mask. */ -#define DMA_PRIMODE1_bp 1 /* Channel Priority Mode bit 1 position. */ - -/* DMA.INTFLAGS bit masks and bit positions */ -#define DMA_CH3ERRIF_bm 0x80 /* Channel 3 Block Transfer Error Interrupt Flag bit mask. */ -#define DMA_CH3ERRIF_bp 7 /* Channel 3 Block Transfer Error Interrupt Flag bit position. */ - -#define DMA_CH2ERRIF_bm 0x40 /* Channel 2 Block Transfer Error Interrupt Flag bit mask. */ -#define DMA_CH2ERRIF_bp 6 /* Channel 2 Block Transfer Error Interrupt Flag bit position. */ - -#define DMA_CH1ERRIF_bm 0x20 /* Channel 1 Block Transfer Error Interrupt Flag bit mask. */ -#define DMA_CH1ERRIF_bp 5 /* Channel 1 Block Transfer Error Interrupt Flag bit position. */ - -#define DMA_CH0ERRIF_bm 0x10 /* Channel 0 Block Transfer Error Interrupt Flag bit mask. */ -#define DMA_CH0ERRIF_bp 4 /* Channel 0 Block Transfer Error Interrupt Flag bit position. */ - -#define DMA_CH3TRNIF_bm 0x08 /* Channel 3 Transaction Complete Interrupt Flag bit mask. */ -#define DMA_CH3TRNIF_bp 3 /* Channel 3 Transaction Complete Interrupt Flag bit position. */ - -#define DMA_CH2TRNIF_bm 0x04 /* Channel 2 Transaction Complete Interrupt Flag bit mask. */ -#define DMA_CH2TRNIF_bp 2 /* Channel 2 Transaction Complete Interrupt Flag bit position. */ - -#define DMA_CH1TRNIF_bm 0x02 /* Channel 1 Transaction Complete Interrupt Flag bit mask. */ -#define DMA_CH1TRNIF_bp 1 /* Channel 1 Transaction Complete Interrupt Flag bit position. */ - -#define DMA_CH0TRNIF_bm 0x01 /* Channel 0 Transaction Complete Interrupt Flag bit mask. */ -#define DMA_CH0TRNIF_bp 0 /* Channel 0 Transaction Complete Interrupt Flag bit position. */ - -/* DMA.STATUS bit masks and bit positions */ -#define DMA_CH3BUSY_bm 0x80 /* Channel 3 Block Transfer Busy bit mask. */ -#define DMA_CH3BUSY_bp 7 /* Channel 3 Block Transfer Busy bit position. */ - -#define DMA_CH2BUSY_bm 0x40 /* Channel 2 Block Transfer Busy bit mask. */ -#define DMA_CH2BUSY_bp 6 /* Channel 2 Block Transfer Busy bit position. */ - -#define DMA_CH1BUSY_bm 0x20 /* Channel 1 Block Transfer Busy bit mask. */ -#define DMA_CH1BUSY_bp 5 /* Channel 1 Block Transfer Busy bit position. */ - -#define DMA_CH0BUSY_bm 0x10 /* Channel 0 Block Transfer Busy bit mask. */ -#define DMA_CH0BUSY_bp 4 /* Channel 0 Block Transfer Busy bit position. */ - -#define DMA_CH3PEND_bm 0x08 /* Channel 3 Block Transfer Pending bit mask. */ -#define DMA_CH3PEND_bp 3 /* Channel 3 Block Transfer Pending bit position. */ - -#define DMA_CH2PEND_bm 0x04 /* Channel 2 Block Transfer Pending bit mask. */ -#define DMA_CH2PEND_bp 2 /* Channel 2 Block Transfer Pending bit position. */ - -#define DMA_CH1PEND_bm 0x02 /* Channel 1 Block Transfer Pending bit mask. */ -#define DMA_CH1PEND_bp 1 /* Channel 1 Block Transfer Pending bit position. */ - -#define DMA_CH0PEND_bm 0x01 /* Channel 0 Block Transfer Pending bit mask. */ -#define DMA_CH0PEND_bp 0 /* Channel 0 Block Transfer Pending bit position. */ - -/* EVSYS - Event System */ -/* EVSYS.CH0MUX bit masks and bit positions */ -#define EVSYS_CHMUX_gm 0xFF /* Event Channel 0 Multiplexer group mask. */ -#define EVSYS_CHMUX_gp 0 /* Event Channel 0 Multiplexer group position. */ -#define EVSYS_CHMUX0_bm (1<<0) /* Event Channel 0 Multiplexer bit 0 mask. */ -#define EVSYS_CHMUX0_bp 0 /* Event Channel 0 Multiplexer bit 0 position. */ -#define EVSYS_CHMUX1_bm (1<<1) /* Event Channel 0 Multiplexer bit 1 mask. */ -#define EVSYS_CHMUX1_bp 1 /* Event Channel 0 Multiplexer bit 1 position. */ -#define EVSYS_CHMUX2_bm (1<<2) /* Event Channel 0 Multiplexer bit 2 mask. */ -#define EVSYS_CHMUX2_bp 2 /* Event Channel 0 Multiplexer bit 2 position. */ -#define EVSYS_CHMUX3_bm (1<<3) /* Event Channel 0 Multiplexer bit 3 mask. */ -#define EVSYS_CHMUX3_bp 3 /* Event Channel 0 Multiplexer bit 3 position. */ -#define EVSYS_CHMUX4_bm (1<<4) /* Event Channel 0 Multiplexer bit 4 mask. */ -#define EVSYS_CHMUX4_bp 4 /* Event Channel 0 Multiplexer bit 4 position. */ -#define EVSYS_CHMUX5_bm (1<<5) /* Event Channel 0 Multiplexer bit 5 mask. */ -#define EVSYS_CHMUX5_bp 5 /* Event Channel 0 Multiplexer bit 5 position. */ -#define EVSYS_CHMUX6_bm (1<<6) /* Event Channel 0 Multiplexer bit 6 mask. */ -#define EVSYS_CHMUX6_bp 6 /* Event Channel 0 Multiplexer bit 6 position. */ -#define EVSYS_CHMUX7_bm (1<<7) /* Event Channel 0 Multiplexer bit 7 mask. */ -#define EVSYS_CHMUX7_bp 7 /* Event Channel 0 Multiplexer bit 7 position. */ - -/* EVSYS.CH1MUX bit masks and bit positions */ -/* EVSYS_CHMUX Predefined. */ -/* EVSYS_CHMUX Predefined. */ - -/* EVSYS.CH2MUX bit masks and bit positions */ -/* EVSYS_CHMUX Predefined. */ -/* EVSYS_CHMUX Predefined. */ - -/* EVSYS.CH3MUX bit masks and bit positions */ -/* EVSYS_CHMUX Predefined. */ -/* EVSYS_CHMUX Predefined. */ - -/* EVSYS.CH4MUX bit masks and bit positions */ -/* EVSYS_CHMUX Predefined. */ -/* EVSYS_CHMUX Predefined. */ - -/* EVSYS.CH5MUX bit masks and bit positions */ -/* EVSYS_CHMUX Predefined. */ -/* EVSYS_CHMUX Predefined. */ - -/* EVSYS.CH6MUX bit masks and bit positions */ -/* EVSYS_CHMUX Predefined. */ -/* EVSYS_CHMUX Predefined. */ - -/* EVSYS.CH7MUX bit masks and bit positions */ -/* EVSYS_CHMUX Predefined. */ -/* EVSYS_CHMUX Predefined. */ - -/* EVSYS.CH0CTRL bit masks and bit positions */ -#define EVSYS_QDIRM_gm 0x60 /* Quadrature Decoder Index Recognition Mode group mask. */ -#define EVSYS_QDIRM_gp 5 /* Quadrature Decoder Index Recognition Mode group position. */ -#define EVSYS_QDIRM0_bm (1<<5) /* Quadrature Decoder Index Recognition Mode bit 0 mask. */ -#define EVSYS_QDIRM0_bp 5 /* Quadrature Decoder Index Recognition Mode bit 0 position. */ -#define EVSYS_QDIRM1_bm (1<<6) /* Quadrature Decoder Index Recognition Mode bit 1 mask. */ -#define EVSYS_QDIRM1_bp 6 /* Quadrature Decoder Index Recognition Mode bit 1 position. */ - -#define EVSYS_QDIEN_bm 0x10 /* Quadrature Decoder Index Enable bit mask. */ -#define EVSYS_QDIEN_bp 4 /* Quadrature Decoder Index Enable bit position. */ - -#define EVSYS_QDEN_bm 0x08 /* Quadrature Decoder Enable bit mask. */ -#define EVSYS_QDEN_bp 3 /* Quadrature Decoder Enable bit position. */ - -#define EVSYS_DIGFILT_gm 0x07 /* Digital Filter group mask. */ -#define EVSYS_DIGFILT_gp 0 /* Digital Filter group position. */ -#define EVSYS_DIGFILT0_bm (1<<0) /* Digital Filter bit 0 mask. */ -#define EVSYS_DIGFILT0_bp 0 /* Digital Filter bit 0 position. */ -#define EVSYS_DIGFILT1_bm (1<<1) /* Digital Filter bit 1 mask. */ -#define EVSYS_DIGFILT1_bp 1 /* Digital Filter bit 1 position. */ -#define EVSYS_DIGFILT2_bm (1<<2) /* Digital Filter bit 2 mask. */ -#define EVSYS_DIGFILT2_bp 2 /* Digital Filter bit 2 position. */ - -/* EVSYS.CH1CTRL bit masks and bit positions */ -/* EVSYS_DIGFILT Predefined. */ -/* EVSYS_DIGFILT Predefined. */ - -/* EVSYS.CH2CTRL bit masks and bit positions */ -/* EVSYS_QDIRM Predefined. */ -/* EVSYS_QDIRM Predefined. */ - -/* EVSYS_QDIEN Predefined. */ -/* EVSYS_QDIEN Predefined. */ - -/* EVSYS_QDEN Predefined. */ -/* EVSYS_QDEN Predefined. */ - -/* EVSYS_DIGFILT Predefined. */ -/* EVSYS_DIGFILT Predefined. */ - -/* EVSYS.CH3CTRL bit masks and bit positions */ -/* EVSYS_DIGFILT Predefined. */ -/* EVSYS_DIGFILT Predefined. */ - -/* EVSYS.CH4CTRL bit masks and bit positions */ -/* EVSYS_QDIRM Predefined. */ -/* EVSYS_QDIRM Predefined. */ - -/* EVSYS_QDIEN Predefined. */ -/* EVSYS_QDIEN Predefined. */ - -/* EVSYS_QDEN Predefined. */ -/* EVSYS_QDEN Predefined. */ - -/* EVSYS_DIGFILT Predefined. */ -/* EVSYS_DIGFILT Predefined. */ - -/* EVSYS.CH5CTRL bit masks and bit positions */ -/* EVSYS_DIGFILT Predefined. */ -/* EVSYS_DIGFILT Predefined. */ - -/* EVSYS.CH6CTRL bit masks and bit positions */ -/* EVSYS_DIGFILT Predefined. */ -/* EVSYS_DIGFILT Predefined. */ - -/* EVSYS.CH7CTRL bit masks and bit positions */ -/* EVSYS_DIGFILT Predefined. */ -/* EVSYS_DIGFILT Predefined. */ - -/* NVM - Non Volatile Memory Controller */ -/* NVM.CMD bit masks and bit positions */ -#define NVM_CMD_gm 0x7F /* Command group mask. */ -#define NVM_CMD_gp 0 /* Command group position. */ -#define NVM_CMD0_bm (1<<0) /* Command bit 0 mask. */ -#define NVM_CMD0_bp 0 /* Command bit 0 position. */ -#define NVM_CMD1_bm (1<<1) /* Command bit 1 mask. */ -#define NVM_CMD1_bp 1 /* Command bit 1 position. */ -#define NVM_CMD2_bm (1<<2) /* Command bit 2 mask. */ -#define NVM_CMD2_bp 2 /* Command bit 2 position. */ -#define NVM_CMD3_bm (1<<3) /* Command bit 3 mask. */ -#define NVM_CMD3_bp 3 /* Command bit 3 position. */ -#define NVM_CMD4_bm (1<<4) /* Command bit 4 mask. */ -#define NVM_CMD4_bp 4 /* Command bit 4 position. */ -#define NVM_CMD5_bm (1<<5) /* Command bit 5 mask. */ -#define NVM_CMD5_bp 5 /* Command bit 5 position. */ -#define NVM_CMD6_bm (1<<6) /* Command bit 6 mask. */ -#define NVM_CMD6_bp 6 /* Command bit 6 position. */ - -/* NVM.CTRLA bit masks and bit positions */ -#define NVM_CMDEX_bm 0x01 /* Command Execute bit mask. */ -#define NVM_CMDEX_bp 0 /* Command Execute bit position. */ - -/* NVM.CTRLB bit masks and bit positions */ -#define NVM_EEMAPEN_bm 0x08 /* EEPROM Mapping Enable bit mask. */ -#define NVM_EEMAPEN_bp 3 /* EEPROM Mapping Enable bit position. */ - -#define NVM_FPRM_bm 0x04 /* Flash Power Reduction Enable bit mask. */ -#define NVM_FPRM_bp 2 /* Flash Power Reduction Enable bit position. */ - -#define NVM_EPRM_bm 0x02 /* EEPROM Power Reduction Enable bit mask. */ -#define NVM_EPRM_bp 1 /* EEPROM Power Reduction Enable bit position. */ - -#define NVM_SPMLOCK_bm 0x01 /* SPM Lock bit mask. */ -#define NVM_SPMLOCK_bp 0 /* SPM Lock bit position. */ - -/* NVM.INTCTRL bit masks and bit positions */ -#define NVM_SPMLVL_gm 0x0C /* SPM Interrupt Level group mask. */ -#define NVM_SPMLVL_gp 2 /* SPM Interrupt Level group position. */ -#define NVM_SPMLVL0_bm (1<<2) /* SPM Interrupt Level bit 0 mask. */ -#define NVM_SPMLVL0_bp 2 /* SPM Interrupt Level bit 0 position. */ -#define NVM_SPMLVL1_bm (1<<3) /* SPM Interrupt Level bit 1 mask. */ -#define NVM_SPMLVL1_bp 3 /* SPM Interrupt Level bit 1 position. */ - -#define NVM_EELVL_gm 0x03 /* EEPROM Interrupt Level group mask. */ -#define NVM_EELVL_gp 0 /* EEPROM Interrupt Level group position. */ -#define NVM_EELVL0_bm (1<<0) /* EEPROM Interrupt Level bit 0 mask. */ -#define NVM_EELVL0_bp 0 /* EEPROM Interrupt Level bit 0 position. */ -#define NVM_EELVL1_bm (1<<1) /* EEPROM Interrupt Level bit 1 mask. */ -#define NVM_EELVL1_bp 1 /* EEPROM Interrupt Level bit 1 position. */ - -/* NVM.STATUS bit masks and bit positions */ -#define NVM_NVMBUSY_bm 0x80 /* Non-volatile Memory Busy bit mask. */ -#define NVM_NVMBUSY_bp 7 /* Non-volatile Memory Busy bit position. */ - -#define NVM_FBUSY_bm 0x40 /* Flash Memory Busy bit mask. */ -#define NVM_FBUSY_bp 6 /* Flash Memory Busy bit position. */ - -#define NVM_EELOAD_bm 0x02 /* EEPROM Page Buffer Active Loading bit mask. */ -#define NVM_EELOAD_bp 1 /* EEPROM Page Buffer Active Loading bit position. */ - -#define NVM_FLOAD_bm 0x01 /* Flash Page Buffer Active Loading bit mask. */ -#define NVM_FLOAD_bp 0 /* Flash Page Buffer Active Loading bit position. */ - -/* NVM.LOCKBITS bit masks and bit positions */ -#define NVM_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ -#define NVM_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ -#define NVM_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ -#define NVM_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ -#define NVM_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ -#define NVM_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ - -#define NVM_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ -#define NVM_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ -#define NVM_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ -#define NVM_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ -#define NVM_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ -#define NVM_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ - -#define NVM_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ -#define NVM_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ -#define NVM_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ -#define NVM_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ -#define NVM_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ -#define NVM_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ - -#define NVM_LB_gm 0x03 /* Lock Bits group mask. */ -#define NVM_LB_gp 0 /* Lock Bits group position. */ -#define NVM_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ -#define NVM_LB0_bp 0 /* Lock Bits bit 0 position. */ -#define NVM_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ -#define NVM_LB1_bp 1 /* Lock Bits bit 1 position. */ - -/* ADC - Analog/Digital Converter */ -/* ADC_CH.CTRL bit masks and bit positions */ -#define ADC_CH_START_bm 0x80 /* Channel Start Conversion bit mask. */ -#define ADC_CH_START_bp 7 /* Channel Start Conversion bit position. */ - -#define ADC_CH_GAIN_gm 0x1C /* Gain Factor group mask. */ -#define ADC_CH_GAIN_gp 2 /* Gain Factor group position. */ -#define ADC_CH_GAIN0_bm (1<<2) /* Gain Factor bit 0 mask. */ -#define ADC_CH_GAIN0_bp 2 /* Gain Factor bit 0 position. */ -#define ADC_CH_GAIN1_bm (1<<3) /* Gain Factor bit 1 mask. */ -#define ADC_CH_GAIN1_bp 3 /* Gain Factor bit 1 position. */ -#define ADC_CH_GAIN2_bm (1<<4) /* Gain Factor bit 2 mask. */ -#define ADC_CH_GAIN2_bp 4 /* Gain Factor bit 2 position. */ - -#define ADC_CH_INPUTMODE_gm 0x03 /* Input Mode Select group mask. */ -#define ADC_CH_INPUTMODE_gp 0 /* Input Mode Select group position. */ -#define ADC_CH_INPUTMODE0_bm (1<<0) /* Input Mode Select bit 0 mask. */ -#define ADC_CH_INPUTMODE0_bp 0 /* Input Mode Select bit 0 position. */ -#define ADC_CH_INPUTMODE1_bm (1<<1) /* Input Mode Select bit 1 mask. */ -#define ADC_CH_INPUTMODE1_bp 1 /* Input Mode Select bit 1 position. */ - -/* ADC_CH.MUXCTRL bit masks and bit positions */ -#define ADC_CH_MUXPOS_gm 0x78 /* MUX selection on Positive ADC input group mask. */ -#define ADC_CH_MUXPOS_gp 3 /* MUX selection on Positive ADC input group position. */ -#define ADC_CH_MUXPOS0_bm (1<<3) /* MUX selection on Positive ADC input bit 0 mask. */ -#define ADC_CH_MUXPOS0_bp 3 /* MUX selection on Positive ADC input bit 0 position. */ -#define ADC_CH_MUXPOS1_bm (1<<4) /* MUX selection on Positive ADC input bit 1 mask. */ -#define ADC_CH_MUXPOS1_bp 4 /* MUX selection on Positive ADC input bit 1 position. */ -#define ADC_CH_MUXPOS2_bm (1<<5) /* MUX selection on Positive ADC input bit 2 mask. */ -#define ADC_CH_MUXPOS2_bp 5 /* MUX selection on Positive ADC input bit 2 position. */ -#define ADC_CH_MUXPOS3_bm (1<<6) /* MUX selection on Positive ADC input bit 3 mask. */ -#define ADC_CH_MUXPOS3_bp 6 /* MUX selection on Positive ADC input bit 3 position. */ - -#define ADC_CH_MUXINT_gm 0x78 /* MUX selection on Internal ADC input group mask. */ -#define ADC_CH_MUXINT_gp 3 /* MUX selection on Internal ADC input group position. */ -#define ADC_CH_MUXINT0_bm (1<<3) /* MUX selection on Internal ADC input bit 0 mask. */ -#define ADC_CH_MUXINT0_bp 3 /* MUX selection on Internal ADC input bit 0 position. */ -#define ADC_CH_MUXINT1_bm (1<<4) /* MUX selection on Internal ADC input bit 1 mask. */ -#define ADC_CH_MUXINT1_bp 4 /* MUX selection on Internal ADC input bit 1 position. */ -#define ADC_CH_MUXINT2_bm (1<<5) /* MUX selection on Internal ADC input bit 2 mask. */ -#define ADC_CH_MUXINT2_bp 5 /* MUX selection on Internal ADC input bit 2 position. */ -#define ADC_CH_MUXINT3_bm (1<<6) /* MUX selection on Internal ADC input bit 3 mask. */ -#define ADC_CH_MUXINT3_bp 6 /* MUX selection on Internal ADC input bit 3 position. */ - -#define ADC_CH_MUXNEG_gm 0x07 /* MUX selection on Negative ADC input group mask. */ -#define ADC_CH_MUXNEG_gp 0 /* MUX selection on Negative ADC input group position. */ -#define ADC_CH_MUXNEG0_bm (1<<0) /* MUX selection on Negative ADC input bit 0 mask. */ -#define ADC_CH_MUXNEG0_bp 0 /* MUX selection on Negative ADC input bit 0 position. */ -#define ADC_CH_MUXNEG1_bm (1<<1) /* MUX selection on Negative ADC input bit 1 mask. */ -#define ADC_CH_MUXNEG1_bp 1 /* MUX selection on Negative ADC input bit 1 position. */ -#define ADC_CH_MUXNEG2_bm (1<<2) /* MUX selection on Negative ADC input bit 2 mask. */ -#define ADC_CH_MUXNEG2_bp 2 /* MUX selection on Negative ADC input bit 2 position. */ - -/* ADC_CH.INTCTRL bit masks and bit positions */ -#define ADC_CH_INTMODE_gm 0x0C /* Interrupt Mode group mask. */ -#define ADC_CH_INTMODE_gp 2 /* Interrupt Mode group position. */ -#define ADC_CH_INTMODE0_bm (1<<2) /* Interrupt Mode bit 0 mask. */ -#define ADC_CH_INTMODE0_bp 2 /* Interrupt Mode bit 0 position. */ -#define ADC_CH_INTMODE1_bm (1<<3) /* Interrupt Mode bit 1 mask. */ -#define ADC_CH_INTMODE1_bp 3 /* Interrupt Mode bit 1 position. */ - -#define ADC_CH_INTLVL_gm 0x03 /* Interrupt Level group mask. */ -#define ADC_CH_INTLVL_gp 0 /* Interrupt Level group position. */ -#define ADC_CH_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */ -#define ADC_CH_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */ -#define ADC_CH_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ -#define ADC_CH_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */ - -/* ADC_CH.INTFLAGS bit masks and bit positions */ -#define ADC_CH_CHIF_bm 0x01 /* Channel Interrupt Flag bit mask. */ -#define ADC_CH_CHIF_bp 0 /* Channel Interrupt Flag bit position. */ - -/* ADC_CH.SCAN bit masks and bit positions */ -#define ADC_CH_OFFSET_gm 0xF0 /* Positive MUX setting offset group mask. */ -#define ADC_CH_OFFSET_gp 4 /* Positive MUX setting offset group position. */ -#define ADC_CH_OFFSET0_bm (1<<4) /* Positive MUX setting offset bit 0 mask. */ -#define ADC_CH_OFFSET0_bp 4 /* Positive MUX setting offset bit 0 position. */ -#define ADC_CH_OFFSET1_bm (1<<5) /* Positive MUX setting offset bit 1 mask. */ -#define ADC_CH_OFFSET1_bp 5 /* Positive MUX setting offset bit 1 position. */ -#define ADC_CH_OFFSET2_bm (1<<6) /* Positive MUX setting offset bit 2 mask. */ -#define ADC_CH_OFFSET2_bp 6 /* Positive MUX setting offset bit 2 position. */ -#define ADC_CH_OFFSET3_bm (1<<7) /* Positive MUX setting offset bit 3 mask. */ -#define ADC_CH_OFFSET3_bp 7 /* Positive MUX setting offset bit 3 position. */ - -#define ADC_CH_SCANNUM_gm 0x0F /* Number of Channels included in scan group mask. */ -#define ADC_CH_SCANNUM_gp 0 /* Number of Channels included in scan group position. */ -#define ADC_CH_SCANNUM0_bm (1<<0) /* Number of Channels included in scan bit 0 mask. */ -#define ADC_CH_SCANNUM0_bp 0 /* Number of Channels included in scan bit 0 position. */ -#define ADC_CH_SCANNUM1_bm (1<<1) /* Number of Channels included in scan bit 1 mask. */ -#define ADC_CH_SCANNUM1_bp 1 /* Number of Channels included in scan bit 1 position. */ -#define ADC_CH_SCANNUM2_bm (1<<2) /* Number of Channels included in scan bit 2 mask. */ -#define ADC_CH_SCANNUM2_bp 2 /* Number of Channels included in scan bit 2 position. */ -#define ADC_CH_SCANNUM3_bm (1<<3) /* Number of Channels included in scan bit 3 mask. */ -#define ADC_CH_SCANNUM3_bp 3 /* Number of Channels included in scan bit 3 position. */ - -/* ADC.CTRLA bit masks and bit positions */ -#define ADC_DMASEL_gm 0xC0 /* DMA Selection group mask. */ -#define ADC_DMASEL_gp 6 /* DMA Selection group position. */ -#define ADC_DMASEL0_bm (1<<6) /* DMA Selection bit 0 mask. */ -#define ADC_DMASEL0_bp 6 /* DMA Selection bit 0 position. */ -#define ADC_DMASEL1_bm (1<<7) /* DMA Selection bit 1 mask. */ -#define ADC_DMASEL1_bp 7 /* DMA Selection bit 1 position. */ - -#define ADC_CH3START_bm 0x20 /* Channel 3 Start Conversion bit mask. */ -#define ADC_CH3START_bp 5 /* Channel 3 Start Conversion bit position. */ - -#define ADC_CH2START_bm 0x10 /* Channel 2 Start Conversion bit mask. */ -#define ADC_CH2START_bp 4 /* Channel 2 Start Conversion bit position. */ - -#define ADC_CH1START_bm 0x08 /* Channel 1 Start Conversion bit mask. */ -#define ADC_CH1START_bp 3 /* Channel 1 Start Conversion bit position. */ - -#define ADC_CH0START_bm 0x04 /* Channel 0 Start Conversion bit mask. */ -#define ADC_CH0START_bp 2 /* Channel 0 Start Conversion bit position. */ - -#define ADC_FLUSH_bm 0x02 /* Flush Pipeline bit mask. */ -#define ADC_FLUSH_bp 1 /* Flush Pipeline bit position. */ - -#define ADC_ENABLE_bm 0x01 /* Enable ADC bit mask. */ -#define ADC_ENABLE_bp 0 /* Enable ADC bit position. */ - -/* ADC.CTRLB bit masks and bit positions */ -#define ADC_IMPMODE_bm 0x80 /* Gain Stage Impedance Mode bit mask. */ -#define ADC_IMPMODE_bp 7 /* Gain Stage Impedance Mode bit position. */ - -#define ADC_CURRLIMIT_gm 0x60 /* Current Limitation group mask. */ -#define ADC_CURRLIMIT_gp 5 /* Current Limitation group position. */ -#define ADC_CURRLIMIT0_bm (1<<5) /* Current Limitation bit 0 mask. */ -#define ADC_CURRLIMIT0_bp 5 /* Current Limitation bit 0 position. */ -#define ADC_CURRLIMIT1_bm (1<<6) /* Current Limitation bit 1 mask. */ -#define ADC_CURRLIMIT1_bp 6 /* Current Limitation bit 1 position. */ - -#define ADC_CONMODE_bm 0x10 /* Conversion Mode bit mask. */ -#define ADC_CONMODE_bp 4 /* Conversion Mode bit position. */ - -#define ADC_FREERUN_bm 0x08 /* Free Running Mode Enable bit mask. */ -#define ADC_FREERUN_bp 3 /* Free Running Mode Enable bit position. */ - -#define ADC_RESOLUTION_gm 0x06 /* Result Resolution group mask. */ -#define ADC_RESOLUTION_gp 1 /* Result Resolution group position. */ -#define ADC_RESOLUTION0_bm (1<<1) /* Result Resolution bit 0 mask. */ -#define ADC_RESOLUTION0_bp 1 /* Result Resolution bit 0 position. */ -#define ADC_RESOLUTION1_bm (1<<2) /* Result Resolution bit 1 mask. */ -#define ADC_RESOLUTION1_bp 2 /* Result Resolution bit 1 position. */ - -/* ADC.REFCTRL bit masks and bit positions */ -#define ADC_REFSEL_gm 0x70 /* Reference Selection group mask. */ -#define ADC_REFSEL_gp 4 /* Reference Selection group position. */ -#define ADC_REFSEL0_bm (1<<4) /* Reference Selection bit 0 mask. */ -#define ADC_REFSEL0_bp 4 /* Reference Selection bit 0 position. */ -#define ADC_REFSEL1_bm (1<<5) /* Reference Selection bit 1 mask. */ -#define ADC_REFSEL1_bp 5 /* Reference Selection bit 1 position. */ -#define ADC_REFSEL2_bm (1<<6) /* Reference Selection bit 2 mask. */ -#define ADC_REFSEL2_bp 6 /* Reference Selection bit 2 position. */ - -#define ADC_BANDGAP_bm 0x02 /* Bandgap enable bit mask. */ -#define ADC_BANDGAP_bp 1 /* Bandgap enable bit position. */ - -#define ADC_TEMPREF_bm 0x01 /* Temperature Reference Enable bit mask. */ -#define ADC_TEMPREF_bp 0 /* Temperature Reference Enable bit position. */ - -/* ADC.EVCTRL bit masks and bit positions */ -#define ADC_SWEEP_gm 0xC0 /* Channel Sweep Selection group mask. */ -#define ADC_SWEEP_gp 6 /* Channel Sweep Selection group position. */ -#define ADC_SWEEP0_bm (1<<6) /* Channel Sweep Selection bit 0 mask. */ -#define ADC_SWEEP0_bp 6 /* Channel Sweep Selection bit 0 position. */ -#define ADC_SWEEP1_bm (1<<7) /* Channel Sweep Selection bit 1 mask. */ -#define ADC_SWEEP1_bp 7 /* Channel Sweep Selection bit 1 position. */ - -#define ADC_EVSEL_gm 0x38 /* Event Input Select group mask. */ -#define ADC_EVSEL_gp 3 /* Event Input Select group position. */ -#define ADC_EVSEL0_bm (1<<3) /* Event Input Select bit 0 mask. */ -#define ADC_EVSEL0_bp 3 /* Event Input Select bit 0 position. */ -#define ADC_EVSEL1_bm (1<<4) /* Event Input Select bit 1 mask. */ -#define ADC_EVSEL1_bp 4 /* Event Input Select bit 1 position. */ -#define ADC_EVSEL2_bm (1<<5) /* Event Input Select bit 2 mask. */ -#define ADC_EVSEL2_bp 5 /* Event Input Select bit 2 position. */ - -#define ADC_EVACT_gm 0x07 /* Event Action Select group mask. */ -#define ADC_EVACT_gp 0 /* Event Action Select group position. */ -#define ADC_EVACT0_bm (1<<0) /* Event Action Select bit 0 mask. */ -#define ADC_EVACT0_bp 0 /* Event Action Select bit 0 position. */ -#define ADC_EVACT1_bm (1<<1) /* Event Action Select bit 1 mask. */ -#define ADC_EVACT1_bp 1 /* Event Action Select bit 1 position. */ -#define ADC_EVACT2_bm (1<<2) /* Event Action Select bit 2 mask. */ -#define ADC_EVACT2_bp 2 /* Event Action Select bit 2 position. */ - -/* ADC.PRESCALER bit masks and bit positions */ -#define ADC_PRESCALER_gm 0x07 /* Clock Prescaler Selection group mask. */ -#define ADC_PRESCALER_gp 0 /* Clock Prescaler Selection group position. */ -#define ADC_PRESCALER0_bm (1<<0) /* Clock Prescaler Selection bit 0 mask. */ -#define ADC_PRESCALER0_bp 0 /* Clock Prescaler Selection bit 0 position. */ -#define ADC_PRESCALER1_bm (1<<1) /* Clock Prescaler Selection bit 1 mask. */ -#define ADC_PRESCALER1_bp 1 /* Clock Prescaler Selection bit 1 position. */ -#define ADC_PRESCALER2_bm (1<<2) /* Clock Prescaler Selection bit 2 mask. */ -#define ADC_PRESCALER2_bp 2 /* Clock Prescaler Selection bit 2 position. */ - -/* ADC.INTFLAGS bit masks and bit positions */ -#define ADC_CH3IF_bm 0x08 /* Channel 3 Interrupt Flag bit mask. */ -#define ADC_CH3IF_bp 3 /* Channel 3 Interrupt Flag bit position. */ - -#define ADC_CH2IF_bm 0x04 /* Channel 2 Interrupt Flag bit mask. */ -#define ADC_CH2IF_bp 2 /* Channel 2 Interrupt Flag bit position. */ - -#define ADC_CH1IF_bm 0x02 /* Channel 1 Interrupt Flag bit mask. */ -#define ADC_CH1IF_bp 1 /* Channel 1 Interrupt Flag bit position. */ - -#define ADC_CH0IF_bm 0x01 /* Channel 0 Interrupt Flag bit mask. */ -#define ADC_CH0IF_bp 0 /* Channel 0 Interrupt Flag bit position. */ - -/* DAC - Digital/Analog Converter */ -/* DAC.CTRLA bit masks and bit positions */ -#define DAC_IDOEN_bm 0x10 /* Internal Output Enable bit mask. */ -#define DAC_IDOEN_bp 4 /* Internal Output Enable bit position. */ - -#define DAC_CH1EN_bm 0x08 /* Channel 1 Output Enable bit mask. */ -#define DAC_CH1EN_bp 3 /* Channel 1 Output Enable bit position. */ - -#define DAC_CH0EN_bm 0x04 /* Channel 0 Output Enable bit mask. */ -#define DAC_CH0EN_bp 2 /* Channel 0 Output Enable bit position. */ - -#define DAC_LPMODE_bm 0x02 /* Low Power Mode bit mask. */ -#define DAC_LPMODE_bp 1 /* Low Power Mode bit position. */ - -#define DAC_ENABLE_bm 0x01 /* Enable bit mask. */ -#define DAC_ENABLE_bp 0 /* Enable bit position. */ - -/* DAC.CTRLB bit masks and bit positions */ -#define DAC_CHSEL_gm 0x60 /* Channel Select group mask. */ -#define DAC_CHSEL_gp 5 /* Channel Select group position. */ -#define DAC_CHSEL0_bm (1<<5) /* Channel Select bit 0 mask. */ -#define DAC_CHSEL0_bp 5 /* Channel Select bit 0 position. */ -#define DAC_CHSEL1_bm (1<<6) /* Channel Select bit 1 mask. */ -#define DAC_CHSEL1_bp 6 /* Channel Select bit 1 position. */ - -#define DAC_CH1TRIG_bm 0x02 /* Channel 1 Event Trig Enable bit mask. */ -#define DAC_CH1TRIG_bp 1 /* Channel 1 Event Trig Enable bit position. */ - -#define DAC_CH0TRIG_bm 0x01 /* Channel 0 Event Trig Enable bit mask. */ -#define DAC_CH0TRIG_bp 0 /* Channel 0 Event Trig Enable bit position. */ - -/* DAC.CTRLC bit masks and bit positions */ -#define DAC_REFSEL_gm 0x18 /* Reference Select group mask. */ -#define DAC_REFSEL_gp 3 /* Reference Select group position. */ -#define DAC_REFSEL0_bm (1<<3) /* Reference Select bit 0 mask. */ -#define DAC_REFSEL0_bp 3 /* Reference Select bit 0 position. */ -#define DAC_REFSEL1_bm (1<<4) /* Reference Select bit 1 mask. */ -#define DAC_REFSEL1_bp 4 /* Reference Select bit 1 position. */ - -#define DAC_LEFTADJ_bm 0x01 /* Left-adjust Result bit mask. */ -#define DAC_LEFTADJ_bp 0 /* Left-adjust Result bit position. */ - -/* DAC.EVCTRL bit masks and bit positions */ -#define DAC_EVSPLIT_bm 0x08 /* Separate Event Channel Input for Channel 1 bit mask. */ -#define DAC_EVSPLIT_bp 3 /* Separate Event Channel Input for Channel 1 bit position. */ - -#define DAC_EVSEL_gm 0x07 /* Event Input Selection group mask. */ -#define DAC_EVSEL_gp 0 /* Event Input Selection group position. */ -#define DAC_EVSEL0_bm (1<<0) /* Event Input Selection bit 0 mask. */ -#define DAC_EVSEL0_bp 0 /* Event Input Selection bit 0 position. */ -#define DAC_EVSEL1_bm (1<<1) /* Event Input Selection bit 1 mask. */ -#define DAC_EVSEL1_bp 1 /* Event Input Selection bit 1 position. */ -#define DAC_EVSEL2_bm (1<<2) /* Event Input Selection bit 2 mask. */ -#define DAC_EVSEL2_bp 2 /* Event Input Selection bit 2 position. */ - -/* DAC.STATUS bit masks and bit positions */ -#define DAC_CH1DRE_bm 0x02 /* Channel 1 Data Register Empty bit mask. */ -#define DAC_CH1DRE_bp 1 /* Channel 1 Data Register Empty bit position. */ - -#define DAC_CH0DRE_bm 0x01 /* Channel 0 Data Register Empty bit mask. */ -#define DAC_CH0DRE_bp 0 /* Channel 0 Data Register Empty bit position. */ - -/* DAC.CH0GAINCAL bit masks and bit positions */ -#define DAC_CH0GAINCAL_gm 0x7F /* Gain Calibration group mask. */ -#define DAC_CH0GAINCAL_gp 0 /* Gain Calibration group position. */ -#define DAC_CH0GAINCAL0_bm (1<<0) /* Gain Calibration bit 0 mask. */ -#define DAC_CH0GAINCAL0_bp 0 /* Gain Calibration bit 0 position. */ -#define DAC_CH0GAINCAL1_bm (1<<1) /* Gain Calibration bit 1 mask. */ -#define DAC_CH0GAINCAL1_bp 1 /* Gain Calibration bit 1 position. */ -#define DAC_CH0GAINCAL2_bm (1<<2) /* Gain Calibration bit 2 mask. */ -#define DAC_CH0GAINCAL2_bp 2 /* Gain Calibration bit 2 position. */ -#define DAC_CH0GAINCAL3_bm (1<<3) /* Gain Calibration bit 3 mask. */ -#define DAC_CH0GAINCAL3_bp 3 /* Gain Calibration bit 3 position. */ -#define DAC_CH0GAINCAL4_bm (1<<4) /* Gain Calibration bit 4 mask. */ -#define DAC_CH0GAINCAL4_bp 4 /* Gain Calibration bit 4 position. */ -#define DAC_CH0GAINCAL5_bm (1<<5) /* Gain Calibration bit 5 mask. */ -#define DAC_CH0GAINCAL5_bp 5 /* Gain Calibration bit 5 position. */ -#define DAC_CH0GAINCAL6_bm (1<<6) /* Gain Calibration bit 6 mask. */ -#define DAC_CH0GAINCAL6_bp 6 /* Gain Calibration bit 6 position. */ - -/* DAC.CH0OFFSETCAL bit masks and bit positions */ -#define DAC_CH0OFFSETCAL_gm 0x7F /* Offset Calibration group mask. */ -#define DAC_CH0OFFSETCAL_gp 0 /* Offset Calibration group position. */ -#define DAC_CH0OFFSETCAL0_bm (1<<0) /* Offset Calibration bit 0 mask. */ -#define DAC_CH0OFFSETCAL0_bp 0 /* Offset Calibration bit 0 position. */ -#define DAC_CH0OFFSETCAL1_bm (1<<1) /* Offset Calibration bit 1 mask. */ -#define DAC_CH0OFFSETCAL1_bp 1 /* Offset Calibration bit 1 position. */ -#define DAC_CH0OFFSETCAL2_bm (1<<2) /* Offset Calibration bit 2 mask. */ -#define DAC_CH0OFFSETCAL2_bp 2 /* Offset Calibration bit 2 position. */ -#define DAC_CH0OFFSETCAL3_bm (1<<3) /* Offset Calibration bit 3 mask. */ -#define DAC_CH0OFFSETCAL3_bp 3 /* Offset Calibration bit 3 position. */ -#define DAC_CH0OFFSETCAL4_bm (1<<4) /* Offset Calibration bit 4 mask. */ -#define DAC_CH0OFFSETCAL4_bp 4 /* Offset Calibration bit 4 position. */ -#define DAC_CH0OFFSETCAL5_bm (1<<5) /* Offset Calibration bit 5 mask. */ -#define DAC_CH0OFFSETCAL5_bp 5 /* Offset Calibration bit 5 position. */ -#define DAC_CH0OFFSETCAL6_bm (1<<6) /* Offset Calibration bit 6 mask. */ -#define DAC_CH0OFFSETCAL6_bp 6 /* Offset Calibration bit 6 position. */ - -/* DAC.CH1GAINCAL bit masks and bit positions */ -#define DAC_CH1GAINCAL_gm 0x7F /* Gain Calibration group mask. */ -#define DAC_CH1GAINCAL_gp 0 /* Gain Calibration group position. */ -#define DAC_CH1GAINCAL0_bm (1<<0) /* Gain Calibration bit 0 mask. */ -#define DAC_CH1GAINCAL0_bp 0 /* Gain Calibration bit 0 position. */ -#define DAC_CH1GAINCAL1_bm (1<<1) /* Gain Calibration bit 1 mask. */ -#define DAC_CH1GAINCAL1_bp 1 /* Gain Calibration bit 1 position. */ -#define DAC_CH1GAINCAL2_bm (1<<2) /* Gain Calibration bit 2 mask. */ -#define DAC_CH1GAINCAL2_bp 2 /* Gain Calibration bit 2 position. */ -#define DAC_CH1GAINCAL3_bm (1<<3) /* Gain Calibration bit 3 mask. */ -#define DAC_CH1GAINCAL3_bp 3 /* Gain Calibration bit 3 position. */ -#define DAC_CH1GAINCAL4_bm (1<<4) /* Gain Calibration bit 4 mask. */ -#define DAC_CH1GAINCAL4_bp 4 /* Gain Calibration bit 4 position. */ -#define DAC_CH1GAINCAL5_bm (1<<5) /* Gain Calibration bit 5 mask. */ -#define DAC_CH1GAINCAL5_bp 5 /* Gain Calibration bit 5 position. */ -#define DAC_CH1GAINCAL6_bm (1<<6) /* Gain Calibration bit 6 mask. */ -#define DAC_CH1GAINCAL6_bp 6 /* Gain Calibration bit 6 position. */ - -/* DAC.CH1OFFSETCAL bit masks and bit positions */ -#define DAC_CH1OFFSETCAL_gm 0x7F /* Offset Calibration group mask. */ -#define DAC_CH1OFFSETCAL_gp 0 /* Offset Calibration group position. */ -#define DAC_CH1OFFSETCAL0_bm (1<<0) /* Offset Calibration bit 0 mask. */ -#define DAC_CH1OFFSETCAL0_bp 0 /* Offset Calibration bit 0 position. */ -#define DAC_CH1OFFSETCAL1_bm (1<<1) /* Offset Calibration bit 1 mask. */ -#define DAC_CH1OFFSETCAL1_bp 1 /* Offset Calibration bit 1 position. */ -#define DAC_CH1OFFSETCAL2_bm (1<<2) /* Offset Calibration bit 2 mask. */ -#define DAC_CH1OFFSETCAL2_bp 2 /* Offset Calibration bit 2 position. */ -#define DAC_CH1OFFSETCAL3_bm (1<<3) /* Offset Calibration bit 3 mask. */ -#define DAC_CH1OFFSETCAL3_bp 3 /* Offset Calibration bit 3 position. */ -#define DAC_CH1OFFSETCAL4_bm (1<<4) /* Offset Calibration bit 4 mask. */ -#define DAC_CH1OFFSETCAL4_bp 4 /* Offset Calibration bit 4 position. */ -#define DAC_CH1OFFSETCAL5_bm (1<<5) /* Offset Calibration bit 5 mask. */ -#define DAC_CH1OFFSETCAL5_bp 5 /* Offset Calibration bit 5 position. */ -#define DAC_CH1OFFSETCAL6_bm (1<<6) /* Offset Calibration bit 6 mask. */ -#define DAC_CH1OFFSETCAL6_bp 6 /* Offset Calibration bit 6 position. */ - -/* AC - Analog Comparator */ -/* AC.AC0CTRL bit masks and bit positions */ -#define AC_INTMODE_gm 0xC0 /* Interrupt Mode group mask. */ -#define AC_INTMODE_gp 6 /* Interrupt Mode group position. */ -#define AC_INTMODE0_bm (1<<6) /* Interrupt Mode bit 0 mask. */ -#define AC_INTMODE0_bp 6 /* Interrupt Mode bit 0 position. */ -#define AC_INTMODE1_bm (1<<7) /* Interrupt Mode bit 1 mask. */ -#define AC_INTMODE1_bp 7 /* Interrupt Mode bit 1 position. */ - -#define AC_INTLVL_gm 0x30 /* Interrupt Level group mask. */ -#define AC_INTLVL_gp 4 /* Interrupt Level group position. */ -#define AC_INTLVL0_bm (1<<4) /* Interrupt Level bit 0 mask. */ -#define AC_INTLVL0_bp 4 /* Interrupt Level bit 0 position. */ -#define AC_INTLVL1_bm (1<<5) /* Interrupt Level bit 1 mask. */ -#define AC_INTLVL1_bp 5 /* Interrupt Level bit 1 position. */ - -#define AC_HSMODE_bm 0x08 /* High-speed Mode bit mask. */ -#define AC_HSMODE_bp 3 /* High-speed Mode bit position. */ - -#define AC_HYSMODE_gm 0x06 /* Hysteresis Mode group mask. */ -#define AC_HYSMODE_gp 1 /* Hysteresis Mode group position. */ -#define AC_HYSMODE0_bm (1<<1) /* Hysteresis Mode bit 0 mask. */ -#define AC_HYSMODE0_bp 1 /* Hysteresis Mode bit 0 position. */ -#define AC_HYSMODE1_bm (1<<2) /* Hysteresis Mode bit 1 mask. */ -#define AC_HYSMODE1_bp 2 /* Hysteresis Mode bit 1 position. */ - -#define AC_ENABLE_bm 0x01 /* Enable bit mask. */ -#define AC_ENABLE_bp 0 /* Enable bit position. */ - -/* AC.AC1CTRL bit masks and bit positions */ -/* AC_INTMODE Predefined. */ -/* AC_INTMODE Predefined. */ - -/* AC_INTLVL Predefined. */ -/* AC_INTLVL Predefined. */ - -/* AC_HSMODE Predefined. */ -/* AC_HSMODE Predefined. */ - -/* AC_HYSMODE Predefined. */ -/* AC_HYSMODE Predefined. */ - -/* AC_ENABLE Predefined. */ -/* AC_ENABLE Predefined. */ - -/* AC.AC0MUXCTRL bit masks and bit positions */ -#define AC_MUXPOS_gm 0x38 /* MUX Positive Input group mask. */ -#define AC_MUXPOS_gp 3 /* MUX Positive Input group position. */ -#define AC_MUXPOS0_bm (1<<3) /* MUX Positive Input bit 0 mask. */ -#define AC_MUXPOS0_bp 3 /* MUX Positive Input bit 0 position. */ -#define AC_MUXPOS1_bm (1<<4) /* MUX Positive Input bit 1 mask. */ -#define AC_MUXPOS1_bp 4 /* MUX Positive Input bit 1 position. */ -#define AC_MUXPOS2_bm (1<<5) /* MUX Positive Input bit 2 mask. */ -#define AC_MUXPOS2_bp 5 /* MUX Positive Input bit 2 position. */ - -#define AC_MUXNEG_gm 0x07 /* MUX Negative Input group mask. */ -#define AC_MUXNEG_gp 0 /* MUX Negative Input group position. */ -#define AC_MUXNEG0_bm (1<<0) /* MUX Negative Input bit 0 mask. */ -#define AC_MUXNEG0_bp 0 /* MUX Negative Input bit 0 position. */ -#define AC_MUXNEG1_bm (1<<1) /* MUX Negative Input bit 1 mask. */ -#define AC_MUXNEG1_bp 1 /* MUX Negative Input bit 1 position. */ -#define AC_MUXNEG2_bm (1<<2) /* MUX Negative Input bit 2 mask. */ -#define AC_MUXNEG2_bp 2 /* MUX Negative Input bit 2 position. */ - -/* AC.AC1MUXCTRL bit masks and bit positions */ -/* AC_MUXPOS Predefined. */ -/* AC_MUXPOS Predefined. */ - -/* AC_MUXNEG Predefined. */ -/* AC_MUXNEG Predefined. */ - -/* AC.CTRLA bit masks and bit positions */ -#define AC_AC1OUT_bm 0x02 /* Analog Comparator 1 Output Enable bit mask. */ -#define AC_AC1OUT_bp 1 /* Analog Comparator 1 Output Enable bit position. */ - -#define AC_AC0OUT_bm 0x01 /* Analog Comparator 0 Output Enable bit mask. */ -#define AC_AC0OUT_bp 0 /* Analog Comparator 0 Output Enable bit position. */ - -/* AC.CTRLB bit masks and bit positions */ -#define AC_SCALEFAC_gm 0x3F /* VCC Voltage Scaler Factor group mask. */ -#define AC_SCALEFAC_gp 0 /* VCC Voltage Scaler Factor group position. */ -#define AC_SCALEFAC0_bm (1<<0) /* VCC Voltage Scaler Factor bit 0 mask. */ -#define AC_SCALEFAC0_bp 0 /* VCC Voltage Scaler Factor bit 0 position. */ -#define AC_SCALEFAC1_bm (1<<1) /* VCC Voltage Scaler Factor bit 1 mask. */ -#define AC_SCALEFAC1_bp 1 /* VCC Voltage Scaler Factor bit 1 position. */ -#define AC_SCALEFAC2_bm (1<<2) /* VCC Voltage Scaler Factor bit 2 mask. */ -#define AC_SCALEFAC2_bp 2 /* VCC Voltage Scaler Factor bit 2 position. */ -#define AC_SCALEFAC3_bm (1<<3) /* VCC Voltage Scaler Factor bit 3 mask. */ -#define AC_SCALEFAC3_bp 3 /* VCC Voltage Scaler Factor bit 3 position. */ -#define AC_SCALEFAC4_bm (1<<4) /* VCC Voltage Scaler Factor bit 4 mask. */ -#define AC_SCALEFAC4_bp 4 /* VCC Voltage Scaler Factor bit 4 position. */ -#define AC_SCALEFAC5_bm (1<<5) /* VCC Voltage Scaler Factor bit 5 mask. */ -#define AC_SCALEFAC5_bp 5 /* VCC Voltage Scaler Factor bit 5 position. */ - -/* AC.WINCTRL bit masks and bit positions */ -#define AC_WEN_bm 0x10 /* Window Mode Enable bit mask. */ -#define AC_WEN_bp 4 /* Window Mode Enable bit position. */ - -#define AC_WINTMODE_gm 0x0C /* Window Interrupt Mode group mask. */ -#define AC_WINTMODE_gp 2 /* Window Interrupt Mode group position. */ -#define AC_WINTMODE0_bm (1<<2) /* Window Interrupt Mode bit 0 mask. */ -#define AC_WINTMODE0_bp 2 /* Window Interrupt Mode bit 0 position. */ -#define AC_WINTMODE1_bm (1<<3) /* Window Interrupt Mode bit 1 mask. */ -#define AC_WINTMODE1_bp 3 /* Window Interrupt Mode bit 1 position. */ - -#define AC_WINTLVL_gm 0x03 /* Window Interrupt Level group mask. */ -#define AC_WINTLVL_gp 0 /* Window Interrupt Level group position. */ -#define AC_WINTLVL0_bm (1<<0) /* Window Interrupt Level bit 0 mask. */ -#define AC_WINTLVL0_bp 0 /* Window Interrupt Level bit 0 position. */ -#define AC_WINTLVL1_bm (1<<1) /* Window Interrupt Level bit 1 mask. */ -#define AC_WINTLVL1_bp 1 /* Window Interrupt Level bit 1 position. */ - -/* AC.STATUS bit masks and bit positions */ -#define AC_WSTATE_gm 0xC0 /* Window Mode State group mask. */ -#define AC_WSTATE_gp 6 /* Window Mode State group position. */ -#define AC_WSTATE0_bm (1<<6) /* Window Mode State bit 0 mask. */ -#define AC_WSTATE0_bp 6 /* Window Mode State bit 0 position. */ -#define AC_WSTATE1_bm (1<<7) /* Window Mode State bit 1 mask. */ -#define AC_WSTATE1_bp 7 /* Window Mode State bit 1 position. */ - -#define AC_AC1STATE_bm 0x20 /* Analog Comparator 1 State bit mask. */ -#define AC_AC1STATE_bp 5 /* Analog Comparator 1 State bit position. */ - -#define AC_AC0STATE_bm 0x10 /* Analog Comparator 0 State bit mask. */ -#define AC_AC0STATE_bp 4 /* Analog Comparator 0 State bit position. */ - -#define AC_WIF_bm 0x04 /* Window Mode Interrupt Flag bit mask. */ -#define AC_WIF_bp 2 /* Window Mode Interrupt Flag bit position. */ - -#define AC_AC1IF_bm 0x02 /* Analog Comparator 1 Interrupt Flag bit mask. */ -#define AC_AC1IF_bp 1 /* Analog Comparator 1 Interrupt Flag bit position. */ - -#define AC_AC0IF_bm 0x01 /* Analog Comparator 0 Interrupt Flag bit mask. */ -#define AC_AC0IF_bp 0 /* Analog Comparator 0 Interrupt Flag bit position. */ - -/* RTC - Real-Time Counter */ -/* RTC.CTRL bit masks and bit positions */ -#define RTC_PRESCALER_gm 0x07 /* Prescaling Factor group mask. */ -#define RTC_PRESCALER_gp 0 /* Prescaling Factor group position. */ -#define RTC_PRESCALER0_bm (1<<0) /* Prescaling Factor bit 0 mask. */ -#define RTC_PRESCALER0_bp 0 /* Prescaling Factor bit 0 position. */ -#define RTC_PRESCALER1_bm (1<<1) /* Prescaling Factor bit 1 mask. */ -#define RTC_PRESCALER1_bp 1 /* Prescaling Factor bit 1 position. */ -#define RTC_PRESCALER2_bm (1<<2) /* Prescaling Factor bit 2 mask. */ -#define RTC_PRESCALER2_bp 2 /* Prescaling Factor bit 2 position. */ - -/* RTC.STATUS bit masks and bit positions */ -#define RTC_SYNCBUSY_bm 0x01 /* Synchronization Busy Flag bit mask. */ -#define RTC_SYNCBUSY_bp 0 /* Synchronization Busy Flag bit position. */ - -/* RTC.INTCTRL bit masks and bit positions */ -#define RTC_COMPINTLVL_gm 0x0C /* Compare Match Interrupt Level group mask. */ -#define RTC_COMPINTLVL_gp 2 /* Compare Match Interrupt Level group position. */ -#define RTC_COMPINTLVL0_bm (1<<2) /* Compare Match Interrupt Level bit 0 mask. */ -#define RTC_COMPINTLVL0_bp 2 /* Compare Match Interrupt Level bit 0 position. */ -#define RTC_COMPINTLVL1_bm (1<<3) /* Compare Match Interrupt Level bit 1 mask. */ -#define RTC_COMPINTLVL1_bp 3 /* Compare Match Interrupt Level bit 1 position. */ - -#define RTC_OVFINTLVL_gm 0x03 /* Overflow Interrupt Level group mask. */ -#define RTC_OVFINTLVL_gp 0 /* Overflow Interrupt Level group position. */ -#define RTC_OVFINTLVL0_bm (1<<0) /* Overflow Interrupt Level bit 0 mask. */ -#define RTC_OVFINTLVL0_bp 0 /* Overflow Interrupt Level bit 0 position. */ -#define RTC_OVFINTLVL1_bm (1<<1) /* Overflow Interrupt Level bit 1 mask. */ -#define RTC_OVFINTLVL1_bp 1 /* Overflow Interrupt Level bit 1 position. */ - -/* RTC.INTFLAGS bit masks and bit positions */ -#define RTC_COMPIF_bm 0x02 /* Compare Match Interrupt Flag bit mask. */ -#define RTC_COMPIF_bp 1 /* Compare Match Interrupt Flag bit position. */ - -#define RTC_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ -#define RTC_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ - -/* TWI - Two-Wire Interface */ -/* TWI_MASTER.CTRLA bit masks and bit positions */ -#define TWI_MASTER_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ -#define TWI_MASTER_INTLVL_gp 6 /* Interrupt Level group position. */ -#define TWI_MASTER_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ -#define TWI_MASTER_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ -#define TWI_MASTER_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ -#define TWI_MASTER_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ - -#define TWI_MASTER_RIEN_bm 0x20 /* Read Interrupt Enable bit mask. */ -#define TWI_MASTER_RIEN_bp 5 /* Read Interrupt Enable bit position. */ - -#define TWI_MASTER_WIEN_bm 0x10 /* Write Interrupt Enable bit mask. */ -#define TWI_MASTER_WIEN_bp 4 /* Write Interrupt Enable bit position. */ - -#define TWI_MASTER_ENABLE_bm 0x08 /* Enable TWI Master bit mask. */ -#define TWI_MASTER_ENABLE_bp 3 /* Enable TWI Master bit position. */ - -/* TWI_MASTER.CTRLB bit masks and bit positions */ -#define TWI_MASTER_TIMEOUT_gm 0x0C /* Inactive Bus Timeout group mask. */ -#define TWI_MASTER_TIMEOUT_gp 2 /* Inactive Bus Timeout group position. */ -#define TWI_MASTER_TIMEOUT0_bm (1<<2) /* Inactive Bus Timeout bit 0 mask. */ -#define TWI_MASTER_TIMEOUT0_bp 2 /* Inactive Bus Timeout bit 0 position. */ -#define TWI_MASTER_TIMEOUT1_bm (1<<3) /* Inactive Bus Timeout bit 1 mask. */ -#define TWI_MASTER_TIMEOUT1_bp 3 /* Inactive Bus Timeout bit 1 position. */ - -#define TWI_MASTER_QCEN_bm 0x02 /* Quick Command Enable bit mask. */ -#define TWI_MASTER_QCEN_bp 1 /* Quick Command Enable bit position. */ - -#define TWI_MASTER_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ -#define TWI_MASTER_SMEN_bp 0 /* Smart Mode Enable bit position. */ - -/* TWI_MASTER.CTRLC bit masks and bit positions */ -#define TWI_MASTER_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ -#define TWI_MASTER_ACKACT_bp 2 /* Acknowledge Action bit position. */ - -#define TWI_MASTER_CMD_gm 0x03 /* Command group mask. */ -#define TWI_MASTER_CMD_gp 0 /* Command group position. */ -#define TWI_MASTER_CMD0_bm (1<<0) /* Command bit 0 mask. */ -#define TWI_MASTER_CMD0_bp 0 /* Command bit 0 position. */ -#define TWI_MASTER_CMD1_bm (1<<1) /* Command bit 1 mask. */ -#define TWI_MASTER_CMD1_bp 1 /* Command bit 1 position. */ - -/* TWI_MASTER.STATUS bit masks and bit positions */ -#define TWI_MASTER_RIF_bm 0x80 /* Read Interrupt Flag bit mask. */ -#define TWI_MASTER_RIF_bp 7 /* Read Interrupt Flag bit position. */ - -#define TWI_MASTER_WIF_bm 0x40 /* Write Interrupt Flag bit mask. */ -#define TWI_MASTER_WIF_bp 6 /* Write Interrupt Flag bit position. */ - -#define TWI_MASTER_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ -#define TWI_MASTER_CLKHOLD_bp 5 /* Clock Hold bit position. */ - -#define TWI_MASTER_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ -#define TWI_MASTER_RXACK_bp 4 /* Received Acknowledge bit position. */ - -#define TWI_MASTER_ARBLOST_bm 0x08 /* Arbitration Lost bit mask. */ -#define TWI_MASTER_ARBLOST_bp 3 /* Arbitration Lost bit position. */ - -#define TWI_MASTER_BUSERR_bm 0x04 /* Bus Error bit mask. */ -#define TWI_MASTER_BUSERR_bp 2 /* Bus Error bit position. */ - -#define TWI_MASTER_BUSSTATE_gm 0x03 /* Bus State group mask. */ -#define TWI_MASTER_BUSSTATE_gp 0 /* Bus State group position. */ -#define TWI_MASTER_BUSSTATE0_bm (1<<0) /* Bus State bit 0 mask. */ -#define TWI_MASTER_BUSSTATE0_bp 0 /* Bus State bit 0 position. */ -#define TWI_MASTER_BUSSTATE1_bm (1<<1) /* Bus State bit 1 mask. */ -#define TWI_MASTER_BUSSTATE1_bp 1 /* Bus State bit 1 position. */ - -/* TWI_SLAVE.CTRLA bit masks and bit positions */ -#define TWI_SLAVE_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ -#define TWI_SLAVE_INTLVL_gp 6 /* Interrupt Level group position. */ -#define TWI_SLAVE_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ -#define TWI_SLAVE_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ -#define TWI_SLAVE_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ -#define TWI_SLAVE_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ - -#define TWI_SLAVE_DIEN_bm 0x20 /* Data Interrupt Enable bit mask. */ -#define TWI_SLAVE_DIEN_bp 5 /* Data Interrupt Enable bit position. */ - -#define TWI_SLAVE_APIEN_bm 0x10 /* Address/Stop Interrupt Enable bit mask. */ -#define TWI_SLAVE_APIEN_bp 4 /* Address/Stop Interrupt Enable bit position. */ - -#define TWI_SLAVE_ENABLE_bm 0x08 /* Enable TWI Slave bit mask. */ -#define TWI_SLAVE_ENABLE_bp 3 /* Enable TWI Slave bit position. */ - -#define TWI_SLAVE_PIEN_bm 0x04 /* Stop Interrupt Enable bit mask. */ -#define TWI_SLAVE_PIEN_bp 2 /* Stop Interrupt Enable bit position. */ - -#define TWI_SLAVE_PMEN_bm 0x02 /* Promiscuous Mode Enable bit mask. */ -#define TWI_SLAVE_PMEN_bp 1 /* Promiscuous Mode Enable bit position. */ - -#define TWI_SLAVE_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ -#define TWI_SLAVE_SMEN_bp 0 /* Smart Mode Enable bit position. */ - -/* TWI_SLAVE.CTRLB bit masks and bit positions */ -#define TWI_SLAVE_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ -#define TWI_SLAVE_ACKACT_bp 2 /* Acknowledge Action bit position. */ - -#define TWI_SLAVE_CMD_gm 0x03 /* Command group mask. */ -#define TWI_SLAVE_CMD_gp 0 /* Command group position. */ -#define TWI_SLAVE_CMD0_bm (1<<0) /* Command bit 0 mask. */ -#define TWI_SLAVE_CMD0_bp 0 /* Command bit 0 position. */ -#define TWI_SLAVE_CMD1_bm (1<<1) /* Command bit 1 mask. */ -#define TWI_SLAVE_CMD1_bp 1 /* Command bit 1 position. */ - -/* TWI_SLAVE.STATUS bit masks and bit positions */ -#define TWI_SLAVE_DIF_bm 0x80 /* Data Interrupt Flag bit mask. */ -#define TWI_SLAVE_DIF_bp 7 /* Data Interrupt Flag bit position. */ - -#define TWI_SLAVE_APIF_bm 0x40 /* Address/Stop Interrupt Flag bit mask. */ -#define TWI_SLAVE_APIF_bp 6 /* Address/Stop Interrupt Flag bit position. */ - -#define TWI_SLAVE_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ -#define TWI_SLAVE_CLKHOLD_bp 5 /* Clock Hold bit position. */ - -#define TWI_SLAVE_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ -#define TWI_SLAVE_RXACK_bp 4 /* Received Acknowledge bit position. */ - -#define TWI_SLAVE_COLL_bm 0x08 /* Collision bit mask. */ -#define TWI_SLAVE_COLL_bp 3 /* Collision bit position. */ - -#define TWI_SLAVE_BUSERR_bm 0x04 /* Bus Error bit mask. */ -#define TWI_SLAVE_BUSERR_bp 2 /* Bus Error bit position. */ - -#define TWI_SLAVE_DIR_bm 0x02 /* Read/Write Direction bit mask. */ -#define TWI_SLAVE_DIR_bp 1 /* Read/Write Direction bit position. */ - -#define TWI_SLAVE_AP_bm 0x01 /* Slave Address or Stop bit mask. */ -#define TWI_SLAVE_AP_bp 0 /* Slave Address or Stop bit position. */ - -/* TWI_SLAVE.ADDRMASK bit masks and bit positions */ -#define TWI_SLAVE_ADDRMASK_gm 0xFE /* Address Mask group mask. */ -#define TWI_SLAVE_ADDRMASK_gp 1 /* Address Mask group position. */ -#define TWI_SLAVE_ADDRMASK0_bm (1<<1) /* Address Mask bit 0 mask. */ -#define TWI_SLAVE_ADDRMASK0_bp 1 /* Address Mask bit 0 position. */ -#define TWI_SLAVE_ADDRMASK1_bm (1<<2) /* Address Mask bit 1 mask. */ -#define TWI_SLAVE_ADDRMASK1_bp 2 /* Address Mask bit 1 position. */ -#define TWI_SLAVE_ADDRMASK2_bm (1<<3) /* Address Mask bit 2 mask. */ -#define TWI_SLAVE_ADDRMASK2_bp 3 /* Address Mask bit 2 position. */ -#define TWI_SLAVE_ADDRMASK3_bm (1<<4) /* Address Mask bit 3 mask. */ -#define TWI_SLAVE_ADDRMASK3_bp 4 /* Address Mask bit 3 position. */ -#define TWI_SLAVE_ADDRMASK4_bm (1<<5) /* Address Mask bit 4 mask. */ -#define TWI_SLAVE_ADDRMASK4_bp 5 /* Address Mask bit 4 position. */ -#define TWI_SLAVE_ADDRMASK5_bm (1<<6) /* Address Mask bit 5 mask. */ -#define TWI_SLAVE_ADDRMASK5_bp 6 /* Address Mask bit 5 position. */ -#define TWI_SLAVE_ADDRMASK6_bm (1<<7) /* Address Mask bit 6 mask. */ -#define TWI_SLAVE_ADDRMASK6_bp 7 /* Address Mask bit 6 position. */ - -#define TWI_SLAVE_ADDREN_bm 0x01 /* Address Enable bit mask. */ -#define TWI_SLAVE_ADDREN_bp 0 /* Address Enable bit position. */ - -/* TWI.CTRL bit masks and bit positions */ -#define TWI_SDAHOLD_gm 0x06 /* SDA Hold Time Enable group mask. */ -#define TWI_SDAHOLD_gp 1 /* SDA Hold Time Enable group position. */ -#define TWI_SDAHOLD0_bm (1<<1) /* SDA Hold Time Enable bit 0 mask. */ -#define TWI_SDAHOLD0_bp 1 /* SDA Hold Time Enable bit 0 position. */ -#define TWI_SDAHOLD1_bm (1<<2) /* SDA Hold Time Enable bit 1 mask. */ -#define TWI_SDAHOLD1_bp 2 /* SDA Hold Time Enable bit 1 position. */ - -#define TWI_EDIEN_bm 0x01 /* External Driver Interface Enable bit mask. */ -#define TWI_EDIEN_bp 0 /* External Driver Interface Enable bit position. */ - -/* USB - USB */ -/* USB_EP.STATUS bit masks and bit positions */ -#define USB_EP_STALLF_bm 0x80 /* Endpoint Stall Flag bit mask. */ -#define USB_EP_STALLF_bp 7 /* Endpoint Stall Flag bit position. */ - -#define USB_EP_CRC_bm 0x80 /* CRC Error Flag bit mask. */ -#define USB_EP_CRC_bp 7 /* CRC Error Flag bit position. */ - -#define USB_EP_UNF_bm 0x40 /* Underflow Enpoint FLag bit mask. */ -#define USB_EP_UNF_bp 6 /* Underflow Enpoint FLag bit position. */ - -#define USB_EP_OVF_bm 0x40 /* Overflow Enpoint Flag for Output Endpoints bit mask. */ -#define USB_EP_OVF_bp 6 /* Overflow Enpoint Flag for Output Endpoints bit position. */ - -#define USB_EP_TRNCOMPL0_bm 0x20 /* Transaction Complete 0 Flag bit mask. */ -#define USB_EP_TRNCOMPL0_bp 5 /* Transaction Complete 0 Flag bit position. */ - -#define USB_EP_TRNCOMPL1_bm 0x10 /* Transaction Complete 1 Flag bit mask. */ -#define USB_EP_TRNCOMPL1_bp 4 /* Transaction Complete 1 Flag bit position. */ - -#define USB_EP_SETUP_bm 0x10 /* SETUP Transaction Complete Flag bit mask. */ -#define USB_EP_SETUP_bp 4 /* SETUP Transaction Complete Flag bit position. */ - -#define USB_EP_BANK_bm 0x08 /* Bank Select bit mask. */ -#define USB_EP_BANK_bp 3 /* Bank Select bit position. */ - -#define USB_EP_BUSNACK1_bm 0x04 /* Data Buffer 1 Not Acknowledge bit mask. */ -#define USB_EP_BUSNACK1_bp 2 /* Data Buffer 1 Not Acknowledge bit position. */ - -#define USB_EP_BUSNACK0_bm 0x02 /* Data Buffer 0 Not Acknowledge bit mask. */ -#define USB_EP_BUSNACK0_bp 1 /* Data Buffer 0 Not Acknowledge bit position. */ - -#define USB_EP_TOGGLE_bm 0x01 /* Data Toggle bit mask. */ -#define USB_EP_TOGGLE_bp 0 /* Data Toggle bit position. */ - -/* USB_EP.CTRL bit masks and bit positions */ -#define USB_EP_TYPE_gm 0xC0 /* Endpoint Type group mask. */ -#define USB_EP_TYPE_gp 6 /* Endpoint Type group position. */ -#define USB_EP_TYPE0_bm (1<<6) /* Endpoint Type bit 0 mask. */ -#define USB_EP_TYPE0_bp 6 /* Endpoint Type bit 0 position. */ -#define USB_EP_TYPE1_bm (1<<7) /* Endpoint Type bit 1 mask. */ -#define USB_EP_TYPE1_bp 7 /* Endpoint Type bit 1 position. */ - -#define USB_EP_MULTIPKT_bm 0x20 /* Multi Packet Transfer Enable bit mask. */ -#define USB_EP_MULTIPKT_bp 5 /* Multi Packet Transfer Enable bit position. */ - -#define USB_EP_PINGPONG_bm 0x10 /* Ping-Pong Enable bit mask. */ -#define USB_EP_PINGPONG_bp 4 /* Ping-Pong Enable bit position. */ - -#define USB_EP_INTDSBL_bm 0x08 /* Interrupt Disable bit mask. */ -#define USB_EP_INTDSBL_bp 3 /* Interrupt Disable bit position. */ - -#define USB_EP_STALL_bm 0x04 /* Data Stall bit mask. */ -#define USB_EP_STALL_bp 2 /* Data Stall bit position. */ - -#define USB_EP_BUFSIZE_gm 0x07 /* Data Buffer Size group mask. */ -#define USB_EP_BUFSIZE_gp 0 /* Data Buffer Size group position. */ -#define USB_EP_BUFSIZE0_bm (1<<0) /* Data Buffer Size bit 0 mask. */ -#define USB_EP_BUFSIZE0_bp 0 /* Data Buffer Size bit 0 position. */ -#define USB_EP_BUFSIZE1_bm (1<<1) /* Data Buffer Size bit 1 mask. */ -#define USB_EP_BUFSIZE1_bp 1 /* Data Buffer Size bit 1 position. */ -#define USB_EP_BUFSIZE2_bm (1<<2) /* Data Buffer Size bit 2 mask. */ -#define USB_EP_BUFSIZE2_bp 2 /* Data Buffer Size bit 2 position. */ - -/* USB_EP.CNT bit masks and bit positions */ -#define USB_EP_ZLP_bm 0x8000 /* Zero Length Packet bit mask. */ -#define USB_EP_ZLP_bp 15 /* Zero Length Packet bit position. */ - -/* USB.CTRLA bit masks and bit positions */ -#define USB_ENABLE_bm 0x80 /* USB Enable bit mask. */ -#define USB_ENABLE_bp 7 /* USB Enable bit position. */ - -#define USB_SPEED_bm 0x40 /* Speed Select bit mask. */ -#define USB_SPEED_bp 6 /* Speed Select bit position. */ - -#define USB_FIFOEN_bm 0x20 /* USB FIFO Enable bit mask. */ -#define USB_FIFOEN_bp 5 /* USB FIFO Enable bit position. */ - -#define USB_STFRNUM_bm 0x10 /* Store Frame Number Enable bit mask. */ -#define USB_STFRNUM_bp 4 /* Store Frame Number Enable bit position. */ - -#define USB_MAXEP_gm 0x0F /* Maximum Endpoint Addresses group mask. */ -#define USB_MAXEP_gp 0 /* Maximum Endpoint Addresses group position. */ -#define USB_MAXEP0_bm (1<<0) /* Maximum Endpoint Addresses bit 0 mask. */ -#define USB_MAXEP0_bp 0 /* Maximum Endpoint Addresses bit 0 position. */ -#define USB_MAXEP1_bm (1<<1) /* Maximum Endpoint Addresses bit 1 mask. */ -#define USB_MAXEP1_bp 1 /* Maximum Endpoint Addresses bit 1 position. */ -#define USB_MAXEP2_bm (1<<2) /* Maximum Endpoint Addresses bit 2 mask. */ -#define USB_MAXEP2_bp 2 /* Maximum Endpoint Addresses bit 2 position. */ -#define USB_MAXEP3_bm (1<<3) /* Maximum Endpoint Addresses bit 3 mask. */ -#define USB_MAXEP3_bp 3 /* Maximum Endpoint Addresses bit 3 position. */ - -/* USB.CTRLB bit masks and bit positions */ -#define USB_PULLRST_bm 0x10 /* Pull during Reset bit mask. */ -#define USB_PULLRST_bp 4 /* Pull during Reset bit position. */ - -#define USB_RWAKEUP_bm 0x04 /* Remote Wake-up bit mask. */ -#define USB_RWAKEUP_bp 2 /* Remote Wake-up bit position. */ - -#define USB_GNACK_bm 0x02 /* Global NACK bit mask. */ -#define USB_GNACK_bp 1 /* Global NACK bit position. */ - -#define USB_ATTACH_bm 0x01 /* Attach bit mask. */ -#define USB_ATTACH_bp 0 /* Attach bit position. */ - -/* USB.STATUS bit masks and bit positions */ -#define USB_URESUME_bm 0x08 /* Upstream Resume bit mask. */ -#define USB_URESUME_bp 3 /* Upstream Resume bit position. */ - -#define USB_RESUME_bm 0x04 /* Resume bit mask. */ -#define USB_RESUME_bp 2 /* Resume bit position. */ - -#define USB_SUSPEND_bm 0x02 /* Bus Suspended bit mask. */ -#define USB_SUSPEND_bp 1 /* Bus Suspended bit position. */ - -#define USB_BUSRST_bm 0x01 /* Bus Reset bit mask. */ -#define USB_BUSRST_bp 0 /* Bus Reset bit position. */ - -/* USB.ADDR bit masks and bit positions */ -#define USB_ADDR_gm 0x7F /* Device Address group mask. */ -#define USB_ADDR_gp 0 /* Device Address group position. */ -#define USB_ADDR0_bm (1<<0) /* Device Address bit 0 mask. */ -#define USB_ADDR0_bp 0 /* Device Address bit 0 position. */ -#define USB_ADDR1_bm (1<<1) /* Device Address bit 1 mask. */ -#define USB_ADDR1_bp 1 /* Device Address bit 1 position. */ -#define USB_ADDR2_bm (1<<2) /* Device Address bit 2 mask. */ -#define USB_ADDR2_bp 2 /* Device Address bit 2 position. */ -#define USB_ADDR3_bm (1<<3) /* Device Address bit 3 mask. */ -#define USB_ADDR3_bp 3 /* Device Address bit 3 position. */ -#define USB_ADDR4_bm (1<<4) /* Device Address bit 4 mask. */ -#define USB_ADDR4_bp 4 /* Device Address bit 4 position. */ -#define USB_ADDR5_bm (1<<5) /* Device Address bit 5 mask. */ -#define USB_ADDR5_bp 5 /* Device Address bit 5 position. */ -#define USB_ADDR6_bm (1<<6) /* Device Address bit 6 mask. */ -#define USB_ADDR6_bp 6 /* Device Address bit 6 position. */ - -/* USB.FIFOWP bit masks and bit positions */ -#define USB_FIFOWP_gm 0x1F /* FIFO Write Pointer group mask. */ -#define USB_FIFOWP_gp 0 /* FIFO Write Pointer group position. */ -#define USB_FIFOWP0_bm (1<<0) /* FIFO Write Pointer bit 0 mask. */ -#define USB_FIFOWP0_bp 0 /* FIFO Write Pointer bit 0 position. */ -#define USB_FIFOWP1_bm (1<<1) /* FIFO Write Pointer bit 1 mask. */ -#define USB_FIFOWP1_bp 1 /* FIFO Write Pointer bit 1 position. */ -#define USB_FIFOWP2_bm (1<<2) /* FIFO Write Pointer bit 2 mask. */ -#define USB_FIFOWP2_bp 2 /* FIFO Write Pointer bit 2 position. */ -#define USB_FIFOWP3_bm (1<<3) /* FIFO Write Pointer bit 3 mask. */ -#define USB_FIFOWP3_bp 3 /* FIFO Write Pointer bit 3 position. */ -#define USB_FIFOWP4_bm (1<<4) /* FIFO Write Pointer bit 4 mask. */ -#define USB_FIFOWP4_bp 4 /* FIFO Write Pointer bit 4 position. */ - -/* USB.FIFORP bit masks and bit positions */ -#define USB_FIFORP_gm 0x1F /* FIFO Read Pointer group mask. */ -#define USB_FIFORP_gp 0 /* FIFO Read Pointer group position. */ -#define USB_FIFORP0_bm (1<<0) /* FIFO Read Pointer bit 0 mask. */ -#define USB_FIFORP0_bp 0 /* FIFO Read Pointer bit 0 position. */ -#define USB_FIFORP1_bm (1<<1) /* FIFO Read Pointer bit 1 mask. */ -#define USB_FIFORP1_bp 1 /* FIFO Read Pointer bit 1 position. */ -#define USB_FIFORP2_bm (1<<2) /* FIFO Read Pointer bit 2 mask. */ -#define USB_FIFORP2_bp 2 /* FIFO Read Pointer bit 2 position. */ -#define USB_FIFORP3_bm (1<<3) /* FIFO Read Pointer bit 3 mask. */ -#define USB_FIFORP3_bp 3 /* FIFO Read Pointer bit 3 position. */ -#define USB_FIFORP4_bm (1<<4) /* FIFO Read Pointer bit 4 mask. */ -#define USB_FIFORP4_bp 4 /* FIFO Read Pointer bit 4 position. */ - -/* USB.INTCTRLA bit masks and bit positions */ -#define USB_SOFIE_bm 0x80 /* Start Of Frame Interrupt Enable bit mask. */ -#define USB_SOFIE_bp 7 /* Start Of Frame Interrupt Enable bit position. */ - -#define USB_BUSEVIE_bm 0x40 /* Bus Event Interrupt Enable bit mask. */ -#define USB_BUSEVIE_bp 6 /* Bus Event Interrupt Enable bit position. */ - -#define USB_BUSERRIE_bm 0x20 /* Bus Error Interrupt Enable bit mask. */ -#define USB_BUSERRIE_bp 5 /* Bus Error Interrupt Enable bit position. */ - -#define USB_STALLIE_bm 0x10 /* STALL Interrupt Enable bit mask. */ -#define USB_STALLIE_bp 4 /* STALL Interrupt Enable bit position. */ - -#define USB_INTLVL_gm 0x03 /* Interrupt Level group mask. */ -#define USB_INTLVL_gp 0 /* Interrupt Level group position. */ -#define USB_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */ -#define USB_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */ -#define USB_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ -#define USB_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */ - -/* USB.INTCTRLB bit masks and bit positions */ -#define USB_TRNIE_bm 0x02 /* Transaction Complete Interrupt Enable bit mask. */ -#define USB_TRNIE_bp 1 /* Transaction Complete Interrupt Enable bit position. */ - -#define USB_SETUPIE_bm 0x01 /* SETUP Transaction Complete Interrupt Enable bit mask. */ -#define USB_SETUPIE_bp 0 /* SETUP Transaction Complete Interrupt Enable bit position. */ - -/* USB.INTFLAGSACLR bit masks and bit positions */ -#define USB_SOFIF_bm 0x80 /* Start Of Frame Interrupt Flag bit mask. */ -#define USB_SOFIF_bp 7 /* Start Of Frame Interrupt Flag bit position. */ - -#define USB_SUSPENDIF_bm 0x40 /* Suspend Interrupt Flag bit mask. */ -#define USB_SUSPENDIF_bp 6 /* Suspend Interrupt Flag bit position. */ - -#define USB_RESUMEIF_bm 0x20 /* Resume Interrupt Flag bit mask. */ -#define USB_RESUMEIF_bp 5 /* Resume Interrupt Flag bit position. */ - -#define USB_RSTIF_bm 0x10 /* Reset Interrupt Flag bit mask. */ -#define USB_RSTIF_bp 4 /* Reset Interrupt Flag bit position. */ - -#define USB_CRCIF_bm 0x08 /* Isochronous CRC Error Interrupt Flag bit mask. */ -#define USB_CRCIF_bp 3 /* Isochronous CRC Error Interrupt Flag bit position. */ - -#define USB_UNFIF_bm 0x04 /* Underflow Interrupt Flag bit mask. */ -#define USB_UNFIF_bp 2 /* Underflow Interrupt Flag bit position. */ - -#define USB_OVFIF_bm 0x02 /* Overflow Interrupt Flag bit mask. */ -#define USB_OVFIF_bp 1 /* Overflow Interrupt Flag bit position. */ - -#define USB_STALLIF_bm 0x01 /* STALL Interrupt Flag bit mask. */ -#define USB_STALLIF_bp 0 /* STALL Interrupt Flag bit position. */ - -/* USB.INTFLAGSASET bit masks and bit positions */ -/* USB_SOFIF Predefined. */ -/* USB_SOFIF Predefined. */ - -/* USB_SUSPENDIF Predefined. */ -/* USB_SUSPENDIF Predefined. */ - -/* USB_RESUMEIF Predefined. */ -/* USB_RESUMEIF Predefined. */ - -/* USB_RSTIF Predefined. */ -/* USB_RSTIF Predefined. */ - -/* USB_CRCIF Predefined. */ -/* USB_CRCIF Predefined. */ - -/* USB_UNFIF Predefined. */ -/* USB_UNFIF Predefined. */ - -/* USB_OVFIF Predefined. */ -/* USB_OVFIF Predefined. */ - -/* USB_STALLIF Predefined. */ -/* USB_STALLIF Predefined. */ - -/* USB.INTFLAGSBCLR bit masks and bit positions */ -#define USB_TRNIF_bm 0x02 /* Transaction Complete Interrupt Flag bit mask. */ -#define USB_TRNIF_bp 1 /* Transaction Complete Interrupt Flag bit position. */ - -#define USB_SETUPIF_bm 0x01 /* SETUP Transaction Complete Interrupt Flag bit mask. */ -#define USB_SETUPIF_bp 0 /* SETUP Transaction Complete Interrupt Flag bit position. */ - -/* USB.INTFLAGSBSET bit masks and bit positions */ -/* USB_TRNIF Predefined. */ -/* USB_TRNIF Predefined. */ - -/* USB_SETUPIF Predefined. */ -/* USB_SETUPIF Predefined. */ - -/* PORT - I/O Port Configuration */ -/* PORT.INTCTRL bit masks and bit positions */ -#define PORT_INT1LVL_gm 0x0C /* Port Interrupt 1 Level group mask. */ -#define PORT_INT1LVL_gp 2 /* Port Interrupt 1 Level group position. */ -#define PORT_INT1LVL0_bm (1<<2) /* Port Interrupt 1 Level bit 0 mask. */ -#define PORT_INT1LVL0_bp 2 /* Port Interrupt 1 Level bit 0 position. */ -#define PORT_INT1LVL1_bm (1<<3) /* Port Interrupt 1 Level bit 1 mask. */ -#define PORT_INT1LVL1_bp 3 /* Port Interrupt 1 Level bit 1 position. */ - -#define PORT_INT0LVL_gm 0x03 /* Port Interrupt 0 Level group mask. */ -#define PORT_INT0LVL_gp 0 /* Port Interrupt 0 Level group position. */ -#define PORT_INT0LVL0_bm (1<<0) /* Port Interrupt 0 Level bit 0 mask. */ -#define PORT_INT0LVL0_bp 0 /* Port Interrupt 0 Level bit 0 position. */ -#define PORT_INT0LVL1_bm (1<<1) /* Port Interrupt 0 Level bit 1 mask. */ -#define PORT_INT0LVL1_bp 1 /* Port Interrupt 0 Level bit 1 position. */ - -/* PORT.INTFLAGS bit masks and bit positions */ -#define PORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ -#define PORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ - -#define PORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ -#define PORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ - -/* PORT.REMAP bit masks and bit positions */ -#define PORT_SPI_bm 0x20 /* SPI bit mask. */ -#define PORT_SPI_bp 5 /* SPI bit position. */ - -#define PORT_USART0_bm 0x10 /* USART0 bit mask. */ -#define PORT_USART0_bp 4 /* USART0 bit position. */ - -#define PORT_TC0D_bm 0x08 /* Timer/Counter 0 Output Compare D bit mask. */ -#define PORT_TC0D_bp 3 /* Timer/Counter 0 Output Compare D bit position. */ - -#define PORT_TC0C_bm 0x04 /* Timer/Counter 0 Output Compare C bit mask. */ -#define PORT_TC0C_bp 2 /* Timer/Counter 0 Output Compare C bit position. */ - -#define PORT_TC0B_bm 0x02 /* Timer/Counter 0 Output Compare B bit mask. */ -#define PORT_TC0B_bp 1 /* Timer/Counter 0 Output Compare B bit position. */ - -#define PORT_TC0A_bm 0x01 /* Timer/Counter 0 Output Compare A bit mask. */ -#define PORT_TC0A_bp 0 /* Timer/Counter 0 Output Compare A bit position. */ - -/* PORT.PIN0CTRL bit masks and bit positions */ -#define PORT_SRLEN_bm 0x80 /* Slew Rate Enable bit mask. */ -#define PORT_SRLEN_bp 7 /* Slew Rate Enable bit position. */ - -#define PORT_INVEN_bm 0x40 /* Inverted I/O Enable bit mask. */ -#define PORT_INVEN_bp 6 /* Inverted I/O Enable bit position. */ - -#define PORT_OPC_gm 0x38 /* Output/Pull Configuration group mask. */ -#define PORT_OPC_gp 3 /* Output/Pull Configuration group position. */ -#define PORT_OPC0_bm (1<<3) /* Output/Pull Configuration bit 0 mask. */ -#define PORT_OPC0_bp 3 /* Output/Pull Configuration bit 0 position. */ -#define PORT_OPC1_bm (1<<4) /* Output/Pull Configuration bit 1 mask. */ -#define PORT_OPC1_bp 4 /* Output/Pull Configuration bit 1 position. */ -#define PORT_OPC2_bm (1<<5) /* Output/Pull Configuration bit 2 mask. */ -#define PORT_OPC2_bp 5 /* Output/Pull Configuration bit 2 position. */ - -#define PORT_ISC_gm 0x07 /* Input/Sense Configuration group mask. */ -#define PORT_ISC_gp 0 /* Input/Sense Configuration group position. */ -#define PORT_ISC0_bm (1<<0) /* Input/Sense Configuration bit 0 mask. */ -#define PORT_ISC0_bp 0 /* Input/Sense Configuration bit 0 position. */ -#define PORT_ISC1_bm (1<<1) /* Input/Sense Configuration bit 1 mask. */ -#define PORT_ISC1_bp 1 /* Input/Sense Configuration bit 1 position. */ -#define PORT_ISC2_bm (1<<2) /* Input/Sense Configuration bit 2 mask. */ -#define PORT_ISC2_bp 2 /* Input/Sense Configuration bit 2 position. */ - -/* PORT.PIN1CTRL bit masks and bit positions */ -/* PORT_SRLEN Predefined. */ -/* PORT_SRLEN Predefined. */ - -/* PORT_INVEN Predefined. */ -/* PORT_INVEN Predefined. */ - -/* PORT_OPC Predefined. */ -/* PORT_OPC Predefined. */ - -/* PORT_ISC Predefined. */ -/* PORT_ISC Predefined. */ - -/* PORT.PIN2CTRL bit masks and bit positions */ -/* PORT_SRLEN Predefined. */ -/* PORT_SRLEN Predefined. */ - -/* PORT_INVEN Predefined. */ -/* PORT_INVEN Predefined. */ - -/* PORT_OPC Predefined. */ -/* PORT_OPC Predefined. */ - -/* PORT_ISC Predefined. */ -/* PORT_ISC Predefined. */ - -/* PORT.PIN3CTRL bit masks and bit positions */ -/* PORT_SRLEN Predefined. */ -/* PORT_SRLEN Predefined. */ - -/* PORT_INVEN Predefined. */ -/* PORT_INVEN Predefined. */ - -/* PORT_OPC Predefined. */ -/* PORT_OPC Predefined. */ - -/* PORT_ISC Predefined. */ -/* PORT_ISC Predefined. */ - -/* PORT.PIN4CTRL bit masks and bit positions */ -/* PORT_SRLEN Predefined. */ -/* PORT_SRLEN Predefined. */ - -/* PORT_INVEN Predefined. */ -/* PORT_INVEN Predefined. */ - -/* PORT_OPC Predefined. */ -/* PORT_OPC Predefined. */ - -/* PORT_ISC Predefined. */ -/* PORT_ISC Predefined. */ - -/* PORT.PIN5CTRL bit masks and bit positions */ -/* PORT_SRLEN Predefined. */ -/* PORT_SRLEN Predefined. */ - -/* PORT_INVEN Predefined. */ -/* PORT_INVEN Predefined. */ - -/* PORT_OPC Predefined. */ -/* PORT_OPC Predefined. */ - -/* PORT_ISC Predefined. */ -/* PORT_ISC Predefined. */ - -/* PORT.PIN6CTRL bit masks and bit positions */ -/* PORT_SRLEN Predefined. */ -/* PORT_SRLEN Predefined. */ - -/* PORT_INVEN Predefined. */ -/* PORT_INVEN Predefined. */ - -/* PORT_OPC Predefined. */ -/* PORT_OPC Predefined. */ - -/* PORT_ISC Predefined. */ -/* PORT_ISC Predefined. */ - -/* PORT.PIN7CTRL bit masks and bit positions */ -/* PORT_SRLEN Predefined. */ -/* PORT_SRLEN Predefined. */ - -/* PORT_INVEN Predefined. */ -/* PORT_INVEN Predefined. */ - -/* PORT_OPC Predefined. */ -/* PORT_OPC Predefined. */ - -/* PORT_ISC Predefined. */ -/* PORT_ISC Predefined. */ - -/* TC - 16-bit Timer/Counter With PWM */ -/* TC0.CTRLA bit masks and bit positions */ -#define TC0_CLKSEL_gm 0x0F /* Clock Selection group mask. */ -#define TC0_CLKSEL_gp 0 /* Clock Selection group position. */ -#define TC0_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ -#define TC0_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ -#define TC0_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ -#define TC0_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ -#define TC0_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ -#define TC0_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ -#define TC0_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ -#define TC0_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ - -/* TC0.CTRLB bit masks and bit positions */ -#define TC0_CCDEN_bm 0x80 /* Compare or Capture D Enable bit mask. */ -#define TC0_CCDEN_bp 7 /* Compare or Capture D Enable bit position. */ - -#define TC0_CCCEN_bm 0x40 /* Compare or Capture C Enable bit mask. */ -#define TC0_CCCEN_bp 6 /* Compare or Capture C Enable bit position. */ - -#define TC0_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ -#define TC0_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ - -#define TC0_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ -#define TC0_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ - -#define TC0_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ -#define TC0_WGMODE_gp 0 /* Waveform generation mode group position. */ -#define TC0_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ -#define TC0_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ -#define TC0_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ -#define TC0_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ -#define TC0_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ -#define TC0_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ - -/* TC0.CTRLC bit masks and bit positions */ -#define TC0_CMPD_bm 0x08 /* Compare D Output Value bit mask. */ -#define TC0_CMPD_bp 3 /* Compare D Output Value bit position. */ - -#define TC0_CMPC_bm 0x04 /* Compare C Output Value bit mask. */ -#define TC0_CMPC_bp 2 /* Compare C Output Value bit position. */ - -#define TC0_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ -#define TC0_CMPB_bp 1 /* Compare B Output Value bit position. */ - -#define TC0_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ -#define TC0_CMPA_bp 0 /* Compare A Output Value bit position. */ - -/* TC0.CTRLD bit masks and bit positions */ -#define TC0_EVACT_gm 0xE0 /* Event Action group mask. */ -#define TC0_EVACT_gp 5 /* Event Action group position. */ -#define TC0_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ -#define TC0_EVACT0_bp 5 /* Event Action bit 0 position. */ -#define TC0_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ -#define TC0_EVACT1_bp 6 /* Event Action bit 1 position. */ -#define TC0_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ -#define TC0_EVACT2_bp 7 /* Event Action bit 2 position. */ - -#define TC0_EVDLY_bm 0x10 /* Event Delay bit mask. */ -#define TC0_EVDLY_bp 4 /* Event Delay bit position. */ - -#define TC0_EVSEL_gm 0x0F /* Event Source Select group mask. */ -#define TC0_EVSEL_gp 0 /* Event Source Select group position. */ -#define TC0_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ -#define TC0_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ -#define TC0_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ -#define TC0_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ -#define TC0_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ -#define TC0_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ -#define TC0_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ -#define TC0_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ - -/* TC0.CTRLE bit masks and bit positions */ -#define TC0_BYTEM_gm 0x03 /* Byte Mode group mask. */ -#define TC0_BYTEM_gp 0 /* Byte Mode group position. */ -#define TC0_BYTEM0_bm (1<<0) /* Byte Mode bit 0 mask. */ -#define TC0_BYTEM0_bp 0 /* Byte Mode bit 0 position. */ -#define TC0_BYTEM1_bm (1<<1) /* Byte Mode bit 1 mask. */ -#define TC0_BYTEM1_bp 1 /* Byte Mode bit 1 position. */ - -/* TC0.INTCTRLA bit masks and bit positions */ -#define TC0_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ -#define TC0_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ -#define TC0_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ -#define TC0_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ -#define TC0_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ -#define TC0_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ - -#define TC0_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ -#define TC0_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ -#define TC0_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ -#define TC0_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ -#define TC0_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ -#define TC0_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ - -/* TC0.INTCTRLB bit masks and bit positions */ -#define TC0_CCDINTLVL_gm 0xC0 /* Compare or Capture D Interrupt Level group mask. */ -#define TC0_CCDINTLVL_gp 6 /* Compare or Capture D Interrupt Level group position. */ -#define TC0_CCDINTLVL0_bm (1<<6) /* Compare or Capture D Interrupt Level bit 0 mask. */ -#define TC0_CCDINTLVL0_bp 6 /* Compare or Capture D Interrupt Level bit 0 position. */ -#define TC0_CCDINTLVL1_bm (1<<7) /* Compare or Capture D Interrupt Level bit 1 mask. */ -#define TC0_CCDINTLVL1_bp 7 /* Compare or Capture D Interrupt Level bit 1 position. */ - -#define TC0_CCCINTLVL_gm 0x30 /* Compare or Capture C Interrupt Level group mask. */ -#define TC0_CCCINTLVL_gp 4 /* Compare or Capture C Interrupt Level group position. */ -#define TC0_CCCINTLVL0_bm (1<<4) /* Compare or Capture C Interrupt Level bit 0 mask. */ -#define TC0_CCCINTLVL0_bp 4 /* Compare or Capture C Interrupt Level bit 0 position. */ -#define TC0_CCCINTLVL1_bm (1<<5) /* Compare or Capture C Interrupt Level bit 1 mask. */ -#define TC0_CCCINTLVL1_bp 5 /* Compare or Capture C Interrupt Level bit 1 position. */ - -#define TC0_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ -#define TC0_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ -#define TC0_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ -#define TC0_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ -#define TC0_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ -#define TC0_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ - -#define TC0_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ -#define TC0_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ -#define TC0_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ -#define TC0_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ -#define TC0_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ -#define TC0_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ - -/* TC0.CTRLFCLR bit masks and bit positions */ -#define TC0_CMD_gm 0x0C /* Command group mask. */ -#define TC0_CMD_gp 2 /* Command group position. */ -#define TC0_CMD0_bm (1<<2) /* Command bit 0 mask. */ -#define TC0_CMD0_bp 2 /* Command bit 0 position. */ -#define TC0_CMD1_bm (1<<3) /* Command bit 1 mask. */ -#define TC0_CMD1_bp 3 /* Command bit 1 position. */ - -#define TC0_LUPD_bm 0x02 /* Lock Update bit mask. */ -#define TC0_LUPD_bp 1 /* Lock Update bit position. */ - -#define TC0_DIR_bm 0x01 /* Direction bit mask. */ -#define TC0_DIR_bp 0 /* Direction bit position. */ - -/* TC0.CTRLFSET bit masks and bit positions */ -/* TC0_CMD Predefined. */ -/* TC0_CMD Predefined. */ - -/* TC0_LUPD Predefined. */ -/* TC0_LUPD Predefined. */ - -/* TC0_DIR Predefined. */ -/* TC0_DIR Predefined. */ - -/* TC0.CTRLGCLR bit masks and bit positions */ -#define TC0_CCDBV_bm 0x10 /* Compare or Capture D Buffer Valid bit mask. */ -#define TC0_CCDBV_bp 4 /* Compare or Capture D Buffer Valid bit position. */ - -#define TC0_CCCBV_bm 0x08 /* Compare or Capture C Buffer Valid bit mask. */ -#define TC0_CCCBV_bp 3 /* Compare or Capture C Buffer Valid bit position. */ - -#define TC0_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ -#define TC0_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ - -#define TC0_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ -#define TC0_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ - -#define TC0_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ -#define TC0_PERBV_bp 0 /* Period Buffer Valid bit position. */ - -/* TC0.CTRLGSET bit masks and bit positions */ -/* TC0_CCDBV Predefined. */ -/* TC0_CCDBV Predefined. */ - -/* TC0_CCCBV Predefined. */ -/* TC0_CCCBV Predefined. */ - -/* TC0_CCBBV Predefined. */ -/* TC0_CCBBV Predefined. */ - -/* TC0_CCABV Predefined. */ -/* TC0_CCABV Predefined. */ - -/* TC0_PERBV Predefined. */ -/* TC0_PERBV Predefined. */ - -/* TC0.INTFLAGS bit masks and bit positions */ -#define TC0_CCDIF_bm 0x80 /* Compare or Capture D Interrupt Flag bit mask. */ -#define TC0_CCDIF_bp 7 /* Compare or Capture D Interrupt Flag bit position. */ - -#define TC0_CCCIF_bm 0x40 /* Compare or Capture C Interrupt Flag bit mask. */ -#define TC0_CCCIF_bp 6 /* Compare or Capture C Interrupt Flag bit position. */ - -#define TC0_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ -#define TC0_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ - -#define TC0_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ -#define TC0_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ - -#define TC0_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ -#define TC0_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ - -#define TC0_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ -#define TC0_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ - -/* TC1.CTRLA bit masks and bit positions */ -#define TC1_CLKSEL_gm 0x0F /* Clock Selection group mask. */ -#define TC1_CLKSEL_gp 0 /* Clock Selection group position. */ -#define TC1_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ -#define TC1_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ -#define TC1_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ -#define TC1_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ -#define TC1_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ -#define TC1_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ -#define TC1_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ -#define TC1_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ - -/* TC1.CTRLB bit masks and bit positions */ -#define TC1_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ -#define TC1_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ - -#define TC1_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ -#define TC1_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ - -#define TC1_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ -#define TC1_WGMODE_gp 0 /* Waveform generation mode group position. */ -#define TC1_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ -#define TC1_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ -#define TC1_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ -#define TC1_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ -#define TC1_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ -#define TC1_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ - -/* TC1.CTRLC bit masks and bit positions */ -#define TC1_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ -#define TC1_CMPB_bp 1 /* Compare B Output Value bit position. */ - -#define TC1_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ -#define TC1_CMPA_bp 0 /* Compare A Output Value bit position. */ - -/* TC1.CTRLD bit masks and bit positions */ -#define TC1_EVACT_gm 0xE0 /* Event Action group mask. */ -#define TC1_EVACT_gp 5 /* Event Action group position. */ -#define TC1_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ -#define TC1_EVACT0_bp 5 /* Event Action bit 0 position. */ -#define TC1_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ -#define TC1_EVACT1_bp 6 /* Event Action bit 1 position. */ -#define TC1_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ -#define TC1_EVACT2_bp 7 /* Event Action bit 2 position. */ - -#define TC1_EVDLY_bm 0x10 /* Event Delay bit mask. */ -#define TC1_EVDLY_bp 4 /* Event Delay bit position. */ - -#define TC1_EVSEL_gm 0x0F /* Event Source Select group mask. */ -#define TC1_EVSEL_gp 0 /* Event Source Select group position. */ -#define TC1_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ -#define TC1_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ -#define TC1_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ -#define TC1_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ -#define TC1_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ -#define TC1_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ -#define TC1_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ -#define TC1_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ - -/* TC1.CTRLE bit masks and bit positions */ -#define TC1_BYTEM_bm 0x01 /* Byte Mode bit mask. */ -#define TC1_BYTEM_bp 0 /* Byte Mode bit position. */ - -/* TC1.INTCTRLA bit masks and bit positions */ -#define TC1_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ -#define TC1_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ -#define TC1_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ -#define TC1_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ -#define TC1_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ -#define TC1_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ - -#define TC1_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ -#define TC1_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ -#define TC1_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ -#define TC1_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ -#define TC1_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ -#define TC1_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ - -/* TC1.INTCTRLB bit masks and bit positions */ -#define TC1_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ -#define TC1_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ -#define TC1_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ -#define TC1_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ -#define TC1_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ -#define TC1_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ - -#define TC1_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ -#define TC1_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ -#define TC1_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ -#define TC1_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ -#define TC1_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ -#define TC1_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ - -/* TC1.CTRLFCLR bit masks and bit positions */ -#define TC1_CMD_gm 0x0C /* Command group mask. */ -#define TC1_CMD_gp 2 /* Command group position. */ -#define TC1_CMD0_bm (1<<2) /* Command bit 0 mask. */ -#define TC1_CMD0_bp 2 /* Command bit 0 position. */ -#define TC1_CMD1_bm (1<<3) /* Command bit 1 mask. */ -#define TC1_CMD1_bp 3 /* Command bit 1 position. */ - -#define TC1_LUPD_bm 0x02 /* Lock Update bit mask. */ -#define TC1_LUPD_bp 1 /* Lock Update bit position. */ - -#define TC1_DIR_bm 0x01 /* Direction bit mask. */ -#define TC1_DIR_bp 0 /* Direction bit position. */ - -/* TC1.CTRLFSET bit masks and bit positions */ -/* TC1_CMD Predefined. */ -/* TC1_CMD Predefined. */ - -/* TC1_LUPD Predefined. */ -/* TC1_LUPD Predefined. */ - -/* TC1_DIR Predefined. */ -/* TC1_DIR Predefined. */ - -/* TC1.CTRLGCLR bit masks and bit positions */ -#define TC1_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ -#define TC1_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ - -#define TC1_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ -#define TC1_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ - -#define TC1_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ -#define TC1_PERBV_bp 0 /* Period Buffer Valid bit position. */ - -/* TC1.CTRLGSET bit masks and bit positions */ -/* TC1_CCBBV Predefined. */ -/* TC1_CCBBV Predefined. */ - -/* TC1_CCABV Predefined. */ -/* TC1_CCABV Predefined. */ - -/* TC1_PERBV Predefined. */ -/* TC1_PERBV Predefined. */ - -/* TC1.INTFLAGS bit masks and bit positions */ -#define TC1_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ -#define TC1_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ - -#define TC1_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ -#define TC1_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ - -#define TC1_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ -#define TC1_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ - -#define TC1_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ -#define TC1_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ - -/* TC2 - 16-bit Timer/Counter type 2 */ -/* TC2.CTRLA bit masks and bit positions */ -#define TC2_CLKSEL_gm 0x0F /* Clock Selection group mask. */ -#define TC2_CLKSEL_gp 0 /* Clock Selection group position. */ -#define TC2_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ -#define TC2_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ -#define TC2_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ -#define TC2_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ -#define TC2_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ -#define TC2_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ -#define TC2_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ -#define TC2_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ - -/* TC2.CTRLB bit masks and bit positions */ -#define TC2_HCMPDEN_bm 0x80 /* High Byte Compare D Enable bit mask. */ -#define TC2_HCMPDEN_bp 7 /* High Byte Compare D Enable bit position. */ - -#define TC2_HCMPCEN_bm 0x40 /* High Byte Compare C Enable bit mask. */ -#define TC2_HCMPCEN_bp 6 /* High Byte Compare C Enable bit position. */ - -#define TC2_HCMPBEN_bm 0x20 /* High Byte Compare B Enable bit mask. */ -#define TC2_HCMPBEN_bp 5 /* High Byte Compare B Enable bit position. */ - -#define TC2_HCMPAEN_bm 0x10 /* High Byte Compare A Enable bit mask. */ -#define TC2_HCMPAEN_bp 4 /* High Byte Compare A Enable bit position. */ - -#define TC2_LCMPDEN_bm 0x08 /* Low Byte Compare D Enable bit mask. */ -#define TC2_LCMPDEN_bp 3 /* Low Byte Compare D Enable bit position. */ - -#define TC2_LCMPCEN_bm 0x04 /* Low Byte Compare C Enable bit mask. */ -#define TC2_LCMPCEN_bp 2 /* Low Byte Compare C Enable bit position. */ - -#define TC2_LCMPBEN_bm 0x02 /* Low Byte Compare B Enable bit mask. */ -#define TC2_LCMPBEN_bp 1 /* Low Byte Compare B Enable bit position. */ - -#define TC2_LCMPAEN_bm 0x01 /* Low Byte Compare A Enable bit mask. */ -#define TC2_LCMPAEN_bp 0 /* Low Byte Compare A Enable bit position. */ - -/* TC2.CTRLC bit masks and bit positions */ -#define TC2_HCMPD_bm 0x80 /* High Byte Compare D Output Value bit mask. */ -#define TC2_HCMPD_bp 7 /* High Byte Compare D Output Value bit position. */ - -#define TC2_HCMPC_bm 0x40 /* High Byte Compare C Output Value bit mask. */ -#define TC2_HCMPC_bp 6 /* High Byte Compare C Output Value bit position. */ - -#define TC2_HCMPB_bm 0x20 /* High Byte Compare B Output Value bit mask. */ -#define TC2_HCMPB_bp 5 /* High Byte Compare B Output Value bit position. */ - -#define TC2_HCMPA_bm 0x10 /* High Byte Compare A Output Value bit mask. */ -#define TC2_HCMPA_bp 4 /* High Byte Compare A Output Value bit position. */ - -#define TC2_LCMPD_bm 0x08 /* Low Byte Compare D Output Value bit mask. */ -#define TC2_LCMPD_bp 3 /* Low Byte Compare D Output Value bit position. */ - -#define TC2_LCMPC_bm 0x04 /* Low Byte Compare C Output Value bit mask. */ -#define TC2_LCMPC_bp 2 /* Low Byte Compare C Output Value bit position. */ - -#define TC2_LCMPB_bm 0x02 /* Low Byte Compare B Output Value bit mask. */ -#define TC2_LCMPB_bp 1 /* Low Byte Compare B Output Value bit position. */ - -#define TC2_LCMPA_bm 0x01 /* Low Byte Compare A Output Value bit mask. */ -#define TC2_LCMPA_bp 0 /* Low Byte Compare A Output Value bit position. */ - -/* TC2.CTRLE bit masks and bit positions */ -#define TC2_BYTEM_gm 0x03 /* Byte Mode group mask. */ -#define TC2_BYTEM_gp 0 /* Byte Mode group position. */ -#define TC2_BYTEM0_bm (1<<0) /* Byte Mode bit 0 mask. */ -#define TC2_BYTEM0_bp 0 /* Byte Mode bit 0 position. */ -#define TC2_BYTEM1_bm (1<<1) /* Byte Mode bit 1 mask. */ -#define TC2_BYTEM1_bp 1 /* Byte Mode bit 1 position. */ - -/* TC2.INTCTRLA bit masks and bit positions */ -#define TC2_HUNFINTLVL_gm 0x0C /* High Byte Underflow Interrupt Level group mask. */ -#define TC2_HUNFINTLVL_gp 2 /* High Byte Underflow Interrupt Level group position. */ -#define TC2_HUNFINTLVL0_bm (1<<2) /* High Byte Underflow Interrupt Level bit 0 mask. */ -#define TC2_HUNFINTLVL0_bp 2 /* High Byte Underflow Interrupt Level bit 0 position. */ -#define TC2_HUNFINTLVL1_bm (1<<3) /* High Byte Underflow Interrupt Level bit 1 mask. */ -#define TC2_HUNFINTLVL1_bp 3 /* High Byte Underflow Interrupt Level bit 1 position. */ - -#define TC2_LUNFINTLVL_gm 0x03 /* Low Byte Underflow interrupt level group mask. */ -#define TC2_LUNFINTLVL_gp 0 /* Low Byte Underflow interrupt level group position. */ -#define TC2_LUNFINTLVL0_bm (1<<0) /* Low Byte Underflow interrupt level bit 0 mask. */ -#define TC2_LUNFINTLVL0_bp 0 /* Low Byte Underflow interrupt level bit 0 position. */ -#define TC2_LUNFINTLVL1_bm (1<<1) /* Low Byte Underflow interrupt level bit 1 mask. */ -#define TC2_LUNFINTLVL1_bp 1 /* Low Byte Underflow interrupt level bit 1 position. */ - -/* TC2.INTCTRLB bit masks and bit positions */ -#define TC2_LCMPDINTLVL_gm 0xC0 /* Low Byte Compare D Interrupt Level group mask. */ -#define TC2_LCMPDINTLVL_gp 6 /* Low Byte Compare D Interrupt Level group position. */ -#define TC2_LCMPDINTLVL0_bm (1<<6) /* Low Byte Compare D Interrupt Level bit 0 mask. */ -#define TC2_LCMPDINTLVL0_bp 6 /* Low Byte Compare D Interrupt Level bit 0 position. */ -#define TC2_LCMPDINTLVL1_bm (1<<7) /* Low Byte Compare D Interrupt Level bit 1 mask. */ -#define TC2_LCMPDINTLVL1_bp 7 /* Low Byte Compare D Interrupt Level bit 1 position. */ - -#define TC2_LCMPCINTLVL_gm 0x30 /* Low Byte Compare C Interrupt Level group mask. */ -#define TC2_LCMPCINTLVL_gp 4 /* Low Byte Compare C Interrupt Level group position. */ -#define TC2_LCMPCINTLVL0_bm (1<<4) /* Low Byte Compare C Interrupt Level bit 0 mask. */ -#define TC2_LCMPCINTLVL0_bp 4 /* Low Byte Compare C Interrupt Level bit 0 position. */ -#define TC2_LCMPCINTLVL1_bm (1<<5) /* Low Byte Compare C Interrupt Level bit 1 mask. */ -#define TC2_LCMPCINTLVL1_bp 5 /* Low Byte Compare C Interrupt Level bit 1 position. */ - -#define TC2_LCMPBINTLVL_gm 0x0C /* Low Byte Compare B Interrupt Level group mask. */ -#define TC2_LCMPBINTLVL_gp 2 /* Low Byte Compare B Interrupt Level group position. */ -#define TC2_LCMPBINTLVL0_bm (1<<2) /* Low Byte Compare B Interrupt Level bit 0 mask. */ -#define TC2_LCMPBINTLVL0_bp 2 /* Low Byte Compare B Interrupt Level bit 0 position. */ -#define TC2_LCMPBINTLVL1_bm (1<<3) /* Low Byte Compare B Interrupt Level bit 1 mask. */ -#define TC2_LCMPBINTLVL1_bp 3 /* Low Byte Compare B Interrupt Level bit 1 position. */ - -#define TC2_LCMPAINTLVL_gm 0x03 /* Low Byte Compare A Interrupt Level group mask. */ -#define TC2_LCMPAINTLVL_gp 0 /* Low Byte Compare A Interrupt Level group position. */ -#define TC2_LCMPAINTLVL0_bm (1<<0) /* Low Byte Compare A Interrupt Level bit 0 mask. */ -#define TC2_LCMPAINTLVL0_bp 0 /* Low Byte Compare A Interrupt Level bit 0 position. */ -#define TC2_LCMPAINTLVL1_bm (1<<1) /* Low Byte Compare A Interrupt Level bit 1 mask. */ -#define TC2_LCMPAINTLVL1_bp 1 /* Low Byte Compare A Interrupt Level bit 1 position. */ - -/* TC2.CTRLF bit masks and bit positions */ -#define TC2_CMD_gm 0x0C /* Command group mask. */ -#define TC2_CMD_gp 2 /* Command group position. */ -#define TC2_CMD0_bm (1<<2) /* Command bit 0 mask. */ -#define TC2_CMD0_bp 2 /* Command bit 0 position. */ -#define TC2_CMD1_bm (1<<3) /* Command bit 1 mask. */ -#define TC2_CMD1_bp 3 /* Command bit 1 position. */ - -#define TC2_CMDEN_gm 0x03 /* Command Enable group mask. */ -#define TC2_CMDEN_gp 0 /* Command Enable group position. */ -#define TC2_CMDEN0_bm (1<<0) /* Command Enable bit 0 mask. */ -#define TC2_CMDEN0_bp 0 /* Command Enable bit 0 position. */ -#define TC2_CMDEN1_bm (1<<1) /* Command Enable bit 1 mask. */ -#define TC2_CMDEN1_bp 1 /* Command Enable bit 1 position. */ - -/* TC2.INTFLAGS bit masks and bit positions */ -#define TC2_LCMPDIF_bm 0x80 /* Low Byte Compare D Interrupt Flag bit mask. */ -#define TC2_LCMPDIF_bp 7 /* Low Byte Compare D Interrupt Flag bit position. */ - -#define TC2_LCMPCIF_bm 0x40 /* Low Byte Compare C Interrupt Flag bit mask. */ -#define TC2_LCMPCIF_bp 6 /* Low Byte Compare C Interrupt Flag bit position. */ - -#define TC2_LCMPBIF_bm 0x20 /* Low Byte Compare B Interrupt Flag bit mask. */ -#define TC2_LCMPBIF_bp 5 /* Low Byte Compare B Interrupt Flag bit position. */ - -#define TC2_LCMPAIF_bm 0x10 /* Low Byte Compare A Interrupt Flag bit mask. */ -#define TC2_LCMPAIF_bp 4 /* Low Byte Compare A Interrupt Flag bit position. */ - -#define TC2_HUNFIF_bm 0x02 /* High Byte Underflow Interrupt Flag bit mask. */ -#define TC2_HUNFIF_bp 1 /* High Byte Underflow Interrupt Flag bit position. */ - -#define TC2_LUNFIF_bm 0x01 /* Low Byte Underflow Interrupt Flag bit mask. */ -#define TC2_LUNFIF_bp 0 /* Low Byte Underflow Interrupt Flag bit position. */ - -/* AWEX - Timer/Counter Advanced Waveform Extension */ -/* AWEX.CTRL bit masks and bit positions */ -#define AWEX_PGM_bm 0x20 /* Pattern Generation Mode bit mask. */ -#define AWEX_PGM_bp 5 /* Pattern Generation Mode bit position. */ - -#define AWEX_CWCM_bm 0x10 /* Common Waveform Channel Mode bit mask. */ -#define AWEX_CWCM_bp 4 /* Common Waveform Channel Mode bit position. */ - -#define AWEX_DTICCDEN_bm 0x08 /* Dead Time Insertion Compare Channel D Enable bit mask. */ -#define AWEX_DTICCDEN_bp 3 /* Dead Time Insertion Compare Channel D Enable bit position. */ - -#define AWEX_DTICCCEN_bm 0x04 /* Dead Time Insertion Compare Channel C Enable bit mask. */ -#define AWEX_DTICCCEN_bp 2 /* Dead Time Insertion Compare Channel C Enable bit position. */ - -#define AWEX_DTICCBEN_bm 0x02 /* Dead Time Insertion Compare Channel B Enable bit mask. */ -#define AWEX_DTICCBEN_bp 1 /* Dead Time Insertion Compare Channel B Enable bit position. */ - -#define AWEX_DTICCAEN_bm 0x01 /* Dead Time Insertion Compare Channel A Enable bit mask. */ -#define AWEX_DTICCAEN_bp 0 /* Dead Time Insertion Compare Channel A Enable bit position. */ - -/* AWEX.FDCTRL bit masks and bit positions */ -#define AWEX_FDDBD_bm 0x10 /* Fault Detect on Disable Break Disable bit mask. */ -#define AWEX_FDDBD_bp 4 /* Fault Detect on Disable Break Disable bit position. */ - -#define AWEX_FDMODE_bm 0x04 /* Fault Detect Mode bit mask. */ -#define AWEX_FDMODE_bp 2 /* Fault Detect Mode bit position. */ - -#define AWEX_FDACT_gm 0x03 /* Fault Detect Action group mask. */ -#define AWEX_FDACT_gp 0 /* Fault Detect Action group position. */ -#define AWEX_FDACT0_bm (1<<0) /* Fault Detect Action bit 0 mask. */ -#define AWEX_FDACT0_bp 0 /* Fault Detect Action bit 0 position. */ -#define AWEX_FDACT1_bm (1<<1) /* Fault Detect Action bit 1 mask. */ -#define AWEX_FDACT1_bp 1 /* Fault Detect Action bit 1 position. */ - -/* AWEX.STATUS bit masks and bit positions */ -#define AWEX_FDF_bm 0x04 /* Fault Detect Flag bit mask. */ -#define AWEX_FDF_bp 2 /* Fault Detect Flag bit position. */ - -#define AWEX_DTHSBUFV_bm 0x02 /* Dead Time High Side Buffer Valid bit mask. */ -#define AWEX_DTHSBUFV_bp 1 /* Dead Time High Side Buffer Valid bit position. */ - -#define AWEX_DTLSBUFV_bm 0x01 /* Dead Time Low Side Buffer Valid bit mask. */ -#define AWEX_DTLSBUFV_bp 0 /* Dead Time Low Side Buffer Valid bit position. */ - -/* AWEX.STATUSSET bit masks and bit positions */ -/* AWEX_FDF Predefined. */ -/* AWEX_FDF Predefined. */ - -/* AWEX_DTHSBUFV Predefined. */ -/* AWEX_DTHSBUFV Predefined. */ - -/* AWEX_DTLSBUFV Predefined. */ -/* AWEX_DTLSBUFV Predefined. */ - -/* HIRES - Timer/Counter High-Resolution Extension */ -/* HIRES.CTRLA bit masks and bit positions */ -#define HIRES_HREN_gm 0x03 /* High Resolution Enable group mask. */ -#define HIRES_HREN_gp 0 /* High Resolution Enable group position. */ -#define HIRES_HREN0_bm (1<<0) /* High Resolution Enable bit 0 mask. */ -#define HIRES_HREN0_bp 0 /* High Resolution Enable bit 0 position. */ -#define HIRES_HREN1_bm (1<<1) /* High Resolution Enable bit 1 mask. */ -#define HIRES_HREN1_bp 1 /* High Resolution Enable bit 1 position. */ - -/* USART - Universal Asynchronous Receiver-Transmitter */ -/* USART.STATUS bit masks and bit positions */ -#define USART_RXCIF_bm 0x80 /* Receive Interrupt Flag bit mask. */ -#define USART_RXCIF_bp 7 /* Receive Interrupt Flag bit position. */ - -#define USART_TXCIF_bm 0x40 /* Transmit Interrupt Flag bit mask. */ -#define USART_TXCIF_bp 6 /* Transmit Interrupt Flag bit position. */ - -#define USART_DREIF_bm 0x20 /* Data Register Empty Flag bit mask. */ -#define USART_DREIF_bp 5 /* Data Register Empty Flag bit position. */ - -#define USART_FERR_bm 0x10 /* Frame Error bit mask. */ -#define USART_FERR_bp 4 /* Frame Error bit position. */ - -#define USART_BUFOVF_bm 0x08 /* Buffer Overflow bit mask. */ -#define USART_BUFOVF_bp 3 /* Buffer Overflow bit position. */ - -#define USART_PERR_bm 0x04 /* Parity Error bit mask. */ -#define USART_PERR_bp 2 /* Parity Error bit position. */ - -#define USART_RXB8_bm 0x01 /* Receive Bit 8 bit mask. */ -#define USART_RXB8_bp 0 /* Receive Bit 8 bit position. */ - -/* USART.CTRLA bit masks and bit positions */ -#define USART_RXCINTLVL_gm 0x30 /* Receive Interrupt Level group mask. */ -#define USART_RXCINTLVL_gp 4 /* Receive Interrupt Level group position. */ -#define USART_RXCINTLVL0_bm (1<<4) /* Receive Interrupt Level bit 0 mask. */ -#define USART_RXCINTLVL0_bp 4 /* Receive Interrupt Level bit 0 position. */ -#define USART_RXCINTLVL1_bm (1<<5) /* Receive Interrupt Level bit 1 mask. */ -#define USART_RXCINTLVL1_bp 5 /* Receive Interrupt Level bit 1 position. */ - -#define USART_TXCINTLVL_gm 0x0C /* Transmit Interrupt Level group mask. */ -#define USART_TXCINTLVL_gp 2 /* Transmit Interrupt Level group position. */ -#define USART_TXCINTLVL0_bm (1<<2) /* Transmit Interrupt Level bit 0 mask. */ -#define USART_TXCINTLVL0_bp 2 /* Transmit Interrupt Level bit 0 position. */ -#define USART_TXCINTLVL1_bm (1<<3) /* Transmit Interrupt Level bit 1 mask. */ -#define USART_TXCINTLVL1_bp 3 /* Transmit Interrupt Level bit 1 position. */ - -#define USART_DREINTLVL_gm 0x03 /* Data Register Empty Interrupt Level group mask. */ -#define USART_DREINTLVL_gp 0 /* Data Register Empty Interrupt Level group position. */ -#define USART_DREINTLVL0_bm (1<<0) /* Data Register Empty Interrupt Level bit 0 mask. */ -#define USART_DREINTLVL0_bp 0 /* Data Register Empty Interrupt Level bit 0 position. */ -#define USART_DREINTLVL1_bm (1<<1) /* Data Register Empty Interrupt Level bit 1 mask. */ -#define USART_DREINTLVL1_bp 1 /* Data Register Empty Interrupt Level bit 1 position. */ - -/* USART.CTRLB bit masks and bit positions */ -#define USART_RXEN_bm 0x10 /* Receiver Enable bit mask. */ -#define USART_RXEN_bp 4 /* Receiver Enable bit position. */ - -#define USART_TXEN_bm 0x08 /* Transmitter Enable bit mask. */ -#define USART_TXEN_bp 3 /* Transmitter Enable bit position. */ - -#define USART_CLK2X_bm 0x04 /* Double transmission speed bit mask. */ -#define USART_CLK2X_bp 2 /* Double transmission speed bit position. */ - -#define USART_MPCM_bm 0x02 /* Multi-processor Communication Mode bit mask. */ -#define USART_MPCM_bp 1 /* Multi-processor Communication Mode bit position. */ - -#define USART_TXB8_bm 0x01 /* Transmit bit 8 bit mask. */ -#define USART_TXB8_bp 0 /* Transmit bit 8 bit position. */ - -/* USART.CTRLC bit masks and bit positions */ -#define USART_CMODE_gm 0xC0 /* Communication Mode group mask. */ -#define USART_CMODE_gp 6 /* Communication Mode group position. */ -#define USART_CMODE0_bm (1<<6) /* Communication Mode bit 0 mask. */ -#define USART_CMODE0_bp 6 /* Communication Mode bit 0 position. */ -#define USART_CMODE1_bm (1<<7) /* Communication Mode bit 1 mask. */ -#define USART_CMODE1_bp 7 /* Communication Mode bit 1 position. */ - -#define USART_PMODE_gm 0x30 /* Parity Mode group mask. */ -#define USART_PMODE_gp 4 /* Parity Mode group position. */ -#define USART_PMODE0_bm (1<<4) /* Parity Mode bit 0 mask. */ -#define USART_PMODE0_bp 4 /* Parity Mode bit 0 position. */ -#define USART_PMODE1_bm (1<<5) /* Parity Mode bit 1 mask. */ -#define USART_PMODE1_bp 5 /* Parity Mode bit 1 position. */ - -#define USART_SBMODE_bm 0x08 /* Stop Bit Mode bit mask. */ -#define USART_SBMODE_bp 3 /* Stop Bit Mode bit position. */ - -#define USART_CHSIZE_gm 0x07 /* Character Size group mask. */ -#define USART_CHSIZE_gp 0 /* Character Size group position. */ -#define USART_CHSIZE0_bm (1<<0) /* Character Size bit 0 mask. */ -#define USART_CHSIZE0_bp 0 /* Character Size bit 0 position. */ -#define USART_CHSIZE1_bm (1<<1) /* Character Size bit 1 mask. */ -#define USART_CHSIZE1_bp 1 /* Character Size bit 1 position. */ -#define USART_CHSIZE2_bm (1<<2) /* Character Size bit 2 mask. */ -#define USART_CHSIZE2_bp 2 /* Character Size bit 2 position. */ - -/* USART.BAUDCTRLA bit masks and bit positions */ -#define USART_BSEL_gm 0xFF /* Baud Rate Selection Bits [7:0] group mask. */ -#define USART_BSEL_gp 0 /* Baud Rate Selection Bits [7:0] group position. */ -#define USART_BSEL0_bm (1<<0) /* Baud Rate Selection Bits [7:0] bit 0 mask. */ -#define USART_BSEL0_bp 0 /* Baud Rate Selection Bits [7:0] bit 0 position. */ -#define USART_BSEL1_bm (1<<1) /* Baud Rate Selection Bits [7:0] bit 1 mask. */ -#define USART_BSEL1_bp 1 /* Baud Rate Selection Bits [7:0] bit 1 position. */ -#define USART_BSEL2_bm (1<<2) /* Baud Rate Selection Bits [7:0] bit 2 mask. */ -#define USART_BSEL2_bp 2 /* Baud Rate Selection Bits [7:0] bit 2 position. */ -#define USART_BSEL3_bm (1<<3) /* Baud Rate Selection Bits [7:0] bit 3 mask. */ -#define USART_BSEL3_bp 3 /* Baud Rate Selection Bits [7:0] bit 3 position. */ -#define USART_BSEL4_bm (1<<4) /* Baud Rate Selection Bits [7:0] bit 4 mask. */ -#define USART_BSEL4_bp 4 /* Baud Rate Selection Bits [7:0] bit 4 position. */ -#define USART_BSEL5_bm (1<<5) /* Baud Rate Selection Bits [7:0] bit 5 mask. */ -#define USART_BSEL5_bp 5 /* Baud Rate Selection Bits [7:0] bit 5 position. */ -#define USART_BSEL6_bm (1<<6) /* Baud Rate Selection Bits [7:0] bit 6 mask. */ -#define USART_BSEL6_bp 6 /* Baud Rate Selection Bits [7:0] bit 6 position. */ -#define USART_BSEL7_bm (1<<7) /* Baud Rate Selection Bits [7:0] bit 7 mask. */ -#define USART_BSEL7_bp 7 /* Baud Rate Selection Bits [7:0] bit 7 position. */ - -/* USART.BAUDCTRLB bit masks and bit positions */ -#define USART_BSCALE_gm 0xF0 /* Baud Rate Scale group mask. */ -#define USART_BSCALE_gp 4 /* Baud Rate Scale group position. */ -#define USART_BSCALE0_bm (1<<4) /* Baud Rate Scale bit 0 mask. */ -#define USART_BSCALE0_bp 4 /* Baud Rate Scale bit 0 position. */ -#define USART_BSCALE1_bm (1<<5) /* Baud Rate Scale bit 1 mask. */ -#define USART_BSCALE1_bp 5 /* Baud Rate Scale bit 1 position. */ -#define USART_BSCALE2_bm (1<<6) /* Baud Rate Scale bit 2 mask. */ -#define USART_BSCALE2_bp 6 /* Baud Rate Scale bit 2 position. */ -#define USART_BSCALE3_bm (1<<7) /* Baud Rate Scale bit 3 mask. */ -#define USART_BSCALE3_bp 7 /* Baud Rate Scale bit 3 position. */ - -/* USART_BSEL Predefined. */ -/* USART_BSEL Predefined. */ - -/* SPI - Serial Peripheral Interface */ -/* SPI.CTRL bit masks and bit positions */ -#define SPI_CLK2X_bm 0x80 /* Enable Double Speed bit mask. */ -#define SPI_CLK2X_bp 7 /* Enable Double Speed bit position. */ - -#define SPI_ENABLE_bm 0x40 /* Enable Module bit mask. */ -#define SPI_ENABLE_bp 6 /* Enable Module bit position. */ - -#define SPI_DORD_bm 0x20 /* Data Order Setting bit mask. */ -#define SPI_DORD_bp 5 /* Data Order Setting bit position. */ - -#define SPI_MASTER_bm 0x10 /* Master Operation Enable bit mask. */ -#define SPI_MASTER_bp 4 /* Master Operation Enable bit position. */ - -#define SPI_MODE_gm 0x0C /* SPI Mode group mask. */ -#define SPI_MODE_gp 2 /* SPI Mode group position. */ -#define SPI_MODE0_bm (1<<2) /* SPI Mode bit 0 mask. */ -#define SPI_MODE0_bp 2 /* SPI Mode bit 0 position. */ -#define SPI_MODE1_bm (1<<3) /* SPI Mode bit 1 mask. */ -#define SPI_MODE1_bp 3 /* SPI Mode bit 1 position. */ - -#define SPI_PRESCALER_gm 0x03 /* Prescaler group mask. */ -#define SPI_PRESCALER_gp 0 /* Prescaler group position. */ -#define SPI_PRESCALER0_bm (1<<0) /* Prescaler bit 0 mask. */ -#define SPI_PRESCALER0_bp 0 /* Prescaler bit 0 position. */ -#define SPI_PRESCALER1_bm (1<<1) /* Prescaler bit 1 mask. */ -#define SPI_PRESCALER1_bp 1 /* Prescaler bit 1 position. */ - -/* SPI.INTCTRL bit masks and bit positions */ -#define SPI_INTLVL_gm 0x03 /* Interrupt level group mask. */ -#define SPI_INTLVL_gp 0 /* Interrupt level group position. */ -#define SPI_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */ -#define SPI_INTLVL0_bp 0 /* Interrupt level bit 0 position. */ -#define SPI_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */ -#define SPI_INTLVL1_bp 1 /* Interrupt level bit 1 position. */ - -/* SPI.STATUS bit masks and bit positions */ -#define SPI_IF_bm 0x80 /* Interrupt Flag bit mask. */ -#define SPI_IF_bp 7 /* Interrupt Flag bit position. */ - -#define SPI_WRCOL_bm 0x40 /* Write Collision bit mask. */ -#define SPI_WRCOL_bp 6 /* Write Collision bit position. */ - -/* IRCOM - IR Communication Module */ -/* IRCOM.CTRL bit masks and bit positions */ -#define IRCOM_EVSEL_gm 0x0F /* Event Channel Select group mask. */ -#define IRCOM_EVSEL_gp 0 /* Event Channel Select group position. */ -#define IRCOM_EVSEL0_bm (1<<0) /* Event Channel Select bit 0 mask. */ -#define IRCOM_EVSEL0_bp 0 /* Event Channel Select bit 0 position. */ -#define IRCOM_EVSEL1_bm (1<<1) /* Event Channel Select bit 1 mask. */ -#define IRCOM_EVSEL1_bp 1 /* Event Channel Select bit 1 position. */ -#define IRCOM_EVSEL2_bm (1<<2) /* Event Channel Select bit 2 mask. */ -#define IRCOM_EVSEL2_bp 2 /* Event Channel Select bit 2 position. */ -#define IRCOM_EVSEL3_bm (1<<3) /* Event Channel Select bit 3 mask. */ -#define IRCOM_EVSEL3_bp 3 /* Event Channel Select bit 3 position. */ - -/* FUSE - Fuses and Lockbits */ -/* NVM_FUSES.FUSEBYTE0 bit masks and bit positions */ -#define NVM_FUSES_JTAGUSERID_gm 0xFF /* JTAG User ID group mask. */ -#define NVM_FUSES_JTAGUSERID_gp 0 /* JTAG User ID group position. */ -#define NVM_FUSES_JTAGUSERID0_bm (1<<0) /* JTAG User ID bit 0 mask. */ -#define NVM_FUSES_JTAGUSERID0_bp 0 /* JTAG User ID bit 0 position. */ -#define NVM_FUSES_JTAGUSERID1_bm (1<<1) /* JTAG User ID bit 1 mask. */ -#define NVM_FUSES_JTAGUSERID1_bp 1 /* JTAG User ID bit 1 position. */ -#define NVM_FUSES_JTAGUSERID2_bm (1<<2) /* JTAG User ID bit 2 mask. */ -#define NVM_FUSES_JTAGUSERID2_bp 2 /* JTAG User ID bit 2 position. */ -#define NVM_FUSES_JTAGUSERID3_bm (1<<3) /* JTAG User ID bit 3 mask. */ -#define NVM_FUSES_JTAGUSERID3_bp 3 /* JTAG User ID bit 3 position. */ -#define NVM_FUSES_JTAGUSERID4_bm (1<<4) /* JTAG User ID bit 4 mask. */ -#define NVM_FUSES_JTAGUSERID4_bp 4 /* JTAG User ID bit 4 position. */ -#define NVM_FUSES_JTAGUSERID5_bm (1<<5) /* JTAG User ID bit 5 mask. */ -#define NVM_FUSES_JTAGUSERID5_bp 5 /* JTAG User ID bit 5 position. */ -#define NVM_FUSES_JTAGUSERID6_bm (1<<6) /* JTAG User ID bit 6 mask. */ -#define NVM_FUSES_JTAGUSERID6_bp 6 /* JTAG User ID bit 6 position. */ -#define NVM_FUSES_JTAGUSERID7_bm (1<<7) /* JTAG User ID bit 7 mask. */ -#define NVM_FUSES_JTAGUSERID7_bp 7 /* JTAG User ID bit 7 position. */ - -/* NVM_FUSES.FUSEBYTE1 bit masks and bit positions */ -#define NVM_FUSES_WDWP_gm 0xF0 /* Watchdog Window Timeout Period group mask. */ -#define NVM_FUSES_WDWP_gp 4 /* Watchdog Window Timeout Period group position. */ -#define NVM_FUSES_WDWP0_bm (1<<4) /* Watchdog Window Timeout Period bit 0 mask. */ -#define NVM_FUSES_WDWP0_bp 4 /* Watchdog Window Timeout Period bit 0 position. */ -#define NVM_FUSES_WDWP1_bm (1<<5) /* Watchdog Window Timeout Period bit 1 mask. */ -#define NVM_FUSES_WDWP1_bp 5 /* Watchdog Window Timeout Period bit 1 position. */ -#define NVM_FUSES_WDWP2_bm (1<<6) /* Watchdog Window Timeout Period bit 2 mask. */ -#define NVM_FUSES_WDWP2_bp 6 /* Watchdog Window Timeout Period bit 2 position. */ -#define NVM_FUSES_WDWP3_bm (1<<7) /* Watchdog Window Timeout Period bit 3 mask. */ -#define NVM_FUSES_WDWP3_bp 7 /* Watchdog Window Timeout Period bit 3 position. */ - -#define NVM_FUSES_WDP_gm 0x0F /* Watchdog Timeout Period group mask. */ -#define NVM_FUSES_WDP_gp 0 /* Watchdog Timeout Period group position. */ -#define NVM_FUSES_WDP0_bm (1<<0) /* Watchdog Timeout Period bit 0 mask. */ -#define NVM_FUSES_WDP0_bp 0 /* Watchdog Timeout Period bit 0 position. */ -#define NVM_FUSES_WDP1_bm (1<<1) /* Watchdog Timeout Period bit 1 mask. */ -#define NVM_FUSES_WDP1_bp 1 /* Watchdog Timeout Period bit 1 position. */ -#define NVM_FUSES_WDP2_bm (1<<2) /* Watchdog Timeout Period bit 2 mask. */ -#define NVM_FUSES_WDP2_bp 2 /* Watchdog Timeout Period bit 2 position. */ -#define NVM_FUSES_WDP3_bm (1<<3) /* Watchdog Timeout Period bit 3 mask. */ -#define NVM_FUSES_WDP3_bp 3 /* Watchdog Timeout Period bit 3 position. */ - -/* NVM_FUSES.FUSEBYTE2 bit masks and bit positions */ -#define NVM_FUSES_BOOTRST_bm 0x40 /* Boot Loader Section Reset Vector bit mask. */ -#define NVM_FUSES_BOOTRST_bp 6 /* Boot Loader Section Reset Vector bit position. */ - -#define NVM_FUSES_TOSCSEL_bm 0x20 /* Timer Oscillator pin location bit mask. */ -#define NVM_FUSES_TOSCSEL_bp 5 /* Timer Oscillator pin location bit position. */ - -#define NVM_FUSES_BODPD_gm 0x03 /* BOD Operation in Power-Down Mode group mask. */ -#define NVM_FUSES_BODPD_gp 0 /* BOD Operation in Power-Down Mode group position. */ -#define NVM_FUSES_BODPD0_bm (1<<0) /* BOD Operation in Power-Down Mode bit 0 mask. */ -#define NVM_FUSES_BODPD0_bp 0 /* BOD Operation in Power-Down Mode bit 0 position. */ -#define NVM_FUSES_BODPD1_bm (1<<1) /* BOD Operation in Power-Down Mode bit 1 mask. */ -#define NVM_FUSES_BODPD1_bp 1 /* BOD Operation in Power-Down Mode bit 1 position. */ - -/* NVM_FUSES.FUSEBYTE4 bit masks and bit positions */ -#define NVM_FUSES_RSTDISBL_bm 0x10 /* External Reset Disable bit mask. */ -#define NVM_FUSES_RSTDISBL_bp 4 /* External Reset Disable bit position. */ - -#define NVM_FUSES_SUT_gm 0x0C /* Start-up Time group mask. */ -#define NVM_FUSES_SUT_gp 2 /* Start-up Time group position. */ -#define NVM_FUSES_SUT0_bm (1<<2) /* Start-up Time bit 0 mask. */ -#define NVM_FUSES_SUT0_bp 2 /* Start-up Time bit 0 position. */ -#define NVM_FUSES_SUT1_bm (1<<3) /* Start-up Time bit 1 mask. */ -#define NVM_FUSES_SUT1_bp 3 /* Start-up Time bit 1 position. */ - -#define NVM_FUSES_WDLOCK_bm 0x02 /* Watchdog Timer Lock bit mask. */ -#define NVM_FUSES_WDLOCK_bp 1 /* Watchdog Timer Lock bit position. */ - -#define NVM_FUSES_JTAGEN_bm 0x01 /* JTAG Interface Enable bit mask. */ -#define NVM_FUSES_JTAGEN_bp 0 /* JTAG Interface Enable bit position. */ - -/* NVM_FUSES.FUSEBYTE5 bit masks and bit positions */ -#define NVM_FUSES_BODACT_gm 0x30 /* BOD Operation in Active Mode group mask. */ -#define NVM_FUSES_BODACT_gp 4 /* BOD Operation in Active Mode group position. */ -#define NVM_FUSES_BODACT0_bm (1<<4) /* BOD Operation in Active Mode bit 0 mask. */ -#define NVM_FUSES_BODACT0_bp 4 /* BOD Operation in Active Mode bit 0 position. */ -#define NVM_FUSES_BODACT1_bm (1<<5) /* BOD Operation in Active Mode bit 1 mask. */ -#define NVM_FUSES_BODACT1_bp 5 /* BOD Operation in Active Mode bit 1 position. */ - -#define NVM_FUSES_EESAVE_bm 0x08 /* Preserve EEPROM Through Chip Erase bit mask. */ -#define NVM_FUSES_EESAVE_bp 3 /* Preserve EEPROM Through Chip Erase bit position. */ - -#define NVM_FUSES_BODLVL_gm 0x07 /* Brownout Detection Voltage Level group mask. */ -#define NVM_FUSES_BODLVL_gp 0 /* Brownout Detection Voltage Level group position. */ -#define NVM_FUSES_BODLVL0_bm (1<<0) /* Brownout Detection Voltage Level bit 0 mask. */ -#define NVM_FUSES_BODLVL0_bp 0 /* Brownout Detection Voltage Level bit 0 position. */ -#define NVM_FUSES_BODLVL1_bm (1<<1) /* Brownout Detection Voltage Level bit 1 mask. */ -#define NVM_FUSES_BODLVL1_bp 1 /* Brownout Detection Voltage Level bit 1 position. */ -#define NVM_FUSES_BODLVL2_bm (1<<2) /* Brownout Detection Voltage Level bit 2 mask. */ -#define NVM_FUSES_BODLVL2_bp 2 /* Brownout Detection Voltage Level bit 2 position. */ - -/* LOCKBIT - Fuses and Lockbits */ -/* NVM_LOCKBITS.LOCKBITS bit masks and bit positions */ -#define NVM_LOCKBITS_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ -#define NVM_LOCKBITS_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ -#define NVM_LOCKBITS_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ -#define NVM_LOCKBITS_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ -#define NVM_LOCKBITS_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ -#define NVM_LOCKBITS_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ - -#define NVM_LOCKBITS_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ -#define NVM_LOCKBITS_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ -#define NVM_LOCKBITS_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ -#define NVM_LOCKBITS_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ -#define NVM_LOCKBITS_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ -#define NVM_LOCKBITS_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ - -#define NVM_LOCKBITS_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ -#define NVM_LOCKBITS_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ -#define NVM_LOCKBITS_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ -#define NVM_LOCKBITS_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ -#define NVM_LOCKBITS_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ -#define NVM_LOCKBITS_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ - -#define NVM_LOCKBITS_LB_gm 0x03 /* Lock Bits group mask. */ -#define NVM_LOCKBITS_LB_gp 0 /* Lock Bits group position. */ -#define NVM_LOCKBITS_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ -#define NVM_LOCKBITS_LB0_bp 0 /* Lock Bits bit 0 position. */ -#define NVM_LOCKBITS_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ -#define NVM_LOCKBITS_LB1_bp 1 /* Lock Bits bit 1 position. */ - - - -// Generic Port Pins - -#define PIN0_bm 0x01 -#define PIN0_bp 0 -#define PIN1_bm 0x02 -#define PIN1_bp 1 -#define PIN2_bm 0x04 -#define PIN2_bp 2 -#define PIN3_bm 0x08 -#define PIN3_bp 3 -#define PIN4_bm 0x10 -#define PIN4_bp 4 -#define PIN5_bm 0x20 -#define PIN5_bp 5 -#define PIN6_bm 0x40 -#define PIN6_bp 6 -#define PIN7_bm 0x80 -#define PIN7_bp 7 - -/* ========== Interrupt Vector Definitions ========== */ -/* Vector 0 is the reset vector */ - -/* OSC interrupt vectors */ -#define OSC_OSCF_vect_num 1 -#define OSC_OSCF_vect _VECTOR(1) /* Oscillator Failure Interrupt (NMI) */ - -/* PORTC interrupt vectors */ -#define PORTC_INT0_vect_num 2 -#define PORTC_INT0_vect _VECTOR(2) /* External Interrupt 0 */ -#define PORTC_INT1_vect_num 3 -#define PORTC_INT1_vect _VECTOR(3) /* External Interrupt 1 */ - -/* PORTR interrupt vectors */ -#define PORTR_INT0_vect_num 4 -#define PORTR_INT0_vect _VECTOR(4) /* External Interrupt 0 */ -#define PORTR_INT1_vect_num 5 -#define PORTR_INT1_vect _VECTOR(5) /* External Interrupt 1 */ - -/* DMA interrupt vectors */ -#define DMA_CH0_vect_num 6 -#define DMA_CH0_vect _VECTOR(6) /* Channel 0 Interrupt */ -#define DMA_CH1_vect_num 7 -#define DMA_CH1_vect _VECTOR(7) /* Channel 1 Interrupt */ -#define DMA_CH2_vect_num 8 -#define DMA_CH2_vect _VECTOR(8) /* Channel 2 Interrupt */ -#define DMA_CH3_vect_num 9 -#define DMA_CH3_vect _VECTOR(9) /* Channel 3 Interrupt */ - -/* RTC interrupt vectors */ -#define RTC_OVF_vect_num 10 -#define RTC_OVF_vect _VECTOR(10) /* Overflow Interrupt */ -#define RTC_COMP_vect_num 11 -#define RTC_COMP_vect _VECTOR(11) /* Compare Interrupt */ - -/* TWIC interrupt vectors */ -#define TWIC_TWIS_vect_num 12 -#define TWIC_TWIS_vect _VECTOR(12) /* TWI Slave Interrupt */ -#define TWIC_TWIM_vect_num 13 -#define TWIC_TWIM_vect _VECTOR(13) /* TWI Master Interrupt */ - -/* TCC0 interrupt vectors */ -#define TCC0_OVF_vect_num 14 -#define TCC0_OVF_vect _VECTOR(14) /* Overflow Interrupt */ - -/* TCC2 interrupt vectors */ -#define TCC2_LUNF_vect_num 14 -#define TCC2_LUNF_vect _VECTOR(14) /* Low Byte Underflow Interrupt */ - -/* TCC0 interrupt vectors */ -#define TCC0_ERR_vect_num 15 -#define TCC0_ERR_vect _VECTOR(15) /* Error Interrupt */ - -/* TCC2 interrupt vectors */ -#define TCC2_HUNF_vect_num 15 -#define TCC2_HUNF_vect _VECTOR(15) /* High Byte Underflow Interrupt */ - -/* TCC0 interrupt vectors */ -#define TCC0_CCA_vect_num 16 -#define TCC0_CCA_vect _VECTOR(16) /* Compare or Capture A Interrupt */ - -/* TCC2 interrupt vectors */ -#define TCC2_LCMPA_vect_num 16 -#define TCC2_LCMPA_vect _VECTOR(16) /* Low Byte Compare A Interrupt */ - -/* TCC0 interrupt vectors */ -#define TCC0_CCB_vect_num 17 -#define TCC0_CCB_vect _VECTOR(17) /* Compare or Capture B Interrupt */ - -/* TCC2 interrupt vectors */ -#define TCC2_LCMPB_vect_num 17 -#define TCC2_LCMPB_vect _VECTOR(17) /* Low Byte Compare B Interrupt */ - -/* TCC0 interrupt vectors */ -#define TCC0_CCC_vect_num 18 -#define TCC0_CCC_vect _VECTOR(18) /* Compare or Capture C Interrupt */ - -/* TCC2 interrupt vectors */ -#define TCC2_LCMPC_vect_num 18 -#define TCC2_LCMPC_vect _VECTOR(18) /* Low Byte Compare C Interrupt */ - -/* TCC0 interrupt vectors */ -#define TCC0_CCD_vect_num 19 -#define TCC0_CCD_vect _VECTOR(19) /* Compare or Capture D Interrupt */ - -/* TCC2 interrupt vectors */ -#define TCC2_LCMPD_vect_num 19 -#define TCC2_LCMPD_vect _VECTOR(19) /* Low Byte Compare D Interrupt */ - -/* TCC1 interrupt vectors */ -#define TCC1_OVF_vect_num 20 -#define TCC1_OVF_vect _VECTOR(20) /* Overflow Interrupt */ -#define TCC1_ERR_vect_num 21 -#define TCC1_ERR_vect _VECTOR(21) /* Error Interrupt */ -#define TCC1_CCA_vect_num 22 -#define TCC1_CCA_vect _VECTOR(22) /* Compare or Capture A Interrupt */ -#define TCC1_CCB_vect_num 23 -#define TCC1_CCB_vect _VECTOR(23) /* Compare or Capture B Interrupt */ - -/* SPIC interrupt vectors */ -#define SPIC_INT_vect_num 24 -#define SPIC_INT_vect _VECTOR(24) /* SPI Interrupt */ - -/* USARTC0 interrupt vectors */ -#define USARTC0_RXC_vect_num 25 -#define USARTC0_RXC_vect _VECTOR(25) /* Reception Complete Interrupt */ -#define USARTC0_DRE_vect_num 26 -#define USARTC0_DRE_vect _VECTOR(26) /* Data Register Empty Interrupt */ -#define USARTC0_TXC_vect_num 27 -#define USARTC0_TXC_vect _VECTOR(27) /* Transmission Complete Interrupt */ - -/* USARTC1 interrupt vectors */ -#define USARTC1_RXC_vect_num 28 -#define USARTC1_RXC_vect _VECTOR(28) /* Reception Complete Interrupt */ -#define USARTC1_DRE_vect_num 29 -#define USARTC1_DRE_vect _VECTOR(29) /* Data Register Empty Interrupt */ -#define USARTC1_TXC_vect_num 30 -#define USARTC1_TXC_vect _VECTOR(30) /* Transmission Complete Interrupt */ - -/* AES interrupt vectors */ -#define AES_INT_vect_num 31 -#define AES_INT_vect _VECTOR(31) /* AES Interrupt */ - -/* NVM interrupt vectors */ -#define NVM_EE_vect_num 32 -#define NVM_EE_vect _VECTOR(32) /* EE Interrupt */ -#define NVM_SPM_vect_num 33 -#define NVM_SPM_vect _VECTOR(33) /* SPM Interrupt */ - -/* PORTB interrupt vectors */ -#define PORTB_INT0_vect_num 34 -#define PORTB_INT0_vect _VECTOR(34) /* External Interrupt 0 */ -#define PORTB_INT1_vect_num 35 -#define PORTB_INT1_vect _VECTOR(35) /* External Interrupt 1 */ - -/* ACB interrupt vectors */ -#define ACB_AC0_vect_num 36 -#define ACB_AC0_vect _VECTOR(36) /* AC0 Interrupt */ -#define ACB_AC1_vect_num 37 -#define ACB_AC1_vect _VECTOR(37) /* AC1 Interrupt */ -#define ACB_ACW_vect_num 38 -#define ACB_ACW_vect _VECTOR(38) /* ACW Window Mode Interrupt */ - -/* ADCB interrupt vectors */ -#define ADCB_CH0_vect_num 39 -#define ADCB_CH0_vect _VECTOR(39) /* Interrupt 0 */ -#define ADCB_CH1_vect_num 40 -#define ADCB_CH1_vect _VECTOR(40) /* Interrupt 1 */ -#define ADCB_CH2_vect_num 41 -#define ADCB_CH2_vect _VECTOR(41) /* Interrupt 2 */ -#define ADCB_CH3_vect_num 42 -#define ADCB_CH3_vect _VECTOR(42) /* Interrupt 3 */ - -/* PORTE interrupt vectors */ -#define PORTE_INT0_vect_num 43 -#define PORTE_INT0_vect _VECTOR(43) /* External Interrupt 0 */ -#define PORTE_INT1_vect_num 44 -#define PORTE_INT1_vect _VECTOR(44) /* External Interrupt 1 */ - -/* TWIE interrupt vectors */ -#define TWIE_TWIS_vect_num 45 -#define TWIE_TWIS_vect _VECTOR(45) /* TWI Slave Interrupt */ -#define TWIE_TWIM_vect_num 46 -#define TWIE_TWIM_vect _VECTOR(46) /* TWI Master Interrupt */ - -/* TCE0 interrupt vectors */ -#define TCE0_OVF_vect_num 47 -#define TCE0_OVF_vect _VECTOR(47) /* Overflow Interrupt */ - -/* TCE2 interrupt vectors */ -#define TCE2_LUNF_vect_num 47 -#define TCE2_LUNF_vect _VECTOR(47) /* Low Byte Underflow Interrupt */ - -/* TCE0 interrupt vectors */ -#define TCE0_ERR_vect_num 48 -#define TCE0_ERR_vect _VECTOR(48) /* Error Interrupt */ - -/* TCE2 interrupt vectors */ -#define TCE2_HUNF_vect_num 48 -#define TCE2_HUNF_vect _VECTOR(48) /* High Byte Underflow Interrupt */ - -/* TCE0 interrupt vectors */ -#define TCE0_CCA_vect_num 49 -#define TCE0_CCA_vect _VECTOR(49) /* Compare or Capture A Interrupt */ - -/* TCE2 interrupt vectors */ -#define TCE2_LCMPA_vect_num 49 -#define TCE2_LCMPA_vect _VECTOR(49) /* Low Byte Compare A Interrupt */ - -/* TCE0 interrupt vectors */ -#define TCE0_CCB_vect_num 50 -#define TCE0_CCB_vect _VECTOR(50) /* Compare or Capture B Interrupt */ - -/* TCE2 interrupt vectors */ -#define TCE2_LCMPB_vect_num 50 -#define TCE2_LCMPB_vect _VECTOR(50) /* Low Byte Compare B Interrupt */ - -/* TCE0 interrupt vectors */ -#define TCE0_CCC_vect_num 51 -#define TCE0_CCC_vect _VECTOR(51) /* Compare or Capture C Interrupt */ - -/* TCE2 interrupt vectors */ -#define TCE2_LCMPC_vect_num 51 -#define TCE2_LCMPC_vect _VECTOR(51) /* Low Byte Compare C Interrupt */ - -/* TCE0 interrupt vectors */ -#define TCE0_CCD_vect_num 52 -#define TCE0_CCD_vect _VECTOR(52) /* Compare or Capture D Interrupt */ - -/* TCE2 interrupt vectors */ -#define TCE2_LCMPD_vect_num 52 -#define TCE2_LCMPD_vect _VECTOR(52) /* Low Byte Compare D Interrupt */ - -/* TCE1 interrupt vectors */ -#define TCE1_OVF_vect_num 53 -#define TCE1_OVF_vect _VECTOR(53) /* Overflow Interrupt */ -#define TCE1_ERR_vect_num 54 -#define TCE1_ERR_vect _VECTOR(54) /* Error Interrupt */ -#define TCE1_CCA_vect_num 55 -#define TCE1_CCA_vect _VECTOR(55) /* Compare or Capture A Interrupt */ -#define TCE1_CCB_vect_num 56 -#define TCE1_CCB_vect _VECTOR(56) /* Compare or Capture B Interrupt */ - -/* SPIE interrupt vectors */ -#define SPIE_INT_vect_num 57 -#define SPIE_INT_vect _VECTOR(57) /* SPI Interrupt */ - -/* USARTE0 interrupt vectors */ -#define USARTE0_RXC_vect_num 58 -#define USARTE0_RXC_vect _VECTOR(58) /* Reception Complete Interrupt */ -#define USARTE0_DRE_vect_num 59 -#define USARTE0_DRE_vect _VECTOR(59) /* Data Register Empty Interrupt */ -#define USARTE0_TXC_vect_num 60 -#define USARTE0_TXC_vect _VECTOR(60) /* Transmission Complete Interrupt */ - -/* USARTE1 interrupt vectors */ -#define USARTE1_RXC_vect_num 61 -#define USARTE1_RXC_vect _VECTOR(61) /* Reception Complete Interrupt */ -#define USARTE1_DRE_vect_num 62 -#define USARTE1_DRE_vect _VECTOR(62) /* Data Register Empty Interrupt */ -#define USARTE1_TXC_vect_num 63 -#define USARTE1_TXC_vect _VECTOR(63) /* Transmission Complete Interrupt */ - -/* PORTD interrupt vectors */ -#define PORTD_INT0_vect_num 64 -#define PORTD_INT0_vect _VECTOR(64) /* External Interrupt 0 */ -#define PORTD_INT1_vect_num 65 -#define PORTD_INT1_vect _VECTOR(65) /* External Interrupt 1 */ - -/* PORTA interrupt vectors */ -#define PORTA_INT0_vect_num 66 -#define PORTA_INT0_vect _VECTOR(66) /* External Interrupt 0 */ -#define PORTA_INT1_vect_num 67 -#define PORTA_INT1_vect _VECTOR(67) /* External Interrupt 1 */ - -/* ACA interrupt vectors */ -#define ACA_AC0_vect_num 68 -#define ACA_AC0_vect _VECTOR(68) /* AC0 Interrupt */ -#define ACA_AC1_vect_num 69 -#define ACA_AC1_vect _VECTOR(69) /* AC1 Interrupt */ -#define ACA_ACW_vect_num 70 -#define ACA_ACW_vect _VECTOR(70) /* ACW Window Mode Interrupt */ - -/* ADCA interrupt vectors */ -#define ADCA_CH0_vect_num 71 -#define ADCA_CH0_vect _VECTOR(71) /* Interrupt 0 */ -#define ADCA_CH1_vect_num 72 -#define ADCA_CH1_vect _VECTOR(72) /* Interrupt 1 */ -#define ADCA_CH2_vect_num 73 -#define ADCA_CH2_vect _VECTOR(73) /* Interrupt 2 */ -#define ADCA_CH3_vect_num 74 -#define ADCA_CH3_vect _VECTOR(74) /* Interrupt 3 */ - -/* TCD0 interrupt vectors */ -#define TCD0_OVF_vect_num 77 -#define TCD0_OVF_vect _VECTOR(77) /* Overflow Interrupt */ - -/* TCD2 interrupt vectors */ -#define TCD2_LUNF_vect_num 77 -#define TCD2_LUNF_vect _VECTOR(77) /* Low Byte Underflow Interrupt */ - -/* TCD0 interrupt vectors */ -#define TCD0_ERR_vect_num 78 -#define TCD0_ERR_vect _VECTOR(78) /* Error Interrupt */ - -/* TCD2 interrupt vectors */ -#define TCD2_HUNF_vect_num 78 -#define TCD2_HUNF_vect _VECTOR(78) /* High Byte Underflow Interrupt */ - -/* TCD0 interrupt vectors */ -#define TCD0_CCA_vect_num 79 -#define TCD0_CCA_vect _VECTOR(79) /* Compare or Capture A Interrupt */ - -/* TCD2 interrupt vectors */ -#define TCD2_LCMPA_vect_num 79 -#define TCD2_LCMPA_vect _VECTOR(79) /* Low Byte Compare A Interrupt */ - -/* TCD0 interrupt vectors */ -#define TCD0_CCB_vect_num 80 -#define TCD0_CCB_vect _VECTOR(80) /* Compare or Capture B Interrupt */ - -/* TCD2 interrupt vectors */ -#define TCD2_LCMPB_vect_num 80 -#define TCD2_LCMPB_vect _VECTOR(80) /* Low Byte Compare B Interrupt */ - -/* TCD0 interrupt vectors */ -#define TCD0_CCC_vect_num 81 -#define TCD0_CCC_vect _VECTOR(81) /* Compare or Capture C Interrupt */ - -/* TCD2 interrupt vectors */ -#define TCD2_LCMPC_vect_num 81 -#define TCD2_LCMPC_vect _VECTOR(81) /* Low Byte Compare C Interrupt */ - -/* TCD0 interrupt vectors */ -#define TCD0_CCD_vect_num 82 -#define TCD0_CCD_vect _VECTOR(82) /* Compare or Capture D Interrupt */ - -/* TCD2 interrupt vectors */ -#define TCD2_LCMPD_vect_num 82 -#define TCD2_LCMPD_vect _VECTOR(82) /* Low Byte Compare D Interrupt */ - -/* TCD1 interrupt vectors */ -#define TCD1_OVF_vect_num 83 -#define TCD1_OVF_vect _VECTOR(83) /* Overflow Interrupt */ -#define TCD1_ERR_vect_num 84 -#define TCD1_ERR_vect _VECTOR(84) /* Error Interrupt */ -#define TCD1_CCA_vect_num 85 -#define TCD1_CCA_vect _VECTOR(85) /* Compare or Capture A Interrupt */ -#define TCD1_CCB_vect_num 86 -#define TCD1_CCB_vect _VECTOR(86) /* Compare or Capture B Interrupt */ - -/* SPID interrupt vectors */ -#define SPID_INT_vect_num 87 -#define SPID_INT_vect _VECTOR(87) /* SPI Interrupt */ - -/* USARTD0 interrupt vectors */ -#define USARTD0_RXC_vect_num 88 -#define USARTD0_RXC_vect _VECTOR(88) /* Reception Complete Interrupt */ -#define USARTD0_DRE_vect_num 89 -#define USARTD0_DRE_vect _VECTOR(89) /* Data Register Empty Interrupt */ -#define USARTD0_TXC_vect_num 90 -#define USARTD0_TXC_vect _VECTOR(90) /* Transmission Complete Interrupt */ - -/* USARTD1 interrupt vectors */ -#define USARTD1_RXC_vect_num 91 -#define USARTD1_RXC_vect _VECTOR(91) /* Reception Complete Interrupt */ -#define USARTD1_DRE_vect_num 92 -#define USARTD1_DRE_vect _VECTOR(92) /* Data Register Empty Interrupt */ -#define USARTD1_TXC_vect_num 93 -#define USARTD1_TXC_vect _VECTOR(93) /* Transmission Complete Interrupt */ - -/* PORTF interrupt vectors */ -#define PORTF_INT0_vect_num 104 -#define PORTF_INT0_vect _VECTOR(104) /* External Interrupt 0 */ -#define PORTF_INT1_vect_num 105 -#define PORTF_INT1_vect _VECTOR(105) /* External Interrupt 1 */ - -/* TCF0 interrupt vectors */ -#define TCF0_OVF_vect_num 108 -#define TCF0_OVF_vect _VECTOR(108) /* Overflow Interrupt */ - -/* TCF2 interrupt vectors */ -#define TCF2_LUNF_vect_num 108 -#define TCF2_LUNF_vect _VECTOR(108) /* Low Byte Underflow Interrupt */ - -/* TCF0 interrupt vectors */ -#define TCF0_ERR_vect_num 109 -#define TCF0_ERR_vect _VECTOR(109) /* Error Interrupt */ - -/* TCF2 interrupt vectors */ -#define TCF2_HUNF_vect_num 109 -#define TCF2_HUNF_vect _VECTOR(109) /* High Byte Underflow Interrupt */ - -/* TCF0 interrupt vectors */ -#define TCF0_CCA_vect_num 110 -#define TCF0_CCA_vect _VECTOR(110) /* Compare or Capture A Interrupt */ - -/* TCF2 interrupt vectors */ -#define TCF2_LCMPA_vect_num 110 -#define TCF2_LCMPA_vect _VECTOR(110) /* Low Byte Compare A Interrupt */ - -/* TCF0 interrupt vectors */ -#define TCF0_CCB_vect_num 111 -#define TCF0_CCB_vect _VECTOR(111) /* Compare or Capture B Interrupt */ - -/* TCF2 interrupt vectors */ -#define TCF2_LCMPB_vect_num 111 -#define TCF2_LCMPB_vect _VECTOR(111) /* Low Byte Compare B Interrupt */ - -/* TCF0 interrupt vectors */ -#define TCF0_CCC_vect_num 112 -#define TCF0_CCC_vect _VECTOR(112) /* Compare or Capture C Interrupt */ - -/* TCF2 interrupt vectors */ -#define TCF2_LCMPC_vect_num 112 -#define TCF2_LCMPC_vect _VECTOR(112) /* Low Byte Compare C Interrupt */ - -/* TCF0 interrupt vectors */ -#define TCF0_CCD_vect_num 113 -#define TCF0_CCD_vect _VECTOR(113) /* Compare or Capture D Interrupt */ - -/* TCF2 interrupt vectors */ -#define TCF2_LCMPD_vect_num 113 -#define TCF2_LCMPD_vect _VECTOR(113) /* Low Byte Compare D Interrupt */ - -/* USARTF0 interrupt vectors */ -#define USARTF0_RXC_vect_num 119 -#define USARTF0_RXC_vect _VECTOR(119) /* Reception Complete Interrupt */ -#define USARTF0_DRE_vect_num 120 -#define USARTF0_DRE_vect _VECTOR(120) /* Data Register Empty Interrupt */ -#define USARTF0_TXC_vect_num 121 -#define USARTF0_TXC_vect _VECTOR(121) /* Transmission Complete Interrupt */ - -/* USB interrupt vectors */ -#define USB_BUSEVENT_vect_num 125 -#define USB_BUSEVENT_vect _VECTOR(125) /* SOF, suspend, resume, reset bus event interrupts, crc, underflow, overflow and stall error interrupts */ -#define USB_TRNCOMPL_vect_num 126 -#define USB_TRNCOMPL_vect _VECTOR(126) /* Transaction complete interrupt */ - -#define _VECTOR_SIZE 4 /* Size of individual vector. */ -#define _VECTORS_SIZE (127 * _VECTOR_SIZE) - - -/* ========== Constants ========== */ - -#define PROGMEM_START (0x0000) -#define PROGMEM_SIZE (270336) -#define PROGMEM_END (PROGMEM_START + PROGMEM_SIZE - 1) - -#define APP_SECTION_START (0x0000) -#define APP_SECTION_SIZE (262144) -#define APP_SECTION_PAGE_SIZE (512) -#define APP_SECTION_END (APP_SECTION_START + APP_SECTION_SIZE - 1) - -#define APPTABLE_SECTION_START (0x3E000) -#define APPTABLE_SECTION_SIZE (8192) -#define APPTABLE_SECTION_PAGE_SIZE (512) -#define APPTABLE_SECTION_END (APPTABLE_SECTION_START + APPTABLE_SECTION_SIZE - 1) - -#define BOOT_SECTION_START (0x40000) -#define BOOT_SECTION_SIZE (8192) -#define BOOT_SECTION_PAGE_SIZE (512) -#define BOOT_SECTION_END (BOOT_SECTION_START + BOOT_SECTION_SIZE - 1) - -#define DATAMEM_START (0x0000) -#define DATAMEM_SIZE (24576) -#define DATAMEM_END (DATAMEM_START + DATAMEM_SIZE - 1) - -#define IO_START (0x0000) -#define IO_SIZE (4096) -#define IO_PAGE_SIZE (0) -#define IO_END (IO_START + IO_SIZE - 1) - -#define MAPPED_EEPROM_START (0x1000) -#define MAPPED_EEPROM_SIZE (4096) -#define MAPPED_EEPROM_PAGE_SIZE (0) -#define MAPPED_EEPROM_END (MAPPED_EEPROM_START + MAPPED_EEPROM_SIZE - 1) - -#define INTERNAL_SRAM_START (0x2000) -#define INTERNAL_SRAM_SIZE (16384) -#define INTERNAL_SRAM_PAGE_SIZE (0) -#define INTERNAL_SRAM_END (INTERNAL_SRAM_START + INTERNAL_SRAM_SIZE - 1) - -#define EEPROM_START (0x0000) -#define EEPROM_SIZE (4096) -#define EEPROM_PAGE_SIZE (32) -#define EEPROM_END (EEPROM_START + EEPROM_SIZE - 1) - -#define SIGNATURES_START (0x0000) -#define SIGNATURES_SIZE (3) -#define SIGNATURES_PAGE_SIZE (0) -#define SIGNATURES_END (SIGNATURES_START + SIGNATURES_SIZE - 1) - -#define FUSES_START (0x0000) -#define FUSES_SIZE (6) -#define FUSES_PAGE_SIZE (0) -#define FUSES_END (FUSES_START + FUSES_SIZE - 1) - -#define LOCKBITS_START (0x0000) -#define LOCKBITS_SIZE (1) -#define LOCKBITS_PAGE_SIZE (0) -#define LOCKBITS_END (LOCKBITS_START + LOCKBITS_SIZE - 1) - -#define USER_SIGNATURES_START (0x0000) -#define USER_SIGNATURES_SIZE (512) -#define USER_SIGNATURES_PAGE_SIZE (512) -#define USER_SIGNATURES_END (USER_SIGNATURES_START + USER_SIGNATURES_SIZE - 1) - -#define PROD_SIGNATURES_START (0x0000) -#define PROD_SIGNATURES_SIZE (52) -#define PROD_SIGNATURES_PAGE_SIZE (512) -#define PROD_SIGNATURES_END (PROD_SIGNATURES_START + PROD_SIGNATURES_SIZE - 1) - -#define FLASHSTART PROGMEM_START -#define FLASHEND PROGMEM_END -#define SPM_PAGESIZE 512 -#define RAMSTART INTERNAL_SRAM_START -#define RAMSIZE INTERNAL_SRAM_SIZE -#define RAMEND INTERNAL_SRAM_END -#define E2END EEPROM_END -#define E2PAGESIZE EEPROM_PAGE_SIZE - - -/* ========== Fuses ========== */ -#define FUSE_MEMORY_SIZE 6 - -/* Fuse Byte 0 */ -#define FUSE_JTAGUSERID0 (unsigned char)~_BV(0) /* JTAG User ID Bit 0 */ -#define FUSE_JTAGUSERID1 (unsigned char)~_BV(1) /* JTAG User ID Bit 1 */ -#define FUSE_JTAGUSERID2 (unsigned char)~_BV(2) /* JTAG User ID Bit 2 */ -#define FUSE_JTAGUSERID3 (unsigned char)~_BV(3) /* JTAG User ID Bit 3 */ -#define FUSE_JTAGUSERID4 (unsigned char)~_BV(4) /* JTAG User ID Bit 4 */ -#define FUSE_JTAGUSERID5 (unsigned char)~_BV(5) /* JTAG User ID Bit 5 */ -#define FUSE_JTAGUSERID6 (unsigned char)~_BV(6) /* JTAG User ID Bit 6 */ -#define FUSE_JTAGUSERID7 (unsigned char)~_BV(7) /* JTAG User ID Bit 7 */ -#define FUSE0_DEFAULT (0xFF) - -/* Fuse Byte 1 */ -#define FUSE_WDP0 (unsigned char)~_BV(0) /* Watchdog Timeout Period Bit 0 */ -#define FUSE_WDP1 (unsigned char)~_BV(1) /* Watchdog Timeout Period Bit 1 */ -#define FUSE_WDP2 (unsigned char)~_BV(2) /* Watchdog Timeout Period Bit 2 */ -#define FUSE_WDP3 (unsigned char)~_BV(3) /* Watchdog Timeout Period Bit 3 */ -#define FUSE_WDWP0 (unsigned char)~_BV(4) /* Watchdog Window Timeout Period Bit 0 */ -#define FUSE_WDWP1 (unsigned char)~_BV(5) /* Watchdog Window Timeout Period Bit 1 */ -#define FUSE_WDWP2 (unsigned char)~_BV(6) /* Watchdog Window Timeout Period Bit 2 */ -#define FUSE_WDWP3 (unsigned char)~_BV(7) /* Watchdog Window Timeout Period Bit 3 */ -#define FUSE1_DEFAULT (0xFF) - -/* Fuse Byte 2 */ -#define FUSE_BODPD0 (unsigned char)~_BV(0) /* BOD Operation in Power-Down Mode Bit 0 */ -#define FUSE_BODPD1 (unsigned char)~_BV(1) /* BOD Operation in Power-Down Mode Bit 1 */ -#define FUSE_TOSCSEL (unsigned char)~_BV(5) /* Timer Oscillator pin location */ -#define FUSE_BOOTRST (unsigned char)~_BV(6) /* Boot Loader Section Reset Vector */ -#define FUSE2_DEFAULT (0xFF) - -/* Fuse Byte 3 Reserved */ - -/* Fuse Byte 4 */ -#define FUSE_JTAGEN (unsigned char)~_BV(0) /* JTAG Interface Enable */ -#define FUSE_WDLOCK (unsigned char)~_BV(1) /* Watchdog Timer Lock */ -#define FUSE_SUT0 (unsigned char)~_BV(2) /* Start-up Time Bit 0 */ -#define FUSE_SUT1 (unsigned char)~_BV(3) /* Start-up Time Bit 1 */ -#define FUSE_RSTDISBL (unsigned char)~_BV(4) /* External Reset Disable */ -#define FUSE4_DEFAULT (0xFF) - -/* Fuse Byte 5 */ -#define FUSE_BODLVL0 (unsigned char)~_BV(0) /* Brownout Detection Voltage Level Bit 0 */ -#define FUSE_BODLVL1 (unsigned char)~_BV(1) /* Brownout Detection Voltage Level Bit 1 */ -#define FUSE_BODLVL2 (unsigned char)~_BV(2) /* Brownout Detection Voltage Level Bit 2 */ -#define FUSE_EESAVE (unsigned char)~_BV(3) /* Preserve EEPROM Through Chip Erase */ -#define FUSE_BODACT0 (unsigned char)~_BV(4) /* BOD Operation in Active Mode Bit 0 */ -#define FUSE_BODACT1 (unsigned char)~_BV(5) /* BOD Operation in Active Mode Bit 1 */ -#define FUSE5_DEFAULT (0xFF) - -/* ========== Lock Bits ========== */ -#define __LOCK_BITS_EXIST -#define __BOOT_LOCK_APPLICATION_TABLE_BITS_EXIST -#define __BOOT_LOCK_APPLICATION_BITS_EXIST -#define __BOOT_LOCK_BOOT_BITS_EXIST - -/* ========== Signature ========== */ -#define SIGNATURE_0 0x1E -#define SIGNATURE_1 0x98 -#define SIGNATURE_2 0x42 - -/* ========== Power Reduction Condition Definitions ========== */ - -/* PR.PRGEN */ -#define __AVR_HAVE_PRGEN (PR_USB_bm|PR_AES_bm|PR_EBI_bm|PR_RTC_bm|PR_EVSYS_bm|PR_DMA_bm) -#define __AVR_HAVE_PRGEN_USB -#define __AVR_HAVE_PRGEN_AES -#define __AVR_HAVE_PRGEN_EBI -#define __AVR_HAVE_PRGEN_RTC -#define __AVR_HAVE_PRGEN_EVSYS -#define __AVR_HAVE_PRGEN_DMA - -/* PR.PRPA */ -#define __AVR_HAVE_PRPA (PR_DAC_bm|PR_ADC_bm|PR_AC_bm) -#define __AVR_HAVE_PRPA_DAC -#define __AVR_HAVE_PRPA_ADC -#define __AVR_HAVE_PRPA_AC - -/* PR.PRPB */ -#define __AVR_HAVE_PRPB (PR_DAC_bm|PR_ADC_bm|PR_AC_bm) -#define __AVR_HAVE_PRPB_DAC -#define __AVR_HAVE_PRPB_ADC -#define __AVR_HAVE_PRPB_AC - -/* PR.PRPC */ -#define __AVR_HAVE_PRPC (PR_TWI_bm|PR_USART1_bm|PR_USART0_bm|PR_SPI_bm|PR_HIRES_bm|PR_TC1_bm|PR_TC0_bm) -#define __AVR_HAVE_PRPC_TWI -#define __AVR_HAVE_PRPC_USART1 -#define __AVR_HAVE_PRPC_USART0 -#define __AVR_HAVE_PRPC_SPI -#define __AVR_HAVE_PRPC_HIRES -#define __AVR_HAVE_PRPC_TC1 -#define __AVR_HAVE_PRPC_TC0 - -/* PR.PRPD */ -#define __AVR_HAVE_PRPD (PR_TWI_bm|PR_USART1_bm|PR_USART0_bm|PR_SPI_bm|PR_HIRES_bm|PR_TC1_bm|PR_TC0_bm) -#define __AVR_HAVE_PRPD_TWI -#define __AVR_HAVE_PRPD_USART1 -#define __AVR_HAVE_PRPD_USART0 -#define __AVR_HAVE_PRPD_SPI -#define __AVR_HAVE_PRPD_HIRES -#define __AVR_HAVE_PRPD_TC1 -#define __AVR_HAVE_PRPD_TC0 - -/* PR.PRPE */ -#define __AVR_HAVE_PRPE (PR_TWI_bm|PR_USART1_bm|PR_USART0_bm|PR_SPI_bm|PR_HIRES_bm|PR_TC1_bm|PR_TC0_bm) -#define __AVR_HAVE_PRPE_TWI -#define __AVR_HAVE_PRPE_USART1 -#define __AVR_HAVE_PRPE_USART0 -#define __AVR_HAVE_PRPE_SPI -#define __AVR_HAVE_PRPE_HIRES -#define __AVR_HAVE_PRPE_TC1 -#define __AVR_HAVE_PRPE_TC0 - -/* PR.PRPF */ -#define __AVR_HAVE_PRPF (PR_TWI_bm|PR_USART1_bm|PR_USART0_bm|PR_SPI_bm|PR_HIRES_bm|PR_TC1_bm|PR_TC0_bm) -#define __AVR_HAVE_PRPF_TWI -#define __AVR_HAVE_PRPF_USART1 -#define __AVR_HAVE_PRPF_USART0 -#define __AVR_HAVE_PRPF_SPI -#define __AVR_HAVE_PRPF_HIRES -#define __AVR_HAVE_PRPF_TC1 -#define __AVR_HAVE_PRPF_TC0 - - -#endif /* #ifdef _AVR_ATXMEGA256A3U_H_INCLUDED */ - diff --git a/arduino/hardware/tools/avr/avr/include/avr/iox256c3.h b/arduino/hardware/tools/avr/avr/include/avr/iox256c3.h deleted file mode 100644 index a856f62..0000000 --- a/arduino/hardware/tools/avr/avr/include/avr/iox256c3.h +++ /dev/null @@ -1,6264 +0,0 @@ -/***************************************************************************** - * - * Copyright (C) 2015 Atmel Corporation - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * - * * Neither the name of the copyright holders nor the names of - * contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - ****************************************************************************/ - - -#ifndef _AVR_IO_H_ -# error "Include instead of this file." -#endif - -#ifndef _AVR_IOXXX_H_ -# define _AVR_IOXXX_H_ "iox256c3.h" -#else -# error "Attempt to include more than one file." -#endif - -#ifndef _AVR_ATXMEGA256C3_H_INCLUDED -#define _AVR_ATXMEGA256C3_H_INCLUDED - -/* Ungrouped common registers */ -#define GPIOR0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ -#define GPIOR1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ -#define GPIOR2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ -#define GPIOR3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ - -/* Deprecated */ -#define GPIO0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ -#define GPIO1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ -#define GPIO2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ -#define GPIO3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ - -#define CCP _SFR_MEM8(0x0034) /* Configuration Change Protection */ -#define RAMPD _SFR_MEM8(0x0038) /* Ramp D */ -#define RAMPX _SFR_MEM8(0x0039) /* Ramp X */ -#define RAMPY _SFR_MEM8(0x003A) /* Ramp Y */ -#define RAMPZ _SFR_MEM8(0x003B) /* Ramp Z */ -#define EIND _SFR_MEM8(0x003C) /* Extended Indirect Jump */ -#define SPL _SFR_MEM8(0x003D) /* Stack Pointer Low */ -#define SPH _SFR_MEM8(0x003E) /* Stack Pointer High */ -#define SREG _SFR_MEM8(0x003F) /* Status Register */ - -/* C Language Only */ -#if !defined (__ASSEMBLER__) - -#include - -typedef volatile uint8_t register8_t; -typedef volatile uint16_t register16_t; -typedef volatile uint32_t register32_t; - - -#ifdef _WORDREGISTER -#undef _WORDREGISTER -#endif -#define _WORDREGISTER(regname) \ - __extension__ union \ - { \ - register16_t regname; \ - struct \ - { \ - register8_t regname ## L; \ - register8_t regname ## H; \ - }; \ - } - -#ifdef _DWORDREGISTER -#undef _DWORDREGISTER -#endif -#define _DWORDREGISTER(regname) \ - __extension__ union \ - { \ - register32_t regname; \ - struct \ - { \ - register8_t regname ## 0; \ - register8_t regname ## 1; \ - register8_t regname ## 2; \ - register8_t regname ## 3; \ - }; \ - } - - -/* -========================================================================== -IO Module Structures -========================================================================== -*/ - - -/* --------------------------------------------------------------------------- -VPORT - Virtual Ports --------------------------------------------------------------------------- -*/ - -/* Virtual Port */ -typedef struct VPORT_struct -{ - register8_t DIR; /* I/O Port Data Direction */ - register8_t OUT; /* I/O Port Output */ - register8_t IN; /* I/O Port Input */ - register8_t INTFLAGS; /* Interrupt Flag Register */ -} VPORT_t; - - -/* --------------------------------------------------------------------------- -XOCD - On-Chip Debug System --------------------------------------------------------------------------- -*/ - -/* On-Chip Debug System */ -typedef struct OCD_struct -{ - register8_t OCDR0; /* OCD Register 0 */ - register8_t OCDR1; /* OCD Register 1 */ -} OCD_t; - - -/* --------------------------------------------------------------------------- -CPU - CPU --------------------------------------------------------------------------- -*/ - -/* CCP signatures */ -typedef enum CCP_enum -{ - CCP_SPM_gc = (0x9D<<0), /* SPM Instruction Protection */ - CCP_IOREG_gc = (0xD8<<0), /* IO Register Protection */ -} CCP_t; - - -/* --------------------------------------------------------------------------- -CLK - Clock System --------------------------------------------------------------------------- -*/ - -/* Clock System */ -typedef struct CLK_struct -{ - register8_t CTRL; /* Control Register */ - register8_t PSCTRL; /* Prescaler Control Register */ - register8_t LOCK; /* Lock register */ - register8_t RTCCTRL; /* RTC Control Register */ - register8_t USBCTRL; /* USB Control Register */ -} CLK_t; - - -/* Power Reduction */ -typedef struct PR_struct -{ - register8_t PRGEN; /* General Power Reduction */ - register8_t PRPA; /* Power Reduction Port A */ - register8_t reserved_0x02; - register8_t PRPC; /* Power Reduction Port C */ - register8_t PRPD; /* Power Reduction Port D */ - register8_t PRPE; /* Power Reduction Port E */ - register8_t PRPF; /* Power Reduction Port F */ -} PR_t; - -/* System Clock Selection */ -typedef enum CLK_SCLKSEL_enum -{ - CLK_SCLKSEL_RC2M_gc = (0x00<<0), /* Internal 2 MHz RC Oscillator */ - CLK_SCLKSEL_RC32M_gc = (0x01<<0), /* Internal 32 MHz RC Oscillator */ - CLK_SCLKSEL_RC32K_gc = (0x02<<0), /* Internal 32.768 kHz RC Oscillator */ - CLK_SCLKSEL_XOSC_gc = (0x03<<0), /* External Crystal Oscillator or Clock */ - CLK_SCLKSEL_PLL_gc = (0x04<<0), /* Phase Locked Loop */ -} CLK_SCLKSEL_t; - -/* Prescaler A Division Factor */ -typedef enum CLK_PSADIV_enum -{ - CLK_PSADIV_1_gc = (0x00<<2), /* Divide by 1 */ - CLK_PSADIV_2_gc = (0x01<<2), /* Divide by 2 */ - CLK_PSADIV_4_gc = (0x03<<2), /* Divide by 4 */ - CLK_PSADIV_8_gc = (0x05<<2), /* Divide by 8 */ - CLK_PSADIV_16_gc = (0x07<<2), /* Divide by 16 */ - CLK_PSADIV_32_gc = (0x09<<2), /* Divide by 32 */ - CLK_PSADIV_64_gc = (0x0B<<2), /* Divide by 64 */ - CLK_PSADIV_128_gc = (0x0D<<2), /* Divide by 128 */ - CLK_PSADIV_256_gc = (0x0F<<2), /* Divide by 256 */ - CLK_PSADIV_512_gc = (0x11<<2), /* Divide by 512 */ -} CLK_PSADIV_t; - -/* Prescaler B and C Division Factor */ -typedef enum CLK_PSBCDIV_enum -{ - CLK_PSBCDIV_1_1_gc = (0x00<<0), /* Divide B by 1 and C by 1 */ - CLK_PSBCDIV_1_2_gc = (0x01<<0), /* Divide B by 1 and C by 2 */ - CLK_PSBCDIV_4_1_gc = (0x02<<0), /* Divide B by 4 and C by 1 */ - CLK_PSBCDIV_2_2_gc = (0x03<<0), /* Divide B by 2 and C by 2 */ -} CLK_PSBCDIV_t; - -/* RTC Clock Source */ -typedef enum CLK_RTCSRC_enum -{ - CLK_RTCSRC_ULP_gc = (0x00<<1), /* 1.024 kHz from internal 32kHz ULP */ - CLK_RTCSRC_TOSC_gc = (0x01<<1), /* 1.024 kHz from 32.768 kHz crystal oscillator on TOSC */ - CLK_RTCSRC_RCOSC_gc = (0x02<<1), /* 1.024 kHz from internal 32.768 kHz RC oscillator */ - CLK_RTCSRC_TOSC32_gc = (0x05<<1), /* 32.768 kHz from 32.768 kHz crystal oscillator on TOSC */ - CLK_RTCSRC_RCOSC32_gc = (0x06<<1), /* 32.768 kHz from internal 32.768 kHz RC oscillator */ - CLK_RTCSRC_EXTCLK_gc = (0x07<<1), /* External Clock from TOSC1 */ -} CLK_RTCSRC_t; - -/* USB Prescaler Division Factor */ -typedef enum CLK_USBPSDIV_enum -{ - CLK_USBPSDIV_1_gc = (0x00<<3), /* Divide by 1 */ - CLK_USBPSDIV_2_gc = (0x01<<3), /* Divide by 2 */ - CLK_USBPSDIV_4_gc = (0x02<<3), /* Divide by 4 */ - CLK_USBPSDIV_8_gc = (0x03<<3), /* Divide by 8 */ - CLK_USBPSDIV_16_gc = (0x04<<3), /* Divide by 16 */ - CLK_USBPSDIV_32_gc = (0x05<<3), /* Divide by 32 */ -} CLK_USBPSDIV_t; - -/* USB Clock Source */ -typedef enum CLK_USBSRC_enum -{ - CLK_USBSRC_PLL_gc = (0x00<<1), /* PLL */ - CLK_USBSRC_RC32M_gc = (0x01<<1), /* Internal 32 MHz RC Oscillator */ -} CLK_USBSRC_t; - - -/* --------------------------------------------------------------------------- -SLEEP - Sleep Controller --------------------------------------------------------------------------- -*/ - -/* Sleep Controller */ -typedef struct SLEEP_struct -{ - register8_t CTRL; /* Control Register */ -} SLEEP_t; - -/* Sleep Mode */ -typedef enum SLEEP_SMODE_enum -{ - SLEEP_SMODE_IDLE_gc = (0x00<<1), /* Idle mode */ - SLEEP_SMODE_PDOWN_gc = (0x02<<1), /* Power-down Mode */ - SLEEP_SMODE_PSAVE_gc = (0x03<<1), /* Power-save Mode */ - SLEEP_SMODE_STDBY_gc = (0x06<<1), /* Standby Mode */ - SLEEP_SMODE_ESTDBY_gc = (0x07<<1), /* Extended Standby Mode */ -} SLEEP_SMODE_t; - - - -#define SLEEP_MODE_IDLE (0x00<<1) -#define SLEEP_MODE_PWR_DOWN (0x02<<1) -#define SLEEP_MODE_PWR_SAVE (0x03<<1) -#define SLEEP_MODE_STANDBY (0x06<<1) -#define SLEEP_MODE_EXT_STANDBY (0x07<<1) -/* --------------------------------------------------------------------------- -OSC - Oscillator --------------------------------------------------------------------------- -*/ - -/* Oscillator */ -typedef struct OSC_struct -{ - register8_t CTRL; /* Control Register */ - register8_t STATUS; /* Status Register */ - register8_t XOSCCTRL; /* External Oscillator Control Register */ - register8_t XOSCFAIL; /* Oscillator Failure Detection Register */ - register8_t RC32KCAL; /* 32.768 kHz Internal Oscillator Calibration Register */ - register8_t PLLCTRL; /* PLL Control Register */ - register8_t DFLLCTRL; /* DFLL Control Register */ -} OSC_t; - -/* Oscillator Frequency Range */ -typedef enum OSC_FRQRANGE_enum -{ - OSC_FRQRANGE_04TO2_gc = (0x00<<6), /* 0.4 - 2 MHz */ - OSC_FRQRANGE_2TO9_gc = (0x01<<6), /* 2 - 9 MHz */ - OSC_FRQRANGE_9TO12_gc = (0x02<<6), /* 9 - 12 MHz */ - OSC_FRQRANGE_12TO16_gc = (0x03<<6), /* 12 - 16 MHz */ -} OSC_FRQRANGE_t; - -/* External Oscillator Selection and Startup Time */ -typedef enum OSC_XOSCSEL_enum -{ - OSC_XOSCSEL_EXTCLK_gc = (0x00<<0), /* External Clock - 6 CLK */ - OSC_XOSCSEL_32KHz_gc = (0x02<<0), /* 32.768 kHz TOSC - 32K CLK */ - OSC_XOSCSEL_XTAL_256CLK_gc = (0x03<<0), /* 0.4-16 MHz XTAL - 256 CLK */ - OSC_XOSCSEL_XTAL_1KCLK_gc = (0x07<<0), /* 0.4-16 MHz XTAL - 1K CLK */ - OSC_XOSCSEL_XTAL_16KCLK_gc = (0x0B<<0), /* 0.4-16 MHz XTAL - 16K CLK */ -} OSC_XOSCSEL_t; - -/* PLL Clock Source */ -typedef enum OSC_PLLSRC_enum -{ - OSC_PLLSRC_RC2M_gc = (0x00<<6), /* Internal 2 MHz RC Oscillator */ - OSC_PLLSRC_RC32M_gc = (0x02<<6), /* Internal 32 MHz RC Oscillator */ - OSC_PLLSRC_XOSC_gc = (0x03<<6), /* External Oscillator */ -} OSC_PLLSRC_t; - -/* 2 MHz DFLL Calibration Reference */ -typedef enum OSC_RC2MCREF_enum -{ - OSC_RC2MCREF_RC32K_gc = (0x00<<0), /* Internal 32.768 kHz RC Oscillator */ - OSC_RC2MCREF_XOSC32K_gc = (0x01<<0), /* External 32.768 kHz Crystal Oscillator */ -} OSC_RC2MCREF_t; - -/* 32 MHz DFLL Calibration Reference */ -typedef enum OSC_RC32MCREF_enum -{ - OSC_RC32MCREF_RC32K_gc = (0x00<<1), /* Internal 32.768 kHz RC Oscillator */ - OSC_RC32MCREF_XOSC32K_gc = (0x01<<1), /* External 32.768 kHz Crystal Oscillator */ - OSC_RC32MCREF_USBSOF_gc = (0x02<<1), /* USB Start of Frame */ -} OSC_RC32MCREF_t; - - -/* --------------------------------------------------------------------------- -DFLL - DFLL --------------------------------------------------------------------------- -*/ - -/* DFLL */ -typedef struct DFLL_struct -{ - register8_t CTRL; /* Control Register */ - register8_t reserved_0x01; - register8_t CALA; /* Calibration Register A */ - register8_t CALB; /* Calibration Register B */ - register8_t COMP0; /* Oscillator Compare Register 0 */ - register8_t COMP1; /* Oscillator Compare Register 1 */ - register8_t COMP2; /* Oscillator Compare Register 2 */ - register8_t reserved_0x07; -} DFLL_t; - - -/* --------------------------------------------------------------------------- -RST - Reset --------------------------------------------------------------------------- -*/ - -/* Reset */ -typedef struct RST_struct -{ - register8_t STATUS; /* Status Register */ - register8_t CTRL; /* Control Register */ -} RST_t; - - -/* --------------------------------------------------------------------------- -WDT - Watch-Dog Timer --------------------------------------------------------------------------- -*/ - -/* Watch-Dog Timer */ -typedef struct WDT_struct -{ - register8_t CTRL; /* Control */ - register8_t WINCTRL; /* Windowed Mode Control */ - register8_t STATUS; /* Status */ -} WDT_t; - -/* Period setting */ -typedef enum WDT_PER_enum -{ - WDT_PER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ - WDT_PER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ - WDT_PER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ - WDT_PER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ - WDT_PER_128CLK_gc = (0x04<<2), /* 128 cycles (0.128s @ 3.3V) */ - WDT_PER_256CLK_gc = (0x05<<2), /* 256 cycles (0.256s @ 3.3V) */ - WDT_PER_512CLK_gc = (0x06<<2), /* 512 cycles (0.512s @ 3.3V) */ - WDT_PER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ - WDT_PER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ - WDT_PER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ - WDT_PER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ -} WDT_PER_t; - -/* Closed window period */ -typedef enum WDT_WPER_enum -{ - WDT_WPER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ - WDT_WPER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ - WDT_WPER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ - WDT_WPER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ - WDT_WPER_128CLK_gc = (0x04<<2), /* 128 cycles (0.128s @ 3.3V) */ - WDT_WPER_256CLK_gc = (0x05<<2), /* 256 cycles (0.256s @ 3.3V) */ - WDT_WPER_512CLK_gc = (0x06<<2), /* 512 cycles (0.512s @ 3.3V) */ - WDT_WPER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ - WDT_WPER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ - WDT_WPER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ - WDT_WPER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ -} WDT_WPER_t; - - -/* --------------------------------------------------------------------------- -MCU - MCU Control --------------------------------------------------------------------------- -*/ - -/* MCU Control */ -typedef struct MCU_struct -{ - register8_t DEVID0; /* Device ID byte 0 */ - register8_t DEVID1; /* Device ID byte 1 */ - register8_t DEVID2; /* Device ID byte 2 */ - register8_t REVID; /* Revision ID */ - register8_t reserved_0x04; - register8_t reserved_0x05; - register8_t reserved_0x06; - register8_t ANAINIT; /* Analog Startup Delay */ - register8_t EVSYSLOCK; /* Event System Lock */ - register8_t AWEXLOCK; /* AWEX Lock */ - register8_t reserved_0x0A; - register8_t reserved_0x0B; -} MCU_t; - - -/* --------------------------------------------------------------------------- -PMIC - Programmable Multi-level Interrupt Controller --------------------------------------------------------------------------- -*/ - -/* Programmable Multi-level Interrupt Controller */ -typedef struct PMIC_struct -{ - register8_t STATUS; /* Status Register */ - register8_t INTPRI; /* Interrupt Priority */ - register8_t CTRL; /* Control Register */ - register8_t reserved_0x03; - register8_t reserved_0x04; - register8_t reserved_0x05; - register8_t reserved_0x06; - register8_t reserved_0x07; - register8_t reserved_0x08; - register8_t reserved_0x09; - register8_t reserved_0x0A; - register8_t reserved_0x0B; - register8_t reserved_0x0C; - register8_t reserved_0x0D; - register8_t reserved_0x0E; - register8_t reserved_0x0F; -} PMIC_t; - - -/* --------------------------------------------------------------------------- -PORTCFG - Port Configuration --------------------------------------------------------------------------- -*/ - -/* I/O port Configuration */ -typedef struct PORTCFG_struct -{ - register8_t MPCMASK; /* Multi-pin Configuration Mask */ - register8_t reserved_0x01; - register8_t VPCTRLA; /* Virtual Port Control Register A */ - register8_t VPCTRLB; /* Virtual Port Control Register B */ - register8_t CLKEVOUT; /* Clock and Event Out Register */ - register8_t reserved_0x05; - register8_t EVOUTSEL; /* Event Output Select */ -} PORTCFG_t; - -/* Virtual Port Mapping */ -typedef enum PORTCFG_VP02MAP_enum -{ - PORTCFG_VP02MAP_PORTA_gc = (0x00<<0), /* Mapped To PORTA */ - PORTCFG_VP02MAP_PORTB_gc = (0x01<<0), /* Mapped To PORTB */ - PORTCFG_VP02MAP_PORTC_gc = (0x02<<0), /* Mapped To PORTC */ - PORTCFG_VP02MAP_PORTD_gc = (0x03<<0), /* Mapped To PORTD */ - PORTCFG_VP02MAP_PORTE_gc = (0x04<<0), /* Mapped To PORTE */ - PORTCFG_VP02MAP_PORTF_gc = (0x05<<0), /* Mapped To PORTF */ - PORTCFG_VP02MAP_PORTG_gc = (0x06<<0), /* Mapped To PORTG */ - PORTCFG_VP02MAP_PORTH_gc = (0x07<<0), /* Mapped To PORTH */ - PORTCFG_VP02MAP_PORTJ_gc = (0x08<<0), /* Mapped To PORTJ */ - PORTCFG_VP02MAP_PORTK_gc = (0x09<<0), /* Mapped To PORTK */ - PORTCFG_VP02MAP_PORTL_gc = (0x0A<<0), /* Mapped To PORTL */ - PORTCFG_VP02MAP_PORTM_gc = (0x0B<<0), /* Mapped To PORTM */ - PORTCFG_VP02MAP_PORTN_gc = (0x0C<<0), /* Mapped To PORTN */ - PORTCFG_VP02MAP_PORTP_gc = (0x0D<<0), /* Mapped To PORTP */ - PORTCFG_VP02MAP_PORTQ_gc = (0x0E<<0), /* Mapped To PORTQ */ - PORTCFG_VP02MAP_PORTR_gc = (0x0F<<0), /* Mapped To PORTR */ -} PORTCFG_VP02MAP_t; - -/* Virtual Port Mapping */ -typedef enum PORTCFG_VP13MAP_enum -{ - PORTCFG_VP13MAP_PORTA_gc = (0x00<<4), /* Mapped To PORTA */ - PORTCFG_VP13MAP_PORTB_gc = (0x01<<4), /* Mapped To PORTB */ - PORTCFG_VP13MAP_PORTC_gc = (0x02<<4), /* Mapped To PORTC */ - PORTCFG_VP13MAP_PORTD_gc = (0x03<<4), /* Mapped To PORTD */ - PORTCFG_VP13MAP_PORTE_gc = (0x04<<4), /* Mapped To PORTE */ - PORTCFG_VP13MAP_PORTF_gc = (0x05<<4), /* Mapped To PORTF */ - PORTCFG_VP13MAP_PORTG_gc = (0x06<<4), /* Mapped To PORTG */ - PORTCFG_VP13MAP_PORTH_gc = (0x07<<4), /* Mapped To PORTH */ - PORTCFG_VP13MAP_PORTJ_gc = (0x08<<4), /* Mapped To PORTJ */ - PORTCFG_VP13MAP_PORTK_gc = (0x09<<4), /* Mapped To PORTK */ - PORTCFG_VP13MAP_PORTL_gc = (0x0A<<4), /* Mapped To PORTL */ - PORTCFG_VP13MAP_PORTM_gc = (0x0B<<4), /* Mapped To PORTM */ - PORTCFG_VP13MAP_PORTN_gc = (0x0C<<4), /* Mapped To PORTN */ - PORTCFG_VP13MAP_PORTP_gc = (0x0D<<4), /* Mapped To PORTP */ - PORTCFG_VP13MAP_PORTQ_gc = (0x0E<<4), /* Mapped To PORTQ */ - PORTCFG_VP13MAP_PORTR_gc = (0x0F<<4), /* Mapped To PORTR */ -} PORTCFG_VP13MAP_t; - -/* System Clock Output Port */ -typedef enum PORTCFG_CLKOUT_enum -{ - PORTCFG_CLKOUT_OFF_gc = (0x00<<0), /* System Clock Output Disabled */ - PORTCFG_CLKOUT_PC7_gc = (0x01<<0), /* System Clock Output on Port C pin 7 */ - PORTCFG_CLKOUT_PD7_gc = (0x02<<0), /* System Clock Output on Port D pin 7 */ - PORTCFG_CLKOUT_PE7_gc = (0x03<<0), /* System Clock Output on Port E pin 7 */ -} PORTCFG_CLKOUT_t; - -/* Peripheral Clock Output Select */ -typedef enum PORTCFG_CLKOUTSEL_enum -{ - PORTCFG_CLKOUTSEL_CLK1X_gc = (0x00<<2), /* 1x Peripheral Clock Output to pin */ - PORTCFG_CLKOUTSEL_CLK2X_gc = (0x01<<2), /* 2x Peripheral Clock Output to pin */ - PORTCFG_CLKOUTSEL_CLK4X_gc = (0x02<<2), /* 4x Peripheral Clock Output to pin */ -} PORTCFG_CLKOUTSEL_t; - -/* Event Output Port */ -typedef enum PORTCFG_EVOUT_enum -{ - PORTCFG_EVOUT_OFF_gc = (0x00<<4), /* Event Output Disabled */ - PORTCFG_EVOUT_PC7_gc = (0x01<<4), /* Event Channel 7 Output on Port C pin 7 */ - PORTCFG_EVOUT_PD7_gc = (0x02<<4), /* Event Channel 7 Output on Port D pin 7 */ - PORTCFG_EVOUT_PE7_gc = (0x03<<4), /* Event Channel 7 Output on Port E pin 7 */ -} PORTCFG_EVOUT_t; - -/* Event Output Select */ -typedef enum PORTCFG_EVOUTSEL_enum -{ - PORTCFG_EVOUTSEL_0_gc = (0x00<<0), /* Event Channel 0 output to pin */ - PORTCFG_EVOUTSEL_1_gc = (0x01<<0), /* Event Channel 1 output to pin */ - PORTCFG_EVOUTSEL_2_gc = (0x02<<0), /* Event Channel 2 output to pin */ - PORTCFG_EVOUTSEL_3_gc = (0x03<<0), /* Event Channel 3 output to pin */ -} PORTCFG_EVOUTSEL_t; - - -/* --------------------------------------------------------------------------- -CRC - Cyclic Redundancy Checker --------------------------------------------------------------------------- -*/ - -/* Cyclic Redundancy Checker */ -typedef struct CRC_struct -{ - register8_t CTRL; /* Control Register */ - register8_t STATUS; /* Status Register */ - register8_t reserved_0x02; - register8_t DATAIN; /* Data Input */ - register8_t CHECKSUM0; /* Checksum byte 0 */ - register8_t CHECKSUM1; /* Checksum byte 1 */ - register8_t CHECKSUM2; /* Checksum byte 2 */ - register8_t CHECKSUM3; /* Checksum byte 3 */ -} CRC_t; - -/* Reset */ -typedef enum CRC_RESET_enum -{ - CRC_RESET_NO_gc = (0x00<<6), /* No Reset */ - CRC_RESET_RESET0_gc = (0x02<<6), /* Reset CRC with CHECKSUM to all zeros */ - CRC_RESET_RESET1_gc = (0x03<<6), /* Reset CRC with CHECKSUM to all ones */ -} CRC_RESET_t; - -/* Input Source */ -typedef enum CRC_SOURCE_enum -{ - CRC_SOURCE_DISABLE_gc = (0x00<<0), /* Disabled */ - CRC_SOURCE_IO_gc = (0x01<<0), /* I/O Interface */ - CRC_SOURCE_FLASH_gc = (0x02<<0), /* Flash */ -} CRC_SOURCE_t; - - -/* --------------------------------------------------------------------------- -EVSYS - Event System --------------------------------------------------------------------------- -*/ - -/* Event System */ -typedef struct EVSYS_struct -{ - register8_t CH0MUX; /* Event Channel 0 Multiplexer */ - register8_t CH1MUX; /* Event Channel 1 Multiplexer */ - register8_t CH2MUX; /* Event Channel 2 Multiplexer */ - register8_t CH3MUX; /* Event Channel 3 Multiplexer */ - register8_t reserved_0x04; - register8_t reserved_0x05; - register8_t reserved_0x06; - register8_t reserved_0x07; - register8_t CH0CTRL; /* Channel 0 Control Register */ - register8_t CH1CTRL; /* Channel 1 Control Register */ - register8_t CH2CTRL; /* Channel 2 Control Register */ - register8_t CH3CTRL; /* Channel 3 Control Register */ - register8_t reserved_0x0C; - register8_t reserved_0x0D; - register8_t reserved_0x0E; - register8_t reserved_0x0F; - register8_t STROBE; /* Event Strobe */ - register8_t DATA; /* Event Data */ -} EVSYS_t; - -/* Quadrature Decoder Index Recognition Mode */ -typedef enum EVSYS_QDIRM_enum -{ - EVSYS_QDIRM_00_gc = (0x00<<5), /* QDPH0 = 0, QDPH90 = 0 */ - EVSYS_QDIRM_01_gc = (0x01<<5), /* QDPH0 = 0, QDPH90 = 1 */ - EVSYS_QDIRM_10_gc = (0x02<<5), /* QDPH0 = 1, QDPH90 = 0 */ - EVSYS_QDIRM_11_gc = (0x03<<5), /* QDPH0 = 1, QDPH90 = 1 */ -} EVSYS_QDIRM_t; - -/* Digital filter coefficient */ -typedef enum EVSYS_DIGFILT_enum -{ - EVSYS_DIGFILT_1SAMPLE_gc = (0x00<<0), /* 1 SAMPLE */ - EVSYS_DIGFILT_2SAMPLES_gc = (0x01<<0), /* 2 SAMPLES */ - EVSYS_DIGFILT_3SAMPLES_gc = (0x02<<0), /* 3 SAMPLES */ - EVSYS_DIGFILT_4SAMPLES_gc = (0x03<<0), /* 4 SAMPLES */ - EVSYS_DIGFILT_5SAMPLES_gc = (0x04<<0), /* 5 SAMPLES */ - EVSYS_DIGFILT_6SAMPLES_gc = (0x05<<0), /* 6 SAMPLES */ - EVSYS_DIGFILT_7SAMPLES_gc = (0x06<<0), /* 7 SAMPLES */ - EVSYS_DIGFILT_8SAMPLES_gc = (0x07<<0), /* 8 SAMPLES */ -} EVSYS_DIGFILT_t; - -/* Event Channel multiplexer input selection */ -typedef enum EVSYS_CHMUX_enum -{ - EVSYS_CHMUX_OFF_gc = (0x00<<0), /* Off */ - EVSYS_CHMUX_RTC_OVF_gc = (0x08<<0), /* RTC Overflow */ - EVSYS_CHMUX_RTC_CMP_gc = (0x09<<0), /* RTC Compare Match */ - EVSYS_CHMUX_USB_gc = (0x0A<<0), /* USB Setup, SOF, CRC error and UNF/OVF */ - EVSYS_CHMUX_ACA_CH0_gc = (0x10<<0), /* Analog Comparator A Channel 0 */ - EVSYS_CHMUX_ACA_CH1_gc = (0x11<<0), /* Analog Comparator A Channel 1 */ - EVSYS_CHMUX_ACA_WIN_gc = (0x12<<0), /* Analog Comparator A Window */ - EVSYS_CHMUX_ADCA_CH0_gc = (0x20<<0), /* ADC A Channel */ - EVSYS_CHMUX_PORTA_PIN0_gc = (0x50<<0), /* Port A, Pin0 */ - EVSYS_CHMUX_PORTA_PIN1_gc = (0x51<<0), /* Port A, Pin1 */ - EVSYS_CHMUX_PORTA_PIN2_gc = (0x52<<0), /* Port A, Pin2 */ - EVSYS_CHMUX_PORTA_PIN3_gc = (0x53<<0), /* Port A, Pin3 */ - EVSYS_CHMUX_PORTA_PIN4_gc = (0x54<<0), /* Port A, Pin4 */ - EVSYS_CHMUX_PORTA_PIN5_gc = (0x55<<0), /* Port A, Pin5 */ - EVSYS_CHMUX_PORTA_PIN6_gc = (0x56<<0), /* Port A, Pin6 */ - EVSYS_CHMUX_PORTA_PIN7_gc = (0x57<<0), /* Port A, Pin7 */ - EVSYS_CHMUX_PORTB_PIN0_gc = (0x58<<0), /* Port B, Pin0 */ - EVSYS_CHMUX_PORTB_PIN1_gc = (0x59<<0), /* Port B, Pin1 */ - EVSYS_CHMUX_PORTB_PIN2_gc = (0x5A<<0), /* Port B, Pin2 */ - EVSYS_CHMUX_PORTB_PIN3_gc = (0x5B<<0), /* Port B, Pin3 */ - EVSYS_CHMUX_PORTB_PIN4_gc = (0x5C<<0), /* Port B, Pin4 */ - EVSYS_CHMUX_PORTB_PIN5_gc = (0x5D<<0), /* Port B, Pin5 */ - EVSYS_CHMUX_PORTB_PIN6_gc = (0x5E<<0), /* Port B, Pin6 */ - EVSYS_CHMUX_PORTB_PIN7_gc = (0x5F<<0), /* Port B, Pin7 */ - EVSYS_CHMUX_PORTC_PIN0_gc = (0x60<<0), /* Port C, Pin0 */ - EVSYS_CHMUX_PORTC_PIN1_gc = (0x61<<0), /* Port C, Pin1 */ - EVSYS_CHMUX_PORTC_PIN2_gc = (0x62<<0), /* Port C, Pin2 */ - EVSYS_CHMUX_PORTC_PIN3_gc = (0x63<<0), /* Port C, Pin3 */ - EVSYS_CHMUX_PORTC_PIN4_gc = (0x64<<0), /* Port C, Pin4 */ - EVSYS_CHMUX_PORTC_PIN5_gc = (0x65<<0), /* Port C, Pin5 */ - EVSYS_CHMUX_PORTC_PIN6_gc = (0x66<<0), /* Port C, Pin6 */ - EVSYS_CHMUX_PORTC_PIN7_gc = (0x67<<0), /* Port C, Pin7 */ - EVSYS_CHMUX_PORTD_PIN0_gc = (0x68<<0), /* Port D, Pin0 */ - EVSYS_CHMUX_PORTD_PIN1_gc = (0x69<<0), /* Port D, Pin1 */ - EVSYS_CHMUX_PORTD_PIN2_gc = (0x6A<<0), /* Port D, Pin2 */ - EVSYS_CHMUX_PORTD_PIN3_gc = (0x6B<<0), /* Port D, Pin3 */ - EVSYS_CHMUX_PORTD_PIN4_gc = (0x6C<<0), /* Port D, Pin4 */ - EVSYS_CHMUX_PORTD_PIN5_gc = (0x6D<<0), /* Port D, Pin5 */ - EVSYS_CHMUX_PORTD_PIN6_gc = (0x6E<<0), /* Port D, Pin6 */ - EVSYS_CHMUX_PORTD_PIN7_gc = (0x6F<<0), /* Port D, Pin7 */ - EVSYS_CHMUX_PORTE_PIN0_gc = (0x70<<0), /* Port E, Pin0 */ - EVSYS_CHMUX_PORTE_PIN1_gc = (0x71<<0), /* Port E, Pin1 */ - EVSYS_CHMUX_PORTE_PIN2_gc = (0x72<<0), /* Port E, Pin2 */ - EVSYS_CHMUX_PORTE_PIN3_gc = (0x73<<0), /* Port E, Pin3 */ - EVSYS_CHMUX_PORTE_PIN4_gc = (0x74<<0), /* Port E, Pin4 */ - EVSYS_CHMUX_PORTE_PIN5_gc = (0x75<<0), /* Port E, Pin5 */ - EVSYS_CHMUX_PORTE_PIN6_gc = (0x76<<0), /* Port E, Pin6 */ - EVSYS_CHMUX_PORTE_PIN7_gc = (0x77<<0), /* Port E, Pin7 */ - EVSYS_CHMUX_PORTF_PIN0_gc = (0x78<<0), /* Port F, Pin0 */ - EVSYS_CHMUX_PORTF_PIN1_gc = (0x79<<0), /* Port F, Pin1 */ - EVSYS_CHMUX_PORTF_PIN2_gc = (0x7A<<0), /* Port F, Pin2 */ - EVSYS_CHMUX_PORTF_PIN3_gc = (0x7B<<0), /* Port F, Pin3 */ - EVSYS_CHMUX_PORTF_PIN4_gc = (0x7C<<0), /* Port F, Pin4 */ - EVSYS_CHMUX_PORTF_PIN5_gc = (0x7D<<0), /* Port F, Pin5 */ - EVSYS_CHMUX_PORTF_PIN6_gc = (0x7E<<0), /* Port F, Pin6 */ - EVSYS_CHMUX_PORTF_PIN7_gc = (0x7F<<0), /* Port F, Pin7 */ - EVSYS_CHMUX_PRESCALER_1_gc = (0x80<<0), /* Prescaler, divide by 1 */ - EVSYS_CHMUX_PRESCALER_2_gc = (0x81<<0), /* Prescaler, divide by 2 */ - EVSYS_CHMUX_PRESCALER_4_gc = (0x82<<0), /* Prescaler, divide by 4 */ - EVSYS_CHMUX_PRESCALER_8_gc = (0x83<<0), /* Prescaler, divide by 8 */ - EVSYS_CHMUX_PRESCALER_16_gc = (0x84<<0), /* Prescaler, divide by 16 */ - EVSYS_CHMUX_PRESCALER_32_gc = (0x85<<0), /* Prescaler, divide by 32 */ - EVSYS_CHMUX_PRESCALER_64_gc = (0x86<<0), /* Prescaler, divide by 64 */ - EVSYS_CHMUX_PRESCALER_128_gc = (0x87<<0), /* Prescaler, divide by 128 */ - EVSYS_CHMUX_PRESCALER_256_gc = (0x88<<0), /* Prescaler, divide by 256 */ - EVSYS_CHMUX_PRESCALER_512_gc = (0x89<<0), /* Prescaler, divide by 512 */ - EVSYS_CHMUX_PRESCALER_1024_gc = (0x8A<<0), /* Prescaler, divide by 1024 */ - EVSYS_CHMUX_PRESCALER_2048_gc = (0x8B<<0), /* Prescaler, divide by 2048 */ - EVSYS_CHMUX_PRESCALER_4096_gc = (0x8C<<0), /* Prescaler, divide by 4096 */ - EVSYS_CHMUX_PRESCALER_8192_gc = (0x8D<<0), /* Prescaler, divide by 8192 */ - EVSYS_CHMUX_PRESCALER_16384_gc = (0x8E<<0), /* Prescaler, divide by 16384 */ - EVSYS_CHMUX_PRESCALER_32768_gc = (0x8F<<0), /* Prescaler, divide by 32768 */ - EVSYS_CHMUX_TCC0_OVF_gc = (0xC0<<0), /* Timer/Counter C0 Overflow */ - EVSYS_CHMUX_TCC0_ERR_gc = (0xC1<<0), /* Timer/Counter C0 Error */ - EVSYS_CHMUX_TCC0_CCA_gc = (0xC4<<0), /* Timer/Counter C0 Compare or Capture A */ - EVSYS_CHMUX_TCC0_CCB_gc = (0xC5<<0), /* Timer/Counter C0 Compare or Capture B */ - EVSYS_CHMUX_TCC0_CCC_gc = (0xC6<<0), /* Timer/Counter C0 Compare or Capture C */ - EVSYS_CHMUX_TCC0_CCD_gc = (0xC7<<0), /* Timer/Counter C0 Compare or Capture D */ - EVSYS_CHMUX_TCC1_OVF_gc = (0xC8<<0), /* Timer/Counter C1 Overflow */ - EVSYS_CHMUX_TCC1_ERR_gc = (0xC9<<0), /* Timer/Counter C1 Error */ - EVSYS_CHMUX_TCC1_CCA_gc = (0xCC<<0), /* Timer/Counter C1 Compare or Capture A */ - EVSYS_CHMUX_TCC1_CCB_gc = (0xCD<<0), /* Timer/Counter C1 Compare or Capture B */ - EVSYS_CHMUX_TCD0_OVF_gc = (0xD0<<0), /* Timer/Counter D0 Overflow */ - EVSYS_CHMUX_TCD0_ERR_gc = (0xD1<<0), /* Timer/Counter D0 Error */ - EVSYS_CHMUX_TCD0_CCA_gc = (0xD4<<0), /* Timer/Counter D0 Compare or Capture A */ - EVSYS_CHMUX_TCD0_CCB_gc = (0xD5<<0), /* Timer/Counter D0 Compare or Capture B */ - EVSYS_CHMUX_TCD0_CCC_gc = (0xD6<<0), /* Timer/Counter D0 Compare or Capture C */ - EVSYS_CHMUX_TCD0_CCD_gc = (0xD7<<0), /* Timer/Counter D0 Compare or Capture D */ - EVSYS_CHMUX_TCE0_OVF_gc = (0xE0<<0), /* Timer/Counter E0 Overflow */ - EVSYS_CHMUX_TCE0_ERR_gc = (0xE1<<0), /* Timer/Counter E0 Error */ - EVSYS_CHMUX_TCE0_CCA_gc = (0xE4<<0), /* Timer/Counter E0 Compare or Capture A */ - EVSYS_CHMUX_TCE0_CCB_gc = (0xE5<<0), /* Timer/Counter E0 Compare or Capture B */ - EVSYS_CHMUX_TCE0_CCC_gc = (0xE6<<0), /* Timer/Counter E0 Compare or Capture C */ - EVSYS_CHMUX_TCE0_CCD_gc = (0xE7<<0), /* Timer/Counter E0 Compare or Capture D */ - EVSYS_CHMUX_TCF0_OVF_gc = (0xF0<<0), /* Timer/Counter F0 Overflow */ - EVSYS_CHMUX_TCF0_ERR_gc = (0xF1<<0), /* Timer/Counter F0 Error */ - EVSYS_CHMUX_TCF0_CCA_gc = (0xF4<<0), /* Timer/Counter F0 Compare or Capture A */ - EVSYS_CHMUX_TCF0_CCB_gc = (0xF5<<0), /* Timer/Counter F0 Compare or Capture B */ - EVSYS_CHMUX_TCF0_CCC_gc = (0xF6<<0), /* Timer/Counter F0 Compare or Capture C */ - EVSYS_CHMUX_TCF0_CCD_gc = (0xF7<<0), /* Timer/Counter F0 Compare or Capture D */ -} EVSYS_CHMUX_t; - - -/* --------------------------------------------------------------------------- -NVM - Non Volatile Memory Controller --------------------------------------------------------------------------- -*/ - -/* Non-volatile Memory Controller */ -typedef struct NVM_struct -{ - register8_t ADDR0; /* Address Register 0 */ - register8_t ADDR1; /* Address Register 1 */ - register8_t ADDR2; /* Address Register 2 */ - register8_t reserved_0x03; - register8_t DATA0; /* Data Register 0 */ - register8_t DATA1; /* Data Register 1 */ - register8_t DATA2; /* Data Register 2 */ - register8_t reserved_0x07; - register8_t reserved_0x08; - register8_t reserved_0x09; - register8_t CMD; /* Command */ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t INTCTRL; /* Interrupt Control */ - register8_t reserved_0x0E; - register8_t STATUS; /* Status */ - register8_t LOCK_BITS; /* Lock Bits (Changed from LOCKBITS to avoid avr-libc collision) */ -} NVM_t; - -/* NVM Command */ -typedef enum NVM_CMD_enum -{ - NVM_CMD_NO_OPERATION_gc = (0x00<<0), /* Noop/Ordinary LPM */ - NVM_CMD_READ_USER_SIG_ROW_gc = (0x01<<0), /* Read user signature row */ - NVM_CMD_READ_CALIB_ROW_gc = (0x02<<0), /* Read calibration row */ - NVM_CMD_READ_EEPROM_gc = (0x06<<0), /* Read EEPROM */ - NVM_CMD_READ_FUSES_gc = (0x07<<0), /* Read fuse byte */ - NVM_CMD_WRITE_LOCK_BITS_gc = (0x08<<0), /* Write lock bits */ - NVM_CMD_ERASE_USER_SIG_ROW_gc = (0x18<<0), /* Erase user signature row */ - NVM_CMD_WRITE_USER_SIG_ROW_gc = (0x1A<<0), /* Write user signature row */ - NVM_CMD_ERASE_APP_gc = (0x20<<0), /* Erase Application Section */ - NVM_CMD_ERASE_APP_PAGE_gc = (0x22<<0), /* Erase Application Section page */ - NVM_CMD_LOAD_FLASH_BUFFER_gc = (0x23<<0), /* Load Flash page buffer */ - NVM_CMD_WRITE_APP_PAGE_gc = (0x24<<0), /* Write Application Section page */ - NVM_CMD_ERASE_WRITE_APP_PAGE_gc = (0x25<<0), /* Erase-and-write Application Section page */ - NVM_CMD_ERASE_FLASH_BUFFER_gc = (0x26<<0), /* Erase/flush Flash page buffer */ - NVM_CMD_ERASE_BOOT_PAGE_gc = (0x2A<<0), /* Erase Boot Section page */ - NVM_CMD_ERASE_FLASH_PAGE_gc = (0x2B<<0), /* Erase Flash Page */ - NVM_CMD_WRITE_BOOT_PAGE_gc = (0x2C<<0), /* Write Boot Section page */ - NVM_CMD_ERASE_WRITE_BOOT_PAGE_gc = (0x2D<<0), /* Erase-and-write Boot Section page */ - NVM_CMD_WRITE_FLASH_PAGE_gc = (0x2E<<0), /* Write Flash Page */ - NVM_CMD_ERASE_WRITE_FLASH_PAGE_gc = (0x2F<<0), /* Erase-and-write Flash Page */ - NVM_CMD_ERASE_EEPROM_gc = (0x30<<0), /* Erase EEPROM */ - NVM_CMD_ERASE_EEPROM_PAGE_gc = (0x32<<0), /* Erase EEPROM page */ - NVM_CMD_LOAD_EEPROM_BUFFER_gc = (0x33<<0), /* Load EEPROM page buffer */ - NVM_CMD_WRITE_EEPROM_PAGE_gc = (0x34<<0), /* Write EEPROM page */ - NVM_CMD_ERASE_WRITE_EEPROM_PAGE_gc = (0x35<<0), /* Erase-and-write EEPROM page */ - NVM_CMD_ERASE_EEPROM_BUFFER_gc = (0x36<<0), /* Erase/flush EEPROM page buffer */ - NVM_CMD_APP_CRC_gc = (0x38<<0), /* Application section CRC */ - NVM_CMD_BOOT_CRC_gc = (0x39<<0), /* Boot Section CRC */ - NVM_CMD_FLASH_RANGE_CRC_gc = (0x3A<<0), /* Flash Range CRC */ - NVM_CMD_CHIP_ERASE_gc = (0x40<<0), /* Erase Chip */ - NVM_CMD_READ_NVM_gc = (0x43<<0), /* Read NVM */ - NVM_CMD_WRITE_FUSE_gc = (0x4C<<0), /* Write Fuse byte */ - NVM_CMD_ERASE_BOOT_gc = (0x68<<0), /* Erase Boot Section */ - NVM_CMD_FLASH_CRC_gc = (0x78<<0), /* Flash CRC */ -} NVM_CMD_t; - -/* SPM ready interrupt level */ -typedef enum NVM_SPMLVL_enum -{ - NVM_SPMLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ - NVM_SPMLVL_LO_gc = (0x01<<2), /* Low level */ - NVM_SPMLVL_MED_gc = (0x02<<2), /* Medium level */ - NVM_SPMLVL_HI_gc = (0x03<<2), /* High level */ -} NVM_SPMLVL_t; - -/* EEPROM ready interrupt level */ -typedef enum NVM_EELVL_enum -{ - NVM_EELVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ - NVM_EELVL_LO_gc = (0x01<<0), /* Low level */ - NVM_EELVL_MED_gc = (0x02<<0), /* Medium level */ - NVM_EELVL_HI_gc = (0x03<<0), /* High level */ -} NVM_EELVL_t; - -/* Boot lock bits - boot setcion */ -typedef enum NVM_BLBB_enum -{ - NVM_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ - NVM_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ - NVM_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ - NVM_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ -} NVM_BLBB_t; - -/* Boot lock bits - application section */ -typedef enum NVM_BLBA_enum -{ - NVM_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ - NVM_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ - NVM_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ - NVM_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ -} NVM_BLBA_t; - -/* Boot lock bits - application table section */ -typedef enum NVM_BLBAT_enum -{ - NVM_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ - NVM_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ - NVM_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ - NVM_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ -} NVM_BLBAT_t; - -/* Lock bits */ -typedef enum NVM_LB_enum -{ - NVM_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ - NVM_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ - NVM_LB_NOLOCK_gc = (0x03<<0), /* No locks */ -} NVM_LB_t; - - -/* --------------------------------------------------------------------------- -ADC - Analog/Digital Converter --------------------------------------------------------------------------- -*/ - -/* ADC Channel */ -typedef struct ADC_CH_struct -{ - register8_t CTRL; /* Control Register */ - register8_t MUXCTRL; /* MUX Control */ - register8_t INTCTRL; /* Channel Interrupt Control Register */ - register8_t INTFLAGS; /* Interrupt Flags */ - _WORDREGISTER(RES); /* Channel Result */ - register8_t SCAN; /* Input Channel Scan */ - register8_t reserved_0x07; -} ADC_CH_t; - - -/* Analog-to-Digital Converter */ -typedef struct ADC_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t REFCTRL; /* Reference Control */ - register8_t EVCTRL; /* Event Control */ - register8_t PRESCALER; /* Clock Prescaler */ - register8_t reserved_0x05; - register8_t INTFLAGS; /* Interrupt Flags */ - register8_t TEMP; /* Temporary Register */ - register8_t reserved_0x08; - register8_t reserved_0x09; - register8_t reserved_0x0A; - register8_t reserved_0x0B; - _WORDREGISTER(CAL); /* Calibration Value */ - register8_t reserved_0x0E; - register8_t reserved_0x0F; - _WORDREGISTER(CH0RES); /* Channel 0 Result */ - register8_t reserved_0x12; - register8_t reserved_0x13; - register8_t reserved_0x14; - register8_t reserved_0x15; - register8_t reserved_0x16; - register8_t reserved_0x17; - _WORDREGISTER(CMP); /* Compare Value */ - register8_t reserved_0x1A; - register8_t reserved_0x1B; - register8_t reserved_0x1C; - register8_t reserved_0x1D; - register8_t reserved_0x1E; - register8_t reserved_0x1F; - ADC_CH_t CH0; /* ADC Channel 0 */ -} ADC_t; - -/* Current Limitation */ -typedef enum ADC_CURRLIMIT_enum -{ - ADC_CURRLIMIT_NO_gc = (0x00<<5), /* No current limit, 300ksps max sampling rate */ - ADC_CURRLIMIT_LOW_gc = (0x01<<5), /* Low current limit, 250ksps max sampling rate */ - ADC_CURRLIMIT_MED_gc = (0x02<<5), /* Medium current limit, 150ksps max sampling rate */ - ADC_CURRLIMIT_HIGH_gc = (0x03<<5), /* High current limit, 50ksps max sampling rate */ -} ADC_CURRLIMIT_t; - -/* Positive input multiplexer selection */ -typedef enum ADC_CH_MUXPOS_enum -{ - ADC_CH_MUXPOS_PIN0_gc = (0x00<<3), /* Input pin 0 */ - ADC_CH_MUXPOS_PIN1_gc = (0x01<<3), /* Input pin 1 */ - ADC_CH_MUXPOS_PIN2_gc = (0x02<<3), /* Input pin 2 */ - ADC_CH_MUXPOS_PIN3_gc = (0x03<<3), /* Input pin 3 */ - ADC_CH_MUXPOS_PIN4_gc = (0x04<<3), /* Input pin 4 */ - ADC_CH_MUXPOS_PIN5_gc = (0x05<<3), /* Input pin 5 */ - ADC_CH_MUXPOS_PIN6_gc = (0x06<<3), /* Input pin 6 */ - ADC_CH_MUXPOS_PIN7_gc = (0x07<<3), /* Input pin 7 */ - ADC_CH_MUXPOS_PIN8_gc = (0x08<<3), /* Input pin 8 */ - ADC_CH_MUXPOS_PIN9_gc = (0x09<<3), /* Input pin 9 */ - ADC_CH_MUXPOS_PIN10_gc = (0x0A<<3), /* Input pin 10 */ - ADC_CH_MUXPOS_PIN11_gc = (0x0B<<3), /* Input pin 11 */ - ADC_CH_MUXPOS_PIN12_gc = (0x0C<<3), /* Input pin 12 */ - ADC_CH_MUXPOS_PIN13_gc = (0x0D<<3), /* Input pin 13 */ - ADC_CH_MUXPOS_PIN14_gc = (0x0E<<3), /* Input pin 14 */ - ADC_CH_MUXPOS_PIN15_gc = (0x0F<<3), /* Input pin 15 */ -} ADC_CH_MUXPOS_t; - -/* Internal input multiplexer selections */ -typedef enum ADC_CH_MUXINT_enum -{ - ADC_CH_MUXINT_TEMP_gc = (0x00<<3), /* Temperature Reference */ - ADC_CH_MUXINT_BANDGAP_gc = (0x01<<3), /* Bandgap Reference */ - ADC_CH_MUXINT_SCALEDVCC_gc = (0x02<<3), /* 1/10 scaled VCC */ -} ADC_CH_MUXINT_t; - -/* Negative input multiplexer selection */ -typedef enum ADC_CH_MUXNEG_enum -{ - ADC_CH_MUXNEG_PIN0_gc = (0x00<<0), /* Input pin 0 */ - ADC_CH_MUXNEG_PIN1_gc = (0x01<<0), /* Input pin 1 */ - ADC_CH_MUXNEG_PIN2_gc = (0x02<<0), /* Input pin 2 */ - ADC_CH_MUXNEG_PIN3_gc = (0x03<<0), /* Input pin 3 */ - ADC_CH_MUXNEG_PIN4_gc = (0x00<<0), /* Input pin 4 */ - ADC_CH_MUXNEG_PIN5_gc = (0x01<<0), /* Input pin 5 */ - ADC_CH_MUXNEG_PIN6_gc = (0x02<<0), /* Input pin 6 */ - ADC_CH_MUXNEG_PIN7_gc = (0x03<<0), /* Input pin 7 */ -} ADC_CH_MUXNEG_t; - -/* Input mode */ -typedef enum ADC_CH_INPUTMODE_enum -{ - ADC_CH_INPUTMODE_INTERNAL_gc = (0x00<<0), /* Internal inputs, no gain */ - ADC_CH_INPUTMODE_SINGLEENDED_gc = (0x01<<0), /* Single-ended input, no gain */ - ADC_CH_INPUTMODE_DIFF_gc = (0x02<<0), /* Differential input, no gain */ - ADC_CH_INPUTMODE_DIFFWGAIN_gc = (0x03<<0), /* Differential input, with gain */ -} ADC_CH_INPUTMODE_t; - -/* Gain factor */ -typedef enum ADC_CH_GAIN_enum -{ - ADC_CH_GAIN_1X_gc = (0x00<<2), /* 1x gain */ - ADC_CH_GAIN_2X_gc = (0x01<<2), /* 2x gain */ - ADC_CH_GAIN_4X_gc = (0x02<<2), /* 4x gain */ - ADC_CH_GAIN_8X_gc = (0x03<<2), /* 8x gain */ - ADC_CH_GAIN_16X_gc = (0x04<<2), /* 16x gain */ - ADC_CH_GAIN_32X_gc = (0x05<<2), /* 32x gain */ - ADC_CH_GAIN_64X_gc = (0x06<<2), /* 64x gain */ - ADC_CH_GAIN_DIV2_gc = (0x07<<2), /* x/2 gain */ -} ADC_CH_GAIN_t; - -/* Conversion result resolution */ -typedef enum ADC_RESOLUTION_enum -{ - ADC_RESOLUTION_12BIT_gc = (0x00<<1), /* 12-bit right-adjusted result */ - ADC_RESOLUTION_8BIT_gc = (0x02<<1), /* 8-bit right-adjusted result */ - ADC_RESOLUTION_LEFT12BIT_gc = (0x03<<1), /* 12-bit left-adjusted result */ -} ADC_RESOLUTION_t; - -/* Voltage reference selection */ -typedef enum ADC_REFSEL_enum -{ - ADC_REFSEL_INT1V_gc = (0x00<<4), /* Internal 1V */ - ADC_REFSEL_INTVCC_gc = (0x01<<4), /* Internal VCC / 1.6 */ - ADC_REFSEL_AREFA_gc = (0x02<<4), /* External reference on PORT A */ - ADC_REFSEL_AREFB_gc = (0x03<<4), /* External reference on PORT B */ - ADC_REFSEL_INTVCC2_gc = (0x04<<4), /* Internal VCC / 2 */ -} ADC_REFSEL_t; - -/* Event channel input selection */ -typedef enum ADC_EVSEL_enum -{ - ADC_EVSEL_0_gc = (0x00<<3), /* Event Channel 0 */ - ADC_EVSEL_1_gc = (0x01<<3), /* Event Channel 1 */ - ADC_EVSEL_2_gc = (0x02<<3), /* Event Channel 2 */ - ADC_EVSEL_3_gc = (0x03<<3), /* Event Channel 3 */ -} ADC_EVSEL_t; - -/* Event action selection */ -typedef enum ADC_EVACT_enum -{ - ADC_EVACT_NONE_gc = (0x00<<0), /* No event action */ - ADC_EVACT_CH0_gc = (0x01<<0), /* First event triggers channel 0 */ - ADC_EVACT_SYNCSWEEP_gc = (0x06<<0), /* The ADC is flushed and restarted for accurate timing */ -} ADC_EVACT_t; - -/* Interupt mode */ -typedef enum ADC_CH_INTMODE_enum -{ - ADC_CH_INTMODE_COMPLETE_gc = (0x00<<2), /* Interrupt on conversion complete */ - ADC_CH_INTMODE_BELOW_gc = (0x01<<2), /* Interrupt on result below compare value */ - ADC_CH_INTMODE_ABOVE_gc = (0x03<<2), /* Interrupt on result above compare value */ -} ADC_CH_INTMODE_t; - -/* Interrupt level */ -typedef enum ADC_CH_INTLVL_enum -{ - ADC_CH_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ - ADC_CH_INTLVL_LO_gc = (0x01<<0), /* Low level */ - ADC_CH_INTLVL_MED_gc = (0x02<<0), /* Medium level */ - ADC_CH_INTLVL_HI_gc = (0x03<<0), /* High level */ -} ADC_CH_INTLVL_t; - -/* Clock prescaler */ -typedef enum ADC_PRESCALER_enum -{ - ADC_PRESCALER_DIV4_gc = (0x00<<0), /* Divide clock by 4 */ - ADC_PRESCALER_DIV8_gc = (0x01<<0), /* Divide clock by 8 */ - ADC_PRESCALER_DIV16_gc = (0x02<<0), /* Divide clock by 16 */ - ADC_PRESCALER_DIV32_gc = (0x03<<0), /* Divide clock by 32 */ - ADC_PRESCALER_DIV64_gc = (0x04<<0), /* Divide clock by 64 */ - ADC_PRESCALER_DIV128_gc = (0x05<<0), /* Divide clock by 128 */ - ADC_PRESCALER_DIV256_gc = (0x06<<0), /* Divide clock by 256 */ - ADC_PRESCALER_DIV512_gc = (0x07<<0), /* Divide clock by 512 */ -} ADC_PRESCALER_t; - - -/* --------------------------------------------------------------------------- -AC - Analog Comparator --------------------------------------------------------------------------- -*/ - -/* Analog Comparator */ -typedef struct AC_struct -{ - register8_t AC0CTRL; /* Analog Comparator 0 Control */ - register8_t AC1CTRL; /* Analog Comparator 1 Control */ - register8_t AC0MUXCTRL; /* Analog Comparator 0 MUX Control */ - register8_t AC1MUXCTRL; /* Analog Comparator 1 MUX Control */ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t WINCTRL; /* Window Mode Control */ - register8_t STATUS; /* Status */ -} AC_t; - -/* Interrupt mode */ -typedef enum AC_INTMODE_enum -{ - AC_INTMODE_BOTHEDGES_gc = (0x00<<6), /* Interrupt on both edges */ - AC_INTMODE_FALLING_gc = (0x02<<6), /* Interrupt on falling edge */ - AC_INTMODE_RISING_gc = (0x03<<6), /* Interrupt on rising edge */ -} AC_INTMODE_t; - -/* Interrupt level */ -typedef enum AC_INTLVL_enum -{ - AC_INTLVL_OFF_gc = (0x00<<4), /* Interrupt disabled */ - AC_INTLVL_LO_gc = (0x01<<4), /* Low level */ - AC_INTLVL_MED_gc = (0x02<<4), /* Medium level */ - AC_INTLVL_HI_gc = (0x03<<4), /* High level */ -} AC_INTLVL_t; - -/* Hysteresis mode selection */ -typedef enum AC_HYSMODE_enum -{ - AC_HYSMODE_NO_gc = (0x00<<1), /* No hysteresis */ - AC_HYSMODE_SMALL_gc = (0x01<<1), /* Small hysteresis */ - AC_HYSMODE_LARGE_gc = (0x02<<1), /* Large hysteresis */ -} AC_HYSMODE_t; - -/* Positive input multiplexer selection */ -typedef enum AC_MUXPOS_enum -{ - AC_MUXPOS_PIN0_gc = (0x00<<3), /* Pin 0 */ - AC_MUXPOS_PIN1_gc = (0x01<<3), /* Pin 1 */ - AC_MUXPOS_PIN2_gc = (0x02<<3), /* Pin 2 */ - AC_MUXPOS_PIN3_gc = (0x03<<3), /* Pin 3 */ - AC_MUXPOS_PIN4_gc = (0x04<<3), /* Pin 4 */ - AC_MUXPOS_PIN5_gc = (0x05<<3), /* Pin 5 */ - AC_MUXPOS_PIN6_gc = (0x06<<3), /* Pin 6 */ -} AC_MUXPOS_t; - -/* Negative input multiplexer selection */ -typedef enum AC_MUXNEG_enum -{ - AC_MUXNEG_PIN0_gc = (0x00<<0), /* Pin 0 */ - AC_MUXNEG_PIN1_gc = (0x01<<0), /* Pin 1 */ - AC_MUXNEG_PIN3_gc = (0x02<<0), /* Pin 3 */ - AC_MUXNEG_PIN5_gc = (0x03<<0), /* Pin 5 */ - AC_MUXNEG_PIN7_gc = (0x04<<0), /* Pin 7 */ - AC_MUXNEG_BANDGAP_gc = (0x06<<0), /* Bandgap Reference */ - AC_MUXNEG_SCALER_gc = (0x07<<0), /* Internal voltage scaler */ -} AC_MUXNEG_t; - -/* Windows interrupt mode */ -typedef enum AC_WINTMODE_enum -{ - AC_WINTMODE_ABOVE_gc = (0x00<<2), /* Interrupt on above window */ - AC_WINTMODE_INSIDE_gc = (0x01<<2), /* Interrupt on inside window */ - AC_WINTMODE_BELOW_gc = (0x02<<2), /* Interrupt on below window */ - AC_WINTMODE_OUTSIDE_gc = (0x03<<2), /* Interrupt on outside window */ -} AC_WINTMODE_t; - -/* Window interrupt level */ -typedef enum AC_WINTLVL_enum -{ - AC_WINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ - AC_WINTLVL_LO_gc = (0x01<<0), /* Low priority */ - AC_WINTLVL_MED_gc = (0x02<<0), /* Medium priority */ - AC_WINTLVL_HI_gc = (0x03<<0), /* High priority */ -} AC_WINTLVL_t; - -/* Window mode state */ -typedef enum AC_WSTATE_enum -{ - AC_WSTATE_ABOVE_gc = (0x00<<6), /* Signal above window */ - AC_WSTATE_INSIDE_gc = (0x01<<6), /* Signal inside window */ - AC_WSTATE_BELOW_gc = (0x02<<6), /* Signal below window */ -} AC_WSTATE_t; - - -/* --------------------------------------------------------------------------- -RTC - Real-Time Counter --------------------------------------------------------------------------- -*/ - -/* Real-Time Counter */ -typedef struct RTC_struct -{ - register8_t CTRL; /* Control Register */ - register8_t STATUS; /* Status Register */ - register8_t INTCTRL; /* Interrupt Control Register */ - register8_t INTFLAGS; /* Interrupt Flags */ - register8_t TEMP; /* Temporary register */ - register8_t reserved_0x05; - register8_t reserved_0x06; - register8_t reserved_0x07; - _WORDREGISTER(CNT); /* Count Register */ - _WORDREGISTER(PER); /* Period Register */ - _WORDREGISTER(COMP); /* Compare Register */ -} RTC_t; - -/* Prescaler Factor */ -typedef enum RTC_PRESCALER_enum -{ - RTC_PRESCALER_OFF_gc = (0x00<<0), /* RTC Off */ - RTC_PRESCALER_DIV1_gc = (0x01<<0), /* RTC Clock */ - RTC_PRESCALER_DIV2_gc = (0x02<<0), /* RTC Clock / 2 */ - RTC_PRESCALER_DIV8_gc = (0x03<<0), /* RTC Clock / 8 */ - RTC_PRESCALER_DIV16_gc = (0x04<<0), /* RTC Clock / 16 */ - RTC_PRESCALER_DIV64_gc = (0x05<<0), /* RTC Clock / 64 */ - RTC_PRESCALER_DIV256_gc = (0x06<<0), /* RTC Clock / 256 */ - RTC_PRESCALER_DIV1024_gc = (0x07<<0), /* RTC Clock / 1024 */ -} RTC_PRESCALER_t; - -/* Compare Interrupt level */ -typedef enum RTC_COMPINTLVL_enum -{ - RTC_COMPINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ - RTC_COMPINTLVL_LO_gc = (0x01<<2), /* Low Level */ - RTC_COMPINTLVL_MED_gc = (0x02<<2), /* Medium Level */ - RTC_COMPINTLVL_HI_gc = (0x03<<2), /* High Level */ -} RTC_COMPINTLVL_t; - -/* Overflow Interrupt level */ -typedef enum RTC_OVFINTLVL_enum -{ - RTC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - RTC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ - RTC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ - RTC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ -} RTC_OVFINTLVL_t; - - -/* --------------------------------------------------------------------------- -TWI - Two-Wire Interface --------------------------------------------------------------------------- -*/ - -/* */ -typedef struct TWI_MASTER_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t CTRLC; /* Control Register C */ - register8_t STATUS; /* Status Register */ - register8_t BAUD; /* Baurd Rate Control Register */ - register8_t ADDR; /* Address Register */ - register8_t DATA; /* Data Register */ -} TWI_MASTER_t; - - -/* */ -typedef struct TWI_SLAVE_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t STATUS; /* Status Register */ - register8_t ADDR; /* Address Register */ - register8_t DATA; /* Data Register */ - register8_t ADDRMASK; /* Address Mask Register */ -} TWI_SLAVE_t; - - -/* Two-Wire Interface */ -typedef struct TWI_struct -{ - register8_t CTRL; /* TWI Common Control Register */ - TWI_MASTER_t MASTER; /* TWI master module */ - TWI_SLAVE_t SLAVE; /* TWI slave module */ -} TWI_t; - -/* SDA Hold Time */ -typedef enum TWI_SDAHOLD_enum -{ - TWI_SDAHOLD_OFF_gc = (0x00<<1), /* SDA Hold Time off */ - TWI_SDAHOLD_50NS_gc = (0x01<<1), /* SDA Hold Time 50 ns */ - TWI_SDAHOLD_300NS_gc = (0x02<<1), /* SDA Hold Time 300 ns */ - TWI_SDAHOLD_400NS_gc = (0x03<<1), /* SDA Hold Time 400 ns */ -} TWI_SDAHOLD_t; - -/* Master Interrupt Level */ -typedef enum TWI_MASTER_INTLVL_enum -{ - TWI_MASTER_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ - TWI_MASTER_INTLVL_LO_gc = (0x01<<6), /* Low Level */ - TWI_MASTER_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ - TWI_MASTER_INTLVL_HI_gc = (0x03<<6), /* High Level */ -} TWI_MASTER_INTLVL_t; - -/* Inactive Timeout */ -typedef enum TWI_MASTER_TIMEOUT_enum -{ - TWI_MASTER_TIMEOUT_DISABLED_gc = (0x00<<2), /* Bus Timeout Disabled */ - TWI_MASTER_TIMEOUT_50US_gc = (0x01<<2), /* 50 Microseconds */ - TWI_MASTER_TIMEOUT_100US_gc = (0x02<<2), /* 100 Microseconds */ - TWI_MASTER_TIMEOUT_200US_gc = (0x03<<2), /* 200 Microseconds */ -} TWI_MASTER_TIMEOUT_t; - -/* Master Command */ -typedef enum TWI_MASTER_CMD_enum -{ - TWI_MASTER_CMD_NOACT_gc = (0x00<<0), /* No Action */ - TWI_MASTER_CMD_REPSTART_gc = (0x01<<0), /* Issue Repeated Start Condition */ - TWI_MASTER_CMD_RECVTRANS_gc = (0x02<<0), /* Receive or Transmit Data */ - TWI_MASTER_CMD_STOP_gc = (0x03<<0), /* Issue Stop Condition */ -} TWI_MASTER_CMD_t; - -/* Master Bus State */ -typedef enum TWI_MASTER_BUSSTATE_enum -{ - TWI_MASTER_BUSSTATE_UNKNOWN_gc = (0x00<<0), /* Unknown Bus State */ - TWI_MASTER_BUSSTATE_IDLE_gc = (0x01<<0), /* Bus is Idle */ - TWI_MASTER_BUSSTATE_OWNER_gc = (0x02<<0), /* This Module Controls The Bus */ - TWI_MASTER_BUSSTATE_BUSY_gc = (0x03<<0), /* The Bus is Busy */ -} TWI_MASTER_BUSSTATE_t; - -/* Slave Interrupt Level */ -typedef enum TWI_SLAVE_INTLVL_enum -{ - TWI_SLAVE_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ - TWI_SLAVE_INTLVL_LO_gc = (0x01<<6), /* Low Level */ - TWI_SLAVE_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ - TWI_SLAVE_INTLVL_HI_gc = (0x03<<6), /* High Level */ -} TWI_SLAVE_INTLVL_t; - -/* Slave Command */ -typedef enum TWI_SLAVE_CMD_enum -{ - TWI_SLAVE_CMD_NOACT_gc = (0x00<<0), /* No Action */ - TWI_SLAVE_CMD_COMPTRANS_gc = (0x02<<0), /* Used To Complete a Transaction */ - TWI_SLAVE_CMD_RESPONSE_gc = (0x03<<0), /* Used in Response to Address/Data Interrupt */ -} TWI_SLAVE_CMD_t; - - -/* --------------------------------------------------------------------------- -USB - USB --------------------------------------------------------------------------- -*/ - -/* USB Endpoint */ -typedef struct USB_EP_struct -{ - register8_t STATUS; /* Endpoint Status */ - register8_t CTRL; /* Endpoint Control */ - _WORDREGISTER(CNT); /* USB Endpoint Counter */ - _WORDREGISTER(DATAPTR); /* Data Pointer */ - _WORDREGISTER(AUXDATA); /* Auxiliary Data */ -} USB_EP_t; - - -/* Universal Serial Bus */ -typedef struct USB_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t STATUS; /* Status Register */ - register8_t ADDR; /* Address Register */ - register8_t FIFOWP; /* FIFO Write Pointer Register */ - register8_t FIFORP; /* FIFO Read Pointer Register */ - _WORDREGISTER(EPPTR); /* Endpoint Configuration Table Pointer */ - register8_t INTCTRLA; /* Interrupt Control Register A */ - register8_t INTCTRLB; /* Interrupt Control Register B */ - register8_t INTFLAGSACLR; /* Clear Interrupt Flag Register A */ - register8_t INTFLAGSASET; /* Set Interrupt Flag Register A */ - register8_t INTFLAGSBCLR; /* Clear Interrupt Flag Register B */ - register8_t INTFLAGSBSET; /* Set Interrupt Flag Register B */ - register8_t reserved_0x0E; - register8_t reserved_0x0F; - register8_t reserved_0x10; - register8_t reserved_0x11; - register8_t reserved_0x12; - register8_t reserved_0x13; - register8_t reserved_0x14; - register8_t reserved_0x15; - register8_t reserved_0x16; - register8_t reserved_0x17; - register8_t reserved_0x18; - register8_t reserved_0x19; - register8_t reserved_0x1A; - register8_t reserved_0x1B; - register8_t reserved_0x1C; - register8_t reserved_0x1D; - register8_t reserved_0x1E; - register8_t reserved_0x1F; - register8_t reserved_0x20; - register8_t reserved_0x21; - register8_t reserved_0x22; - register8_t reserved_0x23; - register8_t reserved_0x24; - register8_t reserved_0x25; - register8_t reserved_0x26; - register8_t reserved_0x27; - register8_t reserved_0x28; - register8_t reserved_0x29; - register8_t reserved_0x2A; - register8_t reserved_0x2B; - register8_t reserved_0x2C; - register8_t reserved_0x2D; - register8_t reserved_0x2E; - register8_t reserved_0x2F; - register8_t reserved_0x30; - register8_t reserved_0x31; - register8_t reserved_0x32; - register8_t reserved_0x33; - register8_t reserved_0x34; - register8_t reserved_0x35; - register8_t reserved_0x36; - register8_t reserved_0x37; - register8_t reserved_0x38; - register8_t reserved_0x39; - register8_t CAL0; /* Calibration Byte 0 */ - register8_t CAL1; /* Calibration Byte 1 */ -} USB_t; - - -/* USB Endpoint Table */ -typedef struct USB_EP_TABLE_struct -{ - USB_EP_t EP0OUT; /* Endpoint 0 */ - USB_EP_t EP0IN; /* Endpoint 0 */ - USB_EP_t EP1OUT; /* Endpoint 1 */ - USB_EP_t EP1IN; /* Endpoint 1 */ - USB_EP_t EP2OUT; /* Endpoint 2 */ - USB_EP_t EP2IN; /* Endpoint 2 */ - USB_EP_t EP3OUT; /* Endpoint 3 */ - USB_EP_t EP3IN; /* Endpoint 3 */ - USB_EP_t EP4OUT; /* Endpoint 4 */ - USB_EP_t EP4IN; /* Endpoint 4 */ - USB_EP_t EP5OUT; /* Endpoint 5 */ - USB_EP_t EP5IN; /* Endpoint 5 */ - USB_EP_t EP6OUT; /* Endpoint 6 */ - USB_EP_t EP6IN; /* Endpoint 6 */ - USB_EP_t EP7OUT; /* Endpoint 7 */ - USB_EP_t EP7IN; /* Endpoint 7 */ - USB_EP_t EP8OUT; /* Endpoint 8 */ - USB_EP_t EP8IN; /* Endpoint 8 */ - USB_EP_t EP9OUT; /* Endpoint 9 */ - USB_EP_t EP9IN; /* Endpoint 9 */ - USB_EP_t EP10OUT; /* Endpoint 10 */ - USB_EP_t EP10IN; /* Endpoint 10 */ - USB_EP_t EP11OUT; /* Endpoint 11 */ - USB_EP_t EP11IN; /* Endpoint 11 */ - USB_EP_t EP12OUT; /* Endpoint 12 */ - USB_EP_t EP12IN; /* Endpoint 12 */ - USB_EP_t EP13OUT; /* Endpoint 13 */ - USB_EP_t EP13IN; /* Endpoint 13 */ - USB_EP_t EP14OUT; /* Endpoint 14 */ - USB_EP_t EP14IN; /* Endpoint 14 */ - USB_EP_t EP15OUT; /* Endpoint 15 */ - USB_EP_t EP15IN; /* Endpoint 15 */ - register8_t reserved_0x100; - register8_t reserved_0x101; - register8_t reserved_0x102; - register8_t reserved_0x103; - register8_t reserved_0x104; - register8_t reserved_0x105; - register8_t reserved_0x106; - register8_t reserved_0x107; - register8_t reserved_0x108; - register8_t reserved_0x109; - register8_t reserved_0x10A; - register8_t reserved_0x10B; - register8_t reserved_0x10C; - register8_t reserved_0x10D; - register8_t reserved_0x10E; - register8_t reserved_0x10F; - register8_t FRAMENUML; /* Frame Number Low Byte */ - register8_t FRAMENUMH; /* Frame Number High Byte */ -} USB_EP_TABLE_t; - -/* Interrupt level */ -typedef enum USB_INTLVL_enum -{ - USB_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ - USB_INTLVL_LO_gc = (0x01<<0), /* Low level */ - USB_INTLVL_MED_gc = (0x02<<0), /* Medium level */ - USB_INTLVL_HI_gc = (0x03<<0), /* High level */ -} USB_INTLVL_t; - -/* USB Endpoint Type */ -typedef enum USB_EP_TYPE_enum -{ - USB_EP_TYPE_DISABLE_gc = (0x00<<6), /* Endpoint Disabled */ - USB_EP_TYPE_CONTROL_gc = (0x01<<6), /* Control */ - USB_EP_TYPE_BULK_gc = (0x02<<6), /* Bulk/Interrupt */ - USB_EP_TYPE_ISOCHRONOUS_gc = (0x03<<6), /* Isochronous */ -} USB_EP_TYPE_t; - -/* USB Endpoint Buffersize */ -typedef enum USB_EP_BUFSIZE_enum -{ - USB_EP_BUFSIZE_8_gc = (0x00<<0), /* 8 bytes buffer size */ - USB_EP_BUFSIZE_16_gc = (0x01<<0), /* 16 bytes buffer size */ - USB_EP_BUFSIZE_32_gc = (0x02<<0), /* 32 bytes buffer size */ - USB_EP_BUFSIZE_64_gc = (0x03<<0), /* 64 bytes buffer size */ - USB_EP_BUFSIZE_128_gc = (0x04<<0), /* 128 bytes buffer size */ - USB_EP_BUFSIZE_256_gc = (0x05<<0), /* 256 bytes buffer size */ - USB_EP_BUFSIZE_512_gc = (0x06<<0), /* 512 bytes buffer size */ - USB_EP_BUFSIZE_1023_gc = (0x07<<0), /* 1023 bytes buffer size */ -} USB_EP_BUFSIZE_t; - - -/* --------------------------------------------------------------------------- -PORT - I/O Port Configuration --------------------------------------------------------------------------- -*/ - -/* I/O Ports */ -typedef struct PORT_struct -{ - register8_t DIR; /* I/O Port Data Direction */ - register8_t DIRSET; /* I/O Port Data Direction Set */ - register8_t DIRCLR; /* I/O Port Data Direction Clear */ - register8_t DIRTGL; /* I/O Port Data Direction Toggle */ - register8_t OUT; /* I/O Port Output */ - register8_t OUTSET; /* I/O Port Output Set */ - register8_t OUTCLR; /* I/O Port Output Clear */ - register8_t OUTTGL; /* I/O Port Output Toggle */ - register8_t IN; /* I/O port Input */ - register8_t INTCTRL; /* Interrupt Control Register */ - register8_t INT0MASK; /* Port Interrupt 0 Mask */ - register8_t INT1MASK; /* Port Interrupt 1 Mask */ - register8_t INTFLAGS; /* Interrupt Flag Register */ - register8_t reserved_0x0D; - register8_t REMAP; /* I/O Port Pin Remap Register */ - register8_t reserved_0x0F; - register8_t PIN0CTRL; /* Pin 0 Control Register */ - register8_t PIN1CTRL; /* Pin 1 Control Register */ - register8_t PIN2CTRL; /* Pin 2 Control Register */ - register8_t PIN3CTRL; /* Pin 3 Control Register */ - register8_t PIN4CTRL; /* Pin 4 Control Register */ - register8_t PIN5CTRL; /* Pin 5 Control Register */ - register8_t PIN6CTRL; /* Pin 6 Control Register */ - register8_t PIN7CTRL; /* Pin 7 Control Register */ -} PORT_t; - -/* Port Interrupt 0 Level */ -typedef enum PORT_INT0LVL_enum -{ - PORT_INT0LVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - PORT_INT0LVL_LO_gc = (0x01<<0), /* Low Level */ - PORT_INT0LVL_MED_gc = (0x02<<0), /* Medium Level */ - PORT_INT0LVL_HI_gc = (0x03<<0), /* High Level */ -} PORT_INT0LVL_t; - -/* Port Interrupt 1 Level */ -typedef enum PORT_INT1LVL_enum -{ - PORT_INT1LVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ - PORT_INT1LVL_LO_gc = (0x01<<2), /* Low Level */ - PORT_INT1LVL_MED_gc = (0x02<<2), /* Medium Level */ - PORT_INT1LVL_HI_gc = (0x03<<2), /* High Level */ -} PORT_INT1LVL_t; - -/* Output/Pull Configuration */ -typedef enum PORT_OPC_enum -{ - PORT_OPC_TOTEM_gc = (0x00<<3), /* Totempole */ - PORT_OPC_BUSKEEPER_gc = (0x01<<3), /* Totempole w/ Bus keeper on Input and Output */ - PORT_OPC_PULLDOWN_gc = (0x02<<3), /* Totempole w/ Pull-down on Input */ - PORT_OPC_PULLUP_gc = (0x03<<3), /* Totempole w/ Pull-up on Input */ - PORT_OPC_WIREDOR_gc = (0x04<<3), /* Wired OR */ - PORT_OPC_WIREDAND_gc = (0x05<<3), /* Wired AND */ - PORT_OPC_WIREDORPULL_gc = (0x06<<3), /* Wired OR w/ Pull-down */ - PORT_OPC_WIREDANDPULL_gc = (0x07<<3), /* Wired AND w/ Pull-up */ -} PORT_OPC_t; - -/* Input/Sense Configuration */ -typedef enum PORT_ISC_enum -{ - PORT_ISC_BOTHEDGES_gc = (0x00<<0), /* Sense Both Edges */ - PORT_ISC_RISING_gc = (0x01<<0), /* Sense Rising Edge */ - PORT_ISC_FALLING_gc = (0x02<<0), /* Sense Falling Edge */ - PORT_ISC_LEVEL_gc = (0x03<<0), /* Sense Level (Transparent For Events) */ - PORT_ISC_INPUT_DISABLE_gc = (0x07<<0), /* Disable Digital Input Buffer */ -} PORT_ISC_t; - - -/* --------------------------------------------------------------------------- -TC - 16-bit Timer/Counter With PWM --------------------------------------------------------------------------- -*/ - -/* 16-bit Timer/Counter 0 */ -typedef struct TC0_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t CTRLC; /* Control register C */ - register8_t CTRLD; /* Control Register D */ - register8_t CTRLE; /* Control Register E */ - register8_t reserved_0x05; - register8_t INTCTRLA; /* Interrupt Control Register A */ - register8_t INTCTRLB; /* Interrupt Control Register B */ - register8_t CTRLFCLR; /* Control Register F Clear */ - register8_t CTRLFSET; /* Control Register F Set */ - register8_t CTRLGCLR; /* Control Register G Clear */ - register8_t CTRLGSET; /* Control Register G Set */ - register8_t INTFLAGS; /* Interrupt Flag Register */ - register8_t reserved_0x0D; - register8_t reserved_0x0E; - register8_t TEMP; /* Temporary Register For 16-bit Access */ - register8_t reserved_0x10; - register8_t reserved_0x11; - register8_t reserved_0x12; - register8_t reserved_0x13; - register8_t reserved_0x14; - register8_t reserved_0x15; - register8_t reserved_0x16; - register8_t reserved_0x17; - register8_t reserved_0x18; - register8_t reserved_0x19; - register8_t reserved_0x1A; - register8_t reserved_0x1B; - register8_t reserved_0x1C; - register8_t reserved_0x1D; - register8_t reserved_0x1E; - register8_t reserved_0x1F; - _WORDREGISTER(CNT); /* Count */ - register8_t reserved_0x22; - register8_t reserved_0x23; - register8_t reserved_0x24; - register8_t reserved_0x25; - _WORDREGISTER(PER); /* Period */ - _WORDREGISTER(CCA); /* Compare or Capture A */ - _WORDREGISTER(CCB); /* Compare or Capture B */ - _WORDREGISTER(CCC); /* Compare or Capture C */ - _WORDREGISTER(CCD); /* Compare or Capture D */ - register8_t reserved_0x30; - register8_t reserved_0x31; - register8_t reserved_0x32; - register8_t reserved_0x33; - register8_t reserved_0x34; - register8_t reserved_0x35; - _WORDREGISTER(PERBUF); /* Period Buffer */ - _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ - _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ - _WORDREGISTER(CCCBUF); /* Compare Or Capture C Buffer */ - _WORDREGISTER(CCDBUF); /* Compare Or Capture D Buffer */ -} TC0_t; - - -/* 16-bit Timer/Counter 1 */ -typedef struct TC1_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t CTRLC; /* Control register C */ - register8_t CTRLD; /* Control Register D */ - register8_t CTRLE; /* Control Register E */ - register8_t reserved_0x05; - register8_t INTCTRLA; /* Interrupt Control Register A */ - register8_t INTCTRLB; /* Interrupt Control Register B */ - register8_t CTRLFCLR; /* Control Register F Clear */ - register8_t CTRLFSET; /* Control Register F Set */ - register8_t CTRLGCLR; /* Control Register G Clear */ - register8_t CTRLGSET; /* Control Register G Set */ - register8_t INTFLAGS; /* Interrupt Flag Register */ - register8_t reserved_0x0D; - register8_t reserved_0x0E; - register8_t TEMP; /* Temporary Register For 16-bit Access */ - register8_t reserved_0x10; - register8_t reserved_0x11; - register8_t reserved_0x12; - register8_t reserved_0x13; - register8_t reserved_0x14; - register8_t reserved_0x15; - register8_t reserved_0x16; - register8_t reserved_0x17; - register8_t reserved_0x18; - register8_t reserved_0x19; - register8_t reserved_0x1A; - register8_t reserved_0x1B; - register8_t reserved_0x1C; - register8_t reserved_0x1D; - register8_t reserved_0x1E; - register8_t reserved_0x1F; - _WORDREGISTER(CNT); /* Count */ - register8_t reserved_0x22; - register8_t reserved_0x23; - register8_t reserved_0x24; - register8_t reserved_0x25; - _WORDREGISTER(PER); /* Period */ - _WORDREGISTER(CCA); /* Compare or Capture A */ - _WORDREGISTER(CCB); /* Compare or Capture B */ - register8_t reserved_0x2C; - register8_t reserved_0x2D; - register8_t reserved_0x2E; - register8_t reserved_0x2F; - register8_t reserved_0x30; - register8_t reserved_0x31; - register8_t reserved_0x32; - register8_t reserved_0x33; - register8_t reserved_0x34; - register8_t reserved_0x35; - _WORDREGISTER(PERBUF); /* Period Buffer */ - _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ - _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ -} TC1_t; - -/* Clock Selection */ -typedef enum TC_CLKSEL_enum -{ - TC_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */ - TC_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */ - TC_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */ - TC_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */ - TC_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */ - TC_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */ - TC_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */ - TC_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */ - TC_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */ - TC_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */ - TC_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */ - TC_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */ -} TC_CLKSEL_t; - -/* Waveform Generation Mode */ -typedef enum TC_WGMODE_enum -{ - TC_WGMODE_NORMAL_gc = (0x00<<0), /* Normal Mode */ - TC_WGMODE_FRQ_gc = (0x01<<0), /* Frequency Generation Mode */ - TC_WGMODE_SINGLESLOPE_gc = (0x03<<0), /* Single Slope */ - TC_WGMODE_SS_gc = (0x03<<0), /* Single Slope */ - TC_WGMODE_DSTOP_gc = (0x05<<0), /* Dual Slope, Update on TOP */ - TC_WGMODE_DS_T_gc = (0x05<<0), /* Dual Slope, Update on TOP */ - TC_WGMODE_DSBOTH_gc = (0x06<<0), /* Dual Slope, Update on both TOP and BOTTOM */ - TC_WGMODE_DS_TB_gc = (0x06<<0), /* Dual Slope, Update on both TOP and BOTTOM */ - TC_WGMODE_DSBOTTOM_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */ - TC_WGMODE_DS_B_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */ -} TC_WGMODE_t; - -/* Byte Mode */ -typedef enum TC_BYTEM_enum -{ - TC_BYTEM_NORMAL_gc = (0x00<<0), /* 16-bit mode */ - TC_BYTEM_BYTEMODE_gc = (0x01<<0), /* Timer/Counter operating in byte mode only */ - TC_BYTEM_SPLITMODE_gc = (0x02<<0), /* Timer/Counter split into two 8-bit Counters (TC2) */ -} TC_BYTEM_t; - -/* Event Action */ -typedef enum TC_EVACT_enum -{ - TC_EVACT_OFF_gc = (0x00<<5), /* No Event Action */ - TC_EVACT_CAPT_gc = (0x01<<5), /* Input Capture */ - TC_EVACT_UPDOWN_gc = (0x02<<5), /* Externally Controlled Up/Down Count */ - TC_EVACT_QDEC_gc = (0x03<<5), /* Quadrature Decode */ - TC_EVACT_RESTART_gc = (0x04<<5), /* Restart */ - TC_EVACT_FRQ_gc = (0x05<<5), /* Frequency Capture */ - TC_EVACT_PW_gc = (0x06<<5), /* Pulse-width Capture */ -} TC_EVACT_t; - -/* Event Selection */ -typedef enum TC_EVSEL_enum -{ - TC_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ - TC_EVSEL_CH0_gc = (0x08<<0), /* Event Channel 0 */ - TC_EVSEL_CH1_gc = (0x09<<0), /* Event Channel 1 */ - TC_EVSEL_CH2_gc = (0x0A<<0), /* Event Channel 2 */ - TC_EVSEL_CH3_gc = (0x0B<<0), /* Event Channel 3 */ -} TC_EVSEL_t; - -/* Error Interrupt Level */ -typedef enum TC_ERRINTLVL_enum -{ - TC_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ - TC_ERRINTLVL_LO_gc = (0x01<<2), /* Low Level */ - TC_ERRINTLVL_MED_gc = (0x02<<2), /* Medium Level */ - TC_ERRINTLVL_HI_gc = (0x03<<2), /* High Level */ -} TC_ERRINTLVL_t; - -/* Overflow Interrupt Level */ -typedef enum TC_OVFINTLVL_enum -{ - TC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - TC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ - TC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ - TC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ -} TC_OVFINTLVL_t; - -/* Compare or Capture D Interrupt Level */ -typedef enum TC_CCDINTLVL_enum -{ - TC_CCDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ - TC_CCDINTLVL_LO_gc = (0x01<<6), /* Low Level */ - TC_CCDINTLVL_MED_gc = (0x02<<6), /* Medium Level */ - TC_CCDINTLVL_HI_gc = (0x03<<6), /* High Level */ -} TC_CCDINTLVL_t; - -/* Compare or Capture C Interrupt Level */ -typedef enum TC_CCCINTLVL_enum -{ - TC_CCCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ - TC_CCCINTLVL_LO_gc = (0x01<<4), /* Low Level */ - TC_CCCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ - TC_CCCINTLVL_HI_gc = (0x03<<4), /* High Level */ -} TC_CCCINTLVL_t; - -/* Compare or Capture B Interrupt Level */ -typedef enum TC_CCBINTLVL_enum -{ - TC_CCBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ - TC_CCBINTLVL_LO_gc = (0x01<<2), /* Low Level */ - TC_CCBINTLVL_MED_gc = (0x02<<2), /* Medium Level */ - TC_CCBINTLVL_HI_gc = (0x03<<2), /* High Level */ -} TC_CCBINTLVL_t; - -/* Compare or Capture A Interrupt Level */ -typedef enum TC_CCAINTLVL_enum -{ - TC_CCAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - TC_CCAINTLVL_LO_gc = (0x01<<0), /* Low Level */ - TC_CCAINTLVL_MED_gc = (0x02<<0), /* Medium Level */ - TC_CCAINTLVL_HI_gc = (0x03<<0), /* High Level */ -} TC_CCAINTLVL_t; - -/* Timer/Counter Command */ -typedef enum TC_CMD_enum -{ - TC_CMD_NONE_gc = (0x00<<2), /* No Command */ - TC_CMD_UPDATE_gc = (0x01<<2), /* Force Update */ - TC_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ - TC_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ -} TC_CMD_t; - - -/* --------------------------------------------------------------------------- -TC2 - 16-bit Timer/Counter type 2 --------------------------------------------------------------------------- -*/ - -/* 16-bit Timer/Counter type 2 */ -typedef struct TC2_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t CTRLC; /* Control register C */ - register8_t reserved_0x03; - register8_t CTRLE; /* Control Register E */ - register8_t reserved_0x05; - register8_t INTCTRLA; /* Interrupt Control Register A */ - register8_t INTCTRLB; /* Interrupt Control Register B */ - register8_t reserved_0x08; - register8_t CTRLF; /* Control Register F */ - register8_t reserved_0x0A; - register8_t reserved_0x0B; - register8_t INTFLAGS; /* Interrupt Flag Register */ - register8_t reserved_0x0D; - register8_t reserved_0x0E; - register8_t reserved_0x0F; - register8_t reserved_0x10; - register8_t reserved_0x11; - register8_t reserved_0x12; - register8_t reserved_0x13; - register8_t reserved_0x14; - register8_t reserved_0x15; - register8_t reserved_0x16; - register8_t reserved_0x17; - register8_t reserved_0x18; - register8_t reserved_0x19; - register8_t reserved_0x1A; - register8_t reserved_0x1B; - register8_t reserved_0x1C; - register8_t reserved_0x1D; - register8_t reserved_0x1E; - register8_t reserved_0x1F; - register8_t LCNT; /* Low Byte Count */ - register8_t HCNT; /* High Byte Count */ - register8_t reserved_0x22; - register8_t reserved_0x23; - register8_t reserved_0x24; - register8_t reserved_0x25; - register8_t LPER; /* Low Byte Period */ - register8_t HPER; /* High Byte Period */ - register8_t LCMPA; /* Low Byte Compare A */ - register8_t HCMPA; /* High Byte Compare A */ - register8_t LCMPB; /* Low Byte Compare B */ - register8_t HCMPB; /* High Byte Compare B */ - register8_t LCMPC; /* Low Byte Compare C */ - register8_t HCMPC; /* High Byte Compare C */ - register8_t LCMPD; /* Low Byte Compare D */ - register8_t HCMPD; /* High Byte Compare D */ -} TC2_t; - -/* Clock Selection */ -typedef enum TC2_CLKSEL_enum -{ - TC2_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */ - TC2_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */ - TC2_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */ - TC2_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */ - TC2_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */ - TC2_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */ - TC2_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */ - TC2_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */ - TC2_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */ - TC2_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */ - TC2_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */ - TC2_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */ -} TC2_CLKSEL_t; - -/* Byte Mode */ -typedef enum TC2_BYTEM_enum -{ - TC2_BYTEM_NORMAL_gc = (0x00<<0), /* 16-bit mode */ - TC2_BYTEM_BYTEMODE_gc = (0x01<<0), /* Timer/Counter operating in byte mode only (TC2) */ - TC2_BYTEM_SPLITMODE_gc = (0x02<<0), /* Timer/Counter split into two 8-bit Counters */ -} TC2_BYTEM_t; - -/* High Byte Underflow Interrupt Level */ -typedef enum TC2_HUNFINTLVL_enum -{ - TC2_HUNFINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ - TC2_HUNFINTLVL_LO_gc = (0x01<<2), /* Low Level */ - TC2_HUNFINTLVL_MED_gc = (0x02<<2), /* Medium Level */ - TC2_HUNFINTLVL_HI_gc = (0x03<<2), /* High Level */ -} TC2_HUNFINTLVL_t; - -/* Low Byte Underflow Interrupt Level */ -typedef enum TC2_LUNFINTLVL_enum -{ - TC2_LUNFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - TC2_LUNFINTLVL_LO_gc = (0x01<<0), /* Low Level */ - TC2_LUNFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ - TC2_LUNFINTLVL_HI_gc = (0x03<<0), /* High Level */ -} TC2_LUNFINTLVL_t; - -/* Low Byte Compare D Interrupt Level */ -typedef enum TC2_LCMPDINTLVL_enum -{ - TC2_LCMPDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ - TC2_LCMPDINTLVL_LO_gc = (0x01<<6), /* Low Level */ - TC2_LCMPDINTLVL_MED_gc = (0x02<<6), /* Medium Level */ - TC2_LCMPDINTLVL_HI_gc = (0x03<<6), /* High Level */ -} TC2_LCMPDINTLVL_t; - -/* Low Byte Compare C Interrupt Level */ -typedef enum TC2_LCMPCINTLVL_enum -{ - TC2_LCMPCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ - TC2_LCMPCINTLVL_LO_gc = (0x01<<4), /* Low Level */ - TC2_LCMPCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ - TC2_LCMPCINTLVL_HI_gc = (0x03<<4), /* High Level */ -} TC2_LCMPCINTLVL_t; - -/* Low Byte Compare B Interrupt Level */ -typedef enum TC2_LCMPBINTLVL_enum -{ - TC2_LCMPBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ - TC2_LCMPBINTLVL_LO_gc = (0x01<<2), /* Low Level */ - TC2_LCMPBINTLVL_MED_gc = (0x02<<2), /* Medium Level */ - TC2_LCMPBINTLVL_HI_gc = (0x03<<2), /* High Level */ -} TC2_LCMPBINTLVL_t; - -/* Low Byte Compare A Interrupt Level */ -typedef enum TC2_LCMPAINTLVL_enum -{ - TC2_LCMPAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - TC2_LCMPAINTLVL_LO_gc = (0x01<<0), /* Low Level */ - TC2_LCMPAINTLVL_MED_gc = (0x02<<0), /* Medium Level */ - TC2_LCMPAINTLVL_HI_gc = (0x03<<0), /* High Level */ -} TC2_LCMPAINTLVL_t; - -/* Timer/Counter Command */ -typedef enum TC2_CMD_enum -{ - TC2_CMD_NONE_gc = (0x00<<2), /* No Command */ - TC2_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ - TC2_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ -} TC2_CMD_t; - -/* Timer/Counter Command */ -typedef enum TC2_CMDEN_enum -{ - TC2_CMDEN_LOW_gc = (0x01<<0), /* Low Byte Timer/Counter */ - TC2_CMDEN_HIGH_gc = (0x02<<0), /* High Byte Timer/Counter */ - TC2_CMDEN_BOTH_gc = (0x03<<0), /* Both Low Byte and High Byte Timer/Counters */ -} TC2_CMDEN_t; - - -/* --------------------------------------------------------------------------- -AWEX - Timer/Counter Advanced Waveform Extension --------------------------------------------------------------------------- -*/ - -/* Advanced Waveform Extension */ -typedef struct AWEX_struct -{ - register8_t CTRL; /* Control Register */ - register8_t reserved_0x01; - register8_t FDEMASK; /* Fault Detection Event Mask */ - register8_t FDCTRL; /* Fault Detection Control Register */ - register8_t STATUS; /* Status Register */ - register8_t STATUSSET; /* Status Set Register */ - register8_t DTBOTH; /* Dead Time Both Sides */ - register8_t DTBOTHBUF; /* Dead Time Both Sides Buffer */ - register8_t DTLS; /* Dead Time Low Side */ - register8_t DTHS; /* Dead Time High Side */ - register8_t DTLSBUF; /* Dead Time Low Side Buffer */ - register8_t DTHSBUF; /* Dead Time High Side Buffer */ - register8_t OUTOVEN; /* Output Override Enable */ -} AWEX_t; - -/* Fault Detect Action */ -typedef enum AWEX_FDACT_enum -{ - AWEX_FDACT_NONE_gc = (0x00<<0), /* No Fault Protection */ - AWEX_FDACT_CLEAROE_gc = (0x01<<0), /* Clear Output Enable Bits */ - AWEX_FDACT_CLEARDIR_gc = (0x03<<0), /* Clear I/O Port Direction Bits */ -} AWEX_FDACT_t; - - -/* --------------------------------------------------------------------------- -HIRES - Timer/Counter High-Resolution Extension --------------------------------------------------------------------------- -*/ - -/* High-Resolution Extension */ -typedef struct HIRES_struct -{ - register8_t CTRLA; /* Control Register */ -} HIRES_t; - -/* High Resolution Enable */ -typedef enum HIRES_HREN_enum -{ - HIRES_HREN_NONE_gc = (0x00<<0), /* No Fault Protection */ - HIRES_HREN_TC0_gc = (0x01<<0), /* Enable High Resolution on Timer/Counter 0 */ - HIRES_HREN_TC1_gc = (0x02<<0), /* Enable High Resolution on Timer/Counter 1 */ - HIRES_HREN_BOTH_gc = (0x03<<0), /* Enable High Resolution both Timer/Counters */ -} HIRES_HREN_t; - - -/* --------------------------------------------------------------------------- -USART - Universal Asynchronous Receiver-Transmitter --------------------------------------------------------------------------- -*/ - -/* Universal Synchronous/Asynchronous Receiver/Transmitter */ -typedef struct USART_struct -{ - register8_t DATA; /* Data Register */ - register8_t STATUS; /* Status Register */ - register8_t reserved_0x02; - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t CTRLC; /* Control Register C */ - register8_t BAUDCTRLA; /* Baud Rate Control Register A */ - register8_t BAUDCTRLB; /* Baud Rate Control Register B */ -} USART_t; - -/* Receive Complete Interrupt level */ -typedef enum USART_RXCINTLVL_enum -{ - USART_RXCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ - USART_RXCINTLVL_LO_gc = (0x01<<4), /* Low Level */ - USART_RXCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ - USART_RXCINTLVL_HI_gc = (0x03<<4), /* High Level */ -} USART_RXCINTLVL_t; - -/* Transmit Complete Interrupt level */ -typedef enum USART_TXCINTLVL_enum -{ - USART_TXCINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ - USART_TXCINTLVL_LO_gc = (0x01<<2), /* Low Level */ - USART_TXCINTLVL_MED_gc = (0x02<<2), /* Medium Level */ - USART_TXCINTLVL_HI_gc = (0x03<<2), /* High Level */ -} USART_TXCINTLVL_t; - -/* Data Register Empty Interrupt level */ -typedef enum USART_DREINTLVL_enum -{ - USART_DREINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - USART_DREINTLVL_LO_gc = (0x01<<0), /* Low Level */ - USART_DREINTLVL_MED_gc = (0x02<<0), /* Medium Level */ - USART_DREINTLVL_HI_gc = (0x03<<0), /* High Level */ -} USART_DREINTLVL_t; - -/* Character Size */ -typedef enum USART_CHSIZE_enum -{ - USART_CHSIZE_5BIT_gc = (0x00<<0), /* Character size: 5 bit */ - USART_CHSIZE_6BIT_gc = (0x01<<0), /* Character size: 6 bit */ - USART_CHSIZE_7BIT_gc = (0x02<<0), /* Character size: 7 bit */ - USART_CHSIZE_8BIT_gc = (0x03<<0), /* Character size: 8 bit */ - USART_CHSIZE_9BIT_gc = (0x07<<0), /* Character size: 9 bit */ -} USART_CHSIZE_t; - -/* Communication Mode */ -typedef enum USART_CMODE_enum -{ - USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6), /* Asynchronous Mode */ - USART_CMODE_SYNCHRONOUS_gc = (0x01<<6), /* Synchronous Mode */ - USART_CMODE_IRDA_gc = (0x02<<6), /* IrDA Mode */ - USART_CMODE_MSPI_gc = (0x03<<6), /* Master SPI Mode */ -} USART_CMODE_t; - -/* Parity Mode */ -typedef enum USART_PMODE_enum -{ - USART_PMODE_DISABLED_gc = (0x00<<4), /* No Parity */ - USART_PMODE_EVEN_gc = (0x02<<4), /* Even Parity */ - USART_PMODE_ODD_gc = (0x03<<4), /* Odd Parity */ -} USART_PMODE_t; - - -/* --------------------------------------------------------------------------- -SPI - Serial Peripheral Interface --------------------------------------------------------------------------- -*/ - -/* Serial Peripheral Interface */ -typedef struct SPI_struct -{ - register8_t CTRL; /* Control Register */ - register8_t INTCTRL; /* Interrupt Control Register */ - register8_t STATUS; /* Status Register */ - register8_t DATA; /* Data Register */ -} SPI_t; - -/* SPI Mode */ -typedef enum SPI_MODE_enum -{ - SPI_MODE_0_gc = (0x00<<2), /* SPI Mode 0 */ - SPI_MODE_1_gc = (0x01<<2), /* SPI Mode 1 */ - SPI_MODE_2_gc = (0x02<<2), /* SPI Mode 2 */ - SPI_MODE_3_gc = (0x03<<2), /* SPI Mode 3 */ -} SPI_MODE_t; - -/* Prescaler setting */ -typedef enum SPI_PRESCALER_enum -{ - SPI_PRESCALER_DIV4_gc = (0x00<<0), /* System Clock / 4 */ - SPI_PRESCALER_DIV16_gc = (0x01<<0), /* System Clock / 16 */ - SPI_PRESCALER_DIV64_gc = (0x02<<0), /* System Clock / 64 */ - SPI_PRESCALER_DIV128_gc = (0x03<<0), /* System Clock / 128 */ -} SPI_PRESCALER_t; - -/* Interrupt level */ -typedef enum SPI_INTLVL_enum -{ - SPI_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - SPI_INTLVL_LO_gc = (0x01<<0), /* Low Level */ - SPI_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ - SPI_INTLVL_HI_gc = (0x03<<0), /* High Level */ -} SPI_INTLVL_t; - - -/* --------------------------------------------------------------------------- -IRCOM - IR Communication Module --------------------------------------------------------------------------- -*/ - -/* IR Communication Module */ -typedef struct IRCOM_struct -{ - register8_t CTRL; /* Control Register */ - register8_t TXPLCTRL; /* IrDA Transmitter Pulse Length Control Register */ - register8_t RXPLCTRL; /* IrDA Receiver Pulse Length Control Register */ -} IRCOM_t; - -/* Event channel selection */ -typedef enum IRDA_EVSEL_enum -{ - IRDA_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ - IRDA_EVSEL_0_gc = (0x08<<0), /* Event Channel 0 */ - IRDA_EVSEL_1_gc = (0x09<<0), /* Event Channel 1 */ - IRDA_EVSEL_2_gc = (0x0A<<0), /* Event Channel 2 */ - IRDA_EVSEL_3_gc = (0x0B<<0), /* Event Channel 3 */ -} IRDA_EVSEL_t; - - -/* --------------------------------------------------------------------------- -FUSE - Fuses and Lockbits --------------------------------------------------------------------------- -*/ - -/* Fuses */ -typedef struct NVM_FUSES_struct -{ - register8_t reserved_0x00; - register8_t FUSEBYTE1; /* Watchdog Configuration */ - register8_t FUSEBYTE2; /* Reset Configuration */ - register8_t reserved_0x03; - register8_t FUSEBYTE4; /* Start-up Configuration */ - register8_t FUSEBYTE5; /* EESAVE and BOD Level */ -} NVM_FUSES_t; - -/* Boot Loader Section Reset Vector */ -typedef enum BOOTRST_enum -{ - BOOTRST_BOOTLDR_gc = (0x00<<6), /* Boot Loader Reset */ - BOOTRST_APPLICATION_gc = (0x01<<6), /* Application Reset */ -} BOOTRST_t; - -/* Timer Oscillator pin location */ -typedef enum TOSCSEL_enum -{ - TOSCSEL_ALTERNATE_gc = (0x00<<5), /* TOSC1 / TOSC2 on separate pins */ - TOSCSEL_XTAL_gc = (0x01<<5), /* TOSC1 / TOSC2 shared with XTAL1 / XTAL2 */ -} TOSCSEL_t; - -/* BOD operation */ -typedef enum BOD_enum -{ - BOD_SAMPLED_gc = (0x01<<0), /* BOD enabled in sampled mode */ - BOD_CONTINUOUS_gc = (0x02<<0), /* BOD enabled continuously */ - BOD_DISABLED_gc = (0x03<<0), /* BOD Disabled */ -} BOD_t; - -/* BOD operation */ -typedef enum BODACT_enum -{ - BODACT_SAMPLED_gc = (0x01<<4), /* BOD enabled in sampled mode */ - BODACT_CONTINUOUS_gc = (0x02<<4), /* BOD enabled continuously */ - BODACT_DISABLED_gc = (0x03<<4), /* BOD Disabled */ -} BODACT_t; - -/* Watchdog (Window) Timeout Period */ -typedef enum WD_enum -{ - WD_8CLK_gc = (0x00<<4), /* 8 cycles (8ms @ 3.3V) */ - WD_16CLK_gc = (0x01<<4), /* 16 cycles (16ms @ 3.3V) */ - WD_32CLK_gc = (0x02<<4), /* 32 cycles (32ms @ 3.3V) */ - WD_64CLK_gc = (0x03<<4), /* 64 cycles (64ms @ 3.3V) */ - WD_128CLK_gc = (0x04<<4), /* 128 cycles (0.125s @ 3.3V) */ - WD_256CLK_gc = (0x05<<4), /* 256 cycles (0.25s @ 3.3V) */ - WD_512CLK_gc = (0x06<<4), /* 512 cycles (0.5s @ 3.3V) */ - WD_1KCLK_gc = (0x07<<4), /* 1K cycles (1s @ 3.3V) */ - WD_2KCLK_gc = (0x08<<4), /* 2K cycles (2s @ 3.3V) */ - WD_4KCLK_gc = (0x09<<4), /* 4K cycles (4s @ 3.3V) */ - WD_8KCLK_gc = (0x0A<<4), /* 8K cycles (8s @ 3.3V) */ -} WD_t; - -/* Watchdog (Window) Timeout Period */ -typedef enum WDP_enum -{ - WDP_8CLK_gc = (0x00<<0), /* 8 cycles (8ms @ 3.3V) */ - WDP_16CLK_gc = (0x01<<0), /* 16 cycles (16ms @ 3.3V) */ - WDP_32CLK_gc = (0x02<<0), /* 32 cycles (32ms @ 3.3V) */ - WDP_64CLK_gc = (0x03<<0), /* 64 cycles (64ms @ 3.3V) */ - WDP_128CLK_gc = (0x04<<0), /* 128 cycles (0.125s @ 3.3V) */ - WDP_256CLK_gc = (0x05<<0), /* 256 cycles (0.25s @ 3.3V) */ - WDP_512CLK_gc = (0x06<<0), /* 512 cycles (0.5s @ 3.3V) */ - WDP_1KCLK_gc = (0x07<<0), /* 1K cycles (1s @ 3.3V) */ - WDP_2KCLK_gc = (0x08<<0), /* 2K cycles (2s @ 3.3V) */ - WDP_4KCLK_gc = (0x09<<0), /* 4K cycles (4s @ 3.3V) */ - WDP_8KCLK_gc = (0x0A<<0), /* 8K cycles (8s @ 3.3V) */ -} WDP_t; - -/* Start-up Time */ -typedef enum SUT_enum -{ - SUT_0MS_gc = (0x03<<2), /* 0 ms */ - SUT_4MS_gc = (0x01<<2), /* 4 ms */ - SUT_64MS_gc = (0x00<<2), /* 64 ms */ -} SUT_t; - -/* Brownout Detection Voltage Level */ -typedef enum BODLVL_enum -{ - BODLVL_1V6_gc = (0x07<<0), /* 1.6 V */ - BODLVL_1V8_gc = (0x06<<0), /* 1.8 V */ - BODLVL_2V0_gc = (0x05<<0), /* 2.0 V */ - BODLVL_2V2_gc = (0x04<<0), /* 2.2 V */ - BODLVL_2V4_gc = (0x03<<0), /* 2.4 V */ - BODLVL_2V6_gc = (0x02<<0), /* 2.6 V */ - BODLVL_2V8_gc = (0x01<<0), /* 2.8 V */ - BODLVL_3V0_gc = (0x00<<0), /* 3.0 V */ -} BODLVL_t; - - -/* --------------------------------------------------------------------------- -LOCKBIT - Fuses and Lockbits --------------------------------------------------------------------------- -*/ - -/* Lock Bits */ -typedef struct NVM_LOCKBITS_struct -{ - register8_t LOCK_BITS; /* Lock Bits (Changed from LOCKBITS to avoid avr-libc collision) */ -} NVM_LOCKBITS_t; - -/* Boot lock bits - boot setcion */ -typedef enum FUSE_BLBB_enum -{ - FUSE_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ - FUSE_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ - FUSE_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ - FUSE_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ -} FUSE_BLBB_t; - -/* Boot lock bits - application section */ -typedef enum FUSE_BLBA_enum -{ - FUSE_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ - FUSE_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ - FUSE_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ - FUSE_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ -} FUSE_BLBA_t; - -/* Boot lock bits - application table section */ -typedef enum FUSE_BLBAT_enum -{ - FUSE_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ - FUSE_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ - FUSE_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ - FUSE_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ -} FUSE_BLBAT_t; - -/* Lock bits */ -typedef enum FUSE_LB_enum -{ - FUSE_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ - FUSE_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ - FUSE_LB_NOLOCK_gc = (0x03<<0), /* No locks */ -} FUSE_LB_t; - - -/* --------------------------------------------------------------------------- -SIGROW - Signature Row --------------------------------------------------------------------------- -*/ - -/* Production Signatures */ -typedef struct NVM_PROD_SIGNATURES_struct -{ - register8_t RCOSC2M; /* RCOSC 2 MHz Calibration Value B */ - register8_t RCOSC2MA; /* RCOSC 2 MHz Calibration Value A */ - register8_t RCOSC32K; /* RCOSC 32.768 kHz Calibration Value */ - register8_t RCOSC32M; /* RCOSC 32 MHz Calibration Value B */ - register8_t RCOSC32MA; /* RCOSC 32 MHz Calibration Value A */ - register8_t reserved_0x05; - register8_t reserved_0x06; - register8_t reserved_0x07; - register8_t LOTNUM0; /* Lot Number Byte 0, ASCII */ - register8_t LOTNUM1; /* Lot Number Byte 1, ASCII */ - register8_t LOTNUM2; /* Lot Number Byte 2, ASCII */ - register8_t LOTNUM3; /* Lot Number Byte 3, ASCII */ - register8_t LOTNUM4; /* Lot Number Byte 4, ASCII */ - register8_t LOTNUM5; /* Lot Number Byte 5, ASCII */ - register8_t reserved_0x0E; - register8_t reserved_0x0F; - register8_t WAFNUM; /* Wafer Number */ - register8_t reserved_0x11; - register8_t COORDX0; /* Wafer Coordinate X Byte 0 */ - register8_t COORDX1; /* Wafer Coordinate X Byte 1 */ - register8_t COORDY0; /* Wafer Coordinate Y Byte 0 */ - register8_t COORDY1; /* Wafer Coordinate Y Byte 1 */ - register8_t reserved_0x16; - register8_t reserved_0x17; - register8_t reserved_0x18; - register8_t reserved_0x19; - register8_t USBCAL0; /* USB Calibration Byte 0 */ - register8_t USBCAL1; /* USB Calibration Byte 1 */ - register8_t USBRCOSC; /* USB RCOSC Calibration Value B */ - register8_t USBRCOSCA; /* USB RCOSC Calibration Value A */ - register8_t reserved_0x1E; - register8_t reserved_0x1F; - register8_t ADCACAL0; /* ADCA Calibration Byte 0 */ - register8_t ADCACAL1; /* ADCA Calibration Byte 1 */ - register8_t reserved_0x22; - register8_t reserved_0x23; - register8_t reserved_0x24; - register8_t reserved_0x25; - register8_t reserved_0x26; - register8_t reserved_0x27; - register8_t reserved_0x28; - register8_t reserved_0x29; - register8_t reserved_0x2A; - register8_t reserved_0x2B; - register8_t reserved_0x2C; - register8_t reserved_0x2D; - register8_t TEMPSENSE0; /* Temperature Sensor Calibration Byte 0 */ - register8_t TEMPSENSE1; /* Temperature Sensor Calibration Byte 1 */ - register8_t reserved_0x30; - register8_t reserved_0x31; - register8_t reserved_0x32; - register8_t reserved_0x33; - register8_t reserved_0x34; - register8_t reserved_0x35; - register8_t reserved_0x36; - register8_t reserved_0x37; - register8_t reserved_0x38; - register8_t reserved_0x39; - register8_t reserved_0x3A; - register8_t reserved_0x3B; - register8_t reserved_0x3C; - register8_t reserved_0x3D; - register8_t reserved_0x3E; - register8_t reserved_0x3F; -} NVM_PROD_SIGNATURES_t; - -/* -========================================================================== -IO Module Instances. Mapped to memory. -========================================================================== -*/ - -#define VPORT0 (*(VPORT_t *) 0x0010) /* Virtual Port */ -#define VPORT1 (*(VPORT_t *) 0x0014) /* Virtual Port */ -#define VPORT2 (*(VPORT_t *) 0x0018) /* Virtual Port */ -#define VPORT3 (*(VPORT_t *) 0x001C) /* Virtual Port */ -#define OCD (*(OCD_t *) 0x002E) /* On-Chip Debug System */ -#define CLK (*(CLK_t *) 0x0040) /* Clock System */ -#define SLEEP (*(SLEEP_t *) 0x0048) /* Sleep Controller */ -#define OSC (*(OSC_t *) 0x0050) /* Oscillator */ -#define DFLLRC32M (*(DFLL_t *) 0x0060) /* DFLL */ -#define DFLLRC2M (*(DFLL_t *) 0x0068) /* DFLL */ -#define PR (*(PR_t *) 0x0070) /* Power Reduction */ -#define RST (*(RST_t *) 0x0078) /* Reset */ -#define WDT (*(WDT_t *) 0x0080) /* Watch-Dog Timer */ -#define MCU (*(MCU_t *) 0x0090) /* MCU Control */ -#define PMIC (*(PMIC_t *) 0x00A0) /* Programmable Multi-level Interrupt Controller */ -#define PORTCFG (*(PORTCFG_t *) 0x00B0) /* I/O port Configuration */ -#define CRC (*(CRC_t *) 0x00D0) /* Cyclic Redundancy Checker */ -#define EVSYS (*(EVSYS_t *) 0x0180) /* Event System */ -#define NVM (*(NVM_t *) 0x01C0) /* Non-volatile Memory Controller */ -#define ADCA (*(ADC_t *) 0x0200) /* Analog-to-Digital Converter */ -#define ACA (*(AC_t *) 0x0380) /* Analog Comparator */ -#define RTC (*(RTC_t *) 0x0400) /* Real-Time Counter */ -#define TWIC (*(TWI_t *) 0x0480) /* Two-Wire Interface */ -#define TWIE (*(TWI_t *) 0x04A0) /* Two-Wire Interface */ -#define USB (*(USB_t *) 0x04C0) /* Universal Serial Bus */ -#define PORTA (*(PORT_t *) 0x0600) /* I/O Ports */ -#define PORTB (*(PORT_t *) 0x0620) /* I/O Ports */ -#define PORTC (*(PORT_t *) 0x0640) /* I/O Ports */ -#define PORTD (*(PORT_t *) 0x0660) /* I/O Ports */ -#define PORTE (*(PORT_t *) 0x0680) /* I/O Ports */ -#define PORTF (*(PORT_t *) 0x06A0) /* I/O Ports */ -#define PORTR (*(PORT_t *) 0x07E0) /* I/O Ports */ -#define TCC0 (*(TC0_t *) 0x0800) /* 16-bit Timer/Counter 0 */ -#define TCC2 (*(TC2_t *) 0x0800) /* 16-bit Timer/Counter type 2 */ -#define TCC1 (*(TC1_t *) 0x0840) /* 16-bit Timer/Counter 1 */ -#define AWEXC (*(AWEX_t *) 0x0880) /* Advanced Waveform Extension */ -#define HIRESC (*(HIRES_t *) 0x0890) /* High-Resolution Extension */ -#define USARTC0 (*(USART_t *) 0x08A0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ -#define SPIC (*(SPI_t *) 0x08C0) /* Serial Peripheral Interface */ -#define IRCOM (*(IRCOM_t *) 0x08F8) /* IR Communication Module */ -#define TCD0 (*(TC0_t *) 0x0900) /* 16-bit Timer/Counter 0 */ -#define TCD2 (*(TC2_t *) 0x0900) /* 16-bit Timer/Counter type 2 */ -#define USARTD0 (*(USART_t *) 0x09A0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ -#define SPID (*(SPI_t *) 0x09C0) /* Serial Peripheral Interface */ -#define TCE0 (*(TC0_t *) 0x0A00) /* 16-bit Timer/Counter 0 */ -#define TCE2 (*(TC2_t *) 0x0A00) /* 16-bit Timer/Counter type 2 */ -#define USARTE0 (*(USART_t *) 0x0AA0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ -#define TCF0 (*(TC0_t *) 0x0B00) /* 16-bit Timer/Counter 0 */ -#define TCF2 (*(TC2_t *) 0x0B00) /* 16-bit Timer/Counter type 2 */ - - -#endif /* !defined (__ASSEMBLER__) */ - - -/* ========== Flattened fully qualified IO register names ========== */ - -/* GPIO - General Purpose IO Registers */ -#define GPIO_GPIOR0 _SFR_MEM8(0x0000) -#define GPIO_GPIOR1 _SFR_MEM8(0x0001) -#define GPIO_GPIOR2 _SFR_MEM8(0x0002) -#define GPIO_GPIOR3 _SFR_MEM8(0x0003) - -/* Deprecated */ -#define GPIO_GPIO0 _SFR_MEM8(0x0000) -#define GPIO_GPIO1 _SFR_MEM8(0x0001) -#define GPIO_GPIO2 _SFR_MEM8(0x0002) -#define GPIO_GPIO3 _SFR_MEM8(0x0003) - -/* NVM_FUSES - Fuses */ -#define FUSE_FUSEBYTE1 _SFR_MEM8(0x0001) -#define FUSE_FUSEBYTE2 _SFR_MEM8(0x0002) -#define FUSE_FUSEBYTE4 _SFR_MEM8(0x0004) -#define FUSE_FUSEBYTE5 _SFR_MEM8(0x0005) - -/* NVM_LOCKBITS - Lock Bits */ -#define LOCKBIT_LOCKBITS _SFR_MEM8(0x0000) - -/* NVM_PROD_SIGNATURES - Production Signatures */ -#define PRODSIGNATURES_RCOSC2M _SFR_MEM8(0x0000) -#define PRODSIGNATURES_RCOSC2MA _SFR_MEM8(0x0001) -#define PRODSIGNATURES_RCOSC32K _SFR_MEM8(0x0002) -#define PRODSIGNATURES_RCOSC32M _SFR_MEM8(0x0003) -#define PRODSIGNATURES_RCOSC32MA _SFR_MEM8(0x0004) -#define PRODSIGNATURES_LOTNUM0 _SFR_MEM8(0x0008) -#define PRODSIGNATURES_LOTNUM1 _SFR_MEM8(0x0009) -#define PRODSIGNATURES_LOTNUM2 _SFR_MEM8(0x000A) -#define PRODSIGNATURES_LOTNUM3 _SFR_MEM8(0x000B) -#define PRODSIGNATURES_LOTNUM4 _SFR_MEM8(0x000C) -#define PRODSIGNATURES_LOTNUM5 _SFR_MEM8(0x000D) -#define PRODSIGNATURES_WAFNUM _SFR_MEM8(0x0010) -#define PRODSIGNATURES_COORDX0 _SFR_MEM8(0x0012) -#define PRODSIGNATURES_COORDX1 _SFR_MEM8(0x0013) -#define PRODSIGNATURES_COORDY0 _SFR_MEM8(0x0014) -#define PRODSIGNATURES_COORDY1 _SFR_MEM8(0x0015) -#define PRODSIGNATURES_USBCAL0 _SFR_MEM8(0x001A) -#define PRODSIGNATURES_USBCAL1 _SFR_MEM8(0x001B) -#define PRODSIGNATURES_USBRCOSC _SFR_MEM8(0x001C) -#define PRODSIGNATURES_USBRCOSCA _SFR_MEM8(0x001D) -#define PRODSIGNATURES_ADCACAL0 _SFR_MEM8(0x0020) -#define PRODSIGNATURES_ADCACAL1 _SFR_MEM8(0x0021) -#define PRODSIGNATURES_TEMPSENSE0 _SFR_MEM8(0x002E) -#define PRODSIGNATURES_TEMPSENSE1 _SFR_MEM8(0x002F) - -/* VPORT - Virtual Port */ -#define VPORT0_DIR _SFR_MEM8(0x0010) -#define VPORT0_OUT _SFR_MEM8(0x0011) -#define VPORT0_IN _SFR_MEM8(0x0012) -#define VPORT0_INTFLAGS _SFR_MEM8(0x0013) - -/* VPORT - Virtual Port */ -#define VPORT1_DIR _SFR_MEM8(0x0014) -#define VPORT1_OUT _SFR_MEM8(0x0015) -#define VPORT1_IN _SFR_MEM8(0x0016) -#define VPORT1_INTFLAGS _SFR_MEM8(0x0017) - -/* VPORT - Virtual Port */ -#define VPORT2_DIR _SFR_MEM8(0x0018) -#define VPORT2_OUT _SFR_MEM8(0x0019) -#define VPORT2_IN _SFR_MEM8(0x001A) -#define VPORT2_INTFLAGS _SFR_MEM8(0x001B) - -/* VPORT - Virtual Port */ -#define VPORT3_DIR _SFR_MEM8(0x001C) -#define VPORT3_OUT _SFR_MEM8(0x001D) -#define VPORT3_IN _SFR_MEM8(0x001E) -#define VPORT3_INTFLAGS _SFR_MEM8(0x001F) - -/* OCD - On-Chip Debug System */ -#define OCD_OCDR0 _SFR_MEM8(0x002E) -#define OCD_OCDR1 _SFR_MEM8(0x002F) - -/* CPU - CPU registers */ -#define CPU_CCP _SFR_MEM8(0x0034) -#define CPU_RAMPD _SFR_MEM8(0x0038) -#define CPU_RAMPX _SFR_MEM8(0x0039) -#define CPU_RAMPY _SFR_MEM8(0x003A) -#define CPU_RAMPZ _SFR_MEM8(0x003B) -#define CPU_EIND _SFR_MEM8(0x003C) -#define CPU_SPL _SFR_MEM8(0x003D) -#define CPU_SPH _SFR_MEM8(0x003E) -#define CPU_SREG _SFR_MEM8(0x003F) - -/* CLK - Clock System */ -#define CLK_CTRL _SFR_MEM8(0x0040) -#define CLK_PSCTRL _SFR_MEM8(0x0041) -#define CLK_LOCK _SFR_MEM8(0x0042) -#define CLK_RTCCTRL _SFR_MEM8(0x0043) -#define CLK_USBCTRL _SFR_MEM8(0x0044) - -/* SLEEP - Sleep Controller */ -#define SLEEP_CTRL _SFR_MEM8(0x0048) - -/* OSC - Oscillator */ -#define OSC_CTRL _SFR_MEM8(0x0050) -#define OSC_STATUS _SFR_MEM8(0x0051) -#define OSC_XOSCCTRL _SFR_MEM8(0x0052) -#define OSC_XOSCFAIL _SFR_MEM8(0x0053) -#define OSC_RC32KCAL _SFR_MEM8(0x0054) -#define OSC_PLLCTRL _SFR_MEM8(0x0055) -#define OSC_DFLLCTRL _SFR_MEM8(0x0056) - -/* DFLL - DFLL */ -#define DFLLRC32M_CTRL _SFR_MEM8(0x0060) -#define DFLLRC32M_CALA _SFR_MEM8(0x0062) -#define DFLLRC32M_CALB _SFR_MEM8(0x0063) -#define DFLLRC32M_COMP0 _SFR_MEM8(0x0064) -#define DFLLRC32M_COMP1 _SFR_MEM8(0x0065) -#define DFLLRC32M_COMP2 _SFR_MEM8(0x0066) - -/* DFLL - DFLL */ -#define DFLLRC2M_CTRL _SFR_MEM8(0x0068) -#define DFLLRC2M_CALA _SFR_MEM8(0x006A) -#define DFLLRC2M_CALB _SFR_MEM8(0x006B) -#define DFLLRC2M_COMP0 _SFR_MEM8(0x006C) -#define DFLLRC2M_COMP1 _SFR_MEM8(0x006D) -#define DFLLRC2M_COMP2 _SFR_MEM8(0x006E) - -/* PR - Power Reduction */ -#define PR_PRGEN _SFR_MEM8(0x0070) -#define PR_PRPA _SFR_MEM8(0x0071) -#define PR_PRPC _SFR_MEM8(0x0073) -#define PR_PRPD _SFR_MEM8(0x0074) -#define PR_PRPE _SFR_MEM8(0x0075) -#define PR_PRPF _SFR_MEM8(0x0076) - -/* RST - Reset */ -#define RST_STATUS _SFR_MEM8(0x0078) -#define RST_CTRL _SFR_MEM8(0x0079) - -/* WDT - Watch-Dog Timer */ -#define WDT_CTRL _SFR_MEM8(0x0080) -#define WDT_WINCTRL _SFR_MEM8(0x0081) -#define WDT_STATUS _SFR_MEM8(0x0082) - -/* MCU - MCU Control */ -#define MCU_DEVID0 _SFR_MEM8(0x0090) -#define MCU_DEVID1 _SFR_MEM8(0x0091) -#define MCU_DEVID2 _SFR_MEM8(0x0092) -#define MCU_REVID _SFR_MEM8(0x0093) -#define MCU_ANAINIT _SFR_MEM8(0x0097) -#define MCU_EVSYSLOCK _SFR_MEM8(0x0098) -#define MCU_AWEXLOCK _SFR_MEM8(0x0099) - -/* PMIC - Programmable Multi-level Interrupt Controller */ -#define PMIC_STATUS _SFR_MEM8(0x00A0) -#define PMIC_INTPRI _SFR_MEM8(0x00A1) -#define PMIC_CTRL _SFR_MEM8(0x00A2) - -/* PORTCFG - I/O port Configuration */ -#define PORTCFG_MPCMASK _SFR_MEM8(0x00B0) -#define PORTCFG_VPCTRLA _SFR_MEM8(0x00B2) -#define PORTCFG_VPCTRLB _SFR_MEM8(0x00B3) -#define PORTCFG_CLKEVOUT _SFR_MEM8(0x00B4) -#define PORTCFG_EVOUTSEL _SFR_MEM8(0x00B6) - -/* CRC - Cyclic Redundancy Checker */ -#define CRC_CTRL _SFR_MEM8(0x00D0) -#define CRC_STATUS _SFR_MEM8(0x00D1) -#define CRC_DATAIN _SFR_MEM8(0x00D3) -#define CRC_CHECKSUM0 _SFR_MEM8(0x00D4) -#define CRC_CHECKSUM1 _SFR_MEM8(0x00D5) -#define CRC_CHECKSUM2 _SFR_MEM8(0x00D6) -#define CRC_CHECKSUM3 _SFR_MEM8(0x00D7) - -/* EVSYS - Event System */ -#define EVSYS_CH0MUX _SFR_MEM8(0x0180) -#define EVSYS_CH1MUX _SFR_MEM8(0x0181) -#define EVSYS_CH2MUX _SFR_MEM8(0x0182) -#define EVSYS_CH3MUX _SFR_MEM8(0x0183) -#define EVSYS_CH0CTRL _SFR_MEM8(0x0188) -#define EVSYS_CH1CTRL _SFR_MEM8(0x0189) -#define EVSYS_CH2CTRL _SFR_MEM8(0x018A) -#define EVSYS_CH3CTRL _SFR_MEM8(0x018B) -#define EVSYS_STROBE _SFR_MEM8(0x0190) -#define EVSYS_DATA _SFR_MEM8(0x0191) - -/* NVM - Non-volatile Memory Controller */ -#define NVM_ADDR0 _SFR_MEM8(0x01C0) -#define NVM_ADDR1 _SFR_MEM8(0x01C1) -#define NVM_ADDR2 _SFR_MEM8(0x01C2) -#define NVM_DATA0 _SFR_MEM8(0x01C4) -#define NVM_DATA1 _SFR_MEM8(0x01C5) -#define NVM_DATA2 _SFR_MEM8(0x01C6) -#define NVM_CMD _SFR_MEM8(0x01CA) -#define NVM_CTRLA _SFR_MEM8(0x01CB) -#define NVM_CTRLB _SFR_MEM8(0x01CC) -#define NVM_INTCTRL _SFR_MEM8(0x01CD) -#define NVM_STATUS _SFR_MEM8(0x01CF) -#define NVM_LOCKBITS _SFR_MEM8(0x01D0) - -/* ADC - Analog-to-Digital Converter */ -#define ADCA_CTRLA _SFR_MEM8(0x0200) -#define ADCA_CTRLB _SFR_MEM8(0x0201) -#define ADCA_REFCTRL _SFR_MEM8(0x0202) -#define ADCA_EVCTRL _SFR_MEM8(0x0203) -#define ADCA_PRESCALER _SFR_MEM8(0x0204) -#define ADCA_INTFLAGS _SFR_MEM8(0x0206) -#define ADCA_TEMP _SFR_MEM8(0x0207) -#define ADCA_CAL _SFR_MEM16(0x020C) -#define ADCA_CH0RES _SFR_MEM16(0x0210) -#define ADCA_CMP _SFR_MEM16(0x0218) -#define ADCA_CH0_CTRL _SFR_MEM8(0x0220) -#define ADCA_CH0_MUXCTRL _SFR_MEM8(0x0221) -#define ADCA_CH0_INTCTRL _SFR_MEM8(0x0222) -#define ADCA_CH0_INTFLAGS _SFR_MEM8(0x0223) -#define ADCA_CH0_RES _SFR_MEM16(0x0224) -#define ADCA_CH0_SCAN _SFR_MEM8(0x0226) - -/* AC - Analog Comparator */ -#define ACA_AC0CTRL _SFR_MEM8(0x0380) -#define ACA_AC1CTRL _SFR_MEM8(0x0381) -#define ACA_AC0MUXCTRL _SFR_MEM8(0x0382) -#define ACA_AC1MUXCTRL _SFR_MEM8(0x0383) -#define ACA_CTRLA _SFR_MEM8(0x0384) -#define ACA_CTRLB _SFR_MEM8(0x0385) -#define ACA_WINCTRL _SFR_MEM8(0x0386) -#define ACA_STATUS _SFR_MEM8(0x0387) - -/* RTC - Real-Time Counter */ -#define RTC_CTRL _SFR_MEM8(0x0400) -#define RTC_STATUS _SFR_MEM8(0x0401) -#define RTC_INTCTRL _SFR_MEM8(0x0402) -#define RTC_INTFLAGS _SFR_MEM8(0x0403) -#define RTC_TEMP _SFR_MEM8(0x0404) -#define RTC_CNT _SFR_MEM16(0x0408) -#define RTC_PER _SFR_MEM16(0x040A) -#define RTC_COMP _SFR_MEM16(0x040C) - -/* TWI - Two-Wire Interface */ -#define TWIC_CTRL _SFR_MEM8(0x0480) -#define TWIC_MASTER_CTRLA _SFR_MEM8(0x0481) -#define TWIC_MASTER_CTRLB _SFR_MEM8(0x0482) -#define TWIC_MASTER_CTRLC _SFR_MEM8(0x0483) -#define TWIC_MASTER_STATUS _SFR_MEM8(0x0484) -#define TWIC_MASTER_BAUD _SFR_MEM8(0x0485) -#define TWIC_MASTER_ADDR _SFR_MEM8(0x0486) -#define TWIC_MASTER_DATA _SFR_MEM8(0x0487) -#define TWIC_SLAVE_CTRLA _SFR_MEM8(0x0488) -#define TWIC_SLAVE_CTRLB _SFR_MEM8(0x0489) -#define TWIC_SLAVE_STATUS _SFR_MEM8(0x048A) -#define TWIC_SLAVE_ADDR _SFR_MEM8(0x048B) -#define TWIC_SLAVE_DATA _SFR_MEM8(0x048C) -#define TWIC_SLAVE_ADDRMASK _SFR_MEM8(0x048D) - -/* TWI - Two-Wire Interface */ -#define TWIE_CTRL _SFR_MEM8(0x04A0) -#define TWIE_MASTER_CTRLA _SFR_MEM8(0x04A1) -#define TWIE_MASTER_CTRLB _SFR_MEM8(0x04A2) -#define TWIE_MASTER_CTRLC _SFR_MEM8(0x04A3) -#define TWIE_MASTER_STATUS _SFR_MEM8(0x04A4) -#define TWIE_MASTER_BAUD _SFR_MEM8(0x04A5) -#define TWIE_MASTER_ADDR _SFR_MEM8(0x04A6) -#define TWIE_MASTER_DATA _SFR_MEM8(0x04A7) -#define TWIE_SLAVE_CTRLA _SFR_MEM8(0x04A8) -#define TWIE_SLAVE_CTRLB _SFR_MEM8(0x04A9) -#define TWIE_SLAVE_STATUS _SFR_MEM8(0x04AA) -#define TWIE_SLAVE_ADDR _SFR_MEM8(0x04AB) -#define TWIE_SLAVE_DATA _SFR_MEM8(0x04AC) -#define TWIE_SLAVE_ADDRMASK _SFR_MEM8(0x04AD) - -/* USB - Universal Serial Bus */ -#define USB_CTRLA _SFR_MEM8(0x04C0) -#define USB_CTRLB _SFR_MEM8(0x04C1) -#define USB_STATUS _SFR_MEM8(0x04C2) -#define USB_ADDR _SFR_MEM8(0x04C3) -#define USB_FIFOWP _SFR_MEM8(0x04C4) -#define USB_FIFORP _SFR_MEM8(0x04C5) -#define USB_EPPTR _SFR_MEM16(0x04C6) -#define USB_INTCTRLA _SFR_MEM8(0x04C8) -#define USB_INTCTRLB _SFR_MEM8(0x04C9) -#define USB_INTFLAGSACLR _SFR_MEM8(0x04CA) -#define USB_INTFLAGSASET _SFR_MEM8(0x04CB) -#define USB_INTFLAGSBCLR _SFR_MEM8(0x04CC) -#define USB_INTFLAGSBSET _SFR_MEM8(0x04CD) -#define USB_CAL0 _SFR_MEM8(0x04FA) -#define USB_CAL1 _SFR_MEM8(0x04FB) - -/* PORT - I/O Ports */ -#define PORTA_DIR _SFR_MEM8(0x0600) -#define PORTA_DIRSET _SFR_MEM8(0x0601) -#define PORTA_DIRCLR _SFR_MEM8(0x0602) -#define PORTA_DIRTGL _SFR_MEM8(0x0603) -#define PORTA_OUT _SFR_MEM8(0x0604) -#define PORTA_OUTSET _SFR_MEM8(0x0605) -#define PORTA_OUTCLR _SFR_MEM8(0x0606) -#define PORTA_OUTTGL _SFR_MEM8(0x0607) -#define PORTA_IN _SFR_MEM8(0x0608) -#define PORTA_INTCTRL _SFR_MEM8(0x0609) -#define PORTA_INT0MASK _SFR_MEM8(0x060A) -#define PORTA_INT1MASK _SFR_MEM8(0x060B) -#define PORTA_INTFLAGS _SFR_MEM8(0x060C) -#define PORTA_REMAP _SFR_MEM8(0x060E) -#define PORTA_PIN0CTRL _SFR_MEM8(0x0610) -#define PORTA_PIN1CTRL _SFR_MEM8(0x0611) -#define PORTA_PIN2CTRL _SFR_MEM8(0x0612) -#define PORTA_PIN3CTRL _SFR_MEM8(0x0613) -#define PORTA_PIN4CTRL _SFR_MEM8(0x0614) -#define PORTA_PIN5CTRL _SFR_MEM8(0x0615) -#define PORTA_PIN6CTRL _SFR_MEM8(0x0616) -#define PORTA_PIN7CTRL _SFR_MEM8(0x0617) - -/* PORT - I/O Ports */ -#define PORTB_DIR _SFR_MEM8(0x0620) -#define PORTB_DIRSET _SFR_MEM8(0x0621) -#define PORTB_DIRCLR _SFR_MEM8(0x0622) -#define PORTB_DIRTGL _SFR_MEM8(0x0623) -#define PORTB_OUT _SFR_MEM8(0x0624) -#define PORTB_OUTSET _SFR_MEM8(0x0625) -#define PORTB_OUTCLR _SFR_MEM8(0x0626) -#define PORTB_OUTTGL _SFR_MEM8(0x0627) -#define PORTB_IN _SFR_MEM8(0x0628) -#define PORTB_INTCTRL _SFR_MEM8(0x0629) -#define PORTB_INT0MASK _SFR_MEM8(0x062A) -#define PORTB_INT1MASK _SFR_MEM8(0x062B) -#define PORTB_INTFLAGS _SFR_MEM8(0x062C) -#define PORTB_REMAP _SFR_MEM8(0x062E) -#define PORTB_PIN0CTRL _SFR_MEM8(0x0630) -#define PORTB_PIN1CTRL _SFR_MEM8(0x0631) -#define PORTB_PIN2CTRL _SFR_MEM8(0x0632) -#define PORTB_PIN3CTRL _SFR_MEM8(0x0633) -#define PORTB_PIN4CTRL _SFR_MEM8(0x0634) -#define PORTB_PIN5CTRL _SFR_MEM8(0x0635) -#define PORTB_PIN6CTRL _SFR_MEM8(0x0636) -#define PORTB_PIN7CTRL _SFR_MEM8(0x0637) - -/* PORT - I/O Ports */ -#define PORTC_DIR _SFR_MEM8(0x0640) -#define PORTC_DIRSET _SFR_MEM8(0x0641) -#define PORTC_DIRCLR _SFR_MEM8(0x0642) -#define PORTC_DIRTGL _SFR_MEM8(0x0643) -#define PORTC_OUT _SFR_MEM8(0x0644) -#define PORTC_OUTSET _SFR_MEM8(0x0645) -#define PORTC_OUTCLR _SFR_MEM8(0x0646) -#define PORTC_OUTTGL _SFR_MEM8(0x0647) -#define PORTC_IN _SFR_MEM8(0x0648) -#define PORTC_INTCTRL _SFR_MEM8(0x0649) -#define PORTC_INT0MASK _SFR_MEM8(0x064A) -#define PORTC_INT1MASK _SFR_MEM8(0x064B) -#define PORTC_INTFLAGS _SFR_MEM8(0x064C) -#define PORTC_REMAP _SFR_MEM8(0x064E) -#define PORTC_PIN0CTRL _SFR_MEM8(0x0650) -#define PORTC_PIN1CTRL _SFR_MEM8(0x0651) -#define PORTC_PIN2CTRL _SFR_MEM8(0x0652) -#define PORTC_PIN3CTRL _SFR_MEM8(0x0653) -#define PORTC_PIN4CTRL _SFR_MEM8(0x0654) -#define PORTC_PIN5CTRL _SFR_MEM8(0x0655) -#define PORTC_PIN6CTRL _SFR_MEM8(0x0656) -#define PORTC_PIN7CTRL _SFR_MEM8(0x0657) - -/* PORT - I/O Ports */ -#define PORTD_DIR _SFR_MEM8(0x0660) -#define PORTD_DIRSET _SFR_MEM8(0x0661) -#define PORTD_DIRCLR _SFR_MEM8(0x0662) -#define PORTD_DIRTGL _SFR_MEM8(0x0663) -#define PORTD_OUT _SFR_MEM8(0x0664) -#define PORTD_OUTSET _SFR_MEM8(0x0665) -#define PORTD_OUTCLR _SFR_MEM8(0x0666) -#define PORTD_OUTTGL _SFR_MEM8(0x0667) -#define PORTD_IN _SFR_MEM8(0x0668) -#define PORTD_INTCTRL _SFR_MEM8(0x0669) -#define PORTD_INT0MASK _SFR_MEM8(0x066A) -#define PORTD_INT1MASK _SFR_MEM8(0x066B) -#define PORTD_INTFLAGS _SFR_MEM8(0x066C) -#define PORTD_REMAP _SFR_MEM8(0x066E) -#define PORTD_PIN0CTRL _SFR_MEM8(0x0670) -#define PORTD_PIN1CTRL _SFR_MEM8(0x0671) -#define PORTD_PIN2CTRL _SFR_MEM8(0x0672) -#define PORTD_PIN3CTRL _SFR_MEM8(0x0673) -#define PORTD_PIN4CTRL _SFR_MEM8(0x0674) -#define PORTD_PIN5CTRL _SFR_MEM8(0x0675) -#define PORTD_PIN6CTRL _SFR_MEM8(0x0676) -#define PORTD_PIN7CTRL _SFR_MEM8(0x0677) - -/* PORT - I/O Ports */ -#define PORTE_DIR _SFR_MEM8(0x0680) -#define PORTE_DIRSET _SFR_MEM8(0x0681) -#define PORTE_DIRCLR _SFR_MEM8(0x0682) -#define PORTE_DIRTGL _SFR_MEM8(0x0683) -#define PORTE_OUT _SFR_MEM8(0x0684) -#define PORTE_OUTSET _SFR_MEM8(0x0685) -#define PORTE_OUTCLR _SFR_MEM8(0x0686) -#define PORTE_OUTTGL _SFR_MEM8(0x0687) -#define PORTE_IN _SFR_MEM8(0x0688) -#define PORTE_INTCTRL _SFR_MEM8(0x0689) -#define PORTE_INT0MASK _SFR_MEM8(0x068A) -#define PORTE_INT1MASK _SFR_MEM8(0x068B) -#define PORTE_INTFLAGS _SFR_MEM8(0x068C) -#define PORTE_REMAP _SFR_MEM8(0x068E) -#define PORTE_PIN0CTRL _SFR_MEM8(0x0690) -#define PORTE_PIN1CTRL _SFR_MEM8(0x0691) -#define PORTE_PIN2CTRL _SFR_MEM8(0x0692) -#define PORTE_PIN3CTRL _SFR_MEM8(0x0693) -#define PORTE_PIN4CTRL _SFR_MEM8(0x0694) -#define PORTE_PIN5CTRL _SFR_MEM8(0x0695) -#define PORTE_PIN6CTRL _SFR_MEM8(0x0696) -#define PORTE_PIN7CTRL _SFR_MEM8(0x0697) - -/* PORT - I/O Ports */ -#define PORTF_DIR _SFR_MEM8(0x06A0) -#define PORTF_DIRSET _SFR_MEM8(0x06A1) -#define PORTF_DIRCLR _SFR_MEM8(0x06A2) -#define PORTF_DIRTGL _SFR_MEM8(0x06A3) -#define PORTF_OUT _SFR_MEM8(0x06A4) -#define PORTF_OUTSET _SFR_MEM8(0x06A5) -#define PORTF_OUTCLR _SFR_MEM8(0x06A6) -#define PORTF_OUTTGL _SFR_MEM8(0x06A7) -#define PORTF_IN _SFR_MEM8(0x06A8) -#define PORTF_INTCTRL _SFR_MEM8(0x06A9) -#define PORTF_INT0MASK _SFR_MEM8(0x06AA) -#define PORTF_INT1MASK _SFR_MEM8(0x06AB) -#define PORTF_INTFLAGS _SFR_MEM8(0x06AC) -#define PORTF_REMAP _SFR_MEM8(0x06AE) -#define PORTF_PIN0CTRL _SFR_MEM8(0x06B0) -#define PORTF_PIN1CTRL _SFR_MEM8(0x06B1) -#define PORTF_PIN2CTRL _SFR_MEM8(0x06B2) -#define PORTF_PIN3CTRL _SFR_MEM8(0x06B3) -#define PORTF_PIN4CTRL _SFR_MEM8(0x06B4) -#define PORTF_PIN5CTRL _SFR_MEM8(0x06B5) -#define PORTF_PIN6CTRL _SFR_MEM8(0x06B6) -#define PORTF_PIN7CTRL _SFR_MEM8(0x06B7) - -/* PORT - I/O Ports */ -#define PORTR_DIR _SFR_MEM8(0x07E0) -#define PORTR_DIRSET _SFR_MEM8(0x07E1) -#define PORTR_DIRCLR _SFR_MEM8(0x07E2) -#define PORTR_DIRTGL _SFR_MEM8(0x07E3) -#define PORTR_OUT _SFR_MEM8(0x07E4) -#define PORTR_OUTSET _SFR_MEM8(0x07E5) -#define PORTR_OUTCLR _SFR_MEM8(0x07E6) -#define PORTR_OUTTGL _SFR_MEM8(0x07E7) -#define PORTR_IN _SFR_MEM8(0x07E8) -#define PORTR_INTCTRL _SFR_MEM8(0x07E9) -#define PORTR_INT0MASK _SFR_MEM8(0x07EA) -#define PORTR_INT1MASK _SFR_MEM8(0x07EB) -#define PORTR_INTFLAGS _SFR_MEM8(0x07EC) -#define PORTR_REMAP _SFR_MEM8(0x07EE) -#define PORTR_PIN0CTRL _SFR_MEM8(0x07F0) -#define PORTR_PIN1CTRL _SFR_MEM8(0x07F1) -#define PORTR_PIN2CTRL _SFR_MEM8(0x07F2) -#define PORTR_PIN3CTRL _SFR_MEM8(0x07F3) -#define PORTR_PIN4CTRL _SFR_MEM8(0x07F4) -#define PORTR_PIN5CTRL _SFR_MEM8(0x07F5) -#define PORTR_PIN6CTRL _SFR_MEM8(0x07F6) -#define PORTR_PIN7CTRL _SFR_MEM8(0x07F7) - -/* TC0 - 16-bit Timer/Counter 0 */ -#define TCC0_CTRLA _SFR_MEM8(0x0800) -#define TCC0_CTRLB _SFR_MEM8(0x0801) -#define TCC0_CTRLC _SFR_MEM8(0x0802) -#define TCC0_CTRLD _SFR_MEM8(0x0803) -#define TCC0_CTRLE _SFR_MEM8(0x0804) -#define TCC0_INTCTRLA _SFR_MEM8(0x0806) -#define TCC0_INTCTRLB _SFR_MEM8(0x0807) -#define TCC0_CTRLFCLR _SFR_MEM8(0x0808) -#define TCC0_CTRLFSET _SFR_MEM8(0x0809) -#define TCC0_CTRLGCLR _SFR_MEM8(0x080A) -#define TCC0_CTRLGSET _SFR_MEM8(0x080B) -#define TCC0_INTFLAGS _SFR_MEM8(0x080C) -#define TCC0_TEMP _SFR_MEM8(0x080F) -#define TCC0_CNT _SFR_MEM16(0x0820) -#define TCC0_PER _SFR_MEM16(0x0826) -#define TCC0_CCA _SFR_MEM16(0x0828) -#define TCC0_CCB _SFR_MEM16(0x082A) -#define TCC0_CCC _SFR_MEM16(0x082C) -#define TCC0_CCD _SFR_MEM16(0x082E) -#define TCC0_PERBUF _SFR_MEM16(0x0836) -#define TCC0_CCABUF _SFR_MEM16(0x0838) -#define TCC0_CCBBUF _SFR_MEM16(0x083A) -#define TCC0_CCCBUF _SFR_MEM16(0x083C) -#define TCC0_CCDBUF _SFR_MEM16(0x083E) - -/* TC2 - 16-bit Timer/Counter type 2 */ -#define TCC2_CTRLA _SFR_MEM8(0x0800) -#define TCC2_CTRLB _SFR_MEM8(0x0801) -#define TCC2_CTRLC _SFR_MEM8(0x0802) -#define TCC2_CTRLE _SFR_MEM8(0x0804) -#define TCC2_INTCTRLA _SFR_MEM8(0x0806) -#define TCC2_INTCTRLB _SFR_MEM8(0x0807) -#define TCC2_CTRLF _SFR_MEM8(0x0809) -#define TCC2_INTFLAGS _SFR_MEM8(0x080C) -#define TCC2_LCNT _SFR_MEM8(0x0820) -#define TCC2_HCNT _SFR_MEM8(0x0821) -#define TCC2_LPER _SFR_MEM8(0x0826) -#define TCC2_HPER _SFR_MEM8(0x0827) -#define TCC2_LCMPA _SFR_MEM8(0x0828) -#define TCC2_HCMPA _SFR_MEM8(0x0829) -#define TCC2_LCMPB _SFR_MEM8(0x082A) -#define TCC2_HCMPB _SFR_MEM8(0x082B) -#define TCC2_LCMPC _SFR_MEM8(0x082C) -#define TCC2_HCMPC _SFR_MEM8(0x082D) -#define TCC2_LCMPD _SFR_MEM8(0x082E) -#define TCC2_HCMPD _SFR_MEM8(0x082F) - -/* TC1 - 16-bit Timer/Counter 1 */ -#define TCC1_CTRLA _SFR_MEM8(0x0840) -#define TCC1_CTRLB _SFR_MEM8(0x0841) -#define TCC1_CTRLC _SFR_MEM8(0x0842) -#define TCC1_CTRLD _SFR_MEM8(0x0843) -#define TCC1_CTRLE _SFR_MEM8(0x0844) -#define TCC1_INTCTRLA _SFR_MEM8(0x0846) -#define TCC1_INTCTRLB _SFR_MEM8(0x0847) -#define TCC1_CTRLFCLR _SFR_MEM8(0x0848) -#define TCC1_CTRLFSET _SFR_MEM8(0x0849) -#define TCC1_CTRLGCLR _SFR_MEM8(0x084A) -#define TCC1_CTRLGSET _SFR_MEM8(0x084B) -#define TCC1_INTFLAGS _SFR_MEM8(0x084C) -#define TCC1_TEMP _SFR_MEM8(0x084F) -#define TCC1_CNT _SFR_MEM16(0x0860) -#define TCC1_PER _SFR_MEM16(0x0866) -#define TCC1_CCA _SFR_MEM16(0x0868) -#define TCC1_CCB _SFR_MEM16(0x086A) -#define TCC1_PERBUF _SFR_MEM16(0x0876) -#define TCC1_CCABUF _SFR_MEM16(0x0878) -#define TCC1_CCBBUF _SFR_MEM16(0x087A) - -/* AWEX - Advanced Waveform Extension */ -#define AWEXC_CTRL _SFR_MEM8(0x0880) -#define AWEXC_FDEMASK _SFR_MEM8(0x0882) -#define AWEXC_FDCTRL _SFR_MEM8(0x0883) -#define AWEXC_STATUS _SFR_MEM8(0x0884) -#define AWEXC_STATUSSET _SFR_MEM8(0x0885) -#define AWEXC_DTBOTH _SFR_MEM8(0x0886) -#define AWEXC_DTBOTHBUF _SFR_MEM8(0x0887) -#define AWEXC_DTLS _SFR_MEM8(0x0888) -#define AWEXC_DTHS _SFR_MEM8(0x0889) -#define AWEXC_DTLSBUF _SFR_MEM8(0x088A) -#define AWEXC_DTHSBUF _SFR_MEM8(0x088B) -#define AWEXC_OUTOVEN _SFR_MEM8(0x088C) - -/* HIRES - High-Resolution Extension */ -#define HIRESC_CTRLA _SFR_MEM8(0x0890) - -/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ -#define USARTC0_DATA _SFR_MEM8(0x08A0) -#define USARTC0_STATUS _SFR_MEM8(0x08A1) -#define USARTC0_CTRLA _SFR_MEM8(0x08A3) -#define USARTC0_CTRLB _SFR_MEM8(0x08A4) -#define USARTC0_CTRLC _SFR_MEM8(0x08A5) -#define USARTC0_BAUDCTRLA _SFR_MEM8(0x08A6) -#define USARTC0_BAUDCTRLB _SFR_MEM8(0x08A7) - -/* SPI - Serial Peripheral Interface */ -#define SPIC_CTRL _SFR_MEM8(0x08C0) -#define SPIC_INTCTRL _SFR_MEM8(0x08C1) -#define SPIC_STATUS _SFR_MEM8(0x08C2) -#define SPIC_DATA _SFR_MEM8(0x08C3) - -/* IRCOM - IR Communication Module */ -#define IRCOM_CTRL _SFR_MEM8(0x08F8) -#define IRCOM_TXPLCTRL _SFR_MEM8(0x08F9) -#define IRCOM_RXPLCTRL _SFR_MEM8(0x08FA) - -/* TC0 - 16-bit Timer/Counter 0 */ -#define TCD0_CTRLA _SFR_MEM8(0x0900) -#define TCD0_CTRLB _SFR_MEM8(0x0901) -#define TCD0_CTRLC _SFR_MEM8(0x0902) -#define TCD0_CTRLD _SFR_MEM8(0x0903) -#define TCD0_CTRLE _SFR_MEM8(0x0904) -#define TCD0_INTCTRLA _SFR_MEM8(0x0906) -#define TCD0_INTCTRLB _SFR_MEM8(0x0907) -#define TCD0_CTRLFCLR _SFR_MEM8(0x0908) -#define TCD0_CTRLFSET _SFR_MEM8(0x0909) -#define TCD0_CTRLGCLR _SFR_MEM8(0x090A) -#define TCD0_CTRLGSET _SFR_MEM8(0x090B) -#define TCD0_INTFLAGS _SFR_MEM8(0x090C) -#define TCD0_TEMP _SFR_MEM8(0x090F) -#define TCD0_CNT _SFR_MEM16(0x0920) -#define TCD0_PER _SFR_MEM16(0x0926) -#define TCD0_CCA _SFR_MEM16(0x0928) -#define TCD0_CCB _SFR_MEM16(0x092A) -#define TCD0_CCC _SFR_MEM16(0x092C) -#define TCD0_CCD _SFR_MEM16(0x092E) -#define TCD0_PERBUF _SFR_MEM16(0x0936) -#define TCD0_CCABUF _SFR_MEM16(0x0938) -#define TCD0_CCBBUF _SFR_MEM16(0x093A) -#define TCD0_CCCBUF _SFR_MEM16(0x093C) -#define TCD0_CCDBUF _SFR_MEM16(0x093E) - -/* TC2 - 16-bit Timer/Counter type 2 */ -#define TCD2_CTRLA _SFR_MEM8(0x0900) -#define TCD2_CTRLB _SFR_MEM8(0x0901) -#define TCD2_CTRLC _SFR_MEM8(0x0902) -#define TCD2_CTRLE _SFR_MEM8(0x0904) -#define TCD2_INTCTRLA _SFR_MEM8(0x0906) -#define TCD2_INTCTRLB _SFR_MEM8(0x0907) -#define TCD2_CTRLF _SFR_MEM8(0x0909) -#define TCD2_INTFLAGS _SFR_MEM8(0x090C) -#define TCD2_LCNT _SFR_MEM8(0x0920) -#define TCD2_HCNT _SFR_MEM8(0x0921) -#define TCD2_LPER _SFR_MEM8(0x0926) -#define TCD2_HPER _SFR_MEM8(0x0927) -#define TCD2_LCMPA _SFR_MEM8(0x0928) -#define TCD2_HCMPA _SFR_MEM8(0x0929) -#define TCD2_LCMPB _SFR_MEM8(0x092A) -#define TCD2_HCMPB _SFR_MEM8(0x092B) -#define TCD2_LCMPC _SFR_MEM8(0x092C) -#define TCD2_HCMPC _SFR_MEM8(0x092D) -#define TCD2_LCMPD _SFR_MEM8(0x092E) -#define TCD2_HCMPD _SFR_MEM8(0x092F) - -/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ -#define USARTD0_DATA _SFR_MEM8(0x09A0) -#define USARTD0_STATUS _SFR_MEM8(0x09A1) -#define USARTD0_CTRLA _SFR_MEM8(0x09A3) -#define USARTD0_CTRLB _SFR_MEM8(0x09A4) -#define USARTD0_CTRLC _SFR_MEM8(0x09A5) -#define USARTD0_BAUDCTRLA _SFR_MEM8(0x09A6) -#define USARTD0_BAUDCTRLB _SFR_MEM8(0x09A7) - -/* SPI - Serial Peripheral Interface */ -#define SPID_CTRL _SFR_MEM8(0x09C0) -#define SPID_INTCTRL _SFR_MEM8(0x09C1) -#define SPID_STATUS _SFR_MEM8(0x09C2) -#define SPID_DATA _SFR_MEM8(0x09C3) - -/* TC0 - 16-bit Timer/Counter 0 */ -#define TCE0_CTRLA _SFR_MEM8(0x0A00) -#define TCE0_CTRLB _SFR_MEM8(0x0A01) -#define TCE0_CTRLC _SFR_MEM8(0x0A02) -#define TCE0_CTRLD _SFR_MEM8(0x0A03) -#define TCE0_CTRLE _SFR_MEM8(0x0A04) -#define TCE0_INTCTRLA _SFR_MEM8(0x0A06) -#define TCE0_INTCTRLB _SFR_MEM8(0x0A07) -#define TCE0_CTRLFCLR _SFR_MEM8(0x0A08) -#define TCE0_CTRLFSET _SFR_MEM8(0x0A09) -#define TCE0_CTRLGCLR _SFR_MEM8(0x0A0A) -#define TCE0_CTRLGSET _SFR_MEM8(0x0A0B) -#define TCE0_INTFLAGS _SFR_MEM8(0x0A0C) -#define TCE0_TEMP _SFR_MEM8(0x0A0F) -#define TCE0_CNT _SFR_MEM16(0x0A20) -#define TCE0_PER _SFR_MEM16(0x0A26) -#define TCE0_CCA _SFR_MEM16(0x0A28) -#define TCE0_CCB _SFR_MEM16(0x0A2A) -#define TCE0_CCC _SFR_MEM16(0x0A2C) -#define TCE0_CCD _SFR_MEM16(0x0A2E) -#define TCE0_PERBUF _SFR_MEM16(0x0A36) -#define TCE0_CCABUF _SFR_MEM16(0x0A38) -#define TCE0_CCBBUF _SFR_MEM16(0x0A3A) -#define TCE0_CCCBUF _SFR_MEM16(0x0A3C) -#define TCE0_CCDBUF _SFR_MEM16(0x0A3E) - -/* TC2 - 16-bit Timer/Counter type 2 */ -#define TCE2_CTRLA _SFR_MEM8(0x0A00) -#define TCE2_CTRLB _SFR_MEM8(0x0A01) -#define TCE2_CTRLC _SFR_MEM8(0x0A02) -#define TCE2_CTRLE _SFR_MEM8(0x0A04) -#define TCE2_INTCTRLA _SFR_MEM8(0x0A06) -#define TCE2_INTCTRLB _SFR_MEM8(0x0A07) -#define TCE2_CTRLF _SFR_MEM8(0x0A09) -#define TCE2_INTFLAGS _SFR_MEM8(0x0A0C) -#define TCE2_LCNT _SFR_MEM8(0x0A20) -#define TCE2_HCNT _SFR_MEM8(0x0A21) -#define TCE2_LPER _SFR_MEM8(0x0A26) -#define TCE2_HPER _SFR_MEM8(0x0A27) -#define TCE2_LCMPA _SFR_MEM8(0x0A28) -#define TCE2_HCMPA _SFR_MEM8(0x0A29) -#define TCE2_LCMPB _SFR_MEM8(0x0A2A) -#define TCE2_HCMPB _SFR_MEM8(0x0A2B) -#define TCE2_LCMPC _SFR_MEM8(0x0A2C) -#define TCE2_HCMPC _SFR_MEM8(0x0A2D) -#define TCE2_LCMPD _SFR_MEM8(0x0A2E) -#define TCE2_HCMPD _SFR_MEM8(0x0A2F) - -/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ -#define USARTE0_DATA _SFR_MEM8(0x0AA0) -#define USARTE0_STATUS _SFR_MEM8(0x0AA1) -#define USARTE0_CTRLA _SFR_MEM8(0x0AA3) -#define USARTE0_CTRLB _SFR_MEM8(0x0AA4) -#define USARTE0_CTRLC _SFR_MEM8(0x0AA5) -#define USARTE0_BAUDCTRLA _SFR_MEM8(0x0AA6) -#define USARTE0_BAUDCTRLB _SFR_MEM8(0x0AA7) - -/* TC0 - 16-bit Timer/Counter 0 */ -#define TCF0_CTRLA _SFR_MEM8(0x0B00) -#define TCF0_CTRLB _SFR_MEM8(0x0B01) -#define TCF0_CTRLC _SFR_MEM8(0x0B02) -#define TCF0_CTRLD _SFR_MEM8(0x0B03) -#define TCF0_CTRLE _SFR_MEM8(0x0B04) -#define TCF0_INTCTRLA _SFR_MEM8(0x0B06) -#define TCF0_INTCTRLB _SFR_MEM8(0x0B07) -#define TCF0_CTRLFCLR _SFR_MEM8(0x0B08) -#define TCF0_CTRLFSET _SFR_MEM8(0x0B09) -#define TCF0_CTRLGCLR _SFR_MEM8(0x0B0A) -#define TCF0_CTRLGSET _SFR_MEM8(0x0B0B) -#define TCF0_INTFLAGS _SFR_MEM8(0x0B0C) -#define TCF0_TEMP _SFR_MEM8(0x0B0F) -#define TCF0_CNT _SFR_MEM16(0x0B20) -#define TCF0_PER _SFR_MEM16(0x0B26) -#define TCF0_CCA _SFR_MEM16(0x0B28) -#define TCF0_CCB _SFR_MEM16(0x0B2A) -#define TCF0_CCC _SFR_MEM16(0x0B2C) -#define TCF0_CCD _SFR_MEM16(0x0B2E) -#define TCF0_PERBUF _SFR_MEM16(0x0B36) -#define TCF0_CCABUF _SFR_MEM16(0x0B38) -#define TCF0_CCBBUF _SFR_MEM16(0x0B3A) -#define TCF0_CCCBUF _SFR_MEM16(0x0B3C) -#define TCF0_CCDBUF _SFR_MEM16(0x0B3E) - -/* TC2 - 16-bit Timer/Counter type 2 */ -#define TCF2_CTRLA _SFR_MEM8(0x0B00) -#define TCF2_CTRLB _SFR_MEM8(0x0B01) -#define TCF2_CTRLC _SFR_MEM8(0x0B02) -#define TCF2_CTRLE _SFR_MEM8(0x0B04) -#define TCF2_INTCTRLA _SFR_MEM8(0x0B06) -#define TCF2_INTCTRLB _SFR_MEM8(0x0B07) -#define TCF2_CTRLF _SFR_MEM8(0x0B09) -#define TCF2_INTFLAGS _SFR_MEM8(0x0B0C) -#define TCF2_LCNT _SFR_MEM8(0x0B20) -#define TCF2_HCNT _SFR_MEM8(0x0B21) -#define TCF2_LPER _SFR_MEM8(0x0B26) -#define TCF2_HPER _SFR_MEM8(0x0B27) -#define TCF2_LCMPA _SFR_MEM8(0x0B28) -#define TCF2_HCMPA _SFR_MEM8(0x0B29) -#define TCF2_LCMPB _SFR_MEM8(0x0B2A) -#define TCF2_HCMPB _SFR_MEM8(0x0B2B) -#define TCF2_LCMPC _SFR_MEM8(0x0B2C) -#define TCF2_HCMPC _SFR_MEM8(0x0B2D) -#define TCF2_LCMPD _SFR_MEM8(0x0B2E) -#define TCF2_HCMPD _SFR_MEM8(0x0B2F) - - - -/*================== Bitfield Definitions ================== */ - -/* VPORT - Virtual Ports */ -/* VPORT.INTFLAGS bit masks and bit positions */ -#define VPORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ -#define VPORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ - -#define VPORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ -#define VPORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ - -/* XOCD - On-Chip Debug System */ -/* OCD.OCDR0 bit masks and bit positions */ -#define OCD_OCDRD_gm 0xFF /* OCDR Dirty group mask. */ -#define OCD_OCDRD_gp 0 /* OCDR Dirty group position. */ -#define OCD_OCDRD0_bm (1<<0) /* OCDR Dirty bit 0 mask. */ -#define OCD_OCDRD0_bp 0 /* OCDR Dirty bit 0 position. */ -#define OCD_OCDRD1_bm (1<<1) /* OCDR Dirty bit 1 mask. */ -#define OCD_OCDRD1_bp 1 /* OCDR Dirty bit 1 position. */ -#define OCD_OCDRD2_bm (1<<2) /* OCDR Dirty bit 2 mask. */ -#define OCD_OCDRD2_bp 2 /* OCDR Dirty bit 2 position. */ -#define OCD_OCDRD3_bm (1<<3) /* OCDR Dirty bit 3 mask. */ -#define OCD_OCDRD3_bp 3 /* OCDR Dirty bit 3 position. */ -#define OCD_OCDRD4_bm (1<<4) /* OCDR Dirty bit 4 mask. */ -#define OCD_OCDRD4_bp 4 /* OCDR Dirty bit 4 position. */ -#define OCD_OCDRD5_bm (1<<5) /* OCDR Dirty bit 5 mask. */ -#define OCD_OCDRD5_bp 5 /* OCDR Dirty bit 5 position. */ -#define OCD_OCDRD6_bm (1<<6) /* OCDR Dirty bit 6 mask. */ -#define OCD_OCDRD6_bp 6 /* OCDR Dirty bit 6 position. */ -#define OCD_OCDRD7_bm (1<<7) /* OCDR Dirty bit 7 mask. */ -#define OCD_OCDRD7_bp 7 /* OCDR Dirty bit 7 position. */ - -/* OCD.OCDR1 bit masks and bit positions */ -/* OCD_OCDRD Predefined. */ -/* OCD_OCDRD Predefined. */ - -/* CPU - CPU */ -/* CPU.CCP bit masks and bit positions */ -#define CPU_CCP_gm 0xFF /* CCP signature group mask. */ -#define CPU_CCP_gp 0 /* CCP signature group position. */ -#define CPU_CCP0_bm (1<<0) /* CCP signature bit 0 mask. */ -#define CPU_CCP0_bp 0 /* CCP signature bit 0 position. */ -#define CPU_CCP1_bm (1<<1) /* CCP signature bit 1 mask. */ -#define CPU_CCP1_bp 1 /* CCP signature bit 1 position. */ -#define CPU_CCP2_bm (1<<2) /* CCP signature bit 2 mask. */ -#define CPU_CCP2_bp 2 /* CCP signature bit 2 position. */ -#define CPU_CCP3_bm (1<<3) /* CCP signature bit 3 mask. */ -#define CPU_CCP3_bp 3 /* CCP signature bit 3 position. */ -#define CPU_CCP4_bm (1<<4) /* CCP signature bit 4 mask. */ -#define CPU_CCP4_bp 4 /* CCP signature bit 4 position. */ -#define CPU_CCP5_bm (1<<5) /* CCP signature bit 5 mask. */ -#define CPU_CCP5_bp 5 /* CCP signature bit 5 position. */ -#define CPU_CCP6_bm (1<<6) /* CCP signature bit 6 mask. */ -#define CPU_CCP6_bp 6 /* CCP signature bit 6 position. */ -#define CPU_CCP7_bm (1<<7) /* CCP signature bit 7 mask. */ -#define CPU_CCP7_bp 7 /* CCP signature bit 7 position. */ - -/* CPU.SREG bit masks and bit positions */ -#define CPU_I_bm 0x80 /* Global Interrupt Enable Flag bit mask. */ -#define CPU_I_bp 7 /* Global Interrupt Enable Flag bit position. */ - -#define CPU_T_bm 0x40 /* Transfer Bit bit mask. */ -#define CPU_T_bp 6 /* Transfer Bit bit position. */ - -#define CPU_H_bm 0x20 /* Half Carry Flag bit mask. */ -#define CPU_H_bp 5 /* Half Carry Flag bit position. */ - -#define CPU_S_bm 0x10 /* N Exclusive Or V Flag bit mask. */ -#define CPU_S_bp 4 /* N Exclusive Or V Flag bit position. */ - -#define CPU_V_bm 0x08 /* Two's Complement Overflow Flag bit mask. */ -#define CPU_V_bp 3 /* Two's Complement Overflow Flag bit position. */ - -#define CPU_N_bm 0x04 /* Negative Flag bit mask. */ -#define CPU_N_bp 2 /* Negative Flag bit position. */ - -#define CPU_Z_bm 0x02 /* Zero Flag bit mask. */ -#define CPU_Z_bp 1 /* Zero Flag bit position. */ - -#define CPU_C_bm 0x01 /* Carry Flag bit mask. */ -#define CPU_C_bp 0 /* Carry Flag bit position. */ - -/* CLK - Clock System */ -/* CLK.CTRL bit masks and bit positions */ -#define CLK_SCLKSEL_gm 0x07 /* System Clock Selection group mask. */ -#define CLK_SCLKSEL_gp 0 /* System Clock Selection group position. */ -#define CLK_SCLKSEL0_bm (1<<0) /* System Clock Selection bit 0 mask. */ -#define CLK_SCLKSEL0_bp 0 /* System Clock Selection bit 0 position. */ -#define CLK_SCLKSEL1_bm (1<<1) /* System Clock Selection bit 1 mask. */ -#define CLK_SCLKSEL1_bp 1 /* System Clock Selection bit 1 position. */ -#define CLK_SCLKSEL2_bm (1<<2) /* System Clock Selection bit 2 mask. */ -#define CLK_SCLKSEL2_bp 2 /* System Clock Selection bit 2 position. */ - -/* CLK.PSCTRL bit masks and bit positions */ -#define CLK_PSADIV_gm 0x7C /* Prescaler A Division Factor group mask. */ -#define CLK_PSADIV_gp 2 /* Prescaler A Division Factor group position. */ -#define CLK_PSADIV0_bm (1<<2) /* Prescaler A Division Factor bit 0 mask. */ -#define CLK_PSADIV0_bp 2 /* Prescaler A Division Factor bit 0 position. */ -#define CLK_PSADIV1_bm (1<<3) /* Prescaler A Division Factor bit 1 mask. */ -#define CLK_PSADIV1_bp 3 /* Prescaler A Division Factor bit 1 position. */ -#define CLK_PSADIV2_bm (1<<4) /* Prescaler A Division Factor bit 2 mask. */ -#define CLK_PSADIV2_bp 4 /* Prescaler A Division Factor bit 2 position. */ -#define CLK_PSADIV3_bm (1<<5) /* Prescaler A Division Factor bit 3 mask. */ -#define CLK_PSADIV3_bp 5 /* Prescaler A Division Factor bit 3 position. */ -#define CLK_PSADIV4_bm (1<<6) /* Prescaler A Division Factor bit 4 mask. */ -#define CLK_PSADIV4_bp 6 /* Prescaler A Division Factor bit 4 position. */ - -#define CLK_PSBCDIV_gm 0x03 /* Prescaler B and C Division factor group mask. */ -#define CLK_PSBCDIV_gp 0 /* Prescaler B and C Division factor group position. */ -#define CLK_PSBCDIV0_bm (1<<0) /* Prescaler B and C Division factor bit 0 mask. */ -#define CLK_PSBCDIV0_bp 0 /* Prescaler B and C Division factor bit 0 position. */ -#define CLK_PSBCDIV1_bm (1<<1) /* Prescaler B and C Division factor bit 1 mask. */ -#define CLK_PSBCDIV1_bp 1 /* Prescaler B and C Division factor bit 1 position. */ - -/* CLK.LOCK bit masks and bit positions */ -#define CLK_LOCK_bm 0x01 /* Clock System Lock bit mask. */ -#define CLK_LOCK_bp 0 /* Clock System Lock bit position. */ - -/* CLK.RTCCTRL bit masks and bit positions */ -#define CLK_RTCSRC_gm 0x0E /* Clock Source group mask. */ -#define CLK_RTCSRC_gp 1 /* Clock Source group position. */ -#define CLK_RTCSRC0_bm (1<<1) /* Clock Source bit 0 mask. */ -#define CLK_RTCSRC0_bp 1 /* Clock Source bit 0 position. */ -#define CLK_RTCSRC1_bm (1<<2) /* Clock Source bit 1 mask. */ -#define CLK_RTCSRC1_bp 2 /* Clock Source bit 1 position. */ -#define CLK_RTCSRC2_bm (1<<3) /* Clock Source bit 2 mask. */ -#define CLK_RTCSRC2_bp 3 /* Clock Source bit 2 position. */ - -#define CLK_RTCEN_bm 0x01 /* Clock Source Enable bit mask. */ -#define CLK_RTCEN_bp 0 /* Clock Source Enable bit position. */ - -/* CLK.USBCTRL bit masks and bit positions */ -#define CLK_USBPSDIV_gm 0x38 /* Prescaler Division Factor group mask. */ -#define CLK_USBPSDIV_gp 3 /* Prescaler Division Factor group position. */ -#define CLK_USBPSDIV0_bm (1<<3) /* Prescaler Division Factor bit 0 mask. */ -#define CLK_USBPSDIV0_bp 3 /* Prescaler Division Factor bit 0 position. */ -#define CLK_USBPSDIV1_bm (1<<4) /* Prescaler Division Factor bit 1 mask. */ -#define CLK_USBPSDIV1_bp 4 /* Prescaler Division Factor bit 1 position. */ -#define CLK_USBPSDIV2_bm (1<<5) /* Prescaler Division Factor bit 2 mask. */ -#define CLK_USBPSDIV2_bp 5 /* Prescaler Division Factor bit 2 position. */ - -#define CLK_USBSRC_gm 0x06 /* Clock Source group mask. */ -#define CLK_USBSRC_gp 1 /* Clock Source group position. */ -#define CLK_USBSRC0_bm (1<<1) /* Clock Source bit 0 mask. */ -#define CLK_USBSRC0_bp 1 /* Clock Source bit 0 position. */ -#define CLK_USBSRC1_bm (1<<2) /* Clock Source bit 1 mask. */ -#define CLK_USBSRC1_bp 2 /* Clock Source bit 1 position. */ - -#define CLK_USBSEN_bm 0x01 /* Clock Source Enable bit mask. */ -#define CLK_USBSEN_bp 0 /* Clock Source Enable bit position. */ - -/* PR.PRGEN bit masks and bit positions */ -#define PR_USB_bm 0x40 /* USB bit mask. */ -#define PR_USB_bp 6 /* USB bit position. */ - -#define PR_AES_bm 0x10 /* AES bit mask. */ -#define PR_AES_bp 4 /* AES bit position. */ - -#define PR_RTC_bm 0x04 /* Real-time Counter bit mask. */ -#define PR_RTC_bp 2 /* Real-time Counter bit position. */ - -#define PR_EVSYS_bm 0x02 /* Event System bit mask. */ -#define PR_EVSYS_bp 1 /* Event System bit position. */ - -#define PR_DMA_bm 0x01 /* DMA-Controller bit mask. */ -#define PR_DMA_bp 0 /* DMA-Controller bit position. */ - -/* PR.PRPA bit masks and bit positions */ -#define PR_ADC_bm 0x02 /* Port A ADC bit mask. */ -#define PR_ADC_bp 1 /* Port A ADC bit position. */ - -#define PR_AC_bm 0x01 /* Port A Analog Comparator bit mask. */ -#define PR_AC_bp 0 /* Port A Analog Comparator bit position. */ - -/* PR.PRPC bit masks and bit positions */ -#define PR_TWI_bm 0x40 /* Port C Two-wire Interface bit mask. */ -#define PR_TWI_bp 6 /* Port C Two-wire Interface bit position. */ - -#define PR_USART1_bm 0x20 /* Port C USART1 bit mask. */ -#define PR_USART1_bp 5 /* Port C USART1 bit position. */ - -#define PR_USART0_bm 0x10 /* Port C USART0 bit mask. */ -#define PR_USART0_bp 4 /* Port C USART0 bit position. */ - -#define PR_SPI_bm 0x08 /* Port C SPI bit mask. */ -#define PR_SPI_bp 3 /* Port C SPI bit position. */ - -#define PR_HIRES_bm 0x04 /* Port C AWEX bit mask. */ -#define PR_HIRES_bp 2 /* Port C AWEX bit position. */ - -#define PR_TC1_bm 0x02 /* Port C Timer/Counter1 bit mask. */ -#define PR_TC1_bp 1 /* Port C Timer/Counter1 bit position. */ - -#define PR_TC0_bm 0x01 /* Port C Timer/Counter0 bit mask. */ -#define PR_TC0_bp 0 /* Port C Timer/Counter0 bit position. */ - -/* PR.PRPD bit masks and bit positions */ -/* PR_USART0 Predefined. */ -/* PR_USART0 Predefined. */ - -/* PR_SPI Predefined. */ -/* PR_SPI Predefined. */ - -/* PR_TC0 Predefined. */ -/* PR_TC0 Predefined. */ - -/* PR.PRPE bit masks and bit positions */ -/* PR_TWI Predefined. */ -/* PR_TWI Predefined. */ - -/* PR_USART0 Predefined. */ -/* PR_USART0 Predefined. */ - -/* PR_TC0 Predefined. */ -/* PR_TC0 Predefined. */ - -/* PR.PRPF bit masks and bit positions */ -/* PR_USART0 Predefined. */ -/* PR_USART0 Predefined. */ - -/* PR_TC0 Predefined. */ -/* PR_TC0 Predefined. */ - -/* SLEEP - Sleep Controller */ -/* SLEEP.CTRL bit masks and bit positions */ -#define SLEEP_SMODE_gm 0x0E /* Sleep Mode group mask. */ -#define SLEEP_SMODE_gp 1 /* Sleep Mode group position. */ -#define SLEEP_SMODE0_bm (1<<1) /* Sleep Mode bit 0 mask. */ -#define SLEEP_SMODE0_bp 1 /* Sleep Mode bit 0 position. */ -#define SLEEP_SMODE1_bm (1<<2) /* Sleep Mode bit 1 mask. */ -#define SLEEP_SMODE1_bp 2 /* Sleep Mode bit 1 position. */ -#define SLEEP_SMODE2_bm (1<<3) /* Sleep Mode bit 2 mask. */ -#define SLEEP_SMODE2_bp 3 /* Sleep Mode bit 2 position. */ - -#define SLEEP_SEN_bm 0x01 /* Sleep Enable bit mask. */ -#define SLEEP_SEN_bp 0 /* Sleep Enable bit position. */ - -/* OSC - Oscillator */ -/* OSC.CTRL bit masks and bit positions */ -#define OSC_PLLEN_bm 0x10 /* PLL Enable bit mask. */ -#define OSC_PLLEN_bp 4 /* PLL Enable bit position. */ - -#define OSC_XOSCEN_bm 0x08 /* External Oscillator Enable bit mask. */ -#define OSC_XOSCEN_bp 3 /* External Oscillator Enable bit position. */ - -#define OSC_RC32KEN_bm 0x04 /* Internal 32.768 kHz RC Oscillator Enable bit mask. */ -#define OSC_RC32KEN_bp 2 /* Internal 32.768 kHz RC Oscillator Enable bit position. */ - -#define OSC_RC32MEN_bm 0x02 /* Internal 32 MHz RC Oscillator Enable bit mask. */ -#define OSC_RC32MEN_bp 1 /* Internal 32 MHz RC Oscillator Enable bit position. */ - -#define OSC_RC2MEN_bm 0x01 /* Internal 2 MHz RC Oscillator Enable bit mask. */ -#define OSC_RC2MEN_bp 0 /* Internal 2 MHz RC Oscillator Enable bit position. */ - -/* OSC.STATUS bit masks and bit positions */ -#define OSC_PLLRDY_bm 0x10 /* PLL Ready bit mask. */ -#define OSC_PLLRDY_bp 4 /* PLL Ready bit position. */ - -#define OSC_XOSCRDY_bm 0x08 /* External Oscillator Ready bit mask. */ -#define OSC_XOSCRDY_bp 3 /* External Oscillator Ready bit position. */ - -#define OSC_RC32KRDY_bm 0x04 /* Internal 32.768 kHz RC Oscillator Ready bit mask. */ -#define OSC_RC32KRDY_bp 2 /* Internal 32.768 kHz RC Oscillator Ready bit position. */ - -#define OSC_RC32MRDY_bm 0x02 /* Internal 32 MHz RC Oscillator Ready bit mask. */ -#define OSC_RC32MRDY_bp 1 /* Internal 32 MHz RC Oscillator Ready bit position. */ - -#define OSC_RC2MRDY_bm 0x01 /* Internal 2 MHz RC Oscillator Ready bit mask. */ -#define OSC_RC2MRDY_bp 0 /* Internal 2 MHz RC Oscillator Ready bit position. */ - -/* OSC.XOSCCTRL bit masks and bit positions */ -#define OSC_FRQRANGE_gm 0xC0 /* Frequency Range group mask. */ -#define OSC_FRQRANGE_gp 6 /* Frequency Range group position. */ -#define OSC_FRQRANGE0_bm (1<<6) /* Frequency Range bit 0 mask. */ -#define OSC_FRQRANGE0_bp 6 /* Frequency Range bit 0 position. */ -#define OSC_FRQRANGE1_bm (1<<7) /* Frequency Range bit 1 mask. */ -#define OSC_FRQRANGE1_bp 7 /* Frequency Range bit 1 position. */ - -#define OSC_X32KLPM_bm 0x20 /* 32.768 kHz XTAL OSC Low-power Mode bit mask. */ -#define OSC_X32KLPM_bp 5 /* 32.768 kHz XTAL OSC Low-power Mode bit position. */ - -#define OSC_XOSCPWR_bm 0x10 /* 16 MHz Crystal Oscillator High Power mode bit mask. */ -#define OSC_XOSCPWR_bp 4 /* 16 MHz Crystal Oscillator High Power mode bit position. */ - -#define OSC_XOSCSEL_gm 0x0F /* External Oscillator Selection and Startup Time group mask. */ -#define OSC_XOSCSEL_gp 0 /* External Oscillator Selection and Startup Time group position. */ -#define OSC_XOSCSEL0_bm (1<<0) /* External Oscillator Selection and Startup Time bit 0 mask. */ -#define OSC_XOSCSEL0_bp 0 /* External Oscillator Selection and Startup Time bit 0 position. */ -#define OSC_XOSCSEL1_bm (1<<1) /* External Oscillator Selection and Startup Time bit 1 mask. */ -#define OSC_XOSCSEL1_bp 1 /* External Oscillator Selection and Startup Time bit 1 position. */ -#define OSC_XOSCSEL2_bm (1<<2) /* External Oscillator Selection and Startup Time bit 2 mask. */ -#define OSC_XOSCSEL2_bp 2 /* External Oscillator Selection and Startup Time bit 2 position. */ -#define OSC_XOSCSEL3_bm (1<<3) /* External Oscillator Selection and Startup Time bit 3 mask. */ -#define OSC_XOSCSEL3_bp 3 /* External Oscillator Selection and Startup Time bit 3 position. */ - -/* OSC.XOSCFAIL bit masks and bit positions */ -#define OSC_PLLFDIF_bm 0x08 /* PLL Failure Detection Interrupt Flag bit mask. */ -#define OSC_PLLFDIF_bp 3 /* PLL Failure Detection Interrupt Flag bit position. */ - -#define OSC_PLLFDEN_bm 0x04 /* PLL Failure Detection Enable bit mask. */ -#define OSC_PLLFDEN_bp 2 /* PLL Failure Detection Enable bit position. */ - -#define OSC_XOSCFDIF_bm 0x02 /* XOSC Failure Detection Interrupt Flag bit mask. */ -#define OSC_XOSCFDIF_bp 1 /* XOSC Failure Detection Interrupt Flag bit position. */ - -#define OSC_XOSCFDEN_bm 0x01 /* XOSC Failure Detection Enable bit mask. */ -#define OSC_XOSCFDEN_bp 0 /* XOSC Failure Detection Enable bit position. */ - -/* OSC.PLLCTRL bit masks and bit positions */ -#define OSC_PLLSRC_gm 0xC0 /* Clock Source group mask. */ -#define OSC_PLLSRC_gp 6 /* Clock Source group position. */ -#define OSC_PLLSRC0_bm (1<<6) /* Clock Source bit 0 mask. */ -#define OSC_PLLSRC0_bp 6 /* Clock Source bit 0 position. */ -#define OSC_PLLSRC1_bm (1<<7) /* Clock Source bit 1 mask. */ -#define OSC_PLLSRC1_bp 7 /* Clock Source bit 1 position. */ - -#define OSC_PLLDIV_bm 0x20 /* Divide by 2 bit mask. */ -#define OSC_PLLDIV_bp 5 /* Divide by 2 bit position. */ - -#define OSC_PLLFAC_gm 0x1F /* Multiplication Factor group mask. */ -#define OSC_PLLFAC_gp 0 /* Multiplication Factor group position. */ -#define OSC_PLLFAC0_bm (1<<0) /* Multiplication Factor bit 0 mask. */ -#define OSC_PLLFAC0_bp 0 /* Multiplication Factor bit 0 position. */ -#define OSC_PLLFAC1_bm (1<<1) /* Multiplication Factor bit 1 mask. */ -#define OSC_PLLFAC1_bp 1 /* Multiplication Factor bit 1 position. */ -#define OSC_PLLFAC2_bm (1<<2) /* Multiplication Factor bit 2 mask. */ -#define OSC_PLLFAC2_bp 2 /* Multiplication Factor bit 2 position. */ -#define OSC_PLLFAC3_bm (1<<3) /* Multiplication Factor bit 3 mask. */ -#define OSC_PLLFAC3_bp 3 /* Multiplication Factor bit 3 position. */ -#define OSC_PLLFAC4_bm (1<<4) /* Multiplication Factor bit 4 mask. */ -#define OSC_PLLFAC4_bp 4 /* Multiplication Factor bit 4 position. */ - -/* OSC.DFLLCTRL bit masks and bit positions */ -#define OSC_RC32MCREF_gm 0x06 /* 32 MHz DFLL Calibration Reference group mask. */ -#define OSC_RC32MCREF_gp 1 /* 32 MHz DFLL Calibration Reference group position. */ -#define OSC_RC32MCREF0_bm (1<<1) /* 32 MHz DFLL Calibration Reference bit 0 mask. */ -#define OSC_RC32MCREF0_bp 1 /* 32 MHz DFLL Calibration Reference bit 0 position. */ -#define OSC_RC32MCREF1_bm (1<<2) /* 32 MHz DFLL Calibration Reference bit 1 mask. */ -#define OSC_RC32MCREF1_bp 2 /* 32 MHz DFLL Calibration Reference bit 1 position. */ - -#define OSC_RC2MCREF_bm 0x01 /* 2 MHz DFLL Calibration Reference bit mask. */ -#define OSC_RC2MCREF_bp 0 /* 2 MHz DFLL Calibration Reference bit position. */ - -/* DFLL - DFLL */ -/* DFLL.CTRL bit masks and bit positions */ -#define DFLL_ENABLE_bm 0x01 /* DFLL Enable bit mask. */ -#define DFLL_ENABLE_bp 0 /* DFLL Enable bit position. */ - -/* DFLL.CALA bit masks and bit positions */ -#define DFLL_CALL_gm 0x7F /* DFLL Calibration Value A group mask. */ -#define DFLL_CALL_gp 0 /* DFLL Calibration Value A group position. */ -#define DFLL_CALL0_bm (1<<0) /* DFLL Calibration Value A bit 0 mask. */ -#define DFLL_CALL0_bp 0 /* DFLL Calibration Value A bit 0 position. */ -#define DFLL_CALL1_bm (1<<1) /* DFLL Calibration Value A bit 1 mask. */ -#define DFLL_CALL1_bp 1 /* DFLL Calibration Value A bit 1 position. */ -#define DFLL_CALL2_bm (1<<2) /* DFLL Calibration Value A bit 2 mask. */ -#define DFLL_CALL2_bp 2 /* DFLL Calibration Value A bit 2 position. */ -#define DFLL_CALL3_bm (1<<3) /* DFLL Calibration Value A bit 3 mask. */ -#define DFLL_CALL3_bp 3 /* DFLL Calibration Value A bit 3 position. */ -#define DFLL_CALL4_bm (1<<4) /* DFLL Calibration Value A bit 4 mask. */ -#define DFLL_CALL4_bp 4 /* DFLL Calibration Value A bit 4 position. */ -#define DFLL_CALL5_bm (1<<5) /* DFLL Calibration Value A bit 5 mask. */ -#define DFLL_CALL5_bp 5 /* DFLL Calibration Value A bit 5 position. */ -#define DFLL_CALL6_bm (1<<6) /* DFLL Calibration Value A bit 6 mask. */ -#define DFLL_CALL6_bp 6 /* DFLL Calibration Value A bit 6 position. */ - -/* DFLL.CALB bit masks and bit positions */ -#define DFLL_CALH_gm 0x3F /* DFLL Calibration Value B group mask. */ -#define DFLL_CALH_gp 0 /* DFLL Calibration Value B group position. */ -#define DFLL_CALH0_bm (1<<0) /* DFLL Calibration Value B bit 0 mask. */ -#define DFLL_CALH0_bp 0 /* DFLL Calibration Value B bit 0 position. */ -#define DFLL_CALH1_bm (1<<1) /* DFLL Calibration Value B bit 1 mask. */ -#define DFLL_CALH1_bp 1 /* DFLL Calibration Value B bit 1 position. */ -#define DFLL_CALH2_bm (1<<2) /* DFLL Calibration Value B bit 2 mask. */ -#define DFLL_CALH2_bp 2 /* DFLL Calibration Value B bit 2 position. */ -#define DFLL_CALH3_bm (1<<3) /* DFLL Calibration Value B bit 3 mask. */ -#define DFLL_CALH3_bp 3 /* DFLL Calibration Value B bit 3 position. */ -#define DFLL_CALH4_bm (1<<4) /* DFLL Calibration Value B bit 4 mask. */ -#define DFLL_CALH4_bp 4 /* DFLL Calibration Value B bit 4 position. */ -#define DFLL_CALH5_bm (1<<5) /* DFLL Calibration Value B bit 5 mask. */ -#define DFLL_CALH5_bp 5 /* DFLL Calibration Value B bit 5 position. */ - -/* RST - Reset */ -/* RST.STATUS bit masks and bit positions */ -#define RST_SDRF_bm 0x40 /* Spike Detection Reset Flag bit mask. */ -#define RST_SDRF_bp 6 /* Spike Detection Reset Flag bit position. */ - -#define RST_SRF_bm 0x20 /* Software Reset Flag bit mask. */ -#define RST_SRF_bp 5 /* Software Reset Flag bit position. */ - -#define RST_PDIRF_bm 0x10 /* Programming and Debug Interface Interface Reset Flag bit mask. */ -#define RST_PDIRF_bp 4 /* Programming and Debug Interface Interface Reset Flag bit position. */ - -#define RST_WDRF_bm 0x08 /* Watchdog Reset Flag bit mask. */ -#define RST_WDRF_bp 3 /* Watchdog Reset Flag bit position. */ - -#define RST_BORF_bm 0x04 /* Brown-out Reset Flag bit mask. */ -#define RST_BORF_bp 2 /* Brown-out Reset Flag bit position. */ - -#define RST_EXTRF_bm 0x02 /* External Reset Flag bit mask. */ -#define RST_EXTRF_bp 1 /* External Reset Flag bit position. */ - -#define RST_PORF_bm 0x01 /* Power-on Reset Flag bit mask. */ -#define RST_PORF_bp 0 /* Power-on Reset Flag bit position. */ - -/* RST.CTRL bit masks and bit positions */ -#define RST_SWRST_bm 0x01 /* Software Reset bit mask. */ -#define RST_SWRST_bp 0 /* Software Reset bit position. */ - -/* WDT - Watch-Dog Timer */ -/* WDT.CTRL bit masks and bit positions */ -#define WDT_PER_gm 0x3C /* Period group mask. */ -#define WDT_PER_gp 2 /* Period group position. */ -#define WDT_PER0_bm (1<<2) /* Period bit 0 mask. */ -#define WDT_PER0_bp 2 /* Period bit 0 position. */ -#define WDT_PER1_bm (1<<3) /* Period bit 1 mask. */ -#define WDT_PER1_bp 3 /* Period bit 1 position. */ -#define WDT_PER2_bm (1<<4) /* Period bit 2 mask. */ -#define WDT_PER2_bp 4 /* Period bit 2 position. */ -#define WDT_PER3_bm (1<<5) /* Period bit 3 mask. */ -#define WDT_PER3_bp 5 /* Period bit 3 position. */ - -#define WDT_ENABLE_bm 0x02 /* Enable bit mask. */ -#define WDT_ENABLE_bp 1 /* Enable bit position. */ - -#define WDT_CEN_bm 0x01 /* Change Enable bit mask. */ -#define WDT_CEN_bp 0 /* Change Enable bit position. */ - -/* WDT.WINCTRL bit masks and bit positions */ -#define WDT_WPER_gm 0x3C /* Windowed Mode Period group mask. */ -#define WDT_WPER_gp 2 /* Windowed Mode Period group position. */ -#define WDT_WPER0_bm (1<<2) /* Windowed Mode Period bit 0 mask. */ -#define WDT_WPER0_bp 2 /* Windowed Mode Period bit 0 position. */ -#define WDT_WPER1_bm (1<<3) /* Windowed Mode Period bit 1 mask. */ -#define WDT_WPER1_bp 3 /* Windowed Mode Period bit 1 position. */ -#define WDT_WPER2_bm (1<<4) /* Windowed Mode Period bit 2 mask. */ -#define WDT_WPER2_bp 4 /* Windowed Mode Period bit 2 position. */ -#define WDT_WPER3_bm (1<<5) /* Windowed Mode Period bit 3 mask. */ -#define WDT_WPER3_bp 5 /* Windowed Mode Period bit 3 position. */ - -#define WDT_WEN_bm 0x02 /* Windowed Mode Enable bit mask. */ -#define WDT_WEN_bp 1 /* Windowed Mode Enable bit position. */ - -#define WDT_WCEN_bm 0x01 /* Windowed Mode Change Enable bit mask. */ -#define WDT_WCEN_bp 0 /* Windowed Mode Change Enable bit position. */ - -/* WDT.STATUS bit masks and bit positions */ -#define WDT_SYNCBUSY_bm 0x01 /* Syncronization busy bit mask. */ -#define WDT_SYNCBUSY_bp 0 /* Syncronization busy bit position. */ - -/* MCU - MCU Control */ -/* MCU.ANAINIT bit masks and bit positions */ -#define MCU_STARTUPDLYA_gm 0x03 /* Analog startup delay Port A group mask. */ -#define MCU_STARTUPDLYA_gp 0 /* Analog startup delay Port A group position. */ -#define MCU_STARTUPDLYA0_bm (1<<0) /* Analog startup delay Port A bit 0 mask. */ -#define MCU_STARTUPDLYA0_bp 0 /* Analog startup delay Port A bit 0 position. */ -#define MCU_STARTUPDLYA1_bm (1<<1) /* Analog startup delay Port A bit 1 mask. */ -#define MCU_STARTUPDLYA1_bp 1 /* Analog startup delay Port A bit 1 position. */ - -/* MCU.EVSYSLOCK bit masks and bit positions */ -#define MCU_EVSYS0LOCK_bm 0x01 /* Event Channel 0-3 Lock bit mask. */ -#define MCU_EVSYS0LOCK_bp 0 /* Event Channel 0-3 Lock bit position. */ - -/* MCU.AWEXLOCK bit masks and bit positions */ -#define MCU_AWEXCLOCK_bm 0x01 /* AWeX on T/C C0 Lock bit mask. */ -#define MCU_AWEXCLOCK_bp 0 /* AWeX on T/C C0 Lock bit position. */ - -/* PMIC - Programmable Multi-level Interrupt Controller */ -/* PMIC.STATUS bit masks and bit positions */ -#define PMIC_NMIEX_bm 0x80 /* Non-maskable Interrupt Executing bit mask. */ -#define PMIC_NMIEX_bp 7 /* Non-maskable Interrupt Executing bit position. */ - -#define PMIC_HILVLEX_bm 0x04 /* High Level Interrupt Executing bit mask. */ -#define PMIC_HILVLEX_bp 2 /* High Level Interrupt Executing bit position. */ - -#define PMIC_MEDLVLEX_bm 0x02 /* Medium Level Interrupt Executing bit mask. */ -#define PMIC_MEDLVLEX_bp 1 /* Medium Level Interrupt Executing bit position. */ - -#define PMIC_LOLVLEX_bm 0x01 /* Low Level Interrupt Executing bit mask. */ -#define PMIC_LOLVLEX_bp 0 /* Low Level Interrupt Executing bit position. */ - -/* PMIC.INTPRI bit masks and bit positions */ -#define PMIC_INTPRI_gm 0xFF /* Interrupt Priority group mask. */ -#define PMIC_INTPRI_gp 0 /* Interrupt Priority group position. */ -#define PMIC_INTPRI0_bm (1<<0) /* Interrupt Priority bit 0 mask. */ -#define PMIC_INTPRI0_bp 0 /* Interrupt Priority bit 0 position. */ -#define PMIC_INTPRI1_bm (1<<1) /* Interrupt Priority bit 1 mask. */ -#define PMIC_INTPRI1_bp 1 /* Interrupt Priority bit 1 position. */ -#define PMIC_INTPRI2_bm (1<<2) /* Interrupt Priority bit 2 mask. */ -#define PMIC_INTPRI2_bp 2 /* Interrupt Priority bit 2 position. */ -#define PMIC_INTPRI3_bm (1<<3) /* Interrupt Priority bit 3 mask. */ -#define PMIC_INTPRI3_bp 3 /* Interrupt Priority bit 3 position. */ -#define PMIC_INTPRI4_bm (1<<4) /* Interrupt Priority bit 4 mask. */ -#define PMIC_INTPRI4_bp 4 /* Interrupt Priority bit 4 position. */ -#define PMIC_INTPRI5_bm (1<<5) /* Interrupt Priority bit 5 mask. */ -#define PMIC_INTPRI5_bp 5 /* Interrupt Priority bit 5 position. */ -#define PMIC_INTPRI6_bm (1<<6) /* Interrupt Priority bit 6 mask. */ -#define PMIC_INTPRI6_bp 6 /* Interrupt Priority bit 6 position. */ -#define PMIC_INTPRI7_bm (1<<7) /* Interrupt Priority bit 7 mask. */ -#define PMIC_INTPRI7_bp 7 /* Interrupt Priority bit 7 position. */ - -/* PMIC.CTRL bit masks and bit positions */ -#define PMIC_RREN_bm 0x80 /* Round-Robin Priority Enable bit mask. */ -#define PMIC_RREN_bp 7 /* Round-Robin Priority Enable bit position. */ - -#define PMIC_IVSEL_bm 0x40 /* Interrupt Vector Select bit mask. */ -#define PMIC_IVSEL_bp 6 /* Interrupt Vector Select bit position. */ - -#define PMIC_HILVLEN_bm 0x04 /* High Level Enable bit mask. */ -#define PMIC_HILVLEN_bp 2 /* High Level Enable bit position. */ - -#define PMIC_MEDLVLEN_bm 0x02 /* Medium Level Enable bit mask. */ -#define PMIC_MEDLVLEN_bp 1 /* Medium Level Enable bit position. */ - -#define PMIC_LOLVLEN_bm 0x01 /* Low Level Enable bit mask. */ -#define PMIC_LOLVLEN_bp 0 /* Low Level Enable bit position. */ - -/* PORTCFG - Port Configuration */ -/* PORTCFG.VPCTRLA bit masks and bit positions */ -#define PORTCFG_VP1MAP_gm 0xF0 /* Virtual Port 1 Mapping group mask. */ -#define PORTCFG_VP1MAP_gp 4 /* Virtual Port 1 Mapping group position. */ -#define PORTCFG_VP1MAP0_bm (1<<4) /* Virtual Port 1 Mapping bit 0 mask. */ -#define PORTCFG_VP1MAP0_bp 4 /* Virtual Port 1 Mapping bit 0 position. */ -#define PORTCFG_VP1MAP1_bm (1<<5) /* Virtual Port 1 Mapping bit 1 mask. */ -#define PORTCFG_VP1MAP1_bp 5 /* Virtual Port 1 Mapping bit 1 position. */ -#define PORTCFG_VP1MAP2_bm (1<<6) /* Virtual Port 1 Mapping bit 2 mask. */ -#define PORTCFG_VP1MAP2_bp 6 /* Virtual Port 1 Mapping bit 2 position. */ -#define PORTCFG_VP1MAP3_bm (1<<7) /* Virtual Port 1 Mapping bit 3 mask. */ -#define PORTCFG_VP1MAP3_bp 7 /* Virtual Port 1 Mapping bit 3 position. */ - -#define PORTCFG_VP0MAP_gm 0x0F /* Virtual Port 0 Mapping group mask. */ -#define PORTCFG_VP0MAP_gp 0 /* Virtual Port 0 Mapping group position. */ -#define PORTCFG_VP0MAP0_bm (1<<0) /* Virtual Port 0 Mapping bit 0 mask. */ -#define PORTCFG_VP0MAP0_bp 0 /* Virtual Port 0 Mapping bit 0 position. */ -#define PORTCFG_VP0MAP1_bm (1<<1) /* Virtual Port 0 Mapping bit 1 mask. */ -#define PORTCFG_VP0MAP1_bp 1 /* Virtual Port 0 Mapping bit 1 position. */ -#define PORTCFG_VP0MAP2_bm (1<<2) /* Virtual Port 0 Mapping bit 2 mask. */ -#define PORTCFG_VP0MAP2_bp 2 /* Virtual Port 0 Mapping bit 2 position. */ -#define PORTCFG_VP0MAP3_bm (1<<3) /* Virtual Port 0 Mapping bit 3 mask. */ -#define PORTCFG_VP0MAP3_bp 3 /* Virtual Port 0 Mapping bit 3 position. */ - -/* PORTCFG.VPCTRLB bit masks and bit positions */ -#define PORTCFG_VP3MAP_gm 0xF0 /* Virtual Port 3 Mapping group mask. */ -#define PORTCFG_VP3MAP_gp 4 /* Virtual Port 3 Mapping group position. */ -#define PORTCFG_VP3MAP0_bm (1<<4) /* Virtual Port 3 Mapping bit 0 mask. */ -#define PORTCFG_VP3MAP0_bp 4 /* Virtual Port 3 Mapping bit 0 position. */ -#define PORTCFG_VP3MAP1_bm (1<<5) /* Virtual Port 3 Mapping bit 1 mask. */ -#define PORTCFG_VP3MAP1_bp 5 /* Virtual Port 3 Mapping bit 1 position. */ -#define PORTCFG_VP3MAP2_bm (1<<6) /* Virtual Port 3 Mapping bit 2 mask. */ -#define PORTCFG_VP3MAP2_bp 6 /* Virtual Port 3 Mapping bit 2 position. */ -#define PORTCFG_VP3MAP3_bm (1<<7) /* Virtual Port 3 Mapping bit 3 mask. */ -#define PORTCFG_VP3MAP3_bp 7 /* Virtual Port 3 Mapping bit 3 position. */ - -#define PORTCFG_VP2MAP_gm 0x0F /* Virtual Port 2 Mapping group mask. */ -#define PORTCFG_VP2MAP_gp 0 /* Virtual Port 2 Mapping group position. */ -#define PORTCFG_VP2MAP0_bm (1<<0) /* Virtual Port 2 Mapping bit 0 mask. */ -#define PORTCFG_VP2MAP0_bp 0 /* Virtual Port 2 Mapping bit 0 position. */ -#define PORTCFG_VP2MAP1_bm (1<<1) /* Virtual Port 2 Mapping bit 1 mask. */ -#define PORTCFG_VP2MAP1_bp 1 /* Virtual Port 2 Mapping bit 1 position. */ -#define PORTCFG_VP2MAP2_bm (1<<2) /* Virtual Port 2 Mapping bit 2 mask. */ -#define PORTCFG_VP2MAP2_bp 2 /* Virtual Port 2 Mapping bit 2 position. */ -#define PORTCFG_VP2MAP3_bm (1<<3) /* Virtual Port 2 Mapping bit 3 mask. */ -#define PORTCFG_VP2MAP3_bp 3 /* Virtual Port 2 Mapping bit 3 position. */ - -/* PORTCFG.CLKEVOUT bit masks and bit positions */ -#define PORTCFG_CLKOUT_gm 0x03 /* Peripheral Clock Output Port group mask. */ -#define PORTCFG_CLKOUT_gp 0 /* Peripheral Clock Output Port group position. */ -#define PORTCFG_CLKOUT0_bm (1<<0) /* Peripheral Clock Output Port bit 0 mask. */ -#define PORTCFG_CLKOUT0_bp 0 /* Peripheral Clock Output Port bit 0 position. */ -#define PORTCFG_CLKOUT1_bm (1<<1) /* Peripheral Clock Output Port bit 1 mask. */ -#define PORTCFG_CLKOUT1_bp 1 /* Peripheral Clock Output Port bit 1 position. */ - -#define PORTCFG_CLKOUTSEL_gm 0x0C /* Peripheral Clock Output Select group mask. */ -#define PORTCFG_CLKOUTSEL_gp 2 /* Peripheral Clock Output Select group position. */ -#define PORTCFG_CLKOUTSEL0_bm (1<<2) /* Peripheral Clock Output Select bit 0 mask. */ -#define PORTCFG_CLKOUTSEL0_bp 2 /* Peripheral Clock Output Select bit 0 position. */ -#define PORTCFG_CLKOUTSEL1_bm (1<<3) /* Peripheral Clock Output Select bit 1 mask. */ -#define PORTCFG_CLKOUTSEL1_bp 3 /* Peripheral Clock Output Select bit 1 position. */ - -#define PORTCFG_EVOUT_gm 0x30 /* Event Output Port group mask. */ -#define PORTCFG_EVOUT_gp 4 /* Event Output Port group position. */ -#define PORTCFG_EVOUT0_bm (1<<4) /* Event Output Port bit 0 mask. */ -#define PORTCFG_EVOUT0_bp 4 /* Event Output Port bit 0 position. */ -#define PORTCFG_EVOUT1_bm (1<<5) /* Event Output Port bit 1 mask. */ -#define PORTCFG_EVOUT1_bp 5 /* Event Output Port bit 1 position. */ - -#define PORTCFG_RTCOUT_bm 0x40 /* RTC Clock Output bit mask. */ -#define PORTCFG_RTCOUT_bp 6 /* RTC Clock Output bit position. */ - -#define PORTCFG_CLKEVPIN_bm 0x80 /* Peripheral Clock and Event Output pin Select bit mask. */ -#define PORTCFG_CLKEVPIN_bp 7 /* Peripheral Clock and Event Output pin Select bit position. */ - -/* PORTCFG.EVOUTSEL bit masks and bit positions */ -#define PORTCFG_EVOUTSEL_gm 0x07 /* Event Output Select group mask. */ -#define PORTCFG_EVOUTSEL_gp 0 /* Event Output Select group position. */ -#define PORTCFG_EVOUTSEL0_bm (1<<0) /* Event Output Select bit 0 mask. */ -#define PORTCFG_EVOUTSEL0_bp 0 /* Event Output Select bit 0 position. */ -#define PORTCFG_EVOUTSEL1_bm (1<<1) /* Event Output Select bit 1 mask. */ -#define PORTCFG_EVOUTSEL1_bp 1 /* Event Output Select bit 1 position. */ -#define PORTCFG_EVOUTSEL2_bm (1<<2) /* Event Output Select bit 2 mask. */ -#define PORTCFG_EVOUTSEL2_bp 2 /* Event Output Select bit 2 position. */ - -/* CRC - Cyclic Redundancy Checker */ -/* CRC.CTRL bit masks and bit positions */ -#define CRC_RESET_gm 0xC0 /* Reset group mask. */ -#define CRC_RESET_gp 6 /* Reset group position. */ -#define CRC_RESET0_bm (1<<6) /* Reset bit 0 mask. */ -#define CRC_RESET0_bp 6 /* Reset bit 0 position. */ -#define CRC_RESET1_bm (1<<7) /* Reset bit 1 mask. */ -#define CRC_RESET1_bp 7 /* Reset bit 1 position. */ - -#define CRC_CRC32_bm 0x20 /* CRC Mode bit mask. */ -#define CRC_CRC32_bp 5 /* CRC Mode bit position. */ - -#define CRC_SOURCE_gm 0x0F /* Input Source group mask. */ -#define CRC_SOURCE_gp 0 /* Input Source group position. */ -#define CRC_SOURCE0_bm (1<<0) /* Input Source bit 0 mask. */ -#define CRC_SOURCE0_bp 0 /* Input Source bit 0 position. */ -#define CRC_SOURCE1_bm (1<<1) /* Input Source bit 1 mask. */ -#define CRC_SOURCE1_bp 1 /* Input Source bit 1 position. */ -#define CRC_SOURCE2_bm (1<<2) /* Input Source bit 2 mask. */ -#define CRC_SOURCE2_bp 2 /* Input Source bit 2 position. */ -#define CRC_SOURCE3_bm (1<<3) /* Input Source bit 3 mask. */ -#define CRC_SOURCE3_bp 3 /* Input Source bit 3 position. */ - -/* CRC.STATUS bit masks and bit positions */ -#define CRC_ZERO_bm 0x02 /* Zero detection bit mask. */ -#define CRC_ZERO_bp 1 /* Zero detection bit position. */ - -#define CRC_BUSY_bm 0x01 /* Busy bit mask. */ -#define CRC_BUSY_bp 0 /* Busy bit position. */ - -/* EVSYS - Event System */ -/* EVSYS.CH0MUX bit masks and bit positions */ -#define EVSYS_CHMUX_gm 0xFF /* Event Channel 0 Multiplexer group mask. */ -#define EVSYS_CHMUX_gp 0 /* Event Channel 0 Multiplexer group position. */ -#define EVSYS_CHMUX0_bm (1<<0) /* Event Channel 0 Multiplexer bit 0 mask. */ -#define EVSYS_CHMUX0_bp 0 /* Event Channel 0 Multiplexer bit 0 position. */ -#define EVSYS_CHMUX1_bm (1<<1) /* Event Channel 0 Multiplexer bit 1 mask. */ -#define EVSYS_CHMUX1_bp 1 /* Event Channel 0 Multiplexer bit 1 position. */ -#define EVSYS_CHMUX2_bm (1<<2) /* Event Channel 0 Multiplexer bit 2 mask. */ -#define EVSYS_CHMUX2_bp 2 /* Event Channel 0 Multiplexer bit 2 position. */ -#define EVSYS_CHMUX3_bm (1<<3) /* Event Channel 0 Multiplexer bit 3 mask. */ -#define EVSYS_CHMUX3_bp 3 /* Event Channel 0 Multiplexer bit 3 position. */ -#define EVSYS_CHMUX4_bm (1<<4) /* Event Channel 0 Multiplexer bit 4 mask. */ -#define EVSYS_CHMUX4_bp 4 /* Event Channel 0 Multiplexer bit 4 position. */ -#define EVSYS_CHMUX5_bm (1<<5) /* Event Channel 0 Multiplexer bit 5 mask. */ -#define EVSYS_CHMUX5_bp 5 /* Event Channel 0 Multiplexer bit 5 position. */ -#define EVSYS_CHMUX6_bm (1<<6) /* Event Channel 0 Multiplexer bit 6 mask. */ -#define EVSYS_CHMUX6_bp 6 /* Event Channel 0 Multiplexer bit 6 position. */ -#define EVSYS_CHMUX7_bm (1<<7) /* Event Channel 0 Multiplexer bit 7 mask. */ -#define EVSYS_CHMUX7_bp 7 /* Event Channel 0 Multiplexer bit 7 position. */ - -/* EVSYS.CH1MUX bit masks and bit positions */ -/* EVSYS_CHMUX Predefined. */ -/* EVSYS_CHMUX Predefined. */ - -/* EVSYS.CH2MUX bit masks and bit positions */ -/* EVSYS_CHMUX Predefined. */ -/* EVSYS_CHMUX Predefined. */ - -/* EVSYS.CH3MUX bit masks and bit positions */ -/* EVSYS_CHMUX Predefined. */ -/* EVSYS_CHMUX Predefined. */ - -/* EVSYS.CH0CTRL bit masks and bit positions */ -#define EVSYS_QDIRM_gm 0x60 /* Quadrature Decoder Index Recognition Mode group mask. */ -#define EVSYS_QDIRM_gp 5 /* Quadrature Decoder Index Recognition Mode group position. */ -#define EVSYS_QDIRM0_bm (1<<5) /* Quadrature Decoder Index Recognition Mode bit 0 mask. */ -#define EVSYS_QDIRM0_bp 5 /* Quadrature Decoder Index Recognition Mode bit 0 position. */ -#define EVSYS_QDIRM1_bm (1<<6) /* Quadrature Decoder Index Recognition Mode bit 1 mask. */ -#define EVSYS_QDIRM1_bp 6 /* Quadrature Decoder Index Recognition Mode bit 1 position. */ - -#define EVSYS_QDIEN_bm 0x10 /* Quadrature Decoder Index Enable bit mask. */ -#define EVSYS_QDIEN_bp 4 /* Quadrature Decoder Index Enable bit position. */ - -#define EVSYS_QDEN_bm 0x08 /* Quadrature Decoder Enable bit mask. */ -#define EVSYS_QDEN_bp 3 /* Quadrature Decoder Enable bit position. */ - -#define EVSYS_DIGFILT_gm 0x07 /* Digital Filter group mask. */ -#define EVSYS_DIGFILT_gp 0 /* Digital Filter group position. */ -#define EVSYS_DIGFILT0_bm (1<<0) /* Digital Filter bit 0 mask. */ -#define EVSYS_DIGFILT0_bp 0 /* Digital Filter bit 0 position. */ -#define EVSYS_DIGFILT1_bm (1<<1) /* Digital Filter bit 1 mask. */ -#define EVSYS_DIGFILT1_bp 1 /* Digital Filter bit 1 position. */ -#define EVSYS_DIGFILT2_bm (1<<2) /* Digital Filter bit 2 mask. */ -#define EVSYS_DIGFILT2_bp 2 /* Digital Filter bit 2 position. */ - -/* EVSYS.CH1CTRL bit masks and bit positions */ -/* EVSYS_DIGFILT Predefined. */ -/* EVSYS_DIGFILT Predefined. */ - -/* EVSYS.CH2CTRL bit masks and bit positions */ -/* EVSYS_DIGFILT Predefined. */ -/* EVSYS_DIGFILT Predefined. */ - -/* EVSYS.CH3CTRL bit masks and bit positions */ -/* EVSYS_DIGFILT Predefined. */ -/* EVSYS_DIGFILT Predefined. */ - -/* NVM - Non Volatile Memory Controller */ -/* NVM.CMD bit masks and bit positions */ -#define NVM_CMD_gm 0x7F /* Command group mask. */ -#define NVM_CMD_gp 0 /* Command group position. */ -#define NVM_CMD0_bm (1<<0) /* Command bit 0 mask. */ -#define NVM_CMD0_bp 0 /* Command bit 0 position. */ -#define NVM_CMD1_bm (1<<1) /* Command bit 1 mask. */ -#define NVM_CMD1_bp 1 /* Command bit 1 position. */ -#define NVM_CMD2_bm (1<<2) /* Command bit 2 mask. */ -#define NVM_CMD2_bp 2 /* Command bit 2 position. */ -#define NVM_CMD3_bm (1<<3) /* Command bit 3 mask. */ -#define NVM_CMD3_bp 3 /* Command bit 3 position. */ -#define NVM_CMD4_bm (1<<4) /* Command bit 4 mask. */ -#define NVM_CMD4_bp 4 /* Command bit 4 position. */ -#define NVM_CMD5_bm (1<<5) /* Command bit 5 mask. */ -#define NVM_CMD5_bp 5 /* Command bit 5 position. */ -#define NVM_CMD6_bm (1<<6) /* Command bit 6 mask. */ -#define NVM_CMD6_bp 6 /* Command bit 6 position. */ - -/* NVM.CTRLA bit masks and bit positions */ -#define NVM_CMDEX_bm 0x01 /* Command Execute bit mask. */ -#define NVM_CMDEX_bp 0 /* Command Execute bit position. */ - -/* NVM.CTRLB bit masks and bit positions */ -#define NVM_EEMAPEN_bm 0x08 /* EEPROM Mapping Enable bit mask. */ -#define NVM_EEMAPEN_bp 3 /* EEPROM Mapping Enable bit position. */ - -#define NVM_FPRM_bm 0x04 /* Flash Power Reduction Enable bit mask. */ -#define NVM_FPRM_bp 2 /* Flash Power Reduction Enable bit position. */ - -#define NVM_EPRM_bm 0x02 /* EEPROM Power Reduction Enable bit mask. */ -#define NVM_EPRM_bp 1 /* EEPROM Power Reduction Enable bit position. */ - -#define NVM_SPMLOCK_bm 0x01 /* SPM Lock bit mask. */ -#define NVM_SPMLOCK_bp 0 /* SPM Lock bit position. */ - -/* NVM.INTCTRL bit masks and bit positions */ -#define NVM_SPMLVL_gm 0x0C /* SPM Interrupt Level group mask. */ -#define NVM_SPMLVL_gp 2 /* SPM Interrupt Level group position. */ -#define NVM_SPMLVL0_bm (1<<2) /* SPM Interrupt Level bit 0 mask. */ -#define NVM_SPMLVL0_bp 2 /* SPM Interrupt Level bit 0 position. */ -#define NVM_SPMLVL1_bm (1<<3) /* SPM Interrupt Level bit 1 mask. */ -#define NVM_SPMLVL1_bp 3 /* SPM Interrupt Level bit 1 position. */ - -#define NVM_EELVL_gm 0x03 /* EEPROM Interrupt Level group mask. */ -#define NVM_EELVL_gp 0 /* EEPROM Interrupt Level group position. */ -#define NVM_EELVL0_bm (1<<0) /* EEPROM Interrupt Level bit 0 mask. */ -#define NVM_EELVL0_bp 0 /* EEPROM Interrupt Level bit 0 position. */ -#define NVM_EELVL1_bm (1<<1) /* EEPROM Interrupt Level bit 1 mask. */ -#define NVM_EELVL1_bp 1 /* EEPROM Interrupt Level bit 1 position. */ - -/* NVM.STATUS bit masks and bit positions */ -#define NVM_NVMBUSY_bm 0x80 /* Non-volatile Memory Busy bit mask. */ -#define NVM_NVMBUSY_bp 7 /* Non-volatile Memory Busy bit position. */ - -#define NVM_FBUSY_bm 0x40 /* Flash Memory Busy bit mask. */ -#define NVM_FBUSY_bp 6 /* Flash Memory Busy bit position. */ - -#define NVM_EELOAD_bm 0x02 /* EEPROM Page Buffer Active Loading bit mask. */ -#define NVM_EELOAD_bp 1 /* EEPROM Page Buffer Active Loading bit position. */ - -#define NVM_FLOAD_bm 0x01 /* Flash Page Buffer Active Loading bit mask. */ -#define NVM_FLOAD_bp 0 /* Flash Page Buffer Active Loading bit position. */ - -/* NVM.LOCKBITS bit masks and bit positions */ -#define NVM_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ -#define NVM_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ -#define NVM_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ -#define NVM_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ -#define NVM_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ -#define NVM_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ - -#define NVM_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ -#define NVM_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ -#define NVM_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ -#define NVM_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ -#define NVM_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ -#define NVM_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ - -#define NVM_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ -#define NVM_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ -#define NVM_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ -#define NVM_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ -#define NVM_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ -#define NVM_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ - -#define NVM_LB_gm 0x03 /* Lock Bits group mask. */ -#define NVM_LB_gp 0 /* Lock Bits group position. */ -#define NVM_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ -#define NVM_LB0_bp 0 /* Lock Bits bit 0 position. */ -#define NVM_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ -#define NVM_LB1_bp 1 /* Lock Bits bit 1 position. */ - -/* ADC - Analog/Digital Converter */ -/* ADC_CH.CTRL bit masks and bit positions */ -#define ADC_CH_START_bm 0x80 /* Channel Start Conversion bit mask. */ -#define ADC_CH_START_bp 7 /* Channel Start Conversion bit position. */ - -#define ADC_CH_GAIN_gm 0x1C /* Gain Factor group mask. */ -#define ADC_CH_GAIN_gp 2 /* Gain Factor group position. */ -#define ADC_CH_GAIN0_bm (1<<2) /* Gain Factor bit 0 mask. */ -#define ADC_CH_GAIN0_bp 2 /* Gain Factor bit 0 position. */ -#define ADC_CH_GAIN1_bm (1<<3) /* Gain Factor bit 1 mask. */ -#define ADC_CH_GAIN1_bp 3 /* Gain Factor bit 1 position. */ -#define ADC_CH_GAIN2_bm (1<<4) /* Gain Factor bit 2 mask. */ -#define ADC_CH_GAIN2_bp 4 /* Gain Factor bit 2 position. */ - -#define ADC_CH_INPUTMODE_gm 0x03 /* Input Mode Select group mask. */ -#define ADC_CH_INPUTMODE_gp 0 /* Input Mode Select group position. */ -#define ADC_CH_INPUTMODE0_bm (1<<0) /* Input Mode Select bit 0 mask. */ -#define ADC_CH_INPUTMODE0_bp 0 /* Input Mode Select bit 0 position. */ -#define ADC_CH_INPUTMODE1_bm (1<<1) /* Input Mode Select bit 1 mask. */ -#define ADC_CH_INPUTMODE1_bp 1 /* Input Mode Select bit 1 position. */ - -/* ADC_CH.MUXCTRL bit masks and bit positions */ -#define ADC_CH_MUXPOS_gm 0x78 /* MUX selection on Positive ADC input group mask. */ -#define ADC_CH_MUXPOS_gp 3 /* MUX selection on Positive ADC input group position. */ -#define ADC_CH_MUXPOS0_bm (1<<3) /* MUX selection on Positive ADC input bit 0 mask. */ -#define ADC_CH_MUXPOS0_bp 3 /* MUX selection on Positive ADC input bit 0 position. */ -#define ADC_CH_MUXPOS1_bm (1<<4) /* MUX selection on Positive ADC input bit 1 mask. */ -#define ADC_CH_MUXPOS1_bp 4 /* MUX selection on Positive ADC input bit 1 position. */ -#define ADC_CH_MUXPOS2_bm (1<<5) /* MUX selection on Positive ADC input bit 2 mask. */ -#define ADC_CH_MUXPOS2_bp 5 /* MUX selection on Positive ADC input bit 2 position. */ -#define ADC_CH_MUXPOS3_bm (1<<6) /* MUX selection on Positive ADC input bit 3 mask. */ -#define ADC_CH_MUXPOS3_bp 6 /* MUX selection on Positive ADC input bit 3 position. */ - -#define ADC_CH_MUXINT_gm 0x78 /* MUX selection on Internal ADC input group mask. */ -#define ADC_CH_MUXINT_gp 3 /* MUX selection on Internal ADC input group position. */ -#define ADC_CH_MUXINT0_bm (1<<3) /* MUX selection on Internal ADC input bit 0 mask. */ -#define ADC_CH_MUXINT0_bp 3 /* MUX selection on Internal ADC input bit 0 position. */ -#define ADC_CH_MUXINT1_bm (1<<4) /* MUX selection on Internal ADC input bit 1 mask. */ -#define ADC_CH_MUXINT1_bp 4 /* MUX selection on Internal ADC input bit 1 position. */ -#define ADC_CH_MUXINT2_bm (1<<5) /* MUX selection on Internal ADC input bit 2 mask. */ -#define ADC_CH_MUXINT2_bp 5 /* MUX selection on Internal ADC input bit 2 position. */ -#define ADC_CH_MUXINT3_bm (1<<6) /* MUX selection on Internal ADC input bit 3 mask. */ -#define ADC_CH_MUXINT3_bp 6 /* MUX selection on Internal ADC input bit 3 position. */ - -#define ADC_CH_MUXNEG_gm 0x03 /* MUX selection on Negative ADC input group mask. */ -#define ADC_CH_MUXNEG_gp 0 /* MUX selection on Negative ADC input group position. */ -#define ADC_CH_MUXNEG0_bm (1<<0) /* MUX selection on Negative ADC input bit 0 mask. */ -#define ADC_CH_MUXNEG0_bp 0 /* MUX selection on Negative ADC input bit 0 position. */ -#define ADC_CH_MUXNEG1_bm (1<<1) /* MUX selection on Negative ADC input bit 1 mask. */ -#define ADC_CH_MUXNEG1_bp 1 /* MUX selection on Negative ADC input bit 1 position. */ - -/* ADC_CH.INTCTRL bit masks and bit positions */ -#define ADC_CH_INTMODE_gm 0x0C /* Interrupt Mode group mask. */ -#define ADC_CH_INTMODE_gp 2 /* Interrupt Mode group position. */ -#define ADC_CH_INTMODE0_bm (1<<2) /* Interrupt Mode bit 0 mask. */ -#define ADC_CH_INTMODE0_bp 2 /* Interrupt Mode bit 0 position. */ -#define ADC_CH_INTMODE1_bm (1<<3) /* Interrupt Mode bit 1 mask. */ -#define ADC_CH_INTMODE1_bp 3 /* Interrupt Mode bit 1 position. */ - -#define ADC_CH_INTLVL_gm 0x03 /* Interrupt Level group mask. */ -#define ADC_CH_INTLVL_gp 0 /* Interrupt Level group position. */ -#define ADC_CH_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */ -#define ADC_CH_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */ -#define ADC_CH_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ -#define ADC_CH_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */ - -/* ADC_CH.INTFLAGS bit masks and bit positions */ -#define ADC_CH_CHIF_bm 0x01 /* Channel Interrupt Flag bit mask. */ -#define ADC_CH_CHIF_bp 0 /* Channel Interrupt Flag bit position. */ - -/* ADC_CH.SCAN bit masks and bit positions */ -#define ADC_CH_OFFSET_gm 0xF0 /* Positive MUX setting offset group mask. */ -#define ADC_CH_OFFSET_gp 4 /* Positive MUX setting offset group position. */ -#define ADC_CH_OFFSET0_bm (1<<4) /* Positive MUX setting offset bit 0 mask. */ -#define ADC_CH_OFFSET0_bp 4 /* Positive MUX setting offset bit 0 position. */ -#define ADC_CH_OFFSET1_bm (1<<5) /* Positive MUX setting offset bit 1 mask. */ -#define ADC_CH_OFFSET1_bp 5 /* Positive MUX setting offset bit 1 position. */ -#define ADC_CH_OFFSET2_bm (1<<6) /* Positive MUX setting offset bit 2 mask. */ -#define ADC_CH_OFFSET2_bp 6 /* Positive MUX setting offset bit 2 position. */ -#define ADC_CH_OFFSET3_bm (1<<7) /* Positive MUX setting offset bit 3 mask. */ -#define ADC_CH_OFFSET3_bp 7 /* Positive MUX setting offset bit 3 position. */ - -#define ADC_CH_SCANNUM_gm 0x0F /* Number of Channels included in scan group mask. */ -#define ADC_CH_SCANNUM_gp 0 /* Number of Channels included in scan group position. */ -#define ADC_CH_SCANNUM0_bm (1<<0) /* Number of Channels included in scan bit 0 mask. */ -#define ADC_CH_SCANNUM0_bp 0 /* Number of Channels included in scan bit 0 position. */ -#define ADC_CH_SCANNUM1_bm (1<<1) /* Number of Channels included in scan bit 1 mask. */ -#define ADC_CH_SCANNUM1_bp 1 /* Number of Channels included in scan bit 1 position. */ -#define ADC_CH_SCANNUM2_bm (1<<2) /* Number of Channels included in scan bit 2 mask. */ -#define ADC_CH_SCANNUM2_bp 2 /* Number of Channels included in scan bit 2 position. */ -#define ADC_CH_SCANNUM3_bm (1<<3) /* Number of Channels included in scan bit 3 mask. */ -#define ADC_CH_SCANNUM3_bp 3 /* Number of Channels included in scan bit 3 position. */ - -/* ADC.CTRLA bit masks and bit positions */ -#define ADC_CH0START_bm 0x04 /* Channel 0 Start Conversion bit mask. */ -#define ADC_CH0START_bp 2 /* Channel 0 Start Conversion bit position. */ - -#define ADC_FLUSH_bm 0x02 /* ADC Flush bit mask. */ -#define ADC_FLUSH_bp 1 /* ADC Flush bit position. */ - -#define ADC_ENABLE_bm 0x01 /* Enable ADC bit mask. */ -#define ADC_ENABLE_bp 0 /* Enable ADC bit position. */ - -/* ADC.CTRLB bit masks and bit positions */ -#define ADC_CURRLIMIT_gm 0x60 /* Current Limitation group mask. */ -#define ADC_CURRLIMIT_gp 5 /* Current Limitation group position. */ -#define ADC_CURRLIMIT0_bm (1<<5) /* Current Limitation bit 0 mask. */ -#define ADC_CURRLIMIT0_bp 5 /* Current Limitation bit 0 position. */ -#define ADC_CURRLIMIT1_bm (1<<6) /* Current Limitation bit 1 mask. */ -#define ADC_CURRLIMIT1_bp 6 /* Current Limitation bit 1 position. */ - -#define ADC_CONMODE_bm 0x10 /* Conversion Mode bit mask. */ -#define ADC_CONMODE_bp 4 /* Conversion Mode bit position. */ - -#define ADC_FREERUN_bm 0x08 /* Free Running Mode Enable bit mask. */ -#define ADC_FREERUN_bp 3 /* Free Running Mode Enable bit position. */ - -#define ADC_RESOLUTION_gm 0x06 /* Result Resolution group mask. */ -#define ADC_RESOLUTION_gp 1 /* Result Resolution group position. */ -#define ADC_RESOLUTION0_bm (1<<1) /* Result Resolution bit 0 mask. */ -#define ADC_RESOLUTION0_bp 1 /* Result Resolution bit 0 position. */ -#define ADC_RESOLUTION1_bm (1<<2) /* Result Resolution bit 1 mask. */ -#define ADC_RESOLUTION1_bp 2 /* Result Resolution bit 1 position. */ - -/* ADC.REFCTRL bit masks and bit positions */ -#define ADC_REFSEL_gm 0x70 /* Reference Selection group mask. */ -#define ADC_REFSEL_gp 4 /* Reference Selection group position. */ -#define ADC_REFSEL0_bm (1<<4) /* Reference Selection bit 0 mask. */ -#define ADC_REFSEL0_bp 4 /* Reference Selection bit 0 position. */ -#define ADC_REFSEL1_bm (1<<5) /* Reference Selection bit 1 mask. */ -#define ADC_REFSEL1_bp 5 /* Reference Selection bit 1 position. */ -#define ADC_REFSEL2_bm (1<<6) /* Reference Selection bit 2 mask. */ -#define ADC_REFSEL2_bp 6 /* Reference Selection bit 2 position. */ - -#define ADC_BANDGAP_bm 0x02 /* Bandgap enable bit mask. */ -#define ADC_BANDGAP_bp 1 /* Bandgap enable bit position. */ - -#define ADC_TEMPREF_bm 0x01 /* Temperature Reference Enable bit mask. */ -#define ADC_TEMPREF_bp 0 /* Temperature Reference Enable bit position. */ - -/* ADC.EVCTRL bit masks and bit positions */ -#define ADC_EVSEL_gm 0x18 /* Event Input Select group mask. */ -#define ADC_EVSEL_gp 3 /* Event Input Select group position. */ -#define ADC_EVSEL0_bm (1<<3) /* Event Input Select bit 0 mask. */ -#define ADC_EVSEL0_bp 3 /* Event Input Select bit 0 position. */ -#define ADC_EVSEL1_bm (1<<4) /* Event Input Select bit 1 mask. */ -#define ADC_EVSEL1_bp 4 /* Event Input Select bit 1 position. */ - -#define ADC_EVACT_gm 0x07 /* Event Action Select group mask. */ -#define ADC_EVACT_gp 0 /* Event Action Select group position. */ -#define ADC_EVACT0_bm (1<<0) /* Event Action Select bit 0 mask. */ -#define ADC_EVACT0_bp 0 /* Event Action Select bit 0 position. */ -#define ADC_EVACT1_bm (1<<1) /* Event Action Select bit 1 mask. */ -#define ADC_EVACT1_bp 1 /* Event Action Select bit 1 position. */ -#define ADC_EVACT2_bm (1<<2) /* Event Action Select bit 2 mask. */ -#define ADC_EVACT2_bp 2 /* Event Action Select bit 2 position. */ - -/* ADC.PRESCALER bit masks and bit positions */ -#define ADC_PRESCALER_gm 0x07 /* Clock Prescaler Selection group mask. */ -#define ADC_PRESCALER_gp 0 /* Clock Prescaler Selection group position. */ -#define ADC_PRESCALER0_bm (1<<0) /* Clock Prescaler Selection bit 0 mask. */ -#define ADC_PRESCALER0_bp 0 /* Clock Prescaler Selection bit 0 position. */ -#define ADC_PRESCALER1_bm (1<<1) /* Clock Prescaler Selection bit 1 mask. */ -#define ADC_PRESCALER1_bp 1 /* Clock Prescaler Selection bit 1 position. */ -#define ADC_PRESCALER2_bm (1<<2) /* Clock Prescaler Selection bit 2 mask. */ -#define ADC_PRESCALER2_bp 2 /* Clock Prescaler Selection bit 2 position. */ - -/* ADC.INTFLAGS bit masks and bit positions */ -#define ADC_CH0IF_bm 0x01 /* Channel 0 Interrupt Flag bit mask. */ -#define ADC_CH0IF_bp 0 /* Channel 0 Interrupt Flag bit position. */ - -/* AC - Analog Comparator */ -/* AC.AC0CTRL bit masks and bit positions */ -#define AC_INTMODE_gm 0xC0 /* Interrupt Mode group mask. */ -#define AC_INTMODE_gp 6 /* Interrupt Mode group position. */ -#define AC_INTMODE0_bm (1<<6) /* Interrupt Mode bit 0 mask. */ -#define AC_INTMODE0_bp 6 /* Interrupt Mode bit 0 position. */ -#define AC_INTMODE1_bm (1<<7) /* Interrupt Mode bit 1 mask. */ -#define AC_INTMODE1_bp 7 /* Interrupt Mode bit 1 position. */ - -#define AC_INTLVL_gm 0x30 /* Interrupt Level group mask. */ -#define AC_INTLVL_gp 4 /* Interrupt Level group position. */ -#define AC_INTLVL0_bm (1<<4) /* Interrupt Level bit 0 mask. */ -#define AC_INTLVL0_bp 4 /* Interrupt Level bit 0 position. */ -#define AC_INTLVL1_bm (1<<5) /* Interrupt Level bit 1 mask. */ -#define AC_INTLVL1_bp 5 /* Interrupt Level bit 1 position. */ - -#define AC_HYSMODE_gm 0x06 /* Hysteresis Mode group mask. */ -#define AC_HYSMODE_gp 1 /* Hysteresis Mode group position. */ -#define AC_HYSMODE0_bm (1<<1) /* Hysteresis Mode bit 0 mask. */ -#define AC_HYSMODE0_bp 1 /* Hysteresis Mode bit 0 position. */ -#define AC_HYSMODE1_bm (1<<2) /* Hysteresis Mode bit 1 mask. */ -#define AC_HYSMODE1_bp 2 /* Hysteresis Mode bit 1 position. */ - -#define AC_ENABLE_bm 0x01 /* Enable bit mask. */ -#define AC_ENABLE_bp 0 /* Enable bit position. */ - -/* AC.AC1CTRL bit masks and bit positions */ -/* AC_INTMODE Predefined. */ -/* AC_INTMODE Predefined. */ - -/* AC_INTLVL Predefined. */ -/* AC_INTLVL Predefined. */ - -/* AC_HYSMODE Predefined. */ -/* AC_HYSMODE Predefined. */ - -/* AC_ENABLE Predefined. */ -/* AC_ENABLE Predefined. */ - -/* AC.AC0MUXCTRL bit masks and bit positions */ -#define AC_MUXPOS_gm 0x38 /* MUX Positive Input group mask. */ -#define AC_MUXPOS_gp 3 /* MUX Positive Input group position. */ -#define AC_MUXPOS0_bm (1<<3) /* MUX Positive Input bit 0 mask. */ -#define AC_MUXPOS0_bp 3 /* MUX Positive Input bit 0 position. */ -#define AC_MUXPOS1_bm (1<<4) /* MUX Positive Input bit 1 mask. */ -#define AC_MUXPOS1_bp 4 /* MUX Positive Input bit 1 position. */ -#define AC_MUXPOS2_bm (1<<5) /* MUX Positive Input bit 2 mask. */ -#define AC_MUXPOS2_bp 5 /* MUX Positive Input bit 2 position. */ - -#define AC_MUXNEG_gm 0x07 /* MUX Negative Input group mask. */ -#define AC_MUXNEG_gp 0 /* MUX Negative Input group position. */ -#define AC_MUXNEG0_bm (1<<0) /* MUX Negative Input bit 0 mask. */ -#define AC_MUXNEG0_bp 0 /* MUX Negative Input bit 0 position. */ -#define AC_MUXNEG1_bm (1<<1) /* MUX Negative Input bit 1 mask. */ -#define AC_MUXNEG1_bp 1 /* MUX Negative Input bit 1 position. */ -#define AC_MUXNEG2_bm (1<<2) /* MUX Negative Input bit 2 mask. */ -#define AC_MUXNEG2_bp 2 /* MUX Negative Input bit 2 position. */ - -/* AC.AC1MUXCTRL bit masks and bit positions */ -/* AC_MUXPOS Predefined. */ -/* AC_MUXPOS Predefined. */ - -/* AC_MUXNEG Predefined. */ -/* AC_MUXNEG Predefined. */ - -/* AC.CTRLA bit masks and bit positions */ -#define AC_AC1OUT_bm 0x02 /* Analog Comparator 1 Output Enable bit mask. */ -#define AC_AC1OUT_bp 1 /* Analog Comparator 1 Output Enable bit position. */ - -#define AC_AC0OUT_bm 0x01 /* Analog Comparator 0 Output Enable bit mask. */ -#define AC_AC0OUT_bp 0 /* Analog Comparator 0 Output Enable bit position. */ - -/* AC.CTRLB bit masks and bit positions */ -#define AC_SCALEFAC_gm 0x3F /* VCC Voltage Scaler Factor group mask. */ -#define AC_SCALEFAC_gp 0 /* VCC Voltage Scaler Factor group position. */ -#define AC_SCALEFAC0_bm (1<<0) /* VCC Voltage Scaler Factor bit 0 mask. */ -#define AC_SCALEFAC0_bp 0 /* VCC Voltage Scaler Factor bit 0 position. */ -#define AC_SCALEFAC1_bm (1<<1) /* VCC Voltage Scaler Factor bit 1 mask. */ -#define AC_SCALEFAC1_bp 1 /* VCC Voltage Scaler Factor bit 1 position. */ -#define AC_SCALEFAC2_bm (1<<2) /* VCC Voltage Scaler Factor bit 2 mask. */ -#define AC_SCALEFAC2_bp 2 /* VCC Voltage Scaler Factor bit 2 position. */ -#define AC_SCALEFAC3_bm (1<<3) /* VCC Voltage Scaler Factor bit 3 mask. */ -#define AC_SCALEFAC3_bp 3 /* VCC Voltage Scaler Factor bit 3 position. */ -#define AC_SCALEFAC4_bm (1<<4) /* VCC Voltage Scaler Factor bit 4 mask. */ -#define AC_SCALEFAC4_bp 4 /* VCC Voltage Scaler Factor bit 4 position. */ -#define AC_SCALEFAC5_bm (1<<5) /* VCC Voltage Scaler Factor bit 5 mask. */ -#define AC_SCALEFAC5_bp 5 /* VCC Voltage Scaler Factor bit 5 position. */ - -/* AC.WINCTRL bit masks and bit positions */ -#define AC_WEN_bm 0x10 /* Window Mode Enable bit mask. */ -#define AC_WEN_bp 4 /* Window Mode Enable bit position. */ - -#define AC_WINTMODE_gm 0x0C /* Window Interrupt Mode group mask. */ -#define AC_WINTMODE_gp 2 /* Window Interrupt Mode group position. */ -#define AC_WINTMODE0_bm (1<<2) /* Window Interrupt Mode bit 0 mask. */ -#define AC_WINTMODE0_bp 2 /* Window Interrupt Mode bit 0 position. */ -#define AC_WINTMODE1_bm (1<<3) /* Window Interrupt Mode bit 1 mask. */ -#define AC_WINTMODE1_bp 3 /* Window Interrupt Mode bit 1 position. */ - -#define AC_WINTLVL_gm 0x03 /* Window Interrupt Level group mask. */ -#define AC_WINTLVL_gp 0 /* Window Interrupt Level group position. */ -#define AC_WINTLVL0_bm (1<<0) /* Window Interrupt Level bit 0 mask. */ -#define AC_WINTLVL0_bp 0 /* Window Interrupt Level bit 0 position. */ -#define AC_WINTLVL1_bm (1<<1) /* Window Interrupt Level bit 1 mask. */ -#define AC_WINTLVL1_bp 1 /* Window Interrupt Level bit 1 position. */ - -/* AC.STATUS bit masks and bit positions */ -#define AC_WSTATE_gm 0xC0 /* Window Mode State group mask. */ -#define AC_WSTATE_gp 6 /* Window Mode State group position. */ -#define AC_WSTATE0_bm (1<<6) /* Window Mode State bit 0 mask. */ -#define AC_WSTATE0_bp 6 /* Window Mode State bit 0 position. */ -#define AC_WSTATE1_bm (1<<7) /* Window Mode State bit 1 mask. */ -#define AC_WSTATE1_bp 7 /* Window Mode State bit 1 position. */ - -#define AC_AC1STATE_bm 0x20 /* Analog Comparator 1 State bit mask. */ -#define AC_AC1STATE_bp 5 /* Analog Comparator 1 State bit position. */ - -#define AC_AC0STATE_bm 0x10 /* Analog Comparator 0 State bit mask. */ -#define AC_AC0STATE_bp 4 /* Analog Comparator 0 State bit position. */ - -#define AC_WIF_bm 0x04 /* Window Mode Interrupt Flag bit mask. */ -#define AC_WIF_bp 2 /* Window Mode Interrupt Flag bit position. */ - -#define AC_AC1IF_bm 0x02 /* Analog Comparator 1 Interrupt Flag bit mask. */ -#define AC_AC1IF_bp 1 /* Analog Comparator 1 Interrupt Flag bit position. */ - -#define AC_AC0IF_bm 0x01 /* Analog Comparator 0 Interrupt Flag bit mask. */ -#define AC_AC0IF_bp 0 /* Analog Comparator 0 Interrupt Flag bit position. */ - -/* RTC - Real-Time Counter */ -/* RTC.CTRL bit masks and bit positions */ -#define RTC_PRESCALER_gm 0x07 /* Prescaling Factor group mask. */ -#define RTC_PRESCALER_gp 0 /* Prescaling Factor group position. */ -#define RTC_PRESCALER0_bm (1<<0) /* Prescaling Factor bit 0 mask. */ -#define RTC_PRESCALER0_bp 0 /* Prescaling Factor bit 0 position. */ -#define RTC_PRESCALER1_bm (1<<1) /* Prescaling Factor bit 1 mask. */ -#define RTC_PRESCALER1_bp 1 /* Prescaling Factor bit 1 position. */ -#define RTC_PRESCALER2_bm (1<<2) /* Prescaling Factor bit 2 mask. */ -#define RTC_PRESCALER2_bp 2 /* Prescaling Factor bit 2 position. */ - -/* RTC.STATUS bit masks and bit positions */ -#define RTC_SYNCBUSY_bm 0x01 /* Synchronization Busy Flag bit mask. */ -#define RTC_SYNCBUSY_bp 0 /* Synchronization Busy Flag bit position. */ - -/* RTC.INTCTRL bit masks and bit positions */ -#define RTC_COMPINTLVL_gm 0x0C /* Compare Match Interrupt Level group mask. */ -#define RTC_COMPINTLVL_gp 2 /* Compare Match Interrupt Level group position. */ -#define RTC_COMPINTLVL0_bm (1<<2) /* Compare Match Interrupt Level bit 0 mask. */ -#define RTC_COMPINTLVL0_bp 2 /* Compare Match Interrupt Level bit 0 position. */ -#define RTC_COMPINTLVL1_bm (1<<3) /* Compare Match Interrupt Level bit 1 mask. */ -#define RTC_COMPINTLVL1_bp 3 /* Compare Match Interrupt Level bit 1 position. */ - -#define RTC_OVFINTLVL_gm 0x03 /* Overflow Interrupt Level group mask. */ -#define RTC_OVFINTLVL_gp 0 /* Overflow Interrupt Level group position. */ -#define RTC_OVFINTLVL0_bm (1<<0) /* Overflow Interrupt Level bit 0 mask. */ -#define RTC_OVFINTLVL0_bp 0 /* Overflow Interrupt Level bit 0 position. */ -#define RTC_OVFINTLVL1_bm (1<<1) /* Overflow Interrupt Level bit 1 mask. */ -#define RTC_OVFINTLVL1_bp 1 /* Overflow Interrupt Level bit 1 position. */ - -/* RTC.INTFLAGS bit masks and bit positions */ -#define RTC_COMPIF_bm 0x02 /* Compare Match Interrupt Flag bit mask. */ -#define RTC_COMPIF_bp 1 /* Compare Match Interrupt Flag bit position. */ - -#define RTC_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ -#define RTC_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ - -/* TWI - Two-Wire Interface */ -/* TWI_MASTER.CTRLA bit masks and bit positions */ -#define TWI_MASTER_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ -#define TWI_MASTER_INTLVL_gp 6 /* Interrupt Level group position. */ -#define TWI_MASTER_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ -#define TWI_MASTER_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ -#define TWI_MASTER_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ -#define TWI_MASTER_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ - -#define TWI_MASTER_RIEN_bm 0x20 /* Read Interrupt Enable bit mask. */ -#define TWI_MASTER_RIEN_bp 5 /* Read Interrupt Enable bit position. */ - -#define TWI_MASTER_WIEN_bm 0x10 /* Write Interrupt Enable bit mask. */ -#define TWI_MASTER_WIEN_bp 4 /* Write Interrupt Enable bit position. */ - -#define TWI_MASTER_ENABLE_bm 0x08 /* Enable TWI Master bit mask. */ -#define TWI_MASTER_ENABLE_bp 3 /* Enable TWI Master bit position. */ - -/* TWI_MASTER.CTRLB bit masks and bit positions */ -#define TWI_MASTER_TIMEOUT_gm 0x0C /* Inactive Bus Timeout group mask. */ -#define TWI_MASTER_TIMEOUT_gp 2 /* Inactive Bus Timeout group position. */ -#define TWI_MASTER_TIMEOUT0_bm (1<<2) /* Inactive Bus Timeout bit 0 mask. */ -#define TWI_MASTER_TIMEOUT0_bp 2 /* Inactive Bus Timeout bit 0 position. */ -#define TWI_MASTER_TIMEOUT1_bm (1<<3) /* Inactive Bus Timeout bit 1 mask. */ -#define TWI_MASTER_TIMEOUT1_bp 3 /* Inactive Bus Timeout bit 1 position. */ - -#define TWI_MASTER_QCEN_bm 0x02 /* Quick Command Enable bit mask. */ -#define TWI_MASTER_QCEN_bp 1 /* Quick Command Enable bit position. */ - -#define TWI_MASTER_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ -#define TWI_MASTER_SMEN_bp 0 /* Smart Mode Enable bit position. */ - -/* TWI_MASTER.CTRLC bit masks and bit positions */ -#define TWI_MASTER_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ -#define TWI_MASTER_ACKACT_bp 2 /* Acknowledge Action bit position. */ - -#define TWI_MASTER_CMD_gm 0x03 /* Command group mask. */ -#define TWI_MASTER_CMD_gp 0 /* Command group position. */ -#define TWI_MASTER_CMD0_bm (1<<0) /* Command bit 0 mask. */ -#define TWI_MASTER_CMD0_bp 0 /* Command bit 0 position. */ -#define TWI_MASTER_CMD1_bm (1<<1) /* Command bit 1 mask. */ -#define TWI_MASTER_CMD1_bp 1 /* Command bit 1 position. */ - -/* TWI_MASTER.STATUS bit masks and bit positions */ -#define TWI_MASTER_RIF_bm 0x80 /* Read Interrupt Flag bit mask. */ -#define TWI_MASTER_RIF_bp 7 /* Read Interrupt Flag bit position. */ - -#define TWI_MASTER_WIF_bm 0x40 /* Write Interrupt Flag bit mask. */ -#define TWI_MASTER_WIF_bp 6 /* Write Interrupt Flag bit position. */ - -#define TWI_MASTER_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ -#define TWI_MASTER_CLKHOLD_bp 5 /* Clock Hold bit position. */ - -#define TWI_MASTER_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ -#define TWI_MASTER_RXACK_bp 4 /* Received Acknowledge bit position. */ - -#define TWI_MASTER_ARBLOST_bm 0x08 /* Arbitration Lost bit mask. */ -#define TWI_MASTER_ARBLOST_bp 3 /* Arbitration Lost bit position. */ - -#define TWI_MASTER_BUSERR_bm 0x04 /* Bus Error bit mask. */ -#define TWI_MASTER_BUSERR_bp 2 /* Bus Error bit position. */ - -#define TWI_MASTER_BUSSTATE_gm 0x03 /* Bus State group mask. */ -#define TWI_MASTER_BUSSTATE_gp 0 /* Bus State group position. */ -#define TWI_MASTER_BUSSTATE0_bm (1<<0) /* Bus State bit 0 mask. */ -#define TWI_MASTER_BUSSTATE0_bp 0 /* Bus State bit 0 position. */ -#define TWI_MASTER_BUSSTATE1_bm (1<<1) /* Bus State bit 1 mask. */ -#define TWI_MASTER_BUSSTATE1_bp 1 /* Bus State bit 1 position. */ - -/* TWI_SLAVE.CTRLA bit masks and bit positions */ -#define TWI_SLAVE_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ -#define TWI_SLAVE_INTLVL_gp 6 /* Interrupt Level group position. */ -#define TWI_SLAVE_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ -#define TWI_SLAVE_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ -#define TWI_SLAVE_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ -#define TWI_SLAVE_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ - -#define TWI_SLAVE_DIEN_bm 0x20 /* Data Interrupt Enable bit mask. */ -#define TWI_SLAVE_DIEN_bp 5 /* Data Interrupt Enable bit position. */ - -#define TWI_SLAVE_APIEN_bm 0x10 /* Address/Stop Interrupt Enable bit mask. */ -#define TWI_SLAVE_APIEN_bp 4 /* Address/Stop Interrupt Enable bit position. */ - -#define TWI_SLAVE_ENABLE_bm 0x08 /* Enable TWI Slave bit mask. */ -#define TWI_SLAVE_ENABLE_bp 3 /* Enable TWI Slave bit position. */ - -#define TWI_SLAVE_PIEN_bm 0x04 /* Stop Interrupt Enable bit mask. */ -#define TWI_SLAVE_PIEN_bp 2 /* Stop Interrupt Enable bit position. */ - -#define TWI_SLAVE_PMEN_bm 0x02 /* Promiscuous Mode Enable bit mask. */ -#define TWI_SLAVE_PMEN_bp 1 /* Promiscuous Mode Enable bit position. */ - -#define TWI_SLAVE_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ -#define TWI_SLAVE_SMEN_bp 0 /* Smart Mode Enable bit position. */ - -/* TWI_SLAVE.CTRLB bit masks and bit positions */ -#define TWI_SLAVE_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ -#define TWI_SLAVE_ACKACT_bp 2 /* Acknowledge Action bit position. */ - -#define TWI_SLAVE_CMD_gm 0x03 /* Command group mask. */ -#define TWI_SLAVE_CMD_gp 0 /* Command group position. */ -#define TWI_SLAVE_CMD0_bm (1<<0) /* Command bit 0 mask. */ -#define TWI_SLAVE_CMD0_bp 0 /* Command bit 0 position. */ -#define TWI_SLAVE_CMD1_bm (1<<1) /* Command bit 1 mask. */ -#define TWI_SLAVE_CMD1_bp 1 /* Command bit 1 position. */ - -/* TWI_SLAVE.STATUS bit masks and bit positions */ -#define TWI_SLAVE_DIF_bm 0x80 /* Data Interrupt Flag bit mask. */ -#define TWI_SLAVE_DIF_bp 7 /* Data Interrupt Flag bit position. */ - -#define TWI_SLAVE_APIF_bm 0x40 /* Address/Stop Interrupt Flag bit mask. */ -#define TWI_SLAVE_APIF_bp 6 /* Address/Stop Interrupt Flag bit position. */ - -#define TWI_SLAVE_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ -#define TWI_SLAVE_CLKHOLD_bp 5 /* Clock Hold bit position. */ - -#define TWI_SLAVE_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ -#define TWI_SLAVE_RXACK_bp 4 /* Received Acknowledge bit position. */ - -#define TWI_SLAVE_COLL_bm 0x08 /* Collision bit mask. */ -#define TWI_SLAVE_COLL_bp 3 /* Collision bit position. */ - -#define TWI_SLAVE_BUSERR_bm 0x04 /* Bus Error bit mask. */ -#define TWI_SLAVE_BUSERR_bp 2 /* Bus Error bit position. */ - -#define TWI_SLAVE_DIR_bm 0x02 /* Read/Write Direction bit mask. */ -#define TWI_SLAVE_DIR_bp 1 /* Read/Write Direction bit position. */ - -#define TWI_SLAVE_AP_bm 0x01 /* Slave Address or Stop bit mask. */ -#define TWI_SLAVE_AP_bp 0 /* Slave Address or Stop bit position. */ - -/* TWI_SLAVE.ADDRMASK bit masks and bit positions */ -#define TWI_SLAVE_ADDRMASK_gm 0xFE /* Address Mask group mask. */ -#define TWI_SLAVE_ADDRMASK_gp 1 /* Address Mask group position. */ -#define TWI_SLAVE_ADDRMASK0_bm (1<<1) /* Address Mask bit 0 mask. */ -#define TWI_SLAVE_ADDRMASK0_bp 1 /* Address Mask bit 0 position. */ -#define TWI_SLAVE_ADDRMASK1_bm (1<<2) /* Address Mask bit 1 mask. */ -#define TWI_SLAVE_ADDRMASK1_bp 2 /* Address Mask bit 1 position. */ -#define TWI_SLAVE_ADDRMASK2_bm (1<<3) /* Address Mask bit 2 mask. */ -#define TWI_SLAVE_ADDRMASK2_bp 3 /* Address Mask bit 2 position. */ -#define TWI_SLAVE_ADDRMASK3_bm (1<<4) /* Address Mask bit 3 mask. */ -#define TWI_SLAVE_ADDRMASK3_bp 4 /* Address Mask bit 3 position. */ -#define TWI_SLAVE_ADDRMASK4_bm (1<<5) /* Address Mask bit 4 mask. */ -#define TWI_SLAVE_ADDRMASK4_bp 5 /* Address Mask bit 4 position. */ -#define TWI_SLAVE_ADDRMASK5_bm (1<<6) /* Address Mask bit 5 mask. */ -#define TWI_SLAVE_ADDRMASK5_bp 6 /* Address Mask bit 5 position. */ -#define TWI_SLAVE_ADDRMASK6_bm (1<<7) /* Address Mask bit 6 mask. */ -#define TWI_SLAVE_ADDRMASK6_bp 7 /* Address Mask bit 6 position. */ - -#define TWI_SLAVE_ADDREN_bm 0x01 /* Address Enable bit mask. */ -#define TWI_SLAVE_ADDREN_bp 0 /* Address Enable bit position. */ - -/* TWI.CTRL bit masks and bit positions */ -#define TWI_SDAHOLD_gm 0x06 /* SDA Hold Time Enable group mask. */ -#define TWI_SDAHOLD_gp 1 /* SDA Hold Time Enable group position. */ -#define TWI_SDAHOLD0_bm (1<<1) /* SDA Hold Time Enable bit 0 mask. */ -#define TWI_SDAHOLD0_bp 1 /* SDA Hold Time Enable bit 0 position. */ -#define TWI_SDAHOLD1_bm (1<<2) /* SDA Hold Time Enable bit 1 mask. */ -#define TWI_SDAHOLD1_bp 2 /* SDA Hold Time Enable bit 1 position. */ - -#define TWI_EDIEN_bm 0x01 /* External Driver Interface Enable bit mask. */ -#define TWI_EDIEN_bp 0 /* External Driver Interface Enable bit position. */ - -/* USB - USB */ -/* USB_EP.STATUS bit masks and bit positions */ -#define USB_EP_STALLF_bm 0x80 /* Endpoint Stall Flag bit mask. */ -#define USB_EP_STALLF_bp 7 /* Endpoint Stall Flag bit position. */ - -#define USB_EP_CRC_bm 0x80 /* CRC Error Flag bit mask. */ -#define USB_EP_CRC_bp 7 /* CRC Error Flag bit position. */ - -#define USB_EP_UNF_bm 0x40 /* Underflow Enpoint FLag bit mask. */ -#define USB_EP_UNF_bp 6 /* Underflow Enpoint FLag bit position. */ - -#define USB_EP_OVF_bm 0x40 /* Overflow Enpoint Flag for Output Endpoints bit mask. */ -#define USB_EP_OVF_bp 6 /* Overflow Enpoint Flag for Output Endpoints bit position. */ - -#define USB_EP_TRNCOMPL0_bm 0x20 /* Transaction Complete 0 Flag bit mask. */ -#define USB_EP_TRNCOMPL0_bp 5 /* Transaction Complete 0 Flag bit position. */ - -#define USB_EP_TRNCOMPL1_bm 0x10 /* Transaction Complete 1 Flag bit mask. */ -#define USB_EP_TRNCOMPL1_bp 4 /* Transaction Complete 1 Flag bit position. */ - -#define USB_EP_SETUP_bm 0x10 /* SETUP Transaction Complete Flag bit mask. */ -#define USB_EP_SETUP_bp 4 /* SETUP Transaction Complete Flag bit position. */ - -#define USB_EP_BANK_bm 0x08 /* Bank Select bit mask. */ -#define USB_EP_BANK_bp 3 /* Bank Select bit position. */ - -#define USB_EP_BUSNACK1_bm 0x04 /* Data Buffer 1 Not Acknowledge bit mask. */ -#define USB_EP_BUSNACK1_bp 2 /* Data Buffer 1 Not Acknowledge bit position. */ - -#define USB_EP_BUSNACK0_bm 0x02 /* Data Buffer 0 Not Acknowledge bit mask. */ -#define USB_EP_BUSNACK0_bp 1 /* Data Buffer 0 Not Acknowledge bit position. */ - -#define USB_EP_TOGGLE_bm 0x01 /* Data Toggle bit mask. */ -#define USB_EP_TOGGLE_bp 0 /* Data Toggle bit position. */ - -/* USB_EP.CTRL bit masks and bit positions */ -#define USB_EP_TYPE_gm 0xC0 /* Endpoint Type group mask. */ -#define USB_EP_TYPE_gp 6 /* Endpoint Type group position. */ -#define USB_EP_TYPE0_bm (1<<6) /* Endpoint Type bit 0 mask. */ -#define USB_EP_TYPE0_bp 6 /* Endpoint Type bit 0 position. */ -#define USB_EP_TYPE1_bm (1<<7) /* Endpoint Type bit 1 mask. */ -#define USB_EP_TYPE1_bp 7 /* Endpoint Type bit 1 position. */ - -#define USB_EP_MULTIPKT_bm 0x20 /* Multi Packet Transfer Enable bit mask. */ -#define USB_EP_MULTIPKT_bp 5 /* Multi Packet Transfer Enable bit position. */ - -#define USB_EP_PINGPONG_bm 0x10 /* Ping-Pong Enable bit mask. */ -#define USB_EP_PINGPONG_bp 4 /* Ping-Pong Enable bit position. */ - -#define USB_EP_INTDSBL_bm 0x08 /* Interrupt Disable bit mask. */ -#define USB_EP_INTDSBL_bp 3 /* Interrupt Disable bit position. */ - -#define USB_EP_STALL_bm 0x04 /* Data Stall bit mask. */ -#define USB_EP_STALL_bp 2 /* Data Stall bit position. */ - -#define USB_EP_BUFSIZE_gm 0x07 /* Data Buffer Size group mask. */ -#define USB_EP_BUFSIZE_gp 0 /* Data Buffer Size group position. */ -#define USB_EP_BUFSIZE0_bm (1<<0) /* Data Buffer Size bit 0 mask. */ -#define USB_EP_BUFSIZE0_bp 0 /* Data Buffer Size bit 0 position. */ -#define USB_EP_BUFSIZE1_bm (1<<1) /* Data Buffer Size bit 1 mask. */ -#define USB_EP_BUFSIZE1_bp 1 /* Data Buffer Size bit 1 position. */ -#define USB_EP_BUFSIZE2_bm (1<<2) /* Data Buffer Size bit 2 mask. */ -#define USB_EP_BUFSIZE2_bp 2 /* Data Buffer Size bit 2 position. */ - -/* USB_EP.CNT bit masks and bit positions */ -#define USB_EP_ZLP_bm 0x8000 /* Zero Length Packet bit mask. */ -#define USB_EP_ZLP_bp 15 /* Zero Length Packet bit position. */ - -/* USB.CTRLA bit masks and bit positions */ -#define USB_ENABLE_bm 0x80 /* USB Enable bit mask. */ -#define USB_ENABLE_bp 7 /* USB Enable bit position. */ - -#define USB_SPEED_bm 0x40 /* Speed Select bit mask. */ -#define USB_SPEED_bp 6 /* Speed Select bit position. */ - -#define USB_FIFOEN_bm 0x20 /* USB FIFO Enable bit mask. */ -#define USB_FIFOEN_bp 5 /* USB FIFO Enable bit position. */ - -#define USB_STFRNUM_bm 0x10 /* Store Frame Number Enable bit mask. */ -#define USB_STFRNUM_bp 4 /* Store Frame Number Enable bit position. */ - -#define USB_MAXEP_gm 0x0F /* Maximum Endpoint Addresses group mask. */ -#define USB_MAXEP_gp 0 /* Maximum Endpoint Addresses group position. */ -#define USB_MAXEP0_bm (1<<0) /* Maximum Endpoint Addresses bit 0 mask. */ -#define USB_MAXEP0_bp 0 /* Maximum Endpoint Addresses bit 0 position. */ -#define USB_MAXEP1_bm (1<<1) /* Maximum Endpoint Addresses bit 1 mask. */ -#define USB_MAXEP1_bp 1 /* Maximum Endpoint Addresses bit 1 position. */ -#define USB_MAXEP2_bm (1<<2) /* Maximum Endpoint Addresses bit 2 mask. */ -#define USB_MAXEP2_bp 2 /* Maximum Endpoint Addresses bit 2 position. */ -#define USB_MAXEP3_bm (1<<3) /* Maximum Endpoint Addresses bit 3 mask. */ -#define USB_MAXEP3_bp 3 /* Maximum Endpoint Addresses bit 3 position. */ - -/* USB.CTRLB bit masks and bit positions */ -#define USB_PULLRST_bm 0x10 /* Pull during Reset bit mask. */ -#define USB_PULLRST_bp 4 /* Pull during Reset bit position. */ - -#define USB_RWAKEUP_bm 0x04 /* Remote Wake-up bit mask. */ -#define USB_RWAKEUP_bp 2 /* Remote Wake-up bit position. */ - -#define USB_GNACK_bm 0x02 /* Global NACK bit mask. */ -#define USB_GNACK_bp 1 /* Global NACK bit position. */ - -#define USB_ATTACH_bm 0x01 /* Attach bit mask. */ -#define USB_ATTACH_bp 0 /* Attach bit position. */ - -/* USB.STATUS bit masks and bit positions */ -#define USB_URESUME_bm 0x08 /* Upstream Resume bit mask. */ -#define USB_URESUME_bp 3 /* Upstream Resume bit position. */ - -#define USB_RESUME_bm 0x04 /* Resume bit mask. */ -#define USB_RESUME_bp 2 /* Resume bit position. */ - -#define USB_SUSPEND_bm 0x02 /* Bus Suspended bit mask. */ -#define USB_SUSPEND_bp 1 /* Bus Suspended bit position. */ - -#define USB_BUSRST_bm 0x01 /* Bus Reset bit mask. */ -#define USB_BUSRST_bp 0 /* Bus Reset bit position. */ - -/* USB.ADDR bit masks and bit positions */ -#define USB_ADDR_gm 0x7F /* Device Address group mask. */ -#define USB_ADDR_gp 0 /* Device Address group position. */ -#define USB_ADDR0_bm (1<<0) /* Device Address bit 0 mask. */ -#define USB_ADDR0_bp 0 /* Device Address bit 0 position. */ -#define USB_ADDR1_bm (1<<1) /* Device Address bit 1 mask. */ -#define USB_ADDR1_bp 1 /* Device Address bit 1 position. */ -#define USB_ADDR2_bm (1<<2) /* Device Address bit 2 mask. */ -#define USB_ADDR2_bp 2 /* Device Address bit 2 position. */ -#define USB_ADDR3_bm (1<<3) /* Device Address bit 3 mask. */ -#define USB_ADDR3_bp 3 /* Device Address bit 3 position. */ -#define USB_ADDR4_bm (1<<4) /* Device Address bit 4 mask. */ -#define USB_ADDR4_bp 4 /* Device Address bit 4 position. */ -#define USB_ADDR5_bm (1<<5) /* Device Address bit 5 mask. */ -#define USB_ADDR5_bp 5 /* Device Address bit 5 position. */ -#define USB_ADDR6_bm (1<<6) /* Device Address bit 6 mask. */ -#define USB_ADDR6_bp 6 /* Device Address bit 6 position. */ - -/* USB.FIFOWP bit masks and bit positions */ -#define USB_FIFOWP_gm 0x1F /* FIFO Write Pointer group mask. */ -#define USB_FIFOWP_gp 0 /* FIFO Write Pointer group position. */ -#define USB_FIFOWP0_bm (1<<0) /* FIFO Write Pointer bit 0 mask. */ -#define USB_FIFOWP0_bp 0 /* FIFO Write Pointer bit 0 position. */ -#define USB_FIFOWP1_bm (1<<1) /* FIFO Write Pointer bit 1 mask. */ -#define USB_FIFOWP1_bp 1 /* FIFO Write Pointer bit 1 position. */ -#define USB_FIFOWP2_bm (1<<2) /* FIFO Write Pointer bit 2 mask. */ -#define USB_FIFOWP2_bp 2 /* FIFO Write Pointer bit 2 position. */ -#define USB_FIFOWP3_bm (1<<3) /* FIFO Write Pointer bit 3 mask. */ -#define USB_FIFOWP3_bp 3 /* FIFO Write Pointer bit 3 position. */ -#define USB_FIFOWP4_bm (1<<4) /* FIFO Write Pointer bit 4 mask. */ -#define USB_FIFOWP4_bp 4 /* FIFO Write Pointer bit 4 position. */ - -/* USB.FIFORP bit masks and bit positions */ -#define USB_FIFORP_gm 0x1F /* FIFO Read Pointer group mask. */ -#define USB_FIFORP_gp 0 /* FIFO Read Pointer group position. */ -#define USB_FIFORP0_bm (1<<0) /* FIFO Read Pointer bit 0 mask. */ -#define USB_FIFORP0_bp 0 /* FIFO Read Pointer bit 0 position. */ -#define USB_FIFORP1_bm (1<<1) /* FIFO Read Pointer bit 1 mask. */ -#define USB_FIFORP1_bp 1 /* FIFO Read Pointer bit 1 position. */ -#define USB_FIFORP2_bm (1<<2) /* FIFO Read Pointer bit 2 mask. */ -#define USB_FIFORP2_bp 2 /* FIFO Read Pointer bit 2 position. */ -#define USB_FIFORP3_bm (1<<3) /* FIFO Read Pointer bit 3 mask. */ -#define USB_FIFORP3_bp 3 /* FIFO Read Pointer bit 3 position. */ -#define USB_FIFORP4_bm (1<<4) /* FIFO Read Pointer bit 4 mask. */ -#define USB_FIFORP4_bp 4 /* FIFO Read Pointer bit 4 position. */ - -/* USB.INTCTRLA bit masks and bit positions */ -#define USB_SOFIE_bm 0x80 /* Start Of Frame Interrupt Enable bit mask. */ -#define USB_SOFIE_bp 7 /* Start Of Frame Interrupt Enable bit position. */ - -#define USB_BUSEVIE_bm 0x40 /* Bus Event Interrupt Enable bit mask. */ -#define USB_BUSEVIE_bp 6 /* Bus Event Interrupt Enable bit position. */ - -#define USB_BUSERRIE_bm 0x20 /* Bus Error Interrupt Enable bit mask. */ -#define USB_BUSERRIE_bp 5 /* Bus Error Interrupt Enable bit position. */ - -#define USB_STALLIE_bm 0x10 /* STALL Interrupt Enable bit mask. */ -#define USB_STALLIE_bp 4 /* STALL Interrupt Enable bit position. */ - -#define USB_INTLVL_gm 0x03 /* Interrupt Level group mask. */ -#define USB_INTLVL_gp 0 /* Interrupt Level group position. */ -#define USB_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */ -#define USB_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */ -#define USB_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ -#define USB_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */ - -/* USB.INTCTRLB bit masks and bit positions */ -#define USB_TRNIE_bm 0x02 /* Transaction Complete Interrupt Enable bit mask. */ -#define USB_TRNIE_bp 1 /* Transaction Complete Interrupt Enable bit position. */ - -#define USB_SETUPIE_bm 0x01 /* SETUP Transaction Complete Interrupt Enable bit mask. */ -#define USB_SETUPIE_bp 0 /* SETUP Transaction Complete Interrupt Enable bit position. */ - -/* USB.INTFLAGSACLR bit masks and bit positions */ -#define USB_SOFIF_bm 0x80 /* Start Of Frame Interrupt Flag bit mask. */ -#define USB_SOFIF_bp 7 /* Start Of Frame Interrupt Flag bit position. */ - -#define USB_SUSPENDIF_bm 0x40 /* Suspend Interrupt Flag bit mask. */ -#define USB_SUSPENDIF_bp 6 /* Suspend Interrupt Flag bit position. */ - -#define USB_RESUMEIF_bm 0x20 /* Resume Interrupt Flag bit mask. */ -#define USB_RESUMEIF_bp 5 /* Resume Interrupt Flag bit position. */ - -#define USB_RSTIF_bm 0x10 /* Reset Interrupt Flag bit mask. */ -#define USB_RSTIF_bp 4 /* Reset Interrupt Flag bit position. */ - -#define USB_CRCIF_bm 0x08 /* Isochronous CRC Error Interrupt Flag bit mask. */ -#define USB_CRCIF_bp 3 /* Isochronous CRC Error Interrupt Flag bit position. */ - -#define USB_UNFIF_bm 0x04 /* Underflow Interrupt Flag bit mask. */ -#define USB_UNFIF_bp 2 /* Underflow Interrupt Flag bit position. */ - -#define USB_OVFIF_bm 0x02 /* Overflow Interrupt Flag bit mask. */ -#define USB_OVFIF_bp 1 /* Overflow Interrupt Flag bit position. */ - -#define USB_STALLIF_bm 0x01 /* STALL Interrupt Flag bit mask. */ -#define USB_STALLIF_bp 0 /* STALL Interrupt Flag bit position. */ - -/* USB.INTFLAGSASET bit masks and bit positions */ -/* USB_SOFIF Predefined. */ -/* USB_SOFIF Predefined. */ - -/* USB_SUSPENDIF Predefined. */ -/* USB_SUSPENDIF Predefined. */ - -/* USB_RESUMEIF Predefined. */ -/* USB_RESUMEIF Predefined. */ - -/* USB_RSTIF Predefined. */ -/* USB_RSTIF Predefined. */ - -/* USB_CRCIF Predefined. */ -/* USB_CRCIF Predefined. */ - -/* USB_UNFIF Predefined. */ -/* USB_UNFIF Predefined. */ - -/* USB_OVFIF Predefined. */ -/* USB_OVFIF Predefined. */ - -/* USB_STALLIF Predefined. */ -/* USB_STALLIF Predefined. */ - -/* USB.INTFLAGSBCLR bit masks and bit positions */ -#define USB_TRNIF_bm 0x02 /* Transaction Complete Interrupt Flag bit mask. */ -#define USB_TRNIF_bp 1 /* Transaction Complete Interrupt Flag bit position. */ - -#define USB_SETUPIF_bm 0x01 /* SETUP Transaction Complete Interrupt Flag bit mask. */ -#define USB_SETUPIF_bp 0 /* SETUP Transaction Complete Interrupt Flag bit position. */ - -/* USB.INTFLAGSBSET bit masks and bit positions */ -/* USB_TRNIF Predefined. */ -/* USB_TRNIF Predefined. */ - -/* USB_SETUPIF Predefined. */ -/* USB_SETUPIF Predefined. */ - -/* PORT - I/O Port Configuration */ -/* PORT.INTCTRL bit masks and bit positions */ -#define PORT_INT1LVL_gm 0x0C /* Port Interrupt 1 Level group mask. */ -#define PORT_INT1LVL_gp 2 /* Port Interrupt 1 Level group position. */ -#define PORT_INT1LVL0_bm (1<<2) /* Port Interrupt 1 Level bit 0 mask. */ -#define PORT_INT1LVL0_bp 2 /* Port Interrupt 1 Level bit 0 position. */ -#define PORT_INT1LVL1_bm (1<<3) /* Port Interrupt 1 Level bit 1 mask. */ -#define PORT_INT1LVL1_bp 3 /* Port Interrupt 1 Level bit 1 position. */ - -#define PORT_INT0LVL_gm 0x03 /* Port Interrupt 0 Level group mask. */ -#define PORT_INT0LVL_gp 0 /* Port Interrupt 0 Level group position. */ -#define PORT_INT0LVL0_bm (1<<0) /* Port Interrupt 0 Level bit 0 mask. */ -#define PORT_INT0LVL0_bp 0 /* Port Interrupt 0 Level bit 0 position. */ -#define PORT_INT0LVL1_bm (1<<1) /* Port Interrupt 0 Level bit 1 mask. */ -#define PORT_INT0LVL1_bp 1 /* Port Interrupt 0 Level bit 1 position. */ - -/* PORT.INTFLAGS bit masks and bit positions */ -#define PORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ -#define PORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ - -#define PORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ -#define PORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ - -/* PORT.REMAP bit masks and bit positions */ -#define PORT_SPI_bm 0x20 /* SPI bit mask. */ -#define PORT_SPI_bp 5 /* SPI bit position. */ - -#define PORT_USART0_bm 0x10 /* USART0 bit mask. */ -#define PORT_USART0_bp 4 /* USART0 bit position. */ - -#define PORT_TC0D_bm 0x08 /* Timer/Counter 0 Output Compare D bit mask. */ -#define PORT_TC0D_bp 3 /* Timer/Counter 0 Output Compare D bit position. */ - -#define PORT_TC0C_bm 0x04 /* Timer/Counter 0 Output Compare C bit mask. */ -#define PORT_TC0C_bp 2 /* Timer/Counter 0 Output Compare C bit position. */ - -#define PORT_TC0B_bm 0x02 /* Timer/Counter 0 Output Compare B bit mask. */ -#define PORT_TC0B_bp 1 /* Timer/Counter 0 Output Compare B bit position. */ - -#define PORT_TC0A_bm 0x01 /* Timer/Counter 0 Output Compare A bit mask. */ -#define PORT_TC0A_bp 0 /* Timer/Counter 0 Output Compare A bit position. */ - -/* PORT.PIN0CTRL bit masks and bit positions */ -#define PORT_SRLEN_bm 0x80 /* Slew Rate Enable bit mask. */ -#define PORT_SRLEN_bp 7 /* Slew Rate Enable bit position. */ - -#define PORT_INVEN_bm 0x40 /* Inverted I/O Enable bit mask. */ -#define PORT_INVEN_bp 6 /* Inverted I/O Enable bit position. */ - -#define PORT_OPC_gm 0x38 /* Output/Pull Configuration group mask. */ -#define PORT_OPC_gp 3 /* Output/Pull Configuration group position. */ -#define PORT_OPC0_bm (1<<3) /* Output/Pull Configuration bit 0 mask. */ -#define PORT_OPC0_bp 3 /* Output/Pull Configuration bit 0 position. */ -#define PORT_OPC1_bm (1<<4) /* Output/Pull Configuration bit 1 mask. */ -#define PORT_OPC1_bp 4 /* Output/Pull Configuration bit 1 position. */ -#define PORT_OPC2_bm (1<<5) /* Output/Pull Configuration bit 2 mask. */ -#define PORT_OPC2_bp 5 /* Output/Pull Configuration bit 2 position. */ - -#define PORT_ISC_gm 0x07 /* Input/Sense Configuration group mask. */ -#define PORT_ISC_gp 0 /* Input/Sense Configuration group position. */ -#define PORT_ISC0_bm (1<<0) /* Input/Sense Configuration bit 0 mask. */ -#define PORT_ISC0_bp 0 /* Input/Sense Configuration bit 0 position. */ -#define PORT_ISC1_bm (1<<1) /* Input/Sense Configuration bit 1 mask. */ -#define PORT_ISC1_bp 1 /* Input/Sense Configuration bit 1 position. */ -#define PORT_ISC2_bm (1<<2) /* Input/Sense Configuration bit 2 mask. */ -#define PORT_ISC2_bp 2 /* Input/Sense Configuration bit 2 position. */ - -/* PORT.PIN1CTRL bit masks and bit positions */ -/* PORT_SRLEN Predefined. */ -/* PORT_SRLEN Predefined. */ - -/* PORT_INVEN Predefined. */ -/* PORT_INVEN Predefined. */ - -/* PORT_OPC Predefined. */ -/* PORT_OPC Predefined. */ - -/* PORT_ISC Predefined. */ -/* PORT_ISC Predefined. */ - -/* PORT.PIN2CTRL bit masks and bit positions */ -/* PORT_SRLEN Predefined. */ -/* PORT_SRLEN Predefined. */ - -/* PORT_INVEN Predefined. */ -/* PORT_INVEN Predefined. */ - -/* PORT_OPC Predefined. */ -/* PORT_OPC Predefined. */ - -/* PORT_ISC Predefined. */ -/* PORT_ISC Predefined. */ - -/* PORT.PIN3CTRL bit masks and bit positions */ -/* PORT_SRLEN Predefined. */ -/* PORT_SRLEN Predefined. */ - -/* PORT_INVEN Predefined. */ -/* PORT_INVEN Predefined. */ - -/* PORT_OPC Predefined. */ -/* PORT_OPC Predefined. */ - -/* PORT_ISC Predefined. */ -/* PORT_ISC Predefined. */ - -/* PORT.PIN4CTRL bit masks and bit positions */ -/* PORT_SRLEN Predefined. */ -/* PORT_SRLEN Predefined. */ - -/* PORT_INVEN Predefined. */ -/* PORT_INVEN Predefined. */ - -/* PORT_OPC Predefined. */ -/* PORT_OPC Predefined. */ - -/* PORT_ISC Predefined. */ -/* PORT_ISC Predefined. */ - -/* PORT.PIN5CTRL bit masks and bit positions */ -/* PORT_SRLEN Predefined. */ -/* PORT_SRLEN Predefined. */ - -/* PORT_INVEN Predefined. */ -/* PORT_INVEN Predefined. */ - -/* PORT_OPC Predefined. */ -/* PORT_OPC Predefined. */ - -/* PORT_ISC Predefined. */ -/* PORT_ISC Predefined. */ - -/* PORT.PIN6CTRL bit masks and bit positions */ -/* PORT_SRLEN Predefined. */ -/* PORT_SRLEN Predefined. */ - -/* PORT_INVEN Predefined. */ -/* PORT_INVEN Predefined. */ - -/* PORT_OPC Predefined. */ -/* PORT_OPC Predefined. */ - -/* PORT_ISC Predefined. */ -/* PORT_ISC Predefined. */ - -/* PORT.PIN7CTRL bit masks and bit positions */ -/* PORT_SRLEN Predefined. */ -/* PORT_SRLEN Predefined. */ - -/* PORT_INVEN Predefined. */ -/* PORT_INVEN Predefined. */ - -/* PORT_OPC Predefined. */ -/* PORT_OPC Predefined. */ - -/* PORT_ISC Predefined. */ -/* PORT_ISC Predefined. */ - -/* TC - 16-bit Timer/Counter With PWM */ -/* TC0.CTRLA bit masks and bit positions */ -#define TC0_CLKSEL_gm 0x0F /* Clock Selection group mask. */ -#define TC0_CLKSEL_gp 0 /* Clock Selection group position. */ -#define TC0_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ -#define TC0_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ -#define TC0_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ -#define TC0_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ -#define TC0_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ -#define TC0_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ -#define TC0_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ -#define TC0_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ - -/* TC0.CTRLB bit masks and bit positions */ -#define TC0_CCDEN_bm 0x80 /* Compare or Capture D Enable bit mask. */ -#define TC0_CCDEN_bp 7 /* Compare or Capture D Enable bit position. */ - -#define TC0_CCCEN_bm 0x40 /* Compare or Capture C Enable bit mask. */ -#define TC0_CCCEN_bp 6 /* Compare or Capture C Enable bit position. */ - -#define TC0_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ -#define TC0_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ - -#define TC0_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ -#define TC0_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ - -#define TC0_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ -#define TC0_WGMODE_gp 0 /* Waveform generation mode group position. */ -#define TC0_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ -#define TC0_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ -#define TC0_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ -#define TC0_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ -#define TC0_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ -#define TC0_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ - -/* TC0.CTRLC bit masks and bit positions */ -#define TC0_CMPD_bm 0x08 /* Compare D Output Value bit mask. */ -#define TC0_CMPD_bp 3 /* Compare D Output Value bit position. */ - -#define TC0_CMPC_bm 0x04 /* Compare C Output Value bit mask. */ -#define TC0_CMPC_bp 2 /* Compare C Output Value bit position. */ - -#define TC0_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ -#define TC0_CMPB_bp 1 /* Compare B Output Value bit position. */ - -#define TC0_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ -#define TC0_CMPA_bp 0 /* Compare A Output Value bit position. */ - -/* TC0.CTRLD bit masks and bit positions */ -#define TC0_EVACT_gm 0xE0 /* Event Action group mask. */ -#define TC0_EVACT_gp 5 /* Event Action group position. */ -#define TC0_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ -#define TC0_EVACT0_bp 5 /* Event Action bit 0 position. */ -#define TC0_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ -#define TC0_EVACT1_bp 6 /* Event Action bit 1 position. */ -#define TC0_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ -#define TC0_EVACT2_bp 7 /* Event Action bit 2 position. */ - -#define TC0_EVDLY_bm 0x10 /* Event Delay bit mask. */ -#define TC0_EVDLY_bp 4 /* Event Delay bit position. */ - -#define TC0_EVSEL_gm 0x0F /* Event Source Select group mask. */ -#define TC0_EVSEL_gp 0 /* Event Source Select group position. */ -#define TC0_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ -#define TC0_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ -#define TC0_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ -#define TC0_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ -#define TC0_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ -#define TC0_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ -#define TC0_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ -#define TC0_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ - -/* TC0.CTRLE bit masks and bit positions */ -#define TC0_BYTEM_gm 0x03 /* Byte Mode group mask. */ -#define TC0_BYTEM_gp 0 /* Byte Mode group position. */ -#define TC0_BYTEM0_bm (1<<0) /* Byte Mode bit 0 mask. */ -#define TC0_BYTEM0_bp 0 /* Byte Mode bit 0 position. */ -#define TC0_BYTEM1_bm (1<<1) /* Byte Mode bit 1 mask. */ -#define TC0_BYTEM1_bp 1 /* Byte Mode bit 1 position. */ - -/* TC0.INTCTRLA bit masks and bit positions */ -#define TC0_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ -#define TC0_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ -#define TC0_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ -#define TC0_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ -#define TC0_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ -#define TC0_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ - -#define TC0_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ -#define TC0_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ -#define TC0_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ -#define TC0_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ -#define TC0_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ -#define TC0_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ - -/* TC0.INTCTRLB bit masks and bit positions */ -#define TC0_CCDINTLVL_gm 0xC0 /* Compare or Capture D Interrupt Level group mask. */ -#define TC0_CCDINTLVL_gp 6 /* Compare or Capture D Interrupt Level group position. */ -#define TC0_CCDINTLVL0_bm (1<<6) /* Compare or Capture D Interrupt Level bit 0 mask. */ -#define TC0_CCDINTLVL0_bp 6 /* Compare or Capture D Interrupt Level bit 0 position. */ -#define TC0_CCDINTLVL1_bm (1<<7) /* Compare or Capture D Interrupt Level bit 1 mask. */ -#define TC0_CCDINTLVL1_bp 7 /* Compare or Capture D Interrupt Level bit 1 position. */ - -#define TC0_CCCINTLVL_gm 0x30 /* Compare or Capture C Interrupt Level group mask. */ -#define TC0_CCCINTLVL_gp 4 /* Compare or Capture C Interrupt Level group position. */ -#define TC0_CCCINTLVL0_bm (1<<4) /* Compare or Capture C Interrupt Level bit 0 mask. */ -#define TC0_CCCINTLVL0_bp 4 /* Compare or Capture C Interrupt Level bit 0 position. */ -#define TC0_CCCINTLVL1_bm (1<<5) /* Compare or Capture C Interrupt Level bit 1 mask. */ -#define TC0_CCCINTLVL1_bp 5 /* Compare or Capture C Interrupt Level bit 1 position. */ - -#define TC0_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ -#define TC0_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ -#define TC0_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ -#define TC0_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ -#define TC0_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ -#define TC0_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ - -#define TC0_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ -#define TC0_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ -#define TC0_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ -#define TC0_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ -#define TC0_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ -#define TC0_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ - -/* TC0.CTRLFCLR bit masks and bit positions */ -#define TC0_CMD_gm 0x0C /* Command group mask. */ -#define TC0_CMD_gp 2 /* Command group position. */ -#define TC0_CMD0_bm (1<<2) /* Command bit 0 mask. */ -#define TC0_CMD0_bp 2 /* Command bit 0 position. */ -#define TC0_CMD1_bm (1<<3) /* Command bit 1 mask. */ -#define TC0_CMD1_bp 3 /* Command bit 1 position. */ - -#define TC0_LUPD_bm 0x02 /* Lock Update bit mask. */ -#define TC0_LUPD_bp 1 /* Lock Update bit position. */ - -#define TC0_DIR_bm 0x01 /* Direction bit mask. */ -#define TC0_DIR_bp 0 /* Direction bit position. */ - -/* TC0.CTRLFSET bit masks and bit positions */ -/* TC0_CMD Predefined. */ -/* TC0_CMD Predefined. */ - -/* TC0_LUPD Predefined. */ -/* TC0_LUPD Predefined. */ - -/* TC0_DIR Predefined. */ -/* TC0_DIR Predefined. */ - -/* TC0.CTRLGCLR bit masks and bit positions */ -#define TC0_CCDBV_bm 0x10 /* Compare or Capture D Buffer Valid bit mask. */ -#define TC0_CCDBV_bp 4 /* Compare or Capture D Buffer Valid bit position. */ - -#define TC0_CCCBV_bm 0x08 /* Compare or Capture C Buffer Valid bit mask. */ -#define TC0_CCCBV_bp 3 /* Compare or Capture C Buffer Valid bit position. */ - -#define TC0_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ -#define TC0_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ - -#define TC0_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ -#define TC0_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ - -#define TC0_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ -#define TC0_PERBV_bp 0 /* Period Buffer Valid bit position. */ - -/* TC0.CTRLGSET bit masks and bit positions */ -/* TC0_CCDBV Predefined. */ -/* TC0_CCDBV Predefined. */ - -/* TC0_CCCBV Predefined. */ -/* TC0_CCCBV Predefined. */ - -/* TC0_CCBBV Predefined. */ -/* TC0_CCBBV Predefined. */ - -/* TC0_CCABV Predefined. */ -/* TC0_CCABV Predefined. */ - -/* TC0_PERBV Predefined. */ -/* TC0_PERBV Predefined. */ - -/* TC0.INTFLAGS bit masks and bit positions */ -#define TC0_CCDIF_bm 0x80 /* Compare or Capture D Interrupt Flag bit mask. */ -#define TC0_CCDIF_bp 7 /* Compare or Capture D Interrupt Flag bit position. */ - -#define TC0_CCCIF_bm 0x40 /* Compare or Capture C Interrupt Flag bit mask. */ -#define TC0_CCCIF_bp 6 /* Compare or Capture C Interrupt Flag bit position. */ - -#define TC0_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ -#define TC0_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ - -#define TC0_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ -#define TC0_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ - -#define TC0_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ -#define TC0_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ - -#define TC0_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ -#define TC0_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ - -/* TC1.CTRLA bit masks and bit positions */ -#define TC1_CLKSEL_gm 0x0F /* Clock Selection group mask. */ -#define TC1_CLKSEL_gp 0 /* Clock Selection group position. */ -#define TC1_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ -#define TC1_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ -#define TC1_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ -#define TC1_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ -#define TC1_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ -#define TC1_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ -#define TC1_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ -#define TC1_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ - -/* TC1.CTRLB bit masks and bit positions */ -#define TC1_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ -#define TC1_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ - -#define TC1_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ -#define TC1_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ - -#define TC1_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ -#define TC1_WGMODE_gp 0 /* Waveform generation mode group position. */ -#define TC1_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ -#define TC1_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ -#define TC1_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ -#define TC1_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ -#define TC1_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ -#define TC1_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ - -/* TC1.CTRLC bit masks and bit positions */ -#define TC1_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ -#define TC1_CMPB_bp 1 /* Compare B Output Value bit position. */ - -#define TC1_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ -#define TC1_CMPA_bp 0 /* Compare A Output Value bit position. */ - -/* TC1.CTRLD bit masks and bit positions */ -#define TC1_EVACT_gm 0xE0 /* Event Action group mask. */ -#define TC1_EVACT_gp 5 /* Event Action group position. */ -#define TC1_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ -#define TC1_EVACT0_bp 5 /* Event Action bit 0 position. */ -#define TC1_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ -#define TC1_EVACT1_bp 6 /* Event Action bit 1 position. */ -#define TC1_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ -#define TC1_EVACT2_bp 7 /* Event Action bit 2 position. */ - -#define TC1_EVDLY_bm 0x10 /* Event Delay bit mask. */ -#define TC1_EVDLY_bp 4 /* Event Delay bit position. */ - -#define TC1_EVSEL_gm 0x0F /* Event Source Select group mask. */ -#define TC1_EVSEL_gp 0 /* Event Source Select group position. */ -#define TC1_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ -#define TC1_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ -#define TC1_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ -#define TC1_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ -#define TC1_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ -#define TC1_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ -#define TC1_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ -#define TC1_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ - -/* TC1.CTRLE bit masks and bit positions */ -#define TC1_BYTEM_bm 0x01 /* Byte Mode bit mask. */ -#define TC1_BYTEM_bp 0 /* Byte Mode bit position. */ - -/* TC1.INTCTRLA bit masks and bit positions */ -#define TC1_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ -#define TC1_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ -#define TC1_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ -#define TC1_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ -#define TC1_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ -#define TC1_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ - -#define TC1_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ -#define TC1_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ -#define TC1_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ -#define TC1_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ -#define TC1_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ -#define TC1_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ - -/* TC1.INTCTRLB bit masks and bit positions */ -#define TC1_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ -#define TC1_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ -#define TC1_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ -#define TC1_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ -#define TC1_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ -#define TC1_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ - -#define TC1_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ -#define TC1_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ -#define TC1_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ -#define TC1_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ -#define TC1_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ -#define TC1_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ - -/* TC1.CTRLFCLR bit masks and bit positions */ -#define TC1_CMD_gm 0x0C /* Command group mask. */ -#define TC1_CMD_gp 2 /* Command group position. */ -#define TC1_CMD0_bm (1<<2) /* Command bit 0 mask. */ -#define TC1_CMD0_bp 2 /* Command bit 0 position. */ -#define TC1_CMD1_bm (1<<3) /* Command bit 1 mask. */ -#define TC1_CMD1_bp 3 /* Command bit 1 position. */ - -#define TC1_LUPD_bm 0x02 /* Lock Update bit mask. */ -#define TC1_LUPD_bp 1 /* Lock Update bit position. */ - -#define TC1_DIR_bm 0x01 /* Direction bit mask. */ -#define TC1_DIR_bp 0 /* Direction bit position. */ - -/* TC1.CTRLFSET bit masks and bit positions */ -/* TC1_CMD Predefined. */ -/* TC1_CMD Predefined. */ - -/* TC1_LUPD Predefined. */ -/* TC1_LUPD Predefined. */ - -/* TC1_DIR Predefined. */ -/* TC1_DIR Predefined. */ - -/* TC1.CTRLGCLR bit masks and bit positions */ -#define TC1_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ -#define TC1_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ - -#define TC1_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ -#define TC1_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ - -#define TC1_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ -#define TC1_PERBV_bp 0 /* Period Buffer Valid bit position. */ - -/* TC1.CTRLGSET bit masks and bit positions */ -/* TC1_CCBBV Predefined. */ -/* TC1_CCBBV Predefined. */ - -/* TC1_CCABV Predefined. */ -/* TC1_CCABV Predefined. */ - -/* TC1_PERBV Predefined. */ -/* TC1_PERBV Predefined. */ - -/* TC1.INTFLAGS bit masks and bit positions */ -#define TC1_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ -#define TC1_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ - -#define TC1_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ -#define TC1_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ - -#define TC1_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ -#define TC1_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ - -#define TC1_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ -#define TC1_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ - -/* TC2 - 16-bit Timer/Counter type 2 */ -/* TC2.CTRLA bit masks and bit positions */ -#define TC2_CLKSEL_gm 0x0F /* Clock Selection group mask. */ -#define TC2_CLKSEL_gp 0 /* Clock Selection group position. */ -#define TC2_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ -#define TC2_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ -#define TC2_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ -#define TC2_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ -#define TC2_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ -#define TC2_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ -#define TC2_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ -#define TC2_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ - -/* TC2.CTRLB bit masks and bit positions */ -#define TC2_HCMPDEN_bm 0x80 /* High Byte Compare D Enable bit mask. */ -#define TC2_HCMPDEN_bp 7 /* High Byte Compare D Enable bit position. */ - -#define TC2_HCMPCEN_bm 0x40 /* High Byte Compare C Enable bit mask. */ -#define TC2_HCMPCEN_bp 6 /* High Byte Compare C Enable bit position. */ - -#define TC2_HCMPBEN_bm 0x20 /* High Byte Compare B Enable bit mask. */ -#define TC2_HCMPBEN_bp 5 /* High Byte Compare B Enable bit position. */ - -#define TC2_HCMPAEN_bm 0x10 /* High Byte Compare A Enable bit mask. */ -#define TC2_HCMPAEN_bp 4 /* High Byte Compare A Enable bit position. */ - -#define TC2_LCMPDEN_bm 0x08 /* Low Byte Compare D Enable bit mask. */ -#define TC2_LCMPDEN_bp 3 /* Low Byte Compare D Enable bit position. */ - -#define TC2_LCMPCEN_bm 0x04 /* Low Byte Compare C Enable bit mask. */ -#define TC2_LCMPCEN_bp 2 /* Low Byte Compare C Enable bit position. */ - -#define TC2_LCMPBEN_bm 0x02 /* Low Byte Compare B Enable bit mask. */ -#define TC2_LCMPBEN_bp 1 /* Low Byte Compare B Enable bit position. */ - -#define TC2_LCMPAEN_bm 0x01 /* Low Byte Compare A Enable bit mask. */ -#define TC2_LCMPAEN_bp 0 /* Low Byte Compare A Enable bit position. */ - -/* TC2.CTRLC bit masks and bit positions */ -#define TC2_HCMPD_bm 0x80 /* High Byte Compare D Output Value bit mask. */ -#define TC2_HCMPD_bp 7 /* High Byte Compare D Output Value bit position. */ - -#define TC2_HCMPC_bm 0x40 /* High Byte Compare C Output Value bit mask. */ -#define TC2_HCMPC_bp 6 /* High Byte Compare C Output Value bit position. */ - -#define TC2_HCMPB_bm 0x20 /* High Byte Compare B Output Value bit mask. */ -#define TC2_HCMPB_bp 5 /* High Byte Compare B Output Value bit position. */ - -#define TC2_HCMPA_bm 0x10 /* High Byte Compare A Output Value bit mask. */ -#define TC2_HCMPA_bp 4 /* High Byte Compare A Output Value bit position. */ - -#define TC2_LCMPD_bm 0x08 /* Low Byte Compare D Output Value bit mask. */ -#define TC2_LCMPD_bp 3 /* Low Byte Compare D Output Value bit position. */ - -#define TC2_LCMPC_bm 0x04 /* Low Byte Compare C Output Value bit mask. */ -#define TC2_LCMPC_bp 2 /* Low Byte Compare C Output Value bit position. */ - -#define TC2_LCMPB_bm 0x02 /* Low Byte Compare B Output Value bit mask. */ -#define TC2_LCMPB_bp 1 /* Low Byte Compare B Output Value bit position. */ - -#define TC2_LCMPA_bm 0x01 /* Low Byte Compare A Output Value bit mask. */ -#define TC2_LCMPA_bp 0 /* Low Byte Compare A Output Value bit position. */ - -/* TC2.CTRLE bit masks and bit positions */ -#define TC2_BYTEM_gm 0x03 /* Byte Mode group mask. */ -#define TC2_BYTEM_gp 0 /* Byte Mode group position. */ -#define TC2_BYTEM0_bm (1<<0) /* Byte Mode bit 0 mask. */ -#define TC2_BYTEM0_bp 0 /* Byte Mode bit 0 position. */ -#define TC2_BYTEM1_bm (1<<1) /* Byte Mode bit 1 mask. */ -#define TC2_BYTEM1_bp 1 /* Byte Mode bit 1 position. */ - -/* TC2.INTCTRLA bit masks and bit positions */ -#define TC2_HUNFINTLVL_gm 0x0C /* High Byte Underflow Interrupt Level group mask. */ -#define TC2_HUNFINTLVL_gp 2 /* High Byte Underflow Interrupt Level group position. */ -#define TC2_HUNFINTLVL0_bm (1<<2) /* High Byte Underflow Interrupt Level bit 0 mask. */ -#define TC2_HUNFINTLVL0_bp 2 /* High Byte Underflow Interrupt Level bit 0 position. */ -#define TC2_HUNFINTLVL1_bm (1<<3) /* High Byte Underflow Interrupt Level bit 1 mask. */ -#define TC2_HUNFINTLVL1_bp 3 /* High Byte Underflow Interrupt Level bit 1 position. */ - -#define TC2_LUNFINTLVL_gm 0x03 /* Low Byte Underflow interrupt level group mask. */ -#define TC2_LUNFINTLVL_gp 0 /* Low Byte Underflow interrupt level group position. */ -#define TC2_LUNFINTLVL0_bm (1<<0) /* Low Byte Underflow interrupt level bit 0 mask. */ -#define TC2_LUNFINTLVL0_bp 0 /* Low Byte Underflow interrupt level bit 0 position. */ -#define TC2_LUNFINTLVL1_bm (1<<1) /* Low Byte Underflow interrupt level bit 1 mask. */ -#define TC2_LUNFINTLVL1_bp 1 /* Low Byte Underflow interrupt level bit 1 position. */ - -/* TC2.INTCTRLB bit masks and bit positions */ -#define TC2_LCMPDINTLVL_gm 0xC0 /* Low Byte Compare D Interrupt Level group mask. */ -#define TC2_LCMPDINTLVL_gp 6 /* Low Byte Compare D Interrupt Level group position. */ -#define TC2_LCMPDINTLVL0_bm (1<<6) /* Low Byte Compare D Interrupt Level bit 0 mask. */ -#define TC2_LCMPDINTLVL0_bp 6 /* Low Byte Compare D Interrupt Level bit 0 position. */ -#define TC2_LCMPDINTLVL1_bm (1<<7) /* Low Byte Compare D Interrupt Level bit 1 mask. */ -#define TC2_LCMPDINTLVL1_bp 7 /* Low Byte Compare D Interrupt Level bit 1 position. */ - -#define TC2_LCMPCINTLVL_gm 0x30 /* Low Byte Compare C Interrupt Level group mask. */ -#define TC2_LCMPCINTLVL_gp 4 /* Low Byte Compare C Interrupt Level group position. */ -#define TC2_LCMPCINTLVL0_bm (1<<4) /* Low Byte Compare C Interrupt Level bit 0 mask. */ -#define TC2_LCMPCINTLVL0_bp 4 /* Low Byte Compare C Interrupt Level bit 0 position. */ -#define TC2_LCMPCINTLVL1_bm (1<<5) /* Low Byte Compare C Interrupt Level bit 1 mask. */ -#define TC2_LCMPCINTLVL1_bp 5 /* Low Byte Compare C Interrupt Level bit 1 position. */ - -#define TC2_LCMPBINTLVL_gm 0x0C /* Low Byte Compare B Interrupt Level group mask. */ -#define TC2_LCMPBINTLVL_gp 2 /* Low Byte Compare B Interrupt Level group position. */ -#define TC2_LCMPBINTLVL0_bm (1<<2) /* Low Byte Compare B Interrupt Level bit 0 mask. */ -#define TC2_LCMPBINTLVL0_bp 2 /* Low Byte Compare B Interrupt Level bit 0 position. */ -#define TC2_LCMPBINTLVL1_bm (1<<3) /* Low Byte Compare B Interrupt Level bit 1 mask. */ -#define TC2_LCMPBINTLVL1_bp 3 /* Low Byte Compare B Interrupt Level bit 1 position. */ - -#define TC2_LCMPAINTLVL_gm 0x03 /* Low Byte Compare A Interrupt Level group mask. */ -#define TC2_LCMPAINTLVL_gp 0 /* Low Byte Compare A Interrupt Level group position. */ -#define TC2_LCMPAINTLVL0_bm (1<<0) /* Low Byte Compare A Interrupt Level bit 0 mask. */ -#define TC2_LCMPAINTLVL0_bp 0 /* Low Byte Compare A Interrupt Level bit 0 position. */ -#define TC2_LCMPAINTLVL1_bm (1<<1) /* Low Byte Compare A Interrupt Level bit 1 mask. */ -#define TC2_LCMPAINTLVL1_bp 1 /* Low Byte Compare A Interrupt Level bit 1 position. */ - -/* TC2.CTRLF bit masks and bit positions */ -#define TC2_CMD_gm 0x0C /* Command group mask. */ -#define TC2_CMD_gp 2 /* Command group position. */ -#define TC2_CMD0_bm (1<<2) /* Command bit 0 mask. */ -#define TC2_CMD0_bp 2 /* Command bit 0 position. */ -#define TC2_CMD1_bm (1<<3) /* Command bit 1 mask. */ -#define TC2_CMD1_bp 3 /* Command bit 1 position. */ - -#define TC2_CMDEN_gm 0x03 /* Command Enable group mask. */ -#define TC2_CMDEN_gp 0 /* Command Enable group position. */ -#define TC2_CMDEN0_bm (1<<0) /* Command Enable bit 0 mask. */ -#define TC2_CMDEN0_bp 0 /* Command Enable bit 0 position. */ -#define TC2_CMDEN1_bm (1<<1) /* Command Enable bit 1 mask. */ -#define TC2_CMDEN1_bp 1 /* Command Enable bit 1 position. */ - -/* TC2.INTFLAGS bit masks and bit positions */ -#define TC2_LCMPDIF_bm 0x80 /* Low Byte Compare D Interrupt Flag bit mask. */ -#define TC2_LCMPDIF_bp 7 /* Low Byte Compare D Interrupt Flag bit position. */ - -#define TC2_LCMPCIF_bm 0x40 /* Low Byte Compare C Interrupt Flag bit mask. */ -#define TC2_LCMPCIF_bp 6 /* Low Byte Compare C Interrupt Flag bit position. */ - -#define TC2_LCMPBIF_bm 0x20 /* Low Byte Compare B Interrupt Flag bit mask. */ -#define TC2_LCMPBIF_bp 5 /* Low Byte Compare B Interrupt Flag bit position. */ - -#define TC2_LCMPAIF_bm 0x10 /* Low Byte Compare A Interrupt Flag bit mask. */ -#define TC2_LCMPAIF_bp 4 /* Low Byte Compare A Interrupt Flag bit position. */ - -#define TC2_HUNFIF_bm 0x02 /* High Byte Underflow Interrupt Flag bit mask. */ -#define TC2_HUNFIF_bp 1 /* High Byte Underflow Interrupt Flag bit position. */ - -#define TC2_LUNFIF_bm 0x01 /* Low Byte Underflow Interrupt Flag bit mask. */ -#define TC2_LUNFIF_bp 0 /* Low Byte Underflow Interrupt Flag bit position. */ - -/* AWEX - Timer/Counter Advanced Waveform Extension */ -/* AWEX.CTRL bit masks and bit positions */ -#define AWEX_PGM_bm 0x20 /* Pattern Generation Mode bit mask. */ -#define AWEX_PGM_bp 5 /* Pattern Generation Mode bit position. */ - -#define AWEX_CWCM_bm 0x10 /* Common Waveform Channel Mode bit mask. */ -#define AWEX_CWCM_bp 4 /* Common Waveform Channel Mode bit position. */ - -#define AWEX_DTICCDEN_bm 0x08 /* Dead Time Insertion Compare Channel D Enable bit mask. */ -#define AWEX_DTICCDEN_bp 3 /* Dead Time Insertion Compare Channel D Enable bit position. */ - -#define AWEX_DTICCCEN_bm 0x04 /* Dead Time Insertion Compare Channel C Enable bit mask. */ -#define AWEX_DTICCCEN_bp 2 /* Dead Time Insertion Compare Channel C Enable bit position. */ - -#define AWEX_DTICCBEN_bm 0x02 /* Dead Time Insertion Compare Channel B Enable bit mask. */ -#define AWEX_DTICCBEN_bp 1 /* Dead Time Insertion Compare Channel B Enable bit position. */ - -#define AWEX_DTICCAEN_bm 0x01 /* Dead Time Insertion Compare Channel A Enable bit mask. */ -#define AWEX_DTICCAEN_bp 0 /* Dead Time Insertion Compare Channel A Enable bit position. */ - -/* AWEX.FDCTRL bit masks and bit positions */ -#define AWEX_FDDBD_bm 0x10 /* Fault Detect on Disable Break Disable bit mask. */ -#define AWEX_FDDBD_bp 4 /* Fault Detect on Disable Break Disable bit position. */ - -#define AWEX_FDMODE_bm 0x04 /* Fault Detect Mode bit mask. */ -#define AWEX_FDMODE_bp 2 /* Fault Detect Mode bit position. */ - -#define AWEX_FDACT_gm 0x03 /* Fault Detect Action group mask. */ -#define AWEX_FDACT_gp 0 /* Fault Detect Action group position. */ -#define AWEX_FDACT0_bm (1<<0) /* Fault Detect Action bit 0 mask. */ -#define AWEX_FDACT0_bp 0 /* Fault Detect Action bit 0 position. */ -#define AWEX_FDACT1_bm (1<<1) /* Fault Detect Action bit 1 mask. */ -#define AWEX_FDACT1_bp 1 /* Fault Detect Action bit 1 position. */ - -/* AWEX.STATUS bit masks and bit positions */ -#define AWEX_FDF_bm 0x04 /* Fault Detect Flag bit mask. */ -#define AWEX_FDF_bp 2 /* Fault Detect Flag bit position. */ - -#define AWEX_DTHSBUFV_bm 0x02 /* Dead Time High Side Buffer Valid bit mask. */ -#define AWEX_DTHSBUFV_bp 1 /* Dead Time High Side Buffer Valid bit position. */ - -#define AWEX_DTLSBUFV_bm 0x01 /* Dead Time Low Side Buffer Valid bit mask. */ -#define AWEX_DTLSBUFV_bp 0 /* Dead Time Low Side Buffer Valid bit position. */ - -/* AWEX.STATUSSET bit masks and bit positions */ -/* AWEX_FDF Predefined. */ -/* AWEX_FDF Predefined. */ - -/* AWEX_DTHSBUFV Predefined. */ -/* AWEX_DTHSBUFV Predefined. */ - -/* AWEX_DTLSBUFV Predefined. */ -/* AWEX_DTLSBUFV Predefined. */ - -/* HIRES - Timer/Counter High-Resolution Extension */ -/* HIRES.CTRLA bit masks and bit positions */ -#define HIRES_HREN_gm 0x03 /* High Resolution Enable group mask. */ -#define HIRES_HREN_gp 0 /* High Resolution Enable group position. */ -#define HIRES_HREN0_bm (1<<0) /* High Resolution Enable bit 0 mask. */ -#define HIRES_HREN0_bp 0 /* High Resolution Enable bit 0 position. */ -#define HIRES_HREN1_bm (1<<1) /* High Resolution Enable bit 1 mask. */ -#define HIRES_HREN1_bp 1 /* High Resolution Enable bit 1 position. */ - -/* USART - Universal Asynchronous Receiver-Transmitter */ -/* USART.STATUS bit masks and bit positions */ -#define USART_RXCIF_bm 0x80 /* Receive Interrupt Flag bit mask. */ -#define USART_RXCIF_bp 7 /* Receive Interrupt Flag bit position. */ - -#define USART_TXCIF_bm 0x40 /* Transmit Interrupt Flag bit mask. */ -#define USART_TXCIF_bp 6 /* Transmit Interrupt Flag bit position. */ - -#define USART_DREIF_bm 0x20 /* Data Register Empty Flag bit mask. */ -#define USART_DREIF_bp 5 /* Data Register Empty Flag bit position. */ - -#define USART_FERR_bm 0x10 /* Frame Error bit mask. */ -#define USART_FERR_bp 4 /* Frame Error bit position. */ - -#define USART_BUFOVF_bm 0x08 /* Buffer Overflow bit mask. */ -#define USART_BUFOVF_bp 3 /* Buffer Overflow bit position. */ - -#define USART_PERR_bm 0x04 /* Parity Error bit mask. */ -#define USART_PERR_bp 2 /* Parity Error bit position. */ - -#define USART_RXB8_bm 0x01 /* Receive Bit 8 bit mask. */ -#define USART_RXB8_bp 0 /* Receive Bit 8 bit position. */ - -/* USART.CTRLA bit masks and bit positions */ -#define USART_RXCINTLVL_gm 0x30 /* Receive Interrupt Level group mask. */ -#define USART_RXCINTLVL_gp 4 /* Receive Interrupt Level group position. */ -#define USART_RXCINTLVL0_bm (1<<4) /* Receive Interrupt Level bit 0 mask. */ -#define USART_RXCINTLVL0_bp 4 /* Receive Interrupt Level bit 0 position. */ -#define USART_RXCINTLVL1_bm (1<<5) /* Receive Interrupt Level bit 1 mask. */ -#define USART_RXCINTLVL1_bp 5 /* Receive Interrupt Level bit 1 position. */ - -#define USART_TXCINTLVL_gm 0x0C /* Transmit Interrupt Level group mask. */ -#define USART_TXCINTLVL_gp 2 /* Transmit Interrupt Level group position. */ -#define USART_TXCINTLVL0_bm (1<<2) /* Transmit Interrupt Level bit 0 mask. */ -#define USART_TXCINTLVL0_bp 2 /* Transmit Interrupt Level bit 0 position. */ -#define USART_TXCINTLVL1_bm (1<<3) /* Transmit Interrupt Level bit 1 mask. */ -#define USART_TXCINTLVL1_bp 3 /* Transmit Interrupt Level bit 1 position. */ - -#define USART_DREINTLVL_gm 0x03 /* Data Register Empty Interrupt Level group mask. */ -#define USART_DREINTLVL_gp 0 /* Data Register Empty Interrupt Level group position. */ -#define USART_DREINTLVL0_bm (1<<0) /* Data Register Empty Interrupt Level bit 0 mask. */ -#define USART_DREINTLVL0_bp 0 /* Data Register Empty Interrupt Level bit 0 position. */ -#define USART_DREINTLVL1_bm (1<<1) /* Data Register Empty Interrupt Level bit 1 mask. */ -#define USART_DREINTLVL1_bp 1 /* Data Register Empty Interrupt Level bit 1 position. */ - -/* USART.CTRLB bit masks and bit positions */ -#define USART_RXEN_bm 0x10 /* Receiver Enable bit mask. */ -#define USART_RXEN_bp 4 /* Receiver Enable bit position. */ - -#define USART_TXEN_bm 0x08 /* Transmitter Enable bit mask. */ -#define USART_TXEN_bp 3 /* Transmitter Enable bit position. */ - -#define USART_CLK2X_bm 0x04 /* Double transmission speed bit mask. */ -#define USART_CLK2X_bp 2 /* Double transmission speed bit position. */ - -#define USART_MPCM_bm 0x02 /* Multi-processor Communication Mode bit mask. */ -#define USART_MPCM_bp 1 /* Multi-processor Communication Mode bit position. */ - -#define USART_TXB8_bm 0x01 /* Transmit bit 8 bit mask. */ -#define USART_TXB8_bp 0 /* Transmit bit 8 bit position. */ - -/* USART.CTRLC bit masks and bit positions */ -#define USART_CMODE_gm 0xC0 /* Communication Mode group mask. */ -#define USART_CMODE_gp 6 /* Communication Mode group position. */ -#define USART_CMODE0_bm (1<<6) /* Communication Mode bit 0 mask. */ -#define USART_CMODE0_bp 6 /* Communication Mode bit 0 position. */ -#define USART_CMODE1_bm (1<<7) /* Communication Mode bit 1 mask. */ -#define USART_CMODE1_bp 7 /* Communication Mode bit 1 position. */ - -#define USART_PMODE_gm 0x30 /* Parity Mode group mask. */ -#define USART_PMODE_gp 4 /* Parity Mode group position. */ -#define USART_PMODE0_bm (1<<4) /* Parity Mode bit 0 mask. */ -#define USART_PMODE0_bp 4 /* Parity Mode bit 0 position. */ -#define USART_PMODE1_bm (1<<5) /* Parity Mode bit 1 mask. */ -#define USART_PMODE1_bp 5 /* Parity Mode bit 1 position. */ - -#define USART_SBMODE_bm 0x08 /* Stop Bit Mode bit mask. */ -#define USART_SBMODE_bp 3 /* Stop Bit Mode bit position. */ - -#define USART_CHSIZE_gm 0x07 /* Character Size group mask. */ -#define USART_CHSIZE_gp 0 /* Character Size group position. */ -#define USART_CHSIZE0_bm (1<<0) /* Character Size bit 0 mask. */ -#define USART_CHSIZE0_bp 0 /* Character Size bit 0 position. */ -#define USART_CHSIZE1_bm (1<<1) /* Character Size bit 1 mask. */ -#define USART_CHSIZE1_bp 1 /* Character Size bit 1 position. */ -#define USART_CHSIZE2_bm (1<<2) /* Character Size bit 2 mask. */ -#define USART_CHSIZE2_bp 2 /* Character Size bit 2 position. */ - -/* USART.BAUDCTRLA bit masks and bit positions */ -#define USART_BSEL_gm 0xFF /* Baud Rate Selection Bits [7:0] group mask. */ -#define USART_BSEL_gp 0 /* Baud Rate Selection Bits [7:0] group position. */ -#define USART_BSEL0_bm (1<<0) /* Baud Rate Selection Bits [7:0] bit 0 mask. */ -#define USART_BSEL0_bp 0 /* Baud Rate Selection Bits [7:0] bit 0 position. */ -#define USART_BSEL1_bm (1<<1) /* Baud Rate Selection Bits [7:0] bit 1 mask. */ -#define USART_BSEL1_bp 1 /* Baud Rate Selection Bits [7:0] bit 1 position. */ -#define USART_BSEL2_bm (1<<2) /* Baud Rate Selection Bits [7:0] bit 2 mask. */ -#define USART_BSEL2_bp 2 /* Baud Rate Selection Bits [7:0] bit 2 position. */ -#define USART_BSEL3_bm (1<<3) /* Baud Rate Selection Bits [7:0] bit 3 mask. */ -#define USART_BSEL3_bp 3 /* Baud Rate Selection Bits [7:0] bit 3 position. */ -#define USART_BSEL4_bm (1<<4) /* Baud Rate Selection Bits [7:0] bit 4 mask. */ -#define USART_BSEL4_bp 4 /* Baud Rate Selection Bits [7:0] bit 4 position. */ -#define USART_BSEL5_bm (1<<5) /* Baud Rate Selection Bits [7:0] bit 5 mask. */ -#define USART_BSEL5_bp 5 /* Baud Rate Selection Bits [7:0] bit 5 position. */ -#define USART_BSEL6_bm (1<<6) /* Baud Rate Selection Bits [7:0] bit 6 mask. */ -#define USART_BSEL6_bp 6 /* Baud Rate Selection Bits [7:0] bit 6 position. */ -#define USART_BSEL7_bm (1<<7) /* Baud Rate Selection Bits [7:0] bit 7 mask. */ -#define USART_BSEL7_bp 7 /* Baud Rate Selection Bits [7:0] bit 7 position. */ - -/* USART.BAUDCTRLB bit masks and bit positions */ -#define USART_BSCALE_gm 0xF0 /* Baud Rate Scale group mask. */ -#define USART_BSCALE_gp 4 /* Baud Rate Scale group position. */ -#define USART_BSCALE0_bm (1<<4) /* Baud Rate Scale bit 0 mask. */ -#define USART_BSCALE0_bp 4 /* Baud Rate Scale bit 0 position. */ -#define USART_BSCALE1_bm (1<<5) /* Baud Rate Scale bit 1 mask. */ -#define USART_BSCALE1_bp 5 /* Baud Rate Scale bit 1 position. */ -#define USART_BSCALE2_bm (1<<6) /* Baud Rate Scale bit 2 mask. */ -#define USART_BSCALE2_bp 6 /* Baud Rate Scale bit 2 position. */ -#define USART_BSCALE3_bm (1<<7) /* Baud Rate Scale bit 3 mask. */ -#define USART_BSCALE3_bp 7 /* Baud Rate Scale bit 3 position. */ - -/* USART_BSEL Predefined. */ -/* USART_BSEL Predefined. */ - -/* SPI - Serial Peripheral Interface */ -/* SPI.CTRL bit masks and bit positions */ -#define SPI_CLK2X_bm 0x80 /* Enable Double Speed bit mask. */ -#define SPI_CLK2X_bp 7 /* Enable Double Speed bit position. */ - -#define SPI_ENABLE_bm 0x40 /* Enable Module bit mask. */ -#define SPI_ENABLE_bp 6 /* Enable Module bit position. */ - -#define SPI_DORD_bm 0x20 /* Data Order Setting bit mask. */ -#define SPI_DORD_bp 5 /* Data Order Setting bit position. */ - -#define SPI_MASTER_bm 0x10 /* Master Operation Enable bit mask. */ -#define SPI_MASTER_bp 4 /* Master Operation Enable bit position. */ - -#define SPI_MODE_gm 0x0C /* SPI Mode group mask. */ -#define SPI_MODE_gp 2 /* SPI Mode group position. */ -#define SPI_MODE0_bm (1<<2) /* SPI Mode bit 0 mask. */ -#define SPI_MODE0_bp 2 /* SPI Mode bit 0 position. */ -#define SPI_MODE1_bm (1<<3) /* SPI Mode bit 1 mask. */ -#define SPI_MODE1_bp 3 /* SPI Mode bit 1 position. */ - -#define SPI_PRESCALER_gm 0x03 /* Prescaler group mask. */ -#define SPI_PRESCALER_gp 0 /* Prescaler group position. */ -#define SPI_PRESCALER0_bm (1<<0) /* Prescaler bit 0 mask. */ -#define SPI_PRESCALER0_bp 0 /* Prescaler bit 0 position. */ -#define SPI_PRESCALER1_bm (1<<1) /* Prescaler bit 1 mask. */ -#define SPI_PRESCALER1_bp 1 /* Prescaler bit 1 position. */ - -/* SPI.INTCTRL bit masks and bit positions */ -#define SPI_INTLVL_gm 0x03 /* Interrupt level group mask. */ -#define SPI_INTLVL_gp 0 /* Interrupt level group position. */ -#define SPI_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */ -#define SPI_INTLVL0_bp 0 /* Interrupt level bit 0 position. */ -#define SPI_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */ -#define SPI_INTLVL1_bp 1 /* Interrupt level bit 1 position. */ - -/* SPI.STATUS bit masks and bit positions */ -#define SPI_IF_bm 0x80 /* Interrupt Flag bit mask. */ -#define SPI_IF_bp 7 /* Interrupt Flag bit position. */ - -#define SPI_WRCOL_bm 0x40 /* Write Collision bit mask. */ -#define SPI_WRCOL_bp 6 /* Write Collision bit position. */ - -/* IRCOM - IR Communication Module */ -/* IRCOM.CTRL bit masks and bit positions */ -#define IRCOM_EVSEL_gm 0x0F /* Event Channel Select group mask. */ -#define IRCOM_EVSEL_gp 0 /* Event Channel Select group position. */ -#define IRCOM_EVSEL0_bm (1<<0) /* Event Channel Select bit 0 mask. */ -#define IRCOM_EVSEL0_bp 0 /* Event Channel Select bit 0 position. */ -#define IRCOM_EVSEL1_bm (1<<1) /* Event Channel Select bit 1 mask. */ -#define IRCOM_EVSEL1_bp 1 /* Event Channel Select bit 1 position. */ -#define IRCOM_EVSEL2_bm (1<<2) /* Event Channel Select bit 2 mask. */ -#define IRCOM_EVSEL2_bp 2 /* Event Channel Select bit 2 position. */ -#define IRCOM_EVSEL3_bm (1<<3) /* Event Channel Select bit 3 mask. */ -#define IRCOM_EVSEL3_bp 3 /* Event Channel Select bit 3 position. */ - -/* FUSE - Fuses and Lockbits */ -/* NVM_FUSES.FUSEBYTE1 bit masks and bit positions */ -#define NVM_FUSES_WDWP_gm 0xF0 /* Watchdog Window Timeout Period group mask. */ -#define NVM_FUSES_WDWP_gp 4 /* Watchdog Window Timeout Period group position. */ -#define NVM_FUSES_WDWP0_bm (1<<4) /* Watchdog Window Timeout Period bit 0 mask. */ -#define NVM_FUSES_WDWP0_bp 4 /* Watchdog Window Timeout Period bit 0 position. */ -#define NVM_FUSES_WDWP1_bm (1<<5) /* Watchdog Window Timeout Period bit 1 mask. */ -#define NVM_FUSES_WDWP1_bp 5 /* Watchdog Window Timeout Period bit 1 position. */ -#define NVM_FUSES_WDWP2_bm (1<<6) /* Watchdog Window Timeout Period bit 2 mask. */ -#define NVM_FUSES_WDWP2_bp 6 /* Watchdog Window Timeout Period bit 2 position. */ -#define NVM_FUSES_WDWP3_bm (1<<7) /* Watchdog Window Timeout Period bit 3 mask. */ -#define NVM_FUSES_WDWP3_bp 7 /* Watchdog Window Timeout Period bit 3 position. */ - -#define NVM_FUSES_WDP_gm 0x0F /* Watchdog Timeout Period group mask. */ -#define NVM_FUSES_WDP_gp 0 /* Watchdog Timeout Period group position. */ -#define NVM_FUSES_WDP0_bm (1<<0) /* Watchdog Timeout Period bit 0 mask. */ -#define NVM_FUSES_WDP0_bp 0 /* Watchdog Timeout Period bit 0 position. */ -#define NVM_FUSES_WDP1_bm (1<<1) /* Watchdog Timeout Period bit 1 mask. */ -#define NVM_FUSES_WDP1_bp 1 /* Watchdog Timeout Period bit 1 position. */ -#define NVM_FUSES_WDP2_bm (1<<2) /* Watchdog Timeout Period bit 2 mask. */ -#define NVM_FUSES_WDP2_bp 2 /* Watchdog Timeout Period bit 2 position. */ -#define NVM_FUSES_WDP3_bm (1<<3) /* Watchdog Timeout Period bit 3 mask. */ -#define NVM_FUSES_WDP3_bp 3 /* Watchdog Timeout Period bit 3 position. */ - -/* NVM_FUSES.FUSEBYTE2 bit masks and bit positions */ -#define NVM_FUSES_BOOTRST_bm 0x40 /* Boot Loader Section Reset Vector bit mask. */ -#define NVM_FUSES_BOOTRST_bp 6 /* Boot Loader Section Reset Vector bit position. */ - -#define NVM_FUSES_TOSCSEL_bm 0x20 /* Timer Oscillator pin location bit mask. */ -#define NVM_FUSES_TOSCSEL_bp 5 /* Timer Oscillator pin location bit position. */ - -#define NVM_FUSES_BODPD_gm 0x03 /* BOD Operation in Power-Down Mode group mask. */ -#define NVM_FUSES_BODPD_gp 0 /* BOD Operation in Power-Down Mode group position. */ -#define NVM_FUSES_BODPD0_bm (1<<0) /* BOD Operation in Power-Down Mode bit 0 mask. */ -#define NVM_FUSES_BODPD0_bp 0 /* BOD Operation in Power-Down Mode bit 0 position. */ -#define NVM_FUSES_BODPD1_bm (1<<1) /* BOD Operation in Power-Down Mode bit 1 mask. */ -#define NVM_FUSES_BODPD1_bp 1 /* BOD Operation in Power-Down Mode bit 1 position. */ - -/* NVM_FUSES.FUSEBYTE4 bit masks and bit positions */ -#define NVM_FUSES_RSTDISBL_bm 0x10 /* External Reset Disable bit mask. */ -#define NVM_FUSES_RSTDISBL_bp 4 /* External Reset Disable bit position. */ - -#define NVM_FUSES_SUT_gm 0x0C /* Start-up Time group mask. */ -#define NVM_FUSES_SUT_gp 2 /* Start-up Time group position. */ -#define NVM_FUSES_SUT0_bm (1<<2) /* Start-up Time bit 0 mask. */ -#define NVM_FUSES_SUT0_bp 2 /* Start-up Time bit 0 position. */ -#define NVM_FUSES_SUT1_bm (1<<3) /* Start-up Time bit 1 mask. */ -#define NVM_FUSES_SUT1_bp 3 /* Start-up Time bit 1 position. */ - -#define NVM_FUSES_WDLOCK_bm 0x02 /* Watchdog Timer Lock bit mask. */ -#define NVM_FUSES_WDLOCK_bp 1 /* Watchdog Timer Lock bit position. */ - -/* NVM_FUSES.FUSEBYTE5 bit masks and bit positions */ -#define NVM_FUSES_BODACT_gm 0x30 /* BOD Operation in Active Mode group mask. */ -#define NVM_FUSES_BODACT_gp 4 /* BOD Operation in Active Mode group position. */ -#define NVM_FUSES_BODACT0_bm (1<<4) /* BOD Operation in Active Mode bit 0 mask. */ -#define NVM_FUSES_BODACT0_bp 4 /* BOD Operation in Active Mode bit 0 position. */ -#define NVM_FUSES_BODACT1_bm (1<<5) /* BOD Operation in Active Mode bit 1 mask. */ -#define NVM_FUSES_BODACT1_bp 5 /* BOD Operation in Active Mode bit 1 position. */ - -#define NVM_FUSES_EESAVE_bm 0x08 /* Preserve EEPROM Through Chip Erase bit mask. */ -#define NVM_FUSES_EESAVE_bp 3 /* Preserve EEPROM Through Chip Erase bit position. */ - -#define NVM_FUSES_BODLVL_gm 0x07 /* Brownout Detection Voltage Level group mask. */ -#define NVM_FUSES_BODLVL_gp 0 /* Brownout Detection Voltage Level group position. */ -#define NVM_FUSES_BODLVL0_bm (1<<0) /* Brownout Detection Voltage Level bit 0 mask. */ -#define NVM_FUSES_BODLVL0_bp 0 /* Brownout Detection Voltage Level bit 0 position. */ -#define NVM_FUSES_BODLVL1_bm (1<<1) /* Brownout Detection Voltage Level bit 1 mask. */ -#define NVM_FUSES_BODLVL1_bp 1 /* Brownout Detection Voltage Level bit 1 position. */ -#define NVM_FUSES_BODLVL2_bm (1<<2) /* Brownout Detection Voltage Level bit 2 mask. */ -#define NVM_FUSES_BODLVL2_bp 2 /* Brownout Detection Voltage Level bit 2 position. */ - -/* LOCKBIT - Fuses and Lockbits */ -/* NVM_LOCKBITS.LOCKBITS bit masks and bit positions */ -#define NVM_LOCKBITS_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ -#define NVM_LOCKBITS_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ -#define NVM_LOCKBITS_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ -#define NVM_LOCKBITS_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ -#define NVM_LOCKBITS_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ -#define NVM_LOCKBITS_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ - -#define NVM_LOCKBITS_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ -#define NVM_LOCKBITS_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ -#define NVM_LOCKBITS_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ -#define NVM_LOCKBITS_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ -#define NVM_LOCKBITS_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ -#define NVM_LOCKBITS_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ - -#define NVM_LOCKBITS_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ -#define NVM_LOCKBITS_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ -#define NVM_LOCKBITS_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ -#define NVM_LOCKBITS_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ -#define NVM_LOCKBITS_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ -#define NVM_LOCKBITS_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ - -#define NVM_LOCKBITS_LB_gm 0x03 /* Lock Bits group mask. */ -#define NVM_LOCKBITS_LB_gp 0 /* Lock Bits group position. */ -#define NVM_LOCKBITS_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ -#define NVM_LOCKBITS_LB0_bp 0 /* Lock Bits bit 0 position. */ -#define NVM_LOCKBITS_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ -#define NVM_LOCKBITS_LB1_bp 1 /* Lock Bits bit 1 position. */ - - - -// Generic Port Pins - -#define PIN0_bm 0x01 -#define PIN0_bp 0 -#define PIN1_bm 0x02 -#define PIN1_bp 1 -#define PIN2_bm 0x04 -#define PIN2_bp 2 -#define PIN3_bm 0x08 -#define PIN3_bp 3 -#define PIN4_bm 0x10 -#define PIN4_bp 4 -#define PIN5_bm 0x20 -#define PIN5_bp 5 -#define PIN6_bm 0x40 -#define PIN6_bp 6 -#define PIN7_bm 0x80 -#define PIN7_bp 7 - -/* ========== Interrupt Vector Definitions ========== */ -/* Vector 0 is the reset vector */ - -/* OSC interrupt vectors */ -#define OSC_OSCF_vect_num 1 -#define OSC_OSCF_vect _VECTOR(1) /* Oscillator Failure Interrupt (NMI) */ - -/* PORTC interrupt vectors */ -#define PORTC_INT0_vect_num 2 -#define PORTC_INT0_vect _VECTOR(2) /* External Interrupt 0 */ -#define PORTC_INT1_vect_num 3 -#define PORTC_INT1_vect _VECTOR(3) /* External Interrupt 1 */ - -/* PORTR interrupt vectors */ -#define PORTR_INT0_vect_num 4 -#define PORTR_INT0_vect _VECTOR(4) /* External Interrupt 0 */ -#define PORTR_INT1_vect_num 5 -#define PORTR_INT1_vect _VECTOR(5) /* External Interrupt 1 */ - -/* RTC interrupt vectors */ -#define RTC_OVF_vect_num 10 -#define RTC_OVF_vect _VECTOR(10) /* Overflow Interrupt */ -#define RTC_COMP_vect_num 11 -#define RTC_COMP_vect _VECTOR(11) /* Compare Interrupt */ - -/* TWIC interrupt vectors */ -#define TWIC_TWIS_vect_num 12 -#define TWIC_TWIS_vect _VECTOR(12) /* TWI Slave Interrupt */ -#define TWIC_TWIM_vect_num 13 -#define TWIC_TWIM_vect _VECTOR(13) /* TWI Master Interrupt */ - -/* TCC0 interrupt vectors */ -#define TCC0_OVF_vect_num 14 -#define TCC0_OVF_vect _VECTOR(14) /* Overflow Interrupt */ - -/* TCC2 interrupt vectors */ -#define TCC2_LUNF_vect_num 14 -#define TCC2_LUNF_vect _VECTOR(14) /* Low Byte Underflow Interrupt */ - -/* TCC0 interrupt vectors */ -#define TCC0_ERR_vect_num 15 -#define TCC0_ERR_vect _VECTOR(15) /* Error Interrupt */ - -/* TCC2 interrupt vectors */ -#define TCC2_HUNF_vect_num 15 -#define TCC2_HUNF_vect _VECTOR(15) /* High Byte Underflow Interrupt */ - -/* TCC0 interrupt vectors */ -#define TCC0_CCA_vect_num 16 -#define TCC0_CCA_vect _VECTOR(16) /* Compare or Capture A Interrupt */ - -/* TCC2 interrupt vectors */ -#define TCC2_LCMPA_vect_num 16 -#define TCC2_LCMPA_vect _VECTOR(16) /* Low Byte Compare A Interrupt */ - -/* TCC0 interrupt vectors */ -#define TCC0_CCB_vect_num 17 -#define TCC0_CCB_vect _VECTOR(17) /* Compare or Capture B Interrupt */ - -/* TCC2 interrupt vectors */ -#define TCC2_LCMPB_vect_num 17 -#define TCC2_LCMPB_vect _VECTOR(17) /* Low Byte Compare B Interrupt */ - -/* TCC0 interrupt vectors */ -#define TCC0_CCC_vect_num 18 -#define TCC0_CCC_vect _VECTOR(18) /* Compare or Capture C Interrupt */ - -/* TCC2 interrupt vectors */ -#define TCC2_LCMPC_vect_num 18 -#define TCC2_LCMPC_vect _VECTOR(18) /* Low Byte Compare C Interrupt */ - -/* TCC0 interrupt vectors */ -#define TCC0_CCD_vect_num 19 -#define TCC0_CCD_vect _VECTOR(19) /* Compare or Capture D Interrupt */ - -/* TCC2 interrupt vectors */ -#define TCC2_LCMPD_vect_num 19 -#define TCC2_LCMPD_vect _VECTOR(19) /* Low Byte Compare D Interrupt */ - -/* TCC1 interrupt vectors */ -#define TCC1_OVF_vect_num 20 -#define TCC1_OVF_vect _VECTOR(20) /* Overflow Interrupt */ -#define TCC1_ERR_vect_num 21 -#define TCC1_ERR_vect _VECTOR(21) /* Error Interrupt */ -#define TCC1_CCA_vect_num 22 -#define TCC1_CCA_vect _VECTOR(22) /* Compare or Capture A Interrupt */ -#define TCC1_CCB_vect_num 23 -#define TCC1_CCB_vect _VECTOR(23) /* Compare or Capture B Interrupt */ - -/* SPIC interrupt vectors */ -#define SPIC_INT_vect_num 24 -#define SPIC_INT_vect _VECTOR(24) /* SPI Interrupt */ - -/* USARTC0 interrupt vectors */ -#define USARTC0_RXC_vect_num 25 -#define USARTC0_RXC_vect _VECTOR(25) /* Reception Complete Interrupt */ -#define USARTC0_DRE_vect_num 26 -#define USARTC0_DRE_vect _VECTOR(26) /* Data Register Empty Interrupt */ -#define USARTC0_TXC_vect_num 27 -#define USARTC0_TXC_vect _VECTOR(27) /* Transmission Complete Interrupt */ - -/* NVM interrupt vectors */ -#define NVM_EE_vect_num 32 -#define NVM_EE_vect _VECTOR(32) /* EE Interrupt */ -#define NVM_SPM_vect_num 33 -#define NVM_SPM_vect _VECTOR(33) /* SPM Interrupt */ - -/* PORTB interrupt vectors */ -#define PORTB_INT0_vect_num 34 -#define PORTB_INT0_vect _VECTOR(34) /* External Interrupt 0 */ -#define PORTB_INT1_vect_num 35 -#define PORTB_INT1_vect _VECTOR(35) /* External Interrupt 1 */ - -/* PORTE interrupt vectors */ -#define PORTE_INT0_vect_num 43 -#define PORTE_INT0_vect _VECTOR(43) /* External Interrupt 0 */ -#define PORTE_INT1_vect_num 44 -#define PORTE_INT1_vect _VECTOR(44) /* External Interrupt 1 */ - -/* TWIE interrupt vectors */ -#define TWIE_TWIS_vect_num 45 -#define TWIE_TWIS_vect _VECTOR(45) /* TWI Slave Interrupt */ -#define TWIE_TWIM_vect_num 46 -#define TWIE_TWIM_vect _VECTOR(46) /* TWI Master Interrupt */ - -/* TCE0 interrupt vectors */ -#define TCE0_OVF_vect_num 47 -#define TCE0_OVF_vect _VECTOR(47) /* Overflow Interrupt */ - -/* TCE2 interrupt vectors */ -#define TCE2_LUNF_vect_num 47 -#define TCE2_LUNF_vect _VECTOR(47) /* Low Byte Underflow Interrupt */ - -/* TCE0 interrupt vectors */ -#define TCE0_ERR_vect_num 48 -#define TCE0_ERR_vect _VECTOR(48) /* Error Interrupt */ - -/* TCE2 interrupt vectors */ -#define TCE2_HUNF_vect_num 48 -#define TCE2_HUNF_vect _VECTOR(48) /* High Byte Underflow Interrupt */ - -/* TCE0 interrupt vectors */ -#define TCE0_CCA_vect_num 49 -#define TCE0_CCA_vect _VECTOR(49) /* Compare or Capture A Interrupt */ - -/* TCE2 interrupt vectors */ -#define TCE2_LCMPA_vect_num 49 -#define TCE2_LCMPA_vect _VECTOR(49) /* Low Byte Compare A Interrupt */ - -/* TCE0 interrupt vectors */ -#define TCE0_CCB_vect_num 50 -#define TCE0_CCB_vect _VECTOR(50) /* Compare or Capture B Interrupt */ - -/* TCE2 interrupt vectors */ -#define TCE2_LCMPB_vect_num 50 -#define TCE2_LCMPB_vect _VECTOR(50) /* Low Byte Compare B Interrupt */ - -/* TCE0 interrupt vectors */ -#define TCE0_CCC_vect_num 51 -#define TCE0_CCC_vect _VECTOR(51) /* Compare or Capture C Interrupt */ - -/* TCE2 interrupt vectors */ -#define TCE2_LCMPC_vect_num 51 -#define TCE2_LCMPC_vect _VECTOR(51) /* Low Byte Compare C Interrupt */ - -/* TCE0 interrupt vectors */ -#define TCE0_CCD_vect_num 52 -#define TCE0_CCD_vect _VECTOR(52) /* Compare or Capture D Interrupt */ - -/* TCE2 interrupt vectors */ -#define TCE2_LCMPD_vect_num 52 -#define TCE2_LCMPD_vect _VECTOR(52) /* Low Byte Compare D Interrupt */ - -/* USARTE0 interrupt vectors */ -#define USARTE0_RXC_vect_num 58 -#define USARTE0_RXC_vect _VECTOR(58) /* Reception Complete Interrupt */ -#define USARTE0_DRE_vect_num 59 -#define USARTE0_DRE_vect _VECTOR(59) /* Data Register Empty Interrupt */ -#define USARTE0_TXC_vect_num 60 -#define USARTE0_TXC_vect _VECTOR(60) /* Transmission Complete Interrupt */ - -/* PORTD interrupt vectors */ -#define PORTD_INT0_vect_num 64 -#define PORTD_INT0_vect _VECTOR(64) /* External Interrupt 0 */ -#define PORTD_INT1_vect_num 65 -#define PORTD_INT1_vect _VECTOR(65) /* External Interrupt 1 */ - -/* PORTA interrupt vectors */ -#define PORTA_INT0_vect_num 66 -#define PORTA_INT0_vect _VECTOR(66) /* External Interrupt 0 */ -#define PORTA_INT1_vect_num 67 -#define PORTA_INT1_vect _VECTOR(67) /* External Interrupt 1 */ - -/* ACA interrupt vectors */ -#define ACA_AC0_vect_num 68 -#define ACA_AC0_vect _VECTOR(68) /* AC0 Interrupt */ -#define ACA_AC1_vect_num 69 -#define ACA_AC1_vect _VECTOR(69) /* AC1 Interrupt */ -#define ACA_ACW_vect_num 70 -#define ACA_ACW_vect _VECTOR(70) /* ACW Window Mode Interrupt */ - -/* ADCA interrupt vectors */ -#define ADCA_CH0_vect_num 71 -#define ADCA_CH0_vect _VECTOR(71) /* Interrupt 0 */ - -/* TCD0 interrupt vectors */ -#define TCD0_OVF_vect_num 77 -#define TCD0_OVF_vect _VECTOR(77) /* Overflow Interrupt */ - -/* TCD2 interrupt vectors */ -#define TCD2_LUNF_vect_num 77 -#define TCD2_LUNF_vect _VECTOR(77) /* Low Byte Underflow Interrupt */ - -/* TCD0 interrupt vectors */ -#define TCD0_ERR_vect_num 78 -#define TCD0_ERR_vect _VECTOR(78) /* Error Interrupt */ - -/* TCD2 interrupt vectors */ -#define TCD2_HUNF_vect_num 78 -#define TCD2_HUNF_vect _VECTOR(78) /* High Byte Underflow Interrupt */ - -/* TCD0 interrupt vectors */ -#define TCD0_CCA_vect_num 79 -#define TCD0_CCA_vect _VECTOR(79) /* Compare or Capture A Interrupt */ - -/* TCD2 interrupt vectors */ -#define TCD2_LCMPA_vect_num 79 -#define TCD2_LCMPA_vect _VECTOR(79) /* Low Byte Compare A Interrupt */ - -/* TCD0 interrupt vectors */ -#define TCD0_CCB_vect_num 80 -#define TCD0_CCB_vect _VECTOR(80) /* Compare or Capture B Interrupt */ - -/* TCD2 interrupt vectors */ -#define TCD2_LCMPB_vect_num 80 -#define TCD2_LCMPB_vect _VECTOR(80) /* Low Byte Compare B Interrupt */ - -/* TCD0 interrupt vectors */ -#define TCD0_CCC_vect_num 81 -#define TCD0_CCC_vect _VECTOR(81) /* Compare or Capture C Interrupt */ - -/* TCD2 interrupt vectors */ -#define TCD2_LCMPC_vect_num 81 -#define TCD2_LCMPC_vect _VECTOR(81) /* Low Byte Compare C Interrupt */ - -/* TCD0 interrupt vectors */ -#define TCD0_CCD_vect_num 82 -#define TCD0_CCD_vect _VECTOR(82) /* Compare or Capture D Interrupt */ - -/* TCD2 interrupt vectors */ -#define TCD2_LCMPD_vect_num 82 -#define TCD2_LCMPD_vect _VECTOR(82) /* Low Byte Compare D Interrupt */ - -/* SPID interrupt vectors */ -#define SPID_INT_vect_num 87 -#define SPID_INT_vect _VECTOR(87) /* SPI Interrupt */ - -/* USARTD0 interrupt vectors */ -#define USARTD0_RXC_vect_num 88 -#define USARTD0_RXC_vect _VECTOR(88) /* Reception Complete Interrupt */ -#define USARTD0_DRE_vect_num 89 -#define USARTD0_DRE_vect _VECTOR(89) /* Data Register Empty Interrupt */ -#define USARTD0_TXC_vect_num 90 -#define USARTD0_TXC_vect _VECTOR(90) /* Transmission Complete Interrupt */ - -/* PORTF interrupt vectors */ -#define PORTF_INT0_vect_num 104 -#define PORTF_INT0_vect _VECTOR(104) /* External Interrupt 0 */ -#define PORTF_INT1_vect_num 105 -#define PORTF_INT1_vect _VECTOR(105) /* External Interrupt 1 */ - -/* TCF0 interrupt vectors */ -#define TCF0_OVF_vect_num 108 -#define TCF0_OVF_vect _VECTOR(108) /* Overflow Interrupt */ - -/* TCF2 interrupt vectors */ -#define TCF2_LUNF_vect_num 108 -#define TCF2_LUNF_vect _VECTOR(108) /* Low Byte Underflow Interrupt */ - -/* TCF0 interrupt vectors */ -#define TCF0_ERR_vect_num 109 -#define TCF0_ERR_vect _VECTOR(109) /* Error Interrupt */ - -/* TCF2 interrupt vectors */ -#define TCF2_HUNF_vect_num 109 -#define TCF2_HUNF_vect _VECTOR(109) /* High Byte Underflow Interrupt */ - -/* TCF0 interrupt vectors */ -#define TCF0_CCA_vect_num 110 -#define TCF0_CCA_vect _VECTOR(110) /* Compare or Capture A Interrupt */ - -/* TCF2 interrupt vectors */ -#define TCF2_LCMPA_vect_num 110 -#define TCF2_LCMPA_vect _VECTOR(110) /* Low Byte Compare A Interrupt */ - -/* TCF0 interrupt vectors */ -#define TCF0_CCB_vect_num 111 -#define TCF0_CCB_vect _VECTOR(111) /* Compare or Capture B Interrupt */ - -/* TCF2 interrupt vectors */ -#define TCF2_LCMPB_vect_num 111 -#define TCF2_LCMPB_vect _VECTOR(111) /* Low Byte Compare B Interrupt */ - -/* TCF0 interrupt vectors */ -#define TCF0_CCC_vect_num 112 -#define TCF0_CCC_vect _VECTOR(112) /* Compare or Capture C Interrupt */ - -/* TCF2 interrupt vectors */ -#define TCF2_LCMPC_vect_num 112 -#define TCF2_LCMPC_vect _VECTOR(112) /* Low Byte Compare C Interrupt */ - -/* TCF0 interrupt vectors */ -#define TCF0_CCD_vect_num 113 -#define TCF0_CCD_vect _VECTOR(113) /* Compare or Capture D Interrupt */ - -/* TCF2 interrupt vectors */ -#define TCF2_LCMPD_vect_num 113 -#define TCF2_LCMPD_vect _VECTOR(113) /* Low Byte Compare D Interrupt */ - -/* USB interrupt vectors */ -#define USB_BUSEVENT_vect_num 125 -#define USB_BUSEVENT_vect _VECTOR(125) /* SOF, suspend, resume, reset bus event interrupts, crc, underflow, overflow and stall error interrupts */ -#define USB_TRNCOMPL_vect_num 126 -#define USB_TRNCOMPL_vect _VECTOR(126) /* Transaction complete interrupt */ - -#define _VECTOR_SIZE 4 /* Size of individual vector. */ -#define _VECTORS_SIZE (127 * _VECTOR_SIZE) - - -/* ========== Constants ========== */ - -#define PROGMEM_START (0x0000) -#define PROGMEM_SIZE (270336) -#define PROGMEM_END (PROGMEM_START + PROGMEM_SIZE - 1) - -#define APP_SECTION_START (0x0000) -#define APP_SECTION_SIZE (262144) -#define APP_SECTION_PAGE_SIZE (512) -#define APP_SECTION_END (APP_SECTION_START + APP_SECTION_SIZE - 1) - -#define APPTABLE_SECTION_START (0x3E000) -#define APPTABLE_SECTION_SIZE (8192) -#define APPTABLE_SECTION_PAGE_SIZE (512) -#define APPTABLE_SECTION_END (APPTABLE_SECTION_START + APPTABLE_SECTION_SIZE - 1) - -#define BOOT_SECTION_START (0x40000) -#define BOOT_SECTION_SIZE (8192) -#define BOOT_SECTION_PAGE_SIZE (512) -#define BOOT_SECTION_END (BOOT_SECTION_START + BOOT_SECTION_SIZE - 1) - -#define DATAMEM_START (0x0000) -#define DATAMEM_SIZE (24576) -#define DATAMEM_END (DATAMEM_START + DATAMEM_SIZE - 1) - -#define IO_START (0x0000) -#define IO_SIZE (4096) -#define IO_PAGE_SIZE (0) -#define IO_END (IO_START + IO_SIZE - 1) - -#define MAPPED_EEPROM_START (0x1000) -#define MAPPED_EEPROM_SIZE (4096) -#define MAPPED_EEPROM_PAGE_SIZE (0) -#define MAPPED_EEPROM_END (MAPPED_EEPROM_START + MAPPED_EEPROM_SIZE - 1) - -#define INTERNAL_SRAM_START (0x2000) -#define INTERNAL_SRAM_SIZE (16384) -#define INTERNAL_SRAM_PAGE_SIZE (0) -#define INTERNAL_SRAM_END (INTERNAL_SRAM_START + INTERNAL_SRAM_SIZE - 1) - -#define EEPROM_START (0x0000) -#define EEPROM_SIZE (4096) -#define EEPROM_PAGE_SIZE (32) -#define EEPROM_END (EEPROM_START + EEPROM_SIZE - 1) - -#define SIGNATURES_START (0x0000) -#define SIGNATURES_SIZE (3) -#define SIGNATURES_PAGE_SIZE (0) -#define SIGNATURES_END (SIGNATURES_START + SIGNATURES_SIZE - 1) - -#define FUSES_START (0x0000) -#define FUSES_SIZE (6) -#define FUSES_PAGE_SIZE (0) -#define FUSES_END (FUSES_START + FUSES_SIZE - 1) - -#define LOCKBITS_START (0x0000) -#define LOCKBITS_SIZE (1) -#define LOCKBITS_PAGE_SIZE (0) -#define LOCKBITS_END (LOCKBITS_START + LOCKBITS_SIZE - 1) - -#define USER_SIGNATURES_START (0x0000) -#define USER_SIGNATURES_SIZE (512) -#define USER_SIGNATURES_PAGE_SIZE (512) -#define USER_SIGNATURES_END (USER_SIGNATURES_START + USER_SIGNATURES_SIZE - 1) - -#define PROD_SIGNATURES_START (0x0000) -#define PROD_SIGNATURES_SIZE (64) -#define PROD_SIGNATURES_PAGE_SIZE (512) -#define PROD_SIGNATURES_END (PROD_SIGNATURES_START + PROD_SIGNATURES_SIZE - 1) - -#define FLASHSTART PROGMEM_START -#define FLASHEND PROGMEM_END -#define SPM_PAGESIZE 512 -#define RAMSTART INTERNAL_SRAM_START -#define RAMSIZE INTERNAL_SRAM_SIZE -#define RAMEND INTERNAL_SRAM_END -#define E2END EEPROM_END -#define E2PAGESIZE EEPROM_PAGE_SIZE - - -/* ========== Fuses ========== */ -#define FUSE_MEMORY_SIZE 6 - -/* Fuse Byte 0 Reserved */ - -/* Fuse Byte 1 */ -#define FUSE_WDP0 (unsigned char)~_BV(0) /* Watchdog Timeout Period Bit 0 */ -#define FUSE_WDP1 (unsigned char)~_BV(1) /* Watchdog Timeout Period Bit 1 */ -#define FUSE_WDP2 (unsigned char)~_BV(2) /* Watchdog Timeout Period Bit 2 */ -#define FUSE_WDP3 (unsigned char)~_BV(3) /* Watchdog Timeout Period Bit 3 */ -#define FUSE_WDWP0 (unsigned char)~_BV(4) /* Watchdog Window Timeout Period Bit 0 */ -#define FUSE_WDWP1 (unsigned char)~_BV(5) /* Watchdog Window Timeout Period Bit 1 */ -#define FUSE_WDWP2 (unsigned char)~_BV(6) /* Watchdog Window Timeout Period Bit 2 */ -#define FUSE_WDWP3 (unsigned char)~_BV(7) /* Watchdog Window Timeout Period Bit 3 */ -#define FUSE1_DEFAULT (0xFF) - -/* Fuse Byte 2 */ -#define FUSE_BODPD0 (unsigned char)~_BV(0) /* BOD Operation in Power-Down Mode Bit 0 */ -#define FUSE_BODPD1 (unsigned char)~_BV(1) /* BOD Operation in Power-Down Mode Bit 1 */ -#define FUSE_TOSCSEL (unsigned char)~_BV(5) /* Timer Oscillator pin location */ -#define FUSE_BOOTRST (unsigned char)~_BV(6) /* Boot Loader Section Reset Vector */ -#define FUSE2_DEFAULT (0xFF) - -/* Fuse Byte 3 Reserved */ - -/* Fuse Byte 4 */ -#define FUSE_WDLOCK (unsigned char)~_BV(1) /* Watchdog Timer Lock */ -#define FUSE_SUT0 (unsigned char)~_BV(2) /* Start-up Time Bit 0 */ -#define FUSE_SUT1 (unsigned char)~_BV(3) /* Start-up Time Bit 1 */ -#define FUSE_RSTDISBL (unsigned char)~_BV(4) /* External Reset Disable */ -#define FUSE4_DEFAULT (0xFF) - -/* Fuse Byte 5 */ -#define FUSE_BODLVL0 (unsigned char)~_BV(0) /* Brownout Detection Voltage Level Bit 0 */ -#define FUSE_BODLVL1 (unsigned char)~_BV(1) /* Brownout Detection Voltage Level Bit 1 */ -#define FUSE_BODLVL2 (unsigned char)~_BV(2) /* Brownout Detection Voltage Level Bit 2 */ -#define FUSE_EESAVE (unsigned char)~_BV(3) /* Preserve EEPROM Through Chip Erase */ -#define FUSE_BODACT0 (unsigned char)~_BV(4) /* BOD Operation in Active Mode Bit 0 */ -#define FUSE_BODACT1 (unsigned char)~_BV(5) /* BOD Operation in Active Mode Bit 1 */ -#define FUSE5_DEFAULT (0xFF) - -/* ========== Lock Bits ========== */ -#define __LOCK_BITS_EXIST -#define __BOOT_LOCK_APPLICATION_TABLE_BITS_EXIST -#define __BOOT_LOCK_APPLICATION_BITS_EXIST -#define __BOOT_LOCK_BOOT_BITS_EXIST - -/* ========== Signature ========== */ -#define SIGNATURE_0 0x1E -#define SIGNATURE_1 0x98 -#define SIGNATURE_2 0x46 - -/* ========== Power Reduction Condition Definitions ========== */ - -/* PR.PRGEN */ -#define __AVR_HAVE_PRGEN (PR_USB_bm|PR_AES_bm|PR_RTC_bm|PR_EVSYS_bm|PR_DMA_bm) -#define __AVR_HAVE_PRGEN_USB -#define __AVR_HAVE_PRGEN_AES -#define __AVR_HAVE_PRGEN_RTC -#define __AVR_HAVE_PRGEN_EVSYS -#define __AVR_HAVE_PRGEN_DMA - -/* PR.PRPA */ -#define __AVR_HAVE_PRPA (PR_ADC_bm|PR_AC_bm) -#define __AVR_HAVE_PRPA_ADC -#define __AVR_HAVE_PRPA_AC - -/* PR.PRPC */ -#define __AVR_HAVE_PRPC (PR_TWI_bm|PR_USART1_bm|PR_USART0_bm|PR_SPI_bm|PR_HIRES_bm|PR_TC1_bm|PR_TC0_bm) -#define __AVR_HAVE_PRPC_TWI -#define __AVR_HAVE_PRPC_USART1 -#define __AVR_HAVE_PRPC_USART0 -#define __AVR_HAVE_PRPC_SPI -#define __AVR_HAVE_PRPC_HIRES -#define __AVR_HAVE_PRPC_TC1 -#define __AVR_HAVE_PRPC_TC0 - -/* PR.PRPD */ -#define __AVR_HAVE_PRPD (PR_USART0_bm|PR_SPI_bm|PR_TC0_bm) -#define __AVR_HAVE_PRPD_USART0 -#define __AVR_HAVE_PRPD_SPI -#define __AVR_HAVE_PRPD_TC0 - -/* PR.PRPE */ -#define __AVR_HAVE_PRPE (PR_TWI_bm|PR_USART0_bm|PR_TC0_bm) -#define __AVR_HAVE_PRPE_TWI -#define __AVR_HAVE_PRPE_USART0 -#define __AVR_HAVE_PRPE_TC0 - -/* PR.PRPF */ -#define __AVR_HAVE_PRPF (PR_USART0_bm|PR_TC0_bm) -#define __AVR_HAVE_PRPF_USART0 -#define __AVR_HAVE_PRPF_TC0 - - -#endif /* #ifdef _AVR_ATXMEGA256C3_H_INCLUDED */ - diff --git a/arduino/hardware/tools/avr/avr/include/avr/iox256d3.h b/arduino/hardware/tools/avr/avr/include/avr/iox256d3.h deleted file mode 100644 index e303cac..0000000 --- a/arduino/hardware/tools/avr/avr/include/avr/iox256d3.h +++ /dev/null @@ -1,5709 +0,0 @@ -/* Copyright (c) 2009-2010 Atmel Corporation - All rights reserved. - - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - * Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - * Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in - the documentation and/or other materials provided with the - distribution. - - * Neither the name of the copyright holders nor the names of - contributors may be used to endorse or promote products derived - from this software without specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. */ - -/* $Id: iox256d3.h 2162 2010-06-11 17:26:12Z arcanum $ */ - -/* avr/iox256d3.h - definitions for ATxmega256D3 */ - -/* This file should only be included from , never directly. */ - -#ifndef _AVR_IO_H_ -# error "Include instead of this file." -#endif - -#ifndef _AVR_IOXXX_H_ -# define _AVR_IOXXX_H_ "iox256d3.h" -#else -# error "Attempt to include more than one file." -#endif - - -#ifndef _AVR_ATxmega256D3_H_ -#define _AVR_ATxmega256D3_H_ 1 - - -/* Ungrouped common registers */ -#define GPIOR0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ -#define GPIOR1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ -#define GPIOR2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ -#define GPIOR3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ -#define GPIOR4 _SFR_MEM8(0x0004) /* General Purpose IO Register 4 */ -#define GPIOR5 _SFR_MEM8(0x0005) /* General Purpose IO Register 5 */ -#define GPIOR6 _SFR_MEM8(0x0006) /* General Purpose IO Register 6 */ -#define GPIOR7 _SFR_MEM8(0x0007) /* General Purpose IO Register 7 */ -#define GPIOR8 _SFR_MEM8(0x0008) /* General Purpose IO Register 8 */ -#define GPIOR9 _SFR_MEM8(0x0009) /* General Purpose IO Register 9 */ -#define GPIORA _SFR_MEM8(0x000A) /* General Purpose IO Register 10 */ -#define GPIORB _SFR_MEM8(0x000B) /* General Purpose IO Register 11 */ -#define GPIORC _SFR_MEM8(0x000C) /* General Purpose IO Register 12 */ -#define GPIORD _SFR_MEM8(0x000D) /* General Purpose IO Register 13 */ -#define GPIORE _SFR_MEM8(0x000E) /* General Purpose IO Register 14 */ -#define GPIORF _SFR_MEM8(0x000F) /* General Purpose IO Register 15 */ - -#define CCP _SFR_MEM8(0x0034) /* Configuration Change Protection */ -#define RAMPD _SFR_MEM8(0x0038) /* Ramp D */ -#define RAMPX _SFR_MEM8(0x0039) /* Ramp X */ -#define RAMPY _SFR_MEM8(0x003A) /* Ramp Y */ -#define RAMPZ _SFR_MEM8(0x003B) /* Ramp Z */ -#define EIND _SFR_MEM8(0x003C) /* Extended Indirect Jump */ -#define SPL _SFR_MEM8(0x003D) /* Stack Pointer Low */ -#define SPH _SFR_MEM8(0x003E) /* Stack Pointer High */ -#define SREG _SFR_MEM8(0x003F) /* Status Register */ - - -/* C Language Only */ -#if !defined (__ASSEMBLER__) - -#include - -typedef volatile uint8_t register8_t; -typedef volatile uint16_t register16_t; -typedef volatile uint32_t register32_t; - - -#ifdef _WORDREGISTER -#undef _WORDREGISTER -#endif -#define _WORDREGISTER(regname) \ - __extension__ union \ - { \ - register16_t regname; \ - struct \ - { \ - register8_t regname ## L; \ - register8_t regname ## H; \ - }; \ - } - -#ifdef _DWORDREGISTER -#undef _DWORDREGISTER -#endif -#define _DWORDREGISTER(regname) \ - __extension__ union \ - { \ - register32_t regname; \ - struct \ - { \ - register8_t regname ## 0; \ - register8_t regname ## 1; \ - register8_t regname ## 2; \ - register8_t regname ## 3; \ - }; \ - } - - -/* -========================================================================== -IO Module Structures -========================================================================== -*/ - - -/* --------------------------------------------------------------------------- -XOCD - On-Chip Debug System --------------------------------------------------------------------------- -*/ - -/* On-Chip Debug System */ -typedef struct OCD_struct -{ - register8_t OCDR0; /* OCD Register 0 */ - register8_t OCDR1; /* OCD Register 1 */ -} OCD_t; - - -/* CCP signatures */ -typedef enum CCP_enum -{ - CCP_SPM_gc = (0x9D<<0), /* SPM Instruction Protection */ - CCP_IOREG_gc = (0xD8<<0), /* IO Register Protection */ -} CCP_t; - - -/* --------------------------------------------------------------------------- -CLK - Clock System --------------------------------------------------------------------------- -*/ - -/* Clock System */ -typedef struct CLK_struct -{ - register8_t CTRL; /* Control Register */ - register8_t PSCTRL; /* Prescaler Control Register */ - register8_t LOCK; /* Lock register */ - register8_t RTCCTRL; /* RTC Control Register */ -} CLK_t; - - -/* Power Reduction */ -typedef struct PR_struct -{ - register8_t PRGEN; /* General Power Reduction */ - register8_t PRPA; /* Power Reduction Port A */ - register8_t reserved_0x02; - register8_t PRPC; /* Power Reduction Port C */ - register8_t PRPD; /* Power Reduction Port D */ - register8_t PRPE; /* Power Reduction Port E */ - register8_t PRPF; /* Power Reduction Port F */ -} PR_t; - -/* System Clock Selection */ -typedef enum CLK_SCLKSEL_enum -{ - CLK_SCLKSEL_RC2M_gc = (0x00<<0), /* Internal 2MHz RC Oscillator */ - CLK_SCLKSEL_RC32M_gc = (0x01<<0), /* Internal 32MHz RC Oscillator */ - CLK_SCLKSEL_RC32K_gc = (0x02<<0), /* Internal 32kHz RC Oscillator */ - CLK_SCLKSEL_XOSC_gc = (0x03<<0), /* External Crystal Oscillator or Clock */ - CLK_SCLKSEL_PLL_gc = (0x04<<0), /* Phase Locked Loop */ -} CLK_SCLKSEL_t; - -/* Prescaler A Division Factor */ -typedef enum CLK_PSADIV_enum -{ - CLK_PSADIV_1_gc = (0x00<<2), /* Divide by 1 */ - CLK_PSADIV_2_gc = (0x01<<2), /* Divide by 2 */ - CLK_PSADIV_4_gc = (0x03<<2), /* Divide by 4 */ - CLK_PSADIV_8_gc = (0x05<<2), /* Divide by 8 */ - CLK_PSADIV_16_gc = (0x07<<2), /* Divide by 16 */ - CLK_PSADIV_32_gc = (0x09<<2), /* Divide by 32 */ - CLK_PSADIV_64_gc = (0x0B<<2), /* Divide by 64 */ - CLK_PSADIV_128_gc = (0x0D<<2), /* Divide by 128 */ - CLK_PSADIV_256_gc = (0x0F<<2), /* Divide by 256 */ - CLK_PSADIV_512_gc = (0x11<<2), /* Divide by 512 */ -} CLK_PSADIV_t; - -/* Prescaler B and C Division Factor */ -typedef enum CLK_PSBCDIV_enum -{ - CLK_PSBCDIV_1_1_gc = (0x00<<0), /* Divide B by 1 and C by 1 */ - CLK_PSBCDIV_1_2_gc = (0x01<<0), /* Divide B by 1 and C by 2 */ - CLK_PSBCDIV_4_1_gc = (0x02<<0), /* Divide B by 4 and C by 1 */ - CLK_PSBCDIV_2_2_gc = (0x03<<0), /* Divide B by 2 and C by 2 */ -} CLK_PSBCDIV_t; - -/* RTC Clock Source */ -typedef enum CLK_RTCSRC_enum -{ - CLK_RTCSRC_ULP_gc = (0x00<<1), /* 1kHz from internal 32kHz ULP */ - CLK_RTCSRC_TOSC_gc = (0x01<<1), /* 1kHz from 32kHz crystal oscillator on TOSC */ - CLK_RTCSRC_RCOSC_gc = (0x02<<1), /* 1kHz from internal 32kHz RC oscillator */ - CLK_RTCSRC_TOSC32_gc = (0x05<<1), /* 32kHz from 32kHz crystal oscillator on TOSC */ -} CLK_RTCSRC_t; - - -/* --------------------------------------------------------------------------- -SLEEP - Sleep Controller --------------------------------------------------------------------------- -*/ - -/* Sleep Controller */ -typedef struct SLEEP_struct -{ - register8_t CTRL; /* Control Register */ -} SLEEP_t; - -/* Sleep Mode */ -typedef enum SLEEP_SMODE_enum -{ - SLEEP_SMODE_IDLE_gc = (0x00<<1), /* Idle mode */ - SLEEP_SMODE_PDOWN_gc = (0x02<<1), /* Power-down Mode */ - SLEEP_SMODE_PSAVE_gc = (0x03<<1), /* Power-save Mode */ - SLEEP_SMODE_STDBY_gc = (0x06<<1), /* Standby Mode */ - SLEEP_SMODE_ESTDBY_gc = (0x07<<1), /* Extended Standby Mode */ -} SLEEP_SMODE_t; - - -#define SLEEP_MODE_IDLE (0x00<<1) -#define SLEEP_MODE_PWR_DOWN (0x02<<1) -#define SLEEP_MODE_PWR_SAVE (0x03<<1) -#define SLEEP_MODE_STANDBY (0x06<<1) -#define SLEEP_MODE_EXT_STANDBY (0x07<<1) - - -/* --------------------------------------------------------------------------- -OSC - Oscillator --------------------------------------------------------------------------- -*/ - -/* Oscillator */ -typedef struct OSC_struct -{ - register8_t CTRL; /* Control Register */ - register8_t STATUS; /* Status Register */ - register8_t XOSCCTRL; /* External Oscillator Control Register */ - register8_t XOSCFAIL; /* External Oscillator Failure Detection Register */ - register8_t RC32KCAL; /* 32kHz Internal Oscillator Calibration Register */ - register8_t PLLCTRL; /* PLL Control REgister */ - register8_t DFLLCTRL; /* DFLL Control Register */ -} OSC_t; - -/* Oscillator Frequency Range */ -typedef enum OSC_FRQRANGE_enum -{ - OSC_FRQRANGE_04TO2_gc = (0x00<<6), /* 0.4 - 2 MHz */ - OSC_FRQRANGE_2TO9_gc = (0x01<<6), /* 2 - 9 MHz */ - OSC_FRQRANGE_9TO12_gc = (0x02<<6), /* 9 - 12 MHz */ - OSC_FRQRANGE_12TO16_gc = (0x03<<6), /* 12 - 16 MHz */ -} OSC_FRQRANGE_t; - -/* External Oscillator Selection and Startup Time */ -typedef enum OSC_XOSCSEL_enum -{ - OSC_XOSCSEL_EXTCLK_gc = (0x00<<0), /* External Clock - 6 CLK */ - OSC_XOSCSEL_32KHz_gc = (0x02<<0), /* 32kHz TOSC - 32K CLK */ - OSC_XOSCSEL_XTAL_256CLK_gc = (0x03<<0), /* 0.4-16MHz XTAL - 256 CLK */ - OSC_XOSCSEL_XTAL_1KCLK_gc = (0x07<<0), /* 0.4-16MHz XTAL - 1K CLK */ - OSC_XOSCSEL_XTAL_16KCLK_gc = (0x0B<<0), /* 0.4-16MHz XTAL - 16K CLK */ -} OSC_XOSCSEL_t; - -/* PLL Clock Source */ -typedef enum OSC_PLLSRC_enum -{ - OSC_PLLSRC_RC2M_gc = (0x00<<6), /* Internal 2MHz RC Oscillator */ - OSC_PLLSRC_RC32M_gc = (0x02<<6), /* Internal 32MHz RC Oscillator */ - OSC_PLLSRC_XOSC_gc = (0x03<<6), /* External Oscillator */ -} OSC_PLLSRC_t; - - -/* --------------------------------------------------------------------------- -DFLL - DFLL --------------------------------------------------------------------------- -*/ - -/* DFLL */ -typedef struct DFLL_struct -{ - register8_t CTRL; /* Control Register */ - register8_t reserved_0x01; - register8_t CALA; /* Calibration Register A */ - register8_t CALB; /* Calibration Register B */ - register8_t COMP0; /* Oscillator Compare Register 0 */ - register8_t COMP1; /* Oscillator Compare Register 1 */ - register8_t COMP2; /* Oscillator Compare Register 2 */ - register8_t reserved_0x07; -} DFLL_t; - - -/* --------------------------------------------------------------------------- -RST - Reset --------------------------------------------------------------------------- -*/ - -/* Reset */ -typedef struct RST_struct -{ - register8_t STATUS; /* Status Register */ - register8_t CTRL; /* Control Register */ -} RST_t; - - -/* --------------------------------------------------------------------------- -WDT - Watch-Dog Timer --------------------------------------------------------------------------- -*/ - -/* Watch-Dog Timer */ -typedef struct WDT_struct -{ - register8_t CTRL; /* Control */ - register8_t WINCTRL; /* Windowed Mode Control */ - register8_t STATUS; /* Status */ -} WDT_t; - -/* Period setting */ -typedef enum WDT_PER_enum -{ - WDT_PER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ - WDT_PER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ - WDT_PER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ - WDT_PER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ - WDT_PER_125CLK_gc = (0x04<<2), /* 125 cycles (0.125s @ 3.3V) */ - WDT_PER_250CLK_gc = (0x05<<2), /* 250 cycles (0.25s @ 3.3V) */ - WDT_PER_500CLK_gc = (0x06<<2), /* 500 cycles (0.5s @ 3.3V) */ - WDT_PER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ - WDT_PER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ - WDT_PER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ - WDT_PER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ -} WDT_PER_t; - -/* Closed window period */ -typedef enum WDT_WPER_enum -{ - WDT_WPER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ - WDT_WPER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ - WDT_WPER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ - WDT_WPER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ - WDT_WPER_125CLK_gc = (0x04<<2), /* 125 cycles (0.125s @ 3.3V) */ - WDT_WPER_250CLK_gc = (0x05<<2), /* 250 cycles (0.25s @ 3.3V) */ - WDT_WPER_500CLK_gc = (0x06<<2), /* 500 cycles (0.5s @ 3.3V) */ - WDT_WPER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ - WDT_WPER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ - WDT_WPER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ - WDT_WPER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ -} WDT_WPER_t; - - -/* --------------------------------------------------------------------------- -MCU - MCU Control --------------------------------------------------------------------------- -*/ - -/* MCU Control */ -typedef struct MCU_struct -{ - register8_t DEVID0; /* Device ID byte 0 */ - register8_t DEVID1; /* Device ID byte 1 */ - register8_t DEVID2; /* Device ID byte 2 */ - register8_t REVID; /* Revision ID */ - register8_t JTAGUID; /* JTAG User ID */ - register8_t reserved_0x05; - register8_t MCUCR; /* MCU Control */ - register8_t reserved_0x07; - register8_t EVSYSLOCK; /* Event System Lock */ - register8_t AWEXLOCK; /* AWEX Lock */ - register8_t reserved_0x0A; - register8_t reserved_0x0B; -} MCU_t; - - -/* --------------------------------------------------------------------------- -PMIC - Programmable Multi-level Interrupt Controller --------------------------------------------------------------------------- -*/ - -/* Programmable Multi-level Interrupt Controller */ -typedef struct PMIC_struct -{ - register8_t STATUS; /* Status Register */ - register8_t INTPRI; /* Interrupt Priority */ - register8_t CTRL; /* Control Register */ -} PMIC_t; - - -/* --------------------------------------------------------------------------- -CRC - Cyclic Redundancy Checker --------------------------------------------------------------------------- -*/ - -/* Cyclic Redundancy Checker */ -typedef struct CRC_struct -{ - register8_t CTRL; /* Control Register */ - register8_t STATUS; /* Status Register */ - register8_t reserved_0x02; - register8_t DATAIN; /* Data Input */ - register8_t CHECKSUM0; /* Checksum byte 0 */ - register8_t CHECKSUM1; /* Checksum byte 1 */ - register8_t CHECKSUM2; /* Checksum byte 2 */ - register8_t CHECKSUM3; /* Checksum byte 3 */ -} CRC_t; - -/* Reset */ -typedef enum CRC_RESET_enum -{ - CRC_RESET_NO_gc = (0x00<<6), /* No Reset */ - CRC_RESET_RESET0_gc = (0x02<<6), /* Reset CRC with CHECKSUM to all zeros */ - CRC_RESET_RESET1_gc = (0x03<<6), /* Reset CRC with CHECKSUM to all ones */ -} CRC_RESET_t; - -/* Input Source */ -typedef enum CRC_SOURCE_enum -{ - CRC_SOURCE_DISABLE_gc = (0x00<<0), /* Disabled */ - CRC_SOURCE_IO_gc = (0x01<<0), /* I/O Interface */ - CRC_SOURCE_FLASH_gc = (0x02<<0), /* Flash */ - CRC_SOURCE_DMAC0_gc = (0x04<<0), /* DMAC Channel 0 */ - CRC_SOURCE_DMAC1_gc = (0x05<<0), /* DMAC Channel 1 */ - CRC_SOURCE_DMAC2_gc = (0x06<<0), /* DMAC Channel 2 */ - CRC_SOURCE_DMAC3_gc = (0x07<<0), /* DMAC Channel 3 */ -} CRC_SOURCE_t; - - -/* --------------------------------------------------------------------------- -EVSYS - Event System --------------------------------------------------------------------------- -*/ - -/* Event System */ -typedef struct EVSYS_struct -{ - register8_t CH0MUX; /* Event Channel 0 Multiplexer */ - register8_t CH1MUX; /* Event Channel 1 Multiplexer */ - register8_t CH2MUX; /* Event Channel 2 Multiplexer */ - register8_t CH3MUX; /* Event Channel 3 Multiplexer */ - register8_t reserved_0x04; - register8_t reserved_0x05; - register8_t reserved_0x06; - register8_t reserved_0x07; - register8_t CH0CTRL; /* Channel 0 Control Register */ - register8_t CH1CTRL; /* Channel 1 Control Register */ - register8_t CH2CTRL; /* Channel 2 Control Register */ - register8_t CH3CTRL; /* Channel 3 Control Register */ - register8_t reserved_0x0C; - register8_t reserved_0x0D; - register8_t reserved_0x0E; - register8_t reserved_0x0F; - register8_t STROBE; /* Event Strobe */ - register8_t DATA; /* Event Data */ -} EVSYS_t; - -/* Quadrature Decoder Index Recognition Mode */ -typedef enum EVSYS_QDIRM_enum -{ - EVSYS_QDIRM_00_gc = (0x00<<5), /* QDPH0 = 0, QDPH90 = 0 */ - EVSYS_QDIRM_01_gc = (0x01<<5), /* QDPH0 = 0, QDPH90 = 1 */ - EVSYS_QDIRM_10_gc = (0x02<<5), /* QDPH0 = 1, QDPH90 = 0 */ - EVSYS_QDIRM_11_gc = (0x03<<5), /* QDPH0 = 1, QDPH90 = 1 */ -} EVSYS_QDIRM_t; - -/* Digital filter coefficient */ -typedef enum EVSYS_DIGFILT_enum -{ - EVSYS_DIGFILT_1SAMPLE_gc = (0x00<<0), /* 1 SAMPLE */ - EVSYS_DIGFILT_2SAMPLES_gc = (0x01<<0), /* 2 SAMPLES */ - EVSYS_DIGFILT_3SAMPLES_gc = (0x02<<0), /* 3 SAMPLES */ - EVSYS_DIGFILT_4SAMPLES_gc = (0x03<<0), /* 4 SAMPLES */ - EVSYS_DIGFILT_5SAMPLES_gc = (0x04<<0), /* 5 SAMPLES */ - EVSYS_DIGFILT_6SAMPLES_gc = (0x05<<0), /* 6 SAMPLES */ - EVSYS_DIGFILT_7SAMPLES_gc = (0x06<<0), /* 7 SAMPLES */ - EVSYS_DIGFILT_8SAMPLES_gc = (0x07<<0), /* 8 SAMPLES */ -} EVSYS_DIGFILT_t; - -/* Event Channel multiplexer input selection */ -typedef enum EVSYS_CHMUX_enum -{ - EVSYS_CHMUX_OFF_gc = (0x00<<0), /* Off */ - EVSYS_CHMUX_RTC_OVF_gc = (0x08<<0), /* RTC Overflow */ - EVSYS_CHMUX_RTC_CMP_gc = (0x09<<0), /* RTC Compare Match */ - EVSYS_CHMUX_ACA_CH0_gc = (0x10<<0), /* Analog Comparator A Channel 0 */ - EVSYS_CHMUX_ACA_CH1_gc = (0x11<<0), /* Analog Comparator A Channel 1 */ - EVSYS_CHMUX_ACA_WIN_gc = (0x12<<0), /* Analog Comparator A Window */ - EVSYS_CHMUX_ADCA_CH0_gc = (0x20<<0), /* ADC A Channel 0 */ - EVSYS_CHMUX_PORTA_PIN0_gc = (0x50<<0), /* Port A, Pin0 */ - EVSYS_CHMUX_PORTA_PIN1_gc = (0x51<<0), /* Port A, Pin1 */ - EVSYS_CHMUX_PORTA_PIN2_gc = (0x52<<0), /* Port A, Pin2 */ - EVSYS_CHMUX_PORTA_PIN3_gc = (0x53<<0), /* Port A, Pin3 */ - EVSYS_CHMUX_PORTA_PIN4_gc = (0x54<<0), /* Port A, Pin4 */ - EVSYS_CHMUX_PORTA_PIN5_gc = (0x55<<0), /* Port A, Pin5 */ - EVSYS_CHMUX_PORTA_PIN6_gc = (0x56<<0), /* Port A, Pin6 */ - EVSYS_CHMUX_PORTA_PIN7_gc = (0x57<<0), /* Port A, Pin7 */ - EVSYS_CHMUX_PORTB_PIN0_gc = (0x58<<0), /* Port B, Pin0 */ - EVSYS_CHMUX_PORTB_PIN1_gc = (0x59<<0), /* Port B, Pin1 */ - EVSYS_CHMUX_PORTB_PIN2_gc = (0x5A<<0), /* Port B, Pin2 */ - EVSYS_CHMUX_PORTB_PIN3_gc = (0x5B<<0), /* Port B, Pin3 */ - EVSYS_CHMUX_PORTB_PIN4_gc = (0x5C<<0), /* Port B, Pin4 */ - EVSYS_CHMUX_PORTB_PIN5_gc = (0x5D<<0), /* Port B, Pin5 */ - EVSYS_CHMUX_PORTB_PIN6_gc = (0x5E<<0), /* Port B, Pin6 */ - EVSYS_CHMUX_PORTB_PIN7_gc = (0x5F<<0), /* Port B, Pin7 */ - EVSYS_CHMUX_PORTC_PIN0_gc = (0x60<<0), /* Port C, Pin0 */ - EVSYS_CHMUX_PORTC_PIN1_gc = (0x61<<0), /* Port C, Pin1 */ - EVSYS_CHMUX_PORTC_PIN2_gc = (0x62<<0), /* Port C, Pin2 */ - EVSYS_CHMUX_PORTC_PIN3_gc = (0x63<<0), /* Port C, Pin3 */ - EVSYS_CHMUX_PORTC_PIN4_gc = (0x64<<0), /* Port C, Pin4 */ - EVSYS_CHMUX_PORTC_PIN5_gc = (0x65<<0), /* Port C, Pin5 */ - EVSYS_CHMUX_PORTC_PIN6_gc = (0x66<<0), /* Port C, Pin6 */ - EVSYS_CHMUX_PORTC_PIN7_gc = (0x67<<0), /* Port C, Pin7 */ - EVSYS_CHMUX_PORTD_PIN0_gc = (0x68<<0), /* Port D, Pin0 */ - EVSYS_CHMUX_PORTD_PIN1_gc = (0x69<<0), /* Port D, Pin1 */ - EVSYS_CHMUX_PORTD_PIN2_gc = (0x6A<<0), /* Port D, Pin2 */ - EVSYS_CHMUX_PORTD_PIN3_gc = (0x6B<<0), /* Port D, Pin3 */ - EVSYS_CHMUX_PORTD_PIN4_gc = (0x6C<<0), /* Port D, Pin4 */ - EVSYS_CHMUX_PORTD_PIN5_gc = (0x6D<<0), /* Port D, Pin5 */ - EVSYS_CHMUX_PORTD_PIN6_gc = (0x6E<<0), /* Port D, Pin6 */ - EVSYS_CHMUX_PORTD_PIN7_gc = (0x6F<<0), /* Port D, Pin7 */ - EVSYS_CHMUX_PORTE_PIN0_gc = (0x70<<0), /* Port E, Pin0 */ - EVSYS_CHMUX_PORTE_PIN1_gc = (0x71<<0), /* Port E, Pin1 */ - EVSYS_CHMUX_PORTE_PIN2_gc = (0x72<<0), /* Port E, Pin2 */ - EVSYS_CHMUX_PORTE_PIN3_gc = (0x73<<0), /* Port E, Pin3 */ - EVSYS_CHMUX_PORTE_PIN4_gc = (0x74<<0), /* Port E, Pin4 */ - EVSYS_CHMUX_PORTE_PIN5_gc = (0x75<<0), /* Port E, Pin5 */ - EVSYS_CHMUX_PORTE_PIN6_gc = (0x76<<0), /* Port E, Pin6 */ - EVSYS_CHMUX_PORTE_PIN7_gc = (0x77<<0), /* Port E, Pin7 */ - EVSYS_CHMUX_PORTF_PIN0_gc = (0x78<<0), /* Port F, Pin0 */ - EVSYS_CHMUX_PORTF_PIN1_gc = (0x79<<0), /* Port F, Pin1 */ - EVSYS_CHMUX_PORTF_PIN2_gc = (0x7A<<0), /* Port F, Pin2 */ - EVSYS_CHMUX_PORTF_PIN3_gc = (0x7B<<0), /* Port F, Pin3 */ - EVSYS_CHMUX_PORTF_PIN4_gc = (0x7C<<0), /* Port F, Pin4 */ - EVSYS_CHMUX_PORTF_PIN5_gc = (0x7D<<0), /* Port F, Pin5 */ - EVSYS_CHMUX_PORTF_PIN6_gc = (0x7E<<0), /* Port F, Pin6 */ - EVSYS_CHMUX_PORTF_PIN7_gc = (0x7F<<0), /* Port F, Pin7 */ - EVSYS_CHMUX_PRESCALER_1_gc = (0x80<<0), /* Prescaler, divide by 1 */ - EVSYS_CHMUX_PRESCALER_2_gc = (0x81<<0), /* Prescaler, divide by 2 */ - EVSYS_CHMUX_PRESCALER_4_gc = (0x82<<0), /* Prescaler, divide by 4 */ - EVSYS_CHMUX_PRESCALER_8_gc = (0x83<<0), /* Prescaler, divide by 8 */ - EVSYS_CHMUX_PRESCALER_16_gc = (0x84<<0), /* Prescaler, divide by 16 */ - EVSYS_CHMUX_PRESCALER_32_gc = (0x85<<0), /* Prescaler, divide by 32 */ - EVSYS_CHMUX_PRESCALER_64_gc = (0x86<<0), /* Prescaler, divide by 64 */ - EVSYS_CHMUX_PRESCALER_128_gc = (0x87<<0), /* Prescaler, divide by 128 */ - EVSYS_CHMUX_PRESCALER_256_gc = (0x88<<0), /* Prescaler, divide by 256 */ - EVSYS_CHMUX_PRESCALER_512_gc = (0x89<<0), /* Prescaler, divide by 512 */ - EVSYS_CHMUX_PRESCALER_1024_gc = (0x8A<<0), /* Prescaler, divide by 1024 */ - EVSYS_CHMUX_PRESCALER_2048_gc = (0x8B<<0), /* Prescaler, divide by 2048 */ - EVSYS_CHMUX_PRESCALER_4096_gc = (0x8C<<0), /* Prescaler, divide by 4096 */ - EVSYS_CHMUX_PRESCALER_8192_gc = (0x8D<<0), /* Prescaler, divide by 8192 */ - EVSYS_CHMUX_PRESCALER_16384_gc = (0x8E<<0), /* Prescaler, divide by 16384 */ - EVSYS_CHMUX_PRESCALER_32768_gc = (0x8F<<0), /* Prescaler, divide by 32768 */ - EVSYS_CHMUX_TCC0_OVF_gc = (0xC0<<0), /* Timer/Counter C0 Overflow */ - EVSYS_CHMUX_TCC0_ERR_gc = (0xC1<<0), /* Timer/Counter C0 Error */ - EVSYS_CHMUX_TCC0_CCA_gc = (0xC4<<0), /* Timer/Counter C0 Compare or Capture A */ - EVSYS_CHMUX_TCC0_CCB_gc = (0xC5<<0), /* Timer/Counter C0 Compare or Capture B */ - EVSYS_CHMUX_TCC0_CCC_gc = (0xC6<<0), /* Timer/Counter C0 Compare or Capture C */ - EVSYS_CHMUX_TCC0_CCD_gc = (0xC7<<0), /* Timer/Counter C0 Compare or Capture D */ - EVSYS_CHMUX_TCC1_OVF_gc = (0xC8<<0), /* Timer/Counter C1 Overflow */ - EVSYS_CHMUX_TCC1_ERR_gc = (0xC9<<0), /* Timer/Counter C1 Error */ - EVSYS_CHMUX_TCC1_CCA_gc = (0xCC<<0), /* Timer/Counter C1 Compare or Capture A */ - EVSYS_CHMUX_TCC1_CCB_gc = (0xCD<<0), /* Timer/Counter C1 Compare or Capture B */ - EVSYS_CHMUX_TCD0_OVF_gc = (0xD0<<0), /* Timer/Counter D0 Overflow */ - EVSYS_CHMUX_TCD0_ERR_gc = (0xD1<<0), /* Timer/Counter D0 Error */ - EVSYS_CHMUX_TCD0_CCA_gc = (0xD4<<0), /* Timer/Counter D0 Compare or Capture A */ - EVSYS_CHMUX_TCD0_CCB_gc = (0xD5<<0), /* Timer/Counter D0 Compare or Capture B */ - EVSYS_CHMUX_TCD0_CCC_gc = (0xD6<<0), /* Timer/Counter D0 Compare or Capture C */ - EVSYS_CHMUX_TCD0_CCD_gc = (0xD7<<0), /* Timer/Counter D0 Compare or Capture D */ - EVSYS_CHMUX_TCD1_OVF_gc = (0xD8<<0), /* Timer/Counter D1 Overflow */ - EVSYS_CHMUX_TCD1_ERR_gc = (0xD9<<0), /* Timer/Counter D1 Error */ - EVSYS_CHMUX_TCD1_CCA_gc = (0xDC<<0), /* Timer/Counter D1 Compare or Capture A */ - EVSYS_CHMUX_TCD1_CCB_gc = (0xDD<<0), /* Timer/Counter D1 Compare or Capture B */ - EVSYS_CHMUX_TCE0_OVF_gc = (0xE0<<0), /* Timer/Counter E0 Overflow */ - EVSYS_CHMUX_TCE0_ERR_gc = (0xE1<<0), /* Timer/Counter E0 Error */ - EVSYS_CHMUX_TCE0_CCA_gc = (0xE4<<0), /* Timer/Counter E0 Compare or Capture A */ - EVSYS_CHMUX_TCE0_CCB_gc = (0xE5<<0), /* Timer/Counter E0 Compare or Capture B */ - EVSYS_CHMUX_TCE0_CCC_gc = (0xE6<<0), /* Timer/Counter E0 Compare or Capture C */ - EVSYS_CHMUX_TCE0_CCD_gc = (0xE7<<0), /* Timer/Counter E0 Compare or Capture D */ - EVSYS_CHMUX_TCE1_OVF_gc = (0xE8<<0), /* Timer/Counter E1 Overflow */ - EVSYS_CHMUX_TCE1_ERR_gc = (0xE9<<0), /* Timer/Counter E1 Error */ - EVSYS_CHMUX_TCE1_CCA_gc = (0xEC<<0), /* Timer/Counter E1 Compare or Capture A */ - EVSYS_CHMUX_TCE1_CCB_gc = (0xED<<0), /* Timer/Counter E1 Compare or Capture B */ - EVSYS_CHMUX_TCF0_OVF_gc = (0xF0<<0), /* Timer/Counter F0 Overflow */ - EVSYS_CHMUX_TCF0_ERR_gc = (0xF1<<0), /* Timer/Counter F0 Error */ - EVSYS_CHMUX_TCF0_CCA_gc = (0xF4<<0), /* Timer/Counter F0 Compare or Capture A */ - EVSYS_CHMUX_TCF0_CCB_gc = (0xF5<<0), /* Timer/Counter F0 Compare or Capture B */ - EVSYS_CHMUX_TCF0_CCC_gc = (0xF6<<0), /* Timer/Counter F0 Compare or Capture C */ - EVSYS_CHMUX_TCF0_CCD_gc = (0xF7<<0), /* Timer/Counter F0 Compare or Capture D */ - EVSYS_CHMUX_TCF1_OVF_gc = (0xF8<<0), /* Timer/Counter F1 Overflow */ - EVSYS_CHMUX_TCF1_ERR_gc = (0xF9<<0), /* Timer/Counter F1 Error */ - EVSYS_CHMUX_TCF1_CCA_gc = (0xFC<<0), /* Timer/Counter F1 Compare or Capture A */ - EVSYS_CHMUX_TCF1_CCB_gc = (0xFD<<0), /* Timer/Counter F1 Compare or Capture B */ -} EVSYS_CHMUX_t; - - -/* --------------------------------------------------------------------------- -NVM - Non Volatile Memory Controller --------------------------------------------------------------------------- -*/ - -/* Non-volatile Memory Controller */ -typedef struct NVM_struct -{ - register8_t ADDR0; /* Address Register 0 */ - register8_t ADDR1; /* Address Register 1 */ - register8_t ADDR2; /* Address Register 2 */ - register8_t reserved_0x03; - register8_t DATA0; /* Data Register 0 */ - register8_t DATA1; /* Data Register 1 */ - register8_t DATA2; /* Data Register 2 */ - register8_t reserved_0x07; - register8_t reserved_0x08; - register8_t reserved_0x09; - register8_t CMD; /* Command */ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t INTCTRL; /* Interrupt Control */ - register8_t reserved_0x0E; - register8_t STATUS; /* Status */ - register8_t LOCK_BITS; /* Lock Bits */ -} NVM_t; - -/* --------------------------------------------------------------------------- -NVM - Non Volatile Memory Controller --------------------------------------------------------------------------- -*/ - -/* Lock Bits */ -typedef struct NVM_LOCKBITS_struct -{ - register8_t LOCKBITS; /* Lock Bits */ -} NVM_LOCKBITS_t; - -/* --------------------------------------------------------------------------- -NVM - Non Volatile Memory Controller --------------------------------------------------------------------------- -*/ - -/* Fuses */ -typedef struct NVM_FUSES_struct -{ - register8_t FUSEBYTE0; /* User ID */ - register8_t FUSEBYTE1; /* Watchdog Configuration */ - register8_t FUSEBYTE2; /* Reset Configuration */ - register8_t reserved_0x03; - register8_t FUSEBYTE4; /* Start-up Configuration */ - register8_t FUSEBYTE5; /* EESAVE and BOD Level */ -} NVM_FUSES_t; - -/* --------------------------------------------------------------------------- -NVM - Non Volatile Memory Controller --------------------------------------------------------------------------- -*/ - -/* Production Signatures */ -typedef struct NVM_PROD_SIGNATURES_struct -{ - register8_t RCOSC2M; /* RCOSC 2MHz Calibration Value */ - register8_t reserved_0x01; - register8_t RCOSC32K; /* RCOSC 32kHz Calibration Value */ - register8_t RCOSC32M; /* RCOSC 32MHz Calibration Value */ - register8_t reserved_0x04; - register8_t reserved_0x05; - register8_t reserved_0x06; - register8_t reserved_0x07; - register8_t LOTNUM0; /* Lot Number Byte 0, ASCII */ - register8_t LOTNUM1; /* Lot Number Byte 1, ASCII */ - register8_t LOTNUM2; /* Lot Number Byte 2, ASCII */ - register8_t LOTNUM3; /* Lot Number Byte 3, ASCII */ - register8_t LOTNUM4; /* Lot Number Byte 4, ASCII */ - register8_t LOTNUM5; /* Lot Number Byte 5, ASCII */ - register8_t reserved_0x0E; - register8_t reserved_0x0F; - register8_t WAFNUM; /* Wafer Number */ - register8_t reserved_0x11; - register8_t COORDX0; /* Wafer Coordinate X Byte 0 */ - register8_t COORDX1; /* Wafer Coordinate X Byte 1 */ - register8_t COORDY0; /* Wafer Coordinate Y Byte 0 */ - register8_t COORDY1; /* Wafer Coordinate Y Byte 1 */ - register8_t reserved_0x16; - register8_t reserved_0x17; - register8_t reserved_0x18; - register8_t reserved_0x19; - register8_t reserved_0x1A; - register8_t reserved_0x1B; - register8_t reserved_0x1C; - register8_t reserved_0x1D; - register8_t reserved_0x1E; - register8_t reserved_0x1F; - register8_t ADCACAL0; /* ADCA Calibration Byte 0 */ - register8_t ADCACAL1; /* ADCA Calibration Byte 1 */ - register8_t reserved_0x22; - register8_t reserved_0x23; - register8_t ADCBCAL0; /* ADCB Calibration Byte 0 */ - register8_t ADCBCAL1; /* ADCB Calibration Byte 1 */ - register8_t reserved_0x26; - register8_t reserved_0x27; - register8_t reserved_0x28; - register8_t reserved_0x29; - register8_t reserved_0x2A; - register8_t reserved_0x2B; - register8_t reserved_0x2C; - register8_t reserved_0x2D; - register8_t TEMPSENSE0; /* Temperature Sensor Calibration Byte 0 */ - register8_t TEMPSENSE1; /* Temperature Sensor Calibration Byte 0 */ - register8_t reserved_0x30; - register8_t reserved_0x31; - register8_t reserved_0x32; - register8_t reserved_0x33; - register8_t reserved_0x34; - register8_t reserved_0x35; - register8_t reserved_0x36; - register8_t reserved_0x37; - register8_t reserved_0x38; - register8_t reserved_0x39; - register8_t reserved_0x3A; - register8_t reserved_0x3B; - register8_t reserved_0x3C; - register8_t reserved_0x3D; - register8_t reserved_0x3E; -} NVM_PROD_SIGNATURES_t; - -/* NVM Command */ -typedef enum NVM_CMD_enum -{ - NVM_CMD_NO_OPERATION_gc = (0x00<<0), /* Noop/Ordinary LPM */ - NVM_CMD_READ_CALIB_ROW_gc = (0x02<<0), /* Read calibration row */ - NVM_CMD_READ_USER_SIG_ROW_gc = (0x01<<0), /* Read user signature row */ - NVM_CMD_READ_EEPROM_gc = (0x06<<0), /* Read EEPROM */ - NVM_CMD_READ_FUSES_gc = (0x07<<0), /* Read fuse byte */ - NVM_CMD_WRITE_LOCK_BITS_gc = (0x08<<0), /* Write lock bits */ - NVM_CMD_ERASE_USER_SIG_ROW_gc = (0x18<<0), /* Erase user signature row */ - NVM_CMD_WRITE_USER_SIG_ROW_gc = (0x1A<<0), /* Write user signature row */ - NVM_CMD_ERASE_APP_gc = (0x20<<0), /* Erase Application Section */ - NVM_CMD_ERASE_APP_PAGE_gc = (0x22<<0), /* Erase Application Section page */ - NVM_CMD_LOAD_FLASH_BUFFER_gc = (0x23<<0), /* Load Flash page buffer */ - NVM_CMD_WRITE_APP_PAGE_gc = (0x24<<0), /* Write Application Section page */ - NVM_CMD_ERASE_WRITE_APP_PAGE_gc = (0x25<<0), /* Erase-and-write Application Section page */ - NVM_CMD_ERASE_FLASH_BUFFER_gc = (0x26<<0), /* Erase/flush Flash page buffer */ - NVM_CMD_ERASE_BOOT_PAGE_gc = (0x2A<<0), /* Erase Boot Section page */ - NVM_CMD_WRITE_BOOT_PAGE_gc = (0x2C<<0), /* Write Boot Section page */ - NVM_CMD_ERASE_WRITE_BOOT_PAGE_gc = (0x2D<<0), /* Erase-and-write Boot Section page */ - NVM_CMD_ERASE_EEPROM_gc = (0x30<<0), /* Erase EEPROM */ - NVM_CMD_ERASE_EEPROM_PAGE_gc = (0x32<<0), /* Erase EEPROM page */ - NVM_CMD_LOAD_EEPROM_BUFFER_gc = (0x33<<0), /* Load EEPROM page buffer */ - NVM_CMD_WRITE_EEPROM_PAGE_gc = (0x34<<0), /* Write EEPROM page */ - NVM_CMD_ERASE_WRITE_EEPROM_PAGE_gc = (0x35<<0), /* Erase-and-write EEPROM page */ - NVM_CMD_ERASE_EEPROM_BUFFER_gc = (0x36<<0), /* Erase/flush EEPROM page buffer */ - NVM_CMD_APP_CRC_gc = (0x38<<0), /* Generate Application section CRC */ - NVM_CMD_BOOT_CRC_gc = (0x39<<0), /* Generate Boot Section CRC */ - NVM_CMD_FLASH_RANGE_CRC_gc = (0x3A<<0), /* Generate Flash Range CRC */ -} NVM_CMD_t; - -/* SPM ready interrupt level */ -typedef enum NVM_SPMLVL_enum -{ - NVM_SPMLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ - NVM_SPMLVL_LO_gc = (0x01<<2), /* Low level */ - NVM_SPMLVL_MED_gc = (0x02<<2), /* Medium level */ - NVM_SPMLVL_HI_gc = (0x03<<2), /* High level */ -} NVM_SPMLVL_t; - -/* EEPROM ready interrupt level */ -typedef enum NVM_EELVL_enum -{ - NVM_EELVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ - NVM_EELVL_LO_gc = (0x01<<0), /* Low level */ - NVM_EELVL_MED_gc = (0x02<<0), /* Medium level */ - NVM_EELVL_HI_gc = (0x03<<0), /* High level */ -} NVM_EELVL_t; - -/* Boot lock bits - boot setcion */ -typedef enum NVM_BLBB_enum -{ - NVM_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ - NVM_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ - NVM_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ - NVM_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ -} NVM_BLBB_t; - -/* Boot lock bits - application section */ -typedef enum NVM_BLBA_enum -{ - NVM_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ - NVM_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ - NVM_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ - NVM_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ -} NVM_BLBA_t; - -/* Boot lock bits - application table section */ -typedef enum NVM_BLBAT_enum -{ - NVM_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ - NVM_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ - NVM_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ - NVM_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ -} NVM_BLBAT_t; - -/* Lock bits */ -typedef enum NVM_LB_enum -{ - NVM_LB_NOLOCK_gc = (0x03<<0), /* No locks */ - NVM_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ - NVM_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ -} NVM_LB_t; - -/* Boot Loader Section Reset Vector */ -typedef enum BOOTRST_enum -{ - BOOTRST_BOOTLDR_gc = (0x00<<6), /* Boot Loader Reset */ - BOOTRST_APPLICATION_gc = (0x01<<6), /* Application Reset */ -} BOOTRST_t; - -/* BOD operation */ -typedef enum BOD_enum -{ - BOD_INSAMPLEDMODE_gc = (0x01<<0), /* BOD enabled in sampled mode */ - BOD_CONTINOUSLY_gc = (0x02<<0), /* BOD enabled continuously */ - BOD_DISABLED_gc = (0x03<<0), /* BOD Disabled */ -} BOD_t; - -/* Watchdog (Window) Timeout Period */ -typedef enum WD_enum -{ - WD_8CLK_gc = (0x00<<4), /* 8 cycles (8ms @ 3.3V) */ - WD_16CLK_gc = (0x01<<4), /* 16 cycles (16ms @ 3.3V) */ - WD_32CLK_gc = (0x02<<4), /* 32 cycles (32ms @ 3.3V) */ - WD_64CLK_gc = (0x03<<4), /* 64 cycles (64ms @ 3.3V) */ - WD_128CLK_gc = (0x04<<4), /* 128 cycles (0.125s @ 3.3V) */ - WD_256CLK_gc = (0x05<<4), /* 256 cycles (0.25s @ 3.3V) */ - WD_512CLK_gc = (0x06<<4), /* 512 cycles (0.5s @ 3.3V) */ - WD_1KCLK_gc = (0x07<<4), /* 1K cycles (1s @ 3.3V) */ - WD_2KCLK_gc = (0x08<<4), /* 2K cycles (2s @ 3.3V) */ - WD_4KCLK_gc = (0x09<<4), /* 4K cycles (4s @ 3.3V) */ - WD_8KCLK_gc = (0x0A<<4), /* 8K cycles (8s @ 3.3V) */ -} WD_t; - -/* Start-up Time */ -typedef enum SUT_enum -{ - SUT_0MS_gc = (0x03<<2), /* 0 ms */ - SUT_4MS_gc = (0x01<<2), /* 4 ms */ - SUT_64MS_gc = (0x00<<2), /* 64 ms */ -} SUT_t; - -/* Brown Out Detection Voltage Level */ -typedef enum BODLVL_enum -{ - BODLVL_1V6_gc = (0x07<<0), /* 1.6 V */ - BODLVL_1V8_gc = (0x06<<0), /* 1.8 V */ - BODLVL_2V0_gc = (0x05<<0), /* 2.0 V */ - BODLVL_2V2_gc = (0x04<<0), /* 2.2 V */ - BODLVL_2V4_gc = (0x03<<0), /* 2.4 V */ - BODLVL_2V6_gc = (0x02<<0), /* 2.6 V */ - BODLVL_2V8_gc = (0x01<<0), /* 2.8 V */ - BODLVL_3V0_gc = (0x00<<0), /* 3.0 V */ -} BODLVL_t; - - -/* --------------------------------------------------------------------------- -AC - Analog Comparator --------------------------------------------------------------------------- -*/ - -/* Analog Comparator */ -typedef struct AC_struct -{ - register8_t AC0CTRL; /* Comparator 0 Control */ - register8_t AC1CTRL; /* Comparator 1 Control */ - register8_t AC0MUXCTRL; /* Comparator 0 MUX Control */ - register8_t AC1MUXCTRL; /* Comparator 1 MUX Control */ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t WINCTRL; /* Window Mode Control */ - register8_t STATUS; /* Status */ -} AC_t; - -/* Interrupt mode */ -typedef enum AC_INTMODE_enum -{ - AC_INTMODE_BOTHEDGES_gc = (0x00<<6), /* Interrupt on both edges */ - AC_INTMODE_FALLING_gc = (0x02<<6), /* Interrupt on falling edge */ - AC_INTMODE_RISING_gc = (0x03<<6), /* Interrupt on rising edge */ -} AC_INTMODE_t; - -/* Interrupt level */ -typedef enum AC_INTLVL_enum -{ - AC_INTLVL_OFF_gc = (0x00<<4), /* Interrupt disabled */ - AC_INTLVL_LO_gc = (0x01<<4), /* Low level */ - AC_INTLVL_MED_gc = (0x02<<4), /* Medium level */ - AC_INTLVL_HI_gc = (0x03<<4), /* High level */ -} AC_INTLVL_t; - -/* Hysteresis mode selection */ -typedef enum AC_HYSMODE_enum -{ - AC_HYSMODE_NO_gc = (0x00<<1), /* No hysteresis */ - AC_HYSMODE_SMALL_gc = (0x01<<1), /* Small hysteresis */ - AC_HYSMODE_LARGE_gc = (0x02<<1), /* Large hysteresis */ -} AC_HYSMODE_t; - -/* Positive input multiplexer selection */ -typedef enum AC_MUXPOS_enum -{ - AC_MUXPOS_PIN0_gc = (0x00<<3), /* Pin 0 */ - AC_MUXPOS_PIN1_gc = (0x01<<3), /* Pin 1 */ - AC_MUXPOS_PIN2_gc = (0x02<<3), /* Pin 2 */ - AC_MUXPOS_PIN3_gc = (0x03<<3), /* Pin 3 */ - AC_MUXPOS_PIN4_gc = (0x04<<3), /* Pin 4 */ - AC_MUXPOS_PIN5_gc = (0x05<<3), /* Pin 5 */ - AC_MUXPOS_PIN6_gc = (0x06<<3), /* Pin 6 */ -} AC_MUXPOS_t; - -/* Negative input multiplexer selection */ -typedef enum AC_MUXNEG_enum -{ - AC_MUXNEG_PIN0_gc = (0x00<<0), /* Pin 0 */ - AC_MUXNEG_PIN1_gc = (0x01<<0), /* Pin 1 */ - AC_MUXNEG_PIN3_gc = (0x02<<0), /* Pin 3 */ - AC_MUXNEG_PIN5_gc = (0x03<<0), /* Pin 5 */ - AC_MUXNEG_PIN7_gc = (0x04<<0), /* Pin 7 */ - AC_MUXNEG_BANDGAP_gc = (0x06<<0), /* Bandgap Reference */ - AC_MUXNEG_SCALER_gc = (0x07<<0), /* Internal voltage scaler */ -} AC_MUXNEG_t; - -/* Windows interrupt mode */ -typedef enum AC_WINTMODE_enum -{ - AC_WINTMODE_ABOVE_gc = (0x00<<2), /* Interrupt on above window */ - AC_WINTMODE_INSIDE_gc = (0x01<<2), /* Interrupt on inside window */ - AC_WINTMODE_BELOW_gc = (0x02<<2), /* Interrupt on below window */ - AC_WINTMODE_OUTSIDE_gc = (0x03<<2), /* Interrupt on outside window */ -} AC_WINTMODE_t; - -/* Window interrupt level */ -typedef enum AC_WINTLVL_enum -{ - AC_WINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ - AC_WINTLVL_LO_gc = (0x01<<0), /* Low priority */ - AC_WINTLVL_MED_gc = (0x02<<0), /* Medium priority */ - AC_WINTLVL_HI_gc = (0x03<<0), /* High priority */ -} AC_WINTLVL_t; - -/* Window mode state */ -typedef enum AC_WSTATE_enum -{ - AC_WSTATE_ABOVE_gc = (0x00<<6), /* Signal above window */ - AC_WSTATE_INSIDE_gc = (0x01<<6), /* Signal inside window */ - AC_WSTATE_BELOW_gc = (0x02<<6), /* Signal below window */ -} AC_WSTATE_t; - - -/* --------------------------------------------------------------------------- -ADC - Analog/Digital Converter --------------------------------------------------------------------------- -*/ - -/* ADC Channel */ -typedef struct ADC_CH_struct -{ - register8_t CTRL; /* Control Register */ - register8_t MUXCTRL; /* MUX Control */ - register8_t INTCTRL; /* Channel Interrupt Control */ - register8_t INTFLAGS; /* Interrupt Flags */ - _WORDREGISTER(RES); /* Channel Result */ - register8_t reserved_0x6; - register8_t reserved_0x7; -} ADC_CH_t; - -/* --------------------------------------------------------------------------- -ADC - Analog/Digital Converter --------------------------------------------------------------------------- -*/ - -/* Analog-to-Digital Converter */ -typedef struct ADC_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t REFCTRL; /* Reference Control */ - register8_t EVCTRL; /* Event Control */ - register8_t PRESCALER; /* Clock Prescaler */ - register8_t reserved_0x05; - register8_t INTFLAGS; /* Interrupt Flags */ - register8_t TEMP; /* ACD Temporary Register */ - register8_t reserved_0x08; - register8_t reserved_0x09; - register8_t reserved_0x0A; - register8_t reserved_0x0B; - _WORDREGISTER(CAL); /* Calibration Value */ - register8_t reserved_0x0E; - register8_t reserved_0x0F; - _WORDREGISTER(CH0RES); /* Channel 0 Result */ - register8_t reserved_0x12; - register8_t reserved_0x13; - register8_t reserved_0x14; - register8_t reserved_0x15; - register8_t reserved_0x16; - register8_t reserved_0x17; - _WORDREGISTER(CMP); /* Compare Value */ - register8_t reserved_0x1A; - register8_t reserved_0x1B; - register8_t reserved_0x1C; - register8_t reserved_0x1D; - register8_t reserved_0x1E; - register8_t reserved_0x1F; - ADC_CH_t CH0; /* ADC Channel 0 */ -} ADC_t; - -/* Current Limitation */ -typedef enum ADC_CURRLIMIT_enum -{ - ADC_CURRLIMIT_NO_gc = (0x00<<5), /* No current limit, 300ksps max sampling rate */ - ADC_CURRLIMIT_LOW_gc = (0x01<<5), /* Low current limit, 225ksps max sampling rate */ - ADC_CURRLIMIT_MED_gc = (0x02<<5), /* Medium current limit, 150ksps max sampling rate */ - ADC_CURRLIMIT_HIGH_gc = (0x03<<5), /* High current limit, 75ksps max sampling rate */ -} ADC_CURRLIMIT_t; - -/* Positive input multiplexer selection */ -typedef enum ADC_CH_MUXPOS_enum -{ - ADC_CH_MUXPOS_PIN0_gc = (0x00<<3), /* Input pin 0 */ - ADC_CH_MUXPOS_PIN1_gc = (0x01<<3), /* Input pin 1 */ - ADC_CH_MUXPOS_PIN2_gc = (0x02<<3), /* Input pin 2 */ - ADC_CH_MUXPOS_PIN3_gc = (0x03<<3), /* Input pin 3 */ - ADC_CH_MUXPOS_PIN4_gc = (0x04<<3), /* Input pin 4 */ - ADC_CH_MUXPOS_PIN5_gc = (0x05<<3), /* Input pin 5 */ - ADC_CH_MUXPOS_PIN6_gc = (0x06<<3), /* Input pin 6 */ - ADC_CH_MUXPOS_PIN7_gc = (0x07<<3), /* Input pin 7 */ -} ADC_CH_MUXPOS_t; - -/* Negative input multiplexer selection */ -typedef enum ADC_CH_MUXNEG_enum -{ - ADC_CH_MUXNEG_PIN0_gc = (0x00<<0), /* Input pin 0 */ - ADC_CH_MUXNEG_PIN1_gc = (0x01<<0), /* Input pin 1 */ - ADC_CH_MUXNEG_PIN2_gc = (0x02<<0), /* Input pin 2 */ - ADC_CH_MUXNEG_PIN3_gc = (0x03<<0), /* Input pin 3 */ - ADC_CH_MUXNEG_PIN4_gc = (0x04<<0), /* Input pin 4 */ - ADC_CH_MUXNEG_PIN5_gc = (0x05<<0), /* Input pin 5 */ - ADC_CH_MUXNEG_PIN6_gc = (0x06<<0), /* Input pin 6 */ - ADC_CH_MUXNEG_PIN7_gc = (0x07<<0), /* Input pin 7 */ -} ADC_CH_MUXNEG_t; - -/* Input mode */ -typedef enum ADC_CH_INPUTMODE_enum -{ - ADC_CH_INPUTMODE_INTERNAL_gc = (0x00<<0), /* Internal inputs, no gain */ - ADC_CH_INPUTMODE_SINGLEENDED_gc = (0x01<<0), /* Single-ended input, no gain */ - ADC_CH_INPUTMODE_DIFF_gc = (0x02<<0), /* Differential input, no gain */ - ADC_CH_INPUTMODE_DIFFWGAIN_gc = (0x03<<0), /* Differential input, with gain */ -} ADC_CH_INPUTMODE_t; - -/* Gain factor */ -typedef enum ADC_CH_GAIN_enum -{ - ADC_CH_GAIN_1X_gc = (0x00<<2), /* 1x gain */ - ADC_CH_GAIN_2X_gc = (0x01<<2), /* 2x gain */ - ADC_CH_GAIN_4X_gc = (0x02<<2), /* 4x gain */ - ADC_CH_GAIN_8X_gc = (0x03<<2), /* 8x gain */ - ADC_CH_GAIN_16X_gc = (0x04<<2), /* 16x gain */ - ADC_CH_GAIN_32X_gc = (0x05<<2), /* 32x gain */ - ADC_CH_GAIN_64X_gc = (0x06<<2), /* 64x gain */ - ADC_CH_GAIN_DIV2_gc = (0x07<<2), /* x/2 gain */ -} ADC_CH_GAIN_t; - -/* Conversion result resolution */ -typedef enum ADC_RESOLUTION_enum -{ - ADC_RESOLUTION_12BIT_gc = (0x00<<1), /* 12-bit right-adjusted result */ - ADC_RESOLUTION_8BIT_gc = (0x02<<1), /* 8-bit right-adjusted result */ - ADC_RESOLUTION_LEFT12BIT_gc = (0x03<<1), /* 12-bit left-adjusted result */ -} ADC_RESOLUTION_t; - -/* Voltage reference selection */ -typedef enum ADC_REFSEL_enum -{ - ADC_REFSEL_INT1V_gc = (0x00<<4), /* Internal 1V */ - ADC_REFSEL_VCC_gc = (0x01<<4), /* Internal VCC/1.6V */ - ADC_REFSEL_AREFA_gc = (0x02<<4), /* External reference on PORT A */ - ADC_REFSEL_AREFB_gc = (0x03<<4), /* External reference on PORT B */ -} ADC_REFSEL_t; - -/* Event channel input selection */ -typedef enum ADC_EVSEL_enum -{ - ADC_EVSEL_0123_gc = (0x00<<3), /* Event Channel 0,1,2,3 */ - ADC_EVSEL_1234_gc = (0x01<<3), /* Event Channel 1,2,3,4 */ - ADC_EVSEL_2345_gc = (0x02<<3), /* Event Channel 2,3,4,5 */ - ADC_EVSEL_3456_gc = (0x03<<3), /* Event Channel 3,4,5,6 */ - ADC_EVSEL_4567_gc = (0x04<<3), /* Event Channel 4,5,6,7 */ - ADC_EVSEL_567_gc = (0x05<<3), /* Event Channel 5,6,7 */ - ADC_EVSEL_67_gc = (0x06<<3), /* Event Channel 6,7 */ - ADC_EVSEL_7_gc = (0x07<<3), /* Event Channel 7 */ -} ADC_EVSEL_t; - -/* Event action selection */ -typedef enum ADC_EVACT_enum -{ - ADC_EVACT_NONE_gc = (0x00<<0), /* No event action */ - ADC_EVACT_CH0_gc = (0x01<<0), /* First event triggers channel 0 */ -} ADC_EVACT_t; - -/* Interupt mode */ -typedef enum ADC_CH_INTMODE_enum -{ - ADC_CH_INTMODE_COMPLETE_gc = (0x00<<2), /* Interrupt on conversion complete */ - ADC_CH_INTMODE_BELOW_gc = (0x01<<2), /* Interrupt on result below compare value */ - ADC_CH_INTMODE_ABOVE_gc = (0x03<<2), /* Interrupt on result above compare value */ -} ADC_CH_INTMODE_t; - -/* Interrupt level */ -typedef enum ADC_CH_INTLVL_enum -{ - ADC_CH_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ - ADC_CH_INTLVL_LO_gc = (0x01<<0), /* Low level */ - ADC_CH_INTLVL_MED_gc = (0x02<<0), /* Medium level */ - ADC_CH_INTLVL_HI_gc = (0x03<<0), /* High level */ -} ADC_CH_INTLVL_t; - -/* Clock prescaler */ -typedef enum ADC_PRESCALER_enum -{ - ADC_PRESCALER_DIV4_gc = (0x00<<0), /* Divide clock by 4 */ - ADC_PRESCALER_DIV8_gc = (0x01<<0), /* Divide clock by 8 */ - ADC_PRESCALER_DIV16_gc = (0x02<<0), /* Divide clock by 16 */ - ADC_PRESCALER_DIV32_gc = (0x03<<0), /* Divide clock by 32 */ - ADC_PRESCALER_DIV64_gc = (0x04<<0), /* Divide clock by 64 */ - ADC_PRESCALER_DIV128_gc = (0x05<<0), /* Divide clock by 128 */ - ADC_PRESCALER_DIV256_gc = (0x06<<0), /* Divide clock by 256 */ - ADC_PRESCALER_DIV512_gc = (0x07<<0), /* Divide clock by 512 */ -} ADC_PRESCALER_t; - - -/* --------------------------------------------------------------------------- -RTC - Real-Time Clounter --------------------------------------------------------------------------- -*/ - -/* Real-Time Counter */ -typedef struct RTC_struct -{ - register8_t CTRL; /* Control Register */ - register8_t STATUS; /* Status Register */ - register8_t INTCTRL; /* Interrupt Control Register */ - register8_t INTFLAGS; /* Interrupt Flags */ - register8_t TEMP; /* Temporary register */ - register8_t reserved_0x05; - register8_t reserved_0x06; - register8_t reserved_0x07; - _WORDREGISTER(CNT); /* Count Register */ - _WORDREGISTER(PER); /* Period Register */ - _WORDREGISTER(COMP); /* Compare Register */ -} RTC_t; - -/* Prescaler Factor */ -typedef enum RTC_PRESCALER_enum -{ - RTC_PRESCALER_OFF_gc = (0x00<<0), /* RTC Off */ - RTC_PRESCALER_DIV1_gc = (0x01<<0), /* RTC Clock */ - RTC_PRESCALER_DIV2_gc = (0x02<<0), /* RTC Clock / 2 */ - RTC_PRESCALER_DIV8_gc = (0x03<<0), /* RTC Clock / 8 */ - RTC_PRESCALER_DIV16_gc = (0x04<<0), /* RTC Clock / 16 */ - RTC_PRESCALER_DIV64_gc = (0x05<<0), /* RTC Clock / 64 */ - RTC_PRESCALER_DIV256_gc = (0x06<<0), /* RTC Clock / 256 */ - RTC_PRESCALER_DIV1024_gc = (0x07<<0), /* RTC Clock / 1024 */ -} RTC_PRESCALER_t; - -/* Compare Interrupt level */ -typedef enum RTC_COMPINTLVL_enum -{ - RTC_COMPINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ - RTC_COMPINTLVL_LO_gc = (0x01<<2), /* Low Level */ - RTC_COMPINTLVL_MED_gc = (0x02<<2), /* Medium Level */ - RTC_COMPINTLVL_HI_gc = (0x03<<2), /* High Level */ -} RTC_COMPINTLVL_t; - -/* Overflow Interrupt level */ -typedef enum RTC_OVFINTLVL_enum -{ - RTC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - RTC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ - RTC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ - RTC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ -} RTC_OVFINTLVL_t; - - -/* --------------------------------------------------------------------------- -EBI - External Bus Interface --------------------------------------------------------------------------- -*/ - -/* EBI Chip Select Module */ -typedef struct EBI_CS_struct -{ - register8_t CTRLA; /* Chip Select Control Register A */ - register8_t CTRLB; /* Chip Select Control Register B */ - _WORDREGISTER(BASEADDR); /* Chip Select Base Address */ -} EBI_CS_t; - -/* --------------------------------------------------------------------------- -EBI - External Bus Interface --------------------------------------------------------------------------- -*/ - -/* External Bus Interface */ -typedef struct EBI_struct -{ - register8_t CTRL; /* Control */ - register8_t SDRAMCTRLA; /* SDRAM Control Register A */ - register8_t reserved_0x02; - register8_t reserved_0x03; - _WORDREGISTER(REFRESH); /* SDRAM Refresh Period */ - _WORDREGISTER(INITDLY); /* SDRAM Initialization Delay */ - register8_t SDRAMCTRLB; /* SDRAM Control Register B */ - register8_t SDRAMCTRLC; /* SDRAM Control Register C */ - register8_t reserved_0x0A; - register8_t reserved_0x0B; - register8_t reserved_0x0C; - register8_t reserved_0x0D; - register8_t reserved_0x0E; - register8_t reserved_0x0F; - EBI_CS_t CS0; /* Chip Select 0 */ - EBI_CS_t CS1; /* Chip Select 1 */ - EBI_CS_t CS2; /* Chip Select 2 */ - EBI_CS_t CS3; /* Chip Select 3 */ -} EBI_t; - -/* Chip Select adress space */ -typedef enum EBI_CS_ASIZE_enum -{ - EBI_CS_ASIZE_256B_gc = (0x00<<2), /* 256 bytes */ - EBI_CS_ASIZE_512B_gc = (0x01<<2), /* 512 bytes */ - EBI_CS_ASIZE_1KB_gc = (0x02<<2), /* 1K bytes */ - EBI_CS_ASIZE_2KB_gc = (0x03<<2), /* 2K bytes */ - EBI_CS_ASIZE_4KB_gc = (0x04<<2), /* 4K bytes */ - EBI_CS_ASIZE_8KB_gc = (0x05<<2), /* 8K bytes */ - EBI_CS_ASIZE_16KB_gc = (0x06<<2), /* 16K bytes */ - EBI_CS_ASIZE_32KB_gc = (0x07<<2), /* 32K bytes */ - EBI_CS_ASIZE_64KB_gc = (0x08<<2), /* 64K bytes */ - EBI_CS_ASIZE_128KB_gc = (0x09<<2), /* 128K bytes */ - EBI_CS_ASIZE_256KB_gc = (0x0A<<2), /* 256K bytes */ - EBI_CS_ASIZE_512KB_gc = (0x0B<<2), /* 512K bytes */ - EBI_CS_ASIZE_1MB_gc = (0x0C<<2), /* 1M bytes */ - EBI_CS_ASIZE_2MB_gc = (0x0D<<2), /* 2M bytes */ - EBI_CS_ASIZE_4MB_gc = (0x0E<<2), /* 4M bytes */ - EBI_CS_ASIZE_8MB_gc = (0x0F<<2), /* 8M bytes */ - EBI_CS_ASIZE_16M_gc = (0x10<<2), /* 16M bytes */ -} EBI_CS_ASIZE_t; - -/* */ -typedef enum EBI_CS_SRWS_enum -{ - EBI_CS_SRWS_0CLK_gc = (0x00<<0), /* 0 cycles */ - EBI_CS_SRWS_1CLK_gc = (0x01<<0), /* 1 cycle */ - EBI_CS_SRWS_2CLK_gc = (0x02<<0), /* 2 cycles */ - EBI_CS_SRWS_3CLK_gc = (0x03<<0), /* 3 cycles */ - EBI_CS_SRWS_4CLK_gc = (0x04<<0), /* 4 cycles */ - EBI_CS_SRWS_5CLK_gc = (0x05<<0), /* 5 cycle */ - EBI_CS_SRWS_6CLK_gc = (0x06<<0), /* 6 cycles */ - EBI_CS_SRWS_7CLK_gc = (0x07<<0), /* 7 cycles */ -} EBI_CS_SRWS_t; - -/* Chip Select address mode */ -typedef enum EBI_CS_MODE_enum -{ - EBI_CS_MODE_DISABLED_gc = (0x00<<0), /* Chip Select Disabled */ - EBI_CS_MODE_SRAM_gc = (0x01<<0), /* Chip Select in SRAM mode */ - EBI_CS_MODE_LPC_gc = (0x02<<0), /* Chip Select in SRAM LPC mode */ - EBI_CS_MODE_SDRAM_gc = (0x03<<0), /* Chip Select in SDRAM mode */ -} EBI_CS_MODE_t; - -/* Chip Select SDRAM mode */ -typedef enum EBI_CS_SDMODE_enum -{ - EBI_CS_SDMODE_NORMAL_gc = (0x00<<0), /* Normal mode */ - EBI_CS_SDMODE_LOAD_gc = (0x01<<0), /* Load Mode Register command mode */ -} EBI_CS_SDMODE_t; - -/* */ -typedef enum EBI_SDDATAW_enum -{ - EBI_SDDATAW_4BIT_gc = (0x00<<6), /* 4-bit data bus */ - EBI_SDDATAW_8BIT_gc = (0x01<<6), /* 8-bit data bus */ -} EBI_SDDATAW_t; - -/* */ -typedef enum EBI_LPCMODE_enum -{ - EBI_LPCMODE_ALE1_gc = (0x00<<4), /* Data muxed with addr byte 0 */ - EBI_LPCMODE_ALE12_gc = (0x02<<4), /* Data muxed with addr byte 0 and 1 */ -} EBI_LPCMODE_t; - -/* */ -typedef enum EBI_SRMODE_enum -{ - EBI_SRMODE_ALE1_gc = (0x00<<2), /* Addr byte 0 muxed with 1 */ - EBI_SRMODE_ALE2_gc = (0x01<<2), /* Addr byte 0 muxed with 2 */ - EBI_SRMODE_ALE12_gc = (0x02<<2), /* Addr byte 0 muxed with 1 and 2 */ - EBI_SRMODE_NOALE_gc = (0x03<<2), /* No addr muxing */ -} EBI_SRMODE_t; - -/* */ -typedef enum EBI_IFMODE_enum -{ - EBI_IFMODE_DISABLED_gc = (0x00<<0), /* EBI Disabled */ - EBI_IFMODE_3PORT_gc = (0x01<<0), /* 3-port mode */ - EBI_IFMODE_4PORT_gc = (0x02<<0), /* 4-port mode */ - EBI_IFMODE_2PORT_gc = (0x03<<0), /* 2-port mode */ -} EBI_IFMODE_t; - -/* */ -typedef enum EBI_SDCOL_enum -{ - EBI_SDCOL_8BIT_gc = (0x00<<0), /* 8 column bits */ - EBI_SDCOL_9BIT_gc = (0x01<<0), /* 9 column bits */ - EBI_SDCOL_10BIT_gc = (0x02<<0), /* 10 column bits */ - EBI_SDCOL_11BIT_gc = (0x03<<0), /* 11 column bits */ -} EBI_SDCOL_t; - -/* */ -typedef enum EBI_MRDLY_enum -{ - EBI_MRDLY_0CLK_gc = (0x00<<6), /* 0 cycles */ - EBI_MRDLY_1CLK_gc = (0x01<<6), /* 1 cycle */ - EBI_MRDLY_2CLK_gc = (0x02<<6), /* 2 cycles */ - EBI_MRDLY_3CLK_gc = (0x03<<6), /* 3 cycles */ -} EBI_MRDLY_t; - -/* */ -typedef enum EBI_ROWCYCDLY_enum -{ - EBI_ROWCYCDLY_0CLK_gc = (0x00<<3), /* 0 cycles */ - EBI_ROWCYCDLY_1CLK_gc = (0x01<<3), /* 1 cycle */ - EBI_ROWCYCDLY_2CLK_gc = (0x02<<3), /* 2 cycles */ - EBI_ROWCYCDLY_3CLK_gc = (0x03<<3), /* 3 cycles */ - EBI_ROWCYCDLY_4CLK_gc = (0x04<<3), /* 4 cycles */ - EBI_ROWCYCDLY_5CLK_gc = (0x05<<3), /* 5 cycle */ - EBI_ROWCYCDLY_6CLK_gc = (0x06<<3), /* 6 cycles */ - EBI_ROWCYCDLY_7CLK_gc = (0x07<<3), /* 7 cycles */ -} EBI_ROWCYCDLY_t; - -/* */ -typedef enum EBI_RPDLY_enum -{ - EBI_RPDLY_0CLK_gc = (0x00<<0), /* 0 cycles */ - EBI_RPDLY_1CLK_gc = (0x01<<0), /* 1 cycle */ - EBI_RPDLY_2CLK_gc = (0x02<<0), /* 2 cycles */ - EBI_RPDLY_3CLK_gc = (0x03<<0), /* 3 cycles */ - EBI_RPDLY_4CLK_gc = (0x04<<0), /* 4 cycles */ - EBI_RPDLY_5CLK_gc = (0x05<<0), /* 5 cycle */ - EBI_RPDLY_6CLK_gc = (0x06<<0), /* 6 cycles */ - EBI_RPDLY_7CLK_gc = (0x07<<0), /* 7 cycles */ -} EBI_RPDLY_t; - -/* */ -typedef enum EBI_WRDLY_enum -{ - EBI_WRDLY_0CLK_gc = (0x00<<6), /* 0 cycles */ - EBI_WRDLY_1CLK_gc = (0x01<<6), /* 1 cycle */ - EBI_WRDLY_2CLK_gc = (0x02<<6), /* 2 cycles */ - EBI_WRDLY_3CLK_gc = (0x03<<6), /* 3 cycles */ -} EBI_WRDLY_t; - -/* */ -typedef enum EBI_ESRDLY_enum -{ - EBI_ESRDLY_0CLK_gc = (0x00<<3), /* 0 cycles */ - EBI_ESRDLY_1CLK_gc = (0x01<<3), /* 1 cycle */ - EBI_ESRDLY_2CLK_gc = (0x02<<3), /* 2 cycles */ - EBI_ESRDLY_3CLK_gc = (0x03<<3), /* 3 cycles */ - EBI_ESRDLY_4CLK_gc = (0x04<<3), /* 4 cycles */ - EBI_ESRDLY_5CLK_gc = (0x05<<3), /* 5 cycle */ - EBI_ESRDLY_6CLK_gc = (0x06<<3), /* 6 cycles */ - EBI_ESRDLY_7CLK_gc = (0x07<<3), /* 7 cycles */ -} EBI_ESRDLY_t; - -/* */ -typedef enum EBI_ROWCOLDLY_enum -{ - EBI_ROWCOLDLY_0CLK_gc = (0x00<<0), /* 0 cycles */ - EBI_ROWCOLDLY_1CLK_gc = (0x01<<0), /* 1 cycle */ - EBI_ROWCOLDLY_2CLK_gc = (0x02<<0), /* 2 cycles */ - EBI_ROWCOLDLY_3CLK_gc = (0x03<<0), /* 3 cycles */ - EBI_ROWCOLDLY_4CLK_gc = (0x04<<0), /* 4 cycles */ - EBI_ROWCOLDLY_5CLK_gc = (0x05<<0), /* 5 cycle */ - EBI_ROWCOLDLY_6CLK_gc = (0x06<<0), /* 6 cycles */ - EBI_ROWCOLDLY_7CLK_gc = (0x07<<0), /* 7 cycles */ -} EBI_ROWCOLDLY_t; - - -/* --------------------------------------------------------------------------- -TWI - Two-Wire Interface --------------------------------------------------------------------------- -*/ - -/* */ -typedef struct TWI_MASTER_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t CTRLC; /* Control Register C */ - register8_t STATUS; /* Status Register */ - register8_t BAUD; /* Baurd Rate Control Register */ - register8_t ADDR; /* Address Register */ - register8_t DATA; /* Data Register */ -} TWI_MASTER_t; - -/* --------------------------------------------------------------------------- -TWI - Two-Wire Interface --------------------------------------------------------------------------- -*/ - -/* */ -typedef struct TWI_SLAVE_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t STATUS; /* Status Register */ - register8_t ADDR; /* Address Register */ - register8_t DATA; /* Data Register */ - register8_t ADDRMASK; /* Address Mask Register */ -} TWI_SLAVE_t; - -/* --------------------------------------------------------------------------- -TWI - Two-Wire Interface --------------------------------------------------------------------------- -*/ - -/* Two-Wire Interface */ -typedef struct TWI_struct -{ - register8_t CTRL; /* TWI Common Control Register */ - TWI_MASTER_t MASTER; /* TWI master module */ - TWI_SLAVE_t SLAVE; /* TWI slave module */ -} TWI_t; - -/* Master Interrupt Level */ -typedef enum TWI_MASTER_INTLVL_enum -{ - TWI_MASTER_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ - TWI_MASTER_INTLVL_LO_gc = (0x01<<6), /* Low Level */ - TWI_MASTER_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ - TWI_MASTER_INTLVL_HI_gc = (0x03<<6), /* High Level */ -} TWI_MASTER_INTLVL_t; - -/* Inactive Timeout */ -typedef enum TWI_MASTER_TIMEOUT_enum -{ - TWI_MASTER_TIMEOUT_DISABLED_gc = (0x00<<2), /* Bus Timeout Disabled */ - TWI_MASTER_TIMEOUT_50US_gc = (0x01<<2), /* 50 Microseconds */ - TWI_MASTER_TIMEOUT_100US_gc = (0x02<<2), /* 100 Microseconds */ - TWI_MASTER_TIMEOUT_200US_gc = (0x03<<2), /* 200 Microseconds */ -} TWI_MASTER_TIMEOUT_t; - -/* Master Command */ -typedef enum TWI_MASTER_CMD_enum -{ - TWI_MASTER_CMD_NOACT_gc = (0x00<<0), /* No Action */ - TWI_MASTER_CMD_REPSTART_gc = (0x01<<0), /* Issue Repeated Start Condition */ - TWI_MASTER_CMD_RECVTRANS_gc = (0x02<<0), /* Receive or Transmit Data */ - TWI_MASTER_CMD_STOP_gc = (0x03<<0), /* Issue Stop Condition */ -} TWI_MASTER_CMD_t; - -/* Master Bus State */ -typedef enum TWI_MASTER_BUSSTATE_enum -{ - TWI_MASTER_BUSSTATE_UNKNOWN_gc = (0x00<<0), /* Unknown Bus State */ - TWI_MASTER_BUSSTATE_IDLE_gc = (0x01<<0), /* Bus is Idle */ - TWI_MASTER_BUSSTATE_OWNER_gc = (0x02<<0), /* This Module Controls The Bus */ - TWI_MASTER_BUSSTATE_BUSY_gc = (0x03<<0), /* The Bus is Busy */ -} TWI_MASTER_BUSSTATE_t; - -/* Slave Interrupt Level */ -typedef enum TWI_SLAVE_INTLVL_enum -{ - TWI_SLAVE_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ - TWI_SLAVE_INTLVL_LO_gc = (0x01<<6), /* Low Level */ - TWI_SLAVE_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ - TWI_SLAVE_INTLVL_HI_gc = (0x03<<6), /* High Level */ -} TWI_SLAVE_INTLVL_t; - -/* Slave Command */ -typedef enum TWI_SLAVE_CMD_enum -{ - TWI_SLAVE_CMD_NOACT_gc = (0x00<<0), /* No Action */ - TWI_SLAVE_CMD_COMPTRANS_gc = (0x02<<0), /* Used To Complete a Transaction */ - TWI_SLAVE_CMD_RESPONSE_gc = (0x03<<0), /* Used in Response to Address/Data Interrupt */ -} TWI_SLAVE_CMD_t; - - -/* --------------------------------------------------------------------------- -PORT - Port Configuration --------------------------------------------------------------------------- -*/ - -/* I/O port Configuration */ -typedef struct PORTCFG_struct -{ - register8_t MPCMASK; /* Multi-pin Configuration Mask */ - register8_t reserved_0x01; - register8_t VPCTRLA; /* Virtual Port Control Register A */ - register8_t VPCTRLB; /* Virtual Port Control Register B */ - register8_t CLKEVOUT; /* Clock and Event Out Register */ -} PORTCFG_t; - -/* --------------------------------------------------------------------------- -PORT - Port Configuration --------------------------------------------------------------------------- -*/ - -/* Virtual Port */ -typedef struct VPORT_struct -{ - register8_t DIR; /* I/O Port Data Direction */ - register8_t OUT; /* I/O Port Output */ - register8_t IN; /* I/O Port Input */ - register8_t INTFLAGS; /* Interrupt Flag Register */ -} VPORT_t; - -/* --------------------------------------------------------------------------- -PORT - Port Configuration --------------------------------------------------------------------------- -*/ - -/* I/O Ports */ -typedef struct PORT_struct -{ - register8_t DIR; /* I/O Port Data Direction */ - register8_t DIRSET; /* I/O Port Data Direction Set */ - register8_t DIRCLR; /* I/O Port Data Direction Clear */ - register8_t DIRTGL; /* I/O Port Data Direction Toggle */ - register8_t OUT; /* I/O Port Output */ - register8_t OUTSET; /* I/O Port Output Set */ - register8_t OUTCLR; /* I/O Port Output Clear */ - register8_t OUTTGL; /* I/O Port Output Toggle */ - register8_t IN; /* I/O port Input */ - register8_t INTCTRL; /* Interrupt Control Register */ - register8_t INT0MASK; /* Port Interrupt 0 Mask */ - register8_t INT1MASK; /* Port Interrupt 1 Mask */ - register8_t INTFLAGS; /* Interrupt Flag Register */ - register8_t reserved_0x0D; - register8_t reserved_0x0E; - register8_t reserved_0x0F; - register8_t PIN0CTRL; /* Pin 0 Control Register */ - register8_t PIN1CTRL; /* Pin 1 Control Register */ - register8_t PIN2CTRL; /* Pin 2 Control Register */ - register8_t PIN3CTRL; /* Pin 3 Control Register */ - register8_t PIN4CTRL; /* Pin 4 Control Register */ - register8_t PIN5CTRL; /* Pin 5 Control Register */ - register8_t PIN6CTRL; /* Pin 6 Control Register */ - register8_t PIN7CTRL; /* Pin 7 Control Register */ -} PORT_t; - -/* Virtual Port 0 Mapping */ -typedef enum PORTCFG_VP0MAP_enum -{ - PORTCFG_VP0MAP_PORTA_gc = (0x00<<0), /* Mapped To PORTA */ - PORTCFG_VP0MAP_PORTB_gc = (0x01<<0), /* Mapped To PORTB */ - PORTCFG_VP0MAP_PORTC_gc = (0x02<<0), /* Mapped To PORTC */ - PORTCFG_VP0MAP_PORTD_gc = (0x03<<0), /* Mapped To PORTD */ - PORTCFG_VP0MAP_PORTE_gc = (0x04<<0), /* Mapped To PORTE */ - PORTCFG_VP0MAP_PORTF_gc = (0x05<<0), /* Mapped To PORTF */ - PORTCFG_VP0MAP_PORTG_gc = (0x06<<0), /* Mapped To PORTG */ - PORTCFG_VP0MAP_PORTH_gc = (0x07<<0), /* Mapped To PORTH */ - PORTCFG_VP0MAP_PORTJ_gc = (0x08<<0), /* Mapped To PORTJ */ - PORTCFG_VP0MAP_PORTK_gc = (0x09<<0), /* Mapped To PORTK */ - PORTCFG_VP0MAP_PORTL_gc = (0x0A<<0), /* Mapped To PORTL */ - PORTCFG_VP0MAP_PORTM_gc = (0x0B<<0), /* Mapped To PORTM */ - PORTCFG_VP0MAP_PORTN_gc = (0x0C<<0), /* Mapped To PORTN */ - PORTCFG_VP0MAP_PORTP_gc = (0x0D<<0), /* Mapped To PORTP */ - PORTCFG_VP0MAP_PORTQ_gc = (0x0E<<0), /* Mapped To PORTQ */ - PORTCFG_VP0MAP_PORTR_gc = (0x0F<<0), /* Mapped To PORTR */ -} PORTCFG_VP0MAP_t; - -/* Virtual Port 1 Mapping */ -typedef enum PORTCFG_VP1MAP_enum -{ - PORTCFG_VP1MAP_PORTA_gc = (0x00<<4), /* Mapped To PORTA */ - PORTCFG_VP1MAP_PORTB_gc = (0x01<<4), /* Mapped To PORTB */ - PORTCFG_VP1MAP_PORTC_gc = (0x02<<4), /* Mapped To PORTC */ - PORTCFG_VP1MAP_PORTD_gc = (0x03<<4), /* Mapped To PORTD */ - PORTCFG_VP1MAP_PORTE_gc = (0x04<<4), /* Mapped To PORTE */ - PORTCFG_VP1MAP_PORTF_gc = (0x05<<4), /* Mapped To PORTF */ - PORTCFG_VP1MAP_PORTG_gc = (0x06<<4), /* Mapped To PORTG */ - PORTCFG_VP1MAP_PORTH_gc = (0x07<<4), /* Mapped To PORTH */ - PORTCFG_VP1MAP_PORTJ_gc = (0x08<<4), /* Mapped To PORTJ */ - PORTCFG_VP1MAP_PORTK_gc = (0x09<<4), /* Mapped To PORTK */ - PORTCFG_VP1MAP_PORTL_gc = (0x0A<<4), /* Mapped To PORTL */ - PORTCFG_VP1MAP_PORTM_gc = (0x0B<<4), /* Mapped To PORTM */ - PORTCFG_VP1MAP_PORTN_gc = (0x0C<<4), /* Mapped To PORTN */ - PORTCFG_VP1MAP_PORTP_gc = (0x0D<<4), /* Mapped To PORTP */ - PORTCFG_VP1MAP_PORTQ_gc = (0x0E<<4), /* Mapped To PORTQ */ - PORTCFG_VP1MAP_PORTR_gc = (0x0F<<4), /* Mapped To PORTR */ -} PORTCFG_VP1MAP_t; - -/* Virtual Port 2 Mapping */ -typedef enum PORTCFG_VP2MAP_enum -{ - PORTCFG_VP2MAP_PORTA_gc = (0x00<<0), /* Mapped To PORTA */ - PORTCFG_VP2MAP_PORTB_gc = (0x01<<0), /* Mapped To PORTB */ - PORTCFG_VP2MAP_PORTC_gc = (0x02<<0), /* Mapped To PORTC */ - PORTCFG_VP2MAP_PORTD_gc = (0x03<<0), /* Mapped To PORTD */ - PORTCFG_VP2MAP_PORTE_gc = (0x04<<0), /* Mapped To PORTE */ - PORTCFG_VP2MAP_PORTF_gc = (0x05<<0), /* Mapped To PORTF */ - PORTCFG_VP2MAP_PORTG_gc = (0x06<<0), /* Mapped To PORTG */ - PORTCFG_VP2MAP_PORTH_gc = (0x07<<0), /* Mapped To PORTH */ - PORTCFG_VP2MAP_PORTJ_gc = (0x08<<0), /* Mapped To PORTJ */ - PORTCFG_VP2MAP_PORTK_gc = (0x09<<0), /* Mapped To PORTK */ - PORTCFG_VP2MAP_PORTL_gc = (0x0A<<0), /* Mapped To PORTL */ - PORTCFG_VP2MAP_PORTM_gc = (0x0B<<0), /* Mapped To PORTM */ - PORTCFG_VP2MAP_PORTN_gc = (0x0C<<0), /* Mapped To PORTN */ - PORTCFG_VP2MAP_PORTP_gc = (0x0D<<0), /* Mapped To PORTP */ - PORTCFG_VP2MAP_PORTQ_gc = (0x0E<<0), /* Mapped To PORTQ */ - PORTCFG_VP2MAP_PORTR_gc = (0x0F<<0), /* Mapped To PORTR */ -} PORTCFG_VP2MAP_t; - -/* Virtual Port 3 Mapping */ -typedef enum PORTCFG_VP3MAP_enum -{ - PORTCFG_VP3MAP_PORTA_gc = (0x00<<4), /* Mapped To PORTA */ - PORTCFG_VP3MAP_PORTB_gc = (0x01<<4), /* Mapped To PORTB */ - PORTCFG_VP3MAP_PORTC_gc = (0x02<<4), /* Mapped To PORTC */ - PORTCFG_VP3MAP_PORTD_gc = (0x03<<4), /* Mapped To PORTD */ - PORTCFG_VP3MAP_PORTE_gc = (0x04<<4), /* Mapped To PORTE */ - PORTCFG_VP3MAP_PORTF_gc = (0x05<<4), /* Mapped To PORTF */ - PORTCFG_VP3MAP_PORTG_gc = (0x06<<4), /* Mapped To PORTG */ - PORTCFG_VP3MAP_PORTH_gc = (0x07<<4), /* Mapped To PORTH */ - PORTCFG_VP3MAP_PORTJ_gc = (0x08<<4), /* Mapped To PORTJ */ - PORTCFG_VP3MAP_PORTK_gc = (0x09<<4), /* Mapped To PORTK */ - PORTCFG_VP3MAP_PORTL_gc = (0x0A<<4), /* Mapped To PORTL */ - PORTCFG_VP3MAP_PORTM_gc = (0x0B<<4), /* Mapped To PORTM */ - PORTCFG_VP3MAP_PORTN_gc = (0x0C<<4), /* Mapped To PORTN */ - PORTCFG_VP3MAP_PORTP_gc = (0x0D<<4), /* Mapped To PORTP */ - PORTCFG_VP3MAP_PORTQ_gc = (0x0E<<4), /* Mapped To PORTQ */ - PORTCFG_VP3MAP_PORTR_gc = (0x0F<<4), /* Mapped To PORTR */ -} PORTCFG_VP3MAP_t; - -/* Clock Output Port */ -typedef enum PORTCFG_CLKOUT_enum -{ - PORTCFG_CLKOUT_OFF_gc = (0x00<<0), /* Clock Output Disabled */ - PORTCFG_CLKOUT_PC7_gc = (0x01<<0), /* Clock Output on Port C pin 7 */ - PORTCFG_CLKOUT_PD7_gc = (0x02<<0), /* Clock Output on Port D pin 7 */ - PORTCFG_CLKOUT_PE7_gc = (0x03<<0), /* Clock Output on Port E pin 7 */ -} PORTCFG_CLKOUT_t; - -/* Event Output Port */ -typedef enum PORTCFG_EVOUT_enum -{ - PORTCFG_EVOUT_OFF_gc = (0x00<<4), /* Event Output Disabled */ - PORTCFG_EVOUT_PC7_gc = (0x01<<4), /* Event Channel 7 Output on Port C pin 7 */ - PORTCFG_EVOUT_PD7_gc = (0x02<<4), /* Event Channel 7 Output on Port D pin 7 */ - PORTCFG_EVOUT_PE7_gc = (0x03<<4), /* Event Channel 7 Output on Port E pin 7 */ -} PORTCFG_EVOUT_t; - -/* Port Interrupt 0 Level */ -typedef enum PORT_INT0LVL_enum -{ - PORT_INT0LVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - PORT_INT0LVL_LO_gc = (0x01<<0), /* Low Level */ - PORT_INT0LVL_MED_gc = (0x02<<0), /* Medium Level */ - PORT_INT0LVL_HI_gc = (0x03<<0), /* High Level */ -} PORT_INT0LVL_t; - -/* Port Interrupt 1 Level */ -typedef enum PORT_INT1LVL_enum -{ - PORT_INT1LVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ - PORT_INT1LVL_LO_gc = (0x01<<2), /* Low Level */ - PORT_INT1LVL_MED_gc = (0x02<<2), /* Medium Level */ - PORT_INT1LVL_HI_gc = (0x03<<2), /* High Level */ -} PORT_INT1LVL_t; - -/* Output/Pull Configuration */ -typedef enum PORT_OPC_enum -{ - PORT_OPC_TOTEM_gc = (0x00<<3), /* Totempole */ - PORT_OPC_BUSKEEPER_gc = (0x01<<3), /* Totempole w/ Bus keeper on Input and Output */ - PORT_OPC_PULLDOWN_gc = (0x02<<3), /* Totempole w/ Pull-down on Input */ - PORT_OPC_PULLUP_gc = (0x03<<3), /* Totempole w/ Pull-up on Input */ - PORT_OPC_WIREDOR_gc = (0x04<<3), /* Wired OR */ - PORT_OPC_WIREDAND_gc = (0x05<<3), /* Wired AND */ - PORT_OPC_WIREDORPULL_gc = (0x06<<3), /* Wired OR w/ Pull-down */ - PORT_OPC_WIREDANDPULL_gc = (0x07<<3), /* Wired AND w/ Pull-up */ -} PORT_OPC_t; - -/* Input/Sense Configuration */ -typedef enum PORT_ISC_enum -{ - PORT_ISC_BOTHEDGES_gc = (0x00<<0), /* Sense Both Edges */ - PORT_ISC_RISING_gc = (0x01<<0), /* Sense Rising Edge */ - PORT_ISC_FALLING_gc = (0x02<<0), /* Sense Falling Edge */ - PORT_ISC_LEVEL_gc = (0x03<<0), /* Sense Level (Transparent For Events) */ - PORT_ISC_INPUT_DISABLE_gc = (0x07<<0), /* Disable Digital Input Buffer */ -} PORT_ISC_t; - - -/* --------------------------------------------------------------------------- -TC - 16-bit Timer/Counter With PWM --------------------------------------------------------------------------- -*/ - -/* 16-bit Timer/Counter 0 */ -typedef struct TC0_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t CTRLC; /* Control register C */ - register8_t CTRLD; /* Control Register D */ - register8_t CTRLE; /* Control Register E */ - register8_t reserved_0x05; - register8_t INTCTRLA; /* Interrupt Control Register A */ - register8_t INTCTRLB; /* Interrupt Control Register B */ - register8_t CTRLFCLR; /* Control Register F Clear */ - register8_t CTRLFSET; /* Control Register F Set */ - register8_t CTRLGCLR; /* Control Register G Clear */ - register8_t CTRLGSET; /* Control Register G Set */ - register8_t INTFLAGS; /* Interrupt Flag Register */ - register8_t reserved_0x0D; - register8_t reserved_0x0E; - register8_t TEMP; /* Temporary Register For 16-bit Access */ - register8_t reserved_0x10; - register8_t reserved_0x11; - register8_t reserved_0x12; - register8_t reserved_0x13; - register8_t reserved_0x14; - register8_t reserved_0x15; - register8_t reserved_0x16; - register8_t reserved_0x17; - register8_t reserved_0x18; - register8_t reserved_0x19; - register8_t reserved_0x1A; - register8_t reserved_0x1B; - register8_t reserved_0x1C; - register8_t reserved_0x1D; - register8_t reserved_0x1E; - register8_t reserved_0x1F; - _WORDREGISTER(CNT); /* Count */ - register8_t reserved_0x22; - register8_t reserved_0x23; - register8_t reserved_0x24; - register8_t reserved_0x25; - _WORDREGISTER(PER); /* Period */ - _WORDREGISTER(CCA); /* Compare or Capture A */ - _WORDREGISTER(CCB); /* Compare or Capture B */ - _WORDREGISTER(CCC); /* Compare or Capture C */ - _WORDREGISTER(CCD); /* Compare or Capture D */ - register8_t reserved_0x30; - register8_t reserved_0x31; - register8_t reserved_0x32; - register8_t reserved_0x33; - register8_t reserved_0x34; - register8_t reserved_0x35; - _WORDREGISTER(PERBUF); /* Period Buffer */ - _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ - _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ - _WORDREGISTER(CCCBUF); /* Compare Or Capture C Buffer */ - _WORDREGISTER(CCDBUF); /* Compare Or Capture D Buffer */ -} TC0_t; - -/* --------------------------------------------------------------------------- -TC - 16-bit Timer/Counter With PWM --------------------------------------------------------------------------- -*/ - -/* 16-bit Timer/Counter 1 */ -typedef struct TC1_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t CTRLC; /* Control register C */ - register8_t CTRLD; /* Control Register D */ - register8_t CTRLE; /* Control Register E */ - register8_t reserved_0x05; - register8_t INTCTRLA; /* Interrupt Control Register A */ - register8_t INTCTRLB; /* Interrupt Control Register B */ - register8_t CTRLFCLR; /* Control Register F Clear */ - register8_t CTRLFSET; /* Control Register F Set */ - register8_t CTRLGCLR; /* Control Register G Clear */ - register8_t CTRLGSET; /* Control Register G Set */ - register8_t INTFLAGS; /* Interrupt Flag Register */ - register8_t reserved_0x0D; - register8_t reserved_0x0E; - register8_t TEMP; /* Temporary Register For 16-bit Access */ - register8_t reserved_0x10; - register8_t reserved_0x11; - register8_t reserved_0x12; - register8_t reserved_0x13; - register8_t reserved_0x14; - register8_t reserved_0x15; - register8_t reserved_0x16; - register8_t reserved_0x17; - register8_t reserved_0x18; - register8_t reserved_0x19; - register8_t reserved_0x1A; - register8_t reserved_0x1B; - register8_t reserved_0x1C; - register8_t reserved_0x1D; - register8_t reserved_0x1E; - register8_t reserved_0x1F; - _WORDREGISTER(CNT); /* Count */ - register8_t reserved_0x22; - register8_t reserved_0x23; - register8_t reserved_0x24; - register8_t reserved_0x25; - _WORDREGISTER(PER); /* Period */ - _WORDREGISTER(CCA); /* Compare or Capture A */ - _WORDREGISTER(CCB); /* Compare or Capture B */ - register8_t reserved_0x2C; - register8_t reserved_0x2D; - register8_t reserved_0x2E; - register8_t reserved_0x2F; - register8_t reserved_0x30; - register8_t reserved_0x31; - register8_t reserved_0x32; - register8_t reserved_0x33; - register8_t reserved_0x34; - register8_t reserved_0x35; - _WORDREGISTER(PERBUF); /* Period Buffer */ - _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ - _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ -} TC1_t; - -/* --------------------------------------------------------------------------- -TC - 16-bit Timer/Counter With PWM --------------------------------------------------------------------------- -*/ - -/* Advanced Waveform Extension */ -typedef struct AWEX_struct -{ - register8_t CTRL; /* Control Register */ - register8_t reserved_0x01; - register8_t FDEMASK; /* Fault Detection Event Mask */ - register8_t FDCTRL; /* Fault Detection Control Register */ - register8_t STATUS; /* Status Register */ - register8_t reserved_0x05; - register8_t DTBOTH; /* Dead Time Both Sides */ - register8_t DTBOTHBUF; /* Dead Time Both Sides Buffer */ - register8_t DTLS; /* Dead Time Low Side */ - register8_t DTHS; /* Dead Time High Side */ - register8_t DTLSBUF; /* Dead Time Low Side Buffer */ - register8_t DTHSBUF; /* Dead Time High Side Buffer */ - register8_t OUTOVEN; /* Output Override Enable */ -} AWEX_t; - -/* --------------------------------------------------------------------------- -TC - 16-bit Timer/Counter With PWM --------------------------------------------------------------------------- -*/ - -/* High-Resolution Extension */ -typedef struct HIRES_struct -{ - register8_t CTRLA; /* Control Register */ -} HIRES_t; - -/* Clock Selection */ -typedef enum TC_CLKSEL_enum -{ - TC_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */ - TC_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */ - TC_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */ - TC_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */ - TC_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */ - TC_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */ - TC_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */ - TC_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */ - TC_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */ - TC_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */ - TC_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */ - TC_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */ - TC_CLKSEL_EVCH4_gc = (0x0C<<0), /* Event Channel 4 */ - TC_CLKSEL_EVCH5_gc = (0x0D<<0), /* Event Channel 5 */ - TC_CLKSEL_EVCH6_gc = (0x0E<<0), /* Event Channel 6 */ - TC_CLKSEL_EVCH7_gc = (0x0F<<0), /* Event Channel 7 */ -} TC_CLKSEL_t; - -/* Waveform Generation Mode */ -typedef enum TC_WGMODE_enum -{ - TC_WGMODE_NORMAL_gc = (0x00<<0), /* Normal Mode */ - TC_WGMODE_FRQ_gc = (0x01<<0), /* Frequency Generation Mode */ - TC_WGMODE_SS_gc = (0x03<<0), /* Single Slope */ - TC_WGMODE_DS_T_gc = (0x05<<0), /* Dual Slope, Update on TOP */ - TC_WGMODE_DS_TB_gc = (0x06<<0), /* Dual Slope, Update on TOP and BOTTOM */ - TC_WGMODE_DS_B_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */ -} TC_WGMODE_t; - -/* Event Action */ -typedef enum TC_EVACT_enum -{ - TC_EVACT_OFF_gc = (0x00<<5), /* No Event Action */ - TC_EVACT_CAPT_gc = (0x01<<5), /* Input Capture */ - TC_EVACT_UPDOWN_gc = (0x02<<5), /* Externally Controlled Up/Down Count */ - TC_EVACT_QDEC_gc = (0x03<<5), /* Quadrature Decode */ - TC_EVACT_RESTART_gc = (0x04<<5), /* Restart */ - TC_EVACT_FRQ_gc = (0x05<<5), /* Frequency Capture */ - TC_EVACT_PW_gc = (0x06<<5), /* Pulse-width Capture */ -} TC_EVACT_t; - -/* Event Selection */ -typedef enum TC_EVSEL_enum -{ - TC_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ - TC_EVSEL_CH0_gc = (0x08<<0), /* Event Channel 0 */ - TC_EVSEL_CH1_gc = (0x09<<0), /* Event Channel 1 */ - TC_EVSEL_CH2_gc = (0x0A<<0), /* Event Channel 2 */ - TC_EVSEL_CH3_gc = (0x0B<<0), /* Event Channel 3 */ - TC_EVSEL_CH4_gc = (0x0C<<0), /* Event Channel 4 */ - TC_EVSEL_CH5_gc = (0x0D<<0), /* Event Channel 5 */ - TC_EVSEL_CH6_gc = (0x0E<<0), /* Event Channel 6 */ - TC_EVSEL_CH7_gc = (0x0F<<0), /* Event Channel 7 */ -} TC_EVSEL_t; - -/* Error Interrupt Level */ -typedef enum TC_ERRINTLVL_enum -{ - TC_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ - TC_ERRINTLVL_LO_gc = (0x01<<2), /* Low Level */ - TC_ERRINTLVL_MED_gc = (0x02<<2), /* Medium Level */ - TC_ERRINTLVL_HI_gc = (0x03<<2), /* High Level */ -} TC_ERRINTLVL_t; - -/* Overflow Interrupt Level */ -typedef enum TC_OVFINTLVL_enum -{ - TC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - TC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ - TC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ - TC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ -} TC_OVFINTLVL_t; - -/* Compare or Capture D Interrupt Level */ -typedef enum TC_CCDINTLVL_enum -{ - TC_CCDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ - TC_CCDINTLVL_LO_gc = (0x01<<6), /* Low Level */ - TC_CCDINTLVL_MED_gc = (0x02<<6), /* Medium Level */ - TC_CCDINTLVL_HI_gc = (0x03<<6), /* High Level */ -} TC_CCDINTLVL_t; - -/* Compare or Capture C Interrupt Level */ -typedef enum TC_CCCINTLVL_enum -{ - TC_CCCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ - TC_CCCINTLVL_LO_gc = (0x01<<4), /* Low Level */ - TC_CCCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ - TC_CCCINTLVL_HI_gc = (0x03<<4), /* High Level */ -} TC_CCCINTLVL_t; - -/* Compare or Capture B Interrupt Level */ -typedef enum TC_CCBINTLVL_enum -{ - TC_CCBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ - TC_CCBINTLVL_LO_gc = (0x01<<2), /* Low Level */ - TC_CCBINTLVL_MED_gc = (0x02<<2), /* Medium Level */ - TC_CCBINTLVL_HI_gc = (0x03<<2), /* High Level */ -} TC_CCBINTLVL_t; - -/* Compare or Capture A Interrupt Level */ -typedef enum TC_CCAINTLVL_enum -{ - TC_CCAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - TC_CCAINTLVL_LO_gc = (0x01<<0), /* Low Level */ - TC_CCAINTLVL_MED_gc = (0x02<<0), /* Medium Level */ - TC_CCAINTLVL_HI_gc = (0x03<<0), /* High Level */ -} TC_CCAINTLVL_t; - -/* Timer/Counter Command */ -typedef enum TC_CMD_enum -{ - TC_CMD_NONE_gc = (0x00<<2), /* No Command */ - TC_CMD_UPDATE_gc = (0x01<<2), /* Force Update */ - TC_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ - TC_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ -} TC_CMD_t; - -/* Fault Detect Action */ -typedef enum AWEX_FDACT_enum -{ - AWEX_FDACT_NONE_gc = (0x00<<0), /* No Fault Protection */ - AWEX_FDACT_CLEAROE_gc = (0x01<<0), /* Clear Output Enable Bits */ - AWEX_FDACT_CLEARDIR_gc = (0x03<<0), /* Clear I/O Port Direction Bits */ -} AWEX_FDACT_t; - -/* High Resolution Enable */ -typedef enum HIRES_HREN_enum -{ - HIRES_HREN_NONE_gc = (0x00<<0), /* No Fault Protection */ - HIRES_HREN_TC0_gc = (0x01<<0), /* Enable High Resolution on Timer/Counter 0 */ - HIRES_HREN_TC1_gc = (0x02<<0), /* Enable High Resolution on Timer/Counter 1 */ - HIRES_HREN_BOTH_gc = (0x03<<0), /* Enable High Resolution both Timer/Counters */ -} HIRES_HREN_t; - - -/* --------------------------------------------------------------------------- -USART - Universal Asynchronous Receiver-Transmitter --------------------------------------------------------------------------- -*/ - -/* Universal Synchronous/Asynchronous Receiver/Transmitter */ -typedef struct USART_struct -{ - register8_t DATA; /* Data Register */ - register8_t STATUS; /* Status Register */ - register8_t reserved_0x02; - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t CTRLC; /* Control Register C */ - register8_t BAUDCTRLA; /* Baud Rate Control Register A */ - register8_t BAUDCTRLB; /* Baud Rate Control Register B */ -} USART_t; - -/* Receive Complete Interrupt level */ -typedef enum USART_RXCINTLVL_enum -{ - USART_RXCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ - USART_RXCINTLVL_LO_gc = (0x01<<4), /* Low Level */ - USART_RXCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ - USART_RXCINTLVL_HI_gc = (0x03<<4), /* High Level */ -} USART_RXCINTLVL_t; - -/* Transmit Complete Interrupt level */ -typedef enum USART_TXCINTLVL_enum -{ - USART_TXCINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ - USART_TXCINTLVL_LO_gc = (0x01<<2), /* Low Level */ - USART_TXCINTLVL_MED_gc = (0x02<<2), /* Medium Level */ - USART_TXCINTLVL_HI_gc = (0x03<<2), /* High Level */ -} USART_TXCINTLVL_t; - -/* Data Register Empty Interrupt level */ -typedef enum USART_DREINTLVL_enum -{ - USART_DREINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - USART_DREINTLVL_LO_gc = (0x01<<0), /* Low Level */ - USART_DREINTLVL_MED_gc = (0x02<<0), /* Medium Level */ - USART_DREINTLVL_HI_gc = (0x03<<0), /* High Level */ -} USART_DREINTLVL_t; - -/* Character Size */ -typedef enum USART_CHSIZE_enum -{ - USART_CHSIZE_5BIT_gc = (0x00<<0), /* Character size: 5 bit */ - USART_CHSIZE_6BIT_gc = (0x01<<0), /* Character size: 6 bit */ - USART_CHSIZE_7BIT_gc = (0x02<<0), /* Character size: 7 bit */ - USART_CHSIZE_8BIT_gc = (0x03<<0), /* Character size: 8 bit */ - USART_CHSIZE_9BIT_gc = (0x07<<0), /* Character size: 9 bit */ -} USART_CHSIZE_t; - -/* Communication Mode */ -typedef enum USART_CMODE_enum -{ - USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6), /* Asynchronous Mode */ - USART_CMODE_SYNCHRONOUS_gc = (0x01<<6), /* Synchronous Mode */ - USART_CMODE_IRDA_gc = (0x02<<6), /* IrDA Mode */ - USART_CMODE_MSPI_gc = (0x03<<6), /* Master SPI Mode */ -} USART_CMODE_t; - -/* Parity Mode */ -typedef enum USART_PMODE_enum -{ - USART_PMODE_DISABLED_gc = (0x00<<4), /* No Parity */ - USART_PMODE_EVEN_gc = (0x02<<4), /* Even Parity */ - USART_PMODE_ODD_gc = (0x03<<4), /* Odd Parity */ -} USART_PMODE_t; - - -/* --------------------------------------------------------------------------- -SPI - Serial Peripheral Interface --------------------------------------------------------------------------- -*/ - -/* Serial Peripheral Interface */ -typedef struct SPI_struct -{ - register8_t CTRL; /* Control Register */ - register8_t INTCTRL; /* Interrupt Control Register */ - register8_t STATUS; /* Status Register */ - register8_t DATA; /* Data Register */ -} SPI_t; - -/* SPI Mode */ -typedef enum SPI_MODE_enum -{ - SPI_MODE_0_gc = (0x00<<2), /* SPI Mode 0 */ - SPI_MODE_1_gc = (0x01<<2), /* SPI Mode 1 */ - SPI_MODE_2_gc = (0x02<<2), /* SPI Mode 2 */ - SPI_MODE_3_gc = (0x03<<2), /* SPI Mode 3 */ -} SPI_MODE_t; - -/* Prescaler setting */ -typedef enum SPI_PRESCALER_enum -{ - SPI_PRESCALER_DIV4_gc = (0x00<<0), /* System Clock / 4 */ - SPI_PRESCALER_DIV16_gc = (0x01<<0), /* System Clock / 16 */ - SPI_PRESCALER_DIV64_gc = (0x02<<0), /* System Clock / 64 */ - SPI_PRESCALER_DIV128_gc = (0x03<<0), /* System Clock / 128 */ -} SPI_PRESCALER_t; - -/* Interrupt level */ -typedef enum SPI_INTLVL_enum -{ - SPI_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - SPI_INTLVL_LO_gc = (0x01<<0), /* Low Level */ - SPI_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ - SPI_INTLVL_HI_gc = (0x03<<0), /* High Level */ -} SPI_INTLVL_t; - - -/* --------------------------------------------------------------------------- -IRCOM - IR Communication Module --------------------------------------------------------------------------- -*/ - -/* IR Communication Module */ -typedef struct IRCOM_struct -{ - register8_t CTRL; /* Control Register */ - register8_t TXPLCTRL; /* IrDA Transmitter Pulse Length Control Register */ - register8_t RXPLCTRL; /* IrDA Receiver Pulse Length Control Register */ -} IRCOM_t; - -/* Event channel selection */ -typedef enum IRDA_EVSEL_enum -{ - IRDA_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ - IRDA_EVSEL_0_gc = (0x08<<0), /* Event Channel 0 */ - IRDA_EVSEL_1_gc = (0x09<<0), /* Event Channel 1 */ - IRDA_EVSEL_2_gc = (0x0A<<0), /* Event Channel 2 */ - IRDA_EVSEL_3_gc = (0x0B<<0), /* Event Channel 3 */ - IRDA_EVSEL_4_gc = (0x0C<<0), /* Event Channel 4 */ - IRDA_EVSEL_5_gc = (0x0D<<0), /* Event Channel 5 */ - IRDA_EVSEL_6_gc = (0x0E<<0), /* Event Channel 6 */ - IRDA_EVSEL_7_gc = (0x0F<<0), /* Event Channel 7 */ -} IRDA_EVSEL_t; - - - -/* -========================================================================== -IO Module Instances. Mapped to memory. -========================================================================== -*/ - -#define VPORT0 (*(VPORT_t *) 0x0010) /* Virtual Port 0 */ -#define VPORT1 (*(VPORT_t *) 0x0014) /* Virtual Port 1 */ -#define VPORT2 (*(VPORT_t *) 0x0018) /* Virtual Port 2 */ -#define VPORT3 (*(VPORT_t *) 0x001C) /* Virtual Port 3 */ -#define OCD (*(OCD_t *) 0x002E) /* On-Chip Debug System */ -#define CLK (*(CLK_t *) 0x0040) /* Clock System */ -#define SLEEP (*(SLEEP_t *) 0x0048) /* Sleep Controller */ -#define OSC (*(OSC_t *) 0x0050) /* Oscillator Control */ -#define DFLLRC32M (*(DFLL_t *) 0x0060) /* DFLL for 32MHz RC Oscillator */ -#define DFLLRC2M (*(DFLL_t *) 0x0068) /* DFLL for 2MHz RC Oscillator */ -#define RST (*(RST_t *) 0x0078) /* Reset Controller */ -#define WDT (*(WDT_t *) 0x0080) /* Watch-Dog Timer */ -#define MCU (*(MCU_t *) 0x0090) /* MCU Control */ -#define PMIC (*(PMIC_t *) 0x00A0) /* Programmable Interrupt Controller */ -#define PORTCFG (*(PORTCFG_t *) 0x00B0) /* Port Configuration */ -#define CRC (*(CRC_t *) 0x00D0) /* Cyclic Redundancy Checker */ -#define EVSYS (*(EVSYS_t *) 0x0180) /* Event System */ -#define NVM (*(NVM_t *) 0x01C0) /* Non Volatile Memory Controller */ -#define ADCA (*(ADC_t *) 0x0200) /* Analog to Digital Converter A */ -#define ACA (*(AC_t *) 0x0380) /* Analog Comparator A */ -#define RTC (*(RTC_t *) 0x0400) /* Real-Time Counter */ -#define TWIC (*(TWI_t *) 0x0480) /* Two-Wire Interface C */ -#define TWIE (*(TWI_t *) 0x04A0) /* Two-Wire Interface E */ -#define PORTA (*(PORT_t *) 0x0600) /* Port A */ -#define PORTB (*(PORT_t *) 0x0620) /* Port B */ -#define PORTC (*(PORT_t *) 0x0640) /* Port C */ -#define PORTD (*(PORT_t *) 0x0660) /* Port D */ -#define PORTE (*(PORT_t *) 0x0680) /* Port E */ -#define PORTF (*(PORT_t *) 0x06A0) /* Port F */ -#define PORTR (*(PORT_t *) 0x07E0) /* Port R */ -#define TCC0 (*(TC0_t *) 0x0800) /* Timer/Counter C0 */ -#define TCC1 (*(TC1_t *) 0x0840) /* Timer/Counter C1 */ -#define AWEXC (*(AWEX_t *) 0x0880) /* Advanced Waveform Extension C */ -#define HIRESC (*(HIRES_t *) 0x0890) /* High-Resolution Extension C */ -#define USARTC0 (*(USART_t *) 0x08A0) /* Universal Asynchronous Receiver-Transmitter C0 */ -#define SPIC (*(SPI_t *) 0x08C0) /* Serial Peripheral Interface C */ -#define IRCOM (*(IRCOM_t *) 0x08F8) /* IR Communication Module */ -#define TCD0 (*(TC0_t *) 0x0900) /* Timer/Counter D0 */ -#define USARTD0 (*(USART_t *) 0x09A0) /* Universal Asynchronous Receiver-Transmitter D0 */ -#define SPID (*(SPI_t *) 0x09C0) /* Serial Peripheral Interface D */ -#define TCE0 (*(TC0_t *) 0x0A00) /* Timer/Counter E0 */ -#define AWEXE (*(AWEX_t *) 0x0A80) /* Advanced Waveform Extension E */ -#define USARTE0 (*(USART_t *) 0x0AA0) /* Universal Asynchronous Receiver-Transmitter E0 */ -#define SPIE (*(SPI_t *) 0x0AC0) /* Serial Peripheral Interface E */ -#define TCF0 (*(TC0_t *) 0x0B00) /* Timer/Counter F0 */ - - -#endif /* !defined (__ASSEMBLER__) */ - - -/* ========== Flattened fully qualified IO register names ========== */ - -/* GPIO - General Purpose IO Registers */ -#define GPIO_GPIOR0 _SFR_MEM8(0x0000) -#define GPIO_GPIOR1 _SFR_MEM8(0x0001) -#define GPIO_GPIOR2 _SFR_MEM8(0x0002) -#define GPIO_GPIOR3 _SFR_MEM8(0x0003) -#define GPIO_GPIOR4 _SFR_MEM8(0x0004) -#define GPIO_GPIOR5 _SFR_MEM8(0x0005) -#define GPIO_GPIOR6 _SFR_MEM8(0x0006) -#define GPIO_GPIOR7 _SFR_MEM8(0x0007) -#define GPIO_GPIOR8 _SFR_MEM8(0x0008) -#define GPIO_GPIOR9 _SFR_MEM8(0x0009) -#define GPIO_GPIORA _SFR_MEM8(0x000A) -#define GPIO_GPIORB _SFR_MEM8(0x000B) -#define GPIO_GPIORC _SFR_MEM8(0x000C) -#define GPIO_GPIORD _SFR_MEM8(0x000D) -#define GPIO_GPIORE _SFR_MEM8(0x000E) -#define GPIO_GPIORF _SFR_MEM8(0x000F) - -/* VPORT0 - Virtual Port 0 */ -#define VPORT0_DIR _SFR_MEM8(0x0010) -#define VPORT0_OUT _SFR_MEM8(0x0011) -#define VPORT0_IN _SFR_MEM8(0x0012) -#define VPORT0_INTFLAGS _SFR_MEM8(0x0013) - -/* VPORT1 - Virtual Port 1 */ -#define VPORT1_DIR _SFR_MEM8(0x0014) -#define VPORT1_OUT _SFR_MEM8(0x0015) -#define VPORT1_IN _SFR_MEM8(0x0016) -#define VPORT1_INTFLAGS _SFR_MEM8(0x0017) - -/* VPORT2 - Virtual Port 2 */ -#define VPORT2_DIR _SFR_MEM8(0x0018) -#define VPORT2_OUT _SFR_MEM8(0x0019) -#define VPORT2_IN _SFR_MEM8(0x001A) -#define VPORT2_INTFLAGS _SFR_MEM8(0x001B) - -/* VPORT3 - Virtual Port 3 */ -#define VPORT3_DIR _SFR_MEM8(0x001C) -#define VPORT3_OUT _SFR_MEM8(0x001D) -#define VPORT3_IN _SFR_MEM8(0x001E) -#define VPORT3_INTFLAGS _SFR_MEM8(0x001F) - -/* OCD - On-Chip Debug System */ -#define OCD_OCDR0 _SFR_MEM8(0x002E) -#define OCD_OCDR1 _SFR_MEM8(0x002F) - -/* CPU - CPU Registers */ -#define CPU_CCP _SFR_MEM8(0x0034) -#define CPU_RAMPD _SFR_MEM8(0x0038) -#define CPU_RAMPX _SFR_MEM8(0x0039) -#define CPU_RAMPY _SFR_MEM8(0x003A) -#define CPU_RAMPZ _SFR_MEM8(0x003B) -#define CPU_EIND _SFR_MEM8(0x003C) -#define CPU_SPL _SFR_MEM8(0x003D) -#define CPU_SPH _SFR_MEM8(0x003E) -#define CPU_SREG _SFR_MEM8(0x003F) - -/* CLK - Clock System */ -#define CLK_CTRL _SFR_MEM8(0x0040) -#define CLK_PSCTRL _SFR_MEM8(0x0041) -#define CLK_LOCK _SFR_MEM8(0x0042) -#define CLK_RTCCTRL _SFR_MEM8(0x0043) - -/* SLEEP - Sleep Controller */ -#define SLEEP_CTRL _SFR_MEM8(0x0048) - -/* OSC - Oscillator Control */ -#define OSC_CTRL _SFR_MEM8(0x0050) -#define OSC_STATUS _SFR_MEM8(0x0051) -#define OSC_XOSCCTRL _SFR_MEM8(0x0052) -#define OSC_XOSCFAIL _SFR_MEM8(0x0053) -#define OSC_RC32KCAL _SFR_MEM8(0x0054) -#define OSC_PLLCTRL _SFR_MEM8(0x0055) -#define OSC_DFLLCTRL _SFR_MEM8(0x0056) - -/* DFLLRC32M - DFLL for 32MHz RC Oscillator */ -#define DFLLRC32M_CTRL _SFR_MEM8(0x0060) -#define DFLLRC32M_CALA _SFR_MEM8(0x0062) -#define DFLLRC32M_CALB _SFR_MEM8(0x0063) -#define DFLLRC32M_COMP0 _SFR_MEM8(0x0064) -#define DFLLRC32M_COMP1 _SFR_MEM8(0x0065) -#define DFLLRC32M_COMP2 _SFR_MEM8(0x0066) - -/* DFLLRC2M - DFLL for 2MHz RC Oscillator */ -#define DFLLRC2M_CTRL _SFR_MEM8(0x0068) -#define DFLLRC2M_CALA _SFR_MEM8(0x006A) -#define DFLLRC2M_CALB _SFR_MEM8(0x006B) -#define DFLLRC2M_COMP0 _SFR_MEM8(0x006C) -#define DFLLRC2M_COMP1 _SFR_MEM8(0x006D) -#define DFLLRC2M_COMP2 _SFR_MEM8(0x006E) - -/* PR - Power Reduction */ -#define PR_PRGEN _SFR_MEM8(0x0070) -#define PR_PRPA _SFR_MEM8(0x0071) -#define PR_PRPC _SFR_MEM8(0x0073) -#define PR_PRPD _SFR_MEM8(0x0074) -#define PR_PRPE _SFR_MEM8(0x0075) -#define PR_PRPF _SFR_MEM8(0x0076) - -/* RST - Reset Controller */ -#define RST_STATUS _SFR_MEM8(0x0078) -#define RST_CTRL _SFR_MEM8(0x0079) - -/* WDT - Watch-Dog Timer */ -#define WDT_CTRL _SFR_MEM8(0x0080) -#define WDT_WINCTRL _SFR_MEM8(0x0081) -#define WDT_STATUS _SFR_MEM8(0x0082) - -/* MCU - MCU Control */ -#define MCU_DEVID0 _SFR_MEM8(0x0090) -#define MCU_DEVID1 _SFR_MEM8(0x0091) -#define MCU_DEVID2 _SFR_MEM8(0x0092) -#define MCU_REVID _SFR_MEM8(0x0093) -#define MCU_JTAGUID _SFR_MEM8(0x0094) -#define MCU_MCUCR _SFR_MEM8(0x0096) -#define MCU_EVSYSLOCK _SFR_MEM8(0x0098) -#define MCU_AWEXLOCK _SFR_MEM8(0x0099) - -/* PMIC - Programmable Interrupt Controller */ -#define PMIC_STATUS _SFR_MEM8(0x00A0) -#define PMIC_INTPRI _SFR_MEM8(0x00A1) -#define PMIC_CTRL _SFR_MEM8(0x00A2) - -/* PORTCFG - Port Configuration */ -#define PORTCFG_MPCMASK _SFR_MEM8(0x00B0) -#define PORTCFG_VPCTRLA _SFR_MEM8(0x00B2) -#define PORTCFG_VPCTRLB _SFR_MEM8(0x00B3) -#define PORTCFG_CLKEVOUT _SFR_MEM8(0x00B4) - -/* CRC - Cyclic Redundancy Checker */ -#define CRC_CTRL _SFR_MEM8(0x00D0) -#define CRC_STATUS _SFR_MEM8(0x00D1) -#define CRC_DATAIN _SFR_MEM8(0x00D3) -#define CRC_CHECKSUM0 _SFR_MEM8(0x00D4) -#define CRC_CHECKSUM1 _SFR_MEM8(0x00D5) -#define CRC_CHECKSUM2 _SFR_MEM8(0x00D6) -#define CRC_CHECKSUM3 _SFR_MEM8(0x00D7) - -/* EVSYS - Event System */ -#define EVSYS_CH0MUX _SFR_MEM8(0x0180) -#define EVSYS_CH1MUX _SFR_MEM8(0x0181) -#define EVSYS_CH2MUX _SFR_MEM8(0x0182) -#define EVSYS_CH3MUX _SFR_MEM8(0x0183) -#define EVSYS_CH0CTRL _SFR_MEM8(0x0188) -#define EVSYS_CH1CTRL _SFR_MEM8(0x0189) -#define EVSYS_CH2CTRL _SFR_MEM8(0x018A) -#define EVSYS_CH3CTRL _SFR_MEM8(0x018B) -#define EVSYS_STROBE _SFR_MEM8(0x0190) -#define EVSYS_DATA _SFR_MEM8(0x0191) - -/* NVM - Non Volatile Memory Controller */ -#define NVM_ADDR0 _SFR_MEM8(0x01C0) -#define NVM_ADDR1 _SFR_MEM8(0x01C1) -#define NVM_ADDR2 _SFR_MEM8(0x01C2) -#define NVM_DATA0 _SFR_MEM8(0x01C4) -#define NVM_DATA1 _SFR_MEM8(0x01C5) -#define NVM_DATA2 _SFR_MEM8(0x01C6) -#define NVM_CMD _SFR_MEM8(0x01CA) -#define NVM_CTRLA _SFR_MEM8(0x01CB) -#define NVM_CTRLB _SFR_MEM8(0x01CC) -#define NVM_INTCTRL _SFR_MEM8(0x01CD) -#define NVM_STATUS _SFR_MEM8(0x01CF) -#define NVM_LOCKBITS _SFR_MEM8(0x01D0) - -/* ADCA - Analog to Digital Converter A */ -#define ADCA_CTRLA _SFR_MEM8(0x0200) -#define ADCA_CTRLB _SFR_MEM8(0x0201) -#define ADCA_REFCTRL _SFR_MEM8(0x0202) -#define ADCA_EVCTRL _SFR_MEM8(0x0203) -#define ADCA_PRESCALER _SFR_MEM8(0x0204) -#define ADCA_INTFLAGS _SFR_MEM8(0x0206) -#define ADCA_TEMP _SFR_MEM8(0x0207) -#define ADCA_CAL _SFR_MEM16(0x020C) -#define ADCA_CH0RES _SFR_MEM16(0x0210) -#define ADCA_CMP _SFR_MEM16(0x0218) -#define ADCA_CH0_CTRL _SFR_MEM8(0x0220) -#define ADCA_CH0_MUXCTRL _SFR_MEM8(0x0221) -#define ADCA_CH0_INTCTRL _SFR_MEM8(0x0222) -#define ADCA_CH0_INTFLAGS _SFR_MEM8(0x0223) -#define ADCA_CH0_RES _SFR_MEM16(0x0224) - -/* ACA - Analog Comparator A */ -#define ACA_AC0CTRL _SFR_MEM8(0x0380) -#define ACA_AC1CTRL _SFR_MEM8(0x0381) -#define ACA_AC0MUXCTRL _SFR_MEM8(0x0382) -#define ACA_AC1MUXCTRL _SFR_MEM8(0x0383) -#define ACA_CTRLA _SFR_MEM8(0x0384) -#define ACA_CTRLB _SFR_MEM8(0x0385) -#define ACA_WINCTRL _SFR_MEM8(0x0386) -#define ACA_STATUS _SFR_MEM8(0x0387) - -/* RTC - Real-Time Counter */ -#define RTC_CTRL _SFR_MEM8(0x0400) -#define RTC_STATUS _SFR_MEM8(0x0401) -#define RTC_INTCTRL _SFR_MEM8(0x0402) -#define RTC_INTFLAGS _SFR_MEM8(0x0403) -#define RTC_TEMP _SFR_MEM8(0x0404) -#define RTC_CNT _SFR_MEM16(0x0408) -#define RTC_PER _SFR_MEM16(0x040A) -#define RTC_COMP _SFR_MEM16(0x040C) - -/* TWIC - Two-Wire Interface C */ -#define TWIC_CTRL _SFR_MEM8(0x0480) -#define TWIC_MASTER_CTRLA _SFR_MEM8(0x0481) -#define TWIC_MASTER_CTRLB _SFR_MEM8(0x0482) -#define TWIC_MASTER_CTRLC _SFR_MEM8(0x0483) -#define TWIC_MASTER_STATUS _SFR_MEM8(0x0484) -#define TWIC_MASTER_BAUD _SFR_MEM8(0x0485) -#define TWIC_MASTER_ADDR _SFR_MEM8(0x0486) -#define TWIC_MASTER_DATA _SFR_MEM8(0x0487) -#define TWIC_SLAVE_CTRLA _SFR_MEM8(0x0488) -#define TWIC_SLAVE_CTRLB _SFR_MEM8(0x0489) -#define TWIC_SLAVE_STATUS _SFR_MEM8(0x048A) -#define TWIC_SLAVE_ADDR _SFR_MEM8(0x048B) -#define TWIC_SLAVE_DATA _SFR_MEM8(0x048C) -#define TWIC_SLAVE_ADDRMASK _SFR_MEM8(0x048D) - -/* TWIE - Two-Wire Interface E */ -#define TWIE_CTRL _SFR_MEM8(0x04A0) -#define TWIE_MASTER_CTRLA _SFR_MEM8(0x04A1) -#define TWIE_MASTER_CTRLB _SFR_MEM8(0x04A2) -#define TWIE_MASTER_CTRLC _SFR_MEM8(0x04A3) -#define TWIE_MASTER_STATUS _SFR_MEM8(0x04A4) -#define TWIE_MASTER_BAUD _SFR_MEM8(0x04A5) -#define TWIE_MASTER_ADDR _SFR_MEM8(0x04A6) -#define TWIE_MASTER_DATA _SFR_MEM8(0x04A7) -#define TWIE_SLAVE_CTRLA _SFR_MEM8(0x04A8) -#define TWIE_SLAVE_CTRLB _SFR_MEM8(0x04A9) -#define TWIE_SLAVE_STATUS _SFR_MEM8(0x04AA) -#define TWIE_SLAVE_ADDR _SFR_MEM8(0x04AB) -#define TWIE_SLAVE_DATA _SFR_MEM8(0x04AC) -#define TWIE_SLAVE_ADDRMASK _SFR_MEM8(0x04AD) - -/* PORTA - Port A */ -#define PORTA_DIR _SFR_MEM8(0x0600) -#define PORTA_DIRSET _SFR_MEM8(0x0601) -#define PORTA_DIRCLR _SFR_MEM8(0x0602) -#define PORTA_DIRTGL _SFR_MEM8(0x0603) -#define PORTA_OUT _SFR_MEM8(0x0604) -#define PORTA_OUTSET _SFR_MEM8(0x0605) -#define PORTA_OUTCLR _SFR_MEM8(0x0606) -#define PORTA_OUTTGL _SFR_MEM8(0x0607) -#define PORTA_IN _SFR_MEM8(0x0608) -#define PORTA_INTCTRL _SFR_MEM8(0x0609) -#define PORTA_INT0MASK _SFR_MEM8(0x060A) -#define PORTA_INT1MASK _SFR_MEM8(0x060B) -#define PORTA_INTFLAGS _SFR_MEM8(0x060C) -#define PORTA_PIN0CTRL _SFR_MEM8(0x0610) -#define PORTA_PIN1CTRL _SFR_MEM8(0x0611) -#define PORTA_PIN2CTRL _SFR_MEM8(0x0612) -#define PORTA_PIN3CTRL _SFR_MEM8(0x0613) -#define PORTA_PIN4CTRL _SFR_MEM8(0x0614) -#define PORTA_PIN5CTRL _SFR_MEM8(0x0615) -#define PORTA_PIN6CTRL _SFR_MEM8(0x0616) -#define PORTA_PIN7CTRL _SFR_MEM8(0x0617) - -/* PORTB - Port B */ -#define PORTB_DIR _SFR_MEM8(0x0620) -#define PORTB_DIRSET _SFR_MEM8(0x0621) -#define PORTB_DIRCLR _SFR_MEM8(0x0622) -#define PORTB_DIRTGL _SFR_MEM8(0x0623) -#define PORTB_OUT _SFR_MEM8(0x0624) -#define PORTB_OUTSET _SFR_MEM8(0x0625) -#define PORTB_OUTCLR _SFR_MEM8(0x0626) -#define PORTB_OUTTGL _SFR_MEM8(0x0627) -#define PORTB_IN _SFR_MEM8(0x0628) -#define PORTB_INTCTRL _SFR_MEM8(0x0629) -#define PORTB_INT0MASK _SFR_MEM8(0x062A) -#define PORTB_INT1MASK _SFR_MEM8(0x062B) -#define PORTB_INTFLAGS _SFR_MEM8(0x062C) -#define PORTB_PIN0CTRL _SFR_MEM8(0x0630) -#define PORTB_PIN1CTRL _SFR_MEM8(0x0631) -#define PORTB_PIN2CTRL _SFR_MEM8(0x0632) -#define PORTB_PIN3CTRL _SFR_MEM8(0x0633) -#define PORTB_PIN4CTRL _SFR_MEM8(0x0634) -#define PORTB_PIN5CTRL _SFR_MEM8(0x0635) -#define PORTB_PIN6CTRL _SFR_MEM8(0x0636) -#define PORTB_PIN7CTRL _SFR_MEM8(0x0637) - -/* PORTC - Port C */ -#define PORTC_DIR _SFR_MEM8(0x0640) -#define PORTC_DIRSET _SFR_MEM8(0x0641) -#define PORTC_DIRCLR _SFR_MEM8(0x0642) -#define PORTC_DIRTGL _SFR_MEM8(0x0643) -#define PORTC_OUT _SFR_MEM8(0x0644) -#define PORTC_OUTSET _SFR_MEM8(0x0645) -#define PORTC_OUTCLR _SFR_MEM8(0x0646) -#define PORTC_OUTTGL _SFR_MEM8(0x0647) -#define PORTC_IN _SFR_MEM8(0x0648) -#define PORTC_INTCTRL _SFR_MEM8(0x0649) -#define PORTC_INT0MASK _SFR_MEM8(0x064A) -#define PORTC_INT1MASK _SFR_MEM8(0x064B) -#define PORTC_INTFLAGS _SFR_MEM8(0x064C) -#define PORTC_PIN0CTRL _SFR_MEM8(0x0650) -#define PORTC_PIN1CTRL _SFR_MEM8(0x0651) -#define PORTC_PIN2CTRL _SFR_MEM8(0x0652) -#define PORTC_PIN3CTRL _SFR_MEM8(0x0653) -#define PORTC_PIN4CTRL _SFR_MEM8(0x0654) -#define PORTC_PIN5CTRL _SFR_MEM8(0x0655) -#define PORTC_PIN6CTRL _SFR_MEM8(0x0656) -#define PORTC_PIN7CTRL _SFR_MEM8(0x0657) - -/* PORTD - Port D */ -#define PORTD_DIR _SFR_MEM8(0x0660) -#define PORTD_DIRSET _SFR_MEM8(0x0661) -#define PORTD_DIRCLR _SFR_MEM8(0x0662) -#define PORTD_DIRTGL _SFR_MEM8(0x0663) -#define PORTD_OUT _SFR_MEM8(0x0664) -#define PORTD_OUTSET _SFR_MEM8(0x0665) -#define PORTD_OUTCLR _SFR_MEM8(0x0666) -#define PORTD_OUTTGL _SFR_MEM8(0x0667) -#define PORTD_IN _SFR_MEM8(0x0668) -#define PORTD_INTCTRL _SFR_MEM8(0x0669) -#define PORTD_INT0MASK _SFR_MEM8(0x066A) -#define PORTD_INT1MASK _SFR_MEM8(0x066B) -#define PORTD_INTFLAGS _SFR_MEM8(0x066C) -#define PORTD_PIN0CTRL _SFR_MEM8(0x0670) -#define PORTD_PIN1CTRL _SFR_MEM8(0x0671) -#define PORTD_PIN2CTRL _SFR_MEM8(0x0672) -#define PORTD_PIN3CTRL _SFR_MEM8(0x0673) -#define PORTD_PIN4CTRL _SFR_MEM8(0x0674) -#define PORTD_PIN5CTRL _SFR_MEM8(0x0675) -#define PORTD_PIN6CTRL _SFR_MEM8(0x0676) -#define PORTD_PIN7CTRL _SFR_MEM8(0x0677) - -/* PORTE - Port E */ -#define PORTE_DIR _SFR_MEM8(0x0680) -#define PORTE_DIRSET _SFR_MEM8(0x0681) -#define PORTE_DIRCLR _SFR_MEM8(0x0682) -#define PORTE_DIRTGL _SFR_MEM8(0x0683) -#define PORTE_OUT _SFR_MEM8(0x0684) -#define PORTE_OUTSET _SFR_MEM8(0x0685) -#define PORTE_OUTCLR _SFR_MEM8(0x0686) -#define PORTE_OUTTGL _SFR_MEM8(0x0687) -#define PORTE_IN _SFR_MEM8(0x0688) -#define PORTE_INTCTRL _SFR_MEM8(0x0689) -#define PORTE_INT0MASK _SFR_MEM8(0x068A) -#define PORTE_INT1MASK _SFR_MEM8(0x068B) -#define PORTE_INTFLAGS _SFR_MEM8(0x068C) -#define PORTE_PIN0CTRL _SFR_MEM8(0x0690) -#define PORTE_PIN1CTRL _SFR_MEM8(0x0691) -#define PORTE_PIN2CTRL _SFR_MEM8(0x0692) -#define PORTE_PIN3CTRL _SFR_MEM8(0x0693) -#define PORTE_PIN4CTRL _SFR_MEM8(0x0694) -#define PORTE_PIN5CTRL _SFR_MEM8(0x0695) -#define PORTE_PIN6CTRL _SFR_MEM8(0x0696) -#define PORTE_PIN7CTRL _SFR_MEM8(0x0697) - -/* PORTF - Port F */ -#define PORTF_DIR _SFR_MEM8(0x06A0) -#define PORTF_DIRSET _SFR_MEM8(0x06A1) -#define PORTF_DIRCLR _SFR_MEM8(0x06A2) -#define PORTF_DIRTGL _SFR_MEM8(0x06A3) -#define PORTF_OUT _SFR_MEM8(0x06A4) -#define PORTF_OUTSET _SFR_MEM8(0x06A5) -#define PORTF_OUTCLR _SFR_MEM8(0x06A6) -#define PORTF_OUTTGL _SFR_MEM8(0x06A7) -#define PORTF_IN _SFR_MEM8(0x06A8) -#define PORTF_INTCTRL _SFR_MEM8(0x06A9) -#define PORTF_INT0MASK _SFR_MEM8(0x06AA) -#define PORTF_INT1MASK _SFR_MEM8(0x06AB) -#define PORTF_INTFLAGS _SFR_MEM8(0x06AC) -#define PORTF_PIN0CTRL _SFR_MEM8(0x06B0) -#define PORTF_PIN1CTRL _SFR_MEM8(0x06B1) -#define PORTF_PIN2CTRL _SFR_MEM8(0x06B2) -#define PORTF_PIN3CTRL _SFR_MEM8(0x06B3) -#define PORTF_PIN4CTRL _SFR_MEM8(0x06B4) -#define PORTF_PIN5CTRL _SFR_MEM8(0x06B5) -#define PORTF_PIN6CTRL _SFR_MEM8(0x06B6) -#define PORTF_PIN7CTRL _SFR_MEM8(0x06B7) - -/* PORTR - Port R */ -#define PORTR_DIR _SFR_MEM8(0x07E0) -#define PORTR_DIRSET _SFR_MEM8(0x07E1) -#define PORTR_DIRCLR _SFR_MEM8(0x07E2) -#define PORTR_DIRTGL _SFR_MEM8(0x07E3) -#define PORTR_OUT _SFR_MEM8(0x07E4) -#define PORTR_OUTSET _SFR_MEM8(0x07E5) -#define PORTR_OUTCLR _SFR_MEM8(0x07E6) -#define PORTR_OUTTGL _SFR_MEM8(0x07E7) -#define PORTR_IN _SFR_MEM8(0x07E8) -#define PORTR_INTCTRL _SFR_MEM8(0x07E9) -#define PORTR_INT0MASK _SFR_MEM8(0x07EA) -#define PORTR_INT1MASK _SFR_MEM8(0x07EB) -#define PORTR_INTFLAGS _SFR_MEM8(0x07EC) -#define PORTR_PIN0CTRL _SFR_MEM8(0x07F0) -#define PORTR_PIN1CTRL _SFR_MEM8(0x07F1) -#define PORTR_PIN2CTRL _SFR_MEM8(0x07F2) -#define PORTR_PIN3CTRL _SFR_MEM8(0x07F3) -#define PORTR_PIN4CTRL _SFR_MEM8(0x07F4) -#define PORTR_PIN5CTRL _SFR_MEM8(0x07F5) -#define PORTR_PIN6CTRL _SFR_MEM8(0x07F6) -#define PORTR_PIN7CTRL _SFR_MEM8(0x07F7) - -/* TCC0 - Timer/Counter C0 */ -#define TCC0_CTRLA _SFR_MEM8(0x0800) -#define TCC0_CTRLB _SFR_MEM8(0x0801) -#define TCC0_CTRLC _SFR_MEM8(0x0802) -#define TCC0_CTRLD _SFR_MEM8(0x0803) -#define TCC0_CTRLE _SFR_MEM8(0x0804) -#define TCC0_INTCTRLA _SFR_MEM8(0x0806) -#define TCC0_INTCTRLB _SFR_MEM8(0x0807) -#define TCC0_CTRLFCLR _SFR_MEM8(0x0808) -#define TCC0_CTRLFSET _SFR_MEM8(0x0809) -#define TCC0_CTRLGCLR _SFR_MEM8(0x080A) -#define TCC0_CTRLGSET _SFR_MEM8(0x080B) -#define TCC0_INTFLAGS _SFR_MEM8(0x080C) -#define TCC0_TEMP _SFR_MEM8(0x080F) -#define TCC0_CNT _SFR_MEM16(0x0820) -#define TCC0_PER _SFR_MEM16(0x0826) -#define TCC0_CCA _SFR_MEM16(0x0828) -#define TCC0_CCB _SFR_MEM16(0x082A) -#define TCC0_CCC _SFR_MEM16(0x082C) -#define TCC0_CCD _SFR_MEM16(0x082E) -#define TCC0_PERBUF _SFR_MEM16(0x0836) -#define TCC0_CCABUF _SFR_MEM16(0x0838) -#define TCC0_CCBBUF _SFR_MEM16(0x083A) -#define TCC0_CCCBUF _SFR_MEM16(0x083C) -#define TCC0_CCDBUF _SFR_MEM16(0x083E) - -/* TCC1 - Timer/Counter C1 */ -#define TCC1_CTRLA _SFR_MEM8(0x0840) -#define TCC1_CTRLB _SFR_MEM8(0x0841) -#define TCC1_CTRLC _SFR_MEM8(0x0842) -#define TCC1_CTRLD _SFR_MEM8(0x0843) -#define TCC1_CTRLE _SFR_MEM8(0x0844) -#define TCC1_INTCTRLA _SFR_MEM8(0x0846) -#define TCC1_INTCTRLB _SFR_MEM8(0x0847) -#define TCC1_CTRLFCLR _SFR_MEM8(0x0848) -#define TCC1_CTRLFSET _SFR_MEM8(0x0849) -#define TCC1_CTRLGCLR _SFR_MEM8(0x084A) -#define TCC1_CTRLGSET _SFR_MEM8(0x084B) -#define TCC1_INTFLAGS _SFR_MEM8(0x084C) -#define TCC1_TEMP _SFR_MEM8(0x084F) -#define TCC1_CNT _SFR_MEM16(0x0860) -#define TCC1_PER _SFR_MEM16(0x0866) -#define TCC1_CCA _SFR_MEM16(0x0868) -#define TCC1_CCB _SFR_MEM16(0x086A) -#define TCC1_PERBUF _SFR_MEM16(0x0876) -#define TCC1_CCABUF _SFR_MEM16(0x0878) -#define TCC1_CCBBUF _SFR_MEM16(0x087A) - -/* AWEXC - Advanced Waveform Extension C */ -#define AWEXC_CTRL _SFR_MEM8(0x0880) -#define AWEXC_FDEMASK _SFR_MEM8(0x0882) -#define AWEXC_FDCTRL _SFR_MEM8(0x0883) -#define AWEXC_STATUS _SFR_MEM8(0x0884) -#define AWEXC_DTBOTH _SFR_MEM8(0x0886) -#define AWEXC_DTBOTHBUF _SFR_MEM8(0x0887) -#define AWEXC_DTLS _SFR_MEM8(0x0888) -#define AWEXC_DTHS _SFR_MEM8(0x0889) -#define AWEXC_DTLSBUF _SFR_MEM8(0x088A) -#define AWEXC_DTHSBUF _SFR_MEM8(0x088B) -#define AWEXC_OUTOVEN _SFR_MEM8(0x088C) - -/* HIRESC - High-Resolution Extension C */ -#define HIRESC_CTRLA _SFR_MEM8(0x0890) - -/* USARTC0 - Universal Asynchronous Receiver-Transmitter C0 */ -#define USARTC0_DATA _SFR_MEM8(0x08A0) -#define USARTC0_STATUS _SFR_MEM8(0x08A1) -#define USARTC0_CTRLA _SFR_MEM8(0x08A3) -#define USARTC0_CTRLB _SFR_MEM8(0x08A4) -#define USARTC0_CTRLC _SFR_MEM8(0x08A5) -#define USARTC0_BAUDCTRLA _SFR_MEM8(0x08A6) -#define USARTC0_BAUDCTRLB _SFR_MEM8(0x08A7) - -/* SPIC - Serial Peripheral Interface C */ -#define SPIC_CTRL _SFR_MEM8(0x08C0) -#define SPIC_INTCTRL _SFR_MEM8(0x08C1) -#define SPIC_STATUS _SFR_MEM8(0x08C2) -#define SPIC_DATA _SFR_MEM8(0x08C3) - -/* IRCOM - IR Communication Module */ -#define IRCOM_CTRL _SFR_MEM8(0x08F8) -#define IRCOM_TXPLCTRL _SFR_MEM8(0x08F9) -#define IRCOM_RXPLCTRL _SFR_MEM8(0x08FA) - -/* TCD0 - Timer/Counter D0 */ -#define TCD0_CTRLA _SFR_MEM8(0x0900) -#define TCD0_CTRLB _SFR_MEM8(0x0901) -#define TCD0_CTRLC _SFR_MEM8(0x0902) -#define TCD0_CTRLD _SFR_MEM8(0x0903) -#define TCD0_CTRLE _SFR_MEM8(0x0904) -#define TCD0_INTCTRLA _SFR_MEM8(0x0906) -#define TCD0_INTCTRLB _SFR_MEM8(0x0907) -#define TCD0_CTRLFCLR _SFR_MEM8(0x0908) -#define TCD0_CTRLFSET _SFR_MEM8(0x0909) -#define TCD0_CTRLGCLR _SFR_MEM8(0x090A) -#define TCD0_CTRLGSET _SFR_MEM8(0x090B) -#define TCD0_INTFLAGS _SFR_MEM8(0x090C) -#define TCD0_TEMP _SFR_MEM8(0x090F) -#define TCD0_CNT _SFR_MEM16(0x0920) -#define TCD0_PER _SFR_MEM16(0x0926) -#define TCD0_CCA _SFR_MEM16(0x0928) -#define TCD0_CCB _SFR_MEM16(0x092A) -#define TCD0_CCC _SFR_MEM16(0x092C) -#define TCD0_CCD _SFR_MEM16(0x092E) -#define TCD0_PERBUF _SFR_MEM16(0x0936) -#define TCD0_CCABUF _SFR_MEM16(0x0938) -#define TCD0_CCBBUF _SFR_MEM16(0x093A) -#define TCD0_CCCBUF _SFR_MEM16(0x093C) -#define TCD0_CCDBUF _SFR_MEM16(0x093E) - -/* USARTD0 - Universal Asynchronous Receiver-Transmitter D0 */ -#define USARTD0_DATA _SFR_MEM8(0x09A0) -#define USARTD0_STATUS _SFR_MEM8(0x09A1) -#define USARTD0_CTRLA _SFR_MEM8(0x09A3) -#define USARTD0_CTRLB _SFR_MEM8(0x09A4) -#define USARTD0_CTRLC _SFR_MEM8(0x09A5) -#define USARTD0_BAUDCTRLA _SFR_MEM8(0x09A6) -#define USARTD0_BAUDCTRLB _SFR_MEM8(0x09A7) - -/* SPID - Serial Peripheral Interface D */ -#define SPID_CTRL _SFR_MEM8(0x09C0) -#define SPID_INTCTRL _SFR_MEM8(0x09C1) -#define SPID_STATUS _SFR_MEM8(0x09C2) -#define SPID_DATA _SFR_MEM8(0x09C3) - -/* TCE0 - Timer/Counter E0 */ -#define TCE0_CTRLA _SFR_MEM8(0x0A00) -#define TCE0_CTRLB _SFR_MEM8(0x0A01) -#define TCE0_CTRLC _SFR_MEM8(0x0A02) -#define TCE0_CTRLD _SFR_MEM8(0x0A03) -#define TCE0_CTRLE _SFR_MEM8(0x0A04) -#define TCE0_INTCTRLA _SFR_MEM8(0x0A06) -#define TCE0_INTCTRLB _SFR_MEM8(0x0A07) -#define TCE0_CTRLFCLR _SFR_MEM8(0x0A08) -#define TCE0_CTRLFSET _SFR_MEM8(0x0A09) -#define TCE0_CTRLGCLR _SFR_MEM8(0x0A0A) -#define TCE0_CTRLGSET _SFR_MEM8(0x0A0B) -#define TCE0_INTFLAGS _SFR_MEM8(0x0A0C) -#define TCE0_TEMP _SFR_MEM8(0x0A0F) -#define TCE0_CNT _SFR_MEM16(0x0A20) -#define TCE0_PER _SFR_MEM16(0x0A26) -#define TCE0_CCA _SFR_MEM16(0x0A28) -#define TCE0_CCB _SFR_MEM16(0x0A2A) -#define TCE0_CCC _SFR_MEM16(0x0A2C) -#define TCE0_CCD _SFR_MEM16(0x0A2E) -#define TCE0_PERBUF _SFR_MEM16(0x0A36) -#define TCE0_CCABUF _SFR_MEM16(0x0A38) -#define TCE0_CCBBUF _SFR_MEM16(0x0A3A) -#define TCE0_CCCBUF _SFR_MEM16(0x0A3C) -#define TCE0_CCDBUF _SFR_MEM16(0x0A3E) - -/* AWEXE - Advanced Waveform Extension E */ -#define AWEXE_CTRL _SFR_MEM8(0x0A80) -#define AWEXE_FDEMASK _SFR_MEM8(0x0A82) -#define AWEXE_FDCTRL _SFR_MEM8(0x0A83) -#define AWEXE_STATUS _SFR_MEM8(0x0A84) -#define AWEXE_DTBOTH _SFR_MEM8(0x0A86) -#define AWEXE_DTBOTHBUF _SFR_MEM8(0x0A87) -#define AWEXE_DTLS _SFR_MEM8(0x0A88) -#define AWEXE_DTHS _SFR_MEM8(0x0A89) -#define AWEXE_DTLSBUF _SFR_MEM8(0x0A8A) -#define AWEXE_DTHSBUF _SFR_MEM8(0x0A8B) -#define AWEXE_OUTOVEN _SFR_MEM8(0x0A8C) - -/* USARTE0 - Universal Asynchronous Receiver-Transmitter E0 */ -#define USARTE0_DATA _SFR_MEM8(0x0AA0) -#define USARTE0_STATUS _SFR_MEM8(0x0AA1) -#define USARTE0_CTRLA _SFR_MEM8(0x0AA3) -#define USARTE0_CTRLB _SFR_MEM8(0x0AA4) -#define USARTE0_CTRLC _SFR_MEM8(0x0AA5) -#define USARTE0_BAUDCTRLA _SFR_MEM8(0x0AA6) -#define USARTE0_BAUDCTRLB _SFR_MEM8(0x0AA7) - -/* SPIE - Serial Peripheral Interface E */ -#define SPIE_CTRL _SFR_MEM8(0x0AC0) -#define SPIE_INTCTRL _SFR_MEM8(0x0AC1) -#define SPIE_STATUS _SFR_MEM8(0x0AC2) -#define SPIE_DATA _SFR_MEM8(0x0AC3) - -/* TCF0 - Timer/Counter F0 */ -#define TCF0_CTRLA _SFR_MEM8(0x0B00) -#define TCF0_CTRLB _SFR_MEM8(0x0B01) -#define TCF0_CTRLC _SFR_MEM8(0x0B02) -#define TCF0_CTRLD _SFR_MEM8(0x0B03) -#define TCF0_CTRLE _SFR_MEM8(0x0B04) -#define TCF0_INTCTRLA _SFR_MEM8(0x0B06) -#define TCF0_INTCTRLB _SFR_MEM8(0x0B07) -#define TCF0_CTRLFCLR _SFR_MEM8(0x0B08) -#define TCF0_CTRLFSET _SFR_MEM8(0x0B09) -#define TCF0_CTRLGCLR _SFR_MEM8(0x0B0A) -#define TCF0_CTRLGSET _SFR_MEM8(0x0B0B) -#define TCF0_INTFLAGS _SFR_MEM8(0x0B0C) -#define TCF0_TEMP _SFR_MEM8(0x0B0F) -#define TCF0_CNT _SFR_MEM16(0x0B20) -#define TCF0_PER _SFR_MEM16(0x0B26) -#define TCF0_CCA _SFR_MEM16(0x0B28) -#define TCF0_CCB _SFR_MEM16(0x0B2A) -#define TCF0_CCC _SFR_MEM16(0x0B2C) -#define TCF0_CCD _SFR_MEM16(0x0B2E) -#define TCF0_PERBUF _SFR_MEM16(0x0B36) -#define TCF0_CCABUF _SFR_MEM16(0x0B38) -#define TCF0_CCBBUF _SFR_MEM16(0x0B3A) -#define TCF0_CCCBUF _SFR_MEM16(0x0B3C) -#define TCF0_CCDBUF _SFR_MEM16(0x0B3E) - - - -/*================== Bitfield Definitions ================== */ - -/* XOCD - On-Chip Debug System */ -/* OCD.OCDR1 bit masks and bit positions */ -#define OCD_OCDRD_bm 0x01 /* OCDR Dirty bit mask. */ -#define OCD_OCDRD_bp 0 /* OCDR Dirty bit position. */ - - -/* CPU - CPU */ -/* CPU.CCP bit masks and bit positions */ -#define CPU_CCP_gm 0xFF /* CCP signature group mask. */ -#define CPU_CCP_gp 0 /* CCP signature group position. */ -#define CPU_CCP0_bm (1<<0) /* CCP signature bit 0 mask. */ -#define CPU_CCP0_bp 0 /* CCP signature bit 0 position. */ -#define CPU_CCP1_bm (1<<1) /* CCP signature bit 1 mask. */ -#define CPU_CCP1_bp 1 /* CCP signature bit 1 position. */ -#define CPU_CCP2_bm (1<<2) /* CCP signature bit 2 mask. */ -#define CPU_CCP2_bp 2 /* CCP signature bit 2 position. */ -#define CPU_CCP3_bm (1<<3) /* CCP signature bit 3 mask. */ -#define CPU_CCP3_bp 3 /* CCP signature bit 3 position. */ -#define CPU_CCP4_bm (1<<4) /* CCP signature bit 4 mask. */ -#define CPU_CCP4_bp 4 /* CCP signature bit 4 position. */ -#define CPU_CCP5_bm (1<<5) /* CCP signature bit 5 mask. */ -#define CPU_CCP5_bp 5 /* CCP signature bit 5 position. */ -#define CPU_CCP6_bm (1<<6) /* CCP signature bit 6 mask. */ -#define CPU_CCP6_bp 6 /* CCP signature bit 6 position. */ -#define CPU_CCP7_bm (1<<7) /* CCP signature bit 7 mask. */ -#define CPU_CCP7_bp 7 /* CCP signature bit 7 position. */ - - -/* CPU.SREG bit masks and bit positions */ -#define CPU_I_bm 0x80 /* Global Interrupt Enable Flag bit mask. */ -#define CPU_I_bp 7 /* Global Interrupt Enable Flag bit position. */ - -#define CPU_T_bm 0x40 /* Transfer Bit bit mask. */ -#define CPU_T_bp 6 /* Transfer Bit bit position. */ - -#define CPU_H_bm 0x20 /* Half Carry Flag bit mask. */ -#define CPU_H_bp 5 /* Half Carry Flag bit position. */ - -#define CPU_S_bm 0x10 /* N Exclusive Or V Flag bit mask. */ -#define CPU_S_bp 4 /* N Exclusive Or V Flag bit position. */ - -#define CPU_V_bm 0x08 /* Two's Complement Overflow Flag bit mask. */ -#define CPU_V_bp 3 /* Two's Complement Overflow Flag bit position. */ - -#define CPU_N_bm 0x04 /* Negative Flag bit mask. */ -#define CPU_N_bp 2 /* Negative Flag bit position. */ - -#define CPU_Z_bm 0x02 /* Zero Flag bit mask. */ -#define CPU_Z_bp 1 /* Zero Flag bit position. */ - -#define CPU_C_bm 0x01 /* Carry Flag bit mask. */ -#define CPU_C_bp 0 /* Carry Flag bit position. */ - - -/* CLK - Clock System */ -/* CLK.CTRL bit masks and bit positions */ -#define CLK_SCLKSEL_gm 0x07 /* System Clock Selection group mask. */ -#define CLK_SCLKSEL_gp 0 /* System Clock Selection group position. */ -#define CLK_SCLKSEL0_bm (1<<0) /* System Clock Selection bit 0 mask. */ -#define CLK_SCLKSEL0_bp 0 /* System Clock Selection bit 0 position. */ -#define CLK_SCLKSEL1_bm (1<<1) /* System Clock Selection bit 1 mask. */ -#define CLK_SCLKSEL1_bp 1 /* System Clock Selection bit 1 position. */ -#define CLK_SCLKSEL2_bm (1<<2) /* System Clock Selection bit 2 mask. */ -#define CLK_SCLKSEL2_bp 2 /* System Clock Selection bit 2 position. */ - - -/* CLK.PSCTRL bit masks and bit positions */ -#define CLK_PSADIV_gm 0x7C /* Prescaler A Division Factor group mask. */ -#define CLK_PSADIV_gp 2 /* Prescaler A Division Factor group position. */ -#define CLK_PSADIV0_bm (1<<2) /* Prescaler A Division Factor bit 0 mask. */ -#define CLK_PSADIV0_bp 2 /* Prescaler A Division Factor bit 0 position. */ -#define CLK_PSADIV1_bm (1<<3) /* Prescaler A Division Factor bit 1 mask. */ -#define CLK_PSADIV1_bp 3 /* Prescaler A Division Factor bit 1 position. */ -#define CLK_PSADIV2_bm (1<<4) /* Prescaler A Division Factor bit 2 mask. */ -#define CLK_PSADIV2_bp 4 /* Prescaler A Division Factor bit 2 position. */ -#define CLK_PSADIV3_bm (1<<5) /* Prescaler A Division Factor bit 3 mask. */ -#define CLK_PSADIV3_bp 5 /* Prescaler A Division Factor bit 3 position. */ -#define CLK_PSADIV4_bm (1<<6) /* Prescaler A Division Factor bit 4 mask. */ -#define CLK_PSADIV4_bp 6 /* Prescaler A Division Factor bit 4 position. */ - -#define CLK_PSBCDIV_gm 0x03 /* Prescaler B and C Division factor group mask. */ -#define CLK_PSBCDIV_gp 0 /* Prescaler B and C Division factor group position. */ -#define CLK_PSBCDIV0_bm (1<<0) /* Prescaler B and C Division factor bit 0 mask. */ -#define CLK_PSBCDIV0_bp 0 /* Prescaler B and C Division factor bit 0 position. */ -#define CLK_PSBCDIV1_bm (1<<1) /* Prescaler B and C Division factor bit 1 mask. */ -#define CLK_PSBCDIV1_bp 1 /* Prescaler B and C Division factor bit 1 position. */ - - -/* CLK.LOCK bit masks and bit positions */ -#define CLK_LOCK_bm 0x01 /* Clock System Lock bit mask. */ -#define CLK_LOCK_bp 0 /* Clock System Lock bit position. */ - - -/* CLK.RTCCTRL bit masks and bit positions */ -#define CLK_RTCSRC_gm 0x0E /* Clock Source group mask. */ -#define CLK_RTCSRC_gp 1 /* Clock Source group position. */ -#define CLK_RTCSRC0_bm (1<<1) /* Clock Source bit 0 mask. */ -#define CLK_RTCSRC0_bp 1 /* Clock Source bit 0 position. */ -#define CLK_RTCSRC1_bm (1<<2) /* Clock Source bit 1 mask. */ -#define CLK_RTCSRC1_bp 2 /* Clock Source bit 1 position. */ -#define CLK_RTCSRC2_bm (1<<3) /* Clock Source bit 2 mask. */ -#define CLK_RTCSRC2_bp 3 /* Clock Source bit 2 position. */ - -#define CLK_RTCEN_bm 0x01 /* RTC Clock Source Enable bit mask. */ -#define CLK_RTCEN_bp 0 /* RTC Clock Source Enable bit position. */ - -/* PR.PRGEN bit masks and bit positions */ -#define PR_RTC_bm 0x04 /* Real-time Counter bit mask. */ -#define PR_RTC_bp 2 /* Real-time Counter bit position. */ - -#define PR_EVSYS_bm 0x02 /* Event System bit mask. */ -#define PR_EVSYS_bp 1 /* Event System bit position. */ - -/* PR.PRPA bit masks and bit positions */ -#define PR_ADC_bm 0x02 /* Port A ADC bit mask. */ -#define PR_ADC_bp 1 /* Port A ADC bit position. */ - -#define PR_AC_bm 0x01 /* Port A Analog Comparator bit mask. */ -#define PR_AC_bp 0 /* Port A Analog Comparator bit position. */ - -/* PR.PRPC bit masks and bit positions */ -#define PR_TWI_bm 0x40 /* Port C Two-wire Interface bit mask. */ -#define PR_TWI_bp 6 /* Port C Two-wire Interface bit position. */ - -#define PR_USART0_bm 0x10 /* Port C USART0 bit mask. */ -#define PR_USART0_bp 4 /* Port C USART0 bit position. */ - -#define PR_SPI_bm 0x08 /* Port C SPI bit mask. */ -#define PR_SPI_bp 3 /* Port C SPI bit position. */ - -#define PR_HIRES_bm 0x04 /* Port C HIRES bit mask. */ -#define PR_HIRES_bp 2 /* Port C HIRES bit position. */ - -#define PR_TC1_bm 0x02 /* Port C Timer/Counter1 bit mask. */ -#define PR_TC1_bp 1 /* Port C Timer/Counter1 bit position. */ - -#define PR_TC0_bm 0x01 /* Port C Timer/Counter0 bit mask. */ -#define PR_TC0_bp 0 /* Port C Timer/Counter0 bit position. */ - -/* PR.PRPD bit masks and bit positions */ -/* PR_USART0 Predefined. */ -/* PR_USART0 Predefined. */ - -/* PR_SPI Predefined. */ -/* PR_SPI Predefined. */ - -/* PR_TC0 Predefined. */ -/* PR_TC0 Predefined. */ - -/* PR.PRPE bit masks and bit positions */ -/* PR_TWI Predefined. */ -/* PR_TWI Predefined. */ - -/* PR_USART0 Predefined. */ -/* PR_USART0 Predefined. */ - -/* PR_TC0 Predefined. */ -/* PR_TC0 Predefined. */ - -/* PR.PRPF bit masks and bit positions */ -/* PR_USART0 Predefined. */ -/* PR_USART0 Predefined. */ - -/* PR_TC0 Predefined. */ -/* PR_TC0 Predefined. */ - -/* SLEEP - Sleep Controller */ -/* SLEEP.CTRL bit masks and bit positions */ -#define SLEEP_SMODE_gm 0x0E /* Sleep Mode group mask. */ -#define SLEEP_SMODE_gp 1 /* Sleep Mode group position. */ -#define SLEEP_SMODE0_bm (1<<1) /* Sleep Mode bit 0 mask. */ -#define SLEEP_SMODE0_bp 1 /* Sleep Mode bit 0 position. */ -#define SLEEP_SMODE1_bm (1<<2) /* Sleep Mode bit 1 mask. */ -#define SLEEP_SMODE1_bp 2 /* Sleep Mode bit 1 position. */ -#define SLEEP_SMODE2_bm (1<<3) /* Sleep Mode bit 2 mask. */ -#define SLEEP_SMODE2_bp 3 /* Sleep Mode bit 2 position. */ - -#define SLEEP_SEN_bm 0x01 /* Sleep Enable bit mask. */ -#define SLEEP_SEN_bp 0 /* Sleep Enable bit position. */ - - -/* OSC - Oscillator */ -/* OSC.CTRL bit masks and bit positions */ -#define OSC_PLLEN_bm 0x10 /* PLL Enable bit mask. */ -#define OSC_PLLEN_bp 4 /* PLL Enable bit position. */ - -#define OSC_XOSCEN_bm 0x08 /* External Oscillator Enable bit mask. */ -#define OSC_XOSCEN_bp 3 /* External Oscillator Enable bit position. */ - -#define OSC_RC32KEN_bm 0x04 /* Internal 32kHz RC Oscillator Enable bit mask. */ -#define OSC_RC32KEN_bp 2 /* Internal 32kHz RC Oscillator Enable bit position. */ - -#define OSC_RC32MEN_bm 0x02 /* Internal 32MHz RC Oscillator Enable bit mask. */ -#define OSC_RC32MEN_bp 1 /* Internal 32MHz RC Oscillator Enable bit position. */ - -#define OSC_RC2MEN_bm 0x01 /* Internal 2MHz RC Oscillator Enable bit mask. */ -#define OSC_RC2MEN_bp 0 /* Internal 2MHz RC Oscillator Enable bit position. */ - - -/* OSC.STATUS bit masks and bit positions */ -#define OSC_PLLRDY_bm 0x10 /* PLL Ready bit mask. */ -#define OSC_PLLRDY_bp 4 /* PLL Ready bit position. */ - -#define OSC_XOSCRDY_bm 0x08 /* External Oscillator Ready bit mask. */ -#define OSC_XOSCRDY_bp 3 /* External Oscillator Ready bit position. */ - -#define OSC_RC32KRDY_bm 0x04 /* Internal 32kHz RC Oscillator Ready bit mask. */ -#define OSC_RC32KRDY_bp 2 /* Internal 32kHz RC Oscillator Ready bit position. */ - -#define OSC_RC32MRDY_bm 0x02 /* Internal 32MHz RC Oscillator Ready bit mask. */ -#define OSC_RC32MRDY_bp 1 /* Internal 32MHz RC Oscillator Ready bit position. */ - -#define OSC_RC2MRDY_bm 0x01 /* Internal 2MHz RC Oscillator Ready bit mask. */ -#define OSC_RC2MRDY_bp 0 /* Internal 2MHz RC Oscillator Ready bit position. */ - - -/* OSC.XOSCCTRL bit masks and bit positions */ -#define OSC_FRQRANGE_gm 0xC0 /* Frequency Range group mask. */ -#define OSC_FRQRANGE_gp 6 /* Frequency Range group position. */ -#define OSC_FRQRANGE0_bm (1<<6) /* Frequency Range bit 0 mask. */ -#define OSC_FRQRANGE0_bp 6 /* Frequency Range bit 0 position. */ -#define OSC_FRQRANGE1_bm (1<<7) /* Frequency Range bit 1 mask. */ -#define OSC_FRQRANGE1_bp 7 /* Frequency Range bit 1 position. */ - -#define OSC_X32KLPM_bm 0x20 /* 32kHz XTAL OSC Low-power Mode bit mask. */ -#define OSC_X32KLPM_bp 5 /* 32kHz XTAL OSC Low-power Mode bit position. */ - -#define OSC_XOSCSEL_gm 0x0F /* External Oscillator Selection and Startup Time group mask. */ -#define OSC_XOSCSEL_gp 0 /* External Oscillator Selection and Startup Time group position. */ -#define OSC_XOSCSEL0_bm (1<<0) /* External Oscillator Selection and Startup Time bit 0 mask. */ -#define OSC_XOSCSEL0_bp 0 /* External Oscillator Selection and Startup Time bit 0 position. */ -#define OSC_XOSCSEL1_bm (1<<1) /* External Oscillator Selection and Startup Time bit 1 mask. */ -#define OSC_XOSCSEL1_bp 1 /* External Oscillator Selection and Startup Time bit 1 position. */ -#define OSC_XOSCSEL2_bm (1<<2) /* External Oscillator Selection and Startup Time bit 2 mask. */ -#define OSC_XOSCSEL2_bp 2 /* External Oscillator Selection and Startup Time bit 2 position. */ -#define OSC_XOSCSEL3_bm (1<<3) /* External Oscillator Selection and Startup Time bit 3 mask. */ -#define OSC_XOSCSEL3_bp 3 /* External Oscillator Selection and Startup Time bit 3 position. */ - - -/* OSC.XOSCFAIL bit masks and bit positions */ -#define OSC_XOSCFDIF_bm 0x02 /* Failure Detection Interrupt Flag bit mask. */ -#define OSC_XOSCFDIF_bp 1 /* Failure Detection Interrupt Flag bit position. */ - -#define OSC_XOSCFDEN_bm 0x01 /* Failure Detection Enable bit mask. */ -#define OSC_XOSCFDEN_bp 0 /* Failure Detection Enable bit position. */ - - -/* OSC.PLLCTRL bit masks and bit positions */ -#define OSC_PLLSRC_gm 0xC0 /* Clock Source group mask. */ -#define OSC_PLLSRC_gp 6 /* Clock Source group position. */ -#define OSC_PLLSRC0_bm (1<<6) /* Clock Source bit 0 mask. */ -#define OSC_PLLSRC0_bp 6 /* Clock Source bit 0 position. */ -#define OSC_PLLSRC1_bm (1<<7) /* Clock Source bit 1 mask. */ -#define OSC_PLLSRC1_bp 7 /* Clock Source bit 1 position. */ - -#define OSC_PLLFAC_gm 0x1F /* Multiplication Factor group mask. */ -#define OSC_PLLFAC_gp 0 /* Multiplication Factor group position. */ -#define OSC_PLLFAC0_bm (1<<0) /* Multiplication Factor bit 0 mask. */ -#define OSC_PLLFAC0_bp 0 /* Multiplication Factor bit 0 position. */ -#define OSC_PLLFAC1_bm (1<<1) /* Multiplication Factor bit 1 mask. */ -#define OSC_PLLFAC1_bp 1 /* Multiplication Factor bit 1 position. */ -#define OSC_PLLFAC2_bm (1<<2) /* Multiplication Factor bit 2 mask. */ -#define OSC_PLLFAC2_bp 2 /* Multiplication Factor bit 2 position. */ -#define OSC_PLLFAC3_bm (1<<3) /* Multiplication Factor bit 3 mask. */ -#define OSC_PLLFAC3_bp 3 /* Multiplication Factor bit 3 position. */ -#define OSC_PLLFAC4_bm (1<<4) /* Multiplication Factor bit 4 mask. */ -#define OSC_PLLFAC4_bp 4 /* Multiplication Factor bit 4 position. */ - - -/* OSC.DFLLCTRL bit masks and bit positions */ -#define OSC_RC32MCREF_bm 0x02 /* 32MHz Calibration Reference bit mask. */ -#define OSC_RC32MCREF_bp 1 /* 32MHz Calibration Reference bit position. */ - -#define OSC_RC2MCREF_bm 0x01 /* 2MHz Calibration Reference bit mask. */ -#define OSC_RC2MCREF_bp 0 /* 2MHz Calibration Reference bit position. */ - - -/* DFLL - DFLL */ -/* DFLL.CTRL bit masks and bit positions */ -#define DFLL_ENABLE_bm 0x01 /* DFLL Enable bit mask. */ -#define DFLL_ENABLE_bp 0 /* DFLL Enable bit position. */ - - -/* DFLL.CALA bit masks and bit positions */ -#define DFLL_CALL_gm 0x7F /* DFLL Calibration bits [6:0] group mask. */ -#define DFLL_CALL_gp 0 /* DFLL Calibration bits [6:0] group position. */ -#define DFLL_CALL0_bm (1<<0) /* DFLL Calibration bits [6:0] bit 0 mask. */ -#define DFLL_CALL0_bp 0 /* DFLL Calibration bits [6:0] bit 0 position. */ -#define DFLL_CALL1_bm (1<<1) /* DFLL Calibration bits [6:0] bit 1 mask. */ -#define DFLL_CALL1_bp 1 /* DFLL Calibration bits [6:0] bit 1 position. */ -#define DFLL_CALL2_bm (1<<2) /* DFLL Calibration bits [6:0] bit 2 mask. */ -#define DFLL_CALL2_bp 2 /* DFLL Calibration bits [6:0] bit 2 position. */ -#define DFLL_CALL3_bm (1<<3) /* DFLL Calibration bits [6:0] bit 3 mask. */ -#define DFLL_CALL3_bp 3 /* DFLL Calibration bits [6:0] bit 3 position. */ -#define DFLL_CALL4_bm (1<<4) /* DFLL Calibration bits [6:0] bit 4 mask. */ -#define DFLL_CALL4_bp 4 /* DFLL Calibration bits [6:0] bit 4 position. */ -#define DFLL_CALL5_bm (1<<5) /* DFLL Calibration bits [6:0] bit 5 mask. */ -#define DFLL_CALL5_bp 5 /* DFLL Calibration bits [6:0] bit 5 position. */ -#define DFLL_CALL6_bm (1<<6) /* DFLL Calibration bits [6:0] bit 6 mask. */ -#define DFLL_CALL6_bp 6 /* DFLL Calibration bits [6:0] bit 6 position. */ - - -/* DFLL.CALB bit masks and bit positions */ -#define DFLL_CALH_gm 0x3F /* DFLL Calibration bits [12:7] group mask. */ -#define DFLL_CALH_gp 0 /* DFLL Calibration bits [12:7] group position. */ -#define DFLL_CALH0_bm (1<<0) /* DFLL Calibration bits [12:7] bit 0 mask. */ -#define DFLL_CALH0_bp 0 /* DFLL Calibration bits [12:7] bit 0 position. */ -#define DFLL_CALH1_bm (1<<1) /* DFLL Calibration bits [12:7] bit 1 mask. */ -#define DFLL_CALH1_bp 1 /* DFLL Calibration bits [12:7] bit 1 position. */ -#define DFLL_CALH2_bm (1<<2) /* DFLL Calibration bits [12:7] bit 2 mask. */ -#define DFLL_CALH2_bp 2 /* DFLL Calibration bits [12:7] bit 2 position. */ -#define DFLL_CALH3_bm (1<<3) /* DFLL Calibration bits [12:7] bit 3 mask. */ -#define DFLL_CALH3_bp 3 /* DFLL Calibration bits [12:7] bit 3 position. */ -#define DFLL_CALH4_bm (1<<4) /* DFLL Calibration bits [12:7] bit 4 mask. */ -#define DFLL_CALH4_bp 4 /* DFLL Calibration bits [12:7] bit 4 position. */ -#define DFLL_CALH5_bm (1<<5) /* DFLL Calibration bits [12:7] bit 5 mask. */ -#define DFLL_CALH5_bp 5 /* DFLL Calibration bits [12:7] bit 5 position. */ - - -/* RST - Reset */ -/* RST.STATUS bit masks and bit positions */ -#define RST_SDRF_bm 0x40 /* Spike Detection Reset Flag bit mask. */ -#define RST_SDRF_bp 6 /* Spike Detection Reset Flag bit position. */ - -#define RST_SRF_bm 0x20 /* Software Reset Flag bit mask. */ -#define RST_SRF_bp 5 /* Software Reset Flag bit position. */ - -#define RST_PDIRF_bm 0x10 /* Programming and Debug Interface Interface Reset Flag bit mask. */ -#define RST_PDIRF_bp 4 /* Programming and Debug Interface Interface Reset Flag bit position. */ - -#define RST_WDRF_bm 0x08 /* Watchdog Reset Flag bit mask. */ -#define RST_WDRF_bp 3 /* Watchdog Reset Flag bit position. */ - -#define RST_BORF_bm 0x04 /* Brown-out Reset Flag bit mask. */ -#define RST_BORF_bp 2 /* Brown-out Reset Flag bit position. */ - -#define RST_EXTRF_bm 0x02 /* External Reset Flag bit mask. */ -#define RST_EXTRF_bp 1 /* External Reset Flag bit position. */ - -#define RST_PORF_bm 0x01 /* Power-on Reset Flag bit mask. */ -#define RST_PORF_bp 0 /* Power-on Reset Flag bit position. */ - - -/* RST.CTRL bit masks and bit positions */ -#define RST_SWRST_bm 0x01 /* Software Reset bit mask. */ -#define RST_SWRST_bp 0 /* Software Reset bit position. */ - - -/* WDT - Watch-Dog Timer */ -/* WDT.CTRL bit masks and bit positions */ -#define WDT_PER_gm 0x3C /* Period group mask. */ -#define WDT_PER_gp 2 /* Period group position. */ -#define WDT_PER0_bm (1<<2) /* Period bit 0 mask. */ -#define WDT_PER0_bp 2 /* Period bit 0 position. */ -#define WDT_PER1_bm (1<<3) /* Period bit 1 mask. */ -#define WDT_PER1_bp 3 /* Period bit 1 position. */ -#define WDT_PER2_bm (1<<4) /* Period bit 2 mask. */ -#define WDT_PER2_bp 4 /* Period bit 2 position. */ -#define WDT_PER3_bm (1<<5) /* Period bit 3 mask. */ -#define WDT_PER3_bp 5 /* Period bit 3 position. */ - -#define WDT_ENABLE_bm 0x02 /* Enable bit mask. */ -#define WDT_ENABLE_bp 1 /* Enable bit position. */ - -#define WDT_CEN_bm 0x01 /* Change Enable bit mask. */ -#define WDT_CEN_bp 0 /* Change Enable bit position. */ - - -/* WDT.WINCTRL bit masks and bit positions */ -#define WDT_WPER_gm 0x3C /* Windowed Mode Period group mask. */ -#define WDT_WPER_gp 2 /* Windowed Mode Period group position. */ -#define WDT_WPER0_bm (1<<2) /* Windowed Mode Period bit 0 mask. */ -#define WDT_WPER0_bp 2 /* Windowed Mode Period bit 0 position. */ -#define WDT_WPER1_bm (1<<3) /* Windowed Mode Period bit 1 mask. */ -#define WDT_WPER1_bp 3 /* Windowed Mode Period bit 1 position. */ -#define WDT_WPER2_bm (1<<4) /* Windowed Mode Period bit 2 mask. */ -#define WDT_WPER2_bp 4 /* Windowed Mode Period bit 2 position. */ -#define WDT_WPER3_bm (1<<5) /* Windowed Mode Period bit 3 mask. */ -#define WDT_WPER3_bp 5 /* Windowed Mode Period bit 3 position. */ - -#define WDT_WEN_bm 0x02 /* Windowed Mode Enable bit mask. */ -#define WDT_WEN_bp 1 /* Windowed Mode Enable bit position. */ - -#define WDT_WCEN_bm 0x01 /* Windowed Mode Change Enable bit mask. */ -#define WDT_WCEN_bp 0 /* Windowed Mode Change Enable bit position. */ - - -/* WDT.STATUS bit masks and bit positions */ -#define WDT_SYNCBUSY_bm 0x01 /* Syncronization busy bit mask. */ -#define WDT_SYNCBUSY_bp 0 /* Syncronization busy bit position. */ - - -/* MCU - MCU Control */ -/* MCU.MCUCR bit masks and bit positions */ -#define MCU_JTAGD_bm 0x01 /* JTAG Disable bit mask. */ -#define MCU_JTAGD_bp 0 /* JTAG Disable bit position. */ - - -/* MCU.EVSYSLOCK bit masks and bit positions */ -#define MCU_EVSYS1LOCK_bm 0x10 /* Event Channel 4-7 Lock bit mask. */ -#define MCU_EVSYS1LOCK_bp 4 /* Event Channel 4-7 Lock bit position. */ - -#define MCU_EVSYS0LOCK_bm 0x01 /* Event Channel 0-3 Lock bit mask. */ -#define MCU_EVSYS0LOCK_bp 0 /* Event Channel 0-3 Lock bit position. */ - - -/* MCU.AWEXLOCK bit masks and bit positions */ -#define MCU_AWEXELOCK_bm 0x04 /* AWeX on T/C E0 Lock bit mask. */ -#define MCU_AWEXELOCK_bp 2 /* AWeX on T/C E0 Lock bit position. */ - -#define MCU_AWEXCLOCK_bm 0x01 /* AWeX on T/C C0 Lock bit mask. */ -#define MCU_AWEXCLOCK_bp 0 /* AWeX on T/C C0 Lock bit position. */ - - -/* PMIC - Programmable Multi-level Interrupt Controller */ -/* PMIC.STATUS bit masks and bit positions */ -#define PMIC_NMIEX_bm 0x80 /* Non-maskable Interrupt Executing bit mask. */ -#define PMIC_NMIEX_bp 7 /* Non-maskable Interrupt Executing bit position. */ - -#define PMIC_HILVLEX_bm 0x04 /* High Level Interrupt Executing bit mask. */ -#define PMIC_HILVLEX_bp 2 /* High Level Interrupt Executing bit position. */ - -#define PMIC_MEDLVLEX_bm 0x02 /* Medium Level Interrupt Executing bit mask. */ -#define PMIC_MEDLVLEX_bp 1 /* Medium Level Interrupt Executing bit position. */ - -#define PMIC_LOLVLEX_bm 0x01 /* Low Level Interrupt Executing bit mask. */ -#define PMIC_LOLVLEX_bp 0 /* Low Level Interrupt Executing bit position. */ - - -/* PMIC.CTRL bit masks and bit positions */ -#define PMIC_RREN_bm 0x80 /* Round-Robin Priority Enable bit mask. */ -#define PMIC_RREN_bp 7 /* Round-Robin Priority Enable bit position. */ - -#define PMIC_IVSEL_bm 0x40 /* Interrupt Vector Select bit mask. */ -#define PMIC_IVSEL_bp 6 /* Interrupt Vector Select bit position. */ - -#define PMIC_HILVLEN_bm 0x04 /* High Level Enable bit mask. */ -#define PMIC_HILVLEN_bp 2 /* High Level Enable bit position. */ - -#define PMIC_MEDLVLEN_bm 0x02 /* Medium Level Enable bit mask. */ -#define PMIC_MEDLVLEN_bp 1 /* Medium Level Enable bit position. */ - -#define PMIC_LOLVLEN_bm 0x01 /* Low Level Enable bit mask. */ -#define PMIC_LOLVLEN_bp 0 /* Low Level Enable bit position. */ - - -/* CRC - Cyclic Redundancy Checker */ -/* CRC.CTRL bit masks and bit positions */ -#define CRC_RESET_gm 0xC0 /* Reset group mask. */ -#define CRC_RESET_gp 6 /* Reset group position. */ -#define CRC_RESET0_bm (1<<6) /* Reset bit 0 mask. */ -#define CRC_RESET0_bp 6 /* Reset bit 0 position. */ -#define CRC_RESET1_bm (1<<7) /* Reset bit 1 mask. */ -#define CRC_RESET1_bp 7 /* Reset bit 1 position. */ - -#define CRC_CRC32_bm 0x20 /* CRC Mode bit mask. */ -#define CRC_CRC32_bp 5 /* CRC Mode bit position. */ - -#define CRC_SOURCE_gm 0x0F /* Input Source group mask. */ -#define CRC_SOURCE_gp 0 /* Input Source group position. */ -#define CRC_SOURCE0_bm (1<<0) /* Input Source bit 0 mask. */ -#define CRC_SOURCE0_bp 0 /* Input Source bit 0 position. */ -#define CRC_SOURCE1_bm (1<<1) /* Input Source bit 1 mask. */ -#define CRC_SOURCE1_bp 1 /* Input Source bit 1 position. */ -#define CRC_SOURCE2_bm (1<<2) /* Input Source bit 2 mask. */ -#define CRC_SOURCE2_bp 2 /* Input Source bit 2 position. */ -#define CRC_SOURCE3_bm (1<<3) /* Input Source bit 3 mask. */ -#define CRC_SOURCE3_bp 3 /* Input Source bit 3 position. */ - -/* CRC.STATUS bit masks and bit positions */ -#define CRC_ZERO_bm 0x02 /* Zero detection bit mask. */ -#define CRC_ZERO_bp 1 /* Zero detection bit position. */ - -#define CRC_BUSY_bm 0x01 /* Busy bit mask. */ -#define CRC_BUSY_bp 0 /* Busy bit position. */ - - -/* EVSYS - Event System */ -/* EVSYS.CH0MUX bit masks and bit positions */ -#define EVSYS_CHMUX_gm 0xFF /* Event Channel 0 Multiplexer group mask. */ -#define EVSYS_CHMUX_gp 0 /* Event Channel 0 Multiplexer group position. */ -#define EVSYS_CHMUX0_bm (1<<0) /* Event Channel 0 Multiplexer bit 0 mask. */ -#define EVSYS_CHMUX0_bp 0 /* Event Channel 0 Multiplexer bit 0 position. */ -#define EVSYS_CHMUX1_bm (1<<1) /* Event Channel 0 Multiplexer bit 1 mask. */ -#define EVSYS_CHMUX1_bp 1 /* Event Channel 0 Multiplexer bit 1 position. */ -#define EVSYS_CHMUX2_bm (1<<2) /* Event Channel 0 Multiplexer bit 2 mask. */ -#define EVSYS_CHMUX2_bp 2 /* Event Channel 0 Multiplexer bit 2 position. */ -#define EVSYS_CHMUX3_bm (1<<3) /* Event Channel 0 Multiplexer bit 3 mask. */ -#define EVSYS_CHMUX3_bp 3 /* Event Channel 0 Multiplexer bit 3 position. */ -#define EVSYS_CHMUX4_bm (1<<4) /* Event Channel 0 Multiplexer bit 4 mask. */ -#define EVSYS_CHMUX4_bp 4 /* Event Channel 0 Multiplexer bit 4 position. */ -#define EVSYS_CHMUX5_bm (1<<5) /* Event Channel 0 Multiplexer bit 5 mask. */ -#define EVSYS_CHMUX5_bp 5 /* Event Channel 0 Multiplexer bit 5 position. */ -#define EVSYS_CHMUX6_bm (1<<6) /* Event Channel 0 Multiplexer bit 6 mask. */ -#define EVSYS_CHMUX6_bp 6 /* Event Channel 0 Multiplexer bit 6 position. */ -#define EVSYS_CHMUX7_bm (1<<7) /* Event Channel 0 Multiplexer bit 7 mask. */ -#define EVSYS_CHMUX7_bp 7 /* Event Channel 0 Multiplexer bit 7 position. */ - - -/* EVSYS.CH1MUX bit masks and bit positions */ -/* EVSYS_CHMUX_gm Predefined. */ -/* EVSYS_CHMUX_gp Predefined. */ -/* EVSYS_CHMUX0_bm Predefined. */ -/* EVSYS_CHMUX0_bp Predefined. */ -/* EVSYS_CHMUX1_bm Predefined. */ -/* EVSYS_CHMUX1_bp Predefined. */ -/* EVSYS_CHMUX2_bm Predefined. */ -/* EVSYS_CHMUX2_bp Predefined. */ -/* EVSYS_CHMUX3_bm Predefined. */ -/* EVSYS_CHMUX3_bp Predefined. */ -/* EVSYS_CHMUX4_bm Predefined. */ -/* EVSYS_CHMUX4_bp Predefined. */ -/* EVSYS_CHMUX5_bm Predefined. */ -/* EVSYS_CHMUX5_bp Predefined. */ -/* EVSYS_CHMUX6_bm Predefined. */ -/* EVSYS_CHMUX6_bp Predefined. */ -/* EVSYS_CHMUX7_bm Predefined. */ -/* EVSYS_CHMUX7_bp Predefined. */ - - -/* EVSYS.CH2MUX bit masks and bit positions */ -/* EVSYS_CHMUX_gm Predefined. */ -/* EVSYS_CHMUX_gp Predefined. */ -/* EVSYS_CHMUX0_bm Predefined. */ -/* EVSYS_CHMUX0_bp Predefined. */ -/* EVSYS_CHMUX1_bm Predefined. */ -/* EVSYS_CHMUX1_bp Predefined. */ -/* EVSYS_CHMUX2_bm Predefined. */ -/* EVSYS_CHMUX2_bp Predefined. */ -/* EVSYS_CHMUX3_bm Predefined. */ -/* EVSYS_CHMUX3_bp Predefined. */ -/* EVSYS_CHMUX4_bm Predefined. */ -/* EVSYS_CHMUX4_bp Predefined. */ -/* EVSYS_CHMUX5_bm Predefined. */ -/* EVSYS_CHMUX5_bp Predefined. */ -/* EVSYS_CHMUX6_bm Predefined. */ -/* EVSYS_CHMUX6_bp Predefined. */ -/* EVSYS_CHMUX7_bm Predefined. */ -/* EVSYS_CHMUX7_bp Predefined. */ - - -/* EVSYS.CH3MUX bit masks and bit positions */ -/* EVSYS_CHMUX_gm Predefined. */ -/* EVSYS_CHMUX_gp Predefined. */ -/* EVSYS_CHMUX0_bm Predefined. */ -/* EVSYS_CHMUX0_bp Predefined. */ -/* EVSYS_CHMUX1_bm Predefined. */ -/* EVSYS_CHMUX1_bp Predefined. */ -/* EVSYS_CHMUX2_bm Predefined. */ -/* EVSYS_CHMUX2_bp Predefined. */ -/* EVSYS_CHMUX3_bm Predefined. */ -/* EVSYS_CHMUX3_bp Predefined. */ -/* EVSYS_CHMUX4_bm Predefined. */ -/* EVSYS_CHMUX4_bp Predefined. */ -/* EVSYS_CHMUX5_bm Predefined. */ -/* EVSYS_CHMUX5_bp Predefined. */ -/* EVSYS_CHMUX6_bm Predefined. */ -/* EVSYS_CHMUX6_bp Predefined. */ -/* EVSYS_CHMUX7_bm Predefined. */ -/* EVSYS_CHMUX7_bp Predefined. */ - - -/* EVSYS.CH0CTRL bit masks and bit positions */ -#define EVSYS_QDIRM_gm 0x60 /* Quadrature Decoder Index Recognition Mode group mask. */ -#define EVSYS_QDIRM_gp 5 /* Quadrature Decoder Index Recognition Mode group position. */ -#define EVSYS_QDIRM0_bm (1<<5) /* Quadrature Decoder Index Recognition Mode bit 0 mask. */ -#define EVSYS_QDIRM0_bp 5 /* Quadrature Decoder Index Recognition Mode bit 0 position. */ -#define EVSYS_QDIRM1_bm (1<<6) /* Quadrature Decoder Index Recognition Mode bit 1 mask. */ -#define EVSYS_QDIRM1_bp 6 /* Quadrature Decoder Index Recognition Mode bit 1 position. */ - -#define EVSYS_QDIEN_bm 0x10 /* Quadrature Decoder Index Enable bit mask. */ -#define EVSYS_QDIEN_bp 4 /* Quadrature Decoder Index Enable bit position. */ - -#define EVSYS_QDEN_bm 0x08 /* Quadrature Decoder Enable bit mask. */ -#define EVSYS_QDEN_bp 3 /* Quadrature Decoder Enable bit position. */ - -#define EVSYS_DIGFILT_gm 0x07 /* Digital Filter group mask. */ -#define EVSYS_DIGFILT_gp 0 /* Digital Filter group position. */ -#define EVSYS_DIGFILT0_bm (1<<0) /* Digital Filter bit 0 mask. */ -#define EVSYS_DIGFILT0_bp 0 /* Digital Filter bit 0 position. */ -#define EVSYS_DIGFILT1_bm (1<<1) /* Digital Filter bit 1 mask. */ -#define EVSYS_DIGFILT1_bp 1 /* Digital Filter bit 1 position. */ -#define EVSYS_DIGFILT2_bm (1<<2) /* Digital Filter bit 2 mask. */ -#define EVSYS_DIGFILT2_bp 2 /* Digital Filter bit 2 position. */ - - -/* EVSYS.CH1CTRL bit masks and bit positions */ -/* EVSYS_DIGFILT_gm Predefined. */ -/* EVSYS_DIGFILT_gp Predefined. */ -/* EVSYS_DIGFILT0_bm Predefined. */ -/* EVSYS_DIGFILT0_bp Predefined. */ -/* EVSYS_DIGFILT1_bm Predefined. */ -/* EVSYS_DIGFILT1_bp Predefined. */ -/* EVSYS_DIGFILT2_bm Predefined. */ -/* EVSYS_DIGFILT2_bp Predefined. */ - - -/* EVSYS.CH2CTRL bit masks and bit positions */ -/* EVSYS_QDIRM_gm Predefined. */ -/* EVSYS_QDIRM_gp Predefined. */ -/* EVSYS_QDIRM0_bm Predefined. */ -/* EVSYS_QDIRM0_bp Predefined. */ -/* EVSYS_QDIRM1_bm Predefined. */ -/* EVSYS_QDIRM1_bp Predefined. */ - -/* EVSYS_QDIEN_bm Predefined. */ -/* EVSYS_QDIEN_bp Predefined. */ - -/* EVSYS_QDEN_bm Predefined. */ -/* EVSYS_QDEN_bp Predefined. */ - -/* EVSYS_DIGFILT_gm Predefined. */ -/* EVSYS_DIGFILT_gp Predefined. */ -/* EVSYS_DIGFILT0_bm Predefined. */ -/* EVSYS_DIGFILT0_bp Predefined. */ -/* EVSYS_DIGFILT1_bm Predefined. */ -/* EVSYS_DIGFILT1_bp Predefined. */ -/* EVSYS_DIGFILT2_bm Predefined. */ -/* EVSYS_DIGFILT2_bp Predefined. */ - - -/* EVSYS.CH3CTRL bit masks and bit positions */ -/* EVSYS_DIGFILT_gm Predefined. */ -/* EVSYS_DIGFILT_gp Predefined. */ -/* EVSYS_DIGFILT0_bm Predefined. */ -/* EVSYS_DIGFILT0_bp Predefined. */ -/* EVSYS_DIGFILT1_bm Predefined. */ -/* EVSYS_DIGFILT1_bp Predefined. */ -/* EVSYS_DIGFILT2_bm Predefined. */ -/* EVSYS_DIGFILT2_bp Predefined. */ - - -/* NVM - Non Volatile Memory Controller */ -/* NVM.CMD bit masks and bit positions */ -#define NVM_CMD_gm 0xFF /* Command group mask. */ -#define NVM_CMD_gp 0 /* Command group position. */ -#define NVM_CMD0_bm (1<<0) /* Command bit 0 mask. */ -#define NVM_CMD0_bp 0 /* Command bit 0 position. */ -#define NVM_CMD1_bm (1<<1) /* Command bit 1 mask. */ -#define NVM_CMD1_bp 1 /* Command bit 1 position. */ -#define NVM_CMD2_bm (1<<2) /* Command bit 2 mask. */ -#define NVM_CMD2_bp 2 /* Command bit 2 position. */ -#define NVM_CMD3_bm (1<<3) /* Command bit 3 mask. */ -#define NVM_CMD3_bp 3 /* Command bit 3 position. */ -#define NVM_CMD4_bm (1<<4) /* Command bit 4 mask. */ -#define NVM_CMD4_bp 4 /* Command bit 4 position. */ -#define NVM_CMD5_bm (1<<5) /* Command bit 5 mask. */ -#define NVM_CMD5_bp 5 /* Command bit 5 position. */ -#define NVM_CMD6_bm (1<<6) /* Command bit 6 mask. */ -#define NVM_CMD6_bp 6 /* Command bit 6 position. */ -#define NVM_CMD7_bm (1<<7) /* Command bit 7 mask. */ -#define NVM_CMD7_bp 7 /* Command bit 7 position. */ - - -/* NVM.CTRLA bit masks and bit positions */ -#define NVM_CMDEX_bm 0x01 /* Command Execute bit mask. */ -#define NVM_CMDEX_bp 0 /* Command Execute bit position. */ - - -/* NVM.CTRLB bit masks and bit positions */ -#define NVM_EEMAPEN_bm 0x08 /* EEPROM Mapping Enable bit mask. */ -#define NVM_EEMAPEN_bp 3 /* EEPROM Mapping Enable bit position. */ - -#define NVM_FPRM_bm 0x04 /* Flash Power Reduction Enable bit mask. */ -#define NVM_FPRM_bp 2 /* Flash Power Reduction Enable bit position. */ - -#define NVM_EPRM_bm 0x02 /* EEPROM Power Reduction Enable bit mask. */ -#define NVM_EPRM_bp 1 /* EEPROM Power Reduction Enable bit position. */ - -#define NVM_SPMLOCK_bm 0x01 /* SPM Lock bit mask. */ -#define NVM_SPMLOCK_bp 0 /* SPM Lock bit position. */ - - -/* NVM.INTCTRL bit masks and bit positions */ -#define NVM_SPMLVL_gm 0x0C /* SPM Interrupt Level group mask. */ -#define NVM_SPMLVL_gp 2 /* SPM Interrupt Level group position. */ -#define NVM_SPMLVL0_bm (1<<2) /* SPM Interrupt Level bit 0 mask. */ -#define NVM_SPMLVL0_bp 2 /* SPM Interrupt Level bit 0 position. */ -#define NVM_SPMLVL1_bm (1<<3) /* SPM Interrupt Level bit 1 mask. */ -#define NVM_SPMLVL1_bp 3 /* SPM Interrupt Level bit 1 position. */ - -#define NVM_EELVL_gm 0x03 /* EEPROM Interrupt Level group mask. */ -#define NVM_EELVL_gp 0 /* EEPROM Interrupt Level group position. */ -#define NVM_EELVL0_bm (1<<0) /* EEPROM Interrupt Level bit 0 mask. */ -#define NVM_EELVL0_bp 0 /* EEPROM Interrupt Level bit 0 position. */ -#define NVM_EELVL1_bm (1<<1) /* EEPROM Interrupt Level bit 1 mask. */ -#define NVM_EELVL1_bp 1 /* EEPROM Interrupt Level bit 1 position. */ - - -/* NVM.STATUS bit masks and bit positions */ -#define NVM_NVMBUSY_bm 0x80 /* Non-volatile Memory Busy bit mask. */ -#define NVM_NVMBUSY_bp 7 /* Non-volatile Memory Busy bit position. */ - -#define NVM_FBUSY_bm 0x40 /* Flash Memory Busy bit mask. */ -#define NVM_FBUSY_bp 6 /* Flash Memory Busy bit position. */ - -#define NVM_EELOAD_bm 0x02 /* EEPROM Page Buffer Active Loading bit mask. */ -#define NVM_EELOAD_bp 1 /* EEPROM Page Buffer Active Loading bit position. */ - -#define NVM_FLOAD_bm 0x01 /* Flash Page Buffer Active Loading bit mask. */ -#define NVM_FLOAD_bp 0 /* Flash Page Buffer Active Loading bit position. */ - - -/* NVM.LOCKBITS bit masks and bit positions */ -#define NVM_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ -#define NVM_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ -#define NVM_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ -#define NVM_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ -#define NVM_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ -#define NVM_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ - -#define NVM_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ -#define NVM_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ -#define NVM_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ -#define NVM_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ -#define NVM_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ -#define NVM_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ - -#define NVM_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ -#define NVM_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ -#define NVM_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ -#define NVM_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ -#define NVM_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ -#define NVM_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ - -#define NVM_LB_gm 0x03 /* Lock Bits group mask. */ -#define NVM_LB_gp 0 /* Lock Bits group position. */ -#define NVM_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ -#define NVM_LB0_bp 0 /* Lock Bits bit 0 position. */ -#define NVM_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ -#define NVM_LB1_bp 1 /* Lock Bits bit 1 position. */ - - -/* NVM_LOCKBITS.LOCKBITS bit masks and bit positions */ -#define NVM_LOCKBITS_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ -#define NVM_LOCKBITS_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ -#define NVM_LOCKBITS_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ -#define NVM_LOCKBITS_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ -#define NVM_LOCKBITS_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ -#define NVM_LOCKBITS_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ - -#define NVM_LOCKBITS_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ -#define NVM_LOCKBITS_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ -#define NVM_LOCKBITS_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ -#define NVM_LOCKBITS_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ -#define NVM_LOCKBITS_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ -#define NVM_LOCKBITS_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ - -#define NVM_LOCKBITS_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ -#define NVM_LOCKBITS_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ -#define NVM_LOCKBITS_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ -#define NVM_LOCKBITS_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ -#define NVM_LOCKBITS_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ -#define NVM_LOCKBITS_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ - -#define NVM_LOCKBITS_LB_gm 0x03 /* Lock Bits group mask. */ -#define NVM_LOCKBITS_LB_gp 0 /* Lock Bits group position. */ -#define NVM_LOCKBITS_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ -#define NVM_LOCKBITS_LB0_bp 0 /* Lock Bits bit 0 position. */ -#define NVM_LOCKBITS_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ -#define NVM_LOCKBITS_LB1_bp 1 /* Lock Bits bit 1 position. */ - - -/* NVM_FUSES.FUSEBYTE0 bit masks and bit positions */ -#define NVM_FUSES_USERID_gm 0xFF /* User ID group mask. */ -#define NVM_FUSES_USERID_gp 0 /* User ID group position. */ -#define NVM_FUSES_USERID0_bm (1<<0) /* User ID bit 0 mask. */ -#define NVM_FUSES_USERID0_bp 0 /* User ID bit 0 position. */ -#define NVM_FUSES_USERID1_bm (1<<1) /* User ID bit 1 mask. */ -#define NVM_FUSES_USERID1_bp 1 /* User ID bit 1 position. */ -#define NVM_FUSES_USERID2_bm (1<<2) /* User ID bit 2 mask. */ -#define NVM_FUSES_USERID2_bp 2 /* User ID bit 2 position. */ -#define NVM_FUSES_USERID3_bm (1<<3) /* User ID bit 3 mask. */ -#define NVM_FUSES_USERID3_bp 3 /* User ID bit 3 position. */ -#define NVM_FUSES_USERID4_bm (1<<4) /* User ID bit 4 mask. */ -#define NVM_FUSES_USERID4_bp 4 /* User ID bit 4 position. */ -#define NVM_FUSES_USERID5_bm (1<<5) /* User ID bit 5 mask. */ -#define NVM_FUSES_USERID5_bp 5 /* User ID bit 5 position. */ -#define NVM_FUSES_USERID6_bm (1<<6) /* User ID bit 6 mask. */ -#define NVM_FUSES_USERID6_bp 6 /* User ID bit 6 position. */ -#define NVM_FUSES_USERID7_bm (1<<7) /* User ID bit 7 mask. */ -#define NVM_FUSES_USERID7_bp 7 /* User ID bit 7 position. */ - - -/* NVM_FUSES.FUSEBYTE1 bit masks and bit positions */ -#define NVM_FUSES_WDWP_gm 0xF0 /* Watchdog Window Timeout Period group mask. */ -#define NVM_FUSES_WDWP_gp 4 /* Watchdog Window Timeout Period group position. */ -#define NVM_FUSES_WDWP0_bm (1<<4) /* Watchdog Window Timeout Period bit 0 mask. */ -#define NVM_FUSES_WDWP0_bp 4 /* Watchdog Window Timeout Period bit 0 position. */ -#define NVM_FUSES_WDWP1_bm (1<<5) /* Watchdog Window Timeout Period bit 1 mask. */ -#define NVM_FUSES_WDWP1_bp 5 /* Watchdog Window Timeout Period bit 1 position. */ -#define NVM_FUSES_WDWP2_bm (1<<6) /* Watchdog Window Timeout Period bit 2 mask. */ -#define NVM_FUSES_WDWP2_bp 6 /* Watchdog Window Timeout Period bit 2 position. */ -#define NVM_FUSES_WDWP3_bm (1<<7) /* Watchdog Window Timeout Period bit 3 mask. */ -#define NVM_FUSES_WDWP3_bp 7 /* Watchdog Window Timeout Period bit 3 position. */ - -#define NVM_FUSES_WDP_gm 0x0F /* Watchdog Timeout Period group mask. */ -#define NVM_FUSES_WDP_gp 0 /* Watchdog Timeout Period group position. */ -#define NVM_FUSES_WDP0_bm (1<<0) /* Watchdog Timeout Period bit 0 mask. */ -#define NVM_FUSES_WDP0_bp 0 /* Watchdog Timeout Period bit 0 position. */ -#define NVM_FUSES_WDP1_bm (1<<1) /* Watchdog Timeout Period bit 1 mask. */ -#define NVM_FUSES_WDP1_bp 1 /* Watchdog Timeout Period bit 1 position. */ -#define NVM_FUSES_WDP2_bm (1<<2) /* Watchdog Timeout Period bit 2 mask. */ -#define NVM_FUSES_WDP2_bp 2 /* Watchdog Timeout Period bit 2 position. */ -#define NVM_FUSES_WDP3_bm (1<<3) /* Watchdog Timeout Period bit 3 mask. */ -#define NVM_FUSES_WDP3_bp 3 /* Watchdog Timeout Period bit 3 position. */ - - -/* NVM_FUSES.FUSEBYTE2 bit masks and bit positions */ -#define NVM_FUSES_DVSDON_bm 0x80 /* Spike Detector Enable bit mask. */ -#define NVM_FUSES_DVSDON_bp 7 /* Spike Detector Enable bit position. */ - -#define NVM_FUSES_BOOTRST_bm 0x40 /* Boot Loader Section Reset Vector bit mask. */ -#define NVM_FUSES_BOOTRST_bp 6 /* Boot Loader Section Reset Vector bit position. */ - -#define NVM_FUSES_BODPD_gm 0x03 /* BOD Operation in Power-Down Mode group mask. */ -#define NVM_FUSES_BODPD_gp 0 /* BOD Operation in Power-Down Mode group position. */ -#define NVM_FUSES_BODPD0_bm (1<<0) /* BOD Operation in Power-Down Mode bit 0 mask. */ -#define NVM_FUSES_BODPD0_bp 0 /* BOD Operation in Power-Down Mode bit 0 position. */ -#define NVM_FUSES_BODPD1_bm (1<<1) /* BOD Operation in Power-Down Mode bit 1 mask. */ -#define NVM_FUSES_BODPD1_bp 1 /* BOD Operation in Power-Down Mode bit 1 position. */ - - -/* NVM_FUSES.FUSEBYTE4 bit masks and bit positions */ -#define NVM_FUSES_RSTDISBL_bm 0x10 /* External Reset Disable bit mask. */ -#define NVM_FUSES_RSTDISBL_bp 4 /* External Reset Disable bit position. */ - -#define NVM_FUSES_SUT_gm 0x0C /* Start-up Time group mask. */ -#define NVM_FUSES_SUT_gp 2 /* Start-up Time group position. */ -#define NVM_FUSES_SUT0_bm (1<<2) /* Start-up Time bit 0 mask. */ -#define NVM_FUSES_SUT0_bp 2 /* Start-up Time bit 0 position. */ -#define NVM_FUSES_SUT1_bm (1<<3) /* Start-up Time bit 1 mask. */ -#define NVM_FUSES_SUT1_bp 3 /* Start-up Time bit 1 position. */ - -#define NVM_FUSES_WDLOCK_bm 0x02 /* Watchdog Timer Lock bit mask. */ -#define NVM_FUSES_WDLOCK_bp 1 /* Watchdog Timer Lock bit position. */ - - -/* NVM_FUSES.FUSEBYTE5 bit masks and bit positions */ -#define NVM_FUSES_BODACT_gm 0x30 /* BOD Operation in Active Mode group mask. */ -#define NVM_FUSES_BODACT_gp 4 /* BOD Operation in Active Mode group position. */ -#define NVM_FUSES_BODACT0_bm (1<<4) /* BOD Operation in Active Mode bit 0 mask. */ -#define NVM_FUSES_BODACT0_bp 4 /* BOD Operation in Active Mode bit 0 position. */ -#define NVM_FUSES_BODACT1_bm (1<<5) /* BOD Operation in Active Mode bit 1 mask. */ -#define NVM_FUSES_BODACT1_bp 5 /* BOD Operation in Active Mode bit 1 position. */ - -#define NVM_FUSES_EESAVE_bm 0x08 /* Preserve EEPROM Through Chip Erase bit mask. */ -#define NVM_FUSES_EESAVE_bp 3 /* Preserve EEPROM Through Chip Erase bit position. */ - -#define NVM_FUSES_BODLVL_gm 0x07 /* Brown Out Detection Voltage Level group mask. */ -#define NVM_FUSES_BODLVL_gp 0 /* Brown Out Detection Voltage Level group position. */ -#define NVM_FUSES_BODLVL0_bm (1<<0) /* Brown Out Detection Voltage Level bit 0 mask. */ -#define NVM_FUSES_BODLVL0_bp 0 /* Brown Out Detection Voltage Level bit 0 position. */ -#define NVM_FUSES_BODLVL1_bm (1<<1) /* Brown Out Detection Voltage Level bit 1 mask. */ -#define NVM_FUSES_BODLVL1_bp 1 /* Brown Out Detection Voltage Level bit 1 position. */ -#define NVM_FUSES_BODLVL2_bm (1<<2) /* Brown Out Detection Voltage Level bit 2 mask. */ -#define NVM_FUSES_BODLVL2_bp 2 /* Brown Out Detection Voltage Level bit 2 position. */ - - -/* AC - Analog Comparator */ -/* AC.AC0CTRL bit masks and bit positions */ -#define AC_INTMODE_gm 0xC0 /* Interrupt Mode group mask. */ -#define AC_INTMODE_gp 6 /* Interrupt Mode group position. */ -#define AC_INTMODE0_bm (1<<6) /* Interrupt Mode bit 0 mask. */ -#define AC_INTMODE0_bp 6 /* Interrupt Mode bit 0 position. */ -#define AC_INTMODE1_bm (1<<7) /* Interrupt Mode bit 1 mask. */ -#define AC_INTMODE1_bp 7 /* Interrupt Mode bit 1 position. */ - -#define AC_INTLVL_gm 0x30 /* Interrupt Level group mask. */ -#define AC_INTLVL_gp 4 /* Interrupt Level group position. */ -#define AC_INTLVL0_bm (1<<4) /* Interrupt Level bit 0 mask. */ -#define AC_INTLVL0_bp 4 /* Interrupt Level bit 0 position. */ -#define AC_INTLVL1_bm (1<<5) /* Interrupt Level bit 1 mask. */ -#define AC_INTLVL1_bp 5 /* Interrupt Level bit 1 position. */ - -#define AC_HSMODE_bm 0x08 /* High-speed Mode bit mask. */ -#define AC_HSMODE_bp 3 /* High-speed Mode bit position. */ - -#define AC_HYSMODE_gm 0x06 /* Hysteresis Mode group mask. */ -#define AC_HYSMODE_gp 1 /* Hysteresis Mode group position. */ -#define AC_HYSMODE0_bm (1<<1) /* Hysteresis Mode bit 0 mask. */ -#define AC_HYSMODE0_bp 1 /* Hysteresis Mode bit 0 position. */ -#define AC_HYSMODE1_bm (1<<2) /* Hysteresis Mode bit 1 mask. */ -#define AC_HYSMODE1_bp 2 /* Hysteresis Mode bit 1 position. */ - -#define AC_ENABLE_bm 0x01 /* Enable bit mask. */ -#define AC_ENABLE_bp 0 /* Enable bit position. */ - - -/* AC.AC1CTRL bit masks and bit positions */ -/* AC_INTMODE_gm Predefined. */ -/* AC_INTMODE_gp Predefined. */ -/* AC_INTMODE0_bm Predefined. */ -/* AC_INTMODE0_bp Predefined. */ -/* AC_INTMODE1_bm Predefined. */ -/* AC_INTMODE1_bp Predefined. */ - -/* AC_INTLVL_gm Predefined. */ -/* AC_INTLVL_gp Predefined. */ -/* AC_INTLVL0_bm Predefined. */ -/* AC_INTLVL0_bp Predefined. */ -/* AC_INTLVL1_bm Predefined. */ -/* AC_INTLVL1_bp Predefined. */ - -/* AC_HSMODE_bm Predefined. */ -/* AC_HSMODE_bp Predefined. */ - -/* AC_HYSMODE_gm Predefined. */ -/* AC_HYSMODE_gp Predefined. */ -/* AC_HYSMODE0_bm Predefined. */ -/* AC_HYSMODE0_bp Predefined. */ -/* AC_HYSMODE1_bm Predefined. */ -/* AC_HYSMODE1_bp Predefined. */ - -/* AC_ENABLE_bm Predefined. */ -/* AC_ENABLE_bp Predefined. */ - - -/* AC.AC0MUXCTRL bit masks and bit positions */ -#define AC_MUXPOS_gm 0x38 /* MUX Positive Input group mask. */ -#define AC_MUXPOS_gp 3 /* MUX Positive Input group position. */ -#define AC_MUXPOS0_bm (1<<3) /* MUX Positive Input bit 0 mask. */ -#define AC_MUXPOS0_bp 3 /* MUX Positive Input bit 0 position. */ -#define AC_MUXPOS1_bm (1<<4) /* MUX Positive Input bit 1 mask. */ -#define AC_MUXPOS1_bp 4 /* MUX Positive Input bit 1 position. */ -#define AC_MUXPOS2_bm (1<<5) /* MUX Positive Input bit 2 mask. */ -#define AC_MUXPOS2_bp 5 /* MUX Positive Input bit 2 position. */ - -#define AC_MUXNEG_gm 0x07 /* MUX Negative Input group mask. */ -#define AC_MUXNEG_gp 0 /* MUX Negative Input group position. */ -#define AC_MUXNEG0_bm (1<<0) /* MUX Negative Input bit 0 mask. */ -#define AC_MUXNEG0_bp 0 /* MUX Negative Input bit 0 position. */ -#define AC_MUXNEG1_bm (1<<1) /* MUX Negative Input bit 1 mask. */ -#define AC_MUXNEG1_bp 1 /* MUX Negative Input bit 1 position. */ -#define AC_MUXNEG2_bm (1<<2) /* MUX Negative Input bit 2 mask. */ -#define AC_MUXNEG2_bp 2 /* MUX Negative Input bit 2 position. */ - - -/* AC.AC1MUXCTRL bit masks and bit positions */ -/* AC_MUXPOS_gm Predefined. */ -/* AC_MUXPOS_gp Predefined. */ -/* AC_MUXPOS0_bm Predefined. */ -/* AC_MUXPOS0_bp Predefined. */ -/* AC_MUXPOS1_bm Predefined. */ -/* AC_MUXPOS1_bp Predefined. */ -/* AC_MUXPOS2_bm Predefined. */ -/* AC_MUXPOS2_bp Predefined. */ - -/* AC_MUXNEG_gm Predefined. */ -/* AC_MUXNEG_gp Predefined. */ -/* AC_MUXNEG0_bm Predefined. */ -/* AC_MUXNEG0_bp Predefined. */ -/* AC_MUXNEG1_bm Predefined. */ -/* AC_MUXNEG1_bp Predefined. */ -/* AC_MUXNEG2_bm Predefined. */ -/* AC_MUXNEG2_bp Predefined. */ - - -/* AC.CTRLA bit masks and bit positions */ -#define AC_AC0OUT_bm 0x01 /* Comparator 0 Output Enable bit mask. */ -#define AC_AC0OUT_bp 0 /* Comparator 0 Output Enable bit position. */ - - -/* AC.CTRLB bit masks and bit positions */ -#define AC_SCALEFAC_gm 0x3F /* VCC Voltage Scaler Factor group mask. */ -#define AC_SCALEFAC_gp 0 /* VCC Voltage Scaler Factor group position. */ -#define AC_SCALEFAC0_bm (1<<0) /* VCC Voltage Scaler Factor bit 0 mask. */ -#define AC_SCALEFAC0_bp 0 /* VCC Voltage Scaler Factor bit 0 position. */ -#define AC_SCALEFAC1_bm (1<<1) /* VCC Voltage Scaler Factor bit 1 mask. */ -#define AC_SCALEFAC1_bp 1 /* VCC Voltage Scaler Factor bit 1 position. */ -#define AC_SCALEFAC2_bm (1<<2) /* VCC Voltage Scaler Factor bit 2 mask. */ -#define AC_SCALEFAC2_bp 2 /* VCC Voltage Scaler Factor bit 2 position. */ -#define AC_SCALEFAC3_bm (1<<3) /* VCC Voltage Scaler Factor bit 3 mask. */ -#define AC_SCALEFAC3_bp 3 /* VCC Voltage Scaler Factor bit 3 position. */ -#define AC_SCALEFAC4_bm (1<<4) /* VCC Voltage Scaler Factor bit 4 mask. */ -#define AC_SCALEFAC4_bp 4 /* VCC Voltage Scaler Factor bit 4 position. */ -#define AC_SCALEFAC5_bm (1<<5) /* VCC Voltage Scaler Factor bit 5 mask. */ -#define AC_SCALEFAC5_bp 5 /* VCC Voltage Scaler Factor bit 5 position. */ - - -/* AC.WINCTRL bit masks and bit positions */ -#define AC_WEN_bm 0x10 /* Window Mode Enable bit mask. */ -#define AC_WEN_bp 4 /* Window Mode Enable bit position. */ - -#define AC_WINTMODE_gm 0x0C /* Window Interrupt Mode group mask. */ -#define AC_WINTMODE_gp 2 /* Window Interrupt Mode group position. */ -#define AC_WINTMODE0_bm (1<<2) /* Window Interrupt Mode bit 0 mask. */ -#define AC_WINTMODE0_bp 2 /* Window Interrupt Mode bit 0 position. */ -#define AC_WINTMODE1_bm (1<<3) /* Window Interrupt Mode bit 1 mask. */ -#define AC_WINTMODE1_bp 3 /* Window Interrupt Mode bit 1 position. */ - -#define AC_WINTLVL_gm 0x03 /* Window Interrupt Level group mask. */ -#define AC_WINTLVL_gp 0 /* Window Interrupt Level group position. */ -#define AC_WINTLVL0_bm (1<<0) /* Window Interrupt Level bit 0 mask. */ -#define AC_WINTLVL0_bp 0 /* Window Interrupt Level bit 0 position. */ -#define AC_WINTLVL1_bm (1<<1) /* Window Interrupt Level bit 1 mask. */ -#define AC_WINTLVL1_bp 1 /* Window Interrupt Level bit 1 position. */ - - -/* AC.STATUS bit masks and bit positions */ -#define AC_WSTATE_gm 0xC0 /* Window Mode State group mask. */ -#define AC_WSTATE_gp 6 /* Window Mode State group position. */ -#define AC_WSTATE0_bm (1<<6) /* Window Mode State bit 0 mask. */ -#define AC_WSTATE0_bp 6 /* Window Mode State bit 0 position. */ -#define AC_WSTATE1_bm (1<<7) /* Window Mode State bit 1 mask. */ -#define AC_WSTATE1_bp 7 /* Window Mode State bit 1 position. */ - -#define AC_AC1STATE_bm 0x20 /* Comparator 1 State bit mask. */ -#define AC_AC1STATE_bp 5 /* Comparator 1 State bit position. */ - -#define AC_AC0STATE_bm 0x10 /* Comparator 0 State bit mask. */ -#define AC_AC0STATE_bp 4 /* Comparator 0 State bit position. */ - -#define AC_WIF_bm 0x04 /* Window Mode Interrupt Flag bit mask. */ -#define AC_WIF_bp 2 /* Window Mode Interrupt Flag bit position. */ - -#define AC_AC1IF_bm 0x02 /* Comparator 1 Interrupt Flag bit mask. */ -#define AC_AC1IF_bp 1 /* Comparator 1 Interrupt Flag bit position. */ - -#define AC_AC0IF_bm 0x01 /* Comparator 0 Interrupt Flag bit mask. */ -#define AC_AC0IF_bp 0 /* Comparator 0 Interrupt Flag bit position. */ - - -/* ADC - Analog/Digital Converter */ -/* ADC_CH.CTRL bit masks and bit positions */ -#define ADC_CH_START_bm 0x80 /* Channel Start Conversion bit mask. */ -#define ADC_CH_START_bp 7 /* Channel Start Conversion bit position. */ - -#define ADC_CH_GAINFAC_gm 0x1C /* Gain Factor group mask. */ -#define ADC_CH_GAINFAC_gp 2 /* Gain Factor group position. */ -#define ADC_CH_GAINFAC0_bm (1<<2) /* Gain Factor bit 0 mask. */ -#define ADC_CH_GAINFAC0_bp 2 /* Gain Factor bit 0 position. */ -#define ADC_CH_GAINFAC1_bm (1<<3) /* Gain Factor bit 1 mask. */ -#define ADC_CH_GAINFAC1_bp 3 /* Gain Factor bit 1 position. */ -#define ADC_CH_GAINFAC2_bm (1<<4) /* Gain Factor bit 2 mask. */ -#define ADC_CH_GAINFAC2_bp 4 /* Gain Factor bit 2 position. */ - -#define ADC_CH_INPUTMODE_gm 0x03 /* Input Mode Select group mask. */ -#define ADC_CH_INPUTMODE_gp 0 /* Input Mode Select group position. */ -#define ADC_CH_INPUTMODE0_bm (1<<0) /* Input Mode Select bit 0 mask. */ -#define ADC_CH_INPUTMODE0_bp 0 /* Input Mode Select bit 0 position. */ -#define ADC_CH_INPUTMODE1_bm (1<<1) /* Input Mode Select bit 1 mask. */ -#define ADC_CH_INPUTMODE1_bp 1 /* Input Mode Select bit 1 position. */ - - -/* ADC_CH.MUXCTRL bit masks and bit positions */ -#define ADC_CH_MUXPOS_gm 0x78 /* Positive Input Select group mask. */ -#define ADC_CH_MUXPOS_gp 3 /* Positive Input Select group position. */ -#define ADC_CH_MUXPOS0_bm (1<<3) /* Positive Input Select bit 0 mask. */ -#define ADC_CH_MUXPOS0_bp 3 /* Positive Input Select bit 0 position. */ -#define ADC_CH_MUXPOS1_bm (1<<4) /* Positive Input Select bit 1 mask. */ -#define ADC_CH_MUXPOS1_bp 4 /* Positive Input Select bit 1 position. */ -#define ADC_CH_MUXPOS2_bm (1<<5) /* Positive Input Select bit 2 mask. */ -#define ADC_CH_MUXPOS2_bp 5 /* Positive Input Select bit 2 position. */ -#define ADC_CH_MUXPOS3_bm (1<<6) /* Positive Input Select bit 3 mask. */ -#define ADC_CH_MUXPOS3_bp 6 /* Positive Input Select bit 3 position. */ - -#define ADC_CH_MUXNEG_gm 0x03 /* Negative Input Select group mask. */ -#define ADC_CH_MUXNEG_gp 0 /* Negative Input Select group position. */ -#define ADC_CH_MUXNEG0_bm (1<<0) /* Negative Input Select bit 0 mask. */ -#define ADC_CH_MUXNEG0_bp 0 /* Negative Input Select bit 0 position. */ -#define ADC_CH_MUXNEG1_bm (1<<1) /* Negative Input Select bit 1 mask. */ -#define ADC_CH_MUXNEG1_bp 1 /* Negative Input Select bit 1 position. */ - - -/* ADC_CH.INTCTRL bit masks and bit positions */ -#define ADC_CH_INTMODE_gm 0x0C /* Interrupt Mode group mask. */ -#define ADC_CH_INTMODE_gp 2 /* Interrupt Mode group position. */ -#define ADC_CH_INTMODE0_bm (1<<2) /* Interrupt Mode bit 0 mask. */ -#define ADC_CH_INTMODE0_bp 2 /* Interrupt Mode bit 0 position. */ -#define ADC_CH_INTMODE1_bm (1<<3) /* Interrupt Mode bit 1 mask. */ -#define ADC_CH_INTMODE1_bp 3 /* Interrupt Mode bit 1 position. */ - -#define ADC_CH_INTLVL_gm 0x03 /* Interrupt Level group mask. */ -#define ADC_CH_INTLVL_gp 0 /* Interrupt Level group position. */ -#define ADC_CH_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */ -#define ADC_CH_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */ -#define ADC_CH_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ -#define ADC_CH_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */ - - -/* ADC_CH.INTFLAGS bit masks and bit positions */ -#define ADC_CH_CHIF_bm 0x01 /* Channel Interrupt Flag bit mask. */ -#define ADC_CH_CHIF_bp 0 /* Channel Interrupt Flag bit position. */ - - -/* ADC.CTRLA bit masks and bit positions */ -#define ADC_CH0START_bm 0x04 /* Channel 0 Start Conversion bit mask. */ -#define ADC_CH0START_bp 2 /* Channel 0 Start Conversion bit position. */ - -#define ADC_FLUSH_bm 0x02 /* ADC Flush bit mask. */ -#define ADC_FLUSH_bp 1 /* ADC Flush bit position. */ - -#define ADC_ENABLE_bm 0x01 /* Enable ADC bit mask. */ -#define ADC_ENABLE_bp 0 /* Enable ADC bit position. */ - - -/* ADC.CTRLB bit masks and bit positions */ -#define ADC_CURRLIMIT_gm 0x60 /* Current Limitation group mask. */ -#define ADC_CURRLIMIT_gp 5 /* Current Limitation group position. */ -#define ADC_CURRLIMIT0_bm (1<<5) /* Current Limitation bit 0 mask. */ -#define ADC_CURRLIMIT0_bp 5 /* Current Limitation bit 0 position. */ -#define ADC_CURRLIMIT1_bm (1<<6) /* Current Limitation bit 1 mask. */ -#define ADC_CURRLIMIT1_bp 6 /* Current Limitation bit 1 position. */ - -#define ADC_CONMODE_bm 0x10 /* Conversion Mode bit mask. */ -#define ADC_CONMODE_bp 4 /* Conversion Mode bit position. */ - -#define ADC_FREERUN_bm 0x08 /* Free Running Mode Enable bit mask. */ -#define ADC_FREERUN_bp 3 /* Free Running Mode Enable bit position. */ - -#define ADC_RESOLUTION_gm 0x06 /* Result Resolution group mask. */ -#define ADC_RESOLUTION_gp 1 /* Result Resolution group position. */ -#define ADC_RESOLUTION0_bm (1<<1) /* Result Resolution bit 0 mask. */ -#define ADC_RESOLUTION0_bp 1 /* Result Resolution bit 0 position. */ -#define ADC_RESOLUTION1_bm (1<<2) /* Result Resolution bit 1 mask. */ -#define ADC_RESOLUTION1_bp 2 /* Result Resolution bit 1 position. */ - - -/* ADC.REFCTRL bit masks and bit positions */ -#define ADC_REFSEL_gm 0x70 /* Reference Selection group mask. */ -#define ADC_REFSEL_gp 4 /* Reference Selection group position. */ -#define ADC_REFSEL0_bm (1<<4) /* Reference Selection bit 0 mask. */ -#define ADC_REFSEL0_bp 4 /* Reference Selection bit 0 position. */ -#define ADC_REFSEL1_bm (1<<5) /* Reference Selection bit 1 mask. */ -#define ADC_REFSEL1_bp 5 /* Reference Selection bit 1 position. */ -#define ADC_REFSEL2_bm (1<<6) /* Reference Selection bit 2 mask. */ -#define ADC_REFSEL2_bp 6 /* Reference Selection bit 2 position. */ - -#define ADC_BANDGAP_bm 0x02 /* Bandgap enable bit mask. */ -#define ADC_BANDGAP_bp 1 /* Bandgap enable bit position. */ - -#define ADC_TEMPREF_bm 0x01 /* Temperature Reference Enable bit mask. */ -#define ADC_TEMPREF_bp 0 /* Temperature Reference Enable bit position. */ - - -/* ADC.EVCTRL bit masks and bit positions */ -#define ADC_EVSEL_gm 0x38 /* Event Input Select group mask. */ -#define ADC_EVSEL_gp 3 /* Event Input Select group position. */ -#define ADC_EVSEL0_bm (1<<3) /* Event Input Select bit 0 mask. */ -#define ADC_EVSEL0_bp 3 /* Event Input Select bit 0 position. */ -#define ADC_EVSEL1_bm (1<<4) /* Event Input Select bit 1 mask. */ -#define ADC_EVSEL1_bp 4 /* Event Input Select bit 1 position. */ -#define ADC_EVSEL2_bm (1<<5) /* Event Input Select bit 2 mask. */ -#define ADC_EVSEL2_bp 5 /* Event Input Select bit 2 position. */ - -#define ADC_EVACT_bm 0x01 /* Event Action Select bit mask. */ -#define ADC_EVACT_bp 0 /* Event Action Select bit position. */ - - -/* ADC.PRESCALER bit masks and bit positions */ -#define ADC_PRESCALER_gm 0x07 /* Clock Prescaler Selection group mask. */ -#define ADC_PRESCALER_gp 0 /* Clock Prescaler Selection group position. */ -#define ADC_PRESCALER0_bm (1<<0) /* Clock Prescaler Selection bit 0 mask. */ -#define ADC_PRESCALER0_bp 0 /* Clock Prescaler Selection bit 0 position. */ -#define ADC_PRESCALER1_bm (1<<1) /* Clock Prescaler Selection bit 1 mask. */ -#define ADC_PRESCALER1_bp 1 /* Clock Prescaler Selection bit 1 position. */ -#define ADC_PRESCALER2_bm (1<<2) /* Clock Prescaler Selection bit 2 mask. */ -#define ADC_PRESCALER2_bp 2 /* Clock Prescaler Selection bit 2 position. */ - - -/* ADC.INTFLAGS bit masks and bit positions */ -#define ADC_CH0IF_bm 0x01 /* Channel 0 Interrupt Flag bit mask. */ -#define ADC_CH0IF_bp 0 /* Channel 0 Interrupt Flag bit position. */ - - -/* RTC - Real-Time Clounter */ -/* RTC.CTRL bit masks and bit positions */ -#define RTC_PRESCALER_gm 0x07 /* Prescaling Factor group mask. */ -#define RTC_PRESCALER_gp 0 /* Prescaling Factor group position. */ -#define RTC_PRESCALER0_bm (1<<0) /* Prescaling Factor bit 0 mask. */ -#define RTC_PRESCALER0_bp 0 /* Prescaling Factor bit 0 position. */ -#define RTC_PRESCALER1_bm (1<<1) /* Prescaling Factor bit 1 mask. */ -#define RTC_PRESCALER1_bp 1 /* Prescaling Factor bit 1 position. */ -#define RTC_PRESCALER2_bm (1<<2) /* Prescaling Factor bit 2 mask. */ -#define RTC_PRESCALER2_bp 2 /* Prescaling Factor bit 2 position. */ - - -/* RTC.STATUS bit masks and bit positions */ -#define RTC_SYNCBUSY_bm 0x01 /* Synchronization Busy Flag bit mask. */ -#define RTC_SYNCBUSY_bp 0 /* Synchronization Busy Flag bit position. */ - - -/* RTC.INTCTRL bit masks and bit positions */ -#define RTC_COMPINTLVL_gm 0x0C /* Compare Match Interrupt Level group mask. */ -#define RTC_COMPINTLVL_gp 2 /* Compare Match Interrupt Level group position. */ -#define RTC_COMPINTLVL0_bm (1<<2) /* Compare Match Interrupt Level bit 0 mask. */ -#define RTC_COMPINTLVL0_bp 2 /* Compare Match Interrupt Level bit 0 position. */ -#define RTC_COMPINTLVL1_bm (1<<3) /* Compare Match Interrupt Level bit 1 mask. */ -#define RTC_COMPINTLVL1_bp 3 /* Compare Match Interrupt Level bit 1 position. */ - -#define RTC_OVFINTLVL_gm 0x03 /* Overflow Interrupt Level group mask. */ -#define RTC_OVFINTLVL_gp 0 /* Overflow Interrupt Level group position. */ -#define RTC_OVFINTLVL0_bm (1<<0) /* Overflow Interrupt Level bit 0 mask. */ -#define RTC_OVFINTLVL0_bp 0 /* Overflow Interrupt Level bit 0 position. */ -#define RTC_OVFINTLVL1_bm (1<<1) /* Overflow Interrupt Level bit 1 mask. */ -#define RTC_OVFINTLVL1_bp 1 /* Overflow Interrupt Level bit 1 position. */ - - -/* RTC.INTFLAGS bit masks and bit positions */ -#define RTC_COMPIF_bm 0x02 /* Compare Match Interrupt Flag bit mask. */ -#define RTC_COMPIF_bp 1 /* Compare Match Interrupt Flag bit position. */ - -#define RTC_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ -#define RTC_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ - - -/* EBI - External Bus Interface */ -/* EBI_CS.CTRLA bit masks and bit positions */ -#define EBI_CS_ASIZE_gm 0x7C /* Address Size group mask. */ -#define EBI_CS_ASIZE_gp 2 /* Address Size group position. */ -#define EBI_CS_ASIZE0_bm (1<<2) /* Address Size bit 0 mask. */ -#define EBI_CS_ASIZE0_bp 2 /* Address Size bit 0 position. */ -#define EBI_CS_ASIZE1_bm (1<<3) /* Address Size bit 1 mask. */ -#define EBI_CS_ASIZE1_bp 3 /* Address Size bit 1 position. */ -#define EBI_CS_ASIZE2_bm (1<<4) /* Address Size bit 2 mask. */ -#define EBI_CS_ASIZE2_bp 4 /* Address Size bit 2 position. */ -#define EBI_CS_ASIZE3_bm (1<<5) /* Address Size bit 3 mask. */ -#define EBI_CS_ASIZE3_bp 5 /* Address Size bit 3 position. */ -#define EBI_CS_ASIZE4_bm (1<<6) /* Address Size bit 4 mask. */ -#define EBI_CS_ASIZE4_bp 6 /* Address Size bit 4 position. */ - -#define EBI_CS_MODE_gm 0x03 /* Memory Mode group mask. */ -#define EBI_CS_MODE_gp 0 /* Memory Mode group position. */ -#define EBI_CS_MODE0_bm (1<<0) /* Memory Mode bit 0 mask. */ -#define EBI_CS_MODE0_bp 0 /* Memory Mode bit 0 position. */ -#define EBI_CS_MODE1_bm (1<<1) /* Memory Mode bit 1 mask. */ -#define EBI_CS_MODE1_bp 1 /* Memory Mode bit 1 position. */ - - -/* EBI_CS.CTRLB bit masks and bit positions */ -#define EBI_CS_SRWS_gm 0x07 /* SRAM Wait State Cycles group mask. */ -#define EBI_CS_SRWS_gp 0 /* SRAM Wait State Cycles group position. */ -#define EBI_CS_SRWS0_bm (1<<0) /* SRAM Wait State Cycles bit 0 mask. */ -#define EBI_CS_SRWS0_bp 0 /* SRAM Wait State Cycles bit 0 position. */ -#define EBI_CS_SRWS1_bm (1<<1) /* SRAM Wait State Cycles bit 1 mask. */ -#define EBI_CS_SRWS1_bp 1 /* SRAM Wait State Cycles bit 1 position. */ -#define EBI_CS_SRWS2_bm (1<<2) /* SRAM Wait State Cycles bit 2 mask. */ -#define EBI_CS_SRWS2_bp 2 /* SRAM Wait State Cycles bit 2 position. */ - -#define EBI_CS_SDINITDONE_bm 0x80 /* SDRAM Initialization Done bit mask. */ -#define EBI_CS_SDINITDONE_bp 7 /* SDRAM Initialization Done bit position. */ - -#define EBI_CS_SDSREN_bm 0x04 /* SDRAM Self-refresh Enable bit mask. */ -#define EBI_CS_SDSREN_bp 2 /* SDRAM Self-refresh Enable bit position. */ - -#define EBI_CS_SDMODE_gm 0x03 /* SDRAM Mode group mask. */ -#define EBI_CS_SDMODE_gp 0 /* SDRAM Mode group position. */ -#define EBI_CS_SDMODE0_bm (1<<0) /* SDRAM Mode bit 0 mask. */ -#define EBI_CS_SDMODE0_bp 0 /* SDRAM Mode bit 0 position. */ -#define EBI_CS_SDMODE1_bm (1<<1) /* SDRAM Mode bit 1 mask. */ -#define EBI_CS_SDMODE1_bp 1 /* SDRAM Mode bit 1 position. */ - - -/* EBI.CTRL bit masks and bit positions */ -#define EBI_SDDATAW_gm 0xC0 /* SDRAM Data Width Setting group mask. */ -#define EBI_SDDATAW_gp 6 /* SDRAM Data Width Setting group position. */ -#define EBI_SDDATAW0_bm (1<<6) /* SDRAM Data Width Setting bit 0 mask. */ -#define EBI_SDDATAW0_bp 6 /* SDRAM Data Width Setting bit 0 position. */ -#define EBI_SDDATAW1_bm (1<<7) /* SDRAM Data Width Setting bit 1 mask. */ -#define EBI_SDDATAW1_bp 7 /* SDRAM Data Width Setting bit 1 position. */ - -#define EBI_LPCMODE_gm 0x30 /* SRAM LPC Mode group mask. */ -#define EBI_LPCMODE_gp 4 /* SRAM LPC Mode group position. */ -#define EBI_LPCMODE0_bm (1<<4) /* SRAM LPC Mode bit 0 mask. */ -#define EBI_LPCMODE0_bp 4 /* SRAM LPC Mode bit 0 position. */ -#define EBI_LPCMODE1_bm (1<<5) /* SRAM LPC Mode bit 1 mask. */ -#define EBI_LPCMODE1_bp 5 /* SRAM LPC Mode bit 1 position. */ - -#define EBI_SRMODE_gm 0x0C /* SRAM Mode group mask. */ -#define EBI_SRMODE_gp 2 /* SRAM Mode group position. */ -#define EBI_SRMODE0_bm (1<<2) /* SRAM Mode bit 0 mask. */ -#define EBI_SRMODE0_bp 2 /* SRAM Mode bit 0 position. */ -#define EBI_SRMODE1_bm (1<<3) /* SRAM Mode bit 1 mask. */ -#define EBI_SRMODE1_bp 3 /* SRAM Mode bit 1 position. */ - -#define EBI_IFMODE_gm 0x03 /* Interface Mode group mask. */ -#define EBI_IFMODE_gp 0 /* Interface Mode group position. */ -#define EBI_IFMODE0_bm (1<<0) /* Interface Mode bit 0 mask. */ -#define EBI_IFMODE0_bp 0 /* Interface Mode bit 0 position. */ -#define EBI_IFMODE1_bm (1<<1) /* Interface Mode bit 1 mask. */ -#define EBI_IFMODE1_bp 1 /* Interface Mode bit 1 position. */ - - -/* EBI.SDRAMCTRLA bit masks and bit positions */ -#define EBI_SDCAS_bm 0x08 /* SDRAM CAS Latency Setting bit mask. */ -#define EBI_SDCAS_bp 3 /* SDRAM CAS Latency Setting bit position. */ - -#define EBI_SDROW_bm 0x04 /* SDRAM ROW Bits Setting bit mask. */ -#define EBI_SDROW_bp 2 /* SDRAM ROW Bits Setting bit position. */ - -#define EBI_SDCOL_gm 0x03 /* SDRAM Column Bits Setting group mask. */ -#define EBI_SDCOL_gp 0 /* SDRAM Column Bits Setting group position. */ -#define EBI_SDCOL0_bm (1<<0) /* SDRAM Column Bits Setting bit 0 mask. */ -#define EBI_SDCOL0_bp 0 /* SDRAM Column Bits Setting bit 0 position. */ -#define EBI_SDCOL1_bm (1<<1) /* SDRAM Column Bits Setting bit 1 mask. */ -#define EBI_SDCOL1_bp 1 /* SDRAM Column Bits Setting bit 1 position. */ - - -/* EBI.SDRAMCTRLB bit masks and bit positions */ -#define EBI_MRDLY_gm 0xC0 /* SDRAM Mode Register Delay group mask. */ -#define EBI_MRDLY_gp 6 /* SDRAM Mode Register Delay group position. */ -#define EBI_MRDLY0_bm (1<<6) /* SDRAM Mode Register Delay bit 0 mask. */ -#define EBI_MRDLY0_bp 6 /* SDRAM Mode Register Delay bit 0 position. */ -#define EBI_MRDLY1_bm (1<<7) /* SDRAM Mode Register Delay bit 1 mask. */ -#define EBI_MRDLY1_bp 7 /* SDRAM Mode Register Delay bit 1 position. */ - -#define EBI_ROWCYCDLY_gm 0x38 /* SDRAM Row Cycle Delay group mask. */ -#define EBI_ROWCYCDLY_gp 3 /* SDRAM Row Cycle Delay group position. */ -#define EBI_ROWCYCDLY0_bm (1<<3) /* SDRAM Row Cycle Delay bit 0 mask. */ -#define EBI_ROWCYCDLY0_bp 3 /* SDRAM Row Cycle Delay bit 0 position. */ -#define EBI_ROWCYCDLY1_bm (1<<4) /* SDRAM Row Cycle Delay bit 1 mask. */ -#define EBI_ROWCYCDLY1_bp 4 /* SDRAM Row Cycle Delay bit 1 position. */ -#define EBI_ROWCYCDLY2_bm (1<<5) /* SDRAM Row Cycle Delay bit 2 mask. */ -#define EBI_ROWCYCDLY2_bp 5 /* SDRAM Row Cycle Delay bit 2 position. */ - -#define EBI_RPDLY_gm 0x07 /* SDRAM Row-to-Precharge Delay group mask. */ -#define EBI_RPDLY_gp 0 /* SDRAM Row-to-Precharge Delay group position. */ -#define EBI_RPDLY0_bm (1<<0) /* SDRAM Row-to-Precharge Delay bit 0 mask. */ -#define EBI_RPDLY0_bp 0 /* SDRAM Row-to-Precharge Delay bit 0 position. */ -#define EBI_RPDLY1_bm (1<<1) /* SDRAM Row-to-Precharge Delay bit 1 mask. */ -#define EBI_RPDLY1_bp 1 /* SDRAM Row-to-Precharge Delay bit 1 position. */ -#define EBI_RPDLY2_bm (1<<2) /* SDRAM Row-to-Precharge Delay bit 2 mask. */ -#define EBI_RPDLY2_bp 2 /* SDRAM Row-to-Precharge Delay bit 2 position. */ - - -/* EBI.SDRAMCTRLC bit masks and bit positions */ -#define EBI_WRDLY_gm 0xC0 /* SDRAM Write Recovery Delay group mask. */ -#define EBI_WRDLY_gp 6 /* SDRAM Write Recovery Delay group position. */ -#define EBI_WRDLY0_bm (1<<6) /* SDRAM Write Recovery Delay bit 0 mask. */ -#define EBI_WRDLY0_bp 6 /* SDRAM Write Recovery Delay bit 0 position. */ -#define EBI_WRDLY1_bm (1<<7) /* SDRAM Write Recovery Delay bit 1 mask. */ -#define EBI_WRDLY1_bp 7 /* SDRAM Write Recovery Delay bit 1 position. */ - -#define EBI_ESRDLY_gm 0x38 /* SDRAM Exit-Self-refresh-to-Active Delay group mask. */ -#define EBI_ESRDLY_gp 3 /* SDRAM Exit-Self-refresh-to-Active Delay group position. */ -#define EBI_ESRDLY0_bm (1<<3) /* SDRAM Exit-Self-refresh-to-Active Delay bit 0 mask. */ -#define EBI_ESRDLY0_bp 3 /* SDRAM Exit-Self-refresh-to-Active Delay bit 0 position. */ -#define EBI_ESRDLY1_bm (1<<4) /* SDRAM Exit-Self-refresh-to-Active Delay bit 1 mask. */ -#define EBI_ESRDLY1_bp 4 /* SDRAM Exit-Self-refresh-to-Active Delay bit 1 position. */ -#define EBI_ESRDLY2_bm (1<<5) /* SDRAM Exit-Self-refresh-to-Active Delay bit 2 mask. */ -#define EBI_ESRDLY2_bp 5 /* SDRAM Exit-Self-refresh-to-Active Delay bit 2 position. */ - -#define EBI_ROWCOLDLY_gm 0x07 /* SDRAM Row-to-Column Delay group mask. */ -#define EBI_ROWCOLDLY_gp 0 /* SDRAM Row-to-Column Delay group position. */ -#define EBI_ROWCOLDLY0_bm (1<<0) /* SDRAM Row-to-Column Delay bit 0 mask. */ -#define EBI_ROWCOLDLY0_bp 0 /* SDRAM Row-to-Column Delay bit 0 position. */ -#define EBI_ROWCOLDLY1_bm (1<<1) /* SDRAM Row-to-Column Delay bit 1 mask. */ -#define EBI_ROWCOLDLY1_bp 1 /* SDRAM Row-to-Column Delay bit 1 position. */ -#define EBI_ROWCOLDLY2_bm (1<<2) /* SDRAM Row-to-Column Delay bit 2 mask. */ -#define EBI_ROWCOLDLY2_bp 2 /* SDRAM Row-to-Column Delay bit 2 position. */ - - -/* TWI - Two-Wire Interface */ -/* TWI_MASTER.CTRLA bit masks and bit positions */ -#define TWI_MASTER_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ -#define TWI_MASTER_INTLVL_gp 6 /* Interrupt Level group position. */ -#define TWI_MASTER_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ -#define TWI_MASTER_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ -#define TWI_MASTER_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ -#define TWI_MASTER_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ - -#define TWI_MASTER_RIEN_bm 0x20 /* Read Interrupt Enable bit mask. */ -#define TWI_MASTER_RIEN_bp 5 /* Read Interrupt Enable bit position. */ - -#define TWI_MASTER_WIEN_bm 0x10 /* Write Interrupt Enable bit mask. */ -#define TWI_MASTER_WIEN_bp 4 /* Write Interrupt Enable bit position. */ - -#define TWI_MASTER_ENABLE_bm 0x08 /* Enable TWI Master bit mask. */ -#define TWI_MASTER_ENABLE_bp 3 /* Enable TWI Master bit position. */ - - -/* TWI_MASTER.CTRLB bit masks and bit positions */ -#define TWI_MASTER_TIMEOUT_gm 0x0C /* Inactive Bus Timeout group mask. */ -#define TWI_MASTER_TIMEOUT_gp 2 /* Inactive Bus Timeout group position. */ -#define TWI_MASTER_TIMEOUT0_bm (1<<2) /* Inactive Bus Timeout bit 0 mask. */ -#define TWI_MASTER_TIMEOUT0_bp 2 /* Inactive Bus Timeout bit 0 position. */ -#define TWI_MASTER_TIMEOUT1_bm (1<<3) /* Inactive Bus Timeout bit 1 mask. */ -#define TWI_MASTER_TIMEOUT1_bp 3 /* Inactive Bus Timeout bit 1 position. */ - -#define TWI_MASTER_QCEN_bm 0x02 /* Quick Command Enable bit mask. */ -#define TWI_MASTER_QCEN_bp 1 /* Quick Command Enable bit position. */ - -#define TWI_MASTER_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ -#define TWI_MASTER_SMEN_bp 0 /* Smart Mode Enable bit position. */ - - -/* TWI_MASTER.CTRLC bit masks and bit positions */ -#define TWI_MASTER_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ -#define TWI_MASTER_ACKACT_bp 2 /* Acknowledge Action bit position. */ - -#define TWI_MASTER_CMD_gm 0x03 /* Command group mask. */ -#define TWI_MASTER_CMD_gp 0 /* Command group position. */ -#define TWI_MASTER_CMD0_bm (1<<0) /* Command bit 0 mask. */ -#define TWI_MASTER_CMD0_bp 0 /* Command bit 0 position. */ -#define TWI_MASTER_CMD1_bm (1<<1) /* Command bit 1 mask. */ -#define TWI_MASTER_CMD1_bp 1 /* Command bit 1 position. */ - - -/* TWI_MASTER.STATUS bit masks and bit positions */ -#define TWI_MASTER_RIF_bm 0x80 /* Read Interrupt Flag bit mask. */ -#define TWI_MASTER_RIF_bp 7 /* Read Interrupt Flag bit position. */ - -#define TWI_MASTER_WIF_bm 0x40 /* Write Interrupt Flag bit mask. */ -#define TWI_MASTER_WIF_bp 6 /* Write Interrupt Flag bit position. */ - -#define TWI_MASTER_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ -#define TWI_MASTER_CLKHOLD_bp 5 /* Clock Hold bit position. */ - -#define TWI_MASTER_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ -#define TWI_MASTER_RXACK_bp 4 /* Received Acknowledge bit position. */ - -#define TWI_MASTER_ARBLOST_bm 0x08 /* Arbitration Lost bit mask. */ -#define TWI_MASTER_ARBLOST_bp 3 /* Arbitration Lost bit position. */ - -#define TWI_MASTER_BUSERR_bm 0x04 /* Bus Error bit mask. */ -#define TWI_MASTER_BUSERR_bp 2 /* Bus Error bit position. */ - -#define TWI_MASTER_BUSSTATE_gm 0x03 /* Bus State group mask. */ -#define TWI_MASTER_BUSSTATE_gp 0 /* Bus State group position. */ -#define TWI_MASTER_BUSSTATE0_bm (1<<0) /* Bus State bit 0 mask. */ -#define TWI_MASTER_BUSSTATE0_bp 0 /* Bus State bit 0 position. */ -#define TWI_MASTER_BUSSTATE1_bm (1<<1) /* Bus State bit 1 mask. */ -#define TWI_MASTER_BUSSTATE1_bp 1 /* Bus State bit 1 position. */ - - -/* TWI_SLAVE.CTRLA bit masks and bit positions */ -#define TWI_SLAVE_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ -#define TWI_SLAVE_INTLVL_gp 6 /* Interrupt Level group position. */ -#define TWI_SLAVE_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ -#define TWI_SLAVE_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ -#define TWI_SLAVE_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ -#define TWI_SLAVE_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ - -#define TWI_SLAVE_DIEN_bm 0x20 /* Data Interrupt Enable bit mask. */ -#define TWI_SLAVE_DIEN_bp 5 /* Data Interrupt Enable bit position. */ - -#define TWI_SLAVE_APIEN_bm 0x10 /* Address/Stop Interrupt Enable bit mask. */ -#define TWI_SLAVE_APIEN_bp 4 /* Address/Stop Interrupt Enable bit position. */ - -#define TWI_SLAVE_ENABLE_bm 0x08 /* Enable TWI Slave bit mask. */ -#define TWI_SLAVE_ENABLE_bp 3 /* Enable TWI Slave bit position. */ - -#define TWI_SLAVE_PIEN_bm 0x04 /* Stop Interrupt Enable bit mask. */ -#define TWI_SLAVE_PIEN_bp 2 /* Stop Interrupt Enable bit position. */ - -#define TWI_SLAVE_PMEN_bm 0x02 /* Promiscuous Mode Enable bit mask. */ -#define TWI_SLAVE_PMEN_bp 1 /* Promiscuous Mode Enable bit position. */ - -#define TWI_SLAVE_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ -#define TWI_SLAVE_SMEN_bp 0 /* Smart Mode Enable bit position. */ - - -/* TWI_SLAVE.CTRLB bit masks and bit positions */ -#define TWI_SLAVE_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ -#define TWI_SLAVE_ACKACT_bp 2 /* Acknowledge Action bit position. */ - -#define TWI_SLAVE_CMD_gm 0x03 /* Command group mask. */ -#define TWI_SLAVE_CMD_gp 0 /* Command group position. */ -#define TWI_SLAVE_CMD0_bm (1<<0) /* Command bit 0 mask. */ -#define TWI_SLAVE_CMD0_bp 0 /* Command bit 0 position. */ -#define TWI_SLAVE_CMD1_bm (1<<1) /* Command bit 1 mask. */ -#define TWI_SLAVE_CMD1_bp 1 /* Command bit 1 position. */ - - -/* TWI_SLAVE.STATUS bit masks and bit positions */ -#define TWI_SLAVE_DIF_bm 0x80 /* Data Interrupt Flag bit mask. */ -#define TWI_SLAVE_DIF_bp 7 /* Data Interrupt Flag bit position. */ - -#define TWI_SLAVE_APIF_bm 0x40 /* Address/Stop Interrupt Flag bit mask. */ -#define TWI_SLAVE_APIF_bp 6 /* Address/Stop Interrupt Flag bit position. */ - -#define TWI_SLAVE_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ -#define TWI_SLAVE_CLKHOLD_bp 5 /* Clock Hold bit position. */ - -#define TWI_SLAVE_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ -#define TWI_SLAVE_RXACK_bp 4 /* Received Acknowledge bit position. */ - -#define TWI_SLAVE_COLL_bm 0x08 /* Collision bit mask. */ -#define TWI_SLAVE_COLL_bp 3 /* Collision bit position. */ - -#define TWI_SLAVE_BUSERR_bm 0x04 /* Bus Error bit mask. */ -#define TWI_SLAVE_BUSERR_bp 2 /* Bus Error bit position. */ - -#define TWI_SLAVE_DIR_bm 0x02 /* Read/Write Direction bit mask. */ -#define TWI_SLAVE_DIR_bp 1 /* Read/Write Direction bit position. */ - -#define TWI_SLAVE_AP_bm 0x01 /* Slave Address or Stop bit mask. */ -#define TWI_SLAVE_AP_bp 0 /* Slave Address or Stop bit position. */ - - -/* TWI_SLAVE.ADDRMASK bit masks and bit positions */ -#define TWI_SLAVE_ADDRMASK_gm 0xFE /* Address Mask group mask. */ -#define TWI_SLAVE_ADDRMASK_gp 1 /* Address Mask group position. */ -#define TWI_SLAVE_ADDRMASK0_bm (1<<1) /* Address Mask bit 0 mask. */ -#define TWI_SLAVE_ADDRMASK0_bp 1 /* Address Mask bit 0 position. */ -#define TWI_SLAVE_ADDRMASK1_bm (1<<2) /* Address Mask bit 1 mask. */ -#define TWI_SLAVE_ADDRMASK1_bp 2 /* Address Mask bit 1 position. */ -#define TWI_SLAVE_ADDRMASK2_bm (1<<3) /* Address Mask bit 2 mask. */ -#define TWI_SLAVE_ADDRMASK2_bp 3 /* Address Mask bit 2 position. */ -#define TWI_SLAVE_ADDRMASK3_bm (1<<4) /* Address Mask bit 3 mask. */ -#define TWI_SLAVE_ADDRMASK3_bp 4 /* Address Mask bit 3 position. */ -#define TWI_SLAVE_ADDRMASK4_bm (1<<5) /* Address Mask bit 4 mask. */ -#define TWI_SLAVE_ADDRMASK4_bp 5 /* Address Mask bit 4 position. */ -#define TWI_SLAVE_ADDRMASK5_bm (1<<6) /* Address Mask bit 5 mask. */ -#define TWI_SLAVE_ADDRMASK5_bp 6 /* Address Mask bit 5 position. */ -#define TWI_SLAVE_ADDRMASK6_bm (1<<7) /* Address Mask bit 6 mask. */ -#define TWI_SLAVE_ADDRMASK6_bp 7 /* Address Mask bit 6 position. */ - -#define TWI_SLAVE_ADDREN_bm 0x01 /* Address Enable bit mask. */ -#define TWI_SLAVE_ADDREN_bp 0 /* Address Enable bit position. */ - - -/* TWI.CTRL bit masks and bit positions */ -#define TWI_SDAHOLD_bm 0x02 /* SDA Hold Time Enable bit mask. */ -#define TWI_SDAHOLD_bp 1 /* SDA Hold Time Enable bit position. */ - -#define TWI_EDIEN_bm 0x01 /* External Driver Interface Enable bit mask. */ -#define TWI_EDIEN_bp 0 /* External Driver Interface Enable bit position. */ - - -/* PORT - Port Configuration */ -/* PORTCFG.VPCTRLA bit masks and bit positions */ -#define PORTCFG_VP1MAP_gm 0xF0 /* Virtual Port 1 Mapping group mask. */ -#define PORTCFG_VP1MAP_gp 4 /* Virtual Port 1 Mapping group position. */ -#define PORTCFG_VP1MAP0_bm (1<<4) /* Virtual Port 1 Mapping bit 0 mask. */ -#define PORTCFG_VP1MAP0_bp 4 /* Virtual Port 1 Mapping bit 0 position. */ -#define PORTCFG_VP1MAP1_bm (1<<5) /* Virtual Port 1 Mapping bit 1 mask. */ -#define PORTCFG_VP1MAP1_bp 5 /* Virtual Port 1 Mapping bit 1 position. */ -#define PORTCFG_VP1MAP2_bm (1<<6) /* Virtual Port 1 Mapping bit 2 mask. */ -#define PORTCFG_VP1MAP2_bp 6 /* Virtual Port 1 Mapping bit 2 position. */ -#define PORTCFG_VP1MAP3_bm (1<<7) /* Virtual Port 1 Mapping bit 3 mask. */ -#define PORTCFG_VP1MAP3_bp 7 /* Virtual Port 1 Mapping bit 3 position. */ - -#define PORTCFG_VP0MAP_gm 0x0F /* Virtual Port 0 Mapping group mask. */ -#define PORTCFG_VP0MAP_gp 0 /* Virtual Port 0 Mapping group position. */ -#define PORTCFG_VP0MAP0_bm (1<<0) /* Virtual Port 0 Mapping bit 0 mask. */ -#define PORTCFG_VP0MAP0_bp 0 /* Virtual Port 0 Mapping bit 0 position. */ -#define PORTCFG_VP0MAP1_bm (1<<1) /* Virtual Port 0 Mapping bit 1 mask. */ -#define PORTCFG_VP0MAP1_bp 1 /* Virtual Port 0 Mapping bit 1 position. */ -#define PORTCFG_VP0MAP2_bm (1<<2) /* Virtual Port 0 Mapping bit 2 mask. */ -#define PORTCFG_VP0MAP2_bp 2 /* Virtual Port 0 Mapping bit 2 position. */ -#define PORTCFG_VP0MAP3_bm (1<<3) /* Virtual Port 0 Mapping bit 3 mask. */ -#define PORTCFG_VP0MAP3_bp 3 /* Virtual Port 0 Mapping bit 3 position. */ - - -/* PORTCFG.VPCTRLB bit masks and bit positions */ -#define PORTCFG_VP3MAP_gm 0xF0 /* Virtual Port 3 Mapping group mask. */ -#define PORTCFG_VP3MAP_gp 4 /* Virtual Port 3 Mapping group position. */ -#define PORTCFG_VP3MAP0_bm (1<<4) /* Virtual Port 3 Mapping bit 0 mask. */ -#define PORTCFG_VP3MAP0_bp 4 /* Virtual Port 3 Mapping bit 0 position. */ -#define PORTCFG_VP3MAP1_bm (1<<5) /* Virtual Port 3 Mapping bit 1 mask. */ -#define PORTCFG_VP3MAP1_bp 5 /* Virtual Port 3 Mapping bit 1 position. */ -#define PORTCFG_VP3MAP2_bm (1<<6) /* Virtual Port 3 Mapping bit 2 mask. */ -#define PORTCFG_VP3MAP2_bp 6 /* Virtual Port 3 Mapping bit 2 position. */ -#define PORTCFG_VP3MAP3_bm (1<<7) /* Virtual Port 3 Mapping bit 3 mask. */ -#define PORTCFG_VP3MAP3_bp 7 /* Virtual Port 3 Mapping bit 3 position. */ - -#define PORTCFG_VP2MAP_gm 0x0F /* Virtual Port 2 Mapping group mask. */ -#define PORTCFG_VP2MAP_gp 0 /* Virtual Port 2 Mapping group position. */ -#define PORTCFG_VP2MAP0_bm (1<<0) /* Virtual Port 2 Mapping bit 0 mask. */ -#define PORTCFG_VP2MAP0_bp 0 /* Virtual Port 2 Mapping bit 0 position. */ -#define PORTCFG_VP2MAP1_bm (1<<1) /* Virtual Port 2 Mapping bit 1 mask. */ -#define PORTCFG_VP2MAP1_bp 1 /* Virtual Port 2 Mapping bit 1 position. */ -#define PORTCFG_VP2MAP2_bm (1<<2) /* Virtual Port 2 Mapping bit 2 mask. */ -#define PORTCFG_VP2MAP2_bp 2 /* Virtual Port 2 Mapping bit 2 position. */ -#define PORTCFG_VP2MAP3_bm (1<<3) /* Virtual Port 2 Mapping bit 3 mask. */ -#define PORTCFG_VP2MAP3_bp 3 /* Virtual Port 2 Mapping bit 3 position. */ - - -/* PORTCFG.CLKEVOUT bit masks and bit positions */ -#define PORTCFG_CLKOUT_gm 0x03 /* Clock Output Port group mask. */ -#define PORTCFG_CLKOUT_gp 0 /* Clock Output Port group position. */ -#define PORTCFG_CLKOUT0_bm (1<<0) /* Clock Output Port bit 0 mask. */ -#define PORTCFG_CLKOUT0_bp 0 /* Clock Output Port bit 0 position. */ -#define PORTCFG_CLKOUT1_bm (1<<1) /* Clock Output Port bit 1 mask. */ -#define PORTCFG_CLKOUT1_bp 1 /* Clock Output Port bit 1 position. */ - -#define PORTCFG_EVOUT_gm 0x30 /* Event Output Port group mask. */ -#define PORTCFG_EVOUT_gp 4 /* Event Output Port group position. */ -#define PORTCFG_EVOUT0_bm (1<<4) /* Event Output Port bit 0 mask. */ -#define PORTCFG_EVOUT0_bp 4 /* Event Output Port bit 0 position. */ -#define PORTCFG_EVOUT1_bm (1<<5) /* Event Output Port bit 1 mask. */ -#define PORTCFG_EVOUT1_bp 5 /* Event Output Port bit 1 position. */ - - -/* VPORT.INTFLAGS bit masks and bit positions */ -#define VPORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ -#define VPORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ - -#define VPORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ -#define VPORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ - - -/* PORT.INTCTRL bit masks and bit positions */ -#define PORT_INT1LVL_gm 0x0C /* Port Interrupt 1 Level group mask. */ -#define PORT_INT1LVL_gp 2 /* Port Interrupt 1 Level group position. */ -#define PORT_INT1LVL0_bm (1<<2) /* Port Interrupt 1 Level bit 0 mask. */ -#define PORT_INT1LVL0_bp 2 /* Port Interrupt 1 Level bit 0 position. */ -#define PORT_INT1LVL1_bm (1<<3) /* Port Interrupt 1 Level bit 1 mask. */ -#define PORT_INT1LVL1_bp 3 /* Port Interrupt 1 Level bit 1 position. */ - -#define PORT_INT0LVL_gm 0x03 /* Port Interrupt 0 Level group mask. */ -#define PORT_INT0LVL_gp 0 /* Port Interrupt 0 Level group position. */ -#define PORT_INT0LVL0_bm (1<<0) /* Port Interrupt 0 Level bit 0 mask. */ -#define PORT_INT0LVL0_bp 0 /* Port Interrupt 0 Level bit 0 position. */ -#define PORT_INT0LVL1_bm (1<<1) /* Port Interrupt 0 Level bit 1 mask. */ -#define PORT_INT0LVL1_bp 1 /* Port Interrupt 0 Level bit 1 position. */ - - -/* PORT.INTFLAGS bit masks and bit positions */ -#define PORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ -#define PORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ - -#define PORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ -#define PORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ - - -/* PORT.PIN0CTRL bit masks and bit positions */ -#define PORT_SRLEN_bm 0x80 /* Slew Rate Enable bit mask. */ -#define PORT_SRLEN_bp 7 /* Slew Rate Enable bit position. */ - -#define PORT_INVEN_bm 0x40 /* Inverted I/O Enable bit mask. */ -#define PORT_INVEN_bp 6 /* Inverted I/O Enable bit position. */ - -#define PORT_OPC_gm 0x38 /* Output/Pull Configuration group mask. */ -#define PORT_OPC_gp 3 /* Output/Pull Configuration group position. */ -#define PORT_OPC0_bm (1<<3) /* Output/Pull Configuration bit 0 mask. */ -#define PORT_OPC0_bp 3 /* Output/Pull Configuration bit 0 position. */ -#define PORT_OPC1_bm (1<<4) /* Output/Pull Configuration bit 1 mask. */ -#define PORT_OPC1_bp 4 /* Output/Pull Configuration bit 1 position. */ -#define PORT_OPC2_bm (1<<5) /* Output/Pull Configuration bit 2 mask. */ -#define PORT_OPC2_bp 5 /* Output/Pull Configuration bit 2 position. */ - -#define PORT_ISC_gm 0x07 /* Input/Sense Configuration group mask. */ -#define PORT_ISC_gp 0 /* Input/Sense Configuration group position. */ -#define PORT_ISC0_bm (1<<0) /* Input/Sense Configuration bit 0 mask. */ -#define PORT_ISC0_bp 0 /* Input/Sense Configuration bit 0 position. */ -#define PORT_ISC1_bm (1<<1) /* Input/Sense Configuration bit 1 mask. */ -#define PORT_ISC1_bp 1 /* Input/Sense Configuration bit 1 position. */ -#define PORT_ISC2_bm (1<<2) /* Input/Sense Configuration bit 2 mask. */ -#define PORT_ISC2_bp 2 /* Input/Sense Configuration bit 2 position. */ - - -/* PORT.PIN1CTRL bit masks and bit positions */ -/* PORT_SRLEN_bm Predefined. */ -/* PORT_SRLEN_bp Predefined. */ - -/* PORT_INVEN_bm Predefined. */ -/* PORT_INVEN_bp Predefined. */ - -/* PORT_OPC_gm Predefined. */ -/* PORT_OPC_gp Predefined. */ -/* PORT_OPC0_bm Predefined. */ -/* PORT_OPC0_bp Predefined. */ -/* PORT_OPC1_bm Predefined. */ -/* PORT_OPC1_bp Predefined. */ -/* PORT_OPC2_bm Predefined. */ -/* PORT_OPC2_bp Predefined. */ - -/* PORT_ISC_gm Predefined. */ -/* PORT_ISC_gp Predefined. */ -/* PORT_ISC0_bm Predefined. */ -/* PORT_ISC0_bp Predefined. */ -/* PORT_ISC1_bm Predefined. */ -/* PORT_ISC1_bp Predefined. */ -/* PORT_ISC2_bm Predefined. */ -/* PORT_ISC2_bp Predefined. */ - - -/* PORT.PIN2CTRL bit masks and bit positions */ -/* PORT_SRLEN_bm Predefined. */ -/* PORT_SRLEN_bp Predefined. */ - -/* PORT_INVEN_bm Predefined. */ -/* PORT_INVEN_bp Predefined. */ - -/* PORT_OPC_gm Predefined. */ -/* PORT_OPC_gp Predefined. */ -/* PORT_OPC0_bm Predefined. */ -/* PORT_OPC0_bp Predefined. */ -/* PORT_OPC1_bm Predefined. */ -/* PORT_OPC1_bp Predefined. */ -/* PORT_OPC2_bm Predefined. */ -/* PORT_OPC2_bp Predefined. */ - -/* PORT_ISC_gm Predefined. */ -/* PORT_ISC_gp Predefined. */ -/* PORT_ISC0_bm Predefined. */ -/* PORT_ISC0_bp Predefined. */ -/* PORT_ISC1_bm Predefined. */ -/* PORT_ISC1_bp Predefined. */ -/* PORT_ISC2_bm Predefined. */ -/* PORT_ISC2_bp Predefined. */ - - -/* PORT.PIN3CTRL bit masks and bit positions */ -/* PORT_SRLEN_bm Predefined. */ -/* PORT_SRLEN_bp Predefined. */ - -/* PORT_INVEN_bm Predefined. */ -/* PORT_INVEN_bp Predefined. */ - -/* PORT_OPC_gm Predefined. */ -/* PORT_OPC_gp Predefined. */ -/* PORT_OPC0_bm Predefined. */ -/* PORT_OPC0_bp Predefined. */ -/* PORT_OPC1_bm Predefined. */ -/* PORT_OPC1_bp Predefined. */ -/* PORT_OPC2_bm Predefined. */ -/* PORT_OPC2_bp Predefined. */ - -/* PORT_ISC_gm Predefined. */ -/* PORT_ISC_gp Predefined. */ -/* PORT_ISC0_bm Predefined. */ -/* PORT_ISC0_bp Predefined. */ -/* PORT_ISC1_bm Predefined. */ -/* PORT_ISC1_bp Predefined. */ -/* PORT_ISC2_bm Predefined. */ -/* PORT_ISC2_bp Predefined. */ - - -/* PORT.PIN4CTRL bit masks and bit positions */ -/* PORT_SRLEN_bm Predefined. */ -/* PORT_SRLEN_bp Predefined. */ - -/* PORT_INVEN_bm Predefined. */ -/* PORT_INVEN_bp Predefined. */ - -/* PORT_OPC_gm Predefined. */ -/* PORT_OPC_gp Predefined. */ -/* PORT_OPC0_bm Predefined. */ -/* PORT_OPC0_bp Predefined. */ -/* PORT_OPC1_bm Predefined. */ -/* PORT_OPC1_bp Predefined. */ -/* PORT_OPC2_bm Predefined. */ -/* PORT_OPC2_bp Predefined. */ - -/* PORT_ISC_gm Predefined. */ -/* PORT_ISC_gp Predefined. */ -/* PORT_ISC0_bm Predefined. */ -/* PORT_ISC0_bp Predefined. */ -/* PORT_ISC1_bm Predefined. */ -/* PORT_ISC1_bp Predefined. */ -/* PORT_ISC2_bm Predefined. */ -/* PORT_ISC2_bp Predefined. */ - - -/* PORT.PIN5CTRL bit masks and bit positions */ -/* PORT_SRLEN_bm Predefined. */ -/* PORT_SRLEN_bp Predefined. */ - -/* PORT_INVEN_bm Predefined. */ -/* PORT_INVEN_bp Predefined. */ - -/* PORT_OPC_gm Predefined. */ -/* PORT_OPC_gp Predefined. */ -/* PORT_OPC0_bm Predefined. */ -/* PORT_OPC0_bp Predefined. */ -/* PORT_OPC1_bm Predefined. */ -/* PORT_OPC1_bp Predefined. */ -/* PORT_OPC2_bm Predefined. */ -/* PORT_OPC2_bp Predefined. */ - -/* PORT_ISC_gm Predefined. */ -/* PORT_ISC_gp Predefined. */ -/* PORT_ISC0_bm Predefined. */ -/* PORT_ISC0_bp Predefined. */ -/* PORT_ISC1_bm Predefined. */ -/* PORT_ISC1_bp Predefined. */ -/* PORT_ISC2_bm Predefined. */ -/* PORT_ISC2_bp Predefined. */ - - -/* PORT.PIN6CTRL bit masks and bit positions */ -/* PORT_SRLEN_bm Predefined. */ -/* PORT_SRLEN_bp Predefined. */ - -/* PORT_INVEN_bm Predefined. */ -/* PORT_INVEN_bp Predefined. */ - -/* PORT_OPC_gm Predefined. */ -/* PORT_OPC_gp Predefined. */ -/* PORT_OPC0_bm Predefined. */ -/* PORT_OPC0_bp Predefined. */ -/* PORT_OPC1_bm Predefined. */ -/* PORT_OPC1_bp Predefined. */ -/* PORT_OPC2_bm Predefined. */ -/* PORT_OPC2_bp Predefined. */ - -/* PORT_ISC_gm Predefined. */ -/* PORT_ISC_gp Predefined. */ -/* PORT_ISC0_bm Predefined. */ -/* PORT_ISC0_bp Predefined. */ -/* PORT_ISC1_bm Predefined. */ -/* PORT_ISC1_bp Predefined. */ -/* PORT_ISC2_bm Predefined. */ -/* PORT_ISC2_bp Predefined. */ - - -/* PORT.PIN7CTRL bit masks and bit positions */ -/* PORT_SRLEN_bm Predefined. */ -/* PORT_SRLEN_bp Predefined. */ - -/* PORT_INVEN_bm Predefined. */ -/* PORT_INVEN_bp Predefined. */ - -/* PORT_OPC_gm Predefined. */ -/* PORT_OPC_gp Predefined. */ -/* PORT_OPC0_bm Predefined. */ -/* PORT_OPC0_bp Predefined. */ -/* PORT_OPC1_bm Predefined. */ -/* PORT_OPC1_bp Predefined. */ -/* PORT_OPC2_bm Predefined. */ -/* PORT_OPC2_bp Predefined. */ - -/* PORT_ISC_gm Predefined. */ -/* PORT_ISC_gp Predefined. */ -/* PORT_ISC0_bm Predefined. */ -/* PORT_ISC0_bp Predefined. */ -/* PORT_ISC1_bm Predefined. */ -/* PORT_ISC1_bp Predefined. */ -/* PORT_ISC2_bm Predefined. */ -/* PORT_ISC2_bp Predefined. */ - - -/* TC - 16-bit Timer/Counter With PWM */ -/* TC0.CTRLA bit masks and bit positions */ -#define TC0_CLKSEL_gm 0x0F /* Clock Selection group mask. */ -#define TC0_CLKSEL_gp 0 /* Clock Selection group position. */ -#define TC0_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ -#define TC0_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ -#define TC0_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ -#define TC0_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ -#define TC0_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ -#define TC0_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ -#define TC0_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ -#define TC0_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ - - -/* TC0.CTRLB bit masks and bit positions */ -#define TC0_CCDEN_bm 0x80 /* Compare or Capture D Enable bit mask. */ -#define TC0_CCDEN_bp 7 /* Compare or Capture D Enable bit position. */ - -#define TC0_CCCEN_bm 0x40 /* Compare or Capture C Enable bit mask. */ -#define TC0_CCCEN_bp 6 /* Compare or Capture C Enable bit position. */ - -#define TC0_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ -#define TC0_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ - -#define TC0_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ -#define TC0_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ - -#define TC0_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ -#define TC0_WGMODE_gp 0 /* Waveform generation mode group position. */ -#define TC0_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ -#define TC0_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ -#define TC0_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ -#define TC0_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ -#define TC0_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ -#define TC0_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ - - -/* TC0.CTRLC bit masks and bit positions */ -#define TC0_CMPD_bm 0x08 /* Compare D Output Value bit mask. */ -#define TC0_CMPD_bp 3 /* Compare D Output Value bit position. */ - -#define TC0_CMPC_bm 0x04 /* Compare C Output Value bit mask. */ -#define TC0_CMPC_bp 2 /* Compare C Output Value bit position. */ - -#define TC0_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ -#define TC0_CMPB_bp 1 /* Compare B Output Value bit position. */ - -#define TC0_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ -#define TC0_CMPA_bp 0 /* Compare A Output Value bit position. */ - - -/* TC0.CTRLD bit masks and bit positions */ -#define TC0_EVACT_gm 0xE0 /* Event Action group mask. */ -#define TC0_EVACT_gp 5 /* Event Action group position. */ -#define TC0_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ -#define TC0_EVACT0_bp 5 /* Event Action bit 0 position. */ -#define TC0_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ -#define TC0_EVACT1_bp 6 /* Event Action bit 1 position. */ -#define TC0_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ -#define TC0_EVACT2_bp 7 /* Event Action bit 2 position. */ - -#define TC0_EVDLY_bm 0x10 /* Event Delay bit mask. */ -#define TC0_EVDLY_bp 4 /* Event Delay bit position. */ - -#define TC0_EVSEL_gm 0x0F /* Event Source Select group mask. */ -#define TC0_EVSEL_gp 0 /* Event Source Select group position. */ -#define TC0_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ -#define TC0_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ -#define TC0_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ -#define TC0_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ -#define TC0_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ -#define TC0_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ -#define TC0_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ -#define TC0_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ - - -/* TC0.CTRLE bit masks and bit positions */ -#define TC0_BYTEM_bm 0x01 /* Byte Mode bit mask. */ -#define TC0_BYTEM_bp 0 /* Byte Mode bit position. */ - - -/* TC0.INTCTRLA bit masks and bit positions */ -#define TC0_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ -#define TC0_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ -#define TC0_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ -#define TC0_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ -#define TC0_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ -#define TC0_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ - -#define TC0_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ -#define TC0_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ -#define TC0_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ -#define TC0_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ -#define TC0_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ -#define TC0_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ - - -/* TC0.INTCTRLB bit masks and bit positions */ -#define TC0_CCDINTLVL_gm 0xC0 /* Compare or Capture D Interrupt Level group mask. */ -#define TC0_CCDINTLVL_gp 6 /* Compare or Capture D Interrupt Level group position. */ -#define TC0_CCDINTLVL0_bm (1<<6) /* Compare or Capture D Interrupt Level bit 0 mask. */ -#define TC0_CCDINTLVL0_bp 6 /* Compare or Capture D Interrupt Level bit 0 position. */ -#define TC0_CCDINTLVL1_bm (1<<7) /* Compare or Capture D Interrupt Level bit 1 mask. */ -#define TC0_CCDINTLVL1_bp 7 /* Compare or Capture D Interrupt Level bit 1 position. */ - -#define TC0_CCCINTLVL_gm 0x30 /* Compare or Capture C Interrupt Level group mask. */ -#define TC0_CCCINTLVL_gp 4 /* Compare or Capture C Interrupt Level group position. */ -#define TC0_CCCINTLVL0_bm (1<<4) /* Compare or Capture C Interrupt Level bit 0 mask. */ -#define TC0_CCCINTLVL0_bp 4 /* Compare or Capture C Interrupt Level bit 0 position. */ -#define TC0_CCCINTLVL1_bm (1<<5) /* Compare or Capture C Interrupt Level bit 1 mask. */ -#define TC0_CCCINTLVL1_bp 5 /* Compare or Capture C Interrupt Level bit 1 position. */ - -#define TC0_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ -#define TC0_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ -#define TC0_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ -#define TC0_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ -#define TC0_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ -#define TC0_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ - -#define TC0_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ -#define TC0_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ -#define TC0_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ -#define TC0_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ -#define TC0_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ -#define TC0_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ - - -/* TC0.CTRLFCLR bit masks and bit positions */ -#define TC0_CMD_gm 0x0C /* Command group mask. */ -#define TC0_CMD_gp 2 /* Command group position. */ -#define TC0_CMD0_bm (1<<2) /* Command bit 0 mask. */ -#define TC0_CMD0_bp 2 /* Command bit 0 position. */ -#define TC0_CMD1_bm (1<<3) /* Command bit 1 mask. */ -#define TC0_CMD1_bp 3 /* Command bit 1 position. */ - -#define TC0_LUPD_bm 0x02 /* Lock Update bit mask. */ -#define TC0_LUPD_bp 1 /* Lock Update bit position. */ - -#define TC0_DIR_bm 0x01 /* Direction bit mask. */ -#define TC0_DIR_bp 0 /* Direction bit position. */ - - -/* TC0.CTRLFSET bit masks and bit positions */ -/* TC0_CMD_gm Predefined. */ -/* TC0_CMD_gp Predefined. */ -/* TC0_CMD0_bm Predefined. */ -/* TC0_CMD0_bp Predefined. */ -/* TC0_CMD1_bm Predefined. */ -/* TC0_CMD1_bp Predefined. */ - -/* TC0_LUPD_bm Predefined. */ -/* TC0_LUPD_bp Predefined. */ - -/* TC0_DIR_bm Predefined. */ -/* TC0_DIR_bp Predefined. */ - - -/* TC0.CTRLGCLR bit masks and bit positions */ -#define TC0_CCDBV_bm 0x10 /* Compare or Capture D Buffer Valid bit mask. */ -#define TC0_CCDBV_bp 4 /* Compare or Capture D Buffer Valid bit position. */ - -#define TC0_CCCBV_bm 0x08 /* Compare or Capture C Buffer Valid bit mask. */ -#define TC0_CCCBV_bp 3 /* Compare or Capture C Buffer Valid bit position. */ - -#define TC0_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ -#define TC0_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ - -#define TC0_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ -#define TC0_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ - -#define TC0_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ -#define TC0_PERBV_bp 0 /* Period Buffer Valid bit position. */ - - -/* TC0.CTRLGSET bit masks and bit positions */ -/* TC0_CCDBV_bm Predefined. */ -/* TC0_CCDBV_bp Predefined. */ - -/* TC0_CCCBV_bm Predefined. */ -/* TC0_CCCBV_bp Predefined. */ - -/* TC0_CCBBV_bm Predefined. */ -/* TC0_CCBBV_bp Predefined. */ - -/* TC0_CCABV_bm Predefined. */ -/* TC0_CCABV_bp Predefined. */ - -/* TC0_PERBV_bm Predefined. */ -/* TC0_PERBV_bp Predefined. */ - - -/* TC0.INTFLAGS bit masks and bit positions */ -#define TC0_CCDIF_bm 0x80 /* Compare or Capture D Interrupt Flag bit mask. */ -#define TC0_CCDIF_bp 7 /* Compare or Capture D Interrupt Flag bit position. */ - -#define TC0_CCCIF_bm 0x40 /* Compare or Capture C Interrupt Flag bit mask. */ -#define TC0_CCCIF_bp 6 /* Compare or Capture C Interrupt Flag bit position. */ - -#define TC0_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ -#define TC0_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ - -#define TC0_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ -#define TC0_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ - -#define TC0_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ -#define TC0_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ - -#define TC0_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ -#define TC0_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ - - -/* TC1.CTRLA bit masks and bit positions */ -#define TC1_CLKSEL_gm 0x0F /* Clock Selection group mask. */ -#define TC1_CLKSEL_gp 0 /* Clock Selection group position. */ -#define TC1_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ -#define TC1_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ -#define TC1_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ -#define TC1_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ -#define TC1_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ -#define TC1_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ -#define TC1_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ -#define TC1_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ - - -/* TC1.CTRLB bit masks and bit positions */ -#define TC1_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ -#define TC1_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ - -#define TC1_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ -#define TC1_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ - -#define TC1_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ -#define TC1_WGMODE_gp 0 /* Waveform generation mode group position. */ -#define TC1_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ -#define TC1_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ -#define TC1_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ -#define TC1_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ -#define TC1_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ -#define TC1_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ - - -/* TC1.CTRLC bit masks and bit positions */ -#define TC1_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ -#define TC1_CMPB_bp 1 /* Compare B Output Value bit position. */ - -#define TC1_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ -#define TC1_CMPA_bp 0 /* Compare A Output Value bit position. */ - - -/* TC1.CTRLD bit masks and bit positions */ -#define TC1_EVACT_gm 0xE0 /* Event Action group mask. */ -#define TC1_EVACT_gp 5 /* Event Action group position. */ -#define TC1_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ -#define TC1_EVACT0_bp 5 /* Event Action bit 0 position. */ -#define TC1_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ -#define TC1_EVACT1_bp 6 /* Event Action bit 1 position. */ -#define TC1_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ -#define TC1_EVACT2_bp 7 /* Event Action bit 2 position. */ - -#define TC1_EVDLY_bm 0x10 /* Event Delay bit mask. */ -#define TC1_EVDLY_bp 4 /* Event Delay bit position. */ - -#define TC1_EVSEL_gm 0x0F /* Event Source Select group mask. */ -#define TC1_EVSEL_gp 0 /* Event Source Select group position. */ -#define TC1_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ -#define TC1_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ -#define TC1_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ -#define TC1_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ -#define TC1_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ -#define TC1_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ -#define TC1_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ -#define TC1_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ - - -/* TC1.CTRLE bit masks and bit positions */ -#define TC1_BYTEM_bm 0x01 /* Byte Mode bit mask. */ -#define TC1_BYTEM_bp 0 /* Byte Mode bit position. */ - - -/* TC1.INTCTRLA bit masks and bit positions */ -#define TC1_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ -#define TC1_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ -#define TC1_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ -#define TC1_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ -#define TC1_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ -#define TC1_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ - -#define TC1_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ -#define TC1_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ -#define TC1_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ -#define TC1_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ -#define TC1_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ -#define TC1_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ - - -/* TC1.INTCTRLB bit masks and bit positions */ -#define TC1_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ -#define TC1_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ -#define TC1_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ -#define TC1_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ -#define TC1_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ -#define TC1_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ - -#define TC1_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ -#define TC1_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ -#define TC1_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ -#define TC1_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ -#define TC1_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ -#define TC1_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ - - -/* TC1.CTRLFCLR bit masks and bit positions */ -#define TC1_CMD_gm 0x0C /* Command group mask. */ -#define TC1_CMD_gp 2 /* Command group position. */ -#define TC1_CMD0_bm (1<<2) /* Command bit 0 mask. */ -#define TC1_CMD0_bp 2 /* Command bit 0 position. */ -#define TC1_CMD1_bm (1<<3) /* Command bit 1 mask. */ -#define TC1_CMD1_bp 3 /* Command bit 1 position. */ - -#define TC1_LUPD_bm 0x02 /* Lock Update bit mask. */ -#define TC1_LUPD_bp 1 /* Lock Update bit position. */ - -#define TC1_DIR_bm 0x01 /* Direction bit mask. */ -#define TC1_DIR_bp 0 /* Direction bit position. */ - - -/* TC1.CTRLFSET bit masks and bit positions */ -/* TC1_CMD_gm Predefined. */ -/* TC1_CMD_gp Predefined. */ -/* TC1_CMD0_bm Predefined. */ -/* TC1_CMD0_bp Predefined. */ -/* TC1_CMD1_bm Predefined. */ -/* TC1_CMD1_bp Predefined. */ - -/* TC1_LUPD_bm Predefined. */ -/* TC1_LUPD_bp Predefined. */ - -/* TC1_DIR_bm Predefined. */ -/* TC1_DIR_bp Predefined. */ - - -/* TC1.CTRLGCLR bit masks and bit positions */ -#define TC1_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ -#define TC1_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ - -#define TC1_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ -#define TC1_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ - -#define TC1_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ -#define TC1_PERBV_bp 0 /* Period Buffer Valid bit position. */ - - -/* TC1.CTRLGSET bit masks and bit positions */ -/* TC1_CCBBV_bm Predefined. */ -/* TC1_CCBBV_bp Predefined. */ - -/* TC1_CCABV_bm Predefined. */ -/* TC1_CCABV_bp Predefined. */ - -/* TC1_PERBV_bm Predefined. */ -/* TC1_PERBV_bp Predefined. */ - - -/* TC1.INTFLAGS bit masks and bit positions */ -#define TC1_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ -#define TC1_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ - -#define TC1_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ -#define TC1_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ - -#define TC1_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ -#define TC1_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ - -#define TC1_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ -#define TC1_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ - - -/* AWEX.CTRL bit masks and bit positions */ -#define AWEX_PGM_bm 0x20 /* Pattern Generation Mode bit mask. */ -#define AWEX_PGM_bp 5 /* Pattern Generation Mode bit position. */ - -#define AWEX_CWCM_bm 0x10 /* Common Waveform Channel Mode bit mask. */ -#define AWEX_CWCM_bp 4 /* Common Waveform Channel Mode bit position. */ - -#define AWEX_DTICCDEN_bm 0x08 /* Dead Time Insertion Compare Channel D Enable bit mask. */ -#define AWEX_DTICCDEN_bp 3 /* Dead Time Insertion Compare Channel D Enable bit position. */ - -#define AWEX_DTICCCEN_bm 0x04 /* Dead Time Insertion Compare Channel C Enable bit mask. */ -#define AWEX_DTICCCEN_bp 2 /* Dead Time Insertion Compare Channel C Enable bit position. */ - -#define AWEX_DTICCBEN_bm 0x02 /* Dead Time Insertion Compare Channel B Enable bit mask. */ -#define AWEX_DTICCBEN_bp 1 /* Dead Time Insertion Compare Channel B Enable bit position. */ - -#define AWEX_DTICCAEN_bm 0x01 /* Dead Time Insertion Compare Channel A Enable bit mask. */ -#define AWEX_DTICCAEN_bp 0 /* Dead Time Insertion Compare Channel A Enable bit position. */ - - -/* AWEX.FDCTRL bit masks and bit positions */ -#define AWEX_FDDBD_bm 0x10 /* Fault Detect on Disable Break Disable bit mask. */ -#define AWEX_FDDBD_bp 4 /* Fault Detect on Disable Break Disable bit position. */ - -#define AWEX_FDMODE_bm 0x04 /* Fault Detect Mode bit mask. */ -#define AWEX_FDMODE_bp 2 /* Fault Detect Mode bit position. */ - -#define AWEX_FDACT_gm 0x03 /* Fault Detect Action group mask. */ -#define AWEX_FDACT_gp 0 /* Fault Detect Action group position. */ -#define AWEX_FDACT0_bm (1<<0) /* Fault Detect Action bit 0 mask. */ -#define AWEX_FDACT0_bp 0 /* Fault Detect Action bit 0 position. */ -#define AWEX_FDACT1_bm (1<<1) /* Fault Detect Action bit 1 mask. */ -#define AWEX_FDACT1_bp 1 /* Fault Detect Action bit 1 position. */ - - -/* AWEX.STATUS bit masks and bit positions */ -#define AWEX_FDF_bm 0x04 /* Fault Detect Flag bit mask. */ -#define AWEX_FDF_bp 2 /* Fault Detect Flag bit position. */ - -#define AWEX_DTHSBUFV_bm 0x02 /* Dead Time High Side Buffer Valid bit mask. */ -#define AWEX_DTHSBUFV_bp 1 /* Dead Time High Side Buffer Valid bit position. */ - -#define AWEX_DTLSBUFV_bm 0x01 /* Dead Time Low Side Buffer Valid bit mask. */ -#define AWEX_DTLSBUFV_bp 0 /* Dead Time Low Side Buffer Valid bit position. */ - - -/* HIRES.CTRLA bit masks and bit positions */ -#define HIRES_HREN_gm 0x03 /* High Resolution Enable group mask. */ -#define HIRES_HREN_gp 0 /* High Resolution Enable group position. */ -#define HIRES_HREN0_bm (1<<0) /* High Resolution Enable bit 0 mask. */ -#define HIRES_HREN0_bp 0 /* High Resolution Enable bit 0 position. */ -#define HIRES_HREN1_bm (1<<1) /* High Resolution Enable bit 1 mask. */ -#define HIRES_HREN1_bp 1 /* High Resolution Enable bit 1 position. */ - - -/* USART - Universal Asynchronous Receiver-Transmitter */ -/* USART.STATUS bit masks and bit positions */ -#define USART_RXCIF_bm 0x80 /* Receive Interrupt Flag bit mask. */ -#define USART_RXCIF_bp 7 /* Receive Interrupt Flag bit position. */ - -#define USART_TXCIF_bm 0x40 /* Transmit Interrupt Flag bit mask. */ -#define USART_TXCIF_bp 6 /* Transmit Interrupt Flag bit position. */ - -#define USART_DREIF_bm 0x20 /* Data Register Empty Flag bit mask. */ -#define USART_DREIF_bp 5 /* Data Register Empty Flag bit position. */ - -#define USART_FERR_bm 0x10 /* Frame Error bit mask. */ -#define USART_FERR_bp 4 /* Frame Error bit position. */ - -#define USART_BUFOVF_bm 0x08 /* Buffer Overflow bit mask. */ -#define USART_BUFOVF_bp 3 /* Buffer Overflow bit position. */ - -#define USART_PERR_bm 0x04 /* Parity Error bit mask. */ -#define USART_PERR_bp 2 /* Parity Error bit position. */ - -#define USART_RXB8_bm 0x01 /* Receive Bit 8 bit mask. */ -#define USART_RXB8_bp 0 /* Receive Bit 8 bit position. */ - - -/* USART.CTRLA bit masks and bit positions */ -#define USART_RXCINTLVL_gm 0x30 /* Receive Interrupt Level group mask. */ -#define USART_RXCINTLVL_gp 4 /* Receive Interrupt Level group position. */ -#define USART_RXCINTLVL0_bm (1<<4) /* Receive Interrupt Level bit 0 mask. */ -#define USART_RXCINTLVL0_bp 4 /* Receive Interrupt Level bit 0 position. */ -#define USART_RXCINTLVL1_bm (1<<5) /* Receive Interrupt Level bit 1 mask. */ -#define USART_RXCINTLVL1_bp 5 /* Receive Interrupt Level bit 1 position. */ - -#define USART_TXCINTLVL_gm 0x0C /* Transmit Interrupt Level group mask. */ -#define USART_TXCINTLVL_gp 2 /* Transmit Interrupt Level group position. */ -#define USART_TXCINTLVL0_bm (1<<2) /* Transmit Interrupt Level bit 0 mask. */ -#define USART_TXCINTLVL0_bp 2 /* Transmit Interrupt Level bit 0 position. */ -#define USART_TXCINTLVL1_bm (1<<3) /* Transmit Interrupt Level bit 1 mask. */ -#define USART_TXCINTLVL1_bp 3 /* Transmit Interrupt Level bit 1 position. */ - -#define USART_DREINTLVL_gm 0x03 /* Data Register Empty Interrupt Level group mask. */ -#define USART_DREINTLVL_gp 0 /* Data Register Empty Interrupt Level group position. */ -#define USART_DREINTLVL0_bm (1<<0) /* Data Register Empty Interrupt Level bit 0 mask. */ -#define USART_DREINTLVL0_bp 0 /* Data Register Empty Interrupt Level bit 0 position. */ -#define USART_DREINTLVL1_bm (1<<1) /* Data Register Empty Interrupt Level bit 1 mask. */ -#define USART_DREINTLVL1_bp 1 /* Data Register Empty Interrupt Level bit 1 position. */ - - -/* USART.CTRLB bit masks and bit positions */ -#define USART_RXEN_bm 0x10 /* Receiver Enable bit mask. */ -#define USART_RXEN_bp 4 /* Receiver Enable bit position. */ - -#define USART_TXEN_bm 0x08 /* Transmitter Enable bit mask. */ -#define USART_TXEN_bp 3 /* Transmitter Enable bit position. */ - -#define USART_CLK2X_bm 0x04 /* Double transmission speed bit mask. */ -#define USART_CLK2X_bp 2 /* Double transmission speed bit position. */ - -#define USART_MPCM_bm 0x02 /* Multi-processor Communication Mode bit mask. */ -#define USART_MPCM_bp 1 /* Multi-processor Communication Mode bit position. */ - -#define USART_TXB8_bm 0x01 /* Transmit bit 8 bit mask. */ -#define USART_TXB8_bp 0 /* Transmit bit 8 bit position. */ - - -/* USART.CTRLC bit masks and bit positions */ -#define USART_CMODE_gm 0xC0 /* Communication Mode group mask. */ -#define USART_CMODE_gp 6 /* Communication Mode group position. */ -#define USART_CMODE0_bm (1<<6) /* Communication Mode bit 0 mask. */ -#define USART_CMODE0_bp 6 /* Communication Mode bit 0 position. */ -#define USART_CMODE1_bm (1<<7) /* Communication Mode bit 1 mask. */ -#define USART_CMODE1_bp 7 /* Communication Mode bit 1 position. */ - -#define USART_PMODE_gm 0x30 /* Parity Mode group mask. */ -#define USART_PMODE_gp 4 /* Parity Mode group position. */ -#define USART_PMODE0_bm (1<<4) /* Parity Mode bit 0 mask. */ -#define USART_PMODE0_bp 4 /* Parity Mode bit 0 position. */ -#define USART_PMODE1_bm (1<<5) /* Parity Mode bit 1 mask. */ -#define USART_PMODE1_bp 5 /* Parity Mode bit 1 position. */ - -#define USART_SBMODE_bm 0x08 /* Stop Bit Mode bit mask. */ -#define USART_SBMODE_bp 3 /* Stop Bit Mode bit position. */ - -#define USART_CHSIZE_gm 0x07 /* Character Size group mask. */ -#define USART_CHSIZE_gp 0 /* Character Size group position. */ -#define USART_CHSIZE0_bm (1<<0) /* Character Size bit 0 mask. */ -#define USART_CHSIZE0_bp 0 /* Character Size bit 0 position. */ -#define USART_CHSIZE1_bm (1<<1) /* Character Size bit 1 mask. */ -#define USART_CHSIZE1_bp 1 /* Character Size bit 1 position. */ -#define USART_CHSIZE2_bm (1<<2) /* Character Size bit 2 mask. */ -#define USART_CHSIZE2_bp 2 /* Character Size bit 2 position. */ - - -/* USART.BAUDCTRLA bit masks and bit positions */ -#define USART_BSEL_gm 0xFF /* Baud Rate Selection Bits [7:0] group mask. */ -#define USART_BSEL_gp 0 /* Baud Rate Selection Bits [7:0] group position. */ -#define USART_BSEL0_bm (1<<0) /* Baud Rate Selection Bits [7:0] bit 0 mask. */ -#define USART_BSEL0_bp 0 /* Baud Rate Selection Bits [7:0] bit 0 position. */ -#define USART_BSEL1_bm (1<<1) /* Baud Rate Selection Bits [7:0] bit 1 mask. */ -#define USART_BSEL1_bp 1 /* Baud Rate Selection Bits [7:0] bit 1 position. */ -#define USART_BSEL2_bm (1<<2) /* Baud Rate Selection Bits [7:0] bit 2 mask. */ -#define USART_BSEL2_bp 2 /* Baud Rate Selection Bits [7:0] bit 2 position. */ -#define USART_BSEL3_bm (1<<3) /* Baud Rate Selection Bits [7:0] bit 3 mask. */ -#define USART_BSEL3_bp 3 /* Baud Rate Selection Bits [7:0] bit 3 position. */ -#define USART_BSEL4_bm (1<<4) /* Baud Rate Selection Bits [7:0] bit 4 mask. */ -#define USART_BSEL4_bp 4 /* Baud Rate Selection Bits [7:0] bit 4 position. */ -#define USART_BSEL5_bm (1<<5) /* Baud Rate Selection Bits [7:0] bit 5 mask. */ -#define USART_BSEL5_bp 5 /* Baud Rate Selection Bits [7:0] bit 5 position. */ -#define USART_BSEL6_bm (1<<6) /* Baud Rate Selection Bits [7:0] bit 6 mask. */ -#define USART_BSEL6_bp 6 /* Baud Rate Selection Bits [7:0] bit 6 position. */ -#define USART_BSEL7_bm (1<<7) /* Baud Rate Selection Bits [7:0] bit 7 mask. */ -#define USART_BSEL7_bp 7 /* Baud Rate Selection Bits [7:0] bit 7 position. */ - - -/* USART.BAUDCTRLB bit masks and bit positions */ -#define USART_BSCALE_gm 0xF0 /* Baud Rate Scale group mask. */ -#define USART_BSCALE_gp 4 /* Baud Rate Scale group position. */ -#define USART_BSCALE0_bm (1<<4) /* Baud Rate Scale bit 0 mask. */ -#define USART_BSCALE0_bp 4 /* Baud Rate Scale bit 0 position. */ -#define USART_BSCALE1_bm (1<<5) /* Baud Rate Scale bit 1 mask. */ -#define USART_BSCALE1_bp 5 /* Baud Rate Scale bit 1 position. */ -#define USART_BSCALE2_bm (1<<6) /* Baud Rate Scale bit 2 mask. */ -#define USART_BSCALE2_bp 6 /* Baud Rate Scale bit 2 position. */ -#define USART_BSCALE3_bm (1<<7) /* Baud Rate Scale bit 3 mask. */ -#define USART_BSCALE3_bp 7 /* Baud Rate Scale bit 3 position. */ - -/* USART_BSEL_gm Predefined. */ -/* USART_BSEL_gp Predefined. */ -/* USART_BSEL0_bm Predefined. */ -/* USART_BSEL0_bp Predefined. */ -/* USART_BSEL1_bm Predefined. */ -/* USART_BSEL1_bp Predefined. */ -/* USART_BSEL2_bm Predefined. */ -/* USART_BSEL2_bp Predefined. */ -/* USART_BSEL3_bm Predefined. */ -/* USART_BSEL3_bp Predefined. */ - - -/* SPI - Serial Peripheral Interface */ -/* SPI.CTRL bit masks and bit positions */ -#define SPI_CLK2X_bm 0x80 /* Enable Double Speed bit mask. */ -#define SPI_CLK2X_bp 7 /* Enable Double Speed bit position. */ - -#define SPI_ENABLE_bm 0x40 /* Enable Module bit mask. */ -#define SPI_ENABLE_bp 6 /* Enable Module bit position. */ - -#define SPI_DORD_bm 0x20 /* Data Order Setting bit mask. */ -#define SPI_DORD_bp 5 /* Data Order Setting bit position. */ - -#define SPI_MASTER_bm 0x10 /* Master Operation Enable bit mask. */ -#define SPI_MASTER_bp 4 /* Master Operation Enable bit position. */ - -#define SPI_MODE_gm 0x0C /* SPI Mode group mask. */ -#define SPI_MODE_gp 2 /* SPI Mode group position. */ -#define SPI_MODE0_bm (1<<2) /* SPI Mode bit 0 mask. */ -#define SPI_MODE0_bp 2 /* SPI Mode bit 0 position. */ -#define SPI_MODE1_bm (1<<3) /* SPI Mode bit 1 mask. */ -#define SPI_MODE1_bp 3 /* SPI Mode bit 1 position. */ - -#define SPI_PRESCALER_gm 0x03 /* Prescaler group mask. */ -#define SPI_PRESCALER_gp 0 /* Prescaler group position. */ -#define SPI_PRESCALER0_bm (1<<0) /* Prescaler bit 0 mask. */ -#define SPI_PRESCALER0_bp 0 /* Prescaler bit 0 position. */ -#define SPI_PRESCALER1_bm (1<<1) /* Prescaler bit 1 mask. */ -#define SPI_PRESCALER1_bp 1 /* Prescaler bit 1 position. */ - - -/* SPI.INTCTRL bit masks and bit positions */ -#define SPI_INTLVL_gm 0x03 /* Interrupt level group mask. */ -#define SPI_INTLVL_gp 0 /* Interrupt level group position. */ -#define SPI_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */ -#define SPI_INTLVL0_bp 0 /* Interrupt level bit 0 position. */ -#define SPI_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */ -#define SPI_INTLVL1_bp 1 /* Interrupt level bit 1 position. */ - - -/* SPI.STATUS bit masks and bit positions */ -#define SPI_IF_bm 0x80 /* Interrupt Flag bit mask. */ -#define SPI_IF_bp 7 /* Interrupt Flag bit position. */ - -#define SPI_WRCOL_bm 0x40 /* Write Collision bit mask. */ -#define SPI_WRCOL_bp 6 /* Write Collision bit position. */ - - -/* IRCOM - IR Communication Module */ -/* IRCOM.CTRL bit masks and bit positions */ -#define IRCOM_EVSEL_gm 0x0F /* Event Channel Select group mask. */ -#define IRCOM_EVSEL_gp 0 /* Event Channel Select group position. */ -#define IRCOM_EVSEL0_bm (1<<0) /* Event Channel Select bit 0 mask. */ -#define IRCOM_EVSEL0_bp 0 /* Event Channel Select bit 0 position. */ -#define IRCOM_EVSEL1_bm (1<<1) /* Event Channel Select bit 1 mask. */ -#define IRCOM_EVSEL1_bp 1 /* Event Channel Select bit 1 position. */ -#define IRCOM_EVSEL2_bm (1<<2) /* Event Channel Select bit 2 mask. */ -#define IRCOM_EVSEL2_bp 2 /* Event Channel Select bit 2 position. */ -#define IRCOM_EVSEL3_bm (1<<3) /* Event Channel Select bit 3 mask. */ -#define IRCOM_EVSEL3_bp 3 /* Event Channel Select bit 3 position. */ - - - -// Generic Port Pins - -#define PIN0_bm 0x01 -#define PIN0_bp 0 -#define PIN1_bm 0x02 -#define PIN1_bp 1 -#define PIN2_bm 0x04 -#define PIN2_bp 2 -#define PIN3_bm 0x08 -#define PIN3_bp 3 -#define PIN4_bm 0x10 -#define PIN4_bp 4 -#define PIN5_bm 0x20 -#define PIN5_bp 5 -#define PIN6_bm 0x40 -#define PIN6_bp 6 -#define PIN7_bm 0x80 -#define PIN7_bp 7 - - -/* ========== Interrupt Vector Definitions ========== */ -/* Vector 0 is the reset vector */ - -/* OSC interrupt vectors */ -#define OSC_XOSCF_vect_num 1 -#define OSC_XOSCF_vect _VECTOR(1) /* External Oscillator Failure Interrupt (NMI) */ - -/* PORTC interrupt vectors */ -#define PORTC_INT0_vect_num 2 -#define PORTC_INT0_vect _VECTOR(2) /* External Interrupt 0 */ -#define PORTC_INT1_vect_num 3 -#define PORTC_INT1_vect _VECTOR(3) /* External Interrupt 1 */ - -/* PORTR interrupt vectors */ -#define PORTR_INT0_vect_num 4 -#define PORTR_INT0_vect _VECTOR(4) /* External Interrupt 0 */ -#define PORTR_INT1_vect_num 5 -#define PORTR_INT1_vect _VECTOR(5) /* External Interrupt 1 */ - -/* RTC interrupt vectors */ -#define RTC_OVF_vect_num 10 -#define RTC_OVF_vect _VECTOR(10) /* Overflow Interrupt */ -#define RTC_COMP_vect_num 11 -#define RTC_COMP_vect _VECTOR(11) /* Compare Interrupt */ - -/* TWIC interrupt vectors */ -#define TWIC_TWIS_vect_num 12 -#define TWIC_TWIS_vect _VECTOR(12) /* TWI Slave Interrupt */ -#define TWIC_TWIM_vect_num 13 -#define TWIC_TWIM_vect _VECTOR(13) /* TWI Master Interrupt */ - -/* TCC0 interrupt vectors */ -#define TCC0_OVF_vect_num 14 -#define TCC0_OVF_vect _VECTOR(14) /* Overflow Interrupt */ -#define TCC0_ERR_vect_num 15 -#define TCC0_ERR_vect _VECTOR(15) /* Error Interrupt */ -#define TCC0_CCA_vect_num 16 -#define TCC0_CCA_vect _VECTOR(16) /* Compare or Capture A Interrupt */ -#define TCC0_CCB_vect_num 17 -#define TCC0_CCB_vect _VECTOR(17) /* Compare or Capture B Interrupt */ -#define TCC0_CCC_vect_num 18 -#define TCC0_CCC_vect _VECTOR(18) /* Compare or Capture C Interrupt */ -#define TCC0_CCD_vect_num 19 -#define TCC0_CCD_vect _VECTOR(19) /* Compare or Capture D Interrupt */ - -/* TCC1 interrupt vectors */ -#define TCC1_OVF_vect_num 20 -#define TCC1_OVF_vect _VECTOR(20) /* Overflow Interrupt */ -#define TCC1_ERR_vect_num 21 -#define TCC1_ERR_vect _VECTOR(21) /* Error Interrupt */ -#define TCC1_CCA_vect_num 22 -#define TCC1_CCA_vect _VECTOR(22) /* Compare or Capture A Interrupt */ -#define TCC1_CCB_vect_num 23 -#define TCC1_CCB_vect _VECTOR(23) /* Compare or Capture B Interrupt */ - -/* SPIC interrupt vectors */ -#define SPIC_INT_vect_num 24 -#define SPIC_INT_vect _VECTOR(24) /* SPI Interrupt */ - -/* USARTC0 interrupt vectors */ -#define USARTC0_RXC_vect_num 25 -#define USARTC0_RXC_vect _VECTOR(25) /* Reception Complete Interrupt */ -#define USARTC0_DRE_vect_num 26 -#define USARTC0_DRE_vect _VECTOR(26) /* Data Register Empty Interrupt */ -#define USARTC0_TXC_vect_num 27 -#define USARTC0_TXC_vect _VECTOR(27) /* Transmission Complete Interrupt */ - -/* NVM interrupt vectors */ -#define NVM_EE_vect_num 32 -#define NVM_EE_vect _VECTOR(32) /* EE Interrupt */ -#define NVM_SPM_vect_num 33 -#define NVM_SPM_vect _VECTOR(33) /* SPM Interrupt */ - -/* PORTB interrupt vectors */ -#define PORTB_INT0_vect_num 34 -#define PORTB_INT0_vect _VECTOR(34) /* External Interrupt 0 */ -#define PORTB_INT1_vect_num 35 -#define PORTB_INT1_vect _VECTOR(35) /* External Interrupt 1 */ - -/* PORTE interrupt vectors */ -#define PORTE_INT0_vect_num 43 -#define PORTE_INT0_vect _VECTOR(43) /* External Interrupt 0 */ -#define PORTE_INT1_vect_num 44 -#define PORTE_INT1_vect _VECTOR(44) /* External Interrupt 1 */ - -/* TWIE interrupt vectors */ -#define TWIE_TWIS_vect_num 45 -#define TWIE_TWIS_vect _VECTOR(45) /* TWI Slave Interrupt */ -#define TWIE_TWIM_vect_num 46 -#define TWIE_TWIM_vect _VECTOR(46) /* TWI Master Interrupt */ - -/* TCE0 interrupt vectors */ -#define TCE0_OVF_vect_num 47 -#define TCE0_OVF_vect _VECTOR(47) /* Overflow Interrupt */ -#define TCE0_ERR_vect_num 48 -#define TCE0_ERR_vect _VECTOR(48) /* Error Interrupt */ -#define TCE0_CCA_vect_num 49 -#define TCE0_CCA_vect _VECTOR(49) /* Compare or Capture A Interrupt */ -#define TCE0_CCB_vect_num 50 -#define TCE0_CCB_vect _VECTOR(50) /* Compare or Capture B Interrupt */ -#define TCE0_CCC_vect_num 51 -#define TCE0_CCC_vect _VECTOR(51) /* Compare or Capture C Interrupt */ -#define TCE0_CCD_vect_num 52 -#define TCE0_CCD_vect _VECTOR(52) /* Compare or Capture D Interrupt */ - -/* USARTE0 interrupt vectors */ -#define USARTE0_RXC_vect_num 58 -#define USARTE0_RXC_vect _VECTOR(58) /* Reception Complete Interrupt */ -#define USARTE0_DRE_vect_num 59 -#define USARTE0_DRE_vect _VECTOR(59) /* Data Register Empty Interrupt */ -#define USARTE0_TXC_vect_num 60 -#define USARTE0_TXC_vect _VECTOR(60) /* Transmission Complete Interrupt */ - -/* PORTD interrupt vectors */ -#define PORTD_INT0_vect_num 64 -#define PORTD_INT0_vect _VECTOR(64) /* External Interrupt 0 */ -#define PORTD_INT1_vect_num 65 -#define PORTD_INT1_vect _VECTOR(65) /* External Interrupt 1 */ - -/* PORTA interrupt vectors */ -#define PORTA_INT0_vect_num 66 -#define PORTA_INT0_vect _VECTOR(66) /* External Interrupt 0 */ -#define PORTA_INT1_vect_num 67 -#define PORTA_INT1_vect _VECTOR(67) /* External Interrupt 1 */ - -/* ACA interrupt vectors */ -#define ACA_AC0_vect_num 68 -#define ACA_AC0_vect _VECTOR(68) /* AC0 Interrupt */ -#define ACA_AC1_vect_num 69 -#define ACA_AC1_vect _VECTOR(69) /* AC1 Interrupt */ -#define ACA_ACW_vect_num 70 -#define ACA_ACW_vect _VECTOR(70) /* ACW Window Mode Interrupt */ - -/* ADCA interrupt vectors */ -#define ADCA_CH0_vect_num 71 -#define ADCA_CH0_vect _VECTOR(71) /* Interrupt 0 */ - -/* TCD0 interrupt vectors */ -#define TCD0_OVF_vect_num 77 -#define TCD0_OVF_vect _VECTOR(77) /* Overflow Interrupt */ -#define TCD0_ERR_vect_num 78 -#define TCD0_ERR_vect _VECTOR(78) /* Error Interrupt */ -#define TCD0_CCA_vect_num 79 -#define TCD0_CCA_vect _VECTOR(79) /* Compare or Capture A Interrupt */ -#define TCD0_CCB_vect_num 80 -#define TCD0_CCB_vect _VECTOR(80) /* Compare or Capture B Interrupt */ -#define TCD0_CCC_vect_num 81 -#define TCD0_CCC_vect _VECTOR(81) /* Compare or Capture C Interrupt */ -#define TCD0_CCD_vect_num 82 -#define TCD0_CCD_vect _VECTOR(82) /* Compare or Capture D Interrupt */ - -/* SPID interrupt vectors */ -#define SPID_INT_vect_num 87 -#define SPID_INT_vect _VECTOR(87) /* SPI Interrupt */ - -/* USARTD0 interrupt vectors */ -#define USARTD0_RXC_vect_num 88 -#define USARTD0_RXC_vect _VECTOR(88) /* Reception Complete Interrupt */ -#define USARTD0_DRE_vect_num 89 -#define USARTD0_DRE_vect _VECTOR(89) /* Data Register Empty Interrupt */ -#define USARTD0_TXC_vect_num 90 -#define USARTD0_TXC_vect _VECTOR(90) /* Transmission Complete Interrupt */ - -/* PORTF interrupt vectors */ -#define PORTF_INT0_vect_num 104 -#define PORTF_INT0_vect _VECTOR(104) /* External Interrupt 0 */ -#define PORTF_INT1_vect_num 105 -#define PORTF_INT1_vect _VECTOR(105) /* External Interrupt 1 */ - -/* TCF0 interrupt vectors */ -#define TCF0_OVF_vect_num 108 -#define TCF0_OVF_vect _VECTOR(108) /* Overflow Interrupt */ -#define TCF0_ERR_vect_num 109 -#define TCF0_ERR_vect _VECTOR(109) /* Error Interrupt */ -#define TCF0_CCA_vect_num 110 -#define TCF0_CCA_vect _VECTOR(110) /* Compare or Capture A Interrupt */ -#define TCF0_CCB_vect_num 111 -#define TCF0_CCB_vect _VECTOR(111) /* Compare or Capture B Interrupt */ -#define TCF0_CCC_vect_num 112 -#define TCF0_CCC_vect _VECTOR(112) /* Compare or Capture C Interrupt */ -#define TCF0_CCD_vect_num 113 -#define TCF0_CCD_vect _VECTOR(113) /* Compare or Capture D Interrupt */ - - -#define _VECTOR_SIZE 4 /* Size of individual vector. */ -#define _VECTORS_SIZE (114 * _VECTOR_SIZE) - - -/* ========== Constants ========== */ - -#define PROGMEM_START (0x0000) -#define PROGMEM_SIZE (270336) -#define PROGMEM_PAGE_SIZE (512) -#define PROGMEM_END (PROGMEM_START + PROGMEM_SIZE - 1) - -#define APP_SECTION_START (0x0000) -#define APP_SECTION_SIZE (262144) -#define APP_SECTION_PAGE_SIZE (512) -#define APP_SECTION_END (APP_SECTION_START + APP_SECTION_SIZE - 1) - -#define APPTABLE_SECTION_START (0x3E000) -#define APPTABLE_SECTION_SIZE (8192) -#define APPTABLE_SECTION_PAGE_SIZE (512) -#define APPTABLE_SECTION_END (APPTABLE_SECTION_START + APPTABLE_SECTION_SIZE - 1) - -#define BOOT_SECTION_START (0x40000) -#define BOOT_SECTION_SIZE (8192) -#define BOOT_SECTION_PAGE_SIZE (512) -#define BOOT_SECTION_END (BOOT_SECTION_START + BOOT_SECTION_SIZE - 1) - -#define DATAMEM_START (0x0000) -#define DATAMEM_SIZE (24576) -#define DATAMEM_PAGE_SIZE (0) -#define DATAMEM_END (DATAMEM_START + DATAMEM_SIZE - 1) - -#define IO_START (0x0000) -#define IO_SIZE (4096) -#define IO_PAGE_SIZE (0) -#define IO_END (IO_START + IO_SIZE - 1) - -#define MAPPED_EEPROM_START (0x1000) -#define MAPPED_EEPROM_SIZE (4096) -#define MAPPED_EEPROM_PAGE_SIZE (0) -#define MAPPED_EEPROM_END (MAPPED_EEPROM_START + MAPPED_EEPROM_SIZE - 1) - -#define INTERNAL_SRAM_START (0x2000) -#define INTERNAL_SRAM_SIZE (16384) -#define INTERNAL_SRAM_PAGE_SIZE (0) -#define INTERNAL_SRAM_END (INTERNAL_SRAM_START + INTERNAL_SRAM_SIZE - 1) - -#define EEPROM_START (0x0000) -#define EEPROM_SIZE (4096) -#define EEPROM_PAGE_SIZE (32) -#define EEPROM_END (EEPROM_START + EEPROM_SIZE - 1) - -#define FUSE_START (0x0000) -#define FUSE_SIZE (6) -#define FUSE_PAGE_SIZE (0) -#define FUSE_END (FUSE_START + FUSE_SIZE - 1) - -#define LOCKBIT_START (0x0000) -#define LOCKBIT_SIZE (1) -#define LOCKBIT_PAGE_SIZE (0) -#define LOCKBIT_END (LOCKBIT_START + LOCKBIT_SIZE - 1) - -#define SIGNATURES_START (0x0000) -#define SIGNATURES_SIZE (3) -#define SIGNATURES_PAGE_SIZE (0) -#define SIGNATURES_END (SIGNATURES_START + SIGNATURES_SIZE - 1) - -#define USER_SIGNATURES_START (0x0000) -#define USER_SIGNATURES_SIZE (512) -#define USER_SIGNATURES_PAGE_SIZE (0) -#define USER_SIGNATURES_END (USER_SIGNATURES_START + USER_SIGNATURES_SIZE - 1) - -#define PROD_SIGNATURES_START (0x0000) -#define PROD_SIGNATURES_SIZE (52) -#define PROD_SIGNATURES_PAGE_SIZE (0) -#define PROD_SIGNATURES_END (PROD_SIGNATURES_START + PROD_SIGNATURES_SIZE - 1) - -#define FLASHEND PROGMEM_END -#define SPM_PAGESIZE PROGMEM_PAGE_SIZE -#define RAMSTART INTERNAL_SRAM_START -#define RAMSIZE INTERNAL_SRAM_SIZE -#define RAMEND INTERNAL_SRAM_END -#define XRAMSTART EXTERNAL_SRAM_START -#define XRAMSIZE EXTERNAL_SRAM_SIZE -#define XRAMEND INTERNAL_SRAM_END -#define E2END EEPROM_END -#define E2PAGESIZE EEPROM_PAGE_SIZE - - -/* ========== Fuses ========== */ -#define FUSE_MEMORY_SIZE 6 - -/* Fuse Byte 0 */ -#define FUSE_USERID0 (unsigned char)~_BV(0) /* User ID Bit 0 */ -#define FUSE_USERID1 (unsigned char)~_BV(1) /* User ID Bit 1 */ -#define FUSE_USERID2 (unsigned char)~_BV(2) /* User ID Bit 2 */ -#define FUSE_USERID3 (unsigned char)~_BV(3) /* User ID Bit 3 */ -#define FUSE_USERID4 (unsigned char)~_BV(4) /* User ID Bit 4 */ -#define FUSE_USERID5 (unsigned char)~_BV(5) /* User ID Bit 5 */ -#define FUSE_USERID6 (unsigned char)~_BV(6) /* User ID Bit 6 */ -#define FUSE_USERID7 (unsigned char)~_BV(7) /* User ID Bit 7 */ -#define FUSE0_DEFAULT (0xFF) - -/* Fuse Byte 1 */ -#define FUSE_WDP0 (unsigned char)~_BV(0) /* Watchdog Timeout Period Bit 0 */ -#define FUSE_WDP1 (unsigned char)~_BV(1) /* Watchdog Timeout Period Bit 1 */ -#define FUSE_WDP2 (unsigned char)~_BV(2) /* Watchdog Timeout Period Bit 2 */ -#define FUSE_WDP3 (unsigned char)~_BV(3) /* Watchdog Timeout Period Bit 3 */ -#define FUSE_WDWP0 (unsigned char)~_BV(4) /* Watchdog Window Timeout Period Bit 0 */ -#define FUSE_WDWP1 (unsigned char)~_BV(5) /* Watchdog Window Timeout Period Bit 1 */ -#define FUSE_WDWP2 (unsigned char)~_BV(6) /* Watchdog Window Timeout Period Bit 2 */ -#define FUSE_WDWP3 (unsigned char)~_BV(7) /* Watchdog Window Timeout Period Bit 3 */ -#define FUSE1_DEFAULT (0xFF) - -/* Fuse Byte 2 */ -#define FUSE_BODPD0 (unsigned char)~_BV(0) /* BOD Operation in Power-Down Mode Bit 0 */ -#define FUSE_BODPD1 (unsigned char)~_BV(1) /* BOD Operation in Power-Down Mode Bit 1 */ -#define FUSE_BOOTRST (unsigned char)~_BV(6) /* Boot Loader Section Reset Vector */ -#define FUSE_DVSDON (unsigned char)~_BV(7) /* Spike Detector Enable */ -#define FUSE2_DEFAULT (0xFF) - -/* Fuse Byte 3 Reserved */ - -/* Fuse Byte 4 */ -#define FUSE_WDLOCK (unsigned char)~_BV(1) /* Watchdog Timer Lock */ -#define FUSE_SUT0 (unsigned char)~_BV(2) /* Start-up Time Bit 0 */ -#define FUSE_SUT1 (unsigned char)~_BV(3) /* Start-up Time Bit 1 */ -#define FUSE_RSTDISBL (unsigned char)~_BV(4) /* External Reset Disable */ -#define FUSE4_DEFAULT (0xFF) - -/* Fuse Byte 5 */ -#define FUSE_BODLVL0 (unsigned char)~_BV(0) /* Brown Out Detection Voltage Level Bit 0 */ -#define FUSE_BODLVL1 (unsigned char)~_BV(1) /* Brown Out Detection Voltage Level Bit 1 */ -#define FUSE_BODLVL2 (unsigned char)~_BV(2) /* Brown Out Detection Voltage Level Bit 2 */ -#define FUSE_EESAVE (unsigned char)~_BV(3) /* Preserve EEPROM Through Chip Erase */ -#define FUSE_BODACT0 (unsigned char)~_BV(4) /* BOD Operation in Active Mode Bit 0 */ -#define FUSE_BODACT1 (unsigned char)~_BV(5) /* BOD Operation in Active Mode Bit 1 */ -#define FUSE5_DEFAULT (0xFF) - - -/* ========== Lock Bits ========== */ -#define __LOCK_BITS_EXIST -#define __BOOT_LOCK_APPLICATION_TABLE_BITS_EXIST -#define __BOOT_LOCK_APPLICATION_BITS_EXIST -#define __BOOT_LOCK_BOOT_BITS_EXIST - - -/* ========== Signature ========== */ -#define SIGNATURE_0 0x1E -#define SIGNATURE_1 0x98 -#define SIGNATURE_2 0x44 - -/* ========== Power Reduction Condition Definitions ========== */ - -/* PR.PRGEN */ -#define __AVR_HAVE_PRGEN (PR_RTC_bm|PR_EVSYS_bm) -#define __AVR_HAVE_PRGEN_RTC -#define __AVR_HAVE_PRGEN_EVSYS - -/* PR.PRPA */ -#define __AVR_HAVE_PRPA (PR_ADC_bm|PR_AC_bm) -#define __AVR_HAVE_PRPA_ADC -#define __AVR_HAVE_PRPA_AC - -/* PR.PRPC */ -#define __AVR_HAVE_PRPC (PR_TWI_bm|PR_USART0_bm|PR_SPI_bm|PR_HIRES_bm|PR_TC1_bm|PR_TC0_bm) -#define __AVR_HAVE_PRPC_TWI -#define __AVR_HAVE_PRPC_USART0 -#define __AVR_HAVE_PRPC_SPI -#define __AVR_HAVE_PRPC_HIRES -#define __AVR_HAVE_PRPC_TC1 -#define __AVR_HAVE_PRPC_TC0 - -/* PR.PRPD */ -#define __AVR_HAVE_PRPD (PR_USART0_bm|PR_SPI_bm|PR_TC0_bm) -#define __AVR_HAVE_PRPD_USART0 -#define __AVR_HAVE_PRPD_SPI -#define __AVR_HAVE_PRPD_TC0 - -/* PR.PRPE */ -#define __AVR_HAVE_PRPE (PR_TWI_bm|PR_USART0_bm|PR_TC0_bm) -#define __AVR_HAVE_PRPE_TWI -#define __AVR_HAVE_PRPE_USART0 -#define __AVR_HAVE_PRPE_TC0 - -/* PR.PRPF */ -#define __AVR_HAVE_PRPF (PR_USART0_bm|PR_TC0_bm) -#define __AVR_HAVE_PRPF_USART0 -#define __AVR_HAVE_PRPF_TC0 - - -#endif /* _AVR_ATxmega256D3_H_ */ - diff --git a/arduino/hardware/tools/avr/avr/include/avr/iox32a4.h b/arduino/hardware/tools/avr/avr/include/avr/iox32a4.h deleted file mode 100644 index c74862a..0000000 --- a/arduino/hardware/tools/avr/avr/include/avr/iox32a4.h +++ /dev/null @@ -1,6747 +0,0 @@ -/* Copyright (c) 2009-2010 Atmel Corporation - All rights reserved. - - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - * Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - * Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in - the documentation and/or other materials provided with the - distribution. - - * Neither the name of the copyright holders nor the names of - contributors may be used to endorse or promote products derived - from this software without specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. */ - -/* $Id: iox32a4.h 2200 2010-12-14 04:24:24Z arcanum $ */ - -/* avr/iox32a4.h - definitions for ATxmega32A4 */ - -/* This file should only be included from , never directly. */ - -#ifndef _AVR_IO_H_ -# error "Include instead of this file." -#endif - -#ifndef _AVR_IOXXX_H_ -# define _AVR_IOXXX_H_ "iox32a4.h" -#else -# error "Attempt to include more than one file." -#endif - - -#ifndef _AVR_ATxmega32A4_H_ -#define _AVR_ATxmega32A4_H_ 1 - - -/* Ungrouped common registers */ -#define GPIOR0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ -#define GPIOR1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ -#define GPIOR2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ -#define GPIOR3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ -#define GPIOR4 _SFR_MEM8(0x0004) /* General Purpose IO Register 4 */ -#define GPIOR5 _SFR_MEM8(0x0005) /* General Purpose IO Register 5 */ -#define GPIOR6 _SFR_MEM8(0x0006) /* General Purpose IO Register 6 */ -#define GPIOR7 _SFR_MEM8(0x0007) /* General Purpose IO Register 7 */ -#define GPIOR8 _SFR_MEM8(0x0008) /* General Purpose IO Register 8 */ -#define GPIOR9 _SFR_MEM8(0x0009) /* General Purpose IO Register 9 */ -#define GPIORA _SFR_MEM8(0x000A) /* General Purpose IO Register 10 */ -#define GPIORB _SFR_MEM8(0x000B) /* General Purpose IO Register 11 */ -#define GPIORC _SFR_MEM8(0x000C) /* General Purpose IO Register 12 */ -#define GPIORD _SFR_MEM8(0x000D) /* General Purpose IO Register 13 */ -#define GPIORE _SFR_MEM8(0x000E) /* General Purpose IO Register 14 */ -#define GPIORF _SFR_MEM8(0x000F) /* General Purpose IO Register 15 */ - -/* Deprecated */ -#define GPIO0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ -#define GPIO1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ -#define GPIO2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ -#define GPIO3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ -#define GPIO4 _SFR_MEM8(0x0004) /* General Purpose IO Register 4 */ -#define GPIO5 _SFR_MEM8(0x0005) /* General Purpose IO Register 5 */ -#define GPIO6 _SFR_MEM8(0x0006) /* General Purpose IO Register 6 */ -#define GPIO7 _SFR_MEM8(0x0007) /* General Purpose IO Register 7 */ -#define GPIO8 _SFR_MEM8(0x0008) /* General Purpose IO Register 8 */ -#define GPIO9 _SFR_MEM8(0x0009) /* General Purpose IO Register 9 */ -#define GPIOA _SFR_MEM8(0x000A) /* General Purpose IO Register 10 */ -#define GPIOB _SFR_MEM8(0x000B) /* General Purpose IO Register 11 */ -#define GPIOC _SFR_MEM8(0x000C) /* General Purpose IO Register 12 */ -#define GPIOD _SFR_MEM8(0x000D) /* General Purpose IO Register 13 */ -#define GPIOE _SFR_MEM8(0x000E) /* General Purpose IO Register 14 */ -#define GPIOF _SFR_MEM8(0x000F) /* General Purpose IO Register 15 */ - -#define CCP _SFR_MEM8(0x0034) /* Configuration Change Protection */ -#define RAMPD _SFR_MEM8(0x0038) /* Ramp D */ -#define RAMPX _SFR_MEM8(0x0039) /* Ramp X */ -#define RAMPY _SFR_MEM8(0x003A) /* Ramp Y */ -#define RAMPZ _SFR_MEM8(0x003B) /* Ramp Z */ -#define EIND _SFR_MEM8(0x003C) /* Extended Indirect Jump */ -#define SPL _SFR_MEM8(0x003D) /* Stack Pointer Low */ -#define SPH _SFR_MEM8(0x003E) /* Stack Pointer High */ -#define SREG _SFR_MEM8(0x003F) /* Status Register */ - - -/* C Language Only */ -#if !defined (__ASSEMBLER__) - -#include - -typedef volatile uint8_t register8_t; -typedef volatile uint16_t register16_t; -typedef volatile uint32_t register32_t; - - -#ifdef _WORDREGISTER -#undef _WORDREGISTER -#endif -#define _WORDREGISTER(regname) \ - __extension__ union \ - { \ - register16_t regname; \ - struct \ - { \ - register8_t regname ## L; \ - register8_t regname ## H; \ - }; \ - } - -#ifdef _DWORDREGISTER -#undef _DWORDREGISTER -#endif -#define _DWORDREGISTER(regname) \ - __extension__ union \ - { \ - register32_t regname; \ - struct \ - { \ - register8_t regname ## 0; \ - register8_t regname ## 1; \ - register8_t regname ## 2; \ - register8_t regname ## 3; \ - }; \ - } - - -/* -========================================================================== -IO Module Structures -========================================================================== -*/ - - -/* --------------------------------------------------------------------------- -XOCD - On-Chip Debug System --------------------------------------------------------------------------- -*/ - -/* On-Chip Debug System */ -typedef struct OCD_struct -{ - register8_t OCDR0; /* OCD Register 0 */ - register8_t OCDR1; /* OCD Register 1 */ -} OCD_t; - - -/* CCP signatures */ -typedef enum CCP_enum -{ - CCP_SPM_gc = (0x9D<<0), /* SPM Instruction Protection */ - CCP_IOREG_gc = (0xD8<<0), /* IO Register Protection */ -} CCP_t; - - -/* --------------------------------------------------------------------------- -CLK - Clock System --------------------------------------------------------------------------- -*/ - -/* Clock System */ -typedef struct CLK_struct -{ - register8_t CTRL; /* Control Register */ - register8_t PSCTRL; /* Prescaler Control Register */ - register8_t LOCK; /* Lock register */ - register8_t RTCCTRL; /* RTC Control Register */ -} CLK_t; - -/* --------------------------------------------------------------------------- -CLK - Clock System --------------------------------------------------------------------------- -*/ - -/* Power Reduction */ -typedef struct PR_struct -{ - register8_t PRGEN; /* General Power Reduction */ - register8_t PRPA; /* Power Reduction Port A */ - register8_t PRPB; /* Power Reduction Port B */ - register8_t PRPC; /* Power Reduction Port C */ - register8_t PRPD; /* Power Reduction Port D */ - register8_t PRPE; /* Power Reduction Port E */ - register8_t PRPF; /* Power Reduction Port F */ -} PR_t; - -/* System Clock Selection */ -typedef enum CLK_SCLKSEL_enum -{ - CLK_SCLKSEL_RC2M_gc = (0x00<<0), /* Internal 2MHz RC Oscillator */ - CLK_SCLKSEL_RC32M_gc = (0x01<<0), /* Internal 32MHz RC Oscillator */ - CLK_SCLKSEL_RC32K_gc = (0x02<<0), /* Internal 32kHz RC Oscillator */ - CLK_SCLKSEL_XOSC_gc = (0x03<<0), /* External Crystal Oscillator or Clock */ - CLK_SCLKSEL_PLL_gc = (0x04<<0), /* Phase Locked Loop */ -} CLK_SCLKSEL_t; - -/* Prescaler A Division Factor */ -typedef enum CLK_PSADIV_enum -{ - CLK_PSADIV_1_gc = (0x00<<2), /* Divide by 1 */ - CLK_PSADIV_2_gc = (0x01<<2), /* Divide by 2 */ - CLK_PSADIV_4_gc = (0x03<<2), /* Divide by 4 */ - CLK_PSADIV_8_gc = (0x05<<2), /* Divide by 8 */ - CLK_PSADIV_16_gc = (0x07<<2), /* Divide by 16 */ - CLK_PSADIV_32_gc = (0x09<<2), /* Divide by 32 */ - CLK_PSADIV_64_gc = (0x0B<<2), /* Divide by 64 */ - CLK_PSADIV_128_gc = (0x0D<<2), /* Divide by 128 */ - CLK_PSADIV_256_gc = (0x0F<<2), /* Divide by 256 */ - CLK_PSADIV_512_gc = (0x11<<2), /* Divide by 512 */ -} CLK_PSADIV_t; - -/* Prescaler B and C Division Factor */ -typedef enum CLK_PSBCDIV_enum -{ - CLK_PSBCDIV_1_1_gc = (0x00<<0), /* Divide B by 1 and C by 1 */ - CLK_PSBCDIV_1_2_gc = (0x01<<0), /* Divide B by 1 and C by 2 */ - CLK_PSBCDIV_4_1_gc = (0x02<<0), /* Divide B by 4 and C by 1 */ - CLK_PSBCDIV_2_2_gc = (0x03<<0), /* Divide B by 2 and C by 2 */ -} CLK_PSBCDIV_t; - -/* RTC Clock Source */ -typedef enum CLK_RTCSRC_enum -{ - CLK_RTCSRC_ULP_gc = (0x00<<1), /* 1kHz from internal 32kHz ULP */ - CLK_RTCSRC_TOSC_gc = (0x01<<1), /* 1kHz from 32kHz crystal oscillator on TOSC */ - CLK_RTCSRC_RCOSC_gc = (0x02<<1), /* 1kHz from internal 32kHz RC oscillator */ - CLK_RTCSRC_TOSC32_gc = (0x05<<1), /* 32kHz from 32kHz crystal oscillator on TOSC */ -} CLK_RTCSRC_t; - - -/* --------------------------------------------------------------------------- -SLEEP - Sleep Controller --------------------------------------------------------------------------- -*/ - -/* Sleep Controller */ -typedef struct SLEEP_struct -{ - register8_t CTRL; /* Control Register */ -} SLEEP_t; - -/* Sleep Mode */ -typedef enum SLEEP_SMODE_enum -{ - SLEEP_SMODE_IDLE_gc = (0x00<<1), /* Idle mode */ - SLEEP_SMODE_PDOWN_gc = (0x02<<1), /* Power-down Mode */ - SLEEP_SMODE_PSAVE_gc = (0x03<<1), /* Power-save Mode */ - SLEEP_SMODE_STDBY_gc = (0x06<<1), /* Standby Mode */ - SLEEP_SMODE_ESTDBY_gc = (0x07<<1), /* Extended Standby Mode */ -} SLEEP_SMODE_t; - - -#define SLEEP_MODE_IDLE (0x00<<1) -#define SLEEP_MODE_PWR_DOWN (0x02<<1) -#define SLEEP_MODE_PWR_SAVE (0x03<<1) -#define SLEEP_MODE_STANDBY (0x06<<1) -#define SLEEP_MODE_EXT_STANDBY (0x07<<1) - -/* --------------------------------------------------------------------------- -OSC - Oscillator --------------------------------------------------------------------------- -*/ - -/* Oscillator */ -typedef struct OSC_struct -{ - register8_t CTRL; /* Control Register */ - register8_t STATUS; /* Status Register */ - register8_t XOSCCTRL; /* External Oscillator Control Register */ - register8_t XOSCFAIL; /* External Oscillator Failure Detection Register */ - register8_t RC32KCAL; /* 32kHz Internal Oscillator Calibration Register */ - register8_t PLLCTRL; /* PLL Control REgister */ - register8_t DFLLCTRL; /* DFLL Control Register */ -} OSC_t; - -/* Oscillator Frequency Range */ -typedef enum OSC_FRQRANGE_enum -{ - OSC_FRQRANGE_04TO2_gc = (0x00<<6), /* 0.4 - 2 MHz */ - OSC_FRQRANGE_2TO9_gc = (0x01<<6), /* 2 - 9 MHz */ - OSC_FRQRANGE_9TO12_gc = (0x02<<6), /* 9 - 12 MHz */ - OSC_FRQRANGE_12TO16_gc = (0x03<<6), /* 12 - 16 MHz */ -} OSC_FRQRANGE_t; - -/* External Oscillator Selection and Startup Time */ -typedef enum OSC_XOSCSEL_enum -{ - OSC_XOSCSEL_EXTCLK_gc = (0x00<<0), /* External Clock - 6 CLK */ - OSC_XOSCSEL_32KHz_gc = (0x02<<0), /* 32kHz TOSC - 32K CLK */ - OSC_XOSCSEL_XTAL_256CLK_gc = (0x03<<0), /* 0.4-16MHz XTAL - 256 CLK */ - OSC_XOSCSEL_XTAL_1KCLK_gc = (0x07<<0), /* 0.4-16MHz XTAL - 1K CLK */ - OSC_XOSCSEL_XTAL_16KCLK_gc = (0x0B<<0), /* 0.4-16MHz XTAL - 16K CLK */ -} OSC_XOSCSEL_t; - -/* PLL Clock Source */ -typedef enum OSC_PLLSRC_enum -{ - OSC_PLLSRC_RC2M_gc = (0x00<<6), /* Internal 2MHz RC Oscillator */ - OSC_PLLSRC_RC32M_gc = (0x02<<6), /* Internal 32MHz RC Oscillator */ - OSC_PLLSRC_XOSC_gc = (0x03<<6), /* External Oscillator */ -} OSC_PLLSRC_t; - - -/* --------------------------------------------------------------------------- -DFLL - DFLL --------------------------------------------------------------------------- -*/ - -/* DFLL */ -typedef struct DFLL_struct -{ - register8_t CTRL; /* Control Register */ - register8_t reserved_0x01; - register8_t CALA; /* Calibration Register A */ - register8_t CALB; /* Calibration Register B */ - register8_t COMP0; /* Oscillator Compare Register 0 */ - register8_t COMP1; /* Oscillator Compare Register 1 */ - register8_t COMP2; /* Oscillator Compare Register 2 */ - register8_t reserved_0x07; -} DFLL_t; - - -/* --------------------------------------------------------------------------- -RST - Reset --------------------------------------------------------------------------- -*/ - -/* Reset */ -typedef struct RST_struct -{ - register8_t STATUS; /* Status Register */ - register8_t CTRL; /* Control Register */ -} RST_t; - - -/* --------------------------------------------------------------------------- -WDT - Watch-Dog Timer --------------------------------------------------------------------------- -*/ - -/* Watch-Dog Timer */ -typedef struct WDT_struct -{ - register8_t CTRL; /* Control */ - register8_t WINCTRL; /* Windowed Mode Control */ - register8_t STATUS; /* Status */ -} WDT_t; - -/* Period setting */ -typedef enum WDT_PER_enum -{ - WDT_PER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ - WDT_PER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ - WDT_PER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ - WDT_PER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ - WDT_PER_128CLK_gc = (0x04<<2), /* 128 cycles (0.125s @ 3.3V) */ - WDT_PER_256CLK_gc = (0x05<<2), /* 256 cycles (0.25s @ 3.3V) */ - WDT_PER_512CLK_gc = (0x06<<2), /* 512 cycles (0.5s @ 3.3V) */ - WDT_PER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ - WDT_PER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ - WDT_PER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ - WDT_PER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ -} WDT_PER_t; - -/* Closed window period */ -typedef enum WDT_WPER_enum -{ - WDT_WPER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ - WDT_WPER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ - WDT_WPER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ - WDT_WPER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ - WDT_WPER_128CLK_gc = (0x04<<2), /* 128 cycles (0.125s @ 3.3V) */ - WDT_WPER_256CLK_gc = (0x05<<2), /* 256 cycles (0.25s @ 3.3V) */ - WDT_WPER_512CLK_gc = (0x06<<2), /* 512 cycles (0.5s @ 3.3V) */ - WDT_WPER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ - WDT_WPER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ - WDT_WPER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ - WDT_WPER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ -} WDT_WPER_t; - - -/* --------------------------------------------------------------------------- -MCU - MCU Control --------------------------------------------------------------------------- -*/ - -/* MCU Control */ -typedef struct MCU_struct -{ - register8_t DEVID0; /* Device ID byte 0 */ - register8_t DEVID1; /* Device ID byte 1 */ - register8_t DEVID2; /* Device ID byte 2 */ - register8_t REVID; /* Revision ID */ - register8_t JTAGUID; /* JTAG User ID */ - register8_t reserved_0x05; - register8_t MCUCR; /* MCU Control */ - register8_t reserved_0x07; - register8_t EVSYSLOCK; /* Event System Lock */ - register8_t AWEXLOCK; /* AWEX Lock */ - register8_t reserved_0x0A; - register8_t reserved_0x0B; -} MCU_t; - - -/* --------------------------------------------------------------------------- -PMIC - Programmable Multi-level Interrupt Controller --------------------------------------------------------------------------- -*/ - -/* Programmable Multi-level Interrupt Controller */ -typedef struct PMIC_struct -{ - register8_t STATUS; /* Status Register */ - register8_t INTPRI; /* Interrupt Priority */ - register8_t CTRL; /* Control Register */ -} PMIC_t; - - -/* --------------------------------------------------------------------------- -DMA - DMA Controller --------------------------------------------------------------------------- -*/ - -/* DMA Channel */ -typedef struct DMA_CH_struct -{ - register8_t CTRLA; /* Channel Control */ - register8_t CTRLB; /* Channel Control */ - register8_t ADDRCTRL; /* Address Control */ - register8_t TRIGSRC; /* Channel Trigger Source */ - _WORDREGISTER(TRFCNT); /* Channel Block Transfer Count */ - register8_t REPCNT; /* Channel Repeat Count */ - register8_t reserved_0x07; - register8_t SRCADDR0; /* Channel Source Address 0 */ - register8_t SRCADDR1; /* Channel Source Address 1 */ - register8_t SRCADDR2; /* Channel Source Address 2 */ - register8_t reserved_0x0B; - register8_t DESTADDR0; /* Channel Destination Address 0 */ - register8_t DESTADDR1; /* Channel Destination Address 1 */ - register8_t DESTADDR2; /* Channel Destination Address 2 */ - register8_t reserved_0x0F; -} DMA_CH_t; - -/* --------------------------------------------------------------------------- -DMA - DMA Controller --------------------------------------------------------------------------- -*/ - -/* DMA Controller */ -typedef struct DMA_struct -{ - register8_t CTRL; /* Control */ - register8_t reserved_0x01; - register8_t reserved_0x02; - register8_t INTFLAGS; /* Transfer Interrupt Status */ - register8_t STATUS; /* Status */ - register8_t reserved_0x05; - _WORDREGISTER(TEMP); /* Temporary Register For 16/24-bit Access */ - register8_t reserved_0x08; - register8_t reserved_0x09; - register8_t reserved_0x0A; - register8_t reserved_0x0B; - register8_t reserved_0x0C; - register8_t reserved_0x0D; - register8_t reserved_0x0E; - register8_t reserved_0x0F; - DMA_CH_t CH0; /* DMA Channel 0 */ - DMA_CH_t CH1; /* DMA Channel 1 */ - DMA_CH_t CH2; /* DMA Channel 2 */ - DMA_CH_t CH3; /* DMA Channel 3 */ -} DMA_t; - -/* Burst mode */ -typedef enum DMA_CH_BURSTLEN_enum -{ - DMA_CH_BURSTLEN_1BYTE_gc = (0x00<<0), /* 1-byte burst mode */ - DMA_CH_BURSTLEN_2BYTE_gc = (0x01<<0), /* 2-byte burst mode */ - DMA_CH_BURSTLEN_4BYTE_gc = (0x02<<0), /* 4-byte burst mode */ - DMA_CH_BURSTLEN_8BYTE_gc = (0x03<<0), /* 8-byte burst mode */ -} DMA_CH_BURSTLEN_t; - -/* Source address reload mode */ -typedef enum DMA_CH_SRCRELOAD_enum -{ - DMA_CH_SRCRELOAD_NONE_gc = (0x00<<6), /* No reload */ - DMA_CH_SRCRELOAD_BLOCK_gc = (0x01<<6), /* Reload at end of block */ - DMA_CH_SRCRELOAD_BURST_gc = (0x02<<6), /* Reload at end of burst */ - DMA_CH_SRCRELOAD_TRANSACTION_gc = (0x03<<6), /* Reload at end of transaction */ -} DMA_CH_SRCRELOAD_t; - -/* Source addressing mode */ -typedef enum DMA_CH_SRCDIR_enum -{ - DMA_CH_SRCDIR_FIXED_gc = (0x00<<4), /* Fixed */ - DMA_CH_SRCDIR_INC_gc = (0x01<<4), /* Increment */ - DMA_CH_SRCDIR_DEC_gc = (0x02<<4), /* Decrement */ -} DMA_CH_SRCDIR_t; - -/* Destination adress reload mode */ -typedef enum DMA_CH_DESTRELOAD_enum -{ - DMA_CH_DESTRELOAD_NONE_gc = (0x00<<2), /* No reload */ - DMA_CH_DESTRELOAD_BLOCK_gc = (0x01<<2), /* Reload at end of block */ - DMA_CH_DESTRELOAD_BURST_gc = (0x02<<2), /* Reload at end of burst */ - DMA_CH_DESTRELOAD_TRANSACTION_gc = (0x03<<2), /* Reload at end of transaction */ -} DMA_CH_DESTRELOAD_t; - -/* Destination adressing mode */ -typedef enum DMA_CH_DESTDIR_enum -{ - DMA_CH_DESTDIR_FIXED_gc = (0x00<<0), /* Fixed */ - DMA_CH_DESTDIR_INC_gc = (0x01<<0), /* Increment */ - DMA_CH_DESTDIR_DEC_gc = (0x02<<0), /* Decrement */ -} DMA_CH_DESTDIR_t; - -/* Transfer trigger source */ -typedef enum DMA_CH_TRIGSRC_enum -{ - DMA_CH_TRIGSRC_OFF_gc = (0x00<<0), /* Off software triggers only */ - DMA_CH_TRIGSRC_EVSYS_CH0_gc = (0x01<<0), /* Event System Channel 0 */ - DMA_CH_TRIGSRC_EVSYS_CH1_gc = (0x02<<0), /* Event System Channel 1 */ - DMA_CH_TRIGSRC_EVSYS_CH2_gc = (0x03<<0), /* Event System Channel 2 */ - DMA_CH_TRIGSRC_ADCA_CH0_gc = (0x10<<0), /* ADCA Channel 0 */ - DMA_CH_TRIGSRC_ADCA_CH1_gc = (0x11<<0), /* ADCA Channel 1 */ - DMA_CH_TRIGSRC_ADCA_CH2_gc = (0x12<<0), /* ADCA Channel 2 */ - DMA_CH_TRIGSRC_ADCA_CH3_gc = (0x13<<0), /* ADCA Channel 3 */ - DMA_CH_TRIGSRC_ADCA_CH4_gc = (0x14<<0), /* ADCA Channel 0,1,2,3 combined */ - DMA_CH_TRIGSRC_DACA_CH0_gc = (0x15<<0), /* DACA Channel 0 */ - DMA_CH_TRIGSRC_DACA_CH1_gc = (0x16<<0), /* DACA Channel 1 */ - DMA_CH_TRIGSRC_ADCB_CH0_gc = (0x20<<0), /* ADCB Channel 0 */ - DMA_CH_TRIGSRC_ADCB_CH1_gc = (0x21<<0), /* ADCB Channel 1 */ - DMA_CH_TRIGSRC_ADCB_CH2_gc = (0x22<<0), /* ADCB Channel 2 */ - DMA_CH_TRIGSRC_ADCB_CH3_gc = (0x23<<0), /* ADCB Channel 3 */ - DMA_CH_TRIGSRC_ADCB_CH4_gc = (0x24<<0), /* ADCB Channel 0,1,2,3 combined */ - DMA_CH_TRIGSRC_DACB_CH0_gc = (0x25<<0), /* DACB Channel 0 */ - DMA_CH_TRIGSRC_DACB_CH1_gc = (0x26<<0), /* DACB Channel 1 */ - DMA_CH_TRIGSRC_TCC0_OVF_gc = (0x40<<0), /* Timer/Counter C0 Overflow */ - DMA_CH_TRIGSRC_TCC0_ERR_gc = (0x41<<0), /* Timer/Counter C0 Error */ - DMA_CH_TRIGSRC_TCC0_CCA_gc = (0x42<<0), /* Timer/Counter C0 Compare or Capture A */ - DMA_CH_TRIGSRC_TCC0_CCB_gc = (0x43<<0), /* Timer/Counter C0 Compare or Capture B */ - DMA_CH_TRIGSRC_TCC0_CCC_gc = (0x44<<0), /* Timer/Counter C0 Compare or Capture C */ - DMA_CH_TRIGSRC_TCC0_CCD_gc = (0x45<<0), /* Timer/Counter C0 Compare or Capture D */ - DMA_CH_TRIGSRC_TCC1_OVF_gc = (0x46<<0), /* Timer/Counter C1 Overflow */ - DMA_CH_TRIGSRC_TCC1_ERR_gc = (0x47<<0), /* Timer/Counter C1 Error */ - DMA_CH_TRIGSRC_TCC1_CCA_gc = (0x48<<0), /* Timer/Counter C1 Compare or Capture A */ - DMA_CH_TRIGSRC_TCC1_CCB_gc = (0x49<<0), /* Timer/Counter C1 Compare or Capture B */ - DMA_CH_TRIGSRC_SPIC_gc = (0x4A<<0), /* SPI C Transfer Complete */ - DMA_CH_TRIGSRC_USARTC0_RXC_gc = (0x4B<<0), /* USART C0 Receive Complete */ - DMA_CH_TRIGSRC_USARTC0_DRE_gc = (0x4C<<0), /* USART C0 Data Register Empty */ - DMA_CH_TRIGSRC_USARTC1_RXC_gc = (0x4E<<0), /* USART C1 Receive Complete */ - DMA_CH_TRIGSRC_USARTC1_DRE_gc = (0x4F<<0), /* USART C1 Data Register Empty */ - DMA_CH_TRIGSRC_TCD0_OVF_gc = (0x60<<0), /* Timer/Counter D0 Overflow */ - DMA_CH_TRIGSRC_TCD0_ERR_gc = (0x61<<0), /* Timer/Counter D0 Error */ - DMA_CH_TRIGSRC_TCD0_CCA_gc = (0x62<<0), /* Timer/Counter D0 Compare or Capture A */ - DMA_CH_TRIGSRC_TCD0_CCB_gc = (0x63<<0), /* Timer/Counter D0 Compare or Capture B */ - DMA_CH_TRIGSRC_TCD0_CCC_gc = (0x64<<0), /* Timer/Counter D0 Compare or Capture C */ - DMA_CH_TRIGSRC_TCD0_CCD_gc = (0x65<<0), /* Timer/Counter D0 Compare or Capture D */ - DMA_CH_TRIGSRC_TCD1_OVF_gc = (0x66<<0), /* Timer/Counter D1 Overflow */ - DMA_CH_TRIGSRC_TCD1_ERR_gc = (0x67<<0), /* Timer/Counter D1 Error */ - DMA_CH_TRIGSRC_TCD1_CCA_gc = (0x68<<0), /* Timer/Counter D1 Compare or Capture A */ - DMA_CH_TRIGSRC_TCD1_CCB_gc = (0x69<<0), /* Timer/Counter D1 Compare or Capture B */ - DMA_CH_TRIGSRC_SPID_gc = (0x6A<<0), /* SPI D Transfer Complete */ - DMA_CH_TRIGSRC_USARTD0_RXC_gc = (0x6B<<0), /* USART D0 Receive Complete */ - DMA_CH_TRIGSRC_USARTD0_DRE_gc = (0x6C<<0), /* USART D0 Data Register Empty */ - DMA_CH_TRIGSRC_USARTD1_RXC_gc = (0x6E<<0), /* USART D1 Receive Complete */ - DMA_CH_TRIGSRC_USARTD1_DRE_gc = (0x6F<<0), /* USART D1 Data Register Empty */ - DMA_CH_TRIGSRC_TCE0_OVF_gc = (0x80<<0), /* Timer/Counter E0 Overflow */ - DMA_CH_TRIGSRC_TCE0_ERR_gc = (0x81<<0), /* Timer/Counter E0 Error */ - DMA_CH_TRIGSRC_TCE0_CCA_gc = (0x82<<0), /* Timer/Counter E0 Compare or Capture A */ - DMA_CH_TRIGSRC_TCE0_CCB_gc = (0x83<<0), /* Timer/Counter E0 Compare or Capture B */ - DMA_CH_TRIGSRC_TCE0_CCC_gc = (0x84<<0), /* Timer/Counter E0 Compare or Capture C */ - DMA_CH_TRIGSRC_TCE0_CCD_gc = (0x85<<0), /* Timer/Counter E0 Compare or Capture D */ - DMA_CH_TRIGSRC_TCE1_OVF_gc = (0x86<<0), /* Timer/Counter E1 Overflow */ - DMA_CH_TRIGSRC_TCE1_ERR_gc = (0x87<<0), /* Timer/Counter E1 Error */ - DMA_CH_TRIGSRC_TCE1_CCA_gc = (0x88<<0), /* Timer/Counter E1 Compare or Capture A */ - DMA_CH_TRIGSRC_TCE1_CCB_gc = (0x89<<0), /* Timer/Counter E1 Compare or Capture B */ - DMA_CH_TRIGSRC_SPIE_gc = (0x8A<<0), /* SPI E Transfer Complete */ - DMA_CH_TRIGSRC_USARTE0_RXC_gc = (0x8B<<0), /* USART E0 Receive Complete */ - DMA_CH_TRIGSRC_USARTE0_DRE_gc = (0x8C<<0), /* USART E0 Data Register Empty */ - DMA_CH_TRIGSRC_USARTE1_RXC_gc = (0x8E<<0), /* USART E1 Receive Complete */ - DMA_CH_TRIGSRC_USARTE1_DRE_gc = (0x8F<<0), /* USART E1 Data Register Empty */ - DMA_CH_TRIGSRC_TCF0_OVF_gc = (0xA0<<0), /* Timer/Counter F0 Overflow */ - DMA_CH_TRIGSRC_TCF0_ERR_gc = (0xA1<<0), /* Timer/Counter F0 Error */ - DMA_CH_TRIGSRC_TCF0_CCA_gc = (0xA2<<0), /* Timer/Counter F0 Compare or Capture A */ - DMA_CH_TRIGSRC_TCF0_CCB_gc = (0xA3<<0), /* Timer/Counter F0 Compare or Capture B */ - DMA_CH_TRIGSRC_TCF0_CCC_gc = (0xA4<<0), /* Timer/Counter F0 Compare or Capture C */ - DMA_CH_TRIGSRC_TCF0_CCD_gc = (0xA5<<0), /* Timer/Counter F0 Compare or Capture D */ - DMA_CH_TRIGSRC_TCF1_OVF_gc = (0xA6<<0), /* Timer/Counter F1 Overflow */ - DMA_CH_TRIGSRC_TCF1_ERR_gc = (0xA7<<0), /* Timer/Counter F1 Error */ - DMA_CH_TRIGSRC_TCF1_CCA_gc = (0xA8<<0), /* Timer/Counter F1 Compare or Capture A */ - DMA_CH_TRIGSRC_TCF1_CCB_gc = (0xA9<<0), /* Timer/Counter F1 Compare or Capture B */ - DMA_CH_TRIGSRC_SPIF_gc = (0xAA<<0), /* SPI F Transfer Complete */ - DMA_CH_TRIGSRC_USARTF0_RXC_gc = (0xAB<<0), /* USART F0 Receive Complete */ - DMA_CH_TRIGSRC_USARTF0_DRE_gc = (0xAC<<0), /* USART F0 Data Register Empty */ - DMA_CH_TRIGSRC_USARTF1_RXC_gc = (0xAE<<0), /* USART F1 Receive Complete */ - DMA_CH_TRIGSRC_USARTF1_DRE_gc = (0xAF<<0), /* USART F1 Data Register Empty */ -} DMA_CH_TRIGSRC_t; - -/* Double buffering mode */ -typedef enum DMA_DBUFMODE_enum -{ - DMA_DBUFMODE_DISABLED_gc = (0x00<<2), /* Double buffering disabled */ - DMA_DBUFMODE_CH01_gc = (0x01<<2), /* Double buffering enabled on channel 0/1 */ - DMA_DBUFMODE_CH23_gc = (0x02<<2), /* Double buffering enabled on channel 2/3 */ - DMA_DBUFMODE_CH01CH23_gc = (0x03<<2), /* Double buffering enabled on ch. 0/1 and ch. 2/3 */ -} DMA_DBUFMODE_t; - -/* Priority mode */ -typedef enum DMA_PRIMODE_enum -{ - DMA_PRIMODE_RR0123_gc = (0x00<<0), /* Round Robin */ - DMA_PRIMODE_CH0RR123_gc = (0x01<<0), /* Channel 0 > Round Robin on channel 1/2/3 */ - DMA_PRIMODE_CH01RR23_gc = (0x02<<0), /* Channel 0 > channel 1 > Round Robin on channel 2/3 */ - DMA_PRIMODE_CH0123_gc = (0x03<<0), /* Channel 0 > channel 1 > channel 2 > channel 3 */ -} DMA_PRIMODE_t; - -/* Interrupt level */ -typedef enum DMA_CH_ERRINTLVL_enum -{ - DMA_CH_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ - DMA_CH_ERRINTLVL_LO_gc = (0x01<<2), /* Low level */ - DMA_CH_ERRINTLVL_MED_gc = (0x02<<2), /* Medium level */ - DMA_CH_ERRINTLVL_HI_gc = (0x03<<2), /* High level */ -} DMA_CH_ERRINTLVL_t; - -/* Interrupt level */ -typedef enum DMA_CH_TRNINTLVL_enum -{ - DMA_CH_TRNINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ - DMA_CH_TRNINTLVL_LO_gc = (0x01<<0), /* Low level */ - DMA_CH_TRNINTLVL_MED_gc = (0x02<<0), /* Medium level */ - DMA_CH_TRNINTLVL_HI_gc = (0x03<<0), /* High level */ -} DMA_CH_TRNINTLVL_t; - - -/* --------------------------------------------------------------------------- -EVSYS - Event System --------------------------------------------------------------------------- -*/ - -/* Event System */ -typedef struct EVSYS_struct -{ - register8_t CH0MUX; /* Event Channel 0 Multiplexer */ - register8_t CH1MUX; /* Event Channel 1 Multiplexer */ - register8_t CH2MUX; /* Event Channel 2 Multiplexer */ - register8_t CH3MUX; /* Event Channel 3 Multiplexer */ - register8_t CH4MUX; /* Event Channel 4 Multiplexer */ - register8_t CH5MUX; /* Event Channel 5 Multiplexer */ - register8_t CH6MUX; /* Event Channel 6 Multiplexer */ - register8_t CH7MUX; /* Event Channel 7 Multiplexer */ - register8_t CH0CTRL; /* Channel 0 Control Register */ - register8_t CH1CTRL; /* Channel 1 Control Register */ - register8_t CH2CTRL; /* Channel 2 Control Register */ - register8_t CH3CTRL; /* Channel 3 Control Register */ - register8_t CH4CTRL; /* Channel 4 Control Register */ - register8_t CH5CTRL; /* Channel 5 Control Register */ - register8_t CH6CTRL; /* Channel 6 Control Register */ - register8_t CH7CTRL; /* Channel 7 Control Register */ - register8_t STROBE; /* Event Strobe */ - register8_t DATA; /* Event Data */ -} EVSYS_t; - -/* Quadrature Decoder Index Recognition Mode */ -typedef enum EVSYS_QDIRM_enum -{ - EVSYS_QDIRM_00_gc = (0x00<<5), /* QDPH0 = 0, QDPH90 = 0 */ - EVSYS_QDIRM_01_gc = (0x01<<5), /* QDPH0 = 0, QDPH90 = 1 */ - EVSYS_QDIRM_10_gc = (0x02<<5), /* QDPH0 = 1, QDPH90 = 0 */ - EVSYS_QDIRM_11_gc = (0x03<<5), /* QDPH0 = 1, QDPH90 = 1 */ -} EVSYS_QDIRM_t; - -/* Digital filter coefficient */ -typedef enum EVSYS_DIGFILT_enum -{ - EVSYS_DIGFILT_1SAMPLE_gc = (0x00<<0), /* 1 SAMPLE */ - EVSYS_DIGFILT_2SAMPLES_gc = (0x01<<0), /* 2 SAMPLES */ - EVSYS_DIGFILT_3SAMPLES_gc = (0x02<<0), /* 3 SAMPLES */ - EVSYS_DIGFILT_4SAMPLES_gc = (0x03<<0), /* 4 SAMPLES */ - EVSYS_DIGFILT_5SAMPLES_gc = (0x04<<0), /* 5 SAMPLES */ - EVSYS_DIGFILT_6SAMPLES_gc = (0x05<<0), /* 6 SAMPLES */ - EVSYS_DIGFILT_7SAMPLES_gc = (0x06<<0), /* 7 SAMPLES */ - EVSYS_DIGFILT_8SAMPLES_gc = (0x07<<0), /* 8 SAMPLES */ -} EVSYS_DIGFILT_t; - -/* Event Channel multiplexer input selection */ -typedef enum EVSYS_CHMUX_enum -{ - EVSYS_CHMUX_OFF_gc = (0x00<<0), /* Off */ - EVSYS_CHMUX_RTC_OVF_gc = (0x08<<0), /* RTC Overflow */ - EVSYS_CHMUX_RTC_CMP_gc = (0x09<<0), /* RTC Compare Match */ - EVSYS_CHMUX_ACA_CH0_gc = (0x10<<0), /* Analog Comparator A Channel 0 */ - EVSYS_CHMUX_ACA_CH1_gc = (0x11<<0), /* Analog Comparator A Channel 1 */ - EVSYS_CHMUX_ACA_WIN_gc = (0x12<<0), /* Analog Comparator A Window */ - EVSYS_CHMUX_ACB_CH0_gc = (0x13<<0), /* Analog Comparator B Channel 0 */ - EVSYS_CHMUX_ACB_CH1_gc = (0x14<<0), /* Analog Comparator B Channel 1 */ - EVSYS_CHMUX_ACB_WIN_gc = (0x15<<0), /* Analog Comparator B Window */ - EVSYS_CHMUX_ADCA_CH0_gc = (0x20<<0), /* ADC A Channel 0 */ - EVSYS_CHMUX_ADCA_CH1_gc = (0x21<<0), /* ADC A Channel 1 */ - EVSYS_CHMUX_ADCA_CH2_gc = (0x22<<0), /* ADC A Channel 2 */ - EVSYS_CHMUX_ADCA_CH3_gc = (0x23<<0), /* ADC A Channel 3 */ - EVSYS_CHMUX_ADCB_CH0_gc = (0x24<<0), /* ADC B Channel 0 */ - EVSYS_CHMUX_ADCB_CH1_gc = (0x25<<0), /* ADC B Channel 1 */ - EVSYS_CHMUX_ADCB_CH2_gc = (0x26<<0), /* ADC B Channel 2 */ - EVSYS_CHMUX_ADCB_CH3_gc = (0x27<<0), /* ADC B Channel 3 */ - EVSYS_CHMUX_PORTA_PIN0_gc = (0x50<<0), /* Port A, Pin0 */ - EVSYS_CHMUX_PORTA_PIN1_gc = (0x51<<0), /* Port A, Pin1 */ - EVSYS_CHMUX_PORTA_PIN2_gc = (0x52<<0), /* Port A, Pin2 */ - EVSYS_CHMUX_PORTA_PIN3_gc = (0x53<<0), /* Port A, Pin3 */ - EVSYS_CHMUX_PORTA_PIN4_gc = (0x54<<0), /* Port A, Pin4 */ - EVSYS_CHMUX_PORTA_PIN5_gc = (0x55<<0), /* Port A, Pin5 */ - EVSYS_CHMUX_PORTA_PIN6_gc = (0x56<<0), /* Port A, Pin6 */ - EVSYS_CHMUX_PORTA_PIN7_gc = (0x57<<0), /* Port A, Pin7 */ - EVSYS_CHMUX_PORTB_PIN0_gc = (0x58<<0), /* Port B, Pin0 */ - EVSYS_CHMUX_PORTB_PIN1_gc = (0x59<<0), /* Port B, Pin1 */ - EVSYS_CHMUX_PORTB_PIN2_gc = (0x5A<<0), /* Port B, Pin2 */ - EVSYS_CHMUX_PORTB_PIN3_gc = (0x5B<<0), /* Port B, Pin3 */ - EVSYS_CHMUX_PORTB_PIN4_gc = (0x5C<<0), /* Port B, Pin4 */ - EVSYS_CHMUX_PORTB_PIN5_gc = (0x5D<<0), /* Port B, Pin5 */ - EVSYS_CHMUX_PORTB_PIN6_gc = (0x5E<<0), /* Port B, Pin6 */ - EVSYS_CHMUX_PORTB_PIN7_gc = (0x5F<<0), /* Port B, Pin7 */ - EVSYS_CHMUX_PORTC_PIN0_gc = (0x60<<0), /* Port C, Pin0 */ - EVSYS_CHMUX_PORTC_PIN1_gc = (0x61<<0), /* Port C, Pin1 */ - EVSYS_CHMUX_PORTC_PIN2_gc = (0x62<<0), /* Port C, Pin2 */ - EVSYS_CHMUX_PORTC_PIN3_gc = (0x63<<0), /* Port C, Pin3 */ - EVSYS_CHMUX_PORTC_PIN4_gc = (0x64<<0), /* Port C, Pin4 */ - EVSYS_CHMUX_PORTC_PIN5_gc = (0x65<<0), /* Port C, Pin5 */ - EVSYS_CHMUX_PORTC_PIN6_gc = (0x66<<0), /* Port C, Pin6 */ - EVSYS_CHMUX_PORTC_PIN7_gc = (0x67<<0), /* Port C, Pin7 */ - EVSYS_CHMUX_PORTD_PIN0_gc = (0x68<<0), /* Port D, Pin0 */ - EVSYS_CHMUX_PORTD_PIN1_gc = (0x69<<0), /* Port D, Pin1 */ - EVSYS_CHMUX_PORTD_PIN2_gc = (0x6A<<0), /* Port D, Pin2 */ - EVSYS_CHMUX_PORTD_PIN3_gc = (0x6B<<0), /* Port D, Pin3 */ - EVSYS_CHMUX_PORTD_PIN4_gc = (0x6C<<0), /* Port D, Pin4 */ - EVSYS_CHMUX_PORTD_PIN5_gc = (0x6D<<0), /* Port D, Pin5 */ - EVSYS_CHMUX_PORTD_PIN6_gc = (0x6E<<0), /* Port D, Pin6 */ - EVSYS_CHMUX_PORTD_PIN7_gc = (0x6F<<0), /* Port D, Pin7 */ - EVSYS_CHMUX_PORTE_PIN0_gc = (0x70<<0), /* Port E, Pin0 */ - EVSYS_CHMUX_PORTE_PIN1_gc = (0x71<<0), /* Port E, Pin1 */ - EVSYS_CHMUX_PORTE_PIN2_gc = (0x72<<0), /* Port E, Pin2 */ - EVSYS_CHMUX_PORTE_PIN3_gc = (0x73<<0), /* Port E, Pin3 */ - EVSYS_CHMUX_PORTE_PIN4_gc = (0x74<<0), /* Port E, Pin4 */ - EVSYS_CHMUX_PORTE_PIN5_gc = (0x75<<0), /* Port E, Pin5 */ - EVSYS_CHMUX_PORTE_PIN6_gc = (0x76<<0), /* Port E, Pin6 */ - EVSYS_CHMUX_PORTE_PIN7_gc = (0x77<<0), /* Port E, Pin7 */ - EVSYS_CHMUX_PORTF_PIN0_gc = (0x78<<0), /* Port F, Pin0 */ - EVSYS_CHMUX_PORTF_PIN1_gc = (0x79<<0), /* Port F, Pin1 */ - EVSYS_CHMUX_PORTF_PIN2_gc = (0x7A<<0), /* Port F, Pin2 */ - EVSYS_CHMUX_PORTF_PIN3_gc = (0x7B<<0), /* Port F, Pin3 */ - EVSYS_CHMUX_PORTF_PIN4_gc = (0x7C<<0), /* Port F, Pin4 */ - EVSYS_CHMUX_PORTF_PIN5_gc = (0x7D<<0), /* Port F, Pin5 */ - EVSYS_CHMUX_PORTF_PIN6_gc = (0x7E<<0), /* Port F, Pin6 */ - EVSYS_CHMUX_PORTF_PIN7_gc = (0x7F<<0), /* Port F, Pin7 */ - EVSYS_CHMUX_PRESCALER_1_gc = (0x80<<0), /* Prescaler, divide by 1 */ - EVSYS_CHMUX_PRESCALER_2_gc = (0x81<<0), /* Prescaler, divide by 2 */ - EVSYS_CHMUX_PRESCALER_4_gc = (0x82<<0), /* Prescaler, divide by 4 */ - EVSYS_CHMUX_PRESCALER_8_gc = (0x83<<0), /* Prescaler, divide by 8 */ - EVSYS_CHMUX_PRESCALER_16_gc = (0x84<<0), /* Prescaler, divide by 16 */ - EVSYS_CHMUX_PRESCALER_32_gc = (0x85<<0), /* Prescaler, divide by 32 */ - EVSYS_CHMUX_PRESCALER_64_gc = (0x86<<0), /* Prescaler, divide by 64 */ - EVSYS_CHMUX_PRESCALER_128_gc = (0x87<<0), /* Prescaler, divide by 128 */ - EVSYS_CHMUX_PRESCALER_256_gc = (0x88<<0), /* Prescaler, divide by 256 */ - EVSYS_CHMUX_PRESCALER_512_gc = (0x89<<0), /* Prescaler, divide by 512 */ - EVSYS_CHMUX_PRESCALER_1024_gc = (0x8A<<0), /* Prescaler, divide by 1024 */ - EVSYS_CHMUX_PRESCALER_2048_gc = (0x8B<<0), /* Prescaler, divide by 2048 */ - EVSYS_CHMUX_PRESCALER_4096_gc = (0x8C<<0), /* Prescaler, divide by 4096 */ - EVSYS_CHMUX_PRESCALER_8192_gc = (0x8D<<0), /* Prescaler, divide by 8192 */ - EVSYS_CHMUX_PRESCALER_16384_gc = (0x8E<<0), /* Prescaler, divide by 16384 */ - EVSYS_CHMUX_PRESCALER_32768_gc = (0x8F<<0), /* Prescaler, divide by 32768 */ - EVSYS_CHMUX_TCC0_OVF_gc = (0xC0<<0), /* Timer/Counter C0 Overflow */ - EVSYS_CHMUX_TCC0_ERR_gc = (0xC1<<0), /* Timer/Counter C0 Error */ - EVSYS_CHMUX_TCC0_CCA_gc = (0xC4<<0), /* Timer/Counter C0 Compare or Capture A */ - EVSYS_CHMUX_TCC0_CCB_gc = (0xC5<<0), /* Timer/Counter C0 Compare or Capture B */ - EVSYS_CHMUX_TCC0_CCC_gc = (0xC6<<0), /* Timer/Counter C0 Compare or Capture C */ - EVSYS_CHMUX_TCC0_CCD_gc = (0xC7<<0), /* Timer/Counter C0 Compare or Capture D */ - EVSYS_CHMUX_TCC1_OVF_gc = (0xC8<<0), /* Timer/Counter C1 Overflow */ - EVSYS_CHMUX_TCC1_ERR_gc = (0xC9<<0), /* Timer/Counter C1 Error */ - EVSYS_CHMUX_TCC1_CCA_gc = (0xCC<<0), /* Timer/Counter C1 Compare or Capture A */ - EVSYS_CHMUX_TCC1_CCB_gc = (0xCD<<0), /* Timer/Counter C1 Compare or Capture B */ - EVSYS_CHMUX_TCD0_OVF_gc = (0xD0<<0), /* Timer/Counter D0 Overflow */ - EVSYS_CHMUX_TCD0_ERR_gc = (0xD1<<0), /* Timer/Counter D0 Error */ - EVSYS_CHMUX_TCD0_CCA_gc = (0xD4<<0), /* Timer/Counter D0 Compare or Capture A */ - EVSYS_CHMUX_TCD0_CCB_gc = (0xD5<<0), /* Timer/Counter D0 Compare or Capture B */ - EVSYS_CHMUX_TCD0_CCC_gc = (0xD6<<0), /* Timer/Counter D0 Compare or Capture C */ - EVSYS_CHMUX_TCD0_CCD_gc = (0xD7<<0), /* Timer/Counter D0 Compare or Capture D */ - EVSYS_CHMUX_TCD1_OVF_gc = (0xD8<<0), /* Timer/Counter D1 Overflow */ - EVSYS_CHMUX_TCD1_ERR_gc = (0xD9<<0), /* Timer/Counter D1 Error */ - EVSYS_CHMUX_TCD1_CCA_gc = (0xDC<<0), /* Timer/Counter D1 Compare or Capture A */ - EVSYS_CHMUX_TCD1_CCB_gc = (0xDD<<0), /* Timer/Counter D1 Compare or Capture B */ - EVSYS_CHMUX_TCE0_OVF_gc = (0xE0<<0), /* Timer/Counter E0 Overflow */ - EVSYS_CHMUX_TCE0_ERR_gc = (0xE1<<0), /* Timer/Counter E0 Error */ - EVSYS_CHMUX_TCE0_CCA_gc = (0xE4<<0), /* Timer/Counter E0 Compare or Capture A */ - EVSYS_CHMUX_TCE0_CCB_gc = (0xE5<<0), /* Timer/Counter E0 Compare or Capture B */ - EVSYS_CHMUX_TCE0_CCC_gc = (0xE6<<0), /* Timer/Counter E0 Compare or Capture C */ - EVSYS_CHMUX_TCE0_CCD_gc = (0xE7<<0), /* Timer/Counter E0 Compare or Capture D */ - EVSYS_CHMUX_TCE1_OVF_gc = (0xE8<<0), /* Timer/Counter E1 Overflow */ - EVSYS_CHMUX_TCE1_ERR_gc = (0xE9<<0), /* Timer/Counter E1 Error */ - EVSYS_CHMUX_TCE1_CCA_gc = (0xEC<<0), /* Timer/Counter E1 Compare or Capture A */ - EVSYS_CHMUX_TCE1_CCB_gc = (0xED<<0), /* Timer/Counter E1 Compare or Capture B */ - EVSYS_CHMUX_TCF0_OVF_gc = (0xF0<<0), /* Timer/Counter F0 Overflow */ - EVSYS_CHMUX_TCF0_ERR_gc = (0xF1<<0), /* Timer/Counter F0 Error */ - EVSYS_CHMUX_TCF0_CCA_gc = (0xF4<<0), /* Timer/Counter F0 Compare or Capture A */ - EVSYS_CHMUX_TCF0_CCB_gc = (0xF5<<0), /* Timer/Counter F0 Compare or Capture B */ - EVSYS_CHMUX_TCF0_CCC_gc = (0xF6<<0), /* Timer/Counter F0 Compare or Capture C */ - EVSYS_CHMUX_TCF0_CCD_gc = (0xF7<<0), /* Timer/Counter F0 Compare or Capture D */ - EVSYS_CHMUX_TCF1_OVF_gc = (0xF8<<0), /* Timer/Counter F1 Overflow */ - EVSYS_CHMUX_TCF1_ERR_gc = (0xF9<<0), /* Timer/Counter F1 Error */ - EVSYS_CHMUX_TCF1_CCA_gc = (0xFC<<0), /* Timer/Counter F1 Compare or Capture A */ - EVSYS_CHMUX_TCF1_CCB_gc = (0xFD<<0), /* Timer/Counter F1 Compare or Capture B */ -} EVSYS_CHMUX_t; - - -/* --------------------------------------------------------------------------- -NVM - Non Volatile Memory Controller --------------------------------------------------------------------------- -*/ - -/* Non-volatile Memory Controller */ -typedef struct NVM_struct -{ - register8_t ADDR0; /* Address Register 0 */ - register8_t ADDR1; /* Address Register 1 */ - register8_t ADDR2; /* Address Register 2 */ - register8_t reserved_0x03; - register8_t DATA0; /* Data Register 0 */ - register8_t DATA1; /* Data Register 1 */ - register8_t DATA2; /* Data Register 2 */ - register8_t reserved_0x07; - register8_t reserved_0x08; - register8_t reserved_0x09; - register8_t CMD; /* Command */ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t INTCTRL; /* Interrupt Control */ - register8_t reserved_0x0E; - register8_t STATUS; /* Status */ - register8_t LOCK_BITS; /* Lock Bits */ -} NVM_t; - -/* --------------------------------------------------------------------------- -NVM - Non Volatile Memory Controller --------------------------------------------------------------------------- -*/ - -/* Lock Bits */ -typedef struct NVM_LOCKBITS_struct -{ - register8_t LOCKBITS; /* Lock Bits */ -} NVM_LOCKBITS_t; - -/* --------------------------------------------------------------------------- -NVM - Non Volatile Memory Controller --------------------------------------------------------------------------- -*/ - -/* Fuses */ -typedef struct NVM_FUSES_struct -{ - register8_t FUSEBYTE0; /* User ID */ - register8_t FUSEBYTE1; /* Watchdog Configuration */ - register8_t FUSEBYTE2; /* Reset Configuration */ - register8_t reserved_0x03; - register8_t FUSEBYTE4; /* Start-up Configuration */ - register8_t FUSEBYTE5; /* EESAVE and BOD Level */ -} NVM_FUSES_t; - -/* --------------------------------------------------------------------------- -NVM - Non Volatile Memory Controller --------------------------------------------------------------------------- -*/ - -/* Production Signatures */ -typedef struct NVM_PROD_SIGNATURES_struct -{ - register8_t RCOSC2M; /* RCOSC 2MHz Calibration Value */ - register8_t reserved_0x01; - register8_t RCOSC32K; /* RCOSC 32kHz Calibration Value */ - register8_t RCOSC32M; /* RCOSC 32MHz Calibration Value */ - register8_t reserved_0x04; - register8_t reserved_0x05; - register8_t reserved_0x06; - register8_t reserved_0x07; - register8_t LOTNUM0; /* Lot Number Byte 0, ASCII */ - register8_t LOTNUM1; /* Lot Number Byte 1, ASCII */ - register8_t LOTNUM2; /* Lot Number Byte 2, ASCII */ - register8_t LOTNUM3; /* Lot Number Byte 3, ASCII */ - register8_t LOTNUM4; /* Lot Number Byte 4, ASCII */ - register8_t LOTNUM5; /* Lot Number Byte 5, ASCII */ - register8_t reserved_0x0E; - register8_t reserved_0x0F; - register8_t WAFNUM; /* Wafer Number */ - register8_t reserved_0x11; - register8_t COORDX0; /* Wafer Coordinate X Byte 0 */ - register8_t COORDX1; /* Wafer Coordinate X Byte 1 */ - register8_t COORDY0; /* Wafer Coordinate Y Byte 0 */ - register8_t COORDY1; /* Wafer Coordinate Y Byte 1 */ - register8_t reserved_0x16; - register8_t reserved_0x17; - register8_t reserved_0x18; - register8_t reserved_0x19; - register8_t reserved_0x1A; - register8_t reserved_0x1B; - register8_t reserved_0x1C; - register8_t reserved_0x1D; - register8_t reserved_0x1E; - register8_t reserved_0x1F; - register8_t ADCACAL0; /* ADCA Calibration Byte 0 */ - register8_t ADCACAL1; /* ADCA Calibration Byte 1 */ - register8_t reserved_0x22; - register8_t reserved_0x23; - register8_t ADCBCAL0; /* ADCB Calibration Byte 0 */ - register8_t ADCBCAL1; /* ADCB Calibration Byte 1 */ - register8_t reserved_0x26; - register8_t reserved_0x27; - register8_t reserved_0x28; - register8_t reserved_0x29; - register8_t reserved_0x2A; - register8_t reserved_0x2B; - register8_t reserved_0x2C; - register8_t reserved_0x2D; - register8_t TEMPSENSE0; /* Temperature Sensor Calibration Byte 0 */ - register8_t TEMPSENSE1; /* Temperature Sensor Calibration Byte 0 */ - register8_t DACAOFFCAL; /* DACA Calibration Byte 0 */ - register8_t DACAGAINCAL; /* DACA Calibration Byte 1 */ - register8_t DACBOFFCAL; /* DACB Calibration Byte 0 */ - register8_t DACBGAINCAL; /* DACB Calibration Byte 1 */ - register8_t reserved_0x34; - register8_t reserved_0x35; - register8_t reserved_0x36; - register8_t reserved_0x37; - register8_t reserved_0x38; - register8_t reserved_0x39; - register8_t reserved_0x3A; - register8_t reserved_0x3B; - register8_t reserved_0x3C; - register8_t reserved_0x3D; - register8_t reserved_0x3E; -} NVM_PROD_SIGNATURES_t; - -/* NVM Command */ -typedef enum NVM_CMD_enum -{ - NVM_CMD_NO_OPERATION_gc = (0x00<<0), /* Noop/Ordinary LPM */ - NVM_CMD_READ_CALIB_ROW_gc = (0x02<<0), /* Read calibration row */ - NVM_CMD_READ_USER_SIG_ROW_gc = (0x01<<0), /* Read user signature row */ - NVM_CMD_READ_EEPROM_gc = (0x06<<0), /* Read EEPROM */ - NVM_CMD_READ_FUSES_gc = (0x07<<0), /* Read fuse byte */ - NVM_CMD_WRITE_LOCK_BITS_gc = (0x08<<0), /* Write lock bits */ - NVM_CMD_ERASE_USER_SIG_ROW_gc = (0x18<<0), /* Erase user signature row */ - NVM_CMD_WRITE_USER_SIG_ROW_gc = (0x1A<<0), /* Write user signature row */ - NVM_CMD_ERASE_APP_gc = (0x20<<0), /* Erase Application Section */ - NVM_CMD_ERASE_APP_PAGE_gc = (0x22<<0), /* Erase Application Section page */ - NVM_CMD_LOAD_FLASH_BUFFER_gc = (0x23<<0), /* Load Flash page buffer */ - NVM_CMD_WRITE_APP_PAGE_gc = (0x24<<0), /* Write Application Section page */ - NVM_CMD_ERASE_WRITE_APP_PAGE_gc = (0x25<<0), /* Erase-and-write Application Section page */ - NVM_CMD_ERASE_FLASH_BUFFER_gc = (0x26<<0), /* Erase/flush Flash page buffer */ - NVM_CMD_ERASE_BOOT_PAGE_gc = (0x2A<<0), /* Erase Boot Section page */ - NVM_CMD_WRITE_BOOT_PAGE_gc = (0x2C<<0), /* Write Boot Section page */ - NVM_CMD_ERASE_WRITE_BOOT_PAGE_gc = (0x2D<<0), /* Erase-and-write Boot Section page */ - NVM_CMD_ERASE_EEPROM_gc = (0x30<<0), /* Erase EEPROM */ - NVM_CMD_ERASE_EEPROM_PAGE_gc = (0x32<<0), /* Erase EEPROM page */ - NVM_CMD_LOAD_EEPROM_BUFFER_gc = (0x33<<0), /* Load EEPROM page buffer */ - NVM_CMD_WRITE_EEPROM_PAGE_gc = (0x34<<0), /* Write EEPROM page */ - NVM_CMD_ERASE_WRITE_EEPROM_PAGE_gc = (0x35<<0), /* Erase-and-write EEPROM page */ - NVM_CMD_ERASE_EEPROM_BUFFER_gc = (0x36<<0), /* Erase/flush EEPROM page buffer */ - NVM_CMD_APP_CRC_gc = (0x38<<0), /* Generate Application section CRC */ - NVM_CMD_BOOT_CRC_gc = (0x39<<0), /* Generate Boot Section CRC */ - NVM_CMD_FLASH_RANGE_CRC_gc = (0x3A<<0), /* Generate Flash Range CRC */ -} NVM_CMD_t; - -/* SPM ready interrupt level */ -typedef enum NVM_SPMLVL_enum -{ - NVM_SPMLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ - NVM_SPMLVL_LO_gc = (0x01<<2), /* Low level */ - NVM_SPMLVL_MED_gc = (0x02<<2), /* Medium level */ - NVM_SPMLVL_HI_gc = (0x03<<2), /* High level */ -} NVM_SPMLVL_t; - -/* EEPROM ready interrupt level */ -typedef enum NVM_EELVL_enum -{ - NVM_EELVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ - NVM_EELVL_LO_gc = (0x01<<0), /* Low level */ - NVM_EELVL_MED_gc = (0x02<<0), /* Medium level */ - NVM_EELVL_HI_gc = (0x03<<0), /* High level */ -} NVM_EELVL_t; - -/* Boot lock bits - boot setcion */ -typedef enum NVM_BLBB_enum -{ - NVM_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ - NVM_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ - NVM_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ - NVM_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ -} NVM_BLBB_t; - -/* Boot lock bits - application section */ -typedef enum NVM_BLBA_enum -{ - NVM_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ - NVM_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ - NVM_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ - NVM_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ -} NVM_BLBA_t; - -/* Boot lock bits - application table section */ -typedef enum NVM_BLBAT_enum -{ - NVM_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ - NVM_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ - NVM_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ - NVM_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ -} NVM_BLBAT_t; - -/* Lock bits */ -typedef enum NVM_LB_enum -{ - NVM_LB_NOLOCK_gc = (0x03<<0), /* No locks */ - NVM_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ - NVM_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ -} NVM_LB_t; - -/* Boot Loader Section Reset Vector */ -typedef enum BOOTRST_enum -{ - BOOTRST_BOOTLDR_gc = (0x00<<6), /* Boot Loader Reset */ - BOOTRST_APPLICATION_gc = (0x01<<6), /* Application Reset */ -} BOOTRST_t; - -/* BOD operation */ -typedef enum BOD_enum -{ - BOD_INSAMPLEDMODE_gc = (0x01<<0), /* BOD enabled in sampled mode */ - BOD_CONTINOUSLY_gc = (0x02<<0), /* BOD enabled continuously */ - BOD_DISABLED_gc = (0x03<<0), /* BOD Disabled */ -} BOD_t; - -/* Watchdog (Window) Timeout Period */ -typedef enum WD_enum -{ - WD_8CLK_gc = (0x00<<4), /* 8 cycles (8ms @ 3.3V) */ - WD_16CLK_gc = (0x01<<4), /* 16 cycles (16ms @ 3.3V) */ - WD_32CLK_gc = (0x02<<4), /* 32 cycles (32ms @ 3.3V) */ - WD_64CLK_gc = (0x03<<4), /* 64 cycles (64ms @ 3.3V) */ - WD_128CLK_gc = (0x04<<4), /* 128 cycles (0.125s @ 3.3V) */ - WD_256CLK_gc = (0x05<<4), /* 256 cycles (0.25s @ 3.3V) */ - WD_512CLK_gc = (0x06<<4), /* 512 cycles (0.5s @ 3.3V) */ - WD_1KCLK_gc = (0x07<<4), /* 1K cycles (1s @ 3.3V) */ - WD_2KCLK_gc = (0x08<<4), /* 2K cycles (2s @ 3.3V) */ - WD_4KCLK_gc = (0x09<<4), /* 4K cycles (4s @ 3.3V) */ - WD_8KCLK_gc = (0x0A<<4), /* 8K cycles (8s @ 3.3V) */ -} WD_t; - -/* Start-up Time */ -typedef enum SUT_enum -{ - SUT_0MS_gc = (0x03<<2), /* 0 ms */ - SUT_4MS_gc = (0x01<<2), /* 4 ms */ - SUT_64MS_gc = (0x00<<2), /* 64 ms */ -} SUT_t; - -/* Brown Out Detection Voltage Level */ -typedef enum BODLVL_enum -{ - BODLVL_1V6_gc = (0x07<<0), /* 1.6 V */ - BODLVL_1V9_gc = (0x06<<0), /* 1.9 V */ - BODLVL_2V1_gc = (0x05<<0), /* 2.1 V */ - BODLVL_2V4_gc = (0x04<<0), /* 2.4 V */ - BODLVL_2V7_gc = (0x03<<0), /* 2.7 V */ - BODLVL_3V0_gc = (0x02<<0), /* 3.0 V */ - BODLVL_3V2_gc = (0x01<<0), /* 3.2 V */ - BODLVL_3V5_gc = (0x00<<0), /* 3.5 V */ -} BODLVL_t; - - -/* --------------------------------------------------------------------------- -AC - Analog Comparator --------------------------------------------------------------------------- -*/ - -/* Analog Comparator */ -typedef struct AC_struct -{ - register8_t AC0CTRL; /* Comparator 0 Control */ - register8_t AC1CTRL; /* Comparator 1 Control */ - register8_t AC0MUXCTRL; /* Comparator 0 MUX Control */ - register8_t AC1MUXCTRL; /* Comparator 1 MUX Control */ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t WINCTRL; /* Window Mode Control */ - register8_t STATUS; /* Status */ -} AC_t; - -/* Interrupt mode */ -typedef enum AC_INTMODE_enum -{ - AC_INTMODE_BOTHEDGES_gc = (0x00<<6), /* Interrupt on both edges */ - AC_INTMODE_FALLING_gc = (0x02<<6), /* Interrupt on falling edge */ - AC_INTMODE_RISING_gc = (0x03<<6), /* Interrupt on rising edge */ -} AC_INTMODE_t; - -/* Interrupt level */ -typedef enum AC_INTLVL_enum -{ - AC_INTLVL_OFF_gc = (0x00<<4), /* Interrupt disabled */ - AC_INTLVL_LO_gc = (0x01<<4), /* Low level */ - AC_INTLVL_MED_gc = (0x02<<4), /* Medium level */ - AC_INTLVL_HI_gc = (0x03<<4), /* High level */ -} AC_INTLVL_t; - -/* Hysteresis mode selection */ -typedef enum AC_HYSMODE_enum -{ - AC_HYSMODE_NO_gc = (0x00<<1), /* No hysteresis */ - AC_HYSMODE_SMALL_gc = (0x01<<1), /* Small hysteresis */ - AC_HYSMODE_LARGE_gc = (0x02<<1), /* Large hysteresis */ -} AC_HYSMODE_t; - -/* Positive input multiplexer selection */ -typedef enum AC_MUXPOS_enum -{ - AC_MUXPOS_PIN0_gc = (0x00<<3), /* Pin 0 */ - AC_MUXPOS_PIN1_gc = (0x01<<3), /* Pin 1 */ - AC_MUXPOS_PIN2_gc = (0x02<<3), /* Pin 2 */ - AC_MUXPOS_PIN3_gc = (0x03<<3), /* Pin 3 */ - AC_MUXPOS_PIN4_gc = (0x04<<3), /* Pin 4 */ - AC_MUXPOS_PIN5_gc = (0x05<<3), /* Pin 5 */ - AC_MUXPOS_PIN6_gc = (0x06<<3), /* Pin 6 */ - AC_MUXPOS_DAC_gc = (0x07<<3), /* DAC output */ -} AC_MUXPOS_t; - -/* Negative input multiplexer selection */ -typedef enum AC_MUXNEG_enum -{ - AC_MUXNEG_PIN0_gc = (0x00<<0), /* Pin 0 */ - AC_MUXNEG_PIN1_gc = (0x01<<0), /* Pin 1 */ - AC_MUXNEG_PIN3_gc = (0x02<<0), /* Pin 3 */ - AC_MUXNEG_PIN5_gc = (0x03<<0), /* Pin 5 */ - AC_MUXNEG_PIN7_gc = (0x04<<0), /* Pin 7 */ - AC_MUXNEG_DAC_gc = (0x05<<0), /* DAC output */ - AC_MUXNEG_BANDGAP_gc = (0x06<<0), /* Bandgap Reference */ - AC_MUXNEG_SCALER_gc = (0x07<<0), /* Internal voltage scaler */ -} AC_MUXNEG_t; - -/* Windows interrupt mode */ -typedef enum AC_WINTMODE_enum -{ - AC_WINTMODE_ABOVE_gc = (0x00<<2), /* Interrupt on above window */ - AC_WINTMODE_INSIDE_gc = (0x01<<2), /* Interrupt on inside window */ - AC_WINTMODE_BELOW_gc = (0x02<<2), /* Interrupt on below window */ - AC_WINTMODE_OUTSIDE_gc = (0x03<<2), /* Interrupt on outside window */ -} AC_WINTMODE_t; - -/* Window interrupt level */ -typedef enum AC_WINTLVL_enum -{ - AC_WINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ - AC_WINTLVL_LO_gc = (0x01<<0), /* Low priority */ - AC_WINTLVL_MED_gc = (0x02<<0), /* Medium priority */ - AC_WINTLVL_HI_gc = (0x03<<0), /* High priority */ -} AC_WINTLVL_t; - -/* Window mode state */ -typedef enum AC_WSTATE_enum -{ - AC_WSTATE_ABOVE_gc = (0x00<<6), /* Signal above window */ - AC_WSTATE_INSIDE_gc = (0x01<<6), /* Signal inside window */ - AC_WSTATE_BELOW_gc = (0x02<<6), /* Signal below window */ -} AC_WSTATE_t; - - -/* --------------------------------------------------------------------------- -ADC - Analog/Digital Converter --------------------------------------------------------------------------- -*/ - -/* ADC Channel */ -typedef struct ADC_CH_struct -{ - register8_t CTRL; /* Control Register */ - register8_t MUXCTRL; /* MUX Control */ - register8_t INTCTRL; /* Channel Interrupt Control */ - register8_t INTFLAGS; /* Interrupt Flags */ - _WORDREGISTER(RES); /* Channel Result */ - register8_t reserved_0x6; - register8_t reserved_0x7; -} ADC_CH_t; - -/* --------------------------------------------------------------------------- -ADC - Analog/Digital Converter --------------------------------------------------------------------------- -*/ - -/* Analog-to-Digital Converter */ -typedef struct ADC_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t REFCTRL; /* Reference Control */ - register8_t EVCTRL; /* Event Control */ - register8_t PRESCALER; /* Clock Prescaler */ - register8_t reserved_0x05; - register8_t INTFLAGS; /* Interrupt Flags */ - register8_t reserved_0x07; - register8_t reserved_0x08; - register8_t reserved_0x09; - register8_t reserved_0x0A; - register8_t reserved_0x0B; - _WORDREGISTER(CAL); /* Calibration Value */ - register8_t reserved_0x0E; - register8_t reserved_0x0F; - _WORDREGISTER(CH0RES); /* Channel 0 Result */ - _WORDREGISTER(CH1RES); /* Channel 1 Result */ - _WORDREGISTER(CH2RES); /* Channel 2 Result */ - _WORDREGISTER(CH3RES); /* Channel 3 Result */ - _WORDREGISTER(CMP); /* Compare Value */ - register8_t reserved_0x1A; - register8_t reserved_0x1B; - register8_t reserved_0x1C; - register8_t reserved_0x1D; - register8_t reserved_0x1E; - register8_t reserved_0x1F; - ADC_CH_t CH0; /* ADC Channel 0 */ - ADC_CH_t CH1; /* ADC Channel 1 */ - ADC_CH_t CH2; /* ADC Channel 2 */ - ADC_CH_t CH3; /* ADC Channel 3 */ -} ADC_t; - -/* Positive input multiplexer selection */ -typedef enum ADC_CH_MUXPOS_enum -{ - ADC_CH_MUXPOS_PIN0_gc = (0x00<<3), /* Input pin 0 */ - ADC_CH_MUXPOS_PIN1_gc = (0x01<<3), /* Input pin 1 */ - ADC_CH_MUXPOS_PIN2_gc = (0x02<<3), /* Input pin 2 */ - ADC_CH_MUXPOS_PIN3_gc = (0x03<<3), /* Input pin 3 */ - ADC_CH_MUXPOS_PIN4_gc = (0x04<<3), /* Input pin 4 */ - ADC_CH_MUXPOS_PIN5_gc = (0x05<<3), /* Input pin 5 */ - ADC_CH_MUXPOS_PIN6_gc = (0x06<<3), /* Input pin 6 */ - ADC_CH_MUXPOS_PIN7_gc = (0x07<<3), /* Input pin 7 */ - ADC_CH_MUXPOS_PIN8_gc = (0x08<<3), /* Input pin 8 */ - ADC_CH_MUXPOS_PIN9_gc = (0x09<<3), /* Input pin 9 */ - ADC_CH_MUXPOS_PIN10_gc = (0x10<<3), /* Input pin 10 */ - ADC_CH_MUXPOS_PIN11_gc = (0x11<<3), /* Input pin 11 */ -} ADC_CH_MUXPOS_t; - -/* Internal input multiplexer selections */ -typedef enum ADC_CH_MUXINT_enum -{ - ADC_CH_MUXINT_TEMP_gc = (0x00<<3), /* Temperature Reference */ - ADC_CH_MUXINT_BANDGAP_gc = (0x01<<3), /* Bandgap Reference */ - ADC_CH_MUXINT_SCALEDVCC_gc = (0x02<<3), /* 1/10 scaled VCC */ - ADC_CH_MUXINT_DAC_gc = (0x03<<3), /* DAC output */ -} ADC_CH_MUXINT_t; - -/* Negative input multiplexer selection */ -typedef enum ADC_CH_MUXNEG_enum -{ - ADC_CH_MUXNEG_PIN0_gc = (0x00<<0), /* Input pin 0 */ - ADC_CH_MUXNEG_PIN1_gc = (0x01<<0), /* Input pin 1 */ - ADC_CH_MUXNEG_PIN2_gc = (0x02<<0), /* Input pin 2 */ - ADC_CH_MUXNEG_PIN3_gc = (0x03<<0), /* Input pin 3 */ - ADC_CH_MUXNEG_PIN4_gc = (0x04<<0), /* Input pin 4 */ - ADC_CH_MUXNEG_PIN5_gc = (0x05<<0), /* Input pin 5 */ - ADC_CH_MUXNEG_PIN6_gc = (0x06<<0), /* Input pin 6 */ - ADC_CH_MUXNEG_PIN7_gc = (0x07<<0), /* Input pin 7 */ -} ADC_CH_MUXNEG_t; - -/* Input mode */ -typedef enum ADC_CH_INPUTMODE_enum -{ - ADC_CH_INPUTMODE_INTERNAL_gc = (0x00<<0), /* Internal inputs, no gain */ - ADC_CH_INPUTMODE_SINGLEENDED_gc = (0x01<<0), /* Single-ended input, no gain */ - ADC_CH_INPUTMODE_DIFF_gc = (0x02<<0), /* Differential input, no gain */ - ADC_CH_INPUTMODE_DIFFWGAIN_gc = (0x03<<0), /* Differential input, with gain */ -} ADC_CH_INPUTMODE_t; - -/* Gain factor */ -typedef enum ADC_CH_GAIN_enum -{ - ADC_CH_GAIN_1X_gc = (0x00<<2), /* 1x gain */ - ADC_CH_GAIN_2X_gc = (0x01<<2), /* 2x gain */ - ADC_CH_GAIN_4X_gc = (0x02<<2), /* 4x gain */ - ADC_CH_GAIN_8X_gc = (0x03<<2), /* 8x gain */ - ADC_CH_GAIN_16X_gc = (0x04<<2), /* 16x gain */ - ADC_CH_GAIN_32X_gc = (0x05<<2), /* 32x gain */ - ADC_CH_GAIN_64X_gc = (0x06<<2), /* 64x gain */ -} ADC_CH_GAIN_t; - -/* Conversion result resolution */ -typedef enum ADC_RESOLUTION_enum -{ - ADC_RESOLUTION_12BIT_gc = (0x00<<1), /* 12-bit right-adjusted result */ - ADC_RESOLUTION_8BIT_gc = (0x02<<1), /* 8-bit right-adjusted result */ - ADC_RESOLUTION_LEFT12BIT_gc = (0x03<<1), /* 12-bit left-adjusted result */ -} ADC_RESOLUTION_t; - -/* Voltage reference selection */ -typedef enum ADC_REFSEL_enum -{ - ADC_REFSEL_INT1V_gc = (0x00<<4), /* Internal 1V */ - ADC_REFSEL_VCC_gc = (0x01<<4), /* Internal VCC / 1.6V */ - ADC_REFSEL_AREFA_gc = (0x02<<4), /* External reference on PORT A */ - ADC_REFSEL_AREFB_gc = (0x03<<4), /* External reference on PORT B */ -} ADC_REFSEL_t; - -/* Channel sweep selection */ -typedef enum ADC_SWEEP_enum -{ - ADC_SWEEP_0_gc = (0x00<<6), /* ADC Channel 0 */ - ADC_SWEEP_01_gc = (0x01<<6), /* ADC Channel 0,1 */ - ADC_SWEEP_012_gc = (0x02<<6), /* ADC Channel 0,1,2 */ - ADC_SWEEP_0123_gc = (0x03<<6), /* ADC Channel 0,1,2,3 */ -} ADC_SWEEP_t; - -/* Event channel input selection */ -typedef enum ADC_EVSEL_enum -{ - ADC_EVSEL_0123_gc = (0x00<<3), /* Event Channel 0,1,2,3 */ - ADC_EVSEL_1234_gc = (0x01<<3), /* Event Channel 1,2,3,4 */ - ADC_EVSEL_2345_gc = (0x02<<3), /* Event Channel 2,3,4,5 */ - ADC_EVSEL_3456_gc = (0x03<<3), /* Event Channel 3,4,5,6 */ - ADC_EVSEL_4567_gc = (0x04<<3), /* Event Channel 4,5,6,7 */ - ADC_EVSEL_567_gc = (0x05<<3), /* Event Channel 5,6,7 */ - ADC_EVSEL_67_gc = (0x06<<3), /* Event Channel 6,7 */ - ADC_EVSEL_7_gc = (0x07<<3), /* Event Channel 7 */ -} ADC_EVSEL_t; - -/* Event action selection */ -typedef enum ADC_EVACT_enum -{ - ADC_EVACT_NONE_gc = (0x00<<0), /* No event action */ - ADC_EVACT_CH0_gc = (0x01<<0), /* First event triggers channel 0 */ - ADC_EVACT_CH01_gc = (0x02<<0), /* First two events trigger channel 0,1 */ - ADC_EVACT_CH012_gc = (0x03<<0), /* First three events trigger channel 0,1,2 */ - ADC_EVACT_CH0123_gc = (0x04<<0), /* Events trigger channel 0,1,2,3 */ - ADC_EVACT_SWEEP_gc = (0x05<<0), /* First event triggers sweep */ - ADC_EVACT_SYNCHSWEEP_gc = (0x06<<0), /* First event triggers synchronized sweep */ -} ADC_EVACT_t; - -/* Interupt mode */ -typedef enum ADC_CH_INTMODE_enum -{ - ADC_CH_INTMODE_COMPLETE_gc = (0x00<<2), /* Interrupt on conversion complete */ - ADC_CH_INTMODE_BELOW_gc = (0x01<<2), /* Interrupt on result below compare value */ - ADC_CH_INTMODE_ABOVE_gc = (0x03<<2), /* Interrupt on result above compare value */ -} ADC_CH_INTMODE_t; - -/* Interrupt level */ -typedef enum ADC_CH_INTLVL_enum -{ - ADC_CH_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ - ADC_CH_INTLVL_LO_gc = (0x01<<0), /* Low level */ - ADC_CH_INTLVL_MED_gc = (0x02<<0), /* Medium level */ - ADC_CH_INTLVL_HI_gc = (0x03<<0), /* High level */ -} ADC_CH_INTLVL_t; - -/* DMA request selection */ -typedef enum ADC_DMASEL_enum -{ - ADC_DMASEL_OFF_gc = (0x00<<6), /* Combined DMA request OFF */ - ADC_DMASEL_CH01_gc = (0x01<<6), /* ADC Channel 0 or 1 */ - ADC_DMASEL_CH012_gc = (0x02<<6), /* ADC Channel 0 or 1 or 2 */ - ADC_DMASEL_CH0123_gc = (0x03<<6), /* ADC Channel 0 or 1 or 2 or 3 */ -} ADC_DMASEL_t; - -/* Clock prescaler */ -typedef enum ADC_PRESCALER_enum -{ - ADC_PRESCALER_DIV4_gc = (0x00<<0), /* Divide clock by 4 */ - ADC_PRESCALER_DIV8_gc = (0x01<<0), /* Divide clock by 8 */ - ADC_PRESCALER_DIV16_gc = (0x02<<0), /* Divide clock by 16 */ - ADC_PRESCALER_DIV32_gc = (0x03<<0), /* Divide clock by 32 */ - ADC_PRESCALER_DIV64_gc = (0x04<<0), /* Divide clock by 64 */ - ADC_PRESCALER_DIV128_gc = (0x05<<0), /* Divide clock by 128 */ - ADC_PRESCALER_DIV256_gc = (0x06<<0), /* Divide clock by 256 */ - ADC_PRESCALER_DIV512_gc = (0x07<<0), /* Divide clock by 512 */ -} ADC_PRESCALER_t; - - -/* --------------------------------------------------------------------------- -DAC - Digital/Analog Converter --------------------------------------------------------------------------- -*/ - -/* Digital-to-Analog Converter */ -typedef struct DAC_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t CTRLC; /* Control Register C */ - register8_t EVCTRL; /* Event Input Control */ - register8_t TIMCTRL; /* Timing Control */ - register8_t STATUS; /* Status */ - register8_t reserved_0x06; - register8_t reserved_0x07; - register8_t GAINCAL; /* Gain Calibration */ - register8_t OFFSETCAL; /* Offset Calibration */ - register8_t reserved_0x0A; - register8_t reserved_0x0B; - register8_t reserved_0x0C; - register8_t reserved_0x0D; - register8_t reserved_0x0E; - register8_t reserved_0x0F; - register8_t reserved_0x10; - register8_t reserved_0x11; - register8_t reserved_0x12; - register8_t reserved_0x13; - register8_t reserved_0x14; - register8_t reserved_0x15; - register8_t reserved_0x16; - register8_t reserved_0x17; - _WORDREGISTER(CH0DATA); /* Channel 0 Data */ - _WORDREGISTER(CH1DATA); /* Channel 1 Data */ -} DAC_t; - -/* Output channel selection */ -typedef enum DAC_CHSEL_enum -{ - DAC_CHSEL_SINGLE_gc = (0x00<<5), /* Single channel operation (Channel A only) */ - DAC_CHSEL_DUAL_gc = (0x02<<5), /* Dual channel operation (S/H on both channels) */ -} DAC_CHSEL_t; - -/* Reference voltage selection */ -typedef enum DAC_REFSEL_enum -{ - DAC_REFSEL_INT1V_gc = (0x00<<3), /* Internal 1V */ - DAC_REFSEL_AVCC_gc = (0x01<<3), /* Analog supply voltage */ - DAC_REFSEL_AREFA_gc = (0x02<<3), /* External reference on AREF on PORTA */ - DAC_REFSEL_AREFB_gc = (0x03<<3), /* External reference on AREF on PORTB */ -} DAC_REFSEL_t; - -/* Event channel selection */ -typedef enum DAC_EVSEL_enum -{ - DAC_EVSEL_0_gc = (0x00<<0), /* Event Channel 0 */ - DAC_EVSEL_1_gc = (0x01<<0), /* Event Channel 1 */ - DAC_EVSEL_2_gc = (0x02<<0), /* Event Channel 2 */ - DAC_EVSEL_3_gc = (0x03<<0), /* Event Channel 3 */ - DAC_EVSEL_4_gc = (0x04<<0), /* Event Channel 4 */ - DAC_EVSEL_5_gc = (0x05<<0), /* Event Channel 5 */ - DAC_EVSEL_6_gc = (0x06<<0), /* Event Channel 6 */ - DAC_EVSEL_7_gc = (0x07<<0), /* Event Channel 7 */ -} DAC_EVSEL_t; - -/* Conversion interval */ -typedef enum DAC_CONINTVAL_enum -{ - DAC_CONINTVAL_1CLK_gc = (0x00<<4), /* 1 CLK / 2 CLK in S/H mode */ - DAC_CONINTVAL_2CLK_gc = (0x01<<4), /* 2 CLK / 3 CLK in S/H mode */ - DAC_CONINTVAL_4CLK_gc = (0x02<<4), /* 4 CLK / 6 CLK in S/H mode */ - DAC_CONINTVAL_8CLK_gc = (0x03<<4), /* 8 CLK / 12 CLK in S/H mode */ - DAC_CONINTVAL_16CLK_gc = (0x04<<4), /* 16 CLK / 24 CLK in S/H mode */ - DAC_CONINTVAL_32CLK_gc = (0x05<<4), /* 32 CLK / 48 CLK in S/H mode */ - DAC_CONINTVAL_64CLK_gc = (0x06<<4), /* 64 CLK / 96 CLK in S/H mode */ - DAC_CONINTVAL_128CLK_gc = (0x07<<4), /* 128 CLK / 192 CLK in S/H mode */ -} DAC_CONINTVAL_t; - -/* Refresh rate */ -typedef enum DAC_REFRESH_enum -{ - DAC_REFRESH_16CLK_gc = (0x00<<0), /* 16 CLK */ - DAC_REFRESH_32CLK_gc = (0x01<<0), /* 32 CLK */ - DAC_REFRESH_64CLK_gc = (0x02<<0), /* 64 CLK */ - DAC_REFRESH_128CLK_gc = (0x03<<0), /* 128 CLK */ - DAC_REFRESH_256CLK_gc = (0x04<<0), /* 256 CLK */ - DAC_REFRESH_512CLK_gc = (0x05<<0), /* 512 CLK */ - DAC_REFRESH_1024CLK_gc = (0x06<<0), /* 1024 CLK */ - DAC_REFRESH_2048CLK_gc = (0x07<<0), /* 2048 CLK */ - DAC_REFRESH_4096CLK_gc = (0x08<<0), /* 4096 CLK */ - DAC_REFRESH_8192CLK_gc = (0x09<<0), /* 8192 CLK */ - DAC_REFRESH_16384CLK_gc = (0x0A<<0), /* 16384 CLK */ - DAC_REFRESH_32768CLK_gc = (0x0B<<0), /* 32768 CLK */ - DAC_REFRESH_65536CLK_gc = (0x0C<<0), /* 65536 CLK */ - DAC_REFRESH_OFF_gc = (0x0F<<0), /* Auto refresh OFF */ -} DAC_REFRESH_t; - - -/* --------------------------------------------------------------------------- -RTC - Real-Time Clounter --------------------------------------------------------------------------- -*/ - -/* Real-Time Counter */ -typedef struct RTC_struct -{ - register8_t CTRL; /* Control Register */ - register8_t STATUS; /* Status Register */ - register8_t INTCTRL; /* Interrupt Control Register */ - register8_t INTFLAGS; /* Interrupt Flags */ - register8_t TEMP; /* Temporary register */ - register8_t reserved_0x05; - register8_t reserved_0x06; - register8_t reserved_0x07; - _WORDREGISTER(CNT); /* Count Register */ - _WORDREGISTER(PER); /* Period Register */ - _WORDREGISTER(COMP); /* Compare Register */ -} RTC_t; - -/* Prescaler Factor */ -typedef enum RTC_PRESCALER_enum -{ - RTC_PRESCALER_OFF_gc = (0x00<<0), /* RTC Off */ - RTC_PRESCALER_DIV1_gc = (0x01<<0), /* RTC Clock */ - RTC_PRESCALER_DIV2_gc = (0x02<<0), /* RTC Clock / 2 */ - RTC_PRESCALER_DIV8_gc = (0x03<<0), /* RTC Clock / 8 */ - RTC_PRESCALER_DIV16_gc = (0x04<<0), /* RTC Clock / 16 */ - RTC_PRESCALER_DIV64_gc = (0x05<<0), /* RTC Clock / 64 */ - RTC_PRESCALER_DIV256_gc = (0x06<<0), /* RTC Clock / 256 */ - RTC_PRESCALER_DIV1024_gc = (0x07<<0), /* RTC Clock / 1024 */ -} RTC_PRESCALER_t; - -/* Compare Interrupt level */ -typedef enum RTC_COMPINTLVL_enum -{ - RTC_COMPINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ - RTC_COMPINTLVL_LO_gc = (0x01<<2), /* Low Level */ - RTC_COMPINTLVL_MED_gc = (0x02<<2), /* Medium Level */ - RTC_COMPINTLVL_HI_gc = (0x03<<2), /* High Level */ -} RTC_COMPINTLVL_t; - -/* Overflow Interrupt level */ -typedef enum RTC_OVFINTLVL_enum -{ - RTC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - RTC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ - RTC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ - RTC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ -} RTC_OVFINTLVL_t; - - -/* --------------------------------------------------------------------------- -EBI - External Bus Interface --------------------------------------------------------------------------- -*/ - -/* EBI Chip Select Module */ -typedef struct EBI_CS_struct -{ - register8_t CTRLA; /* Chip Select Control Register A */ - register8_t CTRLB; /* Chip Select Control Register B */ - _WORDREGISTER(BASEADDR); /* Chip Select Base Address */ -} EBI_CS_t; - -/* --------------------------------------------------------------------------- -EBI - External Bus Interface --------------------------------------------------------------------------- -*/ - -/* External Bus Interface */ -typedef struct EBI_struct -{ - register8_t CTRL; /* Control */ - register8_t SDRAMCTRLA; /* SDRAM Control Register A */ - register8_t reserved_0x02; - register8_t reserved_0x03; - _WORDREGISTER(REFRESH); /* SDRAM Refresh Period */ - _WORDREGISTER(INITDLY); /* SDRAM Initialization Delay */ - register8_t SDRAMCTRLB; /* SDRAM Control Register B */ - register8_t SDRAMCTRLC; /* SDRAM Control Register C */ - register8_t reserved_0x0A; - register8_t reserved_0x0B; - register8_t reserved_0x0C; - register8_t reserved_0x0D; - register8_t reserved_0x0E; - register8_t reserved_0x0F; - EBI_CS_t CS0; /* Chip Select 0 */ - EBI_CS_t CS1; /* Chip Select 1 */ - EBI_CS_t CS2; /* Chip Select 2 */ - EBI_CS_t CS3; /* Chip Select 3 */ -} EBI_t; - -/* Chip Select adress space */ -typedef enum EBI_CS_ASIZE_enum -{ - EBI_CS_ASIZE_256B_gc = (0x00<<2), /* 256 bytes */ - EBI_CS_ASIZE_512B_gc = (0x01<<2), /* 512 bytes */ - EBI_CS_ASIZE_1KB_gc = (0x02<<2), /* 1K bytes */ - EBI_CS_ASIZE_2KB_gc = (0x03<<2), /* 2K bytes */ - EBI_CS_ASIZE_4KB_gc = (0x04<<2), /* 4K bytes */ - EBI_CS_ASIZE_8KB_gc = (0x05<<2), /* 8K bytes */ - EBI_CS_ASIZE_16KB_gc = (0x06<<2), /* 16K bytes */ - EBI_CS_ASIZE_32KB_gc = (0x07<<2), /* 32K bytes */ - EBI_CS_ASIZE_64KB_gc = (0x08<<2), /* 64K bytes */ - EBI_CS_ASIZE_128KB_gc = (0x09<<2), /* 128K bytes */ - EBI_CS_ASIZE_256KB_gc = (0x0A<<2), /* 256K bytes */ - EBI_CS_ASIZE_512KB_gc = (0x0B<<2), /* 512K bytes */ - EBI_CS_ASIZE_1MB_gc = (0x0C<<2), /* 1M bytes */ - EBI_CS_ASIZE_2MB_gc = (0x0D<<2), /* 2M bytes */ - EBI_CS_ASIZE_4MB_gc = (0x0E<<2), /* 4M bytes */ - EBI_CS_ASIZE_8MB_gc = (0x0F<<2), /* 8M bytes */ - EBI_CS_ASIZE_16M_gc = (0x10<<2), /* 16M bytes */ -} EBI_CS_ASIZE_t; - -/* */ -typedef enum EBI_CS_SRWS_enum -{ - EBI_CS_SRWS_0CLK_gc = (0x00<<0), /* 0 cycles */ - EBI_CS_SRWS_1CLK_gc = (0x01<<0), /* 1 cycle */ - EBI_CS_SRWS_2CLK_gc = (0x02<<0), /* 2 cycles */ - EBI_CS_SRWS_3CLK_gc = (0x03<<0), /* 3 cycles */ - EBI_CS_SRWS_4CLK_gc = (0x04<<0), /* 4 cycles */ - EBI_CS_SRWS_5CLK_gc = (0x05<<0), /* 5 cycle */ - EBI_CS_SRWS_6CLK_gc = (0x06<<0), /* 6 cycles */ - EBI_CS_SRWS_7CLK_gc = (0x07<<0), /* 7 cycles */ -} EBI_CS_SRWS_t; - -/* Chip Select address mode */ -typedef enum EBI_CS_MODE_enum -{ - EBI_CS_MODE_DISABLED_gc = (0x00<<0), /* Chip Select Disabled */ - EBI_CS_MODE_SRAM_gc = (0x01<<0), /* Chip Select in SRAM mode */ - EBI_CS_MODE_LPC_gc = (0x02<<0), /* Chip Select in SRAM LPC mode */ - EBI_CS_MODE_SDRAM_gc = (0x03<<0), /* Chip Select in SDRAM mode */ -} EBI_CS_MODE_t; - -/* Chip Select SDRAM mode */ -typedef enum EBI_CS_SDMODE_enum -{ - EBI_CS_SDMODE_NORMAL_gc = (0x00<<0), /* Normal mode */ - EBI_CS_SDMODE_LOAD_gc = (0x01<<0), /* Load Mode Register command mode */ -} EBI_CS_SDMODE_t; - -/* */ -typedef enum EBI_SDDATAW_enum -{ - EBI_SDDATAW_4BIT_gc = (0x00<<6), /* 4-bit data bus */ - EBI_SDDATAW_8BIT_gc = (0x01<<6), /* 8-bit data bus */ -} EBI_SDDATAW_t; - -/* */ -typedef enum EBI_LPCMODE_enum -{ - EBI_LPCMODE_ALE1_gc = (0x00<<4), /* Data muxed with addr byte 0 */ - EBI_LPCMODE_ALE12_gc = (0x02<<4), /* Data muxed with addr byte 0 and 1 */ -} EBI_LPCMODE_t; - -/* */ -typedef enum EBI_SRMODE_enum -{ - EBI_SRMODE_ALE1_gc = (0x00<<2), /* Addr byte 0 muxed with 1 */ - EBI_SRMODE_ALE2_gc = (0x01<<2), /* Addr byte 0 muxed with 2 */ - EBI_SRMODE_ALE12_gc = (0x02<<2), /* Addr byte 0 muxed with 1 and 2 */ - EBI_SRMODE_NOALE_gc = (0x03<<2), /* No addr muxing */ -} EBI_SRMODE_t; - -/* */ -typedef enum EBI_IFMODE_enum -{ - EBI_IFMODE_DISABLED_gc = (0x00<<0), /* EBI Disabled */ - EBI_IFMODE_3PORT_gc = (0x01<<0), /* 3-port mode */ - EBI_IFMODE_4PORT_gc = (0x02<<0), /* 4-port mode */ - EBI_IFMODE_2PORT_gc = (0x03<<0), /* 2-port mode */ -} EBI_IFMODE_t; - -/* */ -typedef enum EBI_SDCOL_enum -{ - EBI_SDCOL_8BIT_gc = (0x00<<0), /* 8 column bits */ - EBI_SDCOL_9BIT_gc = (0x01<<0), /* 9 column bits */ - EBI_SDCOL_10BIT_gc = (0x02<<0), /* 10 column bits */ - EBI_SDCOL_11BIT_gc = (0x03<<0), /* 11 column bits */ -} EBI_SDCOL_t; - -/* */ -typedef enum EBI_MRDLY_enum -{ - EBI_MRDLY_0CLK_gc = (0x00<<6), /* 0 cycles */ - EBI_MRDLY_1CLK_gc = (0x01<<6), /* 1 cycle */ - EBI_MRDLY_2CLK_gc = (0x02<<6), /* 2 cycles */ - EBI_MRDLY_3CLK_gc = (0x03<<6), /* 3 cycles */ -} EBI_MRDLY_t; - -/* */ -typedef enum EBI_ROWCYCDLY_enum -{ - EBI_ROWCYCDLY_0CLK_gc = (0x00<<3), /* 0 cycles */ - EBI_ROWCYCDLY_1CLK_gc = (0x01<<3), /* 1 cycle */ - EBI_ROWCYCDLY_2CLK_gc = (0x02<<3), /* 2 cycles */ - EBI_ROWCYCDLY_3CLK_gc = (0x03<<3), /* 3 cycles */ - EBI_ROWCYCDLY_4CLK_gc = (0x04<<3), /* 4 cycles */ - EBI_ROWCYCDLY_5CLK_gc = (0x05<<3), /* 5 cycle */ - EBI_ROWCYCDLY_6CLK_gc = (0x06<<3), /* 6 cycles */ - EBI_ROWCYCDLY_7CLK_gc = (0x07<<3), /* 7 cycles */ -} EBI_ROWCYCDLY_t; - -/* */ -typedef enum EBI_RPDLY_enum -{ - EBI_RPDLY_0CLK_gc = (0x00<<0), /* 0 cycles */ - EBI_RPDLY_1CLK_gc = (0x01<<0), /* 1 cycle */ - EBI_RPDLY_2CLK_gc = (0x02<<0), /* 2 cycles */ - EBI_RPDLY_3CLK_gc = (0x03<<0), /* 3 cycles */ - EBI_RPDLY_4CLK_gc = (0x04<<0), /* 4 cycles */ - EBI_RPDLY_5CLK_gc = (0x05<<0), /* 5 cycle */ - EBI_RPDLY_6CLK_gc = (0x06<<0), /* 6 cycles */ - EBI_RPDLY_7CLK_gc = (0x07<<0), /* 7 cycles */ -} EBI_RPDLY_t; - -/* */ -typedef enum EBI_WRDLY_enum -{ - EBI_WRDLY_0CLK_gc = (0x00<<6), /* 0 cycles */ - EBI_WRDLY_1CLK_gc = (0x01<<6), /* 1 cycle */ - EBI_WRDLY_2CLK_gc = (0x02<<6), /* 2 cycles */ - EBI_WRDLY_3CLK_gc = (0x03<<6), /* 3 cycles */ -} EBI_WRDLY_t; - -/* */ -typedef enum EBI_ESRDLY_enum -{ - EBI_ESRDLY_0CLK_gc = (0x00<<3), /* 0 cycles */ - EBI_ESRDLY_1CLK_gc = (0x01<<3), /* 1 cycle */ - EBI_ESRDLY_2CLK_gc = (0x02<<3), /* 2 cycles */ - EBI_ESRDLY_3CLK_gc = (0x03<<3), /* 3 cycles */ - EBI_ESRDLY_4CLK_gc = (0x04<<3), /* 4 cycles */ - EBI_ESRDLY_5CLK_gc = (0x05<<3), /* 5 cycle */ - EBI_ESRDLY_6CLK_gc = (0x06<<3), /* 6 cycles */ - EBI_ESRDLY_7CLK_gc = (0x07<<3), /* 7 cycles */ -} EBI_ESRDLY_t; - -/* */ -typedef enum EBI_ROWCOLDLY_enum -{ - EBI_ROWCOLDLY_0CLK_gc = (0x00<<0), /* 0 cycles */ - EBI_ROWCOLDLY_1CLK_gc = (0x01<<0), /* 1 cycle */ - EBI_ROWCOLDLY_2CLK_gc = (0x02<<0), /* 2 cycles */ - EBI_ROWCOLDLY_3CLK_gc = (0x03<<0), /* 3 cycles */ - EBI_ROWCOLDLY_4CLK_gc = (0x04<<0), /* 4 cycles */ - EBI_ROWCOLDLY_5CLK_gc = (0x05<<0), /* 5 cycle */ - EBI_ROWCOLDLY_6CLK_gc = (0x06<<0), /* 6 cycles */ - EBI_ROWCOLDLY_7CLK_gc = (0x07<<0), /* 7 cycles */ -} EBI_ROWCOLDLY_t; - - -/* --------------------------------------------------------------------------- -TWI - Two-Wire Interface --------------------------------------------------------------------------- -*/ - -/* */ -typedef struct TWI_MASTER_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t CTRLC; /* Control Register C */ - register8_t STATUS; /* Status Register */ - register8_t BAUD; /* Baurd Rate Control Register */ - register8_t ADDR; /* Address Register */ - register8_t DATA; /* Data Register */ -} TWI_MASTER_t; - -/* --------------------------------------------------------------------------- -TWI - Two-Wire Interface --------------------------------------------------------------------------- -*/ - -/* */ -typedef struct TWI_SLAVE_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t STATUS; /* Status Register */ - register8_t ADDR; /* Address Register */ - register8_t DATA; /* Data Register */ - register8_t ADDRMASK; /* Address Mask Register */ -} TWI_SLAVE_t; - -/* --------------------------------------------------------------------------- -TWI - Two-Wire Interface --------------------------------------------------------------------------- -*/ - -/* Two-Wire Interface */ -typedef struct TWI_struct -{ - register8_t CTRL; /* TWI Common Control Register */ - TWI_MASTER_t MASTER; /* TWI master module */ - TWI_SLAVE_t SLAVE; /* TWI slave module */ -} TWI_t; - -/* Master Interrupt Level */ -typedef enum TWI_MASTER_INTLVL_enum -{ - TWI_MASTER_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ - TWI_MASTER_INTLVL_LO_gc = (0x01<<6), /* Low Level */ - TWI_MASTER_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ - TWI_MASTER_INTLVL_HI_gc = (0x03<<6), /* High Level */ -} TWI_MASTER_INTLVL_t; - -/* Inactive Timeout */ -typedef enum TWI_MASTER_TIMEOUT_enum -{ - TWI_MASTER_TIMEOUT_DISABLED_gc = (0x00<<2), /* Bus Timeout Disabled */ - TWI_MASTER_TIMEOUT_50US_gc = (0x01<<2), /* 50 Microseconds */ - TWI_MASTER_TIMEOUT_100US_gc = (0x02<<2), /* 100 Microseconds */ - TWI_MASTER_TIMEOUT_200US_gc = (0x03<<2), /* 200 Microseconds */ -} TWI_MASTER_TIMEOUT_t; - -/* Master Command */ -typedef enum TWI_MASTER_CMD_enum -{ - TWI_MASTER_CMD_NOACT_gc = (0x00<<0), /* No Action */ - TWI_MASTER_CMD_REPSTART_gc = (0x01<<0), /* Issue Repeated Start Condition */ - TWI_MASTER_CMD_RECVTRANS_gc = (0x02<<0), /* Receive or Transmit Data */ - TWI_MASTER_CMD_STOP_gc = (0x03<<0), /* Issue Stop Condition */ -} TWI_MASTER_CMD_t; - -/* Master Bus State */ -typedef enum TWI_MASTER_BUSSTATE_enum -{ - TWI_MASTER_BUSSTATE_UNKNOWN_gc = (0x00<<0), /* Unknown Bus State */ - TWI_MASTER_BUSSTATE_IDLE_gc = (0x01<<0), /* Bus is Idle */ - TWI_MASTER_BUSSTATE_OWNER_gc = (0x02<<0), /* This Module Controls The Bus */ - TWI_MASTER_BUSSTATE_BUSY_gc = (0x03<<0), /* The Bus is Busy */ -} TWI_MASTER_BUSSTATE_t; - -/* Slave Interrupt Level */ -typedef enum TWI_SLAVE_INTLVL_enum -{ - TWI_SLAVE_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ - TWI_SLAVE_INTLVL_LO_gc = (0x01<<6), /* Low Level */ - TWI_SLAVE_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ - TWI_SLAVE_INTLVL_HI_gc = (0x03<<6), /* High Level */ -} TWI_SLAVE_INTLVL_t; - -/* Slave Command */ -typedef enum TWI_SLAVE_CMD_enum -{ - TWI_SLAVE_CMD_NOACT_gc = (0x00<<0), /* No Action */ - TWI_SLAVE_CMD_COMPTRANS_gc = (0x02<<0), /* Used To Complete a Transaction */ - TWI_SLAVE_CMD_RESPONSE_gc = (0x03<<0), /* Used in Response to Address/Data Interrupt */ -} TWI_SLAVE_CMD_t; - - -/* --------------------------------------------------------------------------- -PORT - Port Configuration --------------------------------------------------------------------------- -*/ - -/* I/O port Configuration */ -typedef struct PORTCFG_struct -{ - register8_t MPCMASK; /* Multi-pin Configuration Mask */ - register8_t reserved_0x01; - register8_t VPCTRLA; /* Virtual Port Control Register A */ - register8_t VPCTRLB; /* Virtual Port Control Register B */ - register8_t CLKEVOUT; /* Clock and Event Out Register */ -} PORTCFG_t; - -/* --------------------------------------------------------------------------- -PORT - Port Configuration --------------------------------------------------------------------------- -*/ - -/* Virtual Port */ -typedef struct VPORT_struct -{ - register8_t DIR; /* I/O Port Data Direction */ - register8_t OUT; /* I/O Port Output */ - register8_t IN; /* I/O Port Input */ - register8_t INTFLAGS; /* Interrupt Flag Register */ -} VPORT_t; - -/* --------------------------------------------------------------------------- -PORT - Port Configuration --------------------------------------------------------------------------- -*/ - -/* I/O Ports */ -typedef struct PORT_struct -{ - register8_t DIR; /* I/O Port Data Direction */ - register8_t DIRSET; /* I/O Port Data Direction Set */ - register8_t DIRCLR; /* I/O Port Data Direction Clear */ - register8_t DIRTGL; /* I/O Port Data Direction Toggle */ - register8_t OUT; /* I/O Port Output */ - register8_t OUTSET; /* I/O Port Output Set */ - register8_t OUTCLR; /* I/O Port Output Clear */ - register8_t OUTTGL; /* I/O Port Output Toggle */ - register8_t IN; /* I/O port Input */ - register8_t INTCTRL; /* Interrupt Control Register */ - register8_t INT0MASK; /* Port Interrupt 0 Mask */ - register8_t INT1MASK; /* Port Interrupt 1 Mask */ - register8_t INTFLAGS; /* Interrupt Flag Register */ - register8_t reserved_0x0D; - register8_t reserved_0x0E; - register8_t reserved_0x0F; - register8_t PIN0CTRL; /* Pin 0 Control Register */ - register8_t PIN1CTRL; /* Pin 1 Control Register */ - register8_t PIN2CTRL; /* Pin 2 Control Register */ - register8_t PIN3CTRL; /* Pin 3 Control Register */ - register8_t PIN4CTRL; /* Pin 4 Control Register */ - register8_t PIN5CTRL; /* Pin 5 Control Register */ - register8_t PIN6CTRL; /* Pin 6 Control Register */ - register8_t PIN7CTRL; /* Pin 7 Control Register */ -} PORT_t; - -/* Virtual Port 0 Mapping */ -typedef enum PORTCFG_VP0MAP_enum -{ - PORTCFG_VP0MAP_PORTA_gc = (0x00<<0), /* Mapped To PORTA */ - PORTCFG_VP0MAP_PORTB_gc = (0x01<<0), /* Mapped To PORTB */ - PORTCFG_VP0MAP_PORTC_gc = (0x02<<0), /* Mapped To PORTC */ - PORTCFG_VP0MAP_PORTD_gc = (0x03<<0), /* Mapped To PORTD */ - PORTCFG_VP0MAP_PORTE_gc = (0x04<<0), /* Mapped To PORTE */ - PORTCFG_VP0MAP_PORTF_gc = (0x05<<0), /* Mapped To PORTF */ - PORTCFG_VP0MAP_PORTG_gc = (0x06<<0), /* Mapped To PORTG */ - PORTCFG_VP0MAP_PORTH_gc = (0x07<<0), /* Mapped To PORTH */ - PORTCFG_VP0MAP_PORTJ_gc = (0x08<<0), /* Mapped To PORTJ */ - PORTCFG_VP0MAP_PORTK_gc = (0x09<<0), /* Mapped To PORTK */ - PORTCFG_VP0MAP_PORTL_gc = (0x0A<<0), /* Mapped To PORTL */ - PORTCFG_VP0MAP_PORTM_gc = (0x0B<<0), /* Mapped To PORTM */ - PORTCFG_VP0MAP_PORTN_gc = (0x0C<<0), /* Mapped To PORTN */ - PORTCFG_VP0MAP_PORTP_gc = (0x0D<<0), /* Mapped To PORTP */ - PORTCFG_VP0MAP_PORTQ_gc = (0x0E<<0), /* Mapped To PORTQ */ - PORTCFG_VP0MAP_PORTR_gc = (0x0F<<0), /* Mapped To PORTR */ -} PORTCFG_VP0MAP_t; - -/* Virtual Port 1 Mapping */ -typedef enum PORTCFG_VP1MAP_enum -{ - PORTCFG_VP1MAP_PORTA_gc = (0x00<<4), /* Mapped To PORTA */ - PORTCFG_VP1MAP_PORTB_gc = (0x01<<4), /* Mapped To PORTB */ - PORTCFG_VP1MAP_PORTC_gc = (0x02<<4), /* Mapped To PORTC */ - PORTCFG_VP1MAP_PORTD_gc = (0x03<<4), /* Mapped To PORTD */ - PORTCFG_VP1MAP_PORTE_gc = (0x04<<4), /* Mapped To PORTE */ - PORTCFG_VP1MAP_PORTF_gc = (0x05<<4), /* Mapped To PORTF */ - PORTCFG_VP1MAP_PORTG_gc = (0x06<<4), /* Mapped To PORTG */ - PORTCFG_VP1MAP_PORTH_gc = (0x07<<4), /* Mapped To PORTH */ - PORTCFG_VP1MAP_PORTJ_gc = (0x08<<4), /* Mapped To PORTJ */ - PORTCFG_VP1MAP_PORTK_gc = (0x09<<4), /* Mapped To PORTK */ - PORTCFG_VP1MAP_PORTL_gc = (0x0A<<4), /* Mapped To PORTL */ - PORTCFG_VP1MAP_PORTM_gc = (0x0B<<4), /* Mapped To PORTM */ - PORTCFG_VP1MAP_PORTN_gc = (0x0C<<4), /* Mapped To PORTN */ - PORTCFG_VP1MAP_PORTP_gc = (0x0D<<4), /* Mapped To PORTP */ - PORTCFG_VP1MAP_PORTQ_gc = (0x0E<<4), /* Mapped To PORTQ */ - PORTCFG_VP1MAP_PORTR_gc = (0x0F<<4), /* Mapped To PORTR */ -} PORTCFG_VP1MAP_t; - -/* Virtual Port 2 Mapping */ -typedef enum PORTCFG_VP2MAP_enum -{ - PORTCFG_VP2MAP_PORTA_gc = (0x00<<0), /* Mapped To PORTA */ - PORTCFG_VP2MAP_PORTB_gc = (0x01<<0), /* Mapped To PORTB */ - PORTCFG_VP2MAP_PORTC_gc = (0x02<<0), /* Mapped To PORTC */ - PORTCFG_VP2MAP_PORTD_gc = (0x03<<0), /* Mapped To PORTD */ - PORTCFG_VP2MAP_PORTE_gc = (0x04<<0), /* Mapped To PORTE */ - PORTCFG_VP2MAP_PORTF_gc = (0x05<<0), /* Mapped To PORTF */ - PORTCFG_VP2MAP_PORTG_gc = (0x06<<0), /* Mapped To PORTG */ - PORTCFG_VP2MAP_PORTH_gc = (0x07<<0), /* Mapped To PORTH */ - PORTCFG_VP2MAP_PORTJ_gc = (0x08<<0), /* Mapped To PORTJ */ - PORTCFG_VP2MAP_PORTK_gc = (0x09<<0), /* Mapped To PORTK */ - PORTCFG_VP2MAP_PORTL_gc = (0x0A<<0), /* Mapped To PORTL */ - PORTCFG_VP2MAP_PORTM_gc = (0x0B<<0), /* Mapped To PORTM */ - PORTCFG_VP2MAP_PORTN_gc = (0x0C<<0), /* Mapped To PORTN */ - PORTCFG_VP2MAP_PORTP_gc = (0x0D<<0), /* Mapped To PORTP */ - PORTCFG_VP2MAP_PORTQ_gc = (0x0E<<0), /* Mapped To PORTQ */ - PORTCFG_VP2MAP_PORTR_gc = (0x0F<<0), /* Mapped To PORTR */ -} PORTCFG_VP2MAP_t; - -/* Virtual Port 3 Mapping */ -typedef enum PORTCFG_VP3MAP_enum -{ - PORTCFG_VP3MAP_PORTA_gc = (0x00<<4), /* Mapped To PORTA */ - PORTCFG_VP3MAP_PORTB_gc = (0x01<<4), /* Mapped To PORTB */ - PORTCFG_VP3MAP_PORTC_gc = (0x02<<4), /* Mapped To PORTC */ - PORTCFG_VP3MAP_PORTD_gc = (0x03<<4), /* Mapped To PORTD */ - PORTCFG_VP3MAP_PORTE_gc = (0x04<<4), /* Mapped To PORTE */ - PORTCFG_VP3MAP_PORTF_gc = (0x05<<4), /* Mapped To PORTF */ - PORTCFG_VP3MAP_PORTG_gc = (0x06<<4), /* Mapped To PORTG */ - PORTCFG_VP3MAP_PORTH_gc = (0x07<<4), /* Mapped To PORTH */ - PORTCFG_VP3MAP_PORTJ_gc = (0x08<<4), /* Mapped To PORTJ */ - PORTCFG_VP3MAP_PORTK_gc = (0x09<<4), /* Mapped To PORTK */ - PORTCFG_VP3MAP_PORTL_gc = (0x0A<<4), /* Mapped To PORTL */ - PORTCFG_VP3MAP_PORTM_gc = (0x0B<<4), /* Mapped To PORTM */ - PORTCFG_VP3MAP_PORTN_gc = (0x0C<<4), /* Mapped To PORTN */ - PORTCFG_VP3MAP_PORTP_gc = (0x0D<<4), /* Mapped To PORTP */ - PORTCFG_VP3MAP_PORTQ_gc = (0x0E<<4), /* Mapped To PORTQ */ - PORTCFG_VP3MAP_PORTR_gc = (0x0F<<4), /* Mapped To PORTR */ -} PORTCFG_VP3MAP_t; - -/* Clock Output Port */ -typedef enum PORTCFG_CLKOUT_enum -{ - PORTCFG_CLKOUT_OFF_gc = (0x00<<0), /* Clock Output Disabled */ - PORTCFG_CLKOUT_PC7_gc = (0x01<<0), /* Clock Output on Port C pin 7 */ - PORTCFG_CLKOUT_PD7_gc = (0x02<<0), /* Clock Output on Port D pin 7 */ - PORTCFG_CLKOUT_PE7_gc = (0x03<<0), /* Clock Output on Port E pin 7 */ -} PORTCFG_CLKOUT_t; - -/* Event Output Port */ -typedef enum PORTCFG_EVOUT_enum -{ - PORTCFG_EVOUT_OFF_gc = (0x00<<4), /* Event Output Disabled */ - PORTCFG_EVOUT_PC7_gc = (0x01<<4), /* Event Channel 7 Output on Port C pin 7 */ - PORTCFG_EVOUT_PD7_gc = (0x02<<4), /* Event Channel 7 Output on Port D pin 7 */ - PORTCFG_EVOUT_PE7_gc = (0x03<<4), /* Event Channel 7 Output on Port E pin 7 */ -} PORTCFG_EVOUT_t; - -/* Port Interrupt 0 Level */ -typedef enum PORT_INT0LVL_enum -{ - PORT_INT0LVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - PORT_INT0LVL_LO_gc = (0x01<<0), /* Low Level */ - PORT_INT0LVL_MED_gc = (0x02<<0), /* Medium Level */ - PORT_INT0LVL_HI_gc = (0x03<<0), /* High Level */ -} PORT_INT0LVL_t; - -/* Port Interrupt 1 Level */ -typedef enum PORT_INT1LVL_enum -{ - PORT_INT1LVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ - PORT_INT1LVL_LO_gc = (0x01<<2), /* Low Level */ - PORT_INT1LVL_MED_gc = (0x02<<2), /* Medium Level */ - PORT_INT1LVL_HI_gc = (0x03<<2), /* High Level */ -} PORT_INT1LVL_t; - -/* Output/Pull Configuration */ -typedef enum PORT_OPC_enum -{ - PORT_OPC_TOTEM_gc = (0x00<<3), /* Totempole */ - PORT_OPC_BUSKEEPER_gc = (0x01<<3), /* Totempole w/ Bus keeper on Input and Output */ - PORT_OPC_PULLDOWN_gc = (0x02<<3), /* Totempole w/ Pull-down on Input */ - PORT_OPC_PULLUP_gc = (0x03<<3), /* Totempole w/ Pull-up on Input */ - PORT_OPC_WIREDOR_gc = (0x04<<3), /* Wired OR */ - PORT_OPC_WIREDAND_gc = (0x05<<3), /* Wired AND */ - PORT_OPC_WIREDORPULL_gc = (0x06<<3), /* Wired OR w/ Pull-down */ - PORT_OPC_WIREDANDPULL_gc = (0x07<<3), /* Wired AND w/ Pull-up */ -} PORT_OPC_t; - -/* Input/Sense Configuration */ -typedef enum PORT_ISC_enum -{ - PORT_ISC_BOTHEDGES_gc = (0x00<<0), /* Sense Both Edges */ - PORT_ISC_RISING_gc = (0x01<<0), /* Sense Rising Edge */ - PORT_ISC_FALLING_gc = (0x02<<0), /* Sense Falling Edge */ - PORT_ISC_LEVEL_gc = (0x03<<0), /* Sense Level (Transparent For Events) */ - PORT_ISC_INPUT_DISABLE_gc = (0x07<<0), /* Disable Digital Input Buffer */ -} PORT_ISC_t; - - -/* --------------------------------------------------------------------------- -TC - 16-bit Timer/Counter With PWM --------------------------------------------------------------------------- -*/ - -/* 16-bit Timer/Counter 0 */ -typedef struct TC0_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t CTRLC; /* Control register C */ - register8_t CTRLD; /* Control Register D */ - register8_t CTRLE; /* Control Register E */ - register8_t reserved_0x05; - register8_t INTCTRLA; /* Interrupt Control Register A */ - register8_t INTCTRLB; /* Interrupt Control Register B */ - register8_t CTRLFCLR; /* Control Register F Clear */ - register8_t CTRLFSET; /* Control Register F Set */ - register8_t CTRLGCLR; /* Control Register G Clear */ - register8_t CTRLGSET; /* Control Register G Set */ - register8_t INTFLAGS; /* Interrupt Flag Register */ - register8_t reserved_0x0D; - register8_t reserved_0x0E; - register8_t TEMP; /* Temporary Register For 16-bit Access */ - register8_t reserved_0x10; - register8_t reserved_0x11; - register8_t reserved_0x12; - register8_t reserved_0x13; - register8_t reserved_0x14; - register8_t reserved_0x15; - register8_t reserved_0x16; - register8_t reserved_0x17; - register8_t reserved_0x18; - register8_t reserved_0x19; - register8_t reserved_0x1A; - register8_t reserved_0x1B; - register8_t reserved_0x1C; - register8_t reserved_0x1D; - register8_t reserved_0x1E; - register8_t reserved_0x1F; - _WORDREGISTER(CNT); /* Count */ - register8_t reserved_0x22; - register8_t reserved_0x23; - register8_t reserved_0x24; - register8_t reserved_0x25; - _WORDREGISTER(PER); /* Period */ - _WORDREGISTER(CCA); /* Compare or Capture A */ - _WORDREGISTER(CCB); /* Compare or Capture B */ - _WORDREGISTER(CCC); /* Compare or Capture C */ - _WORDREGISTER(CCD); /* Compare or Capture D */ - register8_t reserved_0x30; - register8_t reserved_0x31; - register8_t reserved_0x32; - register8_t reserved_0x33; - register8_t reserved_0x34; - register8_t reserved_0x35; - _WORDREGISTER(PERBUF); /* Period Buffer */ - _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ - _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ - _WORDREGISTER(CCCBUF); /* Compare Or Capture C Buffer */ - _WORDREGISTER(CCDBUF); /* Compare Or Capture D Buffer */ -} TC0_t; - -/* --------------------------------------------------------------------------- -TC - 16-bit Timer/Counter With PWM --------------------------------------------------------------------------- -*/ - -/* 16-bit Timer/Counter 1 */ -typedef struct TC1_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t CTRLC; /* Control register C */ - register8_t CTRLD; /* Control Register D */ - register8_t CTRLE; /* Control Register E */ - register8_t reserved_0x05; - register8_t INTCTRLA; /* Interrupt Control Register A */ - register8_t INTCTRLB; /* Interrupt Control Register B */ - register8_t CTRLFCLR; /* Control Register F Clear */ - register8_t CTRLFSET; /* Control Register F Set */ - register8_t CTRLGCLR; /* Control Register G Clear */ - register8_t CTRLGSET; /* Control Register G Set */ - register8_t INTFLAGS; /* Interrupt Flag Register */ - register8_t reserved_0x0D; - register8_t reserved_0x0E; - register8_t TEMP; /* Temporary Register For 16-bit Access */ - register8_t reserved_0x10; - register8_t reserved_0x11; - register8_t reserved_0x12; - register8_t reserved_0x13; - register8_t reserved_0x14; - register8_t reserved_0x15; - register8_t reserved_0x16; - register8_t reserved_0x17; - register8_t reserved_0x18; - register8_t reserved_0x19; - register8_t reserved_0x1A; - register8_t reserved_0x1B; - register8_t reserved_0x1C; - register8_t reserved_0x1D; - register8_t reserved_0x1E; - register8_t reserved_0x1F; - _WORDREGISTER(CNT); /* Count */ - register8_t reserved_0x22; - register8_t reserved_0x23; - register8_t reserved_0x24; - register8_t reserved_0x25; - _WORDREGISTER(PER); /* Period */ - _WORDREGISTER(CCA); /* Compare or Capture A */ - _WORDREGISTER(CCB); /* Compare or Capture B */ - register8_t reserved_0x2C; - register8_t reserved_0x2D; - register8_t reserved_0x2E; - register8_t reserved_0x2F; - register8_t reserved_0x30; - register8_t reserved_0x31; - register8_t reserved_0x32; - register8_t reserved_0x33; - register8_t reserved_0x34; - register8_t reserved_0x35; - _WORDREGISTER(PERBUF); /* Period Buffer */ - _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ - _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ -} TC1_t; - -/* --------------------------------------------------------------------------- -TC - 16-bit Timer/Counter With PWM --------------------------------------------------------------------------- -*/ - -/* Advanced Waveform Extension */ -typedef struct AWEX_struct -{ - register8_t CTRL; /* Control Register */ - register8_t reserved_0x01; - register8_t FDEMASK; /* Fault Detection Event Mask */ - register8_t FDCTRL; /* Fault Detection Control Register */ - register8_t STATUS; /* Status Register */ - register8_t reserved_0x05; - register8_t DTBOTH; /* Dead Time Both Sides */ - register8_t DTBOTHBUF; /* Dead Time Both Sides Buffer */ - register8_t DTLS; /* Dead Time Low Side */ - register8_t DTHS; /* Dead Time High Side */ - register8_t DTLSBUF; /* Dead Time Low Side Buffer */ - register8_t DTHSBUF; /* Dead Time High Side Buffer */ - register8_t OUTOVEN; /* Output Override Enable */ -} AWEX_t; - -/* --------------------------------------------------------------------------- -TC - 16-bit Timer/Counter With PWM --------------------------------------------------------------------------- -*/ - -/* High-Resolution Extension */ -typedef struct HIRES_struct -{ - register8_t CTRLA; /* Control Register */ -} HIRES_t; - -/* Clock Selection */ -typedef enum TC_CLKSEL_enum -{ - TC_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */ - TC_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */ - TC_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */ - TC_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */ - TC_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */ - TC_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */ - TC_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */ - TC_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */ - TC_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */ - TC_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */ - TC_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */ - TC_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */ - TC_CLKSEL_EVCH4_gc = (0x0C<<0), /* Event Channel 4 */ - TC_CLKSEL_EVCH5_gc = (0x0D<<0), /* Event Channel 5 */ - TC_CLKSEL_EVCH6_gc = (0x0E<<0), /* Event Channel 6 */ - TC_CLKSEL_EVCH7_gc = (0x0F<<0), /* Event Channel 7 */ -} TC_CLKSEL_t; - -/* Waveform Generation Mode */ -typedef enum TC_WGMODE_enum -{ - TC_WGMODE_NORMAL_gc = (0x00<<0), /* Normal Mode */ - TC_WGMODE_FRQ_gc = (0x01<<0), /* Frequency Generation Mode */ - TC_WGMODE_SS_gc = (0x03<<0), /* Single Slope */ - TC_WGMODE_DS_T_gc = (0x05<<0), /* Dual Slope, Update on TOP */ - TC_WGMODE_DS_TB_gc = (0x06<<0), /* Dual Slope, Update on TOP and BOTTOM */ - TC_WGMODE_DS_B_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */ -} TC_WGMODE_t; - -/* Event Action */ -typedef enum TC_EVACT_enum -{ - TC_EVACT_OFF_gc = (0x00<<5), /* No Event Action */ - TC_EVACT_CAPT_gc = (0x01<<5), /* Input Capture */ - TC_EVACT_UPDOWN_gc = (0x02<<5), /* Externally Controlled Up/Down Count */ - TC_EVACT_QDEC_gc = (0x03<<5), /* Quadrature Decode */ - TC_EVACT_RESTART_gc = (0x04<<5), /* Restart */ - TC_EVACT_FRQ_gc = (0x05<<5), /* Frequency Capture */ - TC_EVACT_FRW_gc = (0x05<<5), /* Frequency Capture (typo in earlier header file) */ - TC_EVACT_PW_gc = (0x06<<5), /* Pulse-width Capture */ -} TC_EVACT_t; - -/* Event Selection */ -typedef enum TC_EVSEL_enum -{ - TC_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ - TC_EVSEL_CH0_gc = (0x08<<0), /* Event Channel 0 */ - TC_EVSEL_CH1_gc = (0x09<<0), /* Event Channel 1 */ - TC_EVSEL_CH2_gc = (0x0A<<0), /* Event Channel 2 */ - TC_EVSEL_CH3_gc = (0x0B<<0), /* Event Channel 3 */ - TC_EVSEL_CH4_gc = (0x0C<<0), /* Event Channel 4 */ - TC_EVSEL_CH5_gc = (0x0D<<0), /* Event Channel 5 */ - TC_EVSEL_CH6_gc = (0x0E<<0), /* Event Channel 6 */ - TC_EVSEL_CH7_gc = (0x0F<<0), /* Event Channel 7 */ -} TC_EVSEL_t; - -/* Error Interrupt Level */ -typedef enum TC_ERRINTLVL_enum -{ - TC_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ - TC_ERRINTLVL_LO_gc = (0x01<<2), /* Low Level */ - TC_ERRINTLVL_MED_gc = (0x02<<2), /* Medium Level */ - TC_ERRINTLVL_HI_gc = (0x03<<2), /* High Level */ -} TC_ERRINTLVL_t; - -/* Overflow Interrupt Level */ -typedef enum TC_OVFINTLVL_enum -{ - TC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - TC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ - TC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ - TC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ -} TC_OVFINTLVL_t; - -/* Compare or Capture D Interrupt Level */ -typedef enum TC_CCDINTLVL_enum -{ - TC_CCDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ - TC_CCDINTLVL_LO_gc = (0x01<<6), /* Low Level */ - TC_CCDINTLVL_MED_gc = (0x02<<6), /* Medium Level */ - TC_CCDINTLVL_HI_gc = (0x03<<6), /* High Level */ -} TC_CCDINTLVL_t; - -/* Compare or Capture C Interrupt Level */ -typedef enum TC_CCCINTLVL_enum -{ - TC_CCCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ - TC_CCCINTLVL_LO_gc = (0x01<<4), /* Low Level */ - TC_CCCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ - TC_CCCINTLVL_HI_gc = (0x03<<4), /* High Level */ -} TC_CCCINTLVL_t; - -/* Compare or Capture B Interrupt Level */ -typedef enum TC_CCBINTLVL_enum -{ - TC_CCBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ - TC_CCBINTLVL_LO_gc = (0x01<<2), /* Low Level */ - TC_CCBINTLVL_MED_gc = (0x02<<2), /* Medium Level */ - TC_CCBINTLVL_HI_gc = (0x03<<2), /* High Level */ -} TC_CCBINTLVL_t; - -/* Compare or Capture A Interrupt Level */ -typedef enum TC_CCAINTLVL_enum -{ - TC_CCAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - TC_CCAINTLVL_LO_gc = (0x01<<0), /* Low Level */ - TC_CCAINTLVL_MED_gc = (0x02<<0), /* Medium Level */ - TC_CCAINTLVL_HI_gc = (0x03<<0), /* High Level */ -} TC_CCAINTLVL_t; - -/* Timer/Counter Command */ -typedef enum TC_CMD_enum -{ - TC_CMD_NONE_gc = (0x00<<2), /* No Command */ - TC_CMD_UPDATE_gc = (0x01<<2), /* Force Update */ - TC_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ - TC_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ -} TC_CMD_t; - -/* Fault Detect Action */ -typedef enum AWEX_FDACT_enum -{ - AWEX_FDACT_NONE_gc = (0x00<<0), /* No Fault Protection */ - AWEX_FDACT_CLEAROE_gc = (0x01<<0), /* Clear Output Enable Bits */ - AWEX_FDACT_CLEARDIR_gc = (0x03<<0), /* Clear I/O Port Direction Bits */ -} AWEX_FDACT_t; - -/* High Resolution Enable */ -typedef enum HIRES_HREN_enum -{ - HIRES_HREN_NONE_gc = (0x00<<0), /* No Fault Protection */ - HIRES_HREN_TC0_gc = (0x01<<0), /* Enable High Resolution on Timer/Counter 0 */ - HIRES_HREN_TC1_gc = (0x02<<0), /* Enable High Resolution on Timer/Counter 1 */ - HIRES_HREN_BOTH_gc = (0x03<<0), /* Enable High Resolution both Timer/Counters */ -} HIRES_HREN_t; - - -/* --------------------------------------------------------------------------- -USART - Universal Asynchronous Receiver-Transmitter --------------------------------------------------------------------------- -*/ - -/* Universal Synchronous/Asynchronous Receiver/Transmitter */ -typedef struct USART_struct -{ - register8_t DATA; /* Data Register */ - register8_t STATUS; /* Status Register */ - register8_t reserved_0x02; - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t CTRLC; /* Control Register C */ - register8_t BAUDCTRLA; /* Baud Rate Control Register A */ - register8_t BAUDCTRLB; /* Baud Rate Control Register B */ -} USART_t; - -/* Receive Complete Interrupt level */ -typedef enum USART_RXCINTLVL_enum -{ - USART_RXCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ - USART_RXCINTLVL_LO_gc = (0x01<<4), /* Low Level */ - USART_RXCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ - USART_RXCINTLVL_HI_gc = (0x03<<4), /* High Level */ -} USART_RXCINTLVL_t; - -/* Transmit Complete Interrupt level */ -typedef enum USART_TXCINTLVL_enum -{ - USART_TXCINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ - USART_TXCINTLVL_LO_gc = (0x01<<2), /* Low Level */ - USART_TXCINTLVL_MED_gc = (0x02<<2), /* Medium Level */ - USART_TXCINTLVL_HI_gc = (0x03<<2), /* High Level */ -} USART_TXCINTLVL_t; - -/* Data Register Empty Interrupt level */ -typedef enum USART_DREINTLVL_enum -{ - USART_DREINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - USART_DREINTLVL_LO_gc = (0x01<<0), /* Low Level */ - USART_DREINTLVL_MED_gc = (0x02<<0), /* Medium Level */ - USART_DREINTLVL_HI_gc = (0x03<<0), /* High Level */ -} USART_DREINTLVL_t; - -/* Character Size */ -typedef enum USART_CHSIZE_enum -{ - USART_CHSIZE_5BIT_gc = (0x00<<0), /* Character size: 5 bit */ - USART_CHSIZE_6BIT_gc = (0x01<<0), /* Character size: 6 bit */ - USART_CHSIZE_7BIT_gc = (0x02<<0), /* Character size: 7 bit */ - USART_CHSIZE_8BIT_gc = (0x03<<0), /* Character size: 8 bit */ - USART_CHSIZE_9BIT_gc = (0x07<<0), /* Character size: 9 bit */ -} USART_CHSIZE_t; - -/* Communication Mode */ -typedef enum USART_CMODE_enum -{ - USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6), /* Asynchronous Mode */ - USART_CMODE_SYNCHRONOUS_gc = (0x01<<6), /* Synchronous Mode */ - USART_CMODE_IRDA_gc = (0x02<<6), /* IrDA Mode */ - USART_CMODE_MSPI_gc = (0x03<<6), /* Master SPI Mode */ -} USART_CMODE_t; - -/* Parity Mode */ -typedef enum USART_PMODE_enum -{ - USART_PMODE_DISABLED_gc = (0x00<<4), /* No Parity */ - USART_PMODE_EVEN_gc = (0x02<<4), /* Even Parity */ - USART_PMODE_ODD_gc = (0x03<<4), /* Odd Parity */ -} USART_PMODE_t; - - -/* --------------------------------------------------------------------------- -SPI - Serial Peripheral Interface --------------------------------------------------------------------------- -*/ - -/* Serial Peripheral Interface */ -typedef struct SPI_struct -{ - register8_t CTRL; /* Control Register */ - register8_t INTCTRL; /* Interrupt Control Register */ - register8_t STATUS; /* Status Register */ - register8_t DATA; /* Data Register */ -} SPI_t; - -/* SPI Mode */ -typedef enum SPI_MODE_enum -{ - SPI_MODE_0_gc = (0x00<<2), /* SPI Mode 0 */ - SPI_MODE_1_gc = (0x01<<2), /* SPI Mode 1 */ - SPI_MODE_2_gc = (0x02<<2), /* SPI Mode 2 */ - SPI_MODE_3_gc = (0x03<<2), /* SPI Mode 3 */ -} SPI_MODE_t; - -/* Prescaler setting */ -typedef enum SPI_PRESCALER_enum -{ - SPI_PRESCALER_DIV4_gc = (0x00<<0), /* System Clock / 4 */ - SPI_PRESCALER_DIV16_gc = (0x01<<0), /* System Clock / 16 */ - SPI_PRESCALER_DIV64_gc = (0x02<<0), /* System Clock / 64 */ - SPI_PRESCALER_DIV128_gc = (0x03<<0), /* System Clock / 128 */ -} SPI_PRESCALER_t; - -/* Interrupt level */ -typedef enum SPI_INTLVL_enum -{ - SPI_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - SPI_INTLVL_LO_gc = (0x01<<0), /* Low Level */ - SPI_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ - SPI_INTLVL_HI_gc = (0x03<<0), /* High Level */ -} SPI_INTLVL_t; - - -/* --------------------------------------------------------------------------- -IRCOM - IR Communication Module --------------------------------------------------------------------------- -*/ - -/* IR Communication Module */ -typedef struct IRCOM_struct -{ - register8_t CTRL; /* Control Register */ - register8_t TXPLCTRL; /* IrDA Transmitter Pulse Length Control Register */ - register8_t RXPLCTRL; /* IrDA Receiver Pulse Length Control Register */ -} IRCOM_t; - -/* Event channel selection */ -typedef enum IRDA_EVSEL_enum -{ - IRDA_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ - IRDA_EVSEL_0_gc = (0x08<<0), /* Event Channel 0 */ - IRDA_EVSEL_1_gc = (0x09<<0), /* Event Channel 1 */ - IRDA_EVSEL_2_gc = (0x0A<<0), /* Event Channel 2 */ - IRDA_EVSEL_3_gc = (0x0B<<0), /* Event Channel 3 */ - IRDA_EVSEL_4_gc = (0x0C<<0), /* Event Channel 4 */ - IRDA_EVSEL_5_gc = (0x0D<<0), /* Event Channel 5 */ - IRDA_EVSEL_6_gc = (0x0E<<0), /* Event Channel 6 */ - IRDA_EVSEL_7_gc = (0x0F<<0), /* Event Channel 7 */ -} IRDA_EVSEL_t; - - -/* --------------------------------------------------------------------------- -AES - AES Module --------------------------------------------------------------------------- -*/ - -/* AES Module */ -typedef struct AES_struct -{ - register8_t CTRL; /* AES Control Register */ - register8_t STATUS; /* AES Status Register */ - register8_t STATE; /* AES State Register */ - register8_t KEY; /* AES Key Register */ - register8_t INTCTRL; /* AES Interrupt Control Register */ -} AES_t; - -/* Interrupt level */ -typedef enum AES_INTLVL_enum -{ - AES_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - AES_INTLVL_LO_gc = (0x01<<0), /* Low Level */ - AES_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ - AES_INTLVL_HI_gc = (0x03<<0), /* High Level */ -} AES_INTLVL_t; - - - -/* -========================================================================== -IO Module Instances. Mapped to memory. -========================================================================== -*/ - -#define VPORT0 (*(VPORT_t *) 0x0010) /* Virtual Port 0 */ -#define VPORT1 (*(VPORT_t *) 0x0014) /* Virtual Port 1 */ -#define VPORT2 (*(VPORT_t *) 0x0018) /* Virtual Port 2 */ -#define VPORT3 (*(VPORT_t *) 0x001C) /* Virtual Port 3 */ -#define OCD (*(OCD_t *) 0x002E) /* On-Chip Debug System */ -#define CLK (*(CLK_t *) 0x0040) /* Clock System */ -#define SLEEP (*(SLEEP_t *) 0x0048) /* Sleep Controller */ -#define OSC (*(OSC_t *) 0x0050) /* Oscillator Control */ -#define DFLLRC32M (*(DFLL_t *) 0x0060) /* DFLL for 32MHz RC Oscillator */ -#define DFLLRC2M (*(DFLL_t *) 0x0068) /* DFLL for 2MHz RC Oscillator */ -#define PR (*(PR_t *) 0x0070) /* Power Reduction */ -#define RST (*(RST_t *) 0x0078) /* Reset Controller */ -#define WDT (*(WDT_t *) 0x0080) /* Watch-Dog Timer */ -#define MCU (*(MCU_t *) 0x0090) /* MCU Control */ -#define PMIC (*(PMIC_t *) 0x00A0) /* Programmable Interrupt Controller */ -#define PORTCFG (*(PORTCFG_t *) 0x00B0) /* Port Configuration */ -#define AES (*(AES_t *) 0x00C0) /* AES Crypto Module */ -#define DMA (*(DMA_t *) 0x0100) /* DMA Controller */ -#define EVSYS (*(EVSYS_t *) 0x0180) /* Event System */ -#define NVM (*(NVM_t *) 0x01C0) /* Non Volatile Memory Controller */ -#define ADCA (*(ADC_t *) 0x0200) /* Analog to Digital Converter A */ -#define DACB (*(DAC_t *) 0x0320) /* Digital to Analog Converter B */ -#define ACA (*(AC_t *) 0x0380) /* Analog Comparator A */ -#define RTC (*(RTC_t *) 0x0400) /* Real-Time Counter */ -#define TWIC (*(TWI_t *) 0x0480) /* Two-Wire Interface C */ -#define TWIE (*(TWI_t *) 0x04A0) /* Two-Wire Interface E */ -#define PORTA (*(PORT_t *) 0x0600) /* Port A */ -#define PORTB (*(PORT_t *) 0x0620) /* Port B */ -#define PORTC (*(PORT_t *) 0x0640) /* Port C */ -#define PORTD (*(PORT_t *) 0x0660) /* Port D */ -#define PORTE (*(PORT_t *) 0x0680) /* Port E */ -#define PORTR (*(PORT_t *) 0x07E0) /* Port R */ -#define TCC0 (*(TC0_t *) 0x0800) /* Timer/Counter C0 */ -#define TCC1 (*(TC1_t *) 0x0840) /* Timer/Counter C1 */ -#define AWEXC (*(AWEX_t *) 0x0880) /* Advanced Waveform Extension C */ -#define HIRESC (*(HIRES_t *) 0x0890) /* High-Resolution Extension C */ -#define USARTC0 (*(USART_t *) 0x08A0) /* Universal Asynchronous Receiver-Transmitter C0 */ -#define USARTC1 (*(USART_t *) 0x08B0) /* Universal Asynchronous Receiver-Transmitter C1 */ -#define SPIC (*(SPI_t *) 0x08C0) /* Serial Peripheral Interface C */ -#define IRCOM (*(IRCOM_t *) 0x08F8) /* IR Communication Module */ -#define TCD0 (*(TC0_t *) 0x0900) /* Timer/Counter D0 */ -#define TCD1 (*(TC1_t *) 0x0940) /* Timer/Counter D1 */ -#define HIRESD (*(HIRES_t *) 0x0990) /* High-Resolution Extension D */ -#define USARTD0 (*(USART_t *) 0x09A0) /* Universal Asynchronous Receiver-Transmitter D0 */ -#define USARTD1 (*(USART_t *) 0x09B0) /* Universal Asynchronous Receiver-Transmitter D1 */ -#define SPID (*(SPI_t *) 0x09C0) /* Serial Peripheral Interface D */ -#define TCE0 (*(TC0_t *) 0x0A00) /* Timer/Counter E0 */ -#define HIRESE (*(HIRES_t *) 0x0A90) /* High-Resolution Extension E */ -#define USARTE0 (*(USART_t *) 0x0AA0) /* Universal Asynchronous Receiver-Transmitter E0 */ - - -#endif /* !defined (__ASSEMBLER__) */ - - -/* ========== Flattened fully qualified IO register names ========== */ - -/* GPIO - General Purpose IO Registers */ -#define GPIO_GPIOR0 _SFR_MEM8(0x0000) -#define GPIO_GPIOR1 _SFR_MEM8(0x0001) -#define GPIO_GPIOR2 _SFR_MEM8(0x0002) -#define GPIO_GPIOR3 _SFR_MEM8(0x0003) -#define GPIO_GPIOR4 _SFR_MEM8(0x0004) -#define GPIO_GPIOR5 _SFR_MEM8(0x0005) -#define GPIO_GPIOR6 _SFR_MEM8(0x0006) -#define GPIO_GPIOR7 _SFR_MEM8(0x0007) -#define GPIO_GPIOR8 _SFR_MEM8(0x0008) -#define GPIO_GPIOR9 _SFR_MEM8(0x0009) -#define GPIO_GPIORA _SFR_MEM8(0x000A) -#define GPIO_GPIORB _SFR_MEM8(0x000B) -#define GPIO_GPIORC _SFR_MEM8(0x000C) -#define GPIO_GPIORD _SFR_MEM8(0x000D) -#define GPIO_GPIORE _SFR_MEM8(0x000E) -#define GPIO_GPIORF _SFR_MEM8(0x000F) - -/* Deprecated */ -#define GPIO_GPIO0 _SFR_MEM8(0x0000) -#define GPIO_GPIO1 _SFR_MEM8(0x0001) -#define GPIO_GPIO2 _SFR_MEM8(0x0002) -#define GPIO_GPIO3 _SFR_MEM8(0x0003) -#define GPIO_GPIO4 _SFR_MEM8(0x0004) -#define GPIO_GPIO5 _SFR_MEM8(0x0005) -#define GPIO_GPIO6 _SFR_MEM8(0x0006) -#define GPIO_GPIO7 _SFR_MEM8(0x0007) -#define GPIO_GPIO8 _SFR_MEM8(0x0008) -#define GPIO_GPIO9 _SFR_MEM8(0x0009) -#define GPIO_GPIOA _SFR_MEM8(0x000A) -#define GPIO_GPIOB _SFR_MEM8(0x000B) -#define GPIO_GPIOC _SFR_MEM8(0x000C) -#define GPIO_GPIOD _SFR_MEM8(0x000D) -#define GPIO_GPIOE _SFR_MEM8(0x000E) -#define GPIO_GPIOF _SFR_MEM8(0x000F) - -/* VPORT0 - Virtual Port 0 */ -#define VPORT0_DIR _SFR_MEM8(0x0010) -#define VPORT0_OUT _SFR_MEM8(0x0011) -#define VPORT0_IN _SFR_MEM8(0x0012) -#define VPORT0_INTFLAGS _SFR_MEM8(0x0013) - -/* VPORT1 - Virtual Port 1 */ -#define VPORT1_DIR _SFR_MEM8(0x0014) -#define VPORT1_OUT _SFR_MEM8(0x0015) -#define VPORT1_IN _SFR_MEM8(0x0016) -#define VPORT1_INTFLAGS _SFR_MEM8(0x0017) - -/* VPORT2 - Virtual Port 2 */ -#define VPORT2_DIR _SFR_MEM8(0x0018) -#define VPORT2_OUT _SFR_MEM8(0x0019) -#define VPORT2_IN _SFR_MEM8(0x001A) -#define VPORT2_INTFLAGS _SFR_MEM8(0x001B) - -/* VPORT3 - Virtual Port 3 */ -#define VPORT3_DIR _SFR_MEM8(0x001C) -#define VPORT3_OUT _SFR_MEM8(0x001D) -#define VPORT3_IN _SFR_MEM8(0x001E) -#define VPORT3_INTFLAGS _SFR_MEM8(0x001F) - -/* OCD - On-Chip Debug System */ -#define OCD_OCDR0 _SFR_MEM8(0x002E) -#define OCD_OCDR1 _SFR_MEM8(0x002F) - -/* CPU - CPU Registers */ -#define CPU_CCP _SFR_MEM8(0x0034) -#define CPU_RAMPD _SFR_MEM8(0x0038) -#define CPU_RAMPX _SFR_MEM8(0x0039) -#define CPU_RAMPY _SFR_MEM8(0x003A) -#define CPU_RAMPZ _SFR_MEM8(0x003B) -#define CPU_EIND _SFR_MEM8(0x003C) -#define CPU_SPL _SFR_MEM8(0x003D) -#define CPU_SPH _SFR_MEM8(0x003E) -#define CPU_SREG _SFR_MEM8(0x003F) - -/* CLK - Clock System */ -#define CLK_CTRL _SFR_MEM8(0x0040) -#define CLK_PSCTRL _SFR_MEM8(0x0041) -#define CLK_LOCK _SFR_MEM8(0x0042) -#define CLK_RTCCTRL _SFR_MEM8(0x0043) - -/* SLEEP - Sleep Controller */ -#define SLEEP_CTRL _SFR_MEM8(0x0048) - -/* OSC - Oscillator Control */ -#define OSC_CTRL _SFR_MEM8(0x0050) -#define OSC_STATUS _SFR_MEM8(0x0051) -#define OSC_XOSCCTRL _SFR_MEM8(0x0052) -#define OSC_XOSCFAIL _SFR_MEM8(0x0053) -#define OSC_RC32KCAL _SFR_MEM8(0x0054) -#define OSC_PLLCTRL _SFR_MEM8(0x0055) -#define OSC_DFLLCTRL _SFR_MEM8(0x0056) - -/* DFLLRC32M - DFLL for 32MHz RC Oscillator */ -#define DFLLRC32M_CTRL _SFR_MEM8(0x0060) -#define DFLLRC32M_CALA _SFR_MEM8(0x0062) -#define DFLLRC32M_CALB _SFR_MEM8(0x0063) -#define DFLLRC32M_COMP0 _SFR_MEM8(0x0064) -#define DFLLRC32M_COMP1 _SFR_MEM8(0x0065) -#define DFLLRC32M_COMP2 _SFR_MEM8(0x0066) - -/* DFLLRC2M - DFLL for 2MHz RC Oscillator */ -#define DFLLRC2M_CTRL _SFR_MEM8(0x0068) -#define DFLLRC2M_CALA _SFR_MEM8(0x006A) -#define DFLLRC2M_CALB _SFR_MEM8(0x006B) -#define DFLLRC2M_COMP0 _SFR_MEM8(0x006C) -#define DFLLRC2M_COMP1 _SFR_MEM8(0x006D) -#define DFLLRC2M_COMP2 _SFR_MEM8(0x006E) - -/* PR - Power Reduction */ -#define PR_PRGEN _SFR_MEM8(0x0070) -#define PR_PRPA _SFR_MEM8(0x0071) -#define PR_PRPB _SFR_MEM8(0x0072) -#define PR_PRPC _SFR_MEM8(0x0073) -#define PR_PRPD _SFR_MEM8(0x0074) -#define PR_PRPE _SFR_MEM8(0x0075) -#define PR_PRPF _SFR_MEM8(0x0076) - -/* RST - Reset Controller */ -#define RST_STATUS _SFR_MEM8(0x0078) -#define RST_CTRL _SFR_MEM8(0x0079) - -/* WDT - Watch-Dog Timer */ -#define WDT_CTRL _SFR_MEM8(0x0080) -#define WDT_WINCTRL _SFR_MEM8(0x0081) -#define WDT_STATUS _SFR_MEM8(0x0082) - -/* MCU - MCU Control */ -#define MCU_DEVID0 _SFR_MEM8(0x0090) -#define MCU_DEVID1 _SFR_MEM8(0x0091) -#define MCU_DEVID2 _SFR_MEM8(0x0092) -#define MCU_REVID _SFR_MEM8(0x0093) -#define MCU_JTAGUID _SFR_MEM8(0x0094) -#define MCU_MCUCR _SFR_MEM8(0x0096) -#define MCU_EVSYSLOCK _SFR_MEM8(0x0098) -#define MCU_AWEXLOCK _SFR_MEM8(0x0099) - -/* PMIC - Programmable Interrupt Controller */ -#define PMIC_STATUS _SFR_MEM8(0x00A0) -#define PMIC_INTPRI _SFR_MEM8(0x00A1) -#define PMIC_CTRL _SFR_MEM8(0x00A2) - -/* PORTCFG - Port Configuration */ -#define PORTCFG_MPCMASK _SFR_MEM8(0x00B0) -#define PORTCFG_VPCTRLA _SFR_MEM8(0x00B2) -#define PORTCFG_VPCTRLB _SFR_MEM8(0x00B3) -#define PORTCFG_CLKEVOUT _SFR_MEM8(0x00B4) - -/* AES - AES Crypto Module */ -#define AES_CTRL _SFR_MEM8(0x00C0) -#define AES_STATUS _SFR_MEM8(0x00C1) -#define AES_STATE _SFR_MEM8(0x00C2) -#define AES_KEY _SFR_MEM8(0x00C3) -#define AES_INTCTRL _SFR_MEM8(0x00C4) - -/* DMA - DMA Controller */ -#define DMA_CTRL _SFR_MEM8(0x0100) -#define DMA_INTFLAGS _SFR_MEM8(0x0103) -#define DMA_STATUS _SFR_MEM8(0x0104) -#define DMA_TEMP _SFR_MEM16(0x0106) -#define DMA_CH0_CTRLA _SFR_MEM8(0x0110) -#define DMA_CH0_CTRLB _SFR_MEM8(0x0111) -#define DMA_CH0_ADDRCTRL _SFR_MEM8(0x0112) -#define DMA_CH0_TRIGSRC _SFR_MEM8(0x0113) -#define DMA_CH0_TRFCNT _SFR_MEM16(0x0114) -#define DMA_CH0_REPCNT _SFR_MEM8(0x0116) -#define DMA_CH0_SRCADDR0 _SFR_MEM8(0x0118) -#define DMA_CH0_SRCADDR1 _SFR_MEM8(0x0119) -#define DMA_CH0_SRCADDR2 _SFR_MEM8(0x011A) -#define DMA_CH0_DESTADDR0 _SFR_MEM8(0x011C) -#define DMA_CH0_DESTADDR1 _SFR_MEM8(0x011D) -#define DMA_CH0_DESTADDR2 _SFR_MEM8(0x011E) -#define DMA_CH1_CTRLA _SFR_MEM8(0x0120) -#define DMA_CH1_CTRLB _SFR_MEM8(0x0121) -#define DMA_CH1_ADDRCTRL _SFR_MEM8(0x0122) -#define DMA_CH1_TRIGSRC _SFR_MEM8(0x0123) -#define DMA_CH1_TRFCNT _SFR_MEM16(0x0124) -#define DMA_CH1_REPCNT _SFR_MEM8(0x0126) -#define DMA_CH1_SRCADDR0 _SFR_MEM8(0x0128) -#define DMA_CH1_SRCADDR1 _SFR_MEM8(0x0129) -#define DMA_CH1_SRCADDR2 _SFR_MEM8(0x012A) -#define DMA_CH1_DESTADDR0 _SFR_MEM8(0x012C) -#define DMA_CH1_DESTADDR1 _SFR_MEM8(0x012D) -#define DMA_CH1_DESTADDR2 _SFR_MEM8(0x012E) -#define DMA_CH2_CTRLA _SFR_MEM8(0x0130) -#define DMA_CH2_CTRLB _SFR_MEM8(0x0131) -#define DMA_CH2_ADDRCTRL _SFR_MEM8(0x0132) -#define DMA_CH2_TRIGSRC _SFR_MEM8(0x0133) -#define DMA_CH2_TRFCNT _SFR_MEM16(0x0134) -#define DMA_CH2_REPCNT _SFR_MEM8(0x0136) -#define DMA_CH2_SRCADDR0 _SFR_MEM8(0x0138) -#define DMA_CH2_SRCADDR1 _SFR_MEM8(0x0139) -#define DMA_CH2_SRCADDR2 _SFR_MEM8(0x013A) -#define DMA_CH2_DESTADDR0 _SFR_MEM8(0x013C) -#define DMA_CH2_DESTADDR1 _SFR_MEM8(0x013D) -#define DMA_CH2_DESTADDR2 _SFR_MEM8(0x013E) -#define DMA_CH3_CTRLA _SFR_MEM8(0x0140) -#define DMA_CH3_CTRLB _SFR_MEM8(0x0141) -#define DMA_CH3_ADDRCTRL _SFR_MEM8(0x0142) -#define DMA_CH3_TRIGSRC _SFR_MEM8(0x0143) -#define DMA_CH3_TRFCNT _SFR_MEM16(0x0144) -#define DMA_CH3_REPCNT _SFR_MEM8(0x0146) -#define DMA_CH3_SRCADDR0 _SFR_MEM8(0x0148) -#define DMA_CH3_SRCADDR1 _SFR_MEM8(0x0149) -#define DMA_CH3_SRCADDR2 _SFR_MEM8(0x014A) -#define DMA_CH3_DESTADDR0 _SFR_MEM8(0x014C) -#define DMA_CH3_DESTADDR1 _SFR_MEM8(0x014D) -#define DMA_CH3_DESTADDR2 _SFR_MEM8(0x014E) - -/* EVSYS - Event System */ -#define EVSYS_CH0MUX _SFR_MEM8(0x0180) -#define EVSYS_CH1MUX _SFR_MEM8(0x0181) -#define EVSYS_CH2MUX _SFR_MEM8(0x0182) -#define EVSYS_CH3MUX _SFR_MEM8(0x0183) -#define EVSYS_CH4MUX _SFR_MEM8(0x0184) -#define EVSYS_CH5MUX _SFR_MEM8(0x0185) -#define EVSYS_CH6MUX _SFR_MEM8(0x0186) -#define EVSYS_CH7MUX _SFR_MEM8(0x0187) -#define EVSYS_CH0CTRL _SFR_MEM8(0x0188) -#define EVSYS_CH1CTRL _SFR_MEM8(0x0189) -#define EVSYS_CH2CTRL _SFR_MEM8(0x018A) -#define EVSYS_CH3CTRL _SFR_MEM8(0x018B) -#define EVSYS_CH4CTRL _SFR_MEM8(0x018C) -#define EVSYS_CH5CTRL _SFR_MEM8(0x018D) -#define EVSYS_CH6CTRL _SFR_MEM8(0x018E) -#define EVSYS_CH7CTRL _SFR_MEM8(0x018F) -#define EVSYS_STROBE _SFR_MEM8(0x0190) -#define EVSYS_DATA _SFR_MEM8(0x0191) - -/* NVM - Non Volatile Memory Controller */ -#define NVM_ADDR0 _SFR_MEM8(0x01C0) -#define NVM_ADDR1 _SFR_MEM8(0x01C1) -#define NVM_ADDR2 _SFR_MEM8(0x01C2) -#define NVM_DATA0 _SFR_MEM8(0x01C4) -#define NVM_DATA1 _SFR_MEM8(0x01C5) -#define NVM_DATA2 _SFR_MEM8(0x01C6) -#define NVM_CMD _SFR_MEM8(0x01CA) -#define NVM_CTRLA _SFR_MEM8(0x01CB) -#define NVM_CTRLB _SFR_MEM8(0x01CC) -#define NVM_INTCTRL _SFR_MEM8(0x01CD) -#define NVM_STATUS _SFR_MEM8(0x01CF) -#define NVM_LOCKBITS _SFR_MEM8(0x01D0) - -/* ADCA - Analog to Digital Converter A */ -#define ADCA_CTRLA _SFR_MEM8(0x0200) -#define ADCA_CTRLB _SFR_MEM8(0x0201) -#define ADCA_REFCTRL _SFR_MEM8(0x0202) -#define ADCA_EVCTRL _SFR_MEM8(0x0203) -#define ADCA_PRESCALER _SFR_MEM8(0x0204) -#define ADCA_INTFLAGS _SFR_MEM8(0x0206) -#define ADCA_CAL _SFR_MEM16(0x020C) -#define ADCA_CH0RES _SFR_MEM16(0x0210) -#define ADCA_CH1RES _SFR_MEM16(0x0212) -#define ADCA_CH2RES _SFR_MEM16(0x0214) -#define ADCA_CH3RES _SFR_MEM16(0x0216) -#define ADCA_CMP _SFR_MEM16(0x0218) -#define ADCA_CH0_CTRL _SFR_MEM8(0x0220) -#define ADCA_CH0_MUXCTRL _SFR_MEM8(0x0221) -#define ADCA_CH0_INTCTRL _SFR_MEM8(0x0222) -#define ADCA_CH0_INTFLAGS _SFR_MEM8(0x0223) -#define ADCA_CH0_RES _SFR_MEM16(0x0224) -#define ADCA_CH1_CTRL _SFR_MEM8(0x0228) -#define ADCA_CH1_MUXCTRL _SFR_MEM8(0x0229) -#define ADCA_CH1_INTCTRL _SFR_MEM8(0x022A) -#define ADCA_CH1_INTFLAGS _SFR_MEM8(0x022B) -#define ADCA_CH1_RES _SFR_MEM16(0x022C) -#define ADCA_CH2_CTRL _SFR_MEM8(0x0230) -#define ADCA_CH2_MUXCTRL _SFR_MEM8(0x0231) -#define ADCA_CH2_INTCTRL _SFR_MEM8(0x0232) -#define ADCA_CH2_INTFLAGS _SFR_MEM8(0x0233) -#define ADCA_CH2_RES _SFR_MEM16(0x0234) -#define ADCA_CH3_CTRL _SFR_MEM8(0x0238) -#define ADCA_CH3_MUXCTRL _SFR_MEM8(0x0239) -#define ADCA_CH3_INTCTRL _SFR_MEM8(0x023A) -#define ADCA_CH3_INTFLAGS _SFR_MEM8(0x023B) -#define ADCA_CH3_RES _SFR_MEM16(0x023C) - -/* DACB - Digital to Analog Converter B */ -#define DACB_CTRLA _SFR_MEM8(0x0320) -#define DACB_CTRLB _SFR_MEM8(0x0321) -#define DACB_CTRLC _SFR_MEM8(0x0322) -#define DACB_EVCTRL _SFR_MEM8(0x0323) -#define DACB_TIMCTRL _SFR_MEM8(0x0324) -#define DACB_STATUS _SFR_MEM8(0x0325) -#define DACB_GAINCAL _SFR_MEM8(0x0328) -#define DACB_OFFSETCAL _SFR_MEM8(0x0329) -#define DACB_CH0DATA _SFR_MEM16(0x0338) -#define DACB_CH1DATA _SFR_MEM16(0x033A) - -/* ACA - Analog Comparator A */ -#define ACA_AC0CTRL _SFR_MEM8(0x0380) -#define ACA_AC1CTRL _SFR_MEM8(0x0381) -#define ACA_AC0MUXCTRL _SFR_MEM8(0x0382) -#define ACA_AC1MUXCTRL _SFR_MEM8(0x0383) -#define ACA_CTRLA _SFR_MEM8(0x0384) -#define ACA_CTRLB _SFR_MEM8(0x0385) -#define ACA_WINCTRL _SFR_MEM8(0x0386) -#define ACA_STATUS _SFR_MEM8(0x0387) - -/* RTC - Real-Time Counter */ -#define RTC_CTRL _SFR_MEM8(0x0400) -#define RTC_STATUS _SFR_MEM8(0x0401) -#define RTC_INTCTRL _SFR_MEM8(0x0402) -#define RTC_INTFLAGS _SFR_MEM8(0x0403) -#define RTC_TEMP _SFR_MEM8(0x0404) -#define RTC_CNT _SFR_MEM16(0x0408) -#define RTC_PER _SFR_MEM16(0x040A) -#define RTC_COMP _SFR_MEM16(0x040C) - -/* TWIC - Two-Wire Interface C */ -#define TWIC_CTRL _SFR_MEM8(0x0480) -#define TWIC_MASTER_CTRLA _SFR_MEM8(0x0481) -#define TWIC_MASTER_CTRLB _SFR_MEM8(0x0482) -#define TWIC_MASTER_CTRLC _SFR_MEM8(0x0483) -#define TWIC_MASTER_STATUS _SFR_MEM8(0x0484) -#define TWIC_MASTER_BAUD _SFR_MEM8(0x0485) -#define TWIC_MASTER_ADDR _SFR_MEM8(0x0486) -#define TWIC_MASTER_DATA _SFR_MEM8(0x0487) -#define TWIC_SLAVE_CTRLA _SFR_MEM8(0x0488) -#define TWIC_SLAVE_CTRLB _SFR_MEM8(0x0489) -#define TWIC_SLAVE_STATUS _SFR_MEM8(0x048A) -#define TWIC_SLAVE_ADDR _SFR_MEM8(0x048B) -#define TWIC_SLAVE_DATA _SFR_MEM8(0x048C) -#define TWIC_SLAVE_ADDRMASK _SFR_MEM8(0x048D) - -/* TWIE - Two-Wire Interface E */ -#define TWIE_CTRL _SFR_MEM8(0x04A0) -#define TWIE_MASTER_CTRLA _SFR_MEM8(0x04A1) -#define TWIE_MASTER_CTRLB _SFR_MEM8(0x04A2) -#define TWIE_MASTER_CTRLC _SFR_MEM8(0x04A3) -#define TWIE_MASTER_STATUS _SFR_MEM8(0x04A4) -#define TWIE_MASTER_BAUD _SFR_MEM8(0x04A5) -#define TWIE_MASTER_ADDR _SFR_MEM8(0x04A6) -#define TWIE_MASTER_DATA _SFR_MEM8(0x04A7) -#define TWIE_SLAVE_CTRLA _SFR_MEM8(0x04A8) -#define TWIE_SLAVE_CTRLB _SFR_MEM8(0x04A9) -#define TWIE_SLAVE_STATUS _SFR_MEM8(0x04AA) -#define TWIE_SLAVE_ADDR _SFR_MEM8(0x04AB) -#define TWIE_SLAVE_DATA _SFR_MEM8(0x04AC) -#define TWIE_SLAVE_ADDRMASK _SFR_MEM8(0x04AD) - -/* PORTA - Port A */ -#define PORTA_DIR _SFR_MEM8(0x0600) -#define PORTA_DIRSET _SFR_MEM8(0x0601) -#define PORTA_DIRCLR _SFR_MEM8(0x0602) -#define PORTA_DIRTGL _SFR_MEM8(0x0603) -#define PORTA_OUT _SFR_MEM8(0x0604) -#define PORTA_OUTSET _SFR_MEM8(0x0605) -#define PORTA_OUTCLR _SFR_MEM8(0x0606) -#define PORTA_OUTTGL _SFR_MEM8(0x0607) -#define PORTA_IN _SFR_MEM8(0x0608) -#define PORTA_INTCTRL _SFR_MEM8(0x0609) -#define PORTA_INT0MASK _SFR_MEM8(0x060A) -#define PORTA_INT1MASK _SFR_MEM8(0x060B) -#define PORTA_INTFLAGS _SFR_MEM8(0x060C) -#define PORTA_PIN0CTRL _SFR_MEM8(0x0610) -#define PORTA_PIN1CTRL _SFR_MEM8(0x0611) -#define PORTA_PIN2CTRL _SFR_MEM8(0x0612) -#define PORTA_PIN3CTRL _SFR_MEM8(0x0613) -#define PORTA_PIN4CTRL _SFR_MEM8(0x0614) -#define PORTA_PIN5CTRL _SFR_MEM8(0x0615) -#define PORTA_PIN6CTRL _SFR_MEM8(0x0616) -#define PORTA_PIN7CTRL _SFR_MEM8(0x0617) - -/* PORTB - Port B */ -#define PORTB_DIR _SFR_MEM8(0x0620) -#define PORTB_DIRSET _SFR_MEM8(0x0621) -#define PORTB_DIRCLR _SFR_MEM8(0x0622) -#define PORTB_DIRTGL _SFR_MEM8(0x0623) -#define PORTB_OUT _SFR_MEM8(0x0624) -#define PORTB_OUTSET _SFR_MEM8(0x0625) -#define PORTB_OUTCLR _SFR_MEM8(0x0626) -#define PORTB_OUTTGL _SFR_MEM8(0x0627) -#define PORTB_IN _SFR_MEM8(0x0628) -#define PORTB_INTCTRL _SFR_MEM8(0x0629) -#define PORTB_INT0MASK _SFR_MEM8(0x062A) -#define PORTB_INT1MASK _SFR_MEM8(0x062B) -#define PORTB_INTFLAGS _SFR_MEM8(0x062C) -#define PORTB_PIN0CTRL _SFR_MEM8(0x0630) -#define PORTB_PIN1CTRL _SFR_MEM8(0x0631) -#define PORTB_PIN2CTRL _SFR_MEM8(0x0632) -#define PORTB_PIN3CTRL _SFR_MEM8(0x0633) -#define PORTB_PIN4CTRL _SFR_MEM8(0x0634) -#define PORTB_PIN5CTRL _SFR_MEM8(0x0635) -#define PORTB_PIN6CTRL _SFR_MEM8(0x0636) -#define PORTB_PIN7CTRL _SFR_MEM8(0x0637) - -/* PORTC - Port C */ -#define PORTC_DIR _SFR_MEM8(0x0640) -#define PORTC_DIRSET _SFR_MEM8(0x0641) -#define PORTC_DIRCLR _SFR_MEM8(0x0642) -#define PORTC_DIRTGL _SFR_MEM8(0x0643) -#define PORTC_OUT _SFR_MEM8(0x0644) -#define PORTC_OUTSET _SFR_MEM8(0x0645) -#define PORTC_OUTCLR _SFR_MEM8(0x0646) -#define PORTC_OUTTGL _SFR_MEM8(0x0647) -#define PORTC_IN _SFR_MEM8(0x0648) -#define PORTC_INTCTRL _SFR_MEM8(0x0649) -#define PORTC_INT0MASK _SFR_MEM8(0x064A) -#define PORTC_INT1MASK _SFR_MEM8(0x064B) -#define PORTC_INTFLAGS _SFR_MEM8(0x064C) -#define PORTC_PIN0CTRL _SFR_MEM8(0x0650) -#define PORTC_PIN1CTRL _SFR_MEM8(0x0651) -#define PORTC_PIN2CTRL _SFR_MEM8(0x0652) -#define PORTC_PIN3CTRL _SFR_MEM8(0x0653) -#define PORTC_PIN4CTRL _SFR_MEM8(0x0654) -#define PORTC_PIN5CTRL _SFR_MEM8(0x0655) -#define PORTC_PIN6CTRL _SFR_MEM8(0x0656) -#define PORTC_PIN7CTRL _SFR_MEM8(0x0657) - -/* PORTD - Port D */ -#define PORTD_DIR _SFR_MEM8(0x0660) -#define PORTD_DIRSET _SFR_MEM8(0x0661) -#define PORTD_DIRCLR _SFR_MEM8(0x0662) -#define PORTD_DIRTGL _SFR_MEM8(0x0663) -#define PORTD_OUT _SFR_MEM8(0x0664) -#define PORTD_OUTSET _SFR_MEM8(0x0665) -#define PORTD_OUTCLR _SFR_MEM8(0x0666) -#define PORTD_OUTTGL _SFR_MEM8(0x0667) -#define PORTD_IN _SFR_MEM8(0x0668) -#define PORTD_INTCTRL _SFR_MEM8(0x0669) -#define PORTD_INT0MASK _SFR_MEM8(0x066A) -#define PORTD_INT1MASK _SFR_MEM8(0x066B) -#define PORTD_INTFLAGS _SFR_MEM8(0x066C) -#define PORTD_PIN0CTRL _SFR_MEM8(0x0670) -#define PORTD_PIN1CTRL _SFR_MEM8(0x0671) -#define PORTD_PIN2CTRL _SFR_MEM8(0x0672) -#define PORTD_PIN3CTRL _SFR_MEM8(0x0673) -#define PORTD_PIN4CTRL _SFR_MEM8(0x0674) -#define PORTD_PIN5CTRL _SFR_MEM8(0x0675) -#define PORTD_PIN6CTRL _SFR_MEM8(0x0676) -#define PORTD_PIN7CTRL _SFR_MEM8(0x0677) - -/* PORTE - Port E */ -#define PORTE_DIR _SFR_MEM8(0x0680) -#define PORTE_DIRSET _SFR_MEM8(0x0681) -#define PORTE_DIRCLR _SFR_MEM8(0x0682) -#define PORTE_DIRTGL _SFR_MEM8(0x0683) -#define PORTE_OUT _SFR_MEM8(0x0684) -#define PORTE_OUTSET _SFR_MEM8(0x0685) -#define PORTE_OUTCLR _SFR_MEM8(0x0686) -#define PORTE_OUTTGL _SFR_MEM8(0x0687) -#define PORTE_IN _SFR_MEM8(0x0688) -#define PORTE_INTCTRL _SFR_MEM8(0x0689) -#define PORTE_INT0MASK _SFR_MEM8(0x068A) -#define PORTE_INT1MASK _SFR_MEM8(0x068B) -#define PORTE_INTFLAGS _SFR_MEM8(0x068C) -#define PORTE_PIN0CTRL _SFR_MEM8(0x0690) -#define PORTE_PIN1CTRL _SFR_MEM8(0x0691) -#define PORTE_PIN2CTRL _SFR_MEM8(0x0692) -#define PORTE_PIN3CTRL _SFR_MEM8(0x0693) -#define PORTE_PIN4CTRL _SFR_MEM8(0x0694) -#define PORTE_PIN5CTRL _SFR_MEM8(0x0695) -#define PORTE_PIN6CTRL _SFR_MEM8(0x0696) -#define PORTE_PIN7CTRL _SFR_MEM8(0x0697) - -/* PORTR - Port R */ -#define PORTR_DIR _SFR_MEM8(0x07E0) -#define PORTR_DIRSET _SFR_MEM8(0x07E1) -#define PORTR_DIRCLR _SFR_MEM8(0x07E2) -#define PORTR_DIRTGL _SFR_MEM8(0x07E3) -#define PORTR_OUT _SFR_MEM8(0x07E4) -#define PORTR_OUTSET _SFR_MEM8(0x07E5) -#define PORTR_OUTCLR _SFR_MEM8(0x07E6) -#define PORTR_OUTTGL _SFR_MEM8(0x07E7) -#define PORTR_IN _SFR_MEM8(0x07E8) -#define PORTR_INTCTRL _SFR_MEM8(0x07E9) -#define PORTR_INT0MASK _SFR_MEM8(0x07EA) -#define PORTR_INT1MASK _SFR_MEM8(0x07EB) -#define PORTR_INTFLAGS _SFR_MEM8(0x07EC) -#define PORTR_PIN0CTRL _SFR_MEM8(0x07F0) -#define PORTR_PIN1CTRL _SFR_MEM8(0x07F1) -#define PORTR_PIN2CTRL _SFR_MEM8(0x07F2) -#define PORTR_PIN3CTRL _SFR_MEM8(0x07F3) -#define PORTR_PIN4CTRL _SFR_MEM8(0x07F4) -#define PORTR_PIN5CTRL _SFR_MEM8(0x07F5) -#define PORTR_PIN6CTRL _SFR_MEM8(0x07F6) -#define PORTR_PIN7CTRL _SFR_MEM8(0x07F7) - -/* TCC0 - Timer/Counter C0 */ -#define TCC0_CTRLA _SFR_MEM8(0x0800) -#define TCC0_CTRLB _SFR_MEM8(0x0801) -#define TCC0_CTRLC _SFR_MEM8(0x0802) -#define TCC0_CTRLD _SFR_MEM8(0x0803) -#define TCC0_CTRLE _SFR_MEM8(0x0804) -#define TCC0_INTCTRLA _SFR_MEM8(0x0806) -#define TCC0_INTCTRLB _SFR_MEM8(0x0807) -#define TCC0_CTRLFCLR _SFR_MEM8(0x0808) -#define TCC0_CTRLFSET _SFR_MEM8(0x0809) -#define TCC0_CTRLGCLR _SFR_MEM8(0x080A) -#define TCC0_CTRLGSET _SFR_MEM8(0x080B) -#define TCC0_INTFLAGS _SFR_MEM8(0x080C) -#define TCC0_TEMP _SFR_MEM8(0x080F) -#define TCC0_CNT _SFR_MEM16(0x0820) -#define TCC0_PER _SFR_MEM16(0x0826) -#define TCC0_CCA _SFR_MEM16(0x0828) -#define TCC0_CCB _SFR_MEM16(0x082A) -#define TCC0_CCC _SFR_MEM16(0x082C) -#define TCC0_CCD _SFR_MEM16(0x082E) -#define TCC0_PERBUF _SFR_MEM16(0x0836) -#define TCC0_CCABUF _SFR_MEM16(0x0838) -#define TCC0_CCBBUF _SFR_MEM16(0x083A) -#define TCC0_CCCBUF _SFR_MEM16(0x083C) -#define TCC0_CCDBUF _SFR_MEM16(0x083E) - -/* TCC1 - Timer/Counter C1 */ -#define TCC1_CTRLA _SFR_MEM8(0x0840) -#define TCC1_CTRLB _SFR_MEM8(0x0841) -#define TCC1_CTRLC _SFR_MEM8(0x0842) -#define TCC1_CTRLD _SFR_MEM8(0x0843) -#define TCC1_CTRLE _SFR_MEM8(0x0844) -#define TCC1_INTCTRLA _SFR_MEM8(0x0846) -#define TCC1_INTCTRLB _SFR_MEM8(0x0847) -#define TCC1_CTRLFCLR _SFR_MEM8(0x0848) -#define TCC1_CTRLFSET _SFR_MEM8(0x0849) -#define TCC1_CTRLGCLR _SFR_MEM8(0x084A) -#define TCC1_CTRLGSET _SFR_MEM8(0x084B) -#define TCC1_INTFLAGS _SFR_MEM8(0x084C) -#define TCC1_TEMP _SFR_MEM8(0x084F) -#define TCC1_CNT _SFR_MEM16(0x0860) -#define TCC1_PER _SFR_MEM16(0x0866) -#define TCC1_CCA _SFR_MEM16(0x0868) -#define TCC1_CCB _SFR_MEM16(0x086A) -#define TCC1_PERBUF _SFR_MEM16(0x0876) -#define TCC1_CCABUF _SFR_MEM16(0x0878) -#define TCC1_CCBBUF _SFR_MEM16(0x087A) - -/* AWEXC - Advanced Waveform Extension C */ -#define AWEXC_CTRL _SFR_MEM8(0x0880) -#define AWEXC_FDEMASK _SFR_MEM8(0x0882) -#define AWEXC_FDCTRL _SFR_MEM8(0x0883) -#define AWEXC_STATUS _SFR_MEM8(0x0884) -#define AWEXC_DTBOTH _SFR_MEM8(0x0886) -#define AWEXC_DTBOTHBUF _SFR_MEM8(0x0887) -#define AWEXC_DTLS _SFR_MEM8(0x0888) -#define AWEXC_DTHS _SFR_MEM8(0x0889) -#define AWEXC_DTLSBUF _SFR_MEM8(0x088A) -#define AWEXC_DTHSBUF _SFR_MEM8(0x088B) -#define AWEXC_OUTOVEN _SFR_MEM8(0x088C) - -/* HIRESC - High-Resolution Extension C */ -#define HIRESC_CTRLA _SFR_MEM8(0x0890) - -/* USARTC0 - Universal Asynchronous Receiver-Transmitter C0 */ -#define USARTC0_DATA _SFR_MEM8(0x08A0) -#define USARTC0_STATUS _SFR_MEM8(0x08A1) -#define USARTC0_CTRLA _SFR_MEM8(0x08A3) -#define USARTC0_CTRLB _SFR_MEM8(0x08A4) -#define USARTC0_CTRLC _SFR_MEM8(0x08A5) -#define USARTC0_BAUDCTRLA _SFR_MEM8(0x08A6) -#define USARTC0_BAUDCTRLB _SFR_MEM8(0x08A7) - -/* USARTC1 - Universal Asynchronous Receiver-Transmitter C1 */ -#define USARTC1_DATA _SFR_MEM8(0x08B0) -#define USARTC1_STATUS _SFR_MEM8(0x08B1) -#define USARTC1_CTRLA _SFR_MEM8(0x08B3) -#define USARTC1_CTRLB _SFR_MEM8(0x08B4) -#define USARTC1_CTRLC _SFR_MEM8(0x08B5) -#define USARTC1_BAUDCTRLA _SFR_MEM8(0x08B6) -#define USARTC1_BAUDCTRLB _SFR_MEM8(0x08B7) - -/* SPIC - Serial Peripheral Interface C */ -#define SPIC_CTRL _SFR_MEM8(0x08C0) -#define SPIC_INTCTRL _SFR_MEM8(0x08C1) -#define SPIC_STATUS _SFR_MEM8(0x08C2) -#define SPIC_DATA _SFR_MEM8(0x08C3) - -/* IRCOM - IR Communication Module */ -#define IRCOM_CTRL _SFR_MEM8(0x08F8) -#define IRCOM_TXPLCTRL _SFR_MEM8(0x08F9) -#define IRCOM_RXPLCTRL _SFR_MEM8(0x08FA) - -/* TCD0 - Timer/Counter D0 */ -#define TCD0_CTRLA _SFR_MEM8(0x0900) -#define TCD0_CTRLB _SFR_MEM8(0x0901) -#define TCD0_CTRLC _SFR_MEM8(0x0902) -#define TCD0_CTRLD _SFR_MEM8(0x0903) -#define TCD0_CTRLE _SFR_MEM8(0x0904) -#define TCD0_INTCTRLA _SFR_MEM8(0x0906) -#define TCD0_INTCTRLB _SFR_MEM8(0x0907) -#define TCD0_CTRLFCLR _SFR_MEM8(0x0908) -#define TCD0_CTRLFSET _SFR_MEM8(0x0909) -#define TCD0_CTRLGCLR _SFR_MEM8(0x090A) -#define TCD0_CTRLGSET _SFR_MEM8(0x090B) -#define TCD0_INTFLAGS _SFR_MEM8(0x090C) -#define TCD0_TEMP _SFR_MEM8(0x090F) -#define TCD0_CNT _SFR_MEM16(0x0920) -#define TCD0_PER _SFR_MEM16(0x0926) -#define TCD0_CCA _SFR_MEM16(0x0928) -#define TCD0_CCB _SFR_MEM16(0x092A) -#define TCD0_CCC _SFR_MEM16(0x092C) -#define TCD0_CCD _SFR_MEM16(0x092E) -#define TCD0_PERBUF _SFR_MEM16(0x0936) -#define TCD0_CCABUF _SFR_MEM16(0x0938) -#define TCD0_CCBBUF _SFR_MEM16(0x093A) -#define TCD0_CCCBUF _SFR_MEM16(0x093C) -#define TCD0_CCDBUF _SFR_MEM16(0x093E) - -/* TCD1 - Timer/Counter D1 */ -#define TCD1_CTRLA _SFR_MEM8(0x0940) -#define TCD1_CTRLB _SFR_MEM8(0x0941) -#define TCD1_CTRLC _SFR_MEM8(0x0942) -#define TCD1_CTRLD _SFR_MEM8(0x0943) -#define TCD1_CTRLE _SFR_MEM8(0x0944) -#define TCD1_INTCTRLA _SFR_MEM8(0x0946) -#define TCD1_INTCTRLB _SFR_MEM8(0x0947) -#define TCD1_CTRLFCLR _SFR_MEM8(0x0948) -#define TCD1_CTRLFSET _SFR_MEM8(0x0949) -#define TCD1_CTRLGCLR _SFR_MEM8(0x094A) -#define TCD1_CTRLGSET _SFR_MEM8(0x094B) -#define TCD1_INTFLAGS _SFR_MEM8(0x094C) -#define TCD1_TEMP _SFR_MEM8(0x094F) -#define TCD1_CNT _SFR_MEM16(0x0960) -#define TCD1_PER _SFR_MEM16(0x0966) -#define TCD1_CCA _SFR_MEM16(0x0968) -#define TCD1_CCB _SFR_MEM16(0x096A) -#define TCD1_PERBUF _SFR_MEM16(0x0976) -#define TCD1_CCABUF _SFR_MEM16(0x0978) -#define TCD1_CCBBUF _SFR_MEM16(0x097A) - -/* HIRESD - High-Resolution Extension D */ -#define HIRESD_CTRLA _SFR_MEM8(0x0990) - -/* USARTD0 - Universal Asynchronous Receiver-Transmitter D0 */ -#define USARTD0_DATA _SFR_MEM8(0x09A0) -#define USARTD0_STATUS _SFR_MEM8(0x09A1) -#define USARTD0_CTRLA _SFR_MEM8(0x09A3) -#define USARTD0_CTRLB _SFR_MEM8(0x09A4) -#define USARTD0_CTRLC _SFR_MEM8(0x09A5) -#define USARTD0_BAUDCTRLA _SFR_MEM8(0x09A6) -#define USARTD0_BAUDCTRLB _SFR_MEM8(0x09A7) - -/* USARTD1 - Universal Asynchronous Receiver-Transmitter D1 */ -#define USARTD1_DATA _SFR_MEM8(0x09B0) -#define USARTD1_STATUS _SFR_MEM8(0x09B1) -#define USARTD1_CTRLA _SFR_MEM8(0x09B3) -#define USARTD1_CTRLB _SFR_MEM8(0x09B4) -#define USARTD1_CTRLC _SFR_MEM8(0x09B5) -#define USARTD1_BAUDCTRLA _SFR_MEM8(0x09B6) -#define USARTD1_BAUDCTRLB _SFR_MEM8(0x09B7) - -/* SPID - Serial Peripheral Interface D */ -#define SPID_CTRL _SFR_MEM8(0x09C0) -#define SPID_INTCTRL _SFR_MEM8(0x09C1) -#define SPID_STATUS _SFR_MEM8(0x09C2) -#define SPID_DATA _SFR_MEM8(0x09C3) - -/* TCE0 - Timer/Counter E0 */ -#define TCE0_CTRLA _SFR_MEM8(0x0A00) -#define TCE0_CTRLB _SFR_MEM8(0x0A01) -#define TCE0_CTRLC _SFR_MEM8(0x0A02) -#define TCE0_CTRLD _SFR_MEM8(0x0A03) -#define TCE0_CTRLE _SFR_MEM8(0x0A04) -#define TCE0_INTCTRLA _SFR_MEM8(0x0A06) -#define TCE0_INTCTRLB _SFR_MEM8(0x0A07) -#define TCE0_CTRLFCLR _SFR_MEM8(0x0A08) -#define TCE0_CTRLFSET _SFR_MEM8(0x0A09) -#define TCE0_CTRLGCLR _SFR_MEM8(0x0A0A) -#define TCE0_CTRLGSET _SFR_MEM8(0x0A0B) -#define TCE0_INTFLAGS _SFR_MEM8(0x0A0C) -#define TCE0_TEMP _SFR_MEM8(0x0A0F) -#define TCE0_CNT _SFR_MEM16(0x0A20) -#define TCE0_PER _SFR_MEM16(0x0A26) -#define TCE0_CCA _SFR_MEM16(0x0A28) -#define TCE0_CCB _SFR_MEM16(0x0A2A) -#define TCE0_CCC _SFR_MEM16(0x0A2C) -#define TCE0_CCD _SFR_MEM16(0x0A2E) -#define TCE0_PERBUF _SFR_MEM16(0x0A36) -#define TCE0_CCABUF _SFR_MEM16(0x0A38) -#define TCE0_CCBBUF _SFR_MEM16(0x0A3A) -#define TCE0_CCCBUF _SFR_MEM16(0x0A3C) -#define TCE0_CCDBUF _SFR_MEM16(0x0A3E) - -/* HIRESE - High-Resolution Extension E */ -#define HIRESE_CTRLA _SFR_MEM8(0x0A90) - -/* USARTE0 - Universal Asynchronous Receiver-Transmitter E0 */ -#define USARTE0_DATA _SFR_MEM8(0x0AA0) -#define USARTE0_STATUS _SFR_MEM8(0x0AA1) -#define USARTE0_CTRLA _SFR_MEM8(0x0AA3) -#define USARTE0_CTRLB _SFR_MEM8(0x0AA4) -#define USARTE0_CTRLC _SFR_MEM8(0x0AA5) -#define USARTE0_BAUDCTRLA _SFR_MEM8(0x0AA6) -#define USARTE0_BAUDCTRLB _SFR_MEM8(0x0AA7) - - - -/*================== Bitfield Definitions ================== */ - -/* XOCD - On-Chip Debug System */ -/* OCD.OCDR1 bit masks and bit positions */ -#define OCD_OCDRD_bm 0x01 /* OCDR Dirty bit mask. */ -#define OCD_OCDRD_bp 0 /* OCDR Dirty bit position. */ - - -/* CPU - CPU */ -/* CPU.CCP bit masks and bit positions */ -#define CPU_CCP_gm 0xFF /* CCP signature group mask. */ -#define CPU_CCP_gp 0 /* CCP signature group position. */ -#define CPU_CCP0_bm (1<<0) /* CCP signature bit 0 mask. */ -#define CPU_CCP0_bp 0 /* CCP signature bit 0 position. */ -#define CPU_CCP1_bm (1<<1) /* CCP signature bit 1 mask. */ -#define CPU_CCP1_bp 1 /* CCP signature bit 1 position. */ -#define CPU_CCP2_bm (1<<2) /* CCP signature bit 2 mask. */ -#define CPU_CCP2_bp 2 /* CCP signature bit 2 position. */ -#define CPU_CCP3_bm (1<<3) /* CCP signature bit 3 mask. */ -#define CPU_CCP3_bp 3 /* CCP signature bit 3 position. */ -#define CPU_CCP4_bm (1<<4) /* CCP signature bit 4 mask. */ -#define CPU_CCP4_bp 4 /* CCP signature bit 4 position. */ -#define CPU_CCP5_bm (1<<5) /* CCP signature bit 5 mask. */ -#define CPU_CCP5_bp 5 /* CCP signature bit 5 position. */ -#define CPU_CCP6_bm (1<<6) /* CCP signature bit 6 mask. */ -#define CPU_CCP6_bp 6 /* CCP signature bit 6 position. */ -#define CPU_CCP7_bm (1<<7) /* CCP signature bit 7 mask. */ -#define CPU_CCP7_bp 7 /* CCP signature bit 7 position. */ - - -/* CPU.SREG bit masks and bit positions */ -#define CPU_I_bm 0x80 /* Global Interrupt Enable Flag bit mask. */ -#define CPU_I_bp 7 /* Global Interrupt Enable Flag bit position. */ - -#define CPU_T_bm 0x40 /* Transfer Bit bit mask. */ -#define CPU_T_bp 6 /* Transfer Bit bit position. */ - -#define CPU_H_bm 0x20 /* Half Carry Flag bit mask. */ -#define CPU_H_bp 5 /* Half Carry Flag bit position. */ - -#define CPU_S_bm 0x10 /* N Exclusive Or V Flag bit mask. */ -#define CPU_S_bp 4 /* N Exclusive Or V Flag bit position. */ - -#define CPU_V_bm 0x08 /* Two's Complement Overflow Flag bit mask. */ -#define CPU_V_bp 3 /* Two's Complement Overflow Flag bit position. */ - -#define CPU_N_bm 0x04 /* Negative Flag bit mask. */ -#define CPU_N_bp 2 /* Negative Flag bit position. */ - -#define CPU_Z_bm 0x02 /* Zero Flag bit mask. */ -#define CPU_Z_bp 1 /* Zero Flag bit position. */ - -#define CPU_C_bm 0x01 /* Carry Flag bit mask. */ -#define CPU_C_bp 0 /* Carry Flag bit position. */ - - -/* CLK - Clock System */ -/* CLK.CTRL bit masks and bit positions */ -#define CLK_SCLKSEL_gm 0x07 /* System Clock Selection group mask. */ -#define CLK_SCLKSEL_gp 0 /* System Clock Selection group position. */ -#define CLK_SCLKSEL0_bm (1<<0) /* System Clock Selection bit 0 mask. */ -#define CLK_SCLKSEL0_bp 0 /* System Clock Selection bit 0 position. */ -#define CLK_SCLKSEL1_bm (1<<1) /* System Clock Selection bit 1 mask. */ -#define CLK_SCLKSEL1_bp 1 /* System Clock Selection bit 1 position. */ -#define CLK_SCLKSEL2_bm (1<<2) /* System Clock Selection bit 2 mask. */ -#define CLK_SCLKSEL2_bp 2 /* System Clock Selection bit 2 position. */ - - -/* CLK.PSCTRL bit masks and bit positions */ -#define CLK_PSADIV_gm 0x7C /* Prescaler A Division Factor group mask. */ -#define CLK_PSADIV_gp 2 /* Prescaler A Division Factor group position. */ -#define CLK_PSADIV0_bm (1<<2) /* Prescaler A Division Factor bit 0 mask. */ -#define CLK_PSADIV0_bp 2 /* Prescaler A Division Factor bit 0 position. */ -#define CLK_PSADIV1_bm (1<<3) /* Prescaler A Division Factor bit 1 mask. */ -#define CLK_PSADIV1_bp 3 /* Prescaler A Division Factor bit 1 position. */ -#define CLK_PSADIV2_bm (1<<4) /* Prescaler A Division Factor bit 2 mask. */ -#define CLK_PSADIV2_bp 4 /* Prescaler A Division Factor bit 2 position. */ -#define CLK_PSADIV3_bm (1<<5) /* Prescaler A Division Factor bit 3 mask. */ -#define CLK_PSADIV3_bp 5 /* Prescaler A Division Factor bit 3 position. */ -#define CLK_PSADIV4_bm (1<<6) /* Prescaler A Division Factor bit 4 mask. */ -#define CLK_PSADIV4_bp 6 /* Prescaler A Division Factor bit 4 position. */ - -#define CLK_PSBCDIV_gm 0x03 /* Prescaler B and C Division factor group mask. */ -#define CLK_PSBCDIV_gp 0 /* Prescaler B and C Division factor group position. */ -#define CLK_PSBCDIV0_bm (1<<0) /* Prescaler B and C Division factor bit 0 mask. */ -#define CLK_PSBCDIV0_bp 0 /* Prescaler B and C Division factor bit 0 position. */ -#define CLK_PSBCDIV1_bm (1<<1) /* Prescaler B and C Division factor bit 1 mask. */ -#define CLK_PSBCDIV1_bp 1 /* Prescaler B and C Division factor bit 1 position. */ - - -/* CLK.LOCK bit masks and bit positions */ -#define CLK_LOCK_bm 0x01 /* Clock System Lock bit mask. */ -#define CLK_LOCK_bp 0 /* Clock System Lock bit position. */ - - -/* CLK.RTCCTRL bit masks and bit positions */ -#define CLK_RTCSRC_gm 0x0E /* Clock Source group mask. */ -#define CLK_RTCSRC_gp 1 /* Clock Source group position. */ -#define CLK_RTCSRC0_bm (1<<1) /* Clock Source bit 0 mask. */ -#define CLK_RTCSRC0_bp 1 /* Clock Source bit 0 position. */ -#define CLK_RTCSRC1_bm (1<<2) /* Clock Source bit 1 mask. */ -#define CLK_RTCSRC1_bp 2 /* Clock Source bit 1 position. */ -#define CLK_RTCSRC2_bm (1<<3) /* Clock Source bit 2 mask. */ -#define CLK_RTCSRC2_bp 3 /* Clock Source bit 2 position. */ - -#define CLK_RTCEN_bm 0x01 /* RTC Clock Source Enable bit mask. */ -#define CLK_RTCEN_bp 0 /* RTC Clock Source Enable bit position. */ - - -/* PR.PRGEN bit masks and bit positions */ -#define PR_AES_bm 0x10 /* AES bit mask. */ -#define PR_AES_bp 4 /* AES bit position. */ - -#define PR_EBI_bm 0x08 /* External Bus Interface bit mask. */ -#define PR_EBI_bp 3 /* External Bus Interface bit position. */ - -#define PR_RTC_bm 0x04 /* Real-time Counter bit mask. */ -#define PR_RTC_bp 2 /* Real-time Counter bit position. */ - -#define PR_EVSYS_bm 0x02 /* Event System bit mask. */ -#define PR_EVSYS_bp 1 /* Event System bit position. */ - -#define PR_DMA_bm 0x01 /* DMA-Controller bit mask. */ -#define PR_DMA_bp 0 /* DMA-Controller bit position. */ - - -/* PR.PRPA bit masks and bit positions */ -#define PR_DAC_bm 0x04 /* Port A DAC bit mask. */ -#define PR_DAC_bp 2 /* Port A DAC bit position. */ - -#define PR_ADC_bm 0x02 /* Port A ADC bit mask. */ -#define PR_ADC_bp 1 /* Port A ADC bit position. */ - -#define PR_AC_bm 0x01 /* Port A Analog Comparator bit mask. */ -#define PR_AC_bp 0 /* Port A Analog Comparator bit position. */ - - -/* PR.PRPB bit masks and bit positions */ -/* PR_DAC_bm Predefined. */ -/* PR_DAC_bp Predefined. */ - -/* PR_ADC_bm Predefined. */ -/* PR_ADC_bp Predefined. */ - -/* PR_AC_bm Predefined. */ -/* PR_AC_bp Predefined. */ - - -/* PR.PRPC bit masks and bit positions */ -#define PR_TWI_bm 0x40 /* Port C Two-wire Interface bit mask. */ -#define PR_TWI_bp 6 /* Port C Two-wire Interface bit position. */ - -#define PR_USART1_bm 0x20 /* Port C USART1 bit mask. */ -#define PR_USART1_bp 5 /* Port C USART1 bit position. */ - -#define PR_USART0_bm 0x10 /* Port C USART0 bit mask. */ -#define PR_USART0_bp 4 /* Port C USART0 bit position. */ - -#define PR_SPI_bm 0x08 /* Port C SPI bit mask. */ -#define PR_SPI_bp 3 /* Port C SPI bit position. */ - -#define PR_HIRES_bm 0x04 /* Port C AWEX bit mask. */ -#define PR_HIRES_bp 2 /* Port C AWEX bit position. */ - -#define PR_TC1_bm 0x02 /* Port C Timer/Counter1 bit mask. */ -#define PR_TC1_bp 1 /* Port C Timer/Counter1 bit position. */ - -#define PR_TC0_bm 0x01 /* Port C Timer/Counter0 bit mask. */ -#define PR_TC0_bp 0 /* Port C Timer/Counter0 bit position. */ - - -/* PR.PRPD bit masks and bit positions */ -/* PR_TWI_bm Predefined. */ -/* PR_TWI_bp Predefined. */ - -/* PR_USART1_bm Predefined. */ -/* PR_USART1_bp Predefined. */ - -/* PR_USART0_bm Predefined. */ -/* PR_USART0_bp Predefined. */ - -/* PR_SPI_bm Predefined. */ -/* PR_SPI_bp Predefined. */ - -/* PR_HIRES_bm Predefined. */ -/* PR_HIRES_bp Predefined. */ - -/* PR_TC1_bm Predefined. */ -/* PR_TC1_bp Predefined. */ - -/* PR_TC0_bm Predefined. */ -/* PR_TC0_bp Predefined. */ - - -/* PR.PRPE bit masks and bit positions */ -/* PR_TWI_bm Predefined. */ -/* PR_TWI_bp Predefined. */ - -/* PR_USART1_bm Predefined. */ -/* PR_USART1_bp Predefined. */ - -/* PR_USART0_bm Predefined. */ -/* PR_USART0_bp Predefined. */ - -/* PR_SPI_bm Predefined. */ -/* PR_SPI_bp Predefined. */ - -/* PR_HIRES_bm Predefined. */ -/* PR_HIRES_bp Predefined. */ - -/* PR_TC1_bm Predefined. */ -/* PR_TC1_bp Predefined. */ - -/* PR_TC0_bm Predefined. */ -/* PR_TC0_bp Predefined. */ - - -/* PR.PRPF bit masks and bit positions */ -/* PR_TWI_bm Predefined. */ -/* PR_TWI_bp Predefined. */ - -/* PR_USART1_bm Predefined. */ -/* PR_USART1_bp Predefined. */ - -/* PR_USART0_bm Predefined. */ -/* PR_USART0_bp Predefined. */ - -/* PR_SPI_bm Predefined. */ -/* PR_SPI_bp Predefined. */ - -/* PR_HIRES_bm Predefined. */ -/* PR_HIRES_bp Predefined. */ - -/* PR_TC1_bm Predefined. */ -/* PR_TC1_bp Predefined. */ - -/* PR_TC0_bm Predefined. */ -/* PR_TC0_bp Predefined. */ - - -/* SLEEP - Sleep Controller */ -/* SLEEP.CTRL bit masks and bit positions */ -#define SLEEP_SMODE_gm 0x0E /* Sleep Mode group mask. */ -#define SLEEP_SMODE_gp 1 /* Sleep Mode group position. */ -#define SLEEP_SMODE0_bm (1<<1) /* Sleep Mode bit 0 mask. */ -#define SLEEP_SMODE0_bp 1 /* Sleep Mode bit 0 position. */ -#define SLEEP_SMODE1_bm (1<<2) /* Sleep Mode bit 1 mask. */ -#define SLEEP_SMODE1_bp 2 /* Sleep Mode bit 1 position. */ -#define SLEEP_SMODE2_bm (1<<3) /* Sleep Mode bit 2 mask. */ -#define SLEEP_SMODE2_bp 3 /* Sleep Mode bit 2 position. */ - -#define SLEEP_SEN_bm 0x01 /* Sleep Enable bit mask. */ -#define SLEEP_SEN_bp 0 /* Sleep Enable bit position. */ - - -/* OSC - Oscillator */ -/* OSC.CTRL bit masks and bit positions */ -#define OSC_PLLEN_bm 0x10 /* PLL Enable bit mask. */ -#define OSC_PLLEN_bp 4 /* PLL Enable bit position. */ - -#define OSC_XOSCEN_bm 0x08 /* External Oscillator Enable bit mask. */ -#define OSC_XOSCEN_bp 3 /* External Oscillator Enable bit position. */ - -#define OSC_RC32KEN_bm 0x04 /* Internal 32kHz RC Oscillator Enable bit mask. */ -#define OSC_RC32KEN_bp 2 /* Internal 32kHz RC Oscillator Enable bit position. */ - -#define OSC_RC32MEN_bm 0x02 /* Internal 32MHz RC Oscillator Enable bit mask. */ -#define OSC_RC32MEN_bp 1 /* Internal 32MHz RC Oscillator Enable bit position. */ - -#define OSC_RC2MEN_bm 0x01 /* Internal 2MHz RC Oscillator Enable bit mask. */ -#define OSC_RC2MEN_bp 0 /* Internal 2MHz RC Oscillator Enable bit position. */ - - -/* OSC.STATUS bit masks and bit positions */ -#define OSC_PLLRDY_bm 0x10 /* PLL Ready bit mask. */ -#define OSC_PLLRDY_bp 4 /* PLL Ready bit position. */ - -#define OSC_XOSCRDY_bm 0x08 /* External Oscillator Ready bit mask. */ -#define OSC_XOSCRDY_bp 3 /* External Oscillator Ready bit position. */ - -#define OSC_RC32KRDY_bm 0x04 /* Internal 32kHz RC Oscillator Ready bit mask. */ -#define OSC_RC32KRDY_bp 2 /* Internal 32kHz RC Oscillator Ready bit position. */ - -#define OSC_RC32MRDY_bm 0x02 /* Internal 32MHz RC Oscillator Ready bit mask. */ -#define OSC_RC32MRDY_bp 1 /* Internal 32MHz RC Oscillator Ready bit position. */ - -#define OSC_RC2MRDY_bm 0x01 /* Internal 2MHz RC Oscillator Ready bit mask. */ -#define OSC_RC2MRDY_bp 0 /* Internal 2MHz RC Oscillator Ready bit position. */ - - -/* OSC.XOSCCTRL bit masks and bit positions */ -#define OSC_FRQRANGE_gm 0xC0 /* Frequency Range group mask. */ -#define OSC_FRQRANGE_gp 6 /* Frequency Range group position. */ -#define OSC_FRQRANGE0_bm (1<<6) /* Frequency Range bit 0 mask. */ -#define OSC_FRQRANGE0_bp 6 /* Frequency Range bit 0 position. */ -#define OSC_FRQRANGE1_bm (1<<7) /* Frequency Range bit 1 mask. */ -#define OSC_FRQRANGE1_bp 7 /* Frequency Range bit 1 position. */ - -#define OSC_X32KLPM_bm 0x20 /* 32kHz XTAL OSC Low-power Mode bit mask. */ -#define OSC_X32KLPM_bp 5 /* 32kHz XTAL OSC Low-power Mode bit position. */ - -#define OSC_XOSCSEL_gm 0x0F /* External Oscillator Selection and Startup Time group mask. */ -#define OSC_XOSCSEL_gp 0 /* External Oscillator Selection and Startup Time group position. */ -#define OSC_XOSCSEL0_bm (1<<0) /* External Oscillator Selection and Startup Time bit 0 mask. */ -#define OSC_XOSCSEL0_bp 0 /* External Oscillator Selection and Startup Time bit 0 position. */ -#define OSC_XOSCSEL1_bm (1<<1) /* External Oscillator Selection and Startup Time bit 1 mask. */ -#define OSC_XOSCSEL1_bp 1 /* External Oscillator Selection and Startup Time bit 1 position. */ -#define OSC_XOSCSEL2_bm (1<<2) /* External Oscillator Selection and Startup Time bit 2 mask. */ -#define OSC_XOSCSEL2_bp 2 /* External Oscillator Selection and Startup Time bit 2 position. */ -#define OSC_XOSCSEL3_bm (1<<3) /* External Oscillator Selection and Startup Time bit 3 mask. */ -#define OSC_XOSCSEL3_bp 3 /* External Oscillator Selection and Startup Time bit 3 position. */ - - -/* OSC.XOSCFAIL bit masks and bit positions */ -#define OSC_XOSCFDIF_bm 0x02 /* Failure Detection Interrupt Flag bit mask. */ -#define OSC_XOSCFDIF_bp 1 /* Failure Detection Interrupt Flag bit position. */ - -#define OSC_XOSCFDEN_bm 0x01 /* Failure Detection Enable bit mask. */ -#define OSC_XOSCFDEN_bp 0 /* Failure Detection Enable bit position. */ - - -/* OSC.PLLCTRL bit masks and bit positions */ -#define OSC_PLLSRC_gm 0xC0 /* Clock Source group mask. */ -#define OSC_PLLSRC_gp 6 /* Clock Source group position. */ -#define OSC_PLLSRC0_bm (1<<6) /* Clock Source bit 0 mask. */ -#define OSC_PLLSRC0_bp 6 /* Clock Source bit 0 position. */ -#define OSC_PLLSRC1_bm (1<<7) /* Clock Source bit 1 mask. */ -#define OSC_PLLSRC1_bp 7 /* Clock Source bit 1 position. */ - -#define OSC_PLLFAC_gm 0x1F /* Multiplication Factor group mask. */ -#define OSC_PLLFAC_gp 0 /* Multiplication Factor group position. */ -#define OSC_PLLFAC0_bm (1<<0) /* Multiplication Factor bit 0 mask. */ -#define OSC_PLLFAC0_bp 0 /* Multiplication Factor bit 0 position. */ -#define OSC_PLLFAC1_bm (1<<1) /* Multiplication Factor bit 1 mask. */ -#define OSC_PLLFAC1_bp 1 /* Multiplication Factor bit 1 position. */ -#define OSC_PLLFAC2_bm (1<<2) /* Multiplication Factor bit 2 mask. */ -#define OSC_PLLFAC2_bp 2 /* Multiplication Factor bit 2 position. */ -#define OSC_PLLFAC3_bm (1<<3) /* Multiplication Factor bit 3 mask. */ -#define OSC_PLLFAC3_bp 3 /* Multiplication Factor bit 3 position. */ -#define OSC_PLLFAC4_bm (1<<4) /* Multiplication Factor bit 4 mask. */ -#define OSC_PLLFAC4_bp 4 /* Multiplication Factor bit 4 position. */ - - -/* OSC.DFLLCTRL bit masks and bit positions */ -#define OSC_RC32MCREF_bm 0x02 /* 32MHz Calibration Reference bit mask. */ -#define OSC_RC32MCREF_bp 1 /* 32MHz Calibration Reference bit position. */ - -#define OSC_RC2MCREF_bm 0x01 /* 2MHz Calibration Reference bit mask. */ -#define OSC_RC2MCREF_bp 0 /* 2MHz Calibration Reference bit position. */ - - -/* DFLL - DFLL */ -/* DFLL.CTRL bit masks and bit positions */ -#define DFLL_ENABLE_bm 0x01 /* DFLL Enable bit mask. */ -#define DFLL_ENABLE_bp 0 /* DFLL Enable bit position. */ - - -/* DFLL.CALA bit masks and bit positions */ -#define DFLL_CALL_gm 0x7F /* DFLL Calibration bits [6:0] group mask. */ -#define DFLL_CALL_gp 0 /* DFLL Calibration bits [6:0] group position. */ -#define DFLL_CALL0_bm (1<<0) /* DFLL Calibration bits [6:0] bit 0 mask. */ -#define DFLL_CALL0_bp 0 /* DFLL Calibration bits [6:0] bit 0 position. */ -#define DFLL_CALL1_bm (1<<1) /* DFLL Calibration bits [6:0] bit 1 mask. */ -#define DFLL_CALL1_bp 1 /* DFLL Calibration bits [6:0] bit 1 position. */ -#define DFLL_CALL2_bm (1<<2) /* DFLL Calibration bits [6:0] bit 2 mask. */ -#define DFLL_CALL2_bp 2 /* DFLL Calibration bits [6:0] bit 2 position. */ -#define DFLL_CALL3_bm (1<<3) /* DFLL Calibration bits [6:0] bit 3 mask. */ -#define DFLL_CALL3_bp 3 /* DFLL Calibration bits [6:0] bit 3 position. */ -#define DFLL_CALL4_bm (1<<4) /* DFLL Calibration bits [6:0] bit 4 mask. */ -#define DFLL_CALL4_bp 4 /* DFLL Calibration bits [6:0] bit 4 position. */ -#define DFLL_CALL5_bm (1<<5) /* DFLL Calibration bits [6:0] bit 5 mask. */ -#define DFLL_CALL5_bp 5 /* DFLL Calibration bits [6:0] bit 5 position. */ -#define DFLL_CALL6_bm (1<<6) /* DFLL Calibration bits [6:0] bit 6 mask. */ -#define DFLL_CALL6_bp 6 /* DFLL Calibration bits [6:0] bit 6 position. */ - - -/* DFLL.CALB bit masks and bit positions */ -#define DFLL_CALH_gm 0x3F /* DFLL Calibration bits [12:7] group mask. */ -#define DFLL_CALH_gp 0 /* DFLL Calibration bits [12:7] group position. */ -#define DFLL_CALH0_bm (1<<0) /* DFLL Calibration bits [12:7] bit 0 mask. */ -#define DFLL_CALH0_bp 0 /* DFLL Calibration bits [12:7] bit 0 position. */ -#define DFLL_CALH1_bm (1<<1) /* DFLL Calibration bits [12:7] bit 1 mask. */ -#define DFLL_CALH1_bp 1 /* DFLL Calibration bits [12:7] bit 1 position. */ -#define DFLL_CALH2_bm (1<<2) /* DFLL Calibration bits [12:7] bit 2 mask. */ -#define DFLL_CALH2_bp 2 /* DFLL Calibration bits [12:7] bit 2 position. */ -#define DFLL_CALH3_bm (1<<3) /* DFLL Calibration bits [12:7] bit 3 mask. */ -#define DFLL_CALH3_bp 3 /* DFLL Calibration bits [12:7] bit 3 position. */ -#define DFLL_CALH4_bm (1<<4) /* DFLL Calibration bits [12:7] bit 4 mask. */ -#define DFLL_CALH4_bp 4 /* DFLL Calibration bits [12:7] bit 4 position. */ -#define DFLL_CALH5_bm (1<<5) /* DFLL Calibration bits [12:7] bit 5 mask. */ -#define DFLL_CALH5_bp 5 /* DFLL Calibration bits [12:7] bit 5 position. */ - - -/* RST - Reset */ -/* RST.STATUS bit masks and bit positions */ -#define RST_SDRF_bm 0x40 /* Spike Detection Reset Flag bit mask. */ -#define RST_SDRF_bp 6 /* Spike Detection Reset Flag bit position. */ - -#define RST_SRF_bm 0x20 /* Software Reset Flag bit mask. */ -#define RST_SRF_bp 5 /* Software Reset Flag bit position. */ - -#define RST_PDIRF_bm 0x10 /* Programming and Debug Interface Interface Reset Flag bit mask. */ -#define RST_PDIRF_bp 4 /* Programming and Debug Interface Interface Reset Flag bit position. */ - -#define RST_WDRF_bm 0x08 /* Watchdog Reset Flag bit mask. */ -#define RST_WDRF_bp 3 /* Watchdog Reset Flag bit position. */ - -#define RST_BORF_bm 0x04 /* Brown-out Reset Flag bit mask. */ -#define RST_BORF_bp 2 /* Brown-out Reset Flag bit position. */ - -#define RST_EXTRF_bm 0x02 /* External Reset Flag bit mask. */ -#define RST_EXTRF_bp 1 /* External Reset Flag bit position. */ - -#define RST_PORF_bm 0x01 /* Power-on Reset Flag bit mask. */ -#define RST_PORF_bp 0 /* Power-on Reset Flag bit position. */ - - -/* RST.CTRL bit masks and bit positions */ -#define RST_SWRST_bm 0x01 /* Software Reset bit mask. */ -#define RST_SWRST_bp 0 /* Software Reset bit position. */ - - -/* WDT - Watch-Dog Timer */ -/* WDT.CTRL bit masks and bit positions */ -#define WDT_PER_gm 0x3C /* Period group mask. */ -#define WDT_PER_gp 2 /* Period group position. */ -#define WDT_PER0_bm (1<<2) /* Period bit 0 mask. */ -#define WDT_PER0_bp 2 /* Period bit 0 position. */ -#define WDT_PER1_bm (1<<3) /* Period bit 1 mask. */ -#define WDT_PER1_bp 3 /* Period bit 1 position. */ -#define WDT_PER2_bm (1<<4) /* Period bit 2 mask. */ -#define WDT_PER2_bp 4 /* Period bit 2 position. */ -#define WDT_PER3_bm (1<<5) /* Period bit 3 mask. */ -#define WDT_PER3_bp 5 /* Period bit 3 position. */ - -#define WDT_ENABLE_bm 0x02 /* Enable bit mask. */ -#define WDT_ENABLE_bp 1 /* Enable bit position. */ - -#define WDT_CEN_bm 0x01 /* Change Enable bit mask. */ -#define WDT_CEN_bp 0 /* Change Enable bit position. */ - - -/* WDT.WINCTRL bit masks and bit positions */ -#define WDT_WPER_gm 0x3C /* Windowed Mode Period group mask. */ -#define WDT_WPER_gp 2 /* Windowed Mode Period group position. */ -#define WDT_WPER0_bm (1<<2) /* Windowed Mode Period bit 0 mask. */ -#define WDT_WPER0_bp 2 /* Windowed Mode Period bit 0 position. */ -#define WDT_WPER1_bm (1<<3) /* Windowed Mode Period bit 1 mask. */ -#define WDT_WPER1_bp 3 /* Windowed Mode Period bit 1 position. */ -#define WDT_WPER2_bm (1<<4) /* Windowed Mode Period bit 2 mask. */ -#define WDT_WPER2_bp 4 /* Windowed Mode Period bit 2 position. */ -#define WDT_WPER3_bm (1<<5) /* Windowed Mode Period bit 3 mask. */ -#define WDT_WPER3_bp 5 /* Windowed Mode Period bit 3 position. */ - -#define WDT_WEN_bm 0x02 /* Windowed Mode Enable bit mask. */ -#define WDT_WEN_bp 1 /* Windowed Mode Enable bit position. */ - -#define WDT_WCEN_bm 0x01 /* Windowed Mode Change Enable bit mask. */ -#define WDT_WCEN_bp 0 /* Windowed Mode Change Enable bit position. */ - - -/* WDT.STATUS bit masks and bit positions */ -#define WDT_SYNCBUSY_bm 0x01 /* Syncronization busy bit mask. */ -#define WDT_SYNCBUSY_bp 0 /* Syncronization busy bit position. */ - - -/* MCU - MCU Control */ -/* MCU.MCUCR bit masks and bit positions */ -#define MCU_JTAGD_bm 0x01 /* JTAG Disable bit mask. */ -#define MCU_JTAGD_bp 0 /* JTAG Disable bit position. */ - - -/* MCU.EVSYSLOCK bit masks and bit positions */ -#define MCU_EVSYS1LOCK_bm 0x10 /* Event Channel 4-7 Lock bit mask. */ -#define MCU_EVSYS1LOCK_bp 4 /* Event Channel 4-7 Lock bit position. */ - -#define MCU_EVSYS0LOCK_bm 0x01 /* Event Channel 0-3 Lock bit mask. */ -#define MCU_EVSYS0LOCK_bp 0 /* Event Channel 0-3 Lock bit position. */ - - -/* MCU.AWEXLOCK bit masks and bit positions */ -#define MCU_AWEXELOCK_bm 0x04 /* AWeX on T/C E0 Lock bit mask. */ -#define MCU_AWEXELOCK_bp 2 /* AWeX on T/C E0 Lock bit position. */ - -#define MCU_AWEXCLOCK_bm 0x01 /* AWeX on T/C C0 Lock bit mask. */ -#define MCU_AWEXCLOCK_bp 0 /* AWeX on T/C C0 Lock bit position. */ - - -/* PMIC - Programmable Multi-level Interrupt Controller */ -/* PMIC.STATUS bit masks and bit positions */ -#define PMIC_NMIEX_bm 0x80 /* Non-maskable Interrupt Executing bit mask. */ -#define PMIC_NMIEX_bp 7 /* Non-maskable Interrupt Executing bit position. */ - -#define PMIC_HILVLEX_bm 0x04 /* High Level Interrupt Executing bit mask. */ -#define PMIC_HILVLEX_bp 2 /* High Level Interrupt Executing bit position. */ - -#define PMIC_MEDLVLEX_bm 0x02 /* Medium Level Interrupt Executing bit mask. */ -#define PMIC_MEDLVLEX_bp 1 /* Medium Level Interrupt Executing bit position. */ - -#define PMIC_LOLVLEX_bm 0x01 /* Low Level Interrupt Executing bit mask. */ -#define PMIC_LOLVLEX_bp 0 /* Low Level Interrupt Executing bit position. */ - - -/* PMIC.CTRL bit masks and bit positions */ -#define PMIC_RREN_bm 0x80 /* Round-Robin Priority Enable bit mask. */ -#define PMIC_RREN_bp 7 /* Round-Robin Priority Enable bit position. */ - -#define PMIC_IVSEL_bm 0x40 /* Interrupt Vector Select bit mask. */ -#define PMIC_IVSEL_bp 6 /* Interrupt Vector Select bit position. */ - -#define PMIC_HILVLEN_bm 0x04 /* High Level Enable bit mask. */ -#define PMIC_HILVLEN_bp 2 /* High Level Enable bit position. */ - -#define PMIC_MEDLVLEN_bm 0x02 /* Medium Level Enable bit mask. */ -#define PMIC_MEDLVLEN_bp 1 /* Medium Level Enable bit position. */ - -#define PMIC_LOLVLEN_bm 0x01 /* Low Level Enable bit mask. */ -#define PMIC_LOLVLEN_bp 0 /* Low Level Enable bit position. */ - - -/* DMA - DMA Controller */ -/* DMA_CH.CTRLA bit masks and bit positions */ -#define DMA_CH_ENABLE_bm 0x80 /* Channel Enable bit mask. */ -#define DMA_CH_ENABLE_bp 7 /* Channel Enable bit position. */ - -#define DMA_CH_RESET_bm 0x40 /* Channel Software Reset bit mask. */ -#define DMA_CH_RESET_bp 6 /* Channel Software Reset bit position. */ - -#define DMA_CH_REPEAT_bm 0x20 /* Channel Repeat Mode bit mask. */ -#define DMA_CH_REPEAT_bp 5 /* Channel Repeat Mode bit position. */ - -#define DMA_CH_TRFREQ_bm 0x10 /* Channel Transfer Request bit mask. */ -#define DMA_CH_TRFREQ_bp 4 /* Channel Transfer Request bit position. */ - -#define DMA_CH_SINGLE_bm 0x04 /* Channel Single Shot Data Transfer bit mask. */ -#define DMA_CH_SINGLE_bp 2 /* Channel Single Shot Data Transfer bit position. */ - -#define DMA_CH_BURSTLEN_gm 0x03 /* Channel Transfer Mode group mask. */ -#define DMA_CH_BURSTLEN_gp 0 /* Channel Transfer Mode group position. */ -#define DMA_CH_BURSTLEN0_bm (1<<0) /* Channel Transfer Mode bit 0 mask. */ -#define DMA_CH_BURSTLEN0_bp 0 /* Channel Transfer Mode bit 0 position. */ -#define DMA_CH_BURSTLEN1_bm (1<<1) /* Channel Transfer Mode bit 1 mask. */ -#define DMA_CH_BURSTLEN1_bp 1 /* Channel Transfer Mode bit 1 position. */ - - -/* DMA_CH.CTRLB bit masks and bit positions */ -#define DMA_CH_CHBUSY_bm 0x80 /* Block Transfer Busy bit mask. */ -#define DMA_CH_CHBUSY_bp 7 /* Block Transfer Busy bit position. */ - -#define DMA_CH_CHPEND_bm 0x40 /* Block Transfer Pending bit mask. */ -#define DMA_CH_CHPEND_bp 6 /* Block Transfer Pending bit position. */ - -#define DMA_CH_ERRIF_bm 0x20 /* Block Transfer Error Interrupt Flag bit mask. */ -#define DMA_CH_ERRIF_bp 5 /* Block Transfer Error Interrupt Flag bit position. */ - -#define DMA_CH_TRNIF_bm 0x10 /* Transaction Complete Interrup Flag bit mask. */ -#define DMA_CH_TRNIF_bp 4 /* Transaction Complete Interrup Flag bit position. */ - -#define DMA_CH_ERRINTLVL_gm 0x0C /* Transfer Error Interrupt Level group mask. */ -#define DMA_CH_ERRINTLVL_gp 2 /* Transfer Error Interrupt Level group position. */ -#define DMA_CH_ERRINTLVL0_bm (1<<2) /* Transfer Error Interrupt Level bit 0 mask. */ -#define DMA_CH_ERRINTLVL0_bp 2 /* Transfer Error Interrupt Level bit 0 position. */ -#define DMA_CH_ERRINTLVL1_bm (1<<3) /* Transfer Error Interrupt Level bit 1 mask. */ -#define DMA_CH_ERRINTLVL1_bp 3 /* Transfer Error Interrupt Level bit 1 position. */ - -#define DMA_CH_TRNINTLVL_gm 0x03 /* Transaction Complete Interrupt Level group mask. */ -#define DMA_CH_TRNINTLVL_gp 0 /* Transaction Complete Interrupt Level group position. */ -#define DMA_CH_TRNINTLVL0_bm (1<<0) /* Transaction Complete Interrupt Level bit 0 mask. */ -#define DMA_CH_TRNINTLVL0_bp 0 /* Transaction Complete Interrupt Level bit 0 position. */ -#define DMA_CH_TRNINTLVL1_bm (1<<1) /* Transaction Complete Interrupt Level bit 1 mask. */ -#define DMA_CH_TRNINTLVL1_bp 1 /* Transaction Complete Interrupt Level bit 1 position. */ - - -/* DMA_CH.ADDRCTRL bit masks and bit positions */ -#define DMA_CH_SRCRELOAD_gm 0xC0 /* Channel Source Address Reload group mask. */ -#define DMA_CH_SRCRELOAD_gp 6 /* Channel Source Address Reload group position. */ -#define DMA_CH_SRCRELOAD0_bm (1<<6) /* Channel Source Address Reload bit 0 mask. */ -#define DMA_CH_SRCRELOAD0_bp 6 /* Channel Source Address Reload bit 0 position. */ -#define DMA_CH_SRCRELOAD1_bm (1<<7) /* Channel Source Address Reload bit 1 mask. */ -#define DMA_CH_SRCRELOAD1_bp 7 /* Channel Source Address Reload bit 1 position. */ - -#define DMA_CH_SRCDIR_gm 0x30 /* Channel Source Address Mode group mask. */ -#define DMA_CH_SRCDIR_gp 4 /* Channel Source Address Mode group position. */ -#define DMA_CH_SRCDIR0_bm (1<<4) /* Channel Source Address Mode bit 0 mask. */ -#define DMA_CH_SRCDIR0_bp 4 /* Channel Source Address Mode bit 0 position. */ -#define DMA_CH_SRCDIR1_bm (1<<5) /* Channel Source Address Mode bit 1 mask. */ -#define DMA_CH_SRCDIR1_bp 5 /* Channel Source Address Mode bit 1 position. */ - -#define DMA_CH_DESTRELOAD_gm 0x0C /* Channel Destination Address Reload group mask. */ -#define DMA_CH_DESTRELOAD_gp 2 /* Channel Destination Address Reload group position. */ -#define DMA_CH_DESTRELOAD0_bm (1<<2) /* Channel Destination Address Reload bit 0 mask. */ -#define DMA_CH_DESTRELOAD0_bp 2 /* Channel Destination Address Reload bit 0 position. */ -#define DMA_CH_DESTRELOAD1_bm (1<<3) /* Channel Destination Address Reload bit 1 mask. */ -#define DMA_CH_DESTRELOAD1_bp 3 /* Channel Destination Address Reload bit 1 position. */ - -#define DMA_CH_DESTDIR_gm 0x03 /* Channel Destination Address Mode group mask. */ -#define DMA_CH_DESTDIR_gp 0 /* Channel Destination Address Mode group position. */ -#define DMA_CH_DESTDIR0_bm (1<<0) /* Channel Destination Address Mode bit 0 mask. */ -#define DMA_CH_DESTDIR0_bp 0 /* Channel Destination Address Mode bit 0 position. */ -#define DMA_CH_DESTDIR1_bm (1<<1) /* Channel Destination Address Mode bit 1 mask. */ -#define DMA_CH_DESTDIR1_bp 1 /* Channel Destination Address Mode bit 1 position. */ - - -/* DMA_CH.TRIGSRC bit masks and bit positions */ -#define DMA_CH_TRIGSRC_gm 0xFF /* Channel Trigger Source group mask. */ -#define DMA_CH_TRIGSRC_gp 0 /* Channel Trigger Source group position. */ -#define DMA_CH_TRIGSRC0_bm (1<<0) /* Channel Trigger Source bit 0 mask. */ -#define DMA_CH_TRIGSRC0_bp 0 /* Channel Trigger Source bit 0 position. */ -#define DMA_CH_TRIGSRC1_bm (1<<1) /* Channel Trigger Source bit 1 mask. */ -#define DMA_CH_TRIGSRC1_bp 1 /* Channel Trigger Source bit 1 position. */ -#define DMA_CH_TRIGSRC2_bm (1<<2) /* Channel Trigger Source bit 2 mask. */ -#define DMA_CH_TRIGSRC2_bp 2 /* Channel Trigger Source bit 2 position. */ -#define DMA_CH_TRIGSRC3_bm (1<<3) /* Channel Trigger Source bit 3 mask. */ -#define DMA_CH_TRIGSRC3_bp 3 /* Channel Trigger Source bit 3 position. */ -#define DMA_CH_TRIGSRC4_bm (1<<4) /* Channel Trigger Source bit 4 mask. */ -#define DMA_CH_TRIGSRC4_bp 4 /* Channel Trigger Source bit 4 position. */ -#define DMA_CH_TRIGSRC5_bm (1<<5) /* Channel Trigger Source bit 5 mask. */ -#define DMA_CH_TRIGSRC5_bp 5 /* Channel Trigger Source bit 5 position. */ -#define DMA_CH_TRIGSRC6_bm (1<<6) /* Channel Trigger Source bit 6 mask. */ -#define DMA_CH_TRIGSRC6_bp 6 /* Channel Trigger Source bit 6 position. */ -#define DMA_CH_TRIGSRC7_bm (1<<7) /* Channel Trigger Source bit 7 mask. */ -#define DMA_CH_TRIGSRC7_bp 7 /* Channel Trigger Source bit 7 position. */ - - -/* DMA.CTRL bit masks and bit positions */ -#define DMA_ENABLE_bm 0x80 /* Enable bit mask. */ -#define DMA_ENABLE_bp 7 /* Enable bit position. */ - -#define DMA_RESET_bm 0x40 /* Software Reset bit mask. */ -#define DMA_RESET_bp 6 /* Software Reset bit position. */ - -#define DMA_DBUFMODE_gm 0x0C /* Double Buffering Mode group mask. */ -#define DMA_DBUFMODE_gp 2 /* Double Buffering Mode group position. */ -#define DMA_DBUFMODE0_bm (1<<2) /* Double Buffering Mode bit 0 mask. */ -#define DMA_DBUFMODE0_bp 2 /* Double Buffering Mode bit 0 position. */ -#define DMA_DBUFMODE1_bm (1<<3) /* Double Buffering Mode bit 1 mask. */ -#define DMA_DBUFMODE1_bp 3 /* Double Buffering Mode bit 1 position. */ - -#define DMA_PRIMODE_gm 0x03 /* Channel Priority Mode group mask. */ -#define DMA_PRIMODE_gp 0 /* Channel Priority Mode group position. */ -#define DMA_PRIMODE0_bm (1<<0) /* Channel Priority Mode bit 0 mask. */ -#define DMA_PRIMODE0_bp 0 /* Channel Priority Mode bit 0 position. */ -#define DMA_PRIMODE1_bm (1<<1) /* Channel Priority Mode bit 1 mask. */ -#define DMA_PRIMODE1_bp 1 /* Channel Priority Mode bit 1 position. */ - - -/* DMA.INTFLAGS bit masks and bit positions */ -#define DMA_CH3ERRIF_bm 0x80 /* Channel 3 Block Transfer Error Interrupt Flag bit mask. */ -#define DMA_CH3ERRIF_bp 7 /* Channel 3 Block Transfer Error Interrupt Flag bit position. */ - -#define DMA_CH2ERRIF_bm 0x40 /* Channel 2 Block Transfer Error Interrupt Flag bit mask. */ -#define DMA_CH2ERRIF_bp 6 /* Channel 2 Block Transfer Error Interrupt Flag bit position. */ - -#define DMA_CH1ERRIF_bm 0x20 /* Channel 1 Block Transfer Error Interrupt Flag bit mask. */ -#define DMA_CH1ERRIF_bp 5 /* Channel 1 Block Transfer Error Interrupt Flag bit position. */ - -#define DMA_CH0ERRIF_bm 0x10 /* Channel 0 Block Transfer Error Interrupt Flag bit mask. */ -#define DMA_CH0ERRIF_bp 4 /* Channel 0 Block Transfer Error Interrupt Flag bit position. */ - -#define DMA_CH3TRNIF_bm 0x08 /* Channel 3 Transaction Complete Interrupt Flag bit mask. */ -#define DMA_CH3TRNIF_bp 3 /* Channel 3 Transaction Complete Interrupt Flag bit position. */ - -#define DMA_CH2TRNIF_bm 0x04 /* Channel 2 Transaction Complete Interrupt Flag bit mask. */ -#define DMA_CH2TRNIF_bp 2 /* Channel 2 Transaction Complete Interrupt Flag bit position. */ - -#define DMA_CH1TRNIF_bm 0x02 /* Channel 1 Transaction Complete Interrupt Flag bit mask. */ -#define DMA_CH1TRNIF_bp 1 /* Channel 1 Transaction Complete Interrupt Flag bit position. */ - -#define DMA_CH0TRNIF_bm 0x01 /* Channel 0 Transaction Complete Interrupt Flag bit mask. */ -#define DMA_CH0TRNIF_bp 0 /* Channel 0 Transaction Complete Interrupt Flag bit position. */ - - -/* DMA.STATUS bit masks and bit positions */ -#define DMA_CH3BUSY_bm 0x80 /* Channel 3 Block Transfer Busy bit mask. */ -#define DMA_CH3BUSY_bp 7 /* Channel 3 Block Transfer Busy bit position. */ - -#define DMA_CH2BUSY_bm 0x40 /* Channel 2 Block Transfer Busy bit mask. */ -#define DMA_CH2BUSY_bp 6 /* Channel 2 Block Transfer Busy bit position. */ - -#define DMA_CH1BUSY_bm 0x20 /* Channel 1 Block Transfer Busy bit mask. */ -#define DMA_CH1BUSY_bp 5 /* Channel 1 Block Transfer Busy bit position. */ - -#define DMA_CH0BUSY_bm 0x10 /* Channel 0 Block Transfer Busy bit mask. */ -#define DMA_CH0BUSY_bp 4 /* Channel 0 Block Transfer Busy bit position. */ - -#define DMA_CH3PEND_bm 0x08 /* Channel 3 Block Transfer Pending bit mask. */ -#define DMA_CH3PEND_bp 3 /* Channel 3 Block Transfer Pending bit position. */ - -#define DMA_CH2PEND_bm 0x04 /* Channel 2 Block Transfer Pending bit mask. */ -#define DMA_CH2PEND_bp 2 /* Channel 2 Block Transfer Pending bit position. */ - -#define DMA_CH1PEND_bm 0x02 /* Channel 1 Block Transfer Pending bit mask. */ -#define DMA_CH1PEND_bp 1 /* Channel 1 Block Transfer Pending bit position. */ - -#define DMA_CH0PEND_bm 0x01 /* Channel 0 Block Transfer Pending bit mask. */ -#define DMA_CH0PEND_bp 0 /* Channel 0 Block Transfer Pending bit position. */ - - -/* EVSYS - Event System */ -/* EVSYS.CH0MUX bit masks and bit positions */ -#define EVSYS_CHMUX_gm 0xFF /* Event Channel 0 Multiplexer group mask. */ -#define EVSYS_CHMUX_gp 0 /* Event Channel 0 Multiplexer group position. */ -#define EVSYS_CHMUX0_bm (1<<0) /* Event Channel 0 Multiplexer bit 0 mask. */ -#define EVSYS_CHMUX0_bp 0 /* Event Channel 0 Multiplexer bit 0 position. */ -#define EVSYS_CHMUX1_bm (1<<1) /* Event Channel 0 Multiplexer bit 1 mask. */ -#define EVSYS_CHMUX1_bp 1 /* Event Channel 0 Multiplexer bit 1 position. */ -#define EVSYS_CHMUX2_bm (1<<2) /* Event Channel 0 Multiplexer bit 2 mask. */ -#define EVSYS_CHMUX2_bp 2 /* Event Channel 0 Multiplexer bit 2 position. */ -#define EVSYS_CHMUX3_bm (1<<3) /* Event Channel 0 Multiplexer bit 3 mask. */ -#define EVSYS_CHMUX3_bp 3 /* Event Channel 0 Multiplexer bit 3 position. */ -#define EVSYS_CHMUX4_bm (1<<4) /* Event Channel 0 Multiplexer bit 4 mask. */ -#define EVSYS_CHMUX4_bp 4 /* Event Channel 0 Multiplexer bit 4 position. */ -#define EVSYS_CHMUX5_bm (1<<5) /* Event Channel 0 Multiplexer bit 5 mask. */ -#define EVSYS_CHMUX5_bp 5 /* Event Channel 0 Multiplexer bit 5 position. */ -#define EVSYS_CHMUX6_bm (1<<6) /* Event Channel 0 Multiplexer bit 6 mask. */ -#define EVSYS_CHMUX6_bp 6 /* Event Channel 0 Multiplexer bit 6 position. */ -#define EVSYS_CHMUX7_bm (1<<7) /* Event Channel 0 Multiplexer bit 7 mask. */ -#define EVSYS_CHMUX7_bp 7 /* Event Channel 0 Multiplexer bit 7 position. */ - - -/* EVSYS.CH1MUX bit masks and bit positions */ -/* EVSYS_CHMUX_gm Predefined. */ -/* EVSYS_CHMUX_gp Predefined. */ -/* EVSYS_CHMUX0_bm Predefined. */ -/* EVSYS_CHMUX0_bp Predefined. */ -/* EVSYS_CHMUX1_bm Predefined. */ -/* EVSYS_CHMUX1_bp Predefined. */ -/* EVSYS_CHMUX2_bm Predefined. */ -/* EVSYS_CHMUX2_bp Predefined. */ -/* EVSYS_CHMUX3_bm Predefined. */ -/* EVSYS_CHMUX3_bp Predefined. */ -/* EVSYS_CHMUX4_bm Predefined. */ -/* EVSYS_CHMUX4_bp Predefined. */ -/* EVSYS_CHMUX5_bm Predefined. */ -/* EVSYS_CHMUX5_bp Predefined. */ -/* EVSYS_CHMUX6_bm Predefined. */ -/* EVSYS_CHMUX6_bp Predefined. */ -/* EVSYS_CHMUX7_bm Predefined. */ -/* EVSYS_CHMUX7_bp Predefined. */ - - -/* EVSYS.CH2MUX bit masks and bit positions */ -/* EVSYS_CHMUX_gm Predefined. */ -/* EVSYS_CHMUX_gp Predefined. */ -/* EVSYS_CHMUX0_bm Predefined. */ -/* EVSYS_CHMUX0_bp Predefined. */ -/* EVSYS_CHMUX1_bm Predefined. */ -/* EVSYS_CHMUX1_bp Predefined. */ -/* EVSYS_CHMUX2_bm Predefined. */ -/* EVSYS_CHMUX2_bp Predefined. */ -/* EVSYS_CHMUX3_bm Predefined. */ -/* EVSYS_CHMUX3_bp Predefined. */ -/* EVSYS_CHMUX4_bm Predefined. */ -/* EVSYS_CHMUX4_bp Predefined. */ -/* EVSYS_CHMUX5_bm Predefined. */ -/* EVSYS_CHMUX5_bp Predefined. */ -/* EVSYS_CHMUX6_bm Predefined. */ -/* EVSYS_CHMUX6_bp Predefined. */ -/* EVSYS_CHMUX7_bm Predefined. */ -/* EVSYS_CHMUX7_bp Predefined. */ - - -/* EVSYS.CH3MUX bit masks and bit positions */ -/* EVSYS_CHMUX_gm Predefined. */ -/* EVSYS_CHMUX_gp Predefined. */ -/* EVSYS_CHMUX0_bm Predefined. */ -/* EVSYS_CHMUX0_bp Predefined. */ -/* EVSYS_CHMUX1_bm Predefined. */ -/* EVSYS_CHMUX1_bp Predefined. */ -/* EVSYS_CHMUX2_bm Predefined. */ -/* EVSYS_CHMUX2_bp Predefined. */ -/* EVSYS_CHMUX3_bm Predefined. */ -/* EVSYS_CHMUX3_bp Predefined. */ -/* EVSYS_CHMUX4_bm Predefined. */ -/* EVSYS_CHMUX4_bp Predefined. */ -/* EVSYS_CHMUX5_bm Predefined. */ -/* EVSYS_CHMUX5_bp Predefined. */ -/* EVSYS_CHMUX6_bm Predefined. */ -/* EVSYS_CHMUX6_bp Predefined. */ -/* EVSYS_CHMUX7_bm Predefined. */ -/* EVSYS_CHMUX7_bp Predefined. */ - - -/* EVSYS.CH4MUX bit masks and bit positions */ -/* EVSYS_CHMUX_gm Predefined. */ -/* EVSYS_CHMUX_gp Predefined. */ -/* EVSYS_CHMUX0_bm Predefined. */ -/* EVSYS_CHMUX0_bp Predefined. */ -/* EVSYS_CHMUX1_bm Predefined. */ -/* EVSYS_CHMUX1_bp Predefined. */ -/* EVSYS_CHMUX2_bm Predefined. */ -/* EVSYS_CHMUX2_bp Predefined. */ -/* EVSYS_CHMUX3_bm Predefined. */ -/* EVSYS_CHMUX3_bp Predefined. */ -/* EVSYS_CHMUX4_bm Predefined. */ -/* EVSYS_CHMUX4_bp Predefined. */ -/* EVSYS_CHMUX5_bm Predefined. */ -/* EVSYS_CHMUX5_bp Predefined. */ -/* EVSYS_CHMUX6_bm Predefined. */ -/* EVSYS_CHMUX6_bp Predefined. */ -/* EVSYS_CHMUX7_bm Predefined. */ -/* EVSYS_CHMUX7_bp Predefined. */ - - -/* EVSYS.CH5MUX bit masks and bit positions */ -/* EVSYS_CHMUX_gm Predefined. */ -/* EVSYS_CHMUX_gp Predefined. */ -/* EVSYS_CHMUX0_bm Predefined. */ -/* EVSYS_CHMUX0_bp Predefined. */ -/* EVSYS_CHMUX1_bm Predefined. */ -/* EVSYS_CHMUX1_bp Predefined. */ -/* EVSYS_CHMUX2_bm Predefined. */ -/* EVSYS_CHMUX2_bp Predefined. */ -/* EVSYS_CHMUX3_bm Predefined. */ -/* EVSYS_CHMUX3_bp Predefined. */ -/* EVSYS_CHMUX4_bm Predefined. */ -/* EVSYS_CHMUX4_bp Predefined. */ -/* EVSYS_CHMUX5_bm Predefined. */ -/* EVSYS_CHMUX5_bp Predefined. */ -/* EVSYS_CHMUX6_bm Predefined. */ -/* EVSYS_CHMUX6_bp Predefined. */ -/* EVSYS_CHMUX7_bm Predefined. */ -/* EVSYS_CHMUX7_bp Predefined. */ - - -/* EVSYS.CH6MUX bit masks and bit positions */ -/* EVSYS_CHMUX_gm Predefined. */ -/* EVSYS_CHMUX_gp Predefined. */ -/* EVSYS_CHMUX0_bm Predefined. */ -/* EVSYS_CHMUX0_bp Predefined. */ -/* EVSYS_CHMUX1_bm Predefined. */ -/* EVSYS_CHMUX1_bp Predefined. */ -/* EVSYS_CHMUX2_bm Predefined. */ -/* EVSYS_CHMUX2_bp Predefined. */ -/* EVSYS_CHMUX3_bm Predefined. */ -/* EVSYS_CHMUX3_bp Predefined. */ -/* EVSYS_CHMUX4_bm Predefined. */ -/* EVSYS_CHMUX4_bp Predefined. */ -/* EVSYS_CHMUX5_bm Predefined. */ -/* EVSYS_CHMUX5_bp Predefined. */ -/* EVSYS_CHMUX6_bm Predefined. */ -/* EVSYS_CHMUX6_bp Predefined. */ -/* EVSYS_CHMUX7_bm Predefined. */ -/* EVSYS_CHMUX7_bp Predefined. */ - - -/* EVSYS.CH7MUX bit masks and bit positions */ -/* EVSYS_CHMUX_gm Predefined. */ -/* EVSYS_CHMUX_gp Predefined. */ -/* EVSYS_CHMUX0_bm Predefined. */ -/* EVSYS_CHMUX0_bp Predefined. */ -/* EVSYS_CHMUX1_bm Predefined. */ -/* EVSYS_CHMUX1_bp Predefined. */ -/* EVSYS_CHMUX2_bm Predefined. */ -/* EVSYS_CHMUX2_bp Predefined. */ -/* EVSYS_CHMUX3_bm Predefined. */ -/* EVSYS_CHMUX3_bp Predefined. */ -/* EVSYS_CHMUX4_bm Predefined. */ -/* EVSYS_CHMUX4_bp Predefined. */ -/* EVSYS_CHMUX5_bm Predefined. */ -/* EVSYS_CHMUX5_bp Predefined. */ -/* EVSYS_CHMUX6_bm Predefined. */ -/* EVSYS_CHMUX6_bp Predefined. */ -/* EVSYS_CHMUX7_bm Predefined. */ -/* EVSYS_CHMUX7_bp Predefined. */ - - -/* EVSYS.CH0CTRL bit masks and bit positions */ -#define EVSYS_QDIRM_gm 0x60 /* Quadrature Decoder Index Recognition Mode group mask. */ -#define EVSYS_QDIRM_gp 5 /* Quadrature Decoder Index Recognition Mode group position. */ -#define EVSYS_QDIRM0_bm (1<<5) /* Quadrature Decoder Index Recognition Mode bit 0 mask. */ -#define EVSYS_QDIRM0_bp 5 /* Quadrature Decoder Index Recognition Mode bit 0 position. */ -#define EVSYS_QDIRM1_bm (1<<6) /* Quadrature Decoder Index Recognition Mode bit 1 mask. */ -#define EVSYS_QDIRM1_bp 6 /* Quadrature Decoder Index Recognition Mode bit 1 position. */ - -#define EVSYS_QDIEN_bm 0x10 /* Quadrature Decoder Index Enable bit mask. */ -#define EVSYS_QDIEN_bp 4 /* Quadrature Decoder Index Enable bit position. */ - -#define EVSYS_QDEN_bm 0x08 /* Quadrature Decoder Enable bit mask. */ -#define EVSYS_QDEN_bp 3 /* Quadrature Decoder Enable bit position. */ - -#define EVSYS_DIGFILT_gm 0x07 /* Digital Filter group mask. */ -#define EVSYS_DIGFILT_gp 0 /* Digital Filter group position. */ -#define EVSYS_DIGFILT0_bm (1<<0) /* Digital Filter bit 0 mask. */ -#define EVSYS_DIGFILT0_bp 0 /* Digital Filter bit 0 position. */ -#define EVSYS_DIGFILT1_bm (1<<1) /* Digital Filter bit 1 mask. */ -#define EVSYS_DIGFILT1_bp 1 /* Digital Filter bit 1 position. */ -#define EVSYS_DIGFILT2_bm (1<<2) /* Digital Filter bit 2 mask. */ -#define EVSYS_DIGFILT2_bp 2 /* Digital Filter bit 2 position. */ - - -/* EVSYS.CH1CTRL bit masks and bit positions */ -/* EVSYS_DIGFILT_gm Predefined. */ -/* EVSYS_DIGFILT_gp Predefined. */ -/* EVSYS_DIGFILT0_bm Predefined. */ -/* EVSYS_DIGFILT0_bp Predefined. */ -/* EVSYS_DIGFILT1_bm Predefined. */ -/* EVSYS_DIGFILT1_bp Predefined. */ -/* EVSYS_DIGFILT2_bm Predefined. */ -/* EVSYS_DIGFILT2_bp Predefined. */ - - -/* EVSYS.CH2CTRL bit masks and bit positions */ -/* EVSYS_QDIRM_gm Predefined. */ -/* EVSYS_QDIRM_gp Predefined. */ -/* EVSYS_QDIRM0_bm Predefined. */ -/* EVSYS_QDIRM0_bp Predefined. */ -/* EVSYS_QDIRM1_bm Predefined. */ -/* EVSYS_QDIRM1_bp Predefined. */ - -/* EVSYS_QDIEN_bm Predefined. */ -/* EVSYS_QDIEN_bp Predefined. */ - -/* EVSYS_QDEN_bm Predefined. */ -/* EVSYS_QDEN_bp Predefined. */ - -/* EVSYS_DIGFILT_gm Predefined. */ -/* EVSYS_DIGFILT_gp Predefined. */ -/* EVSYS_DIGFILT0_bm Predefined. */ -/* EVSYS_DIGFILT0_bp Predefined. */ -/* EVSYS_DIGFILT1_bm Predefined. */ -/* EVSYS_DIGFILT1_bp Predefined. */ -/* EVSYS_DIGFILT2_bm Predefined. */ -/* EVSYS_DIGFILT2_bp Predefined. */ - - -/* EVSYS.CH3CTRL bit masks and bit positions */ -/* EVSYS_DIGFILT_gm Predefined. */ -/* EVSYS_DIGFILT_gp Predefined. */ -/* EVSYS_DIGFILT0_bm Predefined. */ -/* EVSYS_DIGFILT0_bp Predefined. */ -/* EVSYS_DIGFILT1_bm Predefined. */ -/* EVSYS_DIGFILT1_bp Predefined. */ -/* EVSYS_DIGFILT2_bm Predefined. */ -/* EVSYS_DIGFILT2_bp Predefined. */ - - -/* EVSYS.CH4CTRL bit masks and bit positions */ -/* EVSYS_QDIRM_gm Predefined. */ -/* EVSYS_QDIRM_gp Predefined. */ -/* EVSYS_QDIRM0_bm Predefined. */ -/* EVSYS_QDIRM0_bp Predefined. */ -/* EVSYS_QDIRM1_bm Predefined. */ -/* EVSYS_QDIRM1_bp Predefined. */ - -/* EVSYS_QDIEN_bm Predefined. */ -/* EVSYS_QDIEN_bp Predefined. */ - -/* EVSYS_QDEN_bm Predefined. */ -/* EVSYS_QDEN_bp Predefined. */ - -/* EVSYS_DIGFILT_gm Predefined. */ -/* EVSYS_DIGFILT_gp Predefined. */ -/* EVSYS_DIGFILT0_bm Predefined. */ -/* EVSYS_DIGFILT0_bp Predefined. */ -/* EVSYS_DIGFILT1_bm Predefined. */ -/* EVSYS_DIGFILT1_bp Predefined. */ -/* EVSYS_DIGFILT2_bm Predefined. */ -/* EVSYS_DIGFILT2_bp Predefined. */ - - -/* EVSYS.CH5CTRL bit masks and bit positions */ -/* EVSYS_DIGFILT_gm Predefined. */ -/* EVSYS_DIGFILT_gp Predefined. */ -/* EVSYS_DIGFILT0_bm Predefined. */ -/* EVSYS_DIGFILT0_bp Predefined. */ -/* EVSYS_DIGFILT1_bm Predefined. */ -/* EVSYS_DIGFILT1_bp Predefined. */ -/* EVSYS_DIGFILT2_bm Predefined. */ -/* EVSYS_DIGFILT2_bp Predefined. */ - - -/* EVSYS.CH6CTRL bit masks and bit positions */ -/* EVSYS_DIGFILT_gm Predefined. */ -/* EVSYS_DIGFILT_gp Predefined. */ -/* EVSYS_DIGFILT0_bm Predefined. */ -/* EVSYS_DIGFILT0_bp Predefined. */ -/* EVSYS_DIGFILT1_bm Predefined. */ -/* EVSYS_DIGFILT1_bp Predefined. */ -/* EVSYS_DIGFILT2_bm Predefined. */ -/* EVSYS_DIGFILT2_bp Predefined. */ - - -/* EVSYS.CH7CTRL bit masks and bit positions */ -/* EVSYS_DIGFILT_gm Predefined. */ -/* EVSYS_DIGFILT_gp Predefined. */ -/* EVSYS_DIGFILT0_bm Predefined. */ -/* EVSYS_DIGFILT0_bp Predefined. */ -/* EVSYS_DIGFILT1_bm Predefined. */ -/* EVSYS_DIGFILT1_bp Predefined. */ -/* EVSYS_DIGFILT2_bm Predefined. */ -/* EVSYS_DIGFILT2_bp Predefined. */ - - -/* NVM - Non Volatile Memory Controller */ -/* NVM.CMD bit masks and bit positions */ -#define NVM_CMD_gm 0xFF /* Command group mask. */ -#define NVM_CMD_gp 0 /* Command group position. */ -#define NVM_CMD0_bm (1<<0) /* Command bit 0 mask. */ -#define NVM_CMD0_bp 0 /* Command bit 0 position. */ -#define NVM_CMD1_bm (1<<1) /* Command bit 1 mask. */ -#define NVM_CMD1_bp 1 /* Command bit 1 position. */ -#define NVM_CMD2_bm (1<<2) /* Command bit 2 mask. */ -#define NVM_CMD2_bp 2 /* Command bit 2 position. */ -#define NVM_CMD3_bm (1<<3) /* Command bit 3 mask. */ -#define NVM_CMD3_bp 3 /* Command bit 3 position. */ -#define NVM_CMD4_bm (1<<4) /* Command bit 4 mask. */ -#define NVM_CMD4_bp 4 /* Command bit 4 position. */ -#define NVM_CMD5_bm (1<<5) /* Command bit 5 mask. */ -#define NVM_CMD5_bp 5 /* Command bit 5 position. */ -#define NVM_CMD6_bm (1<<6) /* Command bit 6 mask. */ -#define NVM_CMD6_bp 6 /* Command bit 6 position. */ -#define NVM_CMD7_bm (1<<7) /* Command bit 7 mask. */ -#define NVM_CMD7_bp 7 /* Command bit 7 position. */ - - -/* NVM.CTRLA bit masks and bit positions */ -#define NVM_CMDEX_bm 0x01 /* Command Execute bit mask. */ -#define NVM_CMDEX_bp 0 /* Command Execute bit position. */ - - -/* NVM.CTRLB bit masks and bit positions */ -#define NVM_EEMAPEN_bm 0x08 /* EEPROM Mapping Enable bit mask. */ -#define NVM_EEMAPEN_bp 3 /* EEPROM Mapping Enable bit position. */ - -#define NVM_FPRM_bm 0x04 /* Flash Power Reduction Enable bit mask. */ -#define NVM_FPRM_bp 2 /* Flash Power Reduction Enable bit position. */ - -#define NVM_EPRM_bm 0x02 /* EEPROM Power Reduction Enable bit mask. */ -#define NVM_EPRM_bp 1 /* EEPROM Power Reduction Enable bit position. */ - -#define NVM_SPMLOCK_bm 0x01 /* SPM Lock bit mask. */ -#define NVM_SPMLOCK_bp 0 /* SPM Lock bit position. */ - - -/* NVM.INTCTRL bit masks and bit positions */ -#define NVM_SPMLVL_gm 0x0C /* SPM Interrupt Level group mask. */ -#define NVM_SPMLVL_gp 2 /* SPM Interrupt Level group position. */ -#define NVM_SPMLVL0_bm (1<<2) /* SPM Interrupt Level bit 0 mask. */ -#define NVM_SPMLVL0_bp 2 /* SPM Interrupt Level bit 0 position. */ -#define NVM_SPMLVL1_bm (1<<3) /* SPM Interrupt Level bit 1 mask. */ -#define NVM_SPMLVL1_bp 3 /* SPM Interrupt Level bit 1 position. */ - -#define NVM_EELVL_gm 0x03 /* EEPROM Interrupt Level group mask. */ -#define NVM_EELVL_gp 0 /* EEPROM Interrupt Level group position. */ -#define NVM_EELVL0_bm (1<<0) /* EEPROM Interrupt Level bit 0 mask. */ -#define NVM_EELVL0_bp 0 /* EEPROM Interrupt Level bit 0 position. */ -#define NVM_EELVL1_bm (1<<1) /* EEPROM Interrupt Level bit 1 mask. */ -#define NVM_EELVL1_bp 1 /* EEPROM Interrupt Level bit 1 position. */ - - -/* NVM.STATUS bit masks and bit positions */ -#define NVM_NVMBUSY_bm 0x80 /* Non-volatile Memory Busy bit mask. */ -#define NVM_NVMBUSY_bp 7 /* Non-volatile Memory Busy bit position. */ - -#define NVM_FBUSY_bm 0x40 /* Flash Memory Busy bit mask. */ -#define NVM_FBUSY_bp 6 /* Flash Memory Busy bit position. */ - -#define NVM_EELOAD_bm 0x02 /* EEPROM Page Buffer Active Loading bit mask. */ -#define NVM_EELOAD_bp 1 /* EEPROM Page Buffer Active Loading bit position. */ - -#define NVM_FLOAD_bm 0x01 /* Flash Page Buffer Active Loading bit mask. */ -#define NVM_FLOAD_bp 0 /* Flash Page Buffer Active Loading bit position. */ - - -/* NVM.LOCKBITS bit masks and bit positions */ -#define NVM_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ -#define NVM_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ -#define NVM_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ -#define NVM_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ -#define NVM_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ -#define NVM_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ - -#define NVM_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ -#define NVM_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ -#define NVM_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ -#define NVM_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ -#define NVM_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ -#define NVM_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ - -#define NVM_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ -#define NVM_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ -#define NVM_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ -#define NVM_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ -#define NVM_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ -#define NVM_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ - -#define NVM_LB_gm 0x03 /* Lock Bits group mask. */ -#define NVM_LB_gp 0 /* Lock Bits group position. */ -#define NVM_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ -#define NVM_LB0_bp 0 /* Lock Bits bit 0 position. */ -#define NVM_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ -#define NVM_LB1_bp 1 /* Lock Bits bit 1 position. */ - - -/* NVM_LOCKBITS.LOCKBITS bit masks and bit positions */ -#define NVM_LOCKBITS_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ -#define NVM_LOCKBITS_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ -#define NVM_LOCKBITS_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ -#define NVM_LOCKBITS_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ -#define NVM_LOCKBITS_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ -#define NVM_LOCKBITS_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ - -#define NVM_LOCKBITS_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ -#define NVM_LOCKBITS_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ -#define NVM_LOCKBITS_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ -#define NVM_LOCKBITS_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ -#define NVM_LOCKBITS_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ -#define NVM_LOCKBITS_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ - -#define NVM_LOCKBITS_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ -#define NVM_LOCKBITS_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ -#define NVM_LOCKBITS_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ -#define NVM_LOCKBITS_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ -#define NVM_LOCKBITS_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ -#define NVM_LOCKBITS_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ - -#define NVM_LOCKBITS_LB_gm 0x03 /* Lock Bits group mask. */ -#define NVM_LOCKBITS_LB_gp 0 /* Lock Bits group position. */ -#define NVM_LOCKBITS_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ -#define NVM_LOCKBITS_LB0_bp 0 /* Lock Bits bit 0 position. */ -#define NVM_LOCKBITS_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ -#define NVM_LOCKBITS_LB1_bp 1 /* Lock Bits bit 1 position. */ - - -/* NVM_FUSES.FUSEBYTE0 bit masks and bit positions */ -#define NVM_FUSES_USERID_gm 0xFF /* User ID group mask. */ -#define NVM_FUSES_USERID_gp 0 /* User ID group position. */ -#define NVM_FUSES_USERID0_bm (1<<0) /* User ID bit 0 mask. */ -#define NVM_FUSES_USERID0_bp 0 /* User ID bit 0 position. */ -#define NVM_FUSES_USERID1_bm (1<<1) /* User ID bit 1 mask. */ -#define NVM_FUSES_USERID1_bp 1 /* User ID bit 1 position. */ -#define NVM_FUSES_USERID2_bm (1<<2) /* User ID bit 2 mask. */ -#define NVM_FUSES_USERID2_bp 2 /* User ID bit 2 position. */ -#define NVM_FUSES_USERID3_bm (1<<3) /* User ID bit 3 mask. */ -#define NVM_FUSES_USERID3_bp 3 /* User ID bit 3 position. */ -#define NVM_FUSES_USERID4_bm (1<<4) /* User ID bit 4 mask. */ -#define NVM_FUSES_USERID4_bp 4 /* User ID bit 4 position. */ -#define NVM_FUSES_USERID5_bm (1<<5) /* User ID bit 5 mask. */ -#define NVM_FUSES_USERID5_bp 5 /* User ID bit 5 position. */ -#define NVM_FUSES_USERID6_bm (1<<6) /* User ID bit 6 mask. */ -#define NVM_FUSES_USERID6_bp 6 /* User ID bit 6 position. */ -#define NVM_FUSES_USERID7_bm (1<<7) /* User ID bit 7 mask. */ -#define NVM_FUSES_USERID7_bp 7 /* User ID bit 7 position. */ - - -/* NVM_FUSES.FUSEBYTE1 bit masks and bit positions */ -#define NVM_FUSES_WDWP_gm 0xF0 /* Watchdog Window Timeout Period group mask. */ -#define NVM_FUSES_WDWP_gp 4 /* Watchdog Window Timeout Period group position. */ -#define NVM_FUSES_WDWP0_bm (1<<4) /* Watchdog Window Timeout Period bit 0 mask. */ -#define NVM_FUSES_WDWP0_bp 4 /* Watchdog Window Timeout Period bit 0 position. */ -#define NVM_FUSES_WDWP1_bm (1<<5) /* Watchdog Window Timeout Period bit 1 mask. */ -#define NVM_FUSES_WDWP1_bp 5 /* Watchdog Window Timeout Period bit 1 position. */ -#define NVM_FUSES_WDWP2_bm (1<<6) /* Watchdog Window Timeout Period bit 2 mask. */ -#define NVM_FUSES_WDWP2_bp 6 /* Watchdog Window Timeout Period bit 2 position. */ -#define NVM_FUSES_WDWP3_bm (1<<7) /* Watchdog Window Timeout Period bit 3 mask. */ -#define NVM_FUSES_WDWP3_bp 7 /* Watchdog Window Timeout Period bit 3 position. */ - -#define NVM_FUSES_WDP_gm 0x0F /* Watchdog Timeout Period group mask. */ -#define NVM_FUSES_WDP_gp 0 /* Watchdog Timeout Period group position. */ -#define NVM_FUSES_WDP0_bm (1<<0) /* Watchdog Timeout Period bit 0 mask. */ -#define NVM_FUSES_WDP0_bp 0 /* Watchdog Timeout Period bit 0 position. */ -#define NVM_FUSES_WDP1_bm (1<<1) /* Watchdog Timeout Period bit 1 mask. */ -#define NVM_FUSES_WDP1_bp 1 /* Watchdog Timeout Period bit 1 position. */ -#define NVM_FUSES_WDP2_bm (1<<2) /* Watchdog Timeout Period bit 2 mask. */ -#define NVM_FUSES_WDP2_bp 2 /* Watchdog Timeout Period bit 2 position. */ -#define NVM_FUSES_WDP3_bm (1<<3) /* Watchdog Timeout Period bit 3 mask. */ -#define NVM_FUSES_WDP3_bp 3 /* Watchdog Timeout Period bit 3 position. */ - - -/* NVM_FUSES.FUSEBYTE2 bit masks and bit positions */ -#define NVM_FUSES_DVSDON_bm 0x80 /* Spike Detector Enable bit mask. */ -#define NVM_FUSES_DVSDON_bp 7 /* Spike Detector Enable bit position. */ - -#define NVM_FUSES_BOOTRST_bm 0x40 /* Boot Loader Section Reset Vector bit mask. */ -#define NVM_FUSES_BOOTRST_bp 6 /* Boot Loader Section Reset Vector bit position. */ - -#define NVM_FUSES_BODPD_gm 0x03 /* BOD Operation in Power-Down Mode group mask. */ -#define NVM_FUSES_BODPD_gp 0 /* BOD Operation in Power-Down Mode group position. */ -#define NVM_FUSES_BODPD0_bm (1<<0) /* BOD Operation in Power-Down Mode bit 0 mask. */ -#define NVM_FUSES_BODPD0_bp 0 /* BOD Operation in Power-Down Mode bit 0 position. */ -#define NVM_FUSES_BODPD1_bm (1<<1) /* BOD Operation in Power-Down Mode bit 1 mask. */ -#define NVM_FUSES_BODPD1_bp 1 /* BOD Operation in Power-Down Mode bit 1 position. */ - - -/* NVM_FUSES.FUSEBYTE4 bit masks and bit positions */ -#define NVM_FUSES_SUT_gm 0x0C /* Start-up Time group mask. */ -#define NVM_FUSES_SUT_gp 2 /* Start-up Time group position. */ -#define NVM_FUSES_SUT0_bm (1<<2) /* Start-up Time bit 0 mask. */ -#define NVM_FUSES_SUT0_bp 2 /* Start-up Time bit 0 position. */ -#define NVM_FUSES_SUT1_bm (1<<3) /* Start-up Time bit 1 mask. */ -#define NVM_FUSES_SUT1_bp 3 /* Start-up Time bit 1 position. */ - -#define NVM_FUSES_WDLOCK_bm 0x02 /* Watchdog Timer Lock bit mask. */ -#define NVM_FUSES_WDLOCK_bp 1 /* Watchdog Timer Lock bit position. */ - - -/* NVM_FUSES.FUSEBYTE5 bit masks and bit positions */ -#define NVM_FUSES_BODACT_gm 0x30 /* BOD Operation in Active Mode group mask. */ -#define NVM_FUSES_BODACT_gp 4 /* BOD Operation in Active Mode group position. */ -#define NVM_FUSES_BODACT0_bm (1<<4) /* BOD Operation in Active Mode bit 0 mask. */ -#define NVM_FUSES_BODACT0_bp 4 /* BOD Operation in Active Mode bit 0 position. */ -#define NVM_FUSES_BODACT1_bm (1<<5) /* BOD Operation in Active Mode bit 1 mask. */ -#define NVM_FUSES_BODACT1_bp 5 /* BOD Operation in Active Mode bit 1 position. */ - -#define NVM_FUSES_EESAVE_bm 0x08 /* Preserve EEPROM Through Chip Erase bit mask. */ -#define NVM_FUSES_EESAVE_bp 3 /* Preserve EEPROM Through Chip Erase bit position. */ - -#define NVM_FUSES_BODLVL_gm 0x07 /* Brown Out Detection Voltage Level group mask. */ -#define NVM_FUSES_BODLVL_gp 0 /* Brown Out Detection Voltage Level group position. */ -#define NVM_FUSES_BODLVL0_bm (1<<0) /* Brown Out Detection Voltage Level bit 0 mask. */ -#define NVM_FUSES_BODLVL0_bp 0 /* Brown Out Detection Voltage Level bit 0 position. */ -#define NVM_FUSES_BODLVL1_bm (1<<1) /* Brown Out Detection Voltage Level bit 1 mask. */ -#define NVM_FUSES_BODLVL1_bp 1 /* Brown Out Detection Voltage Level bit 1 position. */ -#define NVM_FUSES_BODLVL2_bm (1<<2) /* Brown Out Detection Voltage Level bit 2 mask. */ -#define NVM_FUSES_BODLVL2_bp 2 /* Brown Out Detection Voltage Level bit 2 position. */ - - -/* AC - Analog Comparator */ -/* AC.AC0CTRL bit masks and bit positions */ -#define AC_INTMODE_gm 0xC0 /* Interrupt Mode group mask. */ -#define AC_INTMODE_gp 6 /* Interrupt Mode group position. */ -#define AC_INTMODE0_bm (1<<6) /* Interrupt Mode bit 0 mask. */ -#define AC_INTMODE0_bp 6 /* Interrupt Mode bit 0 position. */ -#define AC_INTMODE1_bm (1<<7) /* Interrupt Mode bit 1 mask. */ -#define AC_INTMODE1_bp 7 /* Interrupt Mode bit 1 position. */ - -#define AC_INTLVL_gm 0x30 /* Interrupt Level group mask. */ -#define AC_INTLVL_gp 4 /* Interrupt Level group position. */ -#define AC_INTLVL0_bm (1<<4) /* Interrupt Level bit 0 mask. */ -#define AC_INTLVL0_bp 4 /* Interrupt Level bit 0 position. */ -#define AC_INTLVL1_bm (1<<5) /* Interrupt Level bit 1 mask. */ -#define AC_INTLVL1_bp 5 /* Interrupt Level bit 1 position. */ - -#define AC_HSMODE_bm 0x08 /* High-speed Mode bit mask. */ -#define AC_HSMODE_bp 3 /* High-speed Mode bit position. */ - -#define AC_HYSMODE_gm 0x06 /* Hysteresis Mode group mask. */ -#define AC_HYSMODE_gp 1 /* Hysteresis Mode group position. */ -#define AC_HYSMODE0_bm (1<<1) /* Hysteresis Mode bit 0 mask. */ -#define AC_HYSMODE0_bp 1 /* Hysteresis Mode bit 0 position. */ -#define AC_HYSMODE1_bm (1<<2) /* Hysteresis Mode bit 1 mask. */ -#define AC_HYSMODE1_bp 2 /* Hysteresis Mode bit 1 position. */ - -#define AC_ENABLE_bm 0x01 /* Enable bit mask. */ -#define AC_ENABLE_bp 0 /* Enable bit position. */ - - -/* AC.AC1CTRL bit masks and bit positions */ -/* AC_INTMODE_gm Predefined. */ -/* AC_INTMODE_gp Predefined. */ -/* AC_INTMODE0_bm Predefined. */ -/* AC_INTMODE0_bp Predefined. */ -/* AC_INTMODE1_bm Predefined. */ -/* AC_INTMODE1_bp Predefined. */ - -/* AC_INTLVL_gm Predefined. */ -/* AC_INTLVL_gp Predefined. */ -/* AC_INTLVL0_bm Predefined. */ -/* AC_INTLVL0_bp Predefined. */ -/* AC_INTLVL1_bm Predefined. */ -/* AC_INTLVL1_bp Predefined. */ - -/* AC_HSMODE_bm Predefined. */ -/* AC_HSMODE_bp Predefined. */ - -/* AC_HYSMODE_gm Predefined. */ -/* AC_HYSMODE_gp Predefined. */ -/* AC_HYSMODE0_bm Predefined. */ -/* AC_HYSMODE0_bp Predefined. */ -/* AC_HYSMODE1_bm Predefined. */ -/* AC_HYSMODE1_bp Predefined. */ - -/* AC_ENABLE_bm Predefined. */ -/* AC_ENABLE_bp Predefined. */ - - -/* AC.AC0MUXCTRL bit masks and bit positions */ -#define AC_MUXPOS_gm 0x38 /* MUX Positive Input group mask. */ -#define AC_MUXPOS_gp 3 /* MUX Positive Input group position. */ -#define AC_MUXPOS0_bm (1<<3) /* MUX Positive Input bit 0 mask. */ -#define AC_MUXPOS0_bp 3 /* MUX Positive Input bit 0 position. */ -#define AC_MUXPOS1_bm (1<<4) /* MUX Positive Input bit 1 mask. */ -#define AC_MUXPOS1_bp 4 /* MUX Positive Input bit 1 position. */ -#define AC_MUXPOS2_bm (1<<5) /* MUX Positive Input bit 2 mask. */ -#define AC_MUXPOS2_bp 5 /* MUX Positive Input bit 2 position. */ - -#define AC_MUXNEG_gm 0x07 /* MUX Negative Input group mask. */ -#define AC_MUXNEG_gp 0 /* MUX Negative Input group position. */ -#define AC_MUXNEG0_bm (1<<0) /* MUX Negative Input bit 0 mask. */ -#define AC_MUXNEG0_bp 0 /* MUX Negative Input bit 0 position. */ -#define AC_MUXNEG1_bm (1<<1) /* MUX Negative Input bit 1 mask. */ -#define AC_MUXNEG1_bp 1 /* MUX Negative Input bit 1 position. */ -#define AC_MUXNEG2_bm (1<<2) /* MUX Negative Input bit 2 mask. */ -#define AC_MUXNEG2_bp 2 /* MUX Negative Input bit 2 position. */ - - -/* AC.AC1MUXCTRL bit masks and bit positions */ -/* AC_MUXPOS_gm Predefined. */ -/* AC_MUXPOS_gp Predefined. */ -/* AC_MUXPOS0_bm Predefined. */ -/* AC_MUXPOS0_bp Predefined. */ -/* AC_MUXPOS1_bm Predefined. */ -/* AC_MUXPOS1_bp Predefined. */ -/* AC_MUXPOS2_bm Predefined. */ -/* AC_MUXPOS2_bp Predefined. */ - -/* AC_MUXNEG_gm Predefined. */ -/* AC_MUXNEG_gp Predefined. */ -/* AC_MUXNEG0_bm Predefined. */ -/* AC_MUXNEG0_bp Predefined. */ -/* AC_MUXNEG1_bm Predefined. */ -/* AC_MUXNEG1_bp Predefined. */ -/* AC_MUXNEG2_bm Predefined. */ -/* AC_MUXNEG2_bp Predefined. */ - - -/* AC.CTRLA bit masks and bit positions */ -#define AC_AC0OUT_bm 0x01 /* Comparator 0 Output Enable bit mask. */ -#define AC_AC0OUT_bp 0 /* Comparator 0 Output Enable bit position. */ - - -/* AC.CTRLB bit masks and bit positions */ -#define AC_SCALEFAC_gm 0x3F /* VCC Voltage Scaler Factor group mask. */ -#define AC_SCALEFAC_gp 0 /* VCC Voltage Scaler Factor group position. */ -#define AC_SCALEFAC0_bm (1<<0) /* VCC Voltage Scaler Factor bit 0 mask. */ -#define AC_SCALEFAC0_bp 0 /* VCC Voltage Scaler Factor bit 0 position. */ -#define AC_SCALEFAC1_bm (1<<1) /* VCC Voltage Scaler Factor bit 1 mask. */ -#define AC_SCALEFAC1_bp 1 /* VCC Voltage Scaler Factor bit 1 position. */ -#define AC_SCALEFAC2_bm (1<<2) /* VCC Voltage Scaler Factor bit 2 mask. */ -#define AC_SCALEFAC2_bp 2 /* VCC Voltage Scaler Factor bit 2 position. */ -#define AC_SCALEFAC3_bm (1<<3) /* VCC Voltage Scaler Factor bit 3 mask. */ -#define AC_SCALEFAC3_bp 3 /* VCC Voltage Scaler Factor bit 3 position. */ -#define AC_SCALEFAC4_bm (1<<4) /* VCC Voltage Scaler Factor bit 4 mask. */ -#define AC_SCALEFAC4_bp 4 /* VCC Voltage Scaler Factor bit 4 position. */ -#define AC_SCALEFAC5_bm (1<<5) /* VCC Voltage Scaler Factor bit 5 mask. */ -#define AC_SCALEFAC5_bp 5 /* VCC Voltage Scaler Factor bit 5 position. */ - - -/* AC.WINCTRL bit masks and bit positions */ -#define AC_WEN_bm 0x10 /* Window Mode Enable bit mask. */ -#define AC_WEN_bp 4 /* Window Mode Enable bit position. */ - -#define AC_WINTMODE_gm 0x0C /* Window Interrupt Mode group mask. */ -#define AC_WINTMODE_gp 2 /* Window Interrupt Mode group position. */ -#define AC_WINTMODE0_bm (1<<2) /* Window Interrupt Mode bit 0 mask. */ -#define AC_WINTMODE0_bp 2 /* Window Interrupt Mode bit 0 position. */ -#define AC_WINTMODE1_bm (1<<3) /* Window Interrupt Mode bit 1 mask. */ -#define AC_WINTMODE1_bp 3 /* Window Interrupt Mode bit 1 position. */ - -#define AC_WINTLVL_gm 0x03 /* Window Interrupt Level group mask. */ -#define AC_WINTLVL_gp 0 /* Window Interrupt Level group position. */ -#define AC_WINTLVL0_bm (1<<0) /* Window Interrupt Level bit 0 mask. */ -#define AC_WINTLVL0_bp 0 /* Window Interrupt Level bit 0 position. */ -#define AC_WINTLVL1_bm (1<<1) /* Window Interrupt Level bit 1 mask. */ -#define AC_WINTLVL1_bp 1 /* Window Interrupt Level bit 1 position. */ - - -/* AC.STATUS bit masks and bit positions */ -#define AC_WSTATE_gm 0xC0 /* Window Mode State group mask. */ -#define AC_WSTATE_gp 6 /* Window Mode State group position. */ -#define AC_WSTATE0_bm (1<<6) /* Window Mode State bit 0 mask. */ -#define AC_WSTATE0_bp 6 /* Window Mode State bit 0 position. */ -#define AC_WSTATE1_bm (1<<7) /* Window Mode State bit 1 mask. */ -#define AC_WSTATE1_bp 7 /* Window Mode State bit 1 position. */ - -#define AC_AC1STATE_bm 0x20 /* Comparator 1 State bit mask. */ -#define AC_AC1STATE_bp 5 /* Comparator 1 State bit position. */ - -#define AC_AC0STATE_bm 0x10 /* Comparator 0 State bit mask. */ -#define AC_AC0STATE_bp 4 /* Comparator 0 State bit position. */ - -#define AC_WIF_bm 0x04 /* Window Mode Interrupt Flag bit mask. */ -#define AC_WIF_bp 2 /* Window Mode Interrupt Flag bit position. */ - -#define AC_AC1IF_bm 0x02 /* Comparator 1 Interrupt Flag bit mask. */ -#define AC_AC1IF_bp 1 /* Comparator 1 Interrupt Flag bit position. */ - -#define AC_AC0IF_bm 0x01 /* Comparator 0 Interrupt Flag bit mask. */ -#define AC_AC0IF_bp 0 /* Comparator 0 Interrupt Flag bit position. */ - - -/* ADC - Analog/Digital Converter */ -/* ADC_CH.CTRL bit masks and bit positions */ -#define ADC_CH_START_bm 0x80 /* Channel Start Conversion bit mask. */ -#define ADC_CH_START_bp 7 /* Channel Start Conversion bit position. */ - -#define ADC_CH_GAINFAC_gm 0x1C /* Gain Factor group mask. */ -#define ADC_CH_GAINFAC_gp 2 /* Gain Factor group position. */ -#define ADC_CH_GAINFAC0_bm (1<<2) /* Gain Factor bit 0 mask. */ -#define ADC_CH_GAINFAC0_bp 2 /* Gain Factor bit 0 position. */ -#define ADC_CH_GAINFAC1_bm (1<<3) /* Gain Factor bit 1 mask. */ -#define ADC_CH_GAINFAC1_bp 3 /* Gain Factor bit 1 position. */ -#define ADC_CH_GAINFAC2_bm (1<<4) /* Gain Factor bit 2 mask. */ -#define ADC_CH_GAINFAC2_bp 4 /* Gain Factor bit 2 position. */ - -#define ADC_CH_INPUTMODE_gm 0x03 /* Input Mode Select group mask. */ -#define ADC_CH_INPUTMODE_gp 0 /* Input Mode Select group position. */ -#define ADC_CH_INPUTMODE0_bm (1<<0) /* Input Mode Select bit 0 mask. */ -#define ADC_CH_INPUTMODE0_bp 0 /* Input Mode Select bit 0 position. */ -#define ADC_CH_INPUTMODE1_bm (1<<1) /* Input Mode Select bit 1 mask. */ -#define ADC_CH_INPUTMODE1_bp 1 /* Input Mode Select bit 1 position. */ - - -/* ADC_CH.MUXCTRL bit masks and bit positions */ -#define ADC_CH_MUXPOS_gm 0x78 /* Positive Input Select group mask. */ -#define ADC_CH_MUXPOS_gp 3 /* Positive Input Select group position. */ -#define ADC_CH_MUXPOS0_bm (1<<3) /* Positive Input Select bit 0 mask. */ -#define ADC_CH_MUXPOS0_bp 3 /* Positive Input Select bit 0 position. */ -#define ADC_CH_MUXPOS1_bm (1<<4) /* Positive Input Select bit 1 mask. */ -#define ADC_CH_MUXPOS1_bp 4 /* Positive Input Select bit 1 position. */ -#define ADC_CH_MUXPOS2_bm (1<<5) /* Positive Input Select bit 2 mask. */ -#define ADC_CH_MUXPOS2_bp 5 /* Positive Input Select bit 2 position. */ -#define ADC_CH_MUXPOS3_bm (1<<6) /* Positive Input Select bit 3 mask. */ -#define ADC_CH_MUXPOS3_bp 6 /* Positive Input Select bit 3 position. */ - -#define ADC_CH_MUXINT_gm 0x78 /* Internal Input Select group mask. */ -#define ADC_CH_MUXINT_gp 3 /* Internal Input Select group position. */ -#define ADC_CH_MUXINT0_bm (1<<3) /* Internal Input Select bit 0 mask. */ -#define ADC_CH_MUXINT0_bp 3 /* Internal Input Select bit 0 position. */ -#define ADC_CH_MUXINT1_bm (1<<4) /* Internal Input Select bit 1 mask. */ -#define ADC_CH_MUXINT1_bp 4 /* Internal Input Select bit 1 position. */ -#define ADC_CH_MUXINT2_bm (1<<5) /* Internal Input Select bit 2 mask. */ -#define ADC_CH_MUXINT2_bp 5 /* Internal Input Select bit 2 position. */ -#define ADC_CH_MUXINT3_bm (1<<6) /* Internal Input Select bit 3 mask. */ -#define ADC_CH_MUXINT3_bp 6 /* Internal Input Select bit 3 position. */ - -#define ADC_CH_MUXNEG_gm 0x03 /* Negative Input Select group mask. */ -#define ADC_CH_MUXNEG_gp 0 /* Negative Input Select group position. */ -#define ADC_CH_MUXNEG0_bm (1<<0) /* Negative Input Select bit 0 mask. */ -#define ADC_CH_MUXNEG0_bp 0 /* Negative Input Select bit 0 position. */ -#define ADC_CH_MUXNEG1_bm (1<<1) /* Negative Input Select bit 1 mask. */ -#define ADC_CH_MUXNEG1_bp 1 /* Negative Input Select bit 1 position. */ - - -/* ADC_CH.INTCTRL bit masks and bit positions */ -#define ADC_CH_INTMODE_gm 0x0C /* Interrupt Mode group mask. */ -#define ADC_CH_INTMODE_gp 2 /* Interrupt Mode group position. */ -#define ADC_CH_INTMODE0_bm (1<<2) /* Interrupt Mode bit 0 mask. */ -#define ADC_CH_INTMODE0_bp 2 /* Interrupt Mode bit 0 position. */ -#define ADC_CH_INTMODE1_bm (1<<3) /* Interrupt Mode bit 1 mask. */ -#define ADC_CH_INTMODE1_bp 3 /* Interrupt Mode bit 1 position. */ - -#define ADC_CH_INTLVL_gm 0x03 /* Interrupt Level group mask. */ -#define ADC_CH_INTLVL_gp 0 /* Interrupt Level group position. */ -#define ADC_CH_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */ -#define ADC_CH_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */ -#define ADC_CH_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ -#define ADC_CH_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */ - - -/* ADC_CH.INTFLAGS bit masks and bit positions */ -#define ADC_CH_CHIF_bm 0x01 /* Channel Interrupt Flag bit mask. */ -#define ADC_CH_CHIF_bp 0 /* Channel Interrupt Flag bit position. */ - - -/* ADC.CTRLA bit masks and bit positions */ -#define ADC_DMASEL_gm 0xC0 /* DMA Selection group mask. */ -#define ADC_DMASEL_gp 6 /* DMA Selection group position. */ -#define ADC_DMASEL0_bm (1<<6) /* DMA Selection bit 0 mask. */ -#define ADC_DMASEL0_bp 6 /* DMA Selection bit 0 position. */ -#define ADC_DMASEL1_bm (1<<7) /* DMA Selection bit 1 mask. */ -#define ADC_DMASEL1_bp 7 /* DMA Selection bit 1 position. */ - -#define ADC_CH3START_bm 0x20 /* Channel 3 Start Conversion bit mask. */ -#define ADC_CH3START_bp 5 /* Channel 3 Start Conversion bit position. */ - -#define ADC_CH2START_bm 0x10 /* Channel 2 Start Conversion bit mask. */ -#define ADC_CH2START_bp 4 /* Channel 2 Start Conversion bit position. */ - -#define ADC_CH1START_bm 0x08 /* Channel 1 Start Conversion bit mask. */ -#define ADC_CH1START_bp 3 /* Channel 1 Start Conversion bit position. */ - -#define ADC_CH0START_bm 0x04 /* Channel 0 Start Conversion bit mask. */ -#define ADC_CH0START_bp 2 /* Channel 0 Start Conversion bit position. */ - -#define ADC_FLUSH_bm 0x02 /* Flush Pipeline bit mask. */ -#define ADC_FLUSH_bp 1 /* Flush Pipeline bit position. */ - -#define ADC_ENABLE_bm 0x01 /* Enable ADC bit mask. */ -#define ADC_ENABLE_bp 0 /* Enable ADC bit position. */ - - -/* ADC.CTRLB bit masks and bit positions */ -#define ADC_CONMODE_bm 0x10 /* Conversion Mode bit mask. */ -#define ADC_CONMODE_bp 4 /* Conversion Mode bit position. */ - -#define ADC_FREERUN_bm 0x08 /* Free Running Mode Enable bit mask. */ -#define ADC_FREERUN_bp 3 /* Free Running Mode Enable bit position. */ - -#define ADC_RESOLUTION_gm 0x06 /* Result Resolution group mask. */ -#define ADC_RESOLUTION_gp 1 /* Result Resolution group position. */ -#define ADC_RESOLUTION0_bm (1<<1) /* Result Resolution bit 0 mask. */ -#define ADC_RESOLUTION0_bp 1 /* Result Resolution bit 0 position. */ -#define ADC_RESOLUTION1_bm (1<<2) /* Result Resolution bit 1 mask. */ -#define ADC_RESOLUTION1_bp 2 /* Result Resolution bit 1 position. */ - - -/* ADC.REFCTRL bit masks and bit positions */ -#define ADC_REFSEL_gm 0x30 /* Reference Selection group mask. */ -#define ADC_REFSEL_gp 4 /* Reference Selection group position. */ -#define ADC_REFSEL0_bm (1<<4) /* Reference Selection bit 0 mask. */ -#define ADC_REFSEL0_bp 4 /* Reference Selection bit 0 position. */ -#define ADC_REFSEL1_bm (1<<5) /* Reference Selection bit 1 mask. */ -#define ADC_REFSEL1_bp 5 /* Reference Selection bit 1 position. */ - -#define ADC_BANDGAP_bm 0x02 /* Bandgap enable bit mask. */ -#define ADC_BANDGAP_bp 1 /* Bandgap enable bit position. */ - -#define ADC_TEMPREF_bm 0x01 /* Temperature Reference Enable bit mask. */ -#define ADC_TEMPREF_bp 0 /* Temperature Reference Enable bit position. */ - - -/* ADC.EVCTRL bit masks and bit positions */ -#define ADC_SWEEP_gm 0xC0 /* Channel Sweep Selection group mask. */ -#define ADC_SWEEP_gp 6 /* Channel Sweep Selection group position. */ -#define ADC_SWEEP0_bm (1<<6) /* Channel Sweep Selection bit 0 mask. */ -#define ADC_SWEEP0_bp 6 /* Channel Sweep Selection bit 0 position. */ -#define ADC_SWEEP1_bm (1<<7) /* Channel Sweep Selection bit 1 mask. */ -#define ADC_SWEEP1_bp 7 /* Channel Sweep Selection bit 1 position. */ - -#define ADC_EVSEL_gm 0x38 /* Event Input Select group mask. */ -#define ADC_EVSEL_gp 3 /* Event Input Select group position. */ -#define ADC_EVSEL0_bm (1<<3) /* Event Input Select bit 0 mask. */ -#define ADC_EVSEL0_bp 3 /* Event Input Select bit 0 position. */ -#define ADC_EVSEL1_bm (1<<4) /* Event Input Select bit 1 mask. */ -#define ADC_EVSEL1_bp 4 /* Event Input Select bit 1 position. */ -#define ADC_EVSEL2_bm (1<<5) /* Event Input Select bit 2 mask. */ -#define ADC_EVSEL2_bp 5 /* Event Input Select bit 2 position. */ - -#define ADC_EVACT_gm 0x07 /* Event Action Select group mask. */ -#define ADC_EVACT_gp 0 /* Event Action Select group position. */ -#define ADC_EVACT0_bm (1<<0) /* Event Action Select bit 0 mask. */ -#define ADC_EVACT0_bp 0 /* Event Action Select bit 0 position. */ -#define ADC_EVACT1_bm (1<<1) /* Event Action Select bit 1 mask. */ -#define ADC_EVACT1_bp 1 /* Event Action Select bit 1 position. */ -#define ADC_EVACT2_bm (1<<2) /* Event Action Select bit 2 mask. */ -#define ADC_EVACT2_bp 2 /* Event Action Select bit 2 position. */ - - -/* ADC.PRESCALER bit masks and bit positions */ -#define ADC_PRESCALER_gm 0x07 /* Clock Prescaler Selection group mask. */ -#define ADC_PRESCALER_gp 0 /* Clock Prescaler Selection group position. */ -#define ADC_PRESCALER0_bm (1<<0) /* Clock Prescaler Selection bit 0 mask. */ -#define ADC_PRESCALER0_bp 0 /* Clock Prescaler Selection bit 0 position. */ -#define ADC_PRESCALER1_bm (1<<1) /* Clock Prescaler Selection bit 1 mask. */ -#define ADC_PRESCALER1_bp 1 /* Clock Prescaler Selection bit 1 position. */ -#define ADC_PRESCALER2_bm (1<<2) /* Clock Prescaler Selection bit 2 mask. */ -#define ADC_PRESCALER2_bp 2 /* Clock Prescaler Selection bit 2 position. */ - - -/* ADC.INTFLAGS bit masks and bit positions */ -#define ADC_CH3IF_bm 0x08 /* Channel 3 Interrupt Flag bit mask. */ -#define ADC_CH3IF_bp 3 /* Channel 3 Interrupt Flag bit position. */ - -#define ADC_CH2IF_bm 0x04 /* Channel 2 Interrupt Flag bit mask. */ -#define ADC_CH2IF_bp 2 /* Channel 2 Interrupt Flag bit position. */ - -#define ADC_CH1IF_bm 0x02 /* Channel 1 Interrupt Flag bit mask. */ -#define ADC_CH1IF_bp 1 /* Channel 1 Interrupt Flag bit position. */ - -#define ADC_CH0IF_bm 0x01 /* Channel 0 Interrupt Flag bit mask. */ -#define ADC_CH0IF_bp 0 /* Channel 0 Interrupt Flag bit position. */ - - -/* DAC - Digital/Analog Converter */ -/* DAC.CTRLA bit masks and bit positions */ -#define DAC_IDOEN_bm 0x10 /* Internal Output Enable bit mask. */ -#define DAC_IDOEN_bp 4 /* Internal Output Enable bit position. */ - -#define DAC_CH1EN_bm 0x08 /* Channel 1 Output Enable bit mask. */ -#define DAC_CH1EN_bp 3 /* Channel 1 Output Enable bit position. */ - -#define DAC_CH0EN_bm 0x04 /* Channel 0 Output Enable bit mask. */ -#define DAC_CH0EN_bp 2 /* Channel 0 Output Enable bit position. */ - -#define DAC_LPMODE_bm 0x02 /* Low Power Mode bit mask. */ -#define DAC_LPMODE_bp 1 /* Low Power Mode bit position. */ - -#define DAC_ENABLE_bm 0x01 /* Enable bit mask. */ -#define DAC_ENABLE_bp 0 /* Enable bit position. */ - - -/* DAC.CTRLB bit masks and bit positions */ -#define DAC_CHSEL_gm 0x60 /* Channel Select group mask. */ -#define DAC_CHSEL_gp 5 /* Channel Select group position. */ -#define DAC_CHSEL0_bm (1<<5) /* Channel Select bit 0 mask. */ -#define DAC_CHSEL0_bp 5 /* Channel Select bit 0 position. */ -#define DAC_CHSEL1_bm (1<<6) /* Channel Select bit 1 mask. */ -#define DAC_CHSEL1_bp 6 /* Channel Select bit 1 position. */ - -#define DAC_CH1TRIG_bm 0x02 /* Channel 1 Event Trig Enable bit mask. */ -#define DAC_CH1TRIG_bp 1 /* Channel 1 Event Trig Enable bit position. */ - -#define DAC_CH0TRIG_bm 0x01 /* Channel 0 Event Trig Enable bit mask. */ -#define DAC_CH0TRIG_bp 0 /* Channel 0 Event Trig Enable bit position. */ - - -/* DAC.CTRLC bit masks and bit positions */ -#define DAC_REFSEL_gm 0x18 /* Reference Select group mask. */ -#define DAC_REFSEL_gp 3 /* Reference Select group position. */ -#define DAC_REFSEL0_bm (1<<3) /* Reference Select bit 0 mask. */ -#define DAC_REFSEL0_bp 3 /* Reference Select bit 0 position. */ -#define DAC_REFSEL1_bm (1<<4) /* Reference Select bit 1 mask. */ -#define DAC_REFSEL1_bp 4 /* Reference Select bit 1 position. */ - -#define DAC_LEFTADJ_bm 0x01 /* Left-adjust Result bit mask. */ -#define DAC_LEFTADJ_bp 0 /* Left-adjust Result bit position. */ - - -/* DAC.EVCTRL bit masks and bit positions */ -#define DAC_EVSEL_gm 0x07 /* Event Input Selection group mask. */ -#define DAC_EVSEL_gp 0 /* Event Input Selection group position. */ -#define DAC_EVSEL0_bm (1<<0) /* Event Input Selection bit 0 mask. */ -#define DAC_EVSEL0_bp 0 /* Event Input Selection bit 0 position. */ -#define DAC_EVSEL1_bm (1<<1) /* Event Input Selection bit 1 mask. */ -#define DAC_EVSEL1_bp 1 /* Event Input Selection bit 1 position. */ -#define DAC_EVSEL2_bm (1<<2) /* Event Input Selection bit 2 mask. */ -#define DAC_EVSEL2_bp 2 /* Event Input Selection bit 2 position. */ - - -/* DAC.TIMCTRL bit masks and bit positions */ -#define DAC_CONINTVAL_gm 0x70 /* Conversion Intercal group mask. */ -#define DAC_CONINTVAL_gp 4 /* Conversion Intercal group position. */ -#define DAC_CONINTVAL0_bm (1<<4) /* Conversion Intercal bit 0 mask. */ -#define DAC_CONINTVAL0_bp 4 /* Conversion Intercal bit 0 position. */ -#define DAC_CONINTVAL1_bm (1<<5) /* Conversion Intercal bit 1 mask. */ -#define DAC_CONINTVAL1_bp 5 /* Conversion Intercal bit 1 position. */ -#define DAC_CONINTVAL2_bm (1<<6) /* Conversion Intercal bit 2 mask. */ -#define DAC_CONINTVAL2_bp 6 /* Conversion Intercal bit 2 position. */ - -#define DAC_REFRESH_gm 0x0F /* Refresh Timing Control group mask. */ -#define DAC_REFRESH_gp 0 /* Refresh Timing Control group position. */ -#define DAC_REFRESH0_bm (1<<0) /* Refresh Timing Control bit 0 mask. */ -#define DAC_REFRESH0_bp 0 /* Refresh Timing Control bit 0 position. */ -#define DAC_REFRESH1_bm (1<<1) /* Refresh Timing Control bit 1 mask. */ -#define DAC_REFRESH1_bp 1 /* Refresh Timing Control bit 1 position. */ -#define DAC_REFRESH2_bm (1<<2) /* Refresh Timing Control bit 2 mask. */ -#define DAC_REFRESH2_bp 2 /* Refresh Timing Control bit 2 position. */ -#define DAC_REFRESH3_bm (1<<3) /* Refresh Timing Control bit 3 mask. */ -#define DAC_REFRESH3_bp 3 /* Refresh Timing Control bit 3 position. */ - - -/* DAC.STATUS bit masks and bit positions */ -#define DAC_CH1DRE_bm 0x02 /* Channel 1 Data Register Empty bit mask. */ -#define DAC_CH1DRE_bp 1 /* Channel 1 Data Register Empty bit position. */ - -#define DAC_CH0DRE_bm 0x01 /* Channel 0 Data Register Empty bit mask. */ -#define DAC_CH0DRE_bp 0 /* Channel 0 Data Register Empty bit position. */ - - -/* RTC - Real-Time Clounter */ -/* RTC.CTRL bit masks and bit positions */ -#define RTC_PRESCALER_gm 0x07 /* Prescaling Factor group mask. */ -#define RTC_PRESCALER_gp 0 /* Prescaling Factor group position. */ -#define RTC_PRESCALER0_bm (1<<0) /* Prescaling Factor bit 0 mask. */ -#define RTC_PRESCALER0_bp 0 /* Prescaling Factor bit 0 position. */ -#define RTC_PRESCALER1_bm (1<<1) /* Prescaling Factor bit 1 mask. */ -#define RTC_PRESCALER1_bp 1 /* Prescaling Factor bit 1 position. */ -#define RTC_PRESCALER2_bm (1<<2) /* Prescaling Factor bit 2 mask. */ -#define RTC_PRESCALER2_bp 2 /* Prescaling Factor bit 2 position. */ - - -/* RTC.STATUS bit masks and bit positions */ -#define RTC_SYNCBUSY_bm 0x01 /* Synchronization Busy Flag bit mask. */ -#define RTC_SYNCBUSY_bp 0 /* Synchronization Busy Flag bit position. */ - - -/* RTC.INTCTRL bit masks and bit positions */ -#define RTC_COMPINTLVL_gm 0x0C /* Compare Match Interrupt Level group mask. */ -#define RTC_COMPINTLVL_gp 2 /* Compare Match Interrupt Level group position. */ -#define RTC_COMPINTLVL0_bm (1<<2) /* Compare Match Interrupt Level bit 0 mask. */ -#define RTC_COMPINTLVL0_bp 2 /* Compare Match Interrupt Level bit 0 position. */ -#define RTC_COMPINTLVL1_bm (1<<3) /* Compare Match Interrupt Level bit 1 mask. */ -#define RTC_COMPINTLVL1_bp 3 /* Compare Match Interrupt Level bit 1 position. */ - -#define RTC_OVFINTLVL_gm 0x03 /* Overflow Interrupt Level group mask. */ -#define RTC_OVFINTLVL_gp 0 /* Overflow Interrupt Level group position. */ -#define RTC_OVFINTLVL0_bm (1<<0) /* Overflow Interrupt Level bit 0 mask. */ -#define RTC_OVFINTLVL0_bp 0 /* Overflow Interrupt Level bit 0 position. */ -#define RTC_OVFINTLVL1_bm (1<<1) /* Overflow Interrupt Level bit 1 mask. */ -#define RTC_OVFINTLVL1_bp 1 /* Overflow Interrupt Level bit 1 position. */ - - -/* RTC.INTFLAGS bit masks and bit positions */ -#define RTC_COMPIF_bm 0x02 /* Compare Match Interrupt Flag bit mask. */ -#define RTC_COMPIF_bp 1 /* Compare Match Interrupt Flag bit position. */ - -#define RTC_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ -#define RTC_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ - - -/* EBI - External Bus Interface */ -/* EBI_CS.CTRLA bit masks and bit positions */ -#define EBI_CS_ASIZE_gm 0x7C /* Address Size group mask. */ -#define EBI_CS_ASIZE_gp 2 /* Address Size group position. */ -#define EBI_CS_ASIZE0_bm (1<<2) /* Address Size bit 0 mask. */ -#define EBI_CS_ASIZE0_bp 2 /* Address Size bit 0 position. */ -#define EBI_CS_ASIZE1_bm (1<<3) /* Address Size bit 1 mask. */ -#define EBI_CS_ASIZE1_bp 3 /* Address Size bit 1 position. */ -#define EBI_CS_ASIZE2_bm (1<<4) /* Address Size bit 2 mask. */ -#define EBI_CS_ASIZE2_bp 4 /* Address Size bit 2 position. */ -#define EBI_CS_ASIZE3_bm (1<<5) /* Address Size bit 3 mask. */ -#define EBI_CS_ASIZE3_bp 5 /* Address Size bit 3 position. */ -#define EBI_CS_ASIZE4_bm (1<<6) /* Address Size bit 4 mask. */ -#define EBI_CS_ASIZE4_bp 6 /* Address Size bit 4 position. */ - -#define EBI_CS_MODE_gm 0x03 /* Memory Mode group mask. */ -#define EBI_CS_MODE_gp 0 /* Memory Mode group position. */ -#define EBI_CS_MODE0_bm (1<<0) /* Memory Mode bit 0 mask. */ -#define EBI_CS_MODE0_bp 0 /* Memory Mode bit 0 position. */ -#define EBI_CS_MODE1_bm (1<<1) /* Memory Mode bit 1 mask. */ -#define EBI_CS_MODE1_bp 1 /* Memory Mode bit 1 position. */ - - -/* EBI_CS.CTRLB bit masks and bit positions */ -#define EBI_CS_SRWS_gm 0x07 /* SRAM Wait State Cycles group mask. */ -#define EBI_CS_SRWS_gp 0 /* SRAM Wait State Cycles group position. */ -#define EBI_CS_SRWS0_bm (1<<0) /* SRAM Wait State Cycles bit 0 mask. */ -#define EBI_CS_SRWS0_bp 0 /* SRAM Wait State Cycles bit 0 position. */ -#define EBI_CS_SRWS1_bm (1<<1) /* SRAM Wait State Cycles bit 1 mask. */ -#define EBI_CS_SRWS1_bp 1 /* SRAM Wait State Cycles bit 1 position. */ -#define EBI_CS_SRWS2_bm (1<<2) /* SRAM Wait State Cycles bit 2 mask. */ -#define EBI_CS_SRWS2_bp 2 /* SRAM Wait State Cycles bit 2 position. */ - -#define EBI_CS_SDINITDONE_bm 0x80 /* SDRAM Initialization Done bit mask. */ -#define EBI_CS_SDINITDONE_bp 7 /* SDRAM Initialization Done bit position. */ - -#define EBI_CS_SDSREN_bm 0x04 /* SDRAM Self-refresh Enable bit mask. */ -#define EBI_CS_SDSREN_bp 2 /* SDRAM Self-refresh Enable bit position. */ - -#define EBI_CS_SDMODE_gm 0x03 /* SDRAM Mode group mask. */ -#define EBI_CS_SDMODE_gp 0 /* SDRAM Mode group position. */ -#define EBI_CS_SDMODE0_bm (1<<0) /* SDRAM Mode bit 0 mask. */ -#define EBI_CS_SDMODE0_bp 0 /* SDRAM Mode bit 0 position. */ -#define EBI_CS_SDMODE1_bm (1<<1) /* SDRAM Mode bit 1 mask. */ -#define EBI_CS_SDMODE1_bp 1 /* SDRAM Mode bit 1 position. */ - - -/* EBI.CTRL bit masks and bit positions */ -#define EBI_SDDATAW_gm 0xC0 /* SDRAM Data Width Setting group mask. */ -#define EBI_SDDATAW_gp 6 /* SDRAM Data Width Setting group position. */ -#define EBI_SDDATAW0_bm (1<<6) /* SDRAM Data Width Setting bit 0 mask. */ -#define EBI_SDDATAW0_bp 6 /* SDRAM Data Width Setting bit 0 position. */ -#define EBI_SDDATAW1_bm (1<<7) /* SDRAM Data Width Setting bit 1 mask. */ -#define EBI_SDDATAW1_bp 7 /* SDRAM Data Width Setting bit 1 position. */ - -#define EBI_LPCMODE_gm 0x30 /* SRAM LPC Mode group mask. */ -#define EBI_LPCMODE_gp 4 /* SRAM LPC Mode group position. */ -#define EBI_LPCMODE0_bm (1<<4) /* SRAM LPC Mode bit 0 mask. */ -#define EBI_LPCMODE0_bp 4 /* SRAM LPC Mode bit 0 position. */ -#define EBI_LPCMODE1_bm (1<<5) /* SRAM LPC Mode bit 1 mask. */ -#define EBI_LPCMODE1_bp 5 /* SRAM LPC Mode bit 1 position. */ - -#define EBI_SRMODE_gm 0x0C /* SRAM Mode group mask. */ -#define EBI_SRMODE_gp 2 /* SRAM Mode group position. */ -#define EBI_SRMODE0_bm (1<<2) /* SRAM Mode bit 0 mask. */ -#define EBI_SRMODE0_bp 2 /* SRAM Mode bit 0 position. */ -#define EBI_SRMODE1_bm (1<<3) /* SRAM Mode bit 1 mask. */ -#define EBI_SRMODE1_bp 3 /* SRAM Mode bit 1 position. */ - -#define EBI_IFMODE_gm 0x03 /* Interface Mode group mask. */ -#define EBI_IFMODE_gp 0 /* Interface Mode group position. */ -#define EBI_IFMODE0_bm (1<<0) /* Interface Mode bit 0 mask. */ -#define EBI_IFMODE0_bp 0 /* Interface Mode bit 0 position. */ -#define EBI_IFMODE1_bm (1<<1) /* Interface Mode bit 1 mask. */ -#define EBI_IFMODE1_bp 1 /* Interface Mode bit 1 position. */ - - -/* EBI.SDRAMCTRLA bit masks and bit positions */ -#define EBI_SDCAS_bm 0x08 /* SDRAM CAS Latency Setting bit mask. */ -#define EBI_SDCAS_bp 3 /* SDRAM CAS Latency Setting bit position. */ - -#define EBI_SDROW_bm 0x04 /* SDRAM ROW Bits Setting bit mask. */ -#define EBI_SDROW_bp 2 /* SDRAM ROW Bits Setting bit position. */ - -#define EBI_SDCOL_gm 0x03 /* SDRAM Column Bits Setting group mask. */ -#define EBI_SDCOL_gp 0 /* SDRAM Column Bits Setting group position. */ -#define EBI_SDCOL0_bm (1<<0) /* SDRAM Column Bits Setting bit 0 mask. */ -#define EBI_SDCOL0_bp 0 /* SDRAM Column Bits Setting bit 0 position. */ -#define EBI_SDCOL1_bm (1<<1) /* SDRAM Column Bits Setting bit 1 mask. */ -#define EBI_SDCOL1_bp 1 /* SDRAM Column Bits Setting bit 1 position. */ - - -/* EBI.SDRAMCTRLB bit masks and bit positions */ -#define EBI_MRDLY_gm 0xC0 /* SDRAM Mode Register Delay group mask. */ -#define EBI_MRDLY_gp 6 /* SDRAM Mode Register Delay group position. */ -#define EBI_MRDLY0_bm (1<<6) /* SDRAM Mode Register Delay bit 0 mask. */ -#define EBI_MRDLY0_bp 6 /* SDRAM Mode Register Delay bit 0 position. */ -#define EBI_MRDLY1_bm (1<<7) /* SDRAM Mode Register Delay bit 1 mask. */ -#define EBI_MRDLY1_bp 7 /* SDRAM Mode Register Delay bit 1 position. */ - -#define EBI_ROWCYCDLY_gm 0x38 /* SDRAM Row Cycle Delay group mask. */ -#define EBI_ROWCYCDLY_gp 3 /* SDRAM Row Cycle Delay group position. */ -#define EBI_ROWCYCDLY0_bm (1<<3) /* SDRAM Row Cycle Delay bit 0 mask. */ -#define EBI_ROWCYCDLY0_bp 3 /* SDRAM Row Cycle Delay bit 0 position. */ -#define EBI_ROWCYCDLY1_bm (1<<4) /* SDRAM Row Cycle Delay bit 1 mask. */ -#define EBI_ROWCYCDLY1_bp 4 /* SDRAM Row Cycle Delay bit 1 position. */ -#define EBI_ROWCYCDLY2_bm (1<<5) /* SDRAM Row Cycle Delay bit 2 mask. */ -#define EBI_ROWCYCDLY2_bp 5 /* SDRAM Row Cycle Delay bit 2 position. */ - -#define EBI_RPDLY_gm 0x07 /* SDRAM Row-to-Precharge Delay group mask. */ -#define EBI_RPDLY_gp 0 /* SDRAM Row-to-Precharge Delay group position. */ -#define EBI_RPDLY0_bm (1<<0) /* SDRAM Row-to-Precharge Delay bit 0 mask. */ -#define EBI_RPDLY0_bp 0 /* SDRAM Row-to-Precharge Delay bit 0 position. */ -#define EBI_RPDLY1_bm (1<<1) /* SDRAM Row-to-Precharge Delay bit 1 mask. */ -#define EBI_RPDLY1_bp 1 /* SDRAM Row-to-Precharge Delay bit 1 position. */ -#define EBI_RPDLY2_bm (1<<2) /* SDRAM Row-to-Precharge Delay bit 2 mask. */ -#define EBI_RPDLY2_bp 2 /* SDRAM Row-to-Precharge Delay bit 2 position. */ - - -/* EBI.SDRAMCTRLC bit masks and bit positions */ -#define EBI_WRDLY_gm 0xC0 /* SDRAM Write Recovery Delay group mask. */ -#define EBI_WRDLY_gp 6 /* SDRAM Write Recovery Delay group position. */ -#define EBI_WRDLY0_bm (1<<6) /* SDRAM Write Recovery Delay bit 0 mask. */ -#define EBI_WRDLY0_bp 6 /* SDRAM Write Recovery Delay bit 0 position. */ -#define EBI_WRDLY1_bm (1<<7) /* SDRAM Write Recovery Delay bit 1 mask. */ -#define EBI_WRDLY1_bp 7 /* SDRAM Write Recovery Delay bit 1 position. */ - -#define EBI_ESRDLY_gm 0x38 /* SDRAM Exit-Self-refresh-to-Active Delay group mask. */ -#define EBI_ESRDLY_gp 3 /* SDRAM Exit-Self-refresh-to-Active Delay group position. */ -#define EBI_ESRDLY0_bm (1<<3) /* SDRAM Exit-Self-refresh-to-Active Delay bit 0 mask. */ -#define EBI_ESRDLY0_bp 3 /* SDRAM Exit-Self-refresh-to-Active Delay bit 0 position. */ -#define EBI_ESRDLY1_bm (1<<4) /* SDRAM Exit-Self-refresh-to-Active Delay bit 1 mask. */ -#define EBI_ESRDLY1_bp 4 /* SDRAM Exit-Self-refresh-to-Active Delay bit 1 position. */ -#define EBI_ESRDLY2_bm (1<<5) /* SDRAM Exit-Self-refresh-to-Active Delay bit 2 mask. */ -#define EBI_ESRDLY2_bp 5 /* SDRAM Exit-Self-refresh-to-Active Delay bit 2 position. */ - -#define EBI_ROWCOLDLY_gm 0x07 /* SDRAM Row-to-Column Delay group mask. */ -#define EBI_ROWCOLDLY_gp 0 /* SDRAM Row-to-Column Delay group position. */ -#define EBI_ROWCOLDLY0_bm (1<<0) /* SDRAM Row-to-Column Delay bit 0 mask. */ -#define EBI_ROWCOLDLY0_bp 0 /* SDRAM Row-to-Column Delay bit 0 position. */ -#define EBI_ROWCOLDLY1_bm (1<<1) /* SDRAM Row-to-Column Delay bit 1 mask. */ -#define EBI_ROWCOLDLY1_bp 1 /* SDRAM Row-to-Column Delay bit 1 position. */ -#define EBI_ROWCOLDLY2_bm (1<<2) /* SDRAM Row-to-Column Delay bit 2 mask. */ -#define EBI_ROWCOLDLY2_bp 2 /* SDRAM Row-to-Column Delay bit 2 position. */ - - -/* TWI - Two-Wire Interface */ -/* TWI_MASTER.CTRLA bit masks and bit positions */ -#define TWI_MASTER_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ -#define TWI_MASTER_INTLVL_gp 6 /* Interrupt Level group position. */ -#define TWI_MASTER_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ -#define TWI_MASTER_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ -#define TWI_MASTER_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ -#define TWI_MASTER_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ - -#define TWI_MASTER_RIEN_bm 0x20 /* Read Interrupt Enable bit mask. */ -#define TWI_MASTER_RIEN_bp 5 /* Read Interrupt Enable bit position. */ - -#define TWI_MASTER_WIEN_bm 0x10 /* Write Interrupt Enable bit mask. */ -#define TWI_MASTER_WIEN_bp 4 /* Write Interrupt Enable bit position. */ - -#define TWI_MASTER_ENABLE_bm 0x08 /* Enable TWI Master bit mask. */ -#define TWI_MASTER_ENABLE_bp 3 /* Enable TWI Master bit position. */ - - -/* TWI_MASTER.CTRLB bit masks and bit positions */ -#define TWI_MASTER_TIMEOUT_gm 0x0C /* Inactive Bus Timeout group mask. */ -#define TWI_MASTER_TIMEOUT_gp 2 /* Inactive Bus Timeout group position. */ -#define TWI_MASTER_TIMEOUT0_bm (1<<2) /* Inactive Bus Timeout bit 0 mask. */ -#define TWI_MASTER_TIMEOUT0_bp 2 /* Inactive Bus Timeout bit 0 position. */ -#define TWI_MASTER_TIMEOUT1_bm (1<<3) /* Inactive Bus Timeout bit 1 mask. */ -#define TWI_MASTER_TIMEOUT1_bp 3 /* Inactive Bus Timeout bit 1 position. */ - -#define TWI_MASTER_QCEN_bm 0x02 /* Quick Command Enable bit mask. */ -#define TWI_MASTER_QCEN_bp 1 /* Quick Command Enable bit position. */ - -#define TWI_MASTER_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ -#define TWI_MASTER_SMEN_bp 0 /* Smart Mode Enable bit position. */ - - -/* TWI_MASTER.CTRLC bit masks and bit positions */ -#define TWI_MASTER_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ -#define TWI_MASTER_ACKACT_bp 2 /* Acknowledge Action bit position. */ - -#define TWI_MASTER_CMD_gm 0x03 /* Command group mask. */ -#define TWI_MASTER_CMD_gp 0 /* Command group position. */ -#define TWI_MASTER_CMD0_bm (1<<0) /* Command bit 0 mask. */ -#define TWI_MASTER_CMD0_bp 0 /* Command bit 0 position. */ -#define TWI_MASTER_CMD1_bm (1<<1) /* Command bit 1 mask. */ -#define TWI_MASTER_CMD1_bp 1 /* Command bit 1 position. */ - - -/* TWI_MASTER.STATUS bit masks and bit positions */ -#define TWI_MASTER_RIF_bm 0x80 /* Read Interrupt Flag bit mask. */ -#define TWI_MASTER_RIF_bp 7 /* Read Interrupt Flag bit position. */ - -#define TWI_MASTER_WIF_bm 0x40 /* Write Interrupt Flag bit mask. */ -#define TWI_MASTER_WIF_bp 6 /* Write Interrupt Flag bit position. */ - -#define TWI_MASTER_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ -#define TWI_MASTER_CLKHOLD_bp 5 /* Clock Hold bit position. */ - -#define TWI_MASTER_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ -#define TWI_MASTER_RXACK_bp 4 /* Received Acknowledge bit position. */ - -#define TWI_MASTER_ARBLOST_bm 0x08 /* Arbitration Lost bit mask. */ -#define TWI_MASTER_ARBLOST_bp 3 /* Arbitration Lost bit position. */ - -#define TWI_MASTER_BUSERR_bm 0x04 /* Bus Error bit mask. */ -#define TWI_MASTER_BUSERR_bp 2 /* Bus Error bit position. */ - -#define TWI_MASTER_BUSSTATE_gm 0x03 /* Bus State group mask. */ -#define TWI_MASTER_BUSSTATE_gp 0 /* Bus State group position. */ -#define TWI_MASTER_BUSSTATE0_bm (1<<0) /* Bus State bit 0 mask. */ -#define TWI_MASTER_BUSSTATE0_bp 0 /* Bus State bit 0 position. */ -#define TWI_MASTER_BUSSTATE1_bm (1<<1) /* Bus State bit 1 mask. */ -#define TWI_MASTER_BUSSTATE1_bp 1 /* Bus State bit 1 position. */ - - -/* TWI_SLAVE.CTRLA bit masks and bit positions */ -#define TWI_SLAVE_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ -#define TWI_SLAVE_INTLVL_gp 6 /* Interrupt Level group position. */ -#define TWI_SLAVE_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ -#define TWI_SLAVE_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ -#define TWI_SLAVE_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ -#define TWI_SLAVE_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ - -#define TWI_SLAVE_DIEN_bm 0x20 /* Data Interrupt Enable bit mask. */ -#define TWI_SLAVE_DIEN_bp 5 /* Data Interrupt Enable bit position. */ - -#define TWI_SLAVE_APIEN_bm 0x10 /* Address/Stop Interrupt Enable bit mask. */ -#define TWI_SLAVE_APIEN_bp 4 /* Address/Stop Interrupt Enable bit position. */ - -#define TWI_SLAVE_ENABLE_bm 0x08 /* Enable TWI Slave bit mask. */ -#define TWI_SLAVE_ENABLE_bp 3 /* Enable TWI Slave bit position. */ - -#define TWI_SLAVE_PIEN_bm 0x04 /* Stop Interrupt Enable bit mask. */ -#define TWI_SLAVE_PIEN_bp 2 /* Stop Interrupt Enable bit position. */ - -#define TWI_SLAVE_PMEN_bm 0x02 /* Promiscuous Mode Enable bit mask. */ -#define TWI_SLAVE_PMEN_bp 1 /* Promiscuous Mode Enable bit position. */ - -#define TWI_SLAVE_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ -#define TWI_SLAVE_SMEN_bp 0 /* Smart Mode Enable bit position. */ - - -/* TWI_SLAVE.CTRLB bit masks and bit positions */ -#define TWI_SLAVE_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ -#define TWI_SLAVE_ACKACT_bp 2 /* Acknowledge Action bit position. */ - -#define TWI_SLAVE_CMD_gm 0x03 /* Command group mask. */ -#define TWI_SLAVE_CMD_gp 0 /* Command group position. */ -#define TWI_SLAVE_CMD0_bm (1<<0) /* Command bit 0 mask. */ -#define TWI_SLAVE_CMD0_bp 0 /* Command bit 0 position. */ -#define TWI_SLAVE_CMD1_bm (1<<1) /* Command bit 1 mask. */ -#define TWI_SLAVE_CMD1_bp 1 /* Command bit 1 position. */ - - -/* TWI_SLAVE.STATUS bit masks and bit positions */ -#define TWI_SLAVE_DIF_bm 0x80 /* Data Interrupt Flag bit mask. */ -#define TWI_SLAVE_DIF_bp 7 /* Data Interrupt Flag bit position. */ - -#define TWI_SLAVE_APIF_bm 0x40 /* Address/Stop Interrupt Flag bit mask. */ -#define TWI_SLAVE_APIF_bp 6 /* Address/Stop Interrupt Flag bit position. */ - -#define TWI_SLAVE_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ -#define TWI_SLAVE_CLKHOLD_bp 5 /* Clock Hold bit position. */ - -#define TWI_SLAVE_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ -#define TWI_SLAVE_RXACK_bp 4 /* Received Acknowledge bit position. */ - -#define TWI_SLAVE_COLL_bm 0x08 /* Collision bit mask. */ -#define TWI_SLAVE_COLL_bp 3 /* Collision bit position. */ - -#define TWI_SLAVE_BUSERR_bm 0x04 /* Bus Error bit mask. */ -#define TWI_SLAVE_BUSERR_bp 2 /* Bus Error bit position. */ - -#define TWI_SLAVE_DIR_bm 0x02 /* Read/Write Direction bit mask. */ -#define TWI_SLAVE_DIR_bp 1 /* Read/Write Direction bit position. */ - -#define TWI_SLAVE_AP_bm 0x01 /* Slave Address or Stop bit mask. */ -#define TWI_SLAVE_AP_bp 0 /* Slave Address or Stop bit position. */ - - -/* TWI_SLAVE.ADDRMASK bit masks and bit positions */ -#define TWI_SLAVE_ADDRMASK_gm 0xFE /* Address Mask group mask. */ -#define TWI_SLAVE_ADDRMASK_gp 1 /* Address Mask group position. */ -#define TWI_SLAVE_ADDRMASK0_bm (1<<1) /* Address Mask bit 0 mask. */ -#define TWI_SLAVE_ADDRMASK0_bp 1 /* Address Mask bit 0 position. */ -#define TWI_SLAVE_ADDRMASK1_bm (1<<2) /* Address Mask bit 1 mask. */ -#define TWI_SLAVE_ADDRMASK1_bp 2 /* Address Mask bit 1 position. */ -#define TWI_SLAVE_ADDRMASK2_bm (1<<3) /* Address Mask bit 2 mask. */ -#define TWI_SLAVE_ADDRMASK2_bp 3 /* Address Mask bit 2 position. */ -#define TWI_SLAVE_ADDRMASK3_bm (1<<4) /* Address Mask bit 3 mask. */ -#define TWI_SLAVE_ADDRMASK3_bp 4 /* Address Mask bit 3 position. */ -#define TWI_SLAVE_ADDRMASK4_bm (1<<5) /* Address Mask bit 4 mask. */ -#define TWI_SLAVE_ADDRMASK4_bp 5 /* Address Mask bit 4 position. */ -#define TWI_SLAVE_ADDRMASK5_bm (1<<6) /* Address Mask bit 5 mask. */ -#define TWI_SLAVE_ADDRMASK5_bp 6 /* Address Mask bit 5 position. */ -#define TWI_SLAVE_ADDRMASK6_bm (1<<7) /* Address Mask bit 6 mask. */ -#define TWI_SLAVE_ADDRMASK6_bp 7 /* Address Mask bit 6 position. */ - -#define TWI_SLAVE_ADDREN_bm 0x01 /* Address Enable bit mask. */ -#define TWI_SLAVE_ADDREN_bp 0 /* Address Enable bit position. */ - - -/* TWI.CTRL bit masks and bit positions */ -#define TWI_SDAHOLD_bm 0x02 /* SDA Hold Time Enable bit mask. */ -#define TWI_SDAHOLD_bp 1 /* SDA Hold Time Enable bit position. */ - -#define TWI_EDIEN_bm 0x01 /* External Driver Interface Enable bit mask. */ -#define TWI_EDIEN_bp 0 /* External Driver Interface Enable bit position. */ - - -/* PORT - Port Configuration */ -/* PORTCFG.VPCTRLA bit masks and bit positions */ -#define PORTCFG_VP1MAP_gm 0xF0 /* Virtual Port 1 Mapping group mask. */ -#define PORTCFG_VP1MAP_gp 4 /* Virtual Port 1 Mapping group position. */ -#define PORTCFG_VP1MAP0_bm (1<<4) /* Virtual Port 1 Mapping bit 0 mask. */ -#define PORTCFG_VP1MAP0_bp 4 /* Virtual Port 1 Mapping bit 0 position. */ -#define PORTCFG_VP1MAP1_bm (1<<5) /* Virtual Port 1 Mapping bit 1 mask. */ -#define PORTCFG_VP1MAP1_bp 5 /* Virtual Port 1 Mapping bit 1 position. */ -#define PORTCFG_VP1MAP2_bm (1<<6) /* Virtual Port 1 Mapping bit 2 mask. */ -#define PORTCFG_VP1MAP2_bp 6 /* Virtual Port 1 Mapping bit 2 position. */ -#define PORTCFG_VP1MAP3_bm (1<<7) /* Virtual Port 1 Mapping bit 3 mask. */ -#define PORTCFG_VP1MAP3_bp 7 /* Virtual Port 1 Mapping bit 3 position. */ - -#define PORTCFG_VP0MAP_gm 0x0F /* Virtual Port 0 Mapping group mask. */ -#define PORTCFG_VP0MAP_gp 0 /* Virtual Port 0 Mapping group position. */ -#define PORTCFG_VP0MAP0_bm (1<<0) /* Virtual Port 0 Mapping bit 0 mask. */ -#define PORTCFG_VP0MAP0_bp 0 /* Virtual Port 0 Mapping bit 0 position. */ -#define PORTCFG_VP0MAP1_bm (1<<1) /* Virtual Port 0 Mapping bit 1 mask. */ -#define PORTCFG_VP0MAP1_bp 1 /* Virtual Port 0 Mapping bit 1 position. */ -#define PORTCFG_VP0MAP2_bm (1<<2) /* Virtual Port 0 Mapping bit 2 mask. */ -#define PORTCFG_VP0MAP2_bp 2 /* Virtual Port 0 Mapping bit 2 position. */ -#define PORTCFG_VP0MAP3_bm (1<<3) /* Virtual Port 0 Mapping bit 3 mask. */ -#define PORTCFG_VP0MAP3_bp 3 /* Virtual Port 0 Mapping bit 3 position. */ - - -/* PORTCFG.VPCTRLB bit masks and bit positions */ -#define PORTCFG_VP3MAP_gm 0xF0 /* Virtual Port 3 Mapping group mask. */ -#define PORTCFG_VP3MAP_gp 4 /* Virtual Port 3 Mapping group position. */ -#define PORTCFG_VP3MAP0_bm (1<<4) /* Virtual Port 3 Mapping bit 0 mask. */ -#define PORTCFG_VP3MAP0_bp 4 /* Virtual Port 3 Mapping bit 0 position. */ -#define PORTCFG_VP3MAP1_bm (1<<5) /* Virtual Port 3 Mapping bit 1 mask. */ -#define PORTCFG_VP3MAP1_bp 5 /* Virtual Port 3 Mapping bit 1 position. */ -#define PORTCFG_VP3MAP2_bm (1<<6) /* Virtual Port 3 Mapping bit 2 mask. */ -#define PORTCFG_VP3MAP2_bp 6 /* Virtual Port 3 Mapping bit 2 position. */ -#define PORTCFG_VP3MAP3_bm (1<<7) /* Virtual Port 3 Mapping bit 3 mask. */ -#define PORTCFG_VP3MAP3_bp 7 /* Virtual Port 3 Mapping bit 3 position. */ - -#define PORTCFG_VP2MAP_gm 0x0F /* Virtual Port 2 Mapping group mask. */ -#define PORTCFG_VP2MAP_gp 0 /* Virtual Port 2 Mapping group position. */ -#define PORTCFG_VP2MAP0_bm (1<<0) /* Virtual Port 2 Mapping bit 0 mask. */ -#define PORTCFG_VP2MAP0_bp 0 /* Virtual Port 2 Mapping bit 0 position. */ -#define PORTCFG_VP2MAP1_bm (1<<1) /* Virtual Port 2 Mapping bit 1 mask. */ -#define PORTCFG_VP2MAP1_bp 1 /* Virtual Port 2 Mapping bit 1 position. */ -#define PORTCFG_VP2MAP2_bm (1<<2) /* Virtual Port 2 Mapping bit 2 mask. */ -#define PORTCFG_VP2MAP2_bp 2 /* Virtual Port 2 Mapping bit 2 position. */ -#define PORTCFG_VP2MAP3_bm (1<<3) /* Virtual Port 2 Mapping bit 3 mask. */ -#define PORTCFG_VP2MAP3_bp 3 /* Virtual Port 2 Mapping bit 3 position. */ - - -/* PORTCFG.CLKEVOUT bit masks and bit positions */ -#define PORTCFG_CLKOUT_gm 0x03 /* Clock Output Port group mask. */ -#define PORTCFG_CLKOUT_gp 0 /* Clock Output Port group position. */ -#define PORTCFG_CLKOUT0_bm (1<<0) /* Clock Output Port bit 0 mask. */ -#define PORTCFG_CLKOUT0_bp 0 /* Clock Output Port bit 0 position. */ -#define PORTCFG_CLKOUT1_bm (1<<1) /* Clock Output Port bit 1 mask. */ -#define PORTCFG_CLKOUT1_bp 1 /* Clock Output Port bit 1 position. */ - -#define PORTCFG_EVOUT_gm 0x30 /* Event Output Port group mask. */ -#define PORTCFG_EVOUT_gp 4 /* Event Output Port group position. */ -#define PORTCFG_EVOUT0_bm (1<<4) /* Event Output Port bit 0 mask. */ -#define PORTCFG_EVOUT0_bp 4 /* Event Output Port bit 0 position. */ -#define PORTCFG_EVOUT1_bm (1<<5) /* Event Output Port bit 1 mask. */ -#define PORTCFG_EVOUT1_bp 5 /* Event Output Port bit 1 position. */ - - -/* VPORT.INTFLAGS bit masks and bit positions */ -#define VPORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ -#define VPORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ - -#define VPORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ -#define VPORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ - - -/* PORT.INTCTRL bit masks and bit positions */ -#define PORT_INT1LVL_gm 0x0C /* Port Interrupt 1 Level group mask. */ -#define PORT_INT1LVL_gp 2 /* Port Interrupt 1 Level group position. */ -#define PORT_INT1LVL0_bm (1<<2) /* Port Interrupt 1 Level bit 0 mask. */ -#define PORT_INT1LVL0_bp 2 /* Port Interrupt 1 Level bit 0 position. */ -#define PORT_INT1LVL1_bm (1<<3) /* Port Interrupt 1 Level bit 1 mask. */ -#define PORT_INT1LVL1_bp 3 /* Port Interrupt 1 Level bit 1 position. */ - -#define PORT_INT0LVL_gm 0x03 /* Port Interrupt 0 Level group mask. */ -#define PORT_INT0LVL_gp 0 /* Port Interrupt 0 Level group position. */ -#define PORT_INT0LVL0_bm (1<<0) /* Port Interrupt 0 Level bit 0 mask. */ -#define PORT_INT0LVL0_bp 0 /* Port Interrupt 0 Level bit 0 position. */ -#define PORT_INT0LVL1_bm (1<<1) /* Port Interrupt 0 Level bit 1 mask. */ -#define PORT_INT0LVL1_bp 1 /* Port Interrupt 0 Level bit 1 position. */ - - -/* PORT.INTFLAGS bit masks and bit positions */ -#define PORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ -#define PORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ - -#define PORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ -#define PORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ - - -/* PORT.PIN0CTRL bit masks and bit positions */ -#define PORT_SRLEN_bm 0x80 /* Slew Rate Enable bit mask. */ -#define PORT_SRLEN_bp 7 /* Slew Rate Enable bit position. */ - -#define PORT_INVEN_bm 0x40 /* Inverted I/O Enable bit mask. */ -#define PORT_INVEN_bp 6 /* Inverted I/O Enable bit position. */ - -#define PORT_OPC_gm 0x38 /* Output/Pull Configuration group mask. */ -#define PORT_OPC_gp 3 /* Output/Pull Configuration group position. */ -#define PORT_OPC0_bm (1<<3) /* Output/Pull Configuration bit 0 mask. */ -#define PORT_OPC0_bp 3 /* Output/Pull Configuration bit 0 position. */ -#define PORT_OPC1_bm (1<<4) /* Output/Pull Configuration bit 1 mask. */ -#define PORT_OPC1_bp 4 /* Output/Pull Configuration bit 1 position. */ -#define PORT_OPC2_bm (1<<5) /* Output/Pull Configuration bit 2 mask. */ -#define PORT_OPC2_bp 5 /* Output/Pull Configuration bit 2 position. */ - -#define PORT_ISC_gm 0x07 /* Input/Sense Configuration group mask. */ -#define PORT_ISC_gp 0 /* Input/Sense Configuration group position. */ -#define PORT_ISC0_bm (1<<0) /* Input/Sense Configuration bit 0 mask. */ -#define PORT_ISC0_bp 0 /* Input/Sense Configuration bit 0 position. */ -#define PORT_ISC1_bm (1<<1) /* Input/Sense Configuration bit 1 mask. */ -#define PORT_ISC1_bp 1 /* Input/Sense Configuration bit 1 position. */ -#define PORT_ISC2_bm (1<<2) /* Input/Sense Configuration bit 2 mask. */ -#define PORT_ISC2_bp 2 /* Input/Sense Configuration bit 2 position. */ - - -/* PORT.PIN1CTRL bit masks and bit positions */ -/* PORT_SRLEN_bm Predefined. */ -/* PORT_SRLEN_bp Predefined. */ - -/* PORT_INVEN_bm Predefined. */ -/* PORT_INVEN_bp Predefined. */ - -/* PORT_OPC_gm Predefined. */ -/* PORT_OPC_gp Predefined. */ -/* PORT_OPC0_bm Predefined. */ -/* PORT_OPC0_bp Predefined. */ -/* PORT_OPC1_bm Predefined. */ -/* PORT_OPC1_bp Predefined. */ -/* PORT_OPC2_bm Predefined. */ -/* PORT_OPC2_bp Predefined. */ - -/* PORT_ISC_gm Predefined. */ -/* PORT_ISC_gp Predefined. */ -/* PORT_ISC0_bm Predefined. */ -/* PORT_ISC0_bp Predefined. */ -/* PORT_ISC1_bm Predefined. */ -/* PORT_ISC1_bp Predefined. */ -/* PORT_ISC2_bm Predefined. */ -/* PORT_ISC2_bp Predefined. */ - - -/* PORT.PIN2CTRL bit masks and bit positions */ -/* PORT_SRLEN_bm Predefined. */ -/* PORT_SRLEN_bp Predefined. */ - -/* PORT_INVEN_bm Predefined. */ -/* PORT_INVEN_bp Predefined. */ - -/* PORT_OPC_gm Predefined. */ -/* PORT_OPC_gp Predefined. */ -/* PORT_OPC0_bm Predefined. */ -/* PORT_OPC0_bp Predefined. */ -/* PORT_OPC1_bm Predefined. */ -/* PORT_OPC1_bp Predefined. */ -/* PORT_OPC2_bm Predefined. */ -/* PORT_OPC2_bp Predefined. */ - -/* PORT_ISC_gm Predefined. */ -/* PORT_ISC_gp Predefined. */ -/* PORT_ISC0_bm Predefined. */ -/* PORT_ISC0_bp Predefined. */ -/* PORT_ISC1_bm Predefined. */ -/* PORT_ISC1_bp Predefined. */ -/* PORT_ISC2_bm Predefined. */ -/* PORT_ISC2_bp Predefined. */ - - -/* PORT.PIN3CTRL bit masks and bit positions */ -/* PORT_SRLEN_bm Predefined. */ -/* PORT_SRLEN_bp Predefined. */ - -/* PORT_INVEN_bm Predefined. */ -/* PORT_INVEN_bp Predefined. */ - -/* PORT_OPC_gm Predefined. */ -/* PORT_OPC_gp Predefined. */ -/* PORT_OPC0_bm Predefined. */ -/* PORT_OPC0_bp Predefined. */ -/* PORT_OPC1_bm Predefined. */ -/* PORT_OPC1_bp Predefined. */ -/* PORT_OPC2_bm Predefined. */ -/* PORT_OPC2_bp Predefined. */ - -/* PORT_ISC_gm Predefined. */ -/* PORT_ISC_gp Predefined. */ -/* PORT_ISC0_bm Predefined. */ -/* PORT_ISC0_bp Predefined. */ -/* PORT_ISC1_bm Predefined. */ -/* PORT_ISC1_bp Predefined. */ -/* PORT_ISC2_bm Predefined. */ -/* PORT_ISC2_bp Predefined. */ - - -/* PORT.PIN4CTRL bit masks and bit positions */ -/* PORT_SRLEN_bm Predefined. */ -/* PORT_SRLEN_bp Predefined. */ - -/* PORT_INVEN_bm Predefined. */ -/* PORT_INVEN_bp Predefined. */ - -/* PORT_OPC_gm Predefined. */ -/* PORT_OPC_gp Predefined. */ -/* PORT_OPC0_bm Predefined. */ -/* PORT_OPC0_bp Predefined. */ -/* PORT_OPC1_bm Predefined. */ -/* PORT_OPC1_bp Predefined. */ -/* PORT_OPC2_bm Predefined. */ -/* PORT_OPC2_bp Predefined. */ - -/* PORT_ISC_gm Predefined. */ -/* PORT_ISC_gp Predefined. */ -/* PORT_ISC0_bm Predefined. */ -/* PORT_ISC0_bp Predefined. */ -/* PORT_ISC1_bm Predefined. */ -/* PORT_ISC1_bp Predefined. */ -/* PORT_ISC2_bm Predefined. */ -/* PORT_ISC2_bp Predefined. */ - - -/* PORT.PIN5CTRL bit masks and bit positions */ -/* PORT_SRLEN_bm Predefined. */ -/* PORT_SRLEN_bp Predefined. */ - -/* PORT_INVEN_bm Predefined. */ -/* PORT_INVEN_bp Predefined. */ - -/* PORT_OPC_gm Predefined. */ -/* PORT_OPC_gp Predefined. */ -/* PORT_OPC0_bm Predefined. */ -/* PORT_OPC0_bp Predefined. */ -/* PORT_OPC1_bm Predefined. */ -/* PORT_OPC1_bp Predefined. */ -/* PORT_OPC2_bm Predefined. */ -/* PORT_OPC2_bp Predefined. */ - -/* PORT_ISC_gm Predefined. */ -/* PORT_ISC_gp Predefined. */ -/* PORT_ISC0_bm Predefined. */ -/* PORT_ISC0_bp Predefined. */ -/* PORT_ISC1_bm Predefined. */ -/* PORT_ISC1_bp Predefined. */ -/* PORT_ISC2_bm Predefined. */ -/* PORT_ISC2_bp Predefined. */ - - -/* PORT.PIN6CTRL bit masks and bit positions */ -/* PORT_SRLEN_bm Predefined. */ -/* PORT_SRLEN_bp Predefined. */ - -/* PORT_INVEN_bm Predefined. */ -/* PORT_INVEN_bp Predefined. */ - -/* PORT_OPC_gm Predefined. */ -/* PORT_OPC_gp Predefined. */ -/* PORT_OPC0_bm Predefined. */ -/* PORT_OPC0_bp Predefined. */ -/* PORT_OPC1_bm Predefined. */ -/* PORT_OPC1_bp Predefined. */ -/* PORT_OPC2_bm Predefined. */ -/* PORT_OPC2_bp Predefined. */ - -/* PORT_ISC_gm Predefined. */ -/* PORT_ISC_gp Predefined. */ -/* PORT_ISC0_bm Predefined. */ -/* PORT_ISC0_bp Predefined. */ -/* PORT_ISC1_bm Predefined. */ -/* PORT_ISC1_bp Predefined. */ -/* PORT_ISC2_bm Predefined. */ -/* PORT_ISC2_bp Predefined. */ - - -/* PORT.PIN7CTRL bit masks and bit positions */ -/* PORT_SRLEN_bm Predefined. */ -/* PORT_SRLEN_bp Predefined. */ - -/* PORT_INVEN_bm Predefined. */ -/* PORT_INVEN_bp Predefined. */ - -/* PORT_OPC_gm Predefined. */ -/* PORT_OPC_gp Predefined. */ -/* PORT_OPC0_bm Predefined. */ -/* PORT_OPC0_bp Predefined. */ -/* PORT_OPC1_bm Predefined. */ -/* PORT_OPC1_bp Predefined. */ -/* PORT_OPC2_bm Predefined. */ -/* PORT_OPC2_bp Predefined. */ - -/* PORT_ISC_gm Predefined. */ -/* PORT_ISC_gp Predefined. */ -/* PORT_ISC0_bm Predefined. */ -/* PORT_ISC0_bp Predefined. */ -/* PORT_ISC1_bm Predefined. */ -/* PORT_ISC1_bp Predefined. */ -/* PORT_ISC2_bm Predefined. */ -/* PORT_ISC2_bp Predefined. */ - - -/* TC - 16-bit Timer/Counter With PWM */ -/* TC0.CTRLA bit masks and bit positions */ -#define TC0_CLKSEL_gm 0x0F /* Clock Selection group mask. */ -#define TC0_CLKSEL_gp 0 /* Clock Selection group position. */ -#define TC0_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ -#define TC0_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ -#define TC0_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ -#define TC0_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ -#define TC0_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ -#define TC0_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ -#define TC0_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ -#define TC0_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ - - -/* TC0.CTRLB bit masks and bit positions */ -#define TC0_CCDEN_bm 0x80 /* Compare or Capture D Enable bit mask. */ -#define TC0_CCDEN_bp 7 /* Compare or Capture D Enable bit position. */ - -#define TC0_CCCEN_bm 0x40 /* Compare or Capture C Enable bit mask. */ -#define TC0_CCCEN_bp 6 /* Compare or Capture C Enable bit position. */ - -#define TC0_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ -#define TC0_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ - -#define TC0_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ -#define TC0_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ - -#define TC0_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ -#define TC0_WGMODE_gp 0 /* Waveform generation mode group position. */ -#define TC0_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ -#define TC0_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ -#define TC0_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ -#define TC0_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ -#define TC0_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ -#define TC0_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ - - -/* TC0.CTRLC bit masks and bit positions */ -#define TC0_CMPD_bm 0x08 /* Compare D Output Value bit mask. */ -#define TC0_CMPD_bp 3 /* Compare D Output Value bit position. */ - -#define TC0_CMPC_bm 0x04 /* Compare C Output Value bit mask. */ -#define TC0_CMPC_bp 2 /* Compare C Output Value bit position. */ - -#define TC0_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ -#define TC0_CMPB_bp 1 /* Compare B Output Value bit position. */ - -#define TC0_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ -#define TC0_CMPA_bp 0 /* Compare A Output Value bit position. */ - - -/* TC0.CTRLD bit masks and bit positions */ -#define TC0_EVACT_gm 0xE0 /* Event Action group mask. */ -#define TC0_EVACT_gp 5 /* Event Action group position. */ -#define TC0_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ -#define TC0_EVACT0_bp 5 /* Event Action bit 0 position. */ -#define TC0_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ -#define TC0_EVACT1_bp 6 /* Event Action bit 1 position. */ -#define TC0_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ -#define TC0_EVACT2_bp 7 /* Event Action bit 2 position. */ - -#define TC0_EVDLY_bm 0x10 /* Event Delay bit mask. */ -#define TC0_EVDLY_bp 4 /* Event Delay bit position. */ - -#define TC0_EVSEL_gm 0x0F /* Event Source Select group mask. */ -#define TC0_EVSEL_gp 0 /* Event Source Select group position. */ -#define TC0_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ -#define TC0_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ -#define TC0_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ -#define TC0_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ -#define TC0_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ -#define TC0_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ -#define TC0_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ -#define TC0_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ - - -/* TC0.CTRLE bit masks and bit positions */ -#define TC0_DTHM_bm 0x02 /* Dead Time Hold Mode bit mask. */ -#define TC0_DTHM_bp 1 /* Dead Time Hold Mode bit position. */ - -#define TC0_BYTEM_bm 0x01 /* Byte Mode bit mask. */ -#define TC0_BYTEM_bp 0 /* Byte Mode bit position. */ - - -/* TC0.INTCTRLA bit masks and bit positions */ -#define TC0_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ -#define TC0_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ -#define TC0_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ -#define TC0_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ -#define TC0_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ -#define TC0_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ - -#define TC0_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ -#define TC0_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ -#define TC0_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ -#define TC0_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ -#define TC0_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ -#define TC0_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ - - -/* TC0.INTCTRLB bit masks and bit positions */ -#define TC0_CCDINTLVL_gm 0xC0 /* Compare or Capture D Interrupt Level group mask. */ -#define TC0_CCDINTLVL_gp 6 /* Compare or Capture D Interrupt Level group position. */ -#define TC0_CCDINTLVL0_bm (1<<6) /* Compare or Capture D Interrupt Level bit 0 mask. */ -#define TC0_CCDINTLVL0_bp 6 /* Compare or Capture D Interrupt Level bit 0 position. */ -#define TC0_CCDINTLVL1_bm (1<<7) /* Compare or Capture D Interrupt Level bit 1 mask. */ -#define TC0_CCDINTLVL1_bp 7 /* Compare or Capture D Interrupt Level bit 1 position. */ - -#define TC0_CCCINTLVL_gm 0x30 /* Compare or Capture C Interrupt Level group mask. */ -#define TC0_CCCINTLVL_gp 4 /* Compare or Capture C Interrupt Level group position. */ -#define TC0_CCCINTLVL0_bm (1<<4) /* Compare or Capture C Interrupt Level bit 0 mask. */ -#define TC0_CCCINTLVL0_bp 4 /* Compare or Capture C Interrupt Level bit 0 position. */ -#define TC0_CCCINTLVL1_bm (1<<5) /* Compare or Capture C Interrupt Level bit 1 mask. */ -#define TC0_CCCINTLVL1_bp 5 /* Compare or Capture C Interrupt Level bit 1 position. */ - -#define TC0_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ -#define TC0_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ -#define TC0_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ -#define TC0_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ -#define TC0_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ -#define TC0_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ - -#define TC0_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ -#define TC0_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ -#define TC0_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ -#define TC0_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ -#define TC0_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ -#define TC0_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ - - -/* TC0.CTRLFCLR bit masks and bit positions */ -#define TC0_CMD_gm 0x0C /* Command group mask. */ -#define TC0_CMD_gp 2 /* Command group position. */ -#define TC0_CMD0_bm (1<<2) /* Command bit 0 mask. */ -#define TC0_CMD0_bp 2 /* Command bit 0 position. */ -#define TC0_CMD1_bm (1<<3) /* Command bit 1 mask. */ -#define TC0_CMD1_bp 3 /* Command bit 1 position. */ - -#define TC0_LUPD_bm 0x02 /* Lock Update bit mask. */ -#define TC0_LUPD_bp 1 /* Lock Update bit position. */ - -#define TC0_DIR_bm 0x01 /* Direction bit mask. */ -#define TC0_DIR_bp 0 /* Direction bit position. */ - - -/* TC0.CTRLFSET bit masks and bit positions */ -/* TC0_CMD_gm Predefined. */ -/* TC0_CMD_gp Predefined. */ -/* TC0_CMD0_bm Predefined. */ -/* TC0_CMD0_bp Predefined. */ -/* TC0_CMD1_bm Predefined. */ -/* TC0_CMD1_bp Predefined. */ - -/* TC0_LUPD_bm Predefined. */ -/* TC0_LUPD_bp Predefined. */ - -/* TC0_DIR_bm Predefined. */ -/* TC0_DIR_bp Predefined. */ - - -/* TC0.CTRLGCLR bit masks and bit positions */ -#define TC0_CCDBV_bm 0x10 /* Compare or Capture D Buffer Valid bit mask. */ -#define TC0_CCDBV_bp 4 /* Compare or Capture D Buffer Valid bit position. */ - -#define TC0_CCCBV_bm 0x08 /* Compare or Capture C Buffer Valid bit mask. */ -#define TC0_CCCBV_bp 3 /* Compare or Capture C Buffer Valid bit position. */ - -#define TC0_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ -#define TC0_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ - -#define TC0_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ -#define TC0_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ - -#define TC0_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ -#define TC0_PERBV_bp 0 /* Period Buffer Valid bit position. */ - - -/* TC0.CTRLGSET bit masks and bit positions */ -/* TC0_CCDBV_bm Predefined. */ -/* TC0_CCDBV_bp Predefined. */ - -/* TC0_CCCBV_bm Predefined. */ -/* TC0_CCCBV_bp Predefined. */ - -/* TC0_CCBBV_bm Predefined. */ -/* TC0_CCBBV_bp Predefined. */ - -/* TC0_CCABV_bm Predefined. */ -/* TC0_CCABV_bp Predefined. */ - -/* TC0_PERBV_bm Predefined. */ -/* TC0_PERBV_bp Predefined. */ - - -/* TC0.INTFLAGS bit masks and bit positions */ -#define TC0_CCDIF_bm 0x80 /* Compare or Capture D Interrupt Flag bit mask. */ -#define TC0_CCDIF_bp 7 /* Compare or Capture D Interrupt Flag bit position. */ - -#define TC0_CCCIF_bm 0x40 /* Compare or Capture C Interrupt Flag bit mask. */ -#define TC0_CCCIF_bp 6 /* Compare or Capture C Interrupt Flag bit position. */ - -#define TC0_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ -#define TC0_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ - -#define TC0_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ -#define TC0_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ - -#define TC0_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ -#define TC0_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ - -#define TC0_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ -#define TC0_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ - - -/* TC1.CTRLA bit masks and bit positions */ -#define TC1_CLKSEL_gm 0x0F /* Clock Selection group mask. */ -#define TC1_CLKSEL_gp 0 /* Clock Selection group position. */ -#define TC1_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ -#define TC1_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ -#define TC1_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ -#define TC1_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ -#define TC1_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ -#define TC1_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ -#define TC1_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ -#define TC1_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ - - -/* TC1.CTRLB bit masks and bit positions */ -#define TC1_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ -#define TC1_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ - -#define TC1_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ -#define TC1_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ - -#define TC1_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ -#define TC1_WGMODE_gp 0 /* Waveform generation mode group position. */ -#define TC1_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ -#define TC1_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ -#define TC1_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ -#define TC1_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ -#define TC1_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ -#define TC1_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ - - -/* TC1.CTRLC bit masks and bit positions */ -#define TC1_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ -#define TC1_CMPB_bp 1 /* Compare B Output Value bit position. */ - -#define TC1_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ -#define TC1_CMPA_bp 0 /* Compare A Output Value bit position. */ - - -/* TC1.CTRLD bit masks and bit positions */ -#define TC1_EVACT_gm 0xE0 /* Event Action group mask. */ -#define TC1_EVACT_gp 5 /* Event Action group position. */ -#define TC1_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ -#define TC1_EVACT0_bp 5 /* Event Action bit 0 position. */ -#define TC1_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ -#define TC1_EVACT1_bp 6 /* Event Action bit 1 position. */ -#define TC1_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ -#define TC1_EVACT2_bp 7 /* Event Action bit 2 position. */ - -#define TC1_EVDLY_bm 0x10 /* Event Delay bit mask. */ -#define TC1_EVDLY_bp 4 /* Event Delay bit position. */ - -#define TC1_EVSEL_gm 0x0F /* Event Source Select group mask. */ -#define TC1_EVSEL_gp 0 /* Event Source Select group position. */ -#define TC1_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ -#define TC1_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ -#define TC1_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ -#define TC1_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ -#define TC1_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ -#define TC1_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ -#define TC1_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ -#define TC1_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ - - -/* TC1.CTRLE bit masks and bit positions */ -#define TC1_DTHM_bm 0x02 /* Dead Time Hold Mode bit mask. */ -#define TC1_DTHM_bp 1 /* Dead Time Hold Mode bit position. */ - -#define TC1_BYTEM_bm 0x01 /* Byte Mode bit mask. */ -#define TC1_BYTEM_bp 0 /* Byte Mode bit position. */ - - -/* TC1.INTCTRLA bit masks and bit positions */ -#define TC1_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ -#define TC1_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ -#define TC1_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ -#define TC1_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ -#define TC1_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ -#define TC1_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ - -#define TC1_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ -#define TC1_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ -#define TC1_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ -#define TC1_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ -#define TC1_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ -#define TC1_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ - - -/* TC1.INTCTRLB bit masks and bit positions */ -#define TC1_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ -#define TC1_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ -#define TC1_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ -#define TC1_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ -#define TC1_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ -#define TC1_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ - -#define TC1_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ -#define TC1_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ -#define TC1_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ -#define TC1_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ -#define TC1_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ -#define TC1_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ - - -/* TC1.CTRLFCLR bit masks and bit positions */ -#define TC1_CMD_gm 0x0C /* Command group mask. */ -#define TC1_CMD_gp 2 /* Command group position. */ -#define TC1_CMD0_bm (1<<2) /* Command bit 0 mask. */ -#define TC1_CMD0_bp 2 /* Command bit 0 position. */ -#define TC1_CMD1_bm (1<<3) /* Command bit 1 mask. */ -#define TC1_CMD1_bp 3 /* Command bit 1 position. */ - -#define TC1_LUPD_bm 0x02 /* Lock Update bit mask. */ -#define TC1_LUPD_bp 1 /* Lock Update bit position. */ - -#define TC1_DIR_bm 0x01 /* Direction bit mask. */ -#define TC1_DIR_bp 0 /* Direction bit position. */ - - -/* TC1.CTRLFSET bit masks and bit positions */ -/* TC1_CMD_gm Predefined. */ -/* TC1_CMD_gp Predefined. */ -/* TC1_CMD0_bm Predefined. */ -/* TC1_CMD0_bp Predefined. */ -/* TC1_CMD1_bm Predefined. */ -/* TC1_CMD1_bp Predefined. */ - -/* TC1_LUPD_bm Predefined. */ -/* TC1_LUPD_bp Predefined. */ - -/* TC1_DIR_bm Predefined. */ -/* TC1_DIR_bp Predefined. */ - - -/* TC1.CTRLGCLR bit masks and bit positions */ -#define TC1_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ -#define TC1_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ - -#define TC1_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ -#define TC1_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ - -#define TC1_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ -#define TC1_PERBV_bp 0 /* Period Buffer Valid bit position. */ - - -/* TC1.CTRLGSET bit masks and bit positions */ -/* TC1_CCBBV_bm Predefined. */ -/* TC1_CCBBV_bp Predefined. */ - -/* TC1_CCABV_bm Predefined. */ -/* TC1_CCABV_bp Predefined. */ - -/* TC1_PERBV_bm Predefined. */ -/* TC1_PERBV_bp Predefined. */ - - -/* TC1.INTFLAGS bit masks and bit positions */ -#define TC1_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ -#define TC1_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ - -#define TC1_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ -#define TC1_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ - -#define TC1_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ -#define TC1_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ - -#define TC1_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ -#define TC1_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ - - -/* AWEX.CTRL bit masks and bit positions */ -#define AWEX_PGM_bm 0x20 /* Pattern Generation Mode bit mask. */ -#define AWEX_PGM_bp 5 /* Pattern Generation Mode bit position. */ - -#define AWEX_CWCM_bm 0x10 /* Common Waveform Channel Mode bit mask. */ -#define AWEX_CWCM_bp 4 /* Common Waveform Channel Mode bit position. */ - -#define AWEX_DTICCDEN_bm 0x08 /* Dead Time Insertion Compare Channel D Enable bit mask. */ -#define AWEX_DTICCDEN_bp 3 /* Dead Time Insertion Compare Channel D Enable bit position. */ - -#define AWEX_DTICCCEN_bm 0x04 /* Dead Time Insertion Compare Channel C Enable bit mask. */ -#define AWEX_DTICCCEN_bp 2 /* Dead Time Insertion Compare Channel C Enable bit position. */ - -#define AWEX_DTICCBEN_bm 0x02 /* Dead Time Insertion Compare Channel B Enable bit mask. */ -#define AWEX_DTICCBEN_bp 1 /* Dead Time Insertion Compare Channel B Enable bit position. */ - -#define AWEX_DTICCAEN_bm 0x01 /* Dead Time Insertion Compare Channel A Enable bit mask. */ -#define AWEX_DTICCAEN_bp 0 /* Dead Time Insertion Compare Channel A Enable bit position. */ - - -/* AWEX.FDCTRL bit masks and bit positions */ -#define AWEX_FDDBD_bm 0x10 /* Fault Detect on Disable Break Disable bit mask. */ -#define AWEX_FDDBD_bp 4 /* Fault Detect on Disable Break Disable bit position. */ - -#define AWEX_FDMODE_bm 0x04 /* Fault Detect Mode bit mask. */ -#define AWEX_FDMODE_bp 2 /* Fault Detect Mode bit position. */ - -#define AWEX_FDACT_gm 0x03 /* Fault Detect Action group mask. */ -#define AWEX_FDACT_gp 0 /* Fault Detect Action group position. */ -#define AWEX_FDACT0_bm (1<<0) /* Fault Detect Action bit 0 mask. */ -#define AWEX_FDACT0_bp 0 /* Fault Detect Action bit 0 position. */ -#define AWEX_FDACT1_bm (1<<1) /* Fault Detect Action bit 1 mask. */ -#define AWEX_FDACT1_bp 1 /* Fault Detect Action bit 1 position. */ - - -/* AWEX.STATUS bit masks and bit positions */ -#define AWEX_FDF_bm 0x04 /* Fault Detect Flag bit mask. */ -#define AWEX_FDF_bp 2 /* Fault Detect Flag bit position. */ - -#define AWEX_DTHSBUFV_bm 0x02 /* Dead Time High Side Buffer Valid bit mask. */ -#define AWEX_DTHSBUFV_bp 1 /* Dead Time High Side Buffer Valid bit position. */ - -#define AWEX_DTLSBUFV_bm 0x01 /* Dead Time Low Side Buffer Valid bit mask. */ -#define AWEX_DTLSBUFV_bp 0 /* Dead Time Low Side Buffer Valid bit position. */ - - -/* HIRES.CTRL bit masks and bit positions */ -#define HIRES_HREN_gm 0x03 /* High Resolution Enable group mask. */ -#define HIRES_HREN_gp 0 /* High Resolution Enable group position. */ -#define HIRES_HREN0_bm (1<<0) /* High Resolution Enable bit 0 mask. */ -#define HIRES_HREN0_bp 0 /* High Resolution Enable bit 0 position. */ -#define HIRES_HREN1_bm (1<<1) /* High Resolution Enable bit 1 mask. */ -#define HIRES_HREN1_bp 1 /* High Resolution Enable bit 1 position. */ - - -/* USART - Universal Asynchronous Receiver-Transmitter */ -/* USART.STATUS bit masks and bit positions */ -#define USART_RXCIF_bm 0x80 /* Receive Interrupt Flag bit mask. */ -#define USART_RXCIF_bp 7 /* Receive Interrupt Flag bit position. */ - -#define USART_TXCIF_bm 0x40 /* Transmit Interrupt Flag bit mask. */ -#define USART_TXCIF_bp 6 /* Transmit Interrupt Flag bit position. */ - -#define USART_DREIF_bm 0x20 /* Data Register Empty Flag bit mask. */ -#define USART_DREIF_bp 5 /* Data Register Empty Flag bit position. */ - -#define USART_FERR_bm 0x10 /* Frame Error bit mask. */ -#define USART_FERR_bp 4 /* Frame Error bit position. */ - -#define USART_BUFOVF_bm 0x08 /* Buffer Overflow bit mask. */ -#define USART_BUFOVF_bp 3 /* Buffer Overflow bit position. */ - -#define USART_PERR_bm 0x04 /* Parity Error bit mask. */ -#define USART_PERR_bp 2 /* Parity Error bit position. */ - -#define USART_RXB8_bm 0x01 /* Receive Bit 8 bit mask. */ -#define USART_RXB8_bp 0 /* Receive Bit 8 bit position. */ - - -/* USART.CTRLA bit masks and bit positions */ -#define USART_RXCINTLVL_gm 0x30 /* Receive Interrupt Level group mask. */ -#define USART_RXCINTLVL_gp 4 /* Receive Interrupt Level group position. */ -#define USART_RXCINTLVL0_bm (1<<4) /* Receive Interrupt Level bit 0 mask. */ -#define USART_RXCINTLVL0_bp 4 /* Receive Interrupt Level bit 0 position. */ -#define USART_RXCINTLVL1_bm (1<<5) /* Receive Interrupt Level bit 1 mask. */ -#define USART_RXCINTLVL1_bp 5 /* Receive Interrupt Level bit 1 position. */ - -#define USART_TXCINTLVL_gm 0x0C /* Transmit Interrupt Level group mask. */ -#define USART_TXCINTLVL_gp 2 /* Transmit Interrupt Level group position. */ -#define USART_TXCINTLVL0_bm (1<<2) /* Transmit Interrupt Level bit 0 mask. */ -#define USART_TXCINTLVL0_bp 2 /* Transmit Interrupt Level bit 0 position. */ -#define USART_TXCINTLVL1_bm (1<<3) /* Transmit Interrupt Level bit 1 mask. */ -#define USART_TXCINTLVL1_bp 3 /* Transmit Interrupt Level bit 1 position. */ - -#define USART_DREINTLVL_gm 0x03 /* Data Register Empty Interrupt Level group mask. */ -#define USART_DREINTLVL_gp 0 /* Data Register Empty Interrupt Level group position. */ -#define USART_DREINTLVL0_bm (1<<0) /* Data Register Empty Interrupt Level bit 0 mask. */ -#define USART_DREINTLVL0_bp 0 /* Data Register Empty Interrupt Level bit 0 position. */ -#define USART_DREINTLVL1_bm (1<<1) /* Data Register Empty Interrupt Level bit 1 mask. */ -#define USART_DREINTLVL1_bp 1 /* Data Register Empty Interrupt Level bit 1 position. */ - - -/* USART.CTRLB bit masks and bit positions */ -#define USART_RXEN_bm 0x10 /* Receiver Enable bit mask. */ -#define USART_RXEN_bp 4 /* Receiver Enable bit position. */ - -#define USART_TXEN_bm 0x08 /* Transmitter Enable bit mask. */ -#define USART_TXEN_bp 3 /* Transmitter Enable bit position. */ - -#define USART_CLK2X_bm 0x04 /* Double transmission speed bit mask. */ -#define USART_CLK2X_bp 2 /* Double transmission speed bit position. */ - -#define USART_MPCM_bm 0x02 /* Multi-processor Communication Mode bit mask. */ -#define USART_MPCM_bp 1 /* Multi-processor Communication Mode bit position. */ - -#define USART_TXB8_bm 0x01 /* Transmit bit 8 bit mask. */ -#define USART_TXB8_bp 0 /* Transmit bit 8 bit position. */ - - -/* USART.CTRLC bit masks and bit positions */ -#define USART_CMODE_gm 0xC0 /* Communication Mode group mask. */ -#define USART_CMODE_gp 6 /* Communication Mode group position. */ -#define USART_CMODE0_bm (1<<6) /* Communication Mode bit 0 mask. */ -#define USART_CMODE0_bp 6 /* Communication Mode bit 0 position. */ -#define USART_CMODE1_bm (1<<7) /* Communication Mode bit 1 mask. */ -#define USART_CMODE1_bp 7 /* Communication Mode bit 1 position. */ - -#define USART_PMODE_gm 0x30 /* Parity Mode group mask. */ -#define USART_PMODE_gp 4 /* Parity Mode group position. */ -#define USART_PMODE0_bm (1<<4) /* Parity Mode bit 0 mask. */ -#define USART_PMODE0_bp 4 /* Parity Mode bit 0 position. */ -#define USART_PMODE1_bm (1<<5) /* Parity Mode bit 1 mask. */ -#define USART_PMODE1_bp 5 /* Parity Mode bit 1 position. */ - -#define USART_SBMODE_bm 0x08 /* Stop Bit Mode bit mask. */ -#define USART_SBMODE_bp 3 /* Stop Bit Mode bit position. */ - -#define USART_CHSIZE_gm 0x07 /* Character Size group mask. */ -#define USART_CHSIZE_gp 0 /* Character Size group position. */ -#define USART_CHSIZE0_bm (1<<0) /* Character Size bit 0 mask. */ -#define USART_CHSIZE0_bp 0 /* Character Size bit 0 position. */ -#define USART_CHSIZE1_bm (1<<1) /* Character Size bit 1 mask. */ -#define USART_CHSIZE1_bp 1 /* Character Size bit 1 position. */ -#define USART_CHSIZE2_bm (1<<2) /* Character Size bit 2 mask. */ -#define USART_CHSIZE2_bp 2 /* Character Size bit 2 position. */ - - -/* USART.BAUDCTRLA bit masks and bit positions */ -#define USART_BSEL_gm 0xFF /* Baud Rate Selection Bits [7:0] group mask. */ -#define USART_BSEL_gp 0 /* Baud Rate Selection Bits [7:0] group position. */ -#define USART_BSEL0_bm (1<<0) /* Baud Rate Selection Bits [7:0] bit 0 mask. */ -#define USART_BSEL0_bp 0 /* Baud Rate Selection Bits [7:0] bit 0 position. */ -#define USART_BSEL1_bm (1<<1) /* Baud Rate Selection Bits [7:0] bit 1 mask. */ -#define USART_BSEL1_bp 1 /* Baud Rate Selection Bits [7:0] bit 1 position. */ -#define USART_BSEL2_bm (1<<2) /* Baud Rate Selection Bits [7:0] bit 2 mask. */ -#define USART_BSEL2_bp 2 /* Baud Rate Selection Bits [7:0] bit 2 position. */ -#define USART_BSEL3_bm (1<<3) /* Baud Rate Selection Bits [7:0] bit 3 mask. */ -#define USART_BSEL3_bp 3 /* Baud Rate Selection Bits [7:0] bit 3 position. */ -#define USART_BSEL4_bm (1<<4) /* Baud Rate Selection Bits [7:0] bit 4 mask. */ -#define USART_BSEL4_bp 4 /* Baud Rate Selection Bits [7:0] bit 4 position. */ -#define USART_BSEL5_bm (1<<5) /* Baud Rate Selection Bits [7:0] bit 5 mask. */ -#define USART_BSEL5_bp 5 /* Baud Rate Selection Bits [7:0] bit 5 position. */ -#define USART_BSEL6_bm (1<<6) /* Baud Rate Selection Bits [7:0] bit 6 mask. */ -#define USART_BSEL6_bp 6 /* Baud Rate Selection Bits [7:0] bit 6 position. */ -#define USART_BSEL7_bm (1<<7) /* Baud Rate Selection Bits [7:0] bit 7 mask. */ -#define USART_BSEL7_bp 7 /* Baud Rate Selection Bits [7:0] bit 7 position. */ - - -/* USART.BAUDCTRLB bit masks and bit positions */ -#define USART_BSCALE_gm 0xF0 /* Baud Rate Scale group mask. */ -#define USART_BSCALE_gp 4 /* Baud Rate Scale group position. */ -#define USART_BSCALE0_bm (1<<4) /* Baud Rate Scale bit 0 mask. */ -#define USART_BSCALE0_bp 4 /* Baud Rate Scale bit 0 position. */ -#define USART_BSCALE1_bm (1<<5) /* Baud Rate Scale bit 1 mask. */ -#define USART_BSCALE1_bp 5 /* Baud Rate Scale bit 1 position. */ -#define USART_BSCALE2_bm (1<<6) /* Baud Rate Scale bit 2 mask. */ -#define USART_BSCALE2_bp 6 /* Baud Rate Scale bit 2 position. */ -#define USART_BSCALE3_bm (1<<7) /* Baud Rate Scale bit 3 mask. */ -#define USART_BSCALE3_bp 7 /* Baud Rate Scale bit 3 position. */ - -/* USART_BSEL_gm Predefined. */ -/* USART_BSEL_gp Predefined. */ -/* USART_BSEL0_bm Predefined. */ -/* USART_BSEL0_bp Predefined. */ -/* USART_BSEL1_bm Predefined. */ -/* USART_BSEL1_bp Predefined. */ -/* USART_BSEL2_bm Predefined. */ -/* USART_BSEL2_bp Predefined. */ -/* USART_BSEL3_bm Predefined. */ -/* USART_BSEL3_bp Predefined. */ - - -/* SPI - Serial Peripheral Interface */ -/* SPI.CTRL bit masks and bit positions */ -#define SPI_CLK2X_bm 0x80 /* Enable Double Speed bit mask. */ -#define SPI_CLK2X_bp 7 /* Enable Double Speed bit position. */ - -#define SPI_ENABLE_bm 0x40 /* Enable Module bit mask. */ -#define SPI_ENABLE_bp 6 /* Enable Module bit position. */ - -#define SPI_DORD_bm 0x20 /* Data Order Setting bit mask. */ -#define SPI_DORD_bp 5 /* Data Order Setting bit position. */ - -#define SPI_MASTER_bm 0x10 /* Master Operation Enable bit mask. */ -#define SPI_MASTER_bp 4 /* Master Operation Enable bit position. */ - -#define SPI_MODE_gm 0x0C /* SPI Mode group mask. */ -#define SPI_MODE_gp 2 /* SPI Mode group position. */ -#define SPI_MODE0_bm (1<<2) /* SPI Mode bit 0 mask. */ -#define SPI_MODE0_bp 2 /* SPI Mode bit 0 position. */ -#define SPI_MODE1_bm (1<<3) /* SPI Mode bit 1 mask. */ -#define SPI_MODE1_bp 3 /* SPI Mode bit 1 position. */ - -#define SPI_PRESCALER_gm 0x03 /* Prescaler group mask. */ -#define SPI_PRESCALER_gp 0 /* Prescaler group position. */ -#define SPI_PRESCALER0_bm (1<<0) /* Prescaler bit 0 mask. */ -#define SPI_PRESCALER0_bp 0 /* Prescaler bit 0 position. */ -#define SPI_PRESCALER1_bm (1<<1) /* Prescaler bit 1 mask. */ -#define SPI_PRESCALER1_bp 1 /* Prescaler bit 1 position. */ - - -/* SPI.INTCTRL bit masks and bit positions */ -#define SPI_INTLVL_gm 0x03 /* Interrupt level group mask. */ -#define SPI_INTLVL_gp 0 /* Interrupt level group position. */ -#define SPI_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */ -#define SPI_INTLVL0_bp 0 /* Interrupt level bit 0 position. */ -#define SPI_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */ -#define SPI_INTLVL1_bp 1 /* Interrupt level bit 1 position. */ - - -/* SPI.STATUS bit masks and bit positions */ -#define SPI_IF_bm 0x80 /* Interrupt Flag bit mask. */ -#define SPI_IF_bp 7 /* Interrupt Flag bit position. */ - -#define SPI_WRCOL_bm 0x40 /* Write Collision bit mask. */ -#define SPI_WRCOL_bp 6 /* Write Collision bit position. */ - - -/* IRCOM - IR Communication Module */ -/* IRCOM.CTRL bit masks and bit positions */ -#define IRCOM_EVSEL_gm 0x0F /* Event Channel Select group mask. */ -#define IRCOM_EVSEL_gp 0 /* Event Channel Select group position. */ -#define IRCOM_EVSEL0_bm (1<<0) /* Event Channel Select bit 0 mask. */ -#define IRCOM_EVSEL0_bp 0 /* Event Channel Select bit 0 position. */ -#define IRCOM_EVSEL1_bm (1<<1) /* Event Channel Select bit 1 mask. */ -#define IRCOM_EVSEL1_bp 1 /* Event Channel Select bit 1 position. */ -#define IRCOM_EVSEL2_bm (1<<2) /* Event Channel Select bit 2 mask. */ -#define IRCOM_EVSEL2_bp 2 /* Event Channel Select bit 2 position. */ -#define IRCOM_EVSEL3_bm (1<<3) /* Event Channel Select bit 3 mask. */ -#define IRCOM_EVSEL3_bp 3 /* Event Channel Select bit 3 position. */ - - -/* AES - AES Module */ -/* AES.CTRL bit masks and bit positions */ -#define AES_START_bm 0x80 /* Start/Run bit mask. */ -#define AES_START_bp 7 /* Start/Run bit position. */ - -#define AES_AUTO_bm 0x40 /* Auto Start Trigger bit mask. */ -#define AES_AUTO_bp 6 /* Auto Start Trigger bit position. */ - -#define AES_RESET_bm 0x20 /* AES Software Reset bit mask. */ -#define AES_RESET_bp 5 /* AES Software Reset bit position. */ - -#define AES_DECRYPT_bm 0x10 /* Decryption / Direction bit mask. */ -#define AES_DECRYPT_bp 4 /* Decryption / Direction bit position. */ - -#define AES_XOR_bm 0x04 /* State XOR Load Enable bit mask. */ -#define AES_XOR_bp 2 /* State XOR Load Enable bit position. */ - - -/* AES.STATUS bit masks and bit positions */ -#define AES_ERROR_bm 0x80 /* AES Error bit mask. */ -#define AES_ERROR_bp 7 /* AES Error bit position. */ - -#define AES_SRIF_bm 0x01 /* State Ready Interrupt Flag bit mask. */ -#define AES_SRIF_bp 0 /* State Ready Interrupt Flag bit position. */ - - -/* AES.INTCTRL bit masks and bit positions */ -#define AES_INTLVL_gm 0x03 /* Interrupt level group mask. */ -#define AES_INTLVL_gp 0 /* Interrupt level group position. */ -#define AES_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */ -#define AES_INTLVL0_bp 0 /* Interrupt level bit 0 position. */ -#define AES_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */ -#define AES_INTLVL1_bp 1 /* Interrupt level bit 1 position. */ - - - -// Generic Port Pins - -#define PIN0_bm 0x01 -#define PIN0_bp 0 -#define PIN1_bm 0x02 -#define PIN1_bp 1 -#define PIN2_bm 0x04 -#define PIN2_bp 2 -#define PIN3_bm 0x08 -#define PIN3_bp 3 -#define PIN4_bm 0x10 -#define PIN4_bp 4 -#define PIN5_bm 0x20 -#define PIN5_bp 5 -#define PIN6_bm 0x40 -#define PIN6_bp 6 -#define PIN7_bm 0x80 -#define PIN7_bp 7 - - -/* ========== Interrupt Vector Definitions ========== */ -/* Vector 0 is the reset vector */ - -/* OSC interrupt vectors */ -#define OSC_XOSCF_vect_num 1 -#define OSC_XOSCF_vect _VECTOR(1) /* External Oscillator Failure Interrupt (NMI) */ - -/* PORTC interrupt vectors */ -#define PORTC_INT0_vect_num 2 -#define PORTC_INT0_vect _VECTOR(2) /* External Interrupt 0 */ -#define PORTC_INT1_vect_num 3 -#define PORTC_INT1_vect _VECTOR(3) /* External Interrupt 1 */ - -/* PORTR interrupt vectors */ -#define PORTR_INT0_vect_num 4 -#define PORTR_INT0_vect _VECTOR(4) /* External Interrupt 0 */ -#define PORTR_INT1_vect_num 5 -#define PORTR_INT1_vect _VECTOR(5) /* External Interrupt 1 */ - -/* DMA interrupt vectors */ -#define DMA_CH0_vect_num 6 -#define DMA_CH0_vect _VECTOR(6) /* Channel 0 Interrupt */ -#define DMA_CH1_vect_num 7 -#define DMA_CH1_vect _VECTOR(7) /* Channel 1 Interrupt */ -#define DMA_CH2_vect_num 8 -#define DMA_CH2_vect _VECTOR(8) /* Channel 2 Interrupt */ -#define DMA_CH3_vect_num 9 -#define DMA_CH3_vect _VECTOR(9) /* Channel 3 Interrupt */ - -/* RTC interrupt vectors */ -#define RTC_OVF_vect_num 10 -#define RTC_OVF_vect _VECTOR(10) /* Overflow Interrupt */ -#define RTC_COMP_vect_num 11 -#define RTC_COMP_vect _VECTOR(11) /* Compare Interrupt */ - -/* TWIC interrupt vectors */ -#define TWIC_TWIS_vect_num 12 -#define TWIC_TWIS_vect _VECTOR(12) /* TWI Slave Interrupt */ -#define TWIC_TWIM_vect_num 13 -#define TWIC_TWIM_vect _VECTOR(13) /* TWI Master Interrupt */ - -/* TCC0 interrupt vectors */ -#define TCC0_OVF_vect_num 14 -#define TCC0_OVF_vect _VECTOR(14) /* Overflow Interrupt */ -#define TCC0_ERR_vect_num 15 -#define TCC0_ERR_vect _VECTOR(15) /* Error Interrupt */ -#define TCC0_CCA_vect_num 16 -#define TCC0_CCA_vect _VECTOR(16) /* Compare or Capture A Interrupt */ -#define TCC0_CCB_vect_num 17 -#define TCC0_CCB_vect _VECTOR(17) /* Compare or Capture B Interrupt */ -#define TCC0_CCC_vect_num 18 -#define TCC0_CCC_vect _VECTOR(18) /* Compare or Capture C Interrupt */ -#define TCC0_CCD_vect_num 19 -#define TCC0_CCD_vect _VECTOR(19) /* Compare or Capture D Interrupt */ - -/* TCC1 interrupt vectors */ -#define TCC1_OVF_vect_num 20 -#define TCC1_OVF_vect _VECTOR(20) /* Overflow Interrupt */ -#define TCC1_ERR_vect_num 21 -#define TCC1_ERR_vect _VECTOR(21) /* Error Interrupt */ -#define TCC1_CCA_vect_num 22 -#define TCC1_CCA_vect _VECTOR(22) /* Compare or Capture A Interrupt */ -#define TCC1_CCB_vect_num 23 -#define TCC1_CCB_vect _VECTOR(23) /* Compare or Capture B Interrupt */ - -/* SPIC interrupt vectors */ -#define SPIC_INT_vect_num 24 -#define SPIC_INT_vect _VECTOR(24) /* SPI Interrupt */ - -/* USARTC0 interrupt vectors */ -#define USARTC0_RXC_vect_num 25 -#define USARTC0_RXC_vect _VECTOR(25) /* Reception Complete Interrupt */ -#define USARTC0_DRE_vect_num 26 -#define USARTC0_DRE_vect _VECTOR(26) /* Data Register Empty Interrupt */ -#define USARTC0_TXC_vect_num 27 -#define USARTC0_TXC_vect _VECTOR(27) /* Transmission Complete Interrupt */ - -/* USARTC1 interrupt vectors */ -#define USARTC1_RXC_vect_num 28 -#define USARTC1_RXC_vect _VECTOR(28) /* Reception Complete Interrupt */ -#define USARTC1_DRE_vect_num 29 -#define USARTC1_DRE_vect _VECTOR(29) /* Data Register Empty Interrupt */ -#define USARTC1_TXC_vect_num 30 -#define USARTC1_TXC_vect _VECTOR(30) /* Transmission Complete Interrupt */ - -/* AES interrupt vectors */ -#define AES_INT_vect_num 31 -#define AES_INT_vect _VECTOR(31) /* AES Interrupt */ - -/* NVM interrupt vectors */ -#define NVM_EE_vect_num 32 -#define NVM_EE_vect _VECTOR(32) /* EE Interrupt */ -#define NVM_SPM_vect_num 33 -#define NVM_SPM_vect _VECTOR(33) /* SPM Interrupt */ - -/* PORTB interrupt vectors */ -#define PORTB_INT0_vect_num 34 -#define PORTB_INT0_vect _VECTOR(34) /* External Interrupt 0 */ -#define PORTB_INT1_vect_num 35 -#define PORTB_INT1_vect _VECTOR(35) /* External Interrupt 1 */ - -/* PORTE interrupt vectors */ -#define PORTE_INT0_vect_num 43 -#define PORTE_INT0_vect _VECTOR(43) /* External Interrupt 0 */ -#define PORTE_INT1_vect_num 44 -#define PORTE_INT1_vect _VECTOR(44) /* External Interrupt 1 */ - -/* TWIE interrupt vectors */ -#define TWIE_TWIS_vect_num 45 -#define TWIE_TWIS_vect _VECTOR(45) /* TWI Slave Interrupt */ -#define TWIE_TWIM_vect_num 46 -#define TWIE_TWIM_vect _VECTOR(46) /* TWI Master Interrupt */ - -/* TCE0 interrupt vectors */ -#define TCE0_OVF_vect_num 47 -#define TCE0_OVF_vect _VECTOR(47) /* Overflow Interrupt */ -#define TCE0_ERR_vect_num 48 -#define TCE0_ERR_vect _VECTOR(48) /* Error Interrupt */ -#define TCE0_CCA_vect_num 49 -#define TCE0_CCA_vect _VECTOR(49) /* Compare or Capture A Interrupt */ -#define TCE0_CCB_vect_num 50 -#define TCE0_CCB_vect _VECTOR(50) /* Compare or Capture B Interrupt */ -#define TCE0_CCC_vect_num 51 -#define TCE0_CCC_vect _VECTOR(51) /* Compare or Capture C Interrupt */ -#define TCE0_CCD_vect_num 52 -#define TCE0_CCD_vect _VECTOR(52) /* Compare or Capture D Interrupt */ - -/* TCE1 interrupt vectors */ -#define TCE1_OVF_vect_num 53 -#define TCE1_OVF_vect _VECTOR(53) /* Overflow Interrupt */ -#define TCE1_ERR_vect_num 54 -#define TCE1_ERR_vect _VECTOR(54) /* Error Interrupt */ -#define TCE1_CCA_vect_num 55 -#define TCE1_CCA_vect _VECTOR(55) /* Compare or Capture A Interrupt */ -#define TCE1_CCB_vect_num 56 -#define TCE1_CCB_vect _VECTOR(56) /* Compare or Capture B Interrupt */ - -/* USARTE0 interrupt vectors */ -#define USARTE0_RXC_vect_num 58 -#define USARTE0_RXC_vect _VECTOR(58) /* Reception Complete Interrupt */ -#define USARTE0_DRE_vect_num 59 -#define USARTE0_DRE_vect _VECTOR(59) /* Data Register Empty Interrupt */ -#define USARTE0_TXC_vect_num 60 -#define USARTE0_TXC_vect _VECTOR(60) /* Transmission Complete Interrupt */ - -/* PORTD interrupt vectors */ -#define PORTD_INT0_vect_num 64 -#define PORTD_INT0_vect _VECTOR(64) /* External Interrupt 0 */ -#define PORTD_INT1_vect_num 65 -#define PORTD_INT1_vect _VECTOR(65) /* External Interrupt 1 */ - -/* PORTA interrupt vectors */ -#define PORTA_INT0_vect_num 66 -#define PORTA_INT0_vect _VECTOR(66) /* External Interrupt 0 */ -#define PORTA_INT1_vect_num 67 -#define PORTA_INT1_vect _VECTOR(67) /* External Interrupt 1 */ - -/* ACA interrupt vectors */ -#define ACA_AC0_vect_num 68 -#define ACA_AC0_vect _VECTOR(68) /* AC0 Interrupt */ -#define ACA_AC1_vect_num 69 -#define ACA_AC1_vect _VECTOR(69) /* AC1 Interrupt */ -#define ACA_ACW_vect_num 70 -#define ACA_ACW_vect _VECTOR(70) /* ACW Window Mode Interrupt */ - -/* ADCA interrupt vectors */ -#define ADCA_CH0_vect_num 71 -#define ADCA_CH0_vect _VECTOR(71) /* Interrupt 0 */ -#define ADCA_CH1_vect_num 72 -#define ADCA_CH1_vect _VECTOR(72) /* Interrupt 1 */ -#define ADCA_CH2_vect_num 73 -#define ADCA_CH2_vect _VECTOR(73) /* Interrupt 2 */ -#define ADCA_CH3_vect_num 74 -#define ADCA_CH3_vect _VECTOR(74) /* Interrupt 3 */ - -/* TCD0 interrupt vectors */ -#define TCD0_OVF_vect_num 77 -#define TCD0_OVF_vect _VECTOR(77) /* Overflow Interrupt */ -#define TCD0_ERR_vect_num 78 -#define TCD0_ERR_vect _VECTOR(78) /* Error Interrupt */ -#define TCD0_CCA_vect_num 79 -#define TCD0_CCA_vect _VECTOR(79) /* Compare or Capture A Interrupt */ -#define TCD0_CCB_vect_num 80 -#define TCD0_CCB_vect _VECTOR(80) /* Compare or Capture B Interrupt */ -#define TCD0_CCC_vect_num 81 -#define TCD0_CCC_vect _VECTOR(81) /* Compare or Capture C Interrupt */ -#define TCD0_CCD_vect_num 82 -#define TCD0_CCD_vect _VECTOR(82) /* Compare or Capture D Interrupt */ - -/* TCD1 interrupt vectors */ -#define TCD1_OVF_vect_num 83 -#define TCD1_OVF_vect _VECTOR(83) /* Overflow Interrupt */ -#define TCD1_ERR_vect_num 84 -#define TCD1_ERR_vect _VECTOR(84) /* Error Interrupt */ -#define TCD1_CCA_vect_num 85 -#define TCD1_CCA_vect _VECTOR(85) /* Compare or Capture A Interrupt */ -#define TCD1_CCB_vect_num 86 -#define TCD1_CCB_vect _VECTOR(86) /* Compare or Capture B Interrupt */ - -/* SPID interrupt vectors */ -#define SPID_INT_vect_num 87 -#define SPID_INT_vect _VECTOR(87) /* SPI Interrupt */ - -/* USARTD0 interrupt vectors */ -#define USARTD0_RXC_vect_num 88 -#define USARTD0_RXC_vect _VECTOR(88) /* Reception Complete Interrupt */ -#define USARTD0_DRE_vect_num 89 -#define USARTD0_DRE_vect _VECTOR(89) /* Data Register Empty Interrupt */ -#define USARTD0_TXC_vect_num 90 -#define USARTD0_TXC_vect _VECTOR(90) /* Transmission Complete Interrupt */ - -/* USARTD1 interrupt vectors */ -#define USARTD1_RXC_vect_num 91 -#define USARTD1_RXC_vect _VECTOR(91) /* Reception Complete Interrupt */ -#define USARTD1_DRE_vect_num 92 -#define USARTD1_DRE_vect _VECTOR(92) /* Data Register Empty Interrupt */ -#define USARTD1_TXC_vect_num 93 -#define USARTD1_TXC_vect _VECTOR(93) /* Transmission Complete Interrupt */ - - -#define _VECTOR_SIZE 4 /* Size of individual vector. */ -#define _VECTORS_SIZE (94 * _VECTOR_SIZE) - - -/* ========== Constants ========== */ - -#define PROGMEM_START (0x0000) -#define PROGMEM_SIZE (36864) -#define PROGMEM_PAGE_SIZE (256) -#define PROGMEM_END (PROGMEM_START + PROGMEM_SIZE - 1) - -#define APP_SECTION_START (0x0000) -#define APP_SECTION_SIZE (32768) -#define APP_SECTION_PAGE_SIZE (256) -#define APP_SECTION_END (APP_SECTION_START + APP_SECTION_SIZE - 1) - -#define APPTABLE_SECTION_START (0x07000) -#define APPTABLE_SECTION_SIZE (4096) -#define APPTABLE_SECTION_PAGE_SIZE (256) -#define APPTABLE_SECTION_END (APPTABLE_SECTION_START + APPTABLE_SECTION_SIZE - 1) - -#define BOOT_SECTION_START (0x8000) -#define BOOT_SECTION_SIZE (4096) -#define BOOT_SECTION_PAGE_SIZE (256) -#define BOOT_SECTION_END (BOOT_SECTION_START + BOOT_SECTION_SIZE - 1) - -#define DATAMEM_START (0x0000) -#define DATAMEM_SIZE (12288) -#define DATAMEM_PAGE_SIZE (0) -#define DATAMEM_END (DATAMEM_START + DATAMEM_SIZE - 1) - -#define IO_START (0x0000) -#define IO_SIZE (4096) -#define IO_PAGE_SIZE (0) -#define IO_END (IO_START + IO_SIZE - 1) - -#define MAPPED_EEPROM_START (0x1000) -#define MAPPED_EEPROM_SIZE (1024) -#define MAPPED_EEPROM_PAGE_SIZE (0) -#define MAPPED_EEPROM_END (MAPPED_EEPROM_START + MAPPED_EEPROM_SIZE - 1) - -#define INTERNAL_SRAM_START (0x2000) -#define INTERNAL_SRAM_SIZE (4096) -#define INTERNAL_SRAM_PAGE_SIZE (0) -#define INTERNAL_SRAM_END (INTERNAL_SRAM_START + INTERNAL_SRAM_SIZE - 1) - -#define EEPROM_START (0x0000) -#define EEPROM_SIZE (1024) -#define EEPROM_PAGE_SIZE (32) -#define EEPROM_END (EEPROM_START + EEPROM_SIZE - 1) - -#define FUSE_START (0x0000) -#define FUSE_SIZE (6) -#define FUSE_PAGE_SIZE (0) -#define FUSE_END (FUSE_START + FUSE_SIZE - 1) - -#define LOCKBIT_START (0x0000) -#define LOCKBIT_SIZE (1) -#define LOCKBIT_PAGE_SIZE (0) -#define LOCKBIT_END (LOCKBIT_START + LOCKBIT_SIZE - 1) - -#define SIGNATURES_START (0x0000) -#define SIGNATURES_SIZE (3) -#define SIGNATURES_PAGE_SIZE (0) -#define SIGNATURES_END (SIGNATURES_START + SIGNATURES_SIZE - 1) - -#define USER_SIGNATURES_START (0x0000) -#define USER_SIGNATURES_SIZE (256) -#define USER_SIGNATURES_PAGE_SIZE (0) -#define USER_SIGNATURES_END (USER_SIGNATURES_START + USER_SIGNATURES_SIZE - 1) - -#define PROD_SIGNATURES_START (0x0000) -#define PROD_SIGNATURES_SIZE (52) -#define PROD_SIGNATURES_PAGE_SIZE (0) -#define PROD_SIGNATURES_END (PROD_SIGNATURES_START + PROD_SIGNATURES_SIZE - 1) - -#define FLASHEND PROGMEM_END -#define SPM_PAGESIZE PROGMEM_PAGE_SIZE -#define RAMSTART INTERNAL_SRAM_START -#define RAMSIZE INTERNAL_SRAM_SIZE -#define RAMEND INTERNAL_SRAM_END -#define XRAMSTART EXTERNAL_SRAM_START -#define XRAMSIZE EXTERNAL_SRAM_SIZE -#define XRAMEND INTERNAL_SRAM_END -#define E2END EEPROM_END -#define E2PAGESIZE EEPROM_PAGE_SIZE - - -/* ========== Fuses ========== */ -#define FUSE_MEMORY_SIZE 6 - -/* Fuse Byte 0 */ -#define FUSE_USERID0 (unsigned char)~_BV(0) /* User ID Bit 0 */ -#define FUSE_USERID1 (unsigned char)~_BV(1) /* User ID Bit 1 */ -#define FUSE_USERID2 (unsigned char)~_BV(2) /* User ID Bit 2 */ -#define FUSE_USERID3 (unsigned char)~_BV(3) /* User ID Bit 3 */ -#define FUSE_USERID4 (unsigned char)~_BV(4) /* User ID Bit 4 */ -#define FUSE_USERID5 (unsigned char)~_BV(5) /* User ID Bit 5 */ -#define FUSE_USERID6 (unsigned char)~_BV(6) /* User ID Bit 6 */ -#define FUSE_USERID7 (unsigned char)~_BV(7) /* User ID Bit 7 */ -#define FUSE0_DEFAULT (0xFF) - -/* Fuse Byte 1 */ -#define FUSE_WDP0 (unsigned char)~_BV(0) /* Watchdog Timeout Period Bit 0 */ -#define FUSE_WDP1 (unsigned char)~_BV(1) /* Watchdog Timeout Period Bit 1 */ -#define FUSE_WDP2 (unsigned char)~_BV(2) /* Watchdog Timeout Period Bit 2 */ -#define FUSE_WDP3 (unsigned char)~_BV(3) /* Watchdog Timeout Period Bit 3 */ -#define FUSE_WDWP0 (unsigned char)~_BV(4) /* Watchdog Window Timeout Period Bit 0 */ -#define FUSE_WDWP1 (unsigned char)~_BV(5) /* Watchdog Window Timeout Period Bit 1 */ -#define FUSE_WDWP2 (unsigned char)~_BV(6) /* Watchdog Window Timeout Period Bit 2 */ -#define FUSE_WDWP3 (unsigned char)~_BV(7) /* Watchdog Window Timeout Period Bit 3 */ -#define FUSE1_DEFAULT (0xFF) - -/* Fuse Byte 2 */ -#define FUSE_BODPD0 (unsigned char)~_BV(0) /* BOD Operation in Power-Down Mode Bit 0 */ -#define FUSE_BODPD1 (unsigned char)~_BV(1) /* BOD Operation in Power-Down Mode Bit 1 */ -#define FUSE_BOOTRST (unsigned char)~_BV(6) /* Boot Loader Section Reset Vector */ -#define FUSE_DVSDON (unsigned char)~_BV(7) /* Spike Detector Enable */ -#define FUSE2_DEFAULT (0xFF) - -/* Fuse Byte 3 Reserved */ - -/* Fuse Byte 4 */ -#define FUSE_WDLOCK (unsigned char)~_BV(1) /* Watchdog Timer Lock */ -#define FUSE_SUT0 (unsigned char)~_BV(2) /* Start-up Time Bit 0 */ -#define FUSE_SUT1 (unsigned char)~_BV(3) /* Start-up Time Bit 1 */ -#define FUSE4_DEFAULT (0xFF) - -/* Fuse Byte 5 */ -#define FUSE_BODLVL0 (unsigned char)~_BV(0) /* Brown Out Detection Voltage Level Bit 0 */ -#define FUSE_BODLVL1 (unsigned char)~_BV(1) /* Brown Out Detection Voltage Level Bit 1 */ -#define FUSE_BODLVL2 (unsigned char)~_BV(2) /* Brown Out Detection Voltage Level Bit 2 */ -#define FUSE_EESAVE (unsigned char)~_BV(3) /* Preserve EEPROM Through Chip Erase */ -#define FUSE_BODACT0 (unsigned char)~_BV(4) /* BOD Operation in Active Mode Bit 0 */ -#define FUSE_BODACT1 (unsigned char)~_BV(5) /* BOD Operation in Active Mode Bit 1 */ -#define FUSE5_DEFAULT (0xFF) - - -/* ========== Lock Bits ========== */ -#define __LOCK_BITS_EXIST -#define __BOOT_LOCK_APPLICATION_TABLE_BITS_EXIST -#define __BOOT_LOCK_APPLICATION_BITS_EXIST -#define __BOOT_LOCK_BOOT_BITS_EXIST - - -/* ========== Signature ========== */ -#define SIGNATURE_0 0x1E -#define SIGNATURE_1 0x95 -#define SIGNATURE_2 0x41 - -/* ========== Power Reduction Condition Definitions ========== */ - -/* PR.PRGEN */ -#define __AVR_HAVE_PRGEN (PR_AES_bm|PR_EBI_bm|PR_RTC_bm|PR_EVSYS_bm|PR_DMA_bm) -#define __AVR_HAVE_PRGEN_AES -#define __AVR_HAVE_PRGEN_EBI -#define __AVR_HAVE_PRGEN_RTC -#define __AVR_HAVE_PRGEN_EVSYS -#define __AVR_HAVE_PRGEN_DMA - -/* PR.PRPA */ -#define __AVR_HAVE_PRPA (PR_DAC_bm|PR_ADC_bm|PR_AC_bm) -#define __AVR_HAVE_PRPA_DAC -#define __AVR_HAVE_PRPA_ADC -#define __AVR_HAVE_PRPA_AC - -/* PR.PRPB */ -#define __AVR_HAVE_PRPB (PR_DAC_bm|PR_ADC_bm|PR_AC_bm) -#define __AVR_HAVE_PRPB_DAC -#define __AVR_HAVE_PRPB_ADC -#define __AVR_HAVE_PRPB_AC - -/* PR.PRPC */ -#define __AVR_HAVE_PRPC (PR_TWI_bm|PR_USART1_bm|PR_USART0_bm|PR_SPI_bm|PR_HIRES_bm|PR_TC1_bm|PR_TC0_bm) -#define __AVR_HAVE_PRPC_TWI -#define __AVR_HAVE_PRPC_USART1 -#define __AVR_HAVE_PRPC_USART0 -#define __AVR_HAVE_PRPC_SPI -#define __AVR_HAVE_PRPC_HIRES -#define __AVR_HAVE_PRPC_TC1 -#define __AVR_HAVE_PRPC_TC0 - -/* PR.PRPD */ -#define __AVR_HAVE_PRPD (PR_TWI_bm|PR_USART1_bm|PR_USART0_bm|PR_SPI_bm|PR_HIRES_bm|PR_TC1_bm|PR_TC0_bm) -#define __AVR_HAVE_PRPD_TWI -#define __AVR_HAVE_PRPD_USART1 -#define __AVR_HAVE_PRPD_USART0 -#define __AVR_HAVE_PRPD_SPI -#define __AVR_HAVE_PRPD_HIRES -#define __AVR_HAVE_PRPD_TC1 -#define __AVR_HAVE_PRPD_TC0 - -/* PR.PRPE */ -#define __AVR_HAVE_PRPE (PR_TWI_bm|PR_USART1_bm|PR_USART0_bm|PR_SPI_bm|PR_HIRES_bm|PR_TC1_bm|PR_TC0_bm) -#define __AVR_HAVE_PRPE_TWI -#define __AVR_HAVE_PRPE_USART1 -#define __AVR_HAVE_PRPE_USART0 -#define __AVR_HAVE_PRPE_SPI -#define __AVR_HAVE_PRPE_HIRES -#define __AVR_HAVE_PRPE_TC1 -#define __AVR_HAVE_PRPE_TC0 - -/* PR.PRPF */ -#define __AVR_HAVE_PRPF (PR_TWI_bm|PR_USART1_bm|PR_USART0_bm|PR_SPI_bm|PR_HIRES_bm|PR_TC1_bm|PR_TC0_bm) -#define __AVR_HAVE_PRPF_TWI -#define __AVR_HAVE_PRPF_USART1 -#define __AVR_HAVE_PRPF_USART0 -#define __AVR_HAVE_PRPF_SPI -#define __AVR_HAVE_PRPF_HIRES -#define __AVR_HAVE_PRPF_TC1 -#define __AVR_HAVE_PRPF_TC0 - - -#endif /* _AVR_ATxmega32A4_H_ */ - diff --git a/arduino/hardware/tools/avr/avr/include/avr/iox32a4u.h b/arduino/hardware/tools/avr/avr/include/avr/iox32a4u.h deleted file mode 100644 index b74fa59..0000000 --- a/arduino/hardware/tools/avr/avr/include/avr/iox32a4u.h +++ /dev/null @@ -1,7309 +0,0 @@ -/***************************************************************************** - * - * Copyright (C) 2015 Atmel Corporation - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * - * * Neither the name of the copyright holders nor the names of - * contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - ****************************************************************************/ - - -#ifndef _AVR_IO_H_ -# error "Include instead of this file." -#endif - -#ifndef _AVR_IOXXX_H_ -# define _AVR_IOXXX_H_ "iox32a4u.h" -#else -# error "Attempt to include more than one file." -#endif - -#ifndef _AVR_ATXMEGA32A4U_H_INCLUDED -#define _AVR_ATXMEGA32A4U_H_INCLUDED - -/* Ungrouped common registers */ -#define GPIOR0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ -#define GPIOR1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ -#define GPIOR2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ -#define GPIOR3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ -#define GPIOR4 _SFR_MEM8(0x0004) /* General Purpose IO Register 4 */ -#define GPIOR5 _SFR_MEM8(0x0005) /* General Purpose IO Register 5 */ -#define GPIOR6 _SFR_MEM8(0x0006) /* General Purpose IO Register 6 */ -#define GPIOR7 _SFR_MEM8(0x0007) /* General Purpose IO Register 7 */ -#define GPIOR8 _SFR_MEM8(0x0008) /* General Purpose IO Register 8 */ -#define GPIOR9 _SFR_MEM8(0x0009) /* General Purpose IO Register 9 */ -#define GPIORA _SFR_MEM8(0x000A) /* General Purpose IO Register 10 */ -#define GPIORB _SFR_MEM8(0x000B) /* General Purpose IO Register 11 */ -#define GPIORC _SFR_MEM8(0x000C) /* General Purpose IO Register 12 */ -#define GPIORD _SFR_MEM8(0x000D) /* General Purpose IO Register 13 */ -#define GPIORE _SFR_MEM8(0x000E) /* General Purpose IO Register 14 */ -#define GPIORF _SFR_MEM8(0x000F) /* General Purpose IO Register 15 */ - -/* Deprecated */ -#define GPIO0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ -#define GPIO1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ -#define GPIO2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ -#define GPIO3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ -#define GPIO4 _SFR_MEM8(0x0004) /* General Purpose IO Register 4 */ -#define GPIO5 _SFR_MEM8(0x0005) /* General Purpose IO Register 5 */ -#define GPIO6 _SFR_MEM8(0x0006) /* General Purpose IO Register 6 */ -#define GPIO7 _SFR_MEM8(0x0007) /* General Purpose IO Register 7 */ -#define GPIO8 _SFR_MEM8(0x0008) /* General Purpose IO Register 8 */ -#define GPIO9 _SFR_MEM8(0x0009) /* General Purpose IO Register 9 */ -#define GPIOA _SFR_MEM8(0x000A) /* General Purpose IO Register 10 */ -#define GPIOB _SFR_MEM8(0x000B) /* General Purpose IO Register 11 */ -#define GPIOC _SFR_MEM8(0x000C) /* General Purpose IO Register 12 */ -#define GPIOD _SFR_MEM8(0x000D) /* General Purpose IO Register 13 */ -#define GPIOE _SFR_MEM8(0x000E) /* General Purpose IO Register 14 */ -#define GPIOF _SFR_MEM8(0x000F) /* General Purpose IO Register 15 */ - -#define CCP _SFR_MEM8(0x0034) /* Configuration Change Protection */ -#define RAMPD _SFR_MEM8(0x0038) /* Ramp D */ -#define RAMPX _SFR_MEM8(0x0039) /* Ramp X */ -#define RAMPY _SFR_MEM8(0x003A) /* Ramp Y */ -#define RAMPZ _SFR_MEM8(0x003B) /* Ramp Z */ -#define EIND _SFR_MEM8(0x003C) /* Extended Indirect Jump */ -#define SPL _SFR_MEM8(0x003D) /* Stack Pointer Low */ -#define SPH _SFR_MEM8(0x003E) /* Stack Pointer High */ -#define SREG _SFR_MEM8(0x003F) /* Status Register */ - -/* C Language Only */ -#if !defined (__ASSEMBLER__) - -#include - -typedef volatile uint8_t register8_t; -typedef volatile uint16_t register16_t; -typedef volatile uint32_t register32_t; - - -#ifdef _WORDREGISTER -#undef _WORDREGISTER -#endif -#define _WORDREGISTER(regname) \ - __extension__ union \ - { \ - register16_t regname; \ - struct \ - { \ - register8_t regname ## L; \ - register8_t regname ## H; \ - }; \ - } - -#ifdef _DWORDREGISTER -#undef _DWORDREGISTER -#endif -#define _DWORDREGISTER(regname) \ - __extension__ union \ - { \ - register32_t regname; \ - struct \ - { \ - register8_t regname ## 0; \ - register8_t regname ## 1; \ - register8_t regname ## 2; \ - register8_t regname ## 3; \ - }; \ - } - - -/* -========================================================================== -IO Module Structures -========================================================================== -*/ - - -/* --------------------------------------------------------------------------- -VPORT - Virtual Ports --------------------------------------------------------------------------- -*/ - -/* Virtual Port */ -typedef struct VPORT_struct -{ - register8_t DIR; /* I/O Port Data Direction */ - register8_t OUT; /* I/O Port Output */ - register8_t IN; /* I/O Port Input */ - register8_t INTFLAGS; /* Interrupt Flag Register */ -} VPORT_t; - - -/* --------------------------------------------------------------------------- -XOCD - On-Chip Debug System --------------------------------------------------------------------------- -*/ - -/* On-Chip Debug System */ -typedef struct OCD_struct -{ - register8_t OCDR0; /* OCD Register 0 */ - register8_t OCDR1; /* OCD Register 1 */ -} OCD_t; - - -/* --------------------------------------------------------------------------- -CPU - CPU --------------------------------------------------------------------------- -*/ - -/* CCP signatures */ -typedef enum CCP_enum -{ - CCP_SPM_gc = (0x9D<<0), /* SPM Instruction Protection */ - CCP_IOREG_gc = (0xD8<<0), /* IO Register Protection */ -} CCP_t; - - -/* --------------------------------------------------------------------------- -CLK - Clock System --------------------------------------------------------------------------- -*/ - -/* Clock System */ -typedef struct CLK_struct -{ - register8_t CTRL; /* Control Register */ - register8_t PSCTRL; /* Prescaler Control Register */ - register8_t LOCK; /* Lock register */ - register8_t RTCCTRL; /* RTC Control Register */ - register8_t USBCTRL; /* USB Control Register */ -} CLK_t; - - -/* Power Reduction */ -typedef struct PR_struct -{ - register8_t PRGEN; /* General Power Reduction */ - register8_t PRPA; /* Power Reduction Port A */ - register8_t PRPB; /* Power Reduction Port B */ - register8_t PRPC; /* Power Reduction Port C */ - register8_t PRPD; /* Power Reduction Port D */ - register8_t PRPE; /* Power Reduction Port E */ - register8_t PRPF; /* Power Reduction Port F */ -} PR_t; - -/* System Clock Selection */ -typedef enum CLK_SCLKSEL_enum -{ - CLK_SCLKSEL_RC2M_gc = (0x00<<0), /* Internal 2 MHz RC Oscillator */ - CLK_SCLKSEL_RC32M_gc = (0x01<<0), /* Internal 32 MHz RC Oscillator */ - CLK_SCLKSEL_RC32K_gc = (0x02<<0), /* Internal 32.768 kHz RC Oscillator */ - CLK_SCLKSEL_XOSC_gc = (0x03<<0), /* External Crystal Oscillator or Clock */ - CLK_SCLKSEL_PLL_gc = (0x04<<0), /* Phase Locked Loop */ -} CLK_SCLKSEL_t; - -/* Prescaler A Division Factor */ -typedef enum CLK_PSADIV_enum -{ - CLK_PSADIV_1_gc = (0x00<<2), /* Divide by 1 */ - CLK_PSADIV_2_gc = (0x01<<2), /* Divide by 2 */ - CLK_PSADIV_4_gc = (0x03<<2), /* Divide by 4 */ - CLK_PSADIV_8_gc = (0x05<<2), /* Divide by 8 */ - CLK_PSADIV_16_gc = (0x07<<2), /* Divide by 16 */ - CLK_PSADIV_32_gc = (0x09<<2), /* Divide by 32 */ - CLK_PSADIV_64_gc = (0x0B<<2), /* Divide by 64 */ - CLK_PSADIV_128_gc = (0x0D<<2), /* Divide by 128 */ - CLK_PSADIV_256_gc = (0x0F<<2), /* Divide by 256 */ - CLK_PSADIV_512_gc = (0x11<<2), /* Divide by 512 */ -} CLK_PSADIV_t; - -/* Prescaler B and C Division Factor */ -typedef enum CLK_PSBCDIV_enum -{ - CLK_PSBCDIV_1_1_gc = (0x00<<0), /* Divide B by 1 and C by 1 */ - CLK_PSBCDIV_1_2_gc = (0x01<<0), /* Divide B by 1 and C by 2 */ - CLK_PSBCDIV_4_1_gc = (0x02<<0), /* Divide B by 4 and C by 1 */ - CLK_PSBCDIV_2_2_gc = (0x03<<0), /* Divide B by 2 and C by 2 */ -} CLK_PSBCDIV_t; - -/* RTC Clock Source */ -typedef enum CLK_RTCSRC_enum -{ - CLK_RTCSRC_ULP_gc = (0x00<<1), /* 1.024 kHz from internal 32kHz ULP */ - CLK_RTCSRC_TOSC_gc = (0x01<<1), /* 1.024 kHz from 32.768 kHz crystal oscillator on TOSC */ - CLK_RTCSRC_RCOSC_gc = (0x02<<1), /* 1.024 kHz from internal 32.768 kHz RC oscillator */ - CLK_RTCSRC_TOSC32_gc = (0x05<<1), /* 32.768 kHz from 32.768 kHz crystal oscillator on TOSC */ - CLK_RTCSRC_RCOSC32_gc = (0x06<<1), /* 32.768 kHz from internal 32.768 kHz RC oscillator */ - CLK_RTCSRC_EXTCLK_gc = (0x07<<1), /* External Clock from TOSC1 */ -} CLK_RTCSRC_t; - -/* USB Prescaler Division Factor */ -typedef enum CLK_USBPSDIV_enum -{ - CLK_USBPSDIV_1_gc = (0x00<<3), /* Divide by 1 */ - CLK_USBPSDIV_2_gc = (0x01<<3), /* Divide by 2 */ - CLK_USBPSDIV_4_gc = (0x02<<3), /* Divide by 4 */ - CLK_USBPSDIV_8_gc = (0x03<<3), /* Divide by 8 */ - CLK_USBPSDIV_16_gc = (0x04<<3), /* Divide by 16 */ - CLK_USBPSDIV_32_gc = (0x05<<3), /* Divide by 32 */ -} CLK_USBPSDIV_t; - -/* USB Clock Source */ -typedef enum CLK_USBSRC_enum -{ - CLK_USBSRC_PLL_gc = (0x00<<1), /* PLL */ - CLK_USBSRC_RC32M_gc = (0x01<<1), /* Internal 32 MHz RC Oscillator */ -} CLK_USBSRC_t; - - -/* --------------------------------------------------------------------------- -SLEEP - Sleep Controller --------------------------------------------------------------------------- -*/ - -/* Sleep Controller */ -typedef struct SLEEP_struct -{ - register8_t CTRL; /* Control Register */ -} SLEEP_t; - -/* Sleep Mode */ -typedef enum SLEEP_SMODE_enum -{ - SLEEP_SMODE_IDLE_gc = (0x00<<1), /* Idle mode */ - SLEEP_SMODE_PDOWN_gc = (0x02<<1), /* Power-down Mode */ - SLEEP_SMODE_PSAVE_gc = (0x03<<1), /* Power-save Mode */ - SLEEP_SMODE_STDBY_gc = (0x06<<1), /* Standby Mode */ - SLEEP_SMODE_ESTDBY_gc = (0x07<<1), /* Extended Standby Mode */ -} SLEEP_SMODE_t; - - - -#define SLEEP_MODE_IDLE (0x00<<1) -#define SLEEP_MODE_PWR_DOWN (0x02<<1) -#define SLEEP_MODE_PWR_SAVE (0x03<<1) -#define SLEEP_MODE_STANDBY (0x06<<1) -#define SLEEP_MODE_EXT_STANDBY (0x07<<1) -/* --------------------------------------------------------------------------- -OSC - Oscillator --------------------------------------------------------------------------- -*/ - -/* Oscillator */ -typedef struct OSC_struct -{ - register8_t CTRL; /* Control Register */ - register8_t STATUS; /* Status Register */ - register8_t XOSCCTRL; /* External Oscillator Control Register */ - register8_t XOSCFAIL; /* Oscillator Failure Detection Register */ - register8_t RC32KCAL; /* 32.768 kHz Internal Oscillator Calibration Register */ - register8_t PLLCTRL; /* PLL Control Register */ - register8_t DFLLCTRL; /* DFLL Control Register */ -} OSC_t; - -/* Oscillator Frequency Range */ -typedef enum OSC_FRQRANGE_enum -{ - OSC_FRQRANGE_04TO2_gc = (0x00<<6), /* 0.4 - 2 MHz */ - OSC_FRQRANGE_2TO9_gc = (0x01<<6), /* 2 - 9 MHz */ - OSC_FRQRANGE_9TO12_gc = (0x02<<6), /* 9 - 12 MHz */ - OSC_FRQRANGE_12TO16_gc = (0x03<<6), /* 12 - 16 MHz */ -} OSC_FRQRANGE_t; - -/* External Oscillator Selection and Startup Time */ -typedef enum OSC_XOSCSEL_enum -{ - OSC_XOSCSEL_EXTCLK_gc = (0x00<<0), /* External Clock - 6 CLK */ - OSC_XOSCSEL_32KHz_gc = (0x02<<0), /* 32.768 kHz TOSC - 32K CLK */ - OSC_XOSCSEL_XTAL_256CLK_gc = (0x03<<0), /* 0.4-16 MHz XTAL - 256 CLK */ - OSC_XOSCSEL_XTAL_1KCLK_gc = (0x07<<0), /* 0.4-16 MHz XTAL - 1K CLK */ - OSC_XOSCSEL_XTAL_16KCLK_gc = (0x0B<<0), /* 0.4-16 MHz XTAL - 16K CLK */ -} OSC_XOSCSEL_t; - -/* PLL Clock Source */ -typedef enum OSC_PLLSRC_enum -{ - OSC_PLLSRC_RC2M_gc = (0x00<<6), /* Internal 2 MHz RC Oscillator */ - OSC_PLLSRC_RC32M_gc = (0x02<<6), /* Internal 32 MHz RC Oscillator */ - OSC_PLLSRC_XOSC_gc = (0x03<<6), /* External Oscillator */ -} OSC_PLLSRC_t; - -/* 2 MHz DFLL Calibration Reference */ -typedef enum OSC_RC2MCREF_enum -{ - OSC_RC2MCREF_RC32K_gc = (0x00<<0), /* Internal 32.768 kHz RC Oscillator */ - OSC_RC2MCREF_XOSC32K_gc = (0x01<<0), /* External 32.768 kHz Crystal Oscillator */ -} OSC_RC2MCREF_t; - -/* 32 MHz DFLL Calibration Reference */ -typedef enum OSC_RC32MCREF_enum -{ - OSC_RC32MCREF_RC32K_gc = (0x00<<1), /* Internal 32.768 kHz RC Oscillator */ - OSC_RC32MCREF_XOSC32K_gc = (0x01<<1), /* External 32.768 kHz Crystal Oscillator */ - OSC_RC32MCREF_USBSOF_gc = (0x02<<1), /* USB Start of Frame */ -} OSC_RC32MCREF_t; - - -/* --------------------------------------------------------------------------- -DFLL - DFLL --------------------------------------------------------------------------- -*/ - -/* DFLL */ -typedef struct DFLL_struct -{ - register8_t CTRL; /* Control Register */ - register8_t reserved_0x01; - register8_t CALA; /* Calibration Register A */ - register8_t CALB; /* Calibration Register B */ - register8_t COMP0; /* Oscillator Compare Register 0 */ - register8_t COMP1; /* Oscillator Compare Register 1 */ - register8_t COMP2; /* Oscillator Compare Register 2 */ - register8_t reserved_0x07; -} DFLL_t; - - -/* --------------------------------------------------------------------------- -RST - Reset --------------------------------------------------------------------------- -*/ - -/* Reset */ -typedef struct RST_struct -{ - register8_t STATUS; /* Status Register */ - register8_t CTRL; /* Control Register */ -} RST_t; - - -/* --------------------------------------------------------------------------- -WDT - Watch-Dog Timer --------------------------------------------------------------------------- -*/ - -/* Watch-Dog Timer */ -typedef struct WDT_struct -{ - register8_t CTRL; /* Control */ - register8_t WINCTRL; /* Windowed Mode Control */ - register8_t STATUS; /* Status */ -} WDT_t; - -/* Period setting */ -typedef enum WDT_PER_enum -{ - WDT_PER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ - WDT_PER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ - WDT_PER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ - WDT_PER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ - WDT_PER_128CLK_gc = (0x04<<2), /* 128 cycles (0.128s @ 3.3V) */ - WDT_PER_256CLK_gc = (0x05<<2), /* 256 cycles (0.256s @ 3.3V) */ - WDT_PER_512CLK_gc = (0x06<<2), /* 512 cycles (0.512s @ 3.3V) */ - WDT_PER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ - WDT_PER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ - WDT_PER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ - WDT_PER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ -} WDT_PER_t; - -/* Closed window period */ -typedef enum WDT_WPER_enum -{ - WDT_WPER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ - WDT_WPER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ - WDT_WPER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ - WDT_WPER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ - WDT_WPER_128CLK_gc = (0x04<<2), /* 128 cycles (0.128s @ 3.3V) */ - WDT_WPER_256CLK_gc = (0x05<<2), /* 256 cycles (0.256s @ 3.3V) */ - WDT_WPER_512CLK_gc = (0x06<<2), /* 512 cycles (0.512s @ 3.3V) */ - WDT_WPER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ - WDT_WPER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ - WDT_WPER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ - WDT_WPER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ -} WDT_WPER_t; - - -/* --------------------------------------------------------------------------- -MCU - MCU Control --------------------------------------------------------------------------- -*/ - -/* MCU Control */ -typedef struct MCU_struct -{ - register8_t DEVID0; /* Device ID byte 0 */ - register8_t DEVID1; /* Device ID byte 1 */ - register8_t DEVID2; /* Device ID byte 2 */ - register8_t REVID; /* Revision ID */ - register8_t JTAGUID; /* JTAG User ID */ - register8_t reserved_0x05; - register8_t MCUCR; /* MCU Control */ - register8_t ANAINIT; /* Analog Startup Delay */ - register8_t EVSYSLOCK; /* Event System Lock */ - register8_t AWEXLOCK; /* AWEX Lock */ - register8_t reserved_0x0A; - register8_t reserved_0x0B; -} MCU_t; - - -/* --------------------------------------------------------------------------- -PMIC - Programmable Multi-level Interrupt Controller --------------------------------------------------------------------------- -*/ - -/* Programmable Multi-level Interrupt Controller */ -typedef struct PMIC_struct -{ - register8_t STATUS; /* Status Register */ - register8_t INTPRI; /* Interrupt Priority */ - register8_t CTRL; /* Control Register */ - register8_t reserved_0x03; - register8_t reserved_0x04; - register8_t reserved_0x05; - register8_t reserved_0x06; - register8_t reserved_0x07; - register8_t reserved_0x08; - register8_t reserved_0x09; - register8_t reserved_0x0A; - register8_t reserved_0x0B; - register8_t reserved_0x0C; - register8_t reserved_0x0D; - register8_t reserved_0x0E; - register8_t reserved_0x0F; -} PMIC_t; - - -/* --------------------------------------------------------------------------- -PORTCFG - Port Configuration --------------------------------------------------------------------------- -*/ - -/* I/O port Configuration */ -typedef struct PORTCFG_struct -{ - register8_t MPCMASK; /* Multi-pin Configuration Mask */ - register8_t reserved_0x01; - register8_t VPCTRLA; /* Virtual Port Control Register A */ - register8_t VPCTRLB; /* Virtual Port Control Register B */ - register8_t CLKEVOUT; /* Clock and Event Out Register */ - register8_t EBIOUT; /* EBI Output register */ - register8_t EVOUTSEL; /* Event Output Select */ -} PORTCFG_t; - -/* Virtual Port Mapping */ -typedef enum PORTCFG_VP02MAP_enum -{ - PORTCFG_VP02MAP_PORTA_gc = (0x00<<0), /* Mapped To PORTA */ - PORTCFG_VP02MAP_PORTB_gc = (0x01<<0), /* Mapped To PORTB */ - PORTCFG_VP02MAP_PORTC_gc = (0x02<<0), /* Mapped To PORTC */ - PORTCFG_VP02MAP_PORTD_gc = (0x03<<0), /* Mapped To PORTD */ - PORTCFG_VP02MAP_PORTE_gc = (0x04<<0), /* Mapped To PORTE */ - PORTCFG_VP02MAP_PORTF_gc = (0x05<<0), /* Mapped To PORTF */ - PORTCFG_VP02MAP_PORTG_gc = (0x06<<0), /* Mapped To PORTG */ - PORTCFG_VP02MAP_PORTH_gc = (0x07<<0), /* Mapped To PORTH */ - PORTCFG_VP02MAP_PORTJ_gc = (0x08<<0), /* Mapped To PORTJ */ - PORTCFG_VP02MAP_PORTK_gc = (0x09<<0), /* Mapped To PORTK */ - PORTCFG_VP02MAP_PORTL_gc = (0x0A<<0), /* Mapped To PORTL */ - PORTCFG_VP02MAP_PORTM_gc = (0x0B<<0), /* Mapped To PORTM */ - PORTCFG_VP02MAP_PORTN_gc = (0x0C<<0), /* Mapped To PORTN */ - PORTCFG_VP02MAP_PORTP_gc = (0x0D<<0), /* Mapped To PORTP */ - PORTCFG_VP02MAP_PORTQ_gc = (0x0E<<0), /* Mapped To PORTQ */ - PORTCFG_VP02MAP_PORTR_gc = (0x0F<<0), /* Mapped To PORTR */ -} PORTCFG_VP02MAP_t; - -/* Virtual Port Mapping */ -typedef enum PORTCFG_VP13MAP_enum -{ - PORTCFG_VP13MAP_PORTA_gc = (0x00<<4), /* Mapped To PORTA */ - PORTCFG_VP13MAP_PORTB_gc = (0x01<<4), /* Mapped To PORTB */ - PORTCFG_VP13MAP_PORTC_gc = (0x02<<4), /* Mapped To PORTC */ - PORTCFG_VP13MAP_PORTD_gc = (0x03<<4), /* Mapped To PORTD */ - PORTCFG_VP13MAP_PORTE_gc = (0x04<<4), /* Mapped To PORTE */ - PORTCFG_VP13MAP_PORTF_gc = (0x05<<4), /* Mapped To PORTF */ - PORTCFG_VP13MAP_PORTG_gc = (0x06<<4), /* Mapped To PORTG */ - PORTCFG_VP13MAP_PORTH_gc = (0x07<<4), /* Mapped To PORTH */ - PORTCFG_VP13MAP_PORTJ_gc = (0x08<<4), /* Mapped To PORTJ */ - PORTCFG_VP13MAP_PORTK_gc = (0x09<<4), /* Mapped To PORTK */ - PORTCFG_VP13MAP_PORTL_gc = (0x0A<<4), /* Mapped To PORTL */ - PORTCFG_VP13MAP_PORTM_gc = (0x0B<<4), /* Mapped To PORTM */ - PORTCFG_VP13MAP_PORTN_gc = (0x0C<<4), /* Mapped To PORTN */ - PORTCFG_VP13MAP_PORTP_gc = (0x0D<<4), /* Mapped To PORTP */ - PORTCFG_VP13MAP_PORTQ_gc = (0x0E<<4), /* Mapped To PORTQ */ - PORTCFG_VP13MAP_PORTR_gc = (0x0F<<4), /* Mapped To PORTR */ -} PORTCFG_VP13MAP_t; - -/* System Clock Output Port */ -typedef enum PORTCFG_CLKOUT_enum -{ - PORTCFG_CLKOUT_OFF_gc = (0x00<<0), /* System Clock Output Disabled */ - PORTCFG_CLKOUT_PC7_gc = (0x01<<0), /* System Clock Output on Port C pin 7 */ - PORTCFG_CLKOUT_PD7_gc = (0x02<<0), /* System Clock Output on Port D pin 7 */ - PORTCFG_CLKOUT_PE7_gc = (0x03<<0), /* System Clock Output on Port E pin 7 */ -} PORTCFG_CLKOUT_t; - -/* Peripheral Clock Output Select */ -typedef enum PORTCFG_CLKOUTSEL_enum -{ - PORTCFG_CLKOUTSEL_CLK1X_gc = (0x00<<2), /* 1x Peripheral Clock Output to pin */ - PORTCFG_CLKOUTSEL_CLK2X_gc = (0x01<<2), /* 2x Peripheral Clock Output to pin */ - PORTCFG_CLKOUTSEL_CLK4X_gc = (0x02<<2), /* 4x Peripheral Clock Output to pin */ -} PORTCFG_CLKOUTSEL_t; - -/* Event Output Port */ -typedef enum PORTCFG_EVOUT_enum -{ - PORTCFG_EVOUT_OFF_gc = (0x00<<4), /* Event Output Disabled */ - PORTCFG_EVOUT_PC7_gc = (0x01<<4), /* Event Channel 7 Output on Port C pin 7 */ - PORTCFG_EVOUT_PD7_gc = (0x02<<4), /* Event Channel 7 Output on Port D pin 7 */ - PORTCFG_EVOUT_PE7_gc = (0x03<<4), /* Event Channel 7 Output on Port E pin 7 */ -} PORTCFG_EVOUT_t; - -/* Clock and Event Output Port */ -typedef enum PORTCFG_CLKEVPIN_enum -{ - PORTCFG_CLKEVPIN_PIN7_gc = (0x00<<7), /* Clock and Event Ouput on PIN 7 */ - PORTCFG_CLKEVPIN_PIN4_gc = (0x01<<7), /* Clock and Event Ouput on PIN 4 */ -} PORTCFG_CLKEVPIN_t; - -/* EBI Address Output Port */ -typedef enum PORTCFG_EBIADROUT_enum -{ - PORTCFG_EBIADROUT_PF_gc = (0x00<<2), /* EBI port 3 address output on PORTF pins 0 to 7 */ - PORTCFG_EBIADROUT_PE_gc = (0x01<<2), /* EBI port 3 address output on PORTE pins 0 to 7 */ - PORTCFG_EBIADROUT_PFH_gc = (0x02<<2), /* EBI port 3 address output on PORTF pins 4 to 7 */ - PORTCFG_EBIADROUT_PEH_gc = (0x03<<2), /* EBI port 3 address output on PORTE pins 4 to 7 */ -} PORTCFG_EBIADROUT_t; - -/* EBI Chip Select Output Port */ -typedef enum PORTCFG_EBICSOUT_enum -{ - PORTCFG_EBICSOUT_PH_gc = (0x00<<0), /* EBI chip select output to PORTH pin 4 to 7 */ - PORTCFG_EBICSOUT_PL_gc = (0x01<<0), /* EBI chip select output to PORTL pin 4 to 7 */ - PORTCFG_EBICSOUT_PF_gc = (0x02<<0), /* EBI chip select output to PORTF pin 4 to 7 */ - PORTCFG_EBICSOUT_PE_gc = (0x03<<0), /* EBI chip select output to PORTE pin 4 to 7 */ -} PORTCFG_EBICSOUT_t; - -/* Event Output Select */ -typedef enum PORTCFG_EVOUTSEL_enum -{ - PORTCFG_EVOUTSEL_0_gc = (0x00<<0), /* Event Channel 0 output to pin */ - PORTCFG_EVOUTSEL_1_gc = (0x01<<0), /* Event Channel 1 output to pin */ - PORTCFG_EVOUTSEL_2_gc = (0x02<<0), /* Event Channel 2 output to pin */ - PORTCFG_EVOUTSEL_3_gc = (0x03<<0), /* Event Channel 3 output to pin */ - PORTCFG_EVOUTSEL_4_gc = (0x04<<0), /* Event Channel 4 output to pin */ - PORTCFG_EVOUTSEL_5_gc = (0x05<<0), /* Event Channel 5 output to pin */ - PORTCFG_EVOUTSEL_6_gc = (0x06<<0), /* Event Channel 6 output to pin */ - PORTCFG_EVOUTSEL_7_gc = (0x07<<0), /* Event Channel 7 output to pin */ -} PORTCFG_EVOUTSEL_t; - - -/* --------------------------------------------------------------------------- -AES - AES Module --------------------------------------------------------------------------- -*/ - -/* AES Module */ -typedef struct AES_struct -{ - register8_t CTRL; /* AES Control Register */ - register8_t STATUS; /* AES Status Register */ - register8_t STATE; /* AES State Register */ - register8_t KEY; /* AES Key Register */ - register8_t INTCTRL; /* AES Interrupt Control Register */ -} AES_t; - -/* Interrupt level */ -typedef enum AES_INTLVL_enum -{ - AES_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - AES_INTLVL_LO_gc = (0x01<<0), /* Low Level */ - AES_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ - AES_INTLVL_HI_gc = (0x03<<0), /* High Level */ -} AES_INTLVL_t; - - -/* --------------------------------------------------------------------------- -CRC - Cyclic Redundancy Checker --------------------------------------------------------------------------- -*/ - -/* Cyclic Redundancy Checker */ -typedef struct CRC_struct -{ - register8_t CTRL; /* Control Register */ - register8_t STATUS; /* Status Register */ - register8_t reserved_0x02; - register8_t DATAIN; /* Data Input */ - register8_t CHECKSUM0; /* Checksum byte 0 */ - register8_t CHECKSUM1; /* Checksum byte 1 */ - register8_t CHECKSUM2; /* Checksum byte 2 */ - register8_t CHECKSUM3; /* Checksum byte 3 */ -} CRC_t; - -/* Reset */ -typedef enum CRC_RESET_enum -{ - CRC_RESET_NO_gc = (0x00<<6), /* No Reset */ - CRC_RESET_RESET0_gc = (0x02<<6), /* Reset CRC with CHECKSUM to all zeros */ - CRC_RESET_RESET1_gc = (0x03<<6), /* Reset CRC with CHECKSUM to all ones */ -} CRC_RESET_t; - -/* Input Source */ -typedef enum CRC_SOURCE_enum -{ - CRC_SOURCE_DISABLE_gc = (0x00<<0), /* Disabled */ - CRC_SOURCE_IO_gc = (0x01<<0), /* I/O Interface */ - CRC_SOURCE_FLASH_gc = (0x02<<0), /* Flash */ - CRC_SOURCE_DMAC0_gc = (0x04<<0), /* DMAC Channel 0 */ - CRC_SOURCE_DMAC1_gc = (0x05<<0), /* DMAC Channel 1 */ - CRC_SOURCE_DMAC2_gc = (0x06<<0), /* DMAC Channel 2 */ - CRC_SOURCE_DMAC3_gc = (0x07<<0), /* DMAC Channel 3 */ -} CRC_SOURCE_t; - - -/* --------------------------------------------------------------------------- -DMA - DMA Controller --------------------------------------------------------------------------- -*/ - -/* DMA Channel */ -typedef struct DMA_CH_struct -{ - register8_t CTRLA; /* Channel Control */ - register8_t CTRLB; /* Channel Control */ - register8_t ADDRCTRL; /* Address Control */ - register8_t TRIGSRC; /* Channel Trigger Source */ - _WORDREGISTER(TRFCNT); /* Channel Block Transfer Count */ - register8_t REPCNT; /* Channel Repeat Count */ - register8_t reserved_0x07; - register8_t SRCADDR0; /* Channel Source Address 0 */ - register8_t SRCADDR1; /* Channel Source Address 1 */ - register8_t SRCADDR2; /* Channel Source Address 2 */ - register8_t reserved_0x0B; - register8_t DESTADDR0; /* Channel Destination Address 0 */ - register8_t DESTADDR1; /* Channel Destination Address 1 */ - register8_t DESTADDR2; /* Channel Destination Address 2 */ - register8_t reserved_0x0F; -} DMA_CH_t; - - -/* DMA Controller */ -typedef struct DMA_struct -{ - register8_t CTRL; /* Control */ - register8_t reserved_0x01; - register8_t reserved_0x02; - register8_t INTFLAGS; /* Transfer Interrupt Status */ - register8_t STATUS; /* Status */ - register8_t reserved_0x05; - _WORDREGISTER(TEMP); /* Temporary Register For 16/24-bit Access */ - register8_t reserved_0x08; - register8_t reserved_0x09; - register8_t reserved_0x0A; - register8_t reserved_0x0B; - register8_t reserved_0x0C; - register8_t reserved_0x0D; - register8_t reserved_0x0E; - register8_t reserved_0x0F; - DMA_CH_t CH0; /* DMA Channel 0 */ - DMA_CH_t CH1; /* DMA Channel 1 */ - DMA_CH_t CH2; /* DMA Channel 2 */ - DMA_CH_t CH3; /* DMA Channel 3 */ -} DMA_t; - -/* Burst mode */ -typedef enum DMA_CH_BURSTLEN_enum -{ - DMA_CH_BURSTLEN_1BYTE_gc = (0x00<<0), /* 1-byte burst mode */ - DMA_CH_BURSTLEN_2BYTE_gc = (0x01<<0), /* 2-byte burst mode */ - DMA_CH_BURSTLEN_4BYTE_gc = (0x02<<0), /* 4-byte burst mode */ - DMA_CH_BURSTLEN_8BYTE_gc = (0x03<<0), /* 8-byte burst mode */ -} DMA_CH_BURSTLEN_t; - -/* Source address reload mode */ -typedef enum DMA_CH_SRCRELOAD_enum -{ - DMA_CH_SRCRELOAD_NONE_gc = (0x00<<6), /* No reload */ - DMA_CH_SRCRELOAD_BLOCK_gc = (0x01<<6), /* Reload at end of block */ - DMA_CH_SRCRELOAD_BURST_gc = (0x02<<6), /* Reload at end of burst */ - DMA_CH_SRCRELOAD_TRANSACTION_gc = (0x03<<6), /* Reload at end of transaction */ -} DMA_CH_SRCRELOAD_t; - -/* Source addressing mode */ -typedef enum DMA_CH_SRCDIR_enum -{ - DMA_CH_SRCDIR_FIXED_gc = (0x00<<4), /* Fixed */ - DMA_CH_SRCDIR_INC_gc = (0x01<<4), /* Increment */ - DMA_CH_SRCDIR_DEC_gc = (0x02<<4), /* Decrement */ -} DMA_CH_SRCDIR_t; - -/* Destination adress reload mode */ -typedef enum DMA_CH_DESTRELOAD_enum -{ - DMA_CH_DESTRELOAD_NONE_gc = (0x00<<2), /* No reload */ - DMA_CH_DESTRELOAD_BLOCK_gc = (0x01<<2), /* Reload at end of block */ - DMA_CH_DESTRELOAD_BURST_gc = (0x02<<2), /* Reload at end of burst */ - DMA_CH_DESTRELOAD_TRANSACTION_gc = (0x03<<2), /* Reload at end of transaction */ -} DMA_CH_DESTRELOAD_t; - -/* Destination adressing mode */ -typedef enum DMA_CH_DESTDIR_enum -{ - DMA_CH_DESTDIR_FIXED_gc = (0x00<<0), /* Fixed */ - DMA_CH_DESTDIR_INC_gc = (0x01<<0), /* Increment */ - DMA_CH_DESTDIR_DEC_gc = (0x02<<0), /* Decrement */ -} DMA_CH_DESTDIR_t; - -/* Transfer trigger source */ -typedef enum DMA_CH_TRIGSRC_enum -{ - DMA_CH_TRIGSRC_OFF_gc = (0x00<<0), /* Off software triggers only */ - DMA_CH_TRIGSRC_EVSYS_CH0_gc = (0x01<<0), /* Event System Channel 0 */ - DMA_CH_TRIGSRC_EVSYS_CH1_gc = (0x02<<0), /* Event System Channel 1 */ - DMA_CH_TRIGSRC_EVSYS_CH2_gc = (0x03<<0), /* Event System Channel 2 */ - DMA_CH_TRIGSRC_ADCA_CH0_gc = (0x10<<0), /* ADCA Channel 0 */ - DMA_CH_TRIGSRC_ADCA_CH1_gc = (0x11<<0), /* ADCA Channel 1 */ - DMA_CH_TRIGSRC_ADCA_CH2_gc = (0x12<<0), /* ADCA Channel 2 */ - DMA_CH_TRIGSRC_ADCA_CH3_gc = (0x13<<0), /* ADCA Channel 3 */ - DMA_CH_TRIGSRC_ADCA_CH4_gc = (0x14<<0), /* ADCA Channel 0,1,2,3 combined */ - DMA_CH_TRIGSRC_DACA_CH0_gc = (0x15<<0), /* DACA Channel 0 */ - DMA_CH_TRIGSRC_DACA_CH1_gc = (0x16<<0), /* DACA Channel 1 */ - DMA_CH_TRIGSRC_ADCB_CH0_gc = (0x20<<0), /* ADCB Channel 0 */ - DMA_CH_TRIGSRC_ADCB_CH1_gc = (0x21<<0), /* ADCB Channel 1 */ - DMA_CH_TRIGSRC_ADCB_CH2_gc = (0x22<<0), /* ADCB Channel 2 */ - DMA_CH_TRIGSRC_ADCB_CH3_gc = (0x23<<0), /* ADCB Channel 3 */ - DMA_CH_TRIGSRC_ADCB_CH4_gc = (0x24<<0), /* ADCB Channel 0,1,2,3 combined */ - DMA_CH_TRIGSRC_DACB_CH0_gc = (0x25<<0), /* DACB Channel 0 */ - DMA_CH_TRIGSRC_DACB_CH1_gc = (0x26<<0), /* DACB Channel 1 */ - DMA_CH_TRIGSRC_TCC0_OVF_gc = (0x40<<0), /* Timer/Counter C0 Overflow */ - DMA_CH_TRIGSRC_TCC0_ERR_gc = (0x41<<0), /* Timer/Counter C0 Error */ - DMA_CH_TRIGSRC_TCC0_CCA_gc = (0x42<<0), /* Timer/Counter C0 Compare or Capture A */ - DMA_CH_TRIGSRC_TCC0_CCB_gc = (0x43<<0), /* Timer/Counter C0 Compare or Capture B */ - DMA_CH_TRIGSRC_TCC0_CCC_gc = (0x44<<0), /* Timer/Counter C0 Compare or Capture C */ - DMA_CH_TRIGSRC_TCC0_CCD_gc = (0x45<<0), /* Timer/Counter C0 Compare or Capture D */ - DMA_CH_TRIGSRC_TCC1_OVF_gc = (0x46<<0), /* Timer/Counter C1 Overflow */ - DMA_CH_TRIGSRC_TCC1_ERR_gc = (0x47<<0), /* Timer/Counter C1 Error */ - DMA_CH_TRIGSRC_TCC1_CCA_gc = (0x48<<0), /* Timer/Counter C1 Compare or Capture A */ - DMA_CH_TRIGSRC_TCC1_CCB_gc = (0x49<<0), /* Timer/Counter C1 Compare or Capture B */ - DMA_CH_TRIGSRC_SPIC_gc = (0x4A<<0), /* SPI C Transfer Complete */ - DMA_CH_TRIGSRC_USARTC0_RXC_gc = (0x4B<<0), /* USART C0 Receive Complete */ - DMA_CH_TRIGSRC_USARTC0_DRE_gc = (0x4C<<0), /* USART C0 Data Register Empty */ - DMA_CH_TRIGSRC_USARTC1_RXC_gc = (0x4E<<0), /* USART C1 Receive Complete */ - DMA_CH_TRIGSRC_USARTC1_DRE_gc = (0x4F<<0), /* USART C1 Data Register Empty */ - DMA_CH_TRIGSRC_TCD0_OVF_gc = (0x60<<0), /* Timer/Counter D0 Overflow */ - DMA_CH_TRIGSRC_TCD0_ERR_gc = (0x61<<0), /* Timer/Counter D0 Error */ - DMA_CH_TRIGSRC_TCD0_CCA_gc = (0x62<<0), /* Timer/Counter D0 Compare or Capture A */ - DMA_CH_TRIGSRC_TCD0_CCB_gc = (0x63<<0), /* Timer/Counter D0 Compare or Capture B */ - DMA_CH_TRIGSRC_TCD0_CCC_gc = (0x64<<0), /* Timer/Counter D0 Compare or Capture C */ - DMA_CH_TRIGSRC_TCD0_CCD_gc = (0x65<<0), /* Timer/Counter D0 Compare or Capture D */ - DMA_CH_TRIGSRC_TCD1_OVF_gc = (0x66<<0), /* Timer/Counter D1 Overflow */ - DMA_CH_TRIGSRC_TCD1_ERR_gc = (0x67<<0), /* Timer/Counter D1 Error */ - DMA_CH_TRIGSRC_TCD1_CCA_gc = (0x68<<0), /* Timer/Counter D1 Compare or Capture A */ - DMA_CH_TRIGSRC_TCD1_CCB_gc = (0x69<<0), /* Timer/Counter D1 Compare or Capture B */ - DMA_CH_TRIGSRC_SPID_gc = (0x6A<<0), /* SPI D Transfer Complete */ - DMA_CH_TRIGSRC_USARTD0_RXC_gc = (0x6B<<0), /* USART D0 Receive Complete */ - DMA_CH_TRIGSRC_USARTD0_DRE_gc = (0x6C<<0), /* USART D0 Data Register Empty */ - DMA_CH_TRIGSRC_USARTD1_RXC_gc = (0x6E<<0), /* USART D1 Receive Complete */ - DMA_CH_TRIGSRC_USARTD1_DRE_gc = (0x6F<<0), /* USART D1 Data Register Empty */ - DMA_CH_TRIGSRC_TCE0_OVF_gc = (0x80<<0), /* Timer/Counter E0 Overflow */ - DMA_CH_TRIGSRC_TCE0_ERR_gc = (0x81<<0), /* Timer/Counter E0 Error */ - DMA_CH_TRIGSRC_TCE0_CCA_gc = (0x82<<0), /* Timer/Counter E0 Compare or Capture A */ - DMA_CH_TRIGSRC_TCE0_CCB_gc = (0x83<<0), /* Timer/Counter E0 Compare or Capture B */ - DMA_CH_TRIGSRC_TCE0_CCC_gc = (0x84<<0), /* Timer/Counter E0 Compare or Capture C */ - DMA_CH_TRIGSRC_TCE0_CCD_gc = (0x85<<0), /* Timer/Counter E0 Compare or Capture D */ - DMA_CH_TRIGSRC_TCE1_OVF_gc = (0x86<<0), /* Timer/Counter E1 Overflow */ - DMA_CH_TRIGSRC_TCE1_ERR_gc = (0x87<<0), /* Timer/Counter E1 Error */ - DMA_CH_TRIGSRC_TCE1_CCA_gc = (0x88<<0), /* Timer/Counter E1 Compare or Capture A */ - DMA_CH_TRIGSRC_TCE1_CCB_gc = (0x89<<0), /* Timer/Counter E1 Compare or Capture B */ - DMA_CH_TRIGSRC_SPIE_gc = (0x8A<<0), /* SPI E Transfer Complete */ - DMA_CH_TRIGSRC_USARTE0_RXC_gc = (0x8B<<0), /* USART E0 Receive Complete */ - DMA_CH_TRIGSRC_USARTE0_DRE_gc = (0x8C<<0), /* USART E0 Data Register Empty */ - DMA_CH_TRIGSRC_USARTE1_RXC_gc = (0x8E<<0), /* USART E1 Receive Complete */ - DMA_CH_TRIGSRC_USARTE1_DRE_gc = (0x8F<<0), /* USART E1 Data Register Empty */ - DMA_CH_TRIGSRC_TCF0_OVF_gc = (0xA0<<0), /* Timer/Counter F0 Overflow */ - DMA_CH_TRIGSRC_TCF0_ERR_gc = (0xA1<<0), /* Timer/Counter F0 Error */ - DMA_CH_TRIGSRC_TCF0_CCA_gc = (0xA2<<0), /* Timer/Counter F0 Compare or Capture A */ - DMA_CH_TRIGSRC_TCF0_CCB_gc = (0xA3<<0), /* Timer/Counter F0 Compare or Capture B */ - DMA_CH_TRIGSRC_TCF0_CCC_gc = (0xA4<<0), /* Timer/Counter F0 Compare or Capture C */ - DMA_CH_TRIGSRC_TCF0_CCD_gc = (0xA5<<0), /* Timer/Counter F0 Compare or Capture D */ - DMA_CH_TRIGSRC_TCF1_OVF_gc = (0xA6<<0), /* Timer/Counter F1 Overflow */ - DMA_CH_TRIGSRC_TCF1_ERR_gc = (0xA7<<0), /* Timer/Counter F1 Error */ - DMA_CH_TRIGSRC_TCF1_CCA_gc = (0xA8<<0), /* Timer/Counter F1 Compare or Capture A */ - DMA_CH_TRIGSRC_TCF1_CCB_gc = (0xA9<<0), /* Timer/Counter F1 Compare or Capture B */ - DMA_CH_TRIGSRC_SPIF_gc = (0xAA<<0), /* SPI F Transfer Complete */ - DMA_CH_TRIGSRC_USARTF0_RXC_gc = (0xAB<<0), /* USART F0 Receive Complete */ - DMA_CH_TRIGSRC_USARTF0_DRE_gc = (0xAC<<0), /* USART F0 Data Register Empty */ - DMA_CH_TRIGSRC_USARTF1_RXC_gc = (0xAE<<0), /* USART F1 Receive Complete */ - DMA_CH_TRIGSRC_USARTF1_DRE_gc = (0xAF<<0), /* USART F1 Data Register Empty */ -} DMA_CH_TRIGSRC_t; - -/* Double buffering mode */ -typedef enum DMA_DBUFMODE_enum -{ - DMA_DBUFMODE_DISABLED_gc = (0x00<<2), /* Double buffering disabled */ - DMA_DBUFMODE_CH01_gc = (0x01<<2), /* Double buffering enabled on channel 0/1 */ - DMA_DBUFMODE_CH23_gc = (0x02<<2), /* Double buffering enabled on channel 2/3 */ - DMA_DBUFMODE_CH01CH23_gc = (0x03<<2), /* Double buffering enabled on ch. 0/1 and ch. 2/3 */ -} DMA_DBUFMODE_t; - -/* Priority mode */ -typedef enum DMA_PRIMODE_enum -{ - DMA_PRIMODE_RR0123_gc = (0x00<<0), /* Round Robin */ - DMA_PRIMODE_CH0RR123_gc = (0x01<<0), /* Channel 0 > Round Robin on channel 1/2/3 */ - DMA_PRIMODE_CH01RR23_gc = (0x02<<0), /* Channel 0 > channel 1 > Round Robin on channel 2/3 */ - DMA_PRIMODE_CH0123_gc = (0x03<<0), /* Channel 0 > channel 1 > channel 2 > channel 3 */ -} DMA_PRIMODE_t; - -/* Interrupt level */ -typedef enum DMA_CH_ERRINTLVL_enum -{ - DMA_CH_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ - DMA_CH_ERRINTLVL_LO_gc = (0x01<<2), /* Low level */ - DMA_CH_ERRINTLVL_MED_gc = (0x02<<2), /* Medium level */ - DMA_CH_ERRINTLVL_HI_gc = (0x03<<2), /* High level */ -} DMA_CH_ERRINTLVL_t; - -/* Interrupt level */ -typedef enum DMA_CH_TRNINTLVL_enum -{ - DMA_CH_TRNINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ - DMA_CH_TRNINTLVL_LO_gc = (0x01<<0), /* Low level */ - DMA_CH_TRNINTLVL_MED_gc = (0x02<<0), /* Medium level */ - DMA_CH_TRNINTLVL_HI_gc = (0x03<<0), /* High level */ -} DMA_CH_TRNINTLVL_t; - - -/* --------------------------------------------------------------------------- -EVSYS - Event System --------------------------------------------------------------------------- -*/ - -/* Event System */ -typedef struct EVSYS_struct -{ - register8_t CH0MUX; /* Event Channel 0 Multiplexer */ - register8_t CH1MUX; /* Event Channel 1 Multiplexer */ - register8_t CH2MUX; /* Event Channel 2 Multiplexer */ - register8_t CH3MUX; /* Event Channel 3 Multiplexer */ - register8_t CH4MUX; /* Event Channel 4 Multiplexer */ - register8_t CH5MUX; /* Event Channel 5 Multiplexer */ - register8_t CH6MUX; /* Event Channel 6 Multiplexer */ - register8_t CH7MUX; /* Event Channel 7 Multiplexer */ - register8_t CH0CTRL; /* Channel 0 Control Register */ - register8_t CH1CTRL; /* Channel 1 Control Register */ - register8_t CH2CTRL; /* Channel 2 Control Register */ - register8_t CH3CTRL; /* Channel 3 Control Register */ - register8_t CH4CTRL; /* Channel 4 Control Register */ - register8_t CH5CTRL; /* Channel 5 Control Register */ - register8_t CH6CTRL; /* Channel 6 Control Register */ - register8_t CH7CTRL; /* Channel 7 Control Register */ - register8_t STROBE; /* Event Strobe */ - register8_t DATA; /* Event Data */ -} EVSYS_t; - -/* Quadrature Decoder Index Recognition Mode */ -typedef enum EVSYS_QDIRM_enum -{ - EVSYS_QDIRM_00_gc = (0x00<<5), /* QDPH0 = 0, QDPH90 = 0 */ - EVSYS_QDIRM_01_gc = (0x01<<5), /* QDPH0 = 0, QDPH90 = 1 */ - EVSYS_QDIRM_10_gc = (0x02<<5), /* QDPH0 = 1, QDPH90 = 0 */ - EVSYS_QDIRM_11_gc = (0x03<<5), /* QDPH0 = 1, QDPH90 = 1 */ -} EVSYS_QDIRM_t; - -/* Digital filter coefficient */ -typedef enum EVSYS_DIGFILT_enum -{ - EVSYS_DIGFILT_1SAMPLE_gc = (0x00<<0), /* 1 SAMPLE */ - EVSYS_DIGFILT_2SAMPLES_gc = (0x01<<0), /* 2 SAMPLES */ - EVSYS_DIGFILT_3SAMPLES_gc = (0x02<<0), /* 3 SAMPLES */ - EVSYS_DIGFILT_4SAMPLES_gc = (0x03<<0), /* 4 SAMPLES */ - EVSYS_DIGFILT_5SAMPLES_gc = (0x04<<0), /* 5 SAMPLES */ - EVSYS_DIGFILT_6SAMPLES_gc = (0x05<<0), /* 6 SAMPLES */ - EVSYS_DIGFILT_7SAMPLES_gc = (0x06<<0), /* 7 SAMPLES */ - EVSYS_DIGFILT_8SAMPLES_gc = (0x07<<0), /* 8 SAMPLES */ -} EVSYS_DIGFILT_t; - -/* Event Channel multiplexer input selection */ -typedef enum EVSYS_CHMUX_enum -{ - EVSYS_CHMUX_OFF_gc = (0x00<<0), /* Off */ - EVSYS_CHMUX_RTC_OVF_gc = (0x08<<0), /* RTC Overflow */ - EVSYS_CHMUX_RTC_CMP_gc = (0x09<<0), /* RTC Compare Match */ - EVSYS_CHMUX_USB_gc = (0x0A<<0), /* USB Setup, SOF, CRC error and UNF/OVF */ - EVSYS_CHMUX_ACA_CH0_gc = (0x10<<0), /* Analog Comparator A Channel 0 */ - EVSYS_CHMUX_ACA_CH1_gc = (0x11<<0), /* Analog Comparator A Channel 1 */ - EVSYS_CHMUX_ACA_WIN_gc = (0x12<<0), /* Analog Comparator A Window */ - EVSYS_CHMUX_ACB_CH0_gc = (0x13<<0), /* Analog Comparator B Channel 0 */ - EVSYS_CHMUX_ACB_CH1_gc = (0x14<<0), /* Analog Comparator B Channel 1 */ - EVSYS_CHMUX_ACB_WIN_gc = (0x15<<0), /* Analog Comparator B Window */ - EVSYS_CHMUX_ADCA_CH0_gc = (0x20<<0), /* ADC A Channel 0 */ - EVSYS_CHMUX_ADCA_CH1_gc = (0x21<<0), /* ADC A Channel 1 */ - EVSYS_CHMUX_ADCA_CH2_gc = (0x22<<0), /* ADC A Channel 2 */ - EVSYS_CHMUX_ADCA_CH3_gc = (0x23<<0), /* ADC A Channel 3 */ - EVSYS_CHMUX_ADCB_CH0_gc = (0x24<<0), /* ADC B Channel 0 */ - EVSYS_CHMUX_ADCB_CH1_gc = (0x25<<0), /* ADC B Channel 1 */ - EVSYS_CHMUX_ADCB_CH2_gc = (0x26<<0), /* ADC B Channel 2 */ - EVSYS_CHMUX_ADCB_CH3_gc = (0x27<<0), /* ADC B Channel 3 */ - EVSYS_CHMUX_PORTA_PIN0_gc = (0x50<<0), /* Port A, Pin0 */ - EVSYS_CHMUX_PORTA_PIN1_gc = (0x51<<0), /* Port A, Pin1 */ - EVSYS_CHMUX_PORTA_PIN2_gc = (0x52<<0), /* Port A, Pin2 */ - EVSYS_CHMUX_PORTA_PIN3_gc = (0x53<<0), /* Port A, Pin3 */ - EVSYS_CHMUX_PORTA_PIN4_gc = (0x54<<0), /* Port A, Pin4 */ - EVSYS_CHMUX_PORTA_PIN5_gc = (0x55<<0), /* Port A, Pin5 */ - EVSYS_CHMUX_PORTA_PIN6_gc = (0x56<<0), /* Port A, Pin6 */ - EVSYS_CHMUX_PORTA_PIN7_gc = (0x57<<0), /* Port A, Pin7 */ - EVSYS_CHMUX_PORTB_PIN0_gc = (0x58<<0), /* Port B, Pin0 */ - EVSYS_CHMUX_PORTB_PIN1_gc = (0x59<<0), /* Port B, Pin1 */ - EVSYS_CHMUX_PORTB_PIN2_gc = (0x5A<<0), /* Port B, Pin2 */ - EVSYS_CHMUX_PORTB_PIN3_gc = (0x5B<<0), /* Port B, Pin3 */ - EVSYS_CHMUX_PORTB_PIN4_gc = (0x5C<<0), /* Port B, Pin4 */ - EVSYS_CHMUX_PORTB_PIN5_gc = (0x5D<<0), /* Port B, Pin5 */ - EVSYS_CHMUX_PORTB_PIN6_gc = (0x5E<<0), /* Port B, Pin6 */ - EVSYS_CHMUX_PORTB_PIN7_gc = (0x5F<<0), /* Port B, Pin7 */ - EVSYS_CHMUX_PORTC_PIN0_gc = (0x60<<0), /* Port C, Pin0 */ - EVSYS_CHMUX_PORTC_PIN1_gc = (0x61<<0), /* Port C, Pin1 */ - EVSYS_CHMUX_PORTC_PIN2_gc = (0x62<<0), /* Port C, Pin2 */ - EVSYS_CHMUX_PORTC_PIN3_gc = (0x63<<0), /* Port C, Pin3 */ - EVSYS_CHMUX_PORTC_PIN4_gc = (0x64<<0), /* Port C, Pin4 */ - EVSYS_CHMUX_PORTC_PIN5_gc = (0x65<<0), /* Port C, Pin5 */ - EVSYS_CHMUX_PORTC_PIN6_gc = (0x66<<0), /* Port C, Pin6 */ - EVSYS_CHMUX_PORTC_PIN7_gc = (0x67<<0), /* Port C, Pin7 */ - EVSYS_CHMUX_PORTD_PIN0_gc = (0x68<<0), /* Port D, Pin0 */ - EVSYS_CHMUX_PORTD_PIN1_gc = (0x69<<0), /* Port D, Pin1 */ - EVSYS_CHMUX_PORTD_PIN2_gc = (0x6A<<0), /* Port D, Pin2 */ - EVSYS_CHMUX_PORTD_PIN3_gc = (0x6B<<0), /* Port D, Pin3 */ - EVSYS_CHMUX_PORTD_PIN4_gc = (0x6C<<0), /* Port D, Pin4 */ - EVSYS_CHMUX_PORTD_PIN5_gc = (0x6D<<0), /* Port D, Pin5 */ - EVSYS_CHMUX_PORTD_PIN6_gc = (0x6E<<0), /* Port D, Pin6 */ - EVSYS_CHMUX_PORTD_PIN7_gc = (0x6F<<0), /* Port D, Pin7 */ - EVSYS_CHMUX_PORTE_PIN0_gc = (0x70<<0), /* Port E, Pin0 */ - EVSYS_CHMUX_PORTE_PIN1_gc = (0x71<<0), /* Port E, Pin1 */ - EVSYS_CHMUX_PORTE_PIN2_gc = (0x72<<0), /* Port E, Pin2 */ - EVSYS_CHMUX_PORTE_PIN3_gc = (0x73<<0), /* Port E, Pin3 */ - EVSYS_CHMUX_PORTE_PIN4_gc = (0x74<<0), /* Port E, Pin4 */ - EVSYS_CHMUX_PORTE_PIN5_gc = (0x75<<0), /* Port E, Pin5 */ - EVSYS_CHMUX_PORTE_PIN6_gc = (0x76<<0), /* Port E, Pin6 */ - EVSYS_CHMUX_PORTE_PIN7_gc = (0x77<<0), /* Port E, Pin7 */ - EVSYS_CHMUX_PORTF_PIN0_gc = (0x78<<0), /* Port F, Pin0 */ - EVSYS_CHMUX_PORTF_PIN1_gc = (0x79<<0), /* Port F, Pin1 */ - EVSYS_CHMUX_PORTF_PIN2_gc = (0x7A<<0), /* Port F, Pin2 */ - EVSYS_CHMUX_PORTF_PIN3_gc = (0x7B<<0), /* Port F, Pin3 */ - EVSYS_CHMUX_PORTF_PIN4_gc = (0x7C<<0), /* Port F, Pin4 */ - EVSYS_CHMUX_PORTF_PIN5_gc = (0x7D<<0), /* Port F, Pin5 */ - EVSYS_CHMUX_PORTF_PIN6_gc = (0x7E<<0), /* Port F, Pin6 */ - EVSYS_CHMUX_PORTF_PIN7_gc = (0x7F<<0), /* Port F, Pin7 */ - EVSYS_CHMUX_PRESCALER_1_gc = (0x80<<0), /* Prescaler, divide by 1 */ - EVSYS_CHMUX_PRESCALER_2_gc = (0x81<<0), /* Prescaler, divide by 2 */ - EVSYS_CHMUX_PRESCALER_4_gc = (0x82<<0), /* Prescaler, divide by 4 */ - EVSYS_CHMUX_PRESCALER_8_gc = (0x83<<0), /* Prescaler, divide by 8 */ - EVSYS_CHMUX_PRESCALER_16_gc = (0x84<<0), /* Prescaler, divide by 16 */ - EVSYS_CHMUX_PRESCALER_32_gc = (0x85<<0), /* Prescaler, divide by 32 */ - EVSYS_CHMUX_PRESCALER_64_gc = (0x86<<0), /* Prescaler, divide by 64 */ - EVSYS_CHMUX_PRESCALER_128_gc = (0x87<<0), /* Prescaler, divide by 128 */ - EVSYS_CHMUX_PRESCALER_256_gc = (0x88<<0), /* Prescaler, divide by 256 */ - EVSYS_CHMUX_PRESCALER_512_gc = (0x89<<0), /* Prescaler, divide by 512 */ - EVSYS_CHMUX_PRESCALER_1024_gc = (0x8A<<0), /* Prescaler, divide by 1024 */ - EVSYS_CHMUX_PRESCALER_2048_gc = (0x8B<<0), /* Prescaler, divide by 2048 */ - EVSYS_CHMUX_PRESCALER_4096_gc = (0x8C<<0), /* Prescaler, divide by 4096 */ - EVSYS_CHMUX_PRESCALER_8192_gc = (0x8D<<0), /* Prescaler, divide by 8192 */ - EVSYS_CHMUX_PRESCALER_16384_gc = (0x8E<<0), /* Prescaler, divide by 16384 */ - EVSYS_CHMUX_PRESCALER_32768_gc = (0x8F<<0), /* Prescaler, divide by 32768 */ - EVSYS_CHMUX_TCC0_OVF_gc = (0xC0<<0), /* Timer/Counter C0 Overflow */ - EVSYS_CHMUX_TCC0_ERR_gc = (0xC1<<0), /* Timer/Counter C0 Error */ - EVSYS_CHMUX_TCC0_CCA_gc = (0xC4<<0), /* Timer/Counter C0 Compare or Capture A */ - EVSYS_CHMUX_TCC0_CCB_gc = (0xC5<<0), /* Timer/Counter C0 Compare or Capture B */ - EVSYS_CHMUX_TCC0_CCC_gc = (0xC6<<0), /* Timer/Counter C0 Compare or Capture C */ - EVSYS_CHMUX_TCC0_CCD_gc = (0xC7<<0), /* Timer/Counter C0 Compare or Capture D */ - EVSYS_CHMUX_TCC1_OVF_gc = (0xC8<<0), /* Timer/Counter C1 Overflow */ - EVSYS_CHMUX_TCC1_ERR_gc = (0xC9<<0), /* Timer/Counter C1 Error */ - EVSYS_CHMUX_TCC1_CCA_gc = (0xCC<<0), /* Timer/Counter C1 Compare or Capture A */ - EVSYS_CHMUX_TCC1_CCB_gc = (0xCD<<0), /* Timer/Counter C1 Compare or Capture B */ - EVSYS_CHMUX_TCD0_OVF_gc = (0xD0<<0), /* Timer/Counter D0 Overflow */ - EVSYS_CHMUX_TCD0_ERR_gc = (0xD1<<0), /* Timer/Counter D0 Error */ - EVSYS_CHMUX_TCD0_CCA_gc = (0xD4<<0), /* Timer/Counter D0 Compare or Capture A */ - EVSYS_CHMUX_TCD0_CCB_gc = (0xD5<<0), /* Timer/Counter D0 Compare or Capture B */ - EVSYS_CHMUX_TCD0_CCC_gc = (0xD6<<0), /* Timer/Counter D0 Compare or Capture C */ - EVSYS_CHMUX_TCD0_CCD_gc = (0xD7<<0), /* Timer/Counter D0 Compare or Capture D */ - EVSYS_CHMUX_TCD1_OVF_gc = (0xD8<<0), /* Timer/Counter D1 Overflow */ - EVSYS_CHMUX_TCD1_ERR_gc = (0xD9<<0), /* Timer/Counter D1 Error */ - EVSYS_CHMUX_TCD1_CCA_gc = (0xDC<<0), /* Timer/Counter D1 Compare or Capture A */ - EVSYS_CHMUX_TCD1_CCB_gc = (0xDD<<0), /* Timer/Counter D1 Compare or Capture B */ - EVSYS_CHMUX_TCE0_OVF_gc = (0xE0<<0), /* Timer/Counter E0 Overflow */ - EVSYS_CHMUX_TCE0_ERR_gc = (0xE1<<0), /* Timer/Counter E0 Error */ - EVSYS_CHMUX_TCE0_CCA_gc = (0xE4<<0), /* Timer/Counter E0 Compare or Capture A */ - EVSYS_CHMUX_TCE0_CCB_gc = (0xE5<<0), /* Timer/Counter E0 Compare or Capture B */ - EVSYS_CHMUX_TCE0_CCC_gc = (0xE6<<0), /* Timer/Counter E0 Compare or Capture C */ - EVSYS_CHMUX_TCE0_CCD_gc = (0xE7<<0), /* Timer/Counter E0 Compare or Capture D */ - EVSYS_CHMUX_TCE1_OVF_gc = (0xE8<<0), /* Timer/Counter E1 Overflow */ - EVSYS_CHMUX_TCE1_ERR_gc = (0xE9<<0), /* Timer/Counter E1 Error */ - EVSYS_CHMUX_TCE1_CCA_gc = (0xEC<<0), /* Timer/Counter E1 Compare or Capture A */ - EVSYS_CHMUX_TCE1_CCB_gc = (0xED<<0), /* Timer/Counter E1 Compare or Capture B */ - EVSYS_CHMUX_TCF0_OVF_gc = (0xF0<<0), /* Timer/Counter F0 Overflow */ - EVSYS_CHMUX_TCF0_ERR_gc = (0xF1<<0), /* Timer/Counter F0 Error */ - EVSYS_CHMUX_TCF0_CCA_gc = (0xF4<<0), /* Timer/Counter F0 Compare or Capture A */ - EVSYS_CHMUX_TCF0_CCB_gc = (0xF5<<0), /* Timer/Counter F0 Compare or Capture B */ - EVSYS_CHMUX_TCF0_CCC_gc = (0xF6<<0), /* Timer/Counter F0 Compare or Capture C */ - EVSYS_CHMUX_TCF0_CCD_gc = (0xF7<<0), /* Timer/Counter F0 Compare or Capture D */ - EVSYS_CHMUX_TCF1_OVF_gc = (0xF8<<0), /* Timer/Counter F1 Overflow */ - EVSYS_CHMUX_TCF1_ERR_gc = (0xF9<<0), /* Timer/Counter F1 Error */ - EVSYS_CHMUX_TCF1_CCA_gc = (0xFC<<0), /* Timer/Counter F1 Compare or Capture A */ - EVSYS_CHMUX_TCF1_CCB_gc = (0xFD<<0), /* Timer/Counter F1 Compare or Capture B */ -} EVSYS_CHMUX_t; - - -/* --------------------------------------------------------------------------- -NVM - Non Volatile Memory Controller --------------------------------------------------------------------------- -*/ - -/* Non-volatile Memory Controller */ -typedef struct NVM_struct -{ - register8_t ADDR0; /* Address Register 0 */ - register8_t ADDR1; /* Address Register 1 */ - register8_t ADDR2; /* Address Register 2 */ - register8_t reserved_0x03; - register8_t DATA0; /* Data Register 0 */ - register8_t DATA1; /* Data Register 1 */ - register8_t DATA2; /* Data Register 2 */ - register8_t reserved_0x07; - register8_t reserved_0x08; - register8_t reserved_0x09; - register8_t CMD; /* Command */ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t INTCTRL; /* Interrupt Control */ - register8_t reserved_0x0E; - register8_t STATUS; /* Status */ - register8_t LOCK_BITS; /* Lock Bits (Changed from LOCKBITS to avoid avr-libc collision) */ -} NVM_t; - -/* NVM Command */ -typedef enum NVM_CMD_enum -{ - NVM_CMD_NO_OPERATION_gc = (0x00<<0), /* Noop/Ordinary LPM */ - NVM_CMD_READ_USER_SIG_ROW_gc = (0x01<<0), /* Read user signature row */ - NVM_CMD_READ_CALIB_ROW_gc = (0x02<<0), /* Read calibration row */ - NVM_CMD_READ_EEPROM_gc = (0x06<<0), /* Read EEPROM */ - NVM_CMD_READ_FUSES_gc = (0x07<<0), /* Read fuse byte */ - NVM_CMD_WRITE_LOCK_BITS_gc = (0x08<<0), /* Write lock bits */ - NVM_CMD_ERASE_USER_SIG_ROW_gc = (0x18<<0), /* Erase user signature row */ - NVM_CMD_WRITE_USER_SIG_ROW_gc = (0x1A<<0), /* Write user signature row */ - NVM_CMD_ERASE_APP_gc = (0x20<<0), /* Erase Application Section */ - NVM_CMD_ERASE_APP_PAGE_gc = (0x22<<0), /* Erase Application Section page */ - NVM_CMD_LOAD_FLASH_BUFFER_gc = (0x23<<0), /* Load Flash page buffer */ - NVM_CMD_WRITE_APP_PAGE_gc = (0x24<<0), /* Write Application Section page */ - NVM_CMD_ERASE_WRITE_APP_PAGE_gc = (0x25<<0), /* Erase-and-write Application Section page */ - NVM_CMD_ERASE_FLASH_BUFFER_gc = (0x26<<0), /* Erase/flush Flash page buffer */ - NVM_CMD_ERASE_BOOT_PAGE_gc = (0x2A<<0), /* Erase Boot Section page */ - NVM_CMD_ERASE_FLASH_PAGE_gc = (0x2B<<0), /* Erase Flash Page */ - NVM_CMD_WRITE_BOOT_PAGE_gc = (0x2C<<0), /* Write Boot Section page */ - NVM_CMD_ERASE_WRITE_BOOT_PAGE_gc = (0x2D<<0), /* Erase-and-write Boot Section page */ - NVM_CMD_WRITE_FLASH_PAGE_gc = (0x2E<<0), /* Write Flash Page */ - NVM_CMD_ERASE_WRITE_FLASH_PAGE_gc = (0x2F<<0), /* Erase-and-write Flash Page */ - NVM_CMD_ERASE_EEPROM_gc = (0x30<<0), /* Erase EEPROM */ - NVM_CMD_ERASE_EEPROM_PAGE_gc = (0x32<<0), /* Erase EEPROM page */ - NVM_CMD_LOAD_EEPROM_BUFFER_gc = (0x33<<0), /* Load EEPROM page buffer */ - NVM_CMD_WRITE_EEPROM_PAGE_gc = (0x34<<0), /* Write EEPROM page */ - NVM_CMD_ERASE_WRITE_EEPROM_PAGE_gc = (0x35<<0), /* Erase-and-write EEPROM page */ - NVM_CMD_ERASE_EEPROM_BUFFER_gc = (0x36<<0), /* Erase/flush EEPROM page buffer */ - NVM_CMD_APP_CRC_gc = (0x38<<0), /* Application section CRC */ - NVM_CMD_BOOT_CRC_gc = (0x39<<0), /* Boot Section CRC */ - NVM_CMD_FLASH_RANGE_CRC_gc = (0x3A<<0), /* Flash Range CRC */ - NVM_CMD_CHIP_ERASE_gc = (0x40<<0), /* Erase Chip */ - NVM_CMD_READ_NVM_gc = (0x43<<0), /* Read NVM */ - NVM_CMD_WRITE_FUSE_gc = (0x4C<<0), /* Write Fuse byte */ - NVM_CMD_ERASE_BOOT_gc = (0x68<<0), /* Erase Boot Section */ - NVM_CMD_FLASH_CRC_gc = (0x78<<0), /* Flash CRC */ -} NVM_CMD_t; - -/* SPM ready interrupt level */ -typedef enum NVM_SPMLVL_enum -{ - NVM_SPMLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ - NVM_SPMLVL_LO_gc = (0x01<<2), /* Low level */ - NVM_SPMLVL_MED_gc = (0x02<<2), /* Medium level */ - NVM_SPMLVL_HI_gc = (0x03<<2), /* High level */ -} NVM_SPMLVL_t; - -/* EEPROM ready interrupt level */ -typedef enum NVM_EELVL_enum -{ - NVM_EELVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ - NVM_EELVL_LO_gc = (0x01<<0), /* Low level */ - NVM_EELVL_MED_gc = (0x02<<0), /* Medium level */ - NVM_EELVL_HI_gc = (0x03<<0), /* High level */ -} NVM_EELVL_t; - -/* Boot lock bits - boot setcion */ -typedef enum NVM_BLBB_enum -{ - NVM_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ - NVM_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ - NVM_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ - NVM_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ -} NVM_BLBB_t; - -/* Boot lock bits - application section */ -typedef enum NVM_BLBA_enum -{ - NVM_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ - NVM_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ - NVM_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ - NVM_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ -} NVM_BLBA_t; - -/* Boot lock bits - application table section */ -typedef enum NVM_BLBAT_enum -{ - NVM_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ - NVM_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ - NVM_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ - NVM_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ -} NVM_BLBAT_t; - -/* Lock bits */ -typedef enum NVM_LB_enum -{ - NVM_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ - NVM_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ - NVM_LB_NOLOCK_gc = (0x03<<0), /* No locks */ -} NVM_LB_t; - - -/* --------------------------------------------------------------------------- -ADC - Analog/Digital Converter --------------------------------------------------------------------------- -*/ - -/* ADC Channel */ -typedef struct ADC_CH_struct -{ - register8_t CTRL; /* Control Register */ - register8_t MUXCTRL; /* MUX Control */ - register8_t INTCTRL; /* Channel Interrupt Control Register */ - register8_t INTFLAGS; /* Interrupt Flags */ - _WORDREGISTER(RES); /* Channel Result */ - register8_t SCAN; /* Input Channel Scan */ - register8_t reserved_0x07; -} ADC_CH_t; - - -/* Analog-to-Digital Converter */ -typedef struct ADC_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t REFCTRL; /* Reference Control */ - register8_t EVCTRL; /* Event Control */ - register8_t PRESCALER; /* Clock Prescaler */ - register8_t reserved_0x05; - register8_t INTFLAGS; /* Interrupt Flags */ - register8_t TEMP; /* Temporary Register */ - register8_t reserved_0x08; - register8_t reserved_0x09; - register8_t reserved_0x0A; - register8_t reserved_0x0B; - _WORDREGISTER(CAL); /* Calibration Value */ - register8_t reserved_0x0E; - register8_t reserved_0x0F; - _WORDREGISTER(CH0RES); /* Channel 0 Result */ - _WORDREGISTER(CH1RES); /* Channel 1 Result */ - _WORDREGISTER(CH2RES); /* Channel 2 Result */ - _WORDREGISTER(CH3RES); /* Channel 3 Result */ - _WORDREGISTER(CMP); /* Compare Value */ - register8_t reserved_0x1A; - register8_t reserved_0x1B; - register8_t reserved_0x1C; - register8_t reserved_0x1D; - register8_t reserved_0x1E; - register8_t reserved_0x1F; - ADC_CH_t CH0; /* ADC Channel 0 */ - ADC_CH_t CH1; /* ADC Channel 1 */ - ADC_CH_t CH2; /* ADC Channel 2 */ - ADC_CH_t CH3; /* ADC Channel 3 */ -} ADC_t; - -/* Positive input multiplexer selection */ -typedef enum ADC_CH_MUXPOS_enum -{ - ADC_CH_MUXPOS_PIN0_gc = (0x00<<3), /* Input pin 0 */ - ADC_CH_MUXPOS_PIN1_gc = (0x01<<3), /* Input pin 1 */ - ADC_CH_MUXPOS_PIN2_gc = (0x02<<3), /* Input pin 2 */ - ADC_CH_MUXPOS_PIN3_gc = (0x03<<3), /* Input pin 3 */ - ADC_CH_MUXPOS_PIN4_gc = (0x04<<3), /* Input pin 4 */ - ADC_CH_MUXPOS_PIN5_gc = (0x05<<3), /* Input pin 5 */ - ADC_CH_MUXPOS_PIN6_gc = (0x06<<3), /* Input pin 6 */ - ADC_CH_MUXPOS_PIN7_gc = (0x07<<3), /* Input pin 7 */ - ADC_CH_MUXPOS_PIN8_gc = (0x08<<3), /* Input pin 8 */ - ADC_CH_MUXPOS_PIN9_gc = (0x09<<3), /* Input pin 9 */ - ADC_CH_MUXPOS_PIN10_gc = (0x0A<<3), /* Input pin 10 */ - ADC_CH_MUXPOS_PIN11_gc = (0x0B<<3), /* Input pin 11 */ - ADC_CH_MUXPOS_PIN12_gc = (0x0C<<3), /* Input pin 12 */ - ADC_CH_MUXPOS_PIN13_gc = (0x0D<<3), /* Input pin 13 */ - ADC_CH_MUXPOS_PIN14_gc = (0x0E<<3), /* Input pin 14 */ - ADC_CH_MUXPOS_PIN15_gc = (0x0F<<3), /* Input pin 15 */ -} ADC_CH_MUXPOS_t; - -/* Internal input multiplexer selections */ -typedef enum ADC_CH_MUXINT_enum -{ - ADC_CH_MUXINT_TEMP_gc = (0x00<<3), /* Temperature Reference */ - ADC_CH_MUXINT_BANDGAP_gc = (0x01<<3), /* Bandgap Reference */ - ADC_CH_MUXINT_SCALEDVCC_gc = (0x02<<3), /* 1/10 scaled VCC */ - ADC_CH_MUXINT_DAC_gc = (0x03<<3), /* DAC output */ -} ADC_CH_MUXINT_t; - -/* Negative input multiplexer selection */ -typedef enum ADC_CH_MUXNEG_enum -{ - ADC_CH_MUXNEG_PIN0_gc = (0x00<<0), /* Input pin 0 (Input Mode = 2) */ - ADC_CH_MUXNEG_PIN1_gc = (0x01<<0), /* Input pin 1 (Input Mode = 2) */ - ADC_CH_MUXNEG_PIN2_gc = (0x02<<0), /* Input pin 2 (Input Mode = 2) */ - ADC_CH_MUXNEG_PIN3_gc = (0x03<<0), /* Input pin 3 (Input Mode = 2) */ - ADC_CH_MUXNEG_PIN4_gc = (0x00<<0), /* Input pin 4 (Input Mode = 3) */ - ADC_CH_MUXNEG_PIN5_gc = (0x01<<0), /* Input pin 5 (Input Mode = 3) */ - ADC_CH_MUXNEG_PIN6_gc = (0x02<<0), /* Input pin 6 (Input Mode = 3) */ - ADC_CH_MUXNEG_PIN7_gc = (0x03<<0), /* Input pin 7 (Input Mode = 3) */ - ADC_CH_MUXNEG_GND_MODE3_gc = (0x05<<0), /* PAD Ground (Input Mode = 2) */ - ADC_CH_MUXNEG_INTGND_MODE3_gc = (0x07<<0), /* Internal Ground (Input Mode = 2) */ - ADC_CH_MUXNEG_INTGND_MODE4_gc = (0x04<<0), /* Internal Ground (Input Mode = 3) */ - ADC_CH_MUXNEG_GND_MODE4_gc = (0x07<<0), /* PAD Ground (Input Mode = 3) */ -} ADC_CH_MUXNEG_t; - -/* Input mode */ -typedef enum ADC_CH_INPUTMODE_enum -{ - ADC_CH_INPUTMODE_INTERNAL_gc = (0x00<<0), /* Internal inputs, no gain */ - ADC_CH_INPUTMODE_SINGLEENDED_gc = (0x01<<0), /* Single-ended input, no gain */ - ADC_CH_INPUTMODE_DIFF_gc = (0x02<<0), /* Differential input, no gain */ - ADC_CH_INPUTMODE_DIFFWGAIN_gc = (0x03<<0), /* Differential input, with gain */ -} ADC_CH_INPUTMODE_t; - -/* Gain factor */ -typedef enum ADC_CH_GAIN_enum -{ - ADC_CH_GAIN_1X_gc = (0x00<<2), /* 1x gain */ - ADC_CH_GAIN_2X_gc = (0x01<<2), /* 2x gain */ - ADC_CH_GAIN_4X_gc = (0x02<<2), /* 4x gain */ - ADC_CH_GAIN_8X_gc = (0x03<<2), /* 8x gain */ - ADC_CH_GAIN_16X_gc = (0x04<<2), /* 16x gain */ - ADC_CH_GAIN_32X_gc = (0x05<<2), /* 32x gain */ - ADC_CH_GAIN_64X_gc = (0x06<<2), /* 64x gain */ - ADC_CH_GAIN_DIV2_gc = (0x07<<2), /* x/2 gain */ -} ADC_CH_GAIN_t; - -/* Conversion result resolution */ -typedef enum ADC_RESOLUTION_enum -{ - ADC_RESOLUTION_12BIT_gc = (0x00<<1), /* 12-bit right-adjusted result */ - ADC_RESOLUTION_8BIT_gc = (0x02<<1), /* 8-bit right-adjusted result */ - ADC_RESOLUTION_LEFT12BIT_gc = (0x03<<1), /* 12-bit left-adjusted result */ -} ADC_RESOLUTION_t; - -/* Current Limitation Mode */ -typedef enum ADC_CURRLIMIT_enum -{ - ADC_CURRLIMIT_NO_gc = (0x00<<5), /* No limit */ - ADC_CURRLIMIT_LOW_gc = (0x01<<5), /* Low current limit, max. sampling rate 1.5MSPS */ - ADC_CURRLIMIT_MED_gc = (0x02<<5), /* Medium current limit, max. sampling rate 1MSPS */ - ADC_CURRLIMIT_HIGH_gc = (0x03<<5), /* High current limit, max. sampling rate 0.5MSPS */ -} ADC_CURRLIMIT_t; - -/* Voltage reference selection */ -typedef enum ADC_REFSEL_enum -{ - ADC_REFSEL_INT1V_gc = (0x00<<4), /* Internal 1V */ - ADC_REFSEL_INTVCC_gc = (0x01<<4), /* Internal VCC / 1.6 */ - ADC_REFSEL_AREFA_gc = (0x02<<4), /* External reference on PORT A */ - ADC_REFSEL_AREFB_gc = (0x03<<4), /* External reference on PORT B */ - ADC_REFSEL_INTVCC2_gc = (0x04<<4), /* Internal VCC / 2 */ -} ADC_REFSEL_t; - -/* Channel sweep selection */ -typedef enum ADC_SWEEP_enum -{ - ADC_SWEEP_0_gc = (0x00<<6), /* ADC Channel 0 */ - ADC_SWEEP_01_gc = (0x01<<6), /* ADC Channel 0,1 */ - ADC_SWEEP_012_gc = (0x02<<6), /* ADC Channel 0,1,2 */ - ADC_SWEEP_0123_gc = (0x03<<6), /* ADC Channel 0,1,2,3 */ -} ADC_SWEEP_t; - -/* Event channel input selection */ -typedef enum ADC_EVSEL_enum -{ - ADC_EVSEL_0123_gc = (0x00<<3), /* Event Channel 0,1,2,3 */ - ADC_EVSEL_1234_gc = (0x01<<3), /* Event Channel 1,2,3,4 */ - ADC_EVSEL_2345_gc = (0x02<<3), /* Event Channel 2,3,4,5 */ - ADC_EVSEL_3456_gc = (0x03<<3), /* Event Channel 3,4,5,6 */ - ADC_EVSEL_4567_gc = (0x04<<3), /* Event Channel 4,5,6,7 */ - ADC_EVSEL_567_gc = (0x05<<3), /* Event Channel 5,6,7 */ - ADC_EVSEL_67_gc = (0x06<<3), /* Event Channel 6,7 */ - ADC_EVSEL_7_gc = (0x07<<3), /* Event Channel 7 */ -} ADC_EVSEL_t; - -/* Event action selection */ -typedef enum ADC_EVACT_enum -{ - ADC_EVACT_NONE_gc = (0x00<<0), /* No event action */ - ADC_EVACT_CH0_gc = (0x01<<0), /* First event triggers channel 0 */ - ADC_EVACT_CH01_gc = (0x02<<0), /* First two events trigger channel 0,1 */ - ADC_EVACT_CH012_gc = (0x03<<0), /* First three events trigger channel 0,1,2 */ - ADC_EVACT_CH0123_gc = (0x04<<0), /* Events trigger channel 0,1,2,3 */ - ADC_EVACT_SWEEP_gc = (0x05<<0), /* First event triggers sweep */ - ADC_EVACT_SYNCSWEEP_gc = (0x06<<0), /* The ADC is flushed and restarted for accurate timing */ -} ADC_EVACT_t; - -/* Interupt mode */ -typedef enum ADC_CH_INTMODE_enum -{ - ADC_CH_INTMODE_COMPLETE_gc = (0x00<<2), /* Interrupt on conversion complete */ - ADC_CH_INTMODE_BELOW_gc = (0x01<<2), /* Interrupt on result below compare value */ - ADC_CH_INTMODE_ABOVE_gc = (0x03<<2), /* Interrupt on result above compare value */ -} ADC_CH_INTMODE_t; - -/* Interrupt level */ -typedef enum ADC_CH_INTLVL_enum -{ - ADC_CH_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ - ADC_CH_INTLVL_LO_gc = (0x01<<0), /* Low level */ - ADC_CH_INTLVL_MED_gc = (0x02<<0), /* Medium level */ - ADC_CH_INTLVL_HI_gc = (0x03<<0), /* High level */ -} ADC_CH_INTLVL_t; - -/* DMA request selection */ -typedef enum ADC_DMASEL_enum -{ - ADC_DMASEL_OFF_gc = (0x00<<6), /* Combined DMA request OFF */ - ADC_DMASEL_CH01_gc = (0x01<<6), /* ADC Channel 0 or 1 */ - ADC_DMASEL_CH012_gc = (0x02<<6), /* ADC Channel 0 or 1 or 2 */ - ADC_DMASEL_CH0123_gc = (0x03<<6), /* ADC Channel 0 or 1 or 2 or 3 */ -} ADC_DMASEL_t; - -/* Clock prescaler */ -typedef enum ADC_PRESCALER_enum -{ - ADC_PRESCALER_DIV4_gc = (0x00<<0), /* Divide clock by 4 */ - ADC_PRESCALER_DIV8_gc = (0x01<<0), /* Divide clock by 8 */ - ADC_PRESCALER_DIV16_gc = (0x02<<0), /* Divide clock by 16 */ - ADC_PRESCALER_DIV32_gc = (0x03<<0), /* Divide clock by 32 */ - ADC_PRESCALER_DIV64_gc = (0x04<<0), /* Divide clock by 64 */ - ADC_PRESCALER_DIV128_gc = (0x05<<0), /* Divide clock by 128 */ - ADC_PRESCALER_DIV256_gc = (0x06<<0), /* Divide clock by 256 */ - ADC_PRESCALER_DIV512_gc = (0x07<<0), /* Divide clock by 512 */ -} ADC_PRESCALER_t; - - -/* --------------------------------------------------------------------------- -DAC - Digital/Analog Converter --------------------------------------------------------------------------- -*/ - -/* Digital-to-Analog Converter */ -typedef struct DAC_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t CTRLC; /* Control Register C */ - register8_t EVCTRL; /* Event Input Control */ - register8_t reserved_0x04; - register8_t STATUS; /* Status */ - register8_t reserved_0x06; - register8_t reserved_0x07; - register8_t CH0GAINCAL; /* Gain Calibration */ - register8_t CH0OFFSETCAL; /* Offset Calibration */ - register8_t CH1GAINCAL; /* Gain Calibration */ - register8_t CH1OFFSETCAL; /* Offset Calibration */ - register8_t reserved_0x0C; - register8_t reserved_0x0D; - register8_t reserved_0x0E; - register8_t reserved_0x0F; - register8_t reserved_0x10; - register8_t reserved_0x11; - register8_t reserved_0x12; - register8_t reserved_0x13; - register8_t reserved_0x14; - register8_t reserved_0x15; - register8_t reserved_0x16; - register8_t reserved_0x17; - _WORDREGISTER(CH0DATA); /* Channel 0 Data */ - _WORDREGISTER(CH1DATA); /* Channel 1 Data */ -} DAC_t; - -/* Output channel selection */ -typedef enum DAC_CHSEL_enum -{ - DAC_CHSEL_SINGLE_gc = (0x00<<5), /* Single channel operation (Channel 0 only) */ - DAC_CHSEL_SINGLE1_gc = (0x01<<5), /* Single channel operation (Channel 1 only) */ - DAC_CHSEL_DUAL_gc = (0x02<<5), /* Dual channel operation (Channel 0 and channel 1) */ -} DAC_CHSEL_t; - -/* Reference voltage selection */ -typedef enum DAC_REFSEL_enum -{ - DAC_REFSEL_INT1V_gc = (0x00<<3), /* Internal 1V */ - DAC_REFSEL_AVCC_gc = (0x01<<3), /* Analog supply voltage */ - DAC_REFSEL_AREFA_gc = (0x02<<3), /* External reference on AREF on PORTA */ - DAC_REFSEL_AREFB_gc = (0x03<<3), /* External reference on AREF on PORTB */ -} DAC_REFSEL_t; - -/* Event channel selection */ -typedef enum DAC_EVSEL_enum -{ - DAC_EVSEL_0_gc = (0x00<<0), /* Event Channel 0 */ - DAC_EVSEL_1_gc = (0x01<<0), /* Event Channel 1 */ - DAC_EVSEL_2_gc = (0x02<<0), /* Event Channel 2 */ - DAC_EVSEL_3_gc = (0x03<<0), /* Event Channel 3 */ - DAC_EVSEL_4_gc = (0x04<<0), /* Event Channel 4 */ - DAC_EVSEL_5_gc = (0x05<<0), /* Event Channel 5 */ - DAC_EVSEL_6_gc = (0x06<<0), /* Event Channel 6 */ - DAC_EVSEL_7_gc = (0x07<<0), /* Event Channel 7 */ -} DAC_EVSEL_t; - - -/* --------------------------------------------------------------------------- -AC - Analog Comparator --------------------------------------------------------------------------- -*/ - -/* Analog Comparator */ -typedef struct AC_struct -{ - register8_t AC0CTRL; /* Analog Comparator 0 Control */ - register8_t AC1CTRL; /* Analog Comparator 1 Control */ - register8_t AC0MUXCTRL; /* Analog Comparator 0 MUX Control */ - register8_t AC1MUXCTRL; /* Analog Comparator 1 MUX Control */ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t WINCTRL; /* Window Mode Control */ - register8_t STATUS; /* Status */ -} AC_t; - -/* Interrupt mode */ -typedef enum AC_INTMODE_enum -{ - AC_INTMODE_BOTHEDGES_gc = (0x00<<6), /* Interrupt on both edges */ - AC_INTMODE_FALLING_gc = (0x02<<6), /* Interrupt on falling edge */ - AC_INTMODE_RISING_gc = (0x03<<6), /* Interrupt on rising edge */ -} AC_INTMODE_t; - -/* Interrupt level */ -typedef enum AC_INTLVL_enum -{ - AC_INTLVL_OFF_gc = (0x00<<4), /* Interrupt disabled */ - AC_INTLVL_LO_gc = (0x01<<4), /* Low level */ - AC_INTLVL_MED_gc = (0x02<<4), /* Medium level */ - AC_INTLVL_HI_gc = (0x03<<4), /* High level */ -} AC_INTLVL_t; - -/* Hysteresis mode selection */ -typedef enum AC_HYSMODE_enum -{ - AC_HYSMODE_NO_gc = (0x00<<1), /* No hysteresis */ - AC_HYSMODE_SMALL_gc = (0x01<<1), /* Small hysteresis */ - AC_HYSMODE_LARGE_gc = (0x02<<1), /* Large hysteresis */ -} AC_HYSMODE_t; - -/* Positive input multiplexer selection */ -typedef enum AC_MUXPOS_enum -{ - AC_MUXPOS_PIN0_gc = (0x00<<3), /* Pin 0 */ - AC_MUXPOS_PIN1_gc = (0x01<<3), /* Pin 1 */ - AC_MUXPOS_PIN2_gc = (0x02<<3), /* Pin 2 */ - AC_MUXPOS_PIN3_gc = (0x03<<3), /* Pin 3 */ - AC_MUXPOS_PIN4_gc = (0x04<<3), /* Pin 4 */ - AC_MUXPOS_PIN5_gc = (0x05<<3), /* Pin 5 */ - AC_MUXPOS_PIN6_gc = (0x06<<3), /* Pin 6 */ - AC_MUXPOS_DAC_gc = (0x07<<3), /* DAC output */ -} AC_MUXPOS_t; - -/* Negative input multiplexer selection */ -typedef enum AC_MUXNEG_enum -{ - AC_MUXNEG_PIN0_gc = (0x00<<0), /* Pin 0 */ - AC_MUXNEG_PIN1_gc = (0x01<<0), /* Pin 1 */ - AC_MUXNEG_PIN3_gc = (0x02<<0), /* Pin 3 */ - AC_MUXNEG_PIN5_gc = (0x03<<0), /* Pin 5 */ - AC_MUXNEG_PIN7_gc = (0x04<<0), /* Pin 7 */ - AC_MUXNEG_DAC_gc = (0x05<<0), /* DAC output */ - AC_MUXNEG_BANDGAP_gc = (0x06<<0), /* Bandgap Reference */ - AC_MUXNEG_SCALER_gc = (0x07<<0), /* Internal voltage scaler */ -} AC_MUXNEG_t; - -/* Windows interrupt mode */ -typedef enum AC_WINTMODE_enum -{ - AC_WINTMODE_ABOVE_gc = (0x00<<2), /* Interrupt on above window */ - AC_WINTMODE_INSIDE_gc = (0x01<<2), /* Interrupt on inside window */ - AC_WINTMODE_BELOW_gc = (0x02<<2), /* Interrupt on below window */ - AC_WINTMODE_OUTSIDE_gc = (0x03<<2), /* Interrupt on outside window */ -} AC_WINTMODE_t; - -/* Window interrupt level */ -typedef enum AC_WINTLVL_enum -{ - AC_WINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ - AC_WINTLVL_LO_gc = (0x01<<0), /* Low priority */ - AC_WINTLVL_MED_gc = (0x02<<0), /* Medium priority */ - AC_WINTLVL_HI_gc = (0x03<<0), /* High priority */ -} AC_WINTLVL_t; - -/* Window mode state */ -typedef enum AC_WSTATE_enum -{ - AC_WSTATE_ABOVE_gc = (0x00<<6), /* Signal above window */ - AC_WSTATE_INSIDE_gc = (0x01<<6), /* Signal inside window */ - AC_WSTATE_BELOW_gc = (0x02<<6), /* Signal below window */ -} AC_WSTATE_t; - - -/* --------------------------------------------------------------------------- -RTC - Real-Time Counter --------------------------------------------------------------------------- -*/ - -/* Real-Time Counter */ -typedef struct RTC_struct -{ - register8_t CTRL; /* Control Register */ - register8_t STATUS; /* Status Register */ - register8_t INTCTRL; /* Interrupt Control Register */ - register8_t INTFLAGS; /* Interrupt Flags */ - register8_t TEMP; /* Temporary register */ - register8_t reserved_0x05; - register8_t reserved_0x06; - register8_t reserved_0x07; - _WORDREGISTER(CNT); /* Count Register */ - _WORDREGISTER(PER); /* Period Register */ - _WORDREGISTER(COMP); /* Compare Register */ -} RTC_t; - -/* Prescaler Factor */ -typedef enum RTC_PRESCALER_enum -{ - RTC_PRESCALER_OFF_gc = (0x00<<0), /* RTC Off */ - RTC_PRESCALER_DIV1_gc = (0x01<<0), /* RTC Clock */ - RTC_PRESCALER_DIV2_gc = (0x02<<0), /* RTC Clock / 2 */ - RTC_PRESCALER_DIV8_gc = (0x03<<0), /* RTC Clock / 8 */ - RTC_PRESCALER_DIV16_gc = (0x04<<0), /* RTC Clock / 16 */ - RTC_PRESCALER_DIV64_gc = (0x05<<0), /* RTC Clock / 64 */ - RTC_PRESCALER_DIV256_gc = (0x06<<0), /* RTC Clock / 256 */ - RTC_PRESCALER_DIV1024_gc = (0x07<<0), /* RTC Clock / 1024 */ -} RTC_PRESCALER_t; - -/* Compare Interrupt level */ -typedef enum RTC_COMPINTLVL_enum -{ - RTC_COMPINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ - RTC_COMPINTLVL_LO_gc = (0x01<<2), /* Low Level */ - RTC_COMPINTLVL_MED_gc = (0x02<<2), /* Medium Level */ - RTC_COMPINTLVL_HI_gc = (0x03<<2), /* High Level */ -} RTC_COMPINTLVL_t; - -/* Overflow Interrupt level */ -typedef enum RTC_OVFINTLVL_enum -{ - RTC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - RTC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ - RTC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ - RTC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ -} RTC_OVFINTLVL_t; - - -/* --------------------------------------------------------------------------- -TWI - Two-Wire Interface --------------------------------------------------------------------------- -*/ - -/* */ -typedef struct TWI_MASTER_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t CTRLC; /* Control Register C */ - register8_t STATUS; /* Status Register */ - register8_t BAUD; /* Baurd Rate Control Register */ - register8_t ADDR; /* Address Register */ - register8_t DATA; /* Data Register */ -} TWI_MASTER_t; - - -/* */ -typedef struct TWI_SLAVE_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t STATUS; /* Status Register */ - register8_t ADDR; /* Address Register */ - register8_t DATA; /* Data Register */ - register8_t ADDRMASK; /* Address Mask Register */ -} TWI_SLAVE_t; - - -/* Two-Wire Interface */ -typedef struct TWI_struct -{ - register8_t CTRL; /* TWI Common Control Register */ - TWI_MASTER_t MASTER; /* TWI master module */ - TWI_SLAVE_t SLAVE; /* TWI slave module */ -} TWI_t; - -/* SDA Hold Time */ -typedef enum TWI_SDAHOLD_enum -{ - TWI_SDAHOLD_OFF_gc = (0x00<<1), /* SDA Hold Time off */ - TWI_SDAHOLD_50NS_gc = (0x01<<1), /* SDA Hold Time 50 ns */ - TWI_SDAHOLD_300NS_gc = (0x02<<1), /* SDA Hold Time 300 ns */ - TWI_SDAHOLD_400NS_gc = (0x03<<1), /* SDA Hold Time 400 ns */ -} TWI_SDAHOLD_t; - -/* Master Interrupt Level */ -typedef enum TWI_MASTER_INTLVL_enum -{ - TWI_MASTER_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ - TWI_MASTER_INTLVL_LO_gc = (0x01<<6), /* Low Level */ - TWI_MASTER_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ - TWI_MASTER_INTLVL_HI_gc = (0x03<<6), /* High Level */ -} TWI_MASTER_INTLVL_t; - -/* Inactive Timeout */ -typedef enum TWI_MASTER_TIMEOUT_enum -{ - TWI_MASTER_TIMEOUT_DISABLED_gc = (0x00<<2), /* Bus Timeout Disabled */ - TWI_MASTER_TIMEOUT_50US_gc = (0x01<<2), /* 50 Microseconds */ - TWI_MASTER_TIMEOUT_100US_gc = (0x02<<2), /* 100 Microseconds */ - TWI_MASTER_TIMEOUT_200US_gc = (0x03<<2), /* 200 Microseconds */ -} TWI_MASTER_TIMEOUT_t; - -/* Master Command */ -typedef enum TWI_MASTER_CMD_enum -{ - TWI_MASTER_CMD_NOACT_gc = (0x00<<0), /* No Action */ - TWI_MASTER_CMD_REPSTART_gc = (0x01<<0), /* Issue Repeated Start Condition */ - TWI_MASTER_CMD_RECVTRANS_gc = (0x02<<0), /* Receive or Transmit Data */ - TWI_MASTER_CMD_STOP_gc = (0x03<<0), /* Issue Stop Condition */ -} TWI_MASTER_CMD_t; - -/* Master Bus State */ -typedef enum TWI_MASTER_BUSSTATE_enum -{ - TWI_MASTER_BUSSTATE_UNKNOWN_gc = (0x00<<0), /* Unknown Bus State */ - TWI_MASTER_BUSSTATE_IDLE_gc = (0x01<<0), /* Bus is Idle */ - TWI_MASTER_BUSSTATE_OWNER_gc = (0x02<<0), /* This Module Controls The Bus */ - TWI_MASTER_BUSSTATE_BUSY_gc = (0x03<<0), /* The Bus is Busy */ -} TWI_MASTER_BUSSTATE_t; - -/* Slave Interrupt Level */ -typedef enum TWI_SLAVE_INTLVL_enum -{ - TWI_SLAVE_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ - TWI_SLAVE_INTLVL_LO_gc = (0x01<<6), /* Low Level */ - TWI_SLAVE_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ - TWI_SLAVE_INTLVL_HI_gc = (0x03<<6), /* High Level */ -} TWI_SLAVE_INTLVL_t; - -/* Slave Command */ -typedef enum TWI_SLAVE_CMD_enum -{ - TWI_SLAVE_CMD_NOACT_gc = (0x00<<0), /* No Action */ - TWI_SLAVE_CMD_COMPTRANS_gc = (0x02<<0), /* Used To Complete a Transaction */ - TWI_SLAVE_CMD_RESPONSE_gc = (0x03<<0), /* Used in Response to Address/Data Interrupt */ -} TWI_SLAVE_CMD_t; - - -/* --------------------------------------------------------------------------- -USB - USB --------------------------------------------------------------------------- -*/ - -/* USB Endpoint */ -typedef struct USB_EP_struct -{ - register8_t STATUS; /* Endpoint Status */ - register8_t CTRL; /* Endpoint Control */ - _WORDREGISTER(CNT); /* USB Endpoint Counter */ - _WORDREGISTER(DATAPTR); /* Data Pointer */ - _WORDREGISTER(AUXDATA); /* Auxiliary Data */ -} USB_EP_t; - - -/* Universal Serial Bus */ -typedef struct USB_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t STATUS; /* Status Register */ - register8_t ADDR; /* Address Register */ - register8_t FIFOWP; /* FIFO Write Pointer Register */ - register8_t FIFORP; /* FIFO Read Pointer Register */ - _WORDREGISTER(EPPTR); /* Endpoint Configuration Table Pointer */ - register8_t INTCTRLA; /* Interrupt Control Register A */ - register8_t INTCTRLB; /* Interrupt Control Register B */ - register8_t INTFLAGSACLR; /* Clear Interrupt Flag Register A */ - register8_t INTFLAGSASET; /* Set Interrupt Flag Register A */ - register8_t INTFLAGSBCLR; /* Clear Interrupt Flag Register B */ - register8_t INTFLAGSBSET; /* Set Interrupt Flag Register B */ - register8_t reserved_0x0E; - register8_t reserved_0x0F; - register8_t reserved_0x10; - register8_t reserved_0x11; - register8_t reserved_0x12; - register8_t reserved_0x13; - register8_t reserved_0x14; - register8_t reserved_0x15; - register8_t reserved_0x16; - register8_t reserved_0x17; - register8_t reserved_0x18; - register8_t reserved_0x19; - register8_t reserved_0x1A; - register8_t reserved_0x1B; - register8_t reserved_0x1C; - register8_t reserved_0x1D; - register8_t reserved_0x1E; - register8_t reserved_0x1F; - register8_t reserved_0x20; - register8_t reserved_0x21; - register8_t reserved_0x22; - register8_t reserved_0x23; - register8_t reserved_0x24; - register8_t reserved_0x25; - register8_t reserved_0x26; - register8_t reserved_0x27; - register8_t reserved_0x28; - register8_t reserved_0x29; - register8_t reserved_0x2A; - register8_t reserved_0x2B; - register8_t reserved_0x2C; - register8_t reserved_0x2D; - register8_t reserved_0x2E; - register8_t reserved_0x2F; - register8_t reserved_0x30; - register8_t reserved_0x31; - register8_t reserved_0x32; - register8_t reserved_0x33; - register8_t reserved_0x34; - register8_t reserved_0x35; - register8_t reserved_0x36; - register8_t reserved_0x37; - register8_t reserved_0x38; - register8_t reserved_0x39; - register8_t CAL0; /* Calibration Byte 0 */ - register8_t CAL1; /* Calibration Byte 1 */ -} USB_t; - - -/* USB Endpoint Table */ -typedef struct USB_EP_TABLE_struct -{ - USB_EP_t EP0OUT; /* Endpoint 0 */ - USB_EP_t EP0IN; /* Endpoint 0 */ - USB_EP_t EP1OUT; /* Endpoint 1 */ - USB_EP_t EP1IN; /* Endpoint 1 */ - USB_EP_t EP2OUT; /* Endpoint 2 */ - USB_EP_t EP2IN; /* Endpoint 2 */ - USB_EP_t EP3OUT; /* Endpoint 3 */ - USB_EP_t EP3IN; /* Endpoint 3 */ - USB_EP_t EP4OUT; /* Endpoint 4 */ - USB_EP_t EP4IN; /* Endpoint 4 */ - USB_EP_t EP5OUT; /* Endpoint 5 */ - USB_EP_t EP5IN; /* Endpoint 5 */ - USB_EP_t EP6OUT; /* Endpoint 6 */ - USB_EP_t EP6IN; /* Endpoint 6 */ - USB_EP_t EP7OUT; /* Endpoint 7 */ - USB_EP_t EP7IN; /* Endpoint 7 */ - USB_EP_t EP8OUT; /* Endpoint 8 */ - USB_EP_t EP8IN; /* Endpoint 8 */ - USB_EP_t EP9OUT; /* Endpoint 9 */ - USB_EP_t EP9IN; /* Endpoint 9 */ - USB_EP_t EP10OUT; /* Endpoint 10 */ - USB_EP_t EP10IN; /* Endpoint 10 */ - USB_EP_t EP11OUT; /* Endpoint 11 */ - USB_EP_t EP11IN; /* Endpoint 11 */ - USB_EP_t EP12OUT; /* Endpoint 12 */ - USB_EP_t EP12IN; /* Endpoint 12 */ - USB_EP_t EP13OUT; /* Endpoint 13 */ - USB_EP_t EP13IN; /* Endpoint 13 */ - USB_EP_t EP14OUT; /* Endpoint 14 */ - USB_EP_t EP14IN; /* Endpoint 14 */ - USB_EP_t EP15OUT; /* Endpoint 15 */ - USB_EP_t EP15IN; /* Endpoint 15 */ - register8_t reserved_0x100; - register8_t reserved_0x101; - register8_t reserved_0x102; - register8_t reserved_0x103; - register8_t reserved_0x104; - register8_t reserved_0x105; - register8_t reserved_0x106; - register8_t reserved_0x107; - register8_t reserved_0x108; - register8_t reserved_0x109; - register8_t reserved_0x10A; - register8_t reserved_0x10B; - register8_t reserved_0x10C; - register8_t reserved_0x10D; - register8_t reserved_0x10E; - register8_t reserved_0x10F; - register8_t FRAMENUML; /* Frame Number Low Byte */ - register8_t FRAMENUMH; /* Frame Number High Byte */ -} USB_EP_TABLE_t; - -/* Interrupt level */ -typedef enum USB_INTLVL_enum -{ - USB_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ - USB_INTLVL_LO_gc = (0x01<<0), /* Low level */ - USB_INTLVL_MED_gc = (0x02<<0), /* Medium level */ - USB_INTLVL_HI_gc = (0x03<<0), /* High level */ -} USB_INTLVL_t; - -/* USB Endpoint Type */ -typedef enum USB_EP_TYPE_enum -{ - USB_EP_TYPE_DISABLE_gc = (0x00<<6), /* Endpoint Disabled */ - USB_EP_TYPE_CONTROL_gc = (0x01<<6), /* Control */ - USB_EP_TYPE_BULK_gc = (0x02<<6), /* Bulk/Interrupt */ - USB_EP_TYPE_ISOCHRONOUS_gc = (0x03<<6), /* Isochronous */ -} USB_EP_TYPE_t; - -/* USB Endpoint Buffersize */ -typedef enum USB_EP_BUFSIZE_enum -{ - USB_EP_BUFSIZE_8_gc = (0x00<<0), /* 8 bytes buffer size */ - USB_EP_BUFSIZE_16_gc = (0x01<<0), /* 16 bytes buffer size */ - USB_EP_BUFSIZE_32_gc = (0x02<<0), /* 32 bytes buffer size */ - USB_EP_BUFSIZE_64_gc = (0x03<<0), /* 64 bytes buffer size */ - USB_EP_BUFSIZE_128_gc = (0x04<<0), /* 128 bytes buffer size */ - USB_EP_BUFSIZE_256_gc = (0x05<<0), /* 256 bytes buffer size */ - USB_EP_BUFSIZE_512_gc = (0x06<<0), /* 512 bytes buffer size */ - USB_EP_BUFSIZE_1023_gc = (0x07<<0), /* 1023 bytes buffer size */ -} USB_EP_BUFSIZE_t; - - -/* --------------------------------------------------------------------------- -PORT - I/O Port Configuration --------------------------------------------------------------------------- -*/ - -/* I/O Ports */ -typedef struct PORT_struct -{ - register8_t DIR; /* I/O Port Data Direction */ - register8_t DIRSET; /* I/O Port Data Direction Set */ - register8_t DIRCLR; /* I/O Port Data Direction Clear */ - register8_t DIRTGL; /* I/O Port Data Direction Toggle */ - register8_t OUT; /* I/O Port Output */ - register8_t OUTSET; /* I/O Port Output Set */ - register8_t OUTCLR; /* I/O Port Output Clear */ - register8_t OUTTGL; /* I/O Port Output Toggle */ - register8_t IN; /* I/O port Input */ - register8_t INTCTRL; /* Interrupt Control Register */ - register8_t INT0MASK; /* Port Interrupt 0 Mask */ - register8_t INT1MASK; /* Port Interrupt 1 Mask */ - register8_t INTFLAGS; /* Interrupt Flag Register */ - register8_t reserved_0x0D; - register8_t REMAP; /* I/O Port Pin Remap Register */ - register8_t reserved_0x0F; - register8_t PIN0CTRL; /* Pin 0 Control Register */ - register8_t PIN1CTRL; /* Pin 1 Control Register */ - register8_t PIN2CTRL; /* Pin 2 Control Register */ - register8_t PIN3CTRL; /* Pin 3 Control Register */ - register8_t PIN4CTRL; /* Pin 4 Control Register */ - register8_t PIN5CTRL; /* Pin 5 Control Register */ - register8_t PIN6CTRL; /* Pin 6 Control Register */ - register8_t PIN7CTRL; /* Pin 7 Control Register */ -} PORT_t; - -/* Port Interrupt 0 Level */ -typedef enum PORT_INT0LVL_enum -{ - PORT_INT0LVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - PORT_INT0LVL_LO_gc = (0x01<<0), /* Low Level */ - PORT_INT0LVL_MED_gc = (0x02<<0), /* Medium Level */ - PORT_INT0LVL_HI_gc = (0x03<<0), /* High Level */ -} PORT_INT0LVL_t; - -/* Port Interrupt 1 Level */ -typedef enum PORT_INT1LVL_enum -{ - PORT_INT1LVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ - PORT_INT1LVL_LO_gc = (0x01<<2), /* Low Level */ - PORT_INT1LVL_MED_gc = (0x02<<2), /* Medium Level */ - PORT_INT1LVL_HI_gc = (0x03<<2), /* High Level */ -} PORT_INT1LVL_t; - -/* Output/Pull Configuration */ -typedef enum PORT_OPC_enum -{ - PORT_OPC_TOTEM_gc = (0x00<<3), /* Totempole */ - PORT_OPC_BUSKEEPER_gc = (0x01<<3), /* Totempole w/ Bus keeper on Input and Output */ - PORT_OPC_PULLDOWN_gc = (0x02<<3), /* Totempole w/ Pull-down on Input */ - PORT_OPC_PULLUP_gc = (0x03<<3), /* Totempole w/ Pull-up on Input */ - PORT_OPC_WIREDOR_gc = (0x04<<3), /* Wired OR */ - PORT_OPC_WIREDAND_gc = (0x05<<3), /* Wired AND */ - PORT_OPC_WIREDORPULL_gc = (0x06<<3), /* Wired OR w/ Pull-down */ - PORT_OPC_WIREDANDPULL_gc = (0x07<<3), /* Wired AND w/ Pull-up */ -} PORT_OPC_t; - -/* Input/Sense Configuration */ -typedef enum PORT_ISC_enum -{ - PORT_ISC_BOTHEDGES_gc = (0x00<<0), /* Sense Both Edges */ - PORT_ISC_RISING_gc = (0x01<<0), /* Sense Rising Edge */ - PORT_ISC_FALLING_gc = (0x02<<0), /* Sense Falling Edge */ - PORT_ISC_LEVEL_gc = (0x03<<0), /* Sense Level (Transparent For Events) */ - PORT_ISC_INPUT_DISABLE_gc = (0x07<<0), /* Disable Digital Input Buffer */ -} PORT_ISC_t; - - -/* --------------------------------------------------------------------------- -TC - 16-bit Timer/Counter With PWM --------------------------------------------------------------------------- -*/ - -/* 16-bit Timer/Counter 0 */ -typedef struct TC0_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t CTRLC; /* Control register C */ - register8_t CTRLD; /* Control Register D */ - register8_t CTRLE; /* Control Register E */ - register8_t reserved_0x05; - register8_t INTCTRLA; /* Interrupt Control Register A */ - register8_t INTCTRLB; /* Interrupt Control Register B */ - register8_t CTRLFCLR; /* Control Register F Clear */ - register8_t CTRLFSET; /* Control Register F Set */ - register8_t CTRLGCLR; /* Control Register G Clear */ - register8_t CTRLGSET; /* Control Register G Set */ - register8_t INTFLAGS; /* Interrupt Flag Register */ - register8_t reserved_0x0D; - register8_t reserved_0x0E; - register8_t TEMP; /* Temporary Register For 16-bit Access */ - register8_t reserved_0x10; - register8_t reserved_0x11; - register8_t reserved_0x12; - register8_t reserved_0x13; - register8_t reserved_0x14; - register8_t reserved_0x15; - register8_t reserved_0x16; - register8_t reserved_0x17; - register8_t reserved_0x18; - register8_t reserved_0x19; - register8_t reserved_0x1A; - register8_t reserved_0x1B; - register8_t reserved_0x1C; - register8_t reserved_0x1D; - register8_t reserved_0x1E; - register8_t reserved_0x1F; - _WORDREGISTER(CNT); /* Count */ - register8_t reserved_0x22; - register8_t reserved_0x23; - register8_t reserved_0x24; - register8_t reserved_0x25; - _WORDREGISTER(PER); /* Period */ - _WORDREGISTER(CCA); /* Compare or Capture A */ - _WORDREGISTER(CCB); /* Compare or Capture B */ - _WORDREGISTER(CCC); /* Compare or Capture C */ - _WORDREGISTER(CCD); /* Compare or Capture D */ - register8_t reserved_0x30; - register8_t reserved_0x31; - register8_t reserved_0x32; - register8_t reserved_0x33; - register8_t reserved_0x34; - register8_t reserved_0x35; - _WORDREGISTER(PERBUF); /* Period Buffer */ - _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ - _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ - _WORDREGISTER(CCCBUF); /* Compare Or Capture C Buffer */ - _WORDREGISTER(CCDBUF); /* Compare Or Capture D Buffer */ -} TC0_t; - - -/* 16-bit Timer/Counter 1 */ -typedef struct TC1_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t CTRLC; /* Control register C */ - register8_t CTRLD; /* Control Register D */ - register8_t CTRLE; /* Control Register E */ - register8_t reserved_0x05; - register8_t INTCTRLA; /* Interrupt Control Register A */ - register8_t INTCTRLB; /* Interrupt Control Register B */ - register8_t CTRLFCLR; /* Control Register F Clear */ - register8_t CTRLFSET; /* Control Register F Set */ - register8_t CTRLGCLR; /* Control Register G Clear */ - register8_t CTRLGSET; /* Control Register G Set */ - register8_t INTFLAGS; /* Interrupt Flag Register */ - register8_t reserved_0x0D; - register8_t reserved_0x0E; - register8_t TEMP; /* Temporary Register For 16-bit Access */ - register8_t reserved_0x10; - register8_t reserved_0x11; - register8_t reserved_0x12; - register8_t reserved_0x13; - register8_t reserved_0x14; - register8_t reserved_0x15; - register8_t reserved_0x16; - register8_t reserved_0x17; - register8_t reserved_0x18; - register8_t reserved_0x19; - register8_t reserved_0x1A; - register8_t reserved_0x1B; - register8_t reserved_0x1C; - register8_t reserved_0x1D; - register8_t reserved_0x1E; - register8_t reserved_0x1F; - _WORDREGISTER(CNT); /* Count */ - register8_t reserved_0x22; - register8_t reserved_0x23; - register8_t reserved_0x24; - register8_t reserved_0x25; - _WORDREGISTER(PER); /* Period */ - _WORDREGISTER(CCA); /* Compare or Capture A */ - _WORDREGISTER(CCB); /* Compare or Capture B */ - register8_t reserved_0x2C; - register8_t reserved_0x2D; - register8_t reserved_0x2E; - register8_t reserved_0x2F; - register8_t reserved_0x30; - register8_t reserved_0x31; - register8_t reserved_0x32; - register8_t reserved_0x33; - register8_t reserved_0x34; - register8_t reserved_0x35; - _WORDREGISTER(PERBUF); /* Period Buffer */ - _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ - _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ -} TC1_t; - -/* Clock Selection */ -typedef enum TC_CLKSEL_enum -{ - TC_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */ - TC_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */ - TC_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */ - TC_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */ - TC_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */ - TC_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */ - TC_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */ - TC_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */ - TC_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */ - TC_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */ - TC_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */ - TC_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */ - TC_CLKSEL_EVCH4_gc = (0x0C<<0), /* Event Channel 4 */ - TC_CLKSEL_EVCH5_gc = (0x0D<<0), /* Event Channel 5 */ - TC_CLKSEL_EVCH6_gc = (0x0E<<0), /* Event Channel 6 */ - TC_CLKSEL_EVCH7_gc = (0x0F<<0), /* Event Channel 7 */ -} TC_CLKSEL_t; - -/* Waveform Generation Mode */ -typedef enum TC_WGMODE_enum -{ - TC_WGMODE_NORMAL_gc = (0x00<<0), /* Normal Mode */ - TC_WGMODE_FRQ_gc = (0x01<<0), /* Frequency Generation Mode */ - TC_WGMODE_SINGLESLOPE_gc = (0x03<<0), /* Single Slope */ - TC_WGMODE_SS_gc = (0x03<<0), /* Single Slope */ - TC_WGMODE_DSTOP_gc = (0x05<<0), /* Dual Slope, Update on TOP */ - TC_WGMODE_DS_T_gc = (0x05<<0), /* Dual Slope, Update on TOP */ - TC_WGMODE_DSBOTH_gc = (0x06<<0), /* Dual Slope, Update on both TOP and BOTTOM */ - TC_WGMODE_DS_TB_gc = (0x06<<0), /* Dual Slope, Update on both TOP and BOTTOM */ - TC_WGMODE_DSBOTTOM_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */ - TC_WGMODE_DS_B_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */ -} TC_WGMODE_t; - -/* Byte Mode */ -typedef enum TC_BYTEM_enum -{ - TC_BYTEM_NORMAL_gc = (0x00<<0), /* 16-bit mode */ - TC_BYTEM_BYTEMODE_gc = (0x01<<0), /* Timer/Counter operating in byte mode only */ - TC_BYTEM_SPLITMODE_gc = (0x02<<0), /* Timer/Counter split into two 8-bit Counters (TC2) */ -} TC_BYTEM_t; - -/* Event Action */ -typedef enum TC_EVACT_enum -{ - TC_EVACT_OFF_gc = (0x00<<5), /* No Event Action */ - TC_EVACT_CAPT_gc = (0x01<<5), /* Input Capture */ - TC_EVACT_UPDOWN_gc = (0x02<<5), /* Externally Controlled Up/Down Count */ - TC_EVACT_QDEC_gc = (0x03<<5), /* Quadrature Decode */ - TC_EVACT_RESTART_gc = (0x04<<5), /* Restart */ - TC_EVACT_FRQ_gc = (0x05<<5), /* Frequency Capture */ - TC_EVACT_PW_gc = (0x06<<5), /* Pulse-width Capture */ -} TC_EVACT_t; - -/* Event Selection */ -typedef enum TC_EVSEL_enum -{ - TC_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ - TC_EVSEL_CH0_gc = (0x08<<0), /* Event Channel 0 */ - TC_EVSEL_CH1_gc = (0x09<<0), /* Event Channel 1 */ - TC_EVSEL_CH2_gc = (0x0A<<0), /* Event Channel 2 */ - TC_EVSEL_CH3_gc = (0x0B<<0), /* Event Channel 3 */ - TC_EVSEL_CH4_gc = (0x0C<<0), /* Event Channel 4 */ - TC_EVSEL_CH5_gc = (0x0D<<0), /* Event Channel 5 */ - TC_EVSEL_CH6_gc = (0x0E<<0), /* Event Channel 6 */ - TC_EVSEL_CH7_gc = (0x0F<<0), /* Event Channel 7 */ -} TC_EVSEL_t; - -/* Error Interrupt Level */ -typedef enum TC_ERRINTLVL_enum -{ - TC_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ - TC_ERRINTLVL_LO_gc = (0x01<<2), /* Low Level */ - TC_ERRINTLVL_MED_gc = (0x02<<2), /* Medium Level */ - TC_ERRINTLVL_HI_gc = (0x03<<2), /* High Level */ -} TC_ERRINTLVL_t; - -/* Overflow Interrupt Level */ -typedef enum TC_OVFINTLVL_enum -{ - TC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - TC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ - TC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ - TC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ -} TC_OVFINTLVL_t; - -/* Compare or Capture D Interrupt Level */ -typedef enum TC_CCDINTLVL_enum -{ - TC_CCDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ - TC_CCDINTLVL_LO_gc = (0x01<<6), /* Low Level */ - TC_CCDINTLVL_MED_gc = (0x02<<6), /* Medium Level */ - TC_CCDINTLVL_HI_gc = (0x03<<6), /* High Level */ -} TC_CCDINTLVL_t; - -/* Compare or Capture C Interrupt Level */ -typedef enum TC_CCCINTLVL_enum -{ - TC_CCCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ - TC_CCCINTLVL_LO_gc = (0x01<<4), /* Low Level */ - TC_CCCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ - TC_CCCINTLVL_HI_gc = (0x03<<4), /* High Level */ -} TC_CCCINTLVL_t; - -/* Compare or Capture B Interrupt Level */ -typedef enum TC_CCBINTLVL_enum -{ - TC_CCBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ - TC_CCBINTLVL_LO_gc = (0x01<<2), /* Low Level */ - TC_CCBINTLVL_MED_gc = (0x02<<2), /* Medium Level */ - TC_CCBINTLVL_HI_gc = (0x03<<2), /* High Level */ -} TC_CCBINTLVL_t; - -/* Compare or Capture A Interrupt Level */ -typedef enum TC_CCAINTLVL_enum -{ - TC_CCAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - TC_CCAINTLVL_LO_gc = (0x01<<0), /* Low Level */ - TC_CCAINTLVL_MED_gc = (0x02<<0), /* Medium Level */ - TC_CCAINTLVL_HI_gc = (0x03<<0), /* High Level */ -} TC_CCAINTLVL_t; - -/* Timer/Counter Command */ -typedef enum TC_CMD_enum -{ - TC_CMD_NONE_gc = (0x00<<2), /* No Command */ - TC_CMD_UPDATE_gc = (0x01<<2), /* Force Update */ - TC_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ - TC_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ -} TC_CMD_t; - - -/* --------------------------------------------------------------------------- -TC2 - 16-bit Timer/Counter type 2 --------------------------------------------------------------------------- -*/ - -/* 16-bit Timer/Counter type 2 */ -typedef struct TC2_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t CTRLC; /* Control register C */ - register8_t reserved_0x03; - register8_t CTRLE; /* Control Register E */ - register8_t reserved_0x05; - register8_t INTCTRLA; /* Interrupt Control Register A */ - register8_t INTCTRLB; /* Interrupt Control Register B */ - register8_t reserved_0x08; - register8_t CTRLF; /* Control Register F */ - register8_t reserved_0x0A; - register8_t reserved_0x0B; - register8_t INTFLAGS; /* Interrupt Flag Register */ - register8_t reserved_0x0D; - register8_t reserved_0x0E; - register8_t reserved_0x0F; - register8_t reserved_0x10; - register8_t reserved_0x11; - register8_t reserved_0x12; - register8_t reserved_0x13; - register8_t reserved_0x14; - register8_t reserved_0x15; - register8_t reserved_0x16; - register8_t reserved_0x17; - register8_t reserved_0x18; - register8_t reserved_0x19; - register8_t reserved_0x1A; - register8_t reserved_0x1B; - register8_t reserved_0x1C; - register8_t reserved_0x1D; - register8_t reserved_0x1E; - register8_t reserved_0x1F; - register8_t LCNT; /* Low Byte Count */ - register8_t HCNT; /* High Byte Count */ - register8_t reserved_0x22; - register8_t reserved_0x23; - register8_t reserved_0x24; - register8_t reserved_0x25; - register8_t LPER; /* Low Byte Period */ - register8_t HPER; /* High Byte Period */ - register8_t LCMPA; /* Low Byte Compare A */ - register8_t HCMPA; /* High Byte Compare A */ - register8_t LCMPB; /* Low Byte Compare B */ - register8_t HCMPB; /* High Byte Compare B */ - register8_t LCMPC; /* Low Byte Compare C */ - register8_t HCMPC; /* High Byte Compare C */ - register8_t LCMPD; /* Low Byte Compare D */ - register8_t HCMPD; /* High Byte Compare D */ -} TC2_t; - -/* Clock Selection */ -typedef enum TC2_CLKSEL_enum -{ - TC2_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */ - TC2_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */ - TC2_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */ - TC2_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */ - TC2_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */ - TC2_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */ - TC2_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */ - TC2_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */ - TC2_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */ - TC2_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */ - TC2_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */ - TC2_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */ - TC2_CLKSEL_EVCH4_gc = (0x0C<<0), /* Event Channel 4 */ - TC2_CLKSEL_EVCH5_gc = (0x0D<<0), /* Event Channel 5 */ - TC2_CLKSEL_EVCH6_gc = (0x0E<<0), /* Event Channel 6 */ - TC2_CLKSEL_EVCH7_gc = (0x0F<<0), /* Event Channel 7 */ -} TC2_CLKSEL_t; - -/* Byte Mode */ -typedef enum TC2_BYTEM_enum -{ - TC2_BYTEM_NORMAL_gc = (0x00<<0), /* 16-bit mode */ - TC2_BYTEM_BYTEMODE_gc = (0x01<<0), /* Timer/Counter operating in byte mode only (TC2) */ - TC2_BYTEM_SPLITMODE_gc = (0x02<<0), /* Timer/Counter split into two 8-bit Counters */ -} TC2_BYTEM_t; - -/* High Byte Underflow Interrupt Level */ -typedef enum TC2_HUNFINTLVL_enum -{ - TC2_HUNFINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ - TC2_HUNFINTLVL_LO_gc = (0x01<<2), /* Low Level */ - TC2_HUNFINTLVL_MED_gc = (0x02<<2), /* Medium Level */ - TC2_HUNFINTLVL_HI_gc = (0x03<<2), /* High Level */ -} TC2_HUNFINTLVL_t; - -/* Low Byte Underflow Interrupt Level */ -typedef enum TC2_LUNFINTLVL_enum -{ - TC2_LUNFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - TC2_LUNFINTLVL_LO_gc = (0x01<<0), /* Low Level */ - TC2_LUNFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ - TC2_LUNFINTLVL_HI_gc = (0x03<<0), /* High Level */ -} TC2_LUNFINTLVL_t; - -/* Low Byte Compare D Interrupt Level */ -typedef enum TC2_LCMPDINTLVL_enum -{ - TC2_LCMPDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ - TC2_LCMPDINTLVL_LO_gc = (0x01<<6), /* Low Level */ - TC2_LCMPDINTLVL_MED_gc = (0x02<<6), /* Medium Level */ - TC2_LCMPDINTLVL_HI_gc = (0x03<<6), /* High Level */ -} TC2_LCMPDINTLVL_t; - -/* Low Byte Compare C Interrupt Level */ -typedef enum TC2_LCMPCINTLVL_enum -{ - TC2_LCMPCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ - TC2_LCMPCINTLVL_LO_gc = (0x01<<4), /* Low Level */ - TC2_LCMPCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ - TC2_LCMPCINTLVL_HI_gc = (0x03<<4), /* High Level */ -} TC2_LCMPCINTLVL_t; - -/* Low Byte Compare B Interrupt Level */ -typedef enum TC2_LCMPBINTLVL_enum -{ - TC2_LCMPBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ - TC2_LCMPBINTLVL_LO_gc = (0x01<<2), /* Low Level */ - TC2_LCMPBINTLVL_MED_gc = (0x02<<2), /* Medium Level */ - TC2_LCMPBINTLVL_HI_gc = (0x03<<2), /* High Level */ -} TC2_LCMPBINTLVL_t; - -/* Low Byte Compare A Interrupt Level */ -typedef enum TC2_LCMPAINTLVL_enum -{ - TC2_LCMPAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - TC2_LCMPAINTLVL_LO_gc = (0x01<<0), /* Low Level */ - TC2_LCMPAINTLVL_MED_gc = (0x02<<0), /* Medium Level */ - TC2_LCMPAINTLVL_HI_gc = (0x03<<0), /* High Level */ -} TC2_LCMPAINTLVL_t; - -/* Timer/Counter Command */ -typedef enum TC2_CMD_enum -{ - TC2_CMD_NONE_gc = (0x00<<2), /* No Command */ - TC2_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ - TC2_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ -} TC2_CMD_t; - -/* Timer/Counter Command */ -typedef enum TC2_CMDEN_enum -{ - TC2_CMDEN_LOW_gc = (0x01<<0), /* Low Byte Timer/Counter */ - TC2_CMDEN_HIGH_gc = (0x02<<0), /* High Byte Timer/Counter */ - TC2_CMDEN_BOTH_gc = (0x03<<0), /* Both Low Byte and High Byte Timer/Counters */ -} TC2_CMDEN_t; - - -/* --------------------------------------------------------------------------- -AWEX - Timer/Counter Advanced Waveform Extension --------------------------------------------------------------------------- -*/ - -/* Advanced Waveform Extension */ -typedef struct AWEX_struct -{ - register8_t CTRL; /* Control Register */ - register8_t reserved_0x01; - register8_t FDEMASK; /* Fault Detection Event Mask */ - register8_t FDCTRL; /* Fault Detection Control Register */ - register8_t STATUS; /* Status Register */ - register8_t STATUSSET; /* Status Set Register */ - register8_t DTBOTH; /* Dead Time Both Sides */ - register8_t DTBOTHBUF; /* Dead Time Both Sides Buffer */ - register8_t DTLS; /* Dead Time Low Side */ - register8_t DTHS; /* Dead Time High Side */ - register8_t DTLSBUF; /* Dead Time Low Side Buffer */ - register8_t DTHSBUF; /* Dead Time High Side Buffer */ - register8_t OUTOVEN; /* Output Override Enable */ -} AWEX_t; - -/* Fault Detect Action */ -typedef enum AWEX_FDACT_enum -{ - AWEX_FDACT_NONE_gc = (0x00<<0), /* No Fault Protection */ - AWEX_FDACT_CLEAROE_gc = (0x01<<0), /* Clear Output Enable Bits */ - AWEX_FDACT_CLEARDIR_gc = (0x03<<0), /* Clear I/O Port Direction Bits */ -} AWEX_FDACT_t; - - -/* --------------------------------------------------------------------------- -HIRES - Timer/Counter High-Resolution Extension --------------------------------------------------------------------------- -*/ - -/* High-Resolution Extension */ -typedef struct HIRES_struct -{ - register8_t CTRLA; /* Control Register */ -} HIRES_t; - -/* High Resolution Enable */ -typedef enum HIRES_HREN_enum -{ - HIRES_HREN_NONE_gc = (0x00<<0), /* No Fault Protection */ - HIRES_HREN_TC0_gc = (0x01<<0), /* Enable High Resolution on Timer/Counter 0 */ - HIRES_HREN_TC1_gc = (0x02<<0), /* Enable High Resolution on Timer/Counter 1 */ - HIRES_HREN_BOTH_gc = (0x03<<0), /* Enable High Resolution both Timer/Counters */ -} HIRES_HREN_t; - - -/* --------------------------------------------------------------------------- -USART - Universal Asynchronous Receiver-Transmitter --------------------------------------------------------------------------- -*/ - -/* Universal Synchronous/Asynchronous Receiver/Transmitter */ -typedef struct USART_struct -{ - register8_t DATA; /* Data Register */ - register8_t STATUS; /* Status Register */ - register8_t reserved_0x02; - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t CTRLC; /* Control Register C */ - register8_t BAUDCTRLA; /* Baud Rate Control Register A */ - register8_t BAUDCTRLB; /* Baud Rate Control Register B */ -} USART_t; - -/* Receive Complete Interrupt level */ -typedef enum USART_RXCINTLVL_enum -{ - USART_RXCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ - USART_RXCINTLVL_LO_gc = (0x01<<4), /* Low Level */ - USART_RXCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ - USART_RXCINTLVL_HI_gc = (0x03<<4), /* High Level */ -} USART_RXCINTLVL_t; - -/* Transmit Complete Interrupt level */ -typedef enum USART_TXCINTLVL_enum -{ - USART_TXCINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ - USART_TXCINTLVL_LO_gc = (0x01<<2), /* Low Level */ - USART_TXCINTLVL_MED_gc = (0x02<<2), /* Medium Level */ - USART_TXCINTLVL_HI_gc = (0x03<<2), /* High Level */ -} USART_TXCINTLVL_t; - -/* Data Register Empty Interrupt level */ -typedef enum USART_DREINTLVL_enum -{ - USART_DREINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - USART_DREINTLVL_LO_gc = (0x01<<0), /* Low Level */ - USART_DREINTLVL_MED_gc = (0x02<<0), /* Medium Level */ - USART_DREINTLVL_HI_gc = (0x03<<0), /* High Level */ -} USART_DREINTLVL_t; - -/* Character Size */ -typedef enum USART_CHSIZE_enum -{ - USART_CHSIZE_5BIT_gc = (0x00<<0), /* Character size: 5 bit */ - USART_CHSIZE_6BIT_gc = (0x01<<0), /* Character size: 6 bit */ - USART_CHSIZE_7BIT_gc = (0x02<<0), /* Character size: 7 bit */ - USART_CHSIZE_8BIT_gc = (0x03<<0), /* Character size: 8 bit */ - USART_CHSIZE_9BIT_gc = (0x07<<0), /* Character size: 9 bit */ -} USART_CHSIZE_t; - -/* Communication Mode */ -typedef enum USART_CMODE_enum -{ - USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6), /* Asynchronous Mode */ - USART_CMODE_SYNCHRONOUS_gc = (0x01<<6), /* Synchronous Mode */ - USART_CMODE_IRDA_gc = (0x02<<6), /* IrDA Mode */ - USART_CMODE_MSPI_gc = (0x03<<6), /* Master SPI Mode */ -} USART_CMODE_t; - -/* Parity Mode */ -typedef enum USART_PMODE_enum -{ - USART_PMODE_DISABLED_gc = (0x00<<4), /* No Parity */ - USART_PMODE_EVEN_gc = (0x02<<4), /* Even Parity */ - USART_PMODE_ODD_gc = (0x03<<4), /* Odd Parity */ -} USART_PMODE_t; - - -/* --------------------------------------------------------------------------- -SPI - Serial Peripheral Interface --------------------------------------------------------------------------- -*/ - -/* Serial Peripheral Interface */ -typedef struct SPI_struct -{ - register8_t CTRL; /* Control Register */ - register8_t INTCTRL; /* Interrupt Control Register */ - register8_t STATUS; /* Status Register */ - register8_t DATA; /* Data Register */ -} SPI_t; - -/* SPI Mode */ -typedef enum SPI_MODE_enum -{ - SPI_MODE_0_gc = (0x00<<2), /* SPI Mode 0 */ - SPI_MODE_1_gc = (0x01<<2), /* SPI Mode 1 */ - SPI_MODE_2_gc = (0x02<<2), /* SPI Mode 2 */ - SPI_MODE_3_gc = (0x03<<2), /* SPI Mode 3 */ -} SPI_MODE_t; - -/* Prescaler setting */ -typedef enum SPI_PRESCALER_enum -{ - SPI_PRESCALER_DIV4_gc = (0x00<<0), /* System Clock / 4 */ - SPI_PRESCALER_DIV16_gc = (0x01<<0), /* System Clock / 16 */ - SPI_PRESCALER_DIV64_gc = (0x02<<0), /* System Clock / 64 */ - SPI_PRESCALER_DIV128_gc = (0x03<<0), /* System Clock / 128 */ -} SPI_PRESCALER_t; - -/* Interrupt level */ -typedef enum SPI_INTLVL_enum -{ - SPI_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - SPI_INTLVL_LO_gc = (0x01<<0), /* Low Level */ - SPI_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ - SPI_INTLVL_HI_gc = (0x03<<0), /* High Level */ -} SPI_INTLVL_t; - - -/* --------------------------------------------------------------------------- -IRCOM - IR Communication Module --------------------------------------------------------------------------- -*/ - -/* IR Communication Module */ -typedef struct IRCOM_struct -{ - register8_t CTRL; /* Control Register */ - register8_t TXPLCTRL; /* IrDA Transmitter Pulse Length Control Register */ - register8_t RXPLCTRL; /* IrDA Receiver Pulse Length Control Register */ -} IRCOM_t; - -/* Event channel selection */ -typedef enum IRDA_EVSEL_enum -{ - IRDA_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ - IRDA_EVSEL_0_gc = (0x08<<0), /* Event Channel 0 */ - IRDA_EVSEL_1_gc = (0x09<<0), /* Event Channel 1 */ - IRDA_EVSEL_2_gc = (0x0A<<0), /* Event Channel 2 */ - IRDA_EVSEL_3_gc = (0x0B<<0), /* Event Channel 3 */ - IRDA_EVSEL_4_gc = (0x0C<<0), /* Event Channel 4 */ - IRDA_EVSEL_5_gc = (0x0D<<0), /* Event Channel 5 */ - IRDA_EVSEL_6_gc = (0x0E<<0), /* Event Channel 6 */ - IRDA_EVSEL_7_gc = (0x0F<<0), /* Event Channel 7 */ -} IRDA_EVSEL_t; - - -/* --------------------------------------------------------------------------- -FUSE - Fuses and Lockbits --------------------------------------------------------------------------- -*/ - -/* Fuses */ -typedef struct NVM_FUSES_struct -{ - register8_t reserved_0x00; - register8_t FUSEBYTE1; /* Watchdog Configuration */ - register8_t FUSEBYTE2; /* Reset Configuration */ - register8_t reserved_0x03; - register8_t FUSEBYTE4; /* Start-up Configuration */ - register8_t FUSEBYTE5; /* EESAVE and BOD Level */ -} NVM_FUSES_t; - -/* Boot Loader Section Reset Vector */ -typedef enum BOOTRST_enum -{ - BOOTRST_BOOTLDR_gc = (0x00<<6), /* Boot Loader Reset */ - BOOTRST_APPLICATION_gc = (0x01<<6), /* Application Reset */ -} BOOTRST_t; - -/* Timer Oscillator pin location */ -typedef enum TOSCSEL_enum -{ - TOSCSEL_ALTERNATE_gc = (0x00<<5), /* TOSC1 / TOSC2 on separate pins */ - TOSCSEL_XTAL_gc = (0x01<<5), /* TOSC1 / TOSC2 shared with XTAL1 / XTAL2 */ -} TOSCSEL_t; - -/* BOD operation */ -typedef enum BOD_enum -{ - BOD_SAMPLED_gc = (0x01<<0), /* BOD enabled in sampled mode */ - BOD_CONTINUOUS_gc = (0x02<<0), /* BOD enabled continuously */ - BOD_DISABLED_gc = (0x03<<0), /* BOD Disabled */ -} BOD_t; - -/* BOD operation */ -typedef enum BODACT_enum -{ - BODACT_SAMPLED_gc = (0x01<<4), /* BOD enabled in sampled mode */ - BODACT_CONTINUOUS_gc = (0x02<<4), /* BOD enabled continuously */ - BODACT_DISABLED_gc = (0x03<<4), /* BOD Disabled */ -} BODACT_t; - -/* Watchdog (Window) Timeout Period */ -typedef enum WD_enum -{ - WD_8CLK_gc = (0x00<<4), /* 8 cycles (8ms @ 3.3V) */ - WD_16CLK_gc = (0x01<<4), /* 16 cycles (16ms @ 3.3V) */ - WD_32CLK_gc = (0x02<<4), /* 32 cycles (32ms @ 3.3V) */ - WD_64CLK_gc = (0x03<<4), /* 64 cycles (64ms @ 3.3V) */ - WD_128CLK_gc = (0x04<<4), /* 128 cycles (0.125s @ 3.3V) */ - WD_256CLK_gc = (0x05<<4), /* 256 cycles (0.25s @ 3.3V) */ - WD_512CLK_gc = (0x06<<4), /* 512 cycles (0.5s @ 3.3V) */ - WD_1KCLK_gc = (0x07<<4), /* 1K cycles (1s @ 3.3V) */ - WD_2KCLK_gc = (0x08<<4), /* 2K cycles (2s @ 3.3V) */ - WD_4KCLK_gc = (0x09<<4), /* 4K cycles (4s @ 3.3V) */ - WD_8KCLK_gc = (0x0A<<4), /* 8K cycles (8s @ 3.3V) */ -} WD_t; - -/* Watchdog (Window) Timeout Period */ -typedef enum WDP_enum -{ - WDP_8CLK_gc = (0x00<<0), /* 8 cycles (8ms @ 3.3V) */ - WDP_16CLK_gc = (0x01<<0), /* 16 cycles (16ms @ 3.3V) */ - WDP_32CLK_gc = (0x02<<0), /* 32 cycles (32ms @ 3.3V) */ - WDP_64CLK_gc = (0x03<<0), /* 64 cycles (64ms @ 3.3V) */ - WDP_128CLK_gc = (0x04<<0), /* 128 cycles (0.125s @ 3.3V) */ - WDP_256CLK_gc = (0x05<<0), /* 256 cycles (0.25s @ 3.3V) */ - WDP_512CLK_gc = (0x06<<0), /* 512 cycles (0.5s @ 3.3V) */ - WDP_1KCLK_gc = (0x07<<0), /* 1K cycles (1s @ 3.3V) */ - WDP_2KCLK_gc = (0x08<<0), /* 2K cycles (2s @ 3.3V) */ - WDP_4KCLK_gc = (0x09<<0), /* 4K cycles (4s @ 3.3V) */ - WDP_8KCLK_gc = (0x0A<<0), /* 8K cycles (8s @ 3.3V) */ -} WDP_t; - -/* Start-up Time */ -typedef enum SUT_enum -{ - SUT_0MS_gc = (0x03<<2), /* 0 ms */ - SUT_4MS_gc = (0x01<<2), /* 4 ms */ - SUT_64MS_gc = (0x00<<2), /* 64 ms */ -} SUT_t; - -/* Brownout Detection Voltage Level */ -typedef enum BODLVL_enum -{ - BODLVL_1V6_gc = (0x07<<0), /* 1.6 V */ - BODLVL_1V8_gc = (0x06<<0), /* 1.8 V */ - BODLVL_2V0_gc = (0x05<<0), /* 2.0 V */ - BODLVL_2V2_gc = (0x04<<0), /* 2.2 V */ - BODLVL_2V4_gc = (0x03<<0), /* 2.4 V */ - BODLVL_2V6_gc = (0x02<<0), /* 2.6 V */ - BODLVL_2V8_gc = (0x01<<0), /* 2.8 V */ - BODLVL_3V0_gc = (0x00<<0), /* 3.0 V */ -} BODLVL_t; - - -/* --------------------------------------------------------------------------- -LOCKBIT - Fuses and Lockbits --------------------------------------------------------------------------- -*/ - -/* Lock Bits */ -typedef struct NVM_LOCKBITS_struct -{ - register8_t LOCK_BITS; /* Lock Bits (Changed from LOCKBITS to avoid avr-libc collision) */ -} NVM_LOCKBITS_t; - -/* Boot lock bits - boot setcion */ -typedef enum FUSE_BLBB_enum -{ - FUSE_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ - FUSE_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ - FUSE_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ - FUSE_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ -} FUSE_BLBB_t; - -/* Boot lock bits - application section */ -typedef enum FUSE_BLBA_enum -{ - FUSE_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ - FUSE_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ - FUSE_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ - FUSE_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ -} FUSE_BLBA_t; - -/* Boot lock bits - application table section */ -typedef enum FUSE_BLBAT_enum -{ - FUSE_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ - FUSE_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ - FUSE_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ - FUSE_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ -} FUSE_BLBAT_t; - -/* Lock bits */ -typedef enum FUSE_LB_enum -{ - FUSE_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ - FUSE_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ - FUSE_LB_NOLOCK_gc = (0x03<<0), /* No locks */ -} FUSE_LB_t; - - -/* --------------------------------------------------------------------------- -SIGROW - Signature Row --------------------------------------------------------------------------- -*/ - -/* Production Signatures */ -typedef struct NVM_PROD_SIGNATURES_struct -{ - register8_t RCOSC2M; /* RCOSC 2 MHz Calibration Value B */ - register8_t RCOSC2MA; /* RCOSC 2 MHz Calibration Value A */ - register8_t RCOSC32K; /* RCOSC 32.768 kHz Calibration Value */ - register8_t RCOSC32M; /* RCOSC 32 MHz Calibration Value B */ - register8_t RCOSC32MA; /* RCOSC 32 MHz Calibration Value A */ - register8_t reserved_0x05; - register8_t reserved_0x06; - register8_t reserved_0x07; - register8_t LOTNUM0; /* Lot Number Byte 0, ASCII */ - register8_t LOTNUM1; /* Lot Number Byte 1, ASCII */ - register8_t LOTNUM2; /* Lot Number Byte 2, ASCII */ - register8_t LOTNUM3; /* Lot Number Byte 3, ASCII */ - register8_t LOTNUM4; /* Lot Number Byte 4, ASCII */ - register8_t LOTNUM5; /* Lot Number Byte 5, ASCII */ - register8_t reserved_0x0E; - register8_t reserved_0x0F; - register8_t WAFNUM; /* Wafer Number */ - register8_t reserved_0x11; - register8_t COORDX0; /* Wafer Coordinate X Byte 0 */ - register8_t COORDX1; /* Wafer Coordinate X Byte 1 */ - register8_t COORDY0; /* Wafer Coordinate Y Byte 0 */ - register8_t COORDY1; /* Wafer Coordinate Y Byte 1 */ - register8_t reserved_0x16; - register8_t reserved_0x17; - register8_t reserved_0x18; - register8_t reserved_0x19; - register8_t USBCAL0; /* USB Calibration Byte 0 */ - register8_t USBCAL1; /* USB Calibration Byte 1 */ - register8_t USBRCOSC; /* USB RCOSC Calibration Value B */ - register8_t USBRCOSCA; /* USB RCOSC Calibration Value A */ - register8_t reserved_0x1E; - register8_t reserved_0x1F; - register8_t ADCACAL0; /* ADCA Calibration Byte 0 */ - register8_t ADCACAL1; /* ADCA Calibration Byte 1 */ - register8_t reserved_0x22; - register8_t reserved_0x23; - register8_t ADCBCAL0; /* ADCB Calibration Byte 0 */ - register8_t ADCBCAL1; /* ADCB Calibration Byte 1 */ - register8_t reserved_0x26; - register8_t reserved_0x27; - register8_t reserved_0x28; - register8_t reserved_0x29; - register8_t reserved_0x2A; - register8_t reserved_0x2B; - register8_t reserved_0x2C; - register8_t reserved_0x2D; - register8_t TEMPSENSE0; /* Temperature Sensor Calibration Byte 0 */ - register8_t TEMPSENSE1; /* Temperature Sensor Calibration Byte 1 */ - register8_t DACA0OFFCAL; /* DACA0 Calibration Byte 0 */ - register8_t DACA0GAINCAL; /* DACA0 Calibration Byte 1 */ - register8_t DACB0OFFCAL; /* DACB0 Calibration Byte 0 */ - register8_t DACB0GAINCAL; /* DACB0 Calibration Byte 1 */ - register8_t DACA1OFFCAL; /* DACA1 Calibration Byte 0 */ - register8_t DACA1GAINCAL; /* DACA1 Calibration Byte 1 */ - register8_t DACB1OFFCAL; /* DACB1 Calibration Byte 0 */ - register8_t DACB1GAINCAL; /* DACB1 Calibration Byte 1 */ - register8_t reserved_0x38; - register8_t reserved_0x39; - register8_t reserved_0x3A; - register8_t reserved_0x3B; - register8_t reserved_0x3C; - register8_t reserved_0x3D; - register8_t reserved_0x3E; - register8_t reserved_0x3F; - register8_t reserved_0x40; - register8_t reserved_0x41; - register8_t reserved_0x42; - register8_t reserved_0x43; - register8_t reserved_0x44; - register8_t reserved_0x45; - register8_t reserved_0x46; - register8_t reserved_0x47; -} NVM_PROD_SIGNATURES_t; - -/* -========================================================================== -IO Module Instances. Mapped to memory. -========================================================================== -*/ - -#define VPORT0 (*(VPORT_t *) 0x0010) /* Virtual Port */ -#define VPORT1 (*(VPORT_t *) 0x0014) /* Virtual Port */ -#define VPORT2 (*(VPORT_t *) 0x0018) /* Virtual Port */ -#define VPORT3 (*(VPORT_t *) 0x001C) /* Virtual Port */ -#define OCD (*(OCD_t *) 0x002E) /* On-Chip Debug System */ -#define CLK (*(CLK_t *) 0x0040) /* Clock System */ -#define SLEEP (*(SLEEP_t *) 0x0048) /* Sleep Controller */ -#define OSC (*(OSC_t *) 0x0050) /* Oscillator */ -#define DFLLRC32M (*(DFLL_t *) 0x0060) /* DFLL */ -#define DFLLRC2M (*(DFLL_t *) 0x0068) /* DFLL */ -#define PR (*(PR_t *) 0x0070) /* Power Reduction */ -#define RST (*(RST_t *) 0x0078) /* Reset */ -#define WDT (*(WDT_t *) 0x0080) /* Watch-Dog Timer */ -#define MCU (*(MCU_t *) 0x0090) /* MCU Control */ -#define PMIC (*(PMIC_t *) 0x00A0) /* Programmable Multi-level Interrupt Controller */ -#define PORTCFG (*(PORTCFG_t *) 0x00B0) /* I/O port Configuration */ -#define AES (*(AES_t *) 0x00C0) /* AES Module */ -#define CRC (*(CRC_t *) 0x00D0) /* Cyclic Redundancy Checker */ -#define DMA (*(DMA_t *) 0x0100) /* DMA Controller */ -#define EVSYS (*(EVSYS_t *) 0x0180) /* Event System */ -#define NVM (*(NVM_t *) 0x01C0) /* Non-volatile Memory Controller */ -#define ADCA (*(ADC_t *) 0x0200) /* Analog-to-Digital Converter */ -#define DACB (*(DAC_t *) 0x0320) /* Digital-to-Analog Converter */ -#define ACA (*(AC_t *) 0x0380) /* Analog Comparator */ -#define RTC (*(RTC_t *) 0x0400) /* Real-Time Counter */ -#define TWIC (*(TWI_t *) 0x0480) /* Two-Wire Interface */ -#define TWIE (*(TWI_t *) 0x04A0) /* Two-Wire Interface */ -#define USB (*(USB_t *) 0x04C0) /* Universal Serial Bus */ -#define PORTA (*(PORT_t *) 0x0600) /* I/O Ports */ -#define PORTB (*(PORT_t *) 0x0620) /* I/O Ports */ -#define PORTC (*(PORT_t *) 0x0640) /* I/O Ports */ -#define PORTD (*(PORT_t *) 0x0660) /* I/O Ports */ -#define PORTE (*(PORT_t *) 0x0680) /* I/O Ports */ -#define PORTR (*(PORT_t *) 0x07E0) /* I/O Ports */ -#define TCC0 (*(TC0_t *) 0x0800) /* 16-bit Timer/Counter 0 */ -#define TCC2 (*(TC2_t *) 0x0800) /* 16-bit Timer/Counter type 2 */ -#define TCC1 (*(TC1_t *) 0x0840) /* 16-bit Timer/Counter 1 */ -#define AWEXC (*(AWEX_t *) 0x0880) /* Advanced Waveform Extension */ -#define HIRESC (*(HIRES_t *) 0x0890) /* High-Resolution Extension */ -#define USARTC0 (*(USART_t *) 0x08A0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ -#define USARTC1 (*(USART_t *) 0x08B0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ -#define SPIC (*(SPI_t *) 0x08C0) /* Serial Peripheral Interface */ -#define IRCOM (*(IRCOM_t *) 0x08F8) /* IR Communication Module */ -#define TCD0 (*(TC0_t *) 0x0900) /* 16-bit Timer/Counter 0 */ -#define TCD2 (*(TC2_t *) 0x0900) /* 16-bit Timer/Counter type 2 */ -#define TCD1 (*(TC1_t *) 0x0940) /* 16-bit Timer/Counter 1 */ -#define HIRESD (*(HIRES_t *) 0x0990) /* High-Resolution Extension */ -#define USARTD0 (*(USART_t *) 0x09A0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ -#define USARTD1 (*(USART_t *) 0x09B0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ -#define SPID (*(SPI_t *) 0x09C0) /* Serial Peripheral Interface */ -#define TCE0 (*(TC0_t *) 0x0A00) /* 16-bit Timer/Counter 0 */ -#define HIRESE (*(HIRES_t *) 0x0A90) /* High-Resolution Extension */ -#define USARTE0 (*(USART_t *) 0x0AA0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ - - -#endif /* !defined (__ASSEMBLER__) */ - - -/* ========== Flattened fully qualified IO register names ========== */ - -/* GPIO - General Purpose IO Registers */ -#define GPIO_GPIOR0 _SFR_MEM8(0x0000) -#define GPIO_GPIOR1 _SFR_MEM8(0x0001) -#define GPIO_GPIOR2 _SFR_MEM8(0x0002) -#define GPIO_GPIOR3 _SFR_MEM8(0x0003) -#define GPIO_GPIOR4 _SFR_MEM8(0x0004) -#define GPIO_GPIOR5 _SFR_MEM8(0x0005) -#define GPIO_GPIOR6 _SFR_MEM8(0x0006) -#define GPIO_GPIOR7 _SFR_MEM8(0x0007) -#define GPIO_GPIOR8 _SFR_MEM8(0x0008) -#define GPIO_GPIOR9 _SFR_MEM8(0x0009) -#define GPIO_GPIORA _SFR_MEM8(0x000A) -#define GPIO_GPIORB _SFR_MEM8(0x000B) -#define GPIO_GPIORC _SFR_MEM8(0x000C) -#define GPIO_GPIORD _SFR_MEM8(0x000D) -#define GPIO_GPIORE _SFR_MEM8(0x000E) -#define GPIO_GPIORF _SFR_MEM8(0x000F) - -/* Deprecated */ -#define GPIO_GPIO0 _SFR_MEM8(0x0000) -#define GPIO_GPIO1 _SFR_MEM8(0x0001) -#define GPIO_GPIO2 _SFR_MEM8(0x0002) -#define GPIO_GPIO3 _SFR_MEM8(0x0003) -#define GPIO_GPIO4 _SFR_MEM8(0x0004) -#define GPIO_GPIO5 _SFR_MEM8(0x0005) -#define GPIO_GPIO6 _SFR_MEM8(0x0006) -#define GPIO_GPIO7 _SFR_MEM8(0x0007) -#define GPIO_GPIO8 _SFR_MEM8(0x0008) -#define GPIO_GPIO9 _SFR_MEM8(0x0009) -#define GPIO_GPIOA _SFR_MEM8(0x000A) -#define GPIO_GPIOB _SFR_MEM8(0x000B) -#define GPIO_GPIOC _SFR_MEM8(0x000C) -#define GPIO_GPIOD _SFR_MEM8(0x000D) -#define GPIO_GPIOE _SFR_MEM8(0x000E) -#define GPIO_GPIOF _SFR_MEM8(0x000F) - -/* NVM_FUSES - Fuses */ -#define FUSE_FUSEBYTE1 _SFR_MEM8(0x0001) -#define FUSE_FUSEBYTE2 _SFR_MEM8(0x0002) -#define FUSE_FUSEBYTE4 _SFR_MEM8(0x0004) -#define FUSE_FUSEBYTE5 _SFR_MEM8(0x0005) - -/* NVM_LOCKBITS - Lock Bits */ -#define LOCKBIT_LOCKBITS _SFR_MEM8(0x0000) - -/* NVM_PROD_SIGNATURES - Production Signatures */ -#define PRODSIGNATURES_RCOSC2M _SFR_MEM8(0x0000) -#define PRODSIGNATURES_RCOSC2MA _SFR_MEM8(0x0001) -#define PRODSIGNATURES_RCOSC32K _SFR_MEM8(0x0002) -#define PRODSIGNATURES_RCOSC32M _SFR_MEM8(0x0003) -#define PRODSIGNATURES_RCOSC32MA _SFR_MEM8(0x0004) -#define PRODSIGNATURES_LOTNUM0 _SFR_MEM8(0x0008) -#define PRODSIGNATURES_LOTNUM1 _SFR_MEM8(0x0009) -#define PRODSIGNATURES_LOTNUM2 _SFR_MEM8(0x000A) -#define PRODSIGNATURES_LOTNUM3 _SFR_MEM8(0x000B) -#define PRODSIGNATURES_LOTNUM4 _SFR_MEM8(0x000C) -#define PRODSIGNATURES_LOTNUM5 _SFR_MEM8(0x000D) -#define PRODSIGNATURES_WAFNUM _SFR_MEM8(0x0010) -#define PRODSIGNATURES_COORDX0 _SFR_MEM8(0x0012) -#define PRODSIGNATURES_COORDX1 _SFR_MEM8(0x0013) -#define PRODSIGNATURES_COORDY0 _SFR_MEM8(0x0014) -#define PRODSIGNATURES_COORDY1 _SFR_MEM8(0x0015) -#define PRODSIGNATURES_USBCAL0 _SFR_MEM8(0x001A) -#define PRODSIGNATURES_USBCAL1 _SFR_MEM8(0x001B) -#define PRODSIGNATURES_USBRCOSC _SFR_MEM8(0x001C) -#define PRODSIGNATURES_USBRCOSCA _SFR_MEM8(0x001D) -#define PRODSIGNATURES_ADCACAL0 _SFR_MEM8(0x0020) -#define PRODSIGNATURES_ADCACAL1 _SFR_MEM8(0x0021) -#define PRODSIGNATURES_ADCBCAL0 _SFR_MEM8(0x0024) -#define PRODSIGNATURES_ADCBCAL1 _SFR_MEM8(0x0025) -#define PRODSIGNATURES_TEMPSENSE0 _SFR_MEM8(0x002E) -#define PRODSIGNATURES_TEMPSENSE1 _SFR_MEM8(0x002F) -#define PRODSIGNATURES_DACA0OFFCAL _SFR_MEM8(0x0030) -#define PRODSIGNATURES_DACA0GAINCAL _SFR_MEM8(0x0031) -#define PRODSIGNATURES_DACB0OFFCAL _SFR_MEM8(0x0032) -#define PRODSIGNATURES_DACB0GAINCAL _SFR_MEM8(0x0033) -#define PRODSIGNATURES_DACA1OFFCAL _SFR_MEM8(0x0034) -#define PRODSIGNATURES_DACA1GAINCAL _SFR_MEM8(0x0035) -#define PRODSIGNATURES_DACB1OFFCAL _SFR_MEM8(0x0036) -#define PRODSIGNATURES_DACB1GAINCAL _SFR_MEM8(0x0037) - -/* VPORT - Virtual Port */ -#define VPORT0_DIR _SFR_MEM8(0x0010) -#define VPORT0_OUT _SFR_MEM8(0x0011) -#define VPORT0_IN _SFR_MEM8(0x0012) -#define VPORT0_INTFLAGS _SFR_MEM8(0x0013) - -/* VPORT - Virtual Port */ -#define VPORT1_DIR _SFR_MEM8(0x0014) -#define VPORT1_OUT _SFR_MEM8(0x0015) -#define VPORT1_IN _SFR_MEM8(0x0016) -#define VPORT1_INTFLAGS _SFR_MEM8(0x0017) - -/* VPORT - Virtual Port */ -#define VPORT2_DIR _SFR_MEM8(0x0018) -#define VPORT2_OUT _SFR_MEM8(0x0019) -#define VPORT2_IN _SFR_MEM8(0x001A) -#define VPORT2_INTFLAGS _SFR_MEM8(0x001B) - -/* VPORT - Virtual Port */ -#define VPORT3_DIR _SFR_MEM8(0x001C) -#define VPORT3_OUT _SFR_MEM8(0x001D) -#define VPORT3_IN _SFR_MEM8(0x001E) -#define VPORT3_INTFLAGS _SFR_MEM8(0x001F) - -/* OCD - On-Chip Debug System */ -#define OCD_OCDR0 _SFR_MEM8(0x002E) -#define OCD_OCDR1 _SFR_MEM8(0x002F) - -/* CPU - CPU registers */ -#define CPU_CCP _SFR_MEM8(0x0034) -#define CPU_RAMPD _SFR_MEM8(0x0038) -#define CPU_RAMPX _SFR_MEM8(0x0039) -#define CPU_RAMPY _SFR_MEM8(0x003A) -#define CPU_RAMPZ _SFR_MEM8(0x003B) -#define CPU_EIND _SFR_MEM8(0x003C) -#define CPU_SPL _SFR_MEM8(0x003D) -#define CPU_SPH _SFR_MEM8(0x003E) -#define CPU_SREG _SFR_MEM8(0x003F) - -/* CLK - Clock System */ -#define CLK_CTRL _SFR_MEM8(0x0040) -#define CLK_PSCTRL _SFR_MEM8(0x0041) -#define CLK_LOCK _SFR_MEM8(0x0042) -#define CLK_RTCCTRL _SFR_MEM8(0x0043) -#define CLK_USBCTRL _SFR_MEM8(0x0044) - -/* SLEEP - Sleep Controller */ -#define SLEEP_CTRL _SFR_MEM8(0x0048) - -/* OSC - Oscillator */ -#define OSC_CTRL _SFR_MEM8(0x0050) -#define OSC_STATUS _SFR_MEM8(0x0051) -#define OSC_XOSCCTRL _SFR_MEM8(0x0052) -#define OSC_XOSCFAIL _SFR_MEM8(0x0053) -#define OSC_RC32KCAL _SFR_MEM8(0x0054) -#define OSC_PLLCTRL _SFR_MEM8(0x0055) -#define OSC_DFLLCTRL _SFR_MEM8(0x0056) - -/* DFLL - DFLL */ -#define DFLLRC32M_CTRL _SFR_MEM8(0x0060) -#define DFLLRC32M_CALA _SFR_MEM8(0x0062) -#define DFLLRC32M_CALB _SFR_MEM8(0x0063) -#define DFLLRC32M_COMP0 _SFR_MEM8(0x0064) -#define DFLLRC32M_COMP1 _SFR_MEM8(0x0065) -#define DFLLRC32M_COMP2 _SFR_MEM8(0x0066) - -/* DFLL - DFLL */ -#define DFLLRC2M_CTRL _SFR_MEM8(0x0068) -#define DFLLRC2M_CALA _SFR_MEM8(0x006A) -#define DFLLRC2M_CALB _SFR_MEM8(0x006B) -#define DFLLRC2M_COMP0 _SFR_MEM8(0x006C) -#define DFLLRC2M_COMP1 _SFR_MEM8(0x006D) -#define DFLLRC2M_COMP2 _SFR_MEM8(0x006E) - -/* PR - Power Reduction */ -#define PR_PRGEN _SFR_MEM8(0x0070) -#define PR_PRPA _SFR_MEM8(0x0071) -#define PR_PRPB _SFR_MEM8(0x0072) -#define PR_PRPC _SFR_MEM8(0x0073) -#define PR_PRPD _SFR_MEM8(0x0074) -#define PR_PRPE _SFR_MEM8(0x0075) -#define PR_PRPF _SFR_MEM8(0x0076) - -/* RST - Reset */ -#define RST_STATUS _SFR_MEM8(0x0078) -#define RST_CTRL _SFR_MEM8(0x0079) - -/* WDT - Watch-Dog Timer */ -#define WDT_CTRL _SFR_MEM8(0x0080) -#define WDT_WINCTRL _SFR_MEM8(0x0081) -#define WDT_STATUS _SFR_MEM8(0x0082) - -/* MCU - MCU Control */ -#define MCU_DEVID0 _SFR_MEM8(0x0090) -#define MCU_DEVID1 _SFR_MEM8(0x0091) -#define MCU_DEVID2 _SFR_MEM8(0x0092) -#define MCU_REVID _SFR_MEM8(0x0093) -#define MCU_JTAGUID _SFR_MEM8(0x0094) -#define MCU_MCUCR _SFR_MEM8(0x0096) -#define MCU_ANAINIT _SFR_MEM8(0x0097) -#define MCU_EVSYSLOCK _SFR_MEM8(0x0098) -#define MCU_AWEXLOCK _SFR_MEM8(0x0099) - -/* PMIC - Programmable Multi-level Interrupt Controller */ -#define PMIC_STATUS _SFR_MEM8(0x00A0) -#define PMIC_INTPRI _SFR_MEM8(0x00A1) -#define PMIC_CTRL _SFR_MEM8(0x00A2) - -/* PORTCFG - I/O port Configuration */ -#define PORTCFG_MPCMASK _SFR_MEM8(0x00B0) -#define PORTCFG_VPCTRLA _SFR_MEM8(0x00B2) -#define PORTCFG_VPCTRLB _SFR_MEM8(0x00B3) -#define PORTCFG_CLKEVOUT _SFR_MEM8(0x00B4) -#define PORTCFG_EBIOUT _SFR_MEM8(0x00B5) -#define PORTCFG_EVOUTSEL _SFR_MEM8(0x00B6) - -/* AES - AES Module */ -#define AES_CTRL _SFR_MEM8(0x00C0) -#define AES_STATUS _SFR_MEM8(0x00C1) -#define AES_STATE _SFR_MEM8(0x00C2) -#define AES_KEY _SFR_MEM8(0x00C3) -#define AES_INTCTRL _SFR_MEM8(0x00C4) - -/* CRC - Cyclic Redundancy Checker */ -#define CRC_CTRL _SFR_MEM8(0x00D0) -#define CRC_STATUS _SFR_MEM8(0x00D1) -#define CRC_DATAIN _SFR_MEM8(0x00D3) -#define CRC_CHECKSUM0 _SFR_MEM8(0x00D4) -#define CRC_CHECKSUM1 _SFR_MEM8(0x00D5) -#define CRC_CHECKSUM2 _SFR_MEM8(0x00D6) -#define CRC_CHECKSUM3 _SFR_MEM8(0x00D7) - -/* DMA - DMA Controller */ -#define DMA_CTRL _SFR_MEM8(0x0100) -#define DMA_INTFLAGS _SFR_MEM8(0x0103) -#define DMA_STATUS _SFR_MEM8(0x0104) -#define DMA_TEMP _SFR_MEM16(0x0106) -#define DMA_CH0_CTRLA _SFR_MEM8(0x0110) -#define DMA_CH0_CTRLB _SFR_MEM8(0x0111) -#define DMA_CH0_ADDRCTRL _SFR_MEM8(0x0112) -#define DMA_CH0_TRIGSRC _SFR_MEM8(0x0113) -#define DMA_CH0_TRFCNT _SFR_MEM16(0x0114) -#define DMA_CH0_REPCNT _SFR_MEM8(0x0116) -#define DMA_CH0_SRCADDR0 _SFR_MEM8(0x0118) -#define DMA_CH0_SRCADDR1 _SFR_MEM8(0x0119) -#define DMA_CH0_SRCADDR2 _SFR_MEM8(0x011A) -#define DMA_CH0_DESTADDR0 _SFR_MEM8(0x011C) -#define DMA_CH0_DESTADDR1 _SFR_MEM8(0x011D) -#define DMA_CH0_DESTADDR2 _SFR_MEM8(0x011E) -#define DMA_CH1_CTRLA _SFR_MEM8(0x0120) -#define DMA_CH1_CTRLB _SFR_MEM8(0x0121) -#define DMA_CH1_ADDRCTRL _SFR_MEM8(0x0122) -#define DMA_CH1_TRIGSRC _SFR_MEM8(0x0123) -#define DMA_CH1_TRFCNT _SFR_MEM16(0x0124) -#define DMA_CH1_REPCNT _SFR_MEM8(0x0126) -#define DMA_CH1_SRCADDR0 _SFR_MEM8(0x0128) -#define DMA_CH1_SRCADDR1 _SFR_MEM8(0x0129) -#define DMA_CH1_SRCADDR2 _SFR_MEM8(0x012A) -#define DMA_CH1_DESTADDR0 _SFR_MEM8(0x012C) -#define DMA_CH1_DESTADDR1 _SFR_MEM8(0x012D) -#define DMA_CH1_DESTADDR2 _SFR_MEM8(0x012E) -#define DMA_CH2_CTRLA _SFR_MEM8(0x0130) -#define DMA_CH2_CTRLB _SFR_MEM8(0x0131) -#define DMA_CH2_ADDRCTRL _SFR_MEM8(0x0132) -#define DMA_CH2_TRIGSRC _SFR_MEM8(0x0133) -#define DMA_CH2_TRFCNT _SFR_MEM16(0x0134) -#define DMA_CH2_REPCNT _SFR_MEM8(0x0136) -#define DMA_CH2_SRCADDR0 _SFR_MEM8(0x0138) -#define DMA_CH2_SRCADDR1 _SFR_MEM8(0x0139) -#define DMA_CH2_SRCADDR2 _SFR_MEM8(0x013A) -#define DMA_CH2_DESTADDR0 _SFR_MEM8(0x013C) -#define DMA_CH2_DESTADDR1 _SFR_MEM8(0x013D) -#define DMA_CH2_DESTADDR2 _SFR_MEM8(0x013E) -#define DMA_CH3_CTRLA _SFR_MEM8(0x0140) -#define DMA_CH3_CTRLB _SFR_MEM8(0x0141) -#define DMA_CH3_ADDRCTRL _SFR_MEM8(0x0142) -#define DMA_CH3_TRIGSRC _SFR_MEM8(0x0143) -#define DMA_CH3_TRFCNT _SFR_MEM16(0x0144) -#define DMA_CH3_REPCNT _SFR_MEM8(0x0146) -#define DMA_CH3_SRCADDR0 _SFR_MEM8(0x0148) -#define DMA_CH3_SRCADDR1 _SFR_MEM8(0x0149) -#define DMA_CH3_SRCADDR2 _SFR_MEM8(0x014A) -#define DMA_CH3_DESTADDR0 _SFR_MEM8(0x014C) -#define DMA_CH3_DESTADDR1 _SFR_MEM8(0x014D) -#define DMA_CH3_DESTADDR2 _SFR_MEM8(0x014E) - -/* EVSYS - Event System */ -#define EVSYS_CH0MUX _SFR_MEM8(0x0180) -#define EVSYS_CH1MUX _SFR_MEM8(0x0181) -#define EVSYS_CH2MUX _SFR_MEM8(0x0182) -#define EVSYS_CH3MUX _SFR_MEM8(0x0183) -#define EVSYS_CH4MUX _SFR_MEM8(0x0184) -#define EVSYS_CH5MUX _SFR_MEM8(0x0185) -#define EVSYS_CH6MUX _SFR_MEM8(0x0186) -#define EVSYS_CH7MUX _SFR_MEM8(0x0187) -#define EVSYS_CH0CTRL _SFR_MEM8(0x0188) -#define EVSYS_CH1CTRL _SFR_MEM8(0x0189) -#define EVSYS_CH2CTRL _SFR_MEM8(0x018A) -#define EVSYS_CH3CTRL _SFR_MEM8(0x018B) -#define EVSYS_CH4CTRL _SFR_MEM8(0x018C) -#define EVSYS_CH5CTRL _SFR_MEM8(0x018D) -#define EVSYS_CH6CTRL _SFR_MEM8(0x018E) -#define EVSYS_CH7CTRL _SFR_MEM8(0x018F) -#define EVSYS_STROBE _SFR_MEM8(0x0190) -#define EVSYS_DATA _SFR_MEM8(0x0191) - -/* NVM - Non-volatile Memory Controller */ -#define NVM_ADDR0 _SFR_MEM8(0x01C0) -#define NVM_ADDR1 _SFR_MEM8(0x01C1) -#define NVM_ADDR2 _SFR_MEM8(0x01C2) -#define NVM_DATA0 _SFR_MEM8(0x01C4) -#define NVM_DATA1 _SFR_MEM8(0x01C5) -#define NVM_DATA2 _SFR_MEM8(0x01C6) -#define NVM_CMD _SFR_MEM8(0x01CA) -#define NVM_CTRLA _SFR_MEM8(0x01CB) -#define NVM_CTRLB _SFR_MEM8(0x01CC) -#define NVM_INTCTRL _SFR_MEM8(0x01CD) -#define NVM_STATUS _SFR_MEM8(0x01CF) -#define NVM_LOCKBITS _SFR_MEM8(0x01D0) - -/* ADC - Analog-to-Digital Converter */ -#define ADCA_CTRLA _SFR_MEM8(0x0200) -#define ADCA_CTRLB _SFR_MEM8(0x0201) -#define ADCA_REFCTRL _SFR_MEM8(0x0202) -#define ADCA_EVCTRL _SFR_MEM8(0x0203) -#define ADCA_PRESCALER _SFR_MEM8(0x0204) -#define ADCA_INTFLAGS _SFR_MEM8(0x0206) -#define ADCA_TEMP _SFR_MEM8(0x0207) -#define ADCA_CAL _SFR_MEM16(0x020C) -#define ADCA_CH0RES _SFR_MEM16(0x0210) -#define ADCA_CH1RES _SFR_MEM16(0x0212) -#define ADCA_CH2RES _SFR_MEM16(0x0214) -#define ADCA_CH3RES _SFR_MEM16(0x0216) -#define ADCA_CMP _SFR_MEM16(0x0218) -#define ADCA_CH0_CTRL _SFR_MEM8(0x0220) -#define ADCA_CH0_MUXCTRL _SFR_MEM8(0x0221) -#define ADCA_CH0_INTCTRL _SFR_MEM8(0x0222) -#define ADCA_CH0_INTFLAGS _SFR_MEM8(0x0223) -#define ADCA_CH0_RES _SFR_MEM16(0x0224) -#define ADCA_CH0_SCAN _SFR_MEM8(0x0226) -#define ADCA_CH1_CTRL _SFR_MEM8(0x0228) -#define ADCA_CH1_MUXCTRL _SFR_MEM8(0x0229) -#define ADCA_CH1_INTCTRL _SFR_MEM8(0x022A) -#define ADCA_CH1_INTFLAGS _SFR_MEM8(0x022B) -#define ADCA_CH1_RES _SFR_MEM16(0x022C) -#define ADCA_CH1_SCAN _SFR_MEM8(0x022E) -#define ADCA_CH2_CTRL _SFR_MEM8(0x0230) -#define ADCA_CH2_MUXCTRL _SFR_MEM8(0x0231) -#define ADCA_CH2_INTCTRL _SFR_MEM8(0x0232) -#define ADCA_CH2_INTFLAGS _SFR_MEM8(0x0233) -#define ADCA_CH2_RES _SFR_MEM16(0x0234) -#define ADCA_CH2_SCAN _SFR_MEM8(0x0236) -#define ADCA_CH3_CTRL _SFR_MEM8(0x0238) -#define ADCA_CH3_MUXCTRL _SFR_MEM8(0x0239) -#define ADCA_CH3_INTCTRL _SFR_MEM8(0x023A) -#define ADCA_CH3_INTFLAGS _SFR_MEM8(0x023B) -#define ADCA_CH3_RES _SFR_MEM16(0x023C) -#define ADCA_CH3_SCAN _SFR_MEM8(0x023E) - -/* DAC - Digital-to-Analog Converter */ -#define DACB_CTRLA _SFR_MEM8(0x0320) -#define DACB_CTRLB _SFR_MEM8(0x0321) -#define DACB_CTRLC _SFR_MEM8(0x0322) -#define DACB_EVCTRL _SFR_MEM8(0x0323) -#define DACB_STATUS _SFR_MEM8(0x0325) -#define DACB_CH0GAINCAL _SFR_MEM8(0x0328) -#define DACB_CH0OFFSETCAL _SFR_MEM8(0x0329) -#define DACB_CH1GAINCAL _SFR_MEM8(0x032A) -#define DACB_CH1OFFSETCAL _SFR_MEM8(0x032B) -#define DACB_CH0DATA _SFR_MEM16(0x0338) -#define DACB_CH1DATA _SFR_MEM16(0x033A) - -/* AC - Analog Comparator */ -#define ACA_AC0CTRL _SFR_MEM8(0x0380) -#define ACA_AC1CTRL _SFR_MEM8(0x0381) -#define ACA_AC0MUXCTRL _SFR_MEM8(0x0382) -#define ACA_AC1MUXCTRL _SFR_MEM8(0x0383) -#define ACA_CTRLA _SFR_MEM8(0x0384) -#define ACA_CTRLB _SFR_MEM8(0x0385) -#define ACA_WINCTRL _SFR_MEM8(0x0386) -#define ACA_STATUS _SFR_MEM8(0x0387) - -/* RTC - Real-Time Counter */ -#define RTC_CTRL _SFR_MEM8(0x0400) -#define RTC_STATUS _SFR_MEM8(0x0401) -#define RTC_INTCTRL _SFR_MEM8(0x0402) -#define RTC_INTFLAGS _SFR_MEM8(0x0403) -#define RTC_TEMP _SFR_MEM8(0x0404) -#define RTC_CNT _SFR_MEM16(0x0408) -#define RTC_PER _SFR_MEM16(0x040A) -#define RTC_COMP _SFR_MEM16(0x040C) - -/* TWI - Two-Wire Interface */ -#define TWIC_CTRL _SFR_MEM8(0x0480) -#define TWIC_MASTER_CTRLA _SFR_MEM8(0x0481) -#define TWIC_MASTER_CTRLB _SFR_MEM8(0x0482) -#define TWIC_MASTER_CTRLC _SFR_MEM8(0x0483) -#define TWIC_MASTER_STATUS _SFR_MEM8(0x0484) -#define TWIC_MASTER_BAUD _SFR_MEM8(0x0485) -#define TWIC_MASTER_ADDR _SFR_MEM8(0x0486) -#define TWIC_MASTER_DATA _SFR_MEM8(0x0487) -#define TWIC_SLAVE_CTRLA _SFR_MEM8(0x0488) -#define TWIC_SLAVE_CTRLB _SFR_MEM8(0x0489) -#define TWIC_SLAVE_STATUS _SFR_MEM8(0x048A) -#define TWIC_SLAVE_ADDR _SFR_MEM8(0x048B) -#define TWIC_SLAVE_DATA _SFR_MEM8(0x048C) -#define TWIC_SLAVE_ADDRMASK _SFR_MEM8(0x048D) - -/* TWI - Two-Wire Interface */ -#define TWIE_CTRL _SFR_MEM8(0x04A0) -#define TWIE_MASTER_CTRLA _SFR_MEM8(0x04A1) -#define TWIE_MASTER_CTRLB _SFR_MEM8(0x04A2) -#define TWIE_MASTER_CTRLC _SFR_MEM8(0x04A3) -#define TWIE_MASTER_STATUS _SFR_MEM8(0x04A4) -#define TWIE_MASTER_BAUD _SFR_MEM8(0x04A5) -#define TWIE_MASTER_ADDR _SFR_MEM8(0x04A6) -#define TWIE_MASTER_DATA _SFR_MEM8(0x04A7) -#define TWIE_SLAVE_CTRLA _SFR_MEM8(0x04A8) -#define TWIE_SLAVE_CTRLB _SFR_MEM8(0x04A9) -#define TWIE_SLAVE_STATUS _SFR_MEM8(0x04AA) -#define TWIE_SLAVE_ADDR _SFR_MEM8(0x04AB) -#define TWIE_SLAVE_DATA _SFR_MEM8(0x04AC) -#define TWIE_SLAVE_ADDRMASK _SFR_MEM8(0x04AD) - -/* USB - Universal Serial Bus */ -#define USB_CTRLA _SFR_MEM8(0x04C0) -#define USB_CTRLB _SFR_MEM8(0x04C1) -#define USB_STATUS _SFR_MEM8(0x04C2) -#define USB_ADDR _SFR_MEM8(0x04C3) -#define USB_FIFOWP _SFR_MEM8(0x04C4) -#define USB_FIFORP _SFR_MEM8(0x04C5) -#define USB_EPPTR _SFR_MEM16(0x04C6) -#define USB_INTCTRLA _SFR_MEM8(0x04C8) -#define USB_INTCTRLB _SFR_MEM8(0x04C9) -#define USB_INTFLAGSACLR _SFR_MEM8(0x04CA) -#define USB_INTFLAGSASET _SFR_MEM8(0x04CB) -#define USB_INTFLAGSBCLR _SFR_MEM8(0x04CC) -#define USB_INTFLAGSBSET _SFR_MEM8(0x04CD) -#define USB_CAL0 _SFR_MEM8(0x04FA) -#define USB_CAL1 _SFR_MEM8(0x04FB) - -/* PORT - I/O Ports */ -#define PORTA_DIR _SFR_MEM8(0x0600) -#define PORTA_DIRSET _SFR_MEM8(0x0601) -#define PORTA_DIRCLR _SFR_MEM8(0x0602) -#define PORTA_DIRTGL _SFR_MEM8(0x0603) -#define PORTA_OUT _SFR_MEM8(0x0604) -#define PORTA_OUTSET _SFR_MEM8(0x0605) -#define PORTA_OUTCLR _SFR_MEM8(0x0606) -#define PORTA_OUTTGL _SFR_MEM8(0x0607) -#define PORTA_IN _SFR_MEM8(0x0608) -#define PORTA_INTCTRL _SFR_MEM8(0x0609) -#define PORTA_INT0MASK _SFR_MEM8(0x060A) -#define PORTA_INT1MASK _SFR_MEM8(0x060B) -#define PORTA_INTFLAGS _SFR_MEM8(0x060C) -#define PORTA_REMAP _SFR_MEM8(0x060E) -#define PORTA_PIN0CTRL _SFR_MEM8(0x0610) -#define PORTA_PIN1CTRL _SFR_MEM8(0x0611) -#define PORTA_PIN2CTRL _SFR_MEM8(0x0612) -#define PORTA_PIN3CTRL _SFR_MEM8(0x0613) -#define PORTA_PIN4CTRL _SFR_MEM8(0x0614) -#define PORTA_PIN5CTRL _SFR_MEM8(0x0615) -#define PORTA_PIN6CTRL _SFR_MEM8(0x0616) -#define PORTA_PIN7CTRL _SFR_MEM8(0x0617) - -/* PORT - I/O Ports */ -#define PORTB_DIR _SFR_MEM8(0x0620) -#define PORTB_DIRSET _SFR_MEM8(0x0621) -#define PORTB_DIRCLR _SFR_MEM8(0x0622) -#define PORTB_DIRTGL _SFR_MEM8(0x0623) -#define PORTB_OUT _SFR_MEM8(0x0624) -#define PORTB_OUTSET _SFR_MEM8(0x0625) -#define PORTB_OUTCLR _SFR_MEM8(0x0626) -#define PORTB_OUTTGL _SFR_MEM8(0x0627) -#define PORTB_IN _SFR_MEM8(0x0628) -#define PORTB_INTCTRL _SFR_MEM8(0x0629) -#define PORTB_INT0MASK _SFR_MEM8(0x062A) -#define PORTB_INT1MASK _SFR_MEM8(0x062B) -#define PORTB_INTFLAGS _SFR_MEM8(0x062C) -#define PORTB_REMAP _SFR_MEM8(0x062E) -#define PORTB_PIN0CTRL _SFR_MEM8(0x0630) -#define PORTB_PIN1CTRL _SFR_MEM8(0x0631) -#define PORTB_PIN2CTRL _SFR_MEM8(0x0632) -#define PORTB_PIN3CTRL _SFR_MEM8(0x0633) -#define PORTB_PIN4CTRL _SFR_MEM8(0x0634) -#define PORTB_PIN5CTRL _SFR_MEM8(0x0635) -#define PORTB_PIN6CTRL _SFR_MEM8(0x0636) -#define PORTB_PIN7CTRL _SFR_MEM8(0x0637) - -/* PORT - I/O Ports */ -#define PORTC_DIR _SFR_MEM8(0x0640) -#define PORTC_DIRSET _SFR_MEM8(0x0641) -#define PORTC_DIRCLR _SFR_MEM8(0x0642) -#define PORTC_DIRTGL _SFR_MEM8(0x0643) -#define PORTC_OUT _SFR_MEM8(0x0644) -#define PORTC_OUTSET _SFR_MEM8(0x0645) -#define PORTC_OUTCLR _SFR_MEM8(0x0646) -#define PORTC_OUTTGL _SFR_MEM8(0x0647) -#define PORTC_IN _SFR_MEM8(0x0648) -#define PORTC_INTCTRL _SFR_MEM8(0x0649) -#define PORTC_INT0MASK _SFR_MEM8(0x064A) -#define PORTC_INT1MASK _SFR_MEM8(0x064B) -#define PORTC_INTFLAGS _SFR_MEM8(0x064C) -#define PORTC_REMAP _SFR_MEM8(0x064E) -#define PORTC_PIN0CTRL _SFR_MEM8(0x0650) -#define PORTC_PIN1CTRL _SFR_MEM8(0x0651) -#define PORTC_PIN2CTRL _SFR_MEM8(0x0652) -#define PORTC_PIN3CTRL _SFR_MEM8(0x0653) -#define PORTC_PIN4CTRL _SFR_MEM8(0x0654) -#define PORTC_PIN5CTRL _SFR_MEM8(0x0655) -#define PORTC_PIN6CTRL _SFR_MEM8(0x0656) -#define PORTC_PIN7CTRL _SFR_MEM8(0x0657) - -/* PORT - I/O Ports */ -#define PORTD_DIR _SFR_MEM8(0x0660) -#define PORTD_DIRSET _SFR_MEM8(0x0661) -#define PORTD_DIRCLR _SFR_MEM8(0x0662) -#define PORTD_DIRTGL _SFR_MEM8(0x0663) -#define PORTD_OUT _SFR_MEM8(0x0664) -#define PORTD_OUTSET _SFR_MEM8(0x0665) -#define PORTD_OUTCLR _SFR_MEM8(0x0666) -#define PORTD_OUTTGL _SFR_MEM8(0x0667) -#define PORTD_IN _SFR_MEM8(0x0668) -#define PORTD_INTCTRL _SFR_MEM8(0x0669) -#define PORTD_INT0MASK _SFR_MEM8(0x066A) -#define PORTD_INT1MASK _SFR_MEM8(0x066B) -#define PORTD_INTFLAGS _SFR_MEM8(0x066C) -#define PORTD_REMAP _SFR_MEM8(0x066E) -#define PORTD_PIN0CTRL _SFR_MEM8(0x0670) -#define PORTD_PIN1CTRL _SFR_MEM8(0x0671) -#define PORTD_PIN2CTRL _SFR_MEM8(0x0672) -#define PORTD_PIN3CTRL _SFR_MEM8(0x0673) -#define PORTD_PIN4CTRL _SFR_MEM8(0x0674) -#define PORTD_PIN5CTRL _SFR_MEM8(0x0675) -#define PORTD_PIN6CTRL _SFR_MEM8(0x0676) -#define PORTD_PIN7CTRL _SFR_MEM8(0x0677) - -/* PORT - I/O Ports */ -#define PORTE_DIR _SFR_MEM8(0x0680) -#define PORTE_DIRSET _SFR_MEM8(0x0681) -#define PORTE_DIRCLR _SFR_MEM8(0x0682) -#define PORTE_DIRTGL _SFR_MEM8(0x0683) -#define PORTE_OUT _SFR_MEM8(0x0684) -#define PORTE_OUTSET _SFR_MEM8(0x0685) -#define PORTE_OUTCLR _SFR_MEM8(0x0686) -#define PORTE_OUTTGL _SFR_MEM8(0x0687) -#define PORTE_IN _SFR_MEM8(0x0688) -#define PORTE_INTCTRL _SFR_MEM8(0x0689) -#define PORTE_INT0MASK _SFR_MEM8(0x068A) -#define PORTE_INT1MASK _SFR_MEM8(0x068B) -#define PORTE_INTFLAGS _SFR_MEM8(0x068C) -#define PORTE_REMAP _SFR_MEM8(0x068E) -#define PORTE_PIN0CTRL _SFR_MEM8(0x0690) -#define PORTE_PIN1CTRL _SFR_MEM8(0x0691) -#define PORTE_PIN2CTRL _SFR_MEM8(0x0692) -#define PORTE_PIN3CTRL _SFR_MEM8(0x0693) -#define PORTE_PIN4CTRL _SFR_MEM8(0x0694) -#define PORTE_PIN5CTRL _SFR_MEM8(0x0695) -#define PORTE_PIN6CTRL _SFR_MEM8(0x0696) -#define PORTE_PIN7CTRL _SFR_MEM8(0x0697) - -/* PORT - I/O Ports */ -#define PORTR_DIR _SFR_MEM8(0x07E0) -#define PORTR_DIRSET _SFR_MEM8(0x07E1) -#define PORTR_DIRCLR _SFR_MEM8(0x07E2) -#define PORTR_DIRTGL _SFR_MEM8(0x07E3) -#define PORTR_OUT _SFR_MEM8(0x07E4) -#define PORTR_OUTSET _SFR_MEM8(0x07E5) -#define PORTR_OUTCLR _SFR_MEM8(0x07E6) -#define PORTR_OUTTGL _SFR_MEM8(0x07E7) -#define PORTR_IN _SFR_MEM8(0x07E8) -#define PORTR_INTCTRL _SFR_MEM8(0x07E9) -#define PORTR_INT0MASK _SFR_MEM8(0x07EA) -#define PORTR_INT1MASK _SFR_MEM8(0x07EB) -#define PORTR_INTFLAGS _SFR_MEM8(0x07EC) -#define PORTR_REMAP _SFR_MEM8(0x07EE) -#define PORTR_PIN0CTRL _SFR_MEM8(0x07F0) -#define PORTR_PIN1CTRL _SFR_MEM8(0x07F1) -#define PORTR_PIN2CTRL _SFR_MEM8(0x07F2) -#define PORTR_PIN3CTRL _SFR_MEM8(0x07F3) -#define PORTR_PIN4CTRL _SFR_MEM8(0x07F4) -#define PORTR_PIN5CTRL _SFR_MEM8(0x07F5) -#define PORTR_PIN6CTRL _SFR_MEM8(0x07F6) -#define PORTR_PIN7CTRL _SFR_MEM8(0x07F7) - -/* TC0 - 16-bit Timer/Counter 0 */ -#define TCC0_CTRLA _SFR_MEM8(0x0800) -#define TCC0_CTRLB _SFR_MEM8(0x0801) -#define TCC0_CTRLC _SFR_MEM8(0x0802) -#define TCC0_CTRLD _SFR_MEM8(0x0803) -#define TCC0_CTRLE _SFR_MEM8(0x0804) -#define TCC0_INTCTRLA _SFR_MEM8(0x0806) -#define TCC0_INTCTRLB _SFR_MEM8(0x0807) -#define TCC0_CTRLFCLR _SFR_MEM8(0x0808) -#define TCC0_CTRLFSET _SFR_MEM8(0x0809) -#define TCC0_CTRLGCLR _SFR_MEM8(0x080A) -#define TCC0_CTRLGSET _SFR_MEM8(0x080B) -#define TCC0_INTFLAGS _SFR_MEM8(0x080C) -#define TCC0_TEMP _SFR_MEM8(0x080F) -#define TCC0_CNT _SFR_MEM16(0x0820) -#define TCC0_PER _SFR_MEM16(0x0826) -#define TCC0_CCA _SFR_MEM16(0x0828) -#define TCC0_CCB _SFR_MEM16(0x082A) -#define TCC0_CCC _SFR_MEM16(0x082C) -#define TCC0_CCD _SFR_MEM16(0x082E) -#define TCC0_PERBUF _SFR_MEM16(0x0836) -#define TCC0_CCABUF _SFR_MEM16(0x0838) -#define TCC0_CCBBUF _SFR_MEM16(0x083A) -#define TCC0_CCCBUF _SFR_MEM16(0x083C) -#define TCC0_CCDBUF _SFR_MEM16(0x083E) - -/* TC2 - 16-bit Timer/Counter type 2 */ -#define TCC2_CTRLA _SFR_MEM8(0x0800) -#define TCC2_CTRLB _SFR_MEM8(0x0801) -#define TCC2_CTRLC _SFR_MEM8(0x0802) -#define TCC2_CTRLE _SFR_MEM8(0x0804) -#define TCC2_INTCTRLA _SFR_MEM8(0x0806) -#define TCC2_INTCTRLB _SFR_MEM8(0x0807) -#define TCC2_CTRLF _SFR_MEM8(0x0809) -#define TCC2_INTFLAGS _SFR_MEM8(0x080C) -#define TCC2_LCNT _SFR_MEM8(0x0820) -#define TCC2_HCNT _SFR_MEM8(0x0821) -#define TCC2_LPER _SFR_MEM8(0x0826) -#define TCC2_HPER _SFR_MEM8(0x0827) -#define TCC2_LCMPA _SFR_MEM8(0x0828) -#define TCC2_HCMPA _SFR_MEM8(0x0829) -#define TCC2_LCMPB _SFR_MEM8(0x082A) -#define TCC2_HCMPB _SFR_MEM8(0x082B) -#define TCC2_LCMPC _SFR_MEM8(0x082C) -#define TCC2_HCMPC _SFR_MEM8(0x082D) -#define TCC2_LCMPD _SFR_MEM8(0x082E) -#define TCC2_HCMPD _SFR_MEM8(0x082F) - -/* TC1 - 16-bit Timer/Counter 1 */ -#define TCC1_CTRLA _SFR_MEM8(0x0840) -#define TCC1_CTRLB _SFR_MEM8(0x0841) -#define TCC1_CTRLC _SFR_MEM8(0x0842) -#define TCC1_CTRLD _SFR_MEM8(0x0843) -#define TCC1_CTRLE _SFR_MEM8(0x0844) -#define TCC1_INTCTRLA _SFR_MEM8(0x0846) -#define TCC1_INTCTRLB _SFR_MEM8(0x0847) -#define TCC1_CTRLFCLR _SFR_MEM8(0x0848) -#define TCC1_CTRLFSET _SFR_MEM8(0x0849) -#define TCC1_CTRLGCLR _SFR_MEM8(0x084A) -#define TCC1_CTRLGSET _SFR_MEM8(0x084B) -#define TCC1_INTFLAGS _SFR_MEM8(0x084C) -#define TCC1_TEMP _SFR_MEM8(0x084F) -#define TCC1_CNT _SFR_MEM16(0x0860) -#define TCC1_PER _SFR_MEM16(0x0866) -#define TCC1_CCA _SFR_MEM16(0x0868) -#define TCC1_CCB _SFR_MEM16(0x086A) -#define TCC1_PERBUF _SFR_MEM16(0x0876) -#define TCC1_CCABUF _SFR_MEM16(0x0878) -#define TCC1_CCBBUF _SFR_MEM16(0x087A) - -/* AWEX - Advanced Waveform Extension */ -#define AWEXC_CTRL _SFR_MEM8(0x0880) -#define AWEXC_FDEMASK _SFR_MEM8(0x0882) -#define AWEXC_FDCTRL _SFR_MEM8(0x0883) -#define AWEXC_STATUS _SFR_MEM8(0x0884) -#define AWEXC_STATUSSET _SFR_MEM8(0x0885) -#define AWEXC_DTBOTH _SFR_MEM8(0x0886) -#define AWEXC_DTBOTHBUF _SFR_MEM8(0x0887) -#define AWEXC_DTLS _SFR_MEM8(0x0888) -#define AWEXC_DTHS _SFR_MEM8(0x0889) -#define AWEXC_DTLSBUF _SFR_MEM8(0x088A) -#define AWEXC_DTHSBUF _SFR_MEM8(0x088B) -#define AWEXC_OUTOVEN _SFR_MEM8(0x088C) - -/* HIRES - High-Resolution Extension */ -#define HIRESC_CTRLA _SFR_MEM8(0x0890) - -/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ -#define USARTC0_DATA _SFR_MEM8(0x08A0) -#define USARTC0_STATUS _SFR_MEM8(0x08A1) -#define USARTC0_CTRLA _SFR_MEM8(0x08A3) -#define USARTC0_CTRLB _SFR_MEM8(0x08A4) -#define USARTC0_CTRLC _SFR_MEM8(0x08A5) -#define USARTC0_BAUDCTRLA _SFR_MEM8(0x08A6) -#define USARTC0_BAUDCTRLB _SFR_MEM8(0x08A7) - -/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ -#define USARTC1_DATA _SFR_MEM8(0x08B0) -#define USARTC1_STATUS _SFR_MEM8(0x08B1) -#define USARTC1_CTRLA _SFR_MEM8(0x08B3) -#define USARTC1_CTRLB _SFR_MEM8(0x08B4) -#define USARTC1_CTRLC _SFR_MEM8(0x08B5) -#define USARTC1_BAUDCTRLA _SFR_MEM8(0x08B6) -#define USARTC1_BAUDCTRLB _SFR_MEM8(0x08B7) - -/* SPI - Serial Peripheral Interface */ -#define SPIC_CTRL _SFR_MEM8(0x08C0) -#define SPIC_INTCTRL _SFR_MEM8(0x08C1) -#define SPIC_STATUS _SFR_MEM8(0x08C2) -#define SPIC_DATA _SFR_MEM8(0x08C3) - -/* IRCOM - IR Communication Module */ -#define IRCOM_CTRL _SFR_MEM8(0x08F8) -#define IRCOM_TXPLCTRL _SFR_MEM8(0x08F9) -#define IRCOM_RXPLCTRL _SFR_MEM8(0x08FA) - -/* TC0 - 16-bit Timer/Counter 0 */ -#define TCD0_CTRLA _SFR_MEM8(0x0900) -#define TCD0_CTRLB _SFR_MEM8(0x0901) -#define TCD0_CTRLC _SFR_MEM8(0x0902) -#define TCD0_CTRLD _SFR_MEM8(0x0903) -#define TCD0_CTRLE _SFR_MEM8(0x0904) -#define TCD0_INTCTRLA _SFR_MEM8(0x0906) -#define TCD0_INTCTRLB _SFR_MEM8(0x0907) -#define TCD0_CTRLFCLR _SFR_MEM8(0x0908) -#define TCD0_CTRLFSET _SFR_MEM8(0x0909) -#define TCD0_CTRLGCLR _SFR_MEM8(0x090A) -#define TCD0_CTRLGSET _SFR_MEM8(0x090B) -#define TCD0_INTFLAGS _SFR_MEM8(0x090C) -#define TCD0_TEMP _SFR_MEM8(0x090F) -#define TCD0_CNT _SFR_MEM16(0x0920) -#define TCD0_PER _SFR_MEM16(0x0926) -#define TCD0_CCA _SFR_MEM16(0x0928) -#define TCD0_CCB _SFR_MEM16(0x092A) -#define TCD0_CCC _SFR_MEM16(0x092C) -#define TCD0_CCD _SFR_MEM16(0x092E) -#define TCD0_PERBUF _SFR_MEM16(0x0936) -#define TCD0_CCABUF _SFR_MEM16(0x0938) -#define TCD0_CCBBUF _SFR_MEM16(0x093A) -#define TCD0_CCCBUF _SFR_MEM16(0x093C) -#define TCD0_CCDBUF _SFR_MEM16(0x093E) - -/* TC2 - 16-bit Timer/Counter type 2 */ -#define TCD2_CTRLA _SFR_MEM8(0x0900) -#define TCD2_CTRLB _SFR_MEM8(0x0901) -#define TCD2_CTRLC _SFR_MEM8(0x0902) -#define TCD2_CTRLE _SFR_MEM8(0x0904) -#define TCD2_INTCTRLA _SFR_MEM8(0x0906) -#define TCD2_INTCTRLB _SFR_MEM8(0x0907) -#define TCD2_CTRLF _SFR_MEM8(0x0909) -#define TCD2_INTFLAGS _SFR_MEM8(0x090C) -#define TCD2_LCNT _SFR_MEM8(0x0920) -#define TCD2_HCNT _SFR_MEM8(0x0921) -#define TCD2_LPER _SFR_MEM8(0x0926) -#define TCD2_HPER _SFR_MEM8(0x0927) -#define TCD2_LCMPA _SFR_MEM8(0x0928) -#define TCD2_HCMPA _SFR_MEM8(0x0929) -#define TCD2_LCMPB _SFR_MEM8(0x092A) -#define TCD2_HCMPB _SFR_MEM8(0x092B) -#define TCD2_LCMPC _SFR_MEM8(0x092C) -#define TCD2_HCMPC _SFR_MEM8(0x092D) -#define TCD2_LCMPD _SFR_MEM8(0x092E) -#define TCD2_HCMPD _SFR_MEM8(0x092F) - -/* TC1 - 16-bit Timer/Counter 1 */ -#define TCD1_CTRLA _SFR_MEM8(0x0940) -#define TCD1_CTRLB _SFR_MEM8(0x0941) -#define TCD1_CTRLC _SFR_MEM8(0x0942) -#define TCD1_CTRLD _SFR_MEM8(0x0943) -#define TCD1_CTRLE _SFR_MEM8(0x0944) -#define TCD1_INTCTRLA _SFR_MEM8(0x0946) -#define TCD1_INTCTRLB _SFR_MEM8(0x0947) -#define TCD1_CTRLFCLR _SFR_MEM8(0x0948) -#define TCD1_CTRLFSET _SFR_MEM8(0x0949) -#define TCD1_CTRLGCLR _SFR_MEM8(0x094A) -#define TCD1_CTRLGSET _SFR_MEM8(0x094B) -#define TCD1_INTFLAGS _SFR_MEM8(0x094C) -#define TCD1_TEMP _SFR_MEM8(0x094F) -#define TCD1_CNT _SFR_MEM16(0x0960) -#define TCD1_PER _SFR_MEM16(0x0966) -#define TCD1_CCA _SFR_MEM16(0x0968) -#define TCD1_CCB _SFR_MEM16(0x096A) -#define TCD1_PERBUF _SFR_MEM16(0x0976) -#define TCD1_CCABUF _SFR_MEM16(0x0978) -#define TCD1_CCBBUF _SFR_MEM16(0x097A) - -/* HIRES - High-Resolution Extension */ -#define HIRESD_CTRLA _SFR_MEM8(0x0990) - -/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ -#define USARTD0_DATA _SFR_MEM8(0x09A0) -#define USARTD0_STATUS _SFR_MEM8(0x09A1) -#define USARTD0_CTRLA _SFR_MEM8(0x09A3) -#define USARTD0_CTRLB _SFR_MEM8(0x09A4) -#define USARTD0_CTRLC _SFR_MEM8(0x09A5) -#define USARTD0_BAUDCTRLA _SFR_MEM8(0x09A6) -#define USARTD0_BAUDCTRLB _SFR_MEM8(0x09A7) - -/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ -#define USARTD1_DATA _SFR_MEM8(0x09B0) -#define USARTD1_STATUS _SFR_MEM8(0x09B1) -#define USARTD1_CTRLA _SFR_MEM8(0x09B3) -#define USARTD1_CTRLB _SFR_MEM8(0x09B4) -#define USARTD1_CTRLC _SFR_MEM8(0x09B5) -#define USARTD1_BAUDCTRLA _SFR_MEM8(0x09B6) -#define USARTD1_BAUDCTRLB _SFR_MEM8(0x09B7) - -/* SPI - Serial Peripheral Interface */ -#define SPID_CTRL _SFR_MEM8(0x09C0) -#define SPID_INTCTRL _SFR_MEM8(0x09C1) -#define SPID_STATUS _SFR_MEM8(0x09C2) -#define SPID_DATA _SFR_MEM8(0x09C3) - -/* TC0 - 16-bit Timer/Counter 0 */ -#define TCE0_CTRLA _SFR_MEM8(0x0A00) -#define TCE0_CTRLB _SFR_MEM8(0x0A01) -#define TCE0_CTRLC _SFR_MEM8(0x0A02) -#define TCE0_CTRLD _SFR_MEM8(0x0A03) -#define TCE0_CTRLE _SFR_MEM8(0x0A04) -#define TCE0_INTCTRLA _SFR_MEM8(0x0A06) -#define TCE0_INTCTRLB _SFR_MEM8(0x0A07) -#define TCE0_CTRLFCLR _SFR_MEM8(0x0A08) -#define TCE0_CTRLFSET _SFR_MEM8(0x0A09) -#define TCE0_CTRLGCLR _SFR_MEM8(0x0A0A) -#define TCE0_CTRLGSET _SFR_MEM8(0x0A0B) -#define TCE0_INTFLAGS _SFR_MEM8(0x0A0C) -#define TCE0_TEMP _SFR_MEM8(0x0A0F) -#define TCE0_CNT _SFR_MEM16(0x0A20) -#define TCE0_PER _SFR_MEM16(0x0A26) -#define TCE0_CCA _SFR_MEM16(0x0A28) -#define TCE0_CCB _SFR_MEM16(0x0A2A) -#define TCE0_CCC _SFR_MEM16(0x0A2C) -#define TCE0_CCD _SFR_MEM16(0x0A2E) -#define TCE0_PERBUF _SFR_MEM16(0x0A36) -#define TCE0_CCABUF _SFR_MEM16(0x0A38) -#define TCE0_CCBBUF _SFR_MEM16(0x0A3A) -#define TCE0_CCCBUF _SFR_MEM16(0x0A3C) -#define TCE0_CCDBUF _SFR_MEM16(0x0A3E) - -/* HIRES - High-Resolution Extension */ -#define HIRESE_CTRLA _SFR_MEM8(0x0A90) - -/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ -#define USARTE0_DATA _SFR_MEM8(0x0AA0) -#define USARTE0_STATUS _SFR_MEM8(0x0AA1) -#define USARTE0_CTRLA _SFR_MEM8(0x0AA3) -#define USARTE0_CTRLB _SFR_MEM8(0x0AA4) -#define USARTE0_CTRLC _SFR_MEM8(0x0AA5) -#define USARTE0_BAUDCTRLA _SFR_MEM8(0x0AA6) -#define USARTE0_BAUDCTRLB _SFR_MEM8(0x0AA7) - - - -/*================== Bitfield Definitions ================== */ - -/* VPORT - Virtual Ports */ -/* VPORT.INTFLAGS bit masks and bit positions */ -#define VPORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ -#define VPORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ - -#define VPORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ -#define VPORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ - -/* XOCD - On-Chip Debug System */ -/* OCD.OCDR0 bit masks and bit positions */ -#define OCD_OCDRD_gm 0xFF /* OCDR Dirty group mask. */ -#define OCD_OCDRD_gp 0 /* OCDR Dirty group position. */ -#define OCD_OCDRD0_bm (1<<0) /* OCDR Dirty bit 0 mask. */ -#define OCD_OCDRD0_bp 0 /* OCDR Dirty bit 0 position. */ -#define OCD_OCDRD1_bm (1<<1) /* OCDR Dirty bit 1 mask. */ -#define OCD_OCDRD1_bp 1 /* OCDR Dirty bit 1 position. */ -#define OCD_OCDRD2_bm (1<<2) /* OCDR Dirty bit 2 mask. */ -#define OCD_OCDRD2_bp 2 /* OCDR Dirty bit 2 position. */ -#define OCD_OCDRD3_bm (1<<3) /* OCDR Dirty bit 3 mask. */ -#define OCD_OCDRD3_bp 3 /* OCDR Dirty bit 3 position. */ -#define OCD_OCDRD4_bm (1<<4) /* OCDR Dirty bit 4 mask. */ -#define OCD_OCDRD4_bp 4 /* OCDR Dirty bit 4 position. */ -#define OCD_OCDRD5_bm (1<<5) /* OCDR Dirty bit 5 mask. */ -#define OCD_OCDRD5_bp 5 /* OCDR Dirty bit 5 position. */ -#define OCD_OCDRD6_bm (1<<6) /* OCDR Dirty bit 6 mask. */ -#define OCD_OCDRD6_bp 6 /* OCDR Dirty bit 6 position. */ -#define OCD_OCDRD7_bm (1<<7) /* OCDR Dirty bit 7 mask. */ -#define OCD_OCDRD7_bp 7 /* OCDR Dirty bit 7 position. */ - -/* OCD.OCDR1 bit masks and bit positions */ -/* OCD_OCDRD Predefined. */ -/* OCD_OCDRD Predefined. */ - -/* CPU - CPU */ -/* CPU.CCP bit masks and bit positions */ -#define CPU_CCP_gm 0xFF /* CCP signature group mask. */ -#define CPU_CCP_gp 0 /* CCP signature group position. */ -#define CPU_CCP0_bm (1<<0) /* CCP signature bit 0 mask. */ -#define CPU_CCP0_bp 0 /* CCP signature bit 0 position. */ -#define CPU_CCP1_bm (1<<1) /* CCP signature bit 1 mask. */ -#define CPU_CCP1_bp 1 /* CCP signature bit 1 position. */ -#define CPU_CCP2_bm (1<<2) /* CCP signature bit 2 mask. */ -#define CPU_CCP2_bp 2 /* CCP signature bit 2 position. */ -#define CPU_CCP3_bm (1<<3) /* CCP signature bit 3 mask. */ -#define CPU_CCP3_bp 3 /* CCP signature bit 3 position. */ -#define CPU_CCP4_bm (1<<4) /* CCP signature bit 4 mask. */ -#define CPU_CCP4_bp 4 /* CCP signature bit 4 position. */ -#define CPU_CCP5_bm (1<<5) /* CCP signature bit 5 mask. */ -#define CPU_CCP5_bp 5 /* CCP signature bit 5 position. */ -#define CPU_CCP6_bm (1<<6) /* CCP signature bit 6 mask. */ -#define CPU_CCP6_bp 6 /* CCP signature bit 6 position. */ -#define CPU_CCP7_bm (1<<7) /* CCP signature bit 7 mask. */ -#define CPU_CCP7_bp 7 /* CCP signature bit 7 position. */ - -/* CPU.SREG bit masks and bit positions */ -#define CPU_I_bm 0x80 /* Global Interrupt Enable Flag bit mask. */ -#define CPU_I_bp 7 /* Global Interrupt Enable Flag bit position. */ - -#define CPU_T_bm 0x40 /* Transfer Bit bit mask. */ -#define CPU_T_bp 6 /* Transfer Bit bit position. */ - -#define CPU_H_bm 0x20 /* Half Carry Flag bit mask. */ -#define CPU_H_bp 5 /* Half Carry Flag bit position. */ - -#define CPU_S_bm 0x10 /* N Exclusive Or V Flag bit mask. */ -#define CPU_S_bp 4 /* N Exclusive Or V Flag bit position. */ - -#define CPU_V_bm 0x08 /* Two's Complement Overflow Flag bit mask. */ -#define CPU_V_bp 3 /* Two's Complement Overflow Flag bit position. */ - -#define CPU_N_bm 0x04 /* Negative Flag bit mask. */ -#define CPU_N_bp 2 /* Negative Flag bit position. */ - -#define CPU_Z_bm 0x02 /* Zero Flag bit mask. */ -#define CPU_Z_bp 1 /* Zero Flag bit position. */ - -#define CPU_C_bm 0x01 /* Carry Flag bit mask. */ -#define CPU_C_bp 0 /* Carry Flag bit position. */ - -/* CLK - Clock System */ -/* CLK.CTRL bit masks and bit positions */ -#define CLK_SCLKSEL_gm 0x07 /* System Clock Selection group mask. */ -#define CLK_SCLKSEL_gp 0 /* System Clock Selection group position. */ -#define CLK_SCLKSEL0_bm (1<<0) /* System Clock Selection bit 0 mask. */ -#define CLK_SCLKSEL0_bp 0 /* System Clock Selection bit 0 position. */ -#define CLK_SCLKSEL1_bm (1<<1) /* System Clock Selection bit 1 mask. */ -#define CLK_SCLKSEL1_bp 1 /* System Clock Selection bit 1 position. */ -#define CLK_SCLKSEL2_bm (1<<2) /* System Clock Selection bit 2 mask. */ -#define CLK_SCLKSEL2_bp 2 /* System Clock Selection bit 2 position. */ - -/* CLK.PSCTRL bit masks and bit positions */ -#define CLK_PSADIV_gm 0x7C /* Prescaler A Division Factor group mask. */ -#define CLK_PSADIV_gp 2 /* Prescaler A Division Factor group position. */ -#define CLK_PSADIV0_bm (1<<2) /* Prescaler A Division Factor bit 0 mask. */ -#define CLK_PSADIV0_bp 2 /* Prescaler A Division Factor bit 0 position. */ -#define CLK_PSADIV1_bm (1<<3) /* Prescaler A Division Factor bit 1 mask. */ -#define CLK_PSADIV1_bp 3 /* Prescaler A Division Factor bit 1 position. */ -#define CLK_PSADIV2_bm (1<<4) /* Prescaler A Division Factor bit 2 mask. */ -#define CLK_PSADIV2_bp 4 /* Prescaler A Division Factor bit 2 position. */ -#define CLK_PSADIV3_bm (1<<5) /* Prescaler A Division Factor bit 3 mask. */ -#define CLK_PSADIV3_bp 5 /* Prescaler A Division Factor bit 3 position. */ -#define CLK_PSADIV4_bm (1<<6) /* Prescaler A Division Factor bit 4 mask. */ -#define CLK_PSADIV4_bp 6 /* Prescaler A Division Factor bit 4 position. */ - -#define CLK_PSBCDIV_gm 0x03 /* Prescaler B and C Division factor group mask. */ -#define CLK_PSBCDIV_gp 0 /* Prescaler B and C Division factor group position. */ -#define CLK_PSBCDIV0_bm (1<<0) /* Prescaler B and C Division factor bit 0 mask. */ -#define CLK_PSBCDIV0_bp 0 /* Prescaler B and C Division factor bit 0 position. */ -#define CLK_PSBCDIV1_bm (1<<1) /* Prescaler B and C Division factor bit 1 mask. */ -#define CLK_PSBCDIV1_bp 1 /* Prescaler B and C Division factor bit 1 position. */ - -/* CLK.LOCK bit masks and bit positions */ -#define CLK_LOCK_bm 0x01 /* Clock System Lock bit mask. */ -#define CLK_LOCK_bp 0 /* Clock System Lock bit position. */ - -/* CLK.RTCCTRL bit masks and bit positions */ -#define CLK_RTCSRC_gm 0x0E /* Clock Source group mask. */ -#define CLK_RTCSRC_gp 1 /* Clock Source group position. */ -#define CLK_RTCSRC0_bm (1<<1) /* Clock Source bit 0 mask. */ -#define CLK_RTCSRC0_bp 1 /* Clock Source bit 0 position. */ -#define CLK_RTCSRC1_bm (1<<2) /* Clock Source bit 1 mask. */ -#define CLK_RTCSRC1_bp 2 /* Clock Source bit 1 position. */ -#define CLK_RTCSRC2_bm (1<<3) /* Clock Source bit 2 mask. */ -#define CLK_RTCSRC2_bp 3 /* Clock Source bit 2 position. */ - -#define CLK_RTCEN_bm 0x01 /* Clock Source Enable bit mask. */ -#define CLK_RTCEN_bp 0 /* Clock Source Enable bit position. */ - -/* CLK.USBCTRL bit masks and bit positions */ -#define CLK_USBPSDIV_gm 0x38 /* Prescaler Division Factor group mask. */ -#define CLK_USBPSDIV_gp 3 /* Prescaler Division Factor group position. */ -#define CLK_USBPSDIV0_bm (1<<3) /* Prescaler Division Factor bit 0 mask. */ -#define CLK_USBPSDIV0_bp 3 /* Prescaler Division Factor bit 0 position. */ -#define CLK_USBPSDIV1_bm (1<<4) /* Prescaler Division Factor bit 1 mask. */ -#define CLK_USBPSDIV1_bp 4 /* Prescaler Division Factor bit 1 position. */ -#define CLK_USBPSDIV2_bm (1<<5) /* Prescaler Division Factor bit 2 mask. */ -#define CLK_USBPSDIV2_bp 5 /* Prescaler Division Factor bit 2 position. */ - -#define CLK_USBSRC_gm 0x06 /* Clock Source group mask. */ -#define CLK_USBSRC_gp 1 /* Clock Source group position. */ -#define CLK_USBSRC0_bm (1<<1) /* Clock Source bit 0 mask. */ -#define CLK_USBSRC0_bp 1 /* Clock Source bit 0 position. */ -#define CLK_USBSRC1_bm (1<<2) /* Clock Source bit 1 mask. */ -#define CLK_USBSRC1_bp 2 /* Clock Source bit 1 position. */ - -#define CLK_USBSEN_bm 0x01 /* Clock Source Enable bit mask. */ -#define CLK_USBSEN_bp 0 /* Clock Source Enable bit position. */ - -/* PR.PRGEN bit masks and bit positions */ -#define PR_USB_bm 0x40 /* USB bit mask. */ -#define PR_USB_bp 6 /* USB bit position. */ - -#define PR_AES_bm 0x10 /* AES bit mask. */ -#define PR_AES_bp 4 /* AES bit position. */ - -#define PR_EBI_bm 0x08 /* External Bus Interface bit mask. */ -#define PR_EBI_bp 3 /* External Bus Interface bit position. */ - -#define PR_RTC_bm 0x04 /* Real-time Counter bit mask. */ -#define PR_RTC_bp 2 /* Real-time Counter bit position. */ - -#define PR_EVSYS_bm 0x02 /* Event System bit mask. */ -#define PR_EVSYS_bp 1 /* Event System bit position. */ - -#define PR_DMA_bm 0x01 /* DMA-Controller bit mask. */ -#define PR_DMA_bp 0 /* DMA-Controller bit position. */ - -/* PR.PRPA bit masks and bit positions */ -#define PR_DAC_bm 0x04 /* Port A DAC bit mask. */ -#define PR_DAC_bp 2 /* Port A DAC bit position. */ - -#define PR_ADC_bm 0x02 /* Port A ADC bit mask. */ -#define PR_ADC_bp 1 /* Port A ADC bit position. */ - -#define PR_AC_bm 0x01 /* Port A Analog Comparator bit mask. */ -#define PR_AC_bp 0 /* Port A Analog Comparator bit position. */ - -/* PR.PRPB bit masks and bit positions */ -/* PR_DAC Predefined. */ -/* PR_DAC Predefined. */ - -/* PR_ADC Predefined. */ -/* PR_ADC Predefined. */ - -/* PR_AC Predefined. */ -/* PR_AC Predefined. */ - -/* PR.PRPC bit masks and bit positions */ -#define PR_TWI_bm 0x40 /* Port C Two-wire Interface bit mask. */ -#define PR_TWI_bp 6 /* Port C Two-wire Interface bit position. */ - -#define PR_USART1_bm 0x20 /* Port C USART1 bit mask. */ -#define PR_USART1_bp 5 /* Port C USART1 bit position. */ - -#define PR_USART0_bm 0x10 /* Port C USART0 bit mask. */ -#define PR_USART0_bp 4 /* Port C USART0 bit position. */ - -#define PR_SPI_bm 0x08 /* Port C SPI bit mask. */ -#define PR_SPI_bp 3 /* Port C SPI bit position. */ - -#define PR_HIRES_bm 0x04 /* Port C AWEX bit mask. */ -#define PR_HIRES_bp 2 /* Port C AWEX bit position. */ - -#define PR_TC1_bm 0x02 /* Port C Timer/Counter1 bit mask. */ -#define PR_TC1_bp 1 /* Port C Timer/Counter1 bit position. */ - -#define PR_TC0_bm 0x01 /* Port C Timer/Counter0 bit mask. */ -#define PR_TC0_bp 0 /* Port C Timer/Counter0 bit position. */ - -/* PR.PRPD bit masks and bit positions */ -/* PR_TWI Predefined. */ -/* PR_TWI Predefined. */ - -/* PR_USART1 Predefined. */ -/* PR_USART1 Predefined. */ - -/* PR_USART0 Predefined. */ -/* PR_USART0 Predefined. */ - -/* PR_SPI Predefined. */ -/* PR_SPI Predefined. */ - -/* PR_HIRES Predefined. */ -/* PR_HIRES Predefined. */ - -/* PR_TC1 Predefined. */ -/* PR_TC1 Predefined. */ - -/* PR_TC0 Predefined. */ -/* PR_TC0 Predefined. */ - -/* PR.PRPE bit masks and bit positions */ -/* PR_TWI Predefined. */ -/* PR_TWI Predefined. */ - -/* PR_USART1 Predefined. */ -/* PR_USART1 Predefined. */ - -/* PR_USART0 Predefined. */ -/* PR_USART0 Predefined. */ - -/* PR_SPI Predefined. */ -/* PR_SPI Predefined. */ - -/* PR_HIRES Predefined. */ -/* PR_HIRES Predefined. */ - -/* PR_TC1 Predefined. */ -/* PR_TC1 Predefined. */ - -/* PR_TC0 Predefined. */ -/* PR_TC0 Predefined. */ - -/* PR.PRPF bit masks and bit positions */ -/* PR_TWI Predefined. */ -/* PR_TWI Predefined. */ - -/* PR_USART1 Predefined. */ -/* PR_USART1 Predefined. */ - -/* PR_USART0 Predefined. */ -/* PR_USART0 Predefined. */ - -/* PR_SPI Predefined. */ -/* PR_SPI Predefined. */ - -/* PR_HIRES Predefined. */ -/* PR_HIRES Predefined. */ - -/* PR_TC1 Predefined. */ -/* PR_TC1 Predefined. */ - -/* PR_TC0 Predefined. */ -/* PR_TC0 Predefined. */ - -/* SLEEP - Sleep Controller */ -/* SLEEP.CTRL bit masks and bit positions */ -#define SLEEP_SMODE_gm 0x0E /* Sleep Mode group mask. */ -#define SLEEP_SMODE_gp 1 /* Sleep Mode group position. */ -#define SLEEP_SMODE0_bm (1<<1) /* Sleep Mode bit 0 mask. */ -#define SLEEP_SMODE0_bp 1 /* Sleep Mode bit 0 position. */ -#define SLEEP_SMODE1_bm (1<<2) /* Sleep Mode bit 1 mask. */ -#define SLEEP_SMODE1_bp 2 /* Sleep Mode bit 1 position. */ -#define SLEEP_SMODE2_bm (1<<3) /* Sleep Mode bit 2 mask. */ -#define SLEEP_SMODE2_bp 3 /* Sleep Mode bit 2 position. */ - -#define SLEEP_SEN_bm 0x01 /* Sleep Enable bit mask. */ -#define SLEEP_SEN_bp 0 /* Sleep Enable bit position. */ - -/* OSC - Oscillator */ -/* OSC.CTRL bit masks and bit positions */ -#define OSC_PLLEN_bm 0x10 /* PLL Enable bit mask. */ -#define OSC_PLLEN_bp 4 /* PLL Enable bit position. */ - -#define OSC_XOSCEN_bm 0x08 /* External Oscillator Enable bit mask. */ -#define OSC_XOSCEN_bp 3 /* External Oscillator Enable bit position. */ - -#define OSC_RC32KEN_bm 0x04 /* Internal 32.768 kHz RC Oscillator Enable bit mask. */ -#define OSC_RC32KEN_bp 2 /* Internal 32.768 kHz RC Oscillator Enable bit position. */ - -#define OSC_RC32MEN_bm 0x02 /* Internal 32 MHz RC Oscillator Enable bit mask. */ -#define OSC_RC32MEN_bp 1 /* Internal 32 MHz RC Oscillator Enable bit position. */ - -#define OSC_RC2MEN_bm 0x01 /* Internal 2 MHz RC Oscillator Enable bit mask. */ -#define OSC_RC2MEN_bp 0 /* Internal 2 MHz RC Oscillator Enable bit position. */ - -/* OSC.STATUS bit masks and bit positions */ -#define OSC_PLLRDY_bm 0x10 /* PLL Ready bit mask. */ -#define OSC_PLLRDY_bp 4 /* PLL Ready bit position. */ - -#define OSC_XOSCRDY_bm 0x08 /* External Oscillator Ready bit mask. */ -#define OSC_XOSCRDY_bp 3 /* External Oscillator Ready bit position. */ - -#define OSC_RC32KRDY_bm 0x04 /* Internal 32.768 kHz RC Oscillator Ready bit mask. */ -#define OSC_RC32KRDY_bp 2 /* Internal 32.768 kHz RC Oscillator Ready bit position. */ - -#define OSC_RC32MRDY_bm 0x02 /* Internal 32 MHz RC Oscillator Ready bit mask. */ -#define OSC_RC32MRDY_bp 1 /* Internal 32 MHz RC Oscillator Ready bit position. */ - -#define OSC_RC2MRDY_bm 0x01 /* Internal 2 MHz RC Oscillator Ready bit mask. */ -#define OSC_RC2MRDY_bp 0 /* Internal 2 MHz RC Oscillator Ready bit position. */ - -/* OSC.XOSCCTRL bit masks and bit positions */ -#define OSC_FRQRANGE_gm 0xC0 /* Frequency Range group mask. */ -#define OSC_FRQRANGE_gp 6 /* Frequency Range group position. */ -#define OSC_FRQRANGE0_bm (1<<6) /* Frequency Range bit 0 mask. */ -#define OSC_FRQRANGE0_bp 6 /* Frequency Range bit 0 position. */ -#define OSC_FRQRANGE1_bm (1<<7) /* Frequency Range bit 1 mask. */ -#define OSC_FRQRANGE1_bp 7 /* Frequency Range bit 1 position. */ - -#define OSC_X32KLPM_bm 0x20 /* 32.768 kHz XTAL OSC Low-power Mode bit mask. */ -#define OSC_X32KLPM_bp 5 /* 32.768 kHz XTAL OSC Low-power Mode bit position. */ - -#define OSC_XOSCPWR_bm 0x10 /* 16 MHz Crystal Oscillator High Power mode bit mask. */ -#define OSC_XOSCPWR_bp 4 /* 16 MHz Crystal Oscillator High Power mode bit position. */ - -#define OSC_XOSCSEL_gm 0x0F /* External Oscillator Selection and Startup Time group mask. */ -#define OSC_XOSCSEL_gp 0 /* External Oscillator Selection and Startup Time group position. */ -#define OSC_XOSCSEL0_bm (1<<0) /* External Oscillator Selection and Startup Time bit 0 mask. */ -#define OSC_XOSCSEL0_bp 0 /* External Oscillator Selection and Startup Time bit 0 position. */ -#define OSC_XOSCSEL1_bm (1<<1) /* External Oscillator Selection and Startup Time bit 1 mask. */ -#define OSC_XOSCSEL1_bp 1 /* External Oscillator Selection and Startup Time bit 1 position. */ -#define OSC_XOSCSEL2_bm (1<<2) /* External Oscillator Selection and Startup Time bit 2 mask. */ -#define OSC_XOSCSEL2_bp 2 /* External Oscillator Selection and Startup Time bit 2 position. */ -#define OSC_XOSCSEL3_bm (1<<3) /* External Oscillator Selection and Startup Time bit 3 mask. */ -#define OSC_XOSCSEL3_bp 3 /* External Oscillator Selection and Startup Time bit 3 position. */ - -/* OSC.XOSCFAIL bit masks and bit positions */ -#define OSC_PLLFDIF_bm 0x08 /* PLL Failure Detection Interrupt Flag bit mask. */ -#define OSC_PLLFDIF_bp 3 /* PLL Failure Detection Interrupt Flag bit position. */ - -#define OSC_PLLFDEN_bm 0x04 /* PLL Failure Detection Enable bit mask. */ -#define OSC_PLLFDEN_bp 2 /* PLL Failure Detection Enable bit position. */ - -#define OSC_XOSCFDIF_bm 0x02 /* XOSC Failure Detection Interrupt Flag bit mask. */ -#define OSC_XOSCFDIF_bp 1 /* XOSC Failure Detection Interrupt Flag bit position. */ - -#define OSC_XOSCFDEN_bm 0x01 /* XOSC Failure Detection Enable bit mask. */ -#define OSC_XOSCFDEN_bp 0 /* XOSC Failure Detection Enable bit position. */ - -/* OSC.PLLCTRL bit masks and bit positions */ -#define OSC_PLLSRC_gm 0xC0 /* Clock Source group mask. */ -#define OSC_PLLSRC_gp 6 /* Clock Source group position. */ -#define OSC_PLLSRC0_bm (1<<6) /* Clock Source bit 0 mask. */ -#define OSC_PLLSRC0_bp 6 /* Clock Source bit 0 position. */ -#define OSC_PLLSRC1_bm (1<<7) /* Clock Source bit 1 mask. */ -#define OSC_PLLSRC1_bp 7 /* Clock Source bit 1 position. */ - -#define OSC_PLLDIV_bm 0x20 /* Divide by 2 bit mask. */ -#define OSC_PLLDIV_bp 5 /* Divide by 2 bit position. */ - -#define OSC_PLLFAC_gm 0x1F /* Multiplication Factor group mask. */ -#define OSC_PLLFAC_gp 0 /* Multiplication Factor group position. */ -#define OSC_PLLFAC0_bm (1<<0) /* Multiplication Factor bit 0 mask. */ -#define OSC_PLLFAC0_bp 0 /* Multiplication Factor bit 0 position. */ -#define OSC_PLLFAC1_bm (1<<1) /* Multiplication Factor bit 1 mask. */ -#define OSC_PLLFAC1_bp 1 /* Multiplication Factor bit 1 position. */ -#define OSC_PLLFAC2_bm (1<<2) /* Multiplication Factor bit 2 mask. */ -#define OSC_PLLFAC2_bp 2 /* Multiplication Factor bit 2 position. */ -#define OSC_PLLFAC3_bm (1<<3) /* Multiplication Factor bit 3 mask. */ -#define OSC_PLLFAC3_bp 3 /* Multiplication Factor bit 3 position. */ -#define OSC_PLLFAC4_bm (1<<4) /* Multiplication Factor bit 4 mask. */ -#define OSC_PLLFAC4_bp 4 /* Multiplication Factor bit 4 position. */ - -/* OSC.DFLLCTRL bit masks and bit positions */ -#define OSC_RC32MCREF_gm 0x06 /* 32 MHz DFLL Calibration Reference group mask. */ -#define OSC_RC32MCREF_gp 1 /* 32 MHz DFLL Calibration Reference group position. */ -#define OSC_RC32MCREF0_bm (1<<1) /* 32 MHz DFLL Calibration Reference bit 0 mask. */ -#define OSC_RC32MCREF0_bp 1 /* 32 MHz DFLL Calibration Reference bit 0 position. */ -#define OSC_RC32MCREF1_bm (1<<2) /* 32 MHz DFLL Calibration Reference bit 1 mask. */ -#define OSC_RC32MCREF1_bp 2 /* 32 MHz DFLL Calibration Reference bit 1 position. */ - -#define OSC_RC2MCREF_bm 0x01 /* 2 MHz DFLL Calibration Reference bit mask. */ -#define OSC_RC2MCREF_bp 0 /* 2 MHz DFLL Calibration Reference bit position. */ - -/* DFLL - DFLL */ -/* DFLL.CTRL bit masks and bit positions */ -#define DFLL_ENABLE_bm 0x01 /* DFLL Enable bit mask. */ -#define DFLL_ENABLE_bp 0 /* DFLL Enable bit position. */ - -/* DFLL.CALA bit masks and bit positions */ -#define DFLL_CALL_gm 0x7F /* DFLL Calibration Value A group mask. */ -#define DFLL_CALL_gp 0 /* DFLL Calibration Value A group position. */ -#define DFLL_CALL0_bm (1<<0) /* DFLL Calibration Value A bit 0 mask. */ -#define DFLL_CALL0_bp 0 /* DFLL Calibration Value A bit 0 position. */ -#define DFLL_CALL1_bm (1<<1) /* DFLL Calibration Value A bit 1 mask. */ -#define DFLL_CALL1_bp 1 /* DFLL Calibration Value A bit 1 position. */ -#define DFLL_CALL2_bm (1<<2) /* DFLL Calibration Value A bit 2 mask. */ -#define DFLL_CALL2_bp 2 /* DFLL Calibration Value A bit 2 position. */ -#define DFLL_CALL3_bm (1<<3) /* DFLL Calibration Value A bit 3 mask. */ -#define DFLL_CALL3_bp 3 /* DFLL Calibration Value A bit 3 position. */ -#define DFLL_CALL4_bm (1<<4) /* DFLL Calibration Value A bit 4 mask. */ -#define DFLL_CALL4_bp 4 /* DFLL Calibration Value A bit 4 position. */ -#define DFLL_CALL5_bm (1<<5) /* DFLL Calibration Value A bit 5 mask. */ -#define DFLL_CALL5_bp 5 /* DFLL Calibration Value A bit 5 position. */ -#define DFLL_CALL6_bm (1<<6) /* DFLL Calibration Value A bit 6 mask. */ -#define DFLL_CALL6_bp 6 /* DFLL Calibration Value A bit 6 position. */ - -/* DFLL.CALB bit masks and bit positions */ -#define DFLL_CALH_gm 0x3F /* DFLL Calibration Value B group mask. */ -#define DFLL_CALH_gp 0 /* DFLL Calibration Value B group position. */ -#define DFLL_CALH0_bm (1<<0) /* DFLL Calibration Value B bit 0 mask. */ -#define DFLL_CALH0_bp 0 /* DFLL Calibration Value B bit 0 position. */ -#define DFLL_CALH1_bm (1<<1) /* DFLL Calibration Value B bit 1 mask. */ -#define DFLL_CALH1_bp 1 /* DFLL Calibration Value B bit 1 position. */ -#define DFLL_CALH2_bm (1<<2) /* DFLL Calibration Value B bit 2 mask. */ -#define DFLL_CALH2_bp 2 /* DFLL Calibration Value B bit 2 position. */ -#define DFLL_CALH3_bm (1<<3) /* DFLL Calibration Value B bit 3 mask. */ -#define DFLL_CALH3_bp 3 /* DFLL Calibration Value B bit 3 position. */ -#define DFLL_CALH4_bm (1<<4) /* DFLL Calibration Value B bit 4 mask. */ -#define DFLL_CALH4_bp 4 /* DFLL Calibration Value B bit 4 position. */ -#define DFLL_CALH5_bm (1<<5) /* DFLL Calibration Value B bit 5 mask. */ -#define DFLL_CALH5_bp 5 /* DFLL Calibration Value B bit 5 position. */ - -/* RST - Reset */ -/* RST.STATUS bit masks and bit positions */ -#define RST_SDRF_bm 0x40 /* Spike Detection Reset Flag bit mask. */ -#define RST_SDRF_bp 6 /* Spike Detection Reset Flag bit position. */ - -#define RST_SRF_bm 0x20 /* Software Reset Flag bit mask. */ -#define RST_SRF_bp 5 /* Software Reset Flag bit position. */ - -#define RST_PDIRF_bm 0x10 /* Programming and Debug Interface Interface Reset Flag bit mask. */ -#define RST_PDIRF_bp 4 /* Programming and Debug Interface Interface Reset Flag bit position. */ - -#define RST_WDRF_bm 0x08 /* Watchdog Reset Flag bit mask. */ -#define RST_WDRF_bp 3 /* Watchdog Reset Flag bit position. */ - -#define RST_BORF_bm 0x04 /* Brown-out Reset Flag bit mask. */ -#define RST_BORF_bp 2 /* Brown-out Reset Flag bit position. */ - -#define RST_EXTRF_bm 0x02 /* External Reset Flag bit mask. */ -#define RST_EXTRF_bp 1 /* External Reset Flag bit position. */ - -#define RST_PORF_bm 0x01 /* Power-on Reset Flag bit mask. */ -#define RST_PORF_bp 0 /* Power-on Reset Flag bit position. */ - -/* RST.CTRL bit masks and bit positions */ -#define RST_SWRST_bm 0x01 /* Software Reset bit mask. */ -#define RST_SWRST_bp 0 /* Software Reset bit position. */ - -/* WDT - Watch-Dog Timer */ -/* WDT.CTRL bit masks and bit positions */ -#define WDT_PER_gm 0x3C /* Period group mask. */ -#define WDT_PER_gp 2 /* Period group position. */ -#define WDT_PER0_bm (1<<2) /* Period bit 0 mask. */ -#define WDT_PER0_bp 2 /* Period bit 0 position. */ -#define WDT_PER1_bm (1<<3) /* Period bit 1 mask. */ -#define WDT_PER1_bp 3 /* Period bit 1 position. */ -#define WDT_PER2_bm (1<<4) /* Period bit 2 mask. */ -#define WDT_PER2_bp 4 /* Period bit 2 position. */ -#define WDT_PER3_bm (1<<5) /* Period bit 3 mask. */ -#define WDT_PER3_bp 5 /* Period bit 3 position. */ - -#define WDT_ENABLE_bm 0x02 /* Enable bit mask. */ -#define WDT_ENABLE_bp 1 /* Enable bit position. */ - -#define WDT_CEN_bm 0x01 /* Change Enable bit mask. */ -#define WDT_CEN_bp 0 /* Change Enable bit position. */ - -/* WDT.WINCTRL bit masks and bit positions */ -#define WDT_WPER_gm 0x3C /* Windowed Mode Period group mask. */ -#define WDT_WPER_gp 2 /* Windowed Mode Period group position. */ -#define WDT_WPER0_bm (1<<2) /* Windowed Mode Period bit 0 mask. */ -#define WDT_WPER0_bp 2 /* Windowed Mode Period bit 0 position. */ -#define WDT_WPER1_bm (1<<3) /* Windowed Mode Period bit 1 mask. */ -#define WDT_WPER1_bp 3 /* Windowed Mode Period bit 1 position. */ -#define WDT_WPER2_bm (1<<4) /* Windowed Mode Period bit 2 mask. */ -#define WDT_WPER2_bp 4 /* Windowed Mode Period bit 2 position. */ -#define WDT_WPER3_bm (1<<5) /* Windowed Mode Period bit 3 mask. */ -#define WDT_WPER3_bp 5 /* Windowed Mode Period bit 3 position. */ - -#define WDT_WEN_bm 0x02 /* Windowed Mode Enable bit mask. */ -#define WDT_WEN_bp 1 /* Windowed Mode Enable bit position. */ - -#define WDT_WCEN_bm 0x01 /* Windowed Mode Change Enable bit mask. */ -#define WDT_WCEN_bp 0 /* Windowed Mode Change Enable bit position. */ - -/* WDT.STATUS bit masks and bit positions */ -#define WDT_SYNCBUSY_bm 0x01 /* Syncronization busy bit mask. */ -#define WDT_SYNCBUSY_bp 0 /* Syncronization busy bit position. */ - -/* MCU - MCU Control */ -/* MCU.MCUCR bit masks and bit positions */ -#define MCU_JTAGD_bm 0x01 /* JTAG Disable bit mask. */ -#define MCU_JTAGD_bp 0 /* JTAG Disable bit position. */ - -/* MCU.ANAINIT bit masks and bit positions */ -#define MCU_STARTUPDLYB_gm 0x0C /* Analog startup delay Port B group mask. */ -#define MCU_STARTUPDLYB_gp 2 /* Analog startup delay Port B group position. */ -#define MCU_STARTUPDLYB0_bm (1<<2) /* Analog startup delay Port B bit 0 mask. */ -#define MCU_STARTUPDLYB0_bp 2 /* Analog startup delay Port B bit 0 position. */ -#define MCU_STARTUPDLYB1_bm (1<<3) /* Analog startup delay Port B bit 1 mask. */ -#define MCU_STARTUPDLYB1_bp 3 /* Analog startup delay Port B bit 1 position. */ - -#define MCU_STARTUPDLYA_gm 0x03 /* Analog startup delay Port A group mask. */ -#define MCU_STARTUPDLYA_gp 0 /* Analog startup delay Port A group position. */ -#define MCU_STARTUPDLYA0_bm (1<<0) /* Analog startup delay Port A bit 0 mask. */ -#define MCU_STARTUPDLYA0_bp 0 /* Analog startup delay Port A bit 0 position. */ -#define MCU_STARTUPDLYA1_bm (1<<1) /* Analog startup delay Port A bit 1 mask. */ -#define MCU_STARTUPDLYA1_bp 1 /* Analog startup delay Port A bit 1 position. */ - -/* MCU.EVSYSLOCK bit masks and bit positions */ -#define MCU_EVSYS1LOCK_bm 0x10 /* Event Channel 4-7 Lock bit mask. */ -#define MCU_EVSYS1LOCK_bp 4 /* Event Channel 4-7 Lock bit position. */ - -#define MCU_EVSYS0LOCK_bm 0x01 /* Event Channel 0-3 Lock bit mask. */ -#define MCU_EVSYS0LOCK_bp 0 /* Event Channel 0-3 Lock bit position. */ - -/* MCU.AWEXLOCK bit masks and bit positions */ -#define MCU_AWEXFLOCK_bm 0x08 /* AWeX on T/C F0 Lock bit mask. */ -#define MCU_AWEXFLOCK_bp 3 /* AWeX on T/C F0 Lock bit position. */ - -#define MCU_AWEXELOCK_bm 0x04 /* AWeX on T/C E0 Lock bit mask. */ -#define MCU_AWEXELOCK_bp 2 /* AWeX on T/C E0 Lock bit position. */ - -#define MCU_AWEXDLOCK_bm 0x02 /* AWeX on T/C D0 Lock bit mask. */ -#define MCU_AWEXDLOCK_bp 1 /* AWeX on T/C D0 Lock bit position. */ - -#define MCU_AWEXCLOCK_bm 0x01 /* AWeX on T/C C0 Lock bit mask. */ -#define MCU_AWEXCLOCK_bp 0 /* AWeX on T/C C0 Lock bit position. */ - -/* PMIC - Programmable Multi-level Interrupt Controller */ -/* PMIC.STATUS bit masks and bit positions */ -#define PMIC_NMIEX_bm 0x80 /* Non-maskable Interrupt Executing bit mask. */ -#define PMIC_NMIEX_bp 7 /* Non-maskable Interrupt Executing bit position. */ - -#define PMIC_HILVLEX_bm 0x04 /* High Level Interrupt Executing bit mask. */ -#define PMIC_HILVLEX_bp 2 /* High Level Interrupt Executing bit position. */ - -#define PMIC_MEDLVLEX_bm 0x02 /* Medium Level Interrupt Executing bit mask. */ -#define PMIC_MEDLVLEX_bp 1 /* Medium Level Interrupt Executing bit position. */ - -#define PMIC_LOLVLEX_bm 0x01 /* Low Level Interrupt Executing bit mask. */ -#define PMIC_LOLVLEX_bp 0 /* Low Level Interrupt Executing bit position. */ - -/* PMIC.INTPRI bit masks and bit positions */ -#define PMIC_INTPRI_gm 0xFF /* Interrupt Priority group mask. */ -#define PMIC_INTPRI_gp 0 /* Interrupt Priority group position. */ -#define PMIC_INTPRI0_bm (1<<0) /* Interrupt Priority bit 0 mask. */ -#define PMIC_INTPRI0_bp 0 /* Interrupt Priority bit 0 position. */ -#define PMIC_INTPRI1_bm (1<<1) /* Interrupt Priority bit 1 mask. */ -#define PMIC_INTPRI1_bp 1 /* Interrupt Priority bit 1 position. */ -#define PMIC_INTPRI2_bm (1<<2) /* Interrupt Priority bit 2 mask. */ -#define PMIC_INTPRI2_bp 2 /* Interrupt Priority bit 2 position. */ -#define PMIC_INTPRI3_bm (1<<3) /* Interrupt Priority bit 3 mask. */ -#define PMIC_INTPRI3_bp 3 /* Interrupt Priority bit 3 position. */ -#define PMIC_INTPRI4_bm (1<<4) /* Interrupt Priority bit 4 mask. */ -#define PMIC_INTPRI4_bp 4 /* Interrupt Priority bit 4 position. */ -#define PMIC_INTPRI5_bm (1<<5) /* Interrupt Priority bit 5 mask. */ -#define PMIC_INTPRI5_bp 5 /* Interrupt Priority bit 5 position. */ -#define PMIC_INTPRI6_bm (1<<6) /* Interrupt Priority bit 6 mask. */ -#define PMIC_INTPRI6_bp 6 /* Interrupt Priority bit 6 position. */ -#define PMIC_INTPRI7_bm (1<<7) /* Interrupt Priority bit 7 mask. */ -#define PMIC_INTPRI7_bp 7 /* Interrupt Priority bit 7 position. */ - -/* PMIC.CTRL bit masks and bit positions */ -#define PMIC_RREN_bm 0x80 /* Round-Robin Priority Enable bit mask. */ -#define PMIC_RREN_bp 7 /* Round-Robin Priority Enable bit position. */ - -#define PMIC_IVSEL_bm 0x40 /* Interrupt Vector Select bit mask. */ -#define PMIC_IVSEL_bp 6 /* Interrupt Vector Select bit position. */ - -#define PMIC_HILVLEN_bm 0x04 /* High Level Enable bit mask. */ -#define PMIC_HILVLEN_bp 2 /* High Level Enable bit position. */ - -#define PMIC_MEDLVLEN_bm 0x02 /* Medium Level Enable bit mask. */ -#define PMIC_MEDLVLEN_bp 1 /* Medium Level Enable bit position. */ - -#define PMIC_LOLVLEN_bm 0x01 /* Low Level Enable bit mask. */ -#define PMIC_LOLVLEN_bp 0 /* Low Level Enable bit position. */ - -/* PORTCFG - Port Configuration */ -/* PORTCFG.VPCTRLA bit masks and bit positions */ -#define PORTCFG_VP1MAP_gm 0xF0 /* Virtual Port 1 Mapping group mask. */ -#define PORTCFG_VP1MAP_gp 4 /* Virtual Port 1 Mapping group position. */ -#define PORTCFG_VP1MAP0_bm (1<<4) /* Virtual Port 1 Mapping bit 0 mask. */ -#define PORTCFG_VP1MAP0_bp 4 /* Virtual Port 1 Mapping bit 0 position. */ -#define PORTCFG_VP1MAP1_bm (1<<5) /* Virtual Port 1 Mapping bit 1 mask. */ -#define PORTCFG_VP1MAP1_bp 5 /* Virtual Port 1 Mapping bit 1 position. */ -#define PORTCFG_VP1MAP2_bm (1<<6) /* Virtual Port 1 Mapping bit 2 mask. */ -#define PORTCFG_VP1MAP2_bp 6 /* Virtual Port 1 Mapping bit 2 position. */ -#define PORTCFG_VP1MAP3_bm (1<<7) /* Virtual Port 1 Mapping bit 3 mask. */ -#define PORTCFG_VP1MAP3_bp 7 /* Virtual Port 1 Mapping bit 3 position. */ - -#define PORTCFG_VP0MAP_gm 0x0F /* Virtual Port 0 Mapping group mask. */ -#define PORTCFG_VP0MAP_gp 0 /* Virtual Port 0 Mapping group position. */ -#define PORTCFG_VP0MAP0_bm (1<<0) /* Virtual Port 0 Mapping bit 0 mask. */ -#define PORTCFG_VP0MAP0_bp 0 /* Virtual Port 0 Mapping bit 0 position. */ -#define PORTCFG_VP0MAP1_bm (1<<1) /* Virtual Port 0 Mapping bit 1 mask. */ -#define PORTCFG_VP0MAP1_bp 1 /* Virtual Port 0 Mapping bit 1 position. */ -#define PORTCFG_VP0MAP2_bm (1<<2) /* Virtual Port 0 Mapping bit 2 mask. */ -#define PORTCFG_VP0MAP2_bp 2 /* Virtual Port 0 Mapping bit 2 position. */ -#define PORTCFG_VP0MAP3_bm (1<<3) /* Virtual Port 0 Mapping bit 3 mask. */ -#define PORTCFG_VP0MAP3_bp 3 /* Virtual Port 0 Mapping bit 3 position. */ - -/* PORTCFG.VPCTRLB bit masks and bit positions */ -#define PORTCFG_VP3MAP_gm 0xF0 /* Virtual Port 3 Mapping group mask. */ -#define PORTCFG_VP3MAP_gp 4 /* Virtual Port 3 Mapping group position. */ -#define PORTCFG_VP3MAP0_bm (1<<4) /* Virtual Port 3 Mapping bit 0 mask. */ -#define PORTCFG_VP3MAP0_bp 4 /* Virtual Port 3 Mapping bit 0 position. */ -#define PORTCFG_VP3MAP1_bm (1<<5) /* Virtual Port 3 Mapping bit 1 mask. */ -#define PORTCFG_VP3MAP1_bp 5 /* Virtual Port 3 Mapping bit 1 position. */ -#define PORTCFG_VP3MAP2_bm (1<<6) /* Virtual Port 3 Mapping bit 2 mask. */ -#define PORTCFG_VP3MAP2_bp 6 /* Virtual Port 3 Mapping bit 2 position. */ -#define PORTCFG_VP3MAP3_bm (1<<7) /* Virtual Port 3 Mapping bit 3 mask. */ -#define PORTCFG_VP3MAP3_bp 7 /* Virtual Port 3 Mapping bit 3 position. */ - -#define PORTCFG_VP2MAP_gm 0x0F /* Virtual Port 2 Mapping group mask. */ -#define PORTCFG_VP2MAP_gp 0 /* Virtual Port 2 Mapping group position. */ -#define PORTCFG_VP2MAP0_bm (1<<0) /* Virtual Port 2 Mapping bit 0 mask. */ -#define PORTCFG_VP2MAP0_bp 0 /* Virtual Port 2 Mapping bit 0 position. */ -#define PORTCFG_VP2MAP1_bm (1<<1) /* Virtual Port 2 Mapping bit 1 mask. */ -#define PORTCFG_VP2MAP1_bp 1 /* Virtual Port 2 Mapping bit 1 position. */ -#define PORTCFG_VP2MAP2_bm (1<<2) /* Virtual Port 2 Mapping bit 2 mask. */ -#define PORTCFG_VP2MAP2_bp 2 /* Virtual Port 2 Mapping bit 2 position. */ -#define PORTCFG_VP2MAP3_bm (1<<3) /* Virtual Port 2 Mapping bit 3 mask. */ -#define PORTCFG_VP2MAP3_bp 3 /* Virtual Port 2 Mapping bit 3 position. */ - -/* PORTCFG.CLKEVOUT bit masks and bit positions */ -#define PORTCFG_CLKOUT_gm 0x03 /* Peripheral Clock Output Port group mask. */ -#define PORTCFG_CLKOUT_gp 0 /* Peripheral Clock Output Port group position. */ -#define PORTCFG_CLKOUT0_bm (1<<0) /* Peripheral Clock Output Port bit 0 mask. */ -#define PORTCFG_CLKOUT0_bp 0 /* Peripheral Clock Output Port bit 0 position. */ -#define PORTCFG_CLKOUT1_bm (1<<1) /* Peripheral Clock Output Port bit 1 mask. */ -#define PORTCFG_CLKOUT1_bp 1 /* Peripheral Clock Output Port bit 1 position. */ - -#define PORTCFG_CLKOUTSEL_gm 0x0C /* Peripheral Clock Output Select group mask. */ -#define PORTCFG_CLKOUTSEL_gp 2 /* Peripheral Clock Output Select group position. */ -#define PORTCFG_CLKOUTSEL0_bm (1<<2) /* Peripheral Clock Output Select bit 0 mask. */ -#define PORTCFG_CLKOUTSEL0_bp 2 /* Peripheral Clock Output Select bit 0 position. */ -#define PORTCFG_CLKOUTSEL1_bm (1<<3) /* Peripheral Clock Output Select bit 1 mask. */ -#define PORTCFG_CLKOUTSEL1_bp 3 /* Peripheral Clock Output Select bit 1 position. */ - -#define PORTCFG_EVOUT_gm 0x30 /* Event Output Port group mask. */ -#define PORTCFG_EVOUT_gp 4 /* Event Output Port group position. */ -#define PORTCFG_EVOUT0_bm (1<<4) /* Event Output Port bit 0 mask. */ -#define PORTCFG_EVOUT0_bp 4 /* Event Output Port bit 0 position. */ -#define PORTCFG_EVOUT1_bm (1<<5) /* Event Output Port bit 1 mask. */ -#define PORTCFG_EVOUT1_bp 5 /* Event Output Port bit 1 position. */ - -#define PORTCFG_RTCOUT_bm 0x40 /* RTC Clock Output bit mask. */ -#define PORTCFG_RTCOUT_bp 6 /* RTC Clock Output bit position. */ - -#define PORTCFG_CLKEVPIN_bm 0x80 /* Peripheral Clock and Event Output pin Select bit mask. */ -#define PORTCFG_CLKEVPIN_bp 7 /* Peripheral Clock and Event Output pin Select bit position. */ - -/* PORTCFG.EBIOUT bit masks and bit positions */ -#define PORTCFG_EBICSOUT_gm 0x03 /* EBI Chip Select Output group mask. */ -#define PORTCFG_EBICSOUT_gp 0 /* EBI Chip Select Output group position. */ -#define PORTCFG_EBICSOUT0_bm (1<<0) /* EBI Chip Select Output bit 0 mask. */ -#define PORTCFG_EBICSOUT0_bp 0 /* EBI Chip Select Output bit 0 position. */ -#define PORTCFG_EBICSOUT1_bm (1<<1) /* EBI Chip Select Output bit 1 mask. */ -#define PORTCFG_EBICSOUT1_bp 1 /* EBI Chip Select Output bit 1 position. */ - -#define PORTCFG_EBIADROUT_gm 0x0C /* EBI Address Output group mask. */ -#define PORTCFG_EBIADROUT_gp 2 /* EBI Address Output group position. */ -#define PORTCFG_EBIADROUT0_bm (1<<2) /* EBI Address Output bit 0 mask. */ -#define PORTCFG_EBIADROUT0_bp 2 /* EBI Address Output bit 0 position. */ -#define PORTCFG_EBIADROUT1_bm (1<<3) /* EBI Address Output bit 1 mask. */ -#define PORTCFG_EBIADROUT1_bp 3 /* EBI Address Output bit 1 position. */ - -/* PORTCFG.EVOUTSEL bit masks and bit positions */ -#define PORTCFG_EVOUTSEL_gm 0x07 /* Event Output Select group mask. */ -#define PORTCFG_EVOUTSEL_gp 0 /* Event Output Select group position. */ -#define PORTCFG_EVOUTSEL0_bm (1<<0) /* Event Output Select bit 0 mask. */ -#define PORTCFG_EVOUTSEL0_bp 0 /* Event Output Select bit 0 position. */ -#define PORTCFG_EVOUTSEL1_bm (1<<1) /* Event Output Select bit 1 mask. */ -#define PORTCFG_EVOUTSEL1_bp 1 /* Event Output Select bit 1 position. */ -#define PORTCFG_EVOUTSEL2_bm (1<<2) /* Event Output Select bit 2 mask. */ -#define PORTCFG_EVOUTSEL2_bp 2 /* Event Output Select bit 2 position. */ - -/* AES - AES Module */ -/* AES.CTRL bit masks and bit positions */ -#define AES_START_bm 0x80 /* Start/Run bit mask. */ -#define AES_START_bp 7 /* Start/Run bit position. */ - -#define AES_AUTO_bm 0x40 /* Auto Start Trigger bit mask. */ -#define AES_AUTO_bp 6 /* Auto Start Trigger bit position. */ - -#define AES_RESET_bm 0x20 /* AES Software Reset bit mask. */ -#define AES_RESET_bp 5 /* AES Software Reset bit position. */ - -#define AES_DECRYPT_bm 0x10 /* Decryption / Direction bit mask. */ -#define AES_DECRYPT_bp 4 /* Decryption / Direction bit position. */ - -#define AES_XOR_bm 0x04 /* State XOR Load Enable bit mask. */ -#define AES_XOR_bp 2 /* State XOR Load Enable bit position. */ - -/* AES.STATUS bit masks and bit positions */ -#define AES_ERROR_bm 0x80 /* AES Error bit mask. */ -#define AES_ERROR_bp 7 /* AES Error bit position. */ - -#define AES_SRIF_bm 0x01 /* State Ready Interrupt Flag bit mask. */ -#define AES_SRIF_bp 0 /* State Ready Interrupt Flag bit position. */ - -/* AES.INTCTRL bit masks and bit positions */ -#define AES_INTLVL_gm 0x03 /* Interrupt level group mask. */ -#define AES_INTLVL_gp 0 /* Interrupt level group position. */ -#define AES_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */ -#define AES_INTLVL0_bp 0 /* Interrupt level bit 0 position. */ -#define AES_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */ -#define AES_INTLVL1_bp 1 /* Interrupt level bit 1 position. */ - -/* CRC - Cyclic Redundancy Checker */ -/* CRC.CTRL bit masks and bit positions */ -#define CRC_RESET_gm 0xC0 /* Reset group mask. */ -#define CRC_RESET_gp 6 /* Reset group position. */ -#define CRC_RESET0_bm (1<<6) /* Reset bit 0 mask. */ -#define CRC_RESET0_bp 6 /* Reset bit 0 position. */ -#define CRC_RESET1_bm (1<<7) /* Reset bit 1 mask. */ -#define CRC_RESET1_bp 7 /* Reset bit 1 position. */ - -#define CRC_CRC32_bm 0x20 /* CRC Mode bit mask. */ -#define CRC_CRC32_bp 5 /* CRC Mode bit position. */ - -#define CRC_SOURCE_gm 0x0F /* Input Source group mask. */ -#define CRC_SOURCE_gp 0 /* Input Source group position. */ -#define CRC_SOURCE0_bm (1<<0) /* Input Source bit 0 mask. */ -#define CRC_SOURCE0_bp 0 /* Input Source bit 0 position. */ -#define CRC_SOURCE1_bm (1<<1) /* Input Source bit 1 mask. */ -#define CRC_SOURCE1_bp 1 /* Input Source bit 1 position. */ -#define CRC_SOURCE2_bm (1<<2) /* Input Source bit 2 mask. */ -#define CRC_SOURCE2_bp 2 /* Input Source bit 2 position. */ -#define CRC_SOURCE3_bm (1<<3) /* Input Source bit 3 mask. */ -#define CRC_SOURCE3_bp 3 /* Input Source bit 3 position. */ - -/* CRC.STATUS bit masks and bit positions */ -#define CRC_ZERO_bm 0x02 /* Zero detection bit mask. */ -#define CRC_ZERO_bp 1 /* Zero detection bit position. */ - -#define CRC_BUSY_bm 0x01 /* Busy bit mask. */ -#define CRC_BUSY_bp 0 /* Busy bit position. */ - -/* DMA - DMA Controller */ -/* DMA_CH.CTRLA bit masks and bit positions */ -#define DMA_CH_ENABLE_bm 0x80 /* Channel Enable bit mask. */ -#define DMA_CH_ENABLE_bp 7 /* Channel Enable bit position. */ - -#define DMA_CH_RESET_bm 0x40 /* Channel Software Reset bit mask. */ -#define DMA_CH_RESET_bp 6 /* Channel Software Reset bit position. */ - -#define DMA_CH_REPEAT_bm 0x20 /* Channel Repeat Mode bit mask. */ -#define DMA_CH_REPEAT_bp 5 /* Channel Repeat Mode bit position. */ - -#define DMA_CH_TRFREQ_bm 0x10 /* Channel Transfer Request bit mask. */ -#define DMA_CH_TRFREQ_bp 4 /* Channel Transfer Request bit position. */ - -#define DMA_CH_SINGLE_bm 0x04 /* Channel Single Shot Data Transfer bit mask. */ -#define DMA_CH_SINGLE_bp 2 /* Channel Single Shot Data Transfer bit position. */ - -#define DMA_CH_BURSTLEN_gm 0x03 /* Channel Transfer Mode group mask. */ -#define DMA_CH_BURSTLEN_gp 0 /* Channel Transfer Mode group position. */ -#define DMA_CH_BURSTLEN0_bm (1<<0) /* Channel Transfer Mode bit 0 mask. */ -#define DMA_CH_BURSTLEN0_bp 0 /* Channel Transfer Mode bit 0 position. */ -#define DMA_CH_BURSTLEN1_bm (1<<1) /* Channel Transfer Mode bit 1 mask. */ -#define DMA_CH_BURSTLEN1_bp 1 /* Channel Transfer Mode bit 1 position. */ - -/* DMA_CH.CTRLB bit masks and bit positions */ -#define DMA_CH_CHBUSY_bm 0x80 /* Block Transfer Busy bit mask. */ -#define DMA_CH_CHBUSY_bp 7 /* Block Transfer Busy bit position. */ - -#define DMA_CH_CHPEND_bm 0x40 /* Block Transfer Pending bit mask. */ -#define DMA_CH_CHPEND_bp 6 /* Block Transfer Pending bit position. */ - -#define DMA_CH_ERRIF_bm 0x20 /* Block Transfer Error Interrupt Flag bit mask. */ -#define DMA_CH_ERRIF_bp 5 /* Block Transfer Error Interrupt Flag bit position. */ - -#define DMA_CH_TRNIF_bm 0x10 /* Transaction Complete Interrup Flag bit mask. */ -#define DMA_CH_TRNIF_bp 4 /* Transaction Complete Interrup Flag bit position. */ - -#define DMA_CH_ERRINTLVL_gm 0x0C /* Transfer Error Interrupt Level group mask. */ -#define DMA_CH_ERRINTLVL_gp 2 /* Transfer Error Interrupt Level group position. */ -#define DMA_CH_ERRINTLVL0_bm (1<<2) /* Transfer Error Interrupt Level bit 0 mask. */ -#define DMA_CH_ERRINTLVL0_bp 2 /* Transfer Error Interrupt Level bit 0 position. */ -#define DMA_CH_ERRINTLVL1_bm (1<<3) /* Transfer Error Interrupt Level bit 1 mask. */ -#define DMA_CH_ERRINTLVL1_bp 3 /* Transfer Error Interrupt Level bit 1 position. */ - -#define DMA_CH_TRNINTLVL_gm 0x03 /* Transaction Complete Interrupt Level group mask. */ -#define DMA_CH_TRNINTLVL_gp 0 /* Transaction Complete Interrupt Level group position. */ -#define DMA_CH_TRNINTLVL0_bm (1<<0) /* Transaction Complete Interrupt Level bit 0 mask. */ -#define DMA_CH_TRNINTLVL0_bp 0 /* Transaction Complete Interrupt Level bit 0 position. */ -#define DMA_CH_TRNINTLVL1_bm (1<<1) /* Transaction Complete Interrupt Level bit 1 mask. */ -#define DMA_CH_TRNINTLVL1_bp 1 /* Transaction Complete Interrupt Level bit 1 position. */ - -/* DMA_CH.ADDRCTRL bit masks and bit positions */ -#define DMA_CH_SRCRELOAD_gm 0xC0 /* Channel Source Address Reload group mask. */ -#define DMA_CH_SRCRELOAD_gp 6 /* Channel Source Address Reload group position. */ -#define DMA_CH_SRCRELOAD0_bm (1<<6) /* Channel Source Address Reload bit 0 mask. */ -#define DMA_CH_SRCRELOAD0_bp 6 /* Channel Source Address Reload bit 0 position. */ -#define DMA_CH_SRCRELOAD1_bm (1<<7) /* Channel Source Address Reload bit 1 mask. */ -#define DMA_CH_SRCRELOAD1_bp 7 /* Channel Source Address Reload bit 1 position. */ - -#define DMA_CH_SRCDIR_gm 0x30 /* Channel Source Address Mode group mask. */ -#define DMA_CH_SRCDIR_gp 4 /* Channel Source Address Mode group position. */ -#define DMA_CH_SRCDIR0_bm (1<<4) /* Channel Source Address Mode bit 0 mask. */ -#define DMA_CH_SRCDIR0_bp 4 /* Channel Source Address Mode bit 0 position. */ -#define DMA_CH_SRCDIR1_bm (1<<5) /* Channel Source Address Mode bit 1 mask. */ -#define DMA_CH_SRCDIR1_bp 5 /* Channel Source Address Mode bit 1 position. */ - -#define DMA_CH_DESTRELOAD_gm 0x0C /* Channel Destination Address Reload group mask. */ -#define DMA_CH_DESTRELOAD_gp 2 /* Channel Destination Address Reload group position. */ -#define DMA_CH_DESTRELOAD0_bm (1<<2) /* Channel Destination Address Reload bit 0 mask. */ -#define DMA_CH_DESTRELOAD0_bp 2 /* Channel Destination Address Reload bit 0 position. */ -#define DMA_CH_DESTRELOAD1_bm (1<<3) /* Channel Destination Address Reload bit 1 mask. */ -#define DMA_CH_DESTRELOAD1_bp 3 /* Channel Destination Address Reload bit 1 position. */ - -#define DMA_CH_DESTDIR_gm 0x03 /* Channel Destination Address Mode group mask. */ -#define DMA_CH_DESTDIR_gp 0 /* Channel Destination Address Mode group position. */ -#define DMA_CH_DESTDIR0_bm (1<<0) /* Channel Destination Address Mode bit 0 mask. */ -#define DMA_CH_DESTDIR0_bp 0 /* Channel Destination Address Mode bit 0 position. */ -#define DMA_CH_DESTDIR1_bm (1<<1) /* Channel Destination Address Mode bit 1 mask. */ -#define DMA_CH_DESTDIR1_bp 1 /* Channel Destination Address Mode bit 1 position. */ - -/* DMA_CH.TRIGSRC bit masks and bit positions */ -#define DMA_CH_TRIGSRC_gm 0xFF /* Channel Trigger Source group mask. */ -#define DMA_CH_TRIGSRC_gp 0 /* Channel Trigger Source group position. */ -#define DMA_CH_TRIGSRC0_bm (1<<0) /* Channel Trigger Source bit 0 mask. */ -#define DMA_CH_TRIGSRC0_bp 0 /* Channel Trigger Source bit 0 position. */ -#define DMA_CH_TRIGSRC1_bm (1<<1) /* Channel Trigger Source bit 1 mask. */ -#define DMA_CH_TRIGSRC1_bp 1 /* Channel Trigger Source bit 1 position. */ -#define DMA_CH_TRIGSRC2_bm (1<<2) /* Channel Trigger Source bit 2 mask. */ -#define DMA_CH_TRIGSRC2_bp 2 /* Channel Trigger Source bit 2 position. */ -#define DMA_CH_TRIGSRC3_bm (1<<3) /* Channel Trigger Source bit 3 mask. */ -#define DMA_CH_TRIGSRC3_bp 3 /* Channel Trigger Source bit 3 position. */ -#define DMA_CH_TRIGSRC4_bm (1<<4) /* Channel Trigger Source bit 4 mask. */ -#define DMA_CH_TRIGSRC4_bp 4 /* Channel Trigger Source bit 4 position. */ -#define DMA_CH_TRIGSRC5_bm (1<<5) /* Channel Trigger Source bit 5 mask. */ -#define DMA_CH_TRIGSRC5_bp 5 /* Channel Trigger Source bit 5 position. */ -#define DMA_CH_TRIGSRC6_bm (1<<6) /* Channel Trigger Source bit 6 mask. */ -#define DMA_CH_TRIGSRC6_bp 6 /* Channel Trigger Source bit 6 position. */ -#define DMA_CH_TRIGSRC7_bm (1<<7) /* Channel Trigger Source bit 7 mask. */ -#define DMA_CH_TRIGSRC7_bp 7 /* Channel Trigger Source bit 7 position. */ - -/* DMA.CTRL bit masks and bit positions */ -#define DMA_ENABLE_bm 0x80 /* Enable bit mask. */ -#define DMA_ENABLE_bp 7 /* Enable bit position. */ - -#define DMA_RESET_bm 0x40 /* Software Reset bit mask. */ -#define DMA_RESET_bp 6 /* Software Reset bit position. */ - -#define DMA_DBUFMODE_gm 0x0C /* Double Buffering Mode group mask. */ -#define DMA_DBUFMODE_gp 2 /* Double Buffering Mode group position. */ -#define DMA_DBUFMODE0_bm (1<<2) /* Double Buffering Mode bit 0 mask. */ -#define DMA_DBUFMODE0_bp 2 /* Double Buffering Mode bit 0 position. */ -#define DMA_DBUFMODE1_bm (1<<3) /* Double Buffering Mode bit 1 mask. */ -#define DMA_DBUFMODE1_bp 3 /* Double Buffering Mode bit 1 position. */ - -#define DMA_PRIMODE_gm 0x03 /* Channel Priority Mode group mask. */ -#define DMA_PRIMODE_gp 0 /* Channel Priority Mode group position. */ -#define DMA_PRIMODE0_bm (1<<0) /* Channel Priority Mode bit 0 mask. */ -#define DMA_PRIMODE0_bp 0 /* Channel Priority Mode bit 0 position. */ -#define DMA_PRIMODE1_bm (1<<1) /* Channel Priority Mode bit 1 mask. */ -#define DMA_PRIMODE1_bp 1 /* Channel Priority Mode bit 1 position. */ - -/* DMA.INTFLAGS bit masks and bit positions */ -#define DMA_CH3ERRIF_bm 0x80 /* Channel 3 Block Transfer Error Interrupt Flag bit mask. */ -#define DMA_CH3ERRIF_bp 7 /* Channel 3 Block Transfer Error Interrupt Flag bit position. */ - -#define DMA_CH2ERRIF_bm 0x40 /* Channel 2 Block Transfer Error Interrupt Flag bit mask. */ -#define DMA_CH2ERRIF_bp 6 /* Channel 2 Block Transfer Error Interrupt Flag bit position. */ - -#define DMA_CH1ERRIF_bm 0x20 /* Channel 1 Block Transfer Error Interrupt Flag bit mask. */ -#define DMA_CH1ERRIF_bp 5 /* Channel 1 Block Transfer Error Interrupt Flag bit position. */ - -#define DMA_CH0ERRIF_bm 0x10 /* Channel 0 Block Transfer Error Interrupt Flag bit mask. */ -#define DMA_CH0ERRIF_bp 4 /* Channel 0 Block Transfer Error Interrupt Flag bit position. */ - -#define DMA_CH3TRNIF_bm 0x08 /* Channel 3 Transaction Complete Interrupt Flag bit mask. */ -#define DMA_CH3TRNIF_bp 3 /* Channel 3 Transaction Complete Interrupt Flag bit position. */ - -#define DMA_CH2TRNIF_bm 0x04 /* Channel 2 Transaction Complete Interrupt Flag bit mask. */ -#define DMA_CH2TRNIF_bp 2 /* Channel 2 Transaction Complete Interrupt Flag bit position. */ - -#define DMA_CH1TRNIF_bm 0x02 /* Channel 1 Transaction Complete Interrupt Flag bit mask. */ -#define DMA_CH1TRNIF_bp 1 /* Channel 1 Transaction Complete Interrupt Flag bit position. */ - -#define DMA_CH0TRNIF_bm 0x01 /* Channel 0 Transaction Complete Interrupt Flag bit mask. */ -#define DMA_CH0TRNIF_bp 0 /* Channel 0 Transaction Complete Interrupt Flag bit position. */ - -/* DMA.STATUS bit masks and bit positions */ -#define DMA_CH3BUSY_bm 0x80 /* Channel 3 Block Transfer Busy bit mask. */ -#define DMA_CH3BUSY_bp 7 /* Channel 3 Block Transfer Busy bit position. */ - -#define DMA_CH2BUSY_bm 0x40 /* Channel 2 Block Transfer Busy bit mask. */ -#define DMA_CH2BUSY_bp 6 /* Channel 2 Block Transfer Busy bit position. */ - -#define DMA_CH1BUSY_bm 0x20 /* Channel 1 Block Transfer Busy bit mask. */ -#define DMA_CH1BUSY_bp 5 /* Channel 1 Block Transfer Busy bit position. */ - -#define DMA_CH0BUSY_bm 0x10 /* Channel 0 Block Transfer Busy bit mask. */ -#define DMA_CH0BUSY_bp 4 /* Channel 0 Block Transfer Busy bit position. */ - -#define DMA_CH3PEND_bm 0x08 /* Channel 3 Block Transfer Pending bit mask. */ -#define DMA_CH3PEND_bp 3 /* Channel 3 Block Transfer Pending bit position. */ - -#define DMA_CH2PEND_bm 0x04 /* Channel 2 Block Transfer Pending bit mask. */ -#define DMA_CH2PEND_bp 2 /* Channel 2 Block Transfer Pending bit position. */ - -#define DMA_CH1PEND_bm 0x02 /* Channel 1 Block Transfer Pending bit mask. */ -#define DMA_CH1PEND_bp 1 /* Channel 1 Block Transfer Pending bit position. */ - -#define DMA_CH0PEND_bm 0x01 /* Channel 0 Block Transfer Pending bit mask. */ -#define DMA_CH0PEND_bp 0 /* Channel 0 Block Transfer Pending bit position. */ - -/* EVSYS - Event System */ -/* EVSYS.CH0MUX bit masks and bit positions */ -#define EVSYS_CHMUX_gm 0xFF /* Event Channel 0 Multiplexer group mask. */ -#define EVSYS_CHMUX_gp 0 /* Event Channel 0 Multiplexer group position. */ -#define EVSYS_CHMUX0_bm (1<<0) /* Event Channel 0 Multiplexer bit 0 mask. */ -#define EVSYS_CHMUX0_bp 0 /* Event Channel 0 Multiplexer bit 0 position. */ -#define EVSYS_CHMUX1_bm (1<<1) /* Event Channel 0 Multiplexer bit 1 mask. */ -#define EVSYS_CHMUX1_bp 1 /* Event Channel 0 Multiplexer bit 1 position. */ -#define EVSYS_CHMUX2_bm (1<<2) /* Event Channel 0 Multiplexer bit 2 mask. */ -#define EVSYS_CHMUX2_bp 2 /* Event Channel 0 Multiplexer bit 2 position. */ -#define EVSYS_CHMUX3_bm (1<<3) /* Event Channel 0 Multiplexer bit 3 mask. */ -#define EVSYS_CHMUX3_bp 3 /* Event Channel 0 Multiplexer bit 3 position. */ -#define EVSYS_CHMUX4_bm (1<<4) /* Event Channel 0 Multiplexer bit 4 mask. */ -#define EVSYS_CHMUX4_bp 4 /* Event Channel 0 Multiplexer bit 4 position. */ -#define EVSYS_CHMUX5_bm (1<<5) /* Event Channel 0 Multiplexer bit 5 mask. */ -#define EVSYS_CHMUX5_bp 5 /* Event Channel 0 Multiplexer bit 5 position. */ -#define EVSYS_CHMUX6_bm (1<<6) /* Event Channel 0 Multiplexer bit 6 mask. */ -#define EVSYS_CHMUX6_bp 6 /* Event Channel 0 Multiplexer bit 6 position. */ -#define EVSYS_CHMUX7_bm (1<<7) /* Event Channel 0 Multiplexer bit 7 mask. */ -#define EVSYS_CHMUX7_bp 7 /* Event Channel 0 Multiplexer bit 7 position. */ - -/* EVSYS.CH1MUX bit masks and bit positions */ -/* EVSYS_CHMUX Predefined. */ -/* EVSYS_CHMUX Predefined. */ - -/* EVSYS.CH2MUX bit masks and bit positions */ -/* EVSYS_CHMUX Predefined. */ -/* EVSYS_CHMUX Predefined. */ - -/* EVSYS.CH3MUX bit masks and bit positions */ -/* EVSYS_CHMUX Predefined. */ -/* EVSYS_CHMUX Predefined. */ - -/* EVSYS.CH4MUX bit masks and bit positions */ -/* EVSYS_CHMUX Predefined. */ -/* EVSYS_CHMUX Predefined. */ - -/* EVSYS.CH5MUX bit masks and bit positions */ -/* EVSYS_CHMUX Predefined. */ -/* EVSYS_CHMUX Predefined. */ - -/* EVSYS.CH6MUX bit masks and bit positions */ -/* EVSYS_CHMUX Predefined. */ -/* EVSYS_CHMUX Predefined. */ - -/* EVSYS.CH7MUX bit masks and bit positions */ -/* EVSYS_CHMUX Predefined. */ -/* EVSYS_CHMUX Predefined. */ - -/* EVSYS.CH0CTRL bit masks and bit positions */ -#define EVSYS_QDIRM_gm 0x60 /* Quadrature Decoder Index Recognition Mode group mask. */ -#define EVSYS_QDIRM_gp 5 /* Quadrature Decoder Index Recognition Mode group position. */ -#define EVSYS_QDIRM0_bm (1<<5) /* Quadrature Decoder Index Recognition Mode bit 0 mask. */ -#define EVSYS_QDIRM0_bp 5 /* Quadrature Decoder Index Recognition Mode bit 0 position. */ -#define EVSYS_QDIRM1_bm (1<<6) /* Quadrature Decoder Index Recognition Mode bit 1 mask. */ -#define EVSYS_QDIRM1_bp 6 /* Quadrature Decoder Index Recognition Mode bit 1 position. */ - -#define EVSYS_QDIEN_bm 0x10 /* Quadrature Decoder Index Enable bit mask. */ -#define EVSYS_QDIEN_bp 4 /* Quadrature Decoder Index Enable bit position. */ - -#define EVSYS_QDEN_bm 0x08 /* Quadrature Decoder Enable bit mask. */ -#define EVSYS_QDEN_bp 3 /* Quadrature Decoder Enable bit position. */ - -#define EVSYS_DIGFILT_gm 0x07 /* Digital Filter group mask. */ -#define EVSYS_DIGFILT_gp 0 /* Digital Filter group position. */ -#define EVSYS_DIGFILT0_bm (1<<0) /* Digital Filter bit 0 mask. */ -#define EVSYS_DIGFILT0_bp 0 /* Digital Filter bit 0 position. */ -#define EVSYS_DIGFILT1_bm (1<<1) /* Digital Filter bit 1 mask. */ -#define EVSYS_DIGFILT1_bp 1 /* Digital Filter bit 1 position. */ -#define EVSYS_DIGFILT2_bm (1<<2) /* Digital Filter bit 2 mask. */ -#define EVSYS_DIGFILT2_bp 2 /* Digital Filter bit 2 position. */ - -/* EVSYS.CH1CTRL bit masks and bit positions */ -/* EVSYS_DIGFILT Predefined. */ -/* EVSYS_DIGFILT Predefined. */ - -/* EVSYS.CH2CTRL bit masks and bit positions */ -/* EVSYS_QDIRM Predefined. */ -/* EVSYS_QDIRM Predefined. */ - -/* EVSYS_QDIEN Predefined. */ -/* EVSYS_QDIEN Predefined. */ - -/* EVSYS_QDEN Predefined. */ -/* EVSYS_QDEN Predefined. */ - -/* EVSYS_DIGFILT Predefined. */ -/* EVSYS_DIGFILT Predefined. */ - -/* EVSYS.CH3CTRL bit masks and bit positions */ -/* EVSYS_DIGFILT Predefined. */ -/* EVSYS_DIGFILT Predefined. */ - -/* EVSYS.CH4CTRL bit masks and bit positions */ -/* EVSYS_QDIRM Predefined. */ -/* EVSYS_QDIRM Predefined. */ - -/* EVSYS_QDIEN Predefined. */ -/* EVSYS_QDIEN Predefined. */ - -/* EVSYS_QDEN Predefined. */ -/* EVSYS_QDEN Predefined. */ - -/* EVSYS_DIGFILT Predefined. */ -/* EVSYS_DIGFILT Predefined. */ - -/* EVSYS.CH5CTRL bit masks and bit positions */ -/* EVSYS_DIGFILT Predefined. */ -/* EVSYS_DIGFILT Predefined. */ - -/* EVSYS.CH6CTRL bit masks and bit positions */ -/* EVSYS_DIGFILT Predefined. */ -/* EVSYS_DIGFILT Predefined. */ - -/* EVSYS.CH7CTRL bit masks and bit positions */ -/* EVSYS_DIGFILT Predefined. */ -/* EVSYS_DIGFILT Predefined. */ - -/* NVM - Non Volatile Memory Controller */ -/* NVM.CMD bit masks and bit positions */ -#define NVM_CMD_gm 0x7F /* Command group mask. */ -#define NVM_CMD_gp 0 /* Command group position. */ -#define NVM_CMD0_bm (1<<0) /* Command bit 0 mask. */ -#define NVM_CMD0_bp 0 /* Command bit 0 position. */ -#define NVM_CMD1_bm (1<<1) /* Command bit 1 mask. */ -#define NVM_CMD1_bp 1 /* Command bit 1 position. */ -#define NVM_CMD2_bm (1<<2) /* Command bit 2 mask. */ -#define NVM_CMD2_bp 2 /* Command bit 2 position. */ -#define NVM_CMD3_bm (1<<3) /* Command bit 3 mask. */ -#define NVM_CMD3_bp 3 /* Command bit 3 position. */ -#define NVM_CMD4_bm (1<<4) /* Command bit 4 mask. */ -#define NVM_CMD4_bp 4 /* Command bit 4 position. */ -#define NVM_CMD5_bm (1<<5) /* Command bit 5 mask. */ -#define NVM_CMD5_bp 5 /* Command bit 5 position. */ -#define NVM_CMD6_bm (1<<6) /* Command bit 6 mask. */ -#define NVM_CMD6_bp 6 /* Command bit 6 position. */ - -/* NVM.CTRLA bit masks and bit positions */ -#define NVM_CMDEX_bm 0x01 /* Command Execute bit mask. */ -#define NVM_CMDEX_bp 0 /* Command Execute bit position. */ - -/* NVM.CTRLB bit masks and bit positions */ -#define NVM_EEMAPEN_bm 0x08 /* EEPROM Mapping Enable bit mask. */ -#define NVM_EEMAPEN_bp 3 /* EEPROM Mapping Enable bit position. */ - -#define NVM_FPRM_bm 0x04 /* Flash Power Reduction Enable bit mask. */ -#define NVM_FPRM_bp 2 /* Flash Power Reduction Enable bit position. */ - -#define NVM_EPRM_bm 0x02 /* EEPROM Power Reduction Enable bit mask. */ -#define NVM_EPRM_bp 1 /* EEPROM Power Reduction Enable bit position. */ - -#define NVM_SPMLOCK_bm 0x01 /* SPM Lock bit mask. */ -#define NVM_SPMLOCK_bp 0 /* SPM Lock bit position. */ - -/* NVM.INTCTRL bit masks and bit positions */ -#define NVM_SPMLVL_gm 0x0C /* SPM Interrupt Level group mask. */ -#define NVM_SPMLVL_gp 2 /* SPM Interrupt Level group position. */ -#define NVM_SPMLVL0_bm (1<<2) /* SPM Interrupt Level bit 0 mask. */ -#define NVM_SPMLVL0_bp 2 /* SPM Interrupt Level bit 0 position. */ -#define NVM_SPMLVL1_bm (1<<3) /* SPM Interrupt Level bit 1 mask. */ -#define NVM_SPMLVL1_bp 3 /* SPM Interrupt Level bit 1 position. */ - -#define NVM_EELVL_gm 0x03 /* EEPROM Interrupt Level group mask. */ -#define NVM_EELVL_gp 0 /* EEPROM Interrupt Level group position. */ -#define NVM_EELVL0_bm (1<<0) /* EEPROM Interrupt Level bit 0 mask. */ -#define NVM_EELVL0_bp 0 /* EEPROM Interrupt Level bit 0 position. */ -#define NVM_EELVL1_bm (1<<1) /* EEPROM Interrupt Level bit 1 mask. */ -#define NVM_EELVL1_bp 1 /* EEPROM Interrupt Level bit 1 position. */ - -/* NVM.STATUS bit masks and bit positions */ -#define NVM_NVMBUSY_bm 0x80 /* Non-volatile Memory Busy bit mask. */ -#define NVM_NVMBUSY_bp 7 /* Non-volatile Memory Busy bit position. */ - -#define NVM_FBUSY_bm 0x40 /* Flash Memory Busy bit mask. */ -#define NVM_FBUSY_bp 6 /* Flash Memory Busy bit position. */ - -#define NVM_EELOAD_bm 0x02 /* EEPROM Page Buffer Active Loading bit mask. */ -#define NVM_EELOAD_bp 1 /* EEPROM Page Buffer Active Loading bit position. */ - -#define NVM_FLOAD_bm 0x01 /* Flash Page Buffer Active Loading bit mask. */ -#define NVM_FLOAD_bp 0 /* Flash Page Buffer Active Loading bit position. */ - -/* NVM.LOCKBITS bit masks and bit positions */ -#define NVM_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ -#define NVM_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ -#define NVM_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ -#define NVM_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ -#define NVM_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ -#define NVM_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ - -#define NVM_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ -#define NVM_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ -#define NVM_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ -#define NVM_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ -#define NVM_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ -#define NVM_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ - -#define NVM_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ -#define NVM_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ -#define NVM_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ -#define NVM_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ -#define NVM_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ -#define NVM_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ - -#define NVM_LB_gm 0x03 /* Lock Bits group mask. */ -#define NVM_LB_gp 0 /* Lock Bits group position. */ -#define NVM_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ -#define NVM_LB0_bp 0 /* Lock Bits bit 0 position. */ -#define NVM_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ -#define NVM_LB1_bp 1 /* Lock Bits bit 1 position. */ - -/* ADC - Analog/Digital Converter */ -/* ADC_CH.CTRL bit masks and bit positions */ -#define ADC_CH_START_bm 0x80 /* Channel Start Conversion bit mask. */ -#define ADC_CH_START_bp 7 /* Channel Start Conversion bit position. */ - -#define ADC_CH_GAIN_gm 0x1C /* Gain Factor group mask. */ -#define ADC_CH_GAIN_gp 2 /* Gain Factor group position. */ -#define ADC_CH_GAIN0_bm (1<<2) /* Gain Factor bit 0 mask. */ -#define ADC_CH_GAIN0_bp 2 /* Gain Factor bit 0 position. */ -#define ADC_CH_GAIN1_bm (1<<3) /* Gain Factor bit 1 mask. */ -#define ADC_CH_GAIN1_bp 3 /* Gain Factor bit 1 position. */ -#define ADC_CH_GAIN2_bm (1<<4) /* Gain Factor bit 2 mask. */ -#define ADC_CH_GAIN2_bp 4 /* Gain Factor bit 2 position. */ - -#define ADC_CH_INPUTMODE_gm 0x03 /* Input Mode Select group mask. */ -#define ADC_CH_INPUTMODE_gp 0 /* Input Mode Select group position. */ -#define ADC_CH_INPUTMODE0_bm (1<<0) /* Input Mode Select bit 0 mask. */ -#define ADC_CH_INPUTMODE0_bp 0 /* Input Mode Select bit 0 position. */ -#define ADC_CH_INPUTMODE1_bm (1<<1) /* Input Mode Select bit 1 mask. */ -#define ADC_CH_INPUTMODE1_bp 1 /* Input Mode Select bit 1 position. */ - -/* ADC_CH.MUXCTRL bit masks and bit positions */ -#define ADC_CH_MUXPOS_gm 0x78 /* MUX selection on Positive ADC input group mask. */ -#define ADC_CH_MUXPOS_gp 3 /* MUX selection on Positive ADC input group position. */ -#define ADC_CH_MUXPOS0_bm (1<<3) /* MUX selection on Positive ADC input bit 0 mask. */ -#define ADC_CH_MUXPOS0_bp 3 /* MUX selection on Positive ADC input bit 0 position. */ -#define ADC_CH_MUXPOS1_bm (1<<4) /* MUX selection on Positive ADC input bit 1 mask. */ -#define ADC_CH_MUXPOS1_bp 4 /* MUX selection on Positive ADC input bit 1 position. */ -#define ADC_CH_MUXPOS2_bm (1<<5) /* MUX selection on Positive ADC input bit 2 mask. */ -#define ADC_CH_MUXPOS2_bp 5 /* MUX selection on Positive ADC input bit 2 position. */ -#define ADC_CH_MUXPOS3_bm (1<<6) /* MUX selection on Positive ADC input bit 3 mask. */ -#define ADC_CH_MUXPOS3_bp 6 /* MUX selection on Positive ADC input bit 3 position. */ - -#define ADC_CH_MUXINT_gm 0x78 /* MUX selection on Internal ADC input group mask. */ -#define ADC_CH_MUXINT_gp 3 /* MUX selection on Internal ADC input group position. */ -#define ADC_CH_MUXINT0_bm (1<<3) /* MUX selection on Internal ADC input bit 0 mask. */ -#define ADC_CH_MUXINT0_bp 3 /* MUX selection on Internal ADC input bit 0 position. */ -#define ADC_CH_MUXINT1_bm (1<<4) /* MUX selection on Internal ADC input bit 1 mask. */ -#define ADC_CH_MUXINT1_bp 4 /* MUX selection on Internal ADC input bit 1 position. */ -#define ADC_CH_MUXINT2_bm (1<<5) /* MUX selection on Internal ADC input bit 2 mask. */ -#define ADC_CH_MUXINT2_bp 5 /* MUX selection on Internal ADC input bit 2 position. */ -#define ADC_CH_MUXINT3_bm (1<<6) /* MUX selection on Internal ADC input bit 3 mask. */ -#define ADC_CH_MUXINT3_bp 6 /* MUX selection on Internal ADC input bit 3 position. */ - -#define ADC_CH_MUXNEG_gm 0x07 /* MUX selection on Negative ADC input group mask. */ -#define ADC_CH_MUXNEG_gp 0 /* MUX selection on Negative ADC input group position. */ -#define ADC_CH_MUXNEG0_bm (1<<0) /* MUX selection on Negative ADC input bit 0 mask. */ -#define ADC_CH_MUXNEG0_bp 0 /* MUX selection on Negative ADC input bit 0 position. */ -#define ADC_CH_MUXNEG1_bm (1<<1) /* MUX selection on Negative ADC input bit 1 mask. */ -#define ADC_CH_MUXNEG1_bp 1 /* MUX selection on Negative ADC input bit 1 position. */ -#define ADC_CH_MUXNEG2_bm (1<<2) /* MUX selection on Negative ADC input bit 2 mask. */ -#define ADC_CH_MUXNEG2_bp 2 /* MUX selection on Negative ADC input bit 2 position. */ - -/* ADC_CH.INTCTRL bit masks and bit positions */ -#define ADC_CH_INTMODE_gm 0x0C /* Interrupt Mode group mask. */ -#define ADC_CH_INTMODE_gp 2 /* Interrupt Mode group position. */ -#define ADC_CH_INTMODE0_bm (1<<2) /* Interrupt Mode bit 0 mask. */ -#define ADC_CH_INTMODE0_bp 2 /* Interrupt Mode bit 0 position. */ -#define ADC_CH_INTMODE1_bm (1<<3) /* Interrupt Mode bit 1 mask. */ -#define ADC_CH_INTMODE1_bp 3 /* Interrupt Mode bit 1 position. */ - -#define ADC_CH_INTLVL_gm 0x03 /* Interrupt Level group mask. */ -#define ADC_CH_INTLVL_gp 0 /* Interrupt Level group position. */ -#define ADC_CH_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */ -#define ADC_CH_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */ -#define ADC_CH_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ -#define ADC_CH_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */ - -/* ADC_CH.INTFLAGS bit masks and bit positions */ -#define ADC_CH_CHIF_bm 0x01 /* Channel Interrupt Flag bit mask. */ -#define ADC_CH_CHIF_bp 0 /* Channel Interrupt Flag bit position. */ - -/* ADC_CH.SCAN bit masks and bit positions */ -#define ADC_CH_OFFSET_gm 0xF0 /* Positive MUX setting offset group mask. */ -#define ADC_CH_OFFSET_gp 4 /* Positive MUX setting offset group position. */ -#define ADC_CH_OFFSET0_bm (1<<4) /* Positive MUX setting offset bit 0 mask. */ -#define ADC_CH_OFFSET0_bp 4 /* Positive MUX setting offset bit 0 position. */ -#define ADC_CH_OFFSET1_bm (1<<5) /* Positive MUX setting offset bit 1 mask. */ -#define ADC_CH_OFFSET1_bp 5 /* Positive MUX setting offset bit 1 position. */ -#define ADC_CH_OFFSET2_bm (1<<6) /* Positive MUX setting offset bit 2 mask. */ -#define ADC_CH_OFFSET2_bp 6 /* Positive MUX setting offset bit 2 position. */ -#define ADC_CH_OFFSET3_bm (1<<7) /* Positive MUX setting offset bit 3 mask. */ -#define ADC_CH_OFFSET3_bp 7 /* Positive MUX setting offset bit 3 position. */ - -#define ADC_CH_SCANNUM_gm 0x0F /* Number of Channels included in scan group mask. */ -#define ADC_CH_SCANNUM_gp 0 /* Number of Channels included in scan group position. */ -#define ADC_CH_SCANNUM0_bm (1<<0) /* Number of Channels included in scan bit 0 mask. */ -#define ADC_CH_SCANNUM0_bp 0 /* Number of Channels included in scan bit 0 position. */ -#define ADC_CH_SCANNUM1_bm (1<<1) /* Number of Channels included in scan bit 1 mask. */ -#define ADC_CH_SCANNUM1_bp 1 /* Number of Channels included in scan bit 1 position. */ -#define ADC_CH_SCANNUM2_bm (1<<2) /* Number of Channels included in scan bit 2 mask. */ -#define ADC_CH_SCANNUM2_bp 2 /* Number of Channels included in scan bit 2 position. */ -#define ADC_CH_SCANNUM3_bm (1<<3) /* Number of Channels included in scan bit 3 mask. */ -#define ADC_CH_SCANNUM3_bp 3 /* Number of Channels included in scan bit 3 position. */ - -/* ADC.CTRLA bit masks and bit positions */ -#define ADC_DMASEL_gm 0xC0 /* DMA Selection group mask. */ -#define ADC_DMASEL_gp 6 /* DMA Selection group position. */ -#define ADC_DMASEL0_bm (1<<6) /* DMA Selection bit 0 mask. */ -#define ADC_DMASEL0_bp 6 /* DMA Selection bit 0 position. */ -#define ADC_DMASEL1_bm (1<<7) /* DMA Selection bit 1 mask. */ -#define ADC_DMASEL1_bp 7 /* DMA Selection bit 1 position. */ - -#define ADC_CH3START_bm 0x20 /* Channel 3 Start Conversion bit mask. */ -#define ADC_CH3START_bp 5 /* Channel 3 Start Conversion bit position. */ - -#define ADC_CH2START_bm 0x10 /* Channel 2 Start Conversion bit mask. */ -#define ADC_CH2START_bp 4 /* Channel 2 Start Conversion bit position. */ - -#define ADC_CH1START_bm 0x08 /* Channel 1 Start Conversion bit mask. */ -#define ADC_CH1START_bp 3 /* Channel 1 Start Conversion bit position. */ - -#define ADC_CH0START_bm 0x04 /* Channel 0 Start Conversion bit mask. */ -#define ADC_CH0START_bp 2 /* Channel 0 Start Conversion bit position. */ - -#define ADC_FLUSH_bm 0x02 /* Flush Pipeline bit mask. */ -#define ADC_FLUSH_bp 1 /* Flush Pipeline bit position. */ - -#define ADC_ENABLE_bm 0x01 /* Enable ADC bit mask. */ -#define ADC_ENABLE_bp 0 /* Enable ADC bit position. */ - -/* ADC.CTRLB bit masks and bit positions */ -#define ADC_IMPMODE_bm 0x80 /* Gain Stage Impedance Mode bit mask. */ -#define ADC_IMPMODE_bp 7 /* Gain Stage Impedance Mode bit position. */ - -#define ADC_CURRLIMIT_gm 0x60 /* Current Limitation group mask. */ -#define ADC_CURRLIMIT_gp 5 /* Current Limitation group position. */ -#define ADC_CURRLIMIT0_bm (1<<5) /* Current Limitation bit 0 mask. */ -#define ADC_CURRLIMIT0_bp 5 /* Current Limitation bit 0 position. */ -#define ADC_CURRLIMIT1_bm (1<<6) /* Current Limitation bit 1 mask. */ -#define ADC_CURRLIMIT1_bp 6 /* Current Limitation bit 1 position. */ - -#define ADC_CONMODE_bm 0x10 /* Conversion Mode bit mask. */ -#define ADC_CONMODE_bp 4 /* Conversion Mode bit position. */ - -#define ADC_FREERUN_bm 0x08 /* Free Running Mode Enable bit mask. */ -#define ADC_FREERUN_bp 3 /* Free Running Mode Enable bit position. */ - -#define ADC_RESOLUTION_gm 0x06 /* Result Resolution group mask. */ -#define ADC_RESOLUTION_gp 1 /* Result Resolution group position. */ -#define ADC_RESOLUTION0_bm (1<<1) /* Result Resolution bit 0 mask. */ -#define ADC_RESOLUTION0_bp 1 /* Result Resolution bit 0 position. */ -#define ADC_RESOLUTION1_bm (1<<2) /* Result Resolution bit 1 mask. */ -#define ADC_RESOLUTION1_bp 2 /* Result Resolution bit 1 position. */ - -/* ADC.REFCTRL bit masks and bit positions */ -#define ADC_REFSEL_gm 0x70 /* Reference Selection group mask. */ -#define ADC_REFSEL_gp 4 /* Reference Selection group position. */ -#define ADC_REFSEL0_bm (1<<4) /* Reference Selection bit 0 mask. */ -#define ADC_REFSEL0_bp 4 /* Reference Selection bit 0 position. */ -#define ADC_REFSEL1_bm (1<<5) /* Reference Selection bit 1 mask. */ -#define ADC_REFSEL1_bp 5 /* Reference Selection bit 1 position. */ -#define ADC_REFSEL2_bm (1<<6) /* Reference Selection bit 2 mask. */ -#define ADC_REFSEL2_bp 6 /* Reference Selection bit 2 position. */ - -#define ADC_BANDGAP_bm 0x02 /* Bandgap enable bit mask. */ -#define ADC_BANDGAP_bp 1 /* Bandgap enable bit position. */ - -#define ADC_TEMPREF_bm 0x01 /* Temperature Reference Enable bit mask. */ -#define ADC_TEMPREF_bp 0 /* Temperature Reference Enable bit position. */ - -/* ADC.EVCTRL bit masks and bit positions */ -#define ADC_SWEEP_gm 0xC0 /* Channel Sweep Selection group mask. */ -#define ADC_SWEEP_gp 6 /* Channel Sweep Selection group position. */ -#define ADC_SWEEP0_bm (1<<6) /* Channel Sweep Selection bit 0 mask. */ -#define ADC_SWEEP0_bp 6 /* Channel Sweep Selection bit 0 position. */ -#define ADC_SWEEP1_bm (1<<7) /* Channel Sweep Selection bit 1 mask. */ -#define ADC_SWEEP1_bp 7 /* Channel Sweep Selection bit 1 position. */ - -#define ADC_EVSEL_gm 0x38 /* Event Input Select group mask. */ -#define ADC_EVSEL_gp 3 /* Event Input Select group position. */ -#define ADC_EVSEL0_bm (1<<3) /* Event Input Select bit 0 mask. */ -#define ADC_EVSEL0_bp 3 /* Event Input Select bit 0 position. */ -#define ADC_EVSEL1_bm (1<<4) /* Event Input Select bit 1 mask. */ -#define ADC_EVSEL1_bp 4 /* Event Input Select bit 1 position. */ -#define ADC_EVSEL2_bm (1<<5) /* Event Input Select bit 2 mask. */ -#define ADC_EVSEL2_bp 5 /* Event Input Select bit 2 position. */ - -#define ADC_EVACT_gm 0x07 /* Event Action Select group mask. */ -#define ADC_EVACT_gp 0 /* Event Action Select group position. */ -#define ADC_EVACT0_bm (1<<0) /* Event Action Select bit 0 mask. */ -#define ADC_EVACT0_bp 0 /* Event Action Select bit 0 position. */ -#define ADC_EVACT1_bm (1<<1) /* Event Action Select bit 1 mask. */ -#define ADC_EVACT1_bp 1 /* Event Action Select bit 1 position. */ -#define ADC_EVACT2_bm (1<<2) /* Event Action Select bit 2 mask. */ -#define ADC_EVACT2_bp 2 /* Event Action Select bit 2 position. */ - -/* ADC.PRESCALER bit masks and bit positions */ -#define ADC_PRESCALER_gm 0x07 /* Clock Prescaler Selection group mask. */ -#define ADC_PRESCALER_gp 0 /* Clock Prescaler Selection group position. */ -#define ADC_PRESCALER0_bm (1<<0) /* Clock Prescaler Selection bit 0 mask. */ -#define ADC_PRESCALER0_bp 0 /* Clock Prescaler Selection bit 0 position. */ -#define ADC_PRESCALER1_bm (1<<1) /* Clock Prescaler Selection bit 1 mask. */ -#define ADC_PRESCALER1_bp 1 /* Clock Prescaler Selection bit 1 position. */ -#define ADC_PRESCALER2_bm (1<<2) /* Clock Prescaler Selection bit 2 mask. */ -#define ADC_PRESCALER2_bp 2 /* Clock Prescaler Selection bit 2 position. */ - -/* ADC.INTFLAGS bit masks and bit positions */ -#define ADC_CH3IF_bm 0x08 /* Channel 3 Interrupt Flag bit mask. */ -#define ADC_CH3IF_bp 3 /* Channel 3 Interrupt Flag bit position. */ - -#define ADC_CH2IF_bm 0x04 /* Channel 2 Interrupt Flag bit mask. */ -#define ADC_CH2IF_bp 2 /* Channel 2 Interrupt Flag bit position. */ - -#define ADC_CH1IF_bm 0x02 /* Channel 1 Interrupt Flag bit mask. */ -#define ADC_CH1IF_bp 1 /* Channel 1 Interrupt Flag bit position. */ - -#define ADC_CH0IF_bm 0x01 /* Channel 0 Interrupt Flag bit mask. */ -#define ADC_CH0IF_bp 0 /* Channel 0 Interrupt Flag bit position. */ - -/* DAC - Digital/Analog Converter */ -/* DAC.CTRLA bit masks and bit positions */ -#define DAC_IDOEN_bm 0x10 /* Internal Output Enable bit mask. */ -#define DAC_IDOEN_bp 4 /* Internal Output Enable bit position. */ - -#define DAC_CH1EN_bm 0x08 /* Channel 1 Output Enable bit mask. */ -#define DAC_CH1EN_bp 3 /* Channel 1 Output Enable bit position. */ - -#define DAC_CH0EN_bm 0x04 /* Channel 0 Output Enable bit mask. */ -#define DAC_CH0EN_bp 2 /* Channel 0 Output Enable bit position. */ - -#define DAC_LPMODE_bm 0x02 /* Low Power Mode bit mask. */ -#define DAC_LPMODE_bp 1 /* Low Power Mode bit position. */ - -#define DAC_ENABLE_bm 0x01 /* Enable bit mask. */ -#define DAC_ENABLE_bp 0 /* Enable bit position. */ - -/* DAC.CTRLB bit masks and bit positions */ -#define DAC_CHSEL_gm 0x60 /* Channel Select group mask. */ -#define DAC_CHSEL_gp 5 /* Channel Select group position. */ -#define DAC_CHSEL0_bm (1<<5) /* Channel Select bit 0 mask. */ -#define DAC_CHSEL0_bp 5 /* Channel Select bit 0 position. */ -#define DAC_CHSEL1_bm (1<<6) /* Channel Select bit 1 mask. */ -#define DAC_CHSEL1_bp 6 /* Channel Select bit 1 position. */ - -#define DAC_CH1TRIG_bm 0x02 /* Channel 1 Event Trig Enable bit mask. */ -#define DAC_CH1TRIG_bp 1 /* Channel 1 Event Trig Enable bit position. */ - -#define DAC_CH0TRIG_bm 0x01 /* Channel 0 Event Trig Enable bit mask. */ -#define DAC_CH0TRIG_bp 0 /* Channel 0 Event Trig Enable bit position. */ - -/* DAC.CTRLC bit masks and bit positions */ -#define DAC_REFSEL_gm 0x18 /* Reference Select group mask. */ -#define DAC_REFSEL_gp 3 /* Reference Select group position. */ -#define DAC_REFSEL0_bm (1<<3) /* Reference Select bit 0 mask. */ -#define DAC_REFSEL0_bp 3 /* Reference Select bit 0 position. */ -#define DAC_REFSEL1_bm (1<<4) /* Reference Select bit 1 mask. */ -#define DAC_REFSEL1_bp 4 /* Reference Select bit 1 position. */ - -#define DAC_LEFTADJ_bm 0x01 /* Left-adjust Result bit mask. */ -#define DAC_LEFTADJ_bp 0 /* Left-adjust Result bit position. */ - -/* DAC.EVCTRL bit masks and bit positions */ -#define DAC_EVSPLIT_bm 0x08 /* Separate Event Channel Input for Channel 1 bit mask. */ -#define DAC_EVSPLIT_bp 3 /* Separate Event Channel Input for Channel 1 bit position. */ - -#define DAC_EVSEL_gm 0x07 /* Event Input Selection group mask. */ -#define DAC_EVSEL_gp 0 /* Event Input Selection group position. */ -#define DAC_EVSEL0_bm (1<<0) /* Event Input Selection bit 0 mask. */ -#define DAC_EVSEL0_bp 0 /* Event Input Selection bit 0 position. */ -#define DAC_EVSEL1_bm (1<<1) /* Event Input Selection bit 1 mask. */ -#define DAC_EVSEL1_bp 1 /* Event Input Selection bit 1 position. */ -#define DAC_EVSEL2_bm (1<<2) /* Event Input Selection bit 2 mask. */ -#define DAC_EVSEL2_bp 2 /* Event Input Selection bit 2 position. */ - -/* DAC.STATUS bit masks and bit positions */ -#define DAC_CH1DRE_bm 0x02 /* Channel 1 Data Register Empty bit mask. */ -#define DAC_CH1DRE_bp 1 /* Channel 1 Data Register Empty bit position. */ - -#define DAC_CH0DRE_bm 0x01 /* Channel 0 Data Register Empty bit mask. */ -#define DAC_CH0DRE_bp 0 /* Channel 0 Data Register Empty bit position. */ - -/* DAC.CH0GAINCAL bit masks and bit positions */ -#define DAC_CH0GAINCAL_gm 0x7F /* Gain Calibration group mask. */ -#define DAC_CH0GAINCAL_gp 0 /* Gain Calibration group position. */ -#define DAC_CH0GAINCAL0_bm (1<<0) /* Gain Calibration bit 0 mask. */ -#define DAC_CH0GAINCAL0_bp 0 /* Gain Calibration bit 0 position. */ -#define DAC_CH0GAINCAL1_bm (1<<1) /* Gain Calibration bit 1 mask. */ -#define DAC_CH0GAINCAL1_bp 1 /* Gain Calibration bit 1 position. */ -#define DAC_CH0GAINCAL2_bm (1<<2) /* Gain Calibration bit 2 mask. */ -#define DAC_CH0GAINCAL2_bp 2 /* Gain Calibration bit 2 position. */ -#define DAC_CH0GAINCAL3_bm (1<<3) /* Gain Calibration bit 3 mask. */ -#define DAC_CH0GAINCAL3_bp 3 /* Gain Calibration bit 3 position. */ -#define DAC_CH0GAINCAL4_bm (1<<4) /* Gain Calibration bit 4 mask. */ -#define DAC_CH0GAINCAL4_bp 4 /* Gain Calibration bit 4 position. */ -#define DAC_CH0GAINCAL5_bm (1<<5) /* Gain Calibration bit 5 mask. */ -#define DAC_CH0GAINCAL5_bp 5 /* Gain Calibration bit 5 position. */ -#define DAC_CH0GAINCAL6_bm (1<<6) /* Gain Calibration bit 6 mask. */ -#define DAC_CH0GAINCAL6_bp 6 /* Gain Calibration bit 6 position. */ - -/* DAC.CH0OFFSETCAL bit masks and bit positions */ -#define DAC_CH0OFFSETCAL_gm 0x7F /* Offset Calibration group mask. */ -#define DAC_CH0OFFSETCAL_gp 0 /* Offset Calibration group position. */ -#define DAC_CH0OFFSETCAL0_bm (1<<0) /* Offset Calibration bit 0 mask. */ -#define DAC_CH0OFFSETCAL0_bp 0 /* Offset Calibration bit 0 position. */ -#define DAC_CH0OFFSETCAL1_bm (1<<1) /* Offset Calibration bit 1 mask. */ -#define DAC_CH0OFFSETCAL1_bp 1 /* Offset Calibration bit 1 position. */ -#define DAC_CH0OFFSETCAL2_bm (1<<2) /* Offset Calibration bit 2 mask. */ -#define DAC_CH0OFFSETCAL2_bp 2 /* Offset Calibration bit 2 position. */ -#define DAC_CH0OFFSETCAL3_bm (1<<3) /* Offset Calibration bit 3 mask. */ -#define DAC_CH0OFFSETCAL3_bp 3 /* Offset Calibration bit 3 position. */ -#define DAC_CH0OFFSETCAL4_bm (1<<4) /* Offset Calibration bit 4 mask. */ -#define DAC_CH0OFFSETCAL4_bp 4 /* Offset Calibration bit 4 position. */ -#define DAC_CH0OFFSETCAL5_bm (1<<5) /* Offset Calibration bit 5 mask. */ -#define DAC_CH0OFFSETCAL5_bp 5 /* Offset Calibration bit 5 position. */ -#define DAC_CH0OFFSETCAL6_bm (1<<6) /* Offset Calibration bit 6 mask. */ -#define DAC_CH0OFFSETCAL6_bp 6 /* Offset Calibration bit 6 position. */ - -/* DAC.CH1GAINCAL bit masks and bit positions */ -#define DAC_CH1GAINCAL_gm 0x7F /* Gain Calibration group mask. */ -#define DAC_CH1GAINCAL_gp 0 /* Gain Calibration group position. */ -#define DAC_CH1GAINCAL0_bm (1<<0) /* Gain Calibration bit 0 mask. */ -#define DAC_CH1GAINCAL0_bp 0 /* Gain Calibration bit 0 position. */ -#define DAC_CH1GAINCAL1_bm (1<<1) /* Gain Calibration bit 1 mask. */ -#define DAC_CH1GAINCAL1_bp 1 /* Gain Calibration bit 1 position. */ -#define DAC_CH1GAINCAL2_bm (1<<2) /* Gain Calibration bit 2 mask. */ -#define DAC_CH1GAINCAL2_bp 2 /* Gain Calibration bit 2 position. */ -#define DAC_CH1GAINCAL3_bm (1<<3) /* Gain Calibration bit 3 mask. */ -#define DAC_CH1GAINCAL3_bp 3 /* Gain Calibration bit 3 position. */ -#define DAC_CH1GAINCAL4_bm (1<<4) /* Gain Calibration bit 4 mask. */ -#define DAC_CH1GAINCAL4_bp 4 /* Gain Calibration bit 4 position. */ -#define DAC_CH1GAINCAL5_bm (1<<5) /* Gain Calibration bit 5 mask. */ -#define DAC_CH1GAINCAL5_bp 5 /* Gain Calibration bit 5 position. */ -#define DAC_CH1GAINCAL6_bm (1<<6) /* Gain Calibration bit 6 mask. */ -#define DAC_CH1GAINCAL6_bp 6 /* Gain Calibration bit 6 position. */ - -/* DAC.CH1OFFSETCAL bit masks and bit positions */ -#define DAC_CH1OFFSETCAL_gm 0x7F /* Offset Calibration group mask. */ -#define DAC_CH1OFFSETCAL_gp 0 /* Offset Calibration group position. */ -#define DAC_CH1OFFSETCAL0_bm (1<<0) /* Offset Calibration bit 0 mask. */ -#define DAC_CH1OFFSETCAL0_bp 0 /* Offset Calibration bit 0 position. */ -#define DAC_CH1OFFSETCAL1_bm (1<<1) /* Offset Calibration bit 1 mask. */ -#define DAC_CH1OFFSETCAL1_bp 1 /* Offset Calibration bit 1 position. */ -#define DAC_CH1OFFSETCAL2_bm (1<<2) /* Offset Calibration bit 2 mask. */ -#define DAC_CH1OFFSETCAL2_bp 2 /* Offset Calibration bit 2 position. */ -#define DAC_CH1OFFSETCAL3_bm (1<<3) /* Offset Calibration bit 3 mask. */ -#define DAC_CH1OFFSETCAL3_bp 3 /* Offset Calibration bit 3 position. */ -#define DAC_CH1OFFSETCAL4_bm (1<<4) /* Offset Calibration bit 4 mask. */ -#define DAC_CH1OFFSETCAL4_bp 4 /* Offset Calibration bit 4 position. */ -#define DAC_CH1OFFSETCAL5_bm (1<<5) /* Offset Calibration bit 5 mask. */ -#define DAC_CH1OFFSETCAL5_bp 5 /* Offset Calibration bit 5 position. */ -#define DAC_CH1OFFSETCAL6_bm (1<<6) /* Offset Calibration bit 6 mask. */ -#define DAC_CH1OFFSETCAL6_bp 6 /* Offset Calibration bit 6 position. */ - -/* AC - Analog Comparator */ -/* AC.AC0CTRL bit masks and bit positions */ -#define AC_INTMODE_gm 0xC0 /* Interrupt Mode group mask. */ -#define AC_INTMODE_gp 6 /* Interrupt Mode group position. */ -#define AC_INTMODE0_bm (1<<6) /* Interrupt Mode bit 0 mask. */ -#define AC_INTMODE0_bp 6 /* Interrupt Mode bit 0 position. */ -#define AC_INTMODE1_bm (1<<7) /* Interrupt Mode bit 1 mask. */ -#define AC_INTMODE1_bp 7 /* Interrupt Mode bit 1 position. */ - -#define AC_INTLVL_gm 0x30 /* Interrupt Level group mask. */ -#define AC_INTLVL_gp 4 /* Interrupt Level group position. */ -#define AC_INTLVL0_bm (1<<4) /* Interrupt Level bit 0 mask. */ -#define AC_INTLVL0_bp 4 /* Interrupt Level bit 0 position. */ -#define AC_INTLVL1_bm (1<<5) /* Interrupt Level bit 1 mask. */ -#define AC_INTLVL1_bp 5 /* Interrupt Level bit 1 position. */ - -#define AC_HSMODE_bm 0x08 /* High-speed Mode bit mask. */ -#define AC_HSMODE_bp 3 /* High-speed Mode bit position. */ - -#define AC_HYSMODE_gm 0x06 /* Hysteresis Mode group mask. */ -#define AC_HYSMODE_gp 1 /* Hysteresis Mode group position. */ -#define AC_HYSMODE0_bm (1<<1) /* Hysteresis Mode bit 0 mask. */ -#define AC_HYSMODE0_bp 1 /* Hysteresis Mode bit 0 position. */ -#define AC_HYSMODE1_bm (1<<2) /* Hysteresis Mode bit 1 mask. */ -#define AC_HYSMODE1_bp 2 /* Hysteresis Mode bit 1 position. */ - -#define AC_ENABLE_bm 0x01 /* Enable bit mask. */ -#define AC_ENABLE_bp 0 /* Enable bit position. */ - -/* AC.AC1CTRL bit masks and bit positions */ -/* AC_INTMODE Predefined. */ -/* AC_INTMODE Predefined. */ - -/* AC_INTLVL Predefined. */ -/* AC_INTLVL Predefined. */ - -/* AC_HSMODE Predefined. */ -/* AC_HSMODE Predefined. */ - -/* AC_HYSMODE Predefined. */ -/* AC_HYSMODE Predefined. */ - -/* AC_ENABLE Predefined. */ -/* AC_ENABLE Predefined. */ - -/* AC.AC0MUXCTRL bit masks and bit positions */ -#define AC_MUXPOS_gm 0x38 /* MUX Positive Input group mask. */ -#define AC_MUXPOS_gp 3 /* MUX Positive Input group position. */ -#define AC_MUXPOS0_bm (1<<3) /* MUX Positive Input bit 0 mask. */ -#define AC_MUXPOS0_bp 3 /* MUX Positive Input bit 0 position. */ -#define AC_MUXPOS1_bm (1<<4) /* MUX Positive Input bit 1 mask. */ -#define AC_MUXPOS1_bp 4 /* MUX Positive Input bit 1 position. */ -#define AC_MUXPOS2_bm (1<<5) /* MUX Positive Input bit 2 mask. */ -#define AC_MUXPOS2_bp 5 /* MUX Positive Input bit 2 position. */ - -#define AC_MUXNEG_gm 0x07 /* MUX Negative Input group mask. */ -#define AC_MUXNEG_gp 0 /* MUX Negative Input group position. */ -#define AC_MUXNEG0_bm (1<<0) /* MUX Negative Input bit 0 mask. */ -#define AC_MUXNEG0_bp 0 /* MUX Negative Input bit 0 position. */ -#define AC_MUXNEG1_bm (1<<1) /* MUX Negative Input bit 1 mask. */ -#define AC_MUXNEG1_bp 1 /* MUX Negative Input bit 1 position. */ -#define AC_MUXNEG2_bm (1<<2) /* MUX Negative Input bit 2 mask. */ -#define AC_MUXNEG2_bp 2 /* MUX Negative Input bit 2 position. */ - -/* AC.AC1MUXCTRL bit masks and bit positions */ -/* AC_MUXPOS Predefined. */ -/* AC_MUXPOS Predefined. */ - -/* AC_MUXNEG Predefined. */ -/* AC_MUXNEG Predefined. */ - -/* AC.CTRLA bit masks and bit positions */ -#define AC_AC1OUT_bm 0x02 /* Analog Comparator 1 Output Enable bit mask. */ -#define AC_AC1OUT_bp 1 /* Analog Comparator 1 Output Enable bit position. */ - -#define AC_AC0OUT_bm 0x01 /* Analog Comparator 0 Output Enable bit mask. */ -#define AC_AC0OUT_bp 0 /* Analog Comparator 0 Output Enable bit position. */ - -/* AC.CTRLB bit masks and bit positions */ -#define AC_SCALEFAC_gm 0x3F /* VCC Voltage Scaler Factor group mask. */ -#define AC_SCALEFAC_gp 0 /* VCC Voltage Scaler Factor group position. */ -#define AC_SCALEFAC0_bm (1<<0) /* VCC Voltage Scaler Factor bit 0 mask. */ -#define AC_SCALEFAC0_bp 0 /* VCC Voltage Scaler Factor bit 0 position. */ -#define AC_SCALEFAC1_bm (1<<1) /* VCC Voltage Scaler Factor bit 1 mask. */ -#define AC_SCALEFAC1_bp 1 /* VCC Voltage Scaler Factor bit 1 position. */ -#define AC_SCALEFAC2_bm (1<<2) /* VCC Voltage Scaler Factor bit 2 mask. */ -#define AC_SCALEFAC2_bp 2 /* VCC Voltage Scaler Factor bit 2 position. */ -#define AC_SCALEFAC3_bm (1<<3) /* VCC Voltage Scaler Factor bit 3 mask. */ -#define AC_SCALEFAC3_bp 3 /* VCC Voltage Scaler Factor bit 3 position. */ -#define AC_SCALEFAC4_bm (1<<4) /* VCC Voltage Scaler Factor bit 4 mask. */ -#define AC_SCALEFAC4_bp 4 /* VCC Voltage Scaler Factor bit 4 position. */ -#define AC_SCALEFAC5_bm (1<<5) /* VCC Voltage Scaler Factor bit 5 mask. */ -#define AC_SCALEFAC5_bp 5 /* VCC Voltage Scaler Factor bit 5 position. */ - -/* AC.WINCTRL bit masks and bit positions */ -#define AC_WEN_bm 0x10 /* Window Mode Enable bit mask. */ -#define AC_WEN_bp 4 /* Window Mode Enable bit position. */ - -#define AC_WINTMODE_gm 0x0C /* Window Interrupt Mode group mask. */ -#define AC_WINTMODE_gp 2 /* Window Interrupt Mode group position. */ -#define AC_WINTMODE0_bm (1<<2) /* Window Interrupt Mode bit 0 mask. */ -#define AC_WINTMODE0_bp 2 /* Window Interrupt Mode bit 0 position. */ -#define AC_WINTMODE1_bm (1<<3) /* Window Interrupt Mode bit 1 mask. */ -#define AC_WINTMODE1_bp 3 /* Window Interrupt Mode bit 1 position. */ - -#define AC_WINTLVL_gm 0x03 /* Window Interrupt Level group mask. */ -#define AC_WINTLVL_gp 0 /* Window Interrupt Level group position. */ -#define AC_WINTLVL0_bm (1<<0) /* Window Interrupt Level bit 0 mask. */ -#define AC_WINTLVL0_bp 0 /* Window Interrupt Level bit 0 position. */ -#define AC_WINTLVL1_bm (1<<1) /* Window Interrupt Level bit 1 mask. */ -#define AC_WINTLVL1_bp 1 /* Window Interrupt Level bit 1 position. */ - -/* AC.STATUS bit masks and bit positions */ -#define AC_WSTATE_gm 0xC0 /* Window Mode State group mask. */ -#define AC_WSTATE_gp 6 /* Window Mode State group position. */ -#define AC_WSTATE0_bm (1<<6) /* Window Mode State bit 0 mask. */ -#define AC_WSTATE0_bp 6 /* Window Mode State bit 0 position. */ -#define AC_WSTATE1_bm (1<<7) /* Window Mode State bit 1 mask. */ -#define AC_WSTATE1_bp 7 /* Window Mode State bit 1 position. */ - -#define AC_AC1STATE_bm 0x20 /* Analog Comparator 1 State bit mask. */ -#define AC_AC1STATE_bp 5 /* Analog Comparator 1 State bit position. */ - -#define AC_AC0STATE_bm 0x10 /* Analog Comparator 0 State bit mask. */ -#define AC_AC0STATE_bp 4 /* Analog Comparator 0 State bit position. */ - -#define AC_WIF_bm 0x04 /* Window Mode Interrupt Flag bit mask. */ -#define AC_WIF_bp 2 /* Window Mode Interrupt Flag bit position. */ - -#define AC_AC1IF_bm 0x02 /* Analog Comparator 1 Interrupt Flag bit mask. */ -#define AC_AC1IF_bp 1 /* Analog Comparator 1 Interrupt Flag bit position. */ - -#define AC_AC0IF_bm 0x01 /* Analog Comparator 0 Interrupt Flag bit mask. */ -#define AC_AC0IF_bp 0 /* Analog Comparator 0 Interrupt Flag bit position. */ - -/* RTC - Real-Time Counter */ -/* RTC.CTRL bit masks and bit positions */ -#define RTC_PRESCALER_gm 0x07 /* Prescaling Factor group mask. */ -#define RTC_PRESCALER_gp 0 /* Prescaling Factor group position. */ -#define RTC_PRESCALER0_bm (1<<0) /* Prescaling Factor bit 0 mask. */ -#define RTC_PRESCALER0_bp 0 /* Prescaling Factor bit 0 position. */ -#define RTC_PRESCALER1_bm (1<<1) /* Prescaling Factor bit 1 mask. */ -#define RTC_PRESCALER1_bp 1 /* Prescaling Factor bit 1 position. */ -#define RTC_PRESCALER2_bm (1<<2) /* Prescaling Factor bit 2 mask. */ -#define RTC_PRESCALER2_bp 2 /* Prescaling Factor bit 2 position. */ - -/* RTC.STATUS bit masks and bit positions */ -#define RTC_SYNCBUSY_bm 0x01 /* Synchronization Busy Flag bit mask. */ -#define RTC_SYNCBUSY_bp 0 /* Synchronization Busy Flag bit position. */ - -/* RTC.INTCTRL bit masks and bit positions */ -#define RTC_COMPINTLVL_gm 0x0C /* Compare Match Interrupt Level group mask. */ -#define RTC_COMPINTLVL_gp 2 /* Compare Match Interrupt Level group position. */ -#define RTC_COMPINTLVL0_bm (1<<2) /* Compare Match Interrupt Level bit 0 mask. */ -#define RTC_COMPINTLVL0_bp 2 /* Compare Match Interrupt Level bit 0 position. */ -#define RTC_COMPINTLVL1_bm (1<<3) /* Compare Match Interrupt Level bit 1 mask. */ -#define RTC_COMPINTLVL1_bp 3 /* Compare Match Interrupt Level bit 1 position. */ - -#define RTC_OVFINTLVL_gm 0x03 /* Overflow Interrupt Level group mask. */ -#define RTC_OVFINTLVL_gp 0 /* Overflow Interrupt Level group position. */ -#define RTC_OVFINTLVL0_bm (1<<0) /* Overflow Interrupt Level bit 0 mask. */ -#define RTC_OVFINTLVL0_bp 0 /* Overflow Interrupt Level bit 0 position. */ -#define RTC_OVFINTLVL1_bm (1<<1) /* Overflow Interrupt Level bit 1 mask. */ -#define RTC_OVFINTLVL1_bp 1 /* Overflow Interrupt Level bit 1 position. */ - -/* RTC.INTFLAGS bit masks and bit positions */ -#define RTC_COMPIF_bm 0x02 /* Compare Match Interrupt Flag bit mask. */ -#define RTC_COMPIF_bp 1 /* Compare Match Interrupt Flag bit position. */ - -#define RTC_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ -#define RTC_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ - -/* TWI - Two-Wire Interface */ -/* TWI_MASTER.CTRLA bit masks and bit positions */ -#define TWI_MASTER_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ -#define TWI_MASTER_INTLVL_gp 6 /* Interrupt Level group position. */ -#define TWI_MASTER_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ -#define TWI_MASTER_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ -#define TWI_MASTER_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ -#define TWI_MASTER_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ - -#define TWI_MASTER_RIEN_bm 0x20 /* Read Interrupt Enable bit mask. */ -#define TWI_MASTER_RIEN_bp 5 /* Read Interrupt Enable bit position. */ - -#define TWI_MASTER_WIEN_bm 0x10 /* Write Interrupt Enable bit mask. */ -#define TWI_MASTER_WIEN_bp 4 /* Write Interrupt Enable bit position. */ - -#define TWI_MASTER_ENABLE_bm 0x08 /* Enable TWI Master bit mask. */ -#define TWI_MASTER_ENABLE_bp 3 /* Enable TWI Master bit position. */ - -/* TWI_MASTER.CTRLB bit masks and bit positions */ -#define TWI_MASTER_TIMEOUT_gm 0x0C /* Inactive Bus Timeout group mask. */ -#define TWI_MASTER_TIMEOUT_gp 2 /* Inactive Bus Timeout group position. */ -#define TWI_MASTER_TIMEOUT0_bm (1<<2) /* Inactive Bus Timeout bit 0 mask. */ -#define TWI_MASTER_TIMEOUT0_bp 2 /* Inactive Bus Timeout bit 0 position. */ -#define TWI_MASTER_TIMEOUT1_bm (1<<3) /* Inactive Bus Timeout bit 1 mask. */ -#define TWI_MASTER_TIMEOUT1_bp 3 /* Inactive Bus Timeout bit 1 position. */ - -#define TWI_MASTER_QCEN_bm 0x02 /* Quick Command Enable bit mask. */ -#define TWI_MASTER_QCEN_bp 1 /* Quick Command Enable bit position. */ - -#define TWI_MASTER_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ -#define TWI_MASTER_SMEN_bp 0 /* Smart Mode Enable bit position. */ - -/* TWI_MASTER.CTRLC bit masks and bit positions */ -#define TWI_MASTER_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ -#define TWI_MASTER_ACKACT_bp 2 /* Acknowledge Action bit position. */ - -#define TWI_MASTER_CMD_gm 0x03 /* Command group mask. */ -#define TWI_MASTER_CMD_gp 0 /* Command group position. */ -#define TWI_MASTER_CMD0_bm (1<<0) /* Command bit 0 mask. */ -#define TWI_MASTER_CMD0_bp 0 /* Command bit 0 position. */ -#define TWI_MASTER_CMD1_bm (1<<1) /* Command bit 1 mask. */ -#define TWI_MASTER_CMD1_bp 1 /* Command bit 1 position. */ - -/* TWI_MASTER.STATUS bit masks and bit positions */ -#define TWI_MASTER_RIF_bm 0x80 /* Read Interrupt Flag bit mask. */ -#define TWI_MASTER_RIF_bp 7 /* Read Interrupt Flag bit position. */ - -#define TWI_MASTER_WIF_bm 0x40 /* Write Interrupt Flag bit mask. */ -#define TWI_MASTER_WIF_bp 6 /* Write Interrupt Flag bit position. */ - -#define TWI_MASTER_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ -#define TWI_MASTER_CLKHOLD_bp 5 /* Clock Hold bit position. */ - -#define TWI_MASTER_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ -#define TWI_MASTER_RXACK_bp 4 /* Received Acknowledge bit position. */ - -#define TWI_MASTER_ARBLOST_bm 0x08 /* Arbitration Lost bit mask. */ -#define TWI_MASTER_ARBLOST_bp 3 /* Arbitration Lost bit position. */ - -#define TWI_MASTER_BUSERR_bm 0x04 /* Bus Error bit mask. */ -#define TWI_MASTER_BUSERR_bp 2 /* Bus Error bit position. */ - -#define TWI_MASTER_BUSSTATE_gm 0x03 /* Bus State group mask. */ -#define TWI_MASTER_BUSSTATE_gp 0 /* Bus State group position. */ -#define TWI_MASTER_BUSSTATE0_bm (1<<0) /* Bus State bit 0 mask. */ -#define TWI_MASTER_BUSSTATE0_bp 0 /* Bus State bit 0 position. */ -#define TWI_MASTER_BUSSTATE1_bm (1<<1) /* Bus State bit 1 mask. */ -#define TWI_MASTER_BUSSTATE1_bp 1 /* Bus State bit 1 position. */ - -/* TWI_SLAVE.CTRLA bit masks and bit positions */ -#define TWI_SLAVE_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ -#define TWI_SLAVE_INTLVL_gp 6 /* Interrupt Level group position. */ -#define TWI_SLAVE_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ -#define TWI_SLAVE_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ -#define TWI_SLAVE_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ -#define TWI_SLAVE_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ - -#define TWI_SLAVE_DIEN_bm 0x20 /* Data Interrupt Enable bit mask. */ -#define TWI_SLAVE_DIEN_bp 5 /* Data Interrupt Enable bit position. */ - -#define TWI_SLAVE_APIEN_bm 0x10 /* Address/Stop Interrupt Enable bit mask. */ -#define TWI_SLAVE_APIEN_bp 4 /* Address/Stop Interrupt Enable bit position. */ - -#define TWI_SLAVE_ENABLE_bm 0x08 /* Enable TWI Slave bit mask. */ -#define TWI_SLAVE_ENABLE_bp 3 /* Enable TWI Slave bit position. */ - -#define TWI_SLAVE_PIEN_bm 0x04 /* Stop Interrupt Enable bit mask. */ -#define TWI_SLAVE_PIEN_bp 2 /* Stop Interrupt Enable bit position. */ - -#define TWI_SLAVE_PMEN_bm 0x02 /* Promiscuous Mode Enable bit mask. */ -#define TWI_SLAVE_PMEN_bp 1 /* Promiscuous Mode Enable bit position. */ - -#define TWI_SLAVE_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ -#define TWI_SLAVE_SMEN_bp 0 /* Smart Mode Enable bit position. */ - -/* TWI_SLAVE.CTRLB bit masks and bit positions */ -#define TWI_SLAVE_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ -#define TWI_SLAVE_ACKACT_bp 2 /* Acknowledge Action bit position. */ - -#define TWI_SLAVE_CMD_gm 0x03 /* Command group mask. */ -#define TWI_SLAVE_CMD_gp 0 /* Command group position. */ -#define TWI_SLAVE_CMD0_bm (1<<0) /* Command bit 0 mask. */ -#define TWI_SLAVE_CMD0_bp 0 /* Command bit 0 position. */ -#define TWI_SLAVE_CMD1_bm (1<<1) /* Command bit 1 mask. */ -#define TWI_SLAVE_CMD1_bp 1 /* Command bit 1 position. */ - -/* TWI_SLAVE.STATUS bit masks and bit positions */ -#define TWI_SLAVE_DIF_bm 0x80 /* Data Interrupt Flag bit mask. */ -#define TWI_SLAVE_DIF_bp 7 /* Data Interrupt Flag bit position. */ - -#define TWI_SLAVE_APIF_bm 0x40 /* Address/Stop Interrupt Flag bit mask. */ -#define TWI_SLAVE_APIF_bp 6 /* Address/Stop Interrupt Flag bit position. */ - -#define TWI_SLAVE_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ -#define TWI_SLAVE_CLKHOLD_bp 5 /* Clock Hold bit position. */ - -#define TWI_SLAVE_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ -#define TWI_SLAVE_RXACK_bp 4 /* Received Acknowledge bit position. */ - -#define TWI_SLAVE_COLL_bm 0x08 /* Collision bit mask. */ -#define TWI_SLAVE_COLL_bp 3 /* Collision bit position. */ - -#define TWI_SLAVE_BUSERR_bm 0x04 /* Bus Error bit mask. */ -#define TWI_SLAVE_BUSERR_bp 2 /* Bus Error bit position. */ - -#define TWI_SLAVE_DIR_bm 0x02 /* Read/Write Direction bit mask. */ -#define TWI_SLAVE_DIR_bp 1 /* Read/Write Direction bit position. */ - -#define TWI_SLAVE_AP_bm 0x01 /* Slave Address or Stop bit mask. */ -#define TWI_SLAVE_AP_bp 0 /* Slave Address or Stop bit position. */ - -/* TWI_SLAVE.ADDRMASK bit masks and bit positions */ -#define TWI_SLAVE_ADDRMASK_gm 0xFE /* Address Mask group mask. */ -#define TWI_SLAVE_ADDRMASK_gp 1 /* Address Mask group position. */ -#define TWI_SLAVE_ADDRMASK0_bm (1<<1) /* Address Mask bit 0 mask. */ -#define TWI_SLAVE_ADDRMASK0_bp 1 /* Address Mask bit 0 position. */ -#define TWI_SLAVE_ADDRMASK1_bm (1<<2) /* Address Mask bit 1 mask. */ -#define TWI_SLAVE_ADDRMASK1_bp 2 /* Address Mask bit 1 position. */ -#define TWI_SLAVE_ADDRMASK2_bm (1<<3) /* Address Mask bit 2 mask. */ -#define TWI_SLAVE_ADDRMASK2_bp 3 /* Address Mask bit 2 position. */ -#define TWI_SLAVE_ADDRMASK3_bm (1<<4) /* Address Mask bit 3 mask. */ -#define TWI_SLAVE_ADDRMASK3_bp 4 /* Address Mask bit 3 position. */ -#define TWI_SLAVE_ADDRMASK4_bm (1<<5) /* Address Mask bit 4 mask. */ -#define TWI_SLAVE_ADDRMASK4_bp 5 /* Address Mask bit 4 position. */ -#define TWI_SLAVE_ADDRMASK5_bm (1<<6) /* Address Mask bit 5 mask. */ -#define TWI_SLAVE_ADDRMASK5_bp 6 /* Address Mask bit 5 position. */ -#define TWI_SLAVE_ADDRMASK6_bm (1<<7) /* Address Mask bit 6 mask. */ -#define TWI_SLAVE_ADDRMASK6_bp 7 /* Address Mask bit 6 position. */ - -#define TWI_SLAVE_ADDREN_bm 0x01 /* Address Enable bit mask. */ -#define TWI_SLAVE_ADDREN_bp 0 /* Address Enable bit position. */ - -/* TWI.CTRL bit masks and bit positions */ -#define TWI_SDAHOLD_gm 0x06 /* SDA Hold Time Enable group mask. */ -#define TWI_SDAHOLD_gp 1 /* SDA Hold Time Enable group position. */ -#define TWI_SDAHOLD0_bm (1<<1) /* SDA Hold Time Enable bit 0 mask. */ -#define TWI_SDAHOLD0_bp 1 /* SDA Hold Time Enable bit 0 position. */ -#define TWI_SDAHOLD1_bm (1<<2) /* SDA Hold Time Enable bit 1 mask. */ -#define TWI_SDAHOLD1_bp 2 /* SDA Hold Time Enable bit 1 position. */ - -#define TWI_EDIEN_bm 0x01 /* External Driver Interface Enable bit mask. */ -#define TWI_EDIEN_bp 0 /* External Driver Interface Enable bit position. */ - -/* USB - USB */ -/* USB_EP.STATUS bit masks and bit positions */ -#define USB_EP_STALLF_bm 0x80 /* Endpoint Stall Flag bit mask. */ -#define USB_EP_STALLF_bp 7 /* Endpoint Stall Flag bit position. */ - -#define USB_EP_CRC_bm 0x80 /* CRC Error Flag bit mask. */ -#define USB_EP_CRC_bp 7 /* CRC Error Flag bit position. */ - -#define USB_EP_UNF_bm 0x40 /* Underflow Enpoint FLag bit mask. */ -#define USB_EP_UNF_bp 6 /* Underflow Enpoint FLag bit position. */ - -#define USB_EP_OVF_bm 0x40 /* Overflow Enpoint Flag for Output Endpoints bit mask. */ -#define USB_EP_OVF_bp 6 /* Overflow Enpoint Flag for Output Endpoints bit position. */ - -#define USB_EP_TRNCOMPL0_bm 0x20 /* Transaction Complete 0 Flag bit mask. */ -#define USB_EP_TRNCOMPL0_bp 5 /* Transaction Complete 0 Flag bit position. */ - -#define USB_EP_TRNCOMPL1_bm 0x10 /* Transaction Complete 1 Flag bit mask. */ -#define USB_EP_TRNCOMPL1_bp 4 /* Transaction Complete 1 Flag bit position. */ - -#define USB_EP_SETUP_bm 0x10 /* SETUP Transaction Complete Flag bit mask. */ -#define USB_EP_SETUP_bp 4 /* SETUP Transaction Complete Flag bit position. */ - -#define USB_EP_BANK_bm 0x08 /* Bank Select bit mask. */ -#define USB_EP_BANK_bp 3 /* Bank Select bit position. */ - -#define USB_EP_BUSNACK1_bm 0x04 /* Data Buffer 1 Not Acknowledge bit mask. */ -#define USB_EP_BUSNACK1_bp 2 /* Data Buffer 1 Not Acknowledge bit position. */ - -#define USB_EP_BUSNACK0_bm 0x02 /* Data Buffer 0 Not Acknowledge bit mask. */ -#define USB_EP_BUSNACK0_bp 1 /* Data Buffer 0 Not Acknowledge bit position. */ - -#define USB_EP_TOGGLE_bm 0x01 /* Data Toggle bit mask. */ -#define USB_EP_TOGGLE_bp 0 /* Data Toggle bit position. */ - -/* USB_EP.CTRL bit masks and bit positions */ -#define USB_EP_TYPE_gm 0xC0 /* Endpoint Type group mask. */ -#define USB_EP_TYPE_gp 6 /* Endpoint Type group position. */ -#define USB_EP_TYPE0_bm (1<<6) /* Endpoint Type bit 0 mask. */ -#define USB_EP_TYPE0_bp 6 /* Endpoint Type bit 0 position. */ -#define USB_EP_TYPE1_bm (1<<7) /* Endpoint Type bit 1 mask. */ -#define USB_EP_TYPE1_bp 7 /* Endpoint Type bit 1 position. */ - -#define USB_EP_MULTIPKT_bm 0x20 /* Multi Packet Transfer Enable bit mask. */ -#define USB_EP_MULTIPKT_bp 5 /* Multi Packet Transfer Enable bit position. */ - -#define USB_EP_PINGPONG_bm 0x10 /* Ping-Pong Enable bit mask. */ -#define USB_EP_PINGPONG_bp 4 /* Ping-Pong Enable bit position. */ - -#define USB_EP_INTDSBL_bm 0x08 /* Interrupt Disable bit mask. */ -#define USB_EP_INTDSBL_bp 3 /* Interrupt Disable bit position. */ - -#define USB_EP_STALL_bm 0x04 /* Data Stall bit mask. */ -#define USB_EP_STALL_bp 2 /* Data Stall bit position. */ - -#define USB_EP_BUFSIZE_gm 0x07 /* Data Buffer Size group mask. */ -#define USB_EP_BUFSIZE_gp 0 /* Data Buffer Size group position. */ -#define USB_EP_BUFSIZE0_bm (1<<0) /* Data Buffer Size bit 0 mask. */ -#define USB_EP_BUFSIZE0_bp 0 /* Data Buffer Size bit 0 position. */ -#define USB_EP_BUFSIZE1_bm (1<<1) /* Data Buffer Size bit 1 mask. */ -#define USB_EP_BUFSIZE1_bp 1 /* Data Buffer Size bit 1 position. */ -#define USB_EP_BUFSIZE2_bm (1<<2) /* Data Buffer Size bit 2 mask. */ -#define USB_EP_BUFSIZE2_bp 2 /* Data Buffer Size bit 2 position. */ - -/* USB_EP.CNT bit masks and bit positions */ -#define USB_EP_ZLP_bm 0x8000 /* Zero Length Packet bit mask. */ -#define USB_EP_ZLP_bp 15 /* Zero Length Packet bit position. */ - -/* USB.CTRLA bit masks and bit positions */ -#define USB_ENABLE_bm 0x80 /* USB Enable bit mask. */ -#define USB_ENABLE_bp 7 /* USB Enable bit position. */ - -#define USB_SPEED_bm 0x40 /* Speed Select bit mask. */ -#define USB_SPEED_bp 6 /* Speed Select bit position. */ - -#define USB_FIFOEN_bm 0x20 /* USB FIFO Enable bit mask. */ -#define USB_FIFOEN_bp 5 /* USB FIFO Enable bit position. */ - -#define USB_STFRNUM_bm 0x10 /* Store Frame Number Enable bit mask. */ -#define USB_STFRNUM_bp 4 /* Store Frame Number Enable bit position. */ - -#define USB_MAXEP_gm 0x0F /* Maximum Endpoint Addresses group mask. */ -#define USB_MAXEP_gp 0 /* Maximum Endpoint Addresses group position. */ -#define USB_MAXEP0_bm (1<<0) /* Maximum Endpoint Addresses bit 0 mask. */ -#define USB_MAXEP0_bp 0 /* Maximum Endpoint Addresses bit 0 position. */ -#define USB_MAXEP1_bm (1<<1) /* Maximum Endpoint Addresses bit 1 mask. */ -#define USB_MAXEP1_bp 1 /* Maximum Endpoint Addresses bit 1 position. */ -#define USB_MAXEP2_bm (1<<2) /* Maximum Endpoint Addresses bit 2 mask. */ -#define USB_MAXEP2_bp 2 /* Maximum Endpoint Addresses bit 2 position. */ -#define USB_MAXEP3_bm (1<<3) /* Maximum Endpoint Addresses bit 3 mask. */ -#define USB_MAXEP3_bp 3 /* Maximum Endpoint Addresses bit 3 position. */ - -/* USB.CTRLB bit masks and bit positions */ -#define USB_PULLRST_bm 0x10 /* Pull during Reset bit mask. */ -#define USB_PULLRST_bp 4 /* Pull during Reset bit position. */ - -#define USB_RWAKEUP_bm 0x04 /* Remote Wake-up bit mask. */ -#define USB_RWAKEUP_bp 2 /* Remote Wake-up bit position. */ - -#define USB_GNACK_bm 0x02 /* Global NACK bit mask. */ -#define USB_GNACK_bp 1 /* Global NACK bit position. */ - -#define USB_ATTACH_bm 0x01 /* Attach bit mask. */ -#define USB_ATTACH_bp 0 /* Attach bit position. */ - -/* USB.STATUS bit masks and bit positions */ -#define USB_URESUME_bm 0x08 /* Upstream Resume bit mask. */ -#define USB_URESUME_bp 3 /* Upstream Resume bit position. */ - -#define USB_RESUME_bm 0x04 /* Resume bit mask. */ -#define USB_RESUME_bp 2 /* Resume bit position. */ - -#define USB_SUSPEND_bm 0x02 /* Bus Suspended bit mask. */ -#define USB_SUSPEND_bp 1 /* Bus Suspended bit position. */ - -#define USB_BUSRST_bm 0x01 /* Bus Reset bit mask. */ -#define USB_BUSRST_bp 0 /* Bus Reset bit position. */ - -/* USB.ADDR bit masks and bit positions */ -#define USB_ADDR_gm 0x7F /* Device Address group mask. */ -#define USB_ADDR_gp 0 /* Device Address group position. */ -#define USB_ADDR0_bm (1<<0) /* Device Address bit 0 mask. */ -#define USB_ADDR0_bp 0 /* Device Address bit 0 position. */ -#define USB_ADDR1_bm (1<<1) /* Device Address bit 1 mask. */ -#define USB_ADDR1_bp 1 /* Device Address bit 1 position. */ -#define USB_ADDR2_bm (1<<2) /* Device Address bit 2 mask. */ -#define USB_ADDR2_bp 2 /* Device Address bit 2 position. */ -#define USB_ADDR3_bm (1<<3) /* Device Address bit 3 mask. */ -#define USB_ADDR3_bp 3 /* Device Address bit 3 position. */ -#define USB_ADDR4_bm (1<<4) /* Device Address bit 4 mask. */ -#define USB_ADDR4_bp 4 /* Device Address bit 4 position. */ -#define USB_ADDR5_bm (1<<5) /* Device Address bit 5 mask. */ -#define USB_ADDR5_bp 5 /* Device Address bit 5 position. */ -#define USB_ADDR6_bm (1<<6) /* Device Address bit 6 mask. */ -#define USB_ADDR6_bp 6 /* Device Address bit 6 position. */ - -/* USB.FIFOWP bit masks and bit positions */ -#define USB_FIFOWP_gm 0x1F /* FIFO Write Pointer group mask. */ -#define USB_FIFOWP_gp 0 /* FIFO Write Pointer group position. */ -#define USB_FIFOWP0_bm (1<<0) /* FIFO Write Pointer bit 0 mask. */ -#define USB_FIFOWP0_bp 0 /* FIFO Write Pointer bit 0 position. */ -#define USB_FIFOWP1_bm (1<<1) /* FIFO Write Pointer bit 1 mask. */ -#define USB_FIFOWP1_bp 1 /* FIFO Write Pointer bit 1 position. */ -#define USB_FIFOWP2_bm (1<<2) /* FIFO Write Pointer bit 2 mask. */ -#define USB_FIFOWP2_bp 2 /* FIFO Write Pointer bit 2 position. */ -#define USB_FIFOWP3_bm (1<<3) /* FIFO Write Pointer bit 3 mask. */ -#define USB_FIFOWP3_bp 3 /* FIFO Write Pointer bit 3 position. */ -#define USB_FIFOWP4_bm (1<<4) /* FIFO Write Pointer bit 4 mask. */ -#define USB_FIFOWP4_bp 4 /* FIFO Write Pointer bit 4 position. */ - -/* USB.FIFORP bit masks and bit positions */ -#define USB_FIFORP_gm 0x1F /* FIFO Read Pointer group mask. */ -#define USB_FIFORP_gp 0 /* FIFO Read Pointer group position. */ -#define USB_FIFORP0_bm (1<<0) /* FIFO Read Pointer bit 0 mask. */ -#define USB_FIFORP0_bp 0 /* FIFO Read Pointer bit 0 position. */ -#define USB_FIFORP1_bm (1<<1) /* FIFO Read Pointer bit 1 mask. */ -#define USB_FIFORP1_bp 1 /* FIFO Read Pointer bit 1 position. */ -#define USB_FIFORP2_bm (1<<2) /* FIFO Read Pointer bit 2 mask. */ -#define USB_FIFORP2_bp 2 /* FIFO Read Pointer bit 2 position. */ -#define USB_FIFORP3_bm (1<<3) /* FIFO Read Pointer bit 3 mask. */ -#define USB_FIFORP3_bp 3 /* FIFO Read Pointer bit 3 position. */ -#define USB_FIFORP4_bm (1<<4) /* FIFO Read Pointer bit 4 mask. */ -#define USB_FIFORP4_bp 4 /* FIFO Read Pointer bit 4 position. */ - -/* USB.INTCTRLA bit masks and bit positions */ -#define USB_SOFIE_bm 0x80 /* Start Of Frame Interrupt Enable bit mask. */ -#define USB_SOFIE_bp 7 /* Start Of Frame Interrupt Enable bit position. */ - -#define USB_BUSEVIE_bm 0x40 /* Bus Event Interrupt Enable bit mask. */ -#define USB_BUSEVIE_bp 6 /* Bus Event Interrupt Enable bit position. */ - -#define USB_BUSERRIE_bm 0x20 /* Bus Error Interrupt Enable bit mask. */ -#define USB_BUSERRIE_bp 5 /* Bus Error Interrupt Enable bit position. */ - -#define USB_STALLIE_bm 0x10 /* STALL Interrupt Enable bit mask. */ -#define USB_STALLIE_bp 4 /* STALL Interrupt Enable bit position. */ - -#define USB_INTLVL_gm 0x03 /* Interrupt Level group mask. */ -#define USB_INTLVL_gp 0 /* Interrupt Level group position. */ -#define USB_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */ -#define USB_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */ -#define USB_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ -#define USB_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */ - -/* USB.INTCTRLB bit masks and bit positions */ -#define USB_TRNIE_bm 0x02 /* Transaction Complete Interrupt Enable bit mask. */ -#define USB_TRNIE_bp 1 /* Transaction Complete Interrupt Enable bit position. */ - -#define USB_SETUPIE_bm 0x01 /* SETUP Transaction Complete Interrupt Enable bit mask. */ -#define USB_SETUPIE_bp 0 /* SETUP Transaction Complete Interrupt Enable bit position. */ - -/* USB.INTFLAGSACLR bit masks and bit positions */ -#define USB_SOFIF_bm 0x80 /* Start Of Frame Interrupt Flag bit mask. */ -#define USB_SOFIF_bp 7 /* Start Of Frame Interrupt Flag bit position. */ - -#define USB_SUSPENDIF_bm 0x40 /* Suspend Interrupt Flag bit mask. */ -#define USB_SUSPENDIF_bp 6 /* Suspend Interrupt Flag bit position. */ - -#define USB_RESUMEIF_bm 0x20 /* Resume Interrupt Flag bit mask. */ -#define USB_RESUMEIF_bp 5 /* Resume Interrupt Flag bit position. */ - -#define USB_RSTIF_bm 0x10 /* Reset Interrupt Flag bit mask. */ -#define USB_RSTIF_bp 4 /* Reset Interrupt Flag bit position. */ - -#define USB_CRCIF_bm 0x08 /* Isochronous CRC Error Interrupt Flag bit mask. */ -#define USB_CRCIF_bp 3 /* Isochronous CRC Error Interrupt Flag bit position. */ - -#define USB_UNFIF_bm 0x04 /* Underflow Interrupt Flag bit mask. */ -#define USB_UNFIF_bp 2 /* Underflow Interrupt Flag bit position. */ - -#define USB_OVFIF_bm 0x02 /* Overflow Interrupt Flag bit mask. */ -#define USB_OVFIF_bp 1 /* Overflow Interrupt Flag bit position. */ - -#define USB_STALLIF_bm 0x01 /* STALL Interrupt Flag bit mask. */ -#define USB_STALLIF_bp 0 /* STALL Interrupt Flag bit position. */ - -/* USB.INTFLAGSASET bit masks and bit positions */ -/* USB_SOFIF Predefined. */ -/* USB_SOFIF Predefined. */ - -/* USB_SUSPENDIF Predefined. */ -/* USB_SUSPENDIF Predefined. */ - -/* USB_RESUMEIF Predefined. */ -/* USB_RESUMEIF Predefined. */ - -/* USB_RSTIF Predefined. */ -/* USB_RSTIF Predefined. */ - -/* USB_CRCIF Predefined. */ -/* USB_CRCIF Predefined. */ - -/* USB_UNFIF Predefined. */ -/* USB_UNFIF Predefined. */ - -/* USB_OVFIF Predefined. */ -/* USB_OVFIF Predefined. */ - -/* USB_STALLIF Predefined. */ -/* USB_STALLIF Predefined. */ - -/* USB.INTFLAGSBCLR bit masks and bit positions */ -#define USB_TRNIF_bm 0x02 /* Transaction Complete Interrupt Flag bit mask. */ -#define USB_TRNIF_bp 1 /* Transaction Complete Interrupt Flag bit position. */ - -#define USB_SETUPIF_bm 0x01 /* SETUP Transaction Complete Interrupt Flag bit mask. */ -#define USB_SETUPIF_bp 0 /* SETUP Transaction Complete Interrupt Flag bit position. */ - -/* USB.INTFLAGSBSET bit masks and bit positions */ -/* USB_TRNIF Predefined. */ -/* USB_TRNIF Predefined. */ - -/* USB_SETUPIF Predefined. */ -/* USB_SETUPIF Predefined. */ - -/* PORT - I/O Port Configuration */ -/* PORT.INTCTRL bit masks and bit positions */ -#define PORT_INT1LVL_gm 0x0C /* Port Interrupt 1 Level group mask. */ -#define PORT_INT1LVL_gp 2 /* Port Interrupt 1 Level group position. */ -#define PORT_INT1LVL0_bm (1<<2) /* Port Interrupt 1 Level bit 0 mask. */ -#define PORT_INT1LVL0_bp 2 /* Port Interrupt 1 Level bit 0 position. */ -#define PORT_INT1LVL1_bm (1<<3) /* Port Interrupt 1 Level bit 1 mask. */ -#define PORT_INT1LVL1_bp 3 /* Port Interrupt 1 Level bit 1 position. */ - -#define PORT_INT0LVL_gm 0x03 /* Port Interrupt 0 Level group mask. */ -#define PORT_INT0LVL_gp 0 /* Port Interrupt 0 Level group position. */ -#define PORT_INT0LVL0_bm (1<<0) /* Port Interrupt 0 Level bit 0 mask. */ -#define PORT_INT0LVL0_bp 0 /* Port Interrupt 0 Level bit 0 position. */ -#define PORT_INT0LVL1_bm (1<<1) /* Port Interrupt 0 Level bit 1 mask. */ -#define PORT_INT0LVL1_bp 1 /* Port Interrupt 0 Level bit 1 position. */ - -/* PORT.INTFLAGS bit masks and bit positions */ -#define PORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ -#define PORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ - -#define PORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ -#define PORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ - -/* PORT.REMAP bit masks and bit positions */ -#define PORT_SPI_bm 0x20 /* SPI bit mask. */ -#define PORT_SPI_bp 5 /* SPI bit position. */ - -#define PORT_USART0_bm 0x10 /* USART0 bit mask. */ -#define PORT_USART0_bp 4 /* USART0 bit position. */ - -#define PORT_TC0D_bm 0x08 /* Timer/Counter 0 Output Compare D bit mask. */ -#define PORT_TC0D_bp 3 /* Timer/Counter 0 Output Compare D bit position. */ - -#define PORT_TC0C_bm 0x04 /* Timer/Counter 0 Output Compare C bit mask. */ -#define PORT_TC0C_bp 2 /* Timer/Counter 0 Output Compare C bit position. */ - -#define PORT_TC0B_bm 0x02 /* Timer/Counter 0 Output Compare B bit mask. */ -#define PORT_TC0B_bp 1 /* Timer/Counter 0 Output Compare B bit position. */ - -#define PORT_TC0A_bm 0x01 /* Timer/Counter 0 Output Compare A bit mask. */ -#define PORT_TC0A_bp 0 /* Timer/Counter 0 Output Compare A bit position. */ - -/* PORT.PIN0CTRL bit masks and bit positions */ -#define PORT_SRLEN_bm 0x80 /* Slew Rate Enable bit mask. */ -#define PORT_SRLEN_bp 7 /* Slew Rate Enable bit position. */ - -#define PORT_INVEN_bm 0x40 /* Inverted I/O Enable bit mask. */ -#define PORT_INVEN_bp 6 /* Inverted I/O Enable bit position. */ - -#define PORT_OPC_gm 0x38 /* Output/Pull Configuration group mask. */ -#define PORT_OPC_gp 3 /* Output/Pull Configuration group position. */ -#define PORT_OPC0_bm (1<<3) /* Output/Pull Configuration bit 0 mask. */ -#define PORT_OPC0_bp 3 /* Output/Pull Configuration bit 0 position. */ -#define PORT_OPC1_bm (1<<4) /* Output/Pull Configuration bit 1 mask. */ -#define PORT_OPC1_bp 4 /* Output/Pull Configuration bit 1 position. */ -#define PORT_OPC2_bm (1<<5) /* Output/Pull Configuration bit 2 mask. */ -#define PORT_OPC2_bp 5 /* Output/Pull Configuration bit 2 position. */ - -#define PORT_ISC_gm 0x07 /* Input/Sense Configuration group mask. */ -#define PORT_ISC_gp 0 /* Input/Sense Configuration group position. */ -#define PORT_ISC0_bm (1<<0) /* Input/Sense Configuration bit 0 mask. */ -#define PORT_ISC0_bp 0 /* Input/Sense Configuration bit 0 position. */ -#define PORT_ISC1_bm (1<<1) /* Input/Sense Configuration bit 1 mask. */ -#define PORT_ISC1_bp 1 /* Input/Sense Configuration bit 1 position. */ -#define PORT_ISC2_bm (1<<2) /* Input/Sense Configuration bit 2 mask. */ -#define PORT_ISC2_bp 2 /* Input/Sense Configuration bit 2 position. */ - -/* PORT.PIN1CTRL bit masks and bit positions */ -/* PORT_SRLEN Predefined. */ -/* PORT_SRLEN Predefined. */ - -/* PORT_INVEN Predefined. */ -/* PORT_INVEN Predefined. */ - -/* PORT_OPC Predefined. */ -/* PORT_OPC Predefined. */ - -/* PORT_ISC Predefined. */ -/* PORT_ISC Predefined. */ - -/* PORT.PIN2CTRL bit masks and bit positions */ -/* PORT_SRLEN Predefined. */ -/* PORT_SRLEN Predefined. */ - -/* PORT_INVEN Predefined. */ -/* PORT_INVEN Predefined. */ - -/* PORT_OPC Predefined. */ -/* PORT_OPC Predefined. */ - -/* PORT_ISC Predefined. */ -/* PORT_ISC Predefined. */ - -/* PORT.PIN3CTRL bit masks and bit positions */ -/* PORT_SRLEN Predefined. */ -/* PORT_SRLEN Predefined. */ - -/* PORT_INVEN Predefined. */ -/* PORT_INVEN Predefined. */ - -/* PORT_OPC Predefined. */ -/* PORT_OPC Predefined. */ - -/* PORT_ISC Predefined. */ -/* PORT_ISC Predefined. */ - -/* PORT.PIN4CTRL bit masks and bit positions */ -/* PORT_SRLEN Predefined. */ -/* PORT_SRLEN Predefined. */ - -/* PORT_INVEN Predefined. */ -/* PORT_INVEN Predefined. */ - -/* PORT_OPC Predefined. */ -/* PORT_OPC Predefined. */ - -/* PORT_ISC Predefined. */ -/* PORT_ISC Predefined. */ - -/* PORT.PIN5CTRL bit masks and bit positions */ -/* PORT_SRLEN Predefined. */ -/* PORT_SRLEN Predefined. */ - -/* PORT_INVEN Predefined. */ -/* PORT_INVEN Predefined. */ - -/* PORT_OPC Predefined. */ -/* PORT_OPC Predefined. */ - -/* PORT_ISC Predefined. */ -/* PORT_ISC Predefined. */ - -/* PORT.PIN6CTRL bit masks and bit positions */ -/* PORT_SRLEN Predefined. */ -/* PORT_SRLEN Predefined. */ - -/* PORT_INVEN Predefined. */ -/* PORT_INVEN Predefined. */ - -/* PORT_OPC Predefined. */ -/* PORT_OPC Predefined. */ - -/* PORT_ISC Predefined. */ -/* PORT_ISC Predefined. */ - -/* PORT.PIN7CTRL bit masks and bit positions */ -/* PORT_SRLEN Predefined. */ -/* PORT_SRLEN Predefined. */ - -/* PORT_INVEN Predefined. */ -/* PORT_INVEN Predefined. */ - -/* PORT_OPC Predefined. */ -/* PORT_OPC Predefined. */ - -/* PORT_ISC Predefined. */ -/* PORT_ISC Predefined. */ - -/* TC - 16-bit Timer/Counter With PWM */ -/* TC0.CTRLA bit masks and bit positions */ -#define TC0_CLKSEL_gm 0x0F /* Clock Selection group mask. */ -#define TC0_CLKSEL_gp 0 /* Clock Selection group position. */ -#define TC0_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ -#define TC0_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ -#define TC0_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ -#define TC0_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ -#define TC0_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ -#define TC0_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ -#define TC0_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ -#define TC0_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ - -/* TC0.CTRLB bit masks and bit positions */ -#define TC0_CCDEN_bm 0x80 /* Compare or Capture D Enable bit mask. */ -#define TC0_CCDEN_bp 7 /* Compare or Capture D Enable bit position. */ - -#define TC0_CCCEN_bm 0x40 /* Compare or Capture C Enable bit mask. */ -#define TC0_CCCEN_bp 6 /* Compare or Capture C Enable bit position. */ - -#define TC0_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ -#define TC0_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ - -#define TC0_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ -#define TC0_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ - -#define TC0_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ -#define TC0_WGMODE_gp 0 /* Waveform generation mode group position. */ -#define TC0_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ -#define TC0_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ -#define TC0_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ -#define TC0_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ -#define TC0_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ -#define TC0_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ - -/* TC0.CTRLC bit masks and bit positions */ -#define TC0_CMPD_bm 0x08 /* Compare D Output Value bit mask. */ -#define TC0_CMPD_bp 3 /* Compare D Output Value bit position. */ - -#define TC0_CMPC_bm 0x04 /* Compare C Output Value bit mask. */ -#define TC0_CMPC_bp 2 /* Compare C Output Value bit position. */ - -#define TC0_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ -#define TC0_CMPB_bp 1 /* Compare B Output Value bit position. */ - -#define TC0_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ -#define TC0_CMPA_bp 0 /* Compare A Output Value bit position. */ - -/* TC0.CTRLD bit masks and bit positions */ -#define TC0_EVACT_gm 0xE0 /* Event Action group mask. */ -#define TC0_EVACT_gp 5 /* Event Action group position. */ -#define TC0_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ -#define TC0_EVACT0_bp 5 /* Event Action bit 0 position. */ -#define TC0_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ -#define TC0_EVACT1_bp 6 /* Event Action bit 1 position. */ -#define TC0_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ -#define TC0_EVACT2_bp 7 /* Event Action bit 2 position. */ - -#define TC0_EVDLY_bm 0x10 /* Event Delay bit mask. */ -#define TC0_EVDLY_bp 4 /* Event Delay bit position. */ - -#define TC0_EVSEL_gm 0x0F /* Event Source Select group mask. */ -#define TC0_EVSEL_gp 0 /* Event Source Select group position. */ -#define TC0_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ -#define TC0_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ -#define TC0_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ -#define TC0_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ -#define TC0_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ -#define TC0_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ -#define TC0_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ -#define TC0_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ - -/* TC0.CTRLE bit masks and bit positions */ -#define TC0_BYTEM_gm 0x03 /* Byte Mode group mask. */ -#define TC0_BYTEM_gp 0 /* Byte Mode group position. */ -#define TC0_BYTEM0_bm (1<<0) /* Byte Mode bit 0 mask. */ -#define TC0_BYTEM0_bp 0 /* Byte Mode bit 0 position. */ -#define TC0_BYTEM1_bm (1<<1) /* Byte Mode bit 1 mask. */ -#define TC0_BYTEM1_bp 1 /* Byte Mode bit 1 position. */ - -/* TC0.INTCTRLA bit masks and bit positions */ -#define TC0_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ -#define TC0_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ -#define TC0_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ -#define TC0_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ -#define TC0_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ -#define TC0_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ - -#define TC0_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ -#define TC0_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ -#define TC0_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ -#define TC0_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ -#define TC0_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ -#define TC0_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ - -/* TC0.INTCTRLB bit masks and bit positions */ -#define TC0_CCDINTLVL_gm 0xC0 /* Compare or Capture D Interrupt Level group mask. */ -#define TC0_CCDINTLVL_gp 6 /* Compare or Capture D Interrupt Level group position. */ -#define TC0_CCDINTLVL0_bm (1<<6) /* Compare or Capture D Interrupt Level bit 0 mask. */ -#define TC0_CCDINTLVL0_bp 6 /* Compare or Capture D Interrupt Level bit 0 position. */ -#define TC0_CCDINTLVL1_bm (1<<7) /* Compare or Capture D Interrupt Level bit 1 mask. */ -#define TC0_CCDINTLVL1_bp 7 /* Compare or Capture D Interrupt Level bit 1 position. */ - -#define TC0_CCCINTLVL_gm 0x30 /* Compare or Capture C Interrupt Level group mask. */ -#define TC0_CCCINTLVL_gp 4 /* Compare or Capture C Interrupt Level group position. */ -#define TC0_CCCINTLVL0_bm (1<<4) /* Compare or Capture C Interrupt Level bit 0 mask. */ -#define TC0_CCCINTLVL0_bp 4 /* Compare or Capture C Interrupt Level bit 0 position. */ -#define TC0_CCCINTLVL1_bm (1<<5) /* Compare or Capture C Interrupt Level bit 1 mask. */ -#define TC0_CCCINTLVL1_bp 5 /* Compare or Capture C Interrupt Level bit 1 position. */ - -#define TC0_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ -#define TC0_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ -#define TC0_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ -#define TC0_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ -#define TC0_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ -#define TC0_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ - -#define TC0_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ -#define TC0_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ -#define TC0_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ -#define TC0_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ -#define TC0_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ -#define TC0_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ - -/* TC0.CTRLFCLR bit masks and bit positions */ -#define TC0_CMD_gm 0x0C /* Command group mask. */ -#define TC0_CMD_gp 2 /* Command group position. */ -#define TC0_CMD0_bm (1<<2) /* Command bit 0 mask. */ -#define TC0_CMD0_bp 2 /* Command bit 0 position. */ -#define TC0_CMD1_bm (1<<3) /* Command bit 1 mask. */ -#define TC0_CMD1_bp 3 /* Command bit 1 position. */ - -#define TC0_LUPD_bm 0x02 /* Lock Update bit mask. */ -#define TC0_LUPD_bp 1 /* Lock Update bit position. */ - -#define TC0_DIR_bm 0x01 /* Direction bit mask. */ -#define TC0_DIR_bp 0 /* Direction bit position. */ - -/* TC0.CTRLFSET bit masks and bit positions */ -/* TC0_CMD Predefined. */ -/* TC0_CMD Predefined. */ - -/* TC0_LUPD Predefined. */ -/* TC0_LUPD Predefined. */ - -/* TC0_DIR Predefined. */ -/* TC0_DIR Predefined. */ - -/* TC0.CTRLGCLR bit masks and bit positions */ -#define TC0_CCDBV_bm 0x10 /* Compare or Capture D Buffer Valid bit mask. */ -#define TC0_CCDBV_bp 4 /* Compare or Capture D Buffer Valid bit position. */ - -#define TC0_CCCBV_bm 0x08 /* Compare or Capture C Buffer Valid bit mask. */ -#define TC0_CCCBV_bp 3 /* Compare or Capture C Buffer Valid bit position. */ - -#define TC0_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ -#define TC0_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ - -#define TC0_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ -#define TC0_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ - -#define TC0_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ -#define TC0_PERBV_bp 0 /* Period Buffer Valid bit position. */ - -/* TC0.CTRLGSET bit masks and bit positions */ -/* TC0_CCDBV Predefined. */ -/* TC0_CCDBV Predefined. */ - -/* TC0_CCCBV Predefined. */ -/* TC0_CCCBV Predefined. */ - -/* TC0_CCBBV Predefined. */ -/* TC0_CCBBV Predefined. */ - -/* TC0_CCABV Predefined. */ -/* TC0_CCABV Predefined. */ - -/* TC0_PERBV Predefined. */ -/* TC0_PERBV Predefined. */ - -/* TC0.INTFLAGS bit masks and bit positions */ -#define TC0_CCDIF_bm 0x80 /* Compare or Capture D Interrupt Flag bit mask. */ -#define TC0_CCDIF_bp 7 /* Compare or Capture D Interrupt Flag bit position. */ - -#define TC0_CCCIF_bm 0x40 /* Compare or Capture C Interrupt Flag bit mask. */ -#define TC0_CCCIF_bp 6 /* Compare or Capture C Interrupt Flag bit position. */ - -#define TC0_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ -#define TC0_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ - -#define TC0_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ -#define TC0_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ - -#define TC0_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ -#define TC0_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ - -#define TC0_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ -#define TC0_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ - -/* TC1.CTRLA bit masks and bit positions */ -#define TC1_CLKSEL_gm 0x0F /* Clock Selection group mask. */ -#define TC1_CLKSEL_gp 0 /* Clock Selection group position. */ -#define TC1_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ -#define TC1_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ -#define TC1_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ -#define TC1_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ -#define TC1_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ -#define TC1_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ -#define TC1_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ -#define TC1_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ - -/* TC1.CTRLB bit masks and bit positions */ -#define TC1_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ -#define TC1_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ - -#define TC1_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ -#define TC1_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ - -#define TC1_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ -#define TC1_WGMODE_gp 0 /* Waveform generation mode group position. */ -#define TC1_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ -#define TC1_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ -#define TC1_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ -#define TC1_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ -#define TC1_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ -#define TC1_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ - -/* TC1.CTRLC bit masks and bit positions */ -#define TC1_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ -#define TC1_CMPB_bp 1 /* Compare B Output Value bit position. */ - -#define TC1_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ -#define TC1_CMPA_bp 0 /* Compare A Output Value bit position. */ - -/* TC1.CTRLD bit masks and bit positions */ -#define TC1_EVACT_gm 0xE0 /* Event Action group mask. */ -#define TC1_EVACT_gp 5 /* Event Action group position. */ -#define TC1_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ -#define TC1_EVACT0_bp 5 /* Event Action bit 0 position. */ -#define TC1_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ -#define TC1_EVACT1_bp 6 /* Event Action bit 1 position. */ -#define TC1_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ -#define TC1_EVACT2_bp 7 /* Event Action bit 2 position. */ - -#define TC1_EVDLY_bm 0x10 /* Event Delay bit mask. */ -#define TC1_EVDLY_bp 4 /* Event Delay bit position. */ - -#define TC1_EVSEL_gm 0x0F /* Event Source Select group mask. */ -#define TC1_EVSEL_gp 0 /* Event Source Select group position. */ -#define TC1_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ -#define TC1_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ -#define TC1_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ -#define TC1_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ -#define TC1_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ -#define TC1_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ -#define TC1_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ -#define TC1_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ - -/* TC1.CTRLE bit masks and bit positions */ -#define TC1_BYTEM_bm 0x01 /* Byte Mode bit mask. */ -#define TC1_BYTEM_bp 0 /* Byte Mode bit position. */ - -/* TC1.INTCTRLA bit masks and bit positions */ -#define TC1_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ -#define TC1_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ -#define TC1_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ -#define TC1_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ -#define TC1_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ -#define TC1_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ - -#define TC1_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ -#define TC1_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ -#define TC1_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ -#define TC1_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ -#define TC1_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ -#define TC1_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ - -/* TC1.INTCTRLB bit masks and bit positions */ -#define TC1_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ -#define TC1_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ -#define TC1_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ -#define TC1_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ -#define TC1_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ -#define TC1_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ - -#define TC1_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ -#define TC1_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ -#define TC1_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ -#define TC1_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ -#define TC1_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ -#define TC1_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ - -/* TC1.CTRLFCLR bit masks and bit positions */ -#define TC1_CMD_gm 0x0C /* Command group mask. */ -#define TC1_CMD_gp 2 /* Command group position. */ -#define TC1_CMD0_bm (1<<2) /* Command bit 0 mask. */ -#define TC1_CMD0_bp 2 /* Command bit 0 position. */ -#define TC1_CMD1_bm (1<<3) /* Command bit 1 mask. */ -#define TC1_CMD1_bp 3 /* Command bit 1 position. */ - -#define TC1_LUPD_bm 0x02 /* Lock Update bit mask. */ -#define TC1_LUPD_bp 1 /* Lock Update bit position. */ - -#define TC1_DIR_bm 0x01 /* Direction bit mask. */ -#define TC1_DIR_bp 0 /* Direction bit position. */ - -/* TC1.CTRLFSET bit masks and bit positions */ -/* TC1_CMD Predefined. */ -/* TC1_CMD Predefined. */ - -/* TC1_LUPD Predefined. */ -/* TC1_LUPD Predefined. */ - -/* TC1_DIR Predefined. */ -/* TC1_DIR Predefined. */ - -/* TC1.CTRLGCLR bit masks and bit positions */ -#define TC1_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ -#define TC1_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ - -#define TC1_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ -#define TC1_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ - -#define TC1_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ -#define TC1_PERBV_bp 0 /* Period Buffer Valid bit position. */ - -/* TC1.CTRLGSET bit masks and bit positions */ -/* TC1_CCBBV Predefined. */ -/* TC1_CCBBV Predefined. */ - -/* TC1_CCABV Predefined. */ -/* TC1_CCABV Predefined. */ - -/* TC1_PERBV Predefined. */ -/* TC1_PERBV Predefined. */ - -/* TC1.INTFLAGS bit masks and bit positions */ -#define TC1_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ -#define TC1_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ - -#define TC1_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ -#define TC1_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ - -#define TC1_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ -#define TC1_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ - -#define TC1_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ -#define TC1_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ - -/* TC2 - 16-bit Timer/Counter type 2 */ -/* TC2.CTRLA bit masks and bit positions */ -#define TC2_CLKSEL_gm 0x0F /* Clock Selection group mask. */ -#define TC2_CLKSEL_gp 0 /* Clock Selection group position. */ -#define TC2_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ -#define TC2_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ -#define TC2_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ -#define TC2_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ -#define TC2_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ -#define TC2_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ -#define TC2_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ -#define TC2_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ - -/* TC2.CTRLB bit masks and bit positions */ -#define TC2_HCMPDEN_bm 0x80 /* High Byte Compare D Enable bit mask. */ -#define TC2_HCMPDEN_bp 7 /* High Byte Compare D Enable bit position. */ - -#define TC2_HCMPCEN_bm 0x40 /* High Byte Compare C Enable bit mask. */ -#define TC2_HCMPCEN_bp 6 /* High Byte Compare C Enable bit position. */ - -#define TC2_HCMPBEN_bm 0x20 /* High Byte Compare B Enable bit mask. */ -#define TC2_HCMPBEN_bp 5 /* High Byte Compare B Enable bit position. */ - -#define TC2_HCMPAEN_bm 0x10 /* High Byte Compare A Enable bit mask. */ -#define TC2_HCMPAEN_bp 4 /* High Byte Compare A Enable bit position. */ - -#define TC2_LCMPDEN_bm 0x08 /* Low Byte Compare D Enable bit mask. */ -#define TC2_LCMPDEN_bp 3 /* Low Byte Compare D Enable bit position. */ - -#define TC2_LCMPCEN_bm 0x04 /* Low Byte Compare C Enable bit mask. */ -#define TC2_LCMPCEN_bp 2 /* Low Byte Compare C Enable bit position. */ - -#define TC2_LCMPBEN_bm 0x02 /* Low Byte Compare B Enable bit mask. */ -#define TC2_LCMPBEN_bp 1 /* Low Byte Compare B Enable bit position. */ - -#define TC2_LCMPAEN_bm 0x01 /* Low Byte Compare A Enable bit mask. */ -#define TC2_LCMPAEN_bp 0 /* Low Byte Compare A Enable bit position. */ - -/* TC2.CTRLC bit masks and bit positions */ -#define TC2_HCMPD_bm 0x80 /* High Byte Compare D Output Value bit mask. */ -#define TC2_HCMPD_bp 7 /* High Byte Compare D Output Value bit position. */ - -#define TC2_HCMPC_bm 0x40 /* High Byte Compare C Output Value bit mask. */ -#define TC2_HCMPC_bp 6 /* High Byte Compare C Output Value bit position. */ - -#define TC2_HCMPB_bm 0x20 /* High Byte Compare B Output Value bit mask. */ -#define TC2_HCMPB_bp 5 /* High Byte Compare B Output Value bit position. */ - -#define TC2_HCMPA_bm 0x10 /* High Byte Compare A Output Value bit mask. */ -#define TC2_HCMPA_bp 4 /* High Byte Compare A Output Value bit position. */ - -#define TC2_LCMPD_bm 0x08 /* Low Byte Compare D Output Value bit mask. */ -#define TC2_LCMPD_bp 3 /* Low Byte Compare D Output Value bit position. */ - -#define TC2_LCMPC_bm 0x04 /* Low Byte Compare C Output Value bit mask. */ -#define TC2_LCMPC_bp 2 /* Low Byte Compare C Output Value bit position. */ - -#define TC2_LCMPB_bm 0x02 /* Low Byte Compare B Output Value bit mask. */ -#define TC2_LCMPB_bp 1 /* Low Byte Compare B Output Value bit position. */ - -#define TC2_LCMPA_bm 0x01 /* Low Byte Compare A Output Value bit mask. */ -#define TC2_LCMPA_bp 0 /* Low Byte Compare A Output Value bit position. */ - -/* TC2.CTRLE bit masks and bit positions */ -#define TC2_BYTEM_gm 0x03 /* Byte Mode group mask. */ -#define TC2_BYTEM_gp 0 /* Byte Mode group position. */ -#define TC2_BYTEM0_bm (1<<0) /* Byte Mode bit 0 mask. */ -#define TC2_BYTEM0_bp 0 /* Byte Mode bit 0 position. */ -#define TC2_BYTEM1_bm (1<<1) /* Byte Mode bit 1 mask. */ -#define TC2_BYTEM1_bp 1 /* Byte Mode bit 1 position. */ - -/* TC2.INTCTRLA bit masks and bit positions */ -#define TC2_HUNFINTLVL_gm 0x0C /* High Byte Underflow Interrupt Level group mask. */ -#define TC2_HUNFINTLVL_gp 2 /* High Byte Underflow Interrupt Level group position. */ -#define TC2_HUNFINTLVL0_bm (1<<2) /* High Byte Underflow Interrupt Level bit 0 mask. */ -#define TC2_HUNFINTLVL0_bp 2 /* High Byte Underflow Interrupt Level bit 0 position. */ -#define TC2_HUNFINTLVL1_bm (1<<3) /* High Byte Underflow Interrupt Level bit 1 mask. */ -#define TC2_HUNFINTLVL1_bp 3 /* High Byte Underflow Interrupt Level bit 1 position. */ - -#define TC2_LUNFINTLVL_gm 0x03 /* Low Byte Underflow interrupt level group mask. */ -#define TC2_LUNFINTLVL_gp 0 /* Low Byte Underflow interrupt level group position. */ -#define TC2_LUNFINTLVL0_bm (1<<0) /* Low Byte Underflow interrupt level bit 0 mask. */ -#define TC2_LUNFINTLVL0_bp 0 /* Low Byte Underflow interrupt level bit 0 position. */ -#define TC2_LUNFINTLVL1_bm (1<<1) /* Low Byte Underflow interrupt level bit 1 mask. */ -#define TC2_LUNFINTLVL1_bp 1 /* Low Byte Underflow interrupt level bit 1 position. */ - -/* TC2.INTCTRLB bit masks and bit positions */ -#define TC2_LCMPDINTLVL_gm 0xC0 /* Low Byte Compare D Interrupt Level group mask. */ -#define TC2_LCMPDINTLVL_gp 6 /* Low Byte Compare D Interrupt Level group position. */ -#define TC2_LCMPDINTLVL0_bm (1<<6) /* Low Byte Compare D Interrupt Level bit 0 mask. */ -#define TC2_LCMPDINTLVL0_bp 6 /* Low Byte Compare D Interrupt Level bit 0 position. */ -#define TC2_LCMPDINTLVL1_bm (1<<7) /* Low Byte Compare D Interrupt Level bit 1 mask. */ -#define TC2_LCMPDINTLVL1_bp 7 /* Low Byte Compare D Interrupt Level bit 1 position. */ - -#define TC2_LCMPCINTLVL_gm 0x30 /* Low Byte Compare C Interrupt Level group mask. */ -#define TC2_LCMPCINTLVL_gp 4 /* Low Byte Compare C Interrupt Level group position. */ -#define TC2_LCMPCINTLVL0_bm (1<<4) /* Low Byte Compare C Interrupt Level bit 0 mask. */ -#define TC2_LCMPCINTLVL0_bp 4 /* Low Byte Compare C Interrupt Level bit 0 position. */ -#define TC2_LCMPCINTLVL1_bm (1<<5) /* Low Byte Compare C Interrupt Level bit 1 mask. */ -#define TC2_LCMPCINTLVL1_bp 5 /* Low Byte Compare C Interrupt Level bit 1 position. */ - -#define TC2_LCMPBINTLVL_gm 0x0C /* Low Byte Compare B Interrupt Level group mask. */ -#define TC2_LCMPBINTLVL_gp 2 /* Low Byte Compare B Interrupt Level group position. */ -#define TC2_LCMPBINTLVL0_bm (1<<2) /* Low Byte Compare B Interrupt Level bit 0 mask. */ -#define TC2_LCMPBINTLVL0_bp 2 /* Low Byte Compare B Interrupt Level bit 0 position. */ -#define TC2_LCMPBINTLVL1_bm (1<<3) /* Low Byte Compare B Interrupt Level bit 1 mask. */ -#define TC2_LCMPBINTLVL1_bp 3 /* Low Byte Compare B Interrupt Level bit 1 position. */ - -#define TC2_LCMPAINTLVL_gm 0x03 /* Low Byte Compare A Interrupt Level group mask. */ -#define TC2_LCMPAINTLVL_gp 0 /* Low Byte Compare A Interrupt Level group position. */ -#define TC2_LCMPAINTLVL0_bm (1<<0) /* Low Byte Compare A Interrupt Level bit 0 mask. */ -#define TC2_LCMPAINTLVL0_bp 0 /* Low Byte Compare A Interrupt Level bit 0 position. */ -#define TC2_LCMPAINTLVL1_bm (1<<1) /* Low Byte Compare A Interrupt Level bit 1 mask. */ -#define TC2_LCMPAINTLVL1_bp 1 /* Low Byte Compare A Interrupt Level bit 1 position. */ - -/* TC2.CTRLF bit masks and bit positions */ -#define TC2_CMD_gm 0x0C /* Command group mask. */ -#define TC2_CMD_gp 2 /* Command group position. */ -#define TC2_CMD0_bm (1<<2) /* Command bit 0 mask. */ -#define TC2_CMD0_bp 2 /* Command bit 0 position. */ -#define TC2_CMD1_bm (1<<3) /* Command bit 1 mask. */ -#define TC2_CMD1_bp 3 /* Command bit 1 position. */ - -#define TC2_CMDEN_gm 0x03 /* Command Enable group mask. */ -#define TC2_CMDEN_gp 0 /* Command Enable group position. */ -#define TC2_CMDEN0_bm (1<<0) /* Command Enable bit 0 mask. */ -#define TC2_CMDEN0_bp 0 /* Command Enable bit 0 position. */ -#define TC2_CMDEN1_bm (1<<1) /* Command Enable bit 1 mask. */ -#define TC2_CMDEN1_bp 1 /* Command Enable bit 1 position. */ - -/* TC2.INTFLAGS bit masks and bit positions */ -#define TC2_LCMPDIF_bm 0x80 /* Low Byte Compare D Interrupt Flag bit mask. */ -#define TC2_LCMPDIF_bp 7 /* Low Byte Compare D Interrupt Flag bit position. */ - -#define TC2_LCMPCIF_bm 0x40 /* Low Byte Compare C Interrupt Flag bit mask. */ -#define TC2_LCMPCIF_bp 6 /* Low Byte Compare C Interrupt Flag bit position. */ - -#define TC2_LCMPBIF_bm 0x20 /* Low Byte Compare B Interrupt Flag bit mask. */ -#define TC2_LCMPBIF_bp 5 /* Low Byte Compare B Interrupt Flag bit position. */ - -#define TC2_LCMPAIF_bm 0x10 /* Low Byte Compare A Interrupt Flag bit mask. */ -#define TC2_LCMPAIF_bp 4 /* Low Byte Compare A Interrupt Flag bit position. */ - -#define TC2_HUNFIF_bm 0x02 /* High Byte Underflow Interrupt Flag bit mask. */ -#define TC2_HUNFIF_bp 1 /* High Byte Underflow Interrupt Flag bit position. */ - -#define TC2_LUNFIF_bm 0x01 /* Low Byte Underflow Interrupt Flag bit mask. */ -#define TC2_LUNFIF_bp 0 /* Low Byte Underflow Interrupt Flag bit position. */ - -/* AWEX - Timer/Counter Advanced Waveform Extension */ -/* AWEX.CTRL bit masks and bit positions */ -#define AWEX_PGM_bm 0x20 /* Pattern Generation Mode bit mask. */ -#define AWEX_PGM_bp 5 /* Pattern Generation Mode bit position. */ - -#define AWEX_CWCM_bm 0x10 /* Common Waveform Channel Mode bit mask. */ -#define AWEX_CWCM_bp 4 /* Common Waveform Channel Mode bit position. */ - -#define AWEX_DTICCDEN_bm 0x08 /* Dead Time Insertion Compare Channel D Enable bit mask. */ -#define AWEX_DTICCDEN_bp 3 /* Dead Time Insertion Compare Channel D Enable bit position. */ - -#define AWEX_DTICCCEN_bm 0x04 /* Dead Time Insertion Compare Channel C Enable bit mask. */ -#define AWEX_DTICCCEN_bp 2 /* Dead Time Insertion Compare Channel C Enable bit position. */ - -#define AWEX_DTICCBEN_bm 0x02 /* Dead Time Insertion Compare Channel B Enable bit mask. */ -#define AWEX_DTICCBEN_bp 1 /* Dead Time Insertion Compare Channel B Enable bit position. */ - -#define AWEX_DTICCAEN_bm 0x01 /* Dead Time Insertion Compare Channel A Enable bit mask. */ -#define AWEX_DTICCAEN_bp 0 /* Dead Time Insertion Compare Channel A Enable bit position. */ - -/* AWEX.FDCTRL bit masks and bit positions */ -#define AWEX_FDDBD_bm 0x10 /* Fault Detect on Disable Break Disable bit mask. */ -#define AWEX_FDDBD_bp 4 /* Fault Detect on Disable Break Disable bit position. */ - -#define AWEX_FDMODE_bm 0x04 /* Fault Detect Mode bit mask. */ -#define AWEX_FDMODE_bp 2 /* Fault Detect Mode bit position. */ - -#define AWEX_FDACT_gm 0x03 /* Fault Detect Action group mask. */ -#define AWEX_FDACT_gp 0 /* Fault Detect Action group position. */ -#define AWEX_FDACT0_bm (1<<0) /* Fault Detect Action bit 0 mask. */ -#define AWEX_FDACT0_bp 0 /* Fault Detect Action bit 0 position. */ -#define AWEX_FDACT1_bm (1<<1) /* Fault Detect Action bit 1 mask. */ -#define AWEX_FDACT1_bp 1 /* Fault Detect Action bit 1 position. */ - -/* AWEX.STATUS bit masks and bit positions */ -#define AWEX_FDF_bm 0x04 /* Fault Detect Flag bit mask. */ -#define AWEX_FDF_bp 2 /* Fault Detect Flag bit position. */ - -#define AWEX_DTHSBUFV_bm 0x02 /* Dead Time High Side Buffer Valid bit mask. */ -#define AWEX_DTHSBUFV_bp 1 /* Dead Time High Side Buffer Valid bit position. */ - -#define AWEX_DTLSBUFV_bm 0x01 /* Dead Time Low Side Buffer Valid bit mask. */ -#define AWEX_DTLSBUFV_bp 0 /* Dead Time Low Side Buffer Valid bit position. */ - -/* AWEX.STATUSSET bit masks and bit positions */ -/* AWEX_FDF Predefined. */ -/* AWEX_FDF Predefined. */ - -/* AWEX_DTHSBUFV Predefined. */ -/* AWEX_DTHSBUFV Predefined. */ - -/* AWEX_DTLSBUFV Predefined. */ -/* AWEX_DTLSBUFV Predefined. */ - -/* HIRES - Timer/Counter High-Resolution Extension */ -/* HIRES.CTRLA bit masks and bit positions */ -#define HIRES_HREN_gm 0x03 /* High Resolution Enable group mask. */ -#define HIRES_HREN_gp 0 /* High Resolution Enable group position. */ -#define HIRES_HREN0_bm (1<<0) /* High Resolution Enable bit 0 mask. */ -#define HIRES_HREN0_bp 0 /* High Resolution Enable bit 0 position. */ -#define HIRES_HREN1_bm (1<<1) /* High Resolution Enable bit 1 mask. */ -#define HIRES_HREN1_bp 1 /* High Resolution Enable bit 1 position. */ - -/* USART - Universal Asynchronous Receiver-Transmitter */ -/* USART.STATUS bit masks and bit positions */ -#define USART_RXCIF_bm 0x80 /* Receive Interrupt Flag bit mask. */ -#define USART_RXCIF_bp 7 /* Receive Interrupt Flag bit position. */ - -#define USART_TXCIF_bm 0x40 /* Transmit Interrupt Flag bit mask. */ -#define USART_TXCIF_bp 6 /* Transmit Interrupt Flag bit position. */ - -#define USART_DREIF_bm 0x20 /* Data Register Empty Flag bit mask. */ -#define USART_DREIF_bp 5 /* Data Register Empty Flag bit position. */ - -#define USART_FERR_bm 0x10 /* Frame Error bit mask. */ -#define USART_FERR_bp 4 /* Frame Error bit position. */ - -#define USART_BUFOVF_bm 0x08 /* Buffer Overflow bit mask. */ -#define USART_BUFOVF_bp 3 /* Buffer Overflow bit position. */ - -#define USART_PERR_bm 0x04 /* Parity Error bit mask. */ -#define USART_PERR_bp 2 /* Parity Error bit position. */ - -#define USART_RXB8_bm 0x01 /* Receive Bit 8 bit mask. */ -#define USART_RXB8_bp 0 /* Receive Bit 8 bit position. */ - -/* USART.CTRLA bit masks and bit positions */ -#define USART_RXCINTLVL_gm 0x30 /* Receive Interrupt Level group mask. */ -#define USART_RXCINTLVL_gp 4 /* Receive Interrupt Level group position. */ -#define USART_RXCINTLVL0_bm (1<<4) /* Receive Interrupt Level bit 0 mask. */ -#define USART_RXCINTLVL0_bp 4 /* Receive Interrupt Level bit 0 position. */ -#define USART_RXCINTLVL1_bm (1<<5) /* Receive Interrupt Level bit 1 mask. */ -#define USART_RXCINTLVL1_bp 5 /* Receive Interrupt Level bit 1 position. */ - -#define USART_TXCINTLVL_gm 0x0C /* Transmit Interrupt Level group mask. */ -#define USART_TXCINTLVL_gp 2 /* Transmit Interrupt Level group position. */ -#define USART_TXCINTLVL0_bm (1<<2) /* Transmit Interrupt Level bit 0 mask. */ -#define USART_TXCINTLVL0_bp 2 /* Transmit Interrupt Level bit 0 position. */ -#define USART_TXCINTLVL1_bm (1<<3) /* Transmit Interrupt Level bit 1 mask. */ -#define USART_TXCINTLVL1_bp 3 /* Transmit Interrupt Level bit 1 position. */ - -#define USART_DREINTLVL_gm 0x03 /* Data Register Empty Interrupt Level group mask. */ -#define USART_DREINTLVL_gp 0 /* Data Register Empty Interrupt Level group position. */ -#define USART_DREINTLVL0_bm (1<<0) /* Data Register Empty Interrupt Level bit 0 mask. */ -#define USART_DREINTLVL0_bp 0 /* Data Register Empty Interrupt Level bit 0 position. */ -#define USART_DREINTLVL1_bm (1<<1) /* Data Register Empty Interrupt Level bit 1 mask. */ -#define USART_DREINTLVL1_bp 1 /* Data Register Empty Interrupt Level bit 1 position. */ - -/* USART.CTRLB bit masks and bit positions */ -#define USART_RXEN_bm 0x10 /* Receiver Enable bit mask. */ -#define USART_RXEN_bp 4 /* Receiver Enable bit position. */ - -#define USART_TXEN_bm 0x08 /* Transmitter Enable bit mask. */ -#define USART_TXEN_bp 3 /* Transmitter Enable bit position. */ - -#define USART_CLK2X_bm 0x04 /* Double transmission speed bit mask. */ -#define USART_CLK2X_bp 2 /* Double transmission speed bit position. */ - -#define USART_MPCM_bm 0x02 /* Multi-processor Communication Mode bit mask. */ -#define USART_MPCM_bp 1 /* Multi-processor Communication Mode bit position. */ - -#define USART_TXB8_bm 0x01 /* Transmit bit 8 bit mask. */ -#define USART_TXB8_bp 0 /* Transmit bit 8 bit position. */ - -/* USART.CTRLC bit masks and bit positions */ -#define USART_CMODE_gm 0xC0 /* Communication Mode group mask. */ -#define USART_CMODE_gp 6 /* Communication Mode group position. */ -#define USART_CMODE0_bm (1<<6) /* Communication Mode bit 0 mask. */ -#define USART_CMODE0_bp 6 /* Communication Mode bit 0 position. */ -#define USART_CMODE1_bm (1<<7) /* Communication Mode bit 1 mask. */ -#define USART_CMODE1_bp 7 /* Communication Mode bit 1 position. */ - -#define USART_PMODE_gm 0x30 /* Parity Mode group mask. */ -#define USART_PMODE_gp 4 /* Parity Mode group position. */ -#define USART_PMODE0_bm (1<<4) /* Parity Mode bit 0 mask. */ -#define USART_PMODE0_bp 4 /* Parity Mode bit 0 position. */ -#define USART_PMODE1_bm (1<<5) /* Parity Mode bit 1 mask. */ -#define USART_PMODE1_bp 5 /* Parity Mode bit 1 position. */ - -#define USART_SBMODE_bm 0x08 /* Stop Bit Mode bit mask. */ -#define USART_SBMODE_bp 3 /* Stop Bit Mode bit position. */ - -#define USART_CHSIZE_gm 0x07 /* Character Size group mask. */ -#define USART_CHSIZE_gp 0 /* Character Size group position. */ -#define USART_CHSIZE0_bm (1<<0) /* Character Size bit 0 mask. */ -#define USART_CHSIZE0_bp 0 /* Character Size bit 0 position. */ -#define USART_CHSIZE1_bm (1<<1) /* Character Size bit 1 mask. */ -#define USART_CHSIZE1_bp 1 /* Character Size bit 1 position. */ -#define USART_CHSIZE2_bm (1<<2) /* Character Size bit 2 mask. */ -#define USART_CHSIZE2_bp 2 /* Character Size bit 2 position. */ - -/* USART.BAUDCTRLA bit masks and bit positions */ -#define USART_BSEL_gm 0xFF /* Baud Rate Selection Bits [7:0] group mask. */ -#define USART_BSEL_gp 0 /* Baud Rate Selection Bits [7:0] group position. */ -#define USART_BSEL0_bm (1<<0) /* Baud Rate Selection Bits [7:0] bit 0 mask. */ -#define USART_BSEL0_bp 0 /* Baud Rate Selection Bits [7:0] bit 0 position. */ -#define USART_BSEL1_bm (1<<1) /* Baud Rate Selection Bits [7:0] bit 1 mask. */ -#define USART_BSEL1_bp 1 /* Baud Rate Selection Bits [7:0] bit 1 position. */ -#define USART_BSEL2_bm (1<<2) /* Baud Rate Selection Bits [7:0] bit 2 mask. */ -#define USART_BSEL2_bp 2 /* Baud Rate Selection Bits [7:0] bit 2 position. */ -#define USART_BSEL3_bm (1<<3) /* Baud Rate Selection Bits [7:0] bit 3 mask. */ -#define USART_BSEL3_bp 3 /* Baud Rate Selection Bits [7:0] bit 3 position. */ -#define USART_BSEL4_bm (1<<4) /* Baud Rate Selection Bits [7:0] bit 4 mask. */ -#define USART_BSEL4_bp 4 /* Baud Rate Selection Bits [7:0] bit 4 position. */ -#define USART_BSEL5_bm (1<<5) /* Baud Rate Selection Bits [7:0] bit 5 mask. */ -#define USART_BSEL5_bp 5 /* Baud Rate Selection Bits [7:0] bit 5 position. */ -#define USART_BSEL6_bm (1<<6) /* Baud Rate Selection Bits [7:0] bit 6 mask. */ -#define USART_BSEL6_bp 6 /* Baud Rate Selection Bits [7:0] bit 6 position. */ -#define USART_BSEL7_bm (1<<7) /* Baud Rate Selection Bits [7:0] bit 7 mask. */ -#define USART_BSEL7_bp 7 /* Baud Rate Selection Bits [7:0] bit 7 position. */ - -/* USART.BAUDCTRLB bit masks and bit positions */ -#define USART_BSCALE_gm 0xF0 /* Baud Rate Scale group mask. */ -#define USART_BSCALE_gp 4 /* Baud Rate Scale group position. */ -#define USART_BSCALE0_bm (1<<4) /* Baud Rate Scale bit 0 mask. */ -#define USART_BSCALE0_bp 4 /* Baud Rate Scale bit 0 position. */ -#define USART_BSCALE1_bm (1<<5) /* Baud Rate Scale bit 1 mask. */ -#define USART_BSCALE1_bp 5 /* Baud Rate Scale bit 1 position. */ -#define USART_BSCALE2_bm (1<<6) /* Baud Rate Scale bit 2 mask. */ -#define USART_BSCALE2_bp 6 /* Baud Rate Scale bit 2 position. */ -#define USART_BSCALE3_bm (1<<7) /* Baud Rate Scale bit 3 mask. */ -#define USART_BSCALE3_bp 7 /* Baud Rate Scale bit 3 position. */ - -/* USART_BSEL Predefined. */ -/* USART_BSEL Predefined. */ - -/* SPI - Serial Peripheral Interface */ -/* SPI.CTRL bit masks and bit positions */ -#define SPI_CLK2X_bm 0x80 /* Enable Double Speed bit mask. */ -#define SPI_CLK2X_bp 7 /* Enable Double Speed bit position. */ - -#define SPI_ENABLE_bm 0x40 /* Enable Module bit mask. */ -#define SPI_ENABLE_bp 6 /* Enable Module bit position. */ - -#define SPI_DORD_bm 0x20 /* Data Order Setting bit mask. */ -#define SPI_DORD_bp 5 /* Data Order Setting bit position. */ - -#define SPI_MASTER_bm 0x10 /* Master Operation Enable bit mask. */ -#define SPI_MASTER_bp 4 /* Master Operation Enable bit position. */ - -#define SPI_MODE_gm 0x0C /* SPI Mode group mask. */ -#define SPI_MODE_gp 2 /* SPI Mode group position. */ -#define SPI_MODE0_bm (1<<2) /* SPI Mode bit 0 mask. */ -#define SPI_MODE0_bp 2 /* SPI Mode bit 0 position. */ -#define SPI_MODE1_bm (1<<3) /* SPI Mode bit 1 mask. */ -#define SPI_MODE1_bp 3 /* SPI Mode bit 1 position. */ - -#define SPI_PRESCALER_gm 0x03 /* Prescaler group mask. */ -#define SPI_PRESCALER_gp 0 /* Prescaler group position. */ -#define SPI_PRESCALER0_bm (1<<0) /* Prescaler bit 0 mask. */ -#define SPI_PRESCALER0_bp 0 /* Prescaler bit 0 position. */ -#define SPI_PRESCALER1_bm (1<<1) /* Prescaler bit 1 mask. */ -#define SPI_PRESCALER1_bp 1 /* Prescaler bit 1 position. */ - -/* SPI.INTCTRL bit masks and bit positions */ -#define SPI_INTLVL_gm 0x03 /* Interrupt level group mask. */ -#define SPI_INTLVL_gp 0 /* Interrupt level group position. */ -#define SPI_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */ -#define SPI_INTLVL0_bp 0 /* Interrupt level bit 0 position. */ -#define SPI_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */ -#define SPI_INTLVL1_bp 1 /* Interrupt level bit 1 position. */ - -/* SPI.STATUS bit masks and bit positions */ -#define SPI_IF_bm 0x80 /* Interrupt Flag bit mask. */ -#define SPI_IF_bp 7 /* Interrupt Flag bit position. */ - -#define SPI_WRCOL_bm 0x40 /* Write Collision bit mask. */ -#define SPI_WRCOL_bp 6 /* Write Collision bit position. */ - -/* IRCOM - IR Communication Module */ -/* IRCOM.CTRL bit masks and bit positions */ -#define IRCOM_EVSEL_gm 0x0F /* Event Channel Select group mask. */ -#define IRCOM_EVSEL_gp 0 /* Event Channel Select group position. */ -#define IRCOM_EVSEL0_bm (1<<0) /* Event Channel Select bit 0 mask. */ -#define IRCOM_EVSEL0_bp 0 /* Event Channel Select bit 0 position. */ -#define IRCOM_EVSEL1_bm (1<<1) /* Event Channel Select bit 1 mask. */ -#define IRCOM_EVSEL1_bp 1 /* Event Channel Select bit 1 position. */ -#define IRCOM_EVSEL2_bm (1<<2) /* Event Channel Select bit 2 mask. */ -#define IRCOM_EVSEL2_bp 2 /* Event Channel Select bit 2 position. */ -#define IRCOM_EVSEL3_bm (1<<3) /* Event Channel Select bit 3 mask. */ -#define IRCOM_EVSEL3_bp 3 /* Event Channel Select bit 3 position. */ - -/* FUSE - Fuses and Lockbits */ -/* NVM_FUSES.FUSEBYTE1 bit masks and bit positions */ -#define NVM_FUSES_WDWP_gm 0xF0 /* Watchdog Window Timeout Period group mask. */ -#define NVM_FUSES_WDWP_gp 4 /* Watchdog Window Timeout Period group position. */ -#define NVM_FUSES_WDWP0_bm (1<<4) /* Watchdog Window Timeout Period bit 0 mask. */ -#define NVM_FUSES_WDWP0_bp 4 /* Watchdog Window Timeout Period bit 0 position. */ -#define NVM_FUSES_WDWP1_bm (1<<5) /* Watchdog Window Timeout Period bit 1 mask. */ -#define NVM_FUSES_WDWP1_bp 5 /* Watchdog Window Timeout Period bit 1 position. */ -#define NVM_FUSES_WDWP2_bm (1<<6) /* Watchdog Window Timeout Period bit 2 mask. */ -#define NVM_FUSES_WDWP2_bp 6 /* Watchdog Window Timeout Period bit 2 position. */ -#define NVM_FUSES_WDWP3_bm (1<<7) /* Watchdog Window Timeout Period bit 3 mask. */ -#define NVM_FUSES_WDWP3_bp 7 /* Watchdog Window Timeout Period bit 3 position. */ - -#define NVM_FUSES_WDP_gm 0x0F /* Watchdog Timeout Period group mask. */ -#define NVM_FUSES_WDP_gp 0 /* Watchdog Timeout Period group position. */ -#define NVM_FUSES_WDP0_bm (1<<0) /* Watchdog Timeout Period bit 0 mask. */ -#define NVM_FUSES_WDP0_bp 0 /* Watchdog Timeout Period bit 0 position. */ -#define NVM_FUSES_WDP1_bm (1<<1) /* Watchdog Timeout Period bit 1 mask. */ -#define NVM_FUSES_WDP1_bp 1 /* Watchdog Timeout Period bit 1 position. */ -#define NVM_FUSES_WDP2_bm (1<<2) /* Watchdog Timeout Period bit 2 mask. */ -#define NVM_FUSES_WDP2_bp 2 /* Watchdog Timeout Period bit 2 position. */ -#define NVM_FUSES_WDP3_bm (1<<3) /* Watchdog Timeout Period bit 3 mask. */ -#define NVM_FUSES_WDP3_bp 3 /* Watchdog Timeout Period bit 3 position. */ - -/* NVM_FUSES.FUSEBYTE2 bit masks and bit positions */ -#define NVM_FUSES_BOOTRST_bm 0x40 /* Boot Loader Section Reset Vector bit mask. */ -#define NVM_FUSES_BOOTRST_bp 6 /* Boot Loader Section Reset Vector bit position. */ - -#define NVM_FUSES_TOSCSEL_bm 0x20 /* Timer Oscillator pin location bit mask. */ -#define NVM_FUSES_TOSCSEL_bp 5 /* Timer Oscillator pin location bit position. */ - -#define NVM_FUSES_BODPD_gm 0x03 /* BOD Operation in Power-Down Mode group mask. */ -#define NVM_FUSES_BODPD_gp 0 /* BOD Operation in Power-Down Mode group position. */ -#define NVM_FUSES_BODPD0_bm (1<<0) /* BOD Operation in Power-Down Mode bit 0 mask. */ -#define NVM_FUSES_BODPD0_bp 0 /* BOD Operation in Power-Down Mode bit 0 position. */ -#define NVM_FUSES_BODPD1_bm (1<<1) /* BOD Operation in Power-Down Mode bit 1 mask. */ -#define NVM_FUSES_BODPD1_bp 1 /* BOD Operation in Power-Down Mode bit 1 position. */ - -/* NVM_FUSES.FUSEBYTE4 bit masks and bit positions */ -#define NVM_FUSES_RSTDISBL_bm 0x10 /* External Reset Disable bit mask. */ -#define NVM_FUSES_RSTDISBL_bp 4 /* External Reset Disable bit position. */ - -#define NVM_FUSES_SUT_gm 0x0C /* Start-up Time group mask. */ -#define NVM_FUSES_SUT_gp 2 /* Start-up Time group position. */ -#define NVM_FUSES_SUT0_bm (1<<2) /* Start-up Time bit 0 mask. */ -#define NVM_FUSES_SUT0_bp 2 /* Start-up Time bit 0 position. */ -#define NVM_FUSES_SUT1_bm (1<<3) /* Start-up Time bit 1 mask. */ -#define NVM_FUSES_SUT1_bp 3 /* Start-up Time bit 1 position. */ - -#define NVM_FUSES_WDLOCK_bm 0x02 /* Watchdog Timer Lock bit mask. */ -#define NVM_FUSES_WDLOCK_bp 1 /* Watchdog Timer Lock bit position. */ - -/* NVM_FUSES.FUSEBYTE5 bit masks and bit positions */ -#define NVM_FUSES_BODACT_gm 0x30 /* BOD Operation in Active Mode group mask. */ -#define NVM_FUSES_BODACT_gp 4 /* BOD Operation in Active Mode group position. */ -#define NVM_FUSES_BODACT0_bm (1<<4) /* BOD Operation in Active Mode bit 0 mask. */ -#define NVM_FUSES_BODACT0_bp 4 /* BOD Operation in Active Mode bit 0 position. */ -#define NVM_FUSES_BODACT1_bm (1<<5) /* BOD Operation in Active Mode bit 1 mask. */ -#define NVM_FUSES_BODACT1_bp 5 /* BOD Operation in Active Mode bit 1 position. */ - -#define NVM_FUSES_EESAVE_bm 0x08 /* Preserve EEPROM Through Chip Erase bit mask. */ -#define NVM_FUSES_EESAVE_bp 3 /* Preserve EEPROM Through Chip Erase bit position. */ - -#define NVM_FUSES_BODLVL_gm 0x07 /* Brownout Detection Voltage Level group mask. */ -#define NVM_FUSES_BODLVL_gp 0 /* Brownout Detection Voltage Level group position. */ -#define NVM_FUSES_BODLVL0_bm (1<<0) /* Brownout Detection Voltage Level bit 0 mask. */ -#define NVM_FUSES_BODLVL0_bp 0 /* Brownout Detection Voltage Level bit 0 position. */ -#define NVM_FUSES_BODLVL1_bm (1<<1) /* Brownout Detection Voltage Level bit 1 mask. */ -#define NVM_FUSES_BODLVL1_bp 1 /* Brownout Detection Voltage Level bit 1 position. */ -#define NVM_FUSES_BODLVL2_bm (1<<2) /* Brownout Detection Voltage Level bit 2 mask. */ -#define NVM_FUSES_BODLVL2_bp 2 /* Brownout Detection Voltage Level bit 2 position. */ - -/* LOCKBIT - Fuses and Lockbits */ -/* NVM_LOCKBITS.LOCKBITS bit masks and bit positions */ -#define NVM_LOCKBITS_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ -#define NVM_LOCKBITS_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ -#define NVM_LOCKBITS_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ -#define NVM_LOCKBITS_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ -#define NVM_LOCKBITS_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ -#define NVM_LOCKBITS_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ - -#define NVM_LOCKBITS_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ -#define NVM_LOCKBITS_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ -#define NVM_LOCKBITS_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ -#define NVM_LOCKBITS_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ -#define NVM_LOCKBITS_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ -#define NVM_LOCKBITS_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ - -#define NVM_LOCKBITS_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ -#define NVM_LOCKBITS_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ -#define NVM_LOCKBITS_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ -#define NVM_LOCKBITS_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ -#define NVM_LOCKBITS_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ -#define NVM_LOCKBITS_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ - -#define NVM_LOCKBITS_LB_gm 0x03 /* Lock Bits group mask. */ -#define NVM_LOCKBITS_LB_gp 0 /* Lock Bits group position. */ -#define NVM_LOCKBITS_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ -#define NVM_LOCKBITS_LB0_bp 0 /* Lock Bits bit 0 position. */ -#define NVM_LOCKBITS_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ -#define NVM_LOCKBITS_LB1_bp 1 /* Lock Bits bit 1 position. */ - - - -// Generic Port Pins - -#define PIN0_bm 0x01 -#define PIN0_bp 0 -#define PIN1_bm 0x02 -#define PIN1_bp 1 -#define PIN2_bm 0x04 -#define PIN2_bp 2 -#define PIN3_bm 0x08 -#define PIN3_bp 3 -#define PIN4_bm 0x10 -#define PIN4_bp 4 -#define PIN5_bm 0x20 -#define PIN5_bp 5 -#define PIN6_bm 0x40 -#define PIN6_bp 6 -#define PIN7_bm 0x80 -#define PIN7_bp 7 - -/* ========== Interrupt Vector Definitions ========== */ -/* Vector 0 is the reset vector */ - -/* OSC interrupt vectors */ -#define OSC_OSCF_vect_num 1 -#define OSC_OSCF_vect _VECTOR(1) /* Oscillator Failure Interrupt (NMI) */ - -/* PORTC interrupt vectors */ -#define PORTC_INT0_vect_num 2 -#define PORTC_INT0_vect _VECTOR(2) /* External Interrupt 0 */ -#define PORTC_INT1_vect_num 3 -#define PORTC_INT1_vect _VECTOR(3) /* External Interrupt 1 */ - -/* PORTR interrupt vectors */ -#define PORTR_INT0_vect_num 4 -#define PORTR_INT0_vect _VECTOR(4) /* External Interrupt 0 */ -#define PORTR_INT1_vect_num 5 -#define PORTR_INT1_vect _VECTOR(5) /* External Interrupt 1 */ - -/* DMA interrupt vectors */ -#define DMA_CH0_vect_num 6 -#define DMA_CH0_vect _VECTOR(6) /* Channel 0 Interrupt */ -#define DMA_CH1_vect_num 7 -#define DMA_CH1_vect _VECTOR(7) /* Channel 1 Interrupt */ -#define DMA_CH2_vect_num 8 -#define DMA_CH2_vect _VECTOR(8) /* Channel 2 Interrupt */ -#define DMA_CH3_vect_num 9 -#define DMA_CH3_vect _VECTOR(9) /* Channel 3 Interrupt */ - -/* RTC interrupt vectors */ -#define RTC_OVF_vect_num 10 -#define RTC_OVF_vect _VECTOR(10) /* Overflow Interrupt */ -#define RTC_COMP_vect_num 11 -#define RTC_COMP_vect _VECTOR(11) /* Compare Interrupt */ - -/* TWIC interrupt vectors */ -#define TWIC_TWIS_vect_num 12 -#define TWIC_TWIS_vect _VECTOR(12) /* TWI Slave Interrupt */ -#define TWIC_TWIM_vect_num 13 -#define TWIC_TWIM_vect _VECTOR(13) /* TWI Master Interrupt */ - -/* TCC0 interrupt vectors */ -#define TCC0_OVF_vect_num 14 -#define TCC0_OVF_vect _VECTOR(14) /* Overflow Interrupt */ - -/* TCC2 interrupt vectors */ -#define TCC2_LUNF_vect_num 14 -#define TCC2_LUNF_vect _VECTOR(14) /* Low Byte Underflow Interrupt */ - -/* TCC0 interrupt vectors */ -#define TCC0_ERR_vect_num 15 -#define TCC0_ERR_vect _VECTOR(15) /* Error Interrupt */ - -/* TCC2 interrupt vectors */ -#define TCC2_HUNF_vect_num 15 -#define TCC2_HUNF_vect _VECTOR(15) /* High Byte Underflow Interrupt */ - -/* TCC0 interrupt vectors */ -#define TCC0_CCA_vect_num 16 -#define TCC0_CCA_vect _VECTOR(16) /* Compare or Capture A Interrupt */ - -/* TCC2 interrupt vectors */ -#define TCC2_LCMPA_vect_num 16 -#define TCC2_LCMPA_vect _VECTOR(16) /* Low Byte Compare A Interrupt */ - -/* TCC0 interrupt vectors */ -#define TCC0_CCB_vect_num 17 -#define TCC0_CCB_vect _VECTOR(17) /* Compare or Capture B Interrupt */ - -/* TCC2 interrupt vectors */ -#define TCC2_LCMPB_vect_num 17 -#define TCC2_LCMPB_vect _VECTOR(17) /* Low Byte Compare B Interrupt */ - -/* TCC0 interrupt vectors */ -#define TCC0_CCC_vect_num 18 -#define TCC0_CCC_vect _VECTOR(18) /* Compare or Capture C Interrupt */ - -/* TCC2 interrupt vectors */ -#define TCC2_LCMPC_vect_num 18 -#define TCC2_LCMPC_vect _VECTOR(18) /* Low Byte Compare C Interrupt */ - -/* TCC0 interrupt vectors */ -#define TCC0_CCD_vect_num 19 -#define TCC0_CCD_vect _VECTOR(19) /* Compare or Capture D Interrupt */ - -/* TCC2 interrupt vectors */ -#define TCC2_LCMPD_vect_num 19 -#define TCC2_LCMPD_vect _VECTOR(19) /* Low Byte Compare D Interrupt */ - -/* TCC1 interrupt vectors */ -#define TCC1_OVF_vect_num 20 -#define TCC1_OVF_vect _VECTOR(20) /* Overflow Interrupt */ -#define TCC1_ERR_vect_num 21 -#define TCC1_ERR_vect _VECTOR(21) /* Error Interrupt */ -#define TCC1_CCA_vect_num 22 -#define TCC1_CCA_vect _VECTOR(22) /* Compare or Capture A Interrupt */ -#define TCC1_CCB_vect_num 23 -#define TCC1_CCB_vect _VECTOR(23) /* Compare or Capture B Interrupt */ - -/* SPIC interrupt vectors */ -#define SPIC_INT_vect_num 24 -#define SPIC_INT_vect _VECTOR(24) /* SPI Interrupt */ - -/* USARTC0 interrupt vectors */ -#define USARTC0_RXC_vect_num 25 -#define USARTC0_RXC_vect _VECTOR(25) /* Reception Complete Interrupt */ -#define USARTC0_DRE_vect_num 26 -#define USARTC0_DRE_vect _VECTOR(26) /* Data Register Empty Interrupt */ -#define USARTC0_TXC_vect_num 27 -#define USARTC0_TXC_vect _VECTOR(27) /* Transmission Complete Interrupt */ - -/* USARTC1 interrupt vectors */ -#define USARTC1_RXC_vect_num 28 -#define USARTC1_RXC_vect _VECTOR(28) /* Reception Complete Interrupt */ -#define USARTC1_DRE_vect_num 29 -#define USARTC1_DRE_vect _VECTOR(29) /* Data Register Empty Interrupt */ -#define USARTC1_TXC_vect_num 30 -#define USARTC1_TXC_vect _VECTOR(30) /* Transmission Complete Interrupt */ - -/* AES interrupt vectors */ -#define AES_INT_vect_num 31 -#define AES_INT_vect _VECTOR(31) /* AES Interrupt */ - -/* NVM interrupt vectors */ -#define NVM_EE_vect_num 32 -#define NVM_EE_vect _VECTOR(32) /* EE Interrupt */ -#define NVM_SPM_vect_num 33 -#define NVM_SPM_vect _VECTOR(33) /* SPM Interrupt */ - -/* PORTB interrupt vectors */ -#define PORTB_INT0_vect_num 34 -#define PORTB_INT0_vect _VECTOR(34) /* External Interrupt 0 */ -#define PORTB_INT1_vect_num 35 -#define PORTB_INT1_vect _VECTOR(35) /* External Interrupt 1 */ - -/* PORTE interrupt vectors */ -#define PORTE_INT0_vect_num 43 -#define PORTE_INT0_vect _VECTOR(43) /* External Interrupt 0 */ -#define PORTE_INT1_vect_num 44 -#define PORTE_INT1_vect _VECTOR(44) /* External Interrupt 1 */ - -/* TWIE interrupt vectors */ -#define TWIE_TWIS_vect_num 45 -#define TWIE_TWIS_vect _VECTOR(45) /* TWI Slave Interrupt */ -#define TWIE_TWIM_vect_num 46 -#define TWIE_TWIM_vect _VECTOR(46) /* TWI Master Interrupt */ - -/* TCE0 interrupt vectors */ -#define TCE0_OVF_vect_num 47 -#define TCE0_OVF_vect _VECTOR(47) /* Overflow Interrupt */ -#define TCE0_ERR_vect_num 48 -#define TCE0_ERR_vect _VECTOR(48) /* Error Interrupt */ -#define TCE0_CCA_vect_num 49 -#define TCE0_CCA_vect _VECTOR(49) /* Compare or Capture A Interrupt */ -#define TCE0_CCB_vect_num 50 -#define TCE0_CCB_vect _VECTOR(50) /* Compare or Capture B Interrupt */ -#define TCE0_CCC_vect_num 51 -#define TCE0_CCC_vect _VECTOR(51) /* Compare or Capture C Interrupt */ -#define TCE0_CCD_vect_num 52 -#define TCE0_CCD_vect _VECTOR(52) /* Compare or Capture D Interrupt */ - -/* USARTE0 interrupt vectors */ -#define USARTE0_RXC_vect_num 58 -#define USARTE0_RXC_vect _VECTOR(58) /* Reception Complete Interrupt */ -#define USARTE0_DRE_vect_num 59 -#define USARTE0_DRE_vect _VECTOR(59) /* Data Register Empty Interrupt */ -#define USARTE0_TXC_vect_num 60 -#define USARTE0_TXC_vect _VECTOR(60) /* Transmission Complete Interrupt */ - -/* PORTD interrupt vectors */ -#define PORTD_INT0_vect_num 64 -#define PORTD_INT0_vect _VECTOR(64) /* External Interrupt 0 */ -#define PORTD_INT1_vect_num 65 -#define PORTD_INT1_vect _VECTOR(65) /* External Interrupt 1 */ - -/* PORTA interrupt vectors */ -#define PORTA_INT0_vect_num 66 -#define PORTA_INT0_vect _VECTOR(66) /* External Interrupt 0 */ -#define PORTA_INT1_vect_num 67 -#define PORTA_INT1_vect _VECTOR(67) /* External Interrupt 1 */ - -/* ACA interrupt vectors */ -#define ACA_AC0_vect_num 68 -#define ACA_AC0_vect _VECTOR(68) /* AC0 Interrupt */ -#define ACA_AC1_vect_num 69 -#define ACA_AC1_vect _VECTOR(69) /* AC1 Interrupt */ -#define ACA_ACW_vect_num 70 -#define ACA_ACW_vect _VECTOR(70) /* ACW Window Mode Interrupt */ - -/* ADCA interrupt vectors */ -#define ADCA_CH0_vect_num 71 -#define ADCA_CH0_vect _VECTOR(71) /* Interrupt 0 */ -#define ADCA_CH1_vect_num 72 -#define ADCA_CH1_vect _VECTOR(72) /* Interrupt 1 */ -#define ADCA_CH2_vect_num 73 -#define ADCA_CH2_vect _VECTOR(73) /* Interrupt 2 */ -#define ADCA_CH3_vect_num 74 -#define ADCA_CH3_vect _VECTOR(74) /* Interrupt 3 */ - -/* TCD0 interrupt vectors */ -#define TCD0_OVF_vect_num 77 -#define TCD0_OVF_vect _VECTOR(77) /* Overflow Interrupt */ - -/* TCD2 interrupt vectors */ -#define TCD2_LUNF_vect_num 77 -#define TCD2_LUNF_vect _VECTOR(77) /* Low Byte Underflow Interrupt */ - -/* TCD0 interrupt vectors */ -#define TCD0_ERR_vect_num 78 -#define TCD0_ERR_vect _VECTOR(78) /* Error Interrupt */ - -/* TCD2 interrupt vectors */ -#define TCD2_HUNF_vect_num 78 -#define TCD2_HUNF_vect _VECTOR(78) /* High Byte Underflow Interrupt */ - -/* TCD0 interrupt vectors */ -#define TCD0_CCA_vect_num 79 -#define TCD0_CCA_vect _VECTOR(79) /* Compare or Capture A Interrupt */ - -/* TCD2 interrupt vectors */ -#define TCD2_LCMPA_vect_num 79 -#define TCD2_LCMPA_vect _VECTOR(79) /* Low Byte Compare A Interrupt */ - -/* TCD0 interrupt vectors */ -#define TCD0_CCB_vect_num 80 -#define TCD0_CCB_vect _VECTOR(80) /* Compare or Capture B Interrupt */ - -/* TCD2 interrupt vectors */ -#define TCD2_LCMPB_vect_num 80 -#define TCD2_LCMPB_vect _VECTOR(80) /* Low Byte Compare B Interrupt */ - -/* TCD0 interrupt vectors */ -#define TCD0_CCC_vect_num 81 -#define TCD0_CCC_vect _VECTOR(81) /* Compare or Capture C Interrupt */ - -/* TCD2 interrupt vectors */ -#define TCD2_LCMPC_vect_num 81 -#define TCD2_LCMPC_vect _VECTOR(81) /* Low Byte Compare C Interrupt */ - -/* TCD0 interrupt vectors */ -#define TCD0_CCD_vect_num 82 -#define TCD0_CCD_vect _VECTOR(82) /* Compare or Capture D Interrupt */ - -/* TCD2 interrupt vectors */ -#define TCD2_LCMPD_vect_num 82 -#define TCD2_LCMPD_vect _VECTOR(82) /* Low Byte Compare D Interrupt */ - -/* TCD1 interrupt vectors */ -#define TCD1_OVF_vect_num 83 -#define TCD1_OVF_vect _VECTOR(83) /* Overflow Interrupt */ -#define TCD1_ERR_vect_num 84 -#define TCD1_ERR_vect _VECTOR(84) /* Error Interrupt */ -#define TCD1_CCA_vect_num 85 -#define TCD1_CCA_vect _VECTOR(85) /* Compare or Capture A Interrupt */ -#define TCD1_CCB_vect_num 86 -#define TCD1_CCB_vect _VECTOR(86) /* Compare or Capture B Interrupt */ - -/* SPID interrupt vectors */ -#define SPID_INT_vect_num 87 -#define SPID_INT_vect _VECTOR(87) /* SPI Interrupt */ - -/* USARTD0 interrupt vectors */ -#define USARTD0_RXC_vect_num 88 -#define USARTD0_RXC_vect _VECTOR(88) /* Reception Complete Interrupt */ -#define USARTD0_DRE_vect_num 89 -#define USARTD0_DRE_vect _VECTOR(89) /* Data Register Empty Interrupt */ -#define USARTD0_TXC_vect_num 90 -#define USARTD0_TXC_vect _VECTOR(90) /* Transmission Complete Interrupt */ - -/* USARTD1 interrupt vectors */ -#define USARTD1_RXC_vect_num 91 -#define USARTD1_RXC_vect _VECTOR(91) /* Reception Complete Interrupt */ -#define USARTD1_DRE_vect_num 92 -#define USARTD1_DRE_vect _VECTOR(92) /* Data Register Empty Interrupt */ -#define USARTD1_TXC_vect_num 93 -#define USARTD1_TXC_vect _VECTOR(93) /* Transmission Complete Interrupt */ - -/* USB interrupt vectors */ -#define USB_BUSEVENT_vect_num 125 -#define USB_BUSEVENT_vect _VECTOR(125) /* SOF, suspend, resume, reset bus event interrupts, crc, underflow, overflow and stall error interrupts */ -#define USB_TRNCOMPL_vect_num 126 -#define USB_TRNCOMPL_vect _VECTOR(126) /* Transaction complete interrupt */ - -#define _VECTOR_SIZE 4 /* Size of individual vector. */ -#define _VECTORS_SIZE (127 * _VECTOR_SIZE) - - -/* ========== Constants ========== */ - -#define PROGMEM_START (0x0000) -#define PROGMEM_SIZE (36864) -#define PROGMEM_END (PROGMEM_START + PROGMEM_SIZE - 1) - -#define APP_SECTION_START (0x0000) -#define APP_SECTION_SIZE (32768) -#define APP_SECTION_PAGE_SIZE (256) -#define APP_SECTION_END (APP_SECTION_START + APP_SECTION_SIZE - 1) - -#define APPTABLE_SECTION_START (0x7000) -#define APPTABLE_SECTION_SIZE (4096) -#define APPTABLE_SECTION_PAGE_SIZE (256) -#define APPTABLE_SECTION_END (APPTABLE_SECTION_START + APPTABLE_SECTION_SIZE - 1) - -#define BOOT_SECTION_START (0x8000) -#define BOOT_SECTION_SIZE (4096) -#define BOOT_SECTION_PAGE_SIZE (256) -#define BOOT_SECTION_END (BOOT_SECTION_START + BOOT_SECTION_SIZE - 1) - -#define DATAMEM_START (0x0000) -#define DATAMEM_SIZE (12288) -#define DATAMEM_END (DATAMEM_START + DATAMEM_SIZE - 1) - -#define IO_START (0x0000) -#define IO_SIZE (4096) -#define IO_PAGE_SIZE (0) -#define IO_END (IO_START + IO_SIZE - 1) - -#define MAPPED_EEPROM_START (0x1000) -#define MAPPED_EEPROM_SIZE (1024) -#define MAPPED_EEPROM_PAGE_SIZE (0) -#define MAPPED_EEPROM_END (MAPPED_EEPROM_START + MAPPED_EEPROM_SIZE - 1) - -#define INTERNAL_SRAM_START (0x2000) -#define INTERNAL_SRAM_SIZE (4096) -#define INTERNAL_SRAM_PAGE_SIZE (0) -#define INTERNAL_SRAM_END (INTERNAL_SRAM_START + INTERNAL_SRAM_SIZE - 1) - -#define EEPROM_START (0x0000) -#define EEPROM_SIZE (1024) -#define EEPROM_PAGE_SIZE (32) -#define EEPROM_END (EEPROM_START + EEPROM_SIZE - 1) - -#define SIGNATURES_START (0x0000) -#define SIGNATURES_SIZE (3) -#define SIGNATURES_PAGE_SIZE (0) -#define SIGNATURES_END (SIGNATURES_START + SIGNATURES_SIZE - 1) - -#define FUSES_START (0x0000) -#define FUSES_SIZE (6) -#define FUSES_PAGE_SIZE (0) -#define FUSES_END (FUSES_START + FUSES_SIZE - 1) - -#define LOCKBITS_START (0x0000) -#define LOCKBITS_SIZE (1) -#define LOCKBITS_PAGE_SIZE (0) -#define LOCKBITS_END (LOCKBITS_START + LOCKBITS_SIZE - 1) - -#define USER_SIGNATURES_START (0x0000) -#define USER_SIGNATURES_SIZE (256) -#define USER_SIGNATURES_PAGE_SIZE (256) -#define USER_SIGNATURES_END (USER_SIGNATURES_START + USER_SIGNATURES_SIZE - 1) - -#define PROD_SIGNATURES_START (0x0000) -#define PROD_SIGNATURES_SIZE (52) -#define PROD_SIGNATURES_PAGE_SIZE (256) -#define PROD_SIGNATURES_END (PROD_SIGNATURES_START + PROD_SIGNATURES_SIZE - 1) - -#define FLASHSTART PROGMEM_START -#define FLASHEND PROGMEM_END -#define SPM_PAGESIZE 256 -#define RAMSTART INTERNAL_SRAM_START -#define RAMSIZE INTERNAL_SRAM_SIZE -#define RAMEND INTERNAL_SRAM_END -#define E2END EEPROM_END -#define E2PAGESIZE EEPROM_PAGE_SIZE - - -/* ========== Fuses ========== */ -#define FUSE_MEMORY_SIZE 6 - -/* Fuse Byte 0 Reserved */ - -/* Fuse Byte 1 */ -#define FUSE_WDP0 (unsigned char)~_BV(0) /* Watchdog Timeout Period Bit 0 */ -#define FUSE_WDP1 (unsigned char)~_BV(1) /* Watchdog Timeout Period Bit 1 */ -#define FUSE_WDP2 (unsigned char)~_BV(2) /* Watchdog Timeout Period Bit 2 */ -#define FUSE_WDP3 (unsigned char)~_BV(3) /* Watchdog Timeout Period Bit 3 */ -#define FUSE_WDWP0 (unsigned char)~_BV(4) /* Watchdog Window Timeout Period Bit 0 */ -#define FUSE_WDWP1 (unsigned char)~_BV(5) /* Watchdog Window Timeout Period Bit 1 */ -#define FUSE_WDWP2 (unsigned char)~_BV(6) /* Watchdog Window Timeout Period Bit 2 */ -#define FUSE_WDWP3 (unsigned char)~_BV(7) /* Watchdog Window Timeout Period Bit 3 */ -#define FUSE1_DEFAULT (0xFF) - -/* Fuse Byte 2 */ -#define FUSE_BODPD0 (unsigned char)~_BV(0) /* BOD Operation in Power-Down Mode Bit 0 */ -#define FUSE_BODPD1 (unsigned char)~_BV(1) /* BOD Operation in Power-Down Mode Bit 1 */ -#define FUSE_TOSCSEL (unsigned char)~_BV(5) /* Timer Oscillator pin location */ -#define FUSE_BOOTRST (unsigned char)~_BV(6) /* Boot Loader Section Reset Vector */ -#define FUSE2_DEFAULT (0xFF) - -/* Fuse Byte 3 Reserved */ - -/* Fuse Byte 4 */ -#define FUSE_WDLOCK (unsigned char)~_BV(1) /* Watchdog Timer Lock */ -#define FUSE_SUT0 (unsigned char)~_BV(2) /* Start-up Time Bit 0 */ -#define FUSE_SUT1 (unsigned char)~_BV(3) /* Start-up Time Bit 1 */ -#define FUSE_RSTDISBL (unsigned char)~_BV(4) /* External Reset Disable */ -#define FUSE4_DEFAULT (0xFF) - -/* Fuse Byte 5 */ -#define FUSE_BODLVL0 (unsigned char)~_BV(0) /* Brownout Detection Voltage Level Bit 0 */ -#define FUSE_BODLVL1 (unsigned char)~_BV(1) /* Brownout Detection Voltage Level Bit 1 */ -#define FUSE_BODLVL2 (unsigned char)~_BV(2) /* Brownout Detection Voltage Level Bit 2 */ -#define FUSE_EESAVE (unsigned char)~_BV(3) /* Preserve EEPROM Through Chip Erase */ -#define FUSE_BODACT0 (unsigned char)~_BV(4) /* BOD Operation in Active Mode Bit 0 */ -#define FUSE_BODACT1 (unsigned char)~_BV(5) /* BOD Operation in Active Mode Bit 1 */ -#define FUSE5_DEFAULT (0xFF) - -/* ========== Lock Bits ========== */ -#define __LOCK_BITS_EXIST -#define __BOOT_LOCK_APPLICATION_TABLE_BITS_EXIST -#define __BOOT_LOCK_APPLICATION_BITS_EXIST -#define __BOOT_LOCK_BOOT_BITS_EXIST - -/* ========== Signature ========== */ -#define SIGNATURE_0 0x1E -#define SIGNATURE_1 0x95 -#define SIGNATURE_2 0x41 - -/* ========== Power Reduction Condition Definitions ========== */ - -/* PR.PRGEN */ -#define __AVR_HAVE_PRGEN (PR_USB_bm|PR_AES_bm|PR_EBI_bm|PR_RTC_bm|PR_EVSYS_bm|PR_DMA_bm) -#define __AVR_HAVE_PRGEN_USB -#define __AVR_HAVE_PRGEN_AES -#define __AVR_HAVE_PRGEN_EBI -#define __AVR_HAVE_PRGEN_RTC -#define __AVR_HAVE_PRGEN_EVSYS -#define __AVR_HAVE_PRGEN_DMA - -/* PR.PRPA */ -#define __AVR_HAVE_PRPA (PR_DAC_bm|PR_ADC_bm|PR_AC_bm) -#define __AVR_HAVE_PRPA_DAC -#define __AVR_HAVE_PRPA_ADC -#define __AVR_HAVE_PRPA_AC - -/* PR.PRPB */ -#define __AVR_HAVE_PRPB (PR_DAC_bm|PR_ADC_bm|PR_AC_bm) -#define __AVR_HAVE_PRPB_DAC -#define __AVR_HAVE_PRPB_ADC -#define __AVR_HAVE_PRPB_AC - -/* PR.PRPC */ -#define __AVR_HAVE_PRPC (PR_TWI_bm|PR_USART1_bm|PR_USART0_bm|PR_SPI_bm|PR_HIRES_bm|PR_TC1_bm|PR_TC0_bm) -#define __AVR_HAVE_PRPC_TWI -#define __AVR_HAVE_PRPC_USART1 -#define __AVR_HAVE_PRPC_USART0 -#define __AVR_HAVE_PRPC_SPI -#define __AVR_HAVE_PRPC_HIRES -#define __AVR_HAVE_PRPC_TC1 -#define __AVR_HAVE_PRPC_TC0 - -/* PR.PRPD */ -#define __AVR_HAVE_PRPD (PR_TWI_bm|PR_USART1_bm|PR_USART0_bm|PR_SPI_bm|PR_HIRES_bm|PR_TC1_bm|PR_TC0_bm) -#define __AVR_HAVE_PRPD_TWI -#define __AVR_HAVE_PRPD_USART1 -#define __AVR_HAVE_PRPD_USART0 -#define __AVR_HAVE_PRPD_SPI -#define __AVR_HAVE_PRPD_HIRES -#define __AVR_HAVE_PRPD_TC1 -#define __AVR_HAVE_PRPD_TC0 - -/* PR.PRPE */ -#define __AVR_HAVE_PRPE (PR_TWI_bm|PR_USART1_bm|PR_USART0_bm|PR_SPI_bm|PR_HIRES_bm|PR_TC1_bm|PR_TC0_bm) -#define __AVR_HAVE_PRPE_TWI -#define __AVR_HAVE_PRPE_USART1 -#define __AVR_HAVE_PRPE_USART0 -#define __AVR_HAVE_PRPE_SPI -#define __AVR_HAVE_PRPE_HIRES -#define __AVR_HAVE_PRPE_TC1 -#define __AVR_HAVE_PRPE_TC0 - -/* PR.PRPF */ -#define __AVR_HAVE_PRPF (PR_TWI_bm|PR_USART1_bm|PR_USART0_bm|PR_SPI_bm|PR_HIRES_bm|PR_TC1_bm|PR_TC0_bm) -#define __AVR_HAVE_PRPF_TWI -#define __AVR_HAVE_PRPF_USART1 -#define __AVR_HAVE_PRPF_USART0 -#define __AVR_HAVE_PRPF_SPI -#define __AVR_HAVE_PRPF_HIRES -#define __AVR_HAVE_PRPF_TC1 -#define __AVR_HAVE_PRPF_TC0 - - -#endif /* #ifdef _AVR_ATXMEGA32A4U_H_INCLUDED */ - diff --git a/arduino/hardware/tools/avr/avr/include/avr/iox32c3.h b/arduino/hardware/tools/avr/avr/include/avr/iox32c3.h deleted file mode 100644 index 16f47c4..0000000 --- a/arduino/hardware/tools/avr/avr/include/avr/iox32c3.h +++ /dev/null @@ -1,6264 +0,0 @@ -/***************************************************************************** - * - * Copyright (C) 2015 Atmel Corporation - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * - * * Neither the name of the copyright holders nor the names of - * contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - ****************************************************************************/ - - -#ifndef _AVR_IO_H_ -# error "Include instead of this file." -#endif - -#ifndef _AVR_IOXXX_H_ -# define _AVR_IOXXX_H_ "iox32c3.h" -#else -# error "Attempt to include more than one file." -#endif - -#ifndef _AVR_ATXMEGA32C3_H_INCLUDED -#define _AVR_ATXMEGA32C3_H_INCLUDED - -/* Ungrouped common registers */ -#define GPIOR0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ -#define GPIOR1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ -#define GPIOR2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ -#define GPIOR3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ - -/* Deprecated */ -#define GPIO0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ -#define GPIO1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ -#define GPIO2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ -#define GPIO3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ - -#define CCP _SFR_MEM8(0x0034) /* Configuration Change Protection */ -#define RAMPD _SFR_MEM8(0x0038) /* Ramp D */ -#define RAMPX _SFR_MEM8(0x0039) /* Ramp X */ -#define RAMPY _SFR_MEM8(0x003A) /* Ramp Y */ -#define RAMPZ _SFR_MEM8(0x003B) /* Ramp Z */ -#define EIND _SFR_MEM8(0x003C) /* Extended Indirect Jump */ -#define SPL _SFR_MEM8(0x003D) /* Stack Pointer Low */ -#define SPH _SFR_MEM8(0x003E) /* Stack Pointer High */ -#define SREG _SFR_MEM8(0x003F) /* Status Register */ - -/* C Language Only */ -#if !defined (__ASSEMBLER__) - -#include - -typedef volatile uint8_t register8_t; -typedef volatile uint16_t register16_t; -typedef volatile uint32_t register32_t; - - -#ifdef _WORDREGISTER -#undef _WORDREGISTER -#endif -#define _WORDREGISTER(regname) \ - __extension__ union \ - { \ - register16_t regname; \ - struct \ - { \ - register8_t regname ## L; \ - register8_t regname ## H; \ - }; \ - } - -#ifdef _DWORDREGISTER -#undef _DWORDREGISTER -#endif -#define _DWORDREGISTER(regname) \ - __extension__ union \ - { \ - register32_t regname; \ - struct \ - { \ - register8_t regname ## 0; \ - register8_t regname ## 1; \ - register8_t regname ## 2; \ - register8_t regname ## 3; \ - }; \ - } - - -/* -========================================================================== -IO Module Structures -========================================================================== -*/ - - -/* --------------------------------------------------------------------------- -VPORT - Virtual Ports --------------------------------------------------------------------------- -*/ - -/* Virtual Port */ -typedef struct VPORT_struct -{ - register8_t DIR; /* I/O Port Data Direction */ - register8_t OUT; /* I/O Port Output */ - register8_t IN; /* I/O Port Input */ - register8_t INTFLAGS; /* Interrupt Flag Register */ -} VPORT_t; - - -/* --------------------------------------------------------------------------- -XOCD - On-Chip Debug System --------------------------------------------------------------------------- -*/ - -/* On-Chip Debug System */ -typedef struct OCD_struct -{ - register8_t OCDR0; /* OCD Register 0 */ - register8_t OCDR1; /* OCD Register 1 */ -} OCD_t; - - -/* --------------------------------------------------------------------------- -CPU - CPU --------------------------------------------------------------------------- -*/ - -/* CCP signatures */ -typedef enum CCP_enum -{ - CCP_SPM_gc = (0x9D<<0), /* SPM Instruction Protection */ - CCP_IOREG_gc = (0xD8<<0), /* IO Register Protection */ -} CCP_t; - - -/* --------------------------------------------------------------------------- -CLK - Clock System --------------------------------------------------------------------------- -*/ - -/* Clock System */ -typedef struct CLK_struct -{ - register8_t CTRL; /* Control Register */ - register8_t PSCTRL; /* Prescaler Control Register */ - register8_t LOCK; /* Lock register */ - register8_t RTCCTRL; /* RTC Control Register */ - register8_t USBCTRL; /* USB Control Register */ -} CLK_t; - - -/* Power Reduction */ -typedef struct PR_struct -{ - register8_t PRGEN; /* General Power Reduction */ - register8_t PRPA; /* Power Reduction Port A */ - register8_t reserved_0x02; - register8_t PRPC; /* Power Reduction Port C */ - register8_t PRPD; /* Power Reduction Port D */ - register8_t PRPE; /* Power Reduction Port E */ - register8_t PRPF; /* Power Reduction Port F */ -} PR_t; - -/* System Clock Selection */ -typedef enum CLK_SCLKSEL_enum -{ - CLK_SCLKSEL_RC2M_gc = (0x00<<0), /* Internal 2 MHz RC Oscillator */ - CLK_SCLKSEL_RC32M_gc = (0x01<<0), /* Internal 32 MHz RC Oscillator */ - CLK_SCLKSEL_RC32K_gc = (0x02<<0), /* Internal 32.768 kHz RC Oscillator */ - CLK_SCLKSEL_XOSC_gc = (0x03<<0), /* External Crystal Oscillator or Clock */ - CLK_SCLKSEL_PLL_gc = (0x04<<0), /* Phase Locked Loop */ -} CLK_SCLKSEL_t; - -/* Prescaler A Division Factor */ -typedef enum CLK_PSADIV_enum -{ - CLK_PSADIV_1_gc = (0x00<<2), /* Divide by 1 */ - CLK_PSADIV_2_gc = (0x01<<2), /* Divide by 2 */ - CLK_PSADIV_4_gc = (0x03<<2), /* Divide by 4 */ - CLK_PSADIV_8_gc = (0x05<<2), /* Divide by 8 */ - CLK_PSADIV_16_gc = (0x07<<2), /* Divide by 16 */ - CLK_PSADIV_32_gc = (0x09<<2), /* Divide by 32 */ - CLK_PSADIV_64_gc = (0x0B<<2), /* Divide by 64 */ - CLK_PSADIV_128_gc = (0x0D<<2), /* Divide by 128 */ - CLK_PSADIV_256_gc = (0x0F<<2), /* Divide by 256 */ - CLK_PSADIV_512_gc = (0x11<<2), /* Divide by 512 */ -} CLK_PSADIV_t; - -/* Prescaler B and C Division Factor */ -typedef enum CLK_PSBCDIV_enum -{ - CLK_PSBCDIV_1_1_gc = (0x00<<0), /* Divide B by 1 and C by 1 */ - CLK_PSBCDIV_1_2_gc = (0x01<<0), /* Divide B by 1 and C by 2 */ - CLK_PSBCDIV_4_1_gc = (0x02<<0), /* Divide B by 4 and C by 1 */ - CLK_PSBCDIV_2_2_gc = (0x03<<0), /* Divide B by 2 and C by 2 */ -} CLK_PSBCDIV_t; - -/* RTC Clock Source */ -typedef enum CLK_RTCSRC_enum -{ - CLK_RTCSRC_ULP_gc = (0x00<<1), /* 1.024 kHz from internal 32kHz ULP */ - CLK_RTCSRC_TOSC_gc = (0x01<<1), /* 1.024 kHz from 32.768 kHz crystal oscillator on TOSC */ - CLK_RTCSRC_RCOSC_gc = (0x02<<1), /* 1.024 kHz from internal 32.768 kHz RC oscillator */ - CLK_RTCSRC_TOSC32_gc = (0x05<<1), /* 32.768 kHz from 32.768 kHz crystal oscillator on TOSC */ - CLK_RTCSRC_RCOSC32_gc = (0x06<<1), /* 32.768 kHz from internal 32.768 kHz RC oscillator */ - CLK_RTCSRC_EXTCLK_gc = (0x07<<1), /* External Clock from TOSC1 */ -} CLK_RTCSRC_t; - -/* USB Prescaler Division Factor */ -typedef enum CLK_USBPSDIV_enum -{ - CLK_USBPSDIV_1_gc = (0x00<<3), /* Divide by 1 */ - CLK_USBPSDIV_2_gc = (0x01<<3), /* Divide by 2 */ - CLK_USBPSDIV_4_gc = (0x02<<3), /* Divide by 4 */ - CLK_USBPSDIV_8_gc = (0x03<<3), /* Divide by 8 */ - CLK_USBPSDIV_16_gc = (0x04<<3), /* Divide by 16 */ - CLK_USBPSDIV_32_gc = (0x05<<3), /* Divide by 32 */ -} CLK_USBPSDIV_t; - -/* USB Clock Source */ -typedef enum CLK_USBSRC_enum -{ - CLK_USBSRC_PLL_gc = (0x00<<1), /* PLL */ - CLK_USBSRC_RC32M_gc = (0x01<<1), /* Internal 32 MHz RC Oscillator */ -} CLK_USBSRC_t; - - -/* --------------------------------------------------------------------------- -SLEEP - Sleep Controller --------------------------------------------------------------------------- -*/ - -/* Sleep Controller */ -typedef struct SLEEP_struct -{ - register8_t CTRL; /* Control Register */ -} SLEEP_t; - -/* Sleep Mode */ -typedef enum SLEEP_SMODE_enum -{ - SLEEP_SMODE_IDLE_gc = (0x00<<1), /* Idle mode */ - SLEEP_SMODE_PDOWN_gc = (0x02<<1), /* Power-down Mode */ - SLEEP_SMODE_PSAVE_gc = (0x03<<1), /* Power-save Mode */ - SLEEP_SMODE_STDBY_gc = (0x06<<1), /* Standby Mode */ - SLEEP_SMODE_ESTDBY_gc = (0x07<<1), /* Extended Standby Mode */ -} SLEEP_SMODE_t; - - - -#define SLEEP_MODE_IDLE (0x00<<1) -#define SLEEP_MODE_PWR_DOWN (0x02<<1) -#define SLEEP_MODE_PWR_SAVE (0x03<<1) -#define SLEEP_MODE_STANDBY (0x06<<1) -#define SLEEP_MODE_EXT_STANDBY (0x07<<1) -/* --------------------------------------------------------------------------- -OSC - Oscillator --------------------------------------------------------------------------- -*/ - -/* Oscillator */ -typedef struct OSC_struct -{ - register8_t CTRL; /* Control Register */ - register8_t STATUS; /* Status Register */ - register8_t XOSCCTRL; /* External Oscillator Control Register */ - register8_t XOSCFAIL; /* Oscillator Failure Detection Register */ - register8_t RC32KCAL; /* 32.768 kHz Internal Oscillator Calibration Register */ - register8_t PLLCTRL; /* PLL Control Register */ - register8_t DFLLCTRL; /* DFLL Control Register */ -} OSC_t; - -/* Oscillator Frequency Range */ -typedef enum OSC_FRQRANGE_enum -{ - OSC_FRQRANGE_04TO2_gc = (0x00<<6), /* 0.4 - 2 MHz */ - OSC_FRQRANGE_2TO9_gc = (0x01<<6), /* 2 - 9 MHz */ - OSC_FRQRANGE_9TO12_gc = (0x02<<6), /* 9 - 12 MHz */ - OSC_FRQRANGE_12TO16_gc = (0x03<<6), /* 12 - 16 MHz */ -} OSC_FRQRANGE_t; - -/* External Oscillator Selection and Startup Time */ -typedef enum OSC_XOSCSEL_enum -{ - OSC_XOSCSEL_EXTCLK_gc = (0x00<<0), /* External Clock - 6 CLK */ - OSC_XOSCSEL_32KHz_gc = (0x02<<0), /* 32.768 kHz TOSC - 32K CLK */ - OSC_XOSCSEL_XTAL_256CLK_gc = (0x03<<0), /* 0.4-16 MHz XTAL - 256 CLK */ - OSC_XOSCSEL_XTAL_1KCLK_gc = (0x07<<0), /* 0.4-16 MHz XTAL - 1K CLK */ - OSC_XOSCSEL_XTAL_16KCLK_gc = (0x0B<<0), /* 0.4-16 MHz XTAL - 16K CLK */ -} OSC_XOSCSEL_t; - -/* PLL Clock Source */ -typedef enum OSC_PLLSRC_enum -{ - OSC_PLLSRC_RC2M_gc = (0x00<<6), /* Internal 2 MHz RC Oscillator */ - OSC_PLLSRC_RC32M_gc = (0x02<<6), /* Internal 32 MHz RC Oscillator */ - OSC_PLLSRC_XOSC_gc = (0x03<<6), /* External Oscillator */ -} OSC_PLLSRC_t; - -/* 2 MHz DFLL Calibration Reference */ -typedef enum OSC_RC2MCREF_enum -{ - OSC_RC2MCREF_RC32K_gc = (0x00<<0), /* Internal 32.768 kHz RC Oscillator */ - OSC_RC2MCREF_XOSC32K_gc = (0x01<<0), /* External 32.768 kHz Crystal Oscillator */ -} OSC_RC2MCREF_t; - -/* 32 MHz DFLL Calibration Reference */ -typedef enum OSC_RC32MCREF_enum -{ - OSC_RC32MCREF_RC32K_gc = (0x00<<1), /* Internal 32.768 kHz RC Oscillator */ - OSC_RC32MCREF_XOSC32K_gc = (0x01<<1), /* External 32.768 kHz Crystal Oscillator */ - OSC_RC32MCREF_USBSOF_gc = (0x02<<1), /* USB Start of Frame */ -} OSC_RC32MCREF_t; - - -/* --------------------------------------------------------------------------- -DFLL - DFLL --------------------------------------------------------------------------- -*/ - -/* DFLL */ -typedef struct DFLL_struct -{ - register8_t CTRL; /* Control Register */ - register8_t reserved_0x01; - register8_t CALA; /* Calibration Register A */ - register8_t CALB; /* Calibration Register B */ - register8_t COMP0; /* Oscillator Compare Register 0 */ - register8_t COMP1; /* Oscillator Compare Register 1 */ - register8_t COMP2; /* Oscillator Compare Register 2 */ - register8_t reserved_0x07; -} DFLL_t; - - -/* --------------------------------------------------------------------------- -RST - Reset --------------------------------------------------------------------------- -*/ - -/* Reset */ -typedef struct RST_struct -{ - register8_t STATUS; /* Status Register */ - register8_t CTRL; /* Control Register */ -} RST_t; - - -/* --------------------------------------------------------------------------- -WDT - Watch-Dog Timer --------------------------------------------------------------------------- -*/ - -/* Watch-Dog Timer */ -typedef struct WDT_struct -{ - register8_t CTRL; /* Control */ - register8_t WINCTRL; /* Windowed Mode Control */ - register8_t STATUS; /* Status */ -} WDT_t; - -/* Period setting */ -typedef enum WDT_PER_enum -{ - WDT_PER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ - WDT_PER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ - WDT_PER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ - WDT_PER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ - WDT_PER_128CLK_gc = (0x04<<2), /* 128 cycles (0.128s @ 3.3V) */ - WDT_PER_256CLK_gc = (0x05<<2), /* 256 cycles (0.256s @ 3.3V) */ - WDT_PER_512CLK_gc = (0x06<<2), /* 512 cycles (0.512s @ 3.3V) */ - WDT_PER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ - WDT_PER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ - WDT_PER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ - WDT_PER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ -} WDT_PER_t; - -/* Closed window period */ -typedef enum WDT_WPER_enum -{ - WDT_WPER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ - WDT_WPER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ - WDT_WPER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ - WDT_WPER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ - WDT_WPER_128CLK_gc = (0x04<<2), /* 128 cycles (0.128s @ 3.3V) */ - WDT_WPER_256CLK_gc = (0x05<<2), /* 256 cycles (0.256s @ 3.3V) */ - WDT_WPER_512CLK_gc = (0x06<<2), /* 512 cycles (0.512s @ 3.3V) */ - WDT_WPER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ - WDT_WPER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ - WDT_WPER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ - WDT_WPER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ -} WDT_WPER_t; - - -/* --------------------------------------------------------------------------- -MCU - MCU Control --------------------------------------------------------------------------- -*/ - -/* MCU Control */ -typedef struct MCU_struct -{ - register8_t DEVID0; /* Device ID byte 0 */ - register8_t DEVID1; /* Device ID byte 1 */ - register8_t DEVID2; /* Device ID byte 2 */ - register8_t REVID; /* Revision ID */ - register8_t reserved_0x04; - register8_t reserved_0x05; - register8_t reserved_0x06; - register8_t ANAINIT; /* Analog Startup Delay */ - register8_t EVSYSLOCK; /* Event System Lock */ - register8_t AWEXLOCK; /* AWEX Lock */ - register8_t reserved_0x0A; - register8_t reserved_0x0B; -} MCU_t; - - -/* --------------------------------------------------------------------------- -PMIC - Programmable Multi-level Interrupt Controller --------------------------------------------------------------------------- -*/ - -/* Programmable Multi-level Interrupt Controller */ -typedef struct PMIC_struct -{ - register8_t STATUS; /* Status Register */ - register8_t INTPRI; /* Interrupt Priority */ - register8_t CTRL; /* Control Register */ - register8_t reserved_0x03; - register8_t reserved_0x04; - register8_t reserved_0x05; - register8_t reserved_0x06; - register8_t reserved_0x07; - register8_t reserved_0x08; - register8_t reserved_0x09; - register8_t reserved_0x0A; - register8_t reserved_0x0B; - register8_t reserved_0x0C; - register8_t reserved_0x0D; - register8_t reserved_0x0E; - register8_t reserved_0x0F; -} PMIC_t; - - -/* --------------------------------------------------------------------------- -PORTCFG - Port Configuration --------------------------------------------------------------------------- -*/ - -/* I/O port Configuration */ -typedef struct PORTCFG_struct -{ - register8_t MPCMASK; /* Multi-pin Configuration Mask */ - register8_t reserved_0x01; - register8_t VPCTRLA; /* Virtual Port Control Register A */ - register8_t VPCTRLB; /* Virtual Port Control Register B */ - register8_t CLKEVOUT; /* Clock and Event Out Register */ - register8_t reserved_0x05; - register8_t EVOUTSEL; /* Event Output Select */ -} PORTCFG_t; - -/* Virtual Port Mapping */ -typedef enum PORTCFG_VP02MAP_enum -{ - PORTCFG_VP02MAP_PORTA_gc = (0x00<<0), /* Mapped To PORTA */ - PORTCFG_VP02MAP_PORTB_gc = (0x01<<0), /* Mapped To PORTB */ - PORTCFG_VP02MAP_PORTC_gc = (0x02<<0), /* Mapped To PORTC */ - PORTCFG_VP02MAP_PORTD_gc = (0x03<<0), /* Mapped To PORTD */ - PORTCFG_VP02MAP_PORTE_gc = (0x04<<0), /* Mapped To PORTE */ - PORTCFG_VP02MAP_PORTF_gc = (0x05<<0), /* Mapped To PORTF */ - PORTCFG_VP02MAP_PORTG_gc = (0x06<<0), /* Mapped To PORTG */ - PORTCFG_VP02MAP_PORTH_gc = (0x07<<0), /* Mapped To PORTH */ - PORTCFG_VP02MAP_PORTJ_gc = (0x08<<0), /* Mapped To PORTJ */ - PORTCFG_VP02MAP_PORTK_gc = (0x09<<0), /* Mapped To PORTK */ - PORTCFG_VP02MAP_PORTL_gc = (0x0A<<0), /* Mapped To PORTL */ - PORTCFG_VP02MAP_PORTM_gc = (0x0B<<0), /* Mapped To PORTM */ - PORTCFG_VP02MAP_PORTN_gc = (0x0C<<0), /* Mapped To PORTN */ - PORTCFG_VP02MAP_PORTP_gc = (0x0D<<0), /* Mapped To PORTP */ - PORTCFG_VP02MAP_PORTQ_gc = (0x0E<<0), /* Mapped To PORTQ */ - PORTCFG_VP02MAP_PORTR_gc = (0x0F<<0), /* Mapped To PORTR */ -} PORTCFG_VP02MAP_t; - -/* Virtual Port Mapping */ -typedef enum PORTCFG_VP13MAP_enum -{ - PORTCFG_VP13MAP_PORTA_gc = (0x00<<4), /* Mapped To PORTA */ - PORTCFG_VP13MAP_PORTB_gc = (0x01<<4), /* Mapped To PORTB */ - PORTCFG_VP13MAP_PORTC_gc = (0x02<<4), /* Mapped To PORTC */ - PORTCFG_VP13MAP_PORTD_gc = (0x03<<4), /* Mapped To PORTD */ - PORTCFG_VP13MAP_PORTE_gc = (0x04<<4), /* Mapped To PORTE */ - PORTCFG_VP13MAP_PORTF_gc = (0x05<<4), /* Mapped To PORTF */ - PORTCFG_VP13MAP_PORTG_gc = (0x06<<4), /* Mapped To PORTG */ - PORTCFG_VP13MAP_PORTH_gc = (0x07<<4), /* Mapped To PORTH */ - PORTCFG_VP13MAP_PORTJ_gc = (0x08<<4), /* Mapped To PORTJ */ - PORTCFG_VP13MAP_PORTK_gc = (0x09<<4), /* Mapped To PORTK */ - PORTCFG_VP13MAP_PORTL_gc = (0x0A<<4), /* Mapped To PORTL */ - PORTCFG_VP13MAP_PORTM_gc = (0x0B<<4), /* Mapped To PORTM */ - PORTCFG_VP13MAP_PORTN_gc = (0x0C<<4), /* Mapped To PORTN */ - PORTCFG_VP13MAP_PORTP_gc = (0x0D<<4), /* Mapped To PORTP */ - PORTCFG_VP13MAP_PORTQ_gc = (0x0E<<4), /* Mapped To PORTQ */ - PORTCFG_VP13MAP_PORTR_gc = (0x0F<<4), /* Mapped To PORTR */ -} PORTCFG_VP13MAP_t; - -/* System Clock Output Port */ -typedef enum PORTCFG_CLKOUT_enum -{ - PORTCFG_CLKOUT_OFF_gc = (0x00<<0), /* System Clock Output Disabled */ - PORTCFG_CLKOUT_PC7_gc = (0x01<<0), /* System Clock Output on Port C pin 7 */ - PORTCFG_CLKOUT_PD7_gc = (0x02<<0), /* System Clock Output on Port D pin 7 */ - PORTCFG_CLKOUT_PE7_gc = (0x03<<0), /* System Clock Output on Port E pin 7 */ -} PORTCFG_CLKOUT_t; - -/* Peripheral Clock Output Select */ -typedef enum PORTCFG_CLKOUTSEL_enum -{ - PORTCFG_CLKOUTSEL_CLK1X_gc = (0x00<<2), /* 1x Peripheral Clock Output to pin */ - PORTCFG_CLKOUTSEL_CLK2X_gc = (0x01<<2), /* 2x Peripheral Clock Output to pin */ - PORTCFG_CLKOUTSEL_CLK4X_gc = (0x02<<2), /* 4x Peripheral Clock Output to pin */ -} PORTCFG_CLKOUTSEL_t; - -/* Event Output Port */ -typedef enum PORTCFG_EVOUT_enum -{ - PORTCFG_EVOUT_OFF_gc = (0x00<<4), /* Event Output Disabled */ - PORTCFG_EVOUT_PC7_gc = (0x01<<4), /* Event Channel 7 Output on Port C pin 7 */ - PORTCFG_EVOUT_PD7_gc = (0x02<<4), /* Event Channel 7 Output on Port D pin 7 */ - PORTCFG_EVOUT_PE7_gc = (0x03<<4), /* Event Channel 7 Output on Port E pin 7 */ -} PORTCFG_EVOUT_t; - -/* Event Output Select */ -typedef enum PORTCFG_EVOUTSEL_enum -{ - PORTCFG_EVOUTSEL_0_gc = (0x00<<0), /* Event Channel 0 output to pin */ - PORTCFG_EVOUTSEL_1_gc = (0x01<<0), /* Event Channel 1 output to pin */ - PORTCFG_EVOUTSEL_2_gc = (0x02<<0), /* Event Channel 2 output to pin */ - PORTCFG_EVOUTSEL_3_gc = (0x03<<0), /* Event Channel 3 output to pin */ -} PORTCFG_EVOUTSEL_t; - - -/* --------------------------------------------------------------------------- -CRC - Cyclic Redundancy Checker --------------------------------------------------------------------------- -*/ - -/* Cyclic Redundancy Checker */ -typedef struct CRC_struct -{ - register8_t CTRL; /* Control Register */ - register8_t STATUS; /* Status Register */ - register8_t reserved_0x02; - register8_t DATAIN; /* Data Input */ - register8_t CHECKSUM0; /* Checksum byte 0 */ - register8_t CHECKSUM1; /* Checksum byte 1 */ - register8_t CHECKSUM2; /* Checksum byte 2 */ - register8_t CHECKSUM3; /* Checksum byte 3 */ -} CRC_t; - -/* Reset */ -typedef enum CRC_RESET_enum -{ - CRC_RESET_NO_gc = (0x00<<6), /* No Reset */ - CRC_RESET_RESET0_gc = (0x02<<6), /* Reset CRC with CHECKSUM to all zeros */ - CRC_RESET_RESET1_gc = (0x03<<6), /* Reset CRC with CHECKSUM to all ones */ -} CRC_RESET_t; - -/* Input Source */ -typedef enum CRC_SOURCE_enum -{ - CRC_SOURCE_DISABLE_gc = (0x00<<0), /* Disabled */ - CRC_SOURCE_IO_gc = (0x01<<0), /* I/O Interface */ - CRC_SOURCE_FLASH_gc = (0x02<<0), /* Flash */ -} CRC_SOURCE_t; - - -/* --------------------------------------------------------------------------- -EVSYS - Event System --------------------------------------------------------------------------- -*/ - -/* Event System */ -typedef struct EVSYS_struct -{ - register8_t CH0MUX; /* Event Channel 0 Multiplexer */ - register8_t CH1MUX; /* Event Channel 1 Multiplexer */ - register8_t CH2MUX; /* Event Channel 2 Multiplexer */ - register8_t CH3MUX; /* Event Channel 3 Multiplexer */ - register8_t reserved_0x04; - register8_t reserved_0x05; - register8_t reserved_0x06; - register8_t reserved_0x07; - register8_t CH0CTRL; /* Channel 0 Control Register */ - register8_t CH1CTRL; /* Channel 1 Control Register */ - register8_t CH2CTRL; /* Channel 2 Control Register */ - register8_t CH3CTRL; /* Channel 3 Control Register */ - register8_t reserved_0x0C; - register8_t reserved_0x0D; - register8_t reserved_0x0E; - register8_t reserved_0x0F; - register8_t STROBE; /* Event Strobe */ - register8_t DATA; /* Event Data */ -} EVSYS_t; - -/* Quadrature Decoder Index Recognition Mode */ -typedef enum EVSYS_QDIRM_enum -{ - EVSYS_QDIRM_00_gc = (0x00<<5), /* QDPH0 = 0, QDPH90 = 0 */ - EVSYS_QDIRM_01_gc = (0x01<<5), /* QDPH0 = 0, QDPH90 = 1 */ - EVSYS_QDIRM_10_gc = (0x02<<5), /* QDPH0 = 1, QDPH90 = 0 */ - EVSYS_QDIRM_11_gc = (0x03<<5), /* QDPH0 = 1, QDPH90 = 1 */ -} EVSYS_QDIRM_t; - -/* Digital filter coefficient */ -typedef enum EVSYS_DIGFILT_enum -{ - EVSYS_DIGFILT_1SAMPLE_gc = (0x00<<0), /* 1 SAMPLE */ - EVSYS_DIGFILT_2SAMPLES_gc = (0x01<<0), /* 2 SAMPLES */ - EVSYS_DIGFILT_3SAMPLES_gc = (0x02<<0), /* 3 SAMPLES */ - EVSYS_DIGFILT_4SAMPLES_gc = (0x03<<0), /* 4 SAMPLES */ - EVSYS_DIGFILT_5SAMPLES_gc = (0x04<<0), /* 5 SAMPLES */ - EVSYS_DIGFILT_6SAMPLES_gc = (0x05<<0), /* 6 SAMPLES */ - EVSYS_DIGFILT_7SAMPLES_gc = (0x06<<0), /* 7 SAMPLES */ - EVSYS_DIGFILT_8SAMPLES_gc = (0x07<<0), /* 8 SAMPLES */ -} EVSYS_DIGFILT_t; - -/* Event Channel multiplexer input selection */ -typedef enum EVSYS_CHMUX_enum -{ - EVSYS_CHMUX_OFF_gc = (0x00<<0), /* Off */ - EVSYS_CHMUX_RTC_OVF_gc = (0x08<<0), /* RTC Overflow */ - EVSYS_CHMUX_RTC_CMP_gc = (0x09<<0), /* RTC Compare Match */ - EVSYS_CHMUX_USB_gc = (0x0A<<0), /* USB Setup, SOF, CRC error and UNF/OVF */ - EVSYS_CHMUX_ACA_CH0_gc = (0x10<<0), /* Analog Comparator A Channel 0 */ - EVSYS_CHMUX_ACA_CH1_gc = (0x11<<0), /* Analog Comparator A Channel 1 */ - EVSYS_CHMUX_ACA_WIN_gc = (0x12<<0), /* Analog Comparator A Window */ - EVSYS_CHMUX_ADCA_CH0_gc = (0x20<<0), /* ADC A Channel */ - EVSYS_CHMUX_PORTA_PIN0_gc = (0x50<<0), /* Port A, Pin0 */ - EVSYS_CHMUX_PORTA_PIN1_gc = (0x51<<0), /* Port A, Pin1 */ - EVSYS_CHMUX_PORTA_PIN2_gc = (0x52<<0), /* Port A, Pin2 */ - EVSYS_CHMUX_PORTA_PIN3_gc = (0x53<<0), /* Port A, Pin3 */ - EVSYS_CHMUX_PORTA_PIN4_gc = (0x54<<0), /* Port A, Pin4 */ - EVSYS_CHMUX_PORTA_PIN5_gc = (0x55<<0), /* Port A, Pin5 */ - EVSYS_CHMUX_PORTA_PIN6_gc = (0x56<<0), /* Port A, Pin6 */ - EVSYS_CHMUX_PORTA_PIN7_gc = (0x57<<0), /* Port A, Pin7 */ - EVSYS_CHMUX_PORTB_PIN0_gc = (0x58<<0), /* Port B, Pin0 */ - EVSYS_CHMUX_PORTB_PIN1_gc = (0x59<<0), /* Port B, Pin1 */ - EVSYS_CHMUX_PORTB_PIN2_gc = (0x5A<<0), /* Port B, Pin2 */ - EVSYS_CHMUX_PORTB_PIN3_gc = (0x5B<<0), /* Port B, Pin3 */ - EVSYS_CHMUX_PORTB_PIN4_gc = (0x5C<<0), /* Port B, Pin4 */ - EVSYS_CHMUX_PORTB_PIN5_gc = (0x5D<<0), /* Port B, Pin5 */ - EVSYS_CHMUX_PORTB_PIN6_gc = (0x5E<<0), /* Port B, Pin6 */ - EVSYS_CHMUX_PORTB_PIN7_gc = (0x5F<<0), /* Port B, Pin7 */ - EVSYS_CHMUX_PORTC_PIN0_gc = (0x60<<0), /* Port C, Pin0 */ - EVSYS_CHMUX_PORTC_PIN1_gc = (0x61<<0), /* Port C, Pin1 */ - EVSYS_CHMUX_PORTC_PIN2_gc = (0x62<<0), /* Port C, Pin2 */ - EVSYS_CHMUX_PORTC_PIN3_gc = (0x63<<0), /* Port C, Pin3 */ - EVSYS_CHMUX_PORTC_PIN4_gc = (0x64<<0), /* Port C, Pin4 */ - EVSYS_CHMUX_PORTC_PIN5_gc = (0x65<<0), /* Port C, Pin5 */ - EVSYS_CHMUX_PORTC_PIN6_gc = (0x66<<0), /* Port C, Pin6 */ - EVSYS_CHMUX_PORTC_PIN7_gc = (0x67<<0), /* Port C, Pin7 */ - EVSYS_CHMUX_PORTD_PIN0_gc = (0x68<<0), /* Port D, Pin0 */ - EVSYS_CHMUX_PORTD_PIN1_gc = (0x69<<0), /* Port D, Pin1 */ - EVSYS_CHMUX_PORTD_PIN2_gc = (0x6A<<0), /* Port D, Pin2 */ - EVSYS_CHMUX_PORTD_PIN3_gc = (0x6B<<0), /* Port D, Pin3 */ - EVSYS_CHMUX_PORTD_PIN4_gc = (0x6C<<0), /* Port D, Pin4 */ - EVSYS_CHMUX_PORTD_PIN5_gc = (0x6D<<0), /* Port D, Pin5 */ - EVSYS_CHMUX_PORTD_PIN6_gc = (0x6E<<0), /* Port D, Pin6 */ - EVSYS_CHMUX_PORTD_PIN7_gc = (0x6F<<0), /* Port D, Pin7 */ - EVSYS_CHMUX_PORTE_PIN0_gc = (0x70<<0), /* Port E, Pin0 */ - EVSYS_CHMUX_PORTE_PIN1_gc = (0x71<<0), /* Port E, Pin1 */ - EVSYS_CHMUX_PORTE_PIN2_gc = (0x72<<0), /* Port E, Pin2 */ - EVSYS_CHMUX_PORTE_PIN3_gc = (0x73<<0), /* Port E, Pin3 */ - EVSYS_CHMUX_PORTE_PIN4_gc = (0x74<<0), /* Port E, Pin4 */ - EVSYS_CHMUX_PORTE_PIN5_gc = (0x75<<0), /* Port E, Pin5 */ - EVSYS_CHMUX_PORTE_PIN6_gc = (0x76<<0), /* Port E, Pin6 */ - EVSYS_CHMUX_PORTE_PIN7_gc = (0x77<<0), /* Port E, Pin7 */ - EVSYS_CHMUX_PORTF_PIN0_gc = (0x78<<0), /* Port F, Pin0 */ - EVSYS_CHMUX_PORTF_PIN1_gc = (0x79<<0), /* Port F, Pin1 */ - EVSYS_CHMUX_PORTF_PIN2_gc = (0x7A<<0), /* Port F, Pin2 */ - EVSYS_CHMUX_PORTF_PIN3_gc = (0x7B<<0), /* Port F, Pin3 */ - EVSYS_CHMUX_PORTF_PIN4_gc = (0x7C<<0), /* Port F, Pin4 */ - EVSYS_CHMUX_PORTF_PIN5_gc = (0x7D<<0), /* Port F, Pin5 */ - EVSYS_CHMUX_PORTF_PIN6_gc = (0x7E<<0), /* Port F, Pin6 */ - EVSYS_CHMUX_PORTF_PIN7_gc = (0x7F<<0), /* Port F, Pin7 */ - EVSYS_CHMUX_PRESCALER_1_gc = (0x80<<0), /* Prescaler, divide by 1 */ - EVSYS_CHMUX_PRESCALER_2_gc = (0x81<<0), /* Prescaler, divide by 2 */ - EVSYS_CHMUX_PRESCALER_4_gc = (0x82<<0), /* Prescaler, divide by 4 */ - EVSYS_CHMUX_PRESCALER_8_gc = (0x83<<0), /* Prescaler, divide by 8 */ - EVSYS_CHMUX_PRESCALER_16_gc = (0x84<<0), /* Prescaler, divide by 16 */ - EVSYS_CHMUX_PRESCALER_32_gc = (0x85<<0), /* Prescaler, divide by 32 */ - EVSYS_CHMUX_PRESCALER_64_gc = (0x86<<0), /* Prescaler, divide by 64 */ - EVSYS_CHMUX_PRESCALER_128_gc = (0x87<<0), /* Prescaler, divide by 128 */ - EVSYS_CHMUX_PRESCALER_256_gc = (0x88<<0), /* Prescaler, divide by 256 */ - EVSYS_CHMUX_PRESCALER_512_gc = (0x89<<0), /* Prescaler, divide by 512 */ - EVSYS_CHMUX_PRESCALER_1024_gc = (0x8A<<0), /* Prescaler, divide by 1024 */ - EVSYS_CHMUX_PRESCALER_2048_gc = (0x8B<<0), /* Prescaler, divide by 2048 */ - EVSYS_CHMUX_PRESCALER_4096_gc = (0x8C<<0), /* Prescaler, divide by 4096 */ - EVSYS_CHMUX_PRESCALER_8192_gc = (0x8D<<0), /* Prescaler, divide by 8192 */ - EVSYS_CHMUX_PRESCALER_16384_gc = (0x8E<<0), /* Prescaler, divide by 16384 */ - EVSYS_CHMUX_PRESCALER_32768_gc = (0x8F<<0), /* Prescaler, divide by 32768 */ - EVSYS_CHMUX_TCC0_OVF_gc = (0xC0<<0), /* Timer/Counter C0 Overflow */ - EVSYS_CHMUX_TCC0_ERR_gc = (0xC1<<0), /* Timer/Counter C0 Error */ - EVSYS_CHMUX_TCC0_CCA_gc = (0xC4<<0), /* Timer/Counter C0 Compare or Capture A */ - EVSYS_CHMUX_TCC0_CCB_gc = (0xC5<<0), /* Timer/Counter C0 Compare or Capture B */ - EVSYS_CHMUX_TCC0_CCC_gc = (0xC6<<0), /* Timer/Counter C0 Compare or Capture C */ - EVSYS_CHMUX_TCC0_CCD_gc = (0xC7<<0), /* Timer/Counter C0 Compare or Capture D */ - EVSYS_CHMUX_TCC1_OVF_gc = (0xC8<<0), /* Timer/Counter C1 Overflow */ - EVSYS_CHMUX_TCC1_ERR_gc = (0xC9<<0), /* Timer/Counter C1 Error */ - EVSYS_CHMUX_TCC1_CCA_gc = (0xCC<<0), /* Timer/Counter C1 Compare or Capture A */ - EVSYS_CHMUX_TCC1_CCB_gc = (0xCD<<0), /* Timer/Counter C1 Compare or Capture B */ - EVSYS_CHMUX_TCD0_OVF_gc = (0xD0<<0), /* Timer/Counter D0 Overflow */ - EVSYS_CHMUX_TCD0_ERR_gc = (0xD1<<0), /* Timer/Counter D0 Error */ - EVSYS_CHMUX_TCD0_CCA_gc = (0xD4<<0), /* Timer/Counter D0 Compare or Capture A */ - EVSYS_CHMUX_TCD0_CCB_gc = (0xD5<<0), /* Timer/Counter D0 Compare or Capture B */ - EVSYS_CHMUX_TCD0_CCC_gc = (0xD6<<0), /* Timer/Counter D0 Compare or Capture C */ - EVSYS_CHMUX_TCD0_CCD_gc = (0xD7<<0), /* Timer/Counter D0 Compare or Capture D */ - EVSYS_CHMUX_TCE0_OVF_gc = (0xE0<<0), /* Timer/Counter E0 Overflow */ - EVSYS_CHMUX_TCE0_ERR_gc = (0xE1<<0), /* Timer/Counter E0 Error */ - EVSYS_CHMUX_TCE0_CCA_gc = (0xE4<<0), /* Timer/Counter E0 Compare or Capture A */ - EVSYS_CHMUX_TCE0_CCB_gc = (0xE5<<0), /* Timer/Counter E0 Compare or Capture B */ - EVSYS_CHMUX_TCE0_CCC_gc = (0xE6<<0), /* Timer/Counter E0 Compare or Capture C */ - EVSYS_CHMUX_TCE0_CCD_gc = (0xE7<<0), /* Timer/Counter E0 Compare or Capture D */ - EVSYS_CHMUX_TCF0_OVF_gc = (0xF0<<0), /* Timer/Counter F0 Overflow */ - EVSYS_CHMUX_TCF0_ERR_gc = (0xF1<<0), /* Timer/Counter F0 Error */ - EVSYS_CHMUX_TCF0_CCA_gc = (0xF4<<0), /* Timer/Counter F0 Compare or Capture A */ - EVSYS_CHMUX_TCF0_CCB_gc = (0xF5<<0), /* Timer/Counter F0 Compare or Capture B */ - EVSYS_CHMUX_TCF0_CCC_gc = (0xF6<<0), /* Timer/Counter F0 Compare or Capture C */ - EVSYS_CHMUX_TCF0_CCD_gc = (0xF7<<0), /* Timer/Counter F0 Compare or Capture D */ -} EVSYS_CHMUX_t; - - -/* --------------------------------------------------------------------------- -NVM - Non Volatile Memory Controller --------------------------------------------------------------------------- -*/ - -/* Non-volatile Memory Controller */ -typedef struct NVM_struct -{ - register8_t ADDR0; /* Address Register 0 */ - register8_t ADDR1; /* Address Register 1 */ - register8_t ADDR2; /* Address Register 2 */ - register8_t reserved_0x03; - register8_t DATA0; /* Data Register 0 */ - register8_t DATA1; /* Data Register 1 */ - register8_t DATA2; /* Data Register 2 */ - register8_t reserved_0x07; - register8_t reserved_0x08; - register8_t reserved_0x09; - register8_t CMD; /* Command */ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t INTCTRL; /* Interrupt Control */ - register8_t reserved_0x0E; - register8_t STATUS; /* Status */ - register8_t LOCK_BITS; /* Lock Bits (Changed from LOCKBITS to avoid avr-libc collision) */ -} NVM_t; - -/* NVM Command */ -typedef enum NVM_CMD_enum -{ - NVM_CMD_NO_OPERATION_gc = (0x00<<0), /* Noop/Ordinary LPM */ - NVM_CMD_READ_USER_SIG_ROW_gc = (0x01<<0), /* Read user signature row */ - NVM_CMD_READ_CALIB_ROW_gc = (0x02<<0), /* Read calibration row */ - NVM_CMD_READ_EEPROM_gc = (0x06<<0), /* Read EEPROM */ - NVM_CMD_READ_FUSES_gc = (0x07<<0), /* Read fuse byte */ - NVM_CMD_WRITE_LOCK_BITS_gc = (0x08<<0), /* Write lock bits */ - NVM_CMD_ERASE_USER_SIG_ROW_gc = (0x18<<0), /* Erase user signature row */ - NVM_CMD_WRITE_USER_SIG_ROW_gc = (0x1A<<0), /* Write user signature row */ - NVM_CMD_ERASE_APP_gc = (0x20<<0), /* Erase Application Section */ - NVM_CMD_ERASE_APP_PAGE_gc = (0x22<<0), /* Erase Application Section page */ - NVM_CMD_LOAD_FLASH_BUFFER_gc = (0x23<<0), /* Load Flash page buffer */ - NVM_CMD_WRITE_APP_PAGE_gc = (0x24<<0), /* Write Application Section page */ - NVM_CMD_ERASE_WRITE_APP_PAGE_gc = (0x25<<0), /* Erase-and-write Application Section page */ - NVM_CMD_ERASE_FLASH_BUFFER_gc = (0x26<<0), /* Erase/flush Flash page buffer */ - NVM_CMD_ERASE_BOOT_PAGE_gc = (0x2A<<0), /* Erase Boot Section page */ - NVM_CMD_ERASE_FLASH_PAGE_gc = (0x2B<<0), /* Erase Flash Page */ - NVM_CMD_WRITE_BOOT_PAGE_gc = (0x2C<<0), /* Write Boot Section page */ - NVM_CMD_ERASE_WRITE_BOOT_PAGE_gc = (0x2D<<0), /* Erase-and-write Boot Section page */ - NVM_CMD_WRITE_FLASH_PAGE_gc = (0x2E<<0), /* Write Flash Page */ - NVM_CMD_ERASE_WRITE_FLASH_PAGE_gc = (0x2F<<0), /* Erase-and-write Flash Page */ - NVM_CMD_ERASE_EEPROM_gc = (0x30<<0), /* Erase EEPROM */ - NVM_CMD_ERASE_EEPROM_PAGE_gc = (0x32<<0), /* Erase EEPROM page */ - NVM_CMD_LOAD_EEPROM_BUFFER_gc = (0x33<<0), /* Load EEPROM page buffer */ - NVM_CMD_WRITE_EEPROM_PAGE_gc = (0x34<<0), /* Write EEPROM page */ - NVM_CMD_ERASE_WRITE_EEPROM_PAGE_gc = (0x35<<0), /* Erase-and-write EEPROM page */ - NVM_CMD_ERASE_EEPROM_BUFFER_gc = (0x36<<0), /* Erase/flush EEPROM page buffer */ - NVM_CMD_APP_CRC_gc = (0x38<<0), /* Application section CRC */ - NVM_CMD_BOOT_CRC_gc = (0x39<<0), /* Boot Section CRC */ - NVM_CMD_FLASH_RANGE_CRC_gc = (0x3A<<0), /* Flash Range CRC */ - NVM_CMD_CHIP_ERASE_gc = (0x40<<0), /* Erase Chip */ - NVM_CMD_READ_NVM_gc = (0x43<<0), /* Read NVM */ - NVM_CMD_WRITE_FUSE_gc = (0x4C<<0), /* Write Fuse byte */ - NVM_CMD_ERASE_BOOT_gc = (0x68<<0), /* Erase Boot Section */ - NVM_CMD_FLASH_CRC_gc = (0x78<<0), /* Flash CRC */ -} NVM_CMD_t; - -/* SPM ready interrupt level */ -typedef enum NVM_SPMLVL_enum -{ - NVM_SPMLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ - NVM_SPMLVL_LO_gc = (0x01<<2), /* Low level */ - NVM_SPMLVL_MED_gc = (0x02<<2), /* Medium level */ - NVM_SPMLVL_HI_gc = (0x03<<2), /* High level */ -} NVM_SPMLVL_t; - -/* EEPROM ready interrupt level */ -typedef enum NVM_EELVL_enum -{ - NVM_EELVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ - NVM_EELVL_LO_gc = (0x01<<0), /* Low level */ - NVM_EELVL_MED_gc = (0x02<<0), /* Medium level */ - NVM_EELVL_HI_gc = (0x03<<0), /* High level */ -} NVM_EELVL_t; - -/* Boot lock bits - boot setcion */ -typedef enum NVM_BLBB_enum -{ - NVM_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ - NVM_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ - NVM_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ - NVM_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ -} NVM_BLBB_t; - -/* Boot lock bits - application section */ -typedef enum NVM_BLBA_enum -{ - NVM_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ - NVM_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ - NVM_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ - NVM_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ -} NVM_BLBA_t; - -/* Boot lock bits - application table section */ -typedef enum NVM_BLBAT_enum -{ - NVM_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ - NVM_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ - NVM_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ - NVM_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ -} NVM_BLBAT_t; - -/* Lock bits */ -typedef enum NVM_LB_enum -{ - NVM_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ - NVM_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ - NVM_LB_NOLOCK_gc = (0x03<<0), /* No locks */ -} NVM_LB_t; - - -/* --------------------------------------------------------------------------- -ADC - Analog/Digital Converter --------------------------------------------------------------------------- -*/ - -/* ADC Channel */ -typedef struct ADC_CH_struct -{ - register8_t CTRL; /* Control Register */ - register8_t MUXCTRL; /* MUX Control */ - register8_t INTCTRL; /* Channel Interrupt Control Register */ - register8_t INTFLAGS; /* Interrupt Flags */ - _WORDREGISTER(RES); /* Channel Result */ - register8_t SCAN; /* Input Channel Scan */ - register8_t reserved_0x07; -} ADC_CH_t; - - -/* Analog-to-Digital Converter */ -typedef struct ADC_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t REFCTRL; /* Reference Control */ - register8_t EVCTRL; /* Event Control */ - register8_t PRESCALER; /* Clock Prescaler */ - register8_t reserved_0x05; - register8_t INTFLAGS; /* Interrupt Flags */ - register8_t TEMP; /* Temporary Register */ - register8_t reserved_0x08; - register8_t reserved_0x09; - register8_t reserved_0x0A; - register8_t reserved_0x0B; - _WORDREGISTER(CAL); /* Calibration Value */ - register8_t reserved_0x0E; - register8_t reserved_0x0F; - _WORDREGISTER(CH0RES); /* Channel 0 Result */ - register8_t reserved_0x12; - register8_t reserved_0x13; - register8_t reserved_0x14; - register8_t reserved_0x15; - register8_t reserved_0x16; - register8_t reserved_0x17; - _WORDREGISTER(CMP); /* Compare Value */ - register8_t reserved_0x1A; - register8_t reserved_0x1B; - register8_t reserved_0x1C; - register8_t reserved_0x1D; - register8_t reserved_0x1E; - register8_t reserved_0x1F; - ADC_CH_t CH0; /* ADC Channel 0 */ -} ADC_t; - -/* Current Limitation */ -typedef enum ADC_CURRLIMIT_enum -{ - ADC_CURRLIMIT_NO_gc = (0x00<<5), /* No current limit, 300ksps max sampling rate */ - ADC_CURRLIMIT_LOW_gc = (0x01<<5), /* Low current limit, 250ksps max sampling rate */ - ADC_CURRLIMIT_MED_gc = (0x02<<5), /* Medium current limit, 150ksps max sampling rate */ - ADC_CURRLIMIT_HIGH_gc = (0x03<<5), /* High current limit, 50ksps max sampling rate */ -} ADC_CURRLIMIT_t; - -/* Positive input multiplexer selection */ -typedef enum ADC_CH_MUXPOS_enum -{ - ADC_CH_MUXPOS_PIN0_gc = (0x00<<3), /* Input pin 0 */ - ADC_CH_MUXPOS_PIN1_gc = (0x01<<3), /* Input pin 1 */ - ADC_CH_MUXPOS_PIN2_gc = (0x02<<3), /* Input pin 2 */ - ADC_CH_MUXPOS_PIN3_gc = (0x03<<3), /* Input pin 3 */ - ADC_CH_MUXPOS_PIN4_gc = (0x04<<3), /* Input pin 4 */ - ADC_CH_MUXPOS_PIN5_gc = (0x05<<3), /* Input pin 5 */ - ADC_CH_MUXPOS_PIN6_gc = (0x06<<3), /* Input pin 6 */ - ADC_CH_MUXPOS_PIN7_gc = (0x07<<3), /* Input pin 7 */ - ADC_CH_MUXPOS_PIN8_gc = (0x08<<3), /* Input pin 8 */ - ADC_CH_MUXPOS_PIN9_gc = (0x09<<3), /* Input pin 9 */ - ADC_CH_MUXPOS_PIN10_gc = (0x0A<<3), /* Input pin 10 */ - ADC_CH_MUXPOS_PIN11_gc = (0x0B<<3), /* Input pin 11 */ - ADC_CH_MUXPOS_PIN12_gc = (0x0C<<3), /* Input pin 12 */ - ADC_CH_MUXPOS_PIN13_gc = (0x0D<<3), /* Input pin 13 */ - ADC_CH_MUXPOS_PIN14_gc = (0x0E<<3), /* Input pin 14 */ - ADC_CH_MUXPOS_PIN15_gc = (0x0F<<3), /* Input pin 15 */ -} ADC_CH_MUXPOS_t; - -/* Internal input multiplexer selections */ -typedef enum ADC_CH_MUXINT_enum -{ - ADC_CH_MUXINT_TEMP_gc = (0x00<<3), /* Temperature Reference */ - ADC_CH_MUXINT_BANDGAP_gc = (0x01<<3), /* Bandgap Reference */ - ADC_CH_MUXINT_SCALEDVCC_gc = (0x02<<3), /* 1/10 scaled VCC */ -} ADC_CH_MUXINT_t; - -/* Negative input multiplexer selection */ -typedef enum ADC_CH_MUXNEG_enum -{ - ADC_CH_MUXNEG_PIN0_gc = (0x00<<0), /* Input pin 0 */ - ADC_CH_MUXNEG_PIN1_gc = (0x01<<0), /* Input pin 1 */ - ADC_CH_MUXNEG_PIN2_gc = (0x02<<0), /* Input pin 2 */ - ADC_CH_MUXNEG_PIN3_gc = (0x03<<0), /* Input pin 3 */ - ADC_CH_MUXNEG_PIN4_gc = (0x00<<0), /* Input pin 4 */ - ADC_CH_MUXNEG_PIN5_gc = (0x01<<0), /* Input pin 5 */ - ADC_CH_MUXNEG_PIN6_gc = (0x02<<0), /* Input pin 6 */ - ADC_CH_MUXNEG_PIN7_gc = (0x03<<0), /* Input pin 7 */ -} ADC_CH_MUXNEG_t; - -/* Input mode */ -typedef enum ADC_CH_INPUTMODE_enum -{ - ADC_CH_INPUTMODE_INTERNAL_gc = (0x00<<0), /* Internal inputs, no gain */ - ADC_CH_INPUTMODE_SINGLEENDED_gc = (0x01<<0), /* Single-ended input, no gain */ - ADC_CH_INPUTMODE_DIFF_gc = (0x02<<0), /* Differential input, no gain */ - ADC_CH_INPUTMODE_DIFFWGAIN_gc = (0x03<<0), /* Differential input, with gain */ -} ADC_CH_INPUTMODE_t; - -/* Gain factor */ -typedef enum ADC_CH_GAIN_enum -{ - ADC_CH_GAIN_1X_gc = (0x00<<2), /* 1x gain */ - ADC_CH_GAIN_2X_gc = (0x01<<2), /* 2x gain */ - ADC_CH_GAIN_4X_gc = (0x02<<2), /* 4x gain */ - ADC_CH_GAIN_8X_gc = (0x03<<2), /* 8x gain */ - ADC_CH_GAIN_16X_gc = (0x04<<2), /* 16x gain */ - ADC_CH_GAIN_32X_gc = (0x05<<2), /* 32x gain */ - ADC_CH_GAIN_64X_gc = (0x06<<2), /* 64x gain */ - ADC_CH_GAIN_DIV2_gc = (0x07<<2), /* x/2 gain */ -} ADC_CH_GAIN_t; - -/* Conversion result resolution */ -typedef enum ADC_RESOLUTION_enum -{ - ADC_RESOLUTION_12BIT_gc = (0x00<<1), /* 12-bit right-adjusted result */ - ADC_RESOLUTION_8BIT_gc = (0x02<<1), /* 8-bit right-adjusted result */ - ADC_RESOLUTION_LEFT12BIT_gc = (0x03<<1), /* 12-bit left-adjusted result */ -} ADC_RESOLUTION_t; - -/* Voltage reference selection */ -typedef enum ADC_REFSEL_enum -{ - ADC_REFSEL_INT1V_gc = (0x00<<4), /* Internal 1V */ - ADC_REFSEL_INTVCC_gc = (0x01<<4), /* Internal VCC / 1.6 */ - ADC_REFSEL_AREFA_gc = (0x02<<4), /* External reference on PORT A */ - ADC_REFSEL_AREFB_gc = (0x03<<4), /* External reference on PORT B */ - ADC_REFSEL_INTVCC2_gc = (0x04<<4), /* Internal VCC / 2 */ -} ADC_REFSEL_t; - -/* Event channel input selection */ -typedef enum ADC_EVSEL_enum -{ - ADC_EVSEL_0_gc = (0x00<<3), /* Event Channel 0 */ - ADC_EVSEL_1_gc = (0x01<<3), /* Event Channel 1 */ - ADC_EVSEL_2_gc = (0x02<<3), /* Event Channel 2 */ - ADC_EVSEL_3_gc = (0x03<<3), /* Event Channel 3 */ -} ADC_EVSEL_t; - -/* Event action selection */ -typedef enum ADC_EVACT_enum -{ - ADC_EVACT_NONE_gc = (0x00<<0), /* No event action */ - ADC_EVACT_CH0_gc = (0x01<<0), /* First event triggers channel 0 */ - ADC_EVACT_SYNCSWEEP_gc = (0x06<<0), /* The ADC is flushed and restarted for accurate timing */ -} ADC_EVACT_t; - -/* Interupt mode */ -typedef enum ADC_CH_INTMODE_enum -{ - ADC_CH_INTMODE_COMPLETE_gc = (0x00<<2), /* Interrupt on conversion complete */ - ADC_CH_INTMODE_BELOW_gc = (0x01<<2), /* Interrupt on result below compare value */ - ADC_CH_INTMODE_ABOVE_gc = (0x03<<2), /* Interrupt on result above compare value */ -} ADC_CH_INTMODE_t; - -/* Interrupt level */ -typedef enum ADC_CH_INTLVL_enum -{ - ADC_CH_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ - ADC_CH_INTLVL_LO_gc = (0x01<<0), /* Low level */ - ADC_CH_INTLVL_MED_gc = (0x02<<0), /* Medium level */ - ADC_CH_INTLVL_HI_gc = (0x03<<0), /* High level */ -} ADC_CH_INTLVL_t; - -/* Clock prescaler */ -typedef enum ADC_PRESCALER_enum -{ - ADC_PRESCALER_DIV4_gc = (0x00<<0), /* Divide clock by 4 */ - ADC_PRESCALER_DIV8_gc = (0x01<<0), /* Divide clock by 8 */ - ADC_PRESCALER_DIV16_gc = (0x02<<0), /* Divide clock by 16 */ - ADC_PRESCALER_DIV32_gc = (0x03<<0), /* Divide clock by 32 */ - ADC_PRESCALER_DIV64_gc = (0x04<<0), /* Divide clock by 64 */ - ADC_PRESCALER_DIV128_gc = (0x05<<0), /* Divide clock by 128 */ - ADC_PRESCALER_DIV256_gc = (0x06<<0), /* Divide clock by 256 */ - ADC_PRESCALER_DIV512_gc = (0x07<<0), /* Divide clock by 512 */ -} ADC_PRESCALER_t; - - -/* --------------------------------------------------------------------------- -AC - Analog Comparator --------------------------------------------------------------------------- -*/ - -/* Analog Comparator */ -typedef struct AC_struct -{ - register8_t AC0CTRL; /* Analog Comparator 0 Control */ - register8_t AC1CTRL; /* Analog Comparator 1 Control */ - register8_t AC0MUXCTRL; /* Analog Comparator 0 MUX Control */ - register8_t AC1MUXCTRL; /* Analog Comparator 1 MUX Control */ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t WINCTRL; /* Window Mode Control */ - register8_t STATUS; /* Status */ -} AC_t; - -/* Interrupt mode */ -typedef enum AC_INTMODE_enum -{ - AC_INTMODE_BOTHEDGES_gc = (0x00<<6), /* Interrupt on both edges */ - AC_INTMODE_FALLING_gc = (0x02<<6), /* Interrupt on falling edge */ - AC_INTMODE_RISING_gc = (0x03<<6), /* Interrupt on rising edge */ -} AC_INTMODE_t; - -/* Interrupt level */ -typedef enum AC_INTLVL_enum -{ - AC_INTLVL_OFF_gc = (0x00<<4), /* Interrupt disabled */ - AC_INTLVL_LO_gc = (0x01<<4), /* Low level */ - AC_INTLVL_MED_gc = (0x02<<4), /* Medium level */ - AC_INTLVL_HI_gc = (0x03<<4), /* High level */ -} AC_INTLVL_t; - -/* Hysteresis mode selection */ -typedef enum AC_HYSMODE_enum -{ - AC_HYSMODE_NO_gc = (0x00<<1), /* No hysteresis */ - AC_HYSMODE_SMALL_gc = (0x01<<1), /* Small hysteresis */ - AC_HYSMODE_LARGE_gc = (0x02<<1), /* Large hysteresis */ -} AC_HYSMODE_t; - -/* Positive input multiplexer selection */ -typedef enum AC_MUXPOS_enum -{ - AC_MUXPOS_PIN0_gc = (0x00<<3), /* Pin 0 */ - AC_MUXPOS_PIN1_gc = (0x01<<3), /* Pin 1 */ - AC_MUXPOS_PIN2_gc = (0x02<<3), /* Pin 2 */ - AC_MUXPOS_PIN3_gc = (0x03<<3), /* Pin 3 */ - AC_MUXPOS_PIN4_gc = (0x04<<3), /* Pin 4 */ - AC_MUXPOS_PIN5_gc = (0x05<<3), /* Pin 5 */ - AC_MUXPOS_PIN6_gc = (0x06<<3), /* Pin 6 */ -} AC_MUXPOS_t; - -/* Negative input multiplexer selection */ -typedef enum AC_MUXNEG_enum -{ - AC_MUXNEG_PIN0_gc = (0x00<<0), /* Pin 0 */ - AC_MUXNEG_PIN1_gc = (0x01<<0), /* Pin 1 */ - AC_MUXNEG_PIN3_gc = (0x02<<0), /* Pin 3 */ - AC_MUXNEG_PIN5_gc = (0x03<<0), /* Pin 5 */ - AC_MUXNEG_PIN7_gc = (0x04<<0), /* Pin 7 */ - AC_MUXNEG_BANDGAP_gc = (0x06<<0), /* Bandgap Reference */ - AC_MUXNEG_SCALER_gc = (0x07<<0), /* Internal voltage scaler */ -} AC_MUXNEG_t; - -/* Windows interrupt mode */ -typedef enum AC_WINTMODE_enum -{ - AC_WINTMODE_ABOVE_gc = (0x00<<2), /* Interrupt on above window */ - AC_WINTMODE_INSIDE_gc = (0x01<<2), /* Interrupt on inside window */ - AC_WINTMODE_BELOW_gc = (0x02<<2), /* Interrupt on below window */ - AC_WINTMODE_OUTSIDE_gc = (0x03<<2), /* Interrupt on outside window */ -} AC_WINTMODE_t; - -/* Window interrupt level */ -typedef enum AC_WINTLVL_enum -{ - AC_WINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ - AC_WINTLVL_LO_gc = (0x01<<0), /* Low priority */ - AC_WINTLVL_MED_gc = (0x02<<0), /* Medium priority */ - AC_WINTLVL_HI_gc = (0x03<<0), /* High priority */ -} AC_WINTLVL_t; - -/* Window mode state */ -typedef enum AC_WSTATE_enum -{ - AC_WSTATE_ABOVE_gc = (0x00<<6), /* Signal above window */ - AC_WSTATE_INSIDE_gc = (0x01<<6), /* Signal inside window */ - AC_WSTATE_BELOW_gc = (0x02<<6), /* Signal below window */ -} AC_WSTATE_t; - - -/* --------------------------------------------------------------------------- -RTC - Real-Time Counter --------------------------------------------------------------------------- -*/ - -/* Real-Time Counter */ -typedef struct RTC_struct -{ - register8_t CTRL; /* Control Register */ - register8_t STATUS; /* Status Register */ - register8_t INTCTRL; /* Interrupt Control Register */ - register8_t INTFLAGS; /* Interrupt Flags */ - register8_t TEMP; /* Temporary register */ - register8_t reserved_0x05; - register8_t reserved_0x06; - register8_t reserved_0x07; - _WORDREGISTER(CNT); /* Count Register */ - _WORDREGISTER(PER); /* Period Register */ - _WORDREGISTER(COMP); /* Compare Register */ -} RTC_t; - -/* Prescaler Factor */ -typedef enum RTC_PRESCALER_enum -{ - RTC_PRESCALER_OFF_gc = (0x00<<0), /* RTC Off */ - RTC_PRESCALER_DIV1_gc = (0x01<<0), /* RTC Clock */ - RTC_PRESCALER_DIV2_gc = (0x02<<0), /* RTC Clock / 2 */ - RTC_PRESCALER_DIV8_gc = (0x03<<0), /* RTC Clock / 8 */ - RTC_PRESCALER_DIV16_gc = (0x04<<0), /* RTC Clock / 16 */ - RTC_PRESCALER_DIV64_gc = (0x05<<0), /* RTC Clock / 64 */ - RTC_PRESCALER_DIV256_gc = (0x06<<0), /* RTC Clock / 256 */ - RTC_PRESCALER_DIV1024_gc = (0x07<<0), /* RTC Clock / 1024 */ -} RTC_PRESCALER_t; - -/* Compare Interrupt level */ -typedef enum RTC_COMPINTLVL_enum -{ - RTC_COMPINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ - RTC_COMPINTLVL_LO_gc = (0x01<<2), /* Low Level */ - RTC_COMPINTLVL_MED_gc = (0x02<<2), /* Medium Level */ - RTC_COMPINTLVL_HI_gc = (0x03<<2), /* High Level */ -} RTC_COMPINTLVL_t; - -/* Overflow Interrupt level */ -typedef enum RTC_OVFINTLVL_enum -{ - RTC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - RTC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ - RTC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ - RTC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ -} RTC_OVFINTLVL_t; - - -/* --------------------------------------------------------------------------- -TWI - Two-Wire Interface --------------------------------------------------------------------------- -*/ - -/* */ -typedef struct TWI_MASTER_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t CTRLC; /* Control Register C */ - register8_t STATUS; /* Status Register */ - register8_t BAUD; /* Baurd Rate Control Register */ - register8_t ADDR; /* Address Register */ - register8_t DATA; /* Data Register */ -} TWI_MASTER_t; - - -/* */ -typedef struct TWI_SLAVE_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t STATUS; /* Status Register */ - register8_t ADDR; /* Address Register */ - register8_t DATA; /* Data Register */ - register8_t ADDRMASK; /* Address Mask Register */ -} TWI_SLAVE_t; - - -/* Two-Wire Interface */ -typedef struct TWI_struct -{ - register8_t CTRL; /* TWI Common Control Register */ - TWI_MASTER_t MASTER; /* TWI master module */ - TWI_SLAVE_t SLAVE; /* TWI slave module */ -} TWI_t; - -/* SDA Hold Time */ -typedef enum TWI_SDAHOLD_enum -{ - TWI_SDAHOLD_OFF_gc = (0x00<<1), /* SDA Hold Time off */ - TWI_SDAHOLD_50NS_gc = (0x01<<1), /* SDA Hold Time 50 ns */ - TWI_SDAHOLD_300NS_gc = (0x02<<1), /* SDA Hold Time 300 ns */ - TWI_SDAHOLD_400NS_gc = (0x03<<1), /* SDA Hold Time 400 ns */ -} TWI_SDAHOLD_t; - -/* Master Interrupt Level */ -typedef enum TWI_MASTER_INTLVL_enum -{ - TWI_MASTER_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ - TWI_MASTER_INTLVL_LO_gc = (0x01<<6), /* Low Level */ - TWI_MASTER_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ - TWI_MASTER_INTLVL_HI_gc = (0x03<<6), /* High Level */ -} TWI_MASTER_INTLVL_t; - -/* Inactive Timeout */ -typedef enum TWI_MASTER_TIMEOUT_enum -{ - TWI_MASTER_TIMEOUT_DISABLED_gc = (0x00<<2), /* Bus Timeout Disabled */ - TWI_MASTER_TIMEOUT_50US_gc = (0x01<<2), /* 50 Microseconds */ - TWI_MASTER_TIMEOUT_100US_gc = (0x02<<2), /* 100 Microseconds */ - TWI_MASTER_TIMEOUT_200US_gc = (0x03<<2), /* 200 Microseconds */ -} TWI_MASTER_TIMEOUT_t; - -/* Master Command */ -typedef enum TWI_MASTER_CMD_enum -{ - TWI_MASTER_CMD_NOACT_gc = (0x00<<0), /* No Action */ - TWI_MASTER_CMD_REPSTART_gc = (0x01<<0), /* Issue Repeated Start Condition */ - TWI_MASTER_CMD_RECVTRANS_gc = (0x02<<0), /* Receive or Transmit Data */ - TWI_MASTER_CMD_STOP_gc = (0x03<<0), /* Issue Stop Condition */ -} TWI_MASTER_CMD_t; - -/* Master Bus State */ -typedef enum TWI_MASTER_BUSSTATE_enum -{ - TWI_MASTER_BUSSTATE_UNKNOWN_gc = (0x00<<0), /* Unknown Bus State */ - TWI_MASTER_BUSSTATE_IDLE_gc = (0x01<<0), /* Bus is Idle */ - TWI_MASTER_BUSSTATE_OWNER_gc = (0x02<<0), /* This Module Controls The Bus */ - TWI_MASTER_BUSSTATE_BUSY_gc = (0x03<<0), /* The Bus is Busy */ -} TWI_MASTER_BUSSTATE_t; - -/* Slave Interrupt Level */ -typedef enum TWI_SLAVE_INTLVL_enum -{ - TWI_SLAVE_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ - TWI_SLAVE_INTLVL_LO_gc = (0x01<<6), /* Low Level */ - TWI_SLAVE_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ - TWI_SLAVE_INTLVL_HI_gc = (0x03<<6), /* High Level */ -} TWI_SLAVE_INTLVL_t; - -/* Slave Command */ -typedef enum TWI_SLAVE_CMD_enum -{ - TWI_SLAVE_CMD_NOACT_gc = (0x00<<0), /* No Action */ - TWI_SLAVE_CMD_COMPTRANS_gc = (0x02<<0), /* Used To Complete a Transaction */ - TWI_SLAVE_CMD_RESPONSE_gc = (0x03<<0), /* Used in Response to Address/Data Interrupt */ -} TWI_SLAVE_CMD_t; - - -/* --------------------------------------------------------------------------- -USB - USB --------------------------------------------------------------------------- -*/ - -/* USB Endpoint */ -typedef struct USB_EP_struct -{ - register8_t STATUS; /* Endpoint Status */ - register8_t CTRL; /* Endpoint Control */ - _WORDREGISTER(CNT); /* USB Endpoint Counter */ - _WORDREGISTER(DATAPTR); /* Data Pointer */ - _WORDREGISTER(AUXDATA); /* Auxiliary Data */ -} USB_EP_t; - - -/* Universal Serial Bus */ -typedef struct USB_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t STATUS; /* Status Register */ - register8_t ADDR; /* Address Register */ - register8_t FIFOWP; /* FIFO Write Pointer Register */ - register8_t FIFORP; /* FIFO Read Pointer Register */ - _WORDREGISTER(EPPTR); /* Endpoint Configuration Table Pointer */ - register8_t INTCTRLA; /* Interrupt Control Register A */ - register8_t INTCTRLB; /* Interrupt Control Register B */ - register8_t INTFLAGSACLR; /* Clear Interrupt Flag Register A */ - register8_t INTFLAGSASET; /* Set Interrupt Flag Register A */ - register8_t INTFLAGSBCLR; /* Clear Interrupt Flag Register B */ - register8_t INTFLAGSBSET; /* Set Interrupt Flag Register B */ - register8_t reserved_0x0E; - register8_t reserved_0x0F; - register8_t reserved_0x10; - register8_t reserved_0x11; - register8_t reserved_0x12; - register8_t reserved_0x13; - register8_t reserved_0x14; - register8_t reserved_0x15; - register8_t reserved_0x16; - register8_t reserved_0x17; - register8_t reserved_0x18; - register8_t reserved_0x19; - register8_t reserved_0x1A; - register8_t reserved_0x1B; - register8_t reserved_0x1C; - register8_t reserved_0x1D; - register8_t reserved_0x1E; - register8_t reserved_0x1F; - register8_t reserved_0x20; - register8_t reserved_0x21; - register8_t reserved_0x22; - register8_t reserved_0x23; - register8_t reserved_0x24; - register8_t reserved_0x25; - register8_t reserved_0x26; - register8_t reserved_0x27; - register8_t reserved_0x28; - register8_t reserved_0x29; - register8_t reserved_0x2A; - register8_t reserved_0x2B; - register8_t reserved_0x2C; - register8_t reserved_0x2D; - register8_t reserved_0x2E; - register8_t reserved_0x2F; - register8_t reserved_0x30; - register8_t reserved_0x31; - register8_t reserved_0x32; - register8_t reserved_0x33; - register8_t reserved_0x34; - register8_t reserved_0x35; - register8_t reserved_0x36; - register8_t reserved_0x37; - register8_t reserved_0x38; - register8_t reserved_0x39; - register8_t CAL0; /* Calibration Byte 0 */ - register8_t CAL1; /* Calibration Byte 1 */ -} USB_t; - - -/* USB Endpoint Table */ -typedef struct USB_EP_TABLE_struct -{ - USB_EP_t EP0OUT; /* Endpoint 0 */ - USB_EP_t EP0IN; /* Endpoint 0 */ - USB_EP_t EP1OUT; /* Endpoint 1 */ - USB_EP_t EP1IN; /* Endpoint 1 */ - USB_EP_t EP2OUT; /* Endpoint 2 */ - USB_EP_t EP2IN; /* Endpoint 2 */ - USB_EP_t EP3OUT; /* Endpoint 3 */ - USB_EP_t EP3IN; /* Endpoint 3 */ - USB_EP_t EP4OUT; /* Endpoint 4 */ - USB_EP_t EP4IN; /* Endpoint 4 */ - USB_EP_t EP5OUT; /* Endpoint 5 */ - USB_EP_t EP5IN; /* Endpoint 5 */ - USB_EP_t EP6OUT; /* Endpoint 6 */ - USB_EP_t EP6IN; /* Endpoint 6 */ - USB_EP_t EP7OUT; /* Endpoint 7 */ - USB_EP_t EP7IN; /* Endpoint 7 */ - USB_EP_t EP8OUT; /* Endpoint 8 */ - USB_EP_t EP8IN; /* Endpoint 8 */ - USB_EP_t EP9OUT; /* Endpoint 9 */ - USB_EP_t EP9IN; /* Endpoint 9 */ - USB_EP_t EP10OUT; /* Endpoint 10 */ - USB_EP_t EP10IN; /* Endpoint 10 */ - USB_EP_t EP11OUT; /* Endpoint 11 */ - USB_EP_t EP11IN; /* Endpoint 11 */ - USB_EP_t EP12OUT; /* Endpoint 12 */ - USB_EP_t EP12IN; /* Endpoint 12 */ - USB_EP_t EP13OUT; /* Endpoint 13 */ - USB_EP_t EP13IN; /* Endpoint 13 */ - USB_EP_t EP14OUT; /* Endpoint 14 */ - USB_EP_t EP14IN; /* Endpoint 14 */ - USB_EP_t EP15OUT; /* Endpoint 15 */ - USB_EP_t EP15IN; /* Endpoint 15 */ - register8_t reserved_0x100; - register8_t reserved_0x101; - register8_t reserved_0x102; - register8_t reserved_0x103; - register8_t reserved_0x104; - register8_t reserved_0x105; - register8_t reserved_0x106; - register8_t reserved_0x107; - register8_t reserved_0x108; - register8_t reserved_0x109; - register8_t reserved_0x10A; - register8_t reserved_0x10B; - register8_t reserved_0x10C; - register8_t reserved_0x10D; - register8_t reserved_0x10E; - register8_t reserved_0x10F; - register8_t FRAMENUML; /* Frame Number Low Byte */ - register8_t FRAMENUMH; /* Frame Number High Byte */ -} USB_EP_TABLE_t; - -/* Interrupt level */ -typedef enum USB_INTLVL_enum -{ - USB_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ - USB_INTLVL_LO_gc = (0x01<<0), /* Low level */ - USB_INTLVL_MED_gc = (0x02<<0), /* Medium level */ - USB_INTLVL_HI_gc = (0x03<<0), /* High level */ -} USB_INTLVL_t; - -/* USB Endpoint Type */ -typedef enum USB_EP_TYPE_enum -{ - USB_EP_TYPE_DISABLE_gc = (0x00<<6), /* Endpoint Disabled */ - USB_EP_TYPE_CONTROL_gc = (0x01<<6), /* Control */ - USB_EP_TYPE_BULK_gc = (0x02<<6), /* Bulk/Interrupt */ - USB_EP_TYPE_ISOCHRONOUS_gc = (0x03<<6), /* Isochronous */ -} USB_EP_TYPE_t; - -/* USB Endpoint Buffersize */ -typedef enum USB_EP_BUFSIZE_enum -{ - USB_EP_BUFSIZE_8_gc = (0x00<<0), /* 8 bytes buffer size */ - USB_EP_BUFSIZE_16_gc = (0x01<<0), /* 16 bytes buffer size */ - USB_EP_BUFSIZE_32_gc = (0x02<<0), /* 32 bytes buffer size */ - USB_EP_BUFSIZE_64_gc = (0x03<<0), /* 64 bytes buffer size */ - USB_EP_BUFSIZE_128_gc = (0x04<<0), /* 128 bytes buffer size */ - USB_EP_BUFSIZE_256_gc = (0x05<<0), /* 256 bytes buffer size */ - USB_EP_BUFSIZE_512_gc = (0x06<<0), /* 512 bytes buffer size */ - USB_EP_BUFSIZE_1023_gc = (0x07<<0), /* 1023 bytes buffer size */ -} USB_EP_BUFSIZE_t; - - -/* --------------------------------------------------------------------------- -PORT - I/O Port Configuration --------------------------------------------------------------------------- -*/ - -/* I/O Ports */ -typedef struct PORT_struct -{ - register8_t DIR; /* I/O Port Data Direction */ - register8_t DIRSET; /* I/O Port Data Direction Set */ - register8_t DIRCLR; /* I/O Port Data Direction Clear */ - register8_t DIRTGL; /* I/O Port Data Direction Toggle */ - register8_t OUT; /* I/O Port Output */ - register8_t OUTSET; /* I/O Port Output Set */ - register8_t OUTCLR; /* I/O Port Output Clear */ - register8_t OUTTGL; /* I/O Port Output Toggle */ - register8_t IN; /* I/O port Input */ - register8_t INTCTRL; /* Interrupt Control Register */ - register8_t INT0MASK; /* Port Interrupt 0 Mask */ - register8_t INT1MASK; /* Port Interrupt 1 Mask */ - register8_t INTFLAGS; /* Interrupt Flag Register */ - register8_t reserved_0x0D; - register8_t REMAP; /* I/O Port Pin Remap Register */ - register8_t reserved_0x0F; - register8_t PIN0CTRL; /* Pin 0 Control Register */ - register8_t PIN1CTRL; /* Pin 1 Control Register */ - register8_t PIN2CTRL; /* Pin 2 Control Register */ - register8_t PIN3CTRL; /* Pin 3 Control Register */ - register8_t PIN4CTRL; /* Pin 4 Control Register */ - register8_t PIN5CTRL; /* Pin 5 Control Register */ - register8_t PIN6CTRL; /* Pin 6 Control Register */ - register8_t PIN7CTRL; /* Pin 7 Control Register */ -} PORT_t; - -/* Port Interrupt 0 Level */ -typedef enum PORT_INT0LVL_enum -{ - PORT_INT0LVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - PORT_INT0LVL_LO_gc = (0x01<<0), /* Low Level */ - PORT_INT0LVL_MED_gc = (0x02<<0), /* Medium Level */ - PORT_INT0LVL_HI_gc = (0x03<<0), /* High Level */ -} PORT_INT0LVL_t; - -/* Port Interrupt 1 Level */ -typedef enum PORT_INT1LVL_enum -{ - PORT_INT1LVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ - PORT_INT1LVL_LO_gc = (0x01<<2), /* Low Level */ - PORT_INT1LVL_MED_gc = (0x02<<2), /* Medium Level */ - PORT_INT1LVL_HI_gc = (0x03<<2), /* High Level */ -} PORT_INT1LVL_t; - -/* Output/Pull Configuration */ -typedef enum PORT_OPC_enum -{ - PORT_OPC_TOTEM_gc = (0x00<<3), /* Totempole */ - PORT_OPC_BUSKEEPER_gc = (0x01<<3), /* Totempole w/ Bus keeper on Input and Output */ - PORT_OPC_PULLDOWN_gc = (0x02<<3), /* Totempole w/ Pull-down on Input */ - PORT_OPC_PULLUP_gc = (0x03<<3), /* Totempole w/ Pull-up on Input */ - PORT_OPC_WIREDOR_gc = (0x04<<3), /* Wired OR */ - PORT_OPC_WIREDAND_gc = (0x05<<3), /* Wired AND */ - PORT_OPC_WIREDORPULL_gc = (0x06<<3), /* Wired OR w/ Pull-down */ - PORT_OPC_WIREDANDPULL_gc = (0x07<<3), /* Wired AND w/ Pull-up */ -} PORT_OPC_t; - -/* Input/Sense Configuration */ -typedef enum PORT_ISC_enum -{ - PORT_ISC_BOTHEDGES_gc = (0x00<<0), /* Sense Both Edges */ - PORT_ISC_RISING_gc = (0x01<<0), /* Sense Rising Edge */ - PORT_ISC_FALLING_gc = (0x02<<0), /* Sense Falling Edge */ - PORT_ISC_LEVEL_gc = (0x03<<0), /* Sense Level (Transparent For Events) */ - PORT_ISC_INPUT_DISABLE_gc = (0x07<<0), /* Disable Digital Input Buffer */ -} PORT_ISC_t; - - -/* --------------------------------------------------------------------------- -TC - 16-bit Timer/Counter With PWM --------------------------------------------------------------------------- -*/ - -/* 16-bit Timer/Counter 0 */ -typedef struct TC0_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t CTRLC; /* Control register C */ - register8_t CTRLD; /* Control Register D */ - register8_t CTRLE; /* Control Register E */ - register8_t reserved_0x05; - register8_t INTCTRLA; /* Interrupt Control Register A */ - register8_t INTCTRLB; /* Interrupt Control Register B */ - register8_t CTRLFCLR; /* Control Register F Clear */ - register8_t CTRLFSET; /* Control Register F Set */ - register8_t CTRLGCLR; /* Control Register G Clear */ - register8_t CTRLGSET; /* Control Register G Set */ - register8_t INTFLAGS; /* Interrupt Flag Register */ - register8_t reserved_0x0D; - register8_t reserved_0x0E; - register8_t TEMP; /* Temporary Register For 16-bit Access */ - register8_t reserved_0x10; - register8_t reserved_0x11; - register8_t reserved_0x12; - register8_t reserved_0x13; - register8_t reserved_0x14; - register8_t reserved_0x15; - register8_t reserved_0x16; - register8_t reserved_0x17; - register8_t reserved_0x18; - register8_t reserved_0x19; - register8_t reserved_0x1A; - register8_t reserved_0x1B; - register8_t reserved_0x1C; - register8_t reserved_0x1D; - register8_t reserved_0x1E; - register8_t reserved_0x1F; - _WORDREGISTER(CNT); /* Count */ - register8_t reserved_0x22; - register8_t reserved_0x23; - register8_t reserved_0x24; - register8_t reserved_0x25; - _WORDREGISTER(PER); /* Period */ - _WORDREGISTER(CCA); /* Compare or Capture A */ - _WORDREGISTER(CCB); /* Compare or Capture B */ - _WORDREGISTER(CCC); /* Compare or Capture C */ - _WORDREGISTER(CCD); /* Compare or Capture D */ - register8_t reserved_0x30; - register8_t reserved_0x31; - register8_t reserved_0x32; - register8_t reserved_0x33; - register8_t reserved_0x34; - register8_t reserved_0x35; - _WORDREGISTER(PERBUF); /* Period Buffer */ - _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ - _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ - _WORDREGISTER(CCCBUF); /* Compare Or Capture C Buffer */ - _WORDREGISTER(CCDBUF); /* Compare Or Capture D Buffer */ -} TC0_t; - - -/* 16-bit Timer/Counter 1 */ -typedef struct TC1_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t CTRLC; /* Control register C */ - register8_t CTRLD; /* Control Register D */ - register8_t CTRLE; /* Control Register E */ - register8_t reserved_0x05; - register8_t INTCTRLA; /* Interrupt Control Register A */ - register8_t INTCTRLB; /* Interrupt Control Register B */ - register8_t CTRLFCLR; /* Control Register F Clear */ - register8_t CTRLFSET; /* Control Register F Set */ - register8_t CTRLGCLR; /* Control Register G Clear */ - register8_t CTRLGSET; /* Control Register G Set */ - register8_t INTFLAGS; /* Interrupt Flag Register */ - register8_t reserved_0x0D; - register8_t reserved_0x0E; - register8_t TEMP; /* Temporary Register For 16-bit Access */ - register8_t reserved_0x10; - register8_t reserved_0x11; - register8_t reserved_0x12; - register8_t reserved_0x13; - register8_t reserved_0x14; - register8_t reserved_0x15; - register8_t reserved_0x16; - register8_t reserved_0x17; - register8_t reserved_0x18; - register8_t reserved_0x19; - register8_t reserved_0x1A; - register8_t reserved_0x1B; - register8_t reserved_0x1C; - register8_t reserved_0x1D; - register8_t reserved_0x1E; - register8_t reserved_0x1F; - _WORDREGISTER(CNT); /* Count */ - register8_t reserved_0x22; - register8_t reserved_0x23; - register8_t reserved_0x24; - register8_t reserved_0x25; - _WORDREGISTER(PER); /* Period */ - _WORDREGISTER(CCA); /* Compare or Capture A */ - _WORDREGISTER(CCB); /* Compare or Capture B */ - register8_t reserved_0x2C; - register8_t reserved_0x2D; - register8_t reserved_0x2E; - register8_t reserved_0x2F; - register8_t reserved_0x30; - register8_t reserved_0x31; - register8_t reserved_0x32; - register8_t reserved_0x33; - register8_t reserved_0x34; - register8_t reserved_0x35; - _WORDREGISTER(PERBUF); /* Period Buffer */ - _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ - _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ -} TC1_t; - -/* Clock Selection */ -typedef enum TC_CLKSEL_enum -{ - TC_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */ - TC_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */ - TC_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */ - TC_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */ - TC_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */ - TC_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */ - TC_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */ - TC_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */ - TC_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */ - TC_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */ - TC_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */ - TC_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */ -} TC_CLKSEL_t; - -/* Waveform Generation Mode */ -typedef enum TC_WGMODE_enum -{ - TC_WGMODE_NORMAL_gc = (0x00<<0), /* Normal Mode */ - TC_WGMODE_FRQ_gc = (0x01<<0), /* Frequency Generation Mode */ - TC_WGMODE_SINGLESLOPE_gc = (0x03<<0), /* Single Slope */ - TC_WGMODE_SS_gc = (0x03<<0), /* Single Slope */ - TC_WGMODE_DSTOP_gc = (0x05<<0), /* Dual Slope, Update on TOP */ - TC_WGMODE_DS_T_gc = (0x05<<0), /* Dual Slope, Update on TOP */ - TC_WGMODE_DSBOTH_gc = (0x06<<0), /* Dual Slope, Update on both TOP and BOTTOM */ - TC_WGMODE_DS_TB_gc = (0x06<<0), /* Dual Slope, Update on both TOP and BOTTOM */ - TC_WGMODE_DSBOTTOM_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */ - TC_WGMODE_DS_B_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */ -} TC_WGMODE_t; - -/* Byte Mode */ -typedef enum TC_BYTEM_enum -{ - TC_BYTEM_NORMAL_gc = (0x00<<0), /* 16-bit mode */ - TC_BYTEM_BYTEMODE_gc = (0x01<<0), /* Timer/Counter operating in byte mode only */ - TC_BYTEM_SPLITMODE_gc = (0x02<<0), /* Timer/Counter split into two 8-bit Counters (TC2) */ -} TC_BYTEM_t; - -/* Event Action */ -typedef enum TC_EVACT_enum -{ - TC_EVACT_OFF_gc = (0x00<<5), /* No Event Action */ - TC_EVACT_CAPT_gc = (0x01<<5), /* Input Capture */ - TC_EVACT_UPDOWN_gc = (0x02<<5), /* Externally Controlled Up/Down Count */ - TC_EVACT_QDEC_gc = (0x03<<5), /* Quadrature Decode */ - TC_EVACT_RESTART_gc = (0x04<<5), /* Restart */ - TC_EVACT_FRQ_gc = (0x05<<5), /* Frequency Capture */ - TC_EVACT_PW_gc = (0x06<<5), /* Pulse-width Capture */ -} TC_EVACT_t; - -/* Event Selection */ -typedef enum TC_EVSEL_enum -{ - TC_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ - TC_EVSEL_CH0_gc = (0x08<<0), /* Event Channel 0 */ - TC_EVSEL_CH1_gc = (0x09<<0), /* Event Channel 1 */ - TC_EVSEL_CH2_gc = (0x0A<<0), /* Event Channel 2 */ - TC_EVSEL_CH3_gc = (0x0B<<0), /* Event Channel 3 */ -} TC_EVSEL_t; - -/* Error Interrupt Level */ -typedef enum TC_ERRINTLVL_enum -{ - TC_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ - TC_ERRINTLVL_LO_gc = (0x01<<2), /* Low Level */ - TC_ERRINTLVL_MED_gc = (0x02<<2), /* Medium Level */ - TC_ERRINTLVL_HI_gc = (0x03<<2), /* High Level */ -} TC_ERRINTLVL_t; - -/* Overflow Interrupt Level */ -typedef enum TC_OVFINTLVL_enum -{ - TC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - TC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ - TC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ - TC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ -} TC_OVFINTLVL_t; - -/* Compare or Capture D Interrupt Level */ -typedef enum TC_CCDINTLVL_enum -{ - TC_CCDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ - TC_CCDINTLVL_LO_gc = (0x01<<6), /* Low Level */ - TC_CCDINTLVL_MED_gc = (0x02<<6), /* Medium Level */ - TC_CCDINTLVL_HI_gc = (0x03<<6), /* High Level */ -} TC_CCDINTLVL_t; - -/* Compare or Capture C Interrupt Level */ -typedef enum TC_CCCINTLVL_enum -{ - TC_CCCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ - TC_CCCINTLVL_LO_gc = (0x01<<4), /* Low Level */ - TC_CCCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ - TC_CCCINTLVL_HI_gc = (0x03<<4), /* High Level */ -} TC_CCCINTLVL_t; - -/* Compare or Capture B Interrupt Level */ -typedef enum TC_CCBINTLVL_enum -{ - TC_CCBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ - TC_CCBINTLVL_LO_gc = (0x01<<2), /* Low Level */ - TC_CCBINTLVL_MED_gc = (0x02<<2), /* Medium Level */ - TC_CCBINTLVL_HI_gc = (0x03<<2), /* High Level */ -} TC_CCBINTLVL_t; - -/* Compare or Capture A Interrupt Level */ -typedef enum TC_CCAINTLVL_enum -{ - TC_CCAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - TC_CCAINTLVL_LO_gc = (0x01<<0), /* Low Level */ - TC_CCAINTLVL_MED_gc = (0x02<<0), /* Medium Level */ - TC_CCAINTLVL_HI_gc = (0x03<<0), /* High Level */ -} TC_CCAINTLVL_t; - -/* Timer/Counter Command */ -typedef enum TC_CMD_enum -{ - TC_CMD_NONE_gc = (0x00<<2), /* No Command */ - TC_CMD_UPDATE_gc = (0x01<<2), /* Force Update */ - TC_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ - TC_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ -} TC_CMD_t; - - -/* --------------------------------------------------------------------------- -TC2 - 16-bit Timer/Counter type 2 --------------------------------------------------------------------------- -*/ - -/* 16-bit Timer/Counter type 2 */ -typedef struct TC2_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t CTRLC; /* Control register C */ - register8_t reserved_0x03; - register8_t CTRLE; /* Control Register E */ - register8_t reserved_0x05; - register8_t INTCTRLA; /* Interrupt Control Register A */ - register8_t INTCTRLB; /* Interrupt Control Register B */ - register8_t reserved_0x08; - register8_t CTRLF; /* Control Register F */ - register8_t reserved_0x0A; - register8_t reserved_0x0B; - register8_t INTFLAGS; /* Interrupt Flag Register */ - register8_t reserved_0x0D; - register8_t reserved_0x0E; - register8_t reserved_0x0F; - register8_t reserved_0x10; - register8_t reserved_0x11; - register8_t reserved_0x12; - register8_t reserved_0x13; - register8_t reserved_0x14; - register8_t reserved_0x15; - register8_t reserved_0x16; - register8_t reserved_0x17; - register8_t reserved_0x18; - register8_t reserved_0x19; - register8_t reserved_0x1A; - register8_t reserved_0x1B; - register8_t reserved_0x1C; - register8_t reserved_0x1D; - register8_t reserved_0x1E; - register8_t reserved_0x1F; - register8_t LCNT; /* Low Byte Count */ - register8_t HCNT; /* High Byte Count */ - register8_t reserved_0x22; - register8_t reserved_0x23; - register8_t reserved_0x24; - register8_t reserved_0x25; - register8_t LPER; /* Low Byte Period */ - register8_t HPER; /* High Byte Period */ - register8_t LCMPA; /* Low Byte Compare A */ - register8_t HCMPA; /* High Byte Compare A */ - register8_t LCMPB; /* Low Byte Compare B */ - register8_t HCMPB; /* High Byte Compare B */ - register8_t LCMPC; /* Low Byte Compare C */ - register8_t HCMPC; /* High Byte Compare C */ - register8_t LCMPD; /* Low Byte Compare D */ - register8_t HCMPD; /* High Byte Compare D */ -} TC2_t; - -/* Clock Selection */ -typedef enum TC2_CLKSEL_enum -{ - TC2_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */ - TC2_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */ - TC2_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */ - TC2_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */ - TC2_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */ - TC2_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */ - TC2_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */ - TC2_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */ - TC2_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */ - TC2_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */ - TC2_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */ - TC2_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */ -} TC2_CLKSEL_t; - -/* Byte Mode */ -typedef enum TC2_BYTEM_enum -{ - TC2_BYTEM_NORMAL_gc = (0x00<<0), /* 16-bit mode */ - TC2_BYTEM_BYTEMODE_gc = (0x01<<0), /* Timer/Counter operating in byte mode only (TC2) */ - TC2_BYTEM_SPLITMODE_gc = (0x02<<0), /* Timer/Counter split into two 8-bit Counters */ -} TC2_BYTEM_t; - -/* High Byte Underflow Interrupt Level */ -typedef enum TC2_HUNFINTLVL_enum -{ - TC2_HUNFINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ - TC2_HUNFINTLVL_LO_gc = (0x01<<2), /* Low Level */ - TC2_HUNFINTLVL_MED_gc = (0x02<<2), /* Medium Level */ - TC2_HUNFINTLVL_HI_gc = (0x03<<2), /* High Level */ -} TC2_HUNFINTLVL_t; - -/* Low Byte Underflow Interrupt Level */ -typedef enum TC2_LUNFINTLVL_enum -{ - TC2_LUNFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - TC2_LUNFINTLVL_LO_gc = (0x01<<0), /* Low Level */ - TC2_LUNFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ - TC2_LUNFINTLVL_HI_gc = (0x03<<0), /* High Level */ -} TC2_LUNFINTLVL_t; - -/* Low Byte Compare D Interrupt Level */ -typedef enum TC2_LCMPDINTLVL_enum -{ - TC2_LCMPDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ - TC2_LCMPDINTLVL_LO_gc = (0x01<<6), /* Low Level */ - TC2_LCMPDINTLVL_MED_gc = (0x02<<6), /* Medium Level */ - TC2_LCMPDINTLVL_HI_gc = (0x03<<6), /* High Level */ -} TC2_LCMPDINTLVL_t; - -/* Low Byte Compare C Interrupt Level */ -typedef enum TC2_LCMPCINTLVL_enum -{ - TC2_LCMPCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ - TC2_LCMPCINTLVL_LO_gc = (0x01<<4), /* Low Level */ - TC2_LCMPCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ - TC2_LCMPCINTLVL_HI_gc = (0x03<<4), /* High Level */ -} TC2_LCMPCINTLVL_t; - -/* Low Byte Compare B Interrupt Level */ -typedef enum TC2_LCMPBINTLVL_enum -{ - TC2_LCMPBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ - TC2_LCMPBINTLVL_LO_gc = (0x01<<2), /* Low Level */ - TC2_LCMPBINTLVL_MED_gc = (0x02<<2), /* Medium Level */ - TC2_LCMPBINTLVL_HI_gc = (0x03<<2), /* High Level */ -} TC2_LCMPBINTLVL_t; - -/* Low Byte Compare A Interrupt Level */ -typedef enum TC2_LCMPAINTLVL_enum -{ - TC2_LCMPAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - TC2_LCMPAINTLVL_LO_gc = (0x01<<0), /* Low Level */ - TC2_LCMPAINTLVL_MED_gc = (0x02<<0), /* Medium Level */ - TC2_LCMPAINTLVL_HI_gc = (0x03<<0), /* High Level */ -} TC2_LCMPAINTLVL_t; - -/* Timer/Counter Command */ -typedef enum TC2_CMD_enum -{ - TC2_CMD_NONE_gc = (0x00<<2), /* No Command */ - TC2_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ - TC2_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ -} TC2_CMD_t; - -/* Timer/Counter Command */ -typedef enum TC2_CMDEN_enum -{ - TC2_CMDEN_LOW_gc = (0x01<<0), /* Low Byte Timer/Counter */ - TC2_CMDEN_HIGH_gc = (0x02<<0), /* High Byte Timer/Counter */ - TC2_CMDEN_BOTH_gc = (0x03<<0), /* Both Low Byte and High Byte Timer/Counters */ -} TC2_CMDEN_t; - - -/* --------------------------------------------------------------------------- -AWEX - Timer/Counter Advanced Waveform Extension --------------------------------------------------------------------------- -*/ - -/* Advanced Waveform Extension */ -typedef struct AWEX_struct -{ - register8_t CTRL; /* Control Register */ - register8_t reserved_0x01; - register8_t FDEMASK; /* Fault Detection Event Mask */ - register8_t FDCTRL; /* Fault Detection Control Register */ - register8_t STATUS; /* Status Register */ - register8_t STATUSSET; /* Status Set Register */ - register8_t DTBOTH; /* Dead Time Both Sides */ - register8_t DTBOTHBUF; /* Dead Time Both Sides Buffer */ - register8_t DTLS; /* Dead Time Low Side */ - register8_t DTHS; /* Dead Time High Side */ - register8_t DTLSBUF; /* Dead Time Low Side Buffer */ - register8_t DTHSBUF; /* Dead Time High Side Buffer */ - register8_t OUTOVEN; /* Output Override Enable */ -} AWEX_t; - -/* Fault Detect Action */ -typedef enum AWEX_FDACT_enum -{ - AWEX_FDACT_NONE_gc = (0x00<<0), /* No Fault Protection */ - AWEX_FDACT_CLEAROE_gc = (0x01<<0), /* Clear Output Enable Bits */ - AWEX_FDACT_CLEARDIR_gc = (0x03<<0), /* Clear I/O Port Direction Bits */ -} AWEX_FDACT_t; - - -/* --------------------------------------------------------------------------- -HIRES - Timer/Counter High-Resolution Extension --------------------------------------------------------------------------- -*/ - -/* High-Resolution Extension */ -typedef struct HIRES_struct -{ - register8_t CTRLA; /* Control Register */ -} HIRES_t; - -/* High Resolution Enable */ -typedef enum HIRES_HREN_enum -{ - HIRES_HREN_NONE_gc = (0x00<<0), /* No Fault Protection */ - HIRES_HREN_TC0_gc = (0x01<<0), /* Enable High Resolution on Timer/Counter 0 */ - HIRES_HREN_TC1_gc = (0x02<<0), /* Enable High Resolution on Timer/Counter 1 */ - HIRES_HREN_BOTH_gc = (0x03<<0), /* Enable High Resolution both Timer/Counters */ -} HIRES_HREN_t; - - -/* --------------------------------------------------------------------------- -USART - Universal Asynchronous Receiver-Transmitter --------------------------------------------------------------------------- -*/ - -/* Universal Synchronous/Asynchronous Receiver/Transmitter */ -typedef struct USART_struct -{ - register8_t DATA; /* Data Register */ - register8_t STATUS; /* Status Register */ - register8_t reserved_0x02; - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t CTRLC; /* Control Register C */ - register8_t BAUDCTRLA; /* Baud Rate Control Register A */ - register8_t BAUDCTRLB; /* Baud Rate Control Register B */ -} USART_t; - -/* Receive Complete Interrupt level */ -typedef enum USART_RXCINTLVL_enum -{ - USART_RXCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ - USART_RXCINTLVL_LO_gc = (0x01<<4), /* Low Level */ - USART_RXCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ - USART_RXCINTLVL_HI_gc = (0x03<<4), /* High Level */ -} USART_RXCINTLVL_t; - -/* Transmit Complete Interrupt level */ -typedef enum USART_TXCINTLVL_enum -{ - USART_TXCINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ - USART_TXCINTLVL_LO_gc = (0x01<<2), /* Low Level */ - USART_TXCINTLVL_MED_gc = (0x02<<2), /* Medium Level */ - USART_TXCINTLVL_HI_gc = (0x03<<2), /* High Level */ -} USART_TXCINTLVL_t; - -/* Data Register Empty Interrupt level */ -typedef enum USART_DREINTLVL_enum -{ - USART_DREINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - USART_DREINTLVL_LO_gc = (0x01<<0), /* Low Level */ - USART_DREINTLVL_MED_gc = (0x02<<0), /* Medium Level */ - USART_DREINTLVL_HI_gc = (0x03<<0), /* High Level */ -} USART_DREINTLVL_t; - -/* Character Size */ -typedef enum USART_CHSIZE_enum -{ - USART_CHSIZE_5BIT_gc = (0x00<<0), /* Character size: 5 bit */ - USART_CHSIZE_6BIT_gc = (0x01<<0), /* Character size: 6 bit */ - USART_CHSIZE_7BIT_gc = (0x02<<0), /* Character size: 7 bit */ - USART_CHSIZE_8BIT_gc = (0x03<<0), /* Character size: 8 bit */ - USART_CHSIZE_9BIT_gc = (0x07<<0), /* Character size: 9 bit */ -} USART_CHSIZE_t; - -/* Communication Mode */ -typedef enum USART_CMODE_enum -{ - USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6), /* Asynchronous Mode */ - USART_CMODE_SYNCHRONOUS_gc = (0x01<<6), /* Synchronous Mode */ - USART_CMODE_IRDA_gc = (0x02<<6), /* IrDA Mode */ - USART_CMODE_MSPI_gc = (0x03<<6), /* Master SPI Mode */ -} USART_CMODE_t; - -/* Parity Mode */ -typedef enum USART_PMODE_enum -{ - USART_PMODE_DISABLED_gc = (0x00<<4), /* No Parity */ - USART_PMODE_EVEN_gc = (0x02<<4), /* Even Parity */ - USART_PMODE_ODD_gc = (0x03<<4), /* Odd Parity */ -} USART_PMODE_t; - - -/* --------------------------------------------------------------------------- -SPI - Serial Peripheral Interface --------------------------------------------------------------------------- -*/ - -/* Serial Peripheral Interface */ -typedef struct SPI_struct -{ - register8_t CTRL; /* Control Register */ - register8_t INTCTRL; /* Interrupt Control Register */ - register8_t STATUS; /* Status Register */ - register8_t DATA; /* Data Register */ -} SPI_t; - -/* SPI Mode */ -typedef enum SPI_MODE_enum -{ - SPI_MODE_0_gc = (0x00<<2), /* SPI Mode 0 */ - SPI_MODE_1_gc = (0x01<<2), /* SPI Mode 1 */ - SPI_MODE_2_gc = (0x02<<2), /* SPI Mode 2 */ - SPI_MODE_3_gc = (0x03<<2), /* SPI Mode 3 */ -} SPI_MODE_t; - -/* Prescaler setting */ -typedef enum SPI_PRESCALER_enum -{ - SPI_PRESCALER_DIV4_gc = (0x00<<0), /* System Clock / 4 */ - SPI_PRESCALER_DIV16_gc = (0x01<<0), /* System Clock / 16 */ - SPI_PRESCALER_DIV64_gc = (0x02<<0), /* System Clock / 64 */ - SPI_PRESCALER_DIV128_gc = (0x03<<0), /* System Clock / 128 */ -} SPI_PRESCALER_t; - -/* Interrupt level */ -typedef enum SPI_INTLVL_enum -{ - SPI_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - SPI_INTLVL_LO_gc = (0x01<<0), /* Low Level */ - SPI_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ - SPI_INTLVL_HI_gc = (0x03<<0), /* High Level */ -} SPI_INTLVL_t; - - -/* --------------------------------------------------------------------------- -IRCOM - IR Communication Module --------------------------------------------------------------------------- -*/ - -/* IR Communication Module */ -typedef struct IRCOM_struct -{ - register8_t CTRL; /* Control Register */ - register8_t TXPLCTRL; /* IrDA Transmitter Pulse Length Control Register */ - register8_t RXPLCTRL; /* IrDA Receiver Pulse Length Control Register */ -} IRCOM_t; - -/* Event channel selection */ -typedef enum IRDA_EVSEL_enum -{ - IRDA_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ - IRDA_EVSEL_0_gc = (0x08<<0), /* Event Channel 0 */ - IRDA_EVSEL_1_gc = (0x09<<0), /* Event Channel 1 */ - IRDA_EVSEL_2_gc = (0x0A<<0), /* Event Channel 2 */ - IRDA_EVSEL_3_gc = (0x0B<<0), /* Event Channel 3 */ -} IRDA_EVSEL_t; - - -/* --------------------------------------------------------------------------- -FUSE - Fuses and Lockbits --------------------------------------------------------------------------- -*/ - -/* Fuses */ -typedef struct NVM_FUSES_struct -{ - register8_t reserved_0x00; - register8_t FUSEBYTE1; /* Watchdog Configuration */ - register8_t FUSEBYTE2; /* Reset Configuration */ - register8_t reserved_0x03; - register8_t FUSEBYTE4; /* Start-up Configuration */ - register8_t FUSEBYTE5; /* EESAVE and BOD Level */ -} NVM_FUSES_t; - -/* Boot Loader Section Reset Vector */ -typedef enum BOOTRST_enum -{ - BOOTRST_BOOTLDR_gc = (0x00<<6), /* Boot Loader Reset */ - BOOTRST_APPLICATION_gc = (0x01<<6), /* Application Reset */ -} BOOTRST_t; - -/* Timer Oscillator pin location */ -typedef enum TOSCSEL_enum -{ - TOSCSEL_ALTERNATE_gc = (0x00<<5), /* TOSC1 / TOSC2 on separate pins */ - TOSCSEL_XTAL_gc = (0x01<<5), /* TOSC1 / TOSC2 shared with XTAL1 / XTAL2 */ -} TOSCSEL_t; - -/* BOD operation */ -typedef enum BOD_enum -{ - BOD_SAMPLED_gc = (0x01<<0), /* BOD enabled in sampled mode */ - BOD_CONTINUOUS_gc = (0x02<<0), /* BOD enabled continuously */ - BOD_DISABLED_gc = (0x03<<0), /* BOD Disabled */ -} BOD_t; - -/* BOD operation */ -typedef enum BODACT_enum -{ - BODACT_SAMPLED_gc = (0x01<<4), /* BOD enabled in sampled mode */ - BODACT_CONTINUOUS_gc = (0x02<<4), /* BOD enabled continuously */ - BODACT_DISABLED_gc = (0x03<<4), /* BOD Disabled */ -} BODACT_t; - -/* Watchdog (Window) Timeout Period */ -typedef enum WD_enum -{ - WD_8CLK_gc = (0x00<<4), /* 8 cycles (8ms @ 3.3V) */ - WD_16CLK_gc = (0x01<<4), /* 16 cycles (16ms @ 3.3V) */ - WD_32CLK_gc = (0x02<<4), /* 32 cycles (32ms @ 3.3V) */ - WD_64CLK_gc = (0x03<<4), /* 64 cycles (64ms @ 3.3V) */ - WD_128CLK_gc = (0x04<<4), /* 128 cycles (0.125s @ 3.3V) */ - WD_256CLK_gc = (0x05<<4), /* 256 cycles (0.25s @ 3.3V) */ - WD_512CLK_gc = (0x06<<4), /* 512 cycles (0.5s @ 3.3V) */ - WD_1KCLK_gc = (0x07<<4), /* 1K cycles (1s @ 3.3V) */ - WD_2KCLK_gc = (0x08<<4), /* 2K cycles (2s @ 3.3V) */ - WD_4KCLK_gc = (0x09<<4), /* 4K cycles (4s @ 3.3V) */ - WD_8KCLK_gc = (0x0A<<4), /* 8K cycles (8s @ 3.3V) */ -} WD_t; - -/* Watchdog (Window) Timeout Period */ -typedef enum WDP_enum -{ - WDP_8CLK_gc = (0x00<<0), /* 8 cycles (8ms @ 3.3V) */ - WDP_16CLK_gc = (0x01<<0), /* 16 cycles (16ms @ 3.3V) */ - WDP_32CLK_gc = (0x02<<0), /* 32 cycles (32ms @ 3.3V) */ - WDP_64CLK_gc = (0x03<<0), /* 64 cycles (64ms @ 3.3V) */ - WDP_128CLK_gc = (0x04<<0), /* 128 cycles (0.125s @ 3.3V) */ - WDP_256CLK_gc = (0x05<<0), /* 256 cycles (0.25s @ 3.3V) */ - WDP_512CLK_gc = (0x06<<0), /* 512 cycles (0.5s @ 3.3V) */ - WDP_1KCLK_gc = (0x07<<0), /* 1K cycles (1s @ 3.3V) */ - WDP_2KCLK_gc = (0x08<<0), /* 2K cycles (2s @ 3.3V) */ - WDP_4KCLK_gc = (0x09<<0), /* 4K cycles (4s @ 3.3V) */ - WDP_8KCLK_gc = (0x0A<<0), /* 8K cycles (8s @ 3.3V) */ -} WDP_t; - -/* Start-up Time */ -typedef enum SUT_enum -{ - SUT_0MS_gc = (0x03<<2), /* 0 ms */ - SUT_4MS_gc = (0x01<<2), /* 4 ms */ - SUT_64MS_gc = (0x00<<2), /* 64 ms */ -} SUT_t; - -/* Brownout Detection Voltage Level */ -typedef enum BODLVL_enum -{ - BODLVL_1V6_gc = (0x07<<0), /* 1.6 V */ - BODLVL_1V8_gc = (0x06<<0), /* 1.8 V */ - BODLVL_2V0_gc = (0x05<<0), /* 2.0 V */ - BODLVL_2V2_gc = (0x04<<0), /* 2.2 V */ - BODLVL_2V4_gc = (0x03<<0), /* 2.4 V */ - BODLVL_2V6_gc = (0x02<<0), /* 2.6 V */ - BODLVL_2V8_gc = (0x01<<0), /* 2.8 V */ - BODLVL_3V0_gc = (0x00<<0), /* 3.0 V */ -} BODLVL_t; - - -/* --------------------------------------------------------------------------- -LOCKBIT - Fuses and Lockbits --------------------------------------------------------------------------- -*/ - -/* Lock Bits */ -typedef struct NVM_LOCKBITS_struct -{ - register8_t LOCK_BITS; /* Lock Bits (Changed from LOCKBITS to avoid avr-libc collision) */ -} NVM_LOCKBITS_t; - -/* Boot lock bits - boot setcion */ -typedef enum FUSE_BLBB_enum -{ - FUSE_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ - FUSE_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ - FUSE_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ - FUSE_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ -} FUSE_BLBB_t; - -/* Boot lock bits - application section */ -typedef enum FUSE_BLBA_enum -{ - FUSE_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ - FUSE_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ - FUSE_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ - FUSE_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ -} FUSE_BLBA_t; - -/* Boot lock bits - application table section */ -typedef enum FUSE_BLBAT_enum -{ - FUSE_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ - FUSE_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ - FUSE_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ - FUSE_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ -} FUSE_BLBAT_t; - -/* Lock bits */ -typedef enum FUSE_LB_enum -{ - FUSE_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ - FUSE_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ - FUSE_LB_NOLOCK_gc = (0x03<<0), /* No locks */ -} FUSE_LB_t; - - -/* --------------------------------------------------------------------------- -SIGROW - Signature Row --------------------------------------------------------------------------- -*/ - -/* Production Signatures */ -typedef struct NVM_PROD_SIGNATURES_struct -{ - register8_t RCOSC2M; /* RCOSC 2 MHz Calibration Value B */ - register8_t RCOSC2MA; /* RCOSC 2 MHz Calibration Value A */ - register8_t RCOSC32K; /* RCOSC 32.768 kHz Calibration Value */ - register8_t RCOSC32M; /* RCOSC 32 MHz Calibration Value B */ - register8_t RCOSC32MA; /* RCOSC 32 MHz Calibration Value A */ - register8_t reserved_0x05; - register8_t reserved_0x06; - register8_t reserved_0x07; - register8_t LOTNUM0; /* Lot Number Byte 0, ASCII */ - register8_t LOTNUM1; /* Lot Number Byte 1, ASCII */ - register8_t LOTNUM2; /* Lot Number Byte 2, ASCII */ - register8_t LOTNUM3; /* Lot Number Byte 3, ASCII */ - register8_t LOTNUM4; /* Lot Number Byte 4, ASCII */ - register8_t LOTNUM5; /* Lot Number Byte 5, ASCII */ - register8_t reserved_0x0E; - register8_t reserved_0x0F; - register8_t WAFNUM; /* Wafer Number */ - register8_t reserved_0x11; - register8_t COORDX0; /* Wafer Coordinate X Byte 0 */ - register8_t COORDX1; /* Wafer Coordinate X Byte 1 */ - register8_t COORDY0; /* Wafer Coordinate Y Byte 0 */ - register8_t COORDY1; /* Wafer Coordinate Y Byte 1 */ - register8_t reserved_0x16; - register8_t reserved_0x17; - register8_t reserved_0x18; - register8_t reserved_0x19; - register8_t USBCAL0; /* USB Calibration Byte 0 */ - register8_t USBCAL1; /* USB Calibration Byte 1 */ - register8_t USBRCOSC; /* USB RCOSC Calibration Value B */ - register8_t USBRCOSCA; /* USB RCOSC Calibration Value A */ - register8_t reserved_0x1E; - register8_t reserved_0x1F; - register8_t ADCACAL0; /* ADCA Calibration Byte 0 */ - register8_t ADCACAL1; /* ADCA Calibration Byte 1 */ - register8_t reserved_0x22; - register8_t reserved_0x23; - register8_t reserved_0x24; - register8_t reserved_0x25; - register8_t reserved_0x26; - register8_t reserved_0x27; - register8_t reserved_0x28; - register8_t reserved_0x29; - register8_t reserved_0x2A; - register8_t reserved_0x2B; - register8_t reserved_0x2C; - register8_t reserved_0x2D; - register8_t TEMPSENSE0; /* Temperature Sensor Calibration Byte 0 */ - register8_t TEMPSENSE1; /* Temperature Sensor Calibration Byte 1 */ - register8_t reserved_0x30; - register8_t reserved_0x31; - register8_t reserved_0x32; - register8_t reserved_0x33; - register8_t reserved_0x34; - register8_t reserved_0x35; - register8_t reserved_0x36; - register8_t reserved_0x37; - register8_t reserved_0x38; - register8_t reserved_0x39; - register8_t reserved_0x3A; - register8_t reserved_0x3B; - register8_t reserved_0x3C; - register8_t reserved_0x3D; - register8_t reserved_0x3E; - register8_t reserved_0x3F; -} NVM_PROD_SIGNATURES_t; - -/* -========================================================================== -IO Module Instances. Mapped to memory. -========================================================================== -*/ - -#define VPORT0 (*(VPORT_t *) 0x0010) /* Virtual Port */ -#define VPORT1 (*(VPORT_t *) 0x0014) /* Virtual Port */ -#define VPORT2 (*(VPORT_t *) 0x0018) /* Virtual Port */ -#define VPORT3 (*(VPORT_t *) 0x001C) /* Virtual Port */ -#define OCD (*(OCD_t *) 0x002E) /* On-Chip Debug System */ -#define CLK (*(CLK_t *) 0x0040) /* Clock System */ -#define SLEEP (*(SLEEP_t *) 0x0048) /* Sleep Controller */ -#define OSC (*(OSC_t *) 0x0050) /* Oscillator */ -#define DFLLRC32M (*(DFLL_t *) 0x0060) /* DFLL */ -#define DFLLRC2M (*(DFLL_t *) 0x0068) /* DFLL */ -#define PR (*(PR_t *) 0x0070) /* Power Reduction */ -#define RST (*(RST_t *) 0x0078) /* Reset */ -#define WDT (*(WDT_t *) 0x0080) /* Watch-Dog Timer */ -#define MCU (*(MCU_t *) 0x0090) /* MCU Control */ -#define PMIC (*(PMIC_t *) 0x00A0) /* Programmable Multi-level Interrupt Controller */ -#define PORTCFG (*(PORTCFG_t *) 0x00B0) /* I/O port Configuration */ -#define CRC (*(CRC_t *) 0x00D0) /* Cyclic Redundancy Checker */ -#define EVSYS (*(EVSYS_t *) 0x0180) /* Event System */ -#define NVM (*(NVM_t *) 0x01C0) /* Non-volatile Memory Controller */ -#define ADCA (*(ADC_t *) 0x0200) /* Analog-to-Digital Converter */ -#define ACA (*(AC_t *) 0x0380) /* Analog Comparator */ -#define RTC (*(RTC_t *) 0x0400) /* Real-Time Counter */ -#define TWIC (*(TWI_t *) 0x0480) /* Two-Wire Interface */ -#define TWIE (*(TWI_t *) 0x04A0) /* Two-Wire Interface */ -#define USB (*(USB_t *) 0x04C0) /* Universal Serial Bus */ -#define PORTA (*(PORT_t *) 0x0600) /* I/O Ports */ -#define PORTB (*(PORT_t *) 0x0620) /* I/O Ports */ -#define PORTC (*(PORT_t *) 0x0640) /* I/O Ports */ -#define PORTD (*(PORT_t *) 0x0660) /* I/O Ports */ -#define PORTE (*(PORT_t *) 0x0680) /* I/O Ports */ -#define PORTF (*(PORT_t *) 0x06A0) /* I/O Ports */ -#define PORTR (*(PORT_t *) 0x07E0) /* I/O Ports */ -#define TCC0 (*(TC0_t *) 0x0800) /* 16-bit Timer/Counter 0 */ -#define TCC2 (*(TC2_t *) 0x0800) /* 16-bit Timer/Counter type 2 */ -#define TCC1 (*(TC1_t *) 0x0840) /* 16-bit Timer/Counter 1 */ -#define AWEXC (*(AWEX_t *) 0x0880) /* Advanced Waveform Extension */ -#define HIRESC (*(HIRES_t *) 0x0890) /* High-Resolution Extension */ -#define USARTC0 (*(USART_t *) 0x08A0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ -#define SPIC (*(SPI_t *) 0x08C0) /* Serial Peripheral Interface */ -#define IRCOM (*(IRCOM_t *) 0x08F8) /* IR Communication Module */ -#define TCD0 (*(TC0_t *) 0x0900) /* 16-bit Timer/Counter 0 */ -#define TCD2 (*(TC2_t *) 0x0900) /* 16-bit Timer/Counter type 2 */ -#define USARTD0 (*(USART_t *) 0x09A0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ -#define SPID (*(SPI_t *) 0x09C0) /* Serial Peripheral Interface */ -#define TCE0 (*(TC0_t *) 0x0A00) /* 16-bit Timer/Counter 0 */ -#define TCE2 (*(TC2_t *) 0x0A00) /* 16-bit Timer/Counter type 2 */ -#define USARTE0 (*(USART_t *) 0x0AA0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ -#define TCF0 (*(TC0_t *) 0x0B00) /* 16-bit Timer/Counter 0 */ -#define TCF2 (*(TC2_t *) 0x0B00) /* 16-bit Timer/Counter type 2 */ - - -#endif /* !defined (__ASSEMBLER__) */ - - -/* ========== Flattened fully qualified IO register names ========== */ - -/* GPIO - General Purpose IO Registers */ -#define GPIO_GPIOR0 _SFR_MEM8(0x0000) -#define GPIO_GPIOR1 _SFR_MEM8(0x0001) -#define GPIO_GPIOR2 _SFR_MEM8(0x0002) -#define GPIO_GPIOR3 _SFR_MEM8(0x0003) - -/* Deprecated */ -#define GPIO_GPIO0 _SFR_MEM8(0x0000) -#define GPIO_GPIO1 _SFR_MEM8(0x0001) -#define GPIO_GPIO2 _SFR_MEM8(0x0002) -#define GPIO_GPIO3 _SFR_MEM8(0x0003) - -/* NVM_FUSES - Fuses */ -#define FUSE_FUSEBYTE1 _SFR_MEM8(0x0001) -#define FUSE_FUSEBYTE2 _SFR_MEM8(0x0002) -#define FUSE_FUSEBYTE4 _SFR_MEM8(0x0004) -#define FUSE_FUSEBYTE5 _SFR_MEM8(0x0005) - -/* NVM_LOCKBITS - Lock Bits */ -#define LOCKBIT_LOCKBITS _SFR_MEM8(0x0000) - -/* NVM_PROD_SIGNATURES - Production Signatures */ -#define PRODSIGNATURES_RCOSC2M _SFR_MEM8(0x0000) -#define PRODSIGNATURES_RCOSC2MA _SFR_MEM8(0x0001) -#define PRODSIGNATURES_RCOSC32K _SFR_MEM8(0x0002) -#define PRODSIGNATURES_RCOSC32M _SFR_MEM8(0x0003) -#define PRODSIGNATURES_RCOSC32MA _SFR_MEM8(0x0004) -#define PRODSIGNATURES_LOTNUM0 _SFR_MEM8(0x0008) -#define PRODSIGNATURES_LOTNUM1 _SFR_MEM8(0x0009) -#define PRODSIGNATURES_LOTNUM2 _SFR_MEM8(0x000A) -#define PRODSIGNATURES_LOTNUM3 _SFR_MEM8(0x000B) -#define PRODSIGNATURES_LOTNUM4 _SFR_MEM8(0x000C) -#define PRODSIGNATURES_LOTNUM5 _SFR_MEM8(0x000D) -#define PRODSIGNATURES_WAFNUM _SFR_MEM8(0x0010) -#define PRODSIGNATURES_COORDX0 _SFR_MEM8(0x0012) -#define PRODSIGNATURES_COORDX1 _SFR_MEM8(0x0013) -#define PRODSIGNATURES_COORDY0 _SFR_MEM8(0x0014) -#define PRODSIGNATURES_COORDY1 _SFR_MEM8(0x0015) -#define PRODSIGNATURES_USBCAL0 _SFR_MEM8(0x001A) -#define PRODSIGNATURES_USBCAL1 _SFR_MEM8(0x001B) -#define PRODSIGNATURES_USBRCOSC _SFR_MEM8(0x001C) -#define PRODSIGNATURES_USBRCOSCA _SFR_MEM8(0x001D) -#define PRODSIGNATURES_ADCACAL0 _SFR_MEM8(0x0020) -#define PRODSIGNATURES_ADCACAL1 _SFR_MEM8(0x0021) -#define PRODSIGNATURES_TEMPSENSE0 _SFR_MEM8(0x002E) -#define PRODSIGNATURES_TEMPSENSE1 _SFR_MEM8(0x002F) - -/* VPORT - Virtual Port */ -#define VPORT0_DIR _SFR_MEM8(0x0010) -#define VPORT0_OUT _SFR_MEM8(0x0011) -#define VPORT0_IN _SFR_MEM8(0x0012) -#define VPORT0_INTFLAGS _SFR_MEM8(0x0013) - -/* VPORT - Virtual Port */ -#define VPORT1_DIR _SFR_MEM8(0x0014) -#define VPORT1_OUT _SFR_MEM8(0x0015) -#define VPORT1_IN _SFR_MEM8(0x0016) -#define VPORT1_INTFLAGS _SFR_MEM8(0x0017) - -/* VPORT - Virtual Port */ -#define VPORT2_DIR _SFR_MEM8(0x0018) -#define VPORT2_OUT _SFR_MEM8(0x0019) -#define VPORT2_IN _SFR_MEM8(0x001A) -#define VPORT2_INTFLAGS _SFR_MEM8(0x001B) - -/* VPORT - Virtual Port */ -#define VPORT3_DIR _SFR_MEM8(0x001C) -#define VPORT3_OUT _SFR_MEM8(0x001D) -#define VPORT3_IN _SFR_MEM8(0x001E) -#define VPORT3_INTFLAGS _SFR_MEM8(0x001F) - -/* OCD - On-Chip Debug System */ -#define OCD_OCDR0 _SFR_MEM8(0x002E) -#define OCD_OCDR1 _SFR_MEM8(0x002F) - -/* CPU - CPU registers */ -#define CPU_CCP _SFR_MEM8(0x0034) -#define CPU_RAMPD _SFR_MEM8(0x0038) -#define CPU_RAMPX _SFR_MEM8(0x0039) -#define CPU_RAMPY _SFR_MEM8(0x003A) -#define CPU_RAMPZ _SFR_MEM8(0x003B) -#define CPU_EIND _SFR_MEM8(0x003C) -#define CPU_SPL _SFR_MEM8(0x003D) -#define CPU_SPH _SFR_MEM8(0x003E) -#define CPU_SREG _SFR_MEM8(0x003F) - -/* CLK - Clock System */ -#define CLK_CTRL _SFR_MEM8(0x0040) -#define CLK_PSCTRL _SFR_MEM8(0x0041) -#define CLK_LOCK _SFR_MEM8(0x0042) -#define CLK_RTCCTRL _SFR_MEM8(0x0043) -#define CLK_USBCTRL _SFR_MEM8(0x0044) - -/* SLEEP - Sleep Controller */ -#define SLEEP_CTRL _SFR_MEM8(0x0048) - -/* OSC - Oscillator */ -#define OSC_CTRL _SFR_MEM8(0x0050) -#define OSC_STATUS _SFR_MEM8(0x0051) -#define OSC_XOSCCTRL _SFR_MEM8(0x0052) -#define OSC_XOSCFAIL _SFR_MEM8(0x0053) -#define OSC_RC32KCAL _SFR_MEM8(0x0054) -#define OSC_PLLCTRL _SFR_MEM8(0x0055) -#define OSC_DFLLCTRL _SFR_MEM8(0x0056) - -/* DFLL - DFLL */ -#define DFLLRC32M_CTRL _SFR_MEM8(0x0060) -#define DFLLRC32M_CALA _SFR_MEM8(0x0062) -#define DFLLRC32M_CALB _SFR_MEM8(0x0063) -#define DFLLRC32M_COMP0 _SFR_MEM8(0x0064) -#define DFLLRC32M_COMP1 _SFR_MEM8(0x0065) -#define DFLLRC32M_COMP2 _SFR_MEM8(0x0066) - -/* DFLL - DFLL */ -#define DFLLRC2M_CTRL _SFR_MEM8(0x0068) -#define DFLLRC2M_CALA _SFR_MEM8(0x006A) -#define DFLLRC2M_CALB _SFR_MEM8(0x006B) -#define DFLLRC2M_COMP0 _SFR_MEM8(0x006C) -#define DFLLRC2M_COMP1 _SFR_MEM8(0x006D) -#define DFLLRC2M_COMP2 _SFR_MEM8(0x006E) - -/* PR - Power Reduction */ -#define PR_PRGEN _SFR_MEM8(0x0070) -#define PR_PRPA _SFR_MEM8(0x0071) -#define PR_PRPC _SFR_MEM8(0x0073) -#define PR_PRPD _SFR_MEM8(0x0074) -#define PR_PRPE _SFR_MEM8(0x0075) -#define PR_PRPF _SFR_MEM8(0x0076) - -/* RST - Reset */ -#define RST_STATUS _SFR_MEM8(0x0078) -#define RST_CTRL _SFR_MEM8(0x0079) - -/* WDT - Watch-Dog Timer */ -#define WDT_CTRL _SFR_MEM8(0x0080) -#define WDT_WINCTRL _SFR_MEM8(0x0081) -#define WDT_STATUS _SFR_MEM8(0x0082) - -/* MCU - MCU Control */ -#define MCU_DEVID0 _SFR_MEM8(0x0090) -#define MCU_DEVID1 _SFR_MEM8(0x0091) -#define MCU_DEVID2 _SFR_MEM8(0x0092) -#define MCU_REVID _SFR_MEM8(0x0093) -#define MCU_ANAINIT _SFR_MEM8(0x0097) -#define MCU_EVSYSLOCK _SFR_MEM8(0x0098) -#define MCU_AWEXLOCK _SFR_MEM8(0x0099) - -/* PMIC - Programmable Multi-level Interrupt Controller */ -#define PMIC_STATUS _SFR_MEM8(0x00A0) -#define PMIC_INTPRI _SFR_MEM8(0x00A1) -#define PMIC_CTRL _SFR_MEM8(0x00A2) - -/* PORTCFG - I/O port Configuration */ -#define PORTCFG_MPCMASK _SFR_MEM8(0x00B0) -#define PORTCFG_VPCTRLA _SFR_MEM8(0x00B2) -#define PORTCFG_VPCTRLB _SFR_MEM8(0x00B3) -#define PORTCFG_CLKEVOUT _SFR_MEM8(0x00B4) -#define PORTCFG_EVOUTSEL _SFR_MEM8(0x00B6) - -/* CRC - Cyclic Redundancy Checker */ -#define CRC_CTRL _SFR_MEM8(0x00D0) -#define CRC_STATUS _SFR_MEM8(0x00D1) -#define CRC_DATAIN _SFR_MEM8(0x00D3) -#define CRC_CHECKSUM0 _SFR_MEM8(0x00D4) -#define CRC_CHECKSUM1 _SFR_MEM8(0x00D5) -#define CRC_CHECKSUM2 _SFR_MEM8(0x00D6) -#define CRC_CHECKSUM3 _SFR_MEM8(0x00D7) - -/* EVSYS - Event System */ -#define EVSYS_CH0MUX _SFR_MEM8(0x0180) -#define EVSYS_CH1MUX _SFR_MEM8(0x0181) -#define EVSYS_CH2MUX _SFR_MEM8(0x0182) -#define EVSYS_CH3MUX _SFR_MEM8(0x0183) -#define EVSYS_CH0CTRL _SFR_MEM8(0x0188) -#define EVSYS_CH1CTRL _SFR_MEM8(0x0189) -#define EVSYS_CH2CTRL _SFR_MEM8(0x018A) -#define EVSYS_CH3CTRL _SFR_MEM8(0x018B) -#define EVSYS_STROBE _SFR_MEM8(0x0190) -#define EVSYS_DATA _SFR_MEM8(0x0191) - -/* NVM - Non-volatile Memory Controller */ -#define NVM_ADDR0 _SFR_MEM8(0x01C0) -#define NVM_ADDR1 _SFR_MEM8(0x01C1) -#define NVM_ADDR2 _SFR_MEM8(0x01C2) -#define NVM_DATA0 _SFR_MEM8(0x01C4) -#define NVM_DATA1 _SFR_MEM8(0x01C5) -#define NVM_DATA2 _SFR_MEM8(0x01C6) -#define NVM_CMD _SFR_MEM8(0x01CA) -#define NVM_CTRLA _SFR_MEM8(0x01CB) -#define NVM_CTRLB _SFR_MEM8(0x01CC) -#define NVM_INTCTRL _SFR_MEM8(0x01CD) -#define NVM_STATUS _SFR_MEM8(0x01CF) -#define NVM_LOCKBITS _SFR_MEM8(0x01D0) - -/* ADC - Analog-to-Digital Converter */ -#define ADCA_CTRLA _SFR_MEM8(0x0200) -#define ADCA_CTRLB _SFR_MEM8(0x0201) -#define ADCA_REFCTRL _SFR_MEM8(0x0202) -#define ADCA_EVCTRL _SFR_MEM8(0x0203) -#define ADCA_PRESCALER _SFR_MEM8(0x0204) -#define ADCA_INTFLAGS _SFR_MEM8(0x0206) -#define ADCA_TEMP _SFR_MEM8(0x0207) -#define ADCA_CAL _SFR_MEM16(0x020C) -#define ADCA_CH0RES _SFR_MEM16(0x0210) -#define ADCA_CMP _SFR_MEM16(0x0218) -#define ADCA_CH0_CTRL _SFR_MEM8(0x0220) -#define ADCA_CH0_MUXCTRL _SFR_MEM8(0x0221) -#define ADCA_CH0_INTCTRL _SFR_MEM8(0x0222) -#define ADCA_CH0_INTFLAGS _SFR_MEM8(0x0223) -#define ADCA_CH0_RES _SFR_MEM16(0x0224) -#define ADCA_CH0_SCAN _SFR_MEM8(0x0226) - -/* AC - Analog Comparator */ -#define ACA_AC0CTRL _SFR_MEM8(0x0380) -#define ACA_AC1CTRL _SFR_MEM8(0x0381) -#define ACA_AC0MUXCTRL _SFR_MEM8(0x0382) -#define ACA_AC1MUXCTRL _SFR_MEM8(0x0383) -#define ACA_CTRLA _SFR_MEM8(0x0384) -#define ACA_CTRLB _SFR_MEM8(0x0385) -#define ACA_WINCTRL _SFR_MEM8(0x0386) -#define ACA_STATUS _SFR_MEM8(0x0387) - -/* RTC - Real-Time Counter */ -#define RTC_CTRL _SFR_MEM8(0x0400) -#define RTC_STATUS _SFR_MEM8(0x0401) -#define RTC_INTCTRL _SFR_MEM8(0x0402) -#define RTC_INTFLAGS _SFR_MEM8(0x0403) -#define RTC_TEMP _SFR_MEM8(0x0404) -#define RTC_CNT _SFR_MEM16(0x0408) -#define RTC_PER _SFR_MEM16(0x040A) -#define RTC_COMP _SFR_MEM16(0x040C) - -/* TWI - Two-Wire Interface */ -#define TWIC_CTRL _SFR_MEM8(0x0480) -#define TWIC_MASTER_CTRLA _SFR_MEM8(0x0481) -#define TWIC_MASTER_CTRLB _SFR_MEM8(0x0482) -#define TWIC_MASTER_CTRLC _SFR_MEM8(0x0483) -#define TWIC_MASTER_STATUS _SFR_MEM8(0x0484) -#define TWIC_MASTER_BAUD _SFR_MEM8(0x0485) -#define TWIC_MASTER_ADDR _SFR_MEM8(0x0486) -#define TWIC_MASTER_DATA _SFR_MEM8(0x0487) -#define TWIC_SLAVE_CTRLA _SFR_MEM8(0x0488) -#define TWIC_SLAVE_CTRLB _SFR_MEM8(0x0489) -#define TWIC_SLAVE_STATUS _SFR_MEM8(0x048A) -#define TWIC_SLAVE_ADDR _SFR_MEM8(0x048B) -#define TWIC_SLAVE_DATA _SFR_MEM8(0x048C) -#define TWIC_SLAVE_ADDRMASK _SFR_MEM8(0x048D) - -/* TWI - Two-Wire Interface */ -#define TWIE_CTRL _SFR_MEM8(0x04A0) -#define TWIE_MASTER_CTRLA _SFR_MEM8(0x04A1) -#define TWIE_MASTER_CTRLB _SFR_MEM8(0x04A2) -#define TWIE_MASTER_CTRLC _SFR_MEM8(0x04A3) -#define TWIE_MASTER_STATUS _SFR_MEM8(0x04A4) -#define TWIE_MASTER_BAUD _SFR_MEM8(0x04A5) -#define TWIE_MASTER_ADDR _SFR_MEM8(0x04A6) -#define TWIE_MASTER_DATA _SFR_MEM8(0x04A7) -#define TWIE_SLAVE_CTRLA _SFR_MEM8(0x04A8) -#define TWIE_SLAVE_CTRLB _SFR_MEM8(0x04A9) -#define TWIE_SLAVE_STATUS _SFR_MEM8(0x04AA) -#define TWIE_SLAVE_ADDR _SFR_MEM8(0x04AB) -#define TWIE_SLAVE_DATA _SFR_MEM8(0x04AC) -#define TWIE_SLAVE_ADDRMASK _SFR_MEM8(0x04AD) - -/* USB - Universal Serial Bus */ -#define USB_CTRLA _SFR_MEM8(0x04C0) -#define USB_CTRLB _SFR_MEM8(0x04C1) -#define USB_STATUS _SFR_MEM8(0x04C2) -#define USB_ADDR _SFR_MEM8(0x04C3) -#define USB_FIFOWP _SFR_MEM8(0x04C4) -#define USB_FIFORP _SFR_MEM8(0x04C5) -#define USB_EPPTR _SFR_MEM16(0x04C6) -#define USB_INTCTRLA _SFR_MEM8(0x04C8) -#define USB_INTCTRLB _SFR_MEM8(0x04C9) -#define USB_INTFLAGSACLR _SFR_MEM8(0x04CA) -#define USB_INTFLAGSASET _SFR_MEM8(0x04CB) -#define USB_INTFLAGSBCLR _SFR_MEM8(0x04CC) -#define USB_INTFLAGSBSET _SFR_MEM8(0x04CD) -#define USB_CAL0 _SFR_MEM8(0x04FA) -#define USB_CAL1 _SFR_MEM8(0x04FB) - -/* PORT - I/O Ports */ -#define PORTA_DIR _SFR_MEM8(0x0600) -#define PORTA_DIRSET _SFR_MEM8(0x0601) -#define PORTA_DIRCLR _SFR_MEM8(0x0602) -#define PORTA_DIRTGL _SFR_MEM8(0x0603) -#define PORTA_OUT _SFR_MEM8(0x0604) -#define PORTA_OUTSET _SFR_MEM8(0x0605) -#define PORTA_OUTCLR _SFR_MEM8(0x0606) -#define PORTA_OUTTGL _SFR_MEM8(0x0607) -#define PORTA_IN _SFR_MEM8(0x0608) -#define PORTA_INTCTRL _SFR_MEM8(0x0609) -#define PORTA_INT0MASK _SFR_MEM8(0x060A) -#define PORTA_INT1MASK _SFR_MEM8(0x060B) -#define PORTA_INTFLAGS _SFR_MEM8(0x060C) -#define PORTA_REMAP _SFR_MEM8(0x060E) -#define PORTA_PIN0CTRL _SFR_MEM8(0x0610) -#define PORTA_PIN1CTRL _SFR_MEM8(0x0611) -#define PORTA_PIN2CTRL _SFR_MEM8(0x0612) -#define PORTA_PIN3CTRL _SFR_MEM8(0x0613) -#define PORTA_PIN4CTRL _SFR_MEM8(0x0614) -#define PORTA_PIN5CTRL _SFR_MEM8(0x0615) -#define PORTA_PIN6CTRL _SFR_MEM8(0x0616) -#define PORTA_PIN7CTRL _SFR_MEM8(0x0617) - -/* PORT - I/O Ports */ -#define PORTB_DIR _SFR_MEM8(0x0620) -#define PORTB_DIRSET _SFR_MEM8(0x0621) -#define PORTB_DIRCLR _SFR_MEM8(0x0622) -#define PORTB_DIRTGL _SFR_MEM8(0x0623) -#define PORTB_OUT _SFR_MEM8(0x0624) -#define PORTB_OUTSET _SFR_MEM8(0x0625) -#define PORTB_OUTCLR _SFR_MEM8(0x0626) -#define PORTB_OUTTGL _SFR_MEM8(0x0627) -#define PORTB_IN _SFR_MEM8(0x0628) -#define PORTB_INTCTRL _SFR_MEM8(0x0629) -#define PORTB_INT0MASK _SFR_MEM8(0x062A) -#define PORTB_INT1MASK _SFR_MEM8(0x062B) -#define PORTB_INTFLAGS _SFR_MEM8(0x062C) -#define PORTB_REMAP _SFR_MEM8(0x062E) -#define PORTB_PIN0CTRL _SFR_MEM8(0x0630) -#define PORTB_PIN1CTRL _SFR_MEM8(0x0631) -#define PORTB_PIN2CTRL _SFR_MEM8(0x0632) -#define PORTB_PIN3CTRL _SFR_MEM8(0x0633) -#define PORTB_PIN4CTRL _SFR_MEM8(0x0634) -#define PORTB_PIN5CTRL _SFR_MEM8(0x0635) -#define PORTB_PIN6CTRL _SFR_MEM8(0x0636) -#define PORTB_PIN7CTRL _SFR_MEM8(0x0637) - -/* PORT - I/O Ports */ -#define PORTC_DIR _SFR_MEM8(0x0640) -#define PORTC_DIRSET _SFR_MEM8(0x0641) -#define PORTC_DIRCLR _SFR_MEM8(0x0642) -#define PORTC_DIRTGL _SFR_MEM8(0x0643) -#define PORTC_OUT _SFR_MEM8(0x0644) -#define PORTC_OUTSET _SFR_MEM8(0x0645) -#define PORTC_OUTCLR _SFR_MEM8(0x0646) -#define PORTC_OUTTGL _SFR_MEM8(0x0647) -#define PORTC_IN _SFR_MEM8(0x0648) -#define PORTC_INTCTRL _SFR_MEM8(0x0649) -#define PORTC_INT0MASK _SFR_MEM8(0x064A) -#define PORTC_INT1MASK _SFR_MEM8(0x064B) -#define PORTC_INTFLAGS _SFR_MEM8(0x064C) -#define PORTC_REMAP _SFR_MEM8(0x064E) -#define PORTC_PIN0CTRL _SFR_MEM8(0x0650) -#define PORTC_PIN1CTRL _SFR_MEM8(0x0651) -#define PORTC_PIN2CTRL _SFR_MEM8(0x0652) -#define PORTC_PIN3CTRL _SFR_MEM8(0x0653) -#define PORTC_PIN4CTRL _SFR_MEM8(0x0654) -#define PORTC_PIN5CTRL _SFR_MEM8(0x0655) -#define PORTC_PIN6CTRL _SFR_MEM8(0x0656) -#define PORTC_PIN7CTRL _SFR_MEM8(0x0657) - -/* PORT - I/O Ports */ -#define PORTD_DIR _SFR_MEM8(0x0660) -#define PORTD_DIRSET _SFR_MEM8(0x0661) -#define PORTD_DIRCLR _SFR_MEM8(0x0662) -#define PORTD_DIRTGL _SFR_MEM8(0x0663) -#define PORTD_OUT _SFR_MEM8(0x0664) -#define PORTD_OUTSET _SFR_MEM8(0x0665) -#define PORTD_OUTCLR _SFR_MEM8(0x0666) -#define PORTD_OUTTGL _SFR_MEM8(0x0667) -#define PORTD_IN _SFR_MEM8(0x0668) -#define PORTD_INTCTRL _SFR_MEM8(0x0669) -#define PORTD_INT0MASK _SFR_MEM8(0x066A) -#define PORTD_INT1MASK _SFR_MEM8(0x066B) -#define PORTD_INTFLAGS _SFR_MEM8(0x066C) -#define PORTD_REMAP _SFR_MEM8(0x066E) -#define PORTD_PIN0CTRL _SFR_MEM8(0x0670) -#define PORTD_PIN1CTRL _SFR_MEM8(0x0671) -#define PORTD_PIN2CTRL _SFR_MEM8(0x0672) -#define PORTD_PIN3CTRL _SFR_MEM8(0x0673) -#define PORTD_PIN4CTRL _SFR_MEM8(0x0674) -#define PORTD_PIN5CTRL _SFR_MEM8(0x0675) -#define PORTD_PIN6CTRL _SFR_MEM8(0x0676) -#define PORTD_PIN7CTRL _SFR_MEM8(0x0677) - -/* PORT - I/O Ports */ -#define PORTE_DIR _SFR_MEM8(0x0680) -#define PORTE_DIRSET _SFR_MEM8(0x0681) -#define PORTE_DIRCLR _SFR_MEM8(0x0682) -#define PORTE_DIRTGL _SFR_MEM8(0x0683) -#define PORTE_OUT _SFR_MEM8(0x0684) -#define PORTE_OUTSET _SFR_MEM8(0x0685) -#define PORTE_OUTCLR _SFR_MEM8(0x0686) -#define PORTE_OUTTGL _SFR_MEM8(0x0687) -#define PORTE_IN _SFR_MEM8(0x0688) -#define PORTE_INTCTRL _SFR_MEM8(0x0689) -#define PORTE_INT0MASK _SFR_MEM8(0x068A) -#define PORTE_INT1MASK _SFR_MEM8(0x068B) -#define PORTE_INTFLAGS _SFR_MEM8(0x068C) -#define PORTE_REMAP _SFR_MEM8(0x068E) -#define PORTE_PIN0CTRL _SFR_MEM8(0x0690) -#define PORTE_PIN1CTRL _SFR_MEM8(0x0691) -#define PORTE_PIN2CTRL _SFR_MEM8(0x0692) -#define PORTE_PIN3CTRL _SFR_MEM8(0x0693) -#define PORTE_PIN4CTRL _SFR_MEM8(0x0694) -#define PORTE_PIN5CTRL _SFR_MEM8(0x0695) -#define PORTE_PIN6CTRL _SFR_MEM8(0x0696) -#define PORTE_PIN7CTRL _SFR_MEM8(0x0697) - -/* PORT - I/O Ports */ -#define PORTF_DIR _SFR_MEM8(0x06A0) -#define PORTF_DIRSET _SFR_MEM8(0x06A1) -#define PORTF_DIRCLR _SFR_MEM8(0x06A2) -#define PORTF_DIRTGL _SFR_MEM8(0x06A3) -#define PORTF_OUT _SFR_MEM8(0x06A4) -#define PORTF_OUTSET _SFR_MEM8(0x06A5) -#define PORTF_OUTCLR _SFR_MEM8(0x06A6) -#define PORTF_OUTTGL _SFR_MEM8(0x06A7) -#define PORTF_IN _SFR_MEM8(0x06A8) -#define PORTF_INTCTRL _SFR_MEM8(0x06A9) -#define PORTF_INT0MASK _SFR_MEM8(0x06AA) -#define PORTF_INT1MASK _SFR_MEM8(0x06AB) -#define PORTF_INTFLAGS _SFR_MEM8(0x06AC) -#define PORTF_REMAP _SFR_MEM8(0x06AE) -#define PORTF_PIN0CTRL _SFR_MEM8(0x06B0) -#define PORTF_PIN1CTRL _SFR_MEM8(0x06B1) -#define PORTF_PIN2CTRL _SFR_MEM8(0x06B2) -#define PORTF_PIN3CTRL _SFR_MEM8(0x06B3) -#define PORTF_PIN4CTRL _SFR_MEM8(0x06B4) -#define PORTF_PIN5CTRL _SFR_MEM8(0x06B5) -#define PORTF_PIN6CTRL _SFR_MEM8(0x06B6) -#define PORTF_PIN7CTRL _SFR_MEM8(0x06B7) - -/* PORT - I/O Ports */ -#define PORTR_DIR _SFR_MEM8(0x07E0) -#define PORTR_DIRSET _SFR_MEM8(0x07E1) -#define PORTR_DIRCLR _SFR_MEM8(0x07E2) -#define PORTR_DIRTGL _SFR_MEM8(0x07E3) -#define PORTR_OUT _SFR_MEM8(0x07E4) -#define PORTR_OUTSET _SFR_MEM8(0x07E5) -#define PORTR_OUTCLR _SFR_MEM8(0x07E6) -#define PORTR_OUTTGL _SFR_MEM8(0x07E7) -#define PORTR_IN _SFR_MEM8(0x07E8) -#define PORTR_INTCTRL _SFR_MEM8(0x07E9) -#define PORTR_INT0MASK _SFR_MEM8(0x07EA) -#define PORTR_INT1MASK _SFR_MEM8(0x07EB) -#define PORTR_INTFLAGS _SFR_MEM8(0x07EC) -#define PORTR_REMAP _SFR_MEM8(0x07EE) -#define PORTR_PIN0CTRL _SFR_MEM8(0x07F0) -#define PORTR_PIN1CTRL _SFR_MEM8(0x07F1) -#define PORTR_PIN2CTRL _SFR_MEM8(0x07F2) -#define PORTR_PIN3CTRL _SFR_MEM8(0x07F3) -#define PORTR_PIN4CTRL _SFR_MEM8(0x07F4) -#define PORTR_PIN5CTRL _SFR_MEM8(0x07F5) -#define PORTR_PIN6CTRL _SFR_MEM8(0x07F6) -#define PORTR_PIN7CTRL _SFR_MEM8(0x07F7) - -/* TC0 - 16-bit Timer/Counter 0 */ -#define TCC0_CTRLA _SFR_MEM8(0x0800) -#define TCC0_CTRLB _SFR_MEM8(0x0801) -#define TCC0_CTRLC _SFR_MEM8(0x0802) -#define TCC0_CTRLD _SFR_MEM8(0x0803) -#define TCC0_CTRLE _SFR_MEM8(0x0804) -#define TCC0_INTCTRLA _SFR_MEM8(0x0806) -#define TCC0_INTCTRLB _SFR_MEM8(0x0807) -#define TCC0_CTRLFCLR _SFR_MEM8(0x0808) -#define TCC0_CTRLFSET _SFR_MEM8(0x0809) -#define TCC0_CTRLGCLR _SFR_MEM8(0x080A) -#define TCC0_CTRLGSET _SFR_MEM8(0x080B) -#define TCC0_INTFLAGS _SFR_MEM8(0x080C) -#define TCC0_TEMP _SFR_MEM8(0x080F) -#define TCC0_CNT _SFR_MEM16(0x0820) -#define TCC0_PER _SFR_MEM16(0x0826) -#define TCC0_CCA _SFR_MEM16(0x0828) -#define TCC0_CCB _SFR_MEM16(0x082A) -#define TCC0_CCC _SFR_MEM16(0x082C) -#define TCC0_CCD _SFR_MEM16(0x082E) -#define TCC0_PERBUF _SFR_MEM16(0x0836) -#define TCC0_CCABUF _SFR_MEM16(0x0838) -#define TCC0_CCBBUF _SFR_MEM16(0x083A) -#define TCC0_CCCBUF _SFR_MEM16(0x083C) -#define TCC0_CCDBUF _SFR_MEM16(0x083E) - -/* TC2 - 16-bit Timer/Counter type 2 */ -#define TCC2_CTRLA _SFR_MEM8(0x0800) -#define TCC2_CTRLB _SFR_MEM8(0x0801) -#define TCC2_CTRLC _SFR_MEM8(0x0802) -#define TCC2_CTRLE _SFR_MEM8(0x0804) -#define TCC2_INTCTRLA _SFR_MEM8(0x0806) -#define TCC2_INTCTRLB _SFR_MEM8(0x0807) -#define TCC2_CTRLF _SFR_MEM8(0x0809) -#define TCC2_INTFLAGS _SFR_MEM8(0x080C) -#define TCC2_LCNT _SFR_MEM8(0x0820) -#define TCC2_HCNT _SFR_MEM8(0x0821) -#define TCC2_LPER _SFR_MEM8(0x0826) -#define TCC2_HPER _SFR_MEM8(0x0827) -#define TCC2_LCMPA _SFR_MEM8(0x0828) -#define TCC2_HCMPA _SFR_MEM8(0x0829) -#define TCC2_LCMPB _SFR_MEM8(0x082A) -#define TCC2_HCMPB _SFR_MEM8(0x082B) -#define TCC2_LCMPC _SFR_MEM8(0x082C) -#define TCC2_HCMPC _SFR_MEM8(0x082D) -#define TCC2_LCMPD _SFR_MEM8(0x082E) -#define TCC2_HCMPD _SFR_MEM8(0x082F) - -/* TC1 - 16-bit Timer/Counter 1 */ -#define TCC1_CTRLA _SFR_MEM8(0x0840) -#define TCC1_CTRLB _SFR_MEM8(0x0841) -#define TCC1_CTRLC _SFR_MEM8(0x0842) -#define TCC1_CTRLD _SFR_MEM8(0x0843) -#define TCC1_CTRLE _SFR_MEM8(0x0844) -#define TCC1_INTCTRLA _SFR_MEM8(0x0846) -#define TCC1_INTCTRLB _SFR_MEM8(0x0847) -#define TCC1_CTRLFCLR _SFR_MEM8(0x0848) -#define TCC1_CTRLFSET _SFR_MEM8(0x0849) -#define TCC1_CTRLGCLR _SFR_MEM8(0x084A) -#define TCC1_CTRLGSET _SFR_MEM8(0x084B) -#define TCC1_INTFLAGS _SFR_MEM8(0x084C) -#define TCC1_TEMP _SFR_MEM8(0x084F) -#define TCC1_CNT _SFR_MEM16(0x0860) -#define TCC1_PER _SFR_MEM16(0x0866) -#define TCC1_CCA _SFR_MEM16(0x0868) -#define TCC1_CCB _SFR_MEM16(0x086A) -#define TCC1_PERBUF _SFR_MEM16(0x0876) -#define TCC1_CCABUF _SFR_MEM16(0x0878) -#define TCC1_CCBBUF _SFR_MEM16(0x087A) - -/* AWEX - Advanced Waveform Extension */ -#define AWEXC_CTRL _SFR_MEM8(0x0880) -#define AWEXC_FDEMASK _SFR_MEM8(0x0882) -#define AWEXC_FDCTRL _SFR_MEM8(0x0883) -#define AWEXC_STATUS _SFR_MEM8(0x0884) -#define AWEXC_STATUSSET _SFR_MEM8(0x0885) -#define AWEXC_DTBOTH _SFR_MEM8(0x0886) -#define AWEXC_DTBOTHBUF _SFR_MEM8(0x0887) -#define AWEXC_DTLS _SFR_MEM8(0x0888) -#define AWEXC_DTHS _SFR_MEM8(0x0889) -#define AWEXC_DTLSBUF _SFR_MEM8(0x088A) -#define AWEXC_DTHSBUF _SFR_MEM8(0x088B) -#define AWEXC_OUTOVEN _SFR_MEM8(0x088C) - -/* HIRES - High-Resolution Extension */ -#define HIRESC_CTRLA _SFR_MEM8(0x0890) - -/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ -#define USARTC0_DATA _SFR_MEM8(0x08A0) -#define USARTC0_STATUS _SFR_MEM8(0x08A1) -#define USARTC0_CTRLA _SFR_MEM8(0x08A3) -#define USARTC0_CTRLB _SFR_MEM8(0x08A4) -#define USARTC0_CTRLC _SFR_MEM8(0x08A5) -#define USARTC0_BAUDCTRLA _SFR_MEM8(0x08A6) -#define USARTC0_BAUDCTRLB _SFR_MEM8(0x08A7) - -/* SPI - Serial Peripheral Interface */ -#define SPIC_CTRL _SFR_MEM8(0x08C0) -#define SPIC_INTCTRL _SFR_MEM8(0x08C1) -#define SPIC_STATUS _SFR_MEM8(0x08C2) -#define SPIC_DATA _SFR_MEM8(0x08C3) - -/* IRCOM - IR Communication Module */ -#define IRCOM_CTRL _SFR_MEM8(0x08F8) -#define IRCOM_TXPLCTRL _SFR_MEM8(0x08F9) -#define IRCOM_RXPLCTRL _SFR_MEM8(0x08FA) - -/* TC0 - 16-bit Timer/Counter 0 */ -#define TCD0_CTRLA _SFR_MEM8(0x0900) -#define TCD0_CTRLB _SFR_MEM8(0x0901) -#define TCD0_CTRLC _SFR_MEM8(0x0902) -#define TCD0_CTRLD _SFR_MEM8(0x0903) -#define TCD0_CTRLE _SFR_MEM8(0x0904) -#define TCD0_INTCTRLA _SFR_MEM8(0x0906) -#define TCD0_INTCTRLB _SFR_MEM8(0x0907) -#define TCD0_CTRLFCLR _SFR_MEM8(0x0908) -#define TCD0_CTRLFSET _SFR_MEM8(0x0909) -#define TCD0_CTRLGCLR _SFR_MEM8(0x090A) -#define TCD0_CTRLGSET _SFR_MEM8(0x090B) -#define TCD0_INTFLAGS _SFR_MEM8(0x090C) -#define TCD0_TEMP _SFR_MEM8(0x090F) -#define TCD0_CNT _SFR_MEM16(0x0920) -#define TCD0_PER _SFR_MEM16(0x0926) -#define TCD0_CCA _SFR_MEM16(0x0928) -#define TCD0_CCB _SFR_MEM16(0x092A) -#define TCD0_CCC _SFR_MEM16(0x092C) -#define TCD0_CCD _SFR_MEM16(0x092E) -#define TCD0_PERBUF _SFR_MEM16(0x0936) -#define TCD0_CCABUF _SFR_MEM16(0x0938) -#define TCD0_CCBBUF _SFR_MEM16(0x093A) -#define TCD0_CCCBUF _SFR_MEM16(0x093C) -#define TCD0_CCDBUF _SFR_MEM16(0x093E) - -/* TC2 - 16-bit Timer/Counter type 2 */ -#define TCD2_CTRLA _SFR_MEM8(0x0900) -#define TCD2_CTRLB _SFR_MEM8(0x0901) -#define TCD2_CTRLC _SFR_MEM8(0x0902) -#define TCD2_CTRLE _SFR_MEM8(0x0904) -#define TCD2_INTCTRLA _SFR_MEM8(0x0906) -#define TCD2_INTCTRLB _SFR_MEM8(0x0907) -#define TCD2_CTRLF _SFR_MEM8(0x0909) -#define TCD2_INTFLAGS _SFR_MEM8(0x090C) -#define TCD2_LCNT _SFR_MEM8(0x0920) -#define TCD2_HCNT _SFR_MEM8(0x0921) -#define TCD2_LPER _SFR_MEM8(0x0926) -#define TCD2_HPER _SFR_MEM8(0x0927) -#define TCD2_LCMPA _SFR_MEM8(0x0928) -#define TCD2_HCMPA _SFR_MEM8(0x0929) -#define TCD2_LCMPB _SFR_MEM8(0x092A) -#define TCD2_HCMPB _SFR_MEM8(0x092B) -#define TCD2_LCMPC _SFR_MEM8(0x092C) -#define TCD2_HCMPC _SFR_MEM8(0x092D) -#define TCD2_LCMPD _SFR_MEM8(0x092E) -#define TCD2_HCMPD _SFR_MEM8(0x092F) - -/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ -#define USARTD0_DATA _SFR_MEM8(0x09A0) -#define USARTD0_STATUS _SFR_MEM8(0x09A1) -#define USARTD0_CTRLA _SFR_MEM8(0x09A3) -#define USARTD0_CTRLB _SFR_MEM8(0x09A4) -#define USARTD0_CTRLC _SFR_MEM8(0x09A5) -#define USARTD0_BAUDCTRLA _SFR_MEM8(0x09A6) -#define USARTD0_BAUDCTRLB _SFR_MEM8(0x09A7) - -/* SPI - Serial Peripheral Interface */ -#define SPID_CTRL _SFR_MEM8(0x09C0) -#define SPID_INTCTRL _SFR_MEM8(0x09C1) -#define SPID_STATUS _SFR_MEM8(0x09C2) -#define SPID_DATA _SFR_MEM8(0x09C3) - -/* TC0 - 16-bit Timer/Counter 0 */ -#define TCE0_CTRLA _SFR_MEM8(0x0A00) -#define TCE0_CTRLB _SFR_MEM8(0x0A01) -#define TCE0_CTRLC _SFR_MEM8(0x0A02) -#define TCE0_CTRLD _SFR_MEM8(0x0A03) -#define TCE0_CTRLE _SFR_MEM8(0x0A04) -#define TCE0_INTCTRLA _SFR_MEM8(0x0A06) -#define TCE0_INTCTRLB _SFR_MEM8(0x0A07) -#define TCE0_CTRLFCLR _SFR_MEM8(0x0A08) -#define TCE0_CTRLFSET _SFR_MEM8(0x0A09) -#define TCE0_CTRLGCLR _SFR_MEM8(0x0A0A) -#define TCE0_CTRLGSET _SFR_MEM8(0x0A0B) -#define TCE0_INTFLAGS _SFR_MEM8(0x0A0C) -#define TCE0_TEMP _SFR_MEM8(0x0A0F) -#define TCE0_CNT _SFR_MEM16(0x0A20) -#define TCE0_PER _SFR_MEM16(0x0A26) -#define TCE0_CCA _SFR_MEM16(0x0A28) -#define TCE0_CCB _SFR_MEM16(0x0A2A) -#define TCE0_CCC _SFR_MEM16(0x0A2C) -#define TCE0_CCD _SFR_MEM16(0x0A2E) -#define TCE0_PERBUF _SFR_MEM16(0x0A36) -#define TCE0_CCABUF _SFR_MEM16(0x0A38) -#define TCE0_CCBBUF _SFR_MEM16(0x0A3A) -#define TCE0_CCCBUF _SFR_MEM16(0x0A3C) -#define TCE0_CCDBUF _SFR_MEM16(0x0A3E) - -/* TC2 - 16-bit Timer/Counter type 2 */ -#define TCE2_CTRLA _SFR_MEM8(0x0A00) -#define TCE2_CTRLB _SFR_MEM8(0x0A01) -#define TCE2_CTRLC _SFR_MEM8(0x0A02) -#define TCE2_CTRLE _SFR_MEM8(0x0A04) -#define TCE2_INTCTRLA _SFR_MEM8(0x0A06) -#define TCE2_INTCTRLB _SFR_MEM8(0x0A07) -#define TCE2_CTRLF _SFR_MEM8(0x0A09) -#define TCE2_INTFLAGS _SFR_MEM8(0x0A0C) -#define TCE2_LCNT _SFR_MEM8(0x0A20) -#define TCE2_HCNT _SFR_MEM8(0x0A21) -#define TCE2_LPER _SFR_MEM8(0x0A26) -#define TCE2_HPER _SFR_MEM8(0x0A27) -#define TCE2_LCMPA _SFR_MEM8(0x0A28) -#define TCE2_HCMPA _SFR_MEM8(0x0A29) -#define TCE2_LCMPB _SFR_MEM8(0x0A2A) -#define TCE2_HCMPB _SFR_MEM8(0x0A2B) -#define TCE2_LCMPC _SFR_MEM8(0x0A2C) -#define TCE2_HCMPC _SFR_MEM8(0x0A2D) -#define TCE2_LCMPD _SFR_MEM8(0x0A2E) -#define TCE2_HCMPD _SFR_MEM8(0x0A2F) - -/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ -#define USARTE0_DATA _SFR_MEM8(0x0AA0) -#define USARTE0_STATUS _SFR_MEM8(0x0AA1) -#define USARTE0_CTRLA _SFR_MEM8(0x0AA3) -#define USARTE0_CTRLB _SFR_MEM8(0x0AA4) -#define USARTE0_CTRLC _SFR_MEM8(0x0AA5) -#define USARTE0_BAUDCTRLA _SFR_MEM8(0x0AA6) -#define USARTE0_BAUDCTRLB _SFR_MEM8(0x0AA7) - -/* TC0 - 16-bit Timer/Counter 0 */ -#define TCF0_CTRLA _SFR_MEM8(0x0B00) -#define TCF0_CTRLB _SFR_MEM8(0x0B01) -#define TCF0_CTRLC _SFR_MEM8(0x0B02) -#define TCF0_CTRLD _SFR_MEM8(0x0B03) -#define TCF0_CTRLE _SFR_MEM8(0x0B04) -#define TCF0_INTCTRLA _SFR_MEM8(0x0B06) -#define TCF0_INTCTRLB _SFR_MEM8(0x0B07) -#define TCF0_CTRLFCLR _SFR_MEM8(0x0B08) -#define TCF0_CTRLFSET _SFR_MEM8(0x0B09) -#define TCF0_CTRLGCLR _SFR_MEM8(0x0B0A) -#define TCF0_CTRLGSET _SFR_MEM8(0x0B0B) -#define TCF0_INTFLAGS _SFR_MEM8(0x0B0C) -#define TCF0_TEMP _SFR_MEM8(0x0B0F) -#define TCF0_CNT _SFR_MEM16(0x0B20) -#define TCF0_PER _SFR_MEM16(0x0B26) -#define TCF0_CCA _SFR_MEM16(0x0B28) -#define TCF0_CCB _SFR_MEM16(0x0B2A) -#define TCF0_CCC _SFR_MEM16(0x0B2C) -#define TCF0_CCD _SFR_MEM16(0x0B2E) -#define TCF0_PERBUF _SFR_MEM16(0x0B36) -#define TCF0_CCABUF _SFR_MEM16(0x0B38) -#define TCF0_CCBBUF _SFR_MEM16(0x0B3A) -#define TCF0_CCCBUF _SFR_MEM16(0x0B3C) -#define TCF0_CCDBUF _SFR_MEM16(0x0B3E) - -/* TC2 - 16-bit Timer/Counter type 2 */ -#define TCF2_CTRLA _SFR_MEM8(0x0B00) -#define TCF2_CTRLB _SFR_MEM8(0x0B01) -#define TCF2_CTRLC _SFR_MEM8(0x0B02) -#define TCF2_CTRLE _SFR_MEM8(0x0B04) -#define TCF2_INTCTRLA _SFR_MEM8(0x0B06) -#define TCF2_INTCTRLB _SFR_MEM8(0x0B07) -#define TCF2_CTRLF _SFR_MEM8(0x0B09) -#define TCF2_INTFLAGS _SFR_MEM8(0x0B0C) -#define TCF2_LCNT _SFR_MEM8(0x0B20) -#define TCF2_HCNT _SFR_MEM8(0x0B21) -#define TCF2_LPER _SFR_MEM8(0x0B26) -#define TCF2_HPER _SFR_MEM8(0x0B27) -#define TCF2_LCMPA _SFR_MEM8(0x0B28) -#define TCF2_HCMPA _SFR_MEM8(0x0B29) -#define TCF2_LCMPB _SFR_MEM8(0x0B2A) -#define TCF2_HCMPB _SFR_MEM8(0x0B2B) -#define TCF2_LCMPC _SFR_MEM8(0x0B2C) -#define TCF2_HCMPC _SFR_MEM8(0x0B2D) -#define TCF2_LCMPD _SFR_MEM8(0x0B2E) -#define TCF2_HCMPD _SFR_MEM8(0x0B2F) - - - -/*================== Bitfield Definitions ================== */ - -/* VPORT - Virtual Ports */ -/* VPORT.INTFLAGS bit masks and bit positions */ -#define VPORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ -#define VPORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ - -#define VPORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ -#define VPORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ - -/* XOCD - On-Chip Debug System */ -/* OCD.OCDR0 bit masks and bit positions */ -#define OCD_OCDRD_gm 0xFF /* OCDR Dirty group mask. */ -#define OCD_OCDRD_gp 0 /* OCDR Dirty group position. */ -#define OCD_OCDRD0_bm (1<<0) /* OCDR Dirty bit 0 mask. */ -#define OCD_OCDRD0_bp 0 /* OCDR Dirty bit 0 position. */ -#define OCD_OCDRD1_bm (1<<1) /* OCDR Dirty bit 1 mask. */ -#define OCD_OCDRD1_bp 1 /* OCDR Dirty bit 1 position. */ -#define OCD_OCDRD2_bm (1<<2) /* OCDR Dirty bit 2 mask. */ -#define OCD_OCDRD2_bp 2 /* OCDR Dirty bit 2 position. */ -#define OCD_OCDRD3_bm (1<<3) /* OCDR Dirty bit 3 mask. */ -#define OCD_OCDRD3_bp 3 /* OCDR Dirty bit 3 position. */ -#define OCD_OCDRD4_bm (1<<4) /* OCDR Dirty bit 4 mask. */ -#define OCD_OCDRD4_bp 4 /* OCDR Dirty bit 4 position. */ -#define OCD_OCDRD5_bm (1<<5) /* OCDR Dirty bit 5 mask. */ -#define OCD_OCDRD5_bp 5 /* OCDR Dirty bit 5 position. */ -#define OCD_OCDRD6_bm (1<<6) /* OCDR Dirty bit 6 mask. */ -#define OCD_OCDRD6_bp 6 /* OCDR Dirty bit 6 position. */ -#define OCD_OCDRD7_bm (1<<7) /* OCDR Dirty bit 7 mask. */ -#define OCD_OCDRD7_bp 7 /* OCDR Dirty bit 7 position. */ - -/* OCD.OCDR1 bit masks and bit positions */ -/* OCD_OCDRD Predefined. */ -/* OCD_OCDRD Predefined. */ - -/* CPU - CPU */ -/* CPU.CCP bit masks and bit positions */ -#define CPU_CCP_gm 0xFF /* CCP signature group mask. */ -#define CPU_CCP_gp 0 /* CCP signature group position. */ -#define CPU_CCP0_bm (1<<0) /* CCP signature bit 0 mask. */ -#define CPU_CCP0_bp 0 /* CCP signature bit 0 position. */ -#define CPU_CCP1_bm (1<<1) /* CCP signature bit 1 mask. */ -#define CPU_CCP1_bp 1 /* CCP signature bit 1 position. */ -#define CPU_CCP2_bm (1<<2) /* CCP signature bit 2 mask. */ -#define CPU_CCP2_bp 2 /* CCP signature bit 2 position. */ -#define CPU_CCP3_bm (1<<3) /* CCP signature bit 3 mask. */ -#define CPU_CCP3_bp 3 /* CCP signature bit 3 position. */ -#define CPU_CCP4_bm (1<<4) /* CCP signature bit 4 mask. */ -#define CPU_CCP4_bp 4 /* CCP signature bit 4 position. */ -#define CPU_CCP5_bm (1<<5) /* CCP signature bit 5 mask. */ -#define CPU_CCP5_bp 5 /* CCP signature bit 5 position. */ -#define CPU_CCP6_bm (1<<6) /* CCP signature bit 6 mask. */ -#define CPU_CCP6_bp 6 /* CCP signature bit 6 position. */ -#define CPU_CCP7_bm (1<<7) /* CCP signature bit 7 mask. */ -#define CPU_CCP7_bp 7 /* CCP signature bit 7 position. */ - -/* CPU.SREG bit masks and bit positions */ -#define CPU_I_bm 0x80 /* Global Interrupt Enable Flag bit mask. */ -#define CPU_I_bp 7 /* Global Interrupt Enable Flag bit position. */ - -#define CPU_T_bm 0x40 /* Transfer Bit bit mask. */ -#define CPU_T_bp 6 /* Transfer Bit bit position. */ - -#define CPU_H_bm 0x20 /* Half Carry Flag bit mask. */ -#define CPU_H_bp 5 /* Half Carry Flag bit position. */ - -#define CPU_S_bm 0x10 /* N Exclusive Or V Flag bit mask. */ -#define CPU_S_bp 4 /* N Exclusive Or V Flag bit position. */ - -#define CPU_V_bm 0x08 /* Two's Complement Overflow Flag bit mask. */ -#define CPU_V_bp 3 /* Two's Complement Overflow Flag bit position. */ - -#define CPU_N_bm 0x04 /* Negative Flag bit mask. */ -#define CPU_N_bp 2 /* Negative Flag bit position. */ - -#define CPU_Z_bm 0x02 /* Zero Flag bit mask. */ -#define CPU_Z_bp 1 /* Zero Flag bit position. */ - -#define CPU_C_bm 0x01 /* Carry Flag bit mask. */ -#define CPU_C_bp 0 /* Carry Flag bit position. */ - -/* CLK - Clock System */ -/* CLK.CTRL bit masks and bit positions */ -#define CLK_SCLKSEL_gm 0x07 /* System Clock Selection group mask. */ -#define CLK_SCLKSEL_gp 0 /* System Clock Selection group position. */ -#define CLK_SCLKSEL0_bm (1<<0) /* System Clock Selection bit 0 mask. */ -#define CLK_SCLKSEL0_bp 0 /* System Clock Selection bit 0 position. */ -#define CLK_SCLKSEL1_bm (1<<1) /* System Clock Selection bit 1 mask. */ -#define CLK_SCLKSEL1_bp 1 /* System Clock Selection bit 1 position. */ -#define CLK_SCLKSEL2_bm (1<<2) /* System Clock Selection bit 2 mask. */ -#define CLK_SCLKSEL2_bp 2 /* System Clock Selection bit 2 position. */ - -/* CLK.PSCTRL bit masks and bit positions */ -#define CLK_PSADIV_gm 0x7C /* Prescaler A Division Factor group mask. */ -#define CLK_PSADIV_gp 2 /* Prescaler A Division Factor group position. */ -#define CLK_PSADIV0_bm (1<<2) /* Prescaler A Division Factor bit 0 mask. */ -#define CLK_PSADIV0_bp 2 /* Prescaler A Division Factor bit 0 position. */ -#define CLK_PSADIV1_bm (1<<3) /* Prescaler A Division Factor bit 1 mask. */ -#define CLK_PSADIV1_bp 3 /* Prescaler A Division Factor bit 1 position. */ -#define CLK_PSADIV2_bm (1<<4) /* Prescaler A Division Factor bit 2 mask. */ -#define CLK_PSADIV2_bp 4 /* Prescaler A Division Factor bit 2 position. */ -#define CLK_PSADIV3_bm (1<<5) /* Prescaler A Division Factor bit 3 mask. */ -#define CLK_PSADIV3_bp 5 /* Prescaler A Division Factor bit 3 position. */ -#define CLK_PSADIV4_bm (1<<6) /* Prescaler A Division Factor bit 4 mask. */ -#define CLK_PSADIV4_bp 6 /* Prescaler A Division Factor bit 4 position. */ - -#define CLK_PSBCDIV_gm 0x03 /* Prescaler B and C Division factor group mask. */ -#define CLK_PSBCDIV_gp 0 /* Prescaler B and C Division factor group position. */ -#define CLK_PSBCDIV0_bm (1<<0) /* Prescaler B and C Division factor bit 0 mask. */ -#define CLK_PSBCDIV0_bp 0 /* Prescaler B and C Division factor bit 0 position. */ -#define CLK_PSBCDIV1_bm (1<<1) /* Prescaler B and C Division factor bit 1 mask. */ -#define CLK_PSBCDIV1_bp 1 /* Prescaler B and C Division factor bit 1 position. */ - -/* CLK.LOCK bit masks and bit positions */ -#define CLK_LOCK_bm 0x01 /* Clock System Lock bit mask. */ -#define CLK_LOCK_bp 0 /* Clock System Lock bit position. */ - -/* CLK.RTCCTRL bit masks and bit positions */ -#define CLK_RTCSRC_gm 0x0E /* Clock Source group mask. */ -#define CLK_RTCSRC_gp 1 /* Clock Source group position. */ -#define CLK_RTCSRC0_bm (1<<1) /* Clock Source bit 0 mask. */ -#define CLK_RTCSRC0_bp 1 /* Clock Source bit 0 position. */ -#define CLK_RTCSRC1_bm (1<<2) /* Clock Source bit 1 mask. */ -#define CLK_RTCSRC1_bp 2 /* Clock Source bit 1 position. */ -#define CLK_RTCSRC2_bm (1<<3) /* Clock Source bit 2 mask. */ -#define CLK_RTCSRC2_bp 3 /* Clock Source bit 2 position. */ - -#define CLK_RTCEN_bm 0x01 /* Clock Source Enable bit mask. */ -#define CLK_RTCEN_bp 0 /* Clock Source Enable bit position. */ - -/* CLK.USBCTRL bit masks and bit positions */ -#define CLK_USBPSDIV_gm 0x38 /* Prescaler Division Factor group mask. */ -#define CLK_USBPSDIV_gp 3 /* Prescaler Division Factor group position. */ -#define CLK_USBPSDIV0_bm (1<<3) /* Prescaler Division Factor bit 0 mask. */ -#define CLK_USBPSDIV0_bp 3 /* Prescaler Division Factor bit 0 position. */ -#define CLK_USBPSDIV1_bm (1<<4) /* Prescaler Division Factor bit 1 mask. */ -#define CLK_USBPSDIV1_bp 4 /* Prescaler Division Factor bit 1 position. */ -#define CLK_USBPSDIV2_bm (1<<5) /* Prescaler Division Factor bit 2 mask. */ -#define CLK_USBPSDIV2_bp 5 /* Prescaler Division Factor bit 2 position. */ - -#define CLK_USBSRC_gm 0x06 /* Clock Source group mask. */ -#define CLK_USBSRC_gp 1 /* Clock Source group position. */ -#define CLK_USBSRC0_bm (1<<1) /* Clock Source bit 0 mask. */ -#define CLK_USBSRC0_bp 1 /* Clock Source bit 0 position. */ -#define CLK_USBSRC1_bm (1<<2) /* Clock Source bit 1 mask. */ -#define CLK_USBSRC1_bp 2 /* Clock Source bit 1 position. */ - -#define CLK_USBSEN_bm 0x01 /* Clock Source Enable bit mask. */ -#define CLK_USBSEN_bp 0 /* Clock Source Enable bit position. */ - -/* PR.PRGEN bit masks and bit positions */ -#define PR_USB_bm 0x40 /* USB bit mask. */ -#define PR_USB_bp 6 /* USB bit position. */ - -#define PR_AES_bm 0x10 /* AES bit mask. */ -#define PR_AES_bp 4 /* AES bit position. */ - -#define PR_RTC_bm 0x04 /* Real-time Counter bit mask. */ -#define PR_RTC_bp 2 /* Real-time Counter bit position. */ - -#define PR_EVSYS_bm 0x02 /* Event System bit mask. */ -#define PR_EVSYS_bp 1 /* Event System bit position. */ - -#define PR_DMA_bm 0x01 /* DMA-Controller bit mask. */ -#define PR_DMA_bp 0 /* DMA-Controller bit position. */ - -/* PR.PRPA bit masks and bit positions */ -#define PR_ADC_bm 0x02 /* Port A ADC bit mask. */ -#define PR_ADC_bp 1 /* Port A ADC bit position. */ - -#define PR_AC_bm 0x01 /* Port A Analog Comparator bit mask. */ -#define PR_AC_bp 0 /* Port A Analog Comparator bit position. */ - -/* PR.PRPC bit masks and bit positions */ -#define PR_TWI_bm 0x40 /* Port C Two-wire Interface bit mask. */ -#define PR_TWI_bp 6 /* Port C Two-wire Interface bit position. */ - -#define PR_USART1_bm 0x20 /* Port C USART1 bit mask. */ -#define PR_USART1_bp 5 /* Port C USART1 bit position. */ - -#define PR_USART0_bm 0x10 /* Port C USART0 bit mask. */ -#define PR_USART0_bp 4 /* Port C USART0 bit position. */ - -#define PR_SPI_bm 0x08 /* Port C SPI bit mask. */ -#define PR_SPI_bp 3 /* Port C SPI bit position. */ - -#define PR_HIRES_bm 0x04 /* Port C AWEX bit mask. */ -#define PR_HIRES_bp 2 /* Port C AWEX bit position. */ - -#define PR_TC1_bm 0x02 /* Port C Timer/Counter1 bit mask. */ -#define PR_TC1_bp 1 /* Port C Timer/Counter1 bit position. */ - -#define PR_TC0_bm 0x01 /* Port C Timer/Counter0 bit mask. */ -#define PR_TC0_bp 0 /* Port C Timer/Counter0 bit position. */ - -/* PR.PRPD bit masks and bit positions */ -/* PR_USART0 Predefined. */ -/* PR_USART0 Predefined. */ - -/* PR_SPI Predefined. */ -/* PR_SPI Predefined. */ - -/* PR_TC0 Predefined. */ -/* PR_TC0 Predefined. */ - -/* PR.PRPE bit masks and bit positions */ -/* PR_TWI Predefined. */ -/* PR_TWI Predefined. */ - -/* PR_USART0 Predefined. */ -/* PR_USART0 Predefined. */ - -/* PR_TC0 Predefined. */ -/* PR_TC0 Predefined. */ - -/* PR.PRPF bit masks and bit positions */ -/* PR_USART0 Predefined. */ -/* PR_USART0 Predefined. */ - -/* PR_TC0 Predefined. */ -/* PR_TC0 Predefined. */ - -/* SLEEP - Sleep Controller */ -/* SLEEP.CTRL bit masks and bit positions */ -#define SLEEP_SMODE_gm 0x0E /* Sleep Mode group mask. */ -#define SLEEP_SMODE_gp 1 /* Sleep Mode group position. */ -#define SLEEP_SMODE0_bm (1<<1) /* Sleep Mode bit 0 mask. */ -#define SLEEP_SMODE0_bp 1 /* Sleep Mode bit 0 position. */ -#define SLEEP_SMODE1_bm (1<<2) /* Sleep Mode bit 1 mask. */ -#define SLEEP_SMODE1_bp 2 /* Sleep Mode bit 1 position. */ -#define SLEEP_SMODE2_bm (1<<3) /* Sleep Mode bit 2 mask. */ -#define SLEEP_SMODE2_bp 3 /* Sleep Mode bit 2 position. */ - -#define SLEEP_SEN_bm 0x01 /* Sleep Enable bit mask. */ -#define SLEEP_SEN_bp 0 /* Sleep Enable bit position. */ - -/* OSC - Oscillator */ -/* OSC.CTRL bit masks and bit positions */ -#define OSC_PLLEN_bm 0x10 /* PLL Enable bit mask. */ -#define OSC_PLLEN_bp 4 /* PLL Enable bit position. */ - -#define OSC_XOSCEN_bm 0x08 /* External Oscillator Enable bit mask. */ -#define OSC_XOSCEN_bp 3 /* External Oscillator Enable bit position. */ - -#define OSC_RC32KEN_bm 0x04 /* Internal 32.768 kHz RC Oscillator Enable bit mask. */ -#define OSC_RC32KEN_bp 2 /* Internal 32.768 kHz RC Oscillator Enable bit position. */ - -#define OSC_RC32MEN_bm 0x02 /* Internal 32 MHz RC Oscillator Enable bit mask. */ -#define OSC_RC32MEN_bp 1 /* Internal 32 MHz RC Oscillator Enable bit position. */ - -#define OSC_RC2MEN_bm 0x01 /* Internal 2 MHz RC Oscillator Enable bit mask. */ -#define OSC_RC2MEN_bp 0 /* Internal 2 MHz RC Oscillator Enable bit position. */ - -/* OSC.STATUS bit masks and bit positions */ -#define OSC_PLLRDY_bm 0x10 /* PLL Ready bit mask. */ -#define OSC_PLLRDY_bp 4 /* PLL Ready bit position. */ - -#define OSC_XOSCRDY_bm 0x08 /* External Oscillator Ready bit mask. */ -#define OSC_XOSCRDY_bp 3 /* External Oscillator Ready bit position. */ - -#define OSC_RC32KRDY_bm 0x04 /* Internal 32.768 kHz RC Oscillator Ready bit mask. */ -#define OSC_RC32KRDY_bp 2 /* Internal 32.768 kHz RC Oscillator Ready bit position. */ - -#define OSC_RC32MRDY_bm 0x02 /* Internal 32 MHz RC Oscillator Ready bit mask. */ -#define OSC_RC32MRDY_bp 1 /* Internal 32 MHz RC Oscillator Ready bit position. */ - -#define OSC_RC2MRDY_bm 0x01 /* Internal 2 MHz RC Oscillator Ready bit mask. */ -#define OSC_RC2MRDY_bp 0 /* Internal 2 MHz RC Oscillator Ready bit position. */ - -/* OSC.XOSCCTRL bit masks and bit positions */ -#define OSC_FRQRANGE_gm 0xC0 /* Frequency Range group mask. */ -#define OSC_FRQRANGE_gp 6 /* Frequency Range group position. */ -#define OSC_FRQRANGE0_bm (1<<6) /* Frequency Range bit 0 mask. */ -#define OSC_FRQRANGE0_bp 6 /* Frequency Range bit 0 position. */ -#define OSC_FRQRANGE1_bm (1<<7) /* Frequency Range bit 1 mask. */ -#define OSC_FRQRANGE1_bp 7 /* Frequency Range bit 1 position. */ - -#define OSC_X32KLPM_bm 0x20 /* 32.768 kHz XTAL OSC Low-power Mode bit mask. */ -#define OSC_X32KLPM_bp 5 /* 32.768 kHz XTAL OSC Low-power Mode bit position. */ - -#define OSC_XOSCPWR_bm 0x10 /* 16 MHz Crystal Oscillator High Power mode bit mask. */ -#define OSC_XOSCPWR_bp 4 /* 16 MHz Crystal Oscillator High Power mode bit position. */ - -#define OSC_XOSCSEL_gm 0x0F /* External Oscillator Selection and Startup Time group mask. */ -#define OSC_XOSCSEL_gp 0 /* External Oscillator Selection and Startup Time group position. */ -#define OSC_XOSCSEL0_bm (1<<0) /* External Oscillator Selection and Startup Time bit 0 mask. */ -#define OSC_XOSCSEL0_bp 0 /* External Oscillator Selection and Startup Time bit 0 position. */ -#define OSC_XOSCSEL1_bm (1<<1) /* External Oscillator Selection and Startup Time bit 1 mask. */ -#define OSC_XOSCSEL1_bp 1 /* External Oscillator Selection and Startup Time bit 1 position. */ -#define OSC_XOSCSEL2_bm (1<<2) /* External Oscillator Selection and Startup Time bit 2 mask. */ -#define OSC_XOSCSEL2_bp 2 /* External Oscillator Selection and Startup Time bit 2 position. */ -#define OSC_XOSCSEL3_bm (1<<3) /* External Oscillator Selection and Startup Time bit 3 mask. */ -#define OSC_XOSCSEL3_bp 3 /* External Oscillator Selection and Startup Time bit 3 position. */ - -/* OSC.XOSCFAIL bit masks and bit positions */ -#define OSC_PLLFDIF_bm 0x08 /* PLL Failure Detection Interrupt Flag bit mask. */ -#define OSC_PLLFDIF_bp 3 /* PLL Failure Detection Interrupt Flag bit position. */ - -#define OSC_PLLFDEN_bm 0x04 /* PLL Failure Detection Enable bit mask. */ -#define OSC_PLLFDEN_bp 2 /* PLL Failure Detection Enable bit position. */ - -#define OSC_XOSCFDIF_bm 0x02 /* XOSC Failure Detection Interrupt Flag bit mask. */ -#define OSC_XOSCFDIF_bp 1 /* XOSC Failure Detection Interrupt Flag bit position. */ - -#define OSC_XOSCFDEN_bm 0x01 /* XOSC Failure Detection Enable bit mask. */ -#define OSC_XOSCFDEN_bp 0 /* XOSC Failure Detection Enable bit position. */ - -/* OSC.PLLCTRL bit masks and bit positions */ -#define OSC_PLLSRC_gm 0xC0 /* Clock Source group mask. */ -#define OSC_PLLSRC_gp 6 /* Clock Source group position. */ -#define OSC_PLLSRC0_bm (1<<6) /* Clock Source bit 0 mask. */ -#define OSC_PLLSRC0_bp 6 /* Clock Source bit 0 position. */ -#define OSC_PLLSRC1_bm (1<<7) /* Clock Source bit 1 mask. */ -#define OSC_PLLSRC1_bp 7 /* Clock Source bit 1 position. */ - -#define OSC_PLLDIV_bm 0x20 /* Divide by 2 bit mask. */ -#define OSC_PLLDIV_bp 5 /* Divide by 2 bit position. */ - -#define OSC_PLLFAC_gm 0x1F /* Multiplication Factor group mask. */ -#define OSC_PLLFAC_gp 0 /* Multiplication Factor group position. */ -#define OSC_PLLFAC0_bm (1<<0) /* Multiplication Factor bit 0 mask. */ -#define OSC_PLLFAC0_bp 0 /* Multiplication Factor bit 0 position. */ -#define OSC_PLLFAC1_bm (1<<1) /* Multiplication Factor bit 1 mask. */ -#define OSC_PLLFAC1_bp 1 /* Multiplication Factor bit 1 position. */ -#define OSC_PLLFAC2_bm (1<<2) /* Multiplication Factor bit 2 mask. */ -#define OSC_PLLFAC2_bp 2 /* Multiplication Factor bit 2 position. */ -#define OSC_PLLFAC3_bm (1<<3) /* Multiplication Factor bit 3 mask. */ -#define OSC_PLLFAC3_bp 3 /* Multiplication Factor bit 3 position. */ -#define OSC_PLLFAC4_bm (1<<4) /* Multiplication Factor bit 4 mask. */ -#define OSC_PLLFAC4_bp 4 /* Multiplication Factor bit 4 position. */ - -/* OSC.DFLLCTRL bit masks and bit positions */ -#define OSC_RC32MCREF_gm 0x06 /* 32 MHz DFLL Calibration Reference group mask. */ -#define OSC_RC32MCREF_gp 1 /* 32 MHz DFLL Calibration Reference group position. */ -#define OSC_RC32MCREF0_bm (1<<1) /* 32 MHz DFLL Calibration Reference bit 0 mask. */ -#define OSC_RC32MCREF0_bp 1 /* 32 MHz DFLL Calibration Reference bit 0 position. */ -#define OSC_RC32MCREF1_bm (1<<2) /* 32 MHz DFLL Calibration Reference bit 1 mask. */ -#define OSC_RC32MCREF1_bp 2 /* 32 MHz DFLL Calibration Reference bit 1 position. */ - -#define OSC_RC2MCREF_bm 0x01 /* 2 MHz DFLL Calibration Reference bit mask. */ -#define OSC_RC2MCREF_bp 0 /* 2 MHz DFLL Calibration Reference bit position. */ - -/* DFLL - DFLL */ -/* DFLL.CTRL bit masks and bit positions */ -#define DFLL_ENABLE_bm 0x01 /* DFLL Enable bit mask. */ -#define DFLL_ENABLE_bp 0 /* DFLL Enable bit position. */ - -/* DFLL.CALA bit masks and bit positions */ -#define DFLL_CALL_gm 0x7F /* DFLL Calibration Value A group mask. */ -#define DFLL_CALL_gp 0 /* DFLL Calibration Value A group position. */ -#define DFLL_CALL0_bm (1<<0) /* DFLL Calibration Value A bit 0 mask. */ -#define DFLL_CALL0_bp 0 /* DFLL Calibration Value A bit 0 position. */ -#define DFLL_CALL1_bm (1<<1) /* DFLL Calibration Value A bit 1 mask. */ -#define DFLL_CALL1_bp 1 /* DFLL Calibration Value A bit 1 position. */ -#define DFLL_CALL2_bm (1<<2) /* DFLL Calibration Value A bit 2 mask. */ -#define DFLL_CALL2_bp 2 /* DFLL Calibration Value A bit 2 position. */ -#define DFLL_CALL3_bm (1<<3) /* DFLL Calibration Value A bit 3 mask. */ -#define DFLL_CALL3_bp 3 /* DFLL Calibration Value A bit 3 position. */ -#define DFLL_CALL4_bm (1<<4) /* DFLL Calibration Value A bit 4 mask. */ -#define DFLL_CALL4_bp 4 /* DFLL Calibration Value A bit 4 position. */ -#define DFLL_CALL5_bm (1<<5) /* DFLL Calibration Value A bit 5 mask. */ -#define DFLL_CALL5_bp 5 /* DFLL Calibration Value A bit 5 position. */ -#define DFLL_CALL6_bm (1<<6) /* DFLL Calibration Value A bit 6 mask. */ -#define DFLL_CALL6_bp 6 /* DFLL Calibration Value A bit 6 position. */ - -/* DFLL.CALB bit masks and bit positions */ -#define DFLL_CALH_gm 0x3F /* DFLL Calibration Value B group mask. */ -#define DFLL_CALH_gp 0 /* DFLL Calibration Value B group position. */ -#define DFLL_CALH0_bm (1<<0) /* DFLL Calibration Value B bit 0 mask. */ -#define DFLL_CALH0_bp 0 /* DFLL Calibration Value B bit 0 position. */ -#define DFLL_CALH1_bm (1<<1) /* DFLL Calibration Value B bit 1 mask. */ -#define DFLL_CALH1_bp 1 /* DFLL Calibration Value B bit 1 position. */ -#define DFLL_CALH2_bm (1<<2) /* DFLL Calibration Value B bit 2 mask. */ -#define DFLL_CALH2_bp 2 /* DFLL Calibration Value B bit 2 position. */ -#define DFLL_CALH3_bm (1<<3) /* DFLL Calibration Value B bit 3 mask. */ -#define DFLL_CALH3_bp 3 /* DFLL Calibration Value B bit 3 position. */ -#define DFLL_CALH4_bm (1<<4) /* DFLL Calibration Value B bit 4 mask. */ -#define DFLL_CALH4_bp 4 /* DFLL Calibration Value B bit 4 position. */ -#define DFLL_CALH5_bm (1<<5) /* DFLL Calibration Value B bit 5 mask. */ -#define DFLL_CALH5_bp 5 /* DFLL Calibration Value B bit 5 position. */ - -/* RST - Reset */ -/* RST.STATUS bit masks and bit positions */ -#define RST_SDRF_bm 0x40 /* Spike Detection Reset Flag bit mask. */ -#define RST_SDRF_bp 6 /* Spike Detection Reset Flag bit position. */ - -#define RST_SRF_bm 0x20 /* Software Reset Flag bit mask. */ -#define RST_SRF_bp 5 /* Software Reset Flag bit position. */ - -#define RST_PDIRF_bm 0x10 /* Programming and Debug Interface Interface Reset Flag bit mask. */ -#define RST_PDIRF_bp 4 /* Programming and Debug Interface Interface Reset Flag bit position. */ - -#define RST_WDRF_bm 0x08 /* Watchdog Reset Flag bit mask. */ -#define RST_WDRF_bp 3 /* Watchdog Reset Flag bit position. */ - -#define RST_BORF_bm 0x04 /* Brown-out Reset Flag bit mask. */ -#define RST_BORF_bp 2 /* Brown-out Reset Flag bit position. */ - -#define RST_EXTRF_bm 0x02 /* External Reset Flag bit mask. */ -#define RST_EXTRF_bp 1 /* External Reset Flag bit position. */ - -#define RST_PORF_bm 0x01 /* Power-on Reset Flag bit mask. */ -#define RST_PORF_bp 0 /* Power-on Reset Flag bit position. */ - -/* RST.CTRL bit masks and bit positions */ -#define RST_SWRST_bm 0x01 /* Software Reset bit mask. */ -#define RST_SWRST_bp 0 /* Software Reset bit position. */ - -/* WDT - Watch-Dog Timer */ -/* WDT.CTRL bit masks and bit positions */ -#define WDT_PER_gm 0x3C /* Period group mask. */ -#define WDT_PER_gp 2 /* Period group position. */ -#define WDT_PER0_bm (1<<2) /* Period bit 0 mask. */ -#define WDT_PER0_bp 2 /* Period bit 0 position. */ -#define WDT_PER1_bm (1<<3) /* Period bit 1 mask. */ -#define WDT_PER1_bp 3 /* Period bit 1 position. */ -#define WDT_PER2_bm (1<<4) /* Period bit 2 mask. */ -#define WDT_PER2_bp 4 /* Period bit 2 position. */ -#define WDT_PER3_bm (1<<5) /* Period bit 3 mask. */ -#define WDT_PER3_bp 5 /* Period bit 3 position. */ - -#define WDT_ENABLE_bm 0x02 /* Enable bit mask. */ -#define WDT_ENABLE_bp 1 /* Enable bit position. */ - -#define WDT_CEN_bm 0x01 /* Change Enable bit mask. */ -#define WDT_CEN_bp 0 /* Change Enable bit position. */ - -/* WDT.WINCTRL bit masks and bit positions */ -#define WDT_WPER_gm 0x3C /* Windowed Mode Period group mask. */ -#define WDT_WPER_gp 2 /* Windowed Mode Period group position. */ -#define WDT_WPER0_bm (1<<2) /* Windowed Mode Period bit 0 mask. */ -#define WDT_WPER0_bp 2 /* Windowed Mode Period bit 0 position. */ -#define WDT_WPER1_bm (1<<3) /* Windowed Mode Period bit 1 mask. */ -#define WDT_WPER1_bp 3 /* Windowed Mode Period bit 1 position. */ -#define WDT_WPER2_bm (1<<4) /* Windowed Mode Period bit 2 mask. */ -#define WDT_WPER2_bp 4 /* Windowed Mode Period bit 2 position. */ -#define WDT_WPER3_bm (1<<5) /* Windowed Mode Period bit 3 mask. */ -#define WDT_WPER3_bp 5 /* Windowed Mode Period bit 3 position. */ - -#define WDT_WEN_bm 0x02 /* Windowed Mode Enable bit mask. */ -#define WDT_WEN_bp 1 /* Windowed Mode Enable bit position. */ - -#define WDT_WCEN_bm 0x01 /* Windowed Mode Change Enable bit mask. */ -#define WDT_WCEN_bp 0 /* Windowed Mode Change Enable bit position. */ - -/* WDT.STATUS bit masks and bit positions */ -#define WDT_SYNCBUSY_bm 0x01 /* Syncronization busy bit mask. */ -#define WDT_SYNCBUSY_bp 0 /* Syncronization busy bit position. */ - -/* MCU - MCU Control */ -/* MCU.ANAINIT bit masks and bit positions */ -#define MCU_STARTUPDLYA_gm 0x03 /* Analog startup delay Port A group mask. */ -#define MCU_STARTUPDLYA_gp 0 /* Analog startup delay Port A group position. */ -#define MCU_STARTUPDLYA0_bm (1<<0) /* Analog startup delay Port A bit 0 mask. */ -#define MCU_STARTUPDLYA0_bp 0 /* Analog startup delay Port A bit 0 position. */ -#define MCU_STARTUPDLYA1_bm (1<<1) /* Analog startup delay Port A bit 1 mask. */ -#define MCU_STARTUPDLYA1_bp 1 /* Analog startup delay Port A bit 1 position. */ - -/* MCU.EVSYSLOCK bit masks and bit positions */ -#define MCU_EVSYS0LOCK_bm 0x01 /* Event Channel 0-3 Lock bit mask. */ -#define MCU_EVSYS0LOCK_bp 0 /* Event Channel 0-3 Lock bit position. */ - -/* MCU.AWEXLOCK bit masks and bit positions */ -#define MCU_AWEXCLOCK_bm 0x01 /* AWeX on T/C C0 Lock bit mask. */ -#define MCU_AWEXCLOCK_bp 0 /* AWeX on T/C C0 Lock bit position. */ - -/* PMIC - Programmable Multi-level Interrupt Controller */ -/* PMIC.STATUS bit masks and bit positions */ -#define PMIC_NMIEX_bm 0x80 /* Non-maskable Interrupt Executing bit mask. */ -#define PMIC_NMIEX_bp 7 /* Non-maskable Interrupt Executing bit position. */ - -#define PMIC_HILVLEX_bm 0x04 /* High Level Interrupt Executing bit mask. */ -#define PMIC_HILVLEX_bp 2 /* High Level Interrupt Executing bit position. */ - -#define PMIC_MEDLVLEX_bm 0x02 /* Medium Level Interrupt Executing bit mask. */ -#define PMIC_MEDLVLEX_bp 1 /* Medium Level Interrupt Executing bit position. */ - -#define PMIC_LOLVLEX_bm 0x01 /* Low Level Interrupt Executing bit mask. */ -#define PMIC_LOLVLEX_bp 0 /* Low Level Interrupt Executing bit position. */ - -/* PMIC.INTPRI bit masks and bit positions */ -#define PMIC_INTPRI_gm 0xFF /* Interrupt Priority group mask. */ -#define PMIC_INTPRI_gp 0 /* Interrupt Priority group position. */ -#define PMIC_INTPRI0_bm (1<<0) /* Interrupt Priority bit 0 mask. */ -#define PMIC_INTPRI0_bp 0 /* Interrupt Priority bit 0 position. */ -#define PMIC_INTPRI1_bm (1<<1) /* Interrupt Priority bit 1 mask. */ -#define PMIC_INTPRI1_bp 1 /* Interrupt Priority bit 1 position. */ -#define PMIC_INTPRI2_bm (1<<2) /* Interrupt Priority bit 2 mask. */ -#define PMIC_INTPRI2_bp 2 /* Interrupt Priority bit 2 position. */ -#define PMIC_INTPRI3_bm (1<<3) /* Interrupt Priority bit 3 mask. */ -#define PMIC_INTPRI3_bp 3 /* Interrupt Priority bit 3 position. */ -#define PMIC_INTPRI4_bm (1<<4) /* Interrupt Priority bit 4 mask. */ -#define PMIC_INTPRI4_bp 4 /* Interrupt Priority bit 4 position. */ -#define PMIC_INTPRI5_bm (1<<5) /* Interrupt Priority bit 5 mask. */ -#define PMIC_INTPRI5_bp 5 /* Interrupt Priority bit 5 position. */ -#define PMIC_INTPRI6_bm (1<<6) /* Interrupt Priority bit 6 mask. */ -#define PMIC_INTPRI6_bp 6 /* Interrupt Priority bit 6 position. */ -#define PMIC_INTPRI7_bm (1<<7) /* Interrupt Priority bit 7 mask. */ -#define PMIC_INTPRI7_bp 7 /* Interrupt Priority bit 7 position. */ - -/* PMIC.CTRL bit masks and bit positions */ -#define PMIC_RREN_bm 0x80 /* Round-Robin Priority Enable bit mask. */ -#define PMIC_RREN_bp 7 /* Round-Robin Priority Enable bit position. */ - -#define PMIC_IVSEL_bm 0x40 /* Interrupt Vector Select bit mask. */ -#define PMIC_IVSEL_bp 6 /* Interrupt Vector Select bit position. */ - -#define PMIC_HILVLEN_bm 0x04 /* High Level Enable bit mask. */ -#define PMIC_HILVLEN_bp 2 /* High Level Enable bit position. */ - -#define PMIC_MEDLVLEN_bm 0x02 /* Medium Level Enable bit mask. */ -#define PMIC_MEDLVLEN_bp 1 /* Medium Level Enable bit position. */ - -#define PMIC_LOLVLEN_bm 0x01 /* Low Level Enable bit mask. */ -#define PMIC_LOLVLEN_bp 0 /* Low Level Enable bit position. */ - -/* PORTCFG - Port Configuration */ -/* PORTCFG.VPCTRLA bit masks and bit positions */ -#define PORTCFG_VP1MAP_gm 0xF0 /* Virtual Port 1 Mapping group mask. */ -#define PORTCFG_VP1MAP_gp 4 /* Virtual Port 1 Mapping group position. */ -#define PORTCFG_VP1MAP0_bm (1<<4) /* Virtual Port 1 Mapping bit 0 mask. */ -#define PORTCFG_VP1MAP0_bp 4 /* Virtual Port 1 Mapping bit 0 position. */ -#define PORTCFG_VP1MAP1_bm (1<<5) /* Virtual Port 1 Mapping bit 1 mask. */ -#define PORTCFG_VP1MAP1_bp 5 /* Virtual Port 1 Mapping bit 1 position. */ -#define PORTCFG_VP1MAP2_bm (1<<6) /* Virtual Port 1 Mapping bit 2 mask. */ -#define PORTCFG_VP1MAP2_bp 6 /* Virtual Port 1 Mapping bit 2 position. */ -#define PORTCFG_VP1MAP3_bm (1<<7) /* Virtual Port 1 Mapping bit 3 mask. */ -#define PORTCFG_VP1MAP3_bp 7 /* Virtual Port 1 Mapping bit 3 position. */ - -#define PORTCFG_VP0MAP_gm 0x0F /* Virtual Port 0 Mapping group mask. */ -#define PORTCFG_VP0MAP_gp 0 /* Virtual Port 0 Mapping group position. */ -#define PORTCFG_VP0MAP0_bm (1<<0) /* Virtual Port 0 Mapping bit 0 mask. */ -#define PORTCFG_VP0MAP0_bp 0 /* Virtual Port 0 Mapping bit 0 position. */ -#define PORTCFG_VP0MAP1_bm (1<<1) /* Virtual Port 0 Mapping bit 1 mask. */ -#define PORTCFG_VP0MAP1_bp 1 /* Virtual Port 0 Mapping bit 1 position. */ -#define PORTCFG_VP0MAP2_bm (1<<2) /* Virtual Port 0 Mapping bit 2 mask. */ -#define PORTCFG_VP0MAP2_bp 2 /* Virtual Port 0 Mapping bit 2 position. */ -#define PORTCFG_VP0MAP3_bm (1<<3) /* Virtual Port 0 Mapping bit 3 mask. */ -#define PORTCFG_VP0MAP3_bp 3 /* Virtual Port 0 Mapping bit 3 position. */ - -/* PORTCFG.VPCTRLB bit masks and bit positions */ -#define PORTCFG_VP3MAP_gm 0xF0 /* Virtual Port 3 Mapping group mask. */ -#define PORTCFG_VP3MAP_gp 4 /* Virtual Port 3 Mapping group position. */ -#define PORTCFG_VP3MAP0_bm (1<<4) /* Virtual Port 3 Mapping bit 0 mask. */ -#define PORTCFG_VP3MAP0_bp 4 /* Virtual Port 3 Mapping bit 0 position. */ -#define PORTCFG_VP3MAP1_bm (1<<5) /* Virtual Port 3 Mapping bit 1 mask. */ -#define PORTCFG_VP3MAP1_bp 5 /* Virtual Port 3 Mapping bit 1 position. */ -#define PORTCFG_VP3MAP2_bm (1<<6) /* Virtual Port 3 Mapping bit 2 mask. */ -#define PORTCFG_VP3MAP2_bp 6 /* Virtual Port 3 Mapping bit 2 position. */ -#define PORTCFG_VP3MAP3_bm (1<<7) /* Virtual Port 3 Mapping bit 3 mask. */ -#define PORTCFG_VP3MAP3_bp 7 /* Virtual Port 3 Mapping bit 3 position. */ - -#define PORTCFG_VP2MAP_gm 0x0F /* Virtual Port 2 Mapping group mask. */ -#define PORTCFG_VP2MAP_gp 0 /* Virtual Port 2 Mapping group position. */ -#define PORTCFG_VP2MAP0_bm (1<<0) /* Virtual Port 2 Mapping bit 0 mask. */ -#define PORTCFG_VP2MAP0_bp 0 /* Virtual Port 2 Mapping bit 0 position. */ -#define PORTCFG_VP2MAP1_bm (1<<1) /* Virtual Port 2 Mapping bit 1 mask. */ -#define PORTCFG_VP2MAP1_bp 1 /* Virtual Port 2 Mapping bit 1 position. */ -#define PORTCFG_VP2MAP2_bm (1<<2) /* Virtual Port 2 Mapping bit 2 mask. */ -#define PORTCFG_VP2MAP2_bp 2 /* Virtual Port 2 Mapping bit 2 position. */ -#define PORTCFG_VP2MAP3_bm (1<<3) /* Virtual Port 2 Mapping bit 3 mask. */ -#define PORTCFG_VP2MAP3_bp 3 /* Virtual Port 2 Mapping bit 3 position. */ - -/* PORTCFG.CLKEVOUT bit masks and bit positions */ -#define PORTCFG_CLKOUT_gm 0x03 /* Peripheral Clock Output Port group mask. */ -#define PORTCFG_CLKOUT_gp 0 /* Peripheral Clock Output Port group position. */ -#define PORTCFG_CLKOUT0_bm (1<<0) /* Peripheral Clock Output Port bit 0 mask. */ -#define PORTCFG_CLKOUT0_bp 0 /* Peripheral Clock Output Port bit 0 position. */ -#define PORTCFG_CLKOUT1_bm (1<<1) /* Peripheral Clock Output Port bit 1 mask. */ -#define PORTCFG_CLKOUT1_bp 1 /* Peripheral Clock Output Port bit 1 position. */ - -#define PORTCFG_CLKOUTSEL_gm 0x0C /* Peripheral Clock Output Select group mask. */ -#define PORTCFG_CLKOUTSEL_gp 2 /* Peripheral Clock Output Select group position. */ -#define PORTCFG_CLKOUTSEL0_bm (1<<2) /* Peripheral Clock Output Select bit 0 mask. */ -#define PORTCFG_CLKOUTSEL0_bp 2 /* Peripheral Clock Output Select bit 0 position. */ -#define PORTCFG_CLKOUTSEL1_bm (1<<3) /* Peripheral Clock Output Select bit 1 mask. */ -#define PORTCFG_CLKOUTSEL1_bp 3 /* Peripheral Clock Output Select bit 1 position. */ - -#define PORTCFG_EVOUT_gm 0x30 /* Event Output Port group mask. */ -#define PORTCFG_EVOUT_gp 4 /* Event Output Port group position. */ -#define PORTCFG_EVOUT0_bm (1<<4) /* Event Output Port bit 0 mask. */ -#define PORTCFG_EVOUT0_bp 4 /* Event Output Port bit 0 position. */ -#define PORTCFG_EVOUT1_bm (1<<5) /* Event Output Port bit 1 mask. */ -#define PORTCFG_EVOUT1_bp 5 /* Event Output Port bit 1 position. */ - -#define PORTCFG_RTCOUT_bm 0x40 /* RTC Clock Output bit mask. */ -#define PORTCFG_RTCOUT_bp 6 /* RTC Clock Output bit position. */ - -#define PORTCFG_CLKEVPIN_bm 0x80 /* Peripheral Clock and Event Output pin Select bit mask. */ -#define PORTCFG_CLKEVPIN_bp 7 /* Peripheral Clock and Event Output pin Select bit position. */ - -/* PORTCFG.EVOUTSEL bit masks and bit positions */ -#define PORTCFG_EVOUTSEL_gm 0x07 /* Event Output Select group mask. */ -#define PORTCFG_EVOUTSEL_gp 0 /* Event Output Select group position. */ -#define PORTCFG_EVOUTSEL0_bm (1<<0) /* Event Output Select bit 0 mask. */ -#define PORTCFG_EVOUTSEL0_bp 0 /* Event Output Select bit 0 position. */ -#define PORTCFG_EVOUTSEL1_bm (1<<1) /* Event Output Select bit 1 mask. */ -#define PORTCFG_EVOUTSEL1_bp 1 /* Event Output Select bit 1 position. */ -#define PORTCFG_EVOUTSEL2_bm (1<<2) /* Event Output Select bit 2 mask. */ -#define PORTCFG_EVOUTSEL2_bp 2 /* Event Output Select bit 2 position. */ - -/* CRC - Cyclic Redundancy Checker */ -/* CRC.CTRL bit masks and bit positions */ -#define CRC_RESET_gm 0xC0 /* Reset group mask. */ -#define CRC_RESET_gp 6 /* Reset group position. */ -#define CRC_RESET0_bm (1<<6) /* Reset bit 0 mask. */ -#define CRC_RESET0_bp 6 /* Reset bit 0 position. */ -#define CRC_RESET1_bm (1<<7) /* Reset bit 1 mask. */ -#define CRC_RESET1_bp 7 /* Reset bit 1 position. */ - -#define CRC_CRC32_bm 0x20 /* CRC Mode bit mask. */ -#define CRC_CRC32_bp 5 /* CRC Mode bit position. */ - -#define CRC_SOURCE_gm 0x0F /* Input Source group mask. */ -#define CRC_SOURCE_gp 0 /* Input Source group position. */ -#define CRC_SOURCE0_bm (1<<0) /* Input Source bit 0 mask. */ -#define CRC_SOURCE0_bp 0 /* Input Source bit 0 position. */ -#define CRC_SOURCE1_bm (1<<1) /* Input Source bit 1 mask. */ -#define CRC_SOURCE1_bp 1 /* Input Source bit 1 position. */ -#define CRC_SOURCE2_bm (1<<2) /* Input Source bit 2 mask. */ -#define CRC_SOURCE2_bp 2 /* Input Source bit 2 position. */ -#define CRC_SOURCE3_bm (1<<3) /* Input Source bit 3 mask. */ -#define CRC_SOURCE3_bp 3 /* Input Source bit 3 position. */ - -/* CRC.STATUS bit masks and bit positions */ -#define CRC_ZERO_bm 0x02 /* Zero detection bit mask. */ -#define CRC_ZERO_bp 1 /* Zero detection bit position. */ - -#define CRC_BUSY_bm 0x01 /* Busy bit mask. */ -#define CRC_BUSY_bp 0 /* Busy bit position. */ - -/* EVSYS - Event System */ -/* EVSYS.CH0MUX bit masks and bit positions */ -#define EVSYS_CHMUX_gm 0xFF /* Event Channel 0 Multiplexer group mask. */ -#define EVSYS_CHMUX_gp 0 /* Event Channel 0 Multiplexer group position. */ -#define EVSYS_CHMUX0_bm (1<<0) /* Event Channel 0 Multiplexer bit 0 mask. */ -#define EVSYS_CHMUX0_bp 0 /* Event Channel 0 Multiplexer bit 0 position. */ -#define EVSYS_CHMUX1_bm (1<<1) /* Event Channel 0 Multiplexer bit 1 mask. */ -#define EVSYS_CHMUX1_bp 1 /* Event Channel 0 Multiplexer bit 1 position. */ -#define EVSYS_CHMUX2_bm (1<<2) /* Event Channel 0 Multiplexer bit 2 mask. */ -#define EVSYS_CHMUX2_bp 2 /* Event Channel 0 Multiplexer bit 2 position. */ -#define EVSYS_CHMUX3_bm (1<<3) /* Event Channel 0 Multiplexer bit 3 mask. */ -#define EVSYS_CHMUX3_bp 3 /* Event Channel 0 Multiplexer bit 3 position. */ -#define EVSYS_CHMUX4_bm (1<<4) /* Event Channel 0 Multiplexer bit 4 mask. */ -#define EVSYS_CHMUX4_bp 4 /* Event Channel 0 Multiplexer bit 4 position. */ -#define EVSYS_CHMUX5_bm (1<<5) /* Event Channel 0 Multiplexer bit 5 mask. */ -#define EVSYS_CHMUX5_bp 5 /* Event Channel 0 Multiplexer bit 5 position. */ -#define EVSYS_CHMUX6_bm (1<<6) /* Event Channel 0 Multiplexer bit 6 mask. */ -#define EVSYS_CHMUX6_bp 6 /* Event Channel 0 Multiplexer bit 6 position. */ -#define EVSYS_CHMUX7_bm (1<<7) /* Event Channel 0 Multiplexer bit 7 mask. */ -#define EVSYS_CHMUX7_bp 7 /* Event Channel 0 Multiplexer bit 7 position. */ - -/* EVSYS.CH1MUX bit masks and bit positions */ -/* EVSYS_CHMUX Predefined. */ -/* EVSYS_CHMUX Predefined. */ - -/* EVSYS.CH2MUX bit masks and bit positions */ -/* EVSYS_CHMUX Predefined. */ -/* EVSYS_CHMUX Predefined. */ - -/* EVSYS.CH3MUX bit masks and bit positions */ -/* EVSYS_CHMUX Predefined. */ -/* EVSYS_CHMUX Predefined. */ - -/* EVSYS.CH0CTRL bit masks and bit positions */ -#define EVSYS_QDIRM_gm 0x60 /* Quadrature Decoder Index Recognition Mode group mask. */ -#define EVSYS_QDIRM_gp 5 /* Quadrature Decoder Index Recognition Mode group position. */ -#define EVSYS_QDIRM0_bm (1<<5) /* Quadrature Decoder Index Recognition Mode bit 0 mask. */ -#define EVSYS_QDIRM0_bp 5 /* Quadrature Decoder Index Recognition Mode bit 0 position. */ -#define EVSYS_QDIRM1_bm (1<<6) /* Quadrature Decoder Index Recognition Mode bit 1 mask. */ -#define EVSYS_QDIRM1_bp 6 /* Quadrature Decoder Index Recognition Mode bit 1 position. */ - -#define EVSYS_QDIEN_bm 0x10 /* Quadrature Decoder Index Enable bit mask. */ -#define EVSYS_QDIEN_bp 4 /* Quadrature Decoder Index Enable bit position. */ - -#define EVSYS_QDEN_bm 0x08 /* Quadrature Decoder Enable bit mask. */ -#define EVSYS_QDEN_bp 3 /* Quadrature Decoder Enable bit position. */ - -#define EVSYS_DIGFILT_gm 0x07 /* Digital Filter group mask. */ -#define EVSYS_DIGFILT_gp 0 /* Digital Filter group position. */ -#define EVSYS_DIGFILT0_bm (1<<0) /* Digital Filter bit 0 mask. */ -#define EVSYS_DIGFILT0_bp 0 /* Digital Filter bit 0 position. */ -#define EVSYS_DIGFILT1_bm (1<<1) /* Digital Filter bit 1 mask. */ -#define EVSYS_DIGFILT1_bp 1 /* Digital Filter bit 1 position. */ -#define EVSYS_DIGFILT2_bm (1<<2) /* Digital Filter bit 2 mask. */ -#define EVSYS_DIGFILT2_bp 2 /* Digital Filter bit 2 position. */ - -/* EVSYS.CH1CTRL bit masks and bit positions */ -/* EVSYS_DIGFILT Predefined. */ -/* EVSYS_DIGFILT Predefined. */ - -/* EVSYS.CH2CTRL bit masks and bit positions */ -/* EVSYS_DIGFILT Predefined. */ -/* EVSYS_DIGFILT Predefined. */ - -/* EVSYS.CH3CTRL bit masks and bit positions */ -/* EVSYS_DIGFILT Predefined. */ -/* EVSYS_DIGFILT Predefined. */ - -/* NVM - Non Volatile Memory Controller */ -/* NVM.CMD bit masks and bit positions */ -#define NVM_CMD_gm 0x7F /* Command group mask. */ -#define NVM_CMD_gp 0 /* Command group position. */ -#define NVM_CMD0_bm (1<<0) /* Command bit 0 mask. */ -#define NVM_CMD0_bp 0 /* Command bit 0 position. */ -#define NVM_CMD1_bm (1<<1) /* Command bit 1 mask. */ -#define NVM_CMD1_bp 1 /* Command bit 1 position. */ -#define NVM_CMD2_bm (1<<2) /* Command bit 2 mask. */ -#define NVM_CMD2_bp 2 /* Command bit 2 position. */ -#define NVM_CMD3_bm (1<<3) /* Command bit 3 mask. */ -#define NVM_CMD3_bp 3 /* Command bit 3 position. */ -#define NVM_CMD4_bm (1<<4) /* Command bit 4 mask. */ -#define NVM_CMD4_bp 4 /* Command bit 4 position. */ -#define NVM_CMD5_bm (1<<5) /* Command bit 5 mask. */ -#define NVM_CMD5_bp 5 /* Command bit 5 position. */ -#define NVM_CMD6_bm (1<<6) /* Command bit 6 mask. */ -#define NVM_CMD6_bp 6 /* Command bit 6 position. */ - -/* NVM.CTRLA bit masks and bit positions */ -#define NVM_CMDEX_bm 0x01 /* Command Execute bit mask. */ -#define NVM_CMDEX_bp 0 /* Command Execute bit position. */ - -/* NVM.CTRLB bit masks and bit positions */ -#define NVM_EEMAPEN_bm 0x08 /* EEPROM Mapping Enable bit mask. */ -#define NVM_EEMAPEN_bp 3 /* EEPROM Mapping Enable bit position. */ - -#define NVM_FPRM_bm 0x04 /* Flash Power Reduction Enable bit mask. */ -#define NVM_FPRM_bp 2 /* Flash Power Reduction Enable bit position. */ - -#define NVM_EPRM_bm 0x02 /* EEPROM Power Reduction Enable bit mask. */ -#define NVM_EPRM_bp 1 /* EEPROM Power Reduction Enable bit position. */ - -#define NVM_SPMLOCK_bm 0x01 /* SPM Lock bit mask. */ -#define NVM_SPMLOCK_bp 0 /* SPM Lock bit position. */ - -/* NVM.INTCTRL bit masks and bit positions */ -#define NVM_SPMLVL_gm 0x0C /* SPM Interrupt Level group mask. */ -#define NVM_SPMLVL_gp 2 /* SPM Interrupt Level group position. */ -#define NVM_SPMLVL0_bm (1<<2) /* SPM Interrupt Level bit 0 mask. */ -#define NVM_SPMLVL0_bp 2 /* SPM Interrupt Level bit 0 position. */ -#define NVM_SPMLVL1_bm (1<<3) /* SPM Interrupt Level bit 1 mask. */ -#define NVM_SPMLVL1_bp 3 /* SPM Interrupt Level bit 1 position. */ - -#define NVM_EELVL_gm 0x03 /* EEPROM Interrupt Level group mask. */ -#define NVM_EELVL_gp 0 /* EEPROM Interrupt Level group position. */ -#define NVM_EELVL0_bm (1<<0) /* EEPROM Interrupt Level bit 0 mask. */ -#define NVM_EELVL0_bp 0 /* EEPROM Interrupt Level bit 0 position. */ -#define NVM_EELVL1_bm (1<<1) /* EEPROM Interrupt Level bit 1 mask. */ -#define NVM_EELVL1_bp 1 /* EEPROM Interrupt Level bit 1 position. */ - -/* NVM.STATUS bit masks and bit positions */ -#define NVM_NVMBUSY_bm 0x80 /* Non-volatile Memory Busy bit mask. */ -#define NVM_NVMBUSY_bp 7 /* Non-volatile Memory Busy bit position. */ - -#define NVM_FBUSY_bm 0x40 /* Flash Memory Busy bit mask. */ -#define NVM_FBUSY_bp 6 /* Flash Memory Busy bit position. */ - -#define NVM_EELOAD_bm 0x02 /* EEPROM Page Buffer Active Loading bit mask. */ -#define NVM_EELOAD_bp 1 /* EEPROM Page Buffer Active Loading bit position. */ - -#define NVM_FLOAD_bm 0x01 /* Flash Page Buffer Active Loading bit mask. */ -#define NVM_FLOAD_bp 0 /* Flash Page Buffer Active Loading bit position. */ - -/* NVM.LOCKBITS bit masks and bit positions */ -#define NVM_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ -#define NVM_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ -#define NVM_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ -#define NVM_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ -#define NVM_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ -#define NVM_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ - -#define NVM_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ -#define NVM_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ -#define NVM_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ -#define NVM_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ -#define NVM_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ -#define NVM_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ - -#define NVM_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ -#define NVM_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ -#define NVM_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ -#define NVM_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ -#define NVM_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ -#define NVM_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ - -#define NVM_LB_gm 0x03 /* Lock Bits group mask. */ -#define NVM_LB_gp 0 /* Lock Bits group position. */ -#define NVM_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ -#define NVM_LB0_bp 0 /* Lock Bits bit 0 position. */ -#define NVM_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ -#define NVM_LB1_bp 1 /* Lock Bits bit 1 position. */ - -/* ADC - Analog/Digital Converter */ -/* ADC_CH.CTRL bit masks and bit positions */ -#define ADC_CH_START_bm 0x80 /* Channel Start Conversion bit mask. */ -#define ADC_CH_START_bp 7 /* Channel Start Conversion bit position. */ - -#define ADC_CH_GAIN_gm 0x1C /* Gain Factor group mask. */ -#define ADC_CH_GAIN_gp 2 /* Gain Factor group position. */ -#define ADC_CH_GAIN0_bm (1<<2) /* Gain Factor bit 0 mask. */ -#define ADC_CH_GAIN0_bp 2 /* Gain Factor bit 0 position. */ -#define ADC_CH_GAIN1_bm (1<<3) /* Gain Factor bit 1 mask. */ -#define ADC_CH_GAIN1_bp 3 /* Gain Factor bit 1 position. */ -#define ADC_CH_GAIN2_bm (1<<4) /* Gain Factor bit 2 mask. */ -#define ADC_CH_GAIN2_bp 4 /* Gain Factor bit 2 position. */ - -#define ADC_CH_INPUTMODE_gm 0x03 /* Input Mode Select group mask. */ -#define ADC_CH_INPUTMODE_gp 0 /* Input Mode Select group position. */ -#define ADC_CH_INPUTMODE0_bm (1<<0) /* Input Mode Select bit 0 mask. */ -#define ADC_CH_INPUTMODE0_bp 0 /* Input Mode Select bit 0 position. */ -#define ADC_CH_INPUTMODE1_bm (1<<1) /* Input Mode Select bit 1 mask. */ -#define ADC_CH_INPUTMODE1_bp 1 /* Input Mode Select bit 1 position. */ - -/* ADC_CH.MUXCTRL bit masks and bit positions */ -#define ADC_CH_MUXPOS_gm 0x78 /* MUX selection on Positive ADC input group mask. */ -#define ADC_CH_MUXPOS_gp 3 /* MUX selection on Positive ADC input group position. */ -#define ADC_CH_MUXPOS0_bm (1<<3) /* MUX selection on Positive ADC input bit 0 mask. */ -#define ADC_CH_MUXPOS0_bp 3 /* MUX selection on Positive ADC input bit 0 position. */ -#define ADC_CH_MUXPOS1_bm (1<<4) /* MUX selection on Positive ADC input bit 1 mask. */ -#define ADC_CH_MUXPOS1_bp 4 /* MUX selection on Positive ADC input bit 1 position. */ -#define ADC_CH_MUXPOS2_bm (1<<5) /* MUX selection on Positive ADC input bit 2 mask. */ -#define ADC_CH_MUXPOS2_bp 5 /* MUX selection on Positive ADC input bit 2 position. */ -#define ADC_CH_MUXPOS3_bm (1<<6) /* MUX selection on Positive ADC input bit 3 mask. */ -#define ADC_CH_MUXPOS3_bp 6 /* MUX selection on Positive ADC input bit 3 position. */ - -#define ADC_CH_MUXINT_gm 0x78 /* MUX selection on Internal ADC input group mask. */ -#define ADC_CH_MUXINT_gp 3 /* MUX selection on Internal ADC input group position. */ -#define ADC_CH_MUXINT0_bm (1<<3) /* MUX selection on Internal ADC input bit 0 mask. */ -#define ADC_CH_MUXINT0_bp 3 /* MUX selection on Internal ADC input bit 0 position. */ -#define ADC_CH_MUXINT1_bm (1<<4) /* MUX selection on Internal ADC input bit 1 mask. */ -#define ADC_CH_MUXINT1_bp 4 /* MUX selection on Internal ADC input bit 1 position. */ -#define ADC_CH_MUXINT2_bm (1<<5) /* MUX selection on Internal ADC input bit 2 mask. */ -#define ADC_CH_MUXINT2_bp 5 /* MUX selection on Internal ADC input bit 2 position. */ -#define ADC_CH_MUXINT3_bm (1<<6) /* MUX selection on Internal ADC input bit 3 mask. */ -#define ADC_CH_MUXINT3_bp 6 /* MUX selection on Internal ADC input bit 3 position. */ - -#define ADC_CH_MUXNEG_gm 0x03 /* MUX selection on Negative ADC input group mask. */ -#define ADC_CH_MUXNEG_gp 0 /* MUX selection on Negative ADC input group position. */ -#define ADC_CH_MUXNEG0_bm (1<<0) /* MUX selection on Negative ADC input bit 0 mask. */ -#define ADC_CH_MUXNEG0_bp 0 /* MUX selection on Negative ADC input bit 0 position. */ -#define ADC_CH_MUXNEG1_bm (1<<1) /* MUX selection on Negative ADC input bit 1 mask. */ -#define ADC_CH_MUXNEG1_bp 1 /* MUX selection on Negative ADC input bit 1 position. */ - -/* ADC_CH.INTCTRL bit masks and bit positions */ -#define ADC_CH_INTMODE_gm 0x0C /* Interrupt Mode group mask. */ -#define ADC_CH_INTMODE_gp 2 /* Interrupt Mode group position. */ -#define ADC_CH_INTMODE0_bm (1<<2) /* Interrupt Mode bit 0 mask. */ -#define ADC_CH_INTMODE0_bp 2 /* Interrupt Mode bit 0 position. */ -#define ADC_CH_INTMODE1_bm (1<<3) /* Interrupt Mode bit 1 mask. */ -#define ADC_CH_INTMODE1_bp 3 /* Interrupt Mode bit 1 position. */ - -#define ADC_CH_INTLVL_gm 0x03 /* Interrupt Level group mask. */ -#define ADC_CH_INTLVL_gp 0 /* Interrupt Level group position. */ -#define ADC_CH_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */ -#define ADC_CH_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */ -#define ADC_CH_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ -#define ADC_CH_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */ - -/* ADC_CH.INTFLAGS bit masks and bit positions */ -#define ADC_CH_CHIF_bm 0x01 /* Channel Interrupt Flag bit mask. */ -#define ADC_CH_CHIF_bp 0 /* Channel Interrupt Flag bit position. */ - -/* ADC_CH.SCAN bit masks and bit positions */ -#define ADC_CH_OFFSET_gm 0xF0 /* Positive MUX setting offset group mask. */ -#define ADC_CH_OFFSET_gp 4 /* Positive MUX setting offset group position. */ -#define ADC_CH_OFFSET0_bm (1<<4) /* Positive MUX setting offset bit 0 mask. */ -#define ADC_CH_OFFSET0_bp 4 /* Positive MUX setting offset bit 0 position. */ -#define ADC_CH_OFFSET1_bm (1<<5) /* Positive MUX setting offset bit 1 mask. */ -#define ADC_CH_OFFSET1_bp 5 /* Positive MUX setting offset bit 1 position. */ -#define ADC_CH_OFFSET2_bm (1<<6) /* Positive MUX setting offset bit 2 mask. */ -#define ADC_CH_OFFSET2_bp 6 /* Positive MUX setting offset bit 2 position. */ -#define ADC_CH_OFFSET3_bm (1<<7) /* Positive MUX setting offset bit 3 mask. */ -#define ADC_CH_OFFSET3_bp 7 /* Positive MUX setting offset bit 3 position. */ - -#define ADC_CH_SCANNUM_gm 0x0F /* Number of Channels included in scan group mask. */ -#define ADC_CH_SCANNUM_gp 0 /* Number of Channels included in scan group position. */ -#define ADC_CH_SCANNUM0_bm (1<<0) /* Number of Channels included in scan bit 0 mask. */ -#define ADC_CH_SCANNUM0_bp 0 /* Number of Channels included in scan bit 0 position. */ -#define ADC_CH_SCANNUM1_bm (1<<1) /* Number of Channels included in scan bit 1 mask. */ -#define ADC_CH_SCANNUM1_bp 1 /* Number of Channels included in scan bit 1 position. */ -#define ADC_CH_SCANNUM2_bm (1<<2) /* Number of Channels included in scan bit 2 mask. */ -#define ADC_CH_SCANNUM2_bp 2 /* Number of Channels included in scan bit 2 position. */ -#define ADC_CH_SCANNUM3_bm (1<<3) /* Number of Channels included in scan bit 3 mask. */ -#define ADC_CH_SCANNUM3_bp 3 /* Number of Channels included in scan bit 3 position. */ - -/* ADC.CTRLA bit masks and bit positions */ -#define ADC_CH0START_bm 0x04 /* Channel 0 Start Conversion bit mask. */ -#define ADC_CH0START_bp 2 /* Channel 0 Start Conversion bit position. */ - -#define ADC_FLUSH_bm 0x02 /* ADC Flush bit mask. */ -#define ADC_FLUSH_bp 1 /* ADC Flush bit position. */ - -#define ADC_ENABLE_bm 0x01 /* Enable ADC bit mask. */ -#define ADC_ENABLE_bp 0 /* Enable ADC bit position. */ - -/* ADC.CTRLB bit masks and bit positions */ -#define ADC_CURRLIMIT_gm 0x60 /* Current Limitation group mask. */ -#define ADC_CURRLIMIT_gp 5 /* Current Limitation group position. */ -#define ADC_CURRLIMIT0_bm (1<<5) /* Current Limitation bit 0 mask. */ -#define ADC_CURRLIMIT0_bp 5 /* Current Limitation bit 0 position. */ -#define ADC_CURRLIMIT1_bm (1<<6) /* Current Limitation bit 1 mask. */ -#define ADC_CURRLIMIT1_bp 6 /* Current Limitation bit 1 position. */ - -#define ADC_CONMODE_bm 0x10 /* Conversion Mode bit mask. */ -#define ADC_CONMODE_bp 4 /* Conversion Mode bit position. */ - -#define ADC_FREERUN_bm 0x08 /* Free Running Mode Enable bit mask. */ -#define ADC_FREERUN_bp 3 /* Free Running Mode Enable bit position. */ - -#define ADC_RESOLUTION_gm 0x06 /* Result Resolution group mask. */ -#define ADC_RESOLUTION_gp 1 /* Result Resolution group position. */ -#define ADC_RESOLUTION0_bm (1<<1) /* Result Resolution bit 0 mask. */ -#define ADC_RESOLUTION0_bp 1 /* Result Resolution bit 0 position. */ -#define ADC_RESOLUTION1_bm (1<<2) /* Result Resolution bit 1 mask. */ -#define ADC_RESOLUTION1_bp 2 /* Result Resolution bit 1 position. */ - -/* ADC.REFCTRL bit masks and bit positions */ -#define ADC_REFSEL_gm 0x70 /* Reference Selection group mask. */ -#define ADC_REFSEL_gp 4 /* Reference Selection group position. */ -#define ADC_REFSEL0_bm (1<<4) /* Reference Selection bit 0 mask. */ -#define ADC_REFSEL0_bp 4 /* Reference Selection bit 0 position. */ -#define ADC_REFSEL1_bm (1<<5) /* Reference Selection bit 1 mask. */ -#define ADC_REFSEL1_bp 5 /* Reference Selection bit 1 position. */ -#define ADC_REFSEL2_bm (1<<6) /* Reference Selection bit 2 mask. */ -#define ADC_REFSEL2_bp 6 /* Reference Selection bit 2 position. */ - -#define ADC_BANDGAP_bm 0x02 /* Bandgap enable bit mask. */ -#define ADC_BANDGAP_bp 1 /* Bandgap enable bit position. */ - -#define ADC_TEMPREF_bm 0x01 /* Temperature Reference Enable bit mask. */ -#define ADC_TEMPREF_bp 0 /* Temperature Reference Enable bit position. */ - -/* ADC.EVCTRL bit masks and bit positions */ -#define ADC_EVSEL_gm 0x18 /* Event Input Select group mask. */ -#define ADC_EVSEL_gp 3 /* Event Input Select group position. */ -#define ADC_EVSEL0_bm (1<<3) /* Event Input Select bit 0 mask. */ -#define ADC_EVSEL0_bp 3 /* Event Input Select bit 0 position. */ -#define ADC_EVSEL1_bm (1<<4) /* Event Input Select bit 1 mask. */ -#define ADC_EVSEL1_bp 4 /* Event Input Select bit 1 position. */ - -#define ADC_EVACT_gm 0x07 /* Event Action Select group mask. */ -#define ADC_EVACT_gp 0 /* Event Action Select group position. */ -#define ADC_EVACT0_bm (1<<0) /* Event Action Select bit 0 mask. */ -#define ADC_EVACT0_bp 0 /* Event Action Select bit 0 position. */ -#define ADC_EVACT1_bm (1<<1) /* Event Action Select bit 1 mask. */ -#define ADC_EVACT1_bp 1 /* Event Action Select bit 1 position. */ -#define ADC_EVACT2_bm (1<<2) /* Event Action Select bit 2 mask. */ -#define ADC_EVACT2_bp 2 /* Event Action Select bit 2 position. */ - -/* ADC.PRESCALER bit masks and bit positions */ -#define ADC_PRESCALER_gm 0x07 /* Clock Prescaler Selection group mask. */ -#define ADC_PRESCALER_gp 0 /* Clock Prescaler Selection group position. */ -#define ADC_PRESCALER0_bm (1<<0) /* Clock Prescaler Selection bit 0 mask. */ -#define ADC_PRESCALER0_bp 0 /* Clock Prescaler Selection bit 0 position. */ -#define ADC_PRESCALER1_bm (1<<1) /* Clock Prescaler Selection bit 1 mask. */ -#define ADC_PRESCALER1_bp 1 /* Clock Prescaler Selection bit 1 position. */ -#define ADC_PRESCALER2_bm (1<<2) /* Clock Prescaler Selection bit 2 mask. */ -#define ADC_PRESCALER2_bp 2 /* Clock Prescaler Selection bit 2 position. */ - -/* ADC.INTFLAGS bit masks and bit positions */ -#define ADC_CH0IF_bm 0x01 /* Channel 0 Interrupt Flag bit mask. */ -#define ADC_CH0IF_bp 0 /* Channel 0 Interrupt Flag bit position. */ - -/* AC - Analog Comparator */ -/* AC.AC0CTRL bit masks and bit positions */ -#define AC_INTMODE_gm 0xC0 /* Interrupt Mode group mask. */ -#define AC_INTMODE_gp 6 /* Interrupt Mode group position. */ -#define AC_INTMODE0_bm (1<<6) /* Interrupt Mode bit 0 mask. */ -#define AC_INTMODE0_bp 6 /* Interrupt Mode bit 0 position. */ -#define AC_INTMODE1_bm (1<<7) /* Interrupt Mode bit 1 mask. */ -#define AC_INTMODE1_bp 7 /* Interrupt Mode bit 1 position. */ - -#define AC_INTLVL_gm 0x30 /* Interrupt Level group mask. */ -#define AC_INTLVL_gp 4 /* Interrupt Level group position. */ -#define AC_INTLVL0_bm (1<<4) /* Interrupt Level bit 0 mask. */ -#define AC_INTLVL0_bp 4 /* Interrupt Level bit 0 position. */ -#define AC_INTLVL1_bm (1<<5) /* Interrupt Level bit 1 mask. */ -#define AC_INTLVL1_bp 5 /* Interrupt Level bit 1 position. */ - -#define AC_HYSMODE_gm 0x06 /* Hysteresis Mode group mask. */ -#define AC_HYSMODE_gp 1 /* Hysteresis Mode group position. */ -#define AC_HYSMODE0_bm (1<<1) /* Hysteresis Mode bit 0 mask. */ -#define AC_HYSMODE0_bp 1 /* Hysteresis Mode bit 0 position. */ -#define AC_HYSMODE1_bm (1<<2) /* Hysteresis Mode bit 1 mask. */ -#define AC_HYSMODE1_bp 2 /* Hysteresis Mode bit 1 position. */ - -#define AC_ENABLE_bm 0x01 /* Enable bit mask. */ -#define AC_ENABLE_bp 0 /* Enable bit position. */ - -/* AC.AC1CTRL bit masks and bit positions */ -/* AC_INTMODE Predefined. */ -/* AC_INTMODE Predefined. */ - -/* AC_INTLVL Predefined. */ -/* AC_INTLVL Predefined. */ - -/* AC_HYSMODE Predefined. */ -/* AC_HYSMODE Predefined. */ - -/* AC_ENABLE Predefined. */ -/* AC_ENABLE Predefined. */ - -/* AC.AC0MUXCTRL bit masks and bit positions */ -#define AC_MUXPOS_gm 0x38 /* MUX Positive Input group mask. */ -#define AC_MUXPOS_gp 3 /* MUX Positive Input group position. */ -#define AC_MUXPOS0_bm (1<<3) /* MUX Positive Input bit 0 mask. */ -#define AC_MUXPOS0_bp 3 /* MUX Positive Input bit 0 position. */ -#define AC_MUXPOS1_bm (1<<4) /* MUX Positive Input bit 1 mask. */ -#define AC_MUXPOS1_bp 4 /* MUX Positive Input bit 1 position. */ -#define AC_MUXPOS2_bm (1<<5) /* MUX Positive Input bit 2 mask. */ -#define AC_MUXPOS2_bp 5 /* MUX Positive Input bit 2 position. */ - -#define AC_MUXNEG_gm 0x07 /* MUX Negative Input group mask. */ -#define AC_MUXNEG_gp 0 /* MUX Negative Input group position. */ -#define AC_MUXNEG0_bm (1<<0) /* MUX Negative Input bit 0 mask. */ -#define AC_MUXNEG0_bp 0 /* MUX Negative Input bit 0 position. */ -#define AC_MUXNEG1_bm (1<<1) /* MUX Negative Input bit 1 mask. */ -#define AC_MUXNEG1_bp 1 /* MUX Negative Input bit 1 position. */ -#define AC_MUXNEG2_bm (1<<2) /* MUX Negative Input bit 2 mask. */ -#define AC_MUXNEG2_bp 2 /* MUX Negative Input bit 2 position. */ - -/* AC.AC1MUXCTRL bit masks and bit positions */ -/* AC_MUXPOS Predefined. */ -/* AC_MUXPOS Predefined. */ - -/* AC_MUXNEG Predefined. */ -/* AC_MUXNEG Predefined. */ - -/* AC.CTRLA bit masks and bit positions */ -#define AC_AC1OUT_bm 0x02 /* Analog Comparator 1 Output Enable bit mask. */ -#define AC_AC1OUT_bp 1 /* Analog Comparator 1 Output Enable bit position. */ - -#define AC_AC0OUT_bm 0x01 /* Analog Comparator 0 Output Enable bit mask. */ -#define AC_AC0OUT_bp 0 /* Analog Comparator 0 Output Enable bit position. */ - -/* AC.CTRLB bit masks and bit positions */ -#define AC_SCALEFAC_gm 0x3F /* VCC Voltage Scaler Factor group mask. */ -#define AC_SCALEFAC_gp 0 /* VCC Voltage Scaler Factor group position. */ -#define AC_SCALEFAC0_bm (1<<0) /* VCC Voltage Scaler Factor bit 0 mask. */ -#define AC_SCALEFAC0_bp 0 /* VCC Voltage Scaler Factor bit 0 position. */ -#define AC_SCALEFAC1_bm (1<<1) /* VCC Voltage Scaler Factor bit 1 mask. */ -#define AC_SCALEFAC1_bp 1 /* VCC Voltage Scaler Factor bit 1 position. */ -#define AC_SCALEFAC2_bm (1<<2) /* VCC Voltage Scaler Factor bit 2 mask. */ -#define AC_SCALEFAC2_bp 2 /* VCC Voltage Scaler Factor bit 2 position. */ -#define AC_SCALEFAC3_bm (1<<3) /* VCC Voltage Scaler Factor bit 3 mask. */ -#define AC_SCALEFAC3_bp 3 /* VCC Voltage Scaler Factor bit 3 position. */ -#define AC_SCALEFAC4_bm (1<<4) /* VCC Voltage Scaler Factor bit 4 mask. */ -#define AC_SCALEFAC4_bp 4 /* VCC Voltage Scaler Factor bit 4 position. */ -#define AC_SCALEFAC5_bm (1<<5) /* VCC Voltage Scaler Factor bit 5 mask. */ -#define AC_SCALEFAC5_bp 5 /* VCC Voltage Scaler Factor bit 5 position. */ - -/* AC.WINCTRL bit masks and bit positions */ -#define AC_WEN_bm 0x10 /* Window Mode Enable bit mask. */ -#define AC_WEN_bp 4 /* Window Mode Enable bit position. */ - -#define AC_WINTMODE_gm 0x0C /* Window Interrupt Mode group mask. */ -#define AC_WINTMODE_gp 2 /* Window Interrupt Mode group position. */ -#define AC_WINTMODE0_bm (1<<2) /* Window Interrupt Mode bit 0 mask. */ -#define AC_WINTMODE0_bp 2 /* Window Interrupt Mode bit 0 position. */ -#define AC_WINTMODE1_bm (1<<3) /* Window Interrupt Mode bit 1 mask. */ -#define AC_WINTMODE1_bp 3 /* Window Interrupt Mode bit 1 position. */ - -#define AC_WINTLVL_gm 0x03 /* Window Interrupt Level group mask. */ -#define AC_WINTLVL_gp 0 /* Window Interrupt Level group position. */ -#define AC_WINTLVL0_bm (1<<0) /* Window Interrupt Level bit 0 mask. */ -#define AC_WINTLVL0_bp 0 /* Window Interrupt Level bit 0 position. */ -#define AC_WINTLVL1_bm (1<<1) /* Window Interrupt Level bit 1 mask. */ -#define AC_WINTLVL1_bp 1 /* Window Interrupt Level bit 1 position. */ - -/* AC.STATUS bit masks and bit positions */ -#define AC_WSTATE_gm 0xC0 /* Window Mode State group mask. */ -#define AC_WSTATE_gp 6 /* Window Mode State group position. */ -#define AC_WSTATE0_bm (1<<6) /* Window Mode State bit 0 mask. */ -#define AC_WSTATE0_bp 6 /* Window Mode State bit 0 position. */ -#define AC_WSTATE1_bm (1<<7) /* Window Mode State bit 1 mask. */ -#define AC_WSTATE1_bp 7 /* Window Mode State bit 1 position. */ - -#define AC_AC1STATE_bm 0x20 /* Analog Comparator 1 State bit mask. */ -#define AC_AC1STATE_bp 5 /* Analog Comparator 1 State bit position. */ - -#define AC_AC0STATE_bm 0x10 /* Analog Comparator 0 State bit mask. */ -#define AC_AC0STATE_bp 4 /* Analog Comparator 0 State bit position. */ - -#define AC_WIF_bm 0x04 /* Window Mode Interrupt Flag bit mask. */ -#define AC_WIF_bp 2 /* Window Mode Interrupt Flag bit position. */ - -#define AC_AC1IF_bm 0x02 /* Analog Comparator 1 Interrupt Flag bit mask. */ -#define AC_AC1IF_bp 1 /* Analog Comparator 1 Interrupt Flag bit position. */ - -#define AC_AC0IF_bm 0x01 /* Analog Comparator 0 Interrupt Flag bit mask. */ -#define AC_AC0IF_bp 0 /* Analog Comparator 0 Interrupt Flag bit position. */ - -/* RTC - Real-Time Counter */ -/* RTC.CTRL bit masks and bit positions */ -#define RTC_PRESCALER_gm 0x07 /* Prescaling Factor group mask. */ -#define RTC_PRESCALER_gp 0 /* Prescaling Factor group position. */ -#define RTC_PRESCALER0_bm (1<<0) /* Prescaling Factor bit 0 mask. */ -#define RTC_PRESCALER0_bp 0 /* Prescaling Factor bit 0 position. */ -#define RTC_PRESCALER1_bm (1<<1) /* Prescaling Factor bit 1 mask. */ -#define RTC_PRESCALER1_bp 1 /* Prescaling Factor bit 1 position. */ -#define RTC_PRESCALER2_bm (1<<2) /* Prescaling Factor bit 2 mask. */ -#define RTC_PRESCALER2_bp 2 /* Prescaling Factor bit 2 position. */ - -/* RTC.STATUS bit masks and bit positions */ -#define RTC_SYNCBUSY_bm 0x01 /* Synchronization Busy Flag bit mask. */ -#define RTC_SYNCBUSY_bp 0 /* Synchronization Busy Flag bit position. */ - -/* RTC.INTCTRL bit masks and bit positions */ -#define RTC_COMPINTLVL_gm 0x0C /* Compare Match Interrupt Level group mask. */ -#define RTC_COMPINTLVL_gp 2 /* Compare Match Interrupt Level group position. */ -#define RTC_COMPINTLVL0_bm (1<<2) /* Compare Match Interrupt Level bit 0 mask. */ -#define RTC_COMPINTLVL0_bp 2 /* Compare Match Interrupt Level bit 0 position. */ -#define RTC_COMPINTLVL1_bm (1<<3) /* Compare Match Interrupt Level bit 1 mask. */ -#define RTC_COMPINTLVL1_bp 3 /* Compare Match Interrupt Level bit 1 position. */ - -#define RTC_OVFINTLVL_gm 0x03 /* Overflow Interrupt Level group mask. */ -#define RTC_OVFINTLVL_gp 0 /* Overflow Interrupt Level group position. */ -#define RTC_OVFINTLVL0_bm (1<<0) /* Overflow Interrupt Level bit 0 mask. */ -#define RTC_OVFINTLVL0_bp 0 /* Overflow Interrupt Level bit 0 position. */ -#define RTC_OVFINTLVL1_bm (1<<1) /* Overflow Interrupt Level bit 1 mask. */ -#define RTC_OVFINTLVL1_bp 1 /* Overflow Interrupt Level bit 1 position. */ - -/* RTC.INTFLAGS bit masks and bit positions */ -#define RTC_COMPIF_bm 0x02 /* Compare Match Interrupt Flag bit mask. */ -#define RTC_COMPIF_bp 1 /* Compare Match Interrupt Flag bit position. */ - -#define RTC_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ -#define RTC_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ - -/* TWI - Two-Wire Interface */ -/* TWI_MASTER.CTRLA bit masks and bit positions */ -#define TWI_MASTER_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ -#define TWI_MASTER_INTLVL_gp 6 /* Interrupt Level group position. */ -#define TWI_MASTER_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ -#define TWI_MASTER_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ -#define TWI_MASTER_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ -#define TWI_MASTER_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ - -#define TWI_MASTER_RIEN_bm 0x20 /* Read Interrupt Enable bit mask. */ -#define TWI_MASTER_RIEN_bp 5 /* Read Interrupt Enable bit position. */ - -#define TWI_MASTER_WIEN_bm 0x10 /* Write Interrupt Enable bit mask. */ -#define TWI_MASTER_WIEN_bp 4 /* Write Interrupt Enable bit position. */ - -#define TWI_MASTER_ENABLE_bm 0x08 /* Enable TWI Master bit mask. */ -#define TWI_MASTER_ENABLE_bp 3 /* Enable TWI Master bit position. */ - -/* TWI_MASTER.CTRLB bit masks and bit positions */ -#define TWI_MASTER_TIMEOUT_gm 0x0C /* Inactive Bus Timeout group mask. */ -#define TWI_MASTER_TIMEOUT_gp 2 /* Inactive Bus Timeout group position. */ -#define TWI_MASTER_TIMEOUT0_bm (1<<2) /* Inactive Bus Timeout bit 0 mask. */ -#define TWI_MASTER_TIMEOUT0_bp 2 /* Inactive Bus Timeout bit 0 position. */ -#define TWI_MASTER_TIMEOUT1_bm (1<<3) /* Inactive Bus Timeout bit 1 mask. */ -#define TWI_MASTER_TIMEOUT1_bp 3 /* Inactive Bus Timeout bit 1 position. */ - -#define TWI_MASTER_QCEN_bm 0x02 /* Quick Command Enable bit mask. */ -#define TWI_MASTER_QCEN_bp 1 /* Quick Command Enable bit position. */ - -#define TWI_MASTER_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ -#define TWI_MASTER_SMEN_bp 0 /* Smart Mode Enable bit position. */ - -/* TWI_MASTER.CTRLC bit masks and bit positions */ -#define TWI_MASTER_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ -#define TWI_MASTER_ACKACT_bp 2 /* Acknowledge Action bit position. */ - -#define TWI_MASTER_CMD_gm 0x03 /* Command group mask. */ -#define TWI_MASTER_CMD_gp 0 /* Command group position. */ -#define TWI_MASTER_CMD0_bm (1<<0) /* Command bit 0 mask. */ -#define TWI_MASTER_CMD0_bp 0 /* Command bit 0 position. */ -#define TWI_MASTER_CMD1_bm (1<<1) /* Command bit 1 mask. */ -#define TWI_MASTER_CMD1_bp 1 /* Command bit 1 position. */ - -/* TWI_MASTER.STATUS bit masks and bit positions */ -#define TWI_MASTER_RIF_bm 0x80 /* Read Interrupt Flag bit mask. */ -#define TWI_MASTER_RIF_bp 7 /* Read Interrupt Flag bit position. */ - -#define TWI_MASTER_WIF_bm 0x40 /* Write Interrupt Flag bit mask. */ -#define TWI_MASTER_WIF_bp 6 /* Write Interrupt Flag bit position. */ - -#define TWI_MASTER_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ -#define TWI_MASTER_CLKHOLD_bp 5 /* Clock Hold bit position. */ - -#define TWI_MASTER_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ -#define TWI_MASTER_RXACK_bp 4 /* Received Acknowledge bit position. */ - -#define TWI_MASTER_ARBLOST_bm 0x08 /* Arbitration Lost bit mask. */ -#define TWI_MASTER_ARBLOST_bp 3 /* Arbitration Lost bit position. */ - -#define TWI_MASTER_BUSERR_bm 0x04 /* Bus Error bit mask. */ -#define TWI_MASTER_BUSERR_bp 2 /* Bus Error bit position. */ - -#define TWI_MASTER_BUSSTATE_gm 0x03 /* Bus State group mask. */ -#define TWI_MASTER_BUSSTATE_gp 0 /* Bus State group position. */ -#define TWI_MASTER_BUSSTATE0_bm (1<<0) /* Bus State bit 0 mask. */ -#define TWI_MASTER_BUSSTATE0_bp 0 /* Bus State bit 0 position. */ -#define TWI_MASTER_BUSSTATE1_bm (1<<1) /* Bus State bit 1 mask. */ -#define TWI_MASTER_BUSSTATE1_bp 1 /* Bus State bit 1 position. */ - -/* TWI_SLAVE.CTRLA bit masks and bit positions */ -#define TWI_SLAVE_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ -#define TWI_SLAVE_INTLVL_gp 6 /* Interrupt Level group position. */ -#define TWI_SLAVE_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ -#define TWI_SLAVE_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ -#define TWI_SLAVE_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ -#define TWI_SLAVE_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ - -#define TWI_SLAVE_DIEN_bm 0x20 /* Data Interrupt Enable bit mask. */ -#define TWI_SLAVE_DIEN_bp 5 /* Data Interrupt Enable bit position. */ - -#define TWI_SLAVE_APIEN_bm 0x10 /* Address/Stop Interrupt Enable bit mask. */ -#define TWI_SLAVE_APIEN_bp 4 /* Address/Stop Interrupt Enable bit position. */ - -#define TWI_SLAVE_ENABLE_bm 0x08 /* Enable TWI Slave bit mask. */ -#define TWI_SLAVE_ENABLE_bp 3 /* Enable TWI Slave bit position. */ - -#define TWI_SLAVE_PIEN_bm 0x04 /* Stop Interrupt Enable bit mask. */ -#define TWI_SLAVE_PIEN_bp 2 /* Stop Interrupt Enable bit position. */ - -#define TWI_SLAVE_PMEN_bm 0x02 /* Promiscuous Mode Enable bit mask. */ -#define TWI_SLAVE_PMEN_bp 1 /* Promiscuous Mode Enable bit position. */ - -#define TWI_SLAVE_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ -#define TWI_SLAVE_SMEN_bp 0 /* Smart Mode Enable bit position. */ - -/* TWI_SLAVE.CTRLB bit masks and bit positions */ -#define TWI_SLAVE_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ -#define TWI_SLAVE_ACKACT_bp 2 /* Acknowledge Action bit position. */ - -#define TWI_SLAVE_CMD_gm 0x03 /* Command group mask. */ -#define TWI_SLAVE_CMD_gp 0 /* Command group position. */ -#define TWI_SLAVE_CMD0_bm (1<<0) /* Command bit 0 mask. */ -#define TWI_SLAVE_CMD0_bp 0 /* Command bit 0 position. */ -#define TWI_SLAVE_CMD1_bm (1<<1) /* Command bit 1 mask. */ -#define TWI_SLAVE_CMD1_bp 1 /* Command bit 1 position. */ - -/* TWI_SLAVE.STATUS bit masks and bit positions */ -#define TWI_SLAVE_DIF_bm 0x80 /* Data Interrupt Flag bit mask. */ -#define TWI_SLAVE_DIF_bp 7 /* Data Interrupt Flag bit position. */ - -#define TWI_SLAVE_APIF_bm 0x40 /* Address/Stop Interrupt Flag bit mask. */ -#define TWI_SLAVE_APIF_bp 6 /* Address/Stop Interrupt Flag bit position. */ - -#define TWI_SLAVE_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ -#define TWI_SLAVE_CLKHOLD_bp 5 /* Clock Hold bit position. */ - -#define TWI_SLAVE_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ -#define TWI_SLAVE_RXACK_bp 4 /* Received Acknowledge bit position. */ - -#define TWI_SLAVE_COLL_bm 0x08 /* Collision bit mask. */ -#define TWI_SLAVE_COLL_bp 3 /* Collision bit position. */ - -#define TWI_SLAVE_BUSERR_bm 0x04 /* Bus Error bit mask. */ -#define TWI_SLAVE_BUSERR_bp 2 /* Bus Error bit position. */ - -#define TWI_SLAVE_DIR_bm 0x02 /* Read/Write Direction bit mask. */ -#define TWI_SLAVE_DIR_bp 1 /* Read/Write Direction bit position. */ - -#define TWI_SLAVE_AP_bm 0x01 /* Slave Address or Stop bit mask. */ -#define TWI_SLAVE_AP_bp 0 /* Slave Address or Stop bit position. */ - -/* TWI_SLAVE.ADDRMASK bit masks and bit positions */ -#define TWI_SLAVE_ADDRMASK_gm 0xFE /* Address Mask group mask. */ -#define TWI_SLAVE_ADDRMASK_gp 1 /* Address Mask group position. */ -#define TWI_SLAVE_ADDRMASK0_bm (1<<1) /* Address Mask bit 0 mask. */ -#define TWI_SLAVE_ADDRMASK0_bp 1 /* Address Mask bit 0 position. */ -#define TWI_SLAVE_ADDRMASK1_bm (1<<2) /* Address Mask bit 1 mask. */ -#define TWI_SLAVE_ADDRMASK1_bp 2 /* Address Mask bit 1 position. */ -#define TWI_SLAVE_ADDRMASK2_bm (1<<3) /* Address Mask bit 2 mask. */ -#define TWI_SLAVE_ADDRMASK2_bp 3 /* Address Mask bit 2 position. */ -#define TWI_SLAVE_ADDRMASK3_bm (1<<4) /* Address Mask bit 3 mask. */ -#define TWI_SLAVE_ADDRMASK3_bp 4 /* Address Mask bit 3 position. */ -#define TWI_SLAVE_ADDRMASK4_bm (1<<5) /* Address Mask bit 4 mask. */ -#define TWI_SLAVE_ADDRMASK4_bp 5 /* Address Mask bit 4 position. */ -#define TWI_SLAVE_ADDRMASK5_bm (1<<6) /* Address Mask bit 5 mask. */ -#define TWI_SLAVE_ADDRMASK5_bp 6 /* Address Mask bit 5 position. */ -#define TWI_SLAVE_ADDRMASK6_bm (1<<7) /* Address Mask bit 6 mask. */ -#define TWI_SLAVE_ADDRMASK6_bp 7 /* Address Mask bit 6 position. */ - -#define TWI_SLAVE_ADDREN_bm 0x01 /* Address Enable bit mask. */ -#define TWI_SLAVE_ADDREN_bp 0 /* Address Enable bit position. */ - -/* TWI.CTRL bit masks and bit positions */ -#define TWI_SDAHOLD_gm 0x06 /* SDA Hold Time Enable group mask. */ -#define TWI_SDAHOLD_gp 1 /* SDA Hold Time Enable group position. */ -#define TWI_SDAHOLD0_bm (1<<1) /* SDA Hold Time Enable bit 0 mask. */ -#define TWI_SDAHOLD0_bp 1 /* SDA Hold Time Enable bit 0 position. */ -#define TWI_SDAHOLD1_bm (1<<2) /* SDA Hold Time Enable bit 1 mask. */ -#define TWI_SDAHOLD1_bp 2 /* SDA Hold Time Enable bit 1 position. */ - -#define TWI_EDIEN_bm 0x01 /* External Driver Interface Enable bit mask. */ -#define TWI_EDIEN_bp 0 /* External Driver Interface Enable bit position. */ - -/* USB - USB */ -/* USB_EP.STATUS bit masks and bit positions */ -#define USB_EP_STALLF_bm 0x80 /* Endpoint Stall Flag bit mask. */ -#define USB_EP_STALLF_bp 7 /* Endpoint Stall Flag bit position. */ - -#define USB_EP_CRC_bm 0x80 /* CRC Error Flag bit mask. */ -#define USB_EP_CRC_bp 7 /* CRC Error Flag bit position. */ - -#define USB_EP_UNF_bm 0x40 /* Underflow Enpoint FLag bit mask. */ -#define USB_EP_UNF_bp 6 /* Underflow Enpoint FLag bit position. */ - -#define USB_EP_OVF_bm 0x40 /* Overflow Enpoint Flag for Output Endpoints bit mask. */ -#define USB_EP_OVF_bp 6 /* Overflow Enpoint Flag for Output Endpoints bit position. */ - -#define USB_EP_TRNCOMPL0_bm 0x20 /* Transaction Complete 0 Flag bit mask. */ -#define USB_EP_TRNCOMPL0_bp 5 /* Transaction Complete 0 Flag bit position. */ - -#define USB_EP_TRNCOMPL1_bm 0x10 /* Transaction Complete 1 Flag bit mask. */ -#define USB_EP_TRNCOMPL1_bp 4 /* Transaction Complete 1 Flag bit position. */ - -#define USB_EP_SETUP_bm 0x10 /* SETUP Transaction Complete Flag bit mask. */ -#define USB_EP_SETUP_bp 4 /* SETUP Transaction Complete Flag bit position. */ - -#define USB_EP_BANK_bm 0x08 /* Bank Select bit mask. */ -#define USB_EP_BANK_bp 3 /* Bank Select bit position. */ - -#define USB_EP_BUSNACK1_bm 0x04 /* Data Buffer 1 Not Acknowledge bit mask. */ -#define USB_EP_BUSNACK1_bp 2 /* Data Buffer 1 Not Acknowledge bit position. */ - -#define USB_EP_BUSNACK0_bm 0x02 /* Data Buffer 0 Not Acknowledge bit mask. */ -#define USB_EP_BUSNACK0_bp 1 /* Data Buffer 0 Not Acknowledge bit position. */ - -#define USB_EP_TOGGLE_bm 0x01 /* Data Toggle bit mask. */ -#define USB_EP_TOGGLE_bp 0 /* Data Toggle bit position. */ - -/* USB_EP.CTRL bit masks and bit positions */ -#define USB_EP_TYPE_gm 0xC0 /* Endpoint Type group mask. */ -#define USB_EP_TYPE_gp 6 /* Endpoint Type group position. */ -#define USB_EP_TYPE0_bm (1<<6) /* Endpoint Type bit 0 mask. */ -#define USB_EP_TYPE0_bp 6 /* Endpoint Type bit 0 position. */ -#define USB_EP_TYPE1_bm (1<<7) /* Endpoint Type bit 1 mask. */ -#define USB_EP_TYPE1_bp 7 /* Endpoint Type bit 1 position. */ - -#define USB_EP_MULTIPKT_bm 0x20 /* Multi Packet Transfer Enable bit mask. */ -#define USB_EP_MULTIPKT_bp 5 /* Multi Packet Transfer Enable bit position. */ - -#define USB_EP_PINGPONG_bm 0x10 /* Ping-Pong Enable bit mask. */ -#define USB_EP_PINGPONG_bp 4 /* Ping-Pong Enable bit position. */ - -#define USB_EP_INTDSBL_bm 0x08 /* Interrupt Disable bit mask. */ -#define USB_EP_INTDSBL_bp 3 /* Interrupt Disable bit position. */ - -#define USB_EP_STALL_bm 0x04 /* Data Stall bit mask. */ -#define USB_EP_STALL_bp 2 /* Data Stall bit position. */ - -#define USB_EP_BUFSIZE_gm 0x07 /* Data Buffer Size group mask. */ -#define USB_EP_BUFSIZE_gp 0 /* Data Buffer Size group position. */ -#define USB_EP_BUFSIZE0_bm (1<<0) /* Data Buffer Size bit 0 mask. */ -#define USB_EP_BUFSIZE0_bp 0 /* Data Buffer Size bit 0 position. */ -#define USB_EP_BUFSIZE1_bm (1<<1) /* Data Buffer Size bit 1 mask. */ -#define USB_EP_BUFSIZE1_bp 1 /* Data Buffer Size bit 1 position. */ -#define USB_EP_BUFSIZE2_bm (1<<2) /* Data Buffer Size bit 2 mask. */ -#define USB_EP_BUFSIZE2_bp 2 /* Data Buffer Size bit 2 position. */ - -/* USB_EP.CNT bit masks and bit positions */ -#define USB_EP_ZLP_bm 0x8000 /* Zero Length Packet bit mask. */ -#define USB_EP_ZLP_bp 15 /* Zero Length Packet bit position. */ - -/* USB.CTRLA bit masks and bit positions */ -#define USB_ENABLE_bm 0x80 /* USB Enable bit mask. */ -#define USB_ENABLE_bp 7 /* USB Enable bit position. */ - -#define USB_SPEED_bm 0x40 /* Speed Select bit mask. */ -#define USB_SPEED_bp 6 /* Speed Select bit position. */ - -#define USB_FIFOEN_bm 0x20 /* USB FIFO Enable bit mask. */ -#define USB_FIFOEN_bp 5 /* USB FIFO Enable bit position. */ - -#define USB_STFRNUM_bm 0x10 /* Store Frame Number Enable bit mask. */ -#define USB_STFRNUM_bp 4 /* Store Frame Number Enable bit position. */ - -#define USB_MAXEP_gm 0x0F /* Maximum Endpoint Addresses group mask. */ -#define USB_MAXEP_gp 0 /* Maximum Endpoint Addresses group position. */ -#define USB_MAXEP0_bm (1<<0) /* Maximum Endpoint Addresses bit 0 mask. */ -#define USB_MAXEP0_bp 0 /* Maximum Endpoint Addresses bit 0 position. */ -#define USB_MAXEP1_bm (1<<1) /* Maximum Endpoint Addresses bit 1 mask. */ -#define USB_MAXEP1_bp 1 /* Maximum Endpoint Addresses bit 1 position. */ -#define USB_MAXEP2_bm (1<<2) /* Maximum Endpoint Addresses bit 2 mask. */ -#define USB_MAXEP2_bp 2 /* Maximum Endpoint Addresses bit 2 position. */ -#define USB_MAXEP3_bm (1<<3) /* Maximum Endpoint Addresses bit 3 mask. */ -#define USB_MAXEP3_bp 3 /* Maximum Endpoint Addresses bit 3 position. */ - -/* USB.CTRLB bit masks and bit positions */ -#define USB_PULLRST_bm 0x10 /* Pull during Reset bit mask. */ -#define USB_PULLRST_bp 4 /* Pull during Reset bit position. */ - -#define USB_RWAKEUP_bm 0x04 /* Remote Wake-up bit mask. */ -#define USB_RWAKEUP_bp 2 /* Remote Wake-up bit position. */ - -#define USB_GNACK_bm 0x02 /* Global NACK bit mask. */ -#define USB_GNACK_bp 1 /* Global NACK bit position. */ - -#define USB_ATTACH_bm 0x01 /* Attach bit mask. */ -#define USB_ATTACH_bp 0 /* Attach bit position. */ - -/* USB.STATUS bit masks and bit positions */ -#define USB_URESUME_bm 0x08 /* Upstream Resume bit mask. */ -#define USB_URESUME_bp 3 /* Upstream Resume bit position. */ - -#define USB_RESUME_bm 0x04 /* Resume bit mask. */ -#define USB_RESUME_bp 2 /* Resume bit position. */ - -#define USB_SUSPEND_bm 0x02 /* Bus Suspended bit mask. */ -#define USB_SUSPEND_bp 1 /* Bus Suspended bit position. */ - -#define USB_BUSRST_bm 0x01 /* Bus Reset bit mask. */ -#define USB_BUSRST_bp 0 /* Bus Reset bit position. */ - -/* USB.ADDR bit masks and bit positions */ -#define USB_ADDR_gm 0x7F /* Device Address group mask. */ -#define USB_ADDR_gp 0 /* Device Address group position. */ -#define USB_ADDR0_bm (1<<0) /* Device Address bit 0 mask. */ -#define USB_ADDR0_bp 0 /* Device Address bit 0 position. */ -#define USB_ADDR1_bm (1<<1) /* Device Address bit 1 mask. */ -#define USB_ADDR1_bp 1 /* Device Address bit 1 position. */ -#define USB_ADDR2_bm (1<<2) /* Device Address bit 2 mask. */ -#define USB_ADDR2_bp 2 /* Device Address bit 2 position. */ -#define USB_ADDR3_bm (1<<3) /* Device Address bit 3 mask. */ -#define USB_ADDR3_bp 3 /* Device Address bit 3 position. */ -#define USB_ADDR4_bm (1<<4) /* Device Address bit 4 mask. */ -#define USB_ADDR4_bp 4 /* Device Address bit 4 position. */ -#define USB_ADDR5_bm (1<<5) /* Device Address bit 5 mask. */ -#define USB_ADDR5_bp 5 /* Device Address bit 5 position. */ -#define USB_ADDR6_bm (1<<6) /* Device Address bit 6 mask. */ -#define USB_ADDR6_bp 6 /* Device Address bit 6 position. */ - -/* USB.FIFOWP bit masks and bit positions */ -#define USB_FIFOWP_gm 0x1F /* FIFO Write Pointer group mask. */ -#define USB_FIFOWP_gp 0 /* FIFO Write Pointer group position. */ -#define USB_FIFOWP0_bm (1<<0) /* FIFO Write Pointer bit 0 mask. */ -#define USB_FIFOWP0_bp 0 /* FIFO Write Pointer bit 0 position. */ -#define USB_FIFOWP1_bm (1<<1) /* FIFO Write Pointer bit 1 mask. */ -#define USB_FIFOWP1_bp 1 /* FIFO Write Pointer bit 1 position. */ -#define USB_FIFOWP2_bm (1<<2) /* FIFO Write Pointer bit 2 mask. */ -#define USB_FIFOWP2_bp 2 /* FIFO Write Pointer bit 2 position. */ -#define USB_FIFOWP3_bm (1<<3) /* FIFO Write Pointer bit 3 mask. */ -#define USB_FIFOWP3_bp 3 /* FIFO Write Pointer bit 3 position. */ -#define USB_FIFOWP4_bm (1<<4) /* FIFO Write Pointer bit 4 mask. */ -#define USB_FIFOWP4_bp 4 /* FIFO Write Pointer bit 4 position. */ - -/* USB.FIFORP bit masks and bit positions */ -#define USB_FIFORP_gm 0x1F /* FIFO Read Pointer group mask. */ -#define USB_FIFORP_gp 0 /* FIFO Read Pointer group position. */ -#define USB_FIFORP0_bm (1<<0) /* FIFO Read Pointer bit 0 mask. */ -#define USB_FIFORP0_bp 0 /* FIFO Read Pointer bit 0 position. */ -#define USB_FIFORP1_bm (1<<1) /* FIFO Read Pointer bit 1 mask. */ -#define USB_FIFORP1_bp 1 /* FIFO Read Pointer bit 1 position. */ -#define USB_FIFORP2_bm (1<<2) /* FIFO Read Pointer bit 2 mask. */ -#define USB_FIFORP2_bp 2 /* FIFO Read Pointer bit 2 position. */ -#define USB_FIFORP3_bm (1<<3) /* FIFO Read Pointer bit 3 mask. */ -#define USB_FIFORP3_bp 3 /* FIFO Read Pointer bit 3 position. */ -#define USB_FIFORP4_bm (1<<4) /* FIFO Read Pointer bit 4 mask. */ -#define USB_FIFORP4_bp 4 /* FIFO Read Pointer bit 4 position. */ - -/* USB.INTCTRLA bit masks and bit positions */ -#define USB_SOFIE_bm 0x80 /* Start Of Frame Interrupt Enable bit mask. */ -#define USB_SOFIE_bp 7 /* Start Of Frame Interrupt Enable bit position. */ - -#define USB_BUSEVIE_bm 0x40 /* Bus Event Interrupt Enable bit mask. */ -#define USB_BUSEVIE_bp 6 /* Bus Event Interrupt Enable bit position. */ - -#define USB_BUSERRIE_bm 0x20 /* Bus Error Interrupt Enable bit mask. */ -#define USB_BUSERRIE_bp 5 /* Bus Error Interrupt Enable bit position. */ - -#define USB_STALLIE_bm 0x10 /* STALL Interrupt Enable bit mask. */ -#define USB_STALLIE_bp 4 /* STALL Interrupt Enable bit position. */ - -#define USB_INTLVL_gm 0x03 /* Interrupt Level group mask. */ -#define USB_INTLVL_gp 0 /* Interrupt Level group position. */ -#define USB_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */ -#define USB_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */ -#define USB_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ -#define USB_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */ - -/* USB.INTCTRLB bit masks and bit positions */ -#define USB_TRNIE_bm 0x02 /* Transaction Complete Interrupt Enable bit mask. */ -#define USB_TRNIE_bp 1 /* Transaction Complete Interrupt Enable bit position. */ - -#define USB_SETUPIE_bm 0x01 /* SETUP Transaction Complete Interrupt Enable bit mask. */ -#define USB_SETUPIE_bp 0 /* SETUP Transaction Complete Interrupt Enable bit position. */ - -/* USB.INTFLAGSACLR bit masks and bit positions */ -#define USB_SOFIF_bm 0x80 /* Start Of Frame Interrupt Flag bit mask. */ -#define USB_SOFIF_bp 7 /* Start Of Frame Interrupt Flag bit position. */ - -#define USB_SUSPENDIF_bm 0x40 /* Suspend Interrupt Flag bit mask. */ -#define USB_SUSPENDIF_bp 6 /* Suspend Interrupt Flag bit position. */ - -#define USB_RESUMEIF_bm 0x20 /* Resume Interrupt Flag bit mask. */ -#define USB_RESUMEIF_bp 5 /* Resume Interrupt Flag bit position. */ - -#define USB_RSTIF_bm 0x10 /* Reset Interrupt Flag bit mask. */ -#define USB_RSTIF_bp 4 /* Reset Interrupt Flag bit position. */ - -#define USB_CRCIF_bm 0x08 /* Isochronous CRC Error Interrupt Flag bit mask. */ -#define USB_CRCIF_bp 3 /* Isochronous CRC Error Interrupt Flag bit position. */ - -#define USB_UNFIF_bm 0x04 /* Underflow Interrupt Flag bit mask. */ -#define USB_UNFIF_bp 2 /* Underflow Interrupt Flag bit position. */ - -#define USB_OVFIF_bm 0x02 /* Overflow Interrupt Flag bit mask. */ -#define USB_OVFIF_bp 1 /* Overflow Interrupt Flag bit position. */ - -#define USB_STALLIF_bm 0x01 /* STALL Interrupt Flag bit mask. */ -#define USB_STALLIF_bp 0 /* STALL Interrupt Flag bit position. */ - -/* USB.INTFLAGSASET bit masks and bit positions */ -/* USB_SOFIF Predefined. */ -/* USB_SOFIF Predefined. */ - -/* USB_SUSPENDIF Predefined. */ -/* USB_SUSPENDIF Predefined. */ - -/* USB_RESUMEIF Predefined. */ -/* USB_RESUMEIF Predefined. */ - -/* USB_RSTIF Predefined. */ -/* USB_RSTIF Predefined. */ - -/* USB_CRCIF Predefined. */ -/* USB_CRCIF Predefined. */ - -/* USB_UNFIF Predefined. */ -/* USB_UNFIF Predefined. */ - -/* USB_OVFIF Predefined. */ -/* USB_OVFIF Predefined. */ - -/* USB_STALLIF Predefined. */ -/* USB_STALLIF Predefined. */ - -/* USB.INTFLAGSBCLR bit masks and bit positions */ -#define USB_TRNIF_bm 0x02 /* Transaction Complete Interrupt Flag bit mask. */ -#define USB_TRNIF_bp 1 /* Transaction Complete Interrupt Flag bit position. */ - -#define USB_SETUPIF_bm 0x01 /* SETUP Transaction Complete Interrupt Flag bit mask. */ -#define USB_SETUPIF_bp 0 /* SETUP Transaction Complete Interrupt Flag bit position. */ - -/* USB.INTFLAGSBSET bit masks and bit positions */ -/* USB_TRNIF Predefined. */ -/* USB_TRNIF Predefined. */ - -/* USB_SETUPIF Predefined. */ -/* USB_SETUPIF Predefined. */ - -/* PORT - I/O Port Configuration */ -/* PORT.INTCTRL bit masks and bit positions */ -#define PORT_INT1LVL_gm 0x0C /* Port Interrupt 1 Level group mask. */ -#define PORT_INT1LVL_gp 2 /* Port Interrupt 1 Level group position. */ -#define PORT_INT1LVL0_bm (1<<2) /* Port Interrupt 1 Level bit 0 mask. */ -#define PORT_INT1LVL0_bp 2 /* Port Interrupt 1 Level bit 0 position. */ -#define PORT_INT1LVL1_bm (1<<3) /* Port Interrupt 1 Level bit 1 mask. */ -#define PORT_INT1LVL1_bp 3 /* Port Interrupt 1 Level bit 1 position. */ - -#define PORT_INT0LVL_gm 0x03 /* Port Interrupt 0 Level group mask. */ -#define PORT_INT0LVL_gp 0 /* Port Interrupt 0 Level group position. */ -#define PORT_INT0LVL0_bm (1<<0) /* Port Interrupt 0 Level bit 0 mask. */ -#define PORT_INT0LVL0_bp 0 /* Port Interrupt 0 Level bit 0 position. */ -#define PORT_INT0LVL1_bm (1<<1) /* Port Interrupt 0 Level bit 1 mask. */ -#define PORT_INT0LVL1_bp 1 /* Port Interrupt 0 Level bit 1 position. */ - -/* PORT.INTFLAGS bit masks and bit positions */ -#define PORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ -#define PORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ - -#define PORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ -#define PORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ - -/* PORT.REMAP bit masks and bit positions */ -#define PORT_SPI_bm 0x20 /* SPI bit mask. */ -#define PORT_SPI_bp 5 /* SPI bit position. */ - -#define PORT_USART0_bm 0x10 /* USART0 bit mask. */ -#define PORT_USART0_bp 4 /* USART0 bit position. */ - -#define PORT_TC0D_bm 0x08 /* Timer/Counter 0 Output Compare D bit mask. */ -#define PORT_TC0D_bp 3 /* Timer/Counter 0 Output Compare D bit position. */ - -#define PORT_TC0C_bm 0x04 /* Timer/Counter 0 Output Compare C bit mask. */ -#define PORT_TC0C_bp 2 /* Timer/Counter 0 Output Compare C bit position. */ - -#define PORT_TC0B_bm 0x02 /* Timer/Counter 0 Output Compare B bit mask. */ -#define PORT_TC0B_bp 1 /* Timer/Counter 0 Output Compare B bit position. */ - -#define PORT_TC0A_bm 0x01 /* Timer/Counter 0 Output Compare A bit mask. */ -#define PORT_TC0A_bp 0 /* Timer/Counter 0 Output Compare A bit position. */ - -/* PORT.PIN0CTRL bit masks and bit positions */ -#define PORT_SRLEN_bm 0x80 /* Slew Rate Enable bit mask. */ -#define PORT_SRLEN_bp 7 /* Slew Rate Enable bit position. */ - -#define PORT_INVEN_bm 0x40 /* Inverted I/O Enable bit mask. */ -#define PORT_INVEN_bp 6 /* Inverted I/O Enable bit position. */ - -#define PORT_OPC_gm 0x38 /* Output/Pull Configuration group mask. */ -#define PORT_OPC_gp 3 /* Output/Pull Configuration group position. */ -#define PORT_OPC0_bm (1<<3) /* Output/Pull Configuration bit 0 mask. */ -#define PORT_OPC0_bp 3 /* Output/Pull Configuration bit 0 position. */ -#define PORT_OPC1_bm (1<<4) /* Output/Pull Configuration bit 1 mask. */ -#define PORT_OPC1_bp 4 /* Output/Pull Configuration bit 1 position. */ -#define PORT_OPC2_bm (1<<5) /* Output/Pull Configuration bit 2 mask. */ -#define PORT_OPC2_bp 5 /* Output/Pull Configuration bit 2 position. */ - -#define PORT_ISC_gm 0x07 /* Input/Sense Configuration group mask. */ -#define PORT_ISC_gp 0 /* Input/Sense Configuration group position. */ -#define PORT_ISC0_bm (1<<0) /* Input/Sense Configuration bit 0 mask. */ -#define PORT_ISC0_bp 0 /* Input/Sense Configuration bit 0 position. */ -#define PORT_ISC1_bm (1<<1) /* Input/Sense Configuration bit 1 mask. */ -#define PORT_ISC1_bp 1 /* Input/Sense Configuration bit 1 position. */ -#define PORT_ISC2_bm (1<<2) /* Input/Sense Configuration bit 2 mask. */ -#define PORT_ISC2_bp 2 /* Input/Sense Configuration bit 2 position. */ - -/* PORT.PIN1CTRL bit masks and bit positions */ -/* PORT_SRLEN Predefined. */ -/* PORT_SRLEN Predefined. */ - -/* PORT_INVEN Predefined. */ -/* PORT_INVEN Predefined. */ - -/* PORT_OPC Predefined. */ -/* PORT_OPC Predefined. */ - -/* PORT_ISC Predefined. */ -/* PORT_ISC Predefined. */ - -/* PORT.PIN2CTRL bit masks and bit positions */ -/* PORT_SRLEN Predefined. */ -/* PORT_SRLEN Predefined. */ - -/* PORT_INVEN Predefined. */ -/* PORT_INVEN Predefined. */ - -/* PORT_OPC Predefined. */ -/* PORT_OPC Predefined. */ - -/* PORT_ISC Predefined. */ -/* PORT_ISC Predefined. */ - -/* PORT.PIN3CTRL bit masks and bit positions */ -/* PORT_SRLEN Predefined. */ -/* PORT_SRLEN Predefined. */ - -/* PORT_INVEN Predefined. */ -/* PORT_INVEN Predefined. */ - -/* PORT_OPC Predefined. */ -/* PORT_OPC Predefined. */ - -/* PORT_ISC Predefined. */ -/* PORT_ISC Predefined. */ - -/* PORT.PIN4CTRL bit masks and bit positions */ -/* PORT_SRLEN Predefined. */ -/* PORT_SRLEN Predefined. */ - -/* PORT_INVEN Predefined. */ -/* PORT_INVEN Predefined. */ - -/* PORT_OPC Predefined. */ -/* PORT_OPC Predefined. */ - -/* PORT_ISC Predefined. */ -/* PORT_ISC Predefined. */ - -/* PORT.PIN5CTRL bit masks and bit positions */ -/* PORT_SRLEN Predefined. */ -/* PORT_SRLEN Predefined. */ - -/* PORT_INVEN Predefined. */ -/* PORT_INVEN Predefined. */ - -/* PORT_OPC Predefined. */ -/* PORT_OPC Predefined. */ - -/* PORT_ISC Predefined. */ -/* PORT_ISC Predefined. */ - -/* PORT.PIN6CTRL bit masks and bit positions */ -/* PORT_SRLEN Predefined. */ -/* PORT_SRLEN Predefined. */ - -/* PORT_INVEN Predefined. */ -/* PORT_INVEN Predefined. */ - -/* PORT_OPC Predefined. */ -/* PORT_OPC Predefined. */ - -/* PORT_ISC Predefined. */ -/* PORT_ISC Predefined. */ - -/* PORT.PIN7CTRL bit masks and bit positions */ -/* PORT_SRLEN Predefined. */ -/* PORT_SRLEN Predefined. */ - -/* PORT_INVEN Predefined. */ -/* PORT_INVEN Predefined. */ - -/* PORT_OPC Predefined. */ -/* PORT_OPC Predefined. */ - -/* PORT_ISC Predefined. */ -/* PORT_ISC Predefined. */ - -/* TC - 16-bit Timer/Counter With PWM */ -/* TC0.CTRLA bit masks and bit positions */ -#define TC0_CLKSEL_gm 0x0F /* Clock Selection group mask. */ -#define TC0_CLKSEL_gp 0 /* Clock Selection group position. */ -#define TC0_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ -#define TC0_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ -#define TC0_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ -#define TC0_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ -#define TC0_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ -#define TC0_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ -#define TC0_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ -#define TC0_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ - -/* TC0.CTRLB bit masks and bit positions */ -#define TC0_CCDEN_bm 0x80 /* Compare or Capture D Enable bit mask. */ -#define TC0_CCDEN_bp 7 /* Compare or Capture D Enable bit position. */ - -#define TC0_CCCEN_bm 0x40 /* Compare or Capture C Enable bit mask. */ -#define TC0_CCCEN_bp 6 /* Compare or Capture C Enable bit position. */ - -#define TC0_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ -#define TC0_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ - -#define TC0_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ -#define TC0_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ - -#define TC0_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ -#define TC0_WGMODE_gp 0 /* Waveform generation mode group position. */ -#define TC0_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ -#define TC0_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ -#define TC0_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ -#define TC0_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ -#define TC0_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ -#define TC0_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ - -/* TC0.CTRLC bit masks and bit positions */ -#define TC0_CMPD_bm 0x08 /* Compare D Output Value bit mask. */ -#define TC0_CMPD_bp 3 /* Compare D Output Value bit position. */ - -#define TC0_CMPC_bm 0x04 /* Compare C Output Value bit mask. */ -#define TC0_CMPC_bp 2 /* Compare C Output Value bit position. */ - -#define TC0_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ -#define TC0_CMPB_bp 1 /* Compare B Output Value bit position. */ - -#define TC0_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ -#define TC0_CMPA_bp 0 /* Compare A Output Value bit position. */ - -/* TC0.CTRLD bit masks and bit positions */ -#define TC0_EVACT_gm 0xE0 /* Event Action group mask. */ -#define TC0_EVACT_gp 5 /* Event Action group position. */ -#define TC0_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ -#define TC0_EVACT0_bp 5 /* Event Action bit 0 position. */ -#define TC0_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ -#define TC0_EVACT1_bp 6 /* Event Action bit 1 position. */ -#define TC0_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ -#define TC0_EVACT2_bp 7 /* Event Action bit 2 position. */ - -#define TC0_EVDLY_bm 0x10 /* Event Delay bit mask. */ -#define TC0_EVDLY_bp 4 /* Event Delay bit position. */ - -#define TC0_EVSEL_gm 0x0F /* Event Source Select group mask. */ -#define TC0_EVSEL_gp 0 /* Event Source Select group position. */ -#define TC0_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ -#define TC0_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ -#define TC0_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ -#define TC0_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ -#define TC0_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ -#define TC0_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ -#define TC0_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ -#define TC0_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ - -/* TC0.CTRLE bit masks and bit positions */ -#define TC0_BYTEM_gm 0x03 /* Byte Mode group mask. */ -#define TC0_BYTEM_gp 0 /* Byte Mode group position. */ -#define TC0_BYTEM0_bm (1<<0) /* Byte Mode bit 0 mask. */ -#define TC0_BYTEM0_bp 0 /* Byte Mode bit 0 position. */ -#define TC0_BYTEM1_bm (1<<1) /* Byte Mode bit 1 mask. */ -#define TC0_BYTEM1_bp 1 /* Byte Mode bit 1 position. */ - -/* TC0.INTCTRLA bit masks and bit positions */ -#define TC0_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ -#define TC0_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ -#define TC0_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ -#define TC0_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ -#define TC0_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ -#define TC0_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ - -#define TC0_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ -#define TC0_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ -#define TC0_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ -#define TC0_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ -#define TC0_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ -#define TC0_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ - -/* TC0.INTCTRLB bit masks and bit positions */ -#define TC0_CCDINTLVL_gm 0xC0 /* Compare or Capture D Interrupt Level group mask. */ -#define TC0_CCDINTLVL_gp 6 /* Compare or Capture D Interrupt Level group position. */ -#define TC0_CCDINTLVL0_bm (1<<6) /* Compare or Capture D Interrupt Level bit 0 mask. */ -#define TC0_CCDINTLVL0_bp 6 /* Compare or Capture D Interrupt Level bit 0 position. */ -#define TC0_CCDINTLVL1_bm (1<<7) /* Compare or Capture D Interrupt Level bit 1 mask. */ -#define TC0_CCDINTLVL1_bp 7 /* Compare or Capture D Interrupt Level bit 1 position. */ - -#define TC0_CCCINTLVL_gm 0x30 /* Compare or Capture C Interrupt Level group mask. */ -#define TC0_CCCINTLVL_gp 4 /* Compare or Capture C Interrupt Level group position. */ -#define TC0_CCCINTLVL0_bm (1<<4) /* Compare or Capture C Interrupt Level bit 0 mask. */ -#define TC0_CCCINTLVL0_bp 4 /* Compare or Capture C Interrupt Level bit 0 position. */ -#define TC0_CCCINTLVL1_bm (1<<5) /* Compare or Capture C Interrupt Level bit 1 mask. */ -#define TC0_CCCINTLVL1_bp 5 /* Compare or Capture C Interrupt Level bit 1 position. */ - -#define TC0_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ -#define TC0_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ -#define TC0_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ -#define TC0_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ -#define TC0_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ -#define TC0_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ - -#define TC0_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ -#define TC0_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ -#define TC0_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ -#define TC0_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ -#define TC0_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ -#define TC0_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ - -/* TC0.CTRLFCLR bit masks and bit positions */ -#define TC0_CMD_gm 0x0C /* Command group mask. */ -#define TC0_CMD_gp 2 /* Command group position. */ -#define TC0_CMD0_bm (1<<2) /* Command bit 0 mask. */ -#define TC0_CMD0_bp 2 /* Command bit 0 position. */ -#define TC0_CMD1_bm (1<<3) /* Command bit 1 mask. */ -#define TC0_CMD1_bp 3 /* Command bit 1 position. */ - -#define TC0_LUPD_bm 0x02 /* Lock Update bit mask. */ -#define TC0_LUPD_bp 1 /* Lock Update bit position. */ - -#define TC0_DIR_bm 0x01 /* Direction bit mask. */ -#define TC0_DIR_bp 0 /* Direction bit position. */ - -/* TC0.CTRLFSET bit masks and bit positions */ -/* TC0_CMD Predefined. */ -/* TC0_CMD Predefined. */ - -/* TC0_LUPD Predefined. */ -/* TC0_LUPD Predefined. */ - -/* TC0_DIR Predefined. */ -/* TC0_DIR Predefined. */ - -/* TC0.CTRLGCLR bit masks and bit positions */ -#define TC0_CCDBV_bm 0x10 /* Compare or Capture D Buffer Valid bit mask. */ -#define TC0_CCDBV_bp 4 /* Compare or Capture D Buffer Valid bit position. */ - -#define TC0_CCCBV_bm 0x08 /* Compare or Capture C Buffer Valid bit mask. */ -#define TC0_CCCBV_bp 3 /* Compare or Capture C Buffer Valid bit position. */ - -#define TC0_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ -#define TC0_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ - -#define TC0_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ -#define TC0_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ - -#define TC0_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ -#define TC0_PERBV_bp 0 /* Period Buffer Valid bit position. */ - -/* TC0.CTRLGSET bit masks and bit positions */ -/* TC0_CCDBV Predefined. */ -/* TC0_CCDBV Predefined. */ - -/* TC0_CCCBV Predefined. */ -/* TC0_CCCBV Predefined. */ - -/* TC0_CCBBV Predefined. */ -/* TC0_CCBBV Predefined. */ - -/* TC0_CCABV Predefined. */ -/* TC0_CCABV Predefined. */ - -/* TC0_PERBV Predefined. */ -/* TC0_PERBV Predefined. */ - -/* TC0.INTFLAGS bit masks and bit positions */ -#define TC0_CCDIF_bm 0x80 /* Compare or Capture D Interrupt Flag bit mask. */ -#define TC0_CCDIF_bp 7 /* Compare or Capture D Interrupt Flag bit position. */ - -#define TC0_CCCIF_bm 0x40 /* Compare or Capture C Interrupt Flag bit mask. */ -#define TC0_CCCIF_bp 6 /* Compare or Capture C Interrupt Flag bit position. */ - -#define TC0_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ -#define TC0_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ - -#define TC0_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ -#define TC0_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ - -#define TC0_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ -#define TC0_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ - -#define TC0_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ -#define TC0_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ - -/* TC1.CTRLA bit masks and bit positions */ -#define TC1_CLKSEL_gm 0x0F /* Clock Selection group mask. */ -#define TC1_CLKSEL_gp 0 /* Clock Selection group position. */ -#define TC1_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ -#define TC1_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ -#define TC1_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ -#define TC1_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ -#define TC1_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ -#define TC1_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ -#define TC1_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ -#define TC1_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ - -/* TC1.CTRLB bit masks and bit positions */ -#define TC1_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ -#define TC1_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ - -#define TC1_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ -#define TC1_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ - -#define TC1_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ -#define TC1_WGMODE_gp 0 /* Waveform generation mode group position. */ -#define TC1_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ -#define TC1_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ -#define TC1_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ -#define TC1_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ -#define TC1_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ -#define TC1_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ - -/* TC1.CTRLC bit masks and bit positions */ -#define TC1_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ -#define TC1_CMPB_bp 1 /* Compare B Output Value bit position. */ - -#define TC1_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ -#define TC1_CMPA_bp 0 /* Compare A Output Value bit position. */ - -/* TC1.CTRLD bit masks and bit positions */ -#define TC1_EVACT_gm 0xE0 /* Event Action group mask. */ -#define TC1_EVACT_gp 5 /* Event Action group position. */ -#define TC1_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ -#define TC1_EVACT0_bp 5 /* Event Action bit 0 position. */ -#define TC1_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ -#define TC1_EVACT1_bp 6 /* Event Action bit 1 position. */ -#define TC1_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ -#define TC1_EVACT2_bp 7 /* Event Action bit 2 position. */ - -#define TC1_EVDLY_bm 0x10 /* Event Delay bit mask. */ -#define TC1_EVDLY_bp 4 /* Event Delay bit position. */ - -#define TC1_EVSEL_gm 0x0F /* Event Source Select group mask. */ -#define TC1_EVSEL_gp 0 /* Event Source Select group position. */ -#define TC1_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ -#define TC1_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ -#define TC1_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ -#define TC1_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ -#define TC1_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ -#define TC1_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ -#define TC1_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ -#define TC1_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ - -/* TC1.CTRLE bit masks and bit positions */ -#define TC1_BYTEM_bm 0x01 /* Byte Mode bit mask. */ -#define TC1_BYTEM_bp 0 /* Byte Mode bit position. */ - -/* TC1.INTCTRLA bit masks and bit positions */ -#define TC1_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ -#define TC1_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ -#define TC1_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ -#define TC1_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ -#define TC1_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ -#define TC1_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ - -#define TC1_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ -#define TC1_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ -#define TC1_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ -#define TC1_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ -#define TC1_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ -#define TC1_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ - -/* TC1.INTCTRLB bit masks and bit positions */ -#define TC1_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ -#define TC1_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ -#define TC1_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ -#define TC1_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ -#define TC1_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ -#define TC1_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ - -#define TC1_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ -#define TC1_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ -#define TC1_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ -#define TC1_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ -#define TC1_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ -#define TC1_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ - -/* TC1.CTRLFCLR bit masks and bit positions */ -#define TC1_CMD_gm 0x0C /* Command group mask. */ -#define TC1_CMD_gp 2 /* Command group position. */ -#define TC1_CMD0_bm (1<<2) /* Command bit 0 mask. */ -#define TC1_CMD0_bp 2 /* Command bit 0 position. */ -#define TC1_CMD1_bm (1<<3) /* Command bit 1 mask. */ -#define TC1_CMD1_bp 3 /* Command bit 1 position. */ - -#define TC1_LUPD_bm 0x02 /* Lock Update bit mask. */ -#define TC1_LUPD_bp 1 /* Lock Update bit position. */ - -#define TC1_DIR_bm 0x01 /* Direction bit mask. */ -#define TC1_DIR_bp 0 /* Direction bit position. */ - -/* TC1.CTRLFSET bit masks and bit positions */ -/* TC1_CMD Predefined. */ -/* TC1_CMD Predefined. */ - -/* TC1_LUPD Predefined. */ -/* TC1_LUPD Predefined. */ - -/* TC1_DIR Predefined. */ -/* TC1_DIR Predefined. */ - -/* TC1.CTRLGCLR bit masks and bit positions */ -#define TC1_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ -#define TC1_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ - -#define TC1_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ -#define TC1_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ - -#define TC1_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ -#define TC1_PERBV_bp 0 /* Period Buffer Valid bit position. */ - -/* TC1.CTRLGSET bit masks and bit positions */ -/* TC1_CCBBV Predefined. */ -/* TC1_CCBBV Predefined. */ - -/* TC1_CCABV Predefined. */ -/* TC1_CCABV Predefined. */ - -/* TC1_PERBV Predefined. */ -/* TC1_PERBV Predefined. */ - -/* TC1.INTFLAGS bit masks and bit positions */ -#define TC1_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ -#define TC1_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ - -#define TC1_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ -#define TC1_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ - -#define TC1_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ -#define TC1_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ - -#define TC1_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ -#define TC1_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ - -/* TC2 - 16-bit Timer/Counter type 2 */ -/* TC2.CTRLA bit masks and bit positions */ -#define TC2_CLKSEL_gm 0x0F /* Clock Selection group mask. */ -#define TC2_CLKSEL_gp 0 /* Clock Selection group position. */ -#define TC2_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ -#define TC2_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ -#define TC2_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ -#define TC2_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ -#define TC2_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ -#define TC2_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ -#define TC2_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ -#define TC2_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ - -/* TC2.CTRLB bit masks and bit positions */ -#define TC2_HCMPDEN_bm 0x80 /* High Byte Compare D Enable bit mask. */ -#define TC2_HCMPDEN_bp 7 /* High Byte Compare D Enable bit position. */ - -#define TC2_HCMPCEN_bm 0x40 /* High Byte Compare C Enable bit mask. */ -#define TC2_HCMPCEN_bp 6 /* High Byte Compare C Enable bit position. */ - -#define TC2_HCMPBEN_bm 0x20 /* High Byte Compare B Enable bit mask. */ -#define TC2_HCMPBEN_bp 5 /* High Byte Compare B Enable bit position. */ - -#define TC2_HCMPAEN_bm 0x10 /* High Byte Compare A Enable bit mask. */ -#define TC2_HCMPAEN_bp 4 /* High Byte Compare A Enable bit position. */ - -#define TC2_LCMPDEN_bm 0x08 /* Low Byte Compare D Enable bit mask. */ -#define TC2_LCMPDEN_bp 3 /* Low Byte Compare D Enable bit position. */ - -#define TC2_LCMPCEN_bm 0x04 /* Low Byte Compare C Enable bit mask. */ -#define TC2_LCMPCEN_bp 2 /* Low Byte Compare C Enable bit position. */ - -#define TC2_LCMPBEN_bm 0x02 /* Low Byte Compare B Enable bit mask. */ -#define TC2_LCMPBEN_bp 1 /* Low Byte Compare B Enable bit position. */ - -#define TC2_LCMPAEN_bm 0x01 /* Low Byte Compare A Enable bit mask. */ -#define TC2_LCMPAEN_bp 0 /* Low Byte Compare A Enable bit position. */ - -/* TC2.CTRLC bit masks and bit positions */ -#define TC2_HCMPD_bm 0x80 /* High Byte Compare D Output Value bit mask. */ -#define TC2_HCMPD_bp 7 /* High Byte Compare D Output Value bit position. */ - -#define TC2_HCMPC_bm 0x40 /* High Byte Compare C Output Value bit mask. */ -#define TC2_HCMPC_bp 6 /* High Byte Compare C Output Value bit position. */ - -#define TC2_HCMPB_bm 0x20 /* High Byte Compare B Output Value bit mask. */ -#define TC2_HCMPB_bp 5 /* High Byte Compare B Output Value bit position. */ - -#define TC2_HCMPA_bm 0x10 /* High Byte Compare A Output Value bit mask. */ -#define TC2_HCMPA_bp 4 /* High Byte Compare A Output Value bit position. */ - -#define TC2_LCMPD_bm 0x08 /* Low Byte Compare D Output Value bit mask. */ -#define TC2_LCMPD_bp 3 /* Low Byte Compare D Output Value bit position. */ - -#define TC2_LCMPC_bm 0x04 /* Low Byte Compare C Output Value bit mask. */ -#define TC2_LCMPC_bp 2 /* Low Byte Compare C Output Value bit position. */ - -#define TC2_LCMPB_bm 0x02 /* Low Byte Compare B Output Value bit mask. */ -#define TC2_LCMPB_bp 1 /* Low Byte Compare B Output Value bit position. */ - -#define TC2_LCMPA_bm 0x01 /* Low Byte Compare A Output Value bit mask. */ -#define TC2_LCMPA_bp 0 /* Low Byte Compare A Output Value bit position. */ - -/* TC2.CTRLE bit masks and bit positions */ -#define TC2_BYTEM_gm 0x03 /* Byte Mode group mask. */ -#define TC2_BYTEM_gp 0 /* Byte Mode group position. */ -#define TC2_BYTEM0_bm (1<<0) /* Byte Mode bit 0 mask. */ -#define TC2_BYTEM0_bp 0 /* Byte Mode bit 0 position. */ -#define TC2_BYTEM1_bm (1<<1) /* Byte Mode bit 1 mask. */ -#define TC2_BYTEM1_bp 1 /* Byte Mode bit 1 position. */ - -/* TC2.INTCTRLA bit masks and bit positions */ -#define TC2_HUNFINTLVL_gm 0x0C /* High Byte Underflow Interrupt Level group mask. */ -#define TC2_HUNFINTLVL_gp 2 /* High Byte Underflow Interrupt Level group position. */ -#define TC2_HUNFINTLVL0_bm (1<<2) /* High Byte Underflow Interrupt Level bit 0 mask. */ -#define TC2_HUNFINTLVL0_bp 2 /* High Byte Underflow Interrupt Level bit 0 position. */ -#define TC2_HUNFINTLVL1_bm (1<<3) /* High Byte Underflow Interrupt Level bit 1 mask. */ -#define TC2_HUNFINTLVL1_bp 3 /* High Byte Underflow Interrupt Level bit 1 position. */ - -#define TC2_LUNFINTLVL_gm 0x03 /* Low Byte Underflow interrupt level group mask. */ -#define TC2_LUNFINTLVL_gp 0 /* Low Byte Underflow interrupt level group position. */ -#define TC2_LUNFINTLVL0_bm (1<<0) /* Low Byte Underflow interrupt level bit 0 mask. */ -#define TC2_LUNFINTLVL0_bp 0 /* Low Byte Underflow interrupt level bit 0 position. */ -#define TC2_LUNFINTLVL1_bm (1<<1) /* Low Byte Underflow interrupt level bit 1 mask. */ -#define TC2_LUNFINTLVL1_bp 1 /* Low Byte Underflow interrupt level bit 1 position. */ - -/* TC2.INTCTRLB bit masks and bit positions */ -#define TC2_LCMPDINTLVL_gm 0xC0 /* Low Byte Compare D Interrupt Level group mask. */ -#define TC2_LCMPDINTLVL_gp 6 /* Low Byte Compare D Interrupt Level group position. */ -#define TC2_LCMPDINTLVL0_bm (1<<6) /* Low Byte Compare D Interrupt Level bit 0 mask. */ -#define TC2_LCMPDINTLVL0_bp 6 /* Low Byte Compare D Interrupt Level bit 0 position. */ -#define TC2_LCMPDINTLVL1_bm (1<<7) /* Low Byte Compare D Interrupt Level bit 1 mask. */ -#define TC2_LCMPDINTLVL1_bp 7 /* Low Byte Compare D Interrupt Level bit 1 position. */ - -#define TC2_LCMPCINTLVL_gm 0x30 /* Low Byte Compare C Interrupt Level group mask. */ -#define TC2_LCMPCINTLVL_gp 4 /* Low Byte Compare C Interrupt Level group position. */ -#define TC2_LCMPCINTLVL0_bm (1<<4) /* Low Byte Compare C Interrupt Level bit 0 mask. */ -#define TC2_LCMPCINTLVL0_bp 4 /* Low Byte Compare C Interrupt Level bit 0 position. */ -#define TC2_LCMPCINTLVL1_bm (1<<5) /* Low Byte Compare C Interrupt Level bit 1 mask. */ -#define TC2_LCMPCINTLVL1_bp 5 /* Low Byte Compare C Interrupt Level bit 1 position. */ - -#define TC2_LCMPBINTLVL_gm 0x0C /* Low Byte Compare B Interrupt Level group mask. */ -#define TC2_LCMPBINTLVL_gp 2 /* Low Byte Compare B Interrupt Level group position. */ -#define TC2_LCMPBINTLVL0_bm (1<<2) /* Low Byte Compare B Interrupt Level bit 0 mask. */ -#define TC2_LCMPBINTLVL0_bp 2 /* Low Byte Compare B Interrupt Level bit 0 position. */ -#define TC2_LCMPBINTLVL1_bm (1<<3) /* Low Byte Compare B Interrupt Level bit 1 mask. */ -#define TC2_LCMPBINTLVL1_bp 3 /* Low Byte Compare B Interrupt Level bit 1 position. */ - -#define TC2_LCMPAINTLVL_gm 0x03 /* Low Byte Compare A Interrupt Level group mask. */ -#define TC2_LCMPAINTLVL_gp 0 /* Low Byte Compare A Interrupt Level group position. */ -#define TC2_LCMPAINTLVL0_bm (1<<0) /* Low Byte Compare A Interrupt Level bit 0 mask. */ -#define TC2_LCMPAINTLVL0_bp 0 /* Low Byte Compare A Interrupt Level bit 0 position. */ -#define TC2_LCMPAINTLVL1_bm (1<<1) /* Low Byte Compare A Interrupt Level bit 1 mask. */ -#define TC2_LCMPAINTLVL1_bp 1 /* Low Byte Compare A Interrupt Level bit 1 position. */ - -/* TC2.CTRLF bit masks and bit positions */ -#define TC2_CMD_gm 0x0C /* Command group mask. */ -#define TC2_CMD_gp 2 /* Command group position. */ -#define TC2_CMD0_bm (1<<2) /* Command bit 0 mask. */ -#define TC2_CMD0_bp 2 /* Command bit 0 position. */ -#define TC2_CMD1_bm (1<<3) /* Command bit 1 mask. */ -#define TC2_CMD1_bp 3 /* Command bit 1 position. */ - -#define TC2_CMDEN_gm 0x03 /* Command Enable group mask. */ -#define TC2_CMDEN_gp 0 /* Command Enable group position. */ -#define TC2_CMDEN0_bm (1<<0) /* Command Enable bit 0 mask. */ -#define TC2_CMDEN0_bp 0 /* Command Enable bit 0 position. */ -#define TC2_CMDEN1_bm (1<<1) /* Command Enable bit 1 mask. */ -#define TC2_CMDEN1_bp 1 /* Command Enable bit 1 position. */ - -/* TC2.INTFLAGS bit masks and bit positions */ -#define TC2_LCMPDIF_bm 0x80 /* Low Byte Compare D Interrupt Flag bit mask. */ -#define TC2_LCMPDIF_bp 7 /* Low Byte Compare D Interrupt Flag bit position. */ - -#define TC2_LCMPCIF_bm 0x40 /* Low Byte Compare C Interrupt Flag bit mask. */ -#define TC2_LCMPCIF_bp 6 /* Low Byte Compare C Interrupt Flag bit position. */ - -#define TC2_LCMPBIF_bm 0x20 /* Low Byte Compare B Interrupt Flag bit mask. */ -#define TC2_LCMPBIF_bp 5 /* Low Byte Compare B Interrupt Flag bit position. */ - -#define TC2_LCMPAIF_bm 0x10 /* Low Byte Compare A Interrupt Flag bit mask. */ -#define TC2_LCMPAIF_bp 4 /* Low Byte Compare A Interrupt Flag bit position. */ - -#define TC2_HUNFIF_bm 0x02 /* High Byte Underflow Interrupt Flag bit mask. */ -#define TC2_HUNFIF_bp 1 /* High Byte Underflow Interrupt Flag bit position. */ - -#define TC2_LUNFIF_bm 0x01 /* Low Byte Underflow Interrupt Flag bit mask. */ -#define TC2_LUNFIF_bp 0 /* Low Byte Underflow Interrupt Flag bit position. */ - -/* AWEX - Timer/Counter Advanced Waveform Extension */ -/* AWEX.CTRL bit masks and bit positions */ -#define AWEX_PGM_bm 0x20 /* Pattern Generation Mode bit mask. */ -#define AWEX_PGM_bp 5 /* Pattern Generation Mode bit position. */ - -#define AWEX_CWCM_bm 0x10 /* Common Waveform Channel Mode bit mask. */ -#define AWEX_CWCM_bp 4 /* Common Waveform Channel Mode bit position. */ - -#define AWEX_DTICCDEN_bm 0x08 /* Dead Time Insertion Compare Channel D Enable bit mask. */ -#define AWEX_DTICCDEN_bp 3 /* Dead Time Insertion Compare Channel D Enable bit position. */ - -#define AWEX_DTICCCEN_bm 0x04 /* Dead Time Insertion Compare Channel C Enable bit mask. */ -#define AWEX_DTICCCEN_bp 2 /* Dead Time Insertion Compare Channel C Enable bit position. */ - -#define AWEX_DTICCBEN_bm 0x02 /* Dead Time Insertion Compare Channel B Enable bit mask. */ -#define AWEX_DTICCBEN_bp 1 /* Dead Time Insertion Compare Channel B Enable bit position. */ - -#define AWEX_DTICCAEN_bm 0x01 /* Dead Time Insertion Compare Channel A Enable bit mask. */ -#define AWEX_DTICCAEN_bp 0 /* Dead Time Insertion Compare Channel A Enable bit position. */ - -/* AWEX.FDCTRL bit masks and bit positions */ -#define AWEX_FDDBD_bm 0x10 /* Fault Detect on Disable Break Disable bit mask. */ -#define AWEX_FDDBD_bp 4 /* Fault Detect on Disable Break Disable bit position. */ - -#define AWEX_FDMODE_bm 0x04 /* Fault Detect Mode bit mask. */ -#define AWEX_FDMODE_bp 2 /* Fault Detect Mode bit position. */ - -#define AWEX_FDACT_gm 0x03 /* Fault Detect Action group mask. */ -#define AWEX_FDACT_gp 0 /* Fault Detect Action group position. */ -#define AWEX_FDACT0_bm (1<<0) /* Fault Detect Action bit 0 mask. */ -#define AWEX_FDACT0_bp 0 /* Fault Detect Action bit 0 position. */ -#define AWEX_FDACT1_bm (1<<1) /* Fault Detect Action bit 1 mask. */ -#define AWEX_FDACT1_bp 1 /* Fault Detect Action bit 1 position. */ - -/* AWEX.STATUS bit masks and bit positions */ -#define AWEX_FDF_bm 0x04 /* Fault Detect Flag bit mask. */ -#define AWEX_FDF_bp 2 /* Fault Detect Flag bit position. */ - -#define AWEX_DTHSBUFV_bm 0x02 /* Dead Time High Side Buffer Valid bit mask. */ -#define AWEX_DTHSBUFV_bp 1 /* Dead Time High Side Buffer Valid bit position. */ - -#define AWEX_DTLSBUFV_bm 0x01 /* Dead Time Low Side Buffer Valid bit mask. */ -#define AWEX_DTLSBUFV_bp 0 /* Dead Time Low Side Buffer Valid bit position. */ - -/* AWEX.STATUSSET bit masks and bit positions */ -/* AWEX_FDF Predefined. */ -/* AWEX_FDF Predefined. */ - -/* AWEX_DTHSBUFV Predefined. */ -/* AWEX_DTHSBUFV Predefined. */ - -/* AWEX_DTLSBUFV Predefined. */ -/* AWEX_DTLSBUFV Predefined. */ - -/* HIRES - Timer/Counter High-Resolution Extension */ -/* HIRES.CTRLA bit masks and bit positions */ -#define HIRES_HREN_gm 0x03 /* High Resolution Enable group mask. */ -#define HIRES_HREN_gp 0 /* High Resolution Enable group position. */ -#define HIRES_HREN0_bm (1<<0) /* High Resolution Enable bit 0 mask. */ -#define HIRES_HREN0_bp 0 /* High Resolution Enable bit 0 position. */ -#define HIRES_HREN1_bm (1<<1) /* High Resolution Enable bit 1 mask. */ -#define HIRES_HREN1_bp 1 /* High Resolution Enable bit 1 position. */ - -/* USART - Universal Asynchronous Receiver-Transmitter */ -/* USART.STATUS bit masks and bit positions */ -#define USART_RXCIF_bm 0x80 /* Receive Interrupt Flag bit mask. */ -#define USART_RXCIF_bp 7 /* Receive Interrupt Flag bit position. */ - -#define USART_TXCIF_bm 0x40 /* Transmit Interrupt Flag bit mask. */ -#define USART_TXCIF_bp 6 /* Transmit Interrupt Flag bit position. */ - -#define USART_DREIF_bm 0x20 /* Data Register Empty Flag bit mask. */ -#define USART_DREIF_bp 5 /* Data Register Empty Flag bit position. */ - -#define USART_FERR_bm 0x10 /* Frame Error bit mask. */ -#define USART_FERR_bp 4 /* Frame Error bit position. */ - -#define USART_BUFOVF_bm 0x08 /* Buffer Overflow bit mask. */ -#define USART_BUFOVF_bp 3 /* Buffer Overflow bit position. */ - -#define USART_PERR_bm 0x04 /* Parity Error bit mask. */ -#define USART_PERR_bp 2 /* Parity Error bit position. */ - -#define USART_RXB8_bm 0x01 /* Receive Bit 8 bit mask. */ -#define USART_RXB8_bp 0 /* Receive Bit 8 bit position. */ - -/* USART.CTRLA bit masks and bit positions */ -#define USART_RXCINTLVL_gm 0x30 /* Receive Interrupt Level group mask. */ -#define USART_RXCINTLVL_gp 4 /* Receive Interrupt Level group position. */ -#define USART_RXCINTLVL0_bm (1<<4) /* Receive Interrupt Level bit 0 mask. */ -#define USART_RXCINTLVL0_bp 4 /* Receive Interrupt Level bit 0 position. */ -#define USART_RXCINTLVL1_bm (1<<5) /* Receive Interrupt Level bit 1 mask. */ -#define USART_RXCINTLVL1_bp 5 /* Receive Interrupt Level bit 1 position. */ - -#define USART_TXCINTLVL_gm 0x0C /* Transmit Interrupt Level group mask. */ -#define USART_TXCINTLVL_gp 2 /* Transmit Interrupt Level group position. */ -#define USART_TXCINTLVL0_bm (1<<2) /* Transmit Interrupt Level bit 0 mask. */ -#define USART_TXCINTLVL0_bp 2 /* Transmit Interrupt Level bit 0 position. */ -#define USART_TXCINTLVL1_bm (1<<3) /* Transmit Interrupt Level bit 1 mask. */ -#define USART_TXCINTLVL1_bp 3 /* Transmit Interrupt Level bit 1 position. */ - -#define USART_DREINTLVL_gm 0x03 /* Data Register Empty Interrupt Level group mask. */ -#define USART_DREINTLVL_gp 0 /* Data Register Empty Interrupt Level group position. */ -#define USART_DREINTLVL0_bm (1<<0) /* Data Register Empty Interrupt Level bit 0 mask. */ -#define USART_DREINTLVL0_bp 0 /* Data Register Empty Interrupt Level bit 0 position. */ -#define USART_DREINTLVL1_bm (1<<1) /* Data Register Empty Interrupt Level bit 1 mask. */ -#define USART_DREINTLVL1_bp 1 /* Data Register Empty Interrupt Level bit 1 position. */ - -/* USART.CTRLB bit masks and bit positions */ -#define USART_RXEN_bm 0x10 /* Receiver Enable bit mask. */ -#define USART_RXEN_bp 4 /* Receiver Enable bit position. */ - -#define USART_TXEN_bm 0x08 /* Transmitter Enable bit mask. */ -#define USART_TXEN_bp 3 /* Transmitter Enable bit position. */ - -#define USART_CLK2X_bm 0x04 /* Double transmission speed bit mask. */ -#define USART_CLK2X_bp 2 /* Double transmission speed bit position. */ - -#define USART_MPCM_bm 0x02 /* Multi-processor Communication Mode bit mask. */ -#define USART_MPCM_bp 1 /* Multi-processor Communication Mode bit position. */ - -#define USART_TXB8_bm 0x01 /* Transmit bit 8 bit mask. */ -#define USART_TXB8_bp 0 /* Transmit bit 8 bit position. */ - -/* USART.CTRLC bit masks and bit positions */ -#define USART_CMODE_gm 0xC0 /* Communication Mode group mask. */ -#define USART_CMODE_gp 6 /* Communication Mode group position. */ -#define USART_CMODE0_bm (1<<6) /* Communication Mode bit 0 mask. */ -#define USART_CMODE0_bp 6 /* Communication Mode bit 0 position. */ -#define USART_CMODE1_bm (1<<7) /* Communication Mode bit 1 mask. */ -#define USART_CMODE1_bp 7 /* Communication Mode bit 1 position. */ - -#define USART_PMODE_gm 0x30 /* Parity Mode group mask. */ -#define USART_PMODE_gp 4 /* Parity Mode group position. */ -#define USART_PMODE0_bm (1<<4) /* Parity Mode bit 0 mask. */ -#define USART_PMODE0_bp 4 /* Parity Mode bit 0 position. */ -#define USART_PMODE1_bm (1<<5) /* Parity Mode bit 1 mask. */ -#define USART_PMODE1_bp 5 /* Parity Mode bit 1 position. */ - -#define USART_SBMODE_bm 0x08 /* Stop Bit Mode bit mask. */ -#define USART_SBMODE_bp 3 /* Stop Bit Mode bit position. */ - -#define USART_CHSIZE_gm 0x07 /* Character Size group mask. */ -#define USART_CHSIZE_gp 0 /* Character Size group position. */ -#define USART_CHSIZE0_bm (1<<0) /* Character Size bit 0 mask. */ -#define USART_CHSIZE0_bp 0 /* Character Size bit 0 position. */ -#define USART_CHSIZE1_bm (1<<1) /* Character Size bit 1 mask. */ -#define USART_CHSIZE1_bp 1 /* Character Size bit 1 position. */ -#define USART_CHSIZE2_bm (1<<2) /* Character Size bit 2 mask. */ -#define USART_CHSIZE2_bp 2 /* Character Size bit 2 position. */ - -/* USART.BAUDCTRLA bit masks and bit positions */ -#define USART_BSEL_gm 0xFF /* Baud Rate Selection Bits [7:0] group mask. */ -#define USART_BSEL_gp 0 /* Baud Rate Selection Bits [7:0] group position. */ -#define USART_BSEL0_bm (1<<0) /* Baud Rate Selection Bits [7:0] bit 0 mask. */ -#define USART_BSEL0_bp 0 /* Baud Rate Selection Bits [7:0] bit 0 position. */ -#define USART_BSEL1_bm (1<<1) /* Baud Rate Selection Bits [7:0] bit 1 mask. */ -#define USART_BSEL1_bp 1 /* Baud Rate Selection Bits [7:0] bit 1 position. */ -#define USART_BSEL2_bm (1<<2) /* Baud Rate Selection Bits [7:0] bit 2 mask. */ -#define USART_BSEL2_bp 2 /* Baud Rate Selection Bits [7:0] bit 2 position. */ -#define USART_BSEL3_bm (1<<3) /* Baud Rate Selection Bits [7:0] bit 3 mask. */ -#define USART_BSEL3_bp 3 /* Baud Rate Selection Bits [7:0] bit 3 position. */ -#define USART_BSEL4_bm (1<<4) /* Baud Rate Selection Bits [7:0] bit 4 mask. */ -#define USART_BSEL4_bp 4 /* Baud Rate Selection Bits [7:0] bit 4 position. */ -#define USART_BSEL5_bm (1<<5) /* Baud Rate Selection Bits [7:0] bit 5 mask. */ -#define USART_BSEL5_bp 5 /* Baud Rate Selection Bits [7:0] bit 5 position. */ -#define USART_BSEL6_bm (1<<6) /* Baud Rate Selection Bits [7:0] bit 6 mask. */ -#define USART_BSEL6_bp 6 /* Baud Rate Selection Bits [7:0] bit 6 position. */ -#define USART_BSEL7_bm (1<<7) /* Baud Rate Selection Bits [7:0] bit 7 mask. */ -#define USART_BSEL7_bp 7 /* Baud Rate Selection Bits [7:0] bit 7 position. */ - -/* USART.BAUDCTRLB bit masks and bit positions */ -#define USART_BSCALE_gm 0xF0 /* Baud Rate Scale group mask. */ -#define USART_BSCALE_gp 4 /* Baud Rate Scale group position. */ -#define USART_BSCALE0_bm (1<<4) /* Baud Rate Scale bit 0 mask. */ -#define USART_BSCALE0_bp 4 /* Baud Rate Scale bit 0 position. */ -#define USART_BSCALE1_bm (1<<5) /* Baud Rate Scale bit 1 mask. */ -#define USART_BSCALE1_bp 5 /* Baud Rate Scale bit 1 position. */ -#define USART_BSCALE2_bm (1<<6) /* Baud Rate Scale bit 2 mask. */ -#define USART_BSCALE2_bp 6 /* Baud Rate Scale bit 2 position. */ -#define USART_BSCALE3_bm (1<<7) /* Baud Rate Scale bit 3 mask. */ -#define USART_BSCALE3_bp 7 /* Baud Rate Scale bit 3 position. */ - -/* USART_BSEL Predefined. */ -/* USART_BSEL Predefined. */ - -/* SPI - Serial Peripheral Interface */ -/* SPI.CTRL bit masks and bit positions */ -#define SPI_CLK2X_bm 0x80 /* Enable Double Speed bit mask. */ -#define SPI_CLK2X_bp 7 /* Enable Double Speed bit position. */ - -#define SPI_ENABLE_bm 0x40 /* Enable Module bit mask. */ -#define SPI_ENABLE_bp 6 /* Enable Module bit position. */ - -#define SPI_DORD_bm 0x20 /* Data Order Setting bit mask. */ -#define SPI_DORD_bp 5 /* Data Order Setting bit position. */ - -#define SPI_MASTER_bm 0x10 /* Master Operation Enable bit mask. */ -#define SPI_MASTER_bp 4 /* Master Operation Enable bit position. */ - -#define SPI_MODE_gm 0x0C /* SPI Mode group mask. */ -#define SPI_MODE_gp 2 /* SPI Mode group position. */ -#define SPI_MODE0_bm (1<<2) /* SPI Mode bit 0 mask. */ -#define SPI_MODE0_bp 2 /* SPI Mode bit 0 position. */ -#define SPI_MODE1_bm (1<<3) /* SPI Mode bit 1 mask. */ -#define SPI_MODE1_bp 3 /* SPI Mode bit 1 position. */ - -#define SPI_PRESCALER_gm 0x03 /* Prescaler group mask. */ -#define SPI_PRESCALER_gp 0 /* Prescaler group position. */ -#define SPI_PRESCALER0_bm (1<<0) /* Prescaler bit 0 mask. */ -#define SPI_PRESCALER0_bp 0 /* Prescaler bit 0 position. */ -#define SPI_PRESCALER1_bm (1<<1) /* Prescaler bit 1 mask. */ -#define SPI_PRESCALER1_bp 1 /* Prescaler bit 1 position. */ - -/* SPI.INTCTRL bit masks and bit positions */ -#define SPI_INTLVL_gm 0x03 /* Interrupt level group mask. */ -#define SPI_INTLVL_gp 0 /* Interrupt level group position. */ -#define SPI_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */ -#define SPI_INTLVL0_bp 0 /* Interrupt level bit 0 position. */ -#define SPI_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */ -#define SPI_INTLVL1_bp 1 /* Interrupt level bit 1 position. */ - -/* SPI.STATUS bit masks and bit positions */ -#define SPI_IF_bm 0x80 /* Interrupt Flag bit mask. */ -#define SPI_IF_bp 7 /* Interrupt Flag bit position. */ - -#define SPI_WRCOL_bm 0x40 /* Write Collision bit mask. */ -#define SPI_WRCOL_bp 6 /* Write Collision bit position. */ - -/* IRCOM - IR Communication Module */ -/* IRCOM.CTRL bit masks and bit positions */ -#define IRCOM_EVSEL_gm 0x0F /* Event Channel Select group mask. */ -#define IRCOM_EVSEL_gp 0 /* Event Channel Select group position. */ -#define IRCOM_EVSEL0_bm (1<<0) /* Event Channel Select bit 0 mask. */ -#define IRCOM_EVSEL0_bp 0 /* Event Channel Select bit 0 position. */ -#define IRCOM_EVSEL1_bm (1<<1) /* Event Channel Select bit 1 mask. */ -#define IRCOM_EVSEL1_bp 1 /* Event Channel Select bit 1 position. */ -#define IRCOM_EVSEL2_bm (1<<2) /* Event Channel Select bit 2 mask. */ -#define IRCOM_EVSEL2_bp 2 /* Event Channel Select bit 2 position. */ -#define IRCOM_EVSEL3_bm (1<<3) /* Event Channel Select bit 3 mask. */ -#define IRCOM_EVSEL3_bp 3 /* Event Channel Select bit 3 position. */ - -/* FUSE - Fuses and Lockbits */ -/* NVM_FUSES.FUSEBYTE1 bit masks and bit positions */ -#define NVM_FUSES_WDWP_gm 0xF0 /* Watchdog Window Timeout Period group mask. */ -#define NVM_FUSES_WDWP_gp 4 /* Watchdog Window Timeout Period group position. */ -#define NVM_FUSES_WDWP0_bm (1<<4) /* Watchdog Window Timeout Period bit 0 mask. */ -#define NVM_FUSES_WDWP0_bp 4 /* Watchdog Window Timeout Period bit 0 position. */ -#define NVM_FUSES_WDWP1_bm (1<<5) /* Watchdog Window Timeout Period bit 1 mask. */ -#define NVM_FUSES_WDWP1_bp 5 /* Watchdog Window Timeout Period bit 1 position. */ -#define NVM_FUSES_WDWP2_bm (1<<6) /* Watchdog Window Timeout Period bit 2 mask. */ -#define NVM_FUSES_WDWP2_bp 6 /* Watchdog Window Timeout Period bit 2 position. */ -#define NVM_FUSES_WDWP3_bm (1<<7) /* Watchdog Window Timeout Period bit 3 mask. */ -#define NVM_FUSES_WDWP3_bp 7 /* Watchdog Window Timeout Period bit 3 position. */ - -#define NVM_FUSES_WDP_gm 0x0F /* Watchdog Timeout Period group mask. */ -#define NVM_FUSES_WDP_gp 0 /* Watchdog Timeout Period group position. */ -#define NVM_FUSES_WDP0_bm (1<<0) /* Watchdog Timeout Period bit 0 mask. */ -#define NVM_FUSES_WDP0_bp 0 /* Watchdog Timeout Period bit 0 position. */ -#define NVM_FUSES_WDP1_bm (1<<1) /* Watchdog Timeout Period bit 1 mask. */ -#define NVM_FUSES_WDP1_bp 1 /* Watchdog Timeout Period bit 1 position. */ -#define NVM_FUSES_WDP2_bm (1<<2) /* Watchdog Timeout Period bit 2 mask. */ -#define NVM_FUSES_WDP2_bp 2 /* Watchdog Timeout Period bit 2 position. */ -#define NVM_FUSES_WDP3_bm (1<<3) /* Watchdog Timeout Period bit 3 mask. */ -#define NVM_FUSES_WDP3_bp 3 /* Watchdog Timeout Period bit 3 position. */ - -/* NVM_FUSES.FUSEBYTE2 bit masks and bit positions */ -#define NVM_FUSES_BOOTRST_bm 0x40 /* Boot Loader Section Reset Vector bit mask. */ -#define NVM_FUSES_BOOTRST_bp 6 /* Boot Loader Section Reset Vector bit position. */ - -#define NVM_FUSES_TOSCSEL_bm 0x20 /* Timer Oscillator pin location bit mask. */ -#define NVM_FUSES_TOSCSEL_bp 5 /* Timer Oscillator pin location bit position. */ - -#define NVM_FUSES_BODPD_gm 0x03 /* BOD Operation in Power-Down Mode group mask. */ -#define NVM_FUSES_BODPD_gp 0 /* BOD Operation in Power-Down Mode group position. */ -#define NVM_FUSES_BODPD0_bm (1<<0) /* BOD Operation in Power-Down Mode bit 0 mask. */ -#define NVM_FUSES_BODPD0_bp 0 /* BOD Operation in Power-Down Mode bit 0 position. */ -#define NVM_FUSES_BODPD1_bm (1<<1) /* BOD Operation in Power-Down Mode bit 1 mask. */ -#define NVM_FUSES_BODPD1_bp 1 /* BOD Operation in Power-Down Mode bit 1 position. */ - -/* NVM_FUSES.FUSEBYTE4 bit masks and bit positions */ -#define NVM_FUSES_RSTDISBL_bm 0x10 /* External Reset Disable bit mask. */ -#define NVM_FUSES_RSTDISBL_bp 4 /* External Reset Disable bit position. */ - -#define NVM_FUSES_SUT_gm 0x0C /* Start-up Time group mask. */ -#define NVM_FUSES_SUT_gp 2 /* Start-up Time group position. */ -#define NVM_FUSES_SUT0_bm (1<<2) /* Start-up Time bit 0 mask. */ -#define NVM_FUSES_SUT0_bp 2 /* Start-up Time bit 0 position. */ -#define NVM_FUSES_SUT1_bm (1<<3) /* Start-up Time bit 1 mask. */ -#define NVM_FUSES_SUT1_bp 3 /* Start-up Time bit 1 position. */ - -#define NVM_FUSES_WDLOCK_bm 0x02 /* Watchdog Timer Lock bit mask. */ -#define NVM_FUSES_WDLOCK_bp 1 /* Watchdog Timer Lock bit position. */ - -/* NVM_FUSES.FUSEBYTE5 bit masks and bit positions */ -#define NVM_FUSES_BODACT_gm 0x30 /* BOD Operation in Active Mode group mask. */ -#define NVM_FUSES_BODACT_gp 4 /* BOD Operation in Active Mode group position. */ -#define NVM_FUSES_BODACT0_bm (1<<4) /* BOD Operation in Active Mode bit 0 mask. */ -#define NVM_FUSES_BODACT0_bp 4 /* BOD Operation in Active Mode bit 0 position. */ -#define NVM_FUSES_BODACT1_bm (1<<5) /* BOD Operation in Active Mode bit 1 mask. */ -#define NVM_FUSES_BODACT1_bp 5 /* BOD Operation in Active Mode bit 1 position. */ - -#define NVM_FUSES_EESAVE_bm 0x08 /* Preserve EEPROM Through Chip Erase bit mask. */ -#define NVM_FUSES_EESAVE_bp 3 /* Preserve EEPROM Through Chip Erase bit position. */ - -#define NVM_FUSES_BODLVL_gm 0x07 /* Brownout Detection Voltage Level group mask. */ -#define NVM_FUSES_BODLVL_gp 0 /* Brownout Detection Voltage Level group position. */ -#define NVM_FUSES_BODLVL0_bm (1<<0) /* Brownout Detection Voltage Level bit 0 mask. */ -#define NVM_FUSES_BODLVL0_bp 0 /* Brownout Detection Voltage Level bit 0 position. */ -#define NVM_FUSES_BODLVL1_bm (1<<1) /* Brownout Detection Voltage Level bit 1 mask. */ -#define NVM_FUSES_BODLVL1_bp 1 /* Brownout Detection Voltage Level bit 1 position. */ -#define NVM_FUSES_BODLVL2_bm (1<<2) /* Brownout Detection Voltage Level bit 2 mask. */ -#define NVM_FUSES_BODLVL2_bp 2 /* Brownout Detection Voltage Level bit 2 position. */ - -/* LOCKBIT - Fuses and Lockbits */ -/* NVM_LOCKBITS.LOCKBITS bit masks and bit positions */ -#define NVM_LOCKBITS_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ -#define NVM_LOCKBITS_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ -#define NVM_LOCKBITS_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ -#define NVM_LOCKBITS_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ -#define NVM_LOCKBITS_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ -#define NVM_LOCKBITS_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ - -#define NVM_LOCKBITS_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ -#define NVM_LOCKBITS_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ -#define NVM_LOCKBITS_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ -#define NVM_LOCKBITS_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ -#define NVM_LOCKBITS_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ -#define NVM_LOCKBITS_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ - -#define NVM_LOCKBITS_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ -#define NVM_LOCKBITS_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ -#define NVM_LOCKBITS_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ -#define NVM_LOCKBITS_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ -#define NVM_LOCKBITS_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ -#define NVM_LOCKBITS_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ - -#define NVM_LOCKBITS_LB_gm 0x03 /* Lock Bits group mask. */ -#define NVM_LOCKBITS_LB_gp 0 /* Lock Bits group position. */ -#define NVM_LOCKBITS_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ -#define NVM_LOCKBITS_LB0_bp 0 /* Lock Bits bit 0 position. */ -#define NVM_LOCKBITS_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ -#define NVM_LOCKBITS_LB1_bp 1 /* Lock Bits bit 1 position. */ - - - -// Generic Port Pins - -#define PIN0_bm 0x01 -#define PIN0_bp 0 -#define PIN1_bm 0x02 -#define PIN1_bp 1 -#define PIN2_bm 0x04 -#define PIN2_bp 2 -#define PIN3_bm 0x08 -#define PIN3_bp 3 -#define PIN4_bm 0x10 -#define PIN4_bp 4 -#define PIN5_bm 0x20 -#define PIN5_bp 5 -#define PIN6_bm 0x40 -#define PIN6_bp 6 -#define PIN7_bm 0x80 -#define PIN7_bp 7 - -/* ========== Interrupt Vector Definitions ========== */ -/* Vector 0 is the reset vector */ - -/* OSC interrupt vectors */ -#define OSC_OSCF_vect_num 1 -#define OSC_OSCF_vect _VECTOR(1) /* Oscillator Failure Interrupt (NMI) */ - -/* PORTC interrupt vectors */ -#define PORTC_INT0_vect_num 2 -#define PORTC_INT0_vect _VECTOR(2) /* External Interrupt 0 */ -#define PORTC_INT1_vect_num 3 -#define PORTC_INT1_vect _VECTOR(3) /* External Interrupt 1 */ - -/* PORTR interrupt vectors */ -#define PORTR_INT0_vect_num 4 -#define PORTR_INT0_vect _VECTOR(4) /* External Interrupt 0 */ -#define PORTR_INT1_vect_num 5 -#define PORTR_INT1_vect _VECTOR(5) /* External Interrupt 1 */ - -/* RTC interrupt vectors */ -#define RTC_OVF_vect_num 10 -#define RTC_OVF_vect _VECTOR(10) /* Overflow Interrupt */ -#define RTC_COMP_vect_num 11 -#define RTC_COMP_vect _VECTOR(11) /* Compare Interrupt */ - -/* TWIC interrupt vectors */ -#define TWIC_TWIS_vect_num 12 -#define TWIC_TWIS_vect _VECTOR(12) /* TWI Slave Interrupt */ -#define TWIC_TWIM_vect_num 13 -#define TWIC_TWIM_vect _VECTOR(13) /* TWI Master Interrupt */ - -/* TCC0 interrupt vectors */ -#define TCC0_OVF_vect_num 14 -#define TCC0_OVF_vect _VECTOR(14) /* Overflow Interrupt */ - -/* TCC2 interrupt vectors */ -#define TCC2_LUNF_vect_num 14 -#define TCC2_LUNF_vect _VECTOR(14) /* Low Byte Underflow Interrupt */ - -/* TCC0 interrupt vectors */ -#define TCC0_ERR_vect_num 15 -#define TCC0_ERR_vect _VECTOR(15) /* Error Interrupt */ - -/* TCC2 interrupt vectors */ -#define TCC2_HUNF_vect_num 15 -#define TCC2_HUNF_vect _VECTOR(15) /* High Byte Underflow Interrupt */ - -/* TCC0 interrupt vectors */ -#define TCC0_CCA_vect_num 16 -#define TCC0_CCA_vect _VECTOR(16) /* Compare or Capture A Interrupt */ - -/* TCC2 interrupt vectors */ -#define TCC2_LCMPA_vect_num 16 -#define TCC2_LCMPA_vect _VECTOR(16) /* Low Byte Compare A Interrupt */ - -/* TCC0 interrupt vectors */ -#define TCC0_CCB_vect_num 17 -#define TCC0_CCB_vect _VECTOR(17) /* Compare or Capture B Interrupt */ - -/* TCC2 interrupt vectors */ -#define TCC2_LCMPB_vect_num 17 -#define TCC2_LCMPB_vect _VECTOR(17) /* Low Byte Compare B Interrupt */ - -/* TCC0 interrupt vectors */ -#define TCC0_CCC_vect_num 18 -#define TCC0_CCC_vect _VECTOR(18) /* Compare or Capture C Interrupt */ - -/* TCC2 interrupt vectors */ -#define TCC2_LCMPC_vect_num 18 -#define TCC2_LCMPC_vect _VECTOR(18) /* Low Byte Compare C Interrupt */ - -/* TCC0 interrupt vectors */ -#define TCC0_CCD_vect_num 19 -#define TCC0_CCD_vect _VECTOR(19) /* Compare or Capture D Interrupt */ - -/* TCC2 interrupt vectors */ -#define TCC2_LCMPD_vect_num 19 -#define TCC2_LCMPD_vect _VECTOR(19) /* Low Byte Compare D Interrupt */ - -/* TCC1 interrupt vectors */ -#define TCC1_OVF_vect_num 20 -#define TCC1_OVF_vect _VECTOR(20) /* Overflow Interrupt */ -#define TCC1_ERR_vect_num 21 -#define TCC1_ERR_vect _VECTOR(21) /* Error Interrupt */ -#define TCC1_CCA_vect_num 22 -#define TCC1_CCA_vect _VECTOR(22) /* Compare or Capture A Interrupt */ -#define TCC1_CCB_vect_num 23 -#define TCC1_CCB_vect _VECTOR(23) /* Compare or Capture B Interrupt */ - -/* SPIC interrupt vectors */ -#define SPIC_INT_vect_num 24 -#define SPIC_INT_vect _VECTOR(24) /* SPI Interrupt */ - -/* USARTC0 interrupt vectors */ -#define USARTC0_RXC_vect_num 25 -#define USARTC0_RXC_vect _VECTOR(25) /* Reception Complete Interrupt */ -#define USARTC0_DRE_vect_num 26 -#define USARTC0_DRE_vect _VECTOR(26) /* Data Register Empty Interrupt */ -#define USARTC0_TXC_vect_num 27 -#define USARTC0_TXC_vect _VECTOR(27) /* Transmission Complete Interrupt */ - -/* NVM interrupt vectors */ -#define NVM_EE_vect_num 32 -#define NVM_EE_vect _VECTOR(32) /* EE Interrupt */ -#define NVM_SPM_vect_num 33 -#define NVM_SPM_vect _VECTOR(33) /* SPM Interrupt */ - -/* PORTB interrupt vectors */ -#define PORTB_INT0_vect_num 34 -#define PORTB_INT0_vect _VECTOR(34) /* External Interrupt 0 */ -#define PORTB_INT1_vect_num 35 -#define PORTB_INT1_vect _VECTOR(35) /* External Interrupt 1 */ - -/* PORTE interrupt vectors */ -#define PORTE_INT0_vect_num 43 -#define PORTE_INT0_vect _VECTOR(43) /* External Interrupt 0 */ -#define PORTE_INT1_vect_num 44 -#define PORTE_INT1_vect _VECTOR(44) /* External Interrupt 1 */ - -/* TWIE interrupt vectors */ -#define TWIE_TWIS_vect_num 45 -#define TWIE_TWIS_vect _VECTOR(45) /* TWI Slave Interrupt */ -#define TWIE_TWIM_vect_num 46 -#define TWIE_TWIM_vect _VECTOR(46) /* TWI Master Interrupt */ - -/* TCE0 interrupt vectors */ -#define TCE0_OVF_vect_num 47 -#define TCE0_OVF_vect _VECTOR(47) /* Overflow Interrupt */ - -/* TCE2 interrupt vectors */ -#define TCE2_LUNF_vect_num 47 -#define TCE2_LUNF_vect _VECTOR(47) /* Low Byte Underflow Interrupt */ - -/* TCE0 interrupt vectors */ -#define TCE0_ERR_vect_num 48 -#define TCE0_ERR_vect _VECTOR(48) /* Error Interrupt */ - -/* TCE2 interrupt vectors */ -#define TCE2_HUNF_vect_num 48 -#define TCE2_HUNF_vect _VECTOR(48) /* High Byte Underflow Interrupt */ - -/* TCE0 interrupt vectors */ -#define TCE0_CCA_vect_num 49 -#define TCE0_CCA_vect _VECTOR(49) /* Compare or Capture A Interrupt */ - -/* TCE2 interrupt vectors */ -#define TCE2_LCMPA_vect_num 49 -#define TCE2_LCMPA_vect _VECTOR(49) /* Low Byte Compare A Interrupt */ - -/* TCE0 interrupt vectors */ -#define TCE0_CCB_vect_num 50 -#define TCE0_CCB_vect _VECTOR(50) /* Compare or Capture B Interrupt */ - -/* TCE2 interrupt vectors */ -#define TCE2_LCMPB_vect_num 50 -#define TCE2_LCMPB_vect _VECTOR(50) /* Low Byte Compare B Interrupt */ - -/* TCE0 interrupt vectors */ -#define TCE0_CCC_vect_num 51 -#define TCE0_CCC_vect _VECTOR(51) /* Compare or Capture C Interrupt */ - -/* TCE2 interrupt vectors */ -#define TCE2_LCMPC_vect_num 51 -#define TCE2_LCMPC_vect _VECTOR(51) /* Low Byte Compare C Interrupt */ - -/* TCE0 interrupt vectors */ -#define TCE0_CCD_vect_num 52 -#define TCE0_CCD_vect _VECTOR(52) /* Compare or Capture D Interrupt */ - -/* TCE2 interrupt vectors */ -#define TCE2_LCMPD_vect_num 52 -#define TCE2_LCMPD_vect _VECTOR(52) /* Low Byte Compare D Interrupt */ - -/* USARTE0 interrupt vectors */ -#define USARTE0_RXC_vect_num 58 -#define USARTE0_RXC_vect _VECTOR(58) /* Reception Complete Interrupt */ -#define USARTE0_DRE_vect_num 59 -#define USARTE0_DRE_vect _VECTOR(59) /* Data Register Empty Interrupt */ -#define USARTE0_TXC_vect_num 60 -#define USARTE0_TXC_vect _VECTOR(60) /* Transmission Complete Interrupt */ - -/* PORTD interrupt vectors */ -#define PORTD_INT0_vect_num 64 -#define PORTD_INT0_vect _VECTOR(64) /* External Interrupt 0 */ -#define PORTD_INT1_vect_num 65 -#define PORTD_INT1_vect _VECTOR(65) /* External Interrupt 1 */ - -/* PORTA interrupt vectors */ -#define PORTA_INT0_vect_num 66 -#define PORTA_INT0_vect _VECTOR(66) /* External Interrupt 0 */ -#define PORTA_INT1_vect_num 67 -#define PORTA_INT1_vect _VECTOR(67) /* External Interrupt 1 */ - -/* ACA interrupt vectors */ -#define ACA_AC0_vect_num 68 -#define ACA_AC0_vect _VECTOR(68) /* AC0 Interrupt */ -#define ACA_AC1_vect_num 69 -#define ACA_AC1_vect _VECTOR(69) /* AC1 Interrupt */ -#define ACA_ACW_vect_num 70 -#define ACA_ACW_vect _VECTOR(70) /* ACW Window Mode Interrupt */ - -/* ADCA interrupt vectors */ -#define ADCA_CH0_vect_num 71 -#define ADCA_CH0_vect _VECTOR(71) /* Interrupt 0 */ - -/* TCD0 interrupt vectors */ -#define TCD0_OVF_vect_num 77 -#define TCD0_OVF_vect _VECTOR(77) /* Overflow Interrupt */ - -/* TCD2 interrupt vectors */ -#define TCD2_LUNF_vect_num 77 -#define TCD2_LUNF_vect _VECTOR(77) /* Low Byte Underflow Interrupt */ - -/* TCD0 interrupt vectors */ -#define TCD0_ERR_vect_num 78 -#define TCD0_ERR_vect _VECTOR(78) /* Error Interrupt */ - -/* TCD2 interrupt vectors */ -#define TCD2_HUNF_vect_num 78 -#define TCD2_HUNF_vect _VECTOR(78) /* High Byte Underflow Interrupt */ - -/* TCD0 interrupt vectors */ -#define TCD0_CCA_vect_num 79 -#define TCD0_CCA_vect _VECTOR(79) /* Compare or Capture A Interrupt */ - -/* TCD2 interrupt vectors */ -#define TCD2_LCMPA_vect_num 79 -#define TCD2_LCMPA_vect _VECTOR(79) /* Low Byte Compare A Interrupt */ - -/* TCD0 interrupt vectors */ -#define TCD0_CCB_vect_num 80 -#define TCD0_CCB_vect _VECTOR(80) /* Compare or Capture B Interrupt */ - -/* TCD2 interrupt vectors */ -#define TCD2_LCMPB_vect_num 80 -#define TCD2_LCMPB_vect _VECTOR(80) /* Low Byte Compare B Interrupt */ - -/* TCD0 interrupt vectors */ -#define TCD0_CCC_vect_num 81 -#define TCD0_CCC_vect _VECTOR(81) /* Compare or Capture C Interrupt */ - -/* TCD2 interrupt vectors */ -#define TCD2_LCMPC_vect_num 81 -#define TCD2_LCMPC_vect _VECTOR(81) /* Low Byte Compare C Interrupt */ - -/* TCD0 interrupt vectors */ -#define TCD0_CCD_vect_num 82 -#define TCD0_CCD_vect _VECTOR(82) /* Compare or Capture D Interrupt */ - -/* TCD2 interrupt vectors */ -#define TCD2_LCMPD_vect_num 82 -#define TCD2_LCMPD_vect _VECTOR(82) /* Low Byte Compare D Interrupt */ - -/* SPID interrupt vectors */ -#define SPID_INT_vect_num 87 -#define SPID_INT_vect _VECTOR(87) /* SPI Interrupt */ - -/* USARTD0 interrupt vectors */ -#define USARTD0_RXC_vect_num 88 -#define USARTD0_RXC_vect _VECTOR(88) /* Reception Complete Interrupt */ -#define USARTD0_DRE_vect_num 89 -#define USARTD0_DRE_vect _VECTOR(89) /* Data Register Empty Interrupt */ -#define USARTD0_TXC_vect_num 90 -#define USARTD0_TXC_vect _VECTOR(90) /* Transmission Complete Interrupt */ - -/* PORTF interrupt vectors */ -#define PORTF_INT0_vect_num 104 -#define PORTF_INT0_vect _VECTOR(104) /* External Interrupt 0 */ -#define PORTF_INT1_vect_num 105 -#define PORTF_INT1_vect _VECTOR(105) /* External Interrupt 1 */ - -/* TCF0 interrupt vectors */ -#define TCF0_OVF_vect_num 108 -#define TCF0_OVF_vect _VECTOR(108) /* Overflow Interrupt */ - -/* TCF2 interrupt vectors */ -#define TCF2_LUNF_vect_num 108 -#define TCF2_LUNF_vect _VECTOR(108) /* Low Byte Underflow Interrupt */ - -/* TCF0 interrupt vectors */ -#define TCF0_ERR_vect_num 109 -#define TCF0_ERR_vect _VECTOR(109) /* Error Interrupt */ - -/* TCF2 interrupt vectors */ -#define TCF2_HUNF_vect_num 109 -#define TCF2_HUNF_vect _VECTOR(109) /* High Byte Underflow Interrupt */ - -/* TCF0 interrupt vectors */ -#define TCF0_CCA_vect_num 110 -#define TCF0_CCA_vect _VECTOR(110) /* Compare or Capture A Interrupt */ - -/* TCF2 interrupt vectors */ -#define TCF2_LCMPA_vect_num 110 -#define TCF2_LCMPA_vect _VECTOR(110) /* Low Byte Compare A Interrupt */ - -/* TCF0 interrupt vectors */ -#define TCF0_CCB_vect_num 111 -#define TCF0_CCB_vect _VECTOR(111) /* Compare or Capture B Interrupt */ - -/* TCF2 interrupt vectors */ -#define TCF2_LCMPB_vect_num 111 -#define TCF2_LCMPB_vect _VECTOR(111) /* Low Byte Compare B Interrupt */ - -/* TCF0 interrupt vectors */ -#define TCF0_CCC_vect_num 112 -#define TCF0_CCC_vect _VECTOR(112) /* Compare or Capture C Interrupt */ - -/* TCF2 interrupt vectors */ -#define TCF2_LCMPC_vect_num 112 -#define TCF2_LCMPC_vect _VECTOR(112) /* Low Byte Compare C Interrupt */ - -/* TCF0 interrupt vectors */ -#define TCF0_CCD_vect_num 113 -#define TCF0_CCD_vect _VECTOR(113) /* Compare or Capture D Interrupt */ - -/* TCF2 interrupt vectors */ -#define TCF2_LCMPD_vect_num 113 -#define TCF2_LCMPD_vect _VECTOR(113) /* Low Byte Compare D Interrupt */ - -/* USB interrupt vectors */ -#define USB_BUSEVENT_vect_num 125 -#define USB_BUSEVENT_vect _VECTOR(125) /* SOF, suspend, resume, reset bus event interrupts, crc, underflow, overflow and stall error interrupts */ -#define USB_TRNCOMPL_vect_num 126 -#define USB_TRNCOMPL_vect _VECTOR(126) /* Transaction complete interrupt */ - -#define _VECTOR_SIZE 4 /* Size of individual vector. */ -#define _VECTORS_SIZE (127 * _VECTOR_SIZE) - - -/* ========== Constants ========== */ - -#define PROGMEM_START (0x0000) -#define PROGMEM_SIZE (36864) -#define PROGMEM_END (PROGMEM_START + PROGMEM_SIZE - 1) - -#define APP_SECTION_START (0x0000) -#define APP_SECTION_SIZE (32768) -#define APP_SECTION_PAGE_SIZE (256) -#define APP_SECTION_END (APP_SECTION_START + APP_SECTION_SIZE - 1) - -#define APPTABLE_SECTION_START (0x7000) -#define APPTABLE_SECTION_SIZE (4096) -#define APPTABLE_SECTION_PAGE_SIZE (256) -#define APPTABLE_SECTION_END (APPTABLE_SECTION_START + APPTABLE_SECTION_SIZE - 1) - -#define BOOT_SECTION_START (0x8000) -#define BOOT_SECTION_SIZE (4096) -#define BOOT_SECTION_PAGE_SIZE (256) -#define BOOT_SECTION_END (BOOT_SECTION_START + BOOT_SECTION_SIZE - 1) - -#define DATAMEM_START (0x0000) -#define DATAMEM_SIZE (12288) -#define DATAMEM_END (DATAMEM_START + DATAMEM_SIZE - 1) - -#define IO_START (0x0000) -#define IO_SIZE (4096) -#define IO_PAGE_SIZE (0) -#define IO_END (IO_START + IO_SIZE - 1) - -#define MAPPED_EEPROM_START (0x1000) -#define MAPPED_EEPROM_SIZE (1024) -#define MAPPED_EEPROM_PAGE_SIZE (0) -#define MAPPED_EEPROM_END (MAPPED_EEPROM_START + MAPPED_EEPROM_SIZE - 1) - -#define INTERNAL_SRAM_START (0x2000) -#define INTERNAL_SRAM_SIZE (4096) -#define INTERNAL_SRAM_PAGE_SIZE (0) -#define INTERNAL_SRAM_END (INTERNAL_SRAM_START + INTERNAL_SRAM_SIZE - 1) - -#define EEPROM_START (0x0000) -#define EEPROM_SIZE (1024) -#define EEPROM_PAGE_SIZE (32) -#define EEPROM_END (EEPROM_START + EEPROM_SIZE - 1) - -#define SIGNATURES_START (0x0000) -#define SIGNATURES_SIZE (3) -#define SIGNATURES_PAGE_SIZE (0) -#define SIGNATURES_END (SIGNATURES_START + SIGNATURES_SIZE - 1) - -#define FUSES_START (0x0000) -#define FUSES_SIZE (6) -#define FUSES_PAGE_SIZE (0) -#define FUSES_END (FUSES_START + FUSES_SIZE - 1) - -#define LOCKBITS_START (0x0000) -#define LOCKBITS_SIZE (1) -#define LOCKBITS_PAGE_SIZE (0) -#define LOCKBITS_END (LOCKBITS_START + LOCKBITS_SIZE - 1) - -#define USER_SIGNATURES_START (0x0000) -#define USER_SIGNATURES_SIZE (256) -#define USER_SIGNATURES_PAGE_SIZE (256) -#define USER_SIGNATURES_END (USER_SIGNATURES_START + USER_SIGNATURES_SIZE - 1) - -#define PROD_SIGNATURES_START (0x0000) -#define PROD_SIGNATURES_SIZE (64) -#define PROD_SIGNATURES_PAGE_SIZE (256) -#define PROD_SIGNATURES_END (PROD_SIGNATURES_START + PROD_SIGNATURES_SIZE - 1) - -#define FLASHSTART PROGMEM_START -#define FLASHEND PROGMEM_END -#define SPM_PAGESIZE 256 -#define RAMSTART INTERNAL_SRAM_START -#define RAMSIZE INTERNAL_SRAM_SIZE -#define RAMEND INTERNAL_SRAM_END -#define E2END EEPROM_END -#define E2PAGESIZE EEPROM_PAGE_SIZE - - -/* ========== Fuses ========== */ -#define FUSE_MEMORY_SIZE 6 - -/* Fuse Byte 0 Reserved */ - -/* Fuse Byte 1 */ -#define FUSE_WDP0 (unsigned char)~_BV(0) /* Watchdog Timeout Period Bit 0 */ -#define FUSE_WDP1 (unsigned char)~_BV(1) /* Watchdog Timeout Period Bit 1 */ -#define FUSE_WDP2 (unsigned char)~_BV(2) /* Watchdog Timeout Period Bit 2 */ -#define FUSE_WDP3 (unsigned char)~_BV(3) /* Watchdog Timeout Period Bit 3 */ -#define FUSE_WDWP0 (unsigned char)~_BV(4) /* Watchdog Window Timeout Period Bit 0 */ -#define FUSE_WDWP1 (unsigned char)~_BV(5) /* Watchdog Window Timeout Period Bit 1 */ -#define FUSE_WDWP2 (unsigned char)~_BV(6) /* Watchdog Window Timeout Period Bit 2 */ -#define FUSE_WDWP3 (unsigned char)~_BV(7) /* Watchdog Window Timeout Period Bit 3 */ -#define FUSE1_DEFAULT (0xFF) - -/* Fuse Byte 2 */ -#define FUSE_BODPD0 (unsigned char)~_BV(0) /* BOD Operation in Power-Down Mode Bit 0 */ -#define FUSE_BODPD1 (unsigned char)~_BV(1) /* BOD Operation in Power-Down Mode Bit 1 */ -#define FUSE_TOSCSEL (unsigned char)~_BV(5) /* Timer Oscillator pin location */ -#define FUSE_BOOTRST (unsigned char)~_BV(6) /* Boot Loader Section Reset Vector */ -#define FUSE2_DEFAULT (0xFF) - -/* Fuse Byte 3 Reserved */ - -/* Fuse Byte 4 */ -#define FUSE_WDLOCK (unsigned char)~_BV(1) /* Watchdog Timer Lock */ -#define FUSE_SUT0 (unsigned char)~_BV(2) /* Start-up Time Bit 0 */ -#define FUSE_SUT1 (unsigned char)~_BV(3) /* Start-up Time Bit 1 */ -#define FUSE_RSTDISBL (unsigned char)~_BV(4) /* External Reset Disable */ -#define FUSE4_DEFAULT (0xFF) - -/* Fuse Byte 5 */ -#define FUSE_BODLVL0 (unsigned char)~_BV(0) /* Brownout Detection Voltage Level Bit 0 */ -#define FUSE_BODLVL1 (unsigned char)~_BV(1) /* Brownout Detection Voltage Level Bit 1 */ -#define FUSE_BODLVL2 (unsigned char)~_BV(2) /* Brownout Detection Voltage Level Bit 2 */ -#define FUSE_EESAVE (unsigned char)~_BV(3) /* Preserve EEPROM Through Chip Erase */ -#define FUSE_BODACT0 (unsigned char)~_BV(4) /* BOD Operation in Active Mode Bit 0 */ -#define FUSE_BODACT1 (unsigned char)~_BV(5) /* BOD Operation in Active Mode Bit 1 */ -#define FUSE5_DEFAULT (0xFF) - -/* ========== Lock Bits ========== */ -#define __LOCK_BITS_EXIST -#define __BOOT_LOCK_APPLICATION_TABLE_BITS_EXIST -#define __BOOT_LOCK_APPLICATION_BITS_EXIST -#define __BOOT_LOCK_BOOT_BITS_EXIST - -/* ========== Signature ========== */ -#define SIGNATURE_0 0x1E -#define SIGNATURE_1 0x95 -#define SIGNATURE_2 0x49 - -/* ========== Power Reduction Condition Definitions ========== */ - -/* PR.PRGEN */ -#define __AVR_HAVE_PRGEN (PR_USB_bm|PR_AES_bm|PR_RTC_bm|PR_EVSYS_bm|PR_DMA_bm) -#define __AVR_HAVE_PRGEN_USB -#define __AVR_HAVE_PRGEN_AES -#define __AVR_HAVE_PRGEN_RTC -#define __AVR_HAVE_PRGEN_EVSYS -#define __AVR_HAVE_PRGEN_DMA - -/* PR.PRPA */ -#define __AVR_HAVE_PRPA (PR_ADC_bm|PR_AC_bm) -#define __AVR_HAVE_PRPA_ADC -#define __AVR_HAVE_PRPA_AC - -/* PR.PRPC */ -#define __AVR_HAVE_PRPC (PR_TWI_bm|PR_USART1_bm|PR_USART0_bm|PR_SPI_bm|PR_HIRES_bm|PR_TC1_bm|PR_TC0_bm) -#define __AVR_HAVE_PRPC_TWI -#define __AVR_HAVE_PRPC_USART1 -#define __AVR_HAVE_PRPC_USART0 -#define __AVR_HAVE_PRPC_SPI -#define __AVR_HAVE_PRPC_HIRES -#define __AVR_HAVE_PRPC_TC1 -#define __AVR_HAVE_PRPC_TC0 - -/* PR.PRPD */ -#define __AVR_HAVE_PRPD (PR_USART0_bm|PR_SPI_bm|PR_TC0_bm) -#define __AVR_HAVE_PRPD_USART0 -#define __AVR_HAVE_PRPD_SPI -#define __AVR_HAVE_PRPD_TC0 - -/* PR.PRPE */ -#define __AVR_HAVE_PRPE (PR_TWI_bm|PR_USART0_bm|PR_TC0_bm) -#define __AVR_HAVE_PRPE_TWI -#define __AVR_HAVE_PRPE_USART0 -#define __AVR_HAVE_PRPE_TC0 - -/* PR.PRPF */ -#define __AVR_HAVE_PRPF (PR_USART0_bm|PR_TC0_bm) -#define __AVR_HAVE_PRPF_USART0 -#define __AVR_HAVE_PRPF_TC0 - - -#endif /* #ifdef _AVR_ATXMEGA32C3_H_INCLUDED */ - diff --git a/arduino/hardware/tools/avr/avr/include/avr/iox32c4.h b/arduino/hardware/tools/avr/avr/include/avr/iox32c4.h deleted file mode 100644 index 28a15b3..0000000 --- a/arduino/hardware/tools/avr/avr/include/avr/iox32c4.h +++ /dev/null @@ -1,6078 +0,0 @@ -/***************************************************************************** - * - * Copyright (C) 2015 Atmel Corporation - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * - * * Neither the name of the copyright holders nor the names of - * contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - ****************************************************************************/ - - -#ifndef _AVR_IO_H_ -# error "Include instead of this file." -#endif - -#ifndef _AVR_IOXXX_H_ -# define _AVR_IOXXX_H_ "iox32c4.h" -#else -# error "Attempt to include more than one file." -#endif - -#ifndef _AVR_ATXMEGA32C4_H_INCLUDED -#define _AVR_ATXMEGA32C4_H_INCLUDED - -/* Ungrouped common registers */ -#define GPIOR0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ -#define GPIOR1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ -#define GPIOR2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ -#define GPIOR3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ - -/* Deprecated */ -#define GPIO0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ -#define GPIO1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ -#define GPIO2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ -#define GPIO3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ - -#define CCP _SFR_MEM8(0x0034) /* Configuration Change Protection */ -#define RAMPD _SFR_MEM8(0x0038) /* Ramp D */ -#define RAMPX _SFR_MEM8(0x0039) /* Ramp X */ -#define RAMPY _SFR_MEM8(0x003A) /* Ramp Y */ -#define RAMPZ _SFR_MEM8(0x003B) /* Ramp Z */ -#define EIND _SFR_MEM8(0x003C) /* Extended Indirect Jump */ -#define SPL _SFR_MEM8(0x003D) /* Stack Pointer Low */ -#define SPH _SFR_MEM8(0x003E) /* Stack Pointer High */ -#define SREG _SFR_MEM8(0x003F) /* Status Register */ - -/* C Language Only */ -#if !defined (__ASSEMBLER__) - -#include - -typedef volatile uint8_t register8_t; -typedef volatile uint16_t register16_t; -typedef volatile uint32_t register32_t; - - -#ifdef _WORDREGISTER -#undef _WORDREGISTER -#endif -#define _WORDREGISTER(regname) \ - __extension__ union \ - { \ - register16_t regname; \ - struct \ - { \ - register8_t regname ## L; \ - register8_t regname ## H; \ - }; \ - } - -#ifdef _DWORDREGISTER -#undef _DWORDREGISTER -#endif -#define _DWORDREGISTER(regname) \ - __extension__ union \ - { \ - register32_t regname; \ - struct \ - { \ - register8_t regname ## 0; \ - register8_t regname ## 1; \ - register8_t regname ## 2; \ - register8_t regname ## 3; \ - }; \ - } - - -/* -========================================================================== -IO Module Structures -========================================================================== -*/ - - -/* --------------------------------------------------------------------------- -VPORT - Virtual Ports --------------------------------------------------------------------------- -*/ - -/* Virtual Port */ -typedef struct VPORT_struct -{ - register8_t DIR; /* I/O Port Data Direction */ - register8_t OUT; /* I/O Port Output */ - register8_t IN; /* I/O Port Input */ - register8_t INTFLAGS; /* Interrupt Flag Register */ -} VPORT_t; - - -/* --------------------------------------------------------------------------- -XOCD - On-Chip Debug System --------------------------------------------------------------------------- -*/ - -/* On-Chip Debug System */ -typedef struct OCD_struct -{ - register8_t OCDR0; /* OCD Register 0 */ - register8_t OCDR1; /* OCD Register 1 */ -} OCD_t; - - -/* --------------------------------------------------------------------------- -CPU - CPU --------------------------------------------------------------------------- -*/ - -/* CCP signatures */ -typedef enum CCP_enum -{ - CCP_SPM_gc = (0x9D<<0), /* SPM Instruction Protection */ - CCP_IOREG_gc = (0xD8<<0), /* IO Register Protection */ -} CCP_t; - - -/* --------------------------------------------------------------------------- -CLK - Clock System --------------------------------------------------------------------------- -*/ - -/* Clock System */ -typedef struct CLK_struct -{ - register8_t CTRL; /* Control Register */ - register8_t PSCTRL; /* Prescaler Control Register */ - register8_t LOCK; /* Lock register */ - register8_t RTCCTRL; /* RTC Control Register */ - register8_t USBCTRL; /* USB Control Register */ -} CLK_t; - - -/* Power Reduction */ -typedef struct PR_struct -{ - register8_t PRGEN; /* General Power Reduction */ - register8_t PRPA; /* Power Reduction Port A */ - register8_t reserved_0x02; - register8_t PRPC; /* Power Reduction Port C */ - register8_t PRPD; /* Power Reduction Port D */ - register8_t PRPE; /* Power Reduction Port E */ - register8_t PRPF; /* Power Reduction Port F */ -} PR_t; - -/* System Clock Selection */ -typedef enum CLK_SCLKSEL_enum -{ - CLK_SCLKSEL_RC2M_gc = (0x00<<0), /* Internal 2 MHz RC Oscillator */ - CLK_SCLKSEL_RC32M_gc = (0x01<<0), /* Internal 32 MHz RC Oscillator */ - CLK_SCLKSEL_RC32K_gc = (0x02<<0), /* Internal 32.768 kHz RC Oscillator */ - CLK_SCLKSEL_XOSC_gc = (0x03<<0), /* External Crystal Oscillator or Clock */ - CLK_SCLKSEL_PLL_gc = (0x04<<0), /* Phase Locked Loop */ -} CLK_SCLKSEL_t; - -/* Prescaler A Division Factor */ -typedef enum CLK_PSADIV_enum -{ - CLK_PSADIV_1_gc = (0x00<<2), /* Divide by 1 */ - CLK_PSADIV_2_gc = (0x01<<2), /* Divide by 2 */ - CLK_PSADIV_4_gc = (0x03<<2), /* Divide by 4 */ - CLK_PSADIV_8_gc = (0x05<<2), /* Divide by 8 */ - CLK_PSADIV_16_gc = (0x07<<2), /* Divide by 16 */ - CLK_PSADIV_32_gc = (0x09<<2), /* Divide by 32 */ - CLK_PSADIV_64_gc = (0x0B<<2), /* Divide by 64 */ - CLK_PSADIV_128_gc = (0x0D<<2), /* Divide by 128 */ - CLK_PSADIV_256_gc = (0x0F<<2), /* Divide by 256 */ - CLK_PSADIV_512_gc = (0x11<<2), /* Divide by 512 */ -} CLK_PSADIV_t; - -/* Prescaler B and C Division Factor */ -typedef enum CLK_PSBCDIV_enum -{ - CLK_PSBCDIV_1_1_gc = (0x00<<0), /* Divide B by 1 and C by 1 */ - CLK_PSBCDIV_1_2_gc = (0x01<<0), /* Divide B by 1 and C by 2 */ - CLK_PSBCDIV_4_1_gc = (0x02<<0), /* Divide B by 4 and C by 1 */ - CLK_PSBCDIV_2_2_gc = (0x03<<0), /* Divide B by 2 and C by 2 */ -} CLK_PSBCDIV_t; - -/* RTC Clock Source */ -typedef enum CLK_RTCSRC_enum -{ - CLK_RTCSRC_ULP_gc = (0x00<<1), /* 1.024 kHz from internal 32kHz ULP */ - CLK_RTCSRC_TOSC_gc = (0x01<<1), /* 1.024 kHz from 32.768 kHz crystal oscillator on TOSC */ - CLK_RTCSRC_RCOSC_gc = (0x02<<1), /* 1.024 kHz from internal 32.768 kHz RC oscillator */ - CLK_RTCSRC_TOSC32_gc = (0x05<<1), /* 32.768 kHz from 32.768 kHz crystal oscillator on TOSC */ - CLK_RTCSRC_RCOSC32_gc = (0x06<<1), /* 32.768 kHz from internal 32.768 kHz RC oscillator */ - CLK_RTCSRC_EXTCLK_gc = (0x07<<1), /* External Clock from TOSC1 */ -} CLK_RTCSRC_t; - -/* USB Prescaler Division Factor */ -typedef enum CLK_USBPSDIV_enum -{ - CLK_USBPSDIV_1_gc = (0x00<<3), /* Divide by 1 */ - CLK_USBPSDIV_2_gc = (0x01<<3), /* Divide by 2 */ - CLK_USBPSDIV_4_gc = (0x02<<3), /* Divide by 4 */ - CLK_USBPSDIV_8_gc = (0x03<<3), /* Divide by 8 */ - CLK_USBPSDIV_16_gc = (0x04<<3), /* Divide by 16 */ - CLK_USBPSDIV_32_gc = (0x05<<3), /* Divide by 32 */ -} CLK_USBPSDIV_t; - -/* USB Clock Source */ -typedef enum CLK_USBSRC_enum -{ - CLK_USBSRC_PLL_gc = (0x00<<1), /* PLL */ - CLK_USBSRC_RC32M_gc = (0x01<<1), /* Internal 32 MHz RC Oscillator */ -} CLK_USBSRC_t; - - -/* --------------------------------------------------------------------------- -SLEEP - Sleep Controller --------------------------------------------------------------------------- -*/ - -/* Sleep Controller */ -typedef struct SLEEP_struct -{ - register8_t CTRL; /* Control Register */ -} SLEEP_t; - -/* Sleep Mode */ -typedef enum SLEEP_SMODE_enum -{ - SLEEP_SMODE_IDLE_gc = (0x00<<1), /* Idle mode */ - SLEEP_SMODE_PDOWN_gc = (0x02<<1), /* Power-down Mode */ - SLEEP_SMODE_PSAVE_gc = (0x03<<1), /* Power-save Mode */ - SLEEP_SMODE_STDBY_gc = (0x06<<1), /* Standby Mode */ - SLEEP_SMODE_ESTDBY_gc = (0x07<<1), /* Extended Standby Mode */ -} SLEEP_SMODE_t; - - - -#define SLEEP_MODE_IDLE (0x00<<1) -#define SLEEP_MODE_PWR_DOWN (0x02<<1) -#define SLEEP_MODE_PWR_SAVE (0x03<<1) -#define SLEEP_MODE_STANDBY (0x06<<1) -#define SLEEP_MODE_EXT_STANDBY (0x07<<1) -/* --------------------------------------------------------------------------- -OSC - Oscillator --------------------------------------------------------------------------- -*/ - -/* Oscillator */ -typedef struct OSC_struct -{ - register8_t CTRL; /* Control Register */ - register8_t STATUS; /* Status Register */ - register8_t XOSCCTRL; /* External Oscillator Control Register */ - register8_t XOSCFAIL; /* Oscillator Failure Detection Register */ - register8_t RC32KCAL; /* 32.768 kHz Internal Oscillator Calibration Register */ - register8_t PLLCTRL; /* PLL Control Register */ - register8_t DFLLCTRL; /* DFLL Control Register */ -} OSC_t; - -/* Oscillator Frequency Range */ -typedef enum OSC_FRQRANGE_enum -{ - OSC_FRQRANGE_04TO2_gc = (0x00<<6), /* 0.4 - 2 MHz */ - OSC_FRQRANGE_2TO9_gc = (0x01<<6), /* 2 - 9 MHz */ - OSC_FRQRANGE_9TO12_gc = (0x02<<6), /* 9 - 12 MHz */ - OSC_FRQRANGE_12TO16_gc = (0x03<<6), /* 12 - 16 MHz */ -} OSC_FRQRANGE_t; - -/* External Oscillator Selection and Startup Time */ -typedef enum OSC_XOSCSEL_enum -{ - OSC_XOSCSEL_EXTCLK_gc = (0x00<<0), /* External Clock - 6 CLK */ - OSC_XOSCSEL_32KHz_gc = (0x02<<0), /* 32.768 kHz TOSC - 32K CLK */ - OSC_XOSCSEL_XTAL_256CLK_gc = (0x03<<0), /* 0.4-16 MHz XTAL - 256 CLK */ - OSC_XOSCSEL_XTAL_1KCLK_gc = (0x07<<0), /* 0.4-16 MHz XTAL - 1K CLK */ - OSC_XOSCSEL_XTAL_16KCLK_gc = (0x0B<<0), /* 0.4-16 MHz XTAL - 16K CLK */ -} OSC_XOSCSEL_t; - -/* PLL Clock Source */ -typedef enum OSC_PLLSRC_enum -{ - OSC_PLLSRC_RC2M_gc = (0x00<<6), /* Internal 2 MHz RC Oscillator */ - OSC_PLLSRC_RC32M_gc = (0x02<<6), /* Internal 32 MHz RC Oscillator */ - OSC_PLLSRC_XOSC_gc = (0x03<<6), /* External Oscillator */ -} OSC_PLLSRC_t; - -/* 2 MHz DFLL Calibration Reference */ -typedef enum OSC_RC2MCREF_enum -{ - OSC_RC2MCREF_RC32K_gc = (0x00<<0), /* Internal 32.768 kHz RC Oscillator */ - OSC_RC2MCREF_XOSC32K_gc = (0x01<<0), /* External 32.768 kHz Crystal Oscillator */ -} OSC_RC2MCREF_t; - -/* 32 MHz DFLL Calibration Reference */ -typedef enum OSC_RC32MCREF_enum -{ - OSC_RC32MCREF_RC32K_gc = (0x00<<1), /* Internal 32.768 kHz RC Oscillator */ - OSC_RC32MCREF_XOSC32K_gc = (0x01<<1), /* External 32.768 kHz Crystal Oscillator */ - OSC_RC32MCREF_USBSOF_gc = (0x02<<1), /* USB Start of Frame */ -} OSC_RC32MCREF_t; - - -/* --------------------------------------------------------------------------- -DFLL - DFLL --------------------------------------------------------------------------- -*/ - -/* DFLL */ -typedef struct DFLL_struct -{ - register8_t CTRL; /* Control Register */ - register8_t reserved_0x01; - register8_t CALA; /* Calibration Register A */ - register8_t CALB; /* Calibration Register B */ - register8_t COMP0; /* Oscillator Compare Register 0 */ - register8_t COMP1; /* Oscillator Compare Register 1 */ - register8_t COMP2; /* Oscillator Compare Register 2 */ - register8_t reserved_0x07; -} DFLL_t; - - -/* --------------------------------------------------------------------------- -RST - Reset --------------------------------------------------------------------------- -*/ - -/* Reset */ -typedef struct RST_struct -{ - register8_t STATUS; /* Status Register */ - register8_t CTRL; /* Control Register */ -} RST_t; - - -/* --------------------------------------------------------------------------- -WDT - Watch-Dog Timer --------------------------------------------------------------------------- -*/ - -/* Watch-Dog Timer */ -typedef struct WDT_struct -{ - register8_t CTRL; /* Control */ - register8_t WINCTRL; /* Windowed Mode Control */ - register8_t STATUS; /* Status */ -} WDT_t; - -/* Period setting */ -typedef enum WDT_PER_enum -{ - WDT_PER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ - WDT_PER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ - WDT_PER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ - WDT_PER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ - WDT_PER_128CLK_gc = (0x04<<2), /* 128 cycles (0.128s @ 3.3V) */ - WDT_PER_256CLK_gc = (0x05<<2), /* 256 cycles (0.256s @ 3.3V) */ - WDT_PER_512CLK_gc = (0x06<<2), /* 512 cycles (0.512s @ 3.3V) */ - WDT_PER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ - WDT_PER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ - WDT_PER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ - WDT_PER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ -} WDT_PER_t; - -/* Closed window period */ -typedef enum WDT_WPER_enum -{ - WDT_WPER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ - WDT_WPER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ - WDT_WPER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ - WDT_WPER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ - WDT_WPER_128CLK_gc = (0x04<<2), /* 128 cycles (0.128s @ 3.3V) */ - WDT_WPER_256CLK_gc = (0x05<<2), /* 256 cycles (0.256s @ 3.3V) */ - WDT_WPER_512CLK_gc = (0x06<<2), /* 512 cycles (0.512s @ 3.3V) */ - WDT_WPER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ - WDT_WPER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ - WDT_WPER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ - WDT_WPER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ -} WDT_WPER_t; - - -/* --------------------------------------------------------------------------- -MCU - MCU Control --------------------------------------------------------------------------- -*/ - -/* MCU Control */ -typedef struct MCU_struct -{ - register8_t DEVID0; /* Device ID byte 0 */ - register8_t DEVID1; /* Device ID byte 1 */ - register8_t DEVID2; /* Device ID byte 2 */ - register8_t REVID; /* Revision ID */ - register8_t reserved_0x04; - register8_t reserved_0x05; - register8_t reserved_0x06; - register8_t ANAINIT; /* Analog Startup Delay */ - register8_t EVSYSLOCK; /* Event System Lock */ - register8_t AWEXLOCK; /* AWEX Lock */ - register8_t reserved_0x0A; - register8_t reserved_0x0B; -} MCU_t; - - -/* --------------------------------------------------------------------------- -PMIC - Programmable Multi-level Interrupt Controller --------------------------------------------------------------------------- -*/ - -/* Programmable Multi-level Interrupt Controller */ -typedef struct PMIC_struct -{ - register8_t STATUS; /* Status Register */ - register8_t INTPRI; /* Interrupt Priority */ - register8_t CTRL; /* Control Register */ - register8_t reserved_0x03; - register8_t reserved_0x04; - register8_t reserved_0x05; - register8_t reserved_0x06; - register8_t reserved_0x07; - register8_t reserved_0x08; - register8_t reserved_0x09; - register8_t reserved_0x0A; - register8_t reserved_0x0B; - register8_t reserved_0x0C; - register8_t reserved_0x0D; - register8_t reserved_0x0E; - register8_t reserved_0x0F; -} PMIC_t; - - -/* --------------------------------------------------------------------------- -PORTCFG - Port Configuration --------------------------------------------------------------------------- -*/ - -/* I/O port Configuration */ -typedef struct PORTCFG_struct -{ - register8_t MPCMASK; /* Multi-pin Configuration Mask */ - register8_t reserved_0x01; - register8_t VPCTRLA; /* Virtual Port Control Register A */ - register8_t VPCTRLB; /* Virtual Port Control Register B */ - register8_t CLKEVOUT; /* Clock and Event Out Register */ - register8_t reserved_0x05; - register8_t EVOUTSEL; /* Event Output Select */ -} PORTCFG_t; - -/* Virtual Port Mapping */ -typedef enum PORTCFG_VP02MAP_enum -{ - PORTCFG_VP02MAP_PORTA_gc = (0x00<<0), /* Mapped To PORTA */ - PORTCFG_VP02MAP_PORTB_gc = (0x01<<0), /* Mapped To PORTB */ - PORTCFG_VP02MAP_PORTC_gc = (0x02<<0), /* Mapped To PORTC */ - PORTCFG_VP02MAP_PORTD_gc = (0x03<<0), /* Mapped To PORTD */ - PORTCFG_VP02MAP_PORTE_gc = (0x04<<0), /* Mapped To PORTE */ - PORTCFG_VP02MAP_PORTF_gc = (0x05<<0), /* Mapped To PORTF */ - PORTCFG_VP02MAP_PORTG_gc = (0x06<<0), /* Mapped To PORTG */ - PORTCFG_VP02MAP_PORTH_gc = (0x07<<0), /* Mapped To PORTH */ - PORTCFG_VP02MAP_PORTJ_gc = (0x08<<0), /* Mapped To PORTJ */ - PORTCFG_VP02MAP_PORTK_gc = (0x09<<0), /* Mapped To PORTK */ - PORTCFG_VP02MAP_PORTL_gc = (0x0A<<0), /* Mapped To PORTL */ - PORTCFG_VP02MAP_PORTM_gc = (0x0B<<0), /* Mapped To PORTM */ - PORTCFG_VP02MAP_PORTN_gc = (0x0C<<0), /* Mapped To PORTN */ - PORTCFG_VP02MAP_PORTP_gc = (0x0D<<0), /* Mapped To PORTP */ - PORTCFG_VP02MAP_PORTQ_gc = (0x0E<<0), /* Mapped To PORTQ */ - PORTCFG_VP02MAP_PORTR_gc = (0x0F<<0), /* Mapped To PORTR */ -} PORTCFG_VP02MAP_t; - -/* Virtual Port Mapping */ -typedef enum PORTCFG_VP13MAP_enum -{ - PORTCFG_VP13MAP_PORTA_gc = (0x00<<4), /* Mapped To PORTA */ - PORTCFG_VP13MAP_PORTB_gc = (0x01<<4), /* Mapped To PORTB */ - PORTCFG_VP13MAP_PORTC_gc = (0x02<<4), /* Mapped To PORTC */ - PORTCFG_VP13MAP_PORTD_gc = (0x03<<4), /* Mapped To PORTD */ - PORTCFG_VP13MAP_PORTE_gc = (0x04<<4), /* Mapped To PORTE */ - PORTCFG_VP13MAP_PORTF_gc = (0x05<<4), /* Mapped To PORTF */ - PORTCFG_VP13MAP_PORTG_gc = (0x06<<4), /* Mapped To PORTG */ - PORTCFG_VP13MAP_PORTH_gc = (0x07<<4), /* Mapped To PORTH */ - PORTCFG_VP13MAP_PORTJ_gc = (0x08<<4), /* Mapped To PORTJ */ - PORTCFG_VP13MAP_PORTK_gc = (0x09<<4), /* Mapped To PORTK */ - PORTCFG_VP13MAP_PORTL_gc = (0x0A<<4), /* Mapped To PORTL */ - PORTCFG_VP13MAP_PORTM_gc = (0x0B<<4), /* Mapped To PORTM */ - PORTCFG_VP13MAP_PORTN_gc = (0x0C<<4), /* Mapped To PORTN */ - PORTCFG_VP13MAP_PORTP_gc = (0x0D<<4), /* Mapped To PORTP */ - PORTCFG_VP13MAP_PORTQ_gc = (0x0E<<4), /* Mapped To PORTQ */ - PORTCFG_VP13MAP_PORTR_gc = (0x0F<<4), /* Mapped To PORTR */ -} PORTCFG_VP13MAP_t; - -/* System Clock Output Port */ -typedef enum PORTCFG_CLKOUT_enum -{ - PORTCFG_CLKOUT_OFF_gc = (0x00<<0), /* System Clock Output Disabled */ - PORTCFG_CLKOUT_PC7_gc = (0x01<<0), /* System Clock Output on Port C pin 7 */ - PORTCFG_CLKOUT_PD7_gc = (0x02<<0), /* System Clock Output on Port D pin 7 */ - PORTCFG_CLKOUT_PE7_gc = (0x03<<0), /* System Clock Output on Port E pin 7 */ -} PORTCFG_CLKOUT_t; - -/* Peripheral Clock Output Select */ -typedef enum PORTCFG_CLKOUTSEL_enum -{ - PORTCFG_CLKOUTSEL_CLK1X_gc = (0x00<<2), /* 1x Peripheral Clock Output to pin */ - PORTCFG_CLKOUTSEL_CLK2X_gc = (0x01<<2), /* 2x Peripheral Clock Output to pin */ - PORTCFG_CLKOUTSEL_CLK4X_gc = (0x02<<2), /* 4x Peripheral Clock Output to pin */ -} PORTCFG_CLKOUTSEL_t; - -/* Event Output Port */ -typedef enum PORTCFG_EVOUT_enum -{ - PORTCFG_EVOUT_OFF_gc = (0x00<<4), /* Event Output Disabled */ - PORTCFG_EVOUT_PC7_gc = (0x01<<4), /* Event Channel 7 Output on Port C pin 7 */ - PORTCFG_EVOUT_PD7_gc = (0x02<<4), /* Event Channel 7 Output on Port D pin 7 */ - PORTCFG_EVOUT_PE7_gc = (0x03<<4), /* Event Channel 7 Output on Port E pin 7 */ -} PORTCFG_EVOUT_t; - -/* Event Output Select */ -typedef enum PORTCFG_EVOUTSEL_enum -{ - PORTCFG_EVOUTSEL_0_gc = (0x00<<0), /* Event Channel 0 output to pin */ - PORTCFG_EVOUTSEL_1_gc = (0x01<<0), /* Event Channel 1 output to pin */ - PORTCFG_EVOUTSEL_2_gc = (0x02<<0), /* Event Channel 2 output to pin */ - PORTCFG_EVOUTSEL_3_gc = (0x03<<0), /* Event Channel 3 output to pin */ -} PORTCFG_EVOUTSEL_t; - - -/* --------------------------------------------------------------------------- -CRC - Cyclic Redundancy Checker --------------------------------------------------------------------------- -*/ - -/* Cyclic Redundancy Checker */ -typedef struct CRC_struct -{ - register8_t CTRL; /* Control Register */ - register8_t STATUS; /* Status Register */ - register8_t reserved_0x02; - register8_t DATAIN; /* Data Input */ - register8_t CHECKSUM0; /* Checksum byte 0 */ - register8_t CHECKSUM1; /* Checksum byte 1 */ - register8_t CHECKSUM2; /* Checksum byte 2 */ - register8_t CHECKSUM3; /* Checksum byte 3 */ -} CRC_t; - -/* Reset */ -typedef enum CRC_RESET_enum -{ - CRC_RESET_NO_gc = (0x00<<6), /* No Reset */ - CRC_RESET_RESET0_gc = (0x02<<6), /* Reset CRC with CHECKSUM to all zeros */ - CRC_RESET_RESET1_gc = (0x03<<6), /* Reset CRC with CHECKSUM to all ones */ -} CRC_RESET_t; - -/* Input Source */ -typedef enum CRC_SOURCE_enum -{ - CRC_SOURCE_DISABLE_gc = (0x00<<0), /* Disabled */ - CRC_SOURCE_IO_gc = (0x01<<0), /* I/O Interface */ - CRC_SOURCE_FLASH_gc = (0x02<<0), /* Flash */ -} CRC_SOURCE_t; - - -/* --------------------------------------------------------------------------- -EVSYS - Event System --------------------------------------------------------------------------- -*/ - -/* Event System */ -typedef struct EVSYS_struct -{ - register8_t CH0MUX; /* Event Channel 0 Multiplexer */ - register8_t CH1MUX; /* Event Channel 1 Multiplexer */ - register8_t CH2MUX; /* Event Channel 2 Multiplexer */ - register8_t CH3MUX; /* Event Channel 3 Multiplexer */ - register8_t reserved_0x04; - register8_t reserved_0x05; - register8_t reserved_0x06; - register8_t reserved_0x07; - register8_t CH0CTRL; /* Channel 0 Control Register */ - register8_t CH1CTRL; /* Channel 1 Control Register */ - register8_t CH2CTRL; /* Channel 2 Control Register */ - register8_t CH3CTRL; /* Channel 3 Control Register */ - register8_t reserved_0x0C; - register8_t reserved_0x0D; - register8_t reserved_0x0E; - register8_t reserved_0x0F; - register8_t STROBE; /* Event Strobe */ - register8_t DATA; /* Event Data */ -} EVSYS_t; - -/* Quadrature Decoder Index Recognition Mode */ -typedef enum EVSYS_QDIRM_enum -{ - EVSYS_QDIRM_00_gc = (0x00<<5), /* QDPH0 = 0, QDPH90 = 0 */ - EVSYS_QDIRM_01_gc = (0x01<<5), /* QDPH0 = 0, QDPH90 = 1 */ - EVSYS_QDIRM_10_gc = (0x02<<5), /* QDPH0 = 1, QDPH90 = 0 */ - EVSYS_QDIRM_11_gc = (0x03<<5), /* QDPH0 = 1, QDPH90 = 1 */ -} EVSYS_QDIRM_t; - -/* Digital filter coefficient */ -typedef enum EVSYS_DIGFILT_enum -{ - EVSYS_DIGFILT_1SAMPLE_gc = (0x00<<0), /* 1 SAMPLE */ - EVSYS_DIGFILT_2SAMPLES_gc = (0x01<<0), /* 2 SAMPLES */ - EVSYS_DIGFILT_3SAMPLES_gc = (0x02<<0), /* 3 SAMPLES */ - EVSYS_DIGFILT_4SAMPLES_gc = (0x03<<0), /* 4 SAMPLES */ - EVSYS_DIGFILT_5SAMPLES_gc = (0x04<<0), /* 5 SAMPLES */ - EVSYS_DIGFILT_6SAMPLES_gc = (0x05<<0), /* 6 SAMPLES */ - EVSYS_DIGFILT_7SAMPLES_gc = (0x06<<0), /* 7 SAMPLES */ - EVSYS_DIGFILT_8SAMPLES_gc = (0x07<<0), /* 8 SAMPLES */ -} EVSYS_DIGFILT_t; - -/* Event Channel multiplexer input selection */ -typedef enum EVSYS_CHMUX_enum -{ - EVSYS_CHMUX_OFF_gc = (0x00<<0), /* Off */ - EVSYS_CHMUX_RTC_OVF_gc = (0x08<<0), /* RTC Overflow */ - EVSYS_CHMUX_RTC_CMP_gc = (0x09<<0), /* RTC Compare Match */ - EVSYS_CHMUX_USB_gc = (0x0A<<0), /* USB Setup, SOF, CRC error and UNF/OVF */ - EVSYS_CHMUX_ACA_CH0_gc = (0x10<<0), /* Analog Comparator A Channel 0 */ - EVSYS_CHMUX_ACA_CH1_gc = (0x11<<0), /* Analog Comparator A Channel 1 */ - EVSYS_CHMUX_ACA_WIN_gc = (0x12<<0), /* Analog Comparator A Window */ - EVSYS_CHMUX_ADCA_CH0_gc = (0x20<<0), /* ADC A Channel */ - EVSYS_CHMUX_PORTA_PIN0_gc = (0x50<<0), /* Port A, Pin0 */ - EVSYS_CHMUX_PORTA_PIN1_gc = (0x51<<0), /* Port A, Pin1 */ - EVSYS_CHMUX_PORTA_PIN2_gc = (0x52<<0), /* Port A, Pin2 */ - EVSYS_CHMUX_PORTA_PIN3_gc = (0x53<<0), /* Port A, Pin3 */ - EVSYS_CHMUX_PORTA_PIN4_gc = (0x54<<0), /* Port A, Pin4 */ - EVSYS_CHMUX_PORTA_PIN5_gc = (0x55<<0), /* Port A, Pin5 */ - EVSYS_CHMUX_PORTA_PIN6_gc = (0x56<<0), /* Port A, Pin6 */ - EVSYS_CHMUX_PORTA_PIN7_gc = (0x57<<0), /* Port A, Pin7 */ - EVSYS_CHMUX_PORTB_PIN0_gc = (0x58<<0), /* Port B, Pin0 */ - EVSYS_CHMUX_PORTB_PIN1_gc = (0x59<<0), /* Port B, Pin1 */ - EVSYS_CHMUX_PORTB_PIN2_gc = (0x5A<<0), /* Port B, Pin2 */ - EVSYS_CHMUX_PORTB_PIN3_gc = (0x5B<<0), /* Port B, Pin3 */ - EVSYS_CHMUX_PORTB_PIN4_gc = (0x5C<<0), /* Port B, Pin4 */ - EVSYS_CHMUX_PORTB_PIN5_gc = (0x5D<<0), /* Port B, Pin5 */ - EVSYS_CHMUX_PORTB_PIN6_gc = (0x5E<<0), /* Port B, Pin6 */ - EVSYS_CHMUX_PORTB_PIN7_gc = (0x5F<<0), /* Port B, Pin7 */ - EVSYS_CHMUX_PORTC_PIN0_gc = (0x60<<0), /* Port C, Pin0 */ - EVSYS_CHMUX_PORTC_PIN1_gc = (0x61<<0), /* Port C, Pin1 */ - EVSYS_CHMUX_PORTC_PIN2_gc = (0x62<<0), /* Port C, Pin2 */ - EVSYS_CHMUX_PORTC_PIN3_gc = (0x63<<0), /* Port C, Pin3 */ - EVSYS_CHMUX_PORTC_PIN4_gc = (0x64<<0), /* Port C, Pin4 */ - EVSYS_CHMUX_PORTC_PIN5_gc = (0x65<<0), /* Port C, Pin5 */ - EVSYS_CHMUX_PORTC_PIN6_gc = (0x66<<0), /* Port C, Pin6 */ - EVSYS_CHMUX_PORTC_PIN7_gc = (0x67<<0), /* Port C, Pin7 */ - EVSYS_CHMUX_PORTD_PIN0_gc = (0x68<<0), /* Port D, Pin0 */ - EVSYS_CHMUX_PORTD_PIN1_gc = (0x69<<0), /* Port D, Pin1 */ - EVSYS_CHMUX_PORTD_PIN2_gc = (0x6A<<0), /* Port D, Pin2 */ - EVSYS_CHMUX_PORTD_PIN3_gc = (0x6B<<0), /* Port D, Pin3 */ - EVSYS_CHMUX_PORTD_PIN4_gc = (0x6C<<0), /* Port D, Pin4 */ - EVSYS_CHMUX_PORTD_PIN5_gc = (0x6D<<0), /* Port D, Pin5 */ - EVSYS_CHMUX_PORTD_PIN6_gc = (0x6E<<0), /* Port D, Pin6 */ - EVSYS_CHMUX_PORTD_PIN7_gc = (0x6F<<0), /* Port D, Pin7 */ - EVSYS_CHMUX_PORTE_PIN0_gc = (0x70<<0), /* Port E, Pin0 */ - EVSYS_CHMUX_PORTE_PIN1_gc = (0x71<<0), /* Port E, Pin1 */ - EVSYS_CHMUX_PORTE_PIN2_gc = (0x72<<0), /* Port E, Pin2 */ - EVSYS_CHMUX_PORTE_PIN3_gc = (0x73<<0), /* Port E, Pin3 */ - EVSYS_CHMUX_PORTE_PIN4_gc = (0x74<<0), /* Port E, Pin4 */ - EVSYS_CHMUX_PORTE_PIN5_gc = (0x75<<0), /* Port E, Pin5 */ - EVSYS_CHMUX_PORTE_PIN6_gc = (0x76<<0), /* Port E, Pin6 */ - EVSYS_CHMUX_PORTE_PIN7_gc = (0x77<<0), /* Port E, Pin7 */ - EVSYS_CHMUX_PORTF_PIN0_gc = (0x78<<0), /* Port F, Pin0 */ - EVSYS_CHMUX_PORTF_PIN1_gc = (0x79<<0), /* Port F, Pin1 */ - EVSYS_CHMUX_PORTF_PIN2_gc = (0x7A<<0), /* Port F, Pin2 */ - EVSYS_CHMUX_PORTF_PIN3_gc = (0x7B<<0), /* Port F, Pin3 */ - EVSYS_CHMUX_PORTF_PIN4_gc = (0x7C<<0), /* Port F, Pin4 */ - EVSYS_CHMUX_PORTF_PIN5_gc = (0x7D<<0), /* Port F, Pin5 */ - EVSYS_CHMUX_PORTF_PIN6_gc = (0x7E<<0), /* Port F, Pin6 */ - EVSYS_CHMUX_PORTF_PIN7_gc = (0x7F<<0), /* Port F, Pin7 */ - EVSYS_CHMUX_PRESCALER_1_gc = (0x80<<0), /* Prescaler, divide by 1 */ - EVSYS_CHMUX_PRESCALER_2_gc = (0x81<<0), /* Prescaler, divide by 2 */ - EVSYS_CHMUX_PRESCALER_4_gc = (0x82<<0), /* Prescaler, divide by 4 */ - EVSYS_CHMUX_PRESCALER_8_gc = (0x83<<0), /* Prescaler, divide by 8 */ - EVSYS_CHMUX_PRESCALER_16_gc = (0x84<<0), /* Prescaler, divide by 16 */ - EVSYS_CHMUX_PRESCALER_32_gc = (0x85<<0), /* Prescaler, divide by 32 */ - EVSYS_CHMUX_PRESCALER_64_gc = (0x86<<0), /* Prescaler, divide by 64 */ - EVSYS_CHMUX_PRESCALER_128_gc = (0x87<<0), /* Prescaler, divide by 128 */ - EVSYS_CHMUX_PRESCALER_256_gc = (0x88<<0), /* Prescaler, divide by 256 */ - EVSYS_CHMUX_PRESCALER_512_gc = (0x89<<0), /* Prescaler, divide by 512 */ - EVSYS_CHMUX_PRESCALER_1024_gc = (0x8A<<0), /* Prescaler, divide by 1024 */ - EVSYS_CHMUX_PRESCALER_2048_gc = (0x8B<<0), /* Prescaler, divide by 2048 */ - EVSYS_CHMUX_PRESCALER_4096_gc = (0x8C<<0), /* Prescaler, divide by 4096 */ - EVSYS_CHMUX_PRESCALER_8192_gc = (0x8D<<0), /* Prescaler, divide by 8192 */ - EVSYS_CHMUX_PRESCALER_16384_gc = (0x8E<<0), /* Prescaler, divide by 16384 */ - EVSYS_CHMUX_PRESCALER_32768_gc = (0x8F<<0), /* Prescaler, divide by 32768 */ - EVSYS_CHMUX_TCC0_OVF_gc = (0xC0<<0), /* Timer/Counter C0 Overflow */ - EVSYS_CHMUX_TCC0_ERR_gc = (0xC1<<0), /* Timer/Counter C0 Error */ - EVSYS_CHMUX_TCC0_CCA_gc = (0xC4<<0), /* Timer/Counter C0 Compare or Capture A */ - EVSYS_CHMUX_TCC0_CCB_gc = (0xC5<<0), /* Timer/Counter C0 Compare or Capture B */ - EVSYS_CHMUX_TCC0_CCC_gc = (0xC6<<0), /* Timer/Counter C0 Compare or Capture C */ - EVSYS_CHMUX_TCC0_CCD_gc = (0xC7<<0), /* Timer/Counter C0 Compare or Capture D */ - EVSYS_CHMUX_TCC1_OVF_gc = (0xC8<<0), /* Timer/Counter C1 Overflow */ - EVSYS_CHMUX_TCC1_ERR_gc = (0xC9<<0), /* Timer/Counter C1 Error */ - EVSYS_CHMUX_TCC1_CCA_gc = (0xCC<<0), /* Timer/Counter C1 Compare or Capture A */ - EVSYS_CHMUX_TCC1_CCB_gc = (0xCD<<0), /* Timer/Counter C1 Compare or Capture B */ - EVSYS_CHMUX_TCD0_OVF_gc = (0xD0<<0), /* Timer/Counter D0 Overflow */ - EVSYS_CHMUX_TCD0_ERR_gc = (0xD1<<0), /* Timer/Counter D0 Error */ - EVSYS_CHMUX_TCD0_CCA_gc = (0xD4<<0), /* Timer/Counter D0 Compare or Capture A */ - EVSYS_CHMUX_TCD0_CCB_gc = (0xD5<<0), /* Timer/Counter D0 Compare or Capture B */ - EVSYS_CHMUX_TCD0_CCC_gc = (0xD6<<0), /* Timer/Counter D0 Compare or Capture C */ - EVSYS_CHMUX_TCD0_CCD_gc = (0xD7<<0), /* Timer/Counter D0 Compare or Capture D */ - EVSYS_CHMUX_TCE0_OVF_gc = (0xE0<<0), /* Timer/Counter E0 Overflow */ - EVSYS_CHMUX_TCE0_ERR_gc = (0xE1<<0), /* Timer/Counter E0 Error */ - EVSYS_CHMUX_TCE0_CCA_gc = (0xE4<<0), /* Timer/Counter E0 Compare or Capture A */ - EVSYS_CHMUX_TCE0_CCB_gc = (0xE5<<0), /* Timer/Counter E0 Compare or Capture B */ - EVSYS_CHMUX_TCE0_CCC_gc = (0xE6<<0), /* Timer/Counter E0 Compare or Capture C */ - EVSYS_CHMUX_TCE0_CCD_gc = (0xE7<<0), /* Timer/Counter E0 Compare or Capture D */ - EVSYS_CHMUX_TCF0_OVF_gc = (0xF0<<0), /* Timer/Counter F0 Overflow */ - EVSYS_CHMUX_TCF0_ERR_gc = (0xF1<<0), /* Timer/Counter F0 Error */ - EVSYS_CHMUX_TCF0_CCA_gc = (0xF4<<0), /* Timer/Counter F0 Compare or Capture A */ - EVSYS_CHMUX_TCF0_CCB_gc = (0xF5<<0), /* Timer/Counter F0 Compare or Capture B */ - EVSYS_CHMUX_TCF0_CCC_gc = (0xF6<<0), /* Timer/Counter F0 Compare or Capture C */ - EVSYS_CHMUX_TCF0_CCD_gc = (0xF7<<0), /* Timer/Counter F0 Compare or Capture D */ -} EVSYS_CHMUX_t; - - -/* --------------------------------------------------------------------------- -NVM - Non Volatile Memory Controller --------------------------------------------------------------------------- -*/ - -/* Non-volatile Memory Controller */ -typedef struct NVM_struct -{ - register8_t ADDR0; /* Address Register 0 */ - register8_t ADDR1; /* Address Register 1 */ - register8_t ADDR2; /* Address Register 2 */ - register8_t reserved_0x03; - register8_t DATA0; /* Data Register 0 */ - register8_t DATA1; /* Data Register 1 */ - register8_t DATA2; /* Data Register 2 */ - register8_t reserved_0x07; - register8_t reserved_0x08; - register8_t reserved_0x09; - register8_t CMD; /* Command */ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t INTCTRL; /* Interrupt Control */ - register8_t reserved_0x0E; - register8_t STATUS; /* Status */ - register8_t LOCK_BITS; /* Lock Bits (Changed from LOCKBITS to avoid avr-libc collision) */ -} NVM_t; - -/* NVM Command */ -typedef enum NVM_CMD_enum -{ - NVM_CMD_NO_OPERATION_gc = (0x00<<0), /* Noop/Ordinary LPM */ - NVM_CMD_READ_USER_SIG_ROW_gc = (0x01<<0), /* Read user signature row */ - NVM_CMD_READ_CALIB_ROW_gc = (0x02<<0), /* Read calibration row */ - NVM_CMD_READ_EEPROM_gc = (0x06<<0), /* Read EEPROM */ - NVM_CMD_READ_FUSES_gc = (0x07<<0), /* Read fuse byte */ - NVM_CMD_WRITE_LOCK_BITS_gc = (0x08<<0), /* Write lock bits */ - NVM_CMD_ERASE_USER_SIG_ROW_gc = (0x18<<0), /* Erase user signature row */ - NVM_CMD_WRITE_USER_SIG_ROW_gc = (0x1A<<0), /* Write user signature row */ - NVM_CMD_ERASE_APP_gc = (0x20<<0), /* Erase Application Section */ - NVM_CMD_ERASE_APP_PAGE_gc = (0x22<<0), /* Erase Application Section page */ - NVM_CMD_LOAD_FLASH_BUFFER_gc = (0x23<<0), /* Load Flash page buffer */ - NVM_CMD_WRITE_APP_PAGE_gc = (0x24<<0), /* Write Application Section page */ - NVM_CMD_ERASE_WRITE_APP_PAGE_gc = (0x25<<0), /* Erase-and-write Application Section page */ - NVM_CMD_ERASE_FLASH_BUFFER_gc = (0x26<<0), /* Erase/flush Flash page buffer */ - NVM_CMD_ERASE_BOOT_PAGE_gc = (0x2A<<0), /* Erase Boot Section page */ - NVM_CMD_ERASE_FLASH_PAGE_gc = (0x2B<<0), /* Erase Flash Page */ - NVM_CMD_WRITE_BOOT_PAGE_gc = (0x2C<<0), /* Write Boot Section page */ - NVM_CMD_ERASE_WRITE_BOOT_PAGE_gc = (0x2D<<0), /* Erase-and-write Boot Section page */ - NVM_CMD_WRITE_FLASH_PAGE_gc = (0x2E<<0), /* Write Flash Page */ - NVM_CMD_ERASE_WRITE_FLASH_PAGE_gc = (0x2F<<0), /* Erase-and-write Flash Page */ - NVM_CMD_ERASE_EEPROM_gc = (0x30<<0), /* Erase EEPROM */ - NVM_CMD_ERASE_EEPROM_PAGE_gc = (0x32<<0), /* Erase EEPROM page */ - NVM_CMD_LOAD_EEPROM_BUFFER_gc = (0x33<<0), /* Load EEPROM page buffer */ - NVM_CMD_WRITE_EEPROM_PAGE_gc = (0x34<<0), /* Write EEPROM page */ - NVM_CMD_ERASE_WRITE_EEPROM_PAGE_gc = (0x35<<0), /* Erase-and-write EEPROM page */ - NVM_CMD_ERASE_EEPROM_BUFFER_gc = (0x36<<0), /* Erase/flush EEPROM page buffer */ - NVM_CMD_APP_CRC_gc = (0x38<<0), /* Application section CRC */ - NVM_CMD_BOOT_CRC_gc = (0x39<<0), /* Boot Section CRC */ - NVM_CMD_FLASH_RANGE_CRC_gc = (0x3A<<0), /* Flash Range CRC */ - NVM_CMD_CHIP_ERASE_gc = (0x40<<0), /* Erase Chip */ - NVM_CMD_READ_NVM_gc = (0x43<<0), /* Read NVM */ - NVM_CMD_WRITE_FUSE_gc = (0x4C<<0), /* Write Fuse byte */ - NVM_CMD_ERASE_BOOT_gc = (0x68<<0), /* Erase Boot Section */ - NVM_CMD_FLASH_CRC_gc = (0x78<<0), /* Flash CRC */ -} NVM_CMD_t; - -/* SPM ready interrupt level */ -typedef enum NVM_SPMLVL_enum -{ - NVM_SPMLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ - NVM_SPMLVL_LO_gc = (0x01<<2), /* Low level */ - NVM_SPMLVL_MED_gc = (0x02<<2), /* Medium level */ - NVM_SPMLVL_HI_gc = (0x03<<2), /* High level */ -} NVM_SPMLVL_t; - -/* EEPROM ready interrupt level */ -typedef enum NVM_EELVL_enum -{ - NVM_EELVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ - NVM_EELVL_LO_gc = (0x01<<0), /* Low level */ - NVM_EELVL_MED_gc = (0x02<<0), /* Medium level */ - NVM_EELVL_HI_gc = (0x03<<0), /* High level */ -} NVM_EELVL_t; - -/* Boot lock bits - boot setcion */ -typedef enum NVM_BLBB_enum -{ - NVM_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ - NVM_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ - NVM_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ - NVM_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ -} NVM_BLBB_t; - -/* Boot lock bits - application section */ -typedef enum NVM_BLBA_enum -{ - NVM_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ - NVM_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ - NVM_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ - NVM_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ -} NVM_BLBA_t; - -/* Boot lock bits - application table section */ -typedef enum NVM_BLBAT_enum -{ - NVM_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ - NVM_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ - NVM_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ - NVM_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ -} NVM_BLBAT_t; - -/* Lock bits */ -typedef enum NVM_LB_enum -{ - NVM_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ - NVM_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ - NVM_LB_NOLOCK_gc = (0x03<<0), /* No locks */ -} NVM_LB_t; - - -/* --------------------------------------------------------------------------- -ADC - Analog/Digital Converter --------------------------------------------------------------------------- -*/ - -/* ADC Channel */ -typedef struct ADC_CH_struct -{ - register8_t CTRL; /* Control Register */ - register8_t MUXCTRL; /* MUX Control */ - register8_t INTCTRL; /* Channel Interrupt Control Register */ - register8_t INTFLAGS; /* Interrupt Flags */ - _WORDREGISTER(RES); /* Channel Result */ - register8_t SCAN; /* Input Channel Scan */ - register8_t reserved_0x07; -} ADC_CH_t; - - -/* Analog-to-Digital Converter */ -typedef struct ADC_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t REFCTRL; /* Reference Control */ - register8_t EVCTRL; /* Event Control */ - register8_t PRESCALER; /* Clock Prescaler */ - register8_t reserved_0x05; - register8_t INTFLAGS; /* Interrupt Flags */ - register8_t TEMP; /* Temporary Register */ - register8_t reserved_0x08; - register8_t reserved_0x09; - register8_t reserved_0x0A; - register8_t reserved_0x0B; - _WORDREGISTER(CAL); /* Calibration Value */ - register8_t reserved_0x0E; - register8_t reserved_0x0F; - _WORDREGISTER(CH0RES); /* Channel 0 Result */ - register8_t reserved_0x12; - register8_t reserved_0x13; - register8_t reserved_0x14; - register8_t reserved_0x15; - register8_t reserved_0x16; - register8_t reserved_0x17; - _WORDREGISTER(CMP); /* Compare Value */ - register8_t reserved_0x1A; - register8_t reserved_0x1B; - register8_t reserved_0x1C; - register8_t reserved_0x1D; - register8_t reserved_0x1E; - register8_t reserved_0x1F; - ADC_CH_t CH0; /* ADC Channel 0 */ -} ADC_t; - -/* Current Limitation */ -typedef enum ADC_CURRLIMIT_enum -{ - ADC_CURRLIMIT_NO_gc = (0x00<<5), /* No current limit, 300ksps max sampling rate */ - ADC_CURRLIMIT_LOW_gc = (0x01<<5), /* Low current limit, 250ksps max sampling rate */ - ADC_CURRLIMIT_MED_gc = (0x02<<5), /* Medium current limit, 150ksps max sampling rate */ - ADC_CURRLIMIT_HIGH_gc = (0x03<<5), /* High current limit, 50ksps max sampling rate */ -} ADC_CURRLIMIT_t; - -/* Positive input multiplexer selection */ -typedef enum ADC_CH_MUXPOS_enum -{ - ADC_CH_MUXPOS_PIN0_gc = (0x00<<3), /* Input pin 0 */ - ADC_CH_MUXPOS_PIN1_gc = (0x01<<3), /* Input pin 1 */ - ADC_CH_MUXPOS_PIN2_gc = (0x02<<3), /* Input pin 2 */ - ADC_CH_MUXPOS_PIN3_gc = (0x03<<3), /* Input pin 3 */ - ADC_CH_MUXPOS_PIN4_gc = (0x04<<3), /* Input pin 4 */ - ADC_CH_MUXPOS_PIN5_gc = (0x05<<3), /* Input pin 5 */ - ADC_CH_MUXPOS_PIN6_gc = (0x06<<3), /* Input pin 6 */ - ADC_CH_MUXPOS_PIN7_gc = (0x07<<3), /* Input pin 7 */ - ADC_CH_MUXPOS_PIN8_gc = (0x08<<3), /* Input pin 8 */ - ADC_CH_MUXPOS_PIN9_gc = (0x09<<3), /* Input pin 9 */ - ADC_CH_MUXPOS_PIN10_gc = (0x0A<<3), /* Input pin 10 */ - ADC_CH_MUXPOS_PIN11_gc = (0x0B<<3), /* Input pin 11 */ - ADC_CH_MUXPOS_PIN12_gc = (0x0C<<3), /* Input pin 12 */ - ADC_CH_MUXPOS_PIN13_gc = (0x0D<<3), /* Input pin 13 */ - ADC_CH_MUXPOS_PIN14_gc = (0x0E<<3), /* Input pin 14 */ - ADC_CH_MUXPOS_PIN15_gc = (0x0F<<3), /* Input pin 15 */ -} ADC_CH_MUXPOS_t; - -/* Internal input multiplexer selections */ -typedef enum ADC_CH_MUXINT_enum -{ - ADC_CH_MUXINT_TEMP_gc = (0x00<<3), /* Temperature Reference */ - ADC_CH_MUXINT_BANDGAP_gc = (0x01<<3), /* Bandgap Reference */ - ADC_CH_MUXINT_SCALEDVCC_gc = (0x02<<3), /* 1/10 scaled VCC */ -} ADC_CH_MUXINT_t; - -/* Negative input multiplexer selection */ -typedef enum ADC_CH_MUXNEG_enum -{ - ADC_CH_MUXNEG_PIN0_gc = (0x00<<0), /* Input pin 0 */ - ADC_CH_MUXNEG_PIN1_gc = (0x01<<0), /* Input pin 1 */ - ADC_CH_MUXNEG_PIN2_gc = (0x02<<0), /* Input pin 2 */ - ADC_CH_MUXNEG_PIN3_gc = (0x03<<0), /* Input pin 3 */ - ADC_CH_MUXNEG_PIN4_gc = (0x00<<0), /* Input pin 4 */ - ADC_CH_MUXNEG_PIN5_gc = (0x01<<0), /* Input pin 5 */ - ADC_CH_MUXNEG_PIN6_gc = (0x02<<0), /* Input pin 6 */ - ADC_CH_MUXNEG_PIN7_gc = (0x03<<0), /* Input pin 7 */ -} ADC_CH_MUXNEG_t; - -/* Input mode */ -typedef enum ADC_CH_INPUTMODE_enum -{ - ADC_CH_INPUTMODE_INTERNAL_gc = (0x00<<0), /* Internal inputs, no gain */ - ADC_CH_INPUTMODE_SINGLEENDED_gc = (0x01<<0), /* Single-ended input, no gain */ - ADC_CH_INPUTMODE_DIFF_gc = (0x02<<0), /* Differential input, no gain */ - ADC_CH_INPUTMODE_DIFFWGAIN_gc = (0x03<<0), /* Differential input, with gain */ -} ADC_CH_INPUTMODE_t; - -/* Gain factor */ -typedef enum ADC_CH_GAIN_enum -{ - ADC_CH_GAIN_1X_gc = (0x00<<2), /* 1x gain */ - ADC_CH_GAIN_2X_gc = (0x01<<2), /* 2x gain */ - ADC_CH_GAIN_4X_gc = (0x02<<2), /* 4x gain */ - ADC_CH_GAIN_8X_gc = (0x03<<2), /* 8x gain */ - ADC_CH_GAIN_16X_gc = (0x04<<2), /* 16x gain */ - ADC_CH_GAIN_32X_gc = (0x05<<2), /* 32x gain */ - ADC_CH_GAIN_64X_gc = (0x06<<2), /* 64x gain */ - ADC_CH_GAIN_DIV2_gc = (0x07<<2), /* x/2 gain */ -} ADC_CH_GAIN_t; - -/* Conversion result resolution */ -typedef enum ADC_RESOLUTION_enum -{ - ADC_RESOLUTION_12BIT_gc = (0x00<<1), /* 12-bit right-adjusted result */ - ADC_RESOLUTION_8BIT_gc = (0x02<<1), /* 8-bit right-adjusted result */ - ADC_RESOLUTION_LEFT12BIT_gc = (0x03<<1), /* 12-bit left-adjusted result */ -} ADC_RESOLUTION_t; - -/* Voltage reference selection */ -typedef enum ADC_REFSEL_enum -{ - ADC_REFSEL_INT1V_gc = (0x00<<4), /* Internal 1V */ - ADC_REFSEL_INTVCC_gc = (0x01<<4), /* Internal VCC / 1.6 */ - ADC_REFSEL_AREFA_gc = (0x02<<4), /* External reference on PORT A */ - ADC_REFSEL_AREFB_gc = (0x03<<4), /* External reference on PORT B */ - ADC_REFSEL_INTVCC2_gc = (0x04<<4), /* Internal VCC / 2 */ -} ADC_REFSEL_t; - -/* Event channel input selection */ -typedef enum ADC_EVSEL_enum -{ - ADC_EVSEL_0_gc = (0x00<<3), /* Event Channel 0 */ - ADC_EVSEL_1_gc = (0x01<<3), /* Event Channel 1 */ - ADC_EVSEL_2_gc = (0x02<<3), /* Event Channel 2 */ - ADC_EVSEL_3_gc = (0x03<<3), /* Event Channel 3 */ -} ADC_EVSEL_t; - -/* Event action selection */ -typedef enum ADC_EVACT_enum -{ - ADC_EVACT_NONE_gc = (0x00<<0), /* No event action */ - ADC_EVACT_CH0_gc = (0x01<<0), /* First event triggers channel 0 */ - ADC_EVACT_SYNCSWEEP_gc = (0x06<<0), /* The ADC is flushed and restarted for accurate timing */ -} ADC_EVACT_t; - -/* Interupt mode */ -typedef enum ADC_CH_INTMODE_enum -{ - ADC_CH_INTMODE_COMPLETE_gc = (0x00<<2), /* Interrupt on conversion complete */ - ADC_CH_INTMODE_BELOW_gc = (0x01<<2), /* Interrupt on result below compare value */ - ADC_CH_INTMODE_ABOVE_gc = (0x03<<2), /* Interrupt on result above compare value */ -} ADC_CH_INTMODE_t; - -/* Interrupt level */ -typedef enum ADC_CH_INTLVL_enum -{ - ADC_CH_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ - ADC_CH_INTLVL_LO_gc = (0x01<<0), /* Low level */ - ADC_CH_INTLVL_MED_gc = (0x02<<0), /* Medium level */ - ADC_CH_INTLVL_HI_gc = (0x03<<0), /* High level */ -} ADC_CH_INTLVL_t; - -/* Clock prescaler */ -typedef enum ADC_PRESCALER_enum -{ - ADC_PRESCALER_DIV4_gc = (0x00<<0), /* Divide clock by 4 */ - ADC_PRESCALER_DIV8_gc = (0x01<<0), /* Divide clock by 8 */ - ADC_PRESCALER_DIV16_gc = (0x02<<0), /* Divide clock by 16 */ - ADC_PRESCALER_DIV32_gc = (0x03<<0), /* Divide clock by 32 */ - ADC_PRESCALER_DIV64_gc = (0x04<<0), /* Divide clock by 64 */ - ADC_PRESCALER_DIV128_gc = (0x05<<0), /* Divide clock by 128 */ - ADC_PRESCALER_DIV256_gc = (0x06<<0), /* Divide clock by 256 */ - ADC_PRESCALER_DIV512_gc = (0x07<<0), /* Divide clock by 512 */ -} ADC_PRESCALER_t; - - -/* --------------------------------------------------------------------------- -AC - Analog Comparator --------------------------------------------------------------------------- -*/ - -/* Analog Comparator */ -typedef struct AC_struct -{ - register8_t AC0CTRL; /* Analog Comparator 0 Control */ - register8_t AC1CTRL; /* Analog Comparator 1 Control */ - register8_t AC0MUXCTRL; /* Analog Comparator 0 MUX Control */ - register8_t AC1MUXCTRL; /* Analog Comparator 1 MUX Control */ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t WINCTRL; /* Window Mode Control */ - register8_t STATUS; /* Status */ -} AC_t; - -/* Interrupt mode */ -typedef enum AC_INTMODE_enum -{ - AC_INTMODE_BOTHEDGES_gc = (0x00<<6), /* Interrupt on both edges */ - AC_INTMODE_FALLING_gc = (0x02<<6), /* Interrupt on falling edge */ - AC_INTMODE_RISING_gc = (0x03<<6), /* Interrupt on rising edge */ -} AC_INTMODE_t; - -/* Interrupt level */ -typedef enum AC_INTLVL_enum -{ - AC_INTLVL_OFF_gc = (0x00<<4), /* Interrupt disabled */ - AC_INTLVL_LO_gc = (0x01<<4), /* Low level */ - AC_INTLVL_MED_gc = (0x02<<4), /* Medium level */ - AC_INTLVL_HI_gc = (0x03<<4), /* High level */ -} AC_INTLVL_t; - -/* Hysteresis mode selection */ -typedef enum AC_HYSMODE_enum -{ - AC_HYSMODE_NO_gc = (0x00<<1), /* No hysteresis */ - AC_HYSMODE_SMALL_gc = (0x01<<1), /* Small hysteresis */ - AC_HYSMODE_LARGE_gc = (0x02<<1), /* Large hysteresis */ -} AC_HYSMODE_t; - -/* Positive input multiplexer selection */ -typedef enum AC_MUXPOS_enum -{ - AC_MUXPOS_PIN0_gc = (0x00<<3), /* Pin 0 */ - AC_MUXPOS_PIN1_gc = (0x01<<3), /* Pin 1 */ - AC_MUXPOS_PIN2_gc = (0x02<<3), /* Pin 2 */ - AC_MUXPOS_PIN3_gc = (0x03<<3), /* Pin 3 */ - AC_MUXPOS_PIN4_gc = (0x04<<3), /* Pin 4 */ - AC_MUXPOS_PIN5_gc = (0x05<<3), /* Pin 5 */ - AC_MUXPOS_PIN6_gc = (0x06<<3), /* Pin 6 */ -} AC_MUXPOS_t; - -/* Negative input multiplexer selection */ -typedef enum AC_MUXNEG_enum -{ - AC_MUXNEG_PIN0_gc = (0x00<<0), /* Pin 0 */ - AC_MUXNEG_PIN1_gc = (0x01<<0), /* Pin 1 */ - AC_MUXNEG_PIN3_gc = (0x02<<0), /* Pin 3 */ - AC_MUXNEG_PIN5_gc = (0x03<<0), /* Pin 5 */ - AC_MUXNEG_PIN7_gc = (0x04<<0), /* Pin 7 */ - AC_MUXNEG_BANDGAP_gc = (0x06<<0), /* Bandgap Reference */ - AC_MUXNEG_SCALER_gc = (0x07<<0), /* Internal voltage scaler */ -} AC_MUXNEG_t; - -/* Windows interrupt mode */ -typedef enum AC_WINTMODE_enum -{ - AC_WINTMODE_ABOVE_gc = (0x00<<2), /* Interrupt on above window */ - AC_WINTMODE_INSIDE_gc = (0x01<<2), /* Interrupt on inside window */ - AC_WINTMODE_BELOW_gc = (0x02<<2), /* Interrupt on below window */ - AC_WINTMODE_OUTSIDE_gc = (0x03<<2), /* Interrupt on outside window */ -} AC_WINTMODE_t; - -/* Window interrupt level */ -typedef enum AC_WINTLVL_enum -{ - AC_WINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ - AC_WINTLVL_LO_gc = (0x01<<0), /* Low priority */ - AC_WINTLVL_MED_gc = (0x02<<0), /* Medium priority */ - AC_WINTLVL_HI_gc = (0x03<<0), /* High priority */ -} AC_WINTLVL_t; - -/* Window mode state */ -typedef enum AC_WSTATE_enum -{ - AC_WSTATE_ABOVE_gc = (0x00<<6), /* Signal above window */ - AC_WSTATE_INSIDE_gc = (0x01<<6), /* Signal inside window */ - AC_WSTATE_BELOW_gc = (0x02<<6), /* Signal below window */ -} AC_WSTATE_t; - - -/* --------------------------------------------------------------------------- -RTC - Real-Time Counter --------------------------------------------------------------------------- -*/ - -/* Real-Time Counter */ -typedef struct RTC_struct -{ - register8_t CTRL; /* Control Register */ - register8_t STATUS; /* Status Register */ - register8_t INTCTRL; /* Interrupt Control Register */ - register8_t INTFLAGS; /* Interrupt Flags */ - register8_t TEMP; /* Temporary register */ - register8_t reserved_0x05; - register8_t reserved_0x06; - register8_t reserved_0x07; - _WORDREGISTER(CNT); /* Count Register */ - _WORDREGISTER(PER); /* Period Register */ - _WORDREGISTER(COMP); /* Compare Register */ -} RTC_t; - -/* Prescaler Factor */ -typedef enum RTC_PRESCALER_enum -{ - RTC_PRESCALER_OFF_gc = (0x00<<0), /* RTC Off */ - RTC_PRESCALER_DIV1_gc = (0x01<<0), /* RTC Clock */ - RTC_PRESCALER_DIV2_gc = (0x02<<0), /* RTC Clock / 2 */ - RTC_PRESCALER_DIV8_gc = (0x03<<0), /* RTC Clock / 8 */ - RTC_PRESCALER_DIV16_gc = (0x04<<0), /* RTC Clock / 16 */ - RTC_PRESCALER_DIV64_gc = (0x05<<0), /* RTC Clock / 64 */ - RTC_PRESCALER_DIV256_gc = (0x06<<0), /* RTC Clock / 256 */ - RTC_PRESCALER_DIV1024_gc = (0x07<<0), /* RTC Clock / 1024 */ -} RTC_PRESCALER_t; - -/* Compare Interrupt level */ -typedef enum RTC_COMPINTLVL_enum -{ - RTC_COMPINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ - RTC_COMPINTLVL_LO_gc = (0x01<<2), /* Low Level */ - RTC_COMPINTLVL_MED_gc = (0x02<<2), /* Medium Level */ - RTC_COMPINTLVL_HI_gc = (0x03<<2), /* High Level */ -} RTC_COMPINTLVL_t; - -/* Overflow Interrupt level */ -typedef enum RTC_OVFINTLVL_enum -{ - RTC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - RTC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ - RTC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ - RTC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ -} RTC_OVFINTLVL_t; - - -/* --------------------------------------------------------------------------- -TWI - Two-Wire Interface --------------------------------------------------------------------------- -*/ - -/* */ -typedef struct TWI_MASTER_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t CTRLC; /* Control Register C */ - register8_t STATUS; /* Status Register */ - register8_t BAUD; /* Baurd Rate Control Register */ - register8_t ADDR; /* Address Register */ - register8_t DATA; /* Data Register */ -} TWI_MASTER_t; - - -/* */ -typedef struct TWI_SLAVE_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t STATUS; /* Status Register */ - register8_t ADDR; /* Address Register */ - register8_t DATA; /* Data Register */ - register8_t ADDRMASK; /* Address Mask Register */ -} TWI_SLAVE_t; - - -/* Two-Wire Interface */ -typedef struct TWI_struct -{ - register8_t CTRL; /* TWI Common Control Register */ - TWI_MASTER_t MASTER; /* TWI master module */ - TWI_SLAVE_t SLAVE; /* TWI slave module */ -} TWI_t; - -/* SDA Hold Time */ -typedef enum TWI_SDAHOLD_enum -{ - TWI_SDAHOLD_OFF_gc = (0x00<<1), /* SDA Hold Time off */ - TWI_SDAHOLD_50NS_gc = (0x01<<1), /* SDA Hold Time 50 ns */ - TWI_SDAHOLD_300NS_gc = (0x02<<1), /* SDA Hold Time 300 ns */ - TWI_SDAHOLD_400NS_gc = (0x03<<1), /* SDA Hold Time 400 ns */ -} TWI_SDAHOLD_t; - -/* Master Interrupt Level */ -typedef enum TWI_MASTER_INTLVL_enum -{ - TWI_MASTER_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ - TWI_MASTER_INTLVL_LO_gc = (0x01<<6), /* Low Level */ - TWI_MASTER_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ - TWI_MASTER_INTLVL_HI_gc = (0x03<<6), /* High Level */ -} TWI_MASTER_INTLVL_t; - -/* Inactive Timeout */ -typedef enum TWI_MASTER_TIMEOUT_enum -{ - TWI_MASTER_TIMEOUT_DISABLED_gc = (0x00<<2), /* Bus Timeout Disabled */ - TWI_MASTER_TIMEOUT_50US_gc = (0x01<<2), /* 50 Microseconds */ - TWI_MASTER_TIMEOUT_100US_gc = (0x02<<2), /* 100 Microseconds */ - TWI_MASTER_TIMEOUT_200US_gc = (0x03<<2), /* 200 Microseconds */ -} TWI_MASTER_TIMEOUT_t; - -/* Master Command */ -typedef enum TWI_MASTER_CMD_enum -{ - TWI_MASTER_CMD_NOACT_gc = (0x00<<0), /* No Action */ - TWI_MASTER_CMD_REPSTART_gc = (0x01<<0), /* Issue Repeated Start Condition */ - TWI_MASTER_CMD_RECVTRANS_gc = (0x02<<0), /* Receive or Transmit Data */ - TWI_MASTER_CMD_STOP_gc = (0x03<<0), /* Issue Stop Condition */ -} TWI_MASTER_CMD_t; - -/* Master Bus State */ -typedef enum TWI_MASTER_BUSSTATE_enum -{ - TWI_MASTER_BUSSTATE_UNKNOWN_gc = (0x00<<0), /* Unknown Bus State */ - TWI_MASTER_BUSSTATE_IDLE_gc = (0x01<<0), /* Bus is Idle */ - TWI_MASTER_BUSSTATE_OWNER_gc = (0x02<<0), /* This Module Controls The Bus */ - TWI_MASTER_BUSSTATE_BUSY_gc = (0x03<<0), /* The Bus is Busy */ -} TWI_MASTER_BUSSTATE_t; - -/* Slave Interrupt Level */ -typedef enum TWI_SLAVE_INTLVL_enum -{ - TWI_SLAVE_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ - TWI_SLAVE_INTLVL_LO_gc = (0x01<<6), /* Low Level */ - TWI_SLAVE_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ - TWI_SLAVE_INTLVL_HI_gc = (0x03<<6), /* High Level */ -} TWI_SLAVE_INTLVL_t; - -/* Slave Command */ -typedef enum TWI_SLAVE_CMD_enum -{ - TWI_SLAVE_CMD_NOACT_gc = (0x00<<0), /* No Action */ - TWI_SLAVE_CMD_COMPTRANS_gc = (0x02<<0), /* Used To Complete a Transaction */ - TWI_SLAVE_CMD_RESPONSE_gc = (0x03<<0), /* Used in Response to Address/Data Interrupt */ -} TWI_SLAVE_CMD_t; - - -/* --------------------------------------------------------------------------- -USB - USB --------------------------------------------------------------------------- -*/ - -/* USB Endpoint */ -typedef struct USB_EP_struct -{ - register8_t STATUS; /* Endpoint Status */ - register8_t CTRL; /* Endpoint Control */ - _WORDREGISTER(CNT); /* USB Endpoint Counter */ - _WORDREGISTER(DATAPTR); /* Data Pointer */ - _WORDREGISTER(AUXDATA); /* Auxiliary Data */ -} USB_EP_t; - - -/* Universal Serial Bus */ -typedef struct USB_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t STATUS; /* Status Register */ - register8_t ADDR; /* Address Register */ - register8_t FIFOWP; /* FIFO Write Pointer Register */ - register8_t FIFORP; /* FIFO Read Pointer Register */ - _WORDREGISTER(EPPTR); /* Endpoint Configuration Table Pointer */ - register8_t INTCTRLA; /* Interrupt Control Register A */ - register8_t INTCTRLB; /* Interrupt Control Register B */ - register8_t INTFLAGSACLR; /* Clear Interrupt Flag Register A */ - register8_t INTFLAGSASET; /* Set Interrupt Flag Register A */ - register8_t INTFLAGSBCLR; /* Clear Interrupt Flag Register B */ - register8_t INTFLAGSBSET; /* Set Interrupt Flag Register B */ - register8_t reserved_0x0E; - register8_t reserved_0x0F; - register8_t reserved_0x10; - register8_t reserved_0x11; - register8_t reserved_0x12; - register8_t reserved_0x13; - register8_t reserved_0x14; - register8_t reserved_0x15; - register8_t reserved_0x16; - register8_t reserved_0x17; - register8_t reserved_0x18; - register8_t reserved_0x19; - register8_t reserved_0x1A; - register8_t reserved_0x1B; - register8_t reserved_0x1C; - register8_t reserved_0x1D; - register8_t reserved_0x1E; - register8_t reserved_0x1F; - register8_t reserved_0x20; - register8_t reserved_0x21; - register8_t reserved_0x22; - register8_t reserved_0x23; - register8_t reserved_0x24; - register8_t reserved_0x25; - register8_t reserved_0x26; - register8_t reserved_0x27; - register8_t reserved_0x28; - register8_t reserved_0x29; - register8_t reserved_0x2A; - register8_t reserved_0x2B; - register8_t reserved_0x2C; - register8_t reserved_0x2D; - register8_t reserved_0x2E; - register8_t reserved_0x2F; - register8_t reserved_0x30; - register8_t reserved_0x31; - register8_t reserved_0x32; - register8_t reserved_0x33; - register8_t reserved_0x34; - register8_t reserved_0x35; - register8_t reserved_0x36; - register8_t reserved_0x37; - register8_t reserved_0x38; - register8_t reserved_0x39; - register8_t CAL0; /* Calibration Byte 0 */ - register8_t CAL1; /* Calibration Byte 1 */ -} USB_t; - - -/* USB Endpoint Table */ -typedef struct USB_EP_TABLE_struct -{ - USB_EP_t EP0OUT; /* Endpoint 0 */ - USB_EP_t EP0IN; /* Endpoint 0 */ - USB_EP_t EP1OUT; /* Endpoint 1 */ - USB_EP_t EP1IN; /* Endpoint 1 */ - USB_EP_t EP2OUT; /* Endpoint 2 */ - USB_EP_t EP2IN; /* Endpoint 2 */ - USB_EP_t EP3OUT; /* Endpoint 3 */ - USB_EP_t EP3IN; /* Endpoint 3 */ - USB_EP_t EP4OUT; /* Endpoint 4 */ - USB_EP_t EP4IN; /* Endpoint 4 */ - USB_EP_t EP5OUT; /* Endpoint 5 */ - USB_EP_t EP5IN; /* Endpoint 5 */ - USB_EP_t EP6OUT; /* Endpoint 6 */ - USB_EP_t EP6IN; /* Endpoint 6 */ - USB_EP_t EP7OUT; /* Endpoint 7 */ - USB_EP_t EP7IN; /* Endpoint 7 */ - USB_EP_t EP8OUT; /* Endpoint 8 */ - USB_EP_t EP8IN; /* Endpoint 8 */ - USB_EP_t EP9OUT; /* Endpoint 9 */ - USB_EP_t EP9IN; /* Endpoint 9 */ - USB_EP_t EP10OUT; /* Endpoint 10 */ - USB_EP_t EP10IN; /* Endpoint 10 */ - USB_EP_t EP11OUT; /* Endpoint 11 */ - USB_EP_t EP11IN; /* Endpoint 11 */ - USB_EP_t EP12OUT; /* Endpoint 12 */ - USB_EP_t EP12IN; /* Endpoint 12 */ - USB_EP_t EP13OUT; /* Endpoint 13 */ - USB_EP_t EP13IN; /* Endpoint 13 */ - USB_EP_t EP14OUT; /* Endpoint 14 */ - USB_EP_t EP14IN; /* Endpoint 14 */ - USB_EP_t EP15OUT; /* Endpoint 15 */ - USB_EP_t EP15IN; /* Endpoint 15 */ - register8_t reserved_0x100; - register8_t reserved_0x101; - register8_t reserved_0x102; - register8_t reserved_0x103; - register8_t reserved_0x104; - register8_t reserved_0x105; - register8_t reserved_0x106; - register8_t reserved_0x107; - register8_t reserved_0x108; - register8_t reserved_0x109; - register8_t reserved_0x10A; - register8_t reserved_0x10B; - register8_t reserved_0x10C; - register8_t reserved_0x10D; - register8_t reserved_0x10E; - register8_t reserved_0x10F; - register8_t FRAMENUML; /* Frame Number Low Byte */ - register8_t FRAMENUMH; /* Frame Number High Byte */ -} USB_EP_TABLE_t; - -/* Interrupt level */ -typedef enum USB_INTLVL_enum -{ - USB_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ - USB_INTLVL_LO_gc = (0x01<<0), /* Low level */ - USB_INTLVL_MED_gc = (0x02<<0), /* Medium level */ - USB_INTLVL_HI_gc = (0x03<<0), /* High level */ -} USB_INTLVL_t; - -/* USB Endpoint Type */ -typedef enum USB_EP_TYPE_enum -{ - USB_EP_TYPE_DISABLE_gc = (0x00<<6), /* Endpoint Disabled */ - USB_EP_TYPE_CONTROL_gc = (0x01<<6), /* Control */ - USB_EP_TYPE_BULK_gc = (0x02<<6), /* Bulk/Interrupt */ - USB_EP_TYPE_ISOCHRONOUS_gc = (0x03<<6), /* Isochronous */ -} USB_EP_TYPE_t; - -/* USB Endpoint Buffersize */ -typedef enum USB_EP_BUFSIZE_enum -{ - USB_EP_BUFSIZE_8_gc = (0x00<<0), /* 8 bytes buffer size */ - USB_EP_BUFSIZE_16_gc = (0x01<<0), /* 16 bytes buffer size */ - USB_EP_BUFSIZE_32_gc = (0x02<<0), /* 32 bytes buffer size */ - USB_EP_BUFSIZE_64_gc = (0x03<<0), /* 64 bytes buffer size */ - USB_EP_BUFSIZE_128_gc = (0x04<<0), /* 128 bytes buffer size */ - USB_EP_BUFSIZE_256_gc = (0x05<<0), /* 256 bytes buffer size */ - USB_EP_BUFSIZE_512_gc = (0x06<<0), /* 512 bytes buffer size */ - USB_EP_BUFSIZE_1023_gc = (0x07<<0), /* 1023 bytes buffer size */ -} USB_EP_BUFSIZE_t; - - -/* --------------------------------------------------------------------------- -PORT - I/O Port Configuration --------------------------------------------------------------------------- -*/ - -/* I/O Ports */ -typedef struct PORT_struct -{ - register8_t DIR; /* I/O Port Data Direction */ - register8_t DIRSET; /* I/O Port Data Direction Set */ - register8_t DIRCLR; /* I/O Port Data Direction Clear */ - register8_t DIRTGL; /* I/O Port Data Direction Toggle */ - register8_t OUT; /* I/O Port Output */ - register8_t OUTSET; /* I/O Port Output Set */ - register8_t OUTCLR; /* I/O Port Output Clear */ - register8_t OUTTGL; /* I/O Port Output Toggle */ - register8_t IN; /* I/O port Input */ - register8_t INTCTRL; /* Interrupt Control Register */ - register8_t INT0MASK; /* Port Interrupt 0 Mask */ - register8_t INT1MASK; /* Port Interrupt 1 Mask */ - register8_t INTFLAGS; /* Interrupt Flag Register */ - register8_t reserved_0x0D; - register8_t REMAP; /* I/O Port Pin Remap Register */ - register8_t reserved_0x0F; - register8_t PIN0CTRL; /* Pin 0 Control Register */ - register8_t PIN1CTRL; /* Pin 1 Control Register */ - register8_t PIN2CTRL; /* Pin 2 Control Register */ - register8_t PIN3CTRL; /* Pin 3 Control Register */ - register8_t PIN4CTRL; /* Pin 4 Control Register */ - register8_t PIN5CTRL; /* Pin 5 Control Register */ - register8_t PIN6CTRL; /* Pin 6 Control Register */ - register8_t PIN7CTRL; /* Pin 7 Control Register */ -} PORT_t; - -/* Port Interrupt 0 Level */ -typedef enum PORT_INT0LVL_enum -{ - PORT_INT0LVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - PORT_INT0LVL_LO_gc = (0x01<<0), /* Low Level */ - PORT_INT0LVL_MED_gc = (0x02<<0), /* Medium Level */ - PORT_INT0LVL_HI_gc = (0x03<<0), /* High Level */ -} PORT_INT0LVL_t; - -/* Port Interrupt 1 Level */ -typedef enum PORT_INT1LVL_enum -{ - PORT_INT1LVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ - PORT_INT1LVL_LO_gc = (0x01<<2), /* Low Level */ - PORT_INT1LVL_MED_gc = (0x02<<2), /* Medium Level */ - PORT_INT1LVL_HI_gc = (0x03<<2), /* High Level */ -} PORT_INT1LVL_t; - -/* Output/Pull Configuration */ -typedef enum PORT_OPC_enum -{ - PORT_OPC_TOTEM_gc = (0x00<<3), /* Totempole */ - PORT_OPC_BUSKEEPER_gc = (0x01<<3), /* Totempole w/ Bus keeper on Input and Output */ - PORT_OPC_PULLDOWN_gc = (0x02<<3), /* Totempole w/ Pull-down on Input */ - PORT_OPC_PULLUP_gc = (0x03<<3), /* Totempole w/ Pull-up on Input */ - PORT_OPC_WIREDOR_gc = (0x04<<3), /* Wired OR */ - PORT_OPC_WIREDAND_gc = (0x05<<3), /* Wired AND */ - PORT_OPC_WIREDORPULL_gc = (0x06<<3), /* Wired OR w/ Pull-down */ - PORT_OPC_WIREDANDPULL_gc = (0x07<<3), /* Wired AND w/ Pull-up */ -} PORT_OPC_t; - -/* Input/Sense Configuration */ -typedef enum PORT_ISC_enum -{ - PORT_ISC_BOTHEDGES_gc = (0x00<<0), /* Sense Both Edges */ - PORT_ISC_RISING_gc = (0x01<<0), /* Sense Rising Edge */ - PORT_ISC_FALLING_gc = (0x02<<0), /* Sense Falling Edge */ - PORT_ISC_LEVEL_gc = (0x03<<0), /* Sense Level (Transparent For Events) */ - PORT_ISC_INPUT_DISABLE_gc = (0x07<<0), /* Disable Digital Input Buffer */ -} PORT_ISC_t; - - -/* --------------------------------------------------------------------------- -TC - 16-bit Timer/Counter With PWM --------------------------------------------------------------------------- -*/ - -/* 16-bit Timer/Counter 0 */ -typedef struct TC0_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t CTRLC; /* Control register C */ - register8_t CTRLD; /* Control Register D */ - register8_t CTRLE; /* Control Register E */ - register8_t reserved_0x05; - register8_t INTCTRLA; /* Interrupt Control Register A */ - register8_t INTCTRLB; /* Interrupt Control Register B */ - register8_t CTRLFCLR; /* Control Register F Clear */ - register8_t CTRLFSET; /* Control Register F Set */ - register8_t CTRLGCLR; /* Control Register G Clear */ - register8_t CTRLGSET; /* Control Register G Set */ - register8_t INTFLAGS; /* Interrupt Flag Register */ - register8_t reserved_0x0D; - register8_t reserved_0x0E; - register8_t TEMP; /* Temporary Register For 16-bit Access */ - register8_t reserved_0x10; - register8_t reserved_0x11; - register8_t reserved_0x12; - register8_t reserved_0x13; - register8_t reserved_0x14; - register8_t reserved_0x15; - register8_t reserved_0x16; - register8_t reserved_0x17; - register8_t reserved_0x18; - register8_t reserved_0x19; - register8_t reserved_0x1A; - register8_t reserved_0x1B; - register8_t reserved_0x1C; - register8_t reserved_0x1D; - register8_t reserved_0x1E; - register8_t reserved_0x1F; - _WORDREGISTER(CNT); /* Count */ - register8_t reserved_0x22; - register8_t reserved_0x23; - register8_t reserved_0x24; - register8_t reserved_0x25; - _WORDREGISTER(PER); /* Period */ - _WORDREGISTER(CCA); /* Compare or Capture A */ - _WORDREGISTER(CCB); /* Compare or Capture B */ - _WORDREGISTER(CCC); /* Compare or Capture C */ - _WORDREGISTER(CCD); /* Compare or Capture D */ - register8_t reserved_0x30; - register8_t reserved_0x31; - register8_t reserved_0x32; - register8_t reserved_0x33; - register8_t reserved_0x34; - register8_t reserved_0x35; - _WORDREGISTER(PERBUF); /* Period Buffer */ - _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ - _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ - _WORDREGISTER(CCCBUF); /* Compare Or Capture C Buffer */ - _WORDREGISTER(CCDBUF); /* Compare Or Capture D Buffer */ -} TC0_t; - - -/* 16-bit Timer/Counter 1 */ -typedef struct TC1_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t CTRLC; /* Control register C */ - register8_t CTRLD; /* Control Register D */ - register8_t CTRLE; /* Control Register E */ - register8_t reserved_0x05; - register8_t INTCTRLA; /* Interrupt Control Register A */ - register8_t INTCTRLB; /* Interrupt Control Register B */ - register8_t CTRLFCLR; /* Control Register F Clear */ - register8_t CTRLFSET; /* Control Register F Set */ - register8_t CTRLGCLR; /* Control Register G Clear */ - register8_t CTRLGSET; /* Control Register G Set */ - register8_t INTFLAGS; /* Interrupt Flag Register */ - register8_t reserved_0x0D; - register8_t reserved_0x0E; - register8_t TEMP; /* Temporary Register For 16-bit Access */ - register8_t reserved_0x10; - register8_t reserved_0x11; - register8_t reserved_0x12; - register8_t reserved_0x13; - register8_t reserved_0x14; - register8_t reserved_0x15; - register8_t reserved_0x16; - register8_t reserved_0x17; - register8_t reserved_0x18; - register8_t reserved_0x19; - register8_t reserved_0x1A; - register8_t reserved_0x1B; - register8_t reserved_0x1C; - register8_t reserved_0x1D; - register8_t reserved_0x1E; - register8_t reserved_0x1F; - _WORDREGISTER(CNT); /* Count */ - register8_t reserved_0x22; - register8_t reserved_0x23; - register8_t reserved_0x24; - register8_t reserved_0x25; - _WORDREGISTER(PER); /* Period */ - _WORDREGISTER(CCA); /* Compare or Capture A */ - _WORDREGISTER(CCB); /* Compare or Capture B */ - register8_t reserved_0x2C; - register8_t reserved_0x2D; - register8_t reserved_0x2E; - register8_t reserved_0x2F; - register8_t reserved_0x30; - register8_t reserved_0x31; - register8_t reserved_0x32; - register8_t reserved_0x33; - register8_t reserved_0x34; - register8_t reserved_0x35; - _WORDREGISTER(PERBUF); /* Period Buffer */ - _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ - _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ -} TC1_t; - -/* Clock Selection */ -typedef enum TC_CLKSEL_enum -{ - TC_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */ - TC_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */ - TC_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */ - TC_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */ - TC_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */ - TC_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */ - TC_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */ - TC_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */ - TC_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */ - TC_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */ - TC_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */ - TC_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */ -} TC_CLKSEL_t; - -/* Waveform Generation Mode */ -typedef enum TC_WGMODE_enum -{ - TC_WGMODE_NORMAL_gc = (0x00<<0), /* Normal Mode */ - TC_WGMODE_FRQ_gc = (0x01<<0), /* Frequency Generation Mode */ - TC_WGMODE_SINGLESLOPE_gc = (0x03<<0), /* Single Slope */ - TC_WGMODE_SS_gc = (0x03<<0), /* Single Slope */ - TC_WGMODE_DSTOP_gc = (0x05<<0), /* Dual Slope, Update on TOP */ - TC_WGMODE_DS_T_gc = (0x05<<0), /* Dual Slope, Update on TOP */ - TC_WGMODE_DSBOTH_gc = (0x06<<0), /* Dual Slope, Update on both TOP and BOTTOM */ - TC_WGMODE_DS_TB_gc = (0x06<<0), /* Dual Slope, Update on both TOP and BOTTOM */ - TC_WGMODE_DSBOTTOM_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */ - TC_WGMODE_DS_B_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */ -} TC_WGMODE_t; - -/* Byte Mode */ -typedef enum TC_BYTEM_enum -{ - TC_BYTEM_NORMAL_gc = (0x00<<0), /* 16-bit mode */ - TC_BYTEM_BYTEMODE_gc = (0x01<<0), /* Timer/Counter operating in byte mode only */ - TC_BYTEM_SPLITMODE_gc = (0x02<<0), /* Timer/Counter split into two 8-bit Counters (TC2) */ -} TC_BYTEM_t; - -/* Event Action */ -typedef enum TC_EVACT_enum -{ - TC_EVACT_OFF_gc = (0x00<<5), /* No Event Action */ - TC_EVACT_CAPT_gc = (0x01<<5), /* Input Capture */ - TC_EVACT_UPDOWN_gc = (0x02<<5), /* Externally Controlled Up/Down Count */ - TC_EVACT_QDEC_gc = (0x03<<5), /* Quadrature Decode */ - TC_EVACT_RESTART_gc = (0x04<<5), /* Restart */ - TC_EVACT_FRQ_gc = (0x05<<5), /* Frequency Capture */ - TC_EVACT_PW_gc = (0x06<<5), /* Pulse-width Capture */ -} TC_EVACT_t; - -/* Event Selection */ -typedef enum TC_EVSEL_enum -{ - TC_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ - TC_EVSEL_CH0_gc = (0x08<<0), /* Event Channel 0 */ - TC_EVSEL_CH1_gc = (0x09<<0), /* Event Channel 1 */ - TC_EVSEL_CH2_gc = (0x0A<<0), /* Event Channel 2 */ - TC_EVSEL_CH3_gc = (0x0B<<0), /* Event Channel 3 */ -} TC_EVSEL_t; - -/* Error Interrupt Level */ -typedef enum TC_ERRINTLVL_enum -{ - TC_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ - TC_ERRINTLVL_LO_gc = (0x01<<2), /* Low Level */ - TC_ERRINTLVL_MED_gc = (0x02<<2), /* Medium Level */ - TC_ERRINTLVL_HI_gc = (0x03<<2), /* High Level */ -} TC_ERRINTLVL_t; - -/* Overflow Interrupt Level */ -typedef enum TC_OVFINTLVL_enum -{ - TC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - TC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ - TC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ - TC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ -} TC_OVFINTLVL_t; - -/* Compare or Capture D Interrupt Level */ -typedef enum TC_CCDINTLVL_enum -{ - TC_CCDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ - TC_CCDINTLVL_LO_gc = (0x01<<6), /* Low Level */ - TC_CCDINTLVL_MED_gc = (0x02<<6), /* Medium Level */ - TC_CCDINTLVL_HI_gc = (0x03<<6), /* High Level */ -} TC_CCDINTLVL_t; - -/* Compare or Capture C Interrupt Level */ -typedef enum TC_CCCINTLVL_enum -{ - TC_CCCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ - TC_CCCINTLVL_LO_gc = (0x01<<4), /* Low Level */ - TC_CCCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ - TC_CCCINTLVL_HI_gc = (0x03<<4), /* High Level */ -} TC_CCCINTLVL_t; - -/* Compare or Capture B Interrupt Level */ -typedef enum TC_CCBINTLVL_enum -{ - TC_CCBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ - TC_CCBINTLVL_LO_gc = (0x01<<2), /* Low Level */ - TC_CCBINTLVL_MED_gc = (0x02<<2), /* Medium Level */ - TC_CCBINTLVL_HI_gc = (0x03<<2), /* High Level */ -} TC_CCBINTLVL_t; - -/* Compare or Capture A Interrupt Level */ -typedef enum TC_CCAINTLVL_enum -{ - TC_CCAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - TC_CCAINTLVL_LO_gc = (0x01<<0), /* Low Level */ - TC_CCAINTLVL_MED_gc = (0x02<<0), /* Medium Level */ - TC_CCAINTLVL_HI_gc = (0x03<<0), /* High Level */ -} TC_CCAINTLVL_t; - -/* Timer/Counter Command */ -typedef enum TC_CMD_enum -{ - TC_CMD_NONE_gc = (0x00<<2), /* No Command */ - TC_CMD_UPDATE_gc = (0x01<<2), /* Force Update */ - TC_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ - TC_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ -} TC_CMD_t; - - -/* --------------------------------------------------------------------------- -TC2 - 16-bit Timer/Counter type 2 --------------------------------------------------------------------------- -*/ - -/* 16-bit Timer/Counter type 2 */ -typedef struct TC2_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t CTRLC; /* Control register C */ - register8_t reserved_0x03; - register8_t CTRLE; /* Control Register E */ - register8_t reserved_0x05; - register8_t INTCTRLA; /* Interrupt Control Register A */ - register8_t INTCTRLB; /* Interrupt Control Register B */ - register8_t reserved_0x08; - register8_t CTRLF; /* Control Register F */ - register8_t reserved_0x0A; - register8_t reserved_0x0B; - register8_t INTFLAGS; /* Interrupt Flag Register */ - register8_t reserved_0x0D; - register8_t reserved_0x0E; - register8_t reserved_0x0F; - register8_t reserved_0x10; - register8_t reserved_0x11; - register8_t reserved_0x12; - register8_t reserved_0x13; - register8_t reserved_0x14; - register8_t reserved_0x15; - register8_t reserved_0x16; - register8_t reserved_0x17; - register8_t reserved_0x18; - register8_t reserved_0x19; - register8_t reserved_0x1A; - register8_t reserved_0x1B; - register8_t reserved_0x1C; - register8_t reserved_0x1D; - register8_t reserved_0x1E; - register8_t reserved_0x1F; - register8_t LCNT; /* Low Byte Count */ - register8_t HCNT; /* High Byte Count */ - register8_t reserved_0x22; - register8_t reserved_0x23; - register8_t reserved_0x24; - register8_t reserved_0x25; - register8_t LPER; /* Low Byte Period */ - register8_t HPER; /* High Byte Period */ - register8_t LCMPA; /* Low Byte Compare A */ - register8_t HCMPA; /* High Byte Compare A */ - register8_t LCMPB; /* Low Byte Compare B */ - register8_t HCMPB; /* High Byte Compare B */ - register8_t LCMPC; /* Low Byte Compare C */ - register8_t HCMPC; /* High Byte Compare C */ - register8_t LCMPD; /* Low Byte Compare D */ - register8_t HCMPD; /* High Byte Compare D */ -} TC2_t; - -/* Clock Selection */ -typedef enum TC2_CLKSEL_enum -{ - TC2_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */ - TC2_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */ - TC2_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */ - TC2_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */ - TC2_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */ - TC2_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */ - TC2_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */ - TC2_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */ - TC2_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */ - TC2_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */ - TC2_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */ - TC2_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */ -} TC2_CLKSEL_t; - -/* Byte Mode */ -typedef enum TC2_BYTEM_enum -{ - TC2_BYTEM_NORMAL_gc = (0x00<<0), /* 16-bit mode */ - TC2_BYTEM_BYTEMODE_gc = (0x01<<0), /* Timer/Counter operating in byte mode only (TC2) */ - TC2_BYTEM_SPLITMODE_gc = (0x02<<0), /* Timer/Counter split into two 8-bit Counters */ -} TC2_BYTEM_t; - -/* High Byte Underflow Interrupt Level */ -typedef enum TC2_HUNFINTLVL_enum -{ - TC2_HUNFINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ - TC2_HUNFINTLVL_LO_gc = (0x01<<2), /* Low Level */ - TC2_HUNFINTLVL_MED_gc = (0x02<<2), /* Medium Level */ - TC2_HUNFINTLVL_HI_gc = (0x03<<2), /* High Level */ -} TC2_HUNFINTLVL_t; - -/* Low Byte Underflow Interrupt Level */ -typedef enum TC2_LUNFINTLVL_enum -{ - TC2_LUNFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - TC2_LUNFINTLVL_LO_gc = (0x01<<0), /* Low Level */ - TC2_LUNFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ - TC2_LUNFINTLVL_HI_gc = (0x03<<0), /* High Level */ -} TC2_LUNFINTLVL_t; - -/* Low Byte Compare D Interrupt Level */ -typedef enum TC2_LCMPDINTLVL_enum -{ - TC2_LCMPDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ - TC2_LCMPDINTLVL_LO_gc = (0x01<<6), /* Low Level */ - TC2_LCMPDINTLVL_MED_gc = (0x02<<6), /* Medium Level */ - TC2_LCMPDINTLVL_HI_gc = (0x03<<6), /* High Level */ -} TC2_LCMPDINTLVL_t; - -/* Low Byte Compare C Interrupt Level */ -typedef enum TC2_LCMPCINTLVL_enum -{ - TC2_LCMPCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ - TC2_LCMPCINTLVL_LO_gc = (0x01<<4), /* Low Level */ - TC2_LCMPCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ - TC2_LCMPCINTLVL_HI_gc = (0x03<<4), /* High Level */ -} TC2_LCMPCINTLVL_t; - -/* Low Byte Compare B Interrupt Level */ -typedef enum TC2_LCMPBINTLVL_enum -{ - TC2_LCMPBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ - TC2_LCMPBINTLVL_LO_gc = (0x01<<2), /* Low Level */ - TC2_LCMPBINTLVL_MED_gc = (0x02<<2), /* Medium Level */ - TC2_LCMPBINTLVL_HI_gc = (0x03<<2), /* High Level */ -} TC2_LCMPBINTLVL_t; - -/* Low Byte Compare A Interrupt Level */ -typedef enum TC2_LCMPAINTLVL_enum -{ - TC2_LCMPAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - TC2_LCMPAINTLVL_LO_gc = (0x01<<0), /* Low Level */ - TC2_LCMPAINTLVL_MED_gc = (0x02<<0), /* Medium Level */ - TC2_LCMPAINTLVL_HI_gc = (0x03<<0), /* High Level */ -} TC2_LCMPAINTLVL_t; - -/* Timer/Counter Command */ -typedef enum TC2_CMD_enum -{ - TC2_CMD_NONE_gc = (0x00<<2), /* No Command */ - TC2_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ - TC2_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ -} TC2_CMD_t; - -/* Timer/Counter Command */ -typedef enum TC2_CMDEN_enum -{ - TC2_CMDEN_LOW_gc = (0x01<<0), /* Low Byte Timer/Counter */ - TC2_CMDEN_HIGH_gc = (0x02<<0), /* High Byte Timer/Counter */ - TC2_CMDEN_BOTH_gc = (0x03<<0), /* Both Low Byte and High Byte Timer/Counters */ -} TC2_CMDEN_t; - - -/* --------------------------------------------------------------------------- -AWEX - Timer/Counter Advanced Waveform Extension --------------------------------------------------------------------------- -*/ - -/* Advanced Waveform Extension */ -typedef struct AWEX_struct -{ - register8_t CTRL; /* Control Register */ - register8_t reserved_0x01; - register8_t FDEMASK; /* Fault Detection Event Mask */ - register8_t FDCTRL; /* Fault Detection Control Register */ - register8_t STATUS; /* Status Register */ - register8_t STATUSSET; /* Status Set Register */ - register8_t DTBOTH; /* Dead Time Both Sides */ - register8_t DTBOTHBUF; /* Dead Time Both Sides Buffer */ - register8_t DTLS; /* Dead Time Low Side */ - register8_t DTHS; /* Dead Time High Side */ - register8_t DTLSBUF; /* Dead Time Low Side Buffer */ - register8_t DTHSBUF; /* Dead Time High Side Buffer */ - register8_t OUTOVEN; /* Output Override Enable */ -} AWEX_t; - -/* Fault Detect Action */ -typedef enum AWEX_FDACT_enum -{ - AWEX_FDACT_NONE_gc = (0x00<<0), /* No Fault Protection */ - AWEX_FDACT_CLEAROE_gc = (0x01<<0), /* Clear Output Enable Bits */ - AWEX_FDACT_CLEARDIR_gc = (0x03<<0), /* Clear I/O Port Direction Bits */ -} AWEX_FDACT_t; - - -/* --------------------------------------------------------------------------- -HIRES - Timer/Counter High-Resolution Extension --------------------------------------------------------------------------- -*/ - -/* High-Resolution Extension */ -typedef struct HIRES_struct -{ - register8_t CTRLA; /* Control Register */ -} HIRES_t; - -/* High Resolution Enable */ -typedef enum HIRES_HREN_enum -{ - HIRES_HREN_NONE_gc = (0x00<<0), /* No Fault Protection */ - HIRES_HREN_TC0_gc = (0x01<<0), /* Enable High Resolution on Timer/Counter 0 */ - HIRES_HREN_TC1_gc = (0x02<<0), /* Enable High Resolution on Timer/Counter 1 */ - HIRES_HREN_BOTH_gc = (0x03<<0), /* Enable High Resolution both Timer/Counters */ -} HIRES_HREN_t; - - -/* --------------------------------------------------------------------------- -USART - Universal Asynchronous Receiver-Transmitter --------------------------------------------------------------------------- -*/ - -/* Universal Synchronous/Asynchronous Receiver/Transmitter */ -typedef struct USART_struct -{ - register8_t DATA; /* Data Register */ - register8_t STATUS; /* Status Register */ - register8_t reserved_0x02; - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t CTRLC; /* Control Register C */ - register8_t BAUDCTRLA; /* Baud Rate Control Register A */ - register8_t BAUDCTRLB; /* Baud Rate Control Register B */ -} USART_t; - -/* Receive Complete Interrupt level */ -typedef enum USART_RXCINTLVL_enum -{ - USART_RXCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ - USART_RXCINTLVL_LO_gc = (0x01<<4), /* Low Level */ - USART_RXCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ - USART_RXCINTLVL_HI_gc = (0x03<<4), /* High Level */ -} USART_RXCINTLVL_t; - -/* Transmit Complete Interrupt level */ -typedef enum USART_TXCINTLVL_enum -{ - USART_TXCINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ - USART_TXCINTLVL_LO_gc = (0x01<<2), /* Low Level */ - USART_TXCINTLVL_MED_gc = (0x02<<2), /* Medium Level */ - USART_TXCINTLVL_HI_gc = (0x03<<2), /* High Level */ -} USART_TXCINTLVL_t; - -/* Data Register Empty Interrupt level */ -typedef enum USART_DREINTLVL_enum -{ - USART_DREINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - USART_DREINTLVL_LO_gc = (0x01<<0), /* Low Level */ - USART_DREINTLVL_MED_gc = (0x02<<0), /* Medium Level */ - USART_DREINTLVL_HI_gc = (0x03<<0), /* High Level */ -} USART_DREINTLVL_t; - -/* Character Size */ -typedef enum USART_CHSIZE_enum -{ - USART_CHSIZE_5BIT_gc = (0x00<<0), /* Character size: 5 bit */ - USART_CHSIZE_6BIT_gc = (0x01<<0), /* Character size: 6 bit */ - USART_CHSIZE_7BIT_gc = (0x02<<0), /* Character size: 7 bit */ - USART_CHSIZE_8BIT_gc = (0x03<<0), /* Character size: 8 bit */ - USART_CHSIZE_9BIT_gc = (0x07<<0), /* Character size: 9 bit */ -} USART_CHSIZE_t; - -/* Communication Mode */ -typedef enum USART_CMODE_enum -{ - USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6), /* Asynchronous Mode */ - USART_CMODE_SYNCHRONOUS_gc = (0x01<<6), /* Synchronous Mode */ - USART_CMODE_IRDA_gc = (0x02<<6), /* IrDA Mode */ - USART_CMODE_MSPI_gc = (0x03<<6), /* Master SPI Mode */ -} USART_CMODE_t; - -/* Parity Mode */ -typedef enum USART_PMODE_enum -{ - USART_PMODE_DISABLED_gc = (0x00<<4), /* No Parity */ - USART_PMODE_EVEN_gc = (0x02<<4), /* Even Parity */ - USART_PMODE_ODD_gc = (0x03<<4), /* Odd Parity */ -} USART_PMODE_t; - - -/* --------------------------------------------------------------------------- -SPI - Serial Peripheral Interface --------------------------------------------------------------------------- -*/ - -/* Serial Peripheral Interface */ -typedef struct SPI_struct -{ - register8_t CTRL; /* Control Register */ - register8_t INTCTRL; /* Interrupt Control Register */ - register8_t STATUS; /* Status Register */ - register8_t DATA; /* Data Register */ -} SPI_t; - -/* SPI Mode */ -typedef enum SPI_MODE_enum -{ - SPI_MODE_0_gc = (0x00<<2), /* SPI Mode 0 */ - SPI_MODE_1_gc = (0x01<<2), /* SPI Mode 1 */ - SPI_MODE_2_gc = (0x02<<2), /* SPI Mode 2 */ - SPI_MODE_3_gc = (0x03<<2), /* SPI Mode 3 */ -} SPI_MODE_t; - -/* Prescaler setting */ -typedef enum SPI_PRESCALER_enum -{ - SPI_PRESCALER_DIV4_gc = (0x00<<0), /* System Clock / 4 */ - SPI_PRESCALER_DIV16_gc = (0x01<<0), /* System Clock / 16 */ - SPI_PRESCALER_DIV64_gc = (0x02<<0), /* System Clock / 64 */ - SPI_PRESCALER_DIV128_gc = (0x03<<0), /* System Clock / 128 */ -} SPI_PRESCALER_t; - -/* Interrupt level */ -typedef enum SPI_INTLVL_enum -{ - SPI_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - SPI_INTLVL_LO_gc = (0x01<<0), /* Low Level */ - SPI_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ - SPI_INTLVL_HI_gc = (0x03<<0), /* High Level */ -} SPI_INTLVL_t; - - -/* --------------------------------------------------------------------------- -IRCOM - IR Communication Module --------------------------------------------------------------------------- -*/ - -/* IR Communication Module */ -typedef struct IRCOM_struct -{ - register8_t CTRL; /* Control Register */ - register8_t TXPLCTRL; /* IrDA Transmitter Pulse Length Control Register */ - register8_t RXPLCTRL; /* IrDA Receiver Pulse Length Control Register */ -} IRCOM_t; - -/* Event channel selection */ -typedef enum IRDA_EVSEL_enum -{ - IRDA_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ - IRDA_EVSEL_0_gc = (0x08<<0), /* Event Channel 0 */ - IRDA_EVSEL_1_gc = (0x09<<0), /* Event Channel 1 */ - IRDA_EVSEL_2_gc = (0x0A<<0), /* Event Channel 2 */ - IRDA_EVSEL_3_gc = (0x0B<<0), /* Event Channel 3 */ -} IRDA_EVSEL_t; - - -/* --------------------------------------------------------------------------- -FUSE - Fuses and Lockbits --------------------------------------------------------------------------- -*/ - -/* Fuses */ -typedef struct NVM_FUSES_struct -{ - register8_t reserved_0x00; - register8_t FUSEBYTE1; /* Watchdog Configuration */ - register8_t FUSEBYTE2; /* Reset Configuration */ - register8_t reserved_0x03; - register8_t FUSEBYTE4; /* Start-up Configuration */ - register8_t FUSEBYTE5; /* EESAVE and BOD Level */ -} NVM_FUSES_t; - -/* Boot Loader Section Reset Vector */ -typedef enum BOOTRST_enum -{ - BOOTRST_BOOTLDR_gc = (0x00<<6), /* Boot Loader Reset */ - BOOTRST_APPLICATION_gc = (0x01<<6), /* Application Reset */ -} BOOTRST_t; - -/* Timer Oscillator pin location */ -typedef enum TOSCSEL_enum -{ - TOSCSEL_ALTERNATE_gc = (0x00<<5), /* TOSC1 / TOSC2 on separate pins */ - TOSCSEL_XTAL_gc = (0x01<<5), /* TOSC1 / TOSC2 shared with XTAL1 / XTAL2 */ -} TOSCSEL_t; - -/* BOD operation */ -typedef enum BOD_enum -{ - BOD_SAMPLED_gc = (0x01<<0), /* BOD enabled in sampled mode */ - BOD_CONTINUOUS_gc = (0x02<<0), /* BOD enabled continuously */ - BOD_DISABLED_gc = (0x03<<0), /* BOD Disabled */ -} BOD_t; - -/* BOD operation */ -typedef enum BODACT_enum -{ - BODACT_SAMPLED_gc = (0x01<<4), /* BOD enabled in sampled mode */ - BODACT_CONTINUOUS_gc = (0x02<<4), /* BOD enabled continuously */ - BODACT_DISABLED_gc = (0x03<<4), /* BOD Disabled */ -} BODACT_t; - -/* Watchdog (Window) Timeout Period */ -typedef enum WD_enum -{ - WD_8CLK_gc = (0x00<<4), /* 8 cycles (8ms @ 3.3V) */ - WD_16CLK_gc = (0x01<<4), /* 16 cycles (16ms @ 3.3V) */ - WD_32CLK_gc = (0x02<<4), /* 32 cycles (32ms @ 3.3V) */ - WD_64CLK_gc = (0x03<<4), /* 64 cycles (64ms @ 3.3V) */ - WD_128CLK_gc = (0x04<<4), /* 128 cycles (0.125s @ 3.3V) */ - WD_256CLK_gc = (0x05<<4), /* 256 cycles (0.25s @ 3.3V) */ - WD_512CLK_gc = (0x06<<4), /* 512 cycles (0.5s @ 3.3V) */ - WD_1KCLK_gc = (0x07<<4), /* 1K cycles (1s @ 3.3V) */ - WD_2KCLK_gc = (0x08<<4), /* 2K cycles (2s @ 3.3V) */ - WD_4KCLK_gc = (0x09<<4), /* 4K cycles (4s @ 3.3V) */ - WD_8KCLK_gc = (0x0A<<4), /* 8K cycles (8s @ 3.3V) */ -} WD_t; - -/* Watchdog (Window) Timeout Period */ -typedef enum WDP_enum -{ - WDP_8CLK_gc = (0x00<<0), /* 8 cycles (8ms @ 3.3V) */ - WDP_16CLK_gc = (0x01<<0), /* 16 cycles (16ms @ 3.3V) */ - WDP_32CLK_gc = (0x02<<0), /* 32 cycles (32ms @ 3.3V) */ - WDP_64CLK_gc = (0x03<<0), /* 64 cycles (64ms @ 3.3V) */ - WDP_128CLK_gc = (0x04<<0), /* 128 cycles (0.125s @ 3.3V) */ - WDP_256CLK_gc = (0x05<<0), /* 256 cycles (0.25s @ 3.3V) */ - WDP_512CLK_gc = (0x06<<0), /* 512 cycles (0.5s @ 3.3V) */ - WDP_1KCLK_gc = (0x07<<0), /* 1K cycles (1s @ 3.3V) */ - WDP_2KCLK_gc = (0x08<<0), /* 2K cycles (2s @ 3.3V) */ - WDP_4KCLK_gc = (0x09<<0), /* 4K cycles (4s @ 3.3V) */ - WDP_8KCLK_gc = (0x0A<<0), /* 8K cycles (8s @ 3.3V) */ -} WDP_t; - -/* Start-up Time */ -typedef enum SUT_enum -{ - SUT_0MS_gc = (0x03<<2), /* 0 ms */ - SUT_4MS_gc = (0x01<<2), /* 4 ms */ - SUT_64MS_gc = (0x00<<2), /* 64 ms */ -} SUT_t; - -/* Brownout Detection Voltage Level */ -typedef enum BODLVL_enum -{ - BODLVL_1V6_gc = (0x07<<0), /* 1.6 V */ - BODLVL_1V8_gc = (0x06<<0), /* 1.8 V */ - BODLVL_2V0_gc = (0x05<<0), /* 2.0 V */ - BODLVL_2V2_gc = (0x04<<0), /* 2.2 V */ - BODLVL_2V4_gc = (0x03<<0), /* 2.4 V */ - BODLVL_2V6_gc = (0x02<<0), /* 2.6 V */ - BODLVL_2V8_gc = (0x01<<0), /* 2.8 V */ - BODLVL_3V0_gc = (0x00<<0), /* 3.0 V */ -} BODLVL_t; - - -/* --------------------------------------------------------------------------- -LOCKBIT - Fuses and Lockbits --------------------------------------------------------------------------- -*/ - -/* Lock Bits */ -typedef struct NVM_LOCKBITS_struct -{ - register8_t LOCK_BITS; /* Lock Bits (Changed from LOCKBITS to avoid avr-libc collision) */ -} NVM_LOCKBITS_t; - -/* Boot lock bits - boot setcion */ -typedef enum FUSE_BLBB_enum -{ - FUSE_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ - FUSE_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ - FUSE_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ - FUSE_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ -} FUSE_BLBB_t; - -/* Boot lock bits - application section */ -typedef enum FUSE_BLBA_enum -{ - FUSE_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ - FUSE_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ - FUSE_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ - FUSE_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ -} FUSE_BLBA_t; - -/* Boot lock bits - application table section */ -typedef enum FUSE_BLBAT_enum -{ - FUSE_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ - FUSE_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ - FUSE_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ - FUSE_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ -} FUSE_BLBAT_t; - -/* Lock bits */ -typedef enum FUSE_LB_enum -{ - FUSE_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ - FUSE_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ - FUSE_LB_NOLOCK_gc = (0x03<<0), /* No locks */ -} FUSE_LB_t; - - -/* --------------------------------------------------------------------------- -SIGROW - Signature Row --------------------------------------------------------------------------- -*/ - -/* Production Signatures */ -typedef struct NVM_PROD_SIGNATURES_struct -{ - register8_t RCOSC2M; /* RCOSC 2 MHz Calibration Value B */ - register8_t RCOSC2MA; /* RCOSC 2 MHz Calibration Value A */ - register8_t RCOSC32K; /* RCOSC 32.768 kHz Calibration Value */ - register8_t RCOSC32M; /* RCOSC 32 MHz Calibration Value B */ - register8_t RCOSC32MA; /* RCOSC 32 MHz Calibration Value A */ - register8_t reserved_0x05; - register8_t reserved_0x06; - register8_t reserved_0x07; - register8_t LOTNUM0; /* Lot Number Byte 0, ASCII */ - register8_t LOTNUM1; /* Lot Number Byte 1, ASCII */ - register8_t LOTNUM2; /* Lot Number Byte 2, ASCII */ - register8_t LOTNUM3; /* Lot Number Byte 3, ASCII */ - register8_t LOTNUM4; /* Lot Number Byte 4, ASCII */ - register8_t LOTNUM5; /* Lot Number Byte 5, ASCII */ - register8_t reserved_0x0E; - register8_t reserved_0x0F; - register8_t WAFNUM; /* Wafer Number */ - register8_t reserved_0x11; - register8_t COORDX0; /* Wafer Coordinate X Byte 0 */ - register8_t COORDX1; /* Wafer Coordinate X Byte 1 */ - register8_t COORDY0; /* Wafer Coordinate Y Byte 0 */ - register8_t COORDY1; /* Wafer Coordinate Y Byte 1 */ - register8_t reserved_0x16; - register8_t reserved_0x17; - register8_t reserved_0x18; - register8_t reserved_0x19; - register8_t USBCAL0; /* USB Calibration Byte 0 */ - register8_t USBCAL1; /* USB Calibration Byte 1 */ - register8_t USBRCOSC; /* USB RCOSC Calibration Value B */ - register8_t USBRCOSCA; /* USB RCOSC Calibration Value A */ - register8_t reserved_0x1E; - register8_t reserved_0x1F; - register8_t ADCACAL0; /* ADCA Calibration Byte 0 */ - register8_t ADCACAL1; /* ADCA Calibration Byte 1 */ - register8_t reserved_0x22; - register8_t reserved_0x23; - register8_t reserved_0x24; - register8_t reserved_0x25; - register8_t reserved_0x26; - register8_t reserved_0x27; - register8_t reserved_0x28; - register8_t reserved_0x29; - register8_t reserved_0x2A; - register8_t reserved_0x2B; - register8_t reserved_0x2C; - register8_t reserved_0x2D; - register8_t TEMPSENSE0; /* Temperature Sensor Calibration Byte 0 */ - register8_t TEMPSENSE1; /* Temperature Sensor Calibration Byte 1 */ - register8_t reserved_0x30; - register8_t reserved_0x31; - register8_t reserved_0x32; - register8_t reserved_0x33; - register8_t reserved_0x34; - register8_t reserved_0x35; - register8_t reserved_0x36; - register8_t reserved_0x37; - register8_t reserved_0x38; - register8_t reserved_0x39; - register8_t reserved_0x3A; - register8_t reserved_0x3B; - register8_t reserved_0x3C; - register8_t reserved_0x3D; - register8_t reserved_0x3E; - register8_t reserved_0x3F; -} NVM_PROD_SIGNATURES_t; - -/* -========================================================================== -IO Module Instances. Mapped to memory. -========================================================================== -*/ - -#define VPORT0 (*(VPORT_t *) 0x0010) /* Virtual Port */ -#define VPORT1 (*(VPORT_t *) 0x0014) /* Virtual Port */ -#define VPORT2 (*(VPORT_t *) 0x0018) /* Virtual Port */ -#define VPORT3 (*(VPORT_t *) 0x001C) /* Virtual Port */ -#define OCD (*(OCD_t *) 0x002E) /* On-Chip Debug System */ -#define CLK (*(CLK_t *) 0x0040) /* Clock System */ -#define SLEEP (*(SLEEP_t *) 0x0048) /* Sleep Controller */ -#define OSC (*(OSC_t *) 0x0050) /* Oscillator */ -#define DFLLRC32M (*(DFLL_t *) 0x0060) /* DFLL */ -#define DFLLRC2M (*(DFLL_t *) 0x0068) /* DFLL */ -#define PR (*(PR_t *) 0x0070) /* Power Reduction */ -#define RST (*(RST_t *) 0x0078) /* Reset */ -#define WDT (*(WDT_t *) 0x0080) /* Watch-Dog Timer */ -#define MCU (*(MCU_t *) 0x0090) /* MCU Control */ -#define PMIC (*(PMIC_t *) 0x00A0) /* Programmable Multi-level Interrupt Controller */ -#define PORTCFG (*(PORTCFG_t *) 0x00B0) /* I/O port Configuration */ -#define CRC (*(CRC_t *) 0x00D0) /* Cyclic Redundancy Checker */ -#define EVSYS (*(EVSYS_t *) 0x0180) /* Event System */ -#define NVM (*(NVM_t *) 0x01C0) /* Non-volatile Memory Controller */ -#define ADCA (*(ADC_t *) 0x0200) /* Analog-to-Digital Converter */ -#define ACA (*(AC_t *) 0x0380) /* Analog Comparator */ -#define RTC (*(RTC_t *) 0x0400) /* Real-Time Counter */ -#define TWIC (*(TWI_t *) 0x0480) /* Two-Wire Interface */ -#define TWIE (*(TWI_t *) 0x04A0) /* Two-Wire Interface */ -#define USB (*(USB_t *) 0x04C0) /* Universal Serial Bus */ -#define PORTA (*(PORT_t *) 0x0600) /* I/O Ports */ -#define PORTB (*(PORT_t *) 0x0620) /* I/O Ports */ -#define PORTC (*(PORT_t *) 0x0640) /* I/O Ports */ -#define PORTD (*(PORT_t *) 0x0660) /* I/O Ports */ -#define PORTE (*(PORT_t *) 0x0680) /* I/O Ports */ -#define PORTR (*(PORT_t *) 0x07E0) /* I/O Ports */ -#define TCC0 (*(TC0_t *) 0x0800) /* 16-bit Timer/Counter 0 */ -#define TCC2 (*(TC2_t *) 0x0800) /* 16-bit Timer/Counter type 2 */ -#define TCC1 (*(TC1_t *) 0x0840) /* 16-bit Timer/Counter 1 */ -#define AWEXC (*(AWEX_t *) 0x0880) /* Advanced Waveform Extension */ -#define HIRESC (*(HIRES_t *) 0x0890) /* High-Resolution Extension */ -#define USARTC0 (*(USART_t *) 0x08A0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ -#define USARTC1 (*(USART_t *) 0x08B0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ -#define SPIC (*(SPI_t *) 0x08C0) /* Serial Peripheral Interface */ -#define IRCOM (*(IRCOM_t *) 0x08F8) /* IR Communication Module */ -#define TCD0 (*(TC0_t *) 0x0900) /* 16-bit Timer/Counter 0 */ -#define TCD2 (*(TC2_t *) 0x0900) /* 16-bit Timer/Counter type 2 */ -#define USARTD0 (*(USART_t *) 0x09A0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ -#define SPID (*(SPI_t *) 0x09C0) /* Serial Peripheral Interface */ -#define TCE0 (*(TC0_t *) 0x0A00) /* 16-bit Timer/Counter 0 */ - - -#endif /* !defined (__ASSEMBLER__) */ - - -/* ========== Flattened fully qualified IO register names ========== */ - -/* GPIO - General Purpose IO Registers */ -#define GPIO_GPIOR0 _SFR_MEM8(0x0000) -#define GPIO_GPIOR1 _SFR_MEM8(0x0001) -#define GPIO_GPIOR2 _SFR_MEM8(0x0002) -#define GPIO_GPIOR3 _SFR_MEM8(0x0003) - -/* Deprecated */ -#define GPIO_GPIO0 _SFR_MEM8(0x0000) -#define GPIO_GPIO1 _SFR_MEM8(0x0001) -#define GPIO_GPIO2 _SFR_MEM8(0x0002) -#define GPIO_GPIO3 _SFR_MEM8(0x0003) - -/* NVM_FUSES - Fuses */ -#define FUSE_FUSEBYTE1 _SFR_MEM8(0x0001) -#define FUSE_FUSEBYTE2 _SFR_MEM8(0x0002) -#define FUSE_FUSEBYTE4 _SFR_MEM8(0x0004) -#define FUSE_FUSEBYTE5 _SFR_MEM8(0x0005) - -/* NVM_LOCKBITS - Lock Bits */ -#define LOCKBIT_LOCKBITS _SFR_MEM8(0x0000) - -/* NVM_PROD_SIGNATURES - Production Signatures */ -#define PRODSIGNATURES_RCOSC2M _SFR_MEM8(0x0000) -#define PRODSIGNATURES_RCOSC2MA _SFR_MEM8(0x0001) -#define PRODSIGNATURES_RCOSC32K _SFR_MEM8(0x0002) -#define PRODSIGNATURES_RCOSC32M _SFR_MEM8(0x0003) -#define PRODSIGNATURES_RCOSC32MA _SFR_MEM8(0x0004) -#define PRODSIGNATURES_LOTNUM0 _SFR_MEM8(0x0008) -#define PRODSIGNATURES_LOTNUM1 _SFR_MEM8(0x0009) -#define PRODSIGNATURES_LOTNUM2 _SFR_MEM8(0x000A) -#define PRODSIGNATURES_LOTNUM3 _SFR_MEM8(0x000B) -#define PRODSIGNATURES_LOTNUM4 _SFR_MEM8(0x000C) -#define PRODSIGNATURES_LOTNUM5 _SFR_MEM8(0x000D) -#define PRODSIGNATURES_WAFNUM _SFR_MEM8(0x0010) -#define PRODSIGNATURES_COORDX0 _SFR_MEM8(0x0012) -#define PRODSIGNATURES_COORDX1 _SFR_MEM8(0x0013) -#define PRODSIGNATURES_COORDY0 _SFR_MEM8(0x0014) -#define PRODSIGNATURES_COORDY1 _SFR_MEM8(0x0015) -#define PRODSIGNATURES_USBCAL0 _SFR_MEM8(0x001A) -#define PRODSIGNATURES_USBCAL1 _SFR_MEM8(0x001B) -#define PRODSIGNATURES_USBRCOSC _SFR_MEM8(0x001C) -#define PRODSIGNATURES_USBRCOSCA _SFR_MEM8(0x001D) -#define PRODSIGNATURES_ADCACAL0 _SFR_MEM8(0x0020) -#define PRODSIGNATURES_ADCACAL1 _SFR_MEM8(0x0021) -#define PRODSIGNATURES_TEMPSENSE0 _SFR_MEM8(0x002E) -#define PRODSIGNATURES_TEMPSENSE1 _SFR_MEM8(0x002F) - -/* VPORT - Virtual Port */ -#define VPORT0_DIR _SFR_MEM8(0x0010) -#define VPORT0_OUT _SFR_MEM8(0x0011) -#define VPORT0_IN _SFR_MEM8(0x0012) -#define VPORT0_INTFLAGS _SFR_MEM8(0x0013) - -/* VPORT - Virtual Port */ -#define VPORT1_DIR _SFR_MEM8(0x0014) -#define VPORT1_OUT _SFR_MEM8(0x0015) -#define VPORT1_IN _SFR_MEM8(0x0016) -#define VPORT1_INTFLAGS _SFR_MEM8(0x0017) - -/* VPORT - Virtual Port */ -#define VPORT2_DIR _SFR_MEM8(0x0018) -#define VPORT2_OUT _SFR_MEM8(0x0019) -#define VPORT2_IN _SFR_MEM8(0x001A) -#define VPORT2_INTFLAGS _SFR_MEM8(0x001B) - -/* VPORT - Virtual Port */ -#define VPORT3_DIR _SFR_MEM8(0x001C) -#define VPORT3_OUT _SFR_MEM8(0x001D) -#define VPORT3_IN _SFR_MEM8(0x001E) -#define VPORT3_INTFLAGS _SFR_MEM8(0x001F) - -/* OCD - On-Chip Debug System */ -#define OCD_OCDR0 _SFR_MEM8(0x002E) -#define OCD_OCDR1 _SFR_MEM8(0x002F) - -/* CPU - CPU registers */ -#define CPU_CCP _SFR_MEM8(0x0034) -#define CPU_RAMPD _SFR_MEM8(0x0038) -#define CPU_RAMPX _SFR_MEM8(0x0039) -#define CPU_RAMPY _SFR_MEM8(0x003A) -#define CPU_RAMPZ _SFR_MEM8(0x003B) -#define CPU_EIND _SFR_MEM8(0x003C) -#define CPU_SPL _SFR_MEM8(0x003D) -#define CPU_SPH _SFR_MEM8(0x003E) -#define CPU_SREG _SFR_MEM8(0x003F) - -/* CLK - Clock System */ -#define CLK_CTRL _SFR_MEM8(0x0040) -#define CLK_PSCTRL _SFR_MEM8(0x0041) -#define CLK_LOCK _SFR_MEM8(0x0042) -#define CLK_RTCCTRL _SFR_MEM8(0x0043) -#define CLK_USBCTRL _SFR_MEM8(0x0044) - -/* SLEEP - Sleep Controller */ -#define SLEEP_CTRL _SFR_MEM8(0x0048) - -/* OSC - Oscillator */ -#define OSC_CTRL _SFR_MEM8(0x0050) -#define OSC_STATUS _SFR_MEM8(0x0051) -#define OSC_XOSCCTRL _SFR_MEM8(0x0052) -#define OSC_XOSCFAIL _SFR_MEM8(0x0053) -#define OSC_RC32KCAL _SFR_MEM8(0x0054) -#define OSC_PLLCTRL _SFR_MEM8(0x0055) -#define OSC_DFLLCTRL _SFR_MEM8(0x0056) - -/* DFLL - DFLL */ -#define DFLLRC32M_CTRL _SFR_MEM8(0x0060) -#define DFLLRC32M_CALA _SFR_MEM8(0x0062) -#define DFLLRC32M_CALB _SFR_MEM8(0x0063) -#define DFLLRC32M_COMP0 _SFR_MEM8(0x0064) -#define DFLLRC32M_COMP1 _SFR_MEM8(0x0065) -#define DFLLRC32M_COMP2 _SFR_MEM8(0x0066) - -/* DFLL - DFLL */ -#define DFLLRC2M_CTRL _SFR_MEM8(0x0068) -#define DFLLRC2M_CALA _SFR_MEM8(0x006A) -#define DFLLRC2M_CALB _SFR_MEM8(0x006B) -#define DFLLRC2M_COMP0 _SFR_MEM8(0x006C) -#define DFLLRC2M_COMP1 _SFR_MEM8(0x006D) -#define DFLLRC2M_COMP2 _SFR_MEM8(0x006E) - -/* PR - Power Reduction */ -#define PR_PRGEN _SFR_MEM8(0x0070) -#define PR_PRPA _SFR_MEM8(0x0071) -#define PR_PRPC _SFR_MEM8(0x0073) -#define PR_PRPD _SFR_MEM8(0x0074) -#define PR_PRPE _SFR_MEM8(0x0075) -#define PR_PRPF _SFR_MEM8(0x0076) - -/* RST - Reset */ -#define RST_STATUS _SFR_MEM8(0x0078) -#define RST_CTRL _SFR_MEM8(0x0079) - -/* WDT - Watch-Dog Timer */ -#define WDT_CTRL _SFR_MEM8(0x0080) -#define WDT_WINCTRL _SFR_MEM8(0x0081) -#define WDT_STATUS _SFR_MEM8(0x0082) - -/* MCU - MCU Control */ -#define MCU_DEVID0 _SFR_MEM8(0x0090) -#define MCU_DEVID1 _SFR_MEM8(0x0091) -#define MCU_DEVID2 _SFR_MEM8(0x0092) -#define MCU_REVID _SFR_MEM8(0x0093) -#define MCU_ANAINIT _SFR_MEM8(0x0097) -#define MCU_EVSYSLOCK _SFR_MEM8(0x0098) -#define MCU_AWEXLOCK _SFR_MEM8(0x0099) - -/* PMIC - Programmable Multi-level Interrupt Controller */ -#define PMIC_STATUS _SFR_MEM8(0x00A0) -#define PMIC_INTPRI _SFR_MEM8(0x00A1) -#define PMIC_CTRL _SFR_MEM8(0x00A2) - -/* PORTCFG - I/O port Configuration */ -#define PORTCFG_MPCMASK _SFR_MEM8(0x00B0) -#define PORTCFG_VPCTRLA _SFR_MEM8(0x00B2) -#define PORTCFG_VPCTRLB _SFR_MEM8(0x00B3) -#define PORTCFG_CLKEVOUT _SFR_MEM8(0x00B4) -#define PORTCFG_EVOUTSEL _SFR_MEM8(0x00B6) - -/* CRC - Cyclic Redundancy Checker */ -#define CRC_CTRL _SFR_MEM8(0x00D0) -#define CRC_STATUS _SFR_MEM8(0x00D1) -#define CRC_DATAIN _SFR_MEM8(0x00D3) -#define CRC_CHECKSUM0 _SFR_MEM8(0x00D4) -#define CRC_CHECKSUM1 _SFR_MEM8(0x00D5) -#define CRC_CHECKSUM2 _SFR_MEM8(0x00D6) -#define CRC_CHECKSUM3 _SFR_MEM8(0x00D7) - -/* EVSYS - Event System */ -#define EVSYS_CH0MUX _SFR_MEM8(0x0180) -#define EVSYS_CH1MUX _SFR_MEM8(0x0181) -#define EVSYS_CH2MUX _SFR_MEM8(0x0182) -#define EVSYS_CH3MUX _SFR_MEM8(0x0183) -#define EVSYS_CH0CTRL _SFR_MEM8(0x0188) -#define EVSYS_CH1CTRL _SFR_MEM8(0x0189) -#define EVSYS_CH2CTRL _SFR_MEM8(0x018A) -#define EVSYS_CH3CTRL _SFR_MEM8(0x018B) -#define EVSYS_STROBE _SFR_MEM8(0x0190) -#define EVSYS_DATA _SFR_MEM8(0x0191) - -/* NVM - Non-volatile Memory Controller */ -#define NVM_ADDR0 _SFR_MEM8(0x01C0) -#define NVM_ADDR1 _SFR_MEM8(0x01C1) -#define NVM_ADDR2 _SFR_MEM8(0x01C2) -#define NVM_DATA0 _SFR_MEM8(0x01C4) -#define NVM_DATA1 _SFR_MEM8(0x01C5) -#define NVM_DATA2 _SFR_MEM8(0x01C6) -#define NVM_CMD _SFR_MEM8(0x01CA) -#define NVM_CTRLA _SFR_MEM8(0x01CB) -#define NVM_CTRLB _SFR_MEM8(0x01CC) -#define NVM_INTCTRL _SFR_MEM8(0x01CD) -#define NVM_STATUS _SFR_MEM8(0x01CF) -#define NVM_LOCKBITS _SFR_MEM8(0x01D0) - -/* ADC - Analog-to-Digital Converter */ -#define ADCA_CTRLA _SFR_MEM8(0x0200) -#define ADCA_CTRLB _SFR_MEM8(0x0201) -#define ADCA_REFCTRL _SFR_MEM8(0x0202) -#define ADCA_EVCTRL _SFR_MEM8(0x0203) -#define ADCA_PRESCALER _SFR_MEM8(0x0204) -#define ADCA_INTFLAGS _SFR_MEM8(0x0206) -#define ADCA_TEMP _SFR_MEM8(0x0207) -#define ADCA_CAL _SFR_MEM16(0x020C) -#define ADCA_CH0RES _SFR_MEM16(0x0210) -#define ADCA_CMP _SFR_MEM16(0x0218) -#define ADCA_CH0_CTRL _SFR_MEM8(0x0220) -#define ADCA_CH0_MUXCTRL _SFR_MEM8(0x0221) -#define ADCA_CH0_INTCTRL _SFR_MEM8(0x0222) -#define ADCA_CH0_INTFLAGS _SFR_MEM8(0x0223) -#define ADCA_CH0_RES _SFR_MEM16(0x0224) -#define ADCA_CH0_SCAN _SFR_MEM8(0x0226) - -/* AC - Analog Comparator */ -#define ACA_AC0CTRL _SFR_MEM8(0x0380) -#define ACA_AC1CTRL _SFR_MEM8(0x0381) -#define ACA_AC0MUXCTRL _SFR_MEM8(0x0382) -#define ACA_AC1MUXCTRL _SFR_MEM8(0x0383) -#define ACA_CTRLA _SFR_MEM8(0x0384) -#define ACA_CTRLB _SFR_MEM8(0x0385) -#define ACA_WINCTRL _SFR_MEM8(0x0386) -#define ACA_STATUS _SFR_MEM8(0x0387) - -/* RTC - Real-Time Counter */ -#define RTC_CTRL _SFR_MEM8(0x0400) -#define RTC_STATUS _SFR_MEM8(0x0401) -#define RTC_INTCTRL _SFR_MEM8(0x0402) -#define RTC_INTFLAGS _SFR_MEM8(0x0403) -#define RTC_TEMP _SFR_MEM8(0x0404) -#define RTC_CNT _SFR_MEM16(0x0408) -#define RTC_PER _SFR_MEM16(0x040A) -#define RTC_COMP _SFR_MEM16(0x040C) - -/* TWI - Two-Wire Interface */ -#define TWIC_CTRL _SFR_MEM8(0x0480) -#define TWIC_MASTER_CTRLA _SFR_MEM8(0x0481) -#define TWIC_MASTER_CTRLB _SFR_MEM8(0x0482) -#define TWIC_MASTER_CTRLC _SFR_MEM8(0x0483) -#define TWIC_MASTER_STATUS _SFR_MEM8(0x0484) -#define TWIC_MASTER_BAUD _SFR_MEM8(0x0485) -#define TWIC_MASTER_ADDR _SFR_MEM8(0x0486) -#define TWIC_MASTER_DATA _SFR_MEM8(0x0487) -#define TWIC_SLAVE_CTRLA _SFR_MEM8(0x0488) -#define TWIC_SLAVE_CTRLB _SFR_MEM8(0x0489) -#define TWIC_SLAVE_STATUS _SFR_MEM8(0x048A) -#define TWIC_SLAVE_ADDR _SFR_MEM8(0x048B) -#define TWIC_SLAVE_DATA _SFR_MEM8(0x048C) -#define TWIC_SLAVE_ADDRMASK _SFR_MEM8(0x048D) - -/* TWI - Two-Wire Interface */ -#define TWIE_CTRL _SFR_MEM8(0x04A0) -#define TWIE_MASTER_CTRLA _SFR_MEM8(0x04A1) -#define TWIE_MASTER_CTRLB _SFR_MEM8(0x04A2) -#define TWIE_MASTER_CTRLC _SFR_MEM8(0x04A3) -#define TWIE_MASTER_STATUS _SFR_MEM8(0x04A4) -#define TWIE_MASTER_BAUD _SFR_MEM8(0x04A5) -#define TWIE_MASTER_ADDR _SFR_MEM8(0x04A6) -#define TWIE_MASTER_DATA _SFR_MEM8(0x04A7) -#define TWIE_SLAVE_CTRLA _SFR_MEM8(0x04A8) -#define TWIE_SLAVE_CTRLB _SFR_MEM8(0x04A9) -#define TWIE_SLAVE_STATUS _SFR_MEM8(0x04AA) -#define TWIE_SLAVE_ADDR _SFR_MEM8(0x04AB) -#define TWIE_SLAVE_DATA _SFR_MEM8(0x04AC) -#define TWIE_SLAVE_ADDRMASK _SFR_MEM8(0x04AD) - -/* USB - Universal Serial Bus */ -#define USB_CTRLA _SFR_MEM8(0x04C0) -#define USB_CTRLB _SFR_MEM8(0x04C1) -#define USB_STATUS _SFR_MEM8(0x04C2) -#define USB_ADDR _SFR_MEM8(0x04C3) -#define USB_FIFOWP _SFR_MEM8(0x04C4) -#define USB_FIFORP _SFR_MEM8(0x04C5) -#define USB_EPPTR _SFR_MEM16(0x04C6) -#define USB_INTCTRLA _SFR_MEM8(0x04C8) -#define USB_INTCTRLB _SFR_MEM8(0x04C9) -#define USB_INTFLAGSACLR _SFR_MEM8(0x04CA) -#define USB_INTFLAGSASET _SFR_MEM8(0x04CB) -#define USB_INTFLAGSBCLR _SFR_MEM8(0x04CC) -#define USB_INTFLAGSBSET _SFR_MEM8(0x04CD) -#define USB_CAL0 _SFR_MEM8(0x04FA) -#define USB_CAL1 _SFR_MEM8(0x04FB) - -/* PORT - I/O Ports */ -#define PORTA_DIR _SFR_MEM8(0x0600) -#define PORTA_DIRSET _SFR_MEM8(0x0601) -#define PORTA_DIRCLR _SFR_MEM8(0x0602) -#define PORTA_DIRTGL _SFR_MEM8(0x0603) -#define PORTA_OUT _SFR_MEM8(0x0604) -#define PORTA_OUTSET _SFR_MEM8(0x0605) -#define PORTA_OUTCLR _SFR_MEM8(0x0606) -#define PORTA_OUTTGL _SFR_MEM8(0x0607) -#define PORTA_IN _SFR_MEM8(0x0608) -#define PORTA_INTCTRL _SFR_MEM8(0x0609) -#define PORTA_INT0MASK _SFR_MEM8(0x060A) -#define PORTA_INT1MASK _SFR_MEM8(0x060B) -#define PORTA_INTFLAGS _SFR_MEM8(0x060C) -#define PORTA_REMAP _SFR_MEM8(0x060E) -#define PORTA_PIN0CTRL _SFR_MEM8(0x0610) -#define PORTA_PIN1CTRL _SFR_MEM8(0x0611) -#define PORTA_PIN2CTRL _SFR_MEM8(0x0612) -#define PORTA_PIN3CTRL _SFR_MEM8(0x0613) -#define PORTA_PIN4CTRL _SFR_MEM8(0x0614) -#define PORTA_PIN5CTRL _SFR_MEM8(0x0615) -#define PORTA_PIN6CTRL _SFR_MEM8(0x0616) -#define PORTA_PIN7CTRL _SFR_MEM8(0x0617) - -/* PORT - I/O Ports */ -#define PORTB_DIR _SFR_MEM8(0x0620) -#define PORTB_DIRSET _SFR_MEM8(0x0621) -#define PORTB_DIRCLR _SFR_MEM8(0x0622) -#define PORTB_DIRTGL _SFR_MEM8(0x0623) -#define PORTB_OUT _SFR_MEM8(0x0624) -#define PORTB_OUTSET _SFR_MEM8(0x0625) -#define PORTB_OUTCLR _SFR_MEM8(0x0626) -#define PORTB_OUTTGL _SFR_MEM8(0x0627) -#define PORTB_IN _SFR_MEM8(0x0628) -#define PORTB_INTCTRL _SFR_MEM8(0x0629) -#define PORTB_INT0MASK _SFR_MEM8(0x062A) -#define PORTB_INT1MASK _SFR_MEM8(0x062B) -#define PORTB_INTFLAGS _SFR_MEM8(0x062C) -#define PORTB_REMAP _SFR_MEM8(0x062E) -#define PORTB_PIN0CTRL _SFR_MEM8(0x0630) -#define PORTB_PIN1CTRL _SFR_MEM8(0x0631) -#define PORTB_PIN2CTRL _SFR_MEM8(0x0632) -#define PORTB_PIN3CTRL _SFR_MEM8(0x0633) -#define PORTB_PIN4CTRL _SFR_MEM8(0x0634) -#define PORTB_PIN5CTRL _SFR_MEM8(0x0635) -#define PORTB_PIN6CTRL _SFR_MEM8(0x0636) -#define PORTB_PIN7CTRL _SFR_MEM8(0x0637) - -/* PORT - I/O Ports */ -#define PORTC_DIR _SFR_MEM8(0x0640) -#define PORTC_DIRSET _SFR_MEM8(0x0641) -#define PORTC_DIRCLR _SFR_MEM8(0x0642) -#define PORTC_DIRTGL _SFR_MEM8(0x0643) -#define PORTC_OUT _SFR_MEM8(0x0644) -#define PORTC_OUTSET _SFR_MEM8(0x0645) -#define PORTC_OUTCLR _SFR_MEM8(0x0646) -#define PORTC_OUTTGL _SFR_MEM8(0x0647) -#define PORTC_IN _SFR_MEM8(0x0648) -#define PORTC_INTCTRL _SFR_MEM8(0x0649) -#define PORTC_INT0MASK _SFR_MEM8(0x064A) -#define PORTC_INT1MASK _SFR_MEM8(0x064B) -#define PORTC_INTFLAGS _SFR_MEM8(0x064C) -#define PORTC_REMAP _SFR_MEM8(0x064E) -#define PORTC_PIN0CTRL _SFR_MEM8(0x0650) -#define PORTC_PIN1CTRL _SFR_MEM8(0x0651) -#define PORTC_PIN2CTRL _SFR_MEM8(0x0652) -#define PORTC_PIN3CTRL _SFR_MEM8(0x0653) -#define PORTC_PIN4CTRL _SFR_MEM8(0x0654) -#define PORTC_PIN5CTRL _SFR_MEM8(0x0655) -#define PORTC_PIN6CTRL _SFR_MEM8(0x0656) -#define PORTC_PIN7CTRL _SFR_MEM8(0x0657) - -/* PORT - I/O Ports */ -#define PORTD_DIR _SFR_MEM8(0x0660) -#define PORTD_DIRSET _SFR_MEM8(0x0661) -#define PORTD_DIRCLR _SFR_MEM8(0x0662) -#define PORTD_DIRTGL _SFR_MEM8(0x0663) -#define PORTD_OUT _SFR_MEM8(0x0664) -#define PORTD_OUTSET _SFR_MEM8(0x0665) -#define PORTD_OUTCLR _SFR_MEM8(0x0666) -#define PORTD_OUTTGL _SFR_MEM8(0x0667) -#define PORTD_IN _SFR_MEM8(0x0668) -#define PORTD_INTCTRL _SFR_MEM8(0x0669) -#define PORTD_INT0MASK _SFR_MEM8(0x066A) -#define PORTD_INT1MASK _SFR_MEM8(0x066B) -#define PORTD_INTFLAGS _SFR_MEM8(0x066C) -#define PORTD_REMAP _SFR_MEM8(0x066E) -#define PORTD_PIN0CTRL _SFR_MEM8(0x0670) -#define PORTD_PIN1CTRL _SFR_MEM8(0x0671) -#define PORTD_PIN2CTRL _SFR_MEM8(0x0672) -#define PORTD_PIN3CTRL _SFR_MEM8(0x0673) -#define PORTD_PIN4CTRL _SFR_MEM8(0x0674) -#define PORTD_PIN5CTRL _SFR_MEM8(0x0675) -#define PORTD_PIN6CTRL _SFR_MEM8(0x0676) -#define PORTD_PIN7CTRL _SFR_MEM8(0x0677) - -/* PORT - I/O Ports */ -#define PORTE_DIR _SFR_MEM8(0x0680) -#define PORTE_DIRSET _SFR_MEM8(0x0681) -#define PORTE_DIRCLR _SFR_MEM8(0x0682) -#define PORTE_DIRTGL _SFR_MEM8(0x0683) -#define PORTE_OUT _SFR_MEM8(0x0684) -#define PORTE_OUTSET _SFR_MEM8(0x0685) -#define PORTE_OUTCLR _SFR_MEM8(0x0686) -#define PORTE_OUTTGL _SFR_MEM8(0x0687) -#define PORTE_IN _SFR_MEM8(0x0688) -#define PORTE_INTCTRL _SFR_MEM8(0x0689) -#define PORTE_INT0MASK _SFR_MEM8(0x068A) -#define PORTE_INT1MASK _SFR_MEM8(0x068B) -#define PORTE_INTFLAGS _SFR_MEM8(0x068C) -#define PORTE_REMAP _SFR_MEM8(0x068E) -#define PORTE_PIN0CTRL _SFR_MEM8(0x0690) -#define PORTE_PIN1CTRL _SFR_MEM8(0x0691) -#define PORTE_PIN2CTRL _SFR_MEM8(0x0692) -#define PORTE_PIN3CTRL _SFR_MEM8(0x0693) -#define PORTE_PIN4CTRL _SFR_MEM8(0x0694) -#define PORTE_PIN5CTRL _SFR_MEM8(0x0695) -#define PORTE_PIN6CTRL _SFR_MEM8(0x0696) -#define PORTE_PIN7CTRL _SFR_MEM8(0x0697) - -/* PORT - I/O Ports */ -#define PORTR_DIR _SFR_MEM8(0x07E0) -#define PORTR_DIRSET _SFR_MEM8(0x07E1) -#define PORTR_DIRCLR _SFR_MEM8(0x07E2) -#define PORTR_DIRTGL _SFR_MEM8(0x07E3) -#define PORTR_OUT _SFR_MEM8(0x07E4) -#define PORTR_OUTSET _SFR_MEM8(0x07E5) -#define PORTR_OUTCLR _SFR_MEM8(0x07E6) -#define PORTR_OUTTGL _SFR_MEM8(0x07E7) -#define PORTR_IN _SFR_MEM8(0x07E8) -#define PORTR_INTCTRL _SFR_MEM8(0x07E9) -#define PORTR_INT0MASK _SFR_MEM8(0x07EA) -#define PORTR_INT1MASK _SFR_MEM8(0x07EB) -#define PORTR_INTFLAGS _SFR_MEM8(0x07EC) -#define PORTR_REMAP _SFR_MEM8(0x07EE) -#define PORTR_PIN0CTRL _SFR_MEM8(0x07F0) -#define PORTR_PIN1CTRL _SFR_MEM8(0x07F1) -#define PORTR_PIN2CTRL _SFR_MEM8(0x07F2) -#define PORTR_PIN3CTRL _SFR_MEM8(0x07F3) -#define PORTR_PIN4CTRL _SFR_MEM8(0x07F4) -#define PORTR_PIN5CTRL _SFR_MEM8(0x07F5) -#define PORTR_PIN6CTRL _SFR_MEM8(0x07F6) -#define PORTR_PIN7CTRL _SFR_MEM8(0x07F7) - -/* TC0 - 16-bit Timer/Counter 0 */ -#define TCC0_CTRLA _SFR_MEM8(0x0800) -#define TCC0_CTRLB _SFR_MEM8(0x0801) -#define TCC0_CTRLC _SFR_MEM8(0x0802) -#define TCC0_CTRLD _SFR_MEM8(0x0803) -#define TCC0_CTRLE _SFR_MEM8(0x0804) -#define TCC0_INTCTRLA _SFR_MEM8(0x0806) -#define TCC0_INTCTRLB _SFR_MEM8(0x0807) -#define TCC0_CTRLFCLR _SFR_MEM8(0x0808) -#define TCC0_CTRLFSET _SFR_MEM8(0x0809) -#define TCC0_CTRLGCLR _SFR_MEM8(0x080A) -#define TCC0_CTRLGSET _SFR_MEM8(0x080B) -#define TCC0_INTFLAGS _SFR_MEM8(0x080C) -#define TCC0_TEMP _SFR_MEM8(0x080F) -#define TCC0_CNT _SFR_MEM16(0x0820) -#define TCC0_PER _SFR_MEM16(0x0826) -#define TCC0_CCA _SFR_MEM16(0x0828) -#define TCC0_CCB _SFR_MEM16(0x082A) -#define TCC0_CCC _SFR_MEM16(0x082C) -#define TCC0_CCD _SFR_MEM16(0x082E) -#define TCC0_PERBUF _SFR_MEM16(0x0836) -#define TCC0_CCABUF _SFR_MEM16(0x0838) -#define TCC0_CCBBUF _SFR_MEM16(0x083A) -#define TCC0_CCCBUF _SFR_MEM16(0x083C) -#define TCC0_CCDBUF _SFR_MEM16(0x083E) - -/* TC2 - 16-bit Timer/Counter type 2 */ -#define TCC2_CTRLA _SFR_MEM8(0x0800) -#define TCC2_CTRLB _SFR_MEM8(0x0801) -#define TCC2_CTRLC _SFR_MEM8(0x0802) -#define TCC2_CTRLE _SFR_MEM8(0x0804) -#define TCC2_INTCTRLA _SFR_MEM8(0x0806) -#define TCC2_INTCTRLB _SFR_MEM8(0x0807) -#define TCC2_CTRLF _SFR_MEM8(0x0809) -#define TCC2_INTFLAGS _SFR_MEM8(0x080C) -#define TCC2_LCNT _SFR_MEM8(0x0820) -#define TCC2_HCNT _SFR_MEM8(0x0821) -#define TCC2_LPER _SFR_MEM8(0x0826) -#define TCC2_HPER _SFR_MEM8(0x0827) -#define TCC2_LCMPA _SFR_MEM8(0x0828) -#define TCC2_HCMPA _SFR_MEM8(0x0829) -#define TCC2_LCMPB _SFR_MEM8(0x082A) -#define TCC2_HCMPB _SFR_MEM8(0x082B) -#define TCC2_LCMPC _SFR_MEM8(0x082C) -#define TCC2_HCMPC _SFR_MEM8(0x082D) -#define TCC2_LCMPD _SFR_MEM8(0x082E) -#define TCC2_HCMPD _SFR_MEM8(0x082F) - -/* TC1 - 16-bit Timer/Counter 1 */ -#define TCC1_CTRLA _SFR_MEM8(0x0840) -#define TCC1_CTRLB _SFR_MEM8(0x0841) -#define TCC1_CTRLC _SFR_MEM8(0x0842) -#define TCC1_CTRLD _SFR_MEM8(0x0843) -#define TCC1_CTRLE _SFR_MEM8(0x0844) -#define TCC1_INTCTRLA _SFR_MEM8(0x0846) -#define TCC1_INTCTRLB _SFR_MEM8(0x0847) -#define TCC1_CTRLFCLR _SFR_MEM8(0x0848) -#define TCC1_CTRLFSET _SFR_MEM8(0x0849) -#define TCC1_CTRLGCLR _SFR_MEM8(0x084A) -#define TCC1_CTRLGSET _SFR_MEM8(0x084B) -#define TCC1_INTFLAGS _SFR_MEM8(0x084C) -#define TCC1_TEMP _SFR_MEM8(0x084F) -#define TCC1_CNT _SFR_MEM16(0x0860) -#define TCC1_PER _SFR_MEM16(0x0866) -#define TCC1_CCA _SFR_MEM16(0x0868) -#define TCC1_CCB _SFR_MEM16(0x086A) -#define TCC1_PERBUF _SFR_MEM16(0x0876) -#define TCC1_CCABUF _SFR_MEM16(0x0878) -#define TCC1_CCBBUF _SFR_MEM16(0x087A) - -/* AWEX - Advanced Waveform Extension */ -#define AWEXC_CTRL _SFR_MEM8(0x0880) -#define AWEXC_FDEMASK _SFR_MEM8(0x0882) -#define AWEXC_FDCTRL _SFR_MEM8(0x0883) -#define AWEXC_STATUS _SFR_MEM8(0x0884) -#define AWEXC_STATUSSET _SFR_MEM8(0x0885) -#define AWEXC_DTBOTH _SFR_MEM8(0x0886) -#define AWEXC_DTBOTHBUF _SFR_MEM8(0x0887) -#define AWEXC_DTLS _SFR_MEM8(0x0888) -#define AWEXC_DTHS _SFR_MEM8(0x0889) -#define AWEXC_DTLSBUF _SFR_MEM8(0x088A) -#define AWEXC_DTHSBUF _SFR_MEM8(0x088B) -#define AWEXC_OUTOVEN _SFR_MEM8(0x088C) - -/* HIRES - High-Resolution Extension */ -#define HIRESC_CTRLA _SFR_MEM8(0x0890) - -/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ -#define USARTC0_DATA _SFR_MEM8(0x08A0) -#define USARTC0_STATUS _SFR_MEM8(0x08A1) -#define USARTC0_CTRLA _SFR_MEM8(0x08A3) -#define USARTC0_CTRLB _SFR_MEM8(0x08A4) -#define USARTC0_CTRLC _SFR_MEM8(0x08A5) -#define USARTC0_BAUDCTRLA _SFR_MEM8(0x08A6) -#define USARTC0_BAUDCTRLB _SFR_MEM8(0x08A7) - -/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ -#define USARTC1_DATA _SFR_MEM8(0x08B0) -#define USARTC1_STATUS _SFR_MEM8(0x08B1) -#define USARTC1_CTRLA _SFR_MEM8(0x08B3) -#define USARTC1_CTRLB _SFR_MEM8(0x08B4) -#define USARTC1_CTRLC _SFR_MEM8(0x08B5) -#define USARTC1_BAUDCTRLA _SFR_MEM8(0x08B6) -#define USARTC1_BAUDCTRLB _SFR_MEM8(0x08B7) - -/* SPI - Serial Peripheral Interface */ -#define SPIC_CTRL _SFR_MEM8(0x08C0) -#define SPIC_INTCTRL _SFR_MEM8(0x08C1) -#define SPIC_STATUS _SFR_MEM8(0x08C2) -#define SPIC_DATA _SFR_MEM8(0x08C3) - -/* IRCOM - IR Communication Module */ -#define IRCOM_CTRL _SFR_MEM8(0x08F8) -#define IRCOM_TXPLCTRL _SFR_MEM8(0x08F9) -#define IRCOM_RXPLCTRL _SFR_MEM8(0x08FA) - -/* TC0 - 16-bit Timer/Counter 0 */ -#define TCD0_CTRLA _SFR_MEM8(0x0900) -#define TCD0_CTRLB _SFR_MEM8(0x0901) -#define TCD0_CTRLC _SFR_MEM8(0x0902) -#define TCD0_CTRLD _SFR_MEM8(0x0903) -#define TCD0_CTRLE _SFR_MEM8(0x0904) -#define TCD0_INTCTRLA _SFR_MEM8(0x0906) -#define TCD0_INTCTRLB _SFR_MEM8(0x0907) -#define TCD0_CTRLFCLR _SFR_MEM8(0x0908) -#define TCD0_CTRLFSET _SFR_MEM8(0x0909) -#define TCD0_CTRLGCLR _SFR_MEM8(0x090A) -#define TCD0_CTRLGSET _SFR_MEM8(0x090B) -#define TCD0_INTFLAGS _SFR_MEM8(0x090C) -#define TCD0_TEMP _SFR_MEM8(0x090F) -#define TCD0_CNT _SFR_MEM16(0x0920) -#define TCD0_PER _SFR_MEM16(0x0926) -#define TCD0_CCA _SFR_MEM16(0x0928) -#define TCD0_CCB _SFR_MEM16(0x092A) -#define TCD0_CCC _SFR_MEM16(0x092C) -#define TCD0_CCD _SFR_MEM16(0x092E) -#define TCD0_PERBUF _SFR_MEM16(0x0936) -#define TCD0_CCABUF _SFR_MEM16(0x0938) -#define TCD0_CCBBUF _SFR_MEM16(0x093A) -#define TCD0_CCCBUF _SFR_MEM16(0x093C) -#define TCD0_CCDBUF _SFR_MEM16(0x093E) - -/* TC2 - 16-bit Timer/Counter type 2 */ -#define TCD2_CTRLA _SFR_MEM8(0x0900) -#define TCD2_CTRLB _SFR_MEM8(0x0901) -#define TCD2_CTRLC _SFR_MEM8(0x0902) -#define TCD2_CTRLE _SFR_MEM8(0x0904) -#define TCD2_INTCTRLA _SFR_MEM8(0x0906) -#define TCD2_INTCTRLB _SFR_MEM8(0x0907) -#define TCD2_CTRLF _SFR_MEM8(0x0909) -#define TCD2_INTFLAGS _SFR_MEM8(0x090C) -#define TCD2_LCNT _SFR_MEM8(0x0920) -#define TCD2_HCNT _SFR_MEM8(0x0921) -#define TCD2_LPER _SFR_MEM8(0x0926) -#define TCD2_HPER _SFR_MEM8(0x0927) -#define TCD2_LCMPA _SFR_MEM8(0x0928) -#define TCD2_HCMPA _SFR_MEM8(0x0929) -#define TCD2_LCMPB _SFR_MEM8(0x092A) -#define TCD2_HCMPB _SFR_MEM8(0x092B) -#define TCD2_LCMPC _SFR_MEM8(0x092C) -#define TCD2_HCMPC _SFR_MEM8(0x092D) -#define TCD2_LCMPD _SFR_MEM8(0x092E) -#define TCD2_HCMPD _SFR_MEM8(0x092F) - -/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ -#define USARTD0_DATA _SFR_MEM8(0x09A0) -#define USARTD0_STATUS _SFR_MEM8(0x09A1) -#define USARTD0_CTRLA _SFR_MEM8(0x09A3) -#define USARTD0_CTRLB _SFR_MEM8(0x09A4) -#define USARTD0_CTRLC _SFR_MEM8(0x09A5) -#define USARTD0_BAUDCTRLA _SFR_MEM8(0x09A6) -#define USARTD0_BAUDCTRLB _SFR_MEM8(0x09A7) - -/* SPI - Serial Peripheral Interface */ -#define SPID_CTRL _SFR_MEM8(0x09C0) -#define SPID_INTCTRL _SFR_MEM8(0x09C1) -#define SPID_STATUS _SFR_MEM8(0x09C2) -#define SPID_DATA _SFR_MEM8(0x09C3) - -/* TC0 - 16-bit Timer/Counter 0 */ -#define TCE0_CTRLA _SFR_MEM8(0x0A00) -#define TCE0_CTRLB _SFR_MEM8(0x0A01) -#define TCE0_CTRLC _SFR_MEM8(0x0A02) -#define TCE0_CTRLD _SFR_MEM8(0x0A03) -#define TCE0_CTRLE _SFR_MEM8(0x0A04) -#define TCE0_INTCTRLA _SFR_MEM8(0x0A06) -#define TCE0_INTCTRLB _SFR_MEM8(0x0A07) -#define TCE0_CTRLFCLR _SFR_MEM8(0x0A08) -#define TCE0_CTRLFSET _SFR_MEM8(0x0A09) -#define TCE0_CTRLGCLR _SFR_MEM8(0x0A0A) -#define TCE0_CTRLGSET _SFR_MEM8(0x0A0B) -#define TCE0_INTFLAGS _SFR_MEM8(0x0A0C) -#define TCE0_TEMP _SFR_MEM8(0x0A0F) -#define TCE0_CNT _SFR_MEM16(0x0A20) -#define TCE0_PER _SFR_MEM16(0x0A26) -#define TCE0_CCA _SFR_MEM16(0x0A28) -#define TCE0_CCB _SFR_MEM16(0x0A2A) -#define TCE0_CCC _SFR_MEM16(0x0A2C) -#define TCE0_CCD _SFR_MEM16(0x0A2E) -#define TCE0_PERBUF _SFR_MEM16(0x0A36) -#define TCE0_CCABUF _SFR_MEM16(0x0A38) -#define TCE0_CCBBUF _SFR_MEM16(0x0A3A) -#define TCE0_CCCBUF _SFR_MEM16(0x0A3C) -#define TCE0_CCDBUF _SFR_MEM16(0x0A3E) - - - -/*================== Bitfield Definitions ================== */ - -/* VPORT - Virtual Ports */ -/* VPORT.INTFLAGS bit masks and bit positions */ -#define VPORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ -#define VPORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ - -#define VPORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ -#define VPORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ - -/* XOCD - On-Chip Debug System */ -/* OCD.OCDR0 bit masks and bit positions */ -#define OCD_OCDRD_gm 0xFF /* OCDR Dirty group mask. */ -#define OCD_OCDRD_gp 0 /* OCDR Dirty group position. */ -#define OCD_OCDRD0_bm (1<<0) /* OCDR Dirty bit 0 mask. */ -#define OCD_OCDRD0_bp 0 /* OCDR Dirty bit 0 position. */ -#define OCD_OCDRD1_bm (1<<1) /* OCDR Dirty bit 1 mask. */ -#define OCD_OCDRD1_bp 1 /* OCDR Dirty bit 1 position. */ -#define OCD_OCDRD2_bm (1<<2) /* OCDR Dirty bit 2 mask. */ -#define OCD_OCDRD2_bp 2 /* OCDR Dirty bit 2 position. */ -#define OCD_OCDRD3_bm (1<<3) /* OCDR Dirty bit 3 mask. */ -#define OCD_OCDRD3_bp 3 /* OCDR Dirty bit 3 position. */ -#define OCD_OCDRD4_bm (1<<4) /* OCDR Dirty bit 4 mask. */ -#define OCD_OCDRD4_bp 4 /* OCDR Dirty bit 4 position. */ -#define OCD_OCDRD5_bm (1<<5) /* OCDR Dirty bit 5 mask. */ -#define OCD_OCDRD5_bp 5 /* OCDR Dirty bit 5 position. */ -#define OCD_OCDRD6_bm (1<<6) /* OCDR Dirty bit 6 mask. */ -#define OCD_OCDRD6_bp 6 /* OCDR Dirty bit 6 position. */ -#define OCD_OCDRD7_bm (1<<7) /* OCDR Dirty bit 7 mask. */ -#define OCD_OCDRD7_bp 7 /* OCDR Dirty bit 7 position. */ - -/* OCD.OCDR1 bit masks and bit positions */ -/* OCD_OCDRD Predefined. */ -/* OCD_OCDRD Predefined. */ - -/* CPU - CPU */ -/* CPU.CCP bit masks and bit positions */ -#define CPU_CCP_gm 0xFF /* CCP signature group mask. */ -#define CPU_CCP_gp 0 /* CCP signature group position. */ -#define CPU_CCP0_bm (1<<0) /* CCP signature bit 0 mask. */ -#define CPU_CCP0_bp 0 /* CCP signature bit 0 position. */ -#define CPU_CCP1_bm (1<<1) /* CCP signature bit 1 mask. */ -#define CPU_CCP1_bp 1 /* CCP signature bit 1 position. */ -#define CPU_CCP2_bm (1<<2) /* CCP signature bit 2 mask. */ -#define CPU_CCP2_bp 2 /* CCP signature bit 2 position. */ -#define CPU_CCP3_bm (1<<3) /* CCP signature bit 3 mask. */ -#define CPU_CCP3_bp 3 /* CCP signature bit 3 position. */ -#define CPU_CCP4_bm (1<<4) /* CCP signature bit 4 mask. */ -#define CPU_CCP4_bp 4 /* CCP signature bit 4 position. */ -#define CPU_CCP5_bm (1<<5) /* CCP signature bit 5 mask. */ -#define CPU_CCP5_bp 5 /* CCP signature bit 5 position. */ -#define CPU_CCP6_bm (1<<6) /* CCP signature bit 6 mask. */ -#define CPU_CCP6_bp 6 /* CCP signature bit 6 position. */ -#define CPU_CCP7_bm (1<<7) /* CCP signature bit 7 mask. */ -#define CPU_CCP7_bp 7 /* CCP signature bit 7 position. */ - -/* CPU.SREG bit masks and bit positions */ -#define CPU_I_bm 0x80 /* Global Interrupt Enable Flag bit mask. */ -#define CPU_I_bp 7 /* Global Interrupt Enable Flag bit position. */ - -#define CPU_T_bm 0x40 /* Transfer Bit bit mask. */ -#define CPU_T_bp 6 /* Transfer Bit bit position. */ - -#define CPU_H_bm 0x20 /* Half Carry Flag bit mask. */ -#define CPU_H_bp 5 /* Half Carry Flag bit position. */ - -#define CPU_S_bm 0x10 /* N Exclusive Or V Flag bit mask. */ -#define CPU_S_bp 4 /* N Exclusive Or V Flag bit position. */ - -#define CPU_V_bm 0x08 /* Two's Complement Overflow Flag bit mask. */ -#define CPU_V_bp 3 /* Two's Complement Overflow Flag bit position. */ - -#define CPU_N_bm 0x04 /* Negative Flag bit mask. */ -#define CPU_N_bp 2 /* Negative Flag bit position. */ - -#define CPU_Z_bm 0x02 /* Zero Flag bit mask. */ -#define CPU_Z_bp 1 /* Zero Flag bit position. */ - -#define CPU_C_bm 0x01 /* Carry Flag bit mask. */ -#define CPU_C_bp 0 /* Carry Flag bit position. */ - -/* CLK - Clock System */ -/* CLK.CTRL bit masks and bit positions */ -#define CLK_SCLKSEL_gm 0x07 /* System Clock Selection group mask. */ -#define CLK_SCLKSEL_gp 0 /* System Clock Selection group position. */ -#define CLK_SCLKSEL0_bm (1<<0) /* System Clock Selection bit 0 mask. */ -#define CLK_SCLKSEL0_bp 0 /* System Clock Selection bit 0 position. */ -#define CLK_SCLKSEL1_bm (1<<1) /* System Clock Selection bit 1 mask. */ -#define CLK_SCLKSEL1_bp 1 /* System Clock Selection bit 1 position. */ -#define CLK_SCLKSEL2_bm (1<<2) /* System Clock Selection bit 2 mask. */ -#define CLK_SCLKSEL2_bp 2 /* System Clock Selection bit 2 position. */ - -/* CLK.PSCTRL bit masks and bit positions */ -#define CLK_PSADIV_gm 0x7C /* Prescaler A Division Factor group mask. */ -#define CLK_PSADIV_gp 2 /* Prescaler A Division Factor group position. */ -#define CLK_PSADIV0_bm (1<<2) /* Prescaler A Division Factor bit 0 mask. */ -#define CLK_PSADIV0_bp 2 /* Prescaler A Division Factor bit 0 position. */ -#define CLK_PSADIV1_bm (1<<3) /* Prescaler A Division Factor bit 1 mask. */ -#define CLK_PSADIV1_bp 3 /* Prescaler A Division Factor bit 1 position. */ -#define CLK_PSADIV2_bm (1<<4) /* Prescaler A Division Factor bit 2 mask. */ -#define CLK_PSADIV2_bp 4 /* Prescaler A Division Factor bit 2 position. */ -#define CLK_PSADIV3_bm (1<<5) /* Prescaler A Division Factor bit 3 mask. */ -#define CLK_PSADIV3_bp 5 /* Prescaler A Division Factor bit 3 position. */ -#define CLK_PSADIV4_bm (1<<6) /* Prescaler A Division Factor bit 4 mask. */ -#define CLK_PSADIV4_bp 6 /* Prescaler A Division Factor bit 4 position. */ - -#define CLK_PSBCDIV_gm 0x03 /* Prescaler B and C Division factor group mask. */ -#define CLK_PSBCDIV_gp 0 /* Prescaler B and C Division factor group position. */ -#define CLK_PSBCDIV0_bm (1<<0) /* Prescaler B and C Division factor bit 0 mask. */ -#define CLK_PSBCDIV0_bp 0 /* Prescaler B and C Division factor bit 0 position. */ -#define CLK_PSBCDIV1_bm (1<<1) /* Prescaler B and C Division factor bit 1 mask. */ -#define CLK_PSBCDIV1_bp 1 /* Prescaler B and C Division factor bit 1 position. */ - -/* CLK.LOCK bit masks and bit positions */ -#define CLK_LOCK_bm 0x01 /* Clock System Lock bit mask. */ -#define CLK_LOCK_bp 0 /* Clock System Lock bit position. */ - -/* CLK.RTCCTRL bit masks and bit positions */ -#define CLK_RTCSRC_gm 0x0E /* Clock Source group mask. */ -#define CLK_RTCSRC_gp 1 /* Clock Source group position. */ -#define CLK_RTCSRC0_bm (1<<1) /* Clock Source bit 0 mask. */ -#define CLK_RTCSRC0_bp 1 /* Clock Source bit 0 position. */ -#define CLK_RTCSRC1_bm (1<<2) /* Clock Source bit 1 mask. */ -#define CLK_RTCSRC1_bp 2 /* Clock Source bit 1 position. */ -#define CLK_RTCSRC2_bm (1<<3) /* Clock Source bit 2 mask. */ -#define CLK_RTCSRC2_bp 3 /* Clock Source bit 2 position. */ - -#define CLK_RTCEN_bm 0x01 /* Clock Source Enable bit mask. */ -#define CLK_RTCEN_bp 0 /* Clock Source Enable bit position. */ - -/* CLK.USBCTRL bit masks and bit positions */ -#define CLK_USBPSDIV_gm 0x38 /* Prescaler Division Factor group mask. */ -#define CLK_USBPSDIV_gp 3 /* Prescaler Division Factor group position. */ -#define CLK_USBPSDIV0_bm (1<<3) /* Prescaler Division Factor bit 0 mask. */ -#define CLK_USBPSDIV0_bp 3 /* Prescaler Division Factor bit 0 position. */ -#define CLK_USBPSDIV1_bm (1<<4) /* Prescaler Division Factor bit 1 mask. */ -#define CLK_USBPSDIV1_bp 4 /* Prescaler Division Factor bit 1 position. */ -#define CLK_USBPSDIV2_bm (1<<5) /* Prescaler Division Factor bit 2 mask. */ -#define CLK_USBPSDIV2_bp 5 /* Prescaler Division Factor bit 2 position. */ - -#define CLK_USBSRC_gm 0x06 /* Clock Source group mask. */ -#define CLK_USBSRC_gp 1 /* Clock Source group position. */ -#define CLK_USBSRC0_bm (1<<1) /* Clock Source bit 0 mask. */ -#define CLK_USBSRC0_bp 1 /* Clock Source bit 0 position. */ -#define CLK_USBSRC1_bm (1<<2) /* Clock Source bit 1 mask. */ -#define CLK_USBSRC1_bp 2 /* Clock Source bit 1 position. */ - -#define CLK_USBSEN_bm 0x01 /* Clock Source Enable bit mask. */ -#define CLK_USBSEN_bp 0 /* Clock Source Enable bit position. */ - -/* PR.PRGEN bit masks and bit positions */ -#define PR_USB_bm 0x40 /* USB bit mask. */ -#define PR_USB_bp 6 /* USB bit position. */ - -#define PR_AES_bm 0x10 /* AES bit mask. */ -#define PR_AES_bp 4 /* AES bit position. */ - -#define PR_RTC_bm 0x04 /* Real-time Counter bit mask. */ -#define PR_RTC_bp 2 /* Real-time Counter bit position. */ - -#define PR_EVSYS_bm 0x02 /* Event System bit mask. */ -#define PR_EVSYS_bp 1 /* Event System bit position. */ - -#define PR_DMA_bm 0x01 /* DMA-Controller bit mask. */ -#define PR_DMA_bp 0 /* DMA-Controller bit position. */ - -/* PR.PRPA bit masks and bit positions */ -#define PR_ADC_bm 0x02 /* Port A ADC bit mask. */ -#define PR_ADC_bp 1 /* Port A ADC bit position. */ - -#define PR_AC_bm 0x01 /* Port A Analog Comparator bit mask. */ -#define PR_AC_bp 0 /* Port A Analog Comparator bit position. */ - -/* PR.PRPC bit masks and bit positions */ -#define PR_TWI_bm 0x40 /* Port C Two-wire Interface bit mask. */ -#define PR_TWI_bp 6 /* Port C Two-wire Interface bit position. */ - -#define PR_USART1_bm 0x20 /* Port C USART1 bit mask. */ -#define PR_USART1_bp 5 /* Port C USART1 bit position. */ - -#define PR_USART0_bm 0x10 /* Port C USART0 bit mask. */ -#define PR_USART0_bp 4 /* Port C USART0 bit position. */ - -#define PR_SPI_bm 0x08 /* Port C SPI bit mask. */ -#define PR_SPI_bp 3 /* Port C SPI bit position. */ - -#define PR_HIRES_bm 0x04 /* Port C AWEX bit mask. */ -#define PR_HIRES_bp 2 /* Port C AWEX bit position. */ - -#define PR_TC1_bm 0x02 /* Port C Timer/Counter1 bit mask. */ -#define PR_TC1_bp 1 /* Port C Timer/Counter1 bit position. */ - -#define PR_TC0_bm 0x01 /* Port C Timer/Counter0 bit mask. */ -#define PR_TC0_bp 0 /* Port C Timer/Counter0 bit position. */ - -/* PR.PRPD bit masks and bit positions */ -/* PR_USART0 Predefined. */ -/* PR_USART0 Predefined. */ - -/* PR_SPI Predefined. */ -/* PR_SPI Predefined. */ - -/* PR_TC0 Predefined. */ -/* PR_TC0 Predefined. */ - -/* PR.PRPE bit masks and bit positions */ -/* PR_TWI Predefined. */ -/* PR_TWI Predefined. */ - -/* PR_USART0 Predefined. */ -/* PR_USART0 Predefined. */ - -/* PR_TC0 Predefined. */ -/* PR_TC0 Predefined. */ - -/* PR.PRPF bit masks and bit positions */ -/* PR_USART0 Predefined. */ -/* PR_USART0 Predefined. */ - -/* PR_TC0 Predefined. */ -/* PR_TC0 Predefined. */ - -/* SLEEP - Sleep Controller */ -/* SLEEP.CTRL bit masks and bit positions */ -#define SLEEP_SMODE_gm 0x0E /* Sleep Mode group mask. */ -#define SLEEP_SMODE_gp 1 /* Sleep Mode group position. */ -#define SLEEP_SMODE0_bm (1<<1) /* Sleep Mode bit 0 mask. */ -#define SLEEP_SMODE0_bp 1 /* Sleep Mode bit 0 position. */ -#define SLEEP_SMODE1_bm (1<<2) /* Sleep Mode bit 1 mask. */ -#define SLEEP_SMODE1_bp 2 /* Sleep Mode bit 1 position. */ -#define SLEEP_SMODE2_bm (1<<3) /* Sleep Mode bit 2 mask. */ -#define SLEEP_SMODE2_bp 3 /* Sleep Mode bit 2 position. */ - -#define SLEEP_SEN_bm 0x01 /* Sleep Enable bit mask. */ -#define SLEEP_SEN_bp 0 /* Sleep Enable bit position. */ - -/* OSC - Oscillator */ -/* OSC.CTRL bit masks and bit positions */ -#define OSC_PLLEN_bm 0x10 /* PLL Enable bit mask. */ -#define OSC_PLLEN_bp 4 /* PLL Enable bit position. */ - -#define OSC_XOSCEN_bm 0x08 /* External Oscillator Enable bit mask. */ -#define OSC_XOSCEN_bp 3 /* External Oscillator Enable bit position. */ - -#define OSC_RC32KEN_bm 0x04 /* Internal 32.768 kHz RC Oscillator Enable bit mask. */ -#define OSC_RC32KEN_bp 2 /* Internal 32.768 kHz RC Oscillator Enable bit position. */ - -#define OSC_RC32MEN_bm 0x02 /* Internal 32 MHz RC Oscillator Enable bit mask. */ -#define OSC_RC32MEN_bp 1 /* Internal 32 MHz RC Oscillator Enable bit position. */ - -#define OSC_RC2MEN_bm 0x01 /* Internal 2 MHz RC Oscillator Enable bit mask. */ -#define OSC_RC2MEN_bp 0 /* Internal 2 MHz RC Oscillator Enable bit position. */ - -/* OSC.STATUS bit masks and bit positions */ -#define OSC_PLLRDY_bm 0x10 /* PLL Ready bit mask. */ -#define OSC_PLLRDY_bp 4 /* PLL Ready bit position. */ - -#define OSC_XOSCRDY_bm 0x08 /* External Oscillator Ready bit mask. */ -#define OSC_XOSCRDY_bp 3 /* External Oscillator Ready bit position. */ - -#define OSC_RC32KRDY_bm 0x04 /* Internal 32.768 kHz RC Oscillator Ready bit mask. */ -#define OSC_RC32KRDY_bp 2 /* Internal 32.768 kHz RC Oscillator Ready bit position. */ - -#define OSC_RC32MRDY_bm 0x02 /* Internal 32 MHz RC Oscillator Ready bit mask. */ -#define OSC_RC32MRDY_bp 1 /* Internal 32 MHz RC Oscillator Ready bit position. */ - -#define OSC_RC2MRDY_bm 0x01 /* Internal 2 MHz RC Oscillator Ready bit mask. */ -#define OSC_RC2MRDY_bp 0 /* Internal 2 MHz RC Oscillator Ready bit position. */ - -/* OSC.XOSCCTRL bit masks and bit positions */ -#define OSC_FRQRANGE_gm 0xC0 /* Frequency Range group mask. */ -#define OSC_FRQRANGE_gp 6 /* Frequency Range group position. */ -#define OSC_FRQRANGE0_bm (1<<6) /* Frequency Range bit 0 mask. */ -#define OSC_FRQRANGE0_bp 6 /* Frequency Range bit 0 position. */ -#define OSC_FRQRANGE1_bm (1<<7) /* Frequency Range bit 1 mask. */ -#define OSC_FRQRANGE1_bp 7 /* Frequency Range bit 1 position. */ - -#define OSC_X32KLPM_bm 0x20 /* 32.768 kHz XTAL OSC Low-power Mode bit mask. */ -#define OSC_X32KLPM_bp 5 /* 32.768 kHz XTAL OSC Low-power Mode bit position. */ - -#define OSC_XOSCPWR_bm 0x10 /* 16 MHz Crystal Oscillator High Power mode bit mask. */ -#define OSC_XOSCPWR_bp 4 /* 16 MHz Crystal Oscillator High Power mode bit position. */ - -#define OSC_XOSCSEL_gm 0x0F /* External Oscillator Selection and Startup Time group mask. */ -#define OSC_XOSCSEL_gp 0 /* External Oscillator Selection and Startup Time group position. */ -#define OSC_XOSCSEL0_bm (1<<0) /* External Oscillator Selection and Startup Time bit 0 mask. */ -#define OSC_XOSCSEL0_bp 0 /* External Oscillator Selection and Startup Time bit 0 position. */ -#define OSC_XOSCSEL1_bm (1<<1) /* External Oscillator Selection and Startup Time bit 1 mask. */ -#define OSC_XOSCSEL1_bp 1 /* External Oscillator Selection and Startup Time bit 1 position. */ -#define OSC_XOSCSEL2_bm (1<<2) /* External Oscillator Selection and Startup Time bit 2 mask. */ -#define OSC_XOSCSEL2_bp 2 /* External Oscillator Selection and Startup Time bit 2 position. */ -#define OSC_XOSCSEL3_bm (1<<3) /* External Oscillator Selection and Startup Time bit 3 mask. */ -#define OSC_XOSCSEL3_bp 3 /* External Oscillator Selection and Startup Time bit 3 position. */ - -/* OSC.XOSCFAIL bit masks and bit positions */ -#define OSC_PLLFDIF_bm 0x08 /* PLL Failure Detection Interrupt Flag bit mask. */ -#define OSC_PLLFDIF_bp 3 /* PLL Failure Detection Interrupt Flag bit position. */ - -#define OSC_PLLFDEN_bm 0x04 /* PLL Failure Detection Enable bit mask. */ -#define OSC_PLLFDEN_bp 2 /* PLL Failure Detection Enable bit position. */ - -#define OSC_XOSCFDIF_bm 0x02 /* XOSC Failure Detection Interrupt Flag bit mask. */ -#define OSC_XOSCFDIF_bp 1 /* XOSC Failure Detection Interrupt Flag bit position. */ - -#define OSC_XOSCFDEN_bm 0x01 /* XOSC Failure Detection Enable bit mask. */ -#define OSC_XOSCFDEN_bp 0 /* XOSC Failure Detection Enable bit position. */ - -/* OSC.PLLCTRL bit masks and bit positions */ -#define OSC_PLLSRC_gm 0xC0 /* Clock Source group mask. */ -#define OSC_PLLSRC_gp 6 /* Clock Source group position. */ -#define OSC_PLLSRC0_bm (1<<6) /* Clock Source bit 0 mask. */ -#define OSC_PLLSRC0_bp 6 /* Clock Source bit 0 position. */ -#define OSC_PLLSRC1_bm (1<<7) /* Clock Source bit 1 mask. */ -#define OSC_PLLSRC1_bp 7 /* Clock Source bit 1 position. */ - -#define OSC_PLLDIV_bm 0x20 /* Divide by 2 bit mask. */ -#define OSC_PLLDIV_bp 5 /* Divide by 2 bit position. */ - -#define OSC_PLLFAC_gm 0x1F /* Multiplication Factor group mask. */ -#define OSC_PLLFAC_gp 0 /* Multiplication Factor group position. */ -#define OSC_PLLFAC0_bm (1<<0) /* Multiplication Factor bit 0 mask. */ -#define OSC_PLLFAC0_bp 0 /* Multiplication Factor bit 0 position. */ -#define OSC_PLLFAC1_bm (1<<1) /* Multiplication Factor bit 1 mask. */ -#define OSC_PLLFAC1_bp 1 /* Multiplication Factor bit 1 position. */ -#define OSC_PLLFAC2_bm (1<<2) /* Multiplication Factor bit 2 mask. */ -#define OSC_PLLFAC2_bp 2 /* Multiplication Factor bit 2 position. */ -#define OSC_PLLFAC3_bm (1<<3) /* Multiplication Factor bit 3 mask. */ -#define OSC_PLLFAC3_bp 3 /* Multiplication Factor bit 3 position. */ -#define OSC_PLLFAC4_bm (1<<4) /* Multiplication Factor bit 4 mask. */ -#define OSC_PLLFAC4_bp 4 /* Multiplication Factor bit 4 position. */ - -/* OSC.DFLLCTRL bit masks and bit positions */ -#define OSC_RC32MCREF_gm 0x06 /* 32 MHz DFLL Calibration Reference group mask. */ -#define OSC_RC32MCREF_gp 1 /* 32 MHz DFLL Calibration Reference group position. */ -#define OSC_RC32MCREF0_bm (1<<1) /* 32 MHz DFLL Calibration Reference bit 0 mask. */ -#define OSC_RC32MCREF0_bp 1 /* 32 MHz DFLL Calibration Reference bit 0 position. */ -#define OSC_RC32MCREF1_bm (1<<2) /* 32 MHz DFLL Calibration Reference bit 1 mask. */ -#define OSC_RC32MCREF1_bp 2 /* 32 MHz DFLL Calibration Reference bit 1 position. */ - -#define OSC_RC2MCREF_bm 0x01 /* 2 MHz DFLL Calibration Reference bit mask. */ -#define OSC_RC2MCREF_bp 0 /* 2 MHz DFLL Calibration Reference bit position. */ - -/* DFLL - DFLL */ -/* DFLL.CTRL bit masks and bit positions */ -#define DFLL_ENABLE_bm 0x01 /* DFLL Enable bit mask. */ -#define DFLL_ENABLE_bp 0 /* DFLL Enable bit position. */ - -/* DFLL.CALA bit masks and bit positions */ -#define DFLL_CALL_gm 0x7F /* DFLL Calibration Value A group mask. */ -#define DFLL_CALL_gp 0 /* DFLL Calibration Value A group position. */ -#define DFLL_CALL0_bm (1<<0) /* DFLL Calibration Value A bit 0 mask. */ -#define DFLL_CALL0_bp 0 /* DFLL Calibration Value A bit 0 position. */ -#define DFLL_CALL1_bm (1<<1) /* DFLL Calibration Value A bit 1 mask. */ -#define DFLL_CALL1_bp 1 /* DFLL Calibration Value A bit 1 position. */ -#define DFLL_CALL2_bm (1<<2) /* DFLL Calibration Value A bit 2 mask. */ -#define DFLL_CALL2_bp 2 /* DFLL Calibration Value A bit 2 position. */ -#define DFLL_CALL3_bm (1<<3) /* DFLL Calibration Value A bit 3 mask. */ -#define DFLL_CALL3_bp 3 /* DFLL Calibration Value A bit 3 position. */ -#define DFLL_CALL4_bm (1<<4) /* DFLL Calibration Value A bit 4 mask. */ -#define DFLL_CALL4_bp 4 /* DFLL Calibration Value A bit 4 position. */ -#define DFLL_CALL5_bm (1<<5) /* DFLL Calibration Value A bit 5 mask. */ -#define DFLL_CALL5_bp 5 /* DFLL Calibration Value A bit 5 position. */ -#define DFLL_CALL6_bm (1<<6) /* DFLL Calibration Value A bit 6 mask. */ -#define DFLL_CALL6_bp 6 /* DFLL Calibration Value A bit 6 position. */ - -/* DFLL.CALB bit masks and bit positions */ -#define DFLL_CALH_gm 0x3F /* DFLL Calibration Value B group mask. */ -#define DFLL_CALH_gp 0 /* DFLL Calibration Value B group position. */ -#define DFLL_CALH0_bm (1<<0) /* DFLL Calibration Value B bit 0 mask. */ -#define DFLL_CALH0_bp 0 /* DFLL Calibration Value B bit 0 position. */ -#define DFLL_CALH1_bm (1<<1) /* DFLL Calibration Value B bit 1 mask. */ -#define DFLL_CALH1_bp 1 /* DFLL Calibration Value B bit 1 position. */ -#define DFLL_CALH2_bm (1<<2) /* DFLL Calibration Value B bit 2 mask. */ -#define DFLL_CALH2_bp 2 /* DFLL Calibration Value B bit 2 position. */ -#define DFLL_CALH3_bm (1<<3) /* DFLL Calibration Value B bit 3 mask. */ -#define DFLL_CALH3_bp 3 /* DFLL Calibration Value B bit 3 position. */ -#define DFLL_CALH4_bm (1<<4) /* DFLL Calibration Value B bit 4 mask. */ -#define DFLL_CALH4_bp 4 /* DFLL Calibration Value B bit 4 position. */ -#define DFLL_CALH5_bm (1<<5) /* DFLL Calibration Value B bit 5 mask. */ -#define DFLL_CALH5_bp 5 /* DFLL Calibration Value B bit 5 position. */ - -/* RST - Reset */ -/* RST.STATUS bit masks and bit positions */ -#define RST_SDRF_bm 0x40 /* Spike Detection Reset Flag bit mask. */ -#define RST_SDRF_bp 6 /* Spike Detection Reset Flag bit position. */ - -#define RST_SRF_bm 0x20 /* Software Reset Flag bit mask. */ -#define RST_SRF_bp 5 /* Software Reset Flag bit position. */ - -#define RST_PDIRF_bm 0x10 /* Programming and Debug Interface Interface Reset Flag bit mask. */ -#define RST_PDIRF_bp 4 /* Programming and Debug Interface Interface Reset Flag bit position. */ - -#define RST_WDRF_bm 0x08 /* Watchdog Reset Flag bit mask. */ -#define RST_WDRF_bp 3 /* Watchdog Reset Flag bit position. */ - -#define RST_BORF_bm 0x04 /* Brown-out Reset Flag bit mask. */ -#define RST_BORF_bp 2 /* Brown-out Reset Flag bit position. */ - -#define RST_EXTRF_bm 0x02 /* External Reset Flag bit mask. */ -#define RST_EXTRF_bp 1 /* External Reset Flag bit position. */ - -#define RST_PORF_bm 0x01 /* Power-on Reset Flag bit mask. */ -#define RST_PORF_bp 0 /* Power-on Reset Flag bit position. */ - -/* RST.CTRL bit masks and bit positions */ -#define RST_SWRST_bm 0x01 /* Software Reset bit mask. */ -#define RST_SWRST_bp 0 /* Software Reset bit position. */ - -/* WDT - Watch-Dog Timer */ -/* WDT.CTRL bit masks and bit positions */ -#define WDT_PER_gm 0x3C /* Period group mask. */ -#define WDT_PER_gp 2 /* Period group position. */ -#define WDT_PER0_bm (1<<2) /* Period bit 0 mask. */ -#define WDT_PER0_bp 2 /* Period bit 0 position. */ -#define WDT_PER1_bm (1<<3) /* Period bit 1 mask. */ -#define WDT_PER1_bp 3 /* Period bit 1 position. */ -#define WDT_PER2_bm (1<<4) /* Period bit 2 mask. */ -#define WDT_PER2_bp 4 /* Period bit 2 position. */ -#define WDT_PER3_bm (1<<5) /* Period bit 3 mask. */ -#define WDT_PER3_bp 5 /* Period bit 3 position. */ - -#define WDT_ENABLE_bm 0x02 /* Enable bit mask. */ -#define WDT_ENABLE_bp 1 /* Enable bit position. */ - -#define WDT_CEN_bm 0x01 /* Change Enable bit mask. */ -#define WDT_CEN_bp 0 /* Change Enable bit position. */ - -/* WDT.WINCTRL bit masks and bit positions */ -#define WDT_WPER_gm 0x3C /* Windowed Mode Period group mask. */ -#define WDT_WPER_gp 2 /* Windowed Mode Period group position. */ -#define WDT_WPER0_bm (1<<2) /* Windowed Mode Period bit 0 mask. */ -#define WDT_WPER0_bp 2 /* Windowed Mode Period bit 0 position. */ -#define WDT_WPER1_bm (1<<3) /* Windowed Mode Period bit 1 mask. */ -#define WDT_WPER1_bp 3 /* Windowed Mode Period bit 1 position. */ -#define WDT_WPER2_bm (1<<4) /* Windowed Mode Period bit 2 mask. */ -#define WDT_WPER2_bp 4 /* Windowed Mode Period bit 2 position. */ -#define WDT_WPER3_bm (1<<5) /* Windowed Mode Period bit 3 mask. */ -#define WDT_WPER3_bp 5 /* Windowed Mode Period bit 3 position. */ - -#define WDT_WEN_bm 0x02 /* Windowed Mode Enable bit mask. */ -#define WDT_WEN_bp 1 /* Windowed Mode Enable bit position. */ - -#define WDT_WCEN_bm 0x01 /* Windowed Mode Change Enable bit mask. */ -#define WDT_WCEN_bp 0 /* Windowed Mode Change Enable bit position. */ - -/* WDT.STATUS bit masks and bit positions */ -#define WDT_SYNCBUSY_bm 0x01 /* Syncronization busy bit mask. */ -#define WDT_SYNCBUSY_bp 0 /* Syncronization busy bit position. */ - -/* MCU - MCU Control */ -/* MCU.ANAINIT bit masks and bit positions */ -#define MCU_STARTUPDLYA_gm 0x03 /* Analog startup delay Port A group mask. */ -#define MCU_STARTUPDLYA_gp 0 /* Analog startup delay Port A group position. */ -#define MCU_STARTUPDLYA0_bm (1<<0) /* Analog startup delay Port A bit 0 mask. */ -#define MCU_STARTUPDLYA0_bp 0 /* Analog startup delay Port A bit 0 position. */ -#define MCU_STARTUPDLYA1_bm (1<<1) /* Analog startup delay Port A bit 1 mask. */ -#define MCU_STARTUPDLYA1_bp 1 /* Analog startup delay Port A bit 1 position. */ - -/* MCU.EVSYSLOCK bit masks and bit positions */ -#define MCU_EVSYS0LOCK_bm 0x01 /* Event Channel 0-3 Lock bit mask. */ -#define MCU_EVSYS0LOCK_bp 0 /* Event Channel 0-3 Lock bit position. */ - -/* MCU.AWEXLOCK bit masks and bit positions */ -#define MCU_AWEXCLOCK_bm 0x01 /* AWeX on T/C C0 Lock bit mask. */ -#define MCU_AWEXCLOCK_bp 0 /* AWeX on T/C C0 Lock bit position. */ - -/* PMIC - Programmable Multi-level Interrupt Controller */ -/* PMIC.STATUS bit masks and bit positions */ -#define PMIC_NMIEX_bm 0x80 /* Non-maskable Interrupt Executing bit mask. */ -#define PMIC_NMIEX_bp 7 /* Non-maskable Interrupt Executing bit position. */ - -#define PMIC_HILVLEX_bm 0x04 /* High Level Interrupt Executing bit mask. */ -#define PMIC_HILVLEX_bp 2 /* High Level Interrupt Executing bit position. */ - -#define PMIC_MEDLVLEX_bm 0x02 /* Medium Level Interrupt Executing bit mask. */ -#define PMIC_MEDLVLEX_bp 1 /* Medium Level Interrupt Executing bit position. */ - -#define PMIC_LOLVLEX_bm 0x01 /* Low Level Interrupt Executing bit mask. */ -#define PMIC_LOLVLEX_bp 0 /* Low Level Interrupt Executing bit position. */ - -/* PMIC.INTPRI bit masks and bit positions */ -#define PMIC_INTPRI_gm 0xFF /* Interrupt Priority group mask. */ -#define PMIC_INTPRI_gp 0 /* Interrupt Priority group position. */ -#define PMIC_INTPRI0_bm (1<<0) /* Interrupt Priority bit 0 mask. */ -#define PMIC_INTPRI0_bp 0 /* Interrupt Priority bit 0 position. */ -#define PMIC_INTPRI1_bm (1<<1) /* Interrupt Priority bit 1 mask. */ -#define PMIC_INTPRI1_bp 1 /* Interrupt Priority bit 1 position. */ -#define PMIC_INTPRI2_bm (1<<2) /* Interrupt Priority bit 2 mask. */ -#define PMIC_INTPRI2_bp 2 /* Interrupt Priority bit 2 position. */ -#define PMIC_INTPRI3_bm (1<<3) /* Interrupt Priority bit 3 mask. */ -#define PMIC_INTPRI3_bp 3 /* Interrupt Priority bit 3 position. */ -#define PMIC_INTPRI4_bm (1<<4) /* Interrupt Priority bit 4 mask. */ -#define PMIC_INTPRI4_bp 4 /* Interrupt Priority bit 4 position. */ -#define PMIC_INTPRI5_bm (1<<5) /* Interrupt Priority bit 5 mask. */ -#define PMIC_INTPRI5_bp 5 /* Interrupt Priority bit 5 position. */ -#define PMIC_INTPRI6_bm (1<<6) /* Interrupt Priority bit 6 mask. */ -#define PMIC_INTPRI6_bp 6 /* Interrupt Priority bit 6 position. */ -#define PMIC_INTPRI7_bm (1<<7) /* Interrupt Priority bit 7 mask. */ -#define PMIC_INTPRI7_bp 7 /* Interrupt Priority bit 7 position. */ - -/* PMIC.CTRL bit masks and bit positions */ -#define PMIC_RREN_bm 0x80 /* Round-Robin Priority Enable bit mask. */ -#define PMIC_RREN_bp 7 /* Round-Robin Priority Enable bit position. */ - -#define PMIC_IVSEL_bm 0x40 /* Interrupt Vector Select bit mask. */ -#define PMIC_IVSEL_bp 6 /* Interrupt Vector Select bit position. */ - -#define PMIC_HILVLEN_bm 0x04 /* High Level Enable bit mask. */ -#define PMIC_HILVLEN_bp 2 /* High Level Enable bit position. */ - -#define PMIC_MEDLVLEN_bm 0x02 /* Medium Level Enable bit mask. */ -#define PMIC_MEDLVLEN_bp 1 /* Medium Level Enable bit position. */ - -#define PMIC_LOLVLEN_bm 0x01 /* Low Level Enable bit mask. */ -#define PMIC_LOLVLEN_bp 0 /* Low Level Enable bit position. */ - -/* PORTCFG - Port Configuration */ -/* PORTCFG.VPCTRLA bit masks and bit positions */ -#define PORTCFG_VP1MAP_gm 0xF0 /* Virtual Port 1 Mapping group mask. */ -#define PORTCFG_VP1MAP_gp 4 /* Virtual Port 1 Mapping group position. */ -#define PORTCFG_VP1MAP0_bm (1<<4) /* Virtual Port 1 Mapping bit 0 mask. */ -#define PORTCFG_VP1MAP0_bp 4 /* Virtual Port 1 Mapping bit 0 position. */ -#define PORTCFG_VP1MAP1_bm (1<<5) /* Virtual Port 1 Mapping bit 1 mask. */ -#define PORTCFG_VP1MAP1_bp 5 /* Virtual Port 1 Mapping bit 1 position. */ -#define PORTCFG_VP1MAP2_bm (1<<6) /* Virtual Port 1 Mapping bit 2 mask. */ -#define PORTCFG_VP1MAP2_bp 6 /* Virtual Port 1 Mapping bit 2 position. */ -#define PORTCFG_VP1MAP3_bm (1<<7) /* Virtual Port 1 Mapping bit 3 mask. */ -#define PORTCFG_VP1MAP3_bp 7 /* Virtual Port 1 Mapping bit 3 position. */ - -#define PORTCFG_VP0MAP_gm 0x0F /* Virtual Port 0 Mapping group mask. */ -#define PORTCFG_VP0MAP_gp 0 /* Virtual Port 0 Mapping group position. */ -#define PORTCFG_VP0MAP0_bm (1<<0) /* Virtual Port 0 Mapping bit 0 mask. */ -#define PORTCFG_VP0MAP0_bp 0 /* Virtual Port 0 Mapping bit 0 position. */ -#define PORTCFG_VP0MAP1_bm (1<<1) /* Virtual Port 0 Mapping bit 1 mask. */ -#define PORTCFG_VP0MAP1_bp 1 /* Virtual Port 0 Mapping bit 1 position. */ -#define PORTCFG_VP0MAP2_bm (1<<2) /* Virtual Port 0 Mapping bit 2 mask. */ -#define PORTCFG_VP0MAP2_bp 2 /* Virtual Port 0 Mapping bit 2 position. */ -#define PORTCFG_VP0MAP3_bm (1<<3) /* Virtual Port 0 Mapping bit 3 mask. */ -#define PORTCFG_VP0MAP3_bp 3 /* Virtual Port 0 Mapping bit 3 position. */ - -/* PORTCFG.VPCTRLB bit masks and bit positions */ -#define PORTCFG_VP3MAP_gm 0xF0 /* Virtual Port 3 Mapping group mask. */ -#define PORTCFG_VP3MAP_gp 4 /* Virtual Port 3 Mapping group position. */ -#define PORTCFG_VP3MAP0_bm (1<<4) /* Virtual Port 3 Mapping bit 0 mask. */ -#define PORTCFG_VP3MAP0_bp 4 /* Virtual Port 3 Mapping bit 0 position. */ -#define PORTCFG_VP3MAP1_bm (1<<5) /* Virtual Port 3 Mapping bit 1 mask. */ -#define PORTCFG_VP3MAP1_bp 5 /* Virtual Port 3 Mapping bit 1 position. */ -#define PORTCFG_VP3MAP2_bm (1<<6) /* Virtual Port 3 Mapping bit 2 mask. */ -#define PORTCFG_VP3MAP2_bp 6 /* Virtual Port 3 Mapping bit 2 position. */ -#define PORTCFG_VP3MAP3_bm (1<<7) /* Virtual Port 3 Mapping bit 3 mask. */ -#define PORTCFG_VP3MAP3_bp 7 /* Virtual Port 3 Mapping bit 3 position. */ - -#define PORTCFG_VP2MAP_gm 0x0F /* Virtual Port 2 Mapping group mask. */ -#define PORTCFG_VP2MAP_gp 0 /* Virtual Port 2 Mapping group position. */ -#define PORTCFG_VP2MAP0_bm (1<<0) /* Virtual Port 2 Mapping bit 0 mask. */ -#define PORTCFG_VP2MAP0_bp 0 /* Virtual Port 2 Mapping bit 0 position. */ -#define PORTCFG_VP2MAP1_bm (1<<1) /* Virtual Port 2 Mapping bit 1 mask. */ -#define PORTCFG_VP2MAP1_bp 1 /* Virtual Port 2 Mapping bit 1 position. */ -#define PORTCFG_VP2MAP2_bm (1<<2) /* Virtual Port 2 Mapping bit 2 mask. */ -#define PORTCFG_VP2MAP2_bp 2 /* Virtual Port 2 Mapping bit 2 position. */ -#define PORTCFG_VP2MAP3_bm (1<<3) /* Virtual Port 2 Mapping bit 3 mask. */ -#define PORTCFG_VP2MAP3_bp 3 /* Virtual Port 2 Mapping bit 3 position. */ - -/* PORTCFG.CLKEVOUT bit masks and bit positions */ -#define PORTCFG_CLKOUT_gm 0x03 /* Peripheral Clock Output Port group mask. */ -#define PORTCFG_CLKOUT_gp 0 /* Peripheral Clock Output Port group position. */ -#define PORTCFG_CLKOUT0_bm (1<<0) /* Peripheral Clock Output Port bit 0 mask. */ -#define PORTCFG_CLKOUT0_bp 0 /* Peripheral Clock Output Port bit 0 position. */ -#define PORTCFG_CLKOUT1_bm (1<<1) /* Peripheral Clock Output Port bit 1 mask. */ -#define PORTCFG_CLKOUT1_bp 1 /* Peripheral Clock Output Port bit 1 position. */ - -#define PORTCFG_CLKOUTSEL_gm 0x0C /* Peripheral Clock Output Select group mask. */ -#define PORTCFG_CLKOUTSEL_gp 2 /* Peripheral Clock Output Select group position. */ -#define PORTCFG_CLKOUTSEL0_bm (1<<2) /* Peripheral Clock Output Select bit 0 mask. */ -#define PORTCFG_CLKOUTSEL0_bp 2 /* Peripheral Clock Output Select bit 0 position. */ -#define PORTCFG_CLKOUTSEL1_bm (1<<3) /* Peripheral Clock Output Select bit 1 mask. */ -#define PORTCFG_CLKOUTSEL1_bp 3 /* Peripheral Clock Output Select bit 1 position. */ - -#define PORTCFG_EVOUT_gm 0x30 /* Event Output Port group mask. */ -#define PORTCFG_EVOUT_gp 4 /* Event Output Port group position. */ -#define PORTCFG_EVOUT0_bm (1<<4) /* Event Output Port bit 0 mask. */ -#define PORTCFG_EVOUT0_bp 4 /* Event Output Port bit 0 position. */ -#define PORTCFG_EVOUT1_bm (1<<5) /* Event Output Port bit 1 mask. */ -#define PORTCFG_EVOUT1_bp 5 /* Event Output Port bit 1 position. */ - -#define PORTCFG_RTCOUT_bm 0x40 /* RTC Clock Output bit mask. */ -#define PORTCFG_RTCOUT_bp 6 /* RTC Clock Output bit position. */ - -#define PORTCFG_CLKEVPIN_bm 0x80 /* Peripheral Clock and Event Output pin Select bit mask. */ -#define PORTCFG_CLKEVPIN_bp 7 /* Peripheral Clock and Event Output pin Select bit position. */ - -/* PORTCFG.EVOUTSEL bit masks and bit positions */ -#define PORTCFG_EVOUTSEL_gm 0x07 /* Event Output Select group mask. */ -#define PORTCFG_EVOUTSEL_gp 0 /* Event Output Select group position. */ -#define PORTCFG_EVOUTSEL0_bm (1<<0) /* Event Output Select bit 0 mask. */ -#define PORTCFG_EVOUTSEL0_bp 0 /* Event Output Select bit 0 position. */ -#define PORTCFG_EVOUTSEL1_bm (1<<1) /* Event Output Select bit 1 mask. */ -#define PORTCFG_EVOUTSEL1_bp 1 /* Event Output Select bit 1 position. */ -#define PORTCFG_EVOUTSEL2_bm (1<<2) /* Event Output Select bit 2 mask. */ -#define PORTCFG_EVOUTSEL2_bp 2 /* Event Output Select bit 2 position. */ - -/* CRC - Cyclic Redundancy Checker */ -/* CRC.CTRL bit masks and bit positions */ -#define CRC_RESET_gm 0xC0 /* Reset group mask. */ -#define CRC_RESET_gp 6 /* Reset group position. */ -#define CRC_RESET0_bm (1<<6) /* Reset bit 0 mask. */ -#define CRC_RESET0_bp 6 /* Reset bit 0 position. */ -#define CRC_RESET1_bm (1<<7) /* Reset bit 1 mask. */ -#define CRC_RESET1_bp 7 /* Reset bit 1 position. */ - -#define CRC_CRC32_bm 0x20 /* CRC Mode bit mask. */ -#define CRC_CRC32_bp 5 /* CRC Mode bit position. */ - -#define CRC_SOURCE_gm 0x0F /* Input Source group mask. */ -#define CRC_SOURCE_gp 0 /* Input Source group position. */ -#define CRC_SOURCE0_bm (1<<0) /* Input Source bit 0 mask. */ -#define CRC_SOURCE0_bp 0 /* Input Source bit 0 position. */ -#define CRC_SOURCE1_bm (1<<1) /* Input Source bit 1 mask. */ -#define CRC_SOURCE1_bp 1 /* Input Source bit 1 position. */ -#define CRC_SOURCE2_bm (1<<2) /* Input Source bit 2 mask. */ -#define CRC_SOURCE2_bp 2 /* Input Source bit 2 position. */ -#define CRC_SOURCE3_bm (1<<3) /* Input Source bit 3 mask. */ -#define CRC_SOURCE3_bp 3 /* Input Source bit 3 position. */ - -/* CRC.STATUS bit masks and bit positions */ -#define CRC_ZERO_bm 0x02 /* Zero detection bit mask. */ -#define CRC_ZERO_bp 1 /* Zero detection bit position. */ - -#define CRC_BUSY_bm 0x01 /* Busy bit mask. */ -#define CRC_BUSY_bp 0 /* Busy bit position. */ - -/* EVSYS - Event System */ -/* EVSYS.CH0MUX bit masks and bit positions */ -#define EVSYS_CHMUX_gm 0xFF /* Event Channel 0 Multiplexer group mask. */ -#define EVSYS_CHMUX_gp 0 /* Event Channel 0 Multiplexer group position. */ -#define EVSYS_CHMUX0_bm (1<<0) /* Event Channel 0 Multiplexer bit 0 mask. */ -#define EVSYS_CHMUX0_bp 0 /* Event Channel 0 Multiplexer bit 0 position. */ -#define EVSYS_CHMUX1_bm (1<<1) /* Event Channel 0 Multiplexer bit 1 mask. */ -#define EVSYS_CHMUX1_bp 1 /* Event Channel 0 Multiplexer bit 1 position. */ -#define EVSYS_CHMUX2_bm (1<<2) /* Event Channel 0 Multiplexer bit 2 mask. */ -#define EVSYS_CHMUX2_bp 2 /* Event Channel 0 Multiplexer bit 2 position. */ -#define EVSYS_CHMUX3_bm (1<<3) /* Event Channel 0 Multiplexer bit 3 mask. */ -#define EVSYS_CHMUX3_bp 3 /* Event Channel 0 Multiplexer bit 3 position. */ -#define EVSYS_CHMUX4_bm (1<<4) /* Event Channel 0 Multiplexer bit 4 mask. */ -#define EVSYS_CHMUX4_bp 4 /* Event Channel 0 Multiplexer bit 4 position. */ -#define EVSYS_CHMUX5_bm (1<<5) /* Event Channel 0 Multiplexer bit 5 mask. */ -#define EVSYS_CHMUX5_bp 5 /* Event Channel 0 Multiplexer bit 5 position. */ -#define EVSYS_CHMUX6_bm (1<<6) /* Event Channel 0 Multiplexer bit 6 mask. */ -#define EVSYS_CHMUX6_bp 6 /* Event Channel 0 Multiplexer bit 6 position. */ -#define EVSYS_CHMUX7_bm (1<<7) /* Event Channel 0 Multiplexer bit 7 mask. */ -#define EVSYS_CHMUX7_bp 7 /* Event Channel 0 Multiplexer bit 7 position. */ - -/* EVSYS.CH1MUX bit masks and bit positions */ -/* EVSYS_CHMUX Predefined. */ -/* EVSYS_CHMUX Predefined. */ - -/* EVSYS.CH2MUX bit masks and bit positions */ -/* EVSYS_CHMUX Predefined. */ -/* EVSYS_CHMUX Predefined. */ - -/* EVSYS.CH3MUX bit masks and bit positions */ -/* EVSYS_CHMUX Predefined. */ -/* EVSYS_CHMUX Predefined. */ - -/* EVSYS.CH0CTRL bit masks and bit positions */ -#define EVSYS_QDIRM_gm 0x60 /* Quadrature Decoder Index Recognition Mode group mask. */ -#define EVSYS_QDIRM_gp 5 /* Quadrature Decoder Index Recognition Mode group position. */ -#define EVSYS_QDIRM0_bm (1<<5) /* Quadrature Decoder Index Recognition Mode bit 0 mask. */ -#define EVSYS_QDIRM0_bp 5 /* Quadrature Decoder Index Recognition Mode bit 0 position. */ -#define EVSYS_QDIRM1_bm (1<<6) /* Quadrature Decoder Index Recognition Mode bit 1 mask. */ -#define EVSYS_QDIRM1_bp 6 /* Quadrature Decoder Index Recognition Mode bit 1 position. */ - -#define EVSYS_QDIEN_bm 0x10 /* Quadrature Decoder Index Enable bit mask. */ -#define EVSYS_QDIEN_bp 4 /* Quadrature Decoder Index Enable bit position. */ - -#define EVSYS_QDEN_bm 0x08 /* Quadrature Decoder Enable bit mask. */ -#define EVSYS_QDEN_bp 3 /* Quadrature Decoder Enable bit position. */ - -#define EVSYS_DIGFILT_gm 0x07 /* Digital Filter group mask. */ -#define EVSYS_DIGFILT_gp 0 /* Digital Filter group position. */ -#define EVSYS_DIGFILT0_bm (1<<0) /* Digital Filter bit 0 mask. */ -#define EVSYS_DIGFILT0_bp 0 /* Digital Filter bit 0 position. */ -#define EVSYS_DIGFILT1_bm (1<<1) /* Digital Filter bit 1 mask. */ -#define EVSYS_DIGFILT1_bp 1 /* Digital Filter bit 1 position. */ -#define EVSYS_DIGFILT2_bm (1<<2) /* Digital Filter bit 2 mask. */ -#define EVSYS_DIGFILT2_bp 2 /* Digital Filter bit 2 position. */ - -/* EVSYS.CH1CTRL bit masks and bit positions */ -/* EVSYS_DIGFILT Predefined. */ -/* EVSYS_DIGFILT Predefined. */ - -/* EVSYS.CH2CTRL bit masks and bit positions */ -/* EVSYS_DIGFILT Predefined. */ -/* EVSYS_DIGFILT Predefined. */ - -/* EVSYS.CH3CTRL bit masks and bit positions */ -/* EVSYS_DIGFILT Predefined. */ -/* EVSYS_DIGFILT Predefined. */ - -/* NVM - Non Volatile Memory Controller */ -/* NVM.CMD bit masks and bit positions */ -#define NVM_CMD_gm 0x7F /* Command group mask. */ -#define NVM_CMD_gp 0 /* Command group position. */ -#define NVM_CMD0_bm (1<<0) /* Command bit 0 mask. */ -#define NVM_CMD0_bp 0 /* Command bit 0 position. */ -#define NVM_CMD1_bm (1<<1) /* Command bit 1 mask. */ -#define NVM_CMD1_bp 1 /* Command bit 1 position. */ -#define NVM_CMD2_bm (1<<2) /* Command bit 2 mask. */ -#define NVM_CMD2_bp 2 /* Command bit 2 position. */ -#define NVM_CMD3_bm (1<<3) /* Command bit 3 mask. */ -#define NVM_CMD3_bp 3 /* Command bit 3 position. */ -#define NVM_CMD4_bm (1<<4) /* Command bit 4 mask. */ -#define NVM_CMD4_bp 4 /* Command bit 4 position. */ -#define NVM_CMD5_bm (1<<5) /* Command bit 5 mask. */ -#define NVM_CMD5_bp 5 /* Command bit 5 position. */ -#define NVM_CMD6_bm (1<<6) /* Command bit 6 mask. */ -#define NVM_CMD6_bp 6 /* Command bit 6 position. */ - -/* NVM.CTRLA bit masks and bit positions */ -#define NVM_CMDEX_bm 0x01 /* Command Execute bit mask. */ -#define NVM_CMDEX_bp 0 /* Command Execute bit position. */ - -/* NVM.CTRLB bit masks and bit positions */ -#define NVM_EEMAPEN_bm 0x08 /* EEPROM Mapping Enable bit mask. */ -#define NVM_EEMAPEN_bp 3 /* EEPROM Mapping Enable bit position. */ - -#define NVM_FPRM_bm 0x04 /* Flash Power Reduction Enable bit mask. */ -#define NVM_FPRM_bp 2 /* Flash Power Reduction Enable bit position. */ - -#define NVM_EPRM_bm 0x02 /* EEPROM Power Reduction Enable bit mask. */ -#define NVM_EPRM_bp 1 /* EEPROM Power Reduction Enable bit position. */ - -#define NVM_SPMLOCK_bm 0x01 /* SPM Lock bit mask. */ -#define NVM_SPMLOCK_bp 0 /* SPM Lock bit position. */ - -/* NVM.INTCTRL bit masks and bit positions */ -#define NVM_SPMLVL_gm 0x0C /* SPM Interrupt Level group mask. */ -#define NVM_SPMLVL_gp 2 /* SPM Interrupt Level group position. */ -#define NVM_SPMLVL0_bm (1<<2) /* SPM Interrupt Level bit 0 mask. */ -#define NVM_SPMLVL0_bp 2 /* SPM Interrupt Level bit 0 position. */ -#define NVM_SPMLVL1_bm (1<<3) /* SPM Interrupt Level bit 1 mask. */ -#define NVM_SPMLVL1_bp 3 /* SPM Interrupt Level bit 1 position. */ - -#define NVM_EELVL_gm 0x03 /* EEPROM Interrupt Level group mask. */ -#define NVM_EELVL_gp 0 /* EEPROM Interrupt Level group position. */ -#define NVM_EELVL0_bm (1<<0) /* EEPROM Interrupt Level bit 0 mask. */ -#define NVM_EELVL0_bp 0 /* EEPROM Interrupt Level bit 0 position. */ -#define NVM_EELVL1_bm (1<<1) /* EEPROM Interrupt Level bit 1 mask. */ -#define NVM_EELVL1_bp 1 /* EEPROM Interrupt Level bit 1 position. */ - -/* NVM.STATUS bit masks and bit positions */ -#define NVM_NVMBUSY_bm 0x80 /* Non-volatile Memory Busy bit mask. */ -#define NVM_NVMBUSY_bp 7 /* Non-volatile Memory Busy bit position. */ - -#define NVM_FBUSY_bm 0x40 /* Flash Memory Busy bit mask. */ -#define NVM_FBUSY_bp 6 /* Flash Memory Busy bit position. */ - -#define NVM_EELOAD_bm 0x02 /* EEPROM Page Buffer Active Loading bit mask. */ -#define NVM_EELOAD_bp 1 /* EEPROM Page Buffer Active Loading bit position. */ - -#define NVM_FLOAD_bm 0x01 /* Flash Page Buffer Active Loading bit mask. */ -#define NVM_FLOAD_bp 0 /* Flash Page Buffer Active Loading bit position. */ - -/* NVM.LOCKBITS bit masks and bit positions */ -#define NVM_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ -#define NVM_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ -#define NVM_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ -#define NVM_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ -#define NVM_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ -#define NVM_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ - -#define NVM_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ -#define NVM_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ -#define NVM_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ -#define NVM_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ -#define NVM_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ -#define NVM_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ - -#define NVM_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ -#define NVM_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ -#define NVM_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ -#define NVM_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ -#define NVM_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ -#define NVM_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ - -#define NVM_LB_gm 0x03 /* Lock Bits group mask. */ -#define NVM_LB_gp 0 /* Lock Bits group position. */ -#define NVM_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ -#define NVM_LB0_bp 0 /* Lock Bits bit 0 position. */ -#define NVM_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ -#define NVM_LB1_bp 1 /* Lock Bits bit 1 position. */ - -/* ADC - Analog/Digital Converter */ -/* ADC_CH.CTRL bit masks and bit positions */ -#define ADC_CH_START_bm 0x80 /* Channel Start Conversion bit mask. */ -#define ADC_CH_START_bp 7 /* Channel Start Conversion bit position. */ - -#define ADC_CH_GAIN_gm 0x1C /* Gain Factor group mask. */ -#define ADC_CH_GAIN_gp 2 /* Gain Factor group position. */ -#define ADC_CH_GAIN0_bm (1<<2) /* Gain Factor bit 0 mask. */ -#define ADC_CH_GAIN0_bp 2 /* Gain Factor bit 0 position. */ -#define ADC_CH_GAIN1_bm (1<<3) /* Gain Factor bit 1 mask. */ -#define ADC_CH_GAIN1_bp 3 /* Gain Factor bit 1 position. */ -#define ADC_CH_GAIN2_bm (1<<4) /* Gain Factor bit 2 mask. */ -#define ADC_CH_GAIN2_bp 4 /* Gain Factor bit 2 position. */ - -#define ADC_CH_INPUTMODE_gm 0x03 /* Input Mode Select group mask. */ -#define ADC_CH_INPUTMODE_gp 0 /* Input Mode Select group position. */ -#define ADC_CH_INPUTMODE0_bm (1<<0) /* Input Mode Select bit 0 mask. */ -#define ADC_CH_INPUTMODE0_bp 0 /* Input Mode Select bit 0 position. */ -#define ADC_CH_INPUTMODE1_bm (1<<1) /* Input Mode Select bit 1 mask. */ -#define ADC_CH_INPUTMODE1_bp 1 /* Input Mode Select bit 1 position. */ - -/* ADC_CH.MUXCTRL bit masks and bit positions */ -#define ADC_CH_MUXPOS_gm 0x78 /* MUX selection on Positive ADC input group mask. */ -#define ADC_CH_MUXPOS_gp 3 /* MUX selection on Positive ADC input group position. */ -#define ADC_CH_MUXPOS0_bm (1<<3) /* MUX selection on Positive ADC input bit 0 mask. */ -#define ADC_CH_MUXPOS0_bp 3 /* MUX selection on Positive ADC input bit 0 position. */ -#define ADC_CH_MUXPOS1_bm (1<<4) /* MUX selection on Positive ADC input bit 1 mask. */ -#define ADC_CH_MUXPOS1_bp 4 /* MUX selection on Positive ADC input bit 1 position. */ -#define ADC_CH_MUXPOS2_bm (1<<5) /* MUX selection on Positive ADC input bit 2 mask. */ -#define ADC_CH_MUXPOS2_bp 5 /* MUX selection on Positive ADC input bit 2 position. */ -#define ADC_CH_MUXPOS3_bm (1<<6) /* MUX selection on Positive ADC input bit 3 mask. */ -#define ADC_CH_MUXPOS3_bp 6 /* MUX selection on Positive ADC input bit 3 position. */ - -#define ADC_CH_MUXINT_gm 0x78 /* MUX selection on Internal ADC input group mask. */ -#define ADC_CH_MUXINT_gp 3 /* MUX selection on Internal ADC input group position. */ -#define ADC_CH_MUXINT0_bm (1<<3) /* MUX selection on Internal ADC input bit 0 mask. */ -#define ADC_CH_MUXINT0_bp 3 /* MUX selection on Internal ADC input bit 0 position. */ -#define ADC_CH_MUXINT1_bm (1<<4) /* MUX selection on Internal ADC input bit 1 mask. */ -#define ADC_CH_MUXINT1_bp 4 /* MUX selection on Internal ADC input bit 1 position. */ -#define ADC_CH_MUXINT2_bm (1<<5) /* MUX selection on Internal ADC input bit 2 mask. */ -#define ADC_CH_MUXINT2_bp 5 /* MUX selection on Internal ADC input bit 2 position. */ -#define ADC_CH_MUXINT3_bm (1<<6) /* MUX selection on Internal ADC input bit 3 mask. */ -#define ADC_CH_MUXINT3_bp 6 /* MUX selection on Internal ADC input bit 3 position. */ - -#define ADC_CH_MUXNEG_gm 0x03 /* MUX selection on Negative ADC input group mask. */ -#define ADC_CH_MUXNEG_gp 0 /* MUX selection on Negative ADC input group position. */ -#define ADC_CH_MUXNEG0_bm (1<<0) /* MUX selection on Negative ADC input bit 0 mask. */ -#define ADC_CH_MUXNEG0_bp 0 /* MUX selection on Negative ADC input bit 0 position. */ -#define ADC_CH_MUXNEG1_bm (1<<1) /* MUX selection on Negative ADC input bit 1 mask. */ -#define ADC_CH_MUXNEG1_bp 1 /* MUX selection on Negative ADC input bit 1 position. */ - -/* ADC_CH.INTCTRL bit masks and bit positions */ -#define ADC_CH_INTMODE_gm 0x0C /* Interrupt Mode group mask. */ -#define ADC_CH_INTMODE_gp 2 /* Interrupt Mode group position. */ -#define ADC_CH_INTMODE0_bm (1<<2) /* Interrupt Mode bit 0 mask. */ -#define ADC_CH_INTMODE0_bp 2 /* Interrupt Mode bit 0 position. */ -#define ADC_CH_INTMODE1_bm (1<<3) /* Interrupt Mode bit 1 mask. */ -#define ADC_CH_INTMODE1_bp 3 /* Interrupt Mode bit 1 position. */ - -#define ADC_CH_INTLVL_gm 0x03 /* Interrupt Level group mask. */ -#define ADC_CH_INTLVL_gp 0 /* Interrupt Level group position. */ -#define ADC_CH_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */ -#define ADC_CH_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */ -#define ADC_CH_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ -#define ADC_CH_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */ - -/* ADC_CH.INTFLAGS bit masks and bit positions */ -#define ADC_CH_CHIF_bm 0x01 /* Channel Interrupt Flag bit mask. */ -#define ADC_CH_CHIF_bp 0 /* Channel Interrupt Flag bit position. */ - -/* ADC_CH.SCAN bit masks and bit positions */ -#define ADC_CH_OFFSET_gm 0xF0 /* Positive MUX setting offset group mask. */ -#define ADC_CH_OFFSET_gp 4 /* Positive MUX setting offset group position. */ -#define ADC_CH_OFFSET0_bm (1<<4) /* Positive MUX setting offset bit 0 mask. */ -#define ADC_CH_OFFSET0_bp 4 /* Positive MUX setting offset bit 0 position. */ -#define ADC_CH_OFFSET1_bm (1<<5) /* Positive MUX setting offset bit 1 mask. */ -#define ADC_CH_OFFSET1_bp 5 /* Positive MUX setting offset bit 1 position. */ -#define ADC_CH_OFFSET2_bm (1<<6) /* Positive MUX setting offset bit 2 mask. */ -#define ADC_CH_OFFSET2_bp 6 /* Positive MUX setting offset bit 2 position. */ -#define ADC_CH_OFFSET3_bm (1<<7) /* Positive MUX setting offset bit 3 mask. */ -#define ADC_CH_OFFSET3_bp 7 /* Positive MUX setting offset bit 3 position. */ - -#define ADC_CH_SCANNUM_gm 0x0F /* Number of Channels included in scan group mask. */ -#define ADC_CH_SCANNUM_gp 0 /* Number of Channels included in scan group position. */ -#define ADC_CH_SCANNUM0_bm (1<<0) /* Number of Channels included in scan bit 0 mask. */ -#define ADC_CH_SCANNUM0_bp 0 /* Number of Channels included in scan bit 0 position. */ -#define ADC_CH_SCANNUM1_bm (1<<1) /* Number of Channels included in scan bit 1 mask. */ -#define ADC_CH_SCANNUM1_bp 1 /* Number of Channels included in scan bit 1 position. */ -#define ADC_CH_SCANNUM2_bm (1<<2) /* Number of Channels included in scan bit 2 mask. */ -#define ADC_CH_SCANNUM2_bp 2 /* Number of Channels included in scan bit 2 position. */ -#define ADC_CH_SCANNUM3_bm (1<<3) /* Number of Channels included in scan bit 3 mask. */ -#define ADC_CH_SCANNUM3_bp 3 /* Number of Channels included in scan bit 3 position. */ - -/* ADC.CTRLA bit masks and bit positions */ -#define ADC_CH0START_bm 0x04 /* Channel 0 Start Conversion bit mask. */ -#define ADC_CH0START_bp 2 /* Channel 0 Start Conversion bit position. */ - -#define ADC_FLUSH_bm 0x02 /* ADC Flush bit mask. */ -#define ADC_FLUSH_bp 1 /* ADC Flush bit position. */ - -#define ADC_ENABLE_bm 0x01 /* Enable ADC bit mask. */ -#define ADC_ENABLE_bp 0 /* Enable ADC bit position. */ - -/* ADC.CTRLB bit masks and bit positions */ -#define ADC_CURRLIMIT_gm 0x60 /* Current Limitation group mask. */ -#define ADC_CURRLIMIT_gp 5 /* Current Limitation group position. */ -#define ADC_CURRLIMIT0_bm (1<<5) /* Current Limitation bit 0 mask. */ -#define ADC_CURRLIMIT0_bp 5 /* Current Limitation bit 0 position. */ -#define ADC_CURRLIMIT1_bm (1<<6) /* Current Limitation bit 1 mask. */ -#define ADC_CURRLIMIT1_bp 6 /* Current Limitation bit 1 position. */ - -#define ADC_CONMODE_bm 0x10 /* Conversion Mode bit mask. */ -#define ADC_CONMODE_bp 4 /* Conversion Mode bit position. */ - -#define ADC_FREERUN_bm 0x08 /* Free Running Mode Enable bit mask. */ -#define ADC_FREERUN_bp 3 /* Free Running Mode Enable bit position. */ - -#define ADC_RESOLUTION_gm 0x06 /* Result Resolution group mask. */ -#define ADC_RESOLUTION_gp 1 /* Result Resolution group position. */ -#define ADC_RESOLUTION0_bm (1<<1) /* Result Resolution bit 0 mask. */ -#define ADC_RESOLUTION0_bp 1 /* Result Resolution bit 0 position. */ -#define ADC_RESOLUTION1_bm (1<<2) /* Result Resolution bit 1 mask. */ -#define ADC_RESOLUTION1_bp 2 /* Result Resolution bit 1 position. */ - -/* ADC.REFCTRL bit masks and bit positions */ -#define ADC_REFSEL_gm 0x70 /* Reference Selection group mask. */ -#define ADC_REFSEL_gp 4 /* Reference Selection group position. */ -#define ADC_REFSEL0_bm (1<<4) /* Reference Selection bit 0 mask. */ -#define ADC_REFSEL0_bp 4 /* Reference Selection bit 0 position. */ -#define ADC_REFSEL1_bm (1<<5) /* Reference Selection bit 1 mask. */ -#define ADC_REFSEL1_bp 5 /* Reference Selection bit 1 position. */ -#define ADC_REFSEL2_bm (1<<6) /* Reference Selection bit 2 mask. */ -#define ADC_REFSEL2_bp 6 /* Reference Selection bit 2 position. */ - -#define ADC_BANDGAP_bm 0x02 /* Bandgap enable bit mask. */ -#define ADC_BANDGAP_bp 1 /* Bandgap enable bit position. */ - -#define ADC_TEMPREF_bm 0x01 /* Temperature Reference Enable bit mask. */ -#define ADC_TEMPREF_bp 0 /* Temperature Reference Enable bit position. */ - -/* ADC.EVCTRL bit masks and bit positions */ -#define ADC_EVSEL_gm 0x18 /* Event Input Select group mask. */ -#define ADC_EVSEL_gp 3 /* Event Input Select group position. */ -#define ADC_EVSEL0_bm (1<<3) /* Event Input Select bit 0 mask. */ -#define ADC_EVSEL0_bp 3 /* Event Input Select bit 0 position. */ -#define ADC_EVSEL1_bm (1<<4) /* Event Input Select bit 1 mask. */ -#define ADC_EVSEL1_bp 4 /* Event Input Select bit 1 position. */ - -#define ADC_EVACT_gm 0x07 /* Event Action Select group mask. */ -#define ADC_EVACT_gp 0 /* Event Action Select group position. */ -#define ADC_EVACT0_bm (1<<0) /* Event Action Select bit 0 mask. */ -#define ADC_EVACT0_bp 0 /* Event Action Select bit 0 position. */ -#define ADC_EVACT1_bm (1<<1) /* Event Action Select bit 1 mask. */ -#define ADC_EVACT1_bp 1 /* Event Action Select bit 1 position. */ -#define ADC_EVACT2_bm (1<<2) /* Event Action Select bit 2 mask. */ -#define ADC_EVACT2_bp 2 /* Event Action Select bit 2 position. */ - -/* ADC.PRESCALER bit masks and bit positions */ -#define ADC_PRESCALER_gm 0x07 /* Clock Prescaler Selection group mask. */ -#define ADC_PRESCALER_gp 0 /* Clock Prescaler Selection group position. */ -#define ADC_PRESCALER0_bm (1<<0) /* Clock Prescaler Selection bit 0 mask. */ -#define ADC_PRESCALER0_bp 0 /* Clock Prescaler Selection bit 0 position. */ -#define ADC_PRESCALER1_bm (1<<1) /* Clock Prescaler Selection bit 1 mask. */ -#define ADC_PRESCALER1_bp 1 /* Clock Prescaler Selection bit 1 position. */ -#define ADC_PRESCALER2_bm (1<<2) /* Clock Prescaler Selection bit 2 mask. */ -#define ADC_PRESCALER2_bp 2 /* Clock Prescaler Selection bit 2 position. */ - -/* ADC.INTFLAGS bit masks and bit positions */ -#define ADC_CH0IF_bm 0x01 /* Channel 0 Interrupt Flag bit mask. */ -#define ADC_CH0IF_bp 0 /* Channel 0 Interrupt Flag bit position. */ - -/* AC - Analog Comparator */ -/* AC.AC0CTRL bit masks and bit positions */ -#define AC_INTMODE_gm 0xC0 /* Interrupt Mode group mask. */ -#define AC_INTMODE_gp 6 /* Interrupt Mode group position. */ -#define AC_INTMODE0_bm (1<<6) /* Interrupt Mode bit 0 mask. */ -#define AC_INTMODE0_bp 6 /* Interrupt Mode bit 0 position. */ -#define AC_INTMODE1_bm (1<<7) /* Interrupt Mode bit 1 mask. */ -#define AC_INTMODE1_bp 7 /* Interrupt Mode bit 1 position. */ - -#define AC_INTLVL_gm 0x30 /* Interrupt Level group mask. */ -#define AC_INTLVL_gp 4 /* Interrupt Level group position. */ -#define AC_INTLVL0_bm (1<<4) /* Interrupt Level bit 0 mask. */ -#define AC_INTLVL0_bp 4 /* Interrupt Level bit 0 position. */ -#define AC_INTLVL1_bm (1<<5) /* Interrupt Level bit 1 mask. */ -#define AC_INTLVL1_bp 5 /* Interrupt Level bit 1 position. */ - -#define AC_HYSMODE_gm 0x06 /* Hysteresis Mode group mask. */ -#define AC_HYSMODE_gp 1 /* Hysteresis Mode group position. */ -#define AC_HYSMODE0_bm (1<<1) /* Hysteresis Mode bit 0 mask. */ -#define AC_HYSMODE0_bp 1 /* Hysteresis Mode bit 0 position. */ -#define AC_HYSMODE1_bm (1<<2) /* Hysteresis Mode bit 1 mask. */ -#define AC_HYSMODE1_bp 2 /* Hysteresis Mode bit 1 position. */ - -#define AC_ENABLE_bm 0x01 /* Enable bit mask. */ -#define AC_ENABLE_bp 0 /* Enable bit position. */ - -/* AC.AC1CTRL bit masks and bit positions */ -/* AC_INTMODE Predefined. */ -/* AC_INTMODE Predefined. */ - -/* AC_INTLVL Predefined. */ -/* AC_INTLVL Predefined. */ - -/* AC_HYSMODE Predefined. */ -/* AC_HYSMODE Predefined. */ - -/* AC_ENABLE Predefined. */ -/* AC_ENABLE Predefined. */ - -/* AC.AC0MUXCTRL bit masks and bit positions */ -#define AC_MUXPOS_gm 0x38 /* MUX Positive Input group mask. */ -#define AC_MUXPOS_gp 3 /* MUX Positive Input group position. */ -#define AC_MUXPOS0_bm (1<<3) /* MUX Positive Input bit 0 mask. */ -#define AC_MUXPOS0_bp 3 /* MUX Positive Input bit 0 position. */ -#define AC_MUXPOS1_bm (1<<4) /* MUX Positive Input bit 1 mask. */ -#define AC_MUXPOS1_bp 4 /* MUX Positive Input bit 1 position. */ -#define AC_MUXPOS2_bm (1<<5) /* MUX Positive Input bit 2 mask. */ -#define AC_MUXPOS2_bp 5 /* MUX Positive Input bit 2 position. */ - -#define AC_MUXNEG_gm 0x07 /* MUX Negative Input group mask. */ -#define AC_MUXNEG_gp 0 /* MUX Negative Input group position. */ -#define AC_MUXNEG0_bm (1<<0) /* MUX Negative Input bit 0 mask. */ -#define AC_MUXNEG0_bp 0 /* MUX Negative Input bit 0 position. */ -#define AC_MUXNEG1_bm (1<<1) /* MUX Negative Input bit 1 mask. */ -#define AC_MUXNEG1_bp 1 /* MUX Negative Input bit 1 position. */ -#define AC_MUXNEG2_bm (1<<2) /* MUX Negative Input bit 2 mask. */ -#define AC_MUXNEG2_bp 2 /* MUX Negative Input bit 2 position. */ - -/* AC.AC1MUXCTRL bit masks and bit positions */ -/* AC_MUXPOS Predefined. */ -/* AC_MUXPOS Predefined. */ - -/* AC_MUXNEG Predefined. */ -/* AC_MUXNEG Predefined. */ - -/* AC.CTRLA bit masks and bit positions */ -#define AC_AC1OUT_bm 0x02 /* Analog Comparator 1 Output Enable bit mask. */ -#define AC_AC1OUT_bp 1 /* Analog Comparator 1 Output Enable bit position. */ - -#define AC_AC0OUT_bm 0x01 /* Analog Comparator 0 Output Enable bit mask. */ -#define AC_AC0OUT_bp 0 /* Analog Comparator 0 Output Enable bit position. */ - -/* AC.CTRLB bit masks and bit positions */ -#define AC_SCALEFAC_gm 0x3F /* VCC Voltage Scaler Factor group mask. */ -#define AC_SCALEFAC_gp 0 /* VCC Voltage Scaler Factor group position. */ -#define AC_SCALEFAC0_bm (1<<0) /* VCC Voltage Scaler Factor bit 0 mask. */ -#define AC_SCALEFAC0_bp 0 /* VCC Voltage Scaler Factor bit 0 position. */ -#define AC_SCALEFAC1_bm (1<<1) /* VCC Voltage Scaler Factor bit 1 mask. */ -#define AC_SCALEFAC1_bp 1 /* VCC Voltage Scaler Factor bit 1 position. */ -#define AC_SCALEFAC2_bm (1<<2) /* VCC Voltage Scaler Factor bit 2 mask. */ -#define AC_SCALEFAC2_bp 2 /* VCC Voltage Scaler Factor bit 2 position. */ -#define AC_SCALEFAC3_bm (1<<3) /* VCC Voltage Scaler Factor bit 3 mask. */ -#define AC_SCALEFAC3_bp 3 /* VCC Voltage Scaler Factor bit 3 position. */ -#define AC_SCALEFAC4_bm (1<<4) /* VCC Voltage Scaler Factor bit 4 mask. */ -#define AC_SCALEFAC4_bp 4 /* VCC Voltage Scaler Factor bit 4 position. */ -#define AC_SCALEFAC5_bm (1<<5) /* VCC Voltage Scaler Factor bit 5 mask. */ -#define AC_SCALEFAC5_bp 5 /* VCC Voltage Scaler Factor bit 5 position. */ - -/* AC.WINCTRL bit masks and bit positions */ -#define AC_WEN_bm 0x10 /* Window Mode Enable bit mask. */ -#define AC_WEN_bp 4 /* Window Mode Enable bit position. */ - -#define AC_WINTMODE_gm 0x0C /* Window Interrupt Mode group mask. */ -#define AC_WINTMODE_gp 2 /* Window Interrupt Mode group position. */ -#define AC_WINTMODE0_bm (1<<2) /* Window Interrupt Mode bit 0 mask. */ -#define AC_WINTMODE0_bp 2 /* Window Interrupt Mode bit 0 position. */ -#define AC_WINTMODE1_bm (1<<3) /* Window Interrupt Mode bit 1 mask. */ -#define AC_WINTMODE1_bp 3 /* Window Interrupt Mode bit 1 position. */ - -#define AC_WINTLVL_gm 0x03 /* Window Interrupt Level group mask. */ -#define AC_WINTLVL_gp 0 /* Window Interrupt Level group position. */ -#define AC_WINTLVL0_bm (1<<0) /* Window Interrupt Level bit 0 mask. */ -#define AC_WINTLVL0_bp 0 /* Window Interrupt Level bit 0 position. */ -#define AC_WINTLVL1_bm (1<<1) /* Window Interrupt Level bit 1 mask. */ -#define AC_WINTLVL1_bp 1 /* Window Interrupt Level bit 1 position. */ - -/* AC.STATUS bit masks and bit positions */ -#define AC_WSTATE_gm 0xC0 /* Window Mode State group mask. */ -#define AC_WSTATE_gp 6 /* Window Mode State group position. */ -#define AC_WSTATE0_bm (1<<6) /* Window Mode State bit 0 mask. */ -#define AC_WSTATE0_bp 6 /* Window Mode State bit 0 position. */ -#define AC_WSTATE1_bm (1<<7) /* Window Mode State bit 1 mask. */ -#define AC_WSTATE1_bp 7 /* Window Mode State bit 1 position. */ - -#define AC_AC1STATE_bm 0x20 /* Analog Comparator 1 State bit mask. */ -#define AC_AC1STATE_bp 5 /* Analog Comparator 1 State bit position. */ - -#define AC_AC0STATE_bm 0x10 /* Analog Comparator 0 State bit mask. */ -#define AC_AC0STATE_bp 4 /* Analog Comparator 0 State bit position. */ - -#define AC_WIF_bm 0x04 /* Window Mode Interrupt Flag bit mask. */ -#define AC_WIF_bp 2 /* Window Mode Interrupt Flag bit position. */ - -#define AC_AC1IF_bm 0x02 /* Analog Comparator 1 Interrupt Flag bit mask. */ -#define AC_AC1IF_bp 1 /* Analog Comparator 1 Interrupt Flag bit position. */ - -#define AC_AC0IF_bm 0x01 /* Analog Comparator 0 Interrupt Flag bit mask. */ -#define AC_AC0IF_bp 0 /* Analog Comparator 0 Interrupt Flag bit position. */ - -/* RTC - Real-Time Counter */ -/* RTC.CTRL bit masks and bit positions */ -#define RTC_PRESCALER_gm 0x07 /* Prescaling Factor group mask. */ -#define RTC_PRESCALER_gp 0 /* Prescaling Factor group position. */ -#define RTC_PRESCALER0_bm (1<<0) /* Prescaling Factor bit 0 mask. */ -#define RTC_PRESCALER0_bp 0 /* Prescaling Factor bit 0 position. */ -#define RTC_PRESCALER1_bm (1<<1) /* Prescaling Factor bit 1 mask. */ -#define RTC_PRESCALER1_bp 1 /* Prescaling Factor bit 1 position. */ -#define RTC_PRESCALER2_bm (1<<2) /* Prescaling Factor bit 2 mask. */ -#define RTC_PRESCALER2_bp 2 /* Prescaling Factor bit 2 position. */ - -/* RTC.STATUS bit masks and bit positions */ -#define RTC_SYNCBUSY_bm 0x01 /* Synchronization Busy Flag bit mask. */ -#define RTC_SYNCBUSY_bp 0 /* Synchronization Busy Flag bit position. */ - -/* RTC.INTCTRL bit masks and bit positions */ -#define RTC_COMPINTLVL_gm 0x0C /* Compare Match Interrupt Level group mask. */ -#define RTC_COMPINTLVL_gp 2 /* Compare Match Interrupt Level group position. */ -#define RTC_COMPINTLVL0_bm (1<<2) /* Compare Match Interrupt Level bit 0 mask. */ -#define RTC_COMPINTLVL0_bp 2 /* Compare Match Interrupt Level bit 0 position. */ -#define RTC_COMPINTLVL1_bm (1<<3) /* Compare Match Interrupt Level bit 1 mask. */ -#define RTC_COMPINTLVL1_bp 3 /* Compare Match Interrupt Level bit 1 position. */ - -#define RTC_OVFINTLVL_gm 0x03 /* Overflow Interrupt Level group mask. */ -#define RTC_OVFINTLVL_gp 0 /* Overflow Interrupt Level group position. */ -#define RTC_OVFINTLVL0_bm (1<<0) /* Overflow Interrupt Level bit 0 mask. */ -#define RTC_OVFINTLVL0_bp 0 /* Overflow Interrupt Level bit 0 position. */ -#define RTC_OVFINTLVL1_bm (1<<1) /* Overflow Interrupt Level bit 1 mask. */ -#define RTC_OVFINTLVL1_bp 1 /* Overflow Interrupt Level bit 1 position. */ - -/* RTC.INTFLAGS bit masks and bit positions */ -#define RTC_COMPIF_bm 0x02 /* Compare Match Interrupt Flag bit mask. */ -#define RTC_COMPIF_bp 1 /* Compare Match Interrupt Flag bit position. */ - -#define RTC_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ -#define RTC_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ - -/* TWI - Two-Wire Interface */ -/* TWI_MASTER.CTRLA bit masks and bit positions */ -#define TWI_MASTER_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ -#define TWI_MASTER_INTLVL_gp 6 /* Interrupt Level group position. */ -#define TWI_MASTER_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ -#define TWI_MASTER_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ -#define TWI_MASTER_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ -#define TWI_MASTER_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ - -#define TWI_MASTER_RIEN_bm 0x20 /* Read Interrupt Enable bit mask. */ -#define TWI_MASTER_RIEN_bp 5 /* Read Interrupt Enable bit position. */ - -#define TWI_MASTER_WIEN_bm 0x10 /* Write Interrupt Enable bit mask. */ -#define TWI_MASTER_WIEN_bp 4 /* Write Interrupt Enable bit position. */ - -#define TWI_MASTER_ENABLE_bm 0x08 /* Enable TWI Master bit mask. */ -#define TWI_MASTER_ENABLE_bp 3 /* Enable TWI Master bit position. */ - -/* TWI_MASTER.CTRLB bit masks and bit positions */ -#define TWI_MASTER_TIMEOUT_gm 0x0C /* Inactive Bus Timeout group mask. */ -#define TWI_MASTER_TIMEOUT_gp 2 /* Inactive Bus Timeout group position. */ -#define TWI_MASTER_TIMEOUT0_bm (1<<2) /* Inactive Bus Timeout bit 0 mask. */ -#define TWI_MASTER_TIMEOUT0_bp 2 /* Inactive Bus Timeout bit 0 position. */ -#define TWI_MASTER_TIMEOUT1_bm (1<<3) /* Inactive Bus Timeout bit 1 mask. */ -#define TWI_MASTER_TIMEOUT1_bp 3 /* Inactive Bus Timeout bit 1 position. */ - -#define TWI_MASTER_QCEN_bm 0x02 /* Quick Command Enable bit mask. */ -#define TWI_MASTER_QCEN_bp 1 /* Quick Command Enable bit position. */ - -#define TWI_MASTER_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ -#define TWI_MASTER_SMEN_bp 0 /* Smart Mode Enable bit position. */ - -/* TWI_MASTER.CTRLC bit masks and bit positions */ -#define TWI_MASTER_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ -#define TWI_MASTER_ACKACT_bp 2 /* Acknowledge Action bit position. */ - -#define TWI_MASTER_CMD_gm 0x03 /* Command group mask. */ -#define TWI_MASTER_CMD_gp 0 /* Command group position. */ -#define TWI_MASTER_CMD0_bm (1<<0) /* Command bit 0 mask. */ -#define TWI_MASTER_CMD0_bp 0 /* Command bit 0 position. */ -#define TWI_MASTER_CMD1_bm (1<<1) /* Command bit 1 mask. */ -#define TWI_MASTER_CMD1_bp 1 /* Command bit 1 position. */ - -/* TWI_MASTER.STATUS bit masks and bit positions */ -#define TWI_MASTER_RIF_bm 0x80 /* Read Interrupt Flag bit mask. */ -#define TWI_MASTER_RIF_bp 7 /* Read Interrupt Flag bit position. */ - -#define TWI_MASTER_WIF_bm 0x40 /* Write Interrupt Flag bit mask. */ -#define TWI_MASTER_WIF_bp 6 /* Write Interrupt Flag bit position. */ - -#define TWI_MASTER_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ -#define TWI_MASTER_CLKHOLD_bp 5 /* Clock Hold bit position. */ - -#define TWI_MASTER_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ -#define TWI_MASTER_RXACK_bp 4 /* Received Acknowledge bit position. */ - -#define TWI_MASTER_ARBLOST_bm 0x08 /* Arbitration Lost bit mask. */ -#define TWI_MASTER_ARBLOST_bp 3 /* Arbitration Lost bit position. */ - -#define TWI_MASTER_BUSERR_bm 0x04 /* Bus Error bit mask. */ -#define TWI_MASTER_BUSERR_bp 2 /* Bus Error bit position. */ - -#define TWI_MASTER_BUSSTATE_gm 0x03 /* Bus State group mask. */ -#define TWI_MASTER_BUSSTATE_gp 0 /* Bus State group position. */ -#define TWI_MASTER_BUSSTATE0_bm (1<<0) /* Bus State bit 0 mask. */ -#define TWI_MASTER_BUSSTATE0_bp 0 /* Bus State bit 0 position. */ -#define TWI_MASTER_BUSSTATE1_bm (1<<1) /* Bus State bit 1 mask. */ -#define TWI_MASTER_BUSSTATE1_bp 1 /* Bus State bit 1 position. */ - -/* TWI_SLAVE.CTRLA bit masks and bit positions */ -#define TWI_SLAVE_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ -#define TWI_SLAVE_INTLVL_gp 6 /* Interrupt Level group position. */ -#define TWI_SLAVE_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ -#define TWI_SLAVE_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ -#define TWI_SLAVE_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ -#define TWI_SLAVE_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ - -#define TWI_SLAVE_DIEN_bm 0x20 /* Data Interrupt Enable bit mask. */ -#define TWI_SLAVE_DIEN_bp 5 /* Data Interrupt Enable bit position. */ - -#define TWI_SLAVE_APIEN_bm 0x10 /* Address/Stop Interrupt Enable bit mask. */ -#define TWI_SLAVE_APIEN_bp 4 /* Address/Stop Interrupt Enable bit position. */ - -#define TWI_SLAVE_ENABLE_bm 0x08 /* Enable TWI Slave bit mask. */ -#define TWI_SLAVE_ENABLE_bp 3 /* Enable TWI Slave bit position. */ - -#define TWI_SLAVE_PIEN_bm 0x04 /* Stop Interrupt Enable bit mask. */ -#define TWI_SLAVE_PIEN_bp 2 /* Stop Interrupt Enable bit position. */ - -#define TWI_SLAVE_PMEN_bm 0x02 /* Promiscuous Mode Enable bit mask. */ -#define TWI_SLAVE_PMEN_bp 1 /* Promiscuous Mode Enable bit position. */ - -#define TWI_SLAVE_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ -#define TWI_SLAVE_SMEN_bp 0 /* Smart Mode Enable bit position. */ - -/* TWI_SLAVE.CTRLB bit masks and bit positions */ -#define TWI_SLAVE_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ -#define TWI_SLAVE_ACKACT_bp 2 /* Acknowledge Action bit position. */ - -#define TWI_SLAVE_CMD_gm 0x03 /* Command group mask. */ -#define TWI_SLAVE_CMD_gp 0 /* Command group position. */ -#define TWI_SLAVE_CMD0_bm (1<<0) /* Command bit 0 mask. */ -#define TWI_SLAVE_CMD0_bp 0 /* Command bit 0 position. */ -#define TWI_SLAVE_CMD1_bm (1<<1) /* Command bit 1 mask. */ -#define TWI_SLAVE_CMD1_bp 1 /* Command bit 1 position. */ - -/* TWI_SLAVE.STATUS bit masks and bit positions */ -#define TWI_SLAVE_DIF_bm 0x80 /* Data Interrupt Flag bit mask. */ -#define TWI_SLAVE_DIF_bp 7 /* Data Interrupt Flag bit position. */ - -#define TWI_SLAVE_APIF_bm 0x40 /* Address/Stop Interrupt Flag bit mask. */ -#define TWI_SLAVE_APIF_bp 6 /* Address/Stop Interrupt Flag bit position. */ - -#define TWI_SLAVE_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ -#define TWI_SLAVE_CLKHOLD_bp 5 /* Clock Hold bit position. */ - -#define TWI_SLAVE_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ -#define TWI_SLAVE_RXACK_bp 4 /* Received Acknowledge bit position. */ - -#define TWI_SLAVE_COLL_bm 0x08 /* Collision bit mask. */ -#define TWI_SLAVE_COLL_bp 3 /* Collision bit position. */ - -#define TWI_SLAVE_BUSERR_bm 0x04 /* Bus Error bit mask. */ -#define TWI_SLAVE_BUSERR_bp 2 /* Bus Error bit position. */ - -#define TWI_SLAVE_DIR_bm 0x02 /* Read/Write Direction bit mask. */ -#define TWI_SLAVE_DIR_bp 1 /* Read/Write Direction bit position. */ - -#define TWI_SLAVE_AP_bm 0x01 /* Slave Address or Stop bit mask. */ -#define TWI_SLAVE_AP_bp 0 /* Slave Address or Stop bit position. */ - -/* TWI_SLAVE.ADDRMASK bit masks and bit positions */ -#define TWI_SLAVE_ADDRMASK_gm 0xFE /* Address Mask group mask. */ -#define TWI_SLAVE_ADDRMASK_gp 1 /* Address Mask group position. */ -#define TWI_SLAVE_ADDRMASK0_bm (1<<1) /* Address Mask bit 0 mask. */ -#define TWI_SLAVE_ADDRMASK0_bp 1 /* Address Mask bit 0 position. */ -#define TWI_SLAVE_ADDRMASK1_bm (1<<2) /* Address Mask bit 1 mask. */ -#define TWI_SLAVE_ADDRMASK1_bp 2 /* Address Mask bit 1 position. */ -#define TWI_SLAVE_ADDRMASK2_bm (1<<3) /* Address Mask bit 2 mask. */ -#define TWI_SLAVE_ADDRMASK2_bp 3 /* Address Mask bit 2 position. */ -#define TWI_SLAVE_ADDRMASK3_bm (1<<4) /* Address Mask bit 3 mask. */ -#define TWI_SLAVE_ADDRMASK3_bp 4 /* Address Mask bit 3 position. */ -#define TWI_SLAVE_ADDRMASK4_bm (1<<5) /* Address Mask bit 4 mask. */ -#define TWI_SLAVE_ADDRMASK4_bp 5 /* Address Mask bit 4 position. */ -#define TWI_SLAVE_ADDRMASK5_bm (1<<6) /* Address Mask bit 5 mask. */ -#define TWI_SLAVE_ADDRMASK5_bp 6 /* Address Mask bit 5 position. */ -#define TWI_SLAVE_ADDRMASK6_bm (1<<7) /* Address Mask bit 6 mask. */ -#define TWI_SLAVE_ADDRMASK6_bp 7 /* Address Mask bit 6 position. */ - -#define TWI_SLAVE_ADDREN_bm 0x01 /* Address Enable bit mask. */ -#define TWI_SLAVE_ADDREN_bp 0 /* Address Enable bit position. */ - -/* TWI.CTRL bit masks and bit positions */ -#define TWI_SDAHOLD_gm 0x06 /* SDA Hold Time Enable group mask. */ -#define TWI_SDAHOLD_gp 1 /* SDA Hold Time Enable group position. */ -#define TWI_SDAHOLD0_bm (1<<1) /* SDA Hold Time Enable bit 0 mask. */ -#define TWI_SDAHOLD0_bp 1 /* SDA Hold Time Enable bit 0 position. */ -#define TWI_SDAHOLD1_bm (1<<2) /* SDA Hold Time Enable bit 1 mask. */ -#define TWI_SDAHOLD1_bp 2 /* SDA Hold Time Enable bit 1 position. */ - -#define TWI_EDIEN_bm 0x01 /* External Driver Interface Enable bit mask. */ -#define TWI_EDIEN_bp 0 /* External Driver Interface Enable bit position. */ - -/* USB - USB */ -/* USB_EP.STATUS bit masks and bit positions */ -#define USB_EP_STALLF_bm 0x80 /* Endpoint Stall Flag bit mask. */ -#define USB_EP_STALLF_bp 7 /* Endpoint Stall Flag bit position. */ - -#define USB_EP_CRC_bm 0x80 /* CRC Error Flag bit mask. */ -#define USB_EP_CRC_bp 7 /* CRC Error Flag bit position. */ - -#define USB_EP_UNF_bm 0x40 /* Underflow Enpoint FLag bit mask. */ -#define USB_EP_UNF_bp 6 /* Underflow Enpoint FLag bit position. */ - -#define USB_EP_OVF_bm 0x40 /* Overflow Enpoint Flag for Output Endpoints bit mask. */ -#define USB_EP_OVF_bp 6 /* Overflow Enpoint Flag for Output Endpoints bit position. */ - -#define USB_EP_TRNCOMPL0_bm 0x20 /* Transaction Complete 0 Flag bit mask. */ -#define USB_EP_TRNCOMPL0_bp 5 /* Transaction Complete 0 Flag bit position. */ - -#define USB_EP_TRNCOMPL1_bm 0x10 /* Transaction Complete 1 Flag bit mask. */ -#define USB_EP_TRNCOMPL1_bp 4 /* Transaction Complete 1 Flag bit position. */ - -#define USB_EP_SETUP_bm 0x10 /* SETUP Transaction Complete Flag bit mask. */ -#define USB_EP_SETUP_bp 4 /* SETUP Transaction Complete Flag bit position. */ - -#define USB_EP_BANK_bm 0x08 /* Bank Select bit mask. */ -#define USB_EP_BANK_bp 3 /* Bank Select bit position. */ - -#define USB_EP_BUSNACK1_bm 0x04 /* Data Buffer 1 Not Acknowledge bit mask. */ -#define USB_EP_BUSNACK1_bp 2 /* Data Buffer 1 Not Acknowledge bit position. */ - -#define USB_EP_BUSNACK0_bm 0x02 /* Data Buffer 0 Not Acknowledge bit mask. */ -#define USB_EP_BUSNACK0_bp 1 /* Data Buffer 0 Not Acknowledge bit position. */ - -#define USB_EP_TOGGLE_bm 0x01 /* Data Toggle bit mask. */ -#define USB_EP_TOGGLE_bp 0 /* Data Toggle bit position. */ - -/* USB_EP.CTRL bit masks and bit positions */ -#define USB_EP_TYPE_gm 0xC0 /* Endpoint Type group mask. */ -#define USB_EP_TYPE_gp 6 /* Endpoint Type group position. */ -#define USB_EP_TYPE0_bm (1<<6) /* Endpoint Type bit 0 mask. */ -#define USB_EP_TYPE0_bp 6 /* Endpoint Type bit 0 position. */ -#define USB_EP_TYPE1_bm (1<<7) /* Endpoint Type bit 1 mask. */ -#define USB_EP_TYPE1_bp 7 /* Endpoint Type bit 1 position. */ - -#define USB_EP_MULTIPKT_bm 0x20 /* Multi Packet Transfer Enable bit mask. */ -#define USB_EP_MULTIPKT_bp 5 /* Multi Packet Transfer Enable bit position. */ - -#define USB_EP_PINGPONG_bm 0x10 /* Ping-Pong Enable bit mask. */ -#define USB_EP_PINGPONG_bp 4 /* Ping-Pong Enable bit position. */ - -#define USB_EP_INTDSBL_bm 0x08 /* Interrupt Disable bit mask. */ -#define USB_EP_INTDSBL_bp 3 /* Interrupt Disable bit position. */ - -#define USB_EP_STALL_bm 0x04 /* Data Stall bit mask. */ -#define USB_EP_STALL_bp 2 /* Data Stall bit position. */ - -#define USB_EP_BUFSIZE_gm 0x07 /* Data Buffer Size group mask. */ -#define USB_EP_BUFSIZE_gp 0 /* Data Buffer Size group position. */ -#define USB_EP_BUFSIZE0_bm (1<<0) /* Data Buffer Size bit 0 mask. */ -#define USB_EP_BUFSIZE0_bp 0 /* Data Buffer Size bit 0 position. */ -#define USB_EP_BUFSIZE1_bm (1<<1) /* Data Buffer Size bit 1 mask. */ -#define USB_EP_BUFSIZE1_bp 1 /* Data Buffer Size bit 1 position. */ -#define USB_EP_BUFSIZE2_bm (1<<2) /* Data Buffer Size bit 2 mask. */ -#define USB_EP_BUFSIZE2_bp 2 /* Data Buffer Size bit 2 position. */ - -/* USB_EP.CNT bit masks and bit positions */ -#define USB_EP_ZLP_bm 0x8000 /* Zero Length Packet bit mask. */ -#define USB_EP_ZLP_bp 15 /* Zero Length Packet bit position. */ - -/* USB.CTRLA bit masks and bit positions */ -#define USB_ENABLE_bm 0x80 /* USB Enable bit mask. */ -#define USB_ENABLE_bp 7 /* USB Enable bit position. */ - -#define USB_SPEED_bm 0x40 /* Speed Select bit mask. */ -#define USB_SPEED_bp 6 /* Speed Select bit position. */ - -#define USB_FIFOEN_bm 0x20 /* USB FIFO Enable bit mask. */ -#define USB_FIFOEN_bp 5 /* USB FIFO Enable bit position. */ - -#define USB_STFRNUM_bm 0x10 /* Store Frame Number Enable bit mask. */ -#define USB_STFRNUM_bp 4 /* Store Frame Number Enable bit position. */ - -#define USB_MAXEP_gm 0x0F /* Maximum Endpoint Addresses group mask. */ -#define USB_MAXEP_gp 0 /* Maximum Endpoint Addresses group position. */ -#define USB_MAXEP0_bm (1<<0) /* Maximum Endpoint Addresses bit 0 mask. */ -#define USB_MAXEP0_bp 0 /* Maximum Endpoint Addresses bit 0 position. */ -#define USB_MAXEP1_bm (1<<1) /* Maximum Endpoint Addresses bit 1 mask. */ -#define USB_MAXEP1_bp 1 /* Maximum Endpoint Addresses bit 1 position. */ -#define USB_MAXEP2_bm (1<<2) /* Maximum Endpoint Addresses bit 2 mask. */ -#define USB_MAXEP2_bp 2 /* Maximum Endpoint Addresses bit 2 position. */ -#define USB_MAXEP3_bm (1<<3) /* Maximum Endpoint Addresses bit 3 mask. */ -#define USB_MAXEP3_bp 3 /* Maximum Endpoint Addresses bit 3 position. */ - -/* USB.CTRLB bit masks and bit positions */ -#define USB_PULLRST_bm 0x10 /* Pull during Reset bit mask. */ -#define USB_PULLRST_bp 4 /* Pull during Reset bit position. */ - -#define USB_RWAKEUP_bm 0x04 /* Remote Wake-up bit mask. */ -#define USB_RWAKEUP_bp 2 /* Remote Wake-up bit position. */ - -#define USB_GNACK_bm 0x02 /* Global NACK bit mask. */ -#define USB_GNACK_bp 1 /* Global NACK bit position. */ - -#define USB_ATTACH_bm 0x01 /* Attach bit mask. */ -#define USB_ATTACH_bp 0 /* Attach bit position. */ - -/* USB.STATUS bit masks and bit positions */ -#define USB_URESUME_bm 0x08 /* Upstream Resume bit mask. */ -#define USB_URESUME_bp 3 /* Upstream Resume bit position. */ - -#define USB_RESUME_bm 0x04 /* Resume bit mask. */ -#define USB_RESUME_bp 2 /* Resume bit position. */ - -#define USB_SUSPEND_bm 0x02 /* Bus Suspended bit mask. */ -#define USB_SUSPEND_bp 1 /* Bus Suspended bit position. */ - -#define USB_BUSRST_bm 0x01 /* Bus Reset bit mask. */ -#define USB_BUSRST_bp 0 /* Bus Reset bit position. */ - -/* USB.ADDR bit masks and bit positions */ -#define USB_ADDR_gm 0x7F /* Device Address group mask. */ -#define USB_ADDR_gp 0 /* Device Address group position. */ -#define USB_ADDR0_bm (1<<0) /* Device Address bit 0 mask. */ -#define USB_ADDR0_bp 0 /* Device Address bit 0 position. */ -#define USB_ADDR1_bm (1<<1) /* Device Address bit 1 mask. */ -#define USB_ADDR1_bp 1 /* Device Address bit 1 position. */ -#define USB_ADDR2_bm (1<<2) /* Device Address bit 2 mask. */ -#define USB_ADDR2_bp 2 /* Device Address bit 2 position. */ -#define USB_ADDR3_bm (1<<3) /* Device Address bit 3 mask. */ -#define USB_ADDR3_bp 3 /* Device Address bit 3 position. */ -#define USB_ADDR4_bm (1<<4) /* Device Address bit 4 mask. */ -#define USB_ADDR4_bp 4 /* Device Address bit 4 position. */ -#define USB_ADDR5_bm (1<<5) /* Device Address bit 5 mask. */ -#define USB_ADDR5_bp 5 /* Device Address bit 5 position. */ -#define USB_ADDR6_bm (1<<6) /* Device Address bit 6 mask. */ -#define USB_ADDR6_bp 6 /* Device Address bit 6 position. */ - -/* USB.FIFOWP bit masks and bit positions */ -#define USB_FIFOWP_gm 0x1F /* FIFO Write Pointer group mask. */ -#define USB_FIFOWP_gp 0 /* FIFO Write Pointer group position. */ -#define USB_FIFOWP0_bm (1<<0) /* FIFO Write Pointer bit 0 mask. */ -#define USB_FIFOWP0_bp 0 /* FIFO Write Pointer bit 0 position. */ -#define USB_FIFOWP1_bm (1<<1) /* FIFO Write Pointer bit 1 mask. */ -#define USB_FIFOWP1_bp 1 /* FIFO Write Pointer bit 1 position. */ -#define USB_FIFOWP2_bm (1<<2) /* FIFO Write Pointer bit 2 mask. */ -#define USB_FIFOWP2_bp 2 /* FIFO Write Pointer bit 2 position. */ -#define USB_FIFOWP3_bm (1<<3) /* FIFO Write Pointer bit 3 mask. */ -#define USB_FIFOWP3_bp 3 /* FIFO Write Pointer bit 3 position. */ -#define USB_FIFOWP4_bm (1<<4) /* FIFO Write Pointer bit 4 mask. */ -#define USB_FIFOWP4_bp 4 /* FIFO Write Pointer bit 4 position. */ - -/* USB.FIFORP bit masks and bit positions */ -#define USB_FIFORP_gm 0x1F /* FIFO Read Pointer group mask. */ -#define USB_FIFORP_gp 0 /* FIFO Read Pointer group position. */ -#define USB_FIFORP0_bm (1<<0) /* FIFO Read Pointer bit 0 mask. */ -#define USB_FIFORP0_bp 0 /* FIFO Read Pointer bit 0 position. */ -#define USB_FIFORP1_bm (1<<1) /* FIFO Read Pointer bit 1 mask. */ -#define USB_FIFORP1_bp 1 /* FIFO Read Pointer bit 1 position. */ -#define USB_FIFORP2_bm (1<<2) /* FIFO Read Pointer bit 2 mask. */ -#define USB_FIFORP2_bp 2 /* FIFO Read Pointer bit 2 position. */ -#define USB_FIFORP3_bm (1<<3) /* FIFO Read Pointer bit 3 mask. */ -#define USB_FIFORP3_bp 3 /* FIFO Read Pointer bit 3 position. */ -#define USB_FIFORP4_bm (1<<4) /* FIFO Read Pointer bit 4 mask. */ -#define USB_FIFORP4_bp 4 /* FIFO Read Pointer bit 4 position. */ - -/* USB.INTCTRLA bit masks and bit positions */ -#define USB_SOFIE_bm 0x80 /* Start Of Frame Interrupt Enable bit mask. */ -#define USB_SOFIE_bp 7 /* Start Of Frame Interrupt Enable bit position. */ - -#define USB_BUSEVIE_bm 0x40 /* Bus Event Interrupt Enable bit mask. */ -#define USB_BUSEVIE_bp 6 /* Bus Event Interrupt Enable bit position. */ - -#define USB_BUSERRIE_bm 0x20 /* Bus Error Interrupt Enable bit mask. */ -#define USB_BUSERRIE_bp 5 /* Bus Error Interrupt Enable bit position. */ - -#define USB_STALLIE_bm 0x10 /* STALL Interrupt Enable bit mask. */ -#define USB_STALLIE_bp 4 /* STALL Interrupt Enable bit position. */ - -#define USB_INTLVL_gm 0x03 /* Interrupt Level group mask. */ -#define USB_INTLVL_gp 0 /* Interrupt Level group position. */ -#define USB_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */ -#define USB_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */ -#define USB_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ -#define USB_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */ - -/* USB.INTCTRLB bit masks and bit positions */ -#define USB_TRNIE_bm 0x02 /* Transaction Complete Interrupt Enable bit mask. */ -#define USB_TRNIE_bp 1 /* Transaction Complete Interrupt Enable bit position. */ - -#define USB_SETUPIE_bm 0x01 /* SETUP Transaction Complete Interrupt Enable bit mask. */ -#define USB_SETUPIE_bp 0 /* SETUP Transaction Complete Interrupt Enable bit position. */ - -/* USB.INTFLAGSACLR bit masks and bit positions */ -#define USB_SOFIF_bm 0x80 /* Start Of Frame Interrupt Flag bit mask. */ -#define USB_SOFIF_bp 7 /* Start Of Frame Interrupt Flag bit position. */ - -#define USB_SUSPENDIF_bm 0x40 /* Suspend Interrupt Flag bit mask. */ -#define USB_SUSPENDIF_bp 6 /* Suspend Interrupt Flag bit position. */ - -#define USB_RESUMEIF_bm 0x20 /* Resume Interrupt Flag bit mask. */ -#define USB_RESUMEIF_bp 5 /* Resume Interrupt Flag bit position. */ - -#define USB_RSTIF_bm 0x10 /* Reset Interrupt Flag bit mask. */ -#define USB_RSTIF_bp 4 /* Reset Interrupt Flag bit position. */ - -#define USB_CRCIF_bm 0x08 /* Isochronous CRC Error Interrupt Flag bit mask. */ -#define USB_CRCIF_bp 3 /* Isochronous CRC Error Interrupt Flag bit position. */ - -#define USB_UNFIF_bm 0x04 /* Underflow Interrupt Flag bit mask. */ -#define USB_UNFIF_bp 2 /* Underflow Interrupt Flag bit position. */ - -#define USB_OVFIF_bm 0x02 /* Overflow Interrupt Flag bit mask. */ -#define USB_OVFIF_bp 1 /* Overflow Interrupt Flag bit position. */ - -#define USB_STALLIF_bm 0x01 /* STALL Interrupt Flag bit mask. */ -#define USB_STALLIF_bp 0 /* STALL Interrupt Flag bit position. */ - -/* USB.INTFLAGSASET bit masks and bit positions */ -/* USB_SOFIF Predefined. */ -/* USB_SOFIF Predefined. */ - -/* USB_SUSPENDIF Predefined. */ -/* USB_SUSPENDIF Predefined. */ - -/* USB_RESUMEIF Predefined. */ -/* USB_RESUMEIF Predefined. */ - -/* USB_RSTIF Predefined. */ -/* USB_RSTIF Predefined. */ - -/* USB_CRCIF Predefined. */ -/* USB_CRCIF Predefined. */ - -/* USB_UNFIF Predefined. */ -/* USB_UNFIF Predefined. */ - -/* USB_OVFIF Predefined. */ -/* USB_OVFIF Predefined. */ - -/* USB_STALLIF Predefined. */ -/* USB_STALLIF Predefined. */ - -/* USB.INTFLAGSBCLR bit masks and bit positions */ -#define USB_TRNIF_bm 0x02 /* Transaction Complete Interrupt Flag bit mask. */ -#define USB_TRNIF_bp 1 /* Transaction Complete Interrupt Flag bit position. */ - -#define USB_SETUPIF_bm 0x01 /* SETUP Transaction Complete Interrupt Flag bit mask. */ -#define USB_SETUPIF_bp 0 /* SETUP Transaction Complete Interrupt Flag bit position. */ - -/* USB.INTFLAGSBSET bit masks and bit positions */ -/* USB_TRNIF Predefined. */ -/* USB_TRNIF Predefined. */ - -/* USB_SETUPIF Predefined. */ -/* USB_SETUPIF Predefined. */ - -/* PORT - I/O Port Configuration */ -/* PORT.INTCTRL bit masks and bit positions */ -#define PORT_INT1LVL_gm 0x0C /* Port Interrupt 1 Level group mask. */ -#define PORT_INT1LVL_gp 2 /* Port Interrupt 1 Level group position. */ -#define PORT_INT1LVL0_bm (1<<2) /* Port Interrupt 1 Level bit 0 mask. */ -#define PORT_INT1LVL0_bp 2 /* Port Interrupt 1 Level bit 0 position. */ -#define PORT_INT1LVL1_bm (1<<3) /* Port Interrupt 1 Level bit 1 mask. */ -#define PORT_INT1LVL1_bp 3 /* Port Interrupt 1 Level bit 1 position. */ - -#define PORT_INT0LVL_gm 0x03 /* Port Interrupt 0 Level group mask. */ -#define PORT_INT0LVL_gp 0 /* Port Interrupt 0 Level group position. */ -#define PORT_INT0LVL0_bm (1<<0) /* Port Interrupt 0 Level bit 0 mask. */ -#define PORT_INT0LVL0_bp 0 /* Port Interrupt 0 Level bit 0 position. */ -#define PORT_INT0LVL1_bm (1<<1) /* Port Interrupt 0 Level bit 1 mask. */ -#define PORT_INT0LVL1_bp 1 /* Port Interrupt 0 Level bit 1 position. */ - -/* PORT.INTFLAGS bit masks and bit positions */ -#define PORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ -#define PORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ - -#define PORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ -#define PORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ - -/* PORT.REMAP bit masks and bit positions */ -#define PORT_SPI_bm 0x20 /* SPI bit mask. */ -#define PORT_SPI_bp 5 /* SPI bit position. */ - -#define PORT_USART0_bm 0x10 /* USART0 bit mask. */ -#define PORT_USART0_bp 4 /* USART0 bit position. */ - -#define PORT_TC0D_bm 0x08 /* Timer/Counter 0 Output Compare D bit mask. */ -#define PORT_TC0D_bp 3 /* Timer/Counter 0 Output Compare D bit position. */ - -#define PORT_TC0C_bm 0x04 /* Timer/Counter 0 Output Compare C bit mask. */ -#define PORT_TC0C_bp 2 /* Timer/Counter 0 Output Compare C bit position. */ - -#define PORT_TC0B_bm 0x02 /* Timer/Counter 0 Output Compare B bit mask. */ -#define PORT_TC0B_bp 1 /* Timer/Counter 0 Output Compare B bit position. */ - -#define PORT_TC0A_bm 0x01 /* Timer/Counter 0 Output Compare A bit mask. */ -#define PORT_TC0A_bp 0 /* Timer/Counter 0 Output Compare A bit position. */ - -/* PORT.PIN0CTRL bit masks and bit positions */ -#define PORT_SRLEN_bm 0x80 /* Slew Rate Enable bit mask. */ -#define PORT_SRLEN_bp 7 /* Slew Rate Enable bit position. */ - -#define PORT_INVEN_bm 0x40 /* Inverted I/O Enable bit mask. */ -#define PORT_INVEN_bp 6 /* Inverted I/O Enable bit position. */ - -#define PORT_OPC_gm 0x38 /* Output/Pull Configuration group mask. */ -#define PORT_OPC_gp 3 /* Output/Pull Configuration group position. */ -#define PORT_OPC0_bm (1<<3) /* Output/Pull Configuration bit 0 mask. */ -#define PORT_OPC0_bp 3 /* Output/Pull Configuration bit 0 position. */ -#define PORT_OPC1_bm (1<<4) /* Output/Pull Configuration bit 1 mask. */ -#define PORT_OPC1_bp 4 /* Output/Pull Configuration bit 1 position. */ -#define PORT_OPC2_bm (1<<5) /* Output/Pull Configuration bit 2 mask. */ -#define PORT_OPC2_bp 5 /* Output/Pull Configuration bit 2 position. */ - -#define PORT_ISC_gm 0x07 /* Input/Sense Configuration group mask. */ -#define PORT_ISC_gp 0 /* Input/Sense Configuration group position. */ -#define PORT_ISC0_bm (1<<0) /* Input/Sense Configuration bit 0 mask. */ -#define PORT_ISC0_bp 0 /* Input/Sense Configuration bit 0 position. */ -#define PORT_ISC1_bm (1<<1) /* Input/Sense Configuration bit 1 mask. */ -#define PORT_ISC1_bp 1 /* Input/Sense Configuration bit 1 position. */ -#define PORT_ISC2_bm (1<<2) /* Input/Sense Configuration bit 2 mask. */ -#define PORT_ISC2_bp 2 /* Input/Sense Configuration bit 2 position. */ - -/* PORT.PIN1CTRL bit masks and bit positions */ -/* PORT_SRLEN Predefined. */ -/* PORT_SRLEN Predefined. */ - -/* PORT_INVEN Predefined. */ -/* PORT_INVEN Predefined. */ - -/* PORT_OPC Predefined. */ -/* PORT_OPC Predefined. */ - -/* PORT_ISC Predefined. */ -/* PORT_ISC Predefined. */ - -/* PORT.PIN2CTRL bit masks and bit positions */ -/* PORT_SRLEN Predefined. */ -/* PORT_SRLEN Predefined. */ - -/* PORT_INVEN Predefined. */ -/* PORT_INVEN Predefined. */ - -/* PORT_OPC Predefined. */ -/* PORT_OPC Predefined. */ - -/* PORT_ISC Predefined. */ -/* PORT_ISC Predefined. */ - -/* PORT.PIN3CTRL bit masks and bit positions */ -/* PORT_SRLEN Predefined. */ -/* PORT_SRLEN Predefined. */ - -/* PORT_INVEN Predefined. */ -/* PORT_INVEN Predefined. */ - -/* PORT_OPC Predefined. */ -/* PORT_OPC Predefined. */ - -/* PORT_ISC Predefined. */ -/* PORT_ISC Predefined. */ - -/* PORT.PIN4CTRL bit masks and bit positions */ -/* PORT_SRLEN Predefined. */ -/* PORT_SRLEN Predefined. */ - -/* PORT_INVEN Predefined. */ -/* PORT_INVEN Predefined. */ - -/* PORT_OPC Predefined. */ -/* PORT_OPC Predefined. */ - -/* PORT_ISC Predefined. */ -/* PORT_ISC Predefined. */ - -/* PORT.PIN5CTRL bit masks and bit positions */ -/* PORT_SRLEN Predefined. */ -/* PORT_SRLEN Predefined. */ - -/* PORT_INVEN Predefined. */ -/* PORT_INVEN Predefined. */ - -/* PORT_OPC Predefined. */ -/* PORT_OPC Predefined. */ - -/* PORT_ISC Predefined. */ -/* PORT_ISC Predefined. */ - -/* PORT.PIN6CTRL bit masks and bit positions */ -/* PORT_SRLEN Predefined. */ -/* PORT_SRLEN Predefined. */ - -/* PORT_INVEN Predefined. */ -/* PORT_INVEN Predefined. */ - -/* PORT_OPC Predefined. */ -/* PORT_OPC Predefined. */ - -/* PORT_ISC Predefined. */ -/* PORT_ISC Predefined. */ - -/* PORT.PIN7CTRL bit masks and bit positions */ -/* PORT_SRLEN Predefined. */ -/* PORT_SRLEN Predefined. */ - -/* PORT_INVEN Predefined. */ -/* PORT_INVEN Predefined. */ - -/* PORT_OPC Predefined. */ -/* PORT_OPC Predefined. */ - -/* PORT_ISC Predefined. */ -/* PORT_ISC Predefined. */ - -/* TC - 16-bit Timer/Counter With PWM */ -/* TC0.CTRLA bit masks and bit positions */ -#define TC0_CLKSEL_gm 0x0F /* Clock Selection group mask. */ -#define TC0_CLKSEL_gp 0 /* Clock Selection group position. */ -#define TC0_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ -#define TC0_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ -#define TC0_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ -#define TC0_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ -#define TC0_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ -#define TC0_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ -#define TC0_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ -#define TC0_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ - -/* TC0.CTRLB bit masks and bit positions */ -#define TC0_CCDEN_bm 0x80 /* Compare or Capture D Enable bit mask. */ -#define TC0_CCDEN_bp 7 /* Compare or Capture D Enable bit position. */ - -#define TC0_CCCEN_bm 0x40 /* Compare or Capture C Enable bit mask. */ -#define TC0_CCCEN_bp 6 /* Compare or Capture C Enable bit position. */ - -#define TC0_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ -#define TC0_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ - -#define TC0_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ -#define TC0_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ - -#define TC0_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ -#define TC0_WGMODE_gp 0 /* Waveform generation mode group position. */ -#define TC0_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ -#define TC0_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ -#define TC0_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ -#define TC0_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ -#define TC0_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ -#define TC0_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ - -/* TC0.CTRLC bit masks and bit positions */ -#define TC0_CMPD_bm 0x08 /* Compare D Output Value bit mask. */ -#define TC0_CMPD_bp 3 /* Compare D Output Value bit position. */ - -#define TC0_CMPC_bm 0x04 /* Compare C Output Value bit mask. */ -#define TC0_CMPC_bp 2 /* Compare C Output Value bit position. */ - -#define TC0_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ -#define TC0_CMPB_bp 1 /* Compare B Output Value bit position. */ - -#define TC0_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ -#define TC0_CMPA_bp 0 /* Compare A Output Value bit position. */ - -/* TC0.CTRLD bit masks and bit positions */ -#define TC0_EVACT_gm 0xE0 /* Event Action group mask. */ -#define TC0_EVACT_gp 5 /* Event Action group position. */ -#define TC0_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ -#define TC0_EVACT0_bp 5 /* Event Action bit 0 position. */ -#define TC0_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ -#define TC0_EVACT1_bp 6 /* Event Action bit 1 position. */ -#define TC0_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ -#define TC0_EVACT2_bp 7 /* Event Action bit 2 position. */ - -#define TC0_EVDLY_bm 0x10 /* Event Delay bit mask. */ -#define TC0_EVDLY_bp 4 /* Event Delay bit position. */ - -#define TC0_EVSEL_gm 0x0F /* Event Source Select group mask. */ -#define TC0_EVSEL_gp 0 /* Event Source Select group position. */ -#define TC0_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ -#define TC0_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ -#define TC0_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ -#define TC0_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ -#define TC0_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ -#define TC0_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ -#define TC0_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ -#define TC0_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ - -/* TC0.CTRLE bit masks and bit positions */ -#define TC0_BYTEM_gm 0x03 /* Byte Mode group mask. */ -#define TC0_BYTEM_gp 0 /* Byte Mode group position. */ -#define TC0_BYTEM0_bm (1<<0) /* Byte Mode bit 0 mask. */ -#define TC0_BYTEM0_bp 0 /* Byte Mode bit 0 position. */ -#define TC0_BYTEM1_bm (1<<1) /* Byte Mode bit 1 mask. */ -#define TC0_BYTEM1_bp 1 /* Byte Mode bit 1 position. */ - -/* TC0.INTCTRLA bit masks and bit positions */ -#define TC0_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ -#define TC0_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ -#define TC0_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ -#define TC0_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ -#define TC0_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ -#define TC0_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ - -#define TC0_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ -#define TC0_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ -#define TC0_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ -#define TC0_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ -#define TC0_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ -#define TC0_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ - -/* TC0.INTCTRLB bit masks and bit positions */ -#define TC0_CCDINTLVL_gm 0xC0 /* Compare or Capture D Interrupt Level group mask. */ -#define TC0_CCDINTLVL_gp 6 /* Compare or Capture D Interrupt Level group position. */ -#define TC0_CCDINTLVL0_bm (1<<6) /* Compare or Capture D Interrupt Level bit 0 mask. */ -#define TC0_CCDINTLVL0_bp 6 /* Compare or Capture D Interrupt Level bit 0 position. */ -#define TC0_CCDINTLVL1_bm (1<<7) /* Compare or Capture D Interrupt Level bit 1 mask. */ -#define TC0_CCDINTLVL1_bp 7 /* Compare or Capture D Interrupt Level bit 1 position. */ - -#define TC0_CCCINTLVL_gm 0x30 /* Compare or Capture C Interrupt Level group mask. */ -#define TC0_CCCINTLVL_gp 4 /* Compare or Capture C Interrupt Level group position. */ -#define TC0_CCCINTLVL0_bm (1<<4) /* Compare or Capture C Interrupt Level bit 0 mask. */ -#define TC0_CCCINTLVL0_bp 4 /* Compare or Capture C Interrupt Level bit 0 position. */ -#define TC0_CCCINTLVL1_bm (1<<5) /* Compare or Capture C Interrupt Level bit 1 mask. */ -#define TC0_CCCINTLVL1_bp 5 /* Compare or Capture C Interrupt Level bit 1 position. */ - -#define TC0_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ -#define TC0_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ -#define TC0_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ -#define TC0_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ -#define TC0_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ -#define TC0_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ - -#define TC0_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ -#define TC0_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ -#define TC0_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ -#define TC0_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ -#define TC0_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ -#define TC0_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ - -/* TC0.CTRLFCLR bit masks and bit positions */ -#define TC0_CMD_gm 0x0C /* Command group mask. */ -#define TC0_CMD_gp 2 /* Command group position. */ -#define TC0_CMD0_bm (1<<2) /* Command bit 0 mask. */ -#define TC0_CMD0_bp 2 /* Command bit 0 position. */ -#define TC0_CMD1_bm (1<<3) /* Command bit 1 mask. */ -#define TC0_CMD1_bp 3 /* Command bit 1 position. */ - -#define TC0_LUPD_bm 0x02 /* Lock Update bit mask. */ -#define TC0_LUPD_bp 1 /* Lock Update bit position. */ - -#define TC0_DIR_bm 0x01 /* Direction bit mask. */ -#define TC0_DIR_bp 0 /* Direction bit position. */ - -/* TC0.CTRLFSET bit masks and bit positions */ -/* TC0_CMD Predefined. */ -/* TC0_CMD Predefined. */ - -/* TC0_LUPD Predefined. */ -/* TC0_LUPD Predefined. */ - -/* TC0_DIR Predefined. */ -/* TC0_DIR Predefined. */ - -/* TC0.CTRLGCLR bit masks and bit positions */ -#define TC0_CCDBV_bm 0x10 /* Compare or Capture D Buffer Valid bit mask. */ -#define TC0_CCDBV_bp 4 /* Compare or Capture D Buffer Valid bit position. */ - -#define TC0_CCCBV_bm 0x08 /* Compare or Capture C Buffer Valid bit mask. */ -#define TC0_CCCBV_bp 3 /* Compare or Capture C Buffer Valid bit position. */ - -#define TC0_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ -#define TC0_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ - -#define TC0_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ -#define TC0_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ - -#define TC0_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ -#define TC0_PERBV_bp 0 /* Period Buffer Valid bit position. */ - -/* TC0.CTRLGSET bit masks and bit positions */ -/* TC0_CCDBV Predefined. */ -/* TC0_CCDBV Predefined. */ - -/* TC0_CCCBV Predefined. */ -/* TC0_CCCBV Predefined. */ - -/* TC0_CCBBV Predefined. */ -/* TC0_CCBBV Predefined. */ - -/* TC0_CCABV Predefined. */ -/* TC0_CCABV Predefined. */ - -/* TC0_PERBV Predefined. */ -/* TC0_PERBV Predefined. */ - -/* TC0.INTFLAGS bit masks and bit positions */ -#define TC0_CCDIF_bm 0x80 /* Compare or Capture D Interrupt Flag bit mask. */ -#define TC0_CCDIF_bp 7 /* Compare or Capture D Interrupt Flag bit position. */ - -#define TC0_CCCIF_bm 0x40 /* Compare or Capture C Interrupt Flag bit mask. */ -#define TC0_CCCIF_bp 6 /* Compare or Capture C Interrupt Flag bit position. */ - -#define TC0_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ -#define TC0_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ - -#define TC0_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ -#define TC0_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ - -#define TC0_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ -#define TC0_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ - -#define TC0_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ -#define TC0_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ - -/* TC1.CTRLA bit masks and bit positions */ -#define TC1_CLKSEL_gm 0x0F /* Clock Selection group mask. */ -#define TC1_CLKSEL_gp 0 /* Clock Selection group position. */ -#define TC1_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ -#define TC1_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ -#define TC1_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ -#define TC1_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ -#define TC1_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ -#define TC1_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ -#define TC1_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ -#define TC1_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ - -/* TC1.CTRLB bit masks and bit positions */ -#define TC1_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ -#define TC1_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ - -#define TC1_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ -#define TC1_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ - -#define TC1_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ -#define TC1_WGMODE_gp 0 /* Waveform generation mode group position. */ -#define TC1_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ -#define TC1_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ -#define TC1_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ -#define TC1_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ -#define TC1_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ -#define TC1_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ - -/* TC1.CTRLC bit masks and bit positions */ -#define TC1_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ -#define TC1_CMPB_bp 1 /* Compare B Output Value bit position. */ - -#define TC1_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ -#define TC1_CMPA_bp 0 /* Compare A Output Value bit position. */ - -/* TC1.CTRLD bit masks and bit positions */ -#define TC1_EVACT_gm 0xE0 /* Event Action group mask. */ -#define TC1_EVACT_gp 5 /* Event Action group position. */ -#define TC1_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ -#define TC1_EVACT0_bp 5 /* Event Action bit 0 position. */ -#define TC1_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ -#define TC1_EVACT1_bp 6 /* Event Action bit 1 position. */ -#define TC1_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ -#define TC1_EVACT2_bp 7 /* Event Action bit 2 position. */ - -#define TC1_EVDLY_bm 0x10 /* Event Delay bit mask. */ -#define TC1_EVDLY_bp 4 /* Event Delay bit position. */ - -#define TC1_EVSEL_gm 0x0F /* Event Source Select group mask. */ -#define TC1_EVSEL_gp 0 /* Event Source Select group position. */ -#define TC1_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ -#define TC1_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ -#define TC1_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ -#define TC1_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ -#define TC1_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ -#define TC1_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ -#define TC1_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ -#define TC1_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ - -/* TC1.CTRLE bit masks and bit positions */ -#define TC1_BYTEM_bm 0x01 /* Byte Mode bit mask. */ -#define TC1_BYTEM_bp 0 /* Byte Mode bit position. */ - -/* TC1.INTCTRLA bit masks and bit positions */ -#define TC1_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ -#define TC1_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ -#define TC1_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ -#define TC1_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ -#define TC1_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ -#define TC1_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ - -#define TC1_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ -#define TC1_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ -#define TC1_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ -#define TC1_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ -#define TC1_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ -#define TC1_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ - -/* TC1.INTCTRLB bit masks and bit positions */ -#define TC1_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ -#define TC1_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ -#define TC1_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ -#define TC1_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ -#define TC1_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ -#define TC1_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ - -#define TC1_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ -#define TC1_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ -#define TC1_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ -#define TC1_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ -#define TC1_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ -#define TC1_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ - -/* TC1.CTRLFCLR bit masks and bit positions */ -#define TC1_CMD_gm 0x0C /* Command group mask. */ -#define TC1_CMD_gp 2 /* Command group position. */ -#define TC1_CMD0_bm (1<<2) /* Command bit 0 mask. */ -#define TC1_CMD0_bp 2 /* Command bit 0 position. */ -#define TC1_CMD1_bm (1<<3) /* Command bit 1 mask. */ -#define TC1_CMD1_bp 3 /* Command bit 1 position. */ - -#define TC1_LUPD_bm 0x02 /* Lock Update bit mask. */ -#define TC1_LUPD_bp 1 /* Lock Update bit position. */ - -#define TC1_DIR_bm 0x01 /* Direction bit mask. */ -#define TC1_DIR_bp 0 /* Direction bit position. */ - -/* TC1.CTRLFSET bit masks and bit positions */ -/* TC1_CMD Predefined. */ -/* TC1_CMD Predefined. */ - -/* TC1_LUPD Predefined. */ -/* TC1_LUPD Predefined. */ - -/* TC1_DIR Predefined. */ -/* TC1_DIR Predefined. */ - -/* TC1.CTRLGCLR bit masks and bit positions */ -#define TC1_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ -#define TC1_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ - -#define TC1_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ -#define TC1_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ - -#define TC1_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ -#define TC1_PERBV_bp 0 /* Period Buffer Valid bit position. */ - -/* TC1.CTRLGSET bit masks and bit positions */ -/* TC1_CCBBV Predefined. */ -/* TC1_CCBBV Predefined. */ - -/* TC1_CCABV Predefined. */ -/* TC1_CCABV Predefined. */ - -/* TC1_PERBV Predefined. */ -/* TC1_PERBV Predefined. */ - -/* TC1.INTFLAGS bit masks and bit positions */ -#define TC1_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ -#define TC1_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ - -#define TC1_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ -#define TC1_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ - -#define TC1_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ -#define TC1_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ - -#define TC1_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ -#define TC1_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ - -/* TC2 - 16-bit Timer/Counter type 2 */ -/* TC2.CTRLA bit masks and bit positions */ -#define TC2_CLKSEL_gm 0x0F /* Clock Selection group mask. */ -#define TC2_CLKSEL_gp 0 /* Clock Selection group position. */ -#define TC2_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ -#define TC2_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ -#define TC2_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ -#define TC2_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ -#define TC2_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ -#define TC2_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ -#define TC2_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ -#define TC2_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ - -/* TC2.CTRLB bit masks and bit positions */ -#define TC2_HCMPDEN_bm 0x80 /* High Byte Compare D Enable bit mask. */ -#define TC2_HCMPDEN_bp 7 /* High Byte Compare D Enable bit position. */ - -#define TC2_HCMPCEN_bm 0x40 /* High Byte Compare C Enable bit mask. */ -#define TC2_HCMPCEN_bp 6 /* High Byte Compare C Enable bit position. */ - -#define TC2_HCMPBEN_bm 0x20 /* High Byte Compare B Enable bit mask. */ -#define TC2_HCMPBEN_bp 5 /* High Byte Compare B Enable bit position. */ - -#define TC2_HCMPAEN_bm 0x10 /* High Byte Compare A Enable bit mask. */ -#define TC2_HCMPAEN_bp 4 /* High Byte Compare A Enable bit position. */ - -#define TC2_LCMPDEN_bm 0x08 /* Low Byte Compare D Enable bit mask. */ -#define TC2_LCMPDEN_bp 3 /* Low Byte Compare D Enable bit position. */ - -#define TC2_LCMPCEN_bm 0x04 /* Low Byte Compare C Enable bit mask. */ -#define TC2_LCMPCEN_bp 2 /* Low Byte Compare C Enable bit position. */ - -#define TC2_LCMPBEN_bm 0x02 /* Low Byte Compare B Enable bit mask. */ -#define TC2_LCMPBEN_bp 1 /* Low Byte Compare B Enable bit position. */ - -#define TC2_LCMPAEN_bm 0x01 /* Low Byte Compare A Enable bit mask. */ -#define TC2_LCMPAEN_bp 0 /* Low Byte Compare A Enable bit position. */ - -/* TC2.CTRLC bit masks and bit positions */ -#define TC2_HCMPD_bm 0x80 /* High Byte Compare D Output Value bit mask. */ -#define TC2_HCMPD_bp 7 /* High Byte Compare D Output Value bit position. */ - -#define TC2_HCMPC_bm 0x40 /* High Byte Compare C Output Value bit mask. */ -#define TC2_HCMPC_bp 6 /* High Byte Compare C Output Value bit position. */ - -#define TC2_HCMPB_bm 0x20 /* High Byte Compare B Output Value bit mask. */ -#define TC2_HCMPB_bp 5 /* High Byte Compare B Output Value bit position. */ - -#define TC2_HCMPA_bm 0x10 /* High Byte Compare A Output Value bit mask. */ -#define TC2_HCMPA_bp 4 /* High Byte Compare A Output Value bit position. */ - -#define TC2_LCMPD_bm 0x08 /* Low Byte Compare D Output Value bit mask. */ -#define TC2_LCMPD_bp 3 /* Low Byte Compare D Output Value bit position. */ - -#define TC2_LCMPC_bm 0x04 /* Low Byte Compare C Output Value bit mask. */ -#define TC2_LCMPC_bp 2 /* Low Byte Compare C Output Value bit position. */ - -#define TC2_LCMPB_bm 0x02 /* Low Byte Compare B Output Value bit mask. */ -#define TC2_LCMPB_bp 1 /* Low Byte Compare B Output Value bit position. */ - -#define TC2_LCMPA_bm 0x01 /* Low Byte Compare A Output Value bit mask. */ -#define TC2_LCMPA_bp 0 /* Low Byte Compare A Output Value bit position. */ - -/* TC2.CTRLE bit masks and bit positions */ -#define TC2_BYTEM_gm 0x03 /* Byte Mode group mask. */ -#define TC2_BYTEM_gp 0 /* Byte Mode group position. */ -#define TC2_BYTEM0_bm (1<<0) /* Byte Mode bit 0 mask. */ -#define TC2_BYTEM0_bp 0 /* Byte Mode bit 0 position. */ -#define TC2_BYTEM1_bm (1<<1) /* Byte Mode bit 1 mask. */ -#define TC2_BYTEM1_bp 1 /* Byte Mode bit 1 position. */ - -/* TC2.INTCTRLA bit masks and bit positions */ -#define TC2_HUNFINTLVL_gm 0x0C /* High Byte Underflow Interrupt Level group mask. */ -#define TC2_HUNFINTLVL_gp 2 /* High Byte Underflow Interrupt Level group position. */ -#define TC2_HUNFINTLVL0_bm (1<<2) /* High Byte Underflow Interrupt Level bit 0 mask. */ -#define TC2_HUNFINTLVL0_bp 2 /* High Byte Underflow Interrupt Level bit 0 position. */ -#define TC2_HUNFINTLVL1_bm (1<<3) /* High Byte Underflow Interrupt Level bit 1 mask. */ -#define TC2_HUNFINTLVL1_bp 3 /* High Byte Underflow Interrupt Level bit 1 position. */ - -#define TC2_LUNFINTLVL_gm 0x03 /* Low Byte Underflow interrupt level group mask. */ -#define TC2_LUNFINTLVL_gp 0 /* Low Byte Underflow interrupt level group position. */ -#define TC2_LUNFINTLVL0_bm (1<<0) /* Low Byte Underflow interrupt level bit 0 mask. */ -#define TC2_LUNFINTLVL0_bp 0 /* Low Byte Underflow interrupt level bit 0 position. */ -#define TC2_LUNFINTLVL1_bm (1<<1) /* Low Byte Underflow interrupt level bit 1 mask. */ -#define TC2_LUNFINTLVL1_bp 1 /* Low Byte Underflow interrupt level bit 1 position. */ - -/* TC2.INTCTRLB bit masks and bit positions */ -#define TC2_LCMPDINTLVL_gm 0xC0 /* Low Byte Compare D Interrupt Level group mask. */ -#define TC2_LCMPDINTLVL_gp 6 /* Low Byte Compare D Interrupt Level group position. */ -#define TC2_LCMPDINTLVL0_bm (1<<6) /* Low Byte Compare D Interrupt Level bit 0 mask. */ -#define TC2_LCMPDINTLVL0_bp 6 /* Low Byte Compare D Interrupt Level bit 0 position. */ -#define TC2_LCMPDINTLVL1_bm (1<<7) /* Low Byte Compare D Interrupt Level bit 1 mask. */ -#define TC2_LCMPDINTLVL1_bp 7 /* Low Byte Compare D Interrupt Level bit 1 position. */ - -#define TC2_LCMPCINTLVL_gm 0x30 /* Low Byte Compare C Interrupt Level group mask. */ -#define TC2_LCMPCINTLVL_gp 4 /* Low Byte Compare C Interrupt Level group position. */ -#define TC2_LCMPCINTLVL0_bm (1<<4) /* Low Byte Compare C Interrupt Level bit 0 mask. */ -#define TC2_LCMPCINTLVL0_bp 4 /* Low Byte Compare C Interrupt Level bit 0 position. */ -#define TC2_LCMPCINTLVL1_bm (1<<5) /* Low Byte Compare C Interrupt Level bit 1 mask. */ -#define TC2_LCMPCINTLVL1_bp 5 /* Low Byte Compare C Interrupt Level bit 1 position. */ - -#define TC2_LCMPBINTLVL_gm 0x0C /* Low Byte Compare B Interrupt Level group mask. */ -#define TC2_LCMPBINTLVL_gp 2 /* Low Byte Compare B Interrupt Level group position. */ -#define TC2_LCMPBINTLVL0_bm (1<<2) /* Low Byte Compare B Interrupt Level bit 0 mask. */ -#define TC2_LCMPBINTLVL0_bp 2 /* Low Byte Compare B Interrupt Level bit 0 position. */ -#define TC2_LCMPBINTLVL1_bm (1<<3) /* Low Byte Compare B Interrupt Level bit 1 mask. */ -#define TC2_LCMPBINTLVL1_bp 3 /* Low Byte Compare B Interrupt Level bit 1 position. */ - -#define TC2_LCMPAINTLVL_gm 0x03 /* Low Byte Compare A Interrupt Level group mask. */ -#define TC2_LCMPAINTLVL_gp 0 /* Low Byte Compare A Interrupt Level group position. */ -#define TC2_LCMPAINTLVL0_bm (1<<0) /* Low Byte Compare A Interrupt Level bit 0 mask. */ -#define TC2_LCMPAINTLVL0_bp 0 /* Low Byte Compare A Interrupt Level bit 0 position. */ -#define TC2_LCMPAINTLVL1_bm (1<<1) /* Low Byte Compare A Interrupt Level bit 1 mask. */ -#define TC2_LCMPAINTLVL1_bp 1 /* Low Byte Compare A Interrupt Level bit 1 position. */ - -/* TC2.CTRLF bit masks and bit positions */ -#define TC2_CMD_gm 0x0C /* Command group mask. */ -#define TC2_CMD_gp 2 /* Command group position. */ -#define TC2_CMD0_bm (1<<2) /* Command bit 0 mask. */ -#define TC2_CMD0_bp 2 /* Command bit 0 position. */ -#define TC2_CMD1_bm (1<<3) /* Command bit 1 mask. */ -#define TC2_CMD1_bp 3 /* Command bit 1 position. */ - -#define TC2_CMDEN_gm 0x03 /* Command Enable group mask. */ -#define TC2_CMDEN_gp 0 /* Command Enable group position. */ -#define TC2_CMDEN0_bm (1<<0) /* Command Enable bit 0 mask. */ -#define TC2_CMDEN0_bp 0 /* Command Enable bit 0 position. */ -#define TC2_CMDEN1_bm (1<<1) /* Command Enable bit 1 mask. */ -#define TC2_CMDEN1_bp 1 /* Command Enable bit 1 position. */ - -/* TC2.INTFLAGS bit masks and bit positions */ -#define TC2_LCMPDIF_bm 0x80 /* Low Byte Compare D Interrupt Flag bit mask. */ -#define TC2_LCMPDIF_bp 7 /* Low Byte Compare D Interrupt Flag bit position. */ - -#define TC2_LCMPCIF_bm 0x40 /* Low Byte Compare C Interrupt Flag bit mask. */ -#define TC2_LCMPCIF_bp 6 /* Low Byte Compare C Interrupt Flag bit position. */ - -#define TC2_LCMPBIF_bm 0x20 /* Low Byte Compare B Interrupt Flag bit mask. */ -#define TC2_LCMPBIF_bp 5 /* Low Byte Compare B Interrupt Flag bit position. */ - -#define TC2_LCMPAIF_bm 0x10 /* Low Byte Compare A Interrupt Flag bit mask. */ -#define TC2_LCMPAIF_bp 4 /* Low Byte Compare A Interrupt Flag bit position. */ - -#define TC2_HUNFIF_bm 0x02 /* High Byte Underflow Interrupt Flag bit mask. */ -#define TC2_HUNFIF_bp 1 /* High Byte Underflow Interrupt Flag bit position. */ - -#define TC2_LUNFIF_bm 0x01 /* Low Byte Underflow Interrupt Flag bit mask. */ -#define TC2_LUNFIF_bp 0 /* Low Byte Underflow Interrupt Flag bit position. */ - -/* AWEX - Timer/Counter Advanced Waveform Extension */ -/* AWEX.CTRL bit masks and bit positions */ -#define AWEX_PGM_bm 0x20 /* Pattern Generation Mode bit mask. */ -#define AWEX_PGM_bp 5 /* Pattern Generation Mode bit position. */ - -#define AWEX_CWCM_bm 0x10 /* Common Waveform Channel Mode bit mask. */ -#define AWEX_CWCM_bp 4 /* Common Waveform Channel Mode bit position. */ - -#define AWEX_DTICCDEN_bm 0x08 /* Dead Time Insertion Compare Channel D Enable bit mask. */ -#define AWEX_DTICCDEN_bp 3 /* Dead Time Insertion Compare Channel D Enable bit position. */ - -#define AWEX_DTICCCEN_bm 0x04 /* Dead Time Insertion Compare Channel C Enable bit mask. */ -#define AWEX_DTICCCEN_bp 2 /* Dead Time Insertion Compare Channel C Enable bit position. */ - -#define AWEX_DTICCBEN_bm 0x02 /* Dead Time Insertion Compare Channel B Enable bit mask. */ -#define AWEX_DTICCBEN_bp 1 /* Dead Time Insertion Compare Channel B Enable bit position. */ - -#define AWEX_DTICCAEN_bm 0x01 /* Dead Time Insertion Compare Channel A Enable bit mask. */ -#define AWEX_DTICCAEN_bp 0 /* Dead Time Insertion Compare Channel A Enable bit position. */ - -/* AWEX.FDCTRL bit masks and bit positions */ -#define AWEX_FDDBD_bm 0x10 /* Fault Detect on Disable Break Disable bit mask. */ -#define AWEX_FDDBD_bp 4 /* Fault Detect on Disable Break Disable bit position. */ - -#define AWEX_FDMODE_bm 0x04 /* Fault Detect Mode bit mask. */ -#define AWEX_FDMODE_bp 2 /* Fault Detect Mode bit position. */ - -#define AWEX_FDACT_gm 0x03 /* Fault Detect Action group mask. */ -#define AWEX_FDACT_gp 0 /* Fault Detect Action group position. */ -#define AWEX_FDACT0_bm (1<<0) /* Fault Detect Action bit 0 mask. */ -#define AWEX_FDACT0_bp 0 /* Fault Detect Action bit 0 position. */ -#define AWEX_FDACT1_bm (1<<1) /* Fault Detect Action bit 1 mask. */ -#define AWEX_FDACT1_bp 1 /* Fault Detect Action bit 1 position. */ - -/* AWEX.STATUS bit masks and bit positions */ -#define AWEX_FDF_bm 0x04 /* Fault Detect Flag bit mask. */ -#define AWEX_FDF_bp 2 /* Fault Detect Flag bit position. */ - -#define AWEX_DTHSBUFV_bm 0x02 /* Dead Time High Side Buffer Valid bit mask. */ -#define AWEX_DTHSBUFV_bp 1 /* Dead Time High Side Buffer Valid bit position. */ - -#define AWEX_DTLSBUFV_bm 0x01 /* Dead Time Low Side Buffer Valid bit mask. */ -#define AWEX_DTLSBUFV_bp 0 /* Dead Time Low Side Buffer Valid bit position. */ - -/* AWEX.STATUSSET bit masks and bit positions */ -/* AWEX_FDF Predefined. */ -/* AWEX_FDF Predefined. */ - -/* AWEX_DTHSBUFV Predefined. */ -/* AWEX_DTHSBUFV Predefined. */ - -/* AWEX_DTLSBUFV Predefined. */ -/* AWEX_DTLSBUFV Predefined. */ - -/* HIRES - Timer/Counter High-Resolution Extension */ -/* HIRES.CTRLA bit masks and bit positions */ -#define HIRES_HREN_gm 0x03 /* High Resolution Enable group mask. */ -#define HIRES_HREN_gp 0 /* High Resolution Enable group position. */ -#define HIRES_HREN0_bm (1<<0) /* High Resolution Enable bit 0 mask. */ -#define HIRES_HREN0_bp 0 /* High Resolution Enable bit 0 position. */ -#define HIRES_HREN1_bm (1<<1) /* High Resolution Enable bit 1 mask. */ -#define HIRES_HREN1_bp 1 /* High Resolution Enable bit 1 position. */ - -/* USART - Universal Asynchronous Receiver-Transmitter */ -/* USART.STATUS bit masks and bit positions */ -#define USART_RXCIF_bm 0x80 /* Receive Interrupt Flag bit mask. */ -#define USART_RXCIF_bp 7 /* Receive Interrupt Flag bit position. */ - -#define USART_TXCIF_bm 0x40 /* Transmit Interrupt Flag bit mask. */ -#define USART_TXCIF_bp 6 /* Transmit Interrupt Flag bit position. */ - -#define USART_DREIF_bm 0x20 /* Data Register Empty Flag bit mask. */ -#define USART_DREIF_bp 5 /* Data Register Empty Flag bit position. */ - -#define USART_FERR_bm 0x10 /* Frame Error bit mask. */ -#define USART_FERR_bp 4 /* Frame Error bit position. */ - -#define USART_BUFOVF_bm 0x08 /* Buffer Overflow bit mask. */ -#define USART_BUFOVF_bp 3 /* Buffer Overflow bit position. */ - -#define USART_PERR_bm 0x04 /* Parity Error bit mask. */ -#define USART_PERR_bp 2 /* Parity Error bit position. */ - -#define USART_RXB8_bm 0x01 /* Receive Bit 8 bit mask. */ -#define USART_RXB8_bp 0 /* Receive Bit 8 bit position. */ - -/* USART.CTRLA bit masks and bit positions */ -#define USART_RXCINTLVL_gm 0x30 /* Receive Interrupt Level group mask. */ -#define USART_RXCINTLVL_gp 4 /* Receive Interrupt Level group position. */ -#define USART_RXCINTLVL0_bm (1<<4) /* Receive Interrupt Level bit 0 mask. */ -#define USART_RXCINTLVL0_bp 4 /* Receive Interrupt Level bit 0 position. */ -#define USART_RXCINTLVL1_bm (1<<5) /* Receive Interrupt Level bit 1 mask. */ -#define USART_RXCINTLVL1_bp 5 /* Receive Interrupt Level bit 1 position. */ - -#define USART_TXCINTLVL_gm 0x0C /* Transmit Interrupt Level group mask. */ -#define USART_TXCINTLVL_gp 2 /* Transmit Interrupt Level group position. */ -#define USART_TXCINTLVL0_bm (1<<2) /* Transmit Interrupt Level bit 0 mask. */ -#define USART_TXCINTLVL0_bp 2 /* Transmit Interrupt Level bit 0 position. */ -#define USART_TXCINTLVL1_bm (1<<3) /* Transmit Interrupt Level bit 1 mask. */ -#define USART_TXCINTLVL1_bp 3 /* Transmit Interrupt Level bit 1 position. */ - -#define USART_DREINTLVL_gm 0x03 /* Data Register Empty Interrupt Level group mask. */ -#define USART_DREINTLVL_gp 0 /* Data Register Empty Interrupt Level group position. */ -#define USART_DREINTLVL0_bm (1<<0) /* Data Register Empty Interrupt Level bit 0 mask. */ -#define USART_DREINTLVL0_bp 0 /* Data Register Empty Interrupt Level bit 0 position. */ -#define USART_DREINTLVL1_bm (1<<1) /* Data Register Empty Interrupt Level bit 1 mask. */ -#define USART_DREINTLVL1_bp 1 /* Data Register Empty Interrupt Level bit 1 position. */ - -/* USART.CTRLB bit masks and bit positions */ -#define USART_RXEN_bm 0x10 /* Receiver Enable bit mask. */ -#define USART_RXEN_bp 4 /* Receiver Enable bit position. */ - -#define USART_TXEN_bm 0x08 /* Transmitter Enable bit mask. */ -#define USART_TXEN_bp 3 /* Transmitter Enable bit position. */ - -#define USART_CLK2X_bm 0x04 /* Double transmission speed bit mask. */ -#define USART_CLK2X_bp 2 /* Double transmission speed bit position. */ - -#define USART_MPCM_bm 0x02 /* Multi-processor Communication Mode bit mask. */ -#define USART_MPCM_bp 1 /* Multi-processor Communication Mode bit position. */ - -#define USART_TXB8_bm 0x01 /* Transmit bit 8 bit mask. */ -#define USART_TXB8_bp 0 /* Transmit bit 8 bit position. */ - -/* USART.CTRLC bit masks and bit positions */ -#define USART_CMODE_gm 0xC0 /* Communication Mode group mask. */ -#define USART_CMODE_gp 6 /* Communication Mode group position. */ -#define USART_CMODE0_bm (1<<6) /* Communication Mode bit 0 mask. */ -#define USART_CMODE0_bp 6 /* Communication Mode bit 0 position. */ -#define USART_CMODE1_bm (1<<7) /* Communication Mode bit 1 mask. */ -#define USART_CMODE1_bp 7 /* Communication Mode bit 1 position. */ - -#define USART_PMODE_gm 0x30 /* Parity Mode group mask. */ -#define USART_PMODE_gp 4 /* Parity Mode group position. */ -#define USART_PMODE0_bm (1<<4) /* Parity Mode bit 0 mask. */ -#define USART_PMODE0_bp 4 /* Parity Mode bit 0 position. */ -#define USART_PMODE1_bm (1<<5) /* Parity Mode bit 1 mask. */ -#define USART_PMODE1_bp 5 /* Parity Mode bit 1 position. */ - -#define USART_SBMODE_bm 0x08 /* Stop Bit Mode bit mask. */ -#define USART_SBMODE_bp 3 /* Stop Bit Mode bit position. */ - -#define USART_CHSIZE_gm 0x07 /* Character Size group mask. */ -#define USART_CHSIZE_gp 0 /* Character Size group position. */ -#define USART_CHSIZE0_bm (1<<0) /* Character Size bit 0 mask. */ -#define USART_CHSIZE0_bp 0 /* Character Size bit 0 position. */ -#define USART_CHSIZE1_bm (1<<1) /* Character Size bit 1 mask. */ -#define USART_CHSIZE1_bp 1 /* Character Size bit 1 position. */ -#define USART_CHSIZE2_bm (1<<2) /* Character Size bit 2 mask. */ -#define USART_CHSIZE2_bp 2 /* Character Size bit 2 position. */ - -/* USART.BAUDCTRLA bit masks and bit positions */ -#define USART_BSEL_gm 0xFF /* Baud Rate Selection Bits [7:0] group mask. */ -#define USART_BSEL_gp 0 /* Baud Rate Selection Bits [7:0] group position. */ -#define USART_BSEL0_bm (1<<0) /* Baud Rate Selection Bits [7:0] bit 0 mask. */ -#define USART_BSEL0_bp 0 /* Baud Rate Selection Bits [7:0] bit 0 position. */ -#define USART_BSEL1_bm (1<<1) /* Baud Rate Selection Bits [7:0] bit 1 mask. */ -#define USART_BSEL1_bp 1 /* Baud Rate Selection Bits [7:0] bit 1 position. */ -#define USART_BSEL2_bm (1<<2) /* Baud Rate Selection Bits [7:0] bit 2 mask. */ -#define USART_BSEL2_bp 2 /* Baud Rate Selection Bits [7:0] bit 2 position. */ -#define USART_BSEL3_bm (1<<3) /* Baud Rate Selection Bits [7:0] bit 3 mask. */ -#define USART_BSEL3_bp 3 /* Baud Rate Selection Bits [7:0] bit 3 position. */ -#define USART_BSEL4_bm (1<<4) /* Baud Rate Selection Bits [7:0] bit 4 mask. */ -#define USART_BSEL4_bp 4 /* Baud Rate Selection Bits [7:0] bit 4 position. */ -#define USART_BSEL5_bm (1<<5) /* Baud Rate Selection Bits [7:0] bit 5 mask. */ -#define USART_BSEL5_bp 5 /* Baud Rate Selection Bits [7:0] bit 5 position. */ -#define USART_BSEL6_bm (1<<6) /* Baud Rate Selection Bits [7:0] bit 6 mask. */ -#define USART_BSEL6_bp 6 /* Baud Rate Selection Bits [7:0] bit 6 position. */ -#define USART_BSEL7_bm (1<<7) /* Baud Rate Selection Bits [7:0] bit 7 mask. */ -#define USART_BSEL7_bp 7 /* Baud Rate Selection Bits [7:0] bit 7 position. */ - -/* USART.BAUDCTRLB bit masks and bit positions */ -#define USART_BSCALE_gm 0xF0 /* Baud Rate Scale group mask. */ -#define USART_BSCALE_gp 4 /* Baud Rate Scale group position. */ -#define USART_BSCALE0_bm (1<<4) /* Baud Rate Scale bit 0 mask. */ -#define USART_BSCALE0_bp 4 /* Baud Rate Scale bit 0 position. */ -#define USART_BSCALE1_bm (1<<5) /* Baud Rate Scale bit 1 mask. */ -#define USART_BSCALE1_bp 5 /* Baud Rate Scale bit 1 position. */ -#define USART_BSCALE2_bm (1<<6) /* Baud Rate Scale bit 2 mask. */ -#define USART_BSCALE2_bp 6 /* Baud Rate Scale bit 2 position. */ -#define USART_BSCALE3_bm (1<<7) /* Baud Rate Scale bit 3 mask. */ -#define USART_BSCALE3_bp 7 /* Baud Rate Scale bit 3 position. */ - -/* USART_BSEL Predefined. */ -/* USART_BSEL Predefined. */ - -/* SPI - Serial Peripheral Interface */ -/* SPI.CTRL bit masks and bit positions */ -#define SPI_CLK2X_bm 0x80 /* Enable Double Speed bit mask. */ -#define SPI_CLK2X_bp 7 /* Enable Double Speed bit position. */ - -#define SPI_ENABLE_bm 0x40 /* Enable Module bit mask. */ -#define SPI_ENABLE_bp 6 /* Enable Module bit position. */ - -#define SPI_DORD_bm 0x20 /* Data Order Setting bit mask. */ -#define SPI_DORD_bp 5 /* Data Order Setting bit position. */ - -#define SPI_MASTER_bm 0x10 /* Master Operation Enable bit mask. */ -#define SPI_MASTER_bp 4 /* Master Operation Enable bit position. */ - -#define SPI_MODE_gm 0x0C /* SPI Mode group mask. */ -#define SPI_MODE_gp 2 /* SPI Mode group position. */ -#define SPI_MODE0_bm (1<<2) /* SPI Mode bit 0 mask. */ -#define SPI_MODE0_bp 2 /* SPI Mode bit 0 position. */ -#define SPI_MODE1_bm (1<<3) /* SPI Mode bit 1 mask. */ -#define SPI_MODE1_bp 3 /* SPI Mode bit 1 position. */ - -#define SPI_PRESCALER_gm 0x03 /* Prescaler group mask. */ -#define SPI_PRESCALER_gp 0 /* Prescaler group position. */ -#define SPI_PRESCALER0_bm (1<<0) /* Prescaler bit 0 mask. */ -#define SPI_PRESCALER0_bp 0 /* Prescaler bit 0 position. */ -#define SPI_PRESCALER1_bm (1<<1) /* Prescaler bit 1 mask. */ -#define SPI_PRESCALER1_bp 1 /* Prescaler bit 1 position. */ - -/* SPI.INTCTRL bit masks and bit positions */ -#define SPI_INTLVL_gm 0x03 /* Interrupt level group mask. */ -#define SPI_INTLVL_gp 0 /* Interrupt level group position. */ -#define SPI_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */ -#define SPI_INTLVL0_bp 0 /* Interrupt level bit 0 position. */ -#define SPI_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */ -#define SPI_INTLVL1_bp 1 /* Interrupt level bit 1 position. */ - -/* SPI.STATUS bit masks and bit positions */ -#define SPI_IF_bm 0x80 /* Interrupt Flag bit mask. */ -#define SPI_IF_bp 7 /* Interrupt Flag bit position. */ - -#define SPI_WRCOL_bm 0x40 /* Write Collision bit mask. */ -#define SPI_WRCOL_bp 6 /* Write Collision bit position. */ - -/* IRCOM - IR Communication Module */ -/* IRCOM.CTRL bit masks and bit positions */ -#define IRCOM_EVSEL_gm 0x0F /* Event Channel Select group mask. */ -#define IRCOM_EVSEL_gp 0 /* Event Channel Select group position. */ -#define IRCOM_EVSEL0_bm (1<<0) /* Event Channel Select bit 0 mask. */ -#define IRCOM_EVSEL0_bp 0 /* Event Channel Select bit 0 position. */ -#define IRCOM_EVSEL1_bm (1<<1) /* Event Channel Select bit 1 mask. */ -#define IRCOM_EVSEL1_bp 1 /* Event Channel Select bit 1 position. */ -#define IRCOM_EVSEL2_bm (1<<2) /* Event Channel Select bit 2 mask. */ -#define IRCOM_EVSEL2_bp 2 /* Event Channel Select bit 2 position. */ -#define IRCOM_EVSEL3_bm (1<<3) /* Event Channel Select bit 3 mask. */ -#define IRCOM_EVSEL3_bp 3 /* Event Channel Select bit 3 position. */ - -/* FUSE - Fuses and Lockbits */ -/* NVM_FUSES.FUSEBYTE1 bit masks and bit positions */ -#define NVM_FUSES_WDWP_gm 0xF0 /* Watchdog Window Timeout Period group mask. */ -#define NVM_FUSES_WDWP_gp 4 /* Watchdog Window Timeout Period group position. */ -#define NVM_FUSES_WDWP0_bm (1<<4) /* Watchdog Window Timeout Period bit 0 mask. */ -#define NVM_FUSES_WDWP0_bp 4 /* Watchdog Window Timeout Period bit 0 position. */ -#define NVM_FUSES_WDWP1_bm (1<<5) /* Watchdog Window Timeout Period bit 1 mask. */ -#define NVM_FUSES_WDWP1_bp 5 /* Watchdog Window Timeout Period bit 1 position. */ -#define NVM_FUSES_WDWP2_bm (1<<6) /* Watchdog Window Timeout Period bit 2 mask. */ -#define NVM_FUSES_WDWP2_bp 6 /* Watchdog Window Timeout Period bit 2 position. */ -#define NVM_FUSES_WDWP3_bm (1<<7) /* Watchdog Window Timeout Period bit 3 mask. */ -#define NVM_FUSES_WDWP3_bp 7 /* Watchdog Window Timeout Period bit 3 position. */ - -#define NVM_FUSES_WDP_gm 0x0F /* Watchdog Timeout Period group mask. */ -#define NVM_FUSES_WDP_gp 0 /* Watchdog Timeout Period group position. */ -#define NVM_FUSES_WDP0_bm (1<<0) /* Watchdog Timeout Period bit 0 mask. */ -#define NVM_FUSES_WDP0_bp 0 /* Watchdog Timeout Period bit 0 position. */ -#define NVM_FUSES_WDP1_bm (1<<1) /* Watchdog Timeout Period bit 1 mask. */ -#define NVM_FUSES_WDP1_bp 1 /* Watchdog Timeout Period bit 1 position. */ -#define NVM_FUSES_WDP2_bm (1<<2) /* Watchdog Timeout Period bit 2 mask. */ -#define NVM_FUSES_WDP2_bp 2 /* Watchdog Timeout Period bit 2 position. */ -#define NVM_FUSES_WDP3_bm (1<<3) /* Watchdog Timeout Period bit 3 mask. */ -#define NVM_FUSES_WDP3_bp 3 /* Watchdog Timeout Period bit 3 position. */ - -/* NVM_FUSES.FUSEBYTE2 bit masks and bit positions */ -#define NVM_FUSES_BOOTRST_bm 0x40 /* Boot Loader Section Reset Vector bit mask. */ -#define NVM_FUSES_BOOTRST_bp 6 /* Boot Loader Section Reset Vector bit position. */ - -#define NVM_FUSES_TOSCSEL_bm 0x20 /* Timer Oscillator pin location bit mask. */ -#define NVM_FUSES_TOSCSEL_bp 5 /* Timer Oscillator pin location bit position. */ - -#define NVM_FUSES_BODPD_gm 0x03 /* BOD Operation in Power-Down Mode group mask. */ -#define NVM_FUSES_BODPD_gp 0 /* BOD Operation in Power-Down Mode group position. */ -#define NVM_FUSES_BODPD0_bm (1<<0) /* BOD Operation in Power-Down Mode bit 0 mask. */ -#define NVM_FUSES_BODPD0_bp 0 /* BOD Operation in Power-Down Mode bit 0 position. */ -#define NVM_FUSES_BODPD1_bm (1<<1) /* BOD Operation in Power-Down Mode bit 1 mask. */ -#define NVM_FUSES_BODPD1_bp 1 /* BOD Operation in Power-Down Mode bit 1 position. */ - -/* NVM_FUSES.FUSEBYTE4 bit masks and bit positions */ -#define NVM_FUSES_RSTDISBL_bm 0x10 /* External Reset Disable bit mask. */ -#define NVM_FUSES_RSTDISBL_bp 4 /* External Reset Disable bit position. */ - -#define NVM_FUSES_SUT_gm 0x0C /* Start-up Time group mask. */ -#define NVM_FUSES_SUT_gp 2 /* Start-up Time group position. */ -#define NVM_FUSES_SUT0_bm (1<<2) /* Start-up Time bit 0 mask. */ -#define NVM_FUSES_SUT0_bp 2 /* Start-up Time bit 0 position. */ -#define NVM_FUSES_SUT1_bm (1<<3) /* Start-up Time bit 1 mask. */ -#define NVM_FUSES_SUT1_bp 3 /* Start-up Time bit 1 position. */ - -#define NVM_FUSES_WDLOCK_bm 0x02 /* Watchdog Timer Lock bit mask. */ -#define NVM_FUSES_WDLOCK_bp 1 /* Watchdog Timer Lock bit position. */ - -/* NVM_FUSES.FUSEBYTE5 bit masks and bit positions */ -#define NVM_FUSES_BODACT_gm 0x30 /* BOD Operation in Active Mode group mask. */ -#define NVM_FUSES_BODACT_gp 4 /* BOD Operation in Active Mode group position. */ -#define NVM_FUSES_BODACT0_bm (1<<4) /* BOD Operation in Active Mode bit 0 mask. */ -#define NVM_FUSES_BODACT0_bp 4 /* BOD Operation in Active Mode bit 0 position. */ -#define NVM_FUSES_BODACT1_bm (1<<5) /* BOD Operation in Active Mode bit 1 mask. */ -#define NVM_FUSES_BODACT1_bp 5 /* BOD Operation in Active Mode bit 1 position. */ - -#define NVM_FUSES_EESAVE_bm 0x08 /* Preserve EEPROM Through Chip Erase bit mask. */ -#define NVM_FUSES_EESAVE_bp 3 /* Preserve EEPROM Through Chip Erase bit position. */ - -#define NVM_FUSES_BODLVL_gm 0x07 /* Brownout Detection Voltage Level group mask. */ -#define NVM_FUSES_BODLVL_gp 0 /* Brownout Detection Voltage Level group position. */ -#define NVM_FUSES_BODLVL0_bm (1<<0) /* Brownout Detection Voltage Level bit 0 mask. */ -#define NVM_FUSES_BODLVL0_bp 0 /* Brownout Detection Voltage Level bit 0 position. */ -#define NVM_FUSES_BODLVL1_bm (1<<1) /* Brownout Detection Voltage Level bit 1 mask. */ -#define NVM_FUSES_BODLVL1_bp 1 /* Brownout Detection Voltage Level bit 1 position. */ -#define NVM_FUSES_BODLVL2_bm (1<<2) /* Brownout Detection Voltage Level bit 2 mask. */ -#define NVM_FUSES_BODLVL2_bp 2 /* Brownout Detection Voltage Level bit 2 position. */ - -/* LOCKBIT - Fuses and Lockbits */ -/* NVM_LOCKBITS.LOCKBITS bit masks and bit positions */ -#define NVM_LOCKBITS_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ -#define NVM_LOCKBITS_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ -#define NVM_LOCKBITS_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ -#define NVM_LOCKBITS_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ -#define NVM_LOCKBITS_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ -#define NVM_LOCKBITS_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ - -#define NVM_LOCKBITS_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ -#define NVM_LOCKBITS_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ -#define NVM_LOCKBITS_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ -#define NVM_LOCKBITS_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ -#define NVM_LOCKBITS_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ -#define NVM_LOCKBITS_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ - -#define NVM_LOCKBITS_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ -#define NVM_LOCKBITS_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ -#define NVM_LOCKBITS_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ -#define NVM_LOCKBITS_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ -#define NVM_LOCKBITS_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ -#define NVM_LOCKBITS_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ - -#define NVM_LOCKBITS_LB_gm 0x03 /* Lock Bits group mask. */ -#define NVM_LOCKBITS_LB_gp 0 /* Lock Bits group position. */ -#define NVM_LOCKBITS_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ -#define NVM_LOCKBITS_LB0_bp 0 /* Lock Bits bit 0 position. */ -#define NVM_LOCKBITS_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ -#define NVM_LOCKBITS_LB1_bp 1 /* Lock Bits bit 1 position. */ - - - -// Generic Port Pins - -#define PIN0_bm 0x01 -#define PIN0_bp 0 -#define PIN1_bm 0x02 -#define PIN1_bp 1 -#define PIN2_bm 0x04 -#define PIN2_bp 2 -#define PIN3_bm 0x08 -#define PIN3_bp 3 -#define PIN4_bm 0x10 -#define PIN4_bp 4 -#define PIN5_bm 0x20 -#define PIN5_bp 5 -#define PIN6_bm 0x40 -#define PIN6_bp 6 -#define PIN7_bm 0x80 -#define PIN7_bp 7 - -/* ========== Interrupt Vector Definitions ========== */ -/* Vector 0 is the reset vector */ - -/* OSC interrupt vectors */ -#define OSC_OSCF_vect_num 1 -#define OSC_OSCF_vect _VECTOR(1) /* Oscillator Failure Interrupt (NMI) */ - -/* PORTC interrupt vectors */ -#define PORTC_INT0_vect_num 2 -#define PORTC_INT0_vect _VECTOR(2) /* External Interrupt 0 */ -#define PORTC_INT1_vect_num 3 -#define PORTC_INT1_vect _VECTOR(3) /* External Interrupt 1 */ - -/* PORTR interrupt vectors */ -#define PORTR_INT0_vect_num 4 -#define PORTR_INT0_vect _VECTOR(4) /* External Interrupt 0 */ -#define PORTR_INT1_vect_num 5 -#define PORTR_INT1_vect _VECTOR(5) /* External Interrupt 1 */ - -/* RTC interrupt vectors */ -#define RTC_OVF_vect_num 10 -#define RTC_OVF_vect _VECTOR(10) /* Overflow Interrupt */ -#define RTC_COMP_vect_num 11 -#define RTC_COMP_vect _VECTOR(11) /* Compare Interrupt */ - -/* TWIC interrupt vectors */ -#define TWIC_TWIS_vect_num 12 -#define TWIC_TWIS_vect _VECTOR(12) /* TWI Slave Interrupt */ -#define TWIC_TWIM_vect_num 13 -#define TWIC_TWIM_vect _VECTOR(13) /* TWI Master Interrupt */ - -/* TCC0 interrupt vectors */ -#define TCC0_OVF_vect_num 14 -#define TCC0_OVF_vect _VECTOR(14) /* Overflow Interrupt */ - -/* TCC2 interrupt vectors */ -#define TCC2_LUNF_vect_num 14 -#define TCC2_LUNF_vect _VECTOR(14) /* Low Byte Underflow Interrupt */ - -/* TCC0 interrupt vectors */ -#define TCC0_ERR_vect_num 15 -#define TCC0_ERR_vect _VECTOR(15) /* Error Interrupt */ - -/* TCC2 interrupt vectors */ -#define TCC2_HUNF_vect_num 15 -#define TCC2_HUNF_vect _VECTOR(15) /* High Byte Underflow Interrupt */ - -/* TCC0 interrupt vectors */ -#define TCC0_CCA_vect_num 16 -#define TCC0_CCA_vect _VECTOR(16) /* Compare or Capture A Interrupt */ - -/* TCC2 interrupt vectors */ -#define TCC2_LCMPA_vect_num 16 -#define TCC2_LCMPA_vect _VECTOR(16) /* Low Byte Compare A Interrupt */ - -/* TCC0 interrupt vectors */ -#define TCC0_CCB_vect_num 17 -#define TCC0_CCB_vect _VECTOR(17) /* Compare or Capture B Interrupt */ - -/* TCC2 interrupt vectors */ -#define TCC2_LCMPB_vect_num 17 -#define TCC2_LCMPB_vect _VECTOR(17) /* Low Byte Compare B Interrupt */ - -/* TCC0 interrupt vectors */ -#define TCC0_CCC_vect_num 18 -#define TCC0_CCC_vect _VECTOR(18) /* Compare or Capture C Interrupt */ - -/* TCC2 interrupt vectors */ -#define TCC2_LCMPC_vect_num 18 -#define TCC2_LCMPC_vect _VECTOR(18) /* Low Byte Compare C Interrupt */ - -/* TCC0 interrupt vectors */ -#define TCC0_CCD_vect_num 19 -#define TCC0_CCD_vect _VECTOR(19) /* Compare or Capture D Interrupt */ - -/* TCC2 interrupt vectors */ -#define TCC2_LCMPD_vect_num 19 -#define TCC2_LCMPD_vect _VECTOR(19) /* Low Byte Compare D Interrupt */ - -/* TCC1 interrupt vectors */ -#define TCC1_OVF_vect_num 20 -#define TCC1_OVF_vect _VECTOR(20) /* Overflow Interrupt */ -#define TCC1_ERR_vect_num 21 -#define TCC1_ERR_vect _VECTOR(21) /* Error Interrupt */ -#define TCC1_CCA_vect_num 22 -#define TCC1_CCA_vect _VECTOR(22) /* Compare or Capture A Interrupt */ -#define TCC1_CCB_vect_num 23 -#define TCC1_CCB_vect _VECTOR(23) /* Compare or Capture B Interrupt */ - -/* SPIC interrupt vectors */ -#define SPIC_INT_vect_num 24 -#define SPIC_INT_vect _VECTOR(24) /* SPI Interrupt */ - -/* USARTC0 interrupt vectors */ -#define USARTC0_RXC_vect_num 25 -#define USARTC0_RXC_vect _VECTOR(25) /* Reception Complete Interrupt */ -#define USARTC0_DRE_vect_num 26 -#define USARTC0_DRE_vect _VECTOR(26) /* Data Register Empty Interrupt */ -#define USARTC0_TXC_vect_num 27 -#define USARTC0_TXC_vect _VECTOR(27) /* Transmission Complete Interrupt */ - -/* USARTC1 interrupt vectors */ -#define USARTC1_RXC_vect_num 28 -#define USARTC1_RXC_vect _VECTOR(28) /* Reception Complete Interrupt */ -#define USARTC1_DRE_vect_num 29 -#define USARTC1_DRE_vect _VECTOR(29) /* Data Register Empty Interrupt */ -#define USARTC1_TXC_vect_num 30 -#define USARTC1_TXC_vect _VECTOR(30) /* Transmission Complete Interrupt */ - -/* NVM interrupt vectors */ -#define NVM_EE_vect_num 32 -#define NVM_EE_vect _VECTOR(32) /* EE Interrupt */ -#define NVM_SPM_vect_num 33 -#define NVM_SPM_vect _VECTOR(33) /* SPM Interrupt */ - -/* PORTB interrupt vectors */ -#define PORTB_INT0_vect_num 34 -#define PORTB_INT0_vect _VECTOR(34) /* External Interrupt 0 */ -#define PORTB_INT1_vect_num 35 -#define PORTB_INT1_vect _VECTOR(35) /* External Interrupt 1 */ - -/* PORTE interrupt vectors */ -#define PORTE_INT0_vect_num 43 -#define PORTE_INT0_vect _VECTOR(43) /* External Interrupt 0 */ -#define PORTE_INT1_vect_num 44 -#define PORTE_INT1_vect _VECTOR(44) /* External Interrupt 1 */ - -/* TWIE interrupt vectors */ -#define TWIE_TWIS_vect_num 45 -#define TWIE_TWIS_vect _VECTOR(45) /* TWI Slave Interrupt */ -#define TWIE_TWIM_vect_num 46 -#define TWIE_TWIM_vect _VECTOR(46) /* TWI Master Interrupt */ - -/* TCE0 interrupt vectors */ -#define TCE0_OVF_vect_num 47 -#define TCE0_OVF_vect _VECTOR(47) /* Overflow Interrupt */ -#define TCE0_ERR_vect_num 48 -#define TCE0_ERR_vect _VECTOR(48) /* Error Interrupt */ -#define TCE0_CCA_vect_num 49 -#define TCE0_CCA_vect _VECTOR(49) /* Compare or Capture A Interrupt */ -#define TCE0_CCB_vect_num 50 -#define TCE0_CCB_vect _VECTOR(50) /* Compare or Capture B Interrupt */ -#define TCE0_CCC_vect_num 51 -#define TCE0_CCC_vect _VECTOR(51) /* Compare or Capture C Interrupt */ -#define TCE0_CCD_vect_num 52 -#define TCE0_CCD_vect _VECTOR(52) /* Compare or Capture D Interrupt */ - -/* PORTD interrupt vectors */ -#define PORTD_INT0_vect_num 64 -#define PORTD_INT0_vect _VECTOR(64) /* External Interrupt 0 */ -#define PORTD_INT1_vect_num 65 -#define PORTD_INT1_vect _VECTOR(65) /* External Interrupt 1 */ - -/* PORTA interrupt vectors */ -#define PORTA_INT0_vect_num 66 -#define PORTA_INT0_vect _VECTOR(66) /* External Interrupt 0 */ -#define PORTA_INT1_vect_num 67 -#define PORTA_INT1_vect _VECTOR(67) /* External Interrupt 1 */ - -/* ACA interrupt vectors */ -#define ACA_AC0_vect_num 68 -#define ACA_AC0_vect _VECTOR(68) /* AC0 Interrupt */ -#define ACA_AC1_vect_num 69 -#define ACA_AC1_vect _VECTOR(69) /* AC1 Interrupt */ -#define ACA_ACW_vect_num 70 -#define ACA_ACW_vect _VECTOR(70) /* ACW Window Mode Interrupt */ - -/* ADCA interrupt vectors */ -#define ADCA_CH0_vect_num 71 -#define ADCA_CH0_vect _VECTOR(71) /* Interrupt 0 */ - -/* TCD0 interrupt vectors */ -#define TCD0_OVF_vect_num 77 -#define TCD0_OVF_vect _VECTOR(77) /* Overflow Interrupt */ - -/* TCD2 interrupt vectors */ -#define TCD2_LUNF_vect_num 77 -#define TCD2_LUNF_vect _VECTOR(77) /* Low Byte Underflow Interrupt */ - -/* TCD0 interrupt vectors */ -#define TCD0_ERR_vect_num 78 -#define TCD0_ERR_vect _VECTOR(78) /* Error Interrupt */ - -/* TCD2 interrupt vectors */ -#define TCD2_HUNF_vect_num 78 -#define TCD2_HUNF_vect _VECTOR(78) /* High Byte Underflow Interrupt */ - -/* TCD0 interrupt vectors */ -#define TCD0_CCA_vect_num 79 -#define TCD0_CCA_vect _VECTOR(79) /* Compare or Capture A Interrupt */ - -/* TCD2 interrupt vectors */ -#define TCD2_LCMPA_vect_num 79 -#define TCD2_LCMPA_vect _VECTOR(79) /* Low Byte Compare A Interrupt */ - -/* TCD0 interrupt vectors */ -#define TCD0_CCB_vect_num 80 -#define TCD0_CCB_vect _VECTOR(80) /* Compare or Capture B Interrupt */ - -/* TCD2 interrupt vectors */ -#define TCD2_LCMPB_vect_num 80 -#define TCD2_LCMPB_vect _VECTOR(80) /* Low Byte Compare B Interrupt */ - -/* TCD0 interrupt vectors */ -#define TCD0_CCC_vect_num 81 -#define TCD0_CCC_vect _VECTOR(81) /* Compare or Capture C Interrupt */ - -/* TCD2 interrupt vectors */ -#define TCD2_LCMPC_vect_num 81 -#define TCD2_LCMPC_vect _VECTOR(81) /* Low Byte Compare C Interrupt */ - -/* TCD0 interrupt vectors */ -#define TCD0_CCD_vect_num 82 -#define TCD0_CCD_vect _VECTOR(82) /* Compare or Capture D Interrupt */ - -/* TCD2 interrupt vectors */ -#define TCD2_LCMPD_vect_num 82 -#define TCD2_LCMPD_vect _VECTOR(82) /* Low Byte Compare D Interrupt */ - -/* SPID interrupt vectors */ -#define SPID_INT_vect_num 87 -#define SPID_INT_vect _VECTOR(87) /* SPI Interrupt */ - -/* USARTD0 interrupt vectors */ -#define USARTD0_RXC_vect_num 88 -#define USARTD0_RXC_vect _VECTOR(88) /* Reception Complete Interrupt */ -#define USARTD0_DRE_vect_num 89 -#define USARTD0_DRE_vect _VECTOR(89) /* Data Register Empty Interrupt */ -#define USARTD0_TXC_vect_num 90 -#define USARTD0_TXC_vect _VECTOR(90) /* Transmission Complete Interrupt */ - -/* USB interrupt vectors */ -#define USB_BUSEVENT_vect_num 125 -#define USB_BUSEVENT_vect _VECTOR(125) /* SOF, suspend, resume, reset bus event interrupts, crc, underflow, overflow and stall error interrupts */ -#define USB_TRNCOMPL_vect_num 126 -#define USB_TRNCOMPL_vect _VECTOR(126) /* Transaction complete interrupt */ - -#define _VECTOR_SIZE 4 /* Size of individual vector. */ -#define _VECTORS_SIZE (127 * _VECTOR_SIZE) - - -/* ========== Constants ========== */ - -#define PROGMEM_START (0x0000) -#define PROGMEM_SIZE (36864) -#define PROGMEM_END (PROGMEM_START + PROGMEM_SIZE - 1) - -#define APP_SECTION_START (0x0000) -#define APP_SECTION_SIZE (32768) -#define APP_SECTION_PAGE_SIZE (256) -#define APP_SECTION_END (APP_SECTION_START + APP_SECTION_SIZE - 1) - -#define APPTABLE_SECTION_START (0x7000) -#define APPTABLE_SECTION_SIZE (4096) -#define APPTABLE_SECTION_PAGE_SIZE (256) -#define APPTABLE_SECTION_END (APPTABLE_SECTION_START + APPTABLE_SECTION_SIZE - 1) - -#define BOOT_SECTION_START (0x8000) -#define BOOT_SECTION_SIZE (4096) -#define BOOT_SECTION_PAGE_SIZE (256) -#define BOOT_SECTION_END (BOOT_SECTION_START + BOOT_SECTION_SIZE - 1) - -#define DATAMEM_START (0x0000) -#define DATAMEM_SIZE (12288) -#define DATAMEM_END (DATAMEM_START + DATAMEM_SIZE - 1) - -#define IO_START (0x0000) -#define IO_SIZE (4096) -#define IO_PAGE_SIZE (0) -#define IO_END (IO_START + IO_SIZE - 1) - -#define MAPPED_EEPROM_START (0x1000) -#define MAPPED_EEPROM_SIZE (1024) -#define MAPPED_EEPROM_PAGE_SIZE (0) -#define MAPPED_EEPROM_END (MAPPED_EEPROM_START + MAPPED_EEPROM_SIZE - 1) - -#define INTERNAL_SRAM_START (0x2000) -#define INTERNAL_SRAM_SIZE (4096) -#define INTERNAL_SRAM_PAGE_SIZE (0) -#define INTERNAL_SRAM_END (INTERNAL_SRAM_START + INTERNAL_SRAM_SIZE - 1) - -#define EEPROM_START (0x0000) -#define EEPROM_SIZE (1024) -#define EEPROM_PAGE_SIZE (32) -#define EEPROM_END (EEPROM_START + EEPROM_SIZE - 1) - -#define SIGNATURES_START (0x0000) -#define SIGNATURES_SIZE (3) -#define SIGNATURES_PAGE_SIZE (0) -#define SIGNATURES_END (SIGNATURES_START + SIGNATURES_SIZE - 1) - -#define FUSES_START (0x0000) -#define FUSES_SIZE (6) -#define FUSES_PAGE_SIZE (0) -#define FUSES_END (FUSES_START + FUSES_SIZE - 1) - -#define LOCKBITS_START (0x0000) -#define LOCKBITS_SIZE (1) -#define LOCKBITS_PAGE_SIZE (0) -#define LOCKBITS_END (LOCKBITS_START + LOCKBITS_SIZE - 1) - -#define USER_SIGNATURES_START (0x0000) -#define USER_SIGNATURES_SIZE (256) -#define USER_SIGNATURES_PAGE_SIZE (256) -#define USER_SIGNATURES_END (USER_SIGNATURES_START + USER_SIGNATURES_SIZE - 1) - -#define PROD_SIGNATURES_START (0x0000) -#define PROD_SIGNATURES_SIZE (64) -#define PROD_SIGNATURES_PAGE_SIZE (256) -#define PROD_SIGNATURES_END (PROD_SIGNATURES_START + PROD_SIGNATURES_SIZE - 1) - -#define FLASHSTART PROGMEM_START -#define FLASHEND PROGMEM_END -#define SPM_PAGESIZE 256 -#define RAMSTART INTERNAL_SRAM_START -#define RAMSIZE INTERNAL_SRAM_SIZE -#define RAMEND INTERNAL_SRAM_END -#define E2END EEPROM_END -#define E2PAGESIZE EEPROM_PAGE_SIZE - - -/* ========== Fuses ========== */ -#define FUSE_MEMORY_SIZE 6 - -/* Fuse Byte 0 Reserved */ - -/* Fuse Byte 1 */ -#define FUSE_WDP0 (unsigned char)~_BV(0) /* Watchdog Timeout Period Bit 0 */ -#define FUSE_WDP1 (unsigned char)~_BV(1) /* Watchdog Timeout Period Bit 1 */ -#define FUSE_WDP2 (unsigned char)~_BV(2) /* Watchdog Timeout Period Bit 2 */ -#define FUSE_WDP3 (unsigned char)~_BV(3) /* Watchdog Timeout Period Bit 3 */ -#define FUSE_WDWP0 (unsigned char)~_BV(4) /* Watchdog Window Timeout Period Bit 0 */ -#define FUSE_WDWP1 (unsigned char)~_BV(5) /* Watchdog Window Timeout Period Bit 1 */ -#define FUSE_WDWP2 (unsigned char)~_BV(6) /* Watchdog Window Timeout Period Bit 2 */ -#define FUSE_WDWP3 (unsigned char)~_BV(7) /* Watchdog Window Timeout Period Bit 3 */ -#define FUSE1_DEFAULT (0xFF) - -/* Fuse Byte 2 */ -#define FUSE_BODPD0 (unsigned char)~_BV(0) /* BOD Operation in Power-Down Mode Bit 0 */ -#define FUSE_BODPD1 (unsigned char)~_BV(1) /* BOD Operation in Power-Down Mode Bit 1 */ -#define FUSE_TOSCSEL (unsigned char)~_BV(5) /* Timer Oscillator pin location */ -#define FUSE_BOOTRST (unsigned char)~_BV(6) /* Boot Loader Section Reset Vector */ -#define FUSE2_DEFAULT (0xFF) - -/* Fuse Byte 3 Reserved */ - -/* Fuse Byte 4 */ -#define FUSE_WDLOCK (unsigned char)~_BV(1) /* Watchdog Timer Lock */ -#define FUSE_SUT0 (unsigned char)~_BV(2) /* Start-up Time Bit 0 */ -#define FUSE_SUT1 (unsigned char)~_BV(3) /* Start-up Time Bit 1 */ -#define FUSE_RSTDISBL (unsigned char)~_BV(4) /* External Reset Disable */ -#define FUSE4_DEFAULT (0xFF) - -/* Fuse Byte 5 */ -#define FUSE_BODLVL0 (unsigned char)~_BV(0) /* Brownout Detection Voltage Level Bit 0 */ -#define FUSE_BODLVL1 (unsigned char)~_BV(1) /* Brownout Detection Voltage Level Bit 1 */ -#define FUSE_BODLVL2 (unsigned char)~_BV(2) /* Brownout Detection Voltage Level Bit 2 */ -#define FUSE_EESAVE (unsigned char)~_BV(3) /* Preserve EEPROM Through Chip Erase */ -#define FUSE_BODACT0 (unsigned char)~_BV(4) /* BOD Operation in Active Mode Bit 0 */ -#define FUSE_BODACT1 (unsigned char)~_BV(5) /* BOD Operation in Active Mode Bit 1 */ -#define FUSE5_DEFAULT (0xFF) - -/* ========== Lock Bits ========== */ -#define __LOCK_BITS_EXIST -#define __BOOT_LOCK_APPLICATION_TABLE_BITS_EXIST -#define __BOOT_LOCK_APPLICATION_BITS_EXIST -#define __BOOT_LOCK_BOOT_BITS_EXIST - -/* ========== Signature ========== */ -#define SIGNATURE_0 0x1E -#define SIGNATURE_1 0x95 -#define SIGNATURE_2 0x44 - -/* ========== Power Reduction Condition Definitions ========== */ - -/* PR.PRGEN */ -#define __AVR_HAVE_PRGEN (PR_USB_bm|PR_AES_bm|PR_RTC_bm|PR_EVSYS_bm|PR_DMA_bm) -#define __AVR_HAVE_PRGEN_USB -#define __AVR_HAVE_PRGEN_AES -#define __AVR_HAVE_PRGEN_RTC -#define __AVR_HAVE_PRGEN_EVSYS -#define __AVR_HAVE_PRGEN_DMA - -/* PR.PRPA */ -#define __AVR_HAVE_PRPA (PR_ADC_bm|PR_AC_bm) -#define __AVR_HAVE_PRPA_ADC -#define __AVR_HAVE_PRPA_AC - -/* PR.PRPC */ -#define __AVR_HAVE_PRPC (PR_TWI_bm|PR_USART1_bm|PR_USART0_bm|PR_SPI_bm|PR_HIRES_bm|PR_TC1_bm|PR_TC0_bm) -#define __AVR_HAVE_PRPC_TWI -#define __AVR_HAVE_PRPC_USART1 -#define __AVR_HAVE_PRPC_USART0 -#define __AVR_HAVE_PRPC_SPI -#define __AVR_HAVE_PRPC_HIRES -#define __AVR_HAVE_PRPC_TC1 -#define __AVR_HAVE_PRPC_TC0 - -/* PR.PRPD */ -#define __AVR_HAVE_PRPD (PR_USART0_bm|PR_SPI_bm|PR_TC0_bm) -#define __AVR_HAVE_PRPD_USART0 -#define __AVR_HAVE_PRPD_SPI -#define __AVR_HAVE_PRPD_TC0 - -/* PR.PRPE */ -#define __AVR_HAVE_PRPE (PR_TWI_bm|PR_USART0_bm|PR_TC0_bm) -#define __AVR_HAVE_PRPE_TWI -#define __AVR_HAVE_PRPE_USART0 -#define __AVR_HAVE_PRPE_TC0 - -/* PR.PRPF */ -#define __AVR_HAVE_PRPF (PR_USART0_bm|PR_TC0_bm) -#define __AVR_HAVE_PRPF_USART0 -#define __AVR_HAVE_PRPF_TC0 - - -#endif /* #ifdef _AVR_ATXMEGA32C4_H_INCLUDED */ - diff --git a/arduino/hardware/tools/avr/avr/include/avr/iox32d3.h b/arduino/hardware/tools/avr/avr/include/avr/iox32d3.h deleted file mode 100644 index c3dc887..0000000 --- a/arduino/hardware/tools/avr/avr/include/avr/iox32d3.h +++ /dev/null @@ -1,5105 +0,0 @@ -/***************************************************************************** - * - * Copyright (C) 2015 Atmel Corporation - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * - * * Neither the name of the copyright holders nor the names of - * contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - ****************************************************************************/ - - -#ifndef _AVR_IO_H_ -# error "Include instead of this file." -#endif - -#ifndef _AVR_IOXXX_H_ -# define _AVR_IOXXX_H_ "iox32d3.h" -#else -# error "Attempt to include more than one file." -#endif - -#ifndef _AVR_ATXMEGA32D3_H_INCLUDED -#define _AVR_ATXMEGA32D3_H_INCLUDED - -/* Ungrouped common registers */ -#define GPIOR0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ -#define GPIOR1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ -#define GPIOR2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ -#define GPIOR3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ - -/* Deprecated */ -#define GPIO0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ -#define GPIO1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ -#define GPIO2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ -#define GPIO3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ - -#define CCP _SFR_MEM8(0x0034) /* Configuration Change Protection */ -#define RAMPD _SFR_MEM8(0x0038) /* Ramp D */ -#define RAMPX _SFR_MEM8(0x0039) /* Ramp X */ -#define RAMPY _SFR_MEM8(0x003A) /* Ramp Y */ -#define RAMPZ _SFR_MEM8(0x003B) /* Ramp Z */ -#define EIND _SFR_MEM8(0x003C) /* Extended Indirect Jump */ -#define SPL _SFR_MEM8(0x003D) /* Stack Pointer Low */ -#define SPH _SFR_MEM8(0x003E) /* Stack Pointer High */ -#define SREG _SFR_MEM8(0x003F) /* Status Register */ - -/* C Language Only */ -#if !defined (__ASSEMBLER__) - -#include - -typedef volatile uint8_t register8_t; -typedef volatile uint16_t register16_t; -typedef volatile uint32_t register32_t; - - -#ifdef _WORDREGISTER -#undef _WORDREGISTER -#endif -#define _WORDREGISTER(regname) \ - __extension__ union \ - { \ - register16_t regname; \ - struct \ - { \ - register8_t regname ## L; \ - register8_t regname ## H; \ - }; \ - } - -#ifdef _DWORDREGISTER -#undef _DWORDREGISTER -#endif -#define _DWORDREGISTER(regname) \ - __extension__ union \ - { \ - register32_t regname; \ - struct \ - { \ - register8_t regname ## 0; \ - register8_t regname ## 1; \ - register8_t regname ## 2; \ - register8_t regname ## 3; \ - }; \ - } - - -/* -========================================================================== -IO Module Structures -========================================================================== -*/ - - -/* --------------------------------------------------------------------------- -XOCD - On-Chip Debug System --------------------------------------------------------------------------- -*/ - -/* On-Chip Debug System */ -typedef struct OCD_struct -{ - register8_t OCDR0; /* OCD Register 0 */ - register8_t OCDR1; /* OCD Register 1 */ -} OCD_t; - - -/* --------------------------------------------------------------------------- -CPU - CPU --------------------------------------------------------------------------- -*/ - -/* CCP signatures */ -typedef enum CCP_enum -{ - CCP_SPM_gc = (0x9D<<0), /* SPM Instruction Protection */ - CCP_IOREG_gc = (0xD8<<0), /* IO Register Protection */ -} CCP_t; - - -/* --------------------------------------------------------------------------- -CLK - Clock System --------------------------------------------------------------------------- -*/ - -/* Clock System */ -typedef struct CLK_struct -{ - register8_t CTRL; /* Control Register */ - register8_t PSCTRL; /* Prescaler Control Register */ - register8_t LOCK; /* Lock register */ - register8_t RTCCTRL; /* RTC Control Register */ - register8_t reserved_0x04; -} CLK_t; - - -/* Power Reduction */ -typedef struct PR_struct -{ - register8_t PRGEN; /* General Power Reduction */ - register8_t PRPA; /* Power Reduction Port A */ - register8_t reserved_0x02; - register8_t PRPC; /* Power Reduction Port C */ - register8_t PRPD; /* Power Reduction Port D */ - register8_t PRPE; /* Power Reduction Port E */ - register8_t PRPF; /* Power Reduction Port F */ -} PR_t; - -/* System Clock Selection */ -typedef enum CLK_SCLKSEL_enum -{ - CLK_SCLKSEL_RC2M_gc = (0x00<<0), /* Internal 2 MHz RC Oscillator */ - CLK_SCLKSEL_RC32M_gc = (0x01<<0), /* Internal 32 MHz RC Oscillator */ - CLK_SCLKSEL_RC32K_gc = (0x02<<0), /* Internal 32.768 kHz RC Oscillator */ - CLK_SCLKSEL_XOSC_gc = (0x03<<0), /* External Crystal Oscillator or Clock */ - CLK_SCLKSEL_PLL_gc = (0x04<<0), /* Phase Locked Loop */ -} CLK_SCLKSEL_t; - -/* Prescaler A Division Factor */ -typedef enum CLK_PSADIV_enum -{ - CLK_PSADIV_1_gc = (0x00<<2), /* Divide by 1 */ - CLK_PSADIV_2_gc = (0x01<<2), /* Divide by 2 */ - CLK_PSADIV_4_gc = (0x03<<2), /* Divide by 4 */ - CLK_PSADIV_8_gc = (0x05<<2), /* Divide by 8 */ - CLK_PSADIV_16_gc = (0x07<<2), /* Divide by 16 */ - CLK_PSADIV_32_gc = (0x09<<2), /* Divide by 32 */ - CLK_PSADIV_64_gc = (0x0B<<2), /* Divide by 64 */ - CLK_PSADIV_128_gc = (0x0D<<2), /* Divide by 128 */ - CLK_PSADIV_256_gc = (0x0F<<2), /* Divide by 256 */ - CLK_PSADIV_512_gc = (0x11<<2), /* Divide by 512 */ -} CLK_PSADIV_t; - -/* Prescaler B and C Division Factor */ -typedef enum CLK_PSBCDIV_enum -{ - CLK_PSBCDIV_1_1_gc = (0x00<<0), /* Divide B by 1 and C by 1 */ - CLK_PSBCDIV_1_2_gc = (0x01<<0), /* Divide B by 1 and C by 2 */ - CLK_PSBCDIV_4_1_gc = (0x02<<0), /* Divide B by 4 and C by 1 */ - CLK_PSBCDIV_2_2_gc = (0x03<<0), /* Divide B by 2 and C by 2 */ -} CLK_PSBCDIV_t; - -/* RTC Clock Source */ -typedef enum CLK_RTCSRC_enum -{ - CLK_RTCSRC_ULP_gc = (0x00<<1), /* 1 kHz from internal 32kHz ULP */ - CLK_RTCSRC_TOSC_gc = (0x01<<1), /* 1.024 kHz from 32.768 kHz crystal oscillator on TOSC */ - CLK_RTCSRC_RCOSC_gc = (0x02<<1), /* 1.024 kHz from 32.768 kHz internal oscillator */ - CLK_RTCSRC_TOSC32_gc = (0x05<<1), /* 32.768 kHz from 32.768 kHz crystal oscillator on TOSC */ - CLK_RTCSRC_RCOSC32_gc = (0x06<<1), /* 32.768 kHz from 32.768 kHz internal oscillator */ - CLK_RTCSRC_EXTCLK_gc = (0x07<<1), /* External Clock from TOSC1 */ -} CLK_RTCSRC_t; - - -/* --------------------------------------------------------------------------- -SLEEP - Sleep Controller --------------------------------------------------------------------------- -*/ - -/* Sleep Controller */ -typedef struct SLEEP_struct -{ - register8_t CTRL; /* Control Register */ -} SLEEP_t; - -/* Sleep Mode */ -typedef enum SLEEP_SMODE_enum -{ - SLEEP_SMODE_IDLE_gc = (0x00<<1), /* Idle mode */ - SLEEP_SMODE_PDOWN_gc = (0x02<<1), /* Power-down Mode */ - SLEEP_SMODE_PSAVE_gc = (0x03<<1), /* Power-save Mode */ - SLEEP_SMODE_STDBY_gc = (0x06<<1), /* Standby Mode */ - SLEEP_SMODE_ESTDBY_gc = (0x07<<1), /* Extended Standby Mode */ -} SLEEP_SMODE_t; - - - -#define SLEEP_MODE_IDLE (0x00<<1) -#define SLEEP_MODE_PWR_DOWN (0x02<<1) -#define SLEEP_MODE_PWR_SAVE (0x03<<1) -#define SLEEP_MODE_STANDBY (0x06<<1) -#define SLEEP_MODE_EXT_STANDBY (0x07<<1) -/* --------------------------------------------------------------------------- -OSC - Oscillator --------------------------------------------------------------------------- -*/ - -/* Oscillator */ -typedef struct OSC_struct -{ - register8_t CTRL; /* Control Register */ - register8_t STATUS; /* Status Register */ - register8_t XOSCCTRL; /* External Oscillator Control Register */ - register8_t XOSCFAIL; /* External Oscillator Failure Detection Register */ - register8_t RC32KCAL; /* 32kHz Internal Oscillator Calibration Register */ - register8_t PLLCTRL; /* PLL Control REgister */ - register8_t DFLLCTRL; /* DFLL Control Register */ -} OSC_t; - -/* Oscillator Frequency Range */ -typedef enum OSC_FRQRANGE_enum -{ - OSC_FRQRANGE_04TO2_gc = (0x00<<6), /* 0.4 - 2 MHz */ - OSC_FRQRANGE_2TO9_gc = (0x01<<6), /* 2 - 9 MHz */ - OSC_FRQRANGE_9TO12_gc = (0x02<<6), /* 9 - 12 MHz */ - OSC_FRQRANGE_12TO16_gc = (0x03<<6), /* 12 - 16 MHz */ -} OSC_FRQRANGE_t; - -/* External Oscillator Selection and Startup Time */ -typedef enum OSC_XOSCSEL_enum -{ - OSC_XOSCSEL_EXTCLK_gc = (0x00<<0), /* External Clock - 6 CLK */ - OSC_XOSCSEL_32KHz_gc = (0x02<<0), /* 32kHz TOSC - 32K CLK */ - OSC_XOSCSEL_XTAL_256CLK_gc = (0x03<<0), /* 0.4-16MHz XTAL - 256 CLK */ - OSC_XOSCSEL_XTAL_1KCLK_gc = (0x07<<0), /* 0.4-16MHz XTAL - 1K CLK */ - OSC_XOSCSEL_XTAL_16KCLK_gc = (0x0B<<0), /* 0.4-16MHz XTAL - 16K CLK */ -} OSC_XOSCSEL_t; - -/* PLL Clock Source */ -typedef enum OSC_PLLSRC_enum -{ - OSC_PLLSRC_RC2M_gc = (0x00<<6), /* Internal 2MHz RC Oscillator */ - OSC_PLLSRC_RC32M_gc = (0x02<<6), /* Internal 32MHz RC Oscillator */ - OSC_PLLSRC_XOSC_gc = (0x03<<6), /* External Oscillator */ -} OSC_PLLSRC_t; - - -/* --------------------------------------------------------------------------- -DFLL - DFLL --------------------------------------------------------------------------- -*/ - -/* DFLL */ -typedef struct DFLL_struct -{ - register8_t CTRL; /* Control Register */ - register8_t reserved_0x01; - register8_t CALA; /* Calibration Register A */ - register8_t CALB; /* Calibration Register B */ - register8_t COMP0; /* Oscillator Compare Register 0 */ - register8_t COMP1; /* Oscillator Compare Register 1 */ - register8_t COMP2; /* Oscillator Compare Register 2 */ - register8_t reserved_0x07; -} DFLL_t; - - -/* --------------------------------------------------------------------------- -RST - Reset --------------------------------------------------------------------------- -*/ - -/* Reset */ -typedef struct RST_struct -{ - register8_t STATUS; /* Status Register */ - register8_t CTRL; /* Control Register */ -} RST_t; - - -/* --------------------------------------------------------------------------- -WDT - Watch-Dog Timer --------------------------------------------------------------------------- -*/ - -/* Watch-Dog Timer */ -typedef struct WDT_struct -{ - register8_t CTRL; /* Control */ - register8_t WINCTRL; /* Windowed Mode Control */ - register8_t STATUS; /* Status */ -} WDT_t; - -/* Period setting */ -typedef enum WDT_PER_enum -{ - WDT_PER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ - WDT_PER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ - WDT_PER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ - WDT_PER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ - WDT_PER_128CLK_gc = (0x04<<2), /* 128 cycles (0.128s @ 3.3V) */ - WDT_PER_256CLK_gc = (0x05<<2), /* 256 cycles (0.256s @ 3.3V) */ - WDT_PER_512CLK_gc = (0x06<<2), /* 512 cycles (0.512s @ 3.3V) */ - WDT_PER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ - WDT_PER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ - WDT_PER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ - WDT_PER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ -} WDT_PER_t; - -/* Closed window period */ -typedef enum WDT_WPER_enum -{ - WDT_WPER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ - WDT_WPER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ - WDT_WPER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ - WDT_WPER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ - WDT_WPER_128CLK_gc = (0x04<<2), /* 128 cycles (0.128s @ 3.3V) */ - WDT_WPER_256CLK_gc = (0x05<<2), /* 256 cycles (0.256s @ 3.3V) */ - WDT_WPER_512CLK_gc = (0x06<<2), /* 512 cycles (0.512s @ 3.3V) */ - WDT_WPER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ - WDT_WPER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ - WDT_WPER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ - WDT_WPER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ -} WDT_WPER_t; - - -/* --------------------------------------------------------------------------- -MCU - MCU Control --------------------------------------------------------------------------- -*/ - -/* MCU Control */ -typedef struct MCU_struct -{ - register8_t DEVID0; /* Device ID byte 0 */ - register8_t DEVID1; /* Device ID byte 1 */ - register8_t DEVID2; /* Device ID byte 2 */ - register8_t REVID; /* Revision ID */ - register8_t JTAGUID; /* JTAG User ID */ - register8_t reserved_0x05; - register8_t MCUCR; /* MCU Control */ - register8_t reserved_0x07; - register8_t EVSYSLOCK; /* Event System Lock */ - register8_t AWEXLOCK; /* AWEX Lock */ - register8_t reserved_0x0A; - register8_t reserved_0x0B; -} MCU_t; - - -/* --------------------------------------------------------------------------- -PMIC - Programmable Multi-level Interrupt Controller --------------------------------------------------------------------------- -*/ - -/* Programmable Multi-level Interrupt Controller */ -typedef struct PMIC_struct -{ - register8_t STATUS; /* Status Register */ - register8_t INTPRI; /* Interrupt Priority */ - register8_t CTRL; /* Control Register */ - register8_t reserved_0x03; - register8_t reserved_0x04; - register8_t reserved_0x05; - register8_t reserved_0x06; - register8_t reserved_0x07; - register8_t reserved_0x08; - register8_t reserved_0x09; - register8_t reserved_0x0A; - register8_t reserved_0x0B; - register8_t reserved_0x0C; - register8_t reserved_0x0D; - register8_t reserved_0x0E; - register8_t reserved_0x0F; -} PMIC_t; - - -/* --------------------------------------------------------------------------- -CRC - Cyclic Redundancy Checker --------------------------------------------------------------------------- -*/ - -/* Cyclic Redundancy Checker */ -typedef struct CRC_struct -{ - register8_t CTRL; /* Control Register */ - register8_t STATUS; /* Status Register */ - register8_t reserved_0x02; - register8_t DATAIN; /* Data Input */ - register8_t CHECKSUM0; /* Checksum byte 0 */ - register8_t CHECKSUM1; /* Checksum byte 1 */ - register8_t CHECKSUM2; /* Checksum byte 2 */ - register8_t CHECKSUM3; /* Checksum byte 3 */ -} CRC_t; - -/* Reset */ -typedef enum CRC_RESET_enum -{ - CRC_RESET_NO_gc = (0x00<<6), /* No Reset */ - CRC_RESET_RESET0_gc = (0x02<<6), /* Reset CRC with CHECKSUM to all zeros */ - CRC_RESET_RESET1_gc = (0x03<<6), /* Reset CRC with CHECKSUM to all ones */ -} CRC_RESET_t; - -/* Input Source */ -typedef enum CRC_SOURCE_enum -{ - CRC_SOURCE_DISABLE_gc = (0x00<<0), /* Disabled */ - CRC_SOURCE_IO_gc = (0x01<<0), /* I/O Interface */ - CRC_SOURCE_FLASH_gc = (0x02<<0), /* Flash */ -} CRC_SOURCE_t; - - -/* --------------------------------------------------------------------------- -EVSYS - Event System --------------------------------------------------------------------------- -*/ - -/* Event System */ -typedef struct EVSYS_struct -{ - register8_t CH0MUX; /* Event Channel 0 Multiplexer */ - register8_t CH1MUX; /* Event Channel 1 Multiplexer */ - register8_t CH2MUX; /* Event Channel 2 Multiplexer */ - register8_t CH3MUX; /* Event Channel 3 Multiplexer */ - register8_t reserved_0x04; - register8_t reserved_0x05; - register8_t reserved_0x06; - register8_t reserved_0x07; - register8_t CH0CTRL; /* Channel 0 Control Register */ - register8_t CH1CTRL; /* Channel 1 Control Register */ - register8_t CH2CTRL; /* Channel 2 Control Register */ - register8_t CH3CTRL; /* Channel 3 Control Register */ - register8_t reserved_0x0C; - register8_t reserved_0x0D; - register8_t reserved_0x0E; - register8_t reserved_0x0F; - register8_t STROBE; /* Event Strobe */ - register8_t DATA; /* Event Data */ -} EVSYS_t; - -/* Quadrature Decoder Index Recognition Mode */ -typedef enum EVSYS_QDIRM_enum -{ - EVSYS_QDIRM_00_gc = (0x00<<5), /* QDPH0 = 0, QDPH90 = 0 */ - EVSYS_QDIRM_01_gc = (0x01<<5), /* QDPH0 = 0, QDPH90 = 1 */ - EVSYS_QDIRM_10_gc = (0x02<<5), /* QDPH0 = 1, QDPH90 = 0 */ - EVSYS_QDIRM_11_gc = (0x03<<5), /* QDPH0 = 1, QDPH90 = 1 */ -} EVSYS_QDIRM_t; - -/* Digital filter coefficient */ -typedef enum EVSYS_DIGFILT_enum -{ - EVSYS_DIGFILT_1SAMPLE_gc = (0x00<<0), /* 1 SAMPLE */ - EVSYS_DIGFILT_2SAMPLES_gc = (0x01<<0), /* 2 SAMPLES */ - EVSYS_DIGFILT_3SAMPLES_gc = (0x02<<0), /* 3 SAMPLES */ - EVSYS_DIGFILT_4SAMPLES_gc = (0x03<<0), /* 4 SAMPLES */ - EVSYS_DIGFILT_5SAMPLES_gc = (0x04<<0), /* 5 SAMPLES */ - EVSYS_DIGFILT_6SAMPLES_gc = (0x05<<0), /* 6 SAMPLES */ - EVSYS_DIGFILT_7SAMPLES_gc = (0x06<<0), /* 7 SAMPLES */ - EVSYS_DIGFILT_8SAMPLES_gc = (0x07<<0), /* 8 SAMPLES */ -} EVSYS_DIGFILT_t; - -/* Event Channel multiplexer input selection */ -typedef enum EVSYS_CHMUX_enum -{ - EVSYS_CHMUX_OFF_gc = (0x00<<0), /* Off */ - EVSYS_CHMUX_RTC_OVF_gc = (0x08<<0), /* RTC Overflow */ - EVSYS_CHMUX_RTC_CMP_gc = (0x09<<0), /* RTC Compare Match */ - EVSYS_CHMUX_ACA_CH0_gc = (0x10<<0), /* Analog Comparator A Channel 0 */ - EVSYS_CHMUX_ACA_CH1_gc = (0x11<<0), /* Analog Comparator A Channel 1 */ - EVSYS_CHMUX_ACA_WIN_gc = (0x12<<0), /* Analog Comparator A Window */ - EVSYS_CHMUX_ADCA_CH0_gc = (0x20<<0), /* ADC A Channel 0 */ - EVSYS_CHMUX_PORTA_PIN0_gc = (0x50<<0), /* Port A, Pin0 */ - EVSYS_CHMUX_PORTA_PIN1_gc = (0x51<<0), /* Port A, Pin1 */ - EVSYS_CHMUX_PORTA_PIN2_gc = (0x52<<0), /* Port A, Pin2 */ - EVSYS_CHMUX_PORTA_PIN3_gc = (0x53<<0), /* Port A, Pin3 */ - EVSYS_CHMUX_PORTA_PIN4_gc = (0x54<<0), /* Port A, Pin4 */ - EVSYS_CHMUX_PORTA_PIN5_gc = (0x55<<0), /* Port A, Pin5 */ - EVSYS_CHMUX_PORTA_PIN6_gc = (0x56<<0), /* Port A, Pin6 */ - EVSYS_CHMUX_PORTA_PIN7_gc = (0x57<<0), /* Port A, Pin7 */ - EVSYS_CHMUX_PORTB_PIN0_gc = (0x58<<0), /* Port B, Pin0 */ - EVSYS_CHMUX_PORTB_PIN1_gc = (0x59<<0), /* Port B, Pin1 */ - EVSYS_CHMUX_PORTB_PIN2_gc = (0x5A<<0), /* Port B, Pin2 */ - EVSYS_CHMUX_PORTB_PIN3_gc = (0x5B<<0), /* Port B, Pin3 */ - EVSYS_CHMUX_PORTB_PIN4_gc = (0x5C<<0), /* Port B, Pin4 */ - EVSYS_CHMUX_PORTB_PIN5_gc = (0x5D<<0), /* Port B, Pin5 */ - EVSYS_CHMUX_PORTB_PIN6_gc = (0x5E<<0), /* Port B, Pin6 */ - EVSYS_CHMUX_PORTB_PIN7_gc = (0x5F<<0), /* Port B, Pin7 */ - EVSYS_CHMUX_PORTC_PIN0_gc = (0x60<<0), /* Port C, Pin0 */ - EVSYS_CHMUX_PORTC_PIN1_gc = (0x61<<0), /* Port C, Pin1 */ - EVSYS_CHMUX_PORTC_PIN2_gc = (0x62<<0), /* Port C, Pin2 */ - EVSYS_CHMUX_PORTC_PIN3_gc = (0x63<<0), /* Port C, Pin3 */ - EVSYS_CHMUX_PORTC_PIN4_gc = (0x64<<0), /* Port C, Pin4 */ - EVSYS_CHMUX_PORTC_PIN5_gc = (0x65<<0), /* Port C, Pin5 */ - EVSYS_CHMUX_PORTC_PIN6_gc = (0x66<<0), /* Port C, Pin6 */ - EVSYS_CHMUX_PORTC_PIN7_gc = (0x67<<0), /* Port C, Pin7 */ - EVSYS_CHMUX_PORTD_PIN0_gc = (0x68<<0), /* Port D, Pin0 */ - EVSYS_CHMUX_PORTD_PIN1_gc = (0x69<<0), /* Port D, Pin1 */ - EVSYS_CHMUX_PORTD_PIN2_gc = (0x6A<<0), /* Port D, Pin2 */ - EVSYS_CHMUX_PORTD_PIN3_gc = (0x6B<<0), /* Port D, Pin3 */ - EVSYS_CHMUX_PORTD_PIN4_gc = (0x6C<<0), /* Port D, Pin4 */ - EVSYS_CHMUX_PORTD_PIN5_gc = (0x6D<<0), /* Port D, Pin5 */ - EVSYS_CHMUX_PORTD_PIN6_gc = (0x6E<<0), /* Port D, Pin6 */ - EVSYS_CHMUX_PORTD_PIN7_gc = (0x6F<<0), /* Port D, Pin7 */ - EVSYS_CHMUX_PORTE_PIN0_gc = (0x70<<0), /* Port E, Pin0 */ - EVSYS_CHMUX_PORTE_PIN1_gc = (0x71<<0), /* Port E, Pin1 */ - EVSYS_CHMUX_PORTE_PIN2_gc = (0x72<<0), /* Port E, Pin2 */ - EVSYS_CHMUX_PORTE_PIN3_gc = (0x73<<0), /* Port E, Pin3 */ - EVSYS_CHMUX_PORTE_PIN4_gc = (0x74<<0), /* Port E, Pin4 */ - EVSYS_CHMUX_PORTE_PIN5_gc = (0x75<<0), /* Port E, Pin5 */ - EVSYS_CHMUX_PORTE_PIN6_gc = (0x76<<0), /* Port E, Pin6 */ - EVSYS_CHMUX_PORTE_PIN7_gc = (0x77<<0), /* Port E, Pin7 */ - EVSYS_CHMUX_PORTF_PIN0_gc = (0x78<<0), /* Port F, Pin0 */ - EVSYS_CHMUX_PORTF_PIN1_gc = (0x79<<0), /* Port F, Pin1 */ - EVSYS_CHMUX_PORTF_PIN2_gc = (0x7A<<0), /* Port F, Pin2 */ - EVSYS_CHMUX_PORTF_PIN3_gc = (0x7B<<0), /* Port F, Pin3 */ - EVSYS_CHMUX_PORTF_PIN4_gc = (0x7C<<0), /* Port F, Pin4 */ - EVSYS_CHMUX_PORTF_PIN5_gc = (0x7D<<0), /* Port F, Pin5 */ - EVSYS_CHMUX_PORTF_PIN6_gc = (0x7E<<0), /* Port F, Pin6 */ - EVSYS_CHMUX_PORTF_PIN7_gc = (0x7F<<0), /* Port F, Pin7 */ - EVSYS_CHMUX_PRESCALER_1_gc = (0x80<<0), /* Prescaler, divide by 1 */ - EVSYS_CHMUX_PRESCALER_2_gc = (0x81<<0), /* Prescaler, divide by 2 */ - EVSYS_CHMUX_PRESCALER_4_gc = (0x82<<0), /* Prescaler, divide by 4 */ - EVSYS_CHMUX_PRESCALER_8_gc = (0x83<<0), /* Prescaler, divide by 8 */ - EVSYS_CHMUX_PRESCALER_16_gc = (0x84<<0), /* Prescaler, divide by 16 */ - EVSYS_CHMUX_PRESCALER_32_gc = (0x85<<0), /* Prescaler, divide by 32 */ - EVSYS_CHMUX_PRESCALER_64_gc = (0x86<<0), /* Prescaler, divide by 64 */ - EVSYS_CHMUX_PRESCALER_128_gc = (0x87<<0), /* Prescaler, divide by 128 */ - EVSYS_CHMUX_PRESCALER_256_gc = (0x88<<0), /* Prescaler, divide by 256 */ - EVSYS_CHMUX_PRESCALER_512_gc = (0x89<<0), /* Prescaler, divide by 512 */ - EVSYS_CHMUX_PRESCALER_1024_gc = (0x8A<<0), /* Prescaler, divide by 1024 */ - EVSYS_CHMUX_PRESCALER_2048_gc = (0x8B<<0), /* Prescaler, divide by 2048 */ - EVSYS_CHMUX_PRESCALER_4096_gc = (0x8C<<0), /* Prescaler, divide by 4096 */ - EVSYS_CHMUX_PRESCALER_8192_gc = (0x8D<<0), /* Prescaler, divide by 8192 */ - EVSYS_CHMUX_PRESCALER_16384_gc = (0x8E<<0), /* Prescaler, divide by 16384 */ - EVSYS_CHMUX_PRESCALER_32768_gc = (0x8F<<0), /* Prescaler, divide by 32768 */ - EVSYS_CHMUX_TCC0_OVF_gc = (0xC0<<0), /* Timer/Counter C0 Overflow */ - EVSYS_CHMUX_TCC0_ERR_gc = (0xC1<<0), /* Timer/Counter C0 Error */ - EVSYS_CHMUX_TCC0_CCA_gc = (0xC4<<0), /* Timer/Counter C0 Compare or Capture A */ - EVSYS_CHMUX_TCC0_CCB_gc = (0xC5<<0), /* Timer/Counter C0 Compare or Capture B */ - EVSYS_CHMUX_TCC0_CCC_gc = (0xC6<<0), /* Timer/Counter C0 Compare or Capture C */ - EVSYS_CHMUX_TCC0_CCD_gc = (0xC7<<0), /* Timer/Counter C0 Compare or Capture D */ - EVSYS_CHMUX_TCC1_OVF_gc = (0xC8<<0), /* Timer/Counter C1 Overflow */ - EVSYS_CHMUX_TCC1_ERR_gc = (0xC9<<0), /* Timer/Counter C1 Error */ - EVSYS_CHMUX_TCC1_CCA_gc = (0xCC<<0), /* Timer/Counter C1 Compare or Capture A */ - EVSYS_CHMUX_TCC1_CCB_gc = (0xCD<<0), /* Timer/Counter C1 Compare or Capture B */ - EVSYS_CHMUX_TCD0_OVF_gc = (0xD0<<0), /* Timer/Counter D0 Overflow */ - EVSYS_CHMUX_TCD0_ERR_gc = (0xD1<<0), /* Timer/Counter D0 Error */ - EVSYS_CHMUX_TCD0_CCA_gc = (0xD4<<0), /* Timer/Counter D0 Compare or Capture A */ - EVSYS_CHMUX_TCD0_CCB_gc = (0xD5<<0), /* Timer/Counter D0 Compare or Capture B */ - EVSYS_CHMUX_TCD0_CCC_gc = (0xD6<<0), /* Timer/Counter D0 Compare or Capture C */ - EVSYS_CHMUX_TCD0_CCD_gc = (0xD7<<0), /* Timer/Counter D0 Compare or Capture D */ - EVSYS_CHMUX_TCE0_OVF_gc = (0xE0<<0), /* Timer/Counter E0 Overflow */ - EVSYS_CHMUX_TCE0_ERR_gc = (0xE1<<0), /* Timer/Counter E0 Error */ - EVSYS_CHMUX_TCE0_CCA_gc = (0xE4<<0), /* Timer/Counter E0 Compare or Capture A */ - EVSYS_CHMUX_TCE0_CCB_gc = (0xE5<<0), /* Timer/Counter E0 Compare or Capture B */ - EVSYS_CHMUX_TCE0_CCC_gc = (0xE6<<0), /* Timer/Counter E0 Compare or Capture C */ - EVSYS_CHMUX_TCE0_CCD_gc = (0xE7<<0), /* Timer/Counter E0 Compare or Capture D */ - EVSYS_CHMUX_TCF0_OVF_gc = (0xF0<<0), /* Timer/Counter F0 Overflow */ - EVSYS_CHMUX_TCF0_ERR_gc = (0xF1<<0), /* Timer/Counter F0 Error */ - EVSYS_CHMUX_TCF0_CCA_gc = (0xF4<<0), /* Timer/Counter F0 Compare or Capture A */ - EVSYS_CHMUX_TCF0_CCB_gc = (0xF5<<0), /* Timer/Counter F0 Compare or Capture B */ - EVSYS_CHMUX_TCF0_CCC_gc = (0xF6<<0), /* Timer/Counter F0 Compare or Capture C */ - EVSYS_CHMUX_TCF0_CCD_gc = (0xF7<<0), /* Timer/Counter F0 Compare or Capture D */ -} EVSYS_CHMUX_t; - - -/* --------------------------------------------------------------------------- -NVM - Non Volatile Memory Controller --------------------------------------------------------------------------- -*/ - -/* Non-volatile Memory Controller */ -typedef struct NVM_struct -{ - register8_t ADDR0; /* Address Register 0 */ - register8_t ADDR1; /* Address Register 1 */ - register8_t ADDR2; /* Address Register 2 */ - register8_t reserved_0x03; - register8_t DATA0; /* Data Register 0 */ - register8_t DATA1; /* Data Register 1 */ - register8_t DATA2; /* Data Register 2 */ - register8_t reserved_0x07; - register8_t reserved_0x08; - register8_t reserved_0x09; - register8_t CMD; /* Command */ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t INTCTRL; /* Interrupt Control */ - register8_t reserved_0x0E; - register8_t STATUS; /* Status */ - register8_t LOCK_BITS; /* Lock Bits (Changed from LOCKBITS to avoid avr-libc collision) */ -} NVM_t; - - -/* Lock Bits */ -typedef struct NVM_LOCKBITS_struct -{ - register8_t LOCK_BITS; /* Lock Bits (Changed from LOCKBITS to avoid avr-libc collision) */ -} NVM_LOCKBITS_t; - - -/* Fuses */ -typedef struct NVM_FUSES_struct -{ - register8_t reserved_0x00; - register8_t FUSEBYTE1; /* Watchdog Configuration */ - register8_t FUSEBYTE2; /* Reset Configuration */ - register8_t reserved_0x03; - register8_t FUSEBYTE4; /* Start-up Configuration */ - register8_t FUSEBYTE5; /* EESAVE and BOD Level */ -} NVM_FUSES_t; - - -/* Production Signatures */ -typedef struct NVM_PROD_SIGNATURES_struct -{ - register8_t RCOSC2M; /* RCOSC 2MHz Calibration Value */ - register8_t reserved_0x01; - register8_t RCOSC32K; /* RCOSC 32kHz Calibration Value */ - register8_t RCOSC32M; /* RCOSC 32MHz Calibration Value */ - register8_t reserved_0x04; - register8_t reserved_0x05; - register8_t reserved_0x06; - register8_t reserved_0x07; - register8_t LOTNUM0; /* Lot Number Byte 0, ASCII */ - register8_t LOTNUM1; /* Lot Number Byte 1, ASCII */ - register8_t LOTNUM2; /* Lot Number Byte 2, ASCII */ - register8_t LOTNUM3; /* Lot Number Byte 3, ASCII */ - register8_t LOTNUM4; /* Lot Number Byte 4, ASCII */ - register8_t LOTNUM5; /* Lot Number Byte 5, ASCII */ - register8_t reserved_0x0E; - register8_t reserved_0x0F; - register8_t WAFNUM; /* Wafer Number */ - register8_t reserved_0x11; - register8_t COORDX0; /* Wafer Coordinate X Byte 0 */ - register8_t COORDX1; /* Wafer Coordinate X Byte 1 */ - register8_t COORDY0; /* Wafer Coordinate Y Byte 0 */ - register8_t COORDY1; /* Wafer Coordinate Y Byte 1 */ - register8_t reserved_0x16; - register8_t reserved_0x17; - register8_t reserved_0x18; - register8_t reserved_0x19; - register8_t reserved_0x1A; - register8_t reserved_0x1B; - register8_t reserved_0x1C; - register8_t reserved_0x1D; - register8_t reserved_0x1E; - register8_t reserved_0x1F; - register8_t ADCACAL0; /* ADCA Calibration Byte 0 */ - register8_t ADCACAL1; /* ADCA Calibration Byte 1 */ - register8_t reserved_0x22; - register8_t reserved_0x23; - register8_t ADCBCAL0; /* ADCB Calibration Byte 0 */ - register8_t ADCBCAL1; /* ADCB Calibration Byte 1 */ - register8_t reserved_0x26; - register8_t reserved_0x27; - register8_t reserved_0x28; - register8_t reserved_0x29; - register8_t reserved_0x2A; - register8_t reserved_0x2B; - register8_t reserved_0x2C; - register8_t reserved_0x2D; - register8_t TEMPSENSE0; /* Temperature Sensor Calibration Byte 0 */ - register8_t TEMPSENSE1; /* Temperature Sensor Calibration Byte 0 */ - register8_t reserved_0x30; - register8_t reserved_0x31; - register8_t reserved_0x32; - register8_t reserved_0x33; - register8_t reserved_0x34; - register8_t reserved_0x35; - register8_t reserved_0x36; - register8_t reserved_0x37; - register8_t reserved_0x38; - register8_t reserved_0x39; - register8_t reserved_0x3A; - register8_t reserved_0x3B; - register8_t reserved_0x3C; - register8_t reserved_0x3D; - register8_t reserved_0x3E; -} NVM_PROD_SIGNATURES_t; - -/* NVM Command */ -typedef enum NVM_CMD_enum -{ - NVM_CMD_NO_OPERATION_gc = (0x00<<0), /* Noop/Ordinary LPM */ - NVM_CMD_READ_CALIB_ROW_gc = (0x02<<0), /* Read calibration row */ - NVM_CMD_READ_USER_SIG_ROW_gc = (0x01<<0), /* Read user signature row */ - NVM_CMD_READ_EEPROM_gc = (0x06<<0), /* Read EEPROM */ - NVM_CMD_READ_FUSES_gc = (0x07<<0), /* Read fuse byte */ - NVM_CMD_WRITE_LOCK_BITS_gc = (0x08<<0), /* Write lock bits */ - NVM_CMD_ERASE_USER_SIG_ROW_gc = (0x18<<0), /* Erase user signature row */ - NVM_CMD_WRITE_USER_SIG_ROW_gc = (0x1A<<0), /* Write user signature row */ - NVM_CMD_ERASE_APP_gc = (0x20<<0), /* Erase Application Section */ - NVM_CMD_ERASE_APP_PAGE_gc = (0x22<<0), /* Erase Application Section page */ - NVM_CMD_LOAD_FLASH_BUFFER_gc = (0x23<<0), /* Load Flash page buffer */ - NVM_CMD_WRITE_APP_PAGE_gc = (0x24<<0), /* Write Application Section page */ - NVM_CMD_ERASE_WRITE_APP_PAGE_gc = (0x25<<0), /* Erase-and-write Application Section page */ - NVM_CMD_ERASE_FLASH_BUFFER_gc = (0x26<<0), /* Erase/flush Flash page buffer */ - NVM_CMD_ERASE_BOOT_PAGE_gc = (0x2A<<0), /* Erase Boot Section page */ - NVM_CMD_ERASE_FLASH_PAGE_gc = (0x2B<<0), /* Erase Flash page */ - NVM_CMD_WRITE_BOOT_PAGE_gc = (0x2C<<0), /* Write Boot Section page */ - NVM_CMD_ERASE_WRITE_BOOT_PAGE_gc = (0x2D<<0), /* Erase-and-write Boot Section page */ - NVM_CMD_WRITE_FLASH_PAGE_gc = (0x2E<<0), /* Write Flash page */ - NVM_CMD_ERASE_WRITE_FLASH_PAGE_gc = (0x2F<<0), /* Erase and Write Flash page */ - NVM_CMD_ERASE_EEPROM_gc = (0x30<<0), /* Erase EEPROM */ - NVM_CMD_ERASE_EEPROM_PAGE_gc = (0x32<<0), /* Erase EEPROM page */ - NVM_CMD_LOAD_EEPROM_BUFFER_gc = (0x33<<0), /* Load EEPROM page buffer */ - NVM_CMD_WRITE_EEPROM_PAGE_gc = (0x34<<0), /* Write EEPROM page */ - NVM_CMD_ERASE_WRITE_EEPROM_PAGE_gc = (0x35<<0), /* Erase-and-write EEPROM page */ - NVM_CMD_ERASE_EEPROM_BUFFER_gc = (0x36<<0), /* Erase/flush EEPROM page buffer */ - NVM_CMD_APP_CRC_gc = (0x38<<0), /* Generate Application section CRC */ - NVM_CMD_BOOT_CRC_gc = (0x39<<0), /* Generate Boot Section CRC */ - NVM_CMD_FLASH_RANGE_CRC_gc = (0x3A<<0), /* Generate Flash Range CRC */ -} NVM_CMD_t; - -/* SPM ready interrupt level */ -typedef enum NVM_SPMLVL_enum -{ - NVM_SPMLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ - NVM_SPMLVL_LO_gc = (0x01<<2), /* Low level */ - NVM_SPMLVL_MED_gc = (0x02<<2), /* Medium level */ - NVM_SPMLVL_HI_gc = (0x03<<2), /* High level */ -} NVM_SPMLVL_t; - -/* EEPROM ready interrupt level */ -typedef enum NVM_EELVL_enum -{ - NVM_EELVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ - NVM_EELVL_LO_gc = (0x01<<0), /* Low level */ - NVM_EELVL_MED_gc = (0x02<<0), /* Medium level */ - NVM_EELVL_HI_gc = (0x03<<0), /* High level */ -} NVM_EELVL_t; - -/* Boot lock bits - boot setcion */ -typedef enum NVM_BLBB_enum -{ - NVM_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ - NVM_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ - NVM_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ - NVM_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ -} NVM_BLBB_t; - -/* Boot lock bits - application section */ -typedef enum NVM_BLBA_enum -{ - NVM_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ - NVM_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ - NVM_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ - NVM_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ -} NVM_BLBA_t; - -/* Boot lock bits - application table section */ -typedef enum NVM_BLBAT_enum -{ - NVM_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ - NVM_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ - NVM_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ - NVM_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ -} NVM_BLBAT_t; - -/* Lock bits */ -typedef enum NVM_LB_enum -{ - NVM_LB_NOLOCK_gc = (0x03<<0), /* No locks */ - NVM_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ - NVM_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ -} NVM_LB_t; - -/* Boot Loader Section Reset Vector */ -typedef enum BOOTRST_enum -{ - BOOTRST_BOOTLDR_gc = (0x00<<6), /* Boot Loader Reset */ - BOOTRST_APPLICATION_gc = (0x01<<6), /* Application Reset */ -} BOOTRST_t; - -/* 32.768kHz Timer Oscillator Pin Selection */ -typedef enum TOSCSEL_enum -{ - TOSCSEL_ALTERNATE_gc = (0x00<<5), /* TOSC1/2 on separate pins */ - TOSCSEL_XTAL_gc = (0x01<<5), /* TOSC1/2 shared with XTAL */ -} TOSCSEL_t; - -/* BOD operation */ -typedef enum BOD_enum -{ - BOD_INSAMPLEDMODE_gc = (0x01<<4), /* BOD enabled in sampled mode */ - BOD_CONTINOUSLY_gc = (0x02<<4), /* BOD enabled continuously */ - BOD_DISABLED_gc = (0x03<<4), /* BOD Disabled */ -} BOD_t; - -/* Watchdog (Window) Timeout Period */ -typedef enum WD_enum -{ - WD_8CLK_gc = (0x00<<4), /* 8 cycles (8ms @ 3.3V) */ - WD_16CLK_gc = (0x01<<4), /* 16 cycles (16ms @ 3.3V) */ - WD_32CLK_gc = (0x02<<4), /* 32 cycles (32ms @ 3.3V) */ - WD_64CLK_gc = (0x03<<4), /* 64 cycles (64ms @ 3.3V) */ - WD_128CLK_gc = (0x04<<4), /* 128 cycles (0.125s @ 3.3V) */ - WD_256CLK_gc = (0x05<<4), /* 256 cycles (0.25s @ 3.3V) */ - WD_512CLK_gc = (0x06<<4), /* 512 cycles (0.5s @ 3.3V) */ - WD_1KCLK_gc = (0x07<<4), /* 1K cycles (1s @ 3.3V) */ - WD_2KCLK_gc = (0x08<<4), /* 2K cycles (2s @ 3.3V) */ - WD_4KCLK_gc = (0x09<<4), /* 4K cycles (4s @ 3.3V) */ - WD_8KCLK_gc = (0x0A<<4), /* 8K cycles (8s @ 3.3V) */ -} WD_t; - -/* Start-up Time */ -typedef enum SUT_enum -{ - SUT_0MS_gc = (0x03<<2), /* 0 ms */ - SUT_4MS_gc = (0x01<<2), /* 4 ms */ - SUT_64MS_gc = (0x00<<2), /* 64 ms */ -} SUT_t; - -/* Brownout Detection Voltage Level */ -typedef enum BODLVL_enum -{ - BODLVL_1V6_gc = (0x07<<0), /* 1.6 V */ - BODLVL_1V8_gc = (0x06<<0), /* 1.8 V */ - BODLVL_2V0_gc = (0x05<<0), /* 2.0 V */ - BODLVL_2V2_gc = (0x04<<0), /* 2.2 V */ - BODLVL_2V4_gc = (0x03<<0), /* 2.4 V */ - BODLVL_2V6_gc = (0x02<<0), /* 2.6 V */ - BODLVL_2V8_gc = (0x01<<0), /* 2.8 V */ - BODLVL_3V0_gc = (0x00<<0), /* 3.0 V */ -} BODLVL_t; - - -/* --------------------------------------------------------------------------- -AC - Analog Comparator --------------------------------------------------------------------------- -*/ - -/* Analog Comparator */ -typedef struct AC_struct -{ - register8_t AC0CTRL; /* Analog Comparator 0 Control */ - register8_t AC1CTRL; /* Analog Comparator 1 Control */ - register8_t AC0MUXCTRL; /* Analog Comparator 0 MUX Control */ - register8_t AC1MUXCTRL; /* Analog Comparator 1 MUX Control */ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t WINCTRL; /* Window Mode Control */ - register8_t STATUS; /* Status */ -} AC_t; - -/* Interrupt mode */ -typedef enum AC_INTMODE_enum -{ - AC_INTMODE_BOTHEDGES_gc = (0x00<<6), /* Interrupt on both edges */ - AC_INTMODE_FALLING_gc = (0x02<<6), /* Interrupt on falling edge */ - AC_INTMODE_RISING_gc = (0x03<<6), /* Interrupt on rising edge */ -} AC_INTMODE_t; - -/* Interrupt level */ -typedef enum AC_INTLVL_enum -{ - AC_INTLVL_OFF_gc = (0x00<<4), /* Interrupt disabled */ - AC_INTLVL_LO_gc = (0x01<<4), /* Low level */ - AC_INTLVL_MED_gc = (0x02<<4), /* Medium level */ - AC_INTLVL_HI_gc = (0x03<<4), /* High level */ -} AC_INTLVL_t; - -/* Hysteresis mode selection */ -typedef enum AC_HYSMODE_enum -{ - AC_HYSMODE_NO_gc = (0x00<<1), /* No hysteresis */ - AC_HYSMODE_SMALL_gc = (0x01<<1), /* Small hysteresis */ - AC_HYSMODE_LARGE_gc = (0x02<<1), /* Large hysteresis */ -} AC_HYSMODE_t; - -/* Positive input multiplexer selection */ -typedef enum AC_MUXPOS_enum -{ - AC_MUXPOS_PIN0_gc = (0x00<<3), /* Pin 0 */ - AC_MUXPOS_PIN1_gc = (0x01<<3), /* Pin 1 */ - AC_MUXPOS_PIN2_gc = (0x02<<3), /* Pin 2 */ - AC_MUXPOS_PIN3_gc = (0x03<<3), /* Pin 3 */ - AC_MUXPOS_PIN4_gc = (0x04<<3), /* Pin 4 */ - AC_MUXPOS_PIN5_gc = (0x05<<3), /* Pin 5 */ - AC_MUXPOS_PIN6_gc = (0x06<<3), /* Pin 6 */ - AC_MUXPOS_DAC_gc = (0x07<<3), /* DAC output */ -} AC_MUXPOS_t; - -/* Negative input multiplexer selection */ -typedef enum AC_MUXNEG_enum -{ - AC_MUXNEG_PIN0_gc = (0x00<<0), /* Pin 0 */ - AC_MUXNEG_PIN1_gc = (0x01<<0), /* Pin 1 */ - AC_MUXNEG_PIN3_gc = (0x02<<0), /* Pin 3 */ - AC_MUXNEG_PIN5_gc = (0x03<<0), /* Pin 5 */ - AC_MUXNEG_PIN7_gc = (0x04<<0), /* Pin 7 */ - AC_MUXNEG_DAC_gc = (0x05<<0), /* DAC output */ - AC_MUXNEG_BANDGAP_gc = (0x06<<0), /* Bandgap Reference */ - AC_MUXNEG_SCALER_gc = (0x07<<0), /* Internal voltage scaler */ -} AC_MUXNEG_t; - -/* Windows interrupt mode */ -typedef enum AC_WINTMODE_enum -{ - AC_WINTMODE_ABOVE_gc = (0x00<<2), /* Interrupt on above window */ - AC_WINTMODE_INSIDE_gc = (0x01<<2), /* Interrupt on inside window */ - AC_WINTMODE_BELOW_gc = (0x02<<2), /* Interrupt on below window */ - AC_WINTMODE_OUTSIDE_gc = (0x03<<2), /* Interrupt on outside window */ -} AC_WINTMODE_t; - -/* Window interrupt level */ -typedef enum AC_WINTLVL_enum -{ - AC_WINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ - AC_WINTLVL_LO_gc = (0x01<<0), /* Low priority */ - AC_WINTLVL_MED_gc = (0x02<<0), /* Medium priority */ - AC_WINTLVL_HI_gc = (0x03<<0), /* High priority */ -} AC_WINTLVL_t; - -/* Window mode state */ -typedef enum AC_WSTATE_enum -{ - AC_WSTATE_ABOVE_gc = (0x00<<6), /* Signal above window */ - AC_WSTATE_INSIDE_gc = (0x01<<6), /* Signal inside window */ - AC_WSTATE_BELOW_gc = (0x02<<6), /* Signal below window */ -} AC_WSTATE_t; - - -/* --------------------------------------------------------------------------- -ADC - Analog/Digital Converter --------------------------------------------------------------------------- -*/ - -/* ADC Channel */ -typedef struct ADC_CH_struct -{ - register8_t CTRL; /* Control Register */ - register8_t MUXCTRL; /* MUX Control */ - register8_t INTCTRL; /* Channel Interrupt Control Register */ - register8_t INTFLAGS; /* Interrupt Flags */ - _WORDREGISTER(RES); /* Channel Result */ - register8_t SCAN; /* Input Channel Scan */ - register8_t reserved_0x07; -} ADC_CH_t; - - -/* Analog-to-Digital Converter */ -typedef struct ADC_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t REFCTRL; /* Reference Control */ - register8_t EVCTRL; /* Event Control */ - register8_t PRESCALER; /* Clock Prescaler */ - register8_t reserved_0x05; - register8_t INTFLAGS; /* Interrupt Flags */ - register8_t TEMP; /* Temporary Register */ - register8_t reserved_0x08; - register8_t reserved_0x09; - register8_t reserved_0x0A; - register8_t reserved_0x0B; - _WORDREGISTER(CAL); /* Calibration Value */ - register8_t reserved_0x0E; - register8_t reserved_0x0F; - _WORDREGISTER(CH0RES); /* Channel 0 Result */ - register8_t reserved_0x12; - register8_t reserved_0x13; - register8_t reserved_0x14; - register8_t reserved_0x15; - register8_t reserved_0x16; - register8_t reserved_0x17; - _WORDREGISTER(CMP); /* Compare Value */ - register8_t reserved_0x1A; - register8_t reserved_0x1B; - register8_t reserved_0x1C; - register8_t reserved_0x1D; - register8_t reserved_0x1E; - register8_t reserved_0x1F; - ADC_CH_t CH0; /* ADC Channel 0 */ -} ADC_t; - -/* Current Limitation */ -typedef enum ADC_CURRLIMIT_enum -{ - ADC_CURRLIMIT_NO_gc = (0x00<<5), /* No current limit, 300ksps max sampling rate */ - ADC_CURRLIMIT_LOW_gc = (0x01<<5), /* Low current limit, 250ksps max sampling rate */ - ADC_CURRLIMIT_MED_gc = (0x02<<5), /* Medium current limit, 150ksps max sampling rate */ - ADC_CURRLIMIT_HIGH_gc = (0x03<<5), /* High current limit, 50ksps max sampling rate */ -} ADC_CURRLIMIT_t; - -/* Positive input multiplexer selection */ -typedef enum ADC_CH_MUXPOS_enum -{ - ADC_CH_MUXPOS_PIN0_gc = (0x00<<3), /* Input pin 0 */ - ADC_CH_MUXPOS_PIN1_gc = (0x01<<3), /* Input pin 1 */ - ADC_CH_MUXPOS_PIN2_gc = (0x02<<3), /* Input pin 2 */ - ADC_CH_MUXPOS_PIN3_gc = (0x03<<3), /* Input pin 3 */ - ADC_CH_MUXPOS_PIN4_gc = (0x04<<3), /* Input pin 4 */ - ADC_CH_MUXPOS_PIN5_gc = (0x05<<3), /* Input pin 5 */ - ADC_CH_MUXPOS_PIN6_gc = (0x06<<3), /* Input pin 6 */ - ADC_CH_MUXPOS_PIN7_gc = (0x07<<3), /* Input pin 7 */ - ADC_CH_MUXPOS_PIN8_gc = (0x08<<3), /* Input pin 8 */ - ADC_CH_MUXPOS_PIN9_gc = (0x09<<3), /* Input pin 9 */ - ADC_CH_MUXPOS_PIN10_gc = (0x0A<<3), /* Input pin 10 */ - ADC_CH_MUXPOS_PIN11_gc = (0x0B<<3), /* Input pin 11 */ - ADC_CH_MUXPOS_PIN12_gc = (0x0C<<3), /* Input pin 12 */ - ADC_CH_MUXPOS_PIN13_gc = (0x0D<<3), /* Input pin 13 */ - ADC_CH_MUXPOS_PIN14_gc = (0x0E<<3), /* Input pin 14 */ - ADC_CH_MUXPOS_PIN15_gc = (0x0F<<3), /* Input pin 15 */ -} ADC_CH_MUXPOS_t; - -/* Internal input multiplexer selections */ -typedef enum ADC_CH_MUXINT_enum -{ - ADC_CH_MUXINT_TEMP_gc = (0x00<<3), /* Temperature Reference */ - ADC_CH_MUXINT_BANDGAP_gc = (0x01<<3), /* Bandgap Reference */ - ADC_CH_MUXINT_SCALEDVCC_gc = (0x02<<3), /* 1/10 scaled VCC */ -} ADC_CH_MUXINT_t; - -/* Negative input multiplexer selection */ -typedef enum ADC_CH_MUXNEG_enum -{ - ADC_CH_MUXNEG_PIN0_gc = (0x00<<0), /* Input pin 0 */ - ADC_CH_MUXNEG_PIN1_gc = (0x01<<0), /* Input pin 1 */ - ADC_CH_MUXNEG_PIN2_gc = (0x02<<0), /* Input pin 2 */ - ADC_CH_MUXNEG_PIN3_gc = (0x03<<0), /* Input pin 3 */ - ADC_CH_MUXNEG_PIN4_gc = (0x00<<0), /* Input pin 4 */ - ADC_CH_MUXNEG_PIN5_gc = (0x01<<0), /* Input pin 5 */ - ADC_CH_MUXNEG_PIN6_gc = (0x02<<0), /* Input pin 6 */ - ADC_CH_MUXNEG_PIN7_gc = (0x03<<0), /* Input pin 7 */ -} ADC_CH_MUXNEG_t; - -/* Input mode */ -typedef enum ADC_CH_INPUTMODE_enum -{ - ADC_CH_INPUTMODE_INTERNAL_gc = (0x00<<0), /* Internal inputs, no gain */ - ADC_CH_INPUTMODE_SINGLEENDED_gc = (0x01<<0), /* Single-ended input, no gain */ - ADC_CH_INPUTMODE_DIFF_gc = (0x02<<0), /* Differential input, no gain */ - ADC_CH_INPUTMODE_DIFFWGAIN_gc = (0x03<<0), /* Differential input, with gain */ -} ADC_CH_INPUTMODE_t; - -/* Gain factor */ -typedef enum ADC_CH_GAIN_enum -{ - ADC_CH_GAIN_1X_gc = (0x00<<2), /* 1x gain */ - ADC_CH_GAIN_2X_gc = (0x01<<2), /* 2x gain */ - ADC_CH_GAIN_4X_gc = (0x02<<2), /* 4x gain */ - ADC_CH_GAIN_8X_gc = (0x03<<2), /* 8x gain */ - ADC_CH_GAIN_16X_gc = (0x04<<2), /* 16x gain */ - ADC_CH_GAIN_32X_gc = (0x05<<2), /* 32x gain */ - ADC_CH_GAIN_64X_gc = (0x06<<2), /* 64x gain */ - ADC_CH_GAIN_DIV2_gc = (0x07<<2), /* x/2 gain */ -} ADC_CH_GAIN_t; - -/* Conversion result resolution */ -typedef enum ADC_RESOLUTION_enum -{ - ADC_RESOLUTION_12BIT_gc = (0x00<<1), /* 12-bit right-adjusted result */ - ADC_RESOLUTION_8BIT_gc = (0x02<<1), /* 8-bit right-adjusted result */ - ADC_RESOLUTION_LEFT12BIT_gc = (0x03<<1), /* 12-bit left-adjusted result */ -} ADC_RESOLUTION_t; - -/* Voltage reference selection */ -typedef enum ADC_REFSEL_enum -{ - ADC_REFSEL_INT1V_gc = (0x00<<4), /* Internal 1V */ - ADC_REFSEL_INTVCC_gc = (0x01<<4), /* Internal VCC / 1.6 */ - ADC_REFSEL_AREFA_gc = (0x02<<4), /* External reference on PORT A */ - ADC_REFSEL_AREFB_gc = (0x03<<4), /* External reference on PORT B */ - ADC_REFSEL_INTVCC2_gc = (0x04<<4), /* Internal VCC / 2 */ -} ADC_REFSEL_t; - -/* Event channel input selection */ -typedef enum ADC_EVSEL_enum -{ - ADC_EVSEL_0_gc = (0x00<<3), /* Event Channel 0 */ - ADC_EVSEL_1_gc = (0x01<<3), /* Event Channel 1 */ - ADC_EVSEL_2_gc = (0x02<<3), /* Event Channel 2 */ - ADC_EVSEL_3_gc = (0x03<<3), /* Event Channel 3 */ -} ADC_EVSEL_t; - -/* Event action selection */ -typedef enum ADC_EVACT_enum -{ - ADC_EVACT_NONE_gc = (0x00<<0), /* No event action */ - ADC_EVACT_CH0_gc = (0x01<<0), /* First event triggers channel 0 */ - ADC_EVACT_SYNCSWEEP_gc = (0x06<<0), /* The ADC is flushed and restarted for accurate timing */ -} ADC_EVACT_t; - -/* Interupt mode */ -typedef enum ADC_CH_INTMODE_enum -{ - ADC_CH_INTMODE_COMPLETE_gc = (0x00<<2), /* Interrupt on conversion complete */ - ADC_CH_INTMODE_BELOW_gc = (0x01<<2), /* Interrupt on result below compare value */ - ADC_CH_INTMODE_ABOVE_gc = (0x03<<2), /* Interrupt on result above compare value */ -} ADC_CH_INTMODE_t; - -/* Interrupt level */ -typedef enum ADC_CH_INTLVL_enum -{ - ADC_CH_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ - ADC_CH_INTLVL_LO_gc = (0x01<<0), /* Low level */ - ADC_CH_INTLVL_MED_gc = (0x02<<0), /* Medium level */ - ADC_CH_INTLVL_HI_gc = (0x03<<0), /* High level */ -} ADC_CH_INTLVL_t; - -/* Clock prescaler */ -typedef enum ADC_PRESCALER_enum -{ - ADC_PRESCALER_DIV4_gc = (0x00<<0), /* Divide clock by 4 */ - ADC_PRESCALER_DIV8_gc = (0x01<<0), /* Divide clock by 8 */ - ADC_PRESCALER_DIV16_gc = (0x02<<0), /* Divide clock by 16 */ - ADC_PRESCALER_DIV32_gc = (0x03<<0), /* Divide clock by 32 */ - ADC_PRESCALER_DIV64_gc = (0x04<<0), /* Divide clock by 64 */ - ADC_PRESCALER_DIV128_gc = (0x05<<0), /* Divide clock by 128 */ - ADC_PRESCALER_DIV256_gc = (0x06<<0), /* Divide clock by 256 */ - ADC_PRESCALER_DIV512_gc = (0x07<<0), /* Divide clock by 512 */ -} ADC_PRESCALER_t; - - -/* --------------------------------------------------------------------------- -RTC - Real-Time Counter --------------------------------------------------------------------------- -*/ - -/* Real-Time Counter */ -typedef struct RTC_struct -{ - register8_t CTRL; /* Control Register */ - register8_t STATUS; /* Status Register */ - register8_t INTCTRL; /* Interrupt Control Register */ - register8_t INTFLAGS; /* Interrupt Flags */ - register8_t TEMP; /* Temporary register */ - register8_t reserved_0x05; - register8_t reserved_0x06; - register8_t reserved_0x07; - _WORDREGISTER(CNT); /* Count Register */ - _WORDREGISTER(PER); /* Period Register */ - _WORDREGISTER(COMP); /* Compare Register */ -} RTC_t; - -/* Prescaler Factor */ -typedef enum RTC_PRESCALER_enum -{ - RTC_PRESCALER_OFF_gc = (0x00<<0), /* RTC Off */ - RTC_PRESCALER_DIV1_gc = (0x01<<0), /* RTC Clock */ - RTC_PRESCALER_DIV2_gc = (0x02<<0), /* RTC Clock / 2 */ - RTC_PRESCALER_DIV8_gc = (0x03<<0), /* RTC Clock / 8 */ - RTC_PRESCALER_DIV16_gc = (0x04<<0), /* RTC Clock / 16 */ - RTC_PRESCALER_DIV64_gc = (0x05<<0), /* RTC Clock / 64 */ - RTC_PRESCALER_DIV256_gc = (0x06<<0), /* RTC Clock / 256 */ - RTC_PRESCALER_DIV1024_gc = (0x07<<0), /* RTC Clock / 1024 */ -} RTC_PRESCALER_t; - -/* Compare Interrupt level */ -typedef enum RTC_COMPINTLVL_enum -{ - RTC_COMPINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ - RTC_COMPINTLVL_LO_gc = (0x01<<2), /* Low Level */ - RTC_COMPINTLVL_MED_gc = (0x02<<2), /* Medium Level */ - RTC_COMPINTLVL_HI_gc = (0x03<<2), /* High Level */ -} RTC_COMPINTLVL_t; - -/* Overflow Interrupt level */ -typedef enum RTC_OVFINTLVL_enum -{ - RTC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - RTC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ - RTC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ - RTC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ -} RTC_OVFINTLVL_t; - - -/* --------------------------------------------------------------------------- -TWI - Two-Wire Interface --------------------------------------------------------------------------- -*/ - -/* */ -typedef struct TWI_MASTER_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t CTRLC; /* Control Register C */ - register8_t STATUS; /* Status Register */ - register8_t BAUD; /* Baurd Rate Control Register */ - register8_t ADDR; /* Address Register */ - register8_t DATA; /* Data Register */ -} TWI_MASTER_t; - - -/* */ -typedef struct TWI_SLAVE_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t STATUS; /* Status Register */ - register8_t ADDR; /* Address Register */ - register8_t DATA; /* Data Register */ - register8_t ADDRMASK; /* Address Mask Register */ -} TWI_SLAVE_t; - - -/* Two-Wire Interface */ -typedef struct TWI_struct -{ - register8_t CTRL; /* TWI Common Control Register */ - TWI_MASTER_t MASTER; /* TWI master module */ - TWI_SLAVE_t SLAVE; /* TWI slave module */ -} TWI_t; - -/* Master Interrupt Level */ -typedef enum TWI_MASTER_INTLVL_enum -{ - TWI_MASTER_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ - TWI_MASTER_INTLVL_LO_gc = (0x01<<6), /* Low Level */ - TWI_MASTER_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ - TWI_MASTER_INTLVL_HI_gc = (0x03<<6), /* High Level */ -} TWI_MASTER_INTLVL_t; - -/* Inactive Timeout */ -typedef enum TWI_MASTER_TIMEOUT_enum -{ - TWI_MASTER_TIMEOUT_DISABLED_gc = (0x00<<2), /* Bus Timeout Disabled */ - TWI_MASTER_TIMEOUT_50US_gc = (0x01<<2), /* 50 Microseconds */ - TWI_MASTER_TIMEOUT_100US_gc = (0x02<<2), /* 100 Microseconds */ - TWI_MASTER_TIMEOUT_200US_gc = (0x03<<2), /* 200 Microseconds */ -} TWI_MASTER_TIMEOUT_t; - -/* Master Command */ -typedef enum TWI_MASTER_CMD_enum -{ - TWI_MASTER_CMD_NOACT_gc = (0x00<<0), /* No Action */ - TWI_MASTER_CMD_REPSTART_gc = (0x01<<0), /* Issue Repeated Start Condition */ - TWI_MASTER_CMD_RECVTRANS_gc = (0x02<<0), /* Receive or Transmit Data */ - TWI_MASTER_CMD_STOP_gc = (0x03<<0), /* Issue Stop Condition */ -} TWI_MASTER_CMD_t; - -/* Master Bus State */ -typedef enum TWI_MASTER_BUSSTATE_enum -{ - TWI_MASTER_BUSSTATE_UNKNOWN_gc = (0x00<<0), /* Unknown Bus State */ - TWI_MASTER_BUSSTATE_IDLE_gc = (0x01<<0), /* Bus is Idle */ - TWI_MASTER_BUSSTATE_OWNER_gc = (0x02<<0), /* This Module Controls The Bus */ - TWI_MASTER_BUSSTATE_BUSY_gc = (0x03<<0), /* The Bus is Busy */ -} TWI_MASTER_BUSSTATE_t; - -/* Slave Interrupt Level */ -typedef enum TWI_SLAVE_INTLVL_enum -{ - TWI_SLAVE_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ - TWI_SLAVE_INTLVL_LO_gc = (0x01<<6), /* Low Level */ - TWI_SLAVE_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ - TWI_SLAVE_INTLVL_HI_gc = (0x03<<6), /* High Level */ -} TWI_SLAVE_INTLVL_t; - -/* Slave Command */ -typedef enum TWI_SLAVE_CMD_enum -{ - TWI_SLAVE_CMD_NOACT_gc = (0x00<<0), /* No Action */ - TWI_SLAVE_CMD_COMPTRANS_gc = (0x02<<0), /* Used To Complete a Transaction */ - TWI_SLAVE_CMD_RESPONSE_gc = (0x03<<0), /* Used in Response to Address/Data Interrupt */ -} TWI_SLAVE_CMD_t; - -/* SDA hold time */ -typedef enum SDA_HOLD_TIME_enum -{ - SDA_HOLD_TIME_OFF_gc = (0x00<<1), /* SDA hold time off */ - SDA_HOLD_TIME_50NS_gc = (0x01<<1), /* Typical 50ns hold time */ - SDA_HOLD_TIME_300NS_gc = (0x02<<1), /* Typical 300ns hold time */ - SDA_HOLD_TIME_400NS_gc = (0x03<<1), /* Typical 400ns hold time */ -} SDA_HOLD_TIME_t; - - -/* --------------------------------------------------------------------------- -PORT - Port Configuration --------------------------------------------------------------------------- -*/ - -/* I/O port Configuration */ -typedef struct PORTCFG_struct -{ - register8_t MPCMASK; /* Multi-pin Configuration Mask */ - register8_t reserved_0x01; - register8_t VPCTRLA; /* Virtual Port Control Register A */ - register8_t VPCTRLB; /* Virtual Port Control Register B */ - register8_t CLKEVOUT; /* Clock and Event Out Register */ -} PORTCFG_t; - - -/* Virtual Port */ -typedef struct VPORT_struct -{ - register8_t DIR; /* I/O Port Data Direction */ - register8_t OUT; /* I/O Port Output */ - register8_t IN; /* I/O Port Input */ - register8_t INTFLAGS; /* Interrupt Flag Register */ -} VPORT_t; - - -/* I/O Ports */ -typedef struct PORT_struct -{ - register8_t DIR; /* I/O Port Data Direction */ - register8_t DIRSET; /* I/O Port Data Direction Set */ - register8_t DIRCLR; /* I/O Port Data Direction Clear */ - register8_t DIRTGL; /* I/O Port Data Direction Toggle */ - register8_t OUT; /* I/O Port Output */ - register8_t OUTSET; /* I/O Port Output Set */ - register8_t OUTCLR; /* I/O Port Output Clear */ - register8_t OUTTGL; /* I/O Port Output Toggle */ - register8_t IN; /* I/O port Input */ - register8_t INTCTRL; /* Interrupt Control Register */ - register8_t INT0MASK; /* Port Interrupt 0 Mask */ - register8_t INT1MASK; /* Port Interrupt 1 Mask */ - register8_t INTFLAGS; /* Interrupt Flag Register */ - register8_t reserved_0x0D; - register8_t REMAP; /* Pin Remap Register (available for PORTC to PORTF only) */ - register8_t reserved_0x0F; - register8_t PIN0CTRL; /* Pin 0 Control Register */ - register8_t PIN1CTRL; /* Pin 1 Control Register */ - register8_t PIN2CTRL; /* Pin 2 Control Register */ - register8_t PIN3CTRL; /* Pin 3 Control Register */ - register8_t PIN4CTRL; /* Pin 4 Control Register */ - register8_t PIN5CTRL; /* Pin 5 Control Register */ - register8_t PIN6CTRL; /* Pin 6 Control Register */ - register8_t PIN7CTRL; /* Pin 7 Control Register */ -} PORT_t; - -/* Virtual Port 0 Mapping */ -typedef enum PORTCFG_VP0MAP_enum -{ - PORTCFG_VP0MAP_PORTA_gc = (0x00<<0), /* Mapped To PORTA */ - PORTCFG_VP0MAP_PORTB_gc = (0x01<<0), /* Mapped To PORTB */ - PORTCFG_VP0MAP_PORTC_gc = (0x02<<0), /* Mapped To PORTC */ - PORTCFG_VP0MAP_PORTD_gc = (0x03<<0), /* Mapped To PORTD */ - PORTCFG_VP0MAP_PORTE_gc = (0x04<<0), /* Mapped To PORTE */ - PORTCFG_VP0MAP_PORTF_gc = (0x05<<0), /* Mapped To PORTF */ - PORTCFG_VP0MAP_PORTG_gc = (0x06<<0), /* Mapped To PORTG */ - PORTCFG_VP0MAP_PORTH_gc = (0x07<<0), /* Mapped To PORTH */ - PORTCFG_VP0MAP_PORTJ_gc = (0x08<<0), /* Mapped To PORTJ */ - PORTCFG_VP0MAP_PORTK_gc = (0x09<<0), /* Mapped To PORTK */ - PORTCFG_VP0MAP_PORTL_gc = (0x0A<<0), /* Mapped To PORTL */ - PORTCFG_VP0MAP_PORTM_gc = (0x0B<<0), /* Mapped To PORTM */ - PORTCFG_VP0MAP_PORTN_gc = (0x0C<<0), /* Mapped To PORTN */ - PORTCFG_VP0MAP_PORTP_gc = (0x0D<<0), /* Mapped To PORTP */ - PORTCFG_VP0MAP_PORTQ_gc = (0x0E<<0), /* Mapped To PORTQ */ - PORTCFG_VP0MAP_PORTR_gc = (0x0F<<0), /* Mapped To PORTR */ -} PORTCFG_VP0MAP_t; - -/* Virtual Port 1 Mapping */ -typedef enum PORTCFG_VP1MAP_enum -{ - PORTCFG_VP1MAP_PORTA_gc = (0x00<<4), /* Mapped To PORTA */ - PORTCFG_VP1MAP_PORTB_gc = (0x01<<4), /* Mapped To PORTB */ - PORTCFG_VP1MAP_PORTC_gc = (0x02<<4), /* Mapped To PORTC */ - PORTCFG_VP1MAP_PORTD_gc = (0x03<<4), /* Mapped To PORTD */ - PORTCFG_VP1MAP_PORTE_gc = (0x04<<4), /* Mapped To PORTE */ - PORTCFG_VP1MAP_PORTF_gc = (0x05<<4), /* Mapped To PORTF */ - PORTCFG_VP1MAP_PORTG_gc = (0x06<<4), /* Mapped To PORTG */ - PORTCFG_VP1MAP_PORTH_gc = (0x07<<4), /* Mapped To PORTH */ - PORTCFG_VP1MAP_PORTJ_gc = (0x08<<4), /* Mapped To PORTJ */ - PORTCFG_VP1MAP_PORTK_gc = (0x09<<4), /* Mapped To PORTK */ - PORTCFG_VP1MAP_PORTL_gc = (0x0A<<4), /* Mapped To PORTL */ - PORTCFG_VP1MAP_PORTM_gc = (0x0B<<4), /* Mapped To PORTM */ - PORTCFG_VP1MAP_PORTN_gc = (0x0C<<4), /* Mapped To PORTN */ - PORTCFG_VP1MAP_PORTP_gc = (0x0D<<4), /* Mapped To PORTP */ - PORTCFG_VP1MAP_PORTQ_gc = (0x0E<<4), /* Mapped To PORTQ */ - PORTCFG_VP1MAP_PORTR_gc = (0x0F<<4), /* Mapped To PORTR */ -} PORTCFG_VP1MAP_t; - -/* Virtual Port 2 Mapping */ -typedef enum PORTCFG_VP2MAP_enum -{ - PORTCFG_VP2MAP_PORTA_gc = (0x00<<0), /* Mapped To PORTA */ - PORTCFG_VP2MAP_PORTB_gc = (0x01<<0), /* Mapped To PORTB */ - PORTCFG_VP2MAP_PORTC_gc = (0x02<<0), /* Mapped To PORTC */ - PORTCFG_VP2MAP_PORTD_gc = (0x03<<0), /* Mapped To PORTD */ - PORTCFG_VP2MAP_PORTE_gc = (0x04<<0), /* Mapped To PORTE */ - PORTCFG_VP2MAP_PORTF_gc = (0x05<<0), /* Mapped To PORTF */ - PORTCFG_VP2MAP_PORTG_gc = (0x06<<0), /* Mapped To PORTG */ - PORTCFG_VP2MAP_PORTH_gc = (0x07<<0), /* Mapped To PORTH */ - PORTCFG_VP2MAP_PORTJ_gc = (0x08<<0), /* Mapped To PORTJ */ - PORTCFG_VP2MAP_PORTK_gc = (0x09<<0), /* Mapped To PORTK */ - PORTCFG_VP2MAP_PORTL_gc = (0x0A<<0), /* Mapped To PORTL */ - PORTCFG_VP2MAP_PORTM_gc = (0x0B<<0), /* Mapped To PORTM */ - PORTCFG_VP2MAP_PORTN_gc = (0x0C<<0), /* Mapped To PORTN */ - PORTCFG_VP2MAP_PORTP_gc = (0x0D<<0), /* Mapped To PORTP */ - PORTCFG_VP2MAP_PORTQ_gc = (0x0E<<0), /* Mapped To PORTQ */ - PORTCFG_VP2MAP_PORTR_gc = (0x0F<<0), /* Mapped To PORTR */ -} PORTCFG_VP2MAP_t; - -/* Virtual Port 3 Mapping */ -typedef enum PORTCFG_VP3MAP_enum -{ - PORTCFG_VP3MAP_PORTA_gc = (0x00<<4), /* Mapped To PORTA */ - PORTCFG_VP3MAP_PORTB_gc = (0x01<<4), /* Mapped To PORTB */ - PORTCFG_VP3MAP_PORTC_gc = (0x02<<4), /* Mapped To PORTC */ - PORTCFG_VP3MAP_PORTD_gc = (0x03<<4), /* Mapped To PORTD */ - PORTCFG_VP3MAP_PORTE_gc = (0x04<<4), /* Mapped To PORTE */ - PORTCFG_VP3MAP_PORTF_gc = (0x05<<4), /* Mapped To PORTF */ - PORTCFG_VP3MAP_PORTG_gc = (0x06<<4), /* Mapped To PORTG */ - PORTCFG_VP3MAP_PORTH_gc = (0x07<<4), /* Mapped To PORTH */ - PORTCFG_VP3MAP_PORTJ_gc = (0x08<<4), /* Mapped To PORTJ */ - PORTCFG_VP3MAP_PORTK_gc = (0x09<<4), /* Mapped To PORTK */ - PORTCFG_VP3MAP_PORTL_gc = (0x0A<<4), /* Mapped To PORTL */ - PORTCFG_VP3MAP_PORTM_gc = (0x0B<<4), /* Mapped To PORTM */ - PORTCFG_VP3MAP_PORTN_gc = (0x0C<<4), /* Mapped To PORTN */ - PORTCFG_VP3MAP_PORTP_gc = (0x0D<<4), /* Mapped To PORTP */ - PORTCFG_VP3MAP_PORTQ_gc = (0x0E<<4), /* Mapped To PORTQ */ - PORTCFG_VP3MAP_PORTR_gc = (0x0F<<4), /* Mapped To PORTR */ -} PORTCFG_VP3MAP_t; - -/* Clock Output Port */ -typedef enum PORTCFG_CLKOUT_enum -{ - PORTCFG_CLKOUT_OFF_gc = (0x00<<0), /* Clock Output Disabled */ - PORTCFG_CLKOUT_PC7_gc = (0x01<<0), /* Clock Output on Port C pin 7 */ - PORTCFG_CLKOUT_PD7_gc = (0x02<<0), /* Clock Output on Port D pin 7 */ - PORTCFG_CLKOUT_PE7_gc = (0x03<<0), /* Clock Output on Port E pin 7 */ -} PORTCFG_CLKOUT_t; - -/* Event Output Port */ -typedef enum PORTCFG_EVOUT_enum -{ - PORTCFG_EVOUT_OFF_gc = (0x00<<4), /* Event Output Disabled */ - PORTCFG_EVOUT_PC7_gc = (0x01<<4), /* Event Channel 7 Output on Port C pin 7 */ - PORTCFG_EVOUT_PD7_gc = (0x02<<4), /* Event Channel 7 Output on Port D pin 7 */ - PORTCFG_EVOUT_PE7_gc = (0x03<<4), /* Event Channel 7 Output on Port E pin 7 */ -} PORTCFG_EVOUT_t; - -/* Port Interrupt 0 Level */ -typedef enum PORT_INT0LVL_enum -{ - PORT_INT0LVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - PORT_INT0LVL_LO_gc = (0x01<<0), /* Low Level */ - PORT_INT0LVL_MED_gc = (0x02<<0), /* Medium Level */ - PORT_INT0LVL_HI_gc = (0x03<<0), /* High Level */ -} PORT_INT0LVL_t; - -/* Port Interrupt 1 Level */ -typedef enum PORT_INT1LVL_enum -{ - PORT_INT1LVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ - PORT_INT1LVL_LO_gc = (0x01<<2), /* Low Level */ - PORT_INT1LVL_MED_gc = (0x02<<2), /* Medium Level */ - PORT_INT1LVL_HI_gc = (0x03<<2), /* High Level */ -} PORT_INT1LVL_t; - -/* Output/Pull Configuration */ -typedef enum PORT_OPC_enum -{ - PORT_OPC_TOTEM_gc = (0x00<<3), /* Totempole */ - PORT_OPC_BUSKEEPER_gc = (0x01<<3), /* Totempole w/ Bus keeper on Input and Output */ - PORT_OPC_PULLDOWN_gc = (0x02<<3), /* Totempole w/ Pull-down on Input */ - PORT_OPC_PULLUP_gc = (0x03<<3), /* Totempole w/ Pull-up on Input */ - PORT_OPC_WIREDOR_gc = (0x04<<3), /* Wired OR */ - PORT_OPC_WIREDAND_gc = (0x05<<3), /* Wired AND */ - PORT_OPC_WIREDORPULL_gc = (0x06<<3), /* Wired OR w/ Pull-down */ - PORT_OPC_WIREDANDPULL_gc = (0x07<<3), /* Wired AND w/ Pull-up */ -} PORT_OPC_t; - -/* Input/Sense Configuration */ -typedef enum PORT_ISC_enum -{ - PORT_ISC_BOTHEDGES_gc = (0x00<<0), /* Sense Both Edges */ - PORT_ISC_RISING_gc = (0x01<<0), /* Sense Rising Edge */ - PORT_ISC_FALLING_gc = (0x02<<0), /* Sense Falling Edge */ - PORT_ISC_LEVEL_gc = (0x03<<0), /* Sense Level (Transparent For Events) */ - PORT_ISC_INPUT_DISABLE_gc = (0x07<<0), /* Disable Digital Input Buffer */ -} PORT_ISC_t; - - -/* --------------------------------------------------------------------------- -TC - 16-bit Timer/Counter With PWM --------------------------------------------------------------------------- -*/ - -/* 16-bit Timer/Counter 0 */ -typedef struct TC0_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t CTRLC; /* Control register C */ - register8_t CTRLD; /* Control Register D */ - register8_t CTRLE; /* Control Register E */ - register8_t reserved_0x05; - register8_t INTCTRLA; /* Interrupt Control Register A */ - register8_t INTCTRLB; /* Interrupt Control Register B */ - register8_t CTRLFCLR; /* Control Register F Clear */ - register8_t CTRLFSET; /* Control Register F Set */ - register8_t CTRLGCLR; /* Control Register G Clear */ - register8_t CTRLGSET; /* Control Register G Set */ - register8_t INTFLAGS; /* Interrupt Flag Register */ - register8_t reserved_0x0D; - register8_t reserved_0x0E; - register8_t TEMP; /* Temporary Register For 16-bit Access */ - register8_t reserved_0x10; - register8_t reserved_0x11; - register8_t reserved_0x12; - register8_t reserved_0x13; - register8_t reserved_0x14; - register8_t reserved_0x15; - register8_t reserved_0x16; - register8_t reserved_0x17; - register8_t reserved_0x18; - register8_t reserved_0x19; - register8_t reserved_0x1A; - register8_t reserved_0x1B; - register8_t reserved_0x1C; - register8_t reserved_0x1D; - register8_t reserved_0x1E; - register8_t reserved_0x1F; - _WORDREGISTER(CNT); /* Count */ - register8_t reserved_0x22; - register8_t reserved_0x23; - register8_t reserved_0x24; - register8_t reserved_0x25; - _WORDREGISTER(PER); /* Period */ - _WORDREGISTER(CCA); /* Compare or Capture A */ - _WORDREGISTER(CCB); /* Compare or Capture B */ - _WORDREGISTER(CCC); /* Compare or Capture C */ - _WORDREGISTER(CCD); /* Compare or Capture D */ - register8_t reserved_0x30; - register8_t reserved_0x31; - register8_t reserved_0x32; - register8_t reserved_0x33; - register8_t reserved_0x34; - register8_t reserved_0x35; - _WORDREGISTER(PERBUF); /* Period Buffer */ - _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ - _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ - _WORDREGISTER(CCCBUF); /* Compare Or Capture C Buffer */ - _WORDREGISTER(CCDBUF); /* Compare Or Capture D Buffer */ -} TC0_t; - - -/* 16-bit Timer/Counter 1 */ -typedef struct TC1_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t CTRLC; /* Control register C */ - register8_t CTRLD; /* Control Register D */ - register8_t CTRLE; /* Control Register E */ - register8_t reserved_0x05; - register8_t INTCTRLA; /* Interrupt Control Register A */ - register8_t INTCTRLB; /* Interrupt Control Register B */ - register8_t CTRLFCLR; /* Control Register F Clear */ - register8_t CTRLFSET; /* Control Register F Set */ - register8_t CTRLGCLR; /* Control Register G Clear */ - register8_t CTRLGSET; /* Control Register G Set */ - register8_t INTFLAGS; /* Interrupt Flag Register */ - register8_t reserved_0x0D; - register8_t reserved_0x0E; - register8_t TEMP; /* Temporary Register For 16-bit Access */ - register8_t reserved_0x10; - register8_t reserved_0x11; - register8_t reserved_0x12; - register8_t reserved_0x13; - register8_t reserved_0x14; - register8_t reserved_0x15; - register8_t reserved_0x16; - register8_t reserved_0x17; - register8_t reserved_0x18; - register8_t reserved_0x19; - register8_t reserved_0x1A; - register8_t reserved_0x1B; - register8_t reserved_0x1C; - register8_t reserved_0x1D; - register8_t reserved_0x1E; - register8_t reserved_0x1F; - _WORDREGISTER(CNT); /* Count */ - register8_t reserved_0x22; - register8_t reserved_0x23; - register8_t reserved_0x24; - register8_t reserved_0x25; - _WORDREGISTER(PER); /* Period */ - _WORDREGISTER(CCA); /* Compare or Capture A */ - _WORDREGISTER(CCB); /* Compare or Capture B */ - register8_t reserved_0x2C; - register8_t reserved_0x2D; - register8_t reserved_0x2E; - register8_t reserved_0x2F; - register8_t reserved_0x30; - register8_t reserved_0x31; - register8_t reserved_0x32; - register8_t reserved_0x33; - register8_t reserved_0x34; - register8_t reserved_0x35; - _WORDREGISTER(PERBUF); /* Period Buffer */ - _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ - _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ -} TC1_t; - - -/* Advanced Waveform Extension */ -typedef struct AWEX_struct -{ - register8_t CTRL; /* Control Register */ - register8_t reserved_0x01; - register8_t FDEMASK; /* Fault Detection Event Mask */ - register8_t FDCTRL; /* Fault Detection Control Register */ - register8_t STATUS; /* Status Register */ - register8_t reserved_0x05; - register8_t DTBOTH; /* Dead Time Both Sides */ - register8_t DTBOTHBUF; /* Dead Time Both Sides Buffer */ - register8_t DTLS; /* Dead Time Low Side */ - register8_t DTHS; /* Dead Time High Side */ - register8_t DTLSBUF; /* Dead Time Low Side Buffer */ - register8_t DTHSBUF; /* Dead Time High Side Buffer */ - register8_t OUTOVEN; /* Output Override Enable */ -} AWEX_t; - - -/* High-Resolution Extension */ -typedef struct HIRES_struct -{ - register8_t CTRLA; /* Control Register */ -} HIRES_t; - -/* Clock Selection */ -typedef enum TC_CLKSEL_enum -{ - TC_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */ - TC_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */ - TC_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */ - TC_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */ - TC_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */ - TC_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */ - TC_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */ - TC_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */ - TC_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */ - TC_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */ - TC_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */ - TC_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */ - TC_CLKSEL_EVCH4_gc = (0x0C<<0), /* Event Channel 4 */ - TC_CLKSEL_EVCH5_gc = (0x0D<<0), /* Event Channel 5 */ - TC_CLKSEL_EVCH6_gc = (0x0E<<0), /* Event Channel 6 */ - TC_CLKSEL_EVCH7_gc = (0x0F<<0), /* Event Channel 7 */ -} TC_CLKSEL_t; - -/* Waveform Generation Mode */ -typedef enum TC_WGMODE_enum -{ - TC_WGMODE_NORMAL_gc = (0x00<<0), /* Normal Mode */ - TC_WGMODE_FRQ_gc = (0x01<<0), /* Frequency Generation Mode */ - TC_WGMODE_SS_gc = (0x03<<0), /* Single Slope */ - TC_WGMODE_DS_T_gc = (0x05<<0), /* Dual Slope, Update on TOP */ - TC_WGMODE_DS_TB_gc = (0x06<<0), /* Dual Slope, Update on TOP and BOTTOM */ - TC_WGMODE_DS_B_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */ -} TC_WGMODE_t; - -/* Event Action */ -typedef enum TC_EVACT_enum -{ - TC_EVACT_OFF_gc = (0x00<<5), /* No Event Action */ - TC_EVACT_CAPT_gc = (0x01<<5), /* Input Capture */ - TC_EVACT_UPDOWN_gc = (0x02<<5), /* Externally Controlled Up/Down Count */ - TC_EVACT_QDEC_gc = (0x03<<5), /* Quadrature Decode */ - TC_EVACT_RESTART_gc = (0x04<<5), /* Restart */ - TC_EVACT_FRQ_gc = (0x05<<5), /* Frequency Capture */ - TC_EVACT_PW_gc = (0x06<<5), /* Pulse-width Capture */ -} TC_EVACT_t; - -/* Event Selection */ -typedef enum TC_EVSEL_enum -{ - TC_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ - TC_EVSEL_CH0_gc = (0x08<<0), /* Event Channel 0 */ - TC_EVSEL_CH1_gc = (0x09<<0), /* Event Channel 1 */ - TC_EVSEL_CH2_gc = (0x0A<<0), /* Event Channel 2 */ - TC_EVSEL_CH3_gc = (0x0B<<0), /* Event Channel 3 */ - TC_EVSEL_CH4_gc = (0x0C<<0), /* Event Channel 4 */ - TC_EVSEL_CH5_gc = (0x0D<<0), /* Event Channel 5 */ - TC_EVSEL_CH6_gc = (0x0E<<0), /* Event Channel 6 */ - TC_EVSEL_CH7_gc = (0x0F<<0), /* Event Channel 7 */ -} TC_EVSEL_t; - -/* Error Interrupt Level */ -typedef enum TC_ERRINTLVL_enum -{ - TC_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ - TC_ERRINTLVL_LO_gc = (0x01<<2), /* Low Level */ - TC_ERRINTLVL_MED_gc = (0x02<<2), /* Medium Level */ - TC_ERRINTLVL_HI_gc = (0x03<<2), /* High Level */ -} TC_ERRINTLVL_t; - -/* Overflow Interrupt Level */ -typedef enum TC_OVFINTLVL_enum -{ - TC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - TC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ - TC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ - TC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ -} TC_OVFINTLVL_t; - -/* Compare or Capture D Interrupt Level */ -typedef enum TC_CCDINTLVL_enum -{ - TC_CCDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ - TC_CCDINTLVL_LO_gc = (0x01<<6), /* Low Level */ - TC_CCDINTLVL_MED_gc = (0x02<<6), /* Medium Level */ - TC_CCDINTLVL_HI_gc = (0x03<<6), /* High Level */ -} TC_CCDINTLVL_t; - -/* Compare or Capture C Interrupt Level */ -typedef enum TC_CCCINTLVL_enum -{ - TC_CCCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ - TC_CCCINTLVL_LO_gc = (0x01<<4), /* Low Level */ - TC_CCCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ - TC_CCCINTLVL_HI_gc = (0x03<<4), /* High Level */ -} TC_CCCINTLVL_t; - -/* Compare or Capture B Interrupt Level */ -typedef enum TC_CCBINTLVL_enum -{ - TC_CCBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ - TC_CCBINTLVL_LO_gc = (0x01<<2), /* Low Level */ - TC_CCBINTLVL_MED_gc = (0x02<<2), /* Medium Level */ - TC_CCBINTLVL_HI_gc = (0x03<<2), /* High Level */ -} TC_CCBINTLVL_t; - -/* Compare or Capture A Interrupt Level */ -typedef enum TC_CCAINTLVL_enum -{ - TC_CCAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - TC_CCAINTLVL_LO_gc = (0x01<<0), /* Low Level */ - TC_CCAINTLVL_MED_gc = (0x02<<0), /* Medium Level */ - TC_CCAINTLVL_HI_gc = (0x03<<0), /* High Level */ -} TC_CCAINTLVL_t; - -/* Timer/Counter Command */ -typedef enum TC_CMD_enum -{ - TC_CMD_NONE_gc = (0x00<<2), /* No Command */ - TC_CMD_UPDATE_gc = (0x01<<2), /* Force Update */ - TC_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ - TC_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ -} TC_CMD_t; - -/* Fault Detect Action */ -typedef enum AWEX_FDACT_enum -{ - AWEX_FDACT_NONE_gc = (0x00<<0), /* No Fault Protection */ - AWEX_FDACT_CLEAROE_gc = (0x01<<0), /* Clear Output Enable Bits */ - AWEX_FDACT_CLEARDIR_gc = (0x03<<0), /* Clear I/O Port Direction Bits */ -} AWEX_FDACT_t; - -/* High Resolution Enable */ -typedef enum HIRES_HREN_enum -{ - HIRES_HREN_NONE_gc = (0x00<<0), /* No Fault Protection */ - HIRES_HREN_TC0_gc = (0x01<<0), /* Enable High Resolution on Timer/Counter 0 */ - HIRES_HREN_TC1_gc = (0x02<<0), /* Enable High Resolution on Timer/Counter 1 */ - HIRES_HREN_BOTH_gc = (0x03<<0), /* Enable High Resolution both Timer/Counters */ -} HIRES_HREN_t; - - -/* --------------------------------------------------------------------------- -USART - Universal Asynchronous Receiver-Transmitter --------------------------------------------------------------------------- -*/ - -/* Universal Synchronous/Asynchronous Receiver/Transmitter */ -typedef struct USART_struct -{ - register8_t DATA; /* Data Register */ - register8_t STATUS; /* Status Register */ - register8_t reserved_0x02; - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t CTRLC; /* Control Register C */ - register8_t BAUDCTRLA; /* Baud Rate Control Register A */ - register8_t BAUDCTRLB; /* Baud Rate Control Register B */ -} USART_t; - -/* Receive Complete Interrupt level */ -typedef enum USART_RXCINTLVL_enum -{ - USART_RXCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ - USART_RXCINTLVL_LO_gc = (0x01<<4), /* Low Level */ - USART_RXCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ - USART_RXCINTLVL_HI_gc = (0x03<<4), /* High Level */ -} USART_RXCINTLVL_t; - -/* Transmit Complete Interrupt level */ -typedef enum USART_TXCINTLVL_enum -{ - USART_TXCINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ - USART_TXCINTLVL_LO_gc = (0x01<<2), /* Low Level */ - USART_TXCINTLVL_MED_gc = (0x02<<2), /* Medium Level */ - USART_TXCINTLVL_HI_gc = (0x03<<2), /* High Level */ -} USART_TXCINTLVL_t; - -/* Data Register Empty Interrupt level */ -typedef enum USART_DREINTLVL_enum -{ - USART_DREINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - USART_DREINTLVL_LO_gc = (0x01<<0), /* Low Level */ - USART_DREINTLVL_MED_gc = (0x02<<0), /* Medium Level */ - USART_DREINTLVL_HI_gc = (0x03<<0), /* High Level */ -} USART_DREINTLVL_t; - -/* Character Size */ -typedef enum USART_CHSIZE_enum -{ - USART_CHSIZE_5BIT_gc = (0x00<<0), /* Character size: 5 bit */ - USART_CHSIZE_6BIT_gc = (0x01<<0), /* Character size: 6 bit */ - USART_CHSIZE_7BIT_gc = (0x02<<0), /* Character size: 7 bit */ - USART_CHSIZE_8BIT_gc = (0x03<<0), /* Character size: 8 bit */ - USART_CHSIZE_9BIT_gc = (0x07<<0), /* Character size: 9 bit */ -} USART_CHSIZE_t; - -/* Communication Mode */ -typedef enum USART_CMODE_enum -{ - USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6), /* Asynchronous Mode */ - USART_CMODE_SYNCHRONOUS_gc = (0x01<<6), /* Synchronous Mode */ - USART_CMODE_IRDA_gc = (0x02<<6), /* IrDA Mode */ - USART_CMODE_MSPI_gc = (0x03<<6), /* Master SPI Mode */ -} USART_CMODE_t; - -/* Parity Mode */ -typedef enum USART_PMODE_enum -{ - USART_PMODE_DISABLED_gc = (0x00<<4), /* No Parity */ - USART_PMODE_EVEN_gc = (0x02<<4), /* Even Parity */ - USART_PMODE_ODD_gc = (0x03<<4), /* Odd Parity */ -} USART_PMODE_t; - - -/* --------------------------------------------------------------------------- -SPI - Serial Peripheral Interface --------------------------------------------------------------------------- -*/ - -/* Serial Peripheral Interface */ -typedef struct SPI_struct -{ - register8_t CTRL; /* Control Register */ - register8_t INTCTRL; /* Interrupt Control Register */ - register8_t STATUS; /* Status Register */ - register8_t DATA; /* Data Register */ -} SPI_t; - -/* SPI Mode */ -typedef enum SPI_MODE_enum -{ - SPI_MODE_0_gc = (0x00<<2), /* SPI Mode 0 */ - SPI_MODE_1_gc = (0x01<<2), /* SPI Mode 1 */ - SPI_MODE_2_gc = (0x02<<2), /* SPI Mode 2 */ - SPI_MODE_3_gc = (0x03<<2), /* SPI Mode 3 */ -} SPI_MODE_t; - -/* Prescaler setting */ -typedef enum SPI_PRESCALER_enum -{ - SPI_PRESCALER_DIV4_gc = (0x00<<0), /* System Clock / 4 */ - SPI_PRESCALER_DIV16_gc = (0x01<<0), /* System Clock / 16 */ - SPI_PRESCALER_DIV64_gc = (0x02<<0), /* System Clock / 64 */ - SPI_PRESCALER_DIV128_gc = (0x03<<0), /* System Clock / 128 */ -} SPI_PRESCALER_t; - -/* Interrupt level */ -typedef enum SPI_INTLVL_enum -{ - SPI_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - SPI_INTLVL_LO_gc = (0x01<<0), /* Low Level */ - SPI_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ - SPI_INTLVL_HI_gc = (0x03<<0), /* High Level */ -} SPI_INTLVL_t; - - -/* --------------------------------------------------------------------------- -IRCOM - IR Communication Module --------------------------------------------------------------------------- -*/ - -/* IR Communication Module */ -typedef struct IRCOM_struct -{ - register8_t CTRL; /* Control Register */ - register8_t TXPLCTRL; /* IrDA Transmitter Pulse Length Control Register */ - register8_t RXPLCTRL; /* IrDA Receiver Pulse Length Control Register */ -} IRCOM_t; - -/* Event channel selection */ -typedef enum IRDA_EVSEL_enum -{ - IRDA_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ - IRDA_EVSEL_0_gc = (0x08<<0), /* Event Channel 0 */ - IRDA_EVSEL_1_gc = (0x09<<0), /* Event Channel 1 */ - IRDA_EVSEL_2_gc = (0x0A<<0), /* Event Channel 2 */ - IRDA_EVSEL_3_gc = (0x0B<<0), /* Event Channel 3 */ - IRDA_EVSEL_4_gc = (0x0C<<0), /* Event Channel 4 */ - IRDA_EVSEL_5_gc = (0x0D<<0), /* Event Channel 5 */ - IRDA_EVSEL_6_gc = (0x0E<<0), /* Event Channel 6 */ - IRDA_EVSEL_7_gc = (0x0F<<0), /* Event Channel 7 */ -} IRDA_EVSEL_t; - -/* -========================================================================== -IO Module Instances. Mapped to memory. -========================================================================== -*/ - -#define VPORT0 (*(VPORT_t *) 0x0010) /* Virtual Port */ -#define VPORT1 (*(VPORT_t *) 0x0014) /* Virtual Port */ -#define VPORT2 (*(VPORT_t *) 0x0018) /* Virtual Port */ -#define VPORT3 (*(VPORT_t *) 0x001C) /* Virtual Port */ -#define OCD (*(OCD_t *) 0x002E) /* On-Chip Debug System */ -#define CLK (*(CLK_t *) 0x0040) /* Clock System */ -#define SLEEP (*(SLEEP_t *) 0x0048) /* Sleep Controller */ -#define OSC (*(OSC_t *) 0x0050) /* Oscillator */ -#define DFLLRC32M (*(DFLL_t *) 0x0060) /* DFLL */ -#define DFLLRC2M (*(DFLL_t *) 0x0068) /* DFLL */ -#define PR (*(PR_t *) 0x0070) /* Power Reduction */ -#define RST (*(RST_t *) 0x0078) /* Reset */ -#define WDT (*(WDT_t *) 0x0080) /* Watch-Dog Timer */ -#define MCU (*(MCU_t *) 0x0090) /* MCU Control */ -#define PMIC (*(PMIC_t *) 0x00A0) /* Programmable Multi-level Interrupt Controller */ -#define PORTCFG (*(PORTCFG_t *) 0x00B0) /* I/O port Configuration */ -#define CRC (*(CRC_t *) 0x00D0) /* Cyclic Redundancy Checker */ -#define EVSYS (*(EVSYS_t *) 0x0180) /* Event System */ -#define NVM (*(NVM_t *) 0x01C0) /* Non-volatile Memory Controller */ -#define ADCA (*(ADC_t *) 0x0200) /* Analog-to-Digital Converter */ -#define ACA (*(AC_t *) 0x0380) /* Analog Comparator */ -#define RTC (*(RTC_t *) 0x0400) /* Real-Time Counter */ -#define TWIC (*(TWI_t *) 0x0480) /* Two-Wire Interface */ -#define TWIE (*(TWI_t *) 0x04A0) /* Two-Wire Interface */ -#define PORTA (*(PORT_t *) 0x0600) /* I/O Ports */ -#define PORTB (*(PORT_t *) 0x0620) /* I/O Ports */ -#define PORTC (*(PORT_t *) 0x0640) /* I/O Ports */ -#define PORTD (*(PORT_t *) 0x0660) /* I/O Ports */ -#define PORTE (*(PORT_t *) 0x0680) /* I/O Ports */ -#define PORTF (*(PORT_t *) 0x06A0) /* I/O Ports */ -#define PORTR (*(PORT_t *) 0x07E0) /* I/O Ports */ -#define TCC0 (*(TC0_t *) 0x0800) /* 16-bit Timer/Counter 0 */ -#define TCC1 (*(TC1_t *) 0x0840) /* 16-bit Timer/Counter 1 */ -#define AWEXC (*(AWEX_t *) 0x0880) /* Advanced Waveform Extension */ -#define HIRESC (*(HIRES_t *) 0x0890) /* High-Resolution Extension */ -#define USARTC0 (*(USART_t *) 0x08A0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ -#define SPIC (*(SPI_t *) 0x08C0) /* Serial Peripheral Interface */ -#define IRCOM (*(IRCOM_t *) 0x08F8) /* IR Communication Module */ -#define TCD0 (*(TC0_t *) 0x0900) /* 16-bit Timer/Counter 0 */ -#define USARTD0 (*(USART_t *) 0x09A0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ -#define SPID (*(SPI_t *) 0x09C0) /* Serial Peripheral Interface */ -#define TCE0 (*(TC0_t *) 0x0A00) /* 16-bit Timer/Counter 0 */ -#define AWEXE (*(AWEX_t *) 0x0A80) /* Advanced Waveform Extension */ -#define USARTE0 (*(USART_t *) 0x0AA0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ -#define SPIE (*(SPI_t *) 0x0AC0) /* Serial Peripheral Interface */ -#define TCF0 (*(TC0_t *) 0x0B00) /* 16-bit Timer/Counter 0 */ - - -#endif /* !defined (__ASSEMBLER__) */ - - -/* ========== Flattened fully qualified IO register names ========== */ - -/* GPIO - General Purpose IO Registers */ -#define GPIO_GPIOR0 _SFR_MEM8(0x0000) -#define GPIO_GPIOR1 _SFR_MEM8(0x0001) -#define GPIO_GPIOR2 _SFR_MEM8(0x0002) -#define GPIO_GPIOR3 _SFR_MEM8(0x0003) - -/* Deprecated */ -#define GPIO_GPIO0 _SFR_MEM8(0x0000) -#define GPIO_GPIO1 _SFR_MEM8(0x0001) -#define GPIO_GPIO2 _SFR_MEM8(0x0002) -#define GPIO_GPIO3 _SFR_MEM8(0x0003) - -/* NVM_FUSES - Fuses */ -#define FUSE_FUSEBYTE1 _SFR_MEM8(0x0001) -#define FUSE_FUSEBYTE2 _SFR_MEM8(0x0002) -#define FUSE_FUSEBYTE4 _SFR_MEM8(0x0004) -#define FUSE_FUSEBYTE5 _SFR_MEM8(0x0005) - -/* NVM_LOCKBITS - Lock Bits */ -#define LOCKBIT_LOCKBITS _SFR_MEM8(0x0000) - -/* NVM_PROD_SIGNATURES - Production Signatures */ -#define PRODSIGNATURES_RCOSC2M _SFR_MEM8(0x0000) -#define PRODSIGNATURES_RCOSC32K _SFR_MEM8(0x0002) -#define PRODSIGNATURES_RCOSC32M _SFR_MEM8(0x0003) -#define PRODSIGNATURES_LOTNUM0 _SFR_MEM8(0x0008) -#define PRODSIGNATURES_LOTNUM1 _SFR_MEM8(0x0009) -#define PRODSIGNATURES_LOTNUM2 _SFR_MEM8(0x000A) -#define PRODSIGNATURES_LOTNUM3 _SFR_MEM8(0x000B) -#define PRODSIGNATURES_LOTNUM4 _SFR_MEM8(0x000C) -#define PRODSIGNATURES_LOTNUM5 _SFR_MEM8(0x000D) -#define PRODSIGNATURES_WAFNUM _SFR_MEM8(0x0010) -#define PRODSIGNATURES_COORDX0 _SFR_MEM8(0x0012) -#define PRODSIGNATURES_COORDX1 _SFR_MEM8(0x0013) -#define PRODSIGNATURES_COORDY0 _SFR_MEM8(0x0014) -#define PRODSIGNATURES_COORDY1 _SFR_MEM8(0x0015) -#define PRODSIGNATURES_ADCACAL0 _SFR_MEM8(0x0020) -#define PRODSIGNATURES_ADCACAL1 _SFR_MEM8(0x0021) -#define PRODSIGNATURES_ADCBCAL0 _SFR_MEM8(0x0024) -#define PRODSIGNATURES_ADCBCAL1 _SFR_MEM8(0x0025) -#define PRODSIGNATURES_TEMPSENSE0 _SFR_MEM8(0x002E) -#define PRODSIGNATURES_TEMPSENSE1 _SFR_MEM8(0x002F) - -/* VPORT - Virtual Port */ -#define VPORT0_DIR _SFR_MEM8(0x0010) -#define VPORT0_OUT _SFR_MEM8(0x0011) -#define VPORT0_IN _SFR_MEM8(0x0012) -#define VPORT0_INTFLAGS _SFR_MEM8(0x0013) - -/* VPORT - Virtual Port */ -#define VPORT1_DIR _SFR_MEM8(0x0014) -#define VPORT1_OUT _SFR_MEM8(0x0015) -#define VPORT1_IN _SFR_MEM8(0x0016) -#define VPORT1_INTFLAGS _SFR_MEM8(0x0017) - -/* VPORT - Virtual Port */ -#define VPORT2_DIR _SFR_MEM8(0x0018) -#define VPORT2_OUT _SFR_MEM8(0x0019) -#define VPORT2_IN _SFR_MEM8(0x001A) -#define VPORT2_INTFLAGS _SFR_MEM8(0x001B) - -/* VPORT - Virtual Port */ -#define VPORT3_DIR _SFR_MEM8(0x001C) -#define VPORT3_OUT _SFR_MEM8(0x001D) -#define VPORT3_IN _SFR_MEM8(0x001E) -#define VPORT3_INTFLAGS _SFR_MEM8(0x001F) - -/* OCD - On-Chip Debug System */ -#define OCD_OCDR0 _SFR_MEM8(0x002E) -#define OCD_OCDR1 _SFR_MEM8(0x002F) - -/* CPU - CPU registers */ -#define CPU_CCP _SFR_MEM8(0x0034) -#define CPU_RAMPD _SFR_MEM8(0x0038) -#define CPU_RAMPX _SFR_MEM8(0x0039) -#define CPU_RAMPY _SFR_MEM8(0x003A) -#define CPU_RAMPZ _SFR_MEM8(0x003B) -#define CPU_EIND _SFR_MEM8(0x003C) -#define CPU_SPL _SFR_MEM8(0x003D) -#define CPU_SPH _SFR_MEM8(0x003E) -#define CPU_SREG _SFR_MEM8(0x003F) - -/* CLK - Clock System */ -#define CLK_CTRL _SFR_MEM8(0x0040) -#define CLK_PSCTRL _SFR_MEM8(0x0041) -#define CLK_LOCK _SFR_MEM8(0x0042) -#define CLK_RTCCTRL _SFR_MEM8(0x0043) - -/* SLEEP - Sleep Controller */ -#define SLEEP_CTRL _SFR_MEM8(0x0048) - -/* OSC - Oscillator */ -#define OSC_CTRL _SFR_MEM8(0x0050) -#define OSC_STATUS _SFR_MEM8(0x0051) -#define OSC_XOSCCTRL _SFR_MEM8(0x0052) -#define OSC_XOSCFAIL _SFR_MEM8(0x0053) -#define OSC_RC32KCAL _SFR_MEM8(0x0054) -#define OSC_PLLCTRL _SFR_MEM8(0x0055) -#define OSC_DFLLCTRL _SFR_MEM8(0x0056) - -/* DFLL - DFLL */ -#define DFLLRC32M_CTRL _SFR_MEM8(0x0060) -#define DFLLRC32M_CALA _SFR_MEM8(0x0062) -#define DFLLRC32M_CALB _SFR_MEM8(0x0063) -#define DFLLRC32M_COMP0 _SFR_MEM8(0x0064) -#define DFLLRC32M_COMP1 _SFR_MEM8(0x0065) -#define DFLLRC32M_COMP2 _SFR_MEM8(0x0066) - -/* DFLL - DFLL */ -#define DFLLRC2M_CTRL _SFR_MEM8(0x0068) -#define DFLLRC2M_CALA _SFR_MEM8(0x006A) -#define DFLLRC2M_CALB _SFR_MEM8(0x006B) -#define DFLLRC2M_COMP0 _SFR_MEM8(0x006C) -#define DFLLRC2M_COMP1 _SFR_MEM8(0x006D) -#define DFLLRC2M_COMP2 _SFR_MEM8(0x006E) - -/* PR - Power Reduction */ -#define PR_PRGEN _SFR_MEM8(0x0070) -#define PR_PRPA _SFR_MEM8(0x0071) -#define PR_PRPC _SFR_MEM8(0x0073) -#define PR_PRPD _SFR_MEM8(0x0074) -#define PR_PRPE _SFR_MEM8(0x0075) -#define PR_PRPF _SFR_MEM8(0x0076) - -/* RST - Reset */ -#define RST_STATUS _SFR_MEM8(0x0078) -#define RST_CTRL _SFR_MEM8(0x0079) - -/* WDT - Watch-Dog Timer */ -#define WDT_CTRL _SFR_MEM8(0x0080) -#define WDT_WINCTRL _SFR_MEM8(0x0081) -#define WDT_STATUS _SFR_MEM8(0x0082) - -/* MCU - MCU Control */ -#define MCU_DEVID0 _SFR_MEM8(0x0090) -#define MCU_DEVID1 _SFR_MEM8(0x0091) -#define MCU_DEVID2 _SFR_MEM8(0x0092) -#define MCU_REVID _SFR_MEM8(0x0093) -#define MCU_JTAGUID _SFR_MEM8(0x0094) -#define MCU_MCUCR _SFR_MEM8(0x0096) -#define MCU_EVSYSLOCK _SFR_MEM8(0x0098) -#define MCU_AWEXLOCK _SFR_MEM8(0x0099) - -/* PMIC - Programmable Multi-level Interrupt Controller */ -#define PMIC_STATUS _SFR_MEM8(0x00A0) -#define PMIC_INTPRI _SFR_MEM8(0x00A1) -#define PMIC_CTRL _SFR_MEM8(0x00A2) - -/* PORTCFG - I/O port Configuration */ -#define PORTCFG_MPCMASK _SFR_MEM8(0x00B0) -#define PORTCFG_VPCTRLA _SFR_MEM8(0x00B2) -#define PORTCFG_VPCTRLB _SFR_MEM8(0x00B3) -#define PORTCFG_CLKEVOUT _SFR_MEM8(0x00B4) - -/* CRC - Cyclic Redundancy Checker */ -#define CRC_CTRL _SFR_MEM8(0x00D0) -#define CRC_STATUS _SFR_MEM8(0x00D1) -#define CRC_DATAIN _SFR_MEM8(0x00D3) -#define CRC_CHECKSUM0 _SFR_MEM8(0x00D4) -#define CRC_CHECKSUM1 _SFR_MEM8(0x00D5) -#define CRC_CHECKSUM2 _SFR_MEM8(0x00D6) -#define CRC_CHECKSUM3 _SFR_MEM8(0x00D7) - -/* EVSYS - Event System */ -#define EVSYS_CH0MUX _SFR_MEM8(0x0180) -#define EVSYS_CH1MUX _SFR_MEM8(0x0181) -#define EVSYS_CH2MUX _SFR_MEM8(0x0182) -#define EVSYS_CH3MUX _SFR_MEM8(0x0183) -#define EVSYS_CH0CTRL _SFR_MEM8(0x0188) -#define EVSYS_CH1CTRL _SFR_MEM8(0x0189) -#define EVSYS_CH2CTRL _SFR_MEM8(0x018A) -#define EVSYS_CH3CTRL _SFR_MEM8(0x018B) -#define EVSYS_STROBE _SFR_MEM8(0x0190) -#define EVSYS_DATA _SFR_MEM8(0x0191) - -/* NVM - Non-volatile Memory Controller */ -#define NVM_ADDR0 _SFR_MEM8(0x01C0) -#define NVM_ADDR1 _SFR_MEM8(0x01C1) -#define NVM_ADDR2 _SFR_MEM8(0x01C2) -#define NVM_DATA0 _SFR_MEM8(0x01C4) -#define NVM_DATA1 _SFR_MEM8(0x01C5) -#define NVM_DATA2 _SFR_MEM8(0x01C6) -#define NVM_CMD _SFR_MEM8(0x01CA) -#define NVM_CTRLA _SFR_MEM8(0x01CB) -#define NVM_CTRLB _SFR_MEM8(0x01CC) -#define NVM_INTCTRL _SFR_MEM8(0x01CD) -#define NVM_STATUS _SFR_MEM8(0x01CF) -#define NVM_LOCKBITS _SFR_MEM8(0x01D0) - -/* ADC - Analog-to-Digital Converter */ -#define ADCA_CTRLA _SFR_MEM8(0x0200) -#define ADCA_CTRLB _SFR_MEM8(0x0201) -#define ADCA_REFCTRL _SFR_MEM8(0x0202) -#define ADCA_EVCTRL _SFR_MEM8(0x0203) -#define ADCA_PRESCALER _SFR_MEM8(0x0204) -#define ADCA_INTFLAGS _SFR_MEM8(0x0206) -#define ADCA_TEMP _SFR_MEM8(0x0207) -#define ADCA_CAL _SFR_MEM16(0x020C) -#define ADCA_CH0RES _SFR_MEM16(0x0210) -#define ADCA_CMP _SFR_MEM16(0x0218) -#define ADCA_CH0_CTRL _SFR_MEM8(0x0220) -#define ADCA_CH0_MUXCTRL _SFR_MEM8(0x0221) -#define ADCA_CH0_INTCTRL _SFR_MEM8(0x0222) -#define ADCA_CH0_INTFLAGS _SFR_MEM8(0x0223) -#define ADCA_CH0_RES _SFR_MEM16(0x0224) -#define ADCA_CH0_SCAN _SFR_MEM8(0x0226) - -/* AC - Analog Comparator */ -#define ACA_AC0CTRL _SFR_MEM8(0x0380) -#define ACA_AC1CTRL _SFR_MEM8(0x0381) -#define ACA_AC0MUXCTRL _SFR_MEM8(0x0382) -#define ACA_AC1MUXCTRL _SFR_MEM8(0x0383) -#define ACA_CTRLA _SFR_MEM8(0x0384) -#define ACA_CTRLB _SFR_MEM8(0x0385) -#define ACA_WINCTRL _SFR_MEM8(0x0386) -#define ACA_STATUS _SFR_MEM8(0x0387) - -/* RTC - Real-Time Counter */ -#define RTC_CTRL _SFR_MEM8(0x0400) -#define RTC_STATUS _SFR_MEM8(0x0401) -#define RTC_INTCTRL _SFR_MEM8(0x0402) -#define RTC_INTFLAGS _SFR_MEM8(0x0403) -#define RTC_TEMP _SFR_MEM8(0x0404) -#define RTC_CNT _SFR_MEM16(0x0408) -#define RTC_PER _SFR_MEM16(0x040A) -#define RTC_COMP _SFR_MEM16(0x040C) - -/* TWI - Two-Wire Interface */ -#define TWIC_CTRL _SFR_MEM8(0x0480) -#define TWIC_MASTER_CTRLA _SFR_MEM8(0x0481) -#define TWIC_MASTER_CTRLB _SFR_MEM8(0x0482) -#define TWIC_MASTER_CTRLC _SFR_MEM8(0x0483) -#define TWIC_MASTER_STATUS _SFR_MEM8(0x0484) -#define TWIC_MASTER_BAUD _SFR_MEM8(0x0485) -#define TWIC_MASTER_ADDR _SFR_MEM8(0x0486) -#define TWIC_MASTER_DATA _SFR_MEM8(0x0487) -#define TWIC_SLAVE_CTRLA _SFR_MEM8(0x0488) -#define TWIC_SLAVE_CTRLB _SFR_MEM8(0x0489) -#define TWIC_SLAVE_STATUS _SFR_MEM8(0x048A) -#define TWIC_SLAVE_ADDR _SFR_MEM8(0x048B) -#define TWIC_SLAVE_DATA _SFR_MEM8(0x048C) -#define TWIC_SLAVE_ADDRMASK _SFR_MEM8(0x048D) - -/* TWI - Two-Wire Interface */ -#define TWIE_CTRL _SFR_MEM8(0x04A0) -#define TWIE_MASTER_CTRLA _SFR_MEM8(0x04A1) -#define TWIE_MASTER_CTRLB _SFR_MEM8(0x04A2) -#define TWIE_MASTER_CTRLC _SFR_MEM8(0x04A3) -#define TWIE_MASTER_STATUS _SFR_MEM8(0x04A4) -#define TWIE_MASTER_BAUD _SFR_MEM8(0x04A5) -#define TWIE_MASTER_ADDR _SFR_MEM8(0x04A6) -#define TWIE_MASTER_DATA _SFR_MEM8(0x04A7) -#define TWIE_SLAVE_CTRLA _SFR_MEM8(0x04A8) -#define TWIE_SLAVE_CTRLB _SFR_MEM8(0x04A9) -#define TWIE_SLAVE_STATUS _SFR_MEM8(0x04AA) -#define TWIE_SLAVE_ADDR _SFR_MEM8(0x04AB) -#define TWIE_SLAVE_DATA _SFR_MEM8(0x04AC) -#define TWIE_SLAVE_ADDRMASK _SFR_MEM8(0x04AD) - -/* PORT - I/O Ports */ -#define PORTA_DIR _SFR_MEM8(0x0600) -#define PORTA_DIRSET _SFR_MEM8(0x0601) -#define PORTA_DIRCLR _SFR_MEM8(0x0602) -#define PORTA_DIRTGL _SFR_MEM8(0x0603) -#define PORTA_OUT _SFR_MEM8(0x0604) -#define PORTA_OUTSET _SFR_MEM8(0x0605) -#define PORTA_OUTCLR _SFR_MEM8(0x0606) -#define PORTA_OUTTGL _SFR_MEM8(0x0607) -#define PORTA_IN _SFR_MEM8(0x0608) -#define PORTA_INTCTRL _SFR_MEM8(0x0609) -#define PORTA_INT0MASK _SFR_MEM8(0x060A) -#define PORTA_INT1MASK _SFR_MEM8(0x060B) -#define PORTA_INTFLAGS _SFR_MEM8(0x060C) -#define PORTA_REMAP _SFR_MEM8(0x060E) -#define PORTA_PIN0CTRL _SFR_MEM8(0x0610) -#define PORTA_PIN1CTRL _SFR_MEM8(0x0611) -#define PORTA_PIN2CTRL _SFR_MEM8(0x0612) -#define PORTA_PIN3CTRL _SFR_MEM8(0x0613) -#define PORTA_PIN4CTRL _SFR_MEM8(0x0614) -#define PORTA_PIN5CTRL _SFR_MEM8(0x0615) -#define PORTA_PIN6CTRL _SFR_MEM8(0x0616) -#define PORTA_PIN7CTRL _SFR_MEM8(0x0617) - -/* PORT - I/O Ports */ -#define PORTB_DIR _SFR_MEM8(0x0620) -#define PORTB_DIRSET _SFR_MEM8(0x0621) -#define PORTB_DIRCLR _SFR_MEM8(0x0622) -#define PORTB_DIRTGL _SFR_MEM8(0x0623) -#define PORTB_OUT _SFR_MEM8(0x0624) -#define PORTB_OUTSET _SFR_MEM8(0x0625) -#define PORTB_OUTCLR _SFR_MEM8(0x0626) -#define PORTB_OUTTGL _SFR_MEM8(0x0627) -#define PORTB_IN _SFR_MEM8(0x0628) -#define PORTB_INTCTRL _SFR_MEM8(0x0629) -#define PORTB_INT0MASK _SFR_MEM8(0x062A) -#define PORTB_INT1MASK _SFR_MEM8(0x062B) -#define PORTB_INTFLAGS _SFR_MEM8(0x062C) -#define PORTB_REMAP _SFR_MEM8(0x062E) -#define PORTB_PIN0CTRL _SFR_MEM8(0x0630) -#define PORTB_PIN1CTRL _SFR_MEM8(0x0631) -#define PORTB_PIN2CTRL _SFR_MEM8(0x0632) -#define PORTB_PIN3CTRL _SFR_MEM8(0x0633) -#define PORTB_PIN4CTRL _SFR_MEM8(0x0634) -#define PORTB_PIN5CTRL _SFR_MEM8(0x0635) -#define PORTB_PIN6CTRL _SFR_MEM8(0x0636) -#define PORTB_PIN7CTRL _SFR_MEM8(0x0637) - -/* PORT - I/O Ports */ -#define PORTC_DIR _SFR_MEM8(0x0640) -#define PORTC_DIRSET _SFR_MEM8(0x0641) -#define PORTC_DIRCLR _SFR_MEM8(0x0642) -#define PORTC_DIRTGL _SFR_MEM8(0x0643) -#define PORTC_OUT _SFR_MEM8(0x0644) -#define PORTC_OUTSET _SFR_MEM8(0x0645) -#define PORTC_OUTCLR _SFR_MEM8(0x0646) -#define PORTC_OUTTGL _SFR_MEM8(0x0647) -#define PORTC_IN _SFR_MEM8(0x0648) -#define PORTC_INTCTRL _SFR_MEM8(0x0649) -#define PORTC_INT0MASK _SFR_MEM8(0x064A) -#define PORTC_INT1MASK _SFR_MEM8(0x064B) -#define PORTC_INTFLAGS _SFR_MEM8(0x064C) -#define PORTC_REMAP _SFR_MEM8(0x064E) -#define PORTC_PIN0CTRL _SFR_MEM8(0x0650) -#define PORTC_PIN1CTRL _SFR_MEM8(0x0651) -#define PORTC_PIN2CTRL _SFR_MEM8(0x0652) -#define PORTC_PIN3CTRL _SFR_MEM8(0x0653) -#define PORTC_PIN4CTRL _SFR_MEM8(0x0654) -#define PORTC_PIN5CTRL _SFR_MEM8(0x0655) -#define PORTC_PIN6CTRL _SFR_MEM8(0x0656) -#define PORTC_PIN7CTRL _SFR_MEM8(0x0657) - -/* PORT - I/O Ports */ -#define PORTD_DIR _SFR_MEM8(0x0660) -#define PORTD_DIRSET _SFR_MEM8(0x0661) -#define PORTD_DIRCLR _SFR_MEM8(0x0662) -#define PORTD_DIRTGL _SFR_MEM8(0x0663) -#define PORTD_OUT _SFR_MEM8(0x0664) -#define PORTD_OUTSET _SFR_MEM8(0x0665) -#define PORTD_OUTCLR _SFR_MEM8(0x0666) -#define PORTD_OUTTGL _SFR_MEM8(0x0667) -#define PORTD_IN _SFR_MEM8(0x0668) -#define PORTD_INTCTRL _SFR_MEM8(0x0669) -#define PORTD_INT0MASK _SFR_MEM8(0x066A) -#define PORTD_INT1MASK _SFR_MEM8(0x066B) -#define PORTD_INTFLAGS _SFR_MEM8(0x066C) -#define PORTD_REMAP _SFR_MEM8(0x066E) -#define PORTD_PIN0CTRL _SFR_MEM8(0x0670) -#define PORTD_PIN1CTRL _SFR_MEM8(0x0671) -#define PORTD_PIN2CTRL _SFR_MEM8(0x0672) -#define PORTD_PIN3CTRL _SFR_MEM8(0x0673) -#define PORTD_PIN4CTRL _SFR_MEM8(0x0674) -#define PORTD_PIN5CTRL _SFR_MEM8(0x0675) -#define PORTD_PIN6CTRL _SFR_MEM8(0x0676) -#define PORTD_PIN7CTRL _SFR_MEM8(0x0677) - -/* PORT - I/O Ports */ -#define PORTE_DIR _SFR_MEM8(0x0680) -#define PORTE_DIRSET _SFR_MEM8(0x0681) -#define PORTE_DIRCLR _SFR_MEM8(0x0682) -#define PORTE_DIRTGL _SFR_MEM8(0x0683) -#define PORTE_OUT _SFR_MEM8(0x0684) -#define PORTE_OUTSET _SFR_MEM8(0x0685) -#define PORTE_OUTCLR _SFR_MEM8(0x0686) -#define PORTE_OUTTGL _SFR_MEM8(0x0687) -#define PORTE_IN _SFR_MEM8(0x0688) -#define PORTE_INTCTRL _SFR_MEM8(0x0689) -#define PORTE_INT0MASK _SFR_MEM8(0x068A) -#define PORTE_INT1MASK _SFR_MEM8(0x068B) -#define PORTE_INTFLAGS _SFR_MEM8(0x068C) -#define PORTE_REMAP _SFR_MEM8(0x068E) -#define PORTE_PIN0CTRL _SFR_MEM8(0x0690) -#define PORTE_PIN1CTRL _SFR_MEM8(0x0691) -#define PORTE_PIN2CTRL _SFR_MEM8(0x0692) -#define PORTE_PIN3CTRL _SFR_MEM8(0x0693) -#define PORTE_PIN4CTRL _SFR_MEM8(0x0694) -#define PORTE_PIN5CTRL _SFR_MEM8(0x0695) -#define PORTE_PIN6CTRL _SFR_MEM8(0x0696) -#define PORTE_PIN7CTRL _SFR_MEM8(0x0697) - -/* PORT - I/O Ports */ -#define PORTF_DIR _SFR_MEM8(0x06A0) -#define PORTF_DIRSET _SFR_MEM8(0x06A1) -#define PORTF_DIRCLR _SFR_MEM8(0x06A2) -#define PORTF_DIRTGL _SFR_MEM8(0x06A3) -#define PORTF_OUT _SFR_MEM8(0x06A4) -#define PORTF_OUTSET _SFR_MEM8(0x06A5) -#define PORTF_OUTCLR _SFR_MEM8(0x06A6) -#define PORTF_OUTTGL _SFR_MEM8(0x06A7) -#define PORTF_IN _SFR_MEM8(0x06A8) -#define PORTF_INTCTRL _SFR_MEM8(0x06A9) -#define PORTF_INT0MASK _SFR_MEM8(0x06AA) -#define PORTF_INT1MASK _SFR_MEM8(0x06AB) -#define PORTF_INTFLAGS _SFR_MEM8(0x06AC) -#define PORTF_REMAP _SFR_MEM8(0x06AE) -#define PORTF_PIN0CTRL _SFR_MEM8(0x06B0) -#define PORTF_PIN1CTRL _SFR_MEM8(0x06B1) -#define PORTF_PIN2CTRL _SFR_MEM8(0x06B2) -#define PORTF_PIN3CTRL _SFR_MEM8(0x06B3) -#define PORTF_PIN4CTRL _SFR_MEM8(0x06B4) -#define PORTF_PIN5CTRL _SFR_MEM8(0x06B5) -#define PORTF_PIN6CTRL _SFR_MEM8(0x06B6) -#define PORTF_PIN7CTRL _SFR_MEM8(0x06B7) - -/* PORT - I/O Ports */ -#define PORTR_DIR _SFR_MEM8(0x07E0) -#define PORTR_DIRSET _SFR_MEM8(0x07E1) -#define PORTR_DIRCLR _SFR_MEM8(0x07E2) -#define PORTR_DIRTGL _SFR_MEM8(0x07E3) -#define PORTR_OUT _SFR_MEM8(0x07E4) -#define PORTR_OUTSET _SFR_MEM8(0x07E5) -#define PORTR_OUTCLR _SFR_MEM8(0x07E6) -#define PORTR_OUTTGL _SFR_MEM8(0x07E7) -#define PORTR_IN _SFR_MEM8(0x07E8) -#define PORTR_INTCTRL _SFR_MEM8(0x07E9) -#define PORTR_INT0MASK _SFR_MEM8(0x07EA) -#define PORTR_INT1MASK _SFR_MEM8(0x07EB) -#define PORTR_INTFLAGS _SFR_MEM8(0x07EC) -#define PORTR_REMAP _SFR_MEM8(0x07EE) -#define PORTR_PIN0CTRL _SFR_MEM8(0x07F0) -#define PORTR_PIN1CTRL _SFR_MEM8(0x07F1) -#define PORTR_PIN2CTRL _SFR_MEM8(0x07F2) -#define PORTR_PIN3CTRL _SFR_MEM8(0x07F3) -#define PORTR_PIN4CTRL _SFR_MEM8(0x07F4) -#define PORTR_PIN5CTRL _SFR_MEM8(0x07F5) -#define PORTR_PIN6CTRL _SFR_MEM8(0x07F6) -#define PORTR_PIN7CTRL _SFR_MEM8(0x07F7) - -/* TC0 - 16-bit Timer/Counter 0 */ -#define TCC0_CTRLA _SFR_MEM8(0x0800) -#define TCC0_CTRLB _SFR_MEM8(0x0801) -#define TCC0_CTRLC _SFR_MEM8(0x0802) -#define TCC0_CTRLD _SFR_MEM8(0x0803) -#define TCC0_CTRLE _SFR_MEM8(0x0804) -#define TCC0_INTCTRLA _SFR_MEM8(0x0806) -#define TCC0_INTCTRLB _SFR_MEM8(0x0807) -#define TCC0_CTRLFCLR _SFR_MEM8(0x0808) -#define TCC0_CTRLFSET _SFR_MEM8(0x0809) -#define TCC0_CTRLGCLR _SFR_MEM8(0x080A) -#define TCC0_CTRLGSET _SFR_MEM8(0x080B) -#define TCC0_INTFLAGS _SFR_MEM8(0x080C) -#define TCC0_TEMP _SFR_MEM8(0x080F) -#define TCC0_CNT _SFR_MEM16(0x0820) -#define TCC0_PER _SFR_MEM16(0x0826) -#define TCC0_CCA _SFR_MEM16(0x0828) -#define TCC0_CCB _SFR_MEM16(0x082A) -#define TCC0_CCC _SFR_MEM16(0x082C) -#define TCC0_CCD _SFR_MEM16(0x082E) -#define TCC0_PERBUF _SFR_MEM16(0x0836) -#define TCC0_CCABUF _SFR_MEM16(0x0838) -#define TCC0_CCBBUF _SFR_MEM16(0x083A) -#define TCC0_CCCBUF _SFR_MEM16(0x083C) -#define TCC0_CCDBUF _SFR_MEM16(0x083E) - -/* TC1 - 16-bit Timer/Counter 1 */ -#define TCC1_CTRLA _SFR_MEM8(0x0840) -#define TCC1_CTRLB _SFR_MEM8(0x0841) -#define TCC1_CTRLC _SFR_MEM8(0x0842) -#define TCC1_CTRLD _SFR_MEM8(0x0843) -#define TCC1_CTRLE _SFR_MEM8(0x0844) -#define TCC1_INTCTRLA _SFR_MEM8(0x0846) -#define TCC1_INTCTRLB _SFR_MEM8(0x0847) -#define TCC1_CTRLFCLR _SFR_MEM8(0x0848) -#define TCC1_CTRLFSET _SFR_MEM8(0x0849) -#define TCC1_CTRLGCLR _SFR_MEM8(0x084A) -#define TCC1_CTRLGSET _SFR_MEM8(0x084B) -#define TCC1_INTFLAGS _SFR_MEM8(0x084C) -#define TCC1_TEMP _SFR_MEM8(0x084F) -#define TCC1_CNT _SFR_MEM16(0x0860) -#define TCC1_PER _SFR_MEM16(0x0866) -#define TCC1_CCA _SFR_MEM16(0x0868) -#define TCC1_CCB _SFR_MEM16(0x086A) -#define TCC1_PERBUF _SFR_MEM16(0x0876) -#define TCC1_CCABUF _SFR_MEM16(0x0878) -#define TCC1_CCBBUF _SFR_MEM16(0x087A) - -/* AWEX - Advanced Waveform Extension */ -#define AWEXC_CTRL _SFR_MEM8(0x0880) -#define AWEXC_FDEMASK _SFR_MEM8(0x0882) -#define AWEXC_FDCTRL _SFR_MEM8(0x0883) -#define AWEXC_STATUS _SFR_MEM8(0x0884) -#define AWEXC_DTBOTH _SFR_MEM8(0x0886) -#define AWEXC_DTBOTHBUF _SFR_MEM8(0x0887) -#define AWEXC_DTLS _SFR_MEM8(0x0888) -#define AWEXC_DTHS _SFR_MEM8(0x0889) -#define AWEXC_DTLSBUF _SFR_MEM8(0x088A) -#define AWEXC_DTHSBUF _SFR_MEM8(0x088B) -#define AWEXC_OUTOVEN _SFR_MEM8(0x088C) - -/* HIRES - High-Resolution Extension */ -#define HIRESC_CTRLA _SFR_MEM8(0x0890) - -/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ -#define USARTC0_DATA _SFR_MEM8(0x08A0) -#define USARTC0_STATUS _SFR_MEM8(0x08A1) -#define USARTC0_CTRLA _SFR_MEM8(0x08A3) -#define USARTC0_CTRLB _SFR_MEM8(0x08A4) -#define USARTC0_CTRLC _SFR_MEM8(0x08A5) -#define USARTC0_BAUDCTRLA _SFR_MEM8(0x08A6) -#define USARTC0_BAUDCTRLB _SFR_MEM8(0x08A7) - -/* SPI - Serial Peripheral Interface */ -#define SPIC_CTRL _SFR_MEM8(0x08C0) -#define SPIC_INTCTRL _SFR_MEM8(0x08C1) -#define SPIC_STATUS _SFR_MEM8(0x08C2) -#define SPIC_DATA _SFR_MEM8(0x08C3) - -/* IRCOM - IR Communication Module */ -#define IRCOM_CTRL _SFR_MEM8(0x08F8) -#define IRCOM_TXPLCTRL _SFR_MEM8(0x08F9) -#define IRCOM_RXPLCTRL _SFR_MEM8(0x08FA) - -/* TC0 - 16-bit Timer/Counter 0 */ -#define TCD0_CTRLA _SFR_MEM8(0x0900) -#define TCD0_CTRLB _SFR_MEM8(0x0901) -#define TCD0_CTRLC _SFR_MEM8(0x0902) -#define TCD0_CTRLD _SFR_MEM8(0x0903) -#define TCD0_CTRLE _SFR_MEM8(0x0904) -#define TCD0_INTCTRLA _SFR_MEM8(0x0906) -#define TCD0_INTCTRLB _SFR_MEM8(0x0907) -#define TCD0_CTRLFCLR _SFR_MEM8(0x0908) -#define TCD0_CTRLFSET _SFR_MEM8(0x0909) -#define TCD0_CTRLGCLR _SFR_MEM8(0x090A) -#define TCD0_CTRLGSET _SFR_MEM8(0x090B) -#define TCD0_INTFLAGS _SFR_MEM8(0x090C) -#define TCD0_TEMP _SFR_MEM8(0x090F) -#define TCD0_CNT _SFR_MEM16(0x0920) -#define TCD0_PER _SFR_MEM16(0x0926) -#define TCD0_CCA _SFR_MEM16(0x0928) -#define TCD0_CCB _SFR_MEM16(0x092A) -#define TCD0_CCC _SFR_MEM16(0x092C) -#define TCD0_CCD _SFR_MEM16(0x092E) -#define TCD0_PERBUF _SFR_MEM16(0x0936) -#define TCD0_CCABUF _SFR_MEM16(0x0938) -#define TCD0_CCBBUF _SFR_MEM16(0x093A) -#define TCD0_CCCBUF _SFR_MEM16(0x093C) -#define TCD0_CCDBUF _SFR_MEM16(0x093E) - -/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ -#define USARTD0_DATA _SFR_MEM8(0x09A0) -#define USARTD0_STATUS _SFR_MEM8(0x09A1) -#define USARTD0_CTRLA _SFR_MEM8(0x09A3) -#define USARTD0_CTRLB _SFR_MEM8(0x09A4) -#define USARTD0_CTRLC _SFR_MEM8(0x09A5) -#define USARTD0_BAUDCTRLA _SFR_MEM8(0x09A6) -#define USARTD0_BAUDCTRLB _SFR_MEM8(0x09A7) - -/* SPI - Serial Peripheral Interface */ -#define SPID_CTRL _SFR_MEM8(0x09C0) -#define SPID_INTCTRL _SFR_MEM8(0x09C1) -#define SPID_STATUS _SFR_MEM8(0x09C2) -#define SPID_DATA _SFR_MEM8(0x09C3) - -/* TC0 - 16-bit Timer/Counter 0 */ -#define TCE0_CTRLA _SFR_MEM8(0x0A00) -#define TCE0_CTRLB _SFR_MEM8(0x0A01) -#define TCE0_CTRLC _SFR_MEM8(0x0A02) -#define TCE0_CTRLD _SFR_MEM8(0x0A03) -#define TCE0_CTRLE _SFR_MEM8(0x0A04) -#define TCE0_INTCTRLA _SFR_MEM8(0x0A06) -#define TCE0_INTCTRLB _SFR_MEM8(0x0A07) -#define TCE0_CTRLFCLR _SFR_MEM8(0x0A08) -#define TCE0_CTRLFSET _SFR_MEM8(0x0A09) -#define TCE0_CTRLGCLR _SFR_MEM8(0x0A0A) -#define TCE0_CTRLGSET _SFR_MEM8(0x0A0B) -#define TCE0_INTFLAGS _SFR_MEM8(0x0A0C) -#define TCE0_TEMP _SFR_MEM8(0x0A0F) -#define TCE0_CNT _SFR_MEM16(0x0A20) -#define TCE0_PER _SFR_MEM16(0x0A26) -#define TCE0_CCA _SFR_MEM16(0x0A28) -#define TCE0_CCB _SFR_MEM16(0x0A2A) -#define TCE0_CCC _SFR_MEM16(0x0A2C) -#define TCE0_CCD _SFR_MEM16(0x0A2E) -#define TCE0_PERBUF _SFR_MEM16(0x0A36) -#define TCE0_CCABUF _SFR_MEM16(0x0A38) -#define TCE0_CCBBUF _SFR_MEM16(0x0A3A) -#define TCE0_CCCBUF _SFR_MEM16(0x0A3C) -#define TCE0_CCDBUF _SFR_MEM16(0x0A3E) - -/* AWEX - Advanced Waveform Extension */ -#define AWEXE_CTRL _SFR_MEM8(0x0A80) -#define AWEXE_FDEMASK _SFR_MEM8(0x0A82) -#define AWEXE_FDCTRL _SFR_MEM8(0x0A83) -#define AWEXE_STATUS _SFR_MEM8(0x0A84) -#define AWEXE_DTBOTH _SFR_MEM8(0x0A86) -#define AWEXE_DTBOTHBUF _SFR_MEM8(0x0A87) -#define AWEXE_DTLS _SFR_MEM8(0x0A88) -#define AWEXE_DTHS _SFR_MEM8(0x0A89) -#define AWEXE_DTLSBUF _SFR_MEM8(0x0A8A) -#define AWEXE_DTHSBUF _SFR_MEM8(0x0A8B) -#define AWEXE_OUTOVEN _SFR_MEM8(0x0A8C) - -/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ -#define USARTE0_DATA _SFR_MEM8(0x0AA0) -#define USARTE0_STATUS _SFR_MEM8(0x0AA1) -#define USARTE0_CTRLA _SFR_MEM8(0x0AA3) -#define USARTE0_CTRLB _SFR_MEM8(0x0AA4) -#define USARTE0_CTRLC _SFR_MEM8(0x0AA5) -#define USARTE0_BAUDCTRLA _SFR_MEM8(0x0AA6) -#define USARTE0_BAUDCTRLB _SFR_MEM8(0x0AA7) - -/* SPI - Serial Peripheral Interface */ -#define SPIE_CTRL _SFR_MEM8(0x0AC0) -#define SPIE_INTCTRL _SFR_MEM8(0x0AC1) -#define SPIE_STATUS _SFR_MEM8(0x0AC2) -#define SPIE_DATA _SFR_MEM8(0x0AC3) - -/* TC0 - 16-bit Timer/Counter 0 */ -#define TCF0_CTRLA _SFR_MEM8(0x0B00) -#define TCF0_CTRLB _SFR_MEM8(0x0B01) -#define TCF0_CTRLC _SFR_MEM8(0x0B02) -#define TCF0_CTRLD _SFR_MEM8(0x0B03) -#define TCF0_CTRLE _SFR_MEM8(0x0B04) -#define TCF0_INTCTRLA _SFR_MEM8(0x0B06) -#define TCF0_INTCTRLB _SFR_MEM8(0x0B07) -#define TCF0_CTRLFCLR _SFR_MEM8(0x0B08) -#define TCF0_CTRLFSET _SFR_MEM8(0x0B09) -#define TCF0_CTRLGCLR _SFR_MEM8(0x0B0A) -#define TCF0_CTRLGSET _SFR_MEM8(0x0B0B) -#define TCF0_INTFLAGS _SFR_MEM8(0x0B0C) -#define TCF0_TEMP _SFR_MEM8(0x0B0F) -#define TCF0_CNT _SFR_MEM16(0x0B20) -#define TCF0_PER _SFR_MEM16(0x0B26) -#define TCF0_CCA _SFR_MEM16(0x0B28) -#define TCF0_CCB _SFR_MEM16(0x0B2A) -#define TCF0_CCC _SFR_MEM16(0x0B2C) -#define TCF0_CCD _SFR_MEM16(0x0B2E) -#define TCF0_PERBUF _SFR_MEM16(0x0B36) -#define TCF0_CCABUF _SFR_MEM16(0x0B38) -#define TCF0_CCBBUF _SFR_MEM16(0x0B3A) -#define TCF0_CCCBUF _SFR_MEM16(0x0B3C) -#define TCF0_CCDBUF _SFR_MEM16(0x0B3E) - - - -/*================== Bitfield Definitions ================== */ - -/* XOCD - On-Chip Debug System */ -/* OCD.OCDR0 bit masks and bit positions */ -#define OCD_OCDRD_gm 0xFF /* OCDR Dirty group mask. */ -#define OCD_OCDRD_gp 0 /* OCDR Dirty group position. */ -#define OCD_OCDRD0_bm (1<<0) /* OCDR Dirty bit 0 mask. */ -#define OCD_OCDRD0_bp 0 /* OCDR Dirty bit 0 position. */ -#define OCD_OCDRD1_bm (1<<1) /* OCDR Dirty bit 1 mask. */ -#define OCD_OCDRD1_bp 1 /* OCDR Dirty bit 1 position. */ -#define OCD_OCDRD2_bm (1<<2) /* OCDR Dirty bit 2 mask. */ -#define OCD_OCDRD2_bp 2 /* OCDR Dirty bit 2 position. */ -#define OCD_OCDRD3_bm (1<<3) /* OCDR Dirty bit 3 mask. */ -#define OCD_OCDRD3_bp 3 /* OCDR Dirty bit 3 position. */ -#define OCD_OCDRD4_bm (1<<4) /* OCDR Dirty bit 4 mask. */ -#define OCD_OCDRD4_bp 4 /* OCDR Dirty bit 4 position. */ -#define OCD_OCDRD5_bm (1<<5) /* OCDR Dirty bit 5 mask. */ -#define OCD_OCDRD5_bp 5 /* OCDR Dirty bit 5 position. */ -#define OCD_OCDRD6_bm (1<<6) /* OCDR Dirty bit 6 mask. */ -#define OCD_OCDRD6_bp 6 /* OCDR Dirty bit 6 position. */ -#define OCD_OCDRD7_bm (1<<7) /* OCDR Dirty bit 7 mask. */ -#define OCD_OCDRD7_bp 7 /* OCDR Dirty bit 7 position. */ - -/* OCD.OCDR1 bit masks and bit positions */ -/* OCD_OCDRD Predefined. */ -/* OCD_OCDRD Predefined. */ - -/* CPU - CPU */ -/* CPU.CCP bit masks and bit positions */ -#define CPU_CCP_gm 0xFF /* CCP signature group mask. */ -#define CPU_CCP_gp 0 /* CCP signature group position. */ -#define CPU_CCP0_bm (1<<0) /* CCP signature bit 0 mask. */ -#define CPU_CCP0_bp 0 /* CCP signature bit 0 position. */ -#define CPU_CCP1_bm (1<<1) /* CCP signature bit 1 mask. */ -#define CPU_CCP1_bp 1 /* CCP signature bit 1 position. */ -#define CPU_CCP2_bm (1<<2) /* CCP signature bit 2 mask. */ -#define CPU_CCP2_bp 2 /* CCP signature bit 2 position. */ -#define CPU_CCP3_bm (1<<3) /* CCP signature bit 3 mask. */ -#define CPU_CCP3_bp 3 /* CCP signature bit 3 position. */ -#define CPU_CCP4_bm (1<<4) /* CCP signature bit 4 mask. */ -#define CPU_CCP4_bp 4 /* CCP signature bit 4 position. */ -#define CPU_CCP5_bm (1<<5) /* CCP signature bit 5 mask. */ -#define CPU_CCP5_bp 5 /* CCP signature bit 5 position. */ -#define CPU_CCP6_bm (1<<6) /* CCP signature bit 6 mask. */ -#define CPU_CCP6_bp 6 /* CCP signature bit 6 position. */ -#define CPU_CCP7_bm (1<<7) /* CCP signature bit 7 mask. */ -#define CPU_CCP7_bp 7 /* CCP signature bit 7 position. */ - -/* CPU.SREG bit masks and bit positions */ -#define CPU_I_bm 0x80 /* Global Interrupt Enable Flag bit mask. */ -#define CPU_I_bp 7 /* Global Interrupt Enable Flag bit position. */ - -#define CPU_T_bm 0x40 /* Transfer Bit bit mask. */ -#define CPU_T_bp 6 /* Transfer Bit bit position. */ - -#define CPU_H_bm 0x20 /* Half Carry Flag bit mask. */ -#define CPU_H_bp 5 /* Half Carry Flag bit position. */ - -#define CPU_S_bm 0x10 /* N Exclusive Or V Flag bit mask. */ -#define CPU_S_bp 4 /* N Exclusive Or V Flag bit position. */ - -#define CPU_V_bm 0x08 /* Two's Complement Overflow Flag bit mask. */ -#define CPU_V_bp 3 /* Two's Complement Overflow Flag bit position. */ - -#define CPU_N_bm 0x04 /* Negative Flag bit mask. */ -#define CPU_N_bp 2 /* Negative Flag bit position. */ - -#define CPU_Z_bm 0x02 /* Zero Flag bit mask. */ -#define CPU_Z_bp 1 /* Zero Flag bit position. */ - -#define CPU_C_bm 0x01 /* Carry Flag bit mask. */ -#define CPU_C_bp 0 /* Carry Flag bit position. */ - -/* CLK - Clock System */ -/* CLK.CTRL bit masks and bit positions */ -#define CLK_SCLKSEL_gm 0x07 /* System Clock Selection group mask. */ -#define CLK_SCLKSEL_gp 0 /* System Clock Selection group position. */ -#define CLK_SCLKSEL0_bm (1<<0) /* System Clock Selection bit 0 mask. */ -#define CLK_SCLKSEL0_bp 0 /* System Clock Selection bit 0 position. */ -#define CLK_SCLKSEL1_bm (1<<1) /* System Clock Selection bit 1 mask. */ -#define CLK_SCLKSEL1_bp 1 /* System Clock Selection bit 1 position. */ -#define CLK_SCLKSEL2_bm (1<<2) /* System Clock Selection bit 2 mask. */ -#define CLK_SCLKSEL2_bp 2 /* System Clock Selection bit 2 position. */ - -/* CLK.PSCTRL bit masks and bit positions */ -#define CLK_PSADIV_gm 0x7C /* Prescaler A Division Factor group mask. */ -#define CLK_PSADIV_gp 2 /* Prescaler A Division Factor group position. */ -#define CLK_PSADIV0_bm (1<<2) /* Prescaler A Division Factor bit 0 mask. */ -#define CLK_PSADIV0_bp 2 /* Prescaler A Division Factor bit 0 position. */ -#define CLK_PSADIV1_bm (1<<3) /* Prescaler A Division Factor bit 1 mask. */ -#define CLK_PSADIV1_bp 3 /* Prescaler A Division Factor bit 1 position. */ -#define CLK_PSADIV2_bm (1<<4) /* Prescaler A Division Factor bit 2 mask. */ -#define CLK_PSADIV2_bp 4 /* Prescaler A Division Factor bit 2 position. */ -#define CLK_PSADIV3_bm (1<<5) /* Prescaler A Division Factor bit 3 mask. */ -#define CLK_PSADIV3_bp 5 /* Prescaler A Division Factor bit 3 position. */ -#define CLK_PSADIV4_bm (1<<6) /* Prescaler A Division Factor bit 4 mask. */ -#define CLK_PSADIV4_bp 6 /* Prescaler A Division Factor bit 4 position. */ - -#define CLK_PSBCDIV_gm 0x03 /* Prescaler B and C Division factor group mask. */ -#define CLK_PSBCDIV_gp 0 /* Prescaler B and C Division factor group position. */ -#define CLK_PSBCDIV0_bm (1<<0) /* Prescaler B and C Division factor bit 0 mask. */ -#define CLK_PSBCDIV0_bp 0 /* Prescaler B and C Division factor bit 0 position. */ -#define CLK_PSBCDIV1_bm (1<<1) /* Prescaler B and C Division factor bit 1 mask. */ -#define CLK_PSBCDIV1_bp 1 /* Prescaler B and C Division factor bit 1 position. */ - -/* CLK.LOCK bit masks and bit positions */ -#define CLK_LOCK_bm 0x01 /* Clock System Lock bit mask. */ -#define CLK_LOCK_bp 0 /* Clock System Lock bit position. */ - -/* CLK.RTCCTRL bit masks and bit positions */ -#define CLK_RTCSRC_gm 0x0E /* Clock Source group mask. */ -#define CLK_RTCSRC_gp 1 /* Clock Source group position. */ -#define CLK_RTCSRC0_bm (1<<1) /* Clock Source bit 0 mask. */ -#define CLK_RTCSRC0_bp 1 /* Clock Source bit 0 position. */ -#define CLK_RTCSRC1_bm (1<<2) /* Clock Source bit 1 mask. */ -#define CLK_RTCSRC1_bp 2 /* Clock Source bit 1 position. */ -#define CLK_RTCSRC2_bm (1<<3) /* Clock Source bit 2 mask. */ -#define CLK_RTCSRC2_bp 3 /* Clock Source bit 2 position. */ - -#define CLK_RTCEN_bm 0x01 /* Clock Source Enable bit mask. */ -#define CLK_RTCEN_bp 0 /* Clock Source Enable bit position. */ - -/* PR.PRGEN bit masks and bit positions */ -#define PR_RTC_bm 0x04 /* Real-time Counter bit mask. */ -#define PR_RTC_bp 2 /* Real-time Counter bit position. */ - -#define PR_EVSYS_bm 0x02 /* Event System bit mask. */ -#define PR_EVSYS_bp 1 /* Event System bit position. */ - -/* PR.PRPA bit masks and bit positions */ -#define PR_ADC_bm 0x02 /* Port A ADC bit mask. */ -#define PR_ADC_bp 1 /* Port A ADC bit position. */ - -#define PR_AC_bm 0x01 /* Port A Analog Comparator bit mask. */ -#define PR_AC_bp 0 /* Port A Analog Comparator bit position. */ - -/* PR.PRPC bit masks and bit positions */ -#define PR_TWI_bm 0x40 /* Port C Two-wire Interface bit mask. */ -#define PR_TWI_bp 6 /* Port C Two-wire Interface bit position. */ - -#define PR_USART0_bm 0x10 /* Port C USART0 bit mask. */ -#define PR_USART0_bp 4 /* Port C USART0 bit position. */ - -#define PR_SPI_bm 0x08 /* Port C SPI bit mask. */ -#define PR_SPI_bp 3 /* Port C SPI bit position. */ - -#define PR_HIRES_bm 0x04 /* Port C HIRES bit mask. */ -#define PR_HIRES_bp 2 /* Port C HIRES bit position. */ - -#define PR_TC1_bm 0x02 /* Port C Timer/Counter1 bit mask. */ -#define PR_TC1_bp 1 /* Port C Timer/Counter1 bit position. */ - -#define PR_TC0_bm 0x01 /* Port C Timer/Counter0 bit mask. */ -#define PR_TC0_bp 0 /* Port C Timer/Counter0 bit position. */ - -/* PR.PRPD bit masks and bit positions */ -/* PR_USART0 Predefined. */ -/* PR_USART0 Predefined. */ - -/* PR_SPI Predefined. */ -/* PR_SPI Predefined. */ - -/* PR_TC0 Predefined. */ -/* PR_TC0 Predefined. */ - -/* PR.PRPE bit masks and bit positions */ -/* PR_TWI Predefined. */ -/* PR_TWI Predefined. */ - -/* PR_USART0 Predefined. */ -/* PR_USART0 Predefined. */ - -/* PR_TC0 Predefined. */ -/* PR_TC0 Predefined. */ - -/* PR.PRPF bit masks and bit positions */ -/* PR_USART0 Predefined. */ -/* PR_USART0 Predefined. */ - -/* PR_TC0 Predefined. */ -/* PR_TC0 Predefined. */ - -/* SLEEP - Sleep Controller */ -/* SLEEP.CTRL bit masks and bit positions */ -#define SLEEP_SMODE_gm 0x0E /* Sleep Mode group mask. */ -#define SLEEP_SMODE_gp 1 /* Sleep Mode group position. */ -#define SLEEP_SMODE0_bm (1<<1) /* Sleep Mode bit 0 mask. */ -#define SLEEP_SMODE0_bp 1 /* Sleep Mode bit 0 position. */ -#define SLEEP_SMODE1_bm (1<<2) /* Sleep Mode bit 1 mask. */ -#define SLEEP_SMODE1_bp 2 /* Sleep Mode bit 1 position. */ -#define SLEEP_SMODE2_bm (1<<3) /* Sleep Mode bit 2 mask. */ -#define SLEEP_SMODE2_bp 3 /* Sleep Mode bit 2 position. */ - -#define SLEEP_SEN_bm 0x01 /* Sleep Enable bit mask. */ -#define SLEEP_SEN_bp 0 /* Sleep Enable bit position. */ - -/* OSC - Oscillator */ -/* OSC.CTRL bit masks and bit positions */ -#define OSC_PLLEN_bm 0x10 /* PLL Enable bit mask. */ -#define OSC_PLLEN_bp 4 /* PLL Enable bit position. */ - -#define OSC_XOSCEN_bm 0x08 /* External Oscillator Enable bit mask. */ -#define OSC_XOSCEN_bp 3 /* External Oscillator Enable bit position. */ - -#define OSC_RC32KEN_bm 0x04 /* Internal 32kHz RC Oscillator Enable bit mask. */ -#define OSC_RC32KEN_bp 2 /* Internal 32kHz RC Oscillator Enable bit position. */ - -#define OSC_RC32MEN_bm 0x02 /* Internal 32MHz RC Oscillator Enable bit mask. */ -#define OSC_RC32MEN_bp 1 /* Internal 32MHz RC Oscillator Enable bit position. */ - -#define OSC_RC2MEN_bm 0x01 /* Internal 2MHz RC Oscillator Enable bit mask. */ -#define OSC_RC2MEN_bp 0 /* Internal 2MHz RC Oscillator Enable bit position. */ - -/* OSC.STATUS bit masks and bit positions */ -#define OSC_PLLRDY_bm 0x10 /* PLL Ready bit mask. */ -#define OSC_PLLRDY_bp 4 /* PLL Ready bit position. */ - -#define OSC_XOSCRDY_bm 0x08 /* External Oscillator Ready bit mask. */ -#define OSC_XOSCRDY_bp 3 /* External Oscillator Ready bit position. */ - -#define OSC_RC32KRDY_bm 0x04 /* Internal 32kHz RC Oscillator Ready bit mask. */ -#define OSC_RC32KRDY_bp 2 /* Internal 32kHz RC Oscillator Ready bit position. */ - -#define OSC_RC32MRDY_bm 0x02 /* Internal 32MHz RC Oscillator Ready bit mask. */ -#define OSC_RC32MRDY_bp 1 /* Internal 32MHz RC Oscillator Ready bit position. */ - -#define OSC_RC2MRDY_bm 0x01 /* Internal 2MHz RC Oscillator Ready bit mask. */ -#define OSC_RC2MRDY_bp 0 /* Internal 2MHz RC Oscillator Ready bit position. */ - -/* OSC.XOSCCTRL bit masks and bit positions */ -#define OSC_FRQRANGE_gm 0xC0 /* Frequency Range group mask. */ -#define OSC_FRQRANGE_gp 6 /* Frequency Range group position. */ -#define OSC_FRQRANGE0_bm (1<<6) /* Frequency Range bit 0 mask. */ -#define OSC_FRQRANGE0_bp 6 /* Frequency Range bit 0 position. */ -#define OSC_FRQRANGE1_bm (1<<7) /* Frequency Range bit 1 mask. */ -#define OSC_FRQRANGE1_bp 7 /* Frequency Range bit 1 position. */ - -#define OSC_X32KLPM_bm 0x20 /* 32kHz XTAL OSC Low-power Mode bit mask. */ -#define OSC_X32KLPM_bp 5 /* 32kHz XTAL OSC Low-power Mode bit position. */ - -#define OSC_XOSCSEL_gm 0x0F /* External Oscillator Selection and Startup Time group mask. */ -#define OSC_XOSCSEL_gp 0 /* External Oscillator Selection and Startup Time group position. */ -#define OSC_XOSCSEL0_bm (1<<0) /* External Oscillator Selection and Startup Time bit 0 mask. */ -#define OSC_XOSCSEL0_bp 0 /* External Oscillator Selection and Startup Time bit 0 position. */ -#define OSC_XOSCSEL1_bm (1<<1) /* External Oscillator Selection and Startup Time bit 1 mask. */ -#define OSC_XOSCSEL1_bp 1 /* External Oscillator Selection and Startup Time bit 1 position. */ -#define OSC_XOSCSEL2_bm (1<<2) /* External Oscillator Selection and Startup Time bit 2 mask. */ -#define OSC_XOSCSEL2_bp 2 /* External Oscillator Selection and Startup Time bit 2 position. */ -#define OSC_XOSCSEL3_bm (1<<3) /* External Oscillator Selection and Startup Time bit 3 mask. */ -#define OSC_XOSCSEL3_bp 3 /* External Oscillator Selection and Startup Time bit 3 position. */ - -/* OSC.XOSCFAIL bit masks and bit positions */ -#define OSC_XOSCFDIF_bm 0x02 /* Failure Detection Interrupt Flag bit mask. */ -#define OSC_XOSCFDIF_bp 1 /* Failure Detection Interrupt Flag bit position. */ - -#define OSC_XOSCFDEN_bm 0x01 /* Failure Detection Enable bit mask. */ -#define OSC_XOSCFDEN_bp 0 /* Failure Detection Enable bit position. */ - -/* OSC.PLLCTRL bit masks and bit positions */ -#define OSC_PLLSRC_gm 0xC0 /* Clock Source group mask. */ -#define OSC_PLLSRC_gp 6 /* Clock Source group position. */ -#define OSC_PLLSRC0_bm (1<<6) /* Clock Source bit 0 mask. */ -#define OSC_PLLSRC0_bp 6 /* Clock Source bit 0 position. */ -#define OSC_PLLSRC1_bm (1<<7) /* Clock Source bit 1 mask. */ -#define OSC_PLLSRC1_bp 7 /* Clock Source bit 1 position. */ - -#define OSC_PLLFAC_gm 0x1F /* Multiplication Factor group mask. */ -#define OSC_PLLFAC_gp 0 /* Multiplication Factor group position. */ -#define OSC_PLLFAC0_bm (1<<0) /* Multiplication Factor bit 0 mask. */ -#define OSC_PLLFAC0_bp 0 /* Multiplication Factor bit 0 position. */ -#define OSC_PLLFAC1_bm (1<<1) /* Multiplication Factor bit 1 mask. */ -#define OSC_PLLFAC1_bp 1 /* Multiplication Factor bit 1 position. */ -#define OSC_PLLFAC2_bm (1<<2) /* Multiplication Factor bit 2 mask. */ -#define OSC_PLLFAC2_bp 2 /* Multiplication Factor bit 2 position. */ -#define OSC_PLLFAC3_bm (1<<3) /* Multiplication Factor bit 3 mask. */ -#define OSC_PLLFAC3_bp 3 /* Multiplication Factor bit 3 position. */ -#define OSC_PLLFAC4_bm (1<<4) /* Multiplication Factor bit 4 mask. */ -#define OSC_PLLFAC4_bp 4 /* Multiplication Factor bit 4 position. */ - -/* OSC.DFLLCTRL bit masks and bit positions */ -#define OSC_RC32MCREF_bm 0x02 /* 32MHz Calibration Reference bit mask. */ -#define OSC_RC32MCREF_bp 1 /* 32MHz Calibration Reference bit position. */ - -#define OSC_RC2MCREF_bm 0x01 /* 2MHz Calibration Reference bit mask. */ -#define OSC_RC2MCREF_bp 0 /* 2MHz Calibration Reference bit position. */ - -/* DFLL - DFLL */ -/* DFLL.CTRL bit masks and bit positions */ -#define DFLL_ENABLE_bm 0x01 /* DFLL Enable bit mask. */ -#define DFLL_ENABLE_bp 0 /* DFLL Enable bit position. */ - -/* DFLL.CALA bit masks and bit positions */ -#define DFLL_CALL_gm 0x7F /* DFLL Calibration bits [6:0] group mask. */ -#define DFLL_CALL_gp 0 /* DFLL Calibration bits [6:0] group position. */ -#define DFLL_CALL0_bm (1<<0) /* DFLL Calibration bits [6:0] bit 0 mask. */ -#define DFLL_CALL0_bp 0 /* DFLL Calibration bits [6:0] bit 0 position. */ -#define DFLL_CALL1_bm (1<<1) /* DFLL Calibration bits [6:0] bit 1 mask. */ -#define DFLL_CALL1_bp 1 /* DFLL Calibration bits [6:0] bit 1 position. */ -#define DFLL_CALL2_bm (1<<2) /* DFLL Calibration bits [6:0] bit 2 mask. */ -#define DFLL_CALL2_bp 2 /* DFLL Calibration bits [6:0] bit 2 position. */ -#define DFLL_CALL3_bm (1<<3) /* DFLL Calibration bits [6:0] bit 3 mask. */ -#define DFLL_CALL3_bp 3 /* DFLL Calibration bits [6:0] bit 3 position. */ -#define DFLL_CALL4_bm (1<<4) /* DFLL Calibration bits [6:0] bit 4 mask. */ -#define DFLL_CALL4_bp 4 /* DFLL Calibration bits [6:0] bit 4 position. */ -#define DFLL_CALL5_bm (1<<5) /* DFLL Calibration bits [6:0] bit 5 mask. */ -#define DFLL_CALL5_bp 5 /* DFLL Calibration bits [6:0] bit 5 position. */ -#define DFLL_CALL6_bm (1<<6) /* DFLL Calibration bits [6:0] bit 6 mask. */ -#define DFLL_CALL6_bp 6 /* DFLL Calibration bits [6:0] bit 6 position. */ - -/* DFLL.CALB bit masks and bit positions */ -#define DFLL_CALH_gm 0x3F /* DFLL Calibration bits [12:7] group mask. */ -#define DFLL_CALH_gp 0 /* DFLL Calibration bits [12:7] group position. */ -#define DFLL_CALH0_bm (1<<0) /* DFLL Calibration bits [12:7] bit 0 mask. */ -#define DFLL_CALH0_bp 0 /* DFLL Calibration bits [12:7] bit 0 position. */ -#define DFLL_CALH1_bm (1<<1) /* DFLL Calibration bits [12:7] bit 1 mask. */ -#define DFLL_CALH1_bp 1 /* DFLL Calibration bits [12:7] bit 1 position. */ -#define DFLL_CALH2_bm (1<<2) /* DFLL Calibration bits [12:7] bit 2 mask. */ -#define DFLL_CALH2_bp 2 /* DFLL Calibration bits [12:7] bit 2 position. */ -#define DFLL_CALH3_bm (1<<3) /* DFLL Calibration bits [12:7] bit 3 mask. */ -#define DFLL_CALH3_bp 3 /* DFLL Calibration bits [12:7] bit 3 position. */ -#define DFLL_CALH4_bm (1<<4) /* DFLL Calibration bits [12:7] bit 4 mask. */ -#define DFLL_CALH4_bp 4 /* DFLL Calibration bits [12:7] bit 4 position. */ -#define DFLL_CALH5_bm (1<<5) /* DFLL Calibration bits [12:7] bit 5 mask. */ -#define DFLL_CALH5_bp 5 /* DFLL Calibration bits [12:7] bit 5 position. */ - -/* RST - Reset */ -/* RST.STATUS bit masks and bit positions */ -#define RST_SDRF_bm 0x40 /* Spike Detection Reset Flag bit mask. */ -#define RST_SDRF_bp 6 /* Spike Detection Reset Flag bit position. */ - -#define RST_SRF_bm 0x20 /* Software Reset Flag bit mask. */ -#define RST_SRF_bp 5 /* Software Reset Flag bit position. */ - -#define RST_PDIRF_bm 0x10 /* Programming and Debug Interface Interface Reset Flag bit mask. */ -#define RST_PDIRF_bp 4 /* Programming and Debug Interface Interface Reset Flag bit position. */ - -#define RST_WDRF_bm 0x08 /* Watchdog Reset Flag bit mask. */ -#define RST_WDRF_bp 3 /* Watchdog Reset Flag bit position. */ - -#define RST_BORF_bm 0x04 /* Brown-out Reset Flag bit mask. */ -#define RST_BORF_bp 2 /* Brown-out Reset Flag bit position. */ - -#define RST_EXTRF_bm 0x02 /* External Reset Flag bit mask. */ -#define RST_EXTRF_bp 1 /* External Reset Flag bit position. */ - -#define RST_PORF_bm 0x01 /* Power-on Reset Flag bit mask. */ -#define RST_PORF_bp 0 /* Power-on Reset Flag bit position. */ - -/* RST.CTRL bit masks and bit positions */ -#define RST_SWRST_bm 0x01 /* Software Reset bit mask. */ -#define RST_SWRST_bp 0 /* Software Reset bit position. */ - -/* WDT - Watch-Dog Timer */ -/* WDT.CTRL bit masks and bit positions */ -#define WDT_PER_gm 0x3C /* Period group mask. */ -#define WDT_PER_gp 2 /* Period group position. */ -#define WDT_PER0_bm (1<<2) /* Period bit 0 mask. */ -#define WDT_PER0_bp 2 /* Period bit 0 position. */ -#define WDT_PER1_bm (1<<3) /* Period bit 1 mask. */ -#define WDT_PER1_bp 3 /* Period bit 1 position. */ -#define WDT_PER2_bm (1<<4) /* Period bit 2 mask. */ -#define WDT_PER2_bp 4 /* Period bit 2 position. */ -#define WDT_PER3_bm (1<<5) /* Period bit 3 mask. */ -#define WDT_PER3_bp 5 /* Period bit 3 position. */ - -#define WDT_ENABLE_bm 0x02 /* Enable bit mask. */ -#define WDT_ENABLE_bp 1 /* Enable bit position. */ - -#define WDT_CEN_bm 0x01 /* Change Enable bit mask. */ -#define WDT_CEN_bp 0 /* Change Enable bit position. */ - -/* WDT.WINCTRL bit masks and bit positions */ -#define WDT_WPER_gm 0x3C /* Windowed Mode Period group mask. */ -#define WDT_WPER_gp 2 /* Windowed Mode Period group position. */ -#define WDT_WPER0_bm (1<<2) /* Windowed Mode Period bit 0 mask. */ -#define WDT_WPER0_bp 2 /* Windowed Mode Period bit 0 position. */ -#define WDT_WPER1_bm (1<<3) /* Windowed Mode Period bit 1 mask. */ -#define WDT_WPER1_bp 3 /* Windowed Mode Period bit 1 position. */ -#define WDT_WPER2_bm (1<<4) /* Windowed Mode Period bit 2 mask. */ -#define WDT_WPER2_bp 4 /* Windowed Mode Period bit 2 position. */ -#define WDT_WPER3_bm (1<<5) /* Windowed Mode Period bit 3 mask. */ -#define WDT_WPER3_bp 5 /* Windowed Mode Period bit 3 position. */ - -#define WDT_WEN_bm 0x02 /* Windowed Mode Enable bit mask. */ -#define WDT_WEN_bp 1 /* Windowed Mode Enable bit position. */ - -#define WDT_WCEN_bm 0x01 /* Windowed Mode Change Enable bit mask. */ -#define WDT_WCEN_bp 0 /* Windowed Mode Change Enable bit position. */ - -/* WDT.STATUS bit masks and bit positions */ -#define WDT_SYNCBUSY_bm 0x01 /* Syncronization busy bit mask. */ -#define WDT_SYNCBUSY_bp 0 /* Syncronization busy bit position. */ - -/* MCU - MCU Control */ -/* MCU.MCUCR bit masks and bit positions */ -#define MCU_JTAGD_bm 0x01 /* JTAG Disable bit mask. */ -#define MCU_JTAGD_bp 0 /* JTAG Disable bit position. */ - -/* MCU.EVSYSLOCK bit masks and bit positions */ -#define MCU_EVSYS1LOCK_bm 0x10 /* Event Channel 4-7 Lock bit mask. */ -#define MCU_EVSYS1LOCK_bp 4 /* Event Channel 4-7 Lock bit position. */ - -#define MCU_EVSYS0LOCK_bm 0x01 /* Event Channel 0-3 Lock bit mask. */ -#define MCU_EVSYS0LOCK_bp 0 /* Event Channel 0-3 Lock bit position. */ - -/* MCU.AWEXLOCK bit masks and bit positions */ -#define MCU_AWEXELOCK_bm 0x04 /* AWeX on T/C E0 Lock bit mask. */ -#define MCU_AWEXELOCK_bp 2 /* AWeX on T/C E0 Lock bit position. */ - -#define MCU_AWEXCLOCK_bm 0x01 /* AWeX on T/C C0 Lock bit mask. */ -#define MCU_AWEXCLOCK_bp 0 /* AWeX on T/C C0 Lock bit position. */ - -/* PMIC - Programmable Multi-level Interrupt Controller */ -/* PMIC.STATUS bit masks and bit positions */ -#define PMIC_NMIEX_bm 0x80 /* Non-maskable Interrupt Executing bit mask. */ -#define PMIC_NMIEX_bp 7 /* Non-maskable Interrupt Executing bit position. */ - -#define PMIC_HILVLEX_bm 0x04 /* High Level Interrupt Executing bit mask. */ -#define PMIC_HILVLEX_bp 2 /* High Level Interrupt Executing bit position. */ - -#define PMIC_MEDLVLEX_bm 0x02 /* Medium Level Interrupt Executing bit mask. */ -#define PMIC_MEDLVLEX_bp 1 /* Medium Level Interrupt Executing bit position. */ - -#define PMIC_LOLVLEX_bm 0x01 /* Low Level Interrupt Executing bit mask. */ -#define PMIC_LOLVLEX_bp 0 /* Low Level Interrupt Executing bit position. */ - -/* PMIC.INTPRI bit masks and bit positions */ -#define PMIC_INTPRI_gm 0xFF /* Interrupt Priority group mask. */ -#define PMIC_INTPRI_gp 0 /* Interrupt Priority group position. */ -#define PMIC_INTPRI0_bm (1<<0) /* Interrupt Priority bit 0 mask. */ -#define PMIC_INTPRI0_bp 0 /* Interrupt Priority bit 0 position. */ -#define PMIC_INTPRI1_bm (1<<1) /* Interrupt Priority bit 1 mask. */ -#define PMIC_INTPRI1_bp 1 /* Interrupt Priority bit 1 position. */ -#define PMIC_INTPRI2_bm (1<<2) /* Interrupt Priority bit 2 mask. */ -#define PMIC_INTPRI2_bp 2 /* Interrupt Priority bit 2 position. */ -#define PMIC_INTPRI3_bm (1<<3) /* Interrupt Priority bit 3 mask. */ -#define PMIC_INTPRI3_bp 3 /* Interrupt Priority bit 3 position. */ -#define PMIC_INTPRI4_bm (1<<4) /* Interrupt Priority bit 4 mask. */ -#define PMIC_INTPRI4_bp 4 /* Interrupt Priority bit 4 position. */ -#define PMIC_INTPRI5_bm (1<<5) /* Interrupt Priority bit 5 mask. */ -#define PMIC_INTPRI5_bp 5 /* Interrupt Priority bit 5 position. */ -#define PMIC_INTPRI6_bm (1<<6) /* Interrupt Priority bit 6 mask. */ -#define PMIC_INTPRI6_bp 6 /* Interrupt Priority bit 6 position. */ -#define PMIC_INTPRI7_bm (1<<7) /* Interrupt Priority bit 7 mask. */ -#define PMIC_INTPRI7_bp 7 /* Interrupt Priority bit 7 position. */ - -/* PMIC.CTRL bit masks and bit positions */ -#define PMIC_RREN_bm 0x80 /* Round-Robin Priority Enable bit mask. */ -#define PMIC_RREN_bp 7 /* Round-Robin Priority Enable bit position. */ - -#define PMIC_IVSEL_bm 0x40 /* Interrupt Vector Select bit mask. */ -#define PMIC_IVSEL_bp 6 /* Interrupt Vector Select bit position. */ - -#define PMIC_HILVLEN_bm 0x04 /* High Level Enable bit mask. */ -#define PMIC_HILVLEN_bp 2 /* High Level Enable bit position. */ - -#define PMIC_MEDLVLEN_bm 0x02 /* Medium Level Enable bit mask. */ -#define PMIC_MEDLVLEN_bp 1 /* Medium Level Enable bit position. */ - -#define PMIC_LOLVLEN_bm 0x01 /* Low Level Enable bit mask. */ -#define PMIC_LOLVLEN_bp 0 /* Low Level Enable bit position. */ - -/* CRC - Cyclic Redundancy Checker */ -/* CRC.CTRL bit masks and bit positions */ -#define CRC_RESET_gm 0xC0 /* Reset group mask. */ -#define CRC_RESET_gp 6 /* Reset group position. */ -#define CRC_RESET0_bm (1<<6) /* Reset bit 0 mask. */ -#define CRC_RESET0_bp 6 /* Reset bit 0 position. */ -#define CRC_RESET1_bm (1<<7) /* Reset bit 1 mask. */ -#define CRC_RESET1_bp 7 /* Reset bit 1 position. */ - -#define CRC_CRC32_bm 0x20 /* CRC Mode bit mask. */ -#define CRC_CRC32_bp 5 /* CRC Mode bit position. */ - -#define CRC_SOURCE_gm 0x0F /* Input Source group mask. */ -#define CRC_SOURCE_gp 0 /* Input Source group position. */ -#define CRC_SOURCE0_bm (1<<0) /* Input Source bit 0 mask. */ -#define CRC_SOURCE0_bp 0 /* Input Source bit 0 position. */ -#define CRC_SOURCE1_bm (1<<1) /* Input Source bit 1 mask. */ -#define CRC_SOURCE1_bp 1 /* Input Source bit 1 position. */ -#define CRC_SOURCE2_bm (1<<2) /* Input Source bit 2 mask. */ -#define CRC_SOURCE2_bp 2 /* Input Source bit 2 position. */ -#define CRC_SOURCE3_bm (1<<3) /* Input Source bit 3 mask. */ -#define CRC_SOURCE3_bp 3 /* Input Source bit 3 position. */ - -/* CRC.STATUS bit masks and bit positions */ -#define CRC_ZERO_bm 0x02 /* Zero detection bit mask. */ -#define CRC_ZERO_bp 1 /* Zero detection bit position. */ - -#define CRC_BUSY_bm 0x01 /* Busy bit mask. */ -#define CRC_BUSY_bp 0 /* Busy bit position. */ - -/* EVSYS - Event System */ -/* EVSYS.CH0MUX bit masks and bit positions */ -#define EVSYS_CHMUX_gm 0xFF /* Event Channel 0 Multiplexer group mask. */ -#define EVSYS_CHMUX_gp 0 /* Event Channel 0 Multiplexer group position. */ -#define EVSYS_CHMUX0_bm (1<<0) /* Event Channel 0 Multiplexer bit 0 mask. */ -#define EVSYS_CHMUX0_bp 0 /* Event Channel 0 Multiplexer bit 0 position. */ -#define EVSYS_CHMUX1_bm (1<<1) /* Event Channel 0 Multiplexer bit 1 mask. */ -#define EVSYS_CHMUX1_bp 1 /* Event Channel 0 Multiplexer bit 1 position. */ -#define EVSYS_CHMUX2_bm (1<<2) /* Event Channel 0 Multiplexer bit 2 mask. */ -#define EVSYS_CHMUX2_bp 2 /* Event Channel 0 Multiplexer bit 2 position. */ -#define EVSYS_CHMUX3_bm (1<<3) /* Event Channel 0 Multiplexer bit 3 mask. */ -#define EVSYS_CHMUX3_bp 3 /* Event Channel 0 Multiplexer bit 3 position. */ -#define EVSYS_CHMUX4_bm (1<<4) /* Event Channel 0 Multiplexer bit 4 mask. */ -#define EVSYS_CHMUX4_bp 4 /* Event Channel 0 Multiplexer bit 4 position. */ -#define EVSYS_CHMUX5_bm (1<<5) /* Event Channel 0 Multiplexer bit 5 mask. */ -#define EVSYS_CHMUX5_bp 5 /* Event Channel 0 Multiplexer bit 5 position. */ -#define EVSYS_CHMUX6_bm (1<<6) /* Event Channel 0 Multiplexer bit 6 mask. */ -#define EVSYS_CHMUX6_bp 6 /* Event Channel 0 Multiplexer bit 6 position. */ -#define EVSYS_CHMUX7_bm (1<<7) /* Event Channel 0 Multiplexer bit 7 mask. */ -#define EVSYS_CHMUX7_bp 7 /* Event Channel 0 Multiplexer bit 7 position. */ - -/* EVSYS.CH1MUX bit masks and bit positions */ -/* EVSYS_CHMUX Predefined. */ -/* EVSYS_CHMUX Predefined. */ - -/* EVSYS.CH2MUX bit masks and bit positions */ -/* EVSYS_CHMUX Predefined. */ -/* EVSYS_CHMUX Predefined. */ - -/* EVSYS.CH3MUX bit masks and bit positions */ -/* EVSYS_CHMUX Predefined. */ -/* EVSYS_CHMUX Predefined. */ - -/* EVSYS.CH0CTRL bit masks and bit positions */ -#define EVSYS_QDIRM_gm 0x60 /* Quadrature Decoder Index Recognition Mode group mask. */ -#define EVSYS_QDIRM_gp 5 /* Quadrature Decoder Index Recognition Mode group position. */ -#define EVSYS_QDIRM0_bm (1<<5) /* Quadrature Decoder Index Recognition Mode bit 0 mask. */ -#define EVSYS_QDIRM0_bp 5 /* Quadrature Decoder Index Recognition Mode bit 0 position. */ -#define EVSYS_QDIRM1_bm (1<<6) /* Quadrature Decoder Index Recognition Mode bit 1 mask. */ -#define EVSYS_QDIRM1_bp 6 /* Quadrature Decoder Index Recognition Mode bit 1 position. */ - -#define EVSYS_QDIEN_bm 0x10 /* Quadrature Decoder Index Enable bit mask. */ -#define EVSYS_QDIEN_bp 4 /* Quadrature Decoder Index Enable bit position. */ - -#define EVSYS_QDEN_bm 0x08 /* Quadrature Decoder Enable bit mask. */ -#define EVSYS_QDEN_bp 3 /* Quadrature Decoder Enable bit position. */ - -#define EVSYS_DIGFILT_gm 0x07 /* Digital Filter group mask. */ -#define EVSYS_DIGFILT_gp 0 /* Digital Filter group position. */ -#define EVSYS_DIGFILT0_bm (1<<0) /* Digital Filter bit 0 mask. */ -#define EVSYS_DIGFILT0_bp 0 /* Digital Filter bit 0 position. */ -#define EVSYS_DIGFILT1_bm (1<<1) /* Digital Filter bit 1 mask. */ -#define EVSYS_DIGFILT1_bp 1 /* Digital Filter bit 1 position. */ -#define EVSYS_DIGFILT2_bm (1<<2) /* Digital Filter bit 2 mask. */ -#define EVSYS_DIGFILT2_bp 2 /* Digital Filter bit 2 position. */ - -/* EVSYS.CH1CTRL bit masks and bit positions */ -/* EVSYS_DIGFILT Predefined. */ -/* EVSYS_DIGFILT Predefined. */ - -/* EVSYS.CH2CTRL bit masks and bit positions */ -/* EVSYS_DIGFILT Predefined. */ -/* EVSYS_DIGFILT Predefined. */ - -/* EVSYS.CH3CTRL bit masks and bit positions */ -/* EVSYS_DIGFILT Predefined. */ -/* EVSYS_DIGFILT Predefined. */ - -/* NVM - Non Volatile Memory Controller */ -/* NVM.CMD bit masks and bit positions */ -#define NVM_CMD_gm 0xFF /* Command group mask. */ -#define NVM_CMD_gp 0 /* Command group position. */ -#define NVM_CMD0_bm (1<<0) /* Command bit 0 mask. */ -#define NVM_CMD0_bp 0 /* Command bit 0 position. */ -#define NVM_CMD1_bm (1<<1) /* Command bit 1 mask. */ -#define NVM_CMD1_bp 1 /* Command bit 1 position. */ -#define NVM_CMD2_bm (1<<2) /* Command bit 2 mask. */ -#define NVM_CMD2_bp 2 /* Command bit 2 position. */ -#define NVM_CMD3_bm (1<<3) /* Command bit 3 mask. */ -#define NVM_CMD3_bp 3 /* Command bit 3 position. */ -#define NVM_CMD4_bm (1<<4) /* Command bit 4 mask. */ -#define NVM_CMD4_bp 4 /* Command bit 4 position. */ -#define NVM_CMD5_bm (1<<5) /* Command bit 5 mask. */ -#define NVM_CMD5_bp 5 /* Command bit 5 position. */ -#define NVM_CMD6_bm (1<<6) /* Command bit 6 mask. */ -#define NVM_CMD6_bp 6 /* Command bit 6 position. */ -#define NVM_CMD7_bm (1<<7) /* Command bit 7 mask. */ -#define NVM_CMD7_bp 7 /* Command bit 7 position. */ - -/* NVM.CTRLA bit masks and bit positions */ -#define NVM_CMDEX_bm 0x01 /* Command Execute bit mask. */ -#define NVM_CMDEX_bp 0 /* Command Execute bit position. */ - -/* NVM.CTRLB bit masks and bit positions */ -#define NVM_EEMAPEN_bm 0x08 /* EEPROM Mapping Enable bit mask. */ -#define NVM_EEMAPEN_bp 3 /* EEPROM Mapping Enable bit position. */ - -#define NVM_FPRM_bm 0x04 /* Flash Power Reduction Enable bit mask. */ -#define NVM_FPRM_bp 2 /* Flash Power Reduction Enable bit position. */ - -#define NVM_EPRM_bm 0x02 /* EEPROM Power Reduction Enable bit mask. */ -#define NVM_EPRM_bp 1 /* EEPROM Power Reduction Enable bit position. */ - -#define NVM_SPMLOCK_bm 0x01 /* SPM Lock bit mask. */ -#define NVM_SPMLOCK_bp 0 /* SPM Lock bit position. */ - -/* NVM.INTCTRL bit masks and bit positions */ -#define NVM_SPMLVL_gm 0x0C /* SPM Interrupt Level group mask. */ -#define NVM_SPMLVL_gp 2 /* SPM Interrupt Level group position. */ -#define NVM_SPMLVL0_bm (1<<2) /* SPM Interrupt Level bit 0 mask. */ -#define NVM_SPMLVL0_bp 2 /* SPM Interrupt Level bit 0 position. */ -#define NVM_SPMLVL1_bm (1<<3) /* SPM Interrupt Level bit 1 mask. */ -#define NVM_SPMLVL1_bp 3 /* SPM Interrupt Level bit 1 position. */ - -#define NVM_EELVL_gm 0x03 /* EEPROM Interrupt Level group mask. */ -#define NVM_EELVL_gp 0 /* EEPROM Interrupt Level group position. */ -#define NVM_EELVL0_bm (1<<0) /* EEPROM Interrupt Level bit 0 mask. */ -#define NVM_EELVL0_bp 0 /* EEPROM Interrupt Level bit 0 position. */ -#define NVM_EELVL1_bm (1<<1) /* EEPROM Interrupt Level bit 1 mask. */ -#define NVM_EELVL1_bp 1 /* EEPROM Interrupt Level bit 1 position. */ - -/* NVM.STATUS bit masks and bit positions */ -#define NVM_NVMBUSY_bm 0x80 /* Non-volatile Memory Busy bit mask. */ -#define NVM_NVMBUSY_bp 7 /* Non-volatile Memory Busy bit position. */ - -#define NVM_FBUSY_bm 0x40 /* Flash Memory Busy bit mask. */ -#define NVM_FBUSY_bp 6 /* Flash Memory Busy bit position. */ - -#define NVM_EELOAD_bm 0x02 /* EEPROM Page Buffer Active Loading bit mask. */ -#define NVM_EELOAD_bp 1 /* EEPROM Page Buffer Active Loading bit position. */ - -#define NVM_FLOAD_bm 0x01 /* Flash Page Buffer Active Loading bit mask. */ -#define NVM_FLOAD_bp 0 /* Flash Page Buffer Active Loading bit position. */ - -/* NVM.LOCKBITS bit masks and bit positions */ -#define NVM_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ -#define NVM_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ -#define NVM_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ -#define NVM_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ -#define NVM_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ -#define NVM_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ - -#define NVM_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ -#define NVM_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ -#define NVM_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ -#define NVM_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ -#define NVM_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ -#define NVM_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ - -#define NVM_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ -#define NVM_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ -#define NVM_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ -#define NVM_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ -#define NVM_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ -#define NVM_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ - -#define NVM_LB_gm 0x03 /* Lock Bits group mask. */ -#define NVM_LB_gp 0 /* Lock Bits group position. */ -#define NVM_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ -#define NVM_LB0_bp 0 /* Lock Bits bit 0 position. */ -#define NVM_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ -#define NVM_LB1_bp 1 /* Lock Bits bit 1 position. */ - -/* NVM_LOCKBITS.LOCKBITS bit masks and bit positions */ -#define NVM_LOCKBITS_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ -#define NVM_LOCKBITS_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ -#define NVM_LOCKBITS_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ -#define NVM_LOCKBITS_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ -#define NVM_LOCKBITS_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ -#define NVM_LOCKBITS_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ - -#define NVM_LOCKBITS_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ -#define NVM_LOCKBITS_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ -#define NVM_LOCKBITS_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ -#define NVM_LOCKBITS_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ -#define NVM_LOCKBITS_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ -#define NVM_LOCKBITS_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ - -#define NVM_LOCKBITS_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ -#define NVM_LOCKBITS_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ -#define NVM_LOCKBITS_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ -#define NVM_LOCKBITS_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ -#define NVM_LOCKBITS_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ -#define NVM_LOCKBITS_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ - -#define NVM_LOCKBITS_LB_gm 0x03 /* Lock Bits group mask. */ -#define NVM_LOCKBITS_LB_gp 0 /* Lock Bits group position. */ -#define NVM_LOCKBITS_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ -#define NVM_LOCKBITS_LB0_bp 0 /* Lock Bits bit 0 position. */ -#define NVM_LOCKBITS_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ -#define NVM_LOCKBITS_LB1_bp 1 /* Lock Bits bit 1 position. */ - -/* NVM_FUSES.FUSEBYTE1 bit masks and bit positions */ -#define NVM_FUSES_WDWP_gm 0xF0 /* Watchdog Window Timeout Period group mask. */ -#define NVM_FUSES_WDWP_gp 4 /* Watchdog Window Timeout Period group position. */ -#define NVM_FUSES_WDWP0_bm (1<<4) /* Watchdog Window Timeout Period bit 0 mask. */ -#define NVM_FUSES_WDWP0_bp 4 /* Watchdog Window Timeout Period bit 0 position. */ -#define NVM_FUSES_WDWP1_bm (1<<5) /* Watchdog Window Timeout Period bit 1 mask. */ -#define NVM_FUSES_WDWP1_bp 5 /* Watchdog Window Timeout Period bit 1 position. */ -#define NVM_FUSES_WDWP2_bm (1<<6) /* Watchdog Window Timeout Period bit 2 mask. */ -#define NVM_FUSES_WDWP2_bp 6 /* Watchdog Window Timeout Period bit 2 position. */ -#define NVM_FUSES_WDWP3_bm (1<<7) /* Watchdog Window Timeout Period bit 3 mask. */ -#define NVM_FUSES_WDWP3_bp 7 /* Watchdog Window Timeout Period bit 3 position. */ - -#define NVM_FUSES_WDP_gm 0x0F /* Watchdog Timeout Period group mask. */ -#define NVM_FUSES_WDP_gp 0 /* Watchdog Timeout Period group position. */ -#define NVM_FUSES_WDP0_bm (1<<0) /* Watchdog Timeout Period bit 0 mask. */ -#define NVM_FUSES_WDP0_bp 0 /* Watchdog Timeout Period bit 0 position. */ -#define NVM_FUSES_WDP1_bm (1<<1) /* Watchdog Timeout Period bit 1 mask. */ -#define NVM_FUSES_WDP1_bp 1 /* Watchdog Timeout Period bit 1 position. */ -#define NVM_FUSES_WDP2_bm (1<<2) /* Watchdog Timeout Period bit 2 mask. */ -#define NVM_FUSES_WDP2_bp 2 /* Watchdog Timeout Period bit 2 position. */ -#define NVM_FUSES_WDP3_bm (1<<3) /* Watchdog Timeout Period bit 3 mask. */ -#define NVM_FUSES_WDP3_bp 3 /* Watchdog Timeout Period bit 3 position. */ - -/* NVM_FUSES.FUSEBYTE2 bit masks and bit positions */ -#define NVM_FUSES_DVSDON_bm 0x80 /* Spike Detector Enable bit mask. */ -#define NVM_FUSES_DVSDON_bp 7 /* Spike Detector Enable bit position. */ - -#define NVM_FUSES_BOOTRST_bm 0x40 /* Boot Loader Section Reset Vector bit mask. */ -#define NVM_FUSES_BOOTRST_bp 6 /* Boot Loader Section Reset Vector bit position. */ - -#define NVM_FUSES_TOSCSEL_bm 0x20 /* 32.768kHz Timer Oscillator Pin Selection bit mask. */ -#define NVM_FUSES_TOSCSEL_bp 5 /* 32.768kHz Timer Oscillator Pin Selection bit position. */ - -#define NVM_FUSES_BODPD_gm 0x03 /* BOD Operation in Power-Down Mode group mask. */ -#define NVM_FUSES_BODPD_gp 0 /* BOD Operation in Power-Down Mode group position. */ -#define NVM_FUSES_BODPD0_bm (1<<0) /* BOD Operation in Power-Down Mode bit 0 mask. */ -#define NVM_FUSES_BODPD0_bp 0 /* BOD Operation in Power-Down Mode bit 0 position. */ -#define NVM_FUSES_BODPD1_bm (1<<1) /* BOD Operation in Power-Down Mode bit 1 mask. */ -#define NVM_FUSES_BODPD1_bp 1 /* BOD Operation in Power-Down Mode bit 1 position. */ - -/* NVM_FUSES.FUSEBYTE4 bit masks and bit positions */ -#define NVM_FUSES_RSTDISBL_bm 0x10 /* External Reset Disable bit mask. */ -#define NVM_FUSES_RSTDISBL_bp 4 /* External Reset Disable bit position. */ - -#define NVM_FUSES_SUT_gm 0x0C /* Start-up Time group mask. */ -#define NVM_FUSES_SUT_gp 2 /* Start-up Time group position. */ -#define NVM_FUSES_SUT0_bm (1<<2) /* Start-up Time bit 0 mask. */ -#define NVM_FUSES_SUT0_bp 2 /* Start-up Time bit 0 position. */ -#define NVM_FUSES_SUT1_bm (1<<3) /* Start-up Time bit 1 mask. */ -#define NVM_FUSES_SUT1_bp 3 /* Start-up Time bit 1 position. */ - -#define NVM_FUSES_WDLOCK_bm 0x02 /* Watchdog Timer Lock bit mask. */ -#define NVM_FUSES_WDLOCK_bp 1 /* Watchdog Timer Lock bit position. */ - -/* NVM_FUSES.FUSEBYTE5 bit masks and bit positions */ -#define NVM_FUSES_BODACT_gm 0x30 /* BOD Operation in Active Mode group mask. */ -#define NVM_FUSES_BODACT_gp 4 /* BOD Operation in Active Mode group position. */ -#define NVM_FUSES_BODACT0_bm (1<<4) /* BOD Operation in Active Mode bit 0 mask. */ -#define NVM_FUSES_BODACT0_bp 4 /* BOD Operation in Active Mode bit 0 position. */ -#define NVM_FUSES_BODACT1_bm (1<<5) /* BOD Operation in Active Mode bit 1 mask. */ -#define NVM_FUSES_BODACT1_bp 5 /* BOD Operation in Active Mode bit 1 position. */ - -#define NVM_FUSES_EESAVE_bm 0x08 /* Preserve EEPROM Through Chip Erase bit mask. */ -#define NVM_FUSES_EESAVE_bp 3 /* Preserve EEPROM Through Chip Erase bit position. */ - -#define NVM_FUSES_BODLVL_gm 0x07 /* Brownout Detection Voltage Level group mask. */ -#define NVM_FUSES_BODLVL_gp 0 /* Brownout Detection Voltage Level group position. */ -#define NVM_FUSES_BODLVL0_bm (1<<0) /* Brownout Detection Voltage Level bit 0 mask. */ -#define NVM_FUSES_BODLVL0_bp 0 /* Brownout Detection Voltage Level bit 0 position. */ -#define NVM_FUSES_BODLVL1_bm (1<<1) /* Brownout Detection Voltage Level bit 1 mask. */ -#define NVM_FUSES_BODLVL1_bp 1 /* Brownout Detection Voltage Level bit 1 position. */ -#define NVM_FUSES_BODLVL2_bm (1<<2) /* Brownout Detection Voltage Level bit 2 mask. */ -#define NVM_FUSES_BODLVL2_bp 2 /* Brownout Detection Voltage Level bit 2 position. */ - -/* AC - Analog Comparator */ -/* AC.AC0CTRL bit masks and bit positions */ -#define AC_INTMODE_gm 0xC0 /* Interrupt Mode group mask. */ -#define AC_INTMODE_gp 6 /* Interrupt Mode group position. */ -#define AC_INTMODE0_bm (1<<6) /* Interrupt Mode bit 0 mask. */ -#define AC_INTMODE0_bp 6 /* Interrupt Mode bit 0 position. */ -#define AC_INTMODE1_bm (1<<7) /* Interrupt Mode bit 1 mask. */ -#define AC_INTMODE1_bp 7 /* Interrupt Mode bit 1 position. */ - -#define AC_INTLVL_gm 0x30 /* Interrupt Level group mask. */ -#define AC_INTLVL_gp 4 /* Interrupt Level group position. */ -#define AC_INTLVL0_bm (1<<4) /* Interrupt Level bit 0 mask. */ -#define AC_INTLVL0_bp 4 /* Interrupt Level bit 0 position. */ -#define AC_INTLVL1_bm (1<<5) /* Interrupt Level bit 1 mask. */ -#define AC_INTLVL1_bp 5 /* Interrupt Level bit 1 position. */ - -#define AC_HSMODE_bm 0x08 /* High-speed Mode bit mask. */ -#define AC_HSMODE_bp 3 /* High-speed Mode bit position. */ - -#define AC_HYSMODE_gm 0x06 /* Hysteresis Mode group mask. */ -#define AC_HYSMODE_gp 1 /* Hysteresis Mode group position. */ -#define AC_HYSMODE0_bm (1<<1) /* Hysteresis Mode bit 0 mask. */ -#define AC_HYSMODE0_bp 1 /* Hysteresis Mode bit 0 position. */ -#define AC_HYSMODE1_bm (1<<2) /* Hysteresis Mode bit 1 mask. */ -#define AC_HYSMODE1_bp 2 /* Hysteresis Mode bit 1 position. */ - -#define AC_ENABLE_bm 0x01 /* Enable bit mask. */ -#define AC_ENABLE_bp 0 /* Enable bit position. */ - -/* AC.AC1CTRL bit masks and bit positions */ -/* AC_INTMODE Predefined. */ -/* AC_INTMODE Predefined. */ - -/* AC_INTLVL Predefined. */ -/* AC_INTLVL Predefined. */ - -/* AC_HSMODE Predefined. */ -/* AC_HSMODE Predefined. */ - -/* AC_HYSMODE Predefined. */ -/* AC_HYSMODE Predefined. */ - -/* AC_ENABLE Predefined. */ -/* AC_ENABLE Predefined. */ - -/* AC.AC0MUXCTRL bit masks and bit positions */ -#define AC_MUXPOS_gm 0x38 /* MUX Positive Input group mask. */ -#define AC_MUXPOS_gp 3 /* MUX Positive Input group position. */ -#define AC_MUXPOS0_bm (1<<3) /* MUX Positive Input bit 0 mask. */ -#define AC_MUXPOS0_bp 3 /* MUX Positive Input bit 0 position. */ -#define AC_MUXPOS1_bm (1<<4) /* MUX Positive Input bit 1 mask. */ -#define AC_MUXPOS1_bp 4 /* MUX Positive Input bit 1 position. */ -#define AC_MUXPOS2_bm (1<<5) /* MUX Positive Input bit 2 mask. */ -#define AC_MUXPOS2_bp 5 /* MUX Positive Input bit 2 position. */ - -#define AC_MUXNEG_gm 0x07 /* MUX Negative Input group mask. */ -#define AC_MUXNEG_gp 0 /* MUX Negative Input group position. */ -#define AC_MUXNEG0_bm (1<<0) /* MUX Negative Input bit 0 mask. */ -#define AC_MUXNEG0_bp 0 /* MUX Negative Input bit 0 position. */ -#define AC_MUXNEG1_bm (1<<1) /* MUX Negative Input bit 1 mask. */ -#define AC_MUXNEG1_bp 1 /* MUX Negative Input bit 1 position. */ -#define AC_MUXNEG2_bm (1<<2) /* MUX Negative Input bit 2 mask. */ -#define AC_MUXNEG2_bp 2 /* MUX Negative Input bit 2 position. */ - -/* AC.AC1MUXCTRL bit masks and bit positions */ -/* AC_MUXPOS Predefined. */ -/* AC_MUXPOS Predefined. */ - -/* AC_MUXNEG Predefined. */ -/* AC_MUXNEG Predefined. */ - -/* AC.CTRLA bit masks and bit positions */ -#define AC_AC0OUT_bm 0x01 /* Analog Comparator 0 Output Enable bit mask. */ -#define AC_AC0OUT_bp 0 /* Analog Comparator 0 Output Enable bit position. */ - -/* AC.CTRLB bit masks and bit positions */ -#define AC_SCALEFAC_gm 0x3F /* VCC Voltage Scaler Factor group mask. */ -#define AC_SCALEFAC_gp 0 /* VCC Voltage Scaler Factor group position. */ -#define AC_SCALEFAC0_bm (1<<0) /* VCC Voltage Scaler Factor bit 0 mask. */ -#define AC_SCALEFAC0_bp 0 /* VCC Voltage Scaler Factor bit 0 position. */ -#define AC_SCALEFAC1_bm (1<<1) /* VCC Voltage Scaler Factor bit 1 mask. */ -#define AC_SCALEFAC1_bp 1 /* VCC Voltage Scaler Factor bit 1 position. */ -#define AC_SCALEFAC2_bm (1<<2) /* VCC Voltage Scaler Factor bit 2 mask. */ -#define AC_SCALEFAC2_bp 2 /* VCC Voltage Scaler Factor bit 2 position. */ -#define AC_SCALEFAC3_bm (1<<3) /* VCC Voltage Scaler Factor bit 3 mask. */ -#define AC_SCALEFAC3_bp 3 /* VCC Voltage Scaler Factor bit 3 position. */ -#define AC_SCALEFAC4_bm (1<<4) /* VCC Voltage Scaler Factor bit 4 mask. */ -#define AC_SCALEFAC4_bp 4 /* VCC Voltage Scaler Factor bit 4 position. */ -#define AC_SCALEFAC5_bm (1<<5) /* VCC Voltage Scaler Factor bit 5 mask. */ -#define AC_SCALEFAC5_bp 5 /* VCC Voltage Scaler Factor bit 5 position. */ - -/* AC.WINCTRL bit masks and bit positions */ -#define AC_WEN_bm 0x10 /* Window Mode Enable bit mask. */ -#define AC_WEN_bp 4 /* Window Mode Enable bit position. */ - -#define AC_WINTMODE_gm 0x0C /* Window Interrupt Mode group mask. */ -#define AC_WINTMODE_gp 2 /* Window Interrupt Mode group position. */ -#define AC_WINTMODE0_bm (1<<2) /* Window Interrupt Mode bit 0 mask. */ -#define AC_WINTMODE0_bp 2 /* Window Interrupt Mode bit 0 position. */ -#define AC_WINTMODE1_bm (1<<3) /* Window Interrupt Mode bit 1 mask. */ -#define AC_WINTMODE1_bp 3 /* Window Interrupt Mode bit 1 position. */ - -#define AC_WINTLVL_gm 0x03 /* Window Interrupt Level group mask. */ -#define AC_WINTLVL_gp 0 /* Window Interrupt Level group position. */ -#define AC_WINTLVL0_bm (1<<0) /* Window Interrupt Level bit 0 mask. */ -#define AC_WINTLVL0_bp 0 /* Window Interrupt Level bit 0 position. */ -#define AC_WINTLVL1_bm (1<<1) /* Window Interrupt Level bit 1 mask. */ -#define AC_WINTLVL1_bp 1 /* Window Interrupt Level bit 1 position. */ - -/* AC.STATUS bit masks and bit positions */ -#define AC_WSTATE_gm 0xC0 /* Window Mode State group mask. */ -#define AC_WSTATE_gp 6 /* Window Mode State group position. */ -#define AC_WSTATE0_bm (1<<6) /* Window Mode State bit 0 mask. */ -#define AC_WSTATE0_bp 6 /* Window Mode State bit 0 position. */ -#define AC_WSTATE1_bm (1<<7) /* Window Mode State bit 1 mask. */ -#define AC_WSTATE1_bp 7 /* Window Mode State bit 1 position. */ - -#define AC_AC1STATE_bm 0x20 /* Analog Comparator 1 State bit mask. */ -#define AC_AC1STATE_bp 5 /* Analog Comparator 1 State bit position. */ - -#define AC_AC0STATE_bm 0x10 /* Analog Comparator 0 State bit mask. */ -#define AC_AC0STATE_bp 4 /* Analog Comparator 0 State bit position. */ - -#define AC_WIF_bm 0x04 /* Window Mode Interrupt Flag bit mask. */ -#define AC_WIF_bp 2 /* Window Mode Interrupt Flag bit position. */ - -#define AC_AC1IF_bm 0x02 /* Analog Comparator 1 Interrupt Flag bit mask. */ -#define AC_AC1IF_bp 1 /* Analog Comparator 1 Interrupt Flag bit position. */ - -#define AC_AC0IF_bm 0x01 /* Analog Comparator 0 Interrupt Flag bit mask. */ -#define AC_AC0IF_bp 0 /* Analog Comparator 0 Interrupt Flag bit position. */ - -/* ADC - Analog/Digital Converter */ -/* ADC_CH.CTRL bit masks and bit positions */ -#define ADC_CH_START_bm 0x80 /* Channel Start Conversion bit mask. */ -#define ADC_CH_START_bp 7 /* Channel Start Conversion bit position. */ - -#define ADC_CH_GAIN_gm 0x1C /* Gain Factor group mask. */ -#define ADC_CH_GAIN_gp 2 /* Gain Factor group position. */ -#define ADC_CH_GAIN0_bm (1<<2) /* Gain Factor bit 0 mask. */ -#define ADC_CH_GAIN0_bp 2 /* Gain Factor bit 0 position. */ -#define ADC_CH_GAIN1_bm (1<<3) /* Gain Factor bit 1 mask. */ -#define ADC_CH_GAIN1_bp 3 /* Gain Factor bit 1 position. */ -#define ADC_CH_GAIN2_bm (1<<4) /* Gain Factor bit 2 mask. */ -#define ADC_CH_GAIN2_bp 4 /* Gain Factor bit 2 position. */ - -#define ADC_CH_INPUTMODE_gm 0x03 /* Input Mode Select group mask. */ -#define ADC_CH_INPUTMODE_gp 0 /* Input Mode Select group position. */ -#define ADC_CH_INPUTMODE0_bm (1<<0) /* Input Mode Select bit 0 mask. */ -#define ADC_CH_INPUTMODE0_bp 0 /* Input Mode Select bit 0 position. */ -#define ADC_CH_INPUTMODE1_bm (1<<1) /* Input Mode Select bit 1 mask. */ -#define ADC_CH_INPUTMODE1_bp 1 /* Input Mode Select bit 1 position. */ - -/* ADC_CH.MUXCTRL bit masks and bit positions */ -#define ADC_CH_MUXPOS_gm 0x78 /* MUX selection on Positive ADC input group mask. */ -#define ADC_CH_MUXPOS_gp 3 /* MUX selection on Positive ADC input group position. */ -#define ADC_CH_MUXPOS0_bm (1<<3) /* MUX selection on Positive ADC input bit 0 mask. */ -#define ADC_CH_MUXPOS0_bp 3 /* MUX selection on Positive ADC input bit 0 position. */ -#define ADC_CH_MUXPOS1_bm (1<<4) /* MUX selection on Positive ADC input bit 1 mask. */ -#define ADC_CH_MUXPOS1_bp 4 /* MUX selection on Positive ADC input bit 1 position. */ -#define ADC_CH_MUXPOS2_bm (1<<5) /* MUX selection on Positive ADC input bit 2 mask. */ -#define ADC_CH_MUXPOS2_bp 5 /* MUX selection on Positive ADC input bit 2 position. */ -#define ADC_CH_MUXPOS3_bm (1<<6) /* MUX selection on Positive ADC input bit 3 mask. */ -#define ADC_CH_MUXPOS3_bp 6 /* MUX selection on Positive ADC input bit 3 position. */ - -#define ADC_CH_MUXINT_gm 0x78 /* MUX selection on Internal ADC input group mask. */ -#define ADC_CH_MUXINT_gp 3 /* MUX selection on Internal ADC input group position. */ -#define ADC_CH_MUXINT0_bm (1<<3) /* MUX selection on Internal ADC input bit 0 mask. */ -#define ADC_CH_MUXINT0_bp 3 /* MUX selection on Internal ADC input bit 0 position. */ -#define ADC_CH_MUXINT1_bm (1<<4) /* MUX selection on Internal ADC input bit 1 mask. */ -#define ADC_CH_MUXINT1_bp 4 /* MUX selection on Internal ADC input bit 1 position. */ -#define ADC_CH_MUXINT2_bm (1<<5) /* MUX selection on Internal ADC input bit 2 mask. */ -#define ADC_CH_MUXINT2_bp 5 /* MUX selection on Internal ADC input bit 2 position. */ -#define ADC_CH_MUXINT3_bm (1<<6) /* MUX selection on Internal ADC input bit 3 mask. */ -#define ADC_CH_MUXINT3_bp 6 /* MUX selection on Internal ADC input bit 3 position. */ - -#define ADC_CH_MUXNEG_gm 0x03 /* MUX selection on Negative ADC input group mask. */ -#define ADC_CH_MUXNEG_gp 0 /* MUX selection on Negative ADC input group position. */ -#define ADC_CH_MUXNEG0_bm (1<<0) /* MUX selection on Negative ADC input bit 0 mask. */ -#define ADC_CH_MUXNEG0_bp 0 /* MUX selection on Negative ADC input bit 0 position. */ -#define ADC_CH_MUXNEG1_bm (1<<1) /* MUX selection on Negative ADC input bit 1 mask. */ -#define ADC_CH_MUXNEG1_bp 1 /* MUX selection on Negative ADC input bit 1 position. */ - -/* ADC_CH.INTCTRL bit masks and bit positions */ -#define ADC_CH_INTMODE_gm 0x0C /* Interrupt Mode group mask. */ -#define ADC_CH_INTMODE_gp 2 /* Interrupt Mode group position. */ -#define ADC_CH_INTMODE0_bm (1<<2) /* Interrupt Mode bit 0 mask. */ -#define ADC_CH_INTMODE0_bp 2 /* Interrupt Mode bit 0 position. */ -#define ADC_CH_INTMODE1_bm (1<<3) /* Interrupt Mode bit 1 mask. */ -#define ADC_CH_INTMODE1_bp 3 /* Interrupt Mode bit 1 position. */ - -#define ADC_CH_INTLVL_gm 0x03 /* Interrupt Level group mask. */ -#define ADC_CH_INTLVL_gp 0 /* Interrupt Level group position. */ -#define ADC_CH_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */ -#define ADC_CH_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */ -#define ADC_CH_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ -#define ADC_CH_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */ - -/* ADC_CH.INTFLAGS bit masks and bit positions */ -#define ADC_CH_CHIF_bm 0x01 /* Channel Interrupt Flag bit mask. */ -#define ADC_CH_CHIF_bp 0 /* Channel Interrupt Flag bit position. */ - -/* ADC_CH.SCAN bit masks and bit positions */ -#define ADC_CH_OFFSET_gm 0xF0 /* Positive MUX setting offset group mask. */ -#define ADC_CH_OFFSET_gp 4 /* Positive MUX setting offset group position. */ -#define ADC_CH_OFFSET0_bm (1<<4) /* Positive MUX setting offset bit 0 mask. */ -#define ADC_CH_OFFSET0_bp 4 /* Positive MUX setting offset bit 0 position. */ -#define ADC_CH_OFFSET1_bm (1<<5) /* Positive MUX setting offset bit 1 mask. */ -#define ADC_CH_OFFSET1_bp 5 /* Positive MUX setting offset bit 1 position. */ -#define ADC_CH_OFFSET2_bm (1<<6) /* Positive MUX setting offset bit 2 mask. */ -#define ADC_CH_OFFSET2_bp 6 /* Positive MUX setting offset bit 2 position. */ -#define ADC_CH_OFFSET3_bm (1<<7) /* Positive MUX setting offset bit 3 mask. */ -#define ADC_CH_OFFSET3_bp 7 /* Positive MUX setting offset bit 3 position. */ - -#define ADC_CH_SCANNUM_gm 0x0F /* Number of Channels included in scan group mask. */ -#define ADC_CH_SCANNUM_gp 0 /* Number of Channels included in scan group position. */ -#define ADC_CH_SCANNUM0_bm (1<<0) /* Number of Channels included in scan bit 0 mask. */ -#define ADC_CH_SCANNUM0_bp 0 /* Number of Channels included in scan bit 0 position. */ -#define ADC_CH_SCANNUM1_bm (1<<1) /* Number of Channels included in scan bit 1 mask. */ -#define ADC_CH_SCANNUM1_bp 1 /* Number of Channels included in scan bit 1 position. */ -#define ADC_CH_SCANNUM2_bm (1<<2) /* Number of Channels included in scan bit 2 mask. */ -#define ADC_CH_SCANNUM2_bp 2 /* Number of Channels included in scan bit 2 position. */ -#define ADC_CH_SCANNUM3_bm (1<<3) /* Number of Channels included in scan bit 3 mask. */ -#define ADC_CH_SCANNUM3_bp 3 /* Number of Channels included in scan bit 3 position. */ - -/* ADC.CTRLA bit masks and bit positions */ -#define ADC_CH0START_bm 0x04 /* Channel 0 Start Conversion bit mask. */ -#define ADC_CH0START_bp 2 /* Channel 0 Start Conversion bit position. */ - -#define ADC_FLUSH_bm 0x02 /* ADC Flush bit mask. */ -#define ADC_FLUSH_bp 1 /* ADC Flush bit position. */ - -#define ADC_ENABLE_bm 0x01 /* Enable ADC bit mask. */ -#define ADC_ENABLE_bp 0 /* Enable ADC bit position. */ - -/* ADC.CTRLB bit masks and bit positions */ -#define ADC_CURRLIMIT_gm 0x60 /* Current Limitation group mask. */ -#define ADC_CURRLIMIT_gp 5 /* Current Limitation group position. */ -#define ADC_CURRLIMIT0_bm (1<<5) /* Current Limitation bit 0 mask. */ -#define ADC_CURRLIMIT0_bp 5 /* Current Limitation bit 0 position. */ -#define ADC_CURRLIMIT1_bm (1<<6) /* Current Limitation bit 1 mask. */ -#define ADC_CURRLIMIT1_bp 6 /* Current Limitation bit 1 position. */ - -#define ADC_CONMODE_bm 0x10 /* Conversion Mode bit mask. */ -#define ADC_CONMODE_bp 4 /* Conversion Mode bit position. */ - -#define ADC_FREERUN_bm 0x08 /* Free Running Mode Enable bit mask. */ -#define ADC_FREERUN_bp 3 /* Free Running Mode Enable bit position. */ - -#define ADC_RESOLUTION_gm 0x06 /* Result Resolution group mask. */ -#define ADC_RESOLUTION_gp 1 /* Result Resolution group position. */ -#define ADC_RESOLUTION0_bm (1<<1) /* Result Resolution bit 0 mask. */ -#define ADC_RESOLUTION0_bp 1 /* Result Resolution bit 0 position. */ -#define ADC_RESOLUTION1_bm (1<<2) /* Result Resolution bit 1 mask. */ -#define ADC_RESOLUTION1_bp 2 /* Result Resolution bit 1 position. */ - -/* ADC.REFCTRL bit masks and bit positions */ -#define ADC_REFSEL_gm 0x70 /* Reference Selection group mask. */ -#define ADC_REFSEL_gp 4 /* Reference Selection group position. */ -#define ADC_REFSEL0_bm (1<<4) /* Reference Selection bit 0 mask. */ -#define ADC_REFSEL0_bp 4 /* Reference Selection bit 0 position. */ -#define ADC_REFSEL1_bm (1<<5) /* Reference Selection bit 1 mask. */ -#define ADC_REFSEL1_bp 5 /* Reference Selection bit 1 position. */ -#define ADC_REFSEL2_bm (1<<6) /* Reference Selection bit 2 mask. */ -#define ADC_REFSEL2_bp 6 /* Reference Selection bit 2 position. */ - -#define ADC_BANDGAP_bm 0x02 /* Bandgap enable bit mask. */ -#define ADC_BANDGAP_bp 1 /* Bandgap enable bit position. */ - -#define ADC_TEMPREF_bm 0x01 /* Temperature Reference Enable bit mask. */ -#define ADC_TEMPREF_bp 0 /* Temperature Reference Enable bit position. */ - -/* ADC.EVCTRL bit masks and bit positions */ -#define ADC_EVSEL_gm 0x18 /* Event Input Select group mask. */ -#define ADC_EVSEL_gp 3 /* Event Input Select group position. */ -#define ADC_EVSEL0_bm (1<<3) /* Event Input Select bit 0 mask. */ -#define ADC_EVSEL0_bp 3 /* Event Input Select bit 0 position. */ -#define ADC_EVSEL1_bm (1<<4) /* Event Input Select bit 1 mask. */ -#define ADC_EVSEL1_bp 4 /* Event Input Select bit 1 position. */ - -#define ADC_EVACT_gm 0x07 /* Event Action Select group mask. */ -#define ADC_EVACT_gp 0 /* Event Action Select group position. */ -#define ADC_EVACT0_bm (1<<0) /* Event Action Select bit 0 mask. */ -#define ADC_EVACT0_bp 0 /* Event Action Select bit 0 position. */ -#define ADC_EVACT1_bm (1<<1) /* Event Action Select bit 1 mask. */ -#define ADC_EVACT1_bp 1 /* Event Action Select bit 1 position. */ -#define ADC_EVACT2_bm (1<<2) /* Event Action Select bit 2 mask. */ -#define ADC_EVACT2_bp 2 /* Event Action Select bit 2 position. */ - -/* ADC.PRESCALER bit masks and bit positions */ -#define ADC_PRESCALER_gm 0x07 /* Clock Prescaler Selection group mask. */ -#define ADC_PRESCALER_gp 0 /* Clock Prescaler Selection group position. */ -#define ADC_PRESCALER0_bm (1<<0) /* Clock Prescaler Selection bit 0 mask. */ -#define ADC_PRESCALER0_bp 0 /* Clock Prescaler Selection bit 0 position. */ -#define ADC_PRESCALER1_bm (1<<1) /* Clock Prescaler Selection bit 1 mask. */ -#define ADC_PRESCALER1_bp 1 /* Clock Prescaler Selection bit 1 position. */ -#define ADC_PRESCALER2_bm (1<<2) /* Clock Prescaler Selection bit 2 mask. */ -#define ADC_PRESCALER2_bp 2 /* Clock Prescaler Selection bit 2 position. */ - -/* ADC.INTFLAGS bit masks and bit positions */ -#define ADC_CH0IF_bm 0x01 /* Channel 0 Interrupt Flag bit mask. */ -#define ADC_CH0IF_bp 0 /* Channel 0 Interrupt Flag bit position. */ - -/* RTC - Real-Time Counter */ -/* RTC.CTRL bit masks and bit positions */ -#define RTC_PRESCALER_gm 0x07 /* Prescaling Factor group mask. */ -#define RTC_PRESCALER_gp 0 /* Prescaling Factor group position. */ -#define RTC_PRESCALER0_bm (1<<0) /* Prescaling Factor bit 0 mask. */ -#define RTC_PRESCALER0_bp 0 /* Prescaling Factor bit 0 position. */ -#define RTC_PRESCALER1_bm (1<<1) /* Prescaling Factor bit 1 mask. */ -#define RTC_PRESCALER1_bp 1 /* Prescaling Factor bit 1 position. */ -#define RTC_PRESCALER2_bm (1<<2) /* Prescaling Factor bit 2 mask. */ -#define RTC_PRESCALER2_bp 2 /* Prescaling Factor bit 2 position. */ - -/* RTC.STATUS bit masks and bit positions */ -#define RTC_SYNCBUSY_bm 0x01 /* Synchronization Busy Flag bit mask. */ -#define RTC_SYNCBUSY_bp 0 /* Synchronization Busy Flag bit position. */ - -/* RTC.INTCTRL bit masks and bit positions */ -#define RTC_COMPINTLVL_gm 0x0C /* Compare Match Interrupt Level group mask. */ -#define RTC_COMPINTLVL_gp 2 /* Compare Match Interrupt Level group position. */ -#define RTC_COMPINTLVL0_bm (1<<2) /* Compare Match Interrupt Level bit 0 mask. */ -#define RTC_COMPINTLVL0_bp 2 /* Compare Match Interrupt Level bit 0 position. */ -#define RTC_COMPINTLVL1_bm (1<<3) /* Compare Match Interrupt Level bit 1 mask. */ -#define RTC_COMPINTLVL1_bp 3 /* Compare Match Interrupt Level bit 1 position. */ - -#define RTC_OVFINTLVL_gm 0x03 /* Overflow Interrupt Level group mask. */ -#define RTC_OVFINTLVL_gp 0 /* Overflow Interrupt Level group position. */ -#define RTC_OVFINTLVL0_bm (1<<0) /* Overflow Interrupt Level bit 0 mask. */ -#define RTC_OVFINTLVL0_bp 0 /* Overflow Interrupt Level bit 0 position. */ -#define RTC_OVFINTLVL1_bm (1<<1) /* Overflow Interrupt Level bit 1 mask. */ -#define RTC_OVFINTLVL1_bp 1 /* Overflow Interrupt Level bit 1 position. */ - -/* RTC.INTFLAGS bit masks and bit positions */ -#define RTC_COMPIF_bm 0x02 /* Compare Match Interrupt Flag bit mask. */ -#define RTC_COMPIF_bp 1 /* Compare Match Interrupt Flag bit position. */ - -#define RTC_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ -#define RTC_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ - -/* TWI - Two-Wire Interface */ -/* TWI_MASTER.CTRLA bit masks and bit positions */ -#define TWI_MASTER_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ -#define TWI_MASTER_INTLVL_gp 6 /* Interrupt Level group position. */ -#define TWI_MASTER_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ -#define TWI_MASTER_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ -#define TWI_MASTER_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ -#define TWI_MASTER_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ - -#define TWI_MASTER_RIEN_bm 0x20 /* Read Interrupt Enable bit mask. */ -#define TWI_MASTER_RIEN_bp 5 /* Read Interrupt Enable bit position. */ - -#define TWI_MASTER_WIEN_bm 0x10 /* Write Interrupt Enable bit mask. */ -#define TWI_MASTER_WIEN_bp 4 /* Write Interrupt Enable bit position. */ - -#define TWI_MASTER_ENABLE_bm 0x08 /* Enable TWI Master bit mask. */ -#define TWI_MASTER_ENABLE_bp 3 /* Enable TWI Master bit position. */ - -/* TWI_MASTER.CTRLB bit masks and bit positions */ -#define TWI_MASTER_TIMEOUT_gm 0x0C /* Inactive Bus Tisdahmeout group mask. */ -#define TWI_MASTER_TIMEOUT_gp 2 /* Inactive Bus Tisdahmeout group position. */ -#define TWI_MASTER_TIMEOUT0_bm (1<<2) /* Inactive Bus Tisdahmeout bit 0 mask. */ -#define TWI_MASTER_TIMEOUT0_bp 2 /* Inactive Bus Tisdahmeout bit 0 position. */ -#define TWI_MASTER_TIMEOUT1_bm (1<<3) /* Inactive Bus Tisdahmeout bit 1 mask. */ -#define TWI_MASTER_TIMEOUT1_bp 3 /* Inactive Bus Tisdahmeout bit 1 position. */ - -#define TWI_MASTER_QCEN_bm 0x02 /* Quick Command Enable bit mask. */ -#define TWI_MASTER_QCEN_bp 1 /* Quick Command Enable bit position. */ - -#define TWI_MASTER_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ -#define TWI_MASTER_SMEN_bp 0 /* Smart Mode Enable bit position. */ - -/* TWI_MASTER.CTRLC bit masks and bit positions */ -#define TWI_MASTER_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ -#define TWI_MASTER_ACKACT_bp 2 /* Acknowledge Action bit position. */ - -#define TWI_MASTER_CMD_gm 0x03 /* Command group mask. */ -#define TWI_MASTER_CMD_gp 0 /* Command group position. */ -#define TWI_MASTER_CMD0_bm (1<<0) /* Command bit 0 mask. */ -#define TWI_MASTER_CMD0_bp 0 /* Command bit 0 position. */ -#define TWI_MASTER_CMD1_bm (1<<1) /* Command bit 1 mask. */ -#define TWI_MASTER_CMD1_bp 1 /* Command bit 1 position. */ - -/* TWI_MASTER.STATUS bit masks and bit positions */ -#define TWI_MASTER_RIF_bm 0x80 /* Read Interrupt Flag bit mask. */ -#define TWI_MASTER_RIF_bp 7 /* Read Interrupt Flag bit position. */ - -#define TWI_MASTER_WIF_bm 0x40 /* Write Interrupt Flag bit mask. */ -#define TWI_MASTER_WIF_bp 6 /* Write Interrupt Flag bit position. */ - -#define TWI_MASTER_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ -#define TWI_MASTER_CLKHOLD_bp 5 /* Clock Hold bit position. */ - -#define TWI_MASTER_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ -#define TWI_MASTER_RXACK_bp 4 /* Received Acknowledge bit position. */ - -#define TWI_MASTER_ARBLOST_bm 0x08 /* Arbitration Lost bit mask. */ -#define TWI_MASTER_ARBLOST_bp 3 /* Arbitration Lost bit position. */ - -#define TWI_MASTER_BUSERR_bm 0x04 /* Bus Error bit mask. */ -#define TWI_MASTER_BUSERR_bp 2 /* Bus Error bit position. */ - -#define TWI_MASTER_BUSSTATE_gm 0x03 /* Bus State group mask. */ -#define TWI_MASTER_BUSSTATE_gp 0 /* Bus State group position. */ -#define TWI_MASTER_BUSSTATE0_bm (1<<0) /* Bus State bit 0 mask. */ -#define TWI_MASTER_BUSSTATE0_bp 0 /* Bus State bit 0 position. */ -#define TWI_MASTER_BUSSTATE1_bm (1<<1) /* Bus State bit 1 mask. */ -#define TWI_MASTER_BUSSTATE1_bp 1 /* Bus State bit 1 position. */ - -/* TWI_SLAVE.CTRLA bit masks and bit positions */ -#define TWI_SLAVE_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ -#define TWI_SLAVE_INTLVL_gp 6 /* Interrupt Level group position. */ -#define TWI_SLAVE_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ -#define TWI_SLAVE_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ -#define TWI_SLAVE_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ -#define TWI_SLAVE_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ - -#define TWI_SLAVE_DIEN_bm 0x20 /* Data Interrupt Enable bit mask. */ -#define TWI_SLAVE_DIEN_bp 5 /* Data Interrupt Enable bit position. */ - -#define TWI_SLAVE_APIEN_bm 0x10 /* Address/Stop Interrupt Enable bit mask. */ -#define TWI_SLAVE_APIEN_bp 4 /* Address/Stop Interrupt Enable bit position. */ - -#define TWI_SLAVE_ENABLE_bm 0x08 /* Enable TWI Slave bit mask. */ -#define TWI_SLAVE_ENABLE_bp 3 /* Enable TWI Slave bit position. */ - -#define TWI_SLAVE_PIEN_bm 0x04 /* Stop Interrupt Enable bit mask. */ -#define TWI_SLAVE_PIEN_bp 2 /* Stop Interrupt Enable bit position. */ - -#define TWI_SLAVE_PMEN_bm 0x02 /* Promiscuous Mode Enable bit mask. */ -#define TWI_SLAVE_PMEN_bp 1 /* Promiscuous Mode Enable bit position. */ - -#define TWI_SLAVE_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ -#define TWI_SLAVE_SMEN_bp 0 /* Smart Mode Enable bit position. */ - -/* TWI_SLAVE.CTRLB bit masks and bit positions */ -#define TWI_SLAVE_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ -#define TWI_SLAVE_ACKACT_bp 2 /* Acknowledge Action bit position. */ - -#define TWI_SLAVE_CMD_gm 0x03 /* Command group mask. */ -#define TWI_SLAVE_CMD_gp 0 /* Command group position. */ -#define TWI_SLAVE_CMD0_bm (1<<0) /* Command bit 0 mask. */ -#define TWI_SLAVE_CMD0_bp 0 /* Command bit 0 position. */ -#define TWI_SLAVE_CMD1_bm (1<<1) /* Command bit 1 mask. */ -#define TWI_SLAVE_CMD1_bp 1 /* Command bit 1 position. */ - -/* TWI_SLAVE.STATUS bit masks and bit positions */ -#define TWI_SLAVE_DIF_bm 0x80 /* Data Interrupt Flag bit mask. */ -#define TWI_SLAVE_DIF_bp 7 /* Data Interrupt Flag bit position. */ - -#define TWI_SLAVE_APIF_bm 0x40 /* Address/Stop Interrupt Flag bit mask. */ -#define TWI_SLAVE_APIF_bp 6 /* Address/Stop Interrupt Flag bit position. */ - -#define TWI_SLAVE_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ -#define TWI_SLAVE_CLKHOLD_bp 5 /* Clock Hold bit position. */ - -#define TWI_SLAVE_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ -#define TWI_SLAVE_RXACK_bp 4 /* Received Acknowledge bit position. */ - -#define TWI_SLAVE_COLL_bm 0x08 /* Collision bit mask. */ -#define TWI_SLAVE_COLL_bp 3 /* Collision bit position. */ - -#define TWI_SLAVE_BUSERR_bm 0x04 /* Bus Error bit mask. */ -#define TWI_SLAVE_BUSERR_bp 2 /* Bus Error bit position. */ - -#define TWI_SLAVE_DIR_bm 0x02 /* Read/Write Direction bit mask. */ -#define TWI_SLAVE_DIR_bp 1 /* Read/Write Direction bit position. */ - -#define TWI_SLAVE_AP_bm 0x01 /* Slave Address or Stop bit mask. */ -#define TWI_SLAVE_AP_bp 0 /* Slave Address or Stop bit position. */ - -/* TWI_SLAVE.ADDRMASK bit masks and bit positions */ -#define TWI_SLAVE_ADDRMASK_gm 0xFE /* Address Mask group mask. */ -#define TWI_SLAVE_ADDRMASK_gp 1 /* Address Mask group position. */ -#define TWI_SLAVE_ADDRMASK0_bm (1<<1) /* Address Mask bit 0 mask. */ -#define TWI_SLAVE_ADDRMASK0_bp 1 /* Address Mask bit 0 position. */ -#define TWI_SLAVE_ADDRMASK1_bm (1<<2) /* Address Mask bit 1 mask. */ -#define TWI_SLAVE_ADDRMASK1_bp 2 /* Address Mask bit 1 position. */ -#define TWI_SLAVE_ADDRMASK2_bm (1<<3) /* Address Mask bit 2 mask. */ -#define TWI_SLAVE_ADDRMASK2_bp 3 /* Address Mask bit 2 position. */ -#define TWI_SLAVE_ADDRMASK3_bm (1<<4) /* Address Mask bit 3 mask. */ -#define TWI_SLAVE_ADDRMASK3_bp 4 /* Address Mask bit 3 position. */ -#define TWI_SLAVE_ADDRMASK4_bm (1<<5) /* Address Mask bit 4 mask. */ -#define TWI_SLAVE_ADDRMASK4_bp 5 /* Address Mask bit 4 position. */ -#define TWI_SLAVE_ADDRMASK5_bm (1<<6) /* Address Mask bit 5 mask. */ -#define TWI_SLAVE_ADDRMASK5_bp 6 /* Address Mask bit 5 position. */ -#define TWI_SLAVE_ADDRMASK6_bm (1<<7) /* Address Mask bit 6 mask. */ -#define TWI_SLAVE_ADDRMASK6_bp 7 /* Address Mask bit 6 position. */ - -#define TWI_SLAVE_ADDREN_bm 0x01 /* Address Enable bit mask. */ -#define TWI_SLAVE_ADDREN_bp 0 /* Address Enable bit position. */ - -/* TWI.CTRL bit masks and bit positions */ -#define TWI_SDAHOLD_gm 0x06 /* SDA Hold Time Enable group mask. */ -#define TWI_SDAHOLD_gp 1 /* SDA Hold Time Enable group position. */ -#define TWI_SDAHOLD0_bm (1<<1) /* SDA Hold Time Enable bit 0 mask. */ -#define TWI_SDAHOLD0_bp 1 /* SDA Hold Time Enable bit 0 position. */ -#define TWI_SDAHOLD1_bm (1<<2) /* SDA Hold Time Enable bit 1 mask. */ -#define TWI_SDAHOLD1_bp 2 /* SDA Hold Time Enable bit 1 position. */ - -#define TWI_EDIEN_bm 0x01 /* External Driver Interface Enable bit mask. */ -#define TWI_EDIEN_bp 0 /* External Driver Interface Enable bit position. */ - -/* PORT - Port Configuration */ -/* PORTCFG.VPCTRLA bit masks and bit positions */ -#define PORTCFG_VP1MAP_gm 0xF0 /* Virtual Port 1 Mapping group mask. */ -#define PORTCFG_VP1MAP_gp 4 /* Virtual Port 1 Mapping group position. */ -#define PORTCFG_VP1MAP0_bm (1<<4) /* Virtual Port 1 Mapping bit 0 mask. */ -#define PORTCFG_VP1MAP0_bp 4 /* Virtual Port 1 Mapping bit 0 position. */ -#define PORTCFG_VP1MAP1_bm (1<<5) /* Virtual Port 1 Mapping bit 1 mask. */ -#define PORTCFG_VP1MAP1_bp 5 /* Virtual Port 1 Mapping bit 1 position. */ -#define PORTCFG_VP1MAP2_bm (1<<6) /* Virtual Port 1 Mapping bit 2 mask. */ -#define PORTCFG_VP1MAP2_bp 6 /* Virtual Port 1 Mapping bit 2 position. */ -#define PORTCFG_VP1MAP3_bm (1<<7) /* Virtual Port 1 Mapping bit 3 mask. */ -#define PORTCFG_VP1MAP3_bp 7 /* Virtual Port 1 Mapping bit 3 position. */ - -#define PORTCFG_VP0MAP_gm 0x0F /* Virtual Port 0 Mapping group mask. */ -#define PORTCFG_VP0MAP_gp 0 /* Virtual Port 0 Mapping group position. */ -#define PORTCFG_VP0MAP0_bm (1<<0) /* Virtual Port 0 Mapping bit 0 mask. */ -#define PORTCFG_VP0MAP0_bp 0 /* Virtual Port 0 Mapping bit 0 position. */ -#define PORTCFG_VP0MAP1_bm (1<<1) /* Virtual Port 0 Mapping bit 1 mask. */ -#define PORTCFG_VP0MAP1_bp 1 /* Virtual Port 0 Mapping bit 1 position. */ -#define PORTCFG_VP0MAP2_bm (1<<2) /* Virtual Port 0 Mapping bit 2 mask. */ -#define PORTCFG_VP0MAP2_bp 2 /* Virtual Port 0 Mapping bit 2 position. */ -#define PORTCFG_VP0MAP3_bm (1<<3) /* Virtual Port 0 Mapping bit 3 mask. */ -#define PORTCFG_VP0MAP3_bp 3 /* Virtual Port 0 Mapping bit 3 position. */ - -/* PORTCFG.VPCTRLB bit masks and bit positions */ -#define PORTCFG_VP3MAP_gm 0xF0 /* Virtual Port 3 Mapping group mask. */ -#define PORTCFG_VP3MAP_gp 4 /* Virtual Port 3 Mapping group position. */ -#define PORTCFG_VP3MAP0_bm (1<<4) /* Virtual Port 3 Mapping bit 0 mask. */ -#define PORTCFG_VP3MAP0_bp 4 /* Virtual Port 3 Mapping bit 0 position. */ -#define PORTCFG_VP3MAP1_bm (1<<5) /* Virtual Port 3 Mapping bit 1 mask. */ -#define PORTCFG_VP3MAP1_bp 5 /* Virtual Port 3 Mapping bit 1 position. */ -#define PORTCFG_VP3MAP2_bm (1<<6) /* Virtual Port 3 Mapping bit 2 mask. */ -#define PORTCFG_VP3MAP2_bp 6 /* Virtual Port 3 Mapping bit 2 position. */ -#define PORTCFG_VP3MAP3_bm (1<<7) /* Virtual Port 3 Mapping bit 3 mask. */ -#define PORTCFG_VP3MAP3_bp 7 /* Virtual Port 3 Mapping bit 3 position. */ - -#define PORTCFG_VP2MAP_gm 0x0F /* Virtual Port 2 Mapping group mask. */ -#define PORTCFG_VP2MAP_gp 0 /* Virtual Port 2 Mapping group position. */ -#define PORTCFG_VP2MAP0_bm (1<<0) /* Virtual Port 2 Mapping bit 0 mask. */ -#define PORTCFG_VP2MAP0_bp 0 /* Virtual Port 2 Mapping bit 0 position. */ -#define PORTCFG_VP2MAP1_bm (1<<1) /* Virtual Port 2 Mapping bit 1 mask. */ -#define PORTCFG_VP2MAP1_bp 1 /* Virtual Port 2 Mapping bit 1 position. */ -#define PORTCFG_VP2MAP2_bm (1<<2) /* Virtual Port 2 Mapping bit 2 mask. */ -#define PORTCFG_VP2MAP2_bp 2 /* Virtual Port 2 Mapping bit 2 position. */ -#define PORTCFG_VP2MAP3_bm (1<<3) /* Virtual Port 2 Mapping bit 3 mask. */ -#define PORTCFG_VP2MAP3_bp 3 /* Virtual Port 2 Mapping bit 3 position. */ - -/* PORTCFG.CLKEVOUT bit masks and bit positions */ -#define PORTCFG_CLKOUT_gm 0x03 /* Clock Output Port group mask. */ -#define PORTCFG_CLKOUT_gp 0 /* Clock Output Port group position. */ -#define PORTCFG_CLKOUT0_bm (1<<0) /* Clock Output Port bit 0 mask. */ -#define PORTCFG_CLKOUT0_bp 0 /* Clock Output Port bit 0 position. */ -#define PORTCFG_CLKOUT1_bm (1<<1) /* Clock Output Port bit 1 mask. */ -#define PORTCFG_CLKOUT1_bp 1 /* Clock Output Port bit 1 position. */ - -#define PORTCFG_EVOUT_gm 0x30 /* Event Output Port group mask. */ -#define PORTCFG_EVOUT_gp 4 /* Event Output Port group position. */ -#define PORTCFG_EVOUT0_bm (1<<4) /* Event Output Port bit 0 mask. */ -#define PORTCFG_EVOUT0_bp 4 /* Event Output Port bit 0 position. */ -#define PORTCFG_EVOUT1_bm (1<<5) /* Event Output Port bit 1 mask. */ -#define PORTCFG_EVOUT1_bp 5 /* Event Output Port bit 1 position. */ - -/* VPORT.INTFLAGS bit masks and bit positions */ -#define VPORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ -#define VPORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ - -#define VPORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ -#define VPORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ - -/* PORT.INTCTRL bit masks and bit positions */ -#define PORT_INT1LVL_gm 0x0C /* Port Interrupt 1 Level group mask. */ -#define PORT_INT1LVL_gp 2 /* Port Interrupt 1 Level group position. */ -#define PORT_INT1LVL0_bm (1<<2) /* Port Interrupt 1 Level bit 0 mask. */ -#define PORT_INT1LVL0_bp 2 /* Port Interrupt 1 Level bit 0 position. */ -#define PORT_INT1LVL1_bm (1<<3) /* Port Interrupt 1 Level bit 1 mask. */ -#define PORT_INT1LVL1_bp 3 /* Port Interrupt 1 Level bit 1 position. */ - -#define PORT_INT0LVL_gm 0x03 /* Port Interrupt 0 Level group mask. */ -#define PORT_INT0LVL_gp 0 /* Port Interrupt 0 Level group position. */ -#define PORT_INT0LVL0_bm (1<<0) /* Port Interrupt 0 Level bit 0 mask. */ -#define PORT_INT0LVL0_bp 0 /* Port Interrupt 0 Level bit 0 position. */ -#define PORT_INT0LVL1_bm (1<<1) /* Port Interrupt 0 Level bit 1 mask. */ -#define PORT_INT0LVL1_bp 1 /* Port Interrupt 0 Level bit 1 position. */ - -/* PORT.INTFLAGS bit masks and bit positions */ -#define PORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ -#define PORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ - -#define PORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ -#define PORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ - -/* PORT.REMAP bit masks and bit positions */ -#define PORT_SPI_bm 0x20 /* SPI Remap bit mask. */ -#define PORT_SPI_bp 5 /* SPI Remap bit position. */ - -#define PORT_USART0_bm 0x10 /* USART0 Remap bit mask. */ -#define PORT_USART0_bp 4 /* USART0 Remap bit position. */ - -#define PORT_TC0D_bm 0x08 /* Timer/Counter 0 Output Compare D bit mask. */ -#define PORT_TC0D_bp 3 /* Timer/Counter 0 Output Compare D bit position. */ - -#define PORT_TC0C_bm 0x04 /* Timer/Counter 0 Output Compare C bit mask. */ -#define PORT_TC0C_bp 2 /* Timer/Counter 0 Output Compare C bit position. */ - -#define PORT_TC0B_bm 0x02 /* Timer/Counter 0 Output Compare B bit mask. */ -#define PORT_TC0B_bp 1 /* Timer/Counter 0 Output Compare B bit position. */ - -#define PORT_TC0A_bm 0x01 /* Timer/Counter 0 Output Compare A bit mask. */ -#define PORT_TC0A_bp 0 /* Timer/Counter 0 Output Compare A bit position. */ - -/* PORT.PIN0CTRL bit masks and bit positions */ -#define PORT_SRLEN_bm 0x80 /* Slew Rate Enable bit mask. */ -#define PORT_SRLEN_bp 7 /* Slew Rate Enable bit position. */ - -#define PORT_INVEN_bm 0x40 /* Inverted I/O Enable bit mask. */ -#define PORT_INVEN_bp 6 /* Inverted I/O Enable bit position. */ - -#define PORT_OPC_gm 0x38 /* Output/Pull Configuration group mask. */ -#define PORT_OPC_gp 3 /* Output/Pull Configuration group position. */ -#define PORT_OPC0_bm (1<<3) /* Output/Pull Configuration bit 0 mask. */ -#define PORT_OPC0_bp 3 /* Output/Pull Configuration bit 0 position. */ -#define PORT_OPC1_bm (1<<4) /* Output/Pull Configuration bit 1 mask. */ -#define PORT_OPC1_bp 4 /* Output/Pull Configuration bit 1 position. */ -#define PORT_OPC2_bm (1<<5) /* Output/Pull Configuration bit 2 mask. */ -#define PORT_OPC2_bp 5 /* Output/Pull Configuration bit 2 position. */ - -#define PORT_ISC_gm 0x07 /* Input/Sense Configuration group mask. */ -#define PORT_ISC_gp 0 /* Input/Sense Configuration group position. */ -#define PORT_ISC0_bm (1<<0) /* Input/Sense Configuration bit 0 mask. */ -#define PORT_ISC0_bp 0 /* Input/Sense Configuration bit 0 position. */ -#define PORT_ISC1_bm (1<<1) /* Input/Sense Configuration bit 1 mask. */ -#define PORT_ISC1_bp 1 /* Input/Sense Configuration bit 1 position. */ -#define PORT_ISC2_bm (1<<2) /* Input/Sense Configuration bit 2 mask. */ -#define PORT_ISC2_bp 2 /* Input/Sense Configuration bit 2 position. */ - -/* PORT.PIN1CTRL bit masks and bit positions */ -/* PORT_SRLEN Predefined. */ -/* PORT_SRLEN Predefined. */ - -/* PORT_INVEN Predefined. */ -/* PORT_INVEN Predefined. */ - -/* PORT_OPC Predefined. */ -/* PORT_OPC Predefined. */ - -/* PORT_ISC Predefined. */ -/* PORT_ISC Predefined. */ - -/* PORT.PIN2CTRL bit masks and bit positions */ -/* PORT_SRLEN Predefined. */ -/* PORT_SRLEN Predefined. */ - -/* PORT_INVEN Predefined. */ -/* PORT_INVEN Predefined. */ - -/* PORT_OPC Predefined. */ -/* PORT_OPC Predefined. */ - -/* PORT_ISC Predefined. */ -/* PORT_ISC Predefined. */ - -/* PORT.PIN3CTRL bit masks and bit positions */ -/* PORT_SRLEN Predefined. */ -/* PORT_SRLEN Predefined. */ - -/* PORT_INVEN Predefined. */ -/* PORT_INVEN Predefined. */ - -/* PORT_OPC Predefined. */ -/* PORT_OPC Predefined. */ - -/* PORT_ISC Predefined. */ -/* PORT_ISC Predefined. */ - -/* PORT.PIN4CTRL bit masks and bit positions */ -/* PORT_SRLEN Predefined. */ -/* PORT_SRLEN Predefined. */ - -/* PORT_INVEN Predefined. */ -/* PORT_INVEN Predefined. */ - -/* PORT_OPC Predefined. */ -/* PORT_OPC Predefined. */ - -/* PORT_ISC Predefined. */ -/* PORT_ISC Predefined. */ - -/* PORT.PIN5CTRL bit masks and bit positions */ -/* PORT_SRLEN Predefined. */ -/* PORT_SRLEN Predefined. */ - -/* PORT_INVEN Predefined. */ -/* PORT_INVEN Predefined. */ - -/* PORT_OPC Predefined. */ -/* PORT_OPC Predefined. */ - -/* PORT_ISC Predefined. */ -/* PORT_ISC Predefined. */ - -/* PORT.PIN6CTRL bit masks and bit positions */ -/* PORT_SRLEN Predefined. */ -/* PORT_SRLEN Predefined. */ - -/* PORT_INVEN Predefined. */ -/* PORT_INVEN Predefined. */ - -/* PORT_OPC Predefined. */ -/* PORT_OPC Predefined. */ - -/* PORT_ISC Predefined. */ -/* PORT_ISC Predefined. */ - -/* PORT.PIN7CTRL bit masks and bit positions */ -/* PORT_SRLEN Predefined. */ -/* PORT_SRLEN Predefined. */ - -/* PORT_INVEN Predefined. */ -/* PORT_INVEN Predefined. */ - -/* PORT_OPC Predefined. */ -/* PORT_OPC Predefined. */ - -/* PORT_ISC Predefined. */ -/* PORT_ISC Predefined. */ - -/* TC - 16-bit Timer/Counter With PWM */ -/* TC0.CTRLA bit masks and bit positions */ -#define TC0_CLKSEL_gm 0x0F /* Clock Selection group mask. */ -#define TC0_CLKSEL_gp 0 /* Clock Selection group position. */ -#define TC0_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ -#define TC0_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ -#define TC0_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ -#define TC0_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ -#define TC0_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ -#define TC0_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ -#define TC0_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ -#define TC0_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ - -/* TC0.CTRLB bit masks and bit positions */ -#define TC0_CCDEN_bm 0x80 /* Compare or Capture D Enable bit mask. */ -#define TC0_CCDEN_bp 7 /* Compare or Capture D Enable bit position. */ - -#define TC0_CCCEN_bm 0x40 /* Compare or Capture C Enable bit mask. */ -#define TC0_CCCEN_bp 6 /* Compare or Capture C Enable bit position. */ - -#define TC0_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ -#define TC0_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ - -#define TC0_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ -#define TC0_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ - -#define TC0_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ -#define TC0_WGMODE_gp 0 /* Waveform generation mode group position. */ -#define TC0_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ -#define TC0_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ -#define TC0_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ -#define TC0_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ -#define TC0_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ -#define TC0_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ - -/* TC0.CTRLC bit masks and bit positions */ -#define TC0_CMPD_bm 0x08 /* Compare D Output Value bit mask. */ -#define TC0_CMPD_bp 3 /* Compare D Output Value bit position. */ - -#define TC0_CMPC_bm 0x04 /* Compare C Output Value bit mask. */ -#define TC0_CMPC_bp 2 /* Compare C Output Value bit position. */ - -#define TC0_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ -#define TC0_CMPB_bp 1 /* Compare B Output Value bit position. */ - -#define TC0_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ -#define TC0_CMPA_bp 0 /* Compare A Output Value bit position. */ - -/* TC0.CTRLD bit masks and bit positions */ -#define TC0_EVACT_gm 0xE0 /* Event Action group mask. */ -#define TC0_EVACT_gp 5 /* Event Action group position. */ -#define TC0_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ -#define TC0_EVACT0_bp 5 /* Event Action bit 0 position. */ -#define TC0_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ -#define TC0_EVACT1_bp 6 /* Event Action bit 1 position. */ -#define TC0_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ -#define TC0_EVACT2_bp 7 /* Event Action bit 2 position. */ - -#define TC0_EVDLY_bm 0x10 /* Event Delay bit mask. */ -#define TC0_EVDLY_bp 4 /* Event Delay bit position. */ - -#define TC0_EVSEL_gm 0x0F /* Event Source Select group mask. */ -#define TC0_EVSEL_gp 0 /* Event Source Select group position. */ -#define TC0_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ -#define TC0_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ -#define TC0_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ -#define TC0_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ -#define TC0_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ -#define TC0_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ -#define TC0_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ -#define TC0_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ - -/* TC0.CTRLE bit masks and bit positions */ -#define TC0_BYTEM_bm 0x01 /* Byte Mode bit mask. */ -#define TC0_BYTEM_bp 0 /* Byte Mode bit position. */ - -/* TC0.INTCTRLA bit masks and bit positions */ -#define TC0_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ -#define TC0_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ -#define TC0_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ -#define TC0_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ -#define TC0_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ -#define TC0_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ - -#define TC0_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ -#define TC0_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ -#define TC0_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ -#define TC0_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ -#define TC0_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ -#define TC0_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ - -/* TC0.INTCTRLB bit masks and bit positions */ -#define TC0_CCDINTLVL_gm 0xC0 /* Compare or Capture D Interrupt Level group mask. */ -#define TC0_CCDINTLVL_gp 6 /* Compare or Capture D Interrupt Level group position. */ -#define TC0_CCDINTLVL0_bm (1<<6) /* Compare or Capture D Interrupt Level bit 0 mask. */ -#define TC0_CCDINTLVL0_bp 6 /* Compare or Capture D Interrupt Level bit 0 position. */ -#define TC0_CCDINTLVL1_bm (1<<7) /* Compare or Capture D Interrupt Level bit 1 mask. */ -#define TC0_CCDINTLVL1_bp 7 /* Compare or Capture D Interrupt Level bit 1 position. */ - -#define TC0_CCCINTLVL_gm 0x30 /* Compare or Capture C Interrupt Level group mask. */ -#define TC0_CCCINTLVL_gp 4 /* Compare or Capture C Interrupt Level group position. */ -#define TC0_CCCINTLVL0_bm (1<<4) /* Compare or Capture C Interrupt Level bit 0 mask. */ -#define TC0_CCCINTLVL0_bp 4 /* Compare or Capture C Interrupt Level bit 0 position. */ -#define TC0_CCCINTLVL1_bm (1<<5) /* Compare or Capture C Interrupt Level bit 1 mask. */ -#define TC0_CCCINTLVL1_bp 5 /* Compare or Capture C Interrupt Level bit 1 position. */ - -#define TC0_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ -#define TC0_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ -#define TC0_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ -#define TC0_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ -#define TC0_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ -#define TC0_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ - -#define TC0_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ -#define TC0_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ -#define TC0_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ -#define TC0_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ -#define TC0_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ -#define TC0_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ - -/* TC0.CTRLFCLR bit masks and bit positions */ -#define TC0_CMD_gm 0x0C /* Command group mask. */ -#define TC0_CMD_gp 2 /* Command group position. */ -#define TC0_CMD0_bm (1<<2) /* Command bit 0 mask. */ -#define TC0_CMD0_bp 2 /* Command bit 0 position. */ -#define TC0_CMD1_bm (1<<3) /* Command bit 1 mask. */ -#define TC0_CMD1_bp 3 /* Command bit 1 position. */ - -#define TC0_LUPD_bm 0x02 /* Lock Update bit mask. */ -#define TC0_LUPD_bp 1 /* Lock Update bit position. */ - -#define TC0_DIR_bm 0x01 /* Direction bit mask. */ -#define TC0_DIR_bp 0 /* Direction bit position. */ - -/* TC0.CTRLFSET bit masks and bit positions */ -/* TC0_CMD Predefined. */ -/* TC0_CMD Predefined. */ - -/* TC0_LUPD Predefined. */ -/* TC0_LUPD Predefined. */ - -/* TC0_DIR Predefined. */ -/* TC0_DIR Predefined. */ - -/* TC0.CTRLGCLR bit masks and bit positions */ -#define TC0_CCDBV_bm 0x10 /* Compare or Capture D Buffer Valid bit mask. */ -#define TC0_CCDBV_bp 4 /* Compare or Capture D Buffer Valid bit position. */ - -#define TC0_CCCBV_bm 0x08 /* Compare or Capture C Buffer Valid bit mask. */ -#define TC0_CCCBV_bp 3 /* Compare or Capture C Buffer Valid bit position. */ - -#define TC0_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ -#define TC0_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ - -#define TC0_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ -#define TC0_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ - -#define TC0_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ -#define TC0_PERBV_bp 0 /* Period Buffer Valid bit position. */ - -/* TC0.CTRLGSET bit masks and bit positions */ -/* TC0_CCDBV Predefined. */ -/* TC0_CCDBV Predefined. */ - -/* TC0_CCCBV Predefined. */ -/* TC0_CCCBV Predefined. */ - -/* TC0_CCBBV Predefined. */ -/* TC0_CCBBV Predefined. */ - -/* TC0_CCABV Predefined. */ -/* TC0_CCABV Predefined. */ - -/* TC0_PERBV Predefined. */ -/* TC0_PERBV Predefined. */ - -/* TC0.INTFLAGS bit masks and bit positions */ -#define TC0_CCDIF_bm 0x80 /* Compare or Capture D Interrupt Flag bit mask. */ -#define TC0_CCDIF_bp 7 /* Compare or Capture D Interrupt Flag bit position. */ - -#define TC0_CCCIF_bm 0x40 /* Compare or Capture C Interrupt Flag bit mask. */ -#define TC0_CCCIF_bp 6 /* Compare or Capture C Interrupt Flag bit position. */ - -#define TC0_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ -#define TC0_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ - -#define TC0_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ -#define TC0_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ - -#define TC0_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ -#define TC0_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ - -#define TC0_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ -#define TC0_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ - -/* TC1.CTRLA bit masks and bit positions */ -#define TC1_CLKSEL_gm 0x0F /* Clock Selection group mask. */ -#define TC1_CLKSEL_gp 0 /* Clock Selection group position. */ -#define TC1_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ -#define TC1_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ -#define TC1_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ -#define TC1_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ -#define TC1_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ -#define TC1_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ -#define TC1_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ -#define TC1_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ - -/* TC1.CTRLB bit masks and bit positions */ -#define TC1_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ -#define TC1_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ - -#define TC1_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ -#define TC1_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ - -#define TC1_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ -#define TC1_WGMODE_gp 0 /* Waveform generation mode group position. */ -#define TC1_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ -#define TC1_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ -#define TC1_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ -#define TC1_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ -#define TC1_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ -#define TC1_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ - -/* TC1.CTRLC bit masks and bit positions */ -#define TC1_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ -#define TC1_CMPB_bp 1 /* Compare B Output Value bit position. */ - -#define TC1_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ -#define TC1_CMPA_bp 0 /* Compare A Output Value bit position. */ - -/* TC1.CTRLD bit masks and bit positions */ -#define TC1_EVACT_gm 0xE0 /* Event Action group mask. */ -#define TC1_EVACT_gp 5 /* Event Action group position. */ -#define TC1_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ -#define TC1_EVACT0_bp 5 /* Event Action bit 0 position. */ -#define TC1_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ -#define TC1_EVACT1_bp 6 /* Event Action bit 1 position. */ -#define TC1_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ -#define TC1_EVACT2_bp 7 /* Event Action bit 2 position. */ - -#define TC1_EVDLY_bm 0x10 /* Event Delay bit mask. */ -#define TC1_EVDLY_bp 4 /* Event Delay bit position. */ - -#define TC1_EVSEL_gm 0x0F /* Event Source Select group mask. */ -#define TC1_EVSEL_gp 0 /* Event Source Select group position. */ -#define TC1_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ -#define TC1_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ -#define TC1_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ -#define TC1_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ -#define TC1_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ -#define TC1_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ -#define TC1_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ -#define TC1_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ - -/* TC1.CTRLE bit masks and bit positions */ -#define TC1_BYTEM_bm 0x01 /* Byte Mode bit mask. */ -#define TC1_BYTEM_bp 0 /* Byte Mode bit position. */ - -/* TC1.INTCTRLA bit masks and bit positions */ -#define TC1_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ -#define TC1_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ -#define TC1_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ -#define TC1_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ -#define TC1_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ -#define TC1_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ - -#define TC1_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ -#define TC1_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ -#define TC1_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ -#define TC1_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ -#define TC1_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ -#define TC1_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ - -/* TC1.INTCTRLB bit masks and bit positions */ -#define TC1_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ -#define TC1_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ -#define TC1_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ -#define TC1_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ -#define TC1_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ -#define TC1_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ - -#define TC1_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ -#define TC1_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ -#define TC1_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ -#define TC1_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ -#define TC1_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ -#define TC1_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ - -/* TC1.CTRLFCLR bit masks and bit positions */ -#define TC1_CMD_gm 0x0C /* Command group mask. */ -#define TC1_CMD_gp 2 /* Command group position. */ -#define TC1_CMD0_bm (1<<2) /* Command bit 0 mask. */ -#define TC1_CMD0_bp 2 /* Command bit 0 position. */ -#define TC1_CMD1_bm (1<<3) /* Command bit 1 mask. */ -#define TC1_CMD1_bp 3 /* Command bit 1 position. */ - -#define TC1_LUPD_bm 0x02 /* Lock Update bit mask. */ -#define TC1_LUPD_bp 1 /* Lock Update bit position. */ - -#define TC1_DIR_bm 0x01 /* Direction bit mask. */ -#define TC1_DIR_bp 0 /* Direction bit position. */ - -/* TC1.CTRLFSET bit masks and bit positions */ -/* TC1_CMD Predefined. */ -/* TC1_CMD Predefined. */ - -/* TC1_LUPD Predefined. */ -/* TC1_LUPD Predefined. */ - -/* TC1_DIR Predefined. */ -/* TC1_DIR Predefined. */ - -/* TC1.CTRLGCLR bit masks and bit positions */ -#define TC1_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ -#define TC1_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ - -#define TC1_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ -#define TC1_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ - -#define TC1_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ -#define TC1_PERBV_bp 0 /* Period Buffer Valid bit position. */ - -/* TC1.CTRLGSET bit masks and bit positions */ -/* TC1_CCBBV Predefined. */ -/* TC1_CCBBV Predefined. */ - -/* TC1_CCABV Predefined. */ -/* TC1_CCABV Predefined. */ - -/* TC1_PERBV Predefined. */ -/* TC1_PERBV Predefined. */ - -/* TC1.INTFLAGS bit masks and bit positions */ -#define TC1_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ -#define TC1_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ - -#define TC1_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ -#define TC1_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ - -#define TC1_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ -#define TC1_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ - -#define TC1_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ -#define TC1_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ - -/* AWEX.CTRL bit masks and bit positions */ -#define AWEX_PGM_bm 0x20 /* Pattern Generation Mode bit mask. */ -#define AWEX_PGM_bp 5 /* Pattern Generation Mode bit position. */ - -#define AWEX_CWCM_bm 0x10 /* Common Waveform Channel Mode bit mask. */ -#define AWEX_CWCM_bp 4 /* Common Waveform Channel Mode bit position. */ - -#define AWEX_DTICCDEN_bm 0x08 /* Dead Time Insertion Compare Channel D Enable bit mask. */ -#define AWEX_DTICCDEN_bp 3 /* Dead Time Insertion Compare Channel D Enable bit position. */ - -#define AWEX_DTICCCEN_bm 0x04 /* Dead Time Insertion Compare Channel C Enable bit mask. */ -#define AWEX_DTICCCEN_bp 2 /* Dead Time Insertion Compare Channel C Enable bit position. */ - -#define AWEX_DTICCBEN_bm 0x02 /* Dead Time Insertion Compare Channel B Enable bit mask. */ -#define AWEX_DTICCBEN_bp 1 /* Dead Time Insertion Compare Channel B Enable bit position. */ - -#define AWEX_DTICCAEN_bm 0x01 /* Dead Time Insertion Compare Channel A Enable bit mask. */ -#define AWEX_DTICCAEN_bp 0 /* Dead Time Insertion Compare Channel A Enable bit position. */ - -/* AWEX.FDCTRL bit masks and bit positions */ -#define AWEX_FDDBD_bm 0x10 /* Fault Detect on Disable Break Disable bit mask. */ -#define AWEX_FDDBD_bp 4 /* Fault Detect on Disable Break Disable bit position. */ - -#define AWEX_FDMODE_bm 0x04 /* Fault Detect Mode bit mask. */ -#define AWEX_FDMODE_bp 2 /* Fault Detect Mode bit position. */ - -#define AWEX_FDACT_gm 0x03 /* Fault Detect Action group mask. */ -#define AWEX_FDACT_gp 0 /* Fault Detect Action group position. */ -#define AWEX_FDACT0_bm (1<<0) /* Fault Detect Action bit 0 mask. */ -#define AWEX_FDACT0_bp 0 /* Fault Detect Action bit 0 position. */ -#define AWEX_FDACT1_bm (1<<1) /* Fault Detect Action bit 1 mask. */ -#define AWEX_FDACT1_bp 1 /* Fault Detect Action bit 1 position. */ - -/* AWEX.STATUS bit masks and bit positions */ -#define AWEX_FDF_bm 0x04 /* Fault Detect Flag bit mask. */ -#define AWEX_FDF_bp 2 /* Fault Detect Flag bit position. */ - -#define AWEX_DTHSBUFV_bm 0x02 /* Dead Time High Side Buffer Valid bit mask. */ -#define AWEX_DTHSBUFV_bp 1 /* Dead Time High Side Buffer Valid bit position. */ - -#define AWEX_DTLSBUFV_bm 0x01 /* Dead Time Low Side Buffer Valid bit mask. */ -#define AWEX_DTLSBUFV_bp 0 /* Dead Time Low Side Buffer Valid bit position. */ - -/* HIRES.CTRLA bit masks and bit positions */ -#define HIRES_HREN_gm 0x03 /* High Resolution Enable group mask. */ -#define HIRES_HREN_gp 0 /* High Resolution Enable group position. */ -#define HIRES_HREN0_bm (1<<0) /* High Resolution Enable bit 0 mask. */ -#define HIRES_HREN0_bp 0 /* High Resolution Enable bit 0 position. */ -#define HIRES_HREN1_bm (1<<1) /* High Resolution Enable bit 1 mask. */ -#define HIRES_HREN1_bp 1 /* High Resolution Enable bit 1 position. */ - -/* USART - Universal Asynchronous Receiver-Transmitter */ -/* USART.STATUS bit masks and bit positions */ -#define USART_RXCIF_bm 0x80 /* Receive Interrupt Flag bit mask. */ -#define USART_RXCIF_bp 7 /* Receive Interrupt Flag bit position. */ - -#define USART_TXCIF_bm 0x40 /* Transmit Interrupt Flag bit mask. */ -#define USART_TXCIF_bp 6 /* Transmit Interrupt Flag bit position. */ - -#define USART_DREIF_bm 0x20 /* Data Register Empty Flag bit mask. */ -#define USART_DREIF_bp 5 /* Data Register Empty Flag bit position. */ - -#define USART_FERR_bm 0x10 /* Frame Error bit mask. */ -#define USART_FERR_bp 4 /* Frame Error bit position. */ - -#define USART_BUFOVF_bm 0x08 /* Buffer Overflow bit mask. */ -#define USART_BUFOVF_bp 3 /* Buffer Overflow bit position. */ - -#define USART_PERR_bm 0x04 /* Parity Error bit mask. */ -#define USART_PERR_bp 2 /* Parity Error bit position. */ - -#define USART_RXB8_bm 0x01 /* Receive Bit 8 bit mask. */ -#define USART_RXB8_bp 0 /* Receive Bit 8 bit position. */ - -/* USART.CTRLA bit masks and bit positions */ -#define USART_RXCINTLVL_gm 0x30 /* Receive Interrupt Level group mask. */ -#define USART_RXCINTLVL_gp 4 /* Receive Interrupt Level group position. */ -#define USART_RXCINTLVL0_bm (1<<4) /* Receive Interrupt Level bit 0 mask. */ -#define USART_RXCINTLVL0_bp 4 /* Receive Interrupt Level bit 0 position. */ -#define USART_RXCINTLVL1_bm (1<<5) /* Receive Interrupt Level bit 1 mask. */ -#define USART_RXCINTLVL1_bp 5 /* Receive Interrupt Level bit 1 position. */ - -#define USART_TXCINTLVL_gm 0x0C /* Transmit Interrupt Level group mask. */ -#define USART_TXCINTLVL_gp 2 /* Transmit Interrupt Level group position. */ -#define USART_TXCINTLVL0_bm (1<<2) /* Transmit Interrupt Level bit 0 mask. */ -#define USART_TXCINTLVL0_bp 2 /* Transmit Interrupt Level bit 0 position. */ -#define USART_TXCINTLVL1_bm (1<<3) /* Transmit Interrupt Level bit 1 mask. */ -#define USART_TXCINTLVL1_bp 3 /* Transmit Interrupt Level bit 1 position. */ - -#define USART_DREINTLVL_gm 0x03 /* Data Register Empty Interrupt Level group mask. */ -#define USART_DREINTLVL_gp 0 /* Data Register Empty Interrupt Level group position. */ -#define USART_DREINTLVL0_bm (1<<0) /* Data Register Empty Interrupt Level bit 0 mask. */ -#define USART_DREINTLVL0_bp 0 /* Data Register Empty Interrupt Level bit 0 position. */ -#define USART_DREINTLVL1_bm (1<<1) /* Data Register Empty Interrupt Level bit 1 mask. */ -#define USART_DREINTLVL1_bp 1 /* Data Register Empty Interrupt Level bit 1 position. */ - -/* USART.CTRLB bit masks and bit positions */ -#define USART_RXEN_bm 0x10 /* Receiver Enable bit mask. */ -#define USART_RXEN_bp 4 /* Receiver Enable bit position. */ - -#define USART_TXEN_bm 0x08 /* Transmitter Enable bit mask. */ -#define USART_TXEN_bp 3 /* Transmitter Enable bit position. */ - -#define USART_CLK2X_bm 0x04 /* Double transmission speed bit mask. */ -#define USART_CLK2X_bp 2 /* Double transmission speed bit position. */ - -#define USART_MPCM_bm 0x02 /* Multi-processor Communication Mode bit mask. */ -#define USART_MPCM_bp 1 /* Multi-processor Communication Mode bit position. */ - -#define USART_TXB8_bm 0x01 /* Transmit bit 8 bit mask. */ -#define USART_TXB8_bp 0 /* Transmit bit 8 bit position. */ - -/* USART.CTRLC bit masks and bit positions */ -#define USART_CMODE_gm 0xC0 /* Communication Mode group mask. */ -#define USART_CMODE_gp 6 /* Communication Mode group position. */ -#define USART_CMODE0_bm (1<<6) /* Communication Mode bit 0 mask. */ -#define USART_CMODE0_bp 6 /* Communication Mode bit 0 position. */ -#define USART_CMODE1_bm (1<<7) /* Communication Mode bit 1 mask. */ -#define USART_CMODE1_bp 7 /* Communication Mode bit 1 position. */ - -#define USART_PMODE_gm 0x30 /* Parity Mode group mask. */ -#define USART_PMODE_gp 4 /* Parity Mode group position. */ -#define USART_PMODE0_bm (1<<4) /* Parity Mode bit 0 mask. */ -#define USART_PMODE0_bp 4 /* Parity Mode bit 0 position. */ -#define USART_PMODE1_bm (1<<5) /* Parity Mode bit 1 mask. */ -#define USART_PMODE1_bp 5 /* Parity Mode bit 1 position. */ - -#define USART_SBMODE_bm 0x08 /* Stop Bit Mode bit mask. */ -#define USART_SBMODE_bp 3 /* Stop Bit Mode bit position. */ - -#define USART_CHSIZE_gm 0x07 /* Character Size group mask. */ -#define USART_CHSIZE_gp 0 /* Character Size group position. */ -#define USART_CHSIZE0_bm (1<<0) /* Character Size bit 0 mask. */ -#define USART_CHSIZE0_bp 0 /* Character Size bit 0 position. */ -#define USART_CHSIZE1_bm (1<<1) /* Character Size bit 1 mask. */ -#define USART_CHSIZE1_bp 1 /* Character Size bit 1 position. */ -#define USART_CHSIZE2_bm (1<<2) /* Character Size bit 2 mask. */ -#define USART_CHSIZE2_bp 2 /* Character Size bit 2 position. */ - -#define USART_UDORD_bm 0x04 /* SPI Master Mode, Data Order bit mask. */ -#define USART_UDORD_bp 2 /* SPI Master Mode, Data Order bit position. */ - -#define USART_UCPHA_bm 0x02 /* SPI Master Mode, Clock Phase bit mask. */ -#define USART_UCPHA_bp 1 /* SPI Master Mode, Clock Phase bit position. */ - -/* USART.BAUDCTRLA bit masks and bit positions */ -#define USART_BSEL_gm 0xFF /* Baud Rate Selection Bits [7:0] group mask. */ -#define USART_BSEL_gp 0 /* Baud Rate Selection Bits [7:0] group position. */ -#define USART_BSEL0_bm (1<<0) /* Baud Rate Selection Bits [7:0] bit 0 mask. */ -#define USART_BSEL0_bp 0 /* Baud Rate Selection Bits [7:0] bit 0 position. */ -#define USART_BSEL1_bm (1<<1) /* Baud Rate Selection Bits [7:0] bit 1 mask. */ -#define USART_BSEL1_bp 1 /* Baud Rate Selection Bits [7:0] bit 1 position. */ -#define USART_BSEL2_bm (1<<2) /* Baud Rate Selection Bits [7:0] bit 2 mask. */ -#define USART_BSEL2_bp 2 /* Baud Rate Selection Bits [7:0] bit 2 position. */ -#define USART_BSEL3_bm (1<<3) /* Baud Rate Selection Bits [7:0] bit 3 mask. */ -#define USART_BSEL3_bp 3 /* Baud Rate Selection Bits [7:0] bit 3 position. */ -#define USART_BSEL4_bm (1<<4) /* Baud Rate Selection Bits [7:0] bit 4 mask. */ -#define USART_BSEL4_bp 4 /* Baud Rate Selection Bits [7:0] bit 4 position. */ -#define USART_BSEL5_bm (1<<5) /* Baud Rate Selection Bits [7:0] bit 5 mask. */ -#define USART_BSEL5_bp 5 /* Baud Rate Selection Bits [7:0] bit 5 position. */ -#define USART_BSEL6_bm (1<<6) /* Baud Rate Selection Bits [7:0] bit 6 mask. */ -#define USART_BSEL6_bp 6 /* Baud Rate Selection Bits [7:0] bit 6 position. */ -#define USART_BSEL7_bm (1<<7) /* Baud Rate Selection Bits [7:0] bit 7 mask. */ -#define USART_BSEL7_bp 7 /* Baud Rate Selection Bits [7:0] bit 7 position. */ - -/* USART.BAUDCTRLB bit masks and bit positions */ -#define USART_BSCALE_gm 0xF0 /* Baud Rate Scale group mask. */ -#define USART_BSCALE_gp 4 /* Baud Rate Scale group position. */ -#define USART_BSCALE0_bm (1<<4) /* Baud Rate Scale bit 0 mask. */ -#define USART_BSCALE0_bp 4 /* Baud Rate Scale bit 0 position. */ -#define USART_BSCALE1_bm (1<<5) /* Baud Rate Scale bit 1 mask. */ -#define USART_BSCALE1_bp 5 /* Baud Rate Scale bit 1 position. */ -#define USART_BSCALE2_bm (1<<6) /* Baud Rate Scale bit 2 mask. */ -#define USART_BSCALE2_bp 6 /* Baud Rate Scale bit 2 position. */ -#define USART_BSCALE3_bm (1<<7) /* Baud Rate Scale bit 3 mask. */ -#define USART_BSCALE3_bp 7 /* Baud Rate Scale bit 3 position. */ - -/* USART_BSEL Predefined. */ -/* USART_BSEL Predefined. */ - -/* SPI - Serial Peripheral Interface */ -/* SPI.CTRL bit masks and bit positions */ -#define SPI_CLK2X_bm 0x80 /* Enable Double Speed bit mask. */ -#define SPI_CLK2X_bp 7 /* Enable Double Speed bit position. */ - -#define SPI_ENABLE_bm 0x40 /* Enable Module bit mask. */ -#define SPI_ENABLE_bp 6 /* Enable Module bit position. */ - -#define SPI_DORD_bm 0x20 /* Data Order Setting bit mask. */ -#define SPI_DORD_bp 5 /* Data Order Setting bit position. */ - -#define SPI_MASTER_bm 0x10 /* Master Operation Enable bit mask. */ -#define SPI_MASTER_bp 4 /* Master Operation Enable bit position. */ - -#define SPI_MODE_gm 0x0C /* SPI Mode group mask. */ -#define SPI_MODE_gp 2 /* SPI Mode group position. */ -#define SPI_MODE0_bm (1<<2) /* SPI Mode bit 0 mask. */ -#define SPI_MODE0_bp 2 /* SPI Mode bit 0 position. */ -#define SPI_MODE1_bm (1<<3) /* SPI Mode bit 1 mask. */ -#define SPI_MODE1_bp 3 /* SPI Mode bit 1 position. */ - -#define SPI_PRESCALER_gm 0x03 /* Prescaler group mask. */ -#define SPI_PRESCALER_gp 0 /* Prescaler group position. */ -#define SPI_PRESCALER0_bm (1<<0) /* Prescaler bit 0 mask. */ -#define SPI_PRESCALER0_bp 0 /* Prescaler bit 0 position. */ -#define SPI_PRESCALER1_bm (1<<1) /* Prescaler bit 1 mask. */ -#define SPI_PRESCALER1_bp 1 /* Prescaler bit 1 position. */ - -/* SPI.INTCTRL bit masks and bit positions */ -#define SPI_INTLVL_gm 0x03 /* Interrupt level group mask. */ -#define SPI_INTLVL_gp 0 /* Interrupt level group position. */ -#define SPI_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */ -#define SPI_INTLVL0_bp 0 /* Interrupt level bit 0 position. */ -#define SPI_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */ -#define SPI_INTLVL1_bp 1 /* Interrupt level bit 1 position. */ - -/* SPI.STATUS bit masks and bit positions */ -#define SPI_IF_bm 0x80 /* Interrupt Flag bit mask. */ -#define SPI_IF_bp 7 /* Interrupt Flag bit position. */ - -#define SPI_WRCOL_bm 0x40 /* Write Collision bit mask. */ -#define SPI_WRCOL_bp 6 /* Write Collision bit position. */ - -/* IRCOM - IR Communication Module */ -/* IRCOM.CTRL bit masks and bit positions */ -#define IRCOM_EVSEL_gm 0x0F /* Event Channel Select group mask. */ -#define IRCOM_EVSEL_gp 0 /* Event Channel Select group position. */ -#define IRCOM_EVSEL0_bm (1<<0) /* Event Channel Select bit 0 mask. */ -#define IRCOM_EVSEL0_bp 0 /* Event Channel Select bit 0 position. */ -#define IRCOM_EVSEL1_bm (1<<1) /* Event Channel Select bit 1 mask. */ -#define IRCOM_EVSEL1_bp 1 /* Event Channel Select bit 1 position. */ -#define IRCOM_EVSEL2_bm (1<<2) /* Event Channel Select bit 2 mask. */ -#define IRCOM_EVSEL2_bp 2 /* Event Channel Select bit 2 position. */ -#define IRCOM_EVSEL3_bm (1<<3) /* Event Channel Select bit 3 mask. */ -#define IRCOM_EVSEL3_bp 3 /* Event Channel Select bit 3 position. */ - - - -// Generic Port Pins - -#define PIN0_bm 0x01 -#define PIN0_bp 0 -#define PIN1_bm 0x02 -#define PIN1_bp 1 -#define PIN2_bm 0x04 -#define PIN2_bp 2 -#define PIN3_bm 0x08 -#define PIN3_bp 3 -#define PIN4_bm 0x10 -#define PIN4_bp 4 -#define PIN5_bm 0x20 -#define PIN5_bp 5 -#define PIN6_bm 0x40 -#define PIN6_bp 6 -#define PIN7_bm 0x80 -#define PIN7_bp 7 - -/* ========== Interrupt Vector Definitions ========== */ -/* Vector 0 is the reset vector */ - -/* OSC interrupt vectors */ -#define OSC_OSCF_vect_num 1 -#define OSC_OSCF_vect _VECTOR(1) /* External Oscillator Failure Interrupt (NMI) */ - -/* PORTC interrupt vectors */ -#define PORTC_INT0_vect_num 2 -#define PORTC_INT0_vect _VECTOR(2) /* External Interrupt 0 */ -#define PORTC_INT1_vect_num 3 -#define PORTC_INT1_vect _VECTOR(3) /* External Interrupt 1 */ - -/* PORTR interrupt vectors */ -#define PORTR_INT0_vect_num 4 -#define PORTR_INT0_vect _VECTOR(4) /* External Interrupt 0 */ -#define PORTR_INT1_vect_num 5 -#define PORTR_INT1_vect _VECTOR(5) /* External Interrupt 1 */ - -/* RTC interrupt vectors */ -#define RTC_OVF_vect_num 10 -#define RTC_OVF_vect _VECTOR(10) /* Overflow Interrupt */ -#define RTC_COMP_vect_num 11 -#define RTC_COMP_vect _VECTOR(11) /* Compare Interrupt */ - -/* TWIC interrupt vectors */ -#define TWIC_TWIS_vect_num 12 -#define TWIC_TWIS_vect _VECTOR(12) /* TWI Slave Interrupt */ -#define TWIC_TWIM_vect_num 13 -#define TWIC_TWIM_vect _VECTOR(13) /* TWI Master Interrupt */ - -/* TCC0 interrupt vectors */ -#define TCC0_OVF_vect_num 14 -#define TCC0_OVF_vect _VECTOR(14) /* Overflow Interrupt */ -#define TCC0_ERR_vect_num 15 -#define TCC0_ERR_vect _VECTOR(15) /* Error Interrupt */ -#define TCC0_CCA_vect_num 16 -#define TCC0_CCA_vect _VECTOR(16) /* Compare or Capture A Interrupt */ -#define TCC0_CCB_vect_num 17 -#define TCC0_CCB_vect _VECTOR(17) /* Compare or Capture B Interrupt */ -#define TCC0_CCC_vect_num 18 -#define TCC0_CCC_vect _VECTOR(18) /* Compare or Capture C Interrupt */ -#define TCC0_CCD_vect_num 19 -#define TCC0_CCD_vect _VECTOR(19) /* Compare or Capture D Interrupt */ - -/* TCC1 interrupt vectors */ -#define TCC1_OVF_vect_num 20 -#define TCC1_OVF_vect _VECTOR(20) /* Overflow Interrupt */ -#define TCC1_ERR_vect_num 21 -#define TCC1_ERR_vect _VECTOR(21) /* Error Interrupt */ -#define TCC1_CCA_vect_num 22 -#define TCC1_CCA_vect _VECTOR(22) /* Compare or Capture A Interrupt */ -#define TCC1_CCB_vect_num 23 -#define TCC1_CCB_vect _VECTOR(23) /* Compare or Capture B Interrupt */ - -/* SPIC interrupt vectors */ -#define SPIC_INT_vect_num 24 -#define SPIC_INT_vect _VECTOR(24) /* SPI Interrupt */ - -/* USARTC0 interrupt vectors */ -#define USARTC0_RXC_vect_num 25 -#define USARTC0_RXC_vect _VECTOR(25) /* Reception Complete Interrupt */ -#define USARTC0_DRE_vect_num 26 -#define USARTC0_DRE_vect _VECTOR(26) /* Data Register Empty Interrupt */ -#define USARTC0_TXC_vect_num 27 -#define USARTC0_TXC_vect _VECTOR(27) /* Transmission Complete Interrupt */ - -/* NVM interrupt vectors */ -#define NVM_EE_vect_num 32 -#define NVM_EE_vect _VECTOR(32) /* EE Interrupt */ -#define NVM_SPM_vect_num 33 -#define NVM_SPM_vect _VECTOR(33) /* SPM Interrupt */ - -/* PORTB interrupt vectors */ -#define PORTB_INT0_vect_num 34 -#define PORTB_INT0_vect _VECTOR(34) /* External Interrupt 0 */ -#define PORTB_INT1_vect_num 35 -#define PORTB_INT1_vect _VECTOR(35) /* External Interrupt 1 */ - -/* PORTE interrupt vectors */ -#define PORTE_INT0_vect_num 43 -#define PORTE_INT0_vect _VECTOR(43) /* External Interrupt 0 */ -#define PORTE_INT1_vect_num 44 -#define PORTE_INT1_vect _VECTOR(44) /* External Interrupt 1 */ - -/* TWIE interrupt vectors */ -#define TWIE_TWIS_vect_num 45 -#define TWIE_TWIS_vect _VECTOR(45) /* TWI Slave Interrupt */ -#define TWIE_TWIM_vect_num 46 -#define TWIE_TWIM_vect _VECTOR(46) /* TWI Master Interrupt */ - -/* TCE0 interrupt vectors */ -#define TCE0_OVF_vect_num 47 -#define TCE0_OVF_vect _VECTOR(47) /* Overflow Interrupt */ -#define TCE0_ERR_vect_num 48 -#define TCE0_ERR_vect _VECTOR(48) /* Error Interrupt */ -#define TCE0_CCA_vect_num 49 -#define TCE0_CCA_vect _VECTOR(49) /* Compare or Capture A Interrupt */ -#define TCE0_CCB_vect_num 50 -#define TCE0_CCB_vect _VECTOR(50) /* Compare or Capture B Interrupt */ -#define TCE0_CCC_vect_num 51 -#define TCE0_CCC_vect _VECTOR(51) /* Compare or Capture C Interrupt */ -#define TCE0_CCD_vect_num 52 -#define TCE0_CCD_vect _VECTOR(52) /* Compare or Capture D Interrupt */ - -/* USARTE0 interrupt vectors */ -#define USARTE0_RXC_vect_num 58 -#define USARTE0_RXC_vect _VECTOR(58) /* Reception Complete Interrupt */ -#define USARTE0_DRE_vect_num 59 -#define USARTE0_DRE_vect _VECTOR(59) /* Data Register Empty Interrupt */ -#define USARTE0_TXC_vect_num 60 -#define USARTE0_TXC_vect _VECTOR(60) /* Transmission Complete Interrupt */ - -/* PORTD interrupt vectors */ -#define PORTD_INT0_vect_num 64 -#define PORTD_INT0_vect _VECTOR(64) /* External Interrupt 0 */ -#define PORTD_INT1_vect_num 65 -#define PORTD_INT1_vect _VECTOR(65) /* External Interrupt 1 */ - -/* PORTA interrupt vectors */ -#define PORTA_INT0_vect_num 66 -#define PORTA_INT0_vect _VECTOR(66) /* External Interrupt 0 */ -#define PORTA_INT1_vect_num 67 -#define PORTA_INT1_vect _VECTOR(67) /* External Interrupt 1 */ - -/* ACA interrupt vectors */ -#define ACA_AC0_vect_num 68 -#define ACA_AC0_vect _VECTOR(68) /* AC0 Interrupt */ -#define ACA_AC1_vect_num 69 -#define ACA_AC1_vect _VECTOR(69) /* AC1 Interrupt */ -#define ACA_ACW_vect_num 70 -#define ACA_ACW_vect _VECTOR(70) /* ACW Window Mode Interrupt */ - -/* ADCA interrupt vectors */ -#define ADCA_CH0_vect_num 71 -#define ADCA_CH0_vect _VECTOR(71) /* Interrupt 0 */ - -/* TCD0 interrupt vectors */ -#define TCD0_OVF_vect_num 77 -#define TCD0_OVF_vect _VECTOR(77) /* Overflow Interrupt */ -#define TCD0_ERR_vect_num 78 -#define TCD0_ERR_vect _VECTOR(78) /* Error Interrupt */ -#define TCD0_CCA_vect_num 79 -#define TCD0_CCA_vect _VECTOR(79) /* Compare or Capture A Interrupt */ -#define TCD0_CCB_vect_num 80 -#define TCD0_CCB_vect _VECTOR(80) /* Compare or Capture B Interrupt */ -#define TCD0_CCC_vect_num 81 -#define TCD0_CCC_vect _VECTOR(81) /* Compare or Capture C Interrupt */ -#define TCD0_CCD_vect_num 82 -#define TCD0_CCD_vect _VECTOR(82) /* Compare or Capture D Interrupt */ - -/* SPID interrupt vectors */ -#define SPID_INT_vect_num 87 -#define SPID_INT_vect _VECTOR(87) /* SPI Interrupt */ - -/* USARTD0 interrupt vectors */ -#define USARTD0_RXC_vect_num 88 -#define USARTD0_RXC_vect _VECTOR(88) /* Reception Complete Interrupt */ -#define USARTD0_DRE_vect_num 89 -#define USARTD0_DRE_vect _VECTOR(89) /* Data Register Empty Interrupt */ -#define USARTD0_TXC_vect_num 90 -#define USARTD0_TXC_vect _VECTOR(90) /* Transmission Complete Interrupt */ - -/* PORTF interrupt vectors */ -#define PORTF_INT0_vect_num 104 -#define PORTF_INT0_vect _VECTOR(104) /* External Interrupt 0 */ -#define PORTF_INT1_vect_num 105 -#define PORTF_INT1_vect _VECTOR(105) /* External Interrupt 1 */ - -/* TCF0 interrupt vectors */ -#define TCF0_OVF_vect_num 108 -#define TCF0_OVF_vect _VECTOR(108) /* Overflow Interrupt */ -#define TCF0_ERR_vect_num 109 -#define TCF0_ERR_vect _VECTOR(109) /* Error Interrupt */ -#define TCF0_CCA_vect_num 110 -#define TCF0_CCA_vect _VECTOR(110) /* Compare or Capture A Interrupt */ -#define TCF0_CCB_vect_num 111 -#define TCF0_CCB_vect _VECTOR(111) /* Compare or Capture B Interrupt */ -#define TCF0_CCC_vect_num 112 -#define TCF0_CCC_vect _VECTOR(112) /* Compare or Capture C Interrupt */ -#define TCF0_CCD_vect_num 113 -#define TCF0_CCD_vect _VECTOR(113) /* Compare or Capture D Interrupt */ - -#define _VECTOR_SIZE 4 /* Size of individual vector. */ -#define _VECTORS_SIZE (114 * _VECTOR_SIZE) - - -/* ========== Constants ========== */ - -#define PROGMEM_START (0x0000) -#define PROGMEM_SIZE (36864) -#define PROGMEM_END (PROGMEM_START + PROGMEM_SIZE - 1) - -#define APP_SECTION_START (0x0000) -#define APP_SECTION_SIZE (32768) -#define APP_SECTION_PAGE_SIZE (256) -#define APP_SECTION_END (APP_SECTION_START + APP_SECTION_SIZE - 1) - -#define APPTABLE_SECTION_START (0x7000) -#define APPTABLE_SECTION_SIZE (4096) -#define APPTABLE_SECTION_PAGE_SIZE (256) -#define APPTABLE_SECTION_END (APPTABLE_SECTION_START + APPTABLE_SECTION_SIZE - 1) - -#define BOOT_SECTION_START (0x8000) -#define BOOT_SECTION_SIZE (4096) -#define BOOT_SECTION_PAGE_SIZE (256) -#define BOOT_SECTION_END (BOOT_SECTION_START + BOOT_SECTION_SIZE - 1) - -#define DATAMEM_START (0x0000) -#define DATAMEM_SIZE (12288) -#define DATAMEM_END (DATAMEM_START + DATAMEM_SIZE - 1) - -#define IO_START (0x0000) -#define IO_SIZE (4096) -#define IO_PAGE_SIZE (0) -#define IO_END (IO_START + IO_SIZE - 1) - -#define MAPPED_EEPROM_START (0x1000) -#define MAPPED_EEPROM_SIZE (1024) -#define MAPPED_EEPROM_PAGE_SIZE (0) -#define MAPPED_EEPROM_END (MAPPED_EEPROM_START + MAPPED_EEPROM_SIZE - 1) - -#define INTERNAL_SRAM_START (0x2000) -#define INTERNAL_SRAM_SIZE (4096) -#define INTERNAL_SRAM_PAGE_SIZE (0) -#define INTERNAL_SRAM_END (INTERNAL_SRAM_START + INTERNAL_SRAM_SIZE - 1) - -#define EEPROM_START (0x0000) -#define EEPROM_SIZE (1024) -#define EEPROM_PAGE_SIZE (32) -#define EEPROM_END (EEPROM_START + EEPROM_SIZE - 1) - -#define SIGNATURES_START (0x0000) -#define SIGNATURES_SIZE (3) -#define SIGNATURES_PAGE_SIZE (0) -#define SIGNATURES_END (SIGNATURES_START + SIGNATURES_SIZE - 1) - -#define FUSES_START (0x0000) -#define FUSES_SIZE (6) -#define FUSES_PAGE_SIZE (0) -#define FUSES_END (FUSES_START + FUSES_SIZE - 1) - -#define LOCKBITS_START (0x0000) -#define LOCKBITS_SIZE (1) -#define LOCKBITS_PAGE_SIZE (0) -#define LOCKBITS_END (LOCKBITS_START + LOCKBITS_SIZE - 1) - -#define USER_SIGNATURES_START (0x0000) -#define USER_SIGNATURES_SIZE (256) -#define USER_SIGNATURES_PAGE_SIZE (256) -#define USER_SIGNATURES_END (USER_SIGNATURES_START + USER_SIGNATURES_SIZE - 1) - -#define PROD_SIGNATURES_START (0x0000) -#define PROD_SIGNATURES_SIZE (52) -#define PROD_SIGNATURES_PAGE_SIZE (256) -#define PROD_SIGNATURES_END (PROD_SIGNATURES_START + PROD_SIGNATURES_SIZE - 1) - -#define FLASHSTART PROGMEM_START -#define FLASHEND PROGMEM_END -#define SPM_PAGESIZE 256 -#define RAMSTART INTERNAL_SRAM_START -#define RAMSIZE INTERNAL_SRAM_SIZE -#define RAMEND INTERNAL_SRAM_END -#define E2END EEPROM_END -#define E2PAGESIZE EEPROM_PAGE_SIZE - - -/* ========== Fuses ========== */ -#define FUSE_MEMORY_SIZE 6 - -/* Fuse Byte 0 Reserved */ - -/* Fuse Byte 1 */ -#define FUSE_WDP0 (unsigned char)~_BV(0) /* Watchdog Timeout Period Bit 0 */ -#define FUSE_WDP1 (unsigned char)~_BV(1) /* Watchdog Timeout Period Bit 1 */ -#define FUSE_WDP2 (unsigned char)~_BV(2) /* Watchdog Timeout Period Bit 2 */ -#define FUSE_WDP3 (unsigned char)~_BV(3) /* Watchdog Timeout Period Bit 3 */ -#define FUSE_WDWP0 (unsigned char)~_BV(4) /* Watchdog Window Timeout Period Bit 0 */ -#define FUSE_WDWP1 (unsigned char)~_BV(5) /* Watchdog Window Timeout Period Bit 1 */ -#define FUSE_WDWP2 (unsigned char)~_BV(6) /* Watchdog Window Timeout Period Bit 2 */ -#define FUSE_WDWP3 (unsigned char)~_BV(7) /* Watchdog Window Timeout Period Bit 3 */ -#define FUSE1_DEFAULT (0xFF) - -/* Fuse Byte 2 */ -#define FUSE_BODPD0 (unsigned char)~_BV(0) /* BOD Operation in Power-Down Mode Bit 0 */ -#define FUSE_BODPD1 (unsigned char)~_BV(1) /* BOD Operation in Power-Down Mode Bit 1 */ -#define FUSE_TOSCSEL (unsigned char)~_BV(5) /* 32.768kHz Timer Oscillator Pin Selection */ -#define FUSE_BOOTRST (unsigned char)~_BV(6) /* Boot Loader Section Reset Vector */ -#define FUSE_DVSDON (unsigned char)~_BV(7) /* Spike Detector Enable */ -#define FUSE2_DEFAULT (0xFF) - -/* Fuse Byte 3 Reserved */ - -/* Fuse Byte 4 */ -#define FUSE_WDLOCK (unsigned char)~_BV(1) /* Watchdog Timer Lock */ -#define FUSE_SUT0 (unsigned char)~_BV(2) /* Start-up Time Bit 0 */ -#define FUSE_SUT1 (unsigned char)~_BV(3) /* Start-up Time Bit 1 */ -#define FUSE_RSTDISBL (unsigned char)~_BV(4) /* External Reset Disable */ -#define FUSE4_DEFAULT (0xFF) - -/* Fuse Byte 5 */ -#define FUSE_BODLVL0 (unsigned char)~_BV(0) /* Brownout Detection Voltage Level Bit 0 */ -#define FUSE_BODLVL1 (unsigned char)~_BV(1) /* Brownout Detection Voltage Level Bit 1 */ -#define FUSE_BODLVL2 (unsigned char)~_BV(2) /* Brownout Detection Voltage Level Bit 2 */ -#define FUSE_EESAVE (unsigned char)~_BV(3) /* Preserve EEPROM Through Chip Erase */ -#define FUSE_BODACT0 (unsigned char)~_BV(4) /* BOD Operation in Active Mode Bit 0 */ -#define FUSE_BODACT1 (unsigned char)~_BV(5) /* BOD Operation in Active Mode Bit 1 */ -#define FUSE5_DEFAULT (0xFF) - -/* ========== Lock Bits ========== */ -#define __LOCK_BITS_EXIST -#define __BOOT_LOCK_APPLICATION_TABLE_BITS_EXIST -#define __BOOT_LOCK_APPLICATION_BITS_EXIST -#define __BOOT_LOCK_BOOT_BITS_EXIST - -/* ========== Signature ========== */ -#define SIGNATURE_0 0x1E -#define SIGNATURE_1 0x95 -#define SIGNATURE_2 0x4A - -/* ========== Power Reduction Condition Definitions ========== */ - -/* PR.PRGEN */ -#define __AVR_HAVE_PRGEN (PR_RTC_bm|PR_EVSYS_bm) -#define __AVR_HAVE_PRGEN_RTC -#define __AVR_HAVE_PRGEN_EVSYS - -/* PR.PRPA */ -#define __AVR_HAVE_PRPA (PR_ADC_bm|PR_AC_bm) -#define __AVR_HAVE_PRPA_ADC -#define __AVR_HAVE_PRPA_AC - -/* PR.PRPC */ -#define __AVR_HAVE_PRPC (PR_TWI_bm|PR_USART0_bm|PR_SPI_bm|PR_HIRES_bm|PR_TC1_bm|PR_TC0_bm) -#define __AVR_HAVE_PRPC_TWI -#define __AVR_HAVE_PRPC_USART0 -#define __AVR_HAVE_PRPC_SPI -#define __AVR_HAVE_PRPC_HIRES -#define __AVR_HAVE_PRPC_TC1 -#define __AVR_HAVE_PRPC_TC0 - -/* PR.PRPD */ -#define __AVR_HAVE_PRPD (PR_USART0_bm|PR_SPI_bm|PR_TC0_bm) -#define __AVR_HAVE_PRPD_USART0 -#define __AVR_HAVE_PRPD_SPI -#define __AVR_HAVE_PRPD_TC0 - -/* PR.PRPE */ -#define __AVR_HAVE_PRPE (PR_TWI_bm|PR_USART0_bm|PR_TC0_bm) -#define __AVR_HAVE_PRPE_TWI -#define __AVR_HAVE_PRPE_USART0 -#define __AVR_HAVE_PRPE_TC0 - -/* PR.PRPF */ -#define __AVR_HAVE_PRPF (PR_USART0_bm|PR_TC0_bm) -#define __AVR_HAVE_PRPF_USART0 -#define __AVR_HAVE_PRPF_TC0 - - -#endif /* #ifdef _AVR_ATXMEGA32D3_H_INCLUDED */ - diff --git a/arduino/hardware/tools/avr/avr/include/avr/iox32d4.h b/arduino/hardware/tools/avr/avr/include/avr/iox32d4.h deleted file mode 100644 index 9de38fc..0000000 --- a/arduino/hardware/tools/avr/avr/include/avr/iox32d4.h +++ /dev/null @@ -1,5685 +0,0 @@ -/* Copyright (c) 2009-2010 Atmel Corporation - All rights reserved. - - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - * Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - * Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in - the documentation and/or other materials provided with the - distribution. - - * Neither the name of the copyright holders nor the names of - contributors may be used to endorse or promote products derived - from this software without specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. */ - -/* $Id: iox32d4.h 2200 2010-12-14 04:24:24Z arcanum $ */ - -/* avr/iox32d4.h - definitions for ATxmega32D4 */ - -/* This file should only be included from , never directly. */ - -#ifndef _AVR_IO_H_ -# error "Include instead of this file." -#endif - -#ifndef _AVR_IOXXX_H_ -# define _AVR_IOXXX_H_ "iox32d4.h" -#else -# error "Attempt to include more than one file." -#endif - - -#ifndef _AVR_ATxmega32D4_H_ -#define _AVR_ATxmega32D4_H_ 1 - - -/* Ungrouped common registers */ -#define GPIO0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ -#define GPIO1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ -#define GPIO2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ -#define GPIO3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ -#define GPIO4 _SFR_MEM8(0x0004) /* General Purpose IO Register 4 */ -#define GPIO5 _SFR_MEM8(0x0005) /* General Purpose IO Register 5 */ -#define GPIO6 _SFR_MEM8(0x0006) /* General Purpose IO Register 6 */ -#define GPIO7 _SFR_MEM8(0x0007) /* General Purpose IO Register 7 */ -#define GPIO8 _SFR_MEM8(0x0008) /* General Purpose IO Register 8 */ -#define GPIO9 _SFR_MEM8(0x0009) /* General Purpose IO Register 9 */ -#define GPIOA _SFR_MEM8(0x000A) /* General Purpose IO Register 10 */ -#define GPIOB _SFR_MEM8(0x000B) /* General Purpose IO Register 11 */ -#define GPIOC _SFR_MEM8(0x000C) /* General Purpose IO Register 12 */ -#define GPIOD _SFR_MEM8(0x000D) /* General Purpose IO Register 13 */ -#define GPIOE _SFR_MEM8(0x000E) /* General Purpose IO Register 14 */ -#define GPIOF _SFR_MEM8(0x000F) /* General Purpose IO Register 15 */ - -#define CCP _SFR_MEM8(0x0034) /* Configuration Change Protection */ -#define RAMPD _SFR_MEM8(0x0038) /* Ramp D */ -#define RAMPX _SFR_MEM8(0x0039) /* Ramp X */ -#define RAMPY _SFR_MEM8(0x003A) /* Ramp Y */ -#define RAMPZ _SFR_MEM8(0x003B) /* Ramp Z */ -#define EIND _SFR_MEM8(0x003C) /* Extended Indirect Jump */ -#define SPL _SFR_MEM8(0x003D) /* Stack Pointer Low */ -#define SPH _SFR_MEM8(0x003E) /* Stack Pointer High */ -#define SREG _SFR_MEM8(0x003F) /* Status Register */ - - -/* C Language Only */ -#if !defined (__ASSEMBLER__) - -#include - -typedef volatile uint8_t register8_t; -typedef volatile uint16_t register16_t; -typedef volatile uint32_t register32_t; - - -#ifdef _WORDREGISTER -#undef _WORDREGISTER -#endif -#define _WORDREGISTER(regname) \ - __extension__ union \ - { \ - register16_t regname; \ - struct \ - { \ - register8_t regname ## L; \ - register8_t regname ## H; \ - }; \ - } - -#ifdef _DWORDREGISTER -#undef _DWORDREGISTER -#endif -#define _DWORDREGISTER(regname) \ - __extension__ union \ - { \ - register32_t regname; \ - struct \ - { \ - register8_t regname ## 0; \ - register8_t regname ## 1; \ - register8_t regname ## 2; \ - register8_t regname ## 3; \ - }; \ - } - - -/* -========================================================================== -IO Module Structures -========================================================================== -*/ - - -/* --------------------------------------------------------------------------- -XOCD - On-Chip Debug System --------------------------------------------------------------------------- -*/ - -/* On-Chip Debug System */ -typedef struct OCD_struct -{ - register8_t OCDR0; /* OCD Register 0 */ - register8_t OCDR1; /* OCD Register 1 */ -} OCD_t; - - -/* CCP signatures */ -typedef enum CCP_enum -{ - CCP_SPM_gc = (0x9D<<0), /* SPM Instruction Protection */ - CCP_IOREG_gc = (0xD8<<0), /* IO Register Protection */ -} CCP_t; - - -/* --------------------------------------------------------------------------- -CLK - Clock System --------------------------------------------------------------------------- -*/ - -/* Clock System */ -typedef struct CLK_struct -{ - register8_t CTRL; /* Control Register */ - register8_t PSCTRL; /* Prescaler Control Register */ - register8_t LOCK; /* Lock register */ - register8_t RTCCTRL; /* RTC Control Register */ -} CLK_t; - -/* --------------------------------------------------------------------------- -CLK - Clock System --------------------------------------------------------------------------- -*/ - -/* Power Reduction */ -typedef struct PR_struct -{ - register8_t PRGEN; /* General Power Reduction */ - register8_t PRPA; /* Power Reduction Port A */ - register8_t PRPB; /* Power Reduction Port B */ - register8_t PRPC; /* Power Reduction Port C */ - register8_t PRPD; /* Power Reduction Port D */ - register8_t PRPE; /* Power Reduction Port E */ - register8_t PRPF; /* Power Reduction Port F */ -} PR_t; - -/* System Clock Selection */ -typedef enum CLK_SCLKSEL_enum -{ - CLK_SCLKSEL_RC2M_gc = (0x00<<0), /* Internal 2MHz RC Oscillator */ - CLK_SCLKSEL_RC32M_gc = (0x01<<0), /* Internal 32MHz RC Oscillator */ - CLK_SCLKSEL_RC32K_gc = (0x02<<0), /* Internal 32kHz RC Oscillator */ - CLK_SCLKSEL_XOSC_gc = (0x03<<0), /* External Crystal Oscillator or Clock */ - CLK_SCLKSEL_PLL_gc = (0x04<<0), /* Phase Locked Loop */ -} CLK_SCLKSEL_t; - -/* Prescaler A Division Factor */ -typedef enum CLK_PSADIV_enum -{ - CLK_PSADIV_1_gc = (0x00<<2), /* Divide by 1 */ - CLK_PSADIV_2_gc = (0x01<<2), /* Divide by 2 */ - CLK_PSADIV_4_gc = (0x03<<2), /* Divide by 4 */ - CLK_PSADIV_8_gc = (0x05<<2), /* Divide by 8 */ - CLK_PSADIV_16_gc = (0x07<<2), /* Divide by 16 */ - CLK_PSADIV_32_gc = (0x09<<2), /* Divide by 32 */ - CLK_PSADIV_64_gc = (0x0B<<2), /* Divide by 64 */ - CLK_PSADIV_128_gc = (0x0D<<2), /* Divide by 128 */ - CLK_PSADIV_256_gc = (0x0F<<2), /* Divide by 256 */ - CLK_PSADIV_512_gc = (0x11<<2), /* Divide by 512 */ -} CLK_PSADIV_t; - -/* Prescaler B and C Division Factor */ -typedef enum CLK_PSBCDIV_enum -{ - CLK_PSBCDIV_1_1_gc = (0x00<<0), /* Divide B by 1 and C by 1 */ - CLK_PSBCDIV_1_2_gc = (0x01<<0), /* Divide B by 1 and C by 2 */ - CLK_PSBCDIV_4_1_gc = (0x02<<0), /* Divide B by 4 and C by 1 */ - CLK_PSBCDIV_2_2_gc = (0x03<<0), /* Divide B by 2 and C by 2 */ -} CLK_PSBCDIV_t; - -/* RTC Clock Source */ -typedef enum CLK_RTCSRC_enum -{ - CLK_RTCSRC_ULP_gc = (0x00<<1), /* 1kHz from internal 32kHz ULP */ - CLK_RTCSRC_TOSC_gc = (0x01<<1), /* 1kHz from 32kHz crystal oscillator on TOSC */ - CLK_RTCSRC_RCOSC_gc = (0x02<<1), /* 1kHz from internal 32kHz RC oscillator */ - CLK_RTCSRC_TOSC32_gc = (0x05<<1), /* 32kHz from 32kHz crystal oscillator on TOSC */ -} CLK_RTCSRC_t; - - -/* --------------------------------------------------------------------------- -SLEEP - Sleep Controller --------------------------------------------------------------------------- -*/ - -/* Sleep Controller */ -typedef struct SLEEP_struct -{ - register8_t CTRL; /* Control Register */ -} SLEEP_t; - -/* Sleep Mode */ -typedef enum SLEEP_SMODE_enum -{ - SLEEP_SMODE_IDLE_gc = (0x00<<1), /* Idle mode */ - SLEEP_SMODE_PDOWN_gc = (0x02<<1), /* Power-down Mode */ - SLEEP_SMODE_PSAVE_gc = (0x03<<1), /* Power-save Mode */ - SLEEP_SMODE_STDBY_gc = (0x06<<1), /* Standby Mode */ - SLEEP_SMODE_ESTDBY_gc = (0x07<<1), /* Extended Standby Mode */ -} SLEEP_SMODE_t; - - -#define SLEEP_MODE_IDLE (0x00<<1) -#define SLEEP_MODE_PWR_DOWN (0x02<<1) -#define SLEEP_MODE_PWR_SAVE (0x03<<1) -#define SLEEP_MODE_STANDBY (0x06<<1) -#define SLEEP_MODE_EXT_STANDBY (0x07<<1) - - -/* --------------------------------------------------------------------------- -OSC - Oscillator --------------------------------------------------------------------------- -*/ - -/* Oscillator */ -typedef struct OSC_struct -{ - register8_t CTRL; /* Control Register */ - register8_t STATUS; /* Status Register */ - register8_t XOSCCTRL; /* External Oscillator Control Register */ - register8_t XOSCFAIL; /* External Oscillator Failure Detection Register */ - register8_t RC32KCAL; /* 32kHz Internal Oscillator Calibration Register */ - register8_t PLLCTRL; /* PLL Control REgister */ - register8_t DFLLCTRL; /* DFLL Control Register */ -} OSC_t; - -/* Oscillator Frequency Range */ -typedef enum OSC_FRQRANGE_enum -{ - OSC_FRQRANGE_04TO2_gc = (0x00<<6), /* 0.4 - 2 MHz */ - OSC_FRQRANGE_2TO9_gc = (0x01<<6), /* 2 - 9 MHz */ - OSC_FRQRANGE_9TO12_gc = (0x02<<6), /* 9 - 12 MHz */ - OSC_FRQRANGE_12TO16_gc = (0x03<<6), /* 12 - 16 MHz */ -} OSC_FRQRANGE_t; - -/* External Oscillator Selection and Startup Time */ -typedef enum OSC_XOSCSEL_enum -{ - OSC_XOSCSEL_EXTCLK_gc = (0x00<<0), /* External Clock - 6 CLK */ - OSC_XOSCSEL_32KHz_gc = (0x02<<0), /* 32kHz TOSC - 32K CLK */ - OSC_XOSCSEL_XTAL_256CLK_gc = (0x03<<0), /* 0.4-16MHz XTAL - 256 CLK */ - OSC_XOSCSEL_XTAL_1KCLK_gc = (0x07<<0), /* 0.4-16MHz XTAL - 1K CLK */ - OSC_XOSCSEL_XTAL_16KCLK_gc = (0x0B<<0), /* 0.4-16MHz XTAL - 16K CLK */ -} OSC_XOSCSEL_t; - -/* PLL Clock Source */ -typedef enum OSC_PLLSRC_enum -{ - OSC_PLLSRC_RC2M_gc = (0x00<<6), /* Internal 2MHz RC Oscillator */ - OSC_PLLSRC_RC32M_gc = (0x02<<6), /* Internal 32MHz RC Oscillator */ - OSC_PLLSRC_XOSC_gc = (0x03<<6), /* External Oscillator */ -} OSC_PLLSRC_t; - - -/* --------------------------------------------------------------------------- -DFLL - DFLL --------------------------------------------------------------------------- -*/ - -/* DFLL */ -typedef struct DFLL_struct -{ - register8_t CTRL; /* Control Register */ - register8_t reserved_0x01; - register8_t CALA; /* Calibration Register A */ - register8_t CALB; /* Calibration Register B */ - register8_t COMP0; /* Oscillator Compare Register 0 */ - register8_t COMP1; /* Oscillator Compare Register 1 */ - register8_t COMP2; /* Oscillator Compare Register 2 */ - register8_t reserved_0x07; -} DFLL_t; - - -/* --------------------------------------------------------------------------- -RST - Reset --------------------------------------------------------------------------- -*/ - -/* Reset */ -typedef struct RST_struct -{ - register8_t STATUS; /* Status Register */ - register8_t CTRL; /* Control Register */ -} RST_t; - - -/* --------------------------------------------------------------------------- -WDT - Watch-Dog Timer --------------------------------------------------------------------------- -*/ - -/* Watch-Dog Timer */ -typedef struct WDT_struct -{ - register8_t CTRL; /* Control */ - register8_t WINCTRL; /* Windowed Mode Control */ - register8_t STATUS; /* Status */ -} WDT_t; - -/* Period setting */ -typedef enum WDT_PER_enum -{ - WDT_PER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ - WDT_PER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ - WDT_PER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ - WDT_PER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ - WDT_PER_128CLK_gc = (0x04<<2), /* 128 cycles (0.125s @ 3.3V) */ - WDT_PER_256CLK_gc = (0x05<<2), /* 256 cycles (0.25s @ 3.3V) */ - WDT_PER_512CLK_gc = (0x06<<2), /* 512 cycles (0.5s @ 3.3V) */ - WDT_PER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ - WDT_PER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ - WDT_PER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ - WDT_PER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ -} WDT_PER_t; - -/* Closed window period */ -typedef enum WDT_WPER_enum -{ - WDT_WPER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ - WDT_WPER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ - WDT_WPER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ - WDT_WPER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ - WDT_WPER_128CLK_gc = (0x04<<2), /* 128 cycles (0.125s @ 3.3V) */ - WDT_WPER_256CLK_gc = (0x05<<2), /* 256 cycles (0.25s @ 3.3V) */ - WDT_WPER_512CLK_gc = (0x06<<2), /* 512 cycles (0.5s @ 3.3V) */ - WDT_WPER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ - WDT_WPER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ - WDT_WPER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ - WDT_WPER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ -} WDT_WPER_t; - - -/* --------------------------------------------------------------------------- -MCU - MCU Control --------------------------------------------------------------------------- -*/ - -/* MCU Control */ -typedef struct MCU_struct -{ - register8_t DEVID0; /* Device ID byte 0 */ - register8_t DEVID1; /* Device ID byte 1 */ - register8_t DEVID2; /* Device ID byte 2 */ - register8_t REVID; /* Revision ID */ - register8_t JTAGUID; /* JTAG User ID */ - register8_t reserved_0x05; - register8_t MCUCR; /* MCU Control */ - register8_t reserved_0x07; - register8_t EVSYSLOCK; /* Event System Lock */ - register8_t AWEXLOCK; /* AWEX Lock */ - register8_t reserved_0x0A; - register8_t reserved_0x0B; -} MCU_t; - - -/* --------------------------------------------------------------------------- -PMIC - Programmable Multi-level Interrupt Controller --------------------------------------------------------------------------- -*/ - -/* Programmable Multi-level Interrupt Controller */ -typedef struct PMIC_struct -{ - register8_t STATUS; /* Status Register */ - register8_t INTPRI; /* Interrupt Priority */ - register8_t CTRL; /* Control Register */ -} PMIC_t; - - - -/* --------------------------------------------------------------------------- -CRC - Cyclic Redundancy Checker --------------------------------------------------------------------------- -*/ - -/* Cyclic Redundancy Checker */ -typedef struct CRC_struct -{ - register8_t CTRL; /* Control Register */ - register8_t STATUS; /* Status Register */ - register8_t reserved_0x02; - register8_t DATAIN; /* Data Input */ - register8_t CHECKSUM0; /* Checksum byte 0 */ - register8_t CHECKSUM1; /* Checksum byte 1 */ - register8_t CHECKSUM2; /* Checksum byte 2 */ - register8_t CHECKSUM3; /* Checksum byte 3 */ -} CRC_t; - -/* Reset */ -typedef enum CRC_RESET_enum -{ - CRC_RESET_NO_gc = (0x00<<6), /* No Reset */ - CRC_RESET_RESET0_gc = (0x02<<6), /* Reset CRC with CHECKSUM to all zeros */ - CRC_RESET_RESET1_gc = (0x03<<6), /* Reset CRC with CHECKSUM to all ones */ -} CRC_RESET_t; - -/* Input Source */ -typedef enum CRC_SOURCE_enum -{ - CRC_SOURCE_DISABLE_gc = (0x00<<0), /* Disabled */ - CRC_SOURCE_IO_gc = (0x01<<0), /* I/O Interface */ - CRC_SOURCE_FLASH_gc = (0x02<<0), /* Flash */ -} CRC_SOURCE_t; - - -/* --------------------------------------------------------------------------- -EVSYS - Event System --------------------------------------------------------------------------- -*/ - -/* Event System */ -typedef struct EVSYS_struct -{ - register8_t CH0MUX; /* Event Channel 0 Multiplexer */ - register8_t CH1MUX; /* Event Channel 1 Multiplexer */ - register8_t CH2MUX; /* Event Channel 2 Multiplexer */ - register8_t CH3MUX; /* Event Channel 3 Multiplexer */ - register8_t reserved_0x04; - register8_t reserved_0x05; - register8_t reserved_0x06; - register8_t reserved_0x07; - register8_t CH0CTRL; /* Channel 0 Control Register */ - register8_t CH1CTRL; /* Channel 1 Control Register */ - register8_t CH2CTRL; /* Channel 2 Control Register */ - register8_t CH3CTRL; /* Channel 3 Control Register */ - register8_t reserved_0x0C; - register8_t reserved_0x0D; - register8_t reserved_0x0E; - register8_t reserved_0x0F; - register8_t STROBE; /* Event Strobe */ - register8_t DATA; /* Event Data */ -} EVSYS_t; - -/* Quadrature Decoder Index Recognition Mode */ -typedef enum EVSYS_QDIRM_enum -{ - EVSYS_QDIRM_00_gc = (0x00<<5), /* QDPH0 = 0, QDPH90 = 0 */ - EVSYS_QDIRM_01_gc = (0x01<<5), /* QDPH0 = 0, QDPH90 = 1 */ - EVSYS_QDIRM_10_gc = (0x02<<5), /* QDPH0 = 1, QDPH90 = 0 */ - EVSYS_QDIRM_11_gc = (0x03<<5), /* QDPH0 = 1, QDPH90 = 1 */ -} EVSYS_QDIRM_t; - -/* Digital filter coefficient */ -typedef enum EVSYS_DIGFILT_enum -{ - EVSYS_DIGFILT_1SAMPLE_gc = (0x00<<0), /* 1 SAMPLE */ - EVSYS_DIGFILT_2SAMPLES_gc = (0x01<<0), /* 2 SAMPLES */ - EVSYS_DIGFILT_3SAMPLES_gc = (0x02<<0), /* 3 SAMPLES */ - EVSYS_DIGFILT_4SAMPLES_gc = (0x03<<0), /* 4 SAMPLES */ - EVSYS_DIGFILT_5SAMPLES_gc = (0x04<<0), /* 5 SAMPLES */ - EVSYS_DIGFILT_6SAMPLES_gc = (0x05<<0), /* 6 SAMPLES */ - EVSYS_DIGFILT_7SAMPLES_gc = (0x06<<0), /* 7 SAMPLES */ - EVSYS_DIGFILT_8SAMPLES_gc = (0x07<<0), /* 8 SAMPLES */ -} EVSYS_DIGFILT_t; - -/* Event Channel multiplexer input selection */ -typedef enum EVSYS_CHMUX_enum -{ - EVSYS_CHMUX_OFF_gc = (0x00<<0), /* Off */ - EVSYS_CHMUX_RTC_OVF_gc = (0x08<<0), /* RTC Overflow */ - EVSYS_CHMUX_RTC_CMP_gc = (0x09<<0), /* RTC Compare Match */ - EVSYS_CHMUX_ACA_CH0_gc = (0x10<<0), /* Analog Comparator A Channel 0 */ - EVSYS_CHMUX_ACA_CH1_gc = (0x11<<0), /* Analog Comparator A Channel 1 */ - EVSYS_CHMUX_ACA_WIN_gc = (0x12<<0), /* Analog Comparator A Window */ - EVSYS_CHMUX_ADCA_CH0_gc = (0x20<<0), /* ADC A Channel 0 */ - EVSYS_CHMUX_PORTA_PIN0_gc = (0x50<<0), /* Port A, Pin0 */ - EVSYS_CHMUX_PORTA_PIN1_gc = (0x51<<0), /* Port A, Pin1 */ - EVSYS_CHMUX_PORTA_PIN2_gc = (0x52<<0), /* Port A, Pin2 */ - EVSYS_CHMUX_PORTA_PIN3_gc = (0x53<<0), /* Port A, Pin3 */ - EVSYS_CHMUX_PORTA_PIN4_gc = (0x54<<0), /* Port A, Pin4 */ - EVSYS_CHMUX_PORTA_PIN5_gc = (0x55<<0), /* Port A, Pin5 */ - EVSYS_CHMUX_PORTA_PIN6_gc = (0x56<<0), /* Port A, Pin6 */ - EVSYS_CHMUX_PORTA_PIN7_gc = (0x57<<0), /* Port A, Pin7 */ - EVSYS_CHMUX_PORTB_PIN0_gc = (0x58<<0), /* Port B, Pin0 */ - EVSYS_CHMUX_PORTB_PIN1_gc = (0x59<<0), /* Port B, Pin1 */ - EVSYS_CHMUX_PORTB_PIN2_gc = (0x5A<<0), /* Port B, Pin2 */ - EVSYS_CHMUX_PORTB_PIN3_gc = (0x5B<<0), /* Port B, Pin3 */ - EVSYS_CHMUX_PORTB_PIN4_gc = (0x5C<<0), /* Port B, Pin4 */ - EVSYS_CHMUX_PORTB_PIN5_gc = (0x5D<<0), /* Port B, Pin5 */ - EVSYS_CHMUX_PORTB_PIN6_gc = (0x5E<<0), /* Port B, Pin6 */ - EVSYS_CHMUX_PORTB_PIN7_gc = (0x5F<<0), /* Port B, Pin7 */ - EVSYS_CHMUX_PORTC_PIN0_gc = (0x60<<0), /* Port C, Pin0 */ - EVSYS_CHMUX_PORTC_PIN1_gc = (0x61<<0), /* Port C, Pin1 */ - EVSYS_CHMUX_PORTC_PIN2_gc = (0x62<<0), /* Port C, Pin2 */ - EVSYS_CHMUX_PORTC_PIN3_gc = (0x63<<0), /* Port C, Pin3 */ - EVSYS_CHMUX_PORTC_PIN4_gc = (0x64<<0), /* Port C, Pin4 */ - EVSYS_CHMUX_PORTC_PIN5_gc = (0x65<<0), /* Port C, Pin5 */ - EVSYS_CHMUX_PORTC_PIN6_gc = (0x66<<0), /* Port C, Pin6 */ - EVSYS_CHMUX_PORTC_PIN7_gc = (0x67<<0), /* Port C, Pin7 */ - EVSYS_CHMUX_PORTD_PIN0_gc = (0x68<<0), /* Port D, Pin0 */ - EVSYS_CHMUX_PORTD_PIN1_gc = (0x69<<0), /* Port D, Pin1 */ - EVSYS_CHMUX_PORTD_PIN2_gc = (0x6A<<0), /* Port D, Pin2 */ - EVSYS_CHMUX_PORTD_PIN3_gc = (0x6B<<0), /* Port D, Pin3 */ - EVSYS_CHMUX_PORTD_PIN4_gc = (0x6C<<0), /* Port D, Pin4 */ - EVSYS_CHMUX_PORTD_PIN5_gc = (0x6D<<0), /* Port D, Pin5 */ - EVSYS_CHMUX_PORTD_PIN6_gc = (0x6E<<0), /* Port D, Pin6 */ - EVSYS_CHMUX_PORTD_PIN7_gc = (0x6F<<0), /* Port D, Pin7 */ - EVSYS_CHMUX_PORTE_PIN0_gc = (0x70<<0), /* Port E, Pin0 */ - EVSYS_CHMUX_PORTE_PIN1_gc = (0x71<<0), /* Port E, Pin1 */ - EVSYS_CHMUX_PORTE_PIN2_gc = (0x72<<0), /* Port E, Pin2 */ - EVSYS_CHMUX_PORTE_PIN3_gc = (0x73<<0), /* Port E, Pin3 */ - EVSYS_CHMUX_PORTE_PIN4_gc = (0x74<<0), /* Port E, Pin4 */ - EVSYS_CHMUX_PORTE_PIN5_gc = (0x75<<0), /* Port E, Pin5 */ - EVSYS_CHMUX_PORTE_PIN6_gc = (0x76<<0), /* Port E, Pin6 */ - EVSYS_CHMUX_PORTE_PIN7_gc = (0x77<<0), /* Port E, Pin7 */ - EVSYS_CHMUX_PORTF_PIN0_gc = (0x78<<0), /* Port F, Pin0 */ - EVSYS_CHMUX_PORTF_PIN1_gc = (0x79<<0), /* Port F, Pin1 */ - EVSYS_CHMUX_PORTF_PIN2_gc = (0x7A<<0), /* Port F, Pin2 */ - EVSYS_CHMUX_PORTF_PIN3_gc = (0x7B<<0), /* Port F, Pin3 */ - EVSYS_CHMUX_PORTF_PIN4_gc = (0x7C<<0), /* Port F, Pin4 */ - EVSYS_CHMUX_PORTF_PIN5_gc = (0x7D<<0), /* Port F, Pin5 */ - EVSYS_CHMUX_PORTF_PIN6_gc = (0x7E<<0), /* Port F, Pin6 */ - EVSYS_CHMUX_PORTF_PIN7_gc = (0x7F<<0), /* Port F, Pin7 */ - EVSYS_CHMUX_PRESCALER_1_gc = (0x80<<0), /* Prescaler, divide by 1 */ - EVSYS_CHMUX_PRESCALER_2_gc = (0x81<<0), /* Prescaler, divide by 2 */ - EVSYS_CHMUX_PRESCALER_4_gc = (0x82<<0), /* Prescaler, divide by 4 */ - EVSYS_CHMUX_PRESCALER_8_gc = (0x83<<0), /* Prescaler, divide by 8 */ - EVSYS_CHMUX_PRESCALER_16_gc = (0x84<<0), /* Prescaler, divide by 16 */ - EVSYS_CHMUX_PRESCALER_32_gc = (0x85<<0), /* Prescaler, divide by 32 */ - EVSYS_CHMUX_PRESCALER_64_gc = (0x86<<0), /* Prescaler, divide by 64 */ - EVSYS_CHMUX_PRESCALER_128_gc = (0x87<<0), /* Prescaler, divide by 128 */ - EVSYS_CHMUX_PRESCALER_256_gc = (0x88<<0), /* Prescaler, divide by 256 */ - EVSYS_CHMUX_PRESCALER_512_gc = (0x89<<0), /* Prescaler, divide by 512 */ - EVSYS_CHMUX_PRESCALER_1024_gc = (0x8A<<0), /* Prescaler, divide by 1024 */ - EVSYS_CHMUX_PRESCALER_2048_gc = (0x8B<<0), /* Prescaler, divide by 2048 */ - EVSYS_CHMUX_PRESCALER_4096_gc = (0x8C<<0), /* Prescaler, divide by 4096 */ - EVSYS_CHMUX_PRESCALER_8192_gc = (0x8D<<0), /* Prescaler, divide by 8192 */ - EVSYS_CHMUX_PRESCALER_16384_gc = (0x8E<<0), /* Prescaler, divide by 16384 */ - EVSYS_CHMUX_PRESCALER_32768_gc = (0x8F<<0), /* Prescaler, divide by 32768 */ - EVSYS_CHMUX_TCC0_OVF_gc = (0xC0<<0), /* Timer/Counter C0 Overflow */ - EVSYS_CHMUX_TCC0_ERR_gc = (0xC1<<0), /* Timer/Counter C0 Error */ - EVSYS_CHMUX_TCC0_CCA_gc = (0xC4<<0), /* Timer/Counter C0 Compare or Capture A */ - EVSYS_CHMUX_TCC0_CCB_gc = (0xC5<<0), /* Timer/Counter C0 Compare or Capture B */ - EVSYS_CHMUX_TCC0_CCC_gc = (0xC6<<0), /* Timer/Counter C0 Compare or Capture C */ - EVSYS_CHMUX_TCC0_CCD_gc = (0xC7<<0), /* Timer/Counter C0 Compare or Capture D */ - EVSYS_CHMUX_TCC1_OVF_gc = (0xC8<<0), /* Timer/Counter C1 Overflow */ - EVSYS_CHMUX_TCC1_ERR_gc = (0xC9<<0), /* Timer/Counter C1 Error */ - EVSYS_CHMUX_TCC1_CCA_gc = (0xCC<<0), /* Timer/Counter C1 Compare or Capture A */ - EVSYS_CHMUX_TCC1_CCB_gc = (0xCD<<0), /* Timer/Counter C1 Compare or Capture B */ - EVSYS_CHMUX_TCD0_OVF_gc = (0xD0<<0), /* Timer/Counter D0 Overflow */ - EVSYS_CHMUX_TCD0_ERR_gc = (0xD1<<0), /* Timer/Counter D0 Error */ - EVSYS_CHMUX_TCD0_CCA_gc = (0xD4<<0), /* Timer/Counter D0 Compare or Capture A */ - EVSYS_CHMUX_TCD0_CCB_gc = (0xD5<<0), /* Timer/Counter D0 Compare or Capture B */ - EVSYS_CHMUX_TCD0_CCC_gc = (0xD6<<0), /* Timer/Counter D0 Compare or Capture C */ - EVSYS_CHMUX_TCD0_CCD_gc = (0xD7<<0), /* Timer/Counter D0 Compare or Capture D */ - EVSYS_CHMUX_TCD1_OVF_gc = (0xD8<<0), /* Timer/Counter D1 Overflow */ - EVSYS_CHMUX_TCD1_ERR_gc = (0xD9<<0), /* Timer/Counter D1 Error */ - EVSYS_CHMUX_TCD1_CCA_gc = (0xDC<<0), /* Timer/Counter D1 Compare or Capture A */ - EVSYS_CHMUX_TCD1_CCB_gc = (0xDD<<0), /* Timer/Counter D1 Compare or Capture B */ - EVSYS_CHMUX_TCE0_OVF_gc = (0xE0<<0), /* Timer/Counter E0 Overflow */ - EVSYS_CHMUX_TCE0_ERR_gc = (0xE1<<0), /* Timer/Counter E0 Error */ - EVSYS_CHMUX_TCE0_CCA_gc = (0xE4<<0), /* Timer/Counter E0 Compare or Capture A */ - EVSYS_CHMUX_TCE0_CCB_gc = (0xE5<<0), /* Timer/Counter E0 Compare or Capture B */ - EVSYS_CHMUX_TCE0_CCC_gc = (0xE6<<0), /* Timer/Counter E0 Compare or Capture C */ - EVSYS_CHMUX_TCE0_CCD_gc = (0xE7<<0), /* Timer/Counter E0 Compare or Capture D */ - EVSYS_CHMUX_TCE1_OVF_gc = (0xE8<<0), /* Timer/Counter E1 Overflow */ - EVSYS_CHMUX_TCE1_ERR_gc = (0xE9<<0), /* Timer/Counter E1 Error */ - EVSYS_CHMUX_TCE1_CCA_gc = (0xEC<<0), /* Timer/Counter E1 Compare or Capture A */ - EVSYS_CHMUX_TCE1_CCB_gc = (0xED<<0), /* Timer/Counter E1 Compare or Capture B */ - EVSYS_CHMUX_TCF0_OVF_gc = (0xF0<<0), /* Timer/Counter F0 Overflow */ - EVSYS_CHMUX_TCF0_ERR_gc = (0xF1<<0), /* Timer/Counter F0 Error */ - EVSYS_CHMUX_TCF0_CCA_gc = (0xF4<<0), /* Timer/Counter F0 Compare or Capture A */ - EVSYS_CHMUX_TCF0_CCB_gc = (0xF5<<0), /* Timer/Counter F0 Compare or Capture B */ - EVSYS_CHMUX_TCF0_CCC_gc = (0xF6<<0), /* Timer/Counter F0 Compare or Capture C */ - EVSYS_CHMUX_TCF0_CCD_gc = (0xF7<<0), /* Timer/Counter F0 Compare or Capture D */ - EVSYS_CHMUX_TCF1_OVF_gc = (0xF8<<0), /* Timer/Counter F1 Overflow */ - EVSYS_CHMUX_TCF1_ERR_gc = (0xF9<<0), /* Timer/Counter F1 Error */ - EVSYS_CHMUX_TCF1_CCA_gc = (0xFC<<0), /* Timer/Counter F1 Compare or Capture A */ - EVSYS_CHMUX_TCF1_CCB_gc = (0xFD<<0), /* Timer/Counter F1 Compare or Capture B */ -} EVSYS_CHMUX_t; - - -/* --------------------------------------------------------------------------- -NVM - Non Volatile Memory Controller --------------------------------------------------------------------------- -*/ - -/* Non-volatile Memory Controller */ -typedef struct NVM_struct -{ - register8_t ADDR0; /* Address Register 0 */ - register8_t ADDR1; /* Address Register 1 */ - register8_t ADDR2; /* Address Register 2 */ - register8_t reserved_0x03; - register8_t DATA0; /* Data Register 0 */ - register8_t DATA1; /* Data Register 1 */ - register8_t DATA2; /* Data Register 2 */ - register8_t reserved_0x07; - register8_t reserved_0x08; - register8_t reserved_0x09; - register8_t CMD; /* Command */ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t INTCTRL; /* Interrupt Control */ - register8_t reserved_0x0E; - register8_t STATUS; /* Status */ - register8_t LOCK_BITS; /* Lock Bits */ -} NVM_t; - -/* --------------------------------------------------------------------------- -NVM - Non Volatile Memory Controller --------------------------------------------------------------------------- -*/ - -/* Lock Bits */ -typedef struct NVM_LOCKBITS_struct -{ - register8_t LOCKBITS; /* Lock Bits */ -} NVM_LOCKBITS_t; - -/* --------------------------------------------------------------------------- -NVM - Non Volatile Memory Controller --------------------------------------------------------------------------- -*/ - -/* Fuses */ -typedef struct NVM_FUSES_struct -{ - register8_t FUSEBYTE0; /* User ID */ - register8_t FUSEBYTE1; /* Watchdog Configuration */ - register8_t FUSEBYTE2; /* Reset Configuration */ - register8_t reserved_0x03; - register8_t FUSEBYTE4; /* Start-up Configuration */ - register8_t FUSEBYTE5; /* EESAVE and BOD Level */ -} NVM_FUSES_t; - -/* --------------------------------------------------------------------------- -NVM - Non Volatile Memory Controller --------------------------------------------------------------------------- -*/ - -/* Production Signatures */ -typedef struct NVM_PROD_SIGNATURES_struct -{ - register8_t RCOSC2M; /* RCOSC 2MHz Calibration Value */ - register8_t reserved_0x01; - register8_t RCOSC32K; /* RCOSC 32kHz Calibration Value */ - register8_t RCOSC32M; /* RCOSC 32MHz Calibration Value */ - register8_t reserved_0x04; - register8_t reserved_0x05; - register8_t reserved_0x06; - register8_t reserved_0x07; - register8_t LOTNUM0; /* Lot Number Byte 0, ASCII */ - register8_t LOTNUM1; /* Lot Number Byte 1, ASCII */ - register8_t LOTNUM2; /* Lot Number Byte 2, ASCII */ - register8_t LOTNUM3; /* Lot Number Byte 3, ASCII */ - register8_t LOTNUM4; /* Lot Number Byte 4, ASCII */ - register8_t LOTNUM5; /* Lot Number Byte 5, ASCII */ - register8_t reserved_0x0E; - register8_t reserved_0x0F; - register8_t WAFNUM; /* Wafer Number */ - register8_t reserved_0x11; - register8_t COORDX0; /* Wafer Coordinate X Byte 0 */ - register8_t COORDX1; /* Wafer Coordinate X Byte 1 */ - register8_t COORDY0; /* Wafer Coordinate Y Byte 0 */ - register8_t COORDY1; /* Wafer Coordinate Y Byte 1 */ - register8_t reserved_0x16; - register8_t reserved_0x17; - register8_t reserved_0x18; - register8_t reserved_0x19; - register8_t reserved_0x1A; - register8_t reserved_0x1B; - register8_t reserved_0x1C; - register8_t reserved_0x1D; - register8_t reserved_0x1E; - register8_t reserved_0x1F; - register8_t ADCACAL0; /* ADCA Calibration Byte 0 */ - register8_t ADCACAL1; /* ADCA Calibration Byte 1 */ - register8_t reserved_0x22; - register8_t reserved_0x23; - register8_t ADCBCAL0; /* ADCB Calibration Byte 0 */ - register8_t ADCBCAL1; /* ADCB Calibration Byte 1 */ - register8_t reserved_0x26; - register8_t reserved_0x27; - register8_t reserved_0x28; - register8_t reserved_0x29; - register8_t reserved_0x2A; - register8_t reserved_0x2B; - register8_t reserved_0x2C; - register8_t reserved_0x2D; - register8_t TEMPSENSE0; /* Temperature Sensor Calibration Byte 0 */ - register8_t TEMPSENSE1; /* Temperature Sensor Calibration Byte 0 */ - register8_t DACAOFFCAL; /* DACA Calibration Byte 0 */ - register8_t DACAGAINCAL; /* DACA Calibration Byte 1 */ - register8_t DACBOFFCAL; /* DACB Calibration Byte 0 */ - register8_t DACBGAINCAL; /* DACB Calibration Byte 1 */ - register8_t reserved_0x34; - register8_t reserved_0x35; - register8_t reserved_0x36; - register8_t reserved_0x37; - register8_t reserved_0x38; - register8_t reserved_0x39; - register8_t reserved_0x3A; - register8_t reserved_0x3B; - register8_t reserved_0x3C; - register8_t reserved_0x3D; - register8_t reserved_0x3E; -} NVM_PROD_SIGNATURES_t; - -/* NVM Command */ -typedef enum NVM_CMD_enum -{ - NVM_CMD_NO_OPERATION_gc = (0x00<<0), /* Noop/Ordinary LPM */ - NVM_CMD_READ_CALIB_ROW_gc = (0x02<<0), /* Read calibration row */ - NVM_CMD_READ_USER_SIG_ROW_gc = (0x01<<0), /* Read user signature row */ - NVM_CMD_READ_EEPROM_gc = (0x06<<0), /* Read EEPROM */ - NVM_CMD_READ_FUSES_gc = (0x07<<0), /* Read fuse byte */ - NVM_CMD_WRITE_LOCK_BITS_gc = (0x08<<0), /* Write lock bits */ - NVM_CMD_ERASE_USER_SIG_ROW_gc = (0x18<<0), /* Erase user signature row */ - NVM_CMD_WRITE_USER_SIG_ROW_gc = (0x1A<<0), /* Write user signature row */ - NVM_CMD_ERASE_APP_gc = (0x20<<0), /* Erase Application Section */ - NVM_CMD_ERASE_APP_PAGE_gc = (0x22<<0), /* Erase Application Section page */ - NVM_CMD_LOAD_FLASH_BUFFER_gc = (0x23<<0), /* Load Flash page buffer */ - NVM_CMD_WRITE_APP_PAGE_gc = (0x24<<0), /* Write Application Section page */ - NVM_CMD_ERASE_WRITE_APP_PAGE_gc = (0x25<<0), /* Erase-and-write Application Section page */ - NVM_CMD_ERASE_FLASH_BUFFER_gc = (0x26<<0), /* Erase/flush Flash page buffer */ - NVM_CMD_ERASE_BOOT_PAGE_gc = (0x2A<<0), /* Erase Boot Section page */ - NVM_CMD_WRITE_BOOT_PAGE_gc = (0x2C<<0), /* Write Boot Section page */ - NVM_CMD_ERASE_WRITE_BOOT_PAGE_gc = (0x2D<<0), /* Erase-and-write Boot Section page */ - NVM_CMD_ERASE_EEPROM_gc = (0x30<<0), /* Erase EEPROM */ - NVM_CMD_ERASE_EEPROM_PAGE_gc = (0x32<<0), /* Erase EEPROM page */ - NVM_CMD_LOAD_EEPROM_BUFFER_gc = (0x33<<0), /* Load EEPROM page buffer */ - NVM_CMD_WRITE_EEPROM_PAGE_gc = (0x34<<0), /* Write EEPROM page */ - NVM_CMD_ERASE_WRITE_EEPROM_PAGE_gc = (0x35<<0), /* Erase-and-write EEPROM page */ - NVM_CMD_ERASE_EEPROM_BUFFER_gc = (0x36<<0), /* Erase/flush EEPROM page buffer */ - NVM_CMD_APP_CRC_gc = (0x38<<0), /* Generate Application section CRC */ - NVM_CMD_BOOT_CRC_gc = (0x39<<0), /* Generate Boot Section CRC */ - NVM_CMD_FLASH_RANGE_CRC_gc = (0x3A<<0), /* Generate Flash Range CRC */ -} NVM_CMD_t; - -/* SPM ready interrupt level */ -typedef enum NVM_SPMLVL_enum -{ - NVM_SPMLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ - NVM_SPMLVL_LO_gc = (0x01<<2), /* Low level */ - NVM_SPMLVL_MED_gc = (0x02<<2), /* Medium level */ - NVM_SPMLVL_HI_gc = (0x03<<2), /* High level */ -} NVM_SPMLVL_t; - -/* EEPROM ready interrupt level */ -typedef enum NVM_EELVL_enum -{ - NVM_EELVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ - NVM_EELVL_LO_gc = (0x01<<0), /* Low level */ - NVM_EELVL_MED_gc = (0x02<<0), /* Medium level */ - NVM_EELVL_HI_gc = (0x03<<0), /* High level */ -} NVM_EELVL_t; - -/* Boot lock bits - boot setcion */ -typedef enum NVM_BLBB_enum -{ - NVM_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ - NVM_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ - NVM_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ - NVM_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ -} NVM_BLBB_t; - -/* Boot lock bits - application section */ -typedef enum NVM_BLBA_enum -{ - NVM_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ - NVM_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ - NVM_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ - NVM_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ -} NVM_BLBA_t; - -/* Boot lock bits - application table section */ -typedef enum NVM_BLBAT_enum -{ - NVM_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ - NVM_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ - NVM_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ - NVM_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ -} NVM_BLBAT_t; - -/* Lock bits */ -typedef enum NVM_LB_enum -{ - NVM_LB_NOLOCK_gc = (0x03<<0), /* No locks */ - NVM_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ - NVM_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ -} NVM_LB_t; - -/* Boot Loader Section Reset Vector */ -typedef enum BOOTRST_enum -{ - BOOTRST_BOOTLDR_gc = (0x00<<6), /* Boot Loader Reset */ - BOOTRST_APPLICATION_gc = (0x01<<6), /* Application Reset */ -} BOOTRST_t; - -/* BOD operation */ -typedef enum BOD_enum -{ - BOD_INSAMPLEDMODE_gc = (0x01<<0), /* BOD enabled in sampled mode */ - BOD_CONTINOUSLY_gc = (0x02<<0), /* BOD enabled continuously */ - BOD_DISABLED_gc = (0x03<<0), /* BOD Disabled */ -} BOD_t; - -/* Watchdog (Window) Timeout Period */ -typedef enum WD_enum -{ - WD_8CLK_gc = (0x00<<4), /* 8 cycles (8ms @ 3.3V) */ - WD_16CLK_gc = (0x01<<4), /* 16 cycles (16ms @ 3.3V) */ - WD_32CLK_gc = (0x02<<4), /* 32 cycles (32ms @ 3.3V) */ - WD_64CLK_gc = (0x03<<4), /* 64 cycles (64ms @ 3.3V) */ - WD_128CLK_gc = (0x04<<4), /* 128 cycles (0.125s @ 3.3V) */ - WD_256CLK_gc = (0x05<<4), /* 256 cycles (0.25s @ 3.3V) */ - WD_512CLK_gc = (0x06<<4), /* 512 cycles (0.5s @ 3.3V) */ - WD_1KCLK_gc = (0x07<<4), /* 1K cycles (1s @ 3.3V) */ - WD_2KCLK_gc = (0x08<<4), /* 2K cycles (2s @ 3.3V) */ - WD_4KCLK_gc = (0x09<<4), /* 4K cycles (4s @ 3.3V) */ - WD_8KCLK_gc = (0x0A<<4), /* 8K cycles (8s @ 3.3V) */ -} WD_t; - -/* Start-up Time */ -typedef enum SUT_enum -{ - SUT_0MS_gc = (0x03<<2), /* 0 ms */ - SUT_4MS_gc = (0x01<<2), /* 4 ms */ - SUT_64MS_gc = (0x00<<2), /* 64 ms */ -} SUT_t; - -/* Brown Out Detection Voltage Level */ -typedef enum BODLVL_enum -{ - BODLVL_1V6_gc = (0x07<<0), /* 1.6 V */ - BODLVL_1V8_gc = (0x06<<0), /* 1.8 V */ - BODLVL_2V0_gc = (0x05<<0), /* 2.0 V */ - BODLVL_2V2_gc = (0x04<<0), /* 2.2 V */ - BODLVL_2V4_gc = (0x03<<0), /* 2.4 V */ - BODLVL_2V6_gc = (0x02<<0), /* 2.6 V */ - BODLVL_2V8_gc = (0x01<<0), /* 2.8 V */ - BODLVL_3V0_gc = (0x00<<0), /* 3.0 V */ -} BODLVL_t; - -/* --------------------------------------------------------------------------- -AC - Analog Comparator --------------------------------------------------------------------------- -*/ - -/* Analog Comparator */ -typedef struct AC_struct -{ - register8_t AC0CTRL; /* Comparator 0 Control */ - register8_t AC1CTRL; /* Comparator 1 Control */ - register8_t AC0MUXCTRL; /* Comparator 0 MUX Control */ - register8_t AC1MUXCTRL; /* Comparator 1 MUX Control */ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t WINCTRL; /* Window Mode Control */ - register8_t STATUS; /* Status */ -} AC_t; - -/* Interrupt mode */ -typedef enum AC_INTMODE_enum -{ - AC_INTMODE_BOTHEDGES_gc = (0x00<<6), /* Interrupt on both edges */ - AC_INTMODE_FALLING_gc = (0x02<<6), /* Interrupt on falling edge */ - AC_INTMODE_RISING_gc = (0x03<<6), /* Interrupt on rising edge */ -} AC_INTMODE_t; - -/* Interrupt level */ -typedef enum AC_INTLVL_enum -{ - AC_INTLVL_OFF_gc = (0x00<<4), /* Interrupt disabled */ - AC_INTLVL_LO_gc = (0x01<<4), /* Low level */ - AC_INTLVL_MED_gc = (0x02<<4), /* Medium level */ - AC_INTLVL_HI_gc = (0x03<<4), /* High level */ -} AC_INTLVL_t; - -/* Hysteresis mode selection */ -typedef enum AC_HYSMODE_enum -{ - AC_HYSMODE_NO_gc = (0x00<<1), /* No hysteresis */ - AC_HYSMODE_SMALL_gc = (0x01<<1), /* Small hysteresis */ - AC_HYSMODE_LARGE_gc = (0x02<<1), /* Large hysteresis */ -} AC_HYSMODE_t; - -/* Positive input multiplexer selection */ -typedef enum AC_MUXPOS_enum -{ - AC_MUXPOS_PIN0_gc = (0x00<<3), /* Pin 0 */ - AC_MUXPOS_PIN1_gc = (0x01<<3), /* Pin 1 */ - AC_MUXPOS_PIN2_gc = (0x02<<3), /* Pin 2 */ - AC_MUXPOS_PIN3_gc = (0x03<<3), /* Pin 3 */ - AC_MUXPOS_PIN4_gc = (0x04<<3), /* Pin 4 */ - AC_MUXPOS_PIN5_gc = (0x05<<3), /* Pin 5 */ - AC_MUXPOS_PIN6_gc = (0x06<<3), /* Pin 6 */ - AC_MUXPOS_DAC_gc = (0x07<<3), /* DAC output */ -} AC_MUXPOS_t; - -/* Negative input multiplexer selection */ -typedef enum AC_MUXNEG_enum -{ - AC_MUXNEG_PIN0_gc = (0x00<<0), /* Pin 0 */ - AC_MUXNEG_PIN1_gc = (0x01<<0), /* Pin 1 */ - AC_MUXNEG_PIN3_gc = (0x02<<0), /* Pin 3 */ - AC_MUXNEG_PIN5_gc = (0x03<<0), /* Pin 5 */ - AC_MUXNEG_PIN7_gc = (0x04<<0), /* Pin 7 */ - AC_MUXNEG_DAC_gc = (0x05<<0), /* DAC output */ - AC_MUXNEG_BANDGAP_gc = (0x06<<0), /* Bandgap Reference */ - AC_MUXNEG_SCALER_gc = (0x07<<0), /* Internal voltage scaler */ -} AC_MUXNEG_t; - -/* Windows interrupt mode */ -typedef enum AC_WINTMODE_enum -{ - AC_WINTMODE_ABOVE_gc = (0x00<<2), /* Interrupt on above window */ - AC_WINTMODE_INSIDE_gc = (0x01<<2), /* Interrupt on inside window */ - AC_WINTMODE_BELOW_gc = (0x02<<2), /* Interrupt on below window */ - AC_WINTMODE_OUTSIDE_gc = (0x03<<2), /* Interrupt on outside window */ -} AC_WINTMODE_t; - -/* Window interrupt level */ -typedef enum AC_WINTLVL_enum -{ - AC_WINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ - AC_WINTLVL_LO_gc = (0x01<<0), /* Low priority */ - AC_WINTLVL_MED_gc = (0x02<<0), /* Medium priority */ - AC_WINTLVL_HI_gc = (0x03<<0), /* High priority */ -} AC_WINTLVL_t; - -/* Window mode state */ -typedef enum AC_WSTATE_enum -{ - AC_WSTATE_ABOVE_gc = (0x00<<6), /* Signal above window */ - AC_WSTATE_INSIDE_gc = (0x01<<6), /* Signal inside window */ - AC_WSTATE_BELOW_gc = (0x02<<6), /* Signal below window */ -} AC_WSTATE_t; - - -/* --------------------------------------------------------------------------- -ADC - Analog/Digital Converter --------------------------------------------------------------------------- -*/ - -/* ADC Channel */ -typedef struct ADC_CH_struct -{ - register8_t CTRL; /* Control Register */ - register8_t MUXCTRL; /* MUX Control */ - register8_t INTCTRL; /* Channel Interrupt Control */ - register8_t INTFLAGS; /* Interrupt Flags */ - _WORDREGISTER(RES); /* Channel Result */ - register8_t reserved_0x6; - register8_t reserved_0x7; -} ADC_CH_t; - -/* --------------------------------------------------------------------------- -ADC - Analog/Digital Converter --------------------------------------------------------------------------- -*/ - -/* Analog-to-Digital Converter */ -typedef struct ADC_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t REFCTRL; /* Reference Control */ - register8_t EVCTRL; /* Event Control */ - register8_t PRESCALER; /* Clock Prescaler */ - register8_t reserved_0x05; - register8_t INTFLAGS; /* Interrupt Flags */ - register8_t reserved_0x07; - register8_t reserved_0x08; - register8_t reserved_0x09; - register8_t reserved_0x0A; - register8_t reserved_0x0B; - _WORDREGISTER(CAL); /* Calibration Value */ - register8_t reserved_0x0E; - register8_t reserved_0x0F; - _WORDREGISTER(CH0RES); /* Channel 0 Result */ - register8_t reserved_0x12; - register8_t reserved_0x13; - register8_t reserved_0x14; - register8_t reserved_0x15; - register8_t reserved_0x16; - register8_t reserved_0x17; - _WORDREGISTER(CMP); /* Compare Value */ - register8_t reserved_0x1A; - register8_t reserved_0x1B; - register8_t reserved_0x1C; - register8_t reserved_0x1D; - register8_t reserved_0x1E; - register8_t reserved_0x1F; - ADC_CH_t CH0; /* ADC Channel 0 */ -} ADC_t; - -/* Positive input multiplexer selection */ -typedef enum ADC_CH_MUXPOS_enum -{ - ADC_CH_MUXPOS_PIN0_gc = (0x00<<3), /* Input pin 0 */ - ADC_CH_MUXPOS_PIN1_gc = (0x01<<3), /* Input pin 1 */ - ADC_CH_MUXPOS_PIN2_gc = (0x02<<3), /* Input pin 2 */ - ADC_CH_MUXPOS_PIN3_gc = (0x03<<3), /* Input pin 3 */ - ADC_CH_MUXPOS_PIN4_gc = (0x04<<3), /* Input pin 4 */ - ADC_CH_MUXPOS_PIN5_gc = (0x05<<3), /* Input pin 5 */ - ADC_CH_MUXPOS_PIN6_gc = (0x06<<3), /* Input pin 6 */ - ADC_CH_MUXPOS_PIN7_gc = (0x07<<3), /* Input pin 7 */ - ADC_CH_MUXPOS_PIN8_gc = (0x08<<3), /* Input pin 8 */ - ADC_CH_MUXPOS_PIN9_gc = (0x09<<3), /* Input pin 9 */ - ADC_CH_MUXPOS_PIN10_gc = (0x10<<3), /* Input pin 10 */ - ADC_CH_MUXPOS_PIN11_gc = (0x11<<3), /* Input pin 11 */ -} ADC_CH_MUXPOS_t; - -/* Internal input multiplexer selections */ -typedef enum ADC_CH_MUXINT_enum -{ - ADC_CH_MUXINT_TEMP_gc = (0x00<<3), /* Temperature Reference */ - ADC_CH_MUXINT_BANDGAP_gc = (0x01<<3), /* Bandgap Reference */ - ADC_CH_MUXINT_SCALEDVCC_gc = (0x02<<3), /* 1/10 scaled VCC */ - ADC_CH_MUXINT_DAC_gc = (0x03<<3), /* DAC output */ -} ADC_CH_MUXINT_t; - -/* Negative input multiplexer selection */ -typedef enum ADC_CH_MUXNEG_enum -{ - ADC_CH_MUXNEG_PIN0_gc = (0x00<<0), /* Input pin 0 */ - ADC_CH_MUXNEG_PIN1_gc = (0x01<<0), /* Input pin 1 */ - ADC_CH_MUXNEG_PIN2_gc = (0x02<<0), /* Input pin 2 */ - ADC_CH_MUXNEG_PIN3_gc = (0x03<<0), /* Input pin 3 */ - ADC_CH_MUXNEG_PIN4_gc = (0x04<<0), /* Input pin 4 */ - ADC_CH_MUXNEG_PIN5_gc = (0x05<<0), /* Input pin 5 */ - ADC_CH_MUXNEG_PIN6_gc = (0x06<<0), /* Input pin 6 */ - ADC_CH_MUXNEG_PIN7_gc = (0x07<<0), /* Input pin 7 */ -} ADC_CH_MUXNEG_t; - -/* Input mode */ -typedef enum ADC_CH_INPUTMODE_enum -{ - ADC_CH_INPUTMODE_INTERNAL_gc = (0x00<<0), /* Internal inputs, no gain */ - ADC_CH_INPUTMODE_SINGLEENDED_gc = (0x01<<0), /* Single-ended input, no gain */ - ADC_CH_INPUTMODE_DIFF_gc = (0x02<<0), /* Differential input, no gain */ - ADC_CH_INPUTMODE_DIFFWGAIN_gc = (0x03<<0), /* Differential input, with gain */ -} ADC_CH_INPUTMODE_t; - -/* Gain factor */ -typedef enum ADC_CH_GAIN_enum -{ - ADC_CH_GAIN_1X_gc = (0x00<<2), /* 1x gain */ - ADC_CH_GAIN_2X_gc = (0x01<<2), /* 2x gain */ - ADC_CH_GAIN_4X_gc = (0x02<<2), /* 4x gain */ - ADC_CH_GAIN_8X_gc = (0x03<<2), /* 8x gain */ - ADC_CH_GAIN_16X_gc = (0x04<<2), /* 16x gain */ - ADC_CH_GAIN_32X_gc = (0x05<<2), /* 32x gain */ - ADC_CH_GAIN_64X_gc = (0x06<<2), /* 64x gain */ - ADC_CH_GAIN_DIV2_gc = (0x07<<2), /* x/2 gain */ -} ADC_CH_GAIN_t; - -/* Conversion result resolution */ -typedef enum ADC_RESOLUTION_enum -{ - ADC_RESOLUTION_12BIT_gc = (0x00<<1), /* 12-bit right-adjusted result */ - ADC_RESOLUTION_8BIT_gc = (0x02<<1), /* 8-bit right-adjusted result */ - ADC_RESOLUTION_LEFT12BIT_gc = (0x03<<1), /* 12-bit left-adjusted result */ -} ADC_RESOLUTION_t; - -typedef enum ADC_CURRLIMIT_enum -{ - ADC_CURRLIMIT_NO_gc = (0x00<<5), /* No limit */ - ADC_CURRLIMIT_LOW_gc = (0x01<<5), /* Low current limit, max. sampling rate 1.5MSPS */ - ADC_CURRLIMIT_MED_gc = (0x02<<5), /* Medium current limit, max. sampling rate 1MSPS */ - ADC_CURRLIMIT_HIGH_gc = (0x03<<5), /* High current limit, max. sampling rate 0.5MSPS */ -} ADC_CURRLIMIT_t; - -/* Voltage reference selection */ -typedef enum ADC_REFSEL_enum -{ - ADC_REFSEL_INT1V_gc = (0x00<<4), /* Internal 1V */ - ADC_REFSEL_VCC_gc = (0x01<<4), /* Internal VCC/1.6V */ - ADC_REFSEL_AREFA_gc = (0x02<<4), /* External reference on PORT A */ - ADC_REFSEL_AREFB_gc = (0x03<<4), /* External reference on PORT B */ -} ADC_REFSEL_t; - -/* Channel sweep selection */ -typedef enum ADC_SWEEP_enum -{ - ADC_SWEEP_0_gc = (0x00<<6), /* ADC Channel 0 */ -} ADC_SWEEP_t; - -/* Event channel input selection */ -typedef enum ADC_EVSEL_enum -{ - ADC_EVSEL_0123_gc = (0x00<<3), /* Event Channel 0,1,2,3 */ - ADC_EVSEL_1234_gc = (0x01<<3), /* Event Channel 1,2,3,4 */ - ADC_EVSEL_2345_gc = (0x02<<3), /* Event Channel 2,3,4,5 */ - ADC_EVSEL_3456_gc = (0x03<<3), /* Event Channel 3,4,5,6 */ - ADC_EVSEL_4567_gc = (0x04<<3), /* Event Channel 4,5,6,7 */ - ADC_EVSEL_567_gc = (0x05<<3), /* Event Channel 5,6,7 */ - ADC_EVSEL_67_gc = (0x06<<3), /* Event Channel 6,7 */ - ADC_EVSEL_7_gc = (0x07<<3), /* Event Channel 7 */ -} ADC_EVSEL_t; - -/* Event action selection */ -typedef enum ADC_EVACT_enum -{ - ADC_EVACT_NONE_gc = (0x00<<0), /* No event action */ - ADC_EVACT_CH0_gc = (0x01<<0), /* First event triggers channel 0 */ -} ADC_EVACT_t; - -/* Interupt mode */ -typedef enum ADC_CH_INTMODE_enum -{ - ADC_CH_INTMODE_COMPLETE_gc = (0x00<<2), /* Interrupt on conversion complete */ - ADC_CH_INTMODE_BELOW_gc = (0x01<<2), /* Interrupt on result below compare value */ - ADC_CH_INTMODE_ABOVE_gc = (0x03<<2), /* Interrupt on result above compare value */ -} ADC_CH_INTMODE_t; - -/* Interrupt level */ -typedef enum ADC_CH_INTLVL_enum -{ - ADC_CH_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ - ADC_CH_INTLVL_LO_gc = (0x01<<0), /* Low level */ - ADC_CH_INTLVL_MED_gc = (0x02<<0), /* Medium level */ - ADC_CH_INTLVL_HI_gc = (0x03<<0), /* High level */ -} ADC_CH_INTLVL_t; - -/* Clock prescaler */ -typedef enum ADC_PRESCALER_enum -{ - ADC_PRESCALER_DIV4_gc = (0x00<<0), /* Divide clock by 4 */ - ADC_PRESCALER_DIV8_gc = (0x01<<0), /* Divide clock by 8 */ - ADC_PRESCALER_DIV16_gc = (0x02<<0), /* Divide clock by 16 */ - ADC_PRESCALER_DIV32_gc = (0x03<<0), /* Divide clock by 32 */ - ADC_PRESCALER_DIV64_gc = (0x04<<0), /* Divide clock by 64 */ - ADC_PRESCALER_DIV128_gc = (0x05<<0), /* Divide clock by 128 */ - ADC_PRESCALER_DIV256_gc = (0x06<<0), /* Divide clock by 256 */ - ADC_PRESCALER_DIV512_gc = (0x07<<0), /* Divide clock by 512 */ -} ADC_PRESCALER_t; - - -/* --------------------------------------------------------------------------- -RTC - Real-Time Clounter --------------------------------------------------------------------------- -*/ - -/* Real-Time Counter */ -typedef struct RTC_struct -{ - register8_t CTRL; /* Control Register */ - register8_t STATUS; /* Status Register */ - register8_t INTCTRL; /* Interrupt Control Register */ - register8_t INTFLAGS; /* Interrupt Flags */ - register8_t TEMP; /* Temporary register */ - register8_t reserved_0x05; - register8_t reserved_0x06; - register8_t reserved_0x07; - _WORDREGISTER(CNT); /* Count Register */ - _WORDREGISTER(PER); /* Period Register */ - _WORDREGISTER(COMP); /* Compare Register */ -} RTC_t; - -/* Prescaler Factor */ -typedef enum RTC_PRESCALER_enum -{ - RTC_PRESCALER_OFF_gc = (0x00<<0), /* RTC Off */ - RTC_PRESCALER_DIV1_gc = (0x01<<0), /* RTC Clock */ - RTC_PRESCALER_DIV2_gc = (0x02<<0), /* RTC Clock / 2 */ - RTC_PRESCALER_DIV8_gc = (0x03<<0), /* RTC Clock / 8 */ - RTC_PRESCALER_DIV16_gc = (0x04<<0), /* RTC Clock / 16 */ - RTC_PRESCALER_DIV64_gc = (0x05<<0), /* RTC Clock / 64 */ - RTC_PRESCALER_DIV256_gc = (0x06<<0), /* RTC Clock / 256 */ - RTC_PRESCALER_DIV1024_gc = (0x07<<0), /* RTC Clock / 1024 */ -} RTC_PRESCALER_t; - -/* Compare Interrupt level */ -typedef enum RTC_COMPINTLVL_enum -{ - RTC_COMPINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ - RTC_COMPINTLVL_LO_gc = (0x01<<2), /* Low Level */ - RTC_COMPINTLVL_MED_gc = (0x02<<2), /* Medium Level */ - RTC_COMPINTLVL_HI_gc = (0x03<<2), /* High Level */ -} RTC_COMPINTLVL_t; - -/* Overflow Interrupt level */ -typedef enum RTC_OVFINTLVL_enum -{ - RTC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - RTC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ - RTC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ - RTC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ -} RTC_OVFINTLVL_t; - - -/* --------------------------------------------------------------------------- -EBI - External Bus Interface --------------------------------------------------------------------------- -*/ - -/* EBI Chip Select Module */ -typedef struct EBI_CS_struct -{ - register8_t CTRLA; /* Chip Select Control Register A */ - register8_t CTRLB; /* Chip Select Control Register B */ - _WORDREGISTER(BASEADDR); /* Chip Select Base Address */ -} EBI_CS_t; - -/* --------------------------------------------------------------------------- -EBI - External Bus Interface --------------------------------------------------------------------------- -*/ - -/* External Bus Interface */ -typedef struct EBI_struct -{ - register8_t CTRL; /* Control */ - register8_t SDRAMCTRLA; /* SDRAM Control Register A */ - register8_t reserved_0x02; - register8_t reserved_0x03; - _WORDREGISTER(REFRESH); /* SDRAM Refresh Period */ - _WORDREGISTER(INITDLY); /* SDRAM Initialization Delay */ - register8_t SDRAMCTRLB; /* SDRAM Control Register B */ - register8_t SDRAMCTRLC; /* SDRAM Control Register C */ - register8_t reserved_0x0A; - register8_t reserved_0x0B; - register8_t reserved_0x0C; - register8_t reserved_0x0D; - register8_t reserved_0x0E; - register8_t reserved_0x0F; - EBI_CS_t CS0; /* Chip Select 0 */ - EBI_CS_t CS1; /* Chip Select 1 */ - EBI_CS_t CS2; /* Chip Select 2 */ - EBI_CS_t CS3; /* Chip Select 3 */ -} EBI_t; - -/* Chip Select adress space */ -typedef enum EBI_CS_ASIZE_enum -{ - EBI_CS_ASIZE_256B_gc = (0x00<<2), /* 256 bytes */ - EBI_CS_ASIZE_512B_gc = (0x01<<2), /* 512 bytes */ - EBI_CS_ASIZE_1KB_gc = (0x02<<2), /* 1K bytes */ - EBI_CS_ASIZE_2KB_gc = (0x03<<2), /* 2K bytes */ - EBI_CS_ASIZE_4KB_gc = (0x04<<2), /* 4K bytes */ - EBI_CS_ASIZE_8KB_gc = (0x05<<2), /* 8K bytes */ - EBI_CS_ASIZE_16KB_gc = (0x06<<2), /* 16K bytes */ - EBI_CS_ASIZE_32KB_gc = (0x07<<2), /* 32K bytes */ - EBI_CS_ASIZE_64KB_gc = (0x08<<2), /* 64K bytes */ - EBI_CS_ASIZE_128KB_gc = (0x09<<2), /* 128K bytes */ - EBI_CS_ASIZE_256KB_gc = (0x0A<<2), /* 256K bytes */ - EBI_CS_ASIZE_512KB_gc = (0x0B<<2), /* 512K bytes */ - EBI_CS_ASIZE_1MB_gc = (0x0C<<2), /* 1M bytes */ - EBI_CS_ASIZE_2MB_gc = (0x0D<<2), /* 2M bytes */ - EBI_CS_ASIZE_4MB_gc = (0x0E<<2), /* 4M bytes */ - EBI_CS_ASIZE_8MB_gc = (0x0F<<2), /* 8M bytes */ - EBI_CS_ASIZE_16M_gc = (0x10<<2), /* 16M bytes */ -} EBI_CS_ASIZE_t; - -/* */ -typedef enum EBI_CS_SRWS_enum -{ - EBI_CS_SRWS_0CLK_gc = (0x00<<0), /* 0 cycles */ - EBI_CS_SRWS_1CLK_gc = (0x01<<0), /* 1 cycle */ - EBI_CS_SRWS_2CLK_gc = (0x02<<0), /* 2 cycles */ - EBI_CS_SRWS_3CLK_gc = (0x03<<0), /* 3 cycles */ - EBI_CS_SRWS_4CLK_gc = (0x04<<0), /* 4 cycles */ - EBI_CS_SRWS_5CLK_gc = (0x05<<0), /* 5 cycle */ - EBI_CS_SRWS_6CLK_gc = (0x06<<0), /* 6 cycles */ - EBI_CS_SRWS_7CLK_gc = (0x07<<0), /* 7 cycles */ -} EBI_CS_SRWS_t; - -/* Chip Select address mode */ -typedef enum EBI_CS_MODE_enum -{ - EBI_CS_MODE_DISABLED_gc = (0x00<<0), /* Chip Select Disabled */ - EBI_CS_MODE_SRAM_gc = (0x01<<0), /* Chip Select in SRAM mode */ - EBI_CS_MODE_LPC_gc = (0x02<<0), /* Chip Select in SRAM LPC mode */ - EBI_CS_MODE_SDRAM_gc = (0x03<<0), /* Chip Select in SDRAM mode */ -} EBI_CS_MODE_t; - -/* Chip Select SDRAM mode */ -typedef enum EBI_CS_SDMODE_enum -{ - EBI_CS_SDMODE_NORMAL_gc = (0x00<<0), /* Normal mode */ - EBI_CS_SDMODE_LOAD_gc = (0x01<<0), /* Load Mode Register command mode */ -} EBI_CS_SDMODE_t; - -/* */ -typedef enum EBI_SDDATAW_enum -{ - EBI_SDDATAW_4BIT_gc = (0x00<<6), /* 4-bit data bus */ - EBI_SDDATAW_8BIT_gc = (0x01<<6), /* 8-bit data bus */ -} EBI_SDDATAW_t; - -/* */ -typedef enum EBI_LPCMODE_enum -{ - EBI_LPCMODE_ALE1_gc = (0x00<<4), /* Data muxed with addr byte 0 */ - EBI_LPCMODE_ALE12_gc = (0x02<<4), /* Data muxed with addr byte 0 and 1 */ -} EBI_LPCMODE_t; - -/* */ -typedef enum EBI_SRMODE_enum -{ - EBI_SRMODE_ALE1_gc = (0x00<<2), /* Addr byte 0 muxed with 1 */ - EBI_SRMODE_ALE2_gc = (0x01<<2), /* Addr byte 0 muxed with 2 */ - EBI_SRMODE_ALE12_gc = (0x02<<2), /* Addr byte 0 muxed with 1 and 2 */ - EBI_SRMODE_NOALE_gc = (0x03<<2), /* No addr muxing */ -} EBI_SRMODE_t; - -/* */ -typedef enum EBI_IFMODE_enum -{ - EBI_IFMODE_DISABLED_gc = (0x00<<0), /* EBI Disabled */ - EBI_IFMODE_3PORT_gc = (0x01<<0), /* 3-port mode */ - EBI_IFMODE_4PORT_gc = (0x02<<0), /* 4-port mode */ - EBI_IFMODE_2PORT_gc = (0x03<<0), /* 2-port mode */ -} EBI_IFMODE_t; - -/* */ -typedef enum EBI_SDCOL_enum -{ - EBI_SDCOL_8BIT_gc = (0x00<<0), /* 8 column bits */ - EBI_SDCOL_9BIT_gc = (0x01<<0), /* 9 column bits */ - EBI_SDCOL_10BIT_gc = (0x02<<0), /* 10 column bits */ - EBI_SDCOL_11BIT_gc = (0x03<<0), /* 11 column bits */ -} EBI_SDCOL_t; - -/* */ -typedef enum EBI_MRDLY_enum -{ - EBI_MRDLY_0CLK_gc = (0x00<<6), /* 0 cycles */ - EBI_MRDLY_1CLK_gc = (0x01<<6), /* 1 cycle */ - EBI_MRDLY_2CLK_gc = (0x02<<6), /* 2 cycles */ - EBI_MRDLY_3CLK_gc = (0x03<<6), /* 3 cycles */ -} EBI_MRDLY_t; - -/* */ -typedef enum EBI_ROWCYCDLY_enum -{ - EBI_ROWCYCDLY_0CLK_gc = (0x00<<3), /* 0 cycles */ - EBI_ROWCYCDLY_1CLK_gc = (0x01<<3), /* 1 cycle */ - EBI_ROWCYCDLY_2CLK_gc = (0x02<<3), /* 2 cycles */ - EBI_ROWCYCDLY_3CLK_gc = (0x03<<3), /* 3 cycles */ - EBI_ROWCYCDLY_4CLK_gc = (0x04<<3), /* 4 cycles */ - EBI_ROWCYCDLY_5CLK_gc = (0x05<<3), /* 5 cycle */ - EBI_ROWCYCDLY_6CLK_gc = (0x06<<3), /* 6 cycles */ - EBI_ROWCYCDLY_7CLK_gc = (0x07<<3), /* 7 cycles */ -} EBI_ROWCYCDLY_t; - -/* */ -typedef enum EBI_RPDLY_enum -{ - EBI_RPDLY_0CLK_gc = (0x00<<0), /* 0 cycles */ - EBI_RPDLY_1CLK_gc = (0x01<<0), /* 1 cycle */ - EBI_RPDLY_2CLK_gc = (0x02<<0), /* 2 cycles */ - EBI_RPDLY_3CLK_gc = (0x03<<0), /* 3 cycles */ - EBI_RPDLY_4CLK_gc = (0x04<<0), /* 4 cycles */ - EBI_RPDLY_5CLK_gc = (0x05<<0), /* 5 cycle */ - EBI_RPDLY_6CLK_gc = (0x06<<0), /* 6 cycles */ - EBI_RPDLY_7CLK_gc = (0x07<<0), /* 7 cycles */ -} EBI_RPDLY_t; - -/* */ -typedef enum EBI_WRDLY_enum -{ - EBI_WRDLY_0CLK_gc = (0x00<<6), /* 0 cycles */ - EBI_WRDLY_1CLK_gc = (0x01<<6), /* 1 cycle */ - EBI_WRDLY_2CLK_gc = (0x02<<6), /* 2 cycles */ - EBI_WRDLY_3CLK_gc = (0x03<<6), /* 3 cycles */ -} EBI_WRDLY_t; - -/* */ -typedef enum EBI_ESRDLY_enum -{ - EBI_ESRDLY_0CLK_gc = (0x00<<3), /* 0 cycles */ - EBI_ESRDLY_1CLK_gc = (0x01<<3), /* 1 cycle */ - EBI_ESRDLY_2CLK_gc = (0x02<<3), /* 2 cycles */ - EBI_ESRDLY_3CLK_gc = (0x03<<3), /* 3 cycles */ - EBI_ESRDLY_4CLK_gc = (0x04<<3), /* 4 cycles */ - EBI_ESRDLY_5CLK_gc = (0x05<<3), /* 5 cycle */ - EBI_ESRDLY_6CLK_gc = (0x06<<3), /* 6 cycles */ - EBI_ESRDLY_7CLK_gc = (0x07<<3), /* 7 cycles */ -} EBI_ESRDLY_t; - -/* */ -typedef enum EBI_ROWCOLDLY_enum -{ - EBI_ROWCOLDLY_0CLK_gc = (0x00<<0), /* 0 cycles */ - EBI_ROWCOLDLY_1CLK_gc = (0x01<<0), /* 1 cycle */ - EBI_ROWCOLDLY_2CLK_gc = (0x02<<0), /* 2 cycles */ - EBI_ROWCOLDLY_3CLK_gc = (0x03<<0), /* 3 cycles */ - EBI_ROWCOLDLY_4CLK_gc = (0x04<<0), /* 4 cycles */ - EBI_ROWCOLDLY_5CLK_gc = (0x05<<0), /* 5 cycle */ - EBI_ROWCOLDLY_6CLK_gc = (0x06<<0), /* 6 cycles */ - EBI_ROWCOLDLY_7CLK_gc = (0x07<<0), /* 7 cycles */ -} EBI_ROWCOLDLY_t; - - -/* --------------------------------------------------------------------------- -TWI - Two-Wire Interface --------------------------------------------------------------------------- -*/ - -/* */ -typedef struct TWI_MASTER_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t CTRLC; /* Control Register C */ - register8_t STATUS; /* Status Register */ - register8_t BAUD; /* Baurd Rate Control Register */ - register8_t ADDR; /* Address Register */ - register8_t DATA; /* Data Register */ -} TWI_MASTER_t; - -/* --------------------------------------------------------------------------- -TWI - Two-Wire Interface --------------------------------------------------------------------------- -*/ - -/* */ -typedef struct TWI_SLAVE_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t STATUS; /* Status Register */ - register8_t ADDR; /* Address Register */ - register8_t DATA; /* Data Register */ - register8_t ADDRMASK; /* Address Mask Register */ -} TWI_SLAVE_t; - -/* --------------------------------------------------------------------------- -TWI - Two-Wire Interface --------------------------------------------------------------------------- -*/ - -/* Two-Wire Interface */ -typedef struct TWI_struct -{ - register8_t CTRL; /* TWI Common Control Register */ - TWI_MASTER_t MASTER; /* TWI master module */ - TWI_SLAVE_t SLAVE; /* TWI slave module */ -} TWI_t; - -/* Master Interrupt Level */ -typedef enum TWI_MASTER_INTLVL_enum -{ - TWI_MASTER_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ - TWI_MASTER_INTLVL_LO_gc = (0x01<<6), /* Low Level */ - TWI_MASTER_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ - TWI_MASTER_INTLVL_HI_gc = (0x03<<6), /* High Level */ -} TWI_MASTER_INTLVL_t; - -/* Inactive Timeout */ -typedef enum TWI_MASTER_TIMEOUT_enum -{ - TWI_MASTER_TIMEOUT_DISABLED_gc = (0x00<<2), /* Bus Timeout Disabled */ - TWI_MASTER_TIMEOUT_50US_gc = (0x01<<2), /* 50 Microseconds */ - TWI_MASTER_TIMEOUT_100US_gc = (0x02<<2), /* 100 Microseconds */ - TWI_MASTER_TIMEOUT_200US_gc = (0x03<<2), /* 200 Microseconds */ -} TWI_MASTER_TIMEOUT_t; - -/* Master Command */ -typedef enum TWI_MASTER_CMD_enum -{ - TWI_MASTER_CMD_NOACT_gc = (0x00<<0), /* No Action */ - TWI_MASTER_CMD_REPSTART_gc = (0x01<<0), /* Issue Repeated Start Condition */ - TWI_MASTER_CMD_RECVTRANS_gc = (0x02<<0), /* Receive or Transmit Data */ - TWI_MASTER_CMD_STOP_gc = (0x03<<0), /* Issue Stop Condition */ -} TWI_MASTER_CMD_t; - -/* Master Bus State */ -typedef enum TWI_MASTER_BUSSTATE_enum -{ - TWI_MASTER_BUSSTATE_UNKNOWN_gc = (0x00<<0), /* Unknown Bus State */ - TWI_MASTER_BUSSTATE_IDLE_gc = (0x01<<0), /* Bus is Idle */ - TWI_MASTER_BUSSTATE_OWNER_gc = (0x02<<0), /* This Module Controls The Bus */ - TWI_MASTER_BUSSTATE_BUSY_gc = (0x03<<0), /* The Bus is Busy */ -} TWI_MASTER_BUSSTATE_t; - -/* Slave Interrupt Level */ -typedef enum TWI_SLAVE_INTLVL_enum -{ - TWI_SLAVE_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ - TWI_SLAVE_INTLVL_LO_gc = (0x01<<6), /* Low Level */ - TWI_SLAVE_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ - TWI_SLAVE_INTLVL_HI_gc = (0x03<<6), /* High Level */ -} TWI_SLAVE_INTLVL_t; - -/* Slave Command */ -typedef enum TWI_SLAVE_CMD_enum -{ - TWI_SLAVE_CMD_NOACT_gc = (0x00<<0), /* No Action */ - TWI_SLAVE_CMD_COMPTRANS_gc = (0x02<<0), /* Used To Complete a Transaction */ - TWI_SLAVE_CMD_RESPONSE_gc = (0x03<<0), /* Used in Response to Address/Data Interrupt */ -} TWI_SLAVE_CMD_t; - - -/* --------------------------------------------------------------------------- -PORT - Port Configuration --------------------------------------------------------------------------- -*/ - -/* I/O port Configuration */ -typedef struct PORTCFG_struct -{ - register8_t MPCMASK; /* Multi-pin Configuration Mask */ - register8_t reserved_0x01; - register8_t VPCTRLA; /* Virtual Port Control Register A */ - register8_t VPCTRLB; /* Virtual Port Control Register B */ - register8_t CLKEVOUT; /* Clock and Event Out Register */ -} PORTCFG_t; - -/* --------------------------------------------------------------------------- -PORT - Port Configuration --------------------------------------------------------------------------- -*/ - -/* Virtual Port */ -typedef struct VPORT_struct -{ - register8_t DIR; /* I/O Port Data Direction */ - register8_t OUT; /* I/O Port Output */ - register8_t IN; /* I/O Port Input */ - register8_t INTFLAGS; /* Interrupt Flag Register */ -} VPORT_t; - -/* --------------------------------------------------------------------------- -PORT - Port Configuration --------------------------------------------------------------------------- -*/ - -/* I/O Ports */ -typedef struct PORT_struct -{ - register8_t DIR; /* I/O Port Data Direction */ - register8_t DIRSET; /* I/O Port Data Direction Set */ - register8_t DIRCLR; /* I/O Port Data Direction Clear */ - register8_t DIRTGL; /* I/O Port Data Direction Toggle */ - register8_t OUT; /* I/O Port Output */ - register8_t OUTSET; /* I/O Port Output Set */ - register8_t OUTCLR; /* I/O Port Output Clear */ - register8_t OUTTGL; /* I/O Port Output Toggle */ - register8_t IN; /* I/O port Input */ - register8_t INTCTRL; /* Interrupt Control Register */ - register8_t INT0MASK; /* Port Interrupt 0 Mask */ - register8_t INT1MASK; /* Port Interrupt 1 Mask */ - register8_t INTFLAGS; /* Interrupt Flag Register */ - register8_t reserved_0x0D; - register8_t reserved_0x0E; - register8_t reserved_0x0F; - register8_t PIN0CTRL; /* Pin 0 Control Register */ - register8_t PIN1CTRL; /* Pin 1 Control Register */ - register8_t PIN2CTRL; /* Pin 2 Control Register */ - register8_t PIN3CTRL; /* Pin 3 Control Register */ - register8_t PIN4CTRL; /* Pin 4 Control Register */ - register8_t PIN5CTRL; /* Pin 5 Control Register */ - register8_t PIN6CTRL; /* Pin 6 Control Register */ - register8_t PIN7CTRL; /* Pin 7 Control Register */ -} PORT_t; - -/* Virtual Port 0 Mapping */ -typedef enum PORTCFG_VP0MAP_enum -{ - PORTCFG_VP0MAP_PORTA_gc = (0x00<<0), /* Mapped To PORTA */ - PORTCFG_VP0MAP_PORTB_gc = (0x01<<0), /* Mapped To PORTB */ - PORTCFG_VP0MAP_PORTC_gc = (0x02<<0), /* Mapped To PORTC */ - PORTCFG_VP0MAP_PORTD_gc = (0x03<<0), /* Mapped To PORTD */ - PORTCFG_VP0MAP_PORTE_gc = (0x04<<0), /* Mapped To PORTE */ - PORTCFG_VP0MAP_PORTF_gc = (0x05<<0), /* Mapped To PORTF */ - PORTCFG_VP0MAP_PORTG_gc = (0x06<<0), /* Mapped To PORTG */ - PORTCFG_VP0MAP_PORTH_gc = (0x07<<0), /* Mapped To PORTH */ - PORTCFG_VP0MAP_PORTJ_gc = (0x08<<0), /* Mapped To PORTJ */ - PORTCFG_VP0MAP_PORTK_gc = (0x09<<0), /* Mapped To PORTK */ - PORTCFG_VP0MAP_PORTL_gc = (0x0A<<0), /* Mapped To PORTL */ - PORTCFG_VP0MAP_PORTM_gc = (0x0B<<0), /* Mapped To PORTM */ - PORTCFG_VP0MAP_PORTN_gc = (0x0C<<0), /* Mapped To PORTN */ - PORTCFG_VP0MAP_PORTP_gc = (0x0D<<0), /* Mapped To PORTP */ - PORTCFG_VP0MAP_PORTQ_gc = (0x0E<<0), /* Mapped To PORTQ */ - PORTCFG_VP0MAP_PORTR_gc = (0x0F<<0), /* Mapped To PORTR */ -} PORTCFG_VP0MAP_t; - -/* Virtual Port 1 Mapping */ -typedef enum PORTCFG_VP1MAP_enum -{ - PORTCFG_VP1MAP_PORTA_gc = (0x00<<4), /* Mapped To PORTA */ - PORTCFG_VP1MAP_PORTB_gc = (0x01<<4), /* Mapped To PORTB */ - PORTCFG_VP1MAP_PORTC_gc = (0x02<<4), /* Mapped To PORTC */ - PORTCFG_VP1MAP_PORTD_gc = (0x03<<4), /* Mapped To PORTD */ - PORTCFG_VP1MAP_PORTE_gc = (0x04<<4), /* Mapped To PORTE */ - PORTCFG_VP1MAP_PORTF_gc = (0x05<<4), /* Mapped To PORTF */ - PORTCFG_VP1MAP_PORTG_gc = (0x06<<4), /* Mapped To PORTG */ - PORTCFG_VP1MAP_PORTH_gc = (0x07<<4), /* Mapped To PORTH */ - PORTCFG_VP1MAP_PORTJ_gc = (0x08<<4), /* Mapped To PORTJ */ - PORTCFG_VP1MAP_PORTK_gc = (0x09<<4), /* Mapped To PORTK */ - PORTCFG_VP1MAP_PORTL_gc = (0x0A<<4), /* Mapped To PORTL */ - PORTCFG_VP1MAP_PORTM_gc = (0x0B<<4), /* Mapped To PORTM */ - PORTCFG_VP1MAP_PORTN_gc = (0x0C<<4), /* Mapped To PORTN */ - PORTCFG_VP1MAP_PORTP_gc = (0x0D<<4), /* Mapped To PORTP */ - PORTCFG_VP1MAP_PORTQ_gc = (0x0E<<4), /* Mapped To PORTQ */ - PORTCFG_VP1MAP_PORTR_gc = (0x0F<<4), /* Mapped To PORTR */ -} PORTCFG_VP1MAP_t; - -/* Virtual Port 2 Mapping */ -typedef enum PORTCFG_VP2MAP_enum -{ - PORTCFG_VP2MAP_PORTA_gc = (0x00<<0), /* Mapped To PORTA */ - PORTCFG_VP2MAP_PORTB_gc = (0x01<<0), /* Mapped To PORTB */ - PORTCFG_VP2MAP_PORTC_gc = (0x02<<0), /* Mapped To PORTC */ - PORTCFG_VP2MAP_PORTD_gc = (0x03<<0), /* Mapped To PORTD */ - PORTCFG_VP2MAP_PORTE_gc = (0x04<<0), /* Mapped To PORTE */ - PORTCFG_VP2MAP_PORTF_gc = (0x05<<0), /* Mapped To PORTF */ - PORTCFG_VP2MAP_PORTG_gc = (0x06<<0), /* Mapped To PORTG */ - PORTCFG_VP2MAP_PORTH_gc = (0x07<<0), /* Mapped To PORTH */ - PORTCFG_VP2MAP_PORTJ_gc = (0x08<<0), /* Mapped To PORTJ */ - PORTCFG_VP2MAP_PORTK_gc = (0x09<<0), /* Mapped To PORTK */ - PORTCFG_VP2MAP_PORTL_gc = (0x0A<<0), /* Mapped To PORTL */ - PORTCFG_VP2MAP_PORTM_gc = (0x0B<<0), /* Mapped To PORTM */ - PORTCFG_VP2MAP_PORTN_gc = (0x0C<<0), /* Mapped To PORTN */ - PORTCFG_VP2MAP_PORTP_gc = (0x0D<<0), /* Mapped To PORTP */ - PORTCFG_VP2MAP_PORTQ_gc = (0x0E<<0), /* Mapped To PORTQ */ - PORTCFG_VP2MAP_PORTR_gc = (0x0F<<0), /* Mapped To PORTR */ -} PORTCFG_VP2MAP_t; - -/* Virtual Port 3 Mapping */ -typedef enum PORTCFG_VP3MAP_enum -{ - PORTCFG_VP3MAP_PORTA_gc = (0x00<<4), /* Mapped To PORTA */ - PORTCFG_VP3MAP_PORTB_gc = (0x01<<4), /* Mapped To PORTB */ - PORTCFG_VP3MAP_PORTC_gc = (0x02<<4), /* Mapped To PORTC */ - PORTCFG_VP3MAP_PORTD_gc = (0x03<<4), /* Mapped To PORTD */ - PORTCFG_VP3MAP_PORTE_gc = (0x04<<4), /* Mapped To PORTE */ - PORTCFG_VP3MAP_PORTF_gc = (0x05<<4), /* Mapped To PORTF */ - PORTCFG_VP3MAP_PORTG_gc = (0x06<<4), /* Mapped To PORTG */ - PORTCFG_VP3MAP_PORTH_gc = (0x07<<4), /* Mapped To PORTH */ - PORTCFG_VP3MAP_PORTJ_gc = (0x08<<4), /* Mapped To PORTJ */ - PORTCFG_VP3MAP_PORTK_gc = (0x09<<4), /* Mapped To PORTK */ - PORTCFG_VP3MAP_PORTL_gc = (0x0A<<4), /* Mapped To PORTL */ - PORTCFG_VP3MAP_PORTM_gc = (0x0B<<4), /* Mapped To PORTM */ - PORTCFG_VP3MAP_PORTN_gc = (0x0C<<4), /* Mapped To PORTN */ - PORTCFG_VP3MAP_PORTP_gc = (0x0D<<4), /* Mapped To PORTP */ - PORTCFG_VP3MAP_PORTQ_gc = (0x0E<<4), /* Mapped To PORTQ */ - PORTCFG_VP3MAP_PORTR_gc = (0x0F<<4), /* Mapped To PORTR */ -} PORTCFG_VP3MAP_t; - -/* Clock Output Port */ -typedef enum PORTCFG_CLKOUT_enum -{ - PORTCFG_CLKOUT_OFF_gc = (0x00<<0), /* Clock Output Disabled */ - PORTCFG_CLKOUT_PC7_gc = (0x01<<0), /* Clock Output on Port C pin 7 */ - PORTCFG_CLKOUT_PD7_gc = (0x02<<0), /* Clock Output on Port D pin 7 */ - PORTCFG_CLKOUT_PE7_gc = (0x03<<0), /* Clock Output on Port E pin 7 */ -} PORTCFG_CLKOUT_t; - -/* Event Output Port */ -typedef enum PORTCFG_EVOUT_enum -{ - PORTCFG_EVOUT_OFF_gc = (0x00<<4), /* Event Output Disabled */ - PORTCFG_EVOUT_PC7_gc = (0x01<<4), /* Event Channel 7 Output on Port C pin 7 */ - PORTCFG_EVOUT_PD7_gc = (0x02<<4), /* Event Channel 7 Output on Port D pin 7 */ - PORTCFG_EVOUT_PE7_gc = (0x03<<4), /* Event Channel 7 Output on Port E pin 7 */ -} PORTCFG_EVOUT_t; - -/* Port Interrupt 0 Level */ -typedef enum PORT_INT0LVL_enum -{ - PORT_INT0LVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - PORT_INT0LVL_LO_gc = (0x01<<0), /* Low Level */ - PORT_INT0LVL_MED_gc = (0x02<<0), /* Medium Level */ - PORT_INT0LVL_HI_gc = (0x03<<0), /* High Level */ -} PORT_INT0LVL_t; - -/* Port Interrupt 1 Level */ -typedef enum PORT_INT1LVL_enum -{ - PORT_INT1LVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ - PORT_INT1LVL_LO_gc = (0x01<<2), /* Low Level */ - PORT_INT1LVL_MED_gc = (0x02<<2), /* Medium Level */ - PORT_INT1LVL_HI_gc = (0x03<<2), /* High Level */ -} PORT_INT1LVL_t; - -/* Output/Pull Configuration */ -typedef enum PORT_OPC_enum -{ - PORT_OPC_TOTEM_gc = (0x00<<3), /* Totempole */ - PORT_OPC_BUSKEEPER_gc = (0x01<<3), /* Totempole w/ Bus keeper on Input and Output */ - PORT_OPC_PULLDOWN_gc = (0x02<<3), /* Totempole w/ Pull-down on Input */ - PORT_OPC_PULLUP_gc = (0x03<<3), /* Totempole w/ Pull-up on Input */ - PORT_OPC_WIREDOR_gc = (0x04<<3), /* Wired OR */ - PORT_OPC_WIREDAND_gc = (0x05<<3), /* Wired AND */ - PORT_OPC_WIREDORPULL_gc = (0x06<<3), /* Wired OR w/ Pull-down */ - PORT_OPC_WIREDANDPULL_gc = (0x07<<3), /* Wired AND w/ Pull-up */ -} PORT_OPC_t; - -/* Input/Sense Configuration */ -typedef enum PORT_ISC_enum -{ - PORT_ISC_BOTHEDGES_gc = (0x00<<0), /* Sense Both Edges */ - PORT_ISC_RISING_gc = (0x01<<0), /* Sense Rising Edge */ - PORT_ISC_FALLING_gc = (0x02<<0), /* Sense Falling Edge */ - PORT_ISC_LEVEL_gc = (0x03<<0), /* Sense Level (Transparent For Events) */ - PORT_ISC_INPUT_DISABLE_gc = (0x07<<0), /* Disable Digital Input Buffer */ -} PORT_ISC_t; - - -/* --------------------------------------------------------------------------- -TC - 16-bit Timer/Counter With PWM --------------------------------------------------------------------------- -*/ - -/* 16-bit Timer/Counter 0 */ -typedef struct TC0_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t CTRLC; /* Control register C */ - register8_t CTRLD; /* Control Register D */ - register8_t CTRLE; /* Control Register E */ - register8_t reserved_0x05; - register8_t INTCTRLA; /* Interrupt Control Register A */ - register8_t INTCTRLB; /* Interrupt Control Register B */ - register8_t CTRLFCLR; /* Control Register F Clear */ - register8_t CTRLFSET; /* Control Register F Set */ - register8_t CTRLGCLR; /* Control Register G Clear */ - register8_t CTRLGSET; /* Control Register G Set */ - register8_t INTFLAGS; /* Interrupt Flag Register */ - register8_t reserved_0x0D; - register8_t reserved_0x0E; - register8_t TEMP; /* Temporary Register For 16-bit Access */ - register8_t reserved_0x10; - register8_t reserved_0x11; - register8_t reserved_0x12; - register8_t reserved_0x13; - register8_t reserved_0x14; - register8_t reserved_0x15; - register8_t reserved_0x16; - register8_t reserved_0x17; - register8_t reserved_0x18; - register8_t reserved_0x19; - register8_t reserved_0x1A; - register8_t reserved_0x1B; - register8_t reserved_0x1C; - register8_t reserved_0x1D; - register8_t reserved_0x1E; - register8_t reserved_0x1F; - _WORDREGISTER(CNT); /* Count */ - register8_t reserved_0x22; - register8_t reserved_0x23; - register8_t reserved_0x24; - register8_t reserved_0x25; - _WORDREGISTER(PER); /* Period */ - _WORDREGISTER(CCA); /* Compare or Capture A */ - _WORDREGISTER(CCB); /* Compare or Capture B */ - _WORDREGISTER(CCC); /* Compare or Capture C */ - _WORDREGISTER(CCD); /* Compare or Capture D */ - register8_t reserved_0x30; - register8_t reserved_0x31; - register8_t reserved_0x32; - register8_t reserved_0x33; - register8_t reserved_0x34; - register8_t reserved_0x35; - _WORDREGISTER(PERBUF); /* Period Buffer */ - _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ - _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ - _WORDREGISTER(CCCBUF); /* Compare Or Capture C Buffer */ - _WORDREGISTER(CCDBUF); /* Compare Or Capture D Buffer */ -} TC0_t; - -/* --------------------------------------------------------------------------- -TC - 16-bit Timer/Counter With PWM --------------------------------------------------------------------------- -*/ - -/* 16-bit Timer/Counter 1 */ -typedef struct TC1_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t CTRLC; /* Control register C */ - register8_t CTRLD; /* Control Register D */ - register8_t CTRLE; /* Control Register E */ - register8_t reserved_0x05; - register8_t INTCTRLA; /* Interrupt Control Register A */ - register8_t INTCTRLB; /* Interrupt Control Register B */ - register8_t CTRLFCLR; /* Control Register F Clear */ - register8_t CTRLFSET; /* Control Register F Set */ - register8_t CTRLGCLR; /* Control Register G Clear */ - register8_t CTRLGSET; /* Control Register G Set */ - register8_t INTFLAGS; /* Interrupt Flag Register */ - register8_t reserved_0x0D; - register8_t reserved_0x0E; - register8_t TEMP; /* Temporary Register For 16-bit Access */ - register8_t reserved_0x10; - register8_t reserved_0x11; - register8_t reserved_0x12; - register8_t reserved_0x13; - register8_t reserved_0x14; - register8_t reserved_0x15; - register8_t reserved_0x16; - register8_t reserved_0x17; - register8_t reserved_0x18; - register8_t reserved_0x19; - register8_t reserved_0x1A; - register8_t reserved_0x1B; - register8_t reserved_0x1C; - register8_t reserved_0x1D; - register8_t reserved_0x1E; - register8_t reserved_0x1F; - _WORDREGISTER(CNT); /* Count */ - register8_t reserved_0x22; - register8_t reserved_0x23; - register8_t reserved_0x24; - register8_t reserved_0x25; - _WORDREGISTER(PER); /* Period */ - _WORDREGISTER(CCA); /* Compare or Capture A */ - _WORDREGISTER(CCB); /* Compare or Capture B */ - register8_t reserved_0x2C; - register8_t reserved_0x2D; - register8_t reserved_0x2E; - register8_t reserved_0x2F; - register8_t reserved_0x30; - register8_t reserved_0x31; - register8_t reserved_0x32; - register8_t reserved_0x33; - register8_t reserved_0x34; - register8_t reserved_0x35; - _WORDREGISTER(PERBUF); /* Period Buffer */ - _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ - _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ -} TC1_t; - -/* --------------------------------------------------------------------------- -TC - 16-bit Timer/Counter With PWM --------------------------------------------------------------------------- -*/ - -/* Advanced Waveform Extension */ -typedef struct AWEX_struct -{ - register8_t CTRL; /* Control Register */ - register8_t reserved_0x01; - register8_t FDEMASK; /* Fault Detection Event Mask */ - register8_t FDCTRL; /* Fault Detection Control Register */ - register8_t STATUS; /* Status Register */ - register8_t reserved_0x05; - register8_t DTBOTH; /* Dead Time Both Sides */ - register8_t DTBOTHBUF; /* Dead Time Both Sides Buffer */ - register8_t DTLS; /* Dead Time Low Side */ - register8_t DTHS; /* Dead Time High Side */ - register8_t DTLSBUF; /* Dead Time Low Side Buffer */ - register8_t DTHSBUF; /* Dead Time High Side Buffer */ - register8_t OUTOVEN; /* Output Override Enable */ -} AWEX_t; - -/* --------------------------------------------------------------------------- -TC - 16-bit Timer/Counter With PWM --------------------------------------------------------------------------- -*/ - -/* High-Resolution Extension */ -typedef struct HIRES_struct -{ - register8_t CTRLA; /* Control Register */ -} HIRES_t; - -/* Clock Selection */ -typedef enum TC_CLKSEL_enum -{ - TC_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */ - TC_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */ - TC_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */ - TC_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */ - TC_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */ - TC_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */ - TC_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */ - TC_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */ - TC_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */ - TC_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */ - TC_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */ - TC_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */ - TC_CLKSEL_EVCH4_gc = (0x0C<<0), /* Event Channel 4 */ - TC_CLKSEL_EVCH5_gc = (0x0D<<0), /* Event Channel 5 */ - TC_CLKSEL_EVCH6_gc = (0x0E<<0), /* Event Channel 6 */ - TC_CLKSEL_EVCH7_gc = (0x0F<<0), /* Event Channel 7 */ -} TC_CLKSEL_t; - -/* Waveform Generation Mode */ -typedef enum TC_WGMODE_enum -{ - TC_WGMODE_NORMAL_gc = (0x00<<0), /* Normal Mode */ - TC_WGMODE_FRQ_gc = (0x01<<0), /* Frequency Generation Mode */ - TC_WGMODE_SS_gc = (0x03<<0), /* Single Slope */ - TC_WGMODE_DS_T_gc = (0x05<<0), /* Dual Slope, Update on TOP */ - TC_WGMODE_DS_TB_gc = (0x06<<0), /* Dual Slope, Update on TOP and BOTTOM */ - TC_WGMODE_DS_B_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */ -} TC_WGMODE_t; - -/* Event Action */ -typedef enum TC_EVACT_enum -{ - TC_EVACT_OFF_gc = (0x00<<5), /* No Event Action */ - TC_EVACT_CAPT_gc = (0x01<<5), /* Input Capture */ - TC_EVACT_UPDOWN_gc = (0x02<<5), /* Externally Controlled Up/Down Count */ - TC_EVACT_QDEC_gc = (0x03<<5), /* Quadrature Decode */ - TC_EVACT_RESTART_gc = (0x04<<5), /* Restart */ - TC_EVACT_FRQ_gc = (0x05<<5), /* Frequency Capture */ - TC_EVACT_FRW_gc = (0x05<<5), /* Frequency Capture (typo in earlier header file) */ - TC_EVACT_PW_gc = (0x06<<5), /* Pulse-width Capture */ -} TC_EVACT_t; - -/* Event Selection */ -typedef enum TC_EVSEL_enum -{ - TC_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ - TC_EVSEL_CH0_gc = (0x08<<0), /* Event Channel 0 */ - TC_EVSEL_CH1_gc = (0x09<<0), /* Event Channel 1 */ - TC_EVSEL_CH2_gc = (0x0A<<0), /* Event Channel 2 */ - TC_EVSEL_CH3_gc = (0x0B<<0), /* Event Channel 3 */ - TC_EVSEL_CH4_gc = (0x0C<<0), /* Event Channel 4 */ - TC_EVSEL_CH5_gc = (0x0D<<0), /* Event Channel 5 */ - TC_EVSEL_CH6_gc = (0x0E<<0), /* Event Channel 6 */ - TC_EVSEL_CH7_gc = (0x0F<<0), /* Event Channel 7 */ -} TC_EVSEL_t; - -/* Error Interrupt Level */ -typedef enum TC_ERRINTLVL_enum -{ - TC_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ - TC_ERRINTLVL_LO_gc = (0x01<<2), /* Low Level */ - TC_ERRINTLVL_MED_gc = (0x02<<2), /* Medium Level */ - TC_ERRINTLVL_HI_gc = (0x03<<2), /* High Level */ -} TC_ERRINTLVL_t; - -/* Overflow Interrupt Level */ -typedef enum TC_OVFINTLVL_enum -{ - TC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - TC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ - TC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ - TC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ -} TC_OVFINTLVL_t; - -/* Compare or Capture D Interrupt Level */ -typedef enum TC_CCDINTLVL_enum -{ - TC_CCDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ - TC_CCDINTLVL_LO_gc = (0x01<<6), /* Low Level */ - TC_CCDINTLVL_MED_gc = (0x02<<6), /* Medium Level */ - TC_CCDINTLVL_HI_gc = (0x03<<6), /* High Level */ -} TC_CCDINTLVL_t; - -/* Compare or Capture C Interrupt Level */ -typedef enum TC_CCCINTLVL_enum -{ - TC_CCCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ - TC_CCCINTLVL_LO_gc = (0x01<<4), /* Low Level */ - TC_CCCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ - TC_CCCINTLVL_HI_gc = (0x03<<4), /* High Level */ -} TC_CCCINTLVL_t; - -/* Compare or Capture B Interrupt Level */ -typedef enum TC_CCBINTLVL_enum -{ - TC_CCBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ - TC_CCBINTLVL_LO_gc = (0x01<<2), /* Low Level */ - TC_CCBINTLVL_MED_gc = (0x02<<2), /* Medium Level */ - TC_CCBINTLVL_HI_gc = (0x03<<2), /* High Level */ -} TC_CCBINTLVL_t; - -/* Compare or Capture A Interrupt Level */ -typedef enum TC_CCAINTLVL_enum -{ - TC_CCAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - TC_CCAINTLVL_LO_gc = (0x01<<0), /* Low Level */ - TC_CCAINTLVL_MED_gc = (0x02<<0), /* Medium Level */ - TC_CCAINTLVL_HI_gc = (0x03<<0), /* High Level */ -} TC_CCAINTLVL_t; - -/* Timer/Counter Command */ -typedef enum TC_CMD_enum -{ - TC_CMD_NONE_gc = (0x00<<2), /* No Command */ - TC_CMD_UPDATE_gc = (0x01<<2), /* Force Update */ - TC_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ - TC_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ -} TC_CMD_t; - -/* Fault Detect Action */ -typedef enum AWEX_FDACT_enum -{ - AWEX_FDACT_NONE_gc = (0x00<<0), /* No Fault Protection */ - AWEX_FDACT_CLEAROE_gc = (0x01<<0), /* Clear Output Enable Bits */ - AWEX_FDACT_CLEARDIR_gc = (0x03<<0), /* Clear I/O Port Direction Bits */ -} AWEX_FDACT_t; - -/* High Resolution Enable */ -typedef enum HIRES_HREN_enum -{ - HIRES_HREN_NONE_gc = (0x00<<0), /* No Fault Protection */ - HIRES_HREN_TC0_gc = (0x01<<0), /* Enable High Resolution on Timer/Counter 0 */ - HIRES_HREN_TC1_gc = (0x02<<0), /* Enable High Resolution on Timer/Counter 1 */ - HIRES_HREN_BOTH_gc = (0x03<<0), /* Enable High Resolution both Timer/Counters */ -} HIRES_HREN_t; - - -/* --------------------------------------------------------------------------- -USART - Universal Asynchronous Receiver-Transmitter --------------------------------------------------------------------------- -*/ - -/* Universal Synchronous/Asynchronous Receiver/Transmitter */ -typedef struct USART_struct -{ - register8_t DATA; /* Data Register */ - register8_t STATUS; /* Status Register */ - register8_t reserved_0x02; - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t CTRLC; /* Control Register C */ - register8_t BAUDCTRLA; /* Baud Rate Control Register A */ - register8_t BAUDCTRLB; /* Baud Rate Control Register B */ -} USART_t; - -/* Receive Complete Interrupt level */ -typedef enum USART_RXCINTLVL_enum -{ - USART_RXCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ - USART_RXCINTLVL_LO_gc = (0x01<<4), /* Low Level */ - USART_RXCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ - USART_RXCINTLVL_HI_gc = (0x03<<4), /* High Level */ -} USART_RXCINTLVL_t; - -/* Transmit Complete Interrupt level */ -typedef enum USART_TXCINTLVL_enum -{ - USART_TXCINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ - USART_TXCINTLVL_LO_gc = (0x01<<2), /* Low Level */ - USART_TXCINTLVL_MED_gc = (0x02<<2), /* Medium Level */ - USART_TXCINTLVL_HI_gc = (0x03<<2), /* High Level */ -} USART_TXCINTLVL_t; - -/* Data Register Empty Interrupt level */ -typedef enum USART_DREINTLVL_enum -{ - USART_DREINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - USART_DREINTLVL_LO_gc = (0x01<<0), /* Low Level */ - USART_DREINTLVL_MED_gc = (0x02<<0), /* Medium Level */ - USART_DREINTLVL_HI_gc = (0x03<<0), /* High Level */ -} USART_DREINTLVL_t; - -/* Character Size */ -typedef enum USART_CHSIZE_enum -{ - USART_CHSIZE_5BIT_gc = (0x00<<0), /* Character size: 5 bit */ - USART_CHSIZE_6BIT_gc = (0x01<<0), /* Character size: 6 bit */ - USART_CHSIZE_7BIT_gc = (0x02<<0), /* Character size: 7 bit */ - USART_CHSIZE_8BIT_gc = (0x03<<0), /* Character size: 8 bit */ - USART_CHSIZE_9BIT_gc = (0x07<<0), /* Character size: 9 bit */ -} USART_CHSIZE_t; - -/* Communication Mode */ -typedef enum USART_CMODE_enum -{ - USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6), /* Asynchronous Mode */ - USART_CMODE_SYNCHRONOUS_gc = (0x01<<6), /* Synchronous Mode */ - USART_CMODE_IRDA_gc = (0x02<<6), /* IrDA Mode */ - USART_CMODE_MSPI_gc = (0x03<<6), /* Master SPI Mode */ -} USART_CMODE_t; - -/* Parity Mode */ -typedef enum USART_PMODE_enum -{ - USART_PMODE_DISABLED_gc = (0x00<<4), /* No Parity */ - USART_PMODE_EVEN_gc = (0x02<<4), /* Even Parity */ - USART_PMODE_ODD_gc = (0x03<<4), /* Odd Parity */ -} USART_PMODE_t; - - -/* --------------------------------------------------------------------------- -SPI - Serial Peripheral Interface --------------------------------------------------------------------------- -*/ - -/* Serial Peripheral Interface */ -typedef struct SPI_struct -{ - register8_t CTRL; /* Control Register */ - register8_t INTCTRL; /* Interrupt Control Register */ - register8_t STATUS; /* Status Register */ - register8_t DATA; /* Data Register */ -} SPI_t; - -/* SPI Mode */ -typedef enum SPI_MODE_enum -{ - SPI_MODE_0_gc = (0x00<<2), /* SPI Mode 0 */ - SPI_MODE_1_gc = (0x01<<2), /* SPI Mode 1 */ - SPI_MODE_2_gc = (0x02<<2), /* SPI Mode 2 */ - SPI_MODE_3_gc = (0x03<<2), /* SPI Mode 3 */ -} SPI_MODE_t; - -/* Prescaler setting */ -typedef enum SPI_PRESCALER_enum -{ - SPI_PRESCALER_DIV4_gc = (0x00<<0), /* System Clock / 4 */ - SPI_PRESCALER_DIV16_gc = (0x01<<0), /* System Clock / 16 */ - SPI_PRESCALER_DIV64_gc = (0x02<<0), /* System Clock / 64 */ - SPI_PRESCALER_DIV128_gc = (0x03<<0), /* System Clock / 128 */ -} SPI_PRESCALER_t; - -/* Interrupt level */ -typedef enum SPI_INTLVL_enum -{ - SPI_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - SPI_INTLVL_LO_gc = (0x01<<0), /* Low Level */ - SPI_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ - SPI_INTLVL_HI_gc = (0x03<<0), /* High Level */ -} SPI_INTLVL_t; - - -/* --------------------------------------------------------------------------- -IRCOM - IR Communication Module --------------------------------------------------------------------------- -*/ - -/* IR Communication Module */ -typedef struct IRCOM_struct -{ - register8_t CTRL; /* Control Register */ - register8_t TXPLCTRL; /* IrDA Transmitter Pulse Length Control Register */ - register8_t RXPLCTRL; /* IrDA Receiver Pulse Length Control Register */ -} IRCOM_t; - -/* Event channel selection */ -typedef enum IRDA_EVSEL_enum -{ - IRDA_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ - IRDA_EVSEL_0_gc = (0x08<<0), /* Event Channel 0 */ - IRDA_EVSEL_1_gc = (0x09<<0), /* Event Channel 1 */ - IRDA_EVSEL_2_gc = (0x0A<<0), /* Event Channel 2 */ - IRDA_EVSEL_3_gc = (0x0B<<0), /* Event Channel 3 */ - IRDA_EVSEL_4_gc = (0x0C<<0), /* Event Channel 4 */ - IRDA_EVSEL_5_gc = (0x0D<<0), /* Event Channel 5 */ - IRDA_EVSEL_6_gc = (0x0E<<0), /* Event Channel 6 */ - IRDA_EVSEL_7_gc = (0x0F<<0), /* Event Channel 7 */ -} IRDA_EVSEL_t; - - - -/* -========================================================================== -IO Module Instances. Mapped to memory. -========================================================================== -*/ - -#define VPORT0 (*(VPORT_t *) 0x0010) /* Virtual Port 0 */ -#define VPORT1 (*(VPORT_t *) 0x0014) /* Virtual Port 1 */ -#define VPORT2 (*(VPORT_t *) 0x0018) /* Virtual Port 2 */ -#define VPORT3 (*(VPORT_t *) 0x001C) /* Virtual Port 3 */ -#define OCD (*(OCD_t *) 0x002E) /* On-Chip Debug System */ -#define CLK (*(CLK_t *) 0x0040) /* Clock System */ -#define SLEEP (*(SLEEP_t *) 0x0048) /* Sleep Controller */ -#define OSC (*(OSC_t *) 0x0050) /* Oscillator Control */ -#define DFLLRC32M (*(DFLL_t *) 0x0060) /* DFLL for 32MHz RC Oscillator */ -#define DFLLRC2M (*(DFLL_t *) 0x0068) /* DFLL for 2MHz RC Oscillator */ -#define PR (*(PR_t *) 0x0070) /* Power Reduction */ -#define RST (*(RST_t *) 0x0078) /* Reset Controller */ -#define WDT (*(WDT_t *) 0x0080) /* Watch-Dog Timer */ -#define MCU (*(MCU_t *) 0x0090) /* MCU Control */ -#define PMIC (*(PMIC_t *) 0x00A0) /* Programmable Interrupt Controller */ -#define PORTCFG (*(PORTCFG_t *) 0x00B0) /* Port Configuration */ -#define EVSYS (*(EVSYS_t *) 0x0180) /* Event System */ -#define NVM (*(NVM_t *) 0x01C0) /* Non Volatile Memory Controller */ -#define ADCA (*(ADC_t *) 0x0200) /* Analog to Digital Converter A */ -#define DACB (*(DAC_t *) 0x0320) /* Digital to Analog Converter B */ -#define ACA (*(AC_t *) 0x0380) /* Analog Comparator A */ -#define RTC (*(RTC_t *) 0x0400) /* Real-Time Counter */ -#define TWIC (*(TWI_t *) 0x0480) /* Two-Wire Interface C */ -#define TWIE (*(TWI_t *) 0x04A0) /* Two-Wire Interface E */ -#define PORTA (*(PORT_t *) 0x0600) /* Port A */ -#define PORTB (*(PORT_t *) 0x0620) /* Port B */ -#define PORTC (*(PORT_t *) 0x0640) /* Port C */ -#define PORTD (*(PORT_t *) 0x0660) /* Port D */ -#define PORTE (*(PORT_t *) 0x0680) /* Port E */ -#define PORTR (*(PORT_t *) 0x07E0) /* Port R */ -#define TCC0 (*(TC0_t *) 0x0800) /* Timer/Counter C0 */ -#define TCC1 (*(TC1_t *) 0x0840) /* Timer/Counter C1 */ -#define AWEXC (*(AWEX_t *) 0x0880) /* Advanced Waveform Extension C */ -#define HIRESC (*(HIRES_t *) 0x0890) /* High-Resolution Extension C */ -#define USARTC0 (*(USART_t *) 0x08A0) /* Universal Asynchronous Receiver-Transmitter C0 */ -#define SPIC (*(SPI_t *) 0x08C0) /* Serial Peripheral Interface C */ -#define IRCOM (*(IRCOM_t *) 0x08F8) /* IR Communication Module */ -#define TCD0 (*(TC0_t *) 0x0900) /* Timer/Counter D0 */ -#define USARTD0 (*(USART_t *) 0x09A0) /* Universal Asynchronous Receiver-Transmitter D0 */ -#define SPID (*(SPI_t *) 0x09C0) /* Serial Peripheral Interface D */ -#define TCE0 (*(TC0_t *) 0x0A00) /* Timer/Counter E0 */ - - -#endif /* !defined (__ASSEMBLER__) */ - - -/* ========== Flattened fully qualified IO register names ========== */ - -/* GPIO - General Purpose IO Registers */ -#define GPIO_GPIO0 _SFR_MEM8(0x0000) -#define GPIO_GPIO1 _SFR_MEM8(0x0001) -#define GPIO_GPIO2 _SFR_MEM8(0x0002) -#define GPIO_GPIO3 _SFR_MEM8(0x0003) -#define GPIO_GPIO4 _SFR_MEM8(0x0004) -#define GPIO_GPIO5 _SFR_MEM8(0x0005) -#define GPIO_GPIO6 _SFR_MEM8(0x0006) -#define GPIO_GPIO7 _SFR_MEM8(0x0007) -#define GPIO_GPIO8 _SFR_MEM8(0x0008) -#define GPIO_GPIO9 _SFR_MEM8(0x0009) -#define GPIO_GPIOA _SFR_MEM8(0x000A) -#define GPIO_GPIOB _SFR_MEM8(0x000B) -#define GPIO_GPIOC _SFR_MEM8(0x000C) -#define GPIO_GPIOD _SFR_MEM8(0x000D) -#define GPIO_GPIOE _SFR_MEM8(0x000E) -#define GPIO_GPIOF _SFR_MEM8(0x000F) - -/* VPORT0 - Virtual Port 0 */ -#define VPORT0_DIR _SFR_MEM8(0x0010) -#define VPORT0_OUT _SFR_MEM8(0x0011) -#define VPORT0_IN _SFR_MEM8(0x0012) -#define VPORT0_INTFLAGS _SFR_MEM8(0x0013) - -/* VPORT1 - Virtual Port 1 */ -#define VPORT1_DIR _SFR_MEM8(0x0014) -#define VPORT1_OUT _SFR_MEM8(0x0015) -#define VPORT1_IN _SFR_MEM8(0x0016) -#define VPORT1_INTFLAGS _SFR_MEM8(0x0017) - -/* VPORT2 - Virtual Port 2 */ -#define VPORT2_DIR _SFR_MEM8(0x0018) -#define VPORT2_OUT _SFR_MEM8(0x0019) -#define VPORT2_IN _SFR_MEM8(0x001A) -#define VPORT2_INTFLAGS _SFR_MEM8(0x001B) - -/* VPORT3 - Virtual Port 3 */ -#define VPORT3_DIR _SFR_MEM8(0x001C) -#define VPORT3_OUT _SFR_MEM8(0x001D) -#define VPORT3_IN _SFR_MEM8(0x001E) -#define VPORT3_INTFLAGS _SFR_MEM8(0x001F) - -/* OCD - On-Chip Debug System */ -#define OCD_OCDR0 _SFR_MEM8(0x002E) -#define OCD_OCDR1 _SFR_MEM8(0x002F) - -/* CPU - CPU Registers */ -#define CPU_CCP _SFR_MEM8(0x0034) -#define CPU_RAMPD _SFR_MEM8(0x0038) -#define CPU_RAMPX _SFR_MEM8(0x0039) -#define CPU_RAMPY _SFR_MEM8(0x003A) -#define CPU_RAMPZ _SFR_MEM8(0x003B) -#define CPU_EIND _SFR_MEM8(0x003C) -#define CPU_SPL _SFR_MEM8(0x003D) -#define CPU_SPH _SFR_MEM8(0x003E) -#define CPU_SREG _SFR_MEM8(0x003F) - -/* CLK - Clock System */ -#define CLK_CTRL _SFR_MEM8(0x0040) -#define CLK_PSCTRL _SFR_MEM8(0x0041) -#define CLK_LOCK _SFR_MEM8(0x0042) -#define CLK_RTCCTRL _SFR_MEM8(0x0043) - -/* SLEEP - Sleep Controller */ -#define SLEEP_CTRL _SFR_MEM8(0x0048) - -/* OSC - Oscillator Control */ -#define OSC_CTRL _SFR_MEM8(0x0050) -#define OSC_STATUS _SFR_MEM8(0x0051) -#define OSC_XOSCCTRL _SFR_MEM8(0x0052) -#define OSC_XOSCFAIL _SFR_MEM8(0x0053) -#define OSC_RC32KCAL _SFR_MEM8(0x0054) -#define OSC_PLLCTRL _SFR_MEM8(0x0055) -#define OSC_DFLLCTRL _SFR_MEM8(0x0056) - -/* DFLLRC32M - DFLL for 32MHz RC Oscillator */ -#define DFLLRC32M_CTRL _SFR_MEM8(0x0060) -#define DFLLRC32M_CALA _SFR_MEM8(0x0062) -#define DFLLRC32M_CALB _SFR_MEM8(0x0063) -#define DFLLRC32M_COMP0 _SFR_MEM8(0x0064) -#define DFLLRC32M_COMP1 _SFR_MEM8(0x0065) -#define DFLLRC32M_COMP2 _SFR_MEM8(0x0066) - -/* DFLLRC2M - DFLL for 2MHz RC Oscillator */ -#define DFLLRC2M_CTRL _SFR_MEM8(0x0068) -#define DFLLRC2M_CALA _SFR_MEM8(0x006A) -#define DFLLRC2M_CALB _SFR_MEM8(0x006B) -#define DFLLRC2M_COMP0 _SFR_MEM8(0x006C) -#define DFLLRC2M_COMP1 _SFR_MEM8(0x006D) -#define DFLLRC2M_COMP2 _SFR_MEM8(0x006E) - -/* PR - Power Reduction */ -#define PR_PRGEN _SFR_MEM8(0x0070) -#define PR_PRPA _SFR_MEM8(0x0071) -#define PR_PRPB _SFR_MEM8(0x0072) -#define PR_PRPC _SFR_MEM8(0x0073) -#define PR_PRPD _SFR_MEM8(0x0074) -#define PR_PRPE _SFR_MEM8(0x0075) -#define PR_PRPF _SFR_MEM8(0x0076) - -/* RST - Reset Controller */ -#define RST_STATUS _SFR_MEM8(0x0078) -#define RST_CTRL _SFR_MEM8(0x0079) - -/* WDT - Watch-Dog Timer */ -#define WDT_CTRL _SFR_MEM8(0x0080) -#define WDT_WINCTRL _SFR_MEM8(0x0081) -#define WDT_STATUS _SFR_MEM8(0x0082) - -/* MCU - MCU Control */ -#define MCU_DEVID0 _SFR_MEM8(0x0090) -#define MCU_DEVID1 _SFR_MEM8(0x0091) -#define MCU_DEVID2 _SFR_MEM8(0x0092) -#define MCU_REVID _SFR_MEM8(0x0093) -#define MCU_JTAGUID _SFR_MEM8(0x0094) -#define MCU_MCUCR _SFR_MEM8(0x0096) -#define MCU_EVSYSLOCK _SFR_MEM8(0x0098) -#define MCU_AWEXLOCK _SFR_MEM8(0x0099) - -/* PMIC - Programmable Interrupt Controller */ -#define PMIC_STATUS _SFR_MEM8(0x00A0) -#define PMIC_INTPRI _SFR_MEM8(0x00A1) -#define PMIC_CTRL _SFR_MEM8(0x00A2) - -/* PORTCFG - Port Configuration */ -#define PORTCFG_MPCMASK _SFR_MEM8(0x00B0) -#define PORTCFG_VPCTRLA _SFR_MEM8(0x00B2) -#define PORTCFG_VPCTRLB _SFR_MEM8(0x00B3) -#define PORTCFG_CLKEVOUT _SFR_MEM8(0x00B4) - -/* EVSYS - Event System */ -#define EVSYS_CH0MUX _SFR_MEM8(0x0180) -#define EVSYS_CH1MUX _SFR_MEM8(0x0181) -#define EVSYS_CH2MUX _SFR_MEM8(0x0182) -#define EVSYS_CH3MUX _SFR_MEM8(0x0183) -#define EVSYS_CH0CTRL _SFR_MEM8(0x0188) -#define EVSYS_CH1CTRL _SFR_MEM8(0x0189) -#define EVSYS_CH2CTRL _SFR_MEM8(0x018A) -#define EVSYS_CH3CTRL _SFR_MEM8(0x018B) -#define EVSYS_STROBE _SFR_MEM8(0x0190) -#define EVSYS_DATA _SFR_MEM8(0x0191) - -/* NVM - Non Volatile Memory Controller */ -#define NVM_ADDR0 _SFR_MEM8(0x01C0) -#define NVM_ADDR1 _SFR_MEM8(0x01C1) -#define NVM_ADDR2 _SFR_MEM8(0x01C2) -#define NVM_DATA0 _SFR_MEM8(0x01C4) -#define NVM_DATA1 _SFR_MEM8(0x01C5) -#define NVM_DATA2 _SFR_MEM8(0x01C6) -#define NVM_CMD _SFR_MEM8(0x01CA) -#define NVM_CTRLA _SFR_MEM8(0x01CB) -#define NVM_CTRLB _SFR_MEM8(0x01CC) -#define NVM_INTCTRL _SFR_MEM8(0x01CD) -#define NVM_STATUS _SFR_MEM8(0x01CF) -#define NVM_LOCKBITS _SFR_MEM8(0x01D0) - -/* ADCA - Analog to Digital Converter A */ -#define ADCA_CTRLA _SFR_MEM8(0x0200) -#define ADCA_CTRLB _SFR_MEM8(0x0201) -#define ADCA_REFCTRL _SFR_MEM8(0x0202) -#define ADCA_EVCTRL _SFR_MEM8(0x0203) -#define ADCA_PRESCALER _SFR_MEM8(0x0204) -#define ADCA_INTFLAGS _SFR_MEM8(0x0206) -#define ADCA_CAL _SFR_MEM16(0x020C) -#define ADCA_CH0RES _SFR_MEM16(0x0210) -#define ADCA_CMP _SFR_MEM16(0x0218) -#define ADCA_CH0_CTRL _SFR_MEM8(0x0220) -#define ADCA_CH0_MUXCTRL _SFR_MEM8(0x0221) -#define ADCA_CH0_INTCTRL _SFR_MEM8(0x0222) -#define ADCA_CH0_INTFLAGS _SFR_MEM8(0x0223) -#define ADCA_CH0_RES _SFR_MEM16(0x0224) - -/* DACB - Digital to Analog Converter B */ - -/* ACA - Analog Comparator A */ -#define ACA_AC0CTRL _SFR_MEM8(0x0380) -#define ACA_AC1CTRL _SFR_MEM8(0x0381) -#define ACA_AC0MUXCTRL _SFR_MEM8(0x0382) -#define ACA_AC1MUXCTRL _SFR_MEM8(0x0383) -#define ACA_CTRLA _SFR_MEM8(0x0384) -#define ACA_CTRLB _SFR_MEM8(0x0385) -#define ACA_WINCTRL _SFR_MEM8(0x0386) -#define ACA_STATUS _SFR_MEM8(0x0387) - -/* RTC - Real-Time Counter */ -#define RTC_CTRL _SFR_MEM8(0x0400) -#define RTC_STATUS _SFR_MEM8(0x0401) -#define RTC_INTCTRL _SFR_MEM8(0x0402) -#define RTC_INTFLAGS _SFR_MEM8(0x0403) -#define RTC_TEMP _SFR_MEM8(0x0404) -#define RTC_CNT _SFR_MEM16(0x0408) -#define RTC_PER _SFR_MEM16(0x040A) -#define RTC_COMP _SFR_MEM16(0x040C) - -/* TWIC - Two-Wire Interface C */ -#define TWIC_CTRL _SFR_MEM8(0x0480) -#define TWIC_MASTER_CTRLA _SFR_MEM8(0x0481) -#define TWIC_MASTER_CTRLB _SFR_MEM8(0x0482) -#define TWIC_MASTER_CTRLC _SFR_MEM8(0x0483) -#define TWIC_MASTER_STATUS _SFR_MEM8(0x0484) -#define TWIC_MASTER_BAUD _SFR_MEM8(0x0485) -#define TWIC_MASTER_ADDR _SFR_MEM8(0x0486) -#define TWIC_MASTER_DATA _SFR_MEM8(0x0487) -#define TWIC_SLAVE_CTRLA _SFR_MEM8(0x0488) -#define TWIC_SLAVE_CTRLB _SFR_MEM8(0x0489) -#define TWIC_SLAVE_STATUS _SFR_MEM8(0x048A) -#define TWIC_SLAVE_ADDR _SFR_MEM8(0x048B) -#define TWIC_SLAVE_DATA _SFR_MEM8(0x048C) -#define TWIC_SLAVE_ADDRMASK _SFR_MEM8(0x048D) - -/* TWIE - Two-Wire Interface E */ -#define TWIE_CTRL _SFR_MEM8(0x04A0) -#define TWIE_MASTER_CTRLA _SFR_MEM8(0x04A1) -#define TWIE_MASTER_CTRLB _SFR_MEM8(0x04A2) -#define TWIE_MASTER_CTRLC _SFR_MEM8(0x04A3) -#define TWIE_MASTER_STATUS _SFR_MEM8(0x04A4) -#define TWIE_MASTER_BAUD _SFR_MEM8(0x04A5) -#define TWIE_MASTER_ADDR _SFR_MEM8(0x04A6) -#define TWIE_MASTER_DATA _SFR_MEM8(0x04A7) -#define TWIE_SLAVE_CTRLA _SFR_MEM8(0x04A8) -#define TWIE_SLAVE_CTRLB _SFR_MEM8(0x04A9) -#define TWIE_SLAVE_STATUS _SFR_MEM8(0x04AA) -#define TWIE_SLAVE_ADDR _SFR_MEM8(0x04AB) -#define TWIE_SLAVE_DATA _SFR_MEM8(0x04AC) -#define TWIE_SLAVE_ADDRMASK _SFR_MEM8(0x04AD) - - -/* PORTA - Port A */ -#define PORTA_DIR _SFR_MEM8(0x0600) -#define PORTA_DIRSET _SFR_MEM8(0x0601) -#define PORTA_DIRCLR _SFR_MEM8(0x0602) -#define PORTA_DIRTGL _SFR_MEM8(0x0603) -#define PORTA_OUT _SFR_MEM8(0x0604) -#define PORTA_OUTSET _SFR_MEM8(0x0605) -#define PORTA_OUTCLR _SFR_MEM8(0x0606) -#define PORTA_OUTTGL _SFR_MEM8(0x0607) -#define PORTA_IN _SFR_MEM8(0x0608) -#define PORTA_INTCTRL _SFR_MEM8(0x0609) -#define PORTA_INT0MASK _SFR_MEM8(0x060A) -#define PORTA_INT1MASK _SFR_MEM8(0x060B) -#define PORTA_INTFLAGS _SFR_MEM8(0x060C) -#define PORTA_PIN0CTRL _SFR_MEM8(0x0610) -#define PORTA_PIN1CTRL _SFR_MEM8(0x0611) -#define PORTA_PIN2CTRL _SFR_MEM8(0x0612) -#define PORTA_PIN3CTRL _SFR_MEM8(0x0613) -#define PORTA_PIN4CTRL _SFR_MEM8(0x0614) -#define PORTA_PIN5CTRL _SFR_MEM8(0x0615) -#define PORTA_PIN6CTRL _SFR_MEM8(0x0616) -#define PORTA_PIN7CTRL _SFR_MEM8(0x0617) - -/* PORTB - Port B */ -#define PORTB_DIR _SFR_MEM8(0x0620) -#define PORTB_DIRSET _SFR_MEM8(0x0621) -#define PORTB_DIRCLR _SFR_MEM8(0x0622) -#define PORTB_DIRTGL _SFR_MEM8(0x0623) -#define PORTB_OUT _SFR_MEM8(0x0624) -#define PORTB_OUTSET _SFR_MEM8(0x0625) -#define PORTB_OUTCLR _SFR_MEM8(0x0626) -#define PORTB_OUTTGL _SFR_MEM8(0x0627) -#define PORTB_IN _SFR_MEM8(0x0628) -#define PORTB_INTCTRL _SFR_MEM8(0x0629) -#define PORTB_INT0MASK _SFR_MEM8(0x062A) -#define PORTB_INT1MASK _SFR_MEM8(0x062B) -#define PORTB_INTFLAGS _SFR_MEM8(0x062C) -#define PORTB_PIN0CTRL _SFR_MEM8(0x0630) -#define PORTB_PIN1CTRL _SFR_MEM8(0x0631) -#define PORTB_PIN2CTRL _SFR_MEM8(0x0632) -#define PORTB_PIN3CTRL _SFR_MEM8(0x0633) -#define PORTB_PIN4CTRL _SFR_MEM8(0x0634) -#define PORTB_PIN5CTRL _SFR_MEM8(0x0635) -#define PORTB_PIN6CTRL _SFR_MEM8(0x0636) -#define PORTB_PIN7CTRL _SFR_MEM8(0x0637) - -/* PORTC - Port C */ -#define PORTC_DIR _SFR_MEM8(0x0640) -#define PORTC_DIRSET _SFR_MEM8(0x0641) -#define PORTC_DIRCLR _SFR_MEM8(0x0642) -#define PORTC_DIRTGL _SFR_MEM8(0x0643) -#define PORTC_OUT _SFR_MEM8(0x0644) -#define PORTC_OUTSET _SFR_MEM8(0x0645) -#define PORTC_OUTCLR _SFR_MEM8(0x0646) -#define PORTC_OUTTGL _SFR_MEM8(0x0647) -#define PORTC_IN _SFR_MEM8(0x0648) -#define PORTC_INTCTRL _SFR_MEM8(0x0649) -#define PORTC_INT0MASK _SFR_MEM8(0x064A) -#define PORTC_INT1MASK _SFR_MEM8(0x064B) -#define PORTC_INTFLAGS _SFR_MEM8(0x064C) -#define PORTC_PIN0CTRL _SFR_MEM8(0x0650) -#define PORTC_PIN1CTRL _SFR_MEM8(0x0651) -#define PORTC_PIN2CTRL _SFR_MEM8(0x0652) -#define PORTC_PIN3CTRL _SFR_MEM8(0x0653) -#define PORTC_PIN4CTRL _SFR_MEM8(0x0654) -#define PORTC_PIN5CTRL _SFR_MEM8(0x0655) -#define PORTC_PIN6CTRL _SFR_MEM8(0x0656) -#define PORTC_PIN7CTRL _SFR_MEM8(0x0657) - -/* PORTD - Port D */ -#define PORTD_DIR _SFR_MEM8(0x0660) -#define PORTD_DIRSET _SFR_MEM8(0x0661) -#define PORTD_DIRCLR _SFR_MEM8(0x0662) -#define PORTD_DIRTGL _SFR_MEM8(0x0663) -#define PORTD_OUT _SFR_MEM8(0x0664) -#define PORTD_OUTSET _SFR_MEM8(0x0665) -#define PORTD_OUTCLR _SFR_MEM8(0x0666) -#define PORTD_OUTTGL _SFR_MEM8(0x0667) -#define PORTD_IN _SFR_MEM8(0x0668) -#define PORTD_INTCTRL _SFR_MEM8(0x0669) -#define PORTD_INT0MASK _SFR_MEM8(0x066A) -#define PORTD_INT1MASK _SFR_MEM8(0x066B) -#define PORTD_INTFLAGS _SFR_MEM8(0x066C) -#define PORTD_PIN0CTRL _SFR_MEM8(0x0670) -#define PORTD_PIN1CTRL _SFR_MEM8(0x0671) -#define PORTD_PIN2CTRL _SFR_MEM8(0x0672) -#define PORTD_PIN3CTRL _SFR_MEM8(0x0673) -#define PORTD_PIN4CTRL _SFR_MEM8(0x0674) -#define PORTD_PIN5CTRL _SFR_MEM8(0x0675) -#define PORTD_PIN6CTRL _SFR_MEM8(0x0676) -#define PORTD_PIN7CTRL _SFR_MEM8(0x0677) - -/* PORTE - Port E */ -#define PORTE_DIR _SFR_MEM8(0x0680) -#define PORTE_DIRSET _SFR_MEM8(0x0681) -#define PORTE_DIRCLR _SFR_MEM8(0x0682) -#define PORTE_DIRTGL _SFR_MEM8(0x0683) -#define PORTE_OUT _SFR_MEM8(0x0684) -#define PORTE_OUTSET _SFR_MEM8(0x0685) -#define PORTE_OUTCLR _SFR_MEM8(0x0686) -#define PORTE_OUTTGL _SFR_MEM8(0x0687) -#define PORTE_IN _SFR_MEM8(0x0688) -#define PORTE_INTCTRL _SFR_MEM8(0x0689) -#define PORTE_INT0MASK _SFR_MEM8(0x068A) -#define PORTE_INT1MASK _SFR_MEM8(0x068B) -#define PORTE_INTFLAGS _SFR_MEM8(0x068C) -#define PORTE_PIN0CTRL _SFR_MEM8(0x0690) -#define PORTE_PIN1CTRL _SFR_MEM8(0x0691) -#define PORTE_PIN2CTRL _SFR_MEM8(0x0692) -#define PORTE_PIN3CTRL _SFR_MEM8(0x0693) -#define PORTE_PIN4CTRL _SFR_MEM8(0x0694) -#define PORTE_PIN5CTRL _SFR_MEM8(0x0695) -#define PORTE_PIN6CTRL _SFR_MEM8(0x0696) -#define PORTE_PIN7CTRL _SFR_MEM8(0x0697) - -/* PORTR - Port R */ -#define PORTR_DIR _SFR_MEM8(0x07E0) -#define PORTR_DIRSET _SFR_MEM8(0x07E1) -#define PORTR_DIRCLR _SFR_MEM8(0x07E2) -#define PORTR_DIRTGL _SFR_MEM8(0x07E3) -#define PORTR_OUT _SFR_MEM8(0x07E4) -#define PORTR_OUTSET _SFR_MEM8(0x07E5) -#define PORTR_OUTCLR _SFR_MEM8(0x07E6) -#define PORTR_OUTTGL _SFR_MEM8(0x07E7) -#define PORTR_IN _SFR_MEM8(0x07E8) -#define PORTR_INTCTRL _SFR_MEM8(0x07E9) -#define PORTR_INT0MASK _SFR_MEM8(0x07EA) -#define PORTR_INT1MASK _SFR_MEM8(0x07EB) -#define PORTR_INTFLAGS _SFR_MEM8(0x07EC) -#define PORTR_PIN0CTRL _SFR_MEM8(0x07F0) -#define PORTR_PIN1CTRL _SFR_MEM8(0x07F1) -#define PORTR_PIN2CTRL _SFR_MEM8(0x07F2) -#define PORTR_PIN3CTRL _SFR_MEM8(0x07F3) -#define PORTR_PIN4CTRL _SFR_MEM8(0x07F4) -#define PORTR_PIN5CTRL _SFR_MEM8(0x07F5) -#define PORTR_PIN6CTRL _SFR_MEM8(0x07F6) -#define PORTR_PIN7CTRL _SFR_MEM8(0x07F7) - -/* TCC0 - Timer/Counter C0 */ -#define TCC0_CTRLA _SFR_MEM8(0x0800) -#define TCC0_CTRLB _SFR_MEM8(0x0801) -#define TCC0_CTRLC _SFR_MEM8(0x0802) -#define TCC0_CTRLD _SFR_MEM8(0x0803) -#define TCC0_CTRLE _SFR_MEM8(0x0804) -#define TCC0_INTCTRLA _SFR_MEM8(0x0806) -#define TCC0_INTCTRLB _SFR_MEM8(0x0807) -#define TCC0_CTRLFCLR _SFR_MEM8(0x0808) -#define TCC0_CTRLFSET _SFR_MEM8(0x0809) -#define TCC0_CTRLGCLR _SFR_MEM8(0x080A) -#define TCC0_CTRLGSET _SFR_MEM8(0x080B) -#define TCC0_INTFLAGS _SFR_MEM8(0x080C) -#define TCC0_TEMP _SFR_MEM8(0x080F) -#define TCC0_CNT _SFR_MEM16(0x0820) -#define TCC0_PER _SFR_MEM16(0x0826) -#define TCC0_CCA _SFR_MEM16(0x0828) -#define TCC0_CCB _SFR_MEM16(0x082A) -#define TCC0_CCC _SFR_MEM16(0x082C) -#define TCC0_CCD _SFR_MEM16(0x082E) -#define TCC0_PERBUF _SFR_MEM16(0x0836) -#define TCC0_CCABUF _SFR_MEM16(0x0838) -#define TCC0_CCBBUF _SFR_MEM16(0x083A) -#define TCC0_CCCBUF _SFR_MEM16(0x083C) -#define TCC0_CCDBUF _SFR_MEM16(0x083E) - -/* TCC1 - Timer/Counter C1 */ -#define TCC1_CTRLA _SFR_MEM8(0x0840) -#define TCC1_CTRLB _SFR_MEM8(0x0841) -#define TCC1_CTRLC _SFR_MEM8(0x0842) -#define TCC1_CTRLD _SFR_MEM8(0x0843) -#define TCC1_CTRLE _SFR_MEM8(0x0844) -#define TCC1_INTCTRLA _SFR_MEM8(0x0846) -#define TCC1_INTCTRLB _SFR_MEM8(0x0847) -#define TCC1_CTRLFCLR _SFR_MEM8(0x0848) -#define TCC1_CTRLFSET _SFR_MEM8(0x0849) -#define TCC1_CTRLGCLR _SFR_MEM8(0x084A) -#define TCC1_CTRLGSET _SFR_MEM8(0x084B) -#define TCC1_INTFLAGS _SFR_MEM8(0x084C) -#define TCC1_TEMP _SFR_MEM8(0x084F) -#define TCC1_CNT _SFR_MEM16(0x0860) -#define TCC1_PER _SFR_MEM16(0x0866) -#define TCC1_CCA _SFR_MEM16(0x0868) -#define TCC1_CCB _SFR_MEM16(0x086A) -#define TCC1_PERBUF _SFR_MEM16(0x0876) -#define TCC1_CCABUF _SFR_MEM16(0x0878) -#define TCC1_CCBBUF _SFR_MEM16(0x087A) - -/* AWEXC - Advanced Waveform Extension C */ -#define AWEXC_CTRL _SFR_MEM8(0x0880) -#define AWEXC_FDEMASK _SFR_MEM8(0x0882) -#define AWEXC_FDCTRL _SFR_MEM8(0x0883) -#define AWEXC_STATUS _SFR_MEM8(0x0884) -#define AWEXC_DTBOTH _SFR_MEM8(0x0886) -#define AWEXC_DTBOTHBUF _SFR_MEM8(0x0887) -#define AWEXC_DTLS _SFR_MEM8(0x0888) -#define AWEXC_DTHS _SFR_MEM8(0x0889) -#define AWEXC_DTLSBUF _SFR_MEM8(0x088A) -#define AWEXC_DTHSBUF _SFR_MEM8(0x088B) -#define AWEXC_OUTOVEN _SFR_MEM8(0x088C) - -/* HIRESC - High-Resolution Extension C */ -#define HIRESC_CTRLA _SFR_MEM8(0x0890) - -/* USARTC0 - Universal Asynchronous Receiver-Transmitter C0 */ -#define USARTC0_DATA _SFR_MEM8(0x08A0) -#define USARTC0_STATUS _SFR_MEM8(0x08A1) -#define USARTC0_CTRLA _SFR_MEM8(0x08A3) -#define USARTC0_CTRLB _SFR_MEM8(0x08A4) -#define USARTC0_CTRLC _SFR_MEM8(0x08A5) -#define USARTC0_BAUDCTRLA _SFR_MEM8(0x08A6) -#define USARTC0_BAUDCTRLB _SFR_MEM8(0x08A7) - -/* SPIC - Serial Peripheral Interface C */ -#define SPIC_CTRL _SFR_MEM8(0x08C0) -#define SPIC_INTCTRL _SFR_MEM8(0x08C1) -#define SPIC_STATUS _SFR_MEM8(0x08C2) -#define SPIC_DATA _SFR_MEM8(0x08C3) - -/* IRCOM - IR Communication Module */ -#define IRCOM_CTRL _SFR_MEM8(0x08F8) -#define IRCOM_TXPLCTRL _SFR_MEM8(0x08F9) -#define IRCOM_RXPLCTRL _SFR_MEM8(0x08FA) - -/* TCD0 - Timer/Counter D0 */ -#define TCD0_CTRLA _SFR_MEM8(0x0900) -#define TCD0_CTRLB _SFR_MEM8(0x0901) -#define TCD0_CTRLC _SFR_MEM8(0x0902) -#define TCD0_CTRLD _SFR_MEM8(0x0903) -#define TCD0_CTRLE _SFR_MEM8(0x0904) -#define TCD0_INTCTRLA _SFR_MEM8(0x0906) -#define TCD0_INTCTRLB _SFR_MEM8(0x0907) -#define TCD0_CTRLFCLR _SFR_MEM8(0x0908) -#define TCD0_CTRLFSET _SFR_MEM8(0x0909) -#define TCD0_CTRLGCLR _SFR_MEM8(0x090A) -#define TCD0_CTRLGSET _SFR_MEM8(0x090B) -#define TCD0_INTFLAGS _SFR_MEM8(0x090C) -#define TCD0_TEMP _SFR_MEM8(0x090F) -#define TCD0_CNT _SFR_MEM16(0x0920) -#define TCD0_PER _SFR_MEM16(0x0926) -#define TCD0_CCA _SFR_MEM16(0x0928) -#define TCD0_CCB _SFR_MEM16(0x092A) -#define TCD0_CCC _SFR_MEM16(0x092C) -#define TCD0_CCD _SFR_MEM16(0x092E) -#define TCD0_PERBUF _SFR_MEM16(0x0936) -#define TCD0_CCABUF _SFR_MEM16(0x0938) -#define TCD0_CCBBUF _SFR_MEM16(0x093A) -#define TCD0_CCCBUF _SFR_MEM16(0x093C) -#define TCD0_CCDBUF _SFR_MEM16(0x093E) - -/* USARTD0 - Universal Asynchronous Receiver-Transmitter D0 */ -#define USARTD0_DATA _SFR_MEM8(0x09A0) -#define USARTD0_STATUS _SFR_MEM8(0x09A1) -#define USARTD0_CTRLA _SFR_MEM8(0x09A3) -#define USARTD0_CTRLB _SFR_MEM8(0x09A4) -#define USARTD0_CTRLC _SFR_MEM8(0x09A5) -#define USARTD0_BAUDCTRLA _SFR_MEM8(0x09A6) -#define USARTD0_BAUDCTRLB _SFR_MEM8(0x09A7) - -/* SPID - Serial Peripheral Interface D */ -#define SPID_CTRL _SFR_MEM8(0x09C0) -#define SPID_INTCTRL _SFR_MEM8(0x09C1) -#define SPID_STATUS _SFR_MEM8(0x09C2) -#define SPID_DATA _SFR_MEM8(0x09C3) - -/* TCE0 - Timer/Counter E0 */ -#define TCE0_CTRLA _SFR_MEM8(0x0A00) -#define TCE0_CTRLB _SFR_MEM8(0x0A01) -#define TCE0_CTRLC _SFR_MEM8(0x0A02) -#define TCE0_CTRLD _SFR_MEM8(0x0A03) -#define TCE0_CTRLE _SFR_MEM8(0x0A04) -#define TCE0_INTCTRLA _SFR_MEM8(0x0A06) -#define TCE0_INTCTRLB _SFR_MEM8(0x0A07) -#define TCE0_CTRLFCLR _SFR_MEM8(0x0A08) -#define TCE0_CTRLFSET _SFR_MEM8(0x0A09) -#define TCE0_CTRLGCLR _SFR_MEM8(0x0A0A) -#define TCE0_CTRLGSET _SFR_MEM8(0x0A0B) -#define TCE0_INTFLAGS _SFR_MEM8(0x0A0C) -#define TCE0_TEMP _SFR_MEM8(0x0A0F) -#define TCE0_CNT _SFR_MEM16(0x0A20) -#define TCE0_PER _SFR_MEM16(0x0A26) -#define TCE0_CCA _SFR_MEM16(0x0A28) -#define TCE0_CCB _SFR_MEM16(0x0A2A) -#define TCE0_CCC _SFR_MEM16(0x0A2C) -#define TCE0_CCD _SFR_MEM16(0x0A2E) -#define TCE0_PERBUF _SFR_MEM16(0x0A36) -#define TCE0_CCABUF _SFR_MEM16(0x0A38) -#define TCE0_CCBBUF _SFR_MEM16(0x0A3A) -#define TCE0_CCCBUF _SFR_MEM16(0x0A3C) -#define TCE0_CCDBUF _SFR_MEM16(0x0A3E) - - - -/*================== Bitfield Definitions ================== */ - -/* XOCD - On-Chip Debug System */ -/* OCD.OCDR1 bit masks and bit positions */ -#define OCD_OCDRD_bm 0x01 /* OCDR Dirty bit mask. */ -#define OCD_OCDRD_bp 0 /* OCDR Dirty bit position. */ - - -/* CPU - CPU */ -/* CPU.CCP bit masks and bit positions */ -#define CPU_CCP_gm 0xFF /* CCP signature group mask. */ -#define CPU_CCP_gp 0 /* CCP signature group position. */ -#define CPU_CCP0_bm (1<<0) /* CCP signature bit 0 mask. */ -#define CPU_CCP0_bp 0 /* CCP signature bit 0 position. */ -#define CPU_CCP1_bm (1<<1) /* CCP signature bit 1 mask. */ -#define CPU_CCP1_bp 1 /* CCP signature bit 1 position. */ -#define CPU_CCP2_bm (1<<2) /* CCP signature bit 2 mask. */ -#define CPU_CCP2_bp 2 /* CCP signature bit 2 position. */ -#define CPU_CCP3_bm (1<<3) /* CCP signature bit 3 mask. */ -#define CPU_CCP3_bp 3 /* CCP signature bit 3 position. */ -#define CPU_CCP4_bm (1<<4) /* CCP signature bit 4 mask. */ -#define CPU_CCP4_bp 4 /* CCP signature bit 4 position. */ -#define CPU_CCP5_bm (1<<5) /* CCP signature bit 5 mask. */ -#define CPU_CCP5_bp 5 /* CCP signature bit 5 position. */ -#define CPU_CCP6_bm (1<<6) /* CCP signature bit 6 mask. */ -#define CPU_CCP6_bp 6 /* CCP signature bit 6 position. */ -#define CPU_CCP7_bm (1<<7) /* CCP signature bit 7 mask. */ -#define CPU_CCP7_bp 7 /* CCP signature bit 7 position. */ - - -/* CPU.SREG bit masks and bit positions */ -#define CPU_I_bm 0x80 /* Global Interrupt Enable Flag bit mask. */ -#define CPU_I_bp 7 /* Global Interrupt Enable Flag bit position. */ - -#define CPU_T_bm 0x40 /* Transfer Bit bit mask. */ -#define CPU_T_bp 6 /* Transfer Bit bit position. */ - -#define CPU_H_bm 0x20 /* Half Carry Flag bit mask. */ -#define CPU_H_bp 5 /* Half Carry Flag bit position. */ - -#define CPU_S_bm 0x10 /* N Exclusive Or V Flag bit mask. */ -#define CPU_S_bp 4 /* N Exclusive Or V Flag bit position. */ - -#define CPU_V_bm 0x08 /* Two's Complement Overflow Flag bit mask. */ -#define CPU_V_bp 3 /* Two's Complement Overflow Flag bit position. */ - -#define CPU_N_bm 0x04 /* Negative Flag bit mask. */ -#define CPU_N_bp 2 /* Negative Flag bit position. */ - -#define CPU_Z_bm 0x02 /* Zero Flag bit mask. */ -#define CPU_Z_bp 1 /* Zero Flag bit position. */ - -#define CPU_C_bm 0x01 /* Carry Flag bit mask. */ -#define CPU_C_bp 0 /* Carry Flag bit position. */ - - -/* CLK - Clock System */ -/* CLK.CTRL bit masks and bit positions */ -#define CLK_SCLKSEL_gm 0x07 /* System Clock Selection group mask. */ -#define CLK_SCLKSEL_gp 0 /* System Clock Selection group position. */ -#define CLK_SCLKSEL0_bm (1<<0) /* System Clock Selection bit 0 mask. */ -#define CLK_SCLKSEL0_bp 0 /* System Clock Selection bit 0 position. */ -#define CLK_SCLKSEL1_bm (1<<1) /* System Clock Selection bit 1 mask. */ -#define CLK_SCLKSEL1_bp 1 /* System Clock Selection bit 1 position. */ -#define CLK_SCLKSEL2_bm (1<<2) /* System Clock Selection bit 2 mask. */ -#define CLK_SCLKSEL2_bp 2 /* System Clock Selection bit 2 position. */ - - -/* CLK.PSCTRL bit masks and bit positions */ -#define CLK_PSADIV_gm 0x7C /* Prescaler A Division Factor group mask. */ -#define CLK_PSADIV_gp 2 /* Prescaler A Division Factor group position. */ -#define CLK_PSADIV0_bm (1<<2) /* Prescaler A Division Factor bit 0 mask. */ -#define CLK_PSADIV0_bp 2 /* Prescaler A Division Factor bit 0 position. */ -#define CLK_PSADIV1_bm (1<<3) /* Prescaler A Division Factor bit 1 mask. */ -#define CLK_PSADIV1_bp 3 /* Prescaler A Division Factor bit 1 position. */ -#define CLK_PSADIV2_bm (1<<4) /* Prescaler A Division Factor bit 2 mask. */ -#define CLK_PSADIV2_bp 4 /* Prescaler A Division Factor bit 2 position. */ -#define CLK_PSADIV3_bm (1<<5) /* Prescaler A Division Factor bit 3 mask. */ -#define CLK_PSADIV3_bp 5 /* Prescaler A Division Factor bit 3 position. */ -#define CLK_PSADIV4_bm (1<<6) /* Prescaler A Division Factor bit 4 mask. */ -#define CLK_PSADIV4_bp 6 /* Prescaler A Division Factor bit 4 position. */ - -#define CLK_PSBCDIV_gm 0x03 /* Prescaler B and C Division factor group mask. */ -#define CLK_PSBCDIV_gp 0 /* Prescaler B and C Division factor group position. */ -#define CLK_PSBCDIV0_bm (1<<0) /* Prescaler B and C Division factor bit 0 mask. */ -#define CLK_PSBCDIV0_bp 0 /* Prescaler B and C Division factor bit 0 position. */ -#define CLK_PSBCDIV1_bm (1<<1) /* Prescaler B and C Division factor bit 1 mask. */ -#define CLK_PSBCDIV1_bp 1 /* Prescaler B and C Division factor bit 1 position. */ - - -/* CLK.LOCK bit masks and bit positions */ -#define CLK_LOCK_bm 0x01 /* Clock System Lock bit mask. */ -#define CLK_LOCK_bp 0 /* Clock System Lock bit position. */ - - -/* CLK.RTCCTRL bit masks and bit positions */ -#define CLK_RTCSRC_gm 0x0E /* Clock Source group mask. */ -#define CLK_RTCSRC_gp 1 /* Clock Source group position. */ -#define CLK_RTCSRC0_bm (1<<1) /* Clock Source bit 0 mask. */ -#define CLK_RTCSRC0_bp 1 /* Clock Source bit 0 position. */ -#define CLK_RTCSRC1_bm (1<<2) /* Clock Source bit 1 mask. */ -#define CLK_RTCSRC1_bp 2 /* Clock Source bit 1 position. */ -#define CLK_RTCSRC2_bm (1<<3) /* Clock Source bit 2 mask. */ -#define CLK_RTCSRC2_bp 3 /* Clock Source bit 2 position. */ - -#define CLK_RTCEN_bm 0x01 /* RTC Clock Source Enable bit mask. */ -#define CLK_RTCEN_bp 0 /* RTC Clock Source Enable bit position. */ - - -/* PR.PRGEN bit masks and bit positions */ -#define PR_AES_bm 0x10 /* AES bit mask. */ -#define PR_AES_bp 4 /* AES bit position. */ - -#define PR_EBI_bm 0x08 /* External Bus Interface bit mask. */ -#define PR_EBI_bp 3 /* External Bus Interface bit position. */ - -#define PR_RTC_bm 0x04 /* Real-time Counter bit mask. */ -#define PR_RTC_bp 2 /* Real-time Counter bit position. */ - -#define PR_EVSYS_bm 0x02 /* Event System bit mask. */ -#define PR_EVSYS_bp 1 /* Event System bit position. */ - -#define PR_DMA_bm 0x01 /* DMA-Controller bit mask. */ -#define PR_DMA_bp 0 /* DMA-Controller bit position. */ - - -/* PR.PRPA bit masks and bit positions */ -#define PR_DAC_bm 0x04 /* Port A DAC bit mask. */ -#define PR_DAC_bp 2 /* Port A DAC bit position. */ - -#define PR_ADC_bm 0x02 /* Port A ADC bit mask. */ -#define PR_ADC_bp 1 /* Port A ADC bit position. */ - -#define PR_AC_bm 0x01 /* Port A Analog Comparator bit mask. */ -#define PR_AC_bp 0 /* Port A Analog Comparator bit position. */ - - -/* PR.PRPB bit masks and bit positions */ -/* PR_DAC_bm Predefined. */ -/* PR_DAC_bp Predefined. */ - -/* PR_ADC_bm Predefined. */ -/* PR_ADC_bp Predefined. */ - -/* PR_AC_bm Predefined. */ -/* PR_AC_bp Predefined. */ - - -/* PR.PRPC bit masks and bit positions */ -#define PR_TWI_bm 0x40 /* Port C Two-wire Interface bit mask. */ -#define PR_TWI_bp 6 /* Port C Two-wire Interface bit position. */ - -#define PR_USART1_bm 0x20 /* Port C USART1 bit mask. */ -#define PR_USART1_bp 5 /* Port C USART1 bit position. */ - -#define PR_USART0_bm 0x10 /* Port C USART0 bit mask. */ -#define PR_USART0_bp 4 /* Port C USART0 bit position. */ - -#define PR_SPI_bm 0x08 /* Port C SPI bit mask. */ -#define PR_SPI_bp 3 /* Port C SPI bit position. */ - -#define PR_HIRES_bm 0x04 /* Port C AWEX bit mask. */ -#define PR_HIRES_bp 2 /* Port C AWEX bit position. */ - -#define PR_TC1_bm 0x02 /* Port C Timer/Counter1 bit mask. */ -#define PR_TC1_bp 1 /* Port C Timer/Counter1 bit position. */ - -#define PR_TC0_bm 0x01 /* Port C Timer/Counter0 bit mask. */ -#define PR_TC0_bp 0 /* Port C Timer/Counter0 bit position. */ - - -/* PR.PRPD bit masks and bit positions */ -/* PR_TWI_bm Predefined. */ -/* PR_TWI_bp Predefined. */ - -/* PR_USART1_bm Predefined. */ -/* PR_USART1_bp Predefined. */ - -/* PR_USART0_bm Predefined. */ -/* PR_USART0_bp Predefined. */ - -/* PR_SPI_bm Predefined. */ -/* PR_SPI_bp Predefined. */ - -/* PR_HIRES_bm Predefined. */ -/* PR_HIRES_bp Predefined. */ - -/* PR_TC1_bm Predefined. */ -/* PR_TC1_bp Predefined. */ - -/* PR_TC0_bm Predefined. */ -/* PR_TC0_bp Predefined. */ - - -/* PR.PRPE bit masks and bit positions */ -/* PR_TWI_bm Predefined. */ -/* PR_TWI_bp Predefined. */ - -/* PR_USART1_bm Predefined. */ -/* PR_USART1_bp Predefined. */ - -/* PR_USART0_bm Predefined. */ -/* PR_USART0_bp Predefined. */ - -/* PR_SPI_bm Predefined. */ -/* PR_SPI_bp Predefined. */ - -/* PR_HIRES_bm Predefined. */ -/* PR_HIRES_bp Predefined. */ - -/* PR_TC1_bm Predefined. */ -/* PR_TC1_bp Predefined. */ - -/* PR_TC0_bm Predefined. */ -/* PR_TC0_bp Predefined. */ - - -/* PR.PRPF bit masks and bit positions */ -/* PR_TWI_bm Predefined. */ -/* PR_TWI_bp Predefined. */ - -/* PR_USART1_bm Predefined. */ -/* PR_USART1_bp Predefined. */ - -/* PR_USART0_bm Predefined. */ -/* PR_USART0_bp Predefined. */ - -/* PR_SPI_bm Predefined. */ -/* PR_SPI_bp Predefined. */ - -/* PR_HIRES_bm Predefined. */ -/* PR_HIRES_bp Predefined. */ - -/* PR_TC1_bm Predefined. */ -/* PR_TC1_bp Predefined. */ - -/* PR_TC0_bm Predefined. */ -/* PR_TC0_bp Predefined. */ - - -/* SLEEP - Sleep Controller */ -/* SLEEP.CTRL bit masks and bit positions */ -#define SLEEP_SMODE_gm 0x0E /* Sleep Mode group mask. */ -#define SLEEP_SMODE_gp 1 /* Sleep Mode group position. */ -#define SLEEP_SMODE0_bm (1<<1) /* Sleep Mode bit 0 mask. */ -#define SLEEP_SMODE0_bp 1 /* Sleep Mode bit 0 position. */ -#define SLEEP_SMODE1_bm (1<<2) /* Sleep Mode bit 1 mask. */ -#define SLEEP_SMODE1_bp 2 /* Sleep Mode bit 1 position. */ -#define SLEEP_SMODE2_bm (1<<3) /* Sleep Mode bit 2 mask. */ -#define SLEEP_SMODE2_bp 3 /* Sleep Mode bit 2 position. */ - -#define SLEEP_SEN_bm 0x01 /* Sleep Enable bit mask. */ -#define SLEEP_SEN_bp 0 /* Sleep Enable bit position. */ - - -/* OSC - Oscillator */ -/* OSC.CTRL bit masks and bit positions */ -#define OSC_PLLEN_bm 0x10 /* PLL Enable bit mask. */ -#define OSC_PLLEN_bp 4 /* PLL Enable bit position. */ - -#define OSC_XOSCEN_bm 0x08 /* External Oscillator Enable bit mask. */ -#define OSC_XOSCEN_bp 3 /* External Oscillator Enable bit position. */ - -#define OSC_RC32KEN_bm 0x04 /* Internal 32kHz RC Oscillator Enable bit mask. */ -#define OSC_RC32KEN_bp 2 /* Internal 32kHz RC Oscillator Enable bit position. */ - -#define OSC_RC32MEN_bm 0x02 /* Internal 32MHz RC Oscillator Enable bit mask. */ -#define OSC_RC32MEN_bp 1 /* Internal 32MHz RC Oscillator Enable bit position. */ - -#define OSC_RC2MEN_bm 0x01 /* Internal 2MHz RC Oscillator Enable bit mask. */ -#define OSC_RC2MEN_bp 0 /* Internal 2MHz RC Oscillator Enable bit position. */ - - -/* OSC.STATUS bit masks and bit positions */ -#define OSC_PLLRDY_bm 0x10 /* PLL Ready bit mask. */ -#define OSC_PLLRDY_bp 4 /* PLL Ready bit position. */ - -#define OSC_XOSCRDY_bm 0x08 /* External Oscillator Ready bit mask. */ -#define OSC_XOSCRDY_bp 3 /* External Oscillator Ready bit position. */ - -#define OSC_RC32KRDY_bm 0x04 /* Internal 32kHz RC Oscillator Ready bit mask. */ -#define OSC_RC32KRDY_bp 2 /* Internal 32kHz RC Oscillator Ready bit position. */ - -#define OSC_RC32MRDY_bm 0x02 /* Internal 32MHz RC Oscillator Ready bit mask. */ -#define OSC_RC32MRDY_bp 1 /* Internal 32MHz RC Oscillator Ready bit position. */ - -#define OSC_RC2MRDY_bm 0x01 /* Internal 2MHz RC Oscillator Ready bit mask. */ -#define OSC_RC2MRDY_bp 0 /* Internal 2MHz RC Oscillator Ready bit position. */ - - -/* OSC.XOSCCTRL bit masks and bit positions */ -#define OSC_FRQRANGE_gm 0xC0 /* Frequency Range group mask. */ -#define OSC_FRQRANGE_gp 6 /* Frequency Range group position. */ -#define OSC_FRQRANGE0_bm (1<<6) /* Frequency Range bit 0 mask. */ -#define OSC_FRQRANGE0_bp 6 /* Frequency Range bit 0 position. */ -#define OSC_FRQRANGE1_bm (1<<7) /* Frequency Range bit 1 mask. */ -#define OSC_FRQRANGE1_bp 7 /* Frequency Range bit 1 position. */ - -#define OSC_X32KLPM_bm 0x20 /* 32kHz XTAL OSC Low-power Mode bit mask. */ -#define OSC_X32KLPM_bp 5 /* 32kHz XTAL OSC Low-power Mode bit position. */ - -#define OSC_XOSCSEL_gm 0x0F /* External Oscillator Selection and Startup Time group mask. */ -#define OSC_XOSCSEL_gp 0 /* External Oscillator Selection and Startup Time group position. */ -#define OSC_XOSCSEL0_bm (1<<0) /* External Oscillator Selection and Startup Time bit 0 mask. */ -#define OSC_XOSCSEL0_bp 0 /* External Oscillator Selection and Startup Time bit 0 position. */ -#define OSC_XOSCSEL1_bm (1<<1) /* External Oscillator Selection and Startup Time bit 1 mask. */ -#define OSC_XOSCSEL1_bp 1 /* External Oscillator Selection and Startup Time bit 1 position. */ -#define OSC_XOSCSEL2_bm (1<<2) /* External Oscillator Selection and Startup Time bit 2 mask. */ -#define OSC_XOSCSEL2_bp 2 /* External Oscillator Selection and Startup Time bit 2 position. */ -#define OSC_XOSCSEL3_bm (1<<3) /* External Oscillator Selection and Startup Time bit 3 mask. */ -#define OSC_XOSCSEL3_bp 3 /* External Oscillator Selection and Startup Time bit 3 position. */ - - -/* OSC.XOSCFAIL bit masks and bit positions */ -#define OSC_XOSCFDIF_bm 0x02 /* Failure Detection Interrupt Flag bit mask. */ -#define OSC_XOSCFDIF_bp 1 /* Failure Detection Interrupt Flag bit position. */ - -#define OSC_XOSCFDEN_bm 0x01 /* Failure Detection Enable bit mask. */ -#define OSC_XOSCFDEN_bp 0 /* Failure Detection Enable bit position. */ - - -/* OSC.PLLCTRL bit masks and bit positions */ -#define OSC_PLLSRC_gm 0xC0 /* Clock Source group mask. */ -#define OSC_PLLSRC_gp 6 /* Clock Source group position. */ -#define OSC_PLLSRC0_bm (1<<6) /* Clock Source bit 0 mask. */ -#define OSC_PLLSRC0_bp 6 /* Clock Source bit 0 position. */ -#define OSC_PLLSRC1_bm (1<<7) /* Clock Source bit 1 mask. */ -#define OSC_PLLSRC1_bp 7 /* Clock Source bit 1 position. */ - -#define OSC_PLLFAC_gm 0x1F /* Multiplication Factor group mask. */ -#define OSC_PLLFAC_gp 0 /* Multiplication Factor group position. */ -#define OSC_PLLFAC0_bm (1<<0) /* Multiplication Factor bit 0 mask. */ -#define OSC_PLLFAC0_bp 0 /* Multiplication Factor bit 0 position. */ -#define OSC_PLLFAC1_bm (1<<1) /* Multiplication Factor bit 1 mask. */ -#define OSC_PLLFAC1_bp 1 /* Multiplication Factor bit 1 position. */ -#define OSC_PLLFAC2_bm (1<<2) /* Multiplication Factor bit 2 mask. */ -#define OSC_PLLFAC2_bp 2 /* Multiplication Factor bit 2 position. */ -#define OSC_PLLFAC3_bm (1<<3) /* Multiplication Factor bit 3 mask. */ -#define OSC_PLLFAC3_bp 3 /* Multiplication Factor bit 3 position. */ -#define OSC_PLLFAC4_bm (1<<4) /* Multiplication Factor bit 4 mask. */ -#define OSC_PLLFAC4_bp 4 /* Multiplication Factor bit 4 position. */ - - -/* OSC.DFLLCTRL bit masks and bit positions */ -#define OSC_RC32MCREF_bm 0x02 /* 32MHz Calibration Reference bit mask. */ -#define OSC_RC32MCREF_bp 1 /* 32MHz Calibration Reference bit position. */ - -#define OSC_RC2MCREF_bm 0x01 /* 2MHz Calibration Reference bit mask. */ -#define OSC_RC2MCREF_bp 0 /* 2MHz Calibration Reference bit position. */ - - -/* DFLL - DFLL */ -/* DFLL.CTRL bit masks and bit positions */ -#define DFLL_ENABLE_bm 0x01 /* DFLL Enable bit mask. */ -#define DFLL_ENABLE_bp 0 /* DFLL Enable bit position. */ - - -/* DFLL.CALA bit masks and bit positions */ -#define DFLL_CALL_gm 0x7F /* DFLL Calibration bits [6:0] group mask. */ -#define DFLL_CALL_gp 0 /* DFLL Calibration bits [6:0] group position. */ -#define DFLL_CALL0_bm (1<<0) /* DFLL Calibration bits [6:0] bit 0 mask. */ -#define DFLL_CALL0_bp 0 /* DFLL Calibration bits [6:0] bit 0 position. */ -#define DFLL_CALL1_bm (1<<1) /* DFLL Calibration bits [6:0] bit 1 mask. */ -#define DFLL_CALL1_bp 1 /* DFLL Calibration bits [6:0] bit 1 position. */ -#define DFLL_CALL2_bm (1<<2) /* DFLL Calibration bits [6:0] bit 2 mask. */ -#define DFLL_CALL2_bp 2 /* DFLL Calibration bits [6:0] bit 2 position. */ -#define DFLL_CALL3_bm (1<<3) /* DFLL Calibration bits [6:0] bit 3 mask. */ -#define DFLL_CALL3_bp 3 /* DFLL Calibration bits [6:0] bit 3 position. */ -#define DFLL_CALL4_bm (1<<4) /* DFLL Calibration bits [6:0] bit 4 mask. */ -#define DFLL_CALL4_bp 4 /* DFLL Calibration bits [6:0] bit 4 position. */ -#define DFLL_CALL5_bm (1<<5) /* DFLL Calibration bits [6:0] bit 5 mask. */ -#define DFLL_CALL5_bp 5 /* DFLL Calibration bits [6:0] bit 5 position. */ -#define DFLL_CALL6_bm (1<<6) /* DFLL Calibration bits [6:0] bit 6 mask. */ -#define DFLL_CALL6_bp 6 /* DFLL Calibration bits [6:0] bit 6 position. */ - - -/* DFLL.CALB bit masks and bit positions */ -#define DFLL_CALH_gm 0x3F /* DFLL Calibration bits [12:7] group mask. */ -#define DFLL_CALH_gp 0 /* DFLL Calibration bits [12:7] group position. */ -#define DFLL_CALH0_bm (1<<0) /* DFLL Calibration bits [12:7] bit 0 mask. */ -#define DFLL_CALH0_bp 0 /* DFLL Calibration bits [12:7] bit 0 position. */ -#define DFLL_CALH1_bm (1<<1) /* DFLL Calibration bits [12:7] bit 1 mask. */ -#define DFLL_CALH1_bp 1 /* DFLL Calibration bits [12:7] bit 1 position. */ -#define DFLL_CALH2_bm (1<<2) /* DFLL Calibration bits [12:7] bit 2 mask. */ -#define DFLL_CALH2_bp 2 /* DFLL Calibration bits [12:7] bit 2 position. */ -#define DFLL_CALH3_bm (1<<3) /* DFLL Calibration bits [12:7] bit 3 mask. */ -#define DFLL_CALH3_bp 3 /* DFLL Calibration bits [12:7] bit 3 position. */ -#define DFLL_CALH4_bm (1<<4) /* DFLL Calibration bits [12:7] bit 4 mask. */ -#define DFLL_CALH4_bp 4 /* DFLL Calibration bits [12:7] bit 4 position. */ -#define DFLL_CALH5_bm (1<<5) /* DFLL Calibration bits [12:7] bit 5 mask. */ -#define DFLL_CALH5_bp 5 /* DFLL Calibration bits [12:7] bit 5 position. */ - - -/* RST - Reset */ -/* RST.STATUS bit masks and bit positions */ -#define RST_SDRF_bm 0x40 /* Spike Detection Reset Flag bit mask. */ -#define RST_SDRF_bp 6 /* Spike Detection Reset Flag bit position. */ - -#define RST_SRF_bm 0x20 /* Software Reset Flag bit mask. */ -#define RST_SRF_bp 5 /* Software Reset Flag bit position. */ - -#define RST_PDIRF_bm 0x10 /* Programming and Debug Interface Interface Reset Flag bit mask. */ -#define RST_PDIRF_bp 4 /* Programming and Debug Interface Interface Reset Flag bit position. */ - -#define RST_WDRF_bm 0x08 /* Watchdog Reset Flag bit mask. */ -#define RST_WDRF_bp 3 /* Watchdog Reset Flag bit position. */ - -#define RST_BORF_bm 0x04 /* Brown-out Reset Flag bit mask. */ -#define RST_BORF_bp 2 /* Brown-out Reset Flag bit position. */ - -#define RST_EXTRF_bm 0x02 /* External Reset Flag bit mask. */ -#define RST_EXTRF_bp 1 /* External Reset Flag bit position. */ - -#define RST_PORF_bm 0x01 /* Power-on Reset Flag bit mask. */ -#define RST_PORF_bp 0 /* Power-on Reset Flag bit position. */ - - -/* RST.CTRL bit masks and bit positions */ -#define RST_SWRST_bm 0x01 /* Software Reset bit mask. */ -#define RST_SWRST_bp 0 /* Software Reset bit position. */ - - -/* WDT - Watch-Dog Timer */ -/* WDT.CTRL bit masks and bit positions */ -#define WDT_PER_gm 0x3C /* Period group mask. */ -#define WDT_PER_gp 2 /* Period group position. */ -#define WDT_PER0_bm (1<<2) /* Period bit 0 mask. */ -#define WDT_PER0_bp 2 /* Period bit 0 position. */ -#define WDT_PER1_bm (1<<3) /* Period bit 1 mask. */ -#define WDT_PER1_bp 3 /* Period bit 1 position. */ -#define WDT_PER2_bm (1<<4) /* Period bit 2 mask. */ -#define WDT_PER2_bp 4 /* Period bit 2 position. */ -#define WDT_PER3_bm (1<<5) /* Period bit 3 mask. */ -#define WDT_PER3_bp 5 /* Period bit 3 position. */ - -#define WDT_ENABLE_bm 0x02 /* Enable bit mask. */ -#define WDT_ENABLE_bp 1 /* Enable bit position. */ - -#define WDT_CEN_bm 0x01 /* Change Enable bit mask. */ -#define WDT_CEN_bp 0 /* Change Enable bit position. */ - - -/* WDT.WINCTRL bit masks and bit positions */ -#define WDT_WPER_gm 0x3C /* Windowed Mode Period group mask. */ -#define WDT_WPER_gp 2 /* Windowed Mode Period group position. */ -#define WDT_WPER0_bm (1<<2) /* Windowed Mode Period bit 0 mask. */ -#define WDT_WPER0_bp 2 /* Windowed Mode Period bit 0 position. */ -#define WDT_WPER1_bm (1<<3) /* Windowed Mode Period bit 1 mask. */ -#define WDT_WPER1_bp 3 /* Windowed Mode Period bit 1 position. */ -#define WDT_WPER2_bm (1<<4) /* Windowed Mode Period bit 2 mask. */ -#define WDT_WPER2_bp 4 /* Windowed Mode Period bit 2 position. */ -#define WDT_WPER3_bm (1<<5) /* Windowed Mode Period bit 3 mask. */ -#define WDT_WPER3_bp 5 /* Windowed Mode Period bit 3 position. */ - -#define WDT_WEN_bm 0x02 /* Windowed Mode Enable bit mask. */ -#define WDT_WEN_bp 1 /* Windowed Mode Enable bit position. */ - -#define WDT_WCEN_bm 0x01 /* Windowed Mode Change Enable bit mask. */ -#define WDT_WCEN_bp 0 /* Windowed Mode Change Enable bit position. */ - - -/* WDT.STATUS bit masks and bit positions */ -#define WDT_SYNCBUSY_bm 0x01 /* Syncronization busy bit mask. */ -#define WDT_SYNCBUSY_bp 0 /* Syncronization busy bit position. */ - - -/* MCU - MCU Control */ -/* MCU.MCUCR bit masks and bit positions */ -#define MCU_JTAGD_bm 0x01 /* JTAG Disable bit mask. */ -#define MCU_JTAGD_bp 0 /* JTAG Disable bit position. */ - - -/* MCU.EVSYSLOCK bit masks and bit positions */ -#define MCU_EVSYS1LOCK_bm 0x10 /* Event Channel 4-7 Lock bit mask. */ -#define MCU_EVSYS1LOCK_bp 4 /* Event Channel 4-7 Lock bit position. */ - -#define MCU_EVSYS0LOCK_bm 0x01 /* Event Channel 0-3 Lock bit mask. */ -#define MCU_EVSYS0LOCK_bp 0 /* Event Channel 0-3 Lock bit position. */ - - -/* MCU.AWEXLOCK bit masks and bit positions */ -#define MCU_AWEXELOCK_bm 0x04 /* AWeX on T/C E0 Lock bit mask. */ -#define MCU_AWEXELOCK_bp 2 /* AWeX on T/C E0 Lock bit position. */ - -#define MCU_AWEXCLOCK_bm 0x01 /* AWeX on T/C C0 Lock bit mask. */ -#define MCU_AWEXCLOCK_bp 0 /* AWeX on T/C C0 Lock bit position. */ - - -/* PMIC - Programmable Multi-level Interrupt Controller */ -/* PMIC.STATUS bit masks and bit positions */ -#define PMIC_NMIEX_bm 0x80 /* Non-maskable Interrupt Executing bit mask. */ -#define PMIC_NMIEX_bp 7 /* Non-maskable Interrupt Executing bit position. */ - -#define PMIC_HILVLEX_bm 0x04 /* High Level Interrupt Executing bit mask. */ -#define PMIC_HILVLEX_bp 2 /* High Level Interrupt Executing bit position. */ - -#define PMIC_MEDLVLEX_bm 0x02 /* Medium Level Interrupt Executing bit mask. */ -#define PMIC_MEDLVLEX_bp 1 /* Medium Level Interrupt Executing bit position. */ - -#define PMIC_LOLVLEX_bm 0x01 /* Low Level Interrupt Executing bit mask. */ -#define PMIC_LOLVLEX_bp 0 /* Low Level Interrupt Executing bit position. */ - - -/* PMIC.CTRL bit masks and bit positions */ -#define PMIC_RREN_bm 0x80 /* Round-Robin Priority Enable bit mask. */ -#define PMIC_RREN_bp 7 /* Round-Robin Priority Enable bit position. */ - -#define PMIC_IVSEL_bm 0x40 /* Interrupt Vector Select bit mask. */ -#define PMIC_IVSEL_bp 6 /* Interrupt Vector Select bit position. */ - -#define PMIC_HILVLEN_bm 0x04 /* High Level Enable bit mask. */ -#define PMIC_HILVLEN_bp 2 /* High Level Enable bit position. */ - -#define PMIC_MEDLVLEN_bm 0x02 /* Medium Level Enable bit mask. */ -#define PMIC_MEDLVLEN_bp 1 /* Medium Level Enable bit position. */ - -#define PMIC_LOLVLEN_bm 0x01 /* Low Level Enable bit mask. */ -#define PMIC_LOLVLEN_bp 0 /* Low Level Enable bit position. */ - - -/* EVSYS - Event System */ -/* EVSYS.CH0MUX bit masks and bit positions */ -#define EVSYS_CHMUX_gm 0xFF /* Event Channel 0 Multiplexer group mask. */ -#define EVSYS_CHMUX_gp 0 /* Event Channel 0 Multiplexer group position. */ -#define EVSYS_CHMUX0_bm (1<<0) /* Event Channel 0 Multiplexer bit 0 mask. */ -#define EVSYS_CHMUX0_bp 0 /* Event Channel 0 Multiplexer bit 0 position. */ -#define EVSYS_CHMUX1_bm (1<<1) /* Event Channel 0 Multiplexer bit 1 mask. */ -#define EVSYS_CHMUX1_bp 1 /* Event Channel 0 Multiplexer bit 1 position. */ -#define EVSYS_CHMUX2_bm (1<<2) /* Event Channel 0 Multiplexer bit 2 mask. */ -#define EVSYS_CHMUX2_bp 2 /* Event Channel 0 Multiplexer bit 2 position. */ -#define EVSYS_CHMUX3_bm (1<<3) /* Event Channel 0 Multiplexer bit 3 mask. */ -#define EVSYS_CHMUX3_bp 3 /* Event Channel 0 Multiplexer bit 3 position. */ -#define EVSYS_CHMUX4_bm (1<<4) /* Event Channel 0 Multiplexer bit 4 mask. */ -#define EVSYS_CHMUX4_bp 4 /* Event Channel 0 Multiplexer bit 4 position. */ -#define EVSYS_CHMUX5_bm (1<<5) /* Event Channel 0 Multiplexer bit 5 mask. */ -#define EVSYS_CHMUX5_bp 5 /* Event Channel 0 Multiplexer bit 5 position. */ -#define EVSYS_CHMUX6_bm (1<<6) /* Event Channel 0 Multiplexer bit 6 mask. */ -#define EVSYS_CHMUX6_bp 6 /* Event Channel 0 Multiplexer bit 6 position. */ -#define EVSYS_CHMUX7_bm (1<<7) /* Event Channel 0 Multiplexer bit 7 mask. */ -#define EVSYS_CHMUX7_bp 7 /* Event Channel 0 Multiplexer bit 7 position. */ - - -/* EVSYS.CH1MUX bit masks and bit positions */ -/* EVSYS_CHMUX_gm Predefined. */ -/* EVSYS_CHMUX_gp Predefined. */ -/* EVSYS_CHMUX0_bm Predefined. */ -/* EVSYS_CHMUX0_bp Predefined. */ -/* EVSYS_CHMUX1_bm Predefined. */ -/* EVSYS_CHMUX1_bp Predefined. */ -/* EVSYS_CHMUX2_bm Predefined. */ -/* EVSYS_CHMUX2_bp Predefined. */ -/* EVSYS_CHMUX3_bm Predefined. */ -/* EVSYS_CHMUX3_bp Predefined. */ -/* EVSYS_CHMUX4_bm Predefined. */ -/* EVSYS_CHMUX4_bp Predefined. */ -/* EVSYS_CHMUX5_bm Predefined. */ -/* EVSYS_CHMUX5_bp Predefined. */ -/* EVSYS_CHMUX6_bm Predefined. */ -/* EVSYS_CHMUX6_bp Predefined. */ -/* EVSYS_CHMUX7_bm Predefined. */ -/* EVSYS_CHMUX7_bp Predefined. */ - - -/* EVSYS.CH2MUX bit masks and bit positions */ -/* EVSYS_CHMUX_gm Predefined. */ -/* EVSYS_CHMUX_gp Predefined. */ -/* EVSYS_CHMUX0_bm Predefined. */ -/* EVSYS_CHMUX0_bp Predefined. */ -/* EVSYS_CHMUX1_bm Predefined. */ -/* EVSYS_CHMUX1_bp Predefined. */ -/* EVSYS_CHMUX2_bm Predefined. */ -/* EVSYS_CHMUX2_bp Predefined. */ -/* EVSYS_CHMUX3_bm Predefined. */ -/* EVSYS_CHMUX3_bp Predefined. */ -/* EVSYS_CHMUX4_bm Predefined. */ -/* EVSYS_CHMUX4_bp Predefined. */ -/* EVSYS_CHMUX5_bm Predefined. */ -/* EVSYS_CHMUX5_bp Predefined. */ -/* EVSYS_CHMUX6_bm Predefined. */ -/* EVSYS_CHMUX6_bp Predefined. */ -/* EVSYS_CHMUX7_bm Predefined. */ -/* EVSYS_CHMUX7_bp Predefined. */ - - -/* EVSYS.CH3MUX bit masks and bit positions */ -/* EVSYS_CHMUX_gm Predefined. */ -/* EVSYS_CHMUX_gp Predefined. */ -/* EVSYS_CHMUX0_bm Predefined. */ -/* EVSYS_CHMUX0_bp Predefined. */ -/* EVSYS_CHMUX1_bm Predefined. */ -/* EVSYS_CHMUX1_bp Predefined. */ -/* EVSYS_CHMUX2_bm Predefined. */ -/* EVSYS_CHMUX2_bp Predefined. */ -/* EVSYS_CHMUX3_bm Predefined. */ -/* EVSYS_CHMUX3_bp Predefined. */ -/* EVSYS_CHMUX4_bm Predefined. */ -/* EVSYS_CHMUX4_bp Predefined. */ -/* EVSYS_CHMUX5_bm Predefined. */ -/* EVSYS_CHMUX5_bp Predefined. */ -/* EVSYS_CHMUX6_bm Predefined. */ -/* EVSYS_CHMUX6_bp Predefined. */ -/* EVSYS_CHMUX7_bm Predefined. */ -/* EVSYS_CHMUX7_bp Predefined. */ - - -/* EVSYS.CH0CTRL bit masks and bit positions */ -#define EVSYS_QDIRM_gm 0x60 /* Quadrature Decoder Index Recognition Mode group mask. */ -#define EVSYS_QDIRM_gp 5 /* Quadrature Decoder Index Recognition Mode group position. */ -#define EVSYS_QDIRM0_bm (1<<5) /* Quadrature Decoder Index Recognition Mode bit 0 mask. */ -#define EVSYS_QDIRM0_bp 5 /* Quadrature Decoder Index Recognition Mode bit 0 position. */ -#define EVSYS_QDIRM1_bm (1<<6) /* Quadrature Decoder Index Recognition Mode bit 1 mask. */ -#define EVSYS_QDIRM1_bp 6 /* Quadrature Decoder Index Recognition Mode bit 1 position. */ - -#define EVSYS_QDIEN_bm 0x10 /* Quadrature Decoder Index Enable bit mask. */ -#define EVSYS_QDIEN_bp 4 /* Quadrature Decoder Index Enable bit position. */ - -#define EVSYS_QDEN_bm 0x08 /* Quadrature Decoder Enable bit mask. */ -#define EVSYS_QDEN_bp 3 /* Quadrature Decoder Enable bit position. */ - -#define EVSYS_DIGFILT_gm 0x07 /* Digital Filter group mask. */ -#define EVSYS_DIGFILT_gp 0 /* Digital Filter group position. */ -#define EVSYS_DIGFILT0_bm (1<<0) /* Digital Filter bit 0 mask. */ -#define EVSYS_DIGFILT0_bp 0 /* Digital Filter bit 0 position. */ -#define EVSYS_DIGFILT1_bm (1<<1) /* Digital Filter bit 1 mask. */ -#define EVSYS_DIGFILT1_bp 1 /* Digital Filter bit 1 position. */ -#define EVSYS_DIGFILT2_bm (1<<2) /* Digital Filter bit 2 mask. */ -#define EVSYS_DIGFILT2_bp 2 /* Digital Filter bit 2 position. */ - - -/* EVSYS.CH1CTRL bit masks and bit positions */ -/* EVSYS_DIGFILT_gm Predefined. */ -/* EVSYS_DIGFILT_gp Predefined. */ -/* EVSYS_DIGFILT0_bm Predefined. */ -/* EVSYS_DIGFILT0_bp Predefined. */ -/* EVSYS_DIGFILT1_bm Predefined. */ -/* EVSYS_DIGFILT1_bp Predefined. */ -/* EVSYS_DIGFILT2_bm Predefined. */ -/* EVSYS_DIGFILT2_bp Predefined. */ - - -/* EVSYS.CH2CTRL bit masks and bit positions */ -/* EVSYS_QDIRM_gm Predefined. */ -/* EVSYS_QDIRM_gp Predefined. */ -/* EVSYS_QDIRM0_bm Predefined. */ -/* EVSYS_QDIRM0_bp Predefined. */ -/* EVSYS_QDIRM1_bm Predefined. */ -/* EVSYS_QDIRM1_bp Predefined. */ - -/* EVSYS_QDIEN_bm Predefined. */ -/* EVSYS_QDIEN_bp Predefined. */ - -/* EVSYS_QDEN_bm Predefined. */ -/* EVSYS_QDEN_bp Predefined. */ - -/* EVSYS_DIGFILT_gm Predefined. */ -/* EVSYS_DIGFILT_gp Predefined. */ -/* EVSYS_DIGFILT0_bm Predefined. */ -/* EVSYS_DIGFILT0_bp Predefined. */ -/* EVSYS_DIGFILT1_bm Predefined. */ -/* EVSYS_DIGFILT1_bp Predefined. */ -/* EVSYS_DIGFILT2_bm Predefined. */ -/* EVSYS_DIGFILT2_bp Predefined. */ - - -/* EVSYS.CH3CTRL bit masks and bit positions */ -/* EVSYS_DIGFILT_gm Predefined. */ -/* EVSYS_DIGFILT_gp Predefined. */ -/* EVSYS_DIGFILT0_bm Predefined. */ -/* EVSYS_DIGFILT0_bp Predefined. */ -/* EVSYS_DIGFILT1_bm Predefined. */ -/* EVSYS_DIGFILT1_bp Predefined. */ -/* EVSYS_DIGFILT2_bm Predefined. */ -/* EVSYS_DIGFILT2_bp Predefined. */ - - -/* NVM - Non Volatile Memory Controller */ -/* NVM.CMD bit masks and bit positions */ -#define NVM_CMD_gm 0xFF /* Command group mask. */ -#define NVM_CMD_gp 0 /* Command group position. */ -#define NVM_CMD0_bm (1<<0) /* Command bit 0 mask. */ -#define NVM_CMD0_bp 0 /* Command bit 0 position. */ -#define NVM_CMD1_bm (1<<1) /* Command bit 1 mask. */ -#define NVM_CMD1_bp 1 /* Command bit 1 position. */ -#define NVM_CMD2_bm (1<<2) /* Command bit 2 mask. */ -#define NVM_CMD2_bp 2 /* Command bit 2 position. */ -#define NVM_CMD3_bm (1<<3) /* Command bit 3 mask. */ -#define NVM_CMD3_bp 3 /* Command bit 3 position. */ -#define NVM_CMD4_bm (1<<4) /* Command bit 4 mask. */ -#define NVM_CMD4_bp 4 /* Command bit 4 position. */ -#define NVM_CMD5_bm (1<<5) /* Command bit 5 mask. */ -#define NVM_CMD5_bp 5 /* Command bit 5 position. */ -#define NVM_CMD6_bm (1<<6) /* Command bit 6 mask. */ -#define NVM_CMD6_bp 6 /* Command bit 6 position. */ -#define NVM_CMD7_bm (1<<7) /* Command bit 7 mask. */ -#define NVM_CMD7_bp 7 /* Command bit 7 position. */ - - -/* NVM.CTRLA bit masks and bit positions */ -#define NVM_CMDEX_bm 0x01 /* Command Execute bit mask. */ -#define NVM_CMDEX_bp 0 /* Command Execute bit position. */ - - -/* NVM.CTRLB bit masks and bit positions */ -#define NVM_EEMAPEN_bm 0x08 /* EEPROM Mapping Enable bit mask. */ -#define NVM_EEMAPEN_bp 3 /* EEPROM Mapping Enable bit position. */ - -#define NVM_FPRM_bm 0x04 /* Flash Power Reduction Enable bit mask. */ -#define NVM_FPRM_bp 2 /* Flash Power Reduction Enable bit position. */ - -#define NVM_EPRM_bm 0x02 /* EEPROM Power Reduction Enable bit mask. */ -#define NVM_EPRM_bp 1 /* EEPROM Power Reduction Enable bit position. */ - -#define NVM_SPMLOCK_bm 0x01 /* SPM Lock bit mask. */ -#define NVM_SPMLOCK_bp 0 /* SPM Lock bit position. */ - - -/* NVM.INTCTRL bit masks and bit positions */ -#define NVM_SPMLVL_gm 0x0C /* SPM Interrupt Level group mask. */ -#define NVM_SPMLVL_gp 2 /* SPM Interrupt Level group position. */ -#define NVM_SPMLVL0_bm (1<<2) /* SPM Interrupt Level bit 0 mask. */ -#define NVM_SPMLVL0_bp 2 /* SPM Interrupt Level bit 0 position. */ -#define NVM_SPMLVL1_bm (1<<3) /* SPM Interrupt Level bit 1 mask. */ -#define NVM_SPMLVL1_bp 3 /* SPM Interrupt Level bit 1 position. */ - -#define NVM_EELVL_gm 0x03 /* EEPROM Interrupt Level group mask. */ -#define NVM_EELVL_gp 0 /* EEPROM Interrupt Level group position. */ -#define NVM_EELVL0_bm (1<<0) /* EEPROM Interrupt Level bit 0 mask. */ -#define NVM_EELVL0_bp 0 /* EEPROM Interrupt Level bit 0 position. */ -#define NVM_EELVL1_bm (1<<1) /* EEPROM Interrupt Level bit 1 mask. */ -#define NVM_EELVL1_bp 1 /* EEPROM Interrupt Level bit 1 position. */ - - -/* NVM.STATUS bit masks and bit positions */ -#define NVM_NVMBUSY_bm 0x80 /* Non-volatile Memory Busy bit mask. */ -#define NVM_NVMBUSY_bp 7 /* Non-volatile Memory Busy bit position. */ - -#define NVM_FBUSY_bm 0x40 /* Flash Memory Busy bit mask. */ -#define NVM_FBUSY_bp 6 /* Flash Memory Busy bit position. */ - -#define NVM_EELOAD_bm 0x02 /* EEPROM Page Buffer Active Loading bit mask. */ -#define NVM_EELOAD_bp 1 /* EEPROM Page Buffer Active Loading bit position. */ - -#define NVM_FLOAD_bm 0x01 /* Flash Page Buffer Active Loading bit mask. */ -#define NVM_FLOAD_bp 0 /* Flash Page Buffer Active Loading bit position. */ - - -/* NVM.LOCKBITS bit masks and bit positions */ -#define NVM_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ -#define NVM_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ -#define NVM_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ -#define NVM_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ -#define NVM_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ -#define NVM_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ - -#define NVM_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ -#define NVM_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ -#define NVM_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ -#define NVM_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ -#define NVM_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ -#define NVM_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ - -#define NVM_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ -#define NVM_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ -#define NVM_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ -#define NVM_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ -#define NVM_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ -#define NVM_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ - -#define NVM_LB_gm 0x03 /* Lock Bits group mask. */ -#define NVM_LB_gp 0 /* Lock Bits group position. */ -#define NVM_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ -#define NVM_LB0_bp 0 /* Lock Bits bit 0 position. */ -#define NVM_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ -#define NVM_LB1_bp 1 /* Lock Bits bit 1 position. */ - - -/* NVM_LOCKBITS.LOCKBITS bit masks and bit positions */ -#define NVM_LOCKBITS_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ -#define NVM_LOCKBITS_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ -#define NVM_LOCKBITS_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ -#define NVM_LOCKBITS_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ -#define NVM_LOCKBITS_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ -#define NVM_LOCKBITS_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ - -#define NVM_LOCKBITS_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ -#define NVM_LOCKBITS_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ -#define NVM_LOCKBITS_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ -#define NVM_LOCKBITS_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ -#define NVM_LOCKBITS_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ -#define NVM_LOCKBITS_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ - -#define NVM_LOCKBITS_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ -#define NVM_LOCKBITS_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ -#define NVM_LOCKBITS_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ -#define NVM_LOCKBITS_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ -#define NVM_LOCKBITS_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ -#define NVM_LOCKBITS_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ - -#define NVM_LOCKBITS_LB_gm 0x03 /* Lock Bits group mask. */ -#define NVM_LOCKBITS_LB_gp 0 /* Lock Bits group position. */ -#define NVM_LOCKBITS_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ -#define NVM_LOCKBITS_LB0_bp 0 /* Lock Bits bit 0 position. */ -#define NVM_LOCKBITS_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ -#define NVM_LOCKBITS_LB1_bp 1 /* Lock Bits bit 1 position. */ - - -/* NVM_FUSES.FUSEBYTE0 bit masks and bit positions */ -#define NVM_FUSES_USERID_gm 0xFF /* User ID group mask. */ -#define NVM_FUSES_USERID_gp 0 /* User ID group position. */ -#define NVM_FUSES_USERID0_bm (1<<0) /* User ID bit 0 mask. */ -#define NVM_FUSES_USERID0_bp 0 /* User ID bit 0 position. */ -#define NVM_FUSES_USERID1_bm (1<<1) /* User ID bit 1 mask. */ -#define NVM_FUSES_USERID1_bp 1 /* User ID bit 1 position. */ -#define NVM_FUSES_USERID2_bm (1<<2) /* User ID bit 2 mask. */ -#define NVM_FUSES_USERID2_bp 2 /* User ID bit 2 position. */ -#define NVM_FUSES_USERID3_bm (1<<3) /* User ID bit 3 mask. */ -#define NVM_FUSES_USERID3_bp 3 /* User ID bit 3 position. */ -#define NVM_FUSES_USERID4_bm (1<<4) /* User ID bit 4 mask. */ -#define NVM_FUSES_USERID4_bp 4 /* User ID bit 4 position. */ -#define NVM_FUSES_USERID5_bm (1<<5) /* User ID bit 5 mask. */ -#define NVM_FUSES_USERID5_bp 5 /* User ID bit 5 position. */ -#define NVM_FUSES_USERID6_bm (1<<6) /* User ID bit 6 mask. */ -#define NVM_FUSES_USERID6_bp 6 /* User ID bit 6 position. */ -#define NVM_FUSES_USERID7_bm (1<<7) /* User ID bit 7 mask. */ -#define NVM_FUSES_USERID7_bp 7 /* User ID bit 7 position. */ - - -/* NVM_FUSES.FUSEBYTE1 bit masks and bit positions */ -#define NVM_FUSES_WDWP_gm 0xF0 /* Watchdog Window Timeout Period group mask. */ -#define NVM_FUSES_WDWP_gp 4 /* Watchdog Window Timeout Period group position. */ -#define NVM_FUSES_WDWP0_bm (1<<4) /* Watchdog Window Timeout Period bit 0 mask. */ -#define NVM_FUSES_WDWP0_bp 4 /* Watchdog Window Timeout Period bit 0 position. */ -#define NVM_FUSES_WDWP1_bm (1<<5) /* Watchdog Window Timeout Period bit 1 mask. */ -#define NVM_FUSES_WDWP1_bp 5 /* Watchdog Window Timeout Period bit 1 position. */ -#define NVM_FUSES_WDWP2_bm (1<<6) /* Watchdog Window Timeout Period bit 2 mask. */ -#define NVM_FUSES_WDWP2_bp 6 /* Watchdog Window Timeout Period bit 2 position. */ -#define NVM_FUSES_WDWP3_bm (1<<7) /* Watchdog Window Timeout Period bit 3 mask. */ -#define NVM_FUSES_WDWP3_bp 7 /* Watchdog Window Timeout Period bit 3 position. */ - -#define NVM_FUSES_WDP_gm 0x0F /* Watchdog Timeout Period group mask. */ -#define NVM_FUSES_WDP_gp 0 /* Watchdog Timeout Period group position. */ -#define NVM_FUSES_WDP0_bm (1<<0) /* Watchdog Timeout Period bit 0 mask. */ -#define NVM_FUSES_WDP0_bp 0 /* Watchdog Timeout Period bit 0 position. */ -#define NVM_FUSES_WDP1_bm (1<<1) /* Watchdog Timeout Period bit 1 mask. */ -#define NVM_FUSES_WDP1_bp 1 /* Watchdog Timeout Period bit 1 position. */ -#define NVM_FUSES_WDP2_bm (1<<2) /* Watchdog Timeout Period bit 2 mask. */ -#define NVM_FUSES_WDP2_bp 2 /* Watchdog Timeout Period bit 2 position. */ -#define NVM_FUSES_WDP3_bm (1<<3) /* Watchdog Timeout Period bit 3 mask. */ -#define NVM_FUSES_WDP3_bp 3 /* Watchdog Timeout Period bit 3 position. */ - - -/* NVM_FUSES.FUSEBYTE2 bit masks and bit positions */ -#define NVM_FUSES_DVSDON_bm 0x80 /* Spike Detector Enable bit mask. */ -#define NVM_FUSES_DVSDON_bp 7 /* Spike Detector Enable bit position. */ - -#define NVM_FUSES_BOOTRST_bm 0x40 /* Boot Loader Section Reset Vector bit mask. */ -#define NVM_FUSES_BOOTRST_bp 6 /* Boot Loader Section Reset Vector bit position. */ - -#define NVM_FUSES_BODPD_gm 0x03 /* BOD Operation in Power-Down Mode group mask. */ -#define NVM_FUSES_BODPD_gp 0 /* BOD Operation in Power-Down Mode group position. */ -#define NVM_FUSES_BODPD0_bm (1<<0) /* BOD Operation in Power-Down Mode bit 0 mask. */ -#define NVM_FUSES_BODPD0_bp 0 /* BOD Operation in Power-Down Mode bit 0 position. */ -#define NVM_FUSES_BODPD1_bm (1<<1) /* BOD Operation in Power-Down Mode bit 1 mask. */ -#define NVM_FUSES_BODPD1_bp 1 /* BOD Operation in Power-Down Mode bit 1 position. */ - - -/* NVM_FUSES.FUSEBYTE4 bit masks and bit positions */ -#define NVM_FUSES_SUT_gm 0x0C /* Start-up Time group mask. */ -#define NVM_FUSES_SUT_gp 2 /* Start-up Time group position. */ -#define NVM_FUSES_SUT0_bm (1<<2) /* Start-up Time bit 0 mask. */ -#define NVM_FUSES_SUT0_bp 2 /* Start-up Time bit 0 position. */ -#define NVM_FUSES_SUT1_bm (1<<3) /* Start-up Time bit 1 mask. */ -#define NVM_FUSES_SUT1_bp 3 /* Start-up Time bit 1 position. */ - -#define NVM_FUSES_WDLOCK_bm 0x02 /* Watchdog Timer Lock bit mask. */ -#define NVM_FUSES_WDLOCK_bp 1 /* Watchdog Timer Lock bit position. */ - - -/* NVM_FUSES.FUSEBYTE5 bit masks and bit positions */ -#define NVM_FUSES_BODACT_gm 0x30 /* BOD Operation in Active Mode group mask. */ -#define NVM_FUSES_BODACT_gp 4 /* BOD Operation in Active Mode group position. */ -#define NVM_FUSES_BODACT0_bm (1<<4) /* BOD Operation in Active Mode bit 0 mask. */ -#define NVM_FUSES_BODACT0_bp 4 /* BOD Operation in Active Mode bit 0 position. */ -#define NVM_FUSES_BODACT1_bm (1<<5) /* BOD Operation in Active Mode bit 1 mask. */ -#define NVM_FUSES_BODACT1_bp 5 /* BOD Operation in Active Mode bit 1 position. */ - -#define NVM_FUSES_EESAVE_bm 0x08 /* Preserve EEPROM Through Chip Erase bit mask. */ -#define NVM_FUSES_EESAVE_bp 3 /* Preserve EEPROM Through Chip Erase bit position. */ - -#define NVM_FUSES_BODLVL_gm 0x07 /* Brown Out Detection Voltage Level group mask. */ -#define NVM_FUSES_BODLVL_gp 0 /* Brown Out Detection Voltage Level group position. */ -#define NVM_FUSES_BODLVL0_bm (1<<0) /* Brown Out Detection Voltage Level bit 0 mask. */ -#define NVM_FUSES_BODLVL0_bp 0 /* Brown Out Detection Voltage Level bit 0 position. */ -#define NVM_FUSES_BODLVL1_bm (1<<1) /* Brown Out Detection Voltage Level bit 1 mask. */ -#define NVM_FUSES_BODLVL1_bp 1 /* Brown Out Detection Voltage Level bit 1 position. */ -#define NVM_FUSES_BODLVL2_bm (1<<2) /* Brown Out Detection Voltage Level bit 2 mask. */ -#define NVM_FUSES_BODLVL2_bp 2 /* Brown Out Detection Voltage Level bit 2 position. */ - - -/* AC - Analog Comparator */ -/* AC.AC0CTRL bit masks and bit positions */ -#define AC_INTMODE_gm 0xC0 /* Interrupt Mode group mask. */ -#define AC_INTMODE_gp 6 /* Interrupt Mode group position. */ -#define AC_INTMODE0_bm (1<<6) /* Interrupt Mode bit 0 mask. */ -#define AC_INTMODE0_bp 6 /* Interrupt Mode bit 0 position. */ -#define AC_INTMODE1_bm (1<<7) /* Interrupt Mode bit 1 mask. */ -#define AC_INTMODE1_bp 7 /* Interrupt Mode bit 1 position. */ - -#define AC_INTLVL_gm 0x30 /* Interrupt Level group mask. */ -#define AC_INTLVL_gp 4 /* Interrupt Level group position. */ -#define AC_INTLVL0_bm (1<<4) /* Interrupt Level bit 0 mask. */ -#define AC_INTLVL0_bp 4 /* Interrupt Level bit 0 position. */ -#define AC_INTLVL1_bm (1<<5) /* Interrupt Level bit 1 mask. */ -#define AC_INTLVL1_bp 5 /* Interrupt Level bit 1 position. */ - -#define AC_HSMODE_bm 0x08 /* High-speed Mode bit mask. */ -#define AC_HSMODE_bp 3 /* High-speed Mode bit position. */ - -#define AC_HYSMODE_gm 0x06 /* Hysteresis Mode group mask. */ -#define AC_HYSMODE_gp 1 /* Hysteresis Mode group position. */ -#define AC_HYSMODE0_bm (1<<1) /* Hysteresis Mode bit 0 mask. */ -#define AC_HYSMODE0_bp 1 /* Hysteresis Mode bit 0 position. */ -#define AC_HYSMODE1_bm (1<<2) /* Hysteresis Mode bit 1 mask. */ -#define AC_HYSMODE1_bp 2 /* Hysteresis Mode bit 1 position. */ - -#define AC_ENABLE_bm 0x01 /* Enable bit mask. */ -#define AC_ENABLE_bp 0 /* Enable bit position. */ - - -/* AC.AC1CTRL bit masks and bit positions */ -/* AC_INTMODE_gm Predefined. */ -/* AC_INTMODE_gp Predefined. */ -/* AC_INTMODE0_bm Predefined. */ -/* AC_INTMODE0_bp Predefined. */ -/* AC_INTMODE1_bm Predefined. */ -/* AC_INTMODE1_bp Predefined. */ - -/* AC_INTLVL_gm Predefined. */ -/* AC_INTLVL_gp Predefined. */ -/* AC_INTLVL0_bm Predefined. */ -/* AC_INTLVL0_bp Predefined. */ -/* AC_INTLVL1_bm Predefined. */ -/* AC_INTLVL1_bp Predefined. */ - -/* AC_HSMODE_bm Predefined. */ -/* AC_HSMODE_bp Predefined. */ - -/* AC_HYSMODE_gm Predefined. */ -/* AC_HYSMODE_gp Predefined. */ -/* AC_HYSMODE0_bm Predefined. */ -/* AC_HYSMODE0_bp Predefined. */ -/* AC_HYSMODE1_bm Predefined. */ -/* AC_HYSMODE1_bp Predefined. */ - -/* AC_ENABLE_bm Predefined. */ -/* AC_ENABLE_bp Predefined. */ - - -/* AC.AC0MUXCTRL bit masks and bit positions */ -#define AC_MUXPOS_gm 0x38 /* MUX Positive Input group mask. */ -#define AC_MUXPOS_gp 3 /* MUX Positive Input group position. */ -#define AC_MUXPOS0_bm (1<<3) /* MUX Positive Input bit 0 mask. */ -#define AC_MUXPOS0_bp 3 /* MUX Positive Input bit 0 position. */ -#define AC_MUXPOS1_bm (1<<4) /* MUX Positive Input bit 1 mask. */ -#define AC_MUXPOS1_bp 4 /* MUX Positive Input bit 1 position. */ -#define AC_MUXPOS2_bm (1<<5) /* MUX Positive Input bit 2 mask. */ -#define AC_MUXPOS2_bp 5 /* MUX Positive Input bit 2 position. */ - -#define AC_MUXNEG_gm 0x07 /* MUX Negative Input group mask. */ -#define AC_MUXNEG_gp 0 /* MUX Negative Input group position. */ -#define AC_MUXNEG0_bm (1<<0) /* MUX Negative Input bit 0 mask. */ -#define AC_MUXNEG0_bp 0 /* MUX Negative Input bit 0 position. */ -#define AC_MUXNEG1_bm (1<<1) /* MUX Negative Input bit 1 mask. */ -#define AC_MUXNEG1_bp 1 /* MUX Negative Input bit 1 position. */ -#define AC_MUXNEG2_bm (1<<2) /* MUX Negative Input bit 2 mask. */ -#define AC_MUXNEG2_bp 2 /* MUX Negative Input bit 2 position. */ - - -/* AC.AC1MUXCTRL bit masks and bit positions */ -/* AC_MUXPOS_gm Predefined. */ -/* AC_MUXPOS_gp Predefined. */ -/* AC_MUXPOS0_bm Predefined. */ -/* AC_MUXPOS0_bp Predefined. */ -/* AC_MUXPOS1_bm Predefined. */ -/* AC_MUXPOS1_bp Predefined. */ -/* AC_MUXPOS2_bm Predefined. */ -/* AC_MUXPOS2_bp Predefined. */ - -/* AC_MUXNEG_gm Predefined. */ -/* AC_MUXNEG_gp Predefined. */ -/* AC_MUXNEG0_bm Predefined. */ -/* AC_MUXNEG0_bp Predefined. */ -/* AC_MUXNEG1_bm Predefined. */ -/* AC_MUXNEG1_bp Predefined. */ -/* AC_MUXNEG2_bm Predefined. */ -/* AC_MUXNEG2_bp Predefined. */ - - -/* AC.CTRLA bit masks and bit positions */ -#define AC_AC0OUT_bm 0x01 /* Comparator 0 Output Enable bit mask. */ -#define AC_AC0OUT_bp 0 /* Comparator 0 Output Enable bit position. */ - - -/* AC.CTRLB bit masks and bit positions */ -#define AC_SCALEFAC_gm 0x3F /* VCC Voltage Scaler Factor group mask. */ -#define AC_SCALEFAC_gp 0 /* VCC Voltage Scaler Factor group position. */ -#define AC_SCALEFAC0_bm (1<<0) /* VCC Voltage Scaler Factor bit 0 mask. */ -#define AC_SCALEFAC0_bp 0 /* VCC Voltage Scaler Factor bit 0 position. */ -#define AC_SCALEFAC1_bm (1<<1) /* VCC Voltage Scaler Factor bit 1 mask. */ -#define AC_SCALEFAC1_bp 1 /* VCC Voltage Scaler Factor bit 1 position. */ -#define AC_SCALEFAC2_bm (1<<2) /* VCC Voltage Scaler Factor bit 2 mask. */ -#define AC_SCALEFAC2_bp 2 /* VCC Voltage Scaler Factor bit 2 position. */ -#define AC_SCALEFAC3_bm (1<<3) /* VCC Voltage Scaler Factor bit 3 mask. */ -#define AC_SCALEFAC3_bp 3 /* VCC Voltage Scaler Factor bit 3 position. */ -#define AC_SCALEFAC4_bm (1<<4) /* VCC Voltage Scaler Factor bit 4 mask. */ -#define AC_SCALEFAC4_bp 4 /* VCC Voltage Scaler Factor bit 4 position. */ -#define AC_SCALEFAC5_bm (1<<5) /* VCC Voltage Scaler Factor bit 5 mask. */ -#define AC_SCALEFAC5_bp 5 /* VCC Voltage Scaler Factor bit 5 position. */ - - -/* AC.WINCTRL bit masks and bit positions */ -#define AC_WEN_bm 0x10 /* Window Mode Enable bit mask. */ -#define AC_WEN_bp 4 /* Window Mode Enable bit position. */ - -#define AC_WINTMODE_gm 0x0C /* Window Interrupt Mode group mask. */ -#define AC_WINTMODE_gp 2 /* Window Interrupt Mode group position. */ -#define AC_WINTMODE0_bm (1<<2) /* Window Interrupt Mode bit 0 mask. */ -#define AC_WINTMODE0_bp 2 /* Window Interrupt Mode bit 0 position. */ -#define AC_WINTMODE1_bm (1<<3) /* Window Interrupt Mode bit 1 mask. */ -#define AC_WINTMODE1_bp 3 /* Window Interrupt Mode bit 1 position. */ - -#define AC_WINTLVL_gm 0x03 /* Window Interrupt Level group mask. */ -#define AC_WINTLVL_gp 0 /* Window Interrupt Level group position. */ -#define AC_WINTLVL0_bm (1<<0) /* Window Interrupt Level bit 0 mask. */ -#define AC_WINTLVL0_bp 0 /* Window Interrupt Level bit 0 position. */ -#define AC_WINTLVL1_bm (1<<1) /* Window Interrupt Level bit 1 mask. */ -#define AC_WINTLVL1_bp 1 /* Window Interrupt Level bit 1 position. */ - - -/* AC.STATUS bit masks and bit positions */ -#define AC_WSTATE_gm 0xC0 /* Window Mode State group mask. */ -#define AC_WSTATE_gp 6 /* Window Mode State group position. */ -#define AC_WSTATE0_bm (1<<6) /* Window Mode State bit 0 mask. */ -#define AC_WSTATE0_bp 6 /* Window Mode State bit 0 position. */ -#define AC_WSTATE1_bm (1<<7) /* Window Mode State bit 1 mask. */ -#define AC_WSTATE1_bp 7 /* Window Mode State bit 1 position. */ - -#define AC_AC1STATE_bm 0x20 /* Comparator 1 State bit mask. */ -#define AC_AC1STATE_bp 5 /* Comparator 1 State bit position. */ - -#define AC_AC0STATE_bm 0x10 /* Comparator 0 State bit mask. */ -#define AC_AC0STATE_bp 4 /* Comparator 0 State bit position. */ - -#define AC_WIF_bm 0x04 /* Window Mode Interrupt Flag bit mask. */ -#define AC_WIF_bp 2 /* Window Mode Interrupt Flag bit position. */ - -#define AC_AC1IF_bm 0x02 /* Comparator 1 Interrupt Flag bit mask. */ -#define AC_AC1IF_bp 1 /* Comparator 1 Interrupt Flag bit position. */ - -#define AC_AC0IF_bm 0x01 /* Comparator 0 Interrupt Flag bit mask. */ -#define AC_AC0IF_bp 0 /* Comparator 0 Interrupt Flag bit position. */ - - -/* ADC - Analog/Digital Converter */ -/* ADC_CH.CTRL bit masks and bit positions */ -#define ADC_CH_START_bm 0x80 /* Channel Start Conversion bit mask. */ -#define ADC_CH_START_bp 7 /* Channel Start Conversion bit position. */ - -#define ADC_CH_GAINFAC_gm 0x1C /* Gain Factor group mask. */ -#define ADC_CH_GAINFAC_gp 2 /* Gain Factor group position. */ -#define ADC_CH_GAINFAC0_bm (1<<2) /* Gain Factor bit 0 mask. */ -#define ADC_CH_GAINFAC0_bp 2 /* Gain Factor bit 0 position. */ -#define ADC_CH_GAINFAC1_bm (1<<3) /* Gain Factor bit 1 mask. */ -#define ADC_CH_GAINFAC1_bp 3 /* Gain Factor bit 1 position. */ -#define ADC_CH_GAINFAC2_bm (1<<4) /* Gain Factor bit 2 mask. */ -#define ADC_CH_GAINFAC2_bp 4 /* Gain Factor bit 2 position. */ - -#define ADC_CH_INPUTMODE_gm 0x03 /* Input Mode Select group mask. */ -#define ADC_CH_INPUTMODE_gp 0 /* Input Mode Select group position. */ -#define ADC_CH_INPUTMODE0_bm (1<<0) /* Input Mode Select bit 0 mask. */ -#define ADC_CH_INPUTMODE0_bp 0 /* Input Mode Select bit 0 position. */ -#define ADC_CH_INPUTMODE1_bm (1<<1) /* Input Mode Select bit 1 mask. */ -#define ADC_CH_INPUTMODE1_bp 1 /* Input Mode Select bit 1 position. */ - - -/* ADC_CH.MUXCTRL bit masks and bit positions */ -#define ADC_CH_MUXPOS_gm 0x78 /* Positive Input Select group mask. */ -#define ADC_CH_MUXPOS_gp 3 /* Positive Input Select group position. */ -#define ADC_CH_MUXPOS0_bm (1<<3) /* Positive Input Select bit 0 mask. */ -#define ADC_CH_MUXPOS0_bp 3 /* Positive Input Select bit 0 position. */ -#define ADC_CH_MUXPOS1_bm (1<<4) /* Positive Input Select bit 1 mask. */ -#define ADC_CH_MUXPOS1_bp 4 /* Positive Input Select bit 1 position. */ -#define ADC_CH_MUXPOS2_bm (1<<5) /* Positive Input Select bit 2 mask. */ -#define ADC_CH_MUXPOS2_bp 5 /* Positive Input Select bit 2 position. */ -#define ADC_CH_MUXPOS3_bm (1<<6) /* Positive Input Select bit 3 mask. */ -#define ADC_CH_MUXPOS3_bp 6 /* Positive Input Select bit 3 position. */ -#define ADC_CH_MUXPOS4_bm (1<<7) /* Positive Input Select bit 3 mask. */ -#define ADC_CH_MUXPOS4_bp 7 /* Positive Input Select bit 3 position. */ - -#define ADC_CH_MUXINT_gm 0x78 /* Internal Input Select group mask. */ -#define ADC_CH_MUXINT_gp 3 /* Internal Input Select group position. */ -#define ADC_CH_MUXINT0_bm (1<<3) /* Internal Input Select bit 0 mask. */ -#define ADC_CH_MUXINT0_bp 3 /* Internal Input Select bit 0 position. */ -#define ADC_CH_MUXINT1_bm (1<<4) /* Internal Input Select bit 1 mask. */ -#define ADC_CH_MUXINT1_bp 4 /* Internal Input Select bit 1 position. */ -#define ADC_CH_MUXINT2_bm (1<<5) /* Internal Input Select bit 2 mask. */ -#define ADC_CH_MUXINT2_bp 5 /* Internal Input Select bit 2 position. */ -#define ADC_CH_MUXINT3_bm (1<<6) /* Internal Input Select bit 3 mask. */ -#define ADC_CH_MUXINT3_bp 6 /* Internal Input Select bit 3 position. */ - -#define ADC_CH_MUXNEG_gm 0x03 /* Negative Input Select group mask. */ -#define ADC_CH_MUXNEG_gp 0 /* Negative Input Select group position. */ -#define ADC_CH_MUXNEG0_bm (1<<0) /* Negative Input Select bit 0 mask. */ -#define ADC_CH_MUXNEG0_bp 0 /* Negative Input Select bit 0 position. */ -#define ADC_CH_MUXNEG1_bm (1<<1) /* Negative Input Select bit 1 mask. */ -#define ADC_CH_MUXNEG1_bp 1 /* Negative Input Select bit 1 position. */ - - -/* ADC_CH.INTCTRL bit masks and bit positions */ -#define ADC_CH_INTMODE_gm 0x0C /* Interrupt Mode group mask. */ -#define ADC_CH_INTMODE_gp 2 /* Interrupt Mode group position. */ -#define ADC_CH_INTMODE0_bm (1<<2) /* Interrupt Mode bit 0 mask. */ -#define ADC_CH_INTMODE0_bp 2 /* Interrupt Mode bit 0 position. */ -#define ADC_CH_INTMODE1_bm (1<<3) /* Interrupt Mode bit 1 mask. */ -#define ADC_CH_INTMODE1_bp 3 /* Interrupt Mode bit 1 position. */ - -#define ADC_CH_INTLVL_gm 0x03 /* Interrupt Level group mask. */ -#define ADC_CH_INTLVL_gp 0 /* Interrupt Level group position. */ -#define ADC_CH_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */ -#define ADC_CH_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */ -#define ADC_CH_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ -#define ADC_CH_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */ - - -/* ADC_CH.INTFLAGS bit masks and bit positions */ -#define ADC_CH_CHIF_bm 0x01 /* Channel Interrupt Flag bit mask. */ -#define ADC_CH_CHIF_bp 0 /* Channel Interrupt Flag bit position. */ - - -/* ADC.CTRLA bit masks and bit positions */ -#define ADC_CH0START_bm 0x04 /* Channel 0 Start Conversion bit mask. */ -#define ADC_CH0START_bp 2 /* Channel 0 Start Conversion bit position. */ - -#define ADC_FLUSH_bm 0x02 /* ADC Flush bit mask. */ -#define ADC_FLUSH_bp 1 /* ADC Flush bit position. */ - -#define ADC_ENABLE_bm 0x01 /* Enable ADC bit mask. */ -#define ADC_ENABLE_bp 0 /* Enable ADC bit position. */ - - -/* ADC.CTRLB bit masks and bit positions */ -#define ADC_IMPMODE_bm 0x80 /* Impedance Mode bit mask. */ -#define ADC_IMPMODE_bp 7 /* Impedance Mode bit position. */ - -#define ADC_CURRENT_bm 0x60 /* Current bit mask. */ -#define ADC_CURRENT1_bp 6 /* Current bit position. */ -#define ADC_CURRENT0_bp 5 /* Current bit position. */ - -#define ADC_CONMODE_bm 0x10 /* Conversion Mode bit mask. */ -#define ADC_CONMODE_bp 4 /* Conversion Mode bit position. */ - -#define ADC_FREERUN_bm 0x08 /* Free Running Mode Enable bit mask. */ -#define ADC_FREERUN_bp 3 /* Free Running Mode Enable bit position. */ - -#define ADC_RESOLUTION_gm 0x06 /* Result Resolution group mask. */ -#define ADC_RESOLUTION_gp 1 /* Result Resolution group position. */ -#define ADC_RESOLUTION0_bm (1<<1) /* Result Resolution bit 0 mask. */ -#define ADC_RESOLUTION0_bp 1 /* Result Resolution bit 0 position. */ -#define ADC_RESOLUTION1_bm (1<<2) /* Result Resolution bit 1 mask. */ -#define ADC_RESOLUTION1_bp 2 /* Result Resolution bit 1 position. */ - - -/* ADC.REFCTRL bit masks and bit positions */ -#define ADC_REFSEL_gm 0x70 /* Reference Selection group mask. */ -#define ADC_REFSEL_gp 4 /* Reference Selection group position. */ -#define ADC_REFSEL0_bm (1<<4) /* Reference Selection bit 0 mask. */ -#define ADC_REFSEL0_bp 4 /* Reference Selection bit 0 position. */ -#define ADC_REFSEL1_bm (1<<5) /* Reference Selection bit 1 mask. */ -#define ADC_REFSEL1_bp 5 /* Reference Selection bit 1 position. */ -#define ADC_REFSEL2_bm (1<<6) /* Reference Selection bit 2 mask. */ -#define ADC_REFSEL2_bp 6 /* Reference Selection bit 2 position. */ - -#define ADC_BANDGAP_bm 0x02 /* Bandgap enable bit mask. */ -#define ADC_BANDGAP_bp 1 /* Bandgap enable bit position. */ - -#define ADC_TEMPREF_bm 0x01 /* Temperature Reference Enable bit mask. */ -#define ADC_TEMPREF_bp 0 /* Temperature Reference Enable bit position. */ - - -/* ADC.EVCTRL bit masks and bit positions */ -#define ADC_SWEEP_gm 0xC0 /* Channel Sweep Selection group mask. */ -#define ADC_SWEEP_gp 6 /* Channel Sweep Selection group position. */ -#define ADC_SWEEP0_bm (1<<6) /* Channel Sweep Selection bit 0 mask. */ -#define ADC_SWEEP0_bp 6 /* Channel Sweep Selection bit 0 position. */ -#define ADC_SWEEP1_bm (1<<7) /* Channel Sweep Selection bit 1 mask. */ -#define ADC_SWEEP1_bp 7 /* Channel Sweep Selection bit 1 position. */ - -#define ADC_EVSEL_gm 0x38 /* Event Input Select group mask. */ -#define ADC_EVSEL_gp 3 /* Event Input Select group position. */ -#define ADC_EVSEL0_bm (1<<3) /* Event Input Select bit 0 mask. */ -#define ADC_EVSEL0_bp 3 /* Event Input Select bit 0 position. */ -#define ADC_EVSEL1_bm (1<<4) /* Event Input Select bit 1 mask. */ -#define ADC_EVSEL1_bp 4 /* Event Input Select bit 1 position. */ -#define ADC_EVSEL2_bm (1<<5) /* Event Input Select bit 2 mask. */ -#define ADC_EVSEL2_bp 5 /* Event Input Select bit 2 position. */ - -#define ADC_EVACT_gm 0x07 /* Event Action Select group mask. */ -#define ADC_EVACT_gp 0 /* Event Action Select group position. */ -#define ADC_EVACT0_bm (1<<0) /* Event Action Select bit 0 mask. */ -#define ADC_EVACT0_bp 0 /* Event Action Select bit 0 position. */ -#define ADC_EVACT1_bm (1<<1) /* Event Action Select bit 1 mask. */ -#define ADC_EVACT1_bp 1 /* Event Action Select bit 1 position. */ -#define ADC_EVACT2_bm (1<<2) /* Event Action Select bit 2 mask. */ -#define ADC_EVACT2_bp 2 /* Event Action Select bit 2 position. */ - - -/* ADC.PRESCALER bit masks and bit positions */ -#define ADC_PRESCALER_gm 0x07 /* Clock Prescaler Selection group mask. */ -#define ADC_PRESCALER_gp 0 /* Clock Prescaler Selection group position. */ -#define ADC_PRESCALER0_bm (1<<0) /* Clock Prescaler Selection bit 0 mask. */ -#define ADC_PRESCALER0_bp 0 /* Clock Prescaler Selection bit 0 position. */ -#define ADC_PRESCALER1_bm (1<<1) /* Clock Prescaler Selection bit 1 mask. */ -#define ADC_PRESCALER1_bp 1 /* Clock Prescaler Selection bit 1 position. */ -#define ADC_PRESCALER2_bm (1<<2) /* Clock Prescaler Selection bit 2 mask. */ -#define ADC_PRESCALER2_bp 2 /* Clock Prescaler Selection bit 2 position. */ - - -/* ADC.INTFLAGS bit masks and bit positions */ -#define ADC_CH0IF_bm 0x01 /* Channel 0 Interrupt Flag bit mask. */ -#define ADC_CH0IF_bp 0 /* Channel 0 Interrupt Flag bit position. */ - - -/* RTC - Real-Time Clounter */ -/* RTC.CTRL bit masks and bit positions */ -#define RTC_PRESCALER_gm 0x07 /* Prescaling Factor group mask. */ -#define RTC_PRESCALER_gp 0 /* Prescaling Factor group position. */ -#define RTC_PRESCALER0_bm (1<<0) /* Prescaling Factor bit 0 mask. */ -#define RTC_PRESCALER0_bp 0 /* Prescaling Factor bit 0 position. */ -#define RTC_PRESCALER1_bm (1<<1) /* Prescaling Factor bit 1 mask. */ -#define RTC_PRESCALER1_bp 1 /* Prescaling Factor bit 1 position. */ -#define RTC_PRESCALER2_bm (1<<2) /* Prescaling Factor bit 2 mask. */ -#define RTC_PRESCALER2_bp 2 /* Prescaling Factor bit 2 position. */ - - -/* RTC.STATUS bit masks and bit positions */ -#define RTC_SYNCBUSY_bm 0x01 /* Synchronization Busy Flag bit mask. */ -#define RTC_SYNCBUSY_bp 0 /* Synchronization Busy Flag bit position. */ - - -/* RTC.INTCTRL bit masks and bit positions */ -#define RTC_COMPINTLVL_gm 0x0C /* Compare Match Interrupt Level group mask. */ -#define RTC_COMPINTLVL_gp 2 /* Compare Match Interrupt Level group position. */ -#define RTC_COMPINTLVL0_bm (1<<2) /* Compare Match Interrupt Level bit 0 mask. */ -#define RTC_COMPINTLVL0_bp 2 /* Compare Match Interrupt Level bit 0 position. */ -#define RTC_COMPINTLVL1_bm (1<<3) /* Compare Match Interrupt Level bit 1 mask. */ -#define RTC_COMPINTLVL1_bp 3 /* Compare Match Interrupt Level bit 1 position. */ - -#define RTC_OVFINTLVL_gm 0x03 /* Overflow Interrupt Level group mask. */ -#define RTC_OVFINTLVL_gp 0 /* Overflow Interrupt Level group position. */ -#define RTC_OVFINTLVL0_bm (1<<0) /* Overflow Interrupt Level bit 0 mask. */ -#define RTC_OVFINTLVL0_bp 0 /* Overflow Interrupt Level bit 0 position. */ -#define RTC_OVFINTLVL1_bm (1<<1) /* Overflow Interrupt Level bit 1 mask. */ -#define RTC_OVFINTLVL1_bp 1 /* Overflow Interrupt Level bit 1 position. */ - - -/* RTC.INTFLAGS bit masks and bit positions */ -#define RTC_COMPIF_bm 0x02 /* Compare Match Interrupt Flag bit mask. */ -#define RTC_COMPIF_bp 1 /* Compare Match Interrupt Flag bit position. */ - -#define RTC_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ -#define RTC_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ - - -/* EBI - External Bus Interface */ -/* EBI_CS.CTRLA bit masks and bit positions */ -#define EBI_CS_ASIZE_gm 0x7C /* Address Size group mask. */ -#define EBI_CS_ASIZE_gp 2 /* Address Size group position. */ -#define EBI_CS_ASIZE0_bm (1<<2) /* Address Size bit 0 mask. */ -#define EBI_CS_ASIZE0_bp 2 /* Address Size bit 0 position. */ -#define EBI_CS_ASIZE1_bm (1<<3) /* Address Size bit 1 mask. */ -#define EBI_CS_ASIZE1_bp 3 /* Address Size bit 1 position. */ -#define EBI_CS_ASIZE2_bm (1<<4) /* Address Size bit 2 mask. */ -#define EBI_CS_ASIZE2_bp 4 /* Address Size bit 2 position. */ -#define EBI_CS_ASIZE3_bm (1<<5) /* Address Size bit 3 mask. */ -#define EBI_CS_ASIZE3_bp 5 /* Address Size bit 3 position. */ -#define EBI_CS_ASIZE4_bm (1<<6) /* Address Size bit 4 mask. */ -#define EBI_CS_ASIZE4_bp 6 /* Address Size bit 4 position. */ - -#define EBI_CS_MODE_gm 0x03 /* Memory Mode group mask. */ -#define EBI_CS_MODE_gp 0 /* Memory Mode group position. */ -#define EBI_CS_MODE0_bm (1<<0) /* Memory Mode bit 0 mask. */ -#define EBI_CS_MODE0_bp 0 /* Memory Mode bit 0 position. */ -#define EBI_CS_MODE1_bm (1<<1) /* Memory Mode bit 1 mask. */ -#define EBI_CS_MODE1_bp 1 /* Memory Mode bit 1 position. */ - - -/* EBI_CS.CTRLB bit masks and bit positions */ -#define EBI_CS_SRWS_gm 0x07 /* SRAM Wait State Cycles group mask. */ -#define EBI_CS_SRWS_gp 0 /* SRAM Wait State Cycles group position. */ -#define EBI_CS_SRWS0_bm (1<<0) /* SRAM Wait State Cycles bit 0 mask. */ -#define EBI_CS_SRWS0_bp 0 /* SRAM Wait State Cycles bit 0 position. */ -#define EBI_CS_SRWS1_bm (1<<1) /* SRAM Wait State Cycles bit 1 mask. */ -#define EBI_CS_SRWS1_bp 1 /* SRAM Wait State Cycles bit 1 position. */ -#define EBI_CS_SRWS2_bm (1<<2) /* SRAM Wait State Cycles bit 2 mask. */ -#define EBI_CS_SRWS2_bp 2 /* SRAM Wait State Cycles bit 2 position. */ - -#define EBI_CS_SDINITDONE_bm 0x80 /* SDRAM Initialization Done bit mask. */ -#define EBI_CS_SDINITDONE_bp 7 /* SDRAM Initialization Done bit position. */ - -#define EBI_CS_SDSREN_bm 0x04 /* SDRAM Self-refresh Enable bit mask. */ -#define EBI_CS_SDSREN_bp 2 /* SDRAM Self-refresh Enable bit position. */ - -#define EBI_CS_SDMODE_gm 0x03 /* SDRAM Mode group mask. */ -#define EBI_CS_SDMODE_gp 0 /* SDRAM Mode group position. */ -#define EBI_CS_SDMODE0_bm (1<<0) /* SDRAM Mode bit 0 mask. */ -#define EBI_CS_SDMODE0_bp 0 /* SDRAM Mode bit 0 position. */ -#define EBI_CS_SDMODE1_bm (1<<1) /* SDRAM Mode bit 1 mask. */ -#define EBI_CS_SDMODE1_bp 1 /* SDRAM Mode bit 1 position. */ - - -/* EBI.CTRL bit masks and bit positions */ -#define EBI_SDDATAW_gm 0xC0 /* SDRAM Data Width Setting group mask. */ -#define EBI_SDDATAW_gp 6 /* SDRAM Data Width Setting group position. */ -#define EBI_SDDATAW0_bm (1<<6) /* SDRAM Data Width Setting bit 0 mask. */ -#define EBI_SDDATAW0_bp 6 /* SDRAM Data Width Setting bit 0 position. */ -#define EBI_SDDATAW1_bm (1<<7) /* SDRAM Data Width Setting bit 1 mask. */ -#define EBI_SDDATAW1_bp 7 /* SDRAM Data Width Setting bit 1 position. */ - -#define EBI_LPCMODE_gm 0x30 /* SRAM LPC Mode group mask. */ -#define EBI_LPCMODE_gp 4 /* SRAM LPC Mode group position. */ -#define EBI_LPCMODE0_bm (1<<4) /* SRAM LPC Mode bit 0 mask. */ -#define EBI_LPCMODE0_bp 4 /* SRAM LPC Mode bit 0 position. */ -#define EBI_LPCMODE1_bm (1<<5) /* SRAM LPC Mode bit 1 mask. */ -#define EBI_LPCMODE1_bp 5 /* SRAM LPC Mode bit 1 position. */ - -#define EBI_SRMODE_gm 0x0C /* SRAM Mode group mask. */ -#define EBI_SRMODE_gp 2 /* SRAM Mode group position. */ -#define EBI_SRMODE0_bm (1<<2) /* SRAM Mode bit 0 mask. */ -#define EBI_SRMODE0_bp 2 /* SRAM Mode bit 0 position. */ -#define EBI_SRMODE1_bm (1<<3) /* SRAM Mode bit 1 mask. */ -#define EBI_SRMODE1_bp 3 /* SRAM Mode bit 1 position. */ - -#define EBI_IFMODE_gm 0x03 /* Interface Mode group mask. */ -#define EBI_IFMODE_gp 0 /* Interface Mode group position. */ -#define EBI_IFMODE0_bm (1<<0) /* Interface Mode bit 0 mask. */ -#define EBI_IFMODE0_bp 0 /* Interface Mode bit 0 position. */ -#define EBI_IFMODE1_bm (1<<1) /* Interface Mode bit 1 mask. */ -#define EBI_IFMODE1_bp 1 /* Interface Mode bit 1 position. */ - - -/* EBI.SDRAMCTRLA bit masks and bit positions */ -#define EBI_SDCAS_bm 0x08 /* SDRAM CAS Latency Setting bit mask. */ -#define EBI_SDCAS_bp 3 /* SDRAM CAS Latency Setting bit position. */ - -#define EBI_SDROW_bm 0x04 /* SDRAM ROW Bits Setting bit mask. */ -#define EBI_SDROW_bp 2 /* SDRAM ROW Bits Setting bit position. */ - -#define EBI_SDCOL_gm 0x03 /* SDRAM Column Bits Setting group mask. */ -#define EBI_SDCOL_gp 0 /* SDRAM Column Bits Setting group position. */ -#define EBI_SDCOL0_bm (1<<0) /* SDRAM Column Bits Setting bit 0 mask. */ -#define EBI_SDCOL0_bp 0 /* SDRAM Column Bits Setting bit 0 position. */ -#define EBI_SDCOL1_bm (1<<1) /* SDRAM Column Bits Setting bit 1 mask. */ -#define EBI_SDCOL1_bp 1 /* SDRAM Column Bits Setting bit 1 position. */ - - -/* EBI.SDRAMCTRLB bit masks and bit positions */ -#define EBI_MRDLY_gm 0xC0 /* SDRAM Mode Register Delay group mask. */ -#define EBI_MRDLY_gp 6 /* SDRAM Mode Register Delay group position. */ -#define EBI_MRDLY0_bm (1<<6) /* SDRAM Mode Register Delay bit 0 mask. */ -#define EBI_MRDLY0_bp 6 /* SDRAM Mode Register Delay bit 0 position. */ -#define EBI_MRDLY1_bm (1<<7) /* SDRAM Mode Register Delay bit 1 mask. */ -#define EBI_MRDLY1_bp 7 /* SDRAM Mode Register Delay bit 1 position. */ - -#define EBI_ROWCYCDLY_gm 0x38 /* SDRAM Row Cycle Delay group mask. */ -#define EBI_ROWCYCDLY_gp 3 /* SDRAM Row Cycle Delay group position. */ -#define EBI_ROWCYCDLY0_bm (1<<3) /* SDRAM Row Cycle Delay bit 0 mask. */ -#define EBI_ROWCYCDLY0_bp 3 /* SDRAM Row Cycle Delay bit 0 position. */ -#define EBI_ROWCYCDLY1_bm (1<<4) /* SDRAM Row Cycle Delay bit 1 mask. */ -#define EBI_ROWCYCDLY1_bp 4 /* SDRAM Row Cycle Delay bit 1 position. */ -#define EBI_ROWCYCDLY2_bm (1<<5) /* SDRAM Row Cycle Delay bit 2 mask. */ -#define EBI_ROWCYCDLY2_bp 5 /* SDRAM Row Cycle Delay bit 2 position. */ - -#define EBI_RPDLY_gm 0x07 /* SDRAM Row-to-Precharge Delay group mask. */ -#define EBI_RPDLY_gp 0 /* SDRAM Row-to-Precharge Delay group position. */ -#define EBI_RPDLY0_bm (1<<0) /* SDRAM Row-to-Precharge Delay bit 0 mask. */ -#define EBI_RPDLY0_bp 0 /* SDRAM Row-to-Precharge Delay bit 0 position. */ -#define EBI_RPDLY1_bm (1<<1) /* SDRAM Row-to-Precharge Delay bit 1 mask. */ -#define EBI_RPDLY1_bp 1 /* SDRAM Row-to-Precharge Delay bit 1 position. */ -#define EBI_RPDLY2_bm (1<<2) /* SDRAM Row-to-Precharge Delay bit 2 mask. */ -#define EBI_RPDLY2_bp 2 /* SDRAM Row-to-Precharge Delay bit 2 position. */ - - -/* EBI.SDRAMCTRLC bit masks and bit positions */ -#define EBI_WRDLY_gm 0xC0 /* SDRAM Write Recovery Delay group mask. */ -#define EBI_WRDLY_gp 6 /* SDRAM Write Recovery Delay group position. */ -#define EBI_WRDLY0_bm (1<<6) /* SDRAM Write Recovery Delay bit 0 mask. */ -#define EBI_WRDLY0_bp 6 /* SDRAM Write Recovery Delay bit 0 position. */ -#define EBI_WRDLY1_bm (1<<7) /* SDRAM Write Recovery Delay bit 1 mask. */ -#define EBI_WRDLY1_bp 7 /* SDRAM Write Recovery Delay bit 1 position. */ - -#define EBI_ESRDLY_gm 0x38 /* SDRAM Exit-Self-refresh-to-Active Delay group mask. */ -#define EBI_ESRDLY_gp 3 /* SDRAM Exit-Self-refresh-to-Active Delay group position. */ -#define EBI_ESRDLY0_bm (1<<3) /* SDRAM Exit-Self-refresh-to-Active Delay bit 0 mask. */ -#define EBI_ESRDLY0_bp 3 /* SDRAM Exit-Self-refresh-to-Active Delay bit 0 position. */ -#define EBI_ESRDLY1_bm (1<<4) /* SDRAM Exit-Self-refresh-to-Active Delay bit 1 mask. */ -#define EBI_ESRDLY1_bp 4 /* SDRAM Exit-Self-refresh-to-Active Delay bit 1 position. */ -#define EBI_ESRDLY2_bm (1<<5) /* SDRAM Exit-Self-refresh-to-Active Delay bit 2 mask. */ -#define EBI_ESRDLY2_bp 5 /* SDRAM Exit-Self-refresh-to-Active Delay bit 2 position. */ - -#define EBI_ROWCOLDLY_gm 0x07 /* SDRAM Row-to-Column Delay group mask. */ -#define EBI_ROWCOLDLY_gp 0 /* SDRAM Row-to-Column Delay group position. */ -#define EBI_ROWCOLDLY0_bm (1<<0) /* SDRAM Row-to-Column Delay bit 0 mask. */ -#define EBI_ROWCOLDLY0_bp 0 /* SDRAM Row-to-Column Delay bit 0 position. */ -#define EBI_ROWCOLDLY1_bm (1<<1) /* SDRAM Row-to-Column Delay bit 1 mask. */ -#define EBI_ROWCOLDLY1_bp 1 /* SDRAM Row-to-Column Delay bit 1 position. */ -#define EBI_ROWCOLDLY2_bm (1<<2) /* SDRAM Row-to-Column Delay bit 2 mask. */ -#define EBI_ROWCOLDLY2_bp 2 /* SDRAM Row-to-Column Delay bit 2 position. */ - - -/* TWI - Two-Wire Interface */ -/* TWI_MASTER.CTRLA bit masks and bit positions */ -#define TWI_MASTER_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ -#define TWI_MASTER_INTLVL_gp 6 /* Interrupt Level group position. */ -#define TWI_MASTER_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ -#define TWI_MASTER_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ -#define TWI_MASTER_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ -#define TWI_MASTER_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ - -#define TWI_MASTER_RIEN_bm 0x20 /* Read Interrupt Enable bit mask. */ -#define TWI_MASTER_RIEN_bp 5 /* Read Interrupt Enable bit position. */ - -#define TWI_MASTER_WIEN_bm 0x10 /* Write Interrupt Enable bit mask. */ -#define TWI_MASTER_WIEN_bp 4 /* Write Interrupt Enable bit position. */ - -#define TWI_MASTER_ENABLE_bm 0x08 /* Enable TWI Master bit mask. */ -#define TWI_MASTER_ENABLE_bp 3 /* Enable TWI Master bit position. */ - - -/* TWI_MASTER.CTRLB bit masks and bit positions */ -#define TWI_MASTER_TIMEOUT_gm 0x0C /* Inactive Bus Timeout group mask. */ -#define TWI_MASTER_TIMEOUT_gp 2 /* Inactive Bus Timeout group position. */ -#define TWI_MASTER_TIMEOUT0_bm (1<<2) /* Inactive Bus Timeout bit 0 mask. */ -#define TWI_MASTER_TIMEOUT0_bp 2 /* Inactive Bus Timeout bit 0 position. */ -#define TWI_MASTER_TIMEOUT1_bm (1<<3) /* Inactive Bus Timeout bit 1 mask. */ -#define TWI_MASTER_TIMEOUT1_bp 3 /* Inactive Bus Timeout bit 1 position. */ - -#define TWI_MASTER_QCEN_bm 0x02 /* Quick Command Enable bit mask. */ -#define TWI_MASTER_QCEN_bp 1 /* Quick Command Enable bit position. */ - -#define TWI_MASTER_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ -#define TWI_MASTER_SMEN_bp 0 /* Smart Mode Enable bit position. */ - - -/* TWI_MASTER.CTRLC bit masks and bit positions */ -#define TWI_MASTER_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ -#define TWI_MASTER_ACKACT_bp 2 /* Acknowledge Action bit position. */ - -#define TWI_MASTER_CMD_gm 0x03 /* Command group mask. */ -#define TWI_MASTER_CMD_gp 0 /* Command group position. */ -#define TWI_MASTER_CMD0_bm (1<<0) /* Command bit 0 mask. */ -#define TWI_MASTER_CMD0_bp 0 /* Command bit 0 position. */ -#define TWI_MASTER_CMD1_bm (1<<1) /* Command bit 1 mask. */ -#define TWI_MASTER_CMD1_bp 1 /* Command bit 1 position. */ - - -/* TWI_MASTER.STATUS bit masks and bit positions */ -#define TWI_MASTER_RIF_bm 0x80 /* Read Interrupt Flag bit mask. */ -#define TWI_MASTER_RIF_bp 7 /* Read Interrupt Flag bit position. */ - -#define TWI_MASTER_WIF_bm 0x40 /* Write Interrupt Flag bit mask. */ -#define TWI_MASTER_WIF_bp 6 /* Write Interrupt Flag bit position. */ - -#define TWI_MASTER_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ -#define TWI_MASTER_CLKHOLD_bp 5 /* Clock Hold bit position. */ - -#define TWI_MASTER_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ -#define TWI_MASTER_RXACK_bp 4 /* Received Acknowledge bit position. */ - -#define TWI_MASTER_ARBLOST_bm 0x08 /* Arbitration Lost bit mask. */ -#define TWI_MASTER_ARBLOST_bp 3 /* Arbitration Lost bit position. */ - -#define TWI_MASTER_BUSERR_bm 0x04 /* Bus Error bit mask. */ -#define TWI_MASTER_BUSERR_bp 2 /* Bus Error bit position. */ - -#define TWI_MASTER_BUSSTATE_gm 0x03 /* Bus State group mask. */ -#define TWI_MASTER_BUSSTATE_gp 0 /* Bus State group position. */ -#define TWI_MASTER_BUSSTATE0_bm (1<<0) /* Bus State bit 0 mask. */ -#define TWI_MASTER_BUSSTATE0_bp 0 /* Bus State bit 0 position. */ -#define TWI_MASTER_BUSSTATE1_bm (1<<1) /* Bus State bit 1 mask. */ -#define TWI_MASTER_BUSSTATE1_bp 1 /* Bus State bit 1 position. */ - - -/* TWI_SLAVE.CTRLA bit masks and bit positions */ -#define TWI_SLAVE_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ -#define TWI_SLAVE_INTLVL_gp 6 /* Interrupt Level group position. */ -#define TWI_SLAVE_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ -#define TWI_SLAVE_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ -#define TWI_SLAVE_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ -#define TWI_SLAVE_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ - -#define TWI_SLAVE_DIEN_bm 0x20 /* Data Interrupt Enable bit mask. */ -#define TWI_SLAVE_DIEN_bp 5 /* Data Interrupt Enable bit position. */ - -#define TWI_SLAVE_APIEN_bm 0x10 /* Address/Stop Interrupt Enable bit mask. */ -#define TWI_SLAVE_APIEN_bp 4 /* Address/Stop Interrupt Enable bit position. */ - -#define TWI_SLAVE_ENABLE_bm 0x08 /* Enable TWI Slave bit mask. */ -#define TWI_SLAVE_ENABLE_bp 3 /* Enable TWI Slave bit position. */ - -#define TWI_SLAVE_PIEN_bm 0x04 /* Stop Interrupt Enable bit mask. */ -#define TWI_SLAVE_PIEN_bp 2 /* Stop Interrupt Enable bit position. */ - -#define TWI_SLAVE_PMEN_bm 0x02 /* Promiscuous Mode Enable bit mask. */ -#define TWI_SLAVE_PMEN_bp 1 /* Promiscuous Mode Enable bit position. */ - -#define TWI_SLAVE_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ -#define TWI_SLAVE_SMEN_bp 0 /* Smart Mode Enable bit position. */ - - -/* TWI_SLAVE.CTRLB bit masks and bit positions */ -#define TWI_SLAVE_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ -#define TWI_SLAVE_ACKACT_bp 2 /* Acknowledge Action bit position. */ - -#define TWI_SLAVE_CMD_gm 0x03 /* Command group mask. */ -#define TWI_SLAVE_CMD_gp 0 /* Command group position. */ -#define TWI_SLAVE_CMD0_bm (1<<0) /* Command bit 0 mask. */ -#define TWI_SLAVE_CMD0_bp 0 /* Command bit 0 position. */ -#define TWI_SLAVE_CMD1_bm (1<<1) /* Command bit 1 mask. */ -#define TWI_SLAVE_CMD1_bp 1 /* Command bit 1 position. */ - - -/* TWI_SLAVE.STATUS bit masks and bit positions */ -#define TWI_SLAVE_DIF_bm 0x80 /* Data Interrupt Flag bit mask. */ -#define TWI_SLAVE_DIF_bp 7 /* Data Interrupt Flag bit position. */ - -#define TWI_SLAVE_APIF_bm 0x40 /* Address/Stop Interrupt Flag bit mask. */ -#define TWI_SLAVE_APIF_bp 6 /* Address/Stop Interrupt Flag bit position. */ - -#define TWI_SLAVE_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ -#define TWI_SLAVE_CLKHOLD_bp 5 /* Clock Hold bit position. */ - -#define TWI_SLAVE_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ -#define TWI_SLAVE_RXACK_bp 4 /* Received Acknowledge bit position. */ - -#define TWI_SLAVE_COLL_bm 0x08 /* Collision bit mask. */ -#define TWI_SLAVE_COLL_bp 3 /* Collision bit position. */ - -#define TWI_SLAVE_BUSERR_bm 0x04 /* Bus Error bit mask. */ -#define TWI_SLAVE_BUSERR_bp 2 /* Bus Error bit position. */ - -#define TWI_SLAVE_DIR_bm 0x02 /* Read/Write Direction bit mask. */ -#define TWI_SLAVE_DIR_bp 1 /* Read/Write Direction bit position. */ - -#define TWI_SLAVE_AP_bm 0x01 /* Slave Address or Stop bit mask. */ -#define TWI_SLAVE_AP_bp 0 /* Slave Address or Stop bit position. */ - - -/* TWI_SLAVE.ADDRMASK bit masks and bit positions */ -#define TWI_SLAVE_ADDRMASK_gm 0xFE /* Address Mask group mask. */ -#define TWI_SLAVE_ADDRMASK_gp 1 /* Address Mask group position. */ -#define TWI_SLAVE_ADDRMASK0_bm (1<<1) /* Address Mask bit 0 mask. */ -#define TWI_SLAVE_ADDRMASK0_bp 1 /* Address Mask bit 0 position. */ -#define TWI_SLAVE_ADDRMASK1_bm (1<<2) /* Address Mask bit 1 mask. */ -#define TWI_SLAVE_ADDRMASK1_bp 2 /* Address Mask bit 1 position. */ -#define TWI_SLAVE_ADDRMASK2_bm (1<<3) /* Address Mask bit 2 mask. */ -#define TWI_SLAVE_ADDRMASK2_bp 3 /* Address Mask bit 2 position. */ -#define TWI_SLAVE_ADDRMASK3_bm (1<<4) /* Address Mask bit 3 mask. */ -#define TWI_SLAVE_ADDRMASK3_bp 4 /* Address Mask bit 3 position. */ -#define TWI_SLAVE_ADDRMASK4_bm (1<<5) /* Address Mask bit 4 mask. */ -#define TWI_SLAVE_ADDRMASK4_bp 5 /* Address Mask bit 4 position. */ -#define TWI_SLAVE_ADDRMASK5_bm (1<<6) /* Address Mask bit 5 mask. */ -#define TWI_SLAVE_ADDRMASK5_bp 6 /* Address Mask bit 5 position. */ -#define TWI_SLAVE_ADDRMASK6_bm (1<<7) /* Address Mask bit 6 mask. */ -#define TWI_SLAVE_ADDRMASK6_bp 7 /* Address Mask bit 6 position. */ - -#define TWI_SLAVE_ADDREN_bm 0x01 /* Address Enable bit mask. */ -#define TWI_SLAVE_ADDREN_bp 0 /* Address Enable bit position. */ - - -/* TWI.CTRL bit masks and bit positions */ -#define TWI_SDAHOLD_bm 0x02 /* SDA Hold Time Enable bit mask. */ -#define TWI_SDAHOLD_bp 1 /* SDA Hold Time Enable bit position. */ - -#define TWI_EDIEN_bm 0x01 /* External Driver Interface Enable bit mask. */ -#define TWI_EDIEN_bp 0 /* External Driver Interface Enable bit position. */ - - -/* PORT - Port Configuration */ -/* PORTCFG.VPCTRLA bit masks and bit positions */ -#define PORTCFG_VP1MAP_gm 0xF0 /* Virtual Port 1 Mapping group mask. */ -#define PORTCFG_VP1MAP_gp 4 /* Virtual Port 1 Mapping group position. */ -#define PORTCFG_VP1MAP0_bm (1<<4) /* Virtual Port 1 Mapping bit 0 mask. */ -#define PORTCFG_VP1MAP0_bp 4 /* Virtual Port 1 Mapping bit 0 position. */ -#define PORTCFG_VP1MAP1_bm (1<<5) /* Virtual Port 1 Mapping bit 1 mask. */ -#define PORTCFG_VP1MAP1_bp 5 /* Virtual Port 1 Mapping bit 1 position. */ -#define PORTCFG_VP1MAP2_bm (1<<6) /* Virtual Port 1 Mapping bit 2 mask. */ -#define PORTCFG_VP1MAP2_bp 6 /* Virtual Port 1 Mapping bit 2 position. */ -#define PORTCFG_VP1MAP3_bm (1<<7) /* Virtual Port 1 Mapping bit 3 mask. */ -#define PORTCFG_VP1MAP3_bp 7 /* Virtual Port 1 Mapping bit 3 position. */ - -#define PORTCFG_VP0MAP_gm 0x0F /* Virtual Port 0 Mapping group mask. */ -#define PORTCFG_VP0MAP_gp 0 /* Virtual Port 0 Mapping group position. */ -#define PORTCFG_VP0MAP0_bm (1<<0) /* Virtual Port 0 Mapping bit 0 mask. */ -#define PORTCFG_VP0MAP0_bp 0 /* Virtual Port 0 Mapping bit 0 position. */ -#define PORTCFG_VP0MAP1_bm (1<<1) /* Virtual Port 0 Mapping bit 1 mask. */ -#define PORTCFG_VP0MAP1_bp 1 /* Virtual Port 0 Mapping bit 1 position. */ -#define PORTCFG_VP0MAP2_bm (1<<2) /* Virtual Port 0 Mapping bit 2 mask. */ -#define PORTCFG_VP0MAP2_bp 2 /* Virtual Port 0 Mapping bit 2 position. */ -#define PORTCFG_VP0MAP3_bm (1<<3) /* Virtual Port 0 Mapping bit 3 mask. */ -#define PORTCFG_VP0MAP3_bp 3 /* Virtual Port 0 Mapping bit 3 position. */ - - -/* PORTCFG.VPCTRLB bit masks and bit positions */ -#define PORTCFG_VP3MAP_gm 0xF0 /* Virtual Port 3 Mapping group mask. */ -#define PORTCFG_VP3MAP_gp 4 /* Virtual Port 3 Mapping group position. */ -#define PORTCFG_VP3MAP0_bm (1<<4) /* Virtual Port 3 Mapping bit 0 mask. */ -#define PORTCFG_VP3MAP0_bp 4 /* Virtual Port 3 Mapping bit 0 position. */ -#define PORTCFG_VP3MAP1_bm (1<<5) /* Virtual Port 3 Mapping bit 1 mask. */ -#define PORTCFG_VP3MAP1_bp 5 /* Virtual Port 3 Mapping bit 1 position. */ -#define PORTCFG_VP3MAP2_bm (1<<6) /* Virtual Port 3 Mapping bit 2 mask. */ -#define PORTCFG_VP3MAP2_bp 6 /* Virtual Port 3 Mapping bit 2 position. */ -#define PORTCFG_VP3MAP3_bm (1<<7) /* Virtual Port 3 Mapping bit 3 mask. */ -#define PORTCFG_VP3MAP3_bp 7 /* Virtual Port 3 Mapping bit 3 position. */ - -#define PORTCFG_VP2MAP_gm 0x0F /* Virtual Port 2 Mapping group mask. */ -#define PORTCFG_VP2MAP_gp 0 /* Virtual Port 2 Mapping group position. */ -#define PORTCFG_VP2MAP0_bm (1<<0) /* Virtual Port 2 Mapping bit 0 mask. */ -#define PORTCFG_VP2MAP0_bp 0 /* Virtual Port 2 Mapping bit 0 position. */ -#define PORTCFG_VP2MAP1_bm (1<<1) /* Virtual Port 2 Mapping bit 1 mask. */ -#define PORTCFG_VP2MAP1_bp 1 /* Virtual Port 2 Mapping bit 1 position. */ -#define PORTCFG_VP2MAP2_bm (1<<2) /* Virtual Port 2 Mapping bit 2 mask. */ -#define PORTCFG_VP2MAP2_bp 2 /* Virtual Port 2 Mapping bit 2 position. */ -#define PORTCFG_VP2MAP3_bm (1<<3) /* Virtual Port 2 Mapping bit 3 mask. */ -#define PORTCFG_VP2MAP3_bp 3 /* Virtual Port 2 Mapping bit 3 position. */ - - -/* PORTCFG.CLKEVOUT bit masks and bit positions */ -#define PORTCFG_CLKOUT_gm 0x03 /* Clock Output Port group mask. */ -#define PORTCFG_CLKOUT_gp 0 /* Clock Output Port group position. */ -#define PORTCFG_CLKOUT0_bm (1<<0) /* Clock Output Port bit 0 mask. */ -#define PORTCFG_CLKOUT0_bp 0 /* Clock Output Port bit 0 position. */ -#define PORTCFG_CLKOUT1_bm (1<<1) /* Clock Output Port bit 1 mask. */ -#define PORTCFG_CLKOUT1_bp 1 /* Clock Output Port bit 1 position. */ - -#define PORTCFG_EVOUT_gm 0x30 /* Event Output Port group mask. */ -#define PORTCFG_EVOUT_gp 4 /* Event Output Port group position. */ -#define PORTCFG_EVOUT0_bm (1<<4) /* Event Output Port bit 0 mask. */ -#define PORTCFG_EVOUT0_bp 4 /* Event Output Port bit 0 position. */ -#define PORTCFG_EVOUT1_bm (1<<5) /* Event Output Port bit 1 mask. */ -#define PORTCFG_EVOUT1_bp 5 /* Event Output Port bit 1 position. */ - - -/* VPORT.INTFLAGS bit masks and bit positions */ -#define VPORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ -#define VPORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ - -#define VPORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ -#define VPORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ - - -/* PORT.INTCTRL bit masks and bit positions */ -#define PORT_INT1LVL_gm 0x0C /* Port Interrupt 1 Level group mask. */ -#define PORT_INT1LVL_gp 2 /* Port Interrupt 1 Level group position. */ -#define PORT_INT1LVL0_bm (1<<2) /* Port Interrupt 1 Level bit 0 mask. */ -#define PORT_INT1LVL0_bp 2 /* Port Interrupt 1 Level bit 0 position. */ -#define PORT_INT1LVL1_bm (1<<3) /* Port Interrupt 1 Level bit 1 mask. */ -#define PORT_INT1LVL1_bp 3 /* Port Interrupt 1 Level bit 1 position. */ - -#define PORT_INT0LVL_gm 0x03 /* Port Interrupt 0 Level group mask. */ -#define PORT_INT0LVL_gp 0 /* Port Interrupt 0 Level group position. */ -#define PORT_INT0LVL0_bm (1<<0) /* Port Interrupt 0 Level bit 0 mask. */ -#define PORT_INT0LVL0_bp 0 /* Port Interrupt 0 Level bit 0 position. */ -#define PORT_INT0LVL1_bm (1<<1) /* Port Interrupt 0 Level bit 1 mask. */ -#define PORT_INT0LVL1_bp 1 /* Port Interrupt 0 Level bit 1 position. */ - - -/* PORT.INTFLAGS bit masks and bit positions */ -#define PORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ -#define PORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ - -#define PORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ -#define PORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ - - -/* PORT.PIN0CTRL bit masks and bit positions */ -#define PORT_SRLEN_bm 0x80 /* Slew Rate Enable bit mask. */ -#define PORT_SRLEN_bp 7 /* Slew Rate Enable bit position. */ - -#define PORT_INVEN_bm 0x40 /* Inverted I/O Enable bit mask. */ -#define PORT_INVEN_bp 6 /* Inverted I/O Enable bit position. */ - -#define PORT_OPC_gm 0x38 /* Output/Pull Configuration group mask. */ -#define PORT_OPC_gp 3 /* Output/Pull Configuration group position. */ -#define PORT_OPC0_bm (1<<3) /* Output/Pull Configuration bit 0 mask. */ -#define PORT_OPC0_bp 3 /* Output/Pull Configuration bit 0 position. */ -#define PORT_OPC1_bm (1<<4) /* Output/Pull Configuration bit 1 mask. */ -#define PORT_OPC1_bp 4 /* Output/Pull Configuration bit 1 position. */ -#define PORT_OPC2_bm (1<<5) /* Output/Pull Configuration bit 2 mask. */ -#define PORT_OPC2_bp 5 /* Output/Pull Configuration bit 2 position. */ - -#define PORT_ISC_gm 0x07 /* Input/Sense Configuration group mask. */ -#define PORT_ISC_gp 0 /* Input/Sense Configuration group position. */ -#define PORT_ISC0_bm (1<<0) /* Input/Sense Configuration bit 0 mask. */ -#define PORT_ISC0_bp 0 /* Input/Sense Configuration bit 0 position. */ -#define PORT_ISC1_bm (1<<1) /* Input/Sense Configuration bit 1 mask. */ -#define PORT_ISC1_bp 1 /* Input/Sense Configuration bit 1 position. */ -#define PORT_ISC2_bm (1<<2) /* Input/Sense Configuration bit 2 mask. */ -#define PORT_ISC2_bp 2 /* Input/Sense Configuration bit 2 position. */ - - -/* PORT.PIN1CTRL bit masks and bit positions */ -/* PORT_SRLEN_bm Predefined. */ -/* PORT_SRLEN_bp Predefined. */ - -/* PORT_INVEN_bm Predefined. */ -/* PORT_INVEN_bp Predefined. */ - -/* PORT_OPC_gm Predefined. */ -/* PORT_OPC_gp Predefined. */ -/* PORT_OPC0_bm Predefined. */ -/* PORT_OPC0_bp Predefined. */ -/* PORT_OPC1_bm Predefined. */ -/* PORT_OPC1_bp Predefined. */ -/* PORT_OPC2_bm Predefined. */ -/* PORT_OPC2_bp Predefined. */ - -/* PORT_ISC_gm Predefined. */ -/* PORT_ISC_gp Predefined. */ -/* PORT_ISC0_bm Predefined. */ -/* PORT_ISC0_bp Predefined. */ -/* PORT_ISC1_bm Predefined. */ -/* PORT_ISC1_bp Predefined. */ -/* PORT_ISC2_bm Predefined. */ -/* PORT_ISC2_bp Predefined. */ - - -/* PORT.PIN2CTRL bit masks and bit positions */ -/* PORT_SRLEN_bm Predefined. */ -/* PORT_SRLEN_bp Predefined. */ - -/* PORT_INVEN_bm Predefined. */ -/* PORT_INVEN_bp Predefined. */ - -/* PORT_OPC_gm Predefined. */ -/* PORT_OPC_gp Predefined. */ -/* PORT_OPC0_bm Predefined. */ -/* PORT_OPC0_bp Predefined. */ -/* PORT_OPC1_bm Predefined. */ -/* PORT_OPC1_bp Predefined. */ -/* PORT_OPC2_bm Predefined. */ -/* PORT_OPC2_bp Predefined. */ - -/* PORT_ISC_gm Predefined. */ -/* PORT_ISC_gp Predefined. */ -/* PORT_ISC0_bm Predefined. */ -/* PORT_ISC0_bp Predefined. */ -/* PORT_ISC1_bm Predefined. */ -/* PORT_ISC1_bp Predefined. */ -/* PORT_ISC2_bm Predefined. */ -/* PORT_ISC2_bp Predefined. */ - - -/* PORT.PIN3CTRL bit masks and bit positions */ -/* PORT_SRLEN_bm Predefined. */ -/* PORT_SRLEN_bp Predefined. */ - -/* PORT_INVEN_bm Predefined. */ -/* PORT_INVEN_bp Predefined. */ - -/* PORT_OPC_gm Predefined. */ -/* PORT_OPC_gp Predefined. */ -/* PORT_OPC0_bm Predefined. */ -/* PORT_OPC0_bp Predefined. */ -/* PORT_OPC1_bm Predefined. */ -/* PORT_OPC1_bp Predefined. */ -/* PORT_OPC2_bm Predefined. */ -/* PORT_OPC2_bp Predefined. */ - -/* PORT_ISC_gm Predefined. */ -/* PORT_ISC_gp Predefined. */ -/* PORT_ISC0_bm Predefined. */ -/* PORT_ISC0_bp Predefined. */ -/* PORT_ISC1_bm Predefined. */ -/* PORT_ISC1_bp Predefined. */ -/* PORT_ISC2_bm Predefined. */ -/* PORT_ISC2_bp Predefined. */ - - -/* PORT.PIN4CTRL bit masks and bit positions */ -/* PORT_SRLEN_bm Predefined. */ -/* PORT_SRLEN_bp Predefined. */ - -/* PORT_INVEN_bm Predefined. */ -/* PORT_INVEN_bp Predefined. */ - -/* PORT_OPC_gm Predefined. */ -/* PORT_OPC_gp Predefined. */ -/* PORT_OPC0_bm Predefined. */ -/* PORT_OPC0_bp Predefined. */ -/* PORT_OPC1_bm Predefined. */ -/* PORT_OPC1_bp Predefined. */ -/* PORT_OPC2_bm Predefined. */ -/* PORT_OPC2_bp Predefined. */ - -/* PORT_ISC_gm Predefined. */ -/* PORT_ISC_gp Predefined. */ -/* PORT_ISC0_bm Predefined. */ -/* PORT_ISC0_bp Predefined. */ -/* PORT_ISC1_bm Predefined. */ -/* PORT_ISC1_bp Predefined. */ -/* PORT_ISC2_bm Predefined. */ -/* PORT_ISC2_bp Predefined. */ - - -/* PORT.PIN5CTRL bit masks and bit positions */ -/* PORT_SRLEN_bm Predefined. */ -/* PORT_SRLEN_bp Predefined. */ - -/* PORT_INVEN_bm Predefined. */ -/* PORT_INVEN_bp Predefined. */ - -/* PORT_OPC_gm Predefined. */ -/* PORT_OPC_gp Predefined. */ -/* PORT_OPC0_bm Predefined. */ -/* PORT_OPC0_bp Predefined. */ -/* PORT_OPC1_bm Predefined. */ -/* PORT_OPC1_bp Predefined. */ -/* PORT_OPC2_bm Predefined. */ -/* PORT_OPC2_bp Predefined. */ - -/* PORT_ISC_gm Predefined. */ -/* PORT_ISC_gp Predefined. */ -/* PORT_ISC0_bm Predefined. */ -/* PORT_ISC0_bp Predefined. */ -/* PORT_ISC1_bm Predefined. */ -/* PORT_ISC1_bp Predefined. */ -/* PORT_ISC2_bm Predefined. */ -/* PORT_ISC2_bp Predefined. */ - - -/* PORT.PIN6CTRL bit masks and bit positions */ -/* PORT_SRLEN_bm Predefined. */ -/* PORT_SRLEN_bp Predefined. */ - -/* PORT_INVEN_bm Predefined. */ -/* PORT_INVEN_bp Predefined. */ - -/* PORT_OPC_gm Predefined. */ -/* PORT_OPC_gp Predefined. */ -/* PORT_OPC0_bm Predefined. */ -/* PORT_OPC0_bp Predefined. */ -/* PORT_OPC1_bm Predefined. */ -/* PORT_OPC1_bp Predefined. */ -/* PORT_OPC2_bm Predefined. */ -/* PORT_OPC2_bp Predefined. */ - -/* PORT_ISC_gm Predefined. */ -/* PORT_ISC_gp Predefined. */ -/* PORT_ISC0_bm Predefined. */ -/* PORT_ISC0_bp Predefined. */ -/* PORT_ISC1_bm Predefined. */ -/* PORT_ISC1_bp Predefined. */ -/* PORT_ISC2_bm Predefined. */ -/* PORT_ISC2_bp Predefined. */ - - -/* PORT.PIN7CTRL bit masks and bit positions */ -/* PORT_SRLEN_bm Predefined. */ -/* PORT_SRLEN_bp Predefined. */ - -/* PORT_INVEN_bm Predefined. */ -/* PORT_INVEN_bp Predefined. */ - -/* PORT_OPC_gm Predefined. */ -/* PORT_OPC_gp Predefined. */ -/* PORT_OPC0_bm Predefined. */ -/* PORT_OPC0_bp Predefined. */ -/* PORT_OPC1_bm Predefined. */ -/* PORT_OPC1_bp Predefined. */ -/* PORT_OPC2_bm Predefined. */ -/* PORT_OPC2_bp Predefined. */ - -/* PORT_ISC_gm Predefined. */ -/* PORT_ISC_gp Predefined. */ -/* PORT_ISC0_bm Predefined. */ -/* PORT_ISC0_bp Predefined. */ -/* PORT_ISC1_bm Predefined. */ -/* PORT_ISC1_bp Predefined. */ -/* PORT_ISC2_bm Predefined. */ -/* PORT_ISC2_bp Predefined. */ - - -/* TC - 16-bit Timer/Counter With PWM */ -/* TC0.CTRLA bit masks and bit positions */ -#define TC0_CLKSEL_gm 0x0F /* Clock Selection group mask. */ -#define TC0_CLKSEL_gp 0 /* Clock Selection group position. */ -#define TC0_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ -#define TC0_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ -#define TC0_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ -#define TC0_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ -#define TC0_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ -#define TC0_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ -#define TC0_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ -#define TC0_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ - - -/* TC0.CTRLB bit masks and bit positions */ -#define TC0_CCDEN_bm 0x80 /* Compare or Capture D Enable bit mask. */ -#define TC0_CCDEN_bp 7 /* Compare or Capture D Enable bit position. */ - -#define TC0_CCCEN_bm 0x40 /* Compare or Capture C Enable bit mask. */ -#define TC0_CCCEN_bp 6 /* Compare or Capture C Enable bit position. */ - -#define TC0_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ -#define TC0_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ - -#define TC0_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ -#define TC0_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ - -#define TC0_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ -#define TC0_WGMODE_gp 0 /* Waveform generation mode group position. */ -#define TC0_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ -#define TC0_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ -#define TC0_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ -#define TC0_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ -#define TC0_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ -#define TC0_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ - - -/* TC0.CTRLC bit masks and bit positions */ -#define TC0_CMPD_bm 0x08 /* Compare D Output Value bit mask. */ -#define TC0_CMPD_bp 3 /* Compare D Output Value bit position. */ - -#define TC0_CMPC_bm 0x04 /* Compare C Output Value bit mask. */ -#define TC0_CMPC_bp 2 /* Compare C Output Value bit position. */ - -#define TC0_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ -#define TC0_CMPB_bp 1 /* Compare B Output Value bit position. */ - -#define TC0_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ -#define TC0_CMPA_bp 0 /* Compare A Output Value bit position. */ - - -/* TC0.CTRLD bit masks and bit positions */ -#define TC0_EVACT_gm 0xE0 /* Event Action group mask. */ -#define TC0_EVACT_gp 5 /* Event Action group position. */ -#define TC0_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ -#define TC0_EVACT0_bp 5 /* Event Action bit 0 position. */ -#define TC0_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ -#define TC0_EVACT1_bp 6 /* Event Action bit 1 position. */ -#define TC0_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ -#define TC0_EVACT2_bp 7 /* Event Action bit 2 position. */ - -#define TC0_EVDLY_bm 0x10 /* Event Delay bit mask. */ -#define TC0_EVDLY_bp 4 /* Event Delay bit position. */ - -#define TC0_EVSEL_gm 0x0F /* Event Source Select group mask. */ -#define TC0_EVSEL_gp 0 /* Event Source Select group position. */ -#define TC0_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ -#define TC0_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ -#define TC0_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ -#define TC0_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ -#define TC0_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ -#define TC0_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ -#define TC0_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ -#define TC0_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ - - -/* TC0.CTRLE bit masks and bit positions */ -#define TC0_DTHM_bm 0x02 /* Dead Time Hold Mode bit mask. */ -#define TC0_DTHM_bp 1 /* Dead Time Hold Mode bit position. */ - -#define TC0_BYTEM_bm 0x01 /* Byte Mode bit mask. */ -#define TC0_BYTEM_bp 0 /* Byte Mode bit position. */ - - -/* TC0.INTCTRLA bit masks and bit positions */ -#define TC0_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ -#define TC0_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ -#define TC0_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ -#define TC0_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ -#define TC0_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ -#define TC0_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ - -#define TC0_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ -#define TC0_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ -#define TC0_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ -#define TC0_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ -#define TC0_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ -#define TC0_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ - - -/* TC0.INTCTRLB bit masks and bit positions */ -#define TC0_CCDINTLVL_gm 0xC0 /* Compare or Capture D Interrupt Level group mask. */ -#define TC0_CCDINTLVL_gp 6 /* Compare or Capture D Interrupt Level group position. */ -#define TC0_CCDINTLVL0_bm (1<<6) /* Compare or Capture D Interrupt Level bit 0 mask. */ -#define TC0_CCDINTLVL0_bp 6 /* Compare or Capture D Interrupt Level bit 0 position. */ -#define TC0_CCDINTLVL1_bm (1<<7) /* Compare or Capture D Interrupt Level bit 1 mask. */ -#define TC0_CCDINTLVL1_bp 7 /* Compare or Capture D Interrupt Level bit 1 position. */ - -#define TC0_CCCINTLVL_gm 0x30 /* Compare or Capture C Interrupt Level group mask. */ -#define TC0_CCCINTLVL_gp 4 /* Compare or Capture C Interrupt Level group position. */ -#define TC0_CCCINTLVL0_bm (1<<4) /* Compare or Capture C Interrupt Level bit 0 mask. */ -#define TC0_CCCINTLVL0_bp 4 /* Compare or Capture C Interrupt Level bit 0 position. */ -#define TC0_CCCINTLVL1_bm (1<<5) /* Compare or Capture C Interrupt Level bit 1 mask. */ -#define TC0_CCCINTLVL1_bp 5 /* Compare or Capture C Interrupt Level bit 1 position. */ - -#define TC0_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ -#define TC0_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ -#define TC0_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ -#define TC0_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ -#define TC0_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ -#define TC0_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ - -#define TC0_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ -#define TC0_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ -#define TC0_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ -#define TC0_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ -#define TC0_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ -#define TC0_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ - - -/* TC0.CTRLFCLR bit masks and bit positions */ -#define TC0_CMD_gm 0x0C /* Command group mask. */ -#define TC0_CMD_gp 2 /* Command group position. */ -#define TC0_CMD0_bm (1<<2) /* Command bit 0 mask. */ -#define TC0_CMD0_bp 2 /* Command bit 0 position. */ -#define TC0_CMD1_bm (1<<3) /* Command bit 1 mask. */ -#define TC0_CMD1_bp 3 /* Command bit 1 position. */ - -#define TC0_LUPD_bm 0x02 /* Lock Update bit mask. */ -#define TC0_LUPD_bp 1 /* Lock Update bit position. */ - -#define TC0_DIR_bm 0x01 /* Direction bit mask. */ -#define TC0_DIR_bp 0 /* Direction bit position. */ - - -/* TC0.CTRLFSET bit masks and bit positions */ -/* TC0_CMD_gm Predefined. */ -/* TC0_CMD_gp Predefined. */ -/* TC0_CMD0_bm Predefined. */ -/* TC0_CMD0_bp Predefined. */ -/* TC0_CMD1_bm Predefined. */ -/* TC0_CMD1_bp Predefined. */ - -/* TC0_LUPD_bm Predefined. */ -/* TC0_LUPD_bp Predefined. */ - -/* TC0_DIR_bm Predefined. */ -/* TC0_DIR_bp Predefined. */ - - -/* TC0.CTRLGCLR bit masks and bit positions */ -#define TC0_CCDBV_bm 0x10 /* Compare or Capture D Buffer Valid bit mask. */ -#define TC0_CCDBV_bp 4 /* Compare or Capture D Buffer Valid bit position. */ - -#define TC0_CCCBV_bm 0x08 /* Compare or Capture C Buffer Valid bit mask. */ -#define TC0_CCCBV_bp 3 /* Compare or Capture C Buffer Valid bit position. */ - -#define TC0_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ -#define TC0_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ - -#define TC0_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ -#define TC0_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ - -#define TC0_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ -#define TC0_PERBV_bp 0 /* Period Buffer Valid bit position. */ - - -/* TC0.CTRLGSET bit masks and bit positions */ -/* TC0_CCDBV_bm Predefined. */ -/* TC0_CCDBV_bp Predefined. */ - -/* TC0_CCCBV_bm Predefined. */ -/* TC0_CCCBV_bp Predefined. */ - -/* TC0_CCBBV_bm Predefined. */ -/* TC0_CCBBV_bp Predefined. */ - -/* TC0_CCABV_bm Predefined. */ -/* TC0_CCABV_bp Predefined. */ - -/* TC0_PERBV_bm Predefined. */ -/* TC0_PERBV_bp Predefined. */ - - -/* TC0.INTFLAGS bit masks and bit positions */ -#define TC0_CCDIF_bm 0x80 /* Compare or Capture D Interrupt Flag bit mask. */ -#define TC0_CCDIF_bp 7 /* Compare or Capture D Interrupt Flag bit position. */ - -#define TC0_CCCIF_bm 0x40 /* Compare or Capture C Interrupt Flag bit mask. */ -#define TC0_CCCIF_bp 6 /* Compare or Capture C Interrupt Flag bit position. */ - -#define TC0_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ -#define TC0_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ - -#define TC0_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ -#define TC0_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ - -#define TC0_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ -#define TC0_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ - -#define TC0_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ -#define TC0_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ - - -/* TC1.CTRLA bit masks and bit positions */ -#define TC1_CLKSEL_gm 0x0F /* Clock Selection group mask. */ -#define TC1_CLKSEL_gp 0 /* Clock Selection group position. */ -#define TC1_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ -#define TC1_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ -#define TC1_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ -#define TC1_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ -#define TC1_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ -#define TC1_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ -#define TC1_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ -#define TC1_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ - - -/* TC1.CTRLB bit masks and bit positions */ -#define TC1_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ -#define TC1_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ - -#define TC1_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ -#define TC1_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ - -#define TC1_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ -#define TC1_WGMODE_gp 0 /* Waveform generation mode group position. */ -#define TC1_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ -#define TC1_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ -#define TC1_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ -#define TC1_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ -#define TC1_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ -#define TC1_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ - - -/* TC1.CTRLC bit masks and bit positions */ -#define TC1_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ -#define TC1_CMPB_bp 1 /* Compare B Output Value bit position. */ - -#define TC1_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ -#define TC1_CMPA_bp 0 /* Compare A Output Value bit position. */ - - -/* TC1.CTRLD bit masks and bit positions */ -#define TC1_EVACT_gm 0xE0 /* Event Action group mask. */ -#define TC1_EVACT_gp 5 /* Event Action group position. */ -#define TC1_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ -#define TC1_EVACT0_bp 5 /* Event Action bit 0 position. */ -#define TC1_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ -#define TC1_EVACT1_bp 6 /* Event Action bit 1 position. */ -#define TC1_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ -#define TC1_EVACT2_bp 7 /* Event Action bit 2 position. */ - -#define TC1_EVDLY_bm 0x10 /* Event Delay bit mask. */ -#define TC1_EVDLY_bp 4 /* Event Delay bit position. */ - -#define TC1_EVSEL_gm 0x0F /* Event Source Select group mask. */ -#define TC1_EVSEL_gp 0 /* Event Source Select group position. */ -#define TC1_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ -#define TC1_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ -#define TC1_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ -#define TC1_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ -#define TC1_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ -#define TC1_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ -#define TC1_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ -#define TC1_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ - - -/* TC1.CTRLE bit masks and bit positions */ -#define TC1_DTHM_bm 0x02 /* Dead Time Hold Mode bit mask. */ -#define TC1_DTHM_bp 1 /* Dead Time Hold Mode bit position. */ - -#define TC1_BYTEM_bm 0x01 /* Byte Mode bit mask. */ -#define TC1_BYTEM_bp 0 /* Byte Mode bit position. */ - - -/* TC1.INTCTRLA bit masks and bit positions */ -#define TC1_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ -#define TC1_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ -#define TC1_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ -#define TC1_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ -#define TC1_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ -#define TC1_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ - -#define TC1_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ -#define TC1_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ -#define TC1_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ -#define TC1_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ -#define TC1_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ -#define TC1_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ - - -/* TC1.INTCTRLB bit masks and bit positions */ -#define TC1_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ -#define TC1_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ -#define TC1_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ -#define TC1_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ -#define TC1_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ -#define TC1_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ - -#define TC1_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ -#define TC1_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ -#define TC1_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ -#define TC1_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ -#define TC1_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ -#define TC1_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ - - -/* TC1.CTRLFCLR bit masks and bit positions */ -#define TC1_CMD_gm 0x0C /* Command group mask. */ -#define TC1_CMD_gp 2 /* Command group position. */ -#define TC1_CMD0_bm (1<<2) /* Command bit 0 mask. */ -#define TC1_CMD0_bp 2 /* Command bit 0 position. */ -#define TC1_CMD1_bm (1<<3) /* Command bit 1 mask. */ -#define TC1_CMD1_bp 3 /* Command bit 1 position. */ - -#define TC1_LUPD_bm 0x02 /* Lock Update bit mask. */ -#define TC1_LUPD_bp 1 /* Lock Update bit position. */ - -#define TC1_DIR_bm 0x01 /* Direction bit mask. */ -#define TC1_DIR_bp 0 /* Direction bit position. */ - - -/* TC1.CTRLFSET bit masks and bit positions */ -/* TC1_CMD_gm Predefined. */ -/* TC1_CMD_gp Predefined. */ -/* TC1_CMD0_bm Predefined. */ -/* TC1_CMD0_bp Predefined. */ -/* TC1_CMD1_bm Predefined. */ -/* TC1_CMD1_bp Predefined. */ - -/* TC1_LUPD_bm Predefined. */ -/* TC1_LUPD_bp Predefined. */ - -/* TC1_DIR_bm Predefined. */ -/* TC1_DIR_bp Predefined. */ - - -/* TC1.CTRLGCLR bit masks and bit positions */ -#define TC1_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ -#define TC1_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ - -#define TC1_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ -#define TC1_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ - -#define TC1_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ -#define TC1_PERBV_bp 0 /* Period Buffer Valid bit position. */ - - -/* TC1.CTRLGSET bit masks and bit positions */ -/* TC1_CCBBV_bm Predefined. */ -/* TC1_CCBBV_bp Predefined. */ - -/* TC1_CCABV_bm Predefined. */ -/* TC1_CCABV_bp Predefined. */ - -/* TC1_PERBV_bm Predefined. */ -/* TC1_PERBV_bp Predefined. */ - - -/* TC1.INTFLAGS bit masks and bit positions */ -#define TC1_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ -#define TC1_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ - -#define TC1_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ -#define TC1_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ - -#define TC1_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ -#define TC1_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ - -#define TC1_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ -#define TC1_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ - - -/* AWEX.CTRL bit masks and bit positions */ -#define AWEX_PGM_bm 0x20 /* Pattern Generation Mode bit mask. */ -#define AWEX_PGM_bp 5 /* Pattern Generation Mode bit position. */ - -#define AWEX_CWCM_bm 0x10 /* Common Waveform Channel Mode bit mask. */ -#define AWEX_CWCM_bp 4 /* Common Waveform Channel Mode bit position. */ - -#define AWEX_DTICCDEN_bm 0x08 /* Dead Time Insertion Compare Channel D Enable bit mask. */ -#define AWEX_DTICCDEN_bp 3 /* Dead Time Insertion Compare Channel D Enable bit position. */ - -#define AWEX_DTICCCEN_bm 0x04 /* Dead Time Insertion Compare Channel C Enable bit mask. */ -#define AWEX_DTICCCEN_bp 2 /* Dead Time Insertion Compare Channel C Enable bit position. */ - -#define AWEX_DTICCBEN_bm 0x02 /* Dead Time Insertion Compare Channel B Enable bit mask. */ -#define AWEX_DTICCBEN_bp 1 /* Dead Time Insertion Compare Channel B Enable bit position. */ - -#define AWEX_DTICCAEN_bm 0x01 /* Dead Time Insertion Compare Channel A Enable bit mask. */ -#define AWEX_DTICCAEN_bp 0 /* Dead Time Insertion Compare Channel A Enable bit position. */ - - -/* AWEX.FDCTRL bit masks and bit positions */ -#define AWEX_FDDBD_bm 0x10 /* Fault Detect on Disable Break Disable bit mask. */ -#define AWEX_FDDBD_bp 4 /* Fault Detect on Disable Break Disable bit position. */ - -#define AWEX_FDMODE_bm 0x04 /* Fault Detect Mode bit mask. */ -#define AWEX_FDMODE_bp 2 /* Fault Detect Mode bit position. */ - -#define AWEX_FDACT_gm 0x03 /* Fault Detect Action group mask. */ -#define AWEX_FDACT_gp 0 /* Fault Detect Action group position. */ -#define AWEX_FDACT0_bm (1<<0) /* Fault Detect Action bit 0 mask. */ -#define AWEX_FDACT0_bp 0 /* Fault Detect Action bit 0 position. */ -#define AWEX_FDACT1_bm (1<<1) /* Fault Detect Action bit 1 mask. */ -#define AWEX_FDACT1_bp 1 /* Fault Detect Action bit 1 position. */ - - -/* AWEX.STATUS bit masks and bit positions */ -#define AWEX_FDF_bm 0x04 /* Fault Detect Flag bit mask. */ -#define AWEX_FDF_bp 2 /* Fault Detect Flag bit position. */ - -#define AWEX_DTHSBUFV_bm 0x02 /* Dead Time High Side Buffer Valid bit mask. */ -#define AWEX_DTHSBUFV_bp 1 /* Dead Time High Side Buffer Valid bit position. */ - -#define AWEX_DTLSBUFV_bm 0x01 /* Dead Time Low Side Buffer Valid bit mask. */ -#define AWEX_DTLSBUFV_bp 0 /* Dead Time Low Side Buffer Valid bit position. */ - - -/* HIRES.CTRL bit masks and bit positions */ -#define HIRES_HREN_gm 0x03 /* High Resolution Enable group mask. */ -#define HIRES_HREN_gp 0 /* High Resolution Enable group position. */ -#define HIRES_HREN0_bm (1<<0) /* High Resolution Enable bit 0 mask. */ -#define HIRES_HREN0_bp 0 /* High Resolution Enable bit 0 position. */ -#define HIRES_HREN1_bm (1<<1) /* High Resolution Enable bit 1 mask. */ -#define HIRES_HREN1_bp 1 /* High Resolution Enable bit 1 position. */ - - -/* USART - Universal Asynchronous Receiver-Transmitter */ -/* USART.STATUS bit masks and bit positions */ -#define USART_RXCIF_bm 0x80 /* Receive Interrupt Flag bit mask. */ -#define USART_RXCIF_bp 7 /* Receive Interrupt Flag bit position. */ - -#define USART_TXCIF_bm 0x40 /* Transmit Interrupt Flag bit mask. */ -#define USART_TXCIF_bp 6 /* Transmit Interrupt Flag bit position. */ - -#define USART_DREIF_bm 0x20 /* Data Register Empty Flag bit mask. */ -#define USART_DREIF_bp 5 /* Data Register Empty Flag bit position. */ - -#define USART_FERR_bm 0x10 /* Frame Error bit mask. */ -#define USART_FERR_bp 4 /* Frame Error bit position. */ - -#define USART_BUFOVF_bm 0x08 /* Buffer Overflow bit mask. */ -#define USART_BUFOVF_bp 3 /* Buffer Overflow bit position. */ - -#define USART_PERR_bm 0x04 /* Parity Error bit mask. */ -#define USART_PERR_bp 2 /* Parity Error bit position. */ - -#define USART_RXB8_bm 0x01 /* Receive Bit 8 bit mask. */ -#define USART_RXB8_bp 0 /* Receive Bit 8 bit position. */ - - -/* USART.CTRLA bit masks and bit positions */ -#define USART_RXCINTLVL_gm 0x30 /* Receive Interrupt Level group mask. */ -#define USART_RXCINTLVL_gp 4 /* Receive Interrupt Level group position. */ -#define USART_RXCINTLVL0_bm (1<<4) /* Receive Interrupt Level bit 0 mask. */ -#define USART_RXCINTLVL0_bp 4 /* Receive Interrupt Level bit 0 position. */ -#define USART_RXCINTLVL1_bm (1<<5) /* Receive Interrupt Level bit 1 mask. */ -#define USART_RXCINTLVL1_bp 5 /* Receive Interrupt Level bit 1 position. */ - -#define USART_TXCINTLVL_gm 0x0C /* Transmit Interrupt Level group mask. */ -#define USART_TXCINTLVL_gp 2 /* Transmit Interrupt Level group position. */ -#define USART_TXCINTLVL0_bm (1<<2) /* Transmit Interrupt Level bit 0 mask. */ -#define USART_TXCINTLVL0_bp 2 /* Transmit Interrupt Level bit 0 position. */ -#define USART_TXCINTLVL1_bm (1<<3) /* Transmit Interrupt Level bit 1 mask. */ -#define USART_TXCINTLVL1_bp 3 /* Transmit Interrupt Level bit 1 position. */ - -#define USART_DREINTLVL_gm 0x03 /* Data Register Empty Interrupt Level group mask. */ -#define USART_DREINTLVL_gp 0 /* Data Register Empty Interrupt Level group position. */ -#define USART_DREINTLVL0_bm (1<<0) /* Data Register Empty Interrupt Level bit 0 mask. */ -#define USART_DREINTLVL0_bp 0 /* Data Register Empty Interrupt Level bit 0 position. */ -#define USART_DREINTLVL1_bm (1<<1) /* Data Register Empty Interrupt Level bit 1 mask. */ -#define USART_DREINTLVL1_bp 1 /* Data Register Empty Interrupt Level bit 1 position. */ - - -/* USART.CTRLB bit masks and bit positions */ -#define USART_RXEN_bm 0x10 /* Receiver Enable bit mask. */ -#define USART_RXEN_bp 4 /* Receiver Enable bit position. */ - -#define USART_TXEN_bm 0x08 /* Transmitter Enable bit mask. */ -#define USART_TXEN_bp 3 /* Transmitter Enable bit position. */ - -#define USART_CLK2X_bm 0x04 /* Double transmission speed bit mask. */ -#define USART_CLK2X_bp 2 /* Double transmission speed bit position. */ - -#define USART_MPCM_bm 0x02 /* Multi-processor Communication Mode bit mask. */ -#define USART_MPCM_bp 1 /* Multi-processor Communication Mode bit position. */ - -#define USART_TXB8_bm 0x01 /* Transmit bit 8 bit mask. */ -#define USART_TXB8_bp 0 /* Transmit bit 8 bit position. */ - - -/* USART.CTRLC bit masks and bit positions */ -#define USART_CMODE_gm 0xC0 /* Communication Mode group mask. */ -#define USART_CMODE_gp 6 /* Communication Mode group position. */ -#define USART_CMODE0_bm (1<<6) /* Communication Mode bit 0 mask. */ -#define USART_CMODE0_bp 6 /* Communication Mode bit 0 position. */ -#define USART_CMODE1_bm (1<<7) /* Communication Mode bit 1 mask. */ -#define USART_CMODE1_bp 7 /* Communication Mode bit 1 position. */ - -#define USART_PMODE_gm 0x30 /* Parity Mode group mask. */ -#define USART_PMODE_gp 4 /* Parity Mode group position. */ -#define USART_PMODE0_bm (1<<4) /* Parity Mode bit 0 mask. */ -#define USART_PMODE0_bp 4 /* Parity Mode bit 0 position. */ -#define USART_PMODE1_bm (1<<5) /* Parity Mode bit 1 mask. */ -#define USART_PMODE1_bp 5 /* Parity Mode bit 1 position. */ - -#define USART_SBMODE_bm 0x08 /* Stop Bit Mode bit mask. */ -#define USART_SBMODE_bp 3 /* Stop Bit Mode bit position. */ - -#define USART_CHSIZE_gm 0x07 /* Character Size group mask. */ -#define USART_CHSIZE_gp 0 /* Character Size group position. */ -#define USART_CHSIZE0_bm (1<<0) /* Character Size bit 0 mask. */ -#define USART_CHSIZE0_bp 0 /* Character Size bit 0 position. */ -#define USART_CHSIZE1_bm (1<<1) /* Character Size bit 1 mask. */ -#define USART_CHSIZE1_bp 1 /* Character Size bit 1 position. */ -#define USART_CHSIZE2_bm (1<<2) /* Character Size bit 2 mask. */ -#define USART_CHSIZE2_bp 2 /* Character Size bit 2 position. */ - - -/* USART.BAUDCTRLA bit masks and bit positions */ -#define USART_BSEL_gm 0xFF /* Baud Rate Selection Bits [7:0] group mask. */ -#define USART_BSEL_gp 0 /* Baud Rate Selection Bits [7:0] group position. */ -#define USART_BSEL0_bm (1<<0) /* Baud Rate Selection Bits [7:0] bit 0 mask. */ -#define USART_BSEL0_bp 0 /* Baud Rate Selection Bits [7:0] bit 0 position. */ -#define USART_BSEL1_bm (1<<1) /* Baud Rate Selection Bits [7:0] bit 1 mask. */ -#define USART_BSEL1_bp 1 /* Baud Rate Selection Bits [7:0] bit 1 position. */ -#define USART_BSEL2_bm (1<<2) /* Baud Rate Selection Bits [7:0] bit 2 mask. */ -#define USART_BSEL2_bp 2 /* Baud Rate Selection Bits [7:0] bit 2 position. */ -#define USART_BSEL3_bm (1<<3) /* Baud Rate Selection Bits [7:0] bit 3 mask. */ -#define USART_BSEL3_bp 3 /* Baud Rate Selection Bits [7:0] bit 3 position. */ -#define USART_BSEL4_bm (1<<4) /* Baud Rate Selection Bits [7:0] bit 4 mask. */ -#define USART_BSEL4_bp 4 /* Baud Rate Selection Bits [7:0] bit 4 position. */ -#define USART_BSEL5_bm (1<<5) /* Baud Rate Selection Bits [7:0] bit 5 mask. */ -#define USART_BSEL5_bp 5 /* Baud Rate Selection Bits [7:0] bit 5 position. */ -#define USART_BSEL6_bm (1<<6) /* Baud Rate Selection Bits [7:0] bit 6 mask. */ -#define USART_BSEL6_bp 6 /* Baud Rate Selection Bits [7:0] bit 6 position. */ -#define USART_BSEL7_bm (1<<7) /* Baud Rate Selection Bits [7:0] bit 7 mask. */ -#define USART_BSEL7_bp 7 /* Baud Rate Selection Bits [7:0] bit 7 position. */ - - -/* USART.BAUDCTRLB bit masks and bit positions */ -#define USART_BSCALE_gm 0xF0 /* Baud Rate Scale group mask. */ -#define USART_BSCALE_gp 4 /* Baud Rate Scale group position. */ -#define USART_BSCALE0_bm (1<<4) /* Baud Rate Scale bit 0 mask. */ -#define USART_BSCALE0_bp 4 /* Baud Rate Scale bit 0 position. */ -#define USART_BSCALE1_bm (1<<5) /* Baud Rate Scale bit 1 mask. */ -#define USART_BSCALE1_bp 5 /* Baud Rate Scale bit 1 position. */ -#define USART_BSCALE2_bm (1<<6) /* Baud Rate Scale bit 2 mask. */ -#define USART_BSCALE2_bp 6 /* Baud Rate Scale bit 2 position. */ -#define USART_BSCALE3_bm (1<<7) /* Baud Rate Scale bit 3 mask. */ -#define USART_BSCALE3_bp 7 /* Baud Rate Scale bit 3 position. */ - -/* USART_BSEL_gm Predefined. */ -/* USART_BSEL_gp Predefined. */ -/* USART_BSEL0_bm Predefined. */ -/* USART_BSEL0_bp Predefined. */ -/* USART_BSEL1_bm Predefined. */ -/* USART_BSEL1_bp Predefined. */ -/* USART_BSEL2_bm Predefined. */ -/* USART_BSEL2_bp Predefined. */ -/* USART_BSEL3_bm Predefined. */ -/* USART_BSEL3_bp Predefined. */ - - -/* SPI - Serial Peripheral Interface */ -/* SPI.CTRL bit masks and bit positions */ -#define SPI_CLK2X_bm 0x80 /* Enable Double Speed bit mask. */ -#define SPI_CLK2X_bp 7 /* Enable Double Speed bit position. */ - -#define SPI_ENABLE_bm 0x40 /* Enable Module bit mask. */ -#define SPI_ENABLE_bp 6 /* Enable Module bit position. */ - -#define SPI_DORD_bm 0x20 /* Data Order Setting bit mask. */ -#define SPI_DORD_bp 5 /* Data Order Setting bit position. */ - -#define SPI_MASTER_bm 0x10 /* Master Operation Enable bit mask. */ -#define SPI_MASTER_bp 4 /* Master Operation Enable bit position. */ - -#define SPI_MODE_gm 0x0C /* SPI Mode group mask. */ -#define SPI_MODE_gp 2 /* SPI Mode group position. */ -#define SPI_MODE0_bm (1<<2) /* SPI Mode bit 0 mask. */ -#define SPI_MODE0_bp 2 /* SPI Mode bit 0 position. */ -#define SPI_MODE1_bm (1<<3) /* SPI Mode bit 1 mask. */ -#define SPI_MODE1_bp 3 /* SPI Mode bit 1 position. */ - -#define SPI_PRESCALER_gm 0x03 /* Prescaler group mask. */ -#define SPI_PRESCALER_gp 0 /* Prescaler group position. */ -#define SPI_PRESCALER0_bm (1<<0) /* Prescaler bit 0 mask. */ -#define SPI_PRESCALER0_bp 0 /* Prescaler bit 0 position. */ -#define SPI_PRESCALER1_bm (1<<1) /* Prescaler bit 1 mask. */ -#define SPI_PRESCALER1_bp 1 /* Prescaler bit 1 position. */ - - -/* SPI.INTCTRL bit masks and bit positions */ -#define SPI_INTLVL_gm 0x03 /* Interrupt level group mask. */ -#define SPI_INTLVL_gp 0 /* Interrupt level group position. */ -#define SPI_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */ -#define SPI_INTLVL0_bp 0 /* Interrupt level bit 0 position. */ -#define SPI_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */ -#define SPI_INTLVL1_bp 1 /* Interrupt level bit 1 position. */ - - -/* SPI.STATUS bit masks and bit positions */ -#define SPI_IF_bm 0x80 /* Interrupt Flag bit mask. */ -#define SPI_IF_bp 7 /* Interrupt Flag bit position. */ - -#define SPI_WRCOL_bm 0x40 /* Write Collision bit mask. */ -#define SPI_WRCOL_bp 6 /* Write Collision bit position. */ - - -/* IRCOM - IR Communication Module */ -/* IRCOM.CTRL bit masks and bit positions */ -#define IRCOM_EVSEL_gm 0x0F /* Event Channel Select group mask. */ -#define IRCOM_EVSEL_gp 0 /* Event Channel Select group position. */ -#define IRCOM_EVSEL0_bm (1<<0) /* Event Channel Select bit 0 mask. */ -#define IRCOM_EVSEL0_bp 0 /* Event Channel Select bit 0 position. */ -#define IRCOM_EVSEL1_bm (1<<1) /* Event Channel Select bit 1 mask. */ -#define IRCOM_EVSEL1_bp 1 /* Event Channel Select bit 1 position. */ -#define IRCOM_EVSEL2_bm (1<<2) /* Event Channel Select bit 2 mask. */ -#define IRCOM_EVSEL2_bp 2 /* Event Channel Select bit 2 position. */ -#define IRCOM_EVSEL3_bm (1<<3) /* Event Channel Select bit 3 mask. */ -#define IRCOM_EVSEL3_bp 3 /* Event Channel Select bit 3 position. */ - - - -// Generic Port Pins - -#define PIN0_bm 0x01 -#define PIN0_bp 0 -#define PIN1_bm 0x02 -#define PIN1_bp 1 -#define PIN2_bm 0x04 -#define PIN2_bp 2 -#define PIN3_bm 0x08 -#define PIN3_bp 3 -#define PIN4_bm 0x10 -#define PIN4_bp 4 -#define PIN5_bm 0x20 -#define PIN5_bp 5 -#define PIN6_bm 0x40 -#define PIN6_bp 6 -#define PIN7_bm 0x80 -#define PIN7_bp 7 - - -/* ========== Interrupt Vector Definitions ========== */ -/* Vector 0 is the reset vector */ - -/* OSC interrupt vectors */ -#define OSC_XOSCF_vect_num 1 -#define OSC_XOSCF_vect _VECTOR(1) /* External Oscillator Failure Interrupt (NMI) */ - -/* PORTC interrupt vectors */ -#define PORTC_INT0_vect_num 2 -#define PORTC_INT0_vect _VECTOR(2) /* External Interrupt 0 */ -#define PORTC_INT1_vect_num 3 -#define PORTC_INT1_vect _VECTOR(3) /* External Interrupt 1 */ - -/* PORTR interrupt vectors */ -#define PORTR_INT0_vect_num 4 -#define PORTR_INT0_vect _VECTOR(4) /* External Interrupt 0 */ -#define PORTR_INT1_vect_num 5 -#define PORTR_INT1_vect _VECTOR(5) /* External Interrupt 1 */ - -/* RTC interrupt vectors */ -#define RTC_OVF_vect_num 10 -#define RTC_OVF_vect _VECTOR(10) /* Overflow Interrupt */ -#define RTC_COMP_vect_num 11 -#define RTC_COMP_vect _VECTOR(11) /* Compare Interrupt */ - -/* TWIC interrupt vectors */ -#define TWIC_TWIS_vect_num 12 -#define TWIC_TWIS_vect _VECTOR(12) /* TWI Slave Interrupt */ -#define TWIC_TWIM_vect_num 13 -#define TWIC_TWIM_vect _VECTOR(13) /* TWI Master Interrupt */ - -/* TCC0 interrupt vectors */ -#define TCC0_OVF_vect_num 14 -#define TCC0_OVF_vect _VECTOR(14) /* Overflow Interrupt */ -#define TCC0_ERR_vect_num 15 -#define TCC0_ERR_vect _VECTOR(15) /* Error Interrupt */ -#define TCC0_CCA_vect_num 16 -#define TCC0_CCA_vect _VECTOR(16) /* Compare or Capture A Interrupt */ -#define TCC0_CCB_vect_num 17 -#define TCC0_CCB_vect _VECTOR(17) /* Compare or Capture B Interrupt */ -#define TCC0_CCC_vect_num 18 -#define TCC0_CCC_vect _VECTOR(18) /* Compare or Capture C Interrupt */ -#define TCC0_CCD_vect_num 19 -#define TCC0_CCD_vect _VECTOR(19) /* Compare or Capture D Interrupt */ - -/* TCC1 interrupt vectors */ -#define TCC1_OVF_vect_num 20 -#define TCC1_OVF_vect _VECTOR(20) /* Overflow Interrupt */ -#define TCC1_ERR_vect_num 21 -#define TCC1_ERR_vect _VECTOR(21) /* Error Interrupt */ -#define TCC1_CCA_vect_num 22 -#define TCC1_CCA_vect _VECTOR(22) /* Compare or Capture A Interrupt */ -#define TCC1_CCB_vect_num 23 -#define TCC1_CCB_vect _VECTOR(23) /* Compare or Capture B Interrupt */ - -/* SPIC interrupt vectors */ -#define SPIC_INT_vect_num 24 -#define SPIC_INT_vect _VECTOR(24) /* SPI Interrupt */ - -/* USARTC0 interrupt vectors */ -#define USARTC0_RXC_vect_num 25 -#define USARTC0_RXC_vect _VECTOR(25) /* Reception Complete Interrupt */ -#define USARTC0_DRE_vect_num 26 -#define USARTC0_DRE_vect _VECTOR(26) /* Data Register Empty Interrupt */ -#define USARTC0_TXC_vect_num 27 -#define USARTC0_TXC_vect _VECTOR(27) /* Transmission Complete Interrupt */ - -/* NVM interrupt vectors */ -#define NVM_EE_vect_num 32 -#define NVM_EE_vect _VECTOR(32) /* EE Interrupt */ -#define NVM_SPM_vect_num 33 -#define NVM_SPM_vect _VECTOR(33) /* SPM Interrupt */ - -/* PORTB interrupt vectors */ -#define PORTB_INT0_vect_num 34 -#define PORTB_INT0_vect _VECTOR(34) /* External Interrupt 0 */ -#define PORTB_INT1_vect_num 35 -#define PORTB_INT1_vect _VECTOR(35) /* External Interrupt 1 */ - -/* PORTE interrupt vectors */ -#define PORTE_INT0_vect_num 43 -#define PORTE_INT0_vect _VECTOR(43) /* External Interrupt 0 */ -#define PORTE_INT1_vect_num 44 -#define PORTE_INT1_vect _VECTOR(44) /* External Interrupt 1 */ - -/* TWIE interrupt vectors */ -#define TWIE_TWIS_vect_num 45 -#define TWIE_TWIS_vect _VECTOR(45) /* TWI Slave Interrupt */ -#define TWIE_TWIM_vect_num 46 -#define TWIE_TWIM_vect _VECTOR(46) /* TWI Master Interrupt */ - -/* TCE0 interrupt vectors */ -#define TCE0_OVF_vect_num 47 -#define TCE0_OVF_vect _VECTOR(47) /* Overflow Interrupt */ -#define TCE0_ERR_vect_num 48 -#define TCE0_ERR_vect _VECTOR(48) /* Error Interrupt */ -#define TCE0_CCA_vect_num 49 -#define TCE0_CCA_vect _VECTOR(49) /* Compare or Capture A Interrupt */ -#define TCE0_CCB_vect_num 50 -#define TCE0_CCB_vect _VECTOR(50) /* Compare or Capture B Interrupt */ -#define TCE0_CCC_vect_num 51 -#define TCE0_CCC_vect _VECTOR(51) /* Compare or Capture C Interrupt */ -#define TCE0_CCD_vect_num 52 -#define TCE0_CCD_vect _VECTOR(52) /* Compare or Capture D Interrupt */ - -/* PORTD interrupt vectors */ -#define PORTD_INT0_vect_num 64 -#define PORTD_INT0_vect _VECTOR(64) /* External Interrupt 0 */ -#define PORTD_INT1_vect_num 65 -#define PORTD_INT1_vect _VECTOR(65) /* External Interrupt 1 */ - -/* PORTA interrupt vectors */ -#define PORTA_INT0_vect_num 66 -#define PORTA_INT0_vect _VECTOR(66) /* External Interrupt 0 */ -#define PORTA_INT1_vect_num 67 -#define PORTA_INT1_vect _VECTOR(67) /* External Interrupt 1 */ - -/* ACA interrupt vectors */ -#define ACA_AC0_vect_num 68 -#define ACA_AC0_vect _VECTOR(68) /* AC0 Interrupt */ -#define ACA_AC1_vect_num 69 -#define ACA_AC1_vect _VECTOR(69) /* AC1 Interrupt */ -#define ACA_ACW_vect_num 70 -#define ACA_ACW_vect _VECTOR(70) /* ACW Window Mode Interrupt */ - -/* ADCA interrupt vectors */ -#define ADCA_CH0_vect_num 71 -#define ADCA_CH0_vect _VECTOR(71) /* Interrupt 0 */ - -/* TCD0 interrupt vectors */ -#define TCD0_OVF_vect_num 77 -#define TCD0_OVF_vect _VECTOR(77) /* Overflow Interrupt */ -#define TCD0_ERR_vect_num 78 -#define TCD0_ERR_vect _VECTOR(78) /* Error Interrupt */ -#define TCD0_CCA_vect_num 79 -#define TCD0_CCA_vect _VECTOR(79) /* Compare or Capture A Interrupt */ -#define TCD0_CCB_vect_num 80 -#define TCD0_CCB_vect _VECTOR(80) /* Compare or Capture B Interrupt */ -#define TCD0_CCC_vect_num 81 -#define TCD0_CCC_vect _VECTOR(81) /* Compare or Capture C Interrupt */ -#define TCD0_CCD_vect_num 82 -#define TCD0_CCD_vect _VECTOR(82) /* Compare or Capture D Interrupt */ - -/* SPID interrupt vectors */ -#define SPID_INT_vect_num 87 -#define SPID_INT_vect _VECTOR(87) /* SPI Interrupt */ - -/* USARTD0 interrupt vectors */ -#define USARTD0_RXC_vect_num 88 -#define USARTD0_RXC_vect _VECTOR(88) /* Reception Complete Interrupt */ -#define USARTD0_DRE_vect_num 89 -#define USARTD0_DRE_vect _VECTOR(89) /* Data Register Empty Interrupt */ -#define USARTD0_TXC_vect_num 90 -#define USARTD0_TXC_vect _VECTOR(90) /* Transmission Complete Interrupt */ - - -#define _VECTOR_SIZE 4 /* Size of individual vector. */ -#define _VECTORS_SIZE (91 * _VECTOR_SIZE) - - -/* ========== Constants ========== */ - -#define PROGMEM_START (0x0000) -#define PROGMEM_SIZE (36864) -#define PROGMEM_PAGE_SIZE (256) -#define PROGMEM_END (PROGMEM_START + PROGMEM_SIZE - 1) - -#define APP_SECTION_START (0x0000) -#define APP_SECTION_SIZE (32768) -#define APP_SECTION_PAGE_SIZE (256) -#define APP_SECTION_END (APP_SECTION_START + APP_SECTION_SIZE - 1) - -#define APPTABLE_SECTION_START (0x7000) -#define APPTABLE_SECTION_SIZE (4096) -#define APPTABLE_SECTION_PAGE_SIZE (256) -#define APPTABLE_SECTION_END (APPTABLE_SECTION_START + APPTABLE_SECTION_SIZE - 1) - -#define BOOT_SECTION_START (0x8000) -#define BOOT_SECTION_SIZE (4096) -#define BOOT_SECTION_PAGE_SIZE (256) -#define BOOT_SECTION_END (BOOT_SECTION_START + BOOT_SECTION_SIZE - 1) - -#define DATAMEM_START (0x0000) -#define DATAMEM_SIZE (12288) -#define DATAMEM_PAGE_SIZE (0) -#define DATAMEM_END (DATAMEM_START + DATAMEM_SIZE - 1) - -#define IO_START (0x0000) -#define IO_SIZE (4096) -#define IO_PAGE_SIZE (0) -#define IO_END (IO_START + IO_SIZE - 1) - -#define MAPPED_EEPROM_START (0x1000) -#define MAPPED_EEPROM_SIZE (1024) -#define MAPPED_EEPROM_PAGE_SIZE (0) -#define MAPPED_EEPROM_END (MAPPED_EEPROM_START + MAPPED_EEPROM_SIZE - 1) - -#define INTERNAL_SRAM_START (0x2000) -#define INTERNAL_SRAM_SIZE (4096) -#define INTERNAL_SRAM_PAGE_SIZE (0) -#define INTERNAL_SRAM_END (INTERNAL_SRAM_START + INTERNAL_SRAM_SIZE - 1) - -#define EEPROM_START (0x0000) -#define EEPROM_SIZE (1024) -#define EEPROM_PAGE_SIZE (32) -#define EEPROM_END (EEPROM_START + EEPROM_SIZE - 1) - -#define FUSE_START (0x0000) -#define FUSE_SIZE (6) -#define FUSE_PAGE_SIZE (0) -#define FUSE_END (FUSE_START + FUSE_SIZE - 1) - -#define LOCKBIT_START (0x0000) -#define LOCKBIT_SIZE (1) -#define LOCKBIT_PAGE_SIZE (0) -#define LOCKBIT_END (LOCKBIT_START + LOCKBIT_SIZE - 1) - -#define SIGNATURES_START (0x0000) -#define SIGNATURES_SIZE (3) -#define SIGNATURES_PAGE_SIZE (0) -#define SIGNATURES_END (SIGNATURES_START + SIGNATURES_SIZE - 1) - -#define USER_SIGNATURES_START (0x0000) -#define USER_SIGNATURES_SIZE (256) -#define USER_SIGNATURES_PAGE_SIZE (0) -#define USER_SIGNATURES_END (USER_SIGNATURES_START + USER_SIGNATURES_SIZE - 1) - -#define PROD_SIGNATURES_START (0x0000) -#define PROD_SIGNATURES_SIZE (52) -#define PROD_SIGNATURES_PAGE_SIZE (0) -#define PROD_SIGNATURES_END (PROD_SIGNATURES_START + PROD_SIGNATURES_SIZE - 1) - -#define FLASHEND PROGMEM_END -#define SPM_PAGESIZE PROGMEM_PAGE_SIZE -#define RAMSTART INTERNAL_SRAM_START -#define RAMSIZE INTERNAL_SRAM_SIZE -#define RAMEND INTERNAL_SRAM_END -#define XRAMSTART EXTERNAL_SRAM_START -#define XRAMSIZE EXTERNAL_SRAM_SIZE -#define XRAMEND INTERNAL_SRAM_END -#define E2END EEPROM_END -#define E2PAGESIZE EEPROM_PAGE_SIZE - - -/* ========== Fuses ========== */ -#define FUSE_MEMORY_SIZE 6 - -/* Fuse Byte 0 */ -#define FUSE_USERID0 (unsigned char)~_BV(0) /* User ID Bit 0 */ -#define FUSE_USERID1 (unsigned char)~_BV(1) /* User ID Bit 1 */ -#define FUSE_USERID2 (unsigned char)~_BV(2) /* User ID Bit 2 */ -#define FUSE_USERID3 (unsigned char)~_BV(3) /* User ID Bit 3 */ -#define FUSE_USERID4 (unsigned char)~_BV(4) /* User ID Bit 4 */ -#define FUSE_USERID5 (unsigned char)~_BV(5) /* User ID Bit 5 */ -#define FUSE_USERID6 (unsigned char)~_BV(6) /* User ID Bit 6 */ -#define FUSE_USERID7 (unsigned char)~_BV(7) /* User ID Bit 7 */ -#define FUSE0_DEFAULT (0xFF) - -/* Fuse Byte 1 */ -#define FUSE_WDP0 (unsigned char)~_BV(0) /* Watchdog Timeout Period Bit 0 */ -#define FUSE_WDP1 (unsigned char)~_BV(1) /* Watchdog Timeout Period Bit 1 */ -#define FUSE_WDP2 (unsigned char)~_BV(2) /* Watchdog Timeout Period Bit 2 */ -#define FUSE_WDP3 (unsigned char)~_BV(3) /* Watchdog Timeout Period Bit 3 */ -#define FUSE_WDWP0 (unsigned char)~_BV(4) /* Watchdog Window Timeout Period Bit 0 */ -#define FUSE_WDWP1 (unsigned char)~_BV(5) /* Watchdog Window Timeout Period Bit 1 */ -#define FUSE_WDWP2 (unsigned char)~_BV(6) /* Watchdog Window Timeout Period Bit 2 */ -#define FUSE_WDWP3 (unsigned char)~_BV(7) /* Watchdog Window Timeout Period Bit 3 */ -#define FUSE1_DEFAULT (0xFF) - -/* Fuse Byte 2 */ -#define FUSE_BODPD0 (unsigned char)~_BV(0) /* BOD Operation in Power-Down Mode Bit 0 */ -#define FUSE_BODPD1 (unsigned char)~_BV(1) /* BOD Operation in Power-Down Mode Bit 1 */ -#define FUSE_BOOTRST (unsigned char)~_BV(6) /* Boot Loader Section Reset Vector */ -#define FUSE_DVSDON (unsigned char)~_BV(7) /* Spike Detector Enable */ -#define FUSE2_DEFAULT (0xFF) - -/* Fuse Byte 3 Reserved */ - -/* Fuse Byte 4 */ -#define FUSE_WDLOCK (unsigned char)~_BV(1) /* Watchdog Timer Lock */ -#define FUSE_SUT0 (unsigned char)~_BV(2) /* Start-up Time Bit 0 */ -#define FUSE_SUT1 (unsigned char)~_BV(3) /* Start-up Time Bit 1 */ -#define FUSE4_DEFAULT (0xFF) - -/* Fuse Byte 5 */ -#define FUSE_BODLVL0 (unsigned char)~_BV(0) /* Brown Out Detection Voltage Level Bit 0 */ -#define FUSE_BODLVL1 (unsigned char)~_BV(1) /* Brown Out Detection Voltage Level Bit 1 */ -#define FUSE_BODLVL2 (unsigned char)~_BV(2) /* Brown Out Detection Voltage Level Bit 2 */ -#define FUSE_EESAVE (unsigned char)~_BV(3) /* Preserve EEPROM Through Chip Erase */ -#define FUSE_BODACT0 (unsigned char)~_BV(4) /* BOD Operation in Active Mode Bit 0 */ -#define FUSE_BODACT1 (unsigned char)~_BV(5) /* BOD Operation in Active Mode Bit 1 */ -#define FUSE5_DEFAULT (0xFF) - - -/* ========== Lock Bits ========== */ -#define __LOCK_BITS_EXIST -#define __BOOT_LOCK_APPLICATION_TABLE_BITS_EXIST -#define __BOOT_LOCK_APPLICATION_BITS_EXIST -#define __BOOT_LOCK_BOOT_BITS_EXIST - - -/* ========== Signature ========== */ -#define SIGNATURE_0 0x1E -#define SIGNATURE_1 0x95 -#define SIGNATURE_2 0x42 - -/* ========== Power Reduction Condition Definitions ========== */ - -/* PR.PRGEN */ -#define __AVR_HAVE_PRGEN (PR_RTC_bm|PR_EVSYS_bm) -#define __AVR_HAVE_PRGEN_RTC -#define __AVR_HAVE_PRGEN_EVSYS - -/* PR.PRPA */ -#define __AVR_HAVE_PRPA (PR_ADC_bm|PR_AC_bm) -#define __AVR_HAVE_PRPA_ADC -#define __AVR_HAVE_PRPA_AC - -/* PR.PRPC */ -#define __AVR_HAVE_PRPC (PR_TWI_bm|PR_USART0_bm|PR_SPI_bm|PR_HIRES_bm|PR_TC1_bm|PR_TC0_bm) -#define __AVR_HAVE_PRPC_TWI -#define __AVR_HAVE_PRPC_USART0 -#define __AVR_HAVE_PRPC_SPI -#define __AVR_HAVE_PRPC_HIRES -#define __AVR_HAVE_PRPC_TC1 -#define __AVR_HAVE_PRPC_TC0 - -/* PR.PRPD */ -#define __AVR_HAVE_PRPD (PR_USART0_bm|PR_SPI_bm|PR_TC0_bm) -#define __AVR_HAVE_PRPD_USART0 -#define __AVR_HAVE_PRPD_SPI -#define __AVR_HAVE_PRPD_TC0 - -/* PR.PRPE */ -#define __AVR_HAVE_PRPE (PR_TWI_bm|PR_USART0_bm|PR_TC0_bm) -#define __AVR_HAVE_PRPE_TWI -#define __AVR_HAVE_PRPE_USART0 -#define __AVR_HAVE_PRPE_TC0 - -/* PR.PRPF */ -#define __AVR_HAVE_PRPF (PR_USART0_bm|PR_TC0_bm) -#define __AVR_HAVE_PRPF_USART0 -#define __AVR_HAVE_PRPF_TC0 - - -#endif /* _AVR_ATxmega32D4_H_ */ - diff --git a/arduino/hardware/tools/avr/avr/include/avr/iox32e5.h b/arduino/hardware/tools/avr/avr/include/avr/iox32e5.h deleted file mode 100644 index dbcf803..0000000 --- a/arduino/hardware/tools/avr/avr/include/avr/iox32e5.h +++ /dev/null @@ -1,7699 +0,0 @@ -/***************************************************************************** - * - * Copyright (C) 2015 Atmel Corporation - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * - * * Neither the name of the copyright holders nor the names of - * contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - ****************************************************************************/ - - -#ifndef _AVR_IO_H_ -# error "Include instead of this file." -#endif - -#ifndef _AVR_IOXXX_H_ -# define _AVR_IOXXX_H_ "iox32e5.h" -#else -# error "Attempt to include more than one file." -#endif - -#ifndef _AVR_ATXMEGA32E5_H_INCLUDED -#define _AVR_ATXMEGA32E5_H_INCLUDED - -/* Ungrouped common registers */ -#define GPIOR0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ -#define GPIOR1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ -#define GPIOR2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ -#define GPIOR3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ - -/* Deprecated */ -#define GPIO0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ -#define GPIO1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ -#define GPIO2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ -#define GPIO3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ - -#define CCP _SFR_MEM8(0x0034) /* Configuration Change Protection */ -#define RAMPD _SFR_MEM8(0x0038) /* Ramp D */ -#define RAMPX _SFR_MEM8(0x0039) /* Ramp X */ -#define RAMPY _SFR_MEM8(0x003A) /* Ramp Y */ -#define RAMPZ _SFR_MEM8(0x003B) /* Ramp Z */ -#define EIND _SFR_MEM8(0x003C) /* Extended Indirect Jump */ -#define SPL _SFR_MEM8(0x003D) /* Stack Pointer Low */ -#define SPH _SFR_MEM8(0x003E) /* Stack Pointer High */ -#define SREG _SFR_MEM8(0x003F) /* Status Register */ - -/* C Language Only */ -#if !defined (__ASSEMBLER__) - -#include - -typedef volatile uint8_t register8_t; -typedef volatile uint16_t register16_t; -typedef volatile uint32_t register32_t; - - -#ifdef _WORDREGISTER -#undef _WORDREGISTER -#endif -#define _WORDREGISTER(regname) \ - __extension__ union \ - { \ - register16_t regname; \ - struct \ - { \ - register8_t regname ## L; \ - register8_t regname ## H; \ - }; \ - } - -#ifdef _DWORDREGISTER -#undef _DWORDREGISTER -#endif -#define _DWORDREGISTER(regname) \ - __extension__ union \ - { \ - register32_t regname; \ - struct \ - { \ - register8_t regname ## 0; \ - register8_t regname ## 1; \ - register8_t regname ## 2; \ - register8_t regname ## 3; \ - }; \ - } - - -/* -========================================================================== -IO Module Structures -========================================================================== -*/ - - -/* --------------------------------------------------------------------------- -VPORT - Virtual Ports --------------------------------------------------------------------------- -*/ - -/* Virtual Port */ -typedef struct VPORT_struct -{ - register8_t DIR; /* I/O Port Data Direction */ - register8_t OUT; /* I/O Port Output */ - register8_t IN; /* I/O Port Input */ - register8_t INTFLAGS; /* Interrupt Flag Register */ -} VPORT_t; - - -/* --------------------------------------------------------------------------- -XOCD - On-Chip Debug System --------------------------------------------------------------------------- -*/ - -/* On-Chip Debug System */ -typedef struct OCD_struct -{ - register8_t OCDR0; /* OCD Register 0 */ - register8_t OCDR1; /* OCD Register 1 */ -} OCD_t; - - -/* --------------------------------------------------------------------------- -CPU - CPU --------------------------------------------------------------------------- -*/ - -/* CCP signatures */ -typedef enum CCP_enum -{ - CCP_SPM_gc = (0x9D<<0), /* SPM Instruction Protection */ - CCP_IOREG_gc = (0xD8<<0), /* IO Register Protection */ -} CCP_t; - - -/* --------------------------------------------------------------------------- -CLK - Clock System --------------------------------------------------------------------------- -*/ - -/* Clock System */ -typedef struct CLK_struct -{ - register8_t CTRL; /* Control Register */ - register8_t PSCTRL; /* Prescaler Control Register */ - register8_t LOCK; /* Lock register */ - register8_t RTCCTRL; /* RTC Control Register */ - register8_t reserved_0x04; -} CLK_t; - - -/* Power Reduction */ -typedef struct PR_struct -{ - register8_t PRGEN; /* General Power Reduction */ - register8_t PRPA; /* Power Reduction Port A */ - register8_t reserved_0x02; - register8_t PRPC; /* Power Reduction Port C */ - register8_t PRPD; /* Power Reduction Port D */ - register8_t reserved_0x05; - register8_t reserved_0x06; -} PR_t; - -/* System Clock Selection */ -typedef enum CLK_SCLKSEL_enum -{ - CLK_SCLKSEL_RC2M_gc = (0x00<<0), /* Internal 2 MHz RC Oscillator */ - CLK_SCLKSEL_RC32M_gc = (0x01<<0), /* Internal 32 MHz RC Oscillator */ - CLK_SCLKSEL_RC32K_gc = (0x02<<0), /* Internal 32.768 kHz RC Oscillator */ - CLK_SCLKSEL_XOSC_gc = (0x03<<0), /* External Crystal Oscillator or Clock */ - CLK_SCLKSEL_PLL_gc = (0x04<<0), /* Phase Locked Loop */ - CLK_SCLKSEL_RC8M_gc = (0x05<<0), /* Internal 8 MHz RC Oscillator */ -} CLK_SCLKSEL_t; - -/* Prescaler A Division Factor */ -typedef enum CLK_PSADIV_enum -{ - CLK_PSADIV_1_gc = (0x00<<2), /* Divide by 1 */ - CLK_PSADIV_2_gc = (0x01<<2), /* Divide by 2 */ - CLK_PSADIV_4_gc = (0x03<<2), /* Divide by 4 */ - CLK_PSADIV_8_gc = (0x05<<2), /* Divide by 8 */ - CLK_PSADIV_16_gc = (0x07<<2), /* Divide by 16 */ - CLK_PSADIV_32_gc = (0x09<<2), /* Divide by 32 */ - CLK_PSADIV_64_gc = (0x0B<<2), /* Divide by 64 */ - CLK_PSADIV_128_gc = (0x0D<<2), /* Divide by 128 */ - CLK_PSADIV_256_gc = (0x0F<<2), /* Divide by 256 */ - CLK_PSADIV_512_gc = (0x11<<2), /* Divide by 512 */ - CLK_PSADIV_6_gc = (0x13<<2), /* Divide by 6 */ - CLK_PSADIV_10_gc = (0x15<<2), /* Divide by 10 */ - CLK_PSADIV_12_gc = (0x17<<2), /* Divide by 12 */ - CLK_PSADIV_24_gc = (0x19<<2), /* Divide by 24 */ - CLK_PSADIV_48_gc = (0x1B<<2), /* Divide by 48 */ -} CLK_PSADIV_t; - -/* Prescaler B and C Division Factor */ -typedef enum CLK_PSBCDIV_enum -{ - CLK_PSBCDIV_1_1_gc = (0x00<<0), /* Divide B by 1 and C by 1 */ - CLK_PSBCDIV_1_2_gc = (0x01<<0), /* Divide B by 1 and C by 2 */ - CLK_PSBCDIV_4_1_gc = (0x02<<0), /* Divide B by 4 and C by 1 */ - CLK_PSBCDIV_2_2_gc = (0x03<<0), /* Divide B by 2 and C by 2 */ -} CLK_PSBCDIV_t; - -/* RTC Clock Source */ -typedef enum CLK_RTCSRC_enum -{ - CLK_RTCSRC_ULP_gc = (0x00<<1), /* 1.024 kHz from internal 32kHz ULP */ - CLK_RTCSRC_TOSC_gc = (0x01<<1), /* 1.024 kHz from 32.768 kHz crystal oscillator on TOSC */ - CLK_RTCSRC_RCOSC_gc = (0x02<<1), /* 1.024 kHz from internal 32.768 kHz RC oscillator */ - CLK_RTCSRC_TOSC32_gc = (0x05<<1), /* 32.768 kHz from 32.768 kHz crystal oscillator on TOSC */ - CLK_RTCSRC_RCOSC32_gc = (0x06<<1), /* 32.768 kHz from internal 32.768 kHz RC oscillator */ - CLK_RTCSRC_EXTCLK_gc = (0x07<<1), /* External Clock from TOSC1 */ -} CLK_RTCSRC_t; - - -/* --------------------------------------------------------------------------- -SLEEP - Sleep Controller --------------------------------------------------------------------------- -*/ - -/* Sleep Controller */ -typedef struct SLEEP_struct -{ - register8_t CTRL; /* Control Register */ -} SLEEP_t; - -/* Sleep Mode */ -typedef enum SLEEP_SMODE_enum -{ - SLEEP_SMODE_IDLE_gc = (0x00<<1), /* Idle mode */ - SLEEP_SMODE_PDOWN_gc = (0x02<<1), /* Power-down Mode */ - SLEEP_SMODE_PSAVE_gc = (0x03<<1), /* Power-save Mode */ - SLEEP_SMODE_STDBY_gc = (0x06<<1), /* Standby Mode */ - SLEEP_SMODE_ESTDBY_gc = (0x07<<1), /* Extended Standby Mode */ -} SLEEP_SMODE_t; - - - -#define SLEEP_MODE_IDLE (0x00<<1) -#define SLEEP_MODE_PWR_DOWN (0x02<<1) -#define SLEEP_MODE_PWR_SAVE (0x03<<1) -#define SLEEP_MODE_STANDBY (0x06<<1) -#define SLEEP_MODE_EXT_STANDBY (0x07<<1) -/* --------------------------------------------------------------------------- -OSC - Oscillator --------------------------------------------------------------------------- -*/ - -/* Oscillator */ -typedef struct OSC_struct -{ - register8_t CTRL; /* Control Register */ - register8_t STATUS; /* Status Register */ - register8_t XOSCCTRL; /* External Oscillator Control Register */ - register8_t XOSCFAIL; /* Oscillator Failure Detection Register */ - register8_t RC32KCAL; /* 32.768 kHz Internal Oscillator Calibration Register */ - register8_t PLLCTRL; /* PLL Control Register */ - register8_t DFLLCTRL; /* DFLL Control Register */ - register8_t RC8MCAL; /* Internal 8 MHz RC Oscillator Calibration Register */ -} OSC_t; - -/* Oscillator Frequency Range */ -typedef enum OSC_FRQRANGE_enum -{ - OSC_FRQRANGE_04TO2_gc = (0x00<<6), /* 0.4 - 2 MHz */ - OSC_FRQRANGE_2TO9_gc = (0x01<<6), /* 2 - 9 MHz */ - OSC_FRQRANGE_9TO12_gc = (0x02<<6), /* 9 - 12 MHz */ - OSC_FRQRANGE_12TO16_gc = (0x03<<6), /* 12 - 16 MHz */ -} OSC_FRQRANGE_t; - -/* External Oscillator Selection and Startup Time */ -typedef enum OSC_XOSCSEL_enum -{ - OSC_XOSCSEL_EXTCLK_gc = (0x00<<0), /* External Clock on port R1 - 6 CLK */ - OSC_XOSCSEL_32KHz_gc = (0x02<<0), /* 32.768 kHz TOSC - 32K CLK */ - OSC_XOSCSEL_XTAL_256CLK_gc = (0x03<<0), /* 0.4-16 MHz XTAL - 256 CLK */ - OSC_XOSCSEL_XTAL_1KCLK_gc = (0x07<<0), /* 0.4-16 MHz XTAL - 1K CLK */ - OSC_XOSCSEL_XTAL_16KCLK_gc = (0x0B<<0), /* 0.4-16 MHz XTAL - 16K CLK */ - OSC_XOSCSEL_EXTCLK_C4_gc = (0x14<<0), /* External Clock on port C4 - 6 CLK */ -} OSC_XOSCSEL_t; - -/* PLL Clock Source */ -typedef enum OSC_PLLSRC_enum -{ - OSC_PLLSRC_RC2M_gc = (0x00<<6), /* Internal 2 MHz RC Oscillator */ - OSC_PLLSRC_RC8M_gc = (0x01<<6), /* Internal 8 MHz RC Oscillator */ - OSC_PLLSRC_RC32M_gc = (0x02<<6), /* Internal 32 MHz RC Oscillator */ - OSC_PLLSRC_XOSC_gc = (0x03<<6), /* External Oscillator */ -} OSC_PLLSRC_t; - -/* 32 MHz DFLL Calibration Reference */ -typedef enum OSC_RC32MCREF_enum -{ - OSC_RC32MCREF_RC32K_gc = (0x00<<1), /* Internal 32.768 kHz RC Oscillator */ - OSC_RC32MCREF_XOSC32K_gc = (0x01<<1), /* External 32.768 kHz Crystal Oscillator */ -} OSC_RC32MCREF_t; - - -/* --------------------------------------------------------------------------- -DFLL - DFLL --------------------------------------------------------------------------- -*/ - -/* DFLL */ -typedef struct DFLL_struct -{ - register8_t CTRL; /* Control Register */ - register8_t reserved_0x01; - register8_t CALA; /* Calibration Register A */ - register8_t CALB; /* Calibration Register B */ - register8_t COMP0; /* Oscillator Compare Register 0 */ - register8_t COMP1; /* Oscillator Compare Register 1 */ - register8_t COMP2; /* Oscillator Compare Register 2 */ - register8_t reserved_0x07; -} DFLL_t; - - -/* --------------------------------------------------------------------------- -RST - Reset --------------------------------------------------------------------------- -*/ - -/* Reset */ -typedef struct RST_struct -{ - register8_t STATUS; /* Status Register */ - register8_t CTRL; /* Control Register */ -} RST_t; - - -/* --------------------------------------------------------------------------- -WDT - Watch-Dog Timer --------------------------------------------------------------------------- -*/ - -/* Watch-Dog Timer */ -typedef struct WDT_struct -{ - register8_t CTRL; /* Control */ - register8_t WINCTRL; /* Windowed Mode Control */ - register8_t STATUS; /* Status */ -} WDT_t; - -/* Period setting */ -typedef enum WDT_PER_enum -{ - WDT_PER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ - WDT_PER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ - WDT_PER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ - WDT_PER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ - WDT_PER_128CLK_gc = (0x04<<2), /* 128 cycles (0.128s @ 3.3V) */ - WDT_PER_256CLK_gc = (0x05<<2), /* 256 cycles (0.256s @ 3.3V) */ - WDT_PER_512CLK_gc = (0x06<<2), /* 512 cycles (0.512s @ 3.3V) */ - WDT_PER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ - WDT_PER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ - WDT_PER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ - WDT_PER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ -} WDT_PER_t; - -/* Closed window period */ -typedef enum WDT_WPER_enum -{ - WDT_WPER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ - WDT_WPER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ - WDT_WPER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ - WDT_WPER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ - WDT_WPER_128CLK_gc = (0x04<<2), /* 128 cycles (0.128s @ 3.3V) */ - WDT_WPER_256CLK_gc = (0x05<<2), /* 256 cycles (0.256s @ 3.3V) */ - WDT_WPER_512CLK_gc = (0x06<<2), /* 512 cycles (0.512s @ 3.3V) */ - WDT_WPER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ - WDT_WPER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ - WDT_WPER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ - WDT_WPER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ -} WDT_WPER_t; - - -/* --------------------------------------------------------------------------- -MCU - MCU Control --------------------------------------------------------------------------- -*/ - -/* MCU Control */ -typedef struct MCU_struct -{ - register8_t DEVID0; /* Device ID byte 0 */ - register8_t DEVID1; /* Device ID byte 1 */ - register8_t DEVID2; /* Device ID byte 2 */ - register8_t REVID; /* Revision ID */ - register8_t reserved_0x04; - register8_t reserved_0x05; - register8_t reserved_0x06; - register8_t ANAINIT; /* Analog Startup Delay */ - register8_t EVSYSLOCK; /* Event System Lock */ - register8_t WEXLOCK; /* WEX Lock */ - register8_t FAULTLOCK; /* FAULT Lock */ - register8_t reserved_0x0B; -} MCU_t; - - -/* --------------------------------------------------------------------------- -PMIC - Programmable Multi-level Interrupt Controller --------------------------------------------------------------------------- -*/ - -/* Programmable Multi-level Interrupt Controller */ -typedef struct PMIC_struct -{ - register8_t STATUS; /* Status Register */ - register8_t INTPRI; /* Interrupt Priority */ - register8_t CTRL; /* Control Register */ - register8_t reserved_0x03; - register8_t reserved_0x04; - register8_t reserved_0x05; - register8_t reserved_0x06; - register8_t reserved_0x07; - register8_t reserved_0x08; - register8_t reserved_0x09; - register8_t reserved_0x0A; - register8_t reserved_0x0B; - register8_t reserved_0x0C; - register8_t reserved_0x0D; - register8_t reserved_0x0E; - register8_t reserved_0x0F; -} PMIC_t; - - -/* --------------------------------------------------------------------------- -PORTCFG - Port Configuration --------------------------------------------------------------------------- -*/ - -/* I/O port Configuration */ -typedef struct PORTCFG_struct -{ - register8_t MPCMASK; /* Multi-pin Configuration Mask */ - register8_t reserved_0x01; - register8_t reserved_0x02; - register8_t reserved_0x03; - register8_t CLKOUT; /* Clock Out Register */ - register8_t reserved_0x05; - register8_t ACEVOUT; /* Analog Comparator and Event Out Register */ - register8_t SRLCTRL; /* Slew Rate Limit Control Register */ -} PORTCFG_t; - -/* Clock and Event Output Port */ -typedef enum PORTCFG_CLKEVPIN_enum -{ - PORTCFG_CLKEVPIN_PIN7_gc = (0x00<<7), /* Clock and Event Ouput on PIN 7 */ - PORTCFG_CLKEVPIN_PIN4_gc = (0x01<<7), /* Clock and Event Ouput on PIN 4 */ -} PORTCFG_CLKEVPIN_t; - -/* RTC Clock Output Port */ -typedef enum PORTCFG_RTCCLKOUT_enum -{ - PORTCFG_RTCCLKOUT_OFF_gc = (0x00<<5), /* System Clock Output Disabled */ - PORTCFG_RTCCLKOUT_PC6_gc = (0x01<<5), /* System Clock Output on Port C pin 6 */ - PORTCFG_RTCCLKOUT_PD6_gc = (0x02<<5), /* System Clock Output on Port D pin 6 */ - PORTCFG_RTCCLKOUT_PR0_gc = (0x03<<5), /* System Clock Output on Port R pin 0 */ -} PORTCFG_RTCCLKOUT_t; - -/* Peripheral Clock Output Select */ -typedef enum PORTCFG_CLKOUTSEL_enum -{ - PORTCFG_CLKOUTSEL_CLK1X_gc = (0x00<<2), /* 1x Peripheral Clock Output to pin */ - PORTCFG_CLKOUTSEL_CLK2X_gc = (0x01<<2), /* 2x Peripheral Clock Output to pin */ - PORTCFG_CLKOUTSEL_CLK4X_gc = (0x02<<2), /* 4x Peripheral Clock Output to pin */ -} PORTCFG_CLKOUTSEL_t; - -/* System Clock Output Port */ -typedef enum PORTCFG_CLKOUT_enum -{ - PORTCFG_CLKOUT_OFF_gc = (0x00<<0), /* System Clock Output Disabled */ - PORTCFG_CLKOUT_PC7_gc = (0x01<<0), /* System Clock Output on Port C pin 7 */ - PORTCFG_CLKOUT_PD7_gc = (0x02<<0), /* System Clock Output on Port D pin 7 */ - PORTCFG_CLKOUT_PR0_gc = (0x03<<0), /* System Clock Output on Port R pin 0 */ -} PORTCFG_CLKOUT_t; - -/* Analog Comparator Output Port */ -typedef enum PORTCFG_ACOUT_enum -{ - PORTCFG_ACOUT_PA_gc = (0x00<<6), /* Analog Comparator Outputs on Port A, Pin 6-7 */ - PORTCFG_ACOUT_PC_gc = (0x01<<6), /* Analog Comparator Outputs on Port C, Pin 6-7 */ - PORTCFG_ACOUT_PD_gc = (0x02<<6), /* Analog Comparator Outputs on Port D, Pin 6-7 */ - PORTCFG_ACOUT_PR_gc = (0x03<<6), /* Analog Comparator Outputs on Port R, Pin 0-1 */ -} PORTCFG_ACOUT_t; - -/* Event Output Port */ -typedef enum PORTCFG_EVOUT_enum -{ - PORTCFG_EVOUT_OFF_gc = (0x00<<4), /* Event Output Disabled */ - PORTCFG_EVOUT_PC7_gc = (0x01<<4), /* Event Channel n Output on Port C pin 7 */ - PORTCFG_EVOUT_PD7_gc = (0x02<<4), /* Event Channel n Output on Port D pin 7 */ - PORTCFG_EVOUT_PR0_gc = (0x03<<4), /* Event Channel n Output on Port R pin 0 */ -} PORTCFG_EVOUT_t; - -/* Event Output Select */ -typedef enum PORTCFG_EVOUTSEL_enum -{ - PORTCFG_EVOUTSEL_0_gc = (0x00<<0), /* Event Channel 0 output to pin */ - PORTCFG_EVOUTSEL_1_gc = (0x01<<0), /* Event Channel 1 output to pin */ - PORTCFG_EVOUTSEL_2_gc = (0x02<<0), /* Event Channel 2 output to pin */ - PORTCFG_EVOUTSEL_3_gc = (0x03<<0), /* Event Channel 3 output to pin */ - PORTCFG_EVOUTSEL_4_gc = (0x04<<0), /* Event Channel 4 output to pin */ - PORTCFG_EVOUTSEL_5_gc = (0x05<<0), /* Event Channel 5 output to pin */ - PORTCFG_EVOUTSEL_6_gc = (0x06<<0), /* Event Channel 6 output to pin */ - PORTCFG_EVOUTSEL_7_gc = (0x07<<0), /* Event Channel 7 output to pin */ -} PORTCFG_EVOUTSEL_t; - - -/* --------------------------------------------------------------------------- -CRC - Cyclic Redundancy Checker --------------------------------------------------------------------------- -*/ - -/* Cyclic Redundancy Checker */ -typedef struct CRC_struct -{ - register8_t CTRL; /* Control Register */ - register8_t STATUS; /* Status Register */ - register8_t reserved_0x02; - register8_t DATAIN; /* Data Input */ - register8_t CHECKSUM0; /* Checksum byte 0 */ - register8_t CHECKSUM1; /* Checksum byte 1 */ - register8_t CHECKSUM2; /* Checksum byte 2 */ - register8_t CHECKSUM3; /* Checksum byte 3 */ -} CRC_t; - -/* Reset */ -typedef enum CRC_RESET_enum -{ - CRC_RESET_NO_gc = (0x00<<6), /* No Reset */ - CRC_RESET_RESET0_gc = (0x02<<6), /* Reset CRC with CHECKSUM to all zeros */ - CRC_RESET_RESET1_gc = (0x03<<6), /* Reset CRC with CHECKSUM to all ones */ -} CRC_RESET_t; - -/* Input Source */ -typedef enum CRC_SOURCE_enum -{ - CRC_SOURCE_DISABLE_gc = (0x00<<0), /* Disabled */ - CRC_SOURCE_IO_gc = (0x01<<0), /* I/O Interface */ - CRC_SOURCE_FLASH_gc = (0x02<<0), /* Flash */ - CRC_SOURCE_DMAC0_gc = (0x04<<0), /* DMAC Channel 0 */ - CRC_SOURCE_DMAC1_gc = (0x05<<0), /* DMAC Channel 1 */ - CRC_SOURCE_DMAC2_gc = (0x06<<0), /* DMAC Channel 2 */ - CRC_SOURCE_DMAC3_gc = (0x07<<0), /* DMAC Channel 3 */ -} CRC_SOURCE_t; - - -/* --------------------------------------------------------------------------- -EDMA - Enhanced DMA Controller --------------------------------------------------------------------------- -*/ - -/* EDMA Channel */ -typedef struct EDMA_CH_struct -{ - register8_t CTRLA; /* Channel Control A */ - register8_t CTRLB; /* Channel Control */ - register8_t ADDRCTRL; /* Memory Address Control for Peripheral Ch., or Source Address Control for Standard Ch. */ - register8_t DESTADDRCTRL; /* Destination Address Control for Standard Channels Only. */ - register8_t TRIGSRC; /* Channel Trigger Source */ - register8_t reserved_0x05; - _WORDREGISTER(TRFCNT); /* Channel Block Transfer Count for Peripheral Ch., or Channel Block Transfer Count Low for Standard Ch. */ - _WORDREGISTER(ADDR); /* Channel Memory Address for Peripheral Ch., or Channel Source Address Low for Standard Ch. */ - register8_t reserved_0x0A; - register8_t reserved_0x0B; - _WORDREGISTER(DESTADDR); /* Channel Destination Address for Standard Channels Only. */ - register8_t reserved_0x0E; - register8_t reserved_0x0F; -} EDMA_CH_t; - - -/* Enhanced DMA Controller */ -typedef struct EDMA_struct -{ - register8_t CTRL; /* Control */ - register8_t reserved_0x01; - register8_t reserved_0x02; - register8_t INTFLAGS; /* Transfer Interrupt Status */ - register8_t STATUS; /* Status */ - register8_t reserved_0x05; - register8_t TEMP; /* Temporary Register For 16-bit Access */ - register8_t reserved_0x07; - register8_t reserved_0x08; - register8_t reserved_0x09; - register8_t reserved_0x0A; - register8_t reserved_0x0B; - register8_t reserved_0x0C; - register8_t reserved_0x0D; - register8_t reserved_0x0E; - register8_t reserved_0x0F; - EDMA_CH_t CH0; /* EDMA Channel 0 */ - EDMA_CH_t CH1; /* EDMA Channel 1 */ - EDMA_CH_t CH2; /* EDMA Channel 2 */ - EDMA_CH_t CH3; /* EDMA Channel 3 */ -} EDMA_t; - -/* Channel mode */ -typedef enum EDMA_CHMODE_enum -{ - EDMA_CHMODE_PER0123_gc = (0x00<<4), /* Channels 0, 1, 2 and 3 in peripheal conf. */ - EDMA_CHMODE_STD0_gc = (0x01<<4), /* Channel 0 in standard conf.; channels 2 and 3 in peripheral conf. */ - EDMA_CHMODE_STD2_gc = (0x02<<4), /* Channel 2 in standard conf.; channels 0 and 1 in peripheral conf. */ - EDMA_CHMODE_STD02_gc = (0x03<<4), /* Channels 0 and 2 in standard conf. */ -} EDMA_CHMODE_t; - -/* Double buffer mode */ -typedef enum EDMA_DBUFMODE_enum -{ - EDMA_DBUFMODE_DISABLE_gc = (0x00<<2), /* No double buffer enabled */ - EDMA_DBUFMODE_BUF01_gc = (0x01<<2), /* Double buffer enabled on peripheral channels 0/1 (if exist) */ - EDMA_DBUFMODE_BUF23_gc = (0x02<<2), /* Double buffer enabled on peripheral channels 2/3 (if exist) */ - EDMA_DBUFMODE_BUF0123_gc = (0x03<<2), /* Double buffer enabled on peripheral channels 0/1 and 2/3 or standard channels 0/2 */ -} EDMA_DBUFMODE_t; - -/* Priority mode */ -typedef enum EDMA_PRIMODE_enum -{ - EDMA_PRIMODE_RR0123_gc = (0x00<<0), /* Round robin on all channels */ - EDMA_PRIMODE_RR123_gc = (0x01<<0), /* Ch0 > round robin (Ch 1 ch2 Ch3) */ - EDMA_PRIMODE_RR23_gc = (0x02<<0), /* Ch0 > Ch 1 > round robin (Ch2 Ch3) */ - EDMA_PRIMODE_CH0123_gc = (0x03<<0), /* Ch0 > Ch1 > Ch2 > Ch3 */ -} EDMA_PRIMODE_t; - -/* Memory Address Reload for Peripheral Ch., or Source Address Reload for Standard Ch. */ -typedef enum EDMA_CH_RELOAD_enum -{ - EDMA_CH_RELOAD_NONE_gc = (0x00<<4), /* No reload */ - EDMA_CH_RELOAD_BLOCK_gc = (0x01<<4), /* Reload at end of each block transfer */ - EDMA_CH_RELOAD_BURST_gc = (0x02<<4), /* Reload at end of each burst transfer */ - EDMA_CH_RELOAD_TRANSACTION_gc = (0x03<<4), /* Reload at end of each transaction */ -} EDMA_CH_RELOAD_t; - -/* Memory Address Mode for Peripheral Ch., or Source Address Mode for Standard Ch. */ -typedef enum EDMA_CH_DIR_enum -{ - EDMA_CH_DIR_FIXED_gc = (0x00<<0), /* Fixed */ - EDMA_CH_DIR_INC_gc = (0x01<<0), /* Increment */ - EDMA_CH_DIR_MP1_gc = (0x04<<0), /* If Peripheral Ch. (Per ==> Mem), 1-byte 'mask-match' (data: ADDRL, mask: ADDRH), else reserved conf. */ - EDMA_CH_DIR_MP2_gc = (0x05<<0), /* If Peripheral Ch. (Per ==> Mem), 1-byte 'OR-match' (data-1: ADDRL OR data-2: ADDRH), else reserved conf. */ - EDMA_CH_DIR_MP3_gc = (0x06<<0), /* If Peripheral Ch. (Per ==> Mem), 2-byte 'match' (data-1: ADDRL followed by data-2: ADDRH), else reserved conf. */ -} EDMA_CH_DIR_t; - -/* Destination addressing mode */ -typedef enum EDMA_CH_DESTDIR_enum -{ - EDMA_CH_DESTDIR_FIXED_gc = (0x00<<0), /* Fixed */ - EDMA_CH_DESTDIR_INC_gc = (0x01<<0), /* Increment */ - EDMA_CH_DESTDIR_MP1_gc = (0x04<<0), /* 1-byte 'mask-match' (data: ADDRL, mask: ADDRH) */ - EDMA_CH_DESTDIR_MP2_gc = (0x05<<0), /* 1-byte 'OR-match' (data-1: ADDRL OR data-2: ADDRH) */ - EDMA_CH_DESTDIR_MP3_gc = (0x06<<0), /* 2-byte 'match' (data1: ADDRL followed by data2: ADDRH) */ -} EDMA_CH_DESTDIR_t; - -/* Transfer trigger source */ -typedef enum EDMA_CH_TRIGSRC_enum -{ - EDMA_CH_TRIGSRC_OFF_gc = (0x00<<0), /* Software triggers only */ - EDMA_CH_TRIGSRC_EVSYS_CH0_gc = (0x01<<0), /* Event CH0 as trigger (Standard Channels Only) */ - EDMA_CH_TRIGSRC_EVSYS_CH1_gc = (0x02<<0), /* Event CH1 as trigger (Standard Channels Only) */ - EDMA_CH_TRIGSRC_EVSYS_CH2_gc = (0x03<<0), /* Event CH2 as trigger (Standard Channels Only) */ - EDMA_CH_TRIGSRC_ADCA_CH0_gc = (0x10<<0), /* ADCA CH0 as trigger */ - EDMA_CH_TRIGSRC_DACA_CH0_gc = (0x15<<0), /* DACA CH0 as trigger */ - EDMA_CH_TRIGSRC_DACA_CH1_gc = (0x16<<0), /* DACA CH1 as trigger */ - EDMA_CH_TRIGSRC_TCC4_OVF_gc = (0x40<<0), /* TCC4 overflow/underflow as trigger (Standard Channels Only) */ - EDMA_CH_TRIGSRC_TCC4_ERR_gc = (0x41<<0), /* TCC4 error as trigger (Standard Channels Only) */ - EDMA_CH_TRIGSRC_TCC4_CCA_gc = (0x42<<0), /* TCC4 compare or capture channel A as trigger (Standard Channels Only) */ - EDMA_CH_TRIGSRC_TCC4_CCB_gc = (0x43<<0), /* TCC4 compare or capture channel B as trigger (Standard Channels Only) */ - EDMA_CH_TRIGSRC_TCC4_CCC_gc = (0x44<<0), /* TCC4 compare or capture channel C as trigger (Standard Channels Only) */ - EDMA_CH_TRIGSRC_TCC4_CCD_gc = (0x45<<0), /* TCC4 compare or capture channel D as trigger (Standard Channels Only) */ - EDMA_CH_TRIGSRC_TCC5_OVF_gc = (0x46<<0), /* TCC5 overflow/underflow as trigger (Standard Channels Only) */ - EDMA_CH_TRIGSRC_TCC5_ERR_gc = (0x47<<0), /* TCC5 error as trigger (Standard Channels Only) */ - EDMA_CH_TRIGSRC_TCC5_CCA_gc = (0x48<<0), /* TCC5 compare or capture channel A as trigger (Standard Channels Only) */ - EDMA_CH_TRIGSRC_TCC5_CCB_gc = (0x49<<0), /* TCC5 compare or capture channel B as trigger (Standard Channels Only) */ - EDMA_CH_TRIGSRC_SPIC_RXC_gc = (0x4A<<0), /* SPI C transfer complete (SPI Standard Mode) or SPI C receive complete as trigger (SPI Buffer Modes) */ - EDMA_CH_TRIGSRC_SPIC_DRE_gc = (0x4B<<0), /* SPI C transfer complete (SPI Standard Mode) or SPI C data register empty as trigger (SPI Buffer modes) */ - EDMA_CH_TRIGSRC_USARTC0_RXC_gc = (0x4C<<0), /* USART C0 receive complete as trigger */ - EDMA_CH_TRIGSRC_USARTC0_DRE_gc = (0x4D<<0), /* USART C0 data register empty as trigger */ - EDMA_CH_TRIGSRC_TCD5_OVF_gc = (0x66<<0), /* TCD5 overflow/underflow as trigger (Standard Channels Only) */ - EDMA_CH_TRIGSRC_TCD5_ERR_gc = (0x67<<0), /* TCD5 error as trigger (Standard Channels Only) */ - EDMA_CH_TRIGSRC_TCD5_CCA_gc = (0x68<<0), /* TCD5 compare or capture channel A as trigger (Standard Channels Only) */ - EDMA_CH_TRIGSRC_TCD5_CCB_gc = (0x69<<0), /* TCD5 compare or capture channel B as trigger (Standard Channels Only) */ - EDMA_CH_TRIGSRC_USARTD0_RXC_gc = (0x6C<<0), /* USART D0 receive complete as trigger */ - EDMA_CH_TRIGSRC_USARTD0_DRE_gc = (0x6D<<0), /* USART D0 data register empty as trigger */ -} EDMA_CH_TRIGSRC_t; - -/* Interrupt level */ -typedef enum EDMA_CH_INTLVL_enum -{ - EDMA_CH_INTLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ - EDMA_CH_INTLVL_LO_gc = (0x01<<2), /* Low level */ - EDMA_CH_INTLVL_MED_gc = (0x02<<2), /* Medium level */ - EDMA_CH_INTLVL_HI_gc = (0x03<<2), /* High level */ -} EDMA_CH_INTLVL_t; - - -/* --------------------------------------------------------------------------- -EVSYS - Event System --------------------------------------------------------------------------- -*/ - -/* Event System */ -typedef struct EVSYS_struct -{ - register8_t CH0MUX; /* Event Channel 0 Multiplexer */ - register8_t CH1MUX; /* Event Channel 1 Multiplexer */ - register8_t CH2MUX; /* Event Channel 2 Multiplexer */ - register8_t CH3MUX; /* Event Channel 3 Multiplexer */ - register8_t CH4MUX; /* Event Channel 4 Multiplexer */ - register8_t CH5MUX; /* Event Channel 5 Multiplexer */ - register8_t CH6MUX; /* Event Channel 6 Multiplexer */ - register8_t CH7MUX; /* Event Channel 7 Multiplexer */ - register8_t CH0CTRL; /* Channel 0 Control Register */ - register8_t CH1CTRL; /* Channel 1 Control Register */ - register8_t CH2CTRL; /* Channel 2 Control Register */ - register8_t CH3CTRL; /* Channel 3 Control Register */ - register8_t CH4CTRL; /* Channel 4 Control Register */ - register8_t CH5CTRL; /* Channel 5 Control Register */ - register8_t CH6CTRL; /* Channel 6 Control Register */ - register8_t CH7CTRL; /* Channel 7 Control Register */ - register8_t STROBE; /* Event Strobe */ - register8_t DATA; /* Event Data */ - register8_t DFCTRL; /* Digital Filter Control Register */ -} EVSYS_t; - -/* Event Channel multiplexer input selection */ -typedef enum EVSYS_CHMUX_enum -{ - EVSYS_CHMUX_OFF_gc = (0x00<<0), /* Off */ - EVSYS_CHMUX_RTC_OVF_gc = (0x08<<0), /* RTC Overflow */ - EVSYS_CHMUX_RTC_CMP_gc = (0x09<<0), /* RTC Compare Match */ - EVSYS_CHMUX_ACA_CH0_gc = (0x10<<0), /* Analog Comparator A Channel 0 */ - EVSYS_CHMUX_ACA_CH1_gc = (0x11<<0), /* Analog Comparator A Channel 1 */ - EVSYS_CHMUX_ACA_WIN_gc = (0x12<<0), /* Analog Comparator A Window */ - EVSYS_CHMUX_ADCA_CH0_gc = (0x20<<0), /* ADC A Channel 0 */ - EVSYS_CHMUX_PORTA_PIN0_gc = (0x50<<0), /* Port A, Pin0 */ - EVSYS_CHMUX_PORTA_PIN1_gc = (0x51<<0), /* Port A, Pin1 */ - EVSYS_CHMUX_PORTA_PIN2_gc = (0x52<<0), /* Port A, Pin2 */ - EVSYS_CHMUX_PORTA_PIN3_gc = (0x53<<0), /* Port A, Pin3 */ - EVSYS_CHMUX_PORTA_PIN4_gc = (0x54<<0), /* Port A, Pin4 */ - EVSYS_CHMUX_PORTA_PIN5_gc = (0x55<<0), /* Port A, Pin5 */ - EVSYS_CHMUX_PORTA_PIN6_gc = (0x56<<0), /* Port A, Pin6 */ - EVSYS_CHMUX_PORTA_PIN7_gc = (0x57<<0), /* Port A, Pin7 */ - EVSYS_CHMUX_PORTC_PIN0_gc = (0x60<<0), /* Port C, Pin0 */ - EVSYS_CHMUX_PORTC_PIN1_gc = (0x61<<0), /* Port C, Pin1 */ - EVSYS_CHMUX_PORTC_PIN2_gc = (0x62<<0), /* Port C, Pin2 */ - EVSYS_CHMUX_PORTC_PIN3_gc = (0x63<<0), /* Port C, Pin3 */ - EVSYS_CHMUX_PORTC_PIN4_gc = (0x64<<0), /* Port C, Pin4 */ - EVSYS_CHMUX_PORTC_PIN5_gc = (0x65<<0), /* Port C, Pin5 */ - EVSYS_CHMUX_PORTC_PIN6_gc = (0x66<<0), /* Port C, Pin6 */ - EVSYS_CHMUX_PORTC_PIN7_gc = (0x67<<0), /* Port C, Pin7 */ - EVSYS_CHMUX_PORTD_PIN0_gc = (0x68<<0), /* Port D, Pin0 */ - EVSYS_CHMUX_PORTD_PIN1_gc = (0x69<<0), /* Port D, Pin1 */ - EVSYS_CHMUX_PORTD_PIN2_gc = (0x6A<<0), /* Port D, Pin2 */ - EVSYS_CHMUX_PORTD_PIN3_gc = (0x6B<<0), /* Port D, Pin3 */ - EVSYS_CHMUX_PORTD_PIN4_gc = (0x6C<<0), /* Port D, Pin4 */ - EVSYS_CHMUX_PORTD_PIN5_gc = (0x6D<<0), /* Port D, Pin5 */ - EVSYS_CHMUX_PORTD_PIN6_gc = (0x6E<<0), /* Port D, Pin6 */ - EVSYS_CHMUX_PORTD_PIN7_gc = (0x6F<<0), /* Port D, Pin7 */ - EVSYS_CHMUX_PRESCALER_1_gc = (0x80<<0), /* Prescaler, divide by 1 */ - EVSYS_CHMUX_PRESCALER_2_gc = (0x81<<0), /* Prescaler, divide by 2 */ - EVSYS_CHMUX_PRESCALER_4_gc = (0x82<<0), /* Prescaler, divide by 4 */ - EVSYS_CHMUX_PRESCALER_8_gc = (0x83<<0), /* Prescaler, divide by 8 */ - EVSYS_CHMUX_PRESCALER_16_gc = (0x84<<0), /* Prescaler, divide by 16 */ - EVSYS_CHMUX_PRESCALER_32_gc = (0x85<<0), /* Prescaler, divide by 32 */ - EVSYS_CHMUX_PRESCALER_64_gc = (0x86<<0), /* Prescaler, divide by 64 */ - EVSYS_CHMUX_PRESCALER_128_gc = (0x87<<0), /* Prescaler, divide by 128 */ - EVSYS_CHMUX_PRESCALER_256_gc = (0x88<<0), /* Prescaler, divide by 256 */ - EVSYS_CHMUX_PRESCALER_512_gc = (0x89<<0), /* Prescaler, divide by 512 */ - EVSYS_CHMUX_PRESCALER_1024_gc = (0x8A<<0), /* Prescaler, divide by 1024 */ - EVSYS_CHMUX_PRESCALER_2048_gc = (0x8B<<0), /* Prescaler, divide by 2048 */ - EVSYS_CHMUX_PRESCALER_4096_gc = (0x8C<<0), /* Prescaler, divide by 4096 */ - EVSYS_CHMUX_PRESCALER_8192_gc = (0x8D<<0), /* Prescaler, divide by 8192 */ - EVSYS_CHMUX_PRESCALER_16384_gc = (0x8E<<0), /* Prescaler, divide by 16384 */ - EVSYS_CHMUX_PRESCALER_32768_gc = (0x8F<<0), /* Prescaler, divide by 32768 */ - EVSYS_CHMUX_XCL_UNF0_gc = (0xB0<<0), /* XCL BTC0 underflow */ - EVSYS_CHMUX_XCL_UNF1_gc = (0xB1<<0), /* XCL BTC1 underflow */ - EVSYS_CHMUX_XCL_CC0_gc = (0xB2<<0), /* XCL BTC0 capture or compare */ - EVSYS_CHMUX_XCL_CC1_gc = (0xB3<<0), /* XCL BTC0 capture or compare */ - EVSYS_CHMUX_XCL_PEC0_gc = (0xB4<<0), /* XCL PEC0 restart */ - EVSYS_CHMUX_XCL_PEC1_gc = (0xB5<<0), /* XCL PEC1 restart */ - EVSYS_CHMUX_XCL_LUT0_gc = (0xB6<<0), /* XCL LUT0 output */ - EVSYS_CHMUX_XCL_LUT1_gc = (0xB7<<0), /* XCL LUT1 output */ - EVSYS_CHMUX_TCC4_OVF_gc = (0xC0<<0), /* Timer/Counter C4 Overflow */ - EVSYS_CHMUX_TCC4_ERR_gc = (0xC1<<0), /* Timer/Counter C4 Error */ - EVSYS_CHMUX_TCC4_CCA_gc = (0xC4<<0), /* Timer/Counter C4 Compare or Capture A */ - EVSYS_CHMUX_TCC4_CCB_gc = (0xC5<<0), /* Timer/Counter C4 Compare or Capture B */ - EVSYS_CHMUX_TCC4_CCC_gc = (0xC6<<0), /* Timer/Counter C4 Compare or Capture C */ - EVSYS_CHMUX_TCC4_CCD_gc = (0xC7<<0), /* Timer/Counter C4 Compare or Capture D */ - EVSYS_CHMUX_TCC5_OVF_gc = (0xC8<<0), /* Timer/Counter C5 Overflow */ - EVSYS_CHMUX_TCC5_ERR_gc = (0xC9<<0), /* Timer/Counter C5 Error */ - EVSYS_CHMUX_TCC5_CCA_gc = (0xCC<<0), /* Timer/Counter C5 Compare or Capture A */ - EVSYS_CHMUX_TCC5_CCB_gc = (0xCD<<0), /* Timer/Counter C5 Compare or Capture B */ - EVSYS_CHMUX_TCD5_OVF_gc = (0xD8<<0), /* Timer/Counter D5 Overflow */ - EVSYS_CHMUX_TCD5_ERR_gc = (0xD9<<0), /* Timer/Counter D5 Error */ - EVSYS_CHMUX_TCD5_CCA_gc = (0xDC<<0), /* Timer/Counter D5 Compare or Capture A */ - EVSYS_CHMUX_TCD5_CCB_gc = (0xDD<<0), /* Timer/Counter D5 Compare or Capture B */ -} EVSYS_CHMUX_t; - -/* Quadrature Decoder Index Recognition Mode */ -typedef enum EVSYS_QDIRM_enum -{ - EVSYS_QDIRM_00_gc = (0x00<<5), /* QDPH0 = 0, QDPH90 = 0 */ - EVSYS_QDIRM_01_gc = (0x01<<5), /* QDPH0 = 0, QDPH90 = 1 */ - EVSYS_QDIRM_10_gc = (0x02<<5), /* QDPH0 = 1, QDPH90 = 0 */ - EVSYS_QDIRM_11_gc = (0x03<<5), /* QDPH0 = 1, QDPH90 = 1 */ -} EVSYS_QDIRM_t; - -/* Digital filter coefficient */ -typedef enum EVSYS_DIGFILT_enum -{ - EVSYS_DIGFILT_1SAMPLE_gc = (0x00<<0), /* 1 SAMPLE */ - EVSYS_DIGFILT_2SAMPLES_gc = (0x01<<0), /* 2 SAMPLES */ - EVSYS_DIGFILT_3SAMPLES_gc = (0x02<<0), /* 3 SAMPLES */ - EVSYS_DIGFILT_4SAMPLES_gc = (0x03<<0), /* 4 SAMPLES */ - EVSYS_DIGFILT_5SAMPLES_gc = (0x04<<0), /* 5 SAMPLES */ - EVSYS_DIGFILT_6SAMPLES_gc = (0x05<<0), /* 6 SAMPLES */ - EVSYS_DIGFILT_7SAMPLES_gc = (0x06<<0), /* 7 SAMPLES */ - EVSYS_DIGFILT_8SAMPLES_gc = (0x07<<0), /* 8 SAMPLES */ -} EVSYS_DIGFILT_t; - -/* Prescaler Filter */ -typedef enum EVSYS_PRESCFILT_enum -{ - EVSYS_PRESCFILT_CH04_gc = (0x01<<4), /* Enable prescaler filter for either channel 0 or 4 */ - EVSYS_PRESCFILT_CH15_gc = (0x02<<4), /* Enable prescaler filter for either channel 1 or 5 */ - EVSYS_PRESCFILT_CH26_gc = (0x04<<4), /* Enable prescaler filter for either channel 2 or 6 */ - EVSYS_PRESCFILT_CH37_gc = (0x08<<4), /* Enable prescaler filter for either channel 3 or 7 */ -} EVSYS_PRESCFILT_t; - -/* Prescaler */ -typedef enum EVSYS_PRESCALER_enum -{ - EVSYS_PRESCALER_CLKPER_8_gc = (0x00<<0), /* CLKPER, divide by 8 */ - EVSYS_PRESCALER_CLKPER_64_gc = (0x01<<0), /* CLKPER, divide by 64 */ - EVSYS_PRESCALER_CLKPER_512_gc = (0x02<<0), /* CLKPER, divide by 512 */ - EVSYS_PRESCALER_CLKPER_4096_gc = (0x03<<0), /* CLKPER, divide by 4096 */ - EVSYS_PRESCALER_CLKPER_32768_gc = (0x04<<0), /* CLKPER, divide by 32768 */ -} EVSYS_PRESCALER_t; - - -/* --------------------------------------------------------------------------- -NVM - Non Volatile Memory Controller --------------------------------------------------------------------------- -*/ - -/* Non-volatile Memory Controller */ -typedef struct NVM_struct -{ - register8_t ADDR0; /* Address Register 0 */ - register8_t ADDR1; /* Address Register 1 */ - register8_t ADDR2; /* Address Register 2 */ - register8_t reserved_0x03; - register8_t DATA0; /* Data Register 0 */ - register8_t DATA1; /* Data Register 1 */ - register8_t DATA2; /* Data Register 2 */ - register8_t reserved_0x07; - register8_t reserved_0x08; - register8_t reserved_0x09; - register8_t CMD; /* Command */ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t INTCTRL; /* Interrupt Control */ - register8_t reserved_0x0E; - register8_t STATUS; /* Status */ - register8_t LOCK_BITS; /* Lock Bits (Changed from LOCKBITS to avoid avr-libc collision) */ -} NVM_t; - -/* NVM Command */ -typedef enum NVM_CMD_enum -{ - NVM_CMD_NO_OPERATION_gc = (0x00<<0), /* Noop/Ordinary LPM */ - NVM_CMD_READ_USER_SIG_ROW_gc = (0x01<<0), /* Read user signature row */ - NVM_CMD_READ_CALIB_ROW_gc = (0x02<<0), /* Read calibration row */ - NVM_CMD_READ_FUSES_gc = (0x07<<0), /* Read fuse byte */ - NVM_CMD_WRITE_LOCK_BITS_gc = (0x08<<0), /* Write lock bits */ - NVM_CMD_ERASE_USER_SIG_ROW_gc = (0x18<<0), /* Erase user signature row */ - NVM_CMD_WRITE_USER_SIG_ROW_gc = (0x1A<<0), /* Write user signature row */ - NVM_CMD_ERASE_APP_gc = (0x20<<0), /* Erase Application Section */ - NVM_CMD_ERASE_APP_PAGE_gc = (0x22<<0), /* Erase Application Section page */ - NVM_CMD_LOAD_FLASH_BUFFER_gc = (0x23<<0), /* Load Flash page buffer */ - NVM_CMD_WRITE_APP_PAGE_gc = (0x24<<0), /* Write Application Section page */ - NVM_CMD_ERASE_WRITE_APP_PAGE_gc = (0x25<<0), /* Erase-and-write Application Section page */ - NVM_CMD_ERASE_FLASH_BUFFER_gc = (0x26<<0), /* Erase/flush Flash page buffer */ - NVM_CMD_ERASE_BOOT_PAGE_gc = (0x2A<<0), /* Erase Boot Section page */ - NVM_CMD_ERASE_FLASH_PAGE_gc = (0x2B<<0), /* Erase Flash Page */ - NVM_CMD_WRITE_BOOT_PAGE_gc = (0x2C<<0), /* Write Boot Section page */ - NVM_CMD_ERASE_WRITE_BOOT_PAGE_gc = (0x2D<<0), /* Erase-and-write Boot Section page */ - NVM_CMD_WRITE_FLASH_PAGE_gc = (0x2E<<0), /* Write Flash Page */ - NVM_CMD_ERASE_WRITE_FLASH_PAGE_gc = (0x2F<<0), /* Erase-and-write Flash Page */ - NVM_CMD_ERASE_EEPROM_gc = (0x30<<0), /* Erase EEPROM */ - NVM_CMD_ERASE_EEPROM_PAGE_gc = (0x32<<0), /* Erase EEPROM page */ - NVM_CMD_WRITE_EEPROM_PAGE_gc = (0x34<<0), /* Write EEPROM page */ - NVM_CMD_ERASE_WRITE_EEPROM_PAGE_gc = (0x35<<0), /* Erase-and-write EEPROM page */ - NVM_CMD_ERASE_EEPROM_BUFFER_gc = (0x36<<0), /* Erase/flush EEPROM page buffer */ - NVM_CMD_APP_CRC_gc = (0x38<<0), /* Application section CRC */ - NVM_CMD_BOOT_CRC_gc = (0x39<<0), /* Boot Section CRC */ - NVM_CMD_FLASH_RANGE_CRC_gc = (0x3A<<0), /* Flash Range CRC */ - NVM_CMD_CHIP_ERASE_gc = (0x40<<0), /* Erase Chip */ - NVM_CMD_READ_NVM_gc = (0x43<<0), /* Read NVM */ - NVM_CMD_WRITE_FUSE_gc = (0x4C<<0), /* Write Fuse byte */ - NVM_CMD_ERASE_BOOT_gc = (0x68<<0), /* Erase Boot Section */ - NVM_CMD_FLASH_CRC_gc = (0x78<<0), /* Flash CRC */ -} NVM_CMD_t; - -/* SPM ready interrupt level */ -typedef enum NVM_SPMLVL_enum -{ - NVM_SPMLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ - NVM_SPMLVL_LO_gc = (0x01<<2), /* Low level */ - NVM_SPMLVL_MED_gc = (0x02<<2), /* Medium level */ - NVM_SPMLVL_HI_gc = (0x03<<2), /* High level */ -} NVM_SPMLVL_t; - -/* EEPROM ready interrupt level */ -typedef enum NVM_EELVL_enum -{ - NVM_EELVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ - NVM_EELVL_LO_gc = (0x01<<0), /* Low level */ - NVM_EELVL_MED_gc = (0x02<<0), /* Medium level */ - NVM_EELVL_HI_gc = (0x03<<0), /* High level */ -} NVM_EELVL_t; - -/* Boot lock bits - boot setcion */ -typedef enum NVM_BLBB_enum -{ - NVM_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ - NVM_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ - NVM_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ - NVM_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ -} NVM_BLBB_t; - -/* Boot lock bits - application section */ -typedef enum NVM_BLBA_enum -{ - NVM_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ - NVM_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ - NVM_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ - NVM_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ -} NVM_BLBA_t; - -/* Boot lock bits - application table section */ -typedef enum NVM_BLBAT_enum -{ - NVM_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ - NVM_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ - NVM_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ - NVM_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ -} NVM_BLBAT_t; - -/* Lock bits */ -typedef enum NVM_LB_enum -{ - NVM_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ - NVM_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ - NVM_LB_NOLOCK_gc = (0x03<<0), /* No locks */ -} NVM_LB_t; - - -/* --------------------------------------------------------------------------- -ADC - Analog/Digital Converter --------------------------------------------------------------------------- -*/ - -/* ADC Channel */ -typedef struct ADC_CH_struct -{ - register8_t CTRL; /* Control Register */ - register8_t MUXCTRL; /* MUX Control */ - register8_t INTCTRL; /* Channel Interrupt Control Register */ - register8_t INTFLAGS; /* Interrupt Flags */ - _WORDREGISTER(RES); /* Channel Result */ - register8_t SCAN; /* Input Channel Scan */ - register8_t CORRCTRL; /* Correction Control Register */ - register8_t OFFSETCORR0; /* Offset Correction Register 0 */ - register8_t OFFSETCORR1; /* Offset Correction Register 1 */ - register8_t GAINCORR0; /* Gain Correction Register 0 */ - register8_t GAINCORR1; /* Gain Correction Register 1 */ - register8_t AVGCTRL; /* Average Control Register */ - register8_t reserved_0x0D; - register8_t reserved_0x0E; - register8_t reserved_0x0F; -} ADC_CH_t; - - -/* Analog-to-Digital Converter */ -typedef struct ADC_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t REFCTRL; /* Reference Control */ - register8_t EVCTRL; /* Event Control */ - register8_t PRESCALER; /* Clock Prescaler */ - register8_t reserved_0x05; - register8_t INTFLAGS; /* Interrupt Flags */ - register8_t TEMP; /* Temporary Register */ - register8_t SAMPCTRL; /* ADC Sampling Time Control Register */ - register8_t reserved_0x09; - register8_t reserved_0x0A; - register8_t reserved_0x0B; - _WORDREGISTER(CAL); /* Calibration Value */ - register8_t reserved_0x0E; - register8_t reserved_0x0F; - _WORDREGISTER(CH0RES); /* Channel 0 Result */ - register8_t reserved_0x12; - register8_t reserved_0x13; - register8_t reserved_0x14; - register8_t reserved_0x15; - register8_t reserved_0x16; - register8_t reserved_0x17; - _WORDREGISTER(CMP); /* Compare Value */ - register8_t reserved_0x1A; - register8_t reserved_0x1B; - register8_t reserved_0x1C; - register8_t reserved_0x1D; - register8_t reserved_0x1E; - register8_t reserved_0x1F; - ADC_CH_t CH0; /* ADC Channel 0 */ -} ADC_t; - -/* Current Limitation */ -typedef enum ADC_CURRLIMIT_enum -{ - ADC_CURRLIMIT_NO_gc = (0x00<<5), /* No current limit, 300ksps max sampling rate */ - ADC_CURRLIMIT_LOW_gc = (0x01<<5), /* Low current limit, 250ksps max sampling rate */ - ADC_CURRLIMIT_MED_gc = (0x02<<5), /* Medium current limit, 150ksps max sampling rate */ - ADC_CURRLIMIT_HIGH_gc = (0x03<<5), /* High current limit, 50ksps max sampling rate */ -} ADC_CURRLIMIT_t; - -/* Conversion result resolution */ -typedef enum ADC_RESOLUTION_enum -{ - ADC_RESOLUTION_12BIT_gc = (0x00<<1), /* 12-bit right-adjusted result */ - ADC_RESOLUTION_MT12BIT_gc = (0x01<<1), /* More than 12-bit (oversapling) right-adjusted result */ - ADC_RESOLUTION_8BIT_gc = (0x02<<1), /* 8-bit right-adjusted result */ - ADC_RESOLUTION_LEFT12BIT_gc = (0x03<<1), /* 12-bit left-adjusted result */ -} ADC_RESOLUTION_t; - -/* Voltage reference selection */ -typedef enum ADC_REFSEL_enum -{ - ADC_REFSEL_INT1V_gc = (0x00<<4), /* Internal 1V */ - ADC_REFSEL_INTVCC_gc = (0x01<<4), /* Internal VCC / 1.6 */ - ADC_REFSEL_AREFA_gc = (0x02<<4), /* External reference on PORT A */ - ADC_REFSEL_AREFD_gc = (0x03<<4), /* External reference on PORT D */ - ADC_REFSEL_INTVCC2_gc = (0x04<<4), /* Internal VCC / 2 */ -} ADC_REFSEL_t; - -/* Event channel input selection */ -typedef enum ADC_EVSEL_enum -{ - ADC_EVSEL_0_gc = (0x00<<3), /* Event Channel 0 */ - ADC_EVSEL_1_gc = (0x01<<3), /* Event Channel 1 */ - ADC_EVSEL_2_gc = (0x02<<3), /* Event Channel 2 */ - ADC_EVSEL_3_gc = (0x03<<3), /* Event Channel 3 */ - ADC_EVSEL_4_gc = (0x04<<3), /* Event Channel 4 */ - ADC_EVSEL_5_gc = (0x05<<3), /* Event Channel 5 */ - ADC_EVSEL_6_gc = (0x06<<3), /* Event Channel 6 */ - ADC_EVSEL_7_gc = (0x07<<3), /* Event Channel 7 */ -} ADC_EVSEL_t; - -/* Event action selection */ -typedef enum ADC_EVACT_enum -{ - ADC_EVACT_NONE_gc = (0x00<<0), /* No event action */ - ADC_EVACT_CH0_gc = (0x01<<0), /* First event triggers channel conversion */ - ADC_EVACT_SYNCSWEEP_gc = (0x06<<0), /* The ADC is flushed and restarted for accurate timing */ -} ADC_EVACT_t; - -/* Clock prescaler */ -typedef enum ADC_PRESCALER_enum -{ - ADC_PRESCALER_DIV4_gc = (0x00<<0), /* Divide clock by 4 */ - ADC_PRESCALER_DIV8_gc = (0x01<<0), /* Divide clock by 8 */ - ADC_PRESCALER_DIV16_gc = (0x02<<0), /* Divide clock by 16 */ - ADC_PRESCALER_DIV32_gc = (0x03<<0), /* Divide clock by 32 */ - ADC_PRESCALER_DIV64_gc = (0x04<<0), /* Divide clock by 64 */ - ADC_PRESCALER_DIV128_gc = (0x05<<0), /* Divide clock by 128 */ - ADC_PRESCALER_DIV256_gc = (0x06<<0), /* Divide clock by 256 */ - ADC_PRESCALER_DIV512_gc = (0x07<<0), /* Divide clock by 512 */ -} ADC_PRESCALER_t; - -/* Gain factor */ -typedef enum ADC_CH_GAIN_enum -{ - ADC_CH_GAIN_1X_gc = (0x00<<2), /* 1x gain */ - ADC_CH_GAIN_2X_gc = (0x01<<2), /* 2x gain */ - ADC_CH_GAIN_4X_gc = (0x02<<2), /* 4x gain */ - ADC_CH_GAIN_8X_gc = (0x03<<2), /* 8x gain */ - ADC_CH_GAIN_16X_gc = (0x04<<2), /* 16x gain */ - ADC_CH_GAIN_32X_gc = (0x05<<2), /* 32x gain */ - ADC_CH_GAIN_64X_gc = (0x06<<2), /* 64x gain */ - ADC_CH_GAIN_DIV2_gc = (0x07<<2), /* x/2 gain */ -} ADC_CH_GAIN_t; - -/* Input mode */ -typedef enum ADC_CH_INPUTMODE_enum -{ - ADC_CH_INPUTMODE_INTERNAL_gc = (0x00<<0), /* Internal inputs, no gain */ - ADC_CH_INPUTMODE_SINGLEENDED_gc = (0x01<<0), /* Single-ended input, no gain */ - ADC_CH_INPUTMODE_DIFFWGAINL_gc = (0x02<<0), /* Differential input, gain with 4 LSB pins selection */ - ADC_CH_INPUTMODE_DIFFWGAINH_gc = (0x03<<0), /* Differential input, gain with 4 MSB pins selection */ -} ADC_CH_INPUTMODE_t; - -/* Positive input multiplexer selection */ -typedef enum ADC_CH_MUXPOS_enum -{ - ADC_CH_MUXPOS_PIN0_gc = (0x00<<3), /* Input pin 0 */ - ADC_CH_MUXPOS_PIN1_gc = (0x01<<3), /* Input pin 1 */ - ADC_CH_MUXPOS_PIN2_gc = (0x02<<3), /* Input pin 2 */ - ADC_CH_MUXPOS_PIN3_gc = (0x03<<3), /* Input pin 3 */ - ADC_CH_MUXPOS_PIN4_gc = (0x04<<3), /* Input pin 4 */ - ADC_CH_MUXPOS_PIN5_gc = (0x05<<3), /* Input pin 5 */ - ADC_CH_MUXPOS_PIN6_gc = (0x06<<3), /* Input pin 6 */ - ADC_CH_MUXPOS_PIN7_gc = (0x07<<3), /* Input pin 7 */ - ADC_CH_MUXPOS_PIN8_gc = (0x08<<3), /* Input pin 8 */ - ADC_CH_MUXPOS_PIN9_gc = (0x09<<3), /* Input pin 9 */ - ADC_CH_MUXPOS_PIN10_gc = (0x0A<<3), /* Input pin 10 */ - ADC_CH_MUXPOS_PIN11_gc = (0x0B<<3), /* Input pin 11 */ - ADC_CH_MUXPOS_PIN12_gc = (0x0C<<3), /* Input pin 12 */ - ADC_CH_MUXPOS_PIN13_gc = (0x0D<<3), /* Input pin 13 */ - ADC_CH_MUXPOS_PIN14_gc = (0x0E<<3), /* Input pin 14 */ - ADC_CH_MUXPOS_PIN15_gc = (0x0F<<3), /* Input pin 15 */ -} ADC_CH_MUXPOS_t; - -/* Internal input multiplexer selections */ -typedef enum ADC_CH_MUXINT_enum -{ - ADC_CH_MUXINT_TEMP_gc = (0x00<<3), /* Temperature Reference */ - ADC_CH_MUXINT_BANDGAP_gc = (0x01<<3), /* Bandgap Reference */ - ADC_CH_MUXINT_SCALEDVCC_gc = (0x02<<3), /* 1/10 Scaled VCC */ - ADC_CH_MUXINT_DAC_gc = (0x03<<3), /* DAC Output */ -} ADC_CH_MUXINT_t; - -/* Negative input multiplexer selection when gain on 4 LSB pins */ -typedef enum ADC_CH_MUXNEGL_enum -{ - ADC_CH_MUXNEGL_PIN0_gc = (0x00<<0), /* Input pin 0 */ - ADC_CH_MUXNEGL_PIN1_gc = (0x01<<0), /* Input pin 1 */ - ADC_CH_MUXNEGL_PIN2_gc = (0x02<<0), /* Input pin 2 */ - ADC_CH_MUXNEGL_PIN3_gc = (0x03<<0), /* Input pin 3 */ - ADC_CH_MUXNEGL_GND_gc = (0x05<<0), /* PAD ground */ - ADC_CH_MUXNEGL_INTGND_gc = (0x07<<0), /* Internal ground */ -} ADC_CH_MUXNEGL_t; - -/* Negative input multiplexer selection when gain on 4 MSB pins */ -typedef enum ADC_CH_MUXNEGH_enum -{ - ADC_CH_MUXNEGH_PIN4_gc = (0x00<<0), /* Input pin 4 */ - ADC_CH_MUXNEGH_PIN5_gc = (0x01<<0), /* Input pin 5 */ - ADC_CH_MUXNEGH_PIN6_gc = (0x02<<0), /* Input pin 6 */ - ADC_CH_MUXNEGH_PIN7_gc = (0x03<<0), /* Input pin 7 */ - ADC_CH_MUXNEGH_GND_gc = (0x05<<0), /* PAD ground */ -} ADC_CH_MUXNEGH_t; - -/* Negative input multiplexer selection */ -typedef enum ADC_CH_MUXNEG_enum -{ - ADC_CH_MUXNEG_PIN0_gc = (0x00<<0), /* Input pin 0 */ -} ADC_CH_MUXNEG_t; - -/* Interupt mode */ -typedef enum ADC_CH_INTMODE_enum -{ - ADC_CH_INTMODE_COMPLETE_gc = (0x00<<2), /* Interrupt on conversion complete */ - ADC_CH_INTMODE_BELOW_gc = (0x01<<2), /* Interrupt on result below compare value */ - ADC_CH_INTMODE_ABOVE_gc = (0x03<<2), /* Interrupt on result above compare value */ -} ADC_CH_INTMODE_t; - -/* Interrupt level */ -typedef enum ADC_CH_INTLVL_enum -{ - ADC_CH_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ - ADC_CH_INTLVL_LO_gc = (0x01<<0), /* Low level */ - ADC_CH_INTLVL_MED_gc = (0x02<<0), /* Medium level */ - ADC_CH_INTLVL_HI_gc = (0x03<<0), /* High level */ -} ADC_CH_INTLVL_t; - -/* Averaged Number of Samples */ -typedef enum ADC_SAMPNUM_enum -{ - ADC_SAMPNUM_1X_gc = (0x00<<0), /* 1 Sample */ - ADC_SAMPNUM_2X_gc = (0x01<<0), /* 2 Samples */ - ADC_SAMPNUM_4X_gc = (0x02<<0), /* 4 Samples */ - ADC_SAMPNUM_8X_gc = (0x03<<0), /* 8 Samples */ - ADC_SAMPNUM_16X_gc = (0x04<<0), /* 16 Samples */ - ADC_SAMPNUM_32X_gc = (0x05<<0), /* 32 Samples */ - ADC_SAMPNUM_64X_gc = (0x06<<0), /* 64 Samples */ - ADC_SAMPNUM_128X_gc = (0x07<<0), /* 128 Samples */ - ADC_SAMPNUM_256X_gc = (0x08<<0), /* 256 Samples */ - ADC_SAMPNUM_512X_gc = (0x09<<0), /* 512 Samples */ - ADC_SAMPNUM_1024X_gc = (0x0A<<0), /* 1024 Samples */ -} ADC_SAMPNUM_t; - - -/* --------------------------------------------------------------------------- -DAC - Digital/Analog Converter --------------------------------------------------------------------------- -*/ - -/* Digital-to-Analog Converter */ -typedef struct DAC_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t CTRLC; /* Control Register C */ - register8_t EVCTRL; /* Event Input Control */ - register8_t reserved_0x04; - register8_t STATUS; /* Status */ - register8_t reserved_0x06; - register8_t reserved_0x07; - register8_t CH0GAINCAL; /* Gain Calibration */ - register8_t CH0OFFSETCAL; /* Offset Calibration */ - register8_t CH1GAINCAL; /* Gain Calibration */ - register8_t CH1OFFSETCAL; /* Offset Calibration */ - register8_t reserved_0x0C; - register8_t reserved_0x0D; - register8_t reserved_0x0E; - register8_t reserved_0x0F; - register8_t reserved_0x10; - register8_t reserved_0x11; - register8_t reserved_0x12; - register8_t reserved_0x13; - register8_t reserved_0x14; - register8_t reserved_0x15; - register8_t reserved_0x16; - register8_t reserved_0x17; - _WORDREGISTER(CH0DATA); /* Channel 0 Data */ - _WORDREGISTER(CH1DATA); /* Channel 1 Data */ -} DAC_t; - -/* Output channel selection */ -typedef enum DAC_CHSEL_enum -{ - DAC_CHSEL_SINGLE_gc = (0x00<<5), /* Single channel operation (Channel 0 only) */ - DAC_CHSEL_SINGLE1_gc = (0x01<<5), /* Single channel operation (Channel 1 only) */ - DAC_CHSEL_DUAL_gc = (0x02<<5), /* Dual channel operation (Channel 0 and channel 1) */ -} DAC_CHSEL_t; - -/* Reference voltage selection */ -typedef enum DAC_REFSEL_enum -{ - DAC_REFSEL_INT1V_gc = (0x00<<3), /* Internal 1V */ - DAC_REFSEL_AVCC_gc = (0x01<<3), /* Analog supply voltage */ - DAC_REFSEL_AREFA_gc = (0x02<<3), /* External reference on AREF on PORTA */ - DAC_REFSEL_AREFB_gc = (0x03<<3), /* External reference on AREF on PORTB */ -} DAC_REFSEL_t; - -/* Event channel selection */ -typedef enum DAC_EVSEL_enum -{ - DAC_EVSEL_0_gc = (0x00<<0), /* Event Channel 0 */ - DAC_EVSEL_1_gc = (0x01<<0), /* Event Channel 1 */ - DAC_EVSEL_2_gc = (0x02<<0), /* Event Channel 2 */ - DAC_EVSEL_3_gc = (0x03<<0), /* Event Channel 3 */ - DAC_EVSEL_4_gc = (0x04<<0), /* Event Channel 4 */ - DAC_EVSEL_5_gc = (0x05<<0), /* Event Channel 5 */ - DAC_EVSEL_6_gc = (0x06<<0), /* Event Channel 6 */ - DAC_EVSEL_7_gc = (0x07<<0), /* Event Channel 7 */ -} DAC_EVSEL_t; - - -/* --------------------------------------------------------------------------- -AC - Analog Comparator --------------------------------------------------------------------------- -*/ - -/* Analog Comparator */ -typedef struct AC_struct -{ - register8_t AC0CTRL; /* Analog Comparator 0 Control */ - register8_t AC1CTRL; /* Analog Comparator 1 Control */ - register8_t AC0MUXCTRL; /* Analog Comparator 0 MUX Control */ - register8_t AC1MUXCTRL; /* Analog Comparator 1 MUX Control */ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t WINCTRL; /* Window Mode Control */ - register8_t STATUS; /* Status */ - register8_t CURRCTRL; /* Current Source Control Register */ - register8_t CURRCALIB; /* Current Source Calibration Register */ -} AC_t; - -/* Interrupt mode */ -typedef enum AC_INTMODE_enum -{ - AC_INTMODE_BOTHEDGES_gc = (0x00<<6), /* Interrupt on both edges */ - AC_INTMODE_FALLING_gc = (0x02<<6), /* Interrupt on falling edge */ - AC_INTMODE_RISING_gc = (0x03<<6), /* Interrupt on rising edge */ -} AC_INTMODE_t; - -/* Interrupt level */ -typedef enum AC_INTLVL_enum -{ - AC_INTLVL_OFF_gc = (0x00<<4), /* Interrupt disabled */ - AC_INTLVL_LO_gc = (0x01<<4), /* Low level */ - AC_INTLVL_MED_gc = (0x02<<4), /* Medium level */ - AC_INTLVL_HI_gc = (0x03<<4), /* High level */ -} AC_INTLVL_t; - -/* Hysteresis mode selection */ -typedef enum AC_HYSMODE_enum -{ - AC_HYSMODE_NO_gc = (0x00<<1), /* No hysteresis */ - AC_HYSMODE_SMALL_gc = (0x01<<1), /* Small hysteresis */ - AC_HYSMODE_LARGE_gc = (0x02<<1), /* Large hysteresis */ -} AC_HYSMODE_t; - -/* Positive input multiplexer selection */ -typedef enum AC_MUXPOS_enum -{ - AC_MUXPOS_PIN0_gc = (0x00<<3), /* Pin 0 */ - AC_MUXPOS_PIN1_gc = (0x01<<3), /* Pin 1 */ - AC_MUXPOS_PIN2_gc = (0x02<<3), /* Pin 2 */ - AC_MUXPOS_PIN3_gc = (0x03<<3), /* Pin 3 */ - AC_MUXPOS_PIN4_gc = (0x04<<3), /* Pin 4 */ - AC_MUXPOS_PIN5_gc = (0x05<<3), /* Pin 5 */ - AC_MUXPOS_PIN6_gc = (0x06<<3), /* Pin 6 */ - AC_MUXPOS_DAC_gc = (0x07<<3), /* DAC output */ -} AC_MUXPOS_t; - -/* Negative input multiplexer selection */ -typedef enum AC_MUXNEG_enum -{ - AC_MUXNEG_PIN0_gc = (0x00<<0), /* Pin 0 */ - AC_MUXNEG_PIN1_gc = (0x01<<0), /* Pin 1 */ - AC_MUXNEG_PIN3_gc = (0x02<<0), /* Pin 3 */ - AC_MUXNEG_PIN5_gc = (0x03<<0), /* Pin 5 */ - AC_MUXNEG_PIN7_gc = (0x04<<0), /* Pin 7 */ - AC_MUXNEG_DAC_gc = (0x05<<0), /* DAC output */ - AC_MUXNEG_BANDGAP_gc = (0x06<<0), /* Bandgap Reference */ - AC_MUXNEG_SCALER_gc = (0x07<<0), /* Internal voltage scaler */ -} AC_MUXNEG_t; - -/* Windows interrupt mode */ -typedef enum AC_WINTMODE_enum -{ - AC_WINTMODE_ABOVE_gc = (0x00<<2), /* Interrupt on above window */ - AC_WINTMODE_INSIDE_gc = (0x01<<2), /* Interrupt on inside window */ - AC_WINTMODE_BELOW_gc = (0x02<<2), /* Interrupt on below window */ - AC_WINTMODE_OUTSIDE_gc = (0x03<<2), /* Interrupt on outside window */ -} AC_WINTMODE_t; - -/* Window interrupt level */ -typedef enum AC_WINTLVL_enum -{ - AC_WINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ - AC_WINTLVL_LO_gc = (0x01<<0), /* Low priority */ - AC_WINTLVL_MED_gc = (0x02<<0), /* Medium priority */ - AC_WINTLVL_HI_gc = (0x03<<0), /* High priority */ -} AC_WINTLVL_t; - -/* Window mode state */ -typedef enum AC_WSTATE_enum -{ - AC_WSTATE_ABOVE_gc = (0x00<<6), /* Signal above window */ - AC_WSTATE_INSIDE_gc = (0x01<<6), /* Signal inside window */ - AC_WSTATE_BELOW_gc = (0x02<<6), /* Signal below window */ -} AC_WSTATE_t; - - -/* --------------------------------------------------------------------------- -RTC - Real-Time Clounter --------------------------------------------------------------------------- -*/ - -/* Real-Time Counter */ -typedef struct RTC_struct -{ - register8_t CTRL; /* Control Register */ - register8_t STATUS; /* Status Register */ - register8_t INTCTRL; /* Interrupt Control Register */ - register8_t INTFLAGS; /* Interrupt Flags */ - register8_t TEMP; /* Temporary register */ - register8_t reserved_0x05; - register8_t CALIB; /* Calibration Register */ - register8_t reserved_0x07; - _WORDREGISTER(CNT); /* Count Register */ - _WORDREGISTER(PER); /* Period Register */ - _WORDREGISTER(COMP); /* Compare Register */ -} RTC_t; - -/* Prescaler Factor */ -typedef enum RTC_PRESCALER_enum -{ - RTC_PRESCALER_OFF_gc = (0x00<<0), /* RTC Off */ - RTC_PRESCALER_DIV1_gc = (0x01<<0), /* RTC Clock */ - RTC_PRESCALER_DIV2_gc = (0x02<<0), /* RTC Clock / 2 */ - RTC_PRESCALER_DIV8_gc = (0x03<<0), /* RTC Clock / 8 */ - RTC_PRESCALER_DIV16_gc = (0x04<<0), /* RTC Clock / 16 */ - RTC_PRESCALER_DIV64_gc = (0x05<<0), /* RTC Clock / 64 */ - RTC_PRESCALER_DIV256_gc = (0x06<<0), /* RTC Clock / 256 */ - RTC_PRESCALER_DIV1024_gc = (0x07<<0), /* RTC Clock / 1024 */ -} RTC_PRESCALER_t; - -/* Compare Interrupt level */ -typedef enum RTC_COMPINTLVL_enum -{ - RTC_COMPINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ - RTC_COMPINTLVL_LO_gc = (0x01<<2), /* Low Level */ - RTC_COMPINTLVL_MED_gc = (0x02<<2), /* Medium Level */ - RTC_COMPINTLVL_HI_gc = (0x03<<2), /* High Level */ -} RTC_COMPINTLVL_t; - -/* Overflow Interrupt level */ -typedef enum RTC_OVFINTLVL_enum -{ - RTC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - RTC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ - RTC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ - RTC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ -} RTC_OVFINTLVL_t; - - -/* --------------------------------------------------------------------------- -XCL - XMEGA Custom Logic --------------------------------------------------------------------------- -*/ - -/* XMEGA Custom Logic */ -typedef struct XCL_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t CTRLC; /* Control Register C */ - register8_t CTRLD; /* Control Register D */ - register8_t CTRLE; /* Control Register E */ - register8_t CTRLF; /* Control Register F */ - register8_t CTRLG; /* Control Register G */ - register8_t INTCTRL; /* Interrupt Control Register */ - register8_t INTFLAGS; /* Interrupt Flag Register */ - register8_t PLC; /* Peripheral Lenght Control Register */ - register8_t CNTL; /* Counter Register Low */ - register8_t CNTH; /* Counter Register High */ - register8_t CMPL; /* Compare Register Low */ - register8_t CMPH; /* Compare Register High */ - register8_t PERCAPTL; /* Period or Capture Register Low */ - register8_t PERCAPTH; /* Period or Capture Register High */ -} XCL_t; - -/* LUT0 Output Enable */ -typedef enum XCL_LUTOUTEN_enum -{ - XCL_LUTOUTEN_DISABLE_gc = (0x00<<6), /* LUT0 output disabled */ - XCL_LUTOUTEN_PIN0_gc = (0x01<<6), /* LUT0 Output to pin 0 */ - XCL_LUTOUTEN_PIN4_gc = (0x02<<6), /* LUT0 Output to pin 4 */ -} XCL_LUTOUTEN_t; - -/* Port Selection */ -typedef enum XCL_PORTSEL_enum -{ - XCL_PORTSEL_PC_gc = (0x00<<4), /* Port C for LUT or USARTC0 for PEC */ - XCL_PORTSEL_PD_gc = (0x01<<4), /* Port D for LUT or USARTD0 for PEC */ -} XCL_PORTSEL_t; - -/* LUT Configuration */ -typedef enum XCL_LUTCONF_enum -{ - XCL_LUTCONF_2LUT2IN_gc = (0x00<<0), /* 2-Input two LUT */ - XCL_LUTCONF_2LUT1IN_gc = (0x01<<0), /* Two LUT with duplicated input */ - XCL_LUTCONF_2LUT3IN_gc = (0x02<<0), /* Two LUT with one common input */ - XCL_LUTCONF_1LUT3IN_gc = (0x03<<0), /* 3-Input LUT */ - XCL_LUTCONF_MUX_gc = (0x04<<0), /* One LUT Mux */ - XCL_LUTCONF_DLATCH_gc = (0x05<<0), /* One D-Latch LUT */ - XCL_LUTCONF_RSLATCH_gc = (0x06<<0), /* One RS-Latch LUT */ - XCL_LUTCONF_DFF_gc = (0x07<<0), /* One DFF LUT */ -} XCL_LUTCONF_t; - -/* Input Selection */ -typedef enum XCL_INSEL_enum -{ - XCL_INSEL_EVSYS_gc = (0x00<<6), /* Event system selected as source */ - XCL_INSEL_XCL_gc = (0x01<<6), /* XCL selected as source */ - XCL_INSEL_PINL_gc = (0x02<<6), /* LSB port pin selected as source */ - XCL_INSEL_PINH_gc = (0x03<<6), /* MSB port pin selected as source */ -} XCL_INSEL_t; - -/* Delay Configuration on LUT */ -typedef enum XCL_DLYCONF_enum -{ - XCL_DLYCONF_DISABLE_gc = (0x00<<2), /* Delay element disabled */ - XCL_DLYCONF_IN_gc = (0x01<<2), /* Delay enabled on LUT input */ - XCL_DLYCONF_OUT_gc = (0x02<<2), /* Delay enabled on LUT output */ -} XCL_DLYCONF_t; - -/* Delay Selection */ -typedef enum XCL_DLYSEL_enum -{ - XCL_DLYSEL_DLY11_gc = (0x00<<4), /* One cycle delay for each LUT1 and LUT0 */ - XCL_DLYSEL_DLY12_gc = (0x01<<4), /* One cycle delay for LUT1 and two cycles for LUT0 */ - XCL_DLYSEL_DLY21_gc = (0x02<<4), /* Two cycles delay for LUT1 and one cycle for LUT0 */ - XCL_DLYSEL_DLY22_gc = (0x03<<4), /* Two cycle delays for each LUT1 and LUT0 */ -} XCL_DLYSEL_t; - -/* Clock Selection */ -typedef enum XCL_CLKSEL_enum -{ - XCL_CLKSEL_OFF_gc = (0x00<<0), /* OFF */ - XCL_CLKSEL_DIV1_gc = (0x01<<0), /* Prescaler clk */ - XCL_CLKSEL_DIV2_gc = (0x02<<0), /* Prescaler clk/2 */ - XCL_CLKSEL_DIV4_gc = (0x03<<0), /* Prescaler clk/4 */ - XCL_CLKSEL_DIV8_gc = (0x04<<0), /* Prescaler clk/8 */ - XCL_CLKSEL_DIV64_gc = (0x05<<0), /* Prescaler clk/64 */ - XCL_CLKSEL_DIV256_gc = (0x06<<0), /* Prescaler clk/256 */ - XCL_CLKSEL_DIV1024_gc = (0x07<<0), /* Prescaler clk/1024 */ - XCL_CLKSEL_EVCH0_gc = (0x08<<0), /* Event channel 0 */ - XCL_CLKSEL_EVCH1_gc = (0x09<<0), /* Event channel 1 */ - XCL_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event channel 2 */ - XCL_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event channel 3 */ - XCL_CLKSEL_EVCH4_gc = (0x0C<<0), /* Event channel 4 */ - XCL_CLKSEL_EVCH5_gc = (0x0D<<0), /* Event channel 5 */ - XCL_CLKSEL_EVCH6_gc = (0x0E<<0), /* Event channel 6 */ - XCL_CLKSEL_EVCH7_gc = (0x0F<<0), /* Event channel 7 */ -} XCL_CLKSEL_t; - -/* Timer/Counter Command Selection */ -typedef enum XCL_CMDSEL_enum -{ - XCL_CMDSEL_NONE_gc = (0x00<<7), /* None */ - XCL_CMDSEL_RESTART_gc = (0x01<<7), /* Force restart */ -} XCL_CMDSEL_t; - -/* Timer/Counter Selection */ -typedef enum XCL_TCSEL_enum -{ - XCL_TCSEL_TC16_gc = (0x00<<4), /* 16-bit timer/counter */ - XCL_TCSEL_BTC0_gc = (0x01<<4), /* One 8-bit timer/counter */ - XCL_TCSEL_BTC01_gc = (0x02<<4), /* Two 8-bit timer/counters */ - XCL_TCSEL_BTC0PEC1_gc = (0x03<<4), /* One 8-bit timer/counter and one 8-bit peripheral counter */ - XCL_TCSEL_PEC0BTC1_gc = (0x04<<4), /* One 8-bit timer/counter and one 8-bit peripheral counter */ - XCL_TCSEL_PEC01_gc = (0x05<<4), /* Two 8-bit peripheral counters */ - XCL_TCSEL_BTC0PEC2_gc = (0x06<<4), /* One 8-bit timer/counter and two 4-bit peripheral counters */ -} XCL_TCSEL_t; - -/* Timer/Counter Mode */ -typedef enum XCL_TCMODE_enum -{ - XCL_TCMODE_NORMAL_gc = (0x00<<0), /* Normal mode with compare/period */ - XCL_TCMODE_CAPT_gc = (0x01<<0), /* Capture mode */ - XCL_TCMODE_PWM_gc = (0x02<<0), /* Single Slope PWM */ -} XCL_TCMODE_t; - -/* Compare Output Value Timer */ -typedef enum XCL_CMPEN_enum -{ - XCL_CMPEN_CLEAR_gc = (0x00<<5), /* Clear WG Output */ - XCL_CMPEN_SET_gc = (0x01<<5), /* Set WG Output */ -} XCL_CMPEN_t; - -/* Command Enable */ -typedef enum XCL_CMDEN_enum -{ - XCL_CMDEN_DISABLE_gc = (0x00<<6), /* Command Ignored */ - XCL_CMDEN_CMD0_gc = (0x01<<6), /* Command valid for timer/counter 0 */ - XCL_CMDEN_CMD1_gc = (0x02<<6), /* Command valid for timer/counter 1 */ - XCL_CMDEN_CMD01_gc = (0x03<<6), /* Command valid for both timer/counter 0 and 1 */ -} XCL_CMDEN_t; - -/* Timer/Counter Event Source Selection */ -typedef enum XCL_EVSRC_enum -{ - XCL_EVSRC_EVCH0_gc = (0x00<<0), /* Event channel 0 */ - XCL_EVSRC_EVCH1_gc = (0x01<<0), /* Event channel 1 */ - XCL_EVSRC_EVCH2_gc = (0x02<<0), /* Event channel 2 */ - XCL_EVSRC_EVCH3_gc = (0x03<<0), /* Event channel 3 */ - XCL_EVSRC_EVCH4_gc = (0x04<<0), /* Event channel 4 */ - XCL_EVSRC_EVCH5_gc = (0x05<<0), /* Event channel 5 */ - XCL_EVSRC_EVCH6_gc = (0x06<<0), /* Event channel 6 */ - XCL_EVSRC_EVCH7_gc = (0x07<<0), /* Event channel 7 */ -} XCL_EVSRC_t; - -/* Timer/Counter Event Action Selection */ -typedef enum XCL_EVACT_enum -{ - XCL_EVACT_INPUT_gc = (0x00<<5), /* Input Capture */ - XCL_EVACT_FREQ_gc = (0x01<<5), /* Frequency Capture */ - XCL_EVACT_PW_gc = (0x02<<5), /* Pulse Width Capture */ - XCL_EVACT_RESTART_gc = (0x03<<5), /* Restart timer/counter */ -} XCL_EVACT_t; - -/* Underflow Interrupt level */ -typedef enum XCL_UNF_INTLVL_enum -{ - XCL_UNF_INTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ - XCL_UNF_INTLVL_LO_gc = (0x01<<2), /* Low Level */ - XCL_UNF_INTLVL_MED_gc = (0x02<<2), /* Medium Level */ - XCL_UNF_INTLVL_HI_gc = (0x03<<2), /* High Level */ -} XCL_UNF_INTLVL_t; - -/* Compare/Capture Interrupt level */ -typedef enum XCL_CC_INTLVL_enum -{ - XCL_CC_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - XCL_CC_INTLVL_LO_gc = (0x01<<0), /* Low Level */ - XCL_CC_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ - XCL_CC_INTLVL_HI_gc = (0x03<<0), /* High Level */ -} XCL_CC_INTLVL_t; - - -/* --------------------------------------------------------------------------- -TWI - Two-Wire Interface --------------------------------------------------------------------------- -*/ - -/* */ -typedef struct TWI_MASTER_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t CTRLC; /* Control Register C */ - register8_t STATUS; /* Status Register */ - register8_t BAUD; /* Baurd Rate Control Register */ - register8_t ADDR; /* Address Register */ - register8_t DATA; /* Data Register */ -} TWI_MASTER_t; - - -/* */ -typedef struct TWI_SLAVE_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t STATUS; /* Status Register */ - register8_t ADDR; /* Address Register */ - register8_t DATA; /* Data Register */ - register8_t ADDRMASK; /* Address Mask Register */ -} TWI_SLAVE_t; - - -/* */ -typedef struct TWI_TIMEOUT_struct -{ - register8_t TOS; /* Timeout Status Register */ - register8_t TOCONF; /* Timeout Configuration Register */ -} TWI_TIMEOUT_t; - - -/* Two-Wire Interface */ -typedef struct TWI_struct -{ - register8_t CTRL; /* TWI Common Control Register */ - TWI_MASTER_t MASTER; /* TWI master module */ - TWI_SLAVE_t SLAVE; /* TWI slave module */ - TWI_TIMEOUT_t TIMEOUT; /* TWI SMBUS timeout module */ -} TWI_t; - -/* SDA Hold Time */ -typedef enum TWI_SDAHOLD_enum -{ - TWI_SDAHOLD_OFF_gc = (0x00<<4), /* SDA Hold Time off */ - TWI_SDAHOLD_50NS_gc = (0x01<<4), /* SDA Hold Time 50 ns */ - TWI_SDAHOLD_300NS_gc = (0x02<<4), /* SDA Hold Time 300 ns */ - TWI_SDAHOLD_400NS_gc = (0x03<<4), /* SDA Hold Time 400 ns */ -} TWI_SDAHOLD_t; - -/* Master Interrupt Level */ -typedef enum TWI_MASTER_INTLVL_enum -{ - TWI_MASTER_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ - TWI_MASTER_INTLVL_LO_gc = (0x01<<6), /* Low Level */ - TWI_MASTER_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ - TWI_MASTER_INTLVL_HI_gc = (0x03<<6), /* High Level */ -} TWI_MASTER_INTLVL_t; - -/* Inactive Timeout */ -typedef enum TWI_MASTER_TIMEOUT_enum -{ - TWI_MASTER_TIMEOUT_DISABLED_gc = (0x00<<2), /* Bus Timeout Disabled */ - TWI_MASTER_TIMEOUT_50US_gc = (0x01<<2), /* 50 Microseconds */ - TWI_MASTER_TIMEOUT_100US_gc = (0x02<<2), /* 100 Microseconds */ - TWI_MASTER_TIMEOUT_200US_gc = (0x03<<2), /* 200 Microseconds */ -} TWI_MASTER_TIMEOUT_t; - -/* Master Command */ -typedef enum TWI_MASTER_CMD_enum -{ - TWI_MASTER_CMD_NOACT_gc = (0x00<<0), /* No Action */ - TWI_MASTER_CMD_REPSTART_gc = (0x01<<0), /* Issue Repeated Start Condition */ - TWI_MASTER_CMD_RECVTRANS_gc = (0x02<<0), /* Receive or Transmit Data */ - TWI_MASTER_CMD_STOP_gc = (0x03<<0), /* Issue Stop Condition */ -} TWI_MASTER_CMD_t; - -/* Master Bus State */ -typedef enum TWI_MASTER_BUSSTATE_enum -{ - TWI_MASTER_BUSSTATE_UNKNOWN_gc = (0x00<<0), /* Unknown Bus State */ - TWI_MASTER_BUSSTATE_IDLE_gc = (0x01<<0), /* Bus is Idle */ - TWI_MASTER_BUSSTATE_OWNER_gc = (0x02<<0), /* This Module Controls The Bus */ - TWI_MASTER_BUSSTATE_BUSY_gc = (0x03<<0), /* The Bus is Busy */ -} TWI_MASTER_BUSSTATE_t; - -/* Slave Interrupt Level */ -typedef enum TWI_SLAVE_INTLVL_enum -{ - TWI_SLAVE_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ - TWI_SLAVE_INTLVL_LO_gc = (0x01<<6), /* Low Level */ - TWI_SLAVE_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ - TWI_SLAVE_INTLVL_HI_gc = (0x03<<6), /* High Level */ -} TWI_SLAVE_INTLVL_t; - -/* Slave Command */ -typedef enum TWI_SLAVE_CMD_enum -{ - TWI_SLAVE_CMD_NOACT_gc = (0x00<<0), /* No Action */ - TWI_SLAVE_CMD_COMPTRANS_gc = (0x02<<0), /* Used To Complete a Transaction */ - TWI_SLAVE_CMD_RESPONSE_gc = (0x03<<0), /* Used in Response to Address/Data Interrupt */ -} TWI_SLAVE_CMD_t; - -/* Master Timeout */ -typedef enum TWI_MASTER_TTIMEOUT_enum -{ - TWI_MASTER_TTIMEOUT_25MS_gc = (0x00<<0), /* 25 Milliseconds */ - TWI_MASTER_TTIMEOUT_24MS_gc = (0x01<<0), /* 24 Milliseconds */ - TWI_MASTER_TTIMEOUT_23MS_gc = (0x02<<0), /* 23 Milliseconds */ - TWI_MASTER_TTIMEOUT_22MS_gc = (0x03<<0), /* 22 Milliseconds */ - TWI_MASTER_TTIMEOUT_26MS_gc = (0x04<<0), /* 26 Milliseconds */ - TWI_MASTER_TTIMEOUT_27MS_gc = (0x05<<0), /* 27 Milliseconds */ - TWI_MASTER_TTIMEOUT_28MS_gc = (0x06<<0), /* 28 Milliseconds */ - TWI_MASTER_TTIMEOUT_29MS_gc = (0x07<<0), /* 29 Milliseconds */ -} TWI_MASTER_TTIMEOUT_t; - -/* Slave Ttimeout */ -typedef enum TWI_SLAVE_TTIMEOUT_enum -{ - TWI_SLAVE_TTIMEOUT_25MS_gc = (0x00<<5), /* 25 Milliseconds */ - TWI_SLAVE_TTIMEOUT_24MS_gc = (0x01<<5), /* 24 Milliseconds */ - TWI_SLAVE_TTIMEOUT_23MS_gc = (0x02<<5), /* 23 Milliseconds */ - TWI_SLAVE_TTIMEOUT_22MS_gc = (0x03<<5), /* 22 Milliseconds */ - TWI_SLAVE_TTIMEOUT_26MS_gc = (0x04<<5), /* 26 Milliseconds */ - TWI_SLAVE_TTIMEOUT_27MS_gc = (0x05<<5), /* 27 Milliseconds */ - TWI_SLAVE_TTIMEOUT_28MS_gc = (0x06<<5), /* 28 Milliseconds */ - TWI_SLAVE_TTIMEOUT_29MS_gc = (0x07<<5), /* 29 Milliseconds */ -} TWI_SLAVE_TTIMEOUT_t; - -/* Master/Slave Extend Timeout */ -typedef enum TWI_MASTER_TMSEXT_enum -{ - TWI_MASTER_TMSEXT_10MS25MS_gc = (0x00<<3), /* Tmext 10ms Tsext 25ms */ - TWI_MASTER_TMSEXT_9MS24MS_gc = (0x01<<3), /* Tmext 9ms Tsext 24ms */ - TWI_MASTER_TMSEXT_11MS26MS_gc = (0x02<<3), /* Tmext 11ms Tsext 26ms */ - TWI_MASTER_TMSEXT_12MS27MS_gc = (0x03<<3), /* Tmext 12ms Tsext 27ms */ -} TWI_MASTER_TMSEXT_t; - - -/* --------------------------------------------------------------------------- -PORT - Port Configuration --------------------------------------------------------------------------- -*/ - -/* I/O Ports */ -typedef struct PORT_struct -{ - register8_t DIR; /* I/O Port Data Direction */ - register8_t DIRSET; /* I/O Port Data Direction Set */ - register8_t DIRCLR; /* I/O Port Data Direction Clear */ - register8_t DIRTGL; /* I/O Port Data Direction Toggle */ - register8_t OUT; /* I/O Port Output */ - register8_t OUTSET; /* I/O Port Output Set */ - register8_t OUTCLR; /* I/O Port Output Clear */ - register8_t OUTTGL; /* I/O Port Output Toggle */ - register8_t IN; /* I/O port Input */ - register8_t INTCTRL; /* Interrupt Control Register */ - register8_t INTMASK; /* Port Interrupt Mask */ - register8_t reserved_0x0B; - register8_t INTFLAGS; /* Interrupt Flag Register */ - register8_t reserved_0x0D; - register8_t REMAP; /* Pin Remap Register */ - register8_t reserved_0x0F; - register8_t PIN0CTRL; /* Pin 0 Control Register */ - register8_t PIN1CTRL; /* Pin 1 Control Register */ - register8_t PIN2CTRL; /* Pin 2 Control Register */ - register8_t PIN3CTRL; /* Pin 3 Control Register */ - register8_t PIN4CTRL; /* Pin 4 Control Register */ - register8_t PIN5CTRL; /* Pin 5 Control Register */ - register8_t PIN6CTRL; /* Pin 6 Control Register */ - register8_t PIN7CTRL; /* Pin 7 Control Register */ -} PORT_t; - -/* Port Interrupt Level */ -typedef enum PORT_INTLVL_enum -{ - PORT_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - PORT_INTLVL_LO_gc = (0x01<<0), /* Low Level */ - PORT_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ - PORT_INTLVL_HI_gc = (0x03<<0), /* High Level */ -} PORT_INTLVL_t; - -/* Output/Pull Configuration */ -typedef enum PORT_OPC_enum -{ - PORT_OPC_TOTEM_gc = (0x00<<3), /* Totempole */ - PORT_OPC_BUSKEEPER_gc = (0x01<<3), /* Totempole w/ Bus keeper on Input and Output */ - PORT_OPC_PULLDOWN_gc = (0x02<<3), /* Totempole w/ Pull-down on Input */ - PORT_OPC_PULLUP_gc = (0x03<<3), /* Totempole w/ Pull-up on Input */ - PORT_OPC_WIREDOR_gc = (0x04<<3), /* Wired OR */ - PORT_OPC_WIREDAND_gc = (0x05<<3), /* Wired AND */ - PORT_OPC_WIREDORPULL_gc = (0x06<<3), /* Wired OR w/ Pull-down */ - PORT_OPC_WIREDANDPULL_gc = (0x07<<3), /* Wired AND w/ Pull-up */ -} PORT_OPC_t; - -/* Input/Sense Configuration */ -typedef enum PORT_ISC_enum -{ - PORT_ISC_BOTHEDGES_gc = (0x00<<0), /* Sense Both Edges */ - PORT_ISC_RISING_gc = (0x01<<0), /* Sense Rising Edge */ - PORT_ISC_FALLING_gc = (0x02<<0), /* Sense Falling Edge */ - PORT_ISC_LEVEL_gc = (0x03<<0), /* Sense Level (Transparent For Events) */ - PORT_ISC_FORCE_ENABLE_gc = (0x06<<0), /* Digital Input Buffer Forced Enable */ - PORT_ISC_INPUT_DISABLE_gc = (0x07<<0), /* Disable Digital Input Buffer */ -} PORT_ISC_t; - - -/* --------------------------------------------------------------------------- -TC - 16-bit Timer/Counter With PWM --------------------------------------------------------------------------- -*/ - -/* 16-bit Timer/Counter 4 */ -typedef struct TC4_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t CTRLC; /* Control register C */ - register8_t CTRLD; /* Control Register D */ - register8_t CTRLE; /* Control Register E */ - register8_t CTRLF; /* Control Register F */ - register8_t INTCTRLA; /* Interrupt Control Register A */ - register8_t INTCTRLB; /* Interrupt Control Register B */ - register8_t CTRLGCLR; /* Control Register G Clear */ - register8_t CTRLGSET; /* Control Register G Set */ - register8_t CTRLHCLR; /* Control Register H Clear */ - register8_t CTRLHSET; /* Control Register H Set */ - register8_t INTFLAGS; /* Interrupt Flag Register */ - register8_t reserved_0x0D; - register8_t reserved_0x0E; - register8_t TEMP; /* Temporary Register For 16-bit Access */ - register8_t reserved_0x10; - register8_t reserved_0x11; - register8_t reserved_0x12; - register8_t reserved_0x13; - register8_t reserved_0x14; - register8_t reserved_0x15; - register8_t reserved_0x16; - register8_t reserved_0x17; - register8_t reserved_0x18; - register8_t reserved_0x19; - register8_t reserved_0x1A; - register8_t reserved_0x1B; - register8_t reserved_0x1C; - register8_t reserved_0x1D; - register8_t reserved_0x1E; - register8_t reserved_0x1F; - _WORDREGISTER(CNT); /* Count */ - register8_t reserved_0x22; - register8_t reserved_0x23; - register8_t reserved_0x24; - register8_t reserved_0x25; - _WORDREGISTER(PER); /* Period */ - _WORDREGISTER(CCA); /* Compare or Capture A */ - _WORDREGISTER(CCB); /* Compare or Capture B */ - _WORDREGISTER(CCC); /* Compare or Capture C */ - _WORDREGISTER(CCD); /* Compare or Capture D */ - register8_t reserved_0x30; - register8_t reserved_0x31; - register8_t reserved_0x32; - register8_t reserved_0x33; - register8_t reserved_0x34; - register8_t reserved_0x35; - _WORDREGISTER(PERBUF); /* Period Buffer */ - _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ - _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ - _WORDREGISTER(CCCBUF); /* Compare Or Capture C Buffer */ - _WORDREGISTER(CCDBUF); /* Compare Or Capture D Buffer */ -} TC4_t; - - -/* 16-bit Timer/Counter 5 */ -typedef struct TC5_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t CTRLC; /* Control register C */ - register8_t CTRLD; /* Control Register D */ - register8_t CTRLE; /* Control Register E */ - register8_t CTRLF; /* Control Register F */ - register8_t INTCTRLA; /* Interrupt Control Register A */ - register8_t INTCTRLB; /* Interrupt Control Register B */ - register8_t CTRLGCLR; /* Control Register G Clear */ - register8_t CTRLGSET; /* Control Register G Set */ - register8_t CTRLHCLR; /* Control Register H Clear */ - register8_t CTRLHSET; /* Control Register H Set */ - register8_t INTFLAGS; /* Interrupt Flag Register */ - register8_t reserved_0x0D; - register8_t reserved_0x0E; - register8_t TEMP; /* Temporary Register For 16-bit Access */ - register8_t reserved_0x10; - register8_t reserved_0x11; - register8_t reserved_0x12; - register8_t reserved_0x13; - register8_t reserved_0x14; - register8_t reserved_0x15; - register8_t reserved_0x16; - register8_t reserved_0x17; - register8_t reserved_0x18; - register8_t reserved_0x19; - register8_t reserved_0x1A; - register8_t reserved_0x1B; - register8_t reserved_0x1C; - register8_t reserved_0x1D; - register8_t reserved_0x1E; - register8_t reserved_0x1F; - _WORDREGISTER(CNT); /* Count */ - register8_t reserved_0x22; - register8_t reserved_0x23; - register8_t reserved_0x24; - register8_t reserved_0x25; - _WORDREGISTER(PER); /* Period */ - _WORDREGISTER(CCA); /* Compare or Capture A */ - _WORDREGISTER(CCB); /* Compare or Capture B */ - register8_t reserved_0x2C; - register8_t reserved_0x2D; - register8_t reserved_0x2E; - register8_t reserved_0x2F; - register8_t reserved_0x30; - register8_t reserved_0x31; - register8_t reserved_0x32; - register8_t reserved_0x33; - register8_t reserved_0x34; - register8_t reserved_0x35; - _WORDREGISTER(PERBUF); /* Period Buffer */ - _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ - _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ - register8_t reserved_0x3C; - register8_t reserved_0x3D; - register8_t reserved_0x3E; - register8_t reserved_0x3F; -} TC5_t; - -/* Clock Selection */ -typedef enum TC45_CLKSEL_enum -{ - TC45_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */ - TC45_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */ - TC45_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */ - TC45_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */ - TC45_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */ - TC45_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */ - TC45_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */ - TC45_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */ - TC45_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */ - TC45_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */ - TC45_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */ - TC45_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */ - TC45_CLKSEL_EVCH4_gc = (0x0C<<0), /* Event Channel 4 */ - TC45_CLKSEL_EVCH5_gc = (0x0D<<0), /* Event Channel 5 */ - TC45_CLKSEL_EVCH6_gc = (0x0E<<0), /* Event Channel 6 */ - TC45_CLKSEL_EVCH7_gc = (0x0F<<0), /* Event Channel 7 */ -} TC45_CLKSEL_t; - -/* Byte Mode */ -typedef enum TC45_BYTEM_enum -{ - TC45_BYTEM_NORMAL_gc = (0x00<<6), /* 16-bit mode */ - TC45_BYTEM_BYTEMODE_gc = (0x01<<6), /* Timer/Counter Operating in Byte Mode Only */ -} TC45_BYTEM_t; - -/* Circular Enable Mode */ -typedef enum TC45_CIRCEN_enum -{ - TC45_CIRCEN_DISABLE_gc = (0x00<<4), /* Circular Buffer Disabled */ - TC45_CIRCEN_PER_gc = (0x01<<4), /* Circular Buffer Enabled on PER/PERBUF */ - TC45_CIRCEN_CCA_gc = (0x02<<4), /* Circular Buffer Enabled on CCA/CCABUF */ - TC45_CIRCEN_BOTH_gc = (0x03<<4), /* Circular Buffer Enabled on All Buffered Registers */ -} TC45_CIRCEN_t; - -/* Waveform Generation Mode */ -typedef enum TC45_WGMODE_enum -{ - TC45_WGMODE_NORMAL_gc = (0x00<<0), /* Normal Mode */ - TC45_WGMODE_FRQ_gc = (0x01<<0), /* Frequency Generation Mode */ - TC45_WGMODE_SINGLESLOPE_gc = (0x03<<0), /* Single Slope */ - TC45_WGMODE_DSTOP_gc = (0x05<<0), /* Dual Slope, Update on TOP */ - TC45_WGMODE_DSBOTH_gc = (0x06<<0), /* Dual Slope, Both */ - TC45_WGMODE_DSBOTTOM_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */ -} TC45_WGMODE_t; - -/* Event Action */ -typedef enum TC45_EVACT_enum -{ - TC45_EVACT_OFF_gc = (0x00<<5), /* No Event Action */ - TC45_EVACT_FMODE1_gc = (0x01<<5), /* Fault Mode 1 capture */ - TC45_EVACT_FMODE2_gc = (0x02<<5), /* Fault Mode 2 capture */ - TC45_EVACT_UPDOWN_gc = (0x03<<5), /* Up/down count */ - TC45_EVACT_QDEC_gc = (0x04<<5), /* Quadrature decode */ - TC45_EVACT_RESTART_gc = (0x05<<5), /* Restart */ - TC45_EVACT_PWF_gc = (0x06<<5), /* Pulse-width Capture */ -} TC45_EVACT_t; - -/* Event Selection */ -typedef enum TC45_EVSEL_enum -{ - TC45_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ - TC45_EVSEL_CH0_gc = (0x08<<0), /* Event Channel 0 */ - TC45_EVSEL_CH1_gc = (0x09<<0), /* Event Channel 1 */ - TC45_EVSEL_CH2_gc = (0x0A<<0), /* Event Channel 2 */ - TC45_EVSEL_CH3_gc = (0x0B<<0), /* Event Channel 3 */ - TC45_EVSEL_CH4_gc = (0x0C<<0), /* Event Channel 4 */ - TC45_EVSEL_CH5_gc = (0x0D<<0), /* Event Channel 5 */ - TC45_EVSEL_CH6_gc = (0x0E<<0), /* Event Channel 6 */ - TC45_EVSEL_CH7_gc = (0x0F<<0), /* Event Channel 7 */ -} TC45_EVSEL_t; - -/* Compare or Capture Channel A Mode */ -typedef enum TC45_CCAMODE_enum -{ - TC45_CCAMODE_DISABLE_gc = (0x00<<0), /* Channel Disabled */ - TC45_CCAMODE_COMP_gc = (0x01<<0), /* Ouput Compare enabled */ - TC45_CCAMODE_CAPT_gc = (0x02<<0), /* Input Capture enabled */ - TC45_CCAMODE_BOTHCC_gc = (0x03<<0), /* Both Compare and Capture enabled */ -} TC45_CCAMODE_t; - -/* Compare or Capture Channel B Mode */ -typedef enum TC45_CCBMODE_enum -{ - TC45_CCBMODE_DISABLE_gc = (0x00<<2), /* Channel Disabled */ - TC45_CCBMODE_COMP_gc = (0x01<<2), /* Ouput Compare enabled */ - TC45_CCBMODE_CAPT_gc = (0x02<<2), /* Input Capture enabled */ - TC45_CCBMODE_BOTHCC_gc = (0x03<<2), /* Both Compare and Capture enabled */ -} TC45_CCBMODE_t; - -/* Compare or Capture Channel C Mode */ -typedef enum TC45_CCCMODE_enum -{ - TC45_CCCMODE_DISABLE_gc = (0x00<<4), /* Channel Disabled */ - TC45_CCCMODE_COMP_gc = (0x01<<4), /* Ouput Compare enabled */ - TC45_CCCMODE_CAPT_gc = (0x02<<4), /* Input Capture enabled */ - TC45_CCCMODE_BOTHCC_gc = (0x03<<4), /* Both Compare and Capture enabled */ -} TC45_CCCMODE_t; - -/* Compare or Capture Channel D Mode */ -typedef enum TC45_CCDMODE_enum -{ - TC45_CCDMODE_DISABLE_gc = (0x00<<6), /* Channel Disabled */ - TC45_CCDMODE_COMP_gc = (0x01<<6), /* Ouput Compare enabled */ - TC45_CCDMODE_CAPT_gc = (0x02<<6), /* Input Capture enabled */ - TC45_CCDMODE_BOTHCC_gc = (0x03<<6), /* Both Compare and Capture enabled */ -} TC45_CCDMODE_t; - -/* Compare or Capture Low Channel A Mode */ -typedef enum TC45_LCCAMODE_enum -{ - TC45_LCCAMODE_DISABLE_gc = (0x00<<0), /* Channel Disabled */ - TC45_LCCAMODE_COMP_gc = (0x01<<0), /* Ouput Compare enabled */ - TC45_LCCAMODE_CAPT_gc = (0x02<<0), /* Input Capture enabled */ - TC45_LCCAMODE_BOTHCC_gc = (0x03<<0), /* Both Compare and Capture enabled */ -} TC45_LCCAMODE_t; - -/* Compare or Capture Low Channel B Mode */ -typedef enum TC45_LCCBMODE_enum -{ - TC45_LCCBMODE_DISABLE_gc = (0x00<<2), /* Channel Disabled */ - TC45_LCCBMODE_COMP_gc = (0x01<<2), /* Ouput Compare enabled */ - TC45_LCCBMODE_CAPT_gc = (0x02<<2), /* Input Capture enabled */ - TC45_LCCBMODE_BOTHCC_gc = (0x03<<2), /* Both Compare and Capture enabled */ -} TC45_LCCBMODE_t; - -/* Compare or Capture Low Channel C Mode */ -typedef enum TC45_LCCCMODE_enum -{ - TC45_LCCCMODE_DISABLE_gc = (0x00<<4), /* Channel Disabled */ - TC45_LCCCMODE_COMP_gc = (0x01<<4), /* Ouput Compare enabled */ - TC45_LCCCMODE_CAPT_gc = (0x02<<4), /* Input Capture enabled */ - TC45_LCCCMODE_BOTHCC_gc = (0x03<<4), /* Both Compare and Capture enabled */ -} TC45_LCCCMODE_t; - -/* Compare or Capture Low Channel D Mode */ -typedef enum TC45_LCCDMODE_enum -{ - TC45_LCCDMODE_DISABLE_gc = (0x00<<6), /* Channel Disabled */ - TC45_LCCDMODE_COMP_gc = (0x01<<6), /* Ouput Compare enabled */ - TC45_LCCDMODE_CAPT_gc = (0x02<<6), /* Input Capture enabled */ - TC45_LCCDMODE_BOTHCC_gc = (0x03<<6), /* Both Compare and Capture enabled */ -} TC45_LCCDMODE_t; - -/* Compare or Capture High Channel A Mode */ -typedef enum TC45_HCCAMODE_enum -{ - TC45_HCCAMODE_DISABLE_gc = (0x00<<0), /* Channel Disabled */ - TC45_HCCAMODE_COMP_gc = (0x01<<0), /* Ouput Compare enabled */ - TC45_HCCAMODE_CAPT_gc = (0x02<<0), /* Input Capture enabled */ - TC45_HCCAMODE_BOTHCC_gc = (0x03<<0), /* Both Compare and Capture enabled */ -} TC45_HCCAMODE_t; - -/* Compare or Capture High Channel B Mode */ -typedef enum TC45_HCCBMODE_enum -{ - TC45_HCCBMODE_DISABLE_gc = (0x00<<2), /* Channel Disabled */ - TC45_HCCBMODE_COMP_gc = (0x01<<2), /* Ouput Compare enabled */ - TC45_HCCBMODE_CAPT_gc = (0x02<<2), /* Input Capture enabled */ - TC45_HCCBMODE_BOTHCC_gc = (0x03<<2), /* Both Compare and Capture enabled */ -} TC45_HCCBMODE_t; - -/* Compare or Capture High Channel C Mode */ -typedef enum TC45_HCCCMODE_enum -{ - TC45_HCCCMODE_DISABLE_gc = (0x00<<4), /* Channel Disabled */ - TC45_HCCCMODE_COMP_gc = (0x01<<4), /* Ouput Compare enabled */ - TC45_HCCCMODE_CAPT_gc = (0x02<<4), /* Input Capture enabled */ - TC45_HCCCMODE_BOTHCC_gc = (0x03<<4), /* Both Compare and Capture enabled */ -} TC45_HCCCMODE_t; - -/* Compare or Capture High Channel D Mode */ -typedef enum TC45_HCCDMODE_enum -{ - TC45_HCCDMODE_DISABLE_gc = (0x00<<6), /* Channel Disabled */ - TC45_HCCDMODE_COMP_gc = (0x01<<6), /* Ouput Compare enabled */ - TC45_HCCDMODE_CAPT_gc = (0x02<<6), /* Input Capture enabled */ - TC45_HCCDMODE_BOTHCC_gc = (0x03<<6), /* Both Compare and Capture enabled */ -} TC45_HCCDMODE_t; - -/* Timer Trigger Restart Interrupt Level */ -typedef enum TC45_TRGINTLVL_enum -{ - TC45_TRGINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ - TC45_TRGINTLVL_LO_gc = (0x01<<4), /* Low Level */ - TC45_TRGINTLVL_MED_gc = (0x02<<4), /* Medium Level */ - TC45_TRGINTLVL_HI_gc = (0x03<<4), /* High Level */ -} TC45_TRGINTLVL_t; - -/* Error Interrupt Level */ -typedef enum TC45_ERRINTLVL_enum -{ - TC45_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ - TC45_ERRINTLVL_LO_gc = (0x01<<2), /* Low Level */ - TC45_ERRINTLVL_MED_gc = (0x02<<2), /* Medium Level */ - TC45_ERRINTLVL_HI_gc = (0x03<<2), /* High Level */ -} TC45_ERRINTLVL_t; - -/* Overflow Interrupt Level */ -typedef enum TC45_OVFINTLVL_enum -{ - TC45_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - TC45_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ - TC45_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ - TC45_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ -} TC45_OVFINTLVL_t; - -/* Compare or Capture Channel A Interrupt Level */ -typedef enum TC45_CCAINTLVL_enum -{ - TC45_CCAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - TC45_CCAINTLVL_LO_gc = (0x01<<0), /* Low Level */ - TC45_CCAINTLVL_MED_gc = (0x02<<0), /* Medium Level */ - TC45_CCAINTLVL_HI_gc = (0x03<<0), /* High Level */ -} TC45_CCAINTLVL_t; - -/* Compare or Capture Channel B Interrupt Level */ -typedef enum TC45_CCBINTLVL_enum -{ - TC45_CCBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ - TC45_CCBINTLVL_LO_gc = (0x01<<2), /* Low Level */ - TC45_CCBINTLVL_MED_gc = (0x02<<2), /* Medium Level */ - TC45_CCBINTLVL_HI_gc = (0x03<<2), /* High Level */ -} TC45_CCBINTLVL_t; - -/* Compare or Capture Channel C Interrupt Level */ -typedef enum TC45_CCCINTLVL_enum -{ - TC45_CCCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ - TC45_CCCINTLVL_LO_gc = (0x01<<4), /* Low Level */ - TC45_CCCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ - TC45_CCCINTLVL_HI_gc = (0x03<<4), /* High Level */ -} TC45_CCCINTLVL_t; - -/* Compare or Capture Channel D Interrupt Level */ -typedef enum TC45_CCDINTLVL_enum -{ - TC45_CCDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ - TC45_CCDINTLVL_LO_gc = (0x01<<6), /* Low Level */ - TC45_CCDINTLVL_MED_gc = (0x02<<6), /* Medium Level */ - TC45_CCDINTLVL_HI_gc = (0x03<<6), /* High Level */ -} TC45_CCDINTLVL_t; - -/* Compare or Capture Low Channel A Interrupt Level */ -typedef enum TC45_LCCAINTLVL_enum -{ - TC45_LCCAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - TC45_LCCAINTLVL_LO_gc = (0x01<<0), /* Low Level */ - TC45_LCCAINTLVL_MED_gc = (0x02<<0), /* Medium Level */ - TC45_LCCAINTLVL_HI_gc = (0x03<<0), /* High Level */ -} TC45_LCCAINTLVL_t; - -/* Compare or Capture Low Channel B Interrupt Level */ -typedef enum TC45_LCCBINTLVL_enum -{ - TC45_LCCBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ - TC45_LCCBINTLVL_LO_gc = (0x01<<2), /* Low Level */ - TC45_LCCBINTLVL_MED_gc = (0x02<<2), /* Medium Level */ - TC45_LCCBINTLVL_HI_gc = (0x03<<2), /* High Level */ -} TC45_LCCBINTLVL_t; - -/* Compare or Capture Low Channel C Interrupt Level */ -typedef enum TC45_LCCCINTLVL_enum -{ - TC45_LCCCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ - TC45_LCCCINTLVL_LO_gc = (0x01<<4), /* Low Level */ - TC45_LCCCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ - TC45_LCCCINTLVL_HI_gc = (0x03<<4), /* High Level */ -} TC45_LCCCINTLVL_t; - -/* Compare or Capture Low Channel D Interrupt Level */ -typedef enum TC45_LCCDINTLVL_enum -{ - TC45_LCCDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ - TC45_LCCDINTLVL_LO_gc = (0x01<<6), /* Low Level */ - TC45_LCCDINTLVL_MED_gc = (0x02<<6), /* Medium Level */ - TC45_LCCDINTLVL_HI_gc = (0x03<<6), /* High Level */ -} TC45_LCCDINTLVL_t; - -/* Timer/Counter Command */ -typedef enum TC45_CMD_enum -{ - TC45_CMD_NONE_gc = (0x00<<2), /* No Command */ - TC45_CMD_UPDATE_gc = (0x01<<2), /* Force Update */ - TC45_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ - TC45_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ -} TC45_CMD_t; - - -/* --------------------------------------------------------------------------- -FAULT - Fault Extension --------------------------------------------------------------------------- -*/ - -/* Fault Extension */ -typedef struct FAULT_struct -{ - register8_t CTRLA; /* Control A Register */ - register8_t CTRLB; /* Control B Register */ - register8_t CTRLC; /* Control C Register */ - register8_t CTRLD; /* Control D Register */ - register8_t CTRLE; /* Control E Register */ - register8_t STATUS; /* Status Register */ - register8_t CTRLGCLR; /* Control Register G Clear */ - register8_t CTRLGSET; /* Control Register G set */ -} FAULT_t; - -/* Ramp Mode Selection */ -typedef enum FAULT_RAMP_enum -{ - FAULT_RAMP_RAMP1_gc = (0x00<<6), /* Normal Mode */ - FAULT_RAMP_RAMP2_gc = (0x02<<6), /* RAMP2 Mode */ -} FAULT_RAMP_t; - -/* Fault E Input Source Selection */ -typedef enum FAULT_SRCE_enum -{ - FAULT_SRCE_DISABLE_gc = (0x00<<0), /* Fault Protection Disabled */ - FAULT_SRCE_CHN_gc = (0x01<<0), /* Event Channel n */ - FAULT_SRCE_CHN1_gc = (0x02<<0), /* Event Channel n+1 */ - FAULT_SRCE_CHN2_gc = (0x03<<0), /* Event Channel n+2 */ -} FAULT_SRCE_t; - -/* Fault A Halt Action Selection */ -typedef enum FAULT_HALTA_enum -{ - FAULT_HALTA_DISABLE_gc = (0x00<<5), /* Halt Action Disabled */ - FAULT_HALTA_HW_gc = (0x01<<5), /* Hardware Halt Action */ - FAULT_HALTA_SW_gc = (0x02<<5), /* Software Halt Action */ -} FAULT_HALTA_t; - -/* Fault A Source Selection */ -typedef enum FAULT_SRCA_enum -{ - FAULT_SRCA_DISABLE_gc = (0x00<<0), /* Fault A Disabled */ - FAULT_SRCA_CHN_gc = (0x01<<0), /* Event Channel n */ - FAULT_SRCA_CHN1_gc = (0x02<<0), /* Event Channel n+1 */ - FAULT_SRCA_LINK_gc = (0x03<<0), /* Fault A linked to Fault B State from previous cycle */ -} FAULT_SRCA_t; - -/* Fault B Halt Action Selection */ -typedef enum FAULT_HALTB_enum -{ - FAULT_HALTB_DISABLE_gc = (0x00<<5), /* Halt Action Disabled */ - FAULT_HALTB_HW_gc = (0x01<<5), /* Hardware Halt Action */ - FAULT_HALTB_SW_gc = (0x02<<5), /* Software Halt Action */ -} FAULT_HALTB_t; - -/* Fault B Source Selection */ -typedef enum FAULT_SRCB_enum -{ - FAULT_SRCB_DISABLE_gc = (0x00<<0), /* Fault B disabled */ - FAULT_SRCB_CHN_gc = (0x01<<0), /* Event Channel n */ - FAULT_SRCB_CHN1_gc = (0x02<<0), /* Event Channel n+1 */ - FAULT_SRCB_LINK_gc = (0x03<<0), /* Fault B linked to Fault A State from previous cycle */ -} FAULT_SRCB_t; - -/* Channel index Command */ -typedef enum FAULT_IDXCMD_enum -{ - FAULT_IDXCMD_DISABLE_gc = (0x00<<3), /* Command Disabled */ - FAULT_IDXCMD_SET_gc = (0x01<<3), /* Force Cycle B in Next Cycle */ - FAULT_IDXCMD_CLEAR_gc = (0x02<<3), /* Force Cycle A in Next Cycle */ - FAULT_IDXCMD_HOLD_gc = (0x03<<3), /* Hold Current Cycle Index in Next Cycle */ -} FAULT_IDXCMD_t; - - -/* --------------------------------------------------------------------------- -WEX - Waveform Extension --------------------------------------------------------------------------- -*/ - -/* Waveform Extension */ -typedef struct WEX_struct -{ - register8_t CTRL; /* Control Register */ - register8_t DTBOTH; /* Dead-time Concurrent Write to Both Sides Register */ - register8_t DTLS; /* Dead-time Low Side Register */ - register8_t DTHS; /* Dead-time High Side Register */ - register8_t STATUSCLR; /* Status Clear Register */ - register8_t STATUSSET; /* Status Set Register */ - register8_t SWAP; /* Swap Register */ - register8_t PGO; /* Pattern Generation Override Register */ - register8_t PGV; /* Pattern Generation Value Register */ - register8_t reserved_0x09; - register8_t SWAPBUF; /* Dead Time Low Side Buffer */ - register8_t PGOBUF; /* Pattern Generation Overwrite Buffer Register */ - register8_t PGVBUF; /* Pattern Generation Value Buffer Register */ - register8_t reserved_0x0D; - register8_t reserved_0x0E; - register8_t OUTOVDIS; /* Output Override Disable Register */ -} WEX_t; - -/* Output Matrix Mode */ -typedef enum WEX_OTMX_enum -{ - WEX_OTMX_DEFAULT_gc = (0x00<<4), /* Default Ouput Matrix Mode */ - WEX_OTMX_FIRST_gc = (0x01<<4), /* First Output matrix Mode */ - WEX_OTMX_SECOND_gc = (0x02<<4), /* Second Output matrix Mode */ - WEX_OTMX_THIRD_gc = (0x03<<4), /* Third Output matrix Mode */ - WEX_OTMX_FOURTH_gc = (0x04<<4), /* Fourth Output matrix Mode */ -} WEX_OTMX_t; - - -/* --------------------------------------------------------------------------- -HIRES - High-Resolution Extension --------------------------------------------------------------------------- -*/ - -/* High-Resolution Extension */ -typedef struct HIRES_struct -{ - register8_t CTRLA; /* Control Register A */ -} HIRES_t; - -/* High Resolution Plus Mode */ -typedef enum HIRES_HRPLUS_enum -{ - HIRES_HRPLUS_NONE_gc = (0x00<<2), /* No Hi-Res Plus */ - HIRES_HRPLUS_HRP4_gc = (0x01<<2), /* Hi-Res Plus enabled on Timer 4 */ - HIRES_HRPLUS_HRP5_gc = (0x02<<2), /* Hi-Res Plus enabled on Timer 5 */ - HIRES_HRPLUS_BOTH_gc = (0x03<<2), /* Hi-Res Plus enabled on Timer 4 and 5 */ -} HIRES_HRPLUS_t; - -/* High Resolution Mode */ -typedef enum HIRES_HREN_enum -{ - HIRES_HREN_NONE_gc = (0x00<<0), /* No Hi-Res */ - HIRES_HREN_HRP4_gc = (0x01<<0), /* Hi-Res enabled on Timer 4 */ - HIRES_HREN_HRP5_gc = (0x02<<0), /* Hi-Res enabled on Timer 5 */ - HIRES_HREN_BOTH_gc = (0x03<<0), /* Hi-Res enabled on Timer 4 and 5 */ -} HIRES_HREN_t; - - -/* --------------------------------------------------------------------------- -USART - Universal Asynchronous Receiver-Transmitter --------------------------------------------------------------------------- -*/ - -/* Universal Synchronous/Asynchronous Receiver/Transmitter */ -typedef struct USART_struct -{ - register8_t DATA; /* Data Register */ - register8_t STATUS; /* Status Register */ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t CTRLC; /* Control Register C */ - register8_t CTRLD; /* Control Register D */ - register8_t BAUDCTRLA; /* Baud Rate Control Register A */ - register8_t BAUDCTRLB; /* Baud Rate Control Register B */ -} USART_t; - -/* Receive Start Interrupt level */ -typedef enum USART_RXSINTLVL_enum -{ - USART_RXSINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - USART_RXSINTLVL_LO_gc = (0x01<<0), /* Low Level */ - USART_RXSINTLVL_MED_gc = (0x02<<0), /* Medium Level */ - USART_RXSINTLVL_HI_gc = (0x03<<0), /* High Level */ -} USART_RXSINTLVL_t; - -/* Receive Complete Interrupt level */ -typedef enum USART_RXCINTLVL_enum -{ - USART_RXCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ - USART_RXCINTLVL_LO_gc = (0x01<<4), /* Low Level */ - USART_RXCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ - USART_RXCINTLVL_HI_gc = (0x03<<4), /* High Level */ -} USART_RXCINTLVL_t; - -/* Transmit Complete Interrupt level */ -typedef enum USART_TXCINTLVL_enum -{ - USART_TXCINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ - USART_TXCINTLVL_LO_gc = (0x01<<2), /* Low Level */ - USART_TXCINTLVL_MED_gc = (0x02<<2), /* Medium Level */ - USART_TXCINTLVL_HI_gc = (0x03<<2), /* High Level */ -} USART_TXCINTLVL_t; - -/* Data Register Empty Interrupt level */ -typedef enum USART_DREINTLVL_enum -{ - USART_DREINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - USART_DREINTLVL_LO_gc = (0x01<<0), /* Low Level */ - USART_DREINTLVL_MED_gc = (0x02<<0), /* Medium Level */ - USART_DREINTLVL_HI_gc = (0x03<<0), /* High Level */ -} USART_DREINTLVL_t; - -/* Character Size */ -typedef enum USART_CHSIZE_enum -{ - USART_CHSIZE_5BIT_gc = (0x00<<0), /* Character size: 5 bit */ - USART_CHSIZE_6BIT_gc = (0x01<<0), /* Character size: 6 bit */ - USART_CHSIZE_7BIT_gc = (0x02<<0), /* Character size: 7 bit */ - USART_CHSIZE_8BIT_gc = (0x03<<0), /* Character size: 8 bit */ - USART_CHSIZE_9BIT_gc = (0x07<<0), /* Character size: 9 bit */ -} USART_CHSIZE_t; - -/* Communication Mode */ -typedef enum USART_CMODE_enum -{ - USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6), /* Asynchronous Mode */ - USART_CMODE_SYNCHRONOUS_gc = (0x01<<6), /* Synchronous Mode */ - USART_CMODE_IRDA_gc = (0x02<<6), /* IrDA Mode */ - USART_CMODE_MSPI_gc = (0x03<<6), /* Master SPI Mode */ -} USART_CMODE_t; - -/* Parity Mode */ -typedef enum USART_PMODE_enum -{ - USART_PMODE_DISABLED_gc = (0x00<<4), /* No Parity */ - USART_PMODE_EVEN_gc = (0x02<<4), /* Even Parity */ - USART_PMODE_ODD_gc = (0x03<<4), /* Odd Parity */ -} USART_PMODE_t; - -/* Encoding and Decoding Type */ -typedef enum USART_DECTYPE_enum -{ - USART_DECTYPE_DATA_gc = (0x00<<4), /* DATA Field Encoding */ - USART_DECTYPE_SDATA_gc = (0x02<<4), /* Start and Data Fields Encoding */ - USART_DECTYPE_NOTSDATA_gc = (0x03<<4), /* Start and Data Fields Encoding, with invertion in START field */ -} USART_DECTYPE_t; - -/* XCL LUT Action */ -typedef enum USART_LUTACT_enum -{ - USART_LUTACT_OFF_gc = (0x00<<2), /* Standard Frame Configuration */ - USART_LUTACT_RX_gc = (0x01<<2), /* Receiver Decoding Enabled */ - USART_LUTACT_TX_gc = (0x02<<2), /* Transmitter Encoding Enabled */ - USART_LUTACT_BOTH_gc = (0x03<<2), /* Both Encoding and Decoding Enabled */ -} USART_LUTACT_t; - -/* XCL Peripheral Counter Action */ -typedef enum USART_PECACT_enum -{ - USART_PECACT_OFF_gc = (0x00<<0), /* Standard Mode */ - USART_PECACT_PEC0_gc = (0x01<<0), /* Variable Data Lenght in Reception */ - USART_PECACT_PEC1_gc = (0x02<<0), /* Variable Data Lenght in Transmission */ - USART_PECACT_PERC01_gc = (0x03<<0), /* Variable Data Lenght in both Reception and Transmission */ -} USART_PECACT_t; - - -/* --------------------------------------------------------------------------- -SPI - Serial Peripheral Interface --------------------------------------------------------------------------- -*/ - -/* Serial Peripheral Interface with Buffer Modes */ -typedef struct SPI_struct -{ - register8_t CTRL; /* Control Register */ - register8_t INTCTRL; /* Interrupt Control Register */ - register8_t STATUS; /* Status Register */ - register8_t DATA; /* Data Register */ - register8_t CTRLB; /* Control Register B */ -} SPI_t; - -/* SPI Mode */ -typedef enum SPI_MODE_enum -{ - SPI_MODE_0_gc = (0x00<<2), /* SPI Mode 0, base clock at "0", sampling on leading edge (rising) & set-up on trailling edge (falling). */ - SPI_MODE_1_gc = (0x01<<2), /* SPI Mode 1, base clock at "0", set-up on leading edge (rising) & sampling on trailling edge (falling). */ - SPI_MODE_2_gc = (0x02<<2), /* SPI Mode 2, base clock at "1", sampling on leading edge (falling) & set-up on trailling edge (rising). */ - SPI_MODE_3_gc = (0x03<<2), /* SPI Mode 3, base clock at "1", set-up on leading edge (falling) & sampling on trailling edge (rising). */ -} SPI_MODE_t; - -/* Prescaler setting */ -typedef enum SPI_PRESCALER_enum -{ - SPI_PRESCALER_DIV4_gc = (0x00<<0), /* If CLK2X=1 CLKper/2, else (CLK2X=0) CLKper/4. */ - SPI_PRESCALER_DIV16_gc = (0x01<<0), /* If CLK2X=1 CLKper/8, else (CLK2X=0) CLKper/16. */ - SPI_PRESCALER_DIV64_gc = (0x02<<0), /* If CLK2X=1 CLKper/32, else (CLK2X=0) CLKper/64. */ - SPI_PRESCALER_DIV128_gc = (0x03<<0), /* If CLK2X=1 CLKper/64, else (CLK2X=0) CLKper/128. */ -} SPI_PRESCALER_t; - -/* Interrupt level */ -typedef enum SPI_INTLVL_enum -{ - SPI_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - SPI_INTLVL_LO_gc = (0x01<<0), /* Low Level */ - SPI_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ - SPI_INTLVL_HI_gc = (0x03<<0), /* High Level */ -} SPI_INTLVL_t; - -/* Buffer Modes */ -typedef enum SPI_BUFMODE_enum -{ - SPI_BUFMODE_OFF_gc = (0x00<<6), /* SPI Unbuffered Mode */ - SPI_BUFMODE_BUFMODE1_gc = (0x02<<6), /* Buffer Mode 1 (with dummy byte) */ - SPI_BUFMODE_BUFMODE2_gc = (0x03<<6), /* Buffer Mode 2 (no dummy byte) */ -} SPI_BUFMODE_t; - - -/* --------------------------------------------------------------------------- -IRCOM - IR Communication Module --------------------------------------------------------------------------- -*/ - -/* IR Communication Module */ -typedef struct IRCOM_struct -{ - register8_t CTRL; /* Control Register */ - register8_t TXPLCTRL; /* IrDA Transmitter Pulse Length Control Register */ - register8_t RXPLCTRL; /* IrDA Receiver Pulse Length Control Register */ -} IRCOM_t; - -/* Event channel selection */ -typedef enum IRDA_EVSEL_enum -{ - IRDA_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ - IRDA_EVSEL_0_gc = (0x08<<0), /* Event Channel 0 */ - IRDA_EVSEL_1_gc = (0x09<<0), /* Event Channel 1 */ - IRDA_EVSEL_2_gc = (0x0A<<0), /* Event Channel 2 */ - IRDA_EVSEL_3_gc = (0x0B<<0), /* Event Channel 3 */ - IRDA_EVSEL_4_gc = (0x0C<<0), /* Event Channel 4 */ - IRDA_EVSEL_5_gc = (0x0D<<0), /* Event Channel 5 */ - IRDA_EVSEL_6_gc = (0x0E<<0), /* Event Channel 6 */ - IRDA_EVSEL_7_gc = (0x0F<<0), /* Event Channel 7 */ -} IRDA_EVSEL_t; - - -/* --------------------------------------------------------------------------- -FUSE - Fuses and Lockbits --------------------------------------------------------------------------- -*/ - -/* Lock Bits */ -typedef struct NVM_LOCKBITS_struct -{ - register8_t LOCK_BITS; /* Lock Bits (Changed from LOCKBITS to avoid avr-libc collision) */ -} NVM_LOCKBITS_t; - - -/* Fuses */ -typedef struct NVM_FUSES_struct -{ - register8_t reserved_0x00; - register8_t FUSEBYTE1; /* Watchdog Configuration */ - register8_t FUSEBYTE2; /* Reset Configuration */ - register8_t reserved_0x03; - register8_t FUSEBYTE4; /* Start-up Configuration */ - register8_t FUSEBYTE5; /* EESAVE and BOD Level */ - register8_t FUSEBYTE6; /* Fault State */ -} NVM_FUSES_t; - -/* Boot lock bits - boot setcion */ -typedef enum FUSE_BLBB_enum -{ - FUSE_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ - FUSE_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ - FUSE_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ - FUSE_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ -} FUSE_BLBB_t; - -/* Boot lock bits - application section */ -typedef enum FUSE_BLBA_enum -{ - FUSE_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ - FUSE_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ - FUSE_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ - FUSE_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ -} FUSE_BLBA_t; - -/* Boot lock bits - application table section */ -typedef enum FUSE_BLBAT_enum -{ - FUSE_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ - FUSE_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ - FUSE_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ - FUSE_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ -} FUSE_BLBAT_t; - -/* Lock bits */ -typedef enum FUSE_LB_enum -{ - FUSE_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ - FUSE_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ - FUSE_LB_NOLOCK_gc = (0x03<<0), /* No locks */ -} FUSE_LB_t; - -/* Boot Loader Section Reset Vector */ -typedef enum BOOTRST_enum -{ - BOOTRST_BOOTLDR_gc = (0x00<<6), /* Boot Loader Reset */ - BOOTRST_APPLICATION_gc = (0x01<<6), /* Application Reset */ -} BOOTRST_t; - -/* BOD operation */ -typedef enum BOD_enum -{ - BOD_SAMPLED_gc = (0x01<<4), /* BOD enabled in sampled mode */ - BOD_CONTINUOUS_gc = (0x02<<4), /* BOD enabled continuously */ - BOD_DISABLED_gc = (0x03<<4), /* BOD Disabled */ -} BOD_t; - -/* Watchdog (Window) Timeout Period */ -typedef enum WD_enum -{ - WD_8CLK_gc = (0x00<<4), /* 8 cycles (8ms @ 3.3V) */ - WD_16CLK_gc = (0x01<<4), /* 16 cycles (16ms @ 3.3V) */ - WD_32CLK_gc = (0x02<<4), /* 32 cycles (32ms @ 3.3V) */ - WD_64CLK_gc = (0x03<<4), /* 64 cycles (64ms @ 3.3V) */ - WD_128CLK_gc = (0x04<<4), /* 128 cycles (0.125s @ 3.3V) */ - WD_256CLK_gc = (0x05<<4), /* 256 cycles (0.25s @ 3.3V) */ - WD_512CLK_gc = (0x06<<4), /* 512 cycles (0.5s @ 3.3V) */ - WD_1KCLK_gc = (0x07<<4), /* 1K cycles (1s @ 3.3V) */ - WD_2KCLK_gc = (0x08<<4), /* 2K cycles (2s @ 3.3V) */ - WD_4KCLK_gc = (0x09<<4), /* 4K cycles (4s @ 3.3V) */ - WD_8KCLK_gc = (0x0A<<4), /* 8K cycles (8s @ 3.3V) */ -} WD_t; - -/* Start-up Time */ -typedef enum SUT_enum -{ - SUT_0MS_gc = (0x03<<2), /* 0 ms */ - SUT_4MS_gc = (0x01<<2), /* 4 ms */ - SUT_64MS_gc = (0x00<<2), /* 64 ms */ -} SUT_t; - -/* Brownout Detection Voltage Level */ -typedef enum BODLVL_enum -{ - BODLVL_1V6_gc = (0x07<<0), /* 1.6 V */ - BODLVL_1V8_gc = (0x06<<0), /* 1.8 V */ - BODLVL_2V0_gc = (0x05<<0), /* 2.0 V */ - BODLVL_2V2_gc = (0x04<<0), /* 2.2 V */ - BODLVL_2V4_gc = (0x03<<0), /* 2.4 V */ - BODLVL_2V6_gc = (0x02<<0), /* 2.6 V */ - BODLVL_2V8_gc = (0x01<<0), /* 2.8 V */ - BODLVL_3V0_gc = (0x00<<0), /* 3.0 V */ -} BODLVL_t; - - -/* --------------------------------------------------------------------------- -SIGROW - Signature Row --------------------------------------------------------------------------- -*/ - -/* Production Signatures */ -typedef struct NVM_PROD_SIGNATURES_struct -{ - register8_t RCOSC8M; /* RCOSC 8MHz Calibration Value */ - register8_t reserved_0x01; - register8_t RCOSC32K; /* RCOSC 32.768 kHz Calibration Value */ - register8_t RCOSC32M; /* RCOSC 32 MHz Calibration Value B */ - register8_t RCOSC32MA; /* RCOSC 32 MHz Calibration Value A */ - register8_t reserved_0x05; - register8_t reserved_0x06; - register8_t reserved_0x07; - register8_t LOTNUM0; /* Lot Number Byte 0, ASCII */ - register8_t LOTNUM1; /* Lot Number Byte 1, ASCII */ - register8_t LOTNUM2; /* Lot Number Byte 2, ASCII */ - register8_t LOTNUM3; /* Lot Number Byte 3, ASCII */ - register8_t LOTNUM4; /* Lot Number Byte 4, ASCII */ - register8_t LOTNUM5; /* Lot Number Byte 5, ASCII */ - register8_t reserved_0x0E; - register8_t reserved_0x0F; - register8_t WAFNUM; /* Wafer Number */ - register8_t reserved_0x11; - register8_t COORDX0; /* Wafer Coordinate X Byte 0 */ - register8_t COORDX1; /* Wafer Coordinate X Byte 1 */ - register8_t COORDY0; /* Wafer Coordinate Y Byte 0 */ - register8_t COORDY1; /* Wafer Coordinate Y Byte 1 */ - register8_t reserved_0x16; - register8_t reserved_0x17; - register8_t reserved_0x18; - register8_t reserved_0x19; - register8_t reserved_0x1A; - register8_t reserved_0x1B; - register8_t reserved_0x1C; - register8_t reserved_0x1D; - register8_t ROOMTEMP; /* Temperature corresponds to TEMPSENSE3/2 */ - register8_t HOTTEMP; /* Temperature corresponds to TEMPSENSE1/0 */ - register8_t ADCACAL0; /* ADCA Calibration Byte 0 */ - register8_t ADCACAL1; /* ADCA Calibration Byte 1 */ - register8_t reserved_0x22; - register8_t reserved_0x23; - register8_t reserved_0x24; - register8_t reserved_0x25; - register8_t reserved_0x26; - register8_t reserved_0x27; - register8_t ACACURRCAL; /* ACA Current Calibration Byte */ - register8_t reserved_0x29; - register8_t reserved_0x2A; - register8_t reserved_0x2B; - register8_t TEMPSENSE2; /* Temperature Sensor Calibration Byte 2 */ - register8_t TEMPSENSE3; /* Temperature Sensor Calibration Byte 3 */ - register8_t TEMPSENSE0; /* Temperature Sensor Calibration Byte 0 */ - register8_t TEMPSENSE1; /* Temperature Sensor Calibration Byte 1 */ - register8_t DACA0OFFCAL; /* DACA0 Calibration Byte 0 */ - register8_t DACA0GAINCAL; /* DACA0 Calibration Byte 1 */ - register8_t reserved_0x32; - register8_t reserved_0x33; - register8_t DACA1OFFCAL; /* DACA1 Calibration Byte 0 */ - register8_t DACA1GAINCAL; /* DACA1 Calibration Byte 1 */ - register8_t reserved_0x36; - register8_t reserved_0x37; - register8_t reserved_0x38; - register8_t reserved_0x39; - register8_t reserved_0x3A; - register8_t reserved_0x3B; - register8_t reserved_0x3C; - register8_t reserved_0x3D; - register8_t reserved_0x3E; - register8_t reserved_0x3F; -} NVM_PROD_SIGNATURES_t; - -/* -========================================================================== -IO Module Instances. Mapped to memory. -========================================================================== -*/ - -#define VPORT0 (*(VPORT_t *) 0x0010) /* Virtual Port */ -#define VPORT1 (*(VPORT_t *) 0x0014) /* Virtual Port */ -#define VPORT2 (*(VPORT_t *) 0x0018) /* Virtual Port */ -#define VPORT3 (*(VPORT_t *) 0x001C) /* Virtual Port */ -#define OCD (*(OCD_t *) 0x002E) /* On-Chip Debug System */ -#define CLK (*(CLK_t *) 0x0040) /* Clock System */ -#define SLEEP (*(SLEEP_t *) 0x0048) /* Sleep Controller */ -#define OSC (*(OSC_t *) 0x0050) /* Oscillator */ -#define DFLLRC32M (*(DFLL_t *) 0x0060) /* DFLL */ -#define PR (*(PR_t *) 0x0070) /* Power Reduction */ -#define RST (*(RST_t *) 0x0078) /* Reset */ -#define WDT (*(WDT_t *) 0x0080) /* Watch-Dog Timer */ -#define MCU (*(MCU_t *) 0x0090) /* MCU Control */ -#define PMIC (*(PMIC_t *) 0x00A0) /* Programmable Multi-level Interrupt Controller */ -#define PORTCFG (*(PORTCFG_t *) 0x00B0) /* I/O port Configuration */ -#define CRC (*(CRC_t *) 0x00D0) /* Cyclic Redundancy Checker */ -#define EDMA (*(EDMA_t *) 0x0100) /* Enhanced DMA Controller */ -#define EVSYS (*(EVSYS_t *) 0x0180) /* Event System */ -#define NVM (*(NVM_t *) 0x01C0) /* Non-volatile Memory Controller */ -#define ADCA (*(ADC_t *) 0x0200) /* Analog-to-Digital Converter */ -#define DACA (*(DAC_t *) 0x0300) /* Digital-to-Analog Converter */ -#define ACA (*(AC_t *) 0x0380) /* Analog Comparator */ -#define RTC (*(RTC_t *) 0x0400) /* Real-Time Counter */ -#define XCL (*(XCL_t *) 0x0460) /* XMEGA Custom Logic */ -#define TWIC (*(TWI_t *) 0x0480) /* Two-Wire Interface */ -#define PORTA (*(PORT_t *) 0x0600) /* I/O Ports */ -#define PORTC (*(PORT_t *) 0x0640) /* I/O Ports */ -#define PORTD (*(PORT_t *) 0x0660) /* I/O Ports */ -#define PORTR (*(PORT_t *) 0x07E0) /* I/O Ports */ -#define TCC4 (*(TC4_t *) 0x0800) /* 16-bit Timer/Counter 4 */ -#define TCC5 (*(TC5_t *) 0x0840) /* 16-bit Timer/Counter 5 */ -#define FAULTC4 (*(FAULT_t *) 0x0880) /* Fault Extension */ -#define FAULTC5 (*(FAULT_t *) 0x0890) /* Fault Extension */ -#define WEXC (*(WEX_t *) 0x08A0) /* Waveform Extension */ -#define HIRESC (*(HIRES_t *) 0x08B0) /* High-Resolution Extension */ -#define USARTC0 (*(USART_t *) 0x08C0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ -#define SPIC (*(SPI_t *) 0x08E0) /* Serial Peripheral Interface with Buffer Modes */ -#define IRCOM (*(IRCOM_t *) 0x08F8) /* IR Communication Module */ -#define TCD5 (*(TC5_t *) 0x0940) /* 16-bit Timer/Counter 5 */ -#define USARTD0 (*(USART_t *) 0x09C0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ - - -#endif /* !defined (__ASSEMBLER__) */ - - -/* ========== Flattened fully qualified IO register names ========== */ - -/* GPIO - General Purpose IO Registers */ -#define GPIO_GPIOR0 _SFR_MEM8(0x0000) -#define GPIO_GPIOR1 _SFR_MEM8(0x0001) -#define GPIO_GPIOR2 _SFR_MEM8(0x0002) -#define GPIO_GPIOR3 _SFR_MEM8(0x0003) - -/* Deprecated */ -#define GPIO_GPIO0 _SFR_MEM8(0x0000) -#define GPIO_GPIO1 _SFR_MEM8(0x0001) -#define GPIO_GPIO2 _SFR_MEM8(0x0002) -#define GPIO_GPIO3 _SFR_MEM8(0x0003) - -/* NVM_FUSES - Fuses */ -#define FUSE_FUSEBYTE1 _SFR_MEM8(0x0001) -#define FUSE_FUSEBYTE2 _SFR_MEM8(0x0002) -#define FUSE_FUSEBYTE4 _SFR_MEM8(0x0004) -#define FUSE_FUSEBYTE5 _SFR_MEM8(0x0005) -#define FUSE_FUSEBYTE6 _SFR_MEM8(0x0006) - -/* NVM_LOCKBITS - Lock Bits */ -#define LOCKBIT_LOCKBITS _SFR_MEM8(0x0000) - -/* NVM_PROD_SIGNATURES - Production Signatures */ -#define PRODSIGNATURES_RCOSC8M _SFR_MEM8(0x0000) -#define PRODSIGNATURES_RCOSC32K _SFR_MEM8(0x0002) -#define PRODSIGNATURES_RCOSC32M _SFR_MEM8(0x0003) -#define PRODSIGNATURES_RCOSC32MA _SFR_MEM8(0x0004) -#define PRODSIGNATURES_LOTNUM0 _SFR_MEM8(0x0008) -#define PRODSIGNATURES_LOTNUM1 _SFR_MEM8(0x0009) -#define PRODSIGNATURES_LOTNUM2 _SFR_MEM8(0x000A) -#define PRODSIGNATURES_LOTNUM3 _SFR_MEM8(0x000B) -#define PRODSIGNATURES_LOTNUM4 _SFR_MEM8(0x000C) -#define PRODSIGNATURES_LOTNUM5 _SFR_MEM8(0x000D) -#define PRODSIGNATURES_WAFNUM _SFR_MEM8(0x0010) -#define PRODSIGNATURES_COORDX0 _SFR_MEM8(0x0012) -#define PRODSIGNATURES_COORDX1 _SFR_MEM8(0x0013) -#define PRODSIGNATURES_COORDY0 _SFR_MEM8(0x0014) -#define PRODSIGNATURES_COORDY1 _SFR_MEM8(0x0015) -#define PRODSIGNATURES_ROOMTEMP _SFR_MEM8(0x001E) -#define PRODSIGNATURES_HOTTEMP _SFR_MEM8(0x001F) -#define PRODSIGNATURES_ADCACAL0 _SFR_MEM8(0x0020) -#define PRODSIGNATURES_ADCACAL1 _SFR_MEM8(0x0021) -#define PRODSIGNATURES_ACACURRCAL _SFR_MEM8(0x0028) -#define PRODSIGNATURES_TEMPSENSE2 _SFR_MEM8(0x002C) -#define PRODSIGNATURES_TEMPSENSE3 _SFR_MEM8(0x002D) -#define PRODSIGNATURES_TEMPSENSE0 _SFR_MEM8(0x002E) -#define PRODSIGNATURES_TEMPSENSE1 _SFR_MEM8(0x002F) -#define PRODSIGNATURES_DACA0OFFCAL _SFR_MEM8(0x0030) -#define PRODSIGNATURES_DACA0GAINCAL _SFR_MEM8(0x0031) -#define PRODSIGNATURES_DACA1OFFCAL _SFR_MEM8(0x0034) -#define PRODSIGNATURES_DACA1GAINCAL _SFR_MEM8(0x0035) - -/* VPORT - Virtual Port */ -#define VPORT0_DIR _SFR_MEM8(0x0010) -#define VPORT0_OUT _SFR_MEM8(0x0011) -#define VPORT0_IN _SFR_MEM8(0x0012) -#define VPORT0_INTFLAGS _SFR_MEM8(0x0013) - -/* VPORT - Virtual Port */ -#define VPORT1_DIR _SFR_MEM8(0x0014) -#define VPORT1_OUT _SFR_MEM8(0x0015) -#define VPORT1_IN _SFR_MEM8(0x0016) -#define VPORT1_INTFLAGS _SFR_MEM8(0x0017) - -/* VPORT - Virtual Port */ -#define VPORT2_DIR _SFR_MEM8(0x0018) -#define VPORT2_OUT _SFR_MEM8(0x0019) -#define VPORT2_IN _SFR_MEM8(0x001A) -#define VPORT2_INTFLAGS _SFR_MEM8(0x001B) - -/* VPORT - Virtual Port */ -#define VPORT3_DIR _SFR_MEM8(0x001C) -#define VPORT3_OUT _SFR_MEM8(0x001D) -#define VPORT3_IN _SFR_MEM8(0x001E) -#define VPORT3_INTFLAGS _SFR_MEM8(0x001F) - -/* OCD - On-Chip Debug System */ -#define OCD_OCDR0 _SFR_MEM8(0x002E) -#define OCD_OCDR1 _SFR_MEM8(0x002F) - -/* CPU - CPU registers */ -#define CPU_CCP _SFR_MEM8(0x0034) -#define CPU_RAMPD _SFR_MEM8(0x0038) -#define CPU_RAMPX _SFR_MEM8(0x0039) -#define CPU_RAMPY _SFR_MEM8(0x003A) -#define CPU_RAMPZ _SFR_MEM8(0x003B) -#define CPU_EIND _SFR_MEM8(0x003C) -#define CPU_SPL _SFR_MEM8(0x003D) -#define CPU_SPH _SFR_MEM8(0x003E) -#define CPU_SREG _SFR_MEM8(0x003F) - -/* CLK - Clock System */ -#define CLK_CTRL _SFR_MEM8(0x0040) -#define CLK_PSCTRL _SFR_MEM8(0x0041) -#define CLK_LOCK _SFR_MEM8(0x0042) -#define CLK_RTCCTRL _SFR_MEM8(0x0043) - -/* SLEEP - Sleep Controller */ -#define SLEEP_CTRL _SFR_MEM8(0x0048) - -/* OSC - Oscillator */ -#define OSC_CTRL _SFR_MEM8(0x0050) -#define OSC_STATUS _SFR_MEM8(0x0051) -#define OSC_XOSCCTRL _SFR_MEM8(0x0052) -#define OSC_XOSCFAIL _SFR_MEM8(0x0053) -#define OSC_RC32KCAL _SFR_MEM8(0x0054) -#define OSC_PLLCTRL _SFR_MEM8(0x0055) -#define OSC_DFLLCTRL _SFR_MEM8(0x0056) -#define OSC_RC8MCAL _SFR_MEM8(0x0057) - -/* DFLL - DFLL */ -#define DFLLRC32M_CTRL _SFR_MEM8(0x0060) -#define DFLLRC32M_CALA _SFR_MEM8(0x0062) -#define DFLLRC32M_CALB _SFR_MEM8(0x0063) -#define DFLLRC32M_COMP0 _SFR_MEM8(0x0064) -#define DFLLRC32M_COMP1 _SFR_MEM8(0x0065) -#define DFLLRC32M_COMP2 _SFR_MEM8(0x0066) - -/* PR - Power Reduction */ -#define PR_PRGEN _SFR_MEM8(0x0070) -#define PR_PRPA _SFR_MEM8(0x0071) -#define PR_PRPC _SFR_MEM8(0x0073) -#define PR_PRPD _SFR_MEM8(0x0074) - -/* RST - Reset */ -#define RST_STATUS _SFR_MEM8(0x0078) -#define RST_CTRL _SFR_MEM8(0x0079) - -/* WDT - Watch-Dog Timer */ -#define WDT_CTRL _SFR_MEM8(0x0080) -#define WDT_WINCTRL _SFR_MEM8(0x0081) -#define WDT_STATUS _SFR_MEM8(0x0082) - -/* MCU - MCU Control */ -#define MCU_DEVID0 _SFR_MEM8(0x0090) -#define MCU_DEVID1 _SFR_MEM8(0x0091) -#define MCU_DEVID2 _SFR_MEM8(0x0092) -#define MCU_REVID _SFR_MEM8(0x0093) -#define MCU_ANAINIT _SFR_MEM8(0x0097) -#define MCU_EVSYSLOCK _SFR_MEM8(0x0098) -#define MCU_WEXLOCK _SFR_MEM8(0x0099) -#define MCU_FAULTLOCK _SFR_MEM8(0x009A) - -/* PMIC - Programmable Multi-level Interrupt Controller */ -#define PMIC_STATUS _SFR_MEM8(0x00A0) -#define PMIC_INTPRI _SFR_MEM8(0x00A1) -#define PMIC_CTRL _SFR_MEM8(0x00A2) - -/* PORTCFG - I/O port Configuration */ -#define PORTCFG_MPCMASK _SFR_MEM8(0x00B0) -#define PORTCFG_CLKOUT _SFR_MEM8(0x00B4) -#define PORTCFG_ACEVOUT _SFR_MEM8(0x00B6) -#define PORTCFG_SRLCTRL _SFR_MEM8(0x00B7) - -/* CRC - Cyclic Redundancy Checker */ -#define CRC_CTRL _SFR_MEM8(0x00D0) -#define CRC_STATUS _SFR_MEM8(0x00D1) -#define CRC_DATAIN _SFR_MEM8(0x00D3) -#define CRC_CHECKSUM0 _SFR_MEM8(0x00D4) -#define CRC_CHECKSUM1 _SFR_MEM8(0x00D5) -#define CRC_CHECKSUM2 _SFR_MEM8(0x00D6) -#define CRC_CHECKSUM3 _SFR_MEM8(0x00D7) - -/* EDMA - Enhanced DMA Controller */ -#define EDMA_CTRL _SFR_MEM8(0x0100) -#define EDMA_INTFLAGS _SFR_MEM8(0x0103) -#define EDMA_STATUS _SFR_MEM8(0x0104) -#define EDMA_TEMP _SFR_MEM8(0x0106) -#define EDMA_CH0_CTRLA _SFR_MEM8(0x0110) -#define EDMA_CH0_CTRLB _SFR_MEM8(0x0111) -#define EDMA_CH0_ADDRCTRL _SFR_MEM8(0x0112) -#define EDMA_CH0_DESTADDRCTRL _SFR_MEM8(0x0113) -#define EDMA_CH0_TRIGSRC _SFR_MEM8(0x0114) -#define EDMA_CH0_TRFCNT _SFR_MEM16(0x0116) -#define EDMA_CH0_ADDR _SFR_MEM16(0x0118) -#define EDMA_CH0_DESTADDR _SFR_MEM16(0x011C) -#define EDMA_CH1_CTRLA _SFR_MEM8(0x0120) -#define EDMA_CH1_CTRLB _SFR_MEM8(0x0121) -#define EDMA_CH1_ADDRCTRL _SFR_MEM8(0x0122) -#define EDMA_CH1_DESTADDRCTRL _SFR_MEM8(0x0123) -#define EDMA_CH1_TRIGSRC _SFR_MEM8(0x0124) -#define EDMA_CH1_TRFCNT _SFR_MEM16(0x0126) -#define EDMA_CH1_ADDR _SFR_MEM16(0x0128) -#define EDMA_CH1_DESTADDR _SFR_MEM16(0x012C) -#define EDMA_CH2_CTRLA _SFR_MEM8(0x0130) -#define EDMA_CH2_CTRLB _SFR_MEM8(0x0131) -#define EDMA_CH2_ADDRCTRL _SFR_MEM8(0x0132) -#define EDMA_CH2_DESTADDRCTRL _SFR_MEM8(0x0133) -#define EDMA_CH2_TRIGSRC _SFR_MEM8(0x0134) -#define EDMA_CH2_TRFCNT _SFR_MEM16(0x0136) -#define EDMA_CH2_ADDR _SFR_MEM16(0x0138) -#define EDMA_CH2_DESTADDR _SFR_MEM16(0x013C) -#define EDMA_CH3_CTRLA _SFR_MEM8(0x0140) -#define EDMA_CH3_CTRLB _SFR_MEM8(0x0141) -#define EDMA_CH3_ADDRCTRL _SFR_MEM8(0x0142) -#define EDMA_CH3_DESTADDRCTRL _SFR_MEM8(0x0143) -#define EDMA_CH3_TRIGSRC _SFR_MEM8(0x0144) -#define EDMA_CH3_TRFCNT _SFR_MEM16(0x0146) -#define EDMA_CH3_ADDR _SFR_MEM16(0x0148) -#define EDMA_CH3_DESTADDR _SFR_MEM16(0x014C) - -/* EVSYS - Event System */ -#define EVSYS_CH0MUX _SFR_MEM8(0x0180) -#define EVSYS_CH1MUX _SFR_MEM8(0x0181) -#define EVSYS_CH2MUX _SFR_MEM8(0x0182) -#define EVSYS_CH3MUX _SFR_MEM8(0x0183) -#define EVSYS_CH4MUX _SFR_MEM8(0x0184) -#define EVSYS_CH5MUX _SFR_MEM8(0x0185) -#define EVSYS_CH6MUX _SFR_MEM8(0x0186) -#define EVSYS_CH7MUX _SFR_MEM8(0x0187) -#define EVSYS_CH0CTRL _SFR_MEM8(0x0188) -#define EVSYS_CH1CTRL _SFR_MEM8(0x0189) -#define EVSYS_CH2CTRL _SFR_MEM8(0x018A) -#define EVSYS_CH3CTRL _SFR_MEM8(0x018B) -#define EVSYS_CH4CTRL _SFR_MEM8(0x018C) -#define EVSYS_CH5CTRL _SFR_MEM8(0x018D) -#define EVSYS_CH6CTRL _SFR_MEM8(0x018E) -#define EVSYS_CH7CTRL _SFR_MEM8(0x018F) -#define EVSYS_STROBE _SFR_MEM8(0x0190) -#define EVSYS_DATA _SFR_MEM8(0x0191) -#define EVSYS_DFCTRL _SFR_MEM8(0x0192) - -/* NVM - Non-volatile Memory Controller */ -#define NVM_ADDR0 _SFR_MEM8(0x01C0) -#define NVM_ADDR1 _SFR_MEM8(0x01C1) -#define NVM_ADDR2 _SFR_MEM8(0x01C2) -#define NVM_DATA0 _SFR_MEM8(0x01C4) -#define NVM_DATA1 _SFR_MEM8(0x01C5) -#define NVM_DATA2 _SFR_MEM8(0x01C6) -#define NVM_CMD _SFR_MEM8(0x01CA) -#define NVM_CTRLA _SFR_MEM8(0x01CB) -#define NVM_CTRLB _SFR_MEM8(0x01CC) -#define NVM_INTCTRL _SFR_MEM8(0x01CD) -#define NVM_STATUS _SFR_MEM8(0x01CF) -#define NVM_LOCKBITS _SFR_MEM8(0x01D0) - -/* ADC - Analog-to-Digital Converter */ -#define ADCA_CTRLA _SFR_MEM8(0x0200) -#define ADCA_CTRLB _SFR_MEM8(0x0201) -#define ADCA_REFCTRL _SFR_MEM8(0x0202) -#define ADCA_EVCTRL _SFR_MEM8(0x0203) -#define ADCA_PRESCALER _SFR_MEM8(0x0204) -#define ADCA_INTFLAGS _SFR_MEM8(0x0206) -#define ADCA_TEMP _SFR_MEM8(0x0207) -#define ADCA_SAMPCTRL _SFR_MEM8(0x0208) -#define ADCA_CAL _SFR_MEM16(0x020C) -#define ADCA_CH0RES _SFR_MEM16(0x0210) -#define ADCA_CMP _SFR_MEM16(0x0218) -#define ADCA_CH0_CTRL _SFR_MEM8(0x0220) -#define ADCA_CH0_MUXCTRL _SFR_MEM8(0x0221) -#define ADCA_CH0_INTCTRL _SFR_MEM8(0x0222) -#define ADCA_CH0_INTFLAGS _SFR_MEM8(0x0223) -#define ADCA_CH0_RES _SFR_MEM16(0x0224) -#define ADCA_CH0_SCAN _SFR_MEM8(0x0226) -#define ADCA_CH0_CORRCTRL _SFR_MEM8(0x0227) -#define ADCA_CH0_OFFSETCORR0 _SFR_MEM8(0x0228) -#define ADCA_CH0_OFFSETCORR1 _SFR_MEM8(0x0229) -#define ADCA_CH0_GAINCORR0 _SFR_MEM8(0x022A) -#define ADCA_CH0_GAINCORR1 _SFR_MEM8(0x022B) -#define ADCA_CH0_AVGCTRL _SFR_MEM8(0x022C) - -/* DAC - Digital-to-Analog Converter */ -#define DACA_CTRLA _SFR_MEM8(0x0300) -#define DACA_CTRLB _SFR_MEM8(0x0301) -#define DACA_CTRLC _SFR_MEM8(0x0302) -#define DACA_EVCTRL _SFR_MEM8(0x0303) -#define DACA_STATUS _SFR_MEM8(0x0305) -#define DACA_CH0GAINCAL _SFR_MEM8(0x0308) -#define DACA_CH0OFFSETCAL _SFR_MEM8(0x0309) -#define DACA_CH1GAINCAL _SFR_MEM8(0x030A) -#define DACA_CH1OFFSETCAL _SFR_MEM8(0x030B) -#define DACA_CH0DATA _SFR_MEM16(0x0318) -#define DACA_CH1DATA _SFR_MEM16(0x031A) - -/* AC - Analog Comparator */ -#define ACA_AC0CTRL _SFR_MEM8(0x0380) -#define ACA_AC1CTRL _SFR_MEM8(0x0381) -#define ACA_AC0MUXCTRL _SFR_MEM8(0x0382) -#define ACA_AC1MUXCTRL _SFR_MEM8(0x0383) -#define ACA_CTRLA _SFR_MEM8(0x0384) -#define ACA_CTRLB _SFR_MEM8(0x0385) -#define ACA_WINCTRL _SFR_MEM8(0x0386) -#define ACA_STATUS _SFR_MEM8(0x0387) -#define ACA_CURRCTRL _SFR_MEM8(0x0388) -#define ACA_CURRCALIB _SFR_MEM8(0x0389) - -/* RTC - Real-Time Counter */ -#define RTC_CTRL _SFR_MEM8(0x0400) -#define RTC_STATUS _SFR_MEM8(0x0401) -#define RTC_INTCTRL _SFR_MEM8(0x0402) -#define RTC_INTFLAGS _SFR_MEM8(0x0403) -#define RTC_TEMP _SFR_MEM8(0x0404) -#define RTC_CALIB _SFR_MEM8(0x0406) -#define RTC_CNT _SFR_MEM16(0x0408) -#define RTC_PER _SFR_MEM16(0x040A) -#define RTC_COMP _SFR_MEM16(0x040C) - -/* XCL - XMEGA Custom Logic */ -#define XCL_CTRLA _SFR_MEM8(0x0460) -#define XCL_CTRLB _SFR_MEM8(0x0461) -#define XCL_CTRLC _SFR_MEM8(0x0462) -#define XCL_CTRLD _SFR_MEM8(0x0463) -#define XCL_CTRLE _SFR_MEM8(0x0464) -#define XCL_CTRLF _SFR_MEM8(0x0465) -#define XCL_CTRLG _SFR_MEM8(0x0466) -#define XCL_INTCTRL _SFR_MEM8(0x0467) -#define XCL_INTFLAGS _SFR_MEM8(0x0468) -#define XCL_PLC _SFR_MEM8(0x0469) -#define XCL_CNTL _SFR_MEM8(0x046A) -#define XCL_CNTH _SFR_MEM8(0x046B) -#define XCL_CMPL _SFR_MEM8(0x046C) -#define XCL_CMPH _SFR_MEM8(0x046D) -#define XCL_PERCAPTL _SFR_MEM8(0x046E) -#define XCL_PERCAPTH _SFR_MEM8(0x046F) - -/* TWI - Two-Wire Interface */ -#define TWIC_CTRL _SFR_MEM8(0x0480) -#define TWIC_MASTER_CTRLA _SFR_MEM8(0x0481) -#define TWIC_MASTER_CTRLB _SFR_MEM8(0x0482) -#define TWIC_MASTER_CTRLC _SFR_MEM8(0x0483) -#define TWIC_MASTER_STATUS _SFR_MEM8(0x0484) -#define TWIC_MASTER_BAUD _SFR_MEM8(0x0485) -#define TWIC_MASTER_ADDR _SFR_MEM8(0x0486) -#define TWIC_MASTER_DATA _SFR_MEM8(0x0487) -#define TWIC_SLAVE_CTRLA _SFR_MEM8(0x0488) -#define TWIC_SLAVE_CTRLB _SFR_MEM8(0x0489) -#define TWIC_SLAVE_STATUS _SFR_MEM8(0x048A) -#define TWIC_SLAVE_ADDR _SFR_MEM8(0x048B) -#define TWIC_SLAVE_DATA _SFR_MEM8(0x048C) -#define TWIC_SLAVE_ADDRMASK _SFR_MEM8(0x048D) -#define TWIC_TIMEOUT_TOS _SFR_MEM8(0x048E) -#define TWIC_TIMEOUT_TOCONF _SFR_MEM8(0x048F) - -/* PORT - I/O Ports */ -#define PORTA_DIR _SFR_MEM8(0x0600) -#define PORTA_DIRSET _SFR_MEM8(0x0601) -#define PORTA_DIRCLR _SFR_MEM8(0x0602) -#define PORTA_DIRTGL _SFR_MEM8(0x0603) -#define PORTA_OUT _SFR_MEM8(0x0604) -#define PORTA_OUTSET _SFR_MEM8(0x0605) -#define PORTA_OUTCLR _SFR_MEM8(0x0606) -#define PORTA_OUTTGL _SFR_MEM8(0x0607) -#define PORTA_IN _SFR_MEM8(0x0608) -#define PORTA_INTCTRL _SFR_MEM8(0x0609) -#define PORTA_INTMASK _SFR_MEM8(0x060A) -#define PORTA_INTFLAGS _SFR_MEM8(0x060C) -#define PORTA_REMAP _SFR_MEM8(0x060E) -#define PORTA_PIN0CTRL _SFR_MEM8(0x0610) -#define PORTA_PIN1CTRL _SFR_MEM8(0x0611) -#define PORTA_PIN2CTRL _SFR_MEM8(0x0612) -#define PORTA_PIN3CTRL _SFR_MEM8(0x0613) -#define PORTA_PIN4CTRL _SFR_MEM8(0x0614) -#define PORTA_PIN5CTRL _SFR_MEM8(0x0615) -#define PORTA_PIN6CTRL _SFR_MEM8(0x0616) -#define PORTA_PIN7CTRL _SFR_MEM8(0x0617) - -/* PORT - I/O Ports */ -#define PORTC_DIR _SFR_MEM8(0x0640) -#define PORTC_DIRSET _SFR_MEM8(0x0641) -#define PORTC_DIRCLR _SFR_MEM8(0x0642) -#define PORTC_DIRTGL _SFR_MEM8(0x0643) -#define PORTC_OUT _SFR_MEM8(0x0644) -#define PORTC_OUTSET _SFR_MEM8(0x0645) -#define PORTC_OUTCLR _SFR_MEM8(0x0646) -#define PORTC_OUTTGL _SFR_MEM8(0x0647) -#define PORTC_IN _SFR_MEM8(0x0648) -#define PORTC_INTCTRL _SFR_MEM8(0x0649) -#define PORTC_INTMASK _SFR_MEM8(0x064A) -#define PORTC_INTFLAGS _SFR_MEM8(0x064C) -#define PORTC_REMAP _SFR_MEM8(0x064E) -#define PORTC_PIN0CTRL _SFR_MEM8(0x0650) -#define PORTC_PIN1CTRL _SFR_MEM8(0x0651) -#define PORTC_PIN2CTRL _SFR_MEM8(0x0652) -#define PORTC_PIN3CTRL _SFR_MEM8(0x0653) -#define PORTC_PIN4CTRL _SFR_MEM8(0x0654) -#define PORTC_PIN5CTRL _SFR_MEM8(0x0655) -#define PORTC_PIN6CTRL _SFR_MEM8(0x0656) -#define PORTC_PIN7CTRL _SFR_MEM8(0x0657) - -/* PORT - I/O Ports */ -#define PORTD_DIR _SFR_MEM8(0x0660) -#define PORTD_DIRSET _SFR_MEM8(0x0661) -#define PORTD_DIRCLR _SFR_MEM8(0x0662) -#define PORTD_DIRTGL _SFR_MEM8(0x0663) -#define PORTD_OUT _SFR_MEM8(0x0664) -#define PORTD_OUTSET _SFR_MEM8(0x0665) -#define PORTD_OUTCLR _SFR_MEM8(0x0666) -#define PORTD_OUTTGL _SFR_MEM8(0x0667) -#define PORTD_IN _SFR_MEM8(0x0668) -#define PORTD_INTCTRL _SFR_MEM8(0x0669) -#define PORTD_INTMASK _SFR_MEM8(0x066A) -#define PORTD_INTFLAGS _SFR_MEM8(0x066C) -#define PORTD_REMAP _SFR_MEM8(0x066E) -#define PORTD_PIN0CTRL _SFR_MEM8(0x0670) -#define PORTD_PIN1CTRL _SFR_MEM8(0x0671) -#define PORTD_PIN2CTRL _SFR_MEM8(0x0672) -#define PORTD_PIN3CTRL _SFR_MEM8(0x0673) -#define PORTD_PIN4CTRL _SFR_MEM8(0x0674) -#define PORTD_PIN5CTRL _SFR_MEM8(0x0675) -#define PORTD_PIN6CTRL _SFR_MEM8(0x0676) -#define PORTD_PIN7CTRL _SFR_MEM8(0x0677) - -/* PORT - I/O Ports */ -#define PORTR_DIR _SFR_MEM8(0x07E0) -#define PORTR_DIRSET _SFR_MEM8(0x07E1) -#define PORTR_DIRCLR _SFR_MEM8(0x07E2) -#define PORTR_DIRTGL _SFR_MEM8(0x07E3) -#define PORTR_OUT _SFR_MEM8(0x07E4) -#define PORTR_OUTSET _SFR_MEM8(0x07E5) -#define PORTR_OUTCLR _SFR_MEM8(0x07E6) -#define PORTR_OUTTGL _SFR_MEM8(0x07E7) -#define PORTR_IN _SFR_MEM8(0x07E8) -#define PORTR_INTCTRL _SFR_MEM8(0x07E9) -#define PORTR_INTMASK _SFR_MEM8(0x07EA) -#define PORTR_INTFLAGS _SFR_MEM8(0x07EC) -#define PORTR_REMAP _SFR_MEM8(0x07EE) -#define PORTR_PIN0CTRL _SFR_MEM8(0x07F0) -#define PORTR_PIN1CTRL _SFR_MEM8(0x07F1) -#define PORTR_PIN2CTRL _SFR_MEM8(0x07F2) -#define PORTR_PIN3CTRL _SFR_MEM8(0x07F3) -#define PORTR_PIN4CTRL _SFR_MEM8(0x07F4) -#define PORTR_PIN5CTRL _SFR_MEM8(0x07F5) -#define PORTR_PIN6CTRL _SFR_MEM8(0x07F6) -#define PORTR_PIN7CTRL _SFR_MEM8(0x07F7) - -/* TC4 - 16-bit Timer/Counter 4 */ -#define TCC4_CTRLA _SFR_MEM8(0x0800) -#define TCC4_CTRLB _SFR_MEM8(0x0801) -#define TCC4_CTRLC _SFR_MEM8(0x0802) -#define TCC4_CTRLD _SFR_MEM8(0x0803) -#define TCC4_CTRLE _SFR_MEM8(0x0804) -#define TCC4_CTRLF _SFR_MEM8(0x0805) -#define TCC4_INTCTRLA _SFR_MEM8(0x0806) -#define TCC4_INTCTRLB _SFR_MEM8(0x0807) -#define TCC4_CTRLGCLR _SFR_MEM8(0x0808) -#define TCC4_CTRLGSET _SFR_MEM8(0x0809) -#define TCC4_CTRLHCLR _SFR_MEM8(0x080A) -#define TCC4_CTRLHSET _SFR_MEM8(0x080B) -#define TCC4_INTFLAGS _SFR_MEM8(0x080C) -#define TCC4_TEMP _SFR_MEM8(0x080F) -#define TCC4_CNT _SFR_MEM16(0x0820) -#define TCC4_PER _SFR_MEM16(0x0826) -#define TCC4_CCA _SFR_MEM16(0x0828) -#define TCC4_CCB _SFR_MEM16(0x082A) -#define TCC4_CCC _SFR_MEM16(0x082C) -#define TCC4_CCD _SFR_MEM16(0x082E) -#define TCC4_PERBUF _SFR_MEM16(0x0836) -#define TCC4_CCABUF _SFR_MEM16(0x0838) -#define TCC4_CCBBUF _SFR_MEM16(0x083A) -#define TCC4_CCCBUF _SFR_MEM16(0x083C) -#define TCC4_CCDBUF _SFR_MEM16(0x083E) - -/* TC5 - 16-bit Timer/Counter 5 */ -#define TCC5_CTRLA _SFR_MEM8(0x0840) -#define TCC5_CTRLB _SFR_MEM8(0x0841) -#define TCC5_CTRLC _SFR_MEM8(0x0842) -#define TCC5_CTRLD _SFR_MEM8(0x0843) -#define TCC5_CTRLE _SFR_MEM8(0x0844) -#define TCC5_CTRLF _SFR_MEM8(0x0845) -#define TCC5_INTCTRLA _SFR_MEM8(0x0846) -#define TCC5_INTCTRLB _SFR_MEM8(0x0847) -#define TCC5_CTRLGCLR _SFR_MEM8(0x0848) -#define TCC5_CTRLGSET _SFR_MEM8(0x0849) -#define TCC5_CTRLHCLR _SFR_MEM8(0x084A) -#define TCC5_CTRLHSET _SFR_MEM8(0x084B) -#define TCC5_INTFLAGS _SFR_MEM8(0x084C) -#define TCC5_TEMP _SFR_MEM8(0x084F) -#define TCC5_CNT _SFR_MEM16(0x0860) -#define TCC5_PER _SFR_MEM16(0x0866) -#define TCC5_CCA _SFR_MEM16(0x0868) -#define TCC5_CCB _SFR_MEM16(0x086A) -#define TCC5_PERBUF _SFR_MEM16(0x0876) -#define TCC5_CCABUF _SFR_MEM16(0x0878) -#define TCC5_CCBBUF _SFR_MEM16(0x087A) - -/* FAULT - Fault Extension */ -#define FAULTC4_CTRLA _SFR_MEM8(0x0880) -#define FAULTC4_CTRLB _SFR_MEM8(0x0881) -#define FAULTC4_CTRLC _SFR_MEM8(0x0882) -#define FAULTC4_CTRLD _SFR_MEM8(0x0883) -#define FAULTC4_CTRLE _SFR_MEM8(0x0884) -#define FAULTC4_STATUS _SFR_MEM8(0x0885) -#define FAULTC4_CTRLGCLR _SFR_MEM8(0x0886) -#define FAULTC4_CTRLGSET _SFR_MEM8(0x0887) - -/* FAULT - Fault Extension */ -#define FAULTC5_CTRLA _SFR_MEM8(0x0890) -#define FAULTC5_CTRLB _SFR_MEM8(0x0891) -#define FAULTC5_CTRLC _SFR_MEM8(0x0892) -#define FAULTC5_CTRLD _SFR_MEM8(0x0893) -#define FAULTC5_CTRLE _SFR_MEM8(0x0894) -#define FAULTC5_STATUS _SFR_MEM8(0x0895) -#define FAULTC5_CTRLGCLR _SFR_MEM8(0x0896) -#define FAULTC5_CTRLGSET _SFR_MEM8(0x0897) - -/* WEX - Waveform Extension */ -#define WEXC_CTRL _SFR_MEM8(0x08A0) -#define WEXC_DTBOTH _SFR_MEM8(0x08A1) -#define WEXC_DTLS _SFR_MEM8(0x08A2) -#define WEXC_DTHS _SFR_MEM8(0x08A3) -#define WEXC_STATUSCLR _SFR_MEM8(0x08A4) -#define WEXC_STATUSSET _SFR_MEM8(0x08A5) -#define WEXC_SWAP _SFR_MEM8(0x08A6) -#define WEXC_PGO _SFR_MEM8(0x08A7) -#define WEXC_PGV _SFR_MEM8(0x08A8) -#define WEXC_SWAPBUF _SFR_MEM8(0x08AA) -#define WEXC_PGOBUF _SFR_MEM8(0x08AB) -#define WEXC_PGVBUF _SFR_MEM8(0x08AC) -#define WEXC_OUTOVDIS _SFR_MEM8(0x08AF) - -/* HIRES - High-Resolution Extension */ -#define HIRESC_CTRLA _SFR_MEM8(0x08B0) - -/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ -#define USARTC0_DATA _SFR_MEM8(0x08C0) -#define USARTC0_STATUS _SFR_MEM8(0x08C1) -#define USARTC0_CTRLA _SFR_MEM8(0x08C2) -#define USARTC0_CTRLB _SFR_MEM8(0x08C3) -#define USARTC0_CTRLC _SFR_MEM8(0x08C4) -#define USARTC0_CTRLD _SFR_MEM8(0x08C5) -#define USARTC0_BAUDCTRLA _SFR_MEM8(0x08C6) -#define USARTC0_BAUDCTRLB _SFR_MEM8(0x08C7) - -/* SPI - Serial Peripheral Interface with Buffer Modes */ -#define SPIC_CTRL _SFR_MEM8(0x08E0) -#define SPIC_INTCTRL _SFR_MEM8(0x08E1) -#define SPIC_STATUS _SFR_MEM8(0x08E2) -#define SPIC_DATA _SFR_MEM8(0x08E3) -#define SPIC_CTRLB _SFR_MEM8(0x08E4) - -/* IRCOM - IR Communication Module */ -#define IRCOM_CTRL _SFR_MEM8(0x08F8) -#define IRCOM_TXPLCTRL _SFR_MEM8(0x08F9) -#define IRCOM_RXPLCTRL _SFR_MEM8(0x08FA) - -/* TC5 - 16-bit Timer/Counter 5 */ -#define TCD5_CTRLA _SFR_MEM8(0x0940) -#define TCD5_CTRLB _SFR_MEM8(0x0941) -#define TCD5_CTRLC _SFR_MEM8(0x0942) -#define TCD5_CTRLD _SFR_MEM8(0x0943) -#define TCD5_CTRLE _SFR_MEM8(0x0944) -#define TCD5_CTRLF _SFR_MEM8(0x0945) -#define TCD5_INTCTRLA _SFR_MEM8(0x0946) -#define TCD5_INTCTRLB _SFR_MEM8(0x0947) -#define TCD5_CTRLGCLR _SFR_MEM8(0x0948) -#define TCD5_CTRLGSET _SFR_MEM8(0x0949) -#define TCD5_CTRLHCLR _SFR_MEM8(0x094A) -#define TCD5_CTRLHSET _SFR_MEM8(0x094B) -#define TCD5_INTFLAGS _SFR_MEM8(0x094C) -#define TCD5_TEMP _SFR_MEM8(0x094F) -#define TCD5_CNT _SFR_MEM16(0x0960) -#define TCD5_PER _SFR_MEM16(0x0966) -#define TCD5_CCA _SFR_MEM16(0x0968) -#define TCD5_CCB _SFR_MEM16(0x096A) -#define TCD5_PERBUF _SFR_MEM16(0x0976) -#define TCD5_CCABUF _SFR_MEM16(0x0978) -#define TCD5_CCBBUF _SFR_MEM16(0x097A) - -/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ -#define USARTD0_DATA _SFR_MEM8(0x09C0) -#define USARTD0_STATUS _SFR_MEM8(0x09C1) -#define USARTD0_CTRLA _SFR_MEM8(0x09C2) -#define USARTD0_CTRLB _SFR_MEM8(0x09C3) -#define USARTD0_CTRLC _SFR_MEM8(0x09C4) -#define USARTD0_CTRLD _SFR_MEM8(0x09C5) -#define USARTD0_BAUDCTRLA _SFR_MEM8(0x09C6) -#define USARTD0_BAUDCTRLB _SFR_MEM8(0x09C7) - - - -/*================== Bitfield Definitions ================== */ - -/* VPORT - Virtual Ports */ -/* VPORT.INTFLAGS bit masks and bit positions */ -#define VPORT_INT7IF_bm 0x80 /* Interrupt Pin 7 Flag bit mask. */ -#define VPORT_INT7IF_bp 7 /* Interrupt Pin 7 Flag bit position. */ - -#define VPORT_INT6IF_bm 0x40 /* Interrupt Pin 6 Flag bit mask. */ -#define VPORT_INT6IF_bp 6 /* Interrupt Pin 6 Flag bit position. */ - -#define VPORT_INT5IF_bm 0x20 /* Interrupt Pin 5 Flag bit mask. */ -#define VPORT_INT5IF_bp 5 /* Interrupt Pin 5 Flag bit position. */ - -#define VPORT_INT4IF_bm 0x10 /* Interrupt Pin 4 Flag bit mask. */ -#define VPORT_INT4IF_bp 4 /* Interrupt Pin 4 Flag bit position. */ - -#define VPORT_INT3IF_bm 0x08 /* Interrupt Pin 3 Flag bit mask. */ -#define VPORT_INT3IF_bp 3 /* Interrupt Pin 3 Flag bit position. */ - -#define VPORT_INT2IF_bm 0x04 /* Interrupt Pin 2 Flag bit mask. */ -#define VPORT_INT2IF_bp 2 /* Interrupt Pin 2 Flag bit position. */ - -#define VPORT_INT1IF_bm 0x02 /* Interrupt Pin 1 Flag bit mask. */ -#define VPORT_INT1IF_bp 1 /* Interrupt Pin 1 Flag bit position. */ - -#define VPORT_INT0IF_bm 0x01 /* Interrupt Pin 0 Flag bit mask. */ -#define VPORT_INT0IF_bp 0 /* Interrupt Pin 0 Flag bit position. */ - -/* XOCD - On-Chip Debug System */ -/* OCD.OCDR0 bit masks and bit positions */ -#define OCD_OCDRD_gm 0xFF /* OCDR Dirty group mask. */ -#define OCD_OCDRD_gp 0 /* OCDR Dirty group position. */ -#define OCD_OCDRD0_bm (1<<0) /* OCDR Dirty bit 0 mask. */ -#define OCD_OCDRD0_bp 0 /* OCDR Dirty bit 0 position. */ -#define OCD_OCDRD1_bm (1<<1) /* OCDR Dirty bit 1 mask. */ -#define OCD_OCDRD1_bp 1 /* OCDR Dirty bit 1 position. */ -#define OCD_OCDRD2_bm (1<<2) /* OCDR Dirty bit 2 mask. */ -#define OCD_OCDRD2_bp 2 /* OCDR Dirty bit 2 position. */ -#define OCD_OCDRD3_bm (1<<3) /* OCDR Dirty bit 3 mask. */ -#define OCD_OCDRD3_bp 3 /* OCDR Dirty bit 3 position. */ -#define OCD_OCDRD4_bm (1<<4) /* OCDR Dirty bit 4 mask. */ -#define OCD_OCDRD4_bp 4 /* OCDR Dirty bit 4 position. */ -#define OCD_OCDRD5_bm (1<<5) /* OCDR Dirty bit 5 mask. */ -#define OCD_OCDRD5_bp 5 /* OCDR Dirty bit 5 position. */ -#define OCD_OCDRD6_bm (1<<6) /* OCDR Dirty bit 6 mask. */ -#define OCD_OCDRD6_bp 6 /* OCDR Dirty bit 6 position. */ -#define OCD_OCDRD7_bm (1<<7) /* OCDR Dirty bit 7 mask. */ -#define OCD_OCDRD7_bp 7 /* OCDR Dirty bit 7 position. */ - -/* OCD.OCDR1 bit masks and bit positions */ -/* OCD_OCDRD Predefined. */ -/* OCD_OCDRD Predefined. */ - -/* CPU - CPU */ -/* CPU.CCP bit masks and bit positions */ -#define CPU_CCP_gm 0xFF /* CCP signature group mask. */ -#define CPU_CCP_gp 0 /* CCP signature group position. */ -#define CPU_CCP0_bm (1<<0) /* CCP signature bit 0 mask. */ -#define CPU_CCP0_bp 0 /* CCP signature bit 0 position. */ -#define CPU_CCP1_bm (1<<1) /* CCP signature bit 1 mask. */ -#define CPU_CCP1_bp 1 /* CCP signature bit 1 position. */ -#define CPU_CCP2_bm (1<<2) /* CCP signature bit 2 mask. */ -#define CPU_CCP2_bp 2 /* CCP signature bit 2 position. */ -#define CPU_CCP3_bm (1<<3) /* CCP signature bit 3 mask. */ -#define CPU_CCP3_bp 3 /* CCP signature bit 3 position. */ -#define CPU_CCP4_bm (1<<4) /* CCP signature bit 4 mask. */ -#define CPU_CCP4_bp 4 /* CCP signature bit 4 position. */ -#define CPU_CCP5_bm (1<<5) /* CCP signature bit 5 mask. */ -#define CPU_CCP5_bp 5 /* CCP signature bit 5 position. */ -#define CPU_CCP6_bm (1<<6) /* CCP signature bit 6 mask. */ -#define CPU_CCP6_bp 6 /* CCP signature bit 6 position. */ -#define CPU_CCP7_bm (1<<7) /* CCP signature bit 7 mask. */ -#define CPU_CCP7_bp 7 /* CCP signature bit 7 position. */ - -/* CPU.SREG bit masks and bit positions */ -#define CPU_I_bm 0x80 /* Global Interrupt Enable Flag bit mask. */ -#define CPU_I_bp 7 /* Global Interrupt Enable Flag bit position. */ - -#define CPU_T_bm 0x40 /* Transfer Bit bit mask. */ -#define CPU_T_bp 6 /* Transfer Bit bit position. */ - -#define CPU_H_bm 0x20 /* Half Carry Flag bit mask. */ -#define CPU_H_bp 5 /* Half Carry Flag bit position. */ - -#define CPU_S_bm 0x10 /* N Exclusive Or V Flag bit mask. */ -#define CPU_S_bp 4 /* N Exclusive Or V Flag bit position. */ - -#define CPU_V_bm 0x08 /* Two's Complement Overflow Flag bit mask. */ -#define CPU_V_bp 3 /* Two's Complement Overflow Flag bit position. */ - -#define CPU_N_bm 0x04 /* Negative Flag bit mask. */ -#define CPU_N_bp 2 /* Negative Flag bit position. */ - -#define CPU_Z_bm 0x02 /* Zero Flag bit mask. */ -#define CPU_Z_bp 1 /* Zero Flag bit position. */ - -#define CPU_C_bm 0x01 /* Carry Flag bit mask. */ -#define CPU_C_bp 0 /* Carry Flag bit position. */ - -/* CLK - Clock System */ -/* CLK.CTRL bit masks and bit positions */ -#define CLK_SCLKSEL_gm 0x07 /* System Clock Selection group mask. */ -#define CLK_SCLKSEL_gp 0 /* System Clock Selection group position. */ -#define CLK_SCLKSEL0_bm (1<<0) /* System Clock Selection bit 0 mask. */ -#define CLK_SCLKSEL0_bp 0 /* System Clock Selection bit 0 position. */ -#define CLK_SCLKSEL1_bm (1<<1) /* System Clock Selection bit 1 mask. */ -#define CLK_SCLKSEL1_bp 1 /* System Clock Selection bit 1 position. */ -#define CLK_SCLKSEL2_bm (1<<2) /* System Clock Selection bit 2 mask. */ -#define CLK_SCLKSEL2_bp 2 /* System Clock Selection bit 2 position. */ - -/* CLK.PSCTRL bit masks and bit positions */ -#define CLK_PSADIV_gm 0x7C /* Prescaler A Division Factor group mask. */ -#define CLK_PSADIV_gp 2 /* Prescaler A Division Factor group position. */ -#define CLK_PSADIV0_bm (1<<2) /* Prescaler A Division Factor bit 0 mask. */ -#define CLK_PSADIV0_bp 2 /* Prescaler A Division Factor bit 0 position. */ -#define CLK_PSADIV1_bm (1<<3) /* Prescaler A Division Factor bit 1 mask. */ -#define CLK_PSADIV1_bp 3 /* Prescaler A Division Factor bit 1 position. */ -#define CLK_PSADIV2_bm (1<<4) /* Prescaler A Division Factor bit 2 mask. */ -#define CLK_PSADIV2_bp 4 /* Prescaler A Division Factor bit 2 position. */ -#define CLK_PSADIV3_bm (1<<5) /* Prescaler A Division Factor bit 3 mask. */ -#define CLK_PSADIV3_bp 5 /* Prescaler A Division Factor bit 3 position. */ -#define CLK_PSADIV4_bm (1<<6) /* Prescaler A Division Factor bit 4 mask. */ -#define CLK_PSADIV4_bp 6 /* Prescaler A Division Factor bit 4 position. */ - -#define CLK_PSBCDIV_gm 0x03 /* Prescaler B and C Division factor group mask. */ -#define CLK_PSBCDIV_gp 0 /* Prescaler B and C Division factor group position. */ -#define CLK_PSBCDIV0_bm (1<<0) /* Prescaler B and C Division factor bit 0 mask. */ -#define CLK_PSBCDIV0_bp 0 /* Prescaler B and C Division factor bit 0 position. */ -#define CLK_PSBCDIV1_bm (1<<1) /* Prescaler B and C Division factor bit 1 mask. */ -#define CLK_PSBCDIV1_bp 1 /* Prescaler B and C Division factor bit 1 position. */ - -/* CLK.LOCK bit masks and bit positions */ -#define CLK_LOCK_bm 0x01 /* Clock System Lock bit mask. */ -#define CLK_LOCK_bp 0 /* Clock System Lock bit position. */ - -/* CLK.RTCCTRL bit masks and bit positions */ -#define CLK_RTCSRC_gm 0x0E /* Clock Source group mask. */ -#define CLK_RTCSRC_gp 1 /* Clock Source group position. */ -#define CLK_RTCSRC0_bm (1<<1) /* Clock Source bit 0 mask. */ -#define CLK_RTCSRC0_bp 1 /* Clock Source bit 0 position. */ -#define CLK_RTCSRC1_bm (1<<2) /* Clock Source bit 1 mask. */ -#define CLK_RTCSRC1_bp 2 /* Clock Source bit 1 position. */ -#define CLK_RTCSRC2_bm (1<<3) /* Clock Source bit 2 mask. */ -#define CLK_RTCSRC2_bp 3 /* Clock Source bit 2 position. */ - -#define CLK_RTCEN_bm 0x01 /* Clock Source Enable bit mask. */ -#define CLK_RTCEN_bp 0 /* Clock Source Enable bit position. */ - -/* PR.PRGEN bit masks and bit positions */ -#define PR_XCL_bm 0x80 /* XMEGA Custom Logic bit mask. */ -#define PR_XCL_bp 7 /* XMEGA Custom Logic bit position. */ - -#define PR_RTC_bm 0x04 /* Real-time Counter bit mask. */ -#define PR_RTC_bp 2 /* Real-time Counter bit position. */ - -#define PR_EVSYS_bm 0x02 /* Event System bit mask. */ -#define PR_EVSYS_bp 1 /* Event System bit position. */ - -#define PR_EDMA_bm 0x01 /* Enhanced DMA-Controller bit mask. */ -#define PR_EDMA_bp 0 /* Enhanced DMA-Controller bit position. */ - -/* PR.PRPA bit masks and bit positions */ -#define PR_DAC_bm 0x04 /* Port A DAC bit mask. */ -#define PR_DAC_bp 2 /* Port A DAC bit position. */ - -#define PR_ADC_bm 0x02 /* Port A ADC bit mask. */ -#define PR_ADC_bp 1 /* Port A ADC bit position. */ - -#define PR_AC_bm 0x01 /* Port A Analog Comparator bit mask. */ -#define PR_AC_bp 0 /* Port A Analog Comparator bit position. */ - -/* PR.PRPC bit masks and bit positions */ -#define PR_TWI_bm 0x40 /* Port C Two-wire Interface bit mask. */ -#define PR_TWI_bp 6 /* Port C Two-wire Interface bit position. */ - -#define PR_USART0_bm 0x10 /* Port C USART0 bit mask. */ -#define PR_USART0_bp 4 /* Port C USART0 bit position. */ - -#define PR_SPI_bm 0x08 /* Port C SPI bit mask. */ -#define PR_SPI_bp 3 /* Port C SPI bit position. */ - -#define PR_HIRES_bm 0x04 /* Port C WEX bit mask. */ -#define PR_HIRES_bp 2 /* Port C WEX bit position. */ - -#define PR_TC5_bm 0x02 /* Port C Timer/Counter5 bit mask. */ -#define PR_TC5_bp 1 /* Port C Timer/Counter5 bit position. */ - -#define PR_TC4_bm 0x01 /* Port C Timer/Counter4 bit mask. */ -#define PR_TC4_bp 0 /* Port C Timer/Counter4 bit position. */ - -/* PR.PRPD bit masks and bit positions */ -/* PR_USART0 Predefined. */ -/* PR_USART0 Predefined. */ - -/* PR_TC5 Predefined. */ -/* PR_TC5 Predefined. */ - -/* SLEEP - Sleep Controller */ -/* SLEEP.CTRL bit masks and bit positions */ -#define SLEEP_SMODE_gm 0x0E /* Sleep Mode group mask. */ -#define SLEEP_SMODE_gp 1 /* Sleep Mode group position. */ -#define SLEEP_SMODE0_bm (1<<1) /* Sleep Mode bit 0 mask. */ -#define SLEEP_SMODE0_bp 1 /* Sleep Mode bit 0 position. */ -#define SLEEP_SMODE1_bm (1<<2) /* Sleep Mode bit 1 mask. */ -#define SLEEP_SMODE1_bp 2 /* Sleep Mode bit 1 position. */ -#define SLEEP_SMODE2_bm (1<<3) /* Sleep Mode bit 2 mask. */ -#define SLEEP_SMODE2_bp 3 /* Sleep Mode bit 2 position. */ - -#define SLEEP_SEN_bm 0x01 /* Sleep Enable bit mask. */ -#define SLEEP_SEN_bp 0 /* Sleep Enable bit position. */ - -/* OSC - Oscillator */ -/* OSC.CTRL bit masks and bit positions */ -#define OSC_RC8MLPM_bm 0x40 /* Internal 8 MHz RC Low Power Mode Enable bit mask. */ -#define OSC_RC8MLPM_bp 6 /* Internal 8 MHz RC Low Power Mode Enable bit position. */ - -#define OSC_RC8MEN_bm 0x20 /* Internal 8 MHz RC Oscillator Enable bit mask. */ -#define OSC_RC8MEN_bp 5 /* Internal 8 MHz RC Oscillator Enable bit position. */ - -#define OSC_PLLEN_bm 0x10 /* PLL Enable bit mask. */ -#define OSC_PLLEN_bp 4 /* PLL Enable bit position. */ - -#define OSC_XOSCEN_bm 0x08 /* External Oscillator Enable bit mask. */ -#define OSC_XOSCEN_bp 3 /* External Oscillator Enable bit position. */ - -#define OSC_RC32KEN_bm 0x04 /* Internal 32.768 kHz RC Oscillator Enable bit mask. */ -#define OSC_RC32KEN_bp 2 /* Internal 32.768 kHz RC Oscillator Enable bit position. */ - -#define OSC_RC32MEN_bm 0x02 /* Internal 32 MHz RC Oscillator Enable bit mask. */ -#define OSC_RC32MEN_bp 1 /* Internal 32 MHz RC Oscillator Enable bit position. */ - -#define OSC_RC2MEN_bm 0x01 /* Internal 2 MHz RC Oscillator Enable bit mask. */ -#define OSC_RC2MEN_bp 0 /* Internal 2 MHz RC Oscillator Enable bit position. */ - -/* OSC.STATUS bit masks and bit positions */ -#define OSC_RC8MRDY_bm 0x20 /* Internal 8 MHz RC Oscillator Ready bit mask. */ -#define OSC_RC8MRDY_bp 5 /* Internal 8 MHz RC Oscillator Ready bit position. */ - -#define OSC_PLLRDY_bm 0x10 /* PLL Ready bit mask. */ -#define OSC_PLLRDY_bp 4 /* PLL Ready bit position. */ - -#define OSC_XOSCRDY_bm 0x08 /* External Oscillator Ready bit mask. */ -#define OSC_XOSCRDY_bp 3 /* External Oscillator Ready bit position. */ - -#define OSC_RC32KRDY_bm 0x04 /* Internal 32.768 kHz RC Oscillator Ready bit mask. */ -#define OSC_RC32KRDY_bp 2 /* Internal 32.768 kHz RC Oscillator Ready bit position. */ - -#define OSC_RC32MRDY_bm 0x02 /* Internal 32 MHz RC Oscillator Ready bit mask. */ -#define OSC_RC32MRDY_bp 1 /* Internal 32 MHz RC Oscillator Ready bit position. */ - -#define OSC_RC2MRDY_bm 0x01 /* Internal 2 MHz RC Oscillator Ready bit mask. */ -#define OSC_RC2MRDY_bp 0 /* Internal 2 MHz RC Oscillator Ready bit position. */ - -/* OSC.XOSCCTRL bit masks and bit positions */ -#define OSC_FRQRANGE_gm 0xC0 /* Frequency Range group mask. */ -#define OSC_FRQRANGE_gp 6 /* Frequency Range group position. */ -#define OSC_FRQRANGE0_bm (1<<6) /* Frequency Range bit 0 mask. */ -#define OSC_FRQRANGE0_bp 6 /* Frequency Range bit 0 position. */ -#define OSC_FRQRANGE1_bm (1<<7) /* Frequency Range bit 1 mask. */ -#define OSC_FRQRANGE1_bp 7 /* Frequency Range bit 1 position. */ - -#define OSC_X32KLPM_bm 0x20 /* 32.768 kHz XTAL OSC Low-power Mode bit mask. */ -#define OSC_X32KLPM_bp 5 /* 32.768 kHz XTAL OSC Low-power Mode bit position. */ - -#define OSC_XOSCPWR_bm 0x10 /* 16 MHz Crystal Oscillator High Power mode bit mask. */ -#define OSC_XOSCPWR_bp 4 /* 16 MHz Crystal Oscillator High Power mode bit position. */ - -#define OSC_XOSCSEL_gm 0x1F /* External Oscillator Selection and Startup Time group mask. */ -#define OSC_XOSCSEL_gp 0 /* External Oscillator Selection and Startup Time group position. */ -#define OSC_XOSCSEL0_bm (1<<0) /* External Oscillator Selection and Startup Time bit 0 mask. */ -#define OSC_XOSCSEL0_bp 0 /* External Oscillator Selection and Startup Time bit 0 position. */ -#define OSC_XOSCSEL1_bm (1<<1) /* External Oscillator Selection and Startup Time bit 1 mask. */ -#define OSC_XOSCSEL1_bp 1 /* External Oscillator Selection and Startup Time bit 1 position. */ -#define OSC_XOSCSEL2_bm (1<<2) /* External Oscillator Selection and Startup Time bit 2 mask. */ -#define OSC_XOSCSEL2_bp 2 /* External Oscillator Selection and Startup Time bit 2 position. */ -#define OSC_XOSCSEL3_bm (1<<3) /* External Oscillator Selection and Startup Time bit 3 mask. */ -#define OSC_XOSCSEL3_bp 3 /* External Oscillator Selection and Startup Time bit 3 position. */ -#define OSC_XOSCSEL4_bm (1<<4) /* External Oscillator Selection and Startup Time bit 4 mask. */ -#define OSC_XOSCSEL4_bp 4 /* External Oscillator Selection and Startup Time bit 4 position. */ - -/* OSC.XOSCFAIL bit masks and bit positions */ -#define OSC_PLLFDIF_bm 0x08 /* PLL Failure Detection Interrupt Flag bit mask. */ -#define OSC_PLLFDIF_bp 3 /* PLL Failure Detection Interrupt Flag bit position. */ - -#define OSC_PLLFDEN_bm 0x04 /* PLL Failure Detection Enable bit mask. */ -#define OSC_PLLFDEN_bp 2 /* PLL Failure Detection Enable bit position. */ - -#define OSC_XOSCFDIF_bm 0x02 /* XOSC Failure Detection Interrupt Flag bit mask. */ -#define OSC_XOSCFDIF_bp 1 /* XOSC Failure Detection Interrupt Flag bit position. */ - -#define OSC_XOSCFDEN_bm 0x01 /* XOSC Failure Detection Enable bit mask. */ -#define OSC_XOSCFDEN_bp 0 /* XOSC Failure Detection Enable bit position. */ - -/* OSC.PLLCTRL bit masks and bit positions */ -#define OSC_PLLSRC_gm 0xC0 /* Clock Source group mask. */ -#define OSC_PLLSRC_gp 6 /* Clock Source group position. */ -#define OSC_PLLSRC0_bm (1<<6) /* Clock Source bit 0 mask. */ -#define OSC_PLLSRC0_bp 6 /* Clock Source bit 0 position. */ -#define OSC_PLLSRC1_bm (1<<7) /* Clock Source bit 1 mask. */ -#define OSC_PLLSRC1_bp 7 /* Clock Source bit 1 position. */ - -#define OSC_PLLDIV_bm 0x20 /* Divide by 2 bit mask. */ -#define OSC_PLLDIV_bp 5 /* Divide by 2 bit position. */ - -#define OSC_PLLFAC_gm 0x1F /* Multiplication Factor group mask. */ -#define OSC_PLLFAC_gp 0 /* Multiplication Factor group position. */ -#define OSC_PLLFAC0_bm (1<<0) /* Multiplication Factor bit 0 mask. */ -#define OSC_PLLFAC0_bp 0 /* Multiplication Factor bit 0 position. */ -#define OSC_PLLFAC1_bm (1<<1) /* Multiplication Factor bit 1 mask. */ -#define OSC_PLLFAC1_bp 1 /* Multiplication Factor bit 1 position. */ -#define OSC_PLLFAC2_bm (1<<2) /* Multiplication Factor bit 2 mask. */ -#define OSC_PLLFAC2_bp 2 /* Multiplication Factor bit 2 position. */ -#define OSC_PLLFAC3_bm (1<<3) /* Multiplication Factor bit 3 mask. */ -#define OSC_PLLFAC3_bp 3 /* Multiplication Factor bit 3 position. */ -#define OSC_PLLFAC4_bm (1<<4) /* Multiplication Factor bit 4 mask. */ -#define OSC_PLLFAC4_bp 4 /* Multiplication Factor bit 4 position. */ - -/* OSC.DFLLCTRL bit masks and bit positions */ -#define OSC_RC32MCREF_gm 0x06 /* 32 MHz DFLL Calibration Reference group mask. */ -#define OSC_RC32MCREF_gp 1 /* 32 MHz DFLL Calibration Reference group position. */ -#define OSC_RC32MCREF0_bm (1<<1) /* 32 MHz DFLL Calibration Reference bit 0 mask. */ -#define OSC_RC32MCREF0_bp 1 /* 32 MHz DFLL Calibration Reference bit 0 position. */ -#define OSC_RC32MCREF1_bm (1<<2) /* 32 MHz DFLL Calibration Reference bit 1 mask. */ -#define OSC_RC32MCREF1_bp 2 /* 32 MHz DFLL Calibration Reference bit 1 position. */ - -/* OSC.RC8MCAL bit masks and bit positions */ -#define OSC_RC8MCAL_gm 0xFF /* Calibration Bits group mask. */ -#define OSC_RC8MCAL_gp 0 /* Calibration Bits group position. */ -#define OSC_RC8MCAL0_bm (1<<0) /* Calibration Bits bit 0 mask. */ -#define OSC_RC8MCAL0_bp 0 /* Calibration Bits bit 0 position. */ -#define OSC_RC8MCAL1_bm (1<<1) /* Calibration Bits bit 1 mask. */ -#define OSC_RC8MCAL1_bp 1 /* Calibration Bits bit 1 position. */ -#define OSC_RC8MCAL2_bm (1<<2) /* Calibration Bits bit 2 mask. */ -#define OSC_RC8MCAL2_bp 2 /* Calibration Bits bit 2 position. */ -#define OSC_RC8MCAL3_bm (1<<3) /* Calibration Bits bit 3 mask. */ -#define OSC_RC8MCAL3_bp 3 /* Calibration Bits bit 3 position. */ -#define OSC_RC8MCAL4_bm (1<<4) /* Calibration Bits bit 4 mask. */ -#define OSC_RC8MCAL4_bp 4 /* Calibration Bits bit 4 position. */ -#define OSC_RC8MCAL5_bm (1<<5) /* Calibration Bits bit 5 mask. */ -#define OSC_RC8MCAL5_bp 5 /* Calibration Bits bit 5 position. */ -#define OSC_RC8MCAL6_bm (1<<6) /* Calibration Bits bit 6 mask. */ -#define OSC_RC8MCAL6_bp 6 /* Calibration Bits bit 6 position. */ -#define OSC_RC8MCAL7_bm (1<<7) /* Calibration Bits bit 7 mask. */ -#define OSC_RC8MCAL7_bp 7 /* Calibration Bits bit 7 position. */ - -/* DFLL - DFLL */ -/* DFLL.CTRL bit masks and bit positions */ -#define DFLL_ENABLE_bm 0x01 /* DFLL Enable bit mask. */ -#define DFLL_ENABLE_bp 0 /* DFLL Enable bit position. */ - -/* DFLL.CALA bit masks and bit positions */ -#define DFLL_CALL_gm 0x7F /* DFLL Calibration Value A group mask. */ -#define DFLL_CALL_gp 0 /* DFLL Calibration Value A group position. */ -#define DFLL_CALL0_bm (1<<0) /* DFLL Calibration Value A bit 0 mask. */ -#define DFLL_CALL0_bp 0 /* DFLL Calibration Value A bit 0 position. */ -#define DFLL_CALL1_bm (1<<1) /* DFLL Calibration Value A bit 1 mask. */ -#define DFLL_CALL1_bp 1 /* DFLL Calibration Value A bit 1 position. */ -#define DFLL_CALL2_bm (1<<2) /* DFLL Calibration Value A bit 2 mask. */ -#define DFLL_CALL2_bp 2 /* DFLL Calibration Value A bit 2 position. */ -#define DFLL_CALL3_bm (1<<3) /* DFLL Calibration Value A bit 3 mask. */ -#define DFLL_CALL3_bp 3 /* DFLL Calibration Value A bit 3 position. */ -#define DFLL_CALL4_bm (1<<4) /* DFLL Calibration Value A bit 4 mask. */ -#define DFLL_CALL4_bp 4 /* DFLL Calibration Value A bit 4 position. */ -#define DFLL_CALL5_bm (1<<5) /* DFLL Calibration Value A bit 5 mask. */ -#define DFLL_CALL5_bp 5 /* DFLL Calibration Value A bit 5 position. */ -#define DFLL_CALL6_bm (1<<6) /* DFLL Calibration Value A bit 6 mask. */ -#define DFLL_CALL6_bp 6 /* DFLL Calibration Value A bit 6 position. */ - -/* DFLL.CALB bit masks and bit positions */ -#define DFLL_CALH_gm 0x3F /* DFLL Calibration Value B group mask. */ -#define DFLL_CALH_gp 0 /* DFLL Calibration Value B group position. */ -#define DFLL_CALH0_bm (1<<0) /* DFLL Calibration Value B bit 0 mask. */ -#define DFLL_CALH0_bp 0 /* DFLL Calibration Value B bit 0 position. */ -#define DFLL_CALH1_bm (1<<1) /* DFLL Calibration Value B bit 1 mask. */ -#define DFLL_CALH1_bp 1 /* DFLL Calibration Value B bit 1 position. */ -#define DFLL_CALH2_bm (1<<2) /* DFLL Calibration Value B bit 2 mask. */ -#define DFLL_CALH2_bp 2 /* DFLL Calibration Value B bit 2 position. */ -#define DFLL_CALH3_bm (1<<3) /* DFLL Calibration Value B bit 3 mask. */ -#define DFLL_CALH3_bp 3 /* DFLL Calibration Value B bit 3 position. */ -#define DFLL_CALH4_bm (1<<4) /* DFLL Calibration Value B bit 4 mask. */ -#define DFLL_CALH4_bp 4 /* DFLL Calibration Value B bit 4 position. */ -#define DFLL_CALH5_bm (1<<5) /* DFLL Calibration Value B bit 5 mask. */ -#define DFLL_CALH5_bp 5 /* DFLL Calibration Value B bit 5 position. */ - -/* RST - Reset */ -/* RST.STATUS bit masks and bit positions */ -#define RST_SDRF_bm 0x40 /* Spike Detection Reset Flag bit mask. */ -#define RST_SDRF_bp 6 /* Spike Detection Reset Flag bit position. */ - -#define RST_SRF_bm 0x20 /* Software Reset Flag bit mask. */ -#define RST_SRF_bp 5 /* Software Reset Flag bit position. */ - -#define RST_PDIRF_bm 0x10 /* Programming and Debug Interface Interface Reset Flag bit mask. */ -#define RST_PDIRF_bp 4 /* Programming and Debug Interface Interface Reset Flag bit position. */ - -#define RST_WDRF_bm 0x08 /* Watchdog Reset Flag bit mask. */ -#define RST_WDRF_bp 3 /* Watchdog Reset Flag bit position. */ - -#define RST_BORF_bm 0x04 /* Brown-out Reset Flag bit mask. */ -#define RST_BORF_bp 2 /* Brown-out Reset Flag bit position. */ - -#define RST_EXTRF_bm 0x02 /* External Reset Flag bit mask. */ -#define RST_EXTRF_bp 1 /* External Reset Flag bit position. */ - -#define RST_PORF_bm 0x01 /* Power-on Reset Flag bit mask. */ -#define RST_PORF_bp 0 /* Power-on Reset Flag bit position. */ - -/* RST.CTRL bit masks and bit positions */ -#define RST_SWRST_bm 0x01 /* Software Reset bit mask. */ -#define RST_SWRST_bp 0 /* Software Reset bit position. */ - -/* WDT - Watch-Dog Timer */ -/* WDT.CTRL bit masks and bit positions */ -#define WDT_PER_gm 0x3C /* Period group mask. */ -#define WDT_PER_gp 2 /* Period group position. */ -#define WDT_PER0_bm (1<<2) /* Period bit 0 mask. */ -#define WDT_PER0_bp 2 /* Period bit 0 position. */ -#define WDT_PER1_bm (1<<3) /* Period bit 1 mask. */ -#define WDT_PER1_bp 3 /* Period bit 1 position. */ -#define WDT_PER2_bm (1<<4) /* Period bit 2 mask. */ -#define WDT_PER2_bp 4 /* Period bit 2 position. */ -#define WDT_PER3_bm (1<<5) /* Period bit 3 mask. */ -#define WDT_PER3_bp 5 /* Period bit 3 position. */ - -#define WDT_ENABLE_bm 0x02 /* Enable bit mask. */ -#define WDT_ENABLE_bp 1 /* Enable bit position. */ - -#define WDT_CEN_bm 0x01 /* Change Enable bit mask. */ -#define WDT_CEN_bp 0 /* Change Enable bit position. */ - -/* WDT.WINCTRL bit masks and bit positions */ -#define WDT_WPER_gm 0x3C /* Windowed Mode Period group mask. */ -#define WDT_WPER_gp 2 /* Windowed Mode Period group position. */ -#define WDT_WPER0_bm (1<<2) /* Windowed Mode Period bit 0 mask. */ -#define WDT_WPER0_bp 2 /* Windowed Mode Period bit 0 position. */ -#define WDT_WPER1_bm (1<<3) /* Windowed Mode Period bit 1 mask. */ -#define WDT_WPER1_bp 3 /* Windowed Mode Period bit 1 position. */ -#define WDT_WPER2_bm (1<<4) /* Windowed Mode Period bit 2 mask. */ -#define WDT_WPER2_bp 4 /* Windowed Mode Period bit 2 position. */ -#define WDT_WPER3_bm (1<<5) /* Windowed Mode Period bit 3 mask. */ -#define WDT_WPER3_bp 5 /* Windowed Mode Period bit 3 position. */ - -#define WDT_WEN_bm 0x02 /* Windowed Mode Enable bit mask. */ -#define WDT_WEN_bp 1 /* Windowed Mode Enable bit position. */ - -#define WDT_WCEN_bm 0x01 /* Windowed Mode Change Enable bit mask. */ -#define WDT_WCEN_bp 0 /* Windowed Mode Change Enable bit position. */ - -/* WDT.STATUS bit masks and bit positions */ -#define WDT_SYNCBUSY_bm 0x01 /* Syncronization busy bit mask. */ -#define WDT_SYNCBUSY_bp 0 /* Syncronization busy bit position. */ - -/* MCU - MCU Control */ -/* MCU.ANAINIT bit masks and bit positions */ -#define MCU_STARTUPDLYA_gm 0x03 /* Analog startup delay Port A group mask. */ -#define MCU_STARTUPDLYA_gp 0 /* Analog startup delay Port A group position. */ -#define MCU_STARTUPDLYA0_bm (1<<0) /* Analog startup delay Port A bit 0 mask. */ -#define MCU_STARTUPDLYA0_bp 0 /* Analog startup delay Port A bit 0 position. */ -#define MCU_STARTUPDLYA1_bm (1<<1) /* Analog startup delay Port A bit 1 mask. */ -#define MCU_STARTUPDLYA1_bp 1 /* Analog startup delay Port A bit 1 position. */ - -/* MCU.EVSYSLOCK bit masks and bit positions */ -#define MCU_EVSYS1LOCK_bm 0x10 /* Event Channel 4-7 Lock bit mask. */ -#define MCU_EVSYS1LOCK_bp 4 /* Event Channel 4-7 Lock bit position. */ - -#define MCU_EVSYS0LOCK_bm 0x01 /* Event Channel 0-3 Lock bit mask. */ -#define MCU_EVSYS0LOCK_bp 0 /* Event Channel 0-3 Lock bit position. */ - -/* MCU.WEXLOCK bit masks and bit positions */ -#define MCU_WEXCLOCK_bm 0x01 /* WeX on T/C C4 Lock bit mask. */ -#define MCU_WEXCLOCK_bp 0 /* WeX on T/C C4 Lock bit position. */ - -/* MCU.FAULTLOCK bit masks and bit positions */ -#define MCU_FAULTC5LOCK_bm 0x02 /* Fault on T/C C5 Lock bit mask. */ -#define MCU_FAULTC5LOCK_bp 1 /* Fault on T/C C5 Lock bit position. */ - -#define MCU_FAULTC4LOCK_bm 0x01 /* Fault on T/C C4 Lock bit mask. */ -#define MCU_FAULTC4LOCK_bp 0 /* Fault on T/C C4 Lock bit position. */ - -/* PMIC - Programmable Multi-level Interrupt Controller */ -/* PMIC.STATUS bit masks and bit positions */ -#define PMIC_NMIEX_bm 0x80 /* Non-maskable Interrupt Executing bit mask. */ -#define PMIC_NMIEX_bp 7 /* Non-maskable Interrupt Executing bit position. */ - -#define PMIC_HILVLEX_bm 0x04 /* High Level Interrupt Executing bit mask. */ -#define PMIC_HILVLEX_bp 2 /* High Level Interrupt Executing bit position. */ - -#define PMIC_MEDLVLEX_bm 0x02 /* Medium Level Interrupt Executing bit mask. */ -#define PMIC_MEDLVLEX_bp 1 /* Medium Level Interrupt Executing bit position. */ - -#define PMIC_LOLVLEX_bm 0x01 /* Low Level Interrupt Executing bit mask. */ -#define PMIC_LOLVLEX_bp 0 /* Low Level Interrupt Executing bit position. */ - -/* PMIC.INTPRI bit masks and bit positions */ -#define PMIC_INTPRI_gm 0xFF /* Interrupt Priority group mask. */ -#define PMIC_INTPRI_gp 0 /* Interrupt Priority group position. */ -#define PMIC_INTPRI0_bm (1<<0) /* Interrupt Priority bit 0 mask. */ -#define PMIC_INTPRI0_bp 0 /* Interrupt Priority bit 0 position. */ -#define PMIC_INTPRI1_bm (1<<1) /* Interrupt Priority bit 1 mask. */ -#define PMIC_INTPRI1_bp 1 /* Interrupt Priority bit 1 position. */ -#define PMIC_INTPRI2_bm (1<<2) /* Interrupt Priority bit 2 mask. */ -#define PMIC_INTPRI2_bp 2 /* Interrupt Priority bit 2 position. */ -#define PMIC_INTPRI3_bm (1<<3) /* Interrupt Priority bit 3 mask. */ -#define PMIC_INTPRI3_bp 3 /* Interrupt Priority bit 3 position. */ -#define PMIC_INTPRI4_bm (1<<4) /* Interrupt Priority bit 4 mask. */ -#define PMIC_INTPRI4_bp 4 /* Interrupt Priority bit 4 position. */ -#define PMIC_INTPRI5_bm (1<<5) /* Interrupt Priority bit 5 mask. */ -#define PMIC_INTPRI5_bp 5 /* Interrupt Priority bit 5 position. */ -#define PMIC_INTPRI6_bm (1<<6) /* Interrupt Priority bit 6 mask. */ -#define PMIC_INTPRI6_bp 6 /* Interrupt Priority bit 6 position. */ -#define PMIC_INTPRI7_bm (1<<7) /* Interrupt Priority bit 7 mask. */ -#define PMIC_INTPRI7_bp 7 /* Interrupt Priority bit 7 position. */ - -/* PMIC.CTRL bit masks and bit positions */ -#define PMIC_RREN_bm 0x80 /* Round-Robin Priority Enable bit mask. */ -#define PMIC_RREN_bp 7 /* Round-Robin Priority Enable bit position. */ - -#define PMIC_IVSEL_bm 0x40 /* Interrupt Vector Select bit mask. */ -#define PMIC_IVSEL_bp 6 /* Interrupt Vector Select bit position. */ - -#define PMIC_HILVLEN_bm 0x04 /* High Level Enable bit mask. */ -#define PMIC_HILVLEN_bp 2 /* High Level Enable bit position. */ - -#define PMIC_MEDLVLEN_bm 0x02 /* Medium Level Enable bit mask. */ -#define PMIC_MEDLVLEN_bp 1 /* Medium Level Enable bit position. */ - -#define PMIC_LOLVLEN_bm 0x01 /* Low Level Enable bit mask. */ -#define PMIC_LOLVLEN_bp 0 /* Low Level Enable bit position. */ - -/* PORTCFG - Port Configuration */ -/* PORTCFG.CLKOUT bit masks and bit positions */ -#define PORTCFG_CLKEVPIN_bm 0x80 /* Clock and Event Output Pin Select bit mask. */ -#define PORTCFG_CLKEVPIN_bp 7 /* Clock and Event Output Pin Select bit position. */ - -#define PORTCFG_RTCOUT_gm 0x60 /* RTC Clock Output Enable group mask. */ -#define PORTCFG_RTCOUT_gp 5 /* RTC Clock Output Enable group position. */ -#define PORTCFG_RTCOUT0_bm (1<<5) /* RTC Clock Output Enable bit 0 mask. */ -#define PORTCFG_RTCOUT0_bp 5 /* RTC Clock Output Enable bit 0 position. */ -#define PORTCFG_RTCOUT1_bm (1<<6) /* RTC Clock Output Enable bit 1 mask. */ -#define PORTCFG_RTCOUT1_bp 6 /* RTC Clock Output Enable bit 1 position. */ - -#define PORTCFG_CLKOUTSEL_gm 0x0C /* Clock Output Select group mask. */ -#define PORTCFG_CLKOUTSEL_gp 2 /* Clock Output Select group position. */ -#define PORTCFG_CLKOUTSEL0_bm (1<<2) /* Clock Output Select bit 0 mask. */ -#define PORTCFG_CLKOUTSEL0_bp 2 /* Clock Output Select bit 0 position. */ -#define PORTCFG_CLKOUTSEL1_bm (1<<3) /* Clock Output Select bit 1 mask. */ -#define PORTCFG_CLKOUTSEL1_bp 3 /* Clock Output Select bit 1 position. */ - -#define PORTCFG_CLKOUT_gm 0x03 /* Clock Output Port group mask. */ -#define PORTCFG_CLKOUT_gp 0 /* Clock Output Port group position. */ -#define PORTCFG_CLKOUT0_bm (1<<0) /* Clock Output Port bit 0 mask. */ -#define PORTCFG_CLKOUT0_bp 0 /* Clock Output Port bit 0 position. */ -#define PORTCFG_CLKOUT1_bm (1<<1) /* Clock Output Port bit 1 mask. */ -#define PORTCFG_CLKOUT1_bp 1 /* Clock Output Port bit 1 position. */ - -/* PORTCFG.ACEVOUT bit masks and bit positions */ -#define PORTCFG_ACOUT_gm 0xC0 /* Analog Comparator Output Port group mask. */ -#define PORTCFG_ACOUT_gp 6 /* Analog Comparator Output Port group position. */ -#define PORTCFG_ACOUT0_bm (1<<6) /* Analog Comparator Output Port bit 0 mask. */ -#define PORTCFG_ACOUT0_bp 6 /* Analog Comparator Output Port bit 0 position. */ -#define PORTCFG_ACOUT1_bm (1<<7) /* Analog Comparator Output Port bit 1 mask. */ -#define PORTCFG_ACOUT1_bp 7 /* Analog Comparator Output Port bit 1 position. */ - -#define PORTCFG_EVOUT_gm 0x30 /* Event Channel Output Port group mask. */ -#define PORTCFG_EVOUT_gp 4 /* Event Channel Output Port group position. */ -#define PORTCFG_EVOUT0_bm (1<<4) /* Event Channel Output Port bit 0 mask. */ -#define PORTCFG_EVOUT0_bp 4 /* Event Channel Output Port bit 0 position. */ -#define PORTCFG_EVOUT1_bm (1<<5) /* Event Channel Output Port bit 1 mask. */ -#define PORTCFG_EVOUT1_bp 5 /* Event Channel Output Port bit 1 position. */ - -#define PORTCFG_EVASYEN_bm 0x08 /* Asynchronous Event Enabled bit mask. */ -#define PORTCFG_EVASYEN_bp 3 /* Asynchronous Event Enabled bit position. */ - -#define PORTCFG_EVOUTSEL_gm 0x07 /* Event Channel Output Selection group mask. */ -#define PORTCFG_EVOUTSEL_gp 0 /* Event Channel Output Selection group position. */ -#define PORTCFG_EVOUTSEL0_bm (1<<0) /* Event Channel Output Selection bit 0 mask. */ -#define PORTCFG_EVOUTSEL0_bp 0 /* Event Channel Output Selection bit 0 position. */ -#define PORTCFG_EVOUTSEL1_bm (1<<1) /* Event Channel Output Selection bit 1 mask. */ -#define PORTCFG_EVOUTSEL1_bp 1 /* Event Channel Output Selection bit 1 position. */ -#define PORTCFG_EVOUTSEL2_bm (1<<2) /* Event Channel Output Selection bit 2 mask. */ -#define PORTCFG_EVOUTSEL2_bp 2 /* Event Channel Output Selection bit 2 position. */ - -/* PORTCFG.SRLCTRL bit masks and bit positions */ -#define PORTCFG_SRLENRA_bm 0x01 /* Slew Rate Limit Enable on PORTA bit mask. */ -#define PORTCFG_SRLENRA_bp 0 /* Slew Rate Limit Enable on PORTA bit position. */ - -#define PORTCFG_SRLENRC_bm 0x04 /* Slew Rate Limit Enable on PORTC bit mask. */ -#define PORTCFG_SRLENRC_bp 2 /* Slew Rate Limit Enable on PORTC bit position. */ - -#define PORTCFG_SRLENRD_bm 0x08 /* Slew Rate Limit Enable on PORTD bit mask. */ -#define PORTCFG_SRLENRD_bp 3 /* Slew Rate Limit Enable on PORTD bit position. */ - -#define PORTCFG_SRLENRR_bm 0x80 /* Slew Rate Limit Enable on PORTR bit mask. */ -#define PORTCFG_SRLENRR_bp 7 /* Slew Rate Limit Enable on PORTR bit position. */ - -/* CRC - Cyclic Redundancy Checker */ -/* CRC.CTRL bit masks and bit positions */ -#define CRC_RESET_gm 0xC0 /* Reset group mask. */ -#define CRC_RESET_gp 6 /* Reset group position. */ -#define CRC_RESET0_bm (1<<6) /* Reset bit 0 mask. */ -#define CRC_RESET0_bp 6 /* Reset bit 0 position. */ -#define CRC_RESET1_bm (1<<7) /* Reset bit 1 mask. */ -#define CRC_RESET1_bp 7 /* Reset bit 1 position. */ - -#define CRC_CRC32_bm 0x20 /* CRC Mode bit mask. */ -#define CRC_CRC32_bp 5 /* CRC Mode bit position. */ - -#define CRC_SOURCE_gm 0x0F /* Input Source group mask. */ -#define CRC_SOURCE_gp 0 /* Input Source group position. */ -#define CRC_SOURCE0_bm (1<<0) /* Input Source bit 0 mask. */ -#define CRC_SOURCE0_bp 0 /* Input Source bit 0 position. */ -#define CRC_SOURCE1_bm (1<<1) /* Input Source bit 1 mask. */ -#define CRC_SOURCE1_bp 1 /* Input Source bit 1 position. */ -#define CRC_SOURCE2_bm (1<<2) /* Input Source bit 2 mask. */ -#define CRC_SOURCE2_bp 2 /* Input Source bit 2 position. */ -#define CRC_SOURCE3_bm (1<<3) /* Input Source bit 3 mask. */ -#define CRC_SOURCE3_bp 3 /* Input Source bit 3 position. */ - -/* CRC.STATUS bit masks and bit positions */ -#define CRC_ZERO_bm 0x02 /* Zero detection bit mask. */ -#define CRC_ZERO_bp 1 /* Zero detection bit position. */ - -#define CRC_BUSY_bm 0x01 /* Busy bit mask. */ -#define CRC_BUSY_bp 0 /* Busy bit position. */ - -/* EDMA - Enhanced DMA Controller */ -/* EDMA.CTRL bit masks and bit positions */ -#define EDMA_ENABLE_bm 0x80 /* Enable bit mask. */ -#define EDMA_ENABLE_bp 7 /* Enable bit position. */ - -#define EDMA_RESET_bm 0x40 /* Software Reset bit mask. */ -#define EDMA_RESET_bp 6 /* Software Reset bit position. */ - -#define EDMA_CHMODE_gm 0x30 /* Channel Mode group mask. */ -#define EDMA_CHMODE_gp 4 /* Channel Mode group position. */ -#define EDMA_CHMODE0_bm (1<<4) /* Channel Mode bit 0 mask. */ -#define EDMA_CHMODE0_bp 4 /* Channel Mode bit 0 position. */ -#define EDMA_CHMODE1_bm (1<<5) /* Channel Mode bit 1 mask. */ -#define EDMA_CHMODE1_bp 5 /* Channel Mode bit 1 position. */ - -#define EDMA_DBUFMODE_gm 0x0C /* Double Buffer Mode group mask. */ -#define EDMA_DBUFMODE_gp 2 /* Double Buffer Mode group position. */ -#define EDMA_DBUFMODE0_bm (1<<2) /* Double Buffer Mode bit 0 mask. */ -#define EDMA_DBUFMODE0_bp 2 /* Double Buffer Mode bit 0 position. */ -#define EDMA_DBUFMODE1_bm (1<<3) /* Double Buffer Mode bit 1 mask. */ -#define EDMA_DBUFMODE1_bp 3 /* Double Buffer Mode bit 1 position. */ - -#define EDMA_PRIMODE_gm 0x03 /* Priority Mode group mask. */ -#define EDMA_PRIMODE_gp 0 /* Priority Mode group position. */ -#define EDMA_PRIMODE0_bm (1<<0) /* Priority Mode bit 0 mask. */ -#define EDMA_PRIMODE0_bp 0 /* Priority Mode bit 0 position. */ -#define EDMA_PRIMODE1_bm (1<<1) /* Priority Mode bit 1 mask. */ -#define EDMA_PRIMODE1_bp 1 /* Priority Mode bit 1 position. */ - -/* EDMA.INTFLAGS bit masks and bit positions */ -#define EDMA_CH3ERRIF_bm 0x80 /* Channel 3 Transaction Error Interrupt Flag bit mask. */ -#define EDMA_CH3ERRIF_bp 7 /* Channel 3 Transaction Error Interrupt Flag bit position. */ - -#define EDMA_CH2ERRIF_bm 0x40 /* Channel 2 Transaction Error Interrupt Flag bit mask. */ -#define EDMA_CH2ERRIF_bp 6 /* Channel 2 Transaction Error Interrupt Flag bit position. */ - -#define EDMA_CH1ERRIF_bm 0x20 /* Channel 1 Transaction Error Interrupt Flag bit mask. */ -#define EDMA_CH1ERRIF_bp 5 /* Channel 1 Transaction Error Interrupt Flag bit position. */ - -#define EDMA_CH0ERRIF_bm 0x10 /* Channel 0 Transaction Error Interrupt Flag bit mask. */ -#define EDMA_CH0ERRIF_bp 4 /* Channel 0 Transaction Error Interrupt Flag bit position. */ - -#define EDMA_CH3TRNFIF_bm 0x08 /* Channel 3 Transaction Complete Interrupt Flag bit mask. */ -#define EDMA_CH3TRNFIF_bp 3 /* Channel 3 Transaction Complete Interrupt Flag bit position. */ - -#define EDMA_CH2TRNFIF_bm 0x04 /* Channel 2 Transaction Complete Interrupt Flag bit mask. */ -#define EDMA_CH2TRNFIF_bp 2 /* Channel 2 Transaction Complete Interrupt Flag bit position. */ - -#define EDMA_CH1TRNFIF_bm 0x02 /* Channel 1 Transaction Complete Interrupt Flag bit mask. */ -#define EDMA_CH1TRNFIF_bp 1 /* Channel 1 Transaction Complete Interrupt Flag bit position. */ - -#define EDMA_CH0TRNFIF_bm 0x01 /* Channel 0 Transaction Complete Interrupt Flag bit mask. */ -#define EDMA_CH0TRNFIF_bp 0 /* Channel 0 Transaction Complete Interrupt Flag bit position. */ - -/* EDMA.STATUS bit masks and bit positions */ -#define EDMA_CH3BUSY_bm 0x80 /* Channel 3 Busy Flag bit mask. */ -#define EDMA_CH3BUSY_bp 7 /* Channel 3 Busy Flag bit position. */ - -#define EDMA_CH2BUSY_bm 0x40 /* Channel 2 Busy Flag bit mask. */ -#define EDMA_CH2BUSY_bp 6 /* Channel 2 Busy Flag bit position. */ - -#define EDMA_CH1BUSY_bm 0x20 /* Channel 1 Busy Flag bit mask. */ -#define EDMA_CH1BUSY_bp 5 /* Channel 1 Busy Flag bit position. */ - -#define EDMA_CH0BUSY_bm 0x10 /* Channel 0 Busy Flag bit mask. */ -#define EDMA_CH0BUSY_bp 4 /* Channel 0 Busy Flag bit position. */ - -#define EDMA_CH3PEND_bm 0x08 /* Channel 3 Pending Flag bit mask. */ -#define EDMA_CH3PEND_bp 3 /* Channel 3 Pending Flag bit position. */ - -#define EDMA_CH2PEND_bm 0x04 /* Channel 2 Pending Flag bit mask. */ -#define EDMA_CH2PEND_bp 2 /* Channel 2 Pending Flag bit position. */ - -#define EDMA_CH1PEND_bm 0x02 /* Channel 1 Pending Flag bit mask. */ -#define EDMA_CH1PEND_bp 1 /* Channel 1 Pending Flag bit position. */ - -#define EDMA_CH0PEND_bm 0x01 /* Channel 0 Pending Flag bit mask. */ -#define EDMA_CH0PEND_bp 0 /* Channel 0 Pending Flag bit position. */ - -/* EDMA_CH.CTRLA bit masks and bit positions */ -#define EDMA_CH_ENABLE_bm 0x80 /* Channel Enable bit mask. */ -#define EDMA_CH_ENABLE_bp 7 /* Channel Enable bit position. */ - -#define EDMA_CH_RESET_bm 0x40 /* Channel Software Reset bit mask. */ -#define EDMA_CH_RESET_bp 6 /* Channel Software Reset bit position. */ - -#define EDMA_CH_REPEAT_bm 0x20 /* Channel Repeat Mode bit mask. */ -#define EDMA_CH_REPEAT_bp 5 /* Channel Repeat Mode bit position. */ - -#define EDMA_CH_TRFREQ_bm 0x10 /* Channel Transfer Request bit mask. */ -#define EDMA_CH_TRFREQ_bp 4 /* Channel Transfer Request bit position. */ - -#define EDMA_CH_SINGLE_bm 0x04 /* Channel Single Shot Data Transfer bit mask. */ -#define EDMA_CH_SINGLE_bp 2 /* Channel Single Shot Data Transfer bit position. */ - -#define EDMA_CH_BURSTLEN_bm 0x01 /* Channel 2-bytes Burst Length bit mask. */ -#define EDMA_CH_BURSTLEN_bp 0 /* Channel 2-bytes Burst Length bit position. */ - -/* EDMA_CH.CTRLB bit masks and bit positions */ -#define EDMA_CH_CHBUSY_bm 0x80 /* Channel Block Transfer Busy bit mask. */ -#define EDMA_CH_CHBUSY_bp 7 /* Channel Block Transfer Busy bit position. */ - -#define EDMA_CH_CHPEND_bm 0x40 /* Channel Block Transfer Pending bit mask. */ -#define EDMA_CH_CHPEND_bp 6 /* Channel Block Transfer Pending bit position. */ - -#define EDMA_CH_ERRIF_bm 0x20 /* Channel Transaction Error Interrupt Flag bit mask. */ -#define EDMA_CH_ERRIF_bp 5 /* Channel Transaction Error Interrupt Flag bit position. */ - -#define EDMA_CH_TRNIF_bm 0x10 /* Channel Transaction Complete Interrup Flag bit mask. */ -#define EDMA_CH_TRNIF_bp 4 /* Channel Transaction Complete Interrup Flag bit position. */ - -#define EDMA_CH_ERRINTLVL_gm 0x0C /* Channel Transaction Error Interrupt Level group mask. */ -#define EDMA_CH_ERRINTLVL_gp 2 /* Channel Transaction Error Interrupt Level group position. */ -#define EDMA_CH_ERRINTLVL0_bm (1<<2) /* Channel Transaction Error Interrupt Level bit 0 mask. */ -#define EDMA_CH_ERRINTLVL0_bp 2 /* Channel Transaction Error Interrupt Level bit 0 position. */ -#define EDMA_CH_ERRINTLVL1_bm (1<<3) /* Channel Transaction Error Interrupt Level bit 1 mask. */ -#define EDMA_CH_ERRINTLVL1_bp 3 /* Channel Transaction Error Interrupt Level bit 1 position. */ - -#define EDMA_CH_TRNINTLVL_gm 0x03 /* Channel Transaction Complete Interrupt Level group mask. */ -#define EDMA_CH_TRNINTLVL_gp 0 /* Channel Transaction Complete Interrupt Level group position. */ -#define EDMA_CH_TRNINTLVL0_bm (1<<0) /* Channel Transaction Complete Interrupt Level bit 0 mask. */ -#define EDMA_CH_TRNINTLVL0_bp 0 /* Channel Transaction Complete Interrupt Level bit 0 position. */ -#define EDMA_CH_TRNINTLVL1_bm (1<<1) /* Channel Transaction Complete Interrupt Level bit 1 mask. */ -#define EDMA_CH_TRNINTLVL1_bp 1 /* Channel Transaction Complete Interrupt Level bit 1 position. */ - -/* EDMA_CH.ADDRCTRL bit masks and bit positions */ -#define EDMA_CH_RELOAD_gm 0x30 /* Memory Address Reload for Peripheral Ch., or Source Address Reload for Standard Ch. group mask. */ -#define EDMA_CH_RELOAD_gp 4 /* Memory Address Reload for Peripheral Ch., or Source Address Reload for Standard Ch. group position. */ -#define EDMA_CH_RELOAD0_bm (1<<4) /* Memory Address Reload for Peripheral Ch., or Source Address Reload for Standard Ch. bit 0 mask. */ -#define EDMA_CH_RELOAD0_bp 4 /* Memory Address Reload for Peripheral Ch., or Source Address Reload for Standard Ch. bit 0 position. */ -#define EDMA_CH_RELOAD1_bm (1<<5) /* Memory Address Reload for Peripheral Ch., or Source Address Reload for Standard Ch. bit 1 mask. */ -#define EDMA_CH_RELOAD1_bp 5 /* Memory Address Reload for Peripheral Ch., or Source Address Reload for Standard Ch. bit 1 position. */ - -#define EDMA_CH_DIR_gm 0x07 /* Memory Address Mode for Peripheral Ch., or Source Address Mode for Standard Ch. group mask. */ -#define EDMA_CH_DIR_gp 0 /* Memory Address Mode for Peripheral Ch., or Source Address Mode for Standard Ch. group position. */ -#define EDMA_CH_DIR0_bm (1<<0) /* Memory Address Mode for Peripheral Ch., or Source Address Mode for Standard Ch. bit 0 mask. */ -#define EDMA_CH_DIR0_bp 0 /* Memory Address Mode for Peripheral Ch., or Source Address Mode for Standard Ch. bit 0 position. */ -#define EDMA_CH_DIR1_bm (1<<1) /* Memory Address Mode for Peripheral Ch., or Source Address Mode for Standard Ch. bit 1 mask. */ -#define EDMA_CH_DIR1_bp 1 /* Memory Address Mode for Peripheral Ch., or Source Address Mode for Standard Ch. bit 1 position. */ -#define EDMA_CH_DIR2_bm (1<<2) /* Memory Address Mode for Peripheral Ch., or Source Address Mode for Standard Ch. bit 2 mask. */ -#define EDMA_CH_DIR2_bp 2 /* Memory Address Mode for Peripheral Ch., or Source Address Mode for Standard Ch. bit 2 position. */ - -/* EDMA_CH.DESTADDRCTRL bit masks and bit positions */ -#define EDMA_CH_DESTRELOAD_gm 0x30 /* Destination Address Reload for Standard Channels Only. group mask. */ -#define EDMA_CH_DESTRELOAD_gp 4 /* Destination Address Reload for Standard Channels Only. group position. */ -#define EDMA_CH_DESTRELOAD0_bm (1<<4) /* Destination Address Reload for Standard Channels Only. bit 0 mask. */ -#define EDMA_CH_DESTRELOAD0_bp 4 /* Destination Address Reload for Standard Channels Only. bit 0 position. */ -#define EDMA_CH_DESTRELOAD1_bm (1<<5) /* Destination Address Reload for Standard Channels Only. bit 1 mask. */ -#define EDMA_CH_DESTRELOAD1_bp 5 /* Destination Address Reload for Standard Channels Only. bit 1 position. */ - -#define EDMA_CH_DESTDIR_gm 0x07 /* Destination Address Mode for Standard Channels Only. group mask. */ -#define EDMA_CH_DESTDIR_gp 0 /* Destination Address Mode for Standard Channels Only. group position. */ -#define EDMA_CH_DESTDIR0_bm (1<<0) /* Destination Address Mode for Standard Channels Only. bit 0 mask. */ -#define EDMA_CH_DESTDIR0_bp 0 /* Destination Address Mode for Standard Channels Only. bit 0 position. */ -#define EDMA_CH_DESTDIR1_bm (1<<1) /* Destination Address Mode for Standard Channels Only. bit 1 mask. */ -#define EDMA_CH_DESTDIR1_bp 1 /* Destination Address Mode for Standard Channels Only. bit 1 position. */ -#define EDMA_CH_DESTDIR2_bm (1<<2) /* Destination Address Mode for Standard Channels Only. bit 2 mask. */ -#define EDMA_CH_DESTDIR2_bp 2 /* Destination Address Mode for Standard Channels Only. bit 2 position. */ - -/* EDMA_CH.TRIGSRC bit masks and bit positions */ -#define EDMA_CH_TRIGSRC_gm 0xFF /* Channel Trigger Source group mask. */ -#define EDMA_CH_TRIGSRC_gp 0 /* Channel Trigger Source group position. */ -#define EDMA_CH_TRIGSRC0_bm (1<<0) /* Channel Trigger Source bit 0 mask. */ -#define EDMA_CH_TRIGSRC0_bp 0 /* Channel Trigger Source bit 0 position. */ -#define EDMA_CH_TRIGSRC1_bm (1<<1) /* Channel Trigger Source bit 1 mask. */ -#define EDMA_CH_TRIGSRC1_bp 1 /* Channel Trigger Source bit 1 position. */ -#define EDMA_CH_TRIGSRC2_bm (1<<2) /* Channel Trigger Source bit 2 mask. */ -#define EDMA_CH_TRIGSRC2_bp 2 /* Channel Trigger Source bit 2 position. */ -#define EDMA_CH_TRIGSRC3_bm (1<<3) /* Channel Trigger Source bit 3 mask. */ -#define EDMA_CH_TRIGSRC3_bp 3 /* Channel Trigger Source bit 3 position. */ -#define EDMA_CH_TRIGSRC4_bm (1<<4) /* Channel Trigger Source bit 4 mask. */ -#define EDMA_CH_TRIGSRC4_bp 4 /* Channel Trigger Source bit 4 position. */ -#define EDMA_CH_TRIGSRC5_bm (1<<5) /* Channel Trigger Source bit 5 mask. */ -#define EDMA_CH_TRIGSRC5_bp 5 /* Channel Trigger Source bit 5 position. */ -#define EDMA_CH_TRIGSRC6_bm (1<<6) /* Channel Trigger Source bit 6 mask. */ -#define EDMA_CH_TRIGSRC6_bp 6 /* Channel Trigger Source bit 6 position. */ -#define EDMA_CH_TRIGSRC7_bm (1<<7) /* Channel Trigger Source bit 7 mask. */ -#define EDMA_CH_TRIGSRC7_bp 7 /* Channel Trigger Source bit 7 position. */ - -/* EVSYS - Event System */ -/* EVSYS.CH0MUX bit masks and bit positions */ -#define EVSYS_CHMUX_gm 0xFF /* Event Channel 0 Multiplexer group mask. */ -#define EVSYS_CHMUX_gp 0 /* Event Channel 0 Multiplexer group position. */ -#define EVSYS_CHMUX0_bm (1<<0) /* Event Channel 0 Multiplexer bit 0 mask. */ -#define EVSYS_CHMUX0_bp 0 /* Event Channel 0 Multiplexer bit 0 position. */ -#define EVSYS_CHMUX1_bm (1<<1) /* Event Channel 0 Multiplexer bit 1 mask. */ -#define EVSYS_CHMUX1_bp 1 /* Event Channel 0 Multiplexer bit 1 position. */ -#define EVSYS_CHMUX2_bm (1<<2) /* Event Channel 0 Multiplexer bit 2 mask. */ -#define EVSYS_CHMUX2_bp 2 /* Event Channel 0 Multiplexer bit 2 position. */ -#define EVSYS_CHMUX3_bm (1<<3) /* Event Channel 0 Multiplexer bit 3 mask. */ -#define EVSYS_CHMUX3_bp 3 /* Event Channel 0 Multiplexer bit 3 position. */ -#define EVSYS_CHMUX4_bm (1<<4) /* Event Channel 0 Multiplexer bit 4 mask. */ -#define EVSYS_CHMUX4_bp 4 /* Event Channel 0 Multiplexer bit 4 position. */ -#define EVSYS_CHMUX5_bm (1<<5) /* Event Channel 0 Multiplexer bit 5 mask. */ -#define EVSYS_CHMUX5_bp 5 /* Event Channel 0 Multiplexer bit 5 position. */ -#define EVSYS_CHMUX6_bm (1<<6) /* Event Channel 0 Multiplexer bit 6 mask. */ -#define EVSYS_CHMUX6_bp 6 /* Event Channel 0 Multiplexer bit 6 position. */ -#define EVSYS_CHMUX7_bm (1<<7) /* Event Channel 0 Multiplexer bit 7 mask. */ -#define EVSYS_CHMUX7_bp 7 /* Event Channel 0 Multiplexer bit 7 position. */ - -/* EVSYS.CH1MUX bit masks and bit positions */ -/* EVSYS_CHMUX Predefined. */ -/* EVSYS_CHMUX Predefined. */ - -/* EVSYS.CH2MUX bit masks and bit positions */ -/* EVSYS_CHMUX Predefined. */ -/* EVSYS_CHMUX Predefined. */ - -/* EVSYS.CH3MUX bit masks and bit positions */ -/* EVSYS_CHMUX Predefined. */ -/* EVSYS_CHMUX Predefined. */ - -/* EVSYS.CH4MUX bit masks and bit positions */ -/* EVSYS_CHMUX Predefined. */ -/* EVSYS_CHMUX Predefined. */ - -/* EVSYS.CH5MUX bit masks and bit positions */ -/* EVSYS_CHMUX Predefined. */ -/* EVSYS_CHMUX Predefined. */ - -/* EVSYS.CH6MUX bit masks and bit positions */ -/* EVSYS_CHMUX Predefined. */ -/* EVSYS_CHMUX Predefined. */ - -/* EVSYS.CH7MUX bit masks and bit positions */ -/* EVSYS_CHMUX Predefined. */ -/* EVSYS_CHMUX Predefined. */ - -/* EVSYS.CH0CTRL bit masks and bit positions */ -#define EVSYS_ROTARY_bm 0x80 /* Rotary Decoder Enable bit mask. */ -#define EVSYS_ROTARY_bp 7 /* Rotary Decoder Enable bit position. */ - -#define EVSYS_QDIRM_gm 0x60 /* Quadrature Decoder Index Recognition Mode group mask. */ -#define EVSYS_QDIRM_gp 5 /* Quadrature Decoder Index Recognition Mode group position. */ -#define EVSYS_QDIRM0_bm (1<<5) /* Quadrature Decoder Index Recognition Mode bit 0 mask. */ -#define EVSYS_QDIRM0_bp 5 /* Quadrature Decoder Index Recognition Mode bit 0 position. */ -#define EVSYS_QDIRM1_bm (1<<6) /* Quadrature Decoder Index Recognition Mode bit 1 mask. */ -#define EVSYS_QDIRM1_bp 6 /* Quadrature Decoder Index Recognition Mode bit 1 position. */ - -#define EVSYS_QDIEN_bm 0x10 /* Quadrature Decoder Index Enable bit mask. */ -#define EVSYS_QDIEN_bp 4 /* Quadrature Decoder Index Enable bit position. */ - -#define EVSYS_QDEN_bm 0x08 /* Quadrature Decoder Enable bit mask. */ -#define EVSYS_QDEN_bp 3 /* Quadrature Decoder Enable bit position. */ - -#define EVSYS_DIGFILT_gm 0x07 /* Digital Filter group mask. */ -#define EVSYS_DIGFILT_gp 0 /* Digital Filter group position. */ -#define EVSYS_DIGFILT0_bm (1<<0) /* Digital Filter bit 0 mask. */ -#define EVSYS_DIGFILT0_bp 0 /* Digital Filter bit 0 position. */ -#define EVSYS_DIGFILT1_bm (1<<1) /* Digital Filter bit 1 mask. */ -#define EVSYS_DIGFILT1_bp 1 /* Digital Filter bit 1 position. */ -#define EVSYS_DIGFILT2_bm (1<<2) /* Digital Filter bit 2 mask. */ -#define EVSYS_DIGFILT2_bp 2 /* Digital Filter bit 2 position. */ - -/* EVSYS.CH1CTRL bit masks and bit positions */ -/* EVSYS_DIGFILT Predefined. */ -/* EVSYS_DIGFILT Predefined. */ - -/* EVSYS.CH2CTRL bit masks and bit positions */ -/* EVSYS_DIGFILT Predefined. */ -/* EVSYS_DIGFILT Predefined. */ - -/* EVSYS.CH3CTRL bit masks and bit positions */ -/* EVSYS_DIGFILT Predefined. */ -/* EVSYS_DIGFILT Predefined. */ - -/* EVSYS.CH4CTRL bit masks and bit positions */ -/* EVSYS_DIGFILT Predefined. */ -/* EVSYS_DIGFILT Predefined. */ - -/* EVSYS.CH5CTRL bit masks and bit positions */ -/* EVSYS_DIGFILT Predefined. */ -/* EVSYS_DIGFILT Predefined. */ - -/* EVSYS.CH6CTRL bit masks and bit positions */ -/* EVSYS_DIGFILT Predefined. */ -/* EVSYS_DIGFILT Predefined. */ - -/* EVSYS.CH7CTRL bit masks and bit positions */ -/* EVSYS_DIGFILT Predefined. */ -/* EVSYS_DIGFILT Predefined. */ - -/* EVSYS.DFCTRL bit masks and bit positions */ -#define EVSYS_PRESCFILT_gm 0xF0 /* Prescaler Filter group mask. */ -#define EVSYS_PRESCFILT_gp 4 /* Prescaler Filter group position. */ -#define EVSYS_PRESCFILT0_bm (1<<4) /* Prescaler Filter bit 0 mask. */ -#define EVSYS_PRESCFILT0_bp 4 /* Prescaler Filter bit 0 position. */ -#define EVSYS_PRESCFILT1_bm (1<<5) /* Prescaler Filter bit 1 mask. */ -#define EVSYS_PRESCFILT1_bp 5 /* Prescaler Filter bit 1 position. */ -#define EVSYS_PRESCFILT2_bm (1<<6) /* Prescaler Filter bit 2 mask. */ -#define EVSYS_PRESCFILT2_bp 6 /* Prescaler Filter bit 2 position. */ -#define EVSYS_PRESCFILT3_bm (1<<7) /* Prescaler Filter bit 3 mask. */ -#define EVSYS_PRESCFILT3_bp 7 /* Prescaler Filter bit 3 position. */ - -#define EVSYS_FILTSEL_bm 0x08 /* Prescaler Filter Select bit mask. */ -#define EVSYS_FILTSEL_bp 3 /* Prescaler Filter Select bit position. */ - -#define EVSYS_PRESC_gm 0x07 /* Prescaler group mask. */ -#define EVSYS_PRESC_gp 0 /* Prescaler group position. */ -#define EVSYS_PRESC0_bm (1<<0) /* Prescaler bit 0 mask. */ -#define EVSYS_PRESC0_bp 0 /* Prescaler bit 0 position. */ -#define EVSYS_PRESC1_bm (1<<1) /* Prescaler bit 1 mask. */ -#define EVSYS_PRESC1_bp 1 /* Prescaler bit 1 position. */ -#define EVSYS_PRESC2_bm (1<<2) /* Prescaler bit 2 mask. */ -#define EVSYS_PRESC2_bp 2 /* Prescaler bit 2 position. */ - -/* NVM - Non Volatile Memory Controller */ -/* NVM.CMD bit masks and bit positions */ -#define NVM_CMD_gm 0x7F /* Command group mask. */ -#define NVM_CMD_gp 0 /* Command group position. */ -#define NVM_CMD0_bm (1<<0) /* Command bit 0 mask. */ -#define NVM_CMD0_bp 0 /* Command bit 0 position. */ -#define NVM_CMD1_bm (1<<1) /* Command bit 1 mask. */ -#define NVM_CMD1_bp 1 /* Command bit 1 position. */ -#define NVM_CMD2_bm (1<<2) /* Command bit 2 mask. */ -#define NVM_CMD2_bp 2 /* Command bit 2 position. */ -#define NVM_CMD3_bm (1<<3) /* Command bit 3 mask. */ -#define NVM_CMD3_bp 3 /* Command bit 3 position. */ -#define NVM_CMD4_bm (1<<4) /* Command bit 4 mask. */ -#define NVM_CMD4_bp 4 /* Command bit 4 position. */ -#define NVM_CMD5_bm (1<<5) /* Command bit 5 mask. */ -#define NVM_CMD5_bp 5 /* Command bit 5 position. */ -#define NVM_CMD6_bm (1<<6) /* Command bit 6 mask. */ -#define NVM_CMD6_bp 6 /* Command bit 6 position. */ - -/* NVM.CTRLA bit masks and bit positions */ -#define NVM_CMDEX_bm 0x01 /* Command Execute bit mask. */ -#define NVM_CMDEX_bp 0 /* Command Execute bit position. */ - -/* NVM.CTRLB bit masks and bit positions */ -#define NVM_EPRM_bm 0x02 /* EEPROM Power Reduction Enable bit mask. */ -#define NVM_EPRM_bp 1 /* EEPROM Power Reduction Enable bit position. */ - -#define NVM_SPMLOCK_bm 0x01 /* SPM Lock bit mask. */ -#define NVM_SPMLOCK_bp 0 /* SPM Lock bit position. */ - -/* NVM.INTCTRL bit masks and bit positions */ -#define NVM_SPMLVL_gm 0x0C /* SPM Interrupt Level group mask. */ -#define NVM_SPMLVL_gp 2 /* SPM Interrupt Level group position. */ -#define NVM_SPMLVL0_bm (1<<2) /* SPM Interrupt Level bit 0 mask. */ -#define NVM_SPMLVL0_bp 2 /* SPM Interrupt Level bit 0 position. */ -#define NVM_SPMLVL1_bm (1<<3) /* SPM Interrupt Level bit 1 mask. */ -#define NVM_SPMLVL1_bp 3 /* SPM Interrupt Level bit 1 position. */ - -#define NVM_EELVL_gm 0x03 /* EEPROM Interrupt Level group mask. */ -#define NVM_EELVL_gp 0 /* EEPROM Interrupt Level group position. */ -#define NVM_EELVL0_bm (1<<0) /* EEPROM Interrupt Level bit 0 mask. */ -#define NVM_EELVL0_bp 0 /* EEPROM Interrupt Level bit 0 position. */ -#define NVM_EELVL1_bm (1<<1) /* EEPROM Interrupt Level bit 1 mask. */ -#define NVM_EELVL1_bp 1 /* EEPROM Interrupt Level bit 1 position. */ - -/* NVM.STATUS bit masks and bit positions */ -#define NVM_NVMBUSY_bm 0x80 /* Non-volatile Memory Busy bit mask. */ -#define NVM_NVMBUSY_bp 7 /* Non-volatile Memory Busy bit position. */ - -#define NVM_FBUSY_bm 0x40 /* Flash Memory Busy bit mask. */ -#define NVM_FBUSY_bp 6 /* Flash Memory Busy bit position. */ - -#define NVM_EELOAD_bm 0x02 /* EEPROM Page Buffer Active Loading bit mask. */ -#define NVM_EELOAD_bp 1 /* EEPROM Page Buffer Active Loading bit position. */ - -#define NVM_FLOAD_bm 0x01 /* Flash Page Buffer Active Loading bit mask. */ -#define NVM_FLOAD_bp 0 /* Flash Page Buffer Active Loading bit position. */ - -/* NVM.LOCKBITS bit masks and bit positions */ -#define NVM_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ -#define NVM_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ -#define NVM_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ -#define NVM_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ -#define NVM_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ -#define NVM_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ - -#define NVM_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ -#define NVM_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ -#define NVM_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ -#define NVM_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ -#define NVM_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ -#define NVM_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ - -#define NVM_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ -#define NVM_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ -#define NVM_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ -#define NVM_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ -#define NVM_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ -#define NVM_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ - -#define NVM_LB_gm 0x03 /* Lock Bits group mask. */ -#define NVM_LB_gp 0 /* Lock Bits group position. */ -#define NVM_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ -#define NVM_LB0_bp 0 /* Lock Bits bit 0 position. */ -#define NVM_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ -#define NVM_LB1_bp 1 /* Lock Bits bit 1 position. */ - -/* ADC - Analog/Digital Converter */ -/* ADC_CH.CTRL bit masks and bit positions */ -#define ADC_CH_START_bm 0x80 /* Channel Start Conversion bit mask. */ -#define ADC_CH_START_bp 7 /* Channel Start Conversion bit position. */ - -#define ADC_CH_GAIN_gm 0x1C /* Gain Factor group mask. */ -#define ADC_CH_GAIN_gp 2 /* Gain Factor group position. */ -#define ADC_CH_GAIN0_bm (1<<2) /* Gain Factor bit 0 mask. */ -#define ADC_CH_GAIN0_bp 2 /* Gain Factor bit 0 position. */ -#define ADC_CH_GAIN1_bm (1<<3) /* Gain Factor bit 1 mask. */ -#define ADC_CH_GAIN1_bp 3 /* Gain Factor bit 1 position. */ -#define ADC_CH_GAIN2_bm (1<<4) /* Gain Factor bit 2 mask. */ -#define ADC_CH_GAIN2_bp 4 /* Gain Factor bit 2 position. */ - -#define ADC_CH_INPUTMODE_gm 0x03 /* Input Mode Select group mask. */ -#define ADC_CH_INPUTMODE_gp 0 /* Input Mode Select group position. */ -#define ADC_CH_INPUTMODE0_bm (1<<0) /* Input Mode Select bit 0 mask. */ -#define ADC_CH_INPUTMODE0_bp 0 /* Input Mode Select bit 0 position. */ -#define ADC_CH_INPUTMODE1_bm (1<<1) /* Input Mode Select bit 1 mask. */ -#define ADC_CH_INPUTMODE1_bp 1 /* Input Mode Select bit 1 position. */ - -/* ADC_CH.MUXCTRL bit masks and bit positions */ -#define ADC_CH_MUXPOS_gm 0x78 /* MUX selection on Positive ADC Input group mask. */ -#define ADC_CH_MUXPOS_gp 3 /* MUX selection on Positive ADC Input group position. */ -#define ADC_CH_MUXPOS0_bm (1<<3) /* MUX selection on Positive ADC Input bit 0 mask. */ -#define ADC_CH_MUXPOS0_bp 3 /* MUX selection on Positive ADC Input bit 0 position. */ -#define ADC_CH_MUXPOS1_bm (1<<4) /* MUX selection on Positive ADC Input bit 1 mask. */ -#define ADC_CH_MUXPOS1_bp 4 /* MUX selection on Positive ADC Input bit 1 position. */ -#define ADC_CH_MUXPOS2_bm (1<<5) /* MUX selection on Positive ADC Input bit 2 mask. */ -#define ADC_CH_MUXPOS2_bp 5 /* MUX selection on Positive ADC Input bit 2 position. */ -#define ADC_CH_MUXPOS3_bm (1<<6) /* MUX selection on Positive ADC Input bit 3 mask. */ -#define ADC_CH_MUXPOS3_bp 6 /* MUX selection on Positive ADC Input bit 3 position. */ - -#define ADC_CH_MUXINT_gm 0x78 /* MUX selection on Internal ADC Input group mask. */ -#define ADC_CH_MUXINT_gp 3 /* MUX selection on Internal ADC Input group position. */ -#define ADC_CH_MUXINT0_bm (1<<3) /* MUX selection on Internal ADC Input bit 0 mask. */ -#define ADC_CH_MUXINT0_bp 3 /* MUX selection on Internal ADC Input bit 0 position. */ -#define ADC_CH_MUXINT1_bm (1<<4) /* MUX selection on Internal ADC Input bit 1 mask. */ -#define ADC_CH_MUXINT1_bp 4 /* MUX selection on Internal ADC Input bit 1 position. */ -#define ADC_CH_MUXINT2_bm (1<<5) /* MUX selection on Internal ADC Input bit 2 mask. */ -#define ADC_CH_MUXINT2_bp 5 /* MUX selection on Internal ADC Input bit 2 position. */ -#define ADC_CH_MUXINT3_bm (1<<6) /* MUX selection on Internal ADC Input bit 3 mask. */ -#define ADC_CH_MUXINT3_bp 6 /* MUX selection on Internal ADC Input bit 3 position. */ - -#define ADC_CH_MUXNEG_gm 0x03 /* MUX selection on Negative ADC Input group mask. */ -#define ADC_CH_MUXNEG_gp 0 /* MUX selection on Negative ADC Input group position. */ -#define ADC_CH_MUXNEG0_bm (1<<0) /* MUX selection on Negative ADC Input bit 0 mask. */ -#define ADC_CH_MUXNEG0_bp 0 /* MUX selection on Negative ADC Input bit 0 position. */ -#define ADC_CH_MUXNEG1_bm (1<<1) /* MUX selection on Negative ADC Input bit 1 mask. */ -#define ADC_CH_MUXNEG1_bp 1 /* MUX selection on Negative ADC Input bit 1 position. */ - -#define ADC_CH_MUXNEGL_gm 0x03 /* MUX selection on Negative ADC Input Gain on 4 LSB pins group mask. */ -#define ADC_CH_MUXNEGL_gp 0 /* MUX selection on Negative ADC Input Gain on 4 LSB pins group position. */ -#define ADC_CH_MUXNEGL0_bm (1<<0) /* MUX selection on Negative ADC Input Gain on 4 LSB pins bit 0 mask. */ -#define ADC_CH_MUXNEGL0_bp 0 /* MUX selection on Negative ADC Input Gain on 4 LSB pins bit 0 position. */ -#define ADC_CH_MUXNEGL1_bm (1<<1) /* MUX selection on Negative ADC Input Gain on 4 LSB pins bit 1 mask. */ -#define ADC_CH_MUXNEGL1_bp 1 /* MUX selection on Negative ADC Input Gain on 4 LSB pins bit 1 position. */ - -#define ADC_CH_MUXNEGH_gm 0x03 /* MUX selection on Negative ADC Input Gain on 4 MSB pins group mask. */ -#define ADC_CH_MUXNEGH_gp 0 /* MUX selection on Negative ADC Input Gain on 4 MSB pins group position. */ -#define ADC_CH_MUXNEGH0_bm (1<<0) /* MUX selection on Negative ADC Input Gain on 4 MSB pins bit 0 mask. */ -#define ADC_CH_MUXNEGH0_bp 0 /* MUX selection on Negative ADC Input Gain on 4 MSB pins bit 0 position. */ -#define ADC_CH_MUXNEGH1_bm (1<<1) /* MUX selection on Negative ADC Input Gain on 4 MSB pins bit 1 mask. */ -#define ADC_CH_MUXNEGH1_bp 1 /* MUX selection on Negative ADC Input Gain on 4 MSB pins bit 1 position. */ - -/* ADC_CH.INTCTRL bit masks and bit positions */ -#define ADC_CH_INTMODE_gm 0x0C /* Interrupt Mode group mask. */ -#define ADC_CH_INTMODE_gp 2 /* Interrupt Mode group position. */ -#define ADC_CH_INTMODE0_bm (1<<2) /* Interrupt Mode bit 0 mask. */ -#define ADC_CH_INTMODE0_bp 2 /* Interrupt Mode bit 0 position. */ -#define ADC_CH_INTMODE1_bm (1<<3) /* Interrupt Mode bit 1 mask. */ -#define ADC_CH_INTMODE1_bp 3 /* Interrupt Mode bit 1 position. */ - -#define ADC_CH_INTLVL_gm 0x03 /* Interrupt Level group mask. */ -#define ADC_CH_INTLVL_gp 0 /* Interrupt Level group position. */ -#define ADC_CH_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */ -#define ADC_CH_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */ -#define ADC_CH_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ -#define ADC_CH_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */ - -/* ADC_CH.INTFLAGS bit masks and bit positions */ -#define ADC_CH_IF_bm 0x01 /* Channel Interrupt Flag bit mask. */ -#define ADC_CH_IF_bp 0 /* Channel Interrupt Flag bit position. */ - -/* ADC_CH.SCAN bit masks and bit positions */ -#define ADC_CH_INPUTOFFSET_gm 0xF0 /* Positive MUX Setting Offset group mask. */ -#define ADC_CH_INPUTOFFSET_gp 4 /* Positive MUX Setting Offset group position. */ -#define ADC_CH_INPUTOFFSET0_bm (1<<4) /* Positive MUX Setting Offset bit 0 mask. */ -#define ADC_CH_INPUTOFFSET0_bp 4 /* Positive MUX Setting Offset bit 0 position. */ -#define ADC_CH_INPUTOFFSET1_bm (1<<5) /* Positive MUX Setting Offset bit 1 mask. */ -#define ADC_CH_INPUTOFFSET1_bp 5 /* Positive MUX Setting Offset bit 1 position. */ -#define ADC_CH_INPUTOFFSET2_bm (1<<6) /* Positive MUX Setting Offset bit 2 mask. */ -#define ADC_CH_INPUTOFFSET2_bp 6 /* Positive MUX Setting Offset bit 2 position. */ -#define ADC_CH_INPUTOFFSET3_bm (1<<7) /* Positive MUX Setting Offset bit 3 mask. */ -#define ADC_CH_INPUTOFFSET3_bp 7 /* Positive MUX Setting Offset bit 3 position. */ - -#define ADC_CH_INPUTSCAN_gm 0x0F /* Number of Channels Included in Scan group mask. */ -#define ADC_CH_INPUTSCAN_gp 0 /* Number of Channels Included in Scan group position. */ -#define ADC_CH_INPUTSCAN0_bm (1<<0) /* Number of Channels Included in Scan bit 0 mask. */ -#define ADC_CH_INPUTSCAN0_bp 0 /* Number of Channels Included in Scan bit 0 position. */ -#define ADC_CH_INPUTSCAN1_bm (1<<1) /* Number of Channels Included in Scan bit 1 mask. */ -#define ADC_CH_INPUTSCAN1_bp 1 /* Number of Channels Included in Scan bit 1 position. */ -#define ADC_CH_INPUTSCAN2_bm (1<<2) /* Number of Channels Included in Scan bit 2 mask. */ -#define ADC_CH_INPUTSCAN2_bp 2 /* Number of Channels Included in Scan bit 2 position. */ -#define ADC_CH_INPUTSCAN3_bm (1<<3) /* Number of Channels Included in Scan bit 3 mask. */ -#define ADC_CH_INPUTSCAN3_bp 3 /* Number of Channels Included in Scan bit 3 position. */ - -/* ADC_CH.CORRCTRL bit masks and bit positions */ -#define ADC_CH_CORREN_bm 0x01 /* Correction Enable bit mask. */ -#define ADC_CH_CORREN_bp 0 /* Correction Enable bit position. */ - -/* ADC_CH.OFFSETCORR1 bit masks and bit positions */ -#define ADC_CH_OFFSETCORR_gm 0x0F /* Offset Correction Byte 1 group mask. */ -#define ADC_CH_OFFSETCORR_gp 0 /* Offset Correction Byte 1 group position. */ -#define ADC_CH_OFFSETCORR0_bm (1<<0) /* Offset Correction Byte 1 bit 0 mask. */ -#define ADC_CH_OFFSETCORR0_bp 0 /* Offset Correction Byte 1 bit 0 position. */ -#define ADC_CH_OFFSETCORR1_bm (1<<1) /* Offset Correction Byte 1 bit 1 mask. */ -#define ADC_CH_OFFSETCORR1_bp 1 /* Offset Correction Byte 1 bit 1 position. */ -#define ADC_CH_OFFSETCORR2_bm (1<<2) /* Offset Correction Byte 1 bit 2 mask. */ -#define ADC_CH_OFFSETCORR2_bp 2 /* Offset Correction Byte 1 bit 2 position. */ -#define ADC_CH_OFFSETCORR3_bm (1<<3) /* Offset Correction Byte 1 bit 3 mask. */ -#define ADC_CH_OFFSETCORR3_bp 3 /* Offset Correction Byte 1 bit 3 position. */ - -/* ADC_CH.GAINCORR1 bit masks and bit positions */ -#define ADC_CH_GAINCORR_gm 0x0F /* Gain Correction Byte 1 group mask. */ -#define ADC_CH_GAINCORR_gp 0 /* Gain Correction Byte 1 group position. */ -#define ADC_CH_GAINCORR0_bm (1<<0) /* Gain Correction Byte 1 bit 0 mask. */ -#define ADC_CH_GAINCORR0_bp 0 /* Gain Correction Byte 1 bit 0 position. */ -#define ADC_CH_GAINCORR1_bm (1<<1) /* Gain Correction Byte 1 bit 1 mask. */ -#define ADC_CH_GAINCORR1_bp 1 /* Gain Correction Byte 1 bit 1 position. */ -#define ADC_CH_GAINCORR2_bm (1<<2) /* Gain Correction Byte 1 bit 2 mask. */ -#define ADC_CH_GAINCORR2_bp 2 /* Gain Correction Byte 1 bit 2 position. */ -#define ADC_CH_GAINCORR3_bm (1<<3) /* Gain Correction Byte 1 bit 3 mask. */ -#define ADC_CH_GAINCORR3_bp 3 /* Gain Correction Byte 1 bit 3 position. */ - -/* ADC_CH.AVGCTRL bit masks and bit positions */ -#define ADC_CH_RIGHTSHIFT_gm 0x70 /* Right Shift group mask. */ -#define ADC_CH_RIGHTSHIFT_gp 4 /* Right Shift group position. */ -#define ADC_CH_RIGHTSHIFT0_bm (1<<4) /* Right Shift bit 0 mask. */ -#define ADC_CH_RIGHTSHIFT0_bp 4 /* Right Shift bit 0 position. */ -#define ADC_CH_RIGHTSHIFT1_bm (1<<5) /* Right Shift bit 1 mask. */ -#define ADC_CH_RIGHTSHIFT1_bp 5 /* Right Shift bit 1 position. */ -#define ADC_CH_RIGHTSHIFT2_bm (1<<6) /* Right Shift bit 2 mask. */ -#define ADC_CH_RIGHTSHIFT2_bp 6 /* Right Shift bit 2 position. */ - -#define ADC_CH_SAMPNUM_gm 0x0F /* Averaged Number of Samples group mask. */ -#define ADC_CH_SAMPNUM_gp 0 /* Averaged Number of Samples group position. */ -#define ADC_CH_SAMPNUM0_bm (1<<0) /* Averaged Number of Samples bit 0 mask. */ -#define ADC_CH_SAMPNUM0_bp 0 /* Averaged Number of Samples bit 0 position. */ -#define ADC_CH_SAMPNUM1_bm (1<<1) /* Averaged Number of Samples bit 1 mask. */ -#define ADC_CH_SAMPNUM1_bp 1 /* Averaged Number of Samples bit 1 position. */ -#define ADC_CH_SAMPNUM2_bm (1<<2) /* Averaged Number of Samples bit 2 mask. */ -#define ADC_CH_SAMPNUM2_bp 2 /* Averaged Number of Samples bit 2 position. */ -#define ADC_CH_SAMPNUM3_bm (1<<3) /* Averaged Number of Samples bit 3 mask. */ -#define ADC_CH_SAMPNUM3_bp 3 /* Averaged Number of Samples bit 3 position. */ - -/* ADC.CTRLA bit masks and bit positions */ -#define ADC_START_bm 0x04 /* Start Conversion bit mask. */ -#define ADC_START_bp 2 /* Start Conversion bit position. */ - -#define ADC_FLUSH_bm 0x02 /* ADC Flush bit mask. */ -#define ADC_FLUSH_bp 1 /* ADC Flush bit position. */ - -#define ADC_ENABLE_bm 0x01 /* Enable ADC bit mask. */ -#define ADC_ENABLE_bp 0 /* Enable ADC bit position. */ - -/* ADC.CTRLB bit masks and bit positions */ -#define ADC_CURRLIMIT_gm 0x60 /* Current Limitation group mask. */ -#define ADC_CURRLIMIT_gp 5 /* Current Limitation group position. */ -#define ADC_CURRLIMIT0_bm (1<<5) /* Current Limitation bit 0 mask. */ -#define ADC_CURRLIMIT0_bp 5 /* Current Limitation bit 0 position. */ -#define ADC_CURRLIMIT1_bm (1<<6) /* Current Limitation bit 1 mask. */ -#define ADC_CURRLIMIT1_bp 6 /* Current Limitation bit 1 position. */ - -#define ADC_CONMODE_bm 0x10 /* Conversion Mode bit mask. */ -#define ADC_CONMODE_bp 4 /* Conversion Mode bit position. */ - -#define ADC_FREERUN_bm 0x08 /* Free Running Mode Enable bit mask. */ -#define ADC_FREERUN_bp 3 /* Free Running Mode Enable bit position. */ - -#define ADC_RESOLUTION_gm 0x06 /* Result Resolution group mask. */ -#define ADC_RESOLUTION_gp 1 /* Result Resolution group position. */ -#define ADC_RESOLUTION0_bm (1<<1) /* Result Resolution bit 0 mask. */ -#define ADC_RESOLUTION0_bp 1 /* Result Resolution bit 0 position. */ -#define ADC_RESOLUTION1_bm (1<<2) /* Result Resolution bit 1 mask. */ -#define ADC_RESOLUTION1_bp 2 /* Result Resolution bit 1 position. */ - -/* ADC.REFCTRL bit masks and bit positions */ -#define ADC_REFSEL_gm 0x70 /* Reference Selection group mask. */ -#define ADC_REFSEL_gp 4 /* Reference Selection group position. */ -#define ADC_REFSEL0_bm (1<<4) /* Reference Selection bit 0 mask. */ -#define ADC_REFSEL0_bp 4 /* Reference Selection bit 0 position. */ -#define ADC_REFSEL1_bm (1<<5) /* Reference Selection bit 1 mask. */ -#define ADC_REFSEL1_bp 5 /* Reference Selection bit 1 position. */ -#define ADC_REFSEL2_bm (1<<6) /* Reference Selection bit 2 mask. */ -#define ADC_REFSEL2_bp 6 /* Reference Selection bit 2 position. */ - -#define ADC_BANDGAP_bm 0x02 /* Bandgap enable bit mask. */ -#define ADC_BANDGAP_bp 1 /* Bandgap enable bit position. */ - -#define ADC_TEMPREF_bm 0x01 /* Temperature Reference Enable bit mask. */ -#define ADC_TEMPREF_bp 0 /* Temperature Reference Enable bit position. */ - -/* ADC.EVCTRL bit masks and bit positions */ -#define ADC_EVSEL_gm 0x38 /* Event Input Select group mask. */ -#define ADC_EVSEL_gp 3 /* Event Input Select group position. */ -#define ADC_EVSEL0_bm (1<<3) /* Event Input Select bit 0 mask. */ -#define ADC_EVSEL0_bp 3 /* Event Input Select bit 0 position. */ -#define ADC_EVSEL1_bm (1<<4) /* Event Input Select bit 1 mask. */ -#define ADC_EVSEL1_bp 4 /* Event Input Select bit 1 position. */ -#define ADC_EVSEL2_bm (1<<5) /* Event Input Select bit 2 mask. */ -#define ADC_EVSEL2_bp 5 /* Event Input Select bit 2 position. */ - -#define ADC_EVACT_gm 0x07 /* Event Action Select group mask. */ -#define ADC_EVACT_gp 0 /* Event Action Select group position. */ -#define ADC_EVACT0_bm (1<<0) /* Event Action Select bit 0 mask. */ -#define ADC_EVACT0_bp 0 /* Event Action Select bit 0 position. */ -#define ADC_EVACT1_bm (1<<1) /* Event Action Select bit 1 mask. */ -#define ADC_EVACT1_bp 1 /* Event Action Select bit 1 position. */ -#define ADC_EVACT2_bm (1<<2) /* Event Action Select bit 2 mask. */ -#define ADC_EVACT2_bp 2 /* Event Action Select bit 2 position. */ - -/* ADC.PRESCALER bit masks and bit positions */ -#define ADC_PRESCALER_gm 0x07 /* Clock Prescaler Selection group mask. */ -#define ADC_PRESCALER_gp 0 /* Clock Prescaler Selection group position. */ -#define ADC_PRESCALER0_bm (1<<0) /* Clock Prescaler Selection bit 0 mask. */ -#define ADC_PRESCALER0_bp 0 /* Clock Prescaler Selection bit 0 position. */ -#define ADC_PRESCALER1_bm (1<<1) /* Clock Prescaler Selection bit 1 mask. */ -#define ADC_PRESCALER1_bp 1 /* Clock Prescaler Selection bit 1 position. */ -#define ADC_PRESCALER2_bm (1<<2) /* Clock Prescaler Selection bit 2 mask. */ -#define ADC_PRESCALER2_bp 2 /* Clock Prescaler Selection bit 2 position. */ - -/* ADC.INTFLAGS bit masks and bit positions */ -#define ADC_CH0IF_bm 0x01 /* Channel 0 Interrupt Flag bit mask. */ -#define ADC_CH0IF_bp 0 /* Channel 0 Interrupt Flag bit position. */ - -/* ADC.SAMPCTRL bit masks and bit positions */ -#define ADC_SAMPVAL_gm 0x3F /* Sampling time control register group mask. */ -#define ADC_SAMPVAL_gp 0 /* Sampling time control register group position. */ -#define ADC_SAMPVAL0_bm (1<<0) /* Sampling time control register bit 0 mask. */ -#define ADC_SAMPVAL0_bp 0 /* Sampling time control register bit 0 position. */ -#define ADC_SAMPVAL1_bm (1<<1) /* Sampling time control register bit 1 mask. */ -#define ADC_SAMPVAL1_bp 1 /* Sampling time control register bit 1 position. */ -#define ADC_SAMPVAL2_bm (1<<2) /* Sampling time control register bit 2 mask. */ -#define ADC_SAMPVAL2_bp 2 /* Sampling time control register bit 2 position. */ -#define ADC_SAMPVAL3_bm (1<<3) /* Sampling time control register bit 3 mask. */ -#define ADC_SAMPVAL3_bp 3 /* Sampling time control register bit 3 position. */ -#define ADC_SAMPVAL4_bm (1<<4) /* Sampling time control register bit 4 mask. */ -#define ADC_SAMPVAL4_bp 4 /* Sampling time control register bit 4 position. */ -#define ADC_SAMPVAL5_bm (1<<5) /* Sampling time control register bit 5 mask. */ -#define ADC_SAMPVAL5_bp 5 /* Sampling time control register bit 5 position. */ - -/* DAC - Digital/Analog Converter */ -/* DAC.CTRLA bit masks and bit positions */ -#define DAC_IDOEN_bm 0x10 /* Internal Output Enable bit mask. */ -#define DAC_IDOEN_bp 4 /* Internal Output Enable bit position. */ - -#define DAC_CH1EN_bm 0x08 /* Channel 1 Output Enable bit mask. */ -#define DAC_CH1EN_bp 3 /* Channel 1 Output Enable bit position. */ - -#define DAC_CH0EN_bm 0x04 /* Channel 0 Output Enable bit mask. */ -#define DAC_CH0EN_bp 2 /* Channel 0 Output Enable bit position. */ - -#define DAC_LPMODE_bm 0x02 /* Low Power Mode bit mask. */ -#define DAC_LPMODE_bp 1 /* Low Power Mode bit position. */ - -#define DAC_ENABLE_bm 0x01 /* Enable bit mask. */ -#define DAC_ENABLE_bp 0 /* Enable bit position. */ - -/* DAC.CTRLB bit masks and bit positions */ -#define DAC_CHSEL_gm 0x60 /* Channel Select group mask. */ -#define DAC_CHSEL_gp 5 /* Channel Select group position. */ -#define DAC_CHSEL0_bm (1<<5) /* Channel Select bit 0 mask. */ -#define DAC_CHSEL0_bp 5 /* Channel Select bit 0 position. */ -#define DAC_CHSEL1_bm (1<<6) /* Channel Select bit 1 mask. */ -#define DAC_CHSEL1_bp 6 /* Channel Select bit 1 position. */ - -#define DAC_CH1TRIG_bm 0x02 /* Channel 1 Event Trig Enable bit mask. */ -#define DAC_CH1TRIG_bp 1 /* Channel 1 Event Trig Enable bit position. */ - -#define DAC_CH0TRIG_bm 0x01 /* Channel 0 Event Trig Enable bit mask. */ -#define DAC_CH0TRIG_bp 0 /* Channel 0 Event Trig Enable bit position. */ - -/* DAC.CTRLC bit masks and bit positions */ -#define DAC_REFSEL_gm 0x18 /* Reference Select group mask. */ -#define DAC_REFSEL_gp 3 /* Reference Select group position. */ -#define DAC_REFSEL0_bm (1<<3) /* Reference Select bit 0 mask. */ -#define DAC_REFSEL0_bp 3 /* Reference Select bit 0 position. */ -#define DAC_REFSEL1_bm (1<<4) /* Reference Select bit 1 mask. */ -#define DAC_REFSEL1_bp 4 /* Reference Select bit 1 position. */ - -#define DAC_LEFTADJ_bm 0x01 /* Left-adjust Result bit mask. */ -#define DAC_LEFTADJ_bp 0 /* Left-adjust Result bit position. */ - -/* DAC.EVCTRL bit masks and bit positions */ -#define DAC_EVSPLIT_bm 0x08 /* Separate Event Channel Input for Channel 1 bit mask. */ -#define DAC_EVSPLIT_bp 3 /* Separate Event Channel Input for Channel 1 bit position. */ - -#define DAC_EVSEL_gm 0x07 /* Event Input Selection group mask. */ -#define DAC_EVSEL_gp 0 /* Event Input Selection group position. */ -#define DAC_EVSEL0_bm (1<<0) /* Event Input Selection bit 0 mask. */ -#define DAC_EVSEL0_bp 0 /* Event Input Selection bit 0 position. */ -#define DAC_EVSEL1_bm (1<<1) /* Event Input Selection bit 1 mask. */ -#define DAC_EVSEL1_bp 1 /* Event Input Selection bit 1 position. */ -#define DAC_EVSEL2_bm (1<<2) /* Event Input Selection bit 2 mask. */ -#define DAC_EVSEL2_bp 2 /* Event Input Selection bit 2 position. */ - -/* DAC.STATUS bit masks and bit positions */ -#define DAC_CH1DRE_bm 0x02 /* Channel 1 Data Register Empty bit mask. */ -#define DAC_CH1DRE_bp 1 /* Channel 1 Data Register Empty bit position. */ - -#define DAC_CH0DRE_bm 0x01 /* Channel 0 Data Register Empty bit mask. */ -#define DAC_CH0DRE_bp 0 /* Channel 0 Data Register Empty bit position. */ - -/* DAC.CH0GAINCAL bit masks and bit positions */ -#define DAC_CH0GAINCAL_gm 0x7F /* Gain Calibration group mask. */ -#define DAC_CH0GAINCAL_gp 0 /* Gain Calibration group position. */ -#define DAC_CH0GAINCAL0_bm (1<<0) /* Gain Calibration bit 0 mask. */ -#define DAC_CH0GAINCAL0_bp 0 /* Gain Calibration bit 0 position. */ -#define DAC_CH0GAINCAL1_bm (1<<1) /* Gain Calibration bit 1 mask. */ -#define DAC_CH0GAINCAL1_bp 1 /* Gain Calibration bit 1 position. */ -#define DAC_CH0GAINCAL2_bm (1<<2) /* Gain Calibration bit 2 mask. */ -#define DAC_CH0GAINCAL2_bp 2 /* Gain Calibration bit 2 position. */ -#define DAC_CH0GAINCAL3_bm (1<<3) /* Gain Calibration bit 3 mask. */ -#define DAC_CH0GAINCAL3_bp 3 /* Gain Calibration bit 3 position. */ -#define DAC_CH0GAINCAL4_bm (1<<4) /* Gain Calibration bit 4 mask. */ -#define DAC_CH0GAINCAL4_bp 4 /* Gain Calibration bit 4 position. */ -#define DAC_CH0GAINCAL5_bm (1<<5) /* Gain Calibration bit 5 mask. */ -#define DAC_CH0GAINCAL5_bp 5 /* Gain Calibration bit 5 position. */ -#define DAC_CH0GAINCAL6_bm (1<<6) /* Gain Calibration bit 6 mask. */ -#define DAC_CH0GAINCAL6_bp 6 /* Gain Calibration bit 6 position. */ - -/* DAC.CH0OFFSETCAL bit masks and bit positions */ -#define DAC_CH0OFFSETCAL_gm 0x7F /* Offset Calibration group mask. */ -#define DAC_CH0OFFSETCAL_gp 0 /* Offset Calibration group position. */ -#define DAC_CH0OFFSETCAL0_bm (1<<0) /* Offset Calibration bit 0 mask. */ -#define DAC_CH0OFFSETCAL0_bp 0 /* Offset Calibration bit 0 position. */ -#define DAC_CH0OFFSETCAL1_bm (1<<1) /* Offset Calibration bit 1 mask. */ -#define DAC_CH0OFFSETCAL1_bp 1 /* Offset Calibration bit 1 position. */ -#define DAC_CH0OFFSETCAL2_bm (1<<2) /* Offset Calibration bit 2 mask. */ -#define DAC_CH0OFFSETCAL2_bp 2 /* Offset Calibration bit 2 position. */ -#define DAC_CH0OFFSETCAL3_bm (1<<3) /* Offset Calibration bit 3 mask. */ -#define DAC_CH0OFFSETCAL3_bp 3 /* Offset Calibration bit 3 position. */ -#define DAC_CH0OFFSETCAL4_bm (1<<4) /* Offset Calibration bit 4 mask. */ -#define DAC_CH0OFFSETCAL4_bp 4 /* Offset Calibration bit 4 position. */ -#define DAC_CH0OFFSETCAL5_bm (1<<5) /* Offset Calibration bit 5 mask. */ -#define DAC_CH0OFFSETCAL5_bp 5 /* Offset Calibration bit 5 position. */ -#define DAC_CH0OFFSETCAL6_bm (1<<6) /* Offset Calibration bit 6 mask. */ -#define DAC_CH0OFFSETCAL6_bp 6 /* Offset Calibration bit 6 position. */ - -/* DAC.CH1GAINCAL bit masks and bit positions */ -#define DAC_CH1GAINCAL_gm 0x7F /* Gain Calibration group mask. */ -#define DAC_CH1GAINCAL_gp 0 /* Gain Calibration group position. */ -#define DAC_CH1GAINCAL0_bm (1<<0) /* Gain Calibration bit 0 mask. */ -#define DAC_CH1GAINCAL0_bp 0 /* Gain Calibration bit 0 position. */ -#define DAC_CH1GAINCAL1_bm (1<<1) /* Gain Calibration bit 1 mask. */ -#define DAC_CH1GAINCAL1_bp 1 /* Gain Calibration bit 1 position. */ -#define DAC_CH1GAINCAL2_bm (1<<2) /* Gain Calibration bit 2 mask. */ -#define DAC_CH1GAINCAL2_bp 2 /* Gain Calibration bit 2 position. */ -#define DAC_CH1GAINCAL3_bm (1<<3) /* Gain Calibration bit 3 mask. */ -#define DAC_CH1GAINCAL3_bp 3 /* Gain Calibration bit 3 position. */ -#define DAC_CH1GAINCAL4_bm (1<<4) /* Gain Calibration bit 4 mask. */ -#define DAC_CH1GAINCAL4_bp 4 /* Gain Calibration bit 4 position. */ -#define DAC_CH1GAINCAL5_bm (1<<5) /* Gain Calibration bit 5 mask. */ -#define DAC_CH1GAINCAL5_bp 5 /* Gain Calibration bit 5 position. */ -#define DAC_CH1GAINCAL6_bm (1<<6) /* Gain Calibration bit 6 mask. */ -#define DAC_CH1GAINCAL6_bp 6 /* Gain Calibration bit 6 position. */ - -/* DAC.CH1OFFSETCAL bit masks and bit positions */ -#define DAC_CH1OFFSETCAL_gm 0x7F /* Offset Calibration group mask. */ -#define DAC_CH1OFFSETCAL_gp 0 /* Offset Calibration group position. */ -#define DAC_CH1OFFSETCAL0_bm (1<<0) /* Offset Calibration bit 0 mask. */ -#define DAC_CH1OFFSETCAL0_bp 0 /* Offset Calibration bit 0 position. */ -#define DAC_CH1OFFSETCAL1_bm (1<<1) /* Offset Calibration bit 1 mask. */ -#define DAC_CH1OFFSETCAL1_bp 1 /* Offset Calibration bit 1 position. */ -#define DAC_CH1OFFSETCAL2_bm (1<<2) /* Offset Calibration bit 2 mask. */ -#define DAC_CH1OFFSETCAL2_bp 2 /* Offset Calibration bit 2 position. */ -#define DAC_CH1OFFSETCAL3_bm (1<<3) /* Offset Calibration bit 3 mask. */ -#define DAC_CH1OFFSETCAL3_bp 3 /* Offset Calibration bit 3 position. */ -#define DAC_CH1OFFSETCAL4_bm (1<<4) /* Offset Calibration bit 4 mask. */ -#define DAC_CH1OFFSETCAL4_bp 4 /* Offset Calibration bit 4 position. */ -#define DAC_CH1OFFSETCAL5_bm (1<<5) /* Offset Calibration bit 5 mask. */ -#define DAC_CH1OFFSETCAL5_bp 5 /* Offset Calibration bit 5 position. */ -#define DAC_CH1OFFSETCAL6_bm (1<<6) /* Offset Calibration bit 6 mask. */ -#define DAC_CH1OFFSETCAL6_bp 6 /* Offset Calibration bit 6 position. */ - -/* AC - Analog Comparator */ -/* AC.AC0CTRL bit masks and bit positions */ -#define AC_INTMODE_gm 0xC0 /* Interrupt Mode group mask. */ -#define AC_INTMODE_gp 6 /* Interrupt Mode group position. */ -#define AC_INTMODE0_bm (1<<6) /* Interrupt Mode bit 0 mask. */ -#define AC_INTMODE0_bp 6 /* Interrupt Mode bit 0 position. */ -#define AC_INTMODE1_bm (1<<7) /* Interrupt Mode bit 1 mask. */ -#define AC_INTMODE1_bp 7 /* Interrupt Mode bit 1 position. */ - -#define AC_INTLVL_gm 0x30 /* Interrupt Level group mask. */ -#define AC_INTLVL_gp 4 /* Interrupt Level group position. */ -#define AC_INTLVL0_bm (1<<4) /* Interrupt Level bit 0 mask. */ -#define AC_INTLVL0_bp 4 /* Interrupt Level bit 0 position. */ -#define AC_INTLVL1_bm (1<<5) /* Interrupt Level bit 1 mask. */ -#define AC_INTLVL1_bp 5 /* Interrupt Level bit 1 position. */ - -#define AC_HYSMODE_gm 0x06 /* Hysteresis Mode group mask. */ -#define AC_HYSMODE_gp 1 /* Hysteresis Mode group position. */ -#define AC_HYSMODE0_bm (1<<1) /* Hysteresis Mode bit 0 mask. */ -#define AC_HYSMODE0_bp 1 /* Hysteresis Mode bit 0 position. */ -#define AC_HYSMODE1_bm (1<<2) /* Hysteresis Mode bit 1 mask. */ -#define AC_HYSMODE1_bp 2 /* Hysteresis Mode bit 1 position. */ - -#define AC_ENABLE_bm 0x01 /* Enable bit mask. */ -#define AC_ENABLE_bp 0 /* Enable bit position. */ - -/* AC.AC1CTRL bit masks and bit positions */ -/* AC_INTMODE Predefined. */ -/* AC_INTMODE Predefined. */ - -/* AC_INTLVL Predefined. */ -/* AC_INTLVL Predefined. */ - -/* AC_HYSMODE Predefined. */ -/* AC_HYSMODE Predefined. */ - -/* AC_ENABLE Predefined. */ -/* AC_ENABLE Predefined. */ - -/* AC.AC0MUXCTRL bit masks and bit positions */ -#define AC_MUXPOS_gm 0x38 /* MUX Positive Input group mask. */ -#define AC_MUXPOS_gp 3 /* MUX Positive Input group position. */ -#define AC_MUXPOS0_bm (1<<3) /* MUX Positive Input bit 0 mask. */ -#define AC_MUXPOS0_bp 3 /* MUX Positive Input bit 0 position. */ -#define AC_MUXPOS1_bm (1<<4) /* MUX Positive Input bit 1 mask. */ -#define AC_MUXPOS1_bp 4 /* MUX Positive Input bit 1 position. */ -#define AC_MUXPOS2_bm (1<<5) /* MUX Positive Input bit 2 mask. */ -#define AC_MUXPOS2_bp 5 /* MUX Positive Input bit 2 position. */ - -#define AC_MUXNEG_gm 0x07 /* MUX Negative Input group mask. */ -#define AC_MUXNEG_gp 0 /* MUX Negative Input group position. */ -#define AC_MUXNEG0_bm (1<<0) /* MUX Negative Input bit 0 mask. */ -#define AC_MUXNEG0_bp 0 /* MUX Negative Input bit 0 position. */ -#define AC_MUXNEG1_bm (1<<1) /* MUX Negative Input bit 1 mask. */ -#define AC_MUXNEG1_bp 1 /* MUX Negative Input bit 1 position. */ -#define AC_MUXNEG2_bm (1<<2) /* MUX Negative Input bit 2 mask. */ -#define AC_MUXNEG2_bp 2 /* MUX Negative Input bit 2 position. */ - -/* AC.AC1MUXCTRL bit masks and bit positions */ -/* AC_MUXPOS Predefined. */ -/* AC_MUXPOS Predefined. */ - -/* AC_MUXNEG Predefined. */ -/* AC_MUXNEG Predefined. */ - -/* AC.CTRLA bit masks and bit positions */ -#define AC_AC1INVEN_bm 0x08 /* Analog Comparator 1 Output Invert Enable bit mask. */ -#define AC_AC1INVEN_bp 3 /* Analog Comparator 1 Output Invert Enable bit position. */ - -#define AC_AC0INVEN_bm 0x04 /* Analog Comparator 0 Output Invert Enable bit mask. */ -#define AC_AC0INVEN_bp 2 /* Analog Comparator 0 Output Invert Enable bit position. */ - -#define AC_AC1OUT_bm 0x02 /* Analog Comparator 1 Output Enable bit mask. */ -#define AC_AC1OUT_bp 1 /* Analog Comparator 1 Output Enable bit position. */ - -#define AC_AC0OUT_bm 0x01 /* Analog Comparator 0 Output Enable bit mask. */ -#define AC_AC0OUT_bp 0 /* Analog Comparator 0 Output Enable bit position. */ - -/* AC.CTRLB bit masks and bit positions */ -#define AC_SCALEFAC_gm 0x3F /* VCC Voltage Scaler Factor group mask. */ -#define AC_SCALEFAC_gp 0 /* VCC Voltage Scaler Factor group position. */ -#define AC_SCALEFAC0_bm (1<<0) /* VCC Voltage Scaler Factor bit 0 mask. */ -#define AC_SCALEFAC0_bp 0 /* VCC Voltage Scaler Factor bit 0 position. */ -#define AC_SCALEFAC1_bm (1<<1) /* VCC Voltage Scaler Factor bit 1 mask. */ -#define AC_SCALEFAC1_bp 1 /* VCC Voltage Scaler Factor bit 1 position. */ -#define AC_SCALEFAC2_bm (1<<2) /* VCC Voltage Scaler Factor bit 2 mask. */ -#define AC_SCALEFAC2_bp 2 /* VCC Voltage Scaler Factor bit 2 position. */ -#define AC_SCALEFAC3_bm (1<<3) /* VCC Voltage Scaler Factor bit 3 mask. */ -#define AC_SCALEFAC3_bp 3 /* VCC Voltage Scaler Factor bit 3 position. */ -#define AC_SCALEFAC4_bm (1<<4) /* VCC Voltage Scaler Factor bit 4 mask. */ -#define AC_SCALEFAC4_bp 4 /* VCC Voltage Scaler Factor bit 4 position. */ -#define AC_SCALEFAC5_bm (1<<5) /* VCC Voltage Scaler Factor bit 5 mask. */ -#define AC_SCALEFAC5_bp 5 /* VCC Voltage Scaler Factor bit 5 position. */ - -/* AC.WINCTRL bit masks and bit positions */ -#define AC_WEN_bm 0x10 /* Window Mode Enable bit mask. */ -#define AC_WEN_bp 4 /* Window Mode Enable bit position. */ - -#define AC_WINTMODE_gm 0x0C /* Window Interrupt Mode group mask. */ -#define AC_WINTMODE_gp 2 /* Window Interrupt Mode group position. */ -#define AC_WINTMODE0_bm (1<<2) /* Window Interrupt Mode bit 0 mask. */ -#define AC_WINTMODE0_bp 2 /* Window Interrupt Mode bit 0 position. */ -#define AC_WINTMODE1_bm (1<<3) /* Window Interrupt Mode bit 1 mask. */ -#define AC_WINTMODE1_bp 3 /* Window Interrupt Mode bit 1 position. */ - -#define AC_WINTLVL_gm 0x03 /* Window Interrupt Level group mask. */ -#define AC_WINTLVL_gp 0 /* Window Interrupt Level group position. */ -#define AC_WINTLVL0_bm (1<<0) /* Window Interrupt Level bit 0 mask. */ -#define AC_WINTLVL0_bp 0 /* Window Interrupt Level bit 0 position. */ -#define AC_WINTLVL1_bm (1<<1) /* Window Interrupt Level bit 1 mask. */ -#define AC_WINTLVL1_bp 1 /* Window Interrupt Level bit 1 position. */ - -/* AC.STATUS bit masks and bit positions */ -#define AC_WSTATE_gm 0xC0 /* Window Mode State group mask. */ -#define AC_WSTATE_gp 6 /* Window Mode State group position. */ -#define AC_WSTATE0_bm (1<<6) /* Window Mode State bit 0 mask. */ -#define AC_WSTATE0_bp 6 /* Window Mode State bit 0 position. */ -#define AC_WSTATE1_bm (1<<7) /* Window Mode State bit 1 mask. */ -#define AC_WSTATE1_bp 7 /* Window Mode State bit 1 position. */ - -#define AC_AC1STATE_bm 0x20 /* Analog Comparator 1 State bit mask. */ -#define AC_AC1STATE_bp 5 /* Analog Comparator 1 State bit position. */ - -#define AC_AC0STATE_bm 0x10 /* Analog Comparator 0 State bit mask. */ -#define AC_AC0STATE_bp 4 /* Analog Comparator 0 State bit position. */ - -#define AC_WIF_bm 0x04 /* Window Mode Interrupt Flag bit mask. */ -#define AC_WIF_bp 2 /* Window Mode Interrupt Flag bit position. */ - -#define AC_AC1IF_bm 0x02 /* Analog Comparator 1 Interrupt Flag bit mask. */ -#define AC_AC1IF_bp 1 /* Analog Comparator 1 Interrupt Flag bit position. */ - -#define AC_AC0IF_bm 0x01 /* Analog Comparator 0 Interrupt Flag bit mask. */ -#define AC_AC0IF_bp 0 /* Analog Comparator 0 Interrupt Flag bit position. */ - -/* AC.CURRCTRL bit masks and bit positions */ -#define AC_CURREN_bm 0x80 /* Current Source Enable bit mask. */ -#define AC_CURREN_bp 7 /* Current Source Enable bit position. */ - -#define AC_CURRMODE_bm 0x40 /* Current Mode bit mask. */ -#define AC_CURRMODE_bp 6 /* Current Mode bit position. */ - -#define AC_AC1CURR_bm 0x02 /* Analog Comparator 1 current source output bit mask. */ -#define AC_AC1CURR_bp 1 /* Analog Comparator 1 current source output bit position. */ - -#define AC_AC0CURR_bm 0x01 /* Analog Comparator 0 current source output bit mask. */ -#define AC_AC0CURR_bp 0 /* Analog Comparator 0 current source output bit position. */ - -/* AC.CURRCALIB bit masks and bit positions */ -#define AC_CALIB_gm 0x0F /* Current Source Calibration group mask. */ -#define AC_CALIB_gp 0 /* Current Source Calibration group position. */ -#define AC_CALIB0_bm (1<<0) /* Current Source Calibration bit 0 mask. */ -#define AC_CALIB0_bp 0 /* Current Source Calibration bit 0 position. */ -#define AC_CALIB1_bm (1<<1) /* Current Source Calibration bit 1 mask. */ -#define AC_CALIB1_bp 1 /* Current Source Calibration bit 1 position. */ -#define AC_CALIB2_bm (1<<2) /* Current Source Calibration bit 2 mask. */ -#define AC_CALIB2_bp 2 /* Current Source Calibration bit 2 position. */ -#define AC_CALIB3_bm (1<<3) /* Current Source Calibration bit 3 mask. */ -#define AC_CALIB3_bp 3 /* Current Source Calibration bit 3 position. */ - -/* RTC - Real-Time Clounter */ -/* RTC.CTRL bit masks and bit positions */ -#define RTC_CORREN_bm 0x08 /* Correction Enable bit mask. */ -#define RTC_CORREN_bp 3 /* Correction Enable bit position. */ - -#define RTC_PRESCALER_gm 0x07 /* Prescaling Factor group mask. */ -#define RTC_PRESCALER_gp 0 /* Prescaling Factor group position. */ -#define RTC_PRESCALER0_bm (1<<0) /* Prescaling Factor bit 0 mask. */ -#define RTC_PRESCALER0_bp 0 /* Prescaling Factor bit 0 position. */ -#define RTC_PRESCALER1_bm (1<<1) /* Prescaling Factor bit 1 mask. */ -#define RTC_PRESCALER1_bp 1 /* Prescaling Factor bit 1 position. */ -#define RTC_PRESCALER2_bm (1<<2) /* Prescaling Factor bit 2 mask. */ -#define RTC_PRESCALER2_bp 2 /* Prescaling Factor bit 2 position. */ - -/* RTC.STATUS bit masks and bit positions */ -#define RTC_SYNCBUSY_bm 0x01 /* Synchronization Busy Flag bit mask. */ -#define RTC_SYNCBUSY_bp 0 /* Synchronization Busy Flag bit position. */ - -/* RTC.INTCTRL bit masks and bit positions */ -#define RTC_COMPINTLVL_gm 0x0C /* Compare Match Interrupt Level group mask. */ -#define RTC_COMPINTLVL_gp 2 /* Compare Match Interrupt Level group position. */ -#define RTC_COMPINTLVL0_bm (1<<2) /* Compare Match Interrupt Level bit 0 mask. */ -#define RTC_COMPINTLVL0_bp 2 /* Compare Match Interrupt Level bit 0 position. */ -#define RTC_COMPINTLVL1_bm (1<<3) /* Compare Match Interrupt Level bit 1 mask. */ -#define RTC_COMPINTLVL1_bp 3 /* Compare Match Interrupt Level bit 1 position. */ - -#define RTC_OVFINTLVL_gm 0x03 /* Overflow Interrupt Level group mask. */ -#define RTC_OVFINTLVL_gp 0 /* Overflow Interrupt Level group position. */ -#define RTC_OVFINTLVL0_bm (1<<0) /* Overflow Interrupt Level bit 0 mask. */ -#define RTC_OVFINTLVL0_bp 0 /* Overflow Interrupt Level bit 0 position. */ -#define RTC_OVFINTLVL1_bm (1<<1) /* Overflow Interrupt Level bit 1 mask. */ -#define RTC_OVFINTLVL1_bp 1 /* Overflow Interrupt Level bit 1 position. */ - -/* RTC.INTFLAGS bit masks and bit positions */ -#define RTC_COMPIF_bm 0x02 /* Compare Match Interrupt Flag bit mask. */ -#define RTC_COMPIF_bp 1 /* Compare Match Interrupt Flag bit position. */ - -#define RTC_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ -#define RTC_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ - -/* RTC.CALIB bit masks and bit positions */ -#define RTC_SIGN_bm 0x80 /* Correction Sign bit mask. */ -#define RTC_SIGN_bp 7 /* Correction Sign bit position. */ - -#define RTC_ERROR_gm 0x7F /* Error Value group mask. */ -#define RTC_ERROR_gp 0 /* Error Value group position. */ -#define RTC_ERROR0_bm (1<<0) /* Error Value bit 0 mask. */ -#define RTC_ERROR0_bp 0 /* Error Value bit 0 position. */ -#define RTC_ERROR1_bm (1<<1) /* Error Value bit 1 mask. */ -#define RTC_ERROR1_bp 1 /* Error Value bit 1 position. */ -#define RTC_ERROR2_bm (1<<2) /* Error Value bit 2 mask. */ -#define RTC_ERROR2_bp 2 /* Error Value bit 2 position. */ -#define RTC_ERROR3_bm (1<<3) /* Error Value bit 3 mask. */ -#define RTC_ERROR3_bp 3 /* Error Value bit 3 position. */ -#define RTC_ERROR4_bm (1<<4) /* Error Value bit 4 mask. */ -#define RTC_ERROR4_bp 4 /* Error Value bit 4 position. */ -#define RTC_ERROR5_bm (1<<5) /* Error Value bit 5 mask. */ -#define RTC_ERROR5_bp 5 /* Error Value bit 5 position. */ -#define RTC_ERROR6_bm (1<<6) /* Error Value bit 6 mask. */ -#define RTC_ERROR6_bp 6 /* Error Value bit 6 position. */ - -/* XCL - XMEGA Custom Logic */ -/* XCL.CTRLA bit masks and bit positions */ -#define XCL_LUT0OUTEN_gm 0xC0 /* LUT0 Output Enable group mask. */ -#define XCL_LUT0OUTEN_gp 6 /* LUT0 Output Enable group position. */ -#define XCL_LUT0OUTEN0_bm (1<<6) /* LUT0 Output Enable bit 0 mask. */ -#define XCL_LUT0OUTEN0_bp 6 /* LUT0 Output Enable bit 0 position. */ -#define XCL_LUT0OUTEN1_bm (1<<7) /* LUT0 Output Enable bit 1 mask. */ -#define XCL_LUT0OUTEN1_bp 7 /* LUT0 Output Enable bit 1 position. */ - -#define XCL_PORTSEL_gm 0x30 /* Port Selection group mask. */ -#define XCL_PORTSEL_gp 4 /* Port Selection group position. */ -#define XCL_PORTSEL0_bm (1<<4) /* Port Selection bit 0 mask. */ -#define XCL_PORTSEL0_bp 4 /* Port Selection bit 0 position. */ -#define XCL_PORTSEL1_bm (1<<5) /* Port Selection bit 1 mask. */ -#define XCL_PORTSEL1_bp 5 /* Port Selection bit 1 position. */ - -#define XCL_LUTCONF_gm 0x07 /* LUT Configuration group mask. */ -#define XCL_LUTCONF_gp 0 /* LUT Configuration group position. */ -#define XCL_LUTCONF0_bm (1<<0) /* LUT Configuration bit 0 mask. */ -#define XCL_LUTCONF0_bp 0 /* LUT Configuration bit 0 position. */ -#define XCL_LUTCONF1_bm (1<<1) /* LUT Configuration bit 1 mask. */ -#define XCL_LUTCONF1_bp 1 /* LUT Configuration bit 1 position. */ -#define XCL_LUTCONF2_bm (1<<2) /* LUT Configuration bit 2 mask. */ -#define XCL_LUTCONF2_bp 2 /* LUT Configuration bit 2 position. */ - -/* XCL.CTRLB bit masks and bit positions */ -#define XCL_IN3SEL_gm 0xC0 /* Input Selection 3 group mask. */ -#define XCL_IN3SEL_gp 6 /* Input Selection 3 group position. */ -#define XCL_IN3SEL0_bm (1<<6) /* Input Selection 3 bit 0 mask. */ -#define XCL_IN3SEL0_bp 6 /* Input Selection 3 bit 0 position. */ -#define XCL_IN3SEL1_bm (1<<7) /* Input Selection 3 bit 1 mask. */ -#define XCL_IN3SEL1_bp 7 /* Input Selection 3 bit 1 position. */ - -#define XCL_IN2SEL_gm 0x30 /* Input Selection 2 group mask. */ -#define XCL_IN2SEL_gp 4 /* Input Selection 2 group position. */ -#define XCL_IN2SEL0_bm (1<<4) /* Input Selection 2 bit 0 mask. */ -#define XCL_IN2SEL0_bp 4 /* Input Selection 2 bit 0 position. */ -#define XCL_IN2SEL1_bm (1<<5) /* Input Selection 2 bit 1 mask. */ -#define XCL_IN2SEL1_bp 5 /* Input Selection 2 bit 1 position. */ - -#define XCL_IN1SEL_gm 0x0C /* Input Selection 1 group mask. */ -#define XCL_IN1SEL_gp 2 /* Input Selection 1 group position. */ -#define XCL_IN1SEL0_bm (1<<2) /* Input Selection 1 bit 0 mask. */ -#define XCL_IN1SEL0_bp 2 /* Input Selection 1 bit 0 position. */ -#define XCL_IN1SEL1_bm (1<<3) /* Input Selection 1 bit 1 mask. */ -#define XCL_IN1SEL1_bp 3 /* Input Selection 1 bit 1 position. */ - -#define XCL_IN0SEL_gm 0x03 /* Input Selection 0 group mask. */ -#define XCL_IN0SEL_gp 0 /* Input Selection 0 group position. */ -#define XCL_IN0SEL0_bm (1<<0) /* Input Selection 0 bit 0 mask. */ -#define XCL_IN0SEL0_bp 0 /* Input Selection 0 bit 0 position. */ -#define XCL_IN0SEL1_bm (1<<1) /* Input Selection 0 bit 1 mask. */ -#define XCL_IN0SEL1_bp 1 /* Input Selection 0 bit 1 position. */ - -/* XCL.CTRLC bit masks and bit positions */ -#define XCL_EVASYSEL1_bm 0x80 /* Asynchronous Event Line Selection for LUT1 bit mask. */ -#define XCL_EVASYSEL1_bp 7 /* Asynchronous Event Line Selection for LUT1 bit position. */ - -#define XCL_EVASYSEL0_bm 0x40 /* Asynchronous Event Line Selection for LUT0 bit mask. */ -#define XCL_EVASYSEL0_bp 6 /* Asynchronous Event Line Selection for LUT0 bit position. */ - -#define XCL_DLYSEL_gm 0x30 /* Delay Selection group mask. */ -#define XCL_DLYSEL_gp 4 /* Delay Selection group position. */ -#define XCL_DLYSEL0_bm (1<<4) /* Delay Selection bit 0 mask. */ -#define XCL_DLYSEL0_bp 4 /* Delay Selection bit 0 position. */ -#define XCL_DLYSEL1_bm (1<<5) /* Delay Selection bit 1 mask. */ -#define XCL_DLYSEL1_bp 5 /* Delay Selection bit 1 position. */ - -#define XCL_DLY1CONF_gm 0x0C /* Delay Configuration on LUT1 group mask. */ -#define XCL_DLY1CONF_gp 2 /* Delay Configuration on LUT1 group position. */ -#define XCL_DLY1CONF0_bm (1<<2) /* Delay Configuration on LUT1 bit 0 mask. */ -#define XCL_DLY1CONF0_bp 2 /* Delay Configuration on LUT1 bit 0 position. */ -#define XCL_DLY1CONF1_bm (1<<3) /* Delay Configuration on LUT1 bit 1 mask. */ -#define XCL_DLY1CONF1_bp 3 /* Delay Configuration on LUT1 bit 1 position. */ - -#define XCL_DLY0CONF_gm 0x03 /* Delay Configuration on LUT0 group mask. */ -#define XCL_DLY0CONF_gp 0 /* Delay Configuration on LUT0 group position. */ -#define XCL_DLY0CONF0_bm (1<<0) /* Delay Configuration on LUT0 bit 0 mask. */ -#define XCL_DLY0CONF0_bp 0 /* Delay Configuration on LUT0 bit 0 position. */ -#define XCL_DLY0CONF1_bm (1<<1) /* Delay Configuration on LUT0 bit 1 mask. */ -#define XCL_DLY0CONF1_bp 1 /* Delay Configuration on LUT0 bit 1 position. */ - -/* XCL.CTRLD bit masks and bit positions */ -#define XCL_TRUTH1_gm 0xF0 /* Truth Table of LUT1 group mask. */ -#define XCL_TRUTH1_gp 4 /* Truth Table of LUT1 group position. */ -#define XCL_TRUTH10_bm (1<<4) /* Truth Table of LUT1 bit 0 mask. */ -#define XCL_TRUTH10_bp 4 /* Truth Table of LUT1 bit 0 position. */ -#define XCL_TRUTH11_bm (1<<5) /* Truth Table of LUT1 bit 1 mask. */ -#define XCL_TRUTH11_bp 5 /* Truth Table of LUT1 bit 1 position. */ -#define XCL_TRUTH12_bm (1<<6) /* Truth Table of LUT1 bit 2 mask. */ -#define XCL_TRUTH12_bp 6 /* Truth Table of LUT1 bit 2 position. */ -#define XCL_TRUTH13_bm (1<<7) /* Truth Table of LUT1 bit 3 mask. */ -#define XCL_TRUTH13_bp 7 /* Truth Table of LUT1 bit 3 position. */ - -#define XCL_TRUTH0_gm 0x0F /* Truth Table of LUT0 group mask. */ -#define XCL_TRUTH0_gp 0 /* Truth Table of LUT0 group position. */ -#define XCL_TRUTH00_bm (1<<0) /* Truth Table of LUT0 bit 0 mask. */ -#define XCL_TRUTH00_bp 0 /* Truth Table of LUT0 bit 0 position. */ -#define XCL_TRUTH01_bm (1<<1) /* Truth Table of LUT0 bit 1 mask. */ -#define XCL_TRUTH01_bp 1 /* Truth Table of LUT0 bit 1 position. */ -#define XCL_TRUTH02_bm (1<<2) /* Truth Table of LUT0 bit 2 mask. */ -#define XCL_TRUTH02_bp 2 /* Truth Table of LUT0 bit 2 position. */ -#define XCL_TRUTH03_bm (1<<3) /* Truth Table of LUT0 bit 3 mask. */ -#define XCL_TRUTH03_bp 3 /* Truth Table of LUT0 bit 3 position. */ - -/* XCL.CTRLE bit masks and bit positions */ -#define XCL_CMDSEL_bm 0x80 /* Timer/Counter Command Selection bit mask. */ -#define XCL_CMDSEL_bp 7 /* Timer/Counter Command Selection bit position. */ - -#define XCL_TCSEL_gm 0x70 /* Timer/Counter Selection group mask. */ -#define XCL_TCSEL_gp 4 /* Timer/Counter Selection group position. */ -#define XCL_TCSEL0_bm (1<<4) /* Timer/Counter Selection bit 0 mask. */ -#define XCL_TCSEL0_bp 4 /* Timer/Counter Selection bit 0 position. */ -#define XCL_TCSEL1_bm (1<<5) /* Timer/Counter Selection bit 1 mask. */ -#define XCL_TCSEL1_bp 5 /* Timer/Counter Selection bit 1 position. */ -#define XCL_TCSEL2_bm (1<<6) /* Timer/Counter Selection bit 2 mask. */ -#define XCL_TCSEL2_bp 6 /* Timer/Counter Selection bit 2 position. */ - -#define XCL_CLKSEL_gm 0x0F /* Clock Selection group mask. */ -#define XCL_CLKSEL_gp 0 /* Clock Selection group position. */ -#define XCL_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ -#define XCL_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ -#define XCL_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ -#define XCL_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ -#define XCL_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ -#define XCL_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ -#define XCL_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ -#define XCL_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ - -/* XCL.CTRLF bit masks and bit positions */ -#define XCL_CMDEN_gm 0xC0 /* Command Enable group mask. */ -#define XCL_CMDEN_gp 6 /* Command Enable group position. */ -#define XCL_CMDEN0_bm (1<<6) /* Command Enable bit 0 mask. */ -#define XCL_CMDEN0_bp 6 /* Command Enable bit 0 position. */ -#define XCL_CMDEN1_bm (1<<7) /* Command Enable bit 1 mask. */ -#define XCL_CMDEN1_bp 7 /* Command Enable bit 1 position. */ - -#define XCL_CMP1_bm 0x20 /* Compare Channel 1 Output Value bit mask. */ -#define XCL_CMP1_bp 5 /* Compare Channel 1 Output Value bit position. */ - -#define XCL_CMP0_bm 0x10 /* Compare Channel 0 Output Value bit mask. */ -#define XCL_CMP0_bp 4 /* Compare Channel 0 Output Value bit position. */ - -#define XCL_CCEN1_bm 0x08 /* Compare or Capture Channel 1 Enable bit mask. */ -#define XCL_CCEN1_bp 3 /* Compare or Capture Channel 1 Enable bit position. */ - -#define XCL_CCEN0_bm 0x04 /* Compare or Capture Channel 0 Enable bit mask. */ -#define XCL_CCEN0_bp 2 /* Compare or Capture Channel 0 Enable bit position. */ - -#define XCL_MODE_gm 0x03 /* Timer/Counter Mode group mask. */ -#define XCL_MODE_gp 0 /* Timer/Counter Mode group position. */ -#define XCL_MODE0_bm (1<<0) /* Timer/Counter Mode bit 0 mask. */ -#define XCL_MODE0_bp 0 /* Timer/Counter Mode bit 0 position. */ -#define XCL_MODE1_bm (1<<1) /* Timer/Counter Mode bit 1 mask. */ -#define XCL_MODE1_bp 1 /* Timer/Counter Mode bit 1 position. */ - -/* XCL.CTRLG bit masks and bit positions */ -#define XCL_EVACTEN_bm 0x80 /* Event Action Enable bit mask. */ -#define XCL_EVACTEN_bp 7 /* Event Action Enable bit position. */ - -#define XCL_EVACT1_gm 0x60 /* Event Action Selection on Timer/Counter 1 group mask. */ -#define XCL_EVACT1_gp 5 /* Event Action Selection on Timer/Counter 1 group position. */ -#define XCL_EVACT10_bm (1<<5) /* Event Action Selection on Timer/Counter 1 bit 0 mask. */ -#define XCL_EVACT10_bp 5 /* Event Action Selection on Timer/Counter 1 bit 0 position. */ -#define XCL_EVACT11_bm (1<<6) /* Event Action Selection on Timer/Counter 1 bit 1 mask. */ -#define XCL_EVACT11_bp 6 /* Event Action Selection on Timer/Counter 1 bit 1 position. */ - -#define XCL_EVACT0_gm 0x18 /* Event Action Selection on Timer/Counter 0 group mask. */ -#define XCL_EVACT0_gp 3 /* Event Action Selection on Timer/Counter 0 group position. */ -#define XCL_EVACT00_bm (1<<3) /* Event Action Selection on Timer/Counter 0 bit 0 mask. */ -#define XCL_EVACT00_bp 3 /* Event Action Selection on Timer/Counter 0 bit 0 position. */ -#define XCL_EVACT01_bm (1<<4) /* Event Action Selection on Timer/Counter 0 bit 1 mask. */ -#define XCL_EVACT01_bp 4 /* Event Action Selection on Timer/Counter 0 bit 1 position. */ - -#define XCL_EVSRC_gm 0x07 /* Event Source Selection group mask. */ -#define XCL_EVSRC_gp 0 /* Event Source Selection group position. */ -#define XCL_EVSRC0_bm (1<<0) /* Event Source Selection bit 0 mask. */ -#define XCL_EVSRC0_bp 0 /* Event Source Selection bit 0 position. */ -#define XCL_EVSRC1_bm (1<<1) /* Event Source Selection bit 1 mask. */ -#define XCL_EVSRC1_bp 1 /* Event Source Selection bit 1 position. */ -#define XCL_EVSRC2_bm (1<<2) /* Event Source Selection bit 2 mask. */ -#define XCL_EVSRC2_bp 2 /* Event Source Selection bit 2 position. */ - -/* XCL.INTCTRL bit masks and bit positions */ -#define XCL_UNF1IE_bm 0x80 /* Underflow 1 Interrupt Enable bit mask. */ -#define XCL_UNF1IE_bp 7 /* Underflow 1 Interrupt Enable bit position. */ - -#define XCL_PEC1IE_bm 0x80 /* Peripheral Counter 1 Interrupt Enable bit mask. */ -#define XCL_PEC1IE_bp 7 /* Peripheral Counter 1 Interrupt Enable bit position. */ - -#define XCL_PEC21IE_bm 0x80 /* Peripheral High Counter 2 Interrupt Enable bit mask. */ -#define XCL_PEC21IE_bp 7 /* Peripheral High Counter 2 Interrupt Enable bit position. */ - -#define XCL_UNF0IE_bm 0x40 /* Underflow 0 Interrupt Enable bit mask. */ -#define XCL_UNF0IE_bp 6 /* Underflow 0 Interrupt Enable bit position. */ - -#define XCL_PEC0IE_bm 0x40 /* Peripheral Counter 0 Interrupt Enable bit mask. */ -#define XCL_PEC0IE_bp 6 /* Peripheral Counter 0 Interrupt Enable bit position. */ - -#define XCL_CC1IE_bm 0x20 /* Compare Or Capture 1 Interrupt Enable bit mask. */ -#define XCL_CC1IE_bp 5 /* Compare Or Capture 1 Interrupt Enable bit position. */ - -#define XCL_PEC20IE_bm 0x20 /* Peripheral Low Counter 2 Interrupt Enable bit mask. */ -#define XCL_PEC20IE_bp 5 /* Peripheral Low Counter 2 Interrupt Enable bit position. */ - -#define XCL_CC0IE_bm 0x10 /* Compare Or Capture 0 Interrupt Enable bit mask. */ -#define XCL_CC0IE_bp 4 /* Compare Or Capture 0 Interrupt Enable bit position. */ - -#define XCL_UNFINTLVL_gm 0x0C /* Timer Underflow Interrupt Level group mask. */ -#define XCL_UNFINTLVL_gp 2 /* Timer Underflow Interrupt Level group position. */ -#define XCL_UNFINTLVL0_bm (1<<2) /* Timer Underflow Interrupt Level bit 0 mask. */ -#define XCL_UNFINTLVL0_bp 2 /* Timer Underflow Interrupt Level bit 0 position. */ -#define XCL_UNFINTLVL1_bm (1<<3) /* Timer Underflow Interrupt Level bit 1 mask. */ -#define XCL_UNFINTLVL1_bp 3 /* Timer Underflow Interrupt Level bit 1 position. */ - -#define XCL_CCINTLVL_gm 0x03 /* Timer Compare or Capture Interrupt Level group mask. */ -#define XCL_CCINTLVL_gp 0 /* Timer Compare or Capture Interrupt Level group position. */ -#define XCL_CCINTLVL0_bm (1<<0) /* Timer Compare or Capture Interrupt Level bit 0 mask. */ -#define XCL_CCINTLVL0_bp 0 /* Timer Compare or Capture Interrupt Level bit 0 position. */ -#define XCL_CCINTLVL1_bm (1<<1) /* Timer Compare or Capture Interrupt Level bit 1 mask. */ -#define XCL_CCINTLVL1_bp 1 /* Timer Compare or Capture Interrupt Level bit 1 position. */ - -/* XCL.INTFLAGS bit masks and bit positions */ -#define XCL_UNF1IF_bm 0x80 /* Timer/Counter 1 Underflow Interrupt Flag bit mask. */ -#define XCL_UNF1IF_bp 7 /* Timer/Counter 1 Underflow Interrupt Flag bit position. */ - -#define XCL_PEC1IF_bm 0x80 /* Peripheral Counter 1 Interrupt Flag bit mask. */ -#define XCL_PEC1IF_bp 7 /* Peripheral Counter 1 Interrupt Flag bit position. */ - -#define XCL_PEC21IF_bm 0x80 /* Peripheral High Counter 2 Interrupt Flag bit mask. */ -#define XCL_PEC21IF_bp 7 /* Peripheral High Counter 2 Interrupt Flag bit position. */ - -#define XCL_UNF0IF_bm 0x40 /* Timer/Counter 0 Underflow Interrupt Flag bit mask. */ -#define XCL_UNF0IF_bp 6 /* Timer/Counter 0 Underflow Interrupt Flag bit position. */ - -#define XCL_PEC0IF_bm 0x40 /* Peripheral Counter 0 Interrupt Flag bit mask. */ -#define XCL_PEC0IF_bp 6 /* Peripheral Counter 0 Interrupt Flag bit position. */ - -#define XCL_CC1IF_bm 0x20 /* Compare or Capture Channel 1 Interrupt Flag bit mask. */ -#define XCL_CC1IF_bp 5 /* Compare or Capture Channel 1 Interrupt Flag bit position. */ - -#define XCL_PEC20IF_bm 0x20 /* Peripheral Low Counter 2 Interrupt Flag bit mask. */ -#define XCL_PEC20IF_bp 5 /* Peripheral Low Counter 2 Interrupt Flag bit position. */ - -#define XCL_CC0IF_bm 0x10 /* Compare or Capture Channel 0 Interrupt Flag bit mask. */ -#define XCL_CC0IF_bp 4 /* Compare or Capture Channel 0 Interrupt Flag bit position. */ - -/* XCL.PLC bit masks and bit positions */ -#define XCL_PLC_gm 0xFF /* Peripheral Lenght Control Bits group mask. */ -#define XCL_PLC_gp 0 /* Peripheral Lenght Control Bits group position. */ -#define XCL_PLC0_bm (1<<0) /* Peripheral Lenght Control Bits bit 0 mask. */ -#define XCL_PLC0_bp 0 /* Peripheral Lenght Control Bits bit 0 position. */ -#define XCL_PLC1_bm (1<<1) /* Peripheral Lenght Control Bits bit 1 mask. */ -#define XCL_PLC1_bp 1 /* Peripheral Lenght Control Bits bit 1 position. */ -#define XCL_PLC2_bm (1<<2) /* Peripheral Lenght Control Bits bit 2 mask. */ -#define XCL_PLC2_bp 2 /* Peripheral Lenght Control Bits bit 2 position. */ -#define XCL_PLC3_bm (1<<3) /* Peripheral Lenght Control Bits bit 3 mask. */ -#define XCL_PLC3_bp 3 /* Peripheral Lenght Control Bits bit 3 position. */ -#define XCL_PLC4_bm (1<<4) /* Peripheral Lenght Control Bits bit 4 mask. */ -#define XCL_PLC4_bp 4 /* Peripheral Lenght Control Bits bit 4 position. */ -#define XCL_PLC5_bm (1<<5) /* Peripheral Lenght Control Bits bit 5 mask. */ -#define XCL_PLC5_bp 5 /* Peripheral Lenght Control Bits bit 5 position. */ -#define XCL_PLC6_bm (1<<6) /* Peripheral Lenght Control Bits bit 6 mask. */ -#define XCL_PLC6_bp 6 /* Peripheral Lenght Control Bits bit 6 position. */ -#define XCL_PLC7_bm (1<<7) /* Peripheral Lenght Control Bits bit 7 mask. */ -#define XCL_PLC7_bp 7 /* Peripheral Lenght Control Bits bit 7 position. */ - -/* XCL.CNTL bit masks and bit positions */ -#define XCL_BCNTO_gm 0xFF /* BTC0 Counter Byte group mask. */ -#define XCL_BCNTO_gp 0 /* BTC0 Counter Byte group position. */ -#define XCL_BCNTO0_bm (1<<0) /* BTC0 Counter Byte bit 0 mask. */ -#define XCL_BCNTO0_bp 0 /* BTC0 Counter Byte bit 0 position. */ -#define XCL_BCNTO1_bm (1<<1) /* BTC0 Counter Byte bit 1 mask. */ -#define XCL_BCNTO1_bp 1 /* BTC0 Counter Byte bit 1 position. */ -#define XCL_BCNTO2_bm (1<<2) /* BTC0 Counter Byte bit 2 mask. */ -#define XCL_BCNTO2_bp 2 /* BTC0 Counter Byte bit 2 position. */ -#define XCL_BCNTO3_bm (1<<3) /* BTC0 Counter Byte bit 3 mask. */ -#define XCL_BCNTO3_bp 3 /* BTC0 Counter Byte bit 3 position. */ -#define XCL_BCNTO4_bm (1<<4) /* BTC0 Counter Byte bit 4 mask. */ -#define XCL_BCNTO4_bp 4 /* BTC0 Counter Byte bit 4 position. */ -#define XCL_BCNTO5_bm (1<<5) /* BTC0 Counter Byte bit 5 mask. */ -#define XCL_BCNTO5_bp 5 /* BTC0 Counter Byte bit 5 position. */ -#define XCL_BCNTO6_bm (1<<6) /* BTC0 Counter Byte bit 6 mask. */ -#define XCL_BCNTO6_bp 6 /* BTC0 Counter Byte bit 6 position. */ -#define XCL_BCNTO7_bm (1<<7) /* BTC0 Counter Byte bit 7 mask. */ -#define XCL_BCNTO7_bp 7 /* BTC0 Counter Byte bit 7 position. */ - -#define XCL_CNTL_gm 0xFF /* TC16 Counter Low Byte group mask. */ -#define XCL_CNTL_gp 0 /* TC16 Counter Low Byte group position. */ -#define XCL_CNTL0_bm (1<<0) /* TC16 Counter Low Byte bit 0 mask. */ -#define XCL_CNTL0_bp 0 /* TC16 Counter Low Byte bit 0 position. */ -#define XCL_CNTL1_bm (1<<1) /* TC16 Counter Low Byte bit 1 mask. */ -#define XCL_CNTL1_bp 1 /* TC16 Counter Low Byte bit 1 position. */ -#define XCL_CNTL2_bm (1<<2) /* TC16 Counter Low Byte bit 2 mask. */ -#define XCL_CNTL2_bp 2 /* TC16 Counter Low Byte bit 2 position. */ -#define XCL_CNTL3_bm (1<<3) /* TC16 Counter Low Byte bit 3 mask. */ -#define XCL_CNTL3_bp 3 /* TC16 Counter Low Byte bit 3 position. */ -#define XCL_CNTL4_bm (1<<4) /* TC16 Counter Low Byte bit 4 mask. */ -#define XCL_CNTL4_bp 4 /* TC16 Counter Low Byte bit 4 position. */ -#define XCL_CNTL5_bm (1<<5) /* TC16 Counter Low Byte bit 5 mask. */ -#define XCL_CNTL5_bp 5 /* TC16 Counter Low Byte bit 5 position. */ -#define XCL_CNTL6_bm (1<<6) /* TC16 Counter Low Byte bit 6 mask. */ -#define XCL_CNTL6_bp 6 /* TC16 Counter Low Byte bit 6 position. */ -#define XCL_CNTL7_bm (1<<7) /* TC16 Counter Low Byte bit 7 mask. */ -#define XCL_CNTL7_bp 7 /* TC16 Counter Low Byte bit 7 position. */ - -#define XCL_PCNTO_gm 0xFF /* Peripheral Counter 0 Byte group mask. */ -#define XCL_PCNTO_gp 0 /* Peripheral Counter 0 Byte group position. */ -#define XCL_PCNTO0_bm (1<<0) /* Peripheral Counter 0 Byte bit 0 mask. */ -#define XCL_PCNTO0_bp 0 /* Peripheral Counter 0 Byte bit 0 position. */ -#define XCL_PCNTO1_bm (1<<1) /* Peripheral Counter 0 Byte bit 1 mask. */ -#define XCL_PCNTO1_bp 1 /* Peripheral Counter 0 Byte bit 1 position. */ -#define XCL_PCNTO2_bm (1<<2) /* Peripheral Counter 0 Byte bit 2 mask. */ -#define XCL_PCNTO2_bp 2 /* Peripheral Counter 0 Byte bit 2 position. */ -#define XCL_PCNTO3_bm (1<<3) /* Peripheral Counter 0 Byte bit 3 mask. */ -#define XCL_PCNTO3_bp 3 /* Peripheral Counter 0 Byte bit 3 position. */ -#define XCL_PCNTO4_bm (1<<4) /* Peripheral Counter 0 Byte bit 4 mask. */ -#define XCL_PCNTO4_bp 4 /* Peripheral Counter 0 Byte bit 4 position. */ -#define XCL_PCNTO5_bm (1<<5) /* Peripheral Counter 0 Byte bit 5 mask. */ -#define XCL_PCNTO5_bp 5 /* Peripheral Counter 0 Byte bit 5 position. */ -#define XCL_PCNTO6_bm (1<<6) /* Peripheral Counter 0 Byte bit 6 mask. */ -#define XCL_PCNTO6_bp 6 /* Peripheral Counter 0 Byte bit 6 position. */ -#define XCL_PCNTO7_bm (1<<7) /* Peripheral Counter 0 Byte bit 7 mask. */ -#define XCL_PCNTO7_bp 7 /* Peripheral Counter 0 Byte bit 7 position. */ - -/* XCL.CNTH bit masks and bit positions */ -#define XCL_BCNT1_gm 0xFF /* BTC1 Counter Byte group mask. */ -#define XCL_BCNT1_gp 0 /* BTC1 Counter Byte group position. */ -#define XCL_BCNT10_bm (1<<0) /* BTC1 Counter Byte bit 0 mask. */ -#define XCL_BCNT10_bp 0 /* BTC1 Counter Byte bit 0 position. */ -#define XCL_BCNT11_bm (1<<1) /* BTC1 Counter Byte bit 1 mask. */ -#define XCL_BCNT11_bp 1 /* BTC1 Counter Byte bit 1 position. */ -#define XCL_BCNT12_bm (1<<2) /* BTC1 Counter Byte bit 2 mask. */ -#define XCL_BCNT12_bp 2 /* BTC1 Counter Byte bit 2 position. */ -#define XCL_BCNT13_bm (1<<3) /* BTC1 Counter Byte bit 3 mask. */ -#define XCL_BCNT13_bp 3 /* BTC1 Counter Byte bit 3 position. */ -#define XCL_BCNT14_bm (1<<4) /* BTC1 Counter Byte bit 4 mask. */ -#define XCL_BCNT14_bp 4 /* BTC1 Counter Byte bit 4 position. */ -#define XCL_BCNT15_bm (1<<5) /* BTC1 Counter Byte bit 5 mask. */ -#define XCL_BCNT15_bp 5 /* BTC1 Counter Byte bit 5 position. */ -#define XCL_BCNT16_bm (1<<6) /* BTC1 Counter Byte bit 6 mask. */ -#define XCL_BCNT16_bp 6 /* BTC1 Counter Byte bit 6 position. */ -#define XCL_BCNT17_bm (1<<7) /* BTC1 Counter Byte bit 7 mask. */ -#define XCL_BCNT17_bp 7 /* BTC1 Counter Byte bit 7 position. */ - -#define XCL_CNTH_gm 0xFF /* TC16 Counter High Byte group mask. */ -#define XCL_CNTH_gp 0 /* TC16 Counter High Byte group position. */ -#define XCL_CNTH0_bm (1<<0) /* TC16 Counter High Byte bit 0 mask. */ -#define XCL_CNTH0_bp 0 /* TC16 Counter High Byte bit 0 position. */ -#define XCL_CNTH1_bm (1<<1) /* TC16 Counter High Byte bit 1 mask. */ -#define XCL_CNTH1_bp 1 /* TC16 Counter High Byte bit 1 position. */ -#define XCL_CNTH2_bm (1<<2) /* TC16 Counter High Byte bit 2 mask. */ -#define XCL_CNTH2_bp 2 /* TC16 Counter High Byte bit 2 position. */ -#define XCL_CNTH3_bm (1<<3) /* TC16 Counter High Byte bit 3 mask. */ -#define XCL_CNTH3_bp 3 /* TC16 Counter High Byte bit 3 position. */ -#define XCL_CNTH4_bm (1<<4) /* TC16 Counter High Byte bit 4 mask. */ -#define XCL_CNTH4_bp 4 /* TC16 Counter High Byte bit 4 position. */ -#define XCL_CNTH5_bm (1<<5) /* TC16 Counter High Byte bit 5 mask. */ -#define XCL_CNTH5_bp 5 /* TC16 Counter High Byte bit 5 position. */ -#define XCL_CNTH6_bm (1<<6) /* TC16 Counter High Byte bit 6 mask. */ -#define XCL_CNTH6_bp 6 /* TC16 Counter High Byte bit 6 position. */ -#define XCL_CNTH7_bm (1<<7) /* TC16 Counter High Byte bit 7 mask. */ -#define XCL_CNTH7_bp 7 /* TC16 Counter High Byte bit 7 position. */ - -#define XCL_PCNT1_gm 0xFF /* Peripheral Counter 1 Byte group mask. */ -#define XCL_PCNT1_gp 0 /* Peripheral Counter 1 Byte group position. */ -#define XCL_PCNT10_bm (1<<0) /* Peripheral Counter 1 Byte bit 0 mask. */ -#define XCL_PCNT10_bp 0 /* Peripheral Counter 1 Byte bit 0 position. */ -#define XCL_PCNT11_bm (1<<1) /* Peripheral Counter 1 Byte bit 1 mask. */ -#define XCL_PCNT11_bp 1 /* Peripheral Counter 1 Byte bit 1 position. */ -#define XCL_PCNT12_bm (1<<2) /* Peripheral Counter 1 Byte bit 2 mask. */ -#define XCL_PCNT12_bp 2 /* Peripheral Counter 1 Byte bit 2 position. */ -#define XCL_PCNT13_bm (1<<3) /* Peripheral Counter 1 Byte bit 3 mask. */ -#define XCL_PCNT13_bp 3 /* Peripheral Counter 1 Byte bit 3 position. */ -#define XCL_PCNT14_bm (1<<4) /* Peripheral Counter 1 Byte bit 4 mask. */ -#define XCL_PCNT14_bp 4 /* Peripheral Counter 1 Byte bit 4 position. */ -#define XCL_PCNT15_bm (1<<5) /* Peripheral Counter 1 Byte bit 5 mask. */ -#define XCL_PCNT15_bp 5 /* Peripheral Counter 1 Byte bit 5 position. */ -#define XCL_PCNT16_bm (1<<6) /* Peripheral Counter 1 Byte bit 6 mask. */ -#define XCL_PCNT16_bp 6 /* Peripheral Counter 1 Byte bit 6 position. */ -#define XCL_PCNT17_bm (1<<7) /* Peripheral Counter 1 Byte bit 7 mask. */ -#define XCL_PCNT17_bp 7 /* Peripheral Counter 1 Byte bit 7 position. */ - -#define XCL_PCNT21_gm 0xF0 /* Peripheral High Counter 2 Bits group mask. */ -#define XCL_PCNT21_gp 4 /* Peripheral High Counter 2 Bits group position. */ -#define XCL_PCNT210_bm (1<<4) /* Peripheral High Counter 2 Bits bit 0 mask. */ -#define XCL_PCNT210_bp 4 /* Peripheral High Counter 2 Bits bit 0 position. */ -#define XCL_PCNT211_bm (1<<5) /* Peripheral High Counter 2 Bits bit 1 mask. */ -#define XCL_PCNT211_bp 5 /* Peripheral High Counter 2 Bits bit 1 position. */ -#define XCL_PCNT212_bm (1<<6) /* Peripheral High Counter 2 Bits bit 2 mask. */ -#define XCL_PCNT212_bp 6 /* Peripheral High Counter 2 Bits bit 2 position. */ -#define XCL_PCNT213_bm (1<<7) /* Peripheral High Counter 2 Bits bit 3 mask. */ -#define XCL_PCNT213_bp 7 /* Peripheral High Counter 2 Bits bit 3 position. */ - -#define XCL_PCNT20_gm 0x0F /* Peripheral Low Counter 2 Bits group mask. */ -#define XCL_PCNT20_gp 0 /* Peripheral Low Counter 2 Bits group position. */ -#define XCL_PCNT200_bm (1<<0) /* Peripheral Low Counter 2 Bits bit 0 mask. */ -#define XCL_PCNT200_bp 0 /* Peripheral Low Counter 2 Bits bit 0 position. */ -#define XCL_PCNT201_bm (1<<1) /* Peripheral Low Counter 2 Bits bit 1 mask. */ -#define XCL_PCNT201_bp 1 /* Peripheral Low Counter 2 Bits bit 1 position. */ -#define XCL_PCNT202_bm (1<<2) /* Peripheral Low Counter 2 Bits bit 2 mask. */ -#define XCL_PCNT202_bp 2 /* Peripheral Low Counter 2 Bits bit 2 position. */ -#define XCL_PCNT203_bm (1<<3) /* Peripheral Low Counter 2 Bits bit 3 mask. */ -#define XCL_PCNT203_bp 3 /* Peripheral Low Counter 2 Bits bit 3 position. */ - -/* XCL.CMPL bit masks and bit positions */ -#define XCL_CMPL_gm 0xFF /* TC16 Compare Low Byte group mask. */ -#define XCL_CMPL_gp 0 /* TC16 Compare Low Byte group position. */ -#define XCL_CMPL0_bm (1<<0) /* TC16 Compare Low Byte bit 0 mask. */ -#define XCL_CMPL0_bp 0 /* TC16 Compare Low Byte bit 0 position. */ -#define XCL_CMPL1_bm (1<<1) /* TC16 Compare Low Byte bit 1 mask. */ -#define XCL_CMPL1_bp 1 /* TC16 Compare Low Byte bit 1 position. */ -#define XCL_CMPL2_bm (1<<2) /* TC16 Compare Low Byte bit 2 mask. */ -#define XCL_CMPL2_bp 2 /* TC16 Compare Low Byte bit 2 position. */ -#define XCL_CMPL3_bm (1<<3) /* TC16 Compare Low Byte bit 3 mask. */ -#define XCL_CMPL3_bp 3 /* TC16 Compare Low Byte bit 3 position. */ -#define XCL_CMPL4_bm (1<<4) /* TC16 Compare Low Byte bit 4 mask. */ -#define XCL_CMPL4_bp 4 /* TC16 Compare Low Byte bit 4 position. */ -#define XCL_CMPL5_bm (1<<5) /* TC16 Compare Low Byte bit 5 mask. */ -#define XCL_CMPL5_bp 5 /* TC16 Compare Low Byte bit 5 position. */ -#define XCL_CMPL6_bm (1<<6) /* TC16 Compare Low Byte bit 6 mask. */ -#define XCL_CMPL6_bp 6 /* TC16 Compare Low Byte bit 6 position. */ -#define XCL_CMPL7_bm (1<<7) /* TC16 Compare Low Byte bit 7 mask. */ -#define XCL_CMPL7_bp 7 /* TC16 Compare Low Byte bit 7 position. */ - -#define XCL_BCMP0_gm 0xFF /* BTC0 Compare Byte group mask. */ -#define XCL_BCMP0_gp 0 /* BTC0 Compare Byte group position. */ -#define XCL_BCMP00_bm (1<<0) /* BTC0 Compare Byte bit 0 mask. */ -#define XCL_BCMP00_bp 0 /* BTC0 Compare Byte bit 0 position. */ -#define XCL_BCMP01_bm (1<<1) /* BTC0 Compare Byte bit 1 mask. */ -#define XCL_BCMP01_bp 1 /* BTC0 Compare Byte bit 1 position. */ -#define XCL_BCMP02_bm (1<<2) /* BTC0 Compare Byte bit 2 mask. */ -#define XCL_BCMP02_bp 2 /* BTC0 Compare Byte bit 2 position. */ -#define XCL_BCMP03_bm (1<<3) /* BTC0 Compare Byte bit 3 mask. */ -#define XCL_BCMP03_bp 3 /* BTC0 Compare Byte bit 3 position. */ -#define XCL_BCMP04_bm (1<<4) /* BTC0 Compare Byte bit 4 mask. */ -#define XCL_BCMP04_bp 4 /* BTC0 Compare Byte bit 4 position. */ -#define XCL_BCMP05_bm (1<<5) /* BTC0 Compare Byte bit 5 mask. */ -#define XCL_BCMP05_bp 5 /* BTC0 Compare Byte bit 5 position. */ -#define XCL_BCMP06_bm (1<<6) /* BTC0 Compare Byte bit 6 mask. */ -#define XCL_BCMP06_bp 6 /* BTC0 Compare Byte bit 6 position. */ -#define XCL_BCMP07_bm (1<<7) /* BTC0 Compare Byte bit 7 mask. */ -#define XCL_BCMP07_bp 7 /* BTC0 Compare Byte bit 7 position. */ - -/* XCL.CMPH bit masks and bit positions */ -#define XCL_CMPH_gm 0xFF /* TC16 Compare High Byte group mask. */ -#define XCL_CMPH_gp 0 /* TC16 Compare High Byte group position. */ -#define XCL_CMPH0_bm (1<<0) /* TC16 Compare High Byte bit 0 mask. */ -#define XCL_CMPH0_bp 0 /* TC16 Compare High Byte bit 0 position. */ -#define XCL_CMPH1_bm (1<<1) /* TC16 Compare High Byte bit 1 mask. */ -#define XCL_CMPH1_bp 1 /* TC16 Compare High Byte bit 1 position. */ -#define XCL_CMPH2_bm (1<<2) /* TC16 Compare High Byte bit 2 mask. */ -#define XCL_CMPH2_bp 2 /* TC16 Compare High Byte bit 2 position. */ -#define XCL_CMPH3_bm (1<<3) /* TC16 Compare High Byte bit 3 mask. */ -#define XCL_CMPH3_bp 3 /* TC16 Compare High Byte bit 3 position. */ -#define XCL_CMPH4_bm (1<<4) /* TC16 Compare High Byte bit 4 mask. */ -#define XCL_CMPH4_bp 4 /* TC16 Compare High Byte bit 4 position. */ -#define XCL_CMPH5_bm (1<<5) /* TC16 Compare High Byte bit 5 mask. */ -#define XCL_CMPH5_bp 5 /* TC16 Compare High Byte bit 5 position. */ -#define XCL_CMPH6_bm (1<<6) /* TC16 Compare High Byte bit 6 mask. */ -#define XCL_CMPH6_bp 6 /* TC16 Compare High Byte bit 6 position. */ -#define XCL_CMPH7_bm (1<<7) /* TC16 Compare High Byte bit 7 mask. */ -#define XCL_CMPH7_bp 7 /* TC16 Compare High Byte bit 7 position. */ - -#define XCL_BCMP1_gm 0xFF /* BTC1 Compare Byte group mask. */ -#define XCL_BCMP1_gp 0 /* BTC1 Compare Byte group position. */ -#define XCL_BCMP10_bm (1<<0) /* BTC1 Compare Byte bit 0 mask. */ -#define XCL_BCMP10_bp 0 /* BTC1 Compare Byte bit 0 position. */ -#define XCL_BCMP11_bm (1<<1) /* BTC1 Compare Byte bit 1 mask. */ -#define XCL_BCMP11_bp 1 /* BTC1 Compare Byte bit 1 position. */ -#define XCL_BCMP12_bm (1<<2) /* BTC1 Compare Byte bit 2 mask. */ -#define XCL_BCMP12_bp 2 /* BTC1 Compare Byte bit 2 position. */ -#define XCL_BCMP13_bm (1<<3) /* BTC1 Compare Byte bit 3 mask. */ -#define XCL_BCMP13_bp 3 /* BTC1 Compare Byte bit 3 position. */ -#define XCL_BCMP14_bm (1<<4) /* BTC1 Compare Byte bit 4 mask. */ -#define XCL_BCMP14_bp 4 /* BTC1 Compare Byte bit 4 position. */ -#define XCL_BCMP15_bm (1<<5) /* BTC1 Compare Byte bit 5 mask. */ -#define XCL_BCMP15_bp 5 /* BTC1 Compare Byte bit 5 position. */ -#define XCL_BCMP16_bm (1<<6) /* BTC1 Compare Byte bit 6 mask. */ -#define XCL_BCMP16_bp 6 /* BTC1 Compare Byte bit 6 position. */ -#define XCL_BCMP17_bm (1<<7) /* BTC1 Compare Byte bit 7 mask. */ -#define XCL_BCMP17_bp 7 /* BTC1 Compare Byte bit 7 position. */ - -/* XCL.PERCAPTL bit masks and bit positions */ -#define XCL_PERL_gm 0xFF /* TC16 Low Byte Period group mask. */ -#define XCL_PERL_gp 0 /* TC16 Low Byte Period group position. */ -#define XCL_PERL0_bm (1<<0) /* TC16 Low Byte Period bit 0 mask. */ -#define XCL_PERL0_bp 0 /* TC16 Low Byte Period bit 0 position. */ -#define XCL_PERL1_bm (1<<1) /* TC16 Low Byte Period bit 1 mask. */ -#define XCL_PERL1_bp 1 /* TC16 Low Byte Period bit 1 position. */ -#define XCL_PERL2_bm (1<<2) /* TC16 Low Byte Period bit 2 mask. */ -#define XCL_PERL2_bp 2 /* TC16 Low Byte Period bit 2 position. */ -#define XCL_PERL3_bm (1<<3) /* TC16 Low Byte Period bit 3 mask. */ -#define XCL_PERL3_bp 3 /* TC16 Low Byte Period bit 3 position. */ -#define XCL_PERL4_bm (1<<4) /* TC16 Low Byte Period bit 4 mask. */ -#define XCL_PERL4_bp 4 /* TC16 Low Byte Period bit 4 position. */ -#define XCL_PERL5_bm (1<<5) /* TC16 Low Byte Period bit 5 mask. */ -#define XCL_PERL5_bp 5 /* TC16 Low Byte Period bit 5 position. */ -#define XCL_PERL6_bm (1<<6) /* TC16 Low Byte Period bit 6 mask. */ -#define XCL_PERL6_bp 6 /* TC16 Low Byte Period bit 6 position. */ -#define XCL_PERL7_bm (1<<7) /* TC16 Low Byte Period bit 7 mask. */ -#define XCL_PERL7_bp 7 /* TC16 Low Byte Period bit 7 position. */ - -#define XCL_CAPTL_gm 0xFF /* TC16 Capture Value Low Byte group mask. */ -#define XCL_CAPTL_gp 0 /* TC16 Capture Value Low Byte group position. */ -#define XCL_CAPTL0_bm (1<<0) /* TC16 Capture Value Low Byte bit 0 mask. */ -#define XCL_CAPTL0_bp 0 /* TC16 Capture Value Low Byte bit 0 position. */ -#define XCL_CAPTL1_bm (1<<1) /* TC16 Capture Value Low Byte bit 1 mask. */ -#define XCL_CAPTL1_bp 1 /* TC16 Capture Value Low Byte bit 1 position. */ -#define XCL_CAPTL2_bm (1<<2) /* TC16 Capture Value Low Byte bit 2 mask. */ -#define XCL_CAPTL2_bp 2 /* TC16 Capture Value Low Byte bit 2 position. */ -#define XCL_CAPTL3_bm (1<<3) /* TC16 Capture Value Low Byte bit 3 mask. */ -#define XCL_CAPTL3_bp 3 /* TC16 Capture Value Low Byte bit 3 position. */ -#define XCL_CAPTL4_bm (1<<4) /* TC16 Capture Value Low Byte bit 4 mask. */ -#define XCL_CAPTL4_bp 4 /* TC16 Capture Value Low Byte bit 4 position. */ -#define XCL_CAPTL5_bm (1<<5) /* TC16 Capture Value Low Byte bit 5 mask. */ -#define XCL_CAPTL5_bp 5 /* TC16 Capture Value Low Byte bit 5 position. */ -#define XCL_CAPTL6_bm (1<<6) /* TC16 Capture Value Low Byte bit 6 mask. */ -#define XCL_CAPTL6_bp 6 /* TC16 Capture Value Low Byte bit 6 position. */ -#define XCL_CAPTL7_bm (1<<7) /* TC16 Capture Value Low Byte bit 7 mask. */ -#define XCL_CAPTL7_bp 7 /* TC16 Capture Value Low Byte bit 7 position. */ - -#define XCL_BPER0_gm 0xFF /* BTC0 Period group mask. */ -#define XCL_BPER0_gp 0 /* BTC0 Period group position. */ -#define XCL_BPER00_bm (1<<0) /* BTC0 Period bit 0 mask. */ -#define XCL_BPER00_bp 0 /* BTC0 Period bit 0 position. */ -#define XCL_BPER01_bm (1<<1) /* BTC0 Period bit 1 mask. */ -#define XCL_BPER01_bp 1 /* BTC0 Period bit 1 position. */ -#define XCL_BPER02_bm (1<<2) /* BTC0 Period bit 2 mask. */ -#define XCL_BPER02_bp 2 /* BTC0 Period bit 2 position. */ -#define XCL_BPER03_bm (1<<3) /* BTC0 Period bit 3 mask. */ -#define XCL_BPER03_bp 3 /* BTC0 Period bit 3 position. */ -#define XCL_BPER04_bm (1<<4) /* BTC0 Period bit 4 mask. */ -#define XCL_BPER04_bp 4 /* BTC0 Period bit 4 position. */ -#define XCL_BPER05_bm (1<<5) /* BTC0 Period bit 5 mask. */ -#define XCL_BPER05_bp 5 /* BTC0 Period bit 5 position. */ -#define XCL_BPER06_bm (1<<6) /* BTC0 Period bit 6 mask. */ -#define XCL_BPER06_bp 6 /* BTC0 Period bit 6 position. */ -#define XCL_BPER07_bm (1<<7) /* BTC0 Period bit 7 mask. */ -#define XCL_BPER07_bp 7 /* BTC0 Period bit 7 position. */ - -#define XCL_BCAPT0_gm 0xFF /* BTC0 Capture Value Byte group mask. */ -#define XCL_BCAPT0_gp 0 /* BTC0 Capture Value Byte group position. */ -#define XCL_BCAPT00_bm (1<<0) /* BTC0 Capture Value Byte bit 0 mask. */ -#define XCL_BCAPT00_bp 0 /* BTC0 Capture Value Byte bit 0 position. */ -#define XCL_BCAPT01_bm (1<<1) /* BTC0 Capture Value Byte bit 1 mask. */ -#define XCL_BCAPT01_bp 1 /* BTC0 Capture Value Byte bit 1 position. */ -#define XCL_BCAPT02_bm (1<<2) /* BTC0 Capture Value Byte bit 2 mask. */ -#define XCL_BCAPT02_bp 2 /* BTC0 Capture Value Byte bit 2 position. */ -#define XCL_BCAPT03_bm (1<<3) /* BTC0 Capture Value Byte bit 3 mask. */ -#define XCL_BCAPT03_bp 3 /* BTC0 Capture Value Byte bit 3 position. */ -#define XCL_BCAPT04_bm (1<<4) /* BTC0 Capture Value Byte bit 4 mask. */ -#define XCL_BCAPT04_bp 4 /* BTC0 Capture Value Byte bit 4 position. */ -#define XCL_BCAPT05_bm (1<<5) /* BTC0 Capture Value Byte bit 5 mask. */ -#define XCL_BCAPT05_bp 5 /* BTC0 Capture Value Byte bit 5 position. */ -#define XCL_BCAPT06_bm (1<<6) /* BTC0 Capture Value Byte bit 6 mask. */ -#define XCL_BCAPT06_bp 6 /* BTC0 Capture Value Byte bit 6 position. */ -#define XCL_BCAPT07_bm (1<<7) /* BTC0 Capture Value Byte bit 7 mask. */ -#define XCL_BCAPT07_bp 7 /* BTC0 Capture Value Byte bit 7 position. */ - -/* XCL.PERCAPTH bit masks and bit positions */ -#define XCL_PERH_gm 0xFF /* TC16 High Byte Period group mask. */ -#define XCL_PERH_gp 0 /* TC16 High Byte Period group position. */ -#define XCL_PERH0_bm (1<<0) /* TC16 High Byte Period bit 0 mask. */ -#define XCL_PERH0_bp 0 /* TC16 High Byte Period bit 0 position. */ -#define XCL_PERH1_bm (1<<1) /* TC16 High Byte Period bit 1 mask. */ -#define XCL_PERH1_bp 1 /* TC16 High Byte Period bit 1 position. */ -#define XCL_PERH2_bm (1<<2) /* TC16 High Byte Period bit 2 mask. */ -#define XCL_PERH2_bp 2 /* TC16 High Byte Period bit 2 position. */ -#define XCL_PERH3_bm (1<<3) /* TC16 High Byte Period bit 3 mask. */ -#define XCL_PERH3_bp 3 /* TC16 High Byte Period bit 3 position. */ -#define XCL_PERH4_bm (1<<4) /* TC16 High Byte Period bit 4 mask. */ -#define XCL_PERH4_bp 4 /* TC16 High Byte Period bit 4 position. */ -#define XCL_PERH5_bm (1<<5) /* TC16 High Byte Period bit 5 mask. */ -#define XCL_PERH5_bp 5 /* TC16 High Byte Period bit 5 position. */ -#define XCL_PERH6_bm (1<<6) /* TC16 High Byte Period bit 6 mask. */ -#define XCL_PERH6_bp 6 /* TC16 High Byte Period bit 6 position. */ -#define XCL_PERH7_bm (1<<7) /* TC16 High Byte Period bit 7 mask. */ -#define XCL_PERH7_bp 7 /* TC16 High Byte Period bit 7 position. */ - -#define XCL_CAPTH_gm 0xFF /* TC16 Capture Value High Byte group mask. */ -#define XCL_CAPTH_gp 0 /* TC16 Capture Value High Byte group position. */ -#define XCL_CAPTH0_bm (1<<0) /* TC16 Capture Value High Byte bit 0 mask. */ -#define XCL_CAPTH0_bp 0 /* TC16 Capture Value High Byte bit 0 position. */ -#define XCL_CAPTH1_bm (1<<1) /* TC16 Capture Value High Byte bit 1 mask. */ -#define XCL_CAPTH1_bp 1 /* TC16 Capture Value High Byte bit 1 position. */ -#define XCL_CAPTH2_bm (1<<2) /* TC16 Capture Value High Byte bit 2 mask. */ -#define XCL_CAPTH2_bp 2 /* TC16 Capture Value High Byte bit 2 position. */ -#define XCL_CAPTH3_bm (1<<3) /* TC16 Capture Value High Byte bit 3 mask. */ -#define XCL_CAPTH3_bp 3 /* TC16 Capture Value High Byte bit 3 position. */ -#define XCL_CAPTH4_bm (1<<4) /* TC16 Capture Value High Byte bit 4 mask. */ -#define XCL_CAPTH4_bp 4 /* TC16 Capture Value High Byte bit 4 position. */ -#define XCL_CAPTH5_bm (1<<5) /* TC16 Capture Value High Byte bit 5 mask. */ -#define XCL_CAPTH5_bp 5 /* TC16 Capture Value High Byte bit 5 position. */ -#define XCL_CAPTH6_bm (1<<6) /* TC16 Capture Value High Byte bit 6 mask. */ -#define XCL_CAPTH6_bp 6 /* TC16 Capture Value High Byte bit 6 position. */ -#define XCL_CAPTH7_bm (1<<7) /* TC16 Capture Value High Byte bit 7 mask. */ -#define XCL_CAPTH7_bp 7 /* TC16 Capture Value High Byte bit 7 position. */ - -#define XCL_BPER1_gm 0xFF /* BTC1 Period group mask. */ -#define XCL_BPER1_gp 0 /* BTC1 Period group position. */ -#define XCL_BPER10_bm (1<<0) /* BTC1 Period bit 0 mask. */ -#define XCL_BPER10_bp 0 /* BTC1 Period bit 0 position. */ -#define XCL_BPER11_bm (1<<1) /* BTC1 Period bit 1 mask. */ -#define XCL_BPER11_bp 1 /* BTC1 Period bit 1 position. */ -#define XCL_BPER12_bm (1<<2) /* BTC1 Period bit 2 mask. */ -#define XCL_BPER12_bp 2 /* BTC1 Period bit 2 position. */ -#define XCL_BPER13_bm (1<<3) /* BTC1 Period bit 3 mask. */ -#define XCL_BPER13_bp 3 /* BTC1 Period bit 3 position. */ -#define XCL_BPER14_bm (1<<4) /* BTC1 Period bit 4 mask. */ -#define XCL_BPER14_bp 4 /* BTC1 Period bit 4 position. */ -#define XCL_BPER15_bm (1<<5) /* BTC1 Period bit 5 mask. */ -#define XCL_BPER15_bp 5 /* BTC1 Period bit 5 position. */ -#define XCL_BPER16_bm (1<<6) /* BTC1 Period bit 6 mask. */ -#define XCL_BPER16_bp 6 /* BTC1 Period bit 6 position. */ -#define XCL_BPER17_bm (1<<7) /* BTC1 Period bit 7 mask. */ -#define XCL_BPER17_bp 7 /* BTC1 Period bit 7 position. */ - -#define XCL_BCAPT1_gm 0xFF /* BTC1 Capture Value Byte group mask. */ -#define XCL_BCAPT1_gp 0 /* BTC1 Capture Value Byte group position. */ -#define XCL_BCAPT10_bm (1<<0) /* BTC1 Capture Value Byte bit 0 mask. */ -#define XCL_BCAPT10_bp 0 /* BTC1 Capture Value Byte bit 0 position. */ -#define XCL_BCAPT11_bm (1<<1) /* BTC1 Capture Value Byte bit 1 mask. */ -#define XCL_BCAPT11_bp 1 /* BTC1 Capture Value Byte bit 1 position. */ -#define XCL_BCAPT12_bm (1<<2) /* BTC1 Capture Value Byte bit 2 mask. */ -#define XCL_BCAPT12_bp 2 /* BTC1 Capture Value Byte bit 2 position. */ -#define XCL_BCAPT13_bm (1<<3) /* BTC1 Capture Value Byte bit 3 mask. */ -#define XCL_BCAPT13_bp 3 /* BTC1 Capture Value Byte bit 3 position. */ -#define XCL_BCAPT14_bm (1<<4) /* BTC1 Capture Value Byte bit 4 mask. */ -#define XCL_BCAPT14_bp 4 /* BTC1 Capture Value Byte bit 4 position. */ -#define XCL_BCAPT15_bm (1<<5) /* BTC1 Capture Value Byte bit 5 mask. */ -#define XCL_BCAPT15_bp 5 /* BTC1 Capture Value Byte bit 5 position. */ -#define XCL_BCAPT16_bm (1<<6) /* BTC1 Capture Value Byte bit 6 mask. */ -#define XCL_BCAPT16_bp 6 /* BTC1 Capture Value Byte bit 6 position. */ -#define XCL_BCAPT17_bm (1<<7) /* BTC1 Capture Value Byte bit 7 mask. */ -#define XCL_BCAPT17_bp 7 /* BTC1 Capture Value Byte bit 7 position. */ - -/* TWI - Two-Wire Interface */ -/* TWI.CTRL bit masks and bit positions */ -#define TWI_BRIDGEEN_bm 0x80 /* Bridge Enable bit mask. */ -#define TWI_BRIDGEEN_bp 7 /* Bridge Enable bit position. */ - -#define TWI_SFMPEN_bm 0x40 /* Slave Fast Mode Plus Enable bit mask. */ -#define TWI_SFMPEN_bp 6 /* Slave Fast Mode Plus Enable bit position. */ - -#define TWI_SSDAHOLD_gm 0x30 /* Slave SDA Hold Time Enable group mask. */ -#define TWI_SSDAHOLD_gp 4 /* Slave SDA Hold Time Enable group position. */ -#define TWI_SSDAHOLD0_bm (1<<4) /* Slave SDA Hold Time Enable bit 0 mask. */ -#define TWI_SSDAHOLD0_bp 4 /* Slave SDA Hold Time Enable bit 0 position. */ -#define TWI_SSDAHOLD1_bm (1<<5) /* Slave SDA Hold Time Enable bit 1 mask. */ -#define TWI_SSDAHOLD1_bp 5 /* Slave SDA Hold Time Enable bit 1 position. */ - -#define TWI_FMPEN_bm 0x08 /* FMPLUS Enable bit mask. */ -#define TWI_FMPEN_bp 3 /* FMPLUS Enable bit position. */ - -#define TWI_SDAHOLD_gm 0x06 /* SDA Hold Time Enable group mask. */ -#define TWI_SDAHOLD_gp 1 /* SDA Hold Time Enable group position. */ -#define TWI_SDAHOLD0_bm (1<<1) /* SDA Hold Time Enable bit 0 mask. */ -#define TWI_SDAHOLD0_bp 1 /* SDA Hold Time Enable bit 0 position. */ -#define TWI_SDAHOLD1_bm (1<<2) /* SDA Hold Time Enable bit 1 mask. */ -#define TWI_SDAHOLD1_bp 2 /* SDA Hold Time Enable bit 1 position. */ - -#define TWI_EDIEN_bm 0x01 /* External Driver Interface Enable bit mask. */ -#define TWI_EDIEN_bp 0 /* External Driver Interface Enable bit position. */ - -/* TWI_MASTER.CTRLA bit masks and bit positions */ -#define TWI_MASTER_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ -#define TWI_MASTER_INTLVL_gp 6 /* Interrupt Level group position. */ -#define TWI_MASTER_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ -#define TWI_MASTER_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ -#define TWI_MASTER_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ -#define TWI_MASTER_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ - -#define TWI_MASTER_RIEN_bm 0x20 /* Read Interrupt Enable bit mask. */ -#define TWI_MASTER_RIEN_bp 5 /* Read Interrupt Enable bit position. */ - -#define TWI_MASTER_WIEN_bm 0x10 /* Write Interrupt Enable bit mask. */ -#define TWI_MASTER_WIEN_bp 4 /* Write Interrupt Enable bit position. */ - -#define TWI_MASTER_ENABLE_bm 0x08 /* Enable TWI Master bit mask. */ -#define TWI_MASTER_ENABLE_bp 3 /* Enable TWI Master bit position. */ - -/* TWI_MASTER.CTRLB bit masks and bit positions */ -#define TWI_MASTER_TIMEOUT_gm 0x0C /* Inactive Bus Timeout group mask. */ -#define TWI_MASTER_TIMEOUT_gp 2 /* Inactive Bus Timeout group position. */ -#define TWI_MASTER_TIMEOUT0_bm (1<<2) /* Inactive Bus Timeout bit 0 mask. */ -#define TWI_MASTER_TIMEOUT0_bp 2 /* Inactive Bus Timeout bit 0 position. */ -#define TWI_MASTER_TIMEOUT1_bm (1<<3) /* Inactive Bus Timeout bit 1 mask. */ -#define TWI_MASTER_TIMEOUT1_bp 3 /* Inactive Bus Timeout bit 1 position. */ - -#define TWI_MASTER_QCEN_bm 0x02 /* Quick Command Enable bit mask. */ -#define TWI_MASTER_QCEN_bp 1 /* Quick Command Enable bit position. */ - -#define TWI_MASTER_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ -#define TWI_MASTER_SMEN_bp 0 /* Smart Mode Enable bit position. */ - -#define TWI_MASTER_TTOUTEN_bm 0x10 /* Ttimeout Enable bit mask. */ -#define TWI_MASTER_TTOUTEN_bp 4 /* Ttimeout Enable bit position. */ - -#define TWI_MASTER_TSEXTEN_bm 0x20 /* Slave Extend Timeout Enable bit mask. */ -#define TWI_MASTER_TSEXTEN_bp 5 /* Slave Extend Timeout Enable bit position. */ - -#define TWI_MASTER_TMEXTEN_bm 0x40 /* Master Extend Timeout Enable bit mask. */ -#define TWI_MASTER_TMEXTEN_bp 6 /* Master Extend Timeout Enable bit position. */ - -#define TWI_MASTER_TOIE_bm 0x80 /* Timeout Interrupt Enable bit mask. */ -#define TWI_MASTER_TOIE_bp 7 /* Timeout Interrupt Enable bit position. */ - -/* TWI_MASTER.CTRLC bit masks and bit positions */ -#define TWI_MASTER_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ -#define TWI_MASTER_ACKACT_bp 2 /* Acknowledge Action bit position. */ - -#define TWI_MASTER_CMD_gm 0x03 /* Command group mask. */ -#define TWI_MASTER_CMD_gp 0 /* Command group position. */ -#define TWI_MASTER_CMD0_bm (1<<0) /* Command bit 0 mask. */ -#define TWI_MASTER_CMD0_bp 0 /* Command bit 0 position. */ -#define TWI_MASTER_CMD1_bm (1<<1) /* Command bit 1 mask. */ -#define TWI_MASTER_CMD1_bp 1 /* Command bit 1 position. */ - -/* TWI_MASTER.STATUS bit masks and bit positions */ -#define TWI_MASTER_RIF_bm 0x80 /* Read Interrupt Flag bit mask. */ -#define TWI_MASTER_RIF_bp 7 /* Read Interrupt Flag bit position. */ - -#define TWI_MASTER_WIF_bm 0x40 /* Write Interrupt Flag bit mask. */ -#define TWI_MASTER_WIF_bp 6 /* Write Interrupt Flag bit position. */ - -#define TWI_MASTER_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ -#define TWI_MASTER_CLKHOLD_bp 5 /* Clock Hold bit position. */ - -#define TWI_MASTER_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ -#define TWI_MASTER_RXACK_bp 4 /* Received Acknowledge bit position. */ - -#define TWI_MASTER_ARBLOST_bm 0x08 /* Arbitration Lost bit mask. */ -#define TWI_MASTER_ARBLOST_bp 3 /* Arbitration Lost bit position. */ - -#define TWI_MASTER_BUSERR_bm 0x04 /* Bus Error bit mask. */ -#define TWI_MASTER_BUSERR_bp 2 /* Bus Error bit position. */ - -#define TWI_MASTER_BUSSTATE_gm 0x03 /* Bus State group mask. */ -#define TWI_MASTER_BUSSTATE_gp 0 /* Bus State group position. */ -#define TWI_MASTER_BUSSTATE0_bm (1<<0) /* Bus State bit 0 mask. */ -#define TWI_MASTER_BUSSTATE0_bp 0 /* Bus State bit 0 position. */ -#define TWI_MASTER_BUSSTATE1_bm (1<<1) /* Bus State bit 1 mask. */ -#define TWI_MASTER_BUSSTATE1_bp 1 /* Bus State bit 1 position. */ - -/* TWI_SLAVE.CTRLA bit masks and bit positions */ -#define TWI_SLAVE_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ -#define TWI_SLAVE_INTLVL_gp 6 /* Interrupt Level group position. */ -#define TWI_SLAVE_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ -#define TWI_SLAVE_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ -#define TWI_SLAVE_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ -#define TWI_SLAVE_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ - -#define TWI_SLAVE_DIEN_bm 0x20 /* Data Interrupt Enable bit mask. */ -#define TWI_SLAVE_DIEN_bp 5 /* Data Interrupt Enable bit position. */ - -#define TWI_SLAVE_APIEN_bm 0x10 /* Address/Stop Interrupt Enable bit mask. */ -#define TWI_SLAVE_APIEN_bp 4 /* Address/Stop Interrupt Enable bit position. */ - -#define TWI_SLAVE_ENABLE_bm 0x08 /* Enable TWI Slave bit mask. */ -#define TWI_SLAVE_ENABLE_bp 3 /* Enable TWI Slave bit position. */ - -#define TWI_SLAVE_PIEN_bm 0x04 /* Stop Interrupt Enable bit mask. */ -#define TWI_SLAVE_PIEN_bp 2 /* Stop Interrupt Enable bit position. */ - -#define TWI_SLAVE_PMEN_bm 0x02 /* Promiscuous Mode Enable bit mask. */ -#define TWI_SLAVE_PMEN_bp 1 /* Promiscuous Mode Enable bit position. */ - -#define TWI_SLAVE_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ -#define TWI_SLAVE_SMEN_bp 0 /* Smart Mode Enable bit position. */ - -/* TWI_SLAVE.CTRLB bit masks and bit positions */ -#define TWI_SLAVE_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ -#define TWI_SLAVE_ACKACT_bp 2 /* Acknowledge Action bit position. */ - -#define TWI_SLAVE_CMD_gm 0x03 /* Command group mask. */ -#define TWI_SLAVE_CMD_gp 0 /* Command group position. */ -#define TWI_SLAVE_CMD0_bm (1<<0) /* Command bit 0 mask. */ -#define TWI_SLAVE_CMD0_bp 0 /* Command bit 0 position. */ -#define TWI_SLAVE_CMD1_bm (1<<1) /* Command bit 1 mask. */ -#define TWI_SLAVE_CMD1_bp 1 /* Command bit 1 position. */ - -#define TWI_SLAVE_TTOUTEN_bm 0x10 /* Ttimeout Enable bit mask. */ -#define TWI_SLAVE_TTOUTEN_bp 4 /* Ttimeout Enable bit position. */ - -#define TWI_SLAVE_TOIE_bm 0x80 /* Timeout Interrupt Enable bit mask. */ -#define TWI_SLAVE_TOIE_bp 7 /* Timeout Interrupt Enable bit position. */ - -/* TWI_SLAVE.STATUS bit masks and bit positions */ -#define TWI_SLAVE_DIF_bm 0x80 /* Data Interrupt Flag bit mask. */ -#define TWI_SLAVE_DIF_bp 7 /* Data Interrupt Flag bit position. */ - -#define TWI_SLAVE_APIF_bm 0x40 /* Address/Stop Interrupt Flag bit mask. */ -#define TWI_SLAVE_APIF_bp 6 /* Address/Stop Interrupt Flag bit position. */ - -#define TWI_SLAVE_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ -#define TWI_SLAVE_CLKHOLD_bp 5 /* Clock Hold bit position. */ - -#define TWI_SLAVE_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ -#define TWI_SLAVE_RXACK_bp 4 /* Received Acknowledge bit position. */ - -#define TWI_SLAVE_COLL_bm 0x08 /* Collision bit mask. */ -#define TWI_SLAVE_COLL_bp 3 /* Collision bit position. */ - -#define TWI_SLAVE_BUSERR_bm 0x04 /* Bus Error bit mask. */ -#define TWI_SLAVE_BUSERR_bp 2 /* Bus Error bit position. */ - -#define TWI_SLAVE_DIR_bm 0x02 /* Read/Write Direction bit mask. */ -#define TWI_SLAVE_DIR_bp 1 /* Read/Write Direction bit position. */ - -#define TWI_SLAVE_AP_bm 0x01 /* Slave Address or Stop bit mask. */ -#define TWI_SLAVE_AP_bp 0 /* Slave Address or Stop bit position. */ - -/* TWI_SLAVE.ADDRMASK bit masks and bit positions */ -#define TWI_SLAVE_ADDRMASK_gm 0xFE /* Address Mask group mask. */ -#define TWI_SLAVE_ADDRMASK_gp 1 /* Address Mask group position. */ -#define TWI_SLAVE_ADDRMASK0_bm (1<<1) /* Address Mask bit 0 mask. */ -#define TWI_SLAVE_ADDRMASK0_bp 1 /* Address Mask bit 0 position. */ -#define TWI_SLAVE_ADDRMASK1_bm (1<<2) /* Address Mask bit 1 mask. */ -#define TWI_SLAVE_ADDRMASK1_bp 2 /* Address Mask bit 1 position. */ -#define TWI_SLAVE_ADDRMASK2_bm (1<<3) /* Address Mask bit 2 mask. */ -#define TWI_SLAVE_ADDRMASK2_bp 3 /* Address Mask bit 2 position. */ -#define TWI_SLAVE_ADDRMASK3_bm (1<<4) /* Address Mask bit 3 mask. */ -#define TWI_SLAVE_ADDRMASK3_bp 4 /* Address Mask bit 3 position. */ -#define TWI_SLAVE_ADDRMASK4_bm (1<<5) /* Address Mask bit 4 mask. */ -#define TWI_SLAVE_ADDRMASK4_bp 5 /* Address Mask bit 4 position. */ -#define TWI_SLAVE_ADDRMASK5_bm (1<<6) /* Address Mask bit 5 mask. */ -#define TWI_SLAVE_ADDRMASK5_bp 6 /* Address Mask bit 5 position. */ -#define TWI_SLAVE_ADDRMASK6_bm (1<<7) /* Address Mask bit 6 mask. */ -#define TWI_SLAVE_ADDRMASK6_bp 7 /* Address Mask bit 6 position. */ - -#define TWI_SLAVE_ADDREN_bm 0x01 /* Address Enable bit mask. */ -#define TWI_SLAVE_ADDREN_bp 0 /* Address Enable bit position. */ - -/* TWI_TIMEOUT.TOS bit masks and bit positions */ -#define TWI_TIMEOUT_TTOUTMIF_bm 0x01 /* Master Ttimeout Interrupt Flag bit mask. */ -#define TWI_TIMEOUT_TTOUTMIF_bp 0 /* Master Ttimeout Interrupt Flag bit position. */ - -#define TWI_TIMEOUT_TSEXTIF_bm 0x02 /* Slave Extend Interrupt Flag bit mask. */ -#define TWI_TIMEOUT_TSEXTIF_bp 1 /* Slave Extend Interrupt Flag bit position. */ - -#define TWI_TIMEOUT_TMEXTIF_bm 0x04 /* Master Extend Interrupt Flag bit mask. */ -#define TWI_TIMEOUT_TMEXTIF_bp 2 /* Master Extend Interrupt Flag bit position. */ - -#define TWI_TIMEOUT_TTOUTSIF_bm 0x10 /* Slave Ttimeout Interrupt Flag bit mask. */ -#define TWI_TIMEOUT_TTOUTSIF_bp 4 /* Slave Ttimeout Interrupt Flag bit position. */ - -/* TWI_TIMEOUT.TOCONF bit masks and bit positions */ -#define TWI_TIMEOUT_TTOUTMSEL_gm 0x07 /* Master Ttimeout Select group mask. */ -#define TWI_TIMEOUT_TTOUTMSEL_gp 0 /* Master Ttimeout Select group position. */ -#define TWI_TIMEOUT_TTOUTMSEL0_bm (1<<0) /* Master Ttimeout Select bit 0 mask. */ -#define TWI_TIMEOUT_TTOUTMSEL0_bp 0 /* Master Ttimeout Select bit 0 position. */ -#define TWI_TIMEOUT_TTOUTMSEL1_bm (1<<1) /* Master Ttimeout Select bit 1 mask. */ -#define TWI_TIMEOUT_TTOUTMSEL1_bp 1 /* Master Ttimeout Select bit 1 position. */ -#define TWI_TIMEOUT_TTOUTMSEL2_bm (1<<2) /* Master Ttimeout Select bit 2 mask. */ -#define TWI_TIMEOUT_TTOUTMSEL2_bp 2 /* Master Ttimeout Select bit 2 position. */ - -#define TWI_TIMEOUT_TMSEXTSEL_gm 0x18 /* Master/Slave Timeout Select group mask. */ -#define TWI_TIMEOUT_TMSEXTSEL_gp 3 /* Master/Slave Timeout Select group position. */ -#define TWI_TIMEOUT_TMSEXTSEL0_bm (1<<3) /* Master/Slave Timeout Select bit 0 mask. */ -#define TWI_TIMEOUT_TMSEXTSEL0_bp 3 /* Master/Slave Timeout Select bit 0 position. */ -#define TWI_TIMEOUT_TMSEXTSEL1_bm (1<<4) /* Master/Slave Timeout Select bit 1 mask. */ -#define TWI_TIMEOUT_TMSEXTSEL1_bp 4 /* Master/Slave Timeout Select bit 1 position. */ - -#define TWI_TIMEOUT_TTOUTSSEL_gm 0xE0 /* Slave Ttimeout Select group mask. */ -#define TWI_TIMEOUT_TTOUTSSEL_gp 5 /* Slave Ttimeout Select group position. */ -#define TWI_TIMEOUT_TTOUTSSEL0_bm (1<<5) /* Slave Ttimeout Select bit 0 mask. */ -#define TWI_TIMEOUT_TTOUTSSEL0_bp 5 /* Slave Ttimeout Select bit 0 position. */ -#define TWI_TIMEOUT_TTOUTSSEL1_bm (1<<6) /* Slave Ttimeout Select bit 1 mask. */ -#define TWI_TIMEOUT_TTOUTSSEL1_bp 6 /* Slave Ttimeout Select bit 1 position. */ -#define TWI_TIMEOUT_TTOUTSSEL2_bm (1<<7) /* Slave Ttimeout Select bit 2 mask. */ -#define TWI_TIMEOUT_TTOUTSSEL2_bp 7 /* Slave Ttimeout Select bit 2 position. */ - -/* PORT - Port Configuration */ -/* PORT.INTCTRL bit masks and bit positions */ -#define PORT_INTLVL_gm 0x03 /* Port Interrupt Level group mask. */ -#define PORT_INTLVL_gp 0 /* Port Interrupt Level group position. */ -#define PORT_INTLVL0_bm (1<<0) /* Port Interrupt Level bit 0 mask. */ -#define PORT_INTLVL0_bp 0 /* Port Interrupt Level bit 0 position. */ -#define PORT_INTLVL1_bm (1<<1) /* Port Interrupt Level bit 1 mask. */ -#define PORT_INTLVL1_bp 1 /* Port Interrupt Level bit 1 position. */ - -/* PORT.INTFLAGS bit masks and bit positions */ -#define PORT_INT7IF_bm 0x80 /* Pin 7 Interrupt Flag bit mask. */ -#define PORT_INT7IF_bp 7 /* Pin 7 Interrupt Flag bit position. */ - -#define PORT_INT6IF_bm 0x40 /* Pin 6 Interrupt Flag bit mask. */ -#define PORT_INT6IF_bp 6 /* Pin 6 Interrupt Flag bit position. */ - -#define PORT_INT5IF_bm 0x20 /* Pin 5 Interrupt Flag bit mask. */ -#define PORT_INT5IF_bp 5 /* Pin 5 Interrupt Flag bit position. */ - -#define PORT_INT4IF_bm 0x10 /* Pin 4 Interrupt Flag bit mask. */ -#define PORT_INT4IF_bp 4 /* Pin 4 Interrupt Flag bit position. */ - -#define PORT_INT3IF_bm 0x08 /* Pin 3 Interrupt Flag bit mask. */ -#define PORT_INT3IF_bp 3 /* Pin 3 Interrupt Flag bit position. */ - -#define PORT_INT2IF_bm 0x04 /* Pin 2 Interrupt Flag bit mask. */ -#define PORT_INT2IF_bp 2 /* Pin 2 Interrupt Flag bit position. */ - -#define PORT_INT1IF_bm 0x02 /* Pin 1 Interrupt Flag bit mask. */ -#define PORT_INT1IF_bp 1 /* Pin 1 Interrupt Flag bit position. */ - -#define PORT_INT0IF_bm 0x01 /* Pin 0 Interrupt Flag bit mask. */ -#define PORT_INT0IF_bp 0 /* Pin 0 Interrupt Flag bit position. */ - -/* PORT.REMAP bit masks and bit positions */ -#define PORT_USART0_bm 0x10 /* Usart0 bit mask. */ -#define PORT_USART0_bp 4 /* Usart0 bit position. */ - -#define PORT_TC4D_bm 0x08 /* Timer/Counter 4 Output Compare D bit mask. */ -#define PORT_TC4D_bp 3 /* Timer/Counter 4 Output Compare D bit position. */ - -#define PORT_TC4C_bm 0x04 /* Timer/Counter 4 Output Compare C bit mask. */ -#define PORT_TC4C_bp 2 /* Timer/Counter 4 Output Compare C bit position. */ - -#define PORT_TC4B_bm 0x02 /* Timer/Counter 4 Output Compare B bit mask. */ -#define PORT_TC4B_bp 1 /* Timer/Counter 4 Output Compare B bit position. */ - -#define PORT_TC4A_bm 0x01 /* Timer/Counter 4 Output Compare A bit mask. */ -#define PORT_TC4A_bp 0 /* Timer/Counter 4 Output Compare A bit position. */ - -/* PORT.PIN0CTRL bit masks and bit positions */ -#define PORT_INVEN_bm 0x40 /* Inverted I/O Enable bit mask. */ -#define PORT_INVEN_bp 6 /* Inverted I/O Enable bit position. */ - -#define PORT_OPC_gm 0x38 /* Output/Pull Configuration group mask. */ -#define PORT_OPC_gp 3 /* Output/Pull Configuration group position. */ -#define PORT_OPC0_bm (1<<3) /* Output/Pull Configuration bit 0 mask. */ -#define PORT_OPC0_bp 3 /* Output/Pull Configuration bit 0 position. */ -#define PORT_OPC1_bm (1<<4) /* Output/Pull Configuration bit 1 mask. */ -#define PORT_OPC1_bp 4 /* Output/Pull Configuration bit 1 position. */ -#define PORT_OPC2_bm (1<<5) /* Output/Pull Configuration bit 2 mask. */ -#define PORT_OPC2_bp 5 /* Output/Pull Configuration bit 2 position. */ - -#define PORT_ISC_gm 0x07 /* Input/Sense Configuration group mask. */ -#define PORT_ISC_gp 0 /* Input/Sense Configuration group position. */ -#define PORT_ISC0_bm (1<<0) /* Input/Sense Configuration bit 0 mask. */ -#define PORT_ISC0_bp 0 /* Input/Sense Configuration bit 0 position. */ -#define PORT_ISC1_bm (1<<1) /* Input/Sense Configuration bit 1 mask. */ -#define PORT_ISC1_bp 1 /* Input/Sense Configuration bit 1 position. */ -#define PORT_ISC2_bm (1<<2) /* Input/Sense Configuration bit 2 mask. */ -#define PORT_ISC2_bp 2 /* Input/Sense Configuration bit 2 position. */ - -/* PORT.PIN1CTRL bit masks and bit positions */ -/* PORT_INVEN Predefined. */ -/* PORT_INVEN Predefined. */ - -/* PORT_OPC Predefined. */ -/* PORT_OPC Predefined. */ - -/* PORT_ISC Predefined. */ -/* PORT_ISC Predefined. */ - -/* PORT.PIN2CTRL bit masks and bit positions */ -/* PORT_INVEN Predefined. */ -/* PORT_INVEN Predefined. */ - -/* PORT_OPC Predefined. */ -/* PORT_OPC Predefined. */ - -/* PORT_ISC Predefined. */ -/* PORT_ISC Predefined. */ - -/* PORT.PIN3CTRL bit masks and bit positions */ -/* PORT_INVEN Predefined. */ -/* PORT_INVEN Predefined. */ - -/* PORT_OPC Predefined. */ -/* PORT_OPC Predefined. */ - -/* PORT_ISC Predefined. */ -/* PORT_ISC Predefined. */ - -/* PORT.PIN4CTRL bit masks and bit positions */ -/* PORT_INVEN Predefined. */ -/* PORT_INVEN Predefined. */ - -/* PORT_OPC Predefined. */ -/* PORT_OPC Predefined. */ - -/* PORT_ISC Predefined. */ -/* PORT_ISC Predefined. */ - -/* PORT.PIN5CTRL bit masks and bit positions */ -/* PORT_INVEN Predefined. */ -/* PORT_INVEN Predefined. */ - -/* PORT_OPC Predefined. */ -/* PORT_OPC Predefined. */ - -/* PORT_ISC Predefined. */ -/* PORT_ISC Predefined. */ - -/* PORT.PIN6CTRL bit masks and bit positions */ -/* PORT_INVEN Predefined. */ -/* PORT_INVEN Predefined. */ - -/* PORT_OPC Predefined. */ -/* PORT_OPC Predefined. */ - -/* PORT_ISC Predefined. */ -/* PORT_ISC Predefined. */ - -/* PORT.PIN7CTRL bit masks and bit positions */ -/* PORT_INVEN Predefined. */ -/* PORT_INVEN Predefined. */ - -/* PORT_OPC Predefined. */ -/* PORT_OPC Predefined. */ - -/* PORT_ISC Predefined. */ -/* PORT_ISC Predefined. */ - -/* TC - 16-bit Timer/Counter With PWM */ -/* TC4.CTRLA bit masks and bit positions */ -#define TC4_SYNCHEN_bm 0x40 /* Synchronization Enabled bit mask. */ -#define TC4_SYNCHEN_bp 6 /* Synchronization Enabled bit position. */ - -#define TC4_EVSTART_bm 0x20 /* Start on Next Event bit mask. */ -#define TC4_EVSTART_bp 5 /* Start on Next Event bit position. */ - -#define TC4_UPSTOP_bm 0x10 /* Stop on Next Update bit mask. */ -#define TC4_UPSTOP_bp 4 /* Stop on Next Update bit position. */ - -#define TC4_CLKSEL_gm 0x0F /* Clock Select group mask. */ -#define TC4_CLKSEL_gp 0 /* Clock Select group position. */ -#define TC4_CLKSEL0_bm (1<<0) /* Clock Select bit 0 mask. */ -#define TC4_CLKSEL0_bp 0 /* Clock Select bit 0 position. */ -#define TC4_CLKSEL1_bm (1<<1) /* Clock Select bit 1 mask. */ -#define TC4_CLKSEL1_bp 1 /* Clock Select bit 1 position. */ -#define TC4_CLKSEL2_bm (1<<2) /* Clock Select bit 2 mask. */ -#define TC4_CLKSEL2_bp 2 /* Clock Select bit 2 position. */ -#define TC4_CLKSEL3_bm (1<<3) /* Clock Select bit 3 mask. */ -#define TC4_CLKSEL3_bp 3 /* Clock Select bit 3 position. */ - -/* TC4.CTRLB bit masks and bit positions */ -#define TC4_BYTEM_gm 0xC0 /* Byte Mode group mask. */ -#define TC4_BYTEM_gp 6 /* Byte Mode group position. */ -#define TC4_BYTEM0_bm (1<<6) /* Byte Mode bit 0 mask. */ -#define TC4_BYTEM0_bp 6 /* Byte Mode bit 0 position. */ -#define TC4_BYTEM1_bm (1<<7) /* Byte Mode bit 1 mask. */ -#define TC4_BYTEM1_bp 7 /* Byte Mode bit 1 position. */ - -#define TC4_CIRCEN_gm 0x30 /* Circular Buffer Enable group mask. */ -#define TC4_CIRCEN_gp 4 /* Circular Buffer Enable group position. */ -#define TC4_CIRCEN0_bm (1<<4) /* Circular Buffer Enable bit 0 mask. */ -#define TC4_CIRCEN0_bp 4 /* Circular Buffer Enable bit 0 position. */ -#define TC4_CIRCEN1_bm (1<<5) /* Circular Buffer Enable bit 1 mask. */ -#define TC4_CIRCEN1_bp 5 /* Circular Buffer Enable bit 1 position. */ - -#define TC4_WGMODE_gm 0x07 /* Waveform Generation Mode group mask. */ -#define TC4_WGMODE_gp 0 /* Waveform Generation Mode group position. */ -#define TC4_WGMODE0_bm (1<<0) /* Waveform Generation Mode bit 0 mask. */ -#define TC4_WGMODE0_bp 0 /* Waveform Generation Mode bit 0 position. */ -#define TC4_WGMODE1_bm (1<<1) /* Waveform Generation Mode bit 1 mask. */ -#define TC4_WGMODE1_bp 1 /* Waveform Generation Mode bit 1 position. */ -#define TC4_WGMODE2_bm (1<<2) /* Waveform Generation Mode bit 2 mask. */ -#define TC4_WGMODE2_bp 2 /* Waveform Generation Mode bit 2 position. */ - -/* TC4.CTRLC bit masks and bit positions */ -#define TC4_POLD_bm 0x80 /* Channel D Output Polarity bit mask. */ -#define TC4_POLD_bp 7 /* Channel D Output Polarity bit position. */ - -#define TC4_POLC_bm 0x40 /* Channel C Output Polarity bit mask. */ -#define TC4_POLC_bp 6 /* Channel C Output Polarity bit position. */ - -#define TC4_POLB_bm 0x20 /* Channel B Output Polarity bit mask. */ -#define TC4_POLB_bp 5 /* Channel B Output Polarity bit position. */ - -#define TC4_POLA_bm 0x10 /* Channel A Output Polarity bit mask. */ -#define TC4_POLA_bp 4 /* Channel A Output Polarity bit position. */ - -#define TC4_CMPD_bm 0x08 /* Channel D Compare Output Value bit mask. */ -#define TC4_CMPD_bp 3 /* Channel D Compare Output Value bit position. */ - -#define TC4_CMPC_bm 0x04 /* Channel C Compare Output Value bit mask. */ -#define TC4_CMPC_bp 2 /* Channel C Compare Output Value bit position. */ - -#define TC4_CMPB_bm 0x02 /* Channel B Compare Output Value bit mask. */ -#define TC4_CMPB_bp 1 /* Channel B Compare Output Value bit position. */ - -#define TC4_CMPA_bm 0x01 /* Channel A Compare Output Value bit mask. */ -#define TC4_CMPA_bp 0 /* Channel A Compare Output Value bit position. */ - -#define TC4_HCMPD_bm 0x80 /* High Channel D Compare Output Value bit mask. */ -#define TC4_HCMPD_bp 7 /* High Channel D Compare Output Value bit position. */ - -#define TC4_HCMPC_bm 0x40 /* High Channel C Compare Output Value bit mask. */ -#define TC4_HCMPC_bp 6 /* High Channel C Compare Output Value bit position. */ - -#define TC4_HCMPB_bm 0x20 /* High Channel B Compare Output Value bit mask. */ -#define TC4_HCMPB_bp 5 /* High Channel B Compare Output Value bit position. */ - -#define TC4_HCMPA_bm 0x10 /* High Channel A Compare Output Value bit mask. */ -#define TC4_HCMPA_bp 4 /* High Channel A Compare Output Value bit position. */ - -#define TC4_LCMPD_bm 0x08 /* Low Channel D Compare Output Value bit mask. */ -#define TC4_LCMPD_bp 3 /* Low Channel D Compare Output Value bit position. */ - -#define TC4_LCMPC_bm 0x04 /* Low Channel C Compare Output Value bit mask. */ -#define TC4_LCMPC_bp 2 /* Low Channel C Compare Output Value bit position. */ - -#define TC4_LCMPB_bm 0x02 /* Low Channel B Compare Output Value bit mask. */ -#define TC4_LCMPB_bp 1 /* Low Channel B Compare Output Value bit position. */ - -#define TC4_LCMPA_bm 0x01 /* Low Channel A Compare Output Value bit mask. */ -#define TC4_LCMPA_bp 0 /* Low Channel A Compare Output Value bit position. */ - -/* TC4.CTRLD bit masks and bit positions */ -#define TC4_EVACT_gm 0xE0 /* Event Action group mask. */ -#define TC4_EVACT_gp 5 /* Event Action group position. */ -#define TC4_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ -#define TC4_EVACT0_bp 5 /* Event Action bit 0 position. */ -#define TC4_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ -#define TC4_EVACT1_bp 6 /* Event Action bit 1 position. */ -#define TC4_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ -#define TC4_EVACT2_bp 7 /* Event Action bit 2 position. */ - -#define TC4_EVDLY_bm 0x10 /* Event Delay bit mask. */ -#define TC4_EVDLY_bp 4 /* Event Delay bit position. */ - -#define TC4_EVSEL_gm 0x0F /* Event Source Select group mask. */ -#define TC4_EVSEL_gp 0 /* Event Source Select group position. */ -#define TC4_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ -#define TC4_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ -#define TC4_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ -#define TC4_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ -#define TC4_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ -#define TC4_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ -#define TC4_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ -#define TC4_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ - -/* TC4.CTRLE bit masks and bit positions */ -#define TC4_CCDMODE_gm 0xC0 /* Channel D Compare or Capture Mode group mask. */ -#define TC4_CCDMODE_gp 6 /* Channel D Compare or Capture Mode group position. */ -#define TC4_CCDMODE0_bm (1<<6) /* Channel D Compare or Capture Mode bit 0 mask. */ -#define TC4_CCDMODE0_bp 6 /* Channel D Compare or Capture Mode bit 0 position. */ -#define TC4_CCDMODE1_bm (1<<7) /* Channel D Compare or Capture Mode bit 1 mask. */ -#define TC4_CCDMODE1_bp 7 /* Channel D Compare or Capture Mode bit 1 position. */ - -#define TC4_CCCMODE_gm 0x30 /* Channel C Compare or Capture Mode group mask. */ -#define TC4_CCCMODE_gp 4 /* Channel C Compare or Capture Mode group position. */ -#define TC4_CCCMODE0_bm (1<<4) /* Channel C Compare or Capture Mode bit 0 mask. */ -#define TC4_CCCMODE0_bp 4 /* Channel C Compare or Capture Mode bit 0 position. */ -#define TC4_CCCMODE1_bm (1<<5) /* Channel C Compare or Capture Mode bit 1 mask. */ -#define TC4_CCCMODE1_bp 5 /* Channel C Compare or Capture Mode bit 1 position. */ - -#define TC4_CCBMODE_gm 0x0C /* Channel B Compare or Capture Mode group mask. */ -#define TC4_CCBMODE_gp 2 /* Channel B Compare or Capture Mode group position. */ -#define TC4_CCBMODE0_bm (1<<2) /* Channel B Compare or Capture Mode bit 0 mask. */ -#define TC4_CCBMODE0_bp 2 /* Channel B Compare or Capture Mode bit 0 position. */ -#define TC4_CCBMODE1_bm (1<<3) /* Channel B Compare or Capture Mode bit 1 mask. */ -#define TC4_CCBMODE1_bp 3 /* Channel B Compare or Capture Mode bit 1 position. */ - -#define TC4_CCAMODE_gm 0x03 /* Channel A Compare or Capture Mode group mask. */ -#define TC4_CCAMODE_gp 0 /* Channel A Compare or Capture Mode group position. */ -#define TC4_CCAMODE0_bm (1<<0) /* Channel A Compare or Capture Mode bit 0 mask. */ -#define TC4_CCAMODE0_bp 0 /* Channel A Compare or Capture Mode bit 0 position. */ -#define TC4_CCAMODE1_bm (1<<1) /* Channel A Compare or Capture Mode bit 1 mask. */ -#define TC4_CCAMODE1_bp 1 /* Channel A Compare or Capture Mode bit 1 position. */ - -#define TC4_LCCDMODE_gm 0xC0 /* Channel Low D Compare or Capture Mode group mask. */ -#define TC4_LCCDMODE_gp 6 /* Channel Low D Compare or Capture Mode group position. */ -#define TC4_LCCDMODE0_bm (1<<6) /* Channel Low D Compare or Capture Mode bit 0 mask. */ -#define TC4_LCCDMODE0_bp 6 /* Channel Low D Compare or Capture Mode bit 0 position. */ -#define TC4_LCCDMODE1_bm (1<<7) /* Channel Low D Compare or Capture Mode bit 1 mask. */ -#define TC4_LCCDMODE1_bp 7 /* Channel Low D Compare or Capture Mode bit 1 position. */ - -#define TC4_LCCCMODE_gm 0x30 /* Channel Low C Compare or Capture Mode group mask. */ -#define TC4_LCCCMODE_gp 4 /* Channel Low C Compare or Capture Mode group position. */ -#define TC4_LCCCMODE0_bm (1<<4) /* Channel Low C Compare or Capture Mode bit 0 mask. */ -#define TC4_LCCCMODE0_bp 4 /* Channel Low C Compare or Capture Mode bit 0 position. */ -#define TC4_LCCCMODE1_bm (1<<5) /* Channel Low C Compare or Capture Mode bit 1 mask. */ -#define TC4_LCCCMODE1_bp 5 /* Channel Low C Compare or Capture Mode bit 1 position. */ - -#define TC4_LCCBMODE_gm 0x0C /* Channel Low B Compare or Capture Mode group mask. */ -#define TC4_LCCBMODE_gp 2 /* Channel Low B Compare or Capture Mode group position. */ -#define TC4_LCCBMODE0_bm (1<<2) /* Channel Low B Compare or Capture Mode bit 0 mask. */ -#define TC4_LCCBMODE0_bp 2 /* Channel Low B Compare or Capture Mode bit 0 position. */ -#define TC4_LCCBMODE1_bm (1<<3) /* Channel Low B Compare or Capture Mode bit 1 mask. */ -#define TC4_LCCBMODE1_bp 3 /* Channel Low B Compare or Capture Mode bit 1 position. */ - -#define TC4_LCCAMODE_gm 0x03 /* Channel Low A Compare or Capture Mode group mask. */ -#define TC4_LCCAMODE_gp 0 /* Channel Low A Compare or Capture Mode group position. */ -#define TC4_LCCAMODE0_bm (1<<0) /* Channel Low A Compare or Capture Mode bit 0 mask. */ -#define TC4_LCCAMODE0_bp 0 /* Channel Low A Compare or Capture Mode bit 0 position. */ -#define TC4_LCCAMODE1_bm (1<<1) /* Channel Low A Compare or Capture Mode bit 1 mask. */ -#define TC4_LCCAMODE1_bp 1 /* Channel Low A Compare or Capture Mode bit 1 position. */ - -/* TC4.CTRLF bit masks and bit positions */ -#define TC4_HCCDMODE_gm 0xC0 /* Channel High D Compare or Capture Mode group mask. */ -#define TC4_HCCDMODE_gp 6 /* Channel High D Compare or Capture Mode group position. */ -#define TC4_HCCDMODE0_bm (1<<6) /* Channel High D Compare or Capture Mode bit 0 mask. */ -#define TC4_HCCDMODE0_bp 6 /* Channel High D Compare or Capture Mode bit 0 position. */ -#define TC4_HCCDMODE1_bm (1<<7) /* Channel High D Compare or Capture Mode bit 1 mask. */ -#define TC4_HCCDMODE1_bp 7 /* Channel High D Compare or Capture Mode bit 1 position. */ - -#define TC4_HCCCMODE_gm 0x30 /* Channel High C Compare or Capture Mode group mask. */ -#define TC4_HCCCMODE_gp 4 /* Channel High C Compare or Capture Mode group position. */ -#define TC4_HCCCMODE0_bm (1<<4) /* Channel High C Compare or Capture Mode bit 0 mask. */ -#define TC4_HCCCMODE0_bp 4 /* Channel High C Compare or Capture Mode bit 0 position. */ -#define TC4_HCCCMODE1_bm (1<<5) /* Channel High C Compare or Capture Mode bit 1 mask. */ -#define TC4_HCCCMODE1_bp 5 /* Channel High C Compare or Capture Mode bit 1 position. */ - -#define TC4_HCCBMODE_gm 0x0C /* Channel High B Compare or Capture Mode group mask. */ -#define TC4_HCCBMODE_gp 2 /* Channel High B Compare or Capture Mode group position. */ -#define TC4_HCCBMODE0_bm (1<<2) /* Channel High B Compare or Capture Mode bit 0 mask. */ -#define TC4_HCCBMODE0_bp 2 /* Channel High B Compare or Capture Mode bit 0 position. */ -#define TC4_HCCBMODE1_bm (1<<3) /* Channel High B Compare or Capture Mode bit 1 mask. */ -#define TC4_HCCBMODE1_bp 3 /* Channel High B Compare or Capture Mode bit 1 position. */ - -#define TC4_HCCAMODE_gm 0x03 /* Channel High A Compare or Capture Mode group mask. */ -#define TC4_HCCAMODE_gp 0 /* Channel High A Compare or Capture Mode group position. */ -#define TC4_HCCAMODE0_bm (1<<0) /* Channel High A Compare or Capture Mode bit 0 mask. */ -#define TC4_HCCAMODE0_bp 0 /* Channel High A Compare or Capture Mode bit 0 position. */ -#define TC4_HCCAMODE1_bm (1<<1) /* Channel High A Compare or Capture Mode bit 1 mask. */ -#define TC4_HCCAMODE1_bp 1 /* Channel High A Compare or Capture Mode bit 1 position. */ - -/* TC4.INTCTRLA bit masks and bit positions */ -#define TC4_TRGINTLVL_gm 0x30 /* Timer Trigger Restart Interrupt Level group mask. */ -#define TC4_TRGINTLVL_gp 4 /* Timer Trigger Restart Interrupt Level group position. */ -#define TC4_TRGINTLVL0_bm (1<<4) /* Timer Trigger Restart Interrupt Level bit 0 mask. */ -#define TC4_TRGINTLVL0_bp 4 /* Timer Trigger Restart Interrupt Level bit 0 position. */ -#define TC4_TRGINTLVL1_bm (1<<5) /* Timer Trigger Restart Interrupt Level bit 1 mask. */ -#define TC4_TRGINTLVL1_bp 5 /* Timer Trigger Restart Interrupt Level bit 1 position. */ - -#define TC4_ERRINTLVL_gm 0x0C /* Timer Error Interrupt Level group mask. */ -#define TC4_ERRINTLVL_gp 2 /* Timer Error Interrupt Level group position. */ -#define TC4_ERRINTLVL0_bm (1<<2) /* Timer Error Interrupt Level bit 0 mask. */ -#define TC4_ERRINTLVL0_bp 2 /* Timer Error Interrupt Level bit 0 position. */ -#define TC4_ERRINTLVL1_bm (1<<3) /* Timer Error Interrupt Level bit 1 mask. */ -#define TC4_ERRINTLVL1_bp 3 /* Timer Error Interrupt Level bit 1 position. */ - -#define TC4_OVFINTLVL_gm 0x03 /* Timer Overflow/Underflow Interrupt Level group mask. */ -#define TC4_OVFINTLVL_gp 0 /* Timer Overflow/Underflow Interrupt Level group position. */ -#define TC4_OVFINTLVL0_bm (1<<0) /* Timer Overflow/Underflow Interrupt Level bit 0 mask. */ -#define TC4_OVFINTLVL0_bp 0 /* Timer Overflow/Underflow Interrupt Level bit 0 position. */ -#define TC4_OVFINTLVL1_bm (1<<1) /* Timer Overflow/Underflow Interrupt Level bit 1 mask. */ -#define TC4_OVFINTLVL1_bp 1 /* Timer Overflow/Underflow Interrupt Level bit 1 position. */ - -/* TC4.INTCTRLB bit masks and bit positions */ -#define TC4_CCDINTLVL_gm 0xC0 /* Channel D Compare or Capture Interrupt Level group mask. */ -#define TC4_CCDINTLVL_gp 6 /* Channel D Compare or Capture Interrupt Level group position. */ -#define TC4_CCDINTLVL0_bm (1<<6) /* Channel D Compare or Capture Interrupt Level bit 0 mask. */ -#define TC4_CCDINTLVL0_bp 6 /* Channel D Compare or Capture Interrupt Level bit 0 position. */ -#define TC4_CCDINTLVL1_bm (1<<7) /* Channel D Compare or Capture Interrupt Level bit 1 mask. */ -#define TC4_CCDINTLVL1_bp 7 /* Channel D Compare or Capture Interrupt Level bit 1 position. */ - -#define TC4_CCCINTLVL_gm 0x30 /* Channel C Compare or Capture Interrupt Level group mask. */ -#define TC4_CCCINTLVL_gp 4 /* Channel C Compare or Capture Interrupt Level group position. */ -#define TC4_CCCINTLVL0_bm (1<<4) /* Channel C Compare or Capture Interrupt Level bit 0 mask. */ -#define TC4_CCCINTLVL0_bp 4 /* Channel C Compare or Capture Interrupt Level bit 0 position. */ -#define TC4_CCCINTLVL1_bm (1<<5) /* Channel C Compare or Capture Interrupt Level bit 1 mask. */ -#define TC4_CCCINTLVL1_bp 5 /* Channel C Compare or Capture Interrupt Level bit 1 position. */ - -#define TC4_CCBINTLVL_gm 0x0C /* Channel B Compare or Capture Interrupt Level group mask. */ -#define TC4_CCBINTLVL_gp 2 /* Channel B Compare or Capture Interrupt Level group position. */ -#define TC4_CCBINTLVL0_bm (1<<2) /* Channel B Compare or Capture Interrupt Level bit 0 mask. */ -#define TC4_CCBINTLVL0_bp 2 /* Channel B Compare or Capture Interrupt Level bit 0 position. */ -#define TC4_CCBINTLVL1_bm (1<<3) /* Channel B Compare or Capture Interrupt Level bit 1 mask. */ -#define TC4_CCBINTLVL1_bp 3 /* Channel B Compare or Capture Interrupt Level bit 1 position. */ - -#define TC4_CCAINTLVL_gm 0x03 /* Channel A Compare or Capture Interrupt Level group mask. */ -#define TC4_CCAINTLVL_gp 0 /* Channel A Compare or Capture Interrupt Level group position. */ -#define TC4_CCAINTLVL0_bm (1<<0) /* Channel A Compare or Capture Interrupt Level bit 0 mask. */ -#define TC4_CCAINTLVL0_bp 0 /* Channel A Compare or Capture Interrupt Level bit 0 position. */ -#define TC4_CCAINTLVL1_bm (1<<1) /* Channel A Compare or Capture Interrupt Level bit 1 mask. */ -#define TC4_CCAINTLVL1_bp 1 /* Channel A Compare or Capture Interrupt Level bit 1 position. */ - -#define TC4_LCCDINTLVL_gm 0xC0 /* Channel Low D Compare or Capture Interrupt Level group mask. */ -#define TC4_LCCDINTLVL_gp 6 /* Channel Low D Compare or Capture Interrupt Level group position. */ -#define TC4_LCCDINTLVL0_bm (1<<6) /* Channel Low D Compare or Capture Interrupt Level bit 0 mask. */ -#define TC4_LCCDINTLVL0_bp 6 /* Channel Low D Compare or Capture Interrupt Level bit 0 position. */ -#define TC4_LCCDINTLVL1_bm (1<<7) /* Channel Low D Compare or Capture Interrupt Level bit 1 mask. */ -#define TC4_LCCDINTLVL1_bp 7 /* Channel Low D Compare or Capture Interrupt Level bit 1 position. */ - -#define TC4_LCCCINTLVL_gm 0x30 /* Channel Low C Compare or Capture Interrupt Level group mask. */ -#define TC4_LCCCINTLVL_gp 4 /* Channel Low C Compare or Capture Interrupt Level group position. */ -#define TC4_LCCCINTLVL0_bm (1<<4) /* Channel Low C Compare or Capture Interrupt Level bit 0 mask. */ -#define TC4_LCCCINTLVL0_bp 4 /* Channel Low C Compare or Capture Interrupt Level bit 0 position. */ -#define TC4_LCCCINTLVL1_bm (1<<5) /* Channel Low C Compare or Capture Interrupt Level bit 1 mask. */ -#define TC4_LCCCINTLVL1_bp 5 /* Channel Low C Compare or Capture Interrupt Level bit 1 position. */ - -#define TC4_LCCBINTLVL_gm 0x0C /* Channel Low B Compare or Capture Interrupt Level group mask. */ -#define TC4_LCCBINTLVL_gp 2 /* Channel Low B Compare or Capture Interrupt Level group position. */ -#define TC4_LCCBINTLVL0_bm (1<<2) /* Channel Low B Compare or Capture Interrupt Level bit 0 mask. */ -#define TC4_LCCBINTLVL0_bp 2 /* Channel Low B Compare or Capture Interrupt Level bit 0 position. */ -#define TC4_LCCBINTLVL1_bm (1<<3) /* Channel Low B Compare or Capture Interrupt Level bit 1 mask. */ -#define TC4_LCCBINTLVL1_bp 3 /* Channel Low B Compare or Capture Interrupt Level bit 1 position. */ - -#define TC4_LCCAINTLVL_gm 0x03 /* Channel Low A Compare or Capture Interrupt Level group mask. */ -#define TC4_LCCAINTLVL_gp 0 /* Channel Low A Compare or Capture Interrupt Level group position. */ -#define TC4_LCCAINTLVL0_bm (1<<0) /* Channel Low A Compare or Capture Interrupt Level bit 0 mask. */ -#define TC4_LCCAINTLVL0_bp 0 /* Channel Low A Compare or Capture Interrupt Level bit 0 position. */ -#define TC4_LCCAINTLVL1_bm (1<<1) /* Channel Low A Compare or Capture Interrupt Level bit 1 mask. */ -#define TC4_LCCAINTLVL1_bp 1 /* Channel Low A Compare or Capture Interrupt Level bit 1 position. */ - -/* TC4.CTRLGCLR bit masks and bit positions */ -#define TC4_STOP_bm 0x20 /* Timer/Counter Stop bit mask. */ -#define TC4_STOP_bp 5 /* Timer/Counter Stop bit position. */ - -#define TC4_CMD_gm 0x0C /* Command group mask. */ -#define TC4_CMD_gp 2 /* Command group position. */ -#define TC4_CMD0_bm (1<<2) /* Command bit 0 mask. */ -#define TC4_CMD0_bp 2 /* Command bit 0 position. */ -#define TC4_CMD1_bm (1<<3) /* Command bit 1 mask. */ -#define TC4_CMD1_bp 3 /* Command bit 1 position. */ - -#define TC4_LUPD_bm 0x02 /* Lock Update bit mask. */ -#define TC4_LUPD_bp 1 /* Lock Update bit position. */ - -#define TC4_DIR_bm 0x01 /* Counter Direction bit mask. */ -#define TC4_DIR_bp 0 /* Counter Direction bit position. */ - -/* TC4.CTRLGSET bit masks and bit positions */ -/* TC4_STOP Predefined. */ -/* TC4_STOP Predefined. */ - -/* TC4_CMD Predefined. */ -/* TC4_CMD Predefined. */ - -/* TC4_LUPD Predefined. */ -/* TC4_LUPD Predefined. */ - -/* TC4_DIR Predefined. */ -/* TC4_DIR Predefined. */ - -/* TC4.CTRLHCLR bit masks and bit positions */ -#define TC4_CCDBV_bm 0x10 /* Channel D Compare or Capture Buffer Valid bit mask. */ -#define TC4_CCDBV_bp 4 /* Channel D Compare or Capture Buffer Valid bit position. */ - -#define TC4_CCCBV_bm 0x08 /* Channel C Compare or Capture Buffer Valid bit mask. */ -#define TC4_CCCBV_bp 3 /* Channel C Compare or Capture Buffer Valid bit position. */ - -#define TC4_CCBBV_bm 0x04 /* Channel B Compare or Capture Buffer Valid bit mask. */ -#define TC4_CCBBV_bp 2 /* Channel B Compare or Capture Buffer Valid bit position. */ - -#define TC4_CCABV_bm 0x02 /* Channel A Compare or Capture Buffer Valid bit mask. */ -#define TC4_CCABV_bp 1 /* Channel A Compare or Capture Buffer Valid bit position. */ - -#define TC4_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ -#define TC4_PERBV_bp 0 /* Period Buffer Valid bit position. */ - -#define TC4_LCCDBV_bm 0x10 /* Channel Low D Compare or Capture Buffer Valid bit mask. */ -#define TC4_LCCDBV_bp 4 /* Channel Low D Compare or Capture Buffer Valid bit position. */ - -#define TC4_LCCCBV_bm 0x08 /* Channel Low C Compare or Capture Buffer Valid bit mask. */ -#define TC4_LCCCBV_bp 3 /* Channel Low C Compare or Capture Buffer Valid bit position. */ - -#define TC4_LCCBBV_bm 0x04 /* Channel Low B Compare or Capture Buffer Valid bit mask. */ -#define TC4_LCCBBV_bp 2 /* Channel Low B Compare or Capture Buffer Valid bit position. */ - -#define TC4_LCCABV_bm 0x02 /* Channel Low A Compare or Capture Buffer Valid bit mask. */ -#define TC4_LCCABV_bp 1 /* Channel Low A Compare or Capture Buffer Valid bit position. */ - -#define TC4_LPERBV_bm 0x01 /* Period Low Buffer Valid bit mask. */ -#define TC4_LPERBV_bp 0 /* Period Low Buffer Valid bit position. */ - -/* TC4.CTRLHSET bit masks and bit positions */ -/* TC4_CCDBV Predefined. */ -/* TC4_CCDBV Predefined. */ - -/* TC4_CCCBV Predefined. */ -/* TC4_CCCBV Predefined. */ - -/* TC4_CCBBV Predefined. */ -/* TC4_CCBBV Predefined. */ - -/* TC4_CCABV Predefined. */ -/* TC4_CCABV Predefined. */ - -/* TC4_PERBV Predefined. */ -/* TC4_PERBV Predefined. */ - -/* TC4_LCCDBV Predefined. */ -/* TC4_LCCDBV Predefined. */ - -/* TC4_LCCCBV Predefined. */ -/* TC4_LCCCBV Predefined. */ - -/* TC4_LCCBBV Predefined. */ -/* TC4_LCCBBV Predefined. */ - -/* TC4_LCCABV Predefined. */ -/* TC4_LCCABV Predefined. */ - -/* TC4_LPERBV Predefined. */ -/* TC4_LPERBV Predefined. */ - -/* TC4.INTFLAGS bit masks and bit positions */ -#define TC4_CCDIF_bm 0x80 /* Channel D Compare or Capture Interrupt Flag bit mask. */ -#define TC4_CCDIF_bp 7 /* Channel D Compare or Capture Interrupt Flag bit position. */ - -#define TC4_CCCIF_bm 0x40 /* Channel C Compare or Capture Interrupt Flag bit mask. */ -#define TC4_CCCIF_bp 6 /* Channel C Compare or Capture Interrupt Flag bit position. */ - -#define TC4_CCBIF_bm 0x20 /* Channel B Compare or Capture Interrupt Flag bit mask. */ -#define TC4_CCBIF_bp 5 /* Channel B Compare or Capture Interrupt Flag bit position. */ - -#define TC4_CCAIF_bm 0x10 /* Channel A Compare or Capture Interrupt Flag bit mask. */ -#define TC4_CCAIF_bp 4 /* Channel A Compare or Capture Interrupt Flag bit position. */ - -#define TC4_TRGIF_bm 0x04 /* Trigger Restart Interrupt Flag bit mask. */ -#define TC4_TRGIF_bp 2 /* Trigger Restart Interrupt Flag bit position. */ - -#define TC4_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ -#define TC4_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ - -#define TC4_OVFIF_bm 0x01 /* Overflow/Underflow Interrupt Flag bit mask. */ -#define TC4_OVFIF_bp 0 /* Overflow/Underflow Interrupt Flag bit position. */ - -#define TC4_LCCDIF_bm 0x80 /* Channel Low D Compare or Capture Interrupt Flag bit mask. */ -#define TC4_LCCDIF_bp 7 /* Channel Low D Compare or Capture Interrupt Flag bit position. */ - -#define TC4_LCCCIF_bm 0x40 /* Channel Low C Compare or Capture Interrupt Flag bit mask. */ -#define TC4_LCCCIF_bp 6 /* Channel Low C Compare or Capture Interrupt Flag bit position. */ - -#define TC4_LCCBIF_bm 0x20 /* Channel Low B Compare or Capture Interrupt Flag bit mask. */ -#define TC4_LCCBIF_bp 5 /* Channel Low B Compare or Capture Interrupt Flag bit position. */ - -#define TC4_LCCAIF_bm 0x10 /* Channel Low A Compare or Capture Interrupt Flag bit mask. */ -#define TC4_LCCAIF_bp 4 /* Channel Low A Compare or Capture Interrupt Flag bit position. */ - -/* TC5.CTRLA bit masks and bit positions */ -#define TC5_SYNCHEN_bm 0x40 /* Synchronization Enabled bit mask. */ -#define TC5_SYNCHEN_bp 6 /* Synchronization Enabled bit position. */ - -#define TC5_EVSTART_bm 0x20 /* Start on Next Event bit mask. */ -#define TC5_EVSTART_bp 5 /* Start on Next Event bit position. */ - -#define TC5_UPSTOP_bm 0x10 /* Stop on Next Update bit mask. */ -#define TC5_UPSTOP_bp 4 /* Stop on Next Update bit position. */ - -#define TC5_CLKSEL_gm 0x0F /* Clock Select group mask. */ -#define TC5_CLKSEL_gp 0 /* Clock Select group position. */ -#define TC5_CLKSEL0_bm (1<<0) /* Clock Select bit 0 mask. */ -#define TC5_CLKSEL0_bp 0 /* Clock Select bit 0 position. */ -#define TC5_CLKSEL1_bm (1<<1) /* Clock Select bit 1 mask. */ -#define TC5_CLKSEL1_bp 1 /* Clock Select bit 1 position. */ -#define TC5_CLKSEL2_bm (1<<2) /* Clock Select bit 2 mask. */ -#define TC5_CLKSEL2_bp 2 /* Clock Select bit 2 position. */ -#define TC5_CLKSEL3_bm (1<<3) /* Clock Select bit 3 mask. */ -#define TC5_CLKSEL3_bp 3 /* Clock Select bit 3 position. */ - -/* TC5.CTRLB bit masks and bit positions */ -#define TC5_BYTEM_gm 0xC0 /* Byte Mode group mask. */ -#define TC5_BYTEM_gp 6 /* Byte Mode group position. */ -#define TC5_BYTEM0_bm (1<<6) /* Byte Mode bit 0 mask. */ -#define TC5_BYTEM0_bp 6 /* Byte Mode bit 0 position. */ -#define TC5_BYTEM1_bm (1<<7) /* Byte Mode bit 1 mask. */ -#define TC5_BYTEM1_bp 7 /* Byte Mode bit 1 position. */ - -#define TC5_CIRCEN_gm 0x30 /* Circular Buffer Enable group mask. */ -#define TC5_CIRCEN_gp 4 /* Circular Buffer Enable group position. */ -#define TC5_CIRCEN0_bm (1<<4) /* Circular Buffer Enable bit 0 mask. */ -#define TC5_CIRCEN0_bp 4 /* Circular Buffer Enable bit 0 position. */ -#define TC5_CIRCEN1_bm (1<<5) /* Circular Buffer Enable bit 1 mask. */ -#define TC5_CIRCEN1_bp 5 /* Circular Buffer Enable bit 1 position. */ - -#define TC5_WGMODE_gm 0x07 /* Waveform Generation Mode group mask. */ -#define TC5_WGMODE_gp 0 /* Waveform Generation Mode group position. */ -#define TC5_WGMODE0_bm (1<<0) /* Waveform Generation Mode bit 0 mask. */ -#define TC5_WGMODE0_bp 0 /* Waveform Generation Mode bit 0 position. */ -#define TC5_WGMODE1_bm (1<<1) /* Waveform Generation Mode bit 1 mask. */ -#define TC5_WGMODE1_bp 1 /* Waveform Generation Mode bit 1 position. */ -#define TC5_WGMODE2_bm (1<<2) /* Waveform Generation Mode bit 2 mask. */ -#define TC5_WGMODE2_bp 2 /* Waveform Generation Mode bit 2 position. */ - -/* TC5.CTRLC bit masks and bit positions */ -#define TC5_POLB_bm 0x20 /* Channel B Output Polarity bit mask. */ -#define TC5_POLB_bp 5 /* Channel B Output Polarity bit position. */ - -#define TC5_POLA_bm 0x10 /* Channel A Output Polarity bit mask. */ -#define TC5_POLA_bp 4 /* Channel A Output Polarity bit position. */ - -#define TC5_CMPB_bm 0x02 /* Channel B Compare Output Value bit mask. */ -#define TC5_CMPB_bp 1 /* Channel B Compare Output Value bit position. */ - -#define TC5_CMPA_bm 0x01 /* Channel A Compare Output Value bit mask. */ -#define TC5_CMPA_bp 0 /* Channel A Compare Output Value bit position. */ - -#define TC5_HCMPB_bm 0x20 /* High Channel B Compare Output Value bit mask. */ -#define TC5_HCMPB_bp 5 /* High Channel B Compare Output Value bit position. */ - -#define TC5_HCMPA_bm 0x10 /* High Channel A Compare Output Value bit mask. */ -#define TC5_HCMPA_bp 4 /* High Channel A Compare Output Value bit position. */ - -#define TC5_LCMPB_bm 0x02 /* Low Channel B Compare Output Value bit mask. */ -#define TC5_LCMPB_bp 1 /* Low Channel B Compare Output Value bit position. */ - -#define TC5_LCMPA_bm 0x01 /* Low Channel A Compare Output Value bit mask. */ -#define TC5_LCMPA_bp 0 /* Low Channel A Compare Output Value bit position. */ - -/* TC5.CTRLD bit masks and bit positions */ -#define TC5_EVACT_gm 0xE0 /* Event Action group mask. */ -#define TC5_EVACT_gp 5 /* Event Action group position. */ -#define TC5_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ -#define TC5_EVACT0_bp 5 /* Event Action bit 0 position. */ -#define TC5_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ -#define TC5_EVACT1_bp 6 /* Event Action bit 1 position. */ -#define TC5_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ -#define TC5_EVACT2_bp 7 /* Event Action bit 2 position. */ - -#define TC5_EVDLY_bm 0x10 /* Event Delay bit mask. */ -#define TC5_EVDLY_bp 4 /* Event Delay bit position. */ - -#define TC5_EVSEL_gm 0x0F /* Event Source Select group mask. */ -#define TC5_EVSEL_gp 0 /* Event Source Select group position. */ -#define TC5_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ -#define TC5_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ -#define TC5_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ -#define TC5_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ -#define TC5_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ -#define TC5_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ -#define TC5_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ -#define TC5_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ - -/* TC5.CTRLE bit masks and bit positions */ -#define TC5_CCBMODE_gm 0x0C /* Channel B Compare or Capture Mode group mask. */ -#define TC5_CCBMODE_gp 2 /* Channel B Compare or Capture Mode group position. */ -#define TC5_CCBMODE0_bm (1<<2) /* Channel B Compare or Capture Mode bit 0 mask. */ -#define TC5_CCBMODE0_bp 2 /* Channel B Compare or Capture Mode bit 0 position. */ -#define TC5_CCBMODE1_bm (1<<3) /* Channel B Compare or Capture Mode bit 1 mask. */ -#define TC5_CCBMODE1_bp 3 /* Channel B Compare or Capture Mode bit 1 position. */ - -#define TC5_CCAMODE_gm 0x03 /* Channel A Compare or Capture Mode group mask. */ -#define TC5_CCAMODE_gp 0 /* Channel A Compare or Capture Mode group position. */ -#define TC5_CCAMODE0_bm (1<<0) /* Channel A Compare or Capture Mode bit 0 mask. */ -#define TC5_CCAMODE0_bp 0 /* Channel A Compare or Capture Mode bit 0 position. */ -#define TC5_CCAMODE1_bm (1<<1) /* Channel A Compare or Capture Mode bit 1 mask. */ -#define TC5_CCAMODE1_bp 1 /* Channel A Compare or Capture Mode bit 1 position. */ - -#define TC5_LCCBMODE_gm 0x0C /* Channel Low B Compare or Capture Mode group mask. */ -#define TC5_LCCBMODE_gp 2 /* Channel Low B Compare or Capture Mode group position. */ -#define TC5_LCCBMODE0_bm (1<<2) /* Channel Low B Compare or Capture Mode bit 0 mask. */ -#define TC5_LCCBMODE0_bp 2 /* Channel Low B Compare or Capture Mode bit 0 position. */ -#define TC5_LCCBMODE1_bm (1<<3) /* Channel Low B Compare or Capture Mode bit 1 mask. */ -#define TC5_LCCBMODE1_bp 3 /* Channel Low B Compare or Capture Mode bit 1 position. */ - -#define TC5_LCCAMODE_gm 0x03 /* Channel Low A Compare or Capture Mode group mask. */ -#define TC5_LCCAMODE_gp 0 /* Channel Low A Compare or Capture Mode group position. */ -#define TC5_LCCAMODE0_bm (1<<0) /* Channel Low A Compare or Capture Mode bit 0 mask. */ -#define TC5_LCCAMODE0_bp 0 /* Channel Low A Compare or Capture Mode bit 0 position. */ -#define TC5_LCCAMODE1_bm (1<<1) /* Channel Low A Compare or Capture Mode bit 1 mask. */ -#define TC5_LCCAMODE1_bp 1 /* Channel Low A Compare or Capture Mode bit 1 position. */ - -/* TC5.CTRLF bit masks and bit positions */ -#define TC5_HCCBMODE_gm 0x0C /* Channel High B Compare or Capture Mode group mask. */ -#define TC5_HCCBMODE_gp 2 /* Channel High B Compare or Capture Mode group position. */ -#define TC5_HCCBMODE0_bm (1<<2) /* Channel High B Compare or Capture Mode bit 0 mask. */ -#define TC5_HCCBMODE0_bp 2 /* Channel High B Compare or Capture Mode bit 0 position. */ -#define TC5_HCCBMODE1_bm (1<<3) /* Channel High B Compare or Capture Mode bit 1 mask. */ -#define TC5_HCCBMODE1_bp 3 /* Channel High B Compare or Capture Mode bit 1 position. */ - -#define TC5_HCCAMODE_gm 0x03 /* Channel High A Compare or Capture Mode group mask. */ -#define TC5_HCCAMODE_gp 0 /* Channel High A Compare or Capture Mode group position. */ -#define TC5_HCCAMODE0_bm (1<<0) /* Channel High A Compare or Capture Mode bit 0 mask. */ -#define TC5_HCCAMODE0_bp 0 /* Channel High A Compare or Capture Mode bit 0 position. */ -#define TC5_HCCAMODE1_bm (1<<1) /* Channel High A Compare or Capture Mode bit 1 mask. */ -#define TC5_HCCAMODE1_bp 1 /* Channel High A Compare or Capture Mode bit 1 position. */ - -/* TC5.INTCTRLA bit masks and bit positions */ -#define TC5_TRGINTLVL_gm 0x30 /* Timer Trigger Restart Interrupt Level group mask. */ -#define TC5_TRGINTLVL_gp 4 /* Timer Trigger Restart Interrupt Level group position. */ -#define TC5_TRGINTLVL0_bm (1<<4) /* Timer Trigger Restart Interrupt Level bit 0 mask. */ -#define TC5_TRGINTLVL0_bp 4 /* Timer Trigger Restart Interrupt Level bit 0 position. */ -#define TC5_TRGINTLVL1_bm (1<<5) /* Timer Trigger Restart Interrupt Level bit 1 mask. */ -#define TC5_TRGINTLVL1_bp 5 /* Timer Trigger Restart Interrupt Level bit 1 position. */ - -#define TC5_ERRINTLVL_gm 0x0C /* Timer Error Interrupt Level group mask. */ -#define TC5_ERRINTLVL_gp 2 /* Timer Error Interrupt Level group position. */ -#define TC5_ERRINTLVL0_bm (1<<2) /* Timer Error Interrupt Level bit 0 mask. */ -#define TC5_ERRINTLVL0_bp 2 /* Timer Error Interrupt Level bit 0 position. */ -#define TC5_ERRINTLVL1_bm (1<<3) /* Timer Error Interrupt Level bit 1 mask. */ -#define TC5_ERRINTLVL1_bp 3 /* Timer Error Interrupt Level bit 1 position. */ - -#define TC5_OVFINTLVL_gm 0x03 /* Timer Overflow/Underflow Interrupt Level group mask. */ -#define TC5_OVFINTLVL_gp 0 /* Timer Overflow/Underflow Interrupt Level group position. */ -#define TC5_OVFINTLVL0_bm (1<<0) /* Timer Overflow/Underflow Interrupt Level bit 0 mask. */ -#define TC5_OVFINTLVL0_bp 0 /* Timer Overflow/Underflow Interrupt Level bit 0 position. */ -#define TC5_OVFINTLVL1_bm (1<<1) /* Timer Overflow/Underflow Interrupt Level bit 1 mask. */ -#define TC5_OVFINTLVL1_bp 1 /* Timer Overflow/Underflow Interrupt Level bit 1 position. */ - -/* TC5.INTCTRLB bit masks and bit positions */ -#define TC5_CCBINTLVL_gm 0x0C /* Channel B Compare or Capture Interrupt Level group mask. */ -#define TC5_CCBINTLVL_gp 2 /* Channel B Compare or Capture Interrupt Level group position. */ -#define TC5_CCBINTLVL0_bm (1<<2) /* Channel B Compare or Capture Interrupt Level bit 0 mask. */ -#define TC5_CCBINTLVL0_bp 2 /* Channel B Compare or Capture Interrupt Level bit 0 position. */ -#define TC5_CCBINTLVL1_bm (1<<3) /* Channel B Compare or Capture Interrupt Level bit 1 mask. */ -#define TC5_CCBINTLVL1_bp 3 /* Channel B Compare or Capture Interrupt Level bit 1 position. */ - -#define TC5_CCAINTLVL_gm 0x03 /* Channel A Compare or Capture Interrupt Level group mask. */ -#define TC5_CCAINTLVL_gp 0 /* Channel A Compare or Capture Interrupt Level group position. */ -#define TC5_CCAINTLVL0_bm (1<<0) /* Channel A Compare or Capture Interrupt Level bit 0 mask. */ -#define TC5_CCAINTLVL0_bp 0 /* Channel A Compare or Capture Interrupt Level bit 0 position. */ -#define TC5_CCAINTLVL1_bm (1<<1) /* Channel A Compare or Capture Interrupt Level bit 1 mask. */ -#define TC5_CCAINTLVL1_bp 1 /* Channel A Compare or Capture Interrupt Level bit 1 position. */ - -#define TC5_LCCBINTLVL_gm 0x0C /* Channel Low B Compare or Capture Interrupt Level group mask. */ -#define TC5_LCCBINTLVL_gp 2 /* Channel Low B Compare or Capture Interrupt Level group position. */ -#define TC5_LCCBINTLVL0_bm (1<<2) /* Channel Low B Compare or Capture Interrupt Level bit 0 mask. */ -#define TC5_LCCBINTLVL0_bp 2 /* Channel Low B Compare or Capture Interrupt Level bit 0 position. */ -#define TC5_LCCBINTLVL1_bm (1<<3) /* Channel Low B Compare or Capture Interrupt Level bit 1 mask. */ -#define TC5_LCCBINTLVL1_bp 3 /* Channel Low B Compare or Capture Interrupt Level bit 1 position. */ - -#define TC5_LCCAINTLVL_gm 0x03 /* Channel Low A Compare or Capture Interrupt Level group mask. */ -#define TC5_LCCAINTLVL_gp 0 /* Channel Low A Compare or Capture Interrupt Level group position. */ -#define TC5_LCCAINTLVL0_bm (1<<0) /* Channel Low A Compare or Capture Interrupt Level bit 0 mask. */ -#define TC5_LCCAINTLVL0_bp 0 /* Channel Low A Compare or Capture Interrupt Level bit 0 position. */ -#define TC5_LCCAINTLVL1_bm (1<<1) /* Channel Low A Compare or Capture Interrupt Level bit 1 mask. */ -#define TC5_LCCAINTLVL1_bp 1 /* Channel Low A Compare or Capture Interrupt Level bit 1 position. */ - -/* TC5.CTRLGCLR bit masks and bit positions */ -#define TC5_STOP_bm 0x20 /* Timer/Counter Stop bit mask. */ -#define TC5_STOP_bp 5 /* Timer/Counter Stop bit position. */ - -#define TC5_CMD_gm 0x0C /* Command group mask. */ -#define TC5_CMD_gp 2 /* Command group position. */ -#define TC5_CMD0_bm (1<<2) /* Command bit 0 mask. */ -#define TC5_CMD0_bp 2 /* Command bit 0 position. */ -#define TC5_CMD1_bm (1<<3) /* Command bit 1 mask. */ -#define TC5_CMD1_bp 3 /* Command bit 1 position. */ - -#define TC5_LUPD_bm 0x02 /* Lock Update bit mask. */ -#define TC5_LUPD_bp 1 /* Lock Update bit position. */ - -#define TC5_DIR_bm 0x01 /* Counter Direction bit mask. */ -#define TC5_DIR_bp 0 /* Counter Direction bit position. */ - -/* TC5.CTRLGSET bit masks and bit positions */ -/* TC5_STOP Predefined. */ -/* TC5_STOP Predefined. */ - -/* TC5_CMD Predefined. */ -/* TC5_CMD Predefined. */ - -/* TC5_LUPD Predefined. */ -/* TC5_LUPD Predefined. */ - -/* TC5_DIR Predefined. */ -/* TC5_DIR Predefined. */ - -/* TC5.CTRLHCLR bit masks and bit positions */ -#define TC5_CCBBV_bm 0x04 /* Channel B Compare or Capture Buffer Valid bit mask. */ -#define TC5_CCBBV_bp 2 /* Channel B Compare or Capture Buffer Valid bit position. */ - -#define TC5_CCABV_bm 0x02 /* Channel A Compare or Capture Buffer Valid bit mask. */ -#define TC5_CCABV_bp 1 /* Channel A Compare or Capture Buffer Valid bit position. */ - -#define TC5_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ -#define TC5_PERBV_bp 0 /* Period Buffer Valid bit position. */ - -#define TC5_LCCBBV_bm 0x04 /* Channel Low B Compare or Capture Buffer Valid bit mask. */ -#define TC5_LCCBBV_bp 2 /* Channel Low B Compare or Capture Buffer Valid bit position. */ - -#define TC5_LCCABV_bm 0x02 /* Channel Low A Compare or Capture Buffer Valid bit mask. */ -#define TC5_LCCABV_bp 1 /* Channel Low A Compare or Capture Buffer Valid bit position. */ - -#define TC5_LPERBV_bm 0x01 /* Period Low Buffer Valid bit mask. */ -#define TC5_LPERBV_bp 0 /* Period Low Buffer Valid bit position. */ - -/* TC5.CTRLHSET bit masks and bit positions */ -/* TC5_CCBBV Predefined. */ -/* TC5_CCBBV Predefined. */ - -/* TC5_CCABV Predefined. */ -/* TC5_CCABV Predefined. */ - -/* TC5_PERBV Predefined. */ -/* TC5_PERBV Predefined. */ - -/* TC5_LCCBBV Predefined. */ -/* TC5_LCCBBV Predefined. */ - -/* TC5_LCCABV Predefined. */ -/* TC5_LCCABV Predefined. */ - -/* TC5_LPERBV Predefined. */ -/* TC5_LPERBV Predefined. */ - -/* TC5.INTFLAGS bit masks and bit positions */ -#define TC5_CCBIF_bm 0x20 /* Channel B Compare or Capture Interrupt Flag bit mask. */ -#define TC5_CCBIF_bp 5 /* Channel B Compare or Capture Interrupt Flag bit position. */ - -#define TC5_CCAIF_bm 0x10 /* Channel A Compare or Capture Interrupt Flag bit mask. */ -#define TC5_CCAIF_bp 4 /* Channel A Compare or Capture Interrupt Flag bit position. */ - -#define TC5_TRGIF_bm 0x04 /* Trigger Restart Interrupt Flag bit mask. */ -#define TC5_TRGIF_bp 2 /* Trigger Restart Interrupt Flag bit position. */ - -#define TC5_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ -#define TC5_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ - -#define TC5_OVFIF_bm 0x01 /* Overflow/Underflow Interrupt Flag bit mask. */ -#define TC5_OVFIF_bp 0 /* Overflow/Underflow Interrupt Flag bit position. */ - -#define TC5_LCCBIF_bm 0x20 /* Channel Low B Compare or Capture Interrupt Flag bit mask. */ -#define TC5_LCCBIF_bp 5 /* Channel Low B Compare or Capture Interrupt Flag bit position. */ - -#define TC5_LCCAIF_bm 0x10 /* Channel Low A Compare or Capture Interrupt Flag bit mask. */ -#define TC5_LCCAIF_bp 4 /* Channel Low A Compare or Capture Interrupt Flag bit position. */ - -/* FAULT - Fault Extension */ -/* FAULT.CTRLA bit masks and bit positions */ -#define FAULT_RAMP_gm 0xC0 /* Ramp Mode Selection group mask. */ -#define FAULT_RAMP_gp 6 /* Ramp Mode Selection group position. */ -#define FAULT_RAMP0_bm (1<<6) /* Ramp Mode Selection bit 0 mask. */ -#define FAULT_RAMP0_bp 6 /* Ramp Mode Selection bit 0 position. */ -#define FAULT_RAMP1_bm (1<<7) /* Ramp Mode Selection bit 1 mask. */ -#define FAULT_RAMP1_bp 7 /* Ramp Mode Selection bit 1 position. */ - -#define FAULT_FDDBD_bm 0x20 /* Fault on Debug Break Detection bit mask. */ -#define FAULT_FDDBD_bp 5 /* Fault on Debug Break Detection bit position. */ - -#define FAULT_PORTCTRL_bm 0x10 /* Port Control Mode bit mask. */ -#define FAULT_PORTCTRL_bp 4 /* Port Control Mode bit position. */ - -#define FAULT_FUSE_bm 0x08 /* Fuse State bit mask. */ -#define FAULT_FUSE_bp 3 /* Fuse State bit position. */ - -#define FAULT_FILTERE_bm 0x04 /* Fault E Digital Filter Selection bit mask. */ -#define FAULT_FILTERE_bp 2 /* Fault E Digital Filter Selection bit position. */ - -#define FAULT_SRCE_gm 0x03 /* Fault E Input selection group mask. */ -#define FAULT_SRCE_gp 0 /* Fault E Input selection group position. */ -#define FAULT_SRCE0_bm (1<<0) /* Fault E Input selection bit 0 mask. */ -#define FAULT_SRCE0_bp 0 /* Fault E Input selection bit 0 position. */ -#define FAULT_SRCE1_bm (1<<1) /* Fault E Input selection bit 1 mask. */ -#define FAULT_SRCE1_bp 1 /* Fault E Input selection bit 1 position. */ - -/* FAULT.CTRLB bit masks and bit positions */ -#define FAULT_SOFTA_bm 0x80 /* Fault A Software Mode bit mask. */ -#define FAULT_SOFTA_bp 7 /* Fault A Software Mode bit position. */ - -#define FAULT_HALTA_gm 0x60 /* Fault A Halt Action group mask. */ -#define FAULT_HALTA_gp 5 /* Fault A Halt Action group position. */ -#define FAULT_HALTA0_bm (1<<5) /* Fault A Halt Action bit 0 mask. */ -#define FAULT_HALTA0_bp 5 /* Fault A Halt Action bit 0 position. */ -#define FAULT_HALTA1_bm (1<<6) /* Fault A Halt Action bit 1 mask. */ -#define FAULT_HALTA1_bp 6 /* Fault A Halt Action bit 1 position. */ - -#define FAULT_RESTARTA_bm 0x10 /* Fault A Restart Action bit mask. */ -#define FAULT_RESTARTA_bp 4 /* Fault A Restart Action bit position. */ - -#define FAULT_KEEPA_bm 0x08 /* Fault A Keep Action bit mask. */ -#define FAULT_KEEPA_bp 3 /* Fault A Keep Action bit position. */ - -#define FAULT_SRCA_gm 0x03 /* Fault A Source Selection group mask. */ -#define FAULT_SRCA_gp 0 /* Fault A Source Selection group position. */ -#define FAULT_SRCA0_bm (1<<0) /* Fault A Source Selection bit 0 mask. */ -#define FAULT_SRCA0_bp 0 /* Fault A Source Selection bit 0 position. */ -#define FAULT_SRCA1_bm (1<<1) /* Fault A Source Selection bit 1 mask. */ -#define FAULT_SRCA1_bp 1 /* Fault A Source Selection bit 1 position. */ - -/* FAULT.CTRLC bit masks and bit positions */ -#define FAULT_CAPTA_bm 0x20 /* Fault A Capture bit mask. */ -#define FAULT_CAPTA_bp 5 /* Fault A Capture bit position. */ - -#define FAULT_FILTERA_bm 0x04 /* Fault A Digital Filter Selection bit mask. */ -#define FAULT_FILTERA_bp 2 /* Fault A Digital Filter Selection bit position. */ - -#define FAULT_BLANKA_bm 0x02 /* Fault A Blanking bit mask. */ -#define FAULT_BLANKA_bp 1 /* Fault A Blanking bit position. */ - -#define FAULT_QUALA_bm 0x01 /* Fault A Qualification bit mask. */ -#define FAULT_QUALA_bp 0 /* Fault A Qualification bit position. */ - -/* FAULT.CTRLD bit masks and bit positions */ -#define FAULT_SOFTB_bm 0x80 /* Fault B Software Mode bit mask. */ -#define FAULT_SOFTB_bp 7 /* Fault B Software Mode bit position. */ - -#define FAULT_HALTB_gm 0x60 /* Fault B Halt Action group mask. */ -#define FAULT_HALTB_gp 5 /* Fault B Halt Action group position. */ -#define FAULT_HALTB0_bm (1<<5) /* Fault B Halt Action bit 0 mask. */ -#define FAULT_HALTB0_bp 5 /* Fault B Halt Action bit 0 position. */ -#define FAULT_HALTB1_bm (1<<6) /* Fault B Halt Action bit 1 mask. */ -#define FAULT_HALTB1_bp 6 /* Fault B Halt Action bit 1 position. */ - -#define FAULT_RESTARTB_bm 0x10 /* Fault B Restart Action bit mask. */ -#define FAULT_RESTARTB_bp 4 /* Fault B Restart Action bit position. */ - -#define FAULT_KEEPB_bm 0x08 /* Fault B Keep Action bit mask. */ -#define FAULT_KEEPB_bp 3 /* Fault B Keep Action bit position. */ - -#define FAULT_SRCB_gm 0x03 /* Fault B Source Selection group mask. */ -#define FAULT_SRCB_gp 0 /* Fault B Source Selection group position. */ -#define FAULT_SRCB0_bm (1<<0) /* Fault B Source Selection bit 0 mask. */ -#define FAULT_SRCB0_bp 0 /* Fault B Source Selection bit 0 position. */ -#define FAULT_SRCB1_bm (1<<1) /* Fault B Source Selection bit 1 mask. */ -#define FAULT_SRCB1_bp 1 /* Fault B Source Selection bit 1 position. */ - -/* FAULT.CTRLE bit masks and bit positions */ -#define FAULT_CAPTB_bm 0x20 /* Fault B Capture bit mask. */ -#define FAULT_CAPTB_bp 5 /* Fault B Capture bit position. */ - -#define FAULT_FILTERB_bm 0x04 /* Fault B Digital Filter Selection bit mask. */ -#define FAULT_FILTERB_bp 2 /* Fault B Digital Filter Selection bit position. */ - -#define FAULT_BLANKB_bm 0x02 /* Fault B Blanking bit mask. */ -#define FAULT_BLANKB_bp 1 /* Fault B Blanking bit position. */ - -#define FAULT_QUALB_bm 0x01 /* Fault B Qualification bit mask. */ -#define FAULT_QUALB_bp 0 /* Fault B Qualification bit position. */ - -/* FAULT.STATUS bit masks and bit positions */ -#define FAULT_STATEB_bm 0x80 /* Fault B State bit mask. */ -#define FAULT_STATEB_bp 7 /* Fault B State bit position. */ - -#define FAULT_STATEA_bm 0x40 /* Fault A State bit mask. */ -#define FAULT_STATEA_bp 6 /* Fault A State bit position. */ - -#define FAULT_STATEE_bm 0x20 /* Fault E State bit mask. */ -#define FAULT_STATEE_bp 5 /* Fault E State bit position. */ - -#define FAULT_IDX_bm 0x08 /* Channel Index Flag bit mask. */ -#define FAULT_IDX_bp 3 /* Channel Index Flag bit position. */ - -#define FAULT_FAULTBIN_bm 0x04 /* Fault B Flag bit mask. */ -#define FAULT_FAULTBIN_bp 2 /* Fault B Flag bit position. */ - -#define FAULT_FAULTAIN_bm 0x02 /* Fault A Flag bit mask. */ -#define FAULT_FAULTAIN_bp 1 /* Fault A Flag bit position. */ - -#define FAULT_FAULTEIN_bm 0x01 /* Fault E Flag bit mask. */ -#define FAULT_FAULTEIN_bp 0 /* Fault E Flag bit position. */ - -/* FAULT.CTRLGCLR bit masks and bit positions */ -#define FAULT_HALTBCLR_bm 0x80 /* State B Clear bit mask. */ -#define FAULT_HALTBCLR_bp 7 /* State B Clear bit position. */ - -#define FAULT_HALTACLR_bm 0x40 /* State A Clear bit mask. */ -#define FAULT_HALTACLR_bp 6 /* State A Clear bit position. */ - -#define FAULT_STATEECLR_bm 0x20 /* State E Clear bit mask. */ -#define FAULT_STATEECLR_bp 5 /* State E Clear bit position. */ - -#define FAULT_FAULTB_bm 0x04 /* Fault B Flag bit mask. */ -#define FAULT_FAULTB_bp 2 /* Fault B Flag bit position. */ - -#define FAULT_FAULTA_bm 0x02 /* Fault A Flag bit mask. */ -#define FAULT_FAULTA_bp 1 /* Fault A Flag bit position. */ - -#define FAULT_FAULTE_bm 0x01 /* Fault E Flag bit mask. */ -#define FAULT_FAULTE_bp 0 /* Fault E Flag bit position. */ - -/* FAULT.CTRLGSET bit masks and bit positions */ -#define FAULT_FAULTBSW_bm 0x80 /* Software Fault B bit mask. */ -#define FAULT_FAULTBSW_bp 7 /* Software Fault B bit position. */ - -#define FAULT_FAULTASW_bm 0x40 /* Software Fault A bit mask. */ -#define FAULT_FAULTASW_bp 6 /* Software Fault A bit position. */ - -#define FAULT_FAULTESW_bm 0x20 /* Software Fault E bit mask. */ -#define FAULT_FAULTESW_bp 5 /* Software Fault E bit position. */ - -#define FAULT_IDXCMD_gm 0x18 /* Channel index Command group mask. */ -#define FAULT_IDXCMD_gp 3 /* Channel index Command group position. */ -#define FAULT_IDXCMD0_bm (1<<3) /* Channel index Command bit 0 mask. */ -#define FAULT_IDXCMD0_bp 3 /* Channel index Command bit 0 position. */ -#define FAULT_IDXCMD1_bm (1<<4) /* Channel index Command bit 1 mask. */ -#define FAULT_IDXCMD1_bp 4 /* Channel index Command bit 1 position. */ - -/* WEX - Waveform Extension */ -/* WEX.CTRL bit masks and bit positions */ -#define WEX_UPSEL_bm 0x80 /* Update Source Selection bit mask. */ -#define WEX_UPSEL_bp 7 /* Update Source Selection bit position. */ - -#define WEX_OTMX_gm 0x70 /* Output Matrix group mask. */ -#define WEX_OTMX_gp 4 /* Output Matrix group position. */ -#define WEX_OTMX0_bm (1<<4) /* Output Matrix bit 0 mask. */ -#define WEX_OTMX0_bp 4 /* Output Matrix bit 0 position. */ -#define WEX_OTMX1_bm (1<<5) /* Output Matrix bit 1 mask. */ -#define WEX_OTMX1_bp 5 /* Output Matrix bit 1 position. */ -#define WEX_OTMX2_bm (1<<6) /* Output Matrix bit 2 mask. */ -#define WEX_OTMX2_bp 6 /* Output Matrix bit 2 position. */ - -#define WEX_DTI3EN_bm 0x08 /* Dead-Time Insertion Generator 3 Enable bit mask. */ -#define WEX_DTI3EN_bp 3 /* Dead-Time Insertion Generator 3 Enable bit position. */ - -#define WEX_DTI2EN_bm 0x04 /* Dead-Time Insertion Generator 2 Enable bit mask. */ -#define WEX_DTI2EN_bp 2 /* Dead-Time Insertion Generator 2 Enable bit position. */ - -#define WEX_DTI1EN_bm 0x02 /* Dead-Time Insertion Generator 1 Enable bit mask. */ -#define WEX_DTI1EN_bp 1 /* Dead-Time Insertion Generator 1 Enable bit position. */ - -#define WEX_DTI0EN_bm 0x01 /* Dead-Time Insertion Generator 0 Enable bit mask. */ -#define WEX_DTI0EN_bp 0 /* Dead-Time Insertion Generator 0 Enable bit position. */ - -/* WEX.STATUSCLR bit masks and bit positions */ -#define WEX_SWAPBUF_bm 0x04 /* Swap Buffer Valid bit mask. */ -#define WEX_SWAPBUF_bp 2 /* Swap Buffer Valid bit position. */ - -#define WEX_PGVBUFV_bm 0x02 /* Pattern Generator Value Buffer Valid bit mask. */ -#define WEX_PGVBUFV_bp 1 /* Pattern Generator Value Buffer Valid bit position. */ - -#define WEX_PGOBUFV_bm 0x01 /* Pattern Generator Overwrite Buffer Valid bit mask. */ -#define WEX_PGOBUFV_bp 0 /* Pattern Generator Overwrite Buffer Valid bit position. */ - -/* WEX.STATUSSET bit masks and bit positions */ -/* WEX_SWAPBUF Predefined. */ -/* WEX_SWAPBUF Predefined. */ - -/* WEX_PGVBUFV Predefined. */ -/* WEX_PGVBUFV Predefined. */ - -/* WEX_PGOBUFV Predefined. */ -/* WEX_PGOBUFV Predefined. */ - -/* WEX.SWAP bit masks and bit positions */ -#define WEX_SWAP3_bm 0x08 /* Swap DTI output pair 3 bit mask. */ -#define WEX_SWAP3_bp 3 /* Swap DTI output pair 3 bit position. */ - -#define WEX_SWAP2_bm 0x04 /* Swap DTI output pair 2 bit mask. */ -#define WEX_SWAP2_bp 2 /* Swap DTI output pair 2 bit position. */ - -#define WEX_SWAP1_bm 0x02 /* Swap DTI output pair 1 bit mask. */ -#define WEX_SWAP1_bp 1 /* Swap DTI output pair 1 bit position. */ - -#define WEX_SWAP0_bm 0x01 /* Swap DTI output pair 0 bit mask. */ -#define WEX_SWAP0_bp 0 /* Swap DTI output pair 0 bit position. */ - -/* WEX.SWAPBUF bit masks and bit positions */ -#define WEX_SWAP3BUF_bm 0x08 /* Swap DTI output pair 3 bit mask. */ -#define WEX_SWAP3BUF_bp 3 /* Swap DTI output pair 3 bit position. */ - -#define WEX_SWAP2BUF_bm 0x04 /* Swap DTI output pair 2 bit mask. */ -#define WEX_SWAP2BUF_bp 2 /* Swap DTI output pair 2 bit position. */ - -#define WEX_SWAP1BUF_bm 0x02 /* Swap DTI output pair 1 bit mask. */ -#define WEX_SWAP1BUF_bp 1 /* Swap DTI output pair 1 bit position. */ - -#define WEX_SWAP0BUF_bm 0x01 /* Swap DTI output pair 0 bit mask. */ -#define WEX_SWAP0BUF_bp 0 /* Swap DTI output pair 0 bit position. */ - -/* HIRES - High-Resolution Extension */ -/* HIRES.CTRLA bit masks and bit positions */ -#define HIRES_HRPLUS_gm 0x0C /* High Resolution Plus group mask. */ -#define HIRES_HRPLUS_gp 2 /* High Resolution Plus group position. */ -#define HIRES_HRPLUS0_bm (1<<2) /* High Resolution Plus bit 0 mask. */ -#define HIRES_HRPLUS0_bp 2 /* High Resolution Plus bit 0 position. */ -#define HIRES_HRPLUS1_bm (1<<3) /* High Resolution Plus bit 1 mask. */ -#define HIRES_HRPLUS1_bp 3 /* High Resolution Plus bit 1 position. */ - -#define HIRES_HREN_gm 0x03 /* High Resolution Mode group mask. */ -#define HIRES_HREN_gp 0 /* High Resolution Mode group position. */ -#define HIRES_HREN0_bm (1<<0) /* High Resolution Mode bit 0 mask. */ -#define HIRES_HREN0_bp 0 /* High Resolution Mode bit 0 position. */ -#define HIRES_HREN1_bm (1<<1) /* High Resolution Mode bit 1 mask. */ -#define HIRES_HREN1_bp 1 /* High Resolution Mode bit 1 position. */ - -/* USART - Universal Asynchronous Receiver-Transmitter */ -/* USART.STATUS bit masks and bit positions */ -#define USART_RXCIF_bm 0x80 /* Receive Interrupt Flag bit mask. */ -#define USART_RXCIF_bp 7 /* Receive Interrupt Flag bit position. */ - -#define USART_TXCIF_bm 0x40 /* Transmit Interrupt Flag bit mask. */ -#define USART_TXCIF_bp 6 /* Transmit Interrupt Flag bit position. */ - -#define USART_DREIF_bm 0x20 /* Data Register Empty Flag bit mask. */ -#define USART_DREIF_bp 5 /* Data Register Empty Flag bit position. */ - -#define USART_FERR_bm 0x10 /* Frame Error bit mask. */ -#define USART_FERR_bp 4 /* Frame Error bit position. */ - -#define USART_BUFOVF_bm 0x08 /* Buffer Overflow bit mask. */ -#define USART_BUFOVF_bp 3 /* Buffer Overflow bit position. */ - -#define USART_PERR_bm 0x04 /* Parity Error bit mask. */ -#define USART_PERR_bp 2 /* Parity Error bit position. */ - -#define USART_RXSIF_bm 0x02 /* Receive Start Bit Interrupt Flag bit mask. */ -#define USART_RXSIF_bp 1 /* Receive Start Bit Interrupt Flag bit position. */ - -#define USART_RXB8_bm 0x01 /* Receive Bit 8 bit mask. */ -#define USART_RXB8_bp 0 /* Receive Bit 8 bit position. */ - -#define USART_DRIF_bm 0x01 /* Data Reception Flag bit mask. */ -#define USART_DRIF_bp 0 /* Data Reception Flag bit position. */ - -/* USART.CTRLA bit masks and bit positions */ -#define USART_RXSIE_bm 0x80 /* Receive Start Interrupt Enable bit mask. */ -#define USART_RXSIE_bp 7 /* Receive Start Interrupt Enable bit position. */ - -#define USART_DRIE_bm 0x40 /* Data Reception Interrupt Enable bit mask. */ -#define USART_DRIE_bp 6 /* Data Reception Interrupt Enable bit position. */ - -#define USART_RXCINTLVL_gm 0x30 /* Receive Interrupt Level group mask. */ -#define USART_RXCINTLVL_gp 4 /* Receive Interrupt Level group position. */ -#define USART_RXCINTLVL0_bm (1<<4) /* Receive Interrupt Level bit 0 mask. */ -#define USART_RXCINTLVL0_bp 4 /* Receive Interrupt Level bit 0 position. */ -#define USART_RXCINTLVL1_bm (1<<5) /* Receive Interrupt Level bit 1 mask. */ -#define USART_RXCINTLVL1_bp 5 /* Receive Interrupt Level bit 1 position. */ - -#define USART_TXCINTLVL_gm 0x0C /* Transmit Interrupt Level group mask. */ -#define USART_TXCINTLVL_gp 2 /* Transmit Interrupt Level group position. */ -#define USART_TXCINTLVL0_bm (1<<2) /* Transmit Interrupt Level bit 0 mask. */ -#define USART_TXCINTLVL0_bp 2 /* Transmit Interrupt Level bit 0 position. */ -#define USART_TXCINTLVL1_bm (1<<3) /* Transmit Interrupt Level bit 1 mask. */ -#define USART_TXCINTLVL1_bp 3 /* Transmit Interrupt Level bit 1 position. */ - -#define USART_DREINTLVL_gm 0x03 /* Data Register Empty Interrupt Level group mask. */ -#define USART_DREINTLVL_gp 0 /* Data Register Empty Interrupt Level group position. */ -#define USART_DREINTLVL0_bm (1<<0) /* Data Register Empty Interrupt Level bit 0 mask. */ -#define USART_DREINTLVL0_bp 0 /* Data Register Empty Interrupt Level bit 0 position. */ -#define USART_DREINTLVL1_bm (1<<1) /* Data Register Empty Interrupt Level bit 1 mask. */ -#define USART_DREINTLVL1_bp 1 /* Data Register Empty Interrupt Level bit 1 position. */ - -/* USART.CTRLB bit masks and bit positions */ -#define USART_ONEWIRE_bm 0x80 /* One Wire Mode bit mask. */ -#define USART_ONEWIRE_bp 7 /* One Wire Mode bit position. */ - -#define USART_SFDEN_bm 0x40 /* Start Frame Detection Enable bit mask. */ -#define USART_SFDEN_bp 6 /* Start Frame Detection Enable bit position. */ - -#define USART_RXEN_bm 0x10 /* Receiver Enable bit mask. */ -#define USART_RXEN_bp 4 /* Receiver Enable bit position. */ - -#define USART_TXEN_bm 0x08 /* Transmitter Enable bit mask. */ -#define USART_TXEN_bp 3 /* Transmitter Enable bit position. */ - -#define USART_CLK2X_bm 0x04 /* Double transmission speed bit mask. */ -#define USART_CLK2X_bp 2 /* Double transmission speed bit position. */ - -#define USART_MPCM_bm 0x02 /* Multi-processor Communication Mode bit mask. */ -#define USART_MPCM_bp 1 /* Multi-processor Communication Mode bit position. */ - -#define USART_TXB8_bm 0x01 /* Transmit bit 8 bit mask. */ -#define USART_TXB8_bp 0 /* Transmit bit 8 bit position. */ - -/* USART.CTRLC bit masks and bit positions */ -#define USART_CMODE_gm 0xC0 /* Communication Mode group mask. */ -#define USART_CMODE_gp 6 /* Communication Mode group position. */ -#define USART_CMODE0_bm (1<<6) /* Communication Mode bit 0 mask. */ -#define USART_CMODE0_bp 6 /* Communication Mode bit 0 position. */ -#define USART_CMODE1_bm (1<<7) /* Communication Mode bit 1 mask. */ -#define USART_CMODE1_bp 7 /* Communication Mode bit 1 position. */ - -#define USART_PMODE_gm 0x30 /* Parity Mode group mask. */ -#define USART_PMODE_gp 4 /* Parity Mode group position. */ -#define USART_PMODE0_bm (1<<4) /* Parity Mode bit 0 mask. */ -#define USART_PMODE0_bp 4 /* Parity Mode bit 0 position. */ -#define USART_PMODE1_bm (1<<5) /* Parity Mode bit 1 mask. */ -#define USART_PMODE1_bp 5 /* Parity Mode bit 1 position. */ - -#define USART_SBMODE_bm 0x08 /* Stop Bit Mode bit mask. */ -#define USART_SBMODE_bp 3 /* Stop Bit Mode bit position. */ - -#define USART_CHSIZE_gm 0x07 /* Character Size group mask. */ -#define USART_CHSIZE_gp 0 /* Character Size group position. */ -#define USART_CHSIZE0_bm (1<<0) /* Character Size bit 0 mask. */ -#define USART_CHSIZE0_bp 0 /* Character Size bit 0 position. */ -#define USART_CHSIZE1_bm (1<<1) /* Character Size bit 1 mask. */ -#define USART_CHSIZE1_bp 1 /* Character Size bit 1 position. */ -#define USART_CHSIZE2_bm (1<<2) /* Character Size bit 2 mask. */ -#define USART_CHSIZE2_bp 2 /* Character Size bit 2 position. */ - -/* USART.CTRLD bit masks and bit positions */ -#define USART_DECTYPE_gm 0x30 /* Receive Interrupt Level group mask. */ -#define USART_DECTYPE_gp 4 /* Receive Interrupt Level group position. */ -#define USART_DECTYPE0_bm (1<<4) /* Receive Interrupt Level bit 0 mask. */ -#define USART_DECTYPE0_bp 4 /* Receive Interrupt Level bit 0 position. */ -#define USART_DECTYPE1_bm (1<<5) /* Receive Interrupt Level bit 1 mask. */ -#define USART_DECTYPE1_bp 5 /* Receive Interrupt Level bit 1 position. */ - -#define USART_LUTACT_gm 0x0C /* Transmit Interrupt Level group mask. */ -#define USART_LUTACT_gp 2 /* Transmit Interrupt Level group position. */ -#define USART_LUTACT0_bm (1<<2) /* Transmit Interrupt Level bit 0 mask. */ -#define USART_LUTACT0_bp 2 /* Transmit Interrupt Level bit 0 position. */ -#define USART_LUTACT1_bm (1<<3) /* Transmit Interrupt Level bit 1 mask. */ -#define USART_LUTACT1_bp 3 /* Transmit Interrupt Level bit 1 position. */ - -#define USART_PECACT_gm 0x03 /* Data Register Empty Interrupt Level group mask. */ -#define USART_PECACT_gp 0 /* Data Register Empty Interrupt Level group position. */ -#define USART_PECACT0_bm (1<<0) /* Data Register Empty Interrupt Level bit 0 mask. */ -#define USART_PECACT0_bp 0 /* Data Register Empty Interrupt Level bit 0 position. */ -#define USART_PECACT1_bm (1<<1) /* Data Register Empty Interrupt Level bit 1 mask. */ -#define USART_PECACT1_bp 1 /* Data Register Empty Interrupt Level bit 1 position. */ - -/* USART.BAUDCTRLA bit masks and bit positions */ -#define USART_BSEL_gm 0xFF /* Baud Rate Selection Bits [7:0] group mask. */ -#define USART_BSEL_gp 0 /* Baud Rate Selection Bits [7:0] group position. */ -#define USART_BSEL0_bm (1<<0) /* Baud Rate Selection Bits [7:0] bit 0 mask. */ -#define USART_BSEL0_bp 0 /* Baud Rate Selection Bits [7:0] bit 0 position. */ -#define USART_BSEL1_bm (1<<1) /* Baud Rate Selection Bits [7:0] bit 1 mask. */ -#define USART_BSEL1_bp 1 /* Baud Rate Selection Bits [7:0] bit 1 position. */ -#define USART_BSEL2_bm (1<<2) /* Baud Rate Selection Bits [7:0] bit 2 mask. */ -#define USART_BSEL2_bp 2 /* Baud Rate Selection Bits [7:0] bit 2 position. */ -#define USART_BSEL3_bm (1<<3) /* Baud Rate Selection Bits [7:0] bit 3 mask. */ -#define USART_BSEL3_bp 3 /* Baud Rate Selection Bits [7:0] bit 3 position. */ -#define USART_BSEL4_bm (1<<4) /* Baud Rate Selection Bits [7:0] bit 4 mask. */ -#define USART_BSEL4_bp 4 /* Baud Rate Selection Bits [7:0] bit 4 position. */ -#define USART_BSEL5_bm (1<<5) /* Baud Rate Selection Bits [7:0] bit 5 mask. */ -#define USART_BSEL5_bp 5 /* Baud Rate Selection Bits [7:0] bit 5 position. */ -#define USART_BSEL6_bm (1<<6) /* Baud Rate Selection Bits [7:0] bit 6 mask. */ -#define USART_BSEL6_bp 6 /* Baud Rate Selection Bits [7:0] bit 6 position. */ -#define USART_BSEL7_bm (1<<7) /* Baud Rate Selection Bits [7:0] bit 7 mask. */ -#define USART_BSEL7_bp 7 /* Baud Rate Selection Bits [7:0] bit 7 position. */ - -/* USART.BAUDCTRLB bit masks and bit positions */ -#define USART_BSCALE_gm 0xF0 /* Baud Rate Scale group mask. */ -#define USART_BSCALE_gp 4 /* Baud Rate Scale group position. */ -#define USART_BSCALE0_bm (1<<4) /* Baud Rate Scale bit 0 mask. */ -#define USART_BSCALE0_bp 4 /* Baud Rate Scale bit 0 position. */ -#define USART_BSCALE1_bm (1<<5) /* Baud Rate Scale bit 1 mask. */ -#define USART_BSCALE1_bp 5 /* Baud Rate Scale bit 1 position. */ -#define USART_BSCALE2_bm (1<<6) /* Baud Rate Scale bit 2 mask. */ -#define USART_BSCALE2_bp 6 /* Baud Rate Scale bit 2 position. */ -#define USART_BSCALE3_bm (1<<7) /* Baud Rate Scale bit 3 mask. */ -#define USART_BSCALE3_bp 7 /* Baud Rate Scale bit 3 position. */ - -/* USART_BSEL Predefined. */ -/* USART_BSEL Predefined. */ - -/* SPI - Serial Peripheral Interface */ -/* SPI.CTRL bit masks and bit positions */ -#define SPI_CLK2X_bm 0x80 /* Enable Double Speed bit mask. */ -#define SPI_CLK2X_bp 7 /* Enable Double Speed bit position. */ - -#define SPI_ENABLE_bm 0x40 /* Enable SPI Module bit mask. */ -#define SPI_ENABLE_bp 6 /* Enable SPI Module bit position. */ - -#define SPI_DORD_bm 0x20 /* Data Order Setting bit mask. */ -#define SPI_DORD_bp 5 /* Data Order Setting bit position. */ - -#define SPI_MASTER_bm 0x10 /* Master Operation Enable bit mask. */ -#define SPI_MASTER_bp 4 /* Master Operation Enable bit position. */ - -#define SPI_MODE_gm 0x0C /* SPI Mode group mask. */ -#define SPI_MODE_gp 2 /* SPI Mode group position. */ -#define SPI_MODE0_bm (1<<2) /* SPI Mode bit 0 mask. */ -#define SPI_MODE0_bp 2 /* SPI Mode bit 0 position. */ -#define SPI_MODE1_bm (1<<3) /* SPI Mode bit 1 mask. */ -#define SPI_MODE1_bp 3 /* SPI Mode bit 1 position. */ - -#define SPI_PRESCALER_gm 0x03 /* Prescaler group mask. */ -#define SPI_PRESCALER_gp 0 /* Prescaler group position. */ -#define SPI_PRESCALER0_bm (1<<0) /* Prescaler bit 0 mask. */ -#define SPI_PRESCALER0_bp 0 /* Prescaler bit 0 position. */ -#define SPI_PRESCALER1_bm (1<<1) /* Prescaler bit 1 mask. */ -#define SPI_PRESCALER1_bp 1 /* Prescaler bit 1 position. */ - -/* SPI.INTCTRL bit masks and bit positions */ -#define SPI_RXCIE_bm 0x80 /* Receive Complete Interrupt Enable (In Buffer Modes Only). bit mask. */ -#define SPI_RXCIE_bp 7 /* Receive Complete Interrupt Enable (In Buffer Modes Only). bit position. */ - -#define SPI_TXCIE_bm 0x40 /* Transmit Complete Interrupt Enable (In Buffer Modes Only). bit mask. */ -#define SPI_TXCIE_bp 6 /* Transmit Complete Interrupt Enable (In Buffer Modes Only). bit position. */ - -#define SPI_DREIE_bm 0x20 /* Data Register Empty Interrupt Enable (In Buffer Modes Only). bit mask. */ -#define SPI_DREIE_bp 5 /* Data Register Empty Interrupt Enable (In Buffer Modes Only). bit position. */ - -#define SPI_SSIE_bm 0x10 /* Slave Select Trigger Interrupt Enable (In Buffer Modes Only). bit mask. */ -#define SPI_SSIE_bp 4 /* Slave Select Trigger Interrupt Enable (In Buffer Modes Only). bit position. */ - -#define SPI_INTLVL_gm 0x03 /* Interrupt level group mask. */ -#define SPI_INTLVL_gp 0 /* Interrupt level group position. */ -#define SPI_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */ -#define SPI_INTLVL0_bp 0 /* Interrupt level bit 0 position. */ -#define SPI_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */ -#define SPI_INTLVL1_bp 1 /* Interrupt level bit 1 position. */ - -/* SPI.STATUS bit masks and bit positions */ -#define SPI_IF_bm 0x80 /* Interrupt Flag (In Standard Mode Only). bit mask. */ -#define SPI_IF_bp 7 /* Interrupt Flag (In Standard Mode Only). bit position. */ - -#define SPI_RXCIF_bm 0x80 /* Receive Complete Interrupt Flag (In Buffer Modes Only). bit mask. */ -#define SPI_RXCIF_bp 7 /* Receive Complete Interrupt Flag (In Buffer Modes Only). bit position. */ - -#define SPI_WRCOL_bm 0x40 /* Write Collision Flag (In Standard Mode Only). bit mask. */ -#define SPI_WRCOL_bp 6 /* Write Collision Flag (In Standard Mode Only). bit position. */ - -#define SPI_TXCIF_bm 0x40 /* Transmit Complete Interrupt Flag (In Buffer Modes Only). bit mask. */ -#define SPI_TXCIF_bp 6 /* Transmit Complete Interrupt Flag (In Buffer Modes Only). bit position. */ - -#define SPI_DREIF_bm 0x20 /* Data Register Empty Interrupt Flag (In Buffer Modes Only). bit mask. */ -#define SPI_DREIF_bp 5 /* Data Register Empty Interrupt Flag (In Buffer Modes Only). bit position. */ - -#define SPI_SSIF_bm 0x10 /* Slave Select Trigger Interrupt Flag (In Buffer Modes Only). bit mask. */ -#define SPI_SSIF_bp 4 /* Slave Select Trigger Interrupt Flag (In Buffer Modes Only). bit position. */ - -#define SPI_BUFOVF_bm 0x01 /* Buffer Overflow (In Buffer Modes Only). bit mask. */ -#define SPI_BUFOVF_bp 0 /* Buffer Overflow (In Buffer Modes Only). bit position. */ - -/* SPI.CTRLB bit masks and bit positions */ -#define SPI_BUFMODE_gm 0xC0 /* Buffer Modes group mask. */ -#define SPI_BUFMODE_gp 6 /* Buffer Modes group position. */ -#define SPI_BUFMODE0_bm (1<<6) /* Buffer Modes bit 0 mask. */ -#define SPI_BUFMODE0_bp 6 /* Buffer Modes bit 0 position. */ -#define SPI_BUFMODE1_bm (1<<7) /* Buffer Modes bit 1 mask. */ -#define SPI_BUFMODE1_bp 7 /* Buffer Modes bit 1 position. */ - -#define SPI_SSD_bm 0x04 /* Slave Select Disable bit mask. */ -#define SPI_SSD_bp 2 /* Slave Select Disable bit position. */ - -/* IRCOM - IR Communication Module */ -/* IRCOM.CTRL bit masks and bit positions */ -#define IRCOM_EVSEL_gm 0x0F /* Event Channel Select group mask. */ -#define IRCOM_EVSEL_gp 0 /* Event Channel Select group position. */ -#define IRCOM_EVSEL0_bm (1<<0) /* Event Channel Select bit 0 mask. */ -#define IRCOM_EVSEL0_bp 0 /* Event Channel Select bit 0 position. */ -#define IRCOM_EVSEL1_bm (1<<1) /* Event Channel Select bit 1 mask. */ -#define IRCOM_EVSEL1_bp 1 /* Event Channel Select bit 1 position. */ -#define IRCOM_EVSEL2_bm (1<<2) /* Event Channel Select bit 2 mask. */ -#define IRCOM_EVSEL2_bp 2 /* Event Channel Select bit 2 position. */ -#define IRCOM_EVSEL3_bm (1<<3) /* Event Channel Select bit 3 mask. */ -#define IRCOM_EVSEL3_bp 3 /* Event Channel Select bit 3 position. */ - -/* FUSE - Fuses and Lockbits */ -/* NVM_LOCKBITS.LOCKBITS bit masks and bit positions */ -#define NVM_LOCKBITS_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ -#define NVM_LOCKBITS_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ -#define NVM_LOCKBITS_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ -#define NVM_LOCKBITS_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ -#define NVM_LOCKBITS_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ -#define NVM_LOCKBITS_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ - -#define NVM_LOCKBITS_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ -#define NVM_LOCKBITS_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ -#define NVM_LOCKBITS_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ -#define NVM_LOCKBITS_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ -#define NVM_LOCKBITS_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ -#define NVM_LOCKBITS_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ - -#define NVM_LOCKBITS_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ -#define NVM_LOCKBITS_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ -#define NVM_LOCKBITS_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ -#define NVM_LOCKBITS_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ -#define NVM_LOCKBITS_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ -#define NVM_LOCKBITS_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ - -#define NVM_LOCKBITS_LB_gm 0x03 /* Lock Bits group mask. */ -#define NVM_LOCKBITS_LB_gp 0 /* Lock Bits group position. */ -#define NVM_LOCKBITS_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ -#define NVM_LOCKBITS_LB0_bp 0 /* Lock Bits bit 0 position. */ -#define NVM_LOCKBITS_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ -#define NVM_LOCKBITS_LB1_bp 1 /* Lock Bits bit 1 position. */ - -/* NVM_FUSES.FUSEBYTE1 bit masks and bit positions */ -#define NVM_FUSES_WDWP_gm 0xF0 /* Watchdog Window Timeout Period group mask. */ -#define NVM_FUSES_WDWP_gp 4 /* Watchdog Window Timeout Period group position. */ -#define NVM_FUSES_WDWP0_bm (1<<4) /* Watchdog Window Timeout Period bit 0 mask. */ -#define NVM_FUSES_WDWP0_bp 4 /* Watchdog Window Timeout Period bit 0 position. */ -#define NVM_FUSES_WDWP1_bm (1<<5) /* Watchdog Window Timeout Period bit 1 mask. */ -#define NVM_FUSES_WDWP1_bp 5 /* Watchdog Window Timeout Period bit 1 position. */ -#define NVM_FUSES_WDWP2_bm (1<<6) /* Watchdog Window Timeout Period bit 2 mask. */ -#define NVM_FUSES_WDWP2_bp 6 /* Watchdog Window Timeout Period bit 2 position. */ -#define NVM_FUSES_WDWP3_bm (1<<7) /* Watchdog Window Timeout Period bit 3 mask. */ -#define NVM_FUSES_WDWP3_bp 7 /* Watchdog Window Timeout Period bit 3 position. */ - -#define NVM_FUSES_WDP_gm 0x0F /* Watchdog Timeout Period group mask. */ -#define NVM_FUSES_WDP_gp 0 /* Watchdog Timeout Period group position. */ -#define NVM_FUSES_WDP0_bm (1<<0) /* Watchdog Timeout Period bit 0 mask. */ -#define NVM_FUSES_WDP0_bp 0 /* Watchdog Timeout Period bit 0 position. */ -#define NVM_FUSES_WDP1_bm (1<<1) /* Watchdog Timeout Period bit 1 mask. */ -#define NVM_FUSES_WDP1_bp 1 /* Watchdog Timeout Period bit 1 position. */ -#define NVM_FUSES_WDP2_bm (1<<2) /* Watchdog Timeout Period bit 2 mask. */ -#define NVM_FUSES_WDP2_bp 2 /* Watchdog Timeout Period bit 2 position. */ -#define NVM_FUSES_WDP3_bm (1<<3) /* Watchdog Timeout Period bit 3 mask. */ -#define NVM_FUSES_WDP3_bp 3 /* Watchdog Timeout Period bit 3 position. */ - -/* NVM_FUSES.FUSEBYTE2 bit masks and bit positions */ -#define NVM_FUSES_BOOTRST_bm 0x40 /* Boot Loader Section Reset Vector bit mask. */ -#define NVM_FUSES_BOOTRST_bp 6 /* Boot Loader Section Reset Vector bit position. */ - -#define NVM_FUSES_BODPD_gm 0x03 /* BOD Operation in Power-Down Mode group mask. */ -#define NVM_FUSES_BODPD_gp 0 /* BOD Operation in Power-Down Mode group position. */ -#define NVM_FUSES_BODPD0_bm (1<<0) /* BOD Operation in Power-Down Mode bit 0 mask. */ -#define NVM_FUSES_BODPD0_bp 0 /* BOD Operation in Power-Down Mode bit 0 position. */ -#define NVM_FUSES_BODPD1_bm (1<<1) /* BOD Operation in Power-Down Mode bit 1 mask. */ -#define NVM_FUSES_BODPD1_bp 1 /* BOD Operation in Power-Down Mode bit 1 position. */ - -/* NVM_FUSES.FUSEBYTE4 bit masks and bit positions */ -#define NVM_FUSES_RSTDISBL_bm 0x10 /* External Reset Disable bit mask. */ -#define NVM_FUSES_RSTDISBL_bp 4 /* External Reset Disable bit position. */ - -#define NVM_FUSES_SUT_gm 0x0C /* Start-up Time group mask. */ -#define NVM_FUSES_SUT_gp 2 /* Start-up Time group position. */ -#define NVM_FUSES_SUT0_bm (1<<2) /* Start-up Time bit 0 mask. */ -#define NVM_FUSES_SUT0_bp 2 /* Start-up Time bit 0 position. */ -#define NVM_FUSES_SUT1_bm (1<<3) /* Start-up Time bit 1 mask. */ -#define NVM_FUSES_SUT1_bp 3 /* Start-up Time bit 1 position. */ - -#define NVM_FUSES_WDLOCK_bm 0x02 /* Watchdog Timer Lock bit mask. */ -#define NVM_FUSES_WDLOCK_bp 1 /* Watchdog Timer Lock bit position. */ - -/* NVM_FUSES.FUSEBYTE5 bit masks and bit positions */ -#define NVM_FUSES_BODACT_gm 0x30 /* BOD Operation in Active Mode group mask. */ -#define NVM_FUSES_BODACT_gp 4 /* BOD Operation in Active Mode group position. */ -#define NVM_FUSES_BODACT0_bm (1<<4) /* BOD Operation in Active Mode bit 0 mask. */ -#define NVM_FUSES_BODACT0_bp 4 /* BOD Operation in Active Mode bit 0 position. */ -#define NVM_FUSES_BODACT1_bm (1<<5) /* BOD Operation in Active Mode bit 1 mask. */ -#define NVM_FUSES_BODACT1_bp 5 /* BOD Operation in Active Mode bit 1 position. */ - -#define NVM_FUSES_EESAVE_bm 0x08 /* Preserve EEPROM Through Chip Erase bit mask. */ -#define NVM_FUSES_EESAVE_bp 3 /* Preserve EEPROM Through Chip Erase bit position. */ - -#define NVM_FUSES_BODLVL_gm 0x07 /* Brownout Detection Voltage Level group mask. */ -#define NVM_FUSES_BODLVL_gp 0 /* Brownout Detection Voltage Level group position. */ -#define NVM_FUSES_BODLVL0_bm (1<<0) /* Brownout Detection Voltage Level bit 0 mask. */ -#define NVM_FUSES_BODLVL0_bp 0 /* Brownout Detection Voltage Level bit 0 position. */ -#define NVM_FUSES_BODLVL1_bm (1<<1) /* Brownout Detection Voltage Level bit 1 mask. */ -#define NVM_FUSES_BODLVL1_bp 1 /* Brownout Detection Voltage Level bit 1 position. */ -#define NVM_FUSES_BODLVL2_bm (1<<2) /* Brownout Detection Voltage Level bit 2 mask. */ -#define NVM_FUSES_BODLVL2_bp 2 /* Brownout Detection Voltage Level bit 2 position. */ - -/* NVM_FUSES.FUSEBYTE6 bit masks and bit positions */ -#define NVM_FUSES_FDACT5_bm 0x80 /* Fault Dectection Action on TC5 bit mask. */ -#define NVM_FUSES_FDACT5_bp 7 /* Fault Dectection Action on TC5 bit position. */ - -#define NVM_FUSES_FDACT4_bm 0x40 /* Fault Dectection Action on TC4 bit mask. */ -#define NVM_FUSES_FDACT4_bp 6 /* Fault Dectection Action on TC4 bit position. */ - -#define NVM_FUSES_VALUE_gm 0x3F /* Port Pin Value group mask. */ -#define NVM_FUSES_VALUE_gp 0 /* Port Pin Value group position. */ -#define NVM_FUSES_VALUE0_bm (1<<0) /* Port Pin Value bit 0 mask. */ -#define NVM_FUSES_VALUE0_bp 0 /* Port Pin Value bit 0 position. */ -#define NVM_FUSES_VALUE1_bm (1<<1) /* Port Pin Value bit 1 mask. */ -#define NVM_FUSES_VALUE1_bp 1 /* Port Pin Value bit 1 position. */ -#define NVM_FUSES_VALUE2_bm (1<<2) /* Port Pin Value bit 2 mask. */ -#define NVM_FUSES_VALUE2_bp 2 /* Port Pin Value bit 2 position. */ -#define NVM_FUSES_VALUE3_bm (1<<3) /* Port Pin Value bit 3 mask. */ -#define NVM_FUSES_VALUE3_bp 3 /* Port Pin Value bit 3 position. */ -#define NVM_FUSES_VALUE4_bm (1<<4) /* Port Pin Value bit 4 mask. */ -#define NVM_FUSES_VALUE4_bp 4 /* Port Pin Value bit 4 position. */ -#define NVM_FUSES_VALUE5_bm (1<<5) /* Port Pin Value bit 5 mask. */ -#define NVM_FUSES_VALUE5_bp 5 /* Port Pin Value bit 5 position. */ - - - -// Generic Port Pins - -#define PIN0_bm 0x01 -#define PIN0_bp 0 -#define PIN1_bm 0x02 -#define PIN1_bp 1 -#define PIN2_bm 0x04 -#define PIN2_bp 2 -#define PIN3_bm 0x08 -#define PIN3_bp 3 -#define PIN4_bm 0x10 -#define PIN4_bp 4 -#define PIN5_bm 0x20 -#define PIN5_bp 5 -#define PIN6_bm 0x40 -#define PIN6_bp 6 -#define PIN7_bm 0x80 -#define PIN7_bp 7 - -/* ========== Interrupt Vector Definitions ========== */ -/* Vector 0 is the reset vector */ - -/* OSC interrupt vectors */ -#define OSC_OSCF_vect_num 1 -#define OSC_OSCF_vect _VECTOR(1) /* Oscillator Failure Interrupt (NMI) */ - -/* PORTR interrupt vectors */ -#define PORTR_INT_vect_num 2 -#define PORTR_INT_vect _VECTOR(2) /* External Interrupt */ - -/* EDMA interrupt vectors */ -#define EDMA_CH0_vect_num 3 -#define EDMA_CH0_vect _VECTOR(3) /* EDMA Channel 0 Interrupt */ -#define EDMA_CH1_vect_num 4 -#define EDMA_CH1_vect _VECTOR(4) /* EDMA Channel 1 Interrupt */ -#define EDMA_CH2_vect_num 5 -#define EDMA_CH2_vect _VECTOR(5) /* EDMA Channel 2 Interrupt */ -#define EDMA_CH3_vect_num 6 -#define EDMA_CH3_vect _VECTOR(6) /* EDMA Channel 3 Interrupt */ - -/* RTC interrupt vectors */ -#define RTC_OVF_vect_num 7 -#define RTC_OVF_vect _VECTOR(7) /* Overflow Interrupt */ -#define RTC_COMP_vect_num 8 -#define RTC_COMP_vect _VECTOR(8) /* Compare Interrupt */ - -/* PORTC interrupt vectors */ -#define PORTC_INT_vect_num 9 -#define PORTC_INT_vect _VECTOR(9) /* External Interrupt */ - -/* TWIC interrupt vectors */ -#define TWIC_TWIS_vect_num 10 -#define TWIC_TWIS_vect _VECTOR(10) /* TWI Slave Interrupt */ -#define TWIC_TWIM_vect_num 11 -#define TWIC_TWIM_vect _VECTOR(11) /* TWI Master Interrupt */ - -/* TCC4 interrupt vectors */ -#define TCC4_OVF_vect_num 12 -#define TCC4_OVF_vect _VECTOR(12) /* Overflow Interrupt */ -#define TCC4_ERR_vect_num 13 -#define TCC4_ERR_vect _VECTOR(13) /* Error Interrupt */ -#define TCC4_CCA_vect_num 14 -#define TCC4_CCA_vect _VECTOR(14) /* Channel A Compare or Capture Interrupt */ -#define TCC4_CCB_vect_num 15 -#define TCC4_CCB_vect _VECTOR(15) /* Channel B Compare or Capture Interrupt */ -#define TCC4_CCC_vect_num 16 -#define TCC4_CCC_vect _VECTOR(16) /* Channel C Compare or Capture Interrupt */ -#define TCC4_CCD_vect_num 17 -#define TCC4_CCD_vect _VECTOR(17) /* Channel D Compare or Capture Interrupt */ - -/* TCC5 interrupt vectors */ -#define TCC5_OVF_vect_num 18 -#define TCC5_OVF_vect _VECTOR(18) /* Overflow Interrupt */ -#define TCC5_ERR_vect_num 19 -#define TCC5_ERR_vect _VECTOR(19) /* Error Interrupt */ -#define TCC5_CCA_vect_num 20 -#define TCC5_CCA_vect _VECTOR(20) /* Channel A Compare or Capture Interrupt */ -#define TCC5_CCB_vect_num 21 -#define TCC5_CCB_vect _VECTOR(21) /* Channel B Compare or Capture Interrupt */ - -/* SPIC interrupt vectors */ -#define SPIC_INT_vect_num 22 -#define SPIC_INT_vect _VECTOR(22) /* SPI Interrupt */ - -/* USARTC0 interrupt vectors */ -#define USARTC0_RXC_vect_num 23 -#define USARTC0_RXC_vect _VECTOR(23) /* Reception Complete Interrupt */ -#define USARTC0_DRE_vect_num 24 -#define USARTC0_DRE_vect _VECTOR(24) /* Data Register Empty Interrupt */ -#define USARTC0_TXC_vect_num 25 -#define USARTC0_TXC_vect _VECTOR(25) /* Transmission Complete Interrupt */ - -/* NVM interrupt vectors */ -#define NVM_EE_vect_num 26 -#define NVM_EE_vect _VECTOR(26) /* EE Interrupt */ -#define NVM_SPM_vect_num 27 -#define NVM_SPM_vect _VECTOR(27) /* SPM Interrupt */ - -/* XCL interrupt vectors */ -#define XCL_UNF_vect_num 28 -#define XCL_UNF_vect _VECTOR(28) /* Timer/Counter Underflow Interrupt */ -#define XCL_CC_vect_num 29 -#define XCL_CC_vect _VECTOR(29) /* Timer/Counter Compare or Capture Interrupt */ - -/* PORTA interrupt vectors */ -#define PORTA_INT_vect_num 30 -#define PORTA_INT_vect _VECTOR(30) /* External Interrupt */ - -/* ACA interrupt vectors */ -#define ACA_AC0_vect_num 31 -#define ACA_AC0_vect _VECTOR(31) /* AC0 Interrupt */ -#define ACA_AC1_vect_num 32 -#define ACA_AC1_vect _VECTOR(32) /* AC1 Interrupt */ -#define ACA_ACW_vect_num 33 -#define ACA_ACW_vect _VECTOR(33) /* ACW Window Mode Interrupt */ - -/* ADCA interrupt vectors */ -#define ADCA_CH0_vect_num 34 -#define ADCA_CH0_vect _VECTOR(34) /* ADC Channel Interrupt */ - -/* PORTD interrupt vectors */ -#define PORTD_INT_vect_num 35 -#define PORTD_INT_vect _VECTOR(35) /* External Interrupt */ - -/* TCD5 interrupt vectors */ -#define TCD5_OVF_vect_num 36 -#define TCD5_OVF_vect _VECTOR(36) /* Overflow Interrupt */ -#define TCD5_ERR_vect_num 37 -#define TCD5_ERR_vect _VECTOR(37) /* Error Interrupt */ -#define TCD5_CCA_vect_num 38 -#define TCD5_CCA_vect _VECTOR(38) /* Channel A Compare or Capture Interrupt */ -#define TCD5_CCB_vect_num 39 -#define TCD5_CCB_vect _VECTOR(39) /* Channel B Compare or Capture Interrupt */ - -/* USARTD0 interrupt vectors */ -#define USARTD0_RXC_vect_num 40 -#define USARTD0_RXC_vect _VECTOR(40) /* Reception Complete Interrupt */ -#define USARTD0_DRE_vect_num 41 -#define USARTD0_DRE_vect _VECTOR(41) /* Data Register Empty Interrupt */ -#define USARTD0_TXC_vect_num 42 -#define USARTD0_TXC_vect _VECTOR(42) /* Transmission Complete Interrupt */ - -#define _VECTOR_SIZE 4 /* Size of individual vector. */ -#define _VECTORS_SIZE (43 * _VECTOR_SIZE) - - -/* ========== Constants ========== */ - -#define PROGMEM_START (0x0000) -#define PROGMEM_SIZE (36864) -#define PROGMEM_END (PROGMEM_START + PROGMEM_SIZE - 1) - -#define APP_SECTION_START (0x0000) -#define APP_SECTION_SIZE (32768) -#define APP_SECTION_PAGE_SIZE (128) -#define APP_SECTION_END (APP_SECTION_START + APP_SECTION_SIZE - 1) - -#define APPTABLE_SECTION_START (0x7000) -#define APPTABLE_SECTION_SIZE (4096) -#define APPTABLE_SECTION_PAGE_SIZE (128) -#define APPTABLE_SECTION_END (APPTABLE_SECTION_START + APPTABLE_SECTION_SIZE - 1) - -#define BOOT_SECTION_START (0x8000) -#define BOOT_SECTION_SIZE (4096) -#define BOOT_SECTION_PAGE_SIZE (128) -#define BOOT_SECTION_END (BOOT_SECTION_START + BOOT_SECTION_SIZE - 1) - -#define DATAMEM_START (0x0000) -#define DATAMEM_SIZE (12288) -#define DATAMEM_END (DATAMEM_START + DATAMEM_SIZE - 1) - -#define IO_START (0x0000) -#define IO_SIZE (4096) -#define IO_PAGE_SIZE (0) -#define IO_END (IO_START + IO_SIZE - 1) - -#define MAPPED_EEPROM_START (0x1000) -#define MAPPED_EEPROM_SIZE (1024) -#define MAPPED_EEPROM_PAGE_SIZE (0) -#define MAPPED_EEPROM_END (MAPPED_EEPROM_START + MAPPED_EEPROM_SIZE - 1) - -#define INTERNAL_SRAM_START (0x2000) -#define INTERNAL_SRAM_SIZE (4096) -#define INTERNAL_SRAM_PAGE_SIZE (0) -#define INTERNAL_SRAM_END (INTERNAL_SRAM_START + INTERNAL_SRAM_SIZE - 1) - -#define EEPROM_START (0x0000) -#define EEPROM_SIZE (1024) -#define EEPROM_PAGE_SIZE (32) -#define EEPROM_END (EEPROM_START + EEPROM_SIZE - 1) - -#define SIGNATURES_START (0x0000) -#define SIGNATURES_SIZE (3) -#define SIGNATURES_PAGE_SIZE (0) -#define SIGNATURES_END (SIGNATURES_START + SIGNATURES_SIZE - 1) - -#define FUSES_START (0x0000) -#define FUSES_SIZE (7) -#define FUSES_PAGE_SIZE (0) -#define FUSES_END (FUSES_START + FUSES_SIZE - 1) - -#define LOCKBITS_START (0x0000) -#define LOCKBITS_SIZE (1) -#define LOCKBITS_PAGE_SIZE (0) -#define LOCKBITS_END (LOCKBITS_START + LOCKBITS_SIZE - 1) - -#define USER_SIGNATURES_START (0x0000) -#define USER_SIGNATURES_SIZE (128) -#define USER_SIGNATURES_PAGE_SIZE (128) -#define USER_SIGNATURES_END (USER_SIGNATURES_START + USER_SIGNATURES_SIZE - 1) - -#define PROD_SIGNATURES_START (0x0000) -#define PROD_SIGNATURES_SIZE (54) -#define PROD_SIGNATURES_PAGE_SIZE (128) -#define PROD_SIGNATURES_END (PROD_SIGNATURES_START + PROD_SIGNATURES_SIZE - 1) - -#define FLASHSTART PROGMEM_START -#define FLASHEND PROGMEM_END -#define SPM_PAGESIZE 128 -#define RAMSTART INTERNAL_SRAM_START -#define RAMSIZE INTERNAL_SRAM_SIZE -#define RAMEND INTERNAL_SRAM_END -#define E2END EEPROM_END -#define E2PAGESIZE EEPROM_PAGE_SIZE - - -/* ========== Fuses ========== */ -#define FUSE_MEMORY_SIZE 7 - -/* Fuse Byte 0 Reserved */ - -/* Fuse Byte 1 */ -#define FUSE_WDP0 (unsigned char)~_BV(0) /* Watchdog Timeout Period Bit 0 */ -#define FUSE_WDP1 (unsigned char)~_BV(1) /* Watchdog Timeout Period Bit 1 */ -#define FUSE_WDP2 (unsigned char)~_BV(2) /* Watchdog Timeout Period Bit 2 */ -#define FUSE_WDP3 (unsigned char)~_BV(3) /* Watchdog Timeout Period Bit 3 */ -#define FUSE_WDWP0 (unsigned char)~_BV(4) /* Watchdog Window Timeout Period Bit 0 */ -#define FUSE_WDWP1 (unsigned char)~_BV(5) /* Watchdog Window Timeout Period Bit 1 */ -#define FUSE_WDWP2 (unsigned char)~_BV(6) /* Watchdog Window Timeout Period Bit 2 */ -#define FUSE_WDWP3 (unsigned char)~_BV(7) /* Watchdog Window Timeout Period Bit 3 */ -#define FUSE1_DEFAULT (0xFF) - -/* Fuse Byte 2 */ -#define FUSE_BODPD0 (unsigned char)~_BV(0) /* BOD Operation in Power-Down Mode Bit 0 */ -#define FUSE_BODPD1 (unsigned char)~_BV(1) /* BOD Operation in Power-Down Mode Bit 1 */ -#define FUSE_BOOTRST (unsigned char)~_BV(6) /* Boot Loader Section Reset Vector */ -#define FUSE2_DEFAULT (0xFF) - -/* Fuse Byte 3 Reserved */ - -/* Fuse Byte 4 */ -#define FUSE_WDLOCK (unsigned char)~_BV(1) /* Watchdog Timer Lock */ -#define FUSE_SUT0 (unsigned char)~_BV(2) /* Start-up Time Bit 0 */ -#define FUSE_SUT1 (unsigned char)~_BV(3) /* Start-up Time Bit 1 */ -#define FUSE_RSTDISBL (unsigned char)~_BV(4) /* External Reset Disable */ -#define FUSE4_DEFAULT (0xFF) - -/* Fuse Byte 5 */ -#define FUSE_BODLVL0 (unsigned char)~_BV(0) /* Brownout Detection Voltage Level Bit 0 */ -#define FUSE_BODLVL1 (unsigned char)~_BV(1) /* Brownout Detection Voltage Level Bit 1 */ -#define FUSE_BODLVL2 (unsigned char)~_BV(2) /* Brownout Detection Voltage Level Bit 2 */ -#define FUSE_EESAVE (unsigned char)~_BV(3) /* Preserve EEPROM Through Chip Erase */ -#define FUSE_BODACT0 (unsigned char)~_BV(4) /* BOD Operation in Active Mode Bit 0 */ -#define FUSE_BODACT1 (unsigned char)~_BV(5) /* BOD Operation in Active Mode Bit 1 */ -#define FUSE5_DEFAULT (0xFF) - -/* Fuse Byte 6 */ -#define FUSE_VALUE0 (unsigned char)~_BV(0) /* Port Pin Value Bit 0 */ -#define FUSE_VALUE1 (unsigned char)~_BV(1) /* Port Pin Value Bit 1 */ -#define FUSE_VALUE2 (unsigned char)~_BV(2) /* Port Pin Value Bit 2 */ -#define FUSE_VALUE3 (unsigned char)~_BV(3) /* Port Pin Value Bit 3 */ -#define FUSE_VALUE4 (unsigned char)~_BV(4) /* Port Pin Value Bit 4 */ -#define FUSE_VALUE5 (unsigned char)~_BV(5) /* Port Pin Value Bit 5 */ -#define FUSE_FDACT4 (unsigned char)~_BV(6) /* Fault Dectection Action on TC4 */ -#define FUSE_FDACT5 (unsigned char)~_BV(7) /* Fault Dectection Action on TC5 */ -#define FUSE6_DEFAULT (0xFF) - -/* ========== Lock Bits ========== */ -#define __LOCK_BITS_EXIST -#define __BOOT_LOCK_APPLICATION_TABLE_BITS_EXIST -#define __BOOT_LOCK_APPLICATION_BITS_EXIST -#define __BOOT_LOCK_BOOT_BITS_EXIST - -/* ========== Signature ========== */ -#define SIGNATURE_0 0x1E -#define SIGNATURE_1 0x95 -#define SIGNATURE_2 0x4C - -/* ========== Power Reduction Condition Definitions ========== */ - -/* PR.PRGEN */ -#define __AVR_HAVE_PRGEN (PR_XCL_bm|PR_RTC_bm|PR_EVSYS_bm|PR_EDMA_bm) -#define __AVR_HAVE_PRGEN_XCL -#define __AVR_HAVE_PRGEN_RTC -#define __AVR_HAVE_PRGEN_EVSYS -#define __AVR_HAVE_PRGEN_EDMA - -/* PR.PRPA */ -#define __AVR_HAVE_PRPA (PR_DAC_bm|PR_ADC_bm|PR_AC_bm) -#define __AVR_HAVE_PRPA_DAC -#define __AVR_HAVE_PRPA_ADC -#define __AVR_HAVE_PRPA_AC - -/* PR.PRPC */ -#define __AVR_HAVE_PRPC (PR_TWI_bm|PR_USART0_bm|PR_SPI_bm|PR_HIRES_bm|PR_TC5_bm|PR_TC4_bm) -#define __AVR_HAVE_PRPC_TWI -#define __AVR_HAVE_PRPC_USART0 -#define __AVR_HAVE_PRPC_SPI -#define __AVR_HAVE_PRPC_HIRES -#define __AVR_HAVE_PRPC_TC5 -#define __AVR_HAVE_PRPC_TC4 - -/* PR.PRPD */ -#define __AVR_HAVE_PRPD (PR_USART0_bm|PR_TC5_bm) -#define __AVR_HAVE_PRPD_USART0 -#define __AVR_HAVE_PRPD_TC5 - - -#endif /* #ifdef _AVR_ATXMEGA32E5_H_INCLUDED */ - diff --git a/arduino/hardware/tools/avr/avr/include/avr/iox384c3.h b/arduino/hardware/tools/avr/avr/include/avr/iox384c3.h deleted file mode 100644 index 9377281..0000000 --- a/arduino/hardware/tools/avr/avr/include/avr/iox384c3.h +++ /dev/null @@ -1,6849 +0,0 @@ -/***************************************************************************** - * - * Copyright (C) 2015 Atmel Corporation - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * - * * Neither the name of the copyright holders nor the names of - * contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - ****************************************************************************/ - - -#ifndef _AVR_IO_H_ -# error "Include instead of this file." -#endif - -#ifndef _AVR_IOXXX_H_ -# define _AVR_IOXXX_H_ "iox384c3.h" -#else -# error "Attempt to include more than one file." -#endif - -#ifndef _AVR_ATXMEGA384C3_H_INCLUDED -#define _AVR_ATXMEGA384C3_H_INCLUDED - -/* Ungrouped common registers */ -#define GPIOR0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ -#define GPIOR1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ -#define GPIOR2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ -#define GPIOR3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ - -/* Deprecated */ -#define GPIO0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ -#define GPIO1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ -#define GPIO2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ -#define GPIO3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ - -#define CCP _SFR_MEM8(0x0034) /* Configuration Change Protection */ -#define RAMPD _SFR_MEM8(0x0038) /* Ramp D */ -#define RAMPX _SFR_MEM8(0x0039) /* Ramp X */ -#define RAMPY _SFR_MEM8(0x003A) /* Ramp Y */ -#define RAMPZ _SFR_MEM8(0x003B) /* Ramp Z */ -#define EIND _SFR_MEM8(0x003C) /* Extended Indirect Jump */ -#define SPL _SFR_MEM8(0x003D) /* Stack Pointer Low */ -#define SPH _SFR_MEM8(0x003E) /* Stack Pointer High */ -#define SREG _SFR_MEM8(0x003F) /* Status Register */ - -/* C Language Only */ -#if !defined (__ASSEMBLER__) - -#include - -typedef volatile uint8_t register8_t; -typedef volatile uint16_t register16_t; -typedef volatile uint32_t register32_t; - - -#ifdef _WORDREGISTER -#undef _WORDREGISTER -#endif -#define _WORDREGISTER(regname) \ - __extension__ union \ - { \ - register16_t regname; \ - struct \ - { \ - register8_t regname ## L; \ - register8_t regname ## H; \ - }; \ - } - -#ifdef _DWORDREGISTER -#undef _DWORDREGISTER -#endif -#define _DWORDREGISTER(regname) \ - __extension__ union \ - { \ - register32_t regname; \ - struct \ - { \ - register8_t regname ## 0; \ - register8_t regname ## 1; \ - register8_t regname ## 2; \ - register8_t regname ## 3; \ - }; \ - } - - -/* -========================================================================== -IO Module Structures -========================================================================== -*/ - - -/* --------------------------------------------------------------------------- -VPORT - Virtual Ports --------------------------------------------------------------------------- -*/ - -/* Virtual Port */ -typedef struct VPORT_struct -{ - register8_t DIR; /* I/O Port Data Direction */ - register8_t OUT; /* I/O Port Output */ - register8_t IN; /* I/O Port Input */ - register8_t INTFLAGS; /* Interrupt Flag Register */ -} VPORT_t; - - -/* --------------------------------------------------------------------------- -XOCD - On-Chip Debug System --------------------------------------------------------------------------- -*/ - -/* On-Chip Debug System */ -typedef struct OCD_struct -{ - register8_t OCDR0; /* OCD Register 0 */ - register8_t OCDR1; /* OCD Register 1 */ -} OCD_t; - - -/* --------------------------------------------------------------------------- -CPU - CPU --------------------------------------------------------------------------- -*/ - -/* CCP signatures */ -typedef enum CCP_enum -{ - CCP_SPM_gc = (0x9D<<0), /* SPM Instruction Protection */ - CCP_IOREG_gc = (0xD8<<0), /* IO Register Protection */ -} CCP_t; - - -/* --------------------------------------------------------------------------- -CLK - Clock System --------------------------------------------------------------------------- -*/ - -/* Clock System */ -typedef struct CLK_struct -{ - register8_t CTRL; /* Control Register */ - register8_t PSCTRL; /* Prescaler Control Register */ - register8_t LOCK; /* Lock register */ - register8_t RTCCTRL; /* RTC Control Register */ - register8_t USBCTRL; /* USB Control Register */ -} CLK_t; - - -/* Power Reduction */ -typedef struct PR_struct -{ - register8_t PRGEN; /* General Power Reduction */ - register8_t PRPA; /* Power Reduction Port A */ - register8_t PRPB; /* Power Reduction Port B */ - register8_t PRPC; /* Power Reduction Port C */ - register8_t PRPD; /* Power Reduction Port D */ - register8_t PRPE; /* Power Reduction Port E */ - register8_t PRPF; /* Power Reduction Port F */ -} PR_t; - -/* System Clock Selection */ -typedef enum CLK_SCLKSEL_enum -{ - CLK_SCLKSEL_RC2M_gc = (0x00<<0), /* Internal 2 MHz RC Oscillator */ - CLK_SCLKSEL_RC32M_gc = (0x01<<0), /* Internal 32 MHz RC Oscillator */ - CLK_SCLKSEL_RC32K_gc = (0x02<<0), /* Internal 32.768 kHz RC Oscillator */ - CLK_SCLKSEL_XOSC_gc = (0x03<<0), /* External Crystal Oscillator or Clock */ - CLK_SCLKSEL_PLL_gc = (0x04<<0), /* Phase Locked Loop */ -} CLK_SCLKSEL_t; - -/* Prescaler A Division Factor */ -typedef enum CLK_PSADIV_enum -{ - CLK_PSADIV_1_gc = (0x00<<2), /* Divide by 1 */ - CLK_PSADIV_2_gc = (0x01<<2), /* Divide by 2 */ - CLK_PSADIV_4_gc = (0x03<<2), /* Divide by 4 */ - CLK_PSADIV_8_gc = (0x05<<2), /* Divide by 8 */ - CLK_PSADIV_16_gc = (0x07<<2), /* Divide by 16 */ - CLK_PSADIV_32_gc = (0x09<<2), /* Divide by 32 */ - CLK_PSADIV_64_gc = (0x0B<<2), /* Divide by 64 */ - CLK_PSADIV_128_gc = (0x0D<<2), /* Divide by 128 */ - CLK_PSADIV_256_gc = (0x0F<<2), /* Divide by 256 */ - CLK_PSADIV_512_gc = (0x11<<2), /* Divide by 512 */ -} CLK_PSADIV_t; - -/* Prescaler B and C Division Factor */ -typedef enum CLK_PSBCDIV_enum -{ - CLK_PSBCDIV_1_1_gc = (0x00<<0), /* Divide B by 1 and C by 1 */ - CLK_PSBCDIV_1_2_gc = (0x01<<0), /* Divide B by 1 and C by 2 */ - CLK_PSBCDIV_4_1_gc = (0x02<<0), /* Divide B by 4 and C by 1 */ - CLK_PSBCDIV_2_2_gc = (0x03<<0), /* Divide B by 2 and C by 2 */ -} CLK_PSBCDIV_t; - -/* RTC Clock Source */ -typedef enum CLK_RTCSRC_enum -{ - CLK_RTCSRC_ULP_gc = (0x00<<1), /* 1.024 kHz from internal 32kHz ULP */ - CLK_RTCSRC_TOSC_gc = (0x01<<1), /* 1.024 kHz from 32.768 kHz crystal oscillator on TOSC */ - CLK_RTCSRC_RCOSC_gc = (0x02<<1), /* 1.024 kHz from internal 32.768 kHz RC oscillator */ - CLK_RTCSRC_TOSC32_gc = (0x05<<1), /* 32.768 kHz from 32.768 kHz crystal oscillator on TOSC */ - CLK_RTCSRC_RCOSC32_gc = (0x06<<1), /* 32.768 kHz from internal 32.768 kHz RC oscillator */ - CLK_RTCSRC_EXTCLK_gc = (0x07<<1), /* External Clock from TOSC1 */ -} CLK_RTCSRC_t; - -/* USB Prescaler Division Factor */ -typedef enum CLK_USBPSDIV_enum -{ - CLK_USBPSDIV_1_gc = (0x00<<3), /* Divide by 1 */ - CLK_USBPSDIV_2_gc = (0x01<<3), /* Divide by 2 */ - CLK_USBPSDIV_4_gc = (0x02<<3), /* Divide by 4 */ - CLK_USBPSDIV_8_gc = (0x03<<3), /* Divide by 8 */ - CLK_USBPSDIV_16_gc = (0x04<<3), /* Divide by 16 */ - CLK_USBPSDIV_32_gc = (0x05<<3), /* Divide by 32 */ -} CLK_USBPSDIV_t; - -/* USB Clock Source */ -typedef enum CLK_USBSRC_enum -{ - CLK_USBSRC_PLL_gc = (0x00<<1), /* PLL */ - CLK_USBSRC_RC32M_gc = (0x01<<1), /* Internal 32 MHz RC Oscillator */ -} CLK_USBSRC_t; - - -/* --------------------------------------------------------------------------- -SLEEP - Sleep Controller --------------------------------------------------------------------------- -*/ - -/* Sleep Controller */ -typedef struct SLEEP_struct -{ - register8_t CTRL; /* Control Register */ -} SLEEP_t; - -/* Sleep Mode */ -typedef enum SLEEP_SMODE_enum -{ - SLEEP_SMODE_IDLE_gc = (0x00<<1), /* Idle mode */ - SLEEP_SMODE_PDOWN_gc = (0x02<<1), /* Power-down Mode */ - SLEEP_SMODE_PSAVE_gc = (0x03<<1), /* Power-save Mode */ - SLEEP_SMODE_STDBY_gc = (0x06<<1), /* Standby Mode */ - SLEEP_SMODE_ESTDBY_gc = (0x07<<1), /* Extended Standby Mode */ -} SLEEP_SMODE_t; - - - -#define SLEEP_MODE_IDLE (0x00<<1) -#define SLEEP_MODE_PWR_DOWN (0x02<<1) -#define SLEEP_MODE_PWR_SAVE (0x03<<1) -#define SLEEP_MODE_STANDBY (0x06<<1) -#define SLEEP_MODE_EXT_STANDBY (0x07<<1) -/* --------------------------------------------------------------------------- -OSC - Oscillator --------------------------------------------------------------------------- -*/ - -/* Oscillator */ -typedef struct OSC_struct -{ - register8_t CTRL; /* Control Register */ - register8_t STATUS; /* Status Register */ - register8_t XOSCCTRL; /* External Oscillator Control Register */ - register8_t XOSCFAIL; /* Oscillator Failure Detection Register */ - register8_t RC32KCAL; /* 32.768 kHz Internal Oscillator Calibration Register */ - register8_t PLLCTRL; /* PLL Control Register */ - register8_t DFLLCTRL; /* DFLL Control Register */ -} OSC_t; - -/* Oscillator Frequency Range */ -typedef enum OSC_FRQRANGE_enum -{ - OSC_FRQRANGE_04TO2_gc = (0x00<<6), /* 0.4 - 2 MHz */ - OSC_FRQRANGE_2TO9_gc = (0x01<<6), /* 2 - 9 MHz */ - OSC_FRQRANGE_9TO12_gc = (0x02<<6), /* 9 - 12 MHz */ - OSC_FRQRANGE_12TO16_gc = (0x03<<6), /* 12 - 16 MHz */ -} OSC_FRQRANGE_t; - -/* External Oscillator Selection and Startup Time */ -typedef enum OSC_XOSCSEL_enum -{ - OSC_XOSCSEL_EXTCLK_gc = (0x00<<0), /* External Clock - 6 CLK */ - OSC_XOSCSEL_32KHz_gc = (0x02<<0), /* 32.768 kHz TOSC - 32K CLK */ - OSC_XOSCSEL_XTAL_256CLK_gc = (0x03<<0), /* 0.4-16 MHz XTAL - 256 CLK */ - OSC_XOSCSEL_XTAL_1KCLK_gc = (0x07<<0), /* 0.4-16 MHz XTAL - 1K CLK */ - OSC_XOSCSEL_XTAL_16KCLK_gc = (0x0B<<0), /* 0.4-16 MHz XTAL - 16K CLK */ -} OSC_XOSCSEL_t; - -/* PLL Clock Source */ -typedef enum OSC_PLLSRC_enum -{ - OSC_PLLSRC_RC2M_gc = (0x00<<6), /* Internal 2 MHz RC Oscillator */ - OSC_PLLSRC_RC32M_gc = (0x02<<6), /* Internal 32 MHz RC Oscillator */ - OSC_PLLSRC_XOSC_gc = (0x03<<6), /* External Oscillator */ -} OSC_PLLSRC_t; - -/* 2 MHz DFLL Calibration Reference */ -typedef enum OSC_RC2MCREF_enum -{ - OSC_RC2MCREF_RC32K_gc = (0x00<<0), /* Internal 32.768 kHz RC Oscillator */ - OSC_RC2MCREF_XOSC32K_gc = (0x01<<0), /* External 32.768 kHz Crystal Oscillator */ -} OSC_RC2MCREF_t; - -/* 32 MHz DFLL Calibration Reference */ -typedef enum OSC_RC32MCREF_enum -{ - OSC_RC32MCREF_RC32K_gc = (0x00<<1), /* Internal 32.768 kHz RC Oscillator */ - OSC_RC32MCREF_XOSC32K_gc = (0x01<<1), /* External 32.768 kHz Crystal Oscillator */ - OSC_RC32MCREF_USBSOF_gc = (0x02<<1), /* USB Start of Frame */ -} OSC_RC32MCREF_t; - - -/* --------------------------------------------------------------------------- -DFLL - DFLL --------------------------------------------------------------------------- -*/ - -/* DFLL */ -typedef struct DFLL_struct -{ - register8_t CTRL; /* Control Register */ - register8_t reserved_0x01; - register8_t CALA; /* Calibration Register A */ - register8_t CALB; /* Calibration Register B */ - register8_t COMP0; /* Oscillator Compare Register 0 */ - register8_t COMP1; /* Oscillator Compare Register 1 */ - register8_t COMP2; /* Oscillator Compare Register 2 */ - register8_t reserved_0x07; -} DFLL_t; - - -/* --------------------------------------------------------------------------- -RST - Reset --------------------------------------------------------------------------- -*/ - -/* Reset */ -typedef struct RST_struct -{ - register8_t STATUS; /* Status Register */ - register8_t CTRL; /* Control Register */ -} RST_t; - - -/* --------------------------------------------------------------------------- -WDT - Watch-Dog Timer --------------------------------------------------------------------------- -*/ - -/* Watch-Dog Timer */ -typedef struct WDT_struct -{ - register8_t CTRL; /* Control */ - register8_t WINCTRL; /* Windowed Mode Control */ - register8_t STATUS; /* Status */ -} WDT_t; - -/* Period setting */ -typedef enum WDT_PER_enum -{ - WDT_PER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ - WDT_PER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ - WDT_PER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ - WDT_PER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ - WDT_PER_128CLK_gc = (0x04<<2), /* 128 cycles (0.128s @ 3.3V) */ - WDT_PER_256CLK_gc = (0x05<<2), /* 256 cycles (0.256s @ 3.3V) */ - WDT_PER_512CLK_gc = (0x06<<2), /* 512 cycles (0.512s @ 3.3V) */ - WDT_PER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ - WDT_PER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ - WDT_PER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ - WDT_PER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ -} WDT_PER_t; - -/* Closed window period */ -typedef enum WDT_WPER_enum -{ - WDT_WPER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ - WDT_WPER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ - WDT_WPER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ - WDT_WPER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ - WDT_WPER_128CLK_gc = (0x04<<2), /* 128 cycles (0.128s @ 3.3V) */ - WDT_WPER_256CLK_gc = (0x05<<2), /* 256 cycles (0.256s @ 3.3V) */ - WDT_WPER_512CLK_gc = (0x06<<2), /* 512 cycles (0.512s @ 3.3V) */ - WDT_WPER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ - WDT_WPER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ - WDT_WPER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ - WDT_WPER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ -} WDT_WPER_t; - - -/* --------------------------------------------------------------------------- -MCU - MCU Control --------------------------------------------------------------------------- -*/ - -/* MCU Control */ -typedef struct MCU_struct -{ - register8_t DEVID0; /* Device ID byte 0 */ - register8_t DEVID1; /* Device ID byte 1 */ - register8_t DEVID2; /* Device ID byte 2 */ - register8_t REVID; /* Revision ID */ - register8_t reserved_0x04; - register8_t reserved_0x05; - register8_t reserved_0x06; - register8_t ANAINIT; /* Analog Startup Delay */ - register8_t EVSYSLOCK; /* Event System Lock */ - register8_t AWEXLOCK; /* AWEX Lock */ - register8_t reserved_0x0A; - register8_t reserved_0x0B; -} MCU_t; - - -/* --------------------------------------------------------------------------- -PMIC - Programmable Multi-level Interrupt Controller --------------------------------------------------------------------------- -*/ - -/* Programmable Multi-level Interrupt Controller */ -typedef struct PMIC_struct -{ - register8_t STATUS; /* Status Register */ - register8_t INTPRI; /* Interrupt Priority */ - register8_t CTRL; /* Control Register */ - register8_t reserved_0x03; - register8_t reserved_0x04; - register8_t reserved_0x05; - register8_t reserved_0x06; - register8_t reserved_0x07; - register8_t reserved_0x08; - register8_t reserved_0x09; - register8_t reserved_0x0A; - register8_t reserved_0x0B; - register8_t reserved_0x0C; - register8_t reserved_0x0D; - register8_t reserved_0x0E; - register8_t reserved_0x0F; -} PMIC_t; - - -/* --------------------------------------------------------------------------- -PORTCFG - Port Configuration --------------------------------------------------------------------------- -*/ - -/* I/O port Configuration */ -typedef struct PORTCFG_struct -{ - register8_t MPCMASK; /* Multi-pin Configuration Mask */ - register8_t reserved_0x01; - register8_t VPCTRLA; /* Virtual Port Control Register A */ - register8_t VPCTRLB; /* Virtual Port Control Register B */ - register8_t CLKEVOUT; /* Clock and Event Out Register */ - register8_t EBIOUT; /* EBI Output register */ - register8_t EVOUTSEL; /* Event Output Select */ -} PORTCFG_t; - -/* Virtual Port Mapping */ -typedef enum PORTCFG_VP02MAP_enum -{ - PORTCFG_VP02MAP_PORTA_gc = (0x00<<0), /* Mapped To PORTA */ - PORTCFG_VP02MAP_PORTB_gc = (0x01<<0), /* Mapped To PORTB */ - PORTCFG_VP02MAP_PORTC_gc = (0x02<<0), /* Mapped To PORTC */ - PORTCFG_VP02MAP_PORTD_gc = (0x03<<0), /* Mapped To PORTD */ - PORTCFG_VP02MAP_PORTE_gc = (0x04<<0), /* Mapped To PORTE */ - PORTCFG_VP02MAP_PORTF_gc = (0x05<<0), /* Mapped To PORTF */ - PORTCFG_VP02MAP_PORTG_gc = (0x06<<0), /* Mapped To PORTG */ - PORTCFG_VP02MAP_PORTH_gc = (0x07<<0), /* Mapped To PORTH */ - PORTCFG_VP02MAP_PORTJ_gc = (0x08<<0), /* Mapped To PORTJ */ - PORTCFG_VP02MAP_PORTK_gc = (0x09<<0), /* Mapped To PORTK */ - PORTCFG_VP02MAP_PORTL_gc = (0x0A<<0), /* Mapped To PORTL */ - PORTCFG_VP02MAP_PORTM_gc = (0x0B<<0), /* Mapped To PORTM */ - PORTCFG_VP02MAP_PORTN_gc = (0x0C<<0), /* Mapped To PORTN */ - PORTCFG_VP02MAP_PORTP_gc = (0x0D<<0), /* Mapped To PORTP */ - PORTCFG_VP02MAP_PORTQ_gc = (0x0E<<0), /* Mapped To PORTQ */ - PORTCFG_VP02MAP_PORTR_gc = (0x0F<<0), /* Mapped To PORTR */ -} PORTCFG_VP02MAP_t; - -/* Virtual Port Mapping */ -typedef enum PORTCFG_VP13MAP_enum -{ - PORTCFG_VP13MAP_PORTA_gc = (0x00<<4), /* Mapped To PORTA */ - PORTCFG_VP13MAP_PORTB_gc = (0x01<<4), /* Mapped To PORTB */ - PORTCFG_VP13MAP_PORTC_gc = (0x02<<4), /* Mapped To PORTC */ - PORTCFG_VP13MAP_PORTD_gc = (0x03<<4), /* Mapped To PORTD */ - PORTCFG_VP13MAP_PORTE_gc = (0x04<<4), /* Mapped To PORTE */ - PORTCFG_VP13MAP_PORTF_gc = (0x05<<4), /* Mapped To PORTF */ - PORTCFG_VP13MAP_PORTG_gc = (0x06<<4), /* Mapped To PORTG */ - PORTCFG_VP13MAP_PORTH_gc = (0x07<<4), /* Mapped To PORTH */ - PORTCFG_VP13MAP_PORTJ_gc = (0x08<<4), /* Mapped To PORTJ */ - PORTCFG_VP13MAP_PORTK_gc = (0x09<<4), /* Mapped To PORTK */ - PORTCFG_VP13MAP_PORTL_gc = (0x0A<<4), /* Mapped To PORTL */ - PORTCFG_VP13MAP_PORTM_gc = (0x0B<<4), /* Mapped To PORTM */ - PORTCFG_VP13MAP_PORTN_gc = (0x0C<<4), /* Mapped To PORTN */ - PORTCFG_VP13MAP_PORTP_gc = (0x0D<<4), /* Mapped To PORTP */ - PORTCFG_VP13MAP_PORTQ_gc = (0x0E<<4), /* Mapped To PORTQ */ - PORTCFG_VP13MAP_PORTR_gc = (0x0F<<4), /* Mapped To PORTR */ -} PORTCFG_VP13MAP_t; - -/* System Clock Output Port */ -typedef enum PORTCFG_CLKOUT_enum -{ - PORTCFG_CLKOUT_OFF_gc = (0x00<<0), /* System Clock Output Disabled */ - PORTCFG_CLKOUT_PC7_gc = (0x01<<0), /* System Clock Output on Port C pin 7 */ - PORTCFG_CLKOUT_PD7_gc = (0x02<<0), /* System Clock Output on Port D pin 7 */ - PORTCFG_CLKOUT_PE7_gc = (0x03<<0), /* System Clock Output on Port E pin 7 */ -} PORTCFG_CLKOUT_t; - -/* Peripheral Clock Output Select */ -typedef enum PORTCFG_CLKOUTSEL_enum -{ - PORTCFG_CLKOUTSEL_CLK1X_gc = (0x00<<2), /* 1x Peripheral Clock Output to pin */ - PORTCFG_CLKOUTSEL_CLK2X_gc = (0x01<<2), /* 2x Peripheral Clock Output to pin */ - PORTCFG_CLKOUTSEL_CLK4X_gc = (0x02<<2), /* 4x Peripheral Clock Output to pin */ -} PORTCFG_CLKOUTSEL_t; - -/* Event Output Port */ -typedef enum PORTCFG_EVOUT_enum -{ - PORTCFG_EVOUT_OFF_gc = (0x00<<4), /* Event Output Disabled */ - PORTCFG_EVOUT_PC7_gc = (0x01<<4), /* Event Channel 7 Output on Port C pin 7 */ - PORTCFG_EVOUT_PD7_gc = (0x02<<4), /* Event Channel 7 Output on Port D pin 7 */ - PORTCFG_EVOUT_PE7_gc = (0x03<<4), /* Event Channel 7 Output on Port E pin 7 */ -} PORTCFG_EVOUT_t; - -/* Clock and Event Output Port */ -typedef enum PORTCFG_CLKEVPIN_enum -{ - PORTCFG_CLKEVPIN_PIN7_gc = (0x00<<7), /* Clock and Event Ouput on PIN 7 */ - PORTCFG_CLKEVPIN_PIN4_gc = (0x01<<7), /* Clock and Event Ouput on PIN 4 */ -} PORTCFG_CLKEVPIN_t; - -/* EBI Address Output Port */ -typedef enum PORTCFG_EBIADROUT_enum -{ - PORTCFG_EBIADROUT_PF_gc = (0x00<<2), /* EBI port 3 address output on PORTF pins 0 to 7 */ - PORTCFG_EBIADROUT_PE_gc = (0x01<<2), /* EBI port 3 address output on PORTE pins 0 to 7 */ - PORTCFG_EBIADROUT_PFH_gc = (0x02<<2), /* EBI port 3 address output on PORTF pins 4 to 7 */ - PORTCFG_EBIADROUT_PEH_gc = (0x03<<2), /* EBI port 3 address output on PORTE pins 4 to 7 */ -} PORTCFG_EBIADROUT_t; - -/* EBI Chip Select Output Port */ -typedef enum PORTCFG_EBICSOUT_enum -{ - PORTCFG_EBICSOUT_PH_gc = (0x00<<0), /* EBI chip select output to PORTH pin 4 to 7 */ - PORTCFG_EBICSOUT_PL_gc = (0x01<<0), /* EBI chip select output to PORTL pin 4 to 7 */ - PORTCFG_EBICSOUT_PF_gc = (0x02<<0), /* EBI chip select output to PORTF pin 4 to 7 */ - PORTCFG_EBICSOUT_PE_gc = (0x03<<0), /* EBI chip select output to PORTE pin 4 to 7 */ -} PORTCFG_EBICSOUT_t; - -/* Event Output Select */ -typedef enum PORTCFG_EVOUTSEL_enum -{ - PORTCFG_EVOUTSEL_0_gc = (0x00<<0), /* Event Channel 0 output to pin */ - PORTCFG_EVOUTSEL_1_gc = (0x01<<0), /* Event Channel 1 output to pin */ - PORTCFG_EVOUTSEL_2_gc = (0x02<<0), /* Event Channel 2 output to pin */ - PORTCFG_EVOUTSEL_3_gc = (0x03<<0), /* Event Channel 3 output to pin */ - PORTCFG_EVOUTSEL_4_gc = (0x04<<0), /* Event Channel 4 output to pin */ - PORTCFG_EVOUTSEL_5_gc = (0x05<<0), /* Event Channel 5 output to pin */ - PORTCFG_EVOUTSEL_6_gc = (0x06<<0), /* Event Channel 6 output to pin */ - PORTCFG_EVOUTSEL_7_gc = (0x07<<0), /* Event Channel 7 output to pin */ -} PORTCFG_EVOUTSEL_t; - - -/* --------------------------------------------------------------------------- -AES - AES Module --------------------------------------------------------------------------- -*/ - -/* AES Module */ -typedef struct AES_struct -{ - register8_t CTRL; /* AES Control Register */ - register8_t STATUS; /* AES Status Register */ - register8_t STATE; /* AES State Register */ - register8_t KEY; /* AES Key Register */ - register8_t INTCTRL; /* AES Interrupt Control Register */ -} AES_t; - -/* Interrupt level */ -typedef enum AES_INTLVL_enum -{ - AES_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - AES_INTLVL_LO_gc = (0x01<<0), /* Low Level */ - AES_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ - AES_INTLVL_HI_gc = (0x03<<0), /* High Level */ -} AES_INTLVL_t; - - -/* --------------------------------------------------------------------------- -CRC - Cyclic Redundancy Checker --------------------------------------------------------------------------- -*/ - -/* Cyclic Redundancy Checker */ -typedef struct CRC_struct -{ - register8_t CTRL; /* Control Register */ - register8_t STATUS; /* Status Register */ - register8_t reserved_0x02; - register8_t DATAIN; /* Data Input */ - register8_t CHECKSUM0; /* Checksum byte 0 */ - register8_t CHECKSUM1; /* Checksum byte 1 */ - register8_t CHECKSUM2; /* Checksum byte 2 */ - register8_t CHECKSUM3; /* Checksum byte 3 */ -} CRC_t; - -/* Reset */ -typedef enum CRC_RESET_enum -{ - CRC_RESET_NO_gc = (0x00<<6), /* No Reset */ - CRC_RESET_RESET0_gc = (0x02<<6), /* Reset CRC with CHECKSUM to all zeros */ - CRC_RESET_RESET1_gc = (0x03<<6), /* Reset CRC with CHECKSUM to all ones */ -} CRC_RESET_t; - -/* Input Source */ -typedef enum CRC_SOURCE_enum -{ - CRC_SOURCE_DISABLE_gc = (0x00<<0), /* Disabled */ - CRC_SOURCE_IO_gc = (0x01<<0), /* I/O Interface */ - CRC_SOURCE_FLASH_gc = (0x02<<0), /* Flash */ - CRC_SOURCE_DMAC0_gc = (0x04<<0), /* DMAC Channel 0 */ - CRC_SOURCE_DMAC1_gc = (0x05<<0), /* DMAC Channel 1 */ - CRC_SOURCE_DMAC2_gc = (0x06<<0), /* DMAC Channel 2 */ - CRC_SOURCE_DMAC3_gc = (0x07<<0), /* DMAC Channel 3 */ -} CRC_SOURCE_t; - - -/* --------------------------------------------------------------------------- -DMA - DMA Controller --------------------------------------------------------------------------- -*/ - -/* DMA Channel */ -typedef struct DMA_CH_struct -{ - register8_t CTRLA; /* Channel Control */ - register8_t CTRLB; /* Channel Control */ - register8_t ADDRCTRL; /* Address Control */ - register8_t TRIGSRC; /* Channel Trigger Source */ - _WORDREGISTER(TRFCNT); /* Channel Block Transfer Count */ - register8_t REPCNT; /* Channel Repeat Count */ - register8_t reserved_0x07; - register8_t SRCADDR0; /* Channel Source Address 0 */ - register8_t SRCADDR1; /* Channel Source Address 1 */ - register8_t reserved_0x0A; - register8_t reserved_0x0B; - register8_t DESTADDR0; /* Channel Destination Address 0 */ - register8_t DESTADDR1; /* Channel Destination Address 1 */ - register8_t reserved_0x0E; - register8_t reserved_0x0F; -} DMA_CH_t; - - -/* DMA Controller */ -typedef struct DMA_struct -{ - register8_t CTRL; /* Control */ - register8_t reserved_0x01; - register8_t reserved_0x02; - register8_t INTFLAGS; /* Transfer Interrupt Status */ - register8_t STATUS; /* Status */ - register8_t reserved_0x05; - _WORDREGISTER(TEMP); /* Temporary Register For 16-bit Access */ - register8_t reserved_0x08; - register8_t reserved_0x09; - register8_t reserved_0x0A; - register8_t reserved_0x0B; - register8_t reserved_0x0C; - register8_t reserved_0x0D; - register8_t reserved_0x0E; - register8_t reserved_0x0F; - DMA_CH_t CH0; /* DMA Channel 0 */ - DMA_CH_t CH1; /* DMA Channel 1 */ -} DMA_t; - -/* Burst mode */ -typedef enum DMA_CH_BURSTLEN_enum -{ - DMA_CH_BURSTLEN_1BYTE_gc = (0x00<<0), /* 1-byte burst mode */ - DMA_CH_BURSTLEN_2BYTE_gc = (0x01<<0), /* 2-byte burst mode */ - DMA_CH_BURSTLEN_4BYTE_gc = (0x02<<0), /* 4-byte burst mode */ - DMA_CH_BURSTLEN_8BYTE_gc = (0x03<<0), /* 8-byte burst mode */ -} DMA_CH_BURSTLEN_t; - -/* Source address reload mode */ -typedef enum DMA_CH_SRCRELOAD_enum -{ - DMA_CH_SRCRELOAD_NONE_gc = (0x00<<6), /* No reload */ - DMA_CH_SRCRELOAD_BLOCK_gc = (0x01<<6), /* Reload at end of block */ - DMA_CH_SRCRELOAD_BURST_gc = (0x02<<6), /* Reload at end of burst */ - DMA_CH_SRCRELOAD_TRANSACTION_gc = (0x03<<6), /* Reload at end of transaction */ -} DMA_CH_SRCRELOAD_t; - -/* Source addressing mode */ -typedef enum DMA_CH_SRCDIR_enum -{ - DMA_CH_SRCDIR_FIXED_gc = (0x00<<4), /* Fixed */ - DMA_CH_SRCDIR_INC_gc = (0x01<<4), /* Increment */ - DMA_CH_SRCDIR_DEC_gc = (0x02<<4), /* Decrement */ -} DMA_CH_SRCDIR_t; - -/* Destination adress reload mode */ -typedef enum DMA_CH_DESTRELOAD_enum -{ - DMA_CH_DESTRELOAD_NONE_gc = (0x00<<2), /* No reload */ - DMA_CH_DESTRELOAD_BLOCK_gc = (0x01<<2), /* Reload at end of block */ - DMA_CH_DESTRELOAD_BURST_gc = (0x02<<2), /* Reload at end of burst */ - DMA_CH_DESTRELOAD_TRANSACTION_gc = (0x03<<2), /* Reload at end of transaction */ -} DMA_CH_DESTRELOAD_t; - -/* Destination adressing mode */ -typedef enum DMA_CH_DESTDIR_enum -{ - DMA_CH_DESTDIR_FIXED_gc = (0x00<<0), /* Fixed */ - DMA_CH_DESTDIR_INC_gc = (0x01<<0), /* Increment */ - DMA_CH_DESTDIR_DEC_gc = (0x02<<0), /* Decrement */ -} DMA_CH_DESTDIR_t; - -/* Transfer trigger source */ -typedef enum DMA_CH_TRIGSRC_enum -{ - DMA_CH_TRIGSRC_OFF_gc = (0x00<<0), /* Off software triggers only */ - DMA_CH_TRIGSRC_EVSYS_CH0_gc = (0x01<<0), /* Event System Channel 0 */ - DMA_CH_TRIGSRC_EVSYS_CH1_gc = (0x02<<0), /* Event System Channel 1 */ - DMA_CH_TRIGSRC_EVSYS_CH2_gc = (0x03<<0), /* Event System Channel 2 */ - DMA_CH_TRIGSRC_ADCA_CH0_gc = (0x10<<0), /* ADCA Channel 0 */ - DMA_CH_TRIGSRC_ADCB_CH0_gc = (0x20<<0), /* ADCB Channel 0 */ - DMA_CH_TRIGSRC_TCC0_OVF_gc = (0x40<<0), /* Timer/Counter C0 Overflow */ - DMA_CH_TRIGSRC_TCC0_ERR_gc = (0x41<<0), /* Timer/Counter C0 Error */ - DMA_CH_TRIGSRC_TCC0_CCA_gc = (0x42<<0), /* Timer/Counter C0 Compare or Capture A */ - DMA_CH_TRIGSRC_TCC0_CCB_gc = (0x43<<0), /* Timer/Counter C0 Compare or Capture B */ - DMA_CH_TRIGSRC_TCC0_CCC_gc = (0x44<<0), /* Timer/Counter C0 Compare or Capture C */ - DMA_CH_TRIGSRC_TCC0_CCD_gc = (0x45<<0), /* Timer/Counter C0 Compare or Capture D */ - DMA_CH_TRIGSRC_TCC1_OVF_gc = (0x46<<0), /* Timer/Counter C1 Overflow */ - DMA_CH_TRIGSRC_TCC1_ERR_gc = (0x47<<0), /* Timer/Counter C1 Error */ - DMA_CH_TRIGSRC_TCC1_CCA_gc = (0x48<<0), /* Timer/Counter C1 Compare or Capture A */ - DMA_CH_TRIGSRC_TCC1_CCB_gc = (0x49<<0), /* Timer/Counter C1 Compare or Capture B */ - DMA_CH_TRIGSRC_SPIC_gc = (0x4A<<0), /* SPI C Transfer Complete */ - DMA_CH_TRIGSRC_USARTC0_RXC_gc = (0x4B<<0), /* USART C0 Receive Complete */ - DMA_CH_TRIGSRC_USARTC0_DRE_gc = (0x4C<<0), /* USART C0 Data Register Empty */ - DMA_CH_TRIGSRC_TCD0_OVF_gc = (0x60<<0), /* Timer/Counter D0 Overflow */ - DMA_CH_TRIGSRC_TCD0_ERR_gc = (0x61<<0), /* Timer/Counter D0 Error */ - DMA_CH_TRIGSRC_TCD0_CCA_gc = (0x62<<0), /* Timer/Counter D0 Compare or Capture A */ - DMA_CH_TRIGSRC_TCD0_CCB_gc = (0x63<<0), /* Timer/Counter D0 Compare or Capture B */ - DMA_CH_TRIGSRC_TCD0_CCC_gc = (0x64<<0), /* Timer/Counter D0 Compare or Capture C */ - DMA_CH_TRIGSRC_TCD0_CCD_gc = (0x65<<0), /* Timer/Counter D0 Compare or Capture D */ - DMA_CH_TRIGSRC_SPID_gc = (0x6A<<0), /* SPI D Transfer Complete */ - DMA_CH_TRIGSRC_USARTD0_RXC_gc = (0x6B<<0), /* USART D0 Receive Complete */ - DMA_CH_TRIGSRC_USARTD0_DRE_gc = (0x6C<<0), /* USART D0 Data Register Empty */ - DMA_CH_TRIGSRC_TCE0_OVF_gc = (0x80<<0), /* Timer/Counter E0 Overflow */ - DMA_CH_TRIGSRC_TCE0_ERR_gc = (0x81<<0), /* Timer/Counter E0 Error */ - DMA_CH_TRIGSRC_TCE0_CCA_gc = (0x82<<0), /* Timer/Counter E0 Compare or Capture A */ - DMA_CH_TRIGSRC_TCE0_CCB_gc = (0x83<<0), /* Timer/Counter E0 Compare or Capture B */ - DMA_CH_TRIGSRC_TCE0_CCC_gc = (0x84<<0), /* Timer/Counter E0 Compare or Capture C */ - DMA_CH_TRIGSRC_TCE0_CCD_gc = (0x85<<0), /* Timer/Counter E0 Compare or Capture D */ - DMA_CH_TRIGSRC_USARTE0_RXC_gc = (0x8B<<0), /* USART E0 Receive Complete */ - DMA_CH_TRIGSRC_USARTE0_DRE_gc = (0x8C<<0), /* USART E0 Data Register Empty */ - DMA_CH_TRIGSRC_TCF0_OVF_gc = (0xA0<<0), /* Timer/Counter F0 Overflow */ - DMA_CH_TRIGSRC_TCF0_ERR_gc = (0xA1<<0), /* Timer/Counter F0 Error */ - DMA_CH_TRIGSRC_TCF0_CCA_gc = (0xA2<<0), /* Timer/Counter F0 Compare or Capture A */ - DMA_CH_TRIGSRC_TCF0_CCB_gc = (0xA3<<0), /* Timer/Counter F0 Compare or Capture B */ - DMA_CH_TRIGSRC_TCF0_CCC_gc = (0xA4<<0), /* Timer/Counter F0 Compare or Capture C */ - DMA_CH_TRIGSRC_TCF0_CCD_gc = (0xA5<<0), /* Timer/Counter F0 Compare or Capture D */ -} DMA_CH_TRIGSRC_t; - -/* Double buffering mode */ -typedef enum DMA_DBUFMODE_enum -{ - DMA_DBUFMODE_DISABLED_gc = (0x00<<2), /* Double buffering disabled */ - DMA_DBUFMODE_CH01_gc = (0x01<<2), /* Double buffering enabled on channel 0/1 */ -} DMA_DBUFMODE_t; - -/* Priority mode */ -typedef enum DMA_PRIMODE_enum -{ - DMA_PRIMODE_RR01_gc = (0x00<<0), /* Round Robin */ - DMA_PRIMODE_CH01_gc = (0x01<<0), /* Channel 0 > channel 1 */ -} DMA_PRIMODE_t; - -/* Interrupt level */ -typedef enum DMA_CH_ERRINTLVL_enum -{ - DMA_CH_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ - DMA_CH_ERRINTLVL_LO_gc = (0x01<<2), /* Low level */ - DMA_CH_ERRINTLVL_MED_gc = (0x02<<2), /* Medium level */ - DMA_CH_ERRINTLVL_HI_gc = (0x03<<2), /* High level */ -} DMA_CH_ERRINTLVL_t; - -/* Interrupt level */ -typedef enum DMA_CH_TRNINTLVL_enum -{ - DMA_CH_TRNINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ - DMA_CH_TRNINTLVL_LO_gc = (0x01<<0), /* Low level */ - DMA_CH_TRNINTLVL_MED_gc = (0x02<<0), /* Medium level */ - DMA_CH_TRNINTLVL_HI_gc = (0x03<<0), /* High level */ -} DMA_CH_TRNINTLVL_t; - - -/* --------------------------------------------------------------------------- -EVSYS - Event System --------------------------------------------------------------------------- -*/ - -/* Event System */ -typedef struct EVSYS_struct -{ - register8_t CH0MUX; /* Event Channel 0 Multiplexer */ - register8_t CH1MUX; /* Event Channel 1 Multiplexer */ - register8_t CH2MUX; /* Event Channel 2 Multiplexer */ - register8_t CH3MUX; /* Event Channel 3 Multiplexer */ - register8_t reserved_0x04; - register8_t reserved_0x05; - register8_t reserved_0x06; - register8_t reserved_0x07; - register8_t CH0CTRL; /* Channel 0 Control Register */ - register8_t CH1CTRL; /* Channel 1 Control Register */ - register8_t CH2CTRL; /* Channel 2 Control Register */ - register8_t CH3CTRL; /* Channel 3 Control Register */ - register8_t reserved_0x0C; - register8_t reserved_0x0D; - register8_t reserved_0x0E; - register8_t reserved_0x0F; - register8_t STROBE; /* Event Strobe */ - register8_t DATA; /* Event Data */ -} EVSYS_t; - -/* Quadrature Decoder Index Recognition Mode */ -typedef enum EVSYS_QDIRM_enum -{ - EVSYS_QDIRM_00_gc = (0x00<<5), /* QDPH0 = 0, QDPH90 = 0 */ - EVSYS_QDIRM_01_gc = (0x01<<5), /* QDPH0 = 0, QDPH90 = 1 */ - EVSYS_QDIRM_10_gc = (0x02<<5), /* QDPH0 = 1, QDPH90 = 0 */ - EVSYS_QDIRM_11_gc = (0x03<<5), /* QDPH0 = 1, QDPH90 = 1 */ -} EVSYS_QDIRM_t; - -/* Digital filter coefficient */ -typedef enum EVSYS_DIGFILT_enum -{ - EVSYS_DIGFILT_1SAMPLE_gc = (0x00<<0), /* 1 SAMPLE */ - EVSYS_DIGFILT_2SAMPLES_gc = (0x01<<0), /* 2 SAMPLES */ - EVSYS_DIGFILT_3SAMPLES_gc = (0x02<<0), /* 3 SAMPLES */ - EVSYS_DIGFILT_4SAMPLES_gc = (0x03<<0), /* 4 SAMPLES */ - EVSYS_DIGFILT_5SAMPLES_gc = (0x04<<0), /* 5 SAMPLES */ - EVSYS_DIGFILT_6SAMPLES_gc = (0x05<<0), /* 6 SAMPLES */ - EVSYS_DIGFILT_7SAMPLES_gc = (0x06<<0), /* 7 SAMPLES */ - EVSYS_DIGFILT_8SAMPLES_gc = (0x07<<0), /* 8 SAMPLES */ -} EVSYS_DIGFILT_t; - -/* Event Channel multiplexer input selection */ -typedef enum EVSYS_CHMUX_enum -{ - EVSYS_CHMUX_OFF_gc = (0x00<<0), /* Off */ - EVSYS_CHMUX_RTC_OVF_gc = (0x08<<0), /* RTC Overflow */ - EVSYS_CHMUX_RTC_CMP_gc = (0x09<<0), /* RTC Compare Match */ - EVSYS_CHMUX_USB_gc = (0x0A<<0), /* USB Setup, SOF, CRC error and UNF/OVF */ - EVSYS_CHMUX_ACA_CH0_gc = (0x10<<0), /* Analog Comparator A Channel 0 */ - EVSYS_CHMUX_ACA_CH1_gc = (0x11<<0), /* Analog Comparator A Channel 1 */ - EVSYS_CHMUX_ACA_WIN_gc = (0x12<<0), /* Analog Comparator A Window */ - EVSYS_CHMUX_ADCA_CH0_gc = (0x20<<0), /* ADC A Channel */ - EVSYS_CHMUX_PORTA_PIN0_gc = (0x50<<0), /* Port A, Pin0 */ - EVSYS_CHMUX_PORTA_PIN1_gc = (0x51<<0), /* Port A, Pin1 */ - EVSYS_CHMUX_PORTA_PIN2_gc = (0x52<<0), /* Port A, Pin2 */ - EVSYS_CHMUX_PORTA_PIN3_gc = (0x53<<0), /* Port A, Pin3 */ - EVSYS_CHMUX_PORTA_PIN4_gc = (0x54<<0), /* Port A, Pin4 */ - EVSYS_CHMUX_PORTA_PIN5_gc = (0x55<<0), /* Port A, Pin5 */ - EVSYS_CHMUX_PORTA_PIN6_gc = (0x56<<0), /* Port A, Pin6 */ - EVSYS_CHMUX_PORTA_PIN7_gc = (0x57<<0), /* Port A, Pin7 */ - EVSYS_CHMUX_PORTB_PIN0_gc = (0x58<<0), /* Port B, Pin0 */ - EVSYS_CHMUX_PORTB_PIN1_gc = (0x59<<0), /* Port B, Pin1 */ - EVSYS_CHMUX_PORTB_PIN2_gc = (0x5A<<0), /* Port B, Pin2 */ - EVSYS_CHMUX_PORTB_PIN3_gc = (0x5B<<0), /* Port B, Pin3 */ - EVSYS_CHMUX_PORTB_PIN4_gc = (0x5C<<0), /* Port B, Pin4 */ - EVSYS_CHMUX_PORTB_PIN5_gc = (0x5D<<0), /* Port B, Pin5 */ - EVSYS_CHMUX_PORTB_PIN6_gc = (0x5E<<0), /* Port B, Pin6 */ - EVSYS_CHMUX_PORTB_PIN7_gc = (0x5F<<0), /* Port B, Pin7 */ - EVSYS_CHMUX_PORTC_PIN0_gc = (0x60<<0), /* Port C, Pin0 */ - EVSYS_CHMUX_PORTC_PIN1_gc = (0x61<<0), /* Port C, Pin1 */ - EVSYS_CHMUX_PORTC_PIN2_gc = (0x62<<0), /* Port C, Pin2 */ - EVSYS_CHMUX_PORTC_PIN3_gc = (0x63<<0), /* Port C, Pin3 */ - EVSYS_CHMUX_PORTC_PIN4_gc = (0x64<<0), /* Port C, Pin4 */ - EVSYS_CHMUX_PORTC_PIN5_gc = (0x65<<0), /* Port C, Pin5 */ - EVSYS_CHMUX_PORTC_PIN6_gc = (0x66<<0), /* Port C, Pin6 */ - EVSYS_CHMUX_PORTC_PIN7_gc = (0x67<<0), /* Port C, Pin7 */ - EVSYS_CHMUX_PORTD_PIN0_gc = (0x68<<0), /* Port D, Pin0 */ - EVSYS_CHMUX_PORTD_PIN1_gc = (0x69<<0), /* Port D, Pin1 */ - EVSYS_CHMUX_PORTD_PIN2_gc = (0x6A<<0), /* Port D, Pin2 */ - EVSYS_CHMUX_PORTD_PIN3_gc = (0x6B<<0), /* Port D, Pin3 */ - EVSYS_CHMUX_PORTD_PIN4_gc = (0x6C<<0), /* Port D, Pin4 */ - EVSYS_CHMUX_PORTD_PIN5_gc = (0x6D<<0), /* Port D, Pin5 */ - EVSYS_CHMUX_PORTD_PIN6_gc = (0x6E<<0), /* Port D, Pin6 */ - EVSYS_CHMUX_PORTD_PIN7_gc = (0x6F<<0), /* Port D, Pin7 */ - EVSYS_CHMUX_PORTE_PIN0_gc = (0x70<<0), /* Port E, Pin0 */ - EVSYS_CHMUX_PORTE_PIN1_gc = (0x71<<0), /* Port E, Pin1 */ - EVSYS_CHMUX_PORTE_PIN2_gc = (0x72<<0), /* Port E, Pin2 */ - EVSYS_CHMUX_PORTE_PIN3_gc = (0x73<<0), /* Port E, Pin3 */ - EVSYS_CHMUX_PORTE_PIN4_gc = (0x74<<0), /* Port E, Pin4 */ - EVSYS_CHMUX_PORTE_PIN5_gc = (0x75<<0), /* Port E, Pin5 */ - EVSYS_CHMUX_PORTE_PIN6_gc = (0x76<<0), /* Port E, Pin6 */ - EVSYS_CHMUX_PORTE_PIN7_gc = (0x77<<0), /* Port E, Pin7 */ - EVSYS_CHMUX_PORTF_PIN0_gc = (0x78<<0), /* Port F, Pin0 */ - EVSYS_CHMUX_PORTF_PIN1_gc = (0x79<<0), /* Port F, Pin1 */ - EVSYS_CHMUX_PORTF_PIN2_gc = (0x7A<<0), /* Port F, Pin2 */ - EVSYS_CHMUX_PORTF_PIN3_gc = (0x7B<<0), /* Port F, Pin3 */ - EVSYS_CHMUX_PORTF_PIN4_gc = (0x7C<<0), /* Port F, Pin4 */ - EVSYS_CHMUX_PORTF_PIN5_gc = (0x7D<<0), /* Port F, Pin5 */ - EVSYS_CHMUX_PORTF_PIN6_gc = (0x7E<<0), /* Port F, Pin6 */ - EVSYS_CHMUX_PORTF_PIN7_gc = (0x7F<<0), /* Port F, Pin7 */ - EVSYS_CHMUX_PRESCALER_1_gc = (0x80<<0), /* Prescaler, divide by 1 */ - EVSYS_CHMUX_PRESCALER_2_gc = (0x81<<0), /* Prescaler, divide by 2 */ - EVSYS_CHMUX_PRESCALER_4_gc = (0x82<<0), /* Prescaler, divide by 4 */ - EVSYS_CHMUX_PRESCALER_8_gc = (0x83<<0), /* Prescaler, divide by 8 */ - EVSYS_CHMUX_PRESCALER_16_gc = (0x84<<0), /* Prescaler, divide by 16 */ - EVSYS_CHMUX_PRESCALER_32_gc = (0x85<<0), /* Prescaler, divide by 32 */ - EVSYS_CHMUX_PRESCALER_64_gc = (0x86<<0), /* Prescaler, divide by 64 */ - EVSYS_CHMUX_PRESCALER_128_gc = (0x87<<0), /* Prescaler, divide by 128 */ - EVSYS_CHMUX_PRESCALER_256_gc = (0x88<<0), /* Prescaler, divide by 256 */ - EVSYS_CHMUX_PRESCALER_512_gc = (0x89<<0), /* Prescaler, divide by 512 */ - EVSYS_CHMUX_PRESCALER_1024_gc = (0x8A<<0), /* Prescaler, divide by 1024 */ - EVSYS_CHMUX_PRESCALER_2048_gc = (0x8B<<0), /* Prescaler, divide by 2048 */ - EVSYS_CHMUX_PRESCALER_4096_gc = (0x8C<<0), /* Prescaler, divide by 4096 */ - EVSYS_CHMUX_PRESCALER_8192_gc = (0x8D<<0), /* Prescaler, divide by 8192 */ - EVSYS_CHMUX_PRESCALER_16384_gc = (0x8E<<0), /* Prescaler, divide by 16384 */ - EVSYS_CHMUX_PRESCALER_32768_gc = (0x8F<<0), /* Prescaler, divide by 32768 */ - EVSYS_CHMUX_TCC0_OVF_gc = (0xC0<<0), /* Timer/Counter C0 Overflow */ - EVSYS_CHMUX_TCC0_ERR_gc = (0xC1<<0), /* Timer/Counter C0 Error */ - EVSYS_CHMUX_TCC0_CCA_gc = (0xC4<<0), /* Timer/Counter C0 Compare or Capture A */ - EVSYS_CHMUX_TCC0_CCB_gc = (0xC5<<0), /* Timer/Counter C0 Compare or Capture B */ - EVSYS_CHMUX_TCC0_CCC_gc = (0xC6<<0), /* Timer/Counter C0 Compare or Capture C */ - EVSYS_CHMUX_TCC0_CCD_gc = (0xC7<<0), /* Timer/Counter C0 Compare or Capture D */ - EVSYS_CHMUX_TCC1_OVF_gc = (0xC8<<0), /* Timer/Counter C1 Overflow */ - EVSYS_CHMUX_TCC1_ERR_gc = (0xC9<<0), /* Timer/Counter C1 Error */ - EVSYS_CHMUX_TCC1_CCA_gc = (0xCC<<0), /* Timer/Counter C1 Compare or Capture A */ - EVSYS_CHMUX_TCC1_CCB_gc = (0xCD<<0), /* Timer/Counter C1 Compare or Capture B */ - EVSYS_CHMUX_TCD0_OVF_gc = (0xD0<<0), /* Timer/Counter D0 Overflow */ - EVSYS_CHMUX_TCD0_ERR_gc = (0xD1<<0), /* Timer/Counter D0 Error */ - EVSYS_CHMUX_TCD0_CCA_gc = (0xD4<<0), /* Timer/Counter D0 Compare or Capture A */ - EVSYS_CHMUX_TCD0_CCB_gc = (0xD5<<0), /* Timer/Counter D0 Compare or Capture B */ - EVSYS_CHMUX_TCD0_CCC_gc = (0xD6<<0), /* Timer/Counter D0 Compare or Capture C */ - EVSYS_CHMUX_TCD0_CCD_gc = (0xD7<<0), /* Timer/Counter D0 Compare or Capture D */ - EVSYS_CHMUX_TCE0_OVF_gc = (0xE0<<0), /* Timer/Counter E0 Overflow */ - EVSYS_CHMUX_TCE0_ERR_gc = (0xE1<<0), /* Timer/Counter E0 Error */ - EVSYS_CHMUX_TCE0_CCA_gc = (0xE4<<0), /* Timer/Counter E0 Compare or Capture A */ - EVSYS_CHMUX_TCE0_CCB_gc = (0xE5<<0), /* Timer/Counter E0 Compare or Capture B */ - EVSYS_CHMUX_TCE0_CCC_gc = (0xE6<<0), /* Timer/Counter E0 Compare or Capture C */ - EVSYS_CHMUX_TCE0_CCD_gc = (0xE7<<0), /* Timer/Counter E0 Compare or Capture D */ - EVSYS_CHMUX_TCF0_OVF_gc = (0xF0<<0), /* Timer/Counter F0 Overflow */ - EVSYS_CHMUX_TCF0_ERR_gc = (0xF1<<0), /* Timer/Counter F0 Error */ - EVSYS_CHMUX_TCF0_CCA_gc = (0xF4<<0), /* Timer/Counter F0 Compare or Capture A */ - EVSYS_CHMUX_TCF0_CCB_gc = (0xF5<<0), /* Timer/Counter F0 Compare or Capture B */ - EVSYS_CHMUX_TCF0_CCC_gc = (0xF6<<0), /* Timer/Counter F0 Compare or Capture C */ - EVSYS_CHMUX_TCF0_CCD_gc = (0xF7<<0), /* Timer/Counter F0 Compare or Capture D */ -} EVSYS_CHMUX_t; - - -/* --------------------------------------------------------------------------- -NVM - Non Volatile Memory Controller --------------------------------------------------------------------------- -*/ - -/* Non-volatile Memory Controller */ -typedef struct NVM_struct -{ - register8_t ADDR0; /* Address Register 0 */ - register8_t ADDR1; /* Address Register 1 */ - register8_t ADDR2; /* Address Register 2 */ - register8_t reserved_0x03; - register8_t DATA0; /* Data Register 0 */ - register8_t DATA1; /* Data Register 1 */ - register8_t DATA2; /* Data Register 2 */ - register8_t reserved_0x07; - register8_t reserved_0x08; - register8_t reserved_0x09; - register8_t CMD; /* Command */ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t INTCTRL; /* Interrupt Control */ - register8_t reserved_0x0E; - register8_t STATUS; /* Status */ - register8_t LOCK_BITS; /* Lock Bits (Changed from LOCKBITS to avoid avr-libc collision) */ -} NVM_t; - -/* NVM Command */ -typedef enum NVM_CMD_enum -{ - NVM_CMD_NO_OPERATION_gc = (0x00<<0), /* Noop/Ordinary LPM */ - NVM_CMD_READ_USER_SIG_ROW_gc = (0x01<<0), /* Read user signature row */ - NVM_CMD_READ_CALIB_ROW_gc = (0x02<<0), /* Read calibration row */ - NVM_CMD_READ_EEPROM_gc = (0x06<<0), /* Read EEPROM */ - NVM_CMD_READ_FUSES_gc = (0x07<<0), /* Read fuse byte */ - NVM_CMD_WRITE_LOCK_BITS_gc = (0x08<<0), /* Write lock bits */ - NVM_CMD_ERASE_USER_SIG_ROW_gc = (0x18<<0), /* Erase user signature row */ - NVM_CMD_WRITE_USER_SIG_ROW_gc = (0x1A<<0), /* Write user signature row */ - NVM_CMD_ERASE_APP_gc = (0x20<<0), /* Erase Application Section */ - NVM_CMD_ERASE_APP_PAGE_gc = (0x22<<0), /* Erase Application Section page */ - NVM_CMD_LOAD_FLASH_BUFFER_gc = (0x23<<0), /* Load Flash page buffer */ - NVM_CMD_WRITE_APP_PAGE_gc = (0x24<<0), /* Write Application Section page */ - NVM_CMD_ERASE_WRITE_APP_PAGE_gc = (0x25<<0), /* Erase-and-write Application Section page */ - NVM_CMD_ERASE_FLASH_BUFFER_gc = (0x26<<0), /* Erase/flush Flash page buffer */ - NVM_CMD_ERASE_BOOT_PAGE_gc = (0x2A<<0), /* Erase Boot Section page */ - NVM_CMD_ERASE_FLASH_PAGE_gc = (0x2B<<0), /* Erase Flash Page */ - NVM_CMD_WRITE_BOOT_PAGE_gc = (0x2C<<0), /* Write Boot Section page */ - NVM_CMD_ERASE_WRITE_BOOT_PAGE_gc = (0x2D<<0), /* Erase-and-write Boot Section page */ - NVM_CMD_WRITE_FLASH_PAGE_gc = (0x2E<<0), /* Write Flash Page */ - NVM_CMD_ERASE_WRITE_FLASH_PAGE_gc = (0x2F<<0), /* Erase-and-write Flash Page */ - NVM_CMD_ERASE_EEPROM_gc = (0x30<<0), /* Erase EEPROM */ - NVM_CMD_ERASE_EEPROM_PAGE_gc = (0x32<<0), /* Erase EEPROM page */ - NVM_CMD_LOAD_EEPROM_BUFFER_gc = (0x33<<0), /* Load EEPROM page buffer */ - NVM_CMD_WRITE_EEPROM_PAGE_gc = (0x34<<0), /* Write EEPROM page */ - NVM_CMD_ERASE_WRITE_EEPROM_PAGE_gc = (0x35<<0), /* Erase-and-write EEPROM page */ - NVM_CMD_ERASE_EEPROM_BUFFER_gc = (0x36<<0), /* Erase/flush EEPROM page buffer */ - NVM_CMD_APP_CRC_gc = (0x38<<0), /* Application section CRC */ - NVM_CMD_BOOT_CRC_gc = (0x39<<0), /* Boot Section CRC */ - NVM_CMD_FLASH_RANGE_CRC_gc = (0x3A<<0), /* Flash Range CRC */ - NVM_CMD_CHIP_ERASE_gc = (0x40<<0), /* Erase Chip */ - NVM_CMD_READ_NVM_gc = (0x43<<0), /* Read NVM */ - NVM_CMD_WRITE_FUSE_gc = (0x4C<<0), /* Write Fuse byte */ - NVM_CMD_ERASE_BOOT_gc = (0x68<<0), /* Erase Boot Section */ - NVM_CMD_FLASH_CRC_gc = (0x78<<0), /* Flash CRC */ -} NVM_CMD_t; - -/* SPM ready interrupt level */ -typedef enum NVM_SPMLVL_enum -{ - NVM_SPMLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ - NVM_SPMLVL_LO_gc = (0x01<<2), /* Low level */ - NVM_SPMLVL_MED_gc = (0x02<<2), /* Medium level */ - NVM_SPMLVL_HI_gc = (0x03<<2), /* High level */ -} NVM_SPMLVL_t; - -/* EEPROM ready interrupt level */ -typedef enum NVM_EELVL_enum -{ - NVM_EELVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ - NVM_EELVL_LO_gc = (0x01<<0), /* Low level */ - NVM_EELVL_MED_gc = (0x02<<0), /* Medium level */ - NVM_EELVL_HI_gc = (0x03<<0), /* High level */ -} NVM_EELVL_t; - -/* Boot lock bits - boot setcion */ -typedef enum NVM_BLBB_enum -{ - NVM_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ - NVM_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ - NVM_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ - NVM_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ -} NVM_BLBB_t; - -/* Boot lock bits - application section */ -typedef enum NVM_BLBA_enum -{ - NVM_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ - NVM_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ - NVM_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ - NVM_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ -} NVM_BLBA_t; - -/* Boot lock bits - application table section */ -typedef enum NVM_BLBAT_enum -{ - NVM_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ - NVM_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ - NVM_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ - NVM_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ -} NVM_BLBAT_t; - -/* Lock bits */ -typedef enum NVM_LB_enum -{ - NVM_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ - NVM_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ - NVM_LB_NOLOCK_gc = (0x03<<0), /* No locks */ -} NVM_LB_t; - - -/* --------------------------------------------------------------------------- -ADC - Analog/Digital Converter --------------------------------------------------------------------------- -*/ - -/* ADC Channel */ -typedef struct ADC_CH_struct -{ - register8_t CTRL; /* Control Register */ - register8_t MUXCTRL; /* MUX Control */ - register8_t INTCTRL; /* Channel Interrupt Control Register */ - register8_t INTFLAGS; /* Interrupt Flags */ - _WORDREGISTER(RES); /* Channel Result */ - register8_t SCAN; /* Input Channel Scan */ - register8_t reserved_0x07; -} ADC_CH_t; - - -/* Analog-to-Digital Converter */ -typedef struct ADC_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t REFCTRL; /* Reference Control */ - register8_t EVCTRL; /* Event Control */ - register8_t PRESCALER; /* Clock Prescaler */ - register8_t reserved_0x05; - register8_t INTFLAGS; /* Interrupt Flags */ - register8_t TEMP; /* Temporary Register */ - register8_t SAMPCTRL; /* ADC Sampling Time Control Register */ - register8_t reserved_0x09; - register8_t reserved_0x0A; - register8_t reserved_0x0B; - _WORDREGISTER(CAL); /* Calibration Value */ - register8_t reserved_0x0E; - register8_t reserved_0x0F; - _WORDREGISTER(CH0RES); /* Channel 0 Result */ - register8_t reserved_0x12; - register8_t reserved_0x13; - register8_t reserved_0x14; - register8_t reserved_0x15; - register8_t reserved_0x16; - register8_t reserved_0x17; - _WORDREGISTER(CMP); /* Compare Value */ - register8_t reserved_0x1A; - register8_t reserved_0x1B; - register8_t reserved_0x1C; - register8_t reserved_0x1D; - register8_t reserved_0x1E; - register8_t reserved_0x1F; - ADC_CH_t CH0; /* ADC Channel 0 */ -} ADC_t; - -/* Current Limitation */ -typedef enum ADC_CURRLIMIT_enum -{ - ADC_CURRLIMIT_NO_gc = (0x00<<5), /* No current limit, 300ksps max sampling rate */ - ADC_CURRLIMIT_LOW_gc = (0x01<<5), /* Low current limit, 250ksps max sampling rate */ - ADC_CURRLIMIT_MED_gc = (0x02<<5), /* Medium current limit, 150ksps max sampling rate */ - ADC_CURRLIMIT_HIGH_gc = (0x03<<5), /* High current limit, 50ksps max sampling rate */ -} ADC_CURRLIMIT_t; - -/* Positive input multiplexer selection */ -typedef enum ADC_CH_MUXPOS_enum -{ - ADC_CH_MUXPOS_PIN0_gc = (0x00<<3), /* Input pin 0 */ - ADC_CH_MUXPOS_PIN1_gc = (0x01<<3), /* Input pin 1 */ - ADC_CH_MUXPOS_PIN2_gc = (0x02<<3), /* Input pin 2 */ - ADC_CH_MUXPOS_PIN3_gc = (0x03<<3), /* Input pin 3 */ - ADC_CH_MUXPOS_PIN4_gc = (0x04<<3), /* Input pin 4 */ - ADC_CH_MUXPOS_PIN5_gc = (0x05<<3), /* Input pin 5 */ - ADC_CH_MUXPOS_PIN6_gc = (0x06<<3), /* Input pin 6 */ - ADC_CH_MUXPOS_PIN7_gc = (0x07<<3), /* Input pin 7 */ - ADC_CH_MUXPOS_PIN8_gc = (0x08<<3), /* Input pin 8 */ - ADC_CH_MUXPOS_PIN9_gc = (0x09<<3), /* Input pin 9 */ - ADC_CH_MUXPOS_PIN10_gc = (0x0A<<3), /* Input pin 10 */ - ADC_CH_MUXPOS_PIN11_gc = (0x0B<<3), /* Input pin 11 */ - ADC_CH_MUXPOS_PIN12_gc = (0x0C<<3), /* Input pin 12 */ - ADC_CH_MUXPOS_PIN13_gc = (0x0D<<3), /* Input pin 13 */ - ADC_CH_MUXPOS_PIN14_gc = (0x0E<<3), /* Input pin 14 */ - ADC_CH_MUXPOS_PIN15_gc = (0x0F<<3), /* Input pin 15 */ -} ADC_CH_MUXPOS_t; - -/* Internal input multiplexer selections */ -typedef enum ADC_CH_MUXINT_enum -{ - ADC_CH_MUXINT_TEMP_gc = (0x00<<3), /* Temperature Reference */ - ADC_CH_MUXINT_BANDGAP_gc = (0x01<<3), /* Bandgap Reference */ - ADC_CH_MUXINT_SCALEDVCC_gc = (0x02<<3), /* 1/10 scaled VCC */ -} ADC_CH_MUXINT_t; - -/* Negative input multiplexer selection */ -typedef enum ADC_CH_MUXNEG_enum -{ - ADC_CH_MUXNEG_PIN0_gc = (0x00<<0), /* Input pin 0 */ - ADC_CH_MUXNEG_PIN1_gc = (0x01<<0), /* Input pin 1 */ - ADC_CH_MUXNEG_PIN2_gc = (0x02<<0), /* Input pin 2 */ - ADC_CH_MUXNEG_PIN3_gc = (0x03<<0), /* Input pin 3 */ - ADC_CH_MUXNEG_PIN4_gc = (0x00<<0), /* Input pin 4 */ - ADC_CH_MUXNEG_PIN5_gc = (0x01<<0), /* Input pin 5 */ - ADC_CH_MUXNEG_PIN6_gc = (0x02<<0), /* Input pin 6 */ - ADC_CH_MUXNEG_PIN7_gc = (0x03<<0), /* Input pin 7 */ -} ADC_CH_MUXNEG_t; - -/* Input mode */ -typedef enum ADC_CH_INPUTMODE_enum -{ - ADC_CH_INPUTMODE_INTERNAL_gc = (0x00<<0), /* Internal inputs, no gain */ - ADC_CH_INPUTMODE_SINGLEENDED_gc = (0x01<<0), /* Single-ended input, no gain */ - ADC_CH_INPUTMODE_DIFF_gc = (0x02<<0), /* Differential input, no gain */ - ADC_CH_INPUTMODE_DIFFWGAIN_gc = (0x03<<0), /* Differential input, with gain */ -} ADC_CH_INPUTMODE_t; - -/* Gain factor */ -typedef enum ADC_CH_GAIN_enum -{ - ADC_CH_GAIN_1X_gc = (0x00<<2), /* 1x gain */ - ADC_CH_GAIN_2X_gc = (0x01<<2), /* 2x gain */ - ADC_CH_GAIN_4X_gc = (0x02<<2), /* 4x gain */ - ADC_CH_GAIN_8X_gc = (0x03<<2), /* 8x gain */ - ADC_CH_GAIN_16X_gc = (0x04<<2), /* 16x gain */ - ADC_CH_GAIN_32X_gc = (0x05<<2), /* 32x gain */ - ADC_CH_GAIN_64X_gc = (0x06<<2), /* 64x gain */ - ADC_CH_GAIN_DIV2_gc = (0x07<<2), /* x/2 gain */ -} ADC_CH_GAIN_t; - -/* Conversion result resolution */ -typedef enum ADC_RESOLUTION_enum -{ - ADC_RESOLUTION_12BIT_gc = (0x00<<1), /* 12-bit right-adjusted result */ - ADC_RESOLUTION_8BIT_gc = (0x02<<1), /* 8-bit right-adjusted result */ - ADC_RESOLUTION_LEFT12BIT_gc = (0x03<<1), /* 12-bit left-adjusted result */ -} ADC_RESOLUTION_t; - -/* Voltage reference selection */ -typedef enum ADC_REFSEL_enum -{ - ADC_REFSEL_INT1V_gc = (0x00<<4), /* Internal 1V */ - ADC_REFSEL_INTVCC_gc = (0x01<<4), /* Internal VCC / 1.6 */ - ADC_REFSEL_AREFA_gc = (0x02<<4), /* External reference on PORT A */ - ADC_REFSEL_AREFB_gc = (0x03<<4), /* External reference on PORT B */ - ADC_REFSEL_INTVCC2_gc = (0x04<<4), /* Internal VCC / 2 */ -} ADC_REFSEL_t; - -/* Event channel input selection */ -typedef enum ADC_EVSEL_enum -{ - ADC_EVSEL_0_gc = (0x00<<3), /* Event Channel 0 */ - ADC_EVSEL_1_gc = (0x01<<3), /* Event Channel 1 */ - ADC_EVSEL_2_gc = (0x02<<3), /* Event Channel 2 */ - ADC_EVSEL_3_gc = (0x03<<3), /* Event Channel 3 */ -} ADC_EVSEL_t; - -/* Event action selection */ -typedef enum ADC_EVACT_enum -{ - ADC_EVACT_NONE_gc = (0x00<<0), /* No event action */ - ADC_EVACT_CH0_gc = (0x01<<0), /* First event triggers channel 0 */ - ADC_EVACT_SYNCSWEEP_gc = (0x06<<0), /* The ADC is flushed and restarted for accurate timing */ -} ADC_EVACT_t; - -/* Interupt mode */ -typedef enum ADC_CH_INTMODE_enum -{ - ADC_CH_INTMODE_COMPLETE_gc = (0x00<<2), /* Interrupt on conversion complete */ - ADC_CH_INTMODE_BELOW_gc = (0x01<<2), /* Interrupt on result below compare value */ - ADC_CH_INTMODE_ABOVE_gc = (0x03<<2), /* Interrupt on result above compare value */ -} ADC_CH_INTMODE_t; - -/* Interrupt level */ -typedef enum ADC_CH_INTLVL_enum -{ - ADC_CH_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ - ADC_CH_INTLVL_LO_gc = (0x01<<0), /* Low level */ - ADC_CH_INTLVL_MED_gc = (0x02<<0), /* Medium level */ - ADC_CH_INTLVL_HI_gc = (0x03<<0), /* High level */ -} ADC_CH_INTLVL_t; - -/* Clock prescaler */ -typedef enum ADC_PRESCALER_enum -{ - ADC_PRESCALER_DIV4_gc = (0x00<<0), /* Divide clock by 4 */ - ADC_PRESCALER_DIV8_gc = (0x01<<0), /* Divide clock by 8 */ - ADC_PRESCALER_DIV16_gc = (0x02<<0), /* Divide clock by 16 */ - ADC_PRESCALER_DIV32_gc = (0x03<<0), /* Divide clock by 32 */ - ADC_PRESCALER_DIV64_gc = (0x04<<0), /* Divide clock by 64 */ - ADC_PRESCALER_DIV128_gc = (0x05<<0), /* Divide clock by 128 */ - ADC_PRESCALER_DIV256_gc = (0x06<<0), /* Divide clock by 256 */ - ADC_PRESCALER_DIV512_gc = (0x07<<0), /* Divide clock by 512 */ -} ADC_PRESCALER_t; - - -/* --------------------------------------------------------------------------- -AC - Analog Comparator --------------------------------------------------------------------------- -*/ - -/* Analog Comparator */ -typedef struct AC_struct -{ - register8_t AC0CTRL; /* Analog Comparator 0 Control */ - register8_t AC1CTRL; /* Analog Comparator 1 Control */ - register8_t AC0MUXCTRL; /* Analog Comparator 0 MUX Control */ - register8_t AC1MUXCTRL; /* Analog Comparator 1 MUX Control */ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t WINCTRL; /* Window Mode Control */ - register8_t STATUS; /* Status */ -} AC_t; - -/* Interrupt mode */ -typedef enum AC_INTMODE_enum -{ - AC_INTMODE_BOTHEDGES_gc = (0x00<<6), /* Interrupt on both edges */ - AC_INTMODE_FALLING_gc = (0x02<<6), /* Interrupt on falling edge */ - AC_INTMODE_RISING_gc = (0x03<<6), /* Interrupt on rising edge */ -} AC_INTMODE_t; - -/* Interrupt level */ -typedef enum AC_INTLVL_enum -{ - AC_INTLVL_OFF_gc = (0x00<<4), /* Interrupt disabled */ - AC_INTLVL_LO_gc = (0x01<<4), /* Low level */ - AC_INTLVL_MED_gc = (0x02<<4), /* Medium level */ - AC_INTLVL_HI_gc = (0x03<<4), /* High level */ -} AC_INTLVL_t; - -/* Hysteresis mode selection */ -typedef enum AC_HYSMODE_enum -{ - AC_HYSMODE_NO_gc = (0x00<<1), /* No hysteresis */ - AC_HYSMODE_SMALL_gc = (0x01<<1), /* Small hysteresis */ - AC_HYSMODE_LARGE_gc = (0x02<<1), /* Large hysteresis */ -} AC_HYSMODE_t; - -/* Positive input multiplexer selection */ -typedef enum AC_MUXPOS_enum -{ - AC_MUXPOS_PIN0_gc = (0x00<<3), /* Pin 0 */ - AC_MUXPOS_PIN1_gc = (0x01<<3), /* Pin 1 */ - AC_MUXPOS_PIN2_gc = (0x02<<3), /* Pin 2 */ - AC_MUXPOS_PIN3_gc = (0x03<<3), /* Pin 3 */ - AC_MUXPOS_PIN4_gc = (0x04<<3), /* Pin 4 */ - AC_MUXPOS_PIN5_gc = (0x05<<3), /* Pin 5 */ - AC_MUXPOS_PIN6_gc = (0x06<<3), /* Pin 6 */ -} AC_MUXPOS_t; - -/* Negative input multiplexer selection */ -typedef enum AC_MUXNEG_enum -{ - AC_MUXNEG_PIN0_gc = (0x00<<0), /* Pin 0 */ - AC_MUXNEG_PIN1_gc = (0x01<<0), /* Pin 1 */ - AC_MUXNEG_PIN3_gc = (0x02<<0), /* Pin 3 */ - AC_MUXNEG_PIN5_gc = (0x03<<0), /* Pin 5 */ - AC_MUXNEG_PIN7_gc = (0x04<<0), /* Pin 7 */ - AC_MUXNEG_BANDGAP_gc = (0x06<<0), /* Bandgap Reference */ - AC_MUXNEG_SCALER_gc = (0x07<<0), /* Internal voltage scaler */ -} AC_MUXNEG_t; - -/* Windows interrupt mode */ -typedef enum AC_WINTMODE_enum -{ - AC_WINTMODE_ABOVE_gc = (0x00<<2), /* Interrupt on above window */ - AC_WINTMODE_INSIDE_gc = (0x01<<2), /* Interrupt on inside window */ - AC_WINTMODE_BELOW_gc = (0x02<<2), /* Interrupt on below window */ - AC_WINTMODE_OUTSIDE_gc = (0x03<<2), /* Interrupt on outside window */ -} AC_WINTMODE_t; - -/* Window interrupt level */ -typedef enum AC_WINTLVL_enum -{ - AC_WINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ - AC_WINTLVL_LO_gc = (0x01<<0), /* Low priority */ - AC_WINTLVL_MED_gc = (0x02<<0), /* Medium priority */ - AC_WINTLVL_HI_gc = (0x03<<0), /* High priority */ -} AC_WINTLVL_t; - -/* Window mode state */ -typedef enum AC_WSTATE_enum -{ - AC_WSTATE_ABOVE_gc = (0x00<<6), /* Signal above window */ - AC_WSTATE_INSIDE_gc = (0x01<<6), /* Signal inside window */ - AC_WSTATE_BELOW_gc = (0x02<<6), /* Signal below window */ -} AC_WSTATE_t; - - -/* --------------------------------------------------------------------------- -RTC - Real-Time Counter --------------------------------------------------------------------------- -*/ - -/* Real-Time Counter */ -typedef struct RTC_struct -{ - register8_t CTRL; /* Control Register */ - register8_t STATUS; /* Status Register */ - register8_t INTCTRL; /* Interrupt Control Register */ - register8_t INTFLAGS; /* Interrupt Flags */ - register8_t TEMP; /* Temporary register */ - register8_t reserved_0x05; - register8_t reserved_0x06; - register8_t reserved_0x07; - _WORDREGISTER(CNT); /* Count Register */ - _WORDREGISTER(PER); /* Period Register */ - _WORDREGISTER(COMP); /* Compare Register */ -} RTC_t; - -/* Prescaler Factor */ -typedef enum RTC_PRESCALER_enum -{ - RTC_PRESCALER_OFF_gc = (0x00<<0), /* RTC Off */ - RTC_PRESCALER_DIV1_gc = (0x01<<0), /* RTC Clock */ - RTC_PRESCALER_DIV2_gc = (0x02<<0), /* RTC Clock / 2 */ - RTC_PRESCALER_DIV8_gc = (0x03<<0), /* RTC Clock / 8 */ - RTC_PRESCALER_DIV16_gc = (0x04<<0), /* RTC Clock / 16 */ - RTC_PRESCALER_DIV64_gc = (0x05<<0), /* RTC Clock / 64 */ - RTC_PRESCALER_DIV256_gc = (0x06<<0), /* RTC Clock / 256 */ - RTC_PRESCALER_DIV1024_gc = (0x07<<0), /* RTC Clock / 1024 */ -} RTC_PRESCALER_t; - -/* Compare Interrupt level */ -typedef enum RTC_COMPINTLVL_enum -{ - RTC_COMPINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ - RTC_COMPINTLVL_LO_gc = (0x01<<2), /* Low Level */ - RTC_COMPINTLVL_MED_gc = (0x02<<2), /* Medium Level */ - RTC_COMPINTLVL_HI_gc = (0x03<<2), /* High Level */ -} RTC_COMPINTLVL_t; - -/* Overflow Interrupt level */ -typedef enum RTC_OVFINTLVL_enum -{ - RTC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - RTC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ - RTC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ - RTC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ -} RTC_OVFINTLVL_t; - - -/* --------------------------------------------------------------------------- -TWI - Two-Wire Interface --------------------------------------------------------------------------- -*/ - -/* */ -typedef struct TWI_MASTER_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t CTRLC; /* Control Register C */ - register8_t STATUS; /* Status Register */ - register8_t BAUD; /* Baurd Rate Control Register */ - register8_t ADDR; /* Address Register */ - register8_t DATA; /* Data Register */ -} TWI_MASTER_t; - - -/* */ -typedef struct TWI_SLAVE_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t STATUS; /* Status Register */ - register8_t ADDR; /* Address Register */ - register8_t DATA; /* Data Register */ - register8_t ADDRMASK; /* Address Mask Register */ -} TWI_SLAVE_t; - - -/* Two-Wire Interface */ -typedef struct TWI_struct -{ - register8_t CTRL; /* TWI Common Control Register */ - TWI_MASTER_t MASTER; /* TWI master module */ - TWI_SLAVE_t SLAVE; /* TWI slave module */ -} TWI_t; - -/* SDA Hold Time */ -typedef enum TWI_SDAHOLD_enum -{ - TWI_SDAHOLD_OFF_gc = (0x00<<1), /* SDA Hold Time off */ - TWI_SDAHOLD_50NS_gc = (0x01<<1), /* SDA Hold Time 50 ns */ - TWI_SDAHOLD_300NS_gc = (0x02<<1), /* SDA Hold Time 300 ns */ - TWI_SDAHOLD_400NS_gc = (0x03<<1), /* SDA Hold Time 400 ns */ -} TWI_SDAHOLD_t; - -/* Master Interrupt Level */ -typedef enum TWI_MASTER_INTLVL_enum -{ - TWI_MASTER_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ - TWI_MASTER_INTLVL_LO_gc = (0x01<<6), /* Low Level */ - TWI_MASTER_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ - TWI_MASTER_INTLVL_HI_gc = (0x03<<6), /* High Level */ -} TWI_MASTER_INTLVL_t; - -/* Inactive Timeout */ -typedef enum TWI_MASTER_TIMEOUT_enum -{ - TWI_MASTER_TIMEOUT_DISABLED_gc = (0x00<<2), /* Bus Timeout Disabled */ - TWI_MASTER_TIMEOUT_50US_gc = (0x01<<2), /* 50 Microseconds */ - TWI_MASTER_TIMEOUT_100US_gc = (0x02<<2), /* 100 Microseconds */ - TWI_MASTER_TIMEOUT_200US_gc = (0x03<<2), /* 200 Microseconds */ -} TWI_MASTER_TIMEOUT_t; - -/* Master Command */ -typedef enum TWI_MASTER_CMD_enum -{ - TWI_MASTER_CMD_NOACT_gc = (0x00<<0), /* No Action */ - TWI_MASTER_CMD_REPSTART_gc = (0x01<<0), /* Issue Repeated Start Condition */ - TWI_MASTER_CMD_RECVTRANS_gc = (0x02<<0), /* Receive or Transmit Data */ - TWI_MASTER_CMD_STOP_gc = (0x03<<0), /* Issue Stop Condition */ -} TWI_MASTER_CMD_t; - -/* Master Bus State */ -typedef enum TWI_MASTER_BUSSTATE_enum -{ - TWI_MASTER_BUSSTATE_UNKNOWN_gc = (0x00<<0), /* Unknown Bus State */ - TWI_MASTER_BUSSTATE_IDLE_gc = (0x01<<0), /* Bus is Idle */ - TWI_MASTER_BUSSTATE_OWNER_gc = (0x02<<0), /* This Module Controls The Bus */ - TWI_MASTER_BUSSTATE_BUSY_gc = (0x03<<0), /* The Bus is Busy */ -} TWI_MASTER_BUSSTATE_t; - -/* Slave Interrupt Level */ -typedef enum TWI_SLAVE_INTLVL_enum -{ - TWI_SLAVE_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ - TWI_SLAVE_INTLVL_LO_gc = (0x01<<6), /* Low Level */ - TWI_SLAVE_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ - TWI_SLAVE_INTLVL_HI_gc = (0x03<<6), /* High Level */ -} TWI_SLAVE_INTLVL_t; - -/* Slave Command */ -typedef enum TWI_SLAVE_CMD_enum -{ - TWI_SLAVE_CMD_NOACT_gc = (0x00<<0), /* No Action */ - TWI_SLAVE_CMD_COMPTRANS_gc = (0x02<<0), /* Used To Complete a Transaction */ - TWI_SLAVE_CMD_RESPONSE_gc = (0x03<<0), /* Used in Response to Address/Data Interrupt */ -} TWI_SLAVE_CMD_t; - - -/* --------------------------------------------------------------------------- -USB - USB --------------------------------------------------------------------------- -*/ - -/* USB Endpoint */ -typedef struct USB_EP_struct -{ - register8_t STATUS; /* Endpoint Status */ - register8_t CTRL; /* Endpoint Control */ - _WORDREGISTER(CNT); /* USB Endpoint Counter */ - _WORDREGISTER(DATAPTR); /* Data Pointer */ - _WORDREGISTER(AUXDATA); /* Auxiliary Data */ -} USB_EP_t; - - -/* Universal Serial Bus */ -typedef struct USB_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t STATUS; /* Status Register */ - register8_t ADDR; /* Address Register */ - register8_t FIFOWP; /* FIFO Write Pointer Register */ - register8_t FIFORP; /* FIFO Read Pointer Register */ - _WORDREGISTER(EPPTR); /* Endpoint Configuration Table Pointer */ - register8_t INTCTRLA; /* Interrupt Control Register A */ - register8_t INTCTRLB; /* Interrupt Control Register B */ - register8_t INTFLAGSACLR; /* Clear Interrupt Flag Register A */ - register8_t INTFLAGSASET; /* Set Interrupt Flag Register A */ - register8_t INTFLAGSBCLR; /* Clear Interrupt Flag Register B */ - register8_t INTFLAGSBSET; /* Set Interrupt Flag Register B */ - register8_t reserved_0x0E; - register8_t reserved_0x0F; - register8_t reserved_0x10; - register8_t reserved_0x11; - register8_t reserved_0x12; - register8_t reserved_0x13; - register8_t reserved_0x14; - register8_t reserved_0x15; - register8_t reserved_0x16; - register8_t reserved_0x17; - register8_t reserved_0x18; - register8_t reserved_0x19; - register8_t reserved_0x1A; - register8_t reserved_0x1B; - register8_t reserved_0x1C; - register8_t reserved_0x1D; - register8_t reserved_0x1E; - register8_t reserved_0x1F; - register8_t reserved_0x20; - register8_t reserved_0x21; - register8_t reserved_0x22; - register8_t reserved_0x23; - register8_t reserved_0x24; - register8_t reserved_0x25; - register8_t reserved_0x26; - register8_t reserved_0x27; - register8_t reserved_0x28; - register8_t reserved_0x29; - register8_t reserved_0x2A; - register8_t reserved_0x2B; - register8_t reserved_0x2C; - register8_t reserved_0x2D; - register8_t reserved_0x2E; - register8_t reserved_0x2F; - register8_t reserved_0x30; - register8_t reserved_0x31; - register8_t reserved_0x32; - register8_t reserved_0x33; - register8_t reserved_0x34; - register8_t reserved_0x35; - register8_t reserved_0x36; - register8_t reserved_0x37; - register8_t reserved_0x38; - register8_t reserved_0x39; - register8_t CAL0; /* Calibration Byte 0 */ - register8_t CAL1; /* Calibration Byte 1 */ -} USB_t; - - -/* USB Endpoint Table */ -typedef struct USB_EP_TABLE_struct -{ - USB_EP_t EP0OUT; /* Endpoint 0 */ - USB_EP_t EP0IN; /* Endpoint 0 */ - USB_EP_t EP1OUT; /* Endpoint 1 */ - USB_EP_t EP1IN; /* Endpoint 1 */ - USB_EP_t EP2OUT; /* Endpoint 2 */ - USB_EP_t EP2IN; /* Endpoint 2 */ - USB_EP_t EP3OUT; /* Endpoint 3 */ - USB_EP_t EP3IN; /* Endpoint 3 */ - USB_EP_t EP4OUT; /* Endpoint 4 */ - USB_EP_t EP4IN; /* Endpoint 4 */ - USB_EP_t EP5OUT; /* Endpoint 5 */ - USB_EP_t EP5IN; /* Endpoint 5 */ - USB_EP_t EP6OUT; /* Endpoint 6 */ - USB_EP_t EP6IN; /* Endpoint 6 */ - USB_EP_t EP7OUT; /* Endpoint 7 */ - USB_EP_t EP7IN; /* Endpoint 7 */ - USB_EP_t EP8OUT; /* Endpoint 8 */ - USB_EP_t EP8IN; /* Endpoint 8 */ - USB_EP_t EP9OUT; /* Endpoint 9 */ - USB_EP_t EP9IN; /* Endpoint 9 */ - USB_EP_t EP10OUT; /* Endpoint 10 */ - USB_EP_t EP10IN; /* Endpoint 10 */ - USB_EP_t EP11OUT; /* Endpoint 11 */ - USB_EP_t EP11IN; /* Endpoint 11 */ - USB_EP_t EP12OUT; /* Endpoint 12 */ - USB_EP_t EP12IN; /* Endpoint 12 */ - USB_EP_t EP13OUT; /* Endpoint 13 */ - USB_EP_t EP13IN; /* Endpoint 13 */ - USB_EP_t EP14OUT; /* Endpoint 14 */ - USB_EP_t EP14IN; /* Endpoint 14 */ - USB_EP_t EP15OUT; /* Endpoint 15 */ - USB_EP_t EP15IN; /* Endpoint 15 */ - register8_t reserved_0x100; - register8_t reserved_0x101; - register8_t reserved_0x102; - register8_t reserved_0x103; - register8_t reserved_0x104; - register8_t reserved_0x105; - register8_t reserved_0x106; - register8_t reserved_0x107; - register8_t reserved_0x108; - register8_t reserved_0x109; - register8_t reserved_0x10A; - register8_t reserved_0x10B; - register8_t reserved_0x10C; - register8_t reserved_0x10D; - register8_t reserved_0x10E; - register8_t reserved_0x10F; - register8_t FRAMENUML; /* Frame Number Low Byte */ - register8_t FRAMENUMH; /* Frame Number High Byte */ -} USB_EP_TABLE_t; - -/* Interrupt level */ -typedef enum USB_INTLVL_enum -{ - USB_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ - USB_INTLVL_LO_gc = (0x01<<0), /* Low level */ - USB_INTLVL_MED_gc = (0x02<<0), /* Medium level */ - USB_INTLVL_HI_gc = (0x03<<0), /* High level */ -} USB_INTLVL_t; - -/* USB Endpoint Type */ -typedef enum USB_EP_TYPE_enum -{ - USB_EP_TYPE_DISABLE_gc = (0x00<<6), /* Endpoint Disabled */ - USB_EP_TYPE_CONTROL_gc = (0x01<<6), /* Control */ - USB_EP_TYPE_BULK_gc = (0x02<<6), /* Bulk/Interrupt */ - USB_EP_TYPE_ISOCHRONOUS_gc = (0x03<<6), /* Isochronous */ -} USB_EP_TYPE_t; - -/* USB Endpoint Buffersize */ -typedef enum USB_EP_BUFSIZE_enum -{ - USB_EP_BUFSIZE_8_gc = (0x00<<0), /* 8 bytes buffer size */ - USB_EP_BUFSIZE_16_gc = (0x01<<0), /* 16 bytes buffer size */ - USB_EP_BUFSIZE_32_gc = (0x02<<0), /* 32 bytes buffer size */ - USB_EP_BUFSIZE_64_gc = (0x03<<0), /* 64 bytes buffer size */ - USB_EP_BUFSIZE_128_gc = (0x04<<0), /* 128 bytes buffer size */ - USB_EP_BUFSIZE_256_gc = (0x05<<0), /* 256 bytes buffer size */ - USB_EP_BUFSIZE_512_gc = (0x06<<0), /* 512 bytes buffer size */ - USB_EP_BUFSIZE_1023_gc = (0x07<<0), /* 1023 bytes buffer size */ -} USB_EP_BUFSIZE_t; - - -/* --------------------------------------------------------------------------- -PORT - I/O Port Configuration --------------------------------------------------------------------------- -*/ - -/* I/O Ports */ -typedef struct PORT_struct -{ - register8_t DIR; /* I/O Port Data Direction */ - register8_t DIRSET; /* I/O Port Data Direction Set */ - register8_t DIRCLR; /* I/O Port Data Direction Clear */ - register8_t DIRTGL; /* I/O Port Data Direction Toggle */ - register8_t OUT; /* I/O Port Output */ - register8_t OUTSET; /* I/O Port Output Set */ - register8_t OUTCLR; /* I/O Port Output Clear */ - register8_t OUTTGL; /* I/O Port Output Toggle */ - register8_t IN; /* I/O port Input */ - register8_t INTCTRL; /* Interrupt Control Register */ - register8_t INT0MASK; /* Port Interrupt 0 Mask */ - register8_t INT1MASK; /* Port Interrupt 1 Mask */ - register8_t INTFLAGS; /* Interrupt Flag Register */ - register8_t reserved_0x0D; - register8_t REMAP; /* I/O Port Pin Remap Register */ - register8_t reserved_0x0F; - register8_t PIN0CTRL; /* Pin 0 Control Register */ - register8_t PIN1CTRL; /* Pin 1 Control Register */ - register8_t PIN2CTRL; /* Pin 2 Control Register */ - register8_t PIN3CTRL; /* Pin 3 Control Register */ - register8_t PIN4CTRL; /* Pin 4 Control Register */ - register8_t PIN5CTRL; /* Pin 5 Control Register */ - register8_t PIN6CTRL; /* Pin 6 Control Register */ - register8_t PIN7CTRL; /* Pin 7 Control Register */ -} PORT_t; - -/* Port Interrupt 0 Level */ -typedef enum PORT_INT0LVL_enum -{ - PORT_INT0LVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - PORT_INT0LVL_LO_gc = (0x01<<0), /* Low Level */ - PORT_INT0LVL_MED_gc = (0x02<<0), /* Medium Level */ - PORT_INT0LVL_HI_gc = (0x03<<0), /* High Level */ -} PORT_INT0LVL_t; - -/* Port Interrupt 1 Level */ -typedef enum PORT_INT1LVL_enum -{ - PORT_INT1LVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ - PORT_INT1LVL_LO_gc = (0x01<<2), /* Low Level */ - PORT_INT1LVL_MED_gc = (0x02<<2), /* Medium Level */ - PORT_INT1LVL_HI_gc = (0x03<<2), /* High Level */ -} PORT_INT1LVL_t; - -/* Output/Pull Configuration */ -typedef enum PORT_OPC_enum -{ - PORT_OPC_TOTEM_gc = (0x00<<3), /* Totempole */ - PORT_OPC_BUSKEEPER_gc = (0x01<<3), /* Totempole w/ Bus keeper on Input and Output */ - PORT_OPC_PULLDOWN_gc = (0x02<<3), /* Totempole w/ Pull-down on Input */ - PORT_OPC_PULLUP_gc = (0x03<<3), /* Totempole w/ Pull-up on Input */ - PORT_OPC_WIREDOR_gc = (0x04<<3), /* Wired OR */ - PORT_OPC_WIREDAND_gc = (0x05<<3), /* Wired AND */ - PORT_OPC_WIREDORPULL_gc = (0x06<<3), /* Wired OR w/ Pull-down */ - PORT_OPC_WIREDANDPULL_gc = (0x07<<3), /* Wired AND w/ Pull-up */ -} PORT_OPC_t; - -/* Input/Sense Configuration */ -typedef enum PORT_ISC_enum -{ - PORT_ISC_BOTHEDGES_gc = (0x00<<0), /* Sense Both Edges */ - PORT_ISC_RISING_gc = (0x01<<0), /* Sense Rising Edge */ - PORT_ISC_FALLING_gc = (0x02<<0), /* Sense Falling Edge */ - PORT_ISC_LEVEL_gc = (0x03<<0), /* Sense Level (Transparent For Events) */ - PORT_ISC_INPUT_DISABLE_gc = (0x07<<0), /* Disable Digital Input Buffer */ -} PORT_ISC_t; - - -/* --------------------------------------------------------------------------- -TC - 16-bit Timer/Counter With PWM --------------------------------------------------------------------------- -*/ - -/* 16-bit Timer/Counter 0 */ -typedef struct TC0_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t CTRLC; /* Control register C */ - register8_t CTRLD; /* Control Register D */ - register8_t CTRLE; /* Control Register E */ - register8_t reserved_0x05; - register8_t INTCTRLA; /* Interrupt Control Register A */ - register8_t INTCTRLB; /* Interrupt Control Register B */ - register8_t CTRLFCLR; /* Control Register F Clear */ - register8_t CTRLFSET; /* Control Register F Set */ - register8_t CTRLGCLR; /* Control Register G Clear */ - register8_t CTRLGSET; /* Control Register G Set */ - register8_t INTFLAGS; /* Interrupt Flag Register */ - register8_t reserved_0x0D; - register8_t reserved_0x0E; - register8_t TEMP; /* Temporary Register For 16-bit Access */ - register8_t reserved_0x10; - register8_t reserved_0x11; - register8_t reserved_0x12; - register8_t reserved_0x13; - register8_t reserved_0x14; - register8_t reserved_0x15; - register8_t reserved_0x16; - register8_t reserved_0x17; - register8_t reserved_0x18; - register8_t reserved_0x19; - register8_t reserved_0x1A; - register8_t reserved_0x1B; - register8_t reserved_0x1C; - register8_t reserved_0x1D; - register8_t reserved_0x1E; - register8_t reserved_0x1F; - _WORDREGISTER(CNT); /* Count */ - register8_t reserved_0x22; - register8_t reserved_0x23; - register8_t reserved_0x24; - register8_t reserved_0x25; - _WORDREGISTER(PER); /* Period */ - _WORDREGISTER(CCA); /* Compare or Capture A */ - _WORDREGISTER(CCB); /* Compare or Capture B */ - _WORDREGISTER(CCC); /* Compare or Capture C */ - _WORDREGISTER(CCD); /* Compare or Capture D */ - register8_t reserved_0x30; - register8_t reserved_0x31; - register8_t reserved_0x32; - register8_t reserved_0x33; - register8_t reserved_0x34; - register8_t reserved_0x35; - _WORDREGISTER(PERBUF); /* Period Buffer */ - _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ - _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ - _WORDREGISTER(CCCBUF); /* Compare Or Capture C Buffer */ - _WORDREGISTER(CCDBUF); /* Compare Or Capture D Buffer */ -} TC0_t; - - -/* 16-bit Timer/Counter 1 */ -typedef struct TC1_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t CTRLC; /* Control register C */ - register8_t CTRLD; /* Control Register D */ - register8_t CTRLE; /* Control Register E */ - register8_t reserved_0x05; - register8_t INTCTRLA; /* Interrupt Control Register A */ - register8_t INTCTRLB; /* Interrupt Control Register B */ - register8_t CTRLFCLR; /* Control Register F Clear */ - register8_t CTRLFSET; /* Control Register F Set */ - register8_t CTRLGCLR; /* Control Register G Clear */ - register8_t CTRLGSET; /* Control Register G Set */ - register8_t INTFLAGS; /* Interrupt Flag Register */ - register8_t reserved_0x0D; - register8_t reserved_0x0E; - register8_t TEMP; /* Temporary Register For 16-bit Access */ - register8_t reserved_0x10; - register8_t reserved_0x11; - register8_t reserved_0x12; - register8_t reserved_0x13; - register8_t reserved_0x14; - register8_t reserved_0x15; - register8_t reserved_0x16; - register8_t reserved_0x17; - register8_t reserved_0x18; - register8_t reserved_0x19; - register8_t reserved_0x1A; - register8_t reserved_0x1B; - register8_t reserved_0x1C; - register8_t reserved_0x1D; - register8_t reserved_0x1E; - register8_t reserved_0x1F; - _WORDREGISTER(CNT); /* Count */ - register8_t reserved_0x22; - register8_t reserved_0x23; - register8_t reserved_0x24; - register8_t reserved_0x25; - _WORDREGISTER(PER); /* Period */ - _WORDREGISTER(CCA); /* Compare or Capture A */ - _WORDREGISTER(CCB); /* Compare or Capture B */ - register8_t reserved_0x2C; - register8_t reserved_0x2D; - register8_t reserved_0x2E; - register8_t reserved_0x2F; - register8_t reserved_0x30; - register8_t reserved_0x31; - register8_t reserved_0x32; - register8_t reserved_0x33; - register8_t reserved_0x34; - register8_t reserved_0x35; - _WORDREGISTER(PERBUF); /* Period Buffer */ - _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ - _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ -} TC1_t; - -/* Clock Selection */ -typedef enum TC_CLKSEL_enum -{ - TC_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */ - TC_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */ - TC_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */ - TC_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */ - TC_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */ - TC_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */ - TC_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */ - TC_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */ - TC_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */ - TC_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */ - TC_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */ - TC_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */ -} TC_CLKSEL_t; - -/* Waveform Generation Mode */ -typedef enum TC_WGMODE_enum -{ - TC_WGMODE_NORMAL_gc = (0x00<<0), /* Normal Mode */ - TC_WGMODE_FRQ_gc = (0x01<<0), /* Frequency Generation Mode */ - TC_WGMODE_SINGLESLOPE_gc = (0x03<<0), /* Single Slope */ - TC_WGMODE_SS_gc = (0x03<<0), /* Single Slope */ - TC_WGMODE_DSTOP_gc = (0x05<<0), /* Dual Slope, Update on TOP */ - TC_WGMODE_DS_T_gc = (0x05<<0), /* Dual Slope, Update on TOP */ - TC_WGMODE_DSBOTH_gc = (0x06<<0), /* Dual Slope, Update on both TOP and BOTTOM */ - TC_WGMODE_DS_TB_gc = (0x06<<0), /* Dual Slope, Update on both TOP and BOTTOM */ - TC_WGMODE_DSBOTTOM_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */ - TC_WGMODE_DS_B_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */ -} TC_WGMODE_t; - -/* Byte Mode */ -typedef enum TC_BYTEM_enum -{ - TC_BYTEM_NORMAL_gc = (0x00<<0), /* 16-bit mode */ - TC_BYTEM_BYTEMODE_gc = (0x01<<0), /* Timer/Counter operating in byte mode only */ - TC_BYTEM_SPLITMODE_gc = (0x02<<0), /* Timer/Counter split into two 8-bit Counters (TC2) */ -} TC_BYTEM_t; - -/* Event Action */ -typedef enum TC_EVACT_enum -{ - TC_EVACT_OFF_gc = (0x00<<5), /* No Event Action */ - TC_EVACT_CAPT_gc = (0x01<<5), /* Input Capture */ - TC_EVACT_UPDOWN_gc = (0x02<<5), /* Externally Controlled Up/Down Count */ - TC_EVACT_QDEC_gc = (0x03<<5), /* Quadrature Decode */ - TC_EVACT_RESTART_gc = (0x04<<5), /* Restart */ - TC_EVACT_FRQ_gc = (0x05<<5), /* Frequency Capture */ - TC_EVACT_PW_gc = (0x06<<5), /* Pulse-width Capture */ -} TC_EVACT_t; - -/* Event Selection */ -typedef enum TC_EVSEL_enum -{ - TC_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ - TC_EVSEL_CH0_gc = (0x08<<0), /* Event Channel 0 */ - TC_EVSEL_CH1_gc = (0x09<<0), /* Event Channel 1 */ - TC_EVSEL_CH2_gc = (0x0A<<0), /* Event Channel 2 */ - TC_EVSEL_CH3_gc = (0x0B<<0), /* Event Channel 3 */ -} TC_EVSEL_t; - -/* Error Interrupt Level */ -typedef enum TC_ERRINTLVL_enum -{ - TC_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ - TC_ERRINTLVL_LO_gc = (0x01<<2), /* Low Level */ - TC_ERRINTLVL_MED_gc = (0x02<<2), /* Medium Level */ - TC_ERRINTLVL_HI_gc = (0x03<<2), /* High Level */ -} TC_ERRINTLVL_t; - -/* Overflow Interrupt Level */ -typedef enum TC_OVFINTLVL_enum -{ - TC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - TC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ - TC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ - TC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ -} TC_OVFINTLVL_t; - -/* Compare or Capture D Interrupt Level */ -typedef enum TC_CCDINTLVL_enum -{ - TC_CCDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ - TC_CCDINTLVL_LO_gc = (0x01<<6), /* Low Level */ - TC_CCDINTLVL_MED_gc = (0x02<<6), /* Medium Level */ - TC_CCDINTLVL_HI_gc = (0x03<<6), /* High Level */ -} TC_CCDINTLVL_t; - -/* Compare or Capture C Interrupt Level */ -typedef enum TC_CCCINTLVL_enum -{ - TC_CCCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ - TC_CCCINTLVL_LO_gc = (0x01<<4), /* Low Level */ - TC_CCCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ - TC_CCCINTLVL_HI_gc = (0x03<<4), /* High Level */ -} TC_CCCINTLVL_t; - -/* Compare or Capture B Interrupt Level */ -typedef enum TC_CCBINTLVL_enum -{ - TC_CCBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ - TC_CCBINTLVL_LO_gc = (0x01<<2), /* Low Level */ - TC_CCBINTLVL_MED_gc = (0x02<<2), /* Medium Level */ - TC_CCBINTLVL_HI_gc = (0x03<<2), /* High Level */ -} TC_CCBINTLVL_t; - -/* Compare or Capture A Interrupt Level */ -typedef enum TC_CCAINTLVL_enum -{ - TC_CCAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - TC_CCAINTLVL_LO_gc = (0x01<<0), /* Low Level */ - TC_CCAINTLVL_MED_gc = (0x02<<0), /* Medium Level */ - TC_CCAINTLVL_HI_gc = (0x03<<0), /* High Level */ -} TC_CCAINTLVL_t; - -/* Timer/Counter Command */ -typedef enum TC_CMD_enum -{ - TC_CMD_NONE_gc = (0x00<<2), /* No Command */ - TC_CMD_UPDATE_gc = (0x01<<2), /* Force Update */ - TC_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ - TC_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ -} TC_CMD_t; - - -/* --------------------------------------------------------------------------- -TC2 - 16-bit Timer/Counter type 2 --------------------------------------------------------------------------- -*/ - -/* 16-bit Timer/Counter type 2 */ -typedef struct TC2_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t CTRLC; /* Control register C */ - register8_t reserved_0x03; - register8_t CTRLE; /* Control Register E */ - register8_t reserved_0x05; - register8_t INTCTRLA; /* Interrupt Control Register A */ - register8_t INTCTRLB; /* Interrupt Control Register B */ - register8_t reserved_0x08; - register8_t CTRLF; /* Control Register F */ - register8_t reserved_0x0A; - register8_t reserved_0x0B; - register8_t INTFLAGS; /* Interrupt Flag Register */ - register8_t reserved_0x0D; - register8_t reserved_0x0E; - register8_t reserved_0x0F; - register8_t reserved_0x10; - register8_t reserved_0x11; - register8_t reserved_0x12; - register8_t reserved_0x13; - register8_t reserved_0x14; - register8_t reserved_0x15; - register8_t reserved_0x16; - register8_t reserved_0x17; - register8_t reserved_0x18; - register8_t reserved_0x19; - register8_t reserved_0x1A; - register8_t reserved_0x1B; - register8_t reserved_0x1C; - register8_t reserved_0x1D; - register8_t reserved_0x1E; - register8_t reserved_0x1F; - register8_t LCNT; /* Low Byte Count */ - register8_t HCNT; /* High Byte Count */ - register8_t reserved_0x22; - register8_t reserved_0x23; - register8_t reserved_0x24; - register8_t reserved_0x25; - register8_t LPER; /* Low Byte Period */ - register8_t HPER; /* High Byte Period */ - register8_t LCMPA; /* Low Byte Compare A */ - register8_t HCMPA; /* High Byte Compare A */ - register8_t LCMPB; /* Low Byte Compare B */ - register8_t HCMPB; /* High Byte Compare B */ - register8_t LCMPC; /* Low Byte Compare C */ - register8_t HCMPC; /* High Byte Compare C */ - register8_t LCMPD; /* Low Byte Compare D */ - register8_t HCMPD; /* High Byte Compare D */ -} TC2_t; - -/* Clock Selection */ -typedef enum TC2_CLKSEL_enum -{ - TC2_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */ - TC2_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */ - TC2_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */ - TC2_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */ - TC2_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */ - TC2_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */ - TC2_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */ - TC2_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */ - TC2_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */ - TC2_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */ - TC2_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */ - TC2_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */ -} TC2_CLKSEL_t; - -/* Byte Mode */ -typedef enum TC2_BYTEM_enum -{ - TC2_BYTEM_NORMAL_gc = (0x00<<0), /* 16-bit mode */ - TC2_BYTEM_BYTEMODE_gc = (0x01<<0), /* Timer/Counter operating in byte mode only (TC2) */ - TC2_BYTEM_SPLITMODE_gc = (0x02<<0), /* Timer/Counter split into two 8-bit Counters */ -} TC2_BYTEM_t; - -/* High Byte Underflow Interrupt Level */ -typedef enum TC2_HUNFINTLVL_enum -{ - TC2_HUNFINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ - TC2_HUNFINTLVL_LO_gc = (0x01<<2), /* Low Level */ - TC2_HUNFINTLVL_MED_gc = (0x02<<2), /* Medium Level */ - TC2_HUNFINTLVL_HI_gc = (0x03<<2), /* High Level */ -} TC2_HUNFINTLVL_t; - -/* Low Byte Underflow Interrupt Level */ -typedef enum TC2_LUNFINTLVL_enum -{ - TC2_LUNFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - TC2_LUNFINTLVL_LO_gc = (0x01<<0), /* Low Level */ - TC2_LUNFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ - TC2_LUNFINTLVL_HI_gc = (0x03<<0), /* High Level */ -} TC2_LUNFINTLVL_t; - -/* Low Byte Compare D Interrupt Level */ -typedef enum TC2_LCMPDINTLVL_enum -{ - TC2_LCMPDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ - TC2_LCMPDINTLVL_LO_gc = (0x01<<6), /* Low Level */ - TC2_LCMPDINTLVL_MED_gc = (0x02<<6), /* Medium Level */ - TC2_LCMPDINTLVL_HI_gc = (0x03<<6), /* High Level */ -} TC2_LCMPDINTLVL_t; - -/* Low Byte Compare C Interrupt Level */ -typedef enum TC2_LCMPCINTLVL_enum -{ - TC2_LCMPCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ - TC2_LCMPCINTLVL_LO_gc = (0x01<<4), /* Low Level */ - TC2_LCMPCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ - TC2_LCMPCINTLVL_HI_gc = (0x03<<4), /* High Level */ -} TC2_LCMPCINTLVL_t; - -/* Low Byte Compare B Interrupt Level */ -typedef enum TC2_LCMPBINTLVL_enum -{ - TC2_LCMPBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ - TC2_LCMPBINTLVL_LO_gc = (0x01<<2), /* Low Level */ - TC2_LCMPBINTLVL_MED_gc = (0x02<<2), /* Medium Level */ - TC2_LCMPBINTLVL_HI_gc = (0x03<<2), /* High Level */ -} TC2_LCMPBINTLVL_t; - -/* Low Byte Compare A Interrupt Level */ -typedef enum TC2_LCMPAINTLVL_enum -{ - TC2_LCMPAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - TC2_LCMPAINTLVL_LO_gc = (0x01<<0), /* Low Level */ - TC2_LCMPAINTLVL_MED_gc = (0x02<<0), /* Medium Level */ - TC2_LCMPAINTLVL_HI_gc = (0x03<<0), /* High Level */ -} TC2_LCMPAINTLVL_t; - -/* Timer/Counter Command */ -typedef enum TC2_CMD_enum -{ - TC2_CMD_NONE_gc = (0x00<<2), /* No Command */ - TC2_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ - TC2_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ -} TC2_CMD_t; - -/* Timer/Counter Command */ -typedef enum TC2_CMDEN_enum -{ - TC2_CMDEN_LOW_gc = (0x01<<0), /* Low Byte Timer/Counter */ - TC2_CMDEN_HIGH_gc = (0x02<<0), /* High Byte Timer/Counter */ - TC2_CMDEN_BOTH_gc = (0x03<<0), /* Both Low Byte and High Byte Timer/Counters */ -} TC2_CMDEN_t; - - -/* --------------------------------------------------------------------------- -AWEX - Timer/Counter Advanced Waveform Extension --------------------------------------------------------------------------- -*/ - -/* Advanced Waveform Extension */ -typedef struct AWEX_struct -{ - register8_t CTRL; /* Control Register */ - register8_t reserved_0x01; - register8_t FDEMASK; /* Fault Detection Event Mask */ - register8_t FDCTRL; /* Fault Detection Control Register */ - register8_t STATUS; /* Status Register */ - register8_t STATUSSET; /* Status Set Register */ - register8_t DTBOTH; /* Dead Time Both Sides */ - register8_t DTBOTHBUF; /* Dead Time Both Sides Buffer */ - register8_t DTLS; /* Dead Time Low Side */ - register8_t DTHS; /* Dead Time High Side */ - register8_t DTLSBUF; /* Dead Time Low Side Buffer */ - register8_t DTHSBUF; /* Dead Time High Side Buffer */ - register8_t OUTOVEN; /* Output Override Enable */ -} AWEX_t; - -/* Fault Detect Action */ -typedef enum AWEX_FDACT_enum -{ - AWEX_FDACT_NONE_gc = (0x00<<0), /* No Fault Protection */ - AWEX_FDACT_CLEAROE_gc = (0x01<<0), /* Clear Output Enable Bits */ - AWEX_FDACT_CLEARDIR_gc = (0x03<<0), /* Clear I/O Port Direction Bits */ -} AWEX_FDACT_t; - - -/* --------------------------------------------------------------------------- -HIRES - Timer/Counter High-Resolution Extension --------------------------------------------------------------------------- -*/ - -/* High-Resolution Extension */ -typedef struct HIRES_struct -{ - register8_t CTRLA; /* Control Register */ -} HIRES_t; - -/* High Resolution Enable */ -typedef enum HIRES_HREN_enum -{ - HIRES_HREN_NONE_gc = (0x00<<0), /* No Fault Protection */ - HIRES_HREN_TC0_gc = (0x01<<0), /* Enable High Resolution on Timer/Counter 0 */ - HIRES_HREN_TC1_gc = (0x02<<0), /* Enable High Resolution on Timer/Counter 1 */ - HIRES_HREN_BOTH_gc = (0x03<<0), /* Enable High Resolution both Timer/Counters */ -} HIRES_HREN_t; - - -/* --------------------------------------------------------------------------- -USART - Universal Asynchronous Receiver-Transmitter --------------------------------------------------------------------------- -*/ - -/* Universal Synchronous/Asynchronous Receiver/Transmitter */ -typedef struct USART_struct -{ - register8_t DATA; /* Data Register */ - register8_t STATUS; /* Status Register */ - register8_t reserved_0x02; - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t CTRLC; /* Control Register C */ - register8_t BAUDCTRLA; /* Baud Rate Control Register A */ - register8_t BAUDCTRLB; /* Baud Rate Control Register B */ -} USART_t; - -/* Receive Complete Interrupt level */ -typedef enum USART_RXCINTLVL_enum -{ - USART_RXCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ - USART_RXCINTLVL_LO_gc = (0x01<<4), /* Low Level */ - USART_RXCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ - USART_RXCINTLVL_HI_gc = (0x03<<4), /* High Level */ -} USART_RXCINTLVL_t; - -/* Transmit Complete Interrupt level */ -typedef enum USART_TXCINTLVL_enum -{ - USART_TXCINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ - USART_TXCINTLVL_LO_gc = (0x01<<2), /* Low Level */ - USART_TXCINTLVL_MED_gc = (0x02<<2), /* Medium Level */ - USART_TXCINTLVL_HI_gc = (0x03<<2), /* High Level */ -} USART_TXCINTLVL_t; - -/* Data Register Empty Interrupt level */ -typedef enum USART_DREINTLVL_enum -{ - USART_DREINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - USART_DREINTLVL_LO_gc = (0x01<<0), /* Low Level */ - USART_DREINTLVL_MED_gc = (0x02<<0), /* Medium Level */ - USART_DREINTLVL_HI_gc = (0x03<<0), /* High Level */ -} USART_DREINTLVL_t; - -/* Character Size */ -typedef enum USART_CHSIZE_enum -{ - USART_CHSIZE_5BIT_gc = (0x00<<0), /* Character size: 5 bit */ - USART_CHSIZE_6BIT_gc = (0x01<<0), /* Character size: 6 bit */ - USART_CHSIZE_7BIT_gc = (0x02<<0), /* Character size: 7 bit */ - USART_CHSIZE_8BIT_gc = (0x03<<0), /* Character size: 8 bit */ - USART_CHSIZE_9BIT_gc = (0x07<<0), /* Character size: 9 bit */ -} USART_CHSIZE_t; - -/* Communication Mode */ -typedef enum USART_CMODE_enum -{ - USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6), /* Asynchronous Mode */ - USART_CMODE_SYNCHRONOUS_gc = (0x01<<6), /* Synchronous Mode */ - USART_CMODE_IRDA_gc = (0x02<<6), /* IrDA Mode */ - USART_CMODE_MSPI_gc = (0x03<<6), /* Master SPI Mode */ -} USART_CMODE_t; - -/* Parity Mode */ -typedef enum USART_PMODE_enum -{ - USART_PMODE_DISABLED_gc = (0x00<<4), /* No Parity */ - USART_PMODE_EVEN_gc = (0x02<<4), /* Even Parity */ - USART_PMODE_ODD_gc = (0x03<<4), /* Odd Parity */ -} USART_PMODE_t; - - -/* --------------------------------------------------------------------------- -SPI - Serial Peripheral Interface --------------------------------------------------------------------------- -*/ - -/* Serial Peripheral Interface */ -typedef struct SPI_struct -{ - register8_t CTRL; /* Control Register */ - register8_t INTCTRL; /* Interrupt Control Register */ - register8_t STATUS; /* Status Register */ - register8_t DATA; /* Data Register */ -} SPI_t; - -/* SPI Mode */ -typedef enum SPI_MODE_enum -{ - SPI_MODE_0_gc = (0x00<<2), /* SPI Mode 0 */ - SPI_MODE_1_gc = (0x01<<2), /* SPI Mode 1 */ - SPI_MODE_2_gc = (0x02<<2), /* SPI Mode 2 */ - SPI_MODE_3_gc = (0x03<<2), /* SPI Mode 3 */ -} SPI_MODE_t; - -/* Prescaler setting */ -typedef enum SPI_PRESCALER_enum -{ - SPI_PRESCALER_DIV4_gc = (0x00<<0), /* System Clock / 4 */ - SPI_PRESCALER_DIV16_gc = (0x01<<0), /* System Clock / 16 */ - SPI_PRESCALER_DIV64_gc = (0x02<<0), /* System Clock / 64 */ - SPI_PRESCALER_DIV128_gc = (0x03<<0), /* System Clock / 128 */ -} SPI_PRESCALER_t; - -/* Interrupt level */ -typedef enum SPI_INTLVL_enum -{ - SPI_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - SPI_INTLVL_LO_gc = (0x01<<0), /* Low Level */ - SPI_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ - SPI_INTLVL_HI_gc = (0x03<<0), /* High Level */ -} SPI_INTLVL_t; - - -/* --------------------------------------------------------------------------- -IRCOM - IR Communication Module --------------------------------------------------------------------------- -*/ - -/* IR Communication Module */ -typedef struct IRCOM_struct -{ - register8_t CTRL; /* Control Register */ - register8_t TXPLCTRL; /* IrDA Transmitter Pulse Length Control Register */ - register8_t RXPLCTRL; /* IrDA Receiver Pulse Length Control Register */ -} IRCOM_t; - -/* Event channel selection */ -typedef enum IRDA_EVSEL_enum -{ - IRDA_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ - IRDA_EVSEL_0_gc = (0x08<<0), /* Event Channel 0 */ - IRDA_EVSEL_1_gc = (0x09<<0), /* Event Channel 1 */ - IRDA_EVSEL_2_gc = (0x0A<<0), /* Event Channel 2 */ - IRDA_EVSEL_3_gc = (0x0B<<0), /* Event Channel 3 */ -} IRDA_EVSEL_t; - - -/* --------------------------------------------------------------------------- -FUSE - Fuses and Lockbits --------------------------------------------------------------------------- -*/ - -/* Fuses */ -typedef struct NVM_FUSES_struct -{ - register8_t reserved_0x00; - register8_t FUSEBYTE1; /* Watchdog Configuration */ - register8_t FUSEBYTE2; /* Reset Configuration */ - register8_t reserved_0x03; - register8_t FUSEBYTE4; /* Start-up Configuration */ - register8_t FUSEBYTE5; /* EESAVE and BOD Level */ -} NVM_FUSES_t; - -/* Boot Loader Section Reset Vector */ -typedef enum BOOTRST_enum -{ - BOOTRST_BOOTLDR_gc = (0x00<<6), /* Boot Loader Reset */ - BOOTRST_APPLICATION_gc = (0x01<<6), /* Application Reset */ -} BOOTRST_t; - -/* Timer Oscillator pin location */ -typedef enum TOSCSEL_enum -{ - TOSCSEL_ALTERNATE_gc = (0x00<<5), /* TOSC1 / TOSC2 on separate pins */ - TOSCSEL_XTAL_gc = (0x01<<5), /* TOSC1 / TOSC2 shared with XTAL1 / XTAL2 */ -} TOSCSEL_t; - -/* BOD operation */ -typedef enum BOD_enum -{ - BOD_SAMPLED_gc = (0x01<<0), /* BOD enabled in sampled mode */ - BOD_CONTINUOUS_gc = (0x02<<0), /* BOD enabled continuously */ - BOD_DISABLED_gc = (0x03<<0), /* BOD Disabled */ -} BOD_t; - -/* BOD operation */ -typedef enum BODACT_enum -{ - BODACT_SAMPLED_gc = (0x01<<4), /* BOD enabled in sampled mode */ - BODACT_CONTINUOUS_gc = (0x02<<4), /* BOD enabled continuously */ - BODACT_DISABLED_gc = (0x03<<4), /* BOD Disabled */ -} BODACT_t; - -/* Watchdog (Window) Timeout Period */ -typedef enum WD_enum -{ - WD_8CLK_gc = (0x00<<4), /* 8 cycles (8ms @ 3.3V) */ - WD_16CLK_gc = (0x01<<4), /* 16 cycles (16ms @ 3.3V) */ - WD_32CLK_gc = (0x02<<4), /* 32 cycles (32ms @ 3.3V) */ - WD_64CLK_gc = (0x03<<4), /* 64 cycles (64ms @ 3.3V) */ - WD_128CLK_gc = (0x04<<4), /* 128 cycles (0.125s @ 3.3V) */ - WD_256CLK_gc = (0x05<<4), /* 256 cycles (0.25s @ 3.3V) */ - WD_512CLK_gc = (0x06<<4), /* 512 cycles (0.5s @ 3.3V) */ - WD_1KCLK_gc = (0x07<<4), /* 1K cycles (1s @ 3.3V) */ - WD_2KCLK_gc = (0x08<<4), /* 2K cycles (2s @ 3.3V) */ - WD_4KCLK_gc = (0x09<<4), /* 4K cycles (4s @ 3.3V) */ - WD_8KCLK_gc = (0x0A<<4), /* 8K cycles (8s @ 3.3V) */ -} WD_t; - -/* Watchdog (Window) Timeout Period */ -typedef enum WDP_enum -{ - WDP_8CLK_gc = (0x00<<0), /* 8 cycles (8ms @ 3.3V) */ - WDP_16CLK_gc = (0x01<<0), /* 16 cycles (16ms @ 3.3V) */ - WDP_32CLK_gc = (0x02<<0), /* 32 cycles (32ms @ 3.3V) */ - WDP_64CLK_gc = (0x03<<0), /* 64 cycles (64ms @ 3.3V) */ - WDP_128CLK_gc = (0x04<<0), /* 128 cycles (0.125s @ 3.3V) */ - WDP_256CLK_gc = (0x05<<0), /* 256 cycles (0.25s @ 3.3V) */ - WDP_512CLK_gc = (0x06<<0), /* 512 cycles (0.5s @ 3.3V) */ - WDP_1KCLK_gc = (0x07<<0), /* 1K cycles (1s @ 3.3V) */ - WDP_2KCLK_gc = (0x08<<0), /* 2K cycles (2s @ 3.3V) */ - WDP_4KCLK_gc = (0x09<<0), /* 4K cycles (4s @ 3.3V) */ - WDP_8KCLK_gc = (0x0A<<0), /* 8K cycles (8s @ 3.3V) */ -} WDP_t; - -/* Start-up Time */ -typedef enum SUT_enum -{ - SUT_0MS_gc = (0x03<<2), /* 0 ms */ - SUT_4MS_gc = (0x01<<2), /* 4 ms */ - SUT_64MS_gc = (0x00<<2), /* 64 ms */ -} SUT_t; - -/* Brownout Detection Voltage Level */ -typedef enum BODLVL_enum -{ - BODLVL_1V6_gc = (0x07<<0), /* 1.6 V */ - BODLVL_1V8_gc = (0x06<<0), /* 1.8 V */ - BODLVL_2V0_gc = (0x05<<0), /* 2.0 V */ - BODLVL_2V2_gc = (0x04<<0), /* 2.2 V */ - BODLVL_2V4_gc = (0x03<<0), /* 2.4 V */ - BODLVL_2V6_gc = (0x02<<0), /* 2.6 V */ - BODLVL_2V8_gc = (0x01<<0), /* 2.8 V */ - BODLVL_3V0_gc = (0x00<<0), /* 3.0 V */ -} BODLVL_t; - - -/* --------------------------------------------------------------------------- -LOCKBIT - Fuses and Lockbits --------------------------------------------------------------------------- -*/ - -/* Lock Bits */ -typedef struct NVM_LOCKBITS_struct -{ - register8_t LOCK_BITS; /* Lock Bits (Changed from LOCKBITS to avoid avr-libc collision) */ -} NVM_LOCKBITS_t; - -/* Boot lock bits - boot setcion */ -typedef enum FUSE_BLBB_enum -{ - FUSE_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ - FUSE_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ - FUSE_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ - FUSE_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ -} FUSE_BLBB_t; - -/* Boot lock bits - application section */ -typedef enum FUSE_BLBA_enum -{ - FUSE_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ - FUSE_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ - FUSE_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ - FUSE_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ -} FUSE_BLBA_t; - -/* Boot lock bits - application table section */ -typedef enum FUSE_BLBAT_enum -{ - FUSE_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ - FUSE_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ - FUSE_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ - FUSE_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ -} FUSE_BLBAT_t; - -/* Lock bits */ -typedef enum FUSE_LB_enum -{ - FUSE_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ - FUSE_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ - FUSE_LB_NOLOCK_gc = (0x03<<0), /* No locks */ -} FUSE_LB_t; - - -/* --------------------------------------------------------------------------- -SIGROW - Signature Row --------------------------------------------------------------------------- -*/ - -/* Production Signatures */ -typedef struct NVM_PROD_SIGNATURES_struct -{ - register8_t RCOSC2M; /* RCOSC 2 MHz Calibration Value B */ - register8_t RCOSC2MA; /* RCOSC 2 MHz Calibration Value A */ - register8_t RCOSC32K; /* RCOSC 32.768 kHz Calibration Value */ - register8_t RCOSC32M; /* RCOSC 32 MHz Calibration Value B */ - register8_t RCOSC32MA; /* RCOSC 32 MHz Calibration Value A */ - register8_t reserved_0x05; - register8_t reserved_0x06; - register8_t reserved_0x07; - register8_t LOTNUM0; /* Lot Number Byte 0, ASCII */ - register8_t LOTNUM1; /* Lot Number Byte 1, ASCII */ - register8_t LOTNUM2; /* Lot Number Byte 2, ASCII */ - register8_t LOTNUM3; /* Lot Number Byte 3, ASCII */ - register8_t LOTNUM4; /* Lot Number Byte 4, ASCII */ - register8_t LOTNUM5; /* Lot Number Byte 5, ASCII */ - register8_t reserved_0x0E; - register8_t reserved_0x0F; - register8_t WAFNUM; /* Wafer Number */ - register8_t reserved_0x11; - register8_t COORDX0; /* Wafer Coordinate X Byte 0 */ - register8_t COORDX1; /* Wafer Coordinate X Byte 1 */ - register8_t COORDY0; /* Wafer Coordinate Y Byte 0 */ - register8_t COORDY1; /* Wafer Coordinate Y Byte 1 */ - register8_t reserved_0x16; - register8_t reserved_0x17; - register8_t reserved_0x18; - register8_t reserved_0x19; - register8_t USBCAL0; /* USB Calibration Byte 0 */ - register8_t USBCAL1; /* USB Calibration Byte 1 */ - register8_t USBRCOSC; /* USB RCOSC Calibration Value B */ - register8_t USBRCOSCA; /* USB RCOSC Calibration Value A */ - register8_t reserved_0x1E; - register8_t reserved_0x1F; - register8_t ADCACAL0; /* ADCA Calibration Byte 0 */ - register8_t ADCACAL1; /* ADCA Calibration Byte 1 */ - register8_t reserved_0x22; - register8_t reserved_0x23; - register8_t reserved_0x24; - register8_t reserved_0x25; - register8_t reserved_0x26; - register8_t reserved_0x27; - register8_t reserved_0x28; - register8_t reserved_0x29; - register8_t reserved_0x2A; - register8_t reserved_0x2B; - register8_t reserved_0x2C; - register8_t reserved_0x2D; - register8_t TEMPSENSE0; /* Temperature Sensor Calibration Byte 0 */ - register8_t TEMPSENSE1; /* Temperature Sensor Calibration Byte 1 */ - register8_t reserved_0x30; - register8_t reserved_0x31; - register8_t reserved_0x32; - register8_t reserved_0x33; - register8_t reserved_0x34; - register8_t reserved_0x35; - register8_t reserved_0x36; - register8_t reserved_0x37; - register8_t reserved_0x38; - register8_t reserved_0x39; - register8_t reserved_0x3A; - register8_t reserved_0x3B; - register8_t reserved_0x3C; - register8_t reserved_0x3D; - register8_t reserved_0x3E; - register8_t reserved_0x3F; -} NVM_PROD_SIGNATURES_t; - -/* -========================================================================== -IO Module Instances. Mapped to memory. -========================================================================== -*/ - -#define VPORT0 (*(VPORT_t *) 0x0010) /* Virtual Port */ -#define VPORT1 (*(VPORT_t *) 0x0014) /* Virtual Port */ -#define VPORT2 (*(VPORT_t *) 0x0018) /* Virtual Port */ -#define VPORT3 (*(VPORT_t *) 0x001C) /* Virtual Port */ -#define OCD (*(OCD_t *) 0x002E) /* On-Chip Debug System */ -#define CLK (*(CLK_t *) 0x0040) /* Clock System */ -#define SLEEP (*(SLEEP_t *) 0x0048) /* Sleep Controller */ -#define OSC (*(OSC_t *) 0x0050) /* Oscillator */ -#define DFLLRC32M (*(DFLL_t *) 0x0060) /* DFLL */ -#define DFLLRC2M (*(DFLL_t *) 0x0068) /* DFLL */ -#define PR (*(PR_t *) 0x0070) /* Power Reduction */ -#define RST (*(RST_t *) 0x0078) /* Reset */ -#define WDT (*(WDT_t *) 0x0080) /* Watch-Dog Timer */ -#define MCU (*(MCU_t *) 0x0090) /* MCU Control */ -#define PMIC (*(PMIC_t *) 0x00A0) /* Programmable Multi-level Interrupt Controller */ -#define PORTCFG (*(PORTCFG_t *) 0x00B0) /* I/O port Configuration */ -#define AES (*(AES_t *) 0x00C0) /* AES Module */ -#define CRC (*(CRC_t *) 0x00D0) /* Cyclic Redundancy Checker */ -#define DMA (*(DMA_t *) 0x0100) /* DMA Controller */ -#define EVSYS (*(EVSYS_t *) 0x0180) /* Event System */ -#define NVM (*(NVM_t *) 0x01C0) /* Non-volatile Memory Controller */ -#define ADCA (*(ADC_t *) 0x0200) /* Analog-to-Digital Converter */ -#define ACA (*(AC_t *) 0x0380) /* Analog Comparator */ -#define RTC (*(RTC_t *) 0x0400) /* Real-Time Counter */ -#define TWIC (*(TWI_t *) 0x0480) /* Two-Wire Interface */ -#define TWIE (*(TWI_t *) 0x04A0) /* Two-Wire Interface */ -#define USB (*(USB_t *) 0x04C0) /* Universal Serial Bus */ -#define PORTA (*(PORT_t *) 0x0600) /* I/O Ports */ -#define PORTB (*(PORT_t *) 0x0620) /* I/O Ports */ -#define PORTC (*(PORT_t *) 0x0640) /* I/O Ports */ -#define PORTD (*(PORT_t *) 0x0660) /* I/O Ports */ -#define PORTE (*(PORT_t *) 0x0680) /* I/O Ports */ -#define PORTF (*(PORT_t *) 0x06A0) /* I/O Ports */ -#define PORTR (*(PORT_t *) 0x07E0) /* I/O Ports */ -#define TCC0 (*(TC0_t *) 0x0800) /* 16-bit Timer/Counter 0 */ -#define TCC2 (*(TC2_t *) 0x0800) /* 16-bit Timer/Counter type 2 */ -#define TCC1 (*(TC1_t *) 0x0840) /* 16-bit Timer/Counter 1 */ -#define AWEXC (*(AWEX_t *) 0x0880) /* Advanced Waveform Extension */ -#define HIRESC (*(HIRES_t *) 0x0890) /* High-Resolution Extension */ -#define USARTC0 (*(USART_t *) 0x08A0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ -#define USARTC1 (*(USART_t *) 0x08B0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ -#define SPIC (*(SPI_t *) 0x08C0) /* Serial Peripheral Interface */ -#define IRCOM (*(IRCOM_t *) 0x08F8) /* IR Communication Module */ -#define TCD0 (*(TC0_t *) 0x0900) /* 16-bit Timer/Counter 0 */ -#define TCD2 (*(TC2_t *) 0x0900) /* 16-bit Timer/Counter type 2 */ -#define USARTD0 (*(USART_t *) 0x09A0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ -#define SPID (*(SPI_t *) 0x09C0) /* Serial Peripheral Interface */ -#define TCE0 (*(TC0_t *) 0x0A00) /* 16-bit Timer/Counter 0 */ -#define TCE2 (*(TC2_t *) 0x0A00) /* 16-bit Timer/Counter type 2 */ -#define USARTE0 (*(USART_t *) 0x0AA0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ -#define TCF0 (*(TC0_t *) 0x0B00) /* 16-bit Timer/Counter 0 */ -#define TCF2 (*(TC2_t *) 0x0B00) /* 16-bit Timer/Counter type 2 */ -#define USARTF0 (*(USART_t *) 0x0BA0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ - - -#endif /* !defined (__ASSEMBLER__) */ - - -/* ========== Flattened fully qualified IO register names ========== */ - -/* GPIO - General Purpose IO Registers */ -#define GPIO_GPIOR0 _SFR_MEM8(0x0000) -#define GPIO_GPIOR1 _SFR_MEM8(0x0001) -#define GPIO_GPIOR2 _SFR_MEM8(0x0002) -#define GPIO_GPIOR3 _SFR_MEM8(0x0003) - -/* Deprecated */ -#define GPIO_GPIO0 _SFR_MEM8(0x0000) -#define GPIO_GPIO1 _SFR_MEM8(0x0001) -#define GPIO_GPIO2 _SFR_MEM8(0x0002) -#define GPIO_GPIO3 _SFR_MEM8(0x0003) - -/* NVM_FUSES - Fuses */ -#define FUSE_FUSEBYTE1 _SFR_MEM8(0x0001) -#define FUSE_FUSEBYTE2 _SFR_MEM8(0x0002) -#define FUSE_FUSEBYTE4 _SFR_MEM8(0x0004) -#define FUSE_FUSEBYTE5 _SFR_MEM8(0x0005) - -/* NVM_LOCKBITS - Lock Bits */ -#define LOCKBIT_LOCKBITS _SFR_MEM8(0x0000) - -/* NVM_PROD_SIGNATURES - Production Signatures */ -#define PRODSIGNATURES_RCOSC2M _SFR_MEM8(0x0000) -#define PRODSIGNATURES_RCOSC2MA _SFR_MEM8(0x0001) -#define PRODSIGNATURES_RCOSC32K _SFR_MEM8(0x0002) -#define PRODSIGNATURES_RCOSC32M _SFR_MEM8(0x0003) -#define PRODSIGNATURES_RCOSC32MA _SFR_MEM8(0x0004) -#define PRODSIGNATURES_LOTNUM0 _SFR_MEM8(0x0008) -#define PRODSIGNATURES_LOTNUM1 _SFR_MEM8(0x0009) -#define PRODSIGNATURES_LOTNUM2 _SFR_MEM8(0x000A) -#define PRODSIGNATURES_LOTNUM3 _SFR_MEM8(0x000B) -#define PRODSIGNATURES_LOTNUM4 _SFR_MEM8(0x000C) -#define PRODSIGNATURES_LOTNUM5 _SFR_MEM8(0x000D) -#define PRODSIGNATURES_WAFNUM _SFR_MEM8(0x0010) -#define PRODSIGNATURES_COORDX0 _SFR_MEM8(0x0012) -#define PRODSIGNATURES_COORDX1 _SFR_MEM8(0x0013) -#define PRODSIGNATURES_COORDY0 _SFR_MEM8(0x0014) -#define PRODSIGNATURES_COORDY1 _SFR_MEM8(0x0015) -#define PRODSIGNATURES_USBCAL0 _SFR_MEM8(0x001A) -#define PRODSIGNATURES_USBCAL1 _SFR_MEM8(0x001B) -#define PRODSIGNATURES_USBRCOSC _SFR_MEM8(0x001C) -#define PRODSIGNATURES_USBRCOSCA _SFR_MEM8(0x001D) -#define PRODSIGNATURES_ADCACAL0 _SFR_MEM8(0x0020) -#define PRODSIGNATURES_ADCACAL1 _SFR_MEM8(0x0021) -#define PRODSIGNATURES_TEMPSENSE0 _SFR_MEM8(0x002E) -#define PRODSIGNATURES_TEMPSENSE1 _SFR_MEM8(0x002F) - -/* VPORT - Virtual Port */ -#define VPORT0_DIR _SFR_MEM8(0x0010) -#define VPORT0_OUT _SFR_MEM8(0x0011) -#define VPORT0_IN _SFR_MEM8(0x0012) -#define VPORT0_INTFLAGS _SFR_MEM8(0x0013) - -/* VPORT - Virtual Port */ -#define VPORT1_DIR _SFR_MEM8(0x0014) -#define VPORT1_OUT _SFR_MEM8(0x0015) -#define VPORT1_IN _SFR_MEM8(0x0016) -#define VPORT1_INTFLAGS _SFR_MEM8(0x0017) - -/* VPORT - Virtual Port */ -#define VPORT2_DIR _SFR_MEM8(0x0018) -#define VPORT2_OUT _SFR_MEM8(0x0019) -#define VPORT2_IN _SFR_MEM8(0x001A) -#define VPORT2_INTFLAGS _SFR_MEM8(0x001B) - -/* VPORT - Virtual Port */ -#define VPORT3_DIR _SFR_MEM8(0x001C) -#define VPORT3_OUT _SFR_MEM8(0x001D) -#define VPORT3_IN _SFR_MEM8(0x001E) -#define VPORT3_INTFLAGS _SFR_MEM8(0x001F) - -/* OCD - On-Chip Debug System */ -#define OCD_OCDR0 _SFR_MEM8(0x002E) -#define OCD_OCDR1 _SFR_MEM8(0x002F) - -/* CPU - CPU registers */ -#define CPU_CCP _SFR_MEM8(0x0034) -#define CPU_RAMPD _SFR_MEM8(0x0038) -#define CPU_RAMPX _SFR_MEM8(0x0039) -#define CPU_RAMPY _SFR_MEM8(0x003A) -#define CPU_RAMPZ _SFR_MEM8(0x003B) -#define CPU_EIND _SFR_MEM8(0x003C) -#define CPU_SPL _SFR_MEM8(0x003D) -#define CPU_SPH _SFR_MEM8(0x003E) -#define CPU_SREG _SFR_MEM8(0x003F) - -/* CLK - Clock System */ -#define CLK_CTRL _SFR_MEM8(0x0040) -#define CLK_PSCTRL _SFR_MEM8(0x0041) -#define CLK_LOCK _SFR_MEM8(0x0042) -#define CLK_RTCCTRL _SFR_MEM8(0x0043) -#define CLK_USBCTRL _SFR_MEM8(0x0044) - -/* SLEEP - Sleep Controller */ -#define SLEEP_CTRL _SFR_MEM8(0x0048) - -/* OSC - Oscillator */ -#define OSC_CTRL _SFR_MEM8(0x0050) -#define OSC_STATUS _SFR_MEM8(0x0051) -#define OSC_XOSCCTRL _SFR_MEM8(0x0052) -#define OSC_XOSCFAIL _SFR_MEM8(0x0053) -#define OSC_RC32KCAL _SFR_MEM8(0x0054) -#define OSC_PLLCTRL _SFR_MEM8(0x0055) -#define OSC_DFLLCTRL _SFR_MEM8(0x0056) - -/* DFLL - DFLL */ -#define DFLLRC32M_CTRL _SFR_MEM8(0x0060) -#define DFLLRC32M_CALA _SFR_MEM8(0x0062) -#define DFLLRC32M_CALB _SFR_MEM8(0x0063) -#define DFLLRC32M_COMP0 _SFR_MEM8(0x0064) -#define DFLLRC32M_COMP1 _SFR_MEM8(0x0065) -#define DFLLRC32M_COMP2 _SFR_MEM8(0x0066) - -/* DFLL - DFLL */ -#define DFLLRC2M_CTRL _SFR_MEM8(0x0068) -#define DFLLRC2M_CALA _SFR_MEM8(0x006A) -#define DFLLRC2M_CALB _SFR_MEM8(0x006B) -#define DFLLRC2M_COMP0 _SFR_MEM8(0x006C) -#define DFLLRC2M_COMP1 _SFR_MEM8(0x006D) -#define DFLLRC2M_COMP2 _SFR_MEM8(0x006E) - -/* PR - Power Reduction */ -#define PR_PRGEN _SFR_MEM8(0x0070) -#define PR_PRPA _SFR_MEM8(0x0071) -#define PR_PRPB _SFR_MEM8(0x0072) -#define PR_PRPC _SFR_MEM8(0x0073) -#define PR_PRPD _SFR_MEM8(0x0074) -#define PR_PRPE _SFR_MEM8(0x0075) -#define PR_PRPF _SFR_MEM8(0x0076) - -/* RST - Reset */ -#define RST_STATUS _SFR_MEM8(0x0078) -#define RST_CTRL _SFR_MEM8(0x0079) - -/* WDT - Watch-Dog Timer */ -#define WDT_CTRL _SFR_MEM8(0x0080) -#define WDT_WINCTRL _SFR_MEM8(0x0081) -#define WDT_STATUS _SFR_MEM8(0x0082) - -/* MCU - MCU Control */ -#define MCU_DEVID0 _SFR_MEM8(0x0090) -#define MCU_DEVID1 _SFR_MEM8(0x0091) -#define MCU_DEVID2 _SFR_MEM8(0x0092) -#define MCU_REVID _SFR_MEM8(0x0093) -#define MCU_ANAINIT _SFR_MEM8(0x0097) -#define MCU_EVSYSLOCK _SFR_MEM8(0x0098) -#define MCU_AWEXLOCK _SFR_MEM8(0x0099) - -/* PMIC - Programmable Multi-level Interrupt Controller */ -#define PMIC_STATUS _SFR_MEM8(0x00A0) -#define PMIC_INTPRI _SFR_MEM8(0x00A1) -#define PMIC_CTRL _SFR_MEM8(0x00A2) - -/* PORTCFG - I/O port Configuration */ -#define PORTCFG_MPCMASK _SFR_MEM8(0x00B0) -#define PORTCFG_VPCTRLA _SFR_MEM8(0x00B2) -#define PORTCFG_VPCTRLB _SFR_MEM8(0x00B3) -#define PORTCFG_CLKEVOUT _SFR_MEM8(0x00B4) -#define PORTCFG_EBIOUT _SFR_MEM8(0x00B5) -#define PORTCFG_EVOUTSEL _SFR_MEM8(0x00B6) - -/* AES - AES Module */ -#define AES_CTRL _SFR_MEM8(0x00C0) -#define AES_STATUS _SFR_MEM8(0x00C1) -#define AES_STATE _SFR_MEM8(0x00C2) -#define AES_KEY _SFR_MEM8(0x00C3) -#define AES_INTCTRL _SFR_MEM8(0x00C4) - -/* CRC - Cyclic Redundancy Checker */ -#define CRC_CTRL _SFR_MEM8(0x00D0) -#define CRC_STATUS _SFR_MEM8(0x00D1) -#define CRC_DATAIN _SFR_MEM8(0x00D3) -#define CRC_CHECKSUM0 _SFR_MEM8(0x00D4) -#define CRC_CHECKSUM1 _SFR_MEM8(0x00D5) -#define CRC_CHECKSUM2 _SFR_MEM8(0x00D6) -#define CRC_CHECKSUM3 _SFR_MEM8(0x00D7) - -/* DMA - DMA Controller */ -#define DMA_CTRL _SFR_MEM8(0x0100) -#define DMA_INTFLAGS _SFR_MEM8(0x0103) -#define DMA_STATUS _SFR_MEM8(0x0104) -#define DMA_TEMP _SFR_MEM16(0x0106) -#define DMA_CH0_CTRLA _SFR_MEM8(0x0110) -#define DMA_CH0_CTRLB _SFR_MEM8(0x0111) -#define DMA_CH0_ADDRCTRL _SFR_MEM8(0x0112) -#define DMA_CH0_TRIGSRC _SFR_MEM8(0x0113) -#define DMA_CH0_TRFCNT _SFR_MEM16(0x0114) -#define DMA_CH0_REPCNT _SFR_MEM8(0x0116) -#define DMA_CH0_SRCADDR0 _SFR_MEM8(0x0118) -#define DMA_CH0_SRCADDR1 _SFR_MEM8(0x0119) -#define DMA_CH0_DESTADDR0 _SFR_MEM8(0x011C) -#define DMA_CH0_DESTADDR1 _SFR_MEM8(0x011D) -#define DMA_CH1_CTRLA _SFR_MEM8(0x0120) -#define DMA_CH1_CTRLB _SFR_MEM8(0x0121) -#define DMA_CH1_ADDRCTRL _SFR_MEM8(0x0122) -#define DMA_CH1_TRIGSRC _SFR_MEM8(0x0123) -#define DMA_CH1_TRFCNT _SFR_MEM16(0x0124) -#define DMA_CH1_REPCNT _SFR_MEM8(0x0126) -#define DMA_CH1_SRCADDR0 _SFR_MEM8(0x0128) -#define DMA_CH1_SRCADDR1 _SFR_MEM8(0x0129) -#define DMA_CH1_DESTADDR0 _SFR_MEM8(0x012C) -#define DMA_CH1_DESTADDR1 _SFR_MEM8(0x012D) - -/* EVSYS - Event System */ -#define EVSYS_CH0MUX _SFR_MEM8(0x0180) -#define EVSYS_CH1MUX _SFR_MEM8(0x0181) -#define EVSYS_CH2MUX _SFR_MEM8(0x0182) -#define EVSYS_CH3MUX _SFR_MEM8(0x0183) -#define EVSYS_CH0CTRL _SFR_MEM8(0x0188) -#define EVSYS_CH1CTRL _SFR_MEM8(0x0189) -#define EVSYS_CH2CTRL _SFR_MEM8(0x018A) -#define EVSYS_CH3CTRL _SFR_MEM8(0x018B) -#define EVSYS_STROBE _SFR_MEM8(0x0190) -#define EVSYS_DATA _SFR_MEM8(0x0191) - -/* NVM - Non-volatile Memory Controller */ -#define NVM_ADDR0 _SFR_MEM8(0x01C0) -#define NVM_ADDR1 _SFR_MEM8(0x01C1) -#define NVM_ADDR2 _SFR_MEM8(0x01C2) -#define NVM_DATA0 _SFR_MEM8(0x01C4) -#define NVM_DATA1 _SFR_MEM8(0x01C5) -#define NVM_DATA2 _SFR_MEM8(0x01C6) -#define NVM_CMD _SFR_MEM8(0x01CA) -#define NVM_CTRLA _SFR_MEM8(0x01CB) -#define NVM_CTRLB _SFR_MEM8(0x01CC) -#define NVM_INTCTRL _SFR_MEM8(0x01CD) -#define NVM_STATUS _SFR_MEM8(0x01CF) -#define NVM_LOCKBITS _SFR_MEM8(0x01D0) - -/* ADC - Analog-to-Digital Converter */ -#define ADCA_CTRLA _SFR_MEM8(0x0200) -#define ADCA_CTRLB _SFR_MEM8(0x0201) -#define ADCA_REFCTRL _SFR_MEM8(0x0202) -#define ADCA_EVCTRL _SFR_MEM8(0x0203) -#define ADCA_PRESCALER _SFR_MEM8(0x0204) -#define ADCA_INTFLAGS _SFR_MEM8(0x0206) -#define ADCA_TEMP _SFR_MEM8(0x0207) -#define ADCA_SAMPCTRL _SFR_MEM8(0x0208) -#define ADCA_CAL _SFR_MEM16(0x020C) -#define ADCA_CH0RES _SFR_MEM16(0x0210) -#define ADCA_CMP _SFR_MEM16(0x0218) -#define ADCA_CH0_CTRL _SFR_MEM8(0x0220) -#define ADCA_CH0_MUXCTRL _SFR_MEM8(0x0221) -#define ADCA_CH0_INTCTRL _SFR_MEM8(0x0222) -#define ADCA_CH0_INTFLAGS _SFR_MEM8(0x0223) -#define ADCA_CH0_RES _SFR_MEM16(0x0224) -#define ADCA_CH0_SCAN _SFR_MEM8(0x0226) - -/* AC - Analog Comparator */ -#define ACA_AC0CTRL _SFR_MEM8(0x0380) -#define ACA_AC1CTRL _SFR_MEM8(0x0381) -#define ACA_AC0MUXCTRL _SFR_MEM8(0x0382) -#define ACA_AC1MUXCTRL _SFR_MEM8(0x0383) -#define ACA_CTRLA _SFR_MEM8(0x0384) -#define ACA_CTRLB _SFR_MEM8(0x0385) -#define ACA_WINCTRL _SFR_MEM8(0x0386) -#define ACA_STATUS _SFR_MEM8(0x0387) - -/* RTC - Real-Time Counter */ -#define RTC_CTRL _SFR_MEM8(0x0400) -#define RTC_STATUS _SFR_MEM8(0x0401) -#define RTC_INTCTRL _SFR_MEM8(0x0402) -#define RTC_INTFLAGS _SFR_MEM8(0x0403) -#define RTC_TEMP _SFR_MEM8(0x0404) -#define RTC_CNT _SFR_MEM16(0x0408) -#define RTC_PER _SFR_MEM16(0x040A) -#define RTC_COMP _SFR_MEM16(0x040C) - -/* TWI - Two-Wire Interface */ -#define TWIC_CTRL _SFR_MEM8(0x0480) -#define TWIC_MASTER_CTRLA _SFR_MEM8(0x0481) -#define TWIC_MASTER_CTRLB _SFR_MEM8(0x0482) -#define TWIC_MASTER_CTRLC _SFR_MEM8(0x0483) -#define TWIC_MASTER_STATUS _SFR_MEM8(0x0484) -#define TWIC_MASTER_BAUD _SFR_MEM8(0x0485) -#define TWIC_MASTER_ADDR _SFR_MEM8(0x0486) -#define TWIC_MASTER_DATA _SFR_MEM8(0x0487) -#define TWIC_SLAVE_CTRLA _SFR_MEM8(0x0488) -#define TWIC_SLAVE_CTRLB _SFR_MEM8(0x0489) -#define TWIC_SLAVE_STATUS _SFR_MEM8(0x048A) -#define TWIC_SLAVE_ADDR _SFR_MEM8(0x048B) -#define TWIC_SLAVE_DATA _SFR_MEM8(0x048C) -#define TWIC_SLAVE_ADDRMASK _SFR_MEM8(0x048D) - -/* TWI - Two-Wire Interface */ -#define TWIE_CTRL _SFR_MEM8(0x04A0) -#define TWIE_MASTER_CTRLA _SFR_MEM8(0x04A1) -#define TWIE_MASTER_CTRLB _SFR_MEM8(0x04A2) -#define TWIE_MASTER_CTRLC _SFR_MEM8(0x04A3) -#define TWIE_MASTER_STATUS _SFR_MEM8(0x04A4) -#define TWIE_MASTER_BAUD _SFR_MEM8(0x04A5) -#define TWIE_MASTER_ADDR _SFR_MEM8(0x04A6) -#define TWIE_MASTER_DATA _SFR_MEM8(0x04A7) -#define TWIE_SLAVE_CTRLA _SFR_MEM8(0x04A8) -#define TWIE_SLAVE_CTRLB _SFR_MEM8(0x04A9) -#define TWIE_SLAVE_STATUS _SFR_MEM8(0x04AA) -#define TWIE_SLAVE_ADDR _SFR_MEM8(0x04AB) -#define TWIE_SLAVE_DATA _SFR_MEM8(0x04AC) -#define TWIE_SLAVE_ADDRMASK _SFR_MEM8(0x04AD) - -/* USB - Universal Serial Bus */ -#define USB_CTRLA _SFR_MEM8(0x04C0) -#define USB_CTRLB _SFR_MEM8(0x04C1) -#define USB_STATUS _SFR_MEM8(0x04C2) -#define USB_ADDR _SFR_MEM8(0x04C3) -#define USB_FIFOWP _SFR_MEM8(0x04C4) -#define USB_FIFORP _SFR_MEM8(0x04C5) -#define USB_EPPTR _SFR_MEM16(0x04C6) -#define USB_INTCTRLA _SFR_MEM8(0x04C8) -#define USB_INTCTRLB _SFR_MEM8(0x04C9) -#define USB_INTFLAGSACLR _SFR_MEM8(0x04CA) -#define USB_INTFLAGSASET _SFR_MEM8(0x04CB) -#define USB_INTFLAGSBCLR _SFR_MEM8(0x04CC) -#define USB_INTFLAGSBSET _SFR_MEM8(0x04CD) -#define USB_CAL0 _SFR_MEM8(0x04FA) -#define USB_CAL1 _SFR_MEM8(0x04FB) - -/* PORT - I/O Ports */ -#define PORTA_DIR _SFR_MEM8(0x0600) -#define PORTA_DIRSET _SFR_MEM8(0x0601) -#define PORTA_DIRCLR _SFR_MEM8(0x0602) -#define PORTA_DIRTGL _SFR_MEM8(0x0603) -#define PORTA_OUT _SFR_MEM8(0x0604) -#define PORTA_OUTSET _SFR_MEM8(0x0605) -#define PORTA_OUTCLR _SFR_MEM8(0x0606) -#define PORTA_OUTTGL _SFR_MEM8(0x0607) -#define PORTA_IN _SFR_MEM8(0x0608) -#define PORTA_INTCTRL _SFR_MEM8(0x0609) -#define PORTA_INT0MASK _SFR_MEM8(0x060A) -#define PORTA_INT1MASK _SFR_MEM8(0x060B) -#define PORTA_INTFLAGS _SFR_MEM8(0x060C) -#define PORTA_REMAP _SFR_MEM8(0x060E) -#define PORTA_PIN0CTRL _SFR_MEM8(0x0610) -#define PORTA_PIN1CTRL _SFR_MEM8(0x0611) -#define PORTA_PIN2CTRL _SFR_MEM8(0x0612) -#define PORTA_PIN3CTRL _SFR_MEM8(0x0613) -#define PORTA_PIN4CTRL _SFR_MEM8(0x0614) -#define PORTA_PIN5CTRL _SFR_MEM8(0x0615) -#define PORTA_PIN6CTRL _SFR_MEM8(0x0616) -#define PORTA_PIN7CTRL _SFR_MEM8(0x0617) - -/* PORT - I/O Ports */ -#define PORTB_DIR _SFR_MEM8(0x0620) -#define PORTB_DIRSET _SFR_MEM8(0x0621) -#define PORTB_DIRCLR _SFR_MEM8(0x0622) -#define PORTB_DIRTGL _SFR_MEM8(0x0623) -#define PORTB_OUT _SFR_MEM8(0x0624) -#define PORTB_OUTSET _SFR_MEM8(0x0625) -#define PORTB_OUTCLR _SFR_MEM8(0x0626) -#define PORTB_OUTTGL _SFR_MEM8(0x0627) -#define PORTB_IN _SFR_MEM8(0x0628) -#define PORTB_INTCTRL _SFR_MEM8(0x0629) -#define PORTB_INT0MASK _SFR_MEM8(0x062A) -#define PORTB_INT1MASK _SFR_MEM8(0x062B) -#define PORTB_INTFLAGS _SFR_MEM8(0x062C) -#define PORTB_REMAP _SFR_MEM8(0x062E) -#define PORTB_PIN0CTRL _SFR_MEM8(0x0630) -#define PORTB_PIN1CTRL _SFR_MEM8(0x0631) -#define PORTB_PIN2CTRL _SFR_MEM8(0x0632) -#define PORTB_PIN3CTRL _SFR_MEM8(0x0633) -#define PORTB_PIN4CTRL _SFR_MEM8(0x0634) -#define PORTB_PIN5CTRL _SFR_MEM8(0x0635) -#define PORTB_PIN6CTRL _SFR_MEM8(0x0636) -#define PORTB_PIN7CTRL _SFR_MEM8(0x0637) - -/* PORT - I/O Ports */ -#define PORTC_DIR _SFR_MEM8(0x0640) -#define PORTC_DIRSET _SFR_MEM8(0x0641) -#define PORTC_DIRCLR _SFR_MEM8(0x0642) -#define PORTC_DIRTGL _SFR_MEM8(0x0643) -#define PORTC_OUT _SFR_MEM8(0x0644) -#define PORTC_OUTSET _SFR_MEM8(0x0645) -#define PORTC_OUTCLR _SFR_MEM8(0x0646) -#define PORTC_OUTTGL _SFR_MEM8(0x0647) -#define PORTC_IN _SFR_MEM8(0x0648) -#define PORTC_INTCTRL _SFR_MEM8(0x0649) -#define PORTC_INT0MASK _SFR_MEM8(0x064A) -#define PORTC_INT1MASK _SFR_MEM8(0x064B) -#define PORTC_INTFLAGS _SFR_MEM8(0x064C) -#define PORTC_REMAP _SFR_MEM8(0x064E) -#define PORTC_PIN0CTRL _SFR_MEM8(0x0650) -#define PORTC_PIN1CTRL _SFR_MEM8(0x0651) -#define PORTC_PIN2CTRL _SFR_MEM8(0x0652) -#define PORTC_PIN3CTRL _SFR_MEM8(0x0653) -#define PORTC_PIN4CTRL _SFR_MEM8(0x0654) -#define PORTC_PIN5CTRL _SFR_MEM8(0x0655) -#define PORTC_PIN6CTRL _SFR_MEM8(0x0656) -#define PORTC_PIN7CTRL _SFR_MEM8(0x0657) - -/* PORT - I/O Ports */ -#define PORTD_DIR _SFR_MEM8(0x0660) -#define PORTD_DIRSET _SFR_MEM8(0x0661) -#define PORTD_DIRCLR _SFR_MEM8(0x0662) -#define PORTD_DIRTGL _SFR_MEM8(0x0663) -#define PORTD_OUT _SFR_MEM8(0x0664) -#define PORTD_OUTSET _SFR_MEM8(0x0665) -#define PORTD_OUTCLR _SFR_MEM8(0x0666) -#define PORTD_OUTTGL _SFR_MEM8(0x0667) -#define PORTD_IN _SFR_MEM8(0x0668) -#define PORTD_INTCTRL _SFR_MEM8(0x0669) -#define PORTD_INT0MASK _SFR_MEM8(0x066A) -#define PORTD_INT1MASK _SFR_MEM8(0x066B) -#define PORTD_INTFLAGS _SFR_MEM8(0x066C) -#define PORTD_REMAP _SFR_MEM8(0x066E) -#define PORTD_PIN0CTRL _SFR_MEM8(0x0670) -#define PORTD_PIN1CTRL _SFR_MEM8(0x0671) -#define PORTD_PIN2CTRL _SFR_MEM8(0x0672) -#define PORTD_PIN3CTRL _SFR_MEM8(0x0673) -#define PORTD_PIN4CTRL _SFR_MEM8(0x0674) -#define PORTD_PIN5CTRL _SFR_MEM8(0x0675) -#define PORTD_PIN6CTRL _SFR_MEM8(0x0676) -#define PORTD_PIN7CTRL _SFR_MEM8(0x0677) - -/* PORT - I/O Ports */ -#define PORTE_DIR _SFR_MEM8(0x0680) -#define PORTE_DIRSET _SFR_MEM8(0x0681) -#define PORTE_DIRCLR _SFR_MEM8(0x0682) -#define PORTE_DIRTGL _SFR_MEM8(0x0683) -#define PORTE_OUT _SFR_MEM8(0x0684) -#define PORTE_OUTSET _SFR_MEM8(0x0685) -#define PORTE_OUTCLR _SFR_MEM8(0x0686) -#define PORTE_OUTTGL _SFR_MEM8(0x0687) -#define PORTE_IN _SFR_MEM8(0x0688) -#define PORTE_INTCTRL _SFR_MEM8(0x0689) -#define PORTE_INT0MASK _SFR_MEM8(0x068A) -#define PORTE_INT1MASK _SFR_MEM8(0x068B) -#define PORTE_INTFLAGS _SFR_MEM8(0x068C) -#define PORTE_REMAP _SFR_MEM8(0x068E) -#define PORTE_PIN0CTRL _SFR_MEM8(0x0690) -#define PORTE_PIN1CTRL _SFR_MEM8(0x0691) -#define PORTE_PIN2CTRL _SFR_MEM8(0x0692) -#define PORTE_PIN3CTRL _SFR_MEM8(0x0693) -#define PORTE_PIN4CTRL _SFR_MEM8(0x0694) -#define PORTE_PIN5CTRL _SFR_MEM8(0x0695) -#define PORTE_PIN6CTRL _SFR_MEM8(0x0696) -#define PORTE_PIN7CTRL _SFR_MEM8(0x0697) - -/* PORT - I/O Ports */ -#define PORTF_DIR _SFR_MEM8(0x06A0) -#define PORTF_DIRSET _SFR_MEM8(0x06A1) -#define PORTF_DIRCLR _SFR_MEM8(0x06A2) -#define PORTF_DIRTGL _SFR_MEM8(0x06A3) -#define PORTF_OUT _SFR_MEM8(0x06A4) -#define PORTF_OUTSET _SFR_MEM8(0x06A5) -#define PORTF_OUTCLR _SFR_MEM8(0x06A6) -#define PORTF_OUTTGL _SFR_MEM8(0x06A7) -#define PORTF_IN _SFR_MEM8(0x06A8) -#define PORTF_INTCTRL _SFR_MEM8(0x06A9) -#define PORTF_INT0MASK _SFR_MEM8(0x06AA) -#define PORTF_INT1MASK _SFR_MEM8(0x06AB) -#define PORTF_INTFLAGS _SFR_MEM8(0x06AC) -#define PORTF_REMAP _SFR_MEM8(0x06AE) -#define PORTF_PIN0CTRL _SFR_MEM8(0x06B0) -#define PORTF_PIN1CTRL _SFR_MEM8(0x06B1) -#define PORTF_PIN2CTRL _SFR_MEM8(0x06B2) -#define PORTF_PIN3CTRL _SFR_MEM8(0x06B3) -#define PORTF_PIN4CTRL _SFR_MEM8(0x06B4) -#define PORTF_PIN5CTRL _SFR_MEM8(0x06B5) -#define PORTF_PIN6CTRL _SFR_MEM8(0x06B6) -#define PORTF_PIN7CTRL _SFR_MEM8(0x06B7) - -/* PORT - I/O Ports */ -#define PORTR_DIR _SFR_MEM8(0x07E0) -#define PORTR_DIRSET _SFR_MEM8(0x07E1) -#define PORTR_DIRCLR _SFR_MEM8(0x07E2) -#define PORTR_DIRTGL _SFR_MEM8(0x07E3) -#define PORTR_OUT _SFR_MEM8(0x07E4) -#define PORTR_OUTSET _SFR_MEM8(0x07E5) -#define PORTR_OUTCLR _SFR_MEM8(0x07E6) -#define PORTR_OUTTGL _SFR_MEM8(0x07E7) -#define PORTR_IN _SFR_MEM8(0x07E8) -#define PORTR_INTCTRL _SFR_MEM8(0x07E9) -#define PORTR_INT0MASK _SFR_MEM8(0x07EA) -#define PORTR_INT1MASK _SFR_MEM8(0x07EB) -#define PORTR_INTFLAGS _SFR_MEM8(0x07EC) -#define PORTR_REMAP _SFR_MEM8(0x07EE) -#define PORTR_PIN0CTRL _SFR_MEM8(0x07F0) -#define PORTR_PIN1CTRL _SFR_MEM8(0x07F1) -#define PORTR_PIN2CTRL _SFR_MEM8(0x07F2) -#define PORTR_PIN3CTRL _SFR_MEM8(0x07F3) -#define PORTR_PIN4CTRL _SFR_MEM8(0x07F4) -#define PORTR_PIN5CTRL _SFR_MEM8(0x07F5) -#define PORTR_PIN6CTRL _SFR_MEM8(0x07F6) -#define PORTR_PIN7CTRL _SFR_MEM8(0x07F7) - -/* TC0 - 16-bit Timer/Counter 0 */ -#define TCC0_CTRLA _SFR_MEM8(0x0800) -#define TCC0_CTRLB _SFR_MEM8(0x0801) -#define TCC0_CTRLC _SFR_MEM8(0x0802) -#define TCC0_CTRLD _SFR_MEM8(0x0803) -#define TCC0_CTRLE _SFR_MEM8(0x0804) -#define TCC0_INTCTRLA _SFR_MEM8(0x0806) -#define TCC0_INTCTRLB _SFR_MEM8(0x0807) -#define TCC0_CTRLFCLR _SFR_MEM8(0x0808) -#define TCC0_CTRLFSET _SFR_MEM8(0x0809) -#define TCC0_CTRLGCLR _SFR_MEM8(0x080A) -#define TCC0_CTRLGSET _SFR_MEM8(0x080B) -#define TCC0_INTFLAGS _SFR_MEM8(0x080C) -#define TCC0_TEMP _SFR_MEM8(0x080F) -#define TCC0_CNT _SFR_MEM16(0x0820) -#define TCC0_PER _SFR_MEM16(0x0826) -#define TCC0_CCA _SFR_MEM16(0x0828) -#define TCC0_CCB _SFR_MEM16(0x082A) -#define TCC0_CCC _SFR_MEM16(0x082C) -#define TCC0_CCD _SFR_MEM16(0x082E) -#define TCC0_PERBUF _SFR_MEM16(0x0836) -#define TCC0_CCABUF _SFR_MEM16(0x0838) -#define TCC0_CCBBUF _SFR_MEM16(0x083A) -#define TCC0_CCCBUF _SFR_MEM16(0x083C) -#define TCC0_CCDBUF _SFR_MEM16(0x083E) - -/* TC2 - 16-bit Timer/Counter type 2 */ -#define TCC2_CTRLA _SFR_MEM8(0x0800) -#define TCC2_CTRLB _SFR_MEM8(0x0801) -#define TCC2_CTRLC _SFR_MEM8(0x0802) -#define TCC2_CTRLE _SFR_MEM8(0x0804) -#define TCC2_INTCTRLA _SFR_MEM8(0x0806) -#define TCC2_INTCTRLB _SFR_MEM8(0x0807) -#define TCC2_CTRLF _SFR_MEM8(0x0809) -#define TCC2_INTFLAGS _SFR_MEM8(0x080C) -#define TCC2_LCNT _SFR_MEM8(0x0820) -#define TCC2_HCNT _SFR_MEM8(0x0821) -#define TCC2_LPER _SFR_MEM8(0x0826) -#define TCC2_HPER _SFR_MEM8(0x0827) -#define TCC2_LCMPA _SFR_MEM8(0x0828) -#define TCC2_HCMPA _SFR_MEM8(0x0829) -#define TCC2_LCMPB _SFR_MEM8(0x082A) -#define TCC2_HCMPB _SFR_MEM8(0x082B) -#define TCC2_LCMPC _SFR_MEM8(0x082C) -#define TCC2_HCMPC _SFR_MEM8(0x082D) -#define TCC2_LCMPD _SFR_MEM8(0x082E) -#define TCC2_HCMPD _SFR_MEM8(0x082F) - -/* TC1 - 16-bit Timer/Counter 1 */ -#define TCC1_CTRLA _SFR_MEM8(0x0840) -#define TCC1_CTRLB _SFR_MEM8(0x0841) -#define TCC1_CTRLC _SFR_MEM8(0x0842) -#define TCC1_CTRLD _SFR_MEM8(0x0843) -#define TCC1_CTRLE _SFR_MEM8(0x0844) -#define TCC1_INTCTRLA _SFR_MEM8(0x0846) -#define TCC1_INTCTRLB _SFR_MEM8(0x0847) -#define TCC1_CTRLFCLR _SFR_MEM8(0x0848) -#define TCC1_CTRLFSET _SFR_MEM8(0x0849) -#define TCC1_CTRLGCLR _SFR_MEM8(0x084A) -#define TCC1_CTRLGSET _SFR_MEM8(0x084B) -#define TCC1_INTFLAGS _SFR_MEM8(0x084C) -#define TCC1_TEMP _SFR_MEM8(0x084F) -#define TCC1_CNT _SFR_MEM16(0x0860) -#define TCC1_PER _SFR_MEM16(0x0866) -#define TCC1_CCA _SFR_MEM16(0x0868) -#define TCC1_CCB _SFR_MEM16(0x086A) -#define TCC1_PERBUF _SFR_MEM16(0x0876) -#define TCC1_CCABUF _SFR_MEM16(0x0878) -#define TCC1_CCBBUF _SFR_MEM16(0x087A) - -/* AWEX - Advanced Waveform Extension */ -#define AWEXC_CTRL _SFR_MEM8(0x0880) -#define AWEXC_FDEMASK _SFR_MEM8(0x0882) -#define AWEXC_FDCTRL _SFR_MEM8(0x0883) -#define AWEXC_STATUS _SFR_MEM8(0x0884) -#define AWEXC_STATUSSET _SFR_MEM8(0x0885) -#define AWEXC_DTBOTH _SFR_MEM8(0x0886) -#define AWEXC_DTBOTHBUF _SFR_MEM8(0x0887) -#define AWEXC_DTLS _SFR_MEM8(0x0888) -#define AWEXC_DTHS _SFR_MEM8(0x0889) -#define AWEXC_DTLSBUF _SFR_MEM8(0x088A) -#define AWEXC_DTHSBUF _SFR_MEM8(0x088B) -#define AWEXC_OUTOVEN _SFR_MEM8(0x088C) - -/* HIRES - High-Resolution Extension */ -#define HIRESC_CTRLA _SFR_MEM8(0x0890) - -/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ -#define USARTC0_DATA _SFR_MEM8(0x08A0) -#define USARTC0_STATUS _SFR_MEM8(0x08A1) -#define USARTC0_CTRLA _SFR_MEM8(0x08A3) -#define USARTC0_CTRLB _SFR_MEM8(0x08A4) -#define USARTC0_CTRLC _SFR_MEM8(0x08A5) -#define USARTC0_BAUDCTRLA _SFR_MEM8(0x08A6) -#define USARTC0_BAUDCTRLB _SFR_MEM8(0x08A7) - -/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ -#define USARTC1_DATA _SFR_MEM8(0x08B0) -#define USARTC1_STATUS _SFR_MEM8(0x08B1) -#define USARTC1_CTRLA _SFR_MEM8(0x08B3) -#define USARTC1_CTRLB _SFR_MEM8(0x08B4) -#define USARTC1_CTRLC _SFR_MEM8(0x08B5) -#define USARTC1_BAUDCTRLA _SFR_MEM8(0x08B6) -#define USARTC1_BAUDCTRLB _SFR_MEM8(0x08B7) - -/* SPI - Serial Peripheral Interface */ -#define SPIC_CTRL _SFR_MEM8(0x08C0) -#define SPIC_INTCTRL _SFR_MEM8(0x08C1) -#define SPIC_STATUS _SFR_MEM8(0x08C2) -#define SPIC_DATA _SFR_MEM8(0x08C3) - -/* IRCOM - IR Communication Module */ -#define IRCOM_CTRL _SFR_MEM8(0x08F8) -#define IRCOM_TXPLCTRL _SFR_MEM8(0x08F9) -#define IRCOM_RXPLCTRL _SFR_MEM8(0x08FA) - -/* TC0 - 16-bit Timer/Counter 0 */ -#define TCD0_CTRLA _SFR_MEM8(0x0900) -#define TCD0_CTRLB _SFR_MEM8(0x0901) -#define TCD0_CTRLC _SFR_MEM8(0x0902) -#define TCD0_CTRLD _SFR_MEM8(0x0903) -#define TCD0_CTRLE _SFR_MEM8(0x0904) -#define TCD0_INTCTRLA _SFR_MEM8(0x0906) -#define TCD0_INTCTRLB _SFR_MEM8(0x0907) -#define TCD0_CTRLFCLR _SFR_MEM8(0x0908) -#define TCD0_CTRLFSET _SFR_MEM8(0x0909) -#define TCD0_CTRLGCLR _SFR_MEM8(0x090A) -#define TCD0_CTRLGSET _SFR_MEM8(0x090B) -#define TCD0_INTFLAGS _SFR_MEM8(0x090C) -#define TCD0_TEMP _SFR_MEM8(0x090F) -#define TCD0_CNT _SFR_MEM16(0x0920) -#define TCD0_PER _SFR_MEM16(0x0926) -#define TCD0_CCA _SFR_MEM16(0x0928) -#define TCD0_CCB _SFR_MEM16(0x092A) -#define TCD0_CCC _SFR_MEM16(0x092C) -#define TCD0_CCD _SFR_MEM16(0x092E) -#define TCD0_PERBUF _SFR_MEM16(0x0936) -#define TCD0_CCABUF _SFR_MEM16(0x0938) -#define TCD0_CCBBUF _SFR_MEM16(0x093A) -#define TCD0_CCCBUF _SFR_MEM16(0x093C) -#define TCD0_CCDBUF _SFR_MEM16(0x093E) - -/* TC2 - 16-bit Timer/Counter type 2 */ -#define TCD2_CTRLA _SFR_MEM8(0x0900) -#define TCD2_CTRLB _SFR_MEM8(0x0901) -#define TCD2_CTRLC _SFR_MEM8(0x0902) -#define TCD2_CTRLE _SFR_MEM8(0x0904) -#define TCD2_INTCTRLA _SFR_MEM8(0x0906) -#define TCD2_INTCTRLB _SFR_MEM8(0x0907) -#define TCD2_CTRLF _SFR_MEM8(0x0909) -#define TCD2_INTFLAGS _SFR_MEM8(0x090C) -#define TCD2_LCNT _SFR_MEM8(0x0920) -#define TCD2_HCNT _SFR_MEM8(0x0921) -#define TCD2_LPER _SFR_MEM8(0x0926) -#define TCD2_HPER _SFR_MEM8(0x0927) -#define TCD2_LCMPA _SFR_MEM8(0x0928) -#define TCD2_HCMPA _SFR_MEM8(0x0929) -#define TCD2_LCMPB _SFR_MEM8(0x092A) -#define TCD2_HCMPB _SFR_MEM8(0x092B) -#define TCD2_LCMPC _SFR_MEM8(0x092C) -#define TCD2_HCMPC _SFR_MEM8(0x092D) -#define TCD2_LCMPD _SFR_MEM8(0x092E) -#define TCD2_HCMPD _SFR_MEM8(0x092F) - -/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ -#define USARTD0_DATA _SFR_MEM8(0x09A0) -#define USARTD0_STATUS _SFR_MEM8(0x09A1) -#define USARTD0_CTRLA _SFR_MEM8(0x09A3) -#define USARTD0_CTRLB _SFR_MEM8(0x09A4) -#define USARTD0_CTRLC _SFR_MEM8(0x09A5) -#define USARTD0_BAUDCTRLA _SFR_MEM8(0x09A6) -#define USARTD0_BAUDCTRLB _SFR_MEM8(0x09A7) - -/* SPI - Serial Peripheral Interface */ -#define SPID_CTRL _SFR_MEM8(0x09C0) -#define SPID_INTCTRL _SFR_MEM8(0x09C1) -#define SPID_STATUS _SFR_MEM8(0x09C2) -#define SPID_DATA _SFR_MEM8(0x09C3) - -/* TC0 - 16-bit Timer/Counter 0 */ -#define TCE0_CTRLA _SFR_MEM8(0x0A00) -#define TCE0_CTRLB _SFR_MEM8(0x0A01) -#define TCE0_CTRLC _SFR_MEM8(0x0A02) -#define TCE0_CTRLD _SFR_MEM8(0x0A03) -#define TCE0_CTRLE _SFR_MEM8(0x0A04) -#define TCE0_INTCTRLA _SFR_MEM8(0x0A06) -#define TCE0_INTCTRLB _SFR_MEM8(0x0A07) -#define TCE0_CTRLFCLR _SFR_MEM8(0x0A08) -#define TCE0_CTRLFSET _SFR_MEM8(0x0A09) -#define TCE0_CTRLGCLR _SFR_MEM8(0x0A0A) -#define TCE0_CTRLGSET _SFR_MEM8(0x0A0B) -#define TCE0_INTFLAGS _SFR_MEM8(0x0A0C) -#define TCE0_TEMP _SFR_MEM8(0x0A0F) -#define TCE0_CNT _SFR_MEM16(0x0A20) -#define TCE0_PER _SFR_MEM16(0x0A26) -#define TCE0_CCA _SFR_MEM16(0x0A28) -#define TCE0_CCB _SFR_MEM16(0x0A2A) -#define TCE0_CCC _SFR_MEM16(0x0A2C) -#define TCE0_CCD _SFR_MEM16(0x0A2E) -#define TCE0_PERBUF _SFR_MEM16(0x0A36) -#define TCE0_CCABUF _SFR_MEM16(0x0A38) -#define TCE0_CCBBUF _SFR_MEM16(0x0A3A) -#define TCE0_CCCBUF _SFR_MEM16(0x0A3C) -#define TCE0_CCDBUF _SFR_MEM16(0x0A3E) - -/* TC2 - 16-bit Timer/Counter type 2 */ -#define TCE2_CTRLA _SFR_MEM8(0x0A00) -#define TCE2_CTRLB _SFR_MEM8(0x0A01) -#define TCE2_CTRLC _SFR_MEM8(0x0A02) -#define TCE2_CTRLE _SFR_MEM8(0x0A04) -#define TCE2_INTCTRLA _SFR_MEM8(0x0A06) -#define TCE2_INTCTRLB _SFR_MEM8(0x0A07) -#define TCE2_CTRLF _SFR_MEM8(0x0A09) -#define TCE2_INTFLAGS _SFR_MEM8(0x0A0C) -#define TCE2_LCNT _SFR_MEM8(0x0A20) -#define TCE2_HCNT _SFR_MEM8(0x0A21) -#define TCE2_LPER _SFR_MEM8(0x0A26) -#define TCE2_HPER _SFR_MEM8(0x0A27) -#define TCE2_LCMPA _SFR_MEM8(0x0A28) -#define TCE2_HCMPA _SFR_MEM8(0x0A29) -#define TCE2_LCMPB _SFR_MEM8(0x0A2A) -#define TCE2_HCMPB _SFR_MEM8(0x0A2B) -#define TCE2_LCMPC _SFR_MEM8(0x0A2C) -#define TCE2_HCMPC _SFR_MEM8(0x0A2D) -#define TCE2_LCMPD _SFR_MEM8(0x0A2E) -#define TCE2_HCMPD _SFR_MEM8(0x0A2F) - -/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ -#define USARTE0_DATA _SFR_MEM8(0x0AA0) -#define USARTE0_STATUS _SFR_MEM8(0x0AA1) -#define USARTE0_CTRLA _SFR_MEM8(0x0AA3) -#define USARTE0_CTRLB _SFR_MEM8(0x0AA4) -#define USARTE0_CTRLC _SFR_MEM8(0x0AA5) -#define USARTE0_BAUDCTRLA _SFR_MEM8(0x0AA6) -#define USARTE0_BAUDCTRLB _SFR_MEM8(0x0AA7) - -/* TC0 - 16-bit Timer/Counter 0 */ -#define TCF0_CTRLA _SFR_MEM8(0x0B00) -#define TCF0_CTRLB _SFR_MEM8(0x0B01) -#define TCF0_CTRLC _SFR_MEM8(0x0B02) -#define TCF0_CTRLD _SFR_MEM8(0x0B03) -#define TCF0_CTRLE _SFR_MEM8(0x0B04) -#define TCF0_INTCTRLA _SFR_MEM8(0x0B06) -#define TCF0_INTCTRLB _SFR_MEM8(0x0B07) -#define TCF0_CTRLFCLR _SFR_MEM8(0x0B08) -#define TCF0_CTRLFSET _SFR_MEM8(0x0B09) -#define TCF0_CTRLGCLR _SFR_MEM8(0x0B0A) -#define TCF0_CTRLGSET _SFR_MEM8(0x0B0B) -#define TCF0_INTFLAGS _SFR_MEM8(0x0B0C) -#define TCF0_TEMP _SFR_MEM8(0x0B0F) -#define TCF0_CNT _SFR_MEM16(0x0B20) -#define TCF0_PER _SFR_MEM16(0x0B26) -#define TCF0_CCA _SFR_MEM16(0x0B28) -#define TCF0_CCB _SFR_MEM16(0x0B2A) -#define TCF0_CCC _SFR_MEM16(0x0B2C) -#define TCF0_CCD _SFR_MEM16(0x0B2E) -#define TCF0_PERBUF _SFR_MEM16(0x0B36) -#define TCF0_CCABUF _SFR_MEM16(0x0B38) -#define TCF0_CCBBUF _SFR_MEM16(0x0B3A) -#define TCF0_CCCBUF _SFR_MEM16(0x0B3C) -#define TCF0_CCDBUF _SFR_MEM16(0x0B3E) - -/* TC2 - 16-bit Timer/Counter type 2 */ -#define TCF2_CTRLA _SFR_MEM8(0x0B00) -#define TCF2_CTRLB _SFR_MEM8(0x0B01) -#define TCF2_CTRLC _SFR_MEM8(0x0B02) -#define TCF2_CTRLE _SFR_MEM8(0x0B04) -#define TCF2_INTCTRLA _SFR_MEM8(0x0B06) -#define TCF2_INTCTRLB _SFR_MEM8(0x0B07) -#define TCF2_CTRLF _SFR_MEM8(0x0B09) -#define TCF2_INTFLAGS _SFR_MEM8(0x0B0C) -#define TCF2_LCNT _SFR_MEM8(0x0B20) -#define TCF2_HCNT _SFR_MEM8(0x0B21) -#define TCF2_LPER _SFR_MEM8(0x0B26) -#define TCF2_HPER _SFR_MEM8(0x0B27) -#define TCF2_LCMPA _SFR_MEM8(0x0B28) -#define TCF2_HCMPA _SFR_MEM8(0x0B29) -#define TCF2_LCMPB _SFR_MEM8(0x0B2A) -#define TCF2_HCMPB _SFR_MEM8(0x0B2B) -#define TCF2_LCMPC _SFR_MEM8(0x0B2C) -#define TCF2_HCMPC _SFR_MEM8(0x0B2D) -#define TCF2_LCMPD _SFR_MEM8(0x0B2E) -#define TCF2_HCMPD _SFR_MEM8(0x0B2F) - -/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ -#define USARTF0_DATA _SFR_MEM8(0x0BA0) -#define USARTF0_STATUS _SFR_MEM8(0x0BA1) -#define USARTF0_CTRLA _SFR_MEM8(0x0BA3) -#define USARTF0_CTRLB _SFR_MEM8(0x0BA4) -#define USARTF0_CTRLC _SFR_MEM8(0x0BA5) -#define USARTF0_BAUDCTRLA _SFR_MEM8(0x0BA6) -#define USARTF0_BAUDCTRLB _SFR_MEM8(0x0BA7) - - - -/*================== Bitfield Definitions ================== */ - -/* VPORT - Virtual Ports */ -/* VPORT.INTFLAGS bit masks and bit positions */ -#define VPORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ -#define VPORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ - -#define VPORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ -#define VPORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ - -/* XOCD - On-Chip Debug System */ -/* OCD.OCDR0 bit masks and bit positions */ -#define OCD_OCDRD_gm 0xFF /* OCDR Dirty group mask. */ -#define OCD_OCDRD_gp 0 /* OCDR Dirty group position. */ -#define OCD_OCDRD0_bm (1<<0) /* OCDR Dirty bit 0 mask. */ -#define OCD_OCDRD0_bp 0 /* OCDR Dirty bit 0 position. */ -#define OCD_OCDRD1_bm (1<<1) /* OCDR Dirty bit 1 mask. */ -#define OCD_OCDRD1_bp 1 /* OCDR Dirty bit 1 position. */ -#define OCD_OCDRD2_bm (1<<2) /* OCDR Dirty bit 2 mask. */ -#define OCD_OCDRD2_bp 2 /* OCDR Dirty bit 2 position. */ -#define OCD_OCDRD3_bm (1<<3) /* OCDR Dirty bit 3 mask. */ -#define OCD_OCDRD3_bp 3 /* OCDR Dirty bit 3 position. */ -#define OCD_OCDRD4_bm (1<<4) /* OCDR Dirty bit 4 mask. */ -#define OCD_OCDRD4_bp 4 /* OCDR Dirty bit 4 position. */ -#define OCD_OCDRD5_bm (1<<5) /* OCDR Dirty bit 5 mask. */ -#define OCD_OCDRD5_bp 5 /* OCDR Dirty bit 5 position. */ -#define OCD_OCDRD6_bm (1<<6) /* OCDR Dirty bit 6 mask. */ -#define OCD_OCDRD6_bp 6 /* OCDR Dirty bit 6 position. */ -#define OCD_OCDRD7_bm (1<<7) /* OCDR Dirty bit 7 mask. */ -#define OCD_OCDRD7_bp 7 /* OCDR Dirty bit 7 position. */ - -/* OCD.OCDR1 bit masks and bit positions */ -/* OCD_OCDRD Predefined. */ -/* OCD_OCDRD Predefined. */ - -/* CPU - CPU */ -/* CPU.CCP bit masks and bit positions */ -#define CPU_CCP_gm 0xFF /* CCP signature group mask. */ -#define CPU_CCP_gp 0 /* CCP signature group position. */ -#define CPU_CCP0_bm (1<<0) /* CCP signature bit 0 mask. */ -#define CPU_CCP0_bp 0 /* CCP signature bit 0 position. */ -#define CPU_CCP1_bm (1<<1) /* CCP signature bit 1 mask. */ -#define CPU_CCP1_bp 1 /* CCP signature bit 1 position. */ -#define CPU_CCP2_bm (1<<2) /* CCP signature bit 2 mask. */ -#define CPU_CCP2_bp 2 /* CCP signature bit 2 position. */ -#define CPU_CCP3_bm (1<<3) /* CCP signature bit 3 mask. */ -#define CPU_CCP3_bp 3 /* CCP signature bit 3 position. */ -#define CPU_CCP4_bm (1<<4) /* CCP signature bit 4 mask. */ -#define CPU_CCP4_bp 4 /* CCP signature bit 4 position. */ -#define CPU_CCP5_bm (1<<5) /* CCP signature bit 5 mask. */ -#define CPU_CCP5_bp 5 /* CCP signature bit 5 position. */ -#define CPU_CCP6_bm (1<<6) /* CCP signature bit 6 mask. */ -#define CPU_CCP6_bp 6 /* CCP signature bit 6 position. */ -#define CPU_CCP7_bm (1<<7) /* CCP signature bit 7 mask. */ -#define CPU_CCP7_bp 7 /* CCP signature bit 7 position. */ - -/* CPU.SREG bit masks and bit positions */ -#define CPU_I_bm 0x80 /* Global Interrupt Enable Flag bit mask. */ -#define CPU_I_bp 7 /* Global Interrupt Enable Flag bit position. */ - -#define CPU_T_bm 0x40 /* Transfer Bit bit mask. */ -#define CPU_T_bp 6 /* Transfer Bit bit position. */ - -#define CPU_H_bm 0x20 /* Half Carry Flag bit mask. */ -#define CPU_H_bp 5 /* Half Carry Flag bit position. */ - -#define CPU_S_bm 0x10 /* N Exclusive Or V Flag bit mask. */ -#define CPU_S_bp 4 /* N Exclusive Or V Flag bit position. */ - -#define CPU_V_bm 0x08 /* Two's Complement Overflow Flag bit mask. */ -#define CPU_V_bp 3 /* Two's Complement Overflow Flag bit position. */ - -#define CPU_N_bm 0x04 /* Negative Flag bit mask. */ -#define CPU_N_bp 2 /* Negative Flag bit position. */ - -#define CPU_Z_bm 0x02 /* Zero Flag bit mask. */ -#define CPU_Z_bp 1 /* Zero Flag bit position. */ - -#define CPU_C_bm 0x01 /* Carry Flag bit mask. */ -#define CPU_C_bp 0 /* Carry Flag bit position. */ - -/* CLK - Clock System */ -/* CLK.CTRL bit masks and bit positions */ -#define CLK_SCLKSEL_gm 0x07 /* System Clock Selection group mask. */ -#define CLK_SCLKSEL_gp 0 /* System Clock Selection group position. */ -#define CLK_SCLKSEL0_bm (1<<0) /* System Clock Selection bit 0 mask. */ -#define CLK_SCLKSEL0_bp 0 /* System Clock Selection bit 0 position. */ -#define CLK_SCLKSEL1_bm (1<<1) /* System Clock Selection bit 1 mask. */ -#define CLK_SCLKSEL1_bp 1 /* System Clock Selection bit 1 position. */ -#define CLK_SCLKSEL2_bm (1<<2) /* System Clock Selection bit 2 mask. */ -#define CLK_SCLKSEL2_bp 2 /* System Clock Selection bit 2 position. */ - -/* CLK.PSCTRL bit masks and bit positions */ -#define CLK_PSADIV_gm 0x7C /* Prescaler A Division Factor group mask. */ -#define CLK_PSADIV_gp 2 /* Prescaler A Division Factor group position. */ -#define CLK_PSADIV0_bm (1<<2) /* Prescaler A Division Factor bit 0 mask. */ -#define CLK_PSADIV0_bp 2 /* Prescaler A Division Factor bit 0 position. */ -#define CLK_PSADIV1_bm (1<<3) /* Prescaler A Division Factor bit 1 mask. */ -#define CLK_PSADIV1_bp 3 /* Prescaler A Division Factor bit 1 position. */ -#define CLK_PSADIV2_bm (1<<4) /* Prescaler A Division Factor bit 2 mask. */ -#define CLK_PSADIV2_bp 4 /* Prescaler A Division Factor bit 2 position. */ -#define CLK_PSADIV3_bm (1<<5) /* Prescaler A Division Factor bit 3 mask. */ -#define CLK_PSADIV3_bp 5 /* Prescaler A Division Factor bit 3 position. */ -#define CLK_PSADIV4_bm (1<<6) /* Prescaler A Division Factor bit 4 mask. */ -#define CLK_PSADIV4_bp 6 /* Prescaler A Division Factor bit 4 position. */ - -#define CLK_PSBCDIV_gm 0x03 /* Prescaler B and C Division factor group mask. */ -#define CLK_PSBCDIV_gp 0 /* Prescaler B and C Division factor group position. */ -#define CLK_PSBCDIV0_bm (1<<0) /* Prescaler B and C Division factor bit 0 mask. */ -#define CLK_PSBCDIV0_bp 0 /* Prescaler B and C Division factor bit 0 position. */ -#define CLK_PSBCDIV1_bm (1<<1) /* Prescaler B and C Division factor bit 1 mask. */ -#define CLK_PSBCDIV1_bp 1 /* Prescaler B and C Division factor bit 1 position. */ - -/* CLK.LOCK bit masks and bit positions */ -#define CLK_LOCK_bm 0x01 /* Clock System Lock bit mask. */ -#define CLK_LOCK_bp 0 /* Clock System Lock bit position. */ - -/* CLK.RTCCTRL bit masks and bit positions */ -#define CLK_RTCSRC_gm 0x0E /* Clock Source group mask. */ -#define CLK_RTCSRC_gp 1 /* Clock Source group position. */ -#define CLK_RTCSRC0_bm (1<<1) /* Clock Source bit 0 mask. */ -#define CLK_RTCSRC0_bp 1 /* Clock Source bit 0 position. */ -#define CLK_RTCSRC1_bm (1<<2) /* Clock Source bit 1 mask. */ -#define CLK_RTCSRC1_bp 2 /* Clock Source bit 1 position. */ -#define CLK_RTCSRC2_bm (1<<3) /* Clock Source bit 2 mask. */ -#define CLK_RTCSRC2_bp 3 /* Clock Source bit 2 position. */ - -#define CLK_RTCEN_bm 0x01 /* Clock Source Enable bit mask. */ -#define CLK_RTCEN_bp 0 /* Clock Source Enable bit position. */ - -/* CLK.USBCTRL bit masks and bit positions */ -#define CLK_USBPSDIV_gm 0x38 /* Prescaler Division Factor group mask. */ -#define CLK_USBPSDIV_gp 3 /* Prescaler Division Factor group position. */ -#define CLK_USBPSDIV0_bm (1<<3) /* Prescaler Division Factor bit 0 mask. */ -#define CLK_USBPSDIV0_bp 3 /* Prescaler Division Factor bit 0 position. */ -#define CLK_USBPSDIV1_bm (1<<4) /* Prescaler Division Factor bit 1 mask. */ -#define CLK_USBPSDIV1_bp 4 /* Prescaler Division Factor bit 1 position. */ -#define CLK_USBPSDIV2_bm (1<<5) /* Prescaler Division Factor bit 2 mask. */ -#define CLK_USBPSDIV2_bp 5 /* Prescaler Division Factor bit 2 position. */ - -#define CLK_USBSRC_gm 0x06 /* Clock Source group mask. */ -#define CLK_USBSRC_gp 1 /* Clock Source group position. */ -#define CLK_USBSRC0_bm (1<<1) /* Clock Source bit 0 mask. */ -#define CLK_USBSRC0_bp 1 /* Clock Source bit 0 position. */ -#define CLK_USBSRC1_bm (1<<2) /* Clock Source bit 1 mask. */ -#define CLK_USBSRC1_bp 2 /* Clock Source bit 1 position. */ - -#define CLK_USBSEN_bm 0x01 /* Clock Source Enable bit mask. */ -#define CLK_USBSEN_bp 0 /* Clock Source Enable bit position. */ - -/* PR.PRGEN bit masks and bit positions */ -#define PR_USB_bm 0x40 /* USB bit mask. */ -#define PR_USB_bp 6 /* USB bit position. */ - -#define PR_AES_bm 0x10 /* AES bit mask. */ -#define PR_AES_bp 4 /* AES bit position. */ - -#define PR_EBI_bm 0x08 /* External Bus Interface bit mask. */ -#define PR_EBI_bp 3 /* External Bus Interface bit position. */ - -#define PR_RTC_bm 0x04 /* Real-time Counter bit mask. */ -#define PR_RTC_bp 2 /* Real-time Counter bit position. */ - -#define PR_EVSYS_bm 0x02 /* Event System bit mask. */ -#define PR_EVSYS_bp 1 /* Event System bit position. */ - -#define PR_DMA_bm 0x01 /* DMA-Controller bit mask. */ -#define PR_DMA_bp 0 /* DMA-Controller bit position. */ - -/* PR.PRPA bit masks and bit positions */ -#define PR_DAC_bm 0x04 /* Port A DAC bit mask. */ -#define PR_DAC_bp 2 /* Port A DAC bit position. */ - -#define PR_ADC_bm 0x02 /* Port A ADC bit mask. */ -#define PR_ADC_bp 1 /* Port A ADC bit position. */ - -#define PR_AC_bm 0x01 /* Port A Analog Comparator bit mask. */ -#define PR_AC_bp 0 /* Port A Analog Comparator bit position. */ - -/* PR.PRPB bit masks and bit positions */ -/* PR_DAC Predefined. */ -/* PR_DAC Predefined. */ - -/* PR_ADC Predefined. */ -/* PR_ADC Predefined. */ - -/* PR_AC Predefined. */ -/* PR_AC Predefined. */ - -/* PR.PRPC bit masks and bit positions */ -#define PR_TWI_bm 0x40 /* Port C Two-wire Interface bit mask. */ -#define PR_TWI_bp 6 /* Port C Two-wire Interface bit position. */ - -#define PR_USART1_bm 0x20 /* Port C USART1 bit mask. */ -#define PR_USART1_bp 5 /* Port C USART1 bit position. */ - -#define PR_USART0_bm 0x10 /* Port C USART0 bit mask. */ -#define PR_USART0_bp 4 /* Port C USART0 bit position. */ - -#define PR_SPI_bm 0x08 /* Port C SPI bit mask. */ -#define PR_SPI_bp 3 /* Port C SPI bit position. */ - -#define PR_HIRES_bm 0x04 /* Port C AWEX bit mask. */ -#define PR_HIRES_bp 2 /* Port C AWEX bit position. */ - -#define PR_TC1_bm 0x02 /* Port C Timer/Counter1 bit mask. */ -#define PR_TC1_bp 1 /* Port C Timer/Counter1 bit position. */ - -#define PR_TC0_bm 0x01 /* Port C Timer/Counter0 bit mask. */ -#define PR_TC0_bp 0 /* Port C Timer/Counter0 bit position. */ - -/* PR.PRPD bit masks and bit positions */ -/* PR_TWI Predefined. */ -/* PR_TWI Predefined. */ - -/* PR_USART1 Predefined. */ -/* PR_USART1 Predefined. */ - -/* PR_USART0 Predefined. */ -/* PR_USART0 Predefined. */ - -/* PR_SPI Predefined. */ -/* PR_SPI Predefined. */ - -/* PR_HIRES Predefined. */ -/* PR_HIRES Predefined. */ - -/* PR_TC1 Predefined. */ -/* PR_TC1 Predefined. */ - -/* PR_TC0 Predefined. */ -/* PR_TC0 Predefined. */ - -/* PR.PRPE bit masks and bit positions */ -/* PR_TWI Predefined. */ -/* PR_TWI Predefined. */ - -/* PR_USART1 Predefined. */ -/* PR_USART1 Predefined. */ - -/* PR_USART0 Predefined. */ -/* PR_USART0 Predefined. */ - -/* PR_SPI Predefined. */ -/* PR_SPI Predefined. */ - -/* PR_HIRES Predefined. */ -/* PR_HIRES Predefined. */ - -/* PR_TC1 Predefined. */ -/* PR_TC1 Predefined. */ - -/* PR_TC0 Predefined. */ -/* PR_TC0 Predefined. */ - -/* PR.PRPF bit masks and bit positions */ -/* PR_TWI Predefined. */ -/* PR_TWI Predefined. */ - -/* PR_USART1 Predefined. */ -/* PR_USART1 Predefined. */ - -/* PR_USART0 Predefined. */ -/* PR_USART0 Predefined. */ - -/* PR_SPI Predefined. */ -/* PR_SPI Predefined. */ - -/* PR_HIRES Predefined. */ -/* PR_HIRES Predefined. */ - -/* PR_TC1 Predefined. */ -/* PR_TC1 Predefined. */ - -/* PR_TC0 Predefined. */ -/* PR_TC0 Predefined. */ - -/* SLEEP - Sleep Controller */ -/* SLEEP.CTRL bit masks and bit positions */ -#define SLEEP_SMODE_gm 0x0E /* Sleep Mode group mask. */ -#define SLEEP_SMODE_gp 1 /* Sleep Mode group position. */ -#define SLEEP_SMODE0_bm (1<<1) /* Sleep Mode bit 0 mask. */ -#define SLEEP_SMODE0_bp 1 /* Sleep Mode bit 0 position. */ -#define SLEEP_SMODE1_bm (1<<2) /* Sleep Mode bit 1 mask. */ -#define SLEEP_SMODE1_bp 2 /* Sleep Mode bit 1 position. */ -#define SLEEP_SMODE2_bm (1<<3) /* Sleep Mode bit 2 mask. */ -#define SLEEP_SMODE2_bp 3 /* Sleep Mode bit 2 position. */ - -#define SLEEP_SEN_bm 0x01 /* Sleep Enable bit mask. */ -#define SLEEP_SEN_bp 0 /* Sleep Enable bit position. */ - -/* OSC - Oscillator */ -/* OSC.CTRL bit masks and bit positions */ -#define OSC_PLLEN_bm 0x10 /* PLL Enable bit mask. */ -#define OSC_PLLEN_bp 4 /* PLL Enable bit position. */ - -#define OSC_XOSCEN_bm 0x08 /* External Oscillator Enable bit mask. */ -#define OSC_XOSCEN_bp 3 /* External Oscillator Enable bit position. */ - -#define OSC_RC32KEN_bm 0x04 /* Internal 32.768 kHz RC Oscillator Enable bit mask. */ -#define OSC_RC32KEN_bp 2 /* Internal 32.768 kHz RC Oscillator Enable bit position. */ - -#define OSC_RC32MEN_bm 0x02 /* Internal 32 MHz RC Oscillator Enable bit mask. */ -#define OSC_RC32MEN_bp 1 /* Internal 32 MHz RC Oscillator Enable bit position. */ - -#define OSC_RC2MEN_bm 0x01 /* Internal 2 MHz RC Oscillator Enable bit mask. */ -#define OSC_RC2MEN_bp 0 /* Internal 2 MHz RC Oscillator Enable bit position. */ - -/* OSC.STATUS bit masks and bit positions */ -#define OSC_PLLRDY_bm 0x10 /* PLL Ready bit mask. */ -#define OSC_PLLRDY_bp 4 /* PLL Ready bit position. */ - -#define OSC_XOSCRDY_bm 0x08 /* External Oscillator Ready bit mask. */ -#define OSC_XOSCRDY_bp 3 /* External Oscillator Ready bit position. */ - -#define OSC_RC32KRDY_bm 0x04 /* Internal 32.768 kHz RC Oscillator Ready bit mask. */ -#define OSC_RC32KRDY_bp 2 /* Internal 32.768 kHz RC Oscillator Ready bit position. */ - -#define OSC_RC32MRDY_bm 0x02 /* Internal 32 MHz RC Oscillator Ready bit mask. */ -#define OSC_RC32MRDY_bp 1 /* Internal 32 MHz RC Oscillator Ready bit position. */ - -#define OSC_RC2MRDY_bm 0x01 /* Internal 2 MHz RC Oscillator Ready bit mask. */ -#define OSC_RC2MRDY_bp 0 /* Internal 2 MHz RC Oscillator Ready bit position. */ - -/* OSC.XOSCCTRL bit masks and bit positions */ -#define OSC_FRQRANGE_gm 0xC0 /* Frequency Range group mask. */ -#define OSC_FRQRANGE_gp 6 /* Frequency Range group position. */ -#define OSC_FRQRANGE0_bm (1<<6) /* Frequency Range bit 0 mask. */ -#define OSC_FRQRANGE0_bp 6 /* Frequency Range bit 0 position. */ -#define OSC_FRQRANGE1_bm (1<<7) /* Frequency Range bit 1 mask. */ -#define OSC_FRQRANGE1_bp 7 /* Frequency Range bit 1 position. */ - -#define OSC_X32KLPM_bm 0x20 /* 32.768 kHz XTAL OSC Low-power Mode bit mask. */ -#define OSC_X32KLPM_bp 5 /* 32.768 kHz XTAL OSC Low-power Mode bit position. */ - -#define OSC_XOSCPWR_bm 0x10 /* 16 MHz Crystal Oscillator High Power mode bit mask. */ -#define OSC_XOSCPWR_bp 4 /* 16 MHz Crystal Oscillator High Power mode bit position. */ - -#define OSC_XOSCSEL_gm 0x0F /* External Oscillator Selection and Startup Time group mask. */ -#define OSC_XOSCSEL_gp 0 /* External Oscillator Selection and Startup Time group position. */ -#define OSC_XOSCSEL0_bm (1<<0) /* External Oscillator Selection and Startup Time bit 0 mask. */ -#define OSC_XOSCSEL0_bp 0 /* External Oscillator Selection and Startup Time bit 0 position. */ -#define OSC_XOSCSEL1_bm (1<<1) /* External Oscillator Selection and Startup Time bit 1 mask. */ -#define OSC_XOSCSEL1_bp 1 /* External Oscillator Selection and Startup Time bit 1 position. */ -#define OSC_XOSCSEL2_bm (1<<2) /* External Oscillator Selection and Startup Time bit 2 mask. */ -#define OSC_XOSCSEL2_bp 2 /* External Oscillator Selection and Startup Time bit 2 position. */ -#define OSC_XOSCSEL3_bm (1<<3) /* External Oscillator Selection and Startup Time bit 3 mask. */ -#define OSC_XOSCSEL3_bp 3 /* External Oscillator Selection and Startup Time bit 3 position. */ - -/* OSC.XOSCFAIL bit masks and bit positions */ -#define OSC_PLLFDIF_bm 0x08 /* PLL Failure Detection Interrupt Flag bit mask. */ -#define OSC_PLLFDIF_bp 3 /* PLL Failure Detection Interrupt Flag bit position. */ - -#define OSC_PLLFDEN_bm 0x04 /* PLL Failure Detection Enable bit mask. */ -#define OSC_PLLFDEN_bp 2 /* PLL Failure Detection Enable bit position. */ - -#define OSC_XOSCFDIF_bm 0x02 /* XOSC Failure Detection Interrupt Flag bit mask. */ -#define OSC_XOSCFDIF_bp 1 /* XOSC Failure Detection Interrupt Flag bit position. */ - -#define OSC_XOSCFDEN_bm 0x01 /* XOSC Failure Detection Enable bit mask. */ -#define OSC_XOSCFDEN_bp 0 /* XOSC Failure Detection Enable bit position. */ - -/* OSC.PLLCTRL bit masks and bit positions */ -#define OSC_PLLSRC_gm 0xC0 /* Clock Source group mask. */ -#define OSC_PLLSRC_gp 6 /* Clock Source group position. */ -#define OSC_PLLSRC0_bm (1<<6) /* Clock Source bit 0 mask. */ -#define OSC_PLLSRC0_bp 6 /* Clock Source bit 0 position. */ -#define OSC_PLLSRC1_bm (1<<7) /* Clock Source bit 1 mask. */ -#define OSC_PLLSRC1_bp 7 /* Clock Source bit 1 position. */ - -#define OSC_PLLDIV_bm 0x20 /* Divide by 2 bit mask. */ -#define OSC_PLLDIV_bp 5 /* Divide by 2 bit position. */ - -#define OSC_PLLFAC_gm 0x1F /* Multiplication Factor group mask. */ -#define OSC_PLLFAC_gp 0 /* Multiplication Factor group position. */ -#define OSC_PLLFAC0_bm (1<<0) /* Multiplication Factor bit 0 mask. */ -#define OSC_PLLFAC0_bp 0 /* Multiplication Factor bit 0 position. */ -#define OSC_PLLFAC1_bm (1<<1) /* Multiplication Factor bit 1 mask. */ -#define OSC_PLLFAC1_bp 1 /* Multiplication Factor bit 1 position. */ -#define OSC_PLLFAC2_bm (1<<2) /* Multiplication Factor bit 2 mask. */ -#define OSC_PLLFAC2_bp 2 /* Multiplication Factor bit 2 position. */ -#define OSC_PLLFAC3_bm (1<<3) /* Multiplication Factor bit 3 mask. */ -#define OSC_PLLFAC3_bp 3 /* Multiplication Factor bit 3 position. */ -#define OSC_PLLFAC4_bm (1<<4) /* Multiplication Factor bit 4 mask. */ -#define OSC_PLLFAC4_bp 4 /* Multiplication Factor bit 4 position. */ - -/* OSC.DFLLCTRL bit masks and bit positions */ -#define OSC_RC32MCREF_gm 0x06 /* 32 MHz DFLL Calibration Reference group mask. */ -#define OSC_RC32MCREF_gp 1 /* 32 MHz DFLL Calibration Reference group position. */ -#define OSC_RC32MCREF0_bm (1<<1) /* 32 MHz DFLL Calibration Reference bit 0 mask. */ -#define OSC_RC32MCREF0_bp 1 /* 32 MHz DFLL Calibration Reference bit 0 position. */ -#define OSC_RC32MCREF1_bm (1<<2) /* 32 MHz DFLL Calibration Reference bit 1 mask. */ -#define OSC_RC32MCREF1_bp 2 /* 32 MHz DFLL Calibration Reference bit 1 position. */ - -#define OSC_RC2MCREF_bm 0x01 /* 2 MHz DFLL Calibration Reference bit mask. */ -#define OSC_RC2MCREF_bp 0 /* 2 MHz DFLL Calibration Reference bit position. */ - -/* DFLL - DFLL */ -/* DFLL.CTRL bit masks and bit positions */ -#define DFLL_ENABLE_bm 0x01 /* DFLL Enable bit mask. */ -#define DFLL_ENABLE_bp 0 /* DFLL Enable bit position. */ - -/* DFLL.CALA bit masks and bit positions */ -#define DFLL_CALL_gm 0x7F /* DFLL Calibration Value A group mask. */ -#define DFLL_CALL_gp 0 /* DFLL Calibration Value A group position. */ -#define DFLL_CALL0_bm (1<<0) /* DFLL Calibration Value A bit 0 mask. */ -#define DFLL_CALL0_bp 0 /* DFLL Calibration Value A bit 0 position. */ -#define DFLL_CALL1_bm (1<<1) /* DFLL Calibration Value A bit 1 mask. */ -#define DFLL_CALL1_bp 1 /* DFLL Calibration Value A bit 1 position. */ -#define DFLL_CALL2_bm (1<<2) /* DFLL Calibration Value A bit 2 mask. */ -#define DFLL_CALL2_bp 2 /* DFLL Calibration Value A bit 2 position. */ -#define DFLL_CALL3_bm (1<<3) /* DFLL Calibration Value A bit 3 mask. */ -#define DFLL_CALL3_bp 3 /* DFLL Calibration Value A bit 3 position. */ -#define DFLL_CALL4_bm (1<<4) /* DFLL Calibration Value A bit 4 mask. */ -#define DFLL_CALL4_bp 4 /* DFLL Calibration Value A bit 4 position. */ -#define DFLL_CALL5_bm (1<<5) /* DFLL Calibration Value A bit 5 mask. */ -#define DFLL_CALL5_bp 5 /* DFLL Calibration Value A bit 5 position. */ -#define DFLL_CALL6_bm (1<<6) /* DFLL Calibration Value A bit 6 mask. */ -#define DFLL_CALL6_bp 6 /* DFLL Calibration Value A bit 6 position. */ - -/* DFLL.CALB bit masks and bit positions */ -#define DFLL_CALH_gm 0x3F /* DFLL Calibration Value B group mask. */ -#define DFLL_CALH_gp 0 /* DFLL Calibration Value B group position. */ -#define DFLL_CALH0_bm (1<<0) /* DFLL Calibration Value B bit 0 mask. */ -#define DFLL_CALH0_bp 0 /* DFLL Calibration Value B bit 0 position. */ -#define DFLL_CALH1_bm (1<<1) /* DFLL Calibration Value B bit 1 mask. */ -#define DFLL_CALH1_bp 1 /* DFLL Calibration Value B bit 1 position. */ -#define DFLL_CALH2_bm (1<<2) /* DFLL Calibration Value B bit 2 mask. */ -#define DFLL_CALH2_bp 2 /* DFLL Calibration Value B bit 2 position. */ -#define DFLL_CALH3_bm (1<<3) /* DFLL Calibration Value B bit 3 mask. */ -#define DFLL_CALH3_bp 3 /* DFLL Calibration Value B bit 3 position. */ -#define DFLL_CALH4_bm (1<<4) /* DFLL Calibration Value B bit 4 mask. */ -#define DFLL_CALH4_bp 4 /* DFLL Calibration Value B bit 4 position. */ -#define DFLL_CALH5_bm (1<<5) /* DFLL Calibration Value B bit 5 mask. */ -#define DFLL_CALH5_bp 5 /* DFLL Calibration Value B bit 5 position. */ - -/* RST - Reset */ -/* RST.STATUS bit masks and bit positions */ -#define RST_SDRF_bm 0x40 /* Spike Detection Reset Flag bit mask. */ -#define RST_SDRF_bp 6 /* Spike Detection Reset Flag bit position. */ - -#define RST_SRF_bm 0x20 /* Software Reset Flag bit mask. */ -#define RST_SRF_bp 5 /* Software Reset Flag bit position. */ - -#define RST_PDIRF_bm 0x10 /* Programming and Debug Interface Interface Reset Flag bit mask. */ -#define RST_PDIRF_bp 4 /* Programming and Debug Interface Interface Reset Flag bit position. */ - -#define RST_WDRF_bm 0x08 /* Watchdog Reset Flag bit mask. */ -#define RST_WDRF_bp 3 /* Watchdog Reset Flag bit position. */ - -#define RST_BORF_bm 0x04 /* Brown-out Reset Flag bit mask. */ -#define RST_BORF_bp 2 /* Brown-out Reset Flag bit position. */ - -#define RST_EXTRF_bm 0x02 /* External Reset Flag bit mask. */ -#define RST_EXTRF_bp 1 /* External Reset Flag bit position. */ - -#define RST_PORF_bm 0x01 /* Power-on Reset Flag bit mask. */ -#define RST_PORF_bp 0 /* Power-on Reset Flag bit position. */ - -/* RST.CTRL bit masks and bit positions */ -#define RST_SWRST_bm 0x01 /* Software Reset bit mask. */ -#define RST_SWRST_bp 0 /* Software Reset bit position. */ - -/* WDT - Watch-Dog Timer */ -/* WDT.CTRL bit masks and bit positions */ -#define WDT_PER_gm 0x3C /* Period group mask. */ -#define WDT_PER_gp 2 /* Period group position. */ -#define WDT_PER0_bm (1<<2) /* Period bit 0 mask. */ -#define WDT_PER0_bp 2 /* Period bit 0 position. */ -#define WDT_PER1_bm (1<<3) /* Period bit 1 mask. */ -#define WDT_PER1_bp 3 /* Period bit 1 position. */ -#define WDT_PER2_bm (1<<4) /* Period bit 2 mask. */ -#define WDT_PER2_bp 4 /* Period bit 2 position. */ -#define WDT_PER3_bm (1<<5) /* Period bit 3 mask. */ -#define WDT_PER3_bp 5 /* Period bit 3 position. */ - -#define WDT_ENABLE_bm 0x02 /* Enable bit mask. */ -#define WDT_ENABLE_bp 1 /* Enable bit position. */ - -#define WDT_CEN_bm 0x01 /* Change Enable bit mask. */ -#define WDT_CEN_bp 0 /* Change Enable bit position. */ - -/* WDT.WINCTRL bit masks and bit positions */ -#define WDT_WPER_gm 0x3C /* Windowed Mode Period group mask. */ -#define WDT_WPER_gp 2 /* Windowed Mode Period group position. */ -#define WDT_WPER0_bm (1<<2) /* Windowed Mode Period bit 0 mask. */ -#define WDT_WPER0_bp 2 /* Windowed Mode Period bit 0 position. */ -#define WDT_WPER1_bm (1<<3) /* Windowed Mode Period bit 1 mask. */ -#define WDT_WPER1_bp 3 /* Windowed Mode Period bit 1 position. */ -#define WDT_WPER2_bm (1<<4) /* Windowed Mode Period bit 2 mask. */ -#define WDT_WPER2_bp 4 /* Windowed Mode Period bit 2 position. */ -#define WDT_WPER3_bm (1<<5) /* Windowed Mode Period bit 3 mask. */ -#define WDT_WPER3_bp 5 /* Windowed Mode Period bit 3 position. */ - -#define WDT_WEN_bm 0x02 /* Windowed Mode Enable bit mask. */ -#define WDT_WEN_bp 1 /* Windowed Mode Enable bit position. */ - -#define WDT_WCEN_bm 0x01 /* Windowed Mode Change Enable bit mask. */ -#define WDT_WCEN_bp 0 /* Windowed Mode Change Enable bit position. */ - -/* WDT.STATUS bit masks and bit positions */ -#define WDT_SYNCBUSY_bm 0x01 /* Syncronization busy bit mask. */ -#define WDT_SYNCBUSY_bp 0 /* Syncronization busy bit position. */ - -/* MCU - MCU Control */ -/* MCU.ANAINIT bit masks and bit positions */ -#define MCU_STARTUPDLYA_gm 0x03 /* Analog startup delay Port A group mask. */ -#define MCU_STARTUPDLYA_gp 0 /* Analog startup delay Port A group position. */ -#define MCU_STARTUPDLYA0_bm (1<<0) /* Analog startup delay Port A bit 0 mask. */ -#define MCU_STARTUPDLYA0_bp 0 /* Analog startup delay Port A bit 0 position. */ -#define MCU_STARTUPDLYA1_bm (1<<1) /* Analog startup delay Port A bit 1 mask. */ -#define MCU_STARTUPDLYA1_bp 1 /* Analog startup delay Port A bit 1 position. */ - -/* MCU.EVSYSLOCK bit masks and bit positions */ -#define MCU_EVSYS0LOCK_bm 0x01 /* Event Channel 0-3 Lock bit mask. */ -#define MCU_EVSYS0LOCK_bp 0 /* Event Channel 0-3 Lock bit position. */ - -/* MCU.AWEXLOCK bit masks and bit positions */ -#define MCU_AWEXCLOCK_bm 0x01 /* AWeX on T/C C0 Lock bit mask. */ -#define MCU_AWEXCLOCK_bp 0 /* AWeX on T/C C0 Lock bit position. */ - -/* PMIC - Programmable Multi-level Interrupt Controller */ -/* PMIC.STATUS bit masks and bit positions */ -#define PMIC_NMIEX_bm 0x80 /* Non-maskable Interrupt Executing bit mask. */ -#define PMIC_NMIEX_bp 7 /* Non-maskable Interrupt Executing bit position. */ - -#define PMIC_HILVLEX_bm 0x04 /* High Level Interrupt Executing bit mask. */ -#define PMIC_HILVLEX_bp 2 /* High Level Interrupt Executing bit position. */ - -#define PMIC_MEDLVLEX_bm 0x02 /* Medium Level Interrupt Executing bit mask. */ -#define PMIC_MEDLVLEX_bp 1 /* Medium Level Interrupt Executing bit position. */ - -#define PMIC_LOLVLEX_bm 0x01 /* Low Level Interrupt Executing bit mask. */ -#define PMIC_LOLVLEX_bp 0 /* Low Level Interrupt Executing bit position. */ - -/* PMIC.INTPRI bit masks and bit positions */ -#define PMIC_INTPRI_gm 0xFF /* Interrupt Priority group mask. */ -#define PMIC_INTPRI_gp 0 /* Interrupt Priority group position. */ -#define PMIC_INTPRI0_bm (1<<0) /* Interrupt Priority bit 0 mask. */ -#define PMIC_INTPRI0_bp 0 /* Interrupt Priority bit 0 position. */ -#define PMIC_INTPRI1_bm (1<<1) /* Interrupt Priority bit 1 mask. */ -#define PMIC_INTPRI1_bp 1 /* Interrupt Priority bit 1 position. */ -#define PMIC_INTPRI2_bm (1<<2) /* Interrupt Priority bit 2 mask. */ -#define PMIC_INTPRI2_bp 2 /* Interrupt Priority bit 2 position. */ -#define PMIC_INTPRI3_bm (1<<3) /* Interrupt Priority bit 3 mask. */ -#define PMIC_INTPRI3_bp 3 /* Interrupt Priority bit 3 position. */ -#define PMIC_INTPRI4_bm (1<<4) /* Interrupt Priority bit 4 mask. */ -#define PMIC_INTPRI4_bp 4 /* Interrupt Priority bit 4 position. */ -#define PMIC_INTPRI5_bm (1<<5) /* Interrupt Priority bit 5 mask. */ -#define PMIC_INTPRI5_bp 5 /* Interrupt Priority bit 5 position. */ -#define PMIC_INTPRI6_bm (1<<6) /* Interrupt Priority bit 6 mask. */ -#define PMIC_INTPRI6_bp 6 /* Interrupt Priority bit 6 position. */ -#define PMIC_INTPRI7_bm (1<<7) /* Interrupt Priority bit 7 mask. */ -#define PMIC_INTPRI7_bp 7 /* Interrupt Priority bit 7 position. */ - -/* PMIC.CTRL bit masks and bit positions */ -#define PMIC_RREN_bm 0x80 /* Round-Robin Priority Enable bit mask. */ -#define PMIC_RREN_bp 7 /* Round-Robin Priority Enable bit position. */ - -#define PMIC_IVSEL_bm 0x40 /* Interrupt Vector Select bit mask. */ -#define PMIC_IVSEL_bp 6 /* Interrupt Vector Select bit position. */ - -#define PMIC_HILVLEN_bm 0x04 /* High Level Enable bit mask. */ -#define PMIC_HILVLEN_bp 2 /* High Level Enable bit position. */ - -#define PMIC_MEDLVLEN_bm 0x02 /* Medium Level Enable bit mask. */ -#define PMIC_MEDLVLEN_bp 1 /* Medium Level Enable bit position. */ - -#define PMIC_LOLVLEN_bm 0x01 /* Low Level Enable bit mask. */ -#define PMIC_LOLVLEN_bp 0 /* Low Level Enable bit position. */ - -/* PORTCFG - Port Configuration */ -/* PORTCFG.VPCTRLA bit masks and bit positions */ -#define PORTCFG_VP1MAP_gm 0xF0 /* Virtual Port 1 Mapping group mask. */ -#define PORTCFG_VP1MAP_gp 4 /* Virtual Port 1 Mapping group position. */ -#define PORTCFG_VP1MAP0_bm (1<<4) /* Virtual Port 1 Mapping bit 0 mask. */ -#define PORTCFG_VP1MAP0_bp 4 /* Virtual Port 1 Mapping bit 0 position. */ -#define PORTCFG_VP1MAP1_bm (1<<5) /* Virtual Port 1 Mapping bit 1 mask. */ -#define PORTCFG_VP1MAP1_bp 5 /* Virtual Port 1 Mapping bit 1 position. */ -#define PORTCFG_VP1MAP2_bm (1<<6) /* Virtual Port 1 Mapping bit 2 mask. */ -#define PORTCFG_VP1MAP2_bp 6 /* Virtual Port 1 Mapping bit 2 position. */ -#define PORTCFG_VP1MAP3_bm (1<<7) /* Virtual Port 1 Mapping bit 3 mask. */ -#define PORTCFG_VP1MAP3_bp 7 /* Virtual Port 1 Mapping bit 3 position. */ - -#define PORTCFG_VP0MAP_gm 0x0F /* Virtual Port 0 Mapping group mask. */ -#define PORTCFG_VP0MAP_gp 0 /* Virtual Port 0 Mapping group position. */ -#define PORTCFG_VP0MAP0_bm (1<<0) /* Virtual Port 0 Mapping bit 0 mask. */ -#define PORTCFG_VP0MAP0_bp 0 /* Virtual Port 0 Mapping bit 0 position. */ -#define PORTCFG_VP0MAP1_bm (1<<1) /* Virtual Port 0 Mapping bit 1 mask. */ -#define PORTCFG_VP0MAP1_bp 1 /* Virtual Port 0 Mapping bit 1 position. */ -#define PORTCFG_VP0MAP2_bm (1<<2) /* Virtual Port 0 Mapping bit 2 mask. */ -#define PORTCFG_VP0MAP2_bp 2 /* Virtual Port 0 Mapping bit 2 position. */ -#define PORTCFG_VP0MAP3_bm (1<<3) /* Virtual Port 0 Mapping bit 3 mask. */ -#define PORTCFG_VP0MAP3_bp 3 /* Virtual Port 0 Mapping bit 3 position. */ - -/* PORTCFG.VPCTRLB bit masks and bit positions */ -#define PORTCFG_VP3MAP_gm 0xF0 /* Virtual Port 3 Mapping group mask. */ -#define PORTCFG_VP3MAP_gp 4 /* Virtual Port 3 Mapping group position. */ -#define PORTCFG_VP3MAP0_bm (1<<4) /* Virtual Port 3 Mapping bit 0 mask. */ -#define PORTCFG_VP3MAP0_bp 4 /* Virtual Port 3 Mapping bit 0 position. */ -#define PORTCFG_VP3MAP1_bm (1<<5) /* Virtual Port 3 Mapping bit 1 mask. */ -#define PORTCFG_VP3MAP1_bp 5 /* Virtual Port 3 Mapping bit 1 position. */ -#define PORTCFG_VP3MAP2_bm (1<<6) /* Virtual Port 3 Mapping bit 2 mask. */ -#define PORTCFG_VP3MAP2_bp 6 /* Virtual Port 3 Mapping bit 2 position. */ -#define PORTCFG_VP3MAP3_bm (1<<7) /* Virtual Port 3 Mapping bit 3 mask. */ -#define PORTCFG_VP3MAP3_bp 7 /* Virtual Port 3 Mapping bit 3 position. */ - -#define PORTCFG_VP2MAP_gm 0x0F /* Virtual Port 2 Mapping group mask. */ -#define PORTCFG_VP2MAP_gp 0 /* Virtual Port 2 Mapping group position. */ -#define PORTCFG_VP2MAP0_bm (1<<0) /* Virtual Port 2 Mapping bit 0 mask. */ -#define PORTCFG_VP2MAP0_bp 0 /* Virtual Port 2 Mapping bit 0 position. */ -#define PORTCFG_VP2MAP1_bm (1<<1) /* Virtual Port 2 Mapping bit 1 mask. */ -#define PORTCFG_VP2MAP1_bp 1 /* Virtual Port 2 Mapping bit 1 position. */ -#define PORTCFG_VP2MAP2_bm (1<<2) /* Virtual Port 2 Mapping bit 2 mask. */ -#define PORTCFG_VP2MAP2_bp 2 /* Virtual Port 2 Mapping bit 2 position. */ -#define PORTCFG_VP2MAP3_bm (1<<3) /* Virtual Port 2 Mapping bit 3 mask. */ -#define PORTCFG_VP2MAP3_bp 3 /* Virtual Port 2 Mapping bit 3 position. */ - -/* PORTCFG.CLKEVOUT bit masks and bit positions */ -#define PORTCFG_CLKOUT_gm 0x03 /* Peripheral Clock Output Port group mask. */ -#define PORTCFG_CLKOUT_gp 0 /* Peripheral Clock Output Port group position. */ -#define PORTCFG_CLKOUT0_bm (1<<0) /* Peripheral Clock Output Port bit 0 mask. */ -#define PORTCFG_CLKOUT0_bp 0 /* Peripheral Clock Output Port bit 0 position. */ -#define PORTCFG_CLKOUT1_bm (1<<1) /* Peripheral Clock Output Port bit 1 mask. */ -#define PORTCFG_CLKOUT1_bp 1 /* Peripheral Clock Output Port bit 1 position. */ - -#define PORTCFG_CLKOUTSEL_gm 0x0C /* Peripheral Clock Output Select group mask. */ -#define PORTCFG_CLKOUTSEL_gp 2 /* Peripheral Clock Output Select group position. */ -#define PORTCFG_CLKOUTSEL0_bm (1<<2) /* Peripheral Clock Output Select bit 0 mask. */ -#define PORTCFG_CLKOUTSEL0_bp 2 /* Peripheral Clock Output Select bit 0 position. */ -#define PORTCFG_CLKOUTSEL1_bm (1<<3) /* Peripheral Clock Output Select bit 1 mask. */ -#define PORTCFG_CLKOUTSEL1_bp 3 /* Peripheral Clock Output Select bit 1 position. */ - -#define PORTCFG_EVOUT_gm 0x30 /* Event Output Port group mask. */ -#define PORTCFG_EVOUT_gp 4 /* Event Output Port group position. */ -#define PORTCFG_EVOUT0_bm (1<<4) /* Event Output Port bit 0 mask. */ -#define PORTCFG_EVOUT0_bp 4 /* Event Output Port bit 0 position. */ -#define PORTCFG_EVOUT1_bm (1<<5) /* Event Output Port bit 1 mask. */ -#define PORTCFG_EVOUT1_bp 5 /* Event Output Port bit 1 position. */ - -#define PORTCFG_RTCOUT_bm 0x40 /* RTC Clock Output bit mask. */ -#define PORTCFG_RTCOUT_bp 6 /* RTC Clock Output bit position. */ - -#define PORTCFG_CLKEVPIN_bm 0x80 /* Peripheral Clock and Event Output pin Select bit mask. */ -#define PORTCFG_CLKEVPIN_bp 7 /* Peripheral Clock and Event Output pin Select bit position. */ - -/* PORTCFG.EBIOUT bit masks and bit positions */ -#define PORTCFG_EBICSOUT_gm 0x03 /* EBI Chip Select Output group mask. */ -#define PORTCFG_EBICSOUT_gp 0 /* EBI Chip Select Output group position. */ -#define PORTCFG_EBICSOUT0_bm (1<<0) /* EBI Chip Select Output bit 0 mask. */ -#define PORTCFG_EBICSOUT0_bp 0 /* EBI Chip Select Output bit 0 position. */ -#define PORTCFG_EBICSOUT1_bm (1<<1) /* EBI Chip Select Output bit 1 mask. */ -#define PORTCFG_EBICSOUT1_bp 1 /* EBI Chip Select Output bit 1 position. */ - -#define PORTCFG_EBIADROUT_gm 0x0C /* EBI Address Output group mask. */ -#define PORTCFG_EBIADROUT_gp 2 /* EBI Address Output group position. */ -#define PORTCFG_EBIADROUT0_bm (1<<2) /* EBI Address Output bit 0 mask. */ -#define PORTCFG_EBIADROUT0_bp 2 /* EBI Address Output bit 0 position. */ -#define PORTCFG_EBIADROUT1_bm (1<<3) /* EBI Address Output bit 1 mask. */ -#define PORTCFG_EBIADROUT1_bp 3 /* EBI Address Output bit 1 position. */ - -/* PORTCFG.EVOUTSEL bit masks and bit positions */ -#define PORTCFG_EVOUTSEL_gm 0x07 /* Event Output Select group mask. */ -#define PORTCFG_EVOUTSEL_gp 0 /* Event Output Select group position. */ -#define PORTCFG_EVOUTSEL0_bm (1<<0) /* Event Output Select bit 0 mask. */ -#define PORTCFG_EVOUTSEL0_bp 0 /* Event Output Select bit 0 position. */ -#define PORTCFG_EVOUTSEL1_bm (1<<1) /* Event Output Select bit 1 mask. */ -#define PORTCFG_EVOUTSEL1_bp 1 /* Event Output Select bit 1 position. */ -#define PORTCFG_EVOUTSEL2_bm (1<<2) /* Event Output Select bit 2 mask. */ -#define PORTCFG_EVOUTSEL2_bp 2 /* Event Output Select bit 2 position. */ - -/* AES - AES Module */ -/* AES.CTRL bit masks and bit positions */ -#define AES_START_bm 0x80 /* Start/Run bit mask. */ -#define AES_START_bp 7 /* Start/Run bit position. */ - -#define AES_AUTO_bm 0x40 /* Auto Start Trigger bit mask. */ -#define AES_AUTO_bp 6 /* Auto Start Trigger bit position. */ - -#define AES_RESET_bm 0x20 /* AES Software Reset bit mask. */ -#define AES_RESET_bp 5 /* AES Software Reset bit position. */ - -#define AES_DECRYPT_bm 0x10 /* Decryption / Direction bit mask. */ -#define AES_DECRYPT_bp 4 /* Decryption / Direction bit position. */ - -#define AES_XOR_bm 0x04 /* State XOR Load Enable bit mask. */ -#define AES_XOR_bp 2 /* State XOR Load Enable bit position. */ - -/* AES.STATUS bit masks and bit positions */ -#define AES_ERROR_bm 0x80 /* AES Error bit mask. */ -#define AES_ERROR_bp 7 /* AES Error bit position. */ - -#define AES_SRIF_bm 0x01 /* State Ready Interrupt Flag bit mask. */ -#define AES_SRIF_bp 0 /* State Ready Interrupt Flag bit position. */ - -/* AES.INTCTRL bit masks and bit positions */ -#define AES_INTLVL_gm 0x03 /* Interrupt level group mask. */ -#define AES_INTLVL_gp 0 /* Interrupt level group position. */ -#define AES_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */ -#define AES_INTLVL0_bp 0 /* Interrupt level bit 0 position. */ -#define AES_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */ -#define AES_INTLVL1_bp 1 /* Interrupt level bit 1 position. */ - -/* CRC - Cyclic Redundancy Checker */ -/* CRC.CTRL bit masks and bit positions */ -#define CRC_RESET_gm 0xC0 /* Reset group mask. */ -#define CRC_RESET_gp 6 /* Reset group position. */ -#define CRC_RESET0_bm (1<<6) /* Reset bit 0 mask. */ -#define CRC_RESET0_bp 6 /* Reset bit 0 position. */ -#define CRC_RESET1_bm (1<<7) /* Reset bit 1 mask. */ -#define CRC_RESET1_bp 7 /* Reset bit 1 position. */ - -#define CRC_CRC32_bm 0x20 /* CRC Mode bit mask. */ -#define CRC_CRC32_bp 5 /* CRC Mode bit position. */ - -#define CRC_SOURCE_gm 0x0F /* Input Source group mask. */ -#define CRC_SOURCE_gp 0 /* Input Source group position. */ -#define CRC_SOURCE0_bm (1<<0) /* Input Source bit 0 mask. */ -#define CRC_SOURCE0_bp 0 /* Input Source bit 0 position. */ -#define CRC_SOURCE1_bm (1<<1) /* Input Source bit 1 mask. */ -#define CRC_SOURCE1_bp 1 /* Input Source bit 1 position. */ -#define CRC_SOURCE2_bm (1<<2) /* Input Source bit 2 mask. */ -#define CRC_SOURCE2_bp 2 /* Input Source bit 2 position. */ -#define CRC_SOURCE3_bm (1<<3) /* Input Source bit 3 mask. */ -#define CRC_SOURCE3_bp 3 /* Input Source bit 3 position. */ - -/* CRC.STATUS bit masks and bit positions */ -#define CRC_ZERO_bm 0x02 /* Zero detection bit mask. */ -#define CRC_ZERO_bp 1 /* Zero detection bit position. */ - -#define CRC_BUSY_bm 0x01 /* Busy bit mask. */ -#define CRC_BUSY_bp 0 /* Busy bit position. */ - -/* DMA - DMA Controller */ -/* DMA_CH.CTRLA bit masks and bit positions */ -#define DMA_CH_ENABLE_bm 0x80 /* Channel Enable bit mask. */ -#define DMA_CH_ENABLE_bp 7 /* Channel Enable bit position. */ - -#define DMA_CH_RESET_bm 0x40 /* Channel Software Reset bit mask. */ -#define DMA_CH_RESET_bp 6 /* Channel Software Reset bit position. */ - -#define DMA_CH_REPEAT_bm 0x20 /* Channel Repeat Mode bit mask. */ -#define DMA_CH_REPEAT_bp 5 /* Channel Repeat Mode bit position. */ - -#define DMA_CH_TRFREQ_bm 0x10 /* Channel Transfer Request bit mask. */ -#define DMA_CH_TRFREQ_bp 4 /* Channel Transfer Request bit position. */ - -#define DMA_CH_SINGLE_bm 0x04 /* Channel Single Shot Data Transfer bit mask. */ -#define DMA_CH_SINGLE_bp 2 /* Channel Single Shot Data Transfer bit position. */ - -#define DMA_CH_BURSTLEN_gm 0x03 /* Channel Transfer Mode group mask. */ -#define DMA_CH_BURSTLEN_gp 0 /* Channel Transfer Mode group position. */ -#define DMA_CH_BURSTLEN0_bm (1<<0) /* Channel Transfer Mode bit 0 mask. */ -#define DMA_CH_BURSTLEN0_bp 0 /* Channel Transfer Mode bit 0 position. */ -#define DMA_CH_BURSTLEN1_bm (1<<1) /* Channel Transfer Mode bit 1 mask. */ -#define DMA_CH_BURSTLEN1_bp 1 /* Channel Transfer Mode bit 1 position. */ - -/* DMA_CH.CTRLB bit masks and bit positions */ -#define DMA_CH_CHBUSY_bm 0x80 /* Block Transfer Busy bit mask. */ -#define DMA_CH_CHBUSY_bp 7 /* Block Transfer Busy bit position. */ - -#define DMA_CH_CHPEND_bm 0x40 /* Block Transfer Pending bit mask. */ -#define DMA_CH_CHPEND_bp 6 /* Block Transfer Pending bit position. */ - -#define DMA_CH_ERRIF_bm 0x20 /* Block Transfer Error Interrupt Flag bit mask. */ -#define DMA_CH_ERRIF_bp 5 /* Block Transfer Error Interrupt Flag bit position. */ - -#define DMA_CH_TRNIF_bm 0x10 /* Transaction Complete Interrup Flag bit mask. */ -#define DMA_CH_TRNIF_bp 4 /* Transaction Complete Interrup Flag bit position. */ - -#define DMA_CH_ERRINTLVL_gm 0x0C /* Transfer Error Interrupt Level group mask. */ -#define DMA_CH_ERRINTLVL_gp 2 /* Transfer Error Interrupt Level group position. */ -#define DMA_CH_ERRINTLVL0_bm (1<<2) /* Transfer Error Interrupt Level bit 0 mask. */ -#define DMA_CH_ERRINTLVL0_bp 2 /* Transfer Error Interrupt Level bit 0 position. */ -#define DMA_CH_ERRINTLVL1_bm (1<<3) /* Transfer Error Interrupt Level bit 1 mask. */ -#define DMA_CH_ERRINTLVL1_bp 3 /* Transfer Error Interrupt Level bit 1 position. */ - -#define DMA_CH_TRNINTLVL_gm 0x03 /* Transaction Complete Interrupt Level group mask. */ -#define DMA_CH_TRNINTLVL_gp 0 /* Transaction Complete Interrupt Level group position. */ -#define DMA_CH_TRNINTLVL0_bm (1<<0) /* Transaction Complete Interrupt Level bit 0 mask. */ -#define DMA_CH_TRNINTLVL0_bp 0 /* Transaction Complete Interrupt Level bit 0 position. */ -#define DMA_CH_TRNINTLVL1_bm (1<<1) /* Transaction Complete Interrupt Level bit 1 mask. */ -#define DMA_CH_TRNINTLVL1_bp 1 /* Transaction Complete Interrupt Level bit 1 position. */ - -/* DMA_CH.ADDRCTRL bit masks and bit positions */ -#define DMA_CH_SRCRELOAD_gm 0xC0 /* Channel Source Address Reload group mask. */ -#define DMA_CH_SRCRELOAD_gp 6 /* Channel Source Address Reload group position. */ -#define DMA_CH_SRCRELOAD0_bm (1<<6) /* Channel Source Address Reload bit 0 mask. */ -#define DMA_CH_SRCRELOAD0_bp 6 /* Channel Source Address Reload bit 0 position. */ -#define DMA_CH_SRCRELOAD1_bm (1<<7) /* Channel Source Address Reload bit 1 mask. */ -#define DMA_CH_SRCRELOAD1_bp 7 /* Channel Source Address Reload bit 1 position. */ - -#define DMA_CH_SRCDIR_gm 0x30 /* Channel Source Address Mode group mask. */ -#define DMA_CH_SRCDIR_gp 4 /* Channel Source Address Mode group position. */ -#define DMA_CH_SRCDIR0_bm (1<<4) /* Channel Source Address Mode bit 0 mask. */ -#define DMA_CH_SRCDIR0_bp 4 /* Channel Source Address Mode bit 0 position. */ -#define DMA_CH_SRCDIR1_bm (1<<5) /* Channel Source Address Mode bit 1 mask. */ -#define DMA_CH_SRCDIR1_bp 5 /* Channel Source Address Mode bit 1 position. */ - -#define DMA_CH_DESTRELOAD_gm 0x0C /* Channel Destination Address Reload group mask. */ -#define DMA_CH_DESTRELOAD_gp 2 /* Channel Destination Address Reload group position. */ -#define DMA_CH_DESTRELOAD0_bm (1<<2) /* Channel Destination Address Reload bit 0 mask. */ -#define DMA_CH_DESTRELOAD0_bp 2 /* Channel Destination Address Reload bit 0 position. */ -#define DMA_CH_DESTRELOAD1_bm (1<<3) /* Channel Destination Address Reload bit 1 mask. */ -#define DMA_CH_DESTRELOAD1_bp 3 /* Channel Destination Address Reload bit 1 position. */ - -#define DMA_CH_DESTDIR_gm 0x03 /* Channel Destination Address Mode group mask. */ -#define DMA_CH_DESTDIR_gp 0 /* Channel Destination Address Mode group position. */ -#define DMA_CH_DESTDIR0_bm (1<<0) /* Channel Destination Address Mode bit 0 mask. */ -#define DMA_CH_DESTDIR0_bp 0 /* Channel Destination Address Mode bit 0 position. */ -#define DMA_CH_DESTDIR1_bm (1<<1) /* Channel Destination Address Mode bit 1 mask. */ -#define DMA_CH_DESTDIR1_bp 1 /* Channel Destination Address Mode bit 1 position. */ - -/* DMA_CH.TRIGSRC bit masks and bit positions */ -#define DMA_CH_TRIGSRC_gm 0xFF /* Channel Trigger Source group mask. */ -#define DMA_CH_TRIGSRC_gp 0 /* Channel Trigger Source group position. */ -#define DMA_CH_TRIGSRC0_bm (1<<0) /* Channel Trigger Source bit 0 mask. */ -#define DMA_CH_TRIGSRC0_bp 0 /* Channel Trigger Source bit 0 position. */ -#define DMA_CH_TRIGSRC1_bm (1<<1) /* Channel Trigger Source bit 1 mask. */ -#define DMA_CH_TRIGSRC1_bp 1 /* Channel Trigger Source bit 1 position. */ -#define DMA_CH_TRIGSRC2_bm (1<<2) /* Channel Trigger Source bit 2 mask. */ -#define DMA_CH_TRIGSRC2_bp 2 /* Channel Trigger Source bit 2 position. */ -#define DMA_CH_TRIGSRC3_bm (1<<3) /* Channel Trigger Source bit 3 mask. */ -#define DMA_CH_TRIGSRC3_bp 3 /* Channel Trigger Source bit 3 position. */ -#define DMA_CH_TRIGSRC4_bm (1<<4) /* Channel Trigger Source bit 4 mask. */ -#define DMA_CH_TRIGSRC4_bp 4 /* Channel Trigger Source bit 4 position. */ -#define DMA_CH_TRIGSRC5_bm (1<<5) /* Channel Trigger Source bit 5 mask. */ -#define DMA_CH_TRIGSRC5_bp 5 /* Channel Trigger Source bit 5 position. */ -#define DMA_CH_TRIGSRC6_bm (1<<6) /* Channel Trigger Source bit 6 mask. */ -#define DMA_CH_TRIGSRC6_bp 6 /* Channel Trigger Source bit 6 position. */ -#define DMA_CH_TRIGSRC7_bm (1<<7) /* Channel Trigger Source bit 7 mask. */ -#define DMA_CH_TRIGSRC7_bp 7 /* Channel Trigger Source bit 7 position. */ - -/* DMA.CTRL bit masks and bit positions */ -#define DMA_ENABLE_bm 0x80 /* Enable bit mask. */ -#define DMA_ENABLE_bp 7 /* Enable bit position. */ - -#define DMA_RESET_bm 0x40 /* Software Reset bit mask. */ -#define DMA_RESET_bp 6 /* Software Reset bit position. */ - -#define DMA_DBUFMODE_bm 0x04 /* Double Buffering Mode bit mask. */ -#define DMA_DBUFMODE_bp 2 /* Double Buffering Mode bit position. */ - -#define DMA_PRIMODE_bm 0x01 /* Channel Priority Mode bit mask. */ -#define DMA_PRIMODE_bp 0 /* Channel Priority Mode bit position. */ - -/* DMA.INTFLAGS bit masks and bit positions */ -#define DMA_CH1ERRIF_bm 0x20 /* Channel 1 Block Transfer Error Interrupt Flag bit mask. */ -#define DMA_CH1ERRIF_bp 5 /* Channel 1 Block Transfer Error Interrupt Flag bit position. */ - -#define DMA_CH0ERRIF_bm 0x10 /* Channel 0 Block Transfer Error Interrupt Flag bit mask. */ -#define DMA_CH0ERRIF_bp 4 /* Channel 0 Block Transfer Error Interrupt Flag bit position. */ - -#define DMA_CH1TRNIF_bm 0x02 /* Channel 1 Transaction Complete Interrupt Flag bit mask. */ -#define DMA_CH1TRNIF_bp 1 /* Channel 1 Transaction Complete Interrupt Flag bit position. */ - -#define DMA_CH0TRNIF_bm 0x01 /* Channel 0 Transaction Complete Interrupt Flag bit mask. */ -#define DMA_CH0TRNIF_bp 0 /* Channel 0 Transaction Complete Interrupt Flag bit position. */ - -/* DMA.STATUS bit masks and bit positions */ -#define DMA_CH1BUSY_bm 0x20 /* Channel 1 Block Transfer Busy bit mask. */ -#define DMA_CH1BUSY_bp 5 /* Channel 1 Block Transfer Busy bit position. */ - -#define DMA_CH0BUSY_bm 0x10 /* Channel 0 Block Transfer Busy bit mask. */ -#define DMA_CH0BUSY_bp 4 /* Channel 0 Block Transfer Busy bit position. */ - -#define DMA_CH1PEND_bm 0x02 /* Channel 1 Block Transfer Pending bit mask. */ -#define DMA_CH1PEND_bp 1 /* Channel 1 Block Transfer Pending bit position. */ - -#define DMA_CH0PEND_bm 0x01 /* Channel 0 Block Transfer Pending bit mask. */ -#define DMA_CH0PEND_bp 0 /* Channel 0 Block Transfer Pending bit position. */ - -/* EVSYS - Event System */ -/* EVSYS.CH0MUX bit masks and bit positions */ -#define EVSYS_CHMUX_gm 0xFF /* Event Channel 0 Multiplexer group mask. */ -#define EVSYS_CHMUX_gp 0 /* Event Channel 0 Multiplexer group position. */ -#define EVSYS_CHMUX0_bm (1<<0) /* Event Channel 0 Multiplexer bit 0 mask. */ -#define EVSYS_CHMUX0_bp 0 /* Event Channel 0 Multiplexer bit 0 position. */ -#define EVSYS_CHMUX1_bm (1<<1) /* Event Channel 0 Multiplexer bit 1 mask. */ -#define EVSYS_CHMUX1_bp 1 /* Event Channel 0 Multiplexer bit 1 position. */ -#define EVSYS_CHMUX2_bm (1<<2) /* Event Channel 0 Multiplexer bit 2 mask. */ -#define EVSYS_CHMUX2_bp 2 /* Event Channel 0 Multiplexer bit 2 position. */ -#define EVSYS_CHMUX3_bm (1<<3) /* Event Channel 0 Multiplexer bit 3 mask. */ -#define EVSYS_CHMUX3_bp 3 /* Event Channel 0 Multiplexer bit 3 position. */ -#define EVSYS_CHMUX4_bm (1<<4) /* Event Channel 0 Multiplexer bit 4 mask. */ -#define EVSYS_CHMUX4_bp 4 /* Event Channel 0 Multiplexer bit 4 position. */ -#define EVSYS_CHMUX5_bm (1<<5) /* Event Channel 0 Multiplexer bit 5 mask. */ -#define EVSYS_CHMUX5_bp 5 /* Event Channel 0 Multiplexer bit 5 position. */ -#define EVSYS_CHMUX6_bm (1<<6) /* Event Channel 0 Multiplexer bit 6 mask. */ -#define EVSYS_CHMUX6_bp 6 /* Event Channel 0 Multiplexer bit 6 position. */ -#define EVSYS_CHMUX7_bm (1<<7) /* Event Channel 0 Multiplexer bit 7 mask. */ -#define EVSYS_CHMUX7_bp 7 /* Event Channel 0 Multiplexer bit 7 position. */ - -/* EVSYS.CH1MUX bit masks and bit positions */ -/* EVSYS_CHMUX Predefined. */ -/* EVSYS_CHMUX Predefined. */ - -/* EVSYS.CH2MUX bit masks and bit positions */ -/* EVSYS_CHMUX Predefined. */ -/* EVSYS_CHMUX Predefined. */ - -/* EVSYS.CH3MUX bit masks and bit positions */ -/* EVSYS_CHMUX Predefined. */ -/* EVSYS_CHMUX Predefined. */ - -/* EVSYS.CH0CTRL bit masks and bit positions */ -#define EVSYS_QDIRM_gm 0x60 /* Quadrature Decoder Index Recognition Mode group mask. */ -#define EVSYS_QDIRM_gp 5 /* Quadrature Decoder Index Recognition Mode group position. */ -#define EVSYS_QDIRM0_bm (1<<5) /* Quadrature Decoder Index Recognition Mode bit 0 mask. */ -#define EVSYS_QDIRM0_bp 5 /* Quadrature Decoder Index Recognition Mode bit 0 position. */ -#define EVSYS_QDIRM1_bm (1<<6) /* Quadrature Decoder Index Recognition Mode bit 1 mask. */ -#define EVSYS_QDIRM1_bp 6 /* Quadrature Decoder Index Recognition Mode bit 1 position. */ - -#define EVSYS_QDIEN_bm 0x10 /* Quadrature Decoder Index Enable bit mask. */ -#define EVSYS_QDIEN_bp 4 /* Quadrature Decoder Index Enable bit position. */ - -#define EVSYS_QDEN_bm 0x08 /* Quadrature Decoder Enable bit mask. */ -#define EVSYS_QDEN_bp 3 /* Quadrature Decoder Enable bit position. */ - -#define EVSYS_DIGFILT_gm 0x07 /* Digital Filter group mask. */ -#define EVSYS_DIGFILT_gp 0 /* Digital Filter group position. */ -#define EVSYS_DIGFILT0_bm (1<<0) /* Digital Filter bit 0 mask. */ -#define EVSYS_DIGFILT0_bp 0 /* Digital Filter bit 0 position. */ -#define EVSYS_DIGFILT1_bm (1<<1) /* Digital Filter bit 1 mask. */ -#define EVSYS_DIGFILT1_bp 1 /* Digital Filter bit 1 position. */ -#define EVSYS_DIGFILT2_bm (1<<2) /* Digital Filter bit 2 mask. */ -#define EVSYS_DIGFILT2_bp 2 /* Digital Filter bit 2 position. */ - -/* EVSYS.CH1CTRL bit masks and bit positions */ -/* EVSYS_DIGFILT Predefined. */ -/* EVSYS_DIGFILT Predefined. */ - -/* EVSYS.CH2CTRL bit masks and bit positions */ -/* EVSYS_DIGFILT Predefined. */ -/* EVSYS_DIGFILT Predefined. */ - -/* EVSYS.CH3CTRL bit masks and bit positions */ -/* EVSYS_DIGFILT Predefined. */ -/* EVSYS_DIGFILT Predefined. */ - -/* NVM - Non Volatile Memory Controller */ -/* NVM.CMD bit masks and bit positions */ -#define NVM_CMD_gm 0x7F /* Command group mask. */ -#define NVM_CMD_gp 0 /* Command group position. */ -#define NVM_CMD0_bm (1<<0) /* Command bit 0 mask. */ -#define NVM_CMD0_bp 0 /* Command bit 0 position. */ -#define NVM_CMD1_bm (1<<1) /* Command bit 1 mask. */ -#define NVM_CMD1_bp 1 /* Command bit 1 position. */ -#define NVM_CMD2_bm (1<<2) /* Command bit 2 mask. */ -#define NVM_CMD2_bp 2 /* Command bit 2 position. */ -#define NVM_CMD3_bm (1<<3) /* Command bit 3 mask. */ -#define NVM_CMD3_bp 3 /* Command bit 3 position. */ -#define NVM_CMD4_bm (1<<4) /* Command bit 4 mask. */ -#define NVM_CMD4_bp 4 /* Command bit 4 position. */ -#define NVM_CMD5_bm (1<<5) /* Command bit 5 mask. */ -#define NVM_CMD5_bp 5 /* Command bit 5 position. */ -#define NVM_CMD6_bm (1<<6) /* Command bit 6 mask. */ -#define NVM_CMD6_bp 6 /* Command bit 6 position. */ - -/* NVM.CTRLA bit masks and bit positions */ -#define NVM_CMDEX_bm 0x01 /* Command Execute bit mask. */ -#define NVM_CMDEX_bp 0 /* Command Execute bit position. */ - -/* NVM.CTRLB bit masks and bit positions */ -#define NVM_EEMAPEN_bm 0x08 /* EEPROM Mapping Enable bit mask. */ -#define NVM_EEMAPEN_bp 3 /* EEPROM Mapping Enable bit position. */ - -#define NVM_FPRM_bm 0x04 /* Flash Power Reduction Enable bit mask. */ -#define NVM_FPRM_bp 2 /* Flash Power Reduction Enable bit position. */ - -#define NVM_EPRM_bm 0x02 /* EEPROM Power Reduction Enable bit mask. */ -#define NVM_EPRM_bp 1 /* EEPROM Power Reduction Enable bit position. */ - -#define NVM_SPMLOCK_bm 0x01 /* SPM Lock bit mask. */ -#define NVM_SPMLOCK_bp 0 /* SPM Lock bit position. */ - -/* NVM.INTCTRL bit masks and bit positions */ -#define NVM_SPMLVL_gm 0x0C /* SPM Interrupt Level group mask. */ -#define NVM_SPMLVL_gp 2 /* SPM Interrupt Level group position. */ -#define NVM_SPMLVL0_bm (1<<2) /* SPM Interrupt Level bit 0 mask. */ -#define NVM_SPMLVL0_bp 2 /* SPM Interrupt Level bit 0 position. */ -#define NVM_SPMLVL1_bm (1<<3) /* SPM Interrupt Level bit 1 mask. */ -#define NVM_SPMLVL1_bp 3 /* SPM Interrupt Level bit 1 position. */ - -#define NVM_EELVL_gm 0x03 /* EEPROM Interrupt Level group mask. */ -#define NVM_EELVL_gp 0 /* EEPROM Interrupt Level group position. */ -#define NVM_EELVL0_bm (1<<0) /* EEPROM Interrupt Level bit 0 mask. */ -#define NVM_EELVL0_bp 0 /* EEPROM Interrupt Level bit 0 position. */ -#define NVM_EELVL1_bm (1<<1) /* EEPROM Interrupt Level bit 1 mask. */ -#define NVM_EELVL1_bp 1 /* EEPROM Interrupt Level bit 1 position. */ - -/* NVM.STATUS bit masks and bit positions */ -#define NVM_NVMBUSY_bm 0x80 /* Non-volatile Memory Busy bit mask. */ -#define NVM_NVMBUSY_bp 7 /* Non-volatile Memory Busy bit position. */ - -#define NVM_FBUSY_bm 0x40 /* Flash Memory Busy bit mask. */ -#define NVM_FBUSY_bp 6 /* Flash Memory Busy bit position. */ - -#define NVM_EELOAD_bm 0x02 /* EEPROM Page Buffer Active Loading bit mask. */ -#define NVM_EELOAD_bp 1 /* EEPROM Page Buffer Active Loading bit position. */ - -#define NVM_FLOAD_bm 0x01 /* Flash Page Buffer Active Loading bit mask. */ -#define NVM_FLOAD_bp 0 /* Flash Page Buffer Active Loading bit position. */ - -/* NVM.LOCKBITS bit masks and bit positions */ -#define NVM_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ -#define NVM_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ -#define NVM_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ -#define NVM_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ -#define NVM_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ -#define NVM_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ - -#define NVM_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ -#define NVM_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ -#define NVM_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ -#define NVM_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ -#define NVM_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ -#define NVM_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ - -#define NVM_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ -#define NVM_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ -#define NVM_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ -#define NVM_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ -#define NVM_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ -#define NVM_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ - -#define NVM_LB_gm 0x03 /* Lock Bits group mask. */ -#define NVM_LB_gp 0 /* Lock Bits group position. */ -#define NVM_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ -#define NVM_LB0_bp 0 /* Lock Bits bit 0 position. */ -#define NVM_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ -#define NVM_LB1_bp 1 /* Lock Bits bit 1 position. */ - -/* ADC - Analog/Digital Converter */ -/* ADC_CH.CTRL bit masks and bit positions */ -#define ADC_CH_START_bm 0x80 /* Channel Start Conversion bit mask. */ -#define ADC_CH_START_bp 7 /* Channel Start Conversion bit position. */ - -#define ADC_CH_GAIN_gm 0x1C /* Gain Factor group mask. */ -#define ADC_CH_GAIN_gp 2 /* Gain Factor group position. */ -#define ADC_CH_GAIN0_bm (1<<2) /* Gain Factor bit 0 mask. */ -#define ADC_CH_GAIN0_bp 2 /* Gain Factor bit 0 position. */ -#define ADC_CH_GAIN1_bm (1<<3) /* Gain Factor bit 1 mask. */ -#define ADC_CH_GAIN1_bp 3 /* Gain Factor bit 1 position. */ -#define ADC_CH_GAIN2_bm (1<<4) /* Gain Factor bit 2 mask. */ -#define ADC_CH_GAIN2_bp 4 /* Gain Factor bit 2 position. */ - -#define ADC_CH_INPUTMODE_gm 0x03 /* Input Mode Select group mask. */ -#define ADC_CH_INPUTMODE_gp 0 /* Input Mode Select group position. */ -#define ADC_CH_INPUTMODE0_bm (1<<0) /* Input Mode Select bit 0 mask. */ -#define ADC_CH_INPUTMODE0_bp 0 /* Input Mode Select bit 0 position. */ -#define ADC_CH_INPUTMODE1_bm (1<<1) /* Input Mode Select bit 1 mask. */ -#define ADC_CH_INPUTMODE1_bp 1 /* Input Mode Select bit 1 position. */ - -/* ADC_CH.MUXCTRL bit masks and bit positions */ -#define ADC_CH_MUXPOS_gm 0x78 /* MUX selection on Positive ADC input group mask. */ -#define ADC_CH_MUXPOS_gp 3 /* MUX selection on Positive ADC input group position. */ -#define ADC_CH_MUXPOS0_bm (1<<3) /* MUX selection on Positive ADC input bit 0 mask. */ -#define ADC_CH_MUXPOS0_bp 3 /* MUX selection on Positive ADC input bit 0 position. */ -#define ADC_CH_MUXPOS1_bm (1<<4) /* MUX selection on Positive ADC input bit 1 mask. */ -#define ADC_CH_MUXPOS1_bp 4 /* MUX selection on Positive ADC input bit 1 position. */ -#define ADC_CH_MUXPOS2_bm (1<<5) /* MUX selection on Positive ADC input bit 2 mask. */ -#define ADC_CH_MUXPOS2_bp 5 /* MUX selection on Positive ADC input bit 2 position. */ -#define ADC_CH_MUXPOS3_bm (1<<6) /* MUX selection on Positive ADC input bit 3 mask. */ -#define ADC_CH_MUXPOS3_bp 6 /* MUX selection on Positive ADC input bit 3 position. */ - -#define ADC_CH_MUXINT_gm 0x78 /* MUX selection on Internal ADC input group mask. */ -#define ADC_CH_MUXINT_gp 3 /* MUX selection on Internal ADC input group position. */ -#define ADC_CH_MUXINT0_bm (1<<3) /* MUX selection on Internal ADC input bit 0 mask. */ -#define ADC_CH_MUXINT0_bp 3 /* MUX selection on Internal ADC input bit 0 position. */ -#define ADC_CH_MUXINT1_bm (1<<4) /* MUX selection on Internal ADC input bit 1 mask. */ -#define ADC_CH_MUXINT1_bp 4 /* MUX selection on Internal ADC input bit 1 position. */ -#define ADC_CH_MUXINT2_bm (1<<5) /* MUX selection on Internal ADC input bit 2 mask. */ -#define ADC_CH_MUXINT2_bp 5 /* MUX selection on Internal ADC input bit 2 position. */ -#define ADC_CH_MUXINT3_bm (1<<6) /* MUX selection on Internal ADC input bit 3 mask. */ -#define ADC_CH_MUXINT3_bp 6 /* MUX selection on Internal ADC input bit 3 position. */ - -#define ADC_CH_MUXNEG_gm 0x03 /* MUX selection on Negative ADC input group mask. */ -#define ADC_CH_MUXNEG_gp 0 /* MUX selection on Negative ADC input group position. */ -#define ADC_CH_MUXNEG0_bm (1<<0) /* MUX selection on Negative ADC input bit 0 mask. */ -#define ADC_CH_MUXNEG0_bp 0 /* MUX selection on Negative ADC input bit 0 position. */ -#define ADC_CH_MUXNEG1_bm (1<<1) /* MUX selection on Negative ADC input bit 1 mask. */ -#define ADC_CH_MUXNEG1_bp 1 /* MUX selection on Negative ADC input bit 1 position. */ - -/* ADC_CH.INTCTRL bit masks and bit positions */ -#define ADC_CH_INTMODE_gm 0x0C /* Interrupt Mode group mask. */ -#define ADC_CH_INTMODE_gp 2 /* Interrupt Mode group position. */ -#define ADC_CH_INTMODE0_bm (1<<2) /* Interrupt Mode bit 0 mask. */ -#define ADC_CH_INTMODE0_bp 2 /* Interrupt Mode bit 0 position. */ -#define ADC_CH_INTMODE1_bm (1<<3) /* Interrupt Mode bit 1 mask. */ -#define ADC_CH_INTMODE1_bp 3 /* Interrupt Mode bit 1 position. */ - -#define ADC_CH_INTLVL_gm 0x03 /* Interrupt Level group mask. */ -#define ADC_CH_INTLVL_gp 0 /* Interrupt Level group position. */ -#define ADC_CH_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */ -#define ADC_CH_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */ -#define ADC_CH_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ -#define ADC_CH_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */ - -/* ADC_CH.INTFLAGS bit masks and bit positions */ -#define ADC_CH_CHIF_bm 0x01 /* Channel Interrupt Flag bit mask. */ -#define ADC_CH_CHIF_bp 0 /* Channel Interrupt Flag bit position. */ - -/* ADC_CH.SCAN bit masks and bit positions */ -#define ADC_CH_OFFSET_gm 0xF0 /* Positive MUX setting offset group mask. */ -#define ADC_CH_OFFSET_gp 4 /* Positive MUX setting offset group position. */ -#define ADC_CH_OFFSET0_bm (1<<4) /* Positive MUX setting offset bit 0 mask. */ -#define ADC_CH_OFFSET0_bp 4 /* Positive MUX setting offset bit 0 position. */ -#define ADC_CH_OFFSET1_bm (1<<5) /* Positive MUX setting offset bit 1 mask. */ -#define ADC_CH_OFFSET1_bp 5 /* Positive MUX setting offset bit 1 position. */ -#define ADC_CH_OFFSET2_bm (1<<6) /* Positive MUX setting offset bit 2 mask. */ -#define ADC_CH_OFFSET2_bp 6 /* Positive MUX setting offset bit 2 position. */ -#define ADC_CH_OFFSET3_bm (1<<7) /* Positive MUX setting offset bit 3 mask. */ -#define ADC_CH_OFFSET3_bp 7 /* Positive MUX setting offset bit 3 position. */ - -#define ADC_CH_COUNT_gm 0x0F /* Number of Channels included in scan group mask. */ -#define ADC_CH_COUNT_gp 0 /* Number of Channels included in scan group position. */ -#define ADC_CH_COUNT0_bm (1<<0) /* Number of Channels included in scan bit 0 mask. */ -#define ADC_CH_COUNT0_bp 0 /* Number of Channels included in scan bit 0 position. */ -#define ADC_CH_COUNT1_bm (1<<1) /* Number of Channels included in scan bit 1 mask. */ -#define ADC_CH_COUNT1_bp 1 /* Number of Channels included in scan bit 1 position. */ -#define ADC_CH_COUNT2_bm (1<<2) /* Number of Channels included in scan bit 2 mask. */ -#define ADC_CH_COUNT2_bp 2 /* Number of Channels included in scan bit 2 position. */ -#define ADC_CH_COUNT3_bm (1<<3) /* Number of Channels included in scan bit 3 mask. */ -#define ADC_CH_COUNT3_bp 3 /* Number of Channels included in scan bit 3 position. */ - -/* ADC.CTRLA bit masks and bit positions */ -#define ADC_CH0START_bm 0x04 /* Channel 0 Start Conversion bit mask. */ -#define ADC_CH0START_bp 2 /* Channel 0 Start Conversion bit position. */ - -#define ADC_FLUSH_bm 0x02 /* ADC Flush bit mask. */ -#define ADC_FLUSH_bp 1 /* ADC Flush bit position. */ - -#define ADC_ENABLE_bm 0x01 /* Enable ADC bit mask. */ -#define ADC_ENABLE_bp 0 /* Enable ADC bit position. */ - -/* ADC.CTRLB bit masks and bit positions */ -#define ADC_CURRLIMIT_gm 0x60 /* Current limit group mask. */ -#define ADC_CURRLIMIT_gp 5 /* Current limit group position. */ -#define ADC_CURRLIMIT0_bm (1<<5) /* Current limit bit 0 mask. */ -#define ADC_CURRLIMIT0_bp 5 /* Current limit bit 0 position. */ -#define ADC_CURRLIMIT1_bm (1<<6) /* Current limit bit 1 mask. */ -#define ADC_CURRLIMIT1_bp 6 /* Current limit bit 1 position. */ - -#define ADC_CONMODE_bm 0x10 /* Conversion Mode bit mask. */ -#define ADC_CONMODE_bp 4 /* Conversion Mode bit position. */ - -#define ADC_FREERUN_bm 0x08 /* Free Running Mode Enable bit mask. */ -#define ADC_FREERUN_bp 3 /* Free Running Mode Enable bit position. */ - -#define ADC_RESOLUTION_gm 0x06 /* Result Resolution group mask. */ -#define ADC_RESOLUTION_gp 1 /* Result Resolution group position. */ -#define ADC_RESOLUTION0_bm (1<<1) /* Result Resolution bit 0 mask. */ -#define ADC_RESOLUTION0_bp 1 /* Result Resolution bit 0 position. */ -#define ADC_RESOLUTION1_bm (1<<2) /* Result Resolution bit 1 mask. */ -#define ADC_RESOLUTION1_bp 2 /* Result Resolution bit 1 position. */ - -/* ADC.REFCTRL bit masks and bit positions */ -#define ADC_REFSEL_gm 0x70 /* Reference Selection group mask. */ -#define ADC_REFSEL_gp 4 /* Reference Selection group position. */ -#define ADC_REFSEL0_bm (1<<4) /* Reference Selection bit 0 mask. */ -#define ADC_REFSEL0_bp 4 /* Reference Selection bit 0 position. */ -#define ADC_REFSEL1_bm (1<<5) /* Reference Selection bit 1 mask. */ -#define ADC_REFSEL1_bp 5 /* Reference Selection bit 1 position. */ -#define ADC_REFSEL2_bm (1<<6) /* Reference Selection bit 2 mask. */ -#define ADC_REFSEL2_bp 6 /* Reference Selection bit 2 position. */ - -#define ADC_BANDGAP_bm 0x02 /* Bandgap enable bit mask. */ -#define ADC_BANDGAP_bp 1 /* Bandgap enable bit position. */ - -#define ADC_TEMPREF_bm 0x01 /* Temperature Reference Enable bit mask. */ -#define ADC_TEMPREF_bp 0 /* Temperature Reference Enable bit position. */ - -/* ADC.EVCTRL bit masks and bit positions */ -#define ADC_EVSEL_gm 0x18 /* Event Input Select group mask. */ -#define ADC_EVSEL_gp 3 /* Event Input Select group position. */ -#define ADC_EVSEL0_bm (1<<3) /* Event Input Select bit 0 mask. */ -#define ADC_EVSEL0_bp 3 /* Event Input Select bit 0 position. */ -#define ADC_EVSEL1_bm (1<<4) /* Event Input Select bit 1 mask. */ -#define ADC_EVSEL1_bp 4 /* Event Input Select bit 1 position. */ - -#define ADC_EVACT_gm 0x07 /* Event Action Select group mask. */ -#define ADC_EVACT_gp 0 /* Event Action Select group position. */ -#define ADC_EVACT0_bm (1<<0) /* Event Action Select bit 0 mask. */ -#define ADC_EVACT0_bp 0 /* Event Action Select bit 0 position. */ -#define ADC_EVACT1_bm (1<<1) /* Event Action Select bit 1 mask. */ -#define ADC_EVACT1_bp 1 /* Event Action Select bit 1 position. */ -#define ADC_EVACT2_bm (1<<2) /* Event Action Select bit 2 mask. */ -#define ADC_EVACT2_bp 2 /* Event Action Select bit 2 position. */ - -/* ADC.PRESCALER bit masks and bit positions */ -#define ADC_PRESCALER_gm 0x07 /* Clock Prescaler Selection group mask. */ -#define ADC_PRESCALER_gp 0 /* Clock Prescaler Selection group position. */ -#define ADC_PRESCALER0_bm (1<<0) /* Clock Prescaler Selection bit 0 mask. */ -#define ADC_PRESCALER0_bp 0 /* Clock Prescaler Selection bit 0 position. */ -#define ADC_PRESCALER1_bm (1<<1) /* Clock Prescaler Selection bit 1 mask. */ -#define ADC_PRESCALER1_bp 1 /* Clock Prescaler Selection bit 1 position. */ -#define ADC_PRESCALER2_bm (1<<2) /* Clock Prescaler Selection bit 2 mask. */ -#define ADC_PRESCALER2_bp 2 /* Clock Prescaler Selection bit 2 position. */ - -/* ADC.INTFLAGS bit masks and bit positions */ -#define ADC_CH0IF_bm 0x01 /* Channel 0 Interrupt Flag bit mask. */ -#define ADC_CH0IF_bp 0 /* Channel 0 Interrupt Flag bit position. */ - -/* ADC.SAMPCTRL bit masks and bit positions */ -#define ADC_SAMPVAL_gm 0x3F /* Sampling time control register group mask. */ -#define ADC_SAMPVAL_gp 0 /* Sampling time control register group position. */ -#define ADC_SAMPVAL0_bm (1<<0) /* Sampling time control register bit 0 mask. */ -#define ADC_SAMPVAL0_bp 0 /* Sampling time control register bit 0 position. */ -#define ADC_SAMPVAL1_bm (1<<1) /* Sampling time control register bit 1 mask. */ -#define ADC_SAMPVAL1_bp 1 /* Sampling time control register bit 1 position. */ -#define ADC_SAMPVAL2_bm (1<<2) /* Sampling time control register bit 2 mask. */ -#define ADC_SAMPVAL2_bp 2 /* Sampling time control register bit 2 position. */ -#define ADC_SAMPVAL3_bm (1<<3) /* Sampling time control register bit 3 mask. */ -#define ADC_SAMPVAL3_bp 3 /* Sampling time control register bit 3 position. */ -#define ADC_SAMPVAL4_bm (1<<4) /* Sampling time control register bit 4 mask. */ -#define ADC_SAMPVAL4_bp 4 /* Sampling time control register bit 4 position. */ -#define ADC_SAMPVAL5_bm (1<<5) /* Sampling time control register bit 5 mask. */ -#define ADC_SAMPVAL5_bp 5 /* Sampling time control register bit 5 position. */ - -/* AC - Analog Comparator */ -/* AC.AC0CTRL bit masks and bit positions */ -#define AC_INTMODE_gm 0xC0 /* Interrupt Mode group mask. */ -#define AC_INTMODE_gp 6 /* Interrupt Mode group position. */ -#define AC_INTMODE0_bm (1<<6) /* Interrupt Mode bit 0 mask. */ -#define AC_INTMODE0_bp 6 /* Interrupt Mode bit 0 position. */ -#define AC_INTMODE1_bm (1<<7) /* Interrupt Mode bit 1 mask. */ -#define AC_INTMODE1_bp 7 /* Interrupt Mode bit 1 position. */ - -#define AC_INTLVL_gm 0x30 /* Interrupt Level group mask. */ -#define AC_INTLVL_gp 4 /* Interrupt Level group position. */ -#define AC_INTLVL0_bm (1<<4) /* Interrupt Level bit 0 mask. */ -#define AC_INTLVL0_bp 4 /* Interrupt Level bit 0 position. */ -#define AC_INTLVL1_bm (1<<5) /* Interrupt Level bit 1 mask. */ -#define AC_INTLVL1_bp 5 /* Interrupt Level bit 1 position. */ - -#define AC_HYSMODE_gm 0x06 /* Hysteresis Mode group mask. */ -#define AC_HYSMODE_gp 1 /* Hysteresis Mode group position. */ -#define AC_HYSMODE0_bm (1<<1) /* Hysteresis Mode bit 0 mask. */ -#define AC_HYSMODE0_bp 1 /* Hysteresis Mode bit 0 position. */ -#define AC_HYSMODE1_bm (1<<2) /* Hysteresis Mode bit 1 mask. */ -#define AC_HYSMODE1_bp 2 /* Hysteresis Mode bit 1 position. */ - -#define AC_ENABLE_bm 0x01 /* Enable bit mask. */ -#define AC_ENABLE_bp 0 /* Enable bit position. */ - -/* AC.AC1CTRL bit masks and bit positions */ -/* AC_INTMODE Predefined. */ -/* AC_INTMODE Predefined. */ - -/* AC_INTLVL Predefined. */ -/* AC_INTLVL Predefined. */ - -/* AC_HYSMODE Predefined. */ -/* AC_HYSMODE Predefined. */ - -/* AC_ENABLE Predefined. */ -/* AC_ENABLE Predefined. */ - -/* AC.AC0MUXCTRL bit masks and bit positions */ -#define AC_MUXPOS_gm 0x38 /* MUX Positive Input group mask. */ -#define AC_MUXPOS_gp 3 /* MUX Positive Input group position. */ -#define AC_MUXPOS0_bm (1<<3) /* MUX Positive Input bit 0 mask. */ -#define AC_MUXPOS0_bp 3 /* MUX Positive Input bit 0 position. */ -#define AC_MUXPOS1_bm (1<<4) /* MUX Positive Input bit 1 mask. */ -#define AC_MUXPOS1_bp 4 /* MUX Positive Input bit 1 position. */ -#define AC_MUXPOS2_bm (1<<5) /* MUX Positive Input bit 2 mask. */ -#define AC_MUXPOS2_bp 5 /* MUX Positive Input bit 2 position. */ - -#define AC_MUXNEG_gm 0x07 /* MUX Negative Input group mask. */ -#define AC_MUXNEG_gp 0 /* MUX Negative Input group position. */ -#define AC_MUXNEG0_bm (1<<0) /* MUX Negative Input bit 0 mask. */ -#define AC_MUXNEG0_bp 0 /* MUX Negative Input bit 0 position. */ -#define AC_MUXNEG1_bm (1<<1) /* MUX Negative Input bit 1 mask. */ -#define AC_MUXNEG1_bp 1 /* MUX Negative Input bit 1 position. */ -#define AC_MUXNEG2_bm (1<<2) /* MUX Negative Input bit 2 mask. */ -#define AC_MUXNEG2_bp 2 /* MUX Negative Input bit 2 position. */ - -/* AC.AC1MUXCTRL bit masks and bit positions */ -/* AC_MUXPOS Predefined. */ -/* AC_MUXPOS Predefined. */ - -/* AC_MUXNEG Predefined. */ -/* AC_MUXNEG Predefined. */ - -/* AC.CTRLA bit masks and bit positions */ -#define AC_AC1OUT_bm 0x02 /* Analog Comparator 1 Output Enable bit mask. */ -#define AC_AC1OUT_bp 1 /* Analog Comparator 1 Output Enable bit position. */ - -#define AC_AC0OUT_bm 0x01 /* Analog Comparator 0 Output Enable bit mask. */ -#define AC_AC0OUT_bp 0 /* Analog Comparator 0 Output Enable bit position. */ - -/* AC.CTRLB bit masks and bit positions */ -#define AC_SCALEFAC_gm 0x3F /* VCC Voltage Scaler Factor group mask. */ -#define AC_SCALEFAC_gp 0 /* VCC Voltage Scaler Factor group position. */ -#define AC_SCALEFAC0_bm (1<<0) /* VCC Voltage Scaler Factor bit 0 mask. */ -#define AC_SCALEFAC0_bp 0 /* VCC Voltage Scaler Factor bit 0 position. */ -#define AC_SCALEFAC1_bm (1<<1) /* VCC Voltage Scaler Factor bit 1 mask. */ -#define AC_SCALEFAC1_bp 1 /* VCC Voltage Scaler Factor bit 1 position. */ -#define AC_SCALEFAC2_bm (1<<2) /* VCC Voltage Scaler Factor bit 2 mask. */ -#define AC_SCALEFAC2_bp 2 /* VCC Voltage Scaler Factor bit 2 position. */ -#define AC_SCALEFAC3_bm (1<<3) /* VCC Voltage Scaler Factor bit 3 mask. */ -#define AC_SCALEFAC3_bp 3 /* VCC Voltage Scaler Factor bit 3 position. */ -#define AC_SCALEFAC4_bm (1<<4) /* VCC Voltage Scaler Factor bit 4 mask. */ -#define AC_SCALEFAC4_bp 4 /* VCC Voltage Scaler Factor bit 4 position. */ -#define AC_SCALEFAC5_bm (1<<5) /* VCC Voltage Scaler Factor bit 5 mask. */ -#define AC_SCALEFAC5_bp 5 /* VCC Voltage Scaler Factor bit 5 position. */ - -/* AC.WINCTRL bit masks and bit positions */ -#define AC_WEN_bm 0x10 /* Window Mode Enable bit mask. */ -#define AC_WEN_bp 4 /* Window Mode Enable bit position. */ - -#define AC_WINTMODE_gm 0x0C /* Window Interrupt Mode group mask. */ -#define AC_WINTMODE_gp 2 /* Window Interrupt Mode group position. */ -#define AC_WINTMODE0_bm (1<<2) /* Window Interrupt Mode bit 0 mask. */ -#define AC_WINTMODE0_bp 2 /* Window Interrupt Mode bit 0 position. */ -#define AC_WINTMODE1_bm (1<<3) /* Window Interrupt Mode bit 1 mask. */ -#define AC_WINTMODE1_bp 3 /* Window Interrupt Mode bit 1 position. */ - -#define AC_WINTLVL_gm 0x03 /* Window Interrupt Level group mask. */ -#define AC_WINTLVL_gp 0 /* Window Interrupt Level group position. */ -#define AC_WINTLVL0_bm (1<<0) /* Window Interrupt Level bit 0 mask. */ -#define AC_WINTLVL0_bp 0 /* Window Interrupt Level bit 0 position. */ -#define AC_WINTLVL1_bm (1<<1) /* Window Interrupt Level bit 1 mask. */ -#define AC_WINTLVL1_bp 1 /* Window Interrupt Level bit 1 position. */ - -/* AC.STATUS bit masks and bit positions */ -#define AC_WSTATE_gm 0xC0 /* Window Mode State group mask. */ -#define AC_WSTATE_gp 6 /* Window Mode State group position. */ -#define AC_WSTATE0_bm (1<<6) /* Window Mode State bit 0 mask. */ -#define AC_WSTATE0_bp 6 /* Window Mode State bit 0 position. */ -#define AC_WSTATE1_bm (1<<7) /* Window Mode State bit 1 mask. */ -#define AC_WSTATE1_bp 7 /* Window Mode State bit 1 position. */ - -#define AC_AC1STATE_bm 0x20 /* Analog Comparator 1 State bit mask. */ -#define AC_AC1STATE_bp 5 /* Analog Comparator 1 State bit position. */ - -#define AC_AC0STATE_bm 0x10 /* Analog Comparator 0 State bit mask. */ -#define AC_AC0STATE_bp 4 /* Analog Comparator 0 State bit position. */ - -#define AC_WIF_bm 0x04 /* Window Mode Interrupt Flag bit mask. */ -#define AC_WIF_bp 2 /* Window Mode Interrupt Flag bit position. */ - -#define AC_AC1IF_bm 0x02 /* Analog Comparator 1 Interrupt Flag bit mask. */ -#define AC_AC1IF_bp 1 /* Analog Comparator 1 Interrupt Flag bit position. */ - -#define AC_AC0IF_bm 0x01 /* Analog Comparator 0 Interrupt Flag bit mask. */ -#define AC_AC0IF_bp 0 /* Analog Comparator 0 Interrupt Flag bit position. */ - -/* RTC - Real-Time Counter */ -/* RTC.CTRL bit masks and bit positions */ -#define RTC_PRESCALER_gm 0x07 /* Prescaling Factor group mask. */ -#define RTC_PRESCALER_gp 0 /* Prescaling Factor group position. */ -#define RTC_PRESCALER0_bm (1<<0) /* Prescaling Factor bit 0 mask. */ -#define RTC_PRESCALER0_bp 0 /* Prescaling Factor bit 0 position. */ -#define RTC_PRESCALER1_bm (1<<1) /* Prescaling Factor bit 1 mask. */ -#define RTC_PRESCALER1_bp 1 /* Prescaling Factor bit 1 position. */ -#define RTC_PRESCALER2_bm (1<<2) /* Prescaling Factor bit 2 mask. */ -#define RTC_PRESCALER2_bp 2 /* Prescaling Factor bit 2 position. */ - -/* RTC.STATUS bit masks and bit positions */ -#define RTC_SYNCBUSY_bm 0x01 /* Synchronization Busy Flag bit mask. */ -#define RTC_SYNCBUSY_bp 0 /* Synchronization Busy Flag bit position. */ - -/* RTC.INTCTRL bit masks and bit positions */ -#define RTC_COMPINTLVL_gm 0x0C /* Compare Match Interrupt Level group mask. */ -#define RTC_COMPINTLVL_gp 2 /* Compare Match Interrupt Level group position. */ -#define RTC_COMPINTLVL0_bm (1<<2) /* Compare Match Interrupt Level bit 0 mask. */ -#define RTC_COMPINTLVL0_bp 2 /* Compare Match Interrupt Level bit 0 position. */ -#define RTC_COMPINTLVL1_bm (1<<3) /* Compare Match Interrupt Level bit 1 mask. */ -#define RTC_COMPINTLVL1_bp 3 /* Compare Match Interrupt Level bit 1 position. */ - -#define RTC_OVFINTLVL_gm 0x03 /* Overflow Interrupt Level group mask. */ -#define RTC_OVFINTLVL_gp 0 /* Overflow Interrupt Level group position. */ -#define RTC_OVFINTLVL0_bm (1<<0) /* Overflow Interrupt Level bit 0 mask. */ -#define RTC_OVFINTLVL0_bp 0 /* Overflow Interrupt Level bit 0 position. */ -#define RTC_OVFINTLVL1_bm (1<<1) /* Overflow Interrupt Level bit 1 mask. */ -#define RTC_OVFINTLVL1_bp 1 /* Overflow Interrupt Level bit 1 position. */ - -/* RTC.INTFLAGS bit masks and bit positions */ -#define RTC_COMPIF_bm 0x02 /* Compare Match Interrupt Flag bit mask. */ -#define RTC_COMPIF_bp 1 /* Compare Match Interrupt Flag bit position. */ - -#define RTC_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ -#define RTC_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ - -/* TWI - Two-Wire Interface */ -/* TWI_MASTER.CTRLA bit masks and bit positions */ -#define TWI_MASTER_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ -#define TWI_MASTER_INTLVL_gp 6 /* Interrupt Level group position. */ -#define TWI_MASTER_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ -#define TWI_MASTER_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ -#define TWI_MASTER_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ -#define TWI_MASTER_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ - -#define TWI_MASTER_RIEN_bm 0x20 /* Read Interrupt Enable bit mask. */ -#define TWI_MASTER_RIEN_bp 5 /* Read Interrupt Enable bit position. */ - -#define TWI_MASTER_WIEN_bm 0x10 /* Write Interrupt Enable bit mask. */ -#define TWI_MASTER_WIEN_bp 4 /* Write Interrupt Enable bit position. */ - -#define TWI_MASTER_ENABLE_bm 0x08 /* Enable TWI Master bit mask. */ -#define TWI_MASTER_ENABLE_bp 3 /* Enable TWI Master bit position. */ - -/* TWI_MASTER.CTRLB bit masks and bit positions */ -#define TWI_MASTER_TIMEOUT_gm 0x0C /* Inactive Bus Timeout group mask. */ -#define TWI_MASTER_TIMEOUT_gp 2 /* Inactive Bus Timeout group position. */ -#define TWI_MASTER_TIMEOUT0_bm (1<<2) /* Inactive Bus Timeout bit 0 mask. */ -#define TWI_MASTER_TIMEOUT0_bp 2 /* Inactive Bus Timeout bit 0 position. */ -#define TWI_MASTER_TIMEOUT1_bm (1<<3) /* Inactive Bus Timeout bit 1 mask. */ -#define TWI_MASTER_TIMEOUT1_bp 3 /* Inactive Bus Timeout bit 1 position. */ - -#define TWI_MASTER_QCEN_bm 0x02 /* Quick Command Enable bit mask. */ -#define TWI_MASTER_QCEN_bp 1 /* Quick Command Enable bit position. */ - -#define TWI_MASTER_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ -#define TWI_MASTER_SMEN_bp 0 /* Smart Mode Enable bit position. */ - -/* TWI_MASTER.CTRLC bit masks and bit positions */ -#define TWI_MASTER_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ -#define TWI_MASTER_ACKACT_bp 2 /* Acknowledge Action bit position. */ - -#define TWI_MASTER_CMD_gm 0x03 /* Command group mask. */ -#define TWI_MASTER_CMD_gp 0 /* Command group position. */ -#define TWI_MASTER_CMD0_bm (1<<0) /* Command bit 0 mask. */ -#define TWI_MASTER_CMD0_bp 0 /* Command bit 0 position. */ -#define TWI_MASTER_CMD1_bm (1<<1) /* Command bit 1 mask. */ -#define TWI_MASTER_CMD1_bp 1 /* Command bit 1 position. */ - -/* TWI_MASTER.STATUS bit masks and bit positions */ -#define TWI_MASTER_RIF_bm 0x80 /* Read Interrupt Flag bit mask. */ -#define TWI_MASTER_RIF_bp 7 /* Read Interrupt Flag bit position. */ - -#define TWI_MASTER_WIF_bm 0x40 /* Write Interrupt Flag bit mask. */ -#define TWI_MASTER_WIF_bp 6 /* Write Interrupt Flag bit position. */ - -#define TWI_MASTER_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ -#define TWI_MASTER_CLKHOLD_bp 5 /* Clock Hold bit position. */ - -#define TWI_MASTER_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ -#define TWI_MASTER_RXACK_bp 4 /* Received Acknowledge bit position. */ - -#define TWI_MASTER_ARBLOST_bm 0x08 /* Arbitration Lost bit mask. */ -#define TWI_MASTER_ARBLOST_bp 3 /* Arbitration Lost bit position. */ - -#define TWI_MASTER_BUSERR_bm 0x04 /* Bus Error bit mask. */ -#define TWI_MASTER_BUSERR_bp 2 /* Bus Error bit position. */ - -#define TWI_MASTER_BUSSTATE_gm 0x03 /* Bus State group mask. */ -#define TWI_MASTER_BUSSTATE_gp 0 /* Bus State group position. */ -#define TWI_MASTER_BUSSTATE0_bm (1<<0) /* Bus State bit 0 mask. */ -#define TWI_MASTER_BUSSTATE0_bp 0 /* Bus State bit 0 position. */ -#define TWI_MASTER_BUSSTATE1_bm (1<<1) /* Bus State bit 1 mask. */ -#define TWI_MASTER_BUSSTATE1_bp 1 /* Bus State bit 1 position. */ - -/* TWI_SLAVE.CTRLA bit masks and bit positions */ -#define TWI_SLAVE_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ -#define TWI_SLAVE_INTLVL_gp 6 /* Interrupt Level group position. */ -#define TWI_SLAVE_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ -#define TWI_SLAVE_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ -#define TWI_SLAVE_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ -#define TWI_SLAVE_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ - -#define TWI_SLAVE_DIEN_bm 0x20 /* Data Interrupt Enable bit mask. */ -#define TWI_SLAVE_DIEN_bp 5 /* Data Interrupt Enable bit position. */ - -#define TWI_SLAVE_APIEN_bm 0x10 /* Address/Stop Interrupt Enable bit mask. */ -#define TWI_SLAVE_APIEN_bp 4 /* Address/Stop Interrupt Enable bit position. */ - -#define TWI_SLAVE_ENABLE_bm 0x08 /* Enable TWI Slave bit mask. */ -#define TWI_SLAVE_ENABLE_bp 3 /* Enable TWI Slave bit position. */ - -#define TWI_SLAVE_PIEN_bm 0x04 /* Stop Interrupt Enable bit mask. */ -#define TWI_SLAVE_PIEN_bp 2 /* Stop Interrupt Enable bit position. */ - -#define TWI_SLAVE_PMEN_bm 0x02 /* Promiscuous Mode Enable bit mask. */ -#define TWI_SLAVE_PMEN_bp 1 /* Promiscuous Mode Enable bit position. */ - -#define TWI_SLAVE_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ -#define TWI_SLAVE_SMEN_bp 0 /* Smart Mode Enable bit position. */ - -/* TWI_SLAVE.CTRLB bit masks and bit positions */ -#define TWI_SLAVE_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ -#define TWI_SLAVE_ACKACT_bp 2 /* Acknowledge Action bit position. */ - -#define TWI_SLAVE_CMD_gm 0x03 /* Command group mask. */ -#define TWI_SLAVE_CMD_gp 0 /* Command group position. */ -#define TWI_SLAVE_CMD0_bm (1<<0) /* Command bit 0 mask. */ -#define TWI_SLAVE_CMD0_bp 0 /* Command bit 0 position. */ -#define TWI_SLAVE_CMD1_bm (1<<1) /* Command bit 1 mask. */ -#define TWI_SLAVE_CMD1_bp 1 /* Command bit 1 position. */ - -/* TWI_SLAVE.STATUS bit masks and bit positions */ -#define TWI_SLAVE_DIF_bm 0x80 /* Data Interrupt Flag bit mask. */ -#define TWI_SLAVE_DIF_bp 7 /* Data Interrupt Flag bit position. */ - -#define TWI_SLAVE_APIF_bm 0x40 /* Address/Stop Interrupt Flag bit mask. */ -#define TWI_SLAVE_APIF_bp 6 /* Address/Stop Interrupt Flag bit position. */ - -#define TWI_SLAVE_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ -#define TWI_SLAVE_CLKHOLD_bp 5 /* Clock Hold bit position. */ - -#define TWI_SLAVE_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ -#define TWI_SLAVE_RXACK_bp 4 /* Received Acknowledge bit position. */ - -#define TWI_SLAVE_COLL_bm 0x08 /* Collision bit mask. */ -#define TWI_SLAVE_COLL_bp 3 /* Collision bit position. */ - -#define TWI_SLAVE_BUSERR_bm 0x04 /* Bus Error bit mask. */ -#define TWI_SLAVE_BUSERR_bp 2 /* Bus Error bit position. */ - -#define TWI_SLAVE_DIR_bm 0x02 /* Read/Write Direction bit mask. */ -#define TWI_SLAVE_DIR_bp 1 /* Read/Write Direction bit position. */ - -#define TWI_SLAVE_AP_bm 0x01 /* Slave Address or Stop bit mask. */ -#define TWI_SLAVE_AP_bp 0 /* Slave Address or Stop bit position. */ - -/* TWI_SLAVE.ADDRMASK bit masks and bit positions */ -#define TWI_SLAVE_ADDRMASK_gm 0xFE /* Address Mask group mask. */ -#define TWI_SLAVE_ADDRMASK_gp 1 /* Address Mask group position. */ -#define TWI_SLAVE_ADDRMASK0_bm (1<<1) /* Address Mask bit 0 mask. */ -#define TWI_SLAVE_ADDRMASK0_bp 1 /* Address Mask bit 0 position. */ -#define TWI_SLAVE_ADDRMASK1_bm (1<<2) /* Address Mask bit 1 mask. */ -#define TWI_SLAVE_ADDRMASK1_bp 2 /* Address Mask bit 1 position. */ -#define TWI_SLAVE_ADDRMASK2_bm (1<<3) /* Address Mask bit 2 mask. */ -#define TWI_SLAVE_ADDRMASK2_bp 3 /* Address Mask bit 2 position. */ -#define TWI_SLAVE_ADDRMASK3_bm (1<<4) /* Address Mask bit 3 mask. */ -#define TWI_SLAVE_ADDRMASK3_bp 4 /* Address Mask bit 3 position. */ -#define TWI_SLAVE_ADDRMASK4_bm (1<<5) /* Address Mask bit 4 mask. */ -#define TWI_SLAVE_ADDRMASK4_bp 5 /* Address Mask bit 4 position. */ -#define TWI_SLAVE_ADDRMASK5_bm (1<<6) /* Address Mask bit 5 mask. */ -#define TWI_SLAVE_ADDRMASK5_bp 6 /* Address Mask bit 5 position. */ -#define TWI_SLAVE_ADDRMASK6_bm (1<<7) /* Address Mask bit 6 mask. */ -#define TWI_SLAVE_ADDRMASK6_bp 7 /* Address Mask bit 6 position. */ - -#define TWI_SLAVE_ADDREN_bm 0x01 /* Address Enable bit mask. */ -#define TWI_SLAVE_ADDREN_bp 0 /* Address Enable bit position. */ - -/* TWI.CTRL bit masks and bit positions */ -#define TWI_SDAHOLD_gm 0x06 /* SDA Hold Time Enable group mask. */ -#define TWI_SDAHOLD_gp 1 /* SDA Hold Time Enable group position. */ -#define TWI_SDAHOLD0_bm (1<<1) /* SDA Hold Time Enable bit 0 mask. */ -#define TWI_SDAHOLD0_bp 1 /* SDA Hold Time Enable bit 0 position. */ -#define TWI_SDAHOLD1_bm (1<<2) /* SDA Hold Time Enable bit 1 mask. */ -#define TWI_SDAHOLD1_bp 2 /* SDA Hold Time Enable bit 1 position. */ - -#define TWI_EDIEN_bm 0x01 /* External Driver Interface Enable bit mask. */ -#define TWI_EDIEN_bp 0 /* External Driver Interface Enable bit position. */ - -/* USB - USB */ -/* USB_EP.STATUS bit masks and bit positions */ -#define USB_EP_STALLF_bm 0x80 /* Endpoint Stall Flag bit mask. */ -#define USB_EP_STALLF_bp 7 /* Endpoint Stall Flag bit position. */ - -#define USB_EP_CRC_bm 0x80 /* CRC Error Flag bit mask. */ -#define USB_EP_CRC_bp 7 /* CRC Error Flag bit position. */ - -#define USB_EP_UNF_bm 0x40 /* Underflow Enpoint FLag bit mask. */ -#define USB_EP_UNF_bp 6 /* Underflow Enpoint FLag bit position. */ - -#define USB_EP_OVF_bm 0x40 /* Overflow Enpoint Flag for Output Endpoints bit mask. */ -#define USB_EP_OVF_bp 6 /* Overflow Enpoint Flag for Output Endpoints bit position. */ - -#define USB_EP_TRNCOMPL0_bm 0x20 /* Transaction Complete 0 Flag bit mask. */ -#define USB_EP_TRNCOMPL0_bp 5 /* Transaction Complete 0 Flag bit position. */ - -#define USB_EP_TRNCOMPL1_bm 0x10 /* Transaction Complete 1 Flag bit mask. */ -#define USB_EP_TRNCOMPL1_bp 4 /* Transaction Complete 1 Flag bit position. */ - -#define USB_EP_SETUP_bm 0x10 /* SETUP Transaction Complete Flag bit mask. */ -#define USB_EP_SETUP_bp 4 /* SETUP Transaction Complete Flag bit position. */ - -#define USB_EP_BANK_bm 0x08 /* Bank Select bit mask. */ -#define USB_EP_BANK_bp 3 /* Bank Select bit position. */ - -#define USB_EP_BUSNACK1_bm 0x04 /* Data Buffer 1 Not Acknowledge bit mask. */ -#define USB_EP_BUSNACK1_bp 2 /* Data Buffer 1 Not Acknowledge bit position. */ - -#define USB_EP_BUSNACK0_bm 0x02 /* Data Buffer 0 Not Acknowledge bit mask. */ -#define USB_EP_BUSNACK0_bp 1 /* Data Buffer 0 Not Acknowledge bit position. */ - -#define USB_EP_TOGGLE_bm 0x01 /* Data Toggle bit mask. */ -#define USB_EP_TOGGLE_bp 0 /* Data Toggle bit position. */ - -/* USB_EP.CTRL bit masks and bit positions */ -#define USB_EP_TYPE_gm 0xC0 /* Endpoint Type group mask. */ -#define USB_EP_TYPE_gp 6 /* Endpoint Type group position. */ -#define USB_EP_TYPE0_bm (1<<6) /* Endpoint Type bit 0 mask. */ -#define USB_EP_TYPE0_bp 6 /* Endpoint Type bit 0 position. */ -#define USB_EP_TYPE1_bm (1<<7) /* Endpoint Type bit 1 mask. */ -#define USB_EP_TYPE1_bp 7 /* Endpoint Type bit 1 position. */ - -#define USB_EP_MULTIPKT_bm 0x20 /* Multi Packet Transfer Enable bit mask. */ -#define USB_EP_MULTIPKT_bp 5 /* Multi Packet Transfer Enable bit position. */ - -#define USB_EP_PINGPONG_bm 0x10 /* Ping-Pong Enable bit mask. */ -#define USB_EP_PINGPONG_bp 4 /* Ping-Pong Enable bit position. */ - -#define USB_EP_INTDSBL_bm 0x08 /* Interrupt Disable bit mask. */ -#define USB_EP_INTDSBL_bp 3 /* Interrupt Disable bit position. */ - -#define USB_EP_STALL_bm 0x04 /* Data Stall bit mask. */ -#define USB_EP_STALL_bp 2 /* Data Stall bit position. */ - -#define USB_EP_BUFSIZE_gm 0x07 /* Data Buffer Size group mask. */ -#define USB_EP_BUFSIZE_gp 0 /* Data Buffer Size group position. */ -#define USB_EP_BUFSIZE0_bm (1<<0) /* Data Buffer Size bit 0 mask. */ -#define USB_EP_BUFSIZE0_bp 0 /* Data Buffer Size bit 0 position. */ -#define USB_EP_BUFSIZE1_bm (1<<1) /* Data Buffer Size bit 1 mask. */ -#define USB_EP_BUFSIZE1_bp 1 /* Data Buffer Size bit 1 position. */ -#define USB_EP_BUFSIZE2_bm (1<<2) /* Data Buffer Size bit 2 mask. */ -#define USB_EP_BUFSIZE2_bp 2 /* Data Buffer Size bit 2 position. */ - -/* USB_EP.CNT bit masks and bit positions */ -#define USB_EP_ZLP_bm 0x8000 /* Zero Length Packet bit mask. */ -#define USB_EP_ZLP_bp 15 /* Zero Length Packet bit position. */ - -/* USB.CTRLA bit masks and bit positions */ -#define USB_ENABLE_bm 0x80 /* USB Enable bit mask. */ -#define USB_ENABLE_bp 7 /* USB Enable bit position. */ - -#define USB_SPEED_bm 0x40 /* Speed Select bit mask. */ -#define USB_SPEED_bp 6 /* Speed Select bit position. */ - -#define USB_FIFOEN_bm 0x20 /* USB FIFO Enable bit mask. */ -#define USB_FIFOEN_bp 5 /* USB FIFO Enable bit position. */ - -#define USB_STFRNUM_bm 0x10 /* Store Frame Number Enable bit mask. */ -#define USB_STFRNUM_bp 4 /* Store Frame Number Enable bit position. */ - -#define USB_MAXEP_gm 0x0F /* Maximum Endpoint Addresses group mask. */ -#define USB_MAXEP_gp 0 /* Maximum Endpoint Addresses group position. */ -#define USB_MAXEP0_bm (1<<0) /* Maximum Endpoint Addresses bit 0 mask. */ -#define USB_MAXEP0_bp 0 /* Maximum Endpoint Addresses bit 0 position. */ -#define USB_MAXEP1_bm (1<<1) /* Maximum Endpoint Addresses bit 1 mask. */ -#define USB_MAXEP1_bp 1 /* Maximum Endpoint Addresses bit 1 position. */ -#define USB_MAXEP2_bm (1<<2) /* Maximum Endpoint Addresses bit 2 mask. */ -#define USB_MAXEP2_bp 2 /* Maximum Endpoint Addresses bit 2 position. */ -#define USB_MAXEP3_bm (1<<3) /* Maximum Endpoint Addresses bit 3 mask. */ -#define USB_MAXEP3_bp 3 /* Maximum Endpoint Addresses bit 3 position. */ - -/* USB.CTRLB bit masks and bit positions */ -#define USB_PULLRST_bm 0x10 /* Pull during Reset bit mask. */ -#define USB_PULLRST_bp 4 /* Pull during Reset bit position. */ - -#define USB_RWAKEUP_bm 0x04 /* Remote Wake-up bit mask. */ -#define USB_RWAKEUP_bp 2 /* Remote Wake-up bit position. */ - -#define USB_GNACK_bm 0x02 /* Global NACK bit mask. */ -#define USB_GNACK_bp 1 /* Global NACK bit position. */ - -#define USB_ATTACH_bm 0x01 /* Attach bit mask. */ -#define USB_ATTACH_bp 0 /* Attach bit position. */ - -/* USB.STATUS bit masks and bit positions */ -#define USB_URESUME_bm 0x08 /* Upstream Resume bit mask. */ -#define USB_URESUME_bp 3 /* Upstream Resume bit position. */ - -#define USB_RESUME_bm 0x04 /* Resume bit mask. */ -#define USB_RESUME_bp 2 /* Resume bit position. */ - -#define USB_SUSPEND_bm 0x02 /* Bus Suspended bit mask. */ -#define USB_SUSPEND_bp 1 /* Bus Suspended bit position. */ - -#define USB_BUSRST_bm 0x01 /* Bus Reset bit mask. */ -#define USB_BUSRST_bp 0 /* Bus Reset bit position. */ - -/* USB.ADDR bit masks and bit positions */ -#define USB_ADDR_gm 0x7F /* Device Address group mask. */ -#define USB_ADDR_gp 0 /* Device Address group position. */ -#define USB_ADDR0_bm (1<<0) /* Device Address bit 0 mask. */ -#define USB_ADDR0_bp 0 /* Device Address bit 0 position. */ -#define USB_ADDR1_bm (1<<1) /* Device Address bit 1 mask. */ -#define USB_ADDR1_bp 1 /* Device Address bit 1 position. */ -#define USB_ADDR2_bm (1<<2) /* Device Address bit 2 mask. */ -#define USB_ADDR2_bp 2 /* Device Address bit 2 position. */ -#define USB_ADDR3_bm (1<<3) /* Device Address bit 3 mask. */ -#define USB_ADDR3_bp 3 /* Device Address bit 3 position. */ -#define USB_ADDR4_bm (1<<4) /* Device Address bit 4 mask. */ -#define USB_ADDR4_bp 4 /* Device Address bit 4 position. */ -#define USB_ADDR5_bm (1<<5) /* Device Address bit 5 mask. */ -#define USB_ADDR5_bp 5 /* Device Address bit 5 position. */ -#define USB_ADDR6_bm (1<<6) /* Device Address bit 6 mask. */ -#define USB_ADDR6_bp 6 /* Device Address bit 6 position. */ - -/* USB.FIFOWP bit masks and bit positions */ -#define USB_FIFOWP_gm 0x1F /* FIFO Write Pointer group mask. */ -#define USB_FIFOWP_gp 0 /* FIFO Write Pointer group position. */ -#define USB_FIFOWP0_bm (1<<0) /* FIFO Write Pointer bit 0 mask. */ -#define USB_FIFOWP0_bp 0 /* FIFO Write Pointer bit 0 position. */ -#define USB_FIFOWP1_bm (1<<1) /* FIFO Write Pointer bit 1 mask. */ -#define USB_FIFOWP1_bp 1 /* FIFO Write Pointer bit 1 position. */ -#define USB_FIFOWP2_bm (1<<2) /* FIFO Write Pointer bit 2 mask. */ -#define USB_FIFOWP2_bp 2 /* FIFO Write Pointer bit 2 position. */ -#define USB_FIFOWP3_bm (1<<3) /* FIFO Write Pointer bit 3 mask. */ -#define USB_FIFOWP3_bp 3 /* FIFO Write Pointer bit 3 position. */ -#define USB_FIFOWP4_bm (1<<4) /* FIFO Write Pointer bit 4 mask. */ -#define USB_FIFOWP4_bp 4 /* FIFO Write Pointer bit 4 position. */ - -/* USB.FIFORP bit masks and bit positions */ -#define USB_FIFORP_gm 0x1F /* FIFO Read Pointer group mask. */ -#define USB_FIFORP_gp 0 /* FIFO Read Pointer group position. */ -#define USB_FIFORP0_bm (1<<0) /* FIFO Read Pointer bit 0 mask. */ -#define USB_FIFORP0_bp 0 /* FIFO Read Pointer bit 0 position. */ -#define USB_FIFORP1_bm (1<<1) /* FIFO Read Pointer bit 1 mask. */ -#define USB_FIFORP1_bp 1 /* FIFO Read Pointer bit 1 position. */ -#define USB_FIFORP2_bm (1<<2) /* FIFO Read Pointer bit 2 mask. */ -#define USB_FIFORP2_bp 2 /* FIFO Read Pointer bit 2 position. */ -#define USB_FIFORP3_bm (1<<3) /* FIFO Read Pointer bit 3 mask. */ -#define USB_FIFORP3_bp 3 /* FIFO Read Pointer bit 3 position. */ -#define USB_FIFORP4_bm (1<<4) /* FIFO Read Pointer bit 4 mask. */ -#define USB_FIFORP4_bp 4 /* FIFO Read Pointer bit 4 position. */ - -/* USB.INTCTRLA bit masks and bit positions */ -#define USB_SOFIE_bm 0x80 /* Start Of Frame Interrupt Enable bit mask. */ -#define USB_SOFIE_bp 7 /* Start Of Frame Interrupt Enable bit position. */ - -#define USB_BUSEVIE_bm 0x40 /* Bus Event Interrupt Enable bit mask. */ -#define USB_BUSEVIE_bp 6 /* Bus Event Interrupt Enable bit position. */ - -#define USB_BUSERRIE_bm 0x20 /* Bus Error Interrupt Enable bit mask. */ -#define USB_BUSERRIE_bp 5 /* Bus Error Interrupt Enable bit position. */ - -#define USB_STALLIE_bm 0x10 /* STALL Interrupt Enable bit mask. */ -#define USB_STALLIE_bp 4 /* STALL Interrupt Enable bit position. */ - -#define USB_INTLVL_gm 0x03 /* Interrupt Level group mask. */ -#define USB_INTLVL_gp 0 /* Interrupt Level group position. */ -#define USB_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */ -#define USB_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */ -#define USB_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ -#define USB_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */ - -/* USB.INTCTRLB bit masks and bit positions */ -#define USB_TRNIE_bm 0x02 /* Transaction Complete Interrupt Enable bit mask. */ -#define USB_TRNIE_bp 1 /* Transaction Complete Interrupt Enable bit position. */ - -#define USB_SETUPIE_bm 0x01 /* SETUP Transaction Complete Interrupt Enable bit mask. */ -#define USB_SETUPIE_bp 0 /* SETUP Transaction Complete Interrupt Enable bit position. */ - -/* USB.INTFLAGSACLR bit masks and bit positions */ -#define USB_SOFIF_bm 0x80 /* Start Of Frame Interrupt Flag bit mask. */ -#define USB_SOFIF_bp 7 /* Start Of Frame Interrupt Flag bit position. */ - -#define USB_SUSPENDIF_bm 0x40 /* Suspend Interrupt Flag bit mask. */ -#define USB_SUSPENDIF_bp 6 /* Suspend Interrupt Flag bit position. */ - -#define USB_RESUMEIF_bm 0x20 /* Resume Interrupt Flag bit mask. */ -#define USB_RESUMEIF_bp 5 /* Resume Interrupt Flag bit position. */ - -#define USB_RSTIF_bm 0x10 /* Reset Interrupt Flag bit mask. */ -#define USB_RSTIF_bp 4 /* Reset Interrupt Flag bit position. */ - -#define USB_CRCIF_bm 0x08 /* Isochronous CRC Error Interrupt Flag bit mask. */ -#define USB_CRCIF_bp 3 /* Isochronous CRC Error Interrupt Flag bit position. */ - -#define USB_UNFIF_bm 0x04 /* Underflow Interrupt Flag bit mask. */ -#define USB_UNFIF_bp 2 /* Underflow Interrupt Flag bit position. */ - -#define USB_OVFIF_bm 0x02 /* Overflow Interrupt Flag bit mask. */ -#define USB_OVFIF_bp 1 /* Overflow Interrupt Flag bit position. */ - -#define USB_STALLIF_bm 0x01 /* STALL Interrupt Flag bit mask. */ -#define USB_STALLIF_bp 0 /* STALL Interrupt Flag bit position. */ - -/* USB.INTFLAGSASET bit masks and bit positions */ -/* USB_SOFIF Predefined. */ -/* USB_SOFIF Predefined. */ - -/* USB_SUSPENDIF Predefined. */ -/* USB_SUSPENDIF Predefined. */ - -/* USB_RESUMEIF Predefined. */ -/* USB_RESUMEIF Predefined. */ - -/* USB_RSTIF Predefined. */ -/* USB_RSTIF Predefined. */ - -/* USB_CRCIF Predefined. */ -/* USB_CRCIF Predefined. */ - -/* USB_UNFIF Predefined. */ -/* USB_UNFIF Predefined. */ - -/* USB_OVFIF Predefined. */ -/* USB_OVFIF Predefined. */ - -/* USB_STALLIF Predefined. */ -/* USB_STALLIF Predefined. */ - -/* USB.INTFLAGSBCLR bit masks and bit positions */ -#define USB_TRNIF_bm 0x02 /* Transaction Complete Interrupt Flag bit mask. */ -#define USB_TRNIF_bp 1 /* Transaction Complete Interrupt Flag bit position. */ - -#define USB_SETUPIF_bm 0x01 /* SETUP Transaction Complete Interrupt Flag bit mask. */ -#define USB_SETUPIF_bp 0 /* SETUP Transaction Complete Interrupt Flag bit position. */ - -/* USB.INTFLAGSBSET bit masks and bit positions */ -/* USB_TRNIF Predefined. */ -/* USB_TRNIF Predefined. */ - -/* USB_SETUPIF Predefined. */ -/* USB_SETUPIF Predefined. */ - -/* PORT - I/O Port Configuration */ -/* PORT.INTCTRL bit masks and bit positions */ -#define PORT_INT1LVL_gm 0x0C /* Port Interrupt 1 Level group mask. */ -#define PORT_INT1LVL_gp 2 /* Port Interrupt 1 Level group position. */ -#define PORT_INT1LVL0_bm (1<<2) /* Port Interrupt 1 Level bit 0 mask. */ -#define PORT_INT1LVL0_bp 2 /* Port Interrupt 1 Level bit 0 position. */ -#define PORT_INT1LVL1_bm (1<<3) /* Port Interrupt 1 Level bit 1 mask. */ -#define PORT_INT1LVL1_bp 3 /* Port Interrupt 1 Level bit 1 position. */ - -#define PORT_INT0LVL_gm 0x03 /* Port Interrupt 0 Level group mask. */ -#define PORT_INT0LVL_gp 0 /* Port Interrupt 0 Level group position. */ -#define PORT_INT0LVL0_bm (1<<0) /* Port Interrupt 0 Level bit 0 mask. */ -#define PORT_INT0LVL0_bp 0 /* Port Interrupt 0 Level bit 0 position. */ -#define PORT_INT0LVL1_bm (1<<1) /* Port Interrupt 0 Level bit 1 mask. */ -#define PORT_INT0LVL1_bp 1 /* Port Interrupt 0 Level bit 1 position. */ - -/* PORT.INTFLAGS bit masks and bit positions */ -#define PORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ -#define PORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ - -#define PORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ -#define PORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ - -/* PORT.REMAP bit masks and bit positions */ -#define PORT_SPI_bm 0x20 /* SPI bit mask. */ -#define PORT_SPI_bp 5 /* SPI bit position. */ - -#define PORT_USART0_bm 0x10 /* USART0 bit mask. */ -#define PORT_USART0_bp 4 /* USART0 bit position. */ - -#define PORT_TC0D_bm 0x08 /* Timer/Counter 0 Output Compare D bit mask. */ -#define PORT_TC0D_bp 3 /* Timer/Counter 0 Output Compare D bit position. */ - -#define PORT_TC0C_bm 0x04 /* Timer/Counter 0 Output Compare C bit mask. */ -#define PORT_TC0C_bp 2 /* Timer/Counter 0 Output Compare C bit position. */ - -#define PORT_TC0B_bm 0x02 /* Timer/Counter 0 Output Compare B bit mask. */ -#define PORT_TC0B_bp 1 /* Timer/Counter 0 Output Compare B bit position. */ - -#define PORT_TC0A_bm 0x01 /* Timer/Counter 0 Output Compare A bit mask. */ -#define PORT_TC0A_bp 0 /* Timer/Counter 0 Output Compare A bit position. */ - -/* PORT.PIN0CTRL bit masks and bit positions */ -#define PORT_SRLEN_bm 0x80 /* Slew Rate Enable bit mask. */ -#define PORT_SRLEN_bp 7 /* Slew Rate Enable bit position. */ - -#define PORT_INVEN_bm 0x40 /* Inverted I/O Enable bit mask. */ -#define PORT_INVEN_bp 6 /* Inverted I/O Enable bit position. */ - -#define PORT_OPC_gm 0x38 /* Output/Pull Configuration group mask. */ -#define PORT_OPC_gp 3 /* Output/Pull Configuration group position. */ -#define PORT_OPC0_bm (1<<3) /* Output/Pull Configuration bit 0 mask. */ -#define PORT_OPC0_bp 3 /* Output/Pull Configuration bit 0 position. */ -#define PORT_OPC1_bm (1<<4) /* Output/Pull Configuration bit 1 mask. */ -#define PORT_OPC1_bp 4 /* Output/Pull Configuration bit 1 position. */ -#define PORT_OPC2_bm (1<<5) /* Output/Pull Configuration bit 2 mask. */ -#define PORT_OPC2_bp 5 /* Output/Pull Configuration bit 2 position. */ - -#define PORT_ISC_gm 0x07 /* Input/Sense Configuration group mask. */ -#define PORT_ISC_gp 0 /* Input/Sense Configuration group position. */ -#define PORT_ISC0_bm (1<<0) /* Input/Sense Configuration bit 0 mask. */ -#define PORT_ISC0_bp 0 /* Input/Sense Configuration bit 0 position. */ -#define PORT_ISC1_bm (1<<1) /* Input/Sense Configuration bit 1 mask. */ -#define PORT_ISC1_bp 1 /* Input/Sense Configuration bit 1 position. */ -#define PORT_ISC2_bm (1<<2) /* Input/Sense Configuration bit 2 mask. */ -#define PORT_ISC2_bp 2 /* Input/Sense Configuration bit 2 position. */ - -/* PORT.PIN1CTRL bit masks and bit positions */ -/* PORT_SRLEN Predefined. */ -/* PORT_SRLEN Predefined. */ - -/* PORT_INVEN Predefined. */ -/* PORT_INVEN Predefined. */ - -/* PORT_OPC Predefined. */ -/* PORT_OPC Predefined. */ - -/* PORT_ISC Predefined. */ -/* PORT_ISC Predefined. */ - -/* PORT.PIN2CTRL bit masks and bit positions */ -/* PORT_SRLEN Predefined. */ -/* PORT_SRLEN Predefined. */ - -/* PORT_INVEN Predefined. */ -/* PORT_INVEN Predefined. */ - -/* PORT_OPC Predefined. */ -/* PORT_OPC Predefined. */ - -/* PORT_ISC Predefined. */ -/* PORT_ISC Predefined. */ - -/* PORT.PIN3CTRL bit masks and bit positions */ -/* PORT_SRLEN Predefined. */ -/* PORT_SRLEN Predefined. */ - -/* PORT_INVEN Predefined. */ -/* PORT_INVEN Predefined. */ - -/* PORT_OPC Predefined. */ -/* PORT_OPC Predefined. */ - -/* PORT_ISC Predefined. */ -/* PORT_ISC Predefined. */ - -/* PORT.PIN4CTRL bit masks and bit positions */ -/* PORT_SRLEN Predefined. */ -/* PORT_SRLEN Predefined. */ - -/* PORT_INVEN Predefined. */ -/* PORT_INVEN Predefined. */ - -/* PORT_OPC Predefined. */ -/* PORT_OPC Predefined. */ - -/* PORT_ISC Predefined. */ -/* PORT_ISC Predefined. */ - -/* PORT.PIN5CTRL bit masks and bit positions */ -/* PORT_SRLEN Predefined. */ -/* PORT_SRLEN Predefined. */ - -/* PORT_INVEN Predefined. */ -/* PORT_INVEN Predefined. */ - -/* PORT_OPC Predefined. */ -/* PORT_OPC Predefined. */ - -/* PORT_ISC Predefined. */ -/* PORT_ISC Predefined. */ - -/* PORT.PIN6CTRL bit masks and bit positions */ -/* PORT_SRLEN Predefined. */ -/* PORT_SRLEN Predefined. */ - -/* PORT_INVEN Predefined. */ -/* PORT_INVEN Predefined. */ - -/* PORT_OPC Predefined. */ -/* PORT_OPC Predefined. */ - -/* PORT_ISC Predefined. */ -/* PORT_ISC Predefined. */ - -/* PORT.PIN7CTRL bit masks and bit positions */ -/* PORT_SRLEN Predefined. */ -/* PORT_SRLEN Predefined. */ - -/* PORT_INVEN Predefined. */ -/* PORT_INVEN Predefined. */ - -/* PORT_OPC Predefined. */ -/* PORT_OPC Predefined. */ - -/* PORT_ISC Predefined. */ -/* PORT_ISC Predefined. */ - -/* TC - 16-bit Timer/Counter With PWM */ -/* TC0.CTRLA bit masks and bit positions */ -#define TC0_CLKSEL_gm 0x0F /* Clock Selection group mask. */ -#define TC0_CLKSEL_gp 0 /* Clock Selection group position. */ -#define TC0_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ -#define TC0_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ -#define TC0_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ -#define TC0_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ -#define TC0_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ -#define TC0_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ -#define TC0_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ -#define TC0_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ - -/* TC0.CTRLB bit masks and bit positions */ -#define TC0_CCDEN_bm 0x80 /* Compare or Capture D Enable bit mask. */ -#define TC0_CCDEN_bp 7 /* Compare or Capture D Enable bit position. */ - -#define TC0_CCCEN_bm 0x40 /* Compare or Capture C Enable bit mask. */ -#define TC0_CCCEN_bp 6 /* Compare or Capture C Enable bit position. */ - -#define TC0_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ -#define TC0_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ - -#define TC0_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ -#define TC0_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ - -#define TC0_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ -#define TC0_WGMODE_gp 0 /* Waveform generation mode group position. */ -#define TC0_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ -#define TC0_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ -#define TC0_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ -#define TC0_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ -#define TC0_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ -#define TC0_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ - -/* TC0.CTRLC bit masks and bit positions */ -#define TC0_CMPD_bm 0x08 /* Compare D Output Value bit mask. */ -#define TC0_CMPD_bp 3 /* Compare D Output Value bit position. */ - -#define TC0_CMPC_bm 0x04 /* Compare C Output Value bit mask. */ -#define TC0_CMPC_bp 2 /* Compare C Output Value bit position. */ - -#define TC0_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ -#define TC0_CMPB_bp 1 /* Compare B Output Value bit position. */ - -#define TC0_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ -#define TC0_CMPA_bp 0 /* Compare A Output Value bit position. */ - -/* TC0.CTRLD bit masks and bit positions */ -#define TC0_EVACT_gm 0xE0 /* Event Action group mask. */ -#define TC0_EVACT_gp 5 /* Event Action group position. */ -#define TC0_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ -#define TC0_EVACT0_bp 5 /* Event Action bit 0 position. */ -#define TC0_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ -#define TC0_EVACT1_bp 6 /* Event Action bit 1 position. */ -#define TC0_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ -#define TC0_EVACT2_bp 7 /* Event Action bit 2 position. */ - -#define TC0_EVDLY_bm 0x10 /* Event Delay bit mask. */ -#define TC0_EVDLY_bp 4 /* Event Delay bit position. */ - -#define TC0_EVSEL_gm 0x0F /* Event Source Select group mask. */ -#define TC0_EVSEL_gp 0 /* Event Source Select group position. */ -#define TC0_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ -#define TC0_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ -#define TC0_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ -#define TC0_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ -#define TC0_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ -#define TC0_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ -#define TC0_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ -#define TC0_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ - -/* TC0.CTRLE bit masks and bit positions */ -#define TC0_BYTEM_gm 0x03 /* Byte Mode group mask. */ -#define TC0_BYTEM_gp 0 /* Byte Mode group position. */ -#define TC0_BYTEM0_bm (1<<0) /* Byte Mode bit 0 mask. */ -#define TC0_BYTEM0_bp 0 /* Byte Mode bit 0 position. */ -#define TC0_BYTEM1_bm (1<<1) /* Byte Mode bit 1 mask. */ -#define TC0_BYTEM1_bp 1 /* Byte Mode bit 1 position. */ - -/* TC0.INTCTRLA bit masks and bit positions */ -#define TC0_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ -#define TC0_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ -#define TC0_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ -#define TC0_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ -#define TC0_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ -#define TC0_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ - -#define TC0_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ -#define TC0_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ -#define TC0_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ -#define TC0_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ -#define TC0_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ -#define TC0_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ - -/* TC0.INTCTRLB bit masks and bit positions */ -#define TC0_CCDINTLVL_gm 0xC0 /* Compare or Capture D Interrupt Level group mask. */ -#define TC0_CCDINTLVL_gp 6 /* Compare or Capture D Interrupt Level group position. */ -#define TC0_CCDINTLVL0_bm (1<<6) /* Compare or Capture D Interrupt Level bit 0 mask. */ -#define TC0_CCDINTLVL0_bp 6 /* Compare or Capture D Interrupt Level bit 0 position. */ -#define TC0_CCDINTLVL1_bm (1<<7) /* Compare or Capture D Interrupt Level bit 1 mask. */ -#define TC0_CCDINTLVL1_bp 7 /* Compare or Capture D Interrupt Level bit 1 position. */ - -#define TC0_CCCINTLVL_gm 0x30 /* Compare or Capture C Interrupt Level group mask. */ -#define TC0_CCCINTLVL_gp 4 /* Compare or Capture C Interrupt Level group position. */ -#define TC0_CCCINTLVL0_bm (1<<4) /* Compare or Capture C Interrupt Level bit 0 mask. */ -#define TC0_CCCINTLVL0_bp 4 /* Compare or Capture C Interrupt Level bit 0 position. */ -#define TC0_CCCINTLVL1_bm (1<<5) /* Compare or Capture C Interrupt Level bit 1 mask. */ -#define TC0_CCCINTLVL1_bp 5 /* Compare or Capture C Interrupt Level bit 1 position. */ - -#define TC0_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ -#define TC0_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ -#define TC0_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ -#define TC0_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ -#define TC0_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ -#define TC0_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ - -#define TC0_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ -#define TC0_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ -#define TC0_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ -#define TC0_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ -#define TC0_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ -#define TC0_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ - -/* TC0.CTRLFCLR bit masks and bit positions */ -#define TC0_CMD_gm 0x0C /* Command group mask. */ -#define TC0_CMD_gp 2 /* Command group position. */ -#define TC0_CMD0_bm (1<<2) /* Command bit 0 mask. */ -#define TC0_CMD0_bp 2 /* Command bit 0 position. */ -#define TC0_CMD1_bm (1<<3) /* Command bit 1 mask. */ -#define TC0_CMD1_bp 3 /* Command bit 1 position. */ - -#define TC0_LUPD_bm 0x02 /* Lock Update bit mask. */ -#define TC0_LUPD_bp 1 /* Lock Update bit position. */ - -#define TC0_DIR_bm 0x01 /* Direction bit mask. */ -#define TC0_DIR_bp 0 /* Direction bit position. */ - -/* TC0.CTRLFSET bit masks and bit positions */ -/* TC0_CMD Predefined. */ -/* TC0_CMD Predefined. */ - -/* TC0_LUPD Predefined. */ -/* TC0_LUPD Predefined. */ - -/* TC0_DIR Predefined. */ -/* TC0_DIR Predefined. */ - -/* TC0.CTRLGCLR bit masks and bit positions */ -#define TC0_CCDBV_bm 0x10 /* Compare or Capture D Buffer Valid bit mask. */ -#define TC0_CCDBV_bp 4 /* Compare or Capture D Buffer Valid bit position. */ - -#define TC0_CCCBV_bm 0x08 /* Compare or Capture C Buffer Valid bit mask. */ -#define TC0_CCCBV_bp 3 /* Compare or Capture C Buffer Valid bit position. */ - -#define TC0_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ -#define TC0_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ - -#define TC0_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ -#define TC0_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ - -#define TC0_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ -#define TC0_PERBV_bp 0 /* Period Buffer Valid bit position. */ - -/* TC0.CTRLGSET bit masks and bit positions */ -/* TC0_CCDBV Predefined. */ -/* TC0_CCDBV Predefined. */ - -/* TC0_CCCBV Predefined. */ -/* TC0_CCCBV Predefined. */ - -/* TC0_CCBBV Predefined. */ -/* TC0_CCBBV Predefined. */ - -/* TC0_CCABV Predefined. */ -/* TC0_CCABV Predefined. */ - -/* TC0_PERBV Predefined. */ -/* TC0_PERBV Predefined. */ - -/* TC0.INTFLAGS bit masks and bit positions */ -#define TC0_CCDIF_bm 0x80 /* Compare or Capture D Interrupt Flag bit mask. */ -#define TC0_CCDIF_bp 7 /* Compare or Capture D Interrupt Flag bit position. */ - -#define TC0_CCCIF_bm 0x40 /* Compare or Capture C Interrupt Flag bit mask. */ -#define TC0_CCCIF_bp 6 /* Compare or Capture C Interrupt Flag bit position. */ - -#define TC0_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ -#define TC0_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ - -#define TC0_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ -#define TC0_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ - -#define TC0_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ -#define TC0_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ - -#define TC0_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ -#define TC0_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ - -/* TC1.CTRLA bit masks and bit positions */ -#define TC1_CLKSEL_gm 0x0F /* Clock Selection group mask. */ -#define TC1_CLKSEL_gp 0 /* Clock Selection group position. */ -#define TC1_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ -#define TC1_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ -#define TC1_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ -#define TC1_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ -#define TC1_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ -#define TC1_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ -#define TC1_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ -#define TC1_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ - -/* TC1.CTRLB bit masks and bit positions */ -#define TC1_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ -#define TC1_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ - -#define TC1_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ -#define TC1_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ - -#define TC1_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ -#define TC1_WGMODE_gp 0 /* Waveform generation mode group position. */ -#define TC1_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ -#define TC1_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ -#define TC1_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ -#define TC1_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ -#define TC1_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ -#define TC1_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ - -/* TC1.CTRLC bit masks and bit positions */ -#define TC1_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ -#define TC1_CMPB_bp 1 /* Compare B Output Value bit position. */ - -#define TC1_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ -#define TC1_CMPA_bp 0 /* Compare A Output Value bit position. */ - -/* TC1.CTRLD bit masks and bit positions */ -#define TC1_EVACT_gm 0xE0 /* Event Action group mask. */ -#define TC1_EVACT_gp 5 /* Event Action group position. */ -#define TC1_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ -#define TC1_EVACT0_bp 5 /* Event Action bit 0 position. */ -#define TC1_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ -#define TC1_EVACT1_bp 6 /* Event Action bit 1 position. */ -#define TC1_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ -#define TC1_EVACT2_bp 7 /* Event Action bit 2 position. */ - -#define TC1_EVDLY_bm 0x10 /* Event Delay bit mask. */ -#define TC1_EVDLY_bp 4 /* Event Delay bit position. */ - -#define TC1_EVSEL_gm 0x0F /* Event Source Select group mask. */ -#define TC1_EVSEL_gp 0 /* Event Source Select group position. */ -#define TC1_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ -#define TC1_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ -#define TC1_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ -#define TC1_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ -#define TC1_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ -#define TC1_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ -#define TC1_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ -#define TC1_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ - -/* TC1.CTRLE bit masks and bit positions */ -#define TC1_BYTEM_bm 0x01 /* Byte Mode bit mask. */ -#define TC1_BYTEM_bp 0 /* Byte Mode bit position. */ - -/* TC1.INTCTRLA bit masks and bit positions */ -#define TC1_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ -#define TC1_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ -#define TC1_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ -#define TC1_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ -#define TC1_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ -#define TC1_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ - -#define TC1_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ -#define TC1_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ -#define TC1_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ -#define TC1_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ -#define TC1_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ -#define TC1_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ - -/* TC1.INTCTRLB bit masks and bit positions */ -#define TC1_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ -#define TC1_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ -#define TC1_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ -#define TC1_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ -#define TC1_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ -#define TC1_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ - -#define TC1_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ -#define TC1_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ -#define TC1_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ -#define TC1_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ -#define TC1_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ -#define TC1_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ - -/* TC1.CTRLFCLR bit masks and bit positions */ -#define TC1_CMD_gm 0x0C /* Command group mask. */ -#define TC1_CMD_gp 2 /* Command group position. */ -#define TC1_CMD0_bm (1<<2) /* Command bit 0 mask. */ -#define TC1_CMD0_bp 2 /* Command bit 0 position. */ -#define TC1_CMD1_bm (1<<3) /* Command bit 1 mask. */ -#define TC1_CMD1_bp 3 /* Command bit 1 position. */ - -#define TC1_LUPD_bm 0x02 /* Lock Update bit mask. */ -#define TC1_LUPD_bp 1 /* Lock Update bit position. */ - -#define TC1_DIR_bm 0x01 /* Direction bit mask. */ -#define TC1_DIR_bp 0 /* Direction bit position. */ - -/* TC1.CTRLFSET bit masks and bit positions */ -/* TC1_CMD Predefined. */ -/* TC1_CMD Predefined. */ - -/* TC1_LUPD Predefined. */ -/* TC1_LUPD Predefined. */ - -/* TC1_DIR Predefined. */ -/* TC1_DIR Predefined. */ - -/* TC1.CTRLGCLR bit masks and bit positions */ -#define TC1_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ -#define TC1_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ - -#define TC1_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ -#define TC1_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ - -#define TC1_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ -#define TC1_PERBV_bp 0 /* Period Buffer Valid bit position. */ - -/* TC1.CTRLGSET bit masks and bit positions */ -/* TC1_CCBBV Predefined. */ -/* TC1_CCBBV Predefined. */ - -/* TC1_CCABV Predefined. */ -/* TC1_CCABV Predefined. */ - -/* TC1_PERBV Predefined. */ -/* TC1_PERBV Predefined. */ - -/* TC1.INTFLAGS bit masks and bit positions */ -#define TC1_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ -#define TC1_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ - -#define TC1_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ -#define TC1_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ - -#define TC1_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ -#define TC1_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ - -#define TC1_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ -#define TC1_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ - -/* TC2 - 16-bit Timer/Counter type 2 */ -/* TC2.CTRLA bit masks and bit positions */ -#define TC2_CLKSEL_gm 0x0F /* Clock Selection group mask. */ -#define TC2_CLKSEL_gp 0 /* Clock Selection group position. */ -#define TC2_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ -#define TC2_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ -#define TC2_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ -#define TC2_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ -#define TC2_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ -#define TC2_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ -#define TC2_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ -#define TC2_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ - -/* TC2.CTRLB bit masks and bit positions */ -#define TC2_HCMPDEN_bm 0x80 /* High Byte Compare D Enable bit mask. */ -#define TC2_HCMPDEN_bp 7 /* High Byte Compare D Enable bit position. */ - -#define TC2_HCMPCEN_bm 0x40 /* High Byte Compare C Enable bit mask. */ -#define TC2_HCMPCEN_bp 6 /* High Byte Compare C Enable bit position. */ - -#define TC2_HCMPBEN_bm 0x20 /* High Byte Compare B Enable bit mask. */ -#define TC2_HCMPBEN_bp 5 /* High Byte Compare B Enable bit position. */ - -#define TC2_HCMPAEN_bm 0x10 /* High Byte Compare A Enable bit mask. */ -#define TC2_HCMPAEN_bp 4 /* High Byte Compare A Enable bit position. */ - -#define TC2_LCMPDEN_bm 0x08 /* Low Byte Compare D Enable bit mask. */ -#define TC2_LCMPDEN_bp 3 /* Low Byte Compare D Enable bit position. */ - -#define TC2_LCMPCEN_bm 0x04 /* Low Byte Compare C Enable bit mask. */ -#define TC2_LCMPCEN_bp 2 /* Low Byte Compare C Enable bit position. */ - -#define TC2_LCMPBEN_bm 0x02 /* Low Byte Compare B Enable bit mask. */ -#define TC2_LCMPBEN_bp 1 /* Low Byte Compare B Enable bit position. */ - -#define TC2_LCMPAEN_bm 0x01 /* Low Byte Compare A Enable bit mask. */ -#define TC2_LCMPAEN_bp 0 /* Low Byte Compare A Enable bit position. */ - -/* TC2.CTRLC bit masks and bit positions */ -#define TC2_HCMPD_bm 0x80 /* High Byte Compare D Output Value bit mask. */ -#define TC2_HCMPD_bp 7 /* High Byte Compare D Output Value bit position. */ - -#define TC2_HCMPC_bm 0x40 /* High Byte Compare C Output Value bit mask. */ -#define TC2_HCMPC_bp 6 /* High Byte Compare C Output Value bit position. */ - -#define TC2_HCMPB_bm 0x20 /* High Byte Compare B Output Value bit mask. */ -#define TC2_HCMPB_bp 5 /* High Byte Compare B Output Value bit position. */ - -#define TC2_HCMPA_bm 0x10 /* High Byte Compare A Output Value bit mask. */ -#define TC2_HCMPA_bp 4 /* High Byte Compare A Output Value bit position. */ - -#define TC2_LCMPD_bm 0x08 /* Low Byte Compare D Output Value bit mask. */ -#define TC2_LCMPD_bp 3 /* Low Byte Compare D Output Value bit position. */ - -#define TC2_LCMPC_bm 0x04 /* Low Byte Compare C Output Value bit mask. */ -#define TC2_LCMPC_bp 2 /* Low Byte Compare C Output Value bit position. */ - -#define TC2_LCMPB_bm 0x02 /* Low Byte Compare B Output Value bit mask. */ -#define TC2_LCMPB_bp 1 /* Low Byte Compare B Output Value bit position. */ - -#define TC2_LCMPA_bm 0x01 /* Low Byte Compare A Output Value bit mask. */ -#define TC2_LCMPA_bp 0 /* Low Byte Compare A Output Value bit position. */ - -/* TC2.CTRLE bit masks and bit positions */ -#define TC2_BYTEM_gm 0x03 /* Byte Mode group mask. */ -#define TC2_BYTEM_gp 0 /* Byte Mode group position. */ -#define TC2_BYTEM0_bm (1<<0) /* Byte Mode bit 0 mask. */ -#define TC2_BYTEM0_bp 0 /* Byte Mode bit 0 position. */ -#define TC2_BYTEM1_bm (1<<1) /* Byte Mode bit 1 mask. */ -#define TC2_BYTEM1_bp 1 /* Byte Mode bit 1 position. */ - -/* TC2.INTCTRLA bit masks and bit positions */ -#define TC2_HUNFINTLVL_gm 0x0C /* High Byte Underflow Interrupt Level group mask. */ -#define TC2_HUNFINTLVL_gp 2 /* High Byte Underflow Interrupt Level group position. */ -#define TC2_HUNFINTLVL0_bm (1<<2) /* High Byte Underflow Interrupt Level bit 0 mask. */ -#define TC2_HUNFINTLVL0_bp 2 /* High Byte Underflow Interrupt Level bit 0 position. */ -#define TC2_HUNFINTLVL1_bm (1<<3) /* High Byte Underflow Interrupt Level bit 1 mask. */ -#define TC2_HUNFINTLVL1_bp 3 /* High Byte Underflow Interrupt Level bit 1 position. */ - -#define TC2_LUNFINTLVL_gm 0x03 /* Low Byte Underflow interrupt level group mask. */ -#define TC2_LUNFINTLVL_gp 0 /* Low Byte Underflow interrupt level group position. */ -#define TC2_LUNFINTLVL0_bm (1<<0) /* Low Byte Underflow interrupt level bit 0 mask. */ -#define TC2_LUNFINTLVL0_bp 0 /* Low Byte Underflow interrupt level bit 0 position. */ -#define TC2_LUNFINTLVL1_bm (1<<1) /* Low Byte Underflow interrupt level bit 1 mask. */ -#define TC2_LUNFINTLVL1_bp 1 /* Low Byte Underflow interrupt level bit 1 position. */ - -/* TC2.INTCTRLB bit masks and bit positions */ -#define TC2_LCMPDINTLVL_gm 0xC0 /* Low Byte Compare D Interrupt Level group mask. */ -#define TC2_LCMPDINTLVL_gp 6 /* Low Byte Compare D Interrupt Level group position. */ -#define TC2_LCMPDINTLVL0_bm (1<<6) /* Low Byte Compare D Interrupt Level bit 0 mask. */ -#define TC2_LCMPDINTLVL0_bp 6 /* Low Byte Compare D Interrupt Level bit 0 position. */ -#define TC2_LCMPDINTLVL1_bm (1<<7) /* Low Byte Compare D Interrupt Level bit 1 mask. */ -#define TC2_LCMPDINTLVL1_bp 7 /* Low Byte Compare D Interrupt Level bit 1 position. */ - -#define TC2_LCMPCINTLVL_gm 0x30 /* Low Byte Compare C Interrupt Level group mask. */ -#define TC2_LCMPCINTLVL_gp 4 /* Low Byte Compare C Interrupt Level group position. */ -#define TC2_LCMPCINTLVL0_bm (1<<4) /* Low Byte Compare C Interrupt Level bit 0 mask. */ -#define TC2_LCMPCINTLVL0_bp 4 /* Low Byte Compare C Interrupt Level bit 0 position. */ -#define TC2_LCMPCINTLVL1_bm (1<<5) /* Low Byte Compare C Interrupt Level bit 1 mask. */ -#define TC2_LCMPCINTLVL1_bp 5 /* Low Byte Compare C Interrupt Level bit 1 position. */ - -#define TC2_LCMPBINTLVL_gm 0x0C /* Low Byte Compare B Interrupt Level group mask. */ -#define TC2_LCMPBINTLVL_gp 2 /* Low Byte Compare B Interrupt Level group position. */ -#define TC2_LCMPBINTLVL0_bm (1<<2) /* Low Byte Compare B Interrupt Level bit 0 mask. */ -#define TC2_LCMPBINTLVL0_bp 2 /* Low Byte Compare B Interrupt Level bit 0 position. */ -#define TC2_LCMPBINTLVL1_bm (1<<3) /* Low Byte Compare B Interrupt Level bit 1 mask. */ -#define TC2_LCMPBINTLVL1_bp 3 /* Low Byte Compare B Interrupt Level bit 1 position. */ - -#define TC2_LCMPAINTLVL_gm 0x03 /* Low Byte Compare A Interrupt Level group mask. */ -#define TC2_LCMPAINTLVL_gp 0 /* Low Byte Compare A Interrupt Level group position. */ -#define TC2_LCMPAINTLVL0_bm (1<<0) /* Low Byte Compare A Interrupt Level bit 0 mask. */ -#define TC2_LCMPAINTLVL0_bp 0 /* Low Byte Compare A Interrupt Level bit 0 position. */ -#define TC2_LCMPAINTLVL1_bm (1<<1) /* Low Byte Compare A Interrupt Level bit 1 mask. */ -#define TC2_LCMPAINTLVL1_bp 1 /* Low Byte Compare A Interrupt Level bit 1 position. */ - -/* TC2.CTRLF bit masks and bit positions */ -#define TC2_CMD_gm 0x0C /* Command group mask. */ -#define TC2_CMD_gp 2 /* Command group position. */ -#define TC2_CMD0_bm (1<<2) /* Command bit 0 mask. */ -#define TC2_CMD0_bp 2 /* Command bit 0 position. */ -#define TC2_CMD1_bm (1<<3) /* Command bit 1 mask. */ -#define TC2_CMD1_bp 3 /* Command bit 1 position. */ - -#define TC2_CMDEN_gm 0x03 /* Command Enable group mask. */ -#define TC2_CMDEN_gp 0 /* Command Enable group position. */ -#define TC2_CMDEN0_bm (1<<0) /* Command Enable bit 0 mask. */ -#define TC2_CMDEN0_bp 0 /* Command Enable bit 0 position. */ -#define TC2_CMDEN1_bm (1<<1) /* Command Enable bit 1 mask. */ -#define TC2_CMDEN1_bp 1 /* Command Enable bit 1 position. */ - -/* TC2.INTFLAGS bit masks and bit positions */ -#define TC2_LCMPDIF_bm 0x80 /* Low Byte Compare D Interrupt Flag bit mask. */ -#define TC2_LCMPDIF_bp 7 /* Low Byte Compare D Interrupt Flag bit position. */ - -#define TC2_LCMPCIF_bm 0x40 /* Low Byte Compare C Interrupt Flag bit mask. */ -#define TC2_LCMPCIF_bp 6 /* Low Byte Compare C Interrupt Flag bit position. */ - -#define TC2_LCMPBIF_bm 0x20 /* Low Byte Compare B Interrupt Flag bit mask. */ -#define TC2_LCMPBIF_bp 5 /* Low Byte Compare B Interrupt Flag bit position. */ - -#define TC2_LCMPAIF_bm 0x10 /* Low Byte Compare A Interrupt Flag bit mask. */ -#define TC2_LCMPAIF_bp 4 /* Low Byte Compare A Interrupt Flag bit position. */ - -#define TC2_HUNFIF_bm 0x02 /* High Byte Underflow Interrupt Flag bit mask. */ -#define TC2_HUNFIF_bp 1 /* High Byte Underflow Interrupt Flag bit position. */ - -#define TC2_LUNFIF_bm 0x01 /* Low Byte Underflow Interrupt Flag bit mask. */ -#define TC2_LUNFIF_bp 0 /* Low Byte Underflow Interrupt Flag bit position. */ - -/* AWEX - Timer/Counter Advanced Waveform Extension */ -/* AWEX.CTRL bit masks and bit positions */ -#define AWEX_PGM_bm 0x20 /* Pattern Generation Mode bit mask. */ -#define AWEX_PGM_bp 5 /* Pattern Generation Mode bit position. */ - -#define AWEX_CWCM_bm 0x10 /* Common Waveform Channel Mode bit mask. */ -#define AWEX_CWCM_bp 4 /* Common Waveform Channel Mode bit position. */ - -#define AWEX_DTICCDEN_bm 0x08 /* Dead Time Insertion Compare Channel D Enable bit mask. */ -#define AWEX_DTICCDEN_bp 3 /* Dead Time Insertion Compare Channel D Enable bit position. */ - -#define AWEX_DTICCCEN_bm 0x04 /* Dead Time Insertion Compare Channel C Enable bit mask. */ -#define AWEX_DTICCCEN_bp 2 /* Dead Time Insertion Compare Channel C Enable bit position. */ - -#define AWEX_DTICCBEN_bm 0x02 /* Dead Time Insertion Compare Channel B Enable bit mask. */ -#define AWEX_DTICCBEN_bp 1 /* Dead Time Insertion Compare Channel B Enable bit position. */ - -#define AWEX_DTICCAEN_bm 0x01 /* Dead Time Insertion Compare Channel A Enable bit mask. */ -#define AWEX_DTICCAEN_bp 0 /* Dead Time Insertion Compare Channel A Enable bit position. */ - -/* AWEX.FDCTRL bit masks and bit positions */ -#define AWEX_FDDBD_bm 0x10 /* Fault Detect on Disable Break Disable bit mask. */ -#define AWEX_FDDBD_bp 4 /* Fault Detect on Disable Break Disable bit position. */ - -#define AWEX_FDMODE_bm 0x04 /* Fault Detect Mode bit mask. */ -#define AWEX_FDMODE_bp 2 /* Fault Detect Mode bit position. */ - -#define AWEX_FDACT_gm 0x03 /* Fault Detect Action group mask. */ -#define AWEX_FDACT_gp 0 /* Fault Detect Action group position. */ -#define AWEX_FDACT0_bm (1<<0) /* Fault Detect Action bit 0 mask. */ -#define AWEX_FDACT0_bp 0 /* Fault Detect Action bit 0 position. */ -#define AWEX_FDACT1_bm (1<<1) /* Fault Detect Action bit 1 mask. */ -#define AWEX_FDACT1_bp 1 /* Fault Detect Action bit 1 position. */ - -/* AWEX.STATUS bit masks and bit positions */ -#define AWEX_FDF_bm 0x04 /* Fault Detect Flag bit mask. */ -#define AWEX_FDF_bp 2 /* Fault Detect Flag bit position. */ - -#define AWEX_DTHSBUFV_bm 0x02 /* Dead Time High Side Buffer Valid bit mask. */ -#define AWEX_DTHSBUFV_bp 1 /* Dead Time High Side Buffer Valid bit position. */ - -#define AWEX_DTLSBUFV_bm 0x01 /* Dead Time Low Side Buffer Valid bit mask. */ -#define AWEX_DTLSBUFV_bp 0 /* Dead Time Low Side Buffer Valid bit position. */ - -/* AWEX.STATUSSET bit masks and bit positions */ -/* AWEX_FDF Predefined. */ -/* AWEX_FDF Predefined. */ - -/* AWEX_DTHSBUFV Predefined. */ -/* AWEX_DTHSBUFV Predefined. */ - -/* AWEX_DTLSBUFV Predefined. */ -/* AWEX_DTLSBUFV Predefined. */ - -/* HIRES - Timer/Counter High-Resolution Extension */ -/* HIRES.CTRLA bit masks and bit positions */ -#define HIRES_HREN_gm 0x03 /* High Resolution Enable group mask. */ -#define HIRES_HREN_gp 0 /* High Resolution Enable group position. */ -#define HIRES_HREN0_bm (1<<0) /* High Resolution Enable bit 0 mask. */ -#define HIRES_HREN0_bp 0 /* High Resolution Enable bit 0 position. */ -#define HIRES_HREN1_bm (1<<1) /* High Resolution Enable bit 1 mask. */ -#define HIRES_HREN1_bp 1 /* High Resolution Enable bit 1 position. */ - -/* USART - Universal Asynchronous Receiver-Transmitter */ -/* USART.STATUS bit masks and bit positions */ -#define USART_RXCIF_bm 0x80 /* Receive Interrupt Flag bit mask. */ -#define USART_RXCIF_bp 7 /* Receive Interrupt Flag bit position. */ - -#define USART_TXCIF_bm 0x40 /* Transmit Interrupt Flag bit mask. */ -#define USART_TXCIF_bp 6 /* Transmit Interrupt Flag bit position. */ - -#define USART_DREIF_bm 0x20 /* Data Register Empty Flag bit mask. */ -#define USART_DREIF_bp 5 /* Data Register Empty Flag bit position. */ - -#define USART_FERR_bm 0x10 /* Frame Error bit mask. */ -#define USART_FERR_bp 4 /* Frame Error bit position. */ - -#define USART_BUFOVF_bm 0x08 /* Buffer Overflow bit mask. */ -#define USART_BUFOVF_bp 3 /* Buffer Overflow bit position. */ - -#define USART_PERR_bm 0x04 /* Parity Error bit mask. */ -#define USART_PERR_bp 2 /* Parity Error bit position. */ - -#define USART_RXB8_bm 0x01 /* Receive Bit 8 bit mask. */ -#define USART_RXB8_bp 0 /* Receive Bit 8 bit position. */ - -/* USART.CTRLA bit masks and bit positions */ -#define USART_RXCINTLVL_gm 0x30 /* Receive Interrupt Level group mask. */ -#define USART_RXCINTLVL_gp 4 /* Receive Interrupt Level group position. */ -#define USART_RXCINTLVL0_bm (1<<4) /* Receive Interrupt Level bit 0 mask. */ -#define USART_RXCINTLVL0_bp 4 /* Receive Interrupt Level bit 0 position. */ -#define USART_RXCINTLVL1_bm (1<<5) /* Receive Interrupt Level bit 1 mask. */ -#define USART_RXCINTLVL1_bp 5 /* Receive Interrupt Level bit 1 position. */ - -#define USART_TXCINTLVL_gm 0x0C /* Transmit Interrupt Level group mask. */ -#define USART_TXCINTLVL_gp 2 /* Transmit Interrupt Level group position. */ -#define USART_TXCINTLVL0_bm (1<<2) /* Transmit Interrupt Level bit 0 mask. */ -#define USART_TXCINTLVL0_bp 2 /* Transmit Interrupt Level bit 0 position. */ -#define USART_TXCINTLVL1_bm (1<<3) /* Transmit Interrupt Level bit 1 mask. */ -#define USART_TXCINTLVL1_bp 3 /* Transmit Interrupt Level bit 1 position. */ - -#define USART_DREINTLVL_gm 0x03 /* Data Register Empty Interrupt Level group mask. */ -#define USART_DREINTLVL_gp 0 /* Data Register Empty Interrupt Level group position. */ -#define USART_DREINTLVL0_bm (1<<0) /* Data Register Empty Interrupt Level bit 0 mask. */ -#define USART_DREINTLVL0_bp 0 /* Data Register Empty Interrupt Level bit 0 position. */ -#define USART_DREINTLVL1_bm (1<<1) /* Data Register Empty Interrupt Level bit 1 mask. */ -#define USART_DREINTLVL1_bp 1 /* Data Register Empty Interrupt Level bit 1 position. */ - -/* USART.CTRLB bit masks and bit positions */ -#define USART_RXEN_bm 0x10 /* Receiver Enable bit mask. */ -#define USART_RXEN_bp 4 /* Receiver Enable bit position. */ - -#define USART_TXEN_bm 0x08 /* Transmitter Enable bit mask. */ -#define USART_TXEN_bp 3 /* Transmitter Enable bit position. */ - -#define USART_CLK2X_bm 0x04 /* Double transmission speed bit mask. */ -#define USART_CLK2X_bp 2 /* Double transmission speed bit position. */ - -#define USART_MPCM_bm 0x02 /* Multi-processor Communication Mode bit mask. */ -#define USART_MPCM_bp 1 /* Multi-processor Communication Mode bit position. */ - -#define USART_TXB8_bm 0x01 /* Transmit bit 8 bit mask. */ -#define USART_TXB8_bp 0 /* Transmit bit 8 bit position. */ - -/* USART.CTRLC bit masks and bit positions */ -#define USART_CMODE_gm 0xC0 /* Communication Mode group mask. */ -#define USART_CMODE_gp 6 /* Communication Mode group position. */ -#define USART_CMODE0_bm (1<<6) /* Communication Mode bit 0 mask. */ -#define USART_CMODE0_bp 6 /* Communication Mode bit 0 position. */ -#define USART_CMODE1_bm (1<<7) /* Communication Mode bit 1 mask. */ -#define USART_CMODE1_bp 7 /* Communication Mode bit 1 position. */ - -#define USART_PMODE_gm 0x30 /* Parity Mode group mask. */ -#define USART_PMODE_gp 4 /* Parity Mode group position. */ -#define USART_PMODE0_bm (1<<4) /* Parity Mode bit 0 mask. */ -#define USART_PMODE0_bp 4 /* Parity Mode bit 0 position. */ -#define USART_PMODE1_bm (1<<5) /* Parity Mode bit 1 mask. */ -#define USART_PMODE1_bp 5 /* Parity Mode bit 1 position. */ - -#define USART_SBMODE_bm 0x08 /* Stop Bit Mode bit mask. */ -#define USART_SBMODE_bp 3 /* Stop Bit Mode bit position. */ - -#define USART_CHSIZE_gm 0x07 /* Character Size group mask. */ -#define USART_CHSIZE_gp 0 /* Character Size group position. */ -#define USART_CHSIZE0_bm (1<<0) /* Character Size bit 0 mask. */ -#define USART_CHSIZE0_bp 0 /* Character Size bit 0 position. */ -#define USART_CHSIZE1_bm (1<<1) /* Character Size bit 1 mask. */ -#define USART_CHSIZE1_bp 1 /* Character Size bit 1 position. */ -#define USART_CHSIZE2_bm (1<<2) /* Character Size bit 2 mask. */ -#define USART_CHSIZE2_bp 2 /* Character Size bit 2 position. */ - -/* USART.BAUDCTRLA bit masks and bit positions */ -#define USART_BSEL_gm 0xFF /* Baud Rate Selection Bits [7:0] group mask. */ -#define USART_BSEL_gp 0 /* Baud Rate Selection Bits [7:0] group position. */ -#define USART_BSEL0_bm (1<<0) /* Baud Rate Selection Bits [7:0] bit 0 mask. */ -#define USART_BSEL0_bp 0 /* Baud Rate Selection Bits [7:0] bit 0 position. */ -#define USART_BSEL1_bm (1<<1) /* Baud Rate Selection Bits [7:0] bit 1 mask. */ -#define USART_BSEL1_bp 1 /* Baud Rate Selection Bits [7:0] bit 1 position. */ -#define USART_BSEL2_bm (1<<2) /* Baud Rate Selection Bits [7:0] bit 2 mask. */ -#define USART_BSEL2_bp 2 /* Baud Rate Selection Bits [7:0] bit 2 position. */ -#define USART_BSEL3_bm (1<<3) /* Baud Rate Selection Bits [7:0] bit 3 mask. */ -#define USART_BSEL3_bp 3 /* Baud Rate Selection Bits [7:0] bit 3 position. */ -#define USART_BSEL4_bm (1<<4) /* Baud Rate Selection Bits [7:0] bit 4 mask. */ -#define USART_BSEL4_bp 4 /* Baud Rate Selection Bits [7:0] bit 4 position. */ -#define USART_BSEL5_bm (1<<5) /* Baud Rate Selection Bits [7:0] bit 5 mask. */ -#define USART_BSEL5_bp 5 /* Baud Rate Selection Bits [7:0] bit 5 position. */ -#define USART_BSEL6_bm (1<<6) /* Baud Rate Selection Bits [7:0] bit 6 mask. */ -#define USART_BSEL6_bp 6 /* Baud Rate Selection Bits [7:0] bit 6 position. */ -#define USART_BSEL7_bm (1<<7) /* Baud Rate Selection Bits [7:0] bit 7 mask. */ -#define USART_BSEL7_bp 7 /* Baud Rate Selection Bits [7:0] bit 7 position. */ - -/* USART.BAUDCTRLB bit masks and bit positions */ -#define USART_BSCALE_gm 0xF0 /* Baud Rate Scale group mask. */ -#define USART_BSCALE_gp 4 /* Baud Rate Scale group position. */ -#define USART_BSCALE0_bm (1<<4) /* Baud Rate Scale bit 0 mask. */ -#define USART_BSCALE0_bp 4 /* Baud Rate Scale bit 0 position. */ -#define USART_BSCALE1_bm (1<<5) /* Baud Rate Scale bit 1 mask. */ -#define USART_BSCALE1_bp 5 /* Baud Rate Scale bit 1 position. */ -#define USART_BSCALE2_bm (1<<6) /* Baud Rate Scale bit 2 mask. */ -#define USART_BSCALE2_bp 6 /* Baud Rate Scale bit 2 position. */ -#define USART_BSCALE3_bm (1<<7) /* Baud Rate Scale bit 3 mask. */ -#define USART_BSCALE3_bp 7 /* Baud Rate Scale bit 3 position. */ - -/* USART_BSEL Predefined. */ -/* USART_BSEL Predefined. */ - -/* SPI - Serial Peripheral Interface */ -/* SPI.CTRL bit masks and bit positions */ -#define SPI_CLK2X_bm 0x80 /* Enable Double Speed bit mask. */ -#define SPI_CLK2X_bp 7 /* Enable Double Speed bit position. */ - -#define SPI_ENABLE_bm 0x40 /* Enable Module bit mask. */ -#define SPI_ENABLE_bp 6 /* Enable Module bit position. */ - -#define SPI_DORD_bm 0x20 /* Data Order Setting bit mask. */ -#define SPI_DORD_bp 5 /* Data Order Setting bit position. */ - -#define SPI_MASTER_bm 0x10 /* Master Operation Enable bit mask. */ -#define SPI_MASTER_bp 4 /* Master Operation Enable bit position. */ - -#define SPI_MODE_gm 0x0C /* SPI Mode group mask. */ -#define SPI_MODE_gp 2 /* SPI Mode group position. */ -#define SPI_MODE0_bm (1<<2) /* SPI Mode bit 0 mask. */ -#define SPI_MODE0_bp 2 /* SPI Mode bit 0 position. */ -#define SPI_MODE1_bm (1<<3) /* SPI Mode bit 1 mask. */ -#define SPI_MODE1_bp 3 /* SPI Mode bit 1 position. */ - -#define SPI_PRESCALER_gm 0x03 /* Prescaler group mask. */ -#define SPI_PRESCALER_gp 0 /* Prescaler group position. */ -#define SPI_PRESCALER0_bm (1<<0) /* Prescaler bit 0 mask. */ -#define SPI_PRESCALER0_bp 0 /* Prescaler bit 0 position. */ -#define SPI_PRESCALER1_bm (1<<1) /* Prescaler bit 1 mask. */ -#define SPI_PRESCALER1_bp 1 /* Prescaler bit 1 position. */ - -/* SPI.INTCTRL bit masks and bit positions */ -#define SPI_INTLVL_gm 0x03 /* Interrupt level group mask. */ -#define SPI_INTLVL_gp 0 /* Interrupt level group position. */ -#define SPI_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */ -#define SPI_INTLVL0_bp 0 /* Interrupt level bit 0 position. */ -#define SPI_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */ -#define SPI_INTLVL1_bp 1 /* Interrupt level bit 1 position. */ - -/* SPI.STATUS bit masks and bit positions */ -#define SPI_IF_bm 0x80 /* Interrupt Flag bit mask. */ -#define SPI_IF_bp 7 /* Interrupt Flag bit position. */ - -#define SPI_WRCOL_bm 0x40 /* Write Collision bit mask. */ -#define SPI_WRCOL_bp 6 /* Write Collision bit position. */ - -/* IRCOM - IR Communication Module */ -/* IRCOM.CTRL bit masks and bit positions */ -#define IRCOM_EVSEL_gm 0x0F /* Event Channel Select group mask. */ -#define IRCOM_EVSEL_gp 0 /* Event Channel Select group position. */ -#define IRCOM_EVSEL0_bm (1<<0) /* Event Channel Select bit 0 mask. */ -#define IRCOM_EVSEL0_bp 0 /* Event Channel Select bit 0 position. */ -#define IRCOM_EVSEL1_bm (1<<1) /* Event Channel Select bit 1 mask. */ -#define IRCOM_EVSEL1_bp 1 /* Event Channel Select bit 1 position. */ -#define IRCOM_EVSEL2_bm (1<<2) /* Event Channel Select bit 2 mask. */ -#define IRCOM_EVSEL2_bp 2 /* Event Channel Select bit 2 position. */ -#define IRCOM_EVSEL3_bm (1<<3) /* Event Channel Select bit 3 mask. */ -#define IRCOM_EVSEL3_bp 3 /* Event Channel Select bit 3 position. */ - -/* FUSE - Fuses and Lockbits */ -/* NVM_FUSES.FUSEBYTE1 bit masks and bit positions */ -#define NVM_FUSES_WDWP_gm 0xF0 /* Watchdog Window Timeout Period group mask. */ -#define NVM_FUSES_WDWP_gp 4 /* Watchdog Window Timeout Period group position. */ -#define NVM_FUSES_WDWP0_bm (1<<4) /* Watchdog Window Timeout Period bit 0 mask. */ -#define NVM_FUSES_WDWP0_bp 4 /* Watchdog Window Timeout Period bit 0 position. */ -#define NVM_FUSES_WDWP1_bm (1<<5) /* Watchdog Window Timeout Period bit 1 mask. */ -#define NVM_FUSES_WDWP1_bp 5 /* Watchdog Window Timeout Period bit 1 position. */ -#define NVM_FUSES_WDWP2_bm (1<<6) /* Watchdog Window Timeout Period bit 2 mask. */ -#define NVM_FUSES_WDWP2_bp 6 /* Watchdog Window Timeout Period bit 2 position. */ -#define NVM_FUSES_WDWP3_bm (1<<7) /* Watchdog Window Timeout Period bit 3 mask. */ -#define NVM_FUSES_WDWP3_bp 7 /* Watchdog Window Timeout Period bit 3 position. */ - -#define NVM_FUSES_WDP_gm 0x0F /* Watchdog Timeout Period group mask. */ -#define NVM_FUSES_WDP_gp 0 /* Watchdog Timeout Period group position. */ -#define NVM_FUSES_WDP0_bm (1<<0) /* Watchdog Timeout Period bit 0 mask. */ -#define NVM_FUSES_WDP0_bp 0 /* Watchdog Timeout Period bit 0 position. */ -#define NVM_FUSES_WDP1_bm (1<<1) /* Watchdog Timeout Period bit 1 mask. */ -#define NVM_FUSES_WDP1_bp 1 /* Watchdog Timeout Period bit 1 position. */ -#define NVM_FUSES_WDP2_bm (1<<2) /* Watchdog Timeout Period bit 2 mask. */ -#define NVM_FUSES_WDP2_bp 2 /* Watchdog Timeout Period bit 2 position. */ -#define NVM_FUSES_WDP3_bm (1<<3) /* Watchdog Timeout Period bit 3 mask. */ -#define NVM_FUSES_WDP3_bp 3 /* Watchdog Timeout Period bit 3 position. */ - -/* NVM_FUSES.FUSEBYTE2 bit masks and bit positions */ -#define NVM_FUSES_BOOTRST_bm 0x40 /* Boot Loader Section Reset Vector bit mask. */ -#define NVM_FUSES_BOOTRST_bp 6 /* Boot Loader Section Reset Vector bit position. */ - -#define NVM_FUSES_TOSCSEL_bm 0x20 /* Timer Oscillator pin location bit mask. */ -#define NVM_FUSES_TOSCSEL_bp 5 /* Timer Oscillator pin location bit position. */ - -#define NVM_FUSES_BODPD_gm 0x03 /* BOD Operation in Power-Down Mode group mask. */ -#define NVM_FUSES_BODPD_gp 0 /* BOD Operation in Power-Down Mode group position. */ -#define NVM_FUSES_BODPD0_bm (1<<0) /* BOD Operation in Power-Down Mode bit 0 mask. */ -#define NVM_FUSES_BODPD0_bp 0 /* BOD Operation in Power-Down Mode bit 0 position. */ -#define NVM_FUSES_BODPD1_bm (1<<1) /* BOD Operation in Power-Down Mode bit 1 mask. */ -#define NVM_FUSES_BODPD1_bp 1 /* BOD Operation in Power-Down Mode bit 1 position. */ - -/* NVM_FUSES.FUSEBYTE4 bit masks and bit positions */ -#define NVM_FUSES_RSTDISBL_bm 0x10 /* External Reset Disable bit mask. */ -#define NVM_FUSES_RSTDISBL_bp 4 /* External Reset Disable bit position. */ - -#define NVM_FUSES_SUT_gm 0x0C /* Start-up Time group mask. */ -#define NVM_FUSES_SUT_gp 2 /* Start-up Time group position. */ -#define NVM_FUSES_SUT0_bm (1<<2) /* Start-up Time bit 0 mask. */ -#define NVM_FUSES_SUT0_bp 2 /* Start-up Time bit 0 position. */ -#define NVM_FUSES_SUT1_bm (1<<3) /* Start-up Time bit 1 mask. */ -#define NVM_FUSES_SUT1_bp 3 /* Start-up Time bit 1 position. */ - -#define NVM_FUSES_WDLOCK_bm 0x02 /* Watchdog Timer Lock bit mask. */ -#define NVM_FUSES_WDLOCK_bp 1 /* Watchdog Timer Lock bit position. */ - -/* NVM_FUSES.FUSEBYTE5 bit masks and bit positions */ -#define NVM_FUSES_BODACT_gm 0x30 /* BOD Operation in Active Mode group mask. */ -#define NVM_FUSES_BODACT_gp 4 /* BOD Operation in Active Mode group position. */ -#define NVM_FUSES_BODACT0_bm (1<<4) /* BOD Operation in Active Mode bit 0 mask. */ -#define NVM_FUSES_BODACT0_bp 4 /* BOD Operation in Active Mode bit 0 position. */ -#define NVM_FUSES_BODACT1_bm (1<<5) /* BOD Operation in Active Mode bit 1 mask. */ -#define NVM_FUSES_BODACT1_bp 5 /* BOD Operation in Active Mode bit 1 position. */ - -#define NVM_FUSES_EESAVE_bm 0x08 /* Preserve EEPROM Through Chip Erase bit mask. */ -#define NVM_FUSES_EESAVE_bp 3 /* Preserve EEPROM Through Chip Erase bit position. */ - -#define NVM_FUSES_BODLVL_gm 0x07 /* Brownout Detection Voltage Level group mask. */ -#define NVM_FUSES_BODLVL_gp 0 /* Brownout Detection Voltage Level group position. */ -#define NVM_FUSES_BODLVL0_bm (1<<0) /* Brownout Detection Voltage Level bit 0 mask. */ -#define NVM_FUSES_BODLVL0_bp 0 /* Brownout Detection Voltage Level bit 0 position. */ -#define NVM_FUSES_BODLVL1_bm (1<<1) /* Brownout Detection Voltage Level bit 1 mask. */ -#define NVM_FUSES_BODLVL1_bp 1 /* Brownout Detection Voltage Level bit 1 position. */ -#define NVM_FUSES_BODLVL2_bm (1<<2) /* Brownout Detection Voltage Level bit 2 mask. */ -#define NVM_FUSES_BODLVL2_bp 2 /* Brownout Detection Voltage Level bit 2 position. */ - -/* LOCKBIT - Fuses and Lockbits */ -/* NVM_LOCKBITS.LOCKBITS bit masks and bit positions */ -#define NVM_LOCKBITS_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ -#define NVM_LOCKBITS_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ -#define NVM_LOCKBITS_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ -#define NVM_LOCKBITS_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ -#define NVM_LOCKBITS_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ -#define NVM_LOCKBITS_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ - -#define NVM_LOCKBITS_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ -#define NVM_LOCKBITS_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ -#define NVM_LOCKBITS_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ -#define NVM_LOCKBITS_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ -#define NVM_LOCKBITS_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ -#define NVM_LOCKBITS_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ - -#define NVM_LOCKBITS_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ -#define NVM_LOCKBITS_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ -#define NVM_LOCKBITS_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ -#define NVM_LOCKBITS_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ -#define NVM_LOCKBITS_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ -#define NVM_LOCKBITS_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ - -#define NVM_LOCKBITS_LB_gm 0x03 /* Lock Bits group mask. */ -#define NVM_LOCKBITS_LB_gp 0 /* Lock Bits group position. */ -#define NVM_LOCKBITS_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ -#define NVM_LOCKBITS_LB0_bp 0 /* Lock Bits bit 0 position. */ -#define NVM_LOCKBITS_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ -#define NVM_LOCKBITS_LB1_bp 1 /* Lock Bits bit 1 position. */ - - - -// Generic Port Pins - -#define PIN0_bm 0x01 -#define PIN0_bp 0 -#define PIN1_bm 0x02 -#define PIN1_bp 1 -#define PIN2_bm 0x04 -#define PIN2_bp 2 -#define PIN3_bm 0x08 -#define PIN3_bp 3 -#define PIN4_bm 0x10 -#define PIN4_bp 4 -#define PIN5_bm 0x20 -#define PIN5_bp 5 -#define PIN6_bm 0x40 -#define PIN6_bp 6 -#define PIN7_bm 0x80 -#define PIN7_bp 7 - -/* ========== Interrupt Vector Definitions ========== */ -/* Vector 0 is the reset vector */ - -/* OSC interrupt vectors */ -#define OSC_OSCF_vect_num 1 -#define OSC_OSCF_vect _VECTOR(1) /* Oscillator Failure Interrupt (NMI) */ - -/* PORTC interrupt vectors */ -#define PORTC_INT0_vect_num 2 -#define PORTC_INT0_vect _VECTOR(2) /* External Interrupt 0 */ -#define PORTC_INT1_vect_num 3 -#define PORTC_INT1_vect _VECTOR(3) /* External Interrupt 1 */ - -/* PORTR interrupt vectors */ -#define PORTR_INT0_vect_num 4 -#define PORTR_INT0_vect _VECTOR(4) /* External Interrupt 0 */ -#define PORTR_INT1_vect_num 5 -#define PORTR_INT1_vect _VECTOR(5) /* External Interrupt 1 */ - -/* DMA interrupt vectors */ -#define DMA_CH0_vect_num 6 -#define DMA_CH0_vect _VECTOR(6) /* Channel 0 Interrupt */ -#define DMA_CH1_vect_num 7 -#define DMA_CH1_vect _VECTOR(7) /* Channel 1 Interrupt */ - -/* RTC interrupt vectors */ -#define RTC_OVF_vect_num 10 -#define RTC_OVF_vect _VECTOR(10) /* Overflow Interrupt */ -#define RTC_COMP_vect_num 11 -#define RTC_COMP_vect _VECTOR(11) /* Compare Interrupt */ - -/* TWIC interrupt vectors */ -#define TWIC_TWIS_vect_num 12 -#define TWIC_TWIS_vect _VECTOR(12) /* TWI Slave Interrupt */ -#define TWIC_TWIM_vect_num 13 -#define TWIC_TWIM_vect _VECTOR(13) /* TWI Master Interrupt */ - -/* TCC0 interrupt vectors */ -#define TCC0_OVF_vect_num 14 -#define TCC0_OVF_vect _VECTOR(14) /* Overflow Interrupt */ - -/* TCC2 interrupt vectors */ -#define TCC2_LUNF_vect_num 14 -#define TCC2_LUNF_vect _VECTOR(14) /* Low Byte Underflow Interrupt */ - -/* TCC0 interrupt vectors */ -#define TCC0_ERR_vect_num 15 -#define TCC0_ERR_vect _VECTOR(15) /* Error Interrupt */ - -/* TCC2 interrupt vectors */ -#define TCC2_HUNF_vect_num 15 -#define TCC2_HUNF_vect _VECTOR(15) /* High Byte Underflow Interrupt */ - -/* TCC0 interrupt vectors */ -#define TCC0_CCA_vect_num 16 -#define TCC0_CCA_vect _VECTOR(16) /* Compare or Capture A Interrupt */ - -/* TCC2 interrupt vectors */ -#define TCC2_LCMPA_vect_num 16 -#define TCC2_LCMPA_vect _VECTOR(16) /* Low Byte Compare A Interrupt */ - -/* TCC0 interrupt vectors */ -#define TCC0_CCB_vect_num 17 -#define TCC0_CCB_vect _VECTOR(17) /* Compare or Capture B Interrupt */ - -/* TCC2 interrupt vectors */ -#define TCC2_LCMPB_vect_num 17 -#define TCC2_LCMPB_vect _VECTOR(17) /* Low Byte Compare B Interrupt */ - -/* TCC0 interrupt vectors */ -#define TCC0_CCC_vect_num 18 -#define TCC0_CCC_vect _VECTOR(18) /* Compare or Capture C Interrupt */ - -/* TCC2 interrupt vectors */ -#define TCC2_LCMPC_vect_num 18 -#define TCC2_LCMPC_vect _VECTOR(18) /* Low Byte Compare C Interrupt */ - -/* TCC0 interrupt vectors */ -#define TCC0_CCD_vect_num 19 -#define TCC0_CCD_vect _VECTOR(19) /* Compare or Capture D Interrupt */ - -/* TCC2 interrupt vectors */ -#define TCC2_LCMPD_vect_num 19 -#define TCC2_LCMPD_vect _VECTOR(19) /* Low Byte Compare D Interrupt */ - -/* TCC1 interrupt vectors */ -#define TCC1_OVF_vect_num 20 -#define TCC1_OVF_vect _VECTOR(20) /* Overflow Interrupt */ -#define TCC1_ERR_vect_num 21 -#define TCC1_ERR_vect _VECTOR(21) /* Error Interrupt */ -#define TCC1_CCA_vect_num 22 -#define TCC1_CCA_vect _VECTOR(22) /* Compare or Capture A Interrupt */ -#define TCC1_CCB_vect_num 23 -#define TCC1_CCB_vect _VECTOR(23) /* Compare or Capture B Interrupt */ - -/* SPIC interrupt vectors */ -#define SPIC_INT_vect_num 24 -#define SPIC_INT_vect _VECTOR(24) /* SPI Interrupt */ - -/* USARTC0 interrupt vectors */ -#define USARTC0_RXC_vect_num 25 -#define USARTC0_RXC_vect _VECTOR(25) /* Reception Complete Interrupt */ -#define USARTC0_DRE_vect_num 26 -#define USARTC0_DRE_vect _VECTOR(26) /* Data Register Empty Interrupt */ -#define USARTC0_TXC_vect_num 27 -#define USARTC0_TXC_vect _VECTOR(27) /* Transmission Complete Interrupt */ - -/* USARTC1 interrupt vectors */ -#define USARTC1_RXC_vect_num 28 -#define USARTC1_RXC_vect _VECTOR(28) /* Reception Complete Interrupt */ -#define USARTC1_DRE_vect_num 29 -#define USARTC1_DRE_vect _VECTOR(29) /* Data Register Empty Interrupt */ -#define USARTC1_TXC_vect_num 30 -#define USARTC1_TXC_vect _VECTOR(30) /* Transmission Complete Interrupt */ - -/* AES interrupt vectors */ -#define AES_INT_vect_num 31 -#define AES_INT_vect _VECTOR(31) /* AES Interrupt */ - -/* NVM interrupt vectors */ -#define NVM_EE_vect_num 32 -#define NVM_EE_vect _VECTOR(32) /* EE Interrupt */ -#define NVM_SPM_vect_num 33 -#define NVM_SPM_vect _VECTOR(33) /* SPM Interrupt */ - -/* PORTB interrupt vectors */ -#define PORTB_INT0_vect_num 34 -#define PORTB_INT0_vect _VECTOR(34) /* External Interrupt 0 */ -#define PORTB_INT1_vect_num 35 -#define PORTB_INT1_vect _VECTOR(35) /* External Interrupt 1 */ - -/* PORTE interrupt vectors */ -#define PORTE_INT0_vect_num 43 -#define PORTE_INT0_vect _VECTOR(43) /* External Interrupt 0 */ -#define PORTE_INT1_vect_num 44 -#define PORTE_INT1_vect _VECTOR(44) /* External Interrupt 1 */ - -/* TWIE interrupt vectors */ -#define TWIE_TWIS_vect_num 45 -#define TWIE_TWIS_vect _VECTOR(45) /* TWI Slave Interrupt */ -#define TWIE_TWIM_vect_num 46 -#define TWIE_TWIM_vect _VECTOR(46) /* TWI Master Interrupt */ - -/* TCE0 interrupt vectors */ -#define TCE0_OVF_vect_num 47 -#define TCE0_OVF_vect _VECTOR(47) /* Overflow Interrupt */ - -/* TCE2 interrupt vectors */ -#define TCE2_LUNF_vect_num 47 -#define TCE2_LUNF_vect _VECTOR(47) /* Low Byte Underflow Interrupt */ - -/* TCE0 interrupt vectors */ -#define TCE0_ERR_vect_num 48 -#define TCE0_ERR_vect _VECTOR(48) /* Error Interrupt */ - -/* TCE2 interrupt vectors */ -#define TCE2_HUNF_vect_num 48 -#define TCE2_HUNF_vect _VECTOR(48) /* High Byte Underflow Interrupt */ - -/* TCE0 interrupt vectors */ -#define TCE0_CCA_vect_num 49 -#define TCE0_CCA_vect _VECTOR(49) /* Compare or Capture A Interrupt */ - -/* TCE2 interrupt vectors */ -#define TCE2_LCMPA_vect_num 49 -#define TCE2_LCMPA_vect _VECTOR(49) /* Low Byte Compare A Interrupt */ - -/* TCE0 interrupt vectors */ -#define TCE0_CCB_vect_num 50 -#define TCE0_CCB_vect _VECTOR(50) /* Compare or Capture B Interrupt */ - -/* TCE2 interrupt vectors */ -#define TCE2_LCMPB_vect_num 50 -#define TCE2_LCMPB_vect _VECTOR(50) /* Low Byte Compare B Interrupt */ - -/* TCE0 interrupt vectors */ -#define TCE0_CCC_vect_num 51 -#define TCE0_CCC_vect _VECTOR(51) /* Compare or Capture C Interrupt */ - -/* TCE2 interrupt vectors */ -#define TCE2_LCMPC_vect_num 51 -#define TCE2_LCMPC_vect _VECTOR(51) /* Low Byte Compare C Interrupt */ - -/* TCE0 interrupt vectors */ -#define TCE0_CCD_vect_num 52 -#define TCE0_CCD_vect _VECTOR(52) /* Compare or Capture D Interrupt */ - -/* TCE2 interrupt vectors */ -#define TCE2_LCMPD_vect_num 52 -#define TCE2_LCMPD_vect _VECTOR(52) /* Low Byte Compare D Interrupt */ - -/* USARTE0 interrupt vectors */ -#define USARTE0_RXC_vect_num 58 -#define USARTE0_RXC_vect _VECTOR(58) /* Reception Complete Interrupt */ -#define USARTE0_DRE_vect_num 59 -#define USARTE0_DRE_vect _VECTOR(59) /* Data Register Empty Interrupt */ -#define USARTE0_TXC_vect_num 60 -#define USARTE0_TXC_vect _VECTOR(60) /* Transmission Complete Interrupt */ - -/* PORTD interrupt vectors */ -#define PORTD_INT0_vect_num 64 -#define PORTD_INT0_vect _VECTOR(64) /* External Interrupt 0 */ -#define PORTD_INT1_vect_num 65 -#define PORTD_INT1_vect _VECTOR(65) /* External Interrupt 1 */ - -/* PORTA interrupt vectors */ -#define PORTA_INT0_vect_num 66 -#define PORTA_INT0_vect _VECTOR(66) /* External Interrupt 0 */ -#define PORTA_INT1_vect_num 67 -#define PORTA_INT1_vect _VECTOR(67) /* External Interrupt 1 */ - -/* ACA interrupt vectors */ -#define ACA_AC0_vect_num 68 -#define ACA_AC0_vect _VECTOR(68) /* AC0 Interrupt */ -#define ACA_AC1_vect_num 69 -#define ACA_AC1_vect _VECTOR(69) /* AC1 Interrupt */ -#define ACA_ACW_vect_num 70 -#define ACA_ACW_vect _VECTOR(70) /* ACW Window Mode Interrupt */ - -/* ADCA interrupt vectors */ -#define ADCA_CH0_vect_num 71 -#define ADCA_CH0_vect _VECTOR(71) /* Interrupt 0 */ - -/* TCD0 interrupt vectors */ -#define TCD0_OVF_vect_num 77 -#define TCD0_OVF_vect _VECTOR(77) /* Overflow Interrupt */ - -/* TCD2 interrupt vectors */ -#define TCD2_LUNF_vect_num 77 -#define TCD2_LUNF_vect _VECTOR(77) /* Low Byte Underflow Interrupt */ - -/* TCD0 interrupt vectors */ -#define TCD0_ERR_vect_num 78 -#define TCD0_ERR_vect _VECTOR(78) /* Error Interrupt */ - -/* TCD2 interrupt vectors */ -#define TCD2_HUNF_vect_num 78 -#define TCD2_HUNF_vect _VECTOR(78) /* High Byte Underflow Interrupt */ - -/* TCD0 interrupt vectors */ -#define TCD0_CCA_vect_num 79 -#define TCD0_CCA_vect _VECTOR(79) /* Compare or Capture A Interrupt */ - -/* TCD2 interrupt vectors */ -#define TCD2_LCMPA_vect_num 79 -#define TCD2_LCMPA_vect _VECTOR(79) /* Low Byte Compare A Interrupt */ - -/* TCD0 interrupt vectors */ -#define TCD0_CCB_vect_num 80 -#define TCD0_CCB_vect _VECTOR(80) /* Compare or Capture B Interrupt */ - -/* TCD2 interrupt vectors */ -#define TCD2_LCMPB_vect_num 80 -#define TCD2_LCMPB_vect _VECTOR(80) /* Low Byte Compare B Interrupt */ - -/* TCD0 interrupt vectors */ -#define TCD0_CCC_vect_num 81 -#define TCD0_CCC_vect _VECTOR(81) /* Compare or Capture C Interrupt */ - -/* TCD2 interrupt vectors */ -#define TCD2_LCMPC_vect_num 81 -#define TCD2_LCMPC_vect _VECTOR(81) /* Low Byte Compare C Interrupt */ - -/* TCD0 interrupt vectors */ -#define TCD0_CCD_vect_num 82 -#define TCD0_CCD_vect _VECTOR(82) /* Compare or Capture D Interrupt */ - -/* TCD2 interrupt vectors */ -#define TCD2_LCMPD_vect_num 82 -#define TCD2_LCMPD_vect _VECTOR(82) /* Low Byte Compare D Interrupt */ - -/* SPID interrupt vectors */ -#define SPID_INT_vect_num 87 -#define SPID_INT_vect _VECTOR(87) /* SPI Interrupt */ - -/* USARTD0 interrupt vectors */ -#define USARTD0_RXC_vect_num 88 -#define USARTD0_RXC_vect _VECTOR(88) /* Reception Complete Interrupt */ -#define USARTD0_DRE_vect_num 89 -#define USARTD0_DRE_vect _VECTOR(89) /* Data Register Empty Interrupt */ -#define USARTD0_TXC_vect_num 90 -#define USARTD0_TXC_vect _VECTOR(90) /* Transmission Complete Interrupt */ - -/* PORTF interrupt vectors */ -#define PORTF_INT0_vect_num 104 -#define PORTF_INT0_vect _VECTOR(104) /* External Interrupt 0 */ -#define PORTF_INT1_vect_num 105 -#define PORTF_INT1_vect _VECTOR(105) /* External Interrupt 1 */ - -/* TCF0 interrupt vectors */ -#define TCF0_OVF_vect_num 108 -#define TCF0_OVF_vect _VECTOR(108) /* Overflow Interrupt */ - -/* TCF2 interrupt vectors */ -#define TCF2_LUNF_vect_num 108 -#define TCF2_LUNF_vect _VECTOR(108) /* Low Byte Underflow Interrupt */ - -/* TCF0 interrupt vectors */ -#define TCF0_ERR_vect_num 109 -#define TCF0_ERR_vect _VECTOR(109) /* Error Interrupt */ - -/* TCF2 interrupt vectors */ -#define TCF2_HUNF_vect_num 109 -#define TCF2_HUNF_vect _VECTOR(109) /* High Byte Underflow Interrupt */ - -/* TCF0 interrupt vectors */ -#define TCF0_CCA_vect_num 110 -#define TCF0_CCA_vect _VECTOR(110) /* Compare or Capture A Interrupt */ - -/* TCF2 interrupt vectors */ -#define TCF2_LCMPA_vect_num 110 -#define TCF2_LCMPA_vect _VECTOR(110) /* Low Byte Compare A Interrupt */ - -/* TCF0 interrupt vectors */ -#define TCF0_CCB_vect_num 111 -#define TCF0_CCB_vect _VECTOR(111) /* Compare or Capture B Interrupt */ - -/* TCF2 interrupt vectors */ -#define TCF2_LCMPB_vect_num 111 -#define TCF2_LCMPB_vect _VECTOR(111) /* Low Byte Compare B Interrupt */ - -/* TCF0 interrupt vectors */ -#define TCF0_CCC_vect_num 112 -#define TCF0_CCC_vect _VECTOR(112) /* Compare or Capture C Interrupt */ - -/* TCF2 interrupt vectors */ -#define TCF2_LCMPC_vect_num 112 -#define TCF2_LCMPC_vect _VECTOR(112) /* Low Byte Compare C Interrupt */ - -/* TCF0 interrupt vectors */ -#define TCF0_CCD_vect_num 113 -#define TCF0_CCD_vect _VECTOR(113) /* Compare or Capture D Interrupt */ - -/* TCF2 interrupt vectors */ -#define TCF2_LCMPD_vect_num 113 -#define TCF2_LCMPD_vect _VECTOR(113) /* Low Byte Compare D Interrupt */ - -/* USB interrupt vectors */ -#define USB_BUSEVENT_vect_num 125 -#define USB_BUSEVENT_vect _VECTOR(125) /* SOF, suspend, resume, reset bus event interrupts, crc, underflow, overflow and stall error interrupts */ -#define USB_TRNCOMPL_vect_num 126 -#define USB_TRNCOMPL_vect _VECTOR(126) /* Transaction complete interrupt */ - -#define _VECTOR_SIZE 4 /* Size of individual vector. */ -#define _VECTORS_SIZE (127 * _VECTOR_SIZE) - - -/* ========== Constants ========== */ - -#define PROGMEM_START (0x0000) -#define PROGMEM_SIZE (401408) -#define PROGMEM_END (PROGMEM_START + PROGMEM_SIZE - 1) - -#define APP_SECTION_START (0x0000) -#define APP_SECTION_SIZE (393216) -#define APP_SECTION_PAGE_SIZE (512) -#define APP_SECTION_END (APP_SECTION_START + APP_SECTION_SIZE - 1) - -#define APPTABLE_SECTION_START (0x5E000) -#define APPTABLE_SECTION_SIZE (8192) -#define APPTABLE_SECTION_PAGE_SIZE (512) -#define APPTABLE_SECTION_END (APPTABLE_SECTION_START + APPTABLE_SECTION_SIZE - 1) - -#define BOOT_SECTION_START (0x60000) -#define BOOT_SECTION_SIZE (8192) -#define BOOT_SECTION_PAGE_SIZE (512) -#define BOOT_SECTION_END (BOOT_SECTION_START + BOOT_SECTION_SIZE - 1) - -#define DATAMEM_START (0x0000) -#define DATAMEM_SIZE (40960) -#define DATAMEM_END (DATAMEM_START + DATAMEM_SIZE - 1) - -#define IO_START (0x0000) -#define IO_SIZE (4096) -#define IO_PAGE_SIZE (0) -#define IO_END (IO_START + IO_SIZE - 1) - -#define MAPPED_EEPROM_START (0x1000) -#define MAPPED_EEPROM_SIZE (4096) -#define MAPPED_EEPROM_PAGE_SIZE (0) -#define MAPPED_EEPROM_END (MAPPED_EEPROM_START + MAPPED_EEPROM_SIZE - 1) - -#define INTERNAL_SRAM_START (0x2000) -#define INTERNAL_SRAM_SIZE (32768) -#define INTERNAL_SRAM_PAGE_SIZE (0) -#define INTERNAL_SRAM_END (INTERNAL_SRAM_START + INTERNAL_SRAM_SIZE - 1) - -#define EEPROM_START (0x0000) -#define EEPROM_SIZE (4096) -#define EEPROM_PAGE_SIZE (32) -#define EEPROM_END (EEPROM_START + EEPROM_SIZE - 1) - -#define SIGNATURES_START (0x0000) -#define SIGNATURES_SIZE (3) -#define SIGNATURES_PAGE_SIZE (0) -#define SIGNATURES_END (SIGNATURES_START + SIGNATURES_SIZE - 1) - -#define FUSES_START (0x0000) -#define FUSES_SIZE (6) -#define FUSES_PAGE_SIZE (0) -#define FUSES_END (FUSES_START + FUSES_SIZE - 1) - -#define LOCKBITS_START (0x0000) -#define LOCKBITS_SIZE (1) -#define LOCKBITS_PAGE_SIZE (0) -#define LOCKBITS_END (LOCKBITS_START + LOCKBITS_SIZE - 1) - -#define USER_SIGNATURES_START (0x0000) -#define USER_SIGNATURES_SIZE (512) -#define USER_SIGNATURES_PAGE_SIZE (512) -#define USER_SIGNATURES_END (USER_SIGNATURES_START + USER_SIGNATURES_SIZE - 1) - -#define PROD_SIGNATURES_START (0x0000) -#define PROD_SIGNATURES_SIZE (64) -#define PROD_SIGNATURES_PAGE_SIZE (512) -#define PROD_SIGNATURES_END (PROD_SIGNATURES_START + PROD_SIGNATURES_SIZE - 1) - -#define FLASHSTART PROGMEM_START -#define FLASHEND PROGMEM_END -#define SPM_PAGESIZE 512 -#define RAMSTART INTERNAL_SRAM_START -#define RAMSIZE INTERNAL_SRAM_SIZE -#define RAMEND INTERNAL_SRAM_END -#define E2END EEPROM_END -#define E2PAGESIZE EEPROM_PAGE_SIZE - - -/* ========== Fuses ========== */ -#define FUSE_MEMORY_SIZE 6 - -/* Fuse Byte 0 Reserved */ - -/* Fuse Byte 1 */ -#define FUSE_WDP0 (unsigned char)~_BV(0) /* Watchdog Timeout Period Bit 0 */ -#define FUSE_WDP1 (unsigned char)~_BV(1) /* Watchdog Timeout Period Bit 1 */ -#define FUSE_WDP2 (unsigned char)~_BV(2) /* Watchdog Timeout Period Bit 2 */ -#define FUSE_WDP3 (unsigned char)~_BV(3) /* Watchdog Timeout Period Bit 3 */ -#define FUSE_WDWP0 (unsigned char)~_BV(4) /* Watchdog Window Timeout Period Bit 0 */ -#define FUSE_WDWP1 (unsigned char)~_BV(5) /* Watchdog Window Timeout Period Bit 1 */ -#define FUSE_WDWP2 (unsigned char)~_BV(6) /* Watchdog Window Timeout Period Bit 2 */ -#define FUSE_WDWP3 (unsigned char)~_BV(7) /* Watchdog Window Timeout Period Bit 3 */ -#define FUSE1_DEFAULT (0xFF) - -/* Fuse Byte 2 */ -#define FUSE_BODPD0 (unsigned char)~_BV(0) /* BOD Operation in Power-Down Mode Bit 0 */ -#define FUSE_BODPD1 (unsigned char)~_BV(1) /* BOD Operation in Power-Down Mode Bit 1 */ -#define FUSE_TOSCSEL (unsigned char)~_BV(5) /* Timer Oscillator pin location */ -#define FUSE_BOOTRST (unsigned char)~_BV(6) /* Boot Loader Section Reset Vector */ -#define FUSE2_DEFAULT (0xFF) - -/* Fuse Byte 3 Reserved */ - -/* Fuse Byte 4 */ -#define FUSE_WDLOCK (unsigned char)~_BV(1) /* Watchdog Timer Lock */ -#define FUSE_SUT0 (unsigned char)~_BV(2) /* Start-up Time Bit 0 */ -#define FUSE_SUT1 (unsigned char)~_BV(3) /* Start-up Time Bit 1 */ -#define FUSE_RSTDISBL (unsigned char)~_BV(4) /* External Reset Disable */ -#define FUSE4_DEFAULT (0xFF) - -/* Fuse Byte 5 */ -#define FUSE_BODLVL0 (unsigned char)~_BV(0) /* Brownout Detection Voltage Level Bit 0 */ -#define FUSE_BODLVL1 (unsigned char)~_BV(1) /* Brownout Detection Voltage Level Bit 1 */ -#define FUSE_BODLVL2 (unsigned char)~_BV(2) /* Brownout Detection Voltage Level Bit 2 */ -#define FUSE_EESAVE (unsigned char)~_BV(3) /* Preserve EEPROM Through Chip Erase */ -#define FUSE_BODACT0 (unsigned char)~_BV(4) /* BOD Operation in Active Mode Bit 0 */ -#define FUSE_BODACT1 (unsigned char)~_BV(5) /* BOD Operation in Active Mode Bit 1 */ -#define FUSE5_DEFAULT (0xFF) - -/* ========== Lock Bits ========== */ -#define __LOCK_BITS_EXIST -#define __BOOT_LOCK_APPLICATION_TABLE_BITS_EXIST -#define __BOOT_LOCK_APPLICATION_BITS_EXIST -#define __BOOT_LOCK_BOOT_BITS_EXIST - -/* ========== Signature ========== */ -#define SIGNATURE_0 0x1E -#define SIGNATURE_1 0x98 -#define SIGNATURE_2 0x45 - -/* ========== Power Reduction Condition Definitions ========== */ - -/* PR.PRGEN */ -#define __AVR_HAVE_PRGEN (PR_USB_bm|PR_AES_bm|PR_EBI_bm|PR_RTC_bm|PR_EVSYS_bm|PR_DMA_bm) -#define __AVR_HAVE_PRGEN_USB -#define __AVR_HAVE_PRGEN_AES -#define __AVR_HAVE_PRGEN_EBI -#define __AVR_HAVE_PRGEN_RTC -#define __AVR_HAVE_PRGEN_EVSYS -#define __AVR_HAVE_PRGEN_DMA - -/* PR.PRPA */ -#define __AVR_HAVE_PRPA (PR_DAC_bm|PR_ADC_bm|PR_AC_bm) -#define __AVR_HAVE_PRPA_DAC -#define __AVR_HAVE_PRPA_ADC -#define __AVR_HAVE_PRPA_AC - -/* PR.PRPB */ -#define __AVR_HAVE_PRPB (PR_DAC_bm|PR_ADC_bm|PR_AC_bm) -#define __AVR_HAVE_PRPB_DAC -#define __AVR_HAVE_PRPB_ADC -#define __AVR_HAVE_PRPB_AC - -/* PR.PRPC */ -#define __AVR_HAVE_PRPC (PR_TWI_bm|PR_USART1_bm|PR_USART0_bm|PR_SPI_bm|PR_HIRES_bm|PR_TC1_bm|PR_TC0_bm) -#define __AVR_HAVE_PRPC_TWI -#define __AVR_HAVE_PRPC_USART1 -#define __AVR_HAVE_PRPC_USART0 -#define __AVR_HAVE_PRPC_SPI -#define __AVR_HAVE_PRPC_HIRES -#define __AVR_HAVE_PRPC_TC1 -#define __AVR_HAVE_PRPC_TC0 - -/* PR.PRPD */ -#define __AVR_HAVE_PRPD (PR_TWI_bm|PR_USART1_bm|PR_USART0_bm|PR_SPI_bm|PR_HIRES_bm|PR_TC1_bm|PR_TC0_bm) -#define __AVR_HAVE_PRPD_TWI -#define __AVR_HAVE_PRPD_USART1 -#define __AVR_HAVE_PRPD_USART0 -#define __AVR_HAVE_PRPD_SPI -#define __AVR_HAVE_PRPD_HIRES -#define __AVR_HAVE_PRPD_TC1 -#define __AVR_HAVE_PRPD_TC0 - -/* PR.PRPE */ -#define __AVR_HAVE_PRPE (PR_TWI_bm|PR_USART1_bm|PR_USART0_bm|PR_SPI_bm|PR_HIRES_bm|PR_TC1_bm|PR_TC0_bm) -#define __AVR_HAVE_PRPE_TWI -#define __AVR_HAVE_PRPE_USART1 -#define __AVR_HAVE_PRPE_USART0 -#define __AVR_HAVE_PRPE_SPI -#define __AVR_HAVE_PRPE_HIRES -#define __AVR_HAVE_PRPE_TC1 -#define __AVR_HAVE_PRPE_TC0 - -/* PR.PRPF */ -#define __AVR_HAVE_PRPF (PR_TWI_bm|PR_USART1_bm|PR_USART0_bm|PR_SPI_bm|PR_HIRES_bm|PR_TC1_bm|PR_TC0_bm) -#define __AVR_HAVE_PRPF_TWI -#define __AVR_HAVE_PRPF_USART1 -#define __AVR_HAVE_PRPF_USART0 -#define __AVR_HAVE_PRPF_SPI -#define __AVR_HAVE_PRPF_HIRES -#define __AVR_HAVE_PRPF_TC1 -#define __AVR_HAVE_PRPF_TC0 - - -#endif /* #ifdef _AVR_ATXMEGA384C3_H_INCLUDED */ - diff --git a/arduino/hardware/tools/avr/avr/include/avr/iox384d3.h b/arduino/hardware/tools/avr/avr/include/avr/iox384d3.h deleted file mode 100644 index 042e1f5..0000000 --- a/arduino/hardware/tools/avr/avr/include/avr/iox384d3.h +++ /dev/null @@ -1,5833 +0,0 @@ -/***************************************************************************** - * - * Copyright (C) 2015 Atmel Corporation - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * - * * Neither the name of the copyright holders nor the names of - * contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - ****************************************************************************/ - - -#ifndef _AVR_IO_H_ -# error "Include instead of this file." -#endif - -#ifndef _AVR_IOXXX_H_ -# define _AVR_IOXXX_H_ "iox384d3.h" -#else -# error "Attempt to include more than one file." -#endif - -#ifndef _AVR_ATXMEGA384D3_H_INCLUDED -#define _AVR_ATXMEGA384D3_H_INCLUDED - -/* Ungrouped common registers */ -#define GPIOR0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ -#define GPIOR1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ -#define GPIOR2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ -#define GPIOR3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ - -/* Deprecated */ -#define GPIO0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ -#define GPIO1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ -#define GPIO2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ -#define GPIO3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ - -#define CCP _SFR_MEM8(0x0034) /* Configuration Change Protection */ -#define RAMPD _SFR_MEM8(0x0038) /* Ramp D */ -#define RAMPX _SFR_MEM8(0x0039) /* Ramp X */ -#define RAMPY _SFR_MEM8(0x003A) /* Ramp Y */ -#define RAMPZ _SFR_MEM8(0x003B) /* Ramp Z */ -#define EIND _SFR_MEM8(0x003C) /* Extended Indirect Jump */ -#define SPL _SFR_MEM8(0x003D) /* Stack Pointer Low */ -#define SPH _SFR_MEM8(0x003E) /* Stack Pointer High */ -#define SREG _SFR_MEM8(0x003F) /* Status Register */ - -/* C Language Only */ -#if !defined (__ASSEMBLER__) - -#include - -typedef volatile uint8_t register8_t; -typedef volatile uint16_t register16_t; -typedef volatile uint32_t register32_t; - - -#ifdef _WORDREGISTER -#undef _WORDREGISTER -#endif -#define _WORDREGISTER(regname) \ - __extension__ union \ - { \ - register16_t regname; \ - struct \ - { \ - register8_t regname ## L; \ - register8_t regname ## H; \ - }; \ - } - -#ifdef _DWORDREGISTER -#undef _DWORDREGISTER -#endif -#define _DWORDREGISTER(regname) \ - __extension__ union \ - { \ - register32_t regname; \ - struct \ - { \ - register8_t regname ## 0; \ - register8_t regname ## 1; \ - register8_t regname ## 2; \ - register8_t regname ## 3; \ - }; \ - } - - -/* -========================================================================== -IO Module Structures -========================================================================== -*/ - - -/* --------------------------------------------------------------------------- -VPORT - Virtual Ports --------------------------------------------------------------------------- -*/ - -/* Virtual Port */ -typedef struct VPORT_struct -{ - register8_t DIR; /* I/O Port Data Direction */ - register8_t OUT; /* I/O Port Output */ - register8_t IN; /* I/O Port Input */ - register8_t INTFLAGS; /* Interrupt Flag Register */ -} VPORT_t; - - -/* --------------------------------------------------------------------------- -XOCD - On-Chip Debug System --------------------------------------------------------------------------- -*/ - -/* On-Chip Debug System */ -typedef struct OCD_struct -{ - register8_t OCDR0; /* OCD Register 0 */ - register8_t OCDR1; /* OCD Register 1 */ -} OCD_t; - - -/* --------------------------------------------------------------------------- -CPU - CPU --------------------------------------------------------------------------- -*/ - -/* CCP signatures */ -typedef enum CCP_enum -{ - CCP_SPM_gc = (0x9D<<0), /* SPM Instruction Protection */ - CCP_IOREG_gc = (0xD8<<0), /* IO Register Protection */ -} CCP_t; - - -/* --------------------------------------------------------------------------- -CLK - Clock System --------------------------------------------------------------------------- -*/ - -/* Clock System */ -typedef struct CLK_struct -{ - register8_t CTRL; /* Control Register */ - register8_t PSCTRL; /* Prescaler Control Register */ - register8_t LOCK; /* Lock register */ - register8_t RTCCTRL; /* RTC Control Register */ - register8_t reserved_0x04; -} CLK_t; - - -/* Power Reduction */ -typedef struct PR_struct -{ - register8_t PRGEN; /* General Power Reduction */ - register8_t PRPA; /* Power Reduction Port A */ - register8_t reserved_0x02; - register8_t PRPC; /* Power Reduction Port C */ - register8_t PRPD; /* Power Reduction Port D */ - register8_t PRPE; /* Power Reduction Port E */ - register8_t PRPF; /* Power Reduction Port F */ -} PR_t; - -/* System Clock Selection */ -typedef enum CLK_SCLKSEL_enum -{ - CLK_SCLKSEL_RC2M_gc = (0x00<<0), /* Internal 2 MHz RC Oscillator */ - CLK_SCLKSEL_RC32M_gc = (0x01<<0), /* Internal 32 MHz RC Oscillator */ - CLK_SCLKSEL_RC32K_gc = (0x02<<0), /* Internal 32.768 kHz RC Oscillator */ - CLK_SCLKSEL_XOSC_gc = (0x03<<0), /* External Crystal Oscillator or Clock */ - CLK_SCLKSEL_PLL_gc = (0x04<<0), /* Phase Locked Loop */ -} CLK_SCLKSEL_t; - -/* Prescaler A Division Factor */ -typedef enum CLK_PSADIV_enum -{ - CLK_PSADIV_1_gc = (0x00<<2), /* Divide by 1 */ - CLK_PSADIV_2_gc = (0x01<<2), /* Divide by 2 */ - CLK_PSADIV_4_gc = (0x03<<2), /* Divide by 4 */ - CLK_PSADIV_8_gc = (0x05<<2), /* Divide by 8 */ - CLK_PSADIV_16_gc = (0x07<<2), /* Divide by 16 */ - CLK_PSADIV_32_gc = (0x09<<2), /* Divide by 32 */ - CLK_PSADIV_64_gc = (0x0B<<2), /* Divide by 64 */ - CLK_PSADIV_128_gc = (0x0D<<2), /* Divide by 128 */ - CLK_PSADIV_256_gc = (0x0F<<2), /* Divide by 256 */ - CLK_PSADIV_512_gc = (0x11<<2), /* Divide by 512 */ -} CLK_PSADIV_t; - -/* Prescaler B and C Division Factor */ -typedef enum CLK_PSBCDIV_enum -{ - CLK_PSBCDIV_1_1_gc = (0x00<<0), /* Divide B by 1 and C by 1 */ - CLK_PSBCDIV_1_2_gc = (0x01<<0), /* Divide B by 1 and C by 2 */ - CLK_PSBCDIV_4_1_gc = (0x02<<0), /* Divide B by 4 and C by 1 */ - CLK_PSBCDIV_2_2_gc = (0x03<<0), /* Divide B by 2 and C by 2 */ -} CLK_PSBCDIV_t; - -/* RTC Clock Source */ -typedef enum CLK_RTCSRC_enum -{ - CLK_RTCSRC_ULP_gc = (0x00<<1), /* 1 kHz from internal 32kHz ULP */ - CLK_RTCSRC_TOSC_gc = (0x01<<1), /* 1.024 kHz from 32.768 kHz crystal oscillator on TOSC */ - CLK_RTCSRC_RCOSC_gc = (0x02<<1), /* 1.024 kHz from 32.768 kHz internal oscillator */ - CLK_RTCSRC_TOSC32_gc = (0x05<<1), /* 32.768 kHz from 32.768 kHz crystal oscillator on TOSC */ - CLK_RTCSRC_RCOSC32_gc = (0x06<<1), /* 32.768 kHz from 32.768 kHz internal oscillator */ - CLK_RTCSRC_EXTCLK_gc = (0x07<<1), /* External Clock from TOSC1 */ -} CLK_RTCSRC_t; - - -/* --------------------------------------------------------------------------- -SLEEP - Sleep Controller --------------------------------------------------------------------------- -*/ - -/* Sleep Controller */ -typedef struct SLEEP_struct -{ - register8_t CTRL; /* Control Register */ -} SLEEP_t; - -/* Sleep Mode */ -typedef enum SLEEP_SMODE_enum -{ - SLEEP_SMODE_IDLE_gc = (0x00<<1), /* Idle mode */ - SLEEP_SMODE_PDOWN_gc = (0x02<<1), /* Power-down Mode */ - SLEEP_SMODE_PSAVE_gc = (0x03<<1), /* Power-save Mode */ - SLEEP_SMODE_STDBY_gc = (0x06<<1), /* Standby Mode */ - SLEEP_SMODE_ESTDBY_gc = (0x07<<1), /* Extended Standby Mode */ -} SLEEP_SMODE_t; - - - -#define SLEEP_MODE_IDLE (0x00<<1) -#define SLEEP_MODE_PWR_DOWN (0x02<<1) -#define SLEEP_MODE_PWR_SAVE (0x03<<1) -#define SLEEP_MODE_STANDBY (0x06<<1) -#define SLEEP_MODE_EXT_STANDBY (0x07<<1) -/* --------------------------------------------------------------------------- -OSC - Oscillator --------------------------------------------------------------------------- -*/ - -/* Oscillator */ -typedef struct OSC_struct -{ - register8_t CTRL; /* Control Register */ - register8_t STATUS; /* Status Register */ - register8_t XOSCCTRL; /* External Oscillator Control Register */ - register8_t XOSCFAIL; /* Oscillator Failure Detection Register */ - register8_t RC32KCAL; /* 32.768 kHz Internal Oscillator Calibration Register */ - register8_t PLLCTRL; /* PLL Control Register */ - register8_t DFLLCTRL; /* DFLL Control Register */ -} OSC_t; - -/* Oscillator Frequency Range */ -typedef enum OSC_FRQRANGE_enum -{ - OSC_FRQRANGE_04TO2_gc = (0x00<<6), /* 0.4 - 2 MHz */ - OSC_FRQRANGE_2TO9_gc = (0x01<<6), /* 2 - 9 MHz */ - OSC_FRQRANGE_9TO12_gc = (0x02<<6), /* 9 - 12 MHz */ - OSC_FRQRANGE_12TO16_gc = (0x03<<6), /* 12 - 16 MHz */ -} OSC_FRQRANGE_t; - -/* External Oscillator Selection and Startup Time */ -typedef enum OSC_XOSCSEL_enum -{ - OSC_XOSCSEL_EXTCLK_gc = (0x00<<0), /* External Clock - 6 CLK */ - OSC_XOSCSEL_32KHz_gc = (0x02<<0), /* 32.768 kHz TOSC - 32K CLK */ - OSC_XOSCSEL_XTAL_256CLK_gc = (0x03<<0), /* 0.4-16 MHz XTAL - 256 CLK */ - OSC_XOSCSEL_XTAL_1KCLK_gc = (0x07<<0), /* 0.4-16 MHz XTAL - 1K CLK */ - OSC_XOSCSEL_XTAL_16KCLK_gc = (0x0B<<0), /* 0.4-16 MHz XTAL - 16K CLK */ -} OSC_XOSCSEL_t; - -/* PLL Clock Source */ -typedef enum OSC_PLLSRC_enum -{ - OSC_PLLSRC_RC2M_gc = (0x00<<6), /* Internal 2 MHz RC Oscillator */ - OSC_PLLSRC_RC32M_gc = (0x02<<6), /* Internal 32 MHz RC Oscillator */ - OSC_PLLSRC_XOSC_gc = (0x03<<6), /* External Oscillator */ -} OSC_PLLSRC_t; - -/* 2 MHz DFLL Calibration Reference */ -typedef enum OSC_RC2MCREF_enum -{ - OSC_RC2MCREF_RC32K_gc = (0x00<<0), /* Internal 32.768 kHz RC Oscillator */ - OSC_RC2MCREF_XOSC32K_gc = (0x01<<0), /* External 32.768 kHz Crystal Oscillator */ -} OSC_RC2MCREF_t; - -/* 32 MHz DFLL Calibration Reference */ -typedef enum OSC_RC32MCREF_enum -{ - OSC_RC32MCREF_RC32K_gc = (0x00<<1), /* Internal 32.768 kHz RC Oscillator */ - OSC_RC32MCREF_XOSC32K_gc = (0x01<<1), /* External 32.768 kHz Crystal Oscillator */ - OSC_RC32MCREF_USBSOF_gc = (0x02<<1), /* USB Start of Frame */ -} OSC_RC32MCREF_t; - - -/* --------------------------------------------------------------------------- -DFLL - DFLL --------------------------------------------------------------------------- -*/ - -/* DFLL */ -typedef struct DFLL_struct -{ - register8_t CTRL; /* Control Register */ - register8_t reserved_0x01; - register8_t CALA; /* Calibration Register A */ - register8_t CALB; /* Calibration Register B */ - register8_t COMP0; /* Oscillator Compare Register 0 */ - register8_t COMP1; /* Oscillator Compare Register 1 */ - register8_t COMP2; /* Oscillator Compare Register 2 */ - register8_t reserved_0x07; -} DFLL_t; - - -/* --------------------------------------------------------------------------- -RST - Reset --------------------------------------------------------------------------- -*/ - -/* Reset */ -typedef struct RST_struct -{ - register8_t STATUS; /* Status Register */ - register8_t CTRL; /* Control Register */ -} RST_t; - - -/* --------------------------------------------------------------------------- -WDT - Watch-Dog Timer --------------------------------------------------------------------------- -*/ - -/* Watch-Dog Timer */ -typedef struct WDT_struct -{ - register8_t CTRL; /* Control */ - register8_t WINCTRL; /* Windowed Mode Control */ - register8_t STATUS; /* Status */ -} WDT_t; - -/* Period setting */ -typedef enum WDT_PER_enum -{ - WDT_PER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ - WDT_PER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ - WDT_PER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ - WDT_PER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ - WDT_PER_128CLK_gc = (0x04<<2), /* 128 cycles (0.128s @ 3.3V) */ - WDT_PER_256CLK_gc = (0x05<<2), /* 256 cycles (0.256s @ 3.3V) */ - WDT_PER_512CLK_gc = (0x06<<2), /* 512 cycles (0.512s @ 3.3V) */ - WDT_PER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ - WDT_PER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ - WDT_PER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ - WDT_PER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ -} WDT_PER_t; - -/* Closed window period */ -typedef enum WDT_WPER_enum -{ - WDT_WPER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ - WDT_WPER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ - WDT_WPER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ - WDT_WPER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ - WDT_WPER_128CLK_gc = (0x04<<2), /* 128 cycles (0.128s @ 3.3V) */ - WDT_WPER_256CLK_gc = (0x05<<2), /* 256 cycles (0.256s @ 3.3V) */ - WDT_WPER_512CLK_gc = (0x06<<2), /* 512 cycles (0.512s @ 3.3V) */ - WDT_WPER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ - WDT_WPER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ - WDT_WPER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ - WDT_WPER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ -} WDT_WPER_t; - - -/* --------------------------------------------------------------------------- -MCU - MCU Control --------------------------------------------------------------------------- -*/ - -/* MCU Control */ -typedef struct MCU_struct -{ - register8_t DEVID0; /* Device ID byte 0 */ - register8_t DEVID1; /* Device ID byte 1 */ - register8_t DEVID2; /* Device ID byte 2 */ - register8_t REVID; /* Revision ID */ - register8_t reserved_0x04; - register8_t reserved_0x05; - register8_t reserved_0x06; - register8_t ANAINIT; /* Analog Startup Delay */ - register8_t EVSYSLOCK; /* Event System Lock */ - register8_t AWEXLOCK; /* AWEX Lock */ - register8_t reserved_0x0A; - register8_t reserved_0x0B; -} MCU_t; - - -/* --------------------------------------------------------------------------- -PMIC - Programmable Multi-level Interrupt Controller --------------------------------------------------------------------------- -*/ - -/* Programmable Multi-level Interrupt Controller */ -typedef struct PMIC_struct -{ - register8_t STATUS; /* Status Register */ - register8_t INTPRI; /* Interrupt Priority */ - register8_t CTRL; /* Control Register */ - register8_t reserved_0x03; - register8_t reserved_0x04; - register8_t reserved_0x05; - register8_t reserved_0x06; - register8_t reserved_0x07; - register8_t reserved_0x08; - register8_t reserved_0x09; - register8_t reserved_0x0A; - register8_t reserved_0x0B; - register8_t reserved_0x0C; - register8_t reserved_0x0D; - register8_t reserved_0x0E; - register8_t reserved_0x0F; -} PMIC_t; - - -/* --------------------------------------------------------------------------- -PORTCFG - Port Configuration --------------------------------------------------------------------------- -*/ - -/* I/O port Configuration */ -typedef struct PORTCFG_struct -{ - register8_t MPCMASK; /* Multi-pin Configuration Mask */ - register8_t reserved_0x01; - register8_t VPCTRLA; /* Virtual Port Control Register A */ - register8_t VPCTRLB; /* Virtual Port Control Register B */ - register8_t CLKEVOUT; /* Clock and Event Out Register */ - register8_t EBIOUT; /* EBI Output register */ - register8_t EVOUTSEL; /* Event Output Select */ -} PORTCFG_t; - -/* Virtual Port Mapping */ -typedef enum PORTCFG_VP02MAP_enum -{ - PORTCFG_VP02MAP_PORTA_gc = (0x00<<0), /* Mapped To PORTA */ - PORTCFG_VP02MAP_PORTB_gc = (0x01<<0), /* Mapped To PORTB */ - PORTCFG_VP02MAP_PORTC_gc = (0x02<<0), /* Mapped To PORTC */ - PORTCFG_VP02MAP_PORTD_gc = (0x03<<0), /* Mapped To PORTD */ - PORTCFG_VP02MAP_PORTE_gc = (0x04<<0), /* Mapped To PORTE */ - PORTCFG_VP02MAP_PORTF_gc = (0x05<<0), /* Mapped To PORTF */ - PORTCFG_VP02MAP_PORTG_gc = (0x06<<0), /* Mapped To PORTG */ - PORTCFG_VP02MAP_PORTH_gc = (0x07<<0), /* Mapped To PORTH */ - PORTCFG_VP02MAP_PORTJ_gc = (0x08<<0), /* Mapped To PORTJ */ - PORTCFG_VP02MAP_PORTK_gc = (0x09<<0), /* Mapped To PORTK */ - PORTCFG_VP02MAP_PORTL_gc = (0x0A<<0), /* Mapped To PORTL */ - PORTCFG_VP02MAP_PORTM_gc = (0x0B<<0), /* Mapped To PORTM */ - PORTCFG_VP02MAP_PORTN_gc = (0x0C<<0), /* Mapped To PORTN */ - PORTCFG_VP02MAP_PORTP_gc = (0x0D<<0), /* Mapped To PORTP */ - PORTCFG_VP02MAP_PORTQ_gc = (0x0E<<0), /* Mapped To PORTQ */ - PORTCFG_VP02MAP_PORTR_gc = (0x0F<<0), /* Mapped To PORTR */ -} PORTCFG_VP02MAP_t; - -/* Virtual Port Mapping */ -typedef enum PORTCFG_VP13MAP_enum -{ - PORTCFG_VP13MAP_PORTA_gc = (0x00<<4), /* Mapped To PORTA */ - PORTCFG_VP13MAP_PORTB_gc = (0x01<<4), /* Mapped To PORTB */ - PORTCFG_VP13MAP_PORTC_gc = (0x02<<4), /* Mapped To PORTC */ - PORTCFG_VP13MAP_PORTD_gc = (0x03<<4), /* Mapped To PORTD */ - PORTCFG_VP13MAP_PORTE_gc = (0x04<<4), /* Mapped To PORTE */ - PORTCFG_VP13MAP_PORTF_gc = (0x05<<4), /* Mapped To PORTF */ - PORTCFG_VP13MAP_PORTG_gc = (0x06<<4), /* Mapped To PORTG */ - PORTCFG_VP13MAP_PORTH_gc = (0x07<<4), /* Mapped To PORTH */ - PORTCFG_VP13MAP_PORTJ_gc = (0x08<<4), /* Mapped To PORTJ */ - PORTCFG_VP13MAP_PORTK_gc = (0x09<<4), /* Mapped To PORTK */ - PORTCFG_VP13MAP_PORTL_gc = (0x0A<<4), /* Mapped To PORTL */ - PORTCFG_VP13MAP_PORTM_gc = (0x0B<<4), /* Mapped To PORTM */ - PORTCFG_VP13MAP_PORTN_gc = (0x0C<<4), /* Mapped To PORTN */ - PORTCFG_VP13MAP_PORTP_gc = (0x0D<<4), /* Mapped To PORTP */ - PORTCFG_VP13MAP_PORTQ_gc = (0x0E<<4), /* Mapped To PORTQ */ - PORTCFG_VP13MAP_PORTR_gc = (0x0F<<4), /* Mapped To PORTR */ -} PORTCFG_VP13MAP_t; - -/* System Clock Output Port */ -typedef enum PORTCFG_CLKOUT_enum -{ - PORTCFG_CLKOUT_OFF_gc = (0x00<<0), /* System Clock Output Disabled */ - PORTCFG_CLKOUT_PC7_gc = (0x01<<0), /* System Clock Output on Port C pin 7 */ - PORTCFG_CLKOUT_PD7_gc = (0x02<<0), /* System Clock Output on Port D pin 7 */ - PORTCFG_CLKOUT_PE7_gc = (0x03<<0), /* System Clock Output on Port E pin 7 */ -} PORTCFG_CLKOUT_t; - -/* Peripheral Clock Output Select */ -typedef enum PORTCFG_CLKOUTSEL_enum -{ - PORTCFG_CLKOUTSEL_CLK1X_gc = (0x00<<2), /* 1x Peripheral Clock Output to pin */ - PORTCFG_CLKOUTSEL_CLK2X_gc = (0x01<<2), /* 2x Peripheral Clock Output to pin */ - PORTCFG_CLKOUTSEL_CLK4X_gc = (0x02<<2), /* 4x Peripheral Clock Output to pin */ -} PORTCFG_CLKOUTSEL_t; - -/* Event Output Port */ -typedef enum PORTCFG_EVOUT_enum -{ - PORTCFG_EVOUT_OFF_gc = (0x00<<4), /* Event Output Disabled */ - PORTCFG_EVOUT_PC7_gc = (0x01<<4), /* Event Channel 7 Output on Port C pin 7 */ - PORTCFG_EVOUT_PD7_gc = (0x02<<4), /* Event Channel 7 Output on Port D pin 7 */ - PORTCFG_EVOUT_PE7_gc = (0x03<<4), /* Event Channel 7 Output on Port E pin 7 */ -} PORTCFG_EVOUT_t; - -/* Clock and Event Output Port */ -typedef enum PORTCFG_CLKEVPIN_enum -{ - PORTCFG_CLKEVPIN_PIN7_gc = (0x00<<7), /* Clock and Event Ouput on PIN 7 */ - PORTCFG_CLKEVPIN_PIN4_gc = (0x01<<7), /* Clock and Event Ouput on PIN 4 */ -} PORTCFG_CLKEVPIN_t; - -/* EBI Address Output Port */ -typedef enum PORTCFG_EBIADROUT_enum -{ - PORTCFG_EBIADROUT_PF_gc = (0x00<<2), /* EBI port 3 address output on PORTF pins 0 to 7 */ - PORTCFG_EBIADROUT_PE_gc = (0x01<<2), /* EBI port 3 address output on PORTE pins 0 to 7 */ - PORTCFG_EBIADROUT_PFH_gc = (0x02<<2), /* EBI port 3 address output on PORTF pins 4 to 7 */ - PORTCFG_EBIADROUT_PEH_gc = (0x03<<2), /* EBI port 3 address output on PORTE pins 4 to 7 */ -} PORTCFG_EBIADROUT_t; - -/* EBI Chip Select Output Port */ -typedef enum PORTCFG_EBICSOUT_enum -{ - PORTCFG_EBICSOUT_PH_gc = (0x00<<0), /* EBI chip select output to PORTH pin 4 to 7 */ - PORTCFG_EBICSOUT_PL_gc = (0x01<<0), /* EBI chip select output to PORTL pin 4 to 7 */ - PORTCFG_EBICSOUT_PF_gc = (0x02<<0), /* EBI chip select output to PORTF pin 4 to 7 */ - PORTCFG_EBICSOUT_PE_gc = (0x03<<0), /* EBI chip select output to PORTE pin 4 to 7 */ -} PORTCFG_EBICSOUT_t; - -/* Event Output Select */ -typedef enum PORTCFG_EVOUTSEL_enum -{ - PORTCFG_EVOUTSEL_0_gc = (0x00<<0), /* Event Channel 0 output to pin */ - PORTCFG_EVOUTSEL_1_gc = (0x01<<0), /* Event Channel 1 output to pin */ - PORTCFG_EVOUTSEL_2_gc = (0x02<<0), /* Event Channel 2 output to pin */ - PORTCFG_EVOUTSEL_3_gc = (0x03<<0), /* Event Channel 3 output to pin */ - PORTCFG_EVOUTSEL_4_gc = (0x04<<0), /* Event Channel 4 output to pin */ - PORTCFG_EVOUTSEL_5_gc = (0x05<<0), /* Event Channel 5 output to pin */ - PORTCFG_EVOUTSEL_6_gc = (0x06<<0), /* Event Channel 6 output to pin */ - PORTCFG_EVOUTSEL_7_gc = (0x07<<0), /* Event Channel 7 output to pin */ -} PORTCFG_EVOUTSEL_t; - - -/* --------------------------------------------------------------------------- -CRC - Cyclic Redundancy Checker --------------------------------------------------------------------------- -*/ - -/* Cyclic Redundancy Checker */ -typedef struct CRC_struct -{ - register8_t CTRL; /* Control Register */ - register8_t STATUS; /* Status Register */ - register8_t reserved_0x02; - register8_t DATAIN; /* Data Input */ - register8_t CHECKSUM0; /* Checksum byte 0 */ - register8_t CHECKSUM1; /* Checksum byte 1 */ - register8_t CHECKSUM2; /* Checksum byte 2 */ - register8_t CHECKSUM3; /* Checksum byte 3 */ -} CRC_t; - -/* Reset */ -typedef enum CRC_RESET_enum -{ - CRC_RESET_NO_gc = (0x00<<6), /* No Reset */ - CRC_RESET_RESET0_gc = (0x02<<6), /* Reset CRC with CHECKSUM to all zeros */ - CRC_RESET_RESET1_gc = (0x03<<6), /* Reset CRC with CHECKSUM to all ones */ -} CRC_RESET_t; - -/* Input Source */ -typedef enum CRC_SOURCE_enum -{ - CRC_SOURCE_DISABLE_gc = (0x00<<0), /* Disabled */ - CRC_SOURCE_IO_gc = (0x01<<0), /* I/O Interface */ - CRC_SOURCE_FLASH_gc = (0x02<<0), /* Flash */ -} CRC_SOURCE_t; - - -/* --------------------------------------------------------------------------- -EVSYS - Event System --------------------------------------------------------------------------- -*/ - -/* Event System */ -typedef struct EVSYS_struct -{ - register8_t CH0MUX; /* Event Channel 0 Multiplexer */ - register8_t CH1MUX; /* Event Channel 1 Multiplexer */ - register8_t CH2MUX; /* Event Channel 2 Multiplexer */ - register8_t CH3MUX; /* Event Channel 3 Multiplexer */ - register8_t reserved_0x04; - register8_t reserved_0x05; - register8_t reserved_0x06; - register8_t reserved_0x07; - register8_t CH0CTRL; /* Channel 0 Control Register */ - register8_t CH1CTRL; /* Channel 1 Control Register */ - register8_t CH2CTRL; /* Channel 2 Control Register */ - register8_t CH3CTRL; /* Channel 3 Control Register */ - register8_t reserved_0x0C; - register8_t reserved_0x0D; - register8_t reserved_0x0E; - register8_t reserved_0x0F; - register8_t STROBE; /* Event Strobe */ - register8_t DATA; /* Event Data */ -} EVSYS_t; - -/* Quadrature Decoder Index Recognition Mode */ -typedef enum EVSYS_QDIRM_enum -{ - EVSYS_QDIRM_00_gc = (0x00<<5), /* QDPH0 = 0, QDPH90 = 0 */ - EVSYS_QDIRM_01_gc = (0x01<<5), /* QDPH0 = 0, QDPH90 = 1 */ - EVSYS_QDIRM_10_gc = (0x02<<5), /* QDPH0 = 1, QDPH90 = 0 */ - EVSYS_QDIRM_11_gc = (0x03<<5), /* QDPH0 = 1, QDPH90 = 1 */ -} EVSYS_QDIRM_t; - -/* Digital filter coefficient */ -typedef enum EVSYS_DIGFILT_enum -{ - EVSYS_DIGFILT_1SAMPLE_gc = (0x00<<0), /* 1 SAMPLE */ - EVSYS_DIGFILT_2SAMPLES_gc = (0x01<<0), /* 2 SAMPLES */ - EVSYS_DIGFILT_3SAMPLES_gc = (0x02<<0), /* 3 SAMPLES */ - EVSYS_DIGFILT_4SAMPLES_gc = (0x03<<0), /* 4 SAMPLES */ - EVSYS_DIGFILT_5SAMPLES_gc = (0x04<<0), /* 5 SAMPLES */ - EVSYS_DIGFILT_6SAMPLES_gc = (0x05<<0), /* 6 SAMPLES */ - EVSYS_DIGFILT_7SAMPLES_gc = (0x06<<0), /* 7 SAMPLES */ - EVSYS_DIGFILT_8SAMPLES_gc = (0x07<<0), /* 8 SAMPLES */ -} EVSYS_DIGFILT_t; - -/* Event Channel multiplexer input selection */ -typedef enum EVSYS_CHMUX_enum -{ - EVSYS_CHMUX_OFF_gc = (0x00<<0), /* Off */ - EVSYS_CHMUX_RTC_OVF_gc = (0x08<<0), /* RTC Overflow */ - EVSYS_CHMUX_RTC_CMP_gc = (0x09<<0), /* RTC Compare Match */ - EVSYS_CHMUX_USB_gc = (0x0A<<0), /* USB Setup, SOF, CRC error and UNF/OVF */ - EVSYS_CHMUX_ACA_CH0_gc = (0x10<<0), /* Analog Comparator A Channel 0 */ - EVSYS_CHMUX_ACA_CH1_gc = (0x11<<0), /* Analog Comparator A Channel 1 */ - EVSYS_CHMUX_ACA_WIN_gc = (0x12<<0), /* Analog Comparator A Window */ - EVSYS_CHMUX_ADCA_CH0_gc = (0x20<<0), /* ADC A Channel */ - EVSYS_CHMUX_PORTA_PIN0_gc = (0x50<<0), /* Port A, Pin0 */ - EVSYS_CHMUX_PORTA_PIN1_gc = (0x51<<0), /* Port A, Pin1 */ - EVSYS_CHMUX_PORTA_PIN2_gc = (0x52<<0), /* Port A, Pin2 */ - EVSYS_CHMUX_PORTA_PIN3_gc = (0x53<<0), /* Port A, Pin3 */ - EVSYS_CHMUX_PORTA_PIN4_gc = (0x54<<0), /* Port A, Pin4 */ - EVSYS_CHMUX_PORTA_PIN5_gc = (0x55<<0), /* Port A, Pin5 */ - EVSYS_CHMUX_PORTA_PIN6_gc = (0x56<<0), /* Port A, Pin6 */ - EVSYS_CHMUX_PORTA_PIN7_gc = (0x57<<0), /* Port A, Pin7 */ - EVSYS_CHMUX_PORTB_PIN0_gc = (0x58<<0), /* Port B, Pin0 */ - EVSYS_CHMUX_PORTB_PIN1_gc = (0x59<<0), /* Port B, Pin1 */ - EVSYS_CHMUX_PORTB_PIN2_gc = (0x5A<<0), /* Port B, Pin2 */ - EVSYS_CHMUX_PORTB_PIN3_gc = (0x5B<<0), /* Port B, Pin3 */ - EVSYS_CHMUX_PORTB_PIN4_gc = (0x5C<<0), /* Port B, Pin4 */ - EVSYS_CHMUX_PORTB_PIN5_gc = (0x5D<<0), /* Port B, Pin5 */ - EVSYS_CHMUX_PORTB_PIN6_gc = (0x5E<<0), /* Port B, Pin6 */ - EVSYS_CHMUX_PORTB_PIN7_gc = (0x5F<<0), /* Port B, Pin7 */ - EVSYS_CHMUX_PORTC_PIN0_gc = (0x60<<0), /* Port C, Pin0 */ - EVSYS_CHMUX_PORTC_PIN1_gc = (0x61<<0), /* Port C, Pin1 */ - EVSYS_CHMUX_PORTC_PIN2_gc = (0x62<<0), /* Port C, Pin2 */ - EVSYS_CHMUX_PORTC_PIN3_gc = (0x63<<0), /* Port C, Pin3 */ - EVSYS_CHMUX_PORTC_PIN4_gc = (0x64<<0), /* Port C, Pin4 */ - EVSYS_CHMUX_PORTC_PIN5_gc = (0x65<<0), /* Port C, Pin5 */ - EVSYS_CHMUX_PORTC_PIN6_gc = (0x66<<0), /* Port C, Pin6 */ - EVSYS_CHMUX_PORTC_PIN7_gc = (0x67<<0), /* Port C, Pin7 */ - EVSYS_CHMUX_PORTD_PIN0_gc = (0x68<<0), /* Port D, Pin0 */ - EVSYS_CHMUX_PORTD_PIN1_gc = (0x69<<0), /* Port D, Pin1 */ - EVSYS_CHMUX_PORTD_PIN2_gc = (0x6A<<0), /* Port D, Pin2 */ - EVSYS_CHMUX_PORTD_PIN3_gc = (0x6B<<0), /* Port D, Pin3 */ - EVSYS_CHMUX_PORTD_PIN4_gc = (0x6C<<0), /* Port D, Pin4 */ - EVSYS_CHMUX_PORTD_PIN5_gc = (0x6D<<0), /* Port D, Pin5 */ - EVSYS_CHMUX_PORTD_PIN6_gc = (0x6E<<0), /* Port D, Pin6 */ - EVSYS_CHMUX_PORTD_PIN7_gc = (0x6F<<0), /* Port D, Pin7 */ - EVSYS_CHMUX_PORTE_PIN0_gc = (0x70<<0), /* Port E, Pin0 */ - EVSYS_CHMUX_PORTE_PIN1_gc = (0x71<<0), /* Port E, Pin1 */ - EVSYS_CHMUX_PORTE_PIN2_gc = (0x72<<0), /* Port E, Pin2 */ - EVSYS_CHMUX_PORTE_PIN3_gc = (0x73<<0), /* Port E, Pin3 */ - EVSYS_CHMUX_PORTE_PIN4_gc = (0x74<<0), /* Port E, Pin4 */ - EVSYS_CHMUX_PORTE_PIN5_gc = (0x75<<0), /* Port E, Pin5 */ - EVSYS_CHMUX_PORTE_PIN6_gc = (0x76<<0), /* Port E, Pin6 */ - EVSYS_CHMUX_PORTE_PIN7_gc = (0x77<<0), /* Port E, Pin7 */ - EVSYS_CHMUX_PORTF_PIN0_gc = (0x78<<0), /* Port F, Pin0 */ - EVSYS_CHMUX_PORTF_PIN1_gc = (0x79<<0), /* Port F, Pin1 */ - EVSYS_CHMUX_PORTF_PIN2_gc = (0x7A<<0), /* Port F, Pin2 */ - EVSYS_CHMUX_PORTF_PIN3_gc = (0x7B<<0), /* Port F, Pin3 */ - EVSYS_CHMUX_PORTF_PIN4_gc = (0x7C<<0), /* Port F, Pin4 */ - EVSYS_CHMUX_PORTF_PIN5_gc = (0x7D<<0), /* Port F, Pin5 */ - EVSYS_CHMUX_PORTF_PIN6_gc = (0x7E<<0), /* Port F, Pin6 */ - EVSYS_CHMUX_PORTF_PIN7_gc = (0x7F<<0), /* Port F, Pin7 */ - EVSYS_CHMUX_PRESCALER_1_gc = (0x80<<0), /* Prescaler, divide by 1 */ - EVSYS_CHMUX_PRESCALER_2_gc = (0x81<<0), /* Prescaler, divide by 2 */ - EVSYS_CHMUX_PRESCALER_4_gc = (0x82<<0), /* Prescaler, divide by 4 */ - EVSYS_CHMUX_PRESCALER_8_gc = (0x83<<0), /* Prescaler, divide by 8 */ - EVSYS_CHMUX_PRESCALER_16_gc = (0x84<<0), /* Prescaler, divide by 16 */ - EVSYS_CHMUX_PRESCALER_32_gc = (0x85<<0), /* Prescaler, divide by 32 */ - EVSYS_CHMUX_PRESCALER_64_gc = (0x86<<0), /* Prescaler, divide by 64 */ - EVSYS_CHMUX_PRESCALER_128_gc = (0x87<<0), /* Prescaler, divide by 128 */ - EVSYS_CHMUX_PRESCALER_256_gc = (0x88<<0), /* Prescaler, divide by 256 */ - EVSYS_CHMUX_PRESCALER_512_gc = (0x89<<0), /* Prescaler, divide by 512 */ - EVSYS_CHMUX_PRESCALER_1024_gc = (0x8A<<0), /* Prescaler, divide by 1024 */ - EVSYS_CHMUX_PRESCALER_2048_gc = (0x8B<<0), /* Prescaler, divide by 2048 */ - EVSYS_CHMUX_PRESCALER_4096_gc = (0x8C<<0), /* Prescaler, divide by 4096 */ - EVSYS_CHMUX_PRESCALER_8192_gc = (0x8D<<0), /* Prescaler, divide by 8192 */ - EVSYS_CHMUX_PRESCALER_16384_gc = (0x8E<<0), /* Prescaler, divide by 16384 */ - EVSYS_CHMUX_PRESCALER_32768_gc = (0x8F<<0), /* Prescaler, divide by 32768 */ - EVSYS_CHMUX_TCC0_OVF_gc = (0xC0<<0), /* Timer/Counter C0 Overflow */ - EVSYS_CHMUX_TCC0_ERR_gc = (0xC1<<0), /* Timer/Counter C0 Error */ - EVSYS_CHMUX_TCC0_CCA_gc = (0xC4<<0), /* Timer/Counter C0 Compare or Capture A */ - EVSYS_CHMUX_TCC0_CCB_gc = (0xC5<<0), /* Timer/Counter C0 Compare or Capture B */ - EVSYS_CHMUX_TCC0_CCC_gc = (0xC6<<0), /* Timer/Counter C0 Compare or Capture C */ - EVSYS_CHMUX_TCC0_CCD_gc = (0xC7<<0), /* Timer/Counter C0 Compare or Capture D */ - EVSYS_CHMUX_TCC1_OVF_gc = (0xC8<<0), /* Timer/Counter C1 Overflow */ - EVSYS_CHMUX_TCC1_ERR_gc = (0xC9<<0), /* Timer/Counter C1 Error */ - EVSYS_CHMUX_TCC1_CCA_gc = (0xCC<<0), /* Timer/Counter C1 Compare or Capture A */ - EVSYS_CHMUX_TCC1_CCB_gc = (0xCD<<0), /* Timer/Counter C1 Compare or Capture B */ - EVSYS_CHMUX_TCD0_OVF_gc = (0xD0<<0), /* Timer/Counter D0 Overflow */ - EVSYS_CHMUX_TCD0_ERR_gc = (0xD1<<0), /* Timer/Counter D0 Error */ - EVSYS_CHMUX_TCD0_CCA_gc = (0xD4<<0), /* Timer/Counter D0 Compare or Capture A */ - EVSYS_CHMUX_TCD0_CCB_gc = (0xD5<<0), /* Timer/Counter D0 Compare or Capture B */ - EVSYS_CHMUX_TCD0_CCC_gc = (0xD6<<0), /* Timer/Counter D0 Compare or Capture C */ - EVSYS_CHMUX_TCD0_CCD_gc = (0xD7<<0), /* Timer/Counter D0 Compare or Capture D */ - EVSYS_CHMUX_TCE0_OVF_gc = (0xE0<<0), /* Timer/Counter E0 Overflow */ - EVSYS_CHMUX_TCE0_ERR_gc = (0xE1<<0), /* Timer/Counter E0 Error */ - EVSYS_CHMUX_TCE0_CCA_gc = (0xE4<<0), /* Timer/Counter E0 Compare or Capture A */ - EVSYS_CHMUX_TCE0_CCB_gc = (0xE5<<0), /* Timer/Counter E0 Compare or Capture B */ - EVSYS_CHMUX_TCE0_CCC_gc = (0xE6<<0), /* Timer/Counter E0 Compare or Capture C */ - EVSYS_CHMUX_TCE0_CCD_gc = (0xE7<<0), /* Timer/Counter E0 Compare or Capture D */ - EVSYS_CHMUX_TCF0_OVF_gc = (0xF0<<0), /* Timer/Counter F0 Overflow */ - EVSYS_CHMUX_TCF0_ERR_gc = (0xF1<<0), /* Timer/Counter F0 Error */ - EVSYS_CHMUX_TCF0_CCA_gc = (0xF4<<0), /* Timer/Counter F0 Compare or Capture A */ - EVSYS_CHMUX_TCF0_CCB_gc = (0xF5<<0), /* Timer/Counter F0 Compare or Capture B */ - EVSYS_CHMUX_TCF0_CCC_gc = (0xF6<<0), /* Timer/Counter F0 Compare or Capture C */ - EVSYS_CHMUX_TCF0_CCD_gc = (0xF7<<0), /* Timer/Counter F0 Compare or Capture D */ -} EVSYS_CHMUX_t; - - -/* --------------------------------------------------------------------------- -NVM - Non Volatile Memory Controller --------------------------------------------------------------------------- -*/ - -/* Non-volatile Memory Controller */ -typedef struct NVM_struct -{ - register8_t ADDR0; /* Address Register 0 */ - register8_t ADDR1; /* Address Register 1 */ - register8_t ADDR2; /* Address Register 2 */ - register8_t reserved_0x03; - register8_t DATA0; /* Data Register 0 */ - register8_t DATA1; /* Data Register 1 */ - register8_t DATA2; /* Data Register 2 */ - register8_t reserved_0x07; - register8_t reserved_0x08; - register8_t reserved_0x09; - register8_t CMD; /* Command */ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t INTCTRL; /* Interrupt Control */ - register8_t reserved_0x0E; - register8_t STATUS; /* Status */ - register8_t LOCK_BITS; /* Lock Bits (Changed from LOCKBITS to avoid avr-libc collision) */ -} NVM_t; - -/* NVM Command */ -typedef enum NVM_CMD_enum -{ - NVM_CMD_NO_OPERATION_gc = (0x00<<0), /* Noop/Ordinary LPM */ - NVM_CMD_READ_USER_SIG_ROW_gc = (0x01<<0), /* Read user signature row */ - NVM_CMD_READ_CALIB_ROW_gc = (0x02<<0), /* Read calibration row */ - NVM_CMD_READ_EEPROM_gc = (0x06<<0), /* Read EEPROM */ - NVM_CMD_READ_FUSES_gc = (0x07<<0), /* Read fuse byte */ - NVM_CMD_WRITE_LOCK_BITS_gc = (0x08<<0), /* Write lock bits */ - NVM_CMD_ERASE_USER_SIG_ROW_gc = (0x18<<0), /* Erase user signature row */ - NVM_CMD_WRITE_USER_SIG_ROW_gc = (0x1A<<0), /* Write user signature row */ - NVM_CMD_ERASE_APP_gc = (0x20<<0), /* Erase Application Section */ - NVM_CMD_ERASE_APP_PAGE_gc = (0x22<<0), /* Erase Application Section page */ - NVM_CMD_LOAD_FLASH_BUFFER_gc = (0x23<<0), /* Load Flash page buffer */ - NVM_CMD_WRITE_APP_PAGE_gc = (0x24<<0), /* Write Application Section page */ - NVM_CMD_ERASE_WRITE_APP_PAGE_gc = (0x25<<0), /* Erase-and-write Application Section page */ - NVM_CMD_ERASE_FLASH_BUFFER_gc = (0x26<<0), /* Erase/flush Flash page buffer */ - NVM_CMD_ERASE_BOOT_PAGE_gc = (0x2A<<0), /* Erase Boot Section page */ - NVM_CMD_ERASE_FLASH_PAGE_gc = (0x2B<<0), /* Erase Flash Page */ - NVM_CMD_WRITE_BOOT_PAGE_gc = (0x2C<<0), /* Write Boot Section page */ - NVM_CMD_ERASE_WRITE_BOOT_PAGE_gc = (0x2D<<0), /* Erase-and-write Boot Section page */ - NVM_CMD_WRITE_FLASH_PAGE_gc = (0x2E<<0), /* Write Flash Page */ - NVM_CMD_ERASE_WRITE_FLASH_PAGE_gc = (0x2F<<0), /* Erase-and-write Flash Page */ - NVM_CMD_ERASE_EEPROM_gc = (0x30<<0), /* Erase EEPROM */ - NVM_CMD_ERASE_EEPROM_PAGE_gc = (0x32<<0), /* Erase EEPROM page */ - NVM_CMD_LOAD_EEPROM_BUFFER_gc = (0x33<<0), /* Load EEPROM page buffer */ - NVM_CMD_WRITE_EEPROM_PAGE_gc = (0x34<<0), /* Write EEPROM page */ - NVM_CMD_ERASE_WRITE_EEPROM_PAGE_gc = (0x35<<0), /* Erase-and-write EEPROM page */ - NVM_CMD_ERASE_EEPROM_BUFFER_gc = (0x36<<0), /* Erase/flush EEPROM page buffer */ - NVM_CMD_APP_CRC_gc = (0x38<<0), /* Application section CRC */ - NVM_CMD_BOOT_CRC_gc = (0x39<<0), /* Boot Section CRC */ - NVM_CMD_FLASH_RANGE_CRC_gc = (0x3A<<0), /* Flash Range CRC */ - NVM_CMD_CHIP_ERASE_gc = (0x40<<0), /* Erase Chip */ - NVM_CMD_READ_NVM_gc = (0x43<<0), /* Read NVM */ - NVM_CMD_WRITE_FUSE_gc = (0x4C<<0), /* Write Fuse byte */ - NVM_CMD_ERASE_BOOT_gc = (0x68<<0), /* Erase Boot Section */ - NVM_CMD_FLASH_CRC_gc = (0x78<<0), /* Flash CRC */ -} NVM_CMD_t; - -/* SPM ready interrupt level */ -typedef enum NVM_SPMLVL_enum -{ - NVM_SPMLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ - NVM_SPMLVL_LO_gc = (0x01<<2), /* Low level */ - NVM_SPMLVL_MED_gc = (0x02<<2), /* Medium level */ - NVM_SPMLVL_HI_gc = (0x03<<2), /* High level */ -} NVM_SPMLVL_t; - -/* EEPROM ready interrupt level */ -typedef enum NVM_EELVL_enum -{ - NVM_EELVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ - NVM_EELVL_LO_gc = (0x01<<0), /* Low level */ - NVM_EELVL_MED_gc = (0x02<<0), /* Medium level */ - NVM_EELVL_HI_gc = (0x03<<0), /* High level */ -} NVM_EELVL_t; - -/* Boot lock bits - boot setcion */ -typedef enum NVM_BLBB_enum -{ - NVM_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ - NVM_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ - NVM_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ - NVM_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ -} NVM_BLBB_t; - -/* Boot lock bits - application section */ -typedef enum NVM_BLBA_enum -{ - NVM_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ - NVM_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ - NVM_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ - NVM_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ -} NVM_BLBA_t; - -/* Boot lock bits - application table section */ -typedef enum NVM_BLBAT_enum -{ - NVM_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ - NVM_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ - NVM_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ - NVM_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ -} NVM_BLBAT_t; - -/* Lock bits */ -typedef enum NVM_LB_enum -{ - NVM_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ - NVM_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ - NVM_LB_NOLOCK_gc = (0x03<<0), /* No locks */ -} NVM_LB_t; - - -/* --------------------------------------------------------------------------- -ADC - Analog/Digital Converter --------------------------------------------------------------------------- -*/ - -/* ADC Channel */ -typedef struct ADC_CH_struct -{ - register8_t CTRL; /* Control Register */ - register8_t MUXCTRL; /* MUX Control */ - register8_t INTCTRL; /* Channel Interrupt Control Register */ - register8_t INTFLAGS; /* Interrupt Flags */ - _WORDREGISTER(RES); /* Channel Result */ - register8_t SCAN; /* Input Channel Scan */ - register8_t reserved_0x07; -} ADC_CH_t; - - -/* Analog-to-Digital Converter */ -typedef struct ADC_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t REFCTRL; /* Reference Control */ - register8_t EVCTRL; /* Event Control */ - register8_t PRESCALER; /* Clock Prescaler */ - register8_t reserved_0x05; - register8_t INTFLAGS; /* Interrupt Flags */ - register8_t TEMP; /* Temporary Register */ - register8_t SAMPCTRL; /* ADC Sampling Time Control Register */ - register8_t reserved_0x09; - register8_t reserved_0x0A; - register8_t reserved_0x0B; - _WORDREGISTER(CAL); /* Calibration Value */ - register8_t reserved_0x0E; - register8_t reserved_0x0F; - _WORDREGISTER(CH0RES); /* Channel 0 Result */ - register8_t reserved_0x12; - register8_t reserved_0x13; - register8_t reserved_0x14; - register8_t reserved_0x15; - register8_t reserved_0x16; - register8_t reserved_0x17; - _WORDREGISTER(CMP); /* Compare Value */ - register8_t reserved_0x1A; - register8_t reserved_0x1B; - register8_t reserved_0x1C; - register8_t reserved_0x1D; - register8_t reserved_0x1E; - register8_t reserved_0x1F; - ADC_CH_t CH0; /* ADC Channel 0 */ -} ADC_t; - -/* Current Limitation */ -typedef enum ADC_CURRLIMIT_enum -{ - ADC_CURRLIMIT_NO_gc = (0x00<<5), /* No current limit, 300ksps max sampling rate */ - ADC_CURRLIMIT_LOW_gc = (0x01<<5), /* Low current limit, 250ksps max sampling rate */ - ADC_CURRLIMIT_MED_gc = (0x02<<5), /* Medium current limit, 150ksps max sampling rate */ - ADC_CURRLIMIT_HIGH_gc = (0x03<<5), /* High current limit, 50ksps max sampling rate */ -} ADC_CURRLIMIT_t; - -/* Positive input multiplexer selection */ -typedef enum ADC_CH_MUXPOS_enum -{ - ADC_CH_MUXPOS_PIN0_gc = (0x00<<3), /* Input pin 0 */ - ADC_CH_MUXPOS_PIN1_gc = (0x01<<3), /* Input pin 1 */ - ADC_CH_MUXPOS_PIN2_gc = (0x02<<3), /* Input pin 2 */ - ADC_CH_MUXPOS_PIN3_gc = (0x03<<3), /* Input pin 3 */ - ADC_CH_MUXPOS_PIN4_gc = (0x04<<3), /* Input pin 4 */ - ADC_CH_MUXPOS_PIN5_gc = (0x05<<3), /* Input pin 5 */ - ADC_CH_MUXPOS_PIN6_gc = (0x06<<3), /* Input pin 6 */ - ADC_CH_MUXPOS_PIN7_gc = (0x07<<3), /* Input pin 7 */ - ADC_CH_MUXPOS_PIN8_gc = (0x08<<3), /* Input pin 8 */ - ADC_CH_MUXPOS_PIN9_gc = (0x09<<3), /* Input pin 9 */ - ADC_CH_MUXPOS_PIN10_gc = (0x0A<<3), /* Input pin 10 */ - ADC_CH_MUXPOS_PIN11_gc = (0x0B<<3), /* Input pin 11 */ - ADC_CH_MUXPOS_PIN12_gc = (0x0C<<3), /* Input pin 12 */ - ADC_CH_MUXPOS_PIN13_gc = (0x0D<<3), /* Input pin 13 */ - ADC_CH_MUXPOS_PIN14_gc = (0x0E<<3), /* Input pin 14 */ - ADC_CH_MUXPOS_PIN15_gc = (0x0F<<3), /* Input pin 15 */ -} ADC_CH_MUXPOS_t; - -/* Internal input multiplexer selections */ -typedef enum ADC_CH_MUXINT_enum -{ - ADC_CH_MUXINT_TEMP_gc = (0x00<<3), /* Temperature Reference */ - ADC_CH_MUXINT_BANDGAP_gc = (0x01<<3), /* Bandgap Reference */ - ADC_CH_MUXINT_SCALEDVCC_gc = (0x02<<3), /* 1/10 scaled VCC */ -} ADC_CH_MUXINT_t; - -/* Negative input multiplexer selection */ -typedef enum ADC_CH_MUXNEG_enum -{ - ADC_CH_MUXNEG_PIN0_gc = (0x00<<0), /* Input pin 0 */ - ADC_CH_MUXNEG_PIN1_gc = (0x01<<0), /* Input pin 1 */ - ADC_CH_MUXNEG_PIN2_gc = (0x02<<0), /* Input pin 2 */ - ADC_CH_MUXNEG_PIN3_gc = (0x03<<0), /* Input pin 3 */ - ADC_CH_MUXNEG_PIN4_gc = (0x00<<0), /* Input pin 4 */ - ADC_CH_MUXNEG_PIN5_gc = (0x01<<0), /* Input pin 5 */ - ADC_CH_MUXNEG_PIN6_gc = (0x02<<0), /* Input pin 6 */ - ADC_CH_MUXNEG_PIN7_gc = (0x03<<0), /* Input pin 7 */ -} ADC_CH_MUXNEG_t; - -/* Input mode */ -typedef enum ADC_CH_INPUTMODE_enum -{ - ADC_CH_INPUTMODE_INTERNAL_gc = (0x00<<0), /* Internal inputs, no gain */ - ADC_CH_INPUTMODE_SINGLEENDED_gc = (0x01<<0), /* Single-ended input, no gain */ - ADC_CH_INPUTMODE_DIFF_gc = (0x02<<0), /* Differential input, no gain */ - ADC_CH_INPUTMODE_DIFFWGAIN_gc = (0x03<<0), /* Differential input, with gain */ -} ADC_CH_INPUTMODE_t; - -/* Gain factor */ -typedef enum ADC_CH_GAIN_enum -{ - ADC_CH_GAIN_1X_gc = (0x00<<2), /* 1x gain */ - ADC_CH_GAIN_2X_gc = (0x01<<2), /* 2x gain */ - ADC_CH_GAIN_4X_gc = (0x02<<2), /* 4x gain */ - ADC_CH_GAIN_8X_gc = (0x03<<2), /* 8x gain */ - ADC_CH_GAIN_16X_gc = (0x04<<2), /* 16x gain */ - ADC_CH_GAIN_32X_gc = (0x05<<2), /* 32x gain */ - ADC_CH_GAIN_64X_gc = (0x06<<2), /* 64x gain */ - ADC_CH_GAIN_DIV2_gc = (0x07<<2), /* x/2 gain */ -} ADC_CH_GAIN_t; - -/* Conversion result resolution */ -typedef enum ADC_RESOLUTION_enum -{ - ADC_RESOLUTION_12BIT_gc = (0x00<<1), /* 12-bit right-adjusted result */ - ADC_RESOLUTION_8BIT_gc = (0x02<<1), /* 8-bit right-adjusted result */ - ADC_RESOLUTION_LEFT12BIT_gc = (0x03<<1), /* 12-bit left-adjusted result */ -} ADC_RESOLUTION_t; - -/* Voltage reference selection */ -typedef enum ADC_REFSEL_enum -{ - ADC_REFSEL_INT1V_gc = (0x00<<4), /* Internal 1V */ - ADC_REFSEL_INTVCC_gc = (0x01<<4), /* Internal VCC / 1.6 */ - ADC_REFSEL_AREFA_gc = (0x02<<4), /* External reference on PORT A */ - ADC_REFSEL_AREFB_gc = (0x03<<4), /* External reference on PORT B */ - ADC_REFSEL_INTVCC2_gc = (0x04<<4), /* Internal VCC / 2 */ -} ADC_REFSEL_t; - -/* Event channel input selection */ -typedef enum ADC_EVSEL_enum -{ - ADC_EVSEL_0_gc = (0x00<<3), /* Event Channel 0 */ - ADC_EVSEL_1_gc = (0x01<<3), /* Event Channel 1 */ - ADC_EVSEL_2_gc = (0x02<<3), /* Event Channel 2 */ - ADC_EVSEL_3_gc = (0x03<<3), /* Event Channel 3 */ -} ADC_EVSEL_t; - -/* Event action selection */ -typedef enum ADC_EVACT_enum -{ - ADC_EVACT_NONE_gc = (0x00<<0), /* No event action */ - ADC_EVACT_CH0_gc = (0x01<<0), /* First event triggers channel 0 */ - ADC_EVACT_SYNCSWEEP_gc = (0x06<<0), /* The ADC is flushed and restarted for accurate timing */ -} ADC_EVACT_t; - -/* Interupt mode */ -typedef enum ADC_CH_INTMODE_enum -{ - ADC_CH_INTMODE_COMPLETE_gc = (0x00<<2), /* Interrupt on conversion complete */ - ADC_CH_INTMODE_BELOW_gc = (0x01<<2), /* Interrupt on result below compare value */ - ADC_CH_INTMODE_ABOVE_gc = (0x03<<2), /* Interrupt on result above compare value */ -} ADC_CH_INTMODE_t; - -/* Interrupt level */ -typedef enum ADC_CH_INTLVL_enum -{ - ADC_CH_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ - ADC_CH_INTLVL_LO_gc = (0x01<<0), /* Low level */ - ADC_CH_INTLVL_MED_gc = (0x02<<0), /* Medium level */ - ADC_CH_INTLVL_HI_gc = (0x03<<0), /* High level */ -} ADC_CH_INTLVL_t; - -/* Clock prescaler */ -typedef enum ADC_PRESCALER_enum -{ - ADC_PRESCALER_DIV4_gc = (0x00<<0), /* Divide clock by 4 */ - ADC_PRESCALER_DIV8_gc = (0x01<<0), /* Divide clock by 8 */ - ADC_PRESCALER_DIV16_gc = (0x02<<0), /* Divide clock by 16 */ - ADC_PRESCALER_DIV32_gc = (0x03<<0), /* Divide clock by 32 */ - ADC_PRESCALER_DIV64_gc = (0x04<<0), /* Divide clock by 64 */ - ADC_PRESCALER_DIV128_gc = (0x05<<0), /* Divide clock by 128 */ - ADC_PRESCALER_DIV256_gc = (0x06<<0), /* Divide clock by 256 */ - ADC_PRESCALER_DIV512_gc = (0x07<<0), /* Divide clock by 512 */ -} ADC_PRESCALER_t; - - -/* --------------------------------------------------------------------------- -AC - Analog Comparator --------------------------------------------------------------------------- -*/ - -/* Analog Comparator */ -typedef struct AC_struct -{ - register8_t AC0CTRL; /* Analog Comparator 0 Control */ - register8_t AC1CTRL; /* Analog Comparator 1 Control */ - register8_t AC0MUXCTRL; /* Analog Comparator 0 MUX Control */ - register8_t AC1MUXCTRL; /* Analog Comparator 1 MUX Control */ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t WINCTRL; /* Window Mode Control */ - register8_t STATUS; /* Status */ -} AC_t; - -/* Interrupt mode */ -typedef enum AC_INTMODE_enum -{ - AC_INTMODE_BOTHEDGES_gc = (0x00<<6), /* Interrupt on both edges */ - AC_INTMODE_FALLING_gc = (0x02<<6), /* Interrupt on falling edge */ - AC_INTMODE_RISING_gc = (0x03<<6), /* Interrupt on rising edge */ -} AC_INTMODE_t; - -/* Interrupt level */ -typedef enum AC_INTLVL_enum -{ - AC_INTLVL_OFF_gc = (0x00<<4), /* Interrupt disabled */ - AC_INTLVL_LO_gc = (0x01<<4), /* Low level */ - AC_INTLVL_MED_gc = (0x02<<4), /* Medium level */ - AC_INTLVL_HI_gc = (0x03<<4), /* High level */ -} AC_INTLVL_t; - -/* Hysteresis mode selection */ -typedef enum AC_HYSMODE_enum -{ - AC_HYSMODE_NO_gc = (0x00<<1), /* No hysteresis */ - AC_HYSMODE_SMALL_gc = (0x01<<1), /* Small hysteresis */ - AC_HYSMODE_LARGE_gc = (0x02<<1), /* Large hysteresis */ -} AC_HYSMODE_t; - -/* Positive input multiplexer selection */ -typedef enum AC_MUXPOS_enum -{ - AC_MUXPOS_PIN0_gc = (0x00<<3), /* Pin 0 */ - AC_MUXPOS_PIN1_gc = (0x01<<3), /* Pin 1 */ - AC_MUXPOS_PIN2_gc = (0x02<<3), /* Pin 2 */ - AC_MUXPOS_PIN3_gc = (0x03<<3), /* Pin 3 */ - AC_MUXPOS_PIN4_gc = (0x04<<3), /* Pin 4 */ - AC_MUXPOS_PIN5_gc = (0x05<<3), /* Pin 5 */ - AC_MUXPOS_PIN6_gc = (0x06<<3), /* Pin 6 */ -} AC_MUXPOS_t; - -/* Negative input multiplexer selection */ -typedef enum AC_MUXNEG_enum -{ - AC_MUXNEG_PIN0_gc = (0x00<<0), /* Pin 0 */ - AC_MUXNEG_PIN1_gc = (0x01<<0), /* Pin 1 */ - AC_MUXNEG_PIN3_gc = (0x02<<0), /* Pin 3 */ - AC_MUXNEG_PIN5_gc = (0x03<<0), /* Pin 5 */ - AC_MUXNEG_PIN7_gc = (0x04<<0), /* Pin 7 */ - AC_MUXNEG_BANDGAP_gc = (0x06<<0), /* Bandgap Reference */ - AC_MUXNEG_SCALER_gc = (0x07<<0), /* Internal voltage scaler */ -} AC_MUXNEG_t; - -/* Windows interrupt mode */ -typedef enum AC_WINTMODE_enum -{ - AC_WINTMODE_ABOVE_gc = (0x00<<2), /* Interrupt on above window */ - AC_WINTMODE_INSIDE_gc = (0x01<<2), /* Interrupt on inside window */ - AC_WINTMODE_BELOW_gc = (0x02<<2), /* Interrupt on below window */ - AC_WINTMODE_OUTSIDE_gc = (0x03<<2), /* Interrupt on outside window */ -} AC_WINTMODE_t; - -/* Window interrupt level */ -typedef enum AC_WINTLVL_enum -{ - AC_WINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ - AC_WINTLVL_LO_gc = (0x01<<0), /* Low priority */ - AC_WINTLVL_MED_gc = (0x02<<0), /* Medium priority */ - AC_WINTLVL_HI_gc = (0x03<<0), /* High priority */ -} AC_WINTLVL_t; - -/* Window mode state */ -typedef enum AC_WSTATE_enum -{ - AC_WSTATE_ABOVE_gc = (0x00<<6), /* Signal above window */ - AC_WSTATE_INSIDE_gc = (0x01<<6), /* Signal inside window */ - AC_WSTATE_BELOW_gc = (0x02<<6), /* Signal below window */ -} AC_WSTATE_t; - - -/* --------------------------------------------------------------------------- -RTC - Real-Time Counter --------------------------------------------------------------------------- -*/ - -/* Real-Time Counter */ -typedef struct RTC_struct -{ - register8_t CTRL; /* Control Register */ - register8_t STATUS; /* Status Register */ - register8_t INTCTRL; /* Interrupt Control Register */ - register8_t INTFLAGS; /* Interrupt Flags */ - register8_t TEMP; /* Temporary register */ - register8_t reserved_0x05; - register8_t reserved_0x06; - register8_t reserved_0x07; - _WORDREGISTER(CNT); /* Count Register */ - _WORDREGISTER(PER); /* Period Register */ - _WORDREGISTER(COMP); /* Compare Register */ -} RTC_t; - -/* Prescaler Factor */ -typedef enum RTC_PRESCALER_enum -{ - RTC_PRESCALER_OFF_gc = (0x00<<0), /* RTC Off */ - RTC_PRESCALER_DIV1_gc = (0x01<<0), /* RTC Clock */ - RTC_PRESCALER_DIV2_gc = (0x02<<0), /* RTC Clock / 2 */ - RTC_PRESCALER_DIV8_gc = (0x03<<0), /* RTC Clock / 8 */ - RTC_PRESCALER_DIV16_gc = (0x04<<0), /* RTC Clock / 16 */ - RTC_PRESCALER_DIV64_gc = (0x05<<0), /* RTC Clock / 64 */ - RTC_PRESCALER_DIV256_gc = (0x06<<0), /* RTC Clock / 256 */ - RTC_PRESCALER_DIV1024_gc = (0x07<<0), /* RTC Clock / 1024 */ -} RTC_PRESCALER_t; - -/* Compare Interrupt level */ -typedef enum RTC_COMPINTLVL_enum -{ - RTC_COMPINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ - RTC_COMPINTLVL_LO_gc = (0x01<<2), /* Low Level */ - RTC_COMPINTLVL_MED_gc = (0x02<<2), /* Medium Level */ - RTC_COMPINTLVL_HI_gc = (0x03<<2), /* High Level */ -} RTC_COMPINTLVL_t; - -/* Overflow Interrupt level */ -typedef enum RTC_OVFINTLVL_enum -{ - RTC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - RTC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ - RTC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ - RTC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ -} RTC_OVFINTLVL_t; - - -/* --------------------------------------------------------------------------- -TWI - Two-Wire Interface --------------------------------------------------------------------------- -*/ - -/* */ -typedef struct TWI_MASTER_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t CTRLC; /* Control Register C */ - register8_t STATUS; /* Status Register */ - register8_t BAUD; /* Baurd Rate Control Register */ - register8_t ADDR; /* Address Register */ - register8_t DATA; /* Data Register */ -} TWI_MASTER_t; - - -/* */ -typedef struct TWI_SLAVE_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t STATUS; /* Status Register */ - register8_t ADDR; /* Address Register */ - register8_t DATA; /* Data Register */ - register8_t ADDRMASK; /* Address Mask Register */ -} TWI_SLAVE_t; - - -/* Two-Wire Interface */ -typedef struct TWI_struct -{ - register8_t CTRL; /* TWI Common Control Register */ - TWI_MASTER_t MASTER; /* TWI master module */ - TWI_SLAVE_t SLAVE; /* TWI slave module */ -} TWI_t; - -/* SDA Hold Time */ -typedef enum TWI_SDAHOLD_enum -{ - TWI_SDAHOLD_OFF_gc = (0x00<<1), /* SDA Hold Time off */ - TWI_SDAHOLD_50NS_gc = (0x01<<1), /* SDA Hold Time 50 ns */ - TWI_SDAHOLD_300NS_gc = (0x02<<1), /* SDA Hold Time 300 ns */ - TWI_SDAHOLD_400NS_gc = (0x03<<1), /* SDA Hold Time 400 ns */ -} TWI_SDAHOLD_t; - -/* Master Interrupt Level */ -typedef enum TWI_MASTER_INTLVL_enum -{ - TWI_MASTER_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ - TWI_MASTER_INTLVL_LO_gc = (0x01<<6), /* Low Level */ - TWI_MASTER_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ - TWI_MASTER_INTLVL_HI_gc = (0x03<<6), /* High Level */ -} TWI_MASTER_INTLVL_t; - -/* Inactive Timeout */ -typedef enum TWI_MASTER_TIMEOUT_enum -{ - TWI_MASTER_TIMEOUT_DISABLED_gc = (0x00<<2), /* Bus Timeout Disabled */ - TWI_MASTER_TIMEOUT_50US_gc = (0x01<<2), /* 50 Microseconds */ - TWI_MASTER_TIMEOUT_100US_gc = (0x02<<2), /* 100 Microseconds */ - TWI_MASTER_TIMEOUT_200US_gc = (0x03<<2), /* 200 Microseconds */ -} TWI_MASTER_TIMEOUT_t; - -/* Master Command */ -typedef enum TWI_MASTER_CMD_enum -{ - TWI_MASTER_CMD_NOACT_gc = (0x00<<0), /* No Action */ - TWI_MASTER_CMD_REPSTART_gc = (0x01<<0), /* Issue Repeated Start Condition */ - TWI_MASTER_CMD_RECVTRANS_gc = (0x02<<0), /* Receive or Transmit Data */ - TWI_MASTER_CMD_STOP_gc = (0x03<<0), /* Issue Stop Condition */ -} TWI_MASTER_CMD_t; - -/* Master Bus State */ -typedef enum TWI_MASTER_BUSSTATE_enum -{ - TWI_MASTER_BUSSTATE_UNKNOWN_gc = (0x00<<0), /* Unknown Bus State */ - TWI_MASTER_BUSSTATE_IDLE_gc = (0x01<<0), /* Bus is Idle */ - TWI_MASTER_BUSSTATE_OWNER_gc = (0x02<<0), /* This Module Controls The Bus */ - TWI_MASTER_BUSSTATE_BUSY_gc = (0x03<<0), /* The Bus is Busy */ -} TWI_MASTER_BUSSTATE_t; - -/* Slave Interrupt Level */ -typedef enum TWI_SLAVE_INTLVL_enum -{ - TWI_SLAVE_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ - TWI_SLAVE_INTLVL_LO_gc = (0x01<<6), /* Low Level */ - TWI_SLAVE_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ - TWI_SLAVE_INTLVL_HI_gc = (0x03<<6), /* High Level */ -} TWI_SLAVE_INTLVL_t; - -/* Slave Command */ -typedef enum TWI_SLAVE_CMD_enum -{ - TWI_SLAVE_CMD_NOACT_gc = (0x00<<0), /* No Action */ - TWI_SLAVE_CMD_COMPTRANS_gc = (0x02<<0), /* Used To Complete a Transaction */ - TWI_SLAVE_CMD_RESPONSE_gc = (0x03<<0), /* Used in Response to Address/Data Interrupt */ -} TWI_SLAVE_CMD_t; - - -/* --------------------------------------------------------------------------- -PORT - I/O Port Configuration --------------------------------------------------------------------------- -*/ - -/* I/O Ports */ -typedef struct PORT_struct -{ - register8_t DIR; /* I/O Port Data Direction */ - register8_t DIRSET; /* I/O Port Data Direction Set */ - register8_t DIRCLR; /* I/O Port Data Direction Clear */ - register8_t DIRTGL; /* I/O Port Data Direction Toggle */ - register8_t OUT; /* I/O Port Output */ - register8_t OUTSET; /* I/O Port Output Set */ - register8_t OUTCLR; /* I/O Port Output Clear */ - register8_t OUTTGL; /* I/O Port Output Toggle */ - register8_t IN; /* I/O port Input */ - register8_t INTCTRL; /* Interrupt Control Register */ - register8_t INT0MASK; /* Port Interrupt 0 Mask */ - register8_t INT1MASK; /* Port Interrupt 1 Mask */ - register8_t INTFLAGS; /* Interrupt Flag Register */ - register8_t reserved_0x0D; - register8_t REMAP; /* I/O Port Pin Remap Register */ - register8_t reserved_0x0F; - register8_t PIN0CTRL; /* Pin 0 Control Register */ - register8_t PIN1CTRL; /* Pin 1 Control Register */ - register8_t PIN2CTRL; /* Pin 2 Control Register */ - register8_t PIN3CTRL; /* Pin 3 Control Register */ - register8_t PIN4CTRL; /* Pin 4 Control Register */ - register8_t PIN5CTRL; /* Pin 5 Control Register */ - register8_t PIN6CTRL; /* Pin 6 Control Register */ - register8_t PIN7CTRL; /* Pin 7 Control Register */ -} PORT_t; - -/* Port Interrupt 0 Level */ -typedef enum PORT_INT0LVL_enum -{ - PORT_INT0LVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - PORT_INT0LVL_LO_gc = (0x01<<0), /* Low Level */ - PORT_INT0LVL_MED_gc = (0x02<<0), /* Medium Level */ - PORT_INT0LVL_HI_gc = (0x03<<0), /* High Level */ -} PORT_INT0LVL_t; - -/* Port Interrupt 1 Level */ -typedef enum PORT_INT1LVL_enum -{ - PORT_INT1LVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ - PORT_INT1LVL_LO_gc = (0x01<<2), /* Low Level */ - PORT_INT1LVL_MED_gc = (0x02<<2), /* Medium Level */ - PORT_INT1LVL_HI_gc = (0x03<<2), /* High Level */ -} PORT_INT1LVL_t; - -/* Output/Pull Configuration */ -typedef enum PORT_OPC_enum -{ - PORT_OPC_TOTEM_gc = (0x00<<3), /* Totempole */ - PORT_OPC_BUSKEEPER_gc = (0x01<<3), /* Totempole w/ Bus keeper on Input and Output */ - PORT_OPC_PULLDOWN_gc = (0x02<<3), /* Totempole w/ Pull-down on Input */ - PORT_OPC_PULLUP_gc = (0x03<<3), /* Totempole w/ Pull-up on Input */ - PORT_OPC_WIREDOR_gc = (0x04<<3), /* Wired OR */ - PORT_OPC_WIREDAND_gc = (0x05<<3), /* Wired AND */ - PORT_OPC_WIREDORPULL_gc = (0x06<<3), /* Wired OR w/ Pull-down */ - PORT_OPC_WIREDANDPULL_gc = (0x07<<3), /* Wired AND w/ Pull-up */ -} PORT_OPC_t; - -/* Input/Sense Configuration */ -typedef enum PORT_ISC_enum -{ - PORT_ISC_BOTHEDGES_gc = (0x00<<0), /* Sense Both Edges */ - PORT_ISC_RISING_gc = (0x01<<0), /* Sense Rising Edge */ - PORT_ISC_FALLING_gc = (0x02<<0), /* Sense Falling Edge */ - PORT_ISC_LEVEL_gc = (0x03<<0), /* Sense Level (Transparent For Events) */ - PORT_ISC_INPUT_DISABLE_gc = (0x07<<0), /* Disable Digital Input Buffer */ -} PORT_ISC_t; - - -/* --------------------------------------------------------------------------- -TC - 16-bit Timer/Counter With PWM --------------------------------------------------------------------------- -*/ - -/* 16-bit Timer/Counter 0 */ -typedef struct TC0_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t CTRLC; /* Control register C */ - register8_t CTRLD; /* Control Register D */ - register8_t CTRLE; /* Control Register E */ - register8_t reserved_0x05; - register8_t INTCTRLA; /* Interrupt Control Register A */ - register8_t INTCTRLB; /* Interrupt Control Register B */ - register8_t CTRLFCLR; /* Control Register F Clear */ - register8_t CTRLFSET; /* Control Register F Set */ - register8_t CTRLGCLR; /* Control Register G Clear */ - register8_t CTRLGSET; /* Control Register G Set */ - register8_t INTFLAGS; /* Interrupt Flag Register */ - register8_t reserved_0x0D; - register8_t reserved_0x0E; - register8_t TEMP; /* Temporary Register For 16-bit Access */ - register8_t reserved_0x10; - register8_t reserved_0x11; - register8_t reserved_0x12; - register8_t reserved_0x13; - register8_t reserved_0x14; - register8_t reserved_0x15; - register8_t reserved_0x16; - register8_t reserved_0x17; - register8_t reserved_0x18; - register8_t reserved_0x19; - register8_t reserved_0x1A; - register8_t reserved_0x1B; - register8_t reserved_0x1C; - register8_t reserved_0x1D; - register8_t reserved_0x1E; - register8_t reserved_0x1F; - _WORDREGISTER(CNT); /* Count */ - register8_t reserved_0x22; - register8_t reserved_0x23; - register8_t reserved_0x24; - register8_t reserved_0x25; - _WORDREGISTER(PER); /* Period */ - _WORDREGISTER(CCA); /* Compare or Capture A */ - _WORDREGISTER(CCB); /* Compare or Capture B */ - _WORDREGISTER(CCC); /* Compare or Capture C */ - _WORDREGISTER(CCD); /* Compare or Capture D */ - register8_t reserved_0x30; - register8_t reserved_0x31; - register8_t reserved_0x32; - register8_t reserved_0x33; - register8_t reserved_0x34; - register8_t reserved_0x35; - _WORDREGISTER(PERBUF); /* Period Buffer */ - _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ - _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ - _WORDREGISTER(CCCBUF); /* Compare Or Capture C Buffer */ - _WORDREGISTER(CCDBUF); /* Compare Or Capture D Buffer */ -} TC0_t; - - -/* 16-bit Timer/Counter 1 */ -typedef struct TC1_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t CTRLC; /* Control register C */ - register8_t CTRLD; /* Control Register D */ - register8_t CTRLE; /* Control Register E */ - register8_t reserved_0x05; - register8_t INTCTRLA; /* Interrupt Control Register A */ - register8_t INTCTRLB; /* Interrupt Control Register B */ - register8_t CTRLFCLR; /* Control Register F Clear */ - register8_t CTRLFSET; /* Control Register F Set */ - register8_t CTRLGCLR; /* Control Register G Clear */ - register8_t CTRLGSET; /* Control Register G Set */ - register8_t INTFLAGS; /* Interrupt Flag Register */ - register8_t reserved_0x0D; - register8_t reserved_0x0E; - register8_t TEMP; /* Temporary Register For 16-bit Access */ - register8_t reserved_0x10; - register8_t reserved_0x11; - register8_t reserved_0x12; - register8_t reserved_0x13; - register8_t reserved_0x14; - register8_t reserved_0x15; - register8_t reserved_0x16; - register8_t reserved_0x17; - register8_t reserved_0x18; - register8_t reserved_0x19; - register8_t reserved_0x1A; - register8_t reserved_0x1B; - register8_t reserved_0x1C; - register8_t reserved_0x1D; - register8_t reserved_0x1E; - register8_t reserved_0x1F; - _WORDREGISTER(CNT); /* Count */ - register8_t reserved_0x22; - register8_t reserved_0x23; - register8_t reserved_0x24; - register8_t reserved_0x25; - _WORDREGISTER(PER); /* Period */ - _WORDREGISTER(CCA); /* Compare or Capture A */ - _WORDREGISTER(CCB); /* Compare or Capture B */ - register8_t reserved_0x2C; - register8_t reserved_0x2D; - register8_t reserved_0x2E; - register8_t reserved_0x2F; - register8_t reserved_0x30; - register8_t reserved_0x31; - register8_t reserved_0x32; - register8_t reserved_0x33; - register8_t reserved_0x34; - register8_t reserved_0x35; - _WORDREGISTER(PERBUF); /* Period Buffer */ - _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ - _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ -} TC1_t; - -/* Clock Selection */ -typedef enum TC_CLKSEL_enum -{ - TC_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */ - TC_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */ - TC_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */ - TC_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */ - TC_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */ - TC_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */ - TC_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */ - TC_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */ - TC_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */ - TC_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */ - TC_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */ - TC_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */ -} TC_CLKSEL_t; - -/* Waveform Generation Mode */ -typedef enum TC_WGMODE_enum -{ - TC_WGMODE_NORMAL_gc = (0x00<<0), /* Normal Mode */ - TC_WGMODE_FRQ_gc = (0x01<<0), /* Frequency Generation Mode */ - TC_WGMODE_SINGLESLOPE_gc = (0x03<<0), /* Single Slope */ - TC_WGMODE_SS_gc = (0x03<<0), /* Single Slope */ - TC_WGMODE_DSTOP_gc = (0x05<<0), /* Dual Slope, Update on TOP */ - TC_WGMODE_DS_T_gc = (0x05<<0), /* Dual Slope, Update on TOP */ - TC_WGMODE_DSBOTH_gc = (0x06<<0), /* Dual Slope, Update on both TOP and BOTTOM */ - TC_WGMODE_DS_TB_gc = (0x06<<0), /* Dual Slope, Update on both TOP and BOTTOM */ - TC_WGMODE_DSBOTTOM_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */ - TC_WGMODE_DS_B_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */ -} TC_WGMODE_t; - -/* Byte Mode */ -typedef enum TC_BYTEM_enum -{ - TC_BYTEM_NORMAL_gc = (0x00<<0), /* 16-bit mode */ - TC_BYTEM_BYTEMODE_gc = (0x01<<0), /* Timer/Counter operating in byte mode only */ - TC_BYTEM_SPLITMODE_gc = (0x02<<0), /* Timer/Counter split into two 8-bit Counters (TC2) */ -} TC_BYTEM_t; - -/* Event Action */ -typedef enum TC_EVACT_enum -{ - TC_EVACT_OFF_gc = (0x00<<5), /* No Event Action */ - TC_EVACT_CAPT_gc = (0x01<<5), /* Input Capture */ - TC_EVACT_UPDOWN_gc = (0x02<<5), /* Externally Controlled Up/Down Count */ - TC_EVACT_QDEC_gc = (0x03<<5), /* Quadrature Decode */ - TC_EVACT_RESTART_gc = (0x04<<5), /* Restart */ - TC_EVACT_FRQ_gc = (0x05<<5), /* Frequency Capture */ - TC_EVACT_PW_gc = (0x06<<5), /* Pulse-width Capture */ -} TC_EVACT_t; - -/* Event Selection */ -typedef enum TC_EVSEL_enum -{ - TC_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ - TC_EVSEL_CH0_gc = (0x08<<0), /* Event Channel 0 */ - TC_EVSEL_CH1_gc = (0x09<<0), /* Event Channel 1 */ - TC_EVSEL_CH2_gc = (0x0A<<0), /* Event Channel 2 */ - TC_EVSEL_CH3_gc = (0x0B<<0), /* Event Channel 3 */ -} TC_EVSEL_t; - -/* Error Interrupt Level */ -typedef enum TC_ERRINTLVL_enum -{ - TC_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ - TC_ERRINTLVL_LO_gc = (0x01<<2), /* Low Level */ - TC_ERRINTLVL_MED_gc = (0x02<<2), /* Medium Level */ - TC_ERRINTLVL_HI_gc = (0x03<<2), /* High Level */ -} TC_ERRINTLVL_t; - -/* Overflow Interrupt Level */ -typedef enum TC_OVFINTLVL_enum -{ - TC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - TC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ - TC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ - TC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ -} TC_OVFINTLVL_t; - -/* Compare or Capture D Interrupt Level */ -typedef enum TC_CCDINTLVL_enum -{ - TC_CCDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ - TC_CCDINTLVL_LO_gc = (0x01<<6), /* Low Level */ - TC_CCDINTLVL_MED_gc = (0x02<<6), /* Medium Level */ - TC_CCDINTLVL_HI_gc = (0x03<<6), /* High Level */ -} TC_CCDINTLVL_t; - -/* Compare or Capture C Interrupt Level */ -typedef enum TC_CCCINTLVL_enum -{ - TC_CCCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ - TC_CCCINTLVL_LO_gc = (0x01<<4), /* Low Level */ - TC_CCCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ - TC_CCCINTLVL_HI_gc = (0x03<<4), /* High Level */ -} TC_CCCINTLVL_t; - -/* Compare or Capture B Interrupt Level */ -typedef enum TC_CCBINTLVL_enum -{ - TC_CCBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ - TC_CCBINTLVL_LO_gc = (0x01<<2), /* Low Level */ - TC_CCBINTLVL_MED_gc = (0x02<<2), /* Medium Level */ - TC_CCBINTLVL_HI_gc = (0x03<<2), /* High Level */ -} TC_CCBINTLVL_t; - -/* Compare or Capture A Interrupt Level */ -typedef enum TC_CCAINTLVL_enum -{ - TC_CCAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - TC_CCAINTLVL_LO_gc = (0x01<<0), /* Low Level */ - TC_CCAINTLVL_MED_gc = (0x02<<0), /* Medium Level */ - TC_CCAINTLVL_HI_gc = (0x03<<0), /* High Level */ -} TC_CCAINTLVL_t; - -/* Timer/Counter Command */ -typedef enum TC_CMD_enum -{ - TC_CMD_NONE_gc = (0x00<<2), /* No Command */ - TC_CMD_UPDATE_gc = (0x01<<2), /* Force Update */ - TC_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ - TC_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ -} TC_CMD_t; - - -/* --------------------------------------------------------------------------- -TC2 - 16-bit Timer/Counter type 2 --------------------------------------------------------------------------- -*/ - -/* 16-bit Timer/Counter type 2 */ -typedef struct TC2_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t CTRLC; /* Control register C */ - register8_t reserved_0x03; - register8_t CTRLE; /* Control Register E */ - register8_t reserved_0x05; - register8_t INTCTRLA; /* Interrupt Control Register A */ - register8_t INTCTRLB; /* Interrupt Control Register B */ - register8_t reserved_0x08; - register8_t CTRLF; /* Control Register F */ - register8_t reserved_0x0A; - register8_t reserved_0x0B; - register8_t INTFLAGS; /* Interrupt Flag Register */ - register8_t reserved_0x0D; - register8_t reserved_0x0E; - register8_t reserved_0x0F; - register8_t reserved_0x10; - register8_t reserved_0x11; - register8_t reserved_0x12; - register8_t reserved_0x13; - register8_t reserved_0x14; - register8_t reserved_0x15; - register8_t reserved_0x16; - register8_t reserved_0x17; - register8_t reserved_0x18; - register8_t reserved_0x19; - register8_t reserved_0x1A; - register8_t reserved_0x1B; - register8_t reserved_0x1C; - register8_t reserved_0x1D; - register8_t reserved_0x1E; - register8_t reserved_0x1F; - register8_t LCNT; /* Low Byte Count */ - register8_t HCNT; /* High Byte Count */ - register8_t reserved_0x22; - register8_t reserved_0x23; - register8_t reserved_0x24; - register8_t reserved_0x25; - register8_t LPER; /* Low Byte Period */ - register8_t HPER; /* High Byte Period */ - register8_t LCMPA; /* Low Byte Compare A */ - register8_t HCMPA; /* High Byte Compare A */ - register8_t LCMPB; /* Low Byte Compare B */ - register8_t HCMPB; /* High Byte Compare B */ - register8_t LCMPC; /* Low Byte Compare C */ - register8_t HCMPC; /* High Byte Compare C */ - register8_t LCMPD; /* Low Byte Compare D */ - register8_t HCMPD; /* High Byte Compare D */ -} TC2_t; - -/* Clock Selection */ -typedef enum TC2_CLKSEL_enum -{ - TC2_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */ - TC2_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */ - TC2_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */ - TC2_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */ - TC2_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */ - TC2_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */ - TC2_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */ - TC2_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */ - TC2_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */ - TC2_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */ - TC2_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */ - TC2_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */ -} TC2_CLKSEL_t; - -/* Byte Mode */ -typedef enum TC2_BYTEM_enum -{ - TC2_BYTEM_NORMAL_gc = (0x00<<0), /* 16-bit mode */ - TC2_BYTEM_BYTEMODE_gc = (0x01<<0), /* Timer/Counter operating in byte mode only (TC2) */ - TC2_BYTEM_SPLITMODE_gc = (0x02<<0), /* Timer/Counter split into two 8-bit Counters */ -} TC2_BYTEM_t; - -/* High Byte Underflow Interrupt Level */ -typedef enum TC2_HUNFINTLVL_enum -{ - TC2_HUNFINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ - TC2_HUNFINTLVL_LO_gc = (0x01<<2), /* Low Level */ - TC2_HUNFINTLVL_MED_gc = (0x02<<2), /* Medium Level */ - TC2_HUNFINTLVL_HI_gc = (0x03<<2), /* High Level */ -} TC2_HUNFINTLVL_t; - -/* Low Byte Underflow Interrupt Level */ -typedef enum TC2_LUNFINTLVL_enum -{ - TC2_LUNFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - TC2_LUNFINTLVL_LO_gc = (0x01<<0), /* Low Level */ - TC2_LUNFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ - TC2_LUNFINTLVL_HI_gc = (0x03<<0), /* High Level */ -} TC2_LUNFINTLVL_t; - -/* Low Byte Compare D Interrupt Level */ -typedef enum TC2_LCMPDINTLVL_enum -{ - TC2_LCMPDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ - TC2_LCMPDINTLVL_LO_gc = (0x01<<6), /* Low Level */ - TC2_LCMPDINTLVL_MED_gc = (0x02<<6), /* Medium Level */ - TC2_LCMPDINTLVL_HI_gc = (0x03<<6), /* High Level */ -} TC2_LCMPDINTLVL_t; - -/* Low Byte Compare C Interrupt Level */ -typedef enum TC2_LCMPCINTLVL_enum -{ - TC2_LCMPCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ - TC2_LCMPCINTLVL_LO_gc = (0x01<<4), /* Low Level */ - TC2_LCMPCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ - TC2_LCMPCINTLVL_HI_gc = (0x03<<4), /* High Level */ -} TC2_LCMPCINTLVL_t; - -/* Low Byte Compare B Interrupt Level */ -typedef enum TC2_LCMPBINTLVL_enum -{ - TC2_LCMPBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ - TC2_LCMPBINTLVL_LO_gc = (0x01<<2), /* Low Level */ - TC2_LCMPBINTLVL_MED_gc = (0x02<<2), /* Medium Level */ - TC2_LCMPBINTLVL_HI_gc = (0x03<<2), /* High Level */ -} TC2_LCMPBINTLVL_t; - -/* Low Byte Compare A Interrupt Level */ -typedef enum TC2_LCMPAINTLVL_enum -{ - TC2_LCMPAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - TC2_LCMPAINTLVL_LO_gc = (0x01<<0), /* Low Level */ - TC2_LCMPAINTLVL_MED_gc = (0x02<<0), /* Medium Level */ - TC2_LCMPAINTLVL_HI_gc = (0x03<<0), /* High Level */ -} TC2_LCMPAINTLVL_t; - -/* Timer/Counter Command */ -typedef enum TC2_CMD_enum -{ - TC2_CMD_NONE_gc = (0x00<<2), /* No Command */ - TC2_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ - TC2_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ -} TC2_CMD_t; - -/* Timer/Counter Command */ -typedef enum TC2_CMDEN_enum -{ - TC2_CMDEN_LOW_gc = (0x01<<0), /* Low Byte Timer/Counter */ - TC2_CMDEN_HIGH_gc = (0x02<<0), /* High Byte Timer/Counter */ - TC2_CMDEN_BOTH_gc = (0x03<<0), /* Both Low Byte and High Byte Timer/Counters */ -} TC2_CMDEN_t; - - -/* --------------------------------------------------------------------------- -AWEX - Timer/Counter Advanced Waveform Extension --------------------------------------------------------------------------- -*/ - -/* Advanced Waveform Extension */ -typedef struct AWEX_struct -{ - register8_t CTRL; /* Control Register */ - register8_t reserved_0x01; - register8_t FDEMASK; /* Fault Detection Event Mask */ - register8_t FDCTRL; /* Fault Detection Control Register */ - register8_t STATUS; /* Status Register */ - register8_t STATUSSET; /* Status Set Register */ - register8_t DTBOTH; /* Dead Time Both Sides */ - register8_t DTBOTHBUF; /* Dead Time Both Sides Buffer */ - register8_t DTLS; /* Dead Time Low Side */ - register8_t DTHS; /* Dead Time High Side */ - register8_t DTLSBUF; /* Dead Time Low Side Buffer */ - register8_t DTHSBUF; /* Dead Time High Side Buffer */ - register8_t OUTOVEN; /* Output Override Enable */ -} AWEX_t; - -/* Fault Detect Action */ -typedef enum AWEX_FDACT_enum -{ - AWEX_FDACT_NONE_gc = (0x00<<0), /* No Fault Protection */ - AWEX_FDACT_CLEAROE_gc = (0x01<<0), /* Clear Output Enable Bits */ - AWEX_FDACT_CLEARDIR_gc = (0x03<<0), /* Clear I/O Port Direction Bits */ -} AWEX_FDACT_t; - - -/* --------------------------------------------------------------------------- -HIRES - Timer/Counter High-Resolution Extension --------------------------------------------------------------------------- -*/ - -/* High-Resolution Extension */ -typedef struct HIRES_struct -{ - register8_t CTRLA; /* Control Register */ -} HIRES_t; - -/* High Resolution Enable */ -typedef enum HIRES_HREN_enum -{ - HIRES_HREN_NONE_gc = (0x00<<0), /* No Fault Protection */ - HIRES_HREN_TC0_gc = (0x01<<0), /* Enable High Resolution on Timer/Counter 0 */ - HIRES_HREN_TC1_gc = (0x02<<0), /* Enable High Resolution on Timer/Counter 1 */ - HIRES_HREN_BOTH_gc = (0x03<<0), /* Enable High Resolution both Timer/Counters */ -} HIRES_HREN_t; - - -/* --------------------------------------------------------------------------- -USART - Universal Asynchronous Receiver-Transmitter --------------------------------------------------------------------------- -*/ - -/* Universal Synchronous/Asynchronous Receiver/Transmitter */ -typedef struct USART_struct -{ - register8_t DATA; /* Data Register */ - register8_t STATUS; /* Status Register */ - register8_t reserved_0x02; - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t CTRLC; /* Control Register C */ - register8_t BAUDCTRLA; /* Baud Rate Control Register A */ - register8_t BAUDCTRLB; /* Baud Rate Control Register B */ -} USART_t; - -/* Receive Complete Interrupt level */ -typedef enum USART_RXCINTLVL_enum -{ - USART_RXCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ - USART_RXCINTLVL_LO_gc = (0x01<<4), /* Low Level */ - USART_RXCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ - USART_RXCINTLVL_HI_gc = (0x03<<4), /* High Level */ -} USART_RXCINTLVL_t; - -/* Transmit Complete Interrupt level */ -typedef enum USART_TXCINTLVL_enum -{ - USART_TXCINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ - USART_TXCINTLVL_LO_gc = (0x01<<2), /* Low Level */ - USART_TXCINTLVL_MED_gc = (0x02<<2), /* Medium Level */ - USART_TXCINTLVL_HI_gc = (0x03<<2), /* High Level */ -} USART_TXCINTLVL_t; - -/* Data Register Empty Interrupt level */ -typedef enum USART_DREINTLVL_enum -{ - USART_DREINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - USART_DREINTLVL_LO_gc = (0x01<<0), /* Low Level */ - USART_DREINTLVL_MED_gc = (0x02<<0), /* Medium Level */ - USART_DREINTLVL_HI_gc = (0x03<<0), /* High Level */ -} USART_DREINTLVL_t; - -/* Character Size */ -typedef enum USART_CHSIZE_enum -{ - USART_CHSIZE_5BIT_gc = (0x00<<0), /* Character size: 5 bit */ - USART_CHSIZE_6BIT_gc = (0x01<<0), /* Character size: 6 bit */ - USART_CHSIZE_7BIT_gc = (0x02<<0), /* Character size: 7 bit */ - USART_CHSIZE_8BIT_gc = (0x03<<0), /* Character size: 8 bit */ - USART_CHSIZE_9BIT_gc = (0x07<<0), /* Character size: 9 bit */ -} USART_CHSIZE_t; - -/* Communication Mode */ -typedef enum USART_CMODE_enum -{ - USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6), /* Asynchronous Mode */ - USART_CMODE_SYNCHRONOUS_gc = (0x01<<6), /* Synchronous Mode */ - USART_CMODE_IRDA_gc = (0x02<<6), /* IrDA Mode */ - USART_CMODE_MSPI_gc = (0x03<<6), /* Master SPI Mode */ -} USART_CMODE_t; - -/* Parity Mode */ -typedef enum USART_PMODE_enum -{ - USART_PMODE_DISABLED_gc = (0x00<<4), /* No Parity */ - USART_PMODE_EVEN_gc = (0x02<<4), /* Even Parity */ - USART_PMODE_ODD_gc = (0x03<<4), /* Odd Parity */ -} USART_PMODE_t; - - -/* --------------------------------------------------------------------------- -SPI - Serial Peripheral Interface --------------------------------------------------------------------------- -*/ - -/* Serial Peripheral Interface */ -typedef struct SPI_struct -{ - register8_t CTRL; /* Control Register */ - register8_t INTCTRL; /* Interrupt Control Register */ - register8_t STATUS; /* Status Register */ - register8_t DATA; /* Data Register */ -} SPI_t; - -/* SPI Mode */ -typedef enum SPI_MODE_enum -{ - SPI_MODE_0_gc = (0x00<<2), /* SPI Mode 0 */ - SPI_MODE_1_gc = (0x01<<2), /* SPI Mode 1 */ - SPI_MODE_2_gc = (0x02<<2), /* SPI Mode 2 */ - SPI_MODE_3_gc = (0x03<<2), /* SPI Mode 3 */ -} SPI_MODE_t; - -/* Prescaler setting */ -typedef enum SPI_PRESCALER_enum -{ - SPI_PRESCALER_DIV4_gc = (0x00<<0), /* System Clock / 4 */ - SPI_PRESCALER_DIV16_gc = (0x01<<0), /* System Clock / 16 */ - SPI_PRESCALER_DIV64_gc = (0x02<<0), /* System Clock / 64 */ - SPI_PRESCALER_DIV128_gc = (0x03<<0), /* System Clock / 128 */ -} SPI_PRESCALER_t; - -/* Interrupt level */ -typedef enum SPI_INTLVL_enum -{ - SPI_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - SPI_INTLVL_LO_gc = (0x01<<0), /* Low Level */ - SPI_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ - SPI_INTLVL_HI_gc = (0x03<<0), /* High Level */ -} SPI_INTLVL_t; - - -/* --------------------------------------------------------------------------- -IRCOM - IR Communication Module --------------------------------------------------------------------------- -*/ - -/* IR Communication Module */ -typedef struct IRCOM_struct -{ - register8_t CTRL; /* Control Register */ - register8_t TXPLCTRL; /* IrDA Transmitter Pulse Length Control Register */ - register8_t RXPLCTRL; /* IrDA Receiver Pulse Length Control Register */ -} IRCOM_t; - -/* Event channel selection */ -typedef enum IRDA_EVSEL_enum -{ - IRDA_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ - IRDA_EVSEL_0_gc = (0x08<<0), /* Event Channel 0 */ - IRDA_EVSEL_1_gc = (0x09<<0), /* Event Channel 1 */ - IRDA_EVSEL_2_gc = (0x0A<<0), /* Event Channel 2 */ - IRDA_EVSEL_3_gc = (0x0B<<0), /* Event Channel 3 */ -} IRDA_EVSEL_t; - - -/* --------------------------------------------------------------------------- -FUSE - Fuses and Lockbits --------------------------------------------------------------------------- -*/ - -/* Fuses */ -typedef struct NVM_FUSES_struct -{ - register8_t reserved_0x00; - register8_t FUSEBYTE1; /* Watchdog Configuration */ - register8_t FUSEBYTE2; /* Reset Configuration */ - register8_t reserved_0x03; - register8_t FUSEBYTE4; /* Start-up Configuration */ - register8_t FUSEBYTE5; /* EESAVE and BOD Level */ -} NVM_FUSES_t; - -/* Boot Loader Section Reset Vector */ -typedef enum BOOTRST_enum -{ - BOOTRST_BOOTLDR_gc = (0x00<<6), /* Boot Loader Reset */ - BOOTRST_APPLICATION_gc = (0x01<<6), /* Application Reset */ -} BOOTRST_t; - -/* Timer Oscillator pin location */ -typedef enum TOSCSEL_enum -{ - TOSCSEL_ALTERNATE_gc = (0x00<<5), /* TOSC1 / TOSC2 on separate pins */ - TOSCSEL_XTAL_gc = (0x01<<5), /* TOSC1 / TOSC2 shared with XTAL1 / XTAL2 */ -} TOSCSEL_t; - -/* BOD operation */ -typedef enum BOD_enum -{ - BOD_SAMPLED_gc = (0x01<<0), /* BOD enabled in sampled mode */ - BOD_CONTINUOUS_gc = (0x02<<0), /* BOD enabled continuously */ - BOD_DISABLED_gc = (0x03<<0), /* BOD Disabled */ -} BOD_t; - -/* BOD operation */ -typedef enum BODACT_enum -{ - BODACT_SAMPLED_gc = (0x01<<4), /* BOD enabled in sampled mode */ - BODACT_CONTINUOUS_gc = (0x02<<4), /* BOD enabled continuously */ - BODACT_DISABLED_gc = (0x03<<4), /* BOD Disabled */ -} BODACT_t; - -/* Watchdog (Window) Timeout Period */ -typedef enum WD_enum -{ - WD_8CLK_gc = (0x00<<4), /* 8 cycles (8ms @ 3.3V) */ - WD_16CLK_gc = (0x01<<4), /* 16 cycles (16ms @ 3.3V) */ - WD_32CLK_gc = (0x02<<4), /* 32 cycles (32ms @ 3.3V) */ - WD_64CLK_gc = (0x03<<4), /* 64 cycles (64ms @ 3.3V) */ - WD_128CLK_gc = (0x04<<4), /* 128 cycles (0.125s @ 3.3V) */ - WD_256CLK_gc = (0x05<<4), /* 256 cycles (0.25s @ 3.3V) */ - WD_512CLK_gc = (0x06<<4), /* 512 cycles (0.5s @ 3.3V) */ - WD_1KCLK_gc = (0x07<<4), /* 1K cycles (1s @ 3.3V) */ - WD_2KCLK_gc = (0x08<<4), /* 2K cycles (2s @ 3.3V) */ - WD_4KCLK_gc = (0x09<<4), /* 4K cycles (4s @ 3.3V) */ - WD_8KCLK_gc = (0x0A<<4), /* 8K cycles (8s @ 3.3V) */ -} WD_t; - -/* Watchdog (Window) Timeout Period */ -typedef enum WDP_enum -{ - WDP_8CLK_gc = (0x00<<0), /* 8 cycles (8ms @ 3.3V) */ - WDP_16CLK_gc = (0x01<<0), /* 16 cycles (16ms @ 3.3V) */ - WDP_32CLK_gc = (0x02<<0), /* 32 cycles (32ms @ 3.3V) */ - WDP_64CLK_gc = (0x03<<0), /* 64 cycles (64ms @ 3.3V) */ - WDP_128CLK_gc = (0x04<<0), /* 128 cycles (0.125s @ 3.3V) */ - WDP_256CLK_gc = (0x05<<0), /* 256 cycles (0.25s @ 3.3V) */ - WDP_512CLK_gc = (0x06<<0), /* 512 cycles (0.5s @ 3.3V) */ - WDP_1KCLK_gc = (0x07<<0), /* 1K cycles (1s @ 3.3V) */ - WDP_2KCLK_gc = (0x08<<0), /* 2K cycles (2s @ 3.3V) */ - WDP_4KCLK_gc = (0x09<<0), /* 4K cycles (4s @ 3.3V) */ - WDP_8KCLK_gc = (0x0A<<0), /* 8K cycles (8s @ 3.3V) */ -} WDP_t; - -/* Start-up Time */ -typedef enum SUT_enum -{ - SUT_0MS_gc = (0x03<<2), /* 0 ms */ - SUT_4MS_gc = (0x01<<2), /* 4 ms */ - SUT_64MS_gc = (0x00<<2), /* 64 ms */ -} SUT_t; - -/* Brownout Detection Voltage Level */ -typedef enum BODLVL_enum -{ - BODLVL_1V6_gc = (0x07<<0), /* 1.6 V */ - BODLVL_1V8_gc = (0x06<<0), /* 1.8 V */ - BODLVL_2V0_gc = (0x05<<0), /* 2.0 V */ - BODLVL_2V2_gc = (0x04<<0), /* 2.2 V */ - BODLVL_2V4_gc = (0x03<<0), /* 2.4 V */ - BODLVL_2V6_gc = (0x02<<0), /* 2.6 V */ - BODLVL_2V8_gc = (0x01<<0), /* 2.8 V */ - BODLVL_3V0_gc = (0x00<<0), /* 3.0 V */ -} BODLVL_t; - - -/* --------------------------------------------------------------------------- -LOCKBIT - Fuses and Lockbits --------------------------------------------------------------------------- -*/ - -/* Lock Bits */ -typedef struct NVM_LOCKBITS_struct -{ - register8_t LOCK_BITS; /* Lock Bits (Changed from LOCKBITS to avoid avr-libc collision) */ -} NVM_LOCKBITS_t; - -/* Boot lock bits - boot setcion */ -typedef enum FUSE_BLBB_enum -{ - FUSE_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ - FUSE_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ - FUSE_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ - FUSE_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ -} FUSE_BLBB_t; - -/* Boot lock bits - application section */ -typedef enum FUSE_BLBA_enum -{ - FUSE_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ - FUSE_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ - FUSE_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ - FUSE_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ -} FUSE_BLBA_t; - -/* Boot lock bits - application table section */ -typedef enum FUSE_BLBAT_enum -{ - FUSE_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ - FUSE_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ - FUSE_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ - FUSE_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ -} FUSE_BLBAT_t; - -/* Lock bits */ -typedef enum FUSE_LB_enum -{ - FUSE_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ - FUSE_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ - FUSE_LB_NOLOCK_gc = (0x03<<0), /* No locks */ -} FUSE_LB_t; - - -/* --------------------------------------------------------------------------- -SIGROW - Signature Row --------------------------------------------------------------------------- -*/ - -/* Production Signatures */ -typedef struct NVM_PROD_SIGNATURES_struct -{ - register8_t RCOSC2M; /* RCOSC 2 MHz Calibration Value B */ - register8_t RCOSC2MA; /* RCOSC 2 MHz Calibration Value A */ - register8_t RCOSC32K; /* RCOSC 32.768 kHz Calibration Value */ - register8_t RCOSC32M; /* RCOSC 32 MHz Calibration Value B */ - register8_t RCOSC32MA; /* RCOSC 32 MHz Calibration Value A */ - register8_t reserved_0x05; - register8_t reserved_0x06; - register8_t reserved_0x07; - register8_t LOTNUM0; /* Lot Number Byte 0, ASCII */ - register8_t LOTNUM1; /* Lot Number Byte 1, ASCII */ - register8_t LOTNUM2; /* Lot Number Byte 2, ASCII */ - register8_t LOTNUM3; /* Lot Number Byte 3, ASCII */ - register8_t LOTNUM4; /* Lot Number Byte 4, ASCII */ - register8_t LOTNUM5; /* Lot Number Byte 5, ASCII */ - register8_t reserved_0x0E; - register8_t reserved_0x0F; - register8_t WAFNUM; /* Wafer Number */ - register8_t reserved_0x11; - register8_t COORDX0; /* Wafer Coordinate X Byte 0 */ - register8_t COORDX1; /* Wafer Coordinate X Byte 1 */ - register8_t COORDY0; /* Wafer Coordinate Y Byte 0 */ - register8_t COORDY1; /* Wafer Coordinate Y Byte 1 */ - register8_t reserved_0x16; - register8_t reserved_0x17; - register8_t reserved_0x18; - register8_t reserved_0x19; - register8_t USBCAL0; /* USB Calibration Byte 0 */ - register8_t USBCAL1; /* USB Calibration Byte 1 */ - register8_t USBRCOSC; /* USB RCOSC Calibration Value B */ - register8_t USBRCOSCA; /* USB RCOSC Calibration Value A */ - register8_t reserved_0x1E; - register8_t reserved_0x1F; - register8_t ADCACAL0; /* ADCA Calibration Byte 0 */ - register8_t ADCACAL1; /* ADCA Calibration Byte 1 */ - register8_t reserved_0x22; - register8_t reserved_0x23; - register8_t reserved_0x24; - register8_t reserved_0x25; - register8_t reserved_0x26; - register8_t reserved_0x27; - register8_t reserved_0x28; - register8_t reserved_0x29; - register8_t reserved_0x2A; - register8_t reserved_0x2B; - register8_t reserved_0x2C; - register8_t reserved_0x2D; - register8_t TEMPSENSE0; /* Temperature Sensor Calibration Byte 0 */ - register8_t TEMPSENSE1; /* Temperature Sensor Calibration Byte 1 */ - register8_t reserved_0x30; - register8_t reserved_0x31; - register8_t reserved_0x32; - register8_t reserved_0x33; - register8_t reserved_0x34; - register8_t reserved_0x35; - register8_t reserved_0x36; - register8_t reserved_0x37; - register8_t reserved_0x38; - register8_t reserved_0x39; - register8_t reserved_0x3A; - register8_t reserved_0x3B; - register8_t reserved_0x3C; - register8_t reserved_0x3D; - register8_t reserved_0x3E; - register8_t reserved_0x3F; -} NVM_PROD_SIGNATURES_t; - -/* -========================================================================== -IO Module Instances. Mapped to memory. -========================================================================== -*/ - -#define VPORT0 (*(VPORT_t *) 0x0010) /* Virtual Port */ -#define VPORT1 (*(VPORT_t *) 0x0014) /* Virtual Port */ -#define VPORT2 (*(VPORT_t *) 0x0018) /* Virtual Port */ -#define VPORT3 (*(VPORT_t *) 0x001C) /* Virtual Port */ -#define OCD (*(OCD_t *) 0x002E) /* On-Chip Debug System */ -#define CLK (*(CLK_t *) 0x0040) /* Clock System */ -#define SLEEP (*(SLEEP_t *) 0x0048) /* Sleep Controller */ -#define OSC (*(OSC_t *) 0x0050) /* Oscillator */ -#define DFLLRC32M (*(DFLL_t *) 0x0060) /* DFLL */ -#define DFLLRC2M (*(DFLL_t *) 0x0068) /* DFLL */ -#define PR (*(PR_t *) 0x0070) /* Power Reduction */ -#define RST (*(RST_t *) 0x0078) /* Reset */ -#define WDT (*(WDT_t *) 0x0080) /* Watch-Dog Timer */ -#define MCU (*(MCU_t *) 0x0090) /* MCU Control */ -#define PMIC (*(PMIC_t *) 0x00A0) /* Programmable Multi-level Interrupt Controller */ -#define PORTCFG (*(PORTCFG_t *) 0x00B0) /* I/O port Configuration */ -#define CRC (*(CRC_t *) 0x00D0) /* Cyclic Redundancy Checker */ -#define EVSYS (*(EVSYS_t *) 0x0180) /* Event System */ -#define NVM (*(NVM_t *) 0x01C0) /* Non-volatile Memory Controller */ -#define ADCA (*(ADC_t *) 0x0200) /* Analog-to-Digital Converter */ -#define ACA (*(AC_t *) 0x0380) /* Analog Comparator */ -#define RTC (*(RTC_t *) 0x0400) /* Real-Time Counter */ -#define TWIC (*(TWI_t *) 0x0480) /* Two-Wire Interface */ -#define TWIE (*(TWI_t *) 0x04A0) /* Two-Wire Interface */ -#define PORTA (*(PORT_t *) 0x0600) /* I/O Ports */ -#define PORTB (*(PORT_t *) 0x0620) /* I/O Ports */ -#define PORTC (*(PORT_t *) 0x0640) /* I/O Ports */ -#define PORTD (*(PORT_t *) 0x0660) /* I/O Ports */ -#define PORTE (*(PORT_t *) 0x0680) /* I/O Ports */ -#define PORTF (*(PORT_t *) 0x06A0) /* I/O Ports */ -#define PORTR (*(PORT_t *) 0x07E0) /* I/O Ports */ -#define TCC0 (*(TC0_t *) 0x0800) /* 16-bit Timer/Counter 0 */ -#define TCC2 (*(TC2_t *) 0x0800) /* 16-bit Timer/Counter type 2 */ -#define TCC1 (*(TC1_t *) 0x0840) /* 16-bit Timer/Counter 1 */ -#define AWEXC (*(AWEX_t *) 0x0880) /* Advanced Waveform Extension */ -#define HIRESC (*(HIRES_t *) 0x0890) /* High-Resolution Extension */ -#define USARTC0 (*(USART_t *) 0x08A0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ -#define SPIC (*(SPI_t *) 0x08C0) /* Serial Peripheral Interface */ -#define IRCOM (*(IRCOM_t *) 0x08F8) /* IR Communication Module */ -#define TCD0 (*(TC0_t *) 0x0900) /* 16-bit Timer/Counter 0 */ -#define TCD2 (*(TC2_t *) 0x0900) /* 16-bit Timer/Counter type 2 */ -#define USARTD0 (*(USART_t *) 0x09A0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ -#define SPID (*(SPI_t *) 0x09C0) /* Serial Peripheral Interface */ -#define TCE0 (*(TC0_t *) 0x0A00) /* 16-bit Timer/Counter 0 */ -#define TCE2 (*(TC2_t *) 0x0A00) /* 16-bit Timer/Counter type 2 */ -#define USARTE0 (*(USART_t *) 0x0AA0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ -#define TCF0 (*(TC0_t *) 0x0B00) /* 16-bit Timer/Counter 0 */ -#define TCF2 (*(TC2_t *) 0x0B00) /* 16-bit Timer/Counter type 2 */ -#define USARTF0 (*(USART_t *) 0x0BA0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ - - -#endif /* !defined (__ASSEMBLER__) */ - - -/* ========== Flattened fully qualified IO register names ========== */ - -/* GPIO - General Purpose IO Registers */ -#define GPIO_GPIOR0 _SFR_MEM8(0x0000) -#define GPIO_GPIOR1 _SFR_MEM8(0x0001) -#define GPIO_GPIOR2 _SFR_MEM8(0x0002) -#define GPIO_GPIOR3 _SFR_MEM8(0x0003) - -/* Deprecated */ -#define GPIO_GPIO0 _SFR_MEM8(0x0000) -#define GPIO_GPIO1 _SFR_MEM8(0x0001) -#define GPIO_GPIO2 _SFR_MEM8(0x0002) -#define GPIO_GPIO3 _SFR_MEM8(0x0003) - -/* NVM_FUSES - Fuses */ -#define FUSE_FUSEBYTE1 _SFR_MEM8(0x0001) -#define FUSE_FUSEBYTE2 _SFR_MEM8(0x0002) -#define FUSE_FUSEBYTE4 _SFR_MEM8(0x0004) -#define FUSE_FUSEBYTE5 _SFR_MEM8(0x0005) - -/* NVM_LOCKBITS - Lock Bits */ -#define LOCKBIT_LOCKBITS _SFR_MEM8(0x0000) - -/* NVM_PROD_SIGNATURES - Production Signatures */ -#define PRODSIGNATURES_RCOSC2M _SFR_MEM8(0x0000) -#define PRODSIGNATURES_RCOSC2MA _SFR_MEM8(0x0001) -#define PRODSIGNATURES_RCOSC32K _SFR_MEM8(0x0002) -#define PRODSIGNATURES_RCOSC32M _SFR_MEM8(0x0003) -#define PRODSIGNATURES_RCOSC32MA _SFR_MEM8(0x0004) -#define PRODSIGNATURES_LOTNUM0 _SFR_MEM8(0x0008) -#define PRODSIGNATURES_LOTNUM1 _SFR_MEM8(0x0009) -#define PRODSIGNATURES_LOTNUM2 _SFR_MEM8(0x000A) -#define PRODSIGNATURES_LOTNUM3 _SFR_MEM8(0x000B) -#define PRODSIGNATURES_LOTNUM4 _SFR_MEM8(0x000C) -#define PRODSIGNATURES_LOTNUM5 _SFR_MEM8(0x000D) -#define PRODSIGNATURES_WAFNUM _SFR_MEM8(0x0010) -#define PRODSIGNATURES_COORDX0 _SFR_MEM8(0x0012) -#define PRODSIGNATURES_COORDX1 _SFR_MEM8(0x0013) -#define PRODSIGNATURES_COORDY0 _SFR_MEM8(0x0014) -#define PRODSIGNATURES_COORDY1 _SFR_MEM8(0x0015) -#define PRODSIGNATURES_USBCAL0 _SFR_MEM8(0x001A) -#define PRODSIGNATURES_USBCAL1 _SFR_MEM8(0x001B) -#define PRODSIGNATURES_USBRCOSC _SFR_MEM8(0x001C) -#define PRODSIGNATURES_USBRCOSCA _SFR_MEM8(0x001D) -#define PRODSIGNATURES_ADCACAL0 _SFR_MEM8(0x0020) -#define PRODSIGNATURES_ADCACAL1 _SFR_MEM8(0x0021) -#define PRODSIGNATURES_TEMPSENSE0 _SFR_MEM8(0x002E) -#define PRODSIGNATURES_TEMPSENSE1 _SFR_MEM8(0x002F) - -/* VPORT - Virtual Port */ -#define VPORT0_DIR _SFR_MEM8(0x0010) -#define VPORT0_OUT _SFR_MEM8(0x0011) -#define VPORT0_IN _SFR_MEM8(0x0012) -#define VPORT0_INTFLAGS _SFR_MEM8(0x0013) - -/* VPORT - Virtual Port */ -#define VPORT1_DIR _SFR_MEM8(0x0014) -#define VPORT1_OUT _SFR_MEM8(0x0015) -#define VPORT1_IN _SFR_MEM8(0x0016) -#define VPORT1_INTFLAGS _SFR_MEM8(0x0017) - -/* VPORT - Virtual Port */ -#define VPORT2_DIR _SFR_MEM8(0x0018) -#define VPORT2_OUT _SFR_MEM8(0x0019) -#define VPORT2_IN _SFR_MEM8(0x001A) -#define VPORT2_INTFLAGS _SFR_MEM8(0x001B) - -/* VPORT - Virtual Port */ -#define VPORT3_DIR _SFR_MEM8(0x001C) -#define VPORT3_OUT _SFR_MEM8(0x001D) -#define VPORT3_IN _SFR_MEM8(0x001E) -#define VPORT3_INTFLAGS _SFR_MEM8(0x001F) - -/* OCD - On-Chip Debug System */ -#define OCD_OCDR0 _SFR_MEM8(0x002E) -#define OCD_OCDR1 _SFR_MEM8(0x002F) - -/* CPU - CPU registers */ -#define CPU_CCP _SFR_MEM8(0x0034) -#define CPU_RAMPD _SFR_MEM8(0x0038) -#define CPU_RAMPX _SFR_MEM8(0x0039) -#define CPU_RAMPY _SFR_MEM8(0x003A) -#define CPU_RAMPZ _SFR_MEM8(0x003B) -#define CPU_EIND _SFR_MEM8(0x003C) -#define CPU_SPL _SFR_MEM8(0x003D) -#define CPU_SPH _SFR_MEM8(0x003E) -#define CPU_SREG _SFR_MEM8(0x003F) - -/* CLK - Clock System */ -#define CLK_CTRL _SFR_MEM8(0x0040) -#define CLK_PSCTRL _SFR_MEM8(0x0041) -#define CLK_LOCK _SFR_MEM8(0x0042) -#define CLK_RTCCTRL _SFR_MEM8(0x0043) - -/* SLEEP - Sleep Controller */ -#define SLEEP_CTRL _SFR_MEM8(0x0048) - -/* OSC - Oscillator */ -#define OSC_CTRL _SFR_MEM8(0x0050) -#define OSC_STATUS _SFR_MEM8(0x0051) -#define OSC_XOSCCTRL _SFR_MEM8(0x0052) -#define OSC_XOSCFAIL _SFR_MEM8(0x0053) -#define OSC_RC32KCAL _SFR_MEM8(0x0054) -#define OSC_PLLCTRL _SFR_MEM8(0x0055) -#define OSC_DFLLCTRL _SFR_MEM8(0x0056) - -/* DFLL - DFLL */ -#define DFLLRC32M_CTRL _SFR_MEM8(0x0060) -#define DFLLRC32M_CALA _SFR_MEM8(0x0062) -#define DFLLRC32M_CALB _SFR_MEM8(0x0063) -#define DFLLRC32M_COMP0 _SFR_MEM8(0x0064) -#define DFLLRC32M_COMP1 _SFR_MEM8(0x0065) -#define DFLLRC32M_COMP2 _SFR_MEM8(0x0066) - -/* DFLL - DFLL */ -#define DFLLRC2M_CTRL _SFR_MEM8(0x0068) -#define DFLLRC2M_CALA _SFR_MEM8(0x006A) -#define DFLLRC2M_CALB _SFR_MEM8(0x006B) -#define DFLLRC2M_COMP0 _SFR_MEM8(0x006C) -#define DFLLRC2M_COMP1 _SFR_MEM8(0x006D) -#define DFLLRC2M_COMP2 _SFR_MEM8(0x006E) - -/* PR - Power Reduction */ -#define PR_PRGEN _SFR_MEM8(0x0070) -#define PR_PRPA _SFR_MEM8(0x0071) -#define PR_PRPC _SFR_MEM8(0x0073) -#define PR_PRPD _SFR_MEM8(0x0074) -#define PR_PRPE _SFR_MEM8(0x0075) -#define PR_PRPF _SFR_MEM8(0x0076) - -/* RST - Reset */ -#define RST_STATUS _SFR_MEM8(0x0078) -#define RST_CTRL _SFR_MEM8(0x0079) - -/* WDT - Watch-Dog Timer */ -#define WDT_CTRL _SFR_MEM8(0x0080) -#define WDT_WINCTRL _SFR_MEM8(0x0081) -#define WDT_STATUS _SFR_MEM8(0x0082) - -/* MCU - MCU Control */ -#define MCU_DEVID0 _SFR_MEM8(0x0090) -#define MCU_DEVID1 _SFR_MEM8(0x0091) -#define MCU_DEVID2 _SFR_MEM8(0x0092) -#define MCU_REVID _SFR_MEM8(0x0093) -#define MCU_ANAINIT _SFR_MEM8(0x0097) -#define MCU_EVSYSLOCK _SFR_MEM8(0x0098) -#define MCU_AWEXLOCK _SFR_MEM8(0x0099) - -/* PMIC - Programmable Multi-level Interrupt Controller */ -#define PMIC_STATUS _SFR_MEM8(0x00A0) -#define PMIC_INTPRI _SFR_MEM8(0x00A1) -#define PMIC_CTRL _SFR_MEM8(0x00A2) - -/* PORTCFG - I/O port Configuration */ -#define PORTCFG_MPCMASK _SFR_MEM8(0x00B0) -#define PORTCFG_VPCTRLA _SFR_MEM8(0x00B2) -#define PORTCFG_VPCTRLB _SFR_MEM8(0x00B3) -#define PORTCFG_CLKEVOUT _SFR_MEM8(0x00B4) -#define PORTCFG_EBIOUT _SFR_MEM8(0x00B5) -#define PORTCFG_EVOUTSEL _SFR_MEM8(0x00B6) - -/* CRC - Cyclic Redundancy Checker */ -#define CRC_CTRL _SFR_MEM8(0x00D0) -#define CRC_STATUS _SFR_MEM8(0x00D1) -#define CRC_DATAIN _SFR_MEM8(0x00D3) -#define CRC_CHECKSUM0 _SFR_MEM8(0x00D4) -#define CRC_CHECKSUM1 _SFR_MEM8(0x00D5) -#define CRC_CHECKSUM2 _SFR_MEM8(0x00D6) -#define CRC_CHECKSUM3 _SFR_MEM8(0x00D7) - -/* EVSYS - Event System */ -#define EVSYS_CH0MUX _SFR_MEM8(0x0180) -#define EVSYS_CH1MUX _SFR_MEM8(0x0181) -#define EVSYS_CH2MUX _SFR_MEM8(0x0182) -#define EVSYS_CH3MUX _SFR_MEM8(0x0183) -#define EVSYS_CH0CTRL _SFR_MEM8(0x0188) -#define EVSYS_CH1CTRL _SFR_MEM8(0x0189) -#define EVSYS_CH2CTRL _SFR_MEM8(0x018A) -#define EVSYS_CH3CTRL _SFR_MEM8(0x018B) -#define EVSYS_STROBE _SFR_MEM8(0x0190) -#define EVSYS_DATA _SFR_MEM8(0x0191) - -/* NVM - Non-volatile Memory Controller */ -#define NVM_ADDR0 _SFR_MEM8(0x01C0) -#define NVM_ADDR1 _SFR_MEM8(0x01C1) -#define NVM_ADDR2 _SFR_MEM8(0x01C2) -#define NVM_DATA0 _SFR_MEM8(0x01C4) -#define NVM_DATA1 _SFR_MEM8(0x01C5) -#define NVM_DATA2 _SFR_MEM8(0x01C6) -#define NVM_CMD _SFR_MEM8(0x01CA) -#define NVM_CTRLA _SFR_MEM8(0x01CB) -#define NVM_CTRLB _SFR_MEM8(0x01CC) -#define NVM_INTCTRL _SFR_MEM8(0x01CD) -#define NVM_STATUS _SFR_MEM8(0x01CF) -#define NVM_LOCKBITS _SFR_MEM8(0x01D0) - -/* ADC - Analog-to-Digital Converter */ -#define ADCA_CTRLA _SFR_MEM8(0x0200) -#define ADCA_CTRLB _SFR_MEM8(0x0201) -#define ADCA_REFCTRL _SFR_MEM8(0x0202) -#define ADCA_EVCTRL _SFR_MEM8(0x0203) -#define ADCA_PRESCALER _SFR_MEM8(0x0204) -#define ADCA_INTFLAGS _SFR_MEM8(0x0206) -#define ADCA_TEMP _SFR_MEM8(0x0207) -#define ADCA_SAMPCTRL _SFR_MEM8(0x0208) -#define ADCA_CAL _SFR_MEM16(0x020C) -#define ADCA_CH0RES _SFR_MEM16(0x0210) -#define ADCA_CMP _SFR_MEM16(0x0218) -#define ADCA_CH0_CTRL _SFR_MEM8(0x0220) -#define ADCA_CH0_MUXCTRL _SFR_MEM8(0x0221) -#define ADCA_CH0_INTCTRL _SFR_MEM8(0x0222) -#define ADCA_CH0_INTFLAGS _SFR_MEM8(0x0223) -#define ADCA_CH0_RES _SFR_MEM16(0x0224) -#define ADCA_CH0_SCAN _SFR_MEM8(0x0226) - -/* AC - Analog Comparator */ -#define ACA_AC0CTRL _SFR_MEM8(0x0380) -#define ACA_AC1CTRL _SFR_MEM8(0x0381) -#define ACA_AC0MUXCTRL _SFR_MEM8(0x0382) -#define ACA_AC1MUXCTRL _SFR_MEM8(0x0383) -#define ACA_CTRLA _SFR_MEM8(0x0384) -#define ACA_CTRLB _SFR_MEM8(0x0385) -#define ACA_WINCTRL _SFR_MEM8(0x0386) -#define ACA_STATUS _SFR_MEM8(0x0387) - -/* RTC - Real-Time Counter */ -#define RTC_CTRL _SFR_MEM8(0x0400) -#define RTC_STATUS _SFR_MEM8(0x0401) -#define RTC_INTCTRL _SFR_MEM8(0x0402) -#define RTC_INTFLAGS _SFR_MEM8(0x0403) -#define RTC_TEMP _SFR_MEM8(0x0404) -#define RTC_CNT _SFR_MEM16(0x0408) -#define RTC_PER _SFR_MEM16(0x040A) -#define RTC_COMP _SFR_MEM16(0x040C) - -/* TWI - Two-Wire Interface */ -#define TWIC_CTRL _SFR_MEM8(0x0480) -#define TWIC_MASTER_CTRLA _SFR_MEM8(0x0481) -#define TWIC_MASTER_CTRLB _SFR_MEM8(0x0482) -#define TWIC_MASTER_CTRLC _SFR_MEM8(0x0483) -#define TWIC_MASTER_STATUS _SFR_MEM8(0x0484) -#define TWIC_MASTER_BAUD _SFR_MEM8(0x0485) -#define TWIC_MASTER_ADDR _SFR_MEM8(0x0486) -#define TWIC_MASTER_DATA _SFR_MEM8(0x0487) -#define TWIC_SLAVE_CTRLA _SFR_MEM8(0x0488) -#define TWIC_SLAVE_CTRLB _SFR_MEM8(0x0489) -#define TWIC_SLAVE_STATUS _SFR_MEM8(0x048A) -#define TWIC_SLAVE_ADDR _SFR_MEM8(0x048B) -#define TWIC_SLAVE_DATA _SFR_MEM8(0x048C) -#define TWIC_SLAVE_ADDRMASK _SFR_MEM8(0x048D) - -/* TWI - Two-Wire Interface */ -#define TWIE_CTRL _SFR_MEM8(0x04A0) -#define TWIE_MASTER_CTRLA _SFR_MEM8(0x04A1) -#define TWIE_MASTER_CTRLB _SFR_MEM8(0x04A2) -#define TWIE_MASTER_CTRLC _SFR_MEM8(0x04A3) -#define TWIE_MASTER_STATUS _SFR_MEM8(0x04A4) -#define TWIE_MASTER_BAUD _SFR_MEM8(0x04A5) -#define TWIE_MASTER_ADDR _SFR_MEM8(0x04A6) -#define TWIE_MASTER_DATA _SFR_MEM8(0x04A7) -#define TWIE_SLAVE_CTRLA _SFR_MEM8(0x04A8) -#define TWIE_SLAVE_CTRLB _SFR_MEM8(0x04A9) -#define TWIE_SLAVE_STATUS _SFR_MEM8(0x04AA) -#define TWIE_SLAVE_ADDR _SFR_MEM8(0x04AB) -#define TWIE_SLAVE_DATA _SFR_MEM8(0x04AC) -#define TWIE_SLAVE_ADDRMASK _SFR_MEM8(0x04AD) - -/* PORT - I/O Ports */ -#define PORTA_DIR _SFR_MEM8(0x0600) -#define PORTA_DIRSET _SFR_MEM8(0x0601) -#define PORTA_DIRCLR _SFR_MEM8(0x0602) -#define PORTA_DIRTGL _SFR_MEM8(0x0603) -#define PORTA_OUT _SFR_MEM8(0x0604) -#define PORTA_OUTSET _SFR_MEM8(0x0605) -#define PORTA_OUTCLR _SFR_MEM8(0x0606) -#define PORTA_OUTTGL _SFR_MEM8(0x0607) -#define PORTA_IN _SFR_MEM8(0x0608) -#define PORTA_INTCTRL _SFR_MEM8(0x0609) -#define PORTA_INT0MASK _SFR_MEM8(0x060A) -#define PORTA_INT1MASK _SFR_MEM8(0x060B) -#define PORTA_INTFLAGS _SFR_MEM8(0x060C) -#define PORTA_REMAP _SFR_MEM8(0x060E) -#define PORTA_PIN0CTRL _SFR_MEM8(0x0610) -#define PORTA_PIN1CTRL _SFR_MEM8(0x0611) -#define PORTA_PIN2CTRL _SFR_MEM8(0x0612) -#define PORTA_PIN3CTRL _SFR_MEM8(0x0613) -#define PORTA_PIN4CTRL _SFR_MEM8(0x0614) -#define PORTA_PIN5CTRL _SFR_MEM8(0x0615) -#define PORTA_PIN6CTRL _SFR_MEM8(0x0616) -#define PORTA_PIN7CTRL _SFR_MEM8(0x0617) - -/* PORT - I/O Ports */ -#define PORTB_DIR _SFR_MEM8(0x0620) -#define PORTB_DIRSET _SFR_MEM8(0x0621) -#define PORTB_DIRCLR _SFR_MEM8(0x0622) -#define PORTB_DIRTGL _SFR_MEM8(0x0623) -#define PORTB_OUT _SFR_MEM8(0x0624) -#define PORTB_OUTSET _SFR_MEM8(0x0625) -#define PORTB_OUTCLR _SFR_MEM8(0x0626) -#define PORTB_OUTTGL _SFR_MEM8(0x0627) -#define PORTB_IN _SFR_MEM8(0x0628) -#define PORTB_INTCTRL _SFR_MEM8(0x0629) -#define PORTB_INT0MASK _SFR_MEM8(0x062A) -#define PORTB_INT1MASK _SFR_MEM8(0x062B) -#define PORTB_INTFLAGS _SFR_MEM8(0x062C) -#define PORTB_REMAP _SFR_MEM8(0x062E) -#define PORTB_PIN0CTRL _SFR_MEM8(0x0630) -#define PORTB_PIN1CTRL _SFR_MEM8(0x0631) -#define PORTB_PIN2CTRL _SFR_MEM8(0x0632) -#define PORTB_PIN3CTRL _SFR_MEM8(0x0633) -#define PORTB_PIN4CTRL _SFR_MEM8(0x0634) -#define PORTB_PIN5CTRL _SFR_MEM8(0x0635) -#define PORTB_PIN6CTRL _SFR_MEM8(0x0636) -#define PORTB_PIN7CTRL _SFR_MEM8(0x0637) - -/* PORT - I/O Ports */ -#define PORTC_DIR _SFR_MEM8(0x0640) -#define PORTC_DIRSET _SFR_MEM8(0x0641) -#define PORTC_DIRCLR _SFR_MEM8(0x0642) -#define PORTC_DIRTGL _SFR_MEM8(0x0643) -#define PORTC_OUT _SFR_MEM8(0x0644) -#define PORTC_OUTSET _SFR_MEM8(0x0645) -#define PORTC_OUTCLR _SFR_MEM8(0x0646) -#define PORTC_OUTTGL _SFR_MEM8(0x0647) -#define PORTC_IN _SFR_MEM8(0x0648) -#define PORTC_INTCTRL _SFR_MEM8(0x0649) -#define PORTC_INT0MASK _SFR_MEM8(0x064A) -#define PORTC_INT1MASK _SFR_MEM8(0x064B) -#define PORTC_INTFLAGS _SFR_MEM8(0x064C) -#define PORTC_REMAP _SFR_MEM8(0x064E) -#define PORTC_PIN0CTRL _SFR_MEM8(0x0650) -#define PORTC_PIN1CTRL _SFR_MEM8(0x0651) -#define PORTC_PIN2CTRL _SFR_MEM8(0x0652) -#define PORTC_PIN3CTRL _SFR_MEM8(0x0653) -#define PORTC_PIN4CTRL _SFR_MEM8(0x0654) -#define PORTC_PIN5CTRL _SFR_MEM8(0x0655) -#define PORTC_PIN6CTRL _SFR_MEM8(0x0656) -#define PORTC_PIN7CTRL _SFR_MEM8(0x0657) - -/* PORT - I/O Ports */ -#define PORTD_DIR _SFR_MEM8(0x0660) -#define PORTD_DIRSET _SFR_MEM8(0x0661) -#define PORTD_DIRCLR _SFR_MEM8(0x0662) -#define PORTD_DIRTGL _SFR_MEM8(0x0663) -#define PORTD_OUT _SFR_MEM8(0x0664) -#define PORTD_OUTSET _SFR_MEM8(0x0665) -#define PORTD_OUTCLR _SFR_MEM8(0x0666) -#define PORTD_OUTTGL _SFR_MEM8(0x0667) -#define PORTD_IN _SFR_MEM8(0x0668) -#define PORTD_INTCTRL _SFR_MEM8(0x0669) -#define PORTD_INT0MASK _SFR_MEM8(0x066A) -#define PORTD_INT1MASK _SFR_MEM8(0x066B) -#define PORTD_INTFLAGS _SFR_MEM8(0x066C) -#define PORTD_REMAP _SFR_MEM8(0x066E) -#define PORTD_PIN0CTRL _SFR_MEM8(0x0670) -#define PORTD_PIN1CTRL _SFR_MEM8(0x0671) -#define PORTD_PIN2CTRL _SFR_MEM8(0x0672) -#define PORTD_PIN3CTRL _SFR_MEM8(0x0673) -#define PORTD_PIN4CTRL _SFR_MEM8(0x0674) -#define PORTD_PIN5CTRL _SFR_MEM8(0x0675) -#define PORTD_PIN6CTRL _SFR_MEM8(0x0676) -#define PORTD_PIN7CTRL _SFR_MEM8(0x0677) - -/* PORT - I/O Ports */ -#define PORTE_DIR _SFR_MEM8(0x0680) -#define PORTE_DIRSET _SFR_MEM8(0x0681) -#define PORTE_DIRCLR _SFR_MEM8(0x0682) -#define PORTE_DIRTGL _SFR_MEM8(0x0683) -#define PORTE_OUT _SFR_MEM8(0x0684) -#define PORTE_OUTSET _SFR_MEM8(0x0685) -#define PORTE_OUTCLR _SFR_MEM8(0x0686) -#define PORTE_OUTTGL _SFR_MEM8(0x0687) -#define PORTE_IN _SFR_MEM8(0x0688) -#define PORTE_INTCTRL _SFR_MEM8(0x0689) -#define PORTE_INT0MASK _SFR_MEM8(0x068A) -#define PORTE_INT1MASK _SFR_MEM8(0x068B) -#define PORTE_INTFLAGS _SFR_MEM8(0x068C) -#define PORTE_REMAP _SFR_MEM8(0x068E) -#define PORTE_PIN0CTRL _SFR_MEM8(0x0690) -#define PORTE_PIN1CTRL _SFR_MEM8(0x0691) -#define PORTE_PIN2CTRL _SFR_MEM8(0x0692) -#define PORTE_PIN3CTRL _SFR_MEM8(0x0693) -#define PORTE_PIN4CTRL _SFR_MEM8(0x0694) -#define PORTE_PIN5CTRL _SFR_MEM8(0x0695) -#define PORTE_PIN6CTRL _SFR_MEM8(0x0696) -#define PORTE_PIN7CTRL _SFR_MEM8(0x0697) - -/* PORT - I/O Ports */ -#define PORTF_DIR _SFR_MEM8(0x06A0) -#define PORTF_DIRSET _SFR_MEM8(0x06A1) -#define PORTF_DIRCLR _SFR_MEM8(0x06A2) -#define PORTF_DIRTGL _SFR_MEM8(0x06A3) -#define PORTF_OUT _SFR_MEM8(0x06A4) -#define PORTF_OUTSET _SFR_MEM8(0x06A5) -#define PORTF_OUTCLR _SFR_MEM8(0x06A6) -#define PORTF_OUTTGL _SFR_MEM8(0x06A7) -#define PORTF_IN _SFR_MEM8(0x06A8) -#define PORTF_INTCTRL _SFR_MEM8(0x06A9) -#define PORTF_INT0MASK _SFR_MEM8(0x06AA) -#define PORTF_INT1MASK _SFR_MEM8(0x06AB) -#define PORTF_INTFLAGS _SFR_MEM8(0x06AC) -#define PORTF_REMAP _SFR_MEM8(0x06AE) -#define PORTF_PIN0CTRL _SFR_MEM8(0x06B0) -#define PORTF_PIN1CTRL _SFR_MEM8(0x06B1) -#define PORTF_PIN2CTRL _SFR_MEM8(0x06B2) -#define PORTF_PIN3CTRL _SFR_MEM8(0x06B3) -#define PORTF_PIN4CTRL _SFR_MEM8(0x06B4) -#define PORTF_PIN5CTRL _SFR_MEM8(0x06B5) -#define PORTF_PIN6CTRL _SFR_MEM8(0x06B6) -#define PORTF_PIN7CTRL _SFR_MEM8(0x06B7) - -/* PORT - I/O Ports */ -#define PORTR_DIR _SFR_MEM8(0x07E0) -#define PORTR_DIRSET _SFR_MEM8(0x07E1) -#define PORTR_DIRCLR _SFR_MEM8(0x07E2) -#define PORTR_DIRTGL _SFR_MEM8(0x07E3) -#define PORTR_OUT _SFR_MEM8(0x07E4) -#define PORTR_OUTSET _SFR_MEM8(0x07E5) -#define PORTR_OUTCLR _SFR_MEM8(0x07E6) -#define PORTR_OUTTGL _SFR_MEM8(0x07E7) -#define PORTR_IN _SFR_MEM8(0x07E8) -#define PORTR_INTCTRL _SFR_MEM8(0x07E9) -#define PORTR_INT0MASK _SFR_MEM8(0x07EA) -#define PORTR_INT1MASK _SFR_MEM8(0x07EB) -#define PORTR_INTFLAGS _SFR_MEM8(0x07EC) -#define PORTR_REMAP _SFR_MEM8(0x07EE) -#define PORTR_PIN0CTRL _SFR_MEM8(0x07F0) -#define PORTR_PIN1CTRL _SFR_MEM8(0x07F1) -#define PORTR_PIN2CTRL _SFR_MEM8(0x07F2) -#define PORTR_PIN3CTRL _SFR_MEM8(0x07F3) -#define PORTR_PIN4CTRL _SFR_MEM8(0x07F4) -#define PORTR_PIN5CTRL _SFR_MEM8(0x07F5) -#define PORTR_PIN6CTRL _SFR_MEM8(0x07F6) -#define PORTR_PIN7CTRL _SFR_MEM8(0x07F7) - -/* TC0 - 16-bit Timer/Counter 0 */ -#define TCC0_CTRLA _SFR_MEM8(0x0800) -#define TCC0_CTRLB _SFR_MEM8(0x0801) -#define TCC0_CTRLC _SFR_MEM8(0x0802) -#define TCC0_CTRLD _SFR_MEM8(0x0803) -#define TCC0_CTRLE _SFR_MEM8(0x0804) -#define TCC0_INTCTRLA _SFR_MEM8(0x0806) -#define TCC0_INTCTRLB _SFR_MEM8(0x0807) -#define TCC0_CTRLFCLR _SFR_MEM8(0x0808) -#define TCC0_CTRLFSET _SFR_MEM8(0x0809) -#define TCC0_CTRLGCLR _SFR_MEM8(0x080A) -#define TCC0_CTRLGSET _SFR_MEM8(0x080B) -#define TCC0_INTFLAGS _SFR_MEM8(0x080C) -#define TCC0_TEMP _SFR_MEM8(0x080F) -#define TCC0_CNT _SFR_MEM16(0x0820) -#define TCC0_PER _SFR_MEM16(0x0826) -#define TCC0_CCA _SFR_MEM16(0x0828) -#define TCC0_CCB _SFR_MEM16(0x082A) -#define TCC0_CCC _SFR_MEM16(0x082C) -#define TCC0_CCD _SFR_MEM16(0x082E) -#define TCC0_PERBUF _SFR_MEM16(0x0836) -#define TCC0_CCABUF _SFR_MEM16(0x0838) -#define TCC0_CCBBUF _SFR_MEM16(0x083A) -#define TCC0_CCCBUF _SFR_MEM16(0x083C) -#define TCC0_CCDBUF _SFR_MEM16(0x083E) - -/* TC2 - 16-bit Timer/Counter type 2 */ -#define TCC2_CTRLA _SFR_MEM8(0x0800) -#define TCC2_CTRLB _SFR_MEM8(0x0801) -#define TCC2_CTRLC _SFR_MEM8(0x0802) -#define TCC2_CTRLE _SFR_MEM8(0x0804) -#define TCC2_INTCTRLA _SFR_MEM8(0x0806) -#define TCC2_INTCTRLB _SFR_MEM8(0x0807) -#define TCC2_CTRLF _SFR_MEM8(0x0809) -#define TCC2_INTFLAGS _SFR_MEM8(0x080C) -#define TCC2_LCNT _SFR_MEM8(0x0820) -#define TCC2_HCNT _SFR_MEM8(0x0821) -#define TCC2_LPER _SFR_MEM8(0x0826) -#define TCC2_HPER _SFR_MEM8(0x0827) -#define TCC2_LCMPA _SFR_MEM8(0x0828) -#define TCC2_HCMPA _SFR_MEM8(0x0829) -#define TCC2_LCMPB _SFR_MEM8(0x082A) -#define TCC2_HCMPB _SFR_MEM8(0x082B) -#define TCC2_LCMPC _SFR_MEM8(0x082C) -#define TCC2_HCMPC _SFR_MEM8(0x082D) -#define TCC2_LCMPD _SFR_MEM8(0x082E) -#define TCC2_HCMPD _SFR_MEM8(0x082F) - -/* TC1 - 16-bit Timer/Counter 1 */ -#define TCC1_CTRLA _SFR_MEM8(0x0840) -#define TCC1_CTRLB _SFR_MEM8(0x0841) -#define TCC1_CTRLC _SFR_MEM8(0x0842) -#define TCC1_CTRLD _SFR_MEM8(0x0843) -#define TCC1_CTRLE _SFR_MEM8(0x0844) -#define TCC1_INTCTRLA _SFR_MEM8(0x0846) -#define TCC1_INTCTRLB _SFR_MEM8(0x0847) -#define TCC1_CTRLFCLR _SFR_MEM8(0x0848) -#define TCC1_CTRLFSET _SFR_MEM8(0x0849) -#define TCC1_CTRLGCLR _SFR_MEM8(0x084A) -#define TCC1_CTRLGSET _SFR_MEM8(0x084B) -#define TCC1_INTFLAGS _SFR_MEM8(0x084C) -#define TCC1_TEMP _SFR_MEM8(0x084F) -#define TCC1_CNT _SFR_MEM16(0x0860) -#define TCC1_PER _SFR_MEM16(0x0866) -#define TCC1_CCA _SFR_MEM16(0x0868) -#define TCC1_CCB _SFR_MEM16(0x086A) -#define TCC1_PERBUF _SFR_MEM16(0x0876) -#define TCC1_CCABUF _SFR_MEM16(0x0878) -#define TCC1_CCBBUF _SFR_MEM16(0x087A) - -/* AWEX - Advanced Waveform Extension */ -#define AWEXC_CTRL _SFR_MEM8(0x0880) -#define AWEXC_FDEMASK _SFR_MEM8(0x0882) -#define AWEXC_FDCTRL _SFR_MEM8(0x0883) -#define AWEXC_STATUS _SFR_MEM8(0x0884) -#define AWEXC_STATUSSET _SFR_MEM8(0x0885) -#define AWEXC_DTBOTH _SFR_MEM8(0x0886) -#define AWEXC_DTBOTHBUF _SFR_MEM8(0x0887) -#define AWEXC_DTLS _SFR_MEM8(0x0888) -#define AWEXC_DTHS _SFR_MEM8(0x0889) -#define AWEXC_DTLSBUF _SFR_MEM8(0x088A) -#define AWEXC_DTHSBUF _SFR_MEM8(0x088B) -#define AWEXC_OUTOVEN _SFR_MEM8(0x088C) - -/* HIRES - High-Resolution Extension */ -#define HIRESC_CTRLA _SFR_MEM8(0x0890) - -/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ -#define USARTC0_DATA _SFR_MEM8(0x08A0) -#define USARTC0_STATUS _SFR_MEM8(0x08A1) -#define USARTC0_CTRLA _SFR_MEM8(0x08A3) -#define USARTC0_CTRLB _SFR_MEM8(0x08A4) -#define USARTC0_CTRLC _SFR_MEM8(0x08A5) -#define USARTC0_BAUDCTRLA _SFR_MEM8(0x08A6) -#define USARTC0_BAUDCTRLB _SFR_MEM8(0x08A7) - -/* SPI - Serial Peripheral Interface */ -#define SPIC_CTRL _SFR_MEM8(0x08C0) -#define SPIC_INTCTRL _SFR_MEM8(0x08C1) -#define SPIC_STATUS _SFR_MEM8(0x08C2) -#define SPIC_DATA _SFR_MEM8(0x08C3) - -/* IRCOM - IR Communication Module */ -#define IRCOM_CTRL _SFR_MEM8(0x08F8) -#define IRCOM_TXPLCTRL _SFR_MEM8(0x08F9) -#define IRCOM_RXPLCTRL _SFR_MEM8(0x08FA) - -/* TC0 - 16-bit Timer/Counter 0 */ -#define TCD0_CTRLA _SFR_MEM8(0x0900) -#define TCD0_CTRLB _SFR_MEM8(0x0901) -#define TCD0_CTRLC _SFR_MEM8(0x0902) -#define TCD0_CTRLD _SFR_MEM8(0x0903) -#define TCD0_CTRLE _SFR_MEM8(0x0904) -#define TCD0_INTCTRLA _SFR_MEM8(0x0906) -#define TCD0_INTCTRLB _SFR_MEM8(0x0907) -#define TCD0_CTRLFCLR _SFR_MEM8(0x0908) -#define TCD0_CTRLFSET _SFR_MEM8(0x0909) -#define TCD0_CTRLGCLR _SFR_MEM8(0x090A) -#define TCD0_CTRLGSET _SFR_MEM8(0x090B) -#define TCD0_INTFLAGS _SFR_MEM8(0x090C) -#define TCD0_TEMP _SFR_MEM8(0x090F) -#define TCD0_CNT _SFR_MEM16(0x0920) -#define TCD0_PER _SFR_MEM16(0x0926) -#define TCD0_CCA _SFR_MEM16(0x0928) -#define TCD0_CCB _SFR_MEM16(0x092A) -#define TCD0_CCC _SFR_MEM16(0x092C) -#define TCD0_CCD _SFR_MEM16(0x092E) -#define TCD0_PERBUF _SFR_MEM16(0x0936) -#define TCD0_CCABUF _SFR_MEM16(0x0938) -#define TCD0_CCBBUF _SFR_MEM16(0x093A) -#define TCD0_CCCBUF _SFR_MEM16(0x093C) -#define TCD0_CCDBUF _SFR_MEM16(0x093E) - -/* TC2 - 16-bit Timer/Counter type 2 */ -#define TCD2_CTRLA _SFR_MEM8(0x0900) -#define TCD2_CTRLB _SFR_MEM8(0x0901) -#define TCD2_CTRLC _SFR_MEM8(0x0902) -#define TCD2_CTRLE _SFR_MEM8(0x0904) -#define TCD2_INTCTRLA _SFR_MEM8(0x0906) -#define TCD2_INTCTRLB _SFR_MEM8(0x0907) -#define TCD2_CTRLF _SFR_MEM8(0x0909) -#define TCD2_INTFLAGS _SFR_MEM8(0x090C) -#define TCD2_LCNT _SFR_MEM8(0x0920) -#define TCD2_HCNT _SFR_MEM8(0x0921) -#define TCD2_LPER _SFR_MEM8(0x0926) -#define TCD2_HPER _SFR_MEM8(0x0927) -#define TCD2_LCMPA _SFR_MEM8(0x0928) -#define TCD2_HCMPA _SFR_MEM8(0x0929) -#define TCD2_LCMPB _SFR_MEM8(0x092A) -#define TCD2_HCMPB _SFR_MEM8(0x092B) -#define TCD2_LCMPC _SFR_MEM8(0x092C) -#define TCD2_HCMPC _SFR_MEM8(0x092D) -#define TCD2_LCMPD _SFR_MEM8(0x092E) -#define TCD2_HCMPD _SFR_MEM8(0x092F) - -/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ -#define USARTD0_DATA _SFR_MEM8(0x09A0) -#define USARTD0_STATUS _SFR_MEM8(0x09A1) -#define USARTD0_CTRLA _SFR_MEM8(0x09A3) -#define USARTD0_CTRLB _SFR_MEM8(0x09A4) -#define USARTD0_CTRLC _SFR_MEM8(0x09A5) -#define USARTD0_BAUDCTRLA _SFR_MEM8(0x09A6) -#define USARTD0_BAUDCTRLB _SFR_MEM8(0x09A7) - -/* SPI - Serial Peripheral Interface */ -#define SPID_CTRL _SFR_MEM8(0x09C0) -#define SPID_INTCTRL _SFR_MEM8(0x09C1) -#define SPID_STATUS _SFR_MEM8(0x09C2) -#define SPID_DATA _SFR_MEM8(0x09C3) - -/* TC0 - 16-bit Timer/Counter 0 */ -#define TCE0_CTRLA _SFR_MEM8(0x0A00) -#define TCE0_CTRLB _SFR_MEM8(0x0A01) -#define TCE0_CTRLC _SFR_MEM8(0x0A02) -#define TCE0_CTRLD _SFR_MEM8(0x0A03) -#define TCE0_CTRLE _SFR_MEM8(0x0A04) -#define TCE0_INTCTRLA _SFR_MEM8(0x0A06) -#define TCE0_INTCTRLB _SFR_MEM8(0x0A07) -#define TCE0_CTRLFCLR _SFR_MEM8(0x0A08) -#define TCE0_CTRLFSET _SFR_MEM8(0x0A09) -#define TCE0_CTRLGCLR _SFR_MEM8(0x0A0A) -#define TCE0_CTRLGSET _SFR_MEM8(0x0A0B) -#define TCE0_INTFLAGS _SFR_MEM8(0x0A0C) -#define TCE0_TEMP _SFR_MEM8(0x0A0F) -#define TCE0_CNT _SFR_MEM16(0x0A20) -#define TCE0_PER _SFR_MEM16(0x0A26) -#define TCE0_CCA _SFR_MEM16(0x0A28) -#define TCE0_CCB _SFR_MEM16(0x0A2A) -#define TCE0_CCC _SFR_MEM16(0x0A2C) -#define TCE0_CCD _SFR_MEM16(0x0A2E) -#define TCE0_PERBUF _SFR_MEM16(0x0A36) -#define TCE0_CCABUF _SFR_MEM16(0x0A38) -#define TCE0_CCBBUF _SFR_MEM16(0x0A3A) -#define TCE0_CCCBUF _SFR_MEM16(0x0A3C) -#define TCE0_CCDBUF _SFR_MEM16(0x0A3E) - -/* TC2 - 16-bit Timer/Counter type 2 */ -#define TCE2_CTRLA _SFR_MEM8(0x0A00) -#define TCE2_CTRLB _SFR_MEM8(0x0A01) -#define TCE2_CTRLC _SFR_MEM8(0x0A02) -#define TCE2_CTRLE _SFR_MEM8(0x0A04) -#define TCE2_INTCTRLA _SFR_MEM8(0x0A06) -#define TCE2_INTCTRLB _SFR_MEM8(0x0A07) -#define TCE2_CTRLF _SFR_MEM8(0x0A09) -#define TCE2_INTFLAGS _SFR_MEM8(0x0A0C) -#define TCE2_LCNT _SFR_MEM8(0x0A20) -#define TCE2_HCNT _SFR_MEM8(0x0A21) -#define TCE2_LPER _SFR_MEM8(0x0A26) -#define TCE2_HPER _SFR_MEM8(0x0A27) -#define TCE2_LCMPA _SFR_MEM8(0x0A28) -#define TCE2_HCMPA _SFR_MEM8(0x0A29) -#define TCE2_LCMPB _SFR_MEM8(0x0A2A) -#define TCE2_HCMPB _SFR_MEM8(0x0A2B) -#define TCE2_LCMPC _SFR_MEM8(0x0A2C) -#define TCE2_HCMPC _SFR_MEM8(0x0A2D) -#define TCE2_LCMPD _SFR_MEM8(0x0A2E) -#define TCE2_HCMPD _SFR_MEM8(0x0A2F) - -/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ -#define USARTE0_DATA _SFR_MEM8(0x0AA0) -#define USARTE0_STATUS _SFR_MEM8(0x0AA1) -#define USARTE0_CTRLA _SFR_MEM8(0x0AA3) -#define USARTE0_CTRLB _SFR_MEM8(0x0AA4) -#define USARTE0_CTRLC _SFR_MEM8(0x0AA5) -#define USARTE0_BAUDCTRLA _SFR_MEM8(0x0AA6) -#define USARTE0_BAUDCTRLB _SFR_MEM8(0x0AA7) - -/* TC0 - 16-bit Timer/Counter 0 */ -#define TCF0_CTRLA _SFR_MEM8(0x0B00) -#define TCF0_CTRLB _SFR_MEM8(0x0B01) -#define TCF0_CTRLC _SFR_MEM8(0x0B02) -#define TCF0_CTRLD _SFR_MEM8(0x0B03) -#define TCF0_CTRLE _SFR_MEM8(0x0B04) -#define TCF0_INTCTRLA _SFR_MEM8(0x0B06) -#define TCF0_INTCTRLB _SFR_MEM8(0x0B07) -#define TCF0_CTRLFCLR _SFR_MEM8(0x0B08) -#define TCF0_CTRLFSET _SFR_MEM8(0x0B09) -#define TCF0_CTRLGCLR _SFR_MEM8(0x0B0A) -#define TCF0_CTRLGSET _SFR_MEM8(0x0B0B) -#define TCF0_INTFLAGS _SFR_MEM8(0x0B0C) -#define TCF0_TEMP _SFR_MEM8(0x0B0F) -#define TCF0_CNT _SFR_MEM16(0x0B20) -#define TCF0_PER _SFR_MEM16(0x0B26) -#define TCF0_CCA _SFR_MEM16(0x0B28) -#define TCF0_CCB _SFR_MEM16(0x0B2A) -#define TCF0_CCC _SFR_MEM16(0x0B2C) -#define TCF0_CCD _SFR_MEM16(0x0B2E) -#define TCF0_PERBUF _SFR_MEM16(0x0B36) -#define TCF0_CCABUF _SFR_MEM16(0x0B38) -#define TCF0_CCBBUF _SFR_MEM16(0x0B3A) -#define TCF0_CCCBUF _SFR_MEM16(0x0B3C) -#define TCF0_CCDBUF _SFR_MEM16(0x0B3E) - -/* TC2 - 16-bit Timer/Counter type 2 */ -#define TCF2_CTRLA _SFR_MEM8(0x0B00) -#define TCF2_CTRLB _SFR_MEM8(0x0B01) -#define TCF2_CTRLC _SFR_MEM8(0x0B02) -#define TCF2_CTRLE _SFR_MEM8(0x0B04) -#define TCF2_INTCTRLA _SFR_MEM8(0x0B06) -#define TCF2_INTCTRLB _SFR_MEM8(0x0B07) -#define TCF2_CTRLF _SFR_MEM8(0x0B09) -#define TCF2_INTFLAGS _SFR_MEM8(0x0B0C) -#define TCF2_LCNT _SFR_MEM8(0x0B20) -#define TCF2_HCNT _SFR_MEM8(0x0B21) -#define TCF2_LPER _SFR_MEM8(0x0B26) -#define TCF2_HPER _SFR_MEM8(0x0B27) -#define TCF2_LCMPA _SFR_MEM8(0x0B28) -#define TCF2_HCMPA _SFR_MEM8(0x0B29) -#define TCF2_LCMPB _SFR_MEM8(0x0B2A) -#define TCF2_HCMPB _SFR_MEM8(0x0B2B) -#define TCF2_LCMPC _SFR_MEM8(0x0B2C) -#define TCF2_HCMPC _SFR_MEM8(0x0B2D) -#define TCF2_LCMPD _SFR_MEM8(0x0B2E) -#define TCF2_HCMPD _SFR_MEM8(0x0B2F) - -/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ -#define USARTF0_DATA _SFR_MEM8(0x0BA0) -#define USARTF0_STATUS _SFR_MEM8(0x0BA1) -#define USARTF0_CTRLA _SFR_MEM8(0x0BA3) -#define USARTF0_CTRLB _SFR_MEM8(0x0BA4) -#define USARTF0_CTRLC _SFR_MEM8(0x0BA5) -#define USARTF0_BAUDCTRLA _SFR_MEM8(0x0BA6) -#define USARTF0_BAUDCTRLB _SFR_MEM8(0x0BA7) - - - -/*================== Bitfield Definitions ================== */ - -/* VPORT - Virtual Ports */ -/* VPORT.INTFLAGS bit masks and bit positions */ -#define VPORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ -#define VPORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ - -#define VPORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ -#define VPORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ - -/* XOCD - On-Chip Debug System */ -/* OCD.OCDR0 bit masks and bit positions */ -#define OCD_OCDRD_gm 0xFF /* OCDR Dirty group mask. */ -#define OCD_OCDRD_gp 0 /* OCDR Dirty group position. */ -#define OCD_OCDRD0_bm (1<<0) /* OCDR Dirty bit 0 mask. */ -#define OCD_OCDRD0_bp 0 /* OCDR Dirty bit 0 position. */ -#define OCD_OCDRD1_bm (1<<1) /* OCDR Dirty bit 1 mask. */ -#define OCD_OCDRD1_bp 1 /* OCDR Dirty bit 1 position. */ -#define OCD_OCDRD2_bm (1<<2) /* OCDR Dirty bit 2 mask. */ -#define OCD_OCDRD2_bp 2 /* OCDR Dirty bit 2 position. */ -#define OCD_OCDRD3_bm (1<<3) /* OCDR Dirty bit 3 mask. */ -#define OCD_OCDRD3_bp 3 /* OCDR Dirty bit 3 position. */ -#define OCD_OCDRD4_bm (1<<4) /* OCDR Dirty bit 4 mask. */ -#define OCD_OCDRD4_bp 4 /* OCDR Dirty bit 4 position. */ -#define OCD_OCDRD5_bm (1<<5) /* OCDR Dirty bit 5 mask. */ -#define OCD_OCDRD5_bp 5 /* OCDR Dirty bit 5 position. */ -#define OCD_OCDRD6_bm (1<<6) /* OCDR Dirty bit 6 mask. */ -#define OCD_OCDRD6_bp 6 /* OCDR Dirty bit 6 position. */ -#define OCD_OCDRD7_bm (1<<7) /* OCDR Dirty bit 7 mask. */ -#define OCD_OCDRD7_bp 7 /* OCDR Dirty bit 7 position. */ - -/* OCD.OCDR1 bit masks and bit positions */ -/* OCD_OCDRD Predefined. */ -/* OCD_OCDRD Predefined. */ - -/* CPU - CPU */ -/* CPU.CCP bit masks and bit positions */ -#define CPU_CCP_gm 0xFF /* CCP signature group mask. */ -#define CPU_CCP_gp 0 /* CCP signature group position. */ -#define CPU_CCP0_bm (1<<0) /* CCP signature bit 0 mask. */ -#define CPU_CCP0_bp 0 /* CCP signature bit 0 position. */ -#define CPU_CCP1_bm (1<<1) /* CCP signature bit 1 mask. */ -#define CPU_CCP1_bp 1 /* CCP signature bit 1 position. */ -#define CPU_CCP2_bm (1<<2) /* CCP signature bit 2 mask. */ -#define CPU_CCP2_bp 2 /* CCP signature bit 2 position. */ -#define CPU_CCP3_bm (1<<3) /* CCP signature bit 3 mask. */ -#define CPU_CCP3_bp 3 /* CCP signature bit 3 position. */ -#define CPU_CCP4_bm (1<<4) /* CCP signature bit 4 mask. */ -#define CPU_CCP4_bp 4 /* CCP signature bit 4 position. */ -#define CPU_CCP5_bm (1<<5) /* CCP signature bit 5 mask. */ -#define CPU_CCP5_bp 5 /* CCP signature bit 5 position. */ -#define CPU_CCP6_bm (1<<6) /* CCP signature bit 6 mask. */ -#define CPU_CCP6_bp 6 /* CCP signature bit 6 position. */ -#define CPU_CCP7_bm (1<<7) /* CCP signature bit 7 mask. */ -#define CPU_CCP7_bp 7 /* CCP signature bit 7 position. */ - -/* CPU.SREG bit masks and bit positions */ -#define CPU_I_bm 0x80 /* Global Interrupt Enable Flag bit mask. */ -#define CPU_I_bp 7 /* Global Interrupt Enable Flag bit position. */ - -#define CPU_T_bm 0x40 /* Transfer Bit bit mask. */ -#define CPU_T_bp 6 /* Transfer Bit bit position. */ - -#define CPU_H_bm 0x20 /* Half Carry Flag bit mask. */ -#define CPU_H_bp 5 /* Half Carry Flag bit position. */ - -#define CPU_S_bm 0x10 /* N Exclusive Or V Flag bit mask. */ -#define CPU_S_bp 4 /* N Exclusive Or V Flag bit position. */ - -#define CPU_V_bm 0x08 /* Two's Complement Overflow Flag bit mask. */ -#define CPU_V_bp 3 /* Two's Complement Overflow Flag bit position. */ - -#define CPU_N_bm 0x04 /* Negative Flag bit mask. */ -#define CPU_N_bp 2 /* Negative Flag bit position. */ - -#define CPU_Z_bm 0x02 /* Zero Flag bit mask. */ -#define CPU_Z_bp 1 /* Zero Flag bit position. */ - -#define CPU_C_bm 0x01 /* Carry Flag bit mask. */ -#define CPU_C_bp 0 /* Carry Flag bit position. */ - -/* CLK - Clock System */ -/* CLK.CTRL bit masks and bit positions */ -#define CLK_SCLKSEL_gm 0x07 /* System Clock Selection group mask. */ -#define CLK_SCLKSEL_gp 0 /* System Clock Selection group position. */ -#define CLK_SCLKSEL0_bm (1<<0) /* System Clock Selection bit 0 mask. */ -#define CLK_SCLKSEL0_bp 0 /* System Clock Selection bit 0 position. */ -#define CLK_SCLKSEL1_bm (1<<1) /* System Clock Selection bit 1 mask. */ -#define CLK_SCLKSEL1_bp 1 /* System Clock Selection bit 1 position. */ -#define CLK_SCLKSEL2_bm (1<<2) /* System Clock Selection bit 2 mask. */ -#define CLK_SCLKSEL2_bp 2 /* System Clock Selection bit 2 position. */ - -/* CLK.PSCTRL bit masks and bit positions */ -#define CLK_PSADIV_gm 0x7C /* Prescaler A Division Factor group mask. */ -#define CLK_PSADIV_gp 2 /* Prescaler A Division Factor group position. */ -#define CLK_PSADIV0_bm (1<<2) /* Prescaler A Division Factor bit 0 mask. */ -#define CLK_PSADIV0_bp 2 /* Prescaler A Division Factor bit 0 position. */ -#define CLK_PSADIV1_bm (1<<3) /* Prescaler A Division Factor bit 1 mask. */ -#define CLK_PSADIV1_bp 3 /* Prescaler A Division Factor bit 1 position. */ -#define CLK_PSADIV2_bm (1<<4) /* Prescaler A Division Factor bit 2 mask. */ -#define CLK_PSADIV2_bp 4 /* Prescaler A Division Factor bit 2 position. */ -#define CLK_PSADIV3_bm (1<<5) /* Prescaler A Division Factor bit 3 mask. */ -#define CLK_PSADIV3_bp 5 /* Prescaler A Division Factor bit 3 position. */ -#define CLK_PSADIV4_bm (1<<6) /* Prescaler A Division Factor bit 4 mask. */ -#define CLK_PSADIV4_bp 6 /* Prescaler A Division Factor bit 4 position. */ - -#define CLK_PSBCDIV_gm 0x03 /* Prescaler B and C Division factor group mask. */ -#define CLK_PSBCDIV_gp 0 /* Prescaler B and C Division factor group position. */ -#define CLK_PSBCDIV0_bm (1<<0) /* Prescaler B and C Division factor bit 0 mask. */ -#define CLK_PSBCDIV0_bp 0 /* Prescaler B and C Division factor bit 0 position. */ -#define CLK_PSBCDIV1_bm (1<<1) /* Prescaler B and C Division factor bit 1 mask. */ -#define CLK_PSBCDIV1_bp 1 /* Prescaler B and C Division factor bit 1 position. */ - -/* CLK.LOCK bit masks and bit positions */ -#define CLK_LOCK_bm 0x01 /* Clock System Lock bit mask. */ -#define CLK_LOCK_bp 0 /* Clock System Lock bit position. */ - -/* CLK.RTCCTRL bit masks and bit positions */ -#define CLK_RTCSRC_gm 0x0E /* Clock Source group mask. */ -#define CLK_RTCSRC_gp 1 /* Clock Source group position. */ -#define CLK_RTCSRC0_bm (1<<1) /* Clock Source bit 0 mask. */ -#define CLK_RTCSRC0_bp 1 /* Clock Source bit 0 position. */ -#define CLK_RTCSRC1_bm (1<<2) /* Clock Source bit 1 mask. */ -#define CLK_RTCSRC1_bp 2 /* Clock Source bit 1 position. */ -#define CLK_RTCSRC2_bm (1<<3) /* Clock Source bit 2 mask. */ -#define CLK_RTCSRC2_bp 3 /* Clock Source bit 2 position. */ - -#define CLK_RTCEN_bm 0x01 /* Clock Source Enable bit mask. */ -#define CLK_RTCEN_bp 0 /* Clock Source Enable bit position. */ - -/* PR.PRGEN bit masks and bit positions */ -#define PR_RTC_bm 0x04 /* Real-time Counter bit mask. */ -#define PR_RTC_bp 2 /* Real-time Counter bit position. */ - -#define PR_EVSYS_bm 0x02 /* Event System bit mask. */ -#define PR_EVSYS_bp 1 /* Event System bit position. */ - -/* PR.PRPA bit masks and bit positions */ -#define PR_ADC_bm 0x02 /* Port A ADC bit mask. */ -#define PR_ADC_bp 1 /* Port A ADC bit position. */ - -#define PR_AC_bm 0x01 /* Port A Analog Comparator bit mask. */ -#define PR_AC_bp 0 /* Port A Analog Comparator bit position. */ - -/* PR.PRPC bit masks and bit positions */ -#define PR_TWI_bm 0x40 /* Port C Two-wire Interface bit mask. */ -#define PR_TWI_bp 6 /* Port C Two-wire Interface bit position. */ - -#define PR_USART0_bm 0x10 /* Port C USART0 bit mask. */ -#define PR_USART0_bp 4 /* Port C USART0 bit position. */ - -#define PR_SPI_bm 0x08 /* Port C SPI bit mask. */ -#define PR_SPI_bp 3 /* Port C SPI bit position. */ - -#define PR_HIRES_bm 0x04 /* Port C HIRES bit mask. */ -#define PR_HIRES_bp 2 /* Port C HIRES bit position. */ - -#define PR_TC1_bm 0x02 /* Port C Timer/Counter1 bit mask. */ -#define PR_TC1_bp 1 /* Port C Timer/Counter1 bit position. */ - -#define PR_TC0_bm 0x01 /* Port C Timer/Counter0 bit mask. */ -#define PR_TC0_bp 0 /* Port C Timer/Counter0 bit position. */ - -/* PR.PRPD bit masks and bit positions */ -/* PR_USART0 Predefined. */ -/* PR_USART0 Predefined. */ - -/* PR_SPI Predefined. */ -/* PR_SPI Predefined. */ - -/* PR_TC0 Predefined. */ -/* PR_TC0 Predefined. */ - -/* PR.PRPE bit masks and bit positions */ -/* PR_TWI Predefined. */ -/* PR_TWI Predefined. */ - -/* PR_USART0 Predefined. */ -/* PR_USART0 Predefined. */ - -/* PR_TC0 Predefined. */ -/* PR_TC0 Predefined. */ - -/* PR.PRPF bit masks and bit positions */ -/* PR_USART0 Predefined. */ -/* PR_USART0 Predefined. */ - -/* PR_TC0 Predefined. */ -/* PR_TC0 Predefined. */ - -/* SLEEP - Sleep Controller */ -/* SLEEP.CTRL bit masks and bit positions */ -#define SLEEP_SMODE_gm 0x0E /* Sleep Mode group mask. */ -#define SLEEP_SMODE_gp 1 /* Sleep Mode group position. */ -#define SLEEP_SMODE0_bm (1<<1) /* Sleep Mode bit 0 mask. */ -#define SLEEP_SMODE0_bp 1 /* Sleep Mode bit 0 position. */ -#define SLEEP_SMODE1_bm (1<<2) /* Sleep Mode bit 1 mask. */ -#define SLEEP_SMODE1_bp 2 /* Sleep Mode bit 1 position. */ -#define SLEEP_SMODE2_bm (1<<3) /* Sleep Mode bit 2 mask. */ -#define SLEEP_SMODE2_bp 3 /* Sleep Mode bit 2 position. */ - -#define SLEEP_SEN_bm 0x01 /* Sleep Enable bit mask. */ -#define SLEEP_SEN_bp 0 /* Sleep Enable bit position. */ - -/* OSC - Oscillator */ -/* OSC.CTRL bit masks and bit positions */ -#define OSC_PLLEN_bm 0x10 /* PLL Enable bit mask. */ -#define OSC_PLLEN_bp 4 /* PLL Enable bit position. */ - -#define OSC_XOSCEN_bm 0x08 /* External Oscillator Enable bit mask. */ -#define OSC_XOSCEN_bp 3 /* External Oscillator Enable bit position. */ - -#define OSC_RC32KEN_bm 0x04 /* Internal 32.768 kHz RC Oscillator Enable bit mask. */ -#define OSC_RC32KEN_bp 2 /* Internal 32.768 kHz RC Oscillator Enable bit position. */ - -#define OSC_RC32MEN_bm 0x02 /* Internal 32 MHz RC Oscillator Enable bit mask. */ -#define OSC_RC32MEN_bp 1 /* Internal 32 MHz RC Oscillator Enable bit position. */ - -#define OSC_RC2MEN_bm 0x01 /* Internal 2 MHz RC Oscillator Enable bit mask. */ -#define OSC_RC2MEN_bp 0 /* Internal 2 MHz RC Oscillator Enable bit position. */ - -/* OSC.STATUS bit masks and bit positions */ -#define OSC_PLLRDY_bm 0x10 /* PLL Ready bit mask. */ -#define OSC_PLLRDY_bp 4 /* PLL Ready bit position. */ - -#define OSC_XOSCRDY_bm 0x08 /* External Oscillator Ready bit mask. */ -#define OSC_XOSCRDY_bp 3 /* External Oscillator Ready bit position. */ - -#define OSC_RC32KRDY_bm 0x04 /* Internal 32.768 kHz RC Oscillator Ready bit mask. */ -#define OSC_RC32KRDY_bp 2 /* Internal 32.768 kHz RC Oscillator Ready bit position. */ - -#define OSC_RC32MRDY_bm 0x02 /* Internal 32 MHz RC Oscillator Ready bit mask. */ -#define OSC_RC32MRDY_bp 1 /* Internal 32 MHz RC Oscillator Ready bit position. */ - -#define OSC_RC2MRDY_bm 0x01 /* Internal 2 MHz RC Oscillator Ready bit mask. */ -#define OSC_RC2MRDY_bp 0 /* Internal 2 MHz RC Oscillator Ready bit position. */ - -/* OSC.XOSCCTRL bit masks and bit positions */ -#define OSC_FRQRANGE_gm 0xC0 /* Frequency Range group mask. */ -#define OSC_FRQRANGE_gp 6 /* Frequency Range group position. */ -#define OSC_FRQRANGE0_bm (1<<6) /* Frequency Range bit 0 mask. */ -#define OSC_FRQRANGE0_bp 6 /* Frequency Range bit 0 position. */ -#define OSC_FRQRANGE1_bm (1<<7) /* Frequency Range bit 1 mask. */ -#define OSC_FRQRANGE1_bp 7 /* Frequency Range bit 1 position. */ - -#define OSC_X32KLPM_bm 0x20 /* 32.768 kHz XTAL OSC Low-power Mode bit mask. */ -#define OSC_X32KLPM_bp 5 /* 32.768 kHz XTAL OSC Low-power Mode bit position. */ - -#define OSC_XOSCPWR_bm 0x10 /* 16 MHz Crystal Oscillator High Power mode bit mask. */ -#define OSC_XOSCPWR_bp 4 /* 16 MHz Crystal Oscillator High Power mode bit position. */ - -#define OSC_XOSCSEL_gm 0x0F /* External Oscillator Selection and Startup Time group mask. */ -#define OSC_XOSCSEL_gp 0 /* External Oscillator Selection and Startup Time group position. */ -#define OSC_XOSCSEL0_bm (1<<0) /* External Oscillator Selection and Startup Time bit 0 mask. */ -#define OSC_XOSCSEL0_bp 0 /* External Oscillator Selection and Startup Time bit 0 position. */ -#define OSC_XOSCSEL1_bm (1<<1) /* External Oscillator Selection and Startup Time bit 1 mask. */ -#define OSC_XOSCSEL1_bp 1 /* External Oscillator Selection and Startup Time bit 1 position. */ -#define OSC_XOSCSEL2_bm (1<<2) /* External Oscillator Selection and Startup Time bit 2 mask. */ -#define OSC_XOSCSEL2_bp 2 /* External Oscillator Selection and Startup Time bit 2 position. */ -#define OSC_XOSCSEL3_bm (1<<3) /* External Oscillator Selection and Startup Time bit 3 mask. */ -#define OSC_XOSCSEL3_bp 3 /* External Oscillator Selection and Startup Time bit 3 position. */ - -/* OSC.XOSCFAIL bit masks and bit positions */ -#define OSC_PLLFDIF_bm 0x08 /* PLL Failure Detection Interrupt Flag bit mask. */ -#define OSC_PLLFDIF_bp 3 /* PLL Failure Detection Interrupt Flag bit position. */ - -#define OSC_PLLFDEN_bm 0x04 /* PLL Failure Detection Enable bit mask. */ -#define OSC_PLLFDEN_bp 2 /* PLL Failure Detection Enable bit position. */ - -#define OSC_XOSCFDIF_bm 0x02 /* XOSC Failure Detection Interrupt Flag bit mask. */ -#define OSC_XOSCFDIF_bp 1 /* XOSC Failure Detection Interrupt Flag bit position. */ - -#define OSC_XOSCFDEN_bm 0x01 /* XOSC Failure Detection Enable bit mask. */ -#define OSC_XOSCFDEN_bp 0 /* XOSC Failure Detection Enable bit position. */ - -/* OSC.PLLCTRL bit masks and bit positions */ -#define OSC_PLLSRC_gm 0xC0 /* Clock Source group mask. */ -#define OSC_PLLSRC_gp 6 /* Clock Source group position. */ -#define OSC_PLLSRC0_bm (1<<6) /* Clock Source bit 0 mask. */ -#define OSC_PLLSRC0_bp 6 /* Clock Source bit 0 position. */ -#define OSC_PLLSRC1_bm (1<<7) /* Clock Source bit 1 mask. */ -#define OSC_PLLSRC1_bp 7 /* Clock Source bit 1 position. */ - -#define OSC_PLLDIV_bm 0x20 /* Divide by 2 bit mask. */ -#define OSC_PLLDIV_bp 5 /* Divide by 2 bit position. */ - -#define OSC_PLLFAC_gm 0x1F /* Multiplication Factor group mask. */ -#define OSC_PLLFAC_gp 0 /* Multiplication Factor group position. */ -#define OSC_PLLFAC0_bm (1<<0) /* Multiplication Factor bit 0 mask. */ -#define OSC_PLLFAC0_bp 0 /* Multiplication Factor bit 0 position. */ -#define OSC_PLLFAC1_bm (1<<1) /* Multiplication Factor bit 1 mask. */ -#define OSC_PLLFAC1_bp 1 /* Multiplication Factor bit 1 position. */ -#define OSC_PLLFAC2_bm (1<<2) /* Multiplication Factor bit 2 mask. */ -#define OSC_PLLFAC2_bp 2 /* Multiplication Factor bit 2 position. */ -#define OSC_PLLFAC3_bm (1<<3) /* Multiplication Factor bit 3 mask. */ -#define OSC_PLLFAC3_bp 3 /* Multiplication Factor bit 3 position. */ -#define OSC_PLLFAC4_bm (1<<4) /* Multiplication Factor bit 4 mask. */ -#define OSC_PLLFAC4_bp 4 /* Multiplication Factor bit 4 position. */ - -/* OSC.DFLLCTRL bit masks and bit positions */ -#define OSC_RC32MCREF_gm 0x06 /* 32 MHz DFLL Calibration Reference group mask. */ -#define OSC_RC32MCREF_gp 1 /* 32 MHz DFLL Calibration Reference group position. */ -#define OSC_RC32MCREF0_bm (1<<1) /* 32 MHz DFLL Calibration Reference bit 0 mask. */ -#define OSC_RC32MCREF0_bp 1 /* 32 MHz DFLL Calibration Reference bit 0 position. */ -#define OSC_RC32MCREF1_bm (1<<2) /* 32 MHz DFLL Calibration Reference bit 1 mask. */ -#define OSC_RC32MCREF1_bp 2 /* 32 MHz DFLL Calibration Reference bit 1 position. */ - -#define OSC_RC2MCREF_bm 0x01 /* 2 MHz DFLL Calibration Reference bit mask. */ -#define OSC_RC2MCREF_bp 0 /* 2 MHz DFLL Calibration Reference bit position. */ - -/* DFLL - DFLL */ -/* DFLL.CTRL bit masks and bit positions */ -#define DFLL_ENABLE_bm 0x01 /* DFLL Enable bit mask. */ -#define DFLL_ENABLE_bp 0 /* DFLL Enable bit position. */ - -/* DFLL.CALA bit masks and bit positions */ -#define DFLL_CALL_gm 0x7F /* DFLL Calibration Value A group mask. */ -#define DFLL_CALL_gp 0 /* DFLL Calibration Value A group position. */ -#define DFLL_CALL0_bm (1<<0) /* DFLL Calibration Value A bit 0 mask. */ -#define DFLL_CALL0_bp 0 /* DFLL Calibration Value A bit 0 position. */ -#define DFLL_CALL1_bm (1<<1) /* DFLL Calibration Value A bit 1 mask. */ -#define DFLL_CALL1_bp 1 /* DFLL Calibration Value A bit 1 position. */ -#define DFLL_CALL2_bm (1<<2) /* DFLL Calibration Value A bit 2 mask. */ -#define DFLL_CALL2_bp 2 /* DFLL Calibration Value A bit 2 position. */ -#define DFLL_CALL3_bm (1<<3) /* DFLL Calibration Value A bit 3 mask. */ -#define DFLL_CALL3_bp 3 /* DFLL Calibration Value A bit 3 position. */ -#define DFLL_CALL4_bm (1<<4) /* DFLL Calibration Value A bit 4 mask. */ -#define DFLL_CALL4_bp 4 /* DFLL Calibration Value A bit 4 position. */ -#define DFLL_CALL5_bm (1<<5) /* DFLL Calibration Value A bit 5 mask. */ -#define DFLL_CALL5_bp 5 /* DFLL Calibration Value A bit 5 position. */ -#define DFLL_CALL6_bm (1<<6) /* DFLL Calibration Value A bit 6 mask. */ -#define DFLL_CALL6_bp 6 /* DFLL Calibration Value A bit 6 position. */ - -/* DFLL.CALB bit masks and bit positions */ -#define DFLL_CALH_gm 0x3F /* DFLL Calibration Value B group mask. */ -#define DFLL_CALH_gp 0 /* DFLL Calibration Value B group position. */ -#define DFLL_CALH0_bm (1<<0) /* DFLL Calibration Value B bit 0 mask. */ -#define DFLL_CALH0_bp 0 /* DFLL Calibration Value B bit 0 position. */ -#define DFLL_CALH1_bm (1<<1) /* DFLL Calibration Value B bit 1 mask. */ -#define DFLL_CALH1_bp 1 /* DFLL Calibration Value B bit 1 position. */ -#define DFLL_CALH2_bm (1<<2) /* DFLL Calibration Value B bit 2 mask. */ -#define DFLL_CALH2_bp 2 /* DFLL Calibration Value B bit 2 position. */ -#define DFLL_CALH3_bm (1<<3) /* DFLL Calibration Value B bit 3 mask. */ -#define DFLL_CALH3_bp 3 /* DFLL Calibration Value B bit 3 position. */ -#define DFLL_CALH4_bm (1<<4) /* DFLL Calibration Value B bit 4 mask. */ -#define DFLL_CALH4_bp 4 /* DFLL Calibration Value B bit 4 position. */ -#define DFLL_CALH5_bm (1<<5) /* DFLL Calibration Value B bit 5 mask. */ -#define DFLL_CALH5_bp 5 /* DFLL Calibration Value B bit 5 position. */ - -/* RST - Reset */ -/* RST.STATUS bit masks and bit positions */ -#define RST_SDRF_bm 0x40 /* Spike Detection Reset Flag bit mask. */ -#define RST_SDRF_bp 6 /* Spike Detection Reset Flag bit position. */ - -#define RST_SRF_bm 0x20 /* Software Reset Flag bit mask. */ -#define RST_SRF_bp 5 /* Software Reset Flag bit position. */ - -#define RST_PDIRF_bm 0x10 /* Programming and Debug Interface Interface Reset Flag bit mask. */ -#define RST_PDIRF_bp 4 /* Programming and Debug Interface Interface Reset Flag bit position. */ - -#define RST_WDRF_bm 0x08 /* Watchdog Reset Flag bit mask. */ -#define RST_WDRF_bp 3 /* Watchdog Reset Flag bit position. */ - -#define RST_BORF_bm 0x04 /* Brown-out Reset Flag bit mask. */ -#define RST_BORF_bp 2 /* Brown-out Reset Flag bit position. */ - -#define RST_EXTRF_bm 0x02 /* External Reset Flag bit mask. */ -#define RST_EXTRF_bp 1 /* External Reset Flag bit position. */ - -#define RST_PORF_bm 0x01 /* Power-on Reset Flag bit mask. */ -#define RST_PORF_bp 0 /* Power-on Reset Flag bit position. */ - -/* RST.CTRL bit masks and bit positions */ -#define RST_SWRST_bm 0x01 /* Software Reset bit mask. */ -#define RST_SWRST_bp 0 /* Software Reset bit position. */ - -/* WDT - Watch-Dog Timer */ -/* WDT.CTRL bit masks and bit positions */ -#define WDT_PER_gm 0x3C /* Period group mask. */ -#define WDT_PER_gp 2 /* Period group position. */ -#define WDT_PER0_bm (1<<2) /* Period bit 0 mask. */ -#define WDT_PER0_bp 2 /* Period bit 0 position. */ -#define WDT_PER1_bm (1<<3) /* Period bit 1 mask. */ -#define WDT_PER1_bp 3 /* Period bit 1 position. */ -#define WDT_PER2_bm (1<<4) /* Period bit 2 mask. */ -#define WDT_PER2_bp 4 /* Period bit 2 position. */ -#define WDT_PER3_bm (1<<5) /* Period bit 3 mask. */ -#define WDT_PER3_bp 5 /* Period bit 3 position. */ - -#define WDT_ENABLE_bm 0x02 /* Enable bit mask. */ -#define WDT_ENABLE_bp 1 /* Enable bit position. */ - -#define WDT_CEN_bm 0x01 /* Change Enable bit mask. */ -#define WDT_CEN_bp 0 /* Change Enable bit position. */ - -/* WDT.WINCTRL bit masks and bit positions */ -#define WDT_WPER_gm 0x3C /* Windowed Mode Period group mask. */ -#define WDT_WPER_gp 2 /* Windowed Mode Period group position. */ -#define WDT_WPER0_bm (1<<2) /* Windowed Mode Period bit 0 mask. */ -#define WDT_WPER0_bp 2 /* Windowed Mode Period bit 0 position. */ -#define WDT_WPER1_bm (1<<3) /* Windowed Mode Period bit 1 mask. */ -#define WDT_WPER1_bp 3 /* Windowed Mode Period bit 1 position. */ -#define WDT_WPER2_bm (1<<4) /* Windowed Mode Period bit 2 mask. */ -#define WDT_WPER2_bp 4 /* Windowed Mode Period bit 2 position. */ -#define WDT_WPER3_bm (1<<5) /* Windowed Mode Period bit 3 mask. */ -#define WDT_WPER3_bp 5 /* Windowed Mode Period bit 3 position. */ - -#define WDT_WEN_bm 0x02 /* Windowed Mode Enable bit mask. */ -#define WDT_WEN_bp 1 /* Windowed Mode Enable bit position. */ - -#define WDT_WCEN_bm 0x01 /* Windowed Mode Change Enable bit mask. */ -#define WDT_WCEN_bp 0 /* Windowed Mode Change Enable bit position. */ - -/* WDT.STATUS bit masks and bit positions */ -#define WDT_SYNCBUSY_bm 0x01 /* Syncronization busy bit mask. */ -#define WDT_SYNCBUSY_bp 0 /* Syncronization busy bit position. */ - -/* MCU - MCU Control */ -/* MCU.ANAINIT bit masks and bit positions */ -#define MCU_STARTUPDLYA_gm 0x03 /* Analog startup delay Port A group mask. */ -#define MCU_STARTUPDLYA_gp 0 /* Analog startup delay Port A group position. */ -#define MCU_STARTUPDLYA0_bm (1<<0) /* Analog startup delay Port A bit 0 mask. */ -#define MCU_STARTUPDLYA0_bp 0 /* Analog startup delay Port A bit 0 position. */ -#define MCU_STARTUPDLYA1_bm (1<<1) /* Analog startup delay Port A bit 1 mask. */ -#define MCU_STARTUPDLYA1_bp 1 /* Analog startup delay Port A bit 1 position. */ - -/* MCU.EVSYSLOCK bit masks and bit positions */ -#define MCU_EVSYS0LOCK_bm 0x01 /* Event Channel 0-3 Lock bit mask. */ -#define MCU_EVSYS0LOCK_bp 0 /* Event Channel 0-3 Lock bit position. */ - -/* MCU.AWEXLOCK bit masks and bit positions */ -#define MCU_AWEXCLOCK_bm 0x01 /* AWeX on T/C C0 Lock bit mask. */ -#define MCU_AWEXCLOCK_bp 0 /* AWeX on T/C C0 Lock bit position. */ - -/* PMIC - Programmable Multi-level Interrupt Controller */ -/* PMIC.STATUS bit masks and bit positions */ -#define PMIC_NMIEX_bm 0x80 /* Non-maskable Interrupt Executing bit mask. */ -#define PMIC_NMIEX_bp 7 /* Non-maskable Interrupt Executing bit position. */ - -#define PMIC_HILVLEX_bm 0x04 /* High Level Interrupt Executing bit mask. */ -#define PMIC_HILVLEX_bp 2 /* High Level Interrupt Executing bit position. */ - -#define PMIC_MEDLVLEX_bm 0x02 /* Medium Level Interrupt Executing bit mask. */ -#define PMIC_MEDLVLEX_bp 1 /* Medium Level Interrupt Executing bit position. */ - -#define PMIC_LOLVLEX_bm 0x01 /* Low Level Interrupt Executing bit mask. */ -#define PMIC_LOLVLEX_bp 0 /* Low Level Interrupt Executing bit position. */ - -/* PMIC.INTPRI bit masks and bit positions */ -#define PMIC_INTPRI_gm 0xFF /* Interrupt Priority group mask. */ -#define PMIC_INTPRI_gp 0 /* Interrupt Priority group position. */ -#define PMIC_INTPRI0_bm (1<<0) /* Interrupt Priority bit 0 mask. */ -#define PMIC_INTPRI0_bp 0 /* Interrupt Priority bit 0 position. */ -#define PMIC_INTPRI1_bm (1<<1) /* Interrupt Priority bit 1 mask. */ -#define PMIC_INTPRI1_bp 1 /* Interrupt Priority bit 1 position. */ -#define PMIC_INTPRI2_bm (1<<2) /* Interrupt Priority bit 2 mask. */ -#define PMIC_INTPRI2_bp 2 /* Interrupt Priority bit 2 position. */ -#define PMIC_INTPRI3_bm (1<<3) /* Interrupt Priority bit 3 mask. */ -#define PMIC_INTPRI3_bp 3 /* Interrupt Priority bit 3 position. */ -#define PMIC_INTPRI4_bm (1<<4) /* Interrupt Priority bit 4 mask. */ -#define PMIC_INTPRI4_bp 4 /* Interrupt Priority bit 4 position. */ -#define PMIC_INTPRI5_bm (1<<5) /* Interrupt Priority bit 5 mask. */ -#define PMIC_INTPRI5_bp 5 /* Interrupt Priority bit 5 position. */ -#define PMIC_INTPRI6_bm (1<<6) /* Interrupt Priority bit 6 mask. */ -#define PMIC_INTPRI6_bp 6 /* Interrupt Priority bit 6 position. */ -#define PMIC_INTPRI7_bm (1<<7) /* Interrupt Priority bit 7 mask. */ -#define PMIC_INTPRI7_bp 7 /* Interrupt Priority bit 7 position. */ - -/* PMIC.CTRL bit masks and bit positions */ -#define PMIC_RREN_bm 0x80 /* Round-Robin Priority Enable bit mask. */ -#define PMIC_RREN_bp 7 /* Round-Robin Priority Enable bit position. */ - -#define PMIC_IVSEL_bm 0x40 /* Interrupt Vector Select bit mask. */ -#define PMIC_IVSEL_bp 6 /* Interrupt Vector Select bit position. */ - -#define PMIC_HILVLEN_bm 0x04 /* High Level Enable bit mask. */ -#define PMIC_HILVLEN_bp 2 /* High Level Enable bit position. */ - -#define PMIC_MEDLVLEN_bm 0x02 /* Medium Level Enable bit mask. */ -#define PMIC_MEDLVLEN_bp 1 /* Medium Level Enable bit position. */ - -#define PMIC_LOLVLEN_bm 0x01 /* Low Level Enable bit mask. */ -#define PMIC_LOLVLEN_bp 0 /* Low Level Enable bit position. */ - -/* PORTCFG - Port Configuration */ -/* PORTCFG.VPCTRLA bit masks and bit positions */ -#define PORTCFG_VP1MAP_gm 0xF0 /* Virtual Port 1 Mapping group mask. */ -#define PORTCFG_VP1MAP_gp 4 /* Virtual Port 1 Mapping group position. */ -#define PORTCFG_VP1MAP0_bm (1<<4) /* Virtual Port 1 Mapping bit 0 mask. */ -#define PORTCFG_VP1MAP0_bp 4 /* Virtual Port 1 Mapping bit 0 position. */ -#define PORTCFG_VP1MAP1_bm (1<<5) /* Virtual Port 1 Mapping bit 1 mask. */ -#define PORTCFG_VP1MAP1_bp 5 /* Virtual Port 1 Mapping bit 1 position. */ -#define PORTCFG_VP1MAP2_bm (1<<6) /* Virtual Port 1 Mapping bit 2 mask. */ -#define PORTCFG_VP1MAP2_bp 6 /* Virtual Port 1 Mapping bit 2 position. */ -#define PORTCFG_VP1MAP3_bm (1<<7) /* Virtual Port 1 Mapping bit 3 mask. */ -#define PORTCFG_VP1MAP3_bp 7 /* Virtual Port 1 Mapping bit 3 position. */ - -#define PORTCFG_VP0MAP_gm 0x0F /* Virtual Port 0 Mapping group mask. */ -#define PORTCFG_VP0MAP_gp 0 /* Virtual Port 0 Mapping group position. */ -#define PORTCFG_VP0MAP0_bm (1<<0) /* Virtual Port 0 Mapping bit 0 mask. */ -#define PORTCFG_VP0MAP0_bp 0 /* Virtual Port 0 Mapping bit 0 position. */ -#define PORTCFG_VP0MAP1_bm (1<<1) /* Virtual Port 0 Mapping bit 1 mask. */ -#define PORTCFG_VP0MAP1_bp 1 /* Virtual Port 0 Mapping bit 1 position. */ -#define PORTCFG_VP0MAP2_bm (1<<2) /* Virtual Port 0 Mapping bit 2 mask. */ -#define PORTCFG_VP0MAP2_bp 2 /* Virtual Port 0 Mapping bit 2 position. */ -#define PORTCFG_VP0MAP3_bm (1<<3) /* Virtual Port 0 Mapping bit 3 mask. */ -#define PORTCFG_VP0MAP3_bp 3 /* Virtual Port 0 Mapping bit 3 position. */ - -/* PORTCFG.VPCTRLB bit masks and bit positions */ -#define PORTCFG_VP3MAP_gm 0xF0 /* Virtual Port 3 Mapping group mask. */ -#define PORTCFG_VP3MAP_gp 4 /* Virtual Port 3 Mapping group position. */ -#define PORTCFG_VP3MAP0_bm (1<<4) /* Virtual Port 3 Mapping bit 0 mask. */ -#define PORTCFG_VP3MAP0_bp 4 /* Virtual Port 3 Mapping bit 0 position. */ -#define PORTCFG_VP3MAP1_bm (1<<5) /* Virtual Port 3 Mapping bit 1 mask. */ -#define PORTCFG_VP3MAP1_bp 5 /* Virtual Port 3 Mapping bit 1 position. */ -#define PORTCFG_VP3MAP2_bm (1<<6) /* Virtual Port 3 Mapping bit 2 mask. */ -#define PORTCFG_VP3MAP2_bp 6 /* Virtual Port 3 Mapping bit 2 position. */ -#define PORTCFG_VP3MAP3_bm (1<<7) /* Virtual Port 3 Mapping bit 3 mask. */ -#define PORTCFG_VP3MAP3_bp 7 /* Virtual Port 3 Mapping bit 3 position. */ - -#define PORTCFG_VP2MAP_gm 0x0F /* Virtual Port 2 Mapping group mask. */ -#define PORTCFG_VP2MAP_gp 0 /* Virtual Port 2 Mapping group position. */ -#define PORTCFG_VP2MAP0_bm (1<<0) /* Virtual Port 2 Mapping bit 0 mask. */ -#define PORTCFG_VP2MAP0_bp 0 /* Virtual Port 2 Mapping bit 0 position. */ -#define PORTCFG_VP2MAP1_bm (1<<1) /* Virtual Port 2 Mapping bit 1 mask. */ -#define PORTCFG_VP2MAP1_bp 1 /* Virtual Port 2 Mapping bit 1 position. */ -#define PORTCFG_VP2MAP2_bm (1<<2) /* Virtual Port 2 Mapping bit 2 mask. */ -#define PORTCFG_VP2MAP2_bp 2 /* Virtual Port 2 Mapping bit 2 position. */ -#define PORTCFG_VP2MAP3_bm (1<<3) /* Virtual Port 2 Mapping bit 3 mask. */ -#define PORTCFG_VP2MAP3_bp 3 /* Virtual Port 2 Mapping bit 3 position. */ - -/* PORTCFG.CLKEVOUT bit masks and bit positions */ -#define PORTCFG_CLKOUT_gm 0x03 /* Peripheral Clock Output Port group mask. */ -#define PORTCFG_CLKOUT_gp 0 /* Peripheral Clock Output Port group position. */ -#define PORTCFG_CLKOUT0_bm (1<<0) /* Peripheral Clock Output Port bit 0 mask. */ -#define PORTCFG_CLKOUT0_bp 0 /* Peripheral Clock Output Port bit 0 position. */ -#define PORTCFG_CLKOUT1_bm (1<<1) /* Peripheral Clock Output Port bit 1 mask. */ -#define PORTCFG_CLKOUT1_bp 1 /* Peripheral Clock Output Port bit 1 position. */ - -#define PORTCFG_CLKOUTSEL_gm 0x0C /* Peripheral Clock Output Select group mask. */ -#define PORTCFG_CLKOUTSEL_gp 2 /* Peripheral Clock Output Select group position. */ -#define PORTCFG_CLKOUTSEL0_bm (1<<2) /* Peripheral Clock Output Select bit 0 mask. */ -#define PORTCFG_CLKOUTSEL0_bp 2 /* Peripheral Clock Output Select bit 0 position. */ -#define PORTCFG_CLKOUTSEL1_bm (1<<3) /* Peripheral Clock Output Select bit 1 mask. */ -#define PORTCFG_CLKOUTSEL1_bp 3 /* Peripheral Clock Output Select bit 1 position. */ - -#define PORTCFG_EVOUT_gm 0x30 /* Event Output Port group mask. */ -#define PORTCFG_EVOUT_gp 4 /* Event Output Port group position. */ -#define PORTCFG_EVOUT0_bm (1<<4) /* Event Output Port bit 0 mask. */ -#define PORTCFG_EVOUT0_bp 4 /* Event Output Port bit 0 position. */ -#define PORTCFG_EVOUT1_bm (1<<5) /* Event Output Port bit 1 mask. */ -#define PORTCFG_EVOUT1_bp 5 /* Event Output Port bit 1 position. */ - -#define PORTCFG_RTCOUT_bm 0x40 /* RTC Clock Output bit mask. */ -#define PORTCFG_RTCOUT_bp 6 /* RTC Clock Output bit position. */ - -#define PORTCFG_CLKEVPIN_bm 0x80 /* Peripheral Clock and Event Output pin Select bit mask. */ -#define PORTCFG_CLKEVPIN_bp 7 /* Peripheral Clock and Event Output pin Select bit position. */ - -/* PORTCFG.EBIOUT bit masks and bit positions */ -#define PORTCFG_EBICSOUT_gm 0x03 /* EBI Chip Select Output group mask. */ -#define PORTCFG_EBICSOUT_gp 0 /* EBI Chip Select Output group position. */ -#define PORTCFG_EBICSOUT0_bm (1<<0) /* EBI Chip Select Output bit 0 mask. */ -#define PORTCFG_EBICSOUT0_bp 0 /* EBI Chip Select Output bit 0 position. */ -#define PORTCFG_EBICSOUT1_bm (1<<1) /* EBI Chip Select Output bit 1 mask. */ -#define PORTCFG_EBICSOUT1_bp 1 /* EBI Chip Select Output bit 1 position. */ - -#define PORTCFG_EBIADROUT_gm 0x0C /* EBI Address Output group mask. */ -#define PORTCFG_EBIADROUT_gp 2 /* EBI Address Output group position. */ -#define PORTCFG_EBIADROUT0_bm (1<<2) /* EBI Address Output bit 0 mask. */ -#define PORTCFG_EBIADROUT0_bp 2 /* EBI Address Output bit 0 position. */ -#define PORTCFG_EBIADROUT1_bm (1<<3) /* EBI Address Output bit 1 mask. */ -#define PORTCFG_EBIADROUT1_bp 3 /* EBI Address Output bit 1 position. */ - -/* PORTCFG.EVOUTSEL bit masks and bit positions */ -#define PORTCFG_EVOUTSEL_gm 0x07 /* Event Output Select group mask. */ -#define PORTCFG_EVOUTSEL_gp 0 /* Event Output Select group position. */ -#define PORTCFG_EVOUTSEL0_bm (1<<0) /* Event Output Select bit 0 mask. */ -#define PORTCFG_EVOUTSEL0_bp 0 /* Event Output Select bit 0 position. */ -#define PORTCFG_EVOUTSEL1_bm (1<<1) /* Event Output Select bit 1 mask. */ -#define PORTCFG_EVOUTSEL1_bp 1 /* Event Output Select bit 1 position. */ -#define PORTCFG_EVOUTSEL2_bm (1<<2) /* Event Output Select bit 2 mask. */ -#define PORTCFG_EVOUTSEL2_bp 2 /* Event Output Select bit 2 position. */ - -/* CRC - Cyclic Redundancy Checker */ -/* CRC.CTRL bit masks and bit positions */ -#define CRC_RESET_gm 0xC0 /* Reset group mask. */ -#define CRC_RESET_gp 6 /* Reset group position. */ -#define CRC_RESET0_bm (1<<6) /* Reset bit 0 mask. */ -#define CRC_RESET0_bp 6 /* Reset bit 0 position. */ -#define CRC_RESET1_bm (1<<7) /* Reset bit 1 mask. */ -#define CRC_RESET1_bp 7 /* Reset bit 1 position. */ - -#define CRC_CRC32_bm 0x20 /* CRC Mode bit mask. */ -#define CRC_CRC32_bp 5 /* CRC Mode bit position. */ - -#define CRC_SOURCE_gm 0x0F /* Input Source group mask. */ -#define CRC_SOURCE_gp 0 /* Input Source group position. */ -#define CRC_SOURCE0_bm (1<<0) /* Input Source bit 0 mask. */ -#define CRC_SOURCE0_bp 0 /* Input Source bit 0 position. */ -#define CRC_SOURCE1_bm (1<<1) /* Input Source bit 1 mask. */ -#define CRC_SOURCE1_bp 1 /* Input Source bit 1 position. */ -#define CRC_SOURCE2_bm (1<<2) /* Input Source bit 2 mask. */ -#define CRC_SOURCE2_bp 2 /* Input Source bit 2 position. */ -#define CRC_SOURCE3_bm (1<<3) /* Input Source bit 3 mask. */ -#define CRC_SOURCE3_bp 3 /* Input Source bit 3 position. */ - -/* CRC.STATUS bit masks and bit positions */ -#define CRC_ZERO_bm 0x02 /* Zero detection bit mask. */ -#define CRC_ZERO_bp 1 /* Zero detection bit position. */ - -#define CRC_BUSY_bm 0x01 /* Busy bit mask. */ -#define CRC_BUSY_bp 0 /* Busy bit position. */ - -/* EVSYS - Event System */ -/* EVSYS.CH0MUX bit masks and bit positions */ -#define EVSYS_CHMUX_gm 0xFF /* Event Channel 0 Multiplexer group mask. */ -#define EVSYS_CHMUX_gp 0 /* Event Channel 0 Multiplexer group position. */ -#define EVSYS_CHMUX0_bm (1<<0) /* Event Channel 0 Multiplexer bit 0 mask. */ -#define EVSYS_CHMUX0_bp 0 /* Event Channel 0 Multiplexer bit 0 position. */ -#define EVSYS_CHMUX1_bm (1<<1) /* Event Channel 0 Multiplexer bit 1 mask. */ -#define EVSYS_CHMUX1_bp 1 /* Event Channel 0 Multiplexer bit 1 position. */ -#define EVSYS_CHMUX2_bm (1<<2) /* Event Channel 0 Multiplexer bit 2 mask. */ -#define EVSYS_CHMUX2_bp 2 /* Event Channel 0 Multiplexer bit 2 position. */ -#define EVSYS_CHMUX3_bm (1<<3) /* Event Channel 0 Multiplexer bit 3 mask. */ -#define EVSYS_CHMUX3_bp 3 /* Event Channel 0 Multiplexer bit 3 position. */ -#define EVSYS_CHMUX4_bm (1<<4) /* Event Channel 0 Multiplexer bit 4 mask. */ -#define EVSYS_CHMUX4_bp 4 /* Event Channel 0 Multiplexer bit 4 position. */ -#define EVSYS_CHMUX5_bm (1<<5) /* Event Channel 0 Multiplexer bit 5 mask. */ -#define EVSYS_CHMUX5_bp 5 /* Event Channel 0 Multiplexer bit 5 position. */ -#define EVSYS_CHMUX6_bm (1<<6) /* Event Channel 0 Multiplexer bit 6 mask. */ -#define EVSYS_CHMUX6_bp 6 /* Event Channel 0 Multiplexer bit 6 position. */ -#define EVSYS_CHMUX7_bm (1<<7) /* Event Channel 0 Multiplexer bit 7 mask. */ -#define EVSYS_CHMUX7_bp 7 /* Event Channel 0 Multiplexer bit 7 position. */ - -/* EVSYS.CH1MUX bit masks and bit positions */ -/* EVSYS_CHMUX Predefined. */ -/* EVSYS_CHMUX Predefined. */ - -/* EVSYS.CH2MUX bit masks and bit positions */ -/* EVSYS_CHMUX Predefined. */ -/* EVSYS_CHMUX Predefined. */ - -/* EVSYS.CH3MUX bit masks and bit positions */ -/* EVSYS_CHMUX Predefined. */ -/* EVSYS_CHMUX Predefined. */ - -/* EVSYS.CH0CTRL bit masks and bit positions */ -#define EVSYS_QDIRM_gm 0x60 /* Quadrature Decoder Index Recognition Mode group mask. */ -#define EVSYS_QDIRM_gp 5 /* Quadrature Decoder Index Recognition Mode group position. */ -#define EVSYS_QDIRM0_bm (1<<5) /* Quadrature Decoder Index Recognition Mode bit 0 mask. */ -#define EVSYS_QDIRM0_bp 5 /* Quadrature Decoder Index Recognition Mode bit 0 position. */ -#define EVSYS_QDIRM1_bm (1<<6) /* Quadrature Decoder Index Recognition Mode bit 1 mask. */ -#define EVSYS_QDIRM1_bp 6 /* Quadrature Decoder Index Recognition Mode bit 1 position. */ - -#define EVSYS_QDIEN_bm 0x10 /* Quadrature Decoder Index Enable bit mask. */ -#define EVSYS_QDIEN_bp 4 /* Quadrature Decoder Index Enable bit position. */ - -#define EVSYS_QDEN_bm 0x08 /* Quadrature Decoder Enable bit mask. */ -#define EVSYS_QDEN_bp 3 /* Quadrature Decoder Enable bit position. */ - -#define EVSYS_DIGFILT_gm 0x07 /* Digital Filter group mask. */ -#define EVSYS_DIGFILT_gp 0 /* Digital Filter group position. */ -#define EVSYS_DIGFILT0_bm (1<<0) /* Digital Filter bit 0 mask. */ -#define EVSYS_DIGFILT0_bp 0 /* Digital Filter bit 0 position. */ -#define EVSYS_DIGFILT1_bm (1<<1) /* Digital Filter bit 1 mask. */ -#define EVSYS_DIGFILT1_bp 1 /* Digital Filter bit 1 position. */ -#define EVSYS_DIGFILT2_bm (1<<2) /* Digital Filter bit 2 mask. */ -#define EVSYS_DIGFILT2_bp 2 /* Digital Filter bit 2 position. */ - -/* EVSYS.CH1CTRL bit masks and bit positions */ -/* EVSYS_DIGFILT Predefined. */ -/* EVSYS_DIGFILT Predefined. */ - -/* EVSYS.CH2CTRL bit masks and bit positions */ -/* EVSYS_DIGFILT Predefined. */ -/* EVSYS_DIGFILT Predefined. */ - -/* EVSYS.CH3CTRL bit masks and bit positions */ -/* EVSYS_DIGFILT Predefined. */ -/* EVSYS_DIGFILT Predefined. */ - -/* NVM - Non Volatile Memory Controller */ -/* NVM.CMD bit masks and bit positions */ -#define NVM_CMD_gm 0x7F /* Command group mask. */ -#define NVM_CMD_gp 0 /* Command group position. */ -#define NVM_CMD0_bm (1<<0) /* Command bit 0 mask. */ -#define NVM_CMD0_bp 0 /* Command bit 0 position. */ -#define NVM_CMD1_bm (1<<1) /* Command bit 1 mask. */ -#define NVM_CMD1_bp 1 /* Command bit 1 position. */ -#define NVM_CMD2_bm (1<<2) /* Command bit 2 mask. */ -#define NVM_CMD2_bp 2 /* Command bit 2 position. */ -#define NVM_CMD3_bm (1<<3) /* Command bit 3 mask. */ -#define NVM_CMD3_bp 3 /* Command bit 3 position. */ -#define NVM_CMD4_bm (1<<4) /* Command bit 4 mask. */ -#define NVM_CMD4_bp 4 /* Command bit 4 position. */ -#define NVM_CMD5_bm (1<<5) /* Command bit 5 mask. */ -#define NVM_CMD5_bp 5 /* Command bit 5 position. */ -#define NVM_CMD6_bm (1<<6) /* Command bit 6 mask. */ -#define NVM_CMD6_bp 6 /* Command bit 6 position. */ - -/* NVM.CTRLA bit masks and bit positions */ -#define NVM_CMDEX_bm 0x01 /* Command Execute bit mask. */ -#define NVM_CMDEX_bp 0 /* Command Execute bit position. */ - -/* NVM.CTRLB bit masks and bit positions */ -#define NVM_EEMAPEN_bm 0x08 /* EEPROM Mapping Enable bit mask. */ -#define NVM_EEMAPEN_bp 3 /* EEPROM Mapping Enable bit position. */ - -#define NVM_FPRM_bm 0x04 /* Flash Power Reduction Enable bit mask. */ -#define NVM_FPRM_bp 2 /* Flash Power Reduction Enable bit position. */ - -#define NVM_EPRM_bm 0x02 /* EEPROM Power Reduction Enable bit mask. */ -#define NVM_EPRM_bp 1 /* EEPROM Power Reduction Enable bit position. */ - -#define NVM_SPMLOCK_bm 0x01 /* SPM Lock bit mask. */ -#define NVM_SPMLOCK_bp 0 /* SPM Lock bit position. */ - -/* NVM.INTCTRL bit masks and bit positions */ -#define NVM_SPMLVL_gm 0x0C /* SPM Interrupt Level group mask. */ -#define NVM_SPMLVL_gp 2 /* SPM Interrupt Level group position. */ -#define NVM_SPMLVL0_bm (1<<2) /* SPM Interrupt Level bit 0 mask. */ -#define NVM_SPMLVL0_bp 2 /* SPM Interrupt Level bit 0 position. */ -#define NVM_SPMLVL1_bm (1<<3) /* SPM Interrupt Level bit 1 mask. */ -#define NVM_SPMLVL1_bp 3 /* SPM Interrupt Level bit 1 position. */ - -#define NVM_EELVL_gm 0x03 /* EEPROM Interrupt Level group mask. */ -#define NVM_EELVL_gp 0 /* EEPROM Interrupt Level group position. */ -#define NVM_EELVL0_bm (1<<0) /* EEPROM Interrupt Level bit 0 mask. */ -#define NVM_EELVL0_bp 0 /* EEPROM Interrupt Level bit 0 position. */ -#define NVM_EELVL1_bm (1<<1) /* EEPROM Interrupt Level bit 1 mask. */ -#define NVM_EELVL1_bp 1 /* EEPROM Interrupt Level bit 1 position. */ - -/* NVM.STATUS bit masks and bit positions */ -#define NVM_NVMBUSY_bm 0x80 /* Non-volatile Memory Busy bit mask. */ -#define NVM_NVMBUSY_bp 7 /* Non-volatile Memory Busy bit position. */ - -#define NVM_FBUSY_bm 0x40 /* Flash Memory Busy bit mask. */ -#define NVM_FBUSY_bp 6 /* Flash Memory Busy bit position. */ - -#define NVM_EELOAD_bm 0x02 /* EEPROM Page Buffer Active Loading bit mask. */ -#define NVM_EELOAD_bp 1 /* EEPROM Page Buffer Active Loading bit position. */ - -#define NVM_FLOAD_bm 0x01 /* Flash Page Buffer Active Loading bit mask. */ -#define NVM_FLOAD_bp 0 /* Flash Page Buffer Active Loading bit position. */ - -/* NVM.LOCKBITS bit masks and bit positions */ -#define NVM_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ -#define NVM_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ -#define NVM_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ -#define NVM_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ -#define NVM_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ -#define NVM_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ - -#define NVM_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ -#define NVM_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ -#define NVM_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ -#define NVM_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ -#define NVM_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ -#define NVM_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ - -#define NVM_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ -#define NVM_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ -#define NVM_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ -#define NVM_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ -#define NVM_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ -#define NVM_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ - -#define NVM_LB_gm 0x03 /* Lock Bits group mask. */ -#define NVM_LB_gp 0 /* Lock Bits group position. */ -#define NVM_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ -#define NVM_LB0_bp 0 /* Lock Bits bit 0 position. */ -#define NVM_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ -#define NVM_LB1_bp 1 /* Lock Bits bit 1 position. */ - -/* ADC - Analog/Digital Converter */ -/* ADC_CH.CTRL bit masks and bit positions */ -#define ADC_CH_START_bm 0x80 /* Channel Start Conversion bit mask. */ -#define ADC_CH_START_bp 7 /* Channel Start Conversion bit position. */ - -#define ADC_CH_GAIN_gm 0x1C /* Gain Factor group mask. */ -#define ADC_CH_GAIN_gp 2 /* Gain Factor group position. */ -#define ADC_CH_GAIN0_bm (1<<2) /* Gain Factor bit 0 mask. */ -#define ADC_CH_GAIN0_bp 2 /* Gain Factor bit 0 position. */ -#define ADC_CH_GAIN1_bm (1<<3) /* Gain Factor bit 1 mask. */ -#define ADC_CH_GAIN1_bp 3 /* Gain Factor bit 1 position. */ -#define ADC_CH_GAIN2_bm (1<<4) /* Gain Factor bit 2 mask. */ -#define ADC_CH_GAIN2_bp 4 /* Gain Factor bit 2 position. */ - -#define ADC_CH_INPUTMODE_gm 0x03 /* Input Mode Select group mask. */ -#define ADC_CH_INPUTMODE_gp 0 /* Input Mode Select group position. */ -#define ADC_CH_INPUTMODE0_bm (1<<0) /* Input Mode Select bit 0 mask. */ -#define ADC_CH_INPUTMODE0_bp 0 /* Input Mode Select bit 0 position. */ -#define ADC_CH_INPUTMODE1_bm (1<<1) /* Input Mode Select bit 1 mask. */ -#define ADC_CH_INPUTMODE1_bp 1 /* Input Mode Select bit 1 position. */ - -/* ADC_CH.MUXCTRL bit masks and bit positions */ -#define ADC_CH_MUXPOS_gm 0x78 /* MUX selection on Positive ADC input group mask. */ -#define ADC_CH_MUXPOS_gp 3 /* MUX selection on Positive ADC input group position. */ -#define ADC_CH_MUXPOS0_bm (1<<3) /* MUX selection on Positive ADC input bit 0 mask. */ -#define ADC_CH_MUXPOS0_bp 3 /* MUX selection on Positive ADC input bit 0 position. */ -#define ADC_CH_MUXPOS1_bm (1<<4) /* MUX selection on Positive ADC input bit 1 mask. */ -#define ADC_CH_MUXPOS1_bp 4 /* MUX selection on Positive ADC input bit 1 position. */ -#define ADC_CH_MUXPOS2_bm (1<<5) /* MUX selection on Positive ADC input bit 2 mask. */ -#define ADC_CH_MUXPOS2_bp 5 /* MUX selection on Positive ADC input bit 2 position. */ -#define ADC_CH_MUXPOS3_bm (1<<6) /* MUX selection on Positive ADC input bit 3 mask. */ -#define ADC_CH_MUXPOS3_bp 6 /* MUX selection on Positive ADC input bit 3 position. */ - -#define ADC_CH_MUXINT_gm 0x78 /* MUX selection on Internal ADC input group mask. */ -#define ADC_CH_MUXINT_gp 3 /* MUX selection on Internal ADC input group position. */ -#define ADC_CH_MUXINT0_bm (1<<3) /* MUX selection on Internal ADC input bit 0 mask. */ -#define ADC_CH_MUXINT0_bp 3 /* MUX selection on Internal ADC input bit 0 position. */ -#define ADC_CH_MUXINT1_bm (1<<4) /* MUX selection on Internal ADC input bit 1 mask. */ -#define ADC_CH_MUXINT1_bp 4 /* MUX selection on Internal ADC input bit 1 position. */ -#define ADC_CH_MUXINT2_bm (1<<5) /* MUX selection on Internal ADC input bit 2 mask. */ -#define ADC_CH_MUXINT2_bp 5 /* MUX selection on Internal ADC input bit 2 position. */ -#define ADC_CH_MUXINT3_bm (1<<6) /* MUX selection on Internal ADC input bit 3 mask. */ -#define ADC_CH_MUXINT3_bp 6 /* MUX selection on Internal ADC input bit 3 position. */ - -#define ADC_CH_MUXNEG_gm 0x03 /* MUX selection on Negative ADC input group mask. */ -#define ADC_CH_MUXNEG_gp 0 /* MUX selection on Negative ADC input group position. */ -#define ADC_CH_MUXNEG0_bm (1<<0) /* MUX selection on Negative ADC input bit 0 mask. */ -#define ADC_CH_MUXNEG0_bp 0 /* MUX selection on Negative ADC input bit 0 position. */ -#define ADC_CH_MUXNEG1_bm (1<<1) /* MUX selection on Negative ADC input bit 1 mask. */ -#define ADC_CH_MUXNEG1_bp 1 /* MUX selection on Negative ADC input bit 1 position. */ - -/* ADC_CH.INTCTRL bit masks and bit positions */ -#define ADC_CH_INTMODE_gm 0x0C /* Interrupt Mode group mask. */ -#define ADC_CH_INTMODE_gp 2 /* Interrupt Mode group position. */ -#define ADC_CH_INTMODE0_bm (1<<2) /* Interrupt Mode bit 0 mask. */ -#define ADC_CH_INTMODE0_bp 2 /* Interrupt Mode bit 0 position. */ -#define ADC_CH_INTMODE1_bm (1<<3) /* Interrupt Mode bit 1 mask. */ -#define ADC_CH_INTMODE1_bp 3 /* Interrupt Mode bit 1 position. */ - -#define ADC_CH_INTLVL_gm 0x03 /* Interrupt Level group mask. */ -#define ADC_CH_INTLVL_gp 0 /* Interrupt Level group position. */ -#define ADC_CH_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */ -#define ADC_CH_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */ -#define ADC_CH_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ -#define ADC_CH_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */ - -/* ADC_CH.INTFLAGS bit masks and bit positions */ -#define ADC_CH_CHIF_bm 0x01 /* Channel Interrupt Flag bit mask. */ -#define ADC_CH_CHIF_bp 0 /* Channel Interrupt Flag bit position. */ - -/* ADC_CH.SCAN bit masks and bit positions */ -#define ADC_CH_OFFSET_gm 0xF0 /* Positive MUX setting offset group mask. */ -#define ADC_CH_OFFSET_gp 4 /* Positive MUX setting offset group position. */ -#define ADC_CH_OFFSET0_bm (1<<4) /* Positive MUX setting offset bit 0 mask. */ -#define ADC_CH_OFFSET0_bp 4 /* Positive MUX setting offset bit 0 position. */ -#define ADC_CH_OFFSET1_bm (1<<5) /* Positive MUX setting offset bit 1 mask. */ -#define ADC_CH_OFFSET1_bp 5 /* Positive MUX setting offset bit 1 position. */ -#define ADC_CH_OFFSET2_bm (1<<6) /* Positive MUX setting offset bit 2 mask. */ -#define ADC_CH_OFFSET2_bp 6 /* Positive MUX setting offset bit 2 position. */ -#define ADC_CH_OFFSET3_bm (1<<7) /* Positive MUX setting offset bit 3 mask. */ -#define ADC_CH_OFFSET3_bp 7 /* Positive MUX setting offset bit 3 position. */ - -#define ADC_CH_COUNT_gm 0x0F /* Number of Channels included in scan group mask. */ -#define ADC_CH_COUNT_gp 0 /* Number of Channels included in scan group position. */ -#define ADC_CH_COUNT0_bm (1<<0) /* Number of Channels included in scan bit 0 mask. */ -#define ADC_CH_COUNT0_bp 0 /* Number of Channels included in scan bit 0 position. */ -#define ADC_CH_COUNT1_bm (1<<1) /* Number of Channels included in scan bit 1 mask. */ -#define ADC_CH_COUNT1_bp 1 /* Number of Channels included in scan bit 1 position. */ -#define ADC_CH_COUNT2_bm (1<<2) /* Number of Channels included in scan bit 2 mask. */ -#define ADC_CH_COUNT2_bp 2 /* Number of Channels included in scan bit 2 position. */ -#define ADC_CH_COUNT3_bm (1<<3) /* Number of Channels included in scan bit 3 mask. */ -#define ADC_CH_COUNT3_bp 3 /* Number of Channels included in scan bit 3 position. */ - -/* ADC.CTRLA bit masks and bit positions */ -#define ADC_CH0START_bm 0x04 /* Channel 0 Start Conversion bit mask. */ -#define ADC_CH0START_bp 2 /* Channel 0 Start Conversion bit position. */ - -#define ADC_FLUSH_bm 0x02 /* ADC Flush bit mask. */ -#define ADC_FLUSH_bp 1 /* ADC Flush bit position. */ - -#define ADC_ENABLE_bm 0x01 /* Enable ADC bit mask. */ -#define ADC_ENABLE_bp 0 /* Enable ADC bit position. */ - -/* ADC.CTRLB bit masks and bit positions */ -#define ADC_CURRLIMIT_gm 0x60 /* Current limit group mask. */ -#define ADC_CURRLIMIT_gp 5 /* Current limit group position. */ -#define ADC_CURRLIMIT0_bm (1<<5) /* Current limit bit 0 mask. */ -#define ADC_CURRLIMIT0_bp 5 /* Current limit bit 0 position. */ -#define ADC_CURRLIMIT1_bm (1<<6) /* Current limit bit 1 mask. */ -#define ADC_CURRLIMIT1_bp 6 /* Current limit bit 1 position. */ - -#define ADC_CONMODE_bm 0x10 /* Conversion Mode bit mask. */ -#define ADC_CONMODE_bp 4 /* Conversion Mode bit position. */ - -#define ADC_FREERUN_bm 0x08 /* Free Running Mode Enable bit mask. */ -#define ADC_FREERUN_bp 3 /* Free Running Mode Enable bit position. */ - -#define ADC_RESOLUTION_gm 0x06 /* Result Resolution group mask. */ -#define ADC_RESOLUTION_gp 1 /* Result Resolution group position. */ -#define ADC_RESOLUTION0_bm (1<<1) /* Result Resolution bit 0 mask. */ -#define ADC_RESOLUTION0_bp 1 /* Result Resolution bit 0 position. */ -#define ADC_RESOLUTION1_bm (1<<2) /* Result Resolution bit 1 mask. */ -#define ADC_RESOLUTION1_bp 2 /* Result Resolution bit 1 position. */ - -/* ADC.REFCTRL bit masks and bit positions */ -#define ADC_REFSEL_gm 0x70 /* Reference Selection group mask. */ -#define ADC_REFSEL_gp 4 /* Reference Selection group position. */ -#define ADC_REFSEL0_bm (1<<4) /* Reference Selection bit 0 mask. */ -#define ADC_REFSEL0_bp 4 /* Reference Selection bit 0 position. */ -#define ADC_REFSEL1_bm (1<<5) /* Reference Selection bit 1 mask. */ -#define ADC_REFSEL1_bp 5 /* Reference Selection bit 1 position. */ -#define ADC_REFSEL2_bm (1<<6) /* Reference Selection bit 2 mask. */ -#define ADC_REFSEL2_bp 6 /* Reference Selection bit 2 position. */ - -#define ADC_BANDGAP_bm 0x02 /* Bandgap enable bit mask. */ -#define ADC_BANDGAP_bp 1 /* Bandgap enable bit position. */ - -#define ADC_TEMPREF_bm 0x01 /* Temperature Reference Enable bit mask. */ -#define ADC_TEMPREF_bp 0 /* Temperature Reference Enable bit position. */ - -/* ADC.EVCTRL bit masks and bit positions */ -#define ADC_EVSEL_gm 0x18 /* Event Input Select group mask. */ -#define ADC_EVSEL_gp 3 /* Event Input Select group position. */ -#define ADC_EVSEL0_bm (1<<3) /* Event Input Select bit 0 mask. */ -#define ADC_EVSEL0_bp 3 /* Event Input Select bit 0 position. */ -#define ADC_EVSEL1_bm (1<<4) /* Event Input Select bit 1 mask. */ -#define ADC_EVSEL1_bp 4 /* Event Input Select bit 1 position. */ - -#define ADC_EVACT_gm 0x07 /* Event Action Select group mask. */ -#define ADC_EVACT_gp 0 /* Event Action Select group position. */ -#define ADC_EVACT0_bm (1<<0) /* Event Action Select bit 0 mask. */ -#define ADC_EVACT0_bp 0 /* Event Action Select bit 0 position. */ -#define ADC_EVACT1_bm (1<<1) /* Event Action Select bit 1 mask. */ -#define ADC_EVACT1_bp 1 /* Event Action Select bit 1 position. */ -#define ADC_EVACT2_bm (1<<2) /* Event Action Select bit 2 mask. */ -#define ADC_EVACT2_bp 2 /* Event Action Select bit 2 position. */ - -/* ADC.PRESCALER bit masks and bit positions */ -#define ADC_PRESCALER_gm 0x07 /* Clock Prescaler Selection group mask. */ -#define ADC_PRESCALER_gp 0 /* Clock Prescaler Selection group position. */ -#define ADC_PRESCALER0_bm (1<<0) /* Clock Prescaler Selection bit 0 mask. */ -#define ADC_PRESCALER0_bp 0 /* Clock Prescaler Selection bit 0 position. */ -#define ADC_PRESCALER1_bm (1<<1) /* Clock Prescaler Selection bit 1 mask. */ -#define ADC_PRESCALER1_bp 1 /* Clock Prescaler Selection bit 1 position. */ -#define ADC_PRESCALER2_bm (1<<2) /* Clock Prescaler Selection bit 2 mask. */ -#define ADC_PRESCALER2_bp 2 /* Clock Prescaler Selection bit 2 position. */ - -/* ADC.INTFLAGS bit masks and bit positions */ -#define ADC_CH0IF_bm 0x01 /* Channel 0 Interrupt Flag bit mask. */ -#define ADC_CH0IF_bp 0 /* Channel 0 Interrupt Flag bit position. */ - -/* ADC.SAMPCTRL bit masks and bit positions */ -#define ADC_SAMPVAL_gm 0x3F /* Sampling time control register group mask. */ -#define ADC_SAMPVAL_gp 0 /* Sampling time control register group position. */ -#define ADC_SAMPVAL0_bm (1<<0) /* Sampling time control register bit 0 mask. */ -#define ADC_SAMPVAL0_bp 0 /* Sampling time control register bit 0 position. */ -#define ADC_SAMPVAL1_bm (1<<1) /* Sampling time control register bit 1 mask. */ -#define ADC_SAMPVAL1_bp 1 /* Sampling time control register bit 1 position. */ -#define ADC_SAMPVAL2_bm (1<<2) /* Sampling time control register bit 2 mask. */ -#define ADC_SAMPVAL2_bp 2 /* Sampling time control register bit 2 position. */ -#define ADC_SAMPVAL3_bm (1<<3) /* Sampling time control register bit 3 mask. */ -#define ADC_SAMPVAL3_bp 3 /* Sampling time control register bit 3 position. */ -#define ADC_SAMPVAL4_bm (1<<4) /* Sampling time control register bit 4 mask. */ -#define ADC_SAMPVAL4_bp 4 /* Sampling time control register bit 4 position. */ -#define ADC_SAMPVAL5_bm (1<<5) /* Sampling time control register bit 5 mask. */ -#define ADC_SAMPVAL5_bp 5 /* Sampling time control register bit 5 position. */ - -/* AC - Analog Comparator */ -/* AC.AC0CTRL bit masks and bit positions */ -#define AC_INTMODE_gm 0xC0 /* Interrupt Mode group mask. */ -#define AC_INTMODE_gp 6 /* Interrupt Mode group position. */ -#define AC_INTMODE0_bm (1<<6) /* Interrupt Mode bit 0 mask. */ -#define AC_INTMODE0_bp 6 /* Interrupt Mode bit 0 position. */ -#define AC_INTMODE1_bm (1<<7) /* Interrupt Mode bit 1 mask. */ -#define AC_INTMODE1_bp 7 /* Interrupt Mode bit 1 position. */ - -#define AC_INTLVL_gm 0x30 /* Interrupt Level group mask. */ -#define AC_INTLVL_gp 4 /* Interrupt Level group position. */ -#define AC_INTLVL0_bm (1<<4) /* Interrupt Level bit 0 mask. */ -#define AC_INTLVL0_bp 4 /* Interrupt Level bit 0 position. */ -#define AC_INTLVL1_bm (1<<5) /* Interrupt Level bit 1 mask. */ -#define AC_INTLVL1_bp 5 /* Interrupt Level bit 1 position. */ - -#define AC_HYSMODE_gm 0x06 /* Hysteresis Mode group mask. */ -#define AC_HYSMODE_gp 1 /* Hysteresis Mode group position. */ -#define AC_HYSMODE0_bm (1<<1) /* Hysteresis Mode bit 0 mask. */ -#define AC_HYSMODE0_bp 1 /* Hysteresis Mode bit 0 position. */ -#define AC_HYSMODE1_bm (1<<2) /* Hysteresis Mode bit 1 mask. */ -#define AC_HYSMODE1_bp 2 /* Hysteresis Mode bit 1 position. */ - -#define AC_ENABLE_bm 0x01 /* Enable bit mask. */ -#define AC_ENABLE_bp 0 /* Enable bit position. */ - -/* AC.AC1CTRL bit masks and bit positions */ -/* AC_INTMODE Predefined. */ -/* AC_INTMODE Predefined. */ - -/* AC_INTLVL Predefined. */ -/* AC_INTLVL Predefined. */ - -/* AC_HYSMODE Predefined. */ -/* AC_HYSMODE Predefined. */ - -/* AC_ENABLE Predefined. */ -/* AC_ENABLE Predefined. */ - -/* AC.AC0MUXCTRL bit masks and bit positions */ -#define AC_MUXPOS_gm 0x38 /* MUX Positive Input group mask. */ -#define AC_MUXPOS_gp 3 /* MUX Positive Input group position. */ -#define AC_MUXPOS0_bm (1<<3) /* MUX Positive Input bit 0 mask. */ -#define AC_MUXPOS0_bp 3 /* MUX Positive Input bit 0 position. */ -#define AC_MUXPOS1_bm (1<<4) /* MUX Positive Input bit 1 mask. */ -#define AC_MUXPOS1_bp 4 /* MUX Positive Input bit 1 position. */ -#define AC_MUXPOS2_bm (1<<5) /* MUX Positive Input bit 2 mask. */ -#define AC_MUXPOS2_bp 5 /* MUX Positive Input bit 2 position. */ - -#define AC_MUXNEG_gm 0x07 /* MUX Negative Input group mask. */ -#define AC_MUXNEG_gp 0 /* MUX Negative Input group position. */ -#define AC_MUXNEG0_bm (1<<0) /* MUX Negative Input bit 0 mask. */ -#define AC_MUXNEG0_bp 0 /* MUX Negative Input bit 0 position. */ -#define AC_MUXNEG1_bm (1<<1) /* MUX Negative Input bit 1 mask. */ -#define AC_MUXNEG1_bp 1 /* MUX Negative Input bit 1 position. */ -#define AC_MUXNEG2_bm (1<<2) /* MUX Negative Input bit 2 mask. */ -#define AC_MUXNEG2_bp 2 /* MUX Negative Input bit 2 position. */ - -/* AC.AC1MUXCTRL bit masks and bit positions */ -/* AC_MUXPOS Predefined. */ -/* AC_MUXPOS Predefined. */ - -/* AC_MUXNEG Predefined. */ -/* AC_MUXNEG Predefined. */ - -/* AC.CTRLA bit masks and bit positions */ -#define AC_AC1OUT_bm 0x02 /* Analog Comparator 1 Output Enable bit mask. */ -#define AC_AC1OUT_bp 1 /* Analog Comparator 1 Output Enable bit position. */ - -#define AC_AC0OUT_bm 0x01 /* Analog Comparator 0 Output Enable bit mask. */ -#define AC_AC0OUT_bp 0 /* Analog Comparator 0 Output Enable bit position. */ - -/* AC.CTRLB bit masks and bit positions */ -#define AC_SCALEFAC_gm 0x3F /* VCC Voltage Scaler Factor group mask. */ -#define AC_SCALEFAC_gp 0 /* VCC Voltage Scaler Factor group position. */ -#define AC_SCALEFAC0_bm (1<<0) /* VCC Voltage Scaler Factor bit 0 mask. */ -#define AC_SCALEFAC0_bp 0 /* VCC Voltage Scaler Factor bit 0 position. */ -#define AC_SCALEFAC1_bm (1<<1) /* VCC Voltage Scaler Factor bit 1 mask. */ -#define AC_SCALEFAC1_bp 1 /* VCC Voltage Scaler Factor bit 1 position. */ -#define AC_SCALEFAC2_bm (1<<2) /* VCC Voltage Scaler Factor bit 2 mask. */ -#define AC_SCALEFAC2_bp 2 /* VCC Voltage Scaler Factor bit 2 position. */ -#define AC_SCALEFAC3_bm (1<<3) /* VCC Voltage Scaler Factor bit 3 mask. */ -#define AC_SCALEFAC3_bp 3 /* VCC Voltage Scaler Factor bit 3 position. */ -#define AC_SCALEFAC4_bm (1<<4) /* VCC Voltage Scaler Factor bit 4 mask. */ -#define AC_SCALEFAC4_bp 4 /* VCC Voltage Scaler Factor bit 4 position. */ -#define AC_SCALEFAC5_bm (1<<5) /* VCC Voltage Scaler Factor bit 5 mask. */ -#define AC_SCALEFAC5_bp 5 /* VCC Voltage Scaler Factor bit 5 position. */ - -/* AC.WINCTRL bit masks and bit positions */ -#define AC_WEN_bm 0x10 /* Window Mode Enable bit mask. */ -#define AC_WEN_bp 4 /* Window Mode Enable bit position. */ - -#define AC_WINTMODE_gm 0x0C /* Window Interrupt Mode group mask. */ -#define AC_WINTMODE_gp 2 /* Window Interrupt Mode group position. */ -#define AC_WINTMODE0_bm (1<<2) /* Window Interrupt Mode bit 0 mask. */ -#define AC_WINTMODE0_bp 2 /* Window Interrupt Mode bit 0 position. */ -#define AC_WINTMODE1_bm (1<<3) /* Window Interrupt Mode bit 1 mask. */ -#define AC_WINTMODE1_bp 3 /* Window Interrupt Mode bit 1 position. */ - -#define AC_WINTLVL_gm 0x03 /* Window Interrupt Level group mask. */ -#define AC_WINTLVL_gp 0 /* Window Interrupt Level group position. */ -#define AC_WINTLVL0_bm (1<<0) /* Window Interrupt Level bit 0 mask. */ -#define AC_WINTLVL0_bp 0 /* Window Interrupt Level bit 0 position. */ -#define AC_WINTLVL1_bm (1<<1) /* Window Interrupt Level bit 1 mask. */ -#define AC_WINTLVL1_bp 1 /* Window Interrupt Level bit 1 position. */ - -/* AC.STATUS bit masks and bit positions */ -#define AC_WSTATE_gm 0xC0 /* Window Mode State group mask. */ -#define AC_WSTATE_gp 6 /* Window Mode State group position. */ -#define AC_WSTATE0_bm (1<<6) /* Window Mode State bit 0 mask. */ -#define AC_WSTATE0_bp 6 /* Window Mode State bit 0 position. */ -#define AC_WSTATE1_bm (1<<7) /* Window Mode State bit 1 mask. */ -#define AC_WSTATE1_bp 7 /* Window Mode State bit 1 position. */ - -#define AC_AC1STATE_bm 0x20 /* Analog Comparator 1 State bit mask. */ -#define AC_AC1STATE_bp 5 /* Analog Comparator 1 State bit position. */ - -#define AC_AC0STATE_bm 0x10 /* Analog Comparator 0 State bit mask. */ -#define AC_AC0STATE_bp 4 /* Analog Comparator 0 State bit position. */ - -#define AC_WIF_bm 0x04 /* Window Mode Interrupt Flag bit mask. */ -#define AC_WIF_bp 2 /* Window Mode Interrupt Flag bit position. */ - -#define AC_AC1IF_bm 0x02 /* Analog Comparator 1 Interrupt Flag bit mask. */ -#define AC_AC1IF_bp 1 /* Analog Comparator 1 Interrupt Flag bit position. */ - -#define AC_AC0IF_bm 0x01 /* Analog Comparator 0 Interrupt Flag bit mask. */ -#define AC_AC0IF_bp 0 /* Analog Comparator 0 Interrupt Flag bit position. */ - -/* RTC - Real-Time Counter */ -/* RTC.CTRL bit masks and bit positions */ -#define RTC_PRESCALER_gm 0x07 /* Prescaling Factor group mask. */ -#define RTC_PRESCALER_gp 0 /* Prescaling Factor group position. */ -#define RTC_PRESCALER0_bm (1<<0) /* Prescaling Factor bit 0 mask. */ -#define RTC_PRESCALER0_bp 0 /* Prescaling Factor bit 0 position. */ -#define RTC_PRESCALER1_bm (1<<1) /* Prescaling Factor bit 1 mask. */ -#define RTC_PRESCALER1_bp 1 /* Prescaling Factor bit 1 position. */ -#define RTC_PRESCALER2_bm (1<<2) /* Prescaling Factor bit 2 mask. */ -#define RTC_PRESCALER2_bp 2 /* Prescaling Factor bit 2 position. */ - -/* RTC.STATUS bit masks and bit positions */ -#define RTC_SYNCBUSY_bm 0x01 /* Synchronization Busy Flag bit mask. */ -#define RTC_SYNCBUSY_bp 0 /* Synchronization Busy Flag bit position. */ - -/* RTC.INTCTRL bit masks and bit positions */ -#define RTC_COMPINTLVL_gm 0x0C /* Compare Match Interrupt Level group mask. */ -#define RTC_COMPINTLVL_gp 2 /* Compare Match Interrupt Level group position. */ -#define RTC_COMPINTLVL0_bm (1<<2) /* Compare Match Interrupt Level bit 0 mask. */ -#define RTC_COMPINTLVL0_bp 2 /* Compare Match Interrupt Level bit 0 position. */ -#define RTC_COMPINTLVL1_bm (1<<3) /* Compare Match Interrupt Level bit 1 mask. */ -#define RTC_COMPINTLVL1_bp 3 /* Compare Match Interrupt Level bit 1 position. */ - -#define RTC_OVFINTLVL_gm 0x03 /* Overflow Interrupt Level group mask. */ -#define RTC_OVFINTLVL_gp 0 /* Overflow Interrupt Level group position. */ -#define RTC_OVFINTLVL0_bm (1<<0) /* Overflow Interrupt Level bit 0 mask. */ -#define RTC_OVFINTLVL0_bp 0 /* Overflow Interrupt Level bit 0 position. */ -#define RTC_OVFINTLVL1_bm (1<<1) /* Overflow Interrupt Level bit 1 mask. */ -#define RTC_OVFINTLVL1_bp 1 /* Overflow Interrupt Level bit 1 position. */ - -/* RTC.INTFLAGS bit masks and bit positions */ -#define RTC_COMPIF_bm 0x02 /* Compare Match Interrupt Flag bit mask. */ -#define RTC_COMPIF_bp 1 /* Compare Match Interrupt Flag bit position. */ - -#define RTC_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ -#define RTC_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ - -/* TWI - Two-Wire Interface */ -/* TWI_MASTER.CTRLA bit masks and bit positions */ -#define TWI_MASTER_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ -#define TWI_MASTER_INTLVL_gp 6 /* Interrupt Level group position. */ -#define TWI_MASTER_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ -#define TWI_MASTER_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ -#define TWI_MASTER_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ -#define TWI_MASTER_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ - -#define TWI_MASTER_RIEN_bm 0x20 /* Read Interrupt Enable bit mask. */ -#define TWI_MASTER_RIEN_bp 5 /* Read Interrupt Enable bit position. */ - -#define TWI_MASTER_WIEN_bm 0x10 /* Write Interrupt Enable bit mask. */ -#define TWI_MASTER_WIEN_bp 4 /* Write Interrupt Enable bit position. */ - -#define TWI_MASTER_ENABLE_bm 0x08 /* Enable TWI Master bit mask. */ -#define TWI_MASTER_ENABLE_bp 3 /* Enable TWI Master bit position. */ - -/* TWI_MASTER.CTRLB bit masks and bit positions */ -#define TWI_MASTER_TIMEOUT_gm 0x0C /* Inactive Bus Timeout group mask. */ -#define TWI_MASTER_TIMEOUT_gp 2 /* Inactive Bus Timeout group position. */ -#define TWI_MASTER_TIMEOUT0_bm (1<<2) /* Inactive Bus Timeout bit 0 mask. */ -#define TWI_MASTER_TIMEOUT0_bp 2 /* Inactive Bus Timeout bit 0 position. */ -#define TWI_MASTER_TIMEOUT1_bm (1<<3) /* Inactive Bus Timeout bit 1 mask. */ -#define TWI_MASTER_TIMEOUT1_bp 3 /* Inactive Bus Timeout bit 1 position. */ - -#define TWI_MASTER_QCEN_bm 0x02 /* Quick Command Enable bit mask. */ -#define TWI_MASTER_QCEN_bp 1 /* Quick Command Enable bit position. */ - -#define TWI_MASTER_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ -#define TWI_MASTER_SMEN_bp 0 /* Smart Mode Enable bit position. */ - -/* TWI_MASTER.CTRLC bit masks and bit positions */ -#define TWI_MASTER_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ -#define TWI_MASTER_ACKACT_bp 2 /* Acknowledge Action bit position. */ - -#define TWI_MASTER_CMD_gm 0x03 /* Command group mask. */ -#define TWI_MASTER_CMD_gp 0 /* Command group position. */ -#define TWI_MASTER_CMD0_bm (1<<0) /* Command bit 0 mask. */ -#define TWI_MASTER_CMD0_bp 0 /* Command bit 0 position. */ -#define TWI_MASTER_CMD1_bm (1<<1) /* Command bit 1 mask. */ -#define TWI_MASTER_CMD1_bp 1 /* Command bit 1 position. */ - -/* TWI_MASTER.STATUS bit masks and bit positions */ -#define TWI_MASTER_RIF_bm 0x80 /* Read Interrupt Flag bit mask. */ -#define TWI_MASTER_RIF_bp 7 /* Read Interrupt Flag bit position. */ - -#define TWI_MASTER_WIF_bm 0x40 /* Write Interrupt Flag bit mask. */ -#define TWI_MASTER_WIF_bp 6 /* Write Interrupt Flag bit position. */ - -#define TWI_MASTER_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ -#define TWI_MASTER_CLKHOLD_bp 5 /* Clock Hold bit position. */ - -#define TWI_MASTER_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ -#define TWI_MASTER_RXACK_bp 4 /* Received Acknowledge bit position. */ - -#define TWI_MASTER_ARBLOST_bm 0x08 /* Arbitration Lost bit mask. */ -#define TWI_MASTER_ARBLOST_bp 3 /* Arbitration Lost bit position. */ - -#define TWI_MASTER_BUSERR_bm 0x04 /* Bus Error bit mask. */ -#define TWI_MASTER_BUSERR_bp 2 /* Bus Error bit position. */ - -#define TWI_MASTER_BUSSTATE_gm 0x03 /* Bus State group mask. */ -#define TWI_MASTER_BUSSTATE_gp 0 /* Bus State group position. */ -#define TWI_MASTER_BUSSTATE0_bm (1<<0) /* Bus State bit 0 mask. */ -#define TWI_MASTER_BUSSTATE0_bp 0 /* Bus State bit 0 position. */ -#define TWI_MASTER_BUSSTATE1_bm (1<<1) /* Bus State bit 1 mask. */ -#define TWI_MASTER_BUSSTATE1_bp 1 /* Bus State bit 1 position. */ - -/* TWI_SLAVE.CTRLA bit masks and bit positions */ -#define TWI_SLAVE_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ -#define TWI_SLAVE_INTLVL_gp 6 /* Interrupt Level group position. */ -#define TWI_SLAVE_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ -#define TWI_SLAVE_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ -#define TWI_SLAVE_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ -#define TWI_SLAVE_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ - -#define TWI_SLAVE_DIEN_bm 0x20 /* Data Interrupt Enable bit mask. */ -#define TWI_SLAVE_DIEN_bp 5 /* Data Interrupt Enable bit position. */ - -#define TWI_SLAVE_APIEN_bm 0x10 /* Address/Stop Interrupt Enable bit mask. */ -#define TWI_SLAVE_APIEN_bp 4 /* Address/Stop Interrupt Enable bit position. */ - -#define TWI_SLAVE_ENABLE_bm 0x08 /* Enable TWI Slave bit mask. */ -#define TWI_SLAVE_ENABLE_bp 3 /* Enable TWI Slave bit position. */ - -#define TWI_SLAVE_PIEN_bm 0x04 /* Stop Interrupt Enable bit mask. */ -#define TWI_SLAVE_PIEN_bp 2 /* Stop Interrupt Enable bit position. */ - -#define TWI_SLAVE_PMEN_bm 0x02 /* Promiscuous Mode Enable bit mask. */ -#define TWI_SLAVE_PMEN_bp 1 /* Promiscuous Mode Enable bit position. */ - -#define TWI_SLAVE_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ -#define TWI_SLAVE_SMEN_bp 0 /* Smart Mode Enable bit position. */ - -/* TWI_SLAVE.CTRLB bit masks and bit positions */ -#define TWI_SLAVE_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ -#define TWI_SLAVE_ACKACT_bp 2 /* Acknowledge Action bit position. */ - -#define TWI_SLAVE_CMD_gm 0x03 /* Command group mask. */ -#define TWI_SLAVE_CMD_gp 0 /* Command group position. */ -#define TWI_SLAVE_CMD0_bm (1<<0) /* Command bit 0 mask. */ -#define TWI_SLAVE_CMD0_bp 0 /* Command bit 0 position. */ -#define TWI_SLAVE_CMD1_bm (1<<1) /* Command bit 1 mask. */ -#define TWI_SLAVE_CMD1_bp 1 /* Command bit 1 position. */ - -/* TWI_SLAVE.STATUS bit masks and bit positions */ -#define TWI_SLAVE_DIF_bm 0x80 /* Data Interrupt Flag bit mask. */ -#define TWI_SLAVE_DIF_bp 7 /* Data Interrupt Flag bit position. */ - -#define TWI_SLAVE_APIF_bm 0x40 /* Address/Stop Interrupt Flag bit mask. */ -#define TWI_SLAVE_APIF_bp 6 /* Address/Stop Interrupt Flag bit position. */ - -#define TWI_SLAVE_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ -#define TWI_SLAVE_CLKHOLD_bp 5 /* Clock Hold bit position. */ - -#define TWI_SLAVE_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ -#define TWI_SLAVE_RXACK_bp 4 /* Received Acknowledge bit position. */ - -#define TWI_SLAVE_COLL_bm 0x08 /* Collision bit mask. */ -#define TWI_SLAVE_COLL_bp 3 /* Collision bit position. */ - -#define TWI_SLAVE_BUSERR_bm 0x04 /* Bus Error bit mask. */ -#define TWI_SLAVE_BUSERR_bp 2 /* Bus Error bit position. */ - -#define TWI_SLAVE_DIR_bm 0x02 /* Read/Write Direction bit mask. */ -#define TWI_SLAVE_DIR_bp 1 /* Read/Write Direction bit position. */ - -#define TWI_SLAVE_AP_bm 0x01 /* Slave Address or Stop bit mask. */ -#define TWI_SLAVE_AP_bp 0 /* Slave Address or Stop bit position. */ - -/* TWI_SLAVE.ADDRMASK bit masks and bit positions */ -#define TWI_SLAVE_ADDRMASK_gm 0xFE /* Address Mask group mask. */ -#define TWI_SLAVE_ADDRMASK_gp 1 /* Address Mask group position. */ -#define TWI_SLAVE_ADDRMASK0_bm (1<<1) /* Address Mask bit 0 mask. */ -#define TWI_SLAVE_ADDRMASK0_bp 1 /* Address Mask bit 0 position. */ -#define TWI_SLAVE_ADDRMASK1_bm (1<<2) /* Address Mask bit 1 mask. */ -#define TWI_SLAVE_ADDRMASK1_bp 2 /* Address Mask bit 1 position. */ -#define TWI_SLAVE_ADDRMASK2_bm (1<<3) /* Address Mask bit 2 mask. */ -#define TWI_SLAVE_ADDRMASK2_bp 3 /* Address Mask bit 2 position. */ -#define TWI_SLAVE_ADDRMASK3_bm (1<<4) /* Address Mask bit 3 mask. */ -#define TWI_SLAVE_ADDRMASK3_bp 4 /* Address Mask bit 3 position. */ -#define TWI_SLAVE_ADDRMASK4_bm (1<<5) /* Address Mask bit 4 mask. */ -#define TWI_SLAVE_ADDRMASK4_bp 5 /* Address Mask bit 4 position. */ -#define TWI_SLAVE_ADDRMASK5_bm (1<<6) /* Address Mask bit 5 mask. */ -#define TWI_SLAVE_ADDRMASK5_bp 6 /* Address Mask bit 5 position. */ -#define TWI_SLAVE_ADDRMASK6_bm (1<<7) /* Address Mask bit 6 mask. */ -#define TWI_SLAVE_ADDRMASK6_bp 7 /* Address Mask bit 6 position. */ - -#define TWI_SLAVE_ADDREN_bm 0x01 /* Address Enable bit mask. */ -#define TWI_SLAVE_ADDREN_bp 0 /* Address Enable bit position. */ - -/* TWI.CTRL bit masks and bit positions */ -#define TWI_SDAHOLD_gm 0x06 /* SDA Hold Time Enable group mask. */ -#define TWI_SDAHOLD_gp 1 /* SDA Hold Time Enable group position. */ -#define TWI_SDAHOLD0_bm (1<<1) /* SDA Hold Time Enable bit 0 mask. */ -#define TWI_SDAHOLD0_bp 1 /* SDA Hold Time Enable bit 0 position. */ -#define TWI_SDAHOLD1_bm (1<<2) /* SDA Hold Time Enable bit 1 mask. */ -#define TWI_SDAHOLD1_bp 2 /* SDA Hold Time Enable bit 1 position. */ - -#define TWI_EDIEN_bm 0x01 /* External Driver Interface Enable bit mask. */ -#define TWI_EDIEN_bp 0 /* External Driver Interface Enable bit position. */ - -/* PORT - I/O Port Configuration */ -/* PORT.INTCTRL bit masks and bit positions */ -#define PORT_INT1LVL_gm 0x0C /* Port Interrupt 1 Level group mask. */ -#define PORT_INT1LVL_gp 2 /* Port Interrupt 1 Level group position. */ -#define PORT_INT1LVL0_bm (1<<2) /* Port Interrupt 1 Level bit 0 mask. */ -#define PORT_INT1LVL0_bp 2 /* Port Interrupt 1 Level bit 0 position. */ -#define PORT_INT1LVL1_bm (1<<3) /* Port Interrupt 1 Level bit 1 mask. */ -#define PORT_INT1LVL1_bp 3 /* Port Interrupt 1 Level bit 1 position. */ - -#define PORT_INT0LVL_gm 0x03 /* Port Interrupt 0 Level group mask. */ -#define PORT_INT0LVL_gp 0 /* Port Interrupt 0 Level group position. */ -#define PORT_INT0LVL0_bm (1<<0) /* Port Interrupt 0 Level bit 0 mask. */ -#define PORT_INT0LVL0_bp 0 /* Port Interrupt 0 Level bit 0 position. */ -#define PORT_INT0LVL1_bm (1<<1) /* Port Interrupt 0 Level bit 1 mask. */ -#define PORT_INT0LVL1_bp 1 /* Port Interrupt 0 Level bit 1 position. */ - -/* PORT.INTFLAGS bit masks and bit positions */ -#define PORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ -#define PORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ - -#define PORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ -#define PORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ - -/* PORT.REMAP bit masks and bit positions */ -#define PORT_SPI_bm 0x20 /* SPI bit mask. */ -#define PORT_SPI_bp 5 /* SPI bit position. */ - -#define PORT_USART0_bm 0x10 /* USART0 bit mask. */ -#define PORT_USART0_bp 4 /* USART0 bit position. */ - -#define PORT_TC0D_bm 0x08 /* Timer/Counter 0 Output Compare D bit mask. */ -#define PORT_TC0D_bp 3 /* Timer/Counter 0 Output Compare D bit position. */ - -#define PORT_TC0C_bm 0x04 /* Timer/Counter 0 Output Compare C bit mask. */ -#define PORT_TC0C_bp 2 /* Timer/Counter 0 Output Compare C bit position. */ - -#define PORT_TC0B_bm 0x02 /* Timer/Counter 0 Output Compare B bit mask. */ -#define PORT_TC0B_bp 1 /* Timer/Counter 0 Output Compare B bit position. */ - -#define PORT_TC0A_bm 0x01 /* Timer/Counter 0 Output Compare A bit mask. */ -#define PORT_TC0A_bp 0 /* Timer/Counter 0 Output Compare A bit position. */ - -/* PORT.PIN0CTRL bit masks and bit positions */ -#define PORT_SRLEN_bm 0x80 /* Slew Rate Enable bit mask. */ -#define PORT_SRLEN_bp 7 /* Slew Rate Enable bit position. */ - -#define PORT_INVEN_bm 0x40 /* Inverted I/O Enable bit mask. */ -#define PORT_INVEN_bp 6 /* Inverted I/O Enable bit position. */ - -#define PORT_OPC_gm 0x38 /* Output/Pull Configuration group mask. */ -#define PORT_OPC_gp 3 /* Output/Pull Configuration group position. */ -#define PORT_OPC0_bm (1<<3) /* Output/Pull Configuration bit 0 mask. */ -#define PORT_OPC0_bp 3 /* Output/Pull Configuration bit 0 position. */ -#define PORT_OPC1_bm (1<<4) /* Output/Pull Configuration bit 1 mask. */ -#define PORT_OPC1_bp 4 /* Output/Pull Configuration bit 1 position. */ -#define PORT_OPC2_bm (1<<5) /* Output/Pull Configuration bit 2 mask. */ -#define PORT_OPC2_bp 5 /* Output/Pull Configuration bit 2 position. */ - -#define PORT_ISC_gm 0x07 /* Input/Sense Configuration group mask. */ -#define PORT_ISC_gp 0 /* Input/Sense Configuration group position. */ -#define PORT_ISC0_bm (1<<0) /* Input/Sense Configuration bit 0 mask. */ -#define PORT_ISC0_bp 0 /* Input/Sense Configuration bit 0 position. */ -#define PORT_ISC1_bm (1<<1) /* Input/Sense Configuration bit 1 mask. */ -#define PORT_ISC1_bp 1 /* Input/Sense Configuration bit 1 position. */ -#define PORT_ISC2_bm (1<<2) /* Input/Sense Configuration bit 2 mask. */ -#define PORT_ISC2_bp 2 /* Input/Sense Configuration bit 2 position. */ - -/* PORT.PIN1CTRL bit masks and bit positions */ -/* PORT_SRLEN Predefined. */ -/* PORT_SRLEN Predefined. */ - -/* PORT_INVEN Predefined. */ -/* PORT_INVEN Predefined. */ - -/* PORT_OPC Predefined. */ -/* PORT_OPC Predefined. */ - -/* PORT_ISC Predefined. */ -/* PORT_ISC Predefined. */ - -/* PORT.PIN2CTRL bit masks and bit positions */ -/* PORT_SRLEN Predefined. */ -/* PORT_SRLEN Predefined. */ - -/* PORT_INVEN Predefined. */ -/* PORT_INVEN Predefined. */ - -/* PORT_OPC Predefined. */ -/* PORT_OPC Predefined. */ - -/* PORT_ISC Predefined. */ -/* PORT_ISC Predefined. */ - -/* PORT.PIN3CTRL bit masks and bit positions */ -/* PORT_SRLEN Predefined. */ -/* PORT_SRLEN Predefined. */ - -/* PORT_INVEN Predefined. */ -/* PORT_INVEN Predefined. */ - -/* PORT_OPC Predefined. */ -/* PORT_OPC Predefined. */ - -/* PORT_ISC Predefined. */ -/* PORT_ISC Predefined. */ - -/* PORT.PIN4CTRL bit masks and bit positions */ -/* PORT_SRLEN Predefined. */ -/* PORT_SRLEN Predefined. */ - -/* PORT_INVEN Predefined. */ -/* PORT_INVEN Predefined. */ - -/* PORT_OPC Predefined. */ -/* PORT_OPC Predefined. */ - -/* PORT_ISC Predefined. */ -/* PORT_ISC Predefined. */ - -/* PORT.PIN5CTRL bit masks and bit positions */ -/* PORT_SRLEN Predefined. */ -/* PORT_SRLEN Predefined. */ - -/* PORT_INVEN Predefined. */ -/* PORT_INVEN Predefined. */ - -/* PORT_OPC Predefined. */ -/* PORT_OPC Predefined. */ - -/* PORT_ISC Predefined. */ -/* PORT_ISC Predefined. */ - -/* PORT.PIN6CTRL bit masks and bit positions */ -/* PORT_SRLEN Predefined. */ -/* PORT_SRLEN Predefined. */ - -/* PORT_INVEN Predefined. */ -/* PORT_INVEN Predefined. */ - -/* PORT_OPC Predefined. */ -/* PORT_OPC Predefined. */ - -/* PORT_ISC Predefined. */ -/* PORT_ISC Predefined. */ - -/* PORT.PIN7CTRL bit masks and bit positions */ -/* PORT_SRLEN Predefined. */ -/* PORT_SRLEN Predefined. */ - -/* PORT_INVEN Predefined. */ -/* PORT_INVEN Predefined. */ - -/* PORT_OPC Predefined. */ -/* PORT_OPC Predefined. */ - -/* PORT_ISC Predefined. */ -/* PORT_ISC Predefined. */ - -/* TC - 16-bit Timer/Counter With PWM */ -/* TC0.CTRLA bit masks and bit positions */ -#define TC0_CLKSEL_gm 0x0F /* Clock Selection group mask. */ -#define TC0_CLKSEL_gp 0 /* Clock Selection group position. */ -#define TC0_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ -#define TC0_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ -#define TC0_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ -#define TC0_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ -#define TC0_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ -#define TC0_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ -#define TC0_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ -#define TC0_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ - -/* TC0.CTRLB bit masks and bit positions */ -#define TC0_CCDEN_bm 0x80 /* Compare or Capture D Enable bit mask. */ -#define TC0_CCDEN_bp 7 /* Compare or Capture D Enable bit position. */ - -#define TC0_CCCEN_bm 0x40 /* Compare or Capture C Enable bit mask. */ -#define TC0_CCCEN_bp 6 /* Compare or Capture C Enable bit position. */ - -#define TC0_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ -#define TC0_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ - -#define TC0_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ -#define TC0_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ - -#define TC0_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ -#define TC0_WGMODE_gp 0 /* Waveform generation mode group position. */ -#define TC0_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ -#define TC0_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ -#define TC0_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ -#define TC0_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ -#define TC0_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ -#define TC0_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ - -/* TC0.CTRLC bit masks and bit positions */ -#define TC0_CMPD_bm 0x08 /* Compare D Output Value bit mask. */ -#define TC0_CMPD_bp 3 /* Compare D Output Value bit position. */ - -#define TC0_CMPC_bm 0x04 /* Compare C Output Value bit mask. */ -#define TC0_CMPC_bp 2 /* Compare C Output Value bit position. */ - -#define TC0_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ -#define TC0_CMPB_bp 1 /* Compare B Output Value bit position. */ - -#define TC0_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ -#define TC0_CMPA_bp 0 /* Compare A Output Value bit position. */ - -/* TC0.CTRLD bit masks and bit positions */ -#define TC0_EVACT_gm 0xE0 /* Event Action group mask. */ -#define TC0_EVACT_gp 5 /* Event Action group position. */ -#define TC0_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ -#define TC0_EVACT0_bp 5 /* Event Action bit 0 position. */ -#define TC0_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ -#define TC0_EVACT1_bp 6 /* Event Action bit 1 position. */ -#define TC0_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ -#define TC0_EVACT2_bp 7 /* Event Action bit 2 position. */ - -#define TC0_EVDLY_bm 0x10 /* Event Delay bit mask. */ -#define TC0_EVDLY_bp 4 /* Event Delay bit position. */ - -#define TC0_EVSEL_gm 0x0F /* Event Source Select group mask. */ -#define TC0_EVSEL_gp 0 /* Event Source Select group position. */ -#define TC0_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ -#define TC0_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ -#define TC0_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ -#define TC0_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ -#define TC0_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ -#define TC0_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ -#define TC0_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ -#define TC0_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ - -/* TC0.CTRLE bit masks and bit positions */ -#define TC0_BYTEM_gm 0x03 /* Byte Mode group mask. */ -#define TC0_BYTEM_gp 0 /* Byte Mode group position. */ -#define TC0_BYTEM0_bm (1<<0) /* Byte Mode bit 0 mask. */ -#define TC0_BYTEM0_bp 0 /* Byte Mode bit 0 position. */ -#define TC0_BYTEM1_bm (1<<1) /* Byte Mode bit 1 mask. */ -#define TC0_BYTEM1_bp 1 /* Byte Mode bit 1 position. */ - -/* TC0.INTCTRLA bit masks and bit positions */ -#define TC0_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ -#define TC0_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ -#define TC0_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ -#define TC0_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ -#define TC0_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ -#define TC0_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ - -#define TC0_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ -#define TC0_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ -#define TC0_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ -#define TC0_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ -#define TC0_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ -#define TC0_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ - -/* TC0.INTCTRLB bit masks and bit positions */ -#define TC0_CCDINTLVL_gm 0xC0 /* Compare or Capture D Interrupt Level group mask. */ -#define TC0_CCDINTLVL_gp 6 /* Compare or Capture D Interrupt Level group position. */ -#define TC0_CCDINTLVL0_bm (1<<6) /* Compare or Capture D Interrupt Level bit 0 mask. */ -#define TC0_CCDINTLVL0_bp 6 /* Compare or Capture D Interrupt Level bit 0 position. */ -#define TC0_CCDINTLVL1_bm (1<<7) /* Compare or Capture D Interrupt Level bit 1 mask. */ -#define TC0_CCDINTLVL1_bp 7 /* Compare or Capture D Interrupt Level bit 1 position. */ - -#define TC0_CCCINTLVL_gm 0x30 /* Compare or Capture C Interrupt Level group mask. */ -#define TC0_CCCINTLVL_gp 4 /* Compare or Capture C Interrupt Level group position. */ -#define TC0_CCCINTLVL0_bm (1<<4) /* Compare or Capture C Interrupt Level bit 0 mask. */ -#define TC0_CCCINTLVL0_bp 4 /* Compare or Capture C Interrupt Level bit 0 position. */ -#define TC0_CCCINTLVL1_bm (1<<5) /* Compare or Capture C Interrupt Level bit 1 mask. */ -#define TC0_CCCINTLVL1_bp 5 /* Compare or Capture C Interrupt Level bit 1 position. */ - -#define TC0_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ -#define TC0_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ -#define TC0_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ -#define TC0_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ -#define TC0_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ -#define TC0_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ - -#define TC0_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ -#define TC0_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ -#define TC0_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ -#define TC0_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ -#define TC0_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ -#define TC0_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ - -/* TC0.CTRLFCLR bit masks and bit positions */ -#define TC0_CMD_gm 0x0C /* Command group mask. */ -#define TC0_CMD_gp 2 /* Command group position. */ -#define TC0_CMD0_bm (1<<2) /* Command bit 0 mask. */ -#define TC0_CMD0_bp 2 /* Command bit 0 position. */ -#define TC0_CMD1_bm (1<<3) /* Command bit 1 mask. */ -#define TC0_CMD1_bp 3 /* Command bit 1 position. */ - -#define TC0_LUPD_bm 0x02 /* Lock Update bit mask. */ -#define TC0_LUPD_bp 1 /* Lock Update bit position. */ - -#define TC0_DIR_bm 0x01 /* Direction bit mask. */ -#define TC0_DIR_bp 0 /* Direction bit position. */ - -/* TC0.CTRLFSET bit masks and bit positions */ -/* TC0_CMD Predefined. */ -/* TC0_CMD Predefined. */ - -/* TC0_LUPD Predefined. */ -/* TC0_LUPD Predefined. */ - -/* TC0_DIR Predefined. */ -/* TC0_DIR Predefined. */ - -/* TC0.CTRLGCLR bit masks and bit positions */ -#define TC0_CCDBV_bm 0x10 /* Compare or Capture D Buffer Valid bit mask. */ -#define TC0_CCDBV_bp 4 /* Compare or Capture D Buffer Valid bit position. */ - -#define TC0_CCCBV_bm 0x08 /* Compare or Capture C Buffer Valid bit mask. */ -#define TC0_CCCBV_bp 3 /* Compare or Capture C Buffer Valid bit position. */ - -#define TC0_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ -#define TC0_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ - -#define TC0_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ -#define TC0_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ - -#define TC0_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ -#define TC0_PERBV_bp 0 /* Period Buffer Valid bit position. */ - -/* TC0.CTRLGSET bit masks and bit positions */ -/* TC0_CCDBV Predefined. */ -/* TC0_CCDBV Predefined. */ - -/* TC0_CCCBV Predefined. */ -/* TC0_CCCBV Predefined. */ - -/* TC0_CCBBV Predefined. */ -/* TC0_CCBBV Predefined. */ - -/* TC0_CCABV Predefined. */ -/* TC0_CCABV Predefined. */ - -/* TC0_PERBV Predefined. */ -/* TC0_PERBV Predefined. */ - -/* TC0.INTFLAGS bit masks and bit positions */ -#define TC0_CCDIF_bm 0x80 /* Compare or Capture D Interrupt Flag bit mask. */ -#define TC0_CCDIF_bp 7 /* Compare or Capture D Interrupt Flag bit position. */ - -#define TC0_CCCIF_bm 0x40 /* Compare or Capture C Interrupt Flag bit mask. */ -#define TC0_CCCIF_bp 6 /* Compare or Capture C Interrupt Flag bit position. */ - -#define TC0_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ -#define TC0_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ - -#define TC0_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ -#define TC0_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ - -#define TC0_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ -#define TC0_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ - -#define TC0_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ -#define TC0_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ - -/* TC1.CTRLA bit masks and bit positions */ -#define TC1_CLKSEL_gm 0x0F /* Clock Selection group mask. */ -#define TC1_CLKSEL_gp 0 /* Clock Selection group position. */ -#define TC1_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ -#define TC1_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ -#define TC1_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ -#define TC1_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ -#define TC1_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ -#define TC1_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ -#define TC1_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ -#define TC1_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ - -/* TC1.CTRLB bit masks and bit positions */ -#define TC1_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ -#define TC1_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ - -#define TC1_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ -#define TC1_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ - -#define TC1_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ -#define TC1_WGMODE_gp 0 /* Waveform generation mode group position. */ -#define TC1_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ -#define TC1_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ -#define TC1_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ -#define TC1_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ -#define TC1_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ -#define TC1_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ - -/* TC1.CTRLC bit masks and bit positions */ -#define TC1_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ -#define TC1_CMPB_bp 1 /* Compare B Output Value bit position. */ - -#define TC1_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ -#define TC1_CMPA_bp 0 /* Compare A Output Value bit position. */ - -/* TC1.CTRLD bit masks and bit positions */ -#define TC1_EVACT_gm 0xE0 /* Event Action group mask. */ -#define TC1_EVACT_gp 5 /* Event Action group position. */ -#define TC1_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ -#define TC1_EVACT0_bp 5 /* Event Action bit 0 position. */ -#define TC1_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ -#define TC1_EVACT1_bp 6 /* Event Action bit 1 position. */ -#define TC1_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ -#define TC1_EVACT2_bp 7 /* Event Action bit 2 position. */ - -#define TC1_EVDLY_bm 0x10 /* Event Delay bit mask. */ -#define TC1_EVDLY_bp 4 /* Event Delay bit position. */ - -#define TC1_EVSEL_gm 0x0F /* Event Source Select group mask. */ -#define TC1_EVSEL_gp 0 /* Event Source Select group position. */ -#define TC1_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ -#define TC1_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ -#define TC1_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ -#define TC1_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ -#define TC1_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ -#define TC1_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ -#define TC1_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ -#define TC1_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ - -/* TC1.CTRLE bit masks and bit positions */ -#define TC1_BYTEM_bm 0x01 /* Byte Mode bit mask. */ -#define TC1_BYTEM_bp 0 /* Byte Mode bit position. */ - -/* TC1.INTCTRLA bit masks and bit positions */ -#define TC1_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ -#define TC1_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ -#define TC1_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ -#define TC1_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ -#define TC1_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ -#define TC1_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ - -#define TC1_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ -#define TC1_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ -#define TC1_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ -#define TC1_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ -#define TC1_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ -#define TC1_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ - -/* TC1.INTCTRLB bit masks and bit positions */ -#define TC1_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ -#define TC1_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ -#define TC1_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ -#define TC1_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ -#define TC1_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ -#define TC1_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ - -#define TC1_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ -#define TC1_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ -#define TC1_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ -#define TC1_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ -#define TC1_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ -#define TC1_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ - -/* TC1.CTRLFCLR bit masks and bit positions */ -#define TC1_CMD_gm 0x0C /* Command group mask. */ -#define TC1_CMD_gp 2 /* Command group position. */ -#define TC1_CMD0_bm (1<<2) /* Command bit 0 mask. */ -#define TC1_CMD0_bp 2 /* Command bit 0 position. */ -#define TC1_CMD1_bm (1<<3) /* Command bit 1 mask. */ -#define TC1_CMD1_bp 3 /* Command bit 1 position. */ - -#define TC1_LUPD_bm 0x02 /* Lock Update bit mask. */ -#define TC1_LUPD_bp 1 /* Lock Update bit position. */ - -#define TC1_DIR_bm 0x01 /* Direction bit mask. */ -#define TC1_DIR_bp 0 /* Direction bit position. */ - -/* TC1.CTRLFSET bit masks and bit positions */ -/* TC1_CMD Predefined. */ -/* TC1_CMD Predefined. */ - -/* TC1_LUPD Predefined. */ -/* TC1_LUPD Predefined. */ - -/* TC1_DIR Predefined. */ -/* TC1_DIR Predefined. */ - -/* TC1.CTRLGCLR bit masks and bit positions */ -#define TC1_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ -#define TC1_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ - -#define TC1_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ -#define TC1_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ - -#define TC1_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ -#define TC1_PERBV_bp 0 /* Period Buffer Valid bit position. */ - -/* TC1.CTRLGSET bit masks and bit positions */ -/* TC1_CCBBV Predefined. */ -/* TC1_CCBBV Predefined. */ - -/* TC1_CCABV Predefined. */ -/* TC1_CCABV Predefined. */ - -/* TC1_PERBV Predefined. */ -/* TC1_PERBV Predefined. */ - -/* TC1.INTFLAGS bit masks and bit positions */ -#define TC1_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ -#define TC1_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ - -#define TC1_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ -#define TC1_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ - -#define TC1_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ -#define TC1_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ - -#define TC1_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ -#define TC1_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ - -/* TC2 - 16-bit Timer/Counter type 2 */ -/* TC2.CTRLA bit masks and bit positions */ -#define TC2_CLKSEL_gm 0x0F /* Clock Selection group mask. */ -#define TC2_CLKSEL_gp 0 /* Clock Selection group position. */ -#define TC2_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ -#define TC2_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ -#define TC2_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ -#define TC2_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ -#define TC2_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ -#define TC2_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ -#define TC2_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ -#define TC2_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ - -/* TC2.CTRLB bit masks and bit positions */ -#define TC2_HCMPDEN_bm 0x80 /* High Byte Compare D Enable bit mask. */ -#define TC2_HCMPDEN_bp 7 /* High Byte Compare D Enable bit position. */ - -#define TC2_HCMPCEN_bm 0x40 /* High Byte Compare C Enable bit mask. */ -#define TC2_HCMPCEN_bp 6 /* High Byte Compare C Enable bit position. */ - -#define TC2_HCMPBEN_bm 0x20 /* High Byte Compare B Enable bit mask. */ -#define TC2_HCMPBEN_bp 5 /* High Byte Compare B Enable bit position. */ - -#define TC2_HCMPAEN_bm 0x10 /* High Byte Compare A Enable bit mask. */ -#define TC2_HCMPAEN_bp 4 /* High Byte Compare A Enable bit position. */ - -#define TC2_LCMPDEN_bm 0x08 /* Low Byte Compare D Enable bit mask. */ -#define TC2_LCMPDEN_bp 3 /* Low Byte Compare D Enable bit position. */ - -#define TC2_LCMPCEN_bm 0x04 /* Low Byte Compare C Enable bit mask. */ -#define TC2_LCMPCEN_bp 2 /* Low Byte Compare C Enable bit position. */ - -#define TC2_LCMPBEN_bm 0x02 /* Low Byte Compare B Enable bit mask. */ -#define TC2_LCMPBEN_bp 1 /* Low Byte Compare B Enable bit position. */ - -#define TC2_LCMPAEN_bm 0x01 /* Low Byte Compare A Enable bit mask. */ -#define TC2_LCMPAEN_bp 0 /* Low Byte Compare A Enable bit position. */ - -/* TC2.CTRLC bit masks and bit positions */ -#define TC2_HCMPD_bm 0x80 /* High Byte Compare D Output Value bit mask. */ -#define TC2_HCMPD_bp 7 /* High Byte Compare D Output Value bit position. */ - -#define TC2_HCMPC_bm 0x40 /* High Byte Compare C Output Value bit mask. */ -#define TC2_HCMPC_bp 6 /* High Byte Compare C Output Value bit position. */ - -#define TC2_HCMPB_bm 0x20 /* High Byte Compare B Output Value bit mask. */ -#define TC2_HCMPB_bp 5 /* High Byte Compare B Output Value bit position. */ - -#define TC2_HCMPA_bm 0x10 /* High Byte Compare A Output Value bit mask. */ -#define TC2_HCMPA_bp 4 /* High Byte Compare A Output Value bit position. */ - -#define TC2_LCMPD_bm 0x08 /* Low Byte Compare D Output Value bit mask. */ -#define TC2_LCMPD_bp 3 /* Low Byte Compare D Output Value bit position. */ - -#define TC2_LCMPC_bm 0x04 /* Low Byte Compare C Output Value bit mask. */ -#define TC2_LCMPC_bp 2 /* Low Byte Compare C Output Value bit position. */ - -#define TC2_LCMPB_bm 0x02 /* Low Byte Compare B Output Value bit mask. */ -#define TC2_LCMPB_bp 1 /* Low Byte Compare B Output Value bit position. */ - -#define TC2_LCMPA_bm 0x01 /* Low Byte Compare A Output Value bit mask. */ -#define TC2_LCMPA_bp 0 /* Low Byte Compare A Output Value bit position. */ - -/* TC2.CTRLE bit masks and bit positions */ -#define TC2_BYTEM_gm 0x03 /* Byte Mode group mask. */ -#define TC2_BYTEM_gp 0 /* Byte Mode group position. */ -#define TC2_BYTEM0_bm (1<<0) /* Byte Mode bit 0 mask. */ -#define TC2_BYTEM0_bp 0 /* Byte Mode bit 0 position. */ -#define TC2_BYTEM1_bm (1<<1) /* Byte Mode bit 1 mask. */ -#define TC2_BYTEM1_bp 1 /* Byte Mode bit 1 position. */ - -/* TC2.INTCTRLA bit masks and bit positions */ -#define TC2_HUNFINTLVL_gm 0x0C /* High Byte Underflow Interrupt Level group mask. */ -#define TC2_HUNFINTLVL_gp 2 /* High Byte Underflow Interrupt Level group position. */ -#define TC2_HUNFINTLVL0_bm (1<<2) /* High Byte Underflow Interrupt Level bit 0 mask. */ -#define TC2_HUNFINTLVL0_bp 2 /* High Byte Underflow Interrupt Level bit 0 position. */ -#define TC2_HUNFINTLVL1_bm (1<<3) /* High Byte Underflow Interrupt Level bit 1 mask. */ -#define TC2_HUNFINTLVL1_bp 3 /* High Byte Underflow Interrupt Level bit 1 position. */ - -#define TC2_LUNFINTLVL_gm 0x03 /* Low Byte Underflow interrupt level group mask. */ -#define TC2_LUNFINTLVL_gp 0 /* Low Byte Underflow interrupt level group position. */ -#define TC2_LUNFINTLVL0_bm (1<<0) /* Low Byte Underflow interrupt level bit 0 mask. */ -#define TC2_LUNFINTLVL0_bp 0 /* Low Byte Underflow interrupt level bit 0 position. */ -#define TC2_LUNFINTLVL1_bm (1<<1) /* Low Byte Underflow interrupt level bit 1 mask. */ -#define TC2_LUNFINTLVL1_bp 1 /* Low Byte Underflow interrupt level bit 1 position. */ - -/* TC2.INTCTRLB bit masks and bit positions */ -#define TC2_LCMPDINTLVL_gm 0xC0 /* Low Byte Compare D Interrupt Level group mask. */ -#define TC2_LCMPDINTLVL_gp 6 /* Low Byte Compare D Interrupt Level group position. */ -#define TC2_LCMPDINTLVL0_bm (1<<6) /* Low Byte Compare D Interrupt Level bit 0 mask. */ -#define TC2_LCMPDINTLVL0_bp 6 /* Low Byte Compare D Interrupt Level bit 0 position. */ -#define TC2_LCMPDINTLVL1_bm (1<<7) /* Low Byte Compare D Interrupt Level bit 1 mask. */ -#define TC2_LCMPDINTLVL1_bp 7 /* Low Byte Compare D Interrupt Level bit 1 position. */ - -#define TC2_LCMPCINTLVL_gm 0x30 /* Low Byte Compare C Interrupt Level group mask. */ -#define TC2_LCMPCINTLVL_gp 4 /* Low Byte Compare C Interrupt Level group position. */ -#define TC2_LCMPCINTLVL0_bm (1<<4) /* Low Byte Compare C Interrupt Level bit 0 mask. */ -#define TC2_LCMPCINTLVL0_bp 4 /* Low Byte Compare C Interrupt Level bit 0 position. */ -#define TC2_LCMPCINTLVL1_bm (1<<5) /* Low Byte Compare C Interrupt Level bit 1 mask. */ -#define TC2_LCMPCINTLVL1_bp 5 /* Low Byte Compare C Interrupt Level bit 1 position. */ - -#define TC2_LCMPBINTLVL_gm 0x0C /* Low Byte Compare B Interrupt Level group mask. */ -#define TC2_LCMPBINTLVL_gp 2 /* Low Byte Compare B Interrupt Level group position. */ -#define TC2_LCMPBINTLVL0_bm (1<<2) /* Low Byte Compare B Interrupt Level bit 0 mask. */ -#define TC2_LCMPBINTLVL0_bp 2 /* Low Byte Compare B Interrupt Level bit 0 position. */ -#define TC2_LCMPBINTLVL1_bm (1<<3) /* Low Byte Compare B Interrupt Level bit 1 mask. */ -#define TC2_LCMPBINTLVL1_bp 3 /* Low Byte Compare B Interrupt Level bit 1 position. */ - -#define TC2_LCMPAINTLVL_gm 0x03 /* Low Byte Compare A Interrupt Level group mask. */ -#define TC2_LCMPAINTLVL_gp 0 /* Low Byte Compare A Interrupt Level group position. */ -#define TC2_LCMPAINTLVL0_bm (1<<0) /* Low Byte Compare A Interrupt Level bit 0 mask. */ -#define TC2_LCMPAINTLVL0_bp 0 /* Low Byte Compare A Interrupt Level bit 0 position. */ -#define TC2_LCMPAINTLVL1_bm (1<<1) /* Low Byte Compare A Interrupt Level bit 1 mask. */ -#define TC2_LCMPAINTLVL1_bp 1 /* Low Byte Compare A Interrupt Level bit 1 position. */ - -/* TC2.CTRLF bit masks and bit positions */ -#define TC2_CMD_gm 0x0C /* Command group mask. */ -#define TC2_CMD_gp 2 /* Command group position. */ -#define TC2_CMD0_bm (1<<2) /* Command bit 0 mask. */ -#define TC2_CMD0_bp 2 /* Command bit 0 position. */ -#define TC2_CMD1_bm (1<<3) /* Command bit 1 mask. */ -#define TC2_CMD1_bp 3 /* Command bit 1 position. */ - -#define TC2_CMDEN_gm 0x03 /* Command Enable group mask. */ -#define TC2_CMDEN_gp 0 /* Command Enable group position. */ -#define TC2_CMDEN0_bm (1<<0) /* Command Enable bit 0 mask. */ -#define TC2_CMDEN0_bp 0 /* Command Enable bit 0 position. */ -#define TC2_CMDEN1_bm (1<<1) /* Command Enable bit 1 mask. */ -#define TC2_CMDEN1_bp 1 /* Command Enable bit 1 position. */ - -/* TC2.INTFLAGS bit masks and bit positions */ -#define TC2_LCMPDIF_bm 0x80 /* Low Byte Compare D Interrupt Flag bit mask. */ -#define TC2_LCMPDIF_bp 7 /* Low Byte Compare D Interrupt Flag bit position. */ - -#define TC2_LCMPCIF_bm 0x40 /* Low Byte Compare C Interrupt Flag bit mask. */ -#define TC2_LCMPCIF_bp 6 /* Low Byte Compare C Interrupt Flag bit position. */ - -#define TC2_LCMPBIF_bm 0x20 /* Low Byte Compare B Interrupt Flag bit mask. */ -#define TC2_LCMPBIF_bp 5 /* Low Byte Compare B Interrupt Flag bit position. */ - -#define TC2_LCMPAIF_bm 0x10 /* Low Byte Compare A Interrupt Flag bit mask. */ -#define TC2_LCMPAIF_bp 4 /* Low Byte Compare A Interrupt Flag bit position. */ - -#define TC2_HUNFIF_bm 0x02 /* High Byte Underflow Interrupt Flag bit mask. */ -#define TC2_HUNFIF_bp 1 /* High Byte Underflow Interrupt Flag bit position. */ - -#define TC2_LUNFIF_bm 0x01 /* Low Byte Underflow Interrupt Flag bit mask. */ -#define TC2_LUNFIF_bp 0 /* Low Byte Underflow Interrupt Flag bit position. */ - -/* AWEX - Timer/Counter Advanced Waveform Extension */ -/* AWEX.CTRL bit masks and bit positions */ -#define AWEX_PGM_bm 0x20 /* Pattern Generation Mode bit mask. */ -#define AWEX_PGM_bp 5 /* Pattern Generation Mode bit position. */ - -#define AWEX_CWCM_bm 0x10 /* Common Waveform Channel Mode bit mask. */ -#define AWEX_CWCM_bp 4 /* Common Waveform Channel Mode bit position. */ - -#define AWEX_DTICCDEN_bm 0x08 /* Dead Time Insertion Compare Channel D Enable bit mask. */ -#define AWEX_DTICCDEN_bp 3 /* Dead Time Insertion Compare Channel D Enable bit position. */ - -#define AWEX_DTICCCEN_bm 0x04 /* Dead Time Insertion Compare Channel C Enable bit mask. */ -#define AWEX_DTICCCEN_bp 2 /* Dead Time Insertion Compare Channel C Enable bit position. */ - -#define AWEX_DTICCBEN_bm 0x02 /* Dead Time Insertion Compare Channel B Enable bit mask. */ -#define AWEX_DTICCBEN_bp 1 /* Dead Time Insertion Compare Channel B Enable bit position. */ - -#define AWEX_DTICCAEN_bm 0x01 /* Dead Time Insertion Compare Channel A Enable bit mask. */ -#define AWEX_DTICCAEN_bp 0 /* Dead Time Insertion Compare Channel A Enable bit position. */ - -/* AWEX.FDCTRL bit masks and bit positions */ -#define AWEX_FDDBD_bm 0x10 /* Fault Detect on Disable Break Disable bit mask. */ -#define AWEX_FDDBD_bp 4 /* Fault Detect on Disable Break Disable bit position. */ - -#define AWEX_FDMODE_bm 0x04 /* Fault Detect Mode bit mask. */ -#define AWEX_FDMODE_bp 2 /* Fault Detect Mode bit position. */ - -#define AWEX_FDACT_gm 0x03 /* Fault Detect Action group mask. */ -#define AWEX_FDACT_gp 0 /* Fault Detect Action group position. */ -#define AWEX_FDACT0_bm (1<<0) /* Fault Detect Action bit 0 mask. */ -#define AWEX_FDACT0_bp 0 /* Fault Detect Action bit 0 position. */ -#define AWEX_FDACT1_bm (1<<1) /* Fault Detect Action bit 1 mask. */ -#define AWEX_FDACT1_bp 1 /* Fault Detect Action bit 1 position. */ - -/* AWEX.STATUS bit masks and bit positions */ -#define AWEX_FDF_bm 0x04 /* Fault Detect Flag bit mask. */ -#define AWEX_FDF_bp 2 /* Fault Detect Flag bit position. */ - -#define AWEX_DTHSBUFV_bm 0x02 /* Dead Time High Side Buffer Valid bit mask. */ -#define AWEX_DTHSBUFV_bp 1 /* Dead Time High Side Buffer Valid bit position. */ - -#define AWEX_DTLSBUFV_bm 0x01 /* Dead Time Low Side Buffer Valid bit mask. */ -#define AWEX_DTLSBUFV_bp 0 /* Dead Time Low Side Buffer Valid bit position. */ - -/* AWEX.STATUSSET bit masks and bit positions */ -/* AWEX_FDF Predefined. */ -/* AWEX_FDF Predefined. */ - -/* AWEX_DTHSBUFV Predefined. */ -/* AWEX_DTHSBUFV Predefined. */ - -/* AWEX_DTLSBUFV Predefined. */ -/* AWEX_DTLSBUFV Predefined. */ - -/* HIRES - Timer/Counter High-Resolution Extension */ -/* HIRES.CTRLA bit masks and bit positions */ -#define HIRES_HREN_gm 0x03 /* High Resolution Enable group mask. */ -#define HIRES_HREN_gp 0 /* High Resolution Enable group position. */ -#define HIRES_HREN0_bm (1<<0) /* High Resolution Enable bit 0 mask. */ -#define HIRES_HREN0_bp 0 /* High Resolution Enable bit 0 position. */ -#define HIRES_HREN1_bm (1<<1) /* High Resolution Enable bit 1 mask. */ -#define HIRES_HREN1_bp 1 /* High Resolution Enable bit 1 position. */ - -/* USART - Universal Asynchronous Receiver-Transmitter */ -/* USART.STATUS bit masks and bit positions */ -#define USART_RXCIF_bm 0x80 /* Receive Interrupt Flag bit mask. */ -#define USART_RXCIF_bp 7 /* Receive Interrupt Flag bit position. */ - -#define USART_TXCIF_bm 0x40 /* Transmit Interrupt Flag bit mask. */ -#define USART_TXCIF_bp 6 /* Transmit Interrupt Flag bit position. */ - -#define USART_DREIF_bm 0x20 /* Data Register Empty Flag bit mask. */ -#define USART_DREIF_bp 5 /* Data Register Empty Flag bit position. */ - -#define USART_FERR_bm 0x10 /* Frame Error bit mask. */ -#define USART_FERR_bp 4 /* Frame Error bit position. */ - -#define USART_BUFOVF_bm 0x08 /* Buffer Overflow bit mask. */ -#define USART_BUFOVF_bp 3 /* Buffer Overflow bit position. */ - -#define USART_PERR_bm 0x04 /* Parity Error bit mask. */ -#define USART_PERR_bp 2 /* Parity Error bit position. */ - -#define USART_RXB8_bm 0x01 /* Receive Bit 8 bit mask. */ -#define USART_RXB8_bp 0 /* Receive Bit 8 bit position. */ - -/* USART.CTRLA bit masks and bit positions */ -#define USART_RXCINTLVL_gm 0x30 /* Receive Interrupt Level group mask. */ -#define USART_RXCINTLVL_gp 4 /* Receive Interrupt Level group position. */ -#define USART_RXCINTLVL0_bm (1<<4) /* Receive Interrupt Level bit 0 mask. */ -#define USART_RXCINTLVL0_bp 4 /* Receive Interrupt Level bit 0 position. */ -#define USART_RXCINTLVL1_bm (1<<5) /* Receive Interrupt Level bit 1 mask. */ -#define USART_RXCINTLVL1_bp 5 /* Receive Interrupt Level bit 1 position. */ - -#define USART_TXCINTLVL_gm 0x0C /* Transmit Interrupt Level group mask. */ -#define USART_TXCINTLVL_gp 2 /* Transmit Interrupt Level group position. */ -#define USART_TXCINTLVL0_bm (1<<2) /* Transmit Interrupt Level bit 0 mask. */ -#define USART_TXCINTLVL0_bp 2 /* Transmit Interrupt Level bit 0 position. */ -#define USART_TXCINTLVL1_bm (1<<3) /* Transmit Interrupt Level bit 1 mask. */ -#define USART_TXCINTLVL1_bp 3 /* Transmit Interrupt Level bit 1 position. */ - -#define USART_DREINTLVL_gm 0x03 /* Data Register Empty Interrupt Level group mask. */ -#define USART_DREINTLVL_gp 0 /* Data Register Empty Interrupt Level group position. */ -#define USART_DREINTLVL0_bm (1<<0) /* Data Register Empty Interrupt Level bit 0 mask. */ -#define USART_DREINTLVL0_bp 0 /* Data Register Empty Interrupt Level bit 0 position. */ -#define USART_DREINTLVL1_bm (1<<1) /* Data Register Empty Interrupt Level bit 1 mask. */ -#define USART_DREINTLVL1_bp 1 /* Data Register Empty Interrupt Level bit 1 position. */ - -/* USART.CTRLB bit masks and bit positions */ -#define USART_RXEN_bm 0x10 /* Receiver Enable bit mask. */ -#define USART_RXEN_bp 4 /* Receiver Enable bit position. */ - -#define USART_TXEN_bm 0x08 /* Transmitter Enable bit mask. */ -#define USART_TXEN_bp 3 /* Transmitter Enable bit position. */ - -#define USART_CLK2X_bm 0x04 /* Double transmission speed bit mask. */ -#define USART_CLK2X_bp 2 /* Double transmission speed bit position. */ - -#define USART_MPCM_bm 0x02 /* Multi-processor Communication Mode bit mask. */ -#define USART_MPCM_bp 1 /* Multi-processor Communication Mode bit position. */ - -#define USART_TXB8_bm 0x01 /* Transmit bit 8 bit mask. */ -#define USART_TXB8_bp 0 /* Transmit bit 8 bit position. */ - -/* USART.CTRLC bit masks and bit positions */ -#define USART_CMODE_gm 0xC0 /* Communication Mode group mask. */ -#define USART_CMODE_gp 6 /* Communication Mode group position. */ -#define USART_CMODE0_bm (1<<6) /* Communication Mode bit 0 mask. */ -#define USART_CMODE0_bp 6 /* Communication Mode bit 0 position. */ -#define USART_CMODE1_bm (1<<7) /* Communication Mode bit 1 mask. */ -#define USART_CMODE1_bp 7 /* Communication Mode bit 1 position. */ - -#define USART_PMODE_gm 0x30 /* Parity Mode group mask. */ -#define USART_PMODE_gp 4 /* Parity Mode group position. */ -#define USART_PMODE0_bm (1<<4) /* Parity Mode bit 0 mask. */ -#define USART_PMODE0_bp 4 /* Parity Mode bit 0 position. */ -#define USART_PMODE1_bm (1<<5) /* Parity Mode bit 1 mask. */ -#define USART_PMODE1_bp 5 /* Parity Mode bit 1 position. */ - -#define USART_SBMODE_bm 0x08 /* Stop Bit Mode bit mask. */ -#define USART_SBMODE_bp 3 /* Stop Bit Mode bit position. */ - -#define USART_CHSIZE_gm 0x07 /* Character Size group mask. */ -#define USART_CHSIZE_gp 0 /* Character Size group position. */ -#define USART_CHSIZE0_bm (1<<0) /* Character Size bit 0 mask. */ -#define USART_CHSIZE0_bp 0 /* Character Size bit 0 position. */ -#define USART_CHSIZE1_bm (1<<1) /* Character Size bit 1 mask. */ -#define USART_CHSIZE1_bp 1 /* Character Size bit 1 position. */ -#define USART_CHSIZE2_bm (1<<2) /* Character Size bit 2 mask. */ -#define USART_CHSIZE2_bp 2 /* Character Size bit 2 position. */ - -/* USART.BAUDCTRLA bit masks and bit positions */ -#define USART_BSEL_gm 0xFF /* Baud Rate Selection Bits [7:0] group mask. */ -#define USART_BSEL_gp 0 /* Baud Rate Selection Bits [7:0] group position. */ -#define USART_BSEL0_bm (1<<0) /* Baud Rate Selection Bits [7:0] bit 0 mask. */ -#define USART_BSEL0_bp 0 /* Baud Rate Selection Bits [7:0] bit 0 position. */ -#define USART_BSEL1_bm (1<<1) /* Baud Rate Selection Bits [7:0] bit 1 mask. */ -#define USART_BSEL1_bp 1 /* Baud Rate Selection Bits [7:0] bit 1 position. */ -#define USART_BSEL2_bm (1<<2) /* Baud Rate Selection Bits [7:0] bit 2 mask. */ -#define USART_BSEL2_bp 2 /* Baud Rate Selection Bits [7:0] bit 2 position. */ -#define USART_BSEL3_bm (1<<3) /* Baud Rate Selection Bits [7:0] bit 3 mask. */ -#define USART_BSEL3_bp 3 /* Baud Rate Selection Bits [7:0] bit 3 position. */ -#define USART_BSEL4_bm (1<<4) /* Baud Rate Selection Bits [7:0] bit 4 mask. */ -#define USART_BSEL4_bp 4 /* Baud Rate Selection Bits [7:0] bit 4 position. */ -#define USART_BSEL5_bm (1<<5) /* Baud Rate Selection Bits [7:0] bit 5 mask. */ -#define USART_BSEL5_bp 5 /* Baud Rate Selection Bits [7:0] bit 5 position. */ -#define USART_BSEL6_bm (1<<6) /* Baud Rate Selection Bits [7:0] bit 6 mask. */ -#define USART_BSEL6_bp 6 /* Baud Rate Selection Bits [7:0] bit 6 position. */ -#define USART_BSEL7_bm (1<<7) /* Baud Rate Selection Bits [7:0] bit 7 mask. */ -#define USART_BSEL7_bp 7 /* Baud Rate Selection Bits [7:0] bit 7 position. */ - -/* USART.BAUDCTRLB bit masks and bit positions */ -#define USART_BSCALE_gm 0xF0 /* Baud Rate Scale group mask. */ -#define USART_BSCALE_gp 4 /* Baud Rate Scale group position. */ -#define USART_BSCALE0_bm (1<<4) /* Baud Rate Scale bit 0 mask. */ -#define USART_BSCALE0_bp 4 /* Baud Rate Scale bit 0 position. */ -#define USART_BSCALE1_bm (1<<5) /* Baud Rate Scale bit 1 mask. */ -#define USART_BSCALE1_bp 5 /* Baud Rate Scale bit 1 position. */ -#define USART_BSCALE2_bm (1<<6) /* Baud Rate Scale bit 2 mask. */ -#define USART_BSCALE2_bp 6 /* Baud Rate Scale bit 2 position. */ -#define USART_BSCALE3_bm (1<<7) /* Baud Rate Scale bit 3 mask. */ -#define USART_BSCALE3_bp 7 /* Baud Rate Scale bit 3 position. */ - -/* USART_BSEL Predefined. */ -/* USART_BSEL Predefined. */ - -/* SPI - Serial Peripheral Interface */ -/* SPI.CTRL bit masks and bit positions */ -#define SPI_CLK2X_bm 0x80 /* Enable Double Speed bit mask. */ -#define SPI_CLK2X_bp 7 /* Enable Double Speed bit position. */ - -#define SPI_ENABLE_bm 0x40 /* Enable Module bit mask. */ -#define SPI_ENABLE_bp 6 /* Enable Module bit position. */ - -#define SPI_DORD_bm 0x20 /* Data Order Setting bit mask. */ -#define SPI_DORD_bp 5 /* Data Order Setting bit position. */ - -#define SPI_MASTER_bm 0x10 /* Master Operation Enable bit mask. */ -#define SPI_MASTER_bp 4 /* Master Operation Enable bit position. */ - -#define SPI_MODE_gm 0x0C /* SPI Mode group mask. */ -#define SPI_MODE_gp 2 /* SPI Mode group position. */ -#define SPI_MODE0_bm (1<<2) /* SPI Mode bit 0 mask. */ -#define SPI_MODE0_bp 2 /* SPI Mode bit 0 position. */ -#define SPI_MODE1_bm (1<<3) /* SPI Mode bit 1 mask. */ -#define SPI_MODE1_bp 3 /* SPI Mode bit 1 position. */ - -#define SPI_PRESCALER_gm 0x03 /* Prescaler group mask. */ -#define SPI_PRESCALER_gp 0 /* Prescaler group position. */ -#define SPI_PRESCALER0_bm (1<<0) /* Prescaler bit 0 mask. */ -#define SPI_PRESCALER0_bp 0 /* Prescaler bit 0 position. */ -#define SPI_PRESCALER1_bm (1<<1) /* Prescaler bit 1 mask. */ -#define SPI_PRESCALER1_bp 1 /* Prescaler bit 1 position. */ - -/* SPI.INTCTRL bit masks and bit positions */ -#define SPI_INTLVL_gm 0x03 /* Interrupt level group mask. */ -#define SPI_INTLVL_gp 0 /* Interrupt level group position. */ -#define SPI_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */ -#define SPI_INTLVL0_bp 0 /* Interrupt level bit 0 position. */ -#define SPI_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */ -#define SPI_INTLVL1_bp 1 /* Interrupt level bit 1 position. */ - -/* SPI.STATUS bit masks and bit positions */ -#define SPI_IF_bm 0x80 /* Interrupt Flag bit mask. */ -#define SPI_IF_bp 7 /* Interrupt Flag bit position. */ - -#define SPI_WRCOL_bm 0x40 /* Write Collision bit mask. */ -#define SPI_WRCOL_bp 6 /* Write Collision bit position. */ - -/* IRCOM - IR Communication Module */ -/* IRCOM.CTRL bit masks and bit positions */ -#define IRCOM_EVSEL_gm 0x0F /* Event Channel Select group mask. */ -#define IRCOM_EVSEL_gp 0 /* Event Channel Select group position. */ -#define IRCOM_EVSEL0_bm (1<<0) /* Event Channel Select bit 0 mask. */ -#define IRCOM_EVSEL0_bp 0 /* Event Channel Select bit 0 position. */ -#define IRCOM_EVSEL1_bm (1<<1) /* Event Channel Select bit 1 mask. */ -#define IRCOM_EVSEL1_bp 1 /* Event Channel Select bit 1 position. */ -#define IRCOM_EVSEL2_bm (1<<2) /* Event Channel Select bit 2 mask. */ -#define IRCOM_EVSEL2_bp 2 /* Event Channel Select bit 2 position. */ -#define IRCOM_EVSEL3_bm (1<<3) /* Event Channel Select bit 3 mask. */ -#define IRCOM_EVSEL3_bp 3 /* Event Channel Select bit 3 position. */ - -/* FUSE - Fuses and Lockbits */ -/* NVM_FUSES.FUSEBYTE1 bit masks and bit positions */ -#define NVM_FUSES_WDWP_gm 0xF0 /* Watchdog Window Timeout Period group mask. */ -#define NVM_FUSES_WDWP_gp 4 /* Watchdog Window Timeout Period group position. */ -#define NVM_FUSES_WDWP0_bm (1<<4) /* Watchdog Window Timeout Period bit 0 mask. */ -#define NVM_FUSES_WDWP0_bp 4 /* Watchdog Window Timeout Period bit 0 position. */ -#define NVM_FUSES_WDWP1_bm (1<<5) /* Watchdog Window Timeout Period bit 1 mask. */ -#define NVM_FUSES_WDWP1_bp 5 /* Watchdog Window Timeout Period bit 1 position. */ -#define NVM_FUSES_WDWP2_bm (1<<6) /* Watchdog Window Timeout Period bit 2 mask. */ -#define NVM_FUSES_WDWP2_bp 6 /* Watchdog Window Timeout Period bit 2 position. */ -#define NVM_FUSES_WDWP3_bm (1<<7) /* Watchdog Window Timeout Period bit 3 mask. */ -#define NVM_FUSES_WDWP3_bp 7 /* Watchdog Window Timeout Period bit 3 position. */ - -#define NVM_FUSES_WDP_gm 0x0F /* Watchdog Timeout Period group mask. */ -#define NVM_FUSES_WDP_gp 0 /* Watchdog Timeout Period group position. */ -#define NVM_FUSES_WDP0_bm (1<<0) /* Watchdog Timeout Period bit 0 mask. */ -#define NVM_FUSES_WDP0_bp 0 /* Watchdog Timeout Period bit 0 position. */ -#define NVM_FUSES_WDP1_bm (1<<1) /* Watchdog Timeout Period bit 1 mask. */ -#define NVM_FUSES_WDP1_bp 1 /* Watchdog Timeout Period bit 1 position. */ -#define NVM_FUSES_WDP2_bm (1<<2) /* Watchdog Timeout Period bit 2 mask. */ -#define NVM_FUSES_WDP2_bp 2 /* Watchdog Timeout Period bit 2 position. */ -#define NVM_FUSES_WDP3_bm (1<<3) /* Watchdog Timeout Period bit 3 mask. */ -#define NVM_FUSES_WDP3_bp 3 /* Watchdog Timeout Period bit 3 position. */ - -/* NVM_FUSES.FUSEBYTE2 bit masks and bit positions */ -#define NVM_FUSES_BOOTRST_bm 0x40 /* Boot Loader Section Reset Vector bit mask. */ -#define NVM_FUSES_BOOTRST_bp 6 /* Boot Loader Section Reset Vector bit position. */ - -#define NVM_FUSES_TOSCSEL_bm 0x20 /* Timer Oscillator pin location bit mask. */ -#define NVM_FUSES_TOSCSEL_bp 5 /* Timer Oscillator pin location bit position. */ - -#define NVM_FUSES_BODPD_gm 0x03 /* BOD Operation in Power-Down Mode group mask. */ -#define NVM_FUSES_BODPD_gp 0 /* BOD Operation in Power-Down Mode group position. */ -#define NVM_FUSES_BODPD0_bm (1<<0) /* BOD Operation in Power-Down Mode bit 0 mask. */ -#define NVM_FUSES_BODPD0_bp 0 /* BOD Operation in Power-Down Mode bit 0 position. */ -#define NVM_FUSES_BODPD1_bm (1<<1) /* BOD Operation in Power-Down Mode bit 1 mask. */ -#define NVM_FUSES_BODPD1_bp 1 /* BOD Operation in Power-Down Mode bit 1 position. */ - -/* NVM_FUSES.FUSEBYTE4 bit masks and bit positions */ -#define NVM_FUSES_RSTDISBL_bm 0x10 /* External Reset Disable bit mask. */ -#define NVM_FUSES_RSTDISBL_bp 4 /* External Reset Disable bit position. */ - -#define NVM_FUSES_SUT_gm 0x0C /* Start-up Time group mask. */ -#define NVM_FUSES_SUT_gp 2 /* Start-up Time group position. */ -#define NVM_FUSES_SUT0_bm (1<<2) /* Start-up Time bit 0 mask. */ -#define NVM_FUSES_SUT0_bp 2 /* Start-up Time bit 0 position. */ -#define NVM_FUSES_SUT1_bm (1<<3) /* Start-up Time bit 1 mask. */ -#define NVM_FUSES_SUT1_bp 3 /* Start-up Time bit 1 position. */ - -#define NVM_FUSES_WDLOCK_bm 0x02 /* Watchdog Timer Lock bit mask. */ -#define NVM_FUSES_WDLOCK_bp 1 /* Watchdog Timer Lock bit position. */ - -/* NVM_FUSES.FUSEBYTE5 bit masks and bit positions */ -#define NVM_FUSES_BODACT_gm 0x30 /* BOD Operation in Active Mode group mask. */ -#define NVM_FUSES_BODACT_gp 4 /* BOD Operation in Active Mode group position. */ -#define NVM_FUSES_BODACT0_bm (1<<4) /* BOD Operation in Active Mode bit 0 mask. */ -#define NVM_FUSES_BODACT0_bp 4 /* BOD Operation in Active Mode bit 0 position. */ -#define NVM_FUSES_BODACT1_bm (1<<5) /* BOD Operation in Active Mode bit 1 mask. */ -#define NVM_FUSES_BODACT1_bp 5 /* BOD Operation in Active Mode bit 1 position. */ - -#define NVM_FUSES_EESAVE_bm 0x08 /* Preserve EEPROM Through Chip Erase bit mask. */ -#define NVM_FUSES_EESAVE_bp 3 /* Preserve EEPROM Through Chip Erase bit position. */ - -#define NVM_FUSES_BODLVL_gm 0x07 /* Brownout Detection Voltage Level group mask. */ -#define NVM_FUSES_BODLVL_gp 0 /* Brownout Detection Voltage Level group position. */ -#define NVM_FUSES_BODLVL0_bm (1<<0) /* Brownout Detection Voltage Level bit 0 mask. */ -#define NVM_FUSES_BODLVL0_bp 0 /* Brownout Detection Voltage Level bit 0 position. */ -#define NVM_FUSES_BODLVL1_bm (1<<1) /* Brownout Detection Voltage Level bit 1 mask. */ -#define NVM_FUSES_BODLVL1_bp 1 /* Brownout Detection Voltage Level bit 1 position. */ -#define NVM_FUSES_BODLVL2_bm (1<<2) /* Brownout Detection Voltage Level bit 2 mask. */ -#define NVM_FUSES_BODLVL2_bp 2 /* Brownout Detection Voltage Level bit 2 position. */ - -/* LOCKBIT - Fuses and Lockbits */ -/* NVM_LOCKBITS.LOCKBITS bit masks and bit positions */ -#define NVM_LOCKBITS_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ -#define NVM_LOCKBITS_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ -#define NVM_LOCKBITS_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ -#define NVM_LOCKBITS_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ -#define NVM_LOCKBITS_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ -#define NVM_LOCKBITS_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ - -#define NVM_LOCKBITS_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ -#define NVM_LOCKBITS_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ -#define NVM_LOCKBITS_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ -#define NVM_LOCKBITS_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ -#define NVM_LOCKBITS_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ -#define NVM_LOCKBITS_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ - -#define NVM_LOCKBITS_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ -#define NVM_LOCKBITS_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ -#define NVM_LOCKBITS_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ -#define NVM_LOCKBITS_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ -#define NVM_LOCKBITS_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ -#define NVM_LOCKBITS_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ - -#define NVM_LOCKBITS_LB_gm 0x03 /* Lock Bits group mask. */ -#define NVM_LOCKBITS_LB_gp 0 /* Lock Bits group position. */ -#define NVM_LOCKBITS_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ -#define NVM_LOCKBITS_LB0_bp 0 /* Lock Bits bit 0 position. */ -#define NVM_LOCKBITS_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ -#define NVM_LOCKBITS_LB1_bp 1 /* Lock Bits bit 1 position. */ - - - -// Generic Port Pins - -#define PIN0_bm 0x01 -#define PIN0_bp 0 -#define PIN1_bm 0x02 -#define PIN1_bp 1 -#define PIN2_bm 0x04 -#define PIN2_bp 2 -#define PIN3_bm 0x08 -#define PIN3_bp 3 -#define PIN4_bm 0x10 -#define PIN4_bp 4 -#define PIN5_bm 0x20 -#define PIN5_bp 5 -#define PIN6_bm 0x40 -#define PIN6_bp 6 -#define PIN7_bm 0x80 -#define PIN7_bp 7 - -/* ========== Interrupt Vector Definitions ========== */ -/* Vector 0 is the reset vector */ - -/* OSC interrupt vectors */ -#define OSC_OSCF_vect_num 1 -#define OSC_OSCF_vect _VECTOR(1) /* Oscillator Failure Interrupt (NMI) */ - -/* PORTC interrupt vectors */ -#define PORTC_INT0_vect_num 2 -#define PORTC_INT0_vect _VECTOR(2) /* External Interrupt 0 */ -#define PORTC_INT1_vect_num 3 -#define PORTC_INT1_vect _VECTOR(3) /* External Interrupt 1 */ - -/* PORTR interrupt vectors */ -#define PORTR_INT0_vect_num 4 -#define PORTR_INT0_vect _VECTOR(4) /* External Interrupt 0 */ -#define PORTR_INT1_vect_num 5 -#define PORTR_INT1_vect _VECTOR(5) /* External Interrupt 1 */ - -/* RTC interrupt vectors */ -#define RTC_OVF_vect_num 10 -#define RTC_OVF_vect _VECTOR(10) /* Overflow Interrupt */ -#define RTC_COMP_vect_num 11 -#define RTC_COMP_vect _VECTOR(11) /* Compare Interrupt */ - -/* TWIC interrupt vectors */ -#define TWIC_TWIS_vect_num 12 -#define TWIC_TWIS_vect _VECTOR(12) /* TWI Slave Interrupt */ -#define TWIC_TWIM_vect_num 13 -#define TWIC_TWIM_vect _VECTOR(13) /* TWI Master Interrupt */ - -/* TCC0 interrupt vectors */ -#define TCC0_OVF_vect_num 14 -#define TCC0_OVF_vect _VECTOR(14) /* Overflow Interrupt */ - -/* TCC2 interrupt vectors */ -#define TCC2_LUNF_vect_num 14 -#define TCC2_LUNF_vect _VECTOR(14) /* Low Byte Underflow Interrupt */ - -/* TCC0 interrupt vectors */ -#define TCC0_ERR_vect_num 15 -#define TCC0_ERR_vect _VECTOR(15) /* Error Interrupt */ - -/* TCC2 interrupt vectors */ -#define TCC2_HUNF_vect_num 15 -#define TCC2_HUNF_vect _VECTOR(15) /* High Byte Underflow Interrupt */ - -/* TCC0 interrupt vectors */ -#define TCC0_CCA_vect_num 16 -#define TCC0_CCA_vect _VECTOR(16) /* Compare or Capture A Interrupt */ - -/* TCC2 interrupt vectors */ -#define TCC2_LCMPA_vect_num 16 -#define TCC2_LCMPA_vect _VECTOR(16) /* Low Byte Compare A Interrupt */ - -/* TCC0 interrupt vectors */ -#define TCC0_CCB_vect_num 17 -#define TCC0_CCB_vect _VECTOR(17) /* Compare or Capture B Interrupt */ - -/* TCC2 interrupt vectors */ -#define TCC2_LCMPB_vect_num 17 -#define TCC2_LCMPB_vect _VECTOR(17) /* Low Byte Compare B Interrupt */ - -/* TCC0 interrupt vectors */ -#define TCC0_CCC_vect_num 18 -#define TCC0_CCC_vect _VECTOR(18) /* Compare or Capture C Interrupt */ - -/* TCC2 interrupt vectors */ -#define TCC2_LCMPC_vect_num 18 -#define TCC2_LCMPC_vect _VECTOR(18) /* Low Byte Compare C Interrupt */ - -/* TCC0 interrupt vectors */ -#define TCC0_CCD_vect_num 19 -#define TCC0_CCD_vect _VECTOR(19) /* Compare or Capture D Interrupt */ - -/* TCC2 interrupt vectors */ -#define TCC2_LCMPD_vect_num 19 -#define TCC2_LCMPD_vect _VECTOR(19) /* Low Byte Compare D Interrupt */ - -/* TCC1 interrupt vectors */ -#define TCC1_OVF_vect_num 20 -#define TCC1_OVF_vect _VECTOR(20) /* Overflow Interrupt */ -#define TCC1_ERR_vect_num 21 -#define TCC1_ERR_vect _VECTOR(21) /* Error Interrupt */ -#define TCC1_CCA_vect_num 22 -#define TCC1_CCA_vect _VECTOR(22) /* Compare or Capture A Interrupt */ -#define TCC1_CCB_vect_num 23 -#define TCC1_CCB_vect _VECTOR(23) /* Compare or Capture B Interrupt */ - -/* SPIC interrupt vectors */ -#define SPIC_INT_vect_num 24 -#define SPIC_INT_vect _VECTOR(24) /* SPI Interrupt */ - -/* USARTC0 interrupt vectors */ -#define USARTC0_RXC_vect_num 25 -#define USARTC0_RXC_vect _VECTOR(25) /* Reception Complete Interrupt */ -#define USARTC0_DRE_vect_num 26 -#define USARTC0_DRE_vect _VECTOR(26) /* Data Register Empty Interrupt */ -#define USARTC0_TXC_vect_num 27 -#define USARTC0_TXC_vect _VECTOR(27) /* Transmission Complete Interrupt */ - -/* NVM interrupt vectors */ -#define NVM_EE_vect_num 32 -#define NVM_EE_vect _VECTOR(32) /* EE Interrupt */ -#define NVM_SPM_vect_num 33 -#define NVM_SPM_vect _VECTOR(33) /* SPM Interrupt */ - -/* PORTB interrupt vectors */ -#define PORTB_INT0_vect_num 34 -#define PORTB_INT0_vect _VECTOR(34) /* External Interrupt 0 */ -#define PORTB_INT1_vect_num 35 -#define PORTB_INT1_vect _VECTOR(35) /* External Interrupt 1 */ - -/* PORTE interrupt vectors */ -#define PORTE_INT0_vect_num 43 -#define PORTE_INT0_vect _VECTOR(43) /* External Interrupt 0 */ -#define PORTE_INT1_vect_num 44 -#define PORTE_INT1_vect _VECTOR(44) /* External Interrupt 1 */ - -/* TWIE interrupt vectors */ -#define TWIE_TWIS_vect_num 45 -#define TWIE_TWIS_vect _VECTOR(45) /* TWI Slave Interrupt */ -#define TWIE_TWIM_vect_num 46 -#define TWIE_TWIM_vect _VECTOR(46) /* TWI Master Interrupt */ - -/* TCE0 interrupt vectors */ -#define TCE0_OVF_vect_num 47 -#define TCE0_OVF_vect _VECTOR(47) /* Overflow Interrupt */ - -/* TCE2 interrupt vectors */ -#define TCE2_LUNF_vect_num 47 -#define TCE2_LUNF_vect _VECTOR(47) /* Low Byte Underflow Interrupt */ - -/* TCE0 interrupt vectors */ -#define TCE0_ERR_vect_num 48 -#define TCE0_ERR_vect _VECTOR(48) /* Error Interrupt */ - -/* TCE2 interrupt vectors */ -#define TCE2_HUNF_vect_num 48 -#define TCE2_HUNF_vect _VECTOR(48) /* High Byte Underflow Interrupt */ - -/* TCE0 interrupt vectors */ -#define TCE0_CCA_vect_num 49 -#define TCE0_CCA_vect _VECTOR(49) /* Compare or Capture A Interrupt */ - -/* TCE2 interrupt vectors */ -#define TCE2_LCMPA_vect_num 49 -#define TCE2_LCMPA_vect _VECTOR(49) /* Low Byte Compare A Interrupt */ - -/* TCE0 interrupt vectors */ -#define TCE0_CCB_vect_num 50 -#define TCE0_CCB_vect _VECTOR(50) /* Compare or Capture B Interrupt */ - -/* TCE2 interrupt vectors */ -#define TCE2_LCMPB_vect_num 50 -#define TCE2_LCMPB_vect _VECTOR(50) /* Low Byte Compare B Interrupt */ - -/* TCE0 interrupt vectors */ -#define TCE0_CCC_vect_num 51 -#define TCE0_CCC_vect _VECTOR(51) /* Compare or Capture C Interrupt */ - -/* TCE2 interrupt vectors */ -#define TCE2_LCMPC_vect_num 51 -#define TCE2_LCMPC_vect _VECTOR(51) /* Low Byte Compare C Interrupt */ - -/* TCE0 interrupt vectors */ -#define TCE0_CCD_vect_num 52 -#define TCE0_CCD_vect _VECTOR(52) /* Compare or Capture D Interrupt */ - -/* TCE2 interrupt vectors */ -#define TCE2_LCMPD_vect_num 52 -#define TCE2_LCMPD_vect _VECTOR(52) /* Low Byte Compare D Interrupt */ - -/* USARTE0 interrupt vectors */ -#define USARTE0_RXC_vect_num 58 -#define USARTE0_RXC_vect _VECTOR(58) /* Reception Complete Interrupt */ -#define USARTE0_DRE_vect_num 59 -#define USARTE0_DRE_vect _VECTOR(59) /* Data Register Empty Interrupt */ -#define USARTE0_TXC_vect_num 60 -#define USARTE0_TXC_vect _VECTOR(60) /* Transmission Complete Interrupt */ - -/* PORTD interrupt vectors */ -#define PORTD_INT0_vect_num 64 -#define PORTD_INT0_vect _VECTOR(64) /* External Interrupt 0 */ -#define PORTD_INT1_vect_num 65 -#define PORTD_INT1_vect _VECTOR(65) /* External Interrupt 1 */ - -/* PORTA interrupt vectors */ -#define PORTA_INT0_vect_num 66 -#define PORTA_INT0_vect _VECTOR(66) /* External Interrupt 0 */ -#define PORTA_INT1_vect_num 67 -#define PORTA_INT1_vect _VECTOR(67) /* External Interrupt 1 */ - -/* ACA interrupt vectors */ -#define ACA_AC0_vect_num 68 -#define ACA_AC0_vect _VECTOR(68) /* AC0 Interrupt */ -#define ACA_AC1_vect_num 69 -#define ACA_AC1_vect _VECTOR(69) /* AC1 Interrupt */ -#define ACA_ACW_vect_num 70 -#define ACA_ACW_vect _VECTOR(70) /* ACW Window Mode Interrupt */ - -/* ADCA interrupt vectors */ -#define ADCA_CH0_vect_num 71 -#define ADCA_CH0_vect _VECTOR(71) /* Interrupt 0 */ - -/* TCD0 interrupt vectors */ -#define TCD0_OVF_vect_num 77 -#define TCD0_OVF_vect _VECTOR(77) /* Overflow Interrupt */ - -/* TCD2 interrupt vectors */ -#define TCD2_LUNF_vect_num 77 -#define TCD2_LUNF_vect _VECTOR(77) /* Low Byte Underflow Interrupt */ - -/* TCD0 interrupt vectors */ -#define TCD0_ERR_vect_num 78 -#define TCD0_ERR_vect _VECTOR(78) /* Error Interrupt */ - -/* TCD2 interrupt vectors */ -#define TCD2_HUNF_vect_num 78 -#define TCD2_HUNF_vect _VECTOR(78) /* High Byte Underflow Interrupt */ - -/* TCD0 interrupt vectors */ -#define TCD0_CCA_vect_num 79 -#define TCD0_CCA_vect _VECTOR(79) /* Compare or Capture A Interrupt */ - -/* TCD2 interrupt vectors */ -#define TCD2_LCMPA_vect_num 79 -#define TCD2_LCMPA_vect _VECTOR(79) /* Low Byte Compare A Interrupt */ - -/* TCD0 interrupt vectors */ -#define TCD0_CCB_vect_num 80 -#define TCD0_CCB_vect _VECTOR(80) /* Compare or Capture B Interrupt */ - -/* TCD2 interrupt vectors */ -#define TCD2_LCMPB_vect_num 80 -#define TCD2_LCMPB_vect _VECTOR(80) /* Low Byte Compare B Interrupt */ - -/* TCD0 interrupt vectors */ -#define TCD0_CCC_vect_num 81 -#define TCD0_CCC_vect _VECTOR(81) /* Compare or Capture C Interrupt */ - -/* TCD2 interrupt vectors */ -#define TCD2_LCMPC_vect_num 81 -#define TCD2_LCMPC_vect _VECTOR(81) /* Low Byte Compare C Interrupt */ - -/* TCD0 interrupt vectors */ -#define TCD0_CCD_vect_num 82 -#define TCD0_CCD_vect _VECTOR(82) /* Compare or Capture D Interrupt */ - -/* TCD2 interrupt vectors */ -#define TCD2_LCMPD_vect_num 82 -#define TCD2_LCMPD_vect _VECTOR(82) /* Low Byte Compare D Interrupt */ - -/* SPID interrupt vectors */ -#define SPID_INT_vect_num 87 -#define SPID_INT_vect _VECTOR(87) /* SPI Interrupt */ - -/* USARTD0 interrupt vectors */ -#define USARTD0_RXC_vect_num 88 -#define USARTD0_RXC_vect _VECTOR(88) /* Reception Complete Interrupt */ -#define USARTD0_DRE_vect_num 89 -#define USARTD0_DRE_vect _VECTOR(89) /* Data Register Empty Interrupt */ -#define USARTD0_TXC_vect_num 90 -#define USARTD0_TXC_vect _VECTOR(90) /* Transmission Complete Interrupt */ - -/* PORTF interrupt vectors */ -#define PORTF_INT0_vect_num 104 -#define PORTF_INT0_vect _VECTOR(104) /* External Interrupt 0 */ -#define PORTF_INT1_vect_num 105 -#define PORTF_INT1_vect _VECTOR(105) /* External Interrupt 1 */ - -/* TCF0 interrupt vectors */ -#define TCF0_OVF_vect_num 108 -#define TCF0_OVF_vect _VECTOR(108) /* Overflow Interrupt */ - -/* TCF2 interrupt vectors */ -#define TCF2_LUNF_vect_num 108 -#define TCF2_LUNF_vect _VECTOR(108) /* Low Byte Underflow Interrupt */ - -/* TCF0 interrupt vectors */ -#define TCF0_ERR_vect_num 109 -#define TCF0_ERR_vect _VECTOR(109) /* Error Interrupt */ - -/* TCF2 interrupt vectors */ -#define TCF2_HUNF_vect_num 109 -#define TCF2_HUNF_vect _VECTOR(109) /* High Byte Underflow Interrupt */ - -/* TCF0 interrupt vectors */ -#define TCF0_CCA_vect_num 110 -#define TCF0_CCA_vect _VECTOR(110) /* Compare or Capture A Interrupt */ - -/* TCF2 interrupt vectors */ -#define TCF2_LCMPA_vect_num 110 -#define TCF2_LCMPA_vect _VECTOR(110) /* Low Byte Compare A Interrupt */ - -/* TCF0 interrupt vectors */ -#define TCF0_CCB_vect_num 111 -#define TCF0_CCB_vect _VECTOR(111) /* Compare or Capture B Interrupt */ - -/* TCF2 interrupt vectors */ -#define TCF2_LCMPB_vect_num 111 -#define TCF2_LCMPB_vect _VECTOR(111) /* Low Byte Compare B Interrupt */ - -/* TCF0 interrupt vectors */ -#define TCF0_CCC_vect_num 112 -#define TCF0_CCC_vect _VECTOR(112) /* Compare or Capture C Interrupt */ - -/* TCF2 interrupt vectors */ -#define TCF2_LCMPC_vect_num 112 -#define TCF2_LCMPC_vect _VECTOR(112) /* Low Byte Compare C Interrupt */ - -/* TCF0 interrupt vectors */ -#define TCF0_CCD_vect_num 113 -#define TCF0_CCD_vect _VECTOR(113) /* Compare or Capture D Interrupt */ - -/* TCF2 interrupt vectors */ -#define TCF2_LCMPD_vect_num 113 -#define TCF2_LCMPD_vect _VECTOR(113) /* Low Byte Compare D Interrupt */ - -#define _VECTOR_SIZE 4 /* Size of individual vector. */ -#define _VECTORS_SIZE (114 * _VECTOR_SIZE) - - -/* ========== Constants ========== */ - -#define PROGMEM_START (0x0000) -#define PROGMEM_SIZE (401408) -#define PROGMEM_END (PROGMEM_START + PROGMEM_SIZE - 1) - -#define APP_SECTION_START (0x0000) -#define APP_SECTION_SIZE (393216) -#define APP_SECTION_PAGE_SIZE (512) -#define APP_SECTION_END (APP_SECTION_START + APP_SECTION_SIZE - 1) - -#define APPTABLE_SECTION_START (0x5E000) -#define APPTABLE_SECTION_SIZE (8192) -#define APPTABLE_SECTION_PAGE_SIZE (512) -#define APPTABLE_SECTION_END (APPTABLE_SECTION_START + APPTABLE_SECTION_SIZE - 1) - -#define BOOT_SECTION_START (0x60000) -#define BOOT_SECTION_SIZE (8192) -#define BOOT_SECTION_PAGE_SIZE (512) -#define BOOT_SECTION_END (BOOT_SECTION_START + BOOT_SECTION_SIZE - 1) - -#define DATAMEM_START (0x0000) -#define DATAMEM_SIZE (40960) -#define DATAMEM_END (DATAMEM_START + DATAMEM_SIZE - 1) - -#define IO_START (0x0000) -#define IO_SIZE (4096) -#define IO_PAGE_SIZE (0) -#define IO_END (IO_START + IO_SIZE - 1) - -#define MAPPED_EEPROM_START (0x1000) -#define MAPPED_EEPROM_SIZE (4096) -#define MAPPED_EEPROM_PAGE_SIZE (0) -#define MAPPED_EEPROM_END (MAPPED_EEPROM_START + MAPPED_EEPROM_SIZE - 1) - -#define INTERNAL_SRAM_START (0x2000) -#define INTERNAL_SRAM_SIZE (32768) -#define INTERNAL_SRAM_PAGE_SIZE (0) -#define INTERNAL_SRAM_END (INTERNAL_SRAM_START + INTERNAL_SRAM_SIZE - 1) - -#define EEPROM_START (0x0000) -#define EEPROM_SIZE (4096) -#define EEPROM_PAGE_SIZE (32) -#define EEPROM_END (EEPROM_START + EEPROM_SIZE - 1) - -#define SIGNATURES_START (0x0000) -#define SIGNATURES_SIZE (3) -#define SIGNATURES_PAGE_SIZE (0) -#define SIGNATURES_END (SIGNATURES_START + SIGNATURES_SIZE - 1) - -#define FUSES_START (0x0000) -#define FUSES_SIZE (6) -#define FUSES_PAGE_SIZE (0) -#define FUSES_END (FUSES_START + FUSES_SIZE - 1) - -#define LOCKBITS_START (0x0000) -#define LOCKBITS_SIZE (1) -#define LOCKBITS_PAGE_SIZE (0) -#define LOCKBITS_END (LOCKBITS_START + LOCKBITS_SIZE - 1) - -#define USER_SIGNATURES_START (0x0000) -#define USER_SIGNATURES_SIZE (512) -#define USER_SIGNATURES_PAGE_SIZE (512) -#define USER_SIGNATURES_END (USER_SIGNATURES_START + USER_SIGNATURES_SIZE - 1) - -#define PROD_SIGNATURES_START (0x0000) -#define PROD_SIGNATURES_SIZE (64) -#define PROD_SIGNATURES_PAGE_SIZE (512) -#define PROD_SIGNATURES_END (PROD_SIGNATURES_START + PROD_SIGNATURES_SIZE - 1) - -#define FLASHSTART PROGMEM_START -#define FLASHEND PROGMEM_END -#define SPM_PAGESIZE 512 -#define RAMSTART INTERNAL_SRAM_START -#define RAMSIZE INTERNAL_SRAM_SIZE -#define RAMEND INTERNAL_SRAM_END -#define E2END EEPROM_END -#define E2PAGESIZE EEPROM_PAGE_SIZE - - -/* ========== Fuses ========== */ -#define FUSE_MEMORY_SIZE 6 - -/* Fuse Byte 0 Reserved */ - -/* Fuse Byte 1 */ -#define FUSE_WDP0 (unsigned char)~_BV(0) /* Watchdog Timeout Period Bit 0 */ -#define FUSE_WDP1 (unsigned char)~_BV(1) /* Watchdog Timeout Period Bit 1 */ -#define FUSE_WDP2 (unsigned char)~_BV(2) /* Watchdog Timeout Period Bit 2 */ -#define FUSE_WDP3 (unsigned char)~_BV(3) /* Watchdog Timeout Period Bit 3 */ -#define FUSE_WDWP0 (unsigned char)~_BV(4) /* Watchdog Window Timeout Period Bit 0 */ -#define FUSE_WDWP1 (unsigned char)~_BV(5) /* Watchdog Window Timeout Period Bit 1 */ -#define FUSE_WDWP2 (unsigned char)~_BV(6) /* Watchdog Window Timeout Period Bit 2 */ -#define FUSE_WDWP3 (unsigned char)~_BV(7) /* Watchdog Window Timeout Period Bit 3 */ -#define FUSE1_DEFAULT (0xFF) - -/* Fuse Byte 2 */ -#define FUSE_BODPD0 (unsigned char)~_BV(0) /* BOD Operation in Power-Down Mode Bit 0 */ -#define FUSE_BODPD1 (unsigned char)~_BV(1) /* BOD Operation in Power-Down Mode Bit 1 */ -#define FUSE_TOSCSEL (unsigned char)~_BV(5) /* Timer Oscillator pin location */ -#define FUSE_BOOTRST (unsigned char)~_BV(6) /* Boot Loader Section Reset Vector */ -#define FUSE2_DEFAULT (0xFF) - -/* Fuse Byte 3 Reserved */ - -/* Fuse Byte 4 */ -#define FUSE_WDLOCK (unsigned char)~_BV(1) /* Watchdog Timer Lock */ -#define FUSE_SUT0 (unsigned char)~_BV(2) /* Start-up Time Bit 0 */ -#define FUSE_SUT1 (unsigned char)~_BV(3) /* Start-up Time Bit 1 */ -#define FUSE_RSTDISBL (unsigned char)~_BV(4) /* External Reset Disable */ -#define FUSE4_DEFAULT (0xFF) - -/* Fuse Byte 5 */ -#define FUSE_BODLVL0 (unsigned char)~_BV(0) /* Brownout Detection Voltage Level Bit 0 */ -#define FUSE_BODLVL1 (unsigned char)~_BV(1) /* Brownout Detection Voltage Level Bit 1 */ -#define FUSE_BODLVL2 (unsigned char)~_BV(2) /* Brownout Detection Voltage Level Bit 2 */ -#define FUSE_EESAVE (unsigned char)~_BV(3) /* Preserve EEPROM Through Chip Erase */ -#define FUSE_BODACT0 (unsigned char)~_BV(4) /* BOD Operation in Active Mode Bit 0 */ -#define FUSE_BODACT1 (unsigned char)~_BV(5) /* BOD Operation in Active Mode Bit 1 */ -#define FUSE5_DEFAULT (0xFF) - -/* ========== Lock Bits ========== */ -#define __LOCK_BITS_EXIST -#define __BOOT_LOCK_APPLICATION_TABLE_BITS_EXIST -#define __BOOT_LOCK_APPLICATION_BITS_EXIST -#define __BOOT_LOCK_BOOT_BITS_EXIST - -/* ========== Signature ========== */ -#define SIGNATURE_0 0x1E -#define SIGNATURE_1 0x98 -#define SIGNATURE_2 0x47 - -/* ========== Power Reduction Condition Definitions ========== */ - -/* PR.PRGEN */ -#define __AVR_HAVE_PRGEN (PR_RTC_bm|PR_EVSYS_bm) -#define __AVR_HAVE_PRGEN_RTC -#define __AVR_HAVE_PRGEN_EVSYS - -/* PR.PRPA */ -#define __AVR_HAVE_PRPA (PR_ADC_bm|PR_AC_bm) -#define __AVR_HAVE_PRPA_ADC -#define __AVR_HAVE_PRPA_AC - -/* PR.PRPC */ -#define __AVR_HAVE_PRPC (PR_TWI_bm|PR_USART0_bm|PR_SPI_bm|PR_HIRES_bm|PR_TC1_bm|PR_TC0_bm) -#define __AVR_HAVE_PRPC_TWI -#define __AVR_HAVE_PRPC_USART0 -#define __AVR_HAVE_PRPC_SPI -#define __AVR_HAVE_PRPC_HIRES -#define __AVR_HAVE_PRPC_TC1 -#define __AVR_HAVE_PRPC_TC0 - -/* PR.PRPD */ -#define __AVR_HAVE_PRPD (PR_USART0_bm|PR_SPI_bm|PR_TC0_bm) -#define __AVR_HAVE_PRPD_USART0 -#define __AVR_HAVE_PRPD_SPI -#define __AVR_HAVE_PRPD_TC0 - -/* PR.PRPE */ -#define __AVR_HAVE_PRPE (PR_TWI_bm|PR_USART0_bm|PR_TC0_bm) -#define __AVR_HAVE_PRPE_TWI -#define __AVR_HAVE_PRPE_USART0 -#define __AVR_HAVE_PRPE_TC0 - -/* PR.PRPF */ -#define __AVR_HAVE_PRPF (PR_USART0_bm|PR_TC0_bm) -#define __AVR_HAVE_PRPF_USART0 -#define __AVR_HAVE_PRPF_TC0 - - -#endif /* #ifdef _AVR_ATXMEGA384D3_H_INCLUDED */ - diff --git a/arduino/hardware/tools/avr/avr/include/avr/iox64a1.h b/arduino/hardware/tools/avr/avr/include/avr/iox64a1.h deleted file mode 100644 index b62b1d6..0000000 --- a/arduino/hardware/tools/avr/avr/include/avr/iox64a1.h +++ /dev/null @@ -1,7236 +0,0 @@ -/* Copyright (c) 2009-2010 Atmel Corporation - All rights reserved. - - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - * Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - * Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in - the documentation and/or other materials provided with the - distribution. - - * Neither the name of the copyright holders nor the names of - contributors may be used to endorse or promote products derived - from this software without specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. */ - -/* $Id: iox64a1.h 2260 2011-11-02 16:53:30Z arcanum $ */ - -/* avr/iox64a1.h - definitions for ATxmega64A1 */ - -/* This file should only be included from , never directly. */ - -#ifndef _AVR_IO_H_ -# error "Include instead of this file." -#endif - -#ifndef _AVR_IOXXX_H_ -# define _AVR_IOXXX_H_ "iox64a1.h" -#else -# error "Attempt to include more than one file." -#endif - - -#ifndef _AVR_ATxmega64A1_H_ -#define _AVR_ATxmega64A1_H_ 1 - - -/* Ungrouped common registers */ -#define GPIOR0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ -#define GPIOR1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ -#define GPIOR2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ -#define GPIOR3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ -#define GPIOR4 _SFR_MEM8(0x0004) /* General Purpose IO Register 4 */ -#define GPIOR5 _SFR_MEM8(0x0005) /* General Purpose IO Register 5 */ -#define GPIOR6 _SFR_MEM8(0x0006) /* General Purpose IO Register 6 */ -#define GPIOR7 _SFR_MEM8(0x0007) /* General Purpose IO Register 7 */ -#define GPIOR8 _SFR_MEM8(0x0008) /* General Purpose IO Register 8 */ -#define GPIOR9 _SFR_MEM8(0x0009) /* General Purpose IO Register 9 */ -#define GPIORA _SFR_MEM8(0x000A) /* General Purpose IO Register 10 */ -#define GPIORB _SFR_MEM8(0x000B) /* General Purpose IO Register 11 */ -#define GPIORC _SFR_MEM8(0x000C) /* General Purpose IO Register 12 */ -#define GPIORD _SFR_MEM8(0x000D) /* General Purpose IO Register 13 */ -#define GPIORE _SFR_MEM8(0x000E) /* General Purpose IO Register 14 */ -#define GPIORF _SFR_MEM8(0x000F) /* General Purpose IO Register 15 */ - -/* Deprecated */ -#define GPIO0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ -#define GPIO1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ -#define GPIO2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ -#define GPIO3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ -#define GPIO4 _SFR_MEM8(0x0004) /* General Purpose IO Register 4 */ -#define GPIO5 _SFR_MEM8(0x0005) /* General Purpose IO Register 5 */ -#define GPIO6 _SFR_MEM8(0x0006) /* General Purpose IO Register 6 */ -#define GPIO7 _SFR_MEM8(0x0007) /* General Purpose IO Register 7 */ -#define GPIO8 _SFR_MEM8(0x0008) /* General Purpose IO Register 8 */ -#define GPIO9 _SFR_MEM8(0x0009) /* General Purpose IO Register 9 */ -#define GPIOA _SFR_MEM8(0x000A) /* General Purpose IO Register 10 */ -#define GPIOB _SFR_MEM8(0x000B) /* General Purpose IO Register 11 */ -#define GPIOC _SFR_MEM8(0x000C) /* General Purpose IO Register 12 */ -#define GPIOD _SFR_MEM8(0x000D) /* General Purpose IO Register 13 */ -#define GPIOE _SFR_MEM8(0x000E) /* General Purpose IO Register 14 */ -#define GPIOF _SFR_MEM8(0x000F) /* General Purpose IO Register 15 */ - -#define CCP _SFR_MEM8(0x0034) /* Configuration Change Protection */ -#define RAMPD _SFR_MEM8(0x0038) /* Ramp D */ -#define RAMPX _SFR_MEM8(0x0039) /* Ramp X */ -#define RAMPY _SFR_MEM8(0x003A) /* Ramp Y */ -#define RAMPZ _SFR_MEM8(0x003B) /* Ramp Z */ -#define EIND _SFR_MEM8(0x003C) /* Extended Indirect Jump */ -#define SPL _SFR_MEM8(0x003D) /* Stack Pointer Low */ -#define SPH _SFR_MEM8(0x003E) /* Stack Pointer High */ -#define SREG _SFR_MEM8(0x003F) /* Status Register */ - - -/* C Language Only */ -#if !defined (__ASSEMBLER__) - -#include - -typedef volatile uint8_t register8_t; -typedef volatile uint16_t register16_t; -typedef volatile uint32_t register32_t; - - -#ifdef _WORDREGISTER -#undef _WORDREGISTER -#endif -#define _WORDREGISTER(regname) \ - __extension__ union \ - { \ - register16_t regname; \ - struct \ - { \ - register8_t regname ## L; \ - register8_t regname ## H; \ - }; \ - } - -#ifdef _DWORDREGISTER -#undef _DWORDREGISTER -#endif -#define _DWORDREGISTER(regname) \ - __extension__ union \ - { \ - register32_t regname; \ - struct \ - { \ - register8_t regname ## 0; \ - register8_t regname ## 1; \ - register8_t regname ## 2; \ - register8_t regname ## 3; \ - }; \ - } - - -/* -========================================================================== -IO Module Structures -========================================================================== -*/ - - -/* --------------------------------------------------------------------------- -XOCD - On-Chip Debug System --------------------------------------------------------------------------- -*/ - -/* On-Chip Debug System */ -typedef struct OCD_struct -{ - register8_t OCDR0; /* OCD Register 0 */ - register8_t OCDR1; /* OCD Register 1 */ -} OCD_t; - - -/* CCP signatures */ -typedef enum CCP_enum -{ - CCP_SPM_gc = (0x9D<<0), /* SPM Instruction Protection */ - CCP_IOREG_gc = (0xD8<<0), /* IO Register Protection */ -} CCP_t; - - -/* --------------------------------------------------------------------------- -CLK - Clock System --------------------------------------------------------------------------- -*/ - -/* Clock System */ -typedef struct CLK_struct -{ - register8_t CTRL; /* Control Register */ - register8_t PSCTRL; /* Prescaler Control Register */ - register8_t LOCK; /* Lock register */ - register8_t RTCCTRL; /* RTC Control Register */ -} CLK_t; - -/* --------------------------------------------------------------------------- -CLK - Clock System --------------------------------------------------------------------------- -*/ - -/* Power Reduction */ -typedef struct PR_struct -{ - register8_t PRGEN; /* General Power Reduction */ - register8_t PRPA; /* Power Reduction Port A */ - register8_t PRPB; /* Power Reduction Port B */ - register8_t PRPC; /* Power Reduction Port C */ - register8_t PRPD; /* Power Reduction Port D */ - register8_t PRPE; /* Power Reduction Port E */ - register8_t PRPF; /* Power Reduction Port F */ -} PR_t; - -/* System Clock Selection */ -typedef enum CLK_SCLKSEL_enum -{ - CLK_SCLKSEL_RC2M_gc = (0x00<<0), /* Internal 2MHz RC Oscillator */ - CLK_SCLKSEL_RC32M_gc = (0x01<<0), /* Internal 32MHz RC Oscillator */ - CLK_SCLKSEL_RC32K_gc = (0x02<<0), /* Internal 32kHz RC Oscillator */ - CLK_SCLKSEL_XOSC_gc = (0x03<<0), /* External Crystal Oscillator or Clock */ - CLK_SCLKSEL_PLL_gc = (0x04<<0), /* Phase Locked Loop */ -} CLK_SCLKSEL_t; - -/* Prescaler A Division Factor */ -typedef enum CLK_PSADIV_enum -{ - CLK_PSADIV_1_gc = (0x00<<2), /* Divide by 1 */ - CLK_PSADIV_2_gc = (0x01<<2), /* Divide by 2 */ - CLK_PSADIV_4_gc = (0x03<<2), /* Divide by 4 */ - CLK_PSADIV_8_gc = (0x05<<2), /* Divide by 8 */ - CLK_PSADIV_16_gc = (0x07<<2), /* Divide by 16 */ - CLK_PSADIV_32_gc = (0x09<<2), /* Divide by 32 */ - CLK_PSADIV_64_gc = (0x0B<<2), /* Divide by 64 */ - CLK_PSADIV_128_gc = (0x0D<<2), /* Divide by 128 */ - CLK_PSADIV_256_gc = (0x0F<<2), /* Divide by 256 */ - CLK_PSADIV_512_gc = (0x11<<2), /* Divide by 512 */ -} CLK_PSADIV_t; - -/* Prescaler B and C Division Factor */ -typedef enum CLK_PSBCDIV_enum -{ - CLK_PSBCDIV_1_1_gc = (0x00<<0), /* Divide B by 1 and C by 1 */ - CLK_PSBCDIV_1_2_gc = (0x01<<0), /* Divide B by 1 and C by 2 */ - CLK_PSBCDIV_4_1_gc = (0x02<<0), /* Divide B by 4 and C by 1 */ - CLK_PSBCDIV_2_2_gc = (0x03<<0), /* Divide B by 2 and C by 2 */ -} CLK_PSBCDIV_t; - -/* RTC Clock Source */ -typedef enum CLK_RTCSRC_enum -{ - CLK_RTCSRC_ULP_gc = (0x00<<1), /* 1kHz from internal 32kHz ULP */ - CLK_RTCSRC_TOSC_gc = (0x01<<1), /* 1kHz from 32kHz crystal oscillator on TOSC */ - CLK_RTCSRC_RCOSC_gc = (0x02<<1), /* 1kHz from internal 32kHz RC oscillator */ - CLK_RTCSRC_TOSC32_gc = (0x05<<1), /* 32kHz from 32kHz crystal oscillator on TOSC */ -} CLK_RTCSRC_t; - - -/* --------------------------------------------------------------------------- -SLEEP - Sleep Controller --------------------------------------------------------------------------- -*/ - -/* Sleep Controller */ -typedef struct SLEEP_struct -{ - register8_t CTRL; /* Control Register */ -} SLEEP_t; - -/* Sleep Mode */ -typedef enum SLEEP_SMODE_enum -{ - SLEEP_SMODE_IDLE_gc = (0x00<<1), /* Idle mode */ - SLEEP_SMODE_PDOWN_gc = (0x02<<1), /* Power-down Mode */ - SLEEP_SMODE_PSAVE_gc = (0x03<<1), /* Power-save Mode */ - SLEEP_SMODE_STDBY_gc = (0x06<<1), /* Standby Mode */ - SLEEP_SMODE_ESTDBY_gc = (0x07<<1), /* Extended Standby Mode */ -} SLEEP_SMODE_t; - - -#define SLEEP_MODE_IDLE (0x00<<1) -#define SLEEP_MODE_PWR_DOWN (0x02<<1) -#define SLEEP_MODE_PWR_SAVE (0x03<<1) -#define SLEEP_MODE_STANDBY (0x06<<1) -#define SLEEP_MODE_EXT_STANDBY (0x07<<1) - - -/* --------------------------------------------------------------------------- -OSC - Oscillator --------------------------------------------------------------------------- -*/ - -/* Oscillator */ -typedef struct OSC_struct -{ - register8_t CTRL; /* Control Register */ - register8_t STATUS; /* Status Register */ - register8_t XOSCCTRL; /* External Oscillator Control Register */ - register8_t XOSCFAIL; /* External Oscillator Failure Detection Register */ - register8_t RC32KCAL; /* 32kHz Internal Oscillator Calibration Register */ - register8_t PLLCTRL; /* PLL Control REgister */ - register8_t DFLLCTRL; /* DFLL Control Register */ -} OSC_t; - -/* Oscillator Frequency Range */ -typedef enum OSC_FRQRANGE_enum -{ - OSC_FRQRANGE_04TO2_gc = (0x00<<6), /* 0.4 - 2 MHz */ - OSC_FRQRANGE_2TO9_gc = (0x01<<6), /* 2 - 9 MHz */ - OSC_FRQRANGE_9TO12_gc = (0x02<<6), /* 9 - 12 MHz */ - OSC_FRQRANGE_12TO16_gc = (0x03<<6), /* 12 - 16 MHz */ -} OSC_FRQRANGE_t; - -/* External Oscillator Selection and Startup Time */ -typedef enum OSC_XOSCSEL_enum -{ - OSC_XOSCSEL_EXTCLK_gc = (0x00<<0), /* External Clock - 6 CLK */ - OSC_XOSCSEL_32KHz_gc = (0x02<<0), /* 32kHz TOSC - 32K CLK */ - OSC_XOSCSEL_XTAL_256CLK_gc = (0x03<<0), /* 0.4-16MHz XTAL - 256 CLK */ - OSC_XOSCSEL_XTAL_1KCLK_gc = (0x07<<0), /* 0.4-16MHz XTAL - 1K CLK */ - OSC_XOSCSEL_XTAL_16KCLK_gc = (0x0B<<0), /* 0.4-16MHz XTAL - 16K CLK */ -} OSC_XOSCSEL_t; - -/* PLL Clock Source */ -typedef enum OSC_PLLSRC_enum -{ - OSC_PLLSRC_RC2M_gc = (0x00<<6), /* Internal 2MHz RC Oscillator */ - OSC_PLLSRC_RC32M_gc = (0x02<<6), /* Internal 32MHz RC Oscillator */ - OSC_PLLSRC_XOSC_gc = (0x03<<6), /* External Oscillator */ -} OSC_PLLSRC_t; - - -/* --------------------------------------------------------------------------- -DFLL - DFLL --------------------------------------------------------------------------- -*/ - -/* DFLL */ -typedef struct DFLL_struct -{ - register8_t CTRL; /* Control Register */ - register8_t reserved_0x01; - register8_t CALA; /* Calibration Register A */ - register8_t CALB; /* Calibration Register B */ - register8_t COMP0; /* Oscillator Compare Register 0 */ - register8_t COMP1; /* Oscillator Compare Register 1 */ - register8_t COMP2; /* Oscillator Compare Register 2 */ - register8_t reserved_0x07; -} DFLL_t; - - -/* --------------------------------------------------------------------------- -RST - Reset --------------------------------------------------------------------------- -*/ - -/* Reset */ -typedef struct RST_struct -{ - register8_t STATUS; /* Status Register */ - register8_t CTRL; /* Control Register */ -} RST_t; - - -/* --------------------------------------------------------------------------- -WDT - Watch-Dog Timer --------------------------------------------------------------------------- -*/ - -/* Watch-Dog Timer */ -typedef struct WDT_struct -{ - register8_t CTRL; /* Control */ - register8_t WINCTRL; /* Windowed Mode Control */ - register8_t STATUS; /* Status */ -} WDT_t; - -/* Period setting */ -typedef enum WDT_PER_enum -{ - WDT_PER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ - WDT_PER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ - WDT_PER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ - WDT_PER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ - WDT_PER_128CLK_gc = (0x04<<2), /* 128 cycles (0.125s @ 3.3V) */ - WDT_PER_256CLK_gc = (0x05<<2), /* 256 cycles (0.25s @ 3.3V) */ - WDT_PER_512CLK_gc = (0x06<<2), /* 512 cycles (0.5s @ 3.3V) */ - WDT_PER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ - WDT_PER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ - WDT_PER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ - WDT_PER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ -} WDT_PER_t; - -/* Closed window period */ -typedef enum WDT_WPER_enum -{ - WDT_WPER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ - WDT_WPER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ - WDT_WPER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ - WDT_WPER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ - WDT_WPER_128CLK_gc = (0x04<<2), /* 128 cycles (0.125s @ 3.3V) */ - WDT_WPER_256CLK_gc = (0x05<<2), /* 256 cycles (0.25s @ 3.3V) */ - WDT_WPER_512CLK_gc = (0x06<<2), /* 512 cycles (0.5s @ 3.3V) */ - WDT_WPER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ - WDT_WPER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ - WDT_WPER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ - WDT_WPER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ -} WDT_WPER_t; - - -/* --------------------------------------------------------------------------- -MCU - MCU Control --------------------------------------------------------------------------- -*/ - -/* MCU Control */ -typedef struct MCU_struct -{ - register8_t DEVID0; /* Device ID byte 0 */ - register8_t DEVID1; /* Device ID byte 1 */ - register8_t DEVID2; /* Device ID byte 2 */ - register8_t REVID; /* Revision ID */ - register8_t JTAGUID; /* JTAG User ID */ - register8_t reserved_0x05; - register8_t MCUCR; /* MCU Control */ - register8_t reserved_0x07; - register8_t EVSYSLOCK; /* Event System Lock */ - register8_t AWEXLOCK; /* AWEX Lock */ - register8_t reserved_0x0A; - register8_t reserved_0x0B; -} MCU_t; - - -/* --------------------------------------------------------------------------- -PMIC - Programmable Multi-level Interrupt Controller --------------------------------------------------------------------------- -*/ - -/* Programmable Multi-level Interrupt Controller */ -typedef struct PMIC_struct -{ - register8_t STATUS; /* Status Register */ - register8_t INTPRI; /* Interrupt Priority */ - register8_t CTRL; /* Control Register */ -} PMIC_t; - - -/* --------------------------------------------------------------------------- -DMA - DMA Controller --------------------------------------------------------------------------- -*/ - -/* DMA Channel */ -typedef struct DMA_CH_struct -{ - register8_t CTRLA; /* Channel Control */ - register8_t CTRLB; /* Channel Control */ - register8_t ADDRCTRL; /* Address Control */ - register8_t TRIGSRC; /* Channel Trigger Source */ - _WORDREGISTER(TRFCNT); /* Channel Block Transfer Count */ - register8_t REPCNT; /* Channel Repeat Count */ - register8_t reserved_0x07; - register8_t SRCADDR0; /* Channel Source Address 0 */ - register8_t SRCADDR1; /* Channel Source Address 1 */ - register8_t SRCADDR2; /* Channel Source Address 2 */ - register8_t reserved_0x0B; - register8_t DESTADDR0; /* Channel Destination Address 0 */ - register8_t DESTADDR1; /* Channel Destination Address 1 */ - register8_t DESTADDR2; /* Channel Destination Address 2 */ - register8_t reserved_0x0F; -} DMA_CH_t; - -/* --------------------------------------------------------------------------- -DMA - DMA Controller --------------------------------------------------------------------------- -*/ - -/* DMA Controller */ -typedef struct DMA_struct -{ - register8_t CTRL; /* Control */ - register8_t reserved_0x01; - register8_t reserved_0x02; - register8_t INTFLAGS; /* Transfer Interrupt Status */ - register8_t STATUS; /* Status */ - register8_t reserved_0x05; - _WORDREGISTER(TEMP); /* Temporary Register For 16/24-bit Access */ - register8_t reserved_0x08; - register8_t reserved_0x09; - register8_t reserved_0x0A; - register8_t reserved_0x0B; - register8_t reserved_0x0C; - register8_t reserved_0x0D; - register8_t reserved_0x0E; - register8_t reserved_0x0F; - DMA_CH_t CH0; /* DMA Channel 0 */ - DMA_CH_t CH1; /* DMA Channel 1 */ - DMA_CH_t CH2; /* DMA Channel 2 */ - DMA_CH_t CH3; /* DMA Channel 3 */ -} DMA_t; - -/* Burst mode */ -typedef enum DMA_CH_BURSTLEN_enum -{ - DMA_CH_BURSTLEN_1BYTE_gc = (0x00<<0), /* 1-byte burst mode */ - DMA_CH_BURSTLEN_2BYTE_gc = (0x01<<0), /* 2-byte burst mode */ - DMA_CH_BURSTLEN_4BYTE_gc = (0x02<<0), /* 4-byte burst mode */ - DMA_CH_BURSTLEN_8BYTE_gc = (0x03<<0), /* 8-byte burst mode */ -} DMA_CH_BURSTLEN_t; - -/* Source address reload mode */ -typedef enum DMA_CH_SRCRELOAD_enum -{ - DMA_CH_SRCRELOAD_NONE_gc = (0x00<<6), /* No reload */ - DMA_CH_SRCRELOAD_BLOCK_gc = (0x01<<6), /* Reload at end of block */ - DMA_CH_SRCRELOAD_BURST_gc = (0x02<<6), /* Reload at end of burst */ - DMA_CH_SRCRELOAD_TRANSACTION_gc = (0x03<<6), /* Reload at end of transaction */ -} DMA_CH_SRCRELOAD_t; - -/* Source addressing mode */ -typedef enum DMA_CH_SRCDIR_enum -{ - DMA_CH_SRCDIR_FIXED_gc = (0x00<<4), /* Fixed */ - DMA_CH_SRCDIR_INC_gc = (0x01<<4), /* Increment */ - DMA_CH_SRCDIR_DEC_gc = (0x02<<4), /* Decrement */ -} DMA_CH_SRCDIR_t; - -/* Destination adress reload mode */ -typedef enum DMA_CH_DESTRELOAD_enum -{ - DMA_CH_DESTRELOAD_NONE_gc = (0x00<<2), /* No reload */ - DMA_CH_DESTRELOAD_BLOCK_gc = (0x01<<2), /* Reload at end of block */ - DMA_CH_DESTRELOAD_BURST_gc = (0x02<<2), /* Reload at end of burst */ - DMA_CH_DESTRELOAD_TRANSACTION_gc = (0x03<<2), /* Reload at end of transaction */ -} DMA_CH_DESTRELOAD_t; - -/* Destination adressing mode */ -typedef enum DMA_CH_DESTDIR_enum -{ - DMA_CH_DESTDIR_FIXED_gc = (0x00<<0), /* Fixed */ - DMA_CH_DESTDIR_INC_gc = (0x01<<0), /* Increment */ - DMA_CH_DESTDIR_DEC_gc = (0x02<<0), /* Decrement */ -} DMA_CH_DESTDIR_t; - -/* Transfer trigger source */ -typedef enum DMA_CH_TRIGSRC_enum -{ - DMA_CH_TRIGSRC_OFF_gc = (0x00<<0), /* Off software triggers only */ - DMA_CH_TRIGSRC_EVSYS_CH0_gc = (0x01<<0), /* Event System Channel 0 */ - DMA_CH_TRIGSRC_EVSYS_CH1_gc = (0x02<<0), /* Event System Channel 1 */ - DMA_CH_TRIGSRC_EVSYS_CH2_gc = (0x03<<0), /* Event System Channel 2 */ - DMA_CH_TRIGSRC_ADCA_CH0_gc = (0x10<<0), /* ADCA Channel 0 */ - DMA_CH_TRIGSRC_ADCA_CH1_gc = (0x11<<0), /* ADCA Channel 1 */ - DMA_CH_TRIGSRC_ADCA_CH2_gc = (0x12<<0), /* ADCA Channel 2 */ - DMA_CH_TRIGSRC_ADCA_CH3_gc = (0x13<<0), /* ADCA Channel 3 */ - DMA_CH_TRIGSRC_ADCA_CH4_gc = (0x14<<0), /* ADCA Channel 0,1,2,3 combined */ - DMA_CH_TRIGSRC_DACA_CH0_gc = (0x15<<0), /* DACA Channel 0 */ - DMA_CH_TRIGSRC_DACA_CH1_gc = (0x16<<0), /* DACA Channel 1 */ - DMA_CH_TRIGSRC_ADCB_CH0_gc = (0x20<<0), /* ADCB Channel 0 */ - DMA_CH_TRIGSRC_ADCB_CH1_gc = (0x21<<0), /* ADCB Channel 1 */ - DMA_CH_TRIGSRC_ADCB_CH2_gc = (0x22<<0), /* ADCB Channel 2 */ - DMA_CH_TRIGSRC_ADCB_CH3_gc = (0x23<<0), /* ADCB Channel 3 */ - DMA_CH_TRIGSRC_ADCB_CH4_gc = (0x24<<0), /* ADCB Channel 0,1,2,3 combined */ - DMA_CH_TRIGSRC_DACB_CH0_gc = (0x25<<0), /* DACB Channel 0 */ - DMA_CH_TRIGSRC_DACB_CH1_gc = (0x26<<0), /* DACB Channel 1 */ - DMA_CH_TRIGSRC_TCC0_OVF_gc = (0x40<<0), /* Timer/Counter C0 Overflow */ - DMA_CH_TRIGSRC_TCC0_ERR_gc = (0x41<<0), /* Timer/Counter C0 Error */ - DMA_CH_TRIGSRC_TCC0_CCA_gc = (0x42<<0), /* Timer/Counter C0 Compare or Capture A */ - DMA_CH_TRIGSRC_TCC0_CCB_gc = (0x43<<0), /* Timer/Counter C0 Compare or Capture B */ - DMA_CH_TRIGSRC_TCC0_CCC_gc = (0x44<<0), /* Timer/Counter C0 Compare or Capture C */ - DMA_CH_TRIGSRC_TCC0_CCD_gc = (0x45<<0), /* Timer/Counter C0 Compare or Capture D */ - DMA_CH_TRIGSRC_TCC1_OVF_gc = (0x46<<0), /* Timer/Counter C1 Overflow */ - DMA_CH_TRIGSRC_TCC1_ERR_gc = (0x47<<0), /* Timer/Counter C1 Error */ - DMA_CH_TRIGSRC_TCC1_CCA_gc = (0x48<<0), /* Timer/Counter C1 Compare or Capture A */ - DMA_CH_TRIGSRC_TCC1_CCB_gc = (0x49<<0), /* Timer/Counter C1 Compare or Capture B */ - DMA_CH_TRIGSRC_SPIC_gc = (0x4A<<0), /* SPI C Transfer Complete */ - DMA_CH_TRIGSRC_USARTC0_RXC_gc = (0x4B<<0), /* USART C0 Receive Complete */ - DMA_CH_TRIGSRC_USARTC0_DRE_gc = (0x4C<<0), /* USART C0 Data Register Empty */ - DMA_CH_TRIGSRC_USARTC1_RXC_gc = (0x4E<<0), /* USART C1 Receive Complete */ - DMA_CH_TRIGSRC_USARTC1_DRE_gc = (0x4F<<0), /* USART C1 Data Register Empty */ - DMA_CH_TRIGSRC_TCD0_OVF_gc = (0x60<<0), /* Timer/Counter D0 Overflow */ - DMA_CH_TRIGSRC_TCD0_ERR_gc = (0x61<<0), /* Timer/Counter D0 Error */ - DMA_CH_TRIGSRC_TCD0_CCA_gc = (0x62<<0), /* Timer/Counter D0 Compare or Capture A */ - DMA_CH_TRIGSRC_TCD0_CCB_gc = (0x63<<0), /* Timer/Counter D0 Compare or Capture B */ - DMA_CH_TRIGSRC_TCD0_CCC_gc = (0x64<<0), /* Timer/Counter D0 Compare or Capture C */ - DMA_CH_TRIGSRC_TCD0_CCD_gc = (0x65<<0), /* Timer/Counter D0 Compare or Capture D */ - DMA_CH_TRIGSRC_TCD1_OVF_gc = (0x66<<0), /* Timer/Counter D1 Overflow */ - DMA_CH_TRIGSRC_TCD1_ERR_gc = (0x67<<0), /* Timer/Counter D1 Error */ - DMA_CH_TRIGSRC_TCD1_CCA_gc = (0x68<<0), /* Timer/Counter D1 Compare or Capture A */ - DMA_CH_TRIGSRC_TCD1_CCB_gc = (0x69<<0), /* Timer/Counter D1 Compare or Capture B */ - DMA_CH_TRIGSRC_SPID_gc = (0x6A<<0), /* SPI D Transfer Complete */ - DMA_CH_TRIGSRC_USARTD0_RXC_gc = (0x6B<<0), /* USART D0 Receive Complete */ - DMA_CH_TRIGSRC_USARTD0_DRE_gc = (0x6C<<0), /* USART D0 Data Register Empty */ - DMA_CH_TRIGSRC_USARTD1_RXC_gc = (0x6E<<0), /* USART D1 Receive Complete */ - DMA_CH_TRIGSRC_USARTD1_DRE_gc = (0x6F<<0), /* USART D1 Data Register Empty */ - DMA_CH_TRIGSRC_TCE0_OVF_gc = (0x80<<0), /* Timer/Counter E0 Overflow */ - DMA_CH_TRIGSRC_TCE0_ERR_gc = (0x81<<0), /* Timer/Counter E0 Error */ - DMA_CH_TRIGSRC_TCE0_CCA_gc = (0x82<<0), /* Timer/Counter E0 Compare or Capture A */ - DMA_CH_TRIGSRC_TCE0_CCB_gc = (0x83<<0), /* Timer/Counter E0 Compare or Capture B */ - DMA_CH_TRIGSRC_TCE0_CCC_gc = (0x84<<0), /* Timer/Counter E0 Compare or Capture C */ - DMA_CH_TRIGSRC_TCE0_CCD_gc = (0x85<<0), /* Timer/Counter E0 Compare or Capture D */ - DMA_CH_TRIGSRC_TCE1_OVF_gc = (0x86<<0), /* Timer/Counter E1 Overflow */ - DMA_CH_TRIGSRC_TCE1_ERR_gc = (0x87<<0), /* Timer/Counter E1 Error */ - DMA_CH_TRIGSRC_TCE1_CCA_gc = (0x88<<0), /* Timer/Counter E1 Compare or Capture A */ - DMA_CH_TRIGSRC_TCE1_CCB_gc = (0x89<<0), /* Timer/Counter E1 Compare or Capture B */ - DMA_CH_TRIGSRC_SPIE_gc = (0x8A<<0), /* SPI E Transfer Complete */ - DMA_CH_TRIGSRC_USARTE0_RXC_gc = (0x8B<<0), /* USART E0 Receive Complete */ - DMA_CH_TRIGSRC_USARTE0_DRE_gc = (0x8C<<0), /* USART E0 Data Register Empty */ - DMA_CH_TRIGSRC_USARTE1_RXC_gc = (0x8E<<0), /* USART E1 Receive Complete */ - DMA_CH_TRIGSRC_USARTE1_DRE_gc = (0x8F<<0), /* USART E1 Data Register Empty */ - DMA_CH_TRIGSRC_TCF0_OVF_gc = (0xA0<<0), /* Timer/Counter F0 Overflow */ - DMA_CH_TRIGSRC_TCF0_ERR_gc = (0xA1<<0), /* Timer/Counter F0 Error */ - DMA_CH_TRIGSRC_TCF0_CCA_gc = (0xA2<<0), /* Timer/Counter F0 Compare or Capture A */ - DMA_CH_TRIGSRC_TCF0_CCB_gc = (0xA3<<0), /* Timer/Counter F0 Compare or Capture B */ - DMA_CH_TRIGSRC_TCF0_CCC_gc = (0xA4<<0), /* Timer/Counter F0 Compare or Capture C */ - DMA_CH_TRIGSRC_TCF0_CCD_gc = (0xA5<<0), /* Timer/Counter F0 Compare or Capture D */ - DMA_CH_TRIGSRC_TCF1_OVF_gc = (0xA6<<0), /* Timer/Counter F1 Overflow */ - DMA_CH_TRIGSRC_TCF1_ERR_gc = (0xA7<<0), /* Timer/Counter F1 Error */ - DMA_CH_TRIGSRC_TCF1_CCA_gc = (0xA8<<0), /* Timer/Counter F1 Compare or Capture A */ - DMA_CH_TRIGSRC_TCF1_CCB_gc = (0xA9<<0), /* Timer/Counter F1 Compare or Capture B */ - DMA_CH_TRIGSRC_SPIF_gc = (0xAA<<0), /* SPI F Transfer Complete */ - DMA_CH_TRIGSRC_USARTF0_RXC_gc = (0xAB<<0), /* USART F0 Receive Complete */ - DMA_CH_TRIGSRC_USARTF0_DRE_gc = (0xAC<<0), /* USART F0 Data Register Empty */ - DMA_CH_TRIGSRC_USARTF1_RXC_gc = (0xAE<<0), /* USART F1 Receive Complete */ - DMA_CH_TRIGSRC_USARTF1_DRE_gc = (0xAF<<0), /* USART F1 Data Register Empty */ -} DMA_CH_TRIGSRC_t; - -/* Double buffering mode */ -typedef enum DMA_DBUFMODE_enum -{ - DMA_DBUFMODE_DISABLED_gc = (0x00<<2), /* Double buffering disabled */ - DMA_DBUFMODE_CH01_gc = (0x01<<2), /* Double buffering enabled on channel 0/1 */ - DMA_DBUFMODE_CH23_gc = (0x02<<2), /* Double buffering enabled on channel 2/3 */ - DMA_DBUFMODE_CH01CH23_gc = (0x03<<2), /* Double buffering enabled on ch. 0/1 and ch. 2/3 */ -} DMA_DBUFMODE_t; - -/* Priority mode */ -typedef enum DMA_PRIMODE_enum -{ - DMA_PRIMODE_RR0123_gc = (0x00<<0), /* Round Robin */ - DMA_PRIMODE_CH0RR123_gc = (0x01<<0), /* Channel 0 > Round Robin on channel 1/2/3 */ - DMA_PRIMODE_CH01RR23_gc = (0x02<<0), /* Channel 0 > channel 1 > Round Robin on channel 2/3 */ - DMA_PRIMODE_CH0123_gc = (0x03<<0), /* Channel 0 > channel 1 > channel 2 > channel 3 */ -} DMA_PRIMODE_t; - -/* Interrupt level */ -typedef enum DMA_CH_ERRINTLVL_enum -{ - DMA_CH_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ - DMA_CH_ERRINTLVL_LO_gc = (0x01<<2), /* Low level */ - DMA_CH_ERRINTLVL_MED_gc = (0x02<<2), /* Medium level */ - DMA_CH_ERRINTLVL_HI_gc = (0x03<<2), /* High level */ -} DMA_CH_ERRINTLVL_t; - -/* Interrupt level */ -typedef enum DMA_CH_TRNINTLVL_enum -{ - DMA_CH_TRNINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ - DMA_CH_TRNINTLVL_LO_gc = (0x01<<0), /* Low level */ - DMA_CH_TRNINTLVL_MED_gc = (0x02<<0), /* Medium level */ - DMA_CH_TRNINTLVL_HI_gc = (0x03<<0), /* High level */ -} DMA_CH_TRNINTLVL_t; - - -/* --------------------------------------------------------------------------- -EVSYS - Event System --------------------------------------------------------------------------- -*/ - -/* Event System */ -typedef struct EVSYS_struct -{ - register8_t CH0MUX; /* Event Channel 0 Multiplexer */ - register8_t CH1MUX; /* Event Channel 1 Multiplexer */ - register8_t CH2MUX; /* Event Channel 2 Multiplexer */ - register8_t CH3MUX; /* Event Channel 3 Multiplexer */ - register8_t CH4MUX; /* Event Channel 4 Multiplexer */ - register8_t CH5MUX; /* Event Channel 5 Multiplexer */ - register8_t CH6MUX; /* Event Channel 6 Multiplexer */ - register8_t CH7MUX; /* Event Channel 7 Multiplexer */ - register8_t CH0CTRL; /* Channel 0 Control Register */ - register8_t CH1CTRL; /* Channel 1 Control Register */ - register8_t CH2CTRL; /* Channel 2 Control Register */ - register8_t CH3CTRL; /* Channel 3 Control Register */ - register8_t CH4CTRL; /* Channel 4 Control Register */ - register8_t CH5CTRL; /* Channel 5 Control Register */ - register8_t CH6CTRL; /* Channel 6 Control Register */ - register8_t CH7CTRL; /* Channel 7 Control Register */ - register8_t STROBE; /* Event Strobe */ - register8_t DATA; /* Event Data */ -} EVSYS_t; - -/* Quadrature Decoder Index Recognition Mode */ -typedef enum EVSYS_QDIRM_enum -{ - EVSYS_QDIRM_00_gc = (0x00<<5), /* QDPH0 = 0, QDPH90 = 0 */ - EVSYS_QDIRM_01_gc = (0x01<<5), /* QDPH0 = 0, QDPH90 = 1 */ - EVSYS_QDIRM_10_gc = (0x02<<5), /* QDPH0 = 1, QDPH90 = 0 */ - EVSYS_QDIRM_11_gc = (0x03<<5), /* QDPH0 = 1, QDPH90 = 1 */ -} EVSYS_QDIRM_t; - -/* Digital filter coefficient */ -typedef enum EVSYS_DIGFILT_enum -{ - EVSYS_DIGFILT_1SAMPLE_gc = (0x00<<0), /* 1 SAMPLE */ - EVSYS_DIGFILT_2SAMPLES_gc = (0x01<<0), /* 2 SAMPLES */ - EVSYS_DIGFILT_3SAMPLES_gc = (0x02<<0), /* 3 SAMPLES */ - EVSYS_DIGFILT_4SAMPLES_gc = (0x03<<0), /* 4 SAMPLES */ - EVSYS_DIGFILT_5SAMPLES_gc = (0x04<<0), /* 5 SAMPLES */ - EVSYS_DIGFILT_6SAMPLES_gc = (0x05<<0), /* 6 SAMPLES */ - EVSYS_DIGFILT_7SAMPLES_gc = (0x06<<0), /* 7 SAMPLES */ - EVSYS_DIGFILT_8SAMPLES_gc = (0x07<<0), /* 8 SAMPLES */ -} EVSYS_DIGFILT_t; - -/* Event Channel multiplexer input selection */ -typedef enum EVSYS_CHMUX_enum -{ - EVSYS_CHMUX_OFF_gc = (0x00<<0), /* Off */ - EVSYS_CHMUX_RTC_OVF_gc = (0x08<<0), /* RTC Overflow */ - EVSYS_CHMUX_RTC_CMP_gc = (0x09<<0), /* RTC Compare Match */ - EVSYS_CHMUX_ACA_CH0_gc = (0x10<<0), /* Analog Comparator A Channel 0 */ - EVSYS_CHMUX_ACA_CH1_gc = (0x11<<0), /* Analog Comparator A Channel 1 */ - EVSYS_CHMUX_ACA_WIN_gc = (0x12<<0), /* Analog Comparator A Window */ - EVSYS_CHMUX_ACB_CH0_gc = (0x13<<0), /* Analog Comparator B Channel 0 */ - EVSYS_CHMUX_ACB_CH1_gc = (0x14<<0), /* Analog Comparator B Channel 1 */ - EVSYS_CHMUX_ACB_WIN_gc = (0x15<<0), /* Analog Comparator B Window */ - EVSYS_CHMUX_ADCA_CH0_gc = (0x20<<0), /* ADC A Channel 0 */ - EVSYS_CHMUX_ADCA_CH1_gc = (0x21<<0), /* ADC A Channel 1 */ - EVSYS_CHMUX_ADCA_CH2_gc = (0x22<<0), /* ADC A Channel 2 */ - EVSYS_CHMUX_ADCA_CH3_gc = (0x23<<0), /* ADC A Channel 3 */ - EVSYS_CHMUX_ADCB_CH0_gc = (0x24<<0), /* ADC B Channel 0 */ - EVSYS_CHMUX_ADCB_CH1_gc = (0x25<<0), /* ADC B Channel 1 */ - EVSYS_CHMUX_ADCB_CH2_gc = (0x26<<0), /* ADC B Channel 2 */ - EVSYS_CHMUX_ADCB_CH3_gc = (0x27<<0), /* ADC B Channel 3 */ - EVSYS_CHMUX_PORTA_PIN0_gc = (0x50<<0), /* Port A, Pin0 */ - EVSYS_CHMUX_PORTA_PIN1_gc = (0x51<<0), /* Port A, Pin1 */ - EVSYS_CHMUX_PORTA_PIN2_gc = (0x52<<0), /* Port A, Pin2 */ - EVSYS_CHMUX_PORTA_PIN3_gc = (0x53<<0), /* Port A, Pin3 */ - EVSYS_CHMUX_PORTA_PIN4_gc = (0x54<<0), /* Port A, Pin4 */ - EVSYS_CHMUX_PORTA_PIN5_gc = (0x55<<0), /* Port A, Pin5 */ - EVSYS_CHMUX_PORTA_PIN6_gc = (0x56<<0), /* Port A, Pin6 */ - EVSYS_CHMUX_PORTA_PIN7_gc = (0x57<<0), /* Port A, Pin7 */ - EVSYS_CHMUX_PORTB_PIN0_gc = (0x58<<0), /* Port B, Pin0 */ - EVSYS_CHMUX_PORTB_PIN1_gc = (0x59<<0), /* Port B, Pin1 */ - EVSYS_CHMUX_PORTB_PIN2_gc = (0x5A<<0), /* Port B, Pin2 */ - EVSYS_CHMUX_PORTB_PIN3_gc = (0x5B<<0), /* Port B, Pin3 */ - EVSYS_CHMUX_PORTB_PIN4_gc = (0x5C<<0), /* Port B, Pin4 */ - EVSYS_CHMUX_PORTB_PIN5_gc = (0x5D<<0), /* Port B, Pin5 */ - EVSYS_CHMUX_PORTB_PIN6_gc = (0x5E<<0), /* Port B, Pin6 */ - EVSYS_CHMUX_PORTB_PIN7_gc = (0x5F<<0), /* Port B, Pin7 */ - EVSYS_CHMUX_PORTC_PIN0_gc = (0x60<<0), /* Port C, Pin0 */ - EVSYS_CHMUX_PORTC_PIN1_gc = (0x61<<0), /* Port C, Pin1 */ - EVSYS_CHMUX_PORTC_PIN2_gc = (0x62<<0), /* Port C, Pin2 */ - EVSYS_CHMUX_PORTC_PIN3_gc = (0x63<<0), /* Port C, Pin3 */ - EVSYS_CHMUX_PORTC_PIN4_gc = (0x64<<0), /* Port C, Pin4 */ - EVSYS_CHMUX_PORTC_PIN5_gc = (0x65<<0), /* Port C, Pin5 */ - EVSYS_CHMUX_PORTC_PIN6_gc = (0x66<<0), /* Port C, Pin6 */ - EVSYS_CHMUX_PORTC_PIN7_gc = (0x67<<0), /* Port C, Pin7 */ - EVSYS_CHMUX_PORTD_PIN0_gc = (0x68<<0), /* Port D, Pin0 */ - EVSYS_CHMUX_PORTD_PIN1_gc = (0x69<<0), /* Port D, Pin1 */ - EVSYS_CHMUX_PORTD_PIN2_gc = (0x6A<<0), /* Port D, Pin2 */ - EVSYS_CHMUX_PORTD_PIN3_gc = (0x6B<<0), /* Port D, Pin3 */ - EVSYS_CHMUX_PORTD_PIN4_gc = (0x6C<<0), /* Port D, Pin4 */ - EVSYS_CHMUX_PORTD_PIN5_gc = (0x6D<<0), /* Port D, Pin5 */ - EVSYS_CHMUX_PORTD_PIN6_gc = (0x6E<<0), /* Port D, Pin6 */ - EVSYS_CHMUX_PORTD_PIN7_gc = (0x6F<<0), /* Port D, Pin7 */ - EVSYS_CHMUX_PORTE_PIN0_gc = (0x70<<0), /* Port E, Pin0 */ - EVSYS_CHMUX_PORTE_PIN1_gc = (0x71<<0), /* Port E, Pin1 */ - EVSYS_CHMUX_PORTE_PIN2_gc = (0x72<<0), /* Port E, Pin2 */ - EVSYS_CHMUX_PORTE_PIN3_gc = (0x73<<0), /* Port E, Pin3 */ - EVSYS_CHMUX_PORTE_PIN4_gc = (0x74<<0), /* Port E, Pin4 */ - EVSYS_CHMUX_PORTE_PIN5_gc = (0x75<<0), /* Port E, Pin5 */ - EVSYS_CHMUX_PORTE_PIN6_gc = (0x76<<0), /* Port E, Pin6 */ - EVSYS_CHMUX_PORTE_PIN7_gc = (0x77<<0), /* Port E, Pin7 */ - EVSYS_CHMUX_PORTF_PIN0_gc = (0x78<<0), /* Port F, Pin0 */ - EVSYS_CHMUX_PORTF_PIN1_gc = (0x79<<0), /* Port F, Pin1 */ - EVSYS_CHMUX_PORTF_PIN2_gc = (0x7A<<0), /* Port F, Pin2 */ - EVSYS_CHMUX_PORTF_PIN3_gc = (0x7B<<0), /* Port F, Pin3 */ - EVSYS_CHMUX_PORTF_PIN4_gc = (0x7C<<0), /* Port F, Pin4 */ - EVSYS_CHMUX_PORTF_PIN5_gc = (0x7D<<0), /* Port F, Pin5 */ - EVSYS_CHMUX_PORTF_PIN6_gc = (0x7E<<0), /* Port F, Pin6 */ - EVSYS_CHMUX_PORTF_PIN7_gc = (0x7F<<0), /* Port F, Pin7 */ - EVSYS_CHMUX_PRESCALER_1_gc = (0x80<<0), /* Prescaler, divide by 1 */ - EVSYS_CHMUX_PRESCALER_2_gc = (0x81<<0), /* Prescaler, divide by 2 */ - EVSYS_CHMUX_PRESCALER_4_gc = (0x82<<0), /* Prescaler, divide by 4 */ - EVSYS_CHMUX_PRESCALER_8_gc = (0x83<<0), /* Prescaler, divide by 8 */ - EVSYS_CHMUX_PRESCALER_16_gc = (0x84<<0), /* Prescaler, divide by 16 */ - EVSYS_CHMUX_PRESCALER_32_gc = (0x85<<0), /* Prescaler, divide by 32 */ - EVSYS_CHMUX_PRESCALER_64_gc = (0x86<<0), /* Prescaler, divide by 64 */ - EVSYS_CHMUX_PRESCALER_128_gc = (0x87<<0), /* Prescaler, divide by 128 */ - EVSYS_CHMUX_PRESCALER_256_gc = (0x88<<0), /* Prescaler, divide by 256 */ - EVSYS_CHMUX_PRESCALER_512_gc = (0x89<<0), /* Prescaler, divide by 512 */ - EVSYS_CHMUX_PRESCALER_1024_gc = (0x8A<<0), /* Prescaler, divide by 1024 */ - EVSYS_CHMUX_PRESCALER_2048_gc = (0x8B<<0), /* Prescaler, divide by 2048 */ - EVSYS_CHMUX_PRESCALER_4096_gc = (0x8C<<0), /* Prescaler, divide by 4096 */ - EVSYS_CHMUX_PRESCALER_8192_gc = (0x8D<<0), /* Prescaler, divide by 8192 */ - EVSYS_CHMUX_PRESCALER_16384_gc = (0x8E<<0), /* Prescaler, divide by 16384 */ - EVSYS_CHMUX_PRESCALER_32768_gc = (0x8F<<0), /* Prescaler, divide by 32768 */ - EVSYS_CHMUX_TCC0_OVF_gc = (0xC0<<0), /* Timer/Counter C0 Overflow */ - EVSYS_CHMUX_TCC0_ERR_gc = (0xC1<<0), /* Timer/Counter C0 Error */ - EVSYS_CHMUX_TCC0_CCA_gc = (0xC4<<0), /* Timer/Counter C0 Compare or Capture A */ - EVSYS_CHMUX_TCC0_CCB_gc = (0xC5<<0), /* Timer/Counter C0 Compare or Capture B */ - EVSYS_CHMUX_TCC0_CCC_gc = (0xC6<<0), /* Timer/Counter C0 Compare or Capture C */ - EVSYS_CHMUX_TCC0_CCD_gc = (0xC7<<0), /* Timer/Counter C0 Compare or Capture D */ - EVSYS_CHMUX_TCC1_OVF_gc = (0xC8<<0), /* Timer/Counter C1 Overflow */ - EVSYS_CHMUX_TCC1_ERR_gc = (0xC9<<0), /* Timer/Counter C1 Error */ - EVSYS_CHMUX_TCC1_CCA_gc = (0xCC<<0), /* Timer/Counter C1 Compare or Capture A */ - EVSYS_CHMUX_TCC1_CCB_gc = (0xCD<<0), /* Timer/Counter C1 Compare or Capture B */ - EVSYS_CHMUX_TCD0_OVF_gc = (0xD0<<0), /* Timer/Counter D0 Overflow */ - EVSYS_CHMUX_TCD0_ERR_gc = (0xD1<<0), /* Timer/Counter D0 Error */ - EVSYS_CHMUX_TCD0_CCA_gc = (0xD4<<0), /* Timer/Counter D0 Compare or Capture A */ - EVSYS_CHMUX_TCD0_CCB_gc = (0xD5<<0), /* Timer/Counter D0 Compare or Capture B */ - EVSYS_CHMUX_TCD0_CCC_gc = (0xD6<<0), /* Timer/Counter D0 Compare or Capture C */ - EVSYS_CHMUX_TCD0_CCD_gc = (0xD7<<0), /* Timer/Counter D0 Compare or Capture D */ - EVSYS_CHMUX_TCD1_OVF_gc = (0xD8<<0), /* Timer/Counter D1 Overflow */ - EVSYS_CHMUX_TCD1_ERR_gc = (0xD9<<0), /* Timer/Counter D1 Error */ - EVSYS_CHMUX_TCD1_CCA_gc = (0xDC<<0), /* Timer/Counter D1 Compare or Capture A */ - EVSYS_CHMUX_TCD1_CCB_gc = (0xDD<<0), /* Timer/Counter D1 Compare or Capture B */ - EVSYS_CHMUX_TCE0_OVF_gc = (0xE0<<0), /* Timer/Counter E0 Overflow */ - EVSYS_CHMUX_TCE0_ERR_gc = (0xE1<<0), /* Timer/Counter E0 Error */ - EVSYS_CHMUX_TCE0_CCA_gc = (0xE4<<0), /* Timer/Counter E0 Compare or Capture A */ - EVSYS_CHMUX_TCE0_CCB_gc = (0xE5<<0), /* Timer/Counter E0 Compare or Capture B */ - EVSYS_CHMUX_TCE0_CCC_gc = (0xE6<<0), /* Timer/Counter E0 Compare or Capture C */ - EVSYS_CHMUX_TCE0_CCD_gc = (0xE7<<0), /* Timer/Counter E0 Compare or Capture D */ - EVSYS_CHMUX_TCE1_OVF_gc = (0xE8<<0), /* Timer/Counter E1 Overflow */ - EVSYS_CHMUX_TCE1_ERR_gc = (0xE9<<0), /* Timer/Counter E1 Error */ - EVSYS_CHMUX_TCE1_CCA_gc = (0xEC<<0), /* Timer/Counter E1 Compare or Capture A */ - EVSYS_CHMUX_TCE1_CCB_gc = (0xED<<0), /* Timer/Counter E1 Compare or Capture B */ - EVSYS_CHMUX_TCF0_OVF_gc = (0xF0<<0), /* Timer/Counter F0 Overflow */ - EVSYS_CHMUX_TCF0_ERR_gc = (0xF1<<0), /* Timer/Counter F0 Error */ - EVSYS_CHMUX_TCF0_CCA_gc = (0xF4<<0), /* Timer/Counter F0 Compare or Capture A */ - EVSYS_CHMUX_TCF0_CCB_gc = (0xF5<<0), /* Timer/Counter F0 Compare or Capture B */ - EVSYS_CHMUX_TCF0_CCC_gc = (0xF6<<0), /* Timer/Counter F0 Compare or Capture C */ - EVSYS_CHMUX_TCF0_CCD_gc = (0xF7<<0), /* Timer/Counter F0 Compare or Capture D */ - EVSYS_CHMUX_TCF1_OVF_gc = (0xF8<<0), /* Timer/Counter F1 Overflow */ - EVSYS_CHMUX_TCF1_ERR_gc = (0xF9<<0), /* Timer/Counter F1 Error */ - EVSYS_CHMUX_TCF1_CCA_gc = (0xFC<<0), /* Timer/Counter F1 Compare or Capture A */ - EVSYS_CHMUX_TCF1_CCB_gc = (0xFD<<0), /* Timer/Counter F1 Compare or Capture B */ -} EVSYS_CHMUX_t; - - -/* --------------------------------------------------------------------------- -NVM - Non Volatile Memory Controller --------------------------------------------------------------------------- -*/ - -/* Non-volatile Memory Controller */ -typedef struct NVM_struct -{ - register8_t ADDR0; /* Address Register 0 */ - register8_t ADDR1; /* Address Register 1 */ - register8_t ADDR2; /* Address Register 2 */ - register8_t reserved_0x03; - register8_t DATA0; /* Data Register 0 */ - register8_t DATA1; /* Data Register 1 */ - register8_t DATA2; /* Data Register 2 */ - register8_t reserved_0x07; - register8_t reserved_0x08; - register8_t reserved_0x09; - register8_t CMD; /* Command */ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t INTCTRL; /* Interrupt Control */ - register8_t reserved_0x0E; - register8_t STATUS; /* Status */ - register8_t LOCK_BITS; /* Lock Bits */ -} NVM_t; - -/* --------------------------------------------------------------------------- -NVM - Non Volatile Memory Controller --------------------------------------------------------------------------- -*/ - -/* Lock Bits */ -typedef struct NVM_LOCKBITS_struct -{ - register8_t LOCKBITS; /* Lock Bits */ -} NVM_LOCKBITS_t; - -/* --------------------------------------------------------------------------- -NVM - Non Volatile Memory Controller --------------------------------------------------------------------------- -*/ - -/* Fuses */ -typedef struct NVM_FUSES_struct -{ - register8_t FUSEBYTE0; /* JTAG User ID */ - register8_t FUSEBYTE1; /* Watchdog Configuration */ - register8_t FUSEBYTE2; /* Reset Configuration */ - register8_t reserved_0x03; - register8_t FUSEBYTE4; /* Start-up Configuration */ - register8_t FUSEBYTE5; /* EESAVE and BOD Level */ -} NVM_FUSES_t; - -/* --------------------------------------------------------------------------- -NVM - Non Volatile Memory Controller --------------------------------------------------------------------------- -*/ - -/* Production Signatures */ -typedef struct NVM_PROD_SIGNATURES_struct -{ - register8_t RCOSC2M; /* RCOSC 2MHz Calibration Value */ - register8_t reserved_0x01; - register8_t RCOSC32K; /* RCOSC 32kHz Calibration Value */ - register8_t RCOSC32M; /* RCOSC 32MHz Calibration Value */ - register8_t reserved_0x04; - register8_t reserved_0x05; - register8_t reserved_0x06; - register8_t reserved_0x07; - register8_t LOTNUM0; /* Lot Number Byte 0, ASCII */ - register8_t LOTNUM1; /* Lot Number Byte 1, ASCII */ - register8_t LOTNUM2; /* Lot Number Byte 2, ASCII */ - register8_t LOTNUM3; /* Lot Number Byte 3, ASCII */ - register8_t LOTNUM4; /* Lot Number Byte 4, ASCII */ - register8_t LOTNUM5; /* Lot Number Byte 5, ASCII */ - register8_t reserved_0x0E; - register8_t reserved_0x0F; - register8_t WAFNUM; /* Wafer Number */ - register8_t reserved_0x11; - register8_t COORDX0; /* Wafer Coordinate X Byte 0 */ - register8_t COORDX1; /* Wafer Coordinate X Byte 1 */ - register8_t COORDY0; /* Wafer Coordinate Y Byte 0 */ - register8_t COORDY1; /* Wafer Coordinate Y Byte 1 */ - register8_t reserved_0x16; - register8_t reserved_0x17; - register8_t reserved_0x18; - register8_t reserved_0x19; - register8_t reserved_0x1A; - register8_t reserved_0x1B; - register8_t reserved_0x1C; - register8_t reserved_0x1D; - register8_t reserved_0x1E; - register8_t reserved_0x1F; - register8_t ADCACAL0; /* ADCA Calibration Byte 0 */ - register8_t ADCACAL1; /* ADCA Calibration Byte 1 */ - register8_t reserved_0x22; - register8_t reserved_0x23; - register8_t ADCBCAL0; /* ADCB Calibration Byte 0 */ - register8_t ADCBCAL1; /* ADCB Calibration Byte 1 */ - register8_t reserved_0x26; - register8_t reserved_0x27; - register8_t reserved_0x28; - register8_t reserved_0x29; - register8_t reserved_0x2A; - register8_t reserved_0x2B; - register8_t reserved_0x2C; - register8_t reserved_0x2D; - register8_t TEMPSENSE0; /* Temperature Sensor Calibration Byte 0 */ - register8_t TEMPSENSE1; /* Temperature Sensor Calibration Byte 0 */ - register8_t DACAOFFCAL; /* DACA Calibration Byte 0 */ - register8_t DACAGAINCAL; /* DACA Calibration Byte 1 */ - register8_t DACBOFFCAL; /* DACB Calibration Byte 0 */ - register8_t DACBGAINCAL; /* DACB Calibration Byte 1 */ - register8_t reserved_0x34; - register8_t reserved_0x35; - register8_t reserved_0x36; - register8_t reserved_0x37; - register8_t reserved_0x38; - register8_t reserved_0x39; - register8_t reserved_0x3A; - register8_t reserved_0x3B; - register8_t reserved_0x3C; - register8_t reserved_0x3D; - register8_t reserved_0x3E; -} NVM_PROD_SIGNATURES_t; - -/* NVM Command */ -typedef enum NVM_CMD_enum -{ - NVM_CMD_NO_OPERATION_gc = (0x00<<0), /* Noop/Ordinary LPM */ - NVM_CMD_READ_CALIB_ROW_gc = (0x02<<0), /* Read calibration row */ - NVM_CMD_READ_USER_SIG_ROW_gc = (0x01<<0), /* Read user signature row */ - NVM_CMD_READ_EEPROM_gc = (0x06<<0), /* Read EEPROM */ - NVM_CMD_READ_FUSES_gc = (0x07<<0), /* Read fuse byte */ - NVM_CMD_WRITE_LOCK_BITS_gc = (0x08<<0), /* Write lock bits */ - NVM_CMD_ERASE_USER_SIG_ROW_gc = (0x18<<0), /* Erase user signature row */ - NVM_CMD_WRITE_USER_SIG_ROW_gc = (0x1A<<0), /* Write user signature row */ - NVM_CMD_ERASE_APP_gc = (0x20<<0), /* Erase Application Section */ - NVM_CMD_ERASE_APP_PAGE_gc = (0x22<<0), /* Erase Application Section page */ - NVM_CMD_LOAD_FLASH_BUFFER_gc = (0x23<<0), /* Load Flash page buffer */ - NVM_CMD_WRITE_APP_PAGE_gc = (0x24<<0), /* Write Application Section page */ - NVM_CMD_ERASE_WRITE_APP_PAGE_gc = (0x25<<0), /* Erase-and-write Application Section page */ - NVM_CMD_ERASE_FLASH_BUFFER_gc = (0x26<<0), /* Erase/flush Flash page buffer */ - NVM_CMD_ERASE_BOOT_PAGE_gc = (0x2A<<0), /* Erase Boot Section page */ - NVM_CMD_WRITE_BOOT_PAGE_gc = (0x2C<<0), /* Write Boot Section page */ - NVM_CMD_ERASE_WRITE_BOOT_PAGE_gc = (0x2D<<0), /* Erase-and-write Boot Section page */ - NVM_CMD_ERASE_EEPROM_gc = (0x30<<0), /* Erase EEPROM */ - NVM_CMD_ERASE_EEPROM_PAGE_gc = (0x32<<0), /* Erase EEPROM page */ - NVM_CMD_LOAD_EEPROM_BUFFER_gc = (0x33<<0), /* Load EEPROM page buffer */ - NVM_CMD_WRITE_EEPROM_PAGE_gc = (0x34<<0), /* Write EEPROM page */ - NVM_CMD_ERASE_WRITE_EEPROM_PAGE_gc = (0x35<<0), /* Erase-and-write EEPROM page */ - NVM_CMD_ERASE_EEPROM_BUFFER_gc = (0x36<<0), /* Erase/flush EEPROM page buffer */ - NVM_CMD_APP_CRC_gc = (0x38<<0), /* Generate Application section CRC */ - NVM_CMD_BOOT_CRC_gc = (0x39<<0), /* Generate Boot Section CRC */ - NVM_CMD_FLASH_RANGE_CRC_gc = (0x3A<<0), /* Generate Flash Range CRC */ -} NVM_CMD_t; - -/* SPM ready interrupt level */ -typedef enum NVM_SPMLVL_enum -{ - NVM_SPMLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ - NVM_SPMLVL_LO_gc = (0x01<<2), /* Low level */ - NVM_SPMLVL_MED_gc = (0x02<<2), /* Medium level */ - NVM_SPMLVL_HI_gc = (0x03<<2), /* High level */ -} NVM_SPMLVL_t; - -/* EEPROM ready interrupt level */ -typedef enum NVM_EELVL_enum -{ - NVM_EELVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ - NVM_EELVL_LO_gc = (0x01<<0), /* Low level */ - NVM_EELVL_MED_gc = (0x02<<0), /* Medium level */ - NVM_EELVL_HI_gc = (0x03<<0), /* High level */ -} NVM_EELVL_t; - -/* Boot lock bits - boot setcion */ -typedef enum NVM_BLBB_enum -{ - NVM_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ - NVM_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ - NVM_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ - NVM_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ -} NVM_BLBB_t; - -/* Boot lock bits - application section */ -typedef enum NVM_BLBA_enum -{ - NVM_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ - NVM_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ - NVM_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ - NVM_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ -} NVM_BLBA_t; - -/* Boot lock bits - application table section */ -typedef enum NVM_BLBAT_enum -{ - NVM_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ - NVM_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ - NVM_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ - NVM_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ -} NVM_BLBAT_t; - -/* Lock bits */ -typedef enum NVM_LB_enum -{ - NVM_LB_NOLOCK_gc = (0x03<<0), /* No locks */ - NVM_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ - NVM_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ -} NVM_LB_t; - -/* Boot Loader Section Reset Vector */ -typedef enum BOOTRST_enum -{ - BOOTRST_BOOTLDR_gc = (0x00<<6), /* Boot Loader Reset */ - BOOTRST_APPLICATION_gc = (0x01<<6), /* Application Reset */ -} BOOTRST_t; - -/* BOD operation */ -typedef enum BOD_enum -{ - BOD_INSAMPLEDMODE_gc = (0x01<<2), /* BOD enabled in sampled mode */ - BOD_CONTINOUSLY_gc = (0x02<<2), /* BOD enabled continuously */ - BOD_DISABLED_gc = (0x03<<2), /* BOD Disabled */ -} BOD_t; - -/* Watchdog (Window) Timeout Period */ -typedef enum WD_enum -{ - WD_8CLK_gc = (0x00<<4), /* 8 cycles (8ms @ 3.3V) */ - WD_16CLK_gc = (0x01<<4), /* 16 cycles (16ms @ 3.3V) */ - WD_32CLK_gc = (0x02<<4), /* 32 cycles (32ms @ 3.3V) */ - WD_64CLK_gc = (0x03<<4), /* 64 cycles (64ms @ 3.3V) */ - WD_128CLK_gc = (0x04<<4), /* 128 cycles (0.125s @ 3.3V) */ - WD_256CLK_gc = (0x05<<4), /* 256 cycles (0.25s @ 3.3V) */ - WD_512CLK_gc = (0x06<<4), /* 512 cycles (0.5s @ 3.3V) */ - WD_1KCLK_gc = (0x07<<4), /* 1K cycles (1s @ 3.3V) */ - WD_2KCLK_gc = (0x08<<4), /* 2K cycles (2s @ 3.3V) */ - WD_4KCLK_gc = (0x09<<4), /* 4K cycles (4s @ 3.3V) */ - WD_8KCLK_gc = (0x0A<<4), /* 8K cycles (8s @ 3.3V) */ -} WD_t; - -/* Start-up Time */ -typedef enum SUT_enum -{ - SUT_0MS_gc = (0x03<<2), /* 0 ms */ - SUT_4MS_gc = (0x01<<2), /* 4 ms */ - SUT_64MS_gc = (0x00<<2), /* 64 ms */ -} SUT_t; - -/* Brown Out Detection Voltage Level */ -typedef enum BODLVL_enum -{ - BODLVL_1V6_gc = (0x07<<0), /* 1.6 V */ - BODLVL_1V9_gc = (0x06<<0), /* 1.8 V */ - BODLVL_2V1_gc = (0x05<<0), /* 2.0 V */ - BODLVL_2V4_gc = (0x04<<0), /* 2.2 V */ - BODLVL_2V6_gc = (0x03<<0), /* 2.4 V */ - BODLVL_2V9_gc = (0x02<<0), /* 2.7 V */ - BODLVL_3V2_gc = (0x01<<0), /* 2.9 V */ -} BODLVL_t; - - -/* --------------------------------------------------------------------------- -AC - Analog Comparator --------------------------------------------------------------------------- -*/ - -/* Analog Comparator */ -typedef struct AC_struct -{ - register8_t AC0CTRL; /* Comparator 0 Control */ - register8_t AC1CTRL; /* Comparator 1 Control */ - register8_t AC0MUXCTRL; /* Comparator 0 MUX Control */ - register8_t AC1MUXCTRL; /* Comparator 1 MUX Control */ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t WINCTRL; /* Window Mode Control */ - register8_t STATUS; /* Status */ -} AC_t; - -/* Interrupt mode */ -typedef enum AC_INTMODE_enum -{ - AC_INTMODE_BOTHEDGES_gc = (0x00<<6), /* Interrupt on both edges */ - AC_INTMODE_FALLING_gc = (0x02<<6), /* Interrupt on falling edge */ - AC_INTMODE_RISING_gc = (0x03<<6), /* Interrupt on rising edge */ -} AC_INTMODE_t; - -/* Interrupt level */ -typedef enum AC_INTLVL_enum -{ - AC_INTLVL_OFF_gc = (0x00<<4), /* Interrupt disabled */ - AC_INTLVL_LO_gc = (0x01<<4), /* Low level */ - AC_INTLVL_MED_gc = (0x02<<4), /* Medium level */ - AC_INTLVL_HI_gc = (0x03<<4), /* High level */ -} AC_INTLVL_t; - -/* Hysteresis mode selection */ -typedef enum AC_HYSMODE_enum -{ - AC_HYSMODE_NO_gc = (0x00<<1), /* No hysteresis */ - AC_HYSMODE_SMALL_gc = (0x01<<1), /* Small hysteresis */ - AC_HYSMODE_LARGE_gc = (0x02<<1), /* Large hysteresis */ -} AC_HYSMODE_t; - -/* Positive input multiplexer selection */ -typedef enum AC_MUXPOS_enum -{ - AC_MUXPOS_PIN0_gc = (0x00<<3), /* Pin 0 */ - AC_MUXPOS_PIN1_gc = (0x01<<3), /* Pin 1 */ - AC_MUXPOS_PIN2_gc = (0x02<<3), /* Pin 2 */ - AC_MUXPOS_PIN3_gc = (0x03<<3), /* Pin 3 */ - AC_MUXPOS_PIN4_gc = (0x04<<3), /* Pin 4 */ - AC_MUXPOS_PIN5_gc = (0x05<<3), /* Pin 5 */ - AC_MUXPOS_PIN6_gc = (0x06<<3), /* Pin 6 */ - AC_MUXPOS_DAC_gc = (0x07<<3), /* DAC output */ -} AC_MUXPOS_t; - -/* Negative input multiplexer selection */ -typedef enum AC_MUXNEG_enum -{ - AC_MUXNEG_PIN0_gc = (0x00<<0), /* Pin 0 */ - AC_MUXNEG_PIN1_gc = (0x01<<0), /* Pin 1 */ - AC_MUXNEG_PIN3_gc = (0x02<<0), /* Pin 3 */ - AC_MUXNEG_PIN5_gc = (0x03<<0), /* Pin 5 */ - AC_MUXNEG_PIN7_gc = (0x04<<0), /* Pin 7 */ - AC_MUXNEG_DAC_gc = (0x05<<0), /* DAC output */ - AC_MUXNEG_BANDGAP_gc = (0x06<<0), /* Bandgap Reference */ - AC_MUXNEG_SCALER_gc = (0x07<<0), /* Internal voltage scaler */ -} AC_MUXNEG_t; - -/* Windows interrupt mode */ -typedef enum AC_WINTMODE_enum -{ - AC_WINTMODE_ABOVE_gc = (0x00<<2), /* Interrupt on above window */ - AC_WINTMODE_INSIDE_gc = (0x01<<2), /* Interrupt on inside window */ - AC_WINTMODE_BELOW_gc = (0x02<<2), /* Interrupt on below window */ - AC_WINTMODE_OUTSIDE_gc = (0x03<<2), /* Interrupt on outside window */ -} AC_WINTMODE_t; - -/* Window interrupt level */ -typedef enum AC_WINTLVL_enum -{ - AC_WINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ - AC_WINTLVL_LO_gc = (0x01<<0), /* Low priority */ - AC_WINTLVL_MED_gc = (0x02<<0), /* Medium priority */ - AC_WINTLVL_HI_gc = (0x03<<0), /* High priority */ -} AC_WINTLVL_t; - -/* Window mode state */ -typedef enum AC_WSTATE_enum -{ - AC_WSTATE_ABOVE_gc = (0x00<<6), /* Signal above window */ - AC_WSTATE_INSIDE_gc = (0x01<<6), /* Signal inside window */ - AC_WSTATE_BELOW_gc = (0x02<<6), /* Signal below window */ -} AC_WSTATE_t; - - -/* --------------------------------------------------------------------------- -ADC - Analog/Digital Converter --------------------------------------------------------------------------- -*/ - -/* ADC Channel */ -typedef struct ADC_CH_struct -{ - register8_t CTRL; /* Control Register */ - register8_t MUXCTRL; /* MUX Control */ - register8_t INTCTRL; /* Channel Interrupt Control */ - register8_t INTFLAGS; /* Interrupt Flags */ - _WORDREGISTER(RES); /* Channel Result */ - register8_t reserved_0x6; - register8_t reserved_0x7; -} ADC_CH_t; - -/* --------------------------------------------------------------------------- -ADC - Analog/Digital Converter --------------------------------------------------------------------------- -*/ - -/* Analog-to-Digital Converter */ -typedef struct ADC_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t REFCTRL; /* Reference Control */ - register8_t EVCTRL; /* Event Control */ - register8_t PRESCALER; /* Clock Prescaler */ - register8_t reserved_0x05; - register8_t INTFLAGS; /* Interrupt Flags */ - register8_t reserved_0x07; - register8_t reserved_0x08; - register8_t reserved_0x09; - register8_t reserved_0x0A; - register8_t reserved_0x0B; - _WORDREGISTER(CAL); /* Calibration Value */ - register8_t reserved_0x0E; - register8_t reserved_0x0F; - _WORDREGISTER(CH0RES); /* Channel 0 Result */ - _WORDREGISTER(CH1RES); /* Channel 1 Result */ - _WORDREGISTER(CH2RES); /* Channel 2 Result */ - _WORDREGISTER(CH3RES); /* Channel 3 Result */ - _WORDREGISTER(CMP); /* Compare Value */ - register8_t reserved_0x1A; - register8_t reserved_0x1B; - register8_t reserved_0x1C; - register8_t reserved_0x1D; - register8_t reserved_0x1E; - register8_t reserved_0x1F; - ADC_CH_t CH0; /* ADC Channel 0 */ - ADC_CH_t CH1; /* ADC Channel 1 */ - ADC_CH_t CH2; /* ADC Channel 2 */ - ADC_CH_t CH3; /* ADC Channel 3 */ -} ADC_t; - -/* Positive input multiplexer selection */ -typedef enum ADC_CH_MUXPOS_enum -{ - ADC_CH_MUXPOS_PIN0_gc = (0x00<<3), /* Input pin 0 */ - ADC_CH_MUXPOS_PIN1_gc = (0x01<<3), /* Input pin 1 */ - ADC_CH_MUXPOS_PIN2_gc = (0x02<<3), /* Input pin 2 */ - ADC_CH_MUXPOS_PIN3_gc = (0x03<<3), /* Input pin 3 */ - ADC_CH_MUXPOS_PIN4_gc = (0x04<<3), /* Input pin 4 */ - ADC_CH_MUXPOS_PIN5_gc = (0x05<<3), /* Input pin 5 */ - ADC_CH_MUXPOS_PIN6_gc = (0x06<<3), /* Input pin 6 */ - ADC_CH_MUXPOS_PIN7_gc = (0x07<<3), /* Input pin 7 */ -} ADC_CH_MUXPOS_t; - -/* Internal input multiplexer selections */ -typedef enum ADC_CH_MUXINT_enum -{ - ADC_CH_MUXINT_TEMP_gc = (0x00<<3), /* Temperature Reference */ - ADC_CH_MUXINT_BANDGAP_gc = (0x01<<3), /* Bandgap Reference */ - ADC_CH_MUXINT_SCALEDVCC_gc = (0x02<<3), /* 1/10 scaled VCC */ - ADC_CH_MUXINT_DAC_gc = (0x03<<3), /* DAC output */ -} ADC_CH_MUXINT_t; - -/* Negative input multiplexer selection */ -typedef enum ADC_CH_MUXNEG_enum -{ - ADC_CH_MUXNEG_PIN0_gc = (0x00<<0), /* Input pin 0 */ - ADC_CH_MUXNEG_PIN1_gc = (0x01<<0), /* Input pin 1 */ - ADC_CH_MUXNEG_PIN2_gc = (0x02<<0), /* Input pin 2 */ - ADC_CH_MUXNEG_PIN3_gc = (0x03<<0), /* Input pin 3 */ - ADC_CH_MUXNEG_PIN4_gc = (0x04<<0), /* Input pin 4 */ - ADC_CH_MUXNEG_PIN5_gc = (0x05<<0), /* Input pin 5 */ - ADC_CH_MUXNEG_PIN6_gc = (0x06<<0), /* Input pin 6 */ - ADC_CH_MUXNEG_PIN7_gc = (0x07<<0), /* Input pin 7 */ -} ADC_CH_MUXNEG_t; - -/* Input mode */ -typedef enum ADC_CH_INPUTMODE_enum -{ - ADC_CH_INPUTMODE_INTERNAL_gc = (0x00<<0), /* Internal inputs, no gain */ - ADC_CH_INPUTMODE_SINGLEENDED_gc = (0x01<<0), /* Single-ended input, no gain */ - ADC_CH_INPUTMODE_DIFF_gc = (0x02<<0), /* Differential input, no gain */ - ADC_CH_INPUTMODE_DIFFWGAIN_gc = (0x03<<0), /* Differential input, with gain */ -} ADC_CH_INPUTMODE_t; - -/* Gain factor */ -typedef enum ADC_CH_GAIN_enum -{ - ADC_CH_GAIN_1X_gc = (0x00<<2), /* 1x gain */ - ADC_CH_GAIN_2X_gc = (0x01<<2), /* 2x gain */ - ADC_CH_GAIN_4X_gc = (0x02<<2), /* 4x gain */ - ADC_CH_GAIN_8X_gc = (0x03<<2), /* 8x gain */ - ADC_CH_GAIN_16X_gc = (0x04<<2), /* 16x gain */ - ADC_CH_GAIN_32X_gc = (0x05<<2), /* 32x gain */ - ADC_CH_GAIN_64X_gc = (0x06<<2), /* 64x gain */ -} ADC_CH_GAIN_t; - -/* Conversion result resolution */ -typedef enum ADC_RESOLUTION_enum -{ - ADC_RESOLUTION_12BIT_gc = (0x00<<1), /* 12-bit right-adjusted result */ - ADC_RESOLUTION_8BIT_gc = (0x02<<1), /* 8-bit right-adjusted result */ - ADC_RESOLUTION_LEFT12BIT_gc = (0x03<<1), /* 12-bit left-adjusted result */ -} ADC_RESOLUTION_t; - -/* Voltage reference selection */ -typedef enum ADC_REFSEL_enum -{ - ADC_REFSEL_INT1V_gc = (0x00<<4), /* Internal 1V */ - ADC_REFSEL_VCC_gc = (0x01<<4), /* Internal VCC / 1.6V */ - ADC_REFSEL_AREFA_gc = (0x02<<4), /* External reference on PORT A */ - ADC_REFSEL_AREFB_gc = (0x03<<4), /* External reference on PORT B */ -} ADC_REFSEL_t; - -/* Channel sweep selection */ -typedef enum ADC_SWEEP_enum -{ - ADC_SWEEP_0_gc = (0x00<<6), /* ADC Channel 0 */ - ADC_SWEEP_01_gc = (0x01<<6), /* ADC Channel 0,1 */ - ADC_SWEEP_012_gc = (0x02<<6), /* ADC Channel 0,1,2 */ - ADC_SWEEP_0123_gc = (0x03<<6), /* ADC Channel 0,1,2,3 */ -} ADC_SWEEP_t; - -/* Event channel input selection */ -typedef enum ADC_EVSEL_enum -{ - ADC_EVSEL_0123_gc = (0x00<<3), /* Event Channel 0,1,2,3 */ - ADC_EVSEL_1234_gc = (0x01<<3), /* Event Channel 1,2,3,4 */ - ADC_EVSEL_2345_gc = (0x02<<3), /* Event Channel 2,3,4,5 */ - ADC_EVSEL_3456_gc = (0x03<<3), /* Event Channel 3,4,5,6 */ - ADC_EVSEL_4567_gc = (0x04<<3), /* Event Channel 4,5,6,7 */ - ADC_EVSEL_567_gc = (0x05<<3), /* Event Channel 5,6,7 */ - ADC_EVSEL_67_gc = (0x06<<3), /* Event Channel 6,7 */ - ADC_EVSEL_7_gc = (0x07<<3), /* Event Channel 7 */ -} ADC_EVSEL_t; - -/* Event action selection */ -typedef enum ADC_EVACT_enum -{ - ADC_EVACT_NONE_gc = (0x00<<0), /* No event action */ - ADC_EVACT_CH0_gc = (0x01<<0), /* First event triggers channel 0 */ - ADC_EVACT_CH01_gc = (0x02<<0), /* First two events trigger channel 0,1 */ - ADC_EVACT_CH012_gc = (0x03<<0), /* First three events trigger channel 0,1,2 */ - ADC_EVACT_CH0123_gc = (0x04<<0), /* Events trigger channel 0,1,2,3 */ - ADC_EVACT_SWEEP_gc = (0x05<<0), /* First event triggers sweep */ - ADC_EVACT_SYNCHSWEEP_gc = (0x06<<0), /* First event triggers synchronized sweep */ -} ADC_EVACT_t; - -/* Interupt mode */ -typedef enum ADC_CH_INTMODE_enum -{ - ADC_CH_INTMODE_COMPLETE_gc = (0x00<<2), /* Interrupt on conversion complete */ - ADC_CH_INTMODE_BELOW_gc = (0x01<<2), /* Interrupt on result below compare value */ - ADC_CH_INTMODE_ABOVE_gc = (0x03<<2), /* Interrupt on result above compare value */ -} ADC_CH_INTMODE_t; - -/* Interrupt level */ -typedef enum ADC_CH_INTLVL_enum -{ - ADC_CH_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ - ADC_CH_INTLVL_LO_gc = (0x01<<0), /* Low level */ - ADC_CH_INTLVL_MED_gc = (0x02<<0), /* Medium level */ - ADC_CH_INTLVL_HI_gc = (0x03<<0), /* High level */ -} ADC_CH_INTLVL_t; - -/* DMA request selection */ -typedef enum ADC_DMASEL_enum -{ - ADC_DMASEL_OFF_gc = (0x00<<6), /* Combined DMA request OFF */ - ADC_DMASEL_CH01_gc = (0x01<<6), /* ADC Channel 0 or 1 */ - ADC_DMASEL_CH012_gc = (0x02<<6), /* ADC Channel 0 or 1 or 2 */ - ADC_DMASEL_CH0123_gc = (0x03<<6), /* ADC Channel 0 or 1 or 2 or 3 */ -} ADC_DMASEL_t; - -/* Clock prescaler */ -typedef enum ADC_PRESCALER_enum -{ - ADC_PRESCALER_DIV4_gc = (0x00<<0), /* Divide clock by 4 */ - ADC_PRESCALER_DIV8_gc = (0x01<<0), /* Divide clock by 8 */ - ADC_PRESCALER_DIV16_gc = (0x02<<0), /* Divide clock by 16 */ - ADC_PRESCALER_DIV32_gc = (0x03<<0), /* Divide clock by 32 */ - ADC_PRESCALER_DIV64_gc = (0x04<<0), /* Divide clock by 64 */ - ADC_PRESCALER_DIV128_gc = (0x05<<0), /* Divide clock by 128 */ - ADC_PRESCALER_DIV256_gc = (0x06<<0), /* Divide clock by 256 */ - ADC_PRESCALER_DIV512_gc = (0x07<<0), /* Divide clock by 512 */ -} ADC_PRESCALER_t; - - -/* --------------------------------------------------------------------------- -DAC - Digital/Analog Converter --------------------------------------------------------------------------- -*/ - -/* Digital-to-Analog Converter */ -typedef struct DAC_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t CTRLC; /* Control Register C */ - register8_t EVCTRL; /* Event Input Control */ - register8_t TIMCTRL; /* Timing Control */ - register8_t STATUS; /* Status */ - register8_t reserved_0x06; - register8_t reserved_0x07; - register8_t GAINCAL; /* Gain Calibration */ - register8_t OFFSETCAL; /* Offset Calibration */ - register8_t reserved_0x0A; - register8_t reserved_0x0B; - register8_t reserved_0x0C; - register8_t reserved_0x0D; - register8_t reserved_0x0E; - register8_t reserved_0x0F; - register8_t reserved_0x10; - register8_t reserved_0x11; - register8_t reserved_0x12; - register8_t reserved_0x13; - register8_t reserved_0x14; - register8_t reserved_0x15; - register8_t reserved_0x16; - register8_t reserved_0x17; - _WORDREGISTER(CH0DATA); /* Channel 0 Data */ - _WORDREGISTER(CH1DATA); /* Channel 1 Data */ -} DAC_t; - -/* Output channel selection */ -typedef enum DAC_CHSEL_enum -{ - DAC_CHSEL_SINGLE_gc = (0x00<<5), /* Single channel operation (Channel A only) */ - DAC_CHSEL_DUAL_gc = (0x02<<5), /* Dual channel operation (S/H on both channels) */ -} DAC_CHSEL_t; - -/* Reference voltage selection */ -typedef enum DAC_REFSEL_enum -{ - DAC_REFSEL_INT1V_gc = (0x00<<3), /* Internal 1V */ - DAC_REFSEL_AVCC_gc = (0x01<<3), /* Analog supply voltage */ - DAC_REFSEL_AREFA_gc = (0x02<<3), /* External reference on AREF on PORTA */ - DAC_REFSEL_AREFB_gc = (0x03<<3), /* External reference on AREF on PORTB */ -} DAC_REFSEL_t; - -/* Event channel selection */ -typedef enum DAC_EVSEL_enum -{ - DAC_EVSEL_0_gc = (0x00<<0), /* Event Channel 0 */ - DAC_EVSEL_1_gc = (0x01<<0), /* Event Channel 1 */ - DAC_EVSEL_2_gc = (0x02<<0), /* Event Channel 2 */ - DAC_EVSEL_3_gc = (0x03<<0), /* Event Channel 3 */ - DAC_EVSEL_4_gc = (0x04<<0), /* Event Channel 4 */ - DAC_EVSEL_5_gc = (0x05<<0), /* Event Channel 5 */ - DAC_EVSEL_6_gc = (0x06<<0), /* Event Channel 6 */ - DAC_EVSEL_7_gc = (0x07<<0), /* Event Channel 7 */ -} DAC_EVSEL_t; - -/* Conversion interval */ -typedef enum DAC_CONINTVAL_enum -{ - DAC_CONINTVAL_1CLK_gc = (0x00<<4), /* 1 CLK / 2 CLK in S/H mode */ - DAC_CONINTVAL_2CLK_gc = (0x01<<4), /* 2 CLK / 3 CLK in S/H mode */ - DAC_CONINTVAL_4CLK_gc = (0x02<<4), /* 4 CLK / 6 CLK in S/H mode */ - DAC_CONINTVAL_8CLK_gc = (0x03<<4), /* 8 CLK / 12 CLK in S/H mode */ - DAC_CONINTVAL_16CLK_gc = (0x04<<4), /* 16 CLK / 24 CLK in S/H mode */ - DAC_CONINTVAL_32CLK_gc = (0x05<<4), /* 32 CLK / 48 CLK in S/H mode */ - DAC_CONINTVAL_64CLK_gc = (0x06<<4), /* 64 CLK / 96 CLK in S/H mode */ - DAC_CONINTVAL_128CLK_gc = (0x07<<4), /* 128 CLK / 192 CLK in S/H mode */ -} DAC_CONINTVAL_t; - -/* Refresh rate */ -typedef enum DAC_REFRESH_enum -{ - DAC_REFRESH_16CLK_gc = (0x00<<0), /* 16 CLK */ - DAC_REFRESH_32CLK_gc = (0x01<<0), /* 32 CLK */ - DAC_REFRESH_64CLK_gc = (0x02<<0), /* 64 CLK */ - DAC_REFRESH_128CLK_gc = (0x03<<0), /* 128 CLK */ - DAC_REFRESH_256CLK_gc = (0x04<<0), /* 256 CLK */ - DAC_REFRESH_512CLK_gc = (0x05<<0), /* 512 CLK */ - DAC_REFRESH_1024CLK_gc = (0x06<<0), /* 1024 CLK */ - DAC_REFRESH_2048CLK_gc = (0x07<<0), /* 2048 CLK */ - DAC_REFRESH_4096CLK_gc = (0x08<<0), /* 4096 CLK */ - DAC_REFRESH_8192CLK_gc = (0x09<<0), /* 8192 CLK */ - DAC_REFRESH_16384CLK_gc = (0x0A<<0), /* 16384 CLK */ - DAC_REFRESH_32768CLK_gc = (0x0B<<0), /* 32768 CLK */ - DAC_REFRESH_65536CLK_gc = (0x0C<<0), /* 65536 CLK */ - DAC_REFRESH_OFF_gc = (0x0F<<0), /* Auto refresh OFF */ -} DAC_REFRESH_t; - - -/* --------------------------------------------------------------------------- -RTC - Real-Time Clounter --------------------------------------------------------------------------- -*/ - -/* Real-Time Counter */ -typedef struct RTC_struct -{ - register8_t CTRL; /* Control Register */ - register8_t STATUS; /* Status Register */ - register8_t INTCTRL; /* Interrupt Control Register */ - register8_t INTFLAGS; /* Interrupt Flags */ - register8_t TEMP; /* Temporary register */ - register8_t reserved_0x05; - register8_t reserved_0x06; - register8_t reserved_0x07; - _WORDREGISTER(CNT); /* Count Register */ - _WORDREGISTER(PER); /* Period Register */ - _WORDREGISTER(COMP); /* Compare Register */ -} RTC_t; - -/* Prescaler Factor */ -typedef enum RTC_PRESCALER_enum -{ - RTC_PRESCALER_OFF_gc = (0x00<<0), /* RTC Off */ - RTC_PRESCALER_DIV1_gc = (0x01<<0), /* RTC Clock */ - RTC_PRESCALER_DIV2_gc = (0x02<<0), /* RTC Clock / 2 */ - RTC_PRESCALER_DIV8_gc = (0x03<<0), /* RTC Clock / 8 */ - RTC_PRESCALER_DIV16_gc = (0x04<<0), /* RTC Clock / 16 */ - RTC_PRESCALER_DIV64_gc = (0x05<<0), /* RTC Clock / 64 */ - RTC_PRESCALER_DIV256_gc = (0x06<<0), /* RTC Clock / 256 */ - RTC_PRESCALER_DIV1024_gc = (0x07<<0), /* RTC Clock / 1024 */ -} RTC_PRESCALER_t; - -/* Compare Interrupt level */ -typedef enum RTC_COMPINTLVL_enum -{ - RTC_COMPINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ - RTC_COMPINTLVL_LO_gc = (0x01<<2), /* Low Level */ - RTC_COMPINTLVL_MED_gc = (0x02<<2), /* Medium Level */ - RTC_COMPINTLVL_HI_gc = (0x03<<2), /* High Level */ -} RTC_COMPINTLVL_t; - -/* Overflow Interrupt level */ -typedef enum RTC_OVFINTLVL_enum -{ - RTC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - RTC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ - RTC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ - RTC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ -} RTC_OVFINTLVL_t; - - -/* --------------------------------------------------------------------------- -EBI - External Bus Interface --------------------------------------------------------------------------- -*/ - -/* EBI Chip Select Module */ -typedef struct EBI_CS_struct -{ - register8_t CTRLA; /* Chip Select Control Register A */ - register8_t CTRLB; /* Chip Select Control Register B */ - _WORDREGISTER(BASEADDR); /* Chip Select Base Address */ -} EBI_CS_t; - -/* --------------------------------------------------------------------------- -EBI - External Bus Interface --------------------------------------------------------------------------- -*/ - -/* External Bus Interface */ -typedef struct EBI_struct -{ - register8_t CTRL; /* Control */ - register8_t SDRAMCTRLA; /* SDRAM Control Register A */ - register8_t reserved_0x02; - register8_t reserved_0x03; - _WORDREGISTER(REFRESH); /* SDRAM Refresh Period */ - _WORDREGISTER(INITDLY); /* SDRAM Initialization Delay */ - register8_t SDRAMCTRLB; /* SDRAM Control Register B */ - register8_t SDRAMCTRLC; /* SDRAM Control Register C */ - register8_t reserved_0x0A; - register8_t reserved_0x0B; - register8_t reserved_0x0C; - register8_t reserved_0x0D; - register8_t reserved_0x0E; - register8_t reserved_0x0F; - EBI_CS_t CS0; /* Chip Select 0 */ - EBI_CS_t CS1; /* Chip Select 1 */ - EBI_CS_t CS2; /* Chip Select 2 */ - EBI_CS_t CS3; /* Chip Select 3 */ -} EBI_t; - -/* Chip Select adress space */ -typedef enum EBI_CS_ASIZE_enum -{ - EBI_CS_ASIZE_256B_gc = (0x00<<2), /* 256 bytes */ - EBI_CS_ASIZE_512B_gc = (0x01<<2), /* 512 bytes */ - EBI_CS_ASIZE_1KB_gc = (0x02<<2), /* 1K bytes */ - EBI_CS_ASIZE_2KB_gc = (0x03<<2), /* 2K bytes */ - EBI_CS_ASIZE_4KB_gc = (0x04<<2), /* 4K bytes */ - EBI_CS_ASIZE_8KB_gc = (0x05<<2), /* 8K bytes */ - EBI_CS_ASIZE_16KB_gc = (0x06<<2), /* 16K bytes */ - EBI_CS_ASIZE_32KB_gc = (0x07<<2), /* 32K bytes */ - EBI_CS_ASIZE_64KB_gc = (0x08<<2), /* 64K bytes */ - EBI_CS_ASIZE_128KB_gc = (0x09<<2), /* 128K bytes */ - EBI_CS_ASIZE_256KB_gc = (0x0A<<2), /* 256K bytes */ - EBI_CS_ASIZE_512KB_gc = (0x0B<<2), /* 512K bytes */ - EBI_CS_ASIZE_1MB_gc = (0x0C<<2), /* 1M bytes */ - EBI_CS_ASIZE_2MB_gc = (0x0D<<2), /* 2M bytes */ - EBI_CS_ASIZE_4MB_gc = (0x0E<<2), /* 4M bytes */ - EBI_CS_ASIZE_8MB_gc = (0x0F<<2), /* 8M bytes */ - EBI_CS_ASIZE_16M_gc = (0x10<<2), /* 16M bytes */ -} EBI_CS_ASIZE_t; - -/* */ -typedef enum EBI_CS_SRWS_enum -{ - EBI_CS_SRWS_0CLK_gc = (0x00<<0), /* 0 cycles */ - EBI_CS_SRWS_1CLK_gc = (0x01<<0), /* 1 cycle */ - EBI_CS_SRWS_2CLK_gc = (0x02<<0), /* 2 cycles */ - EBI_CS_SRWS_3CLK_gc = (0x03<<0), /* 3 cycles */ - EBI_CS_SRWS_4CLK_gc = (0x04<<0), /* 4 cycles */ - EBI_CS_SRWS_5CLK_gc = (0x05<<0), /* 5 cycle */ - EBI_CS_SRWS_6CLK_gc = (0x06<<0), /* 6 cycles */ - EBI_CS_SRWS_7CLK_gc = (0x07<<0), /* 7 cycles */ -} EBI_CS_SRWS_t; - -/* Chip Select address mode */ -typedef enum EBI_CS_MODE_enum -{ - EBI_CS_MODE_DISABLED_gc = (0x00<<0), /* Chip Select Disabled */ - EBI_CS_MODE_SRAM_gc = (0x01<<0), /* Chip Select in SRAM mode */ - EBI_CS_MODE_LPC_gc = (0x02<<0), /* Chip Select in SRAM LPC mode */ - EBI_CS_MODE_SDRAM_gc = (0x03<<0), /* Chip Select in SDRAM mode */ -} EBI_CS_MODE_t; - -/* Chip Select SDRAM mode */ -typedef enum EBI_CS_SDMODE_enum -{ - EBI_CS_SDMODE_NORMAL_gc = (0x00<<0), /* Normal mode */ - EBI_CS_SDMODE_LOAD_gc = (0x01<<0), /* Load Mode Register command mode */ -} EBI_CS_SDMODE_t; - -/* */ -typedef enum EBI_SDDATAW_enum -{ - EBI_SDDATAW_4BIT_gc = (0x00<<6), /* 4-bit data bus */ - EBI_SDDATAW_8BIT_gc = (0x01<<6), /* 8-bit data bus */ -} EBI_SDDATAW_t; - -/* */ -typedef enum EBI_LPCMODE_enum -{ - EBI_LPCMODE_ALE1_gc = (0x00<<4), /* Data muxed with addr byte 0 */ - EBI_LPCMODE_ALE12_gc = (0x02<<4), /* Data muxed with addr byte 0 and 1 */ -} EBI_LPCMODE_t; - -/* */ -typedef enum EBI_SRMODE_enum -{ - EBI_SRMODE_ALE1_gc = (0x00<<2), /* Addr byte 0 muxed with 1 */ - EBI_SRMODE_ALE2_gc = (0x01<<2), /* Addr byte 0 muxed with 2 */ - EBI_SRMODE_ALE12_gc = (0x02<<2), /* Addr byte 0 muxed with 1 and 2 */ - EBI_SRMODE_NOALE_gc = (0x03<<2), /* No addr muxing */ -} EBI_SRMODE_t; - -/* */ -typedef enum EBI_IFMODE_enum -{ - EBI_IFMODE_DISABLED_gc = (0x00<<0), /* EBI Disabled */ - EBI_IFMODE_3PORT_gc = (0x01<<0), /* 3-port mode */ - EBI_IFMODE_4PORT_gc = (0x02<<0), /* 4-port mode */ - EBI_IFMODE_2PORT_gc = (0x03<<0), /* 2-port mode */ -} EBI_IFMODE_t; - -/* */ -typedef enum EBI_SDCOL_enum -{ - EBI_SDCOL_8BIT_gc = (0x00<<0), /* 8 column bits */ - EBI_SDCOL_9BIT_gc = (0x01<<0), /* 9 column bits */ - EBI_SDCOL_10BIT_gc = (0x02<<0), /* 10 column bits */ - EBI_SDCOL_11BIT_gc = (0x03<<0), /* 11 column bits */ -} EBI_SDCOL_t; - -/* */ -typedef enum EBI_MRDLY_enum -{ - EBI_MRDLY_0CLK_gc = (0x00<<6), /* 0 cycles */ - EBI_MRDLY_1CLK_gc = (0x01<<6), /* 1 cycle */ - EBI_MRDLY_2CLK_gc = (0x02<<6), /* 2 cycles */ - EBI_MRDLY_3CLK_gc = (0x03<<6), /* 3 cycles */ -} EBI_MRDLY_t; - -/* */ -typedef enum EBI_ROWCYCDLY_enum -{ - EBI_ROWCYCDLY_0CLK_gc = (0x00<<3), /* 0 cycles */ - EBI_ROWCYCDLY_1CLK_gc = (0x01<<3), /* 1 cycle */ - EBI_ROWCYCDLY_2CLK_gc = (0x02<<3), /* 2 cycles */ - EBI_ROWCYCDLY_3CLK_gc = (0x03<<3), /* 3 cycles */ - EBI_ROWCYCDLY_4CLK_gc = (0x04<<3), /* 4 cycles */ - EBI_ROWCYCDLY_5CLK_gc = (0x05<<3), /* 5 cycle */ - EBI_ROWCYCDLY_6CLK_gc = (0x06<<3), /* 6 cycles */ - EBI_ROWCYCDLY_7CLK_gc = (0x07<<3), /* 7 cycles */ -} EBI_ROWCYCDLY_t; - -/* */ -typedef enum EBI_RPDLY_enum -{ - EBI_RPDLY_0CLK_gc = (0x00<<0), /* 0 cycles */ - EBI_RPDLY_1CLK_gc = (0x01<<0), /* 1 cycle */ - EBI_RPDLY_2CLK_gc = (0x02<<0), /* 2 cycles */ - EBI_RPDLY_3CLK_gc = (0x03<<0), /* 3 cycles */ - EBI_RPDLY_4CLK_gc = (0x04<<0), /* 4 cycles */ - EBI_RPDLY_5CLK_gc = (0x05<<0), /* 5 cycle */ - EBI_RPDLY_6CLK_gc = (0x06<<0), /* 6 cycles */ - EBI_RPDLY_7CLK_gc = (0x07<<0), /* 7 cycles */ -} EBI_RPDLY_t; - -/* */ -typedef enum EBI_WRDLY_enum -{ - EBI_WRDLY_0CLK_gc = (0x00<<6), /* 0 cycles */ - EBI_WRDLY_1CLK_gc = (0x01<<6), /* 1 cycle */ - EBI_WRDLY_2CLK_gc = (0x02<<6), /* 2 cycles */ - EBI_WRDLY_3CLK_gc = (0x03<<6), /* 3 cycles */ -} EBI_WRDLY_t; - -/* */ -typedef enum EBI_ESRDLY_enum -{ - EBI_ESRDLY_0CLK_gc = (0x00<<3), /* 0 cycles */ - EBI_ESRDLY_1CLK_gc = (0x01<<3), /* 1 cycle */ - EBI_ESRDLY_2CLK_gc = (0x02<<3), /* 2 cycles */ - EBI_ESRDLY_3CLK_gc = (0x03<<3), /* 3 cycles */ - EBI_ESRDLY_4CLK_gc = (0x04<<3), /* 4 cycles */ - EBI_ESRDLY_5CLK_gc = (0x05<<3), /* 5 cycle */ - EBI_ESRDLY_6CLK_gc = (0x06<<3), /* 6 cycles */ - EBI_ESRDLY_7CLK_gc = (0x07<<3), /* 7 cycles */ -} EBI_ESRDLY_t; - -/* */ -typedef enum EBI_ROWCOLDLY_enum -{ - EBI_ROWCOLDLY_0CLK_gc = (0x00<<0), /* 0 cycles */ - EBI_ROWCOLDLY_1CLK_gc = (0x01<<0), /* 1 cycle */ - EBI_ROWCOLDLY_2CLK_gc = (0x02<<0), /* 2 cycles */ - EBI_ROWCOLDLY_3CLK_gc = (0x03<<0), /* 3 cycles */ - EBI_ROWCOLDLY_4CLK_gc = (0x04<<0), /* 4 cycles */ - EBI_ROWCOLDLY_5CLK_gc = (0x05<<0), /* 5 cycle */ - EBI_ROWCOLDLY_6CLK_gc = (0x06<<0), /* 6 cycles */ - EBI_ROWCOLDLY_7CLK_gc = (0x07<<0), /* 7 cycles */ -} EBI_ROWCOLDLY_t; - - -/* --------------------------------------------------------------------------- -TWI - Two-Wire Interface --------------------------------------------------------------------------- -*/ - -/* */ -typedef struct TWI_MASTER_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t CTRLC; /* Control Register C */ - register8_t STATUS; /* Status Register */ - register8_t BAUD; /* Baurd Rate Control Register */ - register8_t ADDR; /* Address Register */ - register8_t DATA; /* Data Register */ -} TWI_MASTER_t; - -/* --------------------------------------------------------------------------- -TWI - Two-Wire Interface --------------------------------------------------------------------------- -*/ - -/* */ -typedef struct TWI_SLAVE_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t STATUS; /* Status Register */ - register8_t ADDR; /* Address Register */ - register8_t DATA; /* Data Register */ - register8_t ADDRMASK; /* Address Mask Register */ -} TWI_SLAVE_t; - -/* --------------------------------------------------------------------------- -TWI - Two-Wire Interface --------------------------------------------------------------------------- -*/ - -/* Two-Wire Interface */ -typedef struct TWI_struct -{ - register8_t CTRL; /* TWI Common Control Register */ - TWI_MASTER_t MASTER; /* TWI master module */ - TWI_SLAVE_t SLAVE; /* TWI slave module */ -} TWI_t; - -/* Master Interrupt Level */ -typedef enum TWI_MASTER_INTLVL_enum -{ - TWI_MASTER_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ - TWI_MASTER_INTLVL_LO_gc = (0x01<<6), /* Low Level */ - TWI_MASTER_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ - TWI_MASTER_INTLVL_HI_gc = (0x03<<6), /* High Level */ -} TWI_MASTER_INTLVL_t; - -/* Inactive Timeout */ -typedef enum TWI_MASTER_TIMEOUT_enum -{ - TWI_MASTER_TIMEOUT_DISABLED_gc = (0x00<<2), /* Bus Timeout Disabled */ - TWI_MASTER_TIMEOUT_50US_gc = (0x01<<2), /* 50 Microseconds */ - TWI_MASTER_TIMEOUT_100US_gc = (0x02<<2), /* 100 Microseconds */ - TWI_MASTER_TIMEOUT_200US_gc = (0x03<<2), /* 200 Microseconds */ -} TWI_MASTER_TIMEOUT_t; - -/* Master Command */ -typedef enum TWI_MASTER_CMD_enum -{ - TWI_MASTER_CMD_NOACT_gc = (0x00<<0), /* No Action */ - TWI_MASTER_CMD_REPSTART_gc = (0x01<<0), /* Issue Repeated Start Condition */ - TWI_MASTER_CMD_RECVTRANS_gc = (0x02<<0), /* Receive or Transmit Data */ - TWI_MASTER_CMD_STOP_gc = (0x03<<0), /* Issue Stop Condition */ -} TWI_MASTER_CMD_t; - -/* Master Bus State */ -typedef enum TWI_MASTER_BUSSTATE_enum -{ - TWI_MASTER_BUSSTATE_UNKNOWN_gc = (0x00<<0), /* Unknown Bus State */ - TWI_MASTER_BUSSTATE_IDLE_gc = (0x01<<0), /* Bus is Idle */ - TWI_MASTER_BUSSTATE_OWNER_gc = (0x02<<0), /* This Module Controls The Bus */ - TWI_MASTER_BUSSTATE_BUSY_gc = (0x03<<0), /* The Bus is Busy */ -} TWI_MASTER_BUSSTATE_t; - -/* Slave Interrupt Level */ -typedef enum TWI_SLAVE_INTLVL_enum -{ - TWI_SLAVE_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ - TWI_SLAVE_INTLVL_LO_gc = (0x01<<6), /* Low Level */ - TWI_SLAVE_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ - TWI_SLAVE_INTLVL_HI_gc = (0x03<<6), /* High Level */ -} TWI_SLAVE_INTLVL_t; - -/* Slave Command */ -typedef enum TWI_SLAVE_CMD_enum -{ - TWI_SLAVE_CMD_NOACT_gc = (0x00<<0), /* No Action */ - TWI_SLAVE_CMD_COMPTRANS_gc = (0x02<<0), /* Used To Complete a Transaction */ - TWI_SLAVE_CMD_RESPONSE_gc = (0x03<<0), /* Used in Response to Address/Data Interrupt */ -} TWI_SLAVE_CMD_t; - - -/* --------------------------------------------------------------------------- -PORT - Port Configuration --------------------------------------------------------------------------- -*/ - -/* I/O port Configuration */ -typedef struct PORTCFG_struct -{ - register8_t MPCMASK; /* Multi-pin Configuration Mask */ - register8_t reserved_0x01; - register8_t VPCTRLA; /* Virtual Port Control Register A */ - register8_t VPCTRLB; /* Virtual Port Control Register B */ - register8_t CLKEVOUT; /* Clock and Event Out Register */ -} PORTCFG_t; - -/* --------------------------------------------------------------------------- -PORT - Port Configuration --------------------------------------------------------------------------- -*/ - -/* Virtual Port */ -typedef struct VPORT_struct -{ - register8_t DIR; /* I/O Port Data Direction */ - register8_t OUT; /* I/O Port Output */ - register8_t IN; /* I/O Port Input */ - register8_t INTFLAGS; /* Interrupt Flag Register */ -} VPORT_t; - -/* --------------------------------------------------------------------------- -PORT - Port Configuration --------------------------------------------------------------------------- -*/ - -/* I/O Ports */ -typedef struct PORT_struct -{ - register8_t DIR; /* I/O Port Data Direction */ - register8_t DIRSET; /* I/O Port Data Direction Set */ - register8_t DIRCLR; /* I/O Port Data Direction Clear */ - register8_t DIRTGL; /* I/O Port Data Direction Toggle */ - register8_t OUT; /* I/O Port Output */ - register8_t OUTSET; /* I/O Port Output Set */ - register8_t OUTCLR; /* I/O Port Output Clear */ - register8_t OUTTGL; /* I/O Port Output Toggle */ - register8_t IN; /* I/O port Input */ - register8_t INTCTRL; /* Interrupt Control Register */ - register8_t INT0MASK; /* Port Interrupt 0 Mask */ - register8_t INT1MASK; /* Port Interrupt 1 Mask */ - register8_t INTFLAGS; /* Interrupt Flag Register */ - register8_t reserved_0x0D; - register8_t reserved_0x0E; - register8_t reserved_0x0F; - register8_t PIN0CTRL; /* Pin 0 Control Register */ - register8_t PIN1CTRL; /* Pin 1 Control Register */ - register8_t PIN2CTRL; /* Pin 2 Control Register */ - register8_t PIN3CTRL; /* Pin 3 Control Register */ - register8_t PIN4CTRL; /* Pin 4 Control Register */ - register8_t PIN5CTRL; /* Pin 5 Control Register */ - register8_t PIN6CTRL; /* Pin 6 Control Register */ - register8_t PIN7CTRL; /* Pin 7 Control Register */ -} PORT_t; - -/* Virtual Port 0 Mapping */ -typedef enum PORTCFG_VP0MAP_enum -{ - PORTCFG_VP0MAP_PORTA_gc = (0x00<<0), /* Mapped To PORTA */ - PORTCFG_VP0MAP_PORTB_gc = (0x01<<0), /* Mapped To PORTB */ - PORTCFG_VP0MAP_PORTC_gc = (0x02<<0), /* Mapped To PORTC */ - PORTCFG_VP0MAP_PORTD_gc = (0x03<<0), /* Mapped To PORTD */ - PORTCFG_VP0MAP_PORTE_gc = (0x04<<0), /* Mapped To PORTE */ - PORTCFG_VP0MAP_PORTF_gc = (0x05<<0), /* Mapped To PORTF */ - PORTCFG_VP0MAP_PORTG_gc = (0x06<<0), /* Mapped To PORTG */ - PORTCFG_VP0MAP_PORTH_gc = (0x07<<0), /* Mapped To PORTH */ - PORTCFG_VP0MAP_PORTJ_gc = (0x08<<0), /* Mapped To PORTJ */ - PORTCFG_VP0MAP_PORTK_gc = (0x09<<0), /* Mapped To PORTK */ - PORTCFG_VP0MAP_PORTL_gc = (0x0A<<0), /* Mapped To PORTL */ - PORTCFG_VP0MAP_PORTM_gc = (0x0B<<0), /* Mapped To PORTM */ - PORTCFG_VP0MAP_PORTN_gc = (0x0C<<0), /* Mapped To PORTN */ - PORTCFG_VP0MAP_PORTP_gc = (0x0D<<0), /* Mapped To PORTP */ - PORTCFG_VP0MAP_PORTQ_gc = (0x0E<<0), /* Mapped To PORTQ */ - PORTCFG_VP0MAP_PORTR_gc = (0x0F<<0), /* Mapped To PORTR */ -} PORTCFG_VP0MAP_t; - -/* Virtual Port 1 Mapping */ -typedef enum PORTCFG_VP1MAP_enum -{ - PORTCFG_VP1MAP_PORTA_gc = (0x00<<4), /* Mapped To PORTA */ - PORTCFG_VP1MAP_PORTB_gc = (0x01<<4), /* Mapped To PORTB */ - PORTCFG_VP1MAP_PORTC_gc = (0x02<<4), /* Mapped To PORTC */ - PORTCFG_VP1MAP_PORTD_gc = (0x03<<4), /* Mapped To PORTD */ - PORTCFG_VP1MAP_PORTE_gc = (0x04<<4), /* Mapped To PORTE */ - PORTCFG_VP1MAP_PORTF_gc = (0x05<<4), /* Mapped To PORTF */ - PORTCFG_VP1MAP_PORTG_gc = (0x06<<4), /* Mapped To PORTG */ - PORTCFG_VP1MAP_PORTH_gc = (0x07<<4), /* Mapped To PORTH */ - PORTCFG_VP1MAP_PORTJ_gc = (0x08<<4), /* Mapped To PORTJ */ - PORTCFG_VP1MAP_PORTK_gc = (0x09<<4), /* Mapped To PORTK */ - PORTCFG_VP1MAP_PORTL_gc = (0x0A<<4), /* Mapped To PORTL */ - PORTCFG_VP1MAP_PORTM_gc = (0x0B<<4), /* Mapped To PORTM */ - PORTCFG_VP1MAP_PORTN_gc = (0x0C<<4), /* Mapped To PORTN */ - PORTCFG_VP1MAP_PORTP_gc = (0x0D<<4), /* Mapped To PORTP */ - PORTCFG_VP1MAP_PORTQ_gc = (0x0E<<4), /* Mapped To PORTQ */ - PORTCFG_VP1MAP_PORTR_gc = (0x0F<<4), /* Mapped To PORTR */ -} PORTCFG_VP1MAP_t; - -/* Virtual Port 2 Mapping */ -typedef enum PORTCFG_VP2MAP_enum -{ - PORTCFG_VP2MAP_PORTA_gc = (0x00<<0), /* Mapped To PORTA */ - PORTCFG_VP2MAP_PORTB_gc = (0x01<<0), /* Mapped To PORTB */ - PORTCFG_VP2MAP_PORTC_gc = (0x02<<0), /* Mapped To PORTC */ - PORTCFG_VP2MAP_PORTD_gc = (0x03<<0), /* Mapped To PORTD */ - PORTCFG_VP2MAP_PORTE_gc = (0x04<<0), /* Mapped To PORTE */ - PORTCFG_VP2MAP_PORTF_gc = (0x05<<0), /* Mapped To PORTF */ - PORTCFG_VP2MAP_PORTG_gc = (0x06<<0), /* Mapped To PORTG */ - PORTCFG_VP2MAP_PORTH_gc = (0x07<<0), /* Mapped To PORTH */ - PORTCFG_VP2MAP_PORTJ_gc = (0x08<<0), /* Mapped To PORTJ */ - PORTCFG_VP2MAP_PORTK_gc = (0x09<<0), /* Mapped To PORTK */ - PORTCFG_VP2MAP_PORTL_gc = (0x0A<<0), /* Mapped To PORTL */ - PORTCFG_VP2MAP_PORTM_gc = (0x0B<<0), /* Mapped To PORTM */ - PORTCFG_VP2MAP_PORTN_gc = (0x0C<<0), /* Mapped To PORTN */ - PORTCFG_VP2MAP_PORTP_gc = (0x0D<<0), /* Mapped To PORTP */ - PORTCFG_VP2MAP_PORTQ_gc = (0x0E<<0), /* Mapped To PORTQ */ - PORTCFG_VP2MAP_PORTR_gc = (0x0F<<0), /* Mapped To PORTR */ -} PORTCFG_VP2MAP_t; - -/* Virtual Port 3 Mapping */ -typedef enum PORTCFG_VP3MAP_enum -{ - PORTCFG_VP3MAP_PORTA_gc = (0x00<<4), /* Mapped To PORTA */ - PORTCFG_VP3MAP_PORTB_gc = (0x01<<4), /* Mapped To PORTB */ - PORTCFG_VP3MAP_PORTC_gc = (0x02<<4), /* Mapped To PORTC */ - PORTCFG_VP3MAP_PORTD_gc = (0x03<<4), /* Mapped To PORTD */ - PORTCFG_VP3MAP_PORTE_gc = (0x04<<4), /* Mapped To PORTE */ - PORTCFG_VP3MAP_PORTF_gc = (0x05<<4), /* Mapped To PORTF */ - PORTCFG_VP3MAP_PORTG_gc = (0x06<<4), /* Mapped To PORTG */ - PORTCFG_VP3MAP_PORTH_gc = (0x07<<4), /* Mapped To PORTH */ - PORTCFG_VP3MAP_PORTJ_gc = (0x08<<4), /* Mapped To PORTJ */ - PORTCFG_VP3MAP_PORTK_gc = (0x09<<4), /* Mapped To PORTK */ - PORTCFG_VP3MAP_PORTL_gc = (0x0A<<4), /* Mapped To PORTL */ - PORTCFG_VP3MAP_PORTM_gc = (0x0B<<4), /* Mapped To PORTM */ - PORTCFG_VP3MAP_PORTN_gc = (0x0C<<4), /* Mapped To PORTN */ - PORTCFG_VP3MAP_PORTP_gc = (0x0D<<4), /* Mapped To PORTP */ - PORTCFG_VP3MAP_PORTQ_gc = (0x0E<<4), /* Mapped To PORTQ */ - PORTCFG_VP3MAP_PORTR_gc = (0x0F<<4), /* Mapped To PORTR */ -} PORTCFG_VP3MAP_t; - -/* Clock Output Port */ -typedef enum PORTCFG_CLKOUT_enum -{ - PORTCFG_CLKOUT_OFF_gc = (0x00<<0), /* Clock Output Disabled */ - PORTCFG_CLKOUT_PC7_gc = (0x01<<0), /* Clock Output on Port C pin 7 */ - PORTCFG_CLKOUT_PD7_gc = (0x02<<0), /* Clock Output on Port D pin 7 */ - PORTCFG_CLKOUT_PE7_gc = (0x03<<0), /* Clock Output on Port E pin 7 */ -} PORTCFG_CLKOUT_t; - -/* Event Output Port */ -typedef enum PORTCFG_EVOUT_enum -{ - PORTCFG_EVOUT_OFF_gc = (0x00<<4), /* Event Output Disabled */ - PORTCFG_EVOUT_PC7_gc = (0x01<<4), /* Event Channel 7 Output on Port C pin 7 */ - PORTCFG_EVOUT_PD7_gc = (0x02<<4), /* Event Channel 7 Output on Port D pin 7 */ - PORTCFG_EVOUT_PE7_gc = (0x03<<4), /* Event Channel 7 Output on Port E pin 7 */ -} PORTCFG_EVOUT_t; - -/* Port Interrupt 0 Level */ -typedef enum PORT_INT0LVL_enum -{ - PORT_INT0LVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - PORT_INT0LVL_LO_gc = (0x01<<0), /* Low Level */ - PORT_INT0LVL_MED_gc = (0x02<<0), /* Medium Level */ - PORT_INT0LVL_HI_gc = (0x03<<0), /* High Level */ -} PORT_INT0LVL_t; - -/* Port Interrupt 1 Level */ -typedef enum PORT_INT1LVL_enum -{ - PORT_INT1LVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ - PORT_INT1LVL_LO_gc = (0x01<<2), /* Low Level */ - PORT_INT1LVL_MED_gc = (0x02<<2), /* Medium Level */ - PORT_INT1LVL_HI_gc = (0x03<<2), /* High Level */ -} PORT_INT1LVL_t; - -/* Output/Pull Configuration */ -typedef enum PORT_OPC_enum -{ - PORT_OPC_TOTEM_gc = (0x00<<3), /* Totempole */ - PORT_OPC_BUSKEEPER_gc = (0x01<<3), /* Totempole w/ Bus keeper on Input and Output */ - PORT_OPC_PULLDOWN_gc = (0x02<<3), /* Totempole w/ Pull-down on Input */ - PORT_OPC_PULLUP_gc = (0x03<<3), /* Totempole w/ Pull-up on Input */ - PORT_OPC_WIREDOR_gc = (0x04<<3), /* Wired OR */ - PORT_OPC_WIREDAND_gc = (0x05<<3), /* Wired AND */ - PORT_OPC_WIREDORPULL_gc = (0x06<<3), /* Wired OR w/ Pull-down */ - PORT_OPC_WIREDANDPULL_gc = (0x07<<3), /* Wired AND w/ Pull-up */ -} PORT_OPC_t; - -/* Input/Sense Configuration */ -typedef enum PORT_ISC_enum -{ - PORT_ISC_BOTHEDGES_gc = (0x00<<0), /* Sense Both Edges */ - PORT_ISC_RISING_gc = (0x01<<0), /* Sense Rising Edge */ - PORT_ISC_FALLING_gc = (0x02<<0), /* Sense Falling Edge */ - PORT_ISC_LEVEL_gc = (0x03<<0), /* Sense Level (Transparent For Events) */ - PORT_ISC_INPUT_DISABLE_gc = (0x07<<0), /* Disable Digital Input Buffer */ -} PORT_ISC_t; - - -/* --------------------------------------------------------------------------- -TC - 16-bit Timer/Counter With PWM --------------------------------------------------------------------------- -*/ - -/* 16-bit Timer/Counter 0 */ -typedef struct TC0_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t CTRLC; /* Control register C */ - register8_t CTRLD; /* Control Register D */ - register8_t CTRLE; /* Control Register E */ - register8_t reserved_0x05; - register8_t INTCTRLA; /* Interrupt Control Register A */ - register8_t INTCTRLB; /* Interrupt Control Register B */ - register8_t CTRLFCLR; /* Control Register F Clear */ - register8_t CTRLFSET; /* Control Register F Set */ - register8_t CTRLGCLR; /* Control Register G Clear */ - register8_t CTRLGSET; /* Control Register G Set */ - register8_t INTFLAGS; /* Interrupt Flag Register */ - register8_t reserved_0x0D; - register8_t reserved_0x0E; - register8_t TEMP; /* Temporary Register For 16-bit Access */ - register8_t reserved_0x10; - register8_t reserved_0x11; - register8_t reserved_0x12; - register8_t reserved_0x13; - register8_t reserved_0x14; - register8_t reserved_0x15; - register8_t reserved_0x16; - register8_t reserved_0x17; - register8_t reserved_0x18; - register8_t reserved_0x19; - register8_t reserved_0x1A; - register8_t reserved_0x1B; - register8_t reserved_0x1C; - register8_t reserved_0x1D; - register8_t reserved_0x1E; - register8_t reserved_0x1F; - _WORDREGISTER(CNT); /* Count */ - register8_t reserved_0x22; - register8_t reserved_0x23; - register8_t reserved_0x24; - register8_t reserved_0x25; - _WORDREGISTER(PER); /* Period */ - _WORDREGISTER(CCA); /* Compare or Capture A */ - _WORDREGISTER(CCB); /* Compare or Capture B */ - _WORDREGISTER(CCC); /* Compare or Capture C */ - _WORDREGISTER(CCD); /* Compare or Capture D */ - register8_t reserved_0x30; - register8_t reserved_0x31; - register8_t reserved_0x32; - register8_t reserved_0x33; - register8_t reserved_0x34; - register8_t reserved_0x35; - _WORDREGISTER(PERBUF); /* Period Buffer */ - _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ - _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ - _WORDREGISTER(CCCBUF); /* Compare Or Capture C Buffer */ - _WORDREGISTER(CCDBUF); /* Compare Or Capture D Buffer */ -} TC0_t; - -/* --------------------------------------------------------------------------- -TC - 16-bit Timer/Counter With PWM --------------------------------------------------------------------------- -*/ - -/* 16-bit Timer/Counter 1 */ -typedef struct TC1_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t CTRLC; /* Control register C */ - register8_t CTRLD; /* Control Register D */ - register8_t CTRLE; /* Control Register E */ - register8_t reserved_0x05; - register8_t INTCTRLA; /* Interrupt Control Register A */ - register8_t INTCTRLB; /* Interrupt Control Register B */ - register8_t CTRLFCLR; /* Control Register F Clear */ - register8_t CTRLFSET; /* Control Register F Set */ - register8_t CTRLGCLR; /* Control Register G Clear */ - register8_t CTRLGSET; /* Control Register G Set */ - register8_t INTFLAGS; /* Interrupt Flag Register */ - register8_t reserved_0x0D; - register8_t reserved_0x0E; - register8_t TEMP; /* Temporary Register For 16-bit Access */ - register8_t reserved_0x10; - register8_t reserved_0x11; - register8_t reserved_0x12; - register8_t reserved_0x13; - register8_t reserved_0x14; - register8_t reserved_0x15; - register8_t reserved_0x16; - register8_t reserved_0x17; - register8_t reserved_0x18; - register8_t reserved_0x19; - register8_t reserved_0x1A; - register8_t reserved_0x1B; - register8_t reserved_0x1C; - register8_t reserved_0x1D; - register8_t reserved_0x1E; - register8_t reserved_0x1F; - _WORDREGISTER(CNT); /* Count */ - register8_t reserved_0x22; - register8_t reserved_0x23; - register8_t reserved_0x24; - register8_t reserved_0x25; - _WORDREGISTER(PER); /* Period */ - _WORDREGISTER(CCA); /* Compare or Capture A */ - _WORDREGISTER(CCB); /* Compare or Capture B */ - register8_t reserved_0x2C; - register8_t reserved_0x2D; - register8_t reserved_0x2E; - register8_t reserved_0x2F; - register8_t reserved_0x30; - register8_t reserved_0x31; - register8_t reserved_0x32; - register8_t reserved_0x33; - register8_t reserved_0x34; - register8_t reserved_0x35; - _WORDREGISTER(PERBUF); /* Period Buffer */ - _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ - _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ -} TC1_t; - -/* --------------------------------------------------------------------------- -TC - 16-bit Timer/Counter With PWM --------------------------------------------------------------------------- -*/ - -/* Advanced Waveform Extension */ -typedef struct AWEX_struct -{ - register8_t CTRL; /* Control Register */ - register8_t reserved_0x01; - register8_t FDEMASK; /* Fault Detection Event Mask */ - register8_t FDCTRL; /* Fault Detection Control Register */ - register8_t STATUS; /* Status Register */ - register8_t reserved_0x05; - register8_t DTBOTH; /* Dead Time Both Sides */ - register8_t DTBOTHBUF; /* Dead Time Both Sides Buffer */ - register8_t DTLS; /* Dead Time Low Side */ - register8_t DTHS; /* Dead Time High Side */ - register8_t DTLSBUF; /* Dead Time Low Side Buffer */ - register8_t DTHSBUF; /* Dead Time High Side Buffer */ - register8_t OUTOVEN; /* Output Override Enable */ -} AWEX_t; - -/* --------------------------------------------------------------------------- -TC - 16-bit Timer/Counter With PWM --------------------------------------------------------------------------- -*/ - -/* High-Resolution Extension */ -typedef struct HIRES_struct -{ - register8_t CTRLA; /* Control Register */ -} HIRES_t; - -/* Clock Selection */ -typedef enum TC_CLKSEL_enum -{ - TC_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */ - TC_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */ - TC_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */ - TC_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */ - TC_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */ - TC_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */ - TC_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */ - TC_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */ - TC_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */ - TC_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */ - TC_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */ - TC_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */ - TC_CLKSEL_EVCH4_gc = (0x0C<<0), /* Event Channel 4 */ - TC_CLKSEL_EVCH5_gc = (0x0D<<0), /* Event Channel 5 */ - TC_CLKSEL_EVCH6_gc = (0x0E<<0), /* Event Channel 6 */ - TC_CLKSEL_EVCH7_gc = (0x0F<<0), /* Event Channel 7 */ -} TC_CLKSEL_t; - -/* Waveform Generation Mode */ -typedef enum TC_WGMODE_enum -{ - TC_WGMODE_NORMAL_gc = (0x00<<0), /* Normal Mode */ - TC_WGMODE_FRQ_gc = (0x01<<0), /* Frequency Generation Mode */ - TC_WGMODE_SS_gc = (0x03<<0), /* Single Slope */ - TC_WGMODE_DS_T_gc = (0x05<<0), /* Dual Slope, Update on TOP */ - TC_WGMODE_DS_TB_gc = (0x06<<0), /* Dual Slope, Update on TOP and BOTTOM */ - TC_WGMODE_DS_B_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */ -} TC_WGMODE_t; - -/* Event Action */ -typedef enum TC_EVACT_enum -{ - TC_EVACT_OFF_gc = (0x00<<5), /* No Event Action */ - TC_EVACT_CAPT_gc = (0x01<<5), /* Input Capture */ - TC_EVACT_UPDOWN_gc = (0x02<<5), /* Externally Controlled Up/Down Count */ - TC_EVACT_QDEC_gc = (0x03<<5), /* Quadrature Decode */ - TC_EVACT_RESTART_gc = (0x04<<5), /* Restart */ - TC_EVACT_FRQ_gc = (0x05<<5), /* Frequency Capture */ - TC_EVACT_PW_gc = (0x06<<5), /* Pulse-width Capture */ -} TC_EVACT_t; - -/* Event Selection */ -typedef enum TC_EVSEL_enum -{ - TC_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ - TC_EVSEL_CH0_gc = (0x08<<0), /* Event Channel 0 */ - TC_EVSEL_CH1_gc = (0x09<<0), /* Event Channel 1 */ - TC_EVSEL_CH2_gc = (0x0A<<0), /* Event Channel 2 */ - TC_EVSEL_CH3_gc = (0x0B<<0), /* Event Channel 3 */ - TC_EVSEL_CH4_gc = (0x0C<<0), /* Event Channel 4 */ - TC_EVSEL_CH5_gc = (0x0D<<0), /* Event Channel 5 */ - TC_EVSEL_CH6_gc = (0x0E<<0), /* Event Channel 6 */ - TC_EVSEL_CH7_gc = (0x0F<<0), /* Event Channel 7 */ -} TC_EVSEL_t; - -/* Error Interrupt Level */ -typedef enum TC_ERRINTLVL_enum -{ - TC_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ - TC_ERRINTLVL_LO_gc = (0x01<<2), /* Low Level */ - TC_ERRINTLVL_MED_gc = (0x02<<2), /* Medium Level */ - TC_ERRINTLVL_HI_gc = (0x03<<2), /* High Level */ -} TC_ERRINTLVL_t; - -/* Overflow Interrupt Level */ -typedef enum TC_OVFINTLVL_enum -{ - TC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - TC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ - TC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ - TC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ -} TC_OVFINTLVL_t; - -/* Compare or Capture D Interrupt Level */ -typedef enum TC_CCDINTLVL_enum -{ - TC_CCDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ - TC_CCDINTLVL_LO_gc = (0x01<<6), /* Low Level */ - TC_CCDINTLVL_MED_gc = (0x02<<6), /* Medium Level */ - TC_CCDINTLVL_HI_gc = (0x03<<6), /* High Level */ -} TC_CCDINTLVL_t; - -/* Compare or Capture C Interrupt Level */ -typedef enum TC_CCCINTLVL_enum -{ - TC_CCCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ - TC_CCCINTLVL_LO_gc = (0x01<<4), /* Low Level */ - TC_CCCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ - TC_CCCINTLVL_HI_gc = (0x03<<4), /* High Level */ -} TC_CCCINTLVL_t; - -/* Compare or Capture B Interrupt Level */ -typedef enum TC_CCBINTLVL_enum -{ - TC_CCBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ - TC_CCBINTLVL_LO_gc = (0x01<<2), /* Low Level */ - TC_CCBINTLVL_MED_gc = (0x02<<2), /* Medium Level */ - TC_CCBINTLVL_HI_gc = (0x03<<2), /* High Level */ -} TC_CCBINTLVL_t; - -/* Compare or Capture A Interrupt Level */ -typedef enum TC_CCAINTLVL_enum -{ - TC_CCAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - TC_CCAINTLVL_LO_gc = (0x01<<0), /* Low Level */ - TC_CCAINTLVL_MED_gc = (0x02<<0), /* Medium Level */ - TC_CCAINTLVL_HI_gc = (0x03<<0), /* High Level */ -} TC_CCAINTLVL_t; - -/* Timer/Counter Command */ -typedef enum TC_CMD_enum -{ - TC_CMD_NONE_gc = (0x00<<2), /* No Command */ - TC_CMD_UPDATE_gc = (0x01<<2), /* Force Update */ - TC_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ - TC_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ -} TC_CMD_t; - -/* Fault Detect Action */ -typedef enum AWEX_FDACT_enum -{ - AWEX_FDACT_NONE_gc = (0x00<<0), /* No Fault Protection */ - AWEX_FDACT_CLEAROE_gc = (0x01<<0), /* Clear Output Enable Bits */ - AWEX_FDACT_CLEARDIR_gc = (0x03<<0), /* Clear I/O Port Direction Bits */ -} AWEX_FDACT_t; - -/* High Resolution Enable */ -typedef enum HIRES_HREN_enum -{ - HIRES_HREN_NONE_gc = (0x00<<0), /* No Fault Protection */ - HIRES_HREN_TC0_gc = (0x01<<0), /* Enable High Resolution on Timer/Counter 0 */ - HIRES_HREN_TC1_gc = (0x02<<0), /* Enable High Resolution on Timer/Counter 1 */ - HIRES_HREN_BOTH_gc = (0x03<<0), /* Enable High Resolution both Timer/Counters */ -} HIRES_HREN_t; - - -/* --------------------------------------------------------------------------- -USART - Universal Asynchronous Receiver-Transmitter --------------------------------------------------------------------------- -*/ - -/* Universal Synchronous/Asynchronous Receiver/Transmitter */ -typedef struct USART_struct -{ - register8_t DATA; /* Data Register */ - register8_t STATUS; /* Status Register */ - register8_t reserved_0x02; - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t CTRLC; /* Control Register C */ - register8_t BAUDCTRLA; /* Baud Rate Control Register A */ - register8_t BAUDCTRLB; /* Baud Rate Control Register B */ -} USART_t; - -/* Receive Complete Interrupt level */ -typedef enum USART_RXCINTLVL_enum -{ - USART_RXCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ - USART_RXCINTLVL_LO_gc = (0x01<<4), /* Low Level */ - USART_RXCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ - USART_RXCINTLVL_HI_gc = (0x03<<4), /* High Level */ -} USART_RXCINTLVL_t; - -/* Transmit Complete Interrupt level */ -typedef enum USART_TXCINTLVL_enum -{ - USART_TXCINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ - USART_TXCINTLVL_LO_gc = (0x01<<2), /* Low Level */ - USART_TXCINTLVL_MED_gc = (0x02<<2), /* Medium Level */ - USART_TXCINTLVL_HI_gc = (0x03<<2), /* High Level */ -} USART_TXCINTLVL_t; - -/* Data Register Empty Interrupt level */ -typedef enum USART_DREINTLVL_enum -{ - USART_DREINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - USART_DREINTLVL_LO_gc = (0x01<<0), /* Low Level */ - USART_DREINTLVL_MED_gc = (0x02<<0), /* Medium Level */ - USART_DREINTLVL_HI_gc = (0x03<<0), /* High Level */ -} USART_DREINTLVL_t; - -/* Character Size */ -typedef enum USART_CHSIZE_enum -{ - USART_CHSIZE_5BIT_gc = (0x00<<0), /* Character size: 5 bit */ - USART_CHSIZE_6BIT_gc = (0x01<<0), /* Character size: 6 bit */ - USART_CHSIZE_7BIT_gc = (0x02<<0), /* Character size: 7 bit */ - USART_CHSIZE_8BIT_gc = (0x03<<0), /* Character size: 8 bit */ - USART_CHSIZE_9BIT_gc = (0x07<<0), /* Character size: 9 bit */ -} USART_CHSIZE_t; - -/* Communication Mode */ -typedef enum USART_CMODE_enum -{ - USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6), /* Asynchronous Mode */ - USART_CMODE_SYNCHRONOUS_gc = (0x01<<6), /* Synchronous Mode */ - USART_CMODE_IRDA_gc = (0x02<<6), /* IrDA Mode */ - USART_CMODE_MSPI_gc = (0x03<<6), /* Master SPI Mode */ -} USART_CMODE_t; - -/* Parity Mode */ -typedef enum USART_PMODE_enum -{ - USART_PMODE_DISABLED_gc = (0x00<<4), /* No Parity */ - USART_PMODE_EVEN_gc = (0x02<<4), /* Even Parity */ - USART_PMODE_ODD_gc = (0x03<<4), /* Odd Parity */ -} USART_PMODE_t; - - -/* --------------------------------------------------------------------------- -SPI - Serial Peripheral Interface --------------------------------------------------------------------------- -*/ - -/* Serial Peripheral Interface */ -typedef struct SPI_struct -{ - register8_t CTRL; /* Control Register */ - register8_t INTCTRL; /* Interrupt Control Register */ - register8_t STATUS; /* Status Register */ - register8_t DATA; /* Data Register */ -} SPI_t; - -/* SPI Mode */ -typedef enum SPI_MODE_enum -{ - SPI_MODE_0_gc = (0x00<<2), /* SPI Mode 0 */ - SPI_MODE_1_gc = (0x01<<2), /* SPI Mode 1 */ - SPI_MODE_2_gc = (0x02<<2), /* SPI Mode 2 */ - SPI_MODE_3_gc = (0x03<<2), /* SPI Mode 3 */ -} SPI_MODE_t; - -/* Prescaler setting */ -typedef enum SPI_PRESCALER_enum -{ - SPI_PRESCALER_DIV4_gc = (0x00<<0), /* System Clock / 4 */ - SPI_PRESCALER_DIV16_gc = (0x01<<0), /* System Clock / 16 */ - SPI_PRESCALER_DIV64_gc = (0x02<<0), /* System Clock / 64 */ - SPI_PRESCALER_DIV128_gc = (0x03<<0), /* System Clock / 128 */ -} SPI_PRESCALER_t; - -/* Interrupt level */ -typedef enum SPI_INTLVL_enum -{ - SPI_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - SPI_INTLVL_LO_gc = (0x01<<0), /* Low Level */ - SPI_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ - SPI_INTLVL_HI_gc = (0x03<<0), /* High Level */ -} SPI_INTLVL_t; - - -/* --------------------------------------------------------------------------- -IRCOM - IR Communication Module --------------------------------------------------------------------------- -*/ - -/* IR Communication Module */ -typedef struct IRCOM_struct -{ - register8_t CTRL; /* Control Register */ - register8_t TXPLCTRL; /* IrDA Transmitter Pulse Length Control Register */ - register8_t RXPLCTRL; /* IrDA Receiver Pulse Length Control Register */ -} IRCOM_t; - -/* Event channel selection */ -typedef enum IRDA_EVSEL_enum -{ - IRDA_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ - IRDA_EVSEL_0_gc = (0x08<<0), /* Event Channel 0 */ - IRDA_EVSEL_1_gc = (0x09<<0), /* Event Channel 1 */ - IRDA_EVSEL_2_gc = (0x0A<<0), /* Event Channel 2 */ - IRDA_EVSEL_3_gc = (0x0B<<0), /* Event Channel 3 */ - IRDA_EVSEL_4_gc = (0x0C<<0), /* Event Channel 4 */ - IRDA_EVSEL_5_gc = (0x0D<<0), /* Event Channel 5 */ - IRDA_EVSEL_6_gc = (0x0E<<0), /* Event Channel 6 */ - IRDA_EVSEL_7_gc = (0x0F<<0), /* Event Channel 7 */ -} IRDA_EVSEL_t; - - -/* --------------------------------------------------------------------------- -AES - AES Module --------------------------------------------------------------------------- -*/ - -/* AES Module */ -typedef struct AES_struct -{ - register8_t CTRL; /* AES Control Register */ - register8_t STATUS; /* AES Status Register */ - register8_t STATE; /* AES State Register */ - register8_t KEY; /* AES Key Register */ - register8_t INTCTRL; /* AES Interrupt Control Register */ -} AES_t; - -/* Interrupt level */ -typedef enum AES_INTLVL_enum -{ - AES_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - AES_INTLVL_LO_gc = (0x01<<0), /* Low Level */ - AES_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ - AES_INTLVL_HI_gc = (0x03<<0), /* High Level */ -} AES_INTLVL_t; - - - -/* -========================================================================== -IO Module Instances. Mapped to memory. -========================================================================== -*/ - -#define VPORT0 (*(VPORT_t *) 0x0010) /* Virtual Port 0 */ -#define VPORT1 (*(VPORT_t *) 0x0014) /* Virtual Port 1 */ -#define VPORT2 (*(VPORT_t *) 0x0018) /* Virtual Port 2 */ -#define VPORT3 (*(VPORT_t *) 0x001C) /* Virtual Port 3 */ -#define OCD (*(OCD_t *) 0x002E) /* On-Chip Debug System */ -#define CLK (*(CLK_t *) 0x0040) /* Clock System */ -#define SLEEP (*(SLEEP_t *) 0x0048) /* Sleep Controller */ -#define OSC (*(OSC_t *) 0x0050) /* Oscillator Control */ -#define DFLLRC32M (*(DFLL_t *) 0x0060) /* DFLL for 32MHz RC Oscillator */ -#define DFLLRC2M (*(DFLL_t *) 0x0068) /* DFLL for 2MHz RC Oscillator */ -#define PR (*(PR_t *) 0x0070) /* Power Reduction */ -#define RST (*(RST_t *) 0x0078) /* Reset Controller */ -#define WDT (*(WDT_t *) 0x0080) /* Watch-Dog Timer */ -#define MCU (*(MCU_t *) 0x0090) /* MCU Control */ -#define PMIC (*(PMIC_t *) 0x00A0) /* Programmable Interrupt Controller */ -#define PORTCFG (*(PORTCFG_t *) 0x00B0) /* Port Configuration */ -#define AES (*(AES_t *) 0x00C0) /* AES Crypto Module */ -#define DMA (*(DMA_t *) 0x0100) /* DMA Controller */ -#define EVSYS (*(EVSYS_t *) 0x0180) /* Event System */ -#define NVM (*(NVM_t *) 0x01C0) /* Non Volatile Memory Controller */ -#define ADCA (*(ADC_t *) 0x0200) /* Analog to Digital Converter A */ -#define ADCB (*(ADC_t *) 0x0240) /* Analog to Digital Converter B */ -#define DACA (*(DAC_t *) 0x0300) /* Digitalto Analog Converter A */ -#define DACB (*(DAC_t *) 0x0320) /* Digital to Analog Converter B */ -#define ACA (*(AC_t *) 0x0380) /* Analog Comparator A */ -#define ACB (*(AC_t *) 0x0390) /* Analog Comparator B */ -#define RTC (*(RTC_t *) 0x0400) /* Real-Time Counter */ -#define EBI (*(EBI_t *) 0x0440) /* External Bus Interface */ -#define TWIC (*(TWI_t *) 0x0480) /* Two-Wire Interface C */ -#define TWID (*(TWI_t *) 0x0490) /* Two-Wire Interface D */ -#define TWIE (*(TWI_t *) 0x04A0) /* Two-Wire Interface E */ -#define TWIF (*(TWI_t *) 0x04B0) /* Two-Wire Interface F */ -#define PORTA (*(PORT_t *) 0x0600) /* Port A */ -#define PORTB (*(PORT_t *) 0x0620) /* Port B */ -#define PORTC (*(PORT_t *) 0x0640) /* Port C */ -#define PORTD (*(PORT_t *) 0x0660) /* Port D */ -#define PORTE (*(PORT_t *) 0x0680) /* Port E */ -#define PORTF (*(PORT_t *) 0x06A0) /* Port F */ -#define PORTH (*(PORT_t *) 0x06E0) /* Port H */ -#define PORTJ (*(PORT_t *) 0x0700) /* Port J */ -#define PORTK (*(PORT_t *) 0x0720) /* Port K */ -#define PORTQ (*(PORT_t *) 0x07C0) /* Port Q */ -#define PORTR (*(PORT_t *) 0x07E0) /* Port R */ -#define TCC0 (*(TC0_t *) 0x0800) /* Timer/Counter C0 */ -#define TCC1 (*(TC1_t *) 0x0840) /* Timer/Counter C1 */ -#define AWEXC (*(AWEX_t *) 0x0880) /* Advanced Waveform Extension C */ -#define HIRESC (*(HIRES_t *) 0x0890) /* High-Resolution Extension C */ -#define USARTC0 (*(USART_t *) 0x08A0) /* Universal Asynchronous Receiver-Transmitter C0 */ -#define USARTC1 (*(USART_t *) 0x08B0) /* Universal Asynchronous Receiver-Transmitter C1 */ -#define SPIC (*(SPI_t *) 0x08C0) /* Serial Peripheral Interface C */ -#define IRCOM (*(IRCOM_t *) 0x08F8) /* IR Communication Module */ -#define TCD0 (*(TC0_t *) 0x0900) /* Timer/Counter D0 */ -#define TCD1 (*(TC1_t *) 0x0940) /* Timer/Counter D1 */ -#define HIRESD (*(HIRES_t *) 0x0990) /* High-Resolution Extension D */ -#define USARTD0 (*(USART_t *) 0x09A0) /* Universal Asynchronous Receiver-Transmitter D0 */ -#define USARTD1 (*(USART_t *) 0x09B0) /* Universal Asynchronous Receiver-Transmitter D1 */ -#define SPID (*(SPI_t *) 0x09C0) /* Serial Peripheral Interface D */ -#define TCE0 (*(TC0_t *) 0x0A00) /* Timer/Counter E0 */ -#define TCE1 (*(TC1_t *) 0x0A40) /* Timer/Counter E1 */ -#define AWEXE (*(AWEX_t *) 0x0A80) /* Advanced Waveform Extension E */ -#define HIRESE (*(HIRES_t *) 0x0A90) /* High-Resolution Extension E */ -#define USARTE0 (*(USART_t *) 0x0AA0) /* Universal Asynchronous Receiver-Transmitter E0 */ -#define USARTE1 (*(USART_t *) 0x0AB0) /* Universal Asynchronous Receiver-Transmitter E1 */ -#define SPIE (*(SPI_t *) 0x0AC0) /* Serial Peripheral Interface E */ -#define TCF0 (*(TC0_t *) 0x0B00) /* Timer/Counter F0 */ -#define TCF1 (*(TC1_t *) 0x0B40) /* Timer/Counter F1 */ -#define HIRESF (*(HIRES_t *) 0x0B90) /* High-Resolution Extension F */ -#define USARTF0 (*(USART_t *) 0x0BA0) /* Universal Asynchronous Receiver-Transmitter F0 */ -#define USARTF1 (*(USART_t *) 0x0BB0) /* Universal Asynchronous Receiver-Transmitter F1 */ -#define SPIF (*(SPI_t *) 0x0BC0) /* Serial Peripheral Interface F */ - - -#endif /* !defined (__ASSEMBLER__) */ - - -/* ========== Flattened fully qualified IO register names ========== */ - -/* GPIO - General Purpose IO Registers */ -#define GPIO_GPIOR0 _SFR_MEM8(0x0000) -#define GPIO_GPIOR1 _SFR_MEM8(0x0001) -#define GPIO_GPIOR2 _SFR_MEM8(0x0002) -#define GPIO_GPIOR3 _SFR_MEM8(0x0003) -#define GPIO_GPIOR4 _SFR_MEM8(0x0004) -#define GPIO_GPIOR5 _SFR_MEM8(0x0005) -#define GPIO_GPIOR6 _SFR_MEM8(0x0006) -#define GPIO_GPIOR7 _SFR_MEM8(0x0007) -#define GPIO_GPIOR8 _SFR_MEM8(0x0008) -#define GPIO_GPIOR9 _SFR_MEM8(0x0009) -#define GPIO_GPIORA _SFR_MEM8(0x000A) -#define GPIO_GPIORB _SFR_MEM8(0x000B) -#define GPIO_GPIORC _SFR_MEM8(0x000C) -#define GPIO_GPIORD _SFR_MEM8(0x000D) -#define GPIO_GPIORE _SFR_MEM8(0x000E) -#define GPIO_GPIORF _SFR_MEM8(0x000F) - -/* Deprecated */ -#define GPIO_GPIO0 _SFR_MEM8(0x0000) -#define GPIO_GPIO1 _SFR_MEM8(0x0001) -#define GPIO_GPIO2 _SFR_MEM8(0x0002) -#define GPIO_GPIO3 _SFR_MEM8(0x0003) -#define GPIO_GPIO4 _SFR_MEM8(0x0004) -#define GPIO_GPIO5 _SFR_MEM8(0x0005) -#define GPIO_GPIO6 _SFR_MEM8(0x0006) -#define GPIO_GPIO7 _SFR_MEM8(0x0007) -#define GPIO_GPIO8 _SFR_MEM8(0x0008) -#define GPIO_GPIO9 _SFR_MEM8(0x0009) -#define GPIO_GPIOA _SFR_MEM8(0x000A) -#define GPIO_GPIOB _SFR_MEM8(0x000B) -#define GPIO_GPIOC _SFR_MEM8(0x000C) -#define GPIO_GPIOD _SFR_MEM8(0x000D) -#define GPIO_GPIOE _SFR_MEM8(0x000E) -#define GPIO_GPIOF _SFR_MEM8(0x000F) - -/* VPORT0 - Virtual Port 0 */ -#define VPORT0_DIR _SFR_MEM8(0x0010) -#define VPORT0_OUT _SFR_MEM8(0x0011) -#define VPORT0_IN _SFR_MEM8(0x0012) -#define VPORT0_INTFLAGS _SFR_MEM8(0x0013) - -/* VPORT1 - Virtual Port 1 */ -#define VPORT1_DIR _SFR_MEM8(0x0014) -#define VPORT1_OUT _SFR_MEM8(0x0015) -#define VPORT1_IN _SFR_MEM8(0x0016) -#define VPORT1_INTFLAGS _SFR_MEM8(0x0017) - -/* VPORT2 - Virtual Port 2 */ -#define VPORT2_DIR _SFR_MEM8(0x0018) -#define VPORT2_OUT _SFR_MEM8(0x0019) -#define VPORT2_IN _SFR_MEM8(0x001A) -#define VPORT2_INTFLAGS _SFR_MEM8(0x001B) - -/* VPORT3 - Virtual Port 3 */ -#define VPORT3_DIR _SFR_MEM8(0x001C) -#define VPORT3_OUT _SFR_MEM8(0x001D) -#define VPORT3_IN _SFR_MEM8(0x001E) -#define VPORT3_INTFLAGS _SFR_MEM8(0x001F) - -/* OCD - On-Chip Debug System */ -#define OCD_OCDR0 _SFR_MEM8(0x002E) -#define OCD_OCDR1 _SFR_MEM8(0x002F) - -/* CPU - CPU Registers */ -#define CPU_CCP _SFR_MEM8(0x0034) -#define CPU_RAMPD _SFR_MEM8(0x0038) -#define CPU_RAMPX _SFR_MEM8(0x0039) -#define CPU_RAMPY _SFR_MEM8(0x003A) -#define CPU_RAMPZ _SFR_MEM8(0x003B) -#define CPU_EIND _SFR_MEM8(0x003C) -#define CPU_SPL _SFR_MEM8(0x003D) -#define CPU_SPH _SFR_MEM8(0x003E) -#define CPU_SREG _SFR_MEM8(0x003F) - -/* CLK - Clock System */ -#define CLK_CTRL _SFR_MEM8(0x0040) -#define CLK_PSCTRL _SFR_MEM8(0x0041) -#define CLK_LOCK _SFR_MEM8(0x0042) -#define CLK_RTCCTRL _SFR_MEM8(0x0043) - -/* SLEEP - Sleep Controller */ -#define SLEEP_CTRL _SFR_MEM8(0x0048) - -/* OSC - Oscillator Control */ -#define OSC_CTRL _SFR_MEM8(0x0050) -#define OSC_STATUS _SFR_MEM8(0x0051) -#define OSC_XOSCCTRL _SFR_MEM8(0x0052) -#define OSC_XOSCFAIL _SFR_MEM8(0x0053) -#define OSC_RC32KCAL _SFR_MEM8(0x0054) -#define OSC_PLLCTRL _SFR_MEM8(0x0055) -#define OSC_DFLLCTRL _SFR_MEM8(0x0056) - -/* DFLLRC32M - DFLL for 32MHz RC Oscillator */ -#define DFLLRC32M_CTRL _SFR_MEM8(0x0060) -#define DFLLRC32M_CALA _SFR_MEM8(0x0062) -#define DFLLRC32M_CALB _SFR_MEM8(0x0063) -#define DFLLRC32M_COMP0 _SFR_MEM8(0x0064) -#define DFLLRC32M_COMP1 _SFR_MEM8(0x0065) -#define DFLLRC32M_COMP2 _SFR_MEM8(0x0066) - -/* DFLLRC2M - DFLL for 2MHz RC Oscillator */ -#define DFLLRC2M_CTRL _SFR_MEM8(0x0068) -#define DFLLRC2M_CALA _SFR_MEM8(0x006A) -#define DFLLRC2M_CALB _SFR_MEM8(0x006B) -#define DFLLRC2M_COMP0 _SFR_MEM8(0x006C) -#define DFLLRC2M_COMP1 _SFR_MEM8(0x006D) -#define DFLLRC2M_COMP2 _SFR_MEM8(0x006E) - -/* PR - Power Reduction */ -#define PR_PRGEN _SFR_MEM8(0x0070) -#define PR_PRPA _SFR_MEM8(0x0071) -#define PR_PRPB _SFR_MEM8(0x0072) -#define PR_PRPC _SFR_MEM8(0x0073) -#define PR_PRPD _SFR_MEM8(0x0074) -#define PR_PRPE _SFR_MEM8(0x0075) -#define PR_PRPF _SFR_MEM8(0x0076) - -/* RST - Reset Controller */ -#define RST_STATUS _SFR_MEM8(0x0078) -#define RST_CTRL _SFR_MEM8(0x0079) - -/* WDT - Watch-Dog Timer */ -#define WDT_CTRL _SFR_MEM8(0x0080) -#define WDT_WINCTRL _SFR_MEM8(0x0081) -#define WDT_STATUS _SFR_MEM8(0x0082) - -/* MCU - MCU Control */ -#define MCU_DEVID0 _SFR_MEM8(0x0090) -#define MCU_DEVID1 _SFR_MEM8(0x0091) -#define MCU_DEVID2 _SFR_MEM8(0x0092) -#define MCU_REVID _SFR_MEM8(0x0093) -#define MCU_JTAGUID _SFR_MEM8(0x0094) -#define MCU_MCUCR _SFR_MEM8(0x0096) -#define MCU_EVSYSLOCK _SFR_MEM8(0x0098) -#define MCU_AWEXLOCK _SFR_MEM8(0x0099) - -/* PMIC - Programmable Interrupt Controller */ -#define PMIC_STATUS _SFR_MEM8(0x00A0) -#define PMIC_INTPRI _SFR_MEM8(0x00A1) -#define PMIC_CTRL _SFR_MEM8(0x00A2) - -/* PORTCFG - Port Configuration */ -#define PORTCFG_MPCMASK _SFR_MEM8(0x00B0) -#define PORTCFG_VPCTRLA _SFR_MEM8(0x00B2) -#define PORTCFG_VPCTRLB _SFR_MEM8(0x00B3) -#define PORTCFG_CLKEVOUT _SFR_MEM8(0x00B4) - -/* AES - AES Crypto Module */ -#define AES_CTRL _SFR_MEM8(0x00C0) -#define AES_STATUS _SFR_MEM8(0x00C1) -#define AES_STATE _SFR_MEM8(0x00C2) -#define AES_KEY _SFR_MEM8(0x00C3) -#define AES_INTCTRL _SFR_MEM8(0x00C4) - -/* DMA - DMA Controller */ -#define DMA_CTRL _SFR_MEM8(0x0100) -#define DMA_INTFLAGS _SFR_MEM8(0x0103) -#define DMA_STATUS _SFR_MEM8(0x0104) -#define DMA_TEMP _SFR_MEM16(0x0106) -#define DMA_CH0_CTRLA _SFR_MEM8(0x0110) -#define DMA_CH0_CTRLB _SFR_MEM8(0x0111) -#define DMA_CH0_ADDRCTRL _SFR_MEM8(0x0112) -#define DMA_CH0_TRIGSRC _SFR_MEM8(0x0113) -#define DMA_CH0_TRFCNT _SFR_MEM16(0x0114) -#define DMA_CH0_REPCNT _SFR_MEM8(0x0116) -#define DMA_CH0_SRCADDR0 _SFR_MEM8(0x0118) -#define DMA_CH0_SRCADDR1 _SFR_MEM8(0x0119) -#define DMA_CH0_SRCADDR2 _SFR_MEM8(0x011A) -#define DMA_CH0_DESTADDR0 _SFR_MEM8(0x011C) -#define DMA_CH0_DESTADDR1 _SFR_MEM8(0x011D) -#define DMA_CH0_DESTADDR2 _SFR_MEM8(0x011E) -#define DMA_CH1_CTRLA _SFR_MEM8(0x0120) -#define DMA_CH1_CTRLB _SFR_MEM8(0x0121) -#define DMA_CH1_ADDRCTRL _SFR_MEM8(0x0122) -#define DMA_CH1_TRIGSRC _SFR_MEM8(0x0123) -#define DMA_CH1_TRFCNT _SFR_MEM16(0x0124) -#define DMA_CH1_REPCNT _SFR_MEM8(0x0126) -#define DMA_CH1_SRCADDR0 _SFR_MEM8(0x0128) -#define DMA_CH1_SRCADDR1 _SFR_MEM8(0x0129) -#define DMA_CH1_SRCADDR2 _SFR_MEM8(0x012A) -#define DMA_CH1_DESTADDR0 _SFR_MEM8(0x012C) -#define DMA_CH1_DESTADDR1 _SFR_MEM8(0x012D) -#define DMA_CH1_DESTADDR2 _SFR_MEM8(0x012E) -#define DMA_CH2_CTRLA _SFR_MEM8(0x0130) -#define DMA_CH2_CTRLB _SFR_MEM8(0x0131) -#define DMA_CH2_ADDRCTRL _SFR_MEM8(0x0132) -#define DMA_CH2_TRIGSRC _SFR_MEM8(0x0133) -#define DMA_CH2_TRFCNT _SFR_MEM16(0x0134) -#define DMA_CH2_REPCNT _SFR_MEM8(0x0136) -#define DMA_CH2_SRCADDR0 _SFR_MEM8(0x0138) -#define DMA_CH2_SRCADDR1 _SFR_MEM8(0x0139) -#define DMA_CH2_SRCADDR2 _SFR_MEM8(0x013A) -#define DMA_CH2_DESTADDR0 _SFR_MEM8(0x013C) -#define DMA_CH2_DESTADDR1 _SFR_MEM8(0x013D) -#define DMA_CH2_DESTADDR2 _SFR_MEM8(0x013E) -#define DMA_CH3_CTRLA _SFR_MEM8(0x0140) -#define DMA_CH3_CTRLB _SFR_MEM8(0x0141) -#define DMA_CH3_ADDRCTRL _SFR_MEM8(0x0142) -#define DMA_CH3_TRIGSRC _SFR_MEM8(0x0143) -#define DMA_CH3_TRFCNT _SFR_MEM16(0x0144) -#define DMA_CH3_REPCNT _SFR_MEM8(0x0146) -#define DMA_CH3_SRCADDR0 _SFR_MEM8(0x0148) -#define DMA_CH3_SRCADDR1 _SFR_MEM8(0x0149) -#define DMA_CH3_SRCADDR2 _SFR_MEM8(0x014A) -#define DMA_CH3_DESTADDR0 _SFR_MEM8(0x014C) -#define DMA_CH3_DESTADDR1 _SFR_MEM8(0x014D) -#define DMA_CH3_DESTADDR2 _SFR_MEM8(0x014E) - -/* EVSYS - Event System */ -#define EVSYS_CH0MUX _SFR_MEM8(0x0180) -#define EVSYS_CH1MUX _SFR_MEM8(0x0181) -#define EVSYS_CH2MUX _SFR_MEM8(0x0182) -#define EVSYS_CH3MUX _SFR_MEM8(0x0183) -#define EVSYS_CH4MUX _SFR_MEM8(0x0184) -#define EVSYS_CH5MUX _SFR_MEM8(0x0185) -#define EVSYS_CH6MUX _SFR_MEM8(0x0186) -#define EVSYS_CH7MUX _SFR_MEM8(0x0187) -#define EVSYS_CH0CTRL _SFR_MEM8(0x0188) -#define EVSYS_CH1CTRL _SFR_MEM8(0x0189) -#define EVSYS_CH2CTRL _SFR_MEM8(0x018A) -#define EVSYS_CH3CTRL _SFR_MEM8(0x018B) -#define EVSYS_CH4CTRL _SFR_MEM8(0x018C) -#define EVSYS_CH5CTRL _SFR_MEM8(0x018D) -#define EVSYS_CH6CTRL _SFR_MEM8(0x018E) -#define EVSYS_CH7CTRL _SFR_MEM8(0x018F) -#define EVSYS_STROBE _SFR_MEM8(0x0190) -#define EVSYS_DATA _SFR_MEM8(0x0191) - -/* NVM - Non Volatile Memory Controller */ -#define NVM_ADDR0 _SFR_MEM8(0x01C0) -#define NVM_ADDR1 _SFR_MEM8(0x01C1) -#define NVM_ADDR2 _SFR_MEM8(0x01C2) -#define NVM_DATA0 _SFR_MEM8(0x01C4) -#define NVM_DATA1 _SFR_MEM8(0x01C5) -#define NVM_DATA2 _SFR_MEM8(0x01C6) -#define NVM_CMD _SFR_MEM8(0x01CA) -#define NVM_CTRLA _SFR_MEM8(0x01CB) -#define NVM_CTRLB _SFR_MEM8(0x01CC) -#define NVM_INTCTRL _SFR_MEM8(0x01CD) -#define NVM_STATUS _SFR_MEM8(0x01CF) -#define NVM_LOCKBITS _SFR_MEM8(0x01D0) - -/* ADCA - Analog to Digital Converter A */ -#define ADCA_CTRLA _SFR_MEM8(0x0200) -#define ADCA_CTRLB _SFR_MEM8(0x0201) -#define ADCA_REFCTRL _SFR_MEM8(0x0202) -#define ADCA_EVCTRL _SFR_MEM8(0x0203) -#define ADCA_PRESCALER _SFR_MEM8(0x0204) -#define ADCA_INTFLAGS _SFR_MEM8(0x0206) -#define ADCA_CAL _SFR_MEM16(0x020C) -#define ADCA_CH0RES _SFR_MEM16(0x0210) -#define ADCA_CH1RES _SFR_MEM16(0x0212) -#define ADCA_CH2RES _SFR_MEM16(0x0214) -#define ADCA_CH3RES _SFR_MEM16(0x0216) -#define ADCA_CMP _SFR_MEM16(0x0218) -#define ADCA_CH0_CTRL _SFR_MEM8(0x0220) -#define ADCA_CH0_MUXCTRL _SFR_MEM8(0x0221) -#define ADCA_CH0_INTCTRL _SFR_MEM8(0x0222) -#define ADCA_CH0_INTFLAGS _SFR_MEM8(0x0223) -#define ADCA_CH0_RES _SFR_MEM16(0x0224) -#define ADCA_CH1_CTRL _SFR_MEM8(0x0228) -#define ADCA_CH1_MUXCTRL _SFR_MEM8(0x0229) -#define ADCA_CH1_INTCTRL _SFR_MEM8(0x022A) -#define ADCA_CH1_INTFLAGS _SFR_MEM8(0x022B) -#define ADCA_CH1_RES _SFR_MEM16(0x022C) -#define ADCA_CH2_CTRL _SFR_MEM8(0x0230) -#define ADCA_CH2_MUXCTRL _SFR_MEM8(0x0231) -#define ADCA_CH2_INTCTRL _SFR_MEM8(0x0232) -#define ADCA_CH2_INTFLAGS _SFR_MEM8(0x0233) -#define ADCA_CH2_RES _SFR_MEM16(0x0234) -#define ADCA_CH3_CTRL _SFR_MEM8(0x0238) -#define ADCA_CH3_MUXCTRL _SFR_MEM8(0x0239) -#define ADCA_CH3_INTCTRL _SFR_MEM8(0x023A) -#define ADCA_CH3_INTFLAGS _SFR_MEM8(0x023B) -#define ADCA_CH3_RES _SFR_MEM16(0x023C) - -/* ADCB - Analog to Digital Converter B */ -#define ADCB_CTRLA _SFR_MEM8(0x0240) -#define ADCB_CTRLB _SFR_MEM8(0x0241) -#define ADCB_REFCTRL _SFR_MEM8(0x0242) -#define ADCB_EVCTRL _SFR_MEM8(0x0243) -#define ADCB_PRESCALER _SFR_MEM8(0x0244) -#define ADCB_INTFLAGS _SFR_MEM8(0x0246) -#define ADCB_CAL _SFR_MEM16(0x024C) -#define ADCB_CH0RES _SFR_MEM16(0x0250) -#define ADCB_CH1RES _SFR_MEM16(0x0252) -#define ADCB_CH2RES _SFR_MEM16(0x0254) -#define ADCB_CH3RES _SFR_MEM16(0x0256) -#define ADCB_CMP _SFR_MEM16(0x0258) -#define ADCB_CH0_CTRL _SFR_MEM8(0x0260) -#define ADCB_CH0_MUXCTRL _SFR_MEM8(0x0261) -#define ADCB_CH0_INTCTRL _SFR_MEM8(0x0262) -#define ADCB_CH0_INTFLAGS _SFR_MEM8(0x0263) -#define ADCB_CH0_RES _SFR_MEM16(0x0264) -#define ADCB_CH1_CTRL _SFR_MEM8(0x0268) -#define ADCB_CH1_MUXCTRL _SFR_MEM8(0x0269) -#define ADCB_CH1_INTCTRL _SFR_MEM8(0x026A) -#define ADCB_CH1_INTFLAGS _SFR_MEM8(0x026B) -#define ADCB_CH1_RES _SFR_MEM16(0x026C) -#define ADCB_CH2_CTRL _SFR_MEM8(0x0270) -#define ADCB_CH2_MUXCTRL _SFR_MEM8(0x0271) -#define ADCB_CH2_INTCTRL _SFR_MEM8(0x0272) -#define ADCB_CH2_INTFLAGS _SFR_MEM8(0x0273) -#define ADCB_CH2_RES _SFR_MEM16(0x0274) -#define ADCB_CH3_CTRL _SFR_MEM8(0x0278) -#define ADCB_CH3_MUXCTRL _SFR_MEM8(0x0279) -#define ADCB_CH3_INTCTRL _SFR_MEM8(0x027A) -#define ADCB_CH3_INTFLAGS _SFR_MEM8(0x027B) -#define ADCB_CH3_RES _SFR_MEM16(0x027C) - -/* DACA - Digitalto Analog Converter A */ -#define DACA_CTRLA _SFR_MEM8(0x0300) -#define DACA_CTRLB _SFR_MEM8(0x0301) -#define DACA_CTRLC _SFR_MEM8(0x0302) -#define DACA_EVCTRL _SFR_MEM8(0x0303) -#define DACA_TIMCTRL _SFR_MEM8(0x0304) -#define DACA_STATUS _SFR_MEM8(0x0305) -#define DACA_GAINCAL _SFR_MEM8(0x0308) -#define DACA_OFFSETCAL _SFR_MEM8(0x0309) -#define DACA_CH0DATA _SFR_MEM16(0x0318) -#define DACA_CH1DATA _SFR_MEM16(0x031A) - -/* DACB - Digital to Analog Converter B */ -#define DACB_CTRLA _SFR_MEM8(0x0320) -#define DACB_CTRLB _SFR_MEM8(0x0321) -#define DACB_CTRLC _SFR_MEM8(0x0322) -#define DACB_EVCTRL _SFR_MEM8(0x0323) -#define DACB_TIMCTRL _SFR_MEM8(0x0324) -#define DACB_STATUS _SFR_MEM8(0x0325) -#define DACB_GAINCAL _SFR_MEM8(0x0328) -#define DACB_OFFSETCAL _SFR_MEM8(0x0329) -#define DACB_CH0DATA _SFR_MEM16(0x0338) -#define DACB_CH1DATA _SFR_MEM16(0x033A) - -/* ACA - Analog Comparator A */ -#define ACA_AC0CTRL _SFR_MEM8(0x0380) -#define ACA_AC1CTRL _SFR_MEM8(0x0381) -#define ACA_AC0MUXCTRL _SFR_MEM8(0x0382) -#define ACA_AC1MUXCTRL _SFR_MEM8(0x0383) -#define ACA_CTRLA _SFR_MEM8(0x0384) -#define ACA_CTRLB _SFR_MEM8(0x0385) -#define ACA_WINCTRL _SFR_MEM8(0x0386) -#define ACA_STATUS _SFR_MEM8(0x0387) - -/* ACB - Analog Comparator B */ -#define ACB_AC0CTRL _SFR_MEM8(0x0390) -#define ACB_AC1CTRL _SFR_MEM8(0x0391) -#define ACB_AC0MUXCTRL _SFR_MEM8(0x0392) -#define ACB_AC1MUXCTRL _SFR_MEM8(0x0393) -#define ACB_CTRLA _SFR_MEM8(0x0394) -#define ACB_CTRLB _SFR_MEM8(0x0395) -#define ACB_WINCTRL _SFR_MEM8(0x0396) -#define ACB_STATUS _SFR_MEM8(0x0397) - -/* RTC - Real-Time Counter */ -#define RTC_CTRL _SFR_MEM8(0x0400) -#define RTC_STATUS _SFR_MEM8(0x0401) -#define RTC_INTCTRL _SFR_MEM8(0x0402) -#define RTC_INTFLAGS _SFR_MEM8(0x0403) -#define RTC_TEMP _SFR_MEM8(0x0404) -#define RTC_CNT _SFR_MEM16(0x0408) -#define RTC_PER _SFR_MEM16(0x040A) -#define RTC_COMP _SFR_MEM16(0x040C) - -/* EBI - External Bus Interface */ -#define EBI_CTRL _SFR_MEM8(0x0440) -#define EBI_SDRAMCTRLA _SFR_MEM8(0x0441) -#define EBI_REFRESH _SFR_MEM16(0x0444) -#define EBI_INITDLY _SFR_MEM16(0x0446) -#define EBI_SDRAMCTRLB _SFR_MEM8(0x0448) -#define EBI_SDRAMCTRLC _SFR_MEM8(0x0449) -#define EBI_CS0_CTRLA _SFR_MEM8(0x0450) -#define EBI_CS0_CTRLB _SFR_MEM8(0x0451) -#define EBI_CS0_BASEADDR _SFR_MEM16(0x0452) -#define EBI_CS1_CTRLA _SFR_MEM8(0x0454) -#define EBI_CS1_CTRLB _SFR_MEM8(0x0455) -#define EBI_CS1_BASEADDR _SFR_MEM16(0x0456) -#define EBI_CS2_CTRLA _SFR_MEM8(0x0458) -#define EBI_CS2_CTRLB _SFR_MEM8(0x0459) -#define EBI_CS2_BASEADDR _SFR_MEM16(0x045A) -#define EBI_CS3_CTRLA _SFR_MEM8(0x045C) -#define EBI_CS3_CTRLB _SFR_MEM8(0x045D) -#define EBI_CS3_BASEADDR _SFR_MEM16(0x045E) - -/* TWIC - Two-Wire Interface C */ -#define TWIC_CTRL _SFR_MEM8(0x0480) -#define TWIC_MASTER_CTRLA _SFR_MEM8(0x0481) -#define TWIC_MASTER_CTRLB _SFR_MEM8(0x0482) -#define TWIC_MASTER_CTRLC _SFR_MEM8(0x0483) -#define TWIC_MASTER_STATUS _SFR_MEM8(0x0484) -#define TWIC_MASTER_BAUD _SFR_MEM8(0x0485) -#define TWIC_MASTER_ADDR _SFR_MEM8(0x0486) -#define TWIC_MASTER_DATA _SFR_MEM8(0x0487) -#define TWIC_SLAVE_CTRLA _SFR_MEM8(0x0488) -#define TWIC_SLAVE_CTRLB _SFR_MEM8(0x0489) -#define TWIC_SLAVE_STATUS _SFR_MEM8(0x048A) -#define TWIC_SLAVE_ADDR _SFR_MEM8(0x048B) -#define TWIC_SLAVE_DATA _SFR_MEM8(0x048C) -#define TWIC_SLAVE_ADDRMASK _SFR_MEM8(0x048D) - -/* TWID - Two-Wire Interface D */ -#define TWID_CTRL _SFR_MEM8(0x0490) -#define TWID_MASTER_CTRLA _SFR_MEM8(0x0491) -#define TWID_MASTER_CTRLB _SFR_MEM8(0x0492) -#define TWID_MASTER_CTRLC _SFR_MEM8(0x0493) -#define TWID_MASTER_STATUS _SFR_MEM8(0x0494) -#define TWID_MASTER_BAUD _SFR_MEM8(0x0495) -#define TWID_MASTER_ADDR _SFR_MEM8(0x0496) -#define TWID_MASTER_DATA _SFR_MEM8(0x0497) -#define TWID_SLAVE_CTRLA _SFR_MEM8(0x0498) -#define TWID_SLAVE_CTRLB _SFR_MEM8(0x0499) -#define TWID_SLAVE_STATUS _SFR_MEM8(0x049A) -#define TWID_SLAVE_ADDR _SFR_MEM8(0x049B) -#define TWID_SLAVE_DATA _SFR_MEM8(0x049C) -#define TWID_SLAVE_ADDRMASK _SFR_MEM8(0x049D) - -/* TWIE - Two-Wire Interface E */ -#define TWIE_CTRL _SFR_MEM8(0x04A0) -#define TWIE_MASTER_CTRLA _SFR_MEM8(0x04A1) -#define TWIE_MASTER_CTRLB _SFR_MEM8(0x04A2) -#define TWIE_MASTER_CTRLC _SFR_MEM8(0x04A3) -#define TWIE_MASTER_STATUS _SFR_MEM8(0x04A4) -#define TWIE_MASTER_BAUD _SFR_MEM8(0x04A5) -#define TWIE_MASTER_ADDR _SFR_MEM8(0x04A6) -#define TWIE_MASTER_DATA _SFR_MEM8(0x04A7) -#define TWIE_SLAVE_CTRLA _SFR_MEM8(0x04A8) -#define TWIE_SLAVE_CTRLB _SFR_MEM8(0x04A9) -#define TWIE_SLAVE_STATUS _SFR_MEM8(0x04AA) -#define TWIE_SLAVE_ADDR _SFR_MEM8(0x04AB) -#define TWIE_SLAVE_DATA _SFR_MEM8(0x04AC) -#define TWIE_SLAVE_ADDRMASK _SFR_MEM8(0x04AD) - -/* TWIF - Two-Wire Interface F */ -#define TWIF_CTRL _SFR_MEM8(0x04B0) -#define TWIF_MASTER_CTRLA _SFR_MEM8(0x04B1) -#define TWIF_MASTER_CTRLB _SFR_MEM8(0x04B2) -#define TWIF_MASTER_CTRLC _SFR_MEM8(0x04B3) -#define TWIF_MASTER_STATUS _SFR_MEM8(0x04B4) -#define TWIF_MASTER_BAUD _SFR_MEM8(0x04B5) -#define TWIF_MASTER_ADDR _SFR_MEM8(0x04B6) -#define TWIF_MASTER_DATA _SFR_MEM8(0x04B7) -#define TWIF_SLAVE_CTRLA _SFR_MEM8(0x04B8) -#define TWIF_SLAVE_CTRLB _SFR_MEM8(0x04B9) -#define TWIF_SLAVE_STATUS _SFR_MEM8(0x04BA) -#define TWIF_SLAVE_ADDR _SFR_MEM8(0x04BB) -#define TWIF_SLAVE_DATA _SFR_MEM8(0x04BC) -#define TWIF_SLAVE_ADDRMASK _SFR_MEM8(0x04BD) - -/* PORTA - Port A */ -#define PORTA_DIR _SFR_MEM8(0x0600) -#define PORTA_DIRSET _SFR_MEM8(0x0601) -#define PORTA_DIRCLR _SFR_MEM8(0x0602) -#define PORTA_DIRTGL _SFR_MEM8(0x0603) -#define PORTA_OUT _SFR_MEM8(0x0604) -#define PORTA_OUTSET _SFR_MEM8(0x0605) -#define PORTA_OUTCLR _SFR_MEM8(0x0606) -#define PORTA_OUTTGL _SFR_MEM8(0x0607) -#define PORTA_IN _SFR_MEM8(0x0608) -#define PORTA_INTCTRL _SFR_MEM8(0x0609) -#define PORTA_INT0MASK _SFR_MEM8(0x060A) -#define PORTA_INT1MASK _SFR_MEM8(0x060B) -#define PORTA_INTFLAGS _SFR_MEM8(0x060C) -#define PORTA_PIN0CTRL _SFR_MEM8(0x0610) -#define PORTA_PIN1CTRL _SFR_MEM8(0x0611) -#define PORTA_PIN2CTRL _SFR_MEM8(0x0612) -#define PORTA_PIN3CTRL _SFR_MEM8(0x0613) -#define PORTA_PIN4CTRL _SFR_MEM8(0x0614) -#define PORTA_PIN5CTRL _SFR_MEM8(0x0615) -#define PORTA_PIN6CTRL _SFR_MEM8(0x0616) -#define PORTA_PIN7CTRL _SFR_MEM8(0x0617) - -/* PORTB - Port B */ -#define PORTB_DIR _SFR_MEM8(0x0620) -#define PORTB_DIRSET _SFR_MEM8(0x0621) -#define PORTB_DIRCLR _SFR_MEM8(0x0622) -#define PORTB_DIRTGL _SFR_MEM8(0x0623) -#define PORTB_OUT _SFR_MEM8(0x0624) -#define PORTB_OUTSET _SFR_MEM8(0x0625) -#define PORTB_OUTCLR _SFR_MEM8(0x0626) -#define PORTB_OUTTGL _SFR_MEM8(0x0627) -#define PORTB_IN _SFR_MEM8(0x0628) -#define PORTB_INTCTRL _SFR_MEM8(0x0629) -#define PORTB_INT0MASK _SFR_MEM8(0x062A) -#define PORTB_INT1MASK _SFR_MEM8(0x062B) -#define PORTB_INTFLAGS _SFR_MEM8(0x062C) -#define PORTB_PIN0CTRL _SFR_MEM8(0x0630) -#define PORTB_PIN1CTRL _SFR_MEM8(0x0631) -#define PORTB_PIN2CTRL _SFR_MEM8(0x0632) -#define PORTB_PIN3CTRL _SFR_MEM8(0x0633) -#define PORTB_PIN4CTRL _SFR_MEM8(0x0634) -#define PORTB_PIN5CTRL _SFR_MEM8(0x0635) -#define PORTB_PIN6CTRL _SFR_MEM8(0x0636) -#define PORTB_PIN7CTRL _SFR_MEM8(0x0637) - -/* PORTC - Port C */ -#define PORTC_DIR _SFR_MEM8(0x0640) -#define PORTC_DIRSET _SFR_MEM8(0x0641) -#define PORTC_DIRCLR _SFR_MEM8(0x0642) -#define PORTC_DIRTGL _SFR_MEM8(0x0643) -#define PORTC_OUT _SFR_MEM8(0x0644) -#define PORTC_OUTSET _SFR_MEM8(0x0645) -#define PORTC_OUTCLR _SFR_MEM8(0x0646) -#define PORTC_OUTTGL _SFR_MEM8(0x0647) -#define PORTC_IN _SFR_MEM8(0x0648) -#define PORTC_INTCTRL _SFR_MEM8(0x0649) -#define PORTC_INT0MASK _SFR_MEM8(0x064A) -#define PORTC_INT1MASK _SFR_MEM8(0x064B) -#define PORTC_INTFLAGS _SFR_MEM8(0x064C) -#define PORTC_PIN0CTRL _SFR_MEM8(0x0650) -#define PORTC_PIN1CTRL _SFR_MEM8(0x0651) -#define PORTC_PIN2CTRL _SFR_MEM8(0x0652) -#define PORTC_PIN3CTRL _SFR_MEM8(0x0653) -#define PORTC_PIN4CTRL _SFR_MEM8(0x0654) -#define PORTC_PIN5CTRL _SFR_MEM8(0x0655) -#define PORTC_PIN6CTRL _SFR_MEM8(0x0656) -#define PORTC_PIN7CTRL _SFR_MEM8(0x0657) - -/* PORTD - Port D */ -#define PORTD_DIR _SFR_MEM8(0x0660) -#define PORTD_DIRSET _SFR_MEM8(0x0661) -#define PORTD_DIRCLR _SFR_MEM8(0x0662) -#define PORTD_DIRTGL _SFR_MEM8(0x0663) -#define PORTD_OUT _SFR_MEM8(0x0664) -#define PORTD_OUTSET _SFR_MEM8(0x0665) -#define PORTD_OUTCLR _SFR_MEM8(0x0666) -#define PORTD_OUTTGL _SFR_MEM8(0x0667) -#define PORTD_IN _SFR_MEM8(0x0668) -#define PORTD_INTCTRL _SFR_MEM8(0x0669) -#define PORTD_INT0MASK _SFR_MEM8(0x066A) -#define PORTD_INT1MASK _SFR_MEM8(0x066B) -#define PORTD_INTFLAGS _SFR_MEM8(0x066C) -#define PORTD_PIN0CTRL _SFR_MEM8(0x0670) -#define PORTD_PIN1CTRL _SFR_MEM8(0x0671) -#define PORTD_PIN2CTRL _SFR_MEM8(0x0672) -#define PORTD_PIN3CTRL _SFR_MEM8(0x0673) -#define PORTD_PIN4CTRL _SFR_MEM8(0x0674) -#define PORTD_PIN5CTRL _SFR_MEM8(0x0675) -#define PORTD_PIN6CTRL _SFR_MEM8(0x0676) -#define PORTD_PIN7CTRL _SFR_MEM8(0x0677) - -/* PORTE - Port E */ -#define PORTE_DIR _SFR_MEM8(0x0680) -#define PORTE_DIRSET _SFR_MEM8(0x0681) -#define PORTE_DIRCLR _SFR_MEM8(0x0682) -#define PORTE_DIRTGL _SFR_MEM8(0x0683) -#define PORTE_OUT _SFR_MEM8(0x0684) -#define PORTE_OUTSET _SFR_MEM8(0x0685) -#define PORTE_OUTCLR _SFR_MEM8(0x0686) -#define PORTE_OUTTGL _SFR_MEM8(0x0687) -#define PORTE_IN _SFR_MEM8(0x0688) -#define PORTE_INTCTRL _SFR_MEM8(0x0689) -#define PORTE_INT0MASK _SFR_MEM8(0x068A) -#define PORTE_INT1MASK _SFR_MEM8(0x068B) -#define PORTE_INTFLAGS _SFR_MEM8(0x068C) -#define PORTE_PIN0CTRL _SFR_MEM8(0x0690) -#define PORTE_PIN1CTRL _SFR_MEM8(0x0691) -#define PORTE_PIN2CTRL _SFR_MEM8(0x0692) -#define PORTE_PIN3CTRL _SFR_MEM8(0x0693) -#define PORTE_PIN4CTRL _SFR_MEM8(0x0694) -#define PORTE_PIN5CTRL _SFR_MEM8(0x0695) -#define PORTE_PIN6CTRL _SFR_MEM8(0x0696) -#define PORTE_PIN7CTRL _SFR_MEM8(0x0697) - -/* PORTF - Port F */ -#define PORTF_DIR _SFR_MEM8(0x06A0) -#define PORTF_DIRSET _SFR_MEM8(0x06A1) -#define PORTF_DIRCLR _SFR_MEM8(0x06A2) -#define PORTF_DIRTGL _SFR_MEM8(0x06A3) -#define PORTF_OUT _SFR_MEM8(0x06A4) -#define PORTF_OUTSET _SFR_MEM8(0x06A5) -#define PORTF_OUTCLR _SFR_MEM8(0x06A6) -#define PORTF_OUTTGL _SFR_MEM8(0x06A7) -#define PORTF_IN _SFR_MEM8(0x06A8) -#define PORTF_INTCTRL _SFR_MEM8(0x06A9) -#define PORTF_INT0MASK _SFR_MEM8(0x06AA) -#define PORTF_INT1MASK _SFR_MEM8(0x06AB) -#define PORTF_INTFLAGS _SFR_MEM8(0x06AC) -#define PORTF_PIN0CTRL _SFR_MEM8(0x06B0) -#define PORTF_PIN1CTRL _SFR_MEM8(0x06B1) -#define PORTF_PIN2CTRL _SFR_MEM8(0x06B2) -#define PORTF_PIN3CTRL _SFR_MEM8(0x06B3) -#define PORTF_PIN4CTRL _SFR_MEM8(0x06B4) -#define PORTF_PIN5CTRL _SFR_MEM8(0x06B5) -#define PORTF_PIN6CTRL _SFR_MEM8(0x06B6) -#define PORTF_PIN7CTRL _SFR_MEM8(0x06B7) - -/* PORTH - Port H */ -#define PORTH_DIR _SFR_MEM8(0x06E0) -#define PORTH_DIRSET _SFR_MEM8(0x06E1) -#define PORTH_DIRCLR _SFR_MEM8(0x06E2) -#define PORTH_DIRTGL _SFR_MEM8(0x06E3) -#define PORTH_OUT _SFR_MEM8(0x06E4) -#define PORTH_OUTSET _SFR_MEM8(0x06E5) -#define PORTH_OUTCLR _SFR_MEM8(0x06E6) -#define PORTH_OUTTGL _SFR_MEM8(0x06E7) -#define PORTH_IN _SFR_MEM8(0x06E8) -#define PORTH_INTCTRL _SFR_MEM8(0x06E9) -#define PORTH_INT0MASK _SFR_MEM8(0x06EA) -#define PORTH_INT1MASK _SFR_MEM8(0x06EB) -#define PORTH_INTFLAGS _SFR_MEM8(0x06EC) -#define PORTH_PIN0CTRL _SFR_MEM8(0x06F0) -#define PORTH_PIN1CTRL _SFR_MEM8(0x06F1) -#define PORTH_PIN2CTRL _SFR_MEM8(0x06F2) -#define PORTH_PIN3CTRL _SFR_MEM8(0x06F3) -#define PORTH_PIN4CTRL _SFR_MEM8(0x06F4) -#define PORTH_PIN5CTRL _SFR_MEM8(0x06F5) -#define PORTH_PIN6CTRL _SFR_MEM8(0x06F6) -#define PORTH_PIN7CTRL _SFR_MEM8(0x06F7) - -/* PORTJ - Port J */ -#define PORTJ_DIR _SFR_MEM8(0x0700) -#define PORTJ_DIRSET _SFR_MEM8(0x0701) -#define PORTJ_DIRCLR _SFR_MEM8(0x0702) -#define PORTJ_DIRTGL _SFR_MEM8(0x0703) -#define PORTJ_OUT _SFR_MEM8(0x0704) -#define PORTJ_OUTSET _SFR_MEM8(0x0705) -#define PORTJ_OUTCLR _SFR_MEM8(0x0706) -#define PORTJ_OUTTGL _SFR_MEM8(0x0707) -#define PORTJ_IN _SFR_MEM8(0x0708) -#define PORTJ_INTCTRL _SFR_MEM8(0x0709) -#define PORTJ_INT0MASK _SFR_MEM8(0x070A) -#define PORTJ_INT1MASK _SFR_MEM8(0x070B) -#define PORTJ_INTFLAGS _SFR_MEM8(0x070C) -#define PORTJ_PIN0CTRL _SFR_MEM8(0x0710) -#define PORTJ_PIN1CTRL _SFR_MEM8(0x0711) -#define PORTJ_PIN2CTRL _SFR_MEM8(0x0712) -#define PORTJ_PIN3CTRL _SFR_MEM8(0x0713) -#define PORTJ_PIN4CTRL _SFR_MEM8(0x0714) -#define PORTJ_PIN5CTRL _SFR_MEM8(0x0715) -#define PORTJ_PIN6CTRL _SFR_MEM8(0x0716) -#define PORTJ_PIN7CTRL _SFR_MEM8(0x0717) - -/* PORTK - Port K */ -#define PORTK_DIR _SFR_MEM8(0x0720) -#define PORTK_DIRSET _SFR_MEM8(0x0721) -#define PORTK_DIRCLR _SFR_MEM8(0x0722) -#define PORTK_DIRTGL _SFR_MEM8(0x0723) -#define PORTK_OUT _SFR_MEM8(0x0724) -#define PORTK_OUTSET _SFR_MEM8(0x0725) -#define PORTK_OUTCLR _SFR_MEM8(0x0726) -#define PORTK_OUTTGL _SFR_MEM8(0x0727) -#define PORTK_IN _SFR_MEM8(0x0728) -#define PORTK_INTCTRL _SFR_MEM8(0x0729) -#define PORTK_INT0MASK _SFR_MEM8(0x072A) -#define PORTK_INT1MASK _SFR_MEM8(0x072B) -#define PORTK_INTFLAGS _SFR_MEM8(0x072C) -#define PORTK_PIN0CTRL _SFR_MEM8(0x0730) -#define PORTK_PIN1CTRL _SFR_MEM8(0x0731) -#define PORTK_PIN2CTRL _SFR_MEM8(0x0732) -#define PORTK_PIN3CTRL _SFR_MEM8(0x0733) -#define PORTK_PIN4CTRL _SFR_MEM8(0x0734) -#define PORTK_PIN5CTRL _SFR_MEM8(0x0735) -#define PORTK_PIN6CTRL _SFR_MEM8(0x0736) -#define PORTK_PIN7CTRL _SFR_MEM8(0x0737) - -/* PORTQ - Port Q */ -#define PORTQ_DIR _SFR_MEM8(0x07C0) -#define PORTQ_DIRSET _SFR_MEM8(0x07C1) -#define PORTQ_DIRCLR _SFR_MEM8(0x07C2) -#define PORTQ_DIRTGL _SFR_MEM8(0x07C3) -#define PORTQ_OUT _SFR_MEM8(0x07C4) -#define PORTQ_OUTSET _SFR_MEM8(0x07C5) -#define PORTQ_OUTCLR _SFR_MEM8(0x07C6) -#define PORTQ_OUTTGL _SFR_MEM8(0x07C7) -#define PORTQ_IN _SFR_MEM8(0x07C8) -#define PORTQ_INTCTRL _SFR_MEM8(0x07C9) -#define PORTQ_INT0MASK _SFR_MEM8(0x07CA) -#define PORTQ_INT1MASK _SFR_MEM8(0x07CB) -#define PORTQ_INTFLAGS _SFR_MEM8(0x07CC) -#define PORTQ_PIN0CTRL _SFR_MEM8(0x07D0) -#define PORTQ_PIN1CTRL _SFR_MEM8(0x07D1) -#define PORTQ_PIN2CTRL _SFR_MEM8(0x07D2) -#define PORTQ_PIN3CTRL _SFR_MEM8(0x07D3) -#define PORTQ_PIN4CTRL _SFR_MEM8(0x07D4) -#define PORTQ_PIN5CTRL _SFR_MEM8(0x07D5) -#define PORTQ_PIN6CTRL _SFR_MEM8(0x07D6) -#define PORTQ_PIN7CTRL _SFR_MEM8(0x07D7) - -/* PORTR - Port R */ -#define PORTR_DIR _SFR_MEM8(0x07E0) -#define PORTR_DIRSET _SFR_MEM8(0x07E1) -#define PORTR_DIRCLR _SFR_MEM8(0x07E2) -#define PORTR_DIRTGL _SFR_MEM8(0x07E3) -#define PORTR_OUT _SFR_MEM8(0x07E4) -#define PORTR_OUTSET _SFR_MEM8(0x07E5) -#define PORTR_OUTCLR _SFR_MEM8(0x07E6) -#define PORTR_OUTTGL _SFR_MEM8(0x07E7) -#define PORTR_IN _SFR_MEM8(0x07E8) -#define PORTR_INTCTRL _SFR_MEM8(0x07E9) -#define PORTR_INT0MASK _SFR_MEM8(0x07EA) -#define PORTR_INT1MASK _SFR_MEM8(0x07EB) -#define PORTR_INTFLAGS _SFR_MEM8(0x07EC) -#define PORTR_PIN0CTRL _SFR_MEM8(0x07F0) -#define PORTR_PIN1CTRL _SFR_MEM8(0x07F1) -#define PORTR_PIN2CTRL _SFR_MEM8(0x07F2) -#define PORTR_PIN3CTRL _SFR_MEM8(0x07F3) -#define PORTR_PIN4CTRL _SFR_MEM8(0x07F4) -#define PORTR_PIN5CTRL _SFR_MEM8(0x07F5) -#define PORTR_PIN6CTRL _SFR_MEM8(0x07F6) -#define PORTR_PIN7CTRL _SFR_MEM8(0x07F7) - -/* TCC0 - Timer/Counter C0 */ -#define TCC0_CTRLA _SFR_MEM8(0x0800) -#define TCC0_CTRLB _SFR_MEM8(0x0801) -#define TCC0_CTRLC _SFR_MEM8(0x0802) -#define TCC0_CTRLD _SFR_MEM8(0x0803) -#define TCC0_CTRLE _SFR_MEM8(0x0804) -#define TCC0_INTCTRLA _SFR_MEM8(0x0806) -#define TCC0_INTCTRLB _SFR_MEM8(0x0807) -#define TCC0_CTRLFCLR _SFR_MEM8(0x0808) -#define TCC0_CTRLFSET _SFR_MEM8(0x0809) -#define TCC0_CTRLGCLR _SFR_MEM8(0x080A) -#define TCC0_CTRLGSET _SFR_MEM8(0x080B) -#define TCC0_INTFLAGS _SFR_MEM8(0x080C) -#define TCC0_TEMP _SFR_MEM8(0x080F) -#define TCC0_CNT _SFR_MEM16(0x0820) -#define TCC0_PER _SFR_MEM16(0x0826) -#define TCC0_CCA _SFR_MEM16(0x0828) -#define TCC0_CCB _SFR_MEM16(0x082A) -#define TCC0_CCC _SFR_MEM16(0x082C) -#define TCC0_CCD _SFR_MEM16(0x082E) -#define TCC0_PERBUF _SFR_MEM16(0x0836) -#define TCC0_CCABUF _SFR_MEM16(0x0838) -#define TCC0_CCBBUF _SFR_MEM16(0x083A) -#define TCC0_CCCBUF _SFR_MEM16(0x083C) -#define TCC0_CCDBUF _SFR_MEM16(0x083E) - -/* TCC1 - Timer/Counter C1 */ -#define TCC1_CTRLA _SFR_MEM8(0x0840) -#define TCC1_CTRLB _SFR_MEM8(0x0841) -#define TCC1_CTRLC _SFR_MEM8(0x0842) -#define TCC1_CTRLD _SFR_MEM8(0x0843) -#define TCC1_CTRLE _SFR_MEM8(0x0844) -#define TCC1_INTCTRLA _SFR_MEM8(0x0846) -#define TCC1_INTCTRLB _SFR_MEM8(0x0847) -#define TCC1_CTRLFCLR _SFR_MEM8(0x0848) -#define TCC1_CTRLFSET _SFR_MEM8(0x0849) -#define TCC1_CTRLGCLR _SFR_MEM8(0x084A) -#define TCC1_CTRLGSET _SFR_MEM8(0x084B) -#define TCC1_INTFLAGS _SFR_MEM8(0x084C) -#define TCC1_TEMP _SFR_MEM8(0x084F) -#define TCC1_CNT _SFR_MEM16(0x0860) -#define TCC1_PER _SFR_MEM16(0x0866) -#define TCC1_CCA _SFR_MEM16(0x0868) -#define TCC1_CCB _SFR_MEM16(0x086A) -#define TCC1_PERBUF _SFR_MEM16(0x0876) -#define TCC1_CCABUF _SFR_MEM16(0x0878) -#define TCC1_CCBBUF _SFR_MEM16(0x087A) - -/* AWEXC - Advanced Waveform Extension C */ -#define AWEXC_CTRL _SFR_MEM8(0x0880) -#define AWEXC_FDEMASK _SFR_MEM8(0x0882) -#define AWEXC_FDCTRL _SFR_MEM8(0x0883) -#define AWEXC_STATUS _SFR_MEM8(0x0884) -#define AWEXC_DTBOTH _SFR_MEM8(0x0886) -#define AWEXC_DTBOTHBUF _SFR_MEM8(0x0887) -#define AWEXC_DTLS _SFR_MEM8(0x0888) -#define AWEXC_DTHS _SFR_MEM8(0x0889) -#define AWEXC_DTLSBUF _SFR_MEM8(0x088A) -#define AWEXC_DTHSBUF _SFR_MEM8(0x088B) -#define AWEXC_OUTOVEN _SFR_MEM8(0x088C) - -/* HIRESC - High-Resolution Extension C */ -#define HIRESC_CTRLA _SFR_MEM8(0x0890) - -/* USARTC0 - Universal Asynchronous Receiver-Transmitter C0 */ -#define USARTC0_DATA _SFR_MEM8(0x08A0) -#define USARTC0_STATUS _SFR_MEM8(0x08A1) -#define USARTC0_CTRLA _SFR_MEM8(0x08A3) -#define USARTC0_CTRLB _SFR_MEM8(0x08A4) -#define USARTC0_CTRLC _SFR_MEM8(0x08A5) -#define USARTC0_BAUDCTRLA _SFR_MEM8(0x08A6) -#define USARTC0_BAUDCTRLB _SFR_MEM8(0x08A7) - -/* USARTC1 - Universal Asynchronous Receiver-Transmitter C1 */ -#define USARTC1_DATA _SFR_MEM8(0x08B0) -#define USARTC1_STATUS _SFR_MEM8(0x08B1) -#define USARTC1_CTRLA _SFR_MEM8(0x08B3) -#define USARTC1_CTRLB _SFR_MEM8(0x08B4) -#define USARTC1_CTRLC _SFR_MEM8(0x08B5) -#define USARTC1_BAUDCTRLA _SFR_MEM8(0x08B6) -#define USARTC1_BAUDCTRLB _SFR_MEM8(0x08B7) - -/* SPIC - Serial Peripheral Interface C */ -#define SPIC_CTRL _SFR_MEM8(0x08C0) -#define SPIC_INTCTRL _SFR_MEM8(0x08C1) -#define SPIC_STATUS _SFR_MEM8(0x08C2) -#define SPIC_DATA _SFR_MEM8(0x08C3) - -/* IRCOM - IR Communication Module */ -#define IRCOM_CTRL _SFR_MEM8(0x08F8) -#define IRCOM_TXPLCTRL _SFR_MEM8(0x08F9) -#define IRCOM_RXPLCTRL _SFR_MEM8(0x08FA) - -/* TCD0 - Timer/Counter D0 */ -#define TCD0_CTRLA _SFR_MEM8(0x0900) -#define TCD0_CTRLB _SFR_MEM8(0x0901) -#define TCD0_CTRLC _SFR_MEM8(0x0902) -#define TCD0_CTRLD _SFR_MEM8(0x0903) -#define TCD0_CTRLE _SFR_MEM8(0x0904) -#define TCD0_INTCTRLA _SFR_MEM8(0x0906) -#define TCD0_INTCTRLB _SFR_MEM8(0x0907) -#define TCD0_CTRLFCLR _SFR_MEM8(0x0908) -#define TCD0_CTRLFSET _SFR_MEM8(0x0909) -#define TCD0_CTRLGCLR _SFR_MEM8(0x090A) -#define TCD0_CTRLGSET _SFR_MEM8(0x090B) -#define TCD0_INTFLAGS _SFR_MEM8(0x090C) -#define TCD0_TEMP _SFR_MEM8(0x090F) -#define TCD0_CNT _SFR_MEM16(0x0920) -#define TCD0_PER _SFR_MEM16(0x0926) -#define TCD0_CCA _SFR_MEM16(0x0928) -#define TCD0_CCB _SFR_MEM16(0x092A) -#define TCD0_CCC _SFR_MEM16(0x092C) -#define TCD0_CCD _SFR_MEM16(0x092E) -#define TCD0_PERBUF _SFR_MEM16(0x0936) -#define TCD0_CCABUF _SFR_MEM16(0x0938) -#define TCD0_CCBBUF _SFR_MEM16(0x093A) -#define TCD0_CCCBUF _SFR_MEM16(0x093C) -#define TCD0_CCDBUF _SFR_MEM16(0x093E) - -/* TCD1 - Timer/Counter D1 */ -#define TCD1_CTRLA _SFR_MEM8(0x0940) -#define TCD1_CTRLB _SFR_MEM8(0x0941) -#define TCD1_CTRLC _SFR_MEM8(0x0942) -#define TCD1_CTRLD _SFR_MEM8(0x0943) -#define TCD1_CTRLE _SFR_MEM8(0x0944) -#define TCD1_INTCTRLA _SFR_MEM8(0x0946) -#define TCD1_INTCTRLB _SFR_MEM8(0x0947) -#define TCD1_CTRLFCLR _SFR_MEM8(0x0948) -#define TCD1_CTRLFSET _SFR_MEM8(0x0949) -#define TCD1_CTRLGCLR _SFR_MEM8(0x094A) -#define TCD1_CTRLGSET _SFR_MEM8(0x094B) -#define TCD1_INTFLAGS _SFR_MEM8(0x094C) -#define TCD1_TEMP _SFR_MEM8(0x094F) -#define TCD1_CNT _SFR_MEM16(0x0960) -#define TCD1_PER _SFR_MEM16(0x0966) -#define TCD1_CCA _SFR_MEM16(0x0968) -#define TCD1_CCB _SFR_MEM16(0x096A) -#define TCD1_PERBUF _SFR_MEM16(0x0976) -#define TCD1_CCABUF _SFR_MEM16(0x0978) -#define TCD1_CCBBUF _SFR_MEM16(0x097A) - -/* HIRESD - High-Resolution Extension D */ -#define HIRESD_CTRLA _SFR_MEM8(0x0990) - -/* USARTD0 - Universal Asynchronous Receiver-Transmitter D0 */ -#define USARTD0_DATA _SFR_MEM8(0x09A0) -#define USARTD0_STATUS _SFR_MEM8(0x09A1) -#define USARTD0_CTRLA _SFR_MEM8(0x09A3) -#define USARTD0_CTRLB _SFR_MEM8(0x09A4) -#define USARTD0_CTRLC _SFR_MEM8(0x09A5) -#define USARTD0_BAUDCTRLA _SFR_MEM8(0x09A6) -#define USARTD0_BAUDCTRLB _SFR_MEM8(0x09A7) - -/* USARTD1 - Universal Asynchronous Receiver-Transmitter D1 */ -#define USARTD1_DATA _SFR_MEM8(0x09B0) -#define USARTD1_STATUS _SFR_MEM8(0x09B1) -#define USARTD1_CTRLA _SFR_MEM8(0x09B3) -#define USARTD1_CTRLB _SFR_MEM8(0x09B4) -#define USARTD1_CTRLC _SFR_MEM8(0x09B5) -#define USARTD1_BAUDCTRLA _SFR_MEM8(0x09B6) -#define USARTD1_BAUDCTRLB _SFR_MEM8(0x09B7) - -/* SPID - Serial Peripheral Interface D */ -#define SPID_CTRL _SFR_MEM8(0x09C0) -#define SPID_INTCTRL _SFR_MEM8(0x09C1) -#define SPID_STATUS _SFR_MEM8(0x09C2) -#define SPID_DATA _SFR_MEM8(0x09C3) - -/* TCE0 - Timer/Counter E0 */ -#define TCE0_CTRLA _SFR_MEM8(0x0A00) -#define TCE0_CTRLB _SFR_MEM8(0x0A01) -#define TCE0_CTRLC _SFR_MEM8(0x0A02) -#define TCE0_CTRLD _SFR_MEM8(0x0A03) -#define TCE0_CTRLE _SFR_MEM8(0x0A04) -#define TCE0_INTCTRLA _SFR_MEM8(0x0A06) -#define TCE0_INTCTRLB _SFR_MEM8(0x0A07) -#define TCE0_CTRLFCLR _SFR_MEM8(0x0A08) -#define TCE0_CTRLFSET _SFR_MEM8(0x0A09) -#define TCE0_CTRLGCLR _SFR_MEM8(0x0A0A) -#define TCE0_CTRLGSET _SFR_MEM8(0x0A0B) -#define TCE0_INTFLAGS _SFR_MEM8(0x0A0C) -#define TCE0_TEMP _SFR_MEM8(0x0A0F) -#define TCE0_CNT _SFR_MEM16(0x0A20) -#define TCE0_PER _SFR_MEM16(0x0A26) -#define TCE0_CCA _SFR_MEM16(0x0A28) -#define TCE0_CCB _SFR_MEM16(0x0A2A) -#define TCE0_CCC _SFR_MEM16(0x0A2C) -#define TCE0_CCD _SFR_MEM16(0x0A2E) -#define TCE0_PERBUF _SFR_MEM16(0x0A36) -#define TCE0_CCABUF _SFR_MEM16(0x0A38) -#define TCE0_CCBBUF _SFR_MEM16(0x0A3A) -#define TCE0_CCCBUF _SFR_MEM16(0x0A3C) -#define TCE0_CCDBUF _SFR_MEM16(0x0A3E) - -/* TCE1 - Timer/Counter E1 */ -#define TCE1_CTRLA _SFR_MEM8(0x0A40) -#define TCE1_CTRLB _SFR_MEM8(0x0A41) -#define TCE1_CTRLC _SFR_MEM8(0x0A42) -#define TCE1_CTRLD _SFR_MEM8(0x0A43) -#define TCE1_CTRLE _SFR_MEM8(0x0A44) -#define TCE1_INTCTRLA _SFR_MEM8(0x0A46) -#define TCE1_INTCTRLB _SFR_MEM8(0x0A47) -#define TCE1_CTRLFCLR _SFR_MEM8(0x0A48) -#define TCE1_CTRLFSET _SFR_MEM8(0x0A49) -#define TCE1_CTRLGCLR _SFR_MEM8(0x0A4A) -#define TCE1_CTRLGSET _SFR_MEM8(0x0A4B) -#define TCE1_INTFLAGS _SFR_MEM8(0x0A4C) -#define TCE1_TEMP _SFR_MEM8(0x0A4F) -#define TCE1_CNT _SFR_MEM16(0x0A60) -#define TCE1_PER _SFR_MEM16(0x0A66) -#define TCE1_CCA _SFR_MEM16(0x0A68) -#define TCE1_CCB _SFR_MEM16(0x0A6A) -#define TCE1_PERBUF _SFR_MEM16(0x0A76) -#define TCE1_CCABUF _SFR_MEM16(0x0A78) -#define TCE1_CCBBUF _SFR_MEM16(0x0A7A) - -/* AWEXE - Advanced Waveform Extension E */ -#define AWEXE_CTRL _SFR_MEM8(0x0A80) -#define AWEXE_FDEMASK _SFR_MEM8(0x0A82) -#define AWEXE_FDCTRL _SFR_MEM8(0x0A83) -#define AWEXE_STATUS _SFR_MEM8(0x0A84) -#define AWEXE_DTBOTH _SFR_MEM8(0x0A86) -#define AWEXE_DTBOTHBUF _SFR_MEM8(0x0A87) -#define AWEXE_DTLS _SFR_MEM8(0x0A88) -#define AWEXE_DTHS _SFR_MEM8(0x0A89) -#define AWEXE_DTLSBUF _SFR_MEM8(0x0A8A) -#define AWEXE_DTHSBUF _SFR_MEM8(0x0A8B) -#define AWEXE_OUTOVEN _SFR_MEM8(0x0A8C) - -/* HIRESE - High-Resolution Extension E */ -#define HIRESE_CTRLA _SFR_MEM8(0x0A90) - -/* USARTE0 - Universal Asynchronous Receiver-Transmitter E0 */ -#define USARTE0_DATA _SFR_MEM8(0x0AA0) -#define USARTE0_STATUS _SFR_MEM8(0x0AA1) -#define USARTE0_CTRLA _SFR_MEM8(0x0AA3) -#define USARTE0_CTRLB _SFR_MEM8(0x0AA4) -#define USARTE0_CTRLC _SFR_MEM8(0x0AA5) -#define USARTE0_BAUDCTRLA _SFR_MEM8(0x0AA6) -#define USARTE0_BAUDCTRLB _SFR_MEM8(0x0AA7) - -/* USARTE1 - Universal Asynchronous Receiver-Transmitter E1 */ -#define USARTE1_DATA _SFR_MEM8(0x0AB0) -#define USARTE1_STATUS _SFR_MEM8(0x0AB1) -#define USARTE1_CTRLA _SFR_MEM8(0x0AB3) -#define USARTE1_CTRLB _SFR_MEM8(0x0AB4) -#define USARTE1_CTRLC _SFR_MEM8(0x0AB5) -#define USARTE1_BAUDCTRLA _SFR_MEM8(0x0AB6) -#define USARTE1_BAUDCTRLB _SFR_MEM8(0x0AB7) - -/* SPIE - Serial Peripheral Interface E */ -#define SPIE_CTRL _SFR_MEM8(0x0AC0) -#define SPIE_INTCTRL _SFR_MEM8(0x0AC1) -#define SPIE_STATUS _SFR_MEM8(0x0AC2) -#define SPIE_DATA _SFR_MEM8(0x0AC3) - -/* TCF0 - Timer/Counter F0 */ -#define TCF0_CTRLA _SFR_MEM8(0x0B00) -#define TCF0_CTRLB _SFR_MEM8(0x0B01) -#define TCF0_CTRLC _SFR_MEM8(0x0B02) -#define TCF0_CTRLD _SFR_MEM8(0x0B03) -#define TCF0_CTRLE _SFR_MEM8(0x0B04) -#define TCF0_INTCTRLA _SFR_MEM8(0x0B06) -#define TCF0_INTCTRLB _SFR_MEM8(0x0B07) -#define TCF0_CTRLFCLR _SFR_MEM8(0x0B08) -#define TCF0_CTRLFSET _SFR_MEM8(0x0B09) -#define TCF0_CTRLGCLR _SFR_MEM8(0x0B0A) -#define TCF0_CTRLGSET _SFR_MEM8(0x0B0B) -#define TCF0_INTFLAGS _SFR_MEM8(0x0B0C) -#define TCF0_TEMP _SFR_MEM8(0x0B0F) -#define TCF0_CNT _SFR_MEM16(0x0B20) -#define TCF0_PER _SFR_MEM16(0x0B26) -#define TCF0_CCA _SFR_MEM16(0x0B28) -#define TCF0_CCB _SFR_MEM16(0x0B2A) -#define TCF0_CCC _SFR_MEM16(0x0B2C) -#define TCF0_CCD _SFR_MEM16(0x0B2E) -#define TCF0_PERBUF _SFR_MEM16(0x0B36) -#define TCF0_CCABUF _SFR_MEM16(0x0B38) -#define TCF0_CCBBUF _SFR_MEM16(0x0B3A) -#define TCF0_CCCBUF _SFR_MEM16(0x0B3C) -#define TCF0_CCDBUF _SFR_MEM16(0x0B3E) - -/* TCF1 - Timer/Counter F1 */ -#define TCF1_CTRLA _SFR_MEM8(0x0B40) -#define TCF1_CTRLB _SFR_MEM8(0x0B41) -#define TCF1_CTRLC _SFR_MEM8(0x0B42) -#define TCF1_CTRLD _SFR_MEM8(0x0B43) -#define TCF1_CTRLE _SFR_MEM8(0x0B44) -#define TCF1_INTCTRLA _SFR_MEM8(0x0B46) -#define TCF1_INTCTRLB _SFR_MEM8(0x0B47) -#define TCF1_CTRLFCLR _SFR_MEM8(0x0B48) -#define TCF1_CTRLFSET _SFR_MEM8(0x0B49) -#define TCF1_CTRLGCLR _SFR_MEM8(0x0B4A) -#define TCF1_CTRLGSET _SFR_MEM8(0x0B4B) -#define TCF1_INTFLAGS _SFR_MEM8(0x0B4C) -#define TCF1_TEMP _SFR_MEM8(0x0B4F) -#define TCF1_CNT _SFR_MEM16(0x0B60) -#define TCF1_PER _SFR_MEM16(0x0B66) -#define TCF1_CCA _SFR_MEM16(0x0B68) -#define TCF1_CCB _SFR_MEM16(0x0B6A) -#define TCF1_PERBUF _SFR_MEM16(0x0B76) -#define TCF1_CCABUF _SFR_MEM16(0x0B78) -#define TCF1_CCBBUF _SFR_MEM16(0x0B7A) - -/* HIRESF - High-Resolution Extension F */ -#define HIRESF_CTRLA _SFR_MEM8(0x0B90) - -/* USARTF0 - Universal Asynchronous Receiver-Transmitter F0 */ -#define USARTF0_DATA _SFR_MEM8(0x0BA0) -#define USARTF0_STATUS _SFR_MEM8(0x0BA1) -#define USARTF0_CTRLA _SFR_MEM8(0x0BA3) -#define USARTF0_CTRLB _SFR_MEM8(0x0BA4) -#define USARTF0_CTRLC _SFR_MEM8(0x0BA5) -#define USARTF0_BAUDCTRLA _SFR_MEM8(0x0BA6) -#define USARTF0_BAUDCTRLB _SFR_MEM8(0x0BA7) - -/* USARTF1 - Universal Asynchronous Receiver-Transmitter F1 */ -#define USARTF1_DATA _SFR_MEM8(0x0BB0) -#define USARTF1_STATUS _SFR_MEM8(0x0BB1) -#define USARTF1_CTRLA _SFR_MEM8(0x0BB3) -#define USARTF1_CTRLB _SFR_MEM8(0x0BB4) -#define USARTF1_CTRLC _SFR_MEM8(0x0BB5) -#define USARTF1_BAUDCTRLA _SFR_MEM8(0x0BB6) -#define USARTF1_BAUDCTRLB _SFR_MEM8(0x0BB7) - -/* SPIF - Serial Peripheral Interface F */ -#define SPIF_CTRL _SFR_MEM8(0x0BC0) -#define SPIF_INTCTRL _SFR_MEM8(0x0BC1) -#define SPIF_STATUS _SFR_MEM8(0x0BC2) -#define SPIF_DATA _SFR_MEM8(0x0BC3) - - - -/*================== Bitfield Definitions ================== */ - -/* XOCD - On-Chip Debug System */ -/* OCD.OCDR1 bit masks and bit positions */ -#define OCD_OCDRD_bm 0x01 /* OCDR Dirty bit mask. */ -#define OCD_OCDRD_bp 0 /* OCDR Dirty bit position. */ - - -/* CPU - CPU */ -/* CPU.CCP bit masks and bit positions */ -#define CPU_CCP_gm 0xFF /* CCP signature group mask. */ -#define CPU_CCP_gp 0 /* CCP signature group position. */ -#define CPU_CCP0_bm (1<<0) /* CCP signature bit 0 mask. */ -#define CPU_CCP0_bp 0 /* CCP signature bit 0 position. */ -#define CPU_CCP1_bm (1<<1) /* CCP signature bit 1 mask. */ -#define CPU_CCP1_bp 1 /* CCP signature bit 1 position. */ -#define CPU_CCP2_bm (1<<2) /* CCP signature bit 2 mask. */ -#define CPU_CCP2_bp 2 /* CCP signature bit 2 position. */ -#define CPU_CCP3_bm (1<<3) /* CCP signature bit 3 mask. */ -#define CPU_CCP3_bp 3 /* CCP signature bit 3 position. */ -#define CPU_CCP4_bm (1<<4) /* CCP signature bit 4 mask. */ -#define CPU_CCP4_bp 4 /* CCP signature bit 4 position. */ -#define CPU_CCP5_bm (1<<5) /* CCP signature bit 5 mask. */ -#define CPU_CCP5_bp 5 /* CCP signature bit 5 position. */ -#define CPU_CCP6_bm (1<<6) /* CCP signature bit 6 mask. */ -#define CPU_CCP6_bp 6 /* CCP signature bit 6 position. */ -#define CPU_CCP7_bm (1<<7) /* CCP signature bit 7 mask. */ -#define CPU_CCP7_bp 7 /* CCP signature bit 7 position. */ - - -/* CPU.SREG bit masks and bit positions */ -#define CPU_I_bm 0x80 /* Global Interrupt Enable Flag bit mask. */ -#define CPU_I_bp 7 /* Global Interrupt Enable Flag bit position. */ - -#define CPU_T_bm 0x40 /* Transfer Bit bit mask. */ -#define CPU_T_bp 6 /* Transfer Bit bit position. */ - -#define CPU_H_bm 0x20 /* Half Carry Flag bit mask. */ -#define CPU_H_bp 5 /* Half Carry Flag bit position. */ - -#define CPU_S_bm 0x10 /* N Exclusive Or V Flag bit mask. */ -#define CPU_S_bp 4 /* N Exclusive Or V Flag bit position. */ - -#define CPU_V_bm 0x08 /* Two's Complement Overflow Flag bit mask. */ -#define CPU_V_bp 3 /* Two's Complement Overflow Flag bit position. */ - -#define CPU_N_bm 0x04 /* Negative Flag bit mask. */ -#define CPU_N_bp 2 /* Negative Flag bit position. */ - -#define CPU_Z_bm 0x02 /* Zero Flag bit mask. */ -#define CPU_Z_bp 1 /* Zero Flag bit position. */ - -#define CPU_C_bm 0x01 /* Carry Flag bit mask. */ -#define CPU_C_bp 0 /* Carry Flag bit position. */ - - -/* CLK - Clock System */ -/* CLK.CTRL bit masks and bit positions */ -#define CLK_SCLKSEL_gm 0x07 /* System Clock Selection group mask. */ -#define CLK_SCLKSEL_gp 0 /* System Clock Selection group position. */ -#define CLK_SCLKSEL0_bm (1<<0) /* System Clock Selection bit 0 mask. */ -#define CLK_SCLKSEL0_bp 0 /* System Clock Selection bit 0 position. */ -#define CLK_SCLKSEL1_bm (1<<1) /* System Clock Selection bit 1 mask. */ -#define CLK_SCLKSEL1_bp 1 /* System Clock Selection bit 1 position. */ -#define CLK_SCLKSEL2_bm (1<<2) /* System Clock Selection bit 2 mask. */ -#define CLK_SCLKSEL2_bp 2 /* System Clock Selection bit 2 position. */ - - -/* CLK.PSCTRL bit masks and bit positions */ -#define CLK_PSADIV_gm 0x7C /* Prescaler A Division Factor group mask. */ -#define CLK_PSADIV_gp 2 /* Prescaler A Division Factor group position. */ -#define CLK_PSADIV0_bm (1<<2) /* Prescaler A Division Factor bit 0 mask. */ -#define CLK_PSADIV0_bp 2 /* Prescaler A Division Factor bit 0 position. */ -#define CLK_PSADIV1_bm (1<<3) /* Prescaler A Division Factor bit 1 mask. */ -#define CLK_PSADIV1_bp 3 /* Prescaler A Division Factor bit 1 position. */ -#define CLK_PSADIV2_bm (1<<4) /* Prescaler A Division Factor bit 2 mask. */ -#define CLK_PSADIV2_bp 4 /* Prescaler A Division Factor bit 2 position. */ -#define CLK_PSADIV3_bm (1<<5) /* Prescaler A Division Factor bit 3 mask. */ -#define CLK_PSADIV3_bp 5 /* Prescaler A Division Factor bit 3 position. */ -#define CLK_PSADIV4_bm (1<<6) /* Prescaler A Division Factor bit 4 mask. */ -#define CLK_PSADIV4_bp 6 /* Prescaler A Division Factor bit 4 position. */ - -#define CLK_PSBCDIV_gm 0x03 /* Prescaler B and C Division factor group mask. */ -#define CLK_PSBCDIV_gp 0 /* Prescaler B and C Division factor group position. */ -#define CLK_PSBCDIV0_bm (1<<0) /* Prescaler B and C Division factor bit 0 mask. */ -#define CLK_PSBCDIV0_bp 0 /* Prescaler B and C Division factor bit 0 position. */ -#define CLK_PSBCDIV1_bm (1<<1) /* Prescaler B and C Division factor bit 1 mask. */ -#define CLK_PSBCDIV1_bp 1 /* Prescaler B and C Division factor bit 1 position. */ - - -/* CLK.LOCK bit masks and bit positions */ -#define CLK_LOCK_bm 0x01 /* Clock System Lock bit mask. */ -#define CLK_LOCK_bp 0 /* Clock System Lock bit position. */ - - -/* CLK.RTCCTRL bit masks and bit positions */ -#define CLK_RTCSRC_gm 0x0E /* Clock Source group mask. */ -#define CLK_RTCSRC_gp 1 /* Clock Source group position. */ -#define CLK_RTCSRC0_bm (1<<1) /* Clock Source bit 0 mask. */ -#define CLK_RTCSRC0_bp 1 /* Clock Source bit 0 position. */ -#define CLK_RTCSRC1_bm (1<<2) /* Clock Source bit 1 mask. */ -#define CLK_RTCSRC1_bp 2 /* Clock Source bit 1 position. */ -#define CLK_RTCSRC2_bm (1<<3) /* Clock Source bit 2 mask. */ -#define CLK_RTCSRC2_bp 3 /* Clock Source bit 2 position. */ - -#define CLK_RTCEN_bm 0x01 /* RTC Clock Source Enable bit mask. */ -#define CLK_RTCEN_bp 0 /* RTC Clock Source Enable bit position. */ - - -/* PR.PRGEN bit masks and bit positions */ -#define PR_AES_bm 0x10 /* AES bit mask. */ -#define PR_AES_bp 4 /* AES bit position. */ - -#define PR_EBI_bm 0x08 /* External Bus Interface bit mask. */ -#define PR_EBI_bp 3 /* External Bus Interface bit position. */ - -#define PR_RTC_bm 0x04 /* Real-time Counter bit mask. */ -#define PR_RTC_bp 2 /* Real-time Counter bit position. */ - -#define PR_EVSYS_bm 0x02 /* Event System bit mask. */ -#define PR_EVSYS_bp 1 /* Event System bit position. */ - -#define PR_DMA_bm 0x01 /* DMA-Controller bit mask. */ -#define PR_DMA_bp 0 /* DMA-Controller bit position. */ - - -/* PR.PRPA bit masks and bit positions */ -#define PR_DAC_bm 0x04 /* Port A DAC bit mask. */ -#define PR_DAC_bp 2 /* Port A DAC bit position. */ - -#define PR_ADC_bm 0x02 /* Port A ADC bit mask. */ -#define PR_ADC_bp 1 /* Port A ADC bit position. */ - -#define PR_AC_bm 0x01 /* Port A Analog Comparator bit mask. */ -#define PR_AC_bp 0 /* Port A Analog Comparator bit position. */ - - -/* PR.PRPB bit masks and bit positions */ -/* PR_DAC_bm Predefined. */ -/* PR_DAC_bp Predefined. */ - -/* PR_ADC_bm Predefined. */ -/* PR_ADC_bp Predefined. */ - -/* PR_AC_bm Predefined. */ -/* PR_AC_bp Predefined. */ - - -/* PR.PRPC bit masks and bit positions */ -#define PR_TWI_bm 0x40 /* Port C Two-wire Interface bit mask. */ -#define PR_TWI_bp 6 /* Port C Two-wire Interface bit position. */ - -#define PR_USART1_bm 0x20 /* Port C USART1 bit mask. */ -#define PR_USART1_bp 5 /* Port C USART1 bit position. */ - -#define PR_USART0_bm 0x10 /* Port C USART0 bit mask. */ -#define PR_USART0_bp 4 /* Port C USART0 bit position. */ - -#define PR_SPI_bm 0x08 /* Port C SPI bit mask. */ -#define PR_SPI_bp 3 /* Port C SPI bit position. */ - -#define PR_HIRES_bm 0x04 /* Port C AWEX bit mask. */ -#define PR_HIRES_bp 2 /* Port C AWEX bit position. */ - -#define PR_TC1_bm 0x02 /* Port C Timer/Counter1 bit mask. */ -#define PR_TC1_bp 1 /* Port C Timer/Counter1 bit position. */ - -#define PR_TC0_bm 0x01 /* Port C Timer/Counter0 bit mask. */ -#define PR_TC0_bp 0 /* Port C Timer/Counter0 bit position. */ - - -/* PR.PRPD bit masks and bit positions */ -/* PR_TWI_bm Predefined. */ -/* PR_TWI_bp Predefined. */ - -/* PR_USART1_bm Predefined. */ -/* PR_USART1_bp Predefined. */ - -/* PR_USART0_bm Predefined. */ -/* PR_USART0_bp Predefined. */ - -/* PR_SPI_bm Predefined. */ -/* PR_SPI_bp Predefined. */ - -/* PR_HIRES_bm Predefined. */ -/* PR_HIRES_bp Predefined. */ - -/* PR_TC1_bm Predefined. */ -/* PR_TC1_bp Predefined. */ - -/* PR_TC0_bm Predefined. */ -/* PR_TC0_bp Predefined. */ - - -/* PR.PRPE bit masks and bit positions */ -/* PR_TWI_bm Predefined. */ -/* PR_TWI_bp Predefined. */ - -/* PR_USART1_bm Predefined. */ -/* PR_USART1_bp Predefined. */ - -/* PR_USART0_bm Predefined. */ -/* PR_USART0_bp Predefined. */ - -/* PR_SPI_bm Predefined. */ -/* PR_SPI_bp Predefined. */ - -/* PR_HIRES_bm Predefined. */ -/* PR_HIRES_bp Predefined. */ - -/* PR_TC1_bm Predefined. */ -/* PR_TC1_bp Predefined. */ - -/* PR_TC0_bm Predefined. */ -/* PR_TC0_bp Predefined. */ - - -/* PR.PRPF bit masks and bit positions */ -/* PR_TWI_bm Predefined. */ -/* PR_TWI_bp Predefined. */ - -/* PR_USART1_bm Predefined. */ -/* PR_USART1_bp Predefined. */ - -/* PR_USART0_bm Predefined. */ -/* PR_USART0_bp Predefined. */ - -/* PR_SPI_bm Predefined. */ -/* PR_SPI_bp Predefined. */ - -/* PR_HIRES_bm Predefined. */ -/* PR_HIRES_bp Predefined. */ - -/* PR_TC1_bm Predefined. */ -/* PR_TC1_bp Predefined. */ - -/* PR_TC0_bm Predefined. */ -/* PR_TC0_bp Predefined. */ - - -/* SLEEP - Sleep Controller */ -/* SLEEP.CTRL bit masks and bit positions */ -#define SLEEP_SMODE_gm 0x0E /* Sleep Mode group mask. */ -#define SLEEP_SMODE_gp 1 /* Sleep Mode group position. */ -#define SLEEP_SMODE0_bm (1<<1) /* Sleep Mode bit 0 mask. */ -#define SLEEP_SMODE0_bp 1 /* Sleep Mode bit 0 position. */ -#define SLEEP_SMODE1_bm (1<<2) /* Sleep Mode bit 1 mask. */ -#define SLEEP_SMODE1_bp 2 /* Sleep Mode bit 1 position. */ -#define SLEEP_SMODE2_bm (1<<3) /* Sleep Mode bit 2 mask. */ -#define SLEEP_SMODE2_bp 3 /* Sleep Mode bit 2 position. */ - -#define SLEEP_SEN_bm 0x01 /* Sleep Enable bit mask. */ -#define SLEEP_SEN_bp 0 /* Sleep Enable bit position. */ - - -/* OSC - Oscillator */ -/* OSC.CTRL bit masks and bit positions */ -#define OSC_PLLEN_bm 0x10 /* PLL Enable bit mask. */ -#define OSC_PLLEN_bp 4 /* PLL Enable bit position. */ - -#define OSC_XOSCEN_bm 0x08 /* External Oscillator Enable bit mask. */ -#define OSC_XOSCEN_bp 3 /* External Oscillator Enable bit position. */ - -#define OSC_RC32KEN_bm 0x04 /* Internal 32kHz RC Oscillator Enable bit mask. */ -#define OSC_RC32KEN_bp 2 /* Internal 32kHz RC Oscillator Enable bit position. */ - -#define OSC_RC32MEN_bm 0x02 /* Internal 32MHz RC Oscillator Enable bit mask. */ -#define OSC_RC32MEN_bp 1 /* Internal 32MHz RC Oscillator Enable bit position. */ - -#define OSC_RC2MEN_bm 0x01 /* Internal 2MHz RC Oscillator Enable bit mask. */ -#define OSC_RC2MEN_bp 0 /* Internal 2MHz RC Oscillator Enable bit position. */ - - -/* OSC.STATUS bit masks and bit positions */ -#define OSC_PLLRDY_bm 0x10 /* PLL Ready bit mask. */ -#define OSC_PLLRDY_bp 4 /* PLL Ready bit position. */ - -#define OSC_XOSCRDY_bm 0x08 /* External Oscillator Ready bit mask. */ -#define OSC_XOSCRDY_bp 3 /* External Oscillator Ready bit position. */ - -#define OSC_RC32KRDY_bm 0x04 /* Internal 32kHz RC Oscillator Ready bit mask. */ -#define OSC_RC32KRDY_bp 2 /* Internal 32kHz RC Oscillator Ready bit position. */ - -#define OSC_RC32MRDY_bm 0x02 /* Internal 32MHz RC Oscillator Ready bit mask. */ -#define OSC_RC32MRDY_bp 1 /* Internal 32MHz RC Oscillator Ready bit position. */ - -#define OSC_RC2MRDY_bm 0x01 /* Internal 2MHz RC Oscillator Ready bit mask. */ -#define OSC_RC2MRDY_bp 0 /* Internal 2MHz RC Oscillator Ready bit position. */ - - -/* OSC.XOSCCTRL bit masks and bit positions */ -#define OSC_FRQRANGE_gm 0xC0 /* Frequency Range group mask. */ -#define OSC_FRQRANGE_gp 6 /* Frequency Range group position. */ -#define OSC_FRQRANGE0_bm (1<<6) /* Frequency Range bit 0 mask. */ -#define OSC_FRQRANGE0_bp 6 /* Frequency Range bit 0 position. */ -#define OSC_FRQRANGE1_bm (1<<7) /* Frequency Range bit 1 mask. */ -#define OSC_FRQRANGE1_bp 7 /* Frequency Range bit 1 position. */ - -#define OSC_X32KLPM_bm 0x20 /* 32kHz XTAL OSC Low-power Mode bit mask. */ -#define OSC_X32KLPM_bp 5 /* 32kHz XTAL OSC Low-power Mode bit position. */ - -#define OSC_XOSCSEL_gm 0x0F /* External Oscillator Selection and Startup Time group mask. */ -#define OSC_XOSCSEL_gp 0 /* External Oscillator Selection and Startup Time group position. */ -#define OSC_XOSCSEL0_bm (1<<0) /* External Oscillator Selection and Startup Time bit 0 mask. */ -#define OSC_XOSCSEL0_bp 0 /* External Oscillator Selection and Startup Time bit 0 position. */ -#define OSC_XOSCSEL1_bm (1<<1) /* External Oscillator Selection and Startup Time bit 1 mask. */ -#define OSC_XOSCSEL1_bp 1 /* External Oscillator Selection and Startup Time bit 1 position. */ -#define OSC_XOSCSEL2_bm (1<<2) /* External Oscillator Selection and Startup Time bit 2 mask. */ -#define OSC_XOSCSEL2_bp 2 /* External Oscillator Selection and Startup Time bit 2 position. */ -#define OSC_XOSCSEL3_bm (1<<3) /* External Oscillator Selection and Startup Time bit 3 mask. */ -#define OSC_XOSCSEL3_bp 3 /* External Oscillator Selection and Startup Time bit 3 position. */ - - -/* OSC.XOSCFAIL bit masks and bit positions */ -#define OSC_XOSCFDIF_bm 0x02 /* Failure Detection Interrupt Flag bit mask. */ -#define OSC_XOSCFDIF_bp 1 /* Failure Detection Interrupt Flag bit position. */ - -#define OSC_XOSCFDEN_bm 0x01 /* Failure Detection Enable bit mask. */ -#define OSC_XOSCFDEN_bp 0 /* Failure Detection Enable bit position. */ - - -/* OSC.PLLCTRL bit masks and bit positions */ -#define OSC_PLLSRC_gm 0xC0 /* Clock Source group mask. */ -#define OSC_PLLSRC_gp 6 /* Clock Source group position. */ -#define OSC_PLLSRC0_bm (1<<6) /* Clock Source bit 0 mask. */ -#define OSC_PLLSRC0_bp 6 /* Clock Source bit 0 position. */ -#define OSC_PLLSRC1_bm (1<<7) /* Clock Source bit 1 mask. */ -#define OSC_PLLSRC1_bp 7 /* Clock Source bit 1 position. */ - -#define OSC_PLLFAC_gm 0x1F /* Multiplication Factor group mask. */ -#define OSC_PLLFAC_gp 0 /* Multiplication Factor group position. */ -#define OSC_PLLFAC0_bm (1<<0) /* Multiplication Factor bit 0 mask. */ -#define OSC_PLLFAC0_bp 0 /* Multiplication Factor bit 0 position. */ -#define OSC_PLLFAC1_bm (1<<1) /* Multiplication Factor bit 1 mask. */ -#define OSC_PLLFAC1_bp 1 /* Multiplication Factor bit 1 position. */ -#define OSC_PLLFAC2_bm (1<<2) /* Multiplication Factor bit 2 mask. */ -#define OSC_PLLFAC2_bp 2 /* Multiplication Factor bit 2 position. */ -#define OSC_PLLFAC3_bm (1<<3) /* Multiplication Factor bit 3 mask. */ -#define OSC_PLLFAC3_bp 3 /* Multiplication Factor bit 3 position. */ -#define OSC_PLLFAC4_bm (1<<4) /* Multiplication Factor bit 4 mask. */ -#define OSC_PLLFAC4_bp 4 /* Multiplication Factor bit 4 position. */ - - -/* OSC.DFLLCTRL bit masks and bit positions */ -#define OSC_RC32MCREF_bm 0x02 /* 32MHz Calibration Reference bit mask. */ -#define OSC_RC32MCREF_bp 1 /* 32MHz Calibration Reference bit position. */ - -#define OSC_RC2MCREF_bm 0x01 /* 2MHz Calibration Reference bit mask. */ -#define OSC_RC2MCREF_bp 0 /* 2MHz Calibration Reference bit position. */ - - -/* DFLL - DFLL */ -/* DFLL.CTRL bit masks and bit positions */ -#define DFLL_ENABLE_bm 0x01 /* DFLL Enable bit mask. */ -#define DFLL_ENABLE_bp 0 /* DFLL Enable bit position. */ - - -/* DFLL.CALA bit masks and bit positions */ -#define DFLL_CALL_gm 0x7F /* DFLL Calibration bits [6:0] group mask. */ -#define DFLL_CALL_gp 0 /* DFLL Calibration bits [6:0] group position. */ -#define DFLL_CALL0_bm (1<<0) /* DFLL Calibration bits [6:0] bit 0 mask. */ -#define DFLL_CALL0_bp 0 /* DFLL Calibration bits [6:0] bit 0 position. */ -#define DFLL_CALL1_bm (1<<1) /* DFLL Calibration bits [6:0] bit 1 mask. */ -#define DFLL_CALL1_bp 1 /* DFLL Calibration bits [6:0] bit 1 position. */ -#define DFLL_CALL2_bm (1<<2) /* DFLL Calibration bits [6:0] bit 2 mask. */ -#define DFLL_CALL2_bp 2 /* DFLL Calibration bits [6:0] bit 2 position. */ -#define DFLL_CALL3_bm (1<<3) /* DFLL Calibration bits [6:0] bit 3 mask. */ -#define DFLL_CALL3_bp 3 /* DFLL Calibration bits [6:0] bit 3 position. */ -#define DFLL_CALL4_bm (1<<4) /* DFLL Calibration bits [6:0] bit 4 mask. */ -#define DFLL_CALL4_bp 4 /* DFLL Calibration bits [6:0] bit 4 position. */ -#define DFLL_CALL5_bm (1<<5) /* DFLL Calibration bits [6:0] bit 5 mask. */ -#define DFLL_CALL5_bp 5 /* DFLL Calibration bits [6:0] bit 5 position. */ -#define DFLL_CALL6_bm (1<<6) /* DFLL Calibration bits [6:0] bit 6 mask. */ -#define DFLL_CALL6_bp 6 /* DFLL Calibration bits [6:0] bit 6 position. */ - - -/* DFLL.CALB bit masks and bit positions */ -#define DFLL_CALH_gm 0x3F /* DFLL Calibration bits [12:7] group mask. */ -#define DFLL_CALH_gp 0 /* DFLL Calibration bits [12:7] group position. */ -#define DFLL_CALH0_bm (1<<0) /* DFLL Calibration bits [12:7] bit 0 mask. */ -#define DFLL_CALH0_bp 0 /* DFLL Calibration bits [12:7] bit 0 position. */ -#define DFLL_CALH1_bm (1<<1) /* DFLL Calibration bits [12:7] bit 1 mask. */ -#define DFLL_CALH1_bp 1 /* DFLL Calibration bits [12:7] bit 1 position. */ -#define DFLL_CALH2_bm (1<<2) /* DFLL Calibration bits [12:7] bit 2 mask. */ -#define DFLL_CALH2_bp 2 /* DFLL Calibration bits [12:7] bit 2 position. */ -#define DFLL_CALH3_bm (1<<3) /* DFLL Calibration bits [12:7] bit 3 mask. */ -#define DFLL_CALH3_bp 3 /* DFLL Calibration bits [12:7] bit 3 position. */ -#define DFLL_CALH4_bm (1<<4) /* DFLL Calibration bits [12:7] bit 4 mask. */ -#define DFLL_CALH4_bp 4 /* DFLL Calibration bits [12:7] bit 4 position. */ -#define DFLL_CALH5_bm (1<<5) /* DFLL Calibration bits [12:7] bit 5 mask. */ -#define DFLL_CALH5_bp 5 /* DFLL Calibration bits [12:7] bit 5 position. */ - - -/* RST - Reset */ -/* RST.STATUS bit masks and bit positions */ -#define RST_SDRF_bm 0x40 /* Spike Detection Reset Flag bit mask. */ -#define RST_SDRF_bp 6 /* Spike Detection Reset Flag bit position. */ - -#define RST_SRF_bm 0x20 /* Software Reset Flag bit mask. */ -#define RST_SRF_bp 5 /* Software Reset Flag bit position. */ - -#define RST_PDIRF_bm 0x10 /* Programming and Debug Interface Interface Reset Flag bit mask. */ -#define RST_PDIRF_bp 4 /* Programming and Debug Interface Interface Reset Flag bit position. */ - -#define RST_WDRF_bm 0x08 /* Watchdog Reset Flag bit mask. */ -#define RST_WDRF_bp 3 /* Watchdog Reset Flag bit position. */ - -#define RST_BORF_bm 0x04 /* Brown-out Reset Flag bit mask. */ -#define RST_BORF_bp 2 /* Brown-out Reset Flag bit position. */ - -#define RST_EXTRF_bm 0x02 /* External Reset Flag bit mask. */ -#define RST_EXTRF_bp 1 /* External Reset Flag bit position. */ - -#define RST_PORF_bm 0x01 /* Power-on Reset Flag bit mask. */ -#define RST_PORF_bp 0 /* Power-on Reset Flag bit position. */ - - -/* RST.CTRL bit masks and bit positions */ -#define RST_SWRST_bm 0x01 /* Software Reset bit mask. */ -#define RST_SWRST_bp 0 /* Software Reset bit position. */ - - -/* WDT - Watch-Dog Timer */ -/* WDT.CTRL bit masks and bit positions */ -#define WDT_PER_gm 0x3C /* Period group mask. */ -#define WDT_PER_gp 2 /* Period group position. */ -#define WDT_PER0_bm (1<<2) /* Period bit 0 mask. */ -#define WDT_PER0_bp 2 /* Period bit 0 position. */ -#define WDT_PER1_bm (1<<3) /* Period bit 1 mask. */ -#define WDT_PER1_bp 3 /* Period bit 1 position. */ -#define WDT_PER2_bm (1<<4) /* Period bit 2 mask. */ -#define WDT_PER2_bp 4 /* Period bit 2 position. */ -#define WDT_PER3_bm (1<<5) /* Period bit 3 mask. */ -#define WDT_PER3_bp 5 /* Period bit 3 position. */ - -#define WDT_ENABLE_bm 0x02 /* Enable bit mask. */ -#define WDT_ENABLE_bp 1 /* Enable bit position. */ - -#define WDT_CEN_bm 0x01 /* Change Enable bit mask. */ -#define WDT_CEN_bp 0 /* Change Enable bit position. */ - - -/* WDT.WINCTRL bit masks and bit positions */ -#define WDT_WPER_gm 0x3C /* Windowed Mode Period group mask. */ -#define WDT_WPER_gp 2 /* Windowed Mode Period group position. */ -#define WDT_WPER0_bm (1<<2) /* Windowed Mode Period bit 0 mask. */ -#define WDT_WPER0_bp 2 /* Windowed Mode Period bit 0 position. */ -#define WDT_WPER1_bm (1<<3) /* Windowed Mode Period bit 1 mask. */ -#define WDT_WPER1_bp 3 /* Windowed Mode Period bit 1 position. */ -#define WDT_WPER2_bm (1<<4) /* Windowed Mode Period bit 2 mask. */ -#define WDT_WPER2_bp 4 /* Windowed Mode Period bit 2 position. */ -#define WDT_WPER3_bm (1<<5) /* Windowed Mode Period bit 3 mask. */ -#define WDT_WPER3_bp 5 /* Windowed Mode Period bit 3 position. */ - -#define WDT_WEN_bm 0x02 /* Windowed Mode Enable bit mask. */ -#define WDT_WEN_bp 1 /* Windowed Mode Enable bit position. */ - -#define WDT_WCEN_bm 0x01 /* Windowed Mode Change Enable bit mask. */ -#define WDT_WCEN_bp 0 /* Windowed Mode Change Enable bit position. */ - - -/* WDT.STATUS bit masks and bit positions */ -#define WDT_SYNCBUSY_bm 0x01 /* Syncronization busy bit mask. */ -#define WDT_SYNCBUSY_bp 0 /* Syncronization busy bit position. */ - - -/* MCU - MCU Control */ -/* MCU.MCUCR bit masks and bit positions */ -#define MCU_JTAGD_bm 0x01 /* JTAG Disable bit mask. */ -#define MCU_JTAGD_bp 0 /* JTAG Disable bit position. */ - - -/* MCU.EVSYSLOCK bit masks and bit positions */ -#define MCU_EVSYS1LOCK_bm 0x10 /* Event Channel 4-7 Lock bit mask. */ -#define MCU_EVSYS1LOCK_bp 4 /* Event Channel 4-7 Lock bit position. */ - -#define MCU_EVSYS0LOCK_bm 0x01 /* Event Channel 0-3 Lock bit mask. */ -#define MCU_EVSYS0LOCK_bp 0 /* Event Channel 0-3 Lock bit position. */ - - -/* MCU.AWEXLOCK bit masks and bit positions */ -#define MCU_AWEXELOCK_bm 0x04 /* AWeX on T/C E0 Lock bit mask. */ -#define MCU_AWEXELOCK_bp 2 /* AWeX on T/C E0 Lock bit position. */ - -#define MCU_AWEXCLOCK_bm 0x01 /* AWeX on T/C C0 Lock bit mask. */ -#define MCU_AWEXCLOCK_bp 0 /* AWeX on T/C C0 Lock bit position. */ - - -/* PMIC - Programmable Multi-level Interrupt Controller */ -/* PMIC.STATUS bit masks and bit positions */ -#define PMIC_NMIEX_bm 0x80 /* Non-maskable Interrupt Executing bit mask. */ -#define PMIC_NMIEX_bp 7 /* Non-maskable Interrupt Executing bit position. */ - -#define PMIC_HILVLEX_bm 0x04 /* High Level Interrupt Executing bit mask. */ -#define PMIC_HILVLEX_bp 2 /* High Level Interrupt Executing bit position. */ - -#define PMIC_MEDLVLEX_bm 0x02 /* Medium Level Interrupt Executing bit mask. */ -#define PMIC_MEDLVLEX_bp 1 /* Medium Level Interrupt Executing bit position. */ - -#define PMIC_LOLVLEX_bm 0x01 /* Low Level Interrupt Executing bit mask. */ -#define PMIC_LOLVLEX_bp 0 /* Low Level Interrupt Executing bit position. */ - - -/* PMIC.CTRL bit masks and bit positions */ -#define PMIC_RREN_bm 0x80 /* Round-Robin Priority Enable bit mask. */ -#define PMIC_RREN_bp 7 /* Round-Robin Priority Enable bit position. */ - -#define PMIC_IVSEL_bm 0x40 /* Interrupt Vector Select bit mask. */ -#define PMIC_IVSEL_bp 6 /* Interrupt Vector Select bit position. */ - -#define PMIC_HILVLEN_bm 0x04 /* High Level Enable bit mask. */ -#define PMIC_HILVLEN_bp 2 /* High Level Enable bit position. */ - -#define PMIC_MEDLVLEN_bm 0x02 /* Medium Level Enable bit mask. */ -#define PMIC_MEDLVLEN_bp 1 /* Medium Level Enable bit position. */ - -#define PMIC_LOLVLEN_bm 0x01 /* Low Level Enable bit mask. */ -#define PMIC_LOLVLEN_bp 0 /* Low Level Enable bit position. */ - - -/* DMA - DMA Controller */ -/* DMA_CH.CTRLA bit masks and bit positions */ -#define DMA_CH_ENABLE_bm 0x80 /* Channel Enable bit mask. */ -#define DMA_CH_ENABLE_bp 7 /* Channel Enable bit position. */ - -#define DMA_CH_RESET_bm 0x40 /* Channel Software Reset bit mask. */ -#define DMA_CH_RESET_bp 6 /* Channel Software Reset bit position. */ - -#define DMA_CH_REPEAT_bm 0x20 /* Channel Repeat Mode bit mask. */ -#define DMA_CH_REPEAT_bp 5 /* Channel Repeat Mode bit position. */ - -#define DMA_CH_TRFREQ_bm 0x10 /* Channel Transfer Request bit mask. */ -#define DMA_CH_TRFREQ_bp 4 /* Channel Transfer Request bit position. */ - -#define DMA_CH_SINGLE_bm 0x04 /* Channel Single Shot Data Transfer bit mask. */ -#define DMA_CH_SINGLE_bp 2 /* Channel Single Shot Data Transfer bit position. */ - -#define DMA_CH_BURSTLEN_gm 0x03 /* Channel Transfer Mode group mask. */ -#define DMA_CH_BURSTLEN_gp 0 /* Channel Transfer Mode group position. */ -#define DMA_CH_BURSTLEN0_bm (1<<0) /* Channel Transfer Mode bit 0 mask. */ -#define DMA_CH_BURSTLEN0_bp 0 /* Channel Transfer Mode bit 0 position. */ -#define DMA_CH_BURSTLEN1_bm (1<<1) /* Channel Transfer Mode bit 1 mask. */ -#define DMA_CH_BURSTLEN1_bp 1 /* Channel Transfer Mode bit 1 position. */ - - -/* DMA_CH.CTRLB bit masks and bit positions */ -#define DMA_CH_CHBUSY_bm 0x80 /* Block Transfer Busy bit mask. */ -#define DMA_CH_CHBUSY_bp 7 /* Block Transfer Busy bit position. */ - -#define DMA_CH_CHPEND_bm 0x40 /* Block Transfer Pending bit mask. */ -#define DMA_CH_CHPEND_bp 6 /* Block Transfer Pending bit position. */ - -#define DMA_CH_ERRIF_bm 0x20 /* Block Transfer Error Interrupt Flag bit mask. */ -#define DMA_CH_ERRIF_bp 5 /* Block Transfer Error Interrupt Flag bit position. */ - -#define DMA_CH_TRNIF_bm 0x10 /* Transaction Complete Interrup Flag bit mask. */ -#define DMA_CH_TRNIF_bp 4 /* Transaction Complete Interrup Flag bit position. */ - -#define DMA_CH_ERRINTLVL_gm 0x0C /* Transfer Error Interrupt Level group mask. */ -#define DMA_CH_ERRINTLVL_gp 2 /* Transfer Error Interrupt Level group position. */ -#define DMA_CH_ERRINTLVL0_bm (1<<2) /* Transfer Error Interrupt Level bit 0 mask. */ -#define DMA_CH_ERRINTLVL0_bp 2 /* Transfer Error Interrupt Level bit 0 position. */ -#define DMA_CH_ERRINTLVL1_bm (1<<3) /* Transfer Error Interrupt Level bit 1 mask. */ -#define DMA_CH_ERRINTLVL1_bp 3 /* Transfer Error Interrupt Level bit 1 position. */ - -#define DMA_CH_TRNINTLVL_gm 0x03 /* Transaction Complete Interrupt Level group mask. */ -#define DMA_CH_TRNINTLVL_gp 0 /* Transaction Complete Interrupt Level group position. */ -#define DMA_CH_TRNINTLVL0_bm (1<<0) /* Transaction Complete Interrupt Level bit 0 mask. */ -#define DMA_CH_TRNINTLVL0_bp 0 /* Transaction Complete Interrupt Level bit 0 position. */ -#define DMA_CH_TRNINTLVL1_bm (1<<1) /* Transaction Complete Interrupt Level bit 1 mask. */ -#define DMA_CH_TRNINTLVL1_bp 1 /* Transaction Complete Interrupt Level bit 1 position. */ - - -/* DMA_CH.ADDRCTRL bit masks and bit positions */ -#define DMA_CH_SRCRELOAD_gm 0xC0 /* Channel Source Address Reload group mask. */ -#define DMA_CH_SRCRELOAD_gp 6 /* Channel Source Address Reload group position. */ -#define DMA_CH_SRCRELOAD0_bm (1<<6) /* Channel Source Address Reload bit 0 mask. */ -#define DMA_CH_SRCRELOAD0_bp 6 /* Channel Source Address Reload bit 0 position. */ -#define DMA_CH_SRCRELOAD1_bm (1<<7) /* Channel Source Address Reload bit 1 mask. */ -#define DMA_CH_SRCRELOAD1_bp 7 /* Channel Source Address Reload bit 1 position. */ - -#define DMA_CH_SRCDIR_gm 0x30 /* Channel Source Address Mode group mask. */ -#define DMA_CH_SRCDIR_gp 4 /* Channel Source Address Mode group position. */ -#define DMA_CH_SRCDIR0_bm (1<<4) /* Channel Source Address Mode bit 0 mask. */ -#define DMA_CH_SRCDIR0_bp 4 /* Channel Source Address Mode bit 0 position. */ -#define DMA_CH_SRCDIR1_bm (1<<5) /* Channel Source Address Mode bit 1 mask. */ -#define DMA_CH_SRCDIR1_bp 5 /* Channel Source Address Mode bit 1 position. */ - -#define DMA_CH_DESTRELOAD_gm 0x0C /* Channel Destination Address Reload group mask. */ -#define DMA_CH_DESTRELOAD_gp 2 /* Channel Destination Address Reload group position. */ -#define DMA_CH_DESTRELOAD0_bm (1<<2) /* Channel Destination Address Reload bit 0 mask. */ -#define DMA_CH_DESTRELOAD0_bp 2 /* Channel Destination Address Reload bit 0 position. */ -#define DMA_CH_DESTRELOAD1_bm (1<<3) /* Channel Destination Address Reload bit 1 mask. */ -#define DMA_CH_DESTRELOAD1_bp 3 /* Channel Destination Address Reload bit 1 position. */ - -#define DMA_CH_DESTDIR_gm 0x03 /* Channel Destination Address Mode group mask. */ -#define DMA_CH_DESTDIR_gp 0 /* Channel Destination Address Mode group position. */ -#define DMA_CH_DESTDIR0_bm (1<<0) /* Channel Destination Address Mode bit 0 mask. */ -#define DMA_CH_DESTDIR0_bp 0 /* Channel Destination Address Mode bit 0 position. */ -#define DMA_CH_DESTDIR1_bm (1<<1) /* Channel Destination Address Mode bit 1 mask. */ -#define DMA_CH_DESTDIR1_bp 1 /* Channel Destination Address Mode bit 1 position. */ - - -/* DMA_CH.TRIGSRC bit masks and bit positions */ -#define DMA_CH_TRIGSRC_gm 0xFF /* Channel Trigger Source group mask. */ -#define DMA_CH_TRIGSRC_gp 0 /* Channel Trigger Source group position. */ -#define DMA_CH_TRIGSRC0_bm (1<<0) /* Channel Trigger Source bit 0 mask. */ -#define DMA_CH_TRIGSRC0_bp 0 /* Channel Trigger Source bit 0 position. */ -#define DMA_CH_TRIGSRC1_bm (1<<1) /* Channel Trigger Source bit 1 mask. */ -#define DMA_CH_TRIGSRC1_bp 1 /* Channel Trigger Source bit 1 position. */ -#define DMA_CH_TRIGSRC2_bm (1<<2) /* Channel Trigger Source bit 2 mask. */ -#define DMA_CH_TRIGSRC2_bp 2 /* Channel Trigger Source bit 2 position. */ -#define DMA_CH_TRIGSRC3_bm (1<<3) /* Channel Trigger Source bit 3 mask. */ -#define DMA_CH_TRIGSRC3_bp 3 /* Channel Trigger Source bit 3 position. */ -#define DMA_CH_TRIGSRC4_bm (1<<4) /* Channel Trigger Source bit 4 mask. */ -#define DMA_CH_TRIGSRC4_bp 4 /* Channel Trigger Source bit 4 position. */ -#define DMA_CH_TRIGSRC5_bm (1<<5) /* Channel Trigger Source bit 5 mask. */ -#define DMA_CH_TRIGSRC5_bp 5 /* Channel Trigger Source bit 5 position. */ -#define DMA_CH_TRIGSRC6_bm (1<<6) /* Channel Trigger Source bit 6 mask. */ -#define DMA_CH_TRIGSRC6_bp 6 /* Channel Trigger Source bit 6 position. */ -#define DMA_CH_TRIGSRC7_bm (1<<7) /* Channel Trigger Source bit 7 mask. */ -#define DMA_CH_TRIGSRC7_bp 7 /* Channel Trigger Source bit 7 position. */ - - -/* DMA.CTRL bit masks and bit positions */ -#define DMA_ENABLE_bm 0x80 /* Enable bit mask. */ -#define DMA_ENABLE_bp 7 /* Enable bit position. */ - -#define DMA_RESET_bm 0x40 /* Software Reset bit mask. */ -#define DMA_RESET_bp 6 /* Software Reset bit position. */ - -#define DMA_DBUFMODE_gm 0x0C /* Double Buffering Mode group mask. */ -#define DMA_DBUFMODE_gp 2 /* Double Buffering Mode group position. */ -#define DMA_DBUFMODE0_bm (1<<2) /* Double Buffering Mode bit 0 mask. */ -#define DMA_DBUFMODE0_bp 2 /* Double Buffering Mode bit 0 position. */ -#define DMA_DBUFMODE1_bm (1<<3) /* Double Buffering Mode bit 1 mask. */ -#define DMA_DBUFMODE1_bp 3 /* Double Buffering Mode bit 1 position. */ - -#define DMA_PRIMODE_gm 0x03 /* Channel Priority Mode group mask. */ -#define DMA_PRIMODE_gp 0 /* Channel Priority Mode group position. */ -#define DMA_PRIMODE0_bm (1<<0) /* Channel Priority Mode bit 0 mask. */ -#define DMA_PRIMODE0_bp 0 /* Channel Priority Mode bit 0 position. */ -#define DMA_PRIMODE1_bm (1<<1) /* Channel Priority Mode bit 1 mask. */ -#define DMA_PRIMODE1_bp 1 /* Channel Priority Mode bit 1 position. */ - - -/* DMA.INTFLAGS bit masks and bit positions */ -#define DMA_CH3ERRIF_bm 0x80 /* Channel 3 Block Transfer Error Interrupt Flag bit mask. */ -#define DMA_CH3ERRIF_bp 7 /* Channel 3 Block Transfer Error Interrupt Flag bit position. */ - -#define DMA_CH2ERRIF_bm 0x40 /* Channel 2 Block Transfer Error Interrupt Flag bit mask. */ -#define DMA_CH2ERRIF_bp 6 /* Channel 2 Block Transfer Error Interrupt Flag bit position. */ - -#define DMA_CH1ERRIF_bm 0x20 /* Channel 1 Block Transfer Error Interrupt Flag bit mask. */ -#define DMA_CH1ERRIF_bp 5 /* Channel 1 Block Transfer Error Interrupt Flag bit position. */ - -#define DMA_CH0ERRIF_bm 0x10 /* Channel 0 Block Transfer Error Interrupt Flag bit mask. */ -#define DMA_CH0ERRIF_bp 4 /* Channel 0 Block Transfer Error Interrupt Flag bit position. */ - -#define DMA_CH3TRNIF_bm 0x08 /* Channel 3 Transaction Complete Interrupt Flag bit mask. */ -#define DMA_CH3TRNIF_bp 3 /* Channel 3 Transaction Complete Interrupt Flag bit position. */ - -#define DMA_CH2TRNIF_bm 0x04 /* Channel 2 Transaction Complete Interrupt Flag bit mask. */ -#define DMA_CH2TRNIF_bp 2 /* Channel 2 Transaction Complete Interrupt Flag bit position. */ - -#define DMA_CH1TRNIF_bm 0x02 /* Channel 1 Transaction Complete Interrupt Flag bit mask. */ -#define DMA_CH1TRNIF_bp 1 /* Channel 1 Transaction Complete Interrupt Flag bit position. */ - -#define DMA_CH0TRNIF_bm 0x01 /* Channel 0 Transaction Complete Interrupt Flag bit mask. */ -#define DMA_CH0TRNIF_bp 0 /* Channel 0 Transaction Complete Interrupt Flag bit position. */ - - -/* DMA.STATUS bit masks and bit positions */ -#define DMA_CH3BUSY_bm 0x80 /* Channel 3 Block Transfer Busy bit mask. */ -#define DMA_CH3BUSY_bp 7 /* Channel 3 Block Transfer Busy bit position. */ - -#define DMA_CH2BUSY_bm 0x40 /* Channel 2 Block Transfer Busy bit mask. */ -#define DMA_CH2BUSY_bp 6 /* Channel 2 Block Transfer Busy bit position. */ - -#define DMA_CH1BUSY_bm 0x20 /* Channel 1 Block Transfer Busy bit mask. */ -#define DMA_CH1BUSY_bp 5 /* Channel 1 Block Transfer Busy bit position. */ - -#define DMA_CH0BUSY_bm 0x10 /* Channel 0 Block Transfer Busy bit mask. */ -#define DMA_CH0BUSY_bp 4 /* Channel 0 Block Transfer Busy bit position. */ - -#define DMA_CH3PEND_bm 0x08 /* Channel 3 Block Transfer Pending bit mask. */ -#define DMA_CH3PEND_bp 3 /* Channel 3 Block Transfer Pending bit position. */ - -#define DMA_CH2PEND_bm 0x04 /* Channel 2 Block Transfer Pending bit mask. */ -#define DMA_CH2PEND_bp 2 /* Channel 2 Block Transfer Pending bit position. */ - -#define DMA_CH1PEND_bm 0x02 /* Channel 1 Block Transfer Pending bit mask. */ -#define DMA_CH1PEND_bp 1 /* Channel 1 Block Transfer Pending bit position. */ - -#define DMA_CH0PEND_bm 0x01 /* Channel 0 Block Transfer Pending bit mask. */ -#define DMA_CH0PEND_bp 0 /* Channel 0 Block Transfer Pending bit position. */ - - -/* EVSYS - Event System */ -/* EVSYS.CH0MUX bit masks and bit positions */ -#define EVSYS_CHMUX_gm 0xFF /* Event Channel 0 Multiplexer group mask. */ -#define EVSYS_CHMUX_gp 0 /* Event Channel 0 Multiplexer group position. */ -#define EVSYS_CHMUX0_bm (1<<0) /* Event Channel 0 Multiplexer bit 0 mask. */ -#define EVSYS_CHMUX0_bp 0 /* Event Channel 0 Multiplexer bit 0 position. */ -#define EVSYS_CHMUX1_bm (1<<1) /* Event Channel 0 Multiplexer bit 1 mask. */ -#define EVSYS_CHMUX1_bp 1 /* Event Channel 0 Multiplexer bit 1 position. */ -#define EVSYS_CHMUX2_bm (1<<2) /* Event Channel 0 Multiplexer bit 2 mask. */ -#define EVSYS_CHMUX2_bp 2 /* Event Channel 0 Multiplexer bit 2 position. */ -#define EVSYS_CHMUX3_bm (1<<3) /* Event Channel 0 Multiplexer bit 3 mask. */ -#define EVSYS_CHMUX3_bp 3 /* Event Channel 0 Multiplexer bit 3 position. */ -#define EVSYS_CHMUX4_bm (1<<4) /* Event Channel 0 Multiplexer bit 4 mask. */ -#define EVSYS_CHMUX4_bp 4 /* Event Channel 0 Multiplexer bit 4 position. */ -#define EVSYS_CHMUX5_bm (1<<5) /* Event Channel 0 Multiplexer bit 5 mask. */ -#define EVSYS_CHMUX5_bp 5 /* Event Channel 0 Multiplexer bit 5 position. */ -#define EVSYS_CHMUX6_bm (1<<6) /* Event Channel 0 Multiplexer bit 6 mask. */ -#define EVSYS_CHMUX6_bp 6 /* Event Channel 0 Multiplexer bit 6 position. */ -#define EVSYS_CHMUX7_bm (1<<7) /* Event Channel 0 Multiplexer bit 7 mask. */ -#define EVSYS_CHMUX7_bp 7 /* Event Channel 0 Multiplexer bit 7 position. */ - - -/* EVSYS.CH1MUX bit masks and bit positions */ -/* EVSYS_CHMUX_gm Predefined. */ -/* EVSYS_CHMUX_gp Predefined. */ -/* EVSYS_CHMUX0_bm Predefined. */ -/* EVSYS_CHMUX0_bp Predefined. */ -/* EVSYS_CHMUX1_bm Predefined. */ -/* EVSYS_CHMUX1_bp Predefined. */ -/* EVSYS_CHMUX2_bm Predefined. */ -/* EVSYS_CHMUX2_bp Predefined. */ -/* EVSYS_CHMUX3_bm Predefined. */ -/* EVSYS_CHMUX3_bp Predefined. */ -/* EVSYS_CHMUX4_bm Predefined. */ -/* EVSYS_CHMUX4_bp Predefined. */ -/* EVSYS_CHMUX5_bm Predefined. */ -/* EVSYS_CHMUX5_bp Predefined. */ -/* EVSYS_CHMUX6_bm Predefined. */ -/* EVSYS_CHMUX6_bp Predefined. */ -/* EVSYS_CHMUX7_bm Predefined. */ -/* EVSYS_CHMUX7_bp Predefined. */ - - -/* EVSYS.CH2MUX bit masks and bit positions */ -/* EVSYS_CHMUX_gm Predefined. */ -/* EVSYS_CHMUX_gp Predefined. */ -/* EVSYS_CHMUX0_bm Predefined. */ -/* EVSYS_CHMUX0_bp Predefined. */ -/* EVSYS_CHMUX1_bm Predefined. */ -/* EVSYS_CHMUX1_bp Predefined. */ -/* EVSYS_CHMUX2_bm Predefined. */ -/* EVSYS_CHMUX2_bp Predefined. */ -/* EVSYS_CHMUX3_bm Predefined. */ -/* EVSYS_CHMUX3_bp Predefined. */ -/* EVSYS_CHMUX4_bm Predefined. */ -/* EVSYS_CHMUX4_bp Predefined. */ -/* EVSYS_CHMUX5_bm Predefined. */ -/* EVSYS_CHMUX5_bp Predefined. */ -/* EVSYS_CHMUX6_bm Predefined. */ -/* EVSYS_CHMUX6_bp Predefined. */ -/* EVSYS_CHMUX7_bm Predefined. */ -/* EVSYS_CHMUX7_bp Predefined. */ - - -/* EVSYS.CH3MUX bit masks and bit positions */ -/* EVSYS_CHMUX_gm Predefined. */ -/* EVSYS_CHMUX_gp Predefined. */ -/* EVSYS_CHMUX0_bm Predefined. */ -/* EVSYS_CHMUX0_bp Predefined. */ -/* EVSYS_CHMUX1_bm Predefined. */ -/* EVSYS_CHMUX1_bp Predefined. */ -/* EVSYS_CHMUX2_bm Predefined. */ -/* EVSYS_CHMUX2_bp Predefined. */ -/* EVSYS_CHMUX3_bm Predefined. */ -/* EVSYS_CHMUX3_bp Predefined. */ -/* EVSYS_CHMUX4_bm Predefined. */ -/* EVSYS_CHMUX4_bp Predefined. */ -/* EVSYS_CHMUX5_bm Predefined. */ -/* EVSYS_CHMUX5_bp Predefined. */ -/* EVSYS_CHMUX6_bm Predefined. */ -/* EVSYS_CHMUX6_bp Predefined. */ -/* EVSYS_CHMUX7_bm Predefined. */ -/* EVSYS_CHMUX7_bp Predefined. */ - - -/* EVSYS.CH4MUX bit masks and bit positions */ -/* EVSYS_CHMUX_gm Predefined. */ -/* EVSYS_CHMUX_gp Predefined. */ -/* EVSYS_CHMUX0_bm Predefined. */ -/* EVSYS_CHMUX0_bp Predefined. */ -/* EVSYS_CHMUX1_bm Predefined. */ -/* EVSYS_CHMUX1_bp Predefined. */ -/* EVSYS_CHMUX2_bm Predefined. */ -/* EVSYS_CHMUX2_bp Predefined. */ -/* EVSYS_CHMUX3_bm Predefined. */ -/* EVSYS_CHMUX3_bp Predefined. */ -/* EVSYS_CHMUX4_bm Predefined. */ -/* EVSYS_CHMUX4_bp Predefined. */ -/* EVSYS_CHMUX5_bm Predefined. */ -/* EVSYS_CHMUX5_bp Predefined. */ -/* EVSYS_CHMUX6_bm Predefined. */ -/* EVSYS_CHMUX6_bp Predefined. */ -/* EVSYS_CHMUX7_bm Predefined. */ -/* EVSYS_CHMUX7_bp Predefined. */ - - -/* EVSYS.CH5MUX bit masks and bit positions */ -/* EVSYS_CHMUX_gm Predefined. */ -/* EVSYS_CHMUX_gp Predefined. */ -/* EVSYS_CHMUX0_bm Predefined. */ -/* EVSYS_CHMUX0_bp Predefined. */ -/* EVSYS_CHMUX1_bm Predefined. */ -/* EVSYS_CHMUX1_bp Predefined. */ -/* EVSYS_CHMUX2_bm Predefined. */ -/* EVSYS_CHMUX2_bp Predefined. */ -/* EVSYS_CHMUX3_bm Predefined. */ -/* EVSYS_CHMUX3_bp Predefined. */ -/* EVSYS_CHMUX4_bm Predefined. */ -/* EVSYS_CHMUX4_bp Predefined. */ -/* EVSYS_CHMUX5_bm Predefined. */ -/* EVSYS_CHMUX5_bp Predefined. */ -/* EVSYS_CHMUX6_bm Predefined. */ -/* EVSYS_CHMUX6_bp Predefined. */ -/* EVSYS_CHMUX7_bm Predefined. */ -/* EVSYS_CHMUX7_bp Predefined. */ - - -/* EVSYS.CH6MUX bit masks and bit positions */ -/* EVSYS_CHMUX_gm Predefined. */ -/* EVSYS_CHMUX_gp Predefined. */ -/* EVSYS_CHMUX0_bm Predefined. */ -/* EVSYS_CHMUX0_bp Predefined. */ -/* EVSYS_CHMUX1_bm Predefined. */ -/* EVSYS_CHMUX1_bp Predefined. */ -/* EVSYS_CHMUX2_bm Predefined. */ -/* EVSYS_CHMUX2_bp Predefined. */ -/* EVSYS_CHMUX3_bm Predefined. */ -/* EVSYS_CHMUX3_bp Predefined. */ -/* EVSYS_CHMUX4_bm Predefined. */ -/* EVSYS_CHMUX4_bp Predefined. */ -/* EVSYS_CHMUX5_bm Predefined. */ -/* EVSYS_CHMUX5_bp Predefined. */ -/* EVSYS_CHMUX6_bm Predefined. */ -/* EVSYS_CHMUX6_bp Predefined. */ -/* EVSYS_CHMUX7_bm Predefined. */ -/* EVSYS_CHMUX7_bp Predefined. */ - - -/* EVSYS.CH7MUX bit masks and bit positions */ -/* EVSYS_CHMUX_gm Predefined. */ -/* EVSYS_CHMUX_gp Predefined. */ -/* EVSYS_CHMUX0_bm Predefined. */ -/* EVSYS_CHMUX0_bp Predefined. */ -/* EVSYS_CHMUX1_bm Predefined. */ -/* EVSYS_CHMUX1_bp Predefined. */ -/* EVSYS_CHMUX2_bm Predefined. */ -/* EVSYS_CHMUX2_bp Predefined. */ -/* EVSYS_CHMUX3_bm Predefined. */ -/* EVSYS_CHMUX3_bp Predefined. */ -/* EVSYS_CHMUX4_bm Predefined. */ -/* EVSYS_CHMUX4_bp Predefined. */ -/* EVSYS_CHMUX5_bm Predefined. */ -/* EVSYS_CHMUX5_bp Predefined. */ -/* EVSYS_CHMUX6_bm Predefined. */ -/* EVSYS_CHMUX6_bp Predefined. */ -/* EVSYS_CHMUX7_bm Predefined. */ -/* EVSYS_CHMUX7_bp Predefined. */ - - -/* EVSYS.CH0CTRL bit masks and bit positions */ -#define EVSYS_QDIRM_gm 0x60 /* Quadrature Decoder Index Recognition Mode group mask. */ -#define EVSYS_QDIRM_gp 5 /* Quadrature Decoder Index Recognition Mode group position. */ -#define EVSYS_QDIRM0_bm (1<<5) /* Quadrature Decoder Index Recognition Mode bit 0 mask. */ -#define EVSYS_QDIRM0_bp 5 /* Quadrature Decoder Index Recognition Mode bit 0 position. */ -#define EVSYS_QDIRM1_bm (1<<6) /* Quadrature Decoder Index Recognition Mode bit 1 mask. */ -#define EVSYS_QDIRM1_bp 6 /* Quadrature Decoder Index Recognition Mode bit 1 position. */ - -#define EVSYS_QDIEN_bm 0x10 /* Quadrature Decoder Index Enable bit mask. */ -#define EVSYS_QDIEN_bp 4 /* Quadrature Decoder Index Enable bit position. */ - -#define EVSYS_QDEN_bm 0x08 /* Quadrature Decoder Enable bit mask. */ -#define EVSYS_QDEN_bp 3 /* Quadrature Decoder Enable bit position. */ - -#define EVSYS_DIGFILT_gm 0x07 /* Digital Filter group mask. */ -#define EVSYS_DIGFILT_gp 0 /* Digital Filter group position. */ -#define EVSYS_DIGFILT0_bm (1<<0) /* Digital Filter bit 0 mask. */ -#define EVSYS_DIGFILT0_bp 0 /* Digital Filter bit 0 position. */ -#define EVSYS_DIGFILT1_bm (1<<1) /* Digital Filter bit 1 mask. */ -#define EVSYS_DIGFILT1_bp 1 /* Digital Filter bit 1 position. */ -#define EVSYS_DIGFILT2_bm (1<<2) /* Digital Filter bit 2 mask. */ -#define EVSYS_DIGFILT2_bp 2 /* Digital Filter bit 2 position. */ - - -/* EVSYS.CH1CTRL bit masks and bit positions */ -/* EVSYS_DIGFILT_gm Predefined. */ -/* EVSYS_DIGFILT_gp Predefined. */ -/* EVSYS_DIGFILT0_bm Predefined. */ -/* EVSYS_DIGFILT0_bp Predefined. */ -/* EVSYS_DIGFILT1_bm Predefined. */ -/* EVSYS_DIGFILT1_bp Predefined. */ -/* EVSYS_DIGFILT2_bm Predefined. */ -/* EVSYS_DIGFILT2_bp Predefined. */ - - -/* EVSYS.CH2CTRL bit masks and bit positions */ -/* EVSYS_QDIRM_gm Predefined. */ -/* EVSYS_QDIRM_gp Predefined. */ -/* EVSYS_QDIRM0_bm Predefined. */ -/* EVSYS_QDIRM0_bp Predefined. */ -/* EVSYS_QDIRM1_bm Predefined. */ -/* EVSYS_QDIRM1_bp Predefined. */ - -/* EVSYS_QDIEN_bm Predefined. */ -/* EVSYS_QDIEN_bp Predefined. */ - -/* EVSYS_QDEN_bm Predefined. */ -/* EVSYS_QDEN_bp Predefined. */ - -/* EVSYS_DIGFILT_gm Predefined. */ -/* EVSYS_DIGFILT_gp Predefined. */ -/* EVSYS_DIGFILT0_bm Predefined. */ -/* EVSYS_DIGFILT0_bp Predefined. */ -/* EVSYS_DIGFILT1_bm Predefined. */ -/* EVSYS_DIGFILT1_bp Predefined. */ -/* EVSYS_DIGFILT2_bm Predefined. */ -/* EVSYS_DIGFILT2_bp Predefined. */ - - -/* EVSYS.CH3CTRL bit masks and bit positions */ -/* EVSYS_DIGFILT_gm Predefined. */ -/* EVSYS_DIGFILT_gp Predefined. */ -/* EVSYS_DIGFILT0_bm Predefined. */ -/* EVSYS_DIGFILT0_bp Predefined. */ -/* EVSYS_DIGFILT1_bm Predefined. */ -/* EVSYS_DIGFILT1_bp Predefined. */ -/* EVSYS_DIGFILT2_bm Predefined. */ -/* EVSYS_DIGFILT2_bp Predefined. */ - - -/* EVSYS.CH4CTRL bit masks and bit positions */ -/* EVSYS_QDIRM_gm Predefined. */ -/* EVSYS_QDIRM_gp Predefined. */ -/* EVSYS_QDIRM0_bm Predefined. */ -/* EVSYS_QDIRM0_bp Predefined. */ -/* EVSYS_QDIRM1_bm Predefined. */ -/* EVSYS_QDIRM1_bp Predefined. */ - -/* EVSYS_QDIEN_bm Predefined. */ -/* EVSYS_QDIEN_bp Predefined. */ - -/* EVSYS_QDEN_bm Predefined. */ -/* EVSYS_QDEN_bp Predefined. */ - -/* EVSYS_DIGFILT_gm Predefined. */ -/* EVSYS_DIGFILT_gp Predefined. */ -/* EVSYS_DIGFILT0_bm Predefined. */ -/* EVSYS_DIGFILT0_bp Predefined. */ -/* EVSYS_DIGFILT1_bm Predefined. */ -/* EVSYS_DIGFILT1_bp Predefined. */ -/* EVSYS_DIGFILT2_bm Predefined. */ -/* EVSYS_DIGFILT2_bp Predefined. */ - - -/* EVSYS.CH5CTRL bit masks and bit positions */ -/* EVSYS_DIGFILT_gm Predefined. */ -/* EVSYS_DIGFILT_gp Predefined. */ -/* EVSYS_DIGFILT0_bm Predefined. */ -/* EVSYS_DIGFILT0_bp Predefined. */ -/* EVSYS_DIGFILT1_bm Predefined. */ -/* EVSYS_DIGFILT1_bp Predefined. */ -/* EVSYS_DIGFILT2_bm Predefined. */ -/* EVSYS_DIGFILT2_bp Predefined. */ - - -/* EVSYS.CH6CTRL bit masks and bit positions */ -/* EVSYS_DIGFILT_gm Predefined. */ -/* EVSYS_DIGFILT_gp Predefined. */ -/* EVSYS_DIGFILT0_bm Predefined. */ -/* EVSYS_DIGFILT0_bp Predefined. */ -/* EVSYS_DIGFILT1_bm Predefined. */ -/* EVSYS_DIGFILT1_bp Predefined. */ -/* EVSYS_DIGFILT2_bm Predefined. */ -/* EVSYS_DIGFILT2_bp Predefined. */ - - -/* EVSYS.CH7CTRL bit masks and bit positions */ -/* EVSYS_DIGFILT_gm Predefined. */ -/* EVSYS_DIGFILT_gp Predefined. */ -/* EVSYS_DIGFILT0_bm Predefined. */ -/* EVSYS_DIGFILT0_bp Predefined. */ -/* EVSYS_DIGFILT1_bm Predefined. */ -/* EVSYS_DIGFILT1_bp Predefined. */ -/* EVSYS_DIGFILT2_bm Predefined. */ -/* EVSYS_DIGFILT2_bp Predefined. */ - - -/* NVM - Non Volatile Memory Controller */ -/* NVM.CMD bit masks and bit positions */ -#define NVM_CMD_gm 0xFF /* Command group mask. */ -#define NVM_CMD_gp 0 /* Command group position. */ -#define NVM_CMD0_bm (1<<0) /* Command bit 0 mask. */ -#define NVM_CMD0_bp 0 /* Command bit 0 position. */ -#define NVM_CMD1_bm (1<<1) /* Command bit 1 mask. */ -#define NVM_CMD1_bp 1 /* Command bit 1 position. */ -#define NVM_CMD2_bm (1<<2) /* Command bit 2 mask. */ -#define NVM_CMD2_bp 2 /* Command bit 2 position. */ -#define NVM_CMD3_bm (1<<3) /* Command bit 3 mask. */ -#define NVM_CMD3_bp 3 /* Command bit 3 position. */ -#define NVM_CMD4_bm (1<<4) /* Command bit 4 mask. */ -#define NVM_CMD4_bp 4 /* Command bit 4 position. */ -#define NVM_CMD5_bm (1<<5) /* Command bit 5 mask. */ -#define NVM_CMD5_bp 5 /* Command bit 5 position. */ -#define NVM_CMD6_bm (1<<6) /* Command bit 6 mask. */ -#define NVM_CMD6_bp 6 /* Command bit 6 position. */ -#define NVM_CMD7_bm (1<<7) /* Command bit 7 mask. */ -#define NVM_CMD7_bp 7 /* Command bit 7 position. */ - - -/* NVM.CTRLA bit masks and bit positions */ -#define NVM_CMDEX_bm 0x01 /* Command Execute bit mask. */ -#define NVM_CMDEX_bp 0 /* Command Execute bit position. */ - - -/* NVM.CTRLB bit masks and bit positions */ -#define NVM_EEMAPEN_bm 0x08 /* EEPROM Mapping Enable bit mask. */ -#define NVM_EEMAPEN_bp 3 /* EEPROM Mapping Enable bit position. */ - -#define NVM_FPRM_bm 0x04 /* Flash Power Reduction Enable bit mask. */ -#define NVM_FPRM_bp 2 /* Flash Power Reduction Enable bit position. */ - -#define NVM_EPRM_bm 0x02 /* EEPROM Power Reduction Enable bit mask. */ -#define NVM_EPRM_bp 1 /* EEPROM Power Reduction Enable bit position. */ - -#define NVM_SPMLOCK_bm 0x01 /* SPM Lock bit mask. */ -#define NVM_SPMLOCK_bp 0 /* SPM Lock bit position. */ - - -/* NVM.INTCTRL bit masks and bit positions */ -#define NVM_SPMLVL_gm 0x0C /* SPM Interrupt Level group mask. */ -#define NVM_SPMLVL_gp 2 /* SPM Interrupt Level group position. */ -#define NVM_SPMLVL0_bm (1<<2) /* SPM Interrupt Level bit 0 mask. */ -#define NVM_SPMLVL0_bp 2 /* SPM Interrupt Level bit 0 position. */ -#define NVM_SPMLVL1_bm (1<<3) /* SPM Interrupt Level bit 1 mask. */ -#define NVM_SPMLVL1_bp 3 /* SPM Interrupt Level bit 1 position. */ - -#define NVM_EELVL_gm 0x03 /* EEPROM Interrupt Level group mask. */ -#define NVM_EELVL_gp 0 /* EEPROM Interrupt Level group position. */ -#define NVM_EELVL0_bm (1<<0) /* EEPROM Interrupt Level bit 0 mask. */ -#define NVM_EELVL0_bp 0 /* EEPROM Interrupt Level bit 0 position. */ -#define NVM_EELVL1_bm (1<<1) /* EEPROM Interrupt Level bit 1 mask. */ -#define NVM_EELVL1_bp 1 /* EEPROM Interrupt Level bit 1 position. */ - - -/* NVM.STATUS bit masks and bit positions */ -#define NVM_NVMBUSY_bm 0x80 /* Non-volatile Memory Busy bit mask. */ -#define NVM_NVMBUSY_bp 7 /* Non-volatile Memory Busy bit position. */ - -#define NVM_FBUSY_bm 0x40 /* Flash Memory Busy bit mask. */ -#define NVM_FBUSY_bp 6 /* Flash Memory Busy bit position. */ - -#define NVM_EELOAD_bm 0x02 /* EEPROM Page Buffer Active Loading bit mask. */ -#define NVM_EELOAD_bp 1 /* EEPROM Page Buffer Active Loading bit position. */ - -#define NVM_FLOAD_bm 0x01 /* Flash Page Buffer Active Loading bit mask. */ -#define NVM_FLOAD_bp 0 /* Flash Page Buffer Active Loading bit position. */ - - -/* NVM.LOCKBITS bit masks and bit positions */ -#define NVM_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ -#define NVM_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ -#define NVM_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ -#define NVM_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ -#define NVM_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ -#define NVM_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ - -#define NVM_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ -#define NVM_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ -#define NVM_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ -#define NVM_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ -#define NVM_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ -#define NVM_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ - -#define NVM_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ -#define NVM_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ -#define NVM_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ -#define NVM_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ -#define NVM_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ -#define NVM_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ - -#define NVM_LB_gm 0x03 /* Lock Bits group mask. */ -#define NVM_LB_gp 0 /* Lock Bits group position. */ -#define NVM_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ -#define NVM_LB0_bp 0 /* Lock Bits bit 0 position. */ -#define NVM_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ -#define NVM_LB1_bp 1 /* Lock Bits bit 1 position. */ - - -/* NVM_LOCKBITS.LOCKBITS bit masks and bit positions */ -#define NVM_LOCKBITS_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ -#define NVM_LOCKBITS_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ -#define NVM_LOCKBITS_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ -#define NVM_LOCKBITS_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ -#define NVM_LOCKBITS_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ -#define NVM_LOCKBITS_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ - -#define NVM_LOCKBITS_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ -#define NVM_LOCKBITS_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ -#define NVM_LOCKBITS_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ -#define NVM_LOCKBITS_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ -#define NVM_LOCKBITS_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ -#define NVM_LOCKBITS_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ - -#define NVM_LOCKBITS_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ -#define NVM_LOCKBITS_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ -#define NVM_LOCKBITS_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ -#define NVM_LOCKBITS_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ -#define NVM_LOCKBITS_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ -#define NVM_LOCKBITS_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ - -#define NVM_LOCKBITS_LB_gm 0x03 /* Lock Bits group mask. */ -#define NVM_LOCKBITS_LB_gp 0 /* Lock Bits group position. */ -#define NVM_LOCKBITS_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ -#define NVM_LOCKBITS_LB0_bp 0 /* Lock Bits bit 0 position. */ -#define NVM_LOCKBITS_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ -#define NVM_LOCKBITS_LB1_bp 1 /* Lock Bits bit 1 position. */ - - -/* NVM_FUSES.FUSEBYTE0 bit masks and bit positions */ -#define NVM_FUSES_JTAGUSERID_gm 0xFF /* JTAG User ID group mask. */ -#define NVM_FUSES_JTAGUSERID_gp 0 /* JTAG User ID group position. */ -#define NVM_FUSES_JTAGUSERID0_bm (1<<0) /* JTAG User ID bit 0 mask. */ -#define NVM_FUSES_JTAGUSERID0_bp 0 /* JTAG User ID bit 0 position. */ -#define NVM_FUSES_JTAGUSERID1_bm (1<<1) /* JTAG User ID bit 1 mask. */ -#define NVM_FUSES_JTAGUSERID1_bp 1 /* JTAG User ID bit 1 position. */ -#define NVM_FUSES_JTAGUSERID2_bm (1<<2) /* JTAG User ID bit 2 mask. */ -#define NVM_FUSES_JTAGUSERID2_bp 2 /* JTAG User ID bit 2 position. */ -#define NVM_FUSES_JTAGUSERID3_bm (1<<3) /* JTAG User ID bit 3 mask. */ -#define NVM_FUSES_JTAGUSERID3_bp 3 /* JTAG User ID bit 3 position. */ -#define NVM_FUSES_JTAGUSERID4_bm (1<<4) /* JTAG User ID bit 4 mask. */ -#define NVM_FUSES_JTAGUSERID4_bp 4 /* JTAG User ID bit 4 position. */ -#define NVM_FUSES_JTAGUSERID5_bm (1<<5) /* JTAG User ID bit 5 mask. */ -#define NVM_FUSES_JTAGUSERID5_bp 5 /* JTAG User ID bit 5 position. */ -#define NVM_FUSES_JTAGUSERID6_bm (1<<6) /* JTAG User ID bit 6 mask. */ -#define NVM_FUSES_JTAGUSERID6_bp 6 /* JTAG User ID bit 6 position. */ -#define NVM_FUSES_JTAGUSERID7_bm (1<<7) /* JTAG User ID bit 7 mask. */ -#define NVM_FUSES_JTAGUSERID7_bp 7 /* JTAG User ID bit 7 position. */ - - -/* NVM_FUSES.FUSEBYTE1 bit masks and bit positions */ -#define NVM_FUSES_WDWP_gm 0xF0 /* Watchdog Window Timeout Period group mask. */ -#define NVM_FUSES_WDWP_gp 4 /* Watchdog Window Timeout Period group position. */ -#define NVM_FUSES_WDWP0_bm (1<<4) /* Watchdog Window Timeout Period bit 0 mask. */ -#define NVM_FUSES_WDWP0_bp 4 /* Watchdog Window Timeout Period bit 0 position. */ -#define NVM_FUSES_WDWP1_bm (1<<5) /* Watchdog Window Timeout Period bit 1 mask. */ -#define NVM_FUSES_WDWP1_bp 5 /* Watchdog Window Timeout Period bit 1 position. */ -#define NVM_FUSES_WDWP2_bm (1<<6) /* Watchdog Window Timeout Period bit 2 mask. */ -#define NVM_FUSES_WDWP2_bp 6 /* Watchdog Window Timeout Period bit 2 position. */ -#define NVM_FUSES_WDWP3_bm (1<<7) /* Watchdog Window Timeout Period bit 3 mask. */ -#define NVM_FUSES_WDWP3_bp 7 /* Watchdog Window Timeout Period bit 3 position. */ - -#define NVM_FUSES_WDP_gm 0x0F /* Watchdog Timeout Period group mask. */ -#define NVM_FUSES_WDP_gp 0 /* Watchdog Timeout Period group position. */ -#define NVM_FUSES_WDP0_bm (1<<0) /* Watchdog Timeout Period bit 0 mask. */ -#define NVM_FUSES_WDP0_bp 0 /* Watchdog Timeout Period bit 0 position. */ -#define NVM_FUSES_WDP1_bm (1<<1) /* Watchdog Timeout Period bit 1 mask. */ -#define NVM_FUSES_WDP1_bp 1 /* Watchdog Timeout Period bit 1 position. */ -#define NVM_FUSES_WDP2_bm (1<<2) /* Watchdog Timeout Period bit 2 mask. */ -#define NVM_FUSES_WDP2_bp 2 /* Watchdog Timeout Period bit 2 position. */ -#define NVM_FUSES_WDP3_bm (1<<3) /* Watchdog Timeout Period bit 3 mask. */ -#define NVM_FUSES_WDP3_bp 3 /* Watchdog Timeout Period bit 3 position. */ - - -/* NVM_FUSES.FUSEBYTE2 bit masks and bit positions */ -#define NVM_FUSES_DVSDON_bm 0x80 /* Spike Detector Enable bit mask. */ -#define NVM_FUSES_DVSDON_bp 7 /* Spike Detector Enable bit position. */ - -#define NVM_FUSES_BOOTRST_bm 0x40 /* Boot Loader Section Reset Vector bit mask. */ -#define NVM_FUSES_BOOTRST_bp 6 /* Boot Loader Section Reset Vector bit position. */ - -#define NVM_FUSES_BODACT_gm 0x0C /* BOD Operation in Active Mode group mask. */ -#define NVM_FUSES_BODACT_gp 2 /* BOD Operation in Active Mode group position. */ -#define NVM_FUSES_BODACT0_bm (1<<2) /* BOD Operation in Active Mode bit 0 mask. */ -#define NVM_FUSES_BODACT0_bp 2 /* BOD Operation in Active Mode bit 0 position. */ -#define NVM_FUSES_BODACT1_bm (1<<3) /* BOD Operation in Active Mode bit 1 mask. */ -#define NVM_FUSES_BODACT1_bp 3 /* BOD Operation in Active Mode bit 1 position. */ - -#define NVM_FUSES_BODPD_gm 0x03 /* BOD Operation in Power-Down Mode group mask. */ -#define NVM_FUSES_BODPD_gp 0 /* BOD Operation in Power-Down Mode group position. */ -#define NVM_FUSES_BODPD0_bm (1<<0) /* BOD Operation in Power-Down Mode bit 0 mask. */ -#define NVM_FUSES_BODPD0_bp 0 /* BOD Operation in Power-Down Mode bit 0 position. */ -#define NVM_FUSES_BODPD1_bm (1<<1) /* BOD Operation in Power-Down Mode bit 1 mask. */ -#define NVM_FUSES_BODPD1_bp 1 /* BOD Operation in Power-Down Mode bit 1 position. */ - - -/* NVM_FUSES.FUSEBYTE4 bit masks and bit positions */ -#define NVM_FUSES_SUT_gm 0x0C /* Start-up Time group mask. */ -#define NVM_FUSES_SUT_gp 2 /* Start-up Time group position. */ -#define NVM_FUSES_SUT0_bm (1<<2) /* Start-up Time bit 0 mask. */ -#define NVM_FUSES_SUT0_bp 2 /* Start-up Time bit 0 position. */ -#define NVM_FUSES_SUT1_bm (1<<3) /* Start-up Time bit 1 mask. */ -#define NVM_FUSES_SUT1_bp 3 /* Start-up Time bit 1 position. */ - -#define NVM_FUSES_WDLOCK_bm 0x02 /* Watchdog Timer Lock bit mask. */ -#define NVM_FUSES_WDLOCK_bp 1 /* Watchdog Timer Lock bit position. */ - -#define NVM_FUSES_JTAGEN_bm 0x01 /* JTAG Interface Enable bit mask. */ -#define NVM_FUSES_JTAGEN_bp 0 /* JTAG Interface Enable bit position. */ - - -/* NVM_FUSES.FUSEBYTE5 bit masks and bit positions */ -#define NVM_FUSES_EESAVE_bm 0x08 /* Preserve EEPROM Through Chip Erase bit mask. */ -#define NVM_FUSES_EESAVE_bp 3 /* Preserve EEPROM Through Chip Erase bit position. */ - -#define NVM_FUSES_BODLVL_gm 0x07 /* Brown Out Detection Voltage Level group mask. */ -#define NVM_FUSES_BODLVL_gp 0 /* Brown Out Detection Voltage Level group position. */ -#define NVM_FUSES_BODLVL0_bm (1<<0) /* Brown Out Detection Voltage Level bit 0 mask. */ -#define NVM_FUSES_BODLVL0_bp 0 /* Brown Out Detection Voltage Level bit 0 position. */ -#define NVM_FUSES_BODLVL1_bm (1<<1) /* Brown Out Detection Voltage Level bit 1 mask. */ -#define NVM_FUSES_BODLVL1_bp 1 /* Brown Out Detection Voltage Level bit 1 position. */ -#define NVM_FUSES_BODLVL2_bm (1<<2) /* Brown Out Detection Voltage Level bit 2 mask. */ -#define NVM_FUSES_BODLVL2_bp 2 /* Brown Out Detection Voltage Level bit 2 position. */ - - -/* AC - Analog Comparator */ -/* AC.AC0CTRL bit masks and bit positions */ -#define AC_INTMODE_gm 0xC0 /* Interrupt Mode group mask. */ -#define AC_INTMODE_gp 6 /* Interrupt Mode group position. */ -#define AC_INTMODE0_bm (1<<6) /* Interrupt Mode bit 0 mask. */ -#define AC_INTMODE0_bp 6 /* Interrupt Mode bit 0 position. */ -#define AC_INTMODE1_bm (1<<7) /* Interrupt Mode bit 1 mask. */ -#define AC_INTMODE1_bp 7 /* Interrupt Mode bit 1 position. */ - -#define AC_INTLVL_gm 0x30 /* Interrupt Level group mask. */ -#define AC_INTLVL_gp 4 /* Interrupt Level group position. */ -#define AC_INTLVL0_bm (1<<4) /* Interrupt Level bit 0 mask. */ -#define AC_INTLVL0_bp 4 /* Interrupt Level bit 0 position. */ -#define AC_INTLVL1_bm (1<<5) /* Interrupt Level bit 1 mask. */ -#define AC_INTLVL1_bp 5 /* Interrupt Level bit 1 position. */ - -#define AC_HSMODE_bm 0x08 /* High-speed Mode bit mask. */ -#define AC_HSMODE_bp 3 /* High-speed Mode bit position. */ - -#define AC_HYSMODE_gm 0x06 /* Hysteresis Mode group mask. */ -#define AC_HYSMODE_gp 1 /* Hysteresis Mode group position. */ -#define AC_HYSMODE0_bm (1<<1) /* Hysteresis Mode bit 0 mask. */ -#define AC_HYSMODE0_bp 1 /* Hysteresis Mode bit 0 position. */ -#define AC_HYSMODE1_bm (1<<2) /* Hysteresis Mode bit 1 mask. */ -#define AC_HYSMODE1_bp 2 /* Hysteresis Mode bit 1 position. */ - -#define AC_ENABLE_bm 0x01 /* Enable bit mask. */ -#define AC_ENABLE_bp 0 /* Enable bit position. */ - - -/* AC.AC1CTRL bit masks and bit positions */ -/* AC_INTMODE_gm Predefined. */ -/* AC_INTMODE_gp Predefined. */ -/* AC_INTMODE0_bm Predefined. */ -/* AC_INTMODE0_bp Predefined. */ -/* AC_INTMODE1_bm Predefined. */ -/* AC_INTMODE1_bp Predefined. */ - -/* AC_INTLVL_gm Predefined. */ -/* AC_INTLVL_gp Predefined. */ -/* AC_INTLVL0_bm Predefined. */ -/* AC_INTLVL0_bp Predefined. */ -/* AC_INTLVL1_bm Predefined. */ -/* AC_INTLVL1_bp Predefined. */ - -/* AC_HSMODE_bm Predefined. */ -/* AC_HSMODE_bp Predefined. */ - -/* AC_HYSMODE_gm Predefined. */ -/* AC_HYSMODE_gp Predefined. */ -/* AC_HYSMODE0_bm Predefined. */ -/* AC_HYSMODE0_bp Predefined. */ -/* AC_HYSMODE1_bm Predefined. */ -/* AC_HYSMODE1_bp Predefined. */ - -/* AC_ENABLE_bm Predefined. */ -/* AC_ENABLE_bp Predefined. */ - - -/* AC.AC0MUXCTRL bit masks and bit positions */ -#define AC_MUXPOS_gm 0x38 /* MUX Positive Input group mask. */ -#define AC_MUXPOS_gp 3 /* MUX Positive Input group position. */ -#define AC_MUXPOS0_bm (1<<3) /* MUX Positive Input bit 0 mask. */ -#define AC_MUXPOS0_bp 3 /* MUX Positive Input bit 0 position. */ -#define AC_MUXPOS1_bm (1<<4) /* MUX Positive Input bit 1 mask. */ -#define AC_MUXPOS1_bp 4 /* MUX Positive Input bit 1 position. */ -#define AC_MUXPOS2_bm (1<<5) /* MUX Positive Input bit 2 mask. */ -#define AC_MUXPOS2_bp 5 /* MUX Positive Input bit 2 position. */ - -#define AC_MUXNEG_gm 0x07 /* MUX Negative Input group mask. */ -#define AC_MUXNEG_gp 0 /* MUX Negative Input group position. */ -#define AC_MUXNEG0_bm (1<<0) /* MUX Negative Input bit 0 mask. */ -#define AC_MUXNEG0_bp 0 /* MUX Negative Input bit 0 position. */ -#define AC_MUXNEG1_bm (1<<1) /* MUX Negative Input bit 1 mask. */ -#define AC_MUXNEG1_bp 1 /* MUX Negative Input bit 1 position. */ -#define AC_MUXNEG2_bm (1<<2) /* MUX Negative Input bit 2 mask. */ -#define AC_MUXNEG2_bp 2 /* MUX Negative Input bit 2 position. */ - - -/* AC.AC1MUXCTRL bit masks and bit positions */ -/* AC_MUXPOS_gm Predefined. */ -/* AC_MUXPOS_gp Predefined. */ -/* AC_MUXPOS0_bm Predefined. */ -/* AC_MUXPOS0_bp Predefined. */ -/* AC_MUXPOS1_bm Predefined. */ -/* AC_MUXPOS1_bp Predefined. */ -/* AC_MUXPOS2_bm Predefined. */ -/* AC_MUXPOS2_bp Predefined. */ - -/* AC_MUXNEG_gm Predefined. */ -/* AC_MUXNEG_gp Predefined. */ -/* AC_MUXNEG0_bm Predefined. */ -/* AC_MUXNEG0_bp Predefined. */ -/* AC_MUXNEG1_bm Predefined. */ -/* AC_MUXNEG1_bp Predefined. */ -/* AC_MUXNEG2_bm Predefined. */ -/* AC_MUXNEG2_bp Predefined. */ - - -/* AC.CTRLA bit masks and bit positions */ -#define AC_AC0OUT_bm 0x01 /* Comparator 0 Output Enable bit mask. */ -#define AC_AC0OUT_bp 0 /* Comparator 0 Output Enable bit position. */ - - -/* AC.CTRLB bit masks and bit positions */ -#define AC_SCALEFAC_gm 0x3F /* VCC Voltage Scaler Factor group mask. */ -#define AC_SCALEFAC_gp 0 /* VCC Voltage Scaler Factor group position. */ -#define AC_SCALEFAC0_bm (1<<0) /* VCC Voltage Scaler Factor bit 0 mask. */ -#define AC_SCALEFAC0_bp 0 /* VCC Voltage Scaler Factor bit 0 position. */ -#define AC_SCALEFAC1_bm (1<<1) /* VCC Voltage Scaler Factor bit 1 mask. */ -#define AC_SCALEFAC1_bp 1 /* VCC Voltage Scaler Factor bit 1 position. */ -#define AC_SCALEFAC2_bm (1<<2) /* VCC Voltage Scaler Factor bit 2 mask. */ -#define AC_SCALEFAC2_bp 2 /* VCC Voltage Scaler Factor bit 2 position. */ -#define AC_SCALEFAC3_bm (1<<3) /* VCC Voltage Scaler Factor bit 3 mask. */ -#define AC_SCALEFAC3_bp 3 /* VCC Voltage Scaler Factor bit 3 position. */ -#define AC_SCALEFAC4_bm (1<<4) /* VCC Voltage Scaler Factor bit 4 mask. */ -#define AC_SCALEFAC4_bp 4 /* VCC Voltage Scaler Factor bit 4 position. */ -#define AC_SCALEFAC5_bm (1<<5) /* VCC Voltage Scaler Factor bit 5 mask. */ -#define AC_SCALEFAC5_bp 5 /* VCC Voltage Scaler Factor bit 5 position. */ - - -/* AC.WINCTRL bit masks and bit positions */ -#define AC_WEN_bm 0x10 /* Window Mode Enable bit mask. */ -#define AC_WEN_bp 4 /* Window Mode Enable bit position. */ - -#define AC_WINTMODE_gm 0x0C /* Window Interrupt Mode group mask. */ -#define AC_WINTMODE_gp 2 /* Window Interrupt Mode group position. */ -#define AC_WINTMODE0_bm (1<<2) /* Window Interrupt Mode bit 0 mask. */ -#define AC_WINTMODE0_bp 2 /* Window Interrupt Mode bit 0 position. */ -#define AC_WINTMODE1_bm (1<<3) /* Window Interrupt Mode bit 1 mask. */ -#define AC_WINTMODE1_bp 3 /* Window Interrupt Mode bit 1 position. */ - -#define AC_WINTLVL_gm 0x03 /* Window Interrupt Level group mask. */ -#define AC_WINTLVL_gp 0 /* Window Interrupt Level group position. */ -#define AC_WINTLVL0_bm (1<<0) /* Window Interrupt Level bit 0 mask. */ -#define AC_WINTLVL0_bp 0 /* Window Interrupt Level bit 0 position. */ -#define AC_WINTLVL1_bm (1<<1) /* Window Interrupt Level bit 1 mask. */ -#define AC_WINTLVL1_bp 1 /* Window Interrupt Level bit 1 position. */ - - -/* AC.STATUS bit masks and bit positions */ -#define AC_WSTATE_gm 0xC0 /* Window Mode State group mask. */ -#define AC_WSTATE_gp 6 /* Window Mode State group position. */ -#define AC_WSTATE0_bm (1<<6) /* Window Mode State bit 0 mask. */ -#define AC_WSTATE0_bp 6 /* Window Mode State bit 0 position. */ -#define AC_WSTATE1_bm (1<<7) /* Window Mode State bit 1 mask. */ -#define AC_WSTATE1_bp 7 /* Window Mode State bit 1 position. */ - -#define AC_AC1STATE_bm 0x20 /* Comparator 1 State bit mask. */ -#define AC_AC1STATE_bp 5 /* Comparator 1 State bit position. */ - -#define AC_AC0STATE_bm 0x10 /* Comparator 0 State bit mask. */ -#define AC_AC0STATE_bp 4 /* Comparator 0 State bit position. */ - -#define AC_WIF_bm 0x04 /* Window Mode Interrupt Flag bit mask. */ -#define AC_WIF_bp 2 /* Window Mode Interrupt Flag bit position. */ - -#define AC_AC1IF_bm 0x02 /* Comparator 1 Interrupt Flag bit mask. */ -#define AC_AC1IF_bp 1 /* Comparator 1 Interrupt Flag bit position. */ - -#define AC_AC0IF_bm 0x01 /* Comparator 0 Interrupt Flag bit mask. */ -#define AC_AC0IF_bp 0 /* Comparator 0 Interrupt Flag bit position. */ - - -/* ADC - Analog/Digital Converter */ -/* ADC_CH.CTRL bit masks and bit positions */ -#define ADC_CH_START_bm 0x80 /* Channel Start Conversion bit mask. */ -#define ADC_CH_START_bp 7 /* Channel Start Conversion bit position. */ - -#define ADC_CH_GAINFAC_gm 0x1C /* Gain Factor group mask. */ -#define ADC_CH_GAINFAC_gp 2 /* Gain Factor group position. */ -#define ADC_CH_GAINFAC0_bm (1<<2) /* Gain Factor bit 0 mask. */ -#define ADC_CH_GAINFAC0_bp 2 /* Gain Factor bit 0 position. */ -#define ADC_CH_GAINFAC1_bm (1<<3) /* Gain Factor bit 1 mask. */ -#define ADC_CH_GAINFAC1_bp 3 /* Gain Factor bit 1 position. */ -#define ADC_CH_GAINFAC2_bm (1<<4) /* Gain Factor bit 2 mask. */ -#define ADC_CH_GAINFAC2_bp 4 /* Gain Factor bit 2 position. */ - -#define ADC_CH_INPUTMODE_gm 0x03 /* Input Mode Select group mask. */ -#define ADC_CH_INPUTMODE_gp 0 /* Input Mode Select group position. */ -#define ADC_CH_INPUTMODE0_bm (1<<0) /* Input Mode Select bit 0 mask. */ -#define ADC_CH_INPUTMODE0_bp 0 /* Input Mode Select bit 0 position. */ -#define ADC_CH_INPUTMODE1_bm (1<<1) /* Input Mode Select bit 1 mask. */ -#define ADC_CH_INPUTMODE1_bp 1 /* Input Mode Select bit 1 position. */ - - -/* ADC_CH.MUXCTRL bit masks and bit positions */ -#define ADC_CH_MUXPOS_gm 0x78 /* Positive Input Select group mask. */ -#define ADC_CH_MUXPOS_gp 3 /* Positive Input Select group position. */ -#define ADC_CH_MUXPOS0_bm (1<<3) /* Positive Input Select bit 0 mask. */ -#define ADC_CH_MUXPOS0_bp 3 /* Positive Input Select bit 0 position. */ -#define ADC_CH_MUXPOS1_bm (1<<4) /* Positive Input Select bit 1 mask. */ -#define ADC_CH_MUXPOS1_bp 4 /* Positive Input Select bit 1 position. */ -#define ADC_CH_MUXPOS2_bm (1<<5) /* Positive Input Select bit 2 mask. */ -#define ADC_CH_MUXPOS2_bp 5 /* Positive Input Select bit 2 position. */ -#define ADC_CH_MUXPOS3_bm (1<<6) /* Positive Input Select bit 3 mask. */ -#define ADC_CH_MUXPOS3_bp 6 /* Positive Input Select bit 3 position. */ - -#define ADC_CH_MUXINT_gm 0x78 /* Internal Input Select group mask. */ -#define ADC_CH_MUXINT_gp 3 /* Internal Input Select group position. */ -#define ADC_CH_MUXINT0_bm (1<<3) /* Internal Input Select bit 0 mask. */ -#define ADC_CH_MUXINT0_bp 3 /* Internal Input Select bit 0 position. */ -#define ADC_CH_MUXINT1_bm (1<<4) /* Internal Input Select bit 1 mask. */ -#define ADC_CH_MUXINT1_bp 4 /* Internal Input Select bit 1 position. */ -#define ADC_CH_MUXINT2_bm (1<<5) /* Internal Input Select bit 2 mask. */ -#define ADC_CH_MUXINT2_bp 5 /* Internal Input Select bit 2 position. */ -#define ADC_CH_MUXINT3_bm (1<<6) /* Internal Input Select bit 3 mask. */ -#define ADC_CH_MUXINT3_bp 6 /* Internal Input Select bit 3 position. */ - -#define ADC_CH_MUXNEG_gm 0x03 /* Negative Input Select group mask. */ -#define ADC_CH_MUXNEG_gp 0 /* Negative Input Select group position. */ -#define ADC_CH_MUXNEG0_bm (1<<0) /* Negative Input Select bit 0 mask. */ -#define ADC_CH_MUXNEG0_bp 0 /* Negative Input Select bit 0 position. */ -#define ADC_CH_MUXNEG1_bm (1<<1) /* Negative Input Select bit 1 mask. */ -#define ADC_CH_MUXNEG1_bp 1 /* Negative Input Select bit 1 position. */ - - -/* ADC_CH.INTCTRL bit masks and bit positions */ -#define ADC_CH_INTMODE_gm 0x0C /* Interrupt Mode group mask. */ -#define ADC_CH_INTMODE_gp 2 /* Interrupt Mode group position. */ -#define ADC_CH_INTMODE0_bm (1<<2) /* Interrupt Mode bit 0 mask. */ -#define ADC_CH_INTMODE0_bp 2 /* Interrupt Mode bit 0 position. */ -#define ADC_CH_INTMODE1_bm (1<<3) /* Interrupt Mode bit 1 mask. */ -#define ADC_CH_INTMODE1_bp 3 /* Interrupt Mode bit 1 position. */ - -#define ADC_CH_INTLVL_gm 0x03 /* Interrupt Level group mask. */ -#define ADC_CH_INTLVL_gp 0 /* Interrupt Level group position. */ -#define ADC_CH_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */ -#define ADC_CH_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */ -#define ADC_CH_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ -#define ADC_CH_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */ - - -/* ADC_CH.INTFLAGS bit masks and bit positions */ -#define ADC_CH_CHIF_bm 0x01 /* Channel Interrupt Flag bit mask. */ -#define ADC_CH_CHIF_bp 0 /* Channel Interrupt Flag bit position. */ - - -/* ADC.CTRLA bit masks and bit positions */ -#define ADC_DMASEL_gm 0xC0 /* DMA Selection group mask. */ -#define ADC_DMASEL_gp 6 /* DMA Selection group position. */ -#define ADC_DMASEL0_bm (1<<6) /* DMA Selection bit 0 mask. */ -#define ADC_DMASEL0_bp 6 /* DMA Selection bit 0 position. */ -#define ADC_DMASEL1_bm (1<<7) /* DMA Selection bit 1 mask. */ -#define ADC_DMASEL1_bp 7 /* DMA Selection bit 1 position. */ - -#define ADC_CH3START_bm 0x20 /* Channel 3 Start Conversion bit mask. */ -#define ADC_CH3START_bp 5 /* Channel 3 Start Conversion bit position. */ - -#define ADC_CH2START_bm 0x10 /* Channel 2 Start Conversion bit mask. */ -#define ADC_CH2START_bp 4 /* Channel 2 Start Conversion bit position. */ - -#define ADC_CH1START_bm 0x08 /* Channel 1 Start Conversion bit mask. */ -#define ADC_CH1START_bp 3 /* Channel 1 Start Conversion bit position. */ - -#define ADC_CH0START_bm 0x04 /* Channel 0 Start Conversion bit mask. */ -#define ADC_CH0START_bp 2 /* Channel 0 Start Conversion bit position. */ - -#define ADC_FLUSH_bm 0x02 /* Flush Pipeline bit mask. */ -#define ADC_FLUSH_bp 1 /* Flush Pipeline bit position. */ - -#define ADC_ENABLE_bm 0x01 /* Enable ADC bit mask. */ -#define ADC_ENABLE_bp 0 /* Enable ADC bit position. */ - - -/* ADC.CTRLB bit masks and bit positions */ -#define ADC_CONMODE_bm 0x10 /* Conversion Mode bit mask. */ -#define ADC_CONMODE_bp 4 /* Conversion Mode bit position. */ - -#define ADC_FREERUN_bm 0x08 /* Free Running Mode Enable bit mask. */ -#define ADC_FREERUN_bp 3 /* Free Running Mode Enable bit position. */ - -#define ADC_RESOLUTION_gm 0x06 /* Result Resolution group mask. */ -#define ADC_RESOLUTION_gp 1 /* Result Resolution group position. */ -#define ADC_RESOLUTION0_bm (1<<1) /* Result Resolution bit 0 mask. */ -#define ADC_RESOLUTION0_bp 1 /* Result Resolution bit 0 position. */ -#define ADC_RESOLUTION1_bm (1<<2) /* Result Resolution bit 1 mask. */ -#define ADC_RESOLUTION1_bp 2 /* Result Resolution bit 1 position. */ - - -/* ADC.REFCTRL bit masks and bit positions */ -#define ADC_REFSEL_gm 0x30 /* Reference Selection group mask. */ -#define ADC_REFSEL_gp 4 /* Reference Selection group position. */ -#define ADC_REFSEL0_bm (1<<4) /* Reference Selection bit 0 mask. */ -#define ADC_REFSEL0_bp 4 /* Reference Selection bit 0 position. */ -#define ADC_REFSEL1_bm (1<<5) /* Reference Selection bit 1 mask. */ -#define ADC_REFSEL1_bp 5 /* Reference Selection bit 1 position. */ - -#define ADC_BANDGAP_bm 0x02 /* Bandgap enable bit mask. */ -#define ADC_BANDGAP_bp 1 /* Bandgap enable bit position. */ - -#define ADC_TEMPREF_bm 0x01 /* Temperature Reference Enable bit mask. */ -#define ADC_TEMPREF_bp 0 /* Temperature Reference Enable bit position. */ - - -/* ADC.EVCTRL bit masks and bit positions */ -#define ADC_SWEEP_gm 0xC0 /* Channel Sweep Selection group mask. */ -#define ADC_SWEEP_gp 6 /* Channel Sweep Selection group position. */ -#define ADC_SWEEP0_bm (1<<6) /* Channel Sweep Selection bit 0 mask. */ -#define ADC_SWEEP0_bp 6 /* Channel Sweep Selection bit 0 position. */ -#define ADC_SWEEP1_bm (1<<7) /* Channel Sweep Selection bit 1 mask. */ -#define ADC_SWEEP1_bp 7 /* Channel Sweep Selection bit 1 position. */ - -#define ADC_EVSEL_gm 0x38 /* Event Input Select group mask. */ -#define ADC_EVSEL_gp 3 /* Event Input Select group position. */ -#define ADC_EVSEL0_bm (1<<3) /* Event Input Select bit 0 mask. */ -#define ADC_EVSEL0_bp 3 /* Event Input Select bit 0 position. */ -#define ADC_EVSEL1_bm (1<<4) /* Event Input Select bit 1 mask. */ -#define ADC_EVSEL1_bp 4 /* Event Input Select bit 1 position. */ -#define ADC_EVSEL2_bm (1<<5) /* Event Input Select bit 2 mask. */ -#define ADC_EVSEL2_bp 5 /* Event Input Select bit 2 position. */ - -#define ADC_EVACT_gm 0x07 /* Event Action Select group mask. */ -#define ADC_EVACT_gp 0 /* Event Action Select group position. */ -#define ADC_EVACT0_bm (1<<0) /* Event Action Select bit 0 mask. */ -#define ADC_EVACT0_bp 0 /* Event Action Select bit 0 position. */ -#define ADC_EVACT1_bm (1<<1) /* Event Action Select bit 1 mask. */ -#define ADC_EVACT1_bp 1 /* Event Action Select bit 1 position. */ -#define ADC_EVACT2_bm (1<<2) /* Event Action Select bit 2 mask. */ -#define ADC_EVACT2_bp 2 /* Event Action Select bit 2 position. */ - - -/* ADC.PRESCALER bit masks and bit positions */ -#define ADC_PRESCALER_gm 0x07 /* Clock Prescaler Selection group mask. */ -#define ADC_PRESCALER_gp 0 /* Clock Prescaler Selection group position. */ -#define ADC_PRESCALER0_bm (1<<0) /* Clock Prescaler Selection bit 0 mask. */ -#define ADC_PRESCALER0_bp 0 /* Clock Prescaler Selection bit 0 position. */ -#define ADC_PRESCALER1_bm (1<<1) /* Clock Prescaler Selection bit 1 mask. */ -#define ADC_PRESCALER1_bp 1 /* Clock Prescaler Selection bit 1 position. */ -#define ADC_PRESCALER2_bm (1<<2) /* Clock Prescaler Selection bit 2 mask. */ -#define ADC_PRESCALER2_bp 2 /* Clock Prescaler Selection bit 2 position. */ - - -/* ADC.INTFLAGS bit masks and bit positions */ -#define ADC_CH3IF_bm 0x08 /* Channel 3 Interrupt Flag bit mask. */ -#define ADC_CH3IF_bp 3 /* Channel 3 Interrupt Flag bit position. */ - -#define ADC_CH2IF_bm 0x04 /* Channel 2 Interrupt Flag bit mask. */ -#define ADC_CH2IF_bp 2 /* Channel 2 Interrupt Flag bit position. */ - -#define ADC_CH1IF_bm 0x02 /* Channel 1 Interrupt Flag bit mask. */ -#define ADC_CH1IF_bp 1 /* Channel 1 Interrupt Flag bit position. */ - -#define ADC_CH0IF_bm 0x01 /* Channel 0 Interrupt Flag bit mask. */ -#define ADC_CH0IF_bp 0 /* Channel 0 Interrupt Flag bit position. */ - - -/* DAC - Digital/Analog Converter */ -/* DAC.CTRLA bit masks and bit positions */ -#define DAC_IDOEN_bm 0x10 /* Internal Output Enable bit mask. */ -#define DAC_IDOEN_bp 4 /* Internal Output Enable bit position. */ - -#define DAC_CH1EN_bm 0x08 /* Channel 1 Output Enable bit mask. */ -#define DAC_CH1EN_bp 3 /* Channel 1 Output Enable bit position. */ - -#define DAC_CH0EN_bm 0x04 /* Channel 0 Output Enable bit mask. */ -#define DAC_CH0EN_bp 2 /* Channel 0 Output Enable bit position. */ - -#define DAC_LPMODE_bm 0x02 /* Low Power Mode bit mask. */ -#define DAC_LPMODE_bp 1 /* Low Power Mode bit position. */ - -#define DAC_ENABLE_bm 0x01 /* Enable bit mask. */ -#define DAC_ENABLE_bp 0 /* Enable bit position. */ - - -/* DAC.CTRLB bit masks and bit positions */ -#define DAC_CHSEL_gm 0x60 /* Channel Select group mask. */ -#define DAC_CHSEL_gp 5 /* Channel Select group position. */ -#define DAC_CHSEL0_bm (1<<5) /* Channel Select bit 0 mask. */ -#define DAC_CHSEL0_bp 5 /* Channel Select bit 0 position. */ -#define DAC_CHSEL1_bm (1<<6) /* Channel Select bit 1 mask. */ -#define DAC_CHSEL1_bp 6 /* Channel Select bit 1 position. */ - -#define DAC_CH1TRIG_bm 0x02 /* Channel 1 Event Trig Enable bit mask. */ -#define DAC_CH1TRIG_bp 1 /* Channel 1 Event Trig Enable bit position. */ - -#define DAC_CH0TRIG_bm 0x01 /* Channel 0 Event Trig Enable bit mask. */ -#define DAC_CH0TRIG_bp 0 /* Channel 0 Event Trig Enable bit position. */ - - -/* DAC.CTRLC bit masks and bit positions */ -#define DAC_REFSEL_gm 0x18 /* Reference Select group mask. */ -#define DAC_REFSEL_gp 3 /* Reference Select group position. */ -#define DAC_REFSEL0_bm (1<<3) /* Reference Select bit 0 mask. */ -#define DAC_REFSEL0_bp 3 /* Reference Select bit 0 position. */ -#define DAC_REFSEL1_bm (1<<4) /* Reference Select bit 1 mask. */ -#define DAC_REFSEL1_bp 4 /* Reference Select bit 1 position. */ - -#define DAC_LEFTADJ_bm 0x01 /* Left-adjust Result bit mask. */ -#define DAC_LEFTADJ_bp 0 /* Left-adjust Result bit position. */ - - -/* DAC.EVCTRL bit masks and bit positions */ -#define DAC_EVSEL_gm 0x07 /* Event Input Selection group mask. */ -#define DAC_EVSEL_gp 0 /* Event Input Selection group position. */ -#define DAC_EVSEL0_bm (1<<0) /* Event Input Selection bit 0 mask. */ -#define DAC_EVSEL0_bp 0 /* Event Input Selection bit 0 position. */ -#define DAC_EVSEL1_bm (1<<1) /* Event Input Selection bit 1 mask. */ -#define DAC_EVSEL1_bp 1 /* Event Input Selection bit 1 position. */ -#define DAC_EVSEL2_bm (1<<2) /* Event Input Selection bit 2 mask. */ -#define DAC_EVSEL2_bp 2 /* Event Input Selection bit 2 position. */ - - -/* DAC.TIMCTRL bit masks and bit positions */ -#define DAC_CONINTVAL_gm 0x70 /* Conversion Intercal group mask. */ -#define DAC_CONINTVAL_gp 4 /* Conversion Intercal group position. */ -#define DAC_CONINTVAL0_bm (1<<4) /* Conversion Intercal bit 0 mask. */ -#define DAC_CONINTVAL0_bp 4 /* Conversion Intercal bit 0 position. */ -#define DAC_CONINTVAL1_bm (1<<5) /* Conversion Intercal bit 1 mask. */ -#define DAC_CONINTVAL1_bp 5 /* Conversion Intercal bit 1 position. */ -#define DAC_CONINTVAL2_bm (1<<6) /* Conversion Intercal bit 2 mask. */ -#define DAC_CONINTVAL2_bp 6 /* Conversion Intercal bit 2 position. */ - -#define DAC_REFRESH_gm 0x0F /* Refresh Timing Control group mask. */ -#define DAC_REFRESH_gp 0 /* Refresh Timing Control group position. */ -#define DAC_REFRESH0_bm (1<<0) /* Refresh Timing Control bit 0 mask. */ -#define DAC_REFRESH0_bp 0 /* Refresh Timing Control bit 0 position. */ -#define DAC_REFRESH1_bm (1<<1) /* Refresh Timing Control bit 1 mask. */ -#define DAC_REFRESH1_bp 1 /* Refresh Timing Control bit 1 position. */ -#define DAC_REFRESH2_bm (1<<2) /* Refresh Timing Control bit 2 mask. */ -#define DAC_REFRESH2_bp 2 /* Refresh Timing Control bit 2 position. */ -#define DAC_REFRESH3_bm (1<<3) /* Refresh Timing Control bit 3 mask. */ -#define DAC_REFRESH3_bp 3 /* Refresh Timing Control bit 3 position. */ - - -/* DAC.STATUS bit masks and bit positions */ -#define DAC_CH1DRE_bm 0x02 /* Channel 1 Data Register Empty bit mask. */ -#define DAC_CH1DRE_bp 1 /* Channel 1 Data Register Empty bit position. */ - -#define DAC_CH0DRE_bm 0x01 /* Channel 0 Data Register Empty bit mask. */ -#define DAC_CH0DRE_bp 0 /* Channel 0 Data Register Empty bit position. */ - - -/* RTC - Real-Time Clounter */ -/* RTC.CTRL bit masks and bit positions */ -#define RTC_PRESCALER_gm 0x07 /* Prescaling Factor group mask. */ -#define RTC_PRESCALER_gp 0 /* Prescaling Factor group position. */ -#define RTC_PRESCALER0_bm (1<<0) /* Prescaling Factor bit 0 mask. */ -#define RTC_PRESCALER0_bp 0 /* Prescaling Factor bit 0 position. */ -#define RTC_PRESCALER1_bm (1<<1) /* Prescaling Factor bit 1 mask. */ -#define RTC_PRESCALER1_bp 1 /* Prescaling Factor bit 1 position. */ -#define RTC_PRESCALER2_bm (1<<2) /* Prescaling Factor bit 2 mask. */ -#define RTC_PRESCALER2_bp 2 /* Prescaling Factor bit 2 position. */ - - -/* RTC.STATUS bit masks and bit positions */ -#define RTC_SYNCBUSY_bm 0x01 /* Synchronization Busy Flag bit mask. */ -#define RTC_SYNCBUSY_bp 0 /* Synchronization Busy Flag bit position. */ - - -/* RTC.INTCTRL bit masks and bit positions */ -#define RTC_COMPINTLVL_gm 0x0C /* Compare Match Interrupt Level group mask. */ -#define RTC_COMPINTLVL_gp 2 /* Compare Match Interrupt Level group position. */ -#define RTC_COMPINTLVL0_bm (1<<2) /* Compare Match Interrupt Level bit 0 mask. */ -#define RTC_COMPINTLVL0_bp 2 /* Compare Match Interrupt Level bit 0 position. */ -#define RTC_COMPINTLVL1_bm (1<<3) /* Compare Match Interrupt Level bit 1 mask. */ -#define RTC_COMPINTLVL1_bp 3 /* Compare Match Interrupt Level bit 1 position. */ - -#define RTC_OVFINTLVL_gm 0x03 /* Overflow Interrupt Level group mask. */ -#define RTC_OVFINTLVL_gp 0 /* Overflow Interrupt Level group position. */ -#define RTC_OVFINTLVL0_bm (1<<0) /* Overflow Interrupt Level bit 0 mask. */ -#define RTC_OVFINTLVL0_bp 0 /* Overflow Interrupt Level bit 0 position. */ -#define RTC_OVFINTLVL1_bm (1<<1) /* Overflow Interrupt Level bit 1 mask. */ -#define RTC_OVFINTLVL1_bp 1 /* Overflow Interrupt Level bit 1 position. */ - - -/* RTC.INTFLAGS bit masks and bit positions */ -#define RTC_COMPIF_bm 0x02 /* Compare Match Interrupt Flag bit mask. */ -#define RTC_COMPIF_bp 1 /* Compare Match Interrupt Flag bit position. */ - -#define RTC_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ -#define RTC_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ - - -/* EBI - External Bus Interface */ -/* EBI_CS.CTRLA bit masks and bit positions */ -#define EBI_CS_ASIZE_gm 0x7C /* Address Size group mask. */ -#define EBI_CS_ASIZE_gp 2 /* Address Size group position. */ -#define EBI_CS_ASIZE0_bm (1<<2) /* Address Size bit 0 mask. */ -#define EBI_CS_ASIZE0_bp 2 /* Address Size bit 0 position. */ -#define EBI_CS_ASIZE1_bm (1<<3) /* Address Size bit 1 mask. */ -#define EBI_CS_ASIZE1_bp 3 /* Address Size bit 1 position. */ -#define EBI_CS_ASIZE2_bm (1<<4) /* Address Size bit 2 mask. */ -#define EBI_CS_ASIZE2_bp 4 /* Address Size bit 2 position. */ -#define EBI_CS_ASIZE3_bm (1<<5) /* Address Size bit 3 mask. */ -#define EBI_CS_ASIZE3_bp 5 /* Address Size bit 3 position. */ -#define EBI_CS_ASIZE4_bm (1<<6) /* Address Size bit 4 mask. */ -#define EBI_CS_ASIZE4_bp 6 /* Address Size bit 4 position. */ - -#define EBI_CS_MODE_gm 0x03 /* Memory Mode group mask. */ -#define EBI_CS_MODE_gp 0 /* Memory Mode group position. */ -#define EBI_CS_MODE0_bm (1<<0) /* Memory Mode bit 0 mask. */ -#define EBI_CS_MODE0_bp 0 /* Memory Mode bit 0 position. */ -#define EBI_CS_MODE1_bm (1<<1) /* Memory Mode bit 1 mask. */ -#define EBI_CS_MODE1_bp 1 /* Memory Mode bit 1 position. */ - - -/* EBI_CS.CTRLB bit masks and bit positions */ -#define EBI_CS_SRWS_gm 0x07 /* SRAM Wait State Cycles group mask. */ -#define EBI_CS_SRWS_gp 0 /* SRAM Wait State Cycles group position. */ -#define EBI_CS_SRWS0_bm (1<<0) /* SRAM Wait State Cycles bit 0 mask. */ -#define EBI_CS_SRWS0_bp 0 /* SRAM Wait State Cycles bit 0 position. */ -#define EBI_CS_SRWS1_bm (1<<1) /* SRAM Wait State Cycles bit 1 mask. */ -#define EBI_CS_SRWS1_bp 1 /* SRAM Wait State Cycles bit 1 position. */ -#define EBI_CS_SRWS2_bm (1<<2) /* SRAM Wait State Cycles bit 2 mask. */ -#define EBI_CS_SRWS2_bp 2 /* SRAM Wait State Cycles bit 2 position. */ - -#define EBI_CS_SDINITDONE_bm 0x80 /* SDRAM Initialization Done bit mask. */ -#define EBI_CS_SDINITDONE_bp 7 /* SDRAM Initialization Done bit position. */ - -#define EBI_CS_SDSREN_bm 0x04 /* SDRAM Self-refresh Enable bit mask. */ -#define EBI_CS_SDSREN_bp 2 /* SDRAM Self-refresh Enable bit position. */ - -#define EBI_CS_SDMODE_gm 0x03 /* SDRAM Mode group mask. */ -#define EBI_CS_SDMODE_gp 0 /* SDRAM Mode group position. */ -#define EBI_CS_SDMODE0_bm (1<<0) /* SDRAM Mode bit 0 mask. */ -#define EBI_CS_SDMODE0_bp 0 /* SDRAM Mode bit 0 position. */ -#define EBI_CS_SDMODE1_bm (1<<1) /* SDRAM Mode bit 1 mask. */ -#define EBI_CS_SDMODE1_bp 1 /* SDRAM Mode bit 1 position. */ - - -/* EBI.CTRL bit masks and bit positions */ -#define EBI_SDDATAW_gm 0xC0 /* SDRAM Data Width Setting group mask. */ -#define EBI_SDDATAW_gp 6 /* SDRAM Data Width Setting group position. */ -#define EBI_SDDATAW0_bm (1<<6) /* SDRAM Data Width Setting bit 0 mask. */ -#define EBI_SDDATAW0_bp 6 /* SDRAM Data Width Setting bit 0 position. */ -#define EBI_SDDATAW1_bm (1<<7) /* SDRAM Data Width Setting bit 1 mask. */ -#define EBI_SDDATAW1_bp 7 /* SDRAM Data Width Setting bit 1 position. */ - -#define EBI_LPCMODE_gm 0x30 /* SRAM LPC Mode group mask. */ -#define EBI_LPCMODE_gp 4 /* SRAM LPC Mode group position. */ -#define EBI_LPCMODE0_bm (1<<4) /* SRAM LPC Mode bit 0 mask. */ -#define EBI_LPCMODE0_bp 4 /* SRAM LPC Mode bit 0 position. */ -#define EBI_LPCMODE1_bm (1<<5) /* SRAM LPC Mode bit 1 mask. */ -#define EBI_LPCMODE1_bp 5 /* SRAM LPC Mode bit 1 position. */ - -#define EBI_SRMODE_gm 0x0C /* SRAM Mode group mask. */ -#define EBI_SRMODE_gp 2 /* SRAM Mode group position. */ -#define EBI_SRMODE0_bm (1<<2) /* SRAM Mode bit 0 mask. */ -#define EBI_SRMODE0_bp 2 /* SRAM Mode bit 0 position. */ -#define EBI_SRMODE1_bm (1<<3) /* SRAM Mode bit 1 mask. */ -#define EBI_SRMODE1_bp 3 /* SRAM Mode bit 1 position. */ - -#define EBI_IFMODE_gm 0x03 /* Interface Mode group mask. */ -#define EBI_IFMODE_gp 0 /* Interface Mode group position. */ -#define EBI_IFMODE0_bm (1<<0) /* Interface Mode bit 0 mask. */ -#define EBI_IFMODE0_bp 0 /* Interface Mode bit 0 position. */ -#define EBI_IFMODE1_bm (1<<1) /* Interface Mode bit 1 mask. */ -#define EBI_IFMODE1_bp 1 /* Interface Mode bit 1 position. */ - - -/* EBI.SDRAMCTRLA bit masks and bit positions */ -#define EBI_SDCAS_bm 0x08 /* SDRAM CAS Latency Setting bit mask. */ -#define EBI_SDCAS_bp 3 /* SDRAM CAS Latency Setting bit position. */ - -#define EBI_SDROW_bm 0x04 /* SDRAM ROW Bits Setting bit mask. */ -#define EBI_SDROW_bp 2 /* SDRAM ROW Bits Setting bit position. */ - -#define EBI_SDCOL_gm 0x03 /* SDRAM Column Bits Setting group mask. */ -#define EBI_SDCOL_gp 0 /* SDRAM Column Bits Setting group position. */ -#define EBI_SDCOL0_bm (1<<0) /* SDRAM Column Bits Setting bit 0 mask. */ -#define EBI_SDCOL0_bp 0 /* SDRAM Column Bits Setting bit 0 position. */ -#define EBI_SDCOL1_bm (1<<1) /* SDRAM Column Bits Setting bit 1 mask. */ -#define EBI_SDCOL1_bp 1 /* SDRAM Column Bits Setting bit 1 position. */ - - -/* EBI.SDRAMCTRLB bit masks and bit positions */ -#define EBI_MRDLY_gm 0xC0 /* SDRAM Mode Register Delay group mask. */ -#define EBI_MRDLY_gp 6 /* SDRAM Mode Register Delay group position. */ -#define EBI_MRDLY0_bm (1<<6) /* SDRAM Mode Register Delay bit 0 mask. */ -#define EBI_MRDLY0_bp 6 /* SDRAM Mode Register Delay bit 0 position. */ -#define EBI_MRDLY1_bm (1<<7) /* SDRAM Mode Register Delay bit 1 mask. */ -#define EBI_MRDLY1_bp 7 /* SDRAM Mode Register Delay bit 1 position. */ - -#define EBI_ROWCYCDLY_gm 0x38 /* SDRAM Row Cycle Delay group mask. */ -#define EBI_ROWCYCDLY_gp 3 /* SDRAM Row Cycle Delay group position. */ -#define EBI_ROWCYCDLY0_bm (1<<3) /* SDRAM Row Cycle Delay bit 0 mask. */ -#define EBI_ROWCYCDLY0_bp 3 /* SDRAM Row Cycle Delay bit 0 position. */ -#define EBI_ROWCYCDLY1_bm (1<<4) /* SDRAM Row Cycle Delay bit 1 mask. */ -#define EBI_ROWCYCDLY1_bp 4 /* SDRAM Row Cycle Delay bit 1 position. */ -#define EBI_ROWCYCDLY2_bm (1<<5) /* SDRAM Row Cycle Delay bit 2 mask. */ -#define EBI_ROWCYCDLY2_bp 5 /* SDRAM Row Cycle Delay bit 2 position. */ - -#define EBI_RPDLY_gm 0x07 /* SDRAM Row-to-Precharge Delay group mask. */ -#define EBI_RPDLY_gp 0 /* SDRAM Row-to-Precharge Delay group position. */ -#define EBI_RPDLY0_bm (1<<0) /* SDRAM Row-to-Precharge Delay bit 0 mask. */ -#define EBI_RPDLY0_bp 0 /* SDRAM Row-to-Precharge Delay bit 0 position. */ -#define EBI_RPDLY1_bm (1<<1) /* SDRAM Row-to-Precharge Delay bit 1 mask. */ -#define EBI_RPDLY1_bp 1 /* SDRAM Row-to-Precharge Delay bit 1 position. */ -#define EBI_RPDLY2_bm (1<<2) /* SDRAM Row-to-Precharge Delay bit 2 mask. */ -#define EBI_RPDLY2_bp 2 /* SDRAM Row-to-Precharge Delay bit 2 position. */ - - -/* EBI.SDRAMCTRLC bit masks and bit positions */ -#define EBI_WRDLY_gm 0xC0 /* SDRAM Write Recovery Delay group mask. */ -#define EBI_WRDLY_gp 6 /* SDRAM Write Recovery Delay group position. */ -#define EBI_WRDLY0_bm (1<<6) /* SDRAM Write Recovery Delay bit 0 mask. */ -#define EBI_WRDLY0_bp 6 /* SDRAM Write Recovery Delay bit 0 position. */ -#define EBI_WRDLY1_bm (1<<7) /* SDRAM Write Recovery Delay bit 1 mask. */ -#define EBI_WRDLY1_bp 7 /* SDRAM Write Recovery Delay bit 1 position. */ - -#define EBI_ESRDLY_gm 0x38 /* SDRAM Exit-Self-refresh-to-Active Delay group mask. */ -#define EBI_ESRDLY_gp 3 /* SDRAM Exit-Self-refresh-to-Active Delay group position. */ -#define EBI_ESRDLY0_bm (1<<3) /* SDRAM Exit-Self-refresh-to-Active Delay bit 0 mask. */ -#define EBI_ESRDLY0_bp 3 /* SDRAM Exit-Self-refresh-to-Active Delay bit 0 position. */ -#define EBI_ESRDLY1_bm (1<<4) /* SDRAM Exit-Self-refresh-to-Active Delay bit 1 mask. */ -#define EBI_ESRDLY1_bp 4 /* SDRAM Exit-Self-refresh-to-Active Delay bit 1 position. */ -#define EBI_ESRDLY2_bm (1<<5) /* SDRAM Exit-Self-refresh-to-Active Delay bit 2 mask. */ -#define EBI_ESRDLY2_bp 5 /* SDRAM Exit-Self-refresh-to-Active Delay bit 2 position. */ - -#define EBI_ROWCOLDLY_gm 0x07 /* SDRAM Row-to-Column Delay group mask. */ -#define EBI_ROWCOLDLY_gp 0 /* SDRAM Row-to-Column Delay group position. */ -#define EBI_ROWCOLDLY0_bm (1<<0) /* SDRAM Row-to-Column Delay bit 0 mask. */ -#define EBI_ROWCOLDLY0_bp 0 /* SDRAM Row-to-Column Delay bit 0 position. */ -#define EBI_ROWCOLDLY1_bm (1<<1) /* SDRAM Row-to-Column Delay bit 1 mask. */ -#define EBI_ROWCOLDLY1_bp 1 /* SDRAM Row-to-Column Delay bit 1 position. */ -#define EBI_ROWCOLDLY2_bm (1<<2) /* SDRAM Row-to-Column Delay bit 2 mask. */ -#define EBI_ROWCOLDLY2_bp 2 /* SDRAM Row-to-Column Delay bit 2 position. */ - - -/* TWI - Two-Wire Interface */ -/* TWI_MASTER.CTRLA bit masks and bit positions */ -#define TWI_MASTER_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ -#define TWI_MASTER_INTLVL_gp 6 /* Interrupt Level group position. */ -#define TWI_MASTER_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ -#define TWI_MASTER_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ -#define TWI_MASTER_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ -#define TWI_MASTER_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ - -#define TWI_MASTER_RIEN_bm 0x20 /* Read Interrupt Enable bit mask. */ -#define TWI_MASTER_RIEN_bp 5 /* Read Interrupt Enable bit position. */ - -#define TWI_MASTER_WIEN_bm 0x10 /* Write Interrupt Enable bit mask. */ -#define TWI_MASTER_WIEN_bp 4 /* Write Interrupt Enable bit position. */ - -#define TWI_MASTER_ENABLE_bm 0x08 /* Enable TWI Master bit mask. */ -#define TWI_MASTER_ENABLE_bp 3 /* Enable TWI Master bit position. */ - - -/* TWI_MASTER.CTRLB bit masks and bit positions */ -#define TWI_MASTER_TIMEOUT_gm 0x0C /* Inactive Bus Timeout group mask. */ -#define TWI_MASTER_TIMEOUT_gp 2 /* Inactive Bus Timeout group position. */ -#define TWI_MASTER_TIMEOUT0_bm (1<<2) /* Inactive Bus Timeout bit 0 mask. */ -#define TWI_MASTER_TIMEOUT0_bp 2 /* Inactive Bus Timeout bit 0 position. */ -#define TWI_MASTER_TIMEOUT1_bm (1<<3) /* Inactive Bus Timeout bit 1 mask. */ -#define TWI_MASTER_TIMEOUT1_bp 3 /* Inactive Bus Timeout bit 1 position. */ - -#define TWI_MASTER_QCEN_bm 0x02 /* Quick Command Enable bit mask. */ -#define TWI_MASTER_QCEN_bp 1 /* Quick Command Enable bit position. */ - -#define TWI_MASTER_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ -#define TWI_MASTER_SMEN_bp 0 /* Smart Mode Enable bit position. */ - - -/* TWI_MASTER.CTRLC bit masks and bit positions */ -#define TWI_MASTER_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ -#define TWI_MASTER_ACKACT_bp 2 /* Acknowledge Action bit position. */ - -#define TWI_MASTER_CMD_gm 0x03 /* Command group mask. */ -#define TWI_MASTER_CMD_gp 0 /* Command group position. */ -#define TWI_MASTER_CMD0_bm (1<<0) /* Command bit 0 mask. */ -#define TWI_MASTER_CMD0_bp 0 /* Command bit 0 position. */ -#define TWI_MASTER_CMD1_bm (1<<1) /* Command bit 1 mask. */ -#define TWI_MASTER_CMD1_bp 1 /* Command bit 1 position. */ - - -/* TWI_MASTER.STATUS bit masks and bit positions */ -#define TWI_MASTER_RIF_bm 0x80 /* Read Interrupt Flag bit mask. */ -#define TWI_MASTER_RIF_bp 7 /* Read Interrupt Flag bit position. */ - -#define TWI_MASTER_WIF_bm 0x40 /* Write Interrupt Flag bit mask. */ -#define TWI_MASTER_WIF_bp 6 /* Write Interrupt Flag bit position. */ - -#define TWI_MASTER_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ -#define TWI_MASTER_CLKHOLD_bp 5 /* Clock Hold bit position. */ - -#define TWI_MASTER_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ -#define TWI_MASTER_RXACK_bp 4 /* Received Acknowledge bit position. */ - -#define TWI_MASTER_ARBLOST_bm 0x08 /* Arbitration Lost bit mask. */ -#define TWI_MASTER_ARBLOST_bp 3 /* Arbitration Lost bit position. */ - -#define TWI_MASTER_BUSERR_bm 0x04 /* Bus Error bit mask. */ -#define TWI_MASTER_BUSERR_bp 2 /* Bus Error bit position. */ - -#define TWI_MASTER_BUSSTATE_gm 0x03 /* Bus State group mask. */ -#define TWI_MASTER_BUSSTATE_gp 0 /* Bus State group position. */ -#define TWI_MASTER_BUSSTATE0_bm (1<<0) /* Bus State bit 0 mask. */ -#define TWI_MASTER_BUSSTATE0_bp 0 /* Bus State bit 0 position. */ -#define TWI_MASTER_BUSSTATE1_bm (1<<1) /* Bus State bit 1 mask. */ -#define TWI_MASTER_BUSSTATE1_bp 1 /* Bus State bit 1 position. */ - - -/* TWI_SLAVE.CTRLA bit masks and bit positions */ -#define TWI_SLAVE_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ -#define TWI_SLAVE_INTLVL_gp 6 /* Interrupt Level group position. */ -#define TWI_SLAVE_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ -#define TWI_SLAVE_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ -#define TWI_SLAVE_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ -#define TWI_SLAVE_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ - -#define TWI_SLAVE_DIEN_bm 0x20 /* Data Interrupt Enable bit mask. */ -#define TWI_SLAVE_DIEN_bp 5 /* Data Interrupt Enable bit position. */ - -#define TWI_SLAVE_APIEN_bm 0x10 /* Address/Stop Interrupt Enable bit mask. */ -#define TWI_SLAVE_APIEN_bp 4 /* Address/Stop Interrupt Enable bit position. */ - -#define TWI_SLAVE_ENABLE_bm 0x08 /* Enable TWI Slave bit mask. */ -#define TWI_SLAVE_ENABLE_bp 3 /* Enable TWI Slave bit position. */ - -#define TWI_SLAVE_PIEN_bm 0x04 /* Stop Interrupt Enable bit mask. */ -#define TWI_SLAVE_PIEN_bp 2 /* Stop Interrupt Enable bit position. */ - -#define TWI_SLAVE_PMEN_bm 0x02 /* Promiscuous Mode Enable bit mask. */ -#define TWI_SLAVE_PMEN_bp 1 /* Promiscuous Mode Enable bit position. */ - -#define TWI_SLAVE_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ -#define TWI_SLAVE_SMEN_bp 0 /* Smart Mode Enable bit position. */ - - -/* TWI_SLAVE.CTRLB bit masks and bit positions */ -#define TWI_SLAVE_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ -#define TWI_SLAVE_ACKACT_bp 2 /* Acknowledge Action bit position. */ - -#define TWI_SLAVE_CMD_gm 0x03 /* Command group mask. */ -#define TWI_SLAVE_CMD_gp 0 /* Command group position. */ -#define TWI_SLAVE_CMD0_bm (1<<0) /* Command bit 0 mask. */ -#define TWI_SLAVE_CMD0_bp 0 /* Command bit 0 position. */ -#define TWI_SLAVE_CMD1_bm (1<<1) /* Command bit 1 mask. */ -#define TWI_SLAVE_CMD1_bp 1 /* Command bit 1 position. */ - - -/* TWI_SLAVE.STATUS bit masks and bit positions */ -#define TWI_SLAVE_DIF_bm 0x80 /* Data Interrupt Flag bit mask. */ -#define TWI_SLAVE_DIF_bp 7 /* Data Interrupt Flag bit position. */ - -#define TWI_SLAVE_APIF_bm 0x40 /* Address/Stop Interrupt Flag bit mask. */ -#define TWI_SLAVE_APIF_bp 6 /* Address/Stop Interrupt Flag bit position. */ - -#define TWI_SLAVE_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ -#define TWI_SLAVE_CLKHOLD_bp 5 /* Clock Hold bit position. */ - -#define TWI_SLAVE_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ -#define TWI_SLAVE_RXACK_bp 4 /* Received Acknowledge bit position. */ - -#define TWI_SLAVE_COLL_bm 0x08 /* Collision bit mask. */ -#define TWI_SLAVE_COLL_bp 3 /* Collision bit position. */ - -#define TWI_SLAVE_BUSERR_bm 0x04 /* Bus Error bit mask. */ -#define TWI_SLAVE_BUSERR_bp 2 /* Bus Error bit position. */ - -#define TWI_SLAVE_DIR_bm 0x02 /* Read/Write Direction bit mask. */ -#define TWI_SLAVE_DIR_bp 1 /* Read/Write Direction bit position. */ - -#define TWI_SLAVE_AP_bm 0x01 /* Slave Address or Stop bit mask. */ -#define TWI_SLAVE_AP_bp 0 /* Slave Address or Stop bit position. */ - - -/* TWI_SLAVE.ADDRMASK bit masks and bit positions */ -#define TWI_SLAVE_ADDRMASK_gm 0xFE /* Address Mask group mask. */ -#define TWI_SLAVE_ADDRMASK_gp 1 /* Address Mask group position. */ -#define TWI_SLAVE_ADDRMASK0_bm (1<<1) /* Address Mask bit 0 mask. */ -#define TWI_SLAVE_ADDRMASK0_bp 1 /* Address Mask bit 0 position. */ -#define TWI_SLAVE_ADDRMASK1_bm (1<<2) /* Address Mask bit 1 mask. */ -#define TWI_SLAVE_ADDRMASK1_bp 2 /* Address Mask bit 1 position. */ -#define TWI_SLAVE_ADDRMASK2_bm (1<<3) /* Address Mask bit 2 mask. */ -#define TWI_SLAVE_ADDRMASK2_bp 3 /* Address Mask bit 2 position. */ -#define TWI_SLAVE_ADDRMASK3_bm (1<<4) /* Address Mask bit 3 mask. */ -#define TWI_SLAVE_ADDRMASK3_bp 4 /* Address Mask bit 3 position. */ -#define TWI_SLAVE_ADDRMASK4_bm (1<<5) /* Address Mask bit 4 mask. */ -#define TWI_SLAVE_ADDRMASK4_bp 5 /* Address Mask bit 4 position. */ -#define TWI_SLAVE_ADDRMASK5_bm (1<<6) /* Address Mask bit 5 mask. */ -#define TWI_SLAVE_ADDRMASK5_bp 6 /* Address Mask bit 5 position. */ -#define TWI_SLAVE_ADDRMASK6_bm (1<<7) /* Address Mask bit 6 mask. */ -#define TWI_SLAVE_ADDRMASK6_bp 7 /* Address Mask bit 6 position. */ - -#define TWI_SLAVE_ADDREN_bm 0x01 /* Address Enable bit mask. */ -#define TWI_SLAVE_ADDREN_bp 0 /* Address Enable bit position. */ - - -/* TWI.CTRL bit masks and bit positions */ -#define TWI_SDAHOLD_bm 0x02 /* SDA Hold Time Enable bit mask. */ -#define TWI_SDAHOLD_bp 1 /* SDA Hold Time Enable bit position. */ - -#define TWI_EDIEN_bm 0x01 /* External Driver Interface Enable bit mask. */ -#define TWI_EDIEN_bp 0 /* External Driver Interface Enable bit position. */ - - -/* PORT - Port Configuration */ -/* PORTCFG.VPCTRLA bit masks and bit positions */ -#define PORTCFG_VP1MAP_gm 0xF0 /* Virtual Port 1 Mapping group mask. */ -#define PORTCFG_VP1MAP_gp 4 /* Virtual Port 1 Mapping group position. */ -#define PORTCFG_VP1MAP0_bm (1<<4) /* Virtual Port 1 Mapping bit 0 mask. */ -#define PORTCFG_VP1MAP0_bp 4 /* Virtual Port 1 Mapping bit 0 position. */ -#define PORTCFG_VP1MAP1_bm (1<<5) /* Virtual Port 1 Mapping bit 1 mask. */ -#define PORTCFG_VP1MAP1_bp 5 /* Virtual Port 1 Mapping bit 1 position. */ -#define PORTCFG_VP1MAP2_bm (1<<6) /* Virtual Port 1 Mapping bit 2 mask. */ -#define PORTCFG_VP1MAP2_bp 6 /* Virtual Port 1 Mapping bit 2 position. */ -#define PORTCFG_VP1MAP3_bm (1<<7) /* Virtual Port 1 Mapping bit 3 mask. */ -#define PORTCFG_VP1MAP3_bp 7 /* Virtual Port 1 Mapping bit 3 position. */ - -#define PORTCFG_VP0MAP_gm 0x0F /* Virtual Port 0 Mapping group mask. */ -#define PORTCFG_VP0MAP_gp 0 /* Virtual Port 0 Mapping group position. */ -#define PORTCFG_VP0MAP0_bm (1<<0) /* Virtual Port 0 Mapping bit 0 mask. */ -#define PORTCFG_VP0MAP0_bp 0 /* Virtual Port 0 Mapping bit 0 position. */ -#define PORTCFG_VP0MAP1_bm (1<<1) /* Virtual Port 0 Mapping bit 1 mask. */ -#define PORTCFG_VP0MAP1_bp 1 /* Virtual Port 0 Mapping bit 1 position. */ -#define PORTCFG_VP0MAP2_bm (1<<2) /* Virtual Port 0 Mapping bit 2 mask. */ -#define PORTCFG_VP0MAP2_bp 2 /* Virtual Port 0 Mapping bit 2 position. */ -#define PORTCFG_VP0MAP3_bm (1<<3) /* Virtual Port 0 Mapping bit 3 mask. */ -#define PORTCFG_VP0MAP3_bp 3 /* Virtual Port 0 Mapping bit 3 position. */ - - -/* PORTCFG.VPCTRLB bit masks and bit positions */ -#define PORTCFG_VP3MAP_gm 0xF0 /* Virtual Port 3 Mapping group mask. */ -#define PORTCFG_VP3MAP_gp 4 /* Virtual Port 3 Mapping group position. */ -#define PORTCFG_VP3MAP0_bm (1<<4) /* Virtual Port 3 Mapping bit 0 mask. */ -#define PORTCFG_VP3MAP0_bp 4 /* Virtual Port 3 Mapping bit 0 position. */ -#define PORTCFG_VP3MAP1_bm (1<<5) /* Virtual Port 3 Mapping bit 1 mask. */ -#define PORTCFG_VP3MAP1_bp 5 /* Virtual Port 3 Mapping bit 1 position. */ -#define PORTCFG_VP3MAP2_bm (1<<6) /* Virtual Port 3 Mapping bit 2 mask. */ -#define PORTCFG_VP3MAP2_bp 6 /* Virtual Port 3 Mapping bit 2 position. */ -#define PORTCFG_VP3MAP3_bm (1<<7) /* Virtual Port 3 Mapping bit 3 mask. */ -#define PORTCFG_VP3MAP3_bp 7 /* Virtual Port 3 Mapping bit 3 position. */ - -#define PORTCFG_VP2MAP_gm 0x0F /* Virtual Port 2 Mapping group mask. */ -#define PORTCFG_VP2MAP_gp 0 /* Virtual Port 2 Mapping group position. */ -#define PORTCFG_VP2MAP0_bm (1<<0) /* Virtual Port 2 Mapping bit 0 mask. */ -#define PORTCFG_VP2MAP0_bp 0 /* Virtual Port 2 Mapping bit 0 position. */ -#define PORTCFG_VP2MAP1_bm (1<<1) /* Virtual Port 2 Mapping bit 1 mask. */ -#define PORTCFG_VP2MAP1_bp 1 /* Virtual Port 2 Mapping bit 1 position. */ -#define PORTCFG_VP2MAP2_bm (1<<2) /* Virtual Port 2 Mapping bit 2 mask. */ -#define PORTCFG_VP2MAP2_bp 2 /* Virtual Port 2 Mapping bit 2 position. */ -#define PORTCFG_VP2MAP3_bm (1<<3) /* Virtual Port 2 Mapping bit 3 mask. */ -#define PORTCFG_VP2MAP3_bp 3 /* Virtual Port 2 Mapping bit 3 position. */ - - -/* PORTCFG.CLKEVOUT bit masks and bit positions */ -#define PORTCFG_CLKOUT_gm 0x03 /* Clock Output Port group mask. */ -#define PORTCFG_CLKOUT_gp 0 /* Clock Output Port group position. */ -#define PORTCFG_CLKOUT0_bm (1<<0) /* Clock Output Port bit 0 mask. */ -#define PORTCFG_CLKOUT0_bp 0 /* Clock Output Port bit 0 position. */ -#define PORTCFG_CLKOUT1_bm (1<<1) /* Clock Output Port bit 1 mask. */ -#define PORTCFG_CLKOUT1_bp 1 /* Clock Output Port bit 1 position. */ - -#define PORTCFG_EVOUT_gm 0x30 /* Event Output Port group mask. */ -#define PORTCFG_EVOUT_gp 4 /* Event Output Port group position. */ -#define PORTCFG_EVOUT0_bm (1<<4) /* Event Output Port bit 0 mask. */ -#define PORTCFG_EVOUT0_bp 4 /* Event Output Port bit 0 position. */ -#define PORTCFG_EVOUT1_bm (1<<5) /* Event Output Port bit 1 mask. */ -#define PORTCFG_EVOUT1_bp 5 /* Event Output Port bit 1 position. */ - - -/* VPORT.INTFLAGS bit masks and bit positions */ -#define VPORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ -#define VPORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ - -#define VPORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ -#define VPORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ - - -/* PORT.INTCTRL bit masks and bit positions */ -#define PORT_INT1LVL_gm 0x0C /* Port Interrupt 1 Level group mask. */ -#define PORT_INT1LVL_gp 2 /* Port Interrupt 1 Level group position. */ -#define PORT_INT1LVL0_bm (1<<2) /* Port Interrupt 1 Level bit 0 mask. */ -#define PORT_INT1LVL0_bp 2 /* Port Interrupt 1 Level bit 0 position. */ -#define PORT_INT1LVL1_bm (1<<3) /* Port Interrupt 1 Level bit 1 mask. */ -#define PORT_INT1LVL1_bp 3 /* Port Interrupt 1 Level bit 1 position. */ - -#define PORT_INT0LVL_gm 0x03 /* Port Interrupt 0 Level group mask. */ -#define PORT_INT0LVL_gp 0 /* Port Interrupt 0 Level group position. */ -#define PORT_INT0LVL0_bm (1<<0) /* Port Interrupt 0 Level bit 0 mask. */ -#define PORT_INT0LVL0_bp 0 /* Port Interrupt 0 Level bit 0 position. */ -#define PORT_INT0LVL1_bm (1<<1) /* Port Interrupt 0 Level bit 1 mask. */ -#define PORT_INT0LVL1_bp 1 /* Port Interrupt 0 Level bit 1 position. */ - - -/* PORT.INTFLAGS bit masks and bit positions */ -#define PORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ -#define PORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ - -#define PORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ -#define PORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ - - -/* PORT.PIN0CTRL bit masks and bit positions */ -#define PORT_SRLEN_bm 0x80 /* Slew Rate Enable bit mask. */ -#define PORT_SRLEN_bp 7 /* Slew Rate Enable bit position. */ - -#define PORT_INVEN_bm 0x40 /* Inverted I/O Enable bit mask. */ -#define PORT_INVEN_bp 6 /* Inverted I/O Enable bit position. */ - -#define PORT_OPC_gm 0x38 /* Output/Pull Configuration group mask. */ -#define PORT_OPC_gp 3 /* Output/Pull Configuration group position. */ -#define PORT_OPC0_bm (1<<3) /* Output/Pull Configuration bit 0 mask. */ -#define PORT_OPC0_bp 3 /* Output/Pull Configuration bit 0 position. */ -#define PORT_OPC1_bm (1<<4) /* Output/Pull Configuration bit 1 mask. */ -#define PORT_OPC1_bp 4 /* Output/Pull Configuration bit 1 position. */ -#define PORT_OPC2_bm (1<<5) /* Output/Pull Configuration bit 2 mask. */ -#define PORT_OPC2_bp 5 /* Output/Pull Configuration bit 2 position. */ - -#define PORT_ISC_gm 0x07 /* Input/Sense Configuration group mask. */ -#define PORT_ISC_gp 0 /* Input/Sense Configuration group position. */ -#define PORT_ISC0_bm (1<<0) /* Input/Sense Configuration bit 0 mask. */ -#define PORT_ISC0_bp 0 /* Input/Sense Configuration bit 0 position. */ -#define PORT_ISC1_bm (1<<1) /* Input/Sense Configuration bit 1 mask. */ -#define PORT_ISC1_bp 1 /* Input/Sense Configuration bit 1 position. */ -#define PORT_ISC2_bm (1<<2) /* Input/Sense Configuration bit 2 mask. */ -#define PORT_ISC2_bp 2 /* Input/Sense Configuration bit 2 position. */ - - -/* PORT.PIN1CTRL bit masks and bit positions */ -/* PORT_SRLEN_bm Predefined. */ -/* PORT_SRLEN_bp Predefined. */ - -/* PORT_INVEN_bm Predefined. */ -/* PORT_INVEN_bp Predefined. */ - -/* PORT_OPC_gm Predefined. */ -/* PORT_OPC_gp Predefined. */ -/* PORT_OPC0_bm Predefined. */ -/* PORT_OPC0_bp Predefined. */ -/* PORT_OPC1_bm Predefined. */ -/* PORT_OPC1_bp Predefined. */ -/* PORT_OPC2_bm Predefined. */ -/* PORT_OPC2_bp Predefined. */ - -/* PORT_ISC_gm Predefined. */ -/* PORT_ISC_gp Predefined. */ -/* PORT_ISC0_bm Predefined. */ -/* PORT_ISC0_bp Predefined. */ -/* PORT_ISC1_bm Predefined. */ -/* PORT_ISC1_bp Predefined. */ -/* PORT_ISC2_bm Predefined. */ -/* PORT_ISC2_bp Predefined. */ - - -/* PORT.PIN2CTRL bit masks and bit positions */ -/* PORT_SRLEN_bm Predefined. */ -/* PORT_SRLEN_bp Predefined. */ - -/* PORT_INVEN_bm Predefined. */ -/* PORT_INVEN_bp Predefined. */ - -/* PORT_OPC_gm Predefined. */ -/* PORT_OPC_gp Predefined. */ -/* PORT_OPC0_bm Predefined. */ -/* PORT_OPC0_bp Predefined. */ -/* PORT_OPC1_bm Predefined. */ -/* PORT_OPC1_bp Predefined. */ -/* PORT_OPC2_bm Predefined. */ -/* PORT_OPC2_bp Predefined. */ - -/* PORT_ISC_gm Predefined. */ -/* PORT_ISC_gp Predefined. */ -/* PORT_ISC0_bm Predefined. */ -/* PORT_ISC0_bp Predefined. */ -/* PORT_ISC1_bm Predefined. */ -/* PORT_ISC1_bp Predefined. */ -/* PORT_ISC2_bm Predefined. */ -/* PORT_ISC2_bp Predefined. */ - - -/* PORT.PIN3CTRL bit masks and bit positions */ -/* PORT_SRLEN_bm Predefined. */ -/* PORT_SRLEN_bp Predefined. */ - -/* PORT_INVEN_bm Predefined. */ -/* PORT_INVEN_bp Predefined. */ - -/* PORT_OPC_gm Predefined. */ -/* PORT_OPC_gp Predefined. */ -/* PORT_OPC0_bm Predefined. */ -/* PORT_OPC0_bp Predefined. */ -/* PORT_OPC1_bm Predefined. */ -/* PORT_OPC1_bp Predefined. */ -/* PORT_OPC2_bm Predefined. */ -/* PORT_OPC2_bp Predefined. */ - -/* PORT_ISC_gm Predefined. */ -/* PORT_ISC_gp Predefined. */ -/* PORT_ISC0_bm Predefined. */ -/* PORT_ISC0_bp Predefined. */ -/* PORT_ISC1_bm Predefined. */ -/* PORT_ISC1_bp Predefined. */ -/* PORT_ISC2_bm Predefined. */ -/* PORT_ISC2_bp Predefined. */ - - -/* PORT.PIN4CTRL bit masks and bit positions */ -/* PORT_SRLEN_bm Predefined. */ -/* PORT_SRLEN_bp Predefined. */ - -/* PORT_INVEN_bm Predefined. */ -/* PORT_INVEN_bp Predefined. */ - -/* PORT_OPC_gm Predefined. */ -/* PORT_OPC_gp Predefined. */ -/* PORT_OPC0_bm Predefined. */ -/* PORT_OPC0_bp Predefined. */ -/* PORT_OPC1_bm Predefined. */ -/* PORT_OPC1_bp Predefined. */ -/* PORT_OPC2_bm Predefined. */ -/* PORT_OPC2_bp Predefined. */ - -/* PORT_ISC_gm Predefined. */ -/* PORT_ISC_gp Predefined. */ -/* PORT_ISC0_bm Predefined. */ -/* PORT_ISC0_bp Predefined. */ -/* PORT_ISC1_bm Predefined. */ -/* PORT_ISC1_bp Predefined. */ -/* PORT_ISC2_bm Predefined. */ -/* PORT_ISC2_bp Predefined. */ - - -/* PORT.PIN5CTRL bit masks and bit positions */ -/* PORT_SRLEN_bm Predefined. */ -/* PORT_SRLEN_bp Predefined. */ - -/* PORT_INVEN_bm Predefined. */ -/* PORT_INVEN_bp Predefined. */ - -/* PORT_OPC_gm Predefined. */ -/* PORT_OPC_gp Predefined. */ -/* PORT_OPC0_bm Predefined. */ -/* PORT_OPC0_bp Predefined. */ -/* PORT_OPC1_bm Predefined. */ -/* PORT_OPC1_bp Predefined. */ -/* PORT_OPC2_bm Predefined. */ -/* PORT_OPC2_bp Predefined. */ - -/* PORT_ISC_gm Predefined. */ -/* PORT_ISC_gp Predefined. */ -/* PORT_ISC0_bm Predefined. */ -/* PORT_ISC0_bp Predefined. */ -/* PORT_ISC1_bm Predefined. */ -/* PORT_ISC1_bp Predefined. */ -/* PORT_ISC2_bm Predefined. */ -/* PORT_ISC2_bp Predefined. */ - - -/* PORT.PIN6CTRL bit masks and bit positions */ -/* PORT_SRLEN_bm Predefined. */ -/* PORT_SRLEN_bp Predefined. */ - -/* PORT_INVEN_bm Predefined. */ -/* PORT_INVEN_bp Predefined. */ - -/* PORT_OPC_gm Predefined. */ -/* PORT_OPC_gp Predefined. */ -/* PORT_OPC0_bm Predefined. */ -/* PORT_OPC0_bp Predefined. */ -/* PORT_OPC1_bm Predefined. */ -/* PORT_OPC1_bp Predefined. */ -/* PORT_OPC2_bm Predefined. */ -/* PORT_OPC2_bp Predefined. */ - -/* PORT_ISC_gm Predefined. */ -/* PORT_ISC_gp Predefined. */ -/* PORT_ISC0_bm Predefined. */ -/* PORT_ISC0_bp Predefined. */ -/* PORT_ISC1_bm Predefined. */ -/* PORT_ISC1_bp Predefined. */ -/* PORT_ISC2_bm Predefined. */ -/* PORT_ISC2_bp Predefined. */ - - -/* PORT.PIN7CTRL bit masks and bit positions */ -/* PORT_SRLEN_bm Predefined. */ -/* PORT_SRLEN_bp Predefined. */ - -/* PORT_INVEN_bm Predefined. */ -/* PORT_INVEN_bp Predefined. */ - -/* PORT_OPC_gm Predefined. */ -/* PORT_OPC_gp Predefined. */ -/* PORT_OPC0_bm Predefined. */ -/* PORT_OPC0_bp Predefined. */ -/* PORT_OPC1_bm Predefined. */ -/* PORT_OPC1_bp Predefined. */ -/* PORT_OPC2_bm Predefined. */ -/* PORT_OPC2_bp Predefined. */ - -/* PORT_ISC_gm Predefined. */ -/* PORT_ISC_gp Predefined. */ -/* PORT_ISC0_bm Predefined. */ -/* PORT_ISC0_bp Predefined. */ -/* PORT_ISC1_bm Predefined. */ -/* PORT_ISC1_bp Predefined. */ -/* PORT_ISC2_bm Predefined. */ -/* PORT_ISC2_bp Predefined. */ - - -/* TC - 16-bit Timer/Counter With PWM */ -/* TC0.CTRLA bit masks and bit positions */ -#define TC0_CLKSEL_gm 0x0F /* Clock Selection group mask. */ -#define TC0_CLKSEL_gp 0 /* Clock Selection group position. */ -#define TC0_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ -#define TC0_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ -#define TC0_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ -#define TC0_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ -#define TC0_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ -#define TC0_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ -#define TC0_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ -#define TC0_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ - - -/* TC0.CTRLB bit masks and bit positions */ -#define TC0_CCDEN_bm 0x80 /* Compare or Capture D Enable bit mask. */ -#define TC0_CCDEN_bp 7 /* Compare or Capture D Enable bit position. */ - -#define TC0_CCCEN_bm 0x40 /* Compare or Capture C Enable bit mask. */ -#define TC0_CCCEN_bp 6 /* Compare or Capture C Enable bit position. */ - -#define TC0_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ -#define TC0_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ - -#define TC0_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ -#define TC0_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ - -#define TC0_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ -#define TC0_WGMODE_gp 0 /* Waveform generation mode group position. */ -#define TC0_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ -#define TC0_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ -#define TC0_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ -#define TC0_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ -#define TC0_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ -#define TC0_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ - - -/* TC0.CTRLC bit masks and bit positions */ -#define TC0_CMPD_bm 0x08 /* Compare D Output Value bit mask. */ -#define TC0_CMPD_bp 3 /* Compare D Output Value bit position. */ - -#define TC0_CMPC_bm 0x04 /* Compare C Output Value bit mask. */ -#define TC0_CMPC_bp 2 /* Compare C Output Value bit position. */ - -#define TC0_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ -#define TC0_CMPB_bp 1 /* Compare B Output Value bit position. */ - -#define TC0_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ -#define TC0_CMPA_bp 0 /* Compare A Output Value bit position. */ - - -/* TC0.CTRLD bit masks and bit positions */ -#define TC0_EVACT_gm 0xE0 /* Event Action group mask. */ -#define TC0_EVACT_gp 5 /* Event Action group position. */ -#define TC0_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ -#define TC0_EVACT0_bp 5 /* Event Action bit 0 position. */ -#define TC0_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ -#define TC0_EVACT1_bp 6 /* Event Action bit 1 position. */ -#define TC0_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ -#define TC0_EVACT2_bp 7 /* Event Action bit 2 position. */ - -#define TC0_EVDLY_bm 0x10 /* Event Delay bit mask. */ -#define TC0_EVDLY_bp 4 /* Event Delay bit position. */ - -#define TC0_EVSEL_gm 0x0F /* Event Source Select group mask. */ -#define TC0_EVSEL_gp 0 /* Event Source Select group position. */ -#define TC0_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ -#define TC0_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ -#define TC0_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ -#define TC0_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ -#define TC0_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ -#define TC0_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ -#define TC0_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ -#define TC0_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ - - -/* TC0.CTRLE bit masks and bit positions */ -#define TC0_DTHM_bm 0x02 /* Dead Time Hold Mode bit mask. */ -#define TC0_DTHM_bp 1 /* Dead Time Hold Mode bit position. */ - -#define TC0_BYTEM_bm 0x01 /* Byte Mode bit mask. */ -#define TC0_BYTEM_bp 0 /* Byte Mode bit position. */ - - -/* TC0.INTCTRLA bit masks and bit positions */ -#define TC0_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ -#define TC0_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ -#define TC0_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ -#define TC0_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ -#define TC0_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ -#define TC0_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ - -#define TC0_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ -#define TC0_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ -#define TC0_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ -#define TC0_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ -#define TC0_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ -#define TC0_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ - - -/* TC0.INTCTRLB bit masks and bit positions */ -#define TC0_CCDINTLVL_gm 0xC0 /* Compare or Capture D Interrupt Level group mask. */ -#define TC0_CCDINTLVL_gp 6 /* Compare or Capture D Interrupt Level group position. */ -#define TC0_CCDINTLVL0_bm (1<<6) /* Compare or Capture D Interrupt Level bit 0 mask. */ -#define TC0_CCDINTLVL0_bp 6 /* Compare or Capture D Interrupt Level bit 0 position. */ -#define TC0_CCDINTLVL1_bm (1<<7) /* Compare or Capture D Interrupt Level bit 1 mask. */ -#define TC0_CCDINTLVL1_bp 7 /* Compare or Capture D Interrupt Level bit 1 position. */ - -#define TC0_CCCINTLVL_gm 0x30 /* Compare or Capture C Interrupt Level group mask. */ -#define TC0_CCCINTLVL_gp 4 /* Compare or Capture C Interrupt Level group position. */ -#define TC0_CCCINTLVL0_bm (1<<4) /* Compare or Capture C Interrupt Level bit 0 mask. */ -#define TC0_CCCINTLVL0_bp 4 /* Compare or Capture C Interrupt Level bit 0 position. */ -#define TC0_CCCINTLVL1_bm (1<<5) /* Compare or Capture C Interrupt Level bit 1 mask. */ -#define TC0_CCCINTLVL1_bp 5 /* Compare or Capture C Interrupt Level bit 1 position. */ - -#define TC0_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ -#define TC0_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ -#define TC0_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ -#define TC0_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ -#define TC0_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ -#define TC0_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ - -#define TC0_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ -#define TC0_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ -#define TC0_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ -#define TC0_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ -#define TC0_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ -#define TC0_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ - - -/* TC0.CTRLFCLR bit masks and bit positions */ -#define TC0_CMD_gm 0x0C /* Command group mask. */ -#define TC0_CMD_gp 2 /* Command group position. */ -#define TC0_CMD0_bm (1<<2) /* Command bit 0 mask. */ -#define TC0_CMD0_bp 2 /* Command bit 0 position. */ -#define TC0_CMD1_bm (1<<3) /* Command bit 1 mask. */ -#define TC0_CMD1_bp 3 /* Command bit 1 position. */ - -#define TC0_LUPD_bm 0x02 /* Lock Update bit mask. */ -#define TC0_LUPD_bp 1 /* Lock Update bit position. */ - -#define TC0_DIR_bm 0x01 /* Direction bit mask. */ -#define TC0_DIR_bp 0 /* Direction bit position. */ - - -/* TC0.CTRLFSET bit masks and bit positions */ -/* TC0_CMD_gm Predefined. */ -/* TC0_CMD_gp Predefined. */ -/* TC0_CMD0_bm Predefined. */ -/* TC0_CMD0_bp Predefined. */ -/* TC0_CMD1_bm Predefined. */ -/* TC0_CMD1_bp Predefined. */ - -/* TC0_LUPD_bm Predefined. */ -/* TC0_LUPD_bp Predefined. */ - -/* TC0_DIR_bm Predefined. */ -/* TC0_DIR_bp Predefined. */ - - -/* TC0.CTRLGCLR bit masks and bit positions */ -#define TC0_CCDBV_bm 0x10 /* Compare or Capture D Buffer Valid bit mask. */ -#define TC0_CCDBV_bp 4 /* Compare or Capture D Buffer Valid bit position. */ - -#define TC0_CCCBV_bm 0x08 /* Compare or Capture C Buffer Valid bit mask. */ -#define TC0_CCCBV_bp 3 /* Compare or Capture C Buffer Valid bit position. */ - -#define TC0_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ -#define TC0_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ - -#define TC0_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ -#define TC0_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ - -#define TC0_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ -#define TC0_PERBV_bp 0 /* Period Buffer Valid bit position. */ - - -/* TC0.CTRLGSET bit masks and bit positions */ -/* TC0_CCDBV_bm Predefined. */ -/* TC0_CCDBV_bp Predefined. */ - -/* TC0_CCCBV_bm Predefined. */ -/* TC0_CCCBV_bp Predefined. */ - -/* TC0_CCBBV_bm Predefined. */ -/* TC0_CCBBV_bp Predefined. */ - -/* TC0_CCABV_bm Predefined. */ -/* TC0_CCABV_bp Predefined. */ - -/* TC0_PERBV_bm Predefined. */ -/* TC0_PERBV_bp Predefined. */ - - -/* TC0.INTFLAGS bit masks and bit positions */ -#define TC0_CCDIF_bm 0x80 /* Compare or Capture D Interrupt Flag bit mask. */ -#define TC0_CCDIF_bp 7 /* Compare or Capture D Interrupt Flag bit position. */ - -#define TC0_CCCIF_bm 0x40 /* Compare or Capture C Interrupt Flag bit mask. */ -#define TC0_CCCIF_bp 6 /* Compare or Capture C Interrupt Flag bit position. */ - -#define TC0_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ -#define TC0_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ - -#define TC0_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ -#define TC0_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ - -#define TC0_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ -#define TC0_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ - -#define TC0_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ -#define TC0_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ - - -/* TC1.CTRLA bit masks and bit positions */ -#define TC1_CLKSEL_gm 0x0F /* Clock Selection group mask. */ -#define TC1_CLKSEL_gp 0 /* Clock Selection group position. */ -#define TC1_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ -#define TC1_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ -#define TC1_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ -#define TC1_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ -#define TC1_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ -#define TC1_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ -#define TC1_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ -#define TC1_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ - - -/* TC1.CTRLB bit masks and bit positions */ -#define TC1_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ -#define TC1_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ - -#define TC1_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ -#define TC1_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ - -#define TC1_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ -#define TC1_WGMODE_gp 0 /* Waveform generation mode group position. */ -#define TC1_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ -#define TC1_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ -#define TC1_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ -#define TC1_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ -#define TC1_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ -#define TC1_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ - - -/* TC1.CTRLC bit masks and bit positions */ -#define TC1_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ -#define TC1_CMPB_bp 1 /* Compare B Output Value bit position. */ - -#define TC1_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ -#define TC1_CMPA_bp 0 /* Compare A Output Value bit position. */ - - -/* TC1.CTRLD bit masks and bit positions */ -#define TC1_EVACT_gm 0xE0 /* Event Action group mask. */ -#define TC1_EVACT_gp 5 /* Event Action group position. */ -#define TC1_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ -#define TC1_EVACT0_bp 5 /* Event Action bit 0 position. */ -#define TC1_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ -#define TC1_EVACT1_bp 6 /* Event Action bit 1 position. */ -#define TC1_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ -#define TC1_EVACT2_bp 7 /* Event Action bit 2 position. */ - -#define TC1_EVDLY_bm 0x10 /* Event Delay bit mask. */ -#define TC1_EVDLY_bp 4 /* Event Delay bit position. */ - -#define TC1_EVSEL_gm 0x0F /* Event Source Select group mask. */ -#define TC1_EVSEL_gp 0 /* Event Source Select group position. */ -#define TC1_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ -#define TC1_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ -#define TC1_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ -#define TC1_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ -#define TC1_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ -#define TC1_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ -#define TC1_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ -#define TC1_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ - - -/* TC1.CTRLE bit masks and bit positions */ -#define TC1_DTHM_bm 0x02 /* Dead Time Hold Mode bit mask. */ -#define TC1_DTHM_bp 1 /* Dead Time Hold Mode bit position. */ - -#define TC1_BYTEM_bm 0x01 /* Byte Mode bit mask. */ -#define TC1_BYTEM_bp 0 /* Byte Mode bit position. */ - - -/* TC1.INTCTRLA bit masks and bit positions */ -#define TC1_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ -#define TC1_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ -#define TC1_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ -#define TC1_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ -#define TC1_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ -#define TC1_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ - -#define TC1_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ -#define TC1_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ -#define TC1_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ -#define TC1_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ -#define TC1_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ -#define TC1_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ - - -/* TC1.INTCTRLB bit masks and bit positions */ -#define TC1_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ -#define TC1_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ -#define TC1_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ -#define TC1_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ -#define TC1_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ -#define TC1_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ - -#define TC1_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ -#define TC1_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ -#define TC1_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ -#define TC1_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ -#define TC1_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ -#define TC1_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ - - -/* TC1.CTRLFCLR bit masks and bit positions */ -#define TC1_CMD_gm 0x0C /* Command group mask. */ -#define TC1_CMD_gp 2 /* Command group position. */ -#define TC1_CMD0_bm (1<<2) /* Command bit 0 mask. */ -#define TC1_CMD0_bp 2 /* Command bit 0 position. */ -#define TC1_CMD1_bm (1<<3) /* Command bit 1 mask. */ -#define TC1_CMD1_bp 3 /* Command bit 1 position. */ - -#define TC1_LUPD_bm 0x02 /* Lock Update bit mask. */ -#define TC1_LUPD_bp 1 /* Lock Update bit position. */ - -#define TC1_DIR_bm 0x01 /* Direction bit mask. */ -#define TC1_DIR_bp 0 /* Direction bit position. */ - - -/* TC1.CTRLFSET bit masks and bit positions */ -/* TC1_CMD_gm Predefined. */ -/* TC1_CMD_gp Predefined. */ -/* TC1_CMD0_bm Predefined. */ -/* TC1_CMD0_bp Predefined. */ -/* TC1_CMD1_bm Predefined. */ -/* TC1_CMD1_bp Predefined. */ - -/* TC1_LUPD_bm Predefined. */ -/* TC1_LUPD_bp Predefined. */ - -/* TC1_DIR_bm Predefined. */ -/* TC1_DIR_bp Predefined. */ - - -/* TC1.CTRLGCLR bit masks and bit positions */ -#define TC1_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ -#define TC1_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ - -#define TC1_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ -#define TC1_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ - -#define TC1_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ -#define TC1_PERBV_bp 0 /* Period Buffer Valid bit position. */ - - -/* TC1.CTRLGSET bit masks and bit positions */ -/* TC1_CCBBV_bm Predefined. */ -/* TC1_CCBBV_bp Predefined. */ - -/* TC1_CCABV_bm Predefined. */ -/* TC1_CCABV_bp Predefined. */ - -/* TC1_PERBV_bm Predefined. */ -/* TC1_PERBV_bp Predefined. */ - - -/* TC1.INTFLAGS bit masks and bit positions */ -#define TC1_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ -#define TC1_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ - -#define TC1_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ -#define TC1_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ - -#define TC1_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ -#define TC1_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ - -#define TC1_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ -#define TC1_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ - - -/* AWEX.CTRL bit masks and bit positions */ -#define AWEX_PGM_bm 0x20 /* Pattern Generation Mode bit mask. */ -#define AWEX_PGM_bp 5 /* Pattern Generation Mode bit position. */ - -#define AWEX_CWCM_bm 0x10 /* Common Waveform Channel Mode bit mask. */ -#define AWEX_CWCM_bp 4 /* Common Waveform Channel Mode bit position. */ - -#define AWEX_DTICCDEN_bm 0x08 /* Dead Time Insertion Compare Channel D Enable bit mask. */ -#define AWEX_DTICCDEN_bp 3 /* Dead Time Insertion Compare Channel D Enable bit position. */ - -#define AWEX_DTICCCEN_bm 0x04 /* Dead Time Insertion Compare Channel C Enable bit mask. */ -#define AWEX_DTICCCEN_bp 2 /* Dead Time Insertion Compare Channel C Enable bit position. */ - -#define AWEX_DTICCBEN_bm 0x02 /* Dead Time Insertion Compare Channel B Enable bit mask. */ -#define AWEX_DTICCBEN_bp 1 /* Dead Time Insertion Compare Channel B Enable bit position. */ - -#define AWEX_DTICCAEN_bm 0x01 /* Dead Time Insertion Compare Channel A Enable bit mask. */ -#define AWEX_DTICCAEN_bp 0 /* Dead Time Insertion Compare Channel A Enable bit position. */ - - -/* AWEX.FDCTRL bit masks and bit positions */ -#define AWEX_FDDBD_bm 0x10 /* Fault Detect on Disable Break Disable bit mask. */ -#define AWEX_FDDBD_bp 4 /* Fault Detect on Disable Break Disable bit position. */ - -#define AWEX_FDMODE_bm 0x04 /* Fault Detect Mode bit mask. */ -#define AWEX_FDMODE_bp 2 /* Fault Detect Mode bit position. */ - -#define AWEX_FDACT_gm 0x03 /* Fault Detect Action group mask. */ -#define AWEX_FDACT_gp 0 /* Fault Detect Action group position. */ -#define AWEX_FDACT0_bm (1<<0) /* Fault Detect Action bit 0 mask. */ -#define AWEX_FDACT0_bp 0 /* Fault Detect Action bit 0 position. */ -#define AWEX_FDACT1_bm (1<<1) /* Fault Detect Action bit 1 mask. */ -#define AWEX_FDACT1_bp 1 /* Fault Detect Action bit 1 position. */ - - -/* AWEX.STATUS bit masks and bit positions */ -#define AWEX_FDF_bm 0x04 /* Fault Detect Flag bit mask. */ -#define AWEX_FDF_bp 2 /* Fault Detect Flag bit position. */ - -#define AWEX_DTHSBUFV_bm 0x02 /* Dead Time High Side Buffer Valid bit mask. */ -#define AWEX_DTHSBUFV_bp 1 /* Dead Time High Side Buffer Valid bit position. */ - -#define AWEX_DTLSBUFV_bm 0x01 /* Dead Time Low Side Buffer Valid bit mask. */ -#define AWEX_DTLSBUFV_bp 0 /* Dead Time Low Side Buffer Valid bit position. */ - - -/* HIRES.CTRL bit masks and bit positions */ -#define HIRES_HREN_gm 0x03 /* High Resolution Enable group mask. */ -#define HIRES_HREN_gp 0 /* High Resolution Enable group position. */ -#define HIRES_HREN0_bm (1<<0) /* High Resolution Enable bit 0 mask. */ -#define HIRES_HREN0_bp 0 /* High Resolution Enable bit 0 position. */ -#define HIRES_HREN1_bm (1<<1) /* High Resolution Enable bit 1 mask. */ -#define HIRES_HREN1_bp 1 /* High Resolution Enable bit 1 position. */ - - -/* USART - Universal Asynchronous Receiver-Transmitter */ -/* USART.STATUS bit masks and bit positions */ -#define USART_RXCIF_bm 0x80 /* Receive Interrupt Flag bit mask. */ -#define USART_RXCIF_bp 7 /* Receive Interrupt Flag bit position. */ - -#define USART_TXCIF_bm 0x40 /* Transmit Interrupt Flag bit mask. */ -#define USART_TXCIF_bp 6 /* Transmit Interrupt Flag bit position. */ - -#define USART_DREIF_bm 0x20 /* Data Register Empty Flag bit mask. */ -#define USART_DREIF_bp 5 /* Data Register Empty Flag bit position. */ - -#define USART_FERR_bm 0x10 /* Frame Error bit mask. */ -#define USART_FERR_bp 4 /* Frame Error bit position. */ - -#define USART_BUFOVF_bm 0x08 /* Buffer Overflow bit mask. */ -#define USART_BUFOVF_bp 3 /* Buffer Overflow bit position. */ - -#define USART_PERR_bm 0x04 /* Parity Error bit mask. */ -#define USART_PERR_bp 2 /* Parity Error bit position. */ - -#define USART_RXB8_bm 0x01 /* Receive Bit 8 bit mask. */ -#define USART_RXB8_bp 0 /* Receive Bit 8 bit position. */ - - -/* USART.CTRLA bit masks and bit positions */ -#define USART_RXCINTLVL_gm 0x30 /* Receive Interrupt Level group mask. */ -#define USART_RXCINTLVL_gp 4 /* Receive Interrupt Level group position. */ -#define USART_RXCINTLVL0_bm (1<<4) /* Receive Interrupt Level bit 0 mask. */ -#define USART_RXCINTLVL0_bp 4 /* Receive Interrupt Level bit 0 position. */ -#define USART_RXCINTLVL1_bm (1<<5) /* Receive Interrupt Level bit 1 mask. */ -#define USART_RXCINTLVL1_bp 5 /* Receive Interrupt Level bit 1 position. */ - -#define USART_TXCINTLVL_gm 0x0C /* Transmit Interrupt Level group mask. */ -#define USART_TXCINTLVL_gp 2 /* Transmit Interrupt Level group position. */ -#define USART_TXCINTLVL0_bm (1<<2) /* Transmit Interrupt Level bit 0 mask. */ -#define USART_TXCINTLVL0_bp 2 /* Transmit Interrupt Level bit 0 position. */ -#define USART_TXCINTLVL1_bm (1<<3) /* Transmit Interrupt Level bit 1 mask. */ -#define USART_TXCINTLVL1_bp 3 /* Transmit Interrupt Level bit 1 position. */ - -#define USART_DREINTLVL_gm 0x03 /* Data Register Empty Interrupt Level group mask. */ -#define USART_DREINTLVL_gp 0 /* Data Register Empty Interrupt Level group position. */ -#define USART_DREINTLVL0_bm (1<<0) /* Data Register Empty Interrupt Level bit 0 mask. */ -#define USART_DREINTLVL0_bp 0 /* Data Register Empty Interrupt Level bit 0 position. */ -#define USART_DREINTLVL1_bm (1<<1) /* Data Register Empty Interrupt Level bit 1 mask. */ -#define USART_DREINTLVL1_bp 1 /* Data Register Empty Interrupt Level bit 1 position. */ - - -/* USART.CTRLB bit masks and bit positions */ -#define USART_RXEN_bm 0x10 /* Receiver Enable bit mask. */ -#define USART_RXEN_bp 4 /* Receiver Enable bit position. */ - -#define USART_TXEN_bm 0x08 /* Transmitter Enable bit mask. */ -#define USART_TXEN_bp 3 /* Transmitter Enable bit position. */ - -#define USART_CLK2X_bm 0x04 /* Double transmission speed bit mask. */ -#define USART_CLK2X_bp 2 /* Double transmission speed bit position. */ - -#define USART_MPCM_bm 0x02 /* Multi-processor Communication Mode bit mask. */ -#define USART_MPCM_bp 1 /* Multi-processor Communication Mode bit position. */ - -#define USART_TXB8_bm 0x01 /* Transmit bit 8 bit mask. */ -#define USART_TXB8_bp 0 /* Transmit bit 8 bit position. */ - - -/* USART.CTRLC bit masks and bit positions */ -#define USART_CMODE_gm 0xC0 /* Communication Mode group mask. */ -#define USART_CMODE_gp 6 /* Communication Mode group position. */ -#define USART_CMODE0_bm (1<<6) /* Communication Mode bit 0 mask. */ -#define USART_CMODE0_bp 6 /* Communication Mode bit 0 position. */ -#define USART_CMODE1_bm (1<<7) /* Communication Mode bit 1 mask. */ -#define USART_CMODE1_bp 7 /* Communication Mode bit 1 position. */ - -#define USART_PMODE_gm 0x30 /* Parity Mode group mask. */ -#define USART_PMODE_gp 4 /* Parity Mode group position. */ -#define USART_PMODE0_bm (1<<4) /* Parity Mode bit 0 mask. */ -#define USART_PMODE0_bp 4 /* Parity Mode bit 0 position. */ -#define USART_PMODE1_bm (1<<5) /* Parity Mode bit 1 mask. */ -#define USART_PMODE1_bp 5 /* Parity Mode bit 1 position. */ - -#define USART_SBMODE_bm 0x08 /* Stop Bit Mode bit mask. */ -#define USART_SBMODE_bp 3 /* Stop Bit Mode bit position. */ - -#define USART_CHSIZE_gm 0x07 /* Character Size group mask. */ -#define USART_CHSIZE_gp 0 /* Character Size group position. */ -#define USART_CHSIZE0_bm (1<<0) /* Character Size bit 0 mask. */ -#define USART_CHSIZE0_bp 0 /* Character Size bit 0 position. */ -#define USART_CHSIZE1_bm (1<<1) /* Character Size bit 1 mask. */ -#define USART_CHSIZE1_bp 1 /* Character Size bit 1 position. */ -#define USART_CHSIZE2_bm (1<<2) /* Character Size bit 2 mask. */ -#define USART_CHSIZE2_bp 2 /* Character Size bit 2 position. */ - - -/* USART.BAUDCTRLA bit masks and bit positions */ -#define USART_BSEL_gm 0xFF /* Baud Rate Selection Bits [7:0] group mask. */ -#define USART_BSEL_gp 0 /* Baud Rate Selection Bits [7:0] group position. */ -#define USART_BSEL0_bm (1<<0) /* Baud Rate Selection Bits [7:0] bit 0 mask. */ -#define USART_BSEL0_bp 0 /* Baud Rate Selection Bits [7:0] bit 0 position. */ -#define USART_BSEL1_bm (1<<1) /* Baud Rate Selection Bits [7:0] bit 1 mask. */ -#define USART_BSEL1_bp 1 /* Baud Rate Selection Bits [7:0] bit 1 position. */ -#define USART_BSEL2_bm (1<<2) /* Baud Rate Selection Bits [7:0] bit 2 mask. */ -#define USART_BSEL2_bp 2 /* Baud Rate Selection Bits [7:0] bit 2 position. */ -#define USART_BSEL3_bm (1<<3) /* Baud Rate Selection Bits [7:0] bit 3 mask. */ -#define USART_BSEL3_bp 3 /* Baud Rate Selection Bits [7:0] bit 3 position. */ -#define USART_BSEL4_bm (1<<4) /* Baud Rate Selection Bits [7:0] bit 4 mask. */ -#define USART_BSEL4_bp 4 /* Baud Rate Selection Bits [7:0] bit 4 position. */ -#define USART_BSEL5_bm (1<<5) /* Baud Rate Selection Bits [7:0] bit 5 mask. */ -#define USART_BSEL5_bp 5 /* Baud Rate Selection Bits [7:0] bit 5 position. */ -#define USART_BSEL6_bm (1<<6) /* Baud Rate Selection Bits [7:0] bit 6 mask. */ -#define USART_BSEL6_bp 6 /* Baud Rate Selection Bits [7:0] bit 6 position. */ -#define USART_BSEL7_bm (1<<7) /* Baud Rate Selection Bits [7:0] bit 7 mask. */ -#define USART_BSEL7_bp 7 /* Baud Rate Selection Bits [7:0] bit 7 position. */ - - -/* USART.BAUDCTRLB bit masks and bit positions */ -#define USART_BSCALE_gm 0xF0 /* Baud Rate Scale group mask. */ -#define USART_BSCALE_gp 4 /* Baud Rate Scale group position. */ -#define USART_BSCALE0_bm (1<<4) /* Baud Rate Scale bit 0 mask. */ -#define USART_BSCALE0_bp 4 /* Baud Rate Scale bit 0 position. */ -#define USART_BSCALE1_bm (1<<5) /* Baud Rate Scale bit 1 mask. */ -#define USART_BSCALE1_bp 5 /* Baud Rate Scale bit 1 position. */ -#define USART_BSCALE2_bm (1<<6) /* Baud Rate Scale bit 2 mask. */ -#define USART_BSCALE2_bp 6 /* Baud Rate Scale bit 2 position. */ -#define USART_BSCALE3_bm (1<<7) /* Baud Rate Scale bit 3 mask. */ -#define USART_BSCALE3_bp 7 /* Baud Rate Scale bit 3 position. */ - -/* USART_BSEL_gm Predefined. */ -/* USART_BSEL_gp Predefined. */ -/* USART_BSEL0_bm Predefined. */ -/* USART_BSEL0_bp Predefined. */ -/* USART_BSEL1_bm Predefined. */ -/* USART_BSEL1_bp Predefined. */ -/* USART_BSEL2_bm Predefined. */ -/* USART_BSEL2_bp Predefined. */ -/* USART_BSEL3_bm Predefined. */ -/* USART_BSEL3_bp Predefined. */ - - -/* SPI - Serial Peripheral Interface */ -/* SPI.CTRL bit masks and bit positions */ -#define SPI_CLK2X_bm 0x80 /* Enable Double Speed bit mask. */ -#define SPI_CLK2X_bp 7 /* Enable Double Speed bit position. */ - -#define SPI_ENABLE_bm 0x40 /* Enable Module bit mask. */ -#define SPI_ENABLE_bp 6 /* Enable Module bit position. */ - -#define SPI_DORD_bm 0x20 /* Data Order Setting bit mask. */ -#define SPI_DORD_bp 5 /* Data Order Setting bit position. */ - -#define SPI_MASTER_bm 0x10 /* Master Operation Enable bit mask. */ -#define SPI_MASTER_bp 4 /* Master Operation Enable bit position. */ - -#define SPI_MODE_gm 0x0C /* SPI Mode group mask. */ -#define SPI_MODE_gp 2 /* SPI Mode group position. */ -#define SPI_MODE0_bm (1<<2) /* SPI Mode bit 0 mask. */ -#define SPI_MODE0_bp 2 /* SPI Mode bit 0 position. */ -#define SPI_MODE1_bm (1<<3) /* SPI Mode bit 1 mask. */ -#define SPI_MODE1_bp 3 /* SPI Mode bit 1 position. */ - -#define SPI_PRESCALER_gm 0x03 /* Prescaler group mask. */ -#define SPI_PRESCALER_gp 0 /* Prescaler group position. */ -#define SPI_PRESCALER0_bm (1<<0) /* Prescaler bit 0 mask. */ -#define SPI_PRESCALER0_bp 0 /* Prescaler bit 0 position. */ -#define SPI_PRESCALER1_bm (1<<1) /* Prescaler bit 1 mask. */ -#define SPI_PRESCALER1_bp 1 /* Prescaler bit 1 position. */ - - -/* SPI.INTCTRL bit masks and bit positions */ -#define SPI_INTLVL_gm 0x03 /* Interrupt level group mask. */ -#define SPI_INTLVL_gp 0 /* Interrupt level group position. */ -#define SPI_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */ -#define SPI_INTLVL0_bp 0 /* Interrupt level bit 0 position. */ -#define SPI_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */ -#define SPI_INTLVL1_bp 1 /* Interrupt level bit 1 position. */ - - -/* SPI.STATUS bit masks and bit positions */ -#define SPI_IF_bm 0x80 /* Interrupt Flag bit mask. */ -#define SPI_IF_bp 7 /* Interrupt Flag bit position. */ - -#define SPI_WRCOL_bm 0x40 /* Write Collision bit mask. */ -#define SPI_WRCOL_bp 6 /* Write Collision bit position. */ - - -/* IRCOM - IR Communication Module */ -/* IRCOM.CTRL bit masks and bit positions */ -#define IRCOM_EVSEL_gm 0x0F /* Event Channel Select group mask. */ -#define IRCOM_EVSEL_gp 0 /* Event Channel Select group position. */ -#define IRCOM_EVSEL0_bm (1<<0) /* Event Channel Select bit 0 mask. */ -#define IRCOM_EVSEL0_bp 0 /* Event Channel Select bit 0 position. */ -#define IRCOM_EVSEL1_bm (1<<1) /* Event Channel Select bit 1 mask. */ -#define IRCOM_EVSEL1_bp 1 /* Event Channel Select bit 1 position. */ -#define IRCOM_EVSEL2_bm (1<<2) /* Event Channel Select bit 2 mask. */ -#define IRCOM_EVSEL2_bp 2 /* Event Channel Select bit 2 position. */ -#define IRCOM_EVSEL3_bm (1<<3) /* Event Channel Select bit 3 mask. */ -#define IRCOM_EVSEL3_bp 3 /* Event Channel Select bit 3 position. */ - - -/* AES - AES Module */ -/* AES.CTRL bit masks and bit positions */ -#define AES_START_bm 0x80 /* Start/Run bit mask. */ -#define AES_START_bp 7 /* Start/Run bit position. */ - -#define AES_AUTO_bm 0x40 /* Auto Start Trigger bit mask. */ -#define AES_AUTO_bp 6 /* Auto Start Trigger bit position. */ - -#define AES_RESET_bm 0x20 /* AES Software Reset bit mask. */ -#define AES_RESET_bp 5 /* AES Software Reset bit position. */ - -#define AES_DECRYPT_bm 0x10 /* Decryption / Direction bit mask. */ -#define AES_DECRYPT_bp 4 /* Decryption / Direction bit position. */ - -#define AES_XOR_bm 0x04 /* State XOR Load Enable bit mask. */ -#define AES_XOR_bp 2 /* State XOR Load Enable bit position. */ - - -/* AES.STATUS bit masks and bit positions */ -#define AES_ERROR_bm 0x80 /* AES Error bit mask. */ -#define AES_ERROR_bp 7 /* AES Error bit position. */ - -#define AES_SRIF_bm 0x01 /* State Ready Interrupt Flag bit mask. */ -#define AES_SRIF_bp 0 /* State Ready Interrupt Flag bit position. */ - - -/* AES.INTCTRL bit masks and bit positions */ -#define AES_INTLVL_gm 0x03 /* Interrupt level group mask. */ -#define AES_INTLVL_gp 0 /* Interrupt level group position. */ -#define AES_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */ -#define AES_INTLVL0_bp 0 /* Interrupt level bit 0 position. */ -#define AES_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */ -#define AES_INTLVL1_bp 1 /* Interrupt level bit 1 position. */ - - - -// Generic Port Pins - -#define PIN0_bm 0x01 -#define PIN0_bp 0 -#define PIN1_bm 0x02 -#define PIN1_bp 1 -#define PIN2_bm 0x04 -#define PIN2_bp 2 -#define PIN3_bm 0x08 -#define PIN3_bp 3 -#define PIN4_bm 0x10 -#define PIN4_bp 4 -#define PIN5_bm 0x20 -#define PIN5_bp 5 -#define PIN6_bm 0x40 -#define PIN6_bp 6 -#define PIN7_bm 0x80 -#define PIN7_bp 7 - - -/* ========== Interrupt Vector Definitions ========== */ -/* Vector 0 is the reset vector */ - -/* OSC interrupt vectors */ -#define OSC_XOSCF_vect_num 1 -#define OSC_XOSCF_vect _VECTOR(1) /* External Oscillator Failure Interrupt (NMI) */ - -/* PORTC interrupt vectors */ -#define PORTC_INT0_vect_num 2 -#define PORTC_INT0_vect _VECTOR(2) /* External Interrupt 0 */ -#define PORTC_INT1_vect_num 3 -#define PORTC_INT1_vect _VECTOR(3) /* External Interrupt 1 */ - -/* PORTR interrupt vectors */ -#define PORTR_INT0_vect_num 4 -#define PORTR_INT0_vect _VECTOR(4) /* External Interrupt 0 */ -#define PORTR_INT1_vect_num 5 -#define PORTR_INT1_vect _VECTOR(5) /* External Interrupt 1 */ - -/* DMA interrupt vectors */ -#define DMA_CH0_vect_num 6 -#define DMA_CH0_vect _VECTOR(6) /* Channel 0 Interrupt */ -#define DMA_CH1_vect_num 7 -#define DMA_CH1_vect _VECTOR(7) /* Channel 1 Interrupt */ -#define DMA_CH2_vect_num 8 -#define DMA_CH2_vect _VECTOR(8) /* Channel 2 Interrupt */ -#define DMA_CH3_vect_num 9 -#define DMA_CH3_vect _VECTOR(9) /* Channel 3 Interrupt */ - -/* RTC interrupt vectors */ -#define RTC_OVF_vect_num 10 -#define RTC_OVF_vect _VECTOR(10) /* Overflow Interrupt */ -#define RTC_COMP_vect_num 11 -#define RTC_COMP_vect _VECTOR(11) /* Compare Interrupt */ - -/* TWIC interrupt vectors */ -#define TWIC_TWIS_vect_num 12 -#define TWIC_TWIS_vect _VECTOR(12) /* TWI Slave Interrupt */ -#define TWIC_TWIM_vect_num 13 -#define TWIC_TWIM_vect _VECTOR(13) /* TWI Master Interrupt */ - -/* TCC0 interrupt vectors */ -#define TCC0_OVF_vect_num 14 -#define TCC0_OVF_vect _VECTOR(14) /* Overflow Interrupt */ -#define TCC0_ERR_vect_num 15 -#define TCC0_ERR_vect _VECTOR(15) /* Error Interrupt */ -#define TCC0_CCA_vect_num 16 -#define TCC0_CCA_vect _VECTOR(16) /* Compare or Capture A Interrupt */ -#define TCC0_CCB_vect_num 17 -#define TCC0_CCB_vect _VECTOR(17) /* Compare or Capture B Interrupt */ -#define TCC0_CCC_vect_num 18 -#define TCC0_CCC_vect _VECTOR(18) /* Compare or Capture C Interrupt */ -#define TCC0_CCD_vect_num 19 -#define TCC0_CCD_vect _VECTOR(19) /* Compare or Capture D Interrupt */ - -/* TCC1 interrupt vectors */ -#define TCC1_OVF_vect_num 20 -#define TCC1_OVF_vect _VECTOR(20) /* Overflow Interrupt */ -#define TCC1_ERR_vect_num 21 -#define TCC1_ERR_vect _VECTOR(21) /* Error Interrupt */ -#define TCC1_CCA_vect_num 22 -#define TCC1_CCA_vect _VECTOR(22) /* Compare or Capture A Interrupt */ -#define TCC1_CCB_vect_num 23 -#define TCC1_CCB_vect _VECTOR(23) /* Compare or Capture B Interrupt */ - -/* SPIC interrupt vectors */ -#define SPIC_INT_vect_num 24 -#define SPIC_INT_vect _VECTOR(24) /* SPI Interrupt */ - -/* USARTC0 interrupt vectors */ -#define USARTC0_RXC_vect_num 25 -#define USARTC0_RXC_vect _VECTOR(25) /* Reception Complete Interrupt */ -#define USARTC0_DRE_vect_num 26 -#define USARTC0_DRE_vect _VECTOR(26) /* Data Register Empty Interrupt */ -#define USARTC0_TXC_vect_num 27 -#define USARTC0_TXC_vect _VECTOR(27) /* Transmission Complete Interrupt */ - -/* USARTC1 interrupt vectors */ -#define USARTC1_RXC_vect_num 28 -#define USARTC1_RXC_vect _VECTOR(28) /* Reception Complete Interrupt */ -#define USARTC1_DRE_vect_num 29 -#define USARTC1_DRE_vect _VECTOR(29) /* Data Register Empty Interrupt */ -#define USARTC1_TXC_vect_num 30 -#define USARTC1_TXC_vect _VECTOR(30) /* Transmission Complete Interrupt */ - -/* AES interrupt vectors */ -#define AES_INT_vect_num 31 -#define AES_INT_vect _VECTOR(31) /* AES Interrupt */ - -/* NVM interrupt vectors */ -#define NVM_EE_vect_num 32 -#define NVM_EE_vect _VECTOR(32) /* EE Interrupt */ -#define NVM_SPM_vect_num 33 -#define NVM_SPM_vect _VECTOR(33) /* SPM Interrupt */ - -/* PORTB interrupt vectors */ -#define PORTB_INT0_vect_num 34 -#define PORTB_INT0_vect _VECTOR(34) /* External Interrupt 0 */ -#define PORTB_INT1_vect_num 35 -#define PORTB_INT1_vect _VECTOR(35) /* External Interrupt 1 */ - -/* ACB interrupt vectors */ -#define ACB_AC0_vect_num 36 -#define ACB_AC0_vect _VECTOR(36) /* AC0 Interrupt */ -#define ACB_AC1_vect_num 37 -#define ACB_AC1_vect _VECTOR(37) /* AC1 Interrupt */ -#define ACB_ACW_vect_num 38 -#define ACB_ACW_vect _VECTOR(38) /* ACW Window Mode Interrupt */ - -/* ADCB interrupt vectors */ -#define ADCB_CH0_vect_num 39 -#define ADCB_CH0_vect _VECTOR(39) /* Interrupt 0 */ -#define ADCB_CH1_vect_num 40 -#define ADCB_CH1_vect _VECTOR(40) /* Interrupt 1 */ -#define ADCB_CH2_vect_num 41 -#define ADCB_CH2_vect _VECTOR(41) /* Interrupt 2 */ -#define ADCB_CH3_vect_num 42 -#define ADCB_CH3_vect _VECTOR(42) /* Interrupt 3 */ - -/* PORTE interrupt vectors */ -#define PORTE_INT0_vect_num 43 -#define PORTE_INT0_vect _VECTOR(43) /* External Interrupt 0 */ -#define PORTE_INT1_vect_num 44 -#define PORTE_INT1_vect _VECTOR(44) /* External Interrupt 1 */ - -/* TWIE interrupt vectors */ -#define TWIE_TWIS_vect_num 45 -#define TWIE_TWIS_vect _VECTOR(45) /* TWI Slave Interrupt */ -#define TWIE_TWIM_vect_num 46 -#define TWIE_TWIM_vect _VECTOR(46) /* TWI Master Interrupt */ - -/* TCE0 interrupt vectors */ -#define TCE0_OVF_vect_num 47 -#define TCE0_OVF_vect _VECTOR(47) /* Overflow Interrupt */ -#define TCE0_ERR_vect_num 48 -#define TCE0_ERR_vect _VECTOR(48) /* Error Interrupt */ -#define TCE0_CCA_vect_num 49 -#define TCE0_CCA_vect _VECTOR(49) /* Compare or Capture A Interrupt */ -#define TCE0_CCB_vect_num 50 -#define TCE0_CCB_vect _VECTOR(50) /* Compare or Capture B Interrupt */ -#define TCE0_CCC_vect_num 51 -#define TCE0_CCC_vect _VECTOR(51) /* Compare or Capture C Interrupt */ -#define TCE0_CCD_vect_num 52 -#define TCE0_CCD_vect _VECTOR(52) /* Compare or Capture D Interrupt */ - -/* TCE1 interrupt vectors */ -#define TCE1_OVF_vect_num 53 -#define TCE1_OVF_vect _VECTOR(53) /* Overflow Interrupt */ -#define TCE1_ERR_vect_num 54 -#define TCE1_ERR_vect _VECTOR(54) /* Error Interrupt */ -#define TCE1_CCA_vect_num 55 -#define TCE1_CCA_vect _VECTOR(55) /* Compare or Capture A Interrupt */ -#define TCE1_CCB_vect_num 56 -#define TCE1_CCB_vect _VECTOR(56) /* Compare or Capture B Interrupt */ - -/* SPIE interrupt vectors */ -#define SPIE_INT_vect_num 57 -#define SPIE_INT_vect _VECTOR(57) /* SPI Interrupt */ - -/* USARTE0 interrupt vectors */ -#define USARTE0_RXC_vect_num 58 -#define USARTE0_RXC_vect _VECTOR(58) /* Reception Complete Interrupt */ -#define USARTE0_DRE_vect_num 59 -#define USARTE0_DRE_vect _VECTOR(59) /* Data Register Empty Interrupt */ -#define USARTE0_TXC_vect_num 60 -#define USARTE0_TXC_vect _VECTOR(60) /* Transmission Complete Interrupt */ - -/* USARTE1 interrupt vectors */ -#define USARTE1_RXC_vect_num 61 -#define USARTE1_RXC_vect _VECTOR(61) /* Reception Complete Interrupt */ -#define USARTE1_DRE_vect_num 62 -#define USARTE1_DRE_vect _VECTOR(62) /* Data Register Empty Interrupt */ -#define USARTE1_TXC_vect_num 63 -#define USARTE1_TXC_vect _VECTOR(63) /* Transmission Complete Interrupt */ - -/* PORTD interrupt vectors */ -#define PORTD_INT0_vect_num 64 -#define PORTD_INT0_vect _VECTOR(64) /* External Interrupt 0 */ -#define PORTD_INT1_vect_num 65 -#define PORTD_INT1_vect _VECTOR(65) /* External Interrupt 1 */ - -/* PORTA interrupt vectors */ -#define PORTA_INT0_vect_num 66 -#define PORTA_INT0_vect _VECTOR(66) /* External Interrupt 0 */ -#define PORTA_INT1_vect_num 67 -#define PORTA_INT1_vect _VECTOR(67) /* External Interrupt 1 */ - -/* ACA interrupt vectors */ -#define ACA_AC0_vect_num 68 -#define ACA_AC0_vect _VECTOR(68) /* AC0 Interrupt */ -#define ACA_AC1_vect_num 69 -#define ACA_AC1_vect _VECTOR(69) /* AC1 Interrupt */ -#define ACA_ACW_vect_num 70 -#define ACA_ACW_vect _VECTOR(70) /* ACW Window Mode Interrupt */ - -/* ADCA interrupt vectors */ -#define ADCA_CH0_vect_num 71 -#define ADCA_CH0_vect _VECTOR(71) /* Interrupt 0 */ -#define ADCA_CH1_vect_num 72 -#define ADCA_CH1_vect _VECTOR(72) /* Interrupt 1 */ -#define ADCA_CH2_vect_num 73 -#define ADCA_CH2_vect _VECTOR(73) /* Interrupt 2 */ -#define ADCA_CH3_vect_num 74 -#define ADCA_CH3_vect _VECTOR(74) /* Interrupt 3 */ - -/* TWID interrupt vectors */ -#define TWID_TWIS_vect_num 75 -#define TWID_TWIS_vect _VECTOR(75) /* TWI Slave Interrupt */ -#define TWID_TWIM_vect_num 76 -#define TWID_TWIM_vect _VECTOR(76) /* TWI Master Interrupt */ - -/* TCD0 interrupt vectors */ -#define TCD0_OVF_vect_num 77 -#define TCD0_OVF_vect _VECTOR(77) /* Overflow Interrupt */ -#define TCD0_ERR_vect_num 78 -#define TCD0_ERR_vect _VECTOR(78) /* Error Interrupt */ -#define TCD0_CCA_vect_num 79 -#define TCD0_CCA_vect _VECTOR(79) /* Compare or Capture A Interrupt */ -#define TCD0_CCB_vect_num 80 -#define TCD0_CCB_vect _VECTOR(80) /* Compare or Capture B Interrupt */ -#define TCD0_CCC_vect_num 81 -#define TCD0_CCC_vect _VECTOR(81) /* Compare or Capture C Interrupt */ -#define TCD0_CCD_vect_num 82 -#define TCD0_CCD_vect _VECTOR(82) /* Compare or Capture D Interrupt */ - -/* TCD1 interrupt vectors */ -#define TCD1_OVF_vect_num 83 -#define TCD1_OVF_vect _VECTOR(83) /* Overflow Interrupt */ -#define TCD1_ERR_vect_num 84 -#define TCD1_ERR_vect _VECTOR(84) /* Error Interrupt */ -#define TCD1_CCA_vect_num 85 -#define TCD1_CCA_vect _VECTOR(85) /* Compare or Capture A Interrupt */ -#define TCD1_CCB_vect_num 86 -#define TCD1_CCB_vect _VECTOR(86) /* Compare or Capture B Interrupt */ - -/* SPID interrupt vectors */ -#define SPID_INT_vect_num 87 -#define SPID_INT_vect _VECTOR(87) /* SPI Interrupt */ - -/* USARTD0 interrupt vectors */ -#define USARTD0_RXC_vect_num 88 -#define USARTD0_RXC_vect _VECTOR(88) /* Reception Complete Interrupt */ -#define USARTD0_DRE_vect_num 89 -#define USARTD0_DRE_vect _VECTOR(89) /* Data Register Empty Interrupt */ -#define USARTD0_TXC_vect_num 90 -#define USARTD0_TXC_vect _VECTOR(90) /* Transmission Complete Interrupt */ - -/* USARTD1 interrupt vectors */ -#define USARTD1_RXC_vect_num 91 -#define USARTD1_RXC_vect _VECTOR(91) /* Reception Complete Interrupt */ -#define USARTD1_DRE_vect_num 92 -#define USARTD1_DRE_vect _VECTOR(92) /* Data Register Empty Interrupt */ -#define USARTD1_TXC_vect_num 93 -#define USARTD1_TXC_vect _VECTOR(93) /* Transmission Complete Interrupt */ - -/* PORTQ interrupt vectors */ -#define PORTQ_INT0_vect_num 94 -#define PORTQ_INT0_vect _VECTOR(94) /* External Interrupt 0 */ -#define PORTQ_INT1_vect_num 95 -#define PORTQ_INT1_vect _VECTOR(95) /* External Interrupt 1 */ - -/* PORTH interrupt vectors */ -#define PORTH_INT0_vect_num 96 -#define PORTH_INT0_vect _VECTOR(96) /* External Interrupt 0 */ -#define PORTH_INT1_vect_num 97 -#define PORTH_INT1_vect _VECTOR(97) /* External Interrupt 1 */ - -/* PORTJ interrupt vectors */ -#define PORTJ_INT0_vect_num 98 -#define PORTJ_INT0_vect _VECTOR(98) /* External Interrupt 0 */ -#define PORTJ_INT1_vect_num 99 -#define PORTJ_INT1_vect _VECTOR(99) /* External Interrupt 1 */ - -/* PORTK interrupt vectors */ -#define PORTK_INT0_vect_num 100 -#define PORTK_INT0_vect _VECTOR(100) /* External Interrupt 0 */ -#define PORTK_INT1_vect_num 101 -#define PORTK_INT1_vect _VECTOR(101) /* External Interrupt 1 */ - -/* PORTF interrupt vectors */ -#define PORTF_INT0_vect_num 104 -#define PORTF_INT0_vect _VECTOR(104) /* External Interrupt 0 */ -#define PORTF_INT1_vect_num 105 -#define PORTF_INT1_vect _VECTOR(105) /* External Interrupt 1 */ - -/* TWIF interrupt vectors */ -#define TWIF_TWIS_vect_num 106 -#define TWIF_TWIS_vect _VECTOR(106) /* TWI Slave Interrupt */ -#define TWIF_TWIM_vect_num 107 -#define TWIF_TWIM_vect _VECTOR(107) /* TWI Master Interrupt */ - -/* TCF0 interrupt vectors */ -#define TCF0_OVF_vect_num 108 -#define TCF0_OVF_vect _VECTOR(108) /* Overflow Interrupt */ -#define TCF0_ERR_vect_num 109 -#define TCF0_ERR_vect _VECTOR(109) /* Error Interrupt */ -#define TCF0_CCA_vect_num 110 -#define TCF0_CCA_vect _VECTOR(110) /* Compare or Capture A Interrupt */ -#define TCF0_CCB_vect_num 111 -#define TCF0_CCB_vect _VECTOR(111) /* Compare or Capture B Interrupt */ -#define TCF0_CCC_vect_num 112 -#define TCF0_CCC_vect _VECTOR(112) /* Compare or Capture C Interrupt */ -#define TCF0_CCD_vect_num 113 -#define TCF0_CCD_vect _VECTOR(113) /* Compare or Capture D Interrupt */ - -/* TCF1 interrupt vectors */ -#define TCF1_OVF_vect_num 114 -#define TCF1_OVF_vect _VECTOR(114) /* Overflow Interrupt */ -#define TCF1_ERR_vect_num 115 -#define TCF1_ERR_vect _VECTOR(115) /* Error Interrupt */ -#define TCF1_CCA_vect_num 116 -#define TCF1_CCA_vect _VECTOR(116) /* Compare or Capture A Interrupt */ -#define TCF1_CCB_vect_num 117 -#define TCF1_CCB_vect _VECTOR(117) /* Compare or Capture B Interrupt */ - -/* SPIF interrupt vectors */ -#define SPIF_INT_vect_num 118 -#define SPIF_INT_vect _VECTOR(118) /* SPI Interrupt */ - -/* USARTF0 interrupt vectors */ -#define USARTF0_RXC_vect_num 119 -#define USARTF0_RXC_vect _VECTOR(119) /* Reception Complete Interrupt */ -#define USARTF0_DRE_vect_num 120 -#define USARTF0_DRE_vect _VECTOR(120) /* Data Register Empty Interrupt */ -#define USARTF0_TXC_vect_num 121 -#define USARTF0_TXC_vect _VECTOR(121) /* Transmission Complete Interrupt */ - -/* USARTF1 interrupt vectors */ -#define USARTF1_RXC_vect_num 122 -#define USARTF1_RXC_vect _VECTOR(122) /* Reception Complete Interrupt */ -#define USARTF1_DRE_vect_num 123 -#define USARTF1_DRE_vect _VECTOR(123) /* Data Register Empty Interrupt */ -#define USARTF1_TXC_vect_num 124 -#define USARTF1_TXC_vect _VECTOR(124) /* Transmission Complete Interrupt */ - - -#define _VECTOR_SIZE 4 /* Size of individual vector. */ -#define _VECTORS_SIZE (125 * _VECTOR_SIZE) - - -/* ========== Constants ========== */ - -#define PROGMEM_START (0x0000) -#define PROGMEM_SIZE (69632) -#define PROGMEM_PAGE_SIZE (256) -#define PROGMEM_END (PROGMEM_START + PROGMEM_SIZE - 1) - -#define APP_SECTION_START (0x0000) -#define APP_SECTION_SIZE (65536) -#define APP_SECTION_PAGE_SIZE (256) -#define APP_SECTION_END (APP_SECTION_START + APP_SECTION_SIZE - 1) - -#define APPTABLE_SECTION_START (0x0F000) -#define APPTABLE_SECTION_SIZE (4096) -#define APPTABLE_SECTION_PAGE_SIZE (256) -#define APPTABLE_SECTION_END (APPTABLE_SECTION_START + APPTABLE_SECTION_SIZE - 1) - -#define BOOT_SECTION_START (0x10000) -#define BOOT_SECTION_SIZE (4096) -#define BOOT_SECTION_PAGE_SIZE (256) -#define BOOT_SECTION_END (BOOT_SECTION_START + BOOT_SECTION_SIZE - 1) - -#define DATAMEM_START (0x0000) -#define DATAMEM_SIZE (16777216) -#define DATAMEM_PAGE_SIZE (0) -#define DATAMEM_END (DATAMEM_START + DATAMEM_SIZE - 1) - -#define IO_START (0x0000) -#define IO_SIZE (4096) -#define IO_PAGE_SIZE (0) -#define IO_END (IO_START + IO_SIZE - 1) - -#define MAPPED_EEPROM_START (0x1000) -#define MAPPED_EEPROM_SIZE (2048) -#define MAPPED_EEPROM_PAGE_SIZE (0) -#define MAPPED_EEPROM_END (MAPPED_EEPROM_START + MAPPED_EEPROM_SIZE - 1) - -#define INTERNAL_SRAM_START (0x2000) -#define INTERNAL_SRAM_SIZE (4096) -#define INTERNAL_SRAM_PAGE_SIZE (0) -#define INTERNAL_SRAM_END (INTERNAL_SRAM_START + INTERNAL_SRAM_SIZE - 1) - -#define EXTERNAL_SRAM_START (0x3000) -#define EXTERNAL_SRAM_SIZE (16764928) -#define EXTERNAL_SRAM_PAGE_SIZE (0) -#define EXTERNAL_SRAM_END (EXTERNAL_SRAM_START + EXTERNAL_SRAM_SIZE - 1) - -#define EEPROM_START (0x0000) -#define EEPROM_SIZE (2048) -#define EEPROM_PAGE_SIZE (32) -#define EEPROM_END (EEPROM_START + EEPROM_SIZE - 1) - -#define FUSE_START (0x0000) -#define FUSE_SIZE (6) -#define FUSE_PAGE_SIZE (0) -#define FUSE_END (FUSE_START + FUSE_SIZE - 1) - -#define LOCKBIT_START (0x0000) -#define LOCKBIT_SIZE (1) -#define LOCKBIT_PAGE_SIZE (0) -#define LOCKBIT_END (LOCKBIT_START + LOCKBIT_SIZE - 1) - -#define SIGNATURES_START (0x0000) -#define SIGNATURES_SIZE (3) -#define SIGNATURES_PAGE_SIZE (0) -#define SIGNATURES_END (SIGNATURES_START + SIGNATURES_SIZE - 1) - -#define USER_SIGNATURES_START (0x0000) -#define USER_SIGNATURES_SIZE (256) -#define USER_SIGNATURES_PAGE_SIZE (0) -#define USER_SIGNATURES_END (USER_SIGNATURES_START + USER_SIGNATURES_SIZE - 1) - -#define PROD_SIGNATURES_START (0x0000) -#define PROD_SIGNATURES_SIZE (52) -#define PROD_SIGNATURES_PAGE_SIZE (0) -#define PROD_SIGNATURES_END (PROD_SIGNATURES_START + PROD_SIGNATURES_SIZE - 1) - -#define FLASHEND PROGMEM_END -#define SPM_PAGESIZE PROGMEM_PAGE_SIZE -#define RAMSTART INTERNAL_SRAM_START -#define RAMSIZE INTERNAL_SRAM_SIZE -#define RAMEND INTERNAL_SRAM_END -#define XRAMSTART EXTERNAL_SRAM_START -#define XRAMSIZE EXTERNAL_SRAM_SIZE -#define XRAMEND EXTERNAL_SRAM_END -#define E2END EEPROM_END -#define E2PAGESIZE EEPROM_PAGE_SIZE - - -/* ========== Fuses ========== */ -#define FUSE_MEMORY_SIZE 6 - -/* Fuse Byte 0 */ -#define FUSE_JTAGUSERID0 (unsigned char)~_BV(0) /* JTAG User ID Bit 0 */ -#define FUSE_JTAGUSERID1 (unsigned char)~_BV(1) /* JTAG User ID Bit 1 */ -#define FUSE_JTAGUSERID2 (unsigned char)~_BV(2) /* JTAG User ID Bit 2 */ -#define FUSE_JTAGUSERID3 (unsigned char)~_BV(3) /* JTAG User ID Bit 3 */ -#define FUSE_JTAGUSERID4 (unsigned char)~_BV(4) /* JTAG User ID Bit 4 */ -#define FUSE_JTAGUSERID5 (unsigned char)~_BV(5) /* JTAG User ID Bit 5 */ -#define FUSE_JTAGUSERID6 (unsigned char)~_BV(6) /* JTAG User ID Bit 6 */ -#define FUSE_JTAGUSERID7 (unsigned char)~_BV(7) /* JTAG User ID Bit 7 */ -#define FUSE0_DEFAULT (0xFF) - -/* Fuse Byte 1 */ -#define FUSE_WDP0 (unsigned char)~_BV(0) /* Watchdog Timeout Period Bit 0 */ -#define FUSE_WDP1 (unsigned char)~_BV(1) /* Watchdog Timeout Period Bit 1 */ -#define FUSE_WDP2 (unsigned char)~_BV(2) /* Watchdog Timeout Period Bit 2 */ -#define FUSE_WDP3 (unsigned char)~_BV(3) /* Watchdog Timeout Period Bit 3 */ -#define FUSE_WDWP0 (unsigned char)~_BV(4) /* Watchdog Window Timeout Period Bit 0 */ -#define FUSE_WDWP1 (unsigned char)~_BV(5) /* Watchdog Window Timeout Period Bit 1 */ -#define FUSE_WDWP2 (unsigned char)~_BV(6) /* Watchdog Window Timeout Period Bit 2 */ -#define FUSE_WDWP3 (unsigned char)~_BV(7) /* Watchdog Window Timeout Period Bit 3 */ -#define FUSE1_DEFAULT (0xFF) - -/* Fuse Byte 2 */ -#define FUSE_BODPD0 (unsigned char)~_BV(0) /* BOD Operation in Power-Down Mode Bit 0 */ -#define FUSE_BODPD1 (unsigned char)~_BV(1) /* BOD Operation in Power-Down Mode Bit 1 */ -#define FUSE_BODACT0 (unsigned char)~_BV(2) /* BOD Operation in Active Mode Bit 0 */ -#define FUSE_BODACT1 (unsigned char)~_BV(3) /* BOD Operation in Active Mode Bit 1 */ -#define FUSE_BOOTRST (unsigned char)~_BV(6) /* Boot Loader Section Reset Vector */ -#define FUSE_DVSDON (unsigned char)~_BV(7) /* Spike Detector Enable */ -#define FUSE2_DEFAULT (0xFF) - -/* Fuse Byte 3 Reserved */ - -/* Fuse Byte 4 */ -#define FUSE_JTAGEN (unsigned char)~_BV(0) /* JTAG Interface Enable */ -#define FUSE_WDLOCK (unsigned char)~_BV(1) /* Watchdog Timer Lock */ -#define FUSE_SUT0 (unsigned char)~_BV(2) /* Start-up Time Bit 0 */ -#define FUSE_SUT1 (unsigned char)~_BV(3) /* Start-up Time Bit 1 */ -#define FUSE4_DEFAULT (0xFF) - -/* Fuse Byte 5 */ -#define FUSE_BODLVL0 (unsigned char)~_BV(0) /* Brown Out Detection Voltage Level Bit 0 */ -#define FUSE_BODLVL1 (unsigned char)~_BV(1) /* Brown Out Detection Voltage Level Bit 1 */ -#define FUSE_BODLVL2 (unsigned char)~_BV(2) /* Brown Out Detection Voltage Level Bit 2 */ -#define FUSE_EESAVE (unsigned char)~_BV(3) /* Preserve EEPROM Through Chip Erase */ -#define FUSE5_DEFAULT (0xFF) - - -/* ========== Lock Bits ========== */ -#define __LOCK_BITS_EXIST -#define __BOOT_LOCK_APPLICATION_TABLE_BITS_EXIST -#define __BOOT_LOCK_APPLICATION_BITS_EXIST -#define __BOOT_LOCK_BOOT_BITS_EXIST - - -/* ========== Signature ========== */ -#define SIGNATURE_0 0x1E -#define SIGNATURE_1 0x96 -#define SIGNATURE_2 0x4E - -/* ========== Power Reduction Condition Definitions ========== */ - -/* PR.PRGEN */ -#define __AVR_HAVE_PRGEN (PR_AES_bm|PR_EBI_bm|PR_RTC_bm|PR_EVSYS_bm|PR_DMA_bm) -#define __AVR_HAVE_PRGEN_AES -#define __AVR_HAVE_PRGEN_EBI -#define __AVR_HAVE_PRGEN_RTC -#define __AVR_HAVE_PRGEN_EVSYS -#define __AVR_HAVE_PRGEN_DMA - -/* PR.PRPA */ -#define __AVR_HAVE_PRPA (PR_DAC_bm|PR_ADC_bm|PR_AC_bm) -#define __AVR_HAVE_PRPA_DAC -#define __AVR_HAVE_PRPA_ADC -#define __AVR_HAVE_PRPA_AC - -/* PR.PRPB */ -#define __AVR_HAVE_PRPB (PR_DAC_bm|PR_ADC_bm|PR_AC_bm) -#define __AVR_HAVE_PRPB_DAC -#define __AVR_HAVE_PRPB_ADC -#define __AVR_HAVE_PRPB_AC - -/* PR.PRPC */ -#define __AVR_HAVE_PRPC (PR_TWI_bm|PR_USART1_bm|PR_USART0_bm|PR_SPI_bm|PR_HIRES_bm|PR_TC1_bm|PR_TC0_bm) -#define __AVR_HAVE_PRPC_TWI -#define __AVR_HAVE_PRPC_USART1 -#define __AVR_HAVE_PRPC_USART0 -#define __AVR_HAVE_PRPC_SPI -#define __AVR_HAVE_PRPC_HIRES -#define __AVR_HAVE_PRPC_TC1 -#define __AVR_HAVE_PRPC_TC0 - -/* PR.PRPD */ -#define __AVR_HAVE_PRPD (PR_TWI_bm|PR_USART1_bm|PR_USART0_bm|PR_SPI_bm|PR_HIRES_bm|PR_TC1_bm|PR_TC0_bm) -#define __AVR_HAVE_PRPD_TWI -#define __AVR_HAVE_PRPD_USART1 -#define __AVR_HAVE_PRPD_USART0 -#define __AVR_HAVE_PRPD_SPI -#define __AVR_HAVE_PRPD_HIRES -#define __AVR_HAVE_PRPD_TC1 -#define __AVR_HAVE_PRPD_TC0 - -/* PR.PRPE */ -#define __AVR_HAVE_PRPE (PR_TWI_bm|PR_USART1_bm|PR_USART0_bm|PR_SPI_bm|PR_HIRES_bm|PR_TC1_bm|PR_TC0_bm) -#define __AVR_HAVE_PRPE_TWI -#define __AVR_HAVE_PRPE_USART1 -#define __AVR_HAVE_PRPE_USART0 -#define __AVR_HAVE_PRPE_SPI -#define __AVR_HAVE_PRPE_HIRES -#define __AVR_HAVE_PRPE_TC1 -#define __AVR_HAVE_PRPE_TC0 - -/* PR.PRPF */ -#define __AVR_HAVE_PRPF (PR_TWI_bm|PR_USART1_bm|PR_USART0_bm|PR_SPI_bm|PR_HIRES_bm|PR_TC1_bm|PR_TC0_bm) -#define __AVR_HAVE_PRPF_TWI -#define __AVR_HAVE_PRPF_USART1 -#define __AVR_HAVE_PRPF_USART0 -#define __AVR_HAVE_PRPF_SPI -#define __AVR_HAVE_PRPF_HIRES -#define __AVR_HAVE_PRPF_TC1 -#define __AVR_HAVE_PRPF_TC0 - - -#endif /* _AVR_ATxmega64A1_H_ */ - diff --git a/arduino/hardware/tools/avr/avr/include/avr/iox64a1u.h b/arduino/hardware/tools/avr/avr/include/avr/iox64a1u.h deleted file mode 100644 index 45d7f52..0000000 --- a/arduino/hardware/tools/avr/avr/include/avr/iox64a1u.h +++ /dev/null @@ -1,8305 +0,0 @@ -/***************************************************************************** - * - * Copyright (C) 2015 Atmel Corporation - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * - * * Neither the name of the copyright holders nor the names of - * contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - ****************************************************************************/ - - -#ifndef _AVR_IO_H_ -# error "Include instead of this file." -#endif - -#ifndef _AVR_IOXXX_H_ -# define _AVR_IOXXX_H_ "iox64a1u.h" -#else -# error "Attempt to include more than one file." -#endif - -#ifndef _AVR_ATXMEGA64A1U_H_INCLUDED -#define _AVR_ATXMEGA64A1U_H_INCLUDED - -/* Ungrouped common registers */ -#define GPIOR0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ -#define GPIOR1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ -#define GPIOR2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ -#define GPIOR3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ -#define GPIOR4 _SFR_MEM8(0x0004) /* General Purpose IO Register 4 */ -#define GPIOR5 _SFR_MEM8(0x0005) /* General Purpose IO Register 5 */ -#define GPIOR6 _SFR_MEM8(0x0006) /* General Purpose IO Register 6 */ -#define GPIOR7 _SFR_MEM8(0x0007) /* General Purpose IO Register 7 */ -#define GPIOR8 _SFR_MEM8(0x0008) /* General Purpose IO Register 8 */ -#define GPIOR9 _SFR_MEM8(0x0009) /* General Purpose IO Register 9 */ -#define GPIORA _SFR_MEM8(0x000A) /* General Purpose IO Register 10 */ -#define GPIORB _SFR_MEM8(0x000B) /* General Purpose IO Register 11 */ -#define GPIORC _SFR_MEM8(0x000C) /* General Purpose IO Register 12 */ -#define GPIORD _SFR_MEM8(0x000D) /* General Purpose IO Register 13 */ -#define GPIORE _SFR_MEM8(0x000E) /* General Purpose IO Register 14 */ -#define GPIORF _SFR_MEM8(0x000F) /* General Purpose IO Register 15 */ - -/* Deprecated */ -#define GPIO0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ -#define GPIO1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ -#define GPIO2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ -#define GPIO3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ -#define GPIO4 _SFR_MEM8(0x0004) /* General Purpose IO Register 4 */ -#define GPIO5 _SFR_MEM8(0x0005) /* General Purpose IO Register 5 */ -#define GPIO6 _SFR_MEM8(0x0006) /* General Purpose IO Register 6 */ -#define GPIO7 _SFR_MEM8(0x0007) /* General Purpose IO Register 7 */ -#define GPIO8 _SFR_MEM8(0x0008) /* General Purpose IO Register 8 */ -#define GPIO9 _SFR_MEM8(0x0009) /* General Purpose IO Register 9 */ -#define GPIOA _SFR_MEM8(0x000A) /* General Purpose IO Register 10 */ -#define GPIOB _SFR_MEM8(0x000B) /* General Purpose IO Register 11 */ -#define GPIOC _SFR_MEM8(0x000C) /* General Purpose IO Register 12 */ -#define GPIOD _SFR_MEM8(0x000D) /* General Purpose IO Register 13 */ -#define GPIOE _SFR_MEM8(0x000E) /* General Purpose IO Register 14 */ -#define GPIOF _SFR_MEM8(0x000F) /* General Purpose IO Register 15 */ - -#define CCP _SFR_MEM8(0x0034) /* Configuration Change Protection */ -#define RAMPD _SFR_MEM8(0x0038) /* Ramp D */ -#define RAMPX _SFR_MEM8(0x0039) /* Ramp X */ -#define RAMPY _SFR_MEM8(0x003A) /* Ramp Y */ -#define RAMPZ _SFR_MEM8(0x003B) /* Ramp Z */ -#define EIND _SFR_MEM8(0x003C) /* Extended Indirect Jump */ -#define SPL _SFR_MEM8(0x003D) /* Stack Pointer Low */ -#define SPH _SFR_MEM8(0x003E) /* Stack Pointer High */ -#define SREG _SFR_MEM8(0x003F) /* Status Register */ - -/* C Language Only */ -#if !defined (__ASSEMBLER__) - -#include - -typedef volatile uint8_t register8_t; -typedef volatile uint16_t register16_t; -typedef volatile uint32_t register32_t; - - -#ifdef _WORDREGISTER -#undef _WORDREGISTER -#endif -#define _WORDREGISTER(regname) \ - __extension__ union \ - { \ - register16_t regname; \ - struct \ - { \ - register8_t regname ## L; \ - register8_t regname ## H; \ - }; \ - } - -#ifdef _DWORDREGISTER -#undef _DWORDREGISTER -#endif -#define _DWORDREGISTER(regname) \ - __extension__ union \ - { \ - register32_t regname; \ - struct \ - { \ - register8_t regname ## 0; \ - register8_t regname ## 1; \ - register8_t regname ## 2; \ - register8_t regname ## 3; \ - }; \ - } - - -/* -========================================================================== -IO Module Structures -========================================================================== -*/ - - -/* --------------------------------------------------------------------------- -VPORT - Virtual Ports --------------------------------------------------------------------------- -*/ - -/* Virtual Port */ -typedef struct VPORT_struct -{ - register8_t DIR; /* I/O Port Data Direction */ - register8_t OUT; /* I/O Port Output */ - register8_t IN; /* I/O Port Input */ - register8_t INTFLAGS; /* Interrupt Flag Register */ -} VPORT_t; - - -/* --------------------------------------------------------------------------- -XOCD - On-Chip Debug System --------------------------------------------------------------------------- -*/ - -/* On-Chip Debug System */ -typedef struct OCD_struct -{ - register8_t OCDR0; /* OCD Register 0 */ - register8_t OCDR1; /* OCD Register 1 */ -} OCD_t; - - -/* --------------------------------------------------------------------------- -CPU - CPU --------------------------------------------------------------------------- -*/ - -/* CCP signatures */ -typedef enum CCP_enum -{ - CCP_SPM_gc = (0x9D<<0), /* SPM Instruction Protection */ - CCP_IOREG_gc = (0xD8<<0), /* IO Register Protection */ -} CCP_t; - - -/* --------------------------------------------------------------------------- -CLK - Clock System --------------------------------------------------------------------------- -*/ - -/* Clock System */ -typedef struct CLK_struct -{ - register8_t CTRL; /* Control Register */ - register8_t PSCTRL; /* Prescaler Control Register */ - register8_t LOCK; /* Lock register */ - register8_t RTCCTRL; /* RTC Control Register */ - register8_t USBCTRL; /* USB Control Register */ -} CLK_t; - - -/* Power Reduction */ -typedef struct PR_struct -{ - register8_t PRGEN; /* General Power Reduction */ - register8_t PRPA; /* Power Reduction Port A */ - register8_t PRPB; /* Power Reduction Port B */ - register8_t PRPC; /* Power Reduction Port C */ - register8_t PRPD; /* Power Reduction Port D */ - register8_t PRPE; /* Power Reduction Port E */ - register8_t PRPF; /* Power Reduction Port F */ -} PR_t; - -/* System Clock Selection */ -typedef enum CLK_SCLKSEL_enum -{ - CLK_SCLKSEL_RC2M_gc = (0x00<<0), /* Internal 2 MHz RC Oscillator */ - CLK_SCLKSEL_RC32M_gc = (0x01<<0), /* Internal 32 MHz RC Oscillator */ - CLK_SCLKSEL_RC32K_gc = (0x02<<0), /* Internal 32.768 kHz RC Oscillator */ - CLK_SCLKSEL_XOSC_gc = (0x03<<0), /* External Crystal Oscillator or Clock */ - CLK_SCLKSEL_PLL_gc = (0x04<<0), /* Phase Locked Loop */ -} CLK_SCLKSEL_t; - -/* Prescaler A Division Factor */ -typedef enum CLK_PSADIV_enum -{ - CLK_PSADIV_1_gc = (0x00<<2), /* Divide by 1 */ - CLK_PSADIV_2_gc = (0x01<<2), /* Divide by 2 */ - CLK_PSADIV_4_gc = (0x03<<2), /* Divide by 4 */ - CLK_PSADIV_8_gc = (0x05<<2), /* Divide by 8 */ - CLK_PSADIV_16_gc = (0x07<<2), /* Divide by 16 */ - CLK_PSADIV_32_gc = (0x09<<2), /* Divide by 32 */ - CLK_PSADIV_64_gc = (0x0B<<2), /* Divide by 64 */ - CLK_PSADIV_128_gc = (0x0D<<2), /* Divide by 128 */ - CLK_PSADIV_256_gc = (0x0F<<2), /* Divide by 256 */ - CLK_PSADIV_512_gc = (0x11<<2), /* Divide by 512 */ -} CLK_PSADIV_t; - -/* Prescaler B and C Division Factor */ -typedef enum CLK_PSBCDIV_enum -{ - CLK_PSBCDIV_1_1_gc = (0x00<<0), /* Divide B by 1 and C by 1 */ - CLK_PSBCDIV_1_2_gc = (0x01<<0), /* Divide B by 1 and C by 2 */ - CLK_PSBCDIV_4_1_gc = (0x02<<0), /* Divide B by 4 and C by 1 */ - CLK_PSBCDIV_2_2_gc = (0x03<<0), /* Divide B by 2 and C by 2 */ -} CLK_PSBCDIV_t; - -/* RTC Clock Source */ -typedef enum CLK_RTCSRC_enum -{ - CLK_RTCSRC_ULP_gc = (0x00<<1), /* 1.024 kHz from internal 32kHz ULP */ - CLK_RTCSRC_TOSC_gc = (0x01<<1), /* 1.024 kHz from 32.768 kHz crystal oscillator on TOSC */ - CLK_RTCSRC_RCOSC_gc = (0x02<<1), /* 1.024 kHz from internal 32.768 kHz RC oscillator */ - CLK_RTCSRC_TOSC32_gc = (0x05<<1), /* 32.768 kHz from 32.768 kHz crystal oscillator on TOSC */ - CLK_RTCSRC_RCOSC32_gc = (0x06<<1), /* 32.768 kHz from internal 32.768 kHz RC oscillator */ - CLK_RTCSRC_EXTCLK_gc = (0x07<<1), /* External Clock from TOSC1 */ -} CLK_RTCSRC_t; - -/* USB Prescaler Division Factor */ -typedef enum CLK_USBPSDIV_enum -{ - CLK_USBPSDIV_1_gc = (0x00<<3), /* Divide by 1 */ - CLK_USBPSDIV_2_gc = (0x01<<3), /* Divide by 2 */ - CLK_USBPSDIV_4_gc = (0x02<<3), /* Divide by 4 */ - CLK_USBPSDIV_8_gc = (0x03<<3), /* Divide by 8 */ - CLK_USBPSDIV_16_gc = (0x04<<3), /* Divide by 16 */ - CLK_USBPSDIV_32_gc = (0x05<<3), /* Divide by 32 */ -} CLK_USBPSDIV_t; - -/* USB Clock Source */ -typedef enum CLK_USBSRC_enum -{ - CLK_USBSRC_PLL_gc = (0x00<<1), /* PLL */ - CLK_USBSRC_RC32M_gc = (0x01<<1), /* Internal 32 MHz RC Oscillator */ -} CLK_USBSRC_t; - - -/* --------------------------------------------------------------------------- -SLEEP - Sleep Controller --------------------------------------------------------------------------- -*/ - -/* Sleep Controller */ -typedef struct SLEEP_struct -{ - register8_t CTRL; /* Control Register */ -} SLEEP_t; - -/* Sleep Mode */ -typedef enum SLEEP_SMODE_enum -{ - SLEEP_SMODE_IDLE_gc = (0x00<<1), /* Idle mode */ - SLEEP_SMODE_PDOWN_gc = (0x02<<1), /* Power-down Mode */ - SLEEP_SMODE_PSAVE_gc = (0x03<<1), /* Power-save Mode */ - SLEEP_SMODE_STDBY_gc = (0x06<<1), /* Standby Mode */ - SLEEP_SMODE_ESTDBY_gc = (0x07<<1), /* Extended Standby Mode */ -} SLEEP_SMODE_t; - - - -#define SLEEP_MODE_IDLE (0x00<<1) -#define SLEEP_MODE_PWR_DOWN (0x02<<1) -#define SLEEP_MODE_PWR_SAVE (0x03<<1) -#define SLEEP_MODE_STANDBY (0x06<<1) -#define SLEEP_MODE_EXT_STANDBY (0x07<<1) -/* --------------------------------------------------------------------------- -OSC - Oscillator --------------------------------------------------------------------------- -*/ - -/* Oscillator */ -typedef struct OSC_struct -{ - register8_t CTRL; /* Control Register */ - register8_t STATUS; /* Status Register */ - register8_t XOSCCTRL; /* External Oscillator Control Register */ - register8_t XOSCFAIL; /* Oscillator Failure Detection Register */ - register8_t RC32KCAL; /* 32.768 kHz Internal Oscillator Calibration Register */ - register8_t PLLCTRL; /* PLL Control Register */ - register8_t DFLLCTRL; /* DFLL Control Register */ -} OSC_t; - -/* Oscillator Frequency Range */ -typedef enum OSC_FRQRANGE_enum -{ - OSC_FRQRANGE_04TO2_gc = (0x00<<6), /* 0.4 - 2 MHz */ - OSC_FRQRANGE_2TO9_gc = (0x01<<6), /* 2 - 9 MHz */ - OSC_FRQRANGE_9TO12_gc = (0x02<<6), /* 9 - 12 MHz */ - OSC_FRQRANGE_12TO16_gc = (0x03<<6), /* 12 - 16 MHz */ -} OSC_FRQRANGE_t; - -/* External Oscillator Selection and Startup Time */ -typedef enum OSC_XOSCSEL_enum -{ - OSC_XOSCSEL_EXTCLK_gc = (0x00<<0), /* External Clock - 6 CLK */ - OSC_XOSCSEL_32KHz_gc = (0x02<<0), /* 32.768 kHz TOSC - 32K CLK */ - OSC_XOSCSEL_XTAL_256CLK_gc = (0x03<<0), /* 0.4-16 MHz XTAL - 256 CLK */ - OSC_XOSCSEL_XTAL_1KCLK_gc = (0x07<<0), /* 0.4-16 MHz XTAL - 1K CLK */ - OSC_XOSCSEL_XTAL_16KCLK_gc = (0x0B<<0), /* 0.4-16 MHz XTAL - 16K CLK */ -} OSC_XOSCSEL_t; - -/* PLL Clock Source */ -typedef enum OSC_PLLSRC_enum -{ - OSC_PLLSRC_RC2M_gc = (0x00<<6), /* Internal 2 MHz RC Oscillator */ - OSC_PLLSRC_RC32M_gc = (0x02<<6), /* Internal 32 MHz RC Oscillator */ - OSC_PLLSRC_XOSC_gc = (0x03<<6), /* External Oscillator */ -} OSC_PLLSRC_t; - -/* 2 MHz DFLL Calibration Reference */ -typedef enum OSC_RC2MCREF_enum -{ - OSC_RC2MCREF_RC32K_gc = (0x00<<0), /* Internal 32.768 kHz RC Oscillator */ - OSC_RC2MCREF_XOSC32K_gc = (0x01<<0), /* External 32.768 kHz Crystal Oscillator */ -} OSC_RC2MCREF_t; - -/* 32 MHz DFLL Calibration Reference */ -typedef enum OSC_RC32MCREF_enum -{ - OSC_RC32MCREF_RC32K_gc = (0x00<<1), /* Internal 32.768 kHz RC Oscillator */ - OSC_RC32MCREF_XOSC32K_gc = (0x01<<1), /* External 32.768 kHz Crystal Oscillator */ - OSC_RC32MCREF_USBSOF_gc = (0x02<<1), /* USB Start of Frame */ -} OSC_RC32MCREF_t; - - -/* --------------------------------------------------------------------------- -DFLL - DFLL --------------------------------------------------------------------------- -*/ - -/* DFLL */ -typedef struct DFLL_struct -{ - register8_t CTRL; /* Control Register */ - register8_t reserved_0x01; - register8_t CALA; /* Calibration Register A */ - register8_t CALB; /* Calibration Register B */ - register8_t COMP0; /* Oscillator Compare Register 0 */ - register8_t COMP1; /* Oscillator Compare Register 1 */ - register8_t COMP2; /* Oscillator Compare Register 2 */ - register8_t reserved_0x07; -} DFLL_t; - - -/* --------------------------------------------------------------------------- -RST - Reset --------------------------------------------------------------------------- -*/ - -/* Reset */ -typedef struct RST_struct -{ - register8_t STATUS; /* Status Register */ - register8_t CTRL; /* Control Register */ -} RST_t; - - -/* --------------------------------------------------------------------------- -WDT - Watch-Dog Timer --------------------------------------------------------------------------- -*/ - -/* Watch-Dog Timer */ -typedef struct WDT_struct -{ - register8_t CTRL; /* Control */ - register8_t WINCTRL; /* Windowed Mode Control */ - register8_t STATUS; /* Status */ -} WDT_t; - -/* Period setting */ -typedef enum WDT_PER_enum -{ - WDT_PER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ - WDT_PER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ - WDT_PER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ - WDT_PER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ - WDT_PER_128CLK_gc = (0x04<<2), /* 128 cycles (0.128s @ 3.3V) */ - WDT_PER_256CLK_gc = (0x05<<2), /* 256 cycles (0.256s @ 3.3V) */ - WDT_PER_512CLK_gc = (0x06<<2), /* 512 cycles (0.512s @ 3.3V) */ - WDT_PER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ - WDT_PER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ - WDT_PER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ - WDT_PER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ -} WDT_PER_t; - -/* Closed window period */ -typedef enum WDT_WPER_enum -{ - WDT_WPER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ - WDT_WPER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ - WDT_WPER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ - WDT_WPER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ - WDT_WPER_128CLK_gc = (0x04<<2), /* 128 cycles (0.128s @ 3.3V) */ - WDT_WPER_256CLK_gc = (0x05<<2), /* 256 cycles (0.256s @ 3.3V) */ - WDT_WPER_512CLK_gc = (0x06<<2), /* 512 cycles (0.512s @ 3.3V) */ - WDT_WPER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ - WDT_WPER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ - WDT_WPER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ - WDT_WPER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ -} WDT_WPER_t; - - -/* --------------------------------------------------------------------------- -MCU - MCU Control --------------------------------------------------------------------------- -*/ - -/* MCU Control */ -typedef struct MCU_struct -{ - register8_t DEVID0; /* Device ID byte 0 */ - register8_t DEVID1; /* Device ID byte 1 */ - register8_t DEVID2; /* Device ID byte 2 */ - register8_t REVID; /* Revision ID */ - register8_t JTAGUID; /* JTAG User ID */ - register8_t reserved_0x05; - register8_t MCUCR; /* MCU Control */ - register8_t ANAINIT; /* Analog Startup Delay */ - register8_t EVSYSLOCK; /* Event System Lock */ - register8_t AWEXLOCK; /* AWEX Lock */ - register8_t reserved_0x0A; - register8_t reserved_0x0B; -} MCU_t; - - -/* --------------------------------------------------------------------------- -PMIC - Programmable Multi-level Interrupt Controller --------------------------------------------------------------------------- -*/ - -/* Programmable Multi-level Interrupt Controller */ -typedef struct PMIC_struct -{ - register8_t STATUS; /* Status Register */ - register8_t INTPRI; /* Interrupt Priority */ - register8_t CTRL; /* Control Register */ - register8_t reserved_0x03; - register8_t reserved_0x04; - register8_t reserved_0x05; - register8_t reserved_0x06; - register8_t reserved_0x07; - register8_t reserved_0x08; - register8_t reserved_0x09; - register8_t reserved_0x0A; - register8_t reserved_0x0B; - register8_t reserved_0x0C; - register8_t reserved_0x0D; - register8_t reserved_0x0E; - register8_t reserved_0x0F; -} PMIC_t; - - -/* --------------------------------------------------------------------------- -PORTCFG - Port Configuration --------------------------------------------------------------------------- -*/ - -/* I/O port Configuration */ -typedef struct PORTCFG_struct -{ - register8_t MPCMASK; /* Multi-pin Configuration Mask */ - register8_t reserved_0x01; - register8_t VPCTRLA; /* Virtual Port Control Register A */ - register8_t VPCTRLB; /* Virtual Port Control Register B */ - register8_t CLKEVOUT; /* Clock and Event Out Register */ - register8_t EBIOUT; /* EBI Output register */ - register8_t EVOUTSEL; /* Event Output Select */ -} PORTCFG_t; - -/* Virtual Port Mapping */ -typedef enum PORTCFG_VP02MAP_enum -{ - PORTCFG_VP02MAP_PORTA_gc = (0x00<<0), /* Mapped To PORTA */ - PORTCFG_VP02MAP_PORTB_gc = (0x01<<0), /* Mapped To PORTB */ - PORTCFG_VP02MAP_PORTC_gc = (0x02<<0), /* Mapped To PORTC */ - PORTCFG_VP02MAP_PORTD_gc = (0x03<<0), /* Mapped To PORTD */ - PORTCFG_VP02MAP_PORTE_gc = (0x04<<0), /* Mapped To PORTE */ - PORTCFG_VP02MAP_PORTF_gc = (0x05<<0), /* Mapped To PORTF */ - PORTCFG_VP02MAP_PORTG_gc = (0x06<<0), /* Mapped To PORTG */ - PORTCFG_VP02MAP_PORTH_gc = (0x07<<0), /* Mapped To PORTH */ - PORTCFG_VP02MAP_PORTJ_gc = (0x08<<0), /* Mapped To PORTJ */ - PORTCFG_VP02MAP_PORTK_gc = (0x09<<0), /* Mapped To PORTK */ - PORTCFG_VP02MAP_PORTL_gc = (0x0A<<0), /* Mapped To PORTL */ - PORTCFG_VP02MAP_PORTM_gc = (0x0B<<0), /* Mapped To PORTM */ - PORTCFG_VP02MAP_PORTN_gc = (0x0C<<0), /* Mapped To PORTN */ - PORTCFG_VP02MAP_PORTP_gc = (0x0D<<0), /* Mapped To PORTP */ - PORTCFG_VP02MAP_PORTQ_gc = (0x0E<<0), /* Mapped To PORTQ */ - PORTCFG_VP02MAP_PORTR_gc = (0x0F<<0), /* Mapped To PORTR */ -} PORTCFG_VP02MAP_t; - -/* Virtual Port Mapping */ -typedef enum PORTCFG_VP13MAP_enum -{ - PORTCFG_VP13MAP_PORTA_gc = (0x00<<4), /* Mapped To PORTA */ - PORTCFG_VP13MAP_PORTB_gc = (0x01<<4), /* Mapped To PORTB */ - PORTCFG_VP13MAP_PORTC_gc = (0x02<<4), /* Mapped To PORTC */ - PORTCFG_VP13MAP_PORTD_gc = (0x03<<4), /* Mapped To PORTD */ - PORTCFG_VP13MAP_PORTE_gc = (0x04<<4), /* Mapped To PORTE */ - PORTCFG_VP13MAP_PORTF_gc = (0x05<<4), /* Mapped To PORTF */ - PORTCFG_VP13MAP_PORTG_gc = (0x06<<4), /* Mapped To PORTG */ - PORTCFG_VP13MAP_PORTH_gc = (0x07<<4), /* Mapped To PORTH */ - PORTCFG_VP13MAP_PORTJ_gc = (0x08<<4), /* Mapped To PORTJ */ - PORTCFG_VP13MAP_PORTK_gc = (0x09<<4), /* Mapped To PORTK */ - PORTCFG_VP13MAP_PORTL_gc = (0x0A<<4), /* Mapped To PORTL */ - PORTCFG_VP13MAP_PORTM_gc = (0x0B<<4), /* Mapped To PORTM */ - PORTCFG_VP13MAP_PORTN_gc = (0x0C<<4), /* Mapped To PORTN */ - PORTCFG_VP13MAP_PORTP_gc = (0x0D<<4), /* Mapped To PORTP */ - PORTCFG_VP13MAP_PORTQ_gc = (0x0E<<4), /* Mapped To PORTQ */ - PORTCFG_VP13MAP_PORTR_gc = (0x0F<<4), /* Mapped To PORTR */ -} PORTCFG_VP13MAP_t; - -/* System Clock Output Port */ -typedef enum PORTCFG_CLKOUT_enum -{ - PORTCFG_CLKOUT_OFF_gc = (0x00<<0), /* System Clock Output Disabled */ - PORTCFG_CLKOUT_PC7_gc = (0x01<<0), /* System Clock Output on Port C pin 7 */ - PORTCFG_CLKOUT_PD7_gc = (0x02<<0), /* System Clock Output on Port D pin 7 */ - PORTCFG_CLKOUT_PE7_gc = (0x03<<0), /* System Clock Output on Port E pin 7 */ -} PORTCFG_CLKOUT_t; - -/* Peripheral Clock Output Select */ -typedef enum PORTCFG_CLKOUTSEL_enum -{ - PORTCFG_CLKOUTSEL_CLK1X_gc = (0x00<<2), /* 1x Peripheral Clock Output to pin */ - PORTCFG_CLKOUTSEL_CLK2X_gc = (0x01<<2), /* 2x Peripheral Clock Output to pin */ - PORTCFG_CLKOUTSEL_CLK4X_gc = (0x02<<2), /* 4x Peripheral Clock Output to pin */ -} PORTCFG_CLKOUTSEL_t; - -/* Event Output Port */ -typedef enum PORTCFG_EVOUT_enum -{ - PORTCFG_EVOUT_OFF_gc = (0x00<<4), /* Event Output Disabled */ - PORTCFG_EVOUT_PC7_gc = (0x01<<4), /* Event Channel 7 Output on Port C pin 7 */ - PORTCFG_EVOUT_PD7_gc = (0x02<<4), /* Event Channel 7 Output on Port D pin 7 */ - PORTCFG_EVOUT_PE7_gc = (0x03<<4), /* Event Channel 7 Output on Port E pin 7 */ -} PORTCFG_EVOUT_t; - -/* Clock and Event Output Port */ -typedef enum PORTCFG_CLKEVPIN_enum -{ - PORTCFG_CLKEVPIN_PIN7_gc = (0x00<<7), /* Clock and Event Ouput on PIN 7 */ - PORTCFG_CLKEVPIN_PIN4_gc = (0x01<<7), /* Clock and Event Ouput on PIN 4 */ -} PORTCFG_CLKEVPIN_t; - -/* EBI Address Output Port */ -typedef enum PORTCFG_EBIADROUT_enum -{ - PORTCFG_EBIADROUT_PF_gc = (0x00<<2), /* EBI port 3 address output on PORTF pins 0 to 7 */ - PORTCFG_EBIADROUT_PE_gc = (0x01<<2), /* EBI port 3 address output on PORTE pins 0 to 7 */ - PORTCFG_EBIADROUT_PFH_gc = (0x02<<2), /* EBI port 3 address output on PORTF pins 4 to 7 */ - PORTCFG_EBIADROUT_PEH_gc = (0x03<<2), /* EBI port 3 address output on PORTE pins 4 to 7 */ -} PORTCFG_EBIADROUT_t; - -/* EBI Chip Select Output Port */ -typedef enum PORTCFG_EBICSOUT_enum -{ - PORTCFG_EBICSOUT_PH_gc = (0x00<<0), /* EBI chip select output to PORTH pin 4 to 7 */ - PORTCFG_EBICSOUT_PL_gc = (0x01<<0), /* EBI chip select output to PORTL pin 4 to 7 */ - PORTCFG_EBICSOUT_PF_gc = (0x02<<0), /* EBI chip select output to PORTF pin 4 to 7 */ - PORTCFG_EBICSOUT_PE_gc = (0x03<<0), /* EBI chip select output to PORTE pin 4 to 7 */ -} PORTCFG_EBICSOUT_t; - -/* Event Output Select */ -typedef enum PORTCFG_EVOUTSEL_enum -{ - PORTCFG_EVOUTSEL_0_gc = (0x00<<0), /* Event Channel 0 output to pin */ - PORTCFG_EVOUTSEL_1_gc = (0x01<<0), /* Event Channel 1 output to pin */ - PORTCFG_EVOUTSEL_2_gc = (0x02<<0), /* Event Channel 2 output to pin */ - PORTCFG_EVOUTSEL_3_gc = (0x03<<0), /* Event Channel 3 output to pin */ - PORTCFG_EVOUTSEL_4_gc = (0x04<<0), /* Event Channel 4 output to pin */ - PORTCFG_EVOUTSEL_5_gc = (0x05<<0), /* Event Channel 5 output to pin */ - PORTCFG_EVOUTSEL_6_gc = (0x06<<0), /* Event Channel 6 output to pin */ - PORTCFG_EVOUTSEL_7_gc = (0x07<<0), /* Event Channel 7 output to pin */ -} PORTCFG_EVOUTSEL_t; - - -/* --------------------------------------------------------------------------- -AES - AES Module --------------------------------------------------------------------------- -*/ - -/* AES Module */ -typedef struct AES_struct -{ - register8_t CTRL; /* AES Control Register */ - register8_t STATUS; /* AES Status Register */ - register8_t STATE; /* AES State Register */ - register8_t KEY; /* AES Key Register */ - register8_t INTCTRL; /* AES Interrupt Control Register */ -} AES_t; - -/* Interrupt level */ -typedef enum AES_INTLVL_enum -{ - AES_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - AES_INTLVL_LO_gc = (0x01<<0), /* Low Level */ - AES_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ - AES_INTLVL_HI_gc = (0x03<<0), /* High Level */ -} AES_INTLVL_t; - - -/* --------------------------------------------------------------------------- -CRC - Cyclic Redundancy Checker --------------------------------------------------------------------------- -*/ - -/* Cyclic Redundancy Checker */ -typedef struct CRC_struct -{ - register8_t CTRL; /* Control Register */ - register8_t STATUS; /* Status Register */ - register8_t reserved_0x02; - register8_t DATAIN; /* Data Input */ - register8_t CHECKSUM0; /* Checksum byte 0 */ - register8_t CHECKSUM1; /* Checksum byte 1 */ - register8_t CHECKSUM2; /* Checksum byte 2 */ - register8_t CHECKSUM3; /* Checksum byte 3 */ -} CRC_t; - -/* Reset */ -typedef enum CRC_RESET_enum -{ - CRC_RESET_NO_gc = (0x00<<6), /* No Reset */ - CRC_RESET_RESET0_gc = (0x02<<6), /* Reset CRC with CHECKSUM to all zeros */ - CRC_RESET_RESET1_gc = (0x03<<6), /* Reset CRC with CHECKSUM to all ones */ -} CRC_RESET_t; - -/* Input Source */ -typedef enum CRC_SOURCE_enum -{ - CRC_SOURCE_DISABLE_gc = (0x00<<0), /* Disabled */ - CRC_SOURCE_IO_gc = (0x01<<0), /* I/O Interface */ - CRC_SOURCE_FLASH_gc = (0x02<<0), /* Flash */ - CRC_SOURCE_DMAC0_gc = (0x04<<0), /* DMAC Channel 0 */ - CRC_SOURCE_DMAC1_gc = (0x05<<0), /* DMAC Channel 1 */ - CRC_SOURCE_DMAC2_gc = (0x06<<0), /* DMAC Channel 2 */ - CRC_SOURCE_DMAC3_gc = (0x07<<0), /* DMAC Channel 3 */ -} CRC_SOURCE_t; - - -/* --------------------------------------------------------------------------- -DMA - DMA Controller --------------------------------------------------------------------------- -*/ - -/* DMA Channel */ -typedef struct DMA_CH_struct -{ - register8_t CTRLA; /* Channel Control */ - register8_t CTRLB; /* Channel Control */ - register8_t ADDRCTRL; /* Address Control */ - register8_t TRIGSRC; /* Channel Trigger Source */ - _WORDREGISTER(TRFCNT); /* Channel Block Transfer Count */ - register8_t REPCNT; /* Channel Repeat Count */ - register8_t reserved_0x07; - register8_t SRCADDR0; /* Channel Source Address 0 */ - register8_t SRCADDR1; /* Channel Source Address 1 */ - register8_t SRCADDR2; /* Channel Source Address 2 */ - register8_t reserved_0x0B; - register8_t DESTADDR0; /* Channel Destination Address 0 */ - register8_t DESTADDR1; /* Channel Destination Address 1 */ - register8_t DESTADDR2; /* Channel Destination Address 2 */ - register8_t reserved_0x0F; -} DMA_CH_t; - - -/* DMA Controller */ -typedef struct DMA_struct -{ - register8_t CTRL; /* Control */ - register8_t reserved_0x01; - register8_t reserved_0x02; - register8_t INTFLAGS; /* Transfer Interrupt Status */ - register8_t STATUS; /* Status */ - register8_t reserved_0x05; - _WORDREGISTER(TEMP); /* Temporary Register For 16/24-bit Access */ - register8_t reserved_0x08; - register8_t reserved_0x09; - register8_t reserved_0x0A; - register8_t reserved_0x0B; - register8_t reserved_0x0C; - register8_t reserved_0x0D; - register8_t reserved_0x0E; - register8_t reserved_0x0F; - DMA_CH_t CH0; /* DMA Channel 0 */ - DMA_CH_t CH1; /* DMA Channel 1 */ - DMA_CH_t CH2; /* DMA Channel 2 */ - DMA_CH_t CH3; /* DMA Channel 3 */ -} DMA_t; - -/* Burst mode */ -typedef enum DMA_CH_BURSTLEN_enum -{ - DMA_CH_BURSTLEN_1BYTE_gc = (0x00<<0), /* 1-byte burst mode */ - DMA_CH_BURSTLEN_2BYTE_gc = (0x01<<0), /* 2-byte burst mode */ - DMA_CH_BURSTLEN_4BYTE_gc = (0x02<<0), /* 4-byte burst mode */ - DMA_CH_BURSTLEN_8BYTE_gc = (0x03<<0), /* 8-byte burst mode */ -} DMA_CH_BURSTLEN_t; - -/* Source address reload mode */ -typedef enum DMA_CH_SRCRELOAD_enum -{ - DMA_CH_SRCRELOAD_NONE_gc = (0x00<<6), /* No reload */ - DMA_CH_SRCRELOAD_BLOCK_gc = (0x01<<6), /* Reload at end of block */ - DMA_CH_SRCRELOAD_BURST_gc = (0x02<<6), /* Reload at end of burst */ - DMA_CH_SRCRELOAD_TRANSACTION_gc = (0x03<<6), /* Reload at end of transaction */ -} DMA_CH_SRCRELOAD_t; - -/* Source addressing mode */ -typedef enum DMA_CH_SRCDIR_enum -{ - DMA_CH_SRCDIR_FIXED_gc = (0x00<<4), /* Fixed */ - DMA_CH_SRCDIR_INC_gc = (0x01<<4), /* Increment */ - DMA_CH_SRCDIR_DEC_gc = (0x02<<4), /* Decrement */ -} DMA_CH_SRCDIR_t; - -/* Destination adress reload mode */ -typedef enum DMA_CH_DESTRELOAD_enum -{ - DMA_CH_DESTRELOAD_NONE_gc = (0x00<<2), /* No reload */ - DMA_CH_DESTRELOAD_BLOCK_gc = (0x01<<2), /* Reload at end of block */ - DMA_CH_DESTRELOAD_BURST_gc = (0x02<<2), /* Reload at end of burst */ - DMA_CH_DESTRELOAD_TRANSACTION_gc = (0x03<<2), /* Reload at end of transaction */ -} DMA_CH_DESTRELOAD_t; - -/* Destination adressing mode */ -typedef enum DMA_CH_DESTDIR_enum -{ - DMA_CH_DESTDIR_FIXED_gc = (0x00<<0), /* Fixed */ - DMA_CH_DESTDIR_INC_gc = (0x01<<0), /* Increment */ - DMA_CH_DESTDIR_DEC_gc = (0x02<<0), /* Decrement */ -} DMA_CH_DESTDIR_t; - -/* Transfer trigger source */ -typedef enum DMA_CH_TRIGSRC_enum -{ - DMA_CH_TRIGSRC_OFF_gc = (0x00<<0), /* Off software triggers only */ - DMA_CH_TRIGSRC_EVSYS_CH0_gc = (0x01<<0), /* Event System Channel 0 */ - DMA_CH_TRIGSRC_EVSYS_CH1_gc = (0x02<<0), /* Event System Channel 1 */ - DMA_CH_TRIGSRC_EVSYS_CH2_gc = (0x03<<0), /* Event System Channel 2 */ - DMA_CH_TRIGSRC_ADCA_CH0_gc = (0x10<<0), /* ADCA Channel 0 */ - DMA_CH_TRIGSRC_ADCA_CH1_gc = (0x11<<0), /* ADCA Channel 1 */ - DMA_CH_TRIGSRC_ADCA_CH2_gc = (0x12<<0), /* ADCA Channel 2 */ - DMA_CH_TRIGSRC_ADCA_CH3_gc = (0x13<<0), /* ADCA Channel 3 */ - DMA_CH_TRIGSRC_ADCA_CH4_gc = (0x14<<0), /* ADCA Channel 0,1,2,3 combined */ - DMA_CH_TRIGSRC_DACA_CH0_gc = (0x15<<0), /* DACA Channel 0 */ - DMA_CH_TRIGSRC_DACA_CH1_gc = (0x16<<0), /* DACA Channel 1 */ - DMA_CH_TRIGSRC_ADCB_CH0_gc = (0x20<<0), /* ADCB Channel 0 */ - DMA_CH_TRIGSRC_ADCB_CH1_gc = (0x21<<0), /* ADCB Channel 1 */ - DMA_CH_TRIGSRC_ADCB_CH2_gc = (0x22<<0), /* ADCB Channel 2 */ - DMA_CH_TRIGSRC_ADCB_CH3_gc = (0x23<<0), /* ADCB Channel 3 */ - DMA_CH_TRIGSRC_ADCB_CH4_gc = (0x24<<0), /* ADCB Channel 0,1,2,3 combined */ - DMA_CH_TRIGSRC_DACB_CH0_gc = (0x25<<0), /* DACB Channel 0 */ - DMA_CH_TRIGSRC_DACB_CH1_gc = (0x26<<0), /* DACB Channel 1 */ - DMA_CH_TRIGSRC_TCC0_OVF_gc = (0x40<<0), /* Timer/Counter C0 Overflow */ - DMA_CH_TRIGSRC_TCC0_ERR_gc = (0x41<<0), /* Timer/Counter C0 Error */ - DMA_CH_TRIGSRC_TCC0_CCA_gc = (0x42<<0), /* Timer/Counter C0 Compare or Capture A */ - DMA_CH_TRIGSRC_TCC0_CCB_gc = (0x43<<0), /* Timer/Counter C0 Compare or Capture B */ - DMA_CH_TRIGSRC_TCC0_CCC_gc = (0x44<<0), /* Timer/Counter C0 Compare or Capture C */ - DMA_CH_TRIGSRC_TCC0_CCD_gc = (0x45<<0), /* Timer/Counter C0 Compare or Capture D */ - DMA_CH_TRIGSRC_TCC1_OVF_gc = (0x46<<0), /* Timer/Counter C1 Overflow */ - DMA_CH_TRIGSRC_TCC1_ERR_gc = (0x47<<0), /* Timer/Counter C1 Error */ - DMA_CH_TRIGSRC_TCC1_CCA_gc = (0x48<<0), /* Timer/Counter C1 Compare or Capture A */ - DMA_CH_TRIGSRC_TCC1_CCB_gc = (0x49<<0), /* Timer/Counter C1 Compare or Capture B */ - DMA_CH_TRIGSRC_SPIC_gc = (0x4A<<0), /* SPI C Transfer Complete */ - DMA_CH_TRIGSRC_USARTC0_RXC_gc = (0x4B<<0), /* USART C0 Receive Complete */ - DMA_CH_TRIGSRC_USARTC0_DRE_gc = (0x4C<<0), /* USART C0 Data Register Empty */ - DMA_CH_TRIGSRC_USARTC1_RXC_gc = (0x4E<<0), /* USART C1 Receive Complete */ - DMA_CH_TRIGSRC_USARTC1_DRE_gc = (0x4F<<0), /* USART C1 Data Register Empty */ - DMA_CH_TRIGSRC_TCD0_OVF_gc = (0x60<<0), /* Timer/Counter D0 Overflow */ - DMA_CH_TRIGSRC_TCD0_ERR_gc = (0x61<<0), /* Timer/Counter D0 Error */ - DMA_CH_TRIGSRC_TCD0_CCA_gc = (0x62<<0), /* Timer/Counter D0 Compare or Capture A */ - DMA_CH_TRIGSRC_TCD0_CCB_gc = (0x63<<0), /* Timer/Counter D0 Compare or Capture B */ - DMA_CH_TRIGSRC_TCD0_CCC_gc = (0x64<<0), /* Timer/Counter D0 Compare or Capture C */ - DMA_CH_TRIGSRC_TCD0_CCD_gc = (0x65<<0), /* Timer/Counter D0 Compare or Capture D */ - DMA_CH_TRIGSRC_TCD1_OVF_gc = (0x66<<0), /* Timer/Counter D1 Overflow */ - DMA_CH_TRIGSRC_TCD1_ERR_gc = (0x67<<0), /* Timer/Counter D1 Error */ - DMA_CH_TRIGSRC_TCD1_CCA_gc = (0x68<<0), /* Timer/Counter D1 Compare or Capture A */ - DMA_CH_TRIGSRC_TCD1_CCB_gc = (0x69<<0), /* Timer/Counter D1 Compare or Capture B */ - DMA_CH_TRIGSRC_SPID_gc = (0x6A<<0), /* SPI D Transfer Complete */ - DMA_CH_TRIGSRC_USARTD0_RXC_gc = (0x6B<<0), /* USART D0 Receive Complete */ - DMA_CH_TRIGSRC_USARTD0_DRE_gc = (0x6C<<0), /* USART D0 Data Register Empty */ - DMA_CH_TRIGSRC_USARTD1_RXC_gc = (0x6E<<0), /* USART D1 Receive Complete */ - DMA_CH_TRIGSRC_USARTD1_DRE_gc = (0x6F<<0), /* USART D1 Data Register Empty */ - DMA_CH_TRIGSRC_TCE0_OVF_gc = (0x80<<0), /* Timer/Counter E0 Overflow */ - DMA_CH_TRIGSRC_TCE0_ERR_gc = (0x81<<0), /* Timer/Counter E0 Error */ - DMA_CH_TRIGSRC_TCE0_CCA_gc = (0x82<<0), /* Timer/Counter E0 Compare or Capture A */ - DMA_CH_TRIGSRC_TCE0_CCB_gc = (0x83<<0), /* Timer/Counter E0 Compare or Capture B */ - DMA_CH_TRIGSRC_TCE0_CCC_gc = (0x84<<0), /* Timer/Counter E0 Compare or Capture C */ - DMA_CH_TRIGSRC_TCE0_CCD_gc = (0x85<<0), /* Timer/Counter E0 Compare or Capture D */ - DMA_CH_TRIGSRC_TCE1_OVF_gc = (0x86<<0), /* Timer/Counter E1 Overflow */ - DMA_CH_TRIGSRC_TCE1_ERR_gc = (0x87<<0), /* Timer/Counter E1 Error */ - DMA_CH_TRIGSRC_TCE1_CCA_gc = (0x88<<0), /* Timer/Counter E1 Compare or Capture A */ - DMA_CH_TRIGSRC_TCE1_CCB_gc = (0x89<<0), /* Timer/Counter E1 Compare or Capture B */ - DMA_CH_TRIGSRC_SPIE_gc = (0x8A<<0), /* SPI E Transfer Complete */ - DMA_CH_TRIGSRC_USARTE0_RXC_gc = (0x8B<<0), /* USART E0 Receive Complete */ - DMA_CH_TRIGSRC_USARTE0_DRE_gc = (0x8C<<0), /* USART E0 Data Register Empty */ - DMA_CH_TRIGSRC_USARTE1_RXC_gc = (0x8E<<0), /* USART E1 Receive Complete */ - DMA_CH_TRIGSRC_USARTE1_DRE_gc = (0x8F<<0), /* USART E1 Data Register Empty */ - DMA_CH_TRIGSRC_TCF0_OVF_gc = (0xA0<<0), /* Timer/Counter F0 Overflow */ - DMA_CH_TRIGSRC_TCF0_ERR_gc = (0xA1<<0), /* Timer/Counter F0 Error */ - DMA_CH_TRIGSRC_TCF0_CCA_gc = (0xA2<<0), /* Timer/Counter F0 Compare or Capture A */ - DMA_CH_TRIGSRC_TCF0_CCB_gc = (0xA3<<0), /* Timer/Counter F0 Compare or Capture B */ - DMA_CH_TRIGSRC_TCF0_CCC_gc = (0xA4<<0), /* Timer/Counter F0 Compare or Capture C */ - DMA_CH_TRIGSRC_TCF0_CCD_gc = (0xA5<<0), /* Timer/Counter F0 Compare or Capture D */ - DMA_CH_TRIGSRC_TCF1_OVF_gc = (0xA6<<0), /* Timer/Counter F1 Overflow */ - DMA_CH_TRIGSRC_TCF1_ERR_gc = (0xA7<<0), /* Timer/Counter F1 Error */ - DMA_CH_TRIGSRC_TCF1_CCA_gc = (0xA8<<0), /* Timer/Counter F1 Compare or Capture A */ - DMA_CH_TRIGSRC_TCF1_CCB_gc = (0xA9<<0), /* Timer/Counter F1 Compare or Capture B */ - DMA_CH_TRIGSRC_SPIF_gc = (0xAA<<0), /* SPI F Transfer Complete */ - DMA_CH_TRIGSRC_USARTF0_RXC_gc = (0xAB<<0), /* USART F0 Receive Complete */ - DMA_CH_TRIGSRC_USARTF0_DRE_gc = (0xAC<<0), /* USART F0 Data Register Empty */ - DMA_CH_TRIGSRC_USARTF1_RXC_gc = (0xAE<<0), /* USART F1 Receive Complete */ - DMA_CH_TRIGSRC_USARTF1_DRE_gc = (0xAF<<0), /* USART F1 Data Register Empty */ -} DMA_CH_TRIGSRC_t; - -/* Double buffering mode */ -typedef enum DMA_DBUFMODE_enum -{ - DMA_DBUFMODE_DISABLED_gc = (0x00<<2), /* Double buffering disabled */ - DMA_DBUFMODE_CH01_gc = (0x01<<2), /* Double buffering enabled on channel 0/1 */ - DMA_DBUFMODE_CH23_gc = (0x02<<2), /* Double buffering enabled on channel 2/3 */ - DMA_DBUFMODE_CH01CH23_gc = (0x03<<2), /* Double buffering enabled on ch. 0/1 and ch. 2/3 */ -} DMA_DBUFMODE_t; - -/* Priority mode */ -typedef enum DMA_PRIMODE_enum -{ - DMA_PRIMODE_RR0123_gc = (0x00<<0), /* Round Robin */ - DMA_PRIMODE_CH0RR123_gc = (0x01<<0), /* Channel 0 > Round Robin on channel 1/2/3 */ - DMA_PRIMODE_CH01RR23_gc = (0x02<<0), /* Channel 0 > channel 1 > Round Robin on channel 2/3 */ - DMA_PRIMODE_CH0123_gc = (0x03<<0), /* Channel 0 > channel 1 > channel 2 > channel 3 */ -} DMA_PRIMODE_t; - -/* Interrupt level */ -typedef enum DMA_CH_ERRINTLVL_enum -{ - DMA_CH_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ - DMA_CH_ERRINTLVL_LO_gc = (0x01<<2), /* Low level */ - DMA_CH_ERRINTLVL_MED_gc = (0x02<<2), /* Medium level */ - DMA_CH_ERRINTLVL_HI_gc = (0x03<<2), /* High level */ -} DMA_CH_ERRINTLVL_t; - -/* Interrupt level */ -typedef enum DMA_CH_TRNINTLVL_enum -{ - DMA_CH_TRNINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ - DMA_CH_TRNINTLVL_LO_gc = (0x01<<0), /* Low level */ - DMA_CH_TRNINTLVL_MED_gc = (0x02<<0), /* Medium level */ - DMA_CH_TRNINTLVL_HI_gc = (0x03<<0), /* High level */ -} DMA_CH_TRNINTLVL_t; - - -/* --------------------------------------------------------------------------- -EVSYS - Event System --------------------------------------------------------------------------- -*/ - -/* Event System */ -typedef struct EVSYS_struct -{ - register8_t CH0MUX; /* Event Channel 0 Multiplexer */ - register8_t CH1MUX; /* Event Channel 1 Multiplexer */ - register8_t CH2MUX; /* Event Channel 2 Multiplexer */ - register8_t CH3MUX; /* Event Channel 3 Multiplexer */ - register8_t CH4MUX; /* Event Channel 4 Multiplexer */ - register8_t CH5MUX; /* Event Channel 5 Multiplexer */ - register8_t CH6MUX; /* Event Channel 6 Multiplexer */ - register8_t CH7MUX; /* Event Channel 7 Multiplexer */ - register8_t CH0CTRL; /* Channel 0 Control Register */ - register8_t CH1CTRL; /* Channel 1 Control Register */ - register8_t CH2CTRL; /* Channel 2 Control Register */ - register8_t CH3CTRL; /* Channel 3 Control Register */ - register8_t CH4CTRL; /* Channel 4 Control Register */ - register8_t CH5CTRL; /* Channel 5 Control Register */ - register8_t CH6CTRL; /* Channel 6 Control Register */ - register8_t CH7CTRL; /* Channel 7 Control Register */ - register8_t STROBE; /* Event Strobe */ - register8_t DATA; /* Event Data */ -} EVSYS_t; - -/* Quadrature Decoder Index Recognition Mode */ -typedef enum EVSYS_QDIRM_enum -{ - EVSYS_QDIRM_00_gc = (0x00<<5), /* QDPH0 = 0, QDPH90 = 0 */ - EVSYS_QDIRM_01_gc = (0x01<<5), /* QDPH0 = 0, QDPH90 = 1 */ - EVSYS_QDIRM_10_gc = (0x02<<5), /* QDPH0 = 1, QDPH90 = 0 */ - EVSYS_QDIRM_11_gc = (0x03<<5), /* QDPH0 = 1, QDPH90 = 1 */ -} EVSYS_QDIRM_t; - -/* Digital filter coefficient */ -typedef enum EVSYS_DIGFILT_enum -{ - EVSYS_DIGFILT_1SAMPLE_gc = (0x00<<0), /* 1 SAMPLE */ - EVSYS_DIGFILT_2SAMPLES_gc = (0x01<<0), /* 2 SAMPLES */ - EVSYS_DIGFILT_3SAMPLES_gc = (0x02<<0), /* 3 SAMPLES */ - EVSYS_DIGFILT_4SAMPLES_gc = (0x03<<0), /* 4 SAMPLES */ - EVSYS_DIGFILT_5SAMPLES_gc = (0x04<<0), /* 5 SAMPLES */ - EVSYS_DIGFILT_6SAMPLES_gc = (0x05<<0), /* 6 SAMPLES */ - EVSYS_DIGFILT_7SAMPLES_gc = (0x06<<0), /* 7 SAMPLES */ - EVSYS_DIGFILT_8SAMPLES_gc = (0x07<<0), /* 8 SAMPLES */ -} EVSYS_DIGFILT_t; - -/* Event Channel multiplexer input selection */ -typedef enum EVSYS_CHMUX_enum -{ - EVSYS_CHMUX_OFF_gc = (0x00<<0), /* Off */ - EVSYS_CHMUX_RTC_OVF_gc = (0x08<<0), /* RTC Overflow */ - EVSYS_CHMUX_RTC_CMP_gc = (0x09<<0), /* RTC Compare Match */ - EVSYS_CHMUX_USB_gc = (0x0A<<0), /* USB Setup, SOF, CRC error and UNF/OVF */ - EVSYS_CHMUX_ACA_CH0_gc = (0x10<<0), /* Analog Comparator A Channel 0 */ - EVSYS_CHMUX_ACA_CH1_gc = (0x11<<0), /* Analog Comparator A Channel 1 */ - EVSYS_CHMUX_ACA_WIN_gc = (0x12<<0), /* Analog Comparator A Window */ - EVSYS_CHMUX_ACB_CH0_gc = (0x13<<0), /* Analog Comparator B Channel 0 */ - EVSYS_CHMUX_ACB_CH1_gc = (0x14<<0), /* Analog Comparator B Channel 1 */ - EVSYS_CHMUX_ACB_WIN_gc = (0x15<<0), /* Analog Comparator B Window */ - EVSYS_CHMUX_ADCA_CH0_gc = (0x20<<0), /* ADC A Channel 0 */ - EVSYS_CHMUX_ADCA_CH1_gc = (0x21<<0), /* ADC A Channel 1 */ - EVSYS_CHMUX_ADCA_CH2_gc = (0x22<<0), /* ADC A Channel 2 */ - EVSYS_CHMUX_ADCA_CH3_gc = (0x23<<0), /* ADC A Channel 3 */ - EVSYS_CHMUX_ADCB_CH0_gc = (0x24<<0), /* ADC B Channel 0 */ - EVSYS_CHMUX_ADCB_CH1_gc = (0x25<<0), /* ADC B Channel 1 */ - EVSYS_CHMUX_ADCB_CH2_gc = (0x26<<0), /* ADC B Channel 2 */ - EVSYS_CHMUX_ADCB_CH3_gc = (0x27<<0), /* ADC B Channel 3 */ - EVSYS_CHMUX_PORTA_PIN0_gc = (0x50<<0), /* Port A, Pin0 */ - EVSYS_CHMUX_PORTA_PIN1_gc = (0x51<<0), /* Port A, Pin1 */ - EVSYS_CHMUX_PORTA_PIN2_gc = (0x52<<0), /* Port A, Pin2 */ - EVSYS_CHMUX_PORTA_PIN3_gc = (0x53<<0), /* Port A, Pin3 */ - EVSYS_CHMUX_PORTA_PIN4_gc = (0x54<<0), /* Port A, Pin4 */ - EVSYS_CHMUX_PORTA_PIN5_gc = (0x55<<0), /* Port A, Pin5 */ - EVSYS_CHMUX_PORTA_PIN6_gc = (0x56<<0), /* Port A, Pin6 */ - EVSYS_CHMUX_PORTA_PIN7_gc = (0x57<<0), /* Port A, Pin7 */ - EVSYS_CHMUX_PORTB_PIN0_gc = (0x58<<0), /* Port B, Pin0 */ - EVSYS_CHMUX_PORTB_PIN1_gc = (0x59<<0), /* Port B, Pin1 */ - EVSYS_CHMUX_PORTB_PIN2_gc = (0x5A<<0), /* Port B, Pin2 */ - EVSYS_CHMUX_PORTB_PIN3_gc = (0x5B<<0), /* Port B, Pin3 */ - EVSYS_CHMUX_PORTB_PIN4_gc = (0x5C<<0), /* Port B, Pin4 */ - EVSYS_CHMUX_PORTB_PIN5_gc = (0x5D<<0), /* Port B, Pin5 */ - EVSYS_CHMUX_PORTB_PIN6_gc = (0x5E<<0), /* Port B, Pin6 */ - EVSYS_CHMUX_PORTB_PIN7_gc = (0x5F<<0), /* Port B, Pin7 */ - EVSYS_CHMUX_PORTC_PIN0_gc = (0x60<<0), /* Port C, Pin0 */ - EVSYS_CHMUX_PORTC_PIN1_gc = (0x61<<0), /* Port C, Pin1 */ - EVSYS_CHMUX_PORTC_PIN2_gc = (0x62<<0), /* Port C, Pin2 */ - EVSYS_CHMUX_PORTC_PIN3_gc = (0x63<<0), /* Port C, Pin3 */ - EVSYS_CHMUX_PORTC_PIN4_gc = (0x64<<0), /* Port C, Pin4 */ - EVSYS_CHMUX_PORTC_PIN5_gc = (0x65<<0), /* Port C, Pin5 */ - EVSYS_CHMUX_PORTC_PIN6_gc = (0x66<<0), /* Port C, Pin6 */ - EVSYS_CHMUX_PORTC_PIN7_gc = (0x67<<0), /* Port C, Pin7 */ - EVSYS_CHMUX_PORTD_PIN0_gc = (0x68<<0), /* Port D, Pin0 */ - EVSYS_CHMUX_PORTD_PIN1_gc = (0x69<<0), /* Port D, Pin1 */ - EVSYS_CHMUX_PORTD_PIN2_gc = (0x6A<<0), /* Port D, Pin2 */ - EVSYS_CHMUX_PORTD_PIN3_gc = (0x6B<<0), /* Port D, Pin3 */ - EVSYS_CHMUX_PORTD_PIN4_gc = (0x6C<<0), /* Port D, Pin4 */ - EVSYS_CHMUX_PORTD_PIN5_gc = (0x6D<<0), /* Port D, Pin5 */ - EVSYS_CHMUX_PORTD_PIN6_gc = (0x6E<<0), /* Port D, Pin6 */ - EVSYS_CHMUX_PORTD_PIN7_gc = (0x6F<<0), /* Port D, Pin7 */ - EVSYS_CHMUX_PORTE_PIN0_gc = (0x70<<0), /* Port E, Pin0 */ - EVSYS_CHMUX_PORTE_PIN1_gc = (0x71<<0), /* Port E, Pin1 */ - EVSYS_CHMUX_PORTE_PIN2_gc = (0x72<<0), /* Port E, Pin2 */ - EVSYS_CHMUX_PORTE_PIN3_gc = (0x73<<0), /* Port E, Pin3 */ - EVSYS_CHMUX_PORTE_PIN4_gc = (0x74<<0), /* Port E, Pin4 */ - EVSYS_CHMUX_PORTE_PIN5_gc = (0x75<<0), /* Port E, Pin5 */ - EVSYS_CHMUX_PORTE_PIN6_gc = (0x76<<0), /* Port E, Pin6 */ - EVSYS_CHMUX_PORTE_PIN7_gc = (0x77<<0), /* Port E, Pin7 */ - EVSYS_CHMUX_PORTF_PIN0_gc = (0x78<<0), /* Port F, Pin0 */ - EVSYS_CHMUX_PORTF_PIN1_gc = (0x79<<0), /* Port F, Pin1 */ - EVSYS_CHMUX_PORTF_PIN2_gc = (0x7A<<0), /* Port F, Pin2 */ - EVSYS_CHMUX_PORTF_PIN3_gc = (0x7B<<0), /* Port F, Pin3 */ - EVSYS_CHMUX_PORTF_PIN4_gc = (0x7C<<0), /* Port F, Pin4 */ - EVSYS_CHMUX_PORTF_PIN5_gc = (0x7D<<0), /* Port F, Pin5 */ - EVSYS_CHMUX_PORTF_PIN6_gc = (0x7E<<0), /* Port F, Pin6 */ - EVSYS_CHMUX_PORTF_PIN7_gc = (0x7F<<0), /* Port F, Pin7 */ - EVSYS_CHMUX_PRESCALER_1_gc = (0x80<<0), /* Prescaler, divide by 1 */ - EVSYS_CHMUX_PRESCALER_2_gc = (0x81<<0), /* Prescaler, divide by 2 */ - EVSYS_CHMUX_PRESCALER_4_gc = (0x82<<0), /* Prescaler, divide by 4 */ - EVSYS_CHMUX_PRESCALER_8_gc = (0x83<<0), /* Prescaler, divide by 8 */ - EVSYS_CHMUX_PRESCALER_16_gc = (0x84<<0), /* Prescaler, divide by 16 */ - EVSYS_CHMUX_PRESCALER_32_gc = (0x85<<0), /* Prescaler, divide by 32 */ - EVSYS_CHMUX_PRESCALER_64_gc = (0x86<<0), /* Prescaler, divide by 64 */ - EVSYS_CHMUX_PRESCALER_128_gc = (0x87<<0), /* Prescaler, divide by 128 */ - EVSYS_CHMUX_PRESCALER_256_gc = (0x88<<0), /* Prescaler, divide by 256 */ - EVSYS_CHMUX_PRESCALER_512_gc = (0x89<<0), /* Prescaler, divide by 512 */ - EVSYS_CHMUX_PRESCALER_1024_gc = (0x8A<<0), /* Prescaler, divide by 1024 */ - EVSYS_CHMUX_PRESCALER_2048_gc = (0x8B<<0), /* Prescaler, divide by 2048 */ - EVSYS_CHMUX_PRESCALER_4096_gc = (0x8C<<0), /* Prescaler, divide by 4096 */ - EVSYS_CHMUX_PRESCALER_8192_gc = (0x8D<<0), /* Prescaler, divide by 8192 */ - EVSYS_CHMUX_PRESCALER_16384_gc = (0x8E<<0), /* Prescaler, divide by 16384 */ - EVSYS_CHMUX_PRESCALER_32768_gc = (0x8F<<0), /* Prescaler, divide by 32768 */ - EVSYS_CHMUX_TCC0_OVF_gc = (0xC0<<0), /* Timer/Counter C0 Overflow */ - EVSYS_CHMUX_TCC0_ERR_gc = (0xC1<<0), /* Timer/Counter C0 Error */ - EVSYS_CHMUX_TCC0_CCA_gc = (0xC4<<0), /* Timer/Counter C0 Compare or Capture A */ - EVSYS_CHMUX_TCC0_CCB_gc = (0xC5<<0), /* Timer/Counter C0 Compare or Capture B */ - EVSYS_CHMUX_TCC0_CCC_gc = (0xC6<<0), /* Timer/Counter C0 Compare or Capture C */ - EVSYS_CHMUX_TCC0_CCD_gc = (0xC7<<0), /* Timer/Counter C0 Compare or Capture D */ - EVSYS_CHMUX_TCC1_OVF_gc = (0xC8<<0), /* Timer/Counter C1 Overflow */ - EVSYS_CHMUX_TCC1_ERR_gc = (0xC9<<0), /* Timer/Counter C1 Error */ - EVSYS_CHMUX_TCC1_CCA_gc = (0xCC<<0), /* Timer/Counter C1 Compare or Capture A */ - EVSYS_CHMUX_TCC1_CCB_gc = (0xCD<<0), /* Timer/Counter C1 Compare or Capture B */ - EVSYS_CHMUX_TCD0_OVF_gc = (0xD0<<0), /* Timer/Counter D0 Overflow */ - EVSYS_CHMUX_TCD0_ERR_gc = (0xD1<<0), /* Timer/Counter D0 Error */ - EVSYS_CHMUX_TCD0_CCA_gc = (0xD4<<0), /* Timer/Counter D0 Compare or Capture A */ - EVSYS_CHMUX_TCD0_CCB_gc = (0xD5<<0), /* Timer/Counter D0 Compare or Capture B */ - EVSYS_CHMUX_TCD0_CCC_gc = (0xD6<<0), /* Timer/Counter D0 Compare or Capture C */ - EVSYS_CHMUX_TCD0_CCD_gc = (0xD7<<0), /* Timer/Counter D0 Compare or Capture D */ - EVSYS_CHMUX_TCD1_OVF_gc = (0xD8<<0), /* Timer/Counter D1 Overflow */ - EVSYS_CHMUX_TCD1_ERR_gc = (0xD9<<0), /* Timer/Counter D1 Error */ - EVSYS_CHMUX_TCD1_CCA_gc = (0xDC<<0), /* Timer/Counter D1 Compare or Capture A */ - EVSYS_CHMUX_TCD1_CCB_gc = (0xDD<<0), /* Timer/Counter D1 Compare or Capture B */ - EVSYS_CHMUX_TCE0_OVF_gc = (0xE0<<0), /* Timer/Counter E0 Overflow */ - EVSYS_CHMUX_TCE0_ERR_gc = (0xE1<<0), /* Timer/Counter E0 Error */ - EVSYS_CHMUX_TCE0_CCA_gc = (0xE4<<0), /* Timer/Counter E0 Compare or Capture A */ - EVSYS_CHMUX_TCE0_CCB_gc = (0xE5<<0), /* Timer/Counter E0 Compare or Capture B */ - EVSYS_CHMUX_TCE0_CCC_gc = (0xE6<<0), /* Timer/Counter E0 Compare or Capture C */ - EVSYS_CHMUX_TCE0_CCD_gc = (0xE7<<0), /* Timer/Counter E0 Compare or Capture D */ - EVSYS_CHMUX_TCE1_OVF_gc = (0xE8<<0), /* Timer/Counter E1 Overflow */ - EVSYS_CHMUX_TCE1_ERR_gc = (0xE9<<0), /* Timer/Counter E1 Error */ - EVSYS_CHMUX_TCE1_CCA_gc = (0xEC<<0), /* Timer/Counter E1 Compare or Capture A */ - EVSYS_CHMUX_TCE1_CCB_gc = (0xED<<0), /* Timer/Counter E1 Compare or Capture B */ - EVSYS_CHMUX_TCF0_OVF_gc = (0xF0<<0), /* Timer/Counter F0 Overflow */ - EVSYS_CHMUX_TCF0_ERR_gc = (0xF1<<0), /* Timer/Counter F0 Error */ - EVSYS_CHMUX_TCF0_CCA_gc = (0xF4<<0), /* Timer/Counter F0 Compare or Capture A */ - EVSYS_CHMUX_TCF0_CCB_gc = (0xF5<<0), /* Timer/Counter F0 Compare or Capture B */ - EVSYS_CHMUX_TCF0_CCC_gc = (0xF6<<0), /* Timer/Counter F0 Compare or Capture C */ - EVSYS_CHMUX_TCF0_CCD_gc = (0xF7<<0), /* Timer/Counter F0 Compare or Capture D */ - EVSYS_CHMUX_TCF1_OVF_gc = (0xF8<<0), /* Timer/Counter F1 Overflow */ - EVSYS_CHMUX_TCF1_ERR_gc = (0xF9<<0), /* Timer/Counter F1 Error */ - EVSYS_CHMUX_TCF1_CCA_gc = (0xFC<<0), /* Timer/Counter F1 Compare or Capture A */ - EVSYS_CHMUX_TCF1_CCB_gc = (0xFD<<0), /* Timer/Counter F1 Compare or Capture B */ -} EVSYS_CHMUX_t; - - -/* --------------------------------------------------------------------------- -NVM - Non Volatile Memory Controller --------------------------------------------------------------------------- -*/ - -/* Non-volatile Memory Controller */ -typedef struct NVM_struct -{ - register8_t ADDR0; /* Address Register 0 */ - register8_t ADDR1; /* Address Register 1 */ - register8_t ADDR2; /* Address Register 2 */ - register8_t reserved_0x03; - register8_t DATA0; /* Data Register 0 */ - register8_t DATA1; /* Data Register 1 */ - register8_t DATA2; /* Data Register 2 */ - register8_t reserved_0x07; - register8_t reserved_0x08; - register8_t reserved_0x09; - register8_t CMD; /* Command */ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t INTCTRL; /* Interrupt Control */ - register8_t reserved_0x0E; - register8_t STATUS; /* Status */ - register8_t LOCK_BITS; /* Lock Bits (Changed from LOCKBITS to avoid avr-libc collision) */ -} NVM_t; - -/* NVM Command */ -typedef enum NVM_CMD_enum -{ - NVM_CMD_NO_OPERATION_gc = (0x00<<0), /* Noop/Ordinary LPM */ - NVM_CMD_READ_USER_SIG_ROW_gc = (0x01<<0), /* Read user signature row */ - NVM_CMD_READ_CALIB_ROW_gc = (0x02<<0), /* Read calibration row */ - NVM_CMD_READ_EEPROM_gc = (0x06<<0), /* Read EEPROM */ - NVM_CMD_READ_FUSES_gc = (0x07<<0), /* Read fuse byte */ - NVM_CMD_WRITE_LOCK_BITS_gc = (0x08<<0), /* Write lock bits */ - NVM_CMD_ERASE_USER_SIG_ROW_gc = (0x18<<0), /* Erase user signature row */ - NVM_CMD_WRITE_USER_SIG_ROW_gc = (0x1A<<0), /* Write user signature row */ - NVM_CMD_ERASE_APP_gc = (0x20<<0), /* Erase Application Section */ - NVM_CMD_ERASE_APP_PAGE_gc = (0x22<<0), /* Erase Application Section page */ - NVM_CMD_LOAD_FLASH_BUFFER_gc = (0x23<<0), /* Load Flash page buffer */ - NVM_CMD_WRITE_APP_PAGE_gc = (0x24<<0), /* Write Application Section page */ - NVM_CMD_ERASE_WRITE_APP_PAGE_gc = (0x25<<0), /* Erase-and-write Application Section page */ - NVM_CMD_ERASE_FLASH_BUFFER_gc = (0x26<<0), /* Erase/flush Flash page buffer */ - NVM_CMD_ERASE_BOOT_PAGE_gc = (0x2A<<0), /* Erase Boot Section page */ - NVM_CMD_ERASE_FLASH_PAGE_gc = (0x2B<<0), /* Erase Flash Page */ - NVM_CMD_WRITE_BOOT_PAGE_gc = (0x2C<<0), /* Write Boot Section page */ - NVM_CMD_ERASE_WRITE_BOOT_PAGE_gc = (0x2D<<0), /* Erase-and-write Boot Section page */ - NVM_CMD_WRITE_FLASH_PAGE_gc = (0x2E<<0), /* Write Flash Page */ - NVM_CMD_ERASE_WRITE_FLASH_PAGE_gc = (0x2F<<0), /* Erase-and-write Flash Page */ - NVM_CMD_ERASE_EEPROM_gc = (0x30<<0), /* Erase EEPROM */ - NVM_CMD_ERASE_EEPROM_PAGE_gc = (0x32<<0), /* Erase EEPROM page */ - NVM_CMD_LOAD_EEPROM_BUFFER_gc = (0x33<<0), /* Load EEPROM page buffer */ - NVM_CMD_WRITE_EEPROM_PAGE_gc = (0x34<<0), /* Write EEPROM page */ - NVM_CMD_ERASE_WRITE_EEPROM_PAGE_gc = (0x35<<0), /* Erase-and-write EEPROM page */ - NVM_CMD_ERASE_EEPROM_BUFFER_gc = (0x36<<0), /* Erase/flush EEPROM page buffer */ - NVM_CMD_APP_CRC_gc = (0x38<<0), /* Application section CRC */ - NVM_CMD_BOOT_CRC_gc = (0x39<<0), /* Boot Section CRC */ - NVM_CMD_FLASH_RANGE_CRC_gc = (0x3A<<0), /* Flash Range CRC */ - NVM_CMD_CHIP_ERASE_gc = (0x40<<0), /* Erase Chip */ - NVM_CMD_READ_NVM_gc = (0x43<<0), /* Read NVM */ - NVM_CMD_WRITE_FUSE_gc = (0x4C<<0), /* Write Fuse byte */ - NVM_CMD_ERASE_BOOT_gc = (0x68<<0), /* Erase Boot Section */ - NVM_CMD_FLASH_CRC_gc = (0x78<<0), /* Flash CRC */ -} NVM_CMD_t; - -/* SPM ready interrupt level */ -typedef enum NVM_SPMLVL_enum -{ - NVM_SPMLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ - NVM_SPMLVL_LO_gc = (0x01<<2), /* Low level */ - NVM_SPMLVL_MED_gc = (0x02<<2), /* Medium level */ - NVM_SPMLVL_HI_gc = (0x03<<2), /* High level */ -} NVM_SPMLVL_t; - -/* EEPROM ready interrupt level */ -typedef enum NVM_EELVL_enum -{ - NVM_EELVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ - NVM_EELVL_LO_gc = (0x01<<0), /* Low level */ - NVM_EELVL_MED_gc = (0x02<<0), /* Medium level */ - NVM_EELVL_HI_gc = (0x03<<0), /* High level */ -} NVM_EELVL_t; - -/* Boot lock bits - boot setcion */ -typedef enum NVM_BLBB_enum -{ - NVM_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ - NVM_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ - NVM_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ - NVM_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ -} NVM_BLBB_t; - -/* Boot lock bits - application section */ -typedef enum NVM_BLBA_enum -{ - NVM_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ - NVM_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ - NVM_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ - NVM_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ -} NVM_BLBA_t; - -/* Boot lock bits - application table section */ -typedef enum NVM_BLBAT_enum -{ - NVM_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ - NVM_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ - NVM_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ - NVM_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ -} NVM_BLBAT_t; - -/* Lock bits */ -typedef enum NVM_LB_enum -{ - NVM_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ - NVM_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ - NVM_LB_NOLOCK_gc = (0x03<<0), /* No locks */ -} NVM_LB_t; - - -/* --------------------------------------------------------------------------- -ADC - Analog/Digital Converter --------------------------------------------------------------------------- -*/ - -/* ADC Channel */ -typedef struct ADC_CH_struct -{ - register8_t CTRL; /* Control Register */ - register8_t MUXCTRL; /* MUX Control */ - register8_t INTCTRL; /* Channel Interrupt Control Register */ - register8_t INTFLAGS; /* Interrupt Flags */ - _WORDREGISTER(RES); /* Channel Result */ - register8_t SCAN; /* Input Channel Scan */ - register8_t reserved_0x07; -} ADC_CH_t; - - -/* Analog-to-Digital Converter */ -typedef struct ADC_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t REFCTRL; /* Reference Control */ - register8_t EVCTRL; /* Event Control */ - register8_t PRESCALER; /* Clock Prescaler */ - register8_t reserved_0x05; - register8_t INTFLAGS; /* Interrupt Flags */ - register8_t TEMP; /* Temporary Register */ - register8_t reserved_0x08; - register8_t reserved_0x09; - register8_t reserved_0x0A; - register8_t reserved_0x0B; - _WORDREGISTER(CAL); /* Calibration Value */ - register8_t reserved_0x0E; - register8_t reserved_0x0F; - _WORDREGISTER(CH0RES); /* Channel 0 Result */ - _WORDREGISTER(CH1RES); /* Channel 1 Result */ - _WORDREGISTER(CH2RES); /* Channel 2 Result */ - _WORDREGISTER(CH3RES); /* Channel 3 Result */ - _WORDREGISTER(CMP); /* Compare Value */ - register8_t reserved_0x1A; - register8_t reserved_0x1B; - register8_t reserved_0x1C; - register8_t reserved_0x1D; - register8_t reserved_0x1E; - register8_t reserved_0x1F; - ADC_CH_t CH0; /* ADC Channel 0 */ - ADC_CH_t CH1; /* ADC Channel 1 */ - ADC_CH_t CH2; /* ADC Channel 2 */ - ADC_CH_t CH3; /* ADC Channel 3 */ -} ADC_t; - -/* Positive input multiplexer selection */ -typedef enum ADC_CH_MUXPOS_enum -{ - ADC_CH_MUXPOS_PIN0_gc = (0x00<<3), /* Input pin 0 */ - ADC_CH_MUXPOS_PIN1_gc = (0x01<<3), /* Input pin 1 */ - ADC_CH_MUXPOS_PIN2_gc = (0x02<<3), /* Input pin 2 */ - ADC_CH_MUXPOS_PIN3_gc = (0x03<<3), /* Input pin 3 */ - ADC_CH_MUXPOS_PIN4_gc = (0x04<<3), /* Input pin 4 */ - ADC_CH_MUXPOS_PIN5_gc = (0x05<<3), /* Input pin 5 */ - ADC_CH_MUXPOS_PIN6_gc = (0x06<<3), /* Input pin 6 */ - ADC_CH_MUXPOS_PIN7_gc = (0x07<<3), /* Input pin 7 */ - ADC_CH_MUXPOS_PIN8_gc = (0x08<<3), /* Input pin 8 */ - ADC_CH_MUXPOS_PIN9_gc = (0x09<<3), /* Input pin 9 */ - ADC_CH_MUXPOS_PIN10_gc = (0x0A<<3), /* Input pin 10 */ - ADC_CH_MUXPOS_PIN11_gc = (0x0B<<3), /* Input pin 11 */ - ADC_CH_MUXPOS_PIN12_gc = (0x0C<<3), /* Input pin 12 */ - ADC_CH_MUXPOS_PIN13_gc = (0x0D<<3), /* Input pin 13 */ - ADC_CH_MUXPOS_PIN14_gc = (0x0E<<3), /* Input pin 14 */ - ADC_CH_MUXPOS_PIN15_gc = (0x0F<<3), /* Input pin 15 */ -} ADC_CH_MUXPOS_t; - -/* Internal input multiplexer selections */ -typedef enum ADC_CH_MUXINT_enum -{ - ADC_CH_MUXINT_TEMP_gc = (0x00<<3), /* Temperature Reference */ - ADC_CH_MUXINT_BANDGAP_gc = (0x01<<3), /* Bandgap Reference */ - ADC_CH_MUXINT_SCALEDVCC_gc = (0x02<<3), /* 1/10 scaled VCC */ - ADC_CH_MUXINT_DAC_gc = (0x03<<3), /* DAC output */ -} ADC_CH_MUXINT_t; - -/* Negative input multiplexer selection */ -typedef enum ADC_CH_MUXNEG_enum -{ - ADC_CH_MUXNEG_PIN0_gc = (0x00<<0), /* Input pin 0 (Input Mode = 2) */ - ADC_CH_MUXNEG_PIN1_gc = (0x01<<0), /* Input pin 1 (Input Mode = 2) */ - ADC_CH_MUXNEG_PIN2_gc = (0x02<<0), /* Input pin 2 (Input Mode = 2) */ - ADC_CH_MUXNEG_PIN3_gc = (0x03<<0), /* Input pin 3 (Input Mode = 2) */ - ADC_CH_MUXNEG_PIN4_gc = (0x00<<0), /* Input pin 4 (Input Mode = 3) */ - ADC_CH_MUXNEG_PIN5_gc = (0x01<<0), /* Input pin 5 (Input Mode = 3) */ - ADC_CH_MUXNEG_PIN6_gc = (0x02<<0), /* Input pin 6 (Input Mode = 3) */ - ADC_CH_MUXNEG_PIN7_gc = (0x03<<0), /* Input pin 7 (Input Mode = 3) */ - ADC_CH_MUXNEG_GND_MODE3_gc = (0x05<<0), /* PAD Ground (Input Mode = 2) */ - ADC_CH_MUXNEG_INTGND_MODE3_gc = (0x07<<0), /* Internal Ground (Input Mode = 2) */ - ADC_CH_MUXNEG_INTGND_MODE4_gc = (0x04<<0), /* Internal Ground (Input Mode = 3) */ - ADC_CH_MUXNEG_GND_MODE4_gc = (0x07<<0), /* PAD Ground (Input Mode = 3) */ -} ADC_CH_MUXNEG_t; - -/* Input mode */ -typedef enum ADC_CH_INPUTMODE_enum -{ - ADC_CH_INPUTMODE_INTERNAL_gc = (0x00<<0), /* Internal inputs, no gain */ - ADC_CH_INPUTMODE_SINGLEENDED_gc = (0x01<<0), /* Single-ended input, no gain */ - ADC_CH_INPUTMODE_DIFF_gc = (0x02<<0), /* Differential input, no gain */ - ADC_CH_INPUTMODE_DIFFWGAIN_gc = (0x03<<0), /* Differential input, with gain */ -} ADC_CH_INPUTMODE_t; - -/* Gain factor */ -typedef enum ADC_CH_GAIN_enum -{ - ADC_CH_GAIN_1X_gc = (0x00<<2), /* 1x gain */ - ADC_CH_GAIN_2X_gc = (0x01<<2), /* 2x gain */ - ADC_CH_GAIN_4X_gc = (0x02<<2), /* 4x gain */ - ADC_CH_GAIN_8X_gc = (0x03<<2), /* 8x gain */ - ADC_CH_GAIN_16X_gc = (0x04<<2), /* 16x gain */ - ADC_CH_GAIN_32X_gc = (0x05<<2), /* 32x gain */ - ADC_CH_GAIN_64X_gc = (0x06<<2), /* 64x gain */ - ADC_CH_GAIN_DIV2_gc = (0x07<<2), /* x/2 gain */ -} ADC_CH_GAIN_t; - -/* Conversion result resolution */ -typedef enum ADC_RESOLUTION_enum -{ - ADC_RESOLUTION_12BIT_gc = (0x00<<1), /* 12-bit right-adjusted result */ - ADC_RESOLUTION_8BIT_gc = (0x02<<1), /* 8-bit right-adjusted result */ - ADC_RESOLUTION_LEFT12BIT_gc = (0x03<<1), /* 12-bit left-adjusted result */ -} ADC_RESOLUTION_t; - -/* Current Limitation Mode */ -typedef enum ADC_CURRLIMIT_enum -{ - ADC_CURRLIMIT_NO_gc = (0x00<<5), /* No limit */ - ADC_CURRLIMIT_LOW_gc = (0x01<<5), /* Low current limit, max. sampling rate 1.5MSPS */ - ADC_CURRLIMIT_MED_gc = (0x02<<5), /* Medium current limit, max. sampling rate 1MSPS */ - ADC_CURRLIMIT_HIGH_gc = (0x03<<5), /* High current limit, max. sampling rate 0.5MSPS */ -} ADC_CURRLIMIT_t; - -/* Voltage reference selection */ -typedef enum ADC_REFSEL_enum -{ - ADC_REFSEL_INT1V_gc = (0x00<<4), /* Internal 1V */ - ADC_REFSEL_INTVCC_gc = (0x01<<4), /* Internal VCC / 1.6 */ - ADC_REFSEL_AREFA_gc = (0x02<<4), /* External reference on PORT A */ - ADC_REFSEL_AREFB_gc = (0x03<<4), /* External reference on PORT B */ - ADC_REFSEL_INTVCC2_gc = (0x04<<4), /* Internal VCC / 2 */ -} ADC_REFSEL_t; - -/* Channel sweep selection */ -typedef enum ADC_SWEEP_enum -{ - ADC_SWEEP_0_gc = (0x00<<6), /* ADC Channel 0 */ - ADC_SWEEP_01_gc = (0x01<<6), /* ADC Channel 0,1 */ - ADC_SWEEP_012_gc = (0x02<<6), /* ADC Channel 0,1,2 */ - ADC_SWEEP_0123_gc = (0x03<<6), /* ADC Channel 0,1,2,3 */ -} ADC_SWEEP_t; - -/* Event channel input selection */ -typedef enum ADC_EVSEL_enum -{ - ADC_EVSEL_0123_gc = (0x00<<3), /* Event Channel 0,1,2,3 */ - ADC_EVSEL_1234_gc = (0x01<<3), /* Event Channel 1,2,3,4 */ - ADC_EVSEL_2345_gc = (0x02<<3), /* Event Channel 2,3,4,5 */ - ADC_EVSEL_3456_gc = (0x03<<3), /* Event Channel 3,4,5,6 */ - ADC_EVSEL_4567_gc = (0x04<<3), /* Event Channel 4,5,6,7 */ - ADC_EVSEL_567_gc = (0x05<<3), /* Event Channel 5,6,7 */ - ADC_EVSEL_67_gc = (0x06<<3), /* Event Channel 6,7 */ - ADC_EVSEL_7_gc = (0x07<<3), /* Event Channel 7 */ -} ADC_EVSEL_t; - -/* Event action selection */ -typedef enum ADC_EVACT_enum -{ - ADC_EVACT_NONE_gc = (0x00<<0), /* No event action */ - ADC_EVACT_CH0_gc = (0x01<<0), /* First event triggers channel 0 */ - ADC_EVACT_CH01_gc = (0x02<<0), /* First two events trigger channel 0,1 */ - ADC_EVACT_CH012_gc = (0x03<<0), /* First three events trigger channel 0,1,2 */ - ADC_EVACT_CH0123_gc = (0x04<<0), /* Events trigger channel 0,1,2,3 */ - ADC_EVACT_SWEEP_gc = (0x05<<0), /* First event triggers sweep */ - ADC_EVACT_SYNCSWEEP_gc = (0x06<<0), /* The ADC is flushed and restarted for accurate timing */ -} ADC_EVACT_t; - -/* Interupt mode */ -typedef enum ADC_CH_INTMODE_enum -{ - ADC_CH_INTMODE_COMPLETE_gc = (0x00<<2), /* Interrupt on conversion complete */ - ADC_CH_INTMODE_BELOW_gc = (0x01<<2), /* Interrupt on result below compare value */ - ADC_CH_INTMODE_ABOVE_gc = (0x03<<2), /* Interrupt on result above compare value */ -} ADC_CH_INTMODE_t; - -/* Interrupt level */ -typedef enum ADC_CH_INTLVL_enum -{ - ADC_CH_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ - ADC_CH_INTLVL_LO_gc = (0x01<<0), /* Low level */ - ADC_CH_INTLVL_MED_gc = (0x02<<0), /* Medium level */ - ADC_CH_INTLVL_HI_gc = (0x03<<0), /* High level */ -} ADC_CH_INTLVL_t; - -/* DMA request selection */ -typedef enum ADC_DMASEL_enum -{ - ADC_DMASEL_OFF_gc = (0x00<<6), /* Combined DMA request OFF */ - ADC_DMASEL_CH01_gc = (0x01<<6), /* ADC Channel 0 or 1 */ - ADC_DMASEL_CH012_gc = (0x02<<6), /* ADC Channel 0 or 1 or 2 */ - ADC_DMASEL_CH0123_gc = (0x03<<6), /* ADC Channel 0 or 1 or 2 or 3 */ -} ADC_DMASEL_t; - -/* Clock prescaler */ -typedef enum ADC_PRESCALER_enum -{ - ADC_PRESCALER_DIV4_gc = (0x00<<0), /* Divide clock by 4 */ - ADC_PRESCALER_DIV8_gc = (0x01<<0), /* Divide clock by 8 */ - ADC_PRESCALER_DIV16_gc = (0x02<<0), /* Divide clock by 16 */ - ADC_PRESCALER_DIV32_gc = (0x03<<0), /* Divide clock by 32 */ - ADC_PRESCALER_DIV64_gc = (0x04<<0), /* Divide clock by 64 */ - ADC_PRESCALER_DIV128_gc = (0x05<<0), /* Divide clock by 128 */ - ADC_PRESCALER_DIV256_gc = (0x06<<0), /* Divide clock by 256 */ - ADC_PRESCALER_DIV512_gc = (0x07<<0), /* Divide clock by 512 */ -} ADC_PRESCALER_t; - - -/* --------------------------------------------------------------------------- -DAC - Digital/Analog Converter --------------------------------------------------------------------------- -*/ - -/* Digital-to-Analog Converter */ -typedef struct DAC_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t CTRLC; /* Control Register C */ - register8_t EVCTRL; /* Event Input Control */ - register8_t reserved_0x04; - register8_t STATUS; /* Status */ - register8_t reserved_0x06; - register8_t reserved_0x07; - register8_t CH0GAINCAL; /* Gain Calibration */ - register8_t CH0OFFSETCAL; /* Offset Calibration */ - register8_t CH1GAINCAL; /* Gain Calibration */ - register8_t CH1OFFSETCAL; /* Offset Calibration */ - register8_t reserved_0x0C; - register8_t reserved_0x0D; - register8_t reserved_0x0E; - register8_t reserved_0x0F; - register8_t reserved_0x10; - register8_t reserved_0x11; - register8_t reserved_0x12; - register8_t reserved_0x13; - register8_t reserved_0x14; - register8_t reserved_0x15; - register8_t reserved_0x16; - register8_t reserved_0x17; - _WORDREGISTER(CH0DATA); /* Channel 0 Data */ - _WORDREGISTER(CH1DATA); /* Channel 1 Data */ -} DAC_t; - -/* Output channel selection */ -typedef enum DAC_CHSEL_enum -{ - DAC_CHSEL_SINGLE_gc = (0x00<<5), /* Single channel operation (Channel 0 only) */ - DAC_CHSEL_SINGLE1_gc = (0x01<<5), /* Single channel operation (Channel 1 only) */ - DAC_CHSEL_DUAL_gc = (0x02<<5), /* Dual channel operation (Channel 0 and channel 1) */ -} DAC_CHSEL_t; - -/* Reference voltage selection */ -typedef enum DAC_REFSEL_enum -{ - DAC_REFSEL_INT1V_gc = (0x00<<3), /* Internal 1V */ - DAC_REFSEL_AVCC_gc = (0x01<<3), /* Analog supply voltage */ - DAC_REFSEL_AREFA_gc = (0x02<<3), /* External reference on AREF on PORTA */ - DAC_REFSEL_AREFB_gc = (0x03<<3), /* External reference on AREF on PORTB */ -} DAC_REFSEL_t; - -/* Event channel selection */ -typedef enum DAC_EVSEL_enum -{ - DAC_EVSEL_0_gc = (0x00<<0), /* Event Channel 0 */ - DAC_EVSEL_1_gc = (0x01<<0), /* Event Channel 1 */ - DAC_EVSEL_2_gc = (0x02<<0), /* Event Channel 2 */ - DAC_EVSEL_3_gc = (0x03<<0), /* Event Channel 3 */ - DAC_EVSEL_4_gc = (0x04<<0), /* Event Channel 4 */ - DAC_EVSEL_5_gc = (0x05<<0), /* Event Channel 5 */ - DAC_EVSEL_6_gc = (0x06<<0), /* Event Channel 6 */ - DAC_EVSEL_7_gc = (0x07<<0), /* Event Channel 7 */ -} DAC_EVSEL_t; - - -/* --------------------------------------------------------------------------- -AC - Analog Comparator --------------------------------------------------------------------------- -*/ - -/* Analog Comparator */ -typedef struct AC_struct -{ - register8_t AC0CTRL; /* Analog Comparator 0 Control */ - register8_t AC1CTRL; /* Analog Comparator 1 Control */ - register8_t AC0MUXCTRL; /* Analog Comparator 0 MUX Control */ - register8_t AC1MUXCTRL; /* Analog Comparator 1 MUX Control */ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t WINCTRL; /* Window Mode Control */ - register8_t STATUS; /* Status */ -} AC_t; - -/* Interrupt mode */ -typedef enum AC_INTMODE_enum -{ - AC_INTMODE_BOTHEDGES_gc = (0x00<<6), /* Interrupt on both edges */ - AC_INTMODE_FALLING_gc = (0x02<<6), /* Interrupt on falling edge */ - AC_INTMODE_RISING_gc = (0x03<<6), /* Interrupt on rising edge */ -} AC_INTMODE_t; - -/* Interrupt level */ -typedef enum AC_INTLVL_enum -{ - AC_INTLVL_OFF_gc = (0x00<<4), /* Interrupt disabled */ - AC_INTLVL_LO_gc = (0x01<<4), /* Low level */ - AC_INTLVL_MED_gc = (0x02<<4), /* Medium level */ - AC_INTLVL_HI_gc = (0x03<<4), /* High level */ -} AC_INTLVL_t; - -/* Hysteresis mode selection */ -typedef enum AC_HYSMODE_enum -{ - AC_HYSMODE_NO_gc = (0x00<<1), /* No hysteresis */ - AC_HYSMODE_SMALL_gc = (0x01<<1), /* Small hysteresis */ - AC_HYSMODE_LARGE_gc = (0x02<<1), /* Large hysteresis */ -} AC_HYSMODE_t; - -/* Positive input multiplexer selection */ -typedef enum AC_MUXPOS_enum -{ - AC_MUXPOS_PIN0_gc = (0x00<<3), /* Pin 0 */ - AC_MUXPOS_PIN1_gc = (0x01<<3), /* Pin 1 */ - AC_MUXPOS_PIN2_gc = (0x02<<3), /* Pin 2 */ - AC_MUXPOS_PIN3_gc = (0x03<<3), /* Pin 3 */ - AC_MUXPOS_PIN4_gc = (0x04<<3), /* Pin 4 */ - AC_MUXPOS_PIN5_gc = (0x05<<3), /* Pin 5 */ - AC_MUXPOS_PIN6_gc = (0x06<<3), /* Pin 6 */ - AC_MUXPOS_DAC_gc = (0x07<<3), /* DAC output */ -} AC_MUXPOS_t; - -/* Negative input multiplexer selection */ -typedef enum AC_MUXNEG_enum -{ - AC_MUXNEG_PIN0_gc = (0x00<<0), /* Pin 0 */ - AC_MUXNEG_PIN1_gc = (0x01<<0), /* Pin 1 */ - AC_MUXNEG_PIN3_gc = (0x02<<0), /* Pin 3 */ - AC_MUXNEG_PIN5_gc = (0x03<<0), /* Pin 5 */ - AC_MUXNEG_PIN7_gc = (0x04<<0), /* Pin 7 */ - AC_MUXNEG_DAC_gc = (0x05<<0), /* DAC output */ - AC_MUXNEG_BANDGAP_gc = (0x06<<0), /* Bandgap Reference */ - AC_MUXNEG_SCALER_gc = (0x07<<0), /* Internal voltage scaler */ -} AC_MUXNEG_t; - -/* Windows interrupt mode */ -typedef enum AC_WINTMODE_enum -{ - AC_WINTMODE_ABOVE_gc = (0x00<<2), /* Interrupt on above window */ - AC_WINTMODE_INSIDE_gc = (0x01<<2), /* Interrupt on inside window */ - AC_WINTMODE_BELOW_gc = (0x02<<2), /* Interrupt on below window */ - AC_WINTMODE_OUTSIDE_gc = (0x03<<2), /* Interrupt on outside window */ -} AC_WINTMODE_t; - -/* Window interrupt level */ -typedef enum AC_WINTLVL_enum -{ - AC_WINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ - AC_WINTLVL_LO_gc = (0x01<<0), /* Low priority */ - AC_WINTLVL_MED_gc = (0x02<<0), /* Medium priority */ - AC_WINTLVL_HI_gc = (0x03<<0), /* High priority */ -} AC_WINTLVL_t; - -/* Window mode state */ -typedef enum AC_WSTATE_enum -{ - AC_WSTATE_ABOVE_gc = (0x00<<6), /* Signal above window */ - AC_WSTATE_INSIDE_gc = (0x01<<6), /* Signal inside window */ - AC_WSTATE_BELOW_gc = (0x02<<6), /* Signal below window */ -} AC_WSTATE_t; - - -/* --------------------------------------------------------------------------- -RTC - Real-Time Counter --------------------------------------------------------------------------- -*/ - -/* Real-Time Counter */ -typedef struct RTC_struct -{ - register8_t CTRL; /* Control Register */ - register8_t STATUS; /* Status Register */ - register8_t INTCTRL; /* Interrupt Control Register */ - register8_t INTFLAGS; /* Interrupt Flags */ - register8_t TEMP; /* Temporary register */ - register8_t reserved_0x05; - register8_t reserved_0x06; - register8_t reserved_0x07; - _WORDREGISTER(CNT); /* Count Register */ - _WORDREGISTER(PER); /* Period Register */ - _WORDREGISTER(COMP); /* Compare Register */ -} RTC_t; - -/* Prescaler Factor */ -typedef enum RTC_PRESCALER_enum -{ - RTC_PRESCALER_OFF_gc = (0x00<<0), /* RTC Off */ - RTC_PRESCALER_DIV1_gc = (0x01<<0), /* RTC Clock */ - RTC_PRESCALER_DIV2_gc = (0x02<<0), /* RTC Clock / 2 */ - RTC_PRESCALER_DIV8_gc = (0x03<<0), /* RTC Clock / 8 */ - RTC_PRESCALER_DIV16_gc = (0x04<<0), /* RTC Clock / 16 */ - RTC_PRESCALER_DIV64_gc = (0x05<<0), /* RTC Clock / 64 */ - RTC_PRESCALER_DIV256_gc = (0x06<<0), /* RTC Clock / 256 */ - RTC_PRESCALER_DIV1024_gc = (0x07<<0), /* RTC Clock / 1024 */ -} RTC_PRESCALER_t; - -/* Compare Interrupt level */ -typedef enum RTC_COMPINTLVL_enum -{ - RTC_COMPINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ - RTC_COMPINTLVL_LO_gc = (0x01<<2), /* Low Level */ - RTC_COMPINTLVL_MED_gc = (0x02<<2), /* Medium Level */ - RTC_COMPINTLVL_HI_gc = (0x03<<2), /* High Level */ -} RTC_COMPINTLVL_t; - -/* Overflow Interrupt level */ -typedef enum RTC_OVFINTLVL_enum -{ - RTC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - RTC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ - RTC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ - RTC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ -} RTC_OVFINTLVL_t; - - -/* --------------------------------------------------------------------------- -EBI - External Bus Interface --------------------------------------------------------------------------- -*/ - -/* EBI Chip Select Module */ -typedef struct EBI_CS_struct -{ - register8_t CTRLA; /* Chip Select Control Register A */ - register8_t CTRLB; /* Chip Select Control Register B */ - _WORDREGISTER(BASEADDR); /* Chip Select Base Address */ -} EBI_CS_t; - - -/* External Bus Interface */ -typedef struct EBI_struct -{ - register8_t CTRL; /* Control */ - register8_t SDRAMCTRLA; /* SDRAM Control Register A */ - register8_t reserved_0x02; - register8_t reserved_0x03; - _WORDREGISTER(REFRESH); /* SDRAM Refresh Period */ - _WORDREGISTER(INITDLY); /* SDRAM Initialization Delay */ - register8_t SDRAMCTRLB; /* SDRAM Control Register B */ - register8_t SDRAMCTRLC; /* SDRAM Control Register C */ - register8_t reserved_0x0A; - register8_t reserved_0x0B; - register8_t reserved_0x0C; - register8_t reserved_0x0D; - register8_t reserved_0x0E; - register8_t reserved_0x0F; - EBI_CS_t CS0; /* Chip Select 0 */ - EBI_CS_t CS1; /* Chip Select 1 */ - EBI_CS_t CS2; /* Chip Select 2 */ - EBI_CS_t CS3; /* Chip Select 3 */ -} EBI_t; - -/* Chip Select adress space */ -typedef enum EBI_CS_ASPACE_enum -{ - EBI_CS_ASPACE_256B_gc = (0x00<<2), /* 256 bytes */ - EBI_CS_ASPACE_512B_gc = (0x01<<2), /* 512 bytes */ - EBI_CS_ASPACE_1KB_gc = (0x02<<2), /* 1K bytes */ - EBI_CS_ASPACE_2KB_gc = (0x03<<2), /* 2K bytes */ - EBI_CS_ASPACE_4KB_gc = (0x04<<2), /* 4K bytes */ - EBI_CS_ASPACE_8KB_gc = (0x05<<2), /* 8K bytes */ - EBI_CS_ASPACE_16KB_gc = (0x06<<2), /* 16K bytes */ - EBI_CS_ASPACE_32KB_gc = (0x07<<2), /* 32K bytes */ - EBI_CS_ASPACE_64KB_gc = (0x08<<2), /* 64K bytes */ - EBI_CS_ASPACE_128KB_gc = (0x09<<2), /* 128K bytes */ - EBI_CS_ASPACE_256KB_gc = (0x0A<<2), /* 256K bytes */ - EBI_CS_ASPACE_512KB_gc = (0x0B<<2), /* 512K bytes */ - EBI_CS_ASPACE_1MB_gc = (0x0C<<2), /* 1M bytes */ - EBI_CS_ASPACE_2MB_gc = (0x0D<<2), /* 2M bytes */ - EBI_CS_ASPACE_4MB_gc = (0x0E<<2), /* 4M bytes */ - EBI_CS_ASPACE_8MB_gc = (0x0F<<2), /* 8M bytes */ - EBI_CS_ASPACE_16M_gc = (0x10<<2), /* 16M bytes */ -} EBI_CS_ASPACE_t; - -/* SRAM Wait State Selection */ -typedef enum EBI_CS_SRWS_enum -{ - EBI_CS_SRWS_0CLK_gc = (0x00<<0), /* 0 cycles */ - EBI_CS_SRWS_1CLK_gc = (0x01<<0), /* 1 cycle */ - EBI_CS_SRWS_2CLK_gc = (0x02<<0), /* 2 cycles */ - EBI_CS_SRWS_3CLK_gc = (0x03<<0), /* 3 cycles */ - EBI_CS_SRWS_4CLK_gc = (0x04<<0), /* 4 cycles */ - EBI_CS_SRWS_5CLK_gc = (0x05<<0), /* 5 cycles */ - EBI_CS_SRWS_6CLK_gc = (0x06<<0), /* 6 cycles */ - EBI_CS_SRWS_7CLK_gc = (0x07<<0), /* 7 cycles */ -} EBI_CS_SRWS_t; - -/* Chip Select address mode */ -typedef enum EBI_CS_MODE_enum -{ - EBI_CS_MODE_DISABLED_gc = (0x00<<0), /* Chip Select Disabled */ - EBI_CS_MODE_SRAM_gc = (0x01<<0), /* Chip Select in SRAM mode */ - EBI_CS_MODE_LPC_gc = (0x02<<0), /* Chip Select in SRAM LPC mode */ - EBI_CS_MODE_SDRAM_gc = (0x03<<0), /* Chip Select in SDRAM mode */ -} EBI_CS_MODE_t; - -/* Chip Select SDRAM mode */ -typedef enum EBI_CS_SDMODE_enum -{ - EBI_CS_SDMODE_NORMAL_gc = (0x00<<0), /* Normal mode */ - EBI_CS_SDMODE_LOAD_gc = (0x01<<0), /* Load Mode Register command mode */ -} EBI_CS_SDMODE_t; - -/* */ -typedef enum EBI_SDDATAW_enum -{ - EBI_SDDATAW_4BIT_gc = (0x00<<6), /* 4-bit data bus */ - EBI_SDDATAW_8BIT_gc = (0x01<<6), /* 8-bit data bus */ -} EBI_SDDATAW_t; - -/* */ -typedef enum EBI_LPCMODE_enum -{ - EBI_LPCMODE_ALE1_gc = (0x00<<4), /* Data muxed with addr byte 0 */ - EBI_LPCMODE_ALE12_gc = (0x02<<4), /* Data muxed with addr byte 0 and 1 */ -} EBI_LPCMODE_t; - -/* */ -typedef enum EBI_SRMODE_enum -{ - EBI_SRMODE_ALE1_gc = (0x00<<2), /* Addr byte 0 muxed with 1 */ - EBI_SRMODE_ALE2_gc = (0x01<<2), /* Addr byte 0 muxed with 2 */ - EBI_SRMODE_ALE12_gc = (0x02<<2), /* Addr byte 0 muxed with 1 and 2 */ - EBI_SRMODE_NOALE_gc = (0x03<<2), /* No addr muxing */ -} EBI_SRMODE_t; - -/* */ -typedef enum EBI_IFMODE_enum -{ - EBI_IFMODE_DISABLED_gc = (0x00<<0), /* EBI Disabled */ - EBI_IFMODE_3PORT_gc = (0x01<<0), /* 3-port mode */ - EBI_IFMODE_4PORT_gc = (0x02<<0), /* 4-port mode */ - EBI_IFMODE_2PORT_gc = (0x03<<0), /* 2-port mode */ -} EBI_IFMODE_t; - -/* */ -typedef enum EBI_SDCOL_enum -{ - EBI_SDCOL_8BIT_gc = (0x00<<0), /* 8 column bits */ - EBI_SDCOL_9BIT_gc = (0x01<<0), /* 9 column bits */ - EBI_SDCOL_10BIT_gc = (0x02<<0), /* 10 column bits */ - EBI_SDCOL_11BIT_gc = (0x03<<0), /* 11 column bits */ -} EBI_SDCOL_t; - -/* SDRAM Load Mode to Active delay */ -typedef enum EBI_MRDLY_enum -{ - EBI_MRDLY_0CLK_gc = (0x00<<6), /* 0 cycles */ - EBI_MRDLY_1CLK_gc = (0x01<<6), /* 1 cycle */ - EBI_MRDLY_2CLK_gc = (0x02<<6), /* 2 cycles */ - EBI_MRDLY_3CLK_gc = (0x03<<6), /* 3 cycles */ -} EBI_MRDLY_t; - -/* SDRAM Row Cycle Delay */ -typedef enum EBI_ROWCYCDLY_enum -{ - EBI_ROWCYCDLY_0CLK_gc = (0x00<<3), /* 0 cycles */ - EBI_ROWCYCDLY_1CLK_gc = (0x01<<3), /* 1 cycle */ - EBI_ROWCYCDLY_2CLK_gc = (0x02<<3), /* 2 cycles */ - EBI_ROWCYCDLY_3CLK_gc = (0x03<<3), /* 3 cycles */ - EBI_ROWCYCDLY_4CLK_gc = (0x04<<3), /* 4 cycles */ - EBI_ROWCYCDLY_5CLK_gc = (0x05<<3), /* 5 cycles */ - EBI_ROWCYCDLY_6CLK_gc = (0x06<<3), /* 6 cycles */ - EBI_ROWCYCDLY_7CLK_gc = (0x07<<3), /* 7 cycles */ -} EBI_ROWCYCDLY_t; - -/* SDRAM Row to Precharge Delay */ -typedef enum EBI_RPDLY_enum -{ - EBI_RPDLY_0CLK_gc = (0x00<<0), /* 0 cycles */ - EBI_RPDLY_1CLK_gc = (0x01<<0), /* 1 cycle */ - EBI_RPDLY_2CLK_gc = (0x02<<0), /* 2 cycles */ - EBI_RPDLY_3CLK_gc = (0x03<<0), /* 3 cycles */ - EBI_RPDLY_4CLK_gc = (0x04<<0), /* 4 cycles */ - EBI_RPDLY_5CLK_gc = (0x05<<0), /* 5 cycles */ - EBI_RPDLY_6CLK_gc = (0x06<<0), /* 6 cycles */ - EBI_RPDLY_7CLK_gc = (0x07<<0), /* 7 cycles */ -} EBI_RPDLY_t; - -/* SDRAM Write Recovery Delay */ -typedef enum EBI_WRDLY_enum -{ - EBI_WRDLY_0CLK_gc = (0x00<<6), /* 0 cycles */ - EBI_WRDLY_1CLK_gc = (0x01<<6), /* 1 cycle */ - EBI_WRDLY_2CLK_gc = (0x02<<6), /* 2 cycles */ - EBI_WRDLY_3CLK_gc = (0x03<<6), /* 3 cycles */ -} EBI_WRDLY_t; - -/* SDRAM Exit Self Refresh to Active Delay */ -typedef enum EBI_ESRDLY_enum -{ - EBI_ESRDLY_0CLK_gc = (0x00<<3), /* 0 cycles */ - EBI_ESRDLY_1CLK_gc = (0x01<<3), /* 1 cycle */ - EBI_ESRDLY_2CLK_gc = (0x02<<3), /* 2 cycles */ - EBI_ESRDLY_3CLK_gc = (0x03<<3), /* 3 cycles */ - EBI_ESRDLY_4CLK_gc = (0x04<<3), /* 4 cycles */ - EBI_ESRDLY_5CLK_gc = (0x05<<3), /* 5 cycles */ - EBI_ESRDLY_6CLK_gc = (0x06<<3), /* 6 cycles */ - EBI_ESRDLY_7CLK_gc = (0x07<<3), /* 7 cycles */ -} EBI_ESRDLY_t; - -/* SDRAM Row to Column Delay */ -typedef enum EBI_ROWCOLDLY_enum -{ - EBI_ROWCOLDLY_0CLK_gc = (0x00<<0), /* 0 cycles */ - EBI_ROWCOLDLY_1CLK_gc = (0x01<<0), /* 1 cycle */ - EBI_ROWCOLDLY_2CLK_gc = (0x02<<0), /* 2 cycles */ - EBI_ROWCOLDLY_3CLK_gc = (0x03<<0), /* 3 cycles */ - EBI_ROWCOLDLY_4CLK_gc = (0x04<<0), /* 4 cycles */ - EBI_ROWCOLDLY_5CLK_gc = (0x05<<0), /* 5 cycles */ - EBI_ROWCOLDLY_6CLK_gc = (0x06<<0), /* 6 cycles */ - EBI_ROWCOLDLY_7CLK_gc = (0x07<<0), /* 7 cycles */ -} EBI_ROWCOLDLY_t; - - -/* --------------------------------------------------------------------------- -TWI - Two-Wire Interface --------------------------------------------------------------------------- -*/ - -/* */ -typedef struct TWI_MASTER_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t CTRLC; /* Control Register C */ - register8_t STATUS; /* Status Register */ - register8_t BAUD; /* Baurd Rate Control Register */ - register8_t ADDR; /* Address Register */ - register8_t DATA; /* Data Register */ -} TWI_MASTER_t; - - -/* */ -typedef struct TWI_SLAVE_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t STATUS; /* Status Register */ - register8_t ADDR; /* Address Register */ - register8_t DATA; /* Data Register */ - register8_t ADDRMASK; /* Address Mask Register */ -} TWI_SLAVE_t; - - -/* Two-Wire Interface */ -typedef struct TWI_struct -{ - register8_t CTRL; /* TWI Common Control Register */ - TWI_MASTER_t MASTER; /* TWI master module */ - TWI_SLAVE_t SLAVE; /* TWI slave module */ -} TWI_t; - -/* Master Interrupt Level */ -typedef enum TWI_MASTER_INTLVL_enum -{ - TWI_MASTER_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ - TWI_MASTER_INTLVL_LO_gc = (0x01<<6), /* Low Level */ - TWI_MASTER_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ - TWI_MASTER_INTLVL_HI_gc = (0x03<<6), /* High Level */ -} TWI_MASTER_INTLVL_t; - -/* Inactive Timeout */ -typedef enum TWI_MASTER_TIMEOUT_enum -{ - TWI_MASTER_TIMEOUT_DISABLED_gc = (0x00<<2), /* Bus Timeout Disabled */ - TWI_MASTER_TIMEOUT_50US_gc = (0x01<<2), /* 50 Microseconds */ - TWI_MASTER_TIMEOUT_100US_gc = (0x02<<2), /* 100 Microseconds */ - TWI_MASTER_TIMEOUT_200US_gc = (0x03<<2), /* 200 Microseconds */ -} TWI_MASTER_TIMEOUT_t; - -/* Master Command */ -typedef enum TWI_MASTER_CMD_enum -{ - TWI_MASTER_CMD_NOACT_gc = (0x00<<0), /* No Action */ - TWI_MASTER_CMD_REPSTART_gc = (0x01<<0), /* Issue Repeated Start Condition */ - TWI_MASTER_CMD_RECVTRANS_gc = (0x02<<0), /* Receive or Transmit Data */ - TWI_MASTER_CMD_STOP_gc = (0x03<<0), /* Issue Stop Condition */ -} TWI_MASTER_CMD_t; - -/* Master Bus State */ -typedef enum TWI_MASTER_BUSSTATE_enum -{ - TWI_MASTER_BUSSTATE_UNKNOWN_gc = (0x00<<0), /* Unknown Bus State */ - TWI_MASTER_BUSSTATE_IDLE_gc = (0x01<<0), /* Bus is Idle */ - TWI_MASTER_BUSSTATE_OWNER_gc = (0x02<<0), /* This Module Controls The Bus */ - TWI_MASTER_BUSSTATE_BUSY_gc = (0x03<<0), /* The Bus is Busy */ -} TWI_MASTER_BUSSTATE_t; - -/* Slave Interrupt Level */ -typedef enum TWI_SLAVE_INTLVL_enum -{ - TWI_SLAVE_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ - TWI_SLAVE_INTLVL_LO_gc = (0x01<<6), /* Low Level */ - TWI_SLAVE_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ - TWI_SLAVE_INTLVL_HI_gc = (0x03<<6), /* High Level */ -} TWI_SLAVE_INTLVL_t; - -/* Slave Command */ -typedef enum TWI_SLAVE_CMD_enum -{ - TWI_SLAVE_CMD_NOACT_gc = (0x00<<0), /* No Action */ - TWI_SLAVE_CMD_COMPTRANS_gc = (0x02<<0), /* Used To Complete a Transaction */ - TWI_SLAVE_CMD_RESPONSE_gc = (0x03<<0), /* Used in Response to Address/Data Interrupt */ -} TWI_SLAVE_CMD_t; - -/* SDA hold time */ -typedef enum SDA_HOLD_TIME_enum -{ - SDA_HOLD_TIME_OFF_gc = (0x00<<1), /* SDA hold time off */ - SDA_HOLD_TIME_50NS_gc = (0x01<<1), /* Typical 50ns hold time */ - SDA_HOLD_TIME_300NS_gc = (0x02<<1), /* Typical 300ns hold time */ - SDA_HOLD_TIME_400NS_gc = (0x03<<1), /* Typical 400ns hold time */ -} SDA_HOLD_TIME_t; - - -/* --------------------------------------------------------------------------- -USB - USB --------------------------------------------------------------------------- -*/ - -/* USB Endpoint */ -typedef struct USB_EP_struct -{ - register8_t STATUS; /* Endpoint Status */ - register8_t CTRL; /* Endpoint Control */ - _WORDREGISTER(CNT); /* USB Endpoint Counter */ - _WORDREGISTER(DATAPTR); /* Data Pointer */ - _WORDREGISTER(AUXDATA); /* Auxiliary Data */ -} USB_EP_t; - - -/* Universal Serial Bus */ -typedef struct USB_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t STATUS; /* Status Register */ - register8_t ADDR; /* Address Register */ - register8_t FIFOWP; /* FIFO Write Pointer Register */ - register8_t FIFORP; /* FIFO Read Pointer Register */ - _WORDREGISTER(EPPTR); /* Endpoint Configuration Table Pointer */ - register8_t INTCTRLA; /* Interrupt Control Register A */ - register8_t INTCTRLB; /* Interrupt Control Register B */ - register8_t INTFLAGSACLR; /* Clear Interrupt Flag Register A */ - register8_t INTFLAGSASET; /* Set Interrupt Flag Register A */ - register8_t INTFLAGSBCLR; /* Clear Interrupt Flag Register B */ - register8_t INTFLAGSBSET; /* Set Interrupt Flag Register B */ - register8_t reserved_0x0E; - register8_t reserved_0x0F; - register8_t reserved_0x10; - register8_t reserved_0x11; - register8_t reserved_0x12; - register8_t reserved_0x13; - register8_t reserved_0x14; - register8_t reserved_0x15; - register8_t reserved_0x16; - register8_t reserved_0x17; - register8_t reserved_0x18; - register8_t reserved_0x19; - register8_t reserved_0x1A; - register8_t reserved_0x1B; - register8_t reserved_0x1C; - register8_t reserved_0x1D; - register8_t reserved_0x1E; - register8_t reserved_0x1F; - register8_t reserved_0x20; - register8_t reserved_0x21; - register8_t reserved_0x22; - register8_t reserved_0x23; - register8_t reserved_0x24; - register8_t reserved_0x25; - register8_t reserved_0x26; - register8_t reserved_0x27; - register8_t reserved_0x28; - register8_t reserved_0x29; - register8_t reserved_0x2A; - register8_t reserved_0x2B; - register8_t reserved_0x2C; - register8_t reserved_0x2D; - register8_t reserved_0x2E; - register8_t reserved_0x2F; - register8_t reserved_0x30; - register8_t reserved_0x31; - register8_t reserved_0x32; - register8_t reserved_0x33; - register8_t reserved_0x34; - register8_t reserved_0x35; - register8_t reserved_0x36; - register8_t reserved_0x37; - register8_t reserved_0x38; - register8_t reserved_0x39; - register8_t CAL0; /* Calibration Byte 0 */ - register8_t CAL1; /* Calibration Byte 1 */ -} USB_t; - - -/* USB Endpoint Table */ -typedef struct USB_EP_TABLE_struct -{ - USB_EP_t EP0OUT; /* Endpoint 0 */ - USB_EP_t EP0IN; /* Endpoint 0 */ - USB_EP_t EP1OUT; /* Endpoint 1 */ - USB_EP_t EP1IN; /* Endpoint 1 */ - USB_EP_t EP2OUT; /* Endpoint 2 */ - USB_EP_t EP2IN; /* Endpoint 2 */ - USB_EP_t EP3OUT; /* Endpoint 3 */ - USB_EP_t EP3IN; /* Endpoint 3 */ - USB_EP_t EP4OUT; /* Endpoint 4 */ - USB_EP_t EP4IN; /* Endpoint 4 */ - USB_EP_t EP5OUT; /* Endpoint 5 */ - USB_EP_t EP5IN; /* Endpoint 5 */ - USB_EP_t EP6OUT; /* Endpoint 6 */ - USB_EP_t EP6IN; /* Endpoint 6 */ - USB_EP_t EP7OUT; /* Endpoint 7 */ - USB_EP_t EP7IN; /* Endpoint 7 */ - USB_EP_t EP8OUT; /* Endpoint 8 */ - USB_EP_t EP8IN; /* Endpoint 8 */ - USB_EP_t EP9OUT; /* Endpoint 9 */ - USB_EP_t EP9IN; /* Endpoint 9 */ - USB_EP_t EP10OUT; /* Endpoint 10 */ - USB_EP_t EP10IN; /* Endpoint 10 */ - USB_EP_t EP11OUT; /* Endpoint 11 */ - USB_EP_t EP11IN; /* Endpoint 11 */ - USB_EP_t EP12OUT; /* Endpoint 12 */ - USB_EP_t EP12IN; /* Endpoint 12 */ - USB_EP_t EP13OUT; /* Endpoint 13 */ - USB_EP_t EP13IN; /* Endpoint 13 */ - USB_EP_t EP14OUT; /* Endpoint 14 */ - USB_EP_t EP14IN; /* Endpoint 14 */ - USB_EP_t EP15OUT; /* Endpoint 15 */ - USB_EP_t EP15IN; /* Endpoint 15 */ - register8_t reserved_0x100; - register8_t reserved_0x101; - register8_t reserved_0x102; - register8_t reserved_0x103; - register8_t reserved_0x104; - register8_t reserved_0x105; - register8_t reserved_0x106; - register8_t reserved_0x107; - register8_t reserved_0x108; - register8_t reserved_0x109; - register8_t reserved_0x10A; - register8_t reserved_0x10B; - register8_t reserved_0x10C; - register8_t reserved_0x10D; - register8_t reserved_0x10E; - register8_t reserved_0x10F; - register8_t FRAMENUML; /* Frame Number Low Byte */ - register8_t FRAMENUMH; /* Frame Number High Byte */ -} USB_EP_TABLE_t; - -/* Interrupt level */ -typedef enum USB_INTLVL_enum -{ - USB_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ - USB_INTLVL_LO_gc = (0x01<<0), /* Low level */ - USB_INTLVL_MED_gc = (0x02<<0), /* Medium level */ - USB_INTLVL_HI_gc = (0x03<<0), /* High level */ -} USB_INTLVL_t; - -/* USB Endpoint Type */ -typedef enum USB_EP_TYPE_enum -{ - USB_EP_TYPE_DISABLE_gc = (0x00<<6), /* Endpoint Disabled */ - USB_EP_TYPE_CONTROL_gc = (0x01<<6), /* Control */ - USB_EP_TYPE_BULK_gc = (0x02<<6), /* Bulk/Interrupt */ - USB_EP_TYPE_ISOCHRONOUS_gc = (0x03<<6), /* Isochronous */ -} USB_EP_TYPE_t; - -/* USB Endpoint Buffersize */ -typedef enum USB_EP_BUFSIZE_enum -{ - USB_EP_BUFSIZE_8_gc = (0x00<<0), /* 8 bytes buffer size */ - USB_EP_BUFSIZE_16_gc = (0x01<<0), /* 16 bytes buffer size */ - USB_EP_BUFSIZE_32_gc = (0x02<<0), /* 32 bytes buffer size */ - USB_EP_BUFSIZE_64_gc = (0x03<<0), /* 64 bytes buffer size */ - USB_EP_BUFSIZE_128_gc = (0x04<<0), /* 128 bytes buffer size */ - USB_EP_BUFSIZE_256_gc = (0x05<<0), /* 256 bytes buffer size */ - USB_EP_BUFSIZE_512_gc = (0x06<<0), /* 512 bytes buffer size */ - USB_EP_BUFSIZE_1023_gc = (0x07<<0), /* 1023 bytes buffer size */ -} USB_EP_BUFSIZE_t; - - -/* --------------------------------------------------------------------------- -PORT - I/O Port Configuration --------------------------------------------------------------------------- -*/ - -/* I/O Ports */ -typedef struct PORT_struct -{ - register8_t DIR; /* I/O Port Data Direction */ - register8_t DIRSET; /* I/O Port Data Direction Set */ - register8_t DIRCLR; /* I/O Port Data Direction Clear */ - register8_t DIRTGL; /* I/O Port Data Direction Toggle */ - register8_t OUT; /* I/O Port Output */ - register8_t OUTSET; /* I/O Port Output Set */ - register8_t OUTCLR; /* I/O Port Output Clear */ - register8_t OUTTGL; /* I/O Port Output Toggle */ - register8_t IN; /* I/O port Input */ - register8_t INTCTRL; /* Interrupt Control Register */ - register8_t INT0MASK; /* Port Interrupt 0 Mask */ - register8_t INT1MASK; /* Port Interrupt 1 Mask */ - register8_t INTFLAGS; /* Interrupt Flag Register */ - register8_t reserved_0x0D; - register8_t REMAP; /* I/O Port Pin Remap Register */ - register8_t reserved_0x0F; - register8_t PIN0CTRL; /* Pin 0 Control Register */ - register8_t PIN1CTRL; /* Pin 1 Control Register */ - register8_t PIN2CTRL; /* Pin 2 Control Register */ - register8_t PIN3CTRL; /* Pin 3 Control Register */ - register8_t PIN4CTRL; /* Pin 4 Control Register */ - register8_t PIN5CTRL; /* Pin 5 Control Register */ - register8_t PIN6CTRL; /* Pin 6 Control Register */ - register8_t PIN7CTRL; /* Pin 7 Control Register */ -} PORT_t; - -/* Port Interrupt 0 Level */ -typedef enum PORT_INT0LVL_enum -{ - PORT_INT0LVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - PORT_INT0LVL_LO_gc = (0x01<<0), /* Low Level */ - PORT_INT0LVL_MED_gc = (0x02<<0), /* Medium Level */ - PORT_INT0LVL_HI_gc = (0x03<<0), /* High Level */ -} PORT_INT0LVL_t; - -/* Port Interrupt 1 Level */ -typedef enum PORT_INT1LVL_enum -{ - PORT_INT1LVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ - PORT_INT1LVL_LO_gc = (0x01<<2), /* Low Level */ - PORT_INT1LVL_MED_gc = (0x02<<2), /* Medium Level */ - PORT_INT1LVL_HI_gc = (0x03<<2), /* High Level */ -} PORT_INT1LVL_t; - -/* Output/Pull Configuration */ -typedef enum PORT_OPC_enum -{ - PORT_OPC_TOTEM_gc = (0x00<<3), /* Totempole */ - PORT_OPC_BUSKEEPER_gc = (0x01<<3), /* Totempole w/ Bus keeper on Input and Output */ - PORT_OPC_PULLDOWN_gc = (0x02<<3), /* Totempole w/ Pull-down on Input */ - PORT_OPC_PULLUP_gc = (0x03<<3), /* Totempole w/ Pull-up on Input */ - PORT_OPC_WIREDOR_gc = (0x04<<3), /* Wired OR */ - PORT_OPC_WIREDAND_gc = (0x05<<3), /* Wired AND */ - PORT_OPC_WIREDORPULL_gc = (0x06<<3), /* Wired OR w/ Pull-down */ - PORT_OPC_WIREDANDPULL_gc = (0x07<<3), /* Wired AND w/ Pull-up */ -} PORT_OPC_t; - -/* Input/Sense Configuration */ -typedef enum PORT_ISC_enum -{ - PORT_ISC_BOTHEDGES_gc = (0x00<<0), /* Sense Both Edges */ - PORT_ISC_RISING_gc = (0x01<<0), /* Sense Rising Edge */ - PORT_ISC_FALLING_gc = (0x02<<0), /* Sense Falling Edge */ - PORT_ISC_LEVEL_gc = (0x03<<0), /* Sense Level (Transparent For Events) */ - PORT_ISC_INPUT_DISABLE_gc = (0x07<<0), /* Disable Digital Input Buffer */ -} PORT_ISC_t; - - -/* --------------------------------------------------------------------------- -TC - 16-bit Timer/Counter With PWM --------------------------------------------------------------------------- -*/ - -/* 16-bit Timer/Counter 0 */ -typedef struct TC0_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t CTRLC; /* Control register C */ - register8_t CTRLD; /* Control Register D */ - register8_t CTRLE; /* Control Register E */ - register8_t reserved_0x05; - register8_t INTCTRLA; /* Interrupt Control Register A */ - register8_t INTCTRLB; /* Interrupt Control Register B */ - register8_t CTRLFCLR; /* Control Register F Clear */ - register8_t CTRLFSET; /* Control Register F Set */ - register8_t CTRLGCLR; /* Control Register G Clear */ - register8_t CTRLGSET; /* Control Register G Set */ - register8_t INTFLAGS; /* Interrupt Flag Register */ - register8_t reserved_0x0D; - register8_t reserved_0x0E; - register8_t TEMP; /* Temporary Register For 16-bit Access */ - register8_t reserved_0x10; - register8_t reserved_0x11; - register8_t reserved_0x12; - register8_t reserved_0x13; - register8_t reserved_0x14; - register8_t reserved_0x15; - register8_t reserved_0x16; - register8_t reserved_0x17; - register8_t reserved_0x18; - register8_t reserved_0x19; - register8_t reserved_0x1A; - register8_t reserved_0x1B; - register8_t reserved_0x1C; - register8_t reserved_0x1D; - register8_t reserved_0x1E; - register8_t reserved_0x1F; - _WORDREGISTER(CNT); /* Count */ - register8_t reserved_0x22; - register8_t reserved_0x23; - register8_t reserved_0x24; - register8_t reserved_0x25; - _WORDREGISTER(PER); /* Period */ - _WORDREGISTER(CCA); /* Compare or Capture A */ - _WORDREGISTER(CCB); /* Compare or Capture B */ - _WORDREGISTER(CCC); /* Compare or Capture C */ - _WORDREGISTER(CCD); /* Compare or Capture D */ - register8_t reserved_0x30; - register8_t reserved_0x31; - register8_t reserved_0x32; - register8_t reserved_0x33; - register8_t reserved_0x34; - register8_t reserved_0x35; - _WORDREGISTER(PERBUF); /* Period Buffer */ - _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ - _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ - _WORDREGISTER(CCCBUF); /* Compare Or Capture C Buffer */ - _WORDREGISTER(CCDBUF); /* Compare Or Capture D Buffer */ -} TC0_t; - - -/* 16-bit Timer/Counter 1 */ -typedef struct TC1_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t CTRLC; /* Control register C */ - register8_t CTRLD; /* Control Register D */ - register8_t CTRLE; /* Control Register E */ - register8_t reserved_0x05; - register8_t INTCTRLA; /* Interrupt Control Register A */ - register8_t INTCTRLB; /* Interrupt Control Register B */ - register8_t CTRLFCLR; /* Control Register F Clear */ - register8_t CTRLFSET; /* Control Register F Set */ - register8_t CTRLGCLR; /* Control Register G Clear */ - register8_t CTRLGSET; /* Control Register G Set */ - register8_t INTFLAGS; /* Interrupt Flag Register */ - register8_t reserved_0x0D; - register8_t reserved_0x0E; - register8_t TEMP; /* Temporary Register For 16-bit Access */ - register8_t reserved_0x10; - register8_t reserved_0x11; - register8_t reserved_0x12; - register8_t reserved_0x13; - register8_t reserved_0x14; - register8_t reserved_0x15; - register8_t reserved_0x16; - register8_t reserved_0x17; - register8_t reserved_0x18; - register8_t reserved_0x19; - register8_t reserved_0x1A; - register8_t reserved_0x1B; - register8_t reserved_0x1C; - register8_t reserved_0x1D; - register8_t reserved_0x1E; - register8_t reserved_0x1F; - _WORDREGISTER(CNT); /* Count */ - register8_t reserved_0x22; - register8_t reserved_0x23; - register8_t reserved_0x24; - register8_t reserved_0x25; - _WORDREGISTER(PER); /* Period */ - _WORDREGISTER(CCA); /* Compare or Capture A */ - _WORDREGISTER(CCB); /* Compare or Capture B */ - register8_t reserved_0x2C; - register8_t reserved_0x2D; - register8_t reserved_0x2E; - register8_t reserved_0x2F; - register8_t reserved_0x30; - register8_t reserved_0x31; - register8_t reserved_0x32; - register8_t reserved_0x33; - register8_t reserved_0x34; - register8_t reserved_0x35; - _WORDREGISTER(PERBUF); /* Period Buffer */ - _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ - _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ -} TC1_t; - -/* Clock Selection */ -typedef enum TC_CLKSEL_enum -{ - TC_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */ - TC_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */ - TC_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */ - TC_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */ - TC_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */ - TC_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */ - TC_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */ - TC_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */ - TC_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */ - TC_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */ - TC_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */ - TC_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */ - TC_CLKSEL_EVCH4_gc = (0x0C<<0), /* Event Channel 4 */ - TC_CLKSEL_EVCH5_gc = (0x0D<<0), /* Event Channel 5 */ - TC_CLKSEL_EVCH6_gc = (0x0E<<0), /* Event Channel 6 */ - TC_CLKSEL_EVCH7_gc = (0x0F<<0), /* Event Channel 7 */ -} TC_CLKSEL_t; - -/* Waveform Generation Mode */ -typedef enum TC_WGMODE_enum -{ - TC_WGMODE_NORMAL_gc = (0x00<<0), /* Normal Mode */ - TC_WGMODE_FRQ_gc = (0x01<<0), /* Frequency Generation Mode */ - TC_WGMODE_SINGLESLOPE_gc = (0x03<<0), /* Single Slope */ - TC_WGMODE_SS_gc = (0x03<<0), /* Single Slope */ - TC_WGMODE_DSTOP_gc = (0x05<<0), /* Dual Slope, Update on TOP */ - TC_WGMODE_DS_T_gc = (0x05<<0), /* Dual Slope, Update on TOP */ - TC_WGMODE_DSBOTH_gc = (0x06<<0), /* Dual Slope, Update on both TOP and BOTTOM */ - TC_WGMODE_DS_TB_gc = (0x06<<0), /* Dual Slope, Update on both TOP and BOTTOM */ - TC_WGMODE_DSBOTTOM_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */ - TC_WGMODE_DS_B_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */ -} TC_WGMODE_t; - -/* Byte Mode */ -typedef enum TC_BYTEM_enum -{ - TC_BYTEM_NORMAL_gc = (0x00<<0), /* 16-bit mode */ - TC_BYTEM_BYTEMODE_gc = (0x01<<0), /* Timer/Counter operating in byte mode only */ - TC_BYTEM_SPLITMODE_gc = (0x02<<0), /* Timer/Counter split into two 8-bit Counters (TC2) */ -} TC_BYTEM_t; - -/* Event Action */ -typedef enum TC_EVACT_enum -{ - TC_EVACT_OFF_gc = (0x00<<5), /* No Event Action */ - TC_EVACT_CAPT_gc = (0x01<<5), /* Input Capture */ - TC_EVACT_UPDOWN_gc = (0x02<<5), /* Externally Controlled Up/Down Count */ - TC_EVACT_QDEC_gc = (0x03<<5), /* Quadrature Decode */ - TC_EVACT_RESTART_gc = (0x04<<5), /* Restart */ - TC_EVACT_FRQ_gc = (0x05<<5), /* Frequency Capture */ - TC_EVACT_PW_gc = (0x06<<5), /* Pulse-width Capture */ -} TC_EVACT_t; - -/* Event Selection */ -typedef enum TC_EVSEL_enum -{ - TC_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ - TC_EVSEL_CH0_gc = (0x08<<0), /* Event Channel 0 */ - TC_EVSEL_CH1_gc = (0x09<<0), /* Event Channel 1 */ - TC_EVSEL_CH2_gc = (0x0A<<0), /* Event Channel 2 */ - TC_EVSEL_CH3_gc = (0x0B<<0), /* Event Channel 3 */ - TC_EVSEL_CH4_gc = (0x0C<<0), /* Event Channel 4 */ - TC_EVSEL_CH5_gc = (0x0D<<0), /* Event Channel 5 */ - TC_EVSEL_CH6_gc = (0x0E<<0), /* Event Channel 6 */ - TC_EVSEL_CH7_gc = (0x0F<<0), /* Event Channel 7 */ -} TC_EVSEL_t; - -/* Error Interrupt Level */ -typedef enum TC_ERRINTLVL_enum -{ - TC_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ - TC_ERRINTLVL_LO_gc = (0x01<<2), /* Low Level */ - TC_ERRINTLVL_MED_gc = (0x02<<2), /* Medium Level */ - TC_ERRINTLVL_HI_gc = (0x03<<2), /* High Level */ -} TC_ERRINTLVL_t; - -/* Overflow Interrupt Level */ -typedef enum TC_OVFINTLVL_enum -{ - TC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - TC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ - TC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ - TC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ -} TC_OVFINTLVL_t; - -/* Compare or Capture D Interrupt Level */ -typedef enum TC_CCDINTLVL_enum -{ - TC_CCDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ - TC_CCDINTLVL_LO_gc = (0x01<<6), /* Low Level */ - TC_CCDINTLVL_MED_gc = (0x02<<6), /* Medium Level */ - TC_CCDINTLVL_HI_gc = (0x03<<6), /* High Level */ -} TC_CCDINTLVL_t; - -/* Compare or Capture C Interrupt Level */ -typedef enum TC_CCCINTLVL_enum -{ - TC_CCCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ - TC_CCCINTLVL_LO_gc = (0x01<<4), /* Low Level */ - TC_CCCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ - TC_CCCINTLVL_HI_gc = (0x03<<4), /* High Level */ -} TC_CCCINTLVL_t; - -/* Compare or Capture B Interrupt Level */ -typedef enum TC_CCBINTLVL_enum -{ - TC_CCBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ - TC_CCBINTLVL_LO_gc = (0x01<<2), /* Low Level */ - TC_CCBINTLVL_MED_gc = (0x02<<2), /* Medium Level */ - TC_CCBINTLVL_HI_gc = (0x03<<2), /* High Level */ -} TC_CCBINTLVL_t; - -/* Compare or Capture A Interrupt Level */ -typedef enum TC_CCAINTLVL_enum -{ - TC_CCAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - TC_CCAINTLVL_LO_gc = (0x01<<0), /* Low Level */ - TC_CCAINTLVL_MED_gc = (0x02<<0), /* Medium Level */ - TC_CCAINTLVL_HI_gc = (0x03<<0), /* High Level */ -} TC_CCAINTLVL_t; - -/* Timer/Counter Command */ -typedef enum TC_CMD_enum -{ - TC_CMD_NONE_gc = (0x00<<2), /* No Command */ - TC_CMD_UPDATE_gc = (0x01<<2), /* Force Update */ - TC_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ - TC_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ -} TC_CMD_t; - - -/* --------------------------------------------------------------------------- -TC2 - 16-bit Timer/Counter type 2 --------------------------------------------------------------------------- -*/ - -/* 16-bit Timer/Counter type 2 */ -typedef struct TC2_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t CTRLC; /* Control register C */ - register8_t reserved_0x03; - register8_t CTRLE; /* Control Register E */ - register8_t reserved_0x05; - register8_t INTCTRLA; /* Interrupt Control Register A */ - register8_t INTCTRLB; /* Interrupt Control Register B */ - register8_t reserved_0x08; - register8_t CTRLF; /* Control Register F */ - register8_t reserved_0x0A; - register8_t reserved_0x0B; - register8_t INTFLAGS; /* Interrupt Flag Register */ - register8_t reserved_0x0D; - register8_t reserved_0x0E; - register8_t reserved_0x0F; - register8_t reserved_0x10; - register8_t reserved_0x11; - register8_t reserved_0x12; - register8_t reserved_0x13; - register8_t reserved_0x14; - register8_t reserved_0x15; - register8_t reserved_0x16; - register8_t reserved_0x17; - register8_t reserved_0x18; - register8_t reserved_0x19; - register8_t reserved_0x1A; - register8_t reserved_0x1B; - register8_t reserved_0x1C; - register8_t reserved_0x1D; - register8_t reserved_0x1E; - register8_t reserved_0x1F; - register8_t LCNT; /* Low Byte Count */ - register8_t HCNT; /* High Byte Count */ - register8_t reserved_0x22; - register8_t reserved_0x23; - register8_t reserved_0x24; - register8_t reserved_0x25; - register8_t LPER; /* Low Byte Period */ - register8_t HPER; /* High Byte Period */ - register8_t LCMPA; /* Low Byte Compare A */ - register8_t HCMPA; /* High Byte Compare A */ - register8_t LCMPB; /* Low Byte Compare B */ - register8_t HCMPB; /* High Byte Compare B */ - register8_t LCMPC; /* Low Byte Compare C */ - register8_t HCMPC; /* High Byte Compare C */ - register8_t LCMPD; /* Low Byte Compare D */ - register8_t HCMPD; /* High Byte Compare D */ -} TC2_t; - -/* Clock Selection */ -typedef enum TC2_CLKSEL_enum -{ - TC2_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */ - TC2_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */ - TC2_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */ - TC2_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */ - TC2_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */ - TC2_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */ - TC2_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */ - TC2_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */ - TC2_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */ - TC2_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */ - TC2_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */ - TC2_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */ - TC2_CLKSEL_EVCH4_gc = (0x0C<<0), /* Event Channel 4 */ - TC2_CLKSEL_EVCH5_gc = (0x0D<<0), /* Event Channel 5 */ - TC2_CLKSEL_EVCH6_gc = (0x0E<<0), /* Event Channel 6 */ - TC2_CLKSEL_EVCH7_gc = (0x0F<<0), /* Event Channel 7 */ -} TC2_CLKSEL_t; - -/* Byte Mode */ -typedef enum TC2_BYTEM_enum -{ - TC2_BYTEM_NORMAL_gc = (0x00<<0), /* 16-bit mode */ - TC2_BYTEM_BYTEMODE_gc = (0x01<<0), /* Timer/Counter operating in byte mode only (TC2) */ - TC2_BYTEM_SPLITMODE_gc = (0x02<<0), /* Timer/Counter split into two 8-bit Counters */ -} TC2_BYTEM_t; - -/* High Byte Underflow Interrupt Level */ -typedef enum TC2_HUNFINTLVL_enum -{ - TC2_HUNFINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ - TC2_HUNFINTLVL_LO_gc = (0x01<<2), /* Low Level */ - TC2_HUNFINTLVL_MED_gc = (0x02<<2), /* Medium Level */ - TC2_HUNFINTLVL_HI_gc = (0x03<<2), /* High Level */ -} TC2_HUNFINTLVL_t; - -/* Low Byte Underflow Interrupt Level */ -typedef enum TC2_LUNFINTLVL_enum -{ - TC2_LUNFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - TC2_LUNFINTLVL_LO_gc = (0x01<<0), /* Low Level */ - TC2_LUNFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ - TC2_LUNFINTLVL_HI_gc = (0x03<<0), /* High Level */ -} TC2_LUNFINTLVL_t; - -/* Low Byte Compare D Interrupt Level */ -typedef enum TC2_LCMPDINTLVL_enum -{ - TC2_LCMPDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ - TC2_LCMPDINTLVL_LO_gc = (0x01<<6), /* Low Level */ - TC2_LCMPDINTLVL_MED_gc = (0x02<<6), /* Medium Level */ - TC2_LCMPDINTLVL_HI_gc = (0x03<<6), /* High Level */ -} TC2_LCMPDINTLVL_t; - -/* Low Byte Compare C Interrupt Level */ -typedef enum TC2_LCMPCINTLVL_enum -{ - TC2_LCMPCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ - TC2_LCMPCINTLVL_LO_gc = (0x01<<4), /* Low Level */ - TC2_LCMPCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ - TC2_LCMPCINTLVL_HI_gc = (0x03<<4), /* High Level */ -} TC2_LCMPCINTLVL_t; - -/* Low Byte Compare B Interrupt Level */ -typedef enum TC2_LCMPBINTLVL_enum -{ - TC2_LCMPBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ - TC2_LCMPBINTLVL_LO_gc = (0x01<<2), /* Low Level */ - TC2_LCMPBINTLVL_MED_gc = (0x02<<2), /* Medium Level */ - TC2_LCMPBINTLVL_HI_gc = (0x03<<2), /* High Level */ -} TC2_LCMPBINTLVL_t; - -/* Low Byte Compare A Interrupt Level */ -typedef enum TC2_LCMPAINTLVL_enum -{ - TC2_LCMPAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - TC2_LCMPAINTLVL_LO_gc = (0x01<<0), /* Low Level */ - TC2_LCMPAINTLVL_MED_gc = (0x02<<0), /* Medium Level */ - TC2_LCMPAINTLVL_HI_gc = (0x03<<0), /* High Level */ -} TC2_LCMPAINTLVL_t; - -/* Timer/Counter Command */ -typedef enum TC2_CMD_enum -{ - TC2_CMD_NONE_gc = (0x00<<2), /* No Command */ - TC2_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ - TC2_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ -} TC2_CMD_t; - -/* Timer/Counter Command */ -typedef enum TC2_CMDEN_enum -{ - TC2_CMDEN_LOW_gc = (0x01<<0), /* Low Byte Timer/Counter */ - TC2_CMDEN_HIGH_gc = (0x02<<0), /* High Byte Timer/Counter */ - TC2_CMDEN_BOTH_gc = (0x03<<0), /* Both Low Byte and High Byte Timer/Counters */ -} TC2_CMDEN_t; - - -/* --------------------------------------------------------------------------- -AWEX - Timer/Counter Advanced Waveform Extension --------------------------------------------------------------------------- -*/ - -/* Advanced Waveform Extension */ -typedef struct AWEX_struct -{ - register8_t CTRL; /* Control Register */ - register8_t reserved_0x01; - register8_t FDEMASK; /* Fault Detection Event Mask */ - register8_t FDCTRL; /* Fault Detection Control Register */ - register8_t STATUS; /* Status Register */ - register8_t STATUSSET; /* Status Set Register */ - register8_t DTBOTH; /* Dead Time Both Sides */ - register8_t DTBOTHBUF; /* Dead Time Both Sides Buffer */ - register8_t DTLS; /* Dead Time Low Side */ - register8_t DTHS; /* Dead Time High Side */ - register8_t DTLSBUF; /* Dead Time Low Side Buffer */ - register8_t DTHSBUF; /* Dead Time High Side Buffer */ - register8_t OUTOVEN; /* Output Override Enable */ -} AWEX_t; - -/* Fault Detect Action */ -typedef enum AWEX_FDACT_enum -{ - AWEX_FDACT_NONE_gc = (0x00<<0), /* No Fault Protection */ - AWEX_FDACT_CLEAROE_gc = (0x01<<0), /* Clear Output Enable Bits */ - AWEX_FDACT_CLEARDIR_gc = (0x03<<0), /* Clear I/O Port Direction Bits */ -} AWEX_FDACT_t; - - -/* --------------------------------------------------------------------------- -HIRES - Timer/Counter High-Resolution Extension --------------------------------------------------------------------------- -*/ - -/* High-Resolution Extension */ -typedef struct HIRES_struct -{ - register8_t CTRLA; /* Control Register */ -} HIRES_t; - -/* High Resolution Enable */ -typedef enum HIRES_HREN_enum -{ - HIRES_HREN_NONE_gc = (0x00<<0), /* No Fault Protection */ - HIRES_HREN_TC0_gc = (0x01<<0), /* Enable High Resolution on Timer/Counter 0 */ - HIRES_HREN_TC1_gc = (0x02<<0), /* Enable High Resolution on Timer/Counter 1 */ - HIRES_HREN_BOTH_gc = (0x03<<0), /* Enable High Resolution both Timer/Counters */ -} HIRES_HREN_t; - - -/* --------------------------------------------------------------------------- -USART - Universal Asynchronous Receiver-Transmitter --------------------------------------------------------------------------- -*/ - -/* Universal Synchronous/Asynchronous Receiver/Transmitter */ -typedef struct USART_struct -{ - register8_t DATA; /* Data Register */ - register8_t STATUS; /* Status Register */ - register8_t reserved_0x02; - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t CTRLC; /* Control Register C */ - register8_t BAUDCTRLA; /* Baud Rate Control Register A */ - register8_t BAUDCTRLB; /* Baud Rate Control Register B */ -} USART_t; - -/* Receive Complete Interrupt level */ -typedef enum USART_RXCINTLVL_enum -{ - USART_RXCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ - USART_RXCINTLVL_LO_gc = (0x01<<4), /* Low Level */ - USART_RXCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ - USART_RXCINTLVL_HI_gc = (0x03<<4), /* High Level */ -} USART_RXCINTLVL_t; - -/* Transmit Complete Interrupt level */ -typedef enum USART_TXCINTLVL_enum -{ - USART_TXCINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ - USART_TXCINTLVL_LO_gc = (0x01<<2), /* Low Level */ - USART_TXCINTLVL_MED_gc = (0x02<<2), /* Medium Level */ - USART_TXCINTLVL_HI_gc = (0x03<<2), /* High Level */ -} USART_TXCINTLVL_t; - -/* Data Register Empty Interrupt level */ -typedef enum USART_DREINTLVL_enum -{ - USART_DREINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - USART_DREINTLVL_LO_gc = (0x01<<0), /* Low Level */ - USART_DREINTLVL_MED_gc = (0x02<<0), /* Medium Level */ - USART_DREINTLVL_HI_gc = (0x03<<0), /* High Level */ -} USART_DREINTLVL_t; - -/* Character Size */ -typedef enum USART_CHSIZE_enum -{ - USART_CHSIZE_5BIT_gc = (0x00<<0), /* Character size: 5 bit */ - USART_CHSIZE_6BIT_gc = (0x01<<0), /* Character size: 6 bit */ - USART_CHSIZE_7BIT_gc = (0x02<<0), /* Character size: 7 bit */ - USART_CHSIZE_8BIT_gc = (0x03<<0), /* Character size: 8 bit */ - USART_CHSIZE_9BIT_gc = (0x07<<0), /* Character size: 9 bit */ -} USART_CHSIZE_t; - -/* Communication Mode */ -typedef enum USART_CMODE_enum -{ - USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6), /* Asynchronous Mode */ - USART_CMODE_SYNCHRONOUS_gc = (0x01<<6), /* Synchronous Mode */ - USART_CMODE_IRDA_gc = (0x02<<6), /* IrDA Mode */ - USART_CMODE_MSPI_gc = (0x03<<6), /* Master SPI Mode */ -} USART_CMODE_t; - -/* Parity Mode */ -typedef enum USART_PMODE_enum -{ - USART_PMODE_DISABLED_gc = (0x00<<4), /* No Parity */ - USART_PMODE_EVEN_gc = (0x02<<4), /* Even Parity */ - USART_PMODE_ODD_gc = (0x03<<4), /* Odd Parity */ -} USART_PMODE_t; - - -/* --------------------------------------------------------------------------- -SPI - Serial Peripheral Interface --------------------------------------------------------------------------- -*/ - -/* Serial Peripheral Interface */ -typedef struct SPI_struct -{ - register8_t CTRL; /* Control Register */ - register8_t INTCTRL; /* Interrupt Control Register */ - register8_t STATUS; /* Status Register */ - register8_t DATA; /* Data Register */ -} SPI_t; - -/* SPI Mode */ -typedef enum SPI_MODE_enum -{ - SPI_MODE_0_gc = (0x00<<2), /* SPI Mode 0 */ - SPI_MODE_1_gc = (0x01<<2), /* SPI Mode 1 */ - SPI_MODE_2_gc = (0x02<<2), /* SPI Mode 2 */ - SPI_MODE_3_gc = (0x03<<2), /* SPI Mode 3 */ -} SPI_MODE_t; - -/* Prescaler setting */ -typedef enum SPI_PRESCALER_enum -{ - SPI_PRESCALER_DIV4_gc = (0x00<<0), /* System Clock / 4 */ - SPI_PRESCALER_DIV16_gc = (0x01<<0), /* System Clock / 16 */ - SPI_PRESCALER_DIV64_gc = (0x02<<0), /* System Clock / 64 */ - SPI_PRESCALER_DIV128_gc = (0x03<<0), /* System Clock / 128 */ -} SPI_PRESCALER_t; - -/* Interrupt level */ -typedef enum SPI_INTLVL_enum -{ - SPI_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - SPI_INTLVL_LO_gc = (0x01<<0), /* Low Level */ - SPI_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ - SPI_INTLVL_HI_gc = (0x03<<0), /* High Level */ -} SPI_INTLVL_t; - - -/* --------------------------------------------------------------------------- -IRCOM - IR Communication Module --------------------------------------------------------------------------- -*/ - -/* IR Communication Module */ -typedef struct IRCOM_struct -{ - register8_t CTRL; /* Control Register */ - register8_t TXPLCTRL; /* IrDA Transmitter Pulse Length Control Register */ - register8_t RXPLCTRL; /* IrDA Receiver Pulse Length Control Register */ -} IRCOM_t; - -/* Event channel selection */ -typedef enum IRDA_EVSEL_enum -{ - IRDA_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ - IRDA_EVSEL_0_gc = (0x08<<0), /* Event Channel 0 */ - IRDA_EVSEL_1_gc = (0x09<<0), /* Event Channel 1 */ - IRDA_EVSEL_2_gc = (0x0A<<0), /* Event Channel 2 */ - IRDA_EVSEL_3_gc = (0x0B<<0), /* Event Channel 3 */ - IRDA_EVSEL_4_gc = (0x0C<<0), /* Event Channel 4 */ - IRDA_EVSEL_5_gc = (0x0D<<0), /* Event Channel 5 */ - IRDA_EVSEL_6_gc = (0x0E<<0), /* Event Channel 6 */ - IRDA_EVSEL_7_gc = (0x0F<<0), /* Event Channel 7 */ -} IRDA_EVSEL_t; - - -/* --------------------------------------------------------------------------- -FUSE - Fuses and Lockbits --------------------------------------------------------------------------- -*/ - -/* Fuses */ -typedef struct NVM_FUSES_struct -{ - register8_t FUSEBYTE0; /* JTAG User ID */ - register8_t FUSEBYTE1; /* Watchdog Configuration */ - register8_t FUSEBYTE2; /* Reset Configuration */ - register8_t reserved_0x03; - register8_t FUSEBYTE4; /* Start-up Configuration */ - register8_t FUSEBYTE5; /* EESAVE and BOD Level */ -} NVM_FUSES_t; - -/* Boot Loader Section Reset Vector */ -typedef enum BOOTRST_enum -{ - BOOTRST_BOOTLDR_gc = (0x00<<6), /* Boot Loader Reset */ - BOOTRST_APPLICATION_gc = (0x01<<6), /* Application Reset */ -} BOOTRST_t; - -/* Timer Oscillator pin location */ -typedef enum TOSCSEL_enum -{ - TOSCSEL_ALTERNATE_gc = (0x00<<5), /* TOSC1 / TOSC2 on separate pins */ - TOSCSEL_XTAL_gc = (0x01<<5), /* TOSC1 / TOSC2 shared with XTAL1 / XTAL2 */ -} TOSCSEL_t; - -/* BOD operation */ -typedef enum BOD_enum -{ - BOD_SAMPLED_gc = (0x01<<0), /* BOD enabled in sampled mode */ - BOD_CONTINUOUS_gc = (0x02<<0), /* BOD enabled continuously */ - BOD_DISABLED_gc = (0x03<<0), /* BOD Disabled */ -} BOD_t; - -/* BOD operation */ -typedef enum BODACT_enum -{ - BODACT_SAMPLED_gc = (0x01<<4), /* BOD enabled in sampled mode */ - BODACT_CONTINUOUS_gc = (0x02<<4), /* BOD enabled continuously */ - BODACT_DISABLED_gc = (0x03<<4), /* BOD Disabled */ -} BODACT_t; - -/* Watchdog (Window) Timeout Period */ -typedef enum WD_enum -{ - WD_8CLK_gc = (0x00<<4), /* 8 cycles (8ms @ 3.3V) */ - WD_16CLK_gc = (0x01<<4), /* 16 cycles (16ms @ 3.3V) */ - WD_32CLK_gc = (0x02<<4), /* 32 cycles (32ms @ 3.3V) */ - WD_64CLK_gc = (0x03<<4), /* 64 cycles (64ms @ 3.3V) */ - WD_128CLK_gc = (0x04<<4), /* 128 cycles (0.125s @ 3.3V) */ - WD_256CLK_gc = (0x05<<4), /* 256 cycles (0.25s @ 3.3V) */ - WD_512CLK_gc = (0x06<<4), /* 512 cycles (0.5s @ 3.3V) */ - WD_1KCLK_gc = (0x07<<4), /* 1K cycles (1s @ 3.3V) */ - WD_2KCLK_gc = (0x08<<4), /* 2K cycles (2s @ 3.3V) */ - WD_4KCLK_gc = (0x09<<4), /* 4K cycles (4s @ 3.3V) */ - WD_8KCLK_gc = (0x0A<<4), /* 8K cycles (8s @ 3.3V) */ -} WD_t; - -/* Watchdog (Window) Timeout Period */ -typedef enum WDP_enum -{ - WDP_8CLK_gc = (0x00<<0), /* 8 cycles (8ms @ 3.3V) */ - WDP_16CLK_gc = (0x01<<0), /* 16 cycles (16ms @ 3.3V) */ - WDP_32CLK_gc = (0x02<<0), /* 32 cycles (32ms @ 3.3V) */ - WDP_64CLK_gc = (0x03<<0), /* 64 cycles (64ms @ 3.3V) */ - WDP_128CLK_gc = (0x04<<0), /* 128 cycles (0.125s @ 3.3V) */ - WDP_256CLK_gc = (0x05<<0), /* 256 cycles (0.25s @ 3.3V) */ - WDP_512CLK_gc = (0x06<<0), /* 512 cycles (0.5s @ 3.3V) */ - WDP_1KCLK_gc = (0x07<<0), /* 1K cycles (1s @ 3.3V) */ - WDP_2KCLK_gc = (0x08<<0), /* 2K cycles (2s @ 3.3V) */ - WDP_4KCLK_gc = (0x09<<0), /* 4K cycles (4s @ 3.3V) */ - WDP_8KCLK_gc = (0x0A<<0), /* 8K cycles (8s @ 3.3V) */ -} WDP_t; - -/* Start-up Time */ -typedef enum SUT_enum -{ - SUT_0MS_gc = (0x03<<2), /* 0 ms */ - SUT_4MS_gc = (0x01<<2), /* 4 ms */ - SUT_64MS_gc = (0x00<<2), /* 64 ms */ -} SUT_t; - -/* Brownout Detection Voltage Level */ -typedef enum BODLVL_enum -{ - BODLVL_1V6_gc = (0x07<<0), /* 1.6 V */ - BODLVL_1V8_gc = (0x06<<0), /* 1.8 V */ - BODLVL_2V0_gc = (0x05<<0), /* 2.0 V */ - BODLVL_2V2_gc = (0x04<<0), /* 2.2 V */ - BODLVL_2V4_gc = (0x03<<0), /* 2.4 V */ - BODLVL_2V6_gc = (0x02<<0), /* 2.6 V */ - BODLVL_2V8_gc = (0x01<<0), /* 2.8 V */ - BODLVL_3V0_gc = (0x00<<0), /* 3.0 V */ -} BODLVL_t; - - -/* --------------------------------------------------------------------------- -LOCKBIT - Fuses and Lockbits --------------------------------------------------------------------------- -*/ - -/* Lock Bits */ -typedef struct NVM_LOCKBITS_struct -{ - register8_t LOCK_BITS; /* Lock Bits (Changed from LOCKBITS to avoid avr-libc collision) */ -} NVM_LOCKBITS_t; - -/* Boot lock bits - boot setcion */ -typedef enum FUSE_BLBB_enum -{ - FUSE_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ - FUSE_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ - FUSE_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ - FUSE_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ -} FUSE_BLBB_t; - -/* Boot lock bits - application section */ -typedef enum FUSE_BLBA_enum -{ - FUSE_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ - FUSE_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ - FUSE_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ - FUSE_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ -} FUSE_BLBA_t; - -/* Boot lock bits - application table section */ -typedef enum FUSE_BLBAT_enum -{ - FUSE_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ - FUSE_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ - FUSE_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ - FUSE_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ -} FUSE_BLBAT_t; - -/* Lock bits */ -typedef enum FUSE_LB_enum -{ - FUSE_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ - FUSE_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ - FUSE_LB_NOLOCK_gc = (0x03<<0), /* No locks */ -} FUSE_LB_t; - - -/* --------------------------------------------------------------------------- -SIGROW - Signature Row --------------------------------------------------------------------------- -*/ - -/* Production Signatures */ -typedef struct NVM_PROD_SIGNATURES_struct -{ - register8_t RCOSC2M; /* RCOSC 2 MHz Calibration Value B */ - register8_t RCOSC2MA; /* RCOSC 2 MHz Calibration Value A */ - register8_t RCOSC32K; /* RCOSC 32.768 kHz Calibration Value */ - register8_t RCOSC32M; /* RCOSC 32 MHz Calibration Value B */ - register8_t RCOSC32MA; /* RCOSC 32 MHz Calibration Value A */ - register8_t reserved_0x05; - register8_t reserved_0x06; - register8_t reserved_0x07; - register8_t LOTNUM0; /* Lot Number Byte 0, ASCII */ - register8_t LOTNUM1; /* Lot Number Byte 1, ASCII */ - register8_t LOTNUM2; /* Lot Number Byte 2, ASCII */ - register8_t LOTNUM3; /* Lot Number Byte 3, ASCII */ - register8_t LOTNUM4; /* Lot Number Byte 4, ASCII */ - register8_t LOTNUM5; /* Lot Number Byte 5, ASCII */ - register8_t reserved_0x0E; - register8_t reserved_0x0F; - register8_t WAFNUM; /* Wafer Number */ - register8_t reserved_0x11; - register8_t COORDX0; /* Wafer Coordinate X Byte 0 */ - register8_t COORDX1; /* Wafer Coordinate X Byte 1 */ - register8_t COORDY0; /* Wafer Coordinate Y Byte 0 */ - register8_t COORDY1; /* Wafer Coordinate Y Byte 1 */ - register8_t reserved_0x16; - register8_t reserved_0x17; - register8_t reserved_0x18; - register8_t reserved_0x19; - register8_t USBCAL0; /* USB Calibration Byte 0 */ - register8_t USBCAL1; /* USB Calibration Byte 1 */ - register8_t USBRCOSC; /* USB RCOSC Calibration Value B */ - register8_t USBRCOSCA; /* USB RCOSC Calibration Value A */ - register8_t reserved_0x1E; - register8_t reserved_0x1F; - register8_t ADCACAL0; /* ADCA Calibration Byte 0 */ - register8_t ADCACAL1; /* ADCA Calibration Byte 1 */ - register8_t reserved_0x22; - register8_t reserved_0x23; - register8_t ADCBCAL0; /* ADCB Calibration Byte 0 */ - register8_t ADCBCAL1; /* ADCB Calibration Byte 1 */ - register8_t reserved_0x26; - register8_t reserved_0x27; - register8_t reserved_0x28; - register8_t reserved_0x29; - register8_t reserved_0x2A; - register8_t reserved_0x2B; - register8_t reserved_0x2C; - register8_t reserved_0x2D; - register8_t TEMPSENSE0; /* Temperature Sensor Calibration Byte 0 */ - register8_t TEMPSENSE1; /* Temperature Sensor Calibration Byte 1 */ - register8_t DACA0OFFCAL; /* DACA0 Calibration Byte 0 */ - register8_t DACA0GAINCAL; /* DACA0 Calibration Byte 1 */ - register8_t DACB0OFFCAL; /* DACB0 Calibration Byte 0 */ - register8_t DACB0GAINCAL; /* DACB0 Calibration Byte 1 */ - register8_t DACA1OFFCAL; /* DACA1 Calibration Byte 0 */ - register8_t DACA1GAINCAL; /* DACA1 Calibration Byte 1 */ - register8_t DACB1OFFCAL; /* DACB1 Calibration Byte 0 */ - register8_t DACB1GAINCAL; /* DACB1 Calibration Byte 1 */ - register8_t reserved_0x38; - register8_t reserved_0x39; - register8_t reserved_0x3A; - register8_t reserved_0x3B; - register8_t reserved_0x3C; - register8_t reserved_0x3D; - register8_t reserved_0x3E; - register8_t reserved_0x3F; - register8_t reserved_0x40; - register8_t reserved_0x41; - register8_t reserved_0x42; - register8_t reserved_0x43; - register8_t reserved_0x44; - register8_t reserved_0x45; - register8_t reserved_0x46; - register8_t reserved_0x47; -} NVM_PROD_SIGNATURES_t; - -/* -========================================================================== -IO Module Instances. Mapped to memory. -========================================================================== -*/ - -#define VPORT0 (*(VPORT_t *) 0x0010) /* Virtual Port */ -#define VPORT1 (*(VPORT_t *) 0x0014) /* Virtual Port */ -#define VPORT2 (*(VPORT_t *) 0x0018) /* Virtual Port */ -#define VPORT3 (*(VPORT_t *) 0x001C) /* Virtual Port */ -#define OCD (*(OCD_t *) 0x002E) /* On-Chip Debug System */ -#define CLK (*(CLK_t *) 0x0040) /* Clock System */ -#define SLEEP (*(SLEEP_t *) 0x0048) /* Sleep Controller */ -#define OSC (*(OSC_t *) 0x0050) /* Oscillator */ -#define DFLLRC32M (*(DFLL_t *) 0x0060) /* DFLL */ -#define DFLLRC2M (*(DFLL_t *) 0x0068) /* DFLL */ -#define PR (*(PR_t *) 0x0070) /* Power Reduction */ -#define RST (*(RST_t *) 0x0078) /* Reset */ -#define WDT (*(WDT_t *) 0x0080) /* Watch-Dog Timer */ -#define MCU (*(MCU_t *) 0x0090) /* MCU Control */ -#define PMIC (*(PMIC_t *) 0x00A0) /* Programmable Multi-level Interrupt Controller */ -#define PORTCFG (*(PORTCFG_t *) 0x00B0) /* I/O port Configuration */ -#define AES (*(AES_t *) 0x00C0) /* AES Module */ -#define CRC (*(CRC_t *) 0x00D0) /* Cyclic Redundancy Checker */ -#define DMA (*(DMA_t *) 0x0100) /* DMA Controller */ -#define EVSYS (*(EVSYS_t *) 0x0180) /* Event System */ -#define NVM (*(NVM_t *) 0x01C0) /* Non-volatile Memory Controller */ -#define ADCA (*(ADC_t *) 0x0200) /* Analog-to-Digital Converter */ -#define ADCB (*(ADC_t *) 0x0240) /* Analog-to-Digital Converter */ -#define DACA (*(DAC_t *) 0x0300) /* Digital-to-Analog Converter */ -#define DACB (*(DAC_t *) 0x0320) /* Digital-to-Analog Converter */ -#define ACA (*(AC_t *) 0x0380) /* Analog Comparator */ -#define ACB (*(AC_t *) 0x0390) /* Analog Comparator */ -#define RTC (*(RTC_t *) 0x0400) /* Real-Time Counter */ -#define EBI (*(EBI_t *) 0x0440) /* External Bus Interface */ -#define TWIC (*(TWI_t *) 0x0480) /* Two-Wire Interface */ -#define TWID (*(TWI_t *) 0x0490) /* Two-Wire Interface */ -#define TWIE (*(TWI_t *) 0x04A0) /* Two-Wire Interface */ -#define TWIF (*(TWI_t *) 0x04B0) /* Two-Wire Interface */ -#define USB (*(USB_t *) 0x04C0) /* Universal Serial Bus */ -#define PORTA (*(PORT_t *) 0x0600) /* I/O Ports */ -#define PORTB (*(PORT_t *) 0x0620) /* I/O Ports */ -#define PORTC (*(PORT_t *) 0x0640) /* I/O Ports */ -#define PORTD (*(PORT_t *) 0x0660) /* I/O Ports */ -#define PORTE (*(PORT_t *) 0x0680) /* I/O Ports */ -#define PORTF (*(PORT_t *) 0x06A0) /* I/O Ports */ -#define PORTH (*(PORT_t *) 0x06E0) /* I/O Ports */ -#define PORTJ (*(PORT_t *) 0x0700) /* I/O Ports */ -#define PORTK (*(PORT_t *) 0x0720) /* I/O Ports */ -#define PORTQ (*(PORT_t *) 0x07C0) /* I/O Ports */ -#define PORTR (*(PORT_t *) 0x07E0) /* I/O Ports */ -#define TCC0 (*(TC0_t *) 0x0800) /* 16-bit Timer/Counter 0 */ -#define TCC2 (*(TC2_t *) 0x0800) /* 16-bit Timer/Counter type 2 */ -#define TCC1 (*(TC1_t *) 0x0840) /* 16-bit Timer/Counter 1 */ -#define AWEXC (*(AWEX_t *) 0x0880) /* Advanced Waveform Extension */ -#define HIRESC (*(HIRES_t *) 0x0890) /* High-Resolution Extension */ -#define USARTC0 (*(USART_t *) 0x08A0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ -#define USARTC1 (*(USART_t *) 0x08B0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ -#define SPIC (*(SPI_t *) 0x08C0) /* Serial Peripheral Interface */ -#define IRCOM (*(IRCOM_t *) 0x08F8) /* IR Communication Module */ -#define TCD0 (*(TC0_t *) 0x0900) /* 16-bit Timer/Counter 0 */ -#define TCD2 (*(TC2_t *) 0x0900) /* 16-bit Timer/Counter type 2 */ -#define TCD1 (*(TC1_t *) 0x0940) /* 16-bit Timer/Counter 1 */ -#define HIRESD (*(HIRES_t *) 0x0990) /* High-Resolution Extension */ -#define USARTD0 (*(USART_t *) 0x09A0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ -#define USARTD1 (*(USART_t *) 0x09B0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ -#define SPID (*(SPI_t *) 0x09C0) /* Serial Peripheral Interface */ -#define TCE0 (*(TC0_t *) 0x0A00) /* 16-bit Timer/Counter 0 */ -#define TCE2 (*(TC2_t *) 0x0A00) /* 16-bit Timer/Counter type 2 */ -#define TCE1 (*(TC1_t *) 0x0A40) /* 16-bit Timer/Counter 1 */ -#define AWEXE (*(AWEX_t *) 0x0A80) /* Advanced Waveform Extension */ -#define HIRESE (*(HIRES_t *) 0x0A90) /* High-Resolution Extension */ -#define USARTE0 (*(USART_t *) 0x0AA0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ -#define USARTE1 (*(USART_t *) 0x0AB0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ -#define SPIE (*(SPI_t *) 0x0AC0) /* Serial Peripheral Interface */ -#define TCF0 (*(TC0_t *) 0x0B00) /* 16-bit Timer/Counter 0 */ -#define TCF2 (*(TC2_t *) 0x0B00) /* 16-bit Timer/Counter type 2 */ -#define TCF1 (*(TC1_t *) 0x0B40) /* 16-bit Timer/Counter 1 */ -#define HIRESF (*(HIRES_t *) 0x0B90) /* High-Resolution Extension */ -#define USARTF0 (*(USART_t *) 0x0BA0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ -#define USARTF1 (*(USART_t *) 0x0BB0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ -#define SPIF (*(SPI_t *) 0x0BC0) /* Serial Peripheral Interface */ - - -#endif /* !defined (__ASSEMBLER__) */ - - -/* ========== Flattened fully qualified IO register names ========== */ - -/* GPIO - General Purpose IO Registers */ -#define GPIO_GPIOR0 _SFR_MEM8(0x0000) -#define GPIO_GPIOR1 _SFR_MEM8(0x0001) -#define GPIO_GPIOR2 _SFR_MEM8(0x0002) -#define GPIO_GPIOR3 _SFR_MEM8(0x0003) -#define GPIO_GPIOR4 _SFR_MEM8(0x0004) -#define GPIO_GPIOR5 _SFR_MEM8(0x0005) -#define GPIO_GPIOR6 _SFR_MEM8(0x0006) -#define GPIO_GPIOR7 _SFR_MEM8(0x0007) -#define GPIO_GPIOR8 _SFR_MEM8(0x0008) -#define GPIO_GPIOR9 _SFR_MEM8(0x0009) -#define GPIO_GPIORA _SFR_MEM8(0x000A) -#define GPIO_GPIORB _SFR_MEM8(0x000B) -#define GPIO_GPIORC _SFR_MEM8(0x000C) -#define GPIO_GPIORD _SFR_MEM8(0x000D) -#define GPIO_GPIORE _SFR_MEM8(0x000E) -#define GPIO_GPIORF _SFR_MEM8(0x000F) - -/* Deprecated */ -#define GPIO_GPIO0 _SFR_MEM8(0x0000) -#define GPIO_GPIO1 _SFR_MEM8(0x0001) -#define GPIO_GPIO2 _SFR_MEM8(0x0002) -#define GPIO_GPIO3 _SFR_MEM8(0x0003) -#define GPIO_GPIO4 _SFR_MEM8(0x0004) -#define GPIO_GPIO5 _SFR_MEM8(0x0005) -#define GPIO_GPIO6 _SFR_MEM8(0x0006) -#define GPIO_GPIO7 _SFR_MEM8(0x0007) -#define GPIO_GPIO8 _SFR_MEM8(0x0008) -#define GPIO_GPIO9 _SFR_MEM8(0x0009) -#define GPIO_GPIOA _SFR_MEM8(0x000A) -#define GPIO_GPIOB _SFR_MEM8(0x000B) -#define GPIO_GPIOC _SFR_MEM8(0x000C) -#define GPIO_GPIOD _SFR_MEM8(0x000D) -#define GPIO_GPIOE _SFR_MEM8(0x000E) -#define GPIO_GPIOF _SFR_MEM8(0x000F) - -/* NVM_FUSES - Fuses */ -#define FUSE_FUSEBYTE0 _SFR_MEM8(0x0000) -#define FUSE_FUSEBYTE1 _SFR_MEM8(0x0001) -#define FUSE_FUSEBYTE2 _SFR_MEM8(0x0002) -#define FUSE_FUSEBYTE4 _SFR_MEM8(0x0004) -#define FUSE_FUSEBYTE5 _SFR_MEM8(0x0005) - -/* NVM_LOCKBITS - Lock Bits */ -#define LOCKBIT_LOCKBITS _SFR_MEM8(0x0000) - -/* NVM_PROD_SIGNATURES - Production Signatures */ -#define PRODSIGNATURES_RCOSC2M _SFR_MEM8(0x0000) -#define PRODSIGNATURES_RCOSC2MA _SFR_MEM8(0x0001) -#define PRODSIGNATURES_RCOSC32K _SFR_MEM8(0x0002) -#define PRODSIGNATURES_RCOSC32M _SFR_MEM8(0x0003) -#define PRODSIGNATURES_RCOSC32MA _SFR_MEM8(0x0004) -#define PRODSIGNATURES_LOTNUM0 _SFR_MEM8(0x0008) -#define PRODSIGNATURES_LOTNUM1 _SFR_MEM8(0x0009) -#define PRODSIGNATURES_LOTNUM2 _SFR_MEM8(0x000A) -#define PRODSIGNATURES_LOTNUM3 _SFR_MEM8(0x000B) -#define PRODSIGNATURES_LOTNUM4 _SFR_MEM8(0x000C) -#define PRODSIGNATURES_LOTNUM5 _SFR_MEM8(0x000D) -#define PRODSIGNATURES_WAFNUM _SFR_MEM8(0x0010) -#define PRODSIGNATURES_COORDX0 _SFR_MEM8(0x0012) -#define PRODSIGNATURES_COORDX1 _SFR_MEM8(0x0013) -#define PRODSIGNATURES_COORDY0 _SFR_MEM8(0x0014) -#define PRODSIGNATURES_COORDY1 _SFR_MEM8(0x0015) -#define PRODSIGNATURES_USBCAL0 _SFR_MEM8(0x001A) -#define PRODSIGNATURES_USBCAL1 _SFR_MEM8(0x001B) -#define PRODSIGNATURES_USBRCOSC _SFR_MEM8(0x001C) -#define PRODSIGNATURES_USBRCOSCA _SFR_MEM8(0x001D) -#define PRODSIGNATURES_ADCACAL0 _SFR_MEM8(0x0020) -#define PRODSIGNATURES_ADCACAL1 _SFR_MEM8(0x0021) -#define PRODSIGNATURES_ADCBCAL0 _SFR_MEM8(0x0024) -#define PRODSIGNATURES_ADCBCAL1 _SFR_MEM8(0x0025) -#define PRODSIGNATURES_TEMPSENSE0 _SFR_MEM8(0x002E) -#define PRODSIGNATURES_TEMPSENSE1 _SFR_MEM8(0x002F) -#define PRODSIGNATURES_DACA0OFFCAL _SFR_MEM8(0x0030) -#define PRODSIGNATURES_DACA0GAINCAL _SFR_MEM8(0x0031) -#define PRODSIGNATURES_DACB0OFFCAL _SFR_MEM8(0x0032) -#define PRODSIGNATURES_DACB0GAINCAL _SFR_MEM8(0x0033) -#define PRODSIGNATURES_DACA1OFFCAL _SFR_MEM8(0x0034) -#define PRODSIGNATURES_DACA1GAINCAL _SFR_MEM8(0x0035) -#define PRODSIGNATURES_DACB1OFFCAL _SFR_MEM8(0x0036) -#define PRODSIGNATURES_DACB1GAINCAL _SFR_MEM8(0x0037) - -/* VPORT - Virtual Port */ -#define VPORT0_DIR _SFR_MEM8(0x0010) -#define VPORT0_OUT _SFR_MEM8(0x0011) -#define VPORT0_IN _SFR_MEM8(0x0012) -#define VPORT0_INTFLAGS _SFR_MEM8(0x0013) - -/* VPORT - Virtual Port */ -#define VPORT1_DIR _SFR_MEM8(0x0014) -#define VPORT1_OUT _SFR_MEM8(0x0015) -#define VPORT1_IN _SFR_MEM8(0x0016) -#define VPORT1_INTFLAGS _SFR_MEM8(0x0017) - -/* VPORT - Virtual Port */ -#define VPORT2_DIR _SFR_MEM8(0x0018) -#define VPORT2_OUT _SFR_MEM8(0x0019) -#define VPORT2_IN _SFR_MEM8(0x001A) -#define VPORT2_INTFLAGS _SFR_MEM8(0x001B) - -/* VPORT - Virtual Port */ -#define VPORT3_DIR _SFR_MEM8(0x001C) -#define VPORT3_OUT _SFR_MEM8(0x001D) -#define VPORT3_IN _SFR_MEM8(0x001E) -#define VPORT3_INTFLAGS _SFR_MEM8(0x001F) - -/* OCD - On-Chip Debug System */ -#define OCD_OCDR0 _SFR_MEM8(0x002E) -#define OCD_OCDR1 _SFR_MEM8(0x002F) - -/* CPU - CPU registers */ -#define CPU_CCP _SFR_MEM8(0x0034) -#define CPU_RAMPD _SFR_MEM8(0x0038) -#define CPU_RAMPX _SFR_MEM8(0x0039) -#define CPU_RAMPY _SFR_MEM8(0x003A) -#define CPU_RAMPZ _SFR_MEM8(0x003B) -#define CPU_EIND _SFR_MEM8(0x003C) -#define CPU_SPL _SFR_MEM8(0x003D) -#define CPU_SPH _SFR_MEM8(0x003E) -#define CPU_SREG _SFR_MEM8(0x003F) - -/* CLK - Clock System */ -#define CLK_CTRL _SFR_MEM8(0x0040) -#define CLK_PSCTRL _SFR_MEM8(0x0041) -#define CLK_LOCK _SFR_MEM8(0x0042) -#define CLK_RTCCTRL _SFR_MEM8(0x0043) -#define CLK_USBCTRL _SFR_MEM8(0x0044) - -/* SLEEP - Sleep Controller */ -#define SLEEP_CTRL _SFR_MEM8(0x0048) - -/* OSC - Oscillator */ -#define OSC_CTRL _SFR_MEM8(0x0050) -#define OSC_STATUS _SFR_MEM8(0x0051) -#define OSC_XOSCCTRL _SFR_MEM8(0x0052) -#define OSC_XOSCFAIL _SFR_MEM8(0x0053) -#define OSC_RC32KCAL _SFR_MEM8(0x0054) -#define OSC_PLLCTRL _SFR_MEM8(0x0055) -#define OSC_DFLLCTRL _SFR_MEM8(0x0056) - -/* DFLL - DFLL */ -#define DFLLRC32M_CTRL _SFR_MEM8(0x0060) -#define DFLLRC32M_CALA _SFR_MEM8(0x0062) -#define DFLLRC32M_CALB _SFR_MEM8(0x0063) -#define DFLLRC32M_COMP0 _SFR_MEM8(0x0064) -#define DFLLRC32M_COMP1 _SFR_MEM8(0x0065) -#define DFLLRC32M_COMP2 _SFR_MEM8(0x0066) - -/* DFLL - DFLL */ -#define DFLLRC2M_CTRL _SFR_MEM8(0x0068) -#define DFLLRC2M_CALA _SFR_MEM8(0x006A) -#define DFLLRC2M_CALB _SFR_MEM8(0x006B) -#define DFLLRC2M_COMP0 _SFR_MEM8(0x006C) -#define DFLLRC2M_COMP1 _SFR_MEM8(0x006D) -#define DFLLRC2M_COMP2 _SFR_MEM8(0x006E) - -/* PR - Power Reduction */ -#define PR_PRGEN _SFR_MEM8(0x0070) -#define PR_PRPA _SFR_MEM8(0x0071) -#define PR_PRPB _SFR_MEM8(0x0072) -#define PR_PRPC _SFR_MEM8(0x0073) -#define PR_PRPD _SFR_MEM8(0x0074) -#define PR_PRPE _SFR_MEM8(0x0075) -#define PR_PRPF _SFR_MEM8(0x0076) - -/* RST - Reset */ -#define RST_STATUS _SFR_MEM8(0x0078) -#define RST_CTRL _SFR_MEM8(0x0079) - -/* WDT - Watch-Dog Timer */ -#define WDT_CTRL _SFR_MEM8(0x0080) -#define WDT_WINCTRL _SFR_MEM8(0x0081) -#define WDT_STATUS _SFR_MEM8(0x0082) - -/* MCU - MCU Control */ -#define MCU_DEVID0 _SFR_MEM8(0x0090) -#define MCU_DEVID1 _SFR_MEM8(0x0091) -#define MCU_DEVID2 _SFR_MEM8(0x0092) -#define MCU_REVID _SFR_MEM8(0x0093) -#define MCU_JTAGUID _SFR_MEM8(0x0094) -#define MCU_MCUCR _SFR_MEM8(0x0096) -#define MCU_ANAINIT _SFR_MEM8(0x0097) -#define MCU_EVSYSLOCK _SFR_MEM8(0x0098) -#define MCU_AWEXLOCK _SFR_MEM8(0x0099) - -/* PMIC - Programmable Multi-level Interrupt Controller */ -#define PMIC_STATUS _SFR_MEM8(0x00A0) -#define PMIC_INTPRI _SFR_MEM8(0x00A1) -#define PMIC_CTRL _SFR_MEM8(0x00A2) - -/* PORTCFG - I/O port Configuration */ -#define PORTCFG_MPCMASK _SFR_MEM8(0x00B0) -#define PORTCFG_VPCTRLA _SFR_MEM8(0x00B2) -#define PORTCFG_VPCTRLB _SFR_MEM8(0x00B3) -#define PORTCFG_CLKEVOUT _SFR_MEM8(0x00B4) -#define PORTCFG_EBIOUT _SFR_MEM8(0x00B5) -#define PORTCFG_EVOUTSEL _SFR_MEM8(0x00B6) - -/* AES - AES Module */ -#define AES_CTRL _SFR_MEM8(0x00C0) -#define AES_STATUS _SFR_MEM8(0x00C1) -#define AES_STATE _SFR_MEM8(0x00C2) -#define AES_KEY _SFR_MEM8(0x00C3) -#define AES_INTCTRL _SFR_MEM8(0x00C4) - -/* CRC - Cyclic Redundancy Checker */ -#define CRC_CTRL _SFR_MEM8(0x00D0) -#define CRC_STATUS _SFR_MEM8(0x00D1) -#define CRC_DATAIN _SFR_MEM8(0x00D3) -#define CRC_CHECKSUM0 _SFR_MEM8(0x00D4) -#define CRC_CHECKSUM1 _SFR_MEM8(0x00D5) -#define CRC_CHECKSUM2 _SFR_MEM8(0x00D6) -#define CRC_CHECKSUM3 _SFR_MEM8(0x00D7) - -/* DMA - DMA Controller */ -#define DMA_CTRL _SFR_MEM8(0x0100) -#define DMA_INTFLAGS _SFR_MEM8(0x0103) -#define DMA_STATUS _SFR_MEM8(0x0104) -#define DMA_TEMP _SFR_MEM16(0x0106) -#define DMA_CH0_CTRLA _SFR_MEM8(0x0110) -#define DMA_CH0_CTRLB _SFR_MEM8(0x0111) -#define DMA_CH0_ADDRCTRL _SFR_MEM8(0x0112) -#define DMA_CH0_TRIGSRC _SFR_MEM8(0x0113) -#define DMA_CH0_TRFCNT _SFR_MEM16(0x0114) -#define DMA_CH0_REPCNT _SFR_MEM8(0x0116) -#define DMA_CH0_SRCADDR0 _SFR_MEM8(0x0118) -#define DMA_CH0_SRCADDR1 _SFR_MEM8(0x0119) -#define DMA_CH0_SRCADDR2 _SFR_MEM8(0x011A) -#define DMA_CH0_DESTADDR0 _SFR_MEM8(0x011C) -#define DMA_CH0_DESTADDR1 _SFR_MEM8(0x011D) -#define DMA_CH0_DESTADDR2 _SFR_MEM8(0x011E) -#define DMA_CH1_CTRLA _SFR_MEM8(0x0120) -#define DMA_CH1_CTRLB _SFR_MEM8(0x0121) -#define DMA_CH1_ADDRCTRL _SFR_MEM8(0x0122) -#define DMA_CH1_TRIGSRC _SFR_MEM8(0x0123) -#define DMA_CH1_TRFCNT _SFR_MEM16(0x0124) -#define DMA_CH1_REPCNT _SFR_MEM8(0x0126) -#define DMA_CH1_SRCADDR0 _SFR_MEM8(0x0128) -#define DMA_CH1_SRCADDR1 _SFR_MEM8(0x0129) -#define DMA_CH1_SRCADDR2 _SFR_MEM8(0x012A) -#define DMA_CH1_DESTADDR0 _SFR_MEM8(0x012C) -#define DMA_CH1_DESTADDR1 _SFR_MEM8(0x012D) -#define DMA_CH1_DESTADDR2 _SFR_MEM8(0x012E) -#define DMA_CH2_CTRLA _SFR_MEM8(0x0130) -#define DMA_CH2_CTRLB _SFR_MEM8(0x0131) -#define DMA_CH2_ADDRCTRL _SFR_MEM8(0x0132) -#define DMA_CH2_TRIGSRC _SFR_MEM8(0x0133) -#define DMA_CH2_TRFCNT _SFR_MEM16(0x0134) -#define DMA_CH2_REPCNT _SFR_MEM8(0x0136) -#define DMA_CH2_SRCADDR0 _SFR_MEM8(0x0138) -#define DMA_CH2_SRCADDR1 _SFR_MEM8(0x0139) -#define DMA_CH2_SRCADDR2 _SFR_MEM8(0x013A) -#define DMA_CH2_DESTADDR0 _SFR_MEM8(0x013C) -#define DMA_CH2_DESTADDR1 _SFR_MEM8(0x013D) -#define DMA_CH2_DESTADDR2 _SFR_MEM8(0x013E) -#define DMA_CH3_CTRLA _SFR_MEM8(0x0140) -#define DMA_CH3_CTRLB _SFR_MEM8(0x0141) -#define DMA_CH3_ADDRCTRL _SFR_MEM8(0x0142) -#define DMA_CH3_TRIGSRC _SFR_MEM8(0x0143) -#define DMA_CH3_TRFCNT _SFR_MEM16(0x0144) -#define DMA_CH3_REPCNT _SFR_MEM8(0x0146) -#define DMA_CH3_SRCADDR0 _SFR_MEM8(0x0148) -#define DMA_CH3_SRCADDR1 _SFR_MEM8(0x0149) -#define DMA_CH3_SRCADDR2 _SFR_MEM8(0x014A) -#define DMA_CH3_DESTADDR0 _SFR_MEM8(0x014C) -#define DMA_CH3_DESTADDR1 _SFR_MEM8(0x014D) -#define DMA_CH3_DESTADDR2 _SFR_MEM8(0x014E) - -/* EVSYS - Event System */ -#define EVSYS_CH0MUX _SFR_MEM8(0x0180) -#define EVSYS_CH1MUX _SFR_MEM8(0x0181) -#define EVSYS_CH2MUX _SFR_MEM8(0x0182) -#define EVSYS_CH3MUX _SFR_MEM8(0x0183) -#define EVSYS_CH4MUX _SFR_MEM8(0x0184) -#define EVSYS_CH5MUX _SFR_MEM8(0x0185) -#define EVSYS_CH6MUX _SFR_MEM8(0x0186) -#define EVSYS_CH7MUX _SFR_MEM8(0x0187) -#define EVSYS_CH0CTRL _SFR_MEM8(0x0188) -#define EVSYS_CH1CTRL _SFR_MEM8(0x0189) -#define EVSYS_CH2CTRL _SFR_MEM8(0x018A) -#define EVSYS_CH3CTRL _SFR_MEM8(0x018B) -#define EVSYS_CH4CTRL _SFR_MEM8(0x018C) -#define EVSYS_CH5CTRL _SFR_MEM8(0x018D) -#define EVSYS_CH6CTRL _SFR_MEM8(0x018E) -#define EVSYS_CH7CTRL _SFR_MEM8(0x018F) -#define EVSYS_STROBE _SFR_MEM8(0x0190) -#define EVSYS_DATA _SFR_MEM8(0x0191) - -/* NVM - Non-volatile Memory Controller */ -#define NVM_ADDR0 _SFR_MEM8(0x01C0) -#define NVM_ADDR1 _SFR_MEM8(0x01C1) -#define NVM_ADDR2 _SFR_MEM8(0x01C2) -#define NVM_DATA0 _SFR_MEM8(0x01C4) -#define NVM_DATA1 _SFR_MEM8(0x01C5) -#define NVM_DATA2 _SFR_MEM8(0x01C6) -#define NVM_CMD _SFR_MEM8(0x01CA) -#define NVM_CTRLA _SFR_MEM8(0x01CB) -#define NVM_CTRLB _SFR_MEM8(0x01CC) -#define NVM_INTCTRL _SFR_MEM8(0x01CD) -#define NVM_STATUS _SFR_MEM8(0x01CF) -#define NVM_LOCKBITS _SFR_MEM8(0x01D0) - -/* ADC - Analog-to-Digital Converter */ -#define ADCA_CTRLA _SFR_MEM8(0x0200) -#define ADCA_CTRLB _SFR_MEM8(0x0201) -#define ADCA_REFCTRL _SFR_MEM8(0x0202) -#define ADCA_EVCTRL _SFR_MEM8(0x0203) -#define ADCA_PRESCALER _SFR_MEM8(0x0204) -#define ADCA_INTFLAGS _SFR_MEM8(0x0206) -#define ADCA_TEMP _SFR_MEM8(0x0207) -#define ADCA_CAL _SFR_MEM16(0x020C) -#define ADCA_CH0RES _SFR_MEM16(0x0210) -#define ADCA_CH1RES _SFR_MEM16(0x0212) -#define ADCA_CH2RES _SFR_MEM16(0x0214) -#define ADCA_CH3RES _SFR_MEM16(0x0216) -#define ADCA_CMP _SFR_MEM16(0x0218) -#define ADCA_CH0_CTRL _SFR_MEM8(0x0220) -#define ADCA_CH0_MUXCTRL _SFR_MEM8(0x0221) -#define ADCA_CH0_INTCTRL _SFR_MEM8(0x0222) -#define ADCA_CH0_INTFLAGS _SFR_MEM8(0x0223) -#define ADCA_CH0_RES _SFR_MEM16(0x0224) -#define ADCA_CH0_SCAN _SFR_MEM8(0x0226) -#define ADCA_CH1_CTRL _SFR_MEM8(0x0228) -#define ADCA_CH1_MUXCTRL _SFR_MEM8(0x0229) -#define ADCA_CH1_INTCTRL _SFR_MEM8(0x022A) -#define ADCA_CH1_INTFLAGS _SFR_MEM8(0x022B) -#define ADCA_CH1_RES _SFR_MEM16(0x022C) -#define ADCA_CH1_SCAN _SFR_MEM8(0x022E) -#define ADCA_CH2_CTRL _SFR_MEM8(0x0230) -#define ADCA_CH2_MUXCTRL _SFR_MEM8(0x0231) -#define ADCA_CH2_INTCTRL _SFR_MEM8(0x0232) -#define ADCA_CH2_INTFLAGS _SFR_MEM8(0x0233) -#define ADCA_CH2_RES _SFR_MEM16(0x0234) -#define ADCA_CH2_SCAN _SFR_MEM8(0x0236) -#define ADCA_CH3_CTRL _SFR_MEM8(0x0238) -#define ADCA_CH3_MUXCTRL _SFR_MEM8(0x0239) -#define ADCA_CH3_INTCTRL _SFR_MEM8(0x023A) -#define ADCA_CH3_INTFLAGS _SFR_MEM8(0x023B) -#define ADCA_CH3_RES _SFR_MEM16(0x023C) -#define ADCA_CH3_SCAN _SFR_MEM8(0x023E) - -/* ADC - Analog-to-Digital Converter */ -#define ADCB_CTRLA _SFR_MEM8(0x0240) -#define ADCB_CTRLB _SFR_MEM8(0x0241) -#define ADCB_REFCTRL _SFR_MEM8(0x0242) -#define ADCB_EVCTRL _SFR_MEM8(0x0243) -#define ADCB_PRESCALER _SFR_MEM8(0x0244) -#define ADCB_INTFLAGS _SFR_MEM8(0x0246) -#define ADCB_TEMP _SFR_MEM8(0x0247) -#define ADCB_CAL _SFR_MEM16(0x024C) -#define ADCB_CH0RES _SFR_MEM16(0x0250) -#define ADCB_CH1RES _SFR_MEM16(0x0252) -#define ADCB_CH2RES _SFR_MEM16(0x0254) -#define ADCB_CH3RES _SFR_MEM16(0x0256) -#define ADCB_CMP _SFR_MEM16(0x0258) -#define ADCB_CH0_CTRL _SFR_MEM8(0x0260) -#define ADCB_CH0_MUXCTRL _SFR_MEM8(0x0261) -#define ADCB_CH0_INTCTRL _SFR_MEM8(0x0262) -#define ADCB_CH0_INTFLAGS _SFR_MEM8(0x0263) -#define ADCB_CH0_RES _SFR_MEM16(0x0264) -#define ADCB_CH0_SCAN _SFR_MEM8(0x0266) -#define ADCB_CH1_CTRL _SFR_MEM8(0x0268) -#define ADCB_CH1_MUXCTRL _SFR_MEM8(0x0269) -#define ADCB_CH1_INTCTRL _SFR_MEM8(0x026A) -#define ADCB_CH1_INTFLAGS _SFR_MEM8(0x026B) -#define ADCB_CH1_RES _SFR_MEM16(0x026C) -#define ADCB_CH1_SCAN _SFR_MEM8(0x026E) -#define ADCB_CH2_CTRL _SFR_MEM8(0x0270) -#define ADCB_CH2_MUXCTRL _SFR_MEM8(0x0271) -#define ADCB_CH2_INTCTRL _SFR_MEM8(0x0272) -#define ADCB_CH2_INTFLAGS _SFR_MEM8(0x0273) -#define ADCB_CH2_RES _SFR_MEM16(0x0274) -#define ADCB_CH2_SCAN _SFR_MEM8(0x0276) -#define ADCB_CH3_CTRL _SFR_MEM8(0x0278) -#define ADCB_CH3_MUXCTRL _SFR_MEM8(0x0279) -#define ADCB_CH3_INTCTRL _SFR_MEM8(0x027A) -#define ADCB_CH3_INTFLAGS _SFR_MEM8(0x027B) -#define ADCB_CH3_RES _SFR_MEM16(0x027C) -#define ADCB_CH3_SCAN _SFR_MEM8(0x027E) - -/* DAC - Digital-to-Analog Converter */ -#define DACA_CTRLA _SFR_MEM8(0x0300) -#define DACA_CTRLB _SFR_MEM8(0x0301) -#define DACA_CTRLC _SFR_MEM8(0x0302) -#define DACA_EVCTRL _SFR_MEM8(0x0303) -#define DACA_STATUS _SFR_MEM8(0x0305) -#define DACA_CH0GAINCAL _SFR_MEM8(0x0308) -#define DACA_CH0OFFSETCAL _SFR_MEM8(0x0309) -#define DACA_CH1GAINCAL _SFR_MEM8(0x030A) -#define DACA_CH1OFFSETCAL _SFR_MEM8(0x030B) -#define DACA_CH0DATA _SFR_MEM16(0x0318) -#define DACA_CH1DATA _SFR_MEM16(0x031A) - -/* DAC - Digital-to-Analog Converter */ -#define DACB_CTRLA _SFR_MEM8(0x0320) -#define DACB_CTRLB _SFR_MEM8(0x0321) -#define DACB_CTRLC _SFR_MEM8(0x0322) -#define DACB_EVCTRL _SFR_MEM8(0x0323) -#define DACB_STATUS _SFR_MEM8(0x0325) -#define DACB_CH0GAINCAL _SFR_MEM8(0x0328) -#define DACB_CH0OFFSETCAL _SFR_MEM8(0x0329) -#define DACB_CH1GAINCAL _SFR_MEM8(0x032A) -#define DACB_CH1OFFSETCAL _SFR_MEM8(0x032B) -#define DACB_CH0DATA _SFR_MEM16(0x0338) -#define DACB_CH1DATA _SFR_MEM16(0x033A) - -/* AC - Analog Comparator */ -#define ACA_AC0CTRL _SFR_MEM8(0x0380) -#define ACA_AC1CTRL _SFR_MEM8(0x0381) -#define ACA_AC0MUXCTRL _SFR_MEM8(0x0382) -#define ACA_AC1MUXCTRL _SFR_MEM8(0x0383) -#define ACA_CTRLA _SFR_MEM8(0x0384) -#define ACA_CTRLB _SFR_MEM8(0x0385) -#define ACA_WINCTRL _SFR_MEM8(0x0386) -#define ACA_STATUS _SFR_MEM8(0x0387) - -/* AC - Analog Comparator */ -#define ACB_AC0CTRL _SFR_MEM8(0x0390) -#define ACB_AC1CTRL _SFR_MEM8(0x0391) -#define ACB_AC0MUXCTRL _SFR_MEM8(0x0392) -#define ACB_AC1MUXCTRL _SFR_MEM8(0x0393) -#define ACB_CTRLA _SFR_MEM8(0x0394) -#define ACB_CTRLB _SFR_MEM8(0x0395) -#define ACB_WINCTRL _SFR_MEM8(0x0396) -#define ACB_STATUS _SFR_MEM8(0x0397) - -/* RTC - Real-Time Counter */ -#define RTC_CTRL _SFR_MEM8(0x0400) -#define RTC_STATUS _SFR_MEM8(0x0401) -#define RTC_INTCTRL _SFR_MEM8(0x0402) -#define RTC_INTFLAGS _SFR_MEM8(0x0403) -#define RTC_TEMP _SFR_MEM8(0x0404) -#define RTC_CNT _SFR_MEM16(0x0408) -#define RTC_PER _SFR_MEM16(0x040A) -#define RTC_COMP _SFR_MEM16(0x040C) - -/* EBI - External Bus Interface */ -#define EBI_CTRL _SFR_MEM8(0x0440) -#define EBI_SDRAMCTRLA _SFR_MEM8(0x0441) -#define EBI_REFRESH _SFR_MEM16(0x0444) -#define EBI_INITDLY _SFR_MEM16(0x0446) -#define EBI_SDRAMCTRLB _SFR_MEM8(0x0448) -#define EBI_SDRAMCTRLC _SFR_MEM8(0x0449) -#define EBI_CS0_CTRLA _SFR_MEM8(0x0450) -#define EBI_CS0_CTRLB _SFR_MEM8(0x0451) -#define EBI_CS0_BASEADDR _SFR_MEM16(0x0452) -#define EBI_CS1_CTRLA _SFR_MEM8(0x0454) -#define EBI_CS1_CTRLB _SFR_MEM8(0x0455) -#define EBI_CS1_BASEADDR _SFR_MEM16(0x0456) -#define EBI_CS2_CTRLA _SFR_MEM8(0x0458) -#define EBI_CS2_CTRLB _SFR_MEM8(0x0459) -#define EBI_CS2_BASEADDR _SFR_MEM16(0x045A) -#define EBI_CS3_CTRLA _SFR_MEM8(0x045C) -#define EBI_CS3_CTRLB _SFR_MEM8(0x045D) -#define EBI_CS3_BASEADDR _SFR_MEM16(0x045E) - -/* TWI - Two-Wire Interface */ -#define TWIC_CTRL _SFR_MEM8(0x0480) -#define TWIC_MASTER_CTRLA _SFR_MEM8(0x0481) -#define TWIC_MASTER_CTRLB _SFR_MEM8(0x0482) -#define TWIC_MASTER_CTRLC _SFR_MEM8(0x0483) -#define TWIC_MASTER_STATUS _SFR_MEM8(0x0484) -#define TWIC_MASTER_BAUD _SFR_MEM8(0x0485) -#define TWIC_MASTER_ADDR _SFR_MEM8(0x0486) -#define TWIC_MASTER_DATA _SFR_MEM8(0x0487) -#define TWIC_SLAVE_CTRLA _SFR_MEM8(0x0488) -#define TWIC_SLAVE_CTRLB _SFR_MEM8(0x0489) -#define TWIC_SLAVE_STATUS _SFR_MEM8(0x048A) -#define TWIC_SLAVE_ADDR _SFR_MEM8(0x048B) -#define TWIC_SLAVE_DATA _SFR_MEM8(0x048C) -#define TWIC_SLAVE_ADDRMASK _SFR_MEM8(0x048D) - -/* TWI - Two-Wire Interface */ -#define TWID_CTRL _SFR_MEM8(0x0490) -#define TWID_MASTER_CTRLA _SFR_MEM8(0x0491) -#define TWID_MASTER_CTRLB _SFR_MEM8(0x0492) -#define TWID_MASTER_CTRLC _SFR_MEM8(0x0493) -#define TWID_MASTER_STATUS _SFR_MEM8(0x0494) -#define TWID_MASTER_BAUD _SFR_MEM8(0x0495) -#define TWID_MASTER_ADDR _SFR_MEM8(0x0496) -#define TWID_MASTER_DATA _SFR_MEM8(0x0497) -#define TWID_SLAVE_CTRLA _SFR_MEM8(0x0498) -#define TWID_SLAVE_CTRLB _SFR_MEM8(0x0499) -#define TWID_SLAVE_STATUS _SFR_MEM8(0x049A) -#define TWID_SLAVE_ADDR _SFR_MEM8(0x049B) -#define TWID_SLAVE_DATA _SFR_MEM8(0x049C) -#define TWID_SLAVE_ADDRMASK _SFR_MEM8(0x049D) - -/* TWI - Two-Wire Interface */ -#define TWIE_CTRL _SFR_MEM8(0x04A0) -#define TWIE_MASTER_CTRLA _SFR_MEM8(0x04A1) -#define TWIE_MASTER_CTRLB _SFR_MEM8(0x04A2) -#define TWIE_MASTER_CTRLC _SFR_MEM8(0x04A3) -#define TWIE_MASTER_STATUS _SFR_MEM8(0x04A4) -#define TWIE_MASTER_BAUD _SFR_MEM8(0x04A5) -#define TWIE_MASTER_ADDR _SFR_MEM8(0x04A6) -#define TWIE_MASTER_DATA _SFR_MEM8(0x04A7) -#define TWIE_SLAVE_CTRLA _SFR_MEM8(0x04A8) -#define TWIE_SLAVE_CTRLB _SFR_MEM8(0x04A9) -#define TWIE_SLAVE_STATUS _SFR_MEM8(0x04AA) -#define TWIE_SLAVE_ADDR _SFR_MEM8(0x04AB) -#define TWIE_SLAVE_DATA _SFR_MEM8(0x04AC) -#define TWIE_SLAVE_ADDRMASK _SFR_MEM8(0x04AD) - -/* TWI - Two-Wire Interface */ -#define TWIF_CTRL _SFR_MEM8(0x04B0) -#define TWIF_MASTER_CTRLA _SFR_MEM8(0x04B1) -#define TWIF_MASTER_CTRLB _SFR_MEM8(0x04B2) -#define TWIF_MASTER_CTRLC _SFR_MEM8(0x04B3) -#define TWIF_MASTER_STATUS _SFR_MEM8(0x04B4) -#define TWIF_MASTER_BAUD _SFR_MEM8(0x04B5) -#define TWIF_MASTER_ADDR _SFR_MEM8(0x04B6) -#define TWIF_MASTER_DATA _SFR_MEM8(0x04B7) -#define TWIF_SLAVE_CTRLA _SFR_MEM8(0x04B8) -#define TWIF_SLAVE_CTRLB _SFR_MEM8(0x04B9) -#define TWIF_SLAVE_STATUS _SFR_MEM8(0x04BA) -#define TWIF_SLAVE_ADDR _SFR_MEM8(0x04BB) -#define TWIF_SLAVE_DATA _SFR_MEM8(0x04BC) -#define TWIF_SLAVE_ADDRMASK _SFR_MEM8(0x04BD) - -/* USB - Universal Serial Bus */ -#define USB_CTRLA _SFR_MEM8(0x04C0) -#define USB_CTRLB _SFR_MEM8(0x04C1) -#define USB_STATUS _SFR_MEM8(0x04C2) -#define USB_ADDR _SFR_MEM8(0x04C3) -#define USB_FIFOWP _SFR_MEM8(0x04C4) -#define USB_FIFORP _SFR_MEM8(0x04C5) -#define USB_EPPTR _SFR_MEM16(0x04C6) -#define USB_INTCTRLA _SFR_MEM8(0x04C8) -#define USB_INTCTRLB _SFR_MEM8(0x04C9) -#define USB_INTFLAGSACLR _SFR_MEM8(0x04CA) -#define USB_INTFLAGSASET _SFR_MEM8(0x04CB) -#define USB_INTFLAGSBCLR _SFR_MEM8(0x04CC) -#define USB_INTFLAGSBSET _SFR_MEM8(0x04CD) -#define USB_CAL0 _SFR_MEM8(0x04FA) -#define USB_CAL1 _SFR_MEM8(0x04FB) - -/* PORT - I/O Ports */ -#define PORTA_DIR _SFR_MEM8(0x0600) -#define PORTA_DIRSET _SFR_MEM8(0x0601) -#define PORTA_DIRCLR _SFR_MEM8(0x0602) -#define PORTA_DIRTGL _SFR_MEM8(0x0603) -#define PORTA_OUT _SFR_MEM8(0x0604) -#define PORTA_OUTSET _SFR_MEM8(0x0605) -#define PORTA_OUTCLR _SFR_MEM8(0x0606) -#define PORTA_OUTTGL _SFR_MEM8(0x0607) -#define PORTA_IN _SFR_MEM8(0x0608) -#define PORTA_INTCTRL _SFR_MEM8(0x0609) -#define PORTA_INT0MASK _SFR_MEM8(0x060A) -#define PORTA_INT1MASK _SFR_MEM8(0x060B) -#define PORTA_INTFLAGS _SFR_MEM8(0x060C) -#define PORTA_REMAP _SFR_MEM8(0x060E) -#define PORTA_PIN0CTRL _SFR_MEM8(0x0610) -#define PORTA_PIN1CTRL _SFR_MEM8(0x0611) -#define PORTA_PIN2CTRL _SFR_MEM8(0x0612) -#define PORTA_PIN3CTRL _SFR_MEM8(0x0613) -#define PORTA_PIN4CTRL _SFR_MEM8(0x0614) -#define PORTA_PIN5CTRL _SFR_MEM8(0x0615) -#define PORTA_PIN6CTRL _SFR_MEM8(0x0616) -#define PORTA_PIN7CTRL _SFR_MEM8(0x0617) - -/* PORT - I/O Ports */ -#define PORTB_DIR _SFR_MEM8(0x0620) -#define PORTB_DIRSET _SFR_MEM8(0x0621) -#define PORTB_DIRCLR _SFR_MEM8(0x0622) -#define PORTB_DIRTGL _SFR_MEM8(0x0623) -#define PORTB_OUT _SFR_MEM8(0x0624) -#define PORTB_OUTSET _SFR_MEM8(0x0625) -#define PORTB_OUTCLR _SFR_MEM8(0x0626) -#define PORTB_OUTTGL _SFR_MEM8(0x0627) -#define PORTB_IN _SFR_MEM8(0x0628) -#define PORTB_INTCTRL _SFR_MEM8(0x0629) -#define PORTB_INT0MASK _SFR_MEM8(0x062A) -#define PORTB_INT1MASK _SFR_MEM8(0x062B) -#define PORTB_INTFLAGS _SFR_MEM8(0x062C) -#define PORTB_REMAP _SFR_MEM8(0x062E) -#define PORTB_PIN0CTRL _SFR_MEM8(0x0630) -#define PORTB_PIN1CTRL _SFR_MEM8(0x0631) -#define PORTB_PIN2CTRL _SFR_MEM8(0x0632) -#define PORTB_PIN3CTRL _SFR_MEM8(0x0633) -#define PORTB_PIN4CTRL _SFR_MEM8(0x0634) -#define PORTB_PIN5CTRL _SFR_MEM8(0x0635) -#define PORTB_PIN6CTRL _SFR_MEM8(0x0636) -#define PORTB_PIN7CTRL _SFR_MEM8(0x0637) - -/* PORT - I/O Ports */ -#define PORTC_DIR _SFR_MEM8(0x0640) -#define PORTC_DIRSET _SFR_MEM8(0x0641) -#define PORTC_DIRCLR _SFR_MEM8(0x0642) -#define PORTC_DIRTGL _SFR_MEM8(0x0643) -#define PORTC_OUT _SFR_MEM8(0x0644) -#define PORTC_OUTSET _SFR_MEM8(0x0645) -#define PORTC_OUTCLR _SFR_MEM8(0x0646) -#define PORTC_OUTTGL _SFR_MEM8(0x0647) -#define PORTC_IN _SFR_MEM8(0x0648) -#define PORTC_INTCTRL _SFR_MEM8(0x0649) -#define PORTC_INT0MASK _SFR_MEM8(0x064A) -#define PORTC_INT1MASK _SFR_MEM8(0x064B) -#define PORTC_INTFLAGS _SFR_MEM8(0x064C) -#define PORTC_REMAP _SFR_MEM8(0x064E) -#define PORTC_PIN0CTRL _SFR_MEM8(0x0650) -#define PORTC_PIN1CTRL _SFR_MEM8(0x0651) -#define PORTC_PIN2CTRL _SFR_MEM8(0x0652) -#define PORTC_PIN3CTRL _SFR_MEM8(0x0653) -#define PORTC_PIN4CTRL _SFR_MEM8(0x0654) -#define PORTC_PIN5CTRL _SFR_MEM8(0x0655) -#define PORTC_PIN6CTRL _SFR_MEM8(0x0656) -#define PORTC_PIN7CTRL _SFR_MEM8(0x0657) - -/* PORT - I/O Ports */ -#define PORTD_DIR _SFR_MEM8(0x0660) -#define PORTD_DIRSET _SFR_MEM8(0x0661) -#define PORTD_DIRCLR _SFR_MEM8(0x0662) -#define PORTD_DIRTGL _SFR_MEM8(0x0663) -#define PORTD_OUT _SFR_MEM8(0x0664) -#define PORTD_OUTSET _SFR_MEM8(0x0665) -#define PORTD_OUTCLR _SFR_MEM8(0x0666) -#define PORTD_OUTTGL _SFR_MEM8(0x0667) -#define PORTD_IN _SFR_MEM8(0x0668) -#define PORTD_INTCTRL _SFR_MEM8(0x0669) -#define PORTD_INT0MASK _SFR_MEM8(0x066A) -#define PORTD_INT1MASK _SFR_MEM8(0x066B) -#define PORTD_INTFLAGS _SFR_MEM8(0x066C) -#define PORTD_REMAP _SFR_MEM8(0x066E) -#define PORTD_PIN0CTRL _SFR_MEM8(0x0670) -#define PORTD_PIN1CTRL _SFR_MEM8(0x0671) -#define PORTD_PIN2CTRL _SFR_MEM8(0x0672) -#define PORTD_PIN3CTRL _SFR_MEM8(0x0673) -#define PORTD_PIN4CTRL _SFR_MEM8(0x0674) -#define PORTD_PIN5CTRL _SFR_MEM8(0x0675) -#define PORTD_PIN6CTRL _SFR_MEM8(0x0676) -#define PORTD_PIN7CTRL _SFR_MEM8(0x0677) - -/* PORT - I/O Ports */ -#define PORTE_DIR _SFR_MEM8(0x0680) -#define PORTE_DIRSET _SFR_MEM8(0x0681) -#define PORTE_DIRCLR _SFR_MEM8(0x0682) -#define PORTE_DIRTGL _SFR_MEM8(0x0683) -#define PORTE_OUT _SFR_MEM8(0x0684) -#define PORTE_OUTSET _SFR_MEM8(0x0685) -#define PORTE_OUTCLR _SFR_MEM8(0x0686) -#define PORTE_OUTTGL _SFR_MEM8(0x0687) -#define PORTE_IN _SFR_MEM8(0x0688) -#define PORTE_INTCTRL _SFR_MEM8(0x0689) -#define PORTE_INT0MASK _SFR_MEM8(0x068A) -#define PORTE_INT1MASK _SFR_MEM8(0x068B) -#define PORTE_INTFLAGS _SFR_MEM8(0x068C) -#define PORTE_REMAP _SFR_MEM8(0x068E) -#define PORTE_PIN0CTRL _SFR_MEM8(0x0690) -#define PORTE_PIN1CTRL _SFR_MEM8(0x0691) -#define PORTE_PIN2CTRL _SFR_MEM8(0x0692) -#define PORTE_PIN3CTRL _SFR_MEM8(0x0693) -#define PORTE_PIN4CTRL _SFR_MEM8(0x0694) -#define PORTE_PIN5CTRL _SFR_MEM8(0x0695) -#define PORTE_PIN6CTRL _SFR_MEM8(0x0696) -#define PORTE_PIN7CTRL _SFR_MEM8(0x0697) - -/* PORT - I/O Ports */ -#define PORTF_DIR _SFR_MEM8(0x06A0) -#define PORTF_DIRSET _SFR_MEM8(0x06A1) -#define PORTF_DIRCLR _SFR_MEM8(0x06A2) -#define PORTF_DIRTGL _SFR_MEM8(0x06A3) -#define PORTF_OUT _SFR_MEM8(0x06A4) -#define PORTF_OUTSET _SFR_MEM8(0x06A5) -#define PORTF_OUTCLR _SFR_MEM8(0x06A6) -#define PORTF_OUTTGL _SFR_MEM8(0x06A7) -#define PORTF_IN _SFR_MEM8(0x06A8) -#define PORTF_INTCTRL _SFR_MEM8(0x06A9) -#define PORTF_INT0MASK _SFR_MEM8(0x06AA) -#define PORTF_INT1MASK _SFR_MEM8(0x06AB) -#define PORTF_INTFLAGS _SFR_MEM8(0x06AC) -#define PORTF_REMAP _SFR_MEM8(0x06AE) -#define PORTF_PIN0CTRL _SFR_MEM8(0x06B0) -#define PORTF_PIN1CTRL _SFR_MEM8(0x06B1) -#define PORTF_PIN2CTRL _SFR_MEM8(0x06B2) -#define PORTF_PIN3CTRL _SFR_MEM8(0x06B3) -#define PORTF_PIN4CTRL _SFR_MEM8(0x06B4) -#define PORTF_PIN5CTRL _SFR_MEM8(0x06B5) -#define PORTF_PIN6CTRL _SFR_MEM8(0x06B6) -#define PORTF_PIN7CTRL _SFR_MEM8(0x06B7) - -/* PORT - I/O Ports */ -#define PORTH_DIR _SFR_MEM8(0x06E0) -#define PORTH_DIRSET _SFR_MEM8(0x06E1) -#define PORTH_DIRCLR _SFR_MEM8(0x06E2) -#define PORTH_DIRTGL _SFR_MEM8(0x06E3) -#define PORTH_OUT _SFR_MEM8(0x06E4) -#define PORTH_OUTSET _SFR_MEM8(0x06E5) -#define PORTH_OUTCLR _SFR_MEM8(0x06E6) -#define PORTH_OUTTGL _SFR_MEM8(0x06E7) -#define PORTH_IN _SFR_MEM8(0x06E8) -#define PORTH_INTCTRL _SFR_MEM8(0x06E9) -#define PORTH_INT0MASK _SFR_MEM8(0x06EA) -#define PORTH_INT1MASK _SFR_MEM8(0x06EB) -#define PORTH_INTFLAGS _SFR_MEM8(0x06EC) -#define PORTH_REMAP _SFR_MEM8(0x06EE) -#define PORTH_PIN0CTRL _SFR_MEM8(0x06F0) -#define PORTH_PIN1CTRL _SFR_MEM8(0x06F1) -#define PORTH_PIN2CTRL _SFR_MEM8(0x06F2) -#define PORTH_PIN3CTRL _SFR_MEM8(0x06F3) -#define PORTH_PIN4CTRL _SFR_MEM8(0x06F4) -#define PORTH_PIN5CTRL _SFR_MEM8(0x06F5) -#define PORTH_PIN6CTRL _SFR_MEM8(0x06F6) -#define PORTH_PIN7CTRL _SFR_MEM8(0x06F7) - -/* PORT - I/O Ports */ -#define PORTJ_DIR _SFR_MEM8(0x0700) -#define PORTJ_DIRSET _SFR_MEM8(0x0701) -#define PORTJ_DIRCLR _SFR_MEM8(0x0702) -#define PORTJ_DIRTGL _SFR_MEM8(0x0703) -#define PORTJ_OUT _SFR_MEM8(0x0704) -#define PORTJ_OUTSET _SFR_MEM8(0x0705) -#define PORTJ_OUTCLR _SFR_MEM8(0x0706) -#define PORTJ_OUTTGL _SFR_MEM8(0x0707) -#define PORTJ_IN _SFR_MEM8(0x0708) -#define PORTJ_INTCTRL _SFR_MEM8(0x0709) -#define PORTJ_INT0MASK _SFR_MEM8(0x070A) -#define PORTJ_INT1MASK _SFR_MEM8(0x070B) -#define PORTJ_INTFLAGS _SFR_MEM8(0x070C) -#define PORTJ_REMAP _SFR_MEM8(0x070E) -#define PORTJ_PIN0CTRL _SFR_MEM8(0x0710) -#define PORTJ_PIN1CTRL _SFR_MEM8(0x0711) -#define PORTJ_PIN2CTRL _SFR_MEM8(0x0712) -#define PORTJ_PIN3CTRL _SFR_MEM8(0x0713) -#define PORTJ_PIN4CTRL _SFR_MEM8(0x0714) -#define PORTJ_PIN5CTRL _SFR_MEM8(0x0715) -#define PORTJ_PIN6CTRL _SFR_MEM8(0x0716) -#define PORTJ_PIN7CTRL _SFR_MEM8(0x0717) - -/* PORT - I/O Ports */ -#define PORTK_DIR _SFR_MEM8(0x0720) -#define PORTK_DIRSET _SFR_MEM8(0x0721) -#define PORTK_DIRCLR _SFR_MEM8(0x0722) -#define PORTK_DIRTGL _SFR_MEM8(0x0723) -#define PORTK_OUT _SFR_MEM8(0x0724) -#define PORTK_OUTSET _SFR_MEM8(0x0725) -#define PORTK_OUTCLR _SFR_MEM8(0x0726) -#define PORTK_OUTTGL _SFR_MEM8(0x0727) -#define PORTK_IN _SFR_MEM8(0x0728) -#define PORTK_INTCTRL _SFR_MEM8(0x0729) -#define PORTK_INT0MASK _SFR_MEM8(0x072A) -#define PORTK_INT1MASK _SFR_MEM8(0x072B) -#define PORTK_INTFLAGS _SFR_MEM8(0x072C) -#define PORTK_REMAP _SFR_MEM8(0x072E) -#define PORTK_PIN0CTRL _SFR_MEM8(0x0730) -#define PORTK_PIN1CTRL _SFR_MEM8(0x0731) -#define PORTK_PIN2CTRL _SFR_MEM8(0x0732) -#define PORTK_PIN3CTRL _SFR_MEM8(0x0733) -#define PORTK_PIN4CTRL _SFR_MEM8(0x0734) -#define PORTK_PIN5CTRL _SFR_MEM8(0x0735) -#define PORTK_PIN6CTRL _SFR_MEM8(0x0736) -#define PORTK_PIN7CTRL _SFR_MEM8(0x0737) - -/* PORT - I/O Ports */ -#define PORTQ_DIR _SFR_MEM8(0x07C0) -#define PORTQ_DIRSET _SFR_MEM8(0x07C1) -#define PORTQ_DIRCLR _SFR_MEM8(0x07C2) -#define PORTQ_DIRTGL _SFR_MEM8(0x07C3) -#define PORTQ_OUT _SFR_MEM8(0x07C4) -#define PORTQ_OUTSET _SFR_MEM8(0x07C5) -#define PORTQ_OUTCLR _SFR_MEM8(0x07C6) -#define PORTQ_OUTTGL _SFR_MEM8(0x07C7) -#define PORTQ_IN _SFR_MEM8(0x07C8) -#define PORTQ_INTCTRL _SFR_MEM8(0x07C9) -#define PORTQ_INT0MASK _SFR_MEM8(0x07CA) -#define PORTQ_INT1MASK _SFR_MEM8(0x07CB) -#define PORTQ_INTFLAGS _SFR_MEM8(0x07CC) -#define PORTQ_REMAP _SFR_MEM8(0x07CE) -#define PORTQ_PIN0CTRL _SFR_MEM8(0x07D0) -#define PORTQ_PIN1CTRL _SFR_MEM8(0x07D1) -#define PORTQ_PIN2CTRL _SFR_MEM8(0x07D2) -#define PORTQ_PIN3CTRL _SFR_MEM8(0x07D3) -#define PORTQ_PIN4CTRL _SFR_MEM8(0x07D4) -#define PORTQ_PIN5CTRL _SFR_MEM8(0x07D5) -#define PORTQ_PIN6CTRL _SFR_MEM8(0x07D6) -#define PORTQ_PIN7CTRL _SFR_MEM8(0x07D7) - -/* PORT - I/O Ports */ -#define PORTR_DIR _SFR_MEM8(0x07E0) -#define PORTR_DIRSET _SFR_MEM8(0x07E1) -#define PORTR_DIRCLR _SFR_MEM8(0x07E2) -#define PORTR_DIRTGL _SFR_MEM8(0x07E3) -#define PORTR_OUT _SFR_MEM8(0x07E4) -#define PORTR_OUTSET _SFR_MEM8(0x07E5) -#define PORTR_OUTCLR _SFR_MEM8(0x07E6) -#define PORTR_OUTTGL _SFR_MEM8(0x07E7) -#define PORTR_IN _SFR_MEM8(0x07E8) -#define PORTR_INTCTRL _SFR_MEM8(0x07E9) -#define PORTR_INT0MASK _SFR_MEM8(0x07EA) -#define PORTR_INT1MASK _SFR_MEM8(0x07EB) -#define PORTR_INTFLAGS _SFR_MEM8(0x07EC) -#define PORTR_REMAP _SFR_MEM8(0x07EE) -#define PORTR_PIN0CTRL _SFR_MEM8(0x07F0) -#define PORTR_PIN1CTRL _SFR_MEM8(0x07F1) -#define PORTR_PIN2CTRL _SFR_MEM8(0x07F2) -#define PORTR_PIN3CTRL _SFR_MEM8(0x07F3) -#define PORTR_PIN4CTRL _SFR_MEM8(0x07F4) -#define PORTR_PIN5CTRL _SFR_MEM8(0x07F5) -#define PORTR_PIN6CTRL _SFR_MEM8(0x07F6) -#define PORTR_PIN7CTRL _SFR_MEM8(0x07F7) - -/* TC0 - 16-bit Timer/Counter 0 */ -#define TCC0_CTRLA _SFR_MEM8(0x0800) -#define TCC0_CTRLB _SFR_MEM8(0x0801) -#define TCC0_CTRLC _SFR_MEM8(0x0802) -#define TCC0_CTRLD _SFR_MEM8(0x0803) -#define TCC0_CTRLE _SFR_MEM8(0x0804) -#define TCC0_INTCTRLA _SFR_MEM8(0x0806) -#define TCC0_INTCTRLB _SFR_MEM8(0x0807) -#define TCC0_CTRLFCLR _SFR_MEM8(0x0808) -#define TCC0_CTRLFSET _SFR_MEM8(0x0809) -#define TCC0_CTRLGCLR _SFR_MEM8(0x080A) -#define TCC0_CTRLGSET _SFR_MEM8(0x080B) -#define TCC0_INTFLAGS _SFR_MEM8(0x080C) -#define TCC0_TEMP _SFR_MEM8(0x080F) -#define TCC0_CNT _SFR_MEM16(0x0820) -#define TCC0_PER _SFR_MEM16(0x0826) -#define TCC0_CCA _SFR_MEM16(0x0828) -#define TCC0_CCB _SFR_MEM16(0x082A) -#define TCC0_CCC _SFR_MEM16(0x082C) -#define TCC0_CCD _SFR_MEM16(0x082E) -#define TCC0_PERBUF _SFR_MEM16(0x0836) -#define TCC0_CCABUF _SFR_MEM16(0x0838) -#define TCC0_CCBBUF _SFR_MEM16(0x083A) -#define TCC0_CCCBUF _SFR_MEM16(0x083C) -#define TCC0_CCDBUF _SFR_MEM16(0x083E) - -/* TC2 - 16-bit Timer/Counter type 2 */ -#define TCC2_CTRLA _SFR_MEM8(0x0800) -#define TCC2_CTRLB _SFR_MEM8(0x0801) -#define TCC2_CTRLC _SFR_MEM8(0x0802) -#define TCC2_CTRLE _SFR_MEM8(0x0804) -#define TCC2_INTCTRLA _SFR_MEM8(0x0806) -#define TCC2_INTCTRLB _SFR_MEM8(0x0807) -#define TCC2_CTRLF _SFR_MEM8(0x0809) -#define TCC2_INTFLAGS _SFR_MEM8(0x080C) -#define TCC2_LCNT _SFR_MEM8(0x0820) -#define TCC2_HCNT _SFR_MEM8(0x0821) -#define TCC2_LPER _SFR_MEM8(0x0826) -#define TCC2_HPER _SFR_MEM8(0x0827) -#define TCC2_LCMPA _SFR_MEM8(0x0828) -#define TCC2_HCMPA _SFR_MEM8(0x0829) -#define TCC2_LCMPB _SFR_MEM8(0x082A) -#define TCC2_HCMPB _SFR_MEM8(0x082B) -#define TCC2_LCMPC _SFR_MEM8(0x082C) -#define TCC2_HCMPC _SFR_MEM8(0x082D) -#define TCC2_LCMPD _SFR_MEM8(0x082E) -#define TCC2_HCMPD _SFR_MEM8(0x082F) - -/* TC1 - 16-bit Timer/Counter 1 */ -#define TCC1_CTRLA _SFR_MEM8(0x0840) -#define TCC1_CTRLB _SFR_MEM8(0x0841) -#define TCC1_CTRLC _SFR_MEM8(0x0842) -#define TCC1_CTRLD _SFR_MEM8(0x0843) -#define TCC1_CTRLE _SFR_MEM8(0x0844) -#define TCC1_INTCTRLA _SFR_MEM8(0x0846) -#define TCC1_INTCTRLB _SFR_MEM8(0x0847) -#define TCC1_CTRLFCLR _SFR_MEM8(0x0848) -#define TCC1_CTRLFSET _SFR_MEM8(0x0849) -#define TCC1_CTRLGCLR _SFR_MEM8(0x084A) -#define TCC1_CTRLGSET _SFR_MEM8(0x084B) -#define TCC1_INTFLAGS _SFR_MEM8(0x084C) -#define TCC1_TEMP _SFR_MEM8(0x084F) -#define TCC1_CNT _SFR_MEM16(0x0860) -#define TCC1_PER _SFR_MEM16(0x0866) -#define TCC1_CCA _SFR_MEM16(0x0868) -#define TCC1_CCB _SFR_MEM16(0x086A) -#define TCC1_PERBUF _SFR_MEM16(0x0876) -#define TCC1_CCABUF _SFR_MEM16(0x0878) -#define TCC1_CCBBUF _SFR_MEM16(0x087A) - -/* AWEX - Advanced Waveform Extension */ -#define AWEXC_CTRL _SFR_MEM8(0x0880) -#define AWEXC_FDEMASK _SFR_MEM8(0x0882) -#define AWEXC_FDCTRL _SFR_MEM8(0x0883) -#define AWEXC_STATUS _SFR_MEM8(0x0884) -#define AWEXC_STATUSSET _SFR_MEM8(0x0885) -#define AWEXC_DTBOTH _SFR_MEM8(0x0886) -#define AWEXC_DTBOTHBUF _SFR_MEM8(0x0887) -#define AWEXC_DTLS _SFR_MEM8(0x0888) -#define AWEXC_DTHS _SFR_MEM8(0x0889) -#define AWEXC_DTLSBUF _SFR_MEM8(0x088A) -#define AWEXC_DTHSBUF _SFR_MEM8(0x088B) -#define AWEXC_OUTOVEN _SFR_MEM8(0x088C) - -/* HIRES - High-Resolution Extension */ -#define HIRESC_CTRLA _SFR_MEM8(0x0890) - -/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ -#define USARTC0_DATA _SFR_MEM8(0x08A0) -#define USARTC0_STATUS _SFR_MEM8(0x08A1) -#define USARTC0_CTRLA _SFR_MEM8(0x08A3) -#define USARTC0_CTRLB _SFR_MEM8(0x08A4) -#define USARTC0_CTRLC _SFR_MEM8(0x08A5) -#define USARTC0_BAUDCTRLA _SFR_MEM8(0x08A6) -#define USARTC0_BAUDCTRLB _SFR_MEM8(0x08A7) - -/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ -#define USARTC1_DATA _SFR_MEM8(0x08B0) -#define USARTC1_STATUS _SFR_MEM8(0x08B1) -#define USARTC1_CTRLA _SFR_MEM8(0x08B3) -#define USARTC1_CTRLB _SFR_MEM8(0x08B4) -#define USARTC1_CTRLC _SFR_MEM8(0x08B5) -#define USARTC1_BAUDCTRLA _SFR_MEM8(0x08B6) -#define USARTC1_BAUDCTRLB _SFR_MEM8(0x08B7) - -/* SPI - Serial Peripheral Interface */ -#define SPIC_CTRL _SFR_MEM8(0x08C0) -#define SPIC_INTCTRL _SFR_MEM8(0x08C1) -#define SPIC_STATUS _SFR_MEM8(0x08C2) -#define SPIC_DATA _SFR_MEM8(0x08C3) - -/* IRCOM - IR Communication Module */ -#define IRCOM_CTRL _SFR_MEM8(0x08F8) -#define IRCOM_TXPLCTRL _SFR_MEM8(0x08F9) -#define IRCOM_RXPLCTRL _SFR_MEM8(0x08FA) - -/* TC0 - 16-bit Timer/Counter 0 */ -#define TCD0_CTRLA _SFR_MEM8(0x0900) -#define TCD0_CTRLB _SFR_MEM8(0x0901) -#define TCD0_CTRLC _SFR_MEM8(0x0902) -#define TCD0_CTRLD _SFR_MEM8(0x0903) -#define TCD0_CTRLE _SFR_MEM8(0x0904) -#define TCD0_INTCTRLA _SFR_MEM8(0x0906) -#define TCD0_INTCTRLB _SFR_MEM8(0x0907) -#define TCD0_CTRLFCLR _SFR_MEM8(0x0908) -#define TCD0_CTRLFSET _SFR_MEM8(0x0909) -#define TCD0_CTRLGCLR _SFR_MEM8(0x090A) -#define TCD0_CTRLGSET _SFR_MEM8(0x090B) -#define TCD0_INTFLAGS _SFR_MEM8(0x090C) -#define TCD0_TEMP _SFR_MEM8(0x090F) -#define TCD0_CNT _SFR_MEM16(0x0920) -#define TCD0_PER _SFR_MEM16(0x0926) -#define TCD0_CCA _SFR_MEM16(0x0928) -#define TCD0_CCB _SFR_MEM16(0x092A) -#define TCD0_CCC _SFR_MEM16(0x092C) -#define TCD0_CCD _SFR_MEM16(0x092E) -#define TCD0_PERBUF _SFR_MEM16(0x0936) -#define TCD0_CCABUF _SFR_MEM16(0x0938) -#define TCD0_CCBBUF _SFR_MEM16(0x093A) -#define TCD0_CCCBUF _SFR_MEM16(0x093C) -#define TCD0_CCDBUF _SFR_MEM16(0x093E) - -/* TC2 - 16-bit Timer/Counter type 2 */ -#define TCD2_CTRLA _SFR_MEM8(0x0900) -#define TCD2_CTRLB _SFR_MEM8(0x0901) -#define TCD2_CTRLC _SFR_MEM8(0x0902) -#define TCD2_CTRLE _SFR_MEM8(0x0904) -#define TCD2_INTCTRLA _SFR_MEM8(0x0906) -#define TCD2_INTCTRLB _SFR_MEM8(0x0907) -#define TCD2_CTRLF _SFR_MEM8(0x0909) -#define TCD2_INTFLAGS _SFR_MEM8(0x090C) -#define TCD2_LCNT _SFR_MEM8(0x0920) -#define TCD2_HCNT _SFR_MEM8(0x0921) -#define TCD2_LPER _SFR_MEM8(0x0926) -#define TCD2_HPER _SFR_MEM8(0x0927) -#define TCD2_LCMPA _SFR_MEM8(0x0928) -#define TCD2_HCMPA _SFR_MEM8(0x0929) -#define TCD2_LCMPB _SFR_MEM8(0x092A) -#define TCD2_HCMPB _SFR_MEM8(0x092B) -#define TCD2_LCMPC _SFR_MEM8(0x092C) -#define TCD2_HCMPC _SFR_MEM8(0x092D) -#define TCD2_LCMPD _SFR_MEM8(0x092E) -#define TCD2_HCMPD _SFR_MEM8(0x092F) - -/* TC1 - 16-bit Timer/Counter 1 */ -#define TCD1_CTRLA _SFR_MEM8(0x0940) -#define TCD1_CTRLB _SFR_MEM8(0x0941) -#define TCD1_CTRLC _SFR_MEM8(0x0942) -#define TCD1_CTRLD _SFR_MEM8(0x0943) -#define TCD1_CTRLE _SFR_MEM8(0x0944) -#define TCD1_INTCTRLA _SFR_MEM8(0x0946) -#define TCD1_INTCTRLB _SFR_MEM8(0x0947) -#define TCD1_CTRLFCLR _SFR_MEM8(0x0948) -#define TCD1_CTRLFSET _SFR_MEM8(0x0949) -#define TCD1_CTRLGCLR _SFR_MEM8(0x094A) -#define TCD1_CTRLGSET _SFR_MEM8(0x094B) -#define TCD1_INTFLAGS _SFR_MEM8(0x094C) -#define TCD1_TEMP _SFR_MEM8(0x094F) -#define TCD1_CNT _SFR_MEM16(0x0960) -#define TCD1_PER _SFR_MEM16(0x0966) -#define TCD1_CCA _SFR_MEM16(0x0968) -#define TCD1_CCB _SFR_MEM16(0x096A) -#define TCD1_PERBUF _SFR_MEM16(0x0976) -#define TCD1_CCABUF _SFR_MEM16(0x0978) -#define TCD1_CCBBUF _SFR_MEM16(0x097A) - -/* HIRES - High-Resolution Extension */ -#define HIRESD_CTRLA _SFR_MEM8(0x0990) - -/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ -#define USARTD0_DATA _SFR_MEM8(0x09A0) -#define USARTD0_STATUS _SFR_MEM8(0x09A1) -#define USARTD0_CTRLA _SFR_MEM8(0x09A3) -#define USARTD0_CTRLB _SFR_MEM8(0x09A4) -#define USARTD0_CTRLC _SFR_MEM8(0x09A5) -#define USARTD0_BAUDCTRLA _SFR_MEM8(0x09A6) -#define USARTD0_BAUDCTRLB _SFR_MEM8(0x09A7) - -/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ -#define USARTD1_DATA _SFR_MEM8(0x09B0) -#define USARTD1_STATUS _SFR_MEM8(0x09B1) -#define USARTD1_CTRLA _SFR_MEM8(0x09B3) -#define USARTD1_CTRLB _SFR_MEM8(0x09B4) -#define USARTD1_CTRLC _SFR_MEM8(0x09B5) -#define USARTD1_BAUDCTRLA _SFR_MEM8(0x09B6) -#define USARTD1_BAUDCTRLB _SFR_MEM8(0x09B7) - -/* SPI - Serial Peripheral Interface */ -#define SPID_CTRL _SFR_MEM8(0x09C0) -#define SPID_INTCTRL _SFR_MEM8(0x09C1) -#define SPID_STATUS _SFR_MEM8(0x09C2) -#define SPID_DATA _SFR_MEM8(0x09C3) - -/* TC0 - 16-bit Timer/Counter 0 */ -#define TCE0_CTRLA _SFR_MEM8(0x0A00) -#define TCE0_CTRLB _SFR_MEM8(0x0A01) -#define TCE0_CTRLC _SFR_MEM8(0x0A02) -#define TCE0_CTRLD _SFR_MEM8(0x0A03) -#define TCE0_CTRLE _SFR_MEM8(0x0A04) -#define TCE0_INTCTRLA _SFR_MEM8(0x0A06) -#define TCE0_INTCTRLB _SFR_MEM8(0x0A07) -#define TCE0_CTRLFCLR _SFR_MEM8(0x0A08) -#define TCE0_CTRLFSET _SFR_MEM8(0x0A09) -#define TCE0_CTRLGCLR _SFR_MEM8(0x0A0A) -#define TCE0_CTRLGSET _SFR_MEM8(0x0A0B) -#define TCE0_INTFLAGS _SFR_MEM8(0x0A0C) -#define TCE0_TEMP _SFR_MEM8(0x0A0F) -#define TCE0_CNT _SFR_MEM16(0x0A20) -#define TCE0_PER _SFR_MEM16(0x0A26) -#define TCE0_CCA _SFR_MEM16(0x0A28) -#define TCE0_CCB _SFR_MEM16(0x0A2A) -#define TCE0_CCC _SFR_MEM16(0x0A2C) -#define TCE0_CCD _SFR_MEM16(0x0A2E) -#define TCE0_PERBUF _SFR_MEM16(0x0A36) -#define TCE0_CCABUF _SFR_MEM16(0x0A38) -#define TCE0_CCBBUF _SFR_MEM16(0x0A3A) -#define TCE0_CCCBUF _SFR_MEM16(0x0A3C) -#define TCE0_CCDBUF _SFR_MEM16(0x0A3E) - -/* TC2 - 16-bit Timer/Counter type 2 */ -#define TCE2_CTRLA _SFR_MEM8(0x0A00) -#define TCE2_CTRLB _SFR_MEM8(0x0A01) -#define TCE2_CTRLC _SFR_MEM8(0x0A02) -#define TCE2_CTRLE _SFR_MEM8(0x0A04) -#define TCE2_INTCTRLA _SFR_MEM8(0x0A06) -#define TCE2_INTCTRLB _SFR_MEM8(0x0A07) -#define TCE2_CTRLF _SFR_MEM8(0x0A09) -#define TCE2_INTFLAGS _SFR_MEM8(0x0A0C) -#define TCE2_LCNT _SFR_MEM8(0x0A20) -#define TCE2_HCNT _SFR_MEM8(0x0A21) -#define TCE2_LPER _SFR_MEM8(0x0A26) -#define TCE2_HPER _SFR_MEM8(0x0A27) -#define TCE2_LCMPA _SFR_MEM8(0x0A28) -#define TCE2_HCMPA _SFR_MEM8(0x0A29) -#define TCE2_LCMPB _SFR_MEM8(0x0A2A) -#define TCE2_HCMPB _SFR_MEM8(0x0A2B) -#define TCE2_LCMPC _SFR_MEM8(0x0A2C) -#define TCE2_HCMPC _SFR_MEM8(0x0A2D) -#define TCE2_LCMPD _SFR_MEM8(0x0A2E) -#define TCE2_HCMPD _SFR_MEM8(0x0A2F) - -/* TC1 - 16-bit Timer/Counter 1 */ -#define TCE1_CTRLA _SFR_MEM8(0x0A40) -#define TCE1_CTRLB _SFR_MEM8(0x0A41) -#define TCE1_CTRLC _SFR_MEM8(0x0A42) -#define TCE1_CTRLD _SFR_MEM8(0x0A43) -#define TCE1_CTRLE _SFR_MEM8(0x0A44) -#define TCE1_INTCTRLA _SFR_MEM8(0x0A46) -#define TCE1_INTCTRLB _SFR_MEM8(0x0A47) -#define TCE1_CTRLFCLR _SFR_MEM8(0x0A48) -#define TCE1_CTRLFSET _SFR_MEM8(0x0A49) -#define TCE1_CTRLGCLR _SFR_MEM8(0x0A4A) -#define TCE1_CTRLGSET _SFR_MEM8(0x0A4B) -#define TCE1_INTFLAGS _SFR_MEM8(0x0A4C) -#define TCE1_TEMP _SFR_MEM8(0x0A4F) -#define TCE1_CNT _SFR_MEM16(0x0A60) -#define TCE1_PER _SFR_MEM16(0x0A66) -#define TCE1_CCA _SFR_MEM16(0x0A68) -#define TCE1_CCB _SFR_MEM16(0x0A6A) -#define TCE1_PERBUF _SFR_MEM16(0x0A76) -#define TCE1_CCABUF _SFR_MEM16(0x0A78) -#define TCE1_CCBBUF _SFR_MEM16(0x0A7A) - -/* AWEX - Advanced Waveform Extension */ -#define AWEXE_CTRL _SFR_MEM8(0x0A80) -#define AWEXE_FDEMASK _SFR_MEM8(0x0A82) -#define AWEXE_FDCTRL _SFR_MEM8(0x0A83) -#define AWEXE_STATUS _SFR_MEM8(0x0A84) -#define AWEXE_STATUSSET _SFR_MEM8(0x0A85) -#define AWEXE_DTBOTH _SFR_MEM8(0x0A86) -#define AWEXE_DTBOTHBUF _SFR_MEM8(0x0A87) -#define AWEXE_DTLS _SFR_MEM8(0x0A88) -#define AWEXE_DTHS _SFR_MEM8(0x0A89) -#define AWEXE_DTLSBUF _SFR_MEM8(0x0A8A) -#define AWEXE_DTHSBUF _SFR_MEM8(0x0A8B) -#define AWEXE_OUTOVEN _SFR_MEM8(0x0A8C) - -/* HIRES - High-Resolution Extension */ -#define HIRESE_CTRLA _SFR_MEM8(0x0A90) - -/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ -#define USARTE0_DATA _SFR_MEM8(0x0AA0) -#define USARTE0_STATUS _SFR_MEM8(0x0AA1) -#define USARTE0_CTRLA _SFR_MEM8(0x0AA3) -#define USARTE0_CTRLB _SFR_MEM8(0x0AA4) -#define USARTE0_CTRLC _SFR_MEM8(0x0AA5) -#define USARTE0_BAUDCTRLA _SFR_MEM8(0x0AA6) -#define USARTE0_BAUDCTRLB _SFR_MEM8(0x0AA7) - -/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ -#define USARTE1_DATA _SFR_MEM8(0x0AB0) -#define USARTE1_STATUS _SFR_MEM8(0x0AB1) -#define USARTE1_CTRLA _SFR_MEM8(0x0AB3) -#define USARTE1_CTRLB _SFR_MEM8(0x0AB4) -#define USARTE1_CTRLC _SFR_MEM8(0x0AB5) -#define USARTE1_BAUDCTRLA _SFR_MEM8(0x0AB6) -#define USARTE1_BAUDCTRLB _SFR_MEM8(0x0AB7) - -/* SPI - Serial Peripheral Interface */ -#define SPIE_CTRL _SFR_MEM8(0x0AC0) -#define SPIE_INTCTRL _SFR_MEM8(0x0AC1) -#define SPIE_STATUS _SFR_MEM8(0x0AC2) -#define SPIE_DATA _SFR_MEM8(0x0AC3) - -/* TC0 - 16-bit Timer/Counter 0 */ -#define TCF0_CTRLA _SFR_MEM8(0x0B00) -#define TCF0_CTRLB _SFR_MEM8(0x0B01) -#define TCF0_CTRLC _SFR_MEM8(0x0B02) -#define TCF0_CTRLD _SFR_MEM8(0x0B03) -#define TCF0_CTRLE _SFR_MEM8(0x0B04) -#define TCF0_INTCTRLA _SFR_MEM8(0x0B06) -#define TCF0_INTCTRLB _SFR_MEM8(0x0B07) -#define TCF0_CTRLFCLR _SFR_MEM8(0x0B08) -#define TCF0_CTRLFSET _SFR_MEM8(0x0B09) -#define TCF0_CTRLGCLR _SFR_MEM8(0x0B0A) -#define TCF0_CTRLGSET _SFR_MEM8(0x0B0B) -#define TCF0_INTFLAGS _SFR_MEM8(0x0B0C) -#define TCF0_TEMP _SFR_MEM8(0x0B0F) -#define TCF0_CNT _SFR_MEM16(0x0B20) -#define TCF0_PER _SFR_MEM16(0x0B26) -#define TCF0_CCA _SFR_MEM16(0x0B28) -#define TCF0_CCB _SFR_MEM16(0x0B2A) -#define TCF0_CCC _SFR_MEM16(0x0B2C) -#define TCF0_CCD _SFR_MEM16(0x0B2E) -#define TCF0_PERBUF _SFR_MEM16(0x0B36) -#define TCF0_CCABUF _SFR_MEM16(0x0B38) -#define TCF0_CCBBUF _SFR_MEM16(0x0B3A) -#define TCF0_CCCBUF _SFR_MEM16(0x0B3C) -#define TCF0_CCDBUF _SFR_MEM16(0x0B3E) - -/* TC2 - 16-bit Timer/Counter type 2 */ -#define TCF2_CTRLA _SFR_MEM8(0x0B00) -#define TCF2_CTRLB _SFR_MEM8(0x0B01) -#define TCF2_CTRLC _SFR_MEM8(0x0B02) -#define TCF2_CTRLE _SFR_MEM8(0x0B04) -#define TCF2_INTCTRLA _SFR_MEM8(0x0B06) -#define TCF2_INTCTRLB _SFR_MEM8(0x0B07) -#define TCF2_CTRLF _SFR_MEM8(0x0B09) -#define TCF2_INTFLAGS _SFR_MEM8(0x0B0C) -#define TCF2_LCNT _SFR_MEM8(0x0B20) -#define TCF2_HCNT _SFR_MEM8(0x0B21) -#define TCF2_LPER _SFR_MEM8(0x0B26) -#define TCF2_HPER _SFR_MEM8(0x0B27) -#define TCF2_LCMPA _SFR_MEM8(0x0B28) -#define TCF2_HCMPA _SFR_MEM8(0x0B29) -#define TCF2_LCMPB _SFR_MEM8(0x0B2A) -#define TCF2_HCMPB _SFR_MEM8(0x0B2B) -#define TCF2_LCMPC _SFR_MEM8(0x0B2C) -#define TCF2_HCMPC _SFR_MEM8(0x0B2D) -#define TCF2_LCMPD _SFR_MEM8(0x0B2E) -#define TCF2_HCMPD _SFR_MEM8(0x0B2F) - -/* TC1 - 16-bit Timer/Counter 1 */ -#define TCF1_CTRLA _SFR_MEM8(0x0B40) -#define TCF1_CTRLB _SFR_MEM8(0x0B41) -#define TCF1_CTRLC _SFR_MEM8(0x0B42) -#define TCF1_CTRLD _SFR_MEM8(0x0B43) -#define TCF1_CTRLE _SFR_MEM8(0x0B44) -#define TCF1_INTCTRLA _SFR_MEM8(0x0B46) -#define TCF1_INTCTRLB _SFR_MEM8(0x0B47) -#define TCF1_CTRLFCLR _SFR_MEM8(0x0B48) -#define TCF1_CTRLFSET _SFR_MEM8(0x0B49) -#define TCF1_CTRLGCLR _SFR_MEM8(0x0B4A) -#define TCF1_CTRLGSET _SFR_MEM8(0x0B4B) -#define TCF1_INTFLAGS _SFR_MEM8(0x0B4C) -#define TCF1_TEMP _SFR_MEM8(0x0B4F) -#define TCF1_CNT _SFR_MEM16(0x0B60) -#define TCF1_PER _SFR_MEM16(0x0B66) -#define TCF1_CCA _SFR_MEM16(0x0B68) -#define TCF1_CCB _SFR_MEM16(0x0B6A) -#define TCF1_PERBUF _SFR_MEM16(0x0B76) -#define TCF1_CCABUF _SFR_MEM16(0x0B78) -#define TCF1_CCBBUF _SFR_MEM16(0x0B7A) - -/* HIRES - High-Resolution Extension */ -#define HIRESF_CTRLA _SFR_MEM8(0x0B90) - -/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ -#define USARTF0_DATA _SFR_MEM8(0x0BA0) -#define USARTF0_STATUS _SFR_MEM8(0x0BA1) -#define USARTF0_CTRLA _SFR_MEM8(0x0BA3) -#define USARTF0_CTRLB _SFR_MEM8(0x0BA4) -#define USARTF0_CTRLC _SFR_MEM8(0x0BA5) -#define USARTF0_BAUDCTRLA _SFR_MEM8(0x0BA6) -#define USARTF0_BAUDCTRLB _SFR_MEM8(0x0BA7) - -/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ -#define USARTF1_DATA _SFR_MEM8(0x0BB0) -#define USARTF1_STATUS _SFR_MEM8(0x0BB1) -#define USARTF1_CTRLA _SFR_MEM8(0x0BB3) -#define USARTF1_CTRLB _SFR_MEM8(0x0BB4) -#define USARTF1_CTRLC _SFR_MEM8(0x0BB5) -#define USARTF1_BAUDCTRLA _SFR_MEM8(0x0BB6) -#define USARTF1_BAUDCTRLB _SFR_MEM8(0x0BB7) - -/* SPI - Serial Peripheral Interface */ -#define SPIF_CTRL _SFR_MEM8(0x0BC0) -#define SPIF_INTCTRL _SFR_MEM8(0x0BC1) -#define SPIF_STATUS _SFR_MEM8(0x0BC2) -#define SPIF_DATA _SFR_MEM8(0x0BC3) - - - -/*================== Bitfield Definitions ================== */ - -/* VPORT - Virtual Ports */ -/* VPORT.INTFLAGS bit masks and bit positions */ -#define VPORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ -#define VPORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ - -#define VPORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ -#define VPORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ - -/* XOCD - On-Chip Debug System */ -/* OCD.OCDR0 bit masks and bit positions */ -#define OCD_OCDRD_gm 0xFF /* OCDR Dirty group mask. */ -#define OCD_OCDRD_gp 0 /* OCDR Dirty group position. */ -#define OCD_OCDRD0_bm (1<<0) /* OCDR Dirty bit 0 mask. */ -#define OCD_OCDRD0_bp 0 /* OCDR Dirty bit 0 position. */ -#define OCD_OCDRD1_bm (1<<1) /* OCDR Dirty bit 1 mask. */ -#define OCD_OCDRD1_bp 1 /* OCDR Dirty bit 1 position. */ -#define OCD_OCDRD2_bm (1<<2) /* OCDR Dirty bit 2 mask. */ -#define OCD_OCDRD2_bp 2 /* OCDR Dirty bit 2 position. */ -#define OCD_OCDRD3_bm (1<<3) /* OCDR Dirty bit 3 mask. */ -#define OCD_OCDRD3_bp 3 /* OCDR Dirty bit 3 position. */ -#define OCD_OCDRD4_bm (1<<4) /* OCDR Dirty bit 4 mask. */ -#define OCD_OCDRD4_bp 4 /* OCDR Dirty bit 4 position. */ -#define OCD_OCDRD5_bm (1<<5) /* OCDR Dirty bit 5 mask. */ -#define OCD_OCDRD5_bp 5 /* OCDR Dirty bit 5 position. */ -#define OCD_OCDRD6_bm (1<<6) /* OCDR Dirty bit 6 mask. */ -#define OCD_OCDRD6_bp 6 /* OCDR Dirty bit 6 position. */ -#define OCD_OCDRD7_bm (1<<7) /* OCDR Dirty bit 7 mask. */ -#define OCD_OCDRD7_bp 7 /* OCDR Dirty bit 7 position. */ - -/* OCD.OCDR1 bit masks and bit positions */ -/* OCD_OCDRD Predefined. */ -/* OCD_OCDRD Predefined. */ - -/* CPU - CPU */ -/* CPU.CCP bit masks and bit positions */ -#define CPU_CCP_gm 0xFF /* CCP signature group mask. */ -#define CPU_CCP_gp 0 /* CCP signature group position. */ -#define CPU_CCP0_bm (1<<0) /* CCP signature bit 0 mask. */ -#define CPU_CCP0_bp 0 /* CCP signature bit 0 position. */ -#define CPU_CCP1_bm (1<<1) /* CCP signature bit 1 mask. */ -#define CPU_CCP1_bp 1 /* CCP signature bit 1 position. */ -#define CPU_CCP2_bm (1<<2) /* CCP signature bit 2 mask. */ -#define CPU_CCP2_bp 2 /* CCP signature bit 2 position. */ -#define CPU_CCP3_bm (1<<3) /* CCP signature bit 3 mask. */ -#define CPU_CCP3_bp 3 /* CCP signature bit 3 position. */ -#define CPU_CCP4_bm (1<<4) /* CCP signature bit 4 mask. */ -#define CPU_CCP4_bp 4 /* CCP signature bit 4 position. */ -#define CPU_CCP5_bm (1<<5) /* CCP signature bit 5 mask. */ -#define CPU_CCP5_bp 5 /* CCP signature bit 5 position. */ -#define CPU_CCP6_bm (1<<6) /* CCP signature bit 6 mask. */ -#define CPU_CCP6_bp 6 /* CCP signature bit 6 position. */ -#define CPU_CCP7_bm (1<<7) /* CCP signature bit 7 mask. */ -#define CPU_CCP7_bp 7 /* CCP signature bit 7 position. */ - -/* CPU.SREG bit masks and bit positions */ -#define CPU_I_bm 0x80 /* Global Interrupt Enable Flag bit mask. */ -#define CPU_I_bp 7 /* Global Interrupt Enable Flag bit position. */ - -#define CPU_T_bm 0x40 /* Transfer Bit bit mask. */ -#define CPU_T_bp 6 /* Transfer Bit bit position. */ - -#define CPU_H_bm 0x20 /* Half Carry Flag bit mask. */ -#define CPU_H_bp 5 /* Half Carry Flag bit position. */ - -#define CPU_S_bm 0x10 /* N Exclusive Or V Flag bit mask. */ -#define CPU_S_bp 4 /* N Exclusive Or V Flag bit position. */ - -#define CPU_V_bm 0x08 /* Two's Complement Overflow Flag bit mask. */ -#define CPU_V_bp 3 /* Two's Complement Overflow Flag bit position. */ - -#define CPU_N_bm 0x04 /* Negative Flag bit mask. */ -#define CPU_N_bp 2 /* Negative Flag bit position. */ - -#define CPU_Z_bm 0x02 /* Zero Flag bit mask. */ -#define CPU_Z_bp 1 /* Zero Flag bit position. */ - -#define CPU_C_bm 0x01 /* Carry Flag bit mask. */ -#define CPU_C_bp 0 /* Carry Flag bit position. */ - -/* CLK - Clock System */ -/* CLK.CTRL bit masks and bit positions */ -#define CLK_SCLKSEL_gm 0x07 /* System Clock Selection group mask. */ -#define CLK_SCLKSEL_gp 0 /* System Clock Selection group position. */ -#define CLK_SCLKSEL0_bm (1<<0) /* System Clock Selection bit 0 mask. */ -#define CLK_SCLKSEL0_bp 0 /* System Clock Selection bit 0 position. */ -#define CLK_SCLKSEL1_bm (1<<1) /* System Clock Selection bit 1 mask. */ -#define CLK_SCLKSEL1_bp 1 /* System Clock Selection bit 1 position. */ -#define CLK_SCLKSEL2_bm (1<<2) /* System Clock Selection bit 2 mask. */ -#define CLK_SCLKSEL2_bp 2 /* System Clock Selection bit 2 position. */ - -/* CLK.PSCTRL bit masks and bit positions */ -#define CLK_PSADIV_gm 0x7C /* Prescaler A Division Factor group mask. */ -#define CLK_PSADIV_gp 2 /* Prescaler A Division Factor group position. */ -#define CLK_PSADIV0_bm (1<<2) /* Prescaler A Division Factor bit 0 mask. */ -#define CLK_PSADIV0_bp 2 /* Prescaler A Division Factor bit 0 position. */ -#define CLK_PSADIV1_bm (1<<3) /* Prescaler A Division Factor bit 1 mask. */ -#define CLK_PSADIV1_bp 3 /* Prescaler A Division Factor bit 1 position. */ -#define CLK_PSADIV2_bm (1<<4) /* Prescaler A Division Factor bit 2 mask. */ -#define CLK_PSADIV2_bp 4 /* Prescaler A Division Factor bit 2 position. */ -#define CLK_PSADIV3_bm (1<<5) /* Prescaler A Division Factor bit 3 mask. */ -#define CLK_PSADIV3_bp 5 /* Prescaler A Division Factor bit 3 position. */ -#define CLK_PSADIV4_bm (1<<6) /* Prescaler A Division Factor bit 4 mask. */ -#define CLK_PSADIV4_bp 6 /* Prescaler A Division Factor bit 4 position. */ - -#define CLK_PSBCDIV_gm 0x03 /* Prescaler B and C Division factor group mask. */ -#define CLK_PSBCDIV_gp 0 /* Prescaler B and C Division factor group position. */ -#define CLK_PSBCDIV0_bm (1<<0) /* Prescaler B and C Division factor bit 0 mask. */ -#define CLK_PSBCDIV0_bp 0 /* Prescaler B and C Division factor bit 0 position. */ -#define CLK_PSBCDIV1_bm (1<<1) /* Prescaler B and C Division factor bit 1 mask. */ -#define CLK_PSBCDIV1_bp 1 /* Prescaler B and C Division factor bit 1 position. */ - -/* CLK.LOCK bit masks and bit positions */ -#define CLK_LOCK_bm 0x01 /* Clock System Lock bit mask. */ -#define CLK_LOCK_bp 0 /* Clock System Lock bit position. */ - -/* CLK.RTCCTRL bit masks and bit positions */ -#define CLK_RTCSRC_gm 0x0E /* Clock Source group mask. */ -#define CLK_RTCSRC_gp 1 /* Clock Source group position. */ -#define CLK_RTCSRC0_bm (1<<1) /* Clock Source bit 0 mask. */ -#define CLK_RTCSRC0_bp 1 /* Clock Source bit 0 position. */ -#define CLK_RTCSRC1_bm (1<<2) /* Clock Source bit 1 mask. */ -#define CLK_RTCSRC1_bp 2 /* Clock Source bit 1 position. */ -#define CLK_RTCSRC2_bm (1<<3) /* Clock Source bit 2 mask. */ -#define CLK_RTCSRC2_bp 3 /* Clock Source bit 2 position. */ - -#define CLK_RTCEN_bm 0x01 /* Clock Source Enable bit mask. */ -#define CLK_RTCEN_bp 0 /* Clock Source Enable bit position. */ - -/* CLK.USBCTRL bit masks and bit positions */ -#define CLK_USBPSDIV_gm 0x38 /* Prescaler Division Factor group mask. */ -#define CLK_USBPSDIV_gp 3 /* Prescaler Division Factor group position. */ -#define CLK_USBPSDIV0_bm (1<<3) /* Prescaler Division Factor bit 0 mask. */ -#define CLK_USBPSDIV0_bp 3 /* Prescaler Division Factor bit 0 position. */ -#define CLK_USBPSDIV1_bm (1<<4) /* Prescaler Division Factor bit 1 mask. */ -#define CLK_USBPSDIV1_bp 4 /* Prescaler Division Factor bit 1 position. */ -#define CLK_USBPSDIV2_bm (1<<5) /* Prescaler Division Factor bit 2 mask. */ -#define CLK_USBPSDIV2_bp 5 /* Prescaler Division Factor bit 2 position. */ - -#define CLK_USBSRC_gm 0x06 /* Clock Source group mask. */ -#define CLK_USBSRC_gp 1 /* Clock Source group position. */ -#define CLK_USBSRC0_bm (1<<1) /* Clock Source bit 0 mask. */ -#define CLK_USBSRC0_bp 1 /* Clock Source bit 0 position. */ -#define CLK_USBSRC1_bm (1<<2) /* Clock Source bit 1 mask. */ -#define CLK_USBSRC1_bp 2 /* Clock Source bit 1 position. */ - -#define CLK_USBSEN_bm 0x01 /* Clock Source Enable bit mask. */ -#define CLK_USBSEN_bp 0 /* Clock Source Enable bit position. */ - -/* PR.PRGEN bit masks and bit positions */ -#define PR_USB_bm 0x40 /* USB bit mask. */ -#define PR_USB_bp 6 /* USB bit position. */ - -#define PR_AES_bm 0x10 /* AES bit mask. */ -#define PR_AES_bp 4 /* AES bit position. */ - -#define PR_EBI_bm 0x08 /* External Bus Interface bit mask. */ -#define PR_EBI_bp 3 /* External Bus Interface bit position. */ - -#define PR_RTC_bm 0x04 /* Real-time Counter bit mask. */ -#define PR_RTC_bp 2 /* Real-time Counter bit position. */ - -#define PR_EVSYS_bm 0x02 /* Event System bit mask. */ -#define PR_EVSYS_bp 1 /* Event System bit position. */ - -#define PR_DMA_bm 0x01 /* DMA-Controller bit mask. */ -#define PR_DMA_bp 0 /* DMA-Controller bit position. */ - -/* PR.PRPA bit masks and bit positions */ -#define PR_DAC_bm 0x04 /* Port A DAC bit mask. */ -#define PR_DAC_bp 2 /* Port A DAC bit position. */ - -#define PR_ADC_bm 0x02 /* Port A ADC bit mask. */ -#define PR_ADC_bp 1 /* Port A ADC bit position. */ - -#define PR_AC_bm 0x01 /* Port A Analog Comparator bit mask. */ -#define PR_AC_bp 0 /* Port A Analog Comparator bit position. */ - -/* PR.PRPB bit masks and bit positions */ -/* PR_DAC Predefined. */ -/* PR_DAC Predefined. */ - -/* PR_ADC Predefined. */ -/* PR_ADC Predefined. */ - -/* PR_AC Predefined. */ -/* PR_AC Predefined. */ - -/* PR.PRPC bit masks and bit positions */ -#define PR_TWI_bm 0x40 /* Port C Two-wire Interface bit mask. */ -#define PR_TWI_bp 6 /* Port C Two-wire Interface bit position. */ - -#define PR_USART1_bm 0x20 /* Port C USART1 bit mask. */ -#define PR_USART1_bp 5 /* Port C USART1 bit position. */ - -#define PR_USART0_bm 0x10 /* Port C USART0 bit mask. */ -#define PR_USART0_bp 4 /* Port C USART0 bit position. */ - -#define PR_SPI_bm 0x08 /* Port C SPI bit mask. */ -#define PR_SPI_bp 3 /* Port C SPI bit position. */ - -#define PR_HIRES_bm 0x04 /* Port C AWEX bit mask. */ -#define PR_HIRES_bp 2 /* Port C AWEX bit position. */ - -#define PR_TC1_bm 0x02 /* Port C Timer/Counter1 bit mask. */ -#define PR_TC1_bp 1 /* Port C Timer/Counter1 bit position. */ - -#define PR_TC0_bm 0x01 /* Port C Timer/Counter0 bit mask. */ -#define PR_TC0_bp 0 /* Port C Timer/Counter0 bit position. */ - -/* PR.PRPD bit masks and bit positions */ -/* PR_TWI Predefined. */ -/* PR_TWI Predefined. */ - -/* PR_USART1 Predefined. */ -/* PR_USART1 Predefined. */ - -/* PR_USART0 Predefined. */ -/* PR_USART0 Predefined. */ - -/* PR_SPI Predefined. */ -/* PR_SPI Predefined. */ - -/* PR_HIRES Predefined. */ -/* PR_HIRES Predefined. */ - -/* PR_TC1 Predefined. */ -/* PR_TC1 Predefined. */ - -/* PR_TC0 Predefined. */ -/* PR_TC0 Predefined. */ - -/* PR.PRPE bit masks and bit positions */ -/* PR_TWI Predefined. */ -/* PR_TWI Predefined. */ - -/* PR_USART1 Predefined. */ -/* PR_USART1 Predefined. */ - -/* PR_USART0 Predefined. */ -/* PR_USART0 Predefined. */ - -/* PR_SPI Predefined. */ -/* PR_SPI Predefined. */ - -/* PR_HIRES Predefined. */ -/* PR_HIRES Predefined. */ - -/* PR_TC1 Predefined. */ -/* PR_TC1 Predefined. */ - -/* PR_TC0 Predefined. */ -/* PR_TC0 Predefined. */ - -/* PR.PRPF bit masks and bit positions */ -/* PR_TWI Predefined. */ -/* PR_TWI Predefined. */ - -/* PR_USART1 Predefined. */ -/* PR_USART1 Predefined. */ - -/* PR_USART0 Predefined. */ -/* PR_USART0 Predefined. */ - -/* PR_SPI Predefined. */ -/* PR_SPI Predefined. */ - -/* PR_HIRES Predefined. */ -/* PR_HIRES Predefined. */ - -/* PR_TC1 Predefined. */ -/* PR_TC1 Predefined. */ - -/* PR_TC0 Predefined. */ -/* PR_TC0 Predefined. */ - -/* SLEEP - Sleep Controller */ -/* SLEEP.CTRL bit masks and bit positions */ -#define SLEEP_SMODE_gm 0x0E /* Sleep Mode group mask. */ -#define SLEEP_SMODE_gp 1 /* Sleep Mode group position. */ -#define SLEEP_SMODE0_bm (1<<1) /* Sleep Mode bit 0 mask. */ -#define SLEEP_SMODE0_bp 1 /* Sleep Mode bit 0 position. */ -#define SLEEP_SMODE1_bm (1<<2) /* Sleep Mode bit 1 mask. */ -#define SLEEP_SMODE1_bp 2 /* Sleep Mode bit 1 position. */ -#define SLEEP_SMODE2_bm (1<<3) /* Sleep Mode bit 2 mask. */ -#define SLEEP_SMODE2_bp 3 /* Sleep Mode bit 2 position. */ - -#define SLEEP_SEN_bm 0x01 /* Sleep Enable bit mask. */ -#define SLEEP_SEN_bp 0 /* Sleep Enable bit position. */ - -/* OSC - Oscillator */ -/* OSC.CTRL bit masks and bit positions */ -#define OSC_PLLEN_bm 0x10 /* PLL Enable bit mask. */ -#define OSC_PLLEN_bp 4 /* PLL Enable bit position. */ - -#define OSC_XOSCEN_bm 0x08 /* External Oscillator Enable bit mask. */ -#define OSC_XOSCEN_bp 3 /* External Oscillator Enable bit position. */ - -#define OSC_RC32KEN_bm 0x04 /* Internal 32.768 kHz RC Oscillator Enable bit mask. */ -#define OSC_RC32KEN_bp 2 /* Internal 32.768 kHz RC Oscillator Enable bit position. */ - -#define OSC_RC32MEN_bm 0x02 /* Internal 32 MHz RC Oscillator Enable bit mask. */ -#define OSC_RC32MEN_bp 1 /* Internal 32 MHz RC Oscillator Enable bit position. */ - -#define OSC_RC2MEN_bm 0x01 /* Internal 2 MHz RC Oscillator Enable bit mask. */ -#define OSC_RC2MEN_bp 0 /* Internal 2 MHz RC Oscillator Enable bit position. */ - -/* OSC.STATUS bit masks and bit positions */ -#define OSC_PLLRDY_bm 0x10 /* PLL Ready bit mask. */ -#define OSC_PLLRDY_bp 4 /* PLL Ready bit position. */ - -#define OSC_XOSCRDY_bm 0x08 /* External Oscillator Ready bit mask. */ -#define OSC_XOSCRDY_bp 3 /* External Oscillator Ready bit position. */ - -#define OSC_RC32KRDY_bm 0x04 /* Internal 32.768 kHz RC Oscillator Ready bit mask. */ -#define OSC_RC32KRDY_bp 2 /* Internal 32.768 kHz RC Oscillator Ready bit position. */ - -#define OSC_RC32MRDY_bm 0x02 /* Internal 32 MHz RC Oscillator Ready bit mask. */ -#define OSC_RC32MRDY_bp 1 /* Internal 32 MHz RC Oscillator Ready bit position. */ - -#define OSC_RC2MRDY_bm 0x01 /* Internal 2 MHz RC Oscillator Ready bit mask. */ -#define OSC_RC2MRDY_bp 0 /* Internal 2 MHz RC Oscillator Ready bit position. */ - -/* OSC.XOSCCTRL bit masks and bit positions */ -#define OSC_FRQRANGE_gm 0xC0 /* Frequency Range group mask. */ -#define OSC_FRQRANGE_gp 6 /* Frequency Range group position. */ -#define OSC_FRQRANGE0_bm (1<<6) /* Frequency Range bit 0 mask. */ -#define OSC_FRQRANGE0_bp 6 /* Frequency Range bit 0 position. */ -#define OSC_FRQRANGE1_bm (1<<7) /* Frequency Range bit 1 mask. */ -#define OSC_FRQRANGE1_bp 7 /* Frequency Range bit 1 position. */ - -#define OSC_X32KLPM_bm 0x20 /* 32.768 kHz XTAL OSC Low-power Mode bit mask. */ -#define OSC_X32KLPM_bp 5 /* 32.768 kHz XTAL OSC Low-power Mode bit position. */ - -#define OSC_XOSCPWR_bm 0x10 /* 16 MHz Crystal Oscillator High Power mode bit mask. */ -#define OSC_XOSCPWR_bp 4 /* 16 MHz Crystal Oscillator High Power mode bit position. */ - -#define OSC_XOSCSEL_gm 0x0F /* External Oscillator Selection and Startup Time group mask. */ -#define OSC_XOSCSEL_gp 0 /* External Oscillator Selection and Startup Time group position. */ -#define OSC_XOSCSEL0_bm (1<<0) /* External Oscillator Selection and Startup Time bit 0 mask. */ -#define OSC_XOSCSEL0_bp 0 /* External Oscillator Selection and Startup Time bit 0 position. */ -#define OSC_XOSCSEL1_bm (1<<1) /* External Oscillator Selection and Startup Time bit 1 mask. */ -#define OSC_XOSCSEL1_bp 1 /* External Oscillator Selection and Startup Time bit 1 position. */ -#define OSC_XOSCSEL2_bm (1<<2) /* External Oscillator Selection and Startup Time bit 2 mask. */ -#define OSC_XOSCSEL2_bp 2 /* External Oscillator Selection and Startup Time bit 2 position. */ -#define OSC_XOSCSEL3_bm (1<<3) /* External Oscillator Selection and Startup Time bit 3 mask. */ -#define OSC_XOSCSEL3_bp 3 /* External Oscillator Selection and Startup Time bit 3 position. */ - -/* OSC.XOSCFAIL bit masks and bit positions */ -#define OSC_PLLFDIF_bm 0x08 /* PLL Failure Detection Interrupt Flag bit mask. */ -#define OSC_PLLFDIF_bp 3 /* PLL Failure Detection Interrupt Flag bit position. */ - -#define OSC_PLLFDEN_bm 0x04 /* PLL Failure Detection Enable bit mask. */ -#define OSC_PLLFDEN_bp 2 /* PLL Failure Detection Enable bit position. */ - -#define OSC_XOSCFDIF_bm 0x02 /* XOSC Failure Detection Interrupt Flag bit mask. */ -#define OSC_XOSCFDIF_bp 1 /* XOSC Failure Detection Interrupt Flag bit position. */ - -#define OSC_XOSCFDEN_bm 0x01 /* XOSC Failure Detection Enable bit mask. */ -#define OSC_XOSCFDEN_bp 0 /* XOSC Failure Detection Enable bit position. */ - -/* OSC.PLLCTRL bit masks and bit positions */ -#define OSC_PLLSRC_gm 0xC0 /* Clock Source group mask. */ -#define OSC_PLLSRC_gp 6 /* Clock Source group position. */ -#define OSC_PLLSRC0_bm (1<<6) /* Clock Source bit 0 mask. */ -#define OSC_PLLSRC0_bp 6 /* Clock Source bit 0 position. */ -#define OSC_PLLSRC1_bm (1<<7) /* Clock Source bit 1 mask. */ -#define OSC_PLLSRC1_bp 7 /* Clock Source bit 1 position. */ - -#define OSC_PLLDIV_bm 0x20 /* Divide by 2 bit mask. */ -#define OSC_PLLDIV_bp 5 /* Divide by 2 bit position. */ - -#define OSC_PLLFAC_gm 0x1F /* Multiplication Factor group mask. */ -#define OSC_PLLFAC_gp 0 /* Multiplication Factor group position. */ -#define OSC_PLLFAC0_bm (1<<0) /* Multiplication Factor bit 0 mask. */ -#define OSC_PLLFAC0_bp 0 /* Multiplication Factor bit 0 position. */ -#define OSC_PLLFAC1_bm (1<<1) /* Multiplication Factor bit 1 mask. */ -#define OSC_PLLFAC1_bp 1 /* Multiplication Factor bit 1 position. */ -#define OSC_PLLFAC2_bm (1<<2) /* Multiplication Factor bit 2 mask. */ -#define OSC_PLLFAC2_bp 2 /* Multiplication Factor bit 2 position. */ -#define OSC_PLLFAC3_bm (1<<3) /* Multiplication Factor bit 3 mask. */ -#define OSC_PLLFAC3_bp 3 /* Multiplication Factor bit 3 position. */ -#define OSC_PLLFAC4_bm (1<<4) /* Multiplication Factor bit 4 mask. */ -#define OSC_PLLFAC4_bp 4 /* Multiplication Factor bit 4 position. */ - -/* OSC.DFLLCTRL bit masks and bit positions */ -#define OSC_RC32MCREF_gm 0x06 /* 32 MHz DFLL Calibration Reference group mask. */ -#define OSC_RC32MCREF_gp 1 /* 32 MHz DFLL Calibration Reference group position. */ -#define OSC_RC32MCREF0_bm (1<<1) /* 32 MHz DFLL Calibration Reference bit 0 mask. */ -#define OSC_RC32MCREF0_bp 1 /* 32 MHz DFLL Calibration Reference bit 0 position. */ -#define OSC_RC32MCREF1_bm (1<<2) /* 32 MHz DFLL Calibration Reference bit 1 mask. */ -#define OSC_RC32MCREF1_bp 2 /* 32 MHz DFLL Calibration Reference bit 1 position. */ - -#define OSC_RC2MCREF_bm 0x01 /* 2 MHz DFLL Calibration Reference bit mask. */ -#define OSC_RC2MCREF_bp 0 /* 2 MHz DFLL Calibration Reference bit position. */ - -/* DFLL - DFLL */ -/* DFLL.CTRL bit masks and bit positions */ -#define DFLL_ENABLE_bm 0x01 /* DFLL Enable bit mask. */ -#define DFLL_ENABLE_bp 0 /* DFLL Enable bit position. */ - -/* DFLL.CALA bit masks and bit positions */ -#define DFLL_CALL_gm 0x7F /* DFLL Calibration Value A group mask. */ -#define DFLL_CALL_gp 0 /* DFLL Calibration Value A group position. */ -#define DFLL_CALL0_bm (1<<0) /* DFLL Calibration Value A bit 0 mask. */ -#define DFLL_CALL0_bp 0 /* DFLL Calibration Value A bit 0 position. */ -#define DFLL_CALL1_bm (1<<1) /* DFLL Calibration Value A bit 1 mask. */ -#define DFLL_CALL1_bp 1 /* DFLL Calibration Value A bit 1 position. */ -#define DFLL_CALL2_bm (1<<2) /* DFLL Calibration Value A bit 2 mask. */ -#define DFLL_CALL2_bp 2 /* DFLL Calibration Value A bit 2 position. */ -#define DFLL_CALL3_bm (1<<3) /* DFLL Calibration Value A bit 3 mask. */ -#define DFLL_CALL3_bp 3 /* DFLL Calibration Value A bit 3 position. */ -#define DFLL_CALL4_bm (1<<4) /* DFLL Calibration Value A bit 4 mask. */ -#define DFLL_CALL4_bp 4 /* DFLL Calibration Value A bit 4 position. */ -#define DFLL_CALL5_bm (1<<5) /* DFLL Calibration Value A bit 5 mask. */ -#define DFLL_CALL5_bp 5 /* DFLL Calibration Value A bit 5 position. */ -#define DFLL_CALL6_bm (1<<6) /* DFLL Calibration Value A bit 6 mask. */ -#define DFLL_CALL6_bp 6 /* DFLL Calibration Value A bit 6 position. */ - -/* DFLL.CALB bit masks and bit positions */ -#define DFLL_CALH_gm 0x3F /* DFLL Calibration Value B group mask. */ -#define DFLL_CALH_gp 0 /* DFLL Calibration Value B group position. */ -#define DFLL_CALH0_bm (1<<0) /* DFLL Calibration Value B bit 0 mask. */ -#define DFLL_CALH0_bp 0 /* DFLL Calibration Value B bit 0 position. */ -#define DFLL_CALH1_bm (1<<1) /* DFLL Calibration Value B bit 1 mask. */ -#define DFLL_CALH1_bp 1 /* DFLL Calibration Value B bit 1 position. */ -#define DFLL_CALH2_bm (1<<2) /* DFLL Calibration Value B bit 2 mask. */ -#define DFLL_CALH2_bp 2 /* DFLL Calibration Value B bit 2 position. */ -#define DFLL_CALH3_bm (1<<3) /* DFLL Calibration Value B bit 3 mask. */ -#define DFLL_CALH3_bp 3 /* DFLL Calibration Value B bit 3 position. */ -#define DFLL_CALH4_bm (1<<4) /* DFLL Calibration Value B bit 4 mask. */ -#define DFLL_CALH4_bp 4 /* DFLL Calibration Value B bit 4 position. */ -#define DFLL_CALH5_bm (1<<5) /* DFLL Calibration Value B bit 5 mask. */ -#define DFLL_CALH5_bp 5 /* DFLL Calibration Value B bit 5 position. */ - -/* RST - Reset */ -/* RST.STATUS bit masks and bit positions */ -#define RST_SDRF_bm 0x40 /* Spike Detection Reset Flag bit mask. */ -#define RST_SDRF_bp 6 /* Spike Detection Reset Flag bit position. */ - -#define RST_SRF_bm 0x20 /* Software Reset Flag bit mask. */ -#define RST_SRF_bp 5 /* Software Reset Flag bit position. */ - -#define RST_PDIRF_bm 0x10 /* Programming and Debug Interface Interface Reset Flag bit mask. */ -#define RST_PDIRF_bp 4 /* Programming and Debug Interface Interface Reset Flag bit position. */ - -#define RST_WDRF_bm 0x08 /* Watchdog Reset Flag bit mask. */ -#define RST_WDRF_bp 3 /* Watchdog Reset Flag bit position. */ - -#define RST_BORF_bm 0x04 /* Brown-out Reset Flag bit mask. */ -#define RST_BORF_bp 2 /* Brown-out Reset Flag bit position. */ - -#define RST_EXTRF_bm 0x02 /* External Reset Flag bit mask. */ -#define RST_EXTRF_bp 1 /* External Reset Flag bit position. */ - -#define RST_PORF_bm 0x01 /* Power-on Reset Flag bit mask. */ -#define RST_PORF_bp 0 /* Power-on Reset Flag bit position. */ - -/* RST.CTRL bit masks and bit positions */ -#define RST_SWRST_bm 0x01 /* Software Reset bit mask. */ -#define RST_SWRST_bp 0 /* Software Reset bit position. */ - -/* WDT - Watch-Dog Timer */ -/* WDT.CTRL bit masks and bit positions */ -#define WDT_PER_gm 0x3C /* Period group mask. */ -#define WDT_PER_gp 2 /* Period group position. */ -#define WDT_PER0_bm (1<<2) /* Period bit 0 mask. */ -#define WDT_PER0_bp 2 /* Period bit 0 position. */ -#define WDT_PER1_bm (1<<3) /* Period bit 1 mask. */ -#define WDT_PER1_bp 3 /* Period bit 1 position. */ -#define WDT_PER2_bm (1<<4) /* Period bit 2 mask. */ -#define WDT_PER2_bp 4 /* Period bit 2 position. */ -#define WDT_PER3_bm (1<<5) /* Period bit 3 mask. */ -#define WDT_PER3_bp 5 /* Period bit 3 position. */ - -#define WDT_ENABLE_bm 0x02 /* Enable bit mask. */ -#define WDT_ENABLE_bp 1 /* Enable bit position. */ - -#define WDT_CEN_bm 0x01 /* Change Enable bit mask. */ -#define WDT_CEN_bp 0 /* Change Enable bit position. */ - -/* WDT.WINCTRL bit masks and bit positions */ -#define WDT_WPER_gm 0x3C /* Windowed Mode Period group mask. */ -#define WDT_WPER_gp 2 /* Windowed Mode Period group position. */ -#define WDT_WPER0_bm (1<<2) /* Windowed Mode Period bit 0 mask. */ -#define WDT_WPER0_bp 2 /* Windowed Mode Period bit 0 position. */ -#define WDT_WPER1_bm (1<<3) /* Windowed Mode Period bit 1 mask. */ -#define WDT_WPER1_bp 3 /* Windowed Mode Period bit 1 position. */ -#define WDT_WPER2_bm (1<<4) /* Windowed Mode Period bit 2 mask. */ -#define WDT_WPER2_bp 4 /* Windowed Mode Period bit 2 position. */ -#define WDT_WPER3_bm (1<<5) /* Windowed Mode Period bit 3 mask. */ -#define WDT_WPER3_bp 5 /* Windowed Mode Period bit 3 position. */ - -#define WDT_WEN_bm 0x02 /* Windowed Mode Enable bit mask. */ -#define WDT_WEN_bp 1 /* Windowed Mode Enable bit position. */ - -#define WDT_WCEN_bm 0x01 /* Windowed Mode Change Enable bit mask. */ -#define WDT_WCEN_bp 0 /* Windowed Mode Change Enable bit position. */ - -/* WDT.STATUS bit masks and bit positions */ -#define WDT_SYNCBUSY_bm 0x01 /* Syncronization busy bit mask. */ -#define WDT_SYNCBUSY_bp 0 /* Syncronization busy bit position. */ - -/* MCU - MCU Control */ -/* MCU.MCUCR bit masks and bit positions */ -#define MCU_JTAGD_bm 0x01 /* JTAG Disable bit mask. */ -#define MCU_JTAGD_bp 0 /* JTAG Disable bit position. */ - -/* MCU.ANAINIT bit masks and bit positions */ -#define MCU_STARTUPDLYB_gm 0x0C /* Analog startup delay Port B group mask. */ -#define MCU_STARTUPDLYB_gp 2 /* Analog startup delay Port B group position. */ -#define MCU_STARTUPDLYB0_bm (1<<2) /* Analog startup delay Port B bit 0 mask. */ -#define MCU_STARTUPDLYB0_bp 2 /* Analog startup delay Port B bit 0 position. */ -#define MCU_STARTUPDLYB1_bm (1<<3) /* Analog startup delay Port B bit 1 mask. */ -#define MCU_STARTUPDLYB1_bp 3 /* Analog startup delay Port B bit 1 position. */ - -#define MCU_STARTUPDLYA_gm 0x03 /* Analog startup delay Port A group mask. */ -#define MCU_STARTUPDLYA_gp 0 /* Analog startup delay Port A group position. */ -#define MCU_STARTUPDLYA0_bm (1<<0) /* Analog startup delay Port A bit 0 mask. */ -#define MCU_STARTUPDLYA0_bp 0 /* Analog startup delay Port A bit 0 position. */ -#define MCU_STARTUPDLYA1_bm (1<<1) /* Analog startup delay Port A bit 1 mask. */ -#define MCU_STARTUPDLYA1_bp 1 /* Analog startup delay Port A bit 1 position. */ - -/* MCU.EVSYSLOCK bit masks and bit positions */ -#define MCU_EVSYS1LOCK_bm 0x10 /* Event Channel 4-7 Lock bit mask. */ -#define MCU_EVSYS1LOCK_bp 4 /* Event Channel 4-7 Lock bit position. */ - -#define MCU_EVSYS0LOCK_bm 0x01 /* Event Channel 0-3 Lock bit mask. */ -#define MCU_EVSYS0LOCK_bp 0 /* Event Channel 0-3 Lock bit position. */ - -/* MCU.AWEXLOCK bit masks and bit positions */ -#define MCU_AWEXFLOCK_bm 0x08 /* AWeX on T/C F0 Lock bit mask. */ -#define MCU_AWEXFLOCK_bp 3 /* AWeX on T/C F0 Lock bit position. */ - -#define MCU_AWEXELOCK_bm 0x04 /* AWeX on T/C E0 Lock bit mask. */ -#define MCU_AWEXELOCK_bp 2 /* AWeX on T/C E0 Lock bit position. */ - -#define MCU_AWEXDLOCK_bm 0x02 /* AWeX on T/C D0 Lock bit mask. */ -#define MCU_AWEXDLOCK_bp 1 /* AWeX on T/C D0 Lock bit position. */ - -#define MCU_AWEXCLOCK_bm 0x01 /* AWeX on T/C C0 Lock bit mask. */ -#define MCU_AWEXCLOCK_bp 0 /* AWeX on T/C C0 Lock bit position. */ - -/* PMIC - Programmable Multi-level Interrupt Controller */ -/* PMIC.STATUS bit masks and bit positions */ -#define PMIC_NMIEX_bm 0x80 /* Non-maskable Interrupt Executing bit mask. */ -#define PMIC_NMIEX_bp 7 /* Non-maskable Interrupt Executing bit position. */ - -#define PMIC_HILVLEX_bm 0x04 /* High Level Interrupt Executing bit mask. */ -#define PMIC_HILVLEX_bp 2 /* High Level Interrupt Executing bit position. */ - -#define PMIC_MEDLVLEX_bm 0x02 /* Medium Level Interrupt Executing bit mask. */ -#define PMIC_MEDLVLEX_bp 1 /* Medium Level Interrupt Executing bit position. */ - -#define PMIC_LOLVLEX_bm 0x01 /* Low Level Interrupt Executing bit mask. */ -#define PMIC_LOLVLEX_bp 0 /* Low Level Interrupt Executing bit position. */ - -/* PMIC.INTPRI bit masks and bit positions */ -#define PMIC_INTPRI_gm 0xFF /* Interrupt Priority group mask. */ -#define PMIC_INTPRI_gp 0 /* Interrupt Priority group position. */ -#define PMIC_INTPRI0_bm (1<<0) /* Interrupt Priority bit 0 mask. */ -#define PMIC_INTPRI0_bp 0 /* Interrupt Priority bit 0 position. */ -#define PMIC_INTPRI1_bm (1<<1) /* Interrupt Priority bit 1 mask. */ -#define PMIC_INTPRI1_bp 1 /* Interrupt Priority bit 1 position. */ -#define PMIC_INTPRI2_bm (1<<2) /* Interrupt Priority bit 2 mask. */ -#define PMIC_INTPRI2_bp 2 /* Interrupt Priority bit 2 position. */ -#define PMIC_INTPRI3_bm (1<<3) /* Interrupt Priority bit 3 mask. */ -#define PMIC_INTPRI3_bp 3 /* Interrupt Priority bit 3 position. */ -#define PMIC_INTPRI4_bm (1<<4) /* Interrupt Priority bit 4 mask. */ -#define PMIC_INTPRI4_bp 4 /* Interrupt Priority bit 4 position. */ -#define PMIC_INTPRI5_bm (1<<5) /* Interrupt Priority bit 5 mask. */ -#define PMIC_INTPRI5_bp 5 /* Interrupt Priority bit 5 position. */ -#define PMIC_INTPRI6_bm (1<<6) /* Interrupt Priority bit 6 mask. */ -#define PMIC_INTPRI6_bp 6 /* Interrupt Priority bit 6 position. */ -#define PMIC_INTPRI7_bm (1<<7) /* Interrupt Priority bit 7 mask. */ -#define PMIC_INTPRI7_bp 7 /* Interrupt Priority bit 7 position. */ - -/* PMIC.CTRL bit masks and bit positions */ -#define PMIC_RREN_bm 0x80 /* Round-Robin Priority Enable bit mask. */ -#define PMIC_RREN_bp 7 /* Round-Robin Priority Enable bit position. */ - -#define PMIC_IVSEL_bm 0x40 /* Interrupt Vector Select bit mask. */ -#define PMIC_IVSEL_bp 6 /* Interrupt Vector Select bit position. */ - -#define PMIC_HILVLEN_bm 0x04 /* High Level Enable bit mask. */ -#define PMIC_HILVLEN_bp 2 /* High Level Enable bit position. */ - -#define PMIC_MEDLVLEN_bm 0x02 /* Medium Level Enable bit mask. */ -#define PMIC_MEDLVLEN_bp 1 /* Medium Level Enable bit position. */ - -#define PMIC_LOLVLEN_bm 0x01 /* Low Level Enable bit mask. */ -#define PMIC_LOLVLEN_bp 0 /* Low Level Enable bit position. */ - -/* PORTCFG - Port Configuration */ -/* PORTCFG.VPCTRLA bit masks and bit positions */ -#define PORTCFG_VP1MAP_gm 0xF0 /* Virtual Port 1 Mapping group mask. */ -#define PORTCFG_VP1MAP_gp 4 /* Virtual Port 1 Mapping group position. */ -#define PORTCFG_VP1MAP0_bm (1<<4) /* Virtual Port 1 Mapping bit 0 mask. */ -#define PORTCFG_VP1MAP0_bp 4 /* Virtual Port 1 Mapping bit 0 position. */ -#define PORTCFG_VP1MAP1_bm (1<<5) /* Virtual Port 1 Mapping bit 1 mask. */ -#define PORTCFG_VP1MAP1_bp 5 /* Virtual Port 1 Mapping bit 1 position. */ -#define PORTCFG_VP1MAP2_bm (1<<6) /* Virtual Port 1 Mapping bit 2 mask. */ -#define PORTCFG_VP1MAP2_bp 6 /* Virtual Port 1 Mapping bit 2 position. */ -#define PORTCFG_VP1MAP3_bm (1<<7) /* Virtual Port 1 Mapping bit 3 mask. */ -#define PORTCFG_VP1MAP3_bp 7 /* Virtual Port 1 Mapping bit 3 position. */ - -#define PORTCFG_VP0MAP_gm 0x0F /* Virtual Port 0 Mapping group mask. */ -#define PORTCFG_VP0MAP_gp 0 /* Virtual Port 0 Mapping group position. */ -#define PORTCFG_VP0MAP0_bm (1<<0) /* Virtual Port 0 Mapping bit 0 mask. */ -#define PORTCFG_VP0MAP0_bp 0 /* Virtual Port 0 Mapping bit 0 position. */ -#define PORTCFG_VP0MAP1_bm (1<<1) /* Virtual Port 0 Mapping bit 1 mask. */ -#define PORTCFG_VP0MAP1_bp 1 /* Virtual Port 0 Mapping bit 1 position. */ -#define PORTCFG_VP0MAP2_bm (1<<2) /* Virtual Port 0 Mapping bit 2 mask. */ -#define PORTCFG_VP0MAP2_bp 2 /* Virtual Port 0 Mapping bit 2 position. */ -#define PORTCFG_VP0MAP3_bm (1<<3) /* Virtual Port 0 Mapping bit 3 mask. */ -#define PORTCFG_VP0MAP3_bp 3 /* Virtual Port 0 Mapping bit 3 position. */ - -/* PORTCFG.VPCTRLB bit masks and bit positions */ -#define PORTCFG_VP3MAP_gm 0xF0 /* Virtual Port 3 Mapping group mask. */ -#define PORTCFG_VP3MAP_gp 4 /* Virtual Port 3 Mapping group position. */ -#define PORTCFG_VP3MAP0_bm (1<<4) /* Virtual Port 3 Mapping bit 0 mask. */ -#define PORTCFG_VP3MAP0_bp 4 /* Virtual Port 3 Mapping bit 0 position. */ -#define PORTCFG_VP3MAP1_bm (1<<5) /* Virtual Port 3 Mapping bit 1 mask. */ -#define PORTCFG_VP3MAP1_bp 5 /* Virtual Port 3 Mapping bit 1 position. */ -#define PORTCFG_VP3MAP2_bm (1<<6) /* Virtual Port 3 Mapping bit 2 mask. */ -#define PORTCFG_VP3MAP2_bp 6 /* Virtual Port 3 Mapping bit 2 position. */ -#define PORTCFG_VP3MAP3_bm (1<<7) /* Virtual Port 3 Mapping bit 3 mask. */ -#define PORTCFG_VP3MAP3_bp 7 /* Virtual Port 3 Mapping bit 3 position. */ - -#define PORTCFG_VP2MAP_gm 0x0F /* Virtual Port 2 Mapping group mask. */ -#define PORTCFG_VP2MAP_gp 0 /* Virtual Port 2 Mapping group position. */ -#define PORTCFG_VP2MAP0_bm (1<<0) /* Virtual Port 2 Mapping bit 0 mask. */ -#define PORTCFG_VP2MAP0_bp 0 /* Virtual Port 2 Mapping bit 0 position. */ -#define PORTCFG_VP2MAP1_bm (1<<1) /* Virtual Port 2 Mapping bit 1 mask. */ -#define PORTCFG_VP2MAP1_bp 1 /* Virtual Port 2 Mapping bit 1 position. */ -#define PORTCFG_VP2MAP2_bm (1<<2) /* Virtual Port 2 Mapping bit 2 mask. */ -#define PORTCFG_VP2MAP2_bp 2 /* Virtual Port 2 Mapping bit 2 position. */ -#define PORTCFG_VP2MAP3_bm (1<<3) /* Virtual Port 2 Mapping bit 3 mask. */ -#define PORTCFG_VP2MAP3_bp 3 /* Virtual Port 2 Mapping bit 3 position. */ - -/* PORTCFG.CLKEVOUT bit masks and bit positions */ -#define PORTCFG_CLKOUT_gm 0x03 /* Peripheral Clock Output Port group mask. */ -#define PORTCFG_CLKOUT_gp 0 /* Peripheral Clock Output Port group position. */ -#define PORTCFG_CLKOUT0_bm (1<<0) /* Peripheral Clock Output Port bit 0 mask. */ -#define PORTCFG_CLKOUT0_bp 0 /* Peripheral Clock Output Port bit 0 position. */ -#define PORTCFG_CLKOUT1_bm (1<<1) /* Peripheral Clock Output Port bit 1 mask. */ -#define PORTCFG_CLKOUT1_bp 1 /* Peripheral Clock Output Port bit 1 position. */ - -#define PORTCFG_CLKOUTSEL_gm 0x0C /* Peripheral Clock Output Select group mask. */ -#define PORTCFG_CLKOUTSEL_gp 2 /* Peripheral Clock Output Select group position. */ -#define PORTCFG_CLKOUTSEL0_bm (1<<2) /* Peripheral Clock Output Select bit 0 mask. */ -#define PORTCFG_CLKOUTSEL0_bp 2 /* Peripheral Clock Output Select bit 0 position. */ -#define PORTCFG_CLKOUTSEL1_bm (1<<3) /* Peripheral Clock Output Select bit 1 mask. */ -#define PORTCFG_CLKOUTSEL1_bp 3 /* Peripheral Clock Output Select bit 1 position. */ - -#define PORTCFG_EVOUT_gm 0x30 /* Event Output Port group mask. */ -#define PORTCFG_EVOUT_gp 4 /* Event Output Port group position. */ -#define PORTCFG_EVOUT0_bm (1<<4) /* Event Output Port bit 0 mask. */ -#define PORTCFG_EVOUT0_bp 4 /* Event Output Port bit 0 position. */ -#define PORTCFG_EVOUT1_bm (1<<5) /* Event Output Port bit 1 mask. */ -#define PORTCFG_EVOUT1_bp 5 /* Event Output Port bit 1 position. */ - -#define PORTCFG_RTCOUT_bm 0x40 /* RTC Clock Output bit mask. */ -#define PORTCFG_RTCOUT_bp 6 /* RTC Clock Output bit position. */ - -#define PORTCFG_CLKEVPIN_bm 0x80 /* Peripheral Clock and Event Output pin Select bit mask. */ -#define PORTCFG_CLKEVPIN_bp 7 /* Peripheral Clock and Event Output pin Select bit position. */ - -/* PORTCFG.EBIOUT bit masks and bit positions */ -#define PORTCFG_EBICSOUT_gm 0x03 /* EBI Chip Select Output group mask. */ -#define PORTCFG_EBICSOUT_gp 0 /* EBI Chip Select Output group position. */ -#define PORTCFG_EBICSOUT0_bm (1<<0) /* EBI Chip Select Output bit 0 mask. */ -#define PORTCFG_EBICSOUT0_bp 0 /* EBI Chip Select Output bit 0 position. */ -#define PORTCFG_EBICSOUT1_bm (1<<1) /* EBI Chip Select Output bit 1 mask. */ -#define PORTCFG_EBICSOUT1_bp 1 /* EBI Chip Select Output bit 1 position. */ - -#define PORTCFG_EBIADROUT_gm 0x0C /* EBI Address Output group mask. */ -#define PORTCFG_EBIADROUT_gp 2 /* EBI Address Output group position. */ -#define PORTCFG_EBIADROUT0_bm (1<<2) /* EBI Address Output bit 0 mask. */ -#define PORTCFG_EBIADROUT0_bp 2 /* EBI Address Output bit 0 position. */ -#define PORTCFG_EBIADROUT1_bm (1<<3) /* EBI Address Output bit 1 mask. */ -#define PORTCFG_EBIADROUT1_bp 3 /* EBI Address Output bit 1 position. */ - -/* PORTCFG.EVOUTSEL bit masks and bit positions */ -#define PORTCFG_EVOUTSEL_gm 0x07 /* Event Output Select group mask. */ -#define PORTCFG_EVOUTSEL_gp 0 /* Event Output Select group position. */ -#define PORTCFG_EVOUTSEL0_bm (1<<0) /* Event Output Select bit 0 mask. */ -#define PORTCFG_EVOUTSEL0_bp 0 /* Event Output Select bit 0 position. */ -#define PORTCFG_EVOUTSEL1_bm (1<<1) /* Event Output Select bit 1 mask. */ -#define PORTCFG_EVOUTSEL1_bp 1 /* Event Output Select bit 1 position. */ -#define PORTCFG_EVOUTSEL2_bm (1<<2) /* Event Output Select bit 2 mask. */ -#define PORTCFG_EVOUTSEL2_bp 2 /* Event Output Select bit 2 position. */ - -/* AES - AES Module */ -/* AES.CTRL bit masks and bit positions */ -#define AES_START_bm 0x80 /* Start/Run bit mask. */ -#define AES_START_bp 7 /* Start/Run bit position. */ - -#define AES_AUTO_bm 0x40 /* Auto Start Trigger bit mask. */ -#define AES_AUTO_bp 6 /* Auto Start Trigger bit position. */ - -#define AES_RESET_bm 0x20 /* AES Software Reset bit mask. */ -#define AES_RESET_bp 5 /* AES Software Reset bit position. */ - -#define AES_DECRYPT_bm 0x10 /* Decryption / Direction bit mask. */ -#define AES_DECRYPT_bp 4 /* Decryption / Direction bit position. */ - -#define AES_XOR_bm 0x04 /* State XOR Load Enable bit mask. */ -#define AES_XOR_bp 2 /* State XOR Load Enable bit position. */ - -/* AES.STATUS bit masks and bit positions */ -#define AES_ERROR_bm 0x80 /* AES Error bit mask. */ -#define AES_ERROR_bp 7 /* AES Error bit position. */ - -#define AES_SRIF_bm 0x01 /* State Ready Interrupt Flag bit mask. */ -#define AES_SRIF_bp 0 /* State Ready Interrupt Flag bit position. */ - -/* AES.INTCTRL bit masks and bit positions */ -#define AES_INTLVL_gm 0x03 /* Interrupt level group mask. */ -#define AES_INTLVL_gp 0 /* Interrupt level group position. */ -#define AES_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */ -#define AES_INTLVL0_bp 0 /* Interrupt level bit 0 position. */ -#define AES_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */ -#define AES_INTLVL1_bp 1 /* Interrupt level bit 1 position. */ - -/* CRC - Cyclic Redundancy Checker */ -/* CRC.CTRL bit masks and bit positions */ -#define CRC_RESET_gm 0xC0 /* Reset group mask. */ -#define CRC_RESET_gp 6 /* Reset group position. */ -#define CRC_RESET0_bm (1<<6) /* Reset bit 0 mask. */ -#define CRC_RESET0_bp 6 /* Reset bit 0 position. */ -#define CRC_RESET1_bm (1<<7) /* Reset bit 1 mask. */ -#define CRC_RESET1_bp 7 /* Reset bit 1 position. */ - -#define CRC_CRC32_bm 0x20 /* CRC Mode bit mask. */ -#define CRC_CRC32_bp 5 /* CRC Mode bit position. */ - -#define CRC_SOURCE_gm 0x0F /* Input Source group mask. */ -#define CRC_SOURCE_gp 0 /* Input Source group position. */ -#define CRC_SOURCE0_bm (1<<0) /* Input Source bit 0 mask. */ -#define CRC_SOURCE0_bp 0 /* Input Source bit 0 position. */ -#define CRC_SOURCE1_bm (1<<1) /* Input Source bit 1 mask. */ -#define CRC_SOURCE1_bp 1 /* Input Source bit 1 position. */ -#define CRC_SOURCE2_bm (1<<2) /* Input Source bit 2 mask. */ -#define CRC_SOURCE2_bp 2 /* Input Source bit 2 position. */ -#define CRC_SOURCE3_bm (1<<3) /* Input Source bit 3 mask. */ -#define CRC_SOURCE3_bp 3 /* Input Source bit 3 position. */ - -/* CRC.STATUS bit masks and bit positions */ -#define CRC_ZERO_bm 0x02 /* Zero detection bit mask. */ -#define CRC_ZERO_bp 1 /* Zero detection bit position. */ - -#define CRC_BUSY_bm 0x01 /* Busy bit mask. */ -#define CRC_BUSY_bp 0 /* Busy bit position. */ - -/* DMA - DMA Controller */ -/* DMA_CH.CTRLA bit masks and bit positions */ -#define DMA_CH_ENABLE_bm 0x80 /* Channel Enable bit mask. */ -#define DMA_CH_ENABLE_bp 7 /* Channel Enable bit position. */ - -#define DMA_CH_RESET_bm 0x40 /* Channel Software Reset bit mask. */ -#define DMA_CH_RESET_bp 6 /* Channel Software Reset bit position. */ - -#define DMA_CH_REPEAT_bm 0x20 /* Channel Repeat Mode bit mask. */ -#define DMA_CH_REPEAT_bp 5 /* Channel Repeat Mode bit position. */ - -#define DMA_CH_TRFREQ_bm 0x10 /* Channel Transfer Request bit mask. */ -#define DMA_CH_TRFREQ_bp 4 /* Channel Transfer Request bit position. */ - -#define DMA_CH_SINGLE_bm 0x04 /* Channel Single Shot Data Transfer bit mask. */ -#define DMA_CH_SINGLE_bp 2 /* Channel Single Shot Data Transfer bit position. */ - -#define DMA_CH_BURSTLEN_gm 0x03 /* Channel Transfer Mode group mask. */ -#define DMA_CH_BURSTLEN_gp 0 /* Channel Transfer Mode group position. */ -#define DMA_CH_BURSTLEN0_bm (1<<0) /* Channel Transfer Mode bit 0 mask. */ -#define DMA_CH_BURSTLEN0_bp 0 /* Channel Transfer Mode bit 0 position. */ -#define DMA_CH_BURSTLEN1_bm (1<<1) /* Channel Transfer Mode bit 1 mask. */ -#define DMA_CH_BURSTLEN1_bp 1 /* Channel Transfer Mode bit 1 position. */ - -/* DMA_CH.CTRLB bit masks and bit positions */ -#define DMA_CH_CHBUSY_bm 0x80 /* Block Transfer Busy bit mask. */ -#define DMA_CH_CHBUSY_bp 7 /* Block Transfer Busy bit position. */ - -#define DMA_CH_CHPEND_bm 0x40 /* Block Transfer Pending bit mask. */ -#define DMA_CH_CHPEND_bp 6 /* Block Transfer Pending bit position. */ - -#define DMA_CH_ERRIF_bm 0x20 /* Block Transfer Error Interrupt Flag bit mask. */ -#define DMA_CH_ERRIF_bp 5 /* Block Transfer Error Interrupt Flag bit position. */ - -#define DMA_CH_TRNIF_bm 0x10 /* Transaction Complete Interrup Flag bit mask. */ -#define DMA_CH_TRNIF_bp 4 /* Transaction Complete Interrup Flag bit position. */ - -#define DMA_CH_ERRINTLVL_gm 0x0C /* Transfer Error Interrupt Level group mask. */ -#define DMA_CH_ERRINTLVL_gp 2 /* Transfer Error Interrupt Level group position. */ -#define DMA_CH_ERRINTLVL0_bm (1<<2) /* Transfer Error Interrupt Level bit 0 mask. */ -#define DMA_CH_ERRINTLVL0_bp 2 /* Transfer Error Interrupt Level bit 0 position. */ -#define DMA_CH_ERRINTLVL1_bm (1<<3) /* Transfer Error Interrupt Level bit 1 mask. */ -#define DMA_CH_ERRINTLVL1_bp 3 /* Transfer Error Interrupt Level bit 1 position. */ - -#define DMA_CH_TRNINTLVL_gm 0x03 /* Transaction Complete Interrupt Level group mask. */ -#define DMA_CH_TRNINTLVL_gp 0 /* Transaction Complete Interrupt Level group position. */ -#define DMA_CH_TRNINTLVL0_bm (1<<0) /* Transaction Complete Interrupt Level bit 0 mask. */ -#define DMA_CH_TRNINTLVL0_bp 0 /* Transaction Complete Interrupt Level bit 0 position. */ -#define DMA_CH_TRNINTLVL1_bm (1<<1) /* Transaction Complete Interrupt Level bit 1 mask. */ -#define DMA_CH_TRNINTLVL1_bp 1 /* Transaction Complete Interrupt Level bit 1 position. */ - -/* DMA_CH.ADDRCTRL bit masks and bit positions */ -#define DMA_CH_SRCRELOAD_gm 0xC0 /* Channel Source Address Reload group mask. */ -#define DMA_CH_SRCRELOAD_gp 6 /* Channel Source Address Reload group position. */ -#define DMA_CH_SRCRELOAD0_bm (1<<6) /* Channel Source Address Reload bit 0 mask. */ -#define DMA_CH_SRCRELOAD0_bp 6 /* Channel Source Address Reload bit 0 position. */ -#define DMA_CH_SRCRELOAD1_bm (1<<7) /* Channel Source Address Reload bit 1 mask. */ -#define DMA_CH_SRCRELOAD1_bp 7 /* Channel Source Address Reload bit 1 position. */ - -#define DMA_CH_SRCDIR_gm 0x30 /* Channel Source Address Mode group mask. */ -#define DMA_CH_SRCDIR_gp 4 /* Channel Source Address Mode group position. */ -#define DMA_CH_SRCDIR0_bm (1<<4) /* Channel Source Address Mode bit 0 mask. */ -#define DMA_CH_SRCDIR0_bp 4 /* Channel Source Address Mode bit 0 position. */ -#define DMA_CH_SRCDIR1_bm (1<<5) /* Channel Source Address Mode bit 1 mask. */ -#define DMA_CH_SRCDIR1_bp 5 /* Channel Source Address Mode bit 1 position. */ - -#define DMA_CH_DESTRELOAD_gm 0x0C /* Channel Destination Address Reload group mask. */ -#define DMA_CH_DESTRELOAD_gp 2 /* Channel Destination Address Reload group position. */ -#define DMA_CH_DESTRELOAD0_bm (1<<2) /* Channel Destination Address Reload bit 0 mask. */ -#define DMA_CH_DESTRELOAD0_bp 2 /* Channel Destination Address Reload bit 0 position. */ -#define DMA_CH_DESTRELOAD1_bm (1<<3) /* Channel Destination Address Reload bit 1 mask. */ -#define DMA_CH_DESTRELOAD1_bp 3 /* Channel Destination Address Reload bit 1 position. */ - -#define DMA_CH_DESTDIR_gm 0x03 /* Channel Destination Address Mode group mask. */ -#define DMA_CH_DESTDIR_gp 0 /* Channel Destination Address Mode group position. */ -#define DMA_CH_DESTDIR0_bm (1<<0) /* Channel Destination Address Mode bit 0 mask. */ -#define DMA_CH_DESTDIR0_bp 0 /* Channel Destination Address Mode bit 0 position. */ -#define DMA_CH_DESTDIR1_bm (1<<1) /* Channel Destination Address Mode bit 1 mask. */ -#define DMA_CH_DESTDIR1_bp 1 /* Channel Destination Address Mode bit 1 position. */ - -/* DMA_CH.TRIGSRC bit masks and bit positions */ -#define DMA_CH_TRIGSRC_gm 0xFF /* Channel Trigger Source group mask. */ -#define DMA_CH_TRIGSRC_gp 0 /* Channel Trigger Source group position. */ -#define DMA_CH_TRIGSRC0_bm (1<<0) /* Channel Trigger Source bit 0 mask. */ -#define DMA_CH_TRIGSRC0_bp 0 /* Channel Trigger Source bit 0 position. */ -#define DMA_CH_TRIGSRC1_bm (1<<1) /* Channel Trigger Source bit 1 mask. */ -#define DMA_CH_TRIGSRC1_bp 1 /* Channel Trigger Source bit 1 position. */ -#define DMA_CH_TRIGSRC2_bm (1<<2) /* Channel Trigger Source bit 2 mask. */ -#define DMA_CH_TRIGSRC2_bp 2 /* Channel Trigger Source bit 2 position. */ -#define DMA_CH_TRIGSRC3_bm (1<<3) /* Channel Trigger Source bit 3 mask. */ -#define DMA_CH_TRIGSRC3_bp 3 /* Channel Trigger Source bit 3 position. */ -#define DMA_CH_TRIGSRC4_bm (1<<4) /* Channel Trigger Source bit 4 mask. */ -#define DMA_CH_TRIGSRC4_bp 4 /* Channel Trigger Source bit 4 position. */ -#define DMA_CH_TRIGSRC5_bm (1<<5) /* Channel Trigger Source bit 5 mask. */ -#define DMA_CH_TRIGSRC5_bp 5 /* Channel Trigger Source bit 5 position. */ -#define DMA_CH_TRIGSRC6_bm (1<<6) /* Channel Trigger Source bit 6 mask. */ -#define DMA_CH_TRIGSRC6_bp 6 /* Channel Trigger Source bit 6 position. */ -#define DMA_CH_TRIGSRC7_bm (1<<7) /* Channel Trigger Source bit 7 mask. */ -#define DMA_CH_TRIGSRC7_bp 7 /* Channel Trigger Source bit 7 position. */ - -/* DMA.CTRL bit masks and bit positions */ -#define DMA_ENABLE_bm 0x80 /* Enable bit mask. */ -#define DMA_ENABLE_bp 7 /* Enable bit position. */ - -#define DMA_RESET_bm 0x40 /* Software Reset bit mask. */ -#define DMA_RESET_bp 6 /* Software Reset bit position. */ - -#define DMA_DBUFMODE_gm 0x0C /* Double Buffering Mode group mask. */ -#define DMA_DBUFMODE_gp 2 /* Double Buffering Mode group position. */ -#define DMA_DBUFMODE0_bm (1<<2) /* Double Buffering Mode bit 0 mask. */ -#define DMA_DBUFMODE0_bp 2 /* Double Buffering Mode bit 0 position. */ -#define DMA_DBUFMODE1_bm (1<<3) /* Double Buffering Mode bit 1 mask. */ -#define DMA_DBUFMODE1_bp 3 /* Double Buffering Mode bit 1 position. */ - -#define DMA_PRIMODE_gm 0x03 /* Channel Priority Mode group mask. */ -#define DMA_PRIMODE_gp 0 /* Channel Priority Mode group position. */ -#define DMA_PRIMODE0_bm (1<<0) /* Channel Priority Mode bit 0 mask. */ -#define DMA_PRIMODE0_bp 0 /* Channel Priority Mode bit 0 position. */ -#define DMA_PRIMODE1_bm (1<<1) /* Channel Priority Mode bit 1 mask. */ -#define DMA_PRIMODE1_bp 1 /* Channel Priority Mode bit 1 position. */ - -/* DMA.INTFLAGS bit masks and bit positions */ -#define DMA_CH3ERRIF_bm 0x80 /* Channel 3 Block Transfer Error Interrupt Flag bit mask. */ -#define DMA_CH3ERRIF_bp 7 /* Channel 3 Block Transfer Error Interrupt Flag bit position. */ - -#define DMA_CH2ERRIF_bm 0x40 /* Channel 2 Block Transfer Error Interrupt Flag bit mask. */ -#define DMA_CH2ERRIF_bp 6 /* Channel 2 Block Transfer Error Interrupt Flag bit position. */ - -#define DMA_CH1ERRIF_bm 0x20 /* Channel 1 Block Transfer Error Interrupt Flag bit mask. */ -#define DMA_CH1ERRIF_bp 5 /* Channel 1 Block Transfer Error Interrupt Flag bit position. */ - -#define DMA_CH0ERRIF_bm 0x10 /* Channel 0 Block Transfer Error Interrupt Flag bit mask. */ -#define DMA_CH0ERRIF_bp 4 /* Channel 0 Block Transfer Error Interrupt Flag bit position. */ - -#define DMA_CH3TRNIF_bm 0x08 /* Channel 3 Transaction Complete Interrupt Flag bit mask. */ -#define DMA_CH3TRNIF_bp 3 /* Channel 3 Transaction Complete Interrupt Flag bit position. */ - -#define DMA_CH2TRNIF_bm 0x04 /* Channel 2 Transaction Complete Interrupt Flag bit mask. */ -#define DMA_CH2TRNIF_bp 2 /* Channel 2 Transaction Complete Interrupt Flag bit position. */ - -#define DMA_CH1TRNIF_bm 0x02 /* Channel 1 Transaction Complete Interrupt Flag bit mask. */ -#define DMA_CH1TRNIF_bp 1 /* Channel 1 Transaction Complete Interrupt Flag bit position. */ - -#define DMA_CH0TRNIF_bm 0x01 /* Channel 0 Transaction Complete Interrupt Flag bit mask. */ -#define DMA_CH0TRNIF_bp 0 /* Channel 0 Transaction Complete Interrupt Flag bit position. */ - -/* DMA.STATUS bit masks and bit positions */ -#define DMA_CH3BUSY_bm 0x80 /* Channel 3 Block Transfer Busy bit mask. */ -#define DMA_CH3BUSY_bp 7 /* Channel 3 Block Transfer Busy bit position. */ - -#define DMA_CH2BUSY_bm 0x40 /* Channel 2 Block Transfer Busy bit mask. */ -#define DMA_CH2BUSY_bp 6 /* Channel 2 Block Transfer Busy bit position. */ - -#define DMA_CH1BUSY_bm 0x20 /* Channel 1 Block Transfer Busy bit mask. */ -#define DMA_CH1BUSY_bp 5 /* Channel 1 Block Transfer Busy bit position. */ - -#define DMA_CH0BUSY_bm 0x10 /* Channel 0 Block Transfer Busy bit mask. */ -#define DMA_CH0BUSY_bp 4 /* Channel 0 Block Transfer Busy bit position. */ - -#define DMA_CH3PEND_bm 0x08 /* Channel 3 Block Transfer Pending bit mask. */ -#define DMA_CH3PEND_bp 3 /* Channel 3 Block Transfer Pending bit position. */ - -#define DMA_CH2PEND_bm 0x04 /* Channel 2 Block Transfer Pending bit mask. */ -#define DMA_CH2PEND_bp 2 /* Channel 2 Block Transfer Pending bit position. */ - -#define DMA_CH1PEND_bm 0x02 /* Channel 1 Block Transfer Pending bit mask. */ -#define DMA_CH1PEND_bp 1 /* Channel 1 Block Transfer Pending bit position. */ - -#define DMA_CH0PEND_bm 0x01 /* Channel 0 Block Transfer Pending bit mask. */ -#define DMA_CH0PEND_bp 0 /* Channel 0 Block Transfer Pending bit position. */ - -/* EVSYS - Event System */ -/* EVSYS.CH0MUX bit masks and bit positions */ -#define EVSYS_CHMUX_gm 0xFF /* Event Channel 0 Multiplexer group mask. */ -#define EVSYS_CHMUX_gp 0 /* Event Channel 0 Multiplexer group position. */ -#define EVSYS_CHMUX0_bm (1<<0) /* Event Channel 0 Multiplexer bit 0 mask. */ -#define EVSYS_CHMUX0_bp 0 /* Event Channel 0 Multiplexer bit 0 position. */ -#define EVSYS_CHMUX1_bm (1<<1) /* Event Channel 0 Multiplexer bit 1 mask. */ -#define EVSYS_CHMUX1_bp 1 /* Event Channel 0 Multiplexer bit 1 position. */ -#define EVSYS_CHMUX2_bm (1<<2) /* Event Channel 0 Multiplexer bit 2 mask. */ -#define EVSYS_CHMUX2_bp 2 /* Event Channel 0 Multiplexer bit 2 position. */ -#define EVSYS_CHMUX3_bm (1<<3) /* Event Channel 0 Multiplexer bit 3 mask. */ -#define EVSYS_CHMUX3_bp 3 /* Event Channel 0 Multiplexer bit 3 position. */ -#define EVSYS_CHMUX4_bm (1<<4) /* Event Channel 0 Multiplexer bit 4 mask. */ -#define EVSYS_CHMUX4_bp 4 /* Event Channel 0 Multiplexer bit 4 position. */ -#define EVSYS_CHMUX5_bm (1<<5) /* Event Channel 0 Multiplexer bit 5 mask. */ -#define EVSYS_CHMUX5_bp 5 /* Event Channel 0 Multiplexer bit 5 position. */ -#define EVSYS_CHMUX6_bm (1<<6) /* Event Channel 0 Multiplexer bit 6 mask. */ -#define EVSYS_CHMUX6_bp 6 /* Event Channel 0 Multiplexer bit 6 position. */ -#define EVSYS_CHMUX7_bm (1<<7) /* Event Channel 0 Multiplexer bit 7 mask. */ -#define EVSYS_CHMUX7_bp 7 /* Event Channel 0 Multiplexer bit 7 position. */ - -/* EVSYS.CH1MUX bit masks and bit positions */ -/* EVSYS_CHMUX Predefined. */ -/* EVSYS_CHMUX Predefined. */ - -/* EVSYS.CH2MUX bit masks and bit positions */ -/* EVSYS_CHMUX Predefined. */ -/* EVSYS_CHMUX Predefined. */ - -/* EVSYS.CH3MUX bit masks and bit positions */ -/* EVSYS_CHMUX Predefined. */ -/* EVSYS_CHMUX Predefined. */ - -/* EVSYS.CH4MUX bit masks and bit positions */ -/* EVSYS_CHMUX Predefined. */ -/* EVSYS_CHMUX Predefined. */ - -/* EVSYS.CH5MUX bit masks and bit positions */ -/* EVSYS_CHMUX Predefined. */ -/* EVSYS_CHMUX Predefined. */ - -/* EVSYS.CH6MUX bit masks and bit positions */ -/* EVSYS_CHMUX Predefined. */ -/* EVSYS_CHMUX Predefined. */ - -/* EVSYS.CH7MUX bit masks and bit positions */ -/* EVSYS_CHMUX Predefined. */ -/* EVSYS_CHMUX Predefined. */ - -/* EVSYS.CH0CTRL bit masks and bit positions */ -#define EVSYS_QDIRM_gm 0x60 /* Quadrature Decoder Index Recognition Mode group mask. */ -#define EVSYS_QDIRM_gp 5 /* Quadrature Decoder Index Recognition Mode group position. */ -#define EVSYS_QDIRM0_bm (1<<5) /* Quadrature Decoder Index Recognition Mode bit 0 mask. */ -#define EVSYS_QDIRM0_bp 5 /* Quadrature Decoder Index Recognition Mode bit 0 position. */ -#define EVSYS_QDIRM1_bm (1<<6) /* Quadrature Decoder Index Recognition Mode bit 1 mask. */ -#define EVSYS_QDIRM1_bp 6 /* Quadrature Decoder Index Recognition Mode bit 1 position. */ - -#define EVSYS_QDIEN_bm 0x10 /* Quadrature Decoder Index Enable bit mask. */ -#define EVSYS_QDIEN_bp 4 /* Quadrature Decoder Index Enable bit position. */ - -#define EVSYS_QDEN_bm 0x08 /* Quadrature Decoder Enable bit mask. */ -#define EVSYS_QDEN_bp 3 /* Quadrature Decoder Enable bit position. */ - -#define EVSYS_DIGFILT_gm 0x07 /* Digital Filter group mask. */ -#define EVSYS_DIGFILT_gp 0 /* Digital Filter group position. */ -#define EVSYS_DIGFILT0_bm (1<<0) /* Digital Filter bit 0 mask. */ -#define EVSYS_DIGFILT0_bp 0 /* Digital Filter bit 0 position. */ -#define EVSYS_DIGFILT1_bm (1<<1) /* Digital Filter bit 1 mask. */ -#define EVSYS_DIGFILT1_bp 1 /* Digital Filter bit 1 position. */ -#define EVSYS_DIGFILT2_bm (1<<2) /* Digital Filter bit 2 mask. */ -#define EVSYS_DIGFILT2_bp 2 /* Digital Filter bit 2 position. */ - -/* EVSYS.CH1CTRL bit masks and bit positions */ -/* EVSYS_DIGFILT Predefined. */ -/* EVSYS_DIGFILT Predefined. */ - -/* EVSYS.CH2CTRL bit masks and bit positions */ -/* EVSYS_QDIRM Predefined. */ -/* EVSYS_QDIRM Predefined. */ - -/* EVSYS_QDIEN Predefined. */ -/* EVSYS_QDIEN Predefined. */ - -/* EVSYS_QDEN Predefined. */ -/* EVSYS_QDEN Predefined. */ - -/* EVSYS_DIGFILT Predefined. */ -/* EVSYS_DIGFILT Predefined. */ - -/* EVSYS.CH3CTRL bit masks and bit positions */ -/* EVSYS_DIGFILT Predefined. */ -/* EVSYS_DIGFILT Predefined. */ - -/* EVSYS.CH4CTRL bit masks and bit positions */ -/* EVSYS_QDIRM Predefined. */ -/* EVSYS_QDIRM Predefined. */ - -/* EVSYS_QDIEN Predefined. */ -/* EVSYS_QDIEN Predefined. */ - -/* EVSYS_QDEN Predefined. */ -/* EVSYS_QDEN Predefined. */ - -/* EVSYS_DIGFILT Predefined. */ -/* EVSYS_DIGFILT Predefined. */ - -/* EVSYS.CH5CTRL bit masks and bit positions */ -/* EVSYS_DIGFILT Predefined. */ -/* EVSYS_DIGFILT Predefined. */ - -/* EVSYS.CH6CTRL bit masks and bit positions */ -/* EVSYS_DIGFILT Predefined. */ -/* EVSYS_DIGFILT Predefined. */ - -/* EVSYS.CH7CTRL bit masks and bit positions */ -/* EVSYS_DIGFILT Predefined. */ -/* EVSYS_DIGFILT Predefined. */ - -/* NVM - Non Volatile Memory Controller */ -/* NVM.CMD bit masks and bit positions */ -#define NVM_CMD_gm 0x7F /* Command group mask. */ -#define NVM_CMD_gp 0 /* Command group position. */ -#define NVM_CMD0_bm (1<<0) /* Command bit 0 mask. */ -#define NVM_CMD0_bp 0 /* Command bit 0 position. */ -#define NVM_CMD1_bm (1<<1) /* Command bit 1 mask. */ -#define NVM_CMD1_bp 1 /* Command bit 1 position. */ -#define NVM_CMD2_bm (1<<2) /* Command bit 2 mask. */ -#define NVM_CMD2_bp 2 /* Command bit 2 position. */ -#define NVM_CMD3_bm (1<<3) /* Command bit 3 mask. */ -#define NVM_CMD3_bp 3 /* Command bit 3 position. */ -#define NVM_CMD4_bm (1<<4) /* Command bit 4 mask. */ -#define NVM_CMD4_bp 4 /* Command bit 4 position. */ -#define NVM_CMD5_bm (1<<5) /* Command bit 5 mask. */ -#define NVM_CMD5_bp 5 /* Command bit 5 position. */ -#define NVM_CMD6_bm (1<<6) /* Command bit 6 mask. */ -#define NVM_CMD6_bp 6 /* Command bit 6 position. */ - -/* NVM.CTRLA bit masks and bit positions */ -#define NVM_CMDEX_bm 0x01 /* Command Execute bit mask. */ -#define NVM_CMDEX_bp 0 /* Command Execute bit position. */ - -/* NVM.CTRLB bit masks and bit positions */ -#define NVM_EEMAPEN_bm 0x08 /* EEPROM Mapping Enable bit mask. */ -#define NVM_EEMAPEN_bp 3 /* EEPROM Mapping Enable bit position. */ - -#define NVM_FPRM_bm 0x04 /* Flash Power Reduction Enable bit mask. */ -#define NVM_FPRM_bp 2 /* Flash Power Reduction Enable bit position. */ - -#define NVM_EPRM_bm 0x02 /* EEPROM Power Reduction Enable bit mask. */ -#define NVM_EPRM_bp 1 /* EEPROM Power Reduction Enable bit position. */ - -#define NVM_SPMLOCK_bm 0x01 /* SPM Lock bit mask. */ -#define NVM_SPMLOCK_bp 0 /* SPM Lock bit position. */ - -/* NVM.INTCTRL bit masks and bit positions */ -#define NVM_SPMLVL_gm 0x0C /* SPM Interrupt Level group mask. */ -#define NVM_SPMLVL_gp 2 /* SPM Interrupt Level group position. */ -#define NVM_SPMLVL0_bm (1<<2) /* SPM Interrupt Level bit 0 mask. */ -#define NVM_SPMLVL0_bp 2 /* SPM Interrupt Level bit 0 position. */ -#define NVM_SPMLVL1_bm (1<<3) /* SPM Interrupt Level bit 1 mask. */ -#define NVM_SPMLVL1_bp 3 /* SPM Interrupt Level bit 1 position. */ - -#define NVM_EELVL_gm 0x03 /* EEPROM Interrupt Level group mask. */ -#define NVM_EELVL_gp 0 /* EEPROM Interrupt Level group position. */ -#define NVM_EELVL0_bm (1<<0) /* EEPROM Interrupt Level bit 0 mask. */ -#define NVM_EELVL0_bp 0 /* EEPROM Interrupt Level bit 0 position. */ -#define NVM_EELVL1_bm (1<<1) /* EEPROM Interrupt Level bit 1 mask. */ -#define NVM_EELVL1_bp 1 /* EEPROM Interrupt Level bit 1 position. */ - -/* NVM.STATUS bit masks and bit positions */ -#define NVM_NVMBUSY_bm 0x80 /* Non-volatile Memory Busy bit mask. */ -#define NVM_NVMBUSY_bp 7 /* Non-volatile Memory Busy bit position. */ - -#define NVM_FBUSY_bm 0x40 /* Flash Memory Busy bit mask. */ -#define NVM_FBUSY_bp 6 /* Flash Memory Busy bit position. */ - -#define NVM_EELOAD_bm 0x02 /* EEPROM Page Buffer Active Loading bit mask. */ -#define NVM_EELOAD_bp 1 /* EEPROM Page Buffer Active Loading bit position. */ - -#define NVM_FLOAD_bm 0x01 /* Flash Page Buffer Active Loading bit mask. */ -#define NVM_FLOAD_bp 0 /* Flash Page Buffer Active Loading bit position. */ - -/* NVM.LOCKBITS bit masks and bit positions */ -#define NVM_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ -#define NVM_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ -#define NVM_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ -#define NVM_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ -#define NVM_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ -#define NVM_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ - -#define NVM_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ -#define NVM_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ -#define NVM_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ -#define NVM_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ -#define NVM_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ -#define NVM_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ - -#define NVM_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ -#define NVM_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ -#define NVM_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ -#define NVM_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ -#define NVM_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ -#define NVM_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ - -#define NVM_LB_gm 0x03 /* Lock Bits group mask. */ -#define NVM_LB_gp 0 /* Lock Bits group position. */ -#define NVM_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ -#define NVM_LB0_bp 0 /* Lock Bits bit 0 position. */ -#define NVM_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ -#define NVM_LB1_bp 1 /* Lock Bits bit 1 position. */ - -/* ADC - Analog/Digital Converter */ -/* ADC_CH.CTRL bit masks and bit positions */ -#define ADC_CH_START_bm 0x80 /* Channel Start Conversion bit mask. */ -#define ADC_CH_START_bp 7 /* Channel Start Conversion bit position. */ - -#define ADC_CH_GAIN_gm 0x1C /* Gain Factor group mask. */ -#define ADC_CH_GAIN_gp 2 /* Gain Factor group position. */ -#define ADC_CH_GAIN0_bm (1<<2) /* Gain Factor bit 0 mask. */ -#define ADC_CH_GAIN0_bp 2 /* Gain Factor bit 0 position. */ -#define ADC_CH_GAIN1_bm (1<<3) /* Gain Factor bit 1 mask. */ -#define ADC_CH_GAIN1_bp 3 /* Gain Factor bit 1 position. */ -#define ADC_CH_GAIN2_bm (1<<4) /* Gain Factor bit 2 mask. */ -#define ADC_CH_GAIN2_bp 4 /* Gain Factor bit 2 position. */ - -#define ADC_CH_INPUTMODE_gm 0x03 /* Input Mode Select group mask. */ -#define ADC_CH_INPUTMODE_gp 0 /* Input Mode Select group position. */ -#define ADC_CH_INPUTMODE0_bm (1<<0) /* Input Mode Select bit 0 mask. */ -#define ADC_CH_INPUTMODE0_bp 0 /* Input Mode Select bit 0 position. */ -#define ADC_CH_INPUTMODE1_bm (1<<1) /* Input Mode Select bit 1 mask. */ -#define ADC_CH_INPUTMODE1_bp 1 /* Input Mode Select bit 1 position. */ - -/* ADC_CH.MUXCTRL bit masks and bit positions */ -#define ADC_CH_MUXPOS_gm 0x78 /* MUX selection on Positive ADC input group mask. */ -#define ADC_CH_MUXPOS_gp 3 /* MUX selection on Positive ADC input group position. */ -#define ADC_CH_MUXPOS0_bm (1<<3) /* MUX selection on Positive ADC input bit 0 mask. */ -#define ADC_CH_MUXPOS0_bp 3 /* MUX selection on Positive ADC input bit 0 position. */ -#define ADC_CH_MUXPOS1_bm (1<<4) /* MUX selection on Positive ADC input bit 1 mask. */ -#define ADC_CH_MUXPOS1_bp 4 /* MUX selection on Positive ADC input bit 1 position. */ -#define ADC_CH_MUXPOS2_bm (1<<5) /* MUX selection on Positive ADC input bit 2 mask. */ -#define ADC_CH_MUXPOS2_bp 5 /* MUX selection on Positive ADC input bit 2 position. */ -#define ADC_CH_MUXPOS3_bm (1<<6) /* MUX selection on Positive ADC input bit 3 mask. */ -#define ADC_CH_MUXPOS3_bp 6 /* MUX selection on Positive ADC input bit 3 position. */ - -#define ADC_CH_MUXINT_gm 0x78 /* MUX selection on Internal ADC input group mask. */ -#define ADC_CH_MUXINT_gp 3 /* MUX selection on Internal ADC input group position. */ -#define ADC_CH_MUXINT0_bm (1<<3) /* MUX selection on Internal ADC input bit 0 mask. */ -#define ADC_CH_MUXINT0_bp 3 /* MUX selection on Internal ADC input bit 0 position. */ -#define ADC_CH_MUXINT1_bm (1<<4) /* MUX selection on Internal ADC input bit 1 mask. */ -#define ADC_CH_MUXINT1_bp 4 /* MUX selection on Internal ADC input bit 1 position. */ -#define ADC_CH_MUXINT2_bm (1<<5) /* MUX selection on Internal ADC input bit 2 mask. */ -#define ADC_CH_MUXINT2_bp 5 /* MUX selection on Internal ADC input bit 2 position. */ -#define ADC_CH_MUXINT3_bm (1<<6) /* MUX selection on Internal ADC input bit 3 mask. */ -#define ADC_CH_MUXINT3_bp 6 /* MUX selection on Internal ADC input bit 3 position. */ - -#define ADC_CH_MUXNEG_gm 0x07 /* MUX selection on Negative ADC input group mask. */ -#define ADC_CH_MUXNEG_gp 0 /* MUX selection on Negative ADC input group position. */ -#define ADC_CH_MUXNEG0_bm (1<<0) /* MUX selection on Negative ADC input bit 0 mask. */ -#define ADC_CH_MUXNEG0_bp 0 /* MUX selection on Negative ADC input bit 0 position. */ -#define ADC_CH_MUXNEG1_bm (1<<1) /* MUX selection on Negative ADC input bit 1 mask. */ -#define ADC_CH_MUXNEG1_bp 1 /* MUX selection on Negative ADC input bit 1 position. */ -#define ADC_CH_MUXNEG2_bm (1<<2) /* MUX selection on Negative ADC input bit 2 mask. */ -#define ADC_CH_MUXNEG2_bp 2 /* MUX selection on Negative ADC input bit 2 position. */ - -/* ADC_CH.INTCTRL bit masks and bit positions */ -#define ADC_CH_INTMODE_gm 0x0C /* Interrupt Mode group mask. */ -#define ADC_CH_INTMODE_gp 2 /* Interrupt Mode group position. */ -#define ADC_CH_INTMODE0_bm (1<<2) /* Interrupt Mode bit 0 mask. */ -#define ADC_CH_INTMODE0_bp 2 /* Interrupt Mode bit 0 position. */ -#define ADC_CH_INTMODE1_bm (1<<3) /* Interrupt Mode bit 1 mask. */ -#define ADC_CH_INTMODE1_bp 3 /* Interrupt Mode bit 1 position. */ - -#define ADC_CH_INTLVL_gm 0x03 /* Interrupt Level group mask. */ -#define ADC_CH_INTLVL_gp 0 /* Interrupt Level group position. */ -#define ADC_CH_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */ -#define ADC_CH_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */ -#define ADC_CH_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ -#define ADC_CH_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */ - -/* ADC_CH.INTFLAGS bit masks and bit positions */ -#define ADC_CH_CHIF_bm 0x01 /* Channel Interrupt Flag bit mask. */ -#define ADC_CH_CHIF_bp 0 /* Channel Interrupt Flag bit position. */ - -/* ADC_CH.SCAN bit masks and bit positions */ -#define ADC_CH_OFFSET_gm 0xF0 /* Positive MUX setting offset group mask. */ -#define ADC_CH_OFFSET_gp 4 /* Positive MUX setting offset group position. */ -#define ADC_CH_OFFSET0_bm (1<<4) /* Positive MUX setting offset bit 0 mask. */ -#define ADC_CH_OFFSET0_bp 4 /* Positive MUX setting offset bit 0 position. */ -#define ADC_CH_OFFSET1_bm (1<<5) /* Positive MUX setting offset bit 1 mask. */ -#define ADC_CH_OFFSET1_bp 5 /* Positive MUX setting offset bit 1 position. */ -#define ADC_CH_OFFSET2_bm (1<<6) /* Positive MUX setting offset bit 2 mask. */ -#define ADC_CH_OFFSET2_bp 6 /* Positive MUX setting offset bit 2 position. */ -#define ADC_CH_OFFSET3_bm (1<<7) /* Positive MUX setting offset bit 3 mask. */ -#define ADC_CH_OFFSET3_bp 7 /* Positive MUX setting offset bit 3 position. */ - -#define ADC_CH_SCANNUM_gm 0x0F /* Number of Channels included in scan group mask. */ -#define ADC_CH_SCANNUM_gp 0 /* Number of Channels included in scan group position. */ -#define ADC_CH_SCANNUM0_bm (1<<0) /* Number of Channels included in scan bit 0 mask. */ -#define ADC_CH_SCANNUM0_bp 0 /* Number of Channels included in scan bit 0 position. */ -#define ADC_CH_SCANNUM1_bm (1<<1) /* Number of Channels included in scan bit 1 mask. */ -#define ADC_CH_SCANNUM1_bp 1 /* Number of Channels included in scan bit 1 position. */ -#define ADC_CH_SCANNUM2_bm (1<<2) /* Number of Channels included in scan bit 2 mask. */ -#define ADC_CH_SCANNUM2_bp 2 /* Number of Channels included in scan bit 2 position. */ -#define ADC_CH_SCANNUM3_bm (1<<3) /* Number of Channels included in scan bit 3 mask. */ -#define ADC_CH_SCANNUM3_bp 3 /* Number of Channels included in scan bit 3 position. */ - -/* ADC.CTRLA bit masks and bit positions */ -#define ADC_DMASEL_gm 0xC0 /* DMA Selection group mask. */ -#define ADC_DMASEL_gp 6 /* DMA Selection group position. */ -#define ADC_DMASEL0_bm (1<<6) /* DMA Selection bit 0 mask. */ -#define ADC_DMASEL0_bp 6 /* DMA Selection bit 0 position. */ -#define ADC_DMASEL1_bm (1<<7) /* DMA Selection bit 1 mask. */ -#define ADC_DMASEL1_bp 7 /* DMA Selection bit 1 position. */ - -#define ADC_CH3START_bm 0x20 /* Channel 3 Start Conversion bit mask. */ -#define ADC_CH3START_bp 5 /* Channel 3 Start Conversion bit position. */ - -#define ADC_CH2START_bm 0x10 /* Channel 2 Start Conversion bit mask. */ -#define ADC_CH2START_bp 4 /* Channel 2 Start Conversion bit position. */ - -#define ADC_CH1START_bm 0x08 /* Channel 1 Start Conversion bit mask. */ -#define ADC_CH1START_bp 3 /* Channel 1 Start Conversion bit position. */ - -#define ADC_CH0START_bm 0x04 /* Channel 0 Start Conversion bit mask. */ -#define ADC_CH0START_bp 2 /* Channel 0 Start Conversion bit position. */ - -#define ADC_FLUSH_bm 0x02 /* Flush Pipeline bit mask. */ -#define ADC_FLUSH_bp 1 /* Flush Pipeline bit position. */ - -#define ADC_ENABLE_bm 0x01 /* Enable ADC bit mask. */ -#define ADC_ENABLE_bp 0 /* Enable ADC bit position. */ - -/* ADC.CTRLB bit masks and bit positions */ -#define ADC_IMPMODE_bm 0x80 /* Gain Stage Impedance Mode bit mask. */ -#define ADC_IMPMODE_bp 7 /* Gain Stage Impedance Mode bit position. */ - -#define ADC_CURRLIMIT_gm 0x60 /* Current Limitation group mask. */ -#define ADC_CURRLIMIT_gp 5 /* Current Limitation group position. */ -#define ADC_CURRLIMIT0_bm (1<<5) /* Current Limitation bit 0 mask. */ -#define ADC_CURRLIMIT0_bp 5 /* Current Limitation bit 0 position. */ -#define ADC_CURRLIMIT1_bm (1<<6) /* Current Limitation bit 1 mask. */ -#define ADC_CURRLIMIT1_bp 6 /* Current Limitation bit 1 position. */ - -#define ADC_CONMODE_bm 0x10 /* Conversion Mode bit mask. */ -#define ADC_CONMODE_bp 4 /* Conversion Mode bit position. */ - -#define ADC_FREERUN_bm 0x08 /* Free Running Mode Enable bit mask. */ -#define ADC_FREERUN_bp 3 /* Free Running Mode Enable bit position. */ - -#define ADC_RESOLUTION_gm 0x06 /* Result Resolution group mask. */ -#define ADC_RESOLUTION_gp 1 /* Result Resolution group position. */ -#define ADC_RESOLUTION0_bm (1<<1) /* Result Resolution bit 0 mask. */ -#define ADC_RESOLUTION0_bp 1 /* Result Resolution bit 0 position. */ -#define ADC_RESOLUTION1_bm (1<<2) /* Result Resolution bit 1 mask. */ -#define ADC_RESOLUTION1_bp 2 /* Result Resolution bit 1 position. */ - -/* ADC.REFCTRL bit masks and bit positions */ -#define ADC_REFSEL_gm 0x70 /* Reference Selection group mask. */ -#define ADC_REFSEL_gp 4 /* Reference Selection group position. */ -#define ADC_REFSEL0_bm (1<<4) /* Reference Selection bit 0 mask. */ -#define ADC_REFSEL0_bp 4 /* Reference Selection bit 0 position. */ -#define ADC_REFSEL1_bm (1<<5) /* Reference Selection bit 1 mask. */ -#define ADC_REFSEL1_bp 5 /* Reference Selection bit 1 position. */ -#define ADC_REFSEL2_bm (1<<6) /* Reference Selection bit 2 mask. */ -#define ADC_REFSEL2_bp 6 /* Reference Selection bit 2 position. */ - -#define ADC_BANDGAP_bm 0x02 /* Bandgap enable bit mask. */ -#define ADC_BANDGAP_bp 1 /* Bandgap enable bit position. */ - -#define ADC_TEMPREF_bm 0x01 /* Temperature Reference Enable bit mask. */ -#define ADC_TEMPREF_bp 0 /* Temperature Reference Enable bit position. */ - -/* ADC.EVCTRL bit masks and bit positions */ -#define ADC_SWEEP_gm 0xC0 /* Channel Sweep Selection group mask. */ -#define ADC_SWEEP_gp 6 /* Channel Sweep Selection group position. */ -#define ADC_SWEEP0_bm (1<<6) /* Channel Sweep Selection bit 0 mask. */ -#define ADC_SWEEP0_bp 6 /* Channel Sweep Selection bit 0 position. */ -#define ADC_SWEEP1_bm (1<<7) /* Channel Sweep Selection bit 1 mask. */ -#define ADC_SWEEP1_bp 7 /* Channel Sweep Selection bit 1 position. */ - -#define ADC_EVSEL_gm 0x38 /* Event Input Select group mask. */ -#define ADC_EVSEL_gp 3 /* Event Input Select group position. */ -#define ADC_EVSEL0_bm (1<<3) /* Event Input Select bit 0 mask. */ -#define ADC_EVSEL0_bp 3 /* Event Input Select bit 0 position. */ -#define ADC_EVSEL1_bm (1<<4) /* Event Input Select bit 1 mask. */ -#define ADC_EVSEL1_bp 4 /* Event Input Select bit 1 position. */ -#define ADC_EVSEL2_bm (1<<5) /* Event Input Select bit 2 mask. */ -#define ADC_EVSEL2_bp 5 /* Event Input Select bit 2 position. */ - -#define ADC_EVACT_gm 0x07 /* Event Action Select group mask. */ -#define ADC_EVACT_gp 0 /* Event Action Select group position. */ -#define ADC_EVACT0_bm (1<<0) /* Event Action Select bit 0 mask. */ -#define ADC_EVACT0_bp 0 /* Event Action Select bit 0 position. */ -#define ADC_EVACT1_bm (1<<1) /* Event Action Select bit 1 mask. */ -#define ADC_EVACT1_bp 1 /* Event Action Select bit 1 position. */ -#define ADC_EVACT2_bm (1<<2) /* Event Action Select bit 2 mask. */ -#define ADC_EVACT2_bp 2 /* Event Action Select bit 2 position. */ - -/* ADC.PRESCALER bit masks and bit positions */ -#define ADC_PRESCALER_gm 0x07 /* Clock Prescaler Selection group mask. */ -#define ADC_PRESCALER_gp 0 /* Clock Prescaler Selection group position. */ -#define ADC_PRESCALER0_bm (1<<0) /* Clock Prescaler Selection bit 0 mask. */ -#define ADC_PRESCALER0_bp 0 /* Clock Prescaler Selection bit 0 position. */ -#define ADC_PRESCALER1_bm (1<<1) /* Clock Prescaler Selection bit 1 mask. */ -#define ADC_PRESCALER1_bp 1 /* Clock Prescaler Selection bit 1 position. */ -#define ADC_PRESCALER2_bm (1<<2) /* Clock Prescaler Selection bit 2 mask. */ -#define ADC_PRESCALER2_bp 2 /* Clock Prescaler Selection bit 2 position. */ - -/* ADC.INTFLAGS bit masks and bit positions */ -#define ADC_CH3IF_bm 0x08 /* Channel 3 Interrupt Flag bit mask. */ -#define ADC_CH3IF_bp 3 /* Channel 3 Interrupt Flag bit position. */ - -#define ADC_CH2IF_bm 0x04 /* Channel 2 Interrupt Flag bit mask. */ -#define ADC_CH2IF_bp 2 /* Channel 2 Interrupt Flag bit position. */ - -#define ADC_CH1IF_bm 0x02 /* Channel 1 Interrupt Flag bit mask. */ -#define ADC_CH1IF_bp 1 /* Channel 1 Interrupt Flag bit position. */ - -#define ADC_CH0IF_bm 0x01 /* Channel 0 Interrupt Flag bit mask. */ -#define ADC_CH0IF_bp 0 /* Channel 0 Interrupt Flag bit position. */ - -/* DAC - Digital/Analog Converter */ -/* DAC.CTRLA bit masks and bit positions */ -#define DAC_IDOEN_bm 0x10 /* Internal Output Enable bit mask. */ -#define DAC_IDOEN_bp 4 /* Internal Output Enable bit position. */ - -#define DAC_CH1EN_bm 0x08 /* Channel 1 Output Enable bit mask. */ -#define DAC_CH1EN_bp 3 /* Channel 1 Output Enable bit position. */ - -#define DAC_CH0EN_bm 0x04 /* Channel 0 Output Enable bit mask. */ -#define DAC_CH0EN_bp 2 /* Channel 0 Output Enable bit position. */ - -#define DAC_LPMODE_bm 0x02 /* Low Power Mode bit mask. */ -#define DAC_LPMODE_bp 1 /* Low Power Mode bit position. */ - -#define DAC_ENABLE_bm 0x01 /* Enable bit mask. */ -#define DAC_ENABLE_bp 0 /* Enable bit position. */ - -/* DAC.CTRLB bit masks and bit positions */ -#define DAC_CHSEL_gm 0x60 /* Channel Select group mask. */ -#define DAC_CHSEL_gp 5 /* Channel Select group position. */ -#define DAC_CHSEL0_bm (1<<5) /* Channel Select bit 0 mask. */ -#define DAC_CHSEL0_bp 5 /* Channel Select bit 0 position. */ -#define DAC_CHSEL1_bm (1<<6) /* Channel Select bit 1 mask. */ -#define DAC_CHSEL1_bp 6 /* Channel Select bit 1 position. */ - -#define DAC_CH1TRIG_bm 0x02 /* Channel 1 Event Trig Enable bit mask. */ -#define DAC_CH1TRIG_bp 1 /* Channel 1 Event Trig Enable bit position. */ - -#define DAC_CH0TRIG_bm 0x01 /* Channel 0 Event Trig Enable bit mask. */ -#define DAC_CH0TRIG_bp 0 /* Channel 0 Event Trig Enable bit position. */ - -/* DAC.CTRLC bit masks and bit positions */ -#define DAC_REFSEL_gm 0x18 /* Reference Select group mask. */ -#define DAC_REFSEL_gp 3 /* Reference Select group position. */ -#define DAC_REFSEL0_bm (1<<3) /* Reference Select bit 0 mask. */ -#define DAC_REFSEL0_bp 3 /* Reference Select bit 0 position. */ -#define DAC_REFSEL1_bm (1<<4) /* Reference Select bit 1 mask. */ -#define DAC_REFSEL1_bp 4 /* Reference Select bit 1 position. */ - -#define DAC_LEFTADJ_bm 0x01 /* Left-adjust Result bit mask. */ -#define DAC_LEFTADJ_bp 0 /* Left-adjust Result bit position. */ - -/* DAC.EVCTRL bit masks and bit positions */ -#define DAC_EVSPLIT_bm 0x08 /* Separate Event Channel Input for Channel 1 bit mask. */ -#define DAC_EVSPLIT_bp 3 /* Separate Event Channel Input for Channel 1 bit position. */ - -#define DAC_EVSEL_gm 0x07 /* Event Input Selection group mask. */ -#define DAC_EVSEL_gp 0 /* Event Input Selection group position. */ -#define DAC_EVSEL0_bm (1<<0) /* Event Input Selection bit 0 mask. */ -#define DAC_EVSEL0_bp 0 /* Event Input Selection bit 0 position. */ -#define DAC_EVSEL1_bm (1<<1) /* Event Input Selection bit 1 mask. */ -#define DAC_EVSEL1_bp 1 /* Event Input Selection bit 1 position. */ -#define DAC_EVSEL2_bm (1<<2) /* Event Input Selection bit 2 mask. */ -#define DAC_EVSEL2_bp 2 /* Event Input Selection bit 2 position. */ - -/* DAC.STATUS bit masks and bit positions */ -#define DAC_CH1DRE_bm 0x02 /* Channel 1 Data Register Empty bit mask. */ -#define DAC_CH1DRE_bp 1 /* Channel 1 Data Register Empty bit position. */ - -#define DAC_CH0DRE_bm 0x01 /* Channel 0 Data Register Empty bit mask. */ -#define DAC_CH0DRE_bp 0 /* Channel 0 Data Register Empty bit position. */ - -/* DAC.CH0GAINCAL bit masks and bit positions */ -#define DAC_CH0GAINCAL_gm 0x7F /* Gain Calibration group mask. */ -#define DAC_CH0GAINCAL_gp 0 /* Gain Calibration group position. */ -#define DAC_CH0GAINCAL0_bm (1<<0) /* Gain Calibration bit 0 mask. */ -#define DAC_CH0GAINCAL0_bp 0 /* Gain Calibration bit 0 position. */ -#define DAC_CH0GAINCAL1_bm (1<<1) /* Gain Calibration bit 1 mask. */ -#define DAC_CH0GAINCAL1_bp 1 /* Gain Calibration bit 1 position. */ -#define DAC_CH0GAINCAL2_bm (1<<2) /* Gain Calibration bit 2 mask. */ -#define DAC_CH0GAINCAL2_bp 2 /* Gain Calibration bit 2 position. */ -#define DAC_CH0GAINCAL3_bm (1<<3) /* Gain Calibration bit 3 mask. */ -#define DAC_CH0GAINCAL3_bp 3 /* Gain Calibration bit 3 position. */ -#define DAC_CH0GAINCAL4_bm (1<<4) /* Gain Calibration bit 4 mask. */ -#define DAC_CH0GAINCAL4_bp 4 /* Gain Calibration bit 4 position. */ -#define DAC_CH0GAINCAL5_bm (1<<5) /* Gain Calibration bit 5 mask. */ -#define DAC_CH0GAINCAL5_bp 5 /* Gain Calibration bit 5 position. */ -#define DAC_CH0GAINCAL6_bm (1<<6) /* Gain Calibration bit 6 mask. */ -#define DAC_CH0GAINCAL6_bp 6 /* Gain Calibration bit 6 position. */ - -/* DAC.CH0OFFSETCAL bit masks and bit positions */ -#define DAC_CH0OFFSETCAL_gm 0x7F /* Offset Calibration group mask. */ -#define DAC_CH0OFFSETCAL_gp 0 /* Offset Calibration group position. */ -#define DAC_CH0OFFSETCAL0_bm (1<<0) /* Offset Calibration bit 0 mask. */ -#define DAC_CH0OFFSETCAL0_bp 0 /* Offset Calibration bit 0 position. */ -#define DAC_CH0OFFSETCAL1_bm (1<<1) /* Offset Calibration bit 1 mask. */ -#define DAC_CH0OFFSETCAL1_bp 1 /* Offset Calibration bit 1 position. */ -#define DAC_CH0OFFSETCAL2_bm (1<<2) /* Offset Calibration bit 2 mask. */ -#define DAC_CH0OFFSETCAL2_bp 2 /* Offset Calibration bit 2 position. */ -#define DAC_CH0OFFSETCAL3_bm (1<<3) /* Offset Calibration bit 3 mask. */ -#define DAC_CH0OFFSETCAL3_bp 3 /* Offset Calibration bit 3 position. */ -#define DAC_CH0OFFSETCAL4_bm (1<<4) /* Offset Calibration bit 4 mask. */ -#define DAC_CH0OFFSETCAL4_bp 4 /* Offset Calibration bit 4 position. */ -#define DAC_CH0OFFSETCAL5_bm (1<<5) /* Offset Calibration bit 5 mask. */ -#define DAC_CH0OFFSETCAL5_bp 5 /* Offset Calibration bit 5 position. */ -#define DAC_CH0OFFSETCAL6_bm (1<<6) /* Offset Calibration bit 6 mask. */ -#define DAC_CH0OFFSETCAL6_bp 6 /* Offset Calibration bit 6 position. */ - -/* DAC.CH1GAINCAL bit masks and bit positions */ -#define DAC_CH1GAINCAL_gm 0x7F /* Gain Calibration group mask. */ -#define DAC_CH1GAINCAL_gp 0 /* Gain Calibration group position. */ -#define DAC_CH1GAINCAL0_bm (1<<0) /* Gain Calibration bit 0 mask. */ -#define DAC_CH1GAINCAL0_bp 0 /* Gain Calibration bit 0 position. */ -#define DAC_CH1GAINCAL1_bm (1<<1) /* Gain Calibration bit 1 mask. */ -#define DAC_CH1GAINCAL1_bp 1 /* Gain Calibration bit 1 position. */ -#define DAC_CH1GAINCAL2_bm (1<<2) /* Gain Calibration bit 2 mask. */ -#define DAC_CH1GAINCAL2_bp 2 /* Gain Calibration bit 2 position. */ -#define DAC_CH1GAINCAL3_bm (1<<3) /* Gain Calibration bit 3 mask. */ -#define DAC_CH1GAINCAL3_bp 3 /* Gain Calibration bit 3 position. */ -#define DAC_CH1GAINCAL4_bm (1<<4) /* Gain Calibration bit 4 mask. */ -#define DAC_CH1GAINCAL4_bp 4 /* Gain Calibration bit 4 position. */ -#define DAC_CH1GAINCAL5_bm (1<<5) /* Gain Calibration bit 5 mask. */ -#define DAC_CH1GAINCAL5_bp 5 /* Gain Calibration bit 5 position. */ -#define DAC_CH1GAINCAL6_bm (1<<6) /* Gain Calibration bit 6 mask. */ -#define DAC_CH1GAINCAL6_bp 6 /* Gain Calibration bit 6 position. */ - -/* DAC.CH1OFFSETCAL bit masks and bit positions */ -#define DAC_CH1OFFSETCAL_gm 0x7F /* Offset Calibration group mask. */ -#define DAC_CH1OFFSETCAL_gp 0 /* Offset Calibration group position. */ -#define DAC_CH1OFFSETCAL0_bm (1<<0) /* Offset Calibration bit 0 mask. */ -#define DAC_CH1OFFSETCAL0_bp 0 /* Offset Calibration bit 0 position. */ -#define DAC_CH1OFFSETCAL1_bm (1<<1) /* Offset Calibration bit 1 mask. */ -#define DAC_CH1OFFSETCAL1_bp 1 /* Offset Calibration bit 1 position. */ -#define DAC_CH1OFFSETCAL2_bm (1<<2) /* Offset Calibration bit 2 mask. */ -#define DAC_CH1OFFSETCAL2_bp 2 /* Offset Calibration bit 2 position. */ -#define DAC_CH1OFFSETCAL3_bm (1<<3) /* Offset Calibration bit 3 mask. */ -#define DAC_CH1OFFSETCAL3_bp 3 /* Offset Calibration bit 3 position. */ -#define DAC_CH1OFFSETCAL4_bm (1<<4) /* Offset Calibration bit 4 mask. */ -#define DAC_CH1OFFSETCAL4_bp 4 /* Offset Calibration bit 4 position. */ -#define DAC_CH1OFFSETCAL5_bm (1<<5) /* Offset Calibration bit 5 mask. */ -#define DAC_CH1OFFSETCAL5_bp 5 /* Offset Calibration bit 5 position. */ -#define DAC_CH1OFFSETCAL6_bm (1<<6) /* Offset Calibration bit 6 mask. */ -#define DAC_CH1OFFSETCAL6_bp 6 /* Offset Calibration bit 6 position. */ - -/* AC - Analog Comparator */ -/* AC.AC0CTRL bit masks and bit positions */ -#define AC_INTMODE_gm 0xC0 /* Interrupt Mode group mask. */ -#define AC_INTMODE_gp 6 /* Interrupt Mode group position. */ -#define AC_INTMODE0_bm (1<<6) /* Interrupt Mode bit 0 mask. */ -#define AC_INTMODE0_bp 6 /* Interrupt Mode bit 0 position. */ -#define AC_INTMODE1_bm (1<<7) /* Interrupt Mode bit 1 mask. */ -#define AC_INTMODE1_bp 7 /* Interrupt Mode bit 1 position. */ - -#define AC_INTLVL_gm 0x30 /* Interrupt Level group mask. */ -#define AC_INTLVL_gp 4 /* Interrupt Level group position. */ -#define AC_INTLVL0_bm (1<<4) /* Interrupt Level bit 0 mask. */ -#define AC_INTLVL0_bp 4 /* Interrupt Level bit 0 position. */ -#define AC_INTLVL1_bm (1<<5) /* Interrupt Level bit 1 mask. */ -#define AC_INTLVL1_bp 5 /* Interrupt Level bit 1 position. */ - -#define AC_HSMODE_bm 0x08 /* High-speed Mode bit mask. */ -#define AC_HSMODE_bp 3 /* High-speed Mode bit position. */ - -#define AC_HYSMODE_gm 0x06 /* Hysteresis Mode group mask. */ -#define AC_HYSMODE_gp 1 /* Hysteresis Mode group position. */ -#define AC_HYSMODE0_bm (1<<1) /* Hysteresis Mode bit 0 mask. */ -#define AC_HYSMODE0_bp 1 /* Hysteresis Mode bit 0 position. */ -#define AC_HYSMODE1_bm (1<<2) /* Hysteresis Mode bit 1 mask. */ -#define AC_HYSMODE1_bp 2 /* Hysteresis Mode bit 1 position. */ - -#define AC_ENABLE_bm 0x01 /* Enable bit mask. */ -#define AC_ENABLE_bp 0 /* Enable bit position. */ - -/* AC.AC1CTRL bit masks and bit positions */ -/* AC_INTMODE Predefined. */ -/* AC_INTMODE Predefined. */ - -/* AC_INTLVL Predefined. */ -/* AC_INTLVL Predefined. */ - -/* AC_HSMODE Predefined. */ -/* AC_HSMODE Predefined. */ - -/* AC_HYSMODE Predefined. */ -/* AC_HYSMODE Predefined. */ - -/* AC_ENABLE Predefined. */ -/* AC_ENABLE Predefined. */ - -/* AC.AC0MUXCTRL bit masks and bit positions */ -#define AC_MUXPOS_gm 0x38 /* MUX Positive Input group mask. */ -#define AC_MUXPOS_gp 3 /* MUX Positive Input group position. */ -#define AC_MUXPOS0_bm (1<<3) /* MUX Positive Input bit 0 mask. */ -#define AC_MUXPOS0_bp 3 /* MUX Positive Input bit 0 position. */ -#define AC_MUXPOS1_bm (1<<4) /* MUX Positive Input bit 1 mask. */ -#define AC_MUXPOS1_bp 4 /* MUX Positive Input bit 1 position. */ -#define AC_MUXPOS2_bm (1<<5) /* MUX Positive Input bit 2 mask. */ -#define AC_MUXPOS2_bp 5 /* MUX Positive Input bit 2 position. */ - -#define AC_MUXNEG_gm 0x07 /* MUX Negative Input group mask. */ -#define AC_MUXNEG_gp 0 /* MUX Negative Input group position. */ -#define AC_MUXNEG0_bm (1<<0) /* MUX Negative Input bit 0 mask. */ -#define AC_MUXNEG0_bp 0 /* MUX Negative Input bit 0 position. */ -#define AC_MUXNEG1_bm (1<<1) /* MUX Negative Input bit 1 mask. */ -#define AC_MUXNEG1_bp 1 /* MUX Negative Input bit 1 position. */ -#define AC_MUXNEG2_bm (1<<2) /* MUX Negative Input bit 2 mask. */ -#define AC_MUXNEG2_bp 2 /* MUX Negative Input bit 2 position. */ - -/* AC.AC1MUXCTRL bit masks and bit positions */ -/* AC_MUXPOS Predefined. */ -/* AC_MUXPOS Predefined. */ - -/* AC_MUXNEG Predefined. */ -/* AC_MUXNEG Predefined. */ - -/* AC.CTRLA bit masks and bit positions */ -#define AC_AC1OUT_bm 0x02 /* Analog Comparator 1 Output Enable bit mask. */ -#define AC_AC1OUT_bp 1 /* Analog Comparator 1 Output Enable bit position. */ - -#define AC_AC0OUT_bm 0x01 /* Analog Comparator 0 Output Enable bit mask. */ -#define AC_AC0OUT_bp 0 /* Analog Comparator 0 Output Enable bit position. */ - -/* AC.CTRLB bit masks and bit positions */ -#define AC_SCALEFAC_gm 0x3F /* VCC Voltage Scaler Factor group mask. */ -#define AC_SCALEFAC_gp 0 /* VCC Voltage Scaler Factor group position. */ -#define AC_SCALEFAC0_bm (1<<0) /* VCC Voltage Scaler Factor bit 0 mask. */ -#define AC_SCALEFAC0_bp 0 /* VCC Voltage Scaler Factor bit 0 position. */ -#define AC_SCALEFAC1_bm (1<<1) /* VCC Voltage Scaler Factor bit 1 mask. */ -#define AC_SCALEFAC1_bp 1 /* VCC Voltage Scaler Factor bit 1 position. */ -#define AC_SCALEFAC2_bm (1<<2) /* VCC Voltage Scaler Factor bit 2 mask. */ -#define AC_SCALEFAC2_bp 2 /* VCC Voltage Scaler Factor bit 2 position. */ -#define AC_SCALEFAC3_bm (1<<3) /* VCC Voltage Scaler Factor bit 3 mask. */ -#define AC_SCALEFAC3_bp 3 /* VCC Voltage Scaler Factor bit 3 position. */ -#define AC_SCALEFAC4_bm (1<<4) /* VCC Voltage Scaler Factor bit 4 mask. */ -#define AC_SCALEFAC4_bp 4 /* VCC Voltage Scaler Factor bit 4 position. */ -#define AC_SCALEFAC5_bm (1<<5) /* VCC Voltage Scaler Factor bit 5 mask. */ -#define AC_SCALEFAC5_bp 5 /* VCC Voltage Scaler Factor bit 5 position. */ - -/* AC.WINCTRL bit masks and bit positions */ -#define AC_WEN_bm 0x10 /* Window Mode Enable bit mask. */ -#define AC_WEN_bp 4 /* Window Mode Enable bit position. */ - -#define AC_WINTMODE_gm 0x0C /* Window Interrupt Mode group mask. */ -#define AC_WINTMODE_gp 2 /* Window Interrupt Mode group position. */ -#define AC_WINTMODE0_bm (1<<2) /* Window Interrupt Mode bit 0 mask. */ -#define AC_WINTMODE0_bp 2 /* Window Interrupt Mode bit 0 position. */ -#define AC_WINTMODE1_bm (1<<3) /* Window Interrupt Mode bit 1 mask. */ -#define AC_WINTMODE1_bp 3 /* Window Interrupt Mode bit 1 position. */ - -#define AC_WINTLVL_gm 0x03 /* Window Interrupt Level group mask. */ -#define AC_WINTLVL_gp 0 /* Window Interrupt Level group position. */ -#define AC_WINTLVL0_bm (1<<0) /* Window Interrupt Level bit 0 mask. */ -#define AC_WINTLVL0_bp 0 /* Window Interrupt Level bit 0 position. */ -#define AC_WINTLVL1_bm (1<<1) /* Window Interrupt Level bit 1 mask. */ -#define AC_WINTLVL1_bp 1 /* Window Interrupt Level bit 1 position. */ - -/* AC.STATUS bit masks and bit positions */ -#define AC_WSTATE_gm 0xC0 /* Window Mode State group mask. */ -#define AC_WSTATE_gp 6 /* Window Mode State group position. */ -#define AC_WSTATE0_bm (1<<6) /* Window Mode State bit 0 mask. */ -#define AC_WSTATE0_bp 6 /* Window Mode State bit 0 position. */ -#define AC_WSTATE1_bm (1<<7) /* Window Mode State bit 1 mask. */ -#define AC_WSTATE1_bp 7 /* Window Mode State bit 1 position. */ - -#define AC_AC1STATE_bm 0x20 /* Analog Comparator 1 State bit mask. */ -#define AC_AC1STATE_bp 5 /* Analog Comparator 1 State bit position. */ - -#define AC_AC0STATE_bm 0x10 /* Analog Comparator 0 State bit mask. */ -#define AC_AC0STATE_bp 4 /* Analog Comparator 0 State bit position. */ - -#define AC_WIF_bm 0x04 /* Window Mode Interrupt Flag bit mask. */ -#define AC_WIF_bp 2 /* Window Mode Interrupt Flag bit position. */ - -#define AC_AC1IF_bm 0x02 /* Analog Comparator 1 Interrupt Flag bit mask. */ -#define AC_AC1IF_bp 1 /* Analog Comparator 1 Interrupt Flag bit position. */ - -#define AC_AC0IF_bm 0x01 /* Analog Comparator 0 Interrupt Flag bit mask. */ -#define AC_AC0IF_bp 0 /* Analog Comparator 0 Interrupt Flag bit position. */ - -/* RTC - Real-Time Counter */ -/* RTC.CTRL bit masks and bit positions */ -#define RTC_PRESCALER_gm 0x07 /* Prescaling Factor group mask. */ -#define RTC_PRESCALER_gp 0 /* Prescaling Factor group position. */ -#define RTC_PRESCALER0_bm (1<<0) /* Prescaling Factor bit 0 mask. */ -#define RTC_PRESCALER0_bp 0 /* Prescaling Factor bit 0 position. */ -#define RTC_PRESCALER1_bm (1<<1) /* Prescaling Factor bit 1 mask. */ -#define RTC_PRESCALER1_bp 1 /* Prescaling Factor bit 1 position. */ -#define RTC_PRESCALER2_bm (1<<2) /* Prescaling Factor bit 2 mask. */ -#define RTC_PRESCALER2_bp 2 /* Prescaling Factor bit 2 position. */ - -/* RTC.STATUS bit masks and bit positions */ -#define RTC_SYNCBUSY_bm 0x01 /* Synchronization Busy Flag bit mask. */ -#define RTC_SYNCBUSY_bp 0 /* Synchronization Busy Flag bit position. */ - -/* RTC.INTCTRL bit masks and bit positions */ -#define RTC_COMPINTLVL_gm 0x0C /* Compare Match Interrupt Level group mask. */ -#define RTC_COMPINTLVL_gp 2 /* Compare Match Interrupt Level group position. */ -#define RTC_COMPINTLVL0_bm (1<<2) /* Compare Match Interrupt Level bit 0 mask. */ -#define RTC_COMPINTLVL0_bp 2 /* Compare Match Interrupt Level bit 0 position. */ -#define RTC_COMPINTLVL1_bm (1<<3) /* Compare Match Interrupt Level bit 1 mask. */ -#define RTC_COMPINTLVL1_bp 3 /* Compare Match Interrupt Level bit 1 position. */ - -#define RTC_OVFINTLVL_gm 0x03 /* Overflow Interrupt Level group mask. */ -#define RTC_OVFINTLVL_gp 0 /* Overflow Interrupt Level group position. */ -#define RTC_OVFINTLVL0_bm (1<<0) /* Overflow Interrupt Level bit 0 mask. */ -#define RTC_OVFINTLVL0_bp 0 /* Overflow Interrupt Level bit 0 position. */ -#define RTC_OVFINTLVL1_bm (1<<1) /* Overflow Interrupt Level bit 1 mask. */ -#define RTC_OVFINTLVL1_bp 1 /* Overflow Interrupt Level bit 1 position. */ - -/* RTC.INTFLAGS bit masks and bit positions */ -#define RTC_COMPIF_bm 0x02 /* Compare Match Interrupt Flag bit mask. */ -#define RTC_COMPIF_bp 1 /* Compare Match Interrupt Flag bit position. */ - -#define RTC_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ -#define RTC_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ - -/* EBI - External Bus Interface */ -/* EBI_CS.CTRLA bit masks and bit positions */ -#define EBI_CS_ASPACE_gm 0x7C /* Address Space group mask. */ -#define EBI_CS_ASPACE_gp 2 /* Address Space group position. */ -#define EBI_CS_ASPACE0_bm (1<<2) /* Address Space bit 0 mask. */ -#define EBI_CS_ASPACE0_bp 2 /* Address Space bit 0 position. */ -#define EBI_CS_ASPACE1_bm (1<<3) /* Address Space bit 1 mask. */ -#define EBI_CS_ASPACE1_bp 3 /* Address Space bit 1 position. */ -#define EBI_CS_ASPACE2_bm (1<<4) /* Address Space bit 2 mask. */ -#define EBI_CS_ASPACE2_bp 4 /* Address Space bit 2 position. */ -#define EBI_CS_ASPACE3_bm (1<<5) /* Address Space bit 3 mask. */ -#define EBI_CS_ASPACE3_bp 5 /* Address Space bit 3 position. */ -#define EBI_CS_ASPACE4_bm (1<<6) /* Address Space bit 4 mask. */ -#define EBI_CS_ASPACE4_bp 6 /* Address Space bit 4 position. */ - -#define EBI_CS_MODE_gm 0x03 /* Memory Mode group mask. */ -#define EBI_CS_MODE_gp 0 /* Memory Mode group position. */ -#define EBI_CS_MODE0_bm (1<<0) /* Memory Mode bit 0 mask. */ -#define EBI_CS_MODE0_bp 0 /* Memory Mode bit 0 position. */ -#define EBI_CS_MODE1_bm (1<<1) /* Memory Mode bit 1 mask. */ -#define EBI_CS_MODE1_bp 1 /* Memory Mode bit 1 position. */ - -/* EBI_CS.CTRLB bit masks and bit positions */ -#define EBI_CS_SRWS_gm 0x07 /* SRAM Wait State Cycles group mask. */ -#define EBI_CS_SRWS_gp 0 /* SRAM Wait State Cycles group position. */ -#define EBI_CS_SRWS0_bm (1<<0) /* SRAM Wait State Cycles bit 0 mask. */ -#define EBI_CS_SRWS0_bp 0 /* SRAM Wait State Cycles bit 0 position. */ -#define EBI_CS_SRWS1_bm (1<<1) /* SRAM Wait State Cycles bit 1 mask. */ -#define EBI_CS_SRWS1_bp 1 /* SRAM Wait State Cycles bit 1 position. */ -#define EBI_CS_SRWS2_bm (1<<2) /* SRAM Wait State Cycles bit 2 mask. */ -#define EBI_CS_SRWS2_bp 2 /* SRAM Wait State Cycles bit 2 position. */ - -#define EBI_CS_SDINITDONE_bm 0x80 /* SDRAM Initialization Done bit mask. */ -#define EBI_CS_SDINITDONE_bp 7 /* SDRAM Initialization Done bit position. */ - -#define EBI_CS_SDSREN_bm 0x04 /* SDRAM Self-refresh Enable bit mask. */ -#define EBI_CS_SDSREN_bp 2 /* SDRAM Self-refresh Enable bit position. */ - -#define EBI_CS_SDMODE_gm 0x03 /* SDRAM Mode group mask. */ -#define EBI_CS_SDMODE_gp 0 /* SDRAM Mode group position. */ -#define EBI_CS_SDMODE0_bm (1<<0) /* SDRAM Mode bit 0 mask. */ -#define EBI_CS_SDMODE0_bp 0 /* SDRAM Mode bit 0 position. */ -#define EBI_CS_SDMODE1_bm (1<<1) /* SDRAM Mode bit 1 mask. */ -#define EBI_CS_SDMODE1_bp 1 /* SDRAM Mode bit 1 position. */ - -/* EBI.CTRL bit masks and bit positions */ -#define EBI_SDDATAW_gm 0xC0 /* SDRAM Data Width Setting group mask. */ -#define EBI_SDDATAW_gp 6 /* SDRAM Data Width Setting group position. */ -#define EBI_SDDATAW0_bm (1<<6) /* SDRAM Data Width Setting bit 0 mask. */ -#define EBI_SDDATAW0_bp 6 /* SDRAM Data Width Setting bit 0 position. */ -#define EBI_SDDATAW1_bm (1<<7) /* SDRAM Data Width Setting bit 1 mask. */ -#define EBI_SDDATAW1_bp 7 /* SDRAM Data Width Setting bit 1 position. */ - -#define EBI_LPCMODE_gm 0x30 /* SRAM LPC Mode group mask. */ -#define EBI_LPCMODE_gp 4 /* SRAM LPC Mode group position. */ -#define EBI_LPCMODE0_bm (1<<4) /* SRAM LPC Mode bit 0 mask. */ -#define EBI_LPCMODE0_bp 4 /* SRAM LPC Mode bit 0 position. */ -#define EBI_LPCMODE1_bm (1<<5) /* SRAM LPC Mode bit 1 mask. */ -#define EBI_LPCMODE1_bp 5 /* SRAM LPC Mode bit 1 position. */ - -#define EBI_SRMODE_gm 0x0C /* SRAM Mode group mask. */ -#define EBI_SRMODE_gp 2 /* SRAM Mode group position. */ -#define EBI_SRMODE0_bm (1<<2) /* SRAM Mode bit 0 mask. */ -#define EBI_SRMODE0_bp 2 /* SRAM Mode bit 0 position. */ -#define EBI_SRMODE1_bm (1<<3) /* SRAM Mode bit 1 mask. */ -#define EBI_SRMODE1_bp 3 /* SRAM Mode bit 1 position. */ - -#define EBI_IFMODE_gm 0x03 /* Interface Mode group mask. */ -#define EBI_IFMODE_gp 0 /* Interface Mode group position. */ -#define EBI_IFMODE0_bm (1<<0) /* Interface Mode bit 0 mask. */ -#define EBI_IFMODE0_bp 0 /* Interface Mode bit 0 position. */ -#define EBI_IFMODE1_bm (1<<1) /* Interface Mode bit 1 mask. */ -#define EBI_IFMODE1_bp 1 /* Interface Mode bit 1 position. */ - -/* EBI.SDRAMCTRLA bit masks and bit positions */ -#define EBI_SDCAS_bm 0x08 /* SDRAM CAS Latency Setting bit mask. */ -#define EBI_SDCAS_bp 3 /* SDRAM CAS Latency Setting bit position. */ - -#define EBI_SDROW_bm 0x04 /* SDRAM ROW Bits Setting bit mask. */ -#define EBI_SDROW_bp 2 /* SDRAM ROW Bits Setting bit position. */ - -#define EBI_SDCOL_gm 0x03 /* SDRAM Column Bits Setting group mask. */ -#define EBI_SDCOL_gp 0 /* SDRAM Column Bits Setting group position. */ -#define EBI_SDCOL0_bm (1<<0) /* SDRAM Column Bits Setting bit 0 mask. */ -#define EBI_SDCOL0_bp 0 /* SDRAM Column Bits Setting bit 0 position. */ -#define EBI_SDCOL1_bm (1<<1) /* SDRAM Column Bits Setting bit 1 mask. */ -#define EBI_SDCOL1_bp 1 /* SDRAM Column Bits Setting bit 1 position. */ - -/* EBI.SDRAMCTRLB bit masks and bit positions */ -#define EBI_MRDLY_gm 0xC0 /* SDRAM Mode Register Delay group mask. */ -#define EBI_MRDLY_gp 6 /* SDRAM Mode Register Delay group position. */ -#define EBI_MRDLY0_bm (1<<6) /* SDRAM Mode Register Delay bit 0 mask. */ -#define EBI_MRDLY0_bp 6 /* SDRAM Mode Register Delay bit 0 position. */ -#define EBI_MRDLY1_bm (1<<7) /* SDRAM Mode Register Delay bit 1 mask. */ -#define EBI_MRDLY1_bp 7 /* SDRAM Mode Register Delay bit 1 position. */ - -#define EBI_ROWCYCDLY_gm 0x38 /* SDRAM Row Cycle Delay group mask. */ -#define EBI_ROWCYCDLY_gp 3 /* SDRAM Row Cycle Delay group position. */ -#define EBI_ROWCYCDLY0_bm (1<<3) /* SDRAM Row Cycle Delay bit 0 mask. */ -#define EBI_ROWCYCDLY0_bp 3 /* SDRAM Row Cycle Delay bit 0 position. */ -#define EBI_ROWCYCDLY1_bm (1<<4) /* SDRAM Row Cycle Delay bit 1 mask. */ -#define EBI_ROWCYCDLY1_bp 4 /* SDRAM Row Cycle Delay bit 1 position. */ -#define EBI_ROWCYCDLY2_bm (1<<5) /* SDRAM Row Cycle Delay bit 2 mask. */ -#define EBI_ROWCYCDLY2_bp 5 /* SDRAM Row Cycle Delay bit 2 position. */ - -#define EBI_RPDLY_gm 0x07 /* SDRAM Row-to-Precharge Delay group mask. */ -#define EBI_RPDLY_gp 0 /* SDRAM Row-to-Precharge Delay group position. */ -#define EBI_RPDLY0_bm (1<<0) /* SDRAM Row-to-Precharge Delay bit 0 mask. */ -#define EBI_RPDLY0_bp 0 /* SDRAM Row-to-Precharge Delay bit 0 position. */ -#define EBI_RPDLY1_bm (1<<1) /* SDRAM Row-to-Precharge Delay bit 1 mask. */ -#define EBI_RPDLY1_bp 1 /* SDRAM Row-to-Precharge Delay bit 1 position. */ -#define EBI_RPDLY2_bm (1<<2) /* SDRAM Row-to-Precharge Delay bit 2 mask. */ -#define EBI_RPDLY2_bp 2 /* SDRAM Row-to-Precharge Delay bit 2 position. */ - -/* EBI.SDRAMCTRLC bit masks and bit positions */ -#define EBI_WRDLY_gm 0xC0 /* SDRAM Write Recovery Delay group mask. */ -#define EBI_WRDLY_gp 6 /* SDRAM Write Recovery Delay group position. */ -#define EBI_WRDLY0_bm (1<<6) /* SDRAM Write Recovery Delay bit 0 mask. */ -#define EBI_WRDLY0_bp 6 /* SDRAM Write Recovery Delay bit 0 position. */ -#define EBI_WRDLY1_bm (1<<7) /* SDRAM Write Recovery Delay bit 1 mask. */ -#define EBI_WRDLY1_bp 7 /* SDRAM Write Recovery Delay bit 1 position. */ - -#define EBI_ESRDLY_gm 0x38 /* SDRAM Exit-Self-refresh-to-Active Delay group mask. */ -#define EBI_ESRDLY_gp 3 /* SDRAM Exit-Self-refresh-to-Active Delay group position. */ -#define EBI_ESRDLY0_bm (1<<3) /* SDRAM Exit-Self-refresh-to-Active Delay bit 0 mask. */ -#define EBI_ESRDLY0_bp 3 /* SDRAM Exit-Self-refresh-to-Active Delay bit 0 position. */ -#define EBI_ESRDLY1_bm (1<<4) /* SDRAM Exit-Self-refresh-to-Active Delay bit 1 mask. */ -#define EBI_ESRDLY1_bp 4 /* SDRAM Exit-Self-refresh-to-Active Delay bit 1 position. */ -#define EBI_ESRDLY2_bm (1<<5) /* SDRAM Exit-Self-refresh-to-Active Delay bit 2 mask. */ -#define EBI_ESRDLY2_bp 5 /* SDRAM Exit-Self-refresh-to-Active Delay bit 2 position. */ - -#define EBI_ROWCOLDLY_gm 0x07 /* SDRAM Row-to-Column Delay group mask. */ -#define EBI_ROWCOLDLY_gp 0 /* SDRAM Row-to-Column Delay group position. */ -#define EBI_ROWCOLDLY0_bm (1<<0) /* SDRAM Row-to-Column Delay bit 0 mask. */ -#define EBI_ROWCOLDLY0_bp 0 /* SDRAM Row-to-Column Delay bit 0 position. */ -#define EBI_ROWCOLDLY1_bm (1<<1) /* SDRAM Row-to-Column Delay bit 1 mask. */ -#define EBI_ROWCOLDLY1_bp 1 /* SDRAM Row-to-Column Delay bit 1 position. */ -#define EBI_ROWCOLDLY2_bm (1<<2) /* SDRAM Row-to-Column Delay bit 2 mask. */ -#define EBI_ROWCOLDLY2_bp 2 /* SDRAM Row-to-Column Delay bit 2 position. */ - -/* TWI - Two-Wire Interface */ -/* TWI_MASTER.CTRLA bit masks and bit positions */ -#define TWI_MASTER_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ -#define TWI_MASTER_INTLVL_gp 6 /* Interrupt Level group position. */ -#define TWI_MASTER_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ -#define TWI_MASTER_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ -#define TWI_MASTER_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ -#define TWI_MASTER_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ - -#define TWI_MASTER_RIEN_bm 0x20 /* Read Interrupt Enable bit mask. */ -#define TWI_MASTER_RIEN_bp 5 /* Read Interrupt Enable bit position. */ - -#define TWI_MASTER_WIEN_bm 0x10 /* Write Interrupt Enable bit mask. */ -#define TWI_MASTER_WIEN_bp 4 /* Write Interrupt Enable bit position. */ - -#define TWI_MASTER_ENABLE_bm 0x08 /* Enable TWI Master bit mask. */ -#define TWI_MASTER_ENABLE_bp 3 /* Enable TWI Master bit position. */ - -/* TWI_MASTER.CTRLB bit masks and bit positions */ -#define TWI_MASTER_TIMEOUT_gm 0x0C /* Inactive Bus Tisdahmeout group mask. */ -#define TWI_MASTER_TIMEOUT_gp 2 /* Inactive Bus Tisdahmeout group position. */ -#define TWI_MASTER_TIMEOUT0_bm (1<<2) /* Inactive Bus Tisdahmeout bit 0 mask. */ -#define TWI_MASTER_TIMEOUT0_bp 2 /* Inactive Bus Tisdahmeout bit 0 position. */ -#define TWI_MASTER_TIMEOUT1_bm (1<<3) /* Inactive Bus Tisdahmeout bit 1 mask. */ -#define TWI_MASTER_TIMEOUT1_bp 3 /* Inactive Bus Tisdahmeout bit 1 position. */ - -#define TWI_MASTER_QCEN_bm 0x02 /* Quick Command Enable bit mask. */ -#define TWI_MASTER_QCEN_bp 1 /* Quick Command Enable bit position. */ - -#define TWI_MASTER_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ -#define TWI_MASTER_SMEN_bp 0 /* Smart Mode Enable bit position. */ - -/* TWI_MASTER.CTRLC bit masks and bit positions */ -#define TWI_MASTER_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ -#define TWI_MASTER_ACKACT_bp 2 /* Acknowledge Action bit position. */ - -#define TWI_MASTER_CMD_gm 0x03 /* Command group mask. */ -#define TWI_MASTER_CMD_gp 0 /* Command group position. */ -#define TWI_MASTER_CMD0_bm (1<<0) /* Command bit 0 mask. */ -#define TWI_MASTER_CMD0_bp 0 /* Command bit 0 position. */ -#define TWI_MASTER_CMD1_bm (1<<1) /* Command bit 1 mask. */ -#define TWI_MASTER_CMD1_bp 1 /* Command bit 1 position. */ - -/* TWI_MASTER.STATUS bit masks and bit positions */ -#define TWI_MASTER_RIF_bm 0x80 /* Read Interrupt Flag bit mask. */ -#define TWI_MASTER_RIF_bp 7 /* Read Interrupt Flag bit position. */ - -#define TWI_MASTER_WIF_bm 0x40 /* Write Interrupt Flag bit mask. */ -#define TWI_MASTER_WIF_bp 6 /* Write Interrupt Flag bit position. */ - -#define TWI_MASTER_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ -#define TWI_MASTER_CLKHOLD_bp 5 /* Clock Hold bit position. */ - -#define TWI_MASTER_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ -#define TWI_MASTER_RXACK_bp 4 /* Received Acknowledge bit position. */ - -#define TWI_MASTER_ARBLOST_bm 0x08 /* Arbitration Lost bit mask. */ -#define TWI_MASTER_ARBLOST_bp 3 /* Arbitration Lost bit position. */ - -#define TWI_MASTER_BUSERR_bm 0x04 /* Bus Error bit mask. */ -#define TWI_MASTER_BUSERR_bp 2 /* Bus Error bit position. */ - -#define TWI_MASTER_BUSSTATE_gm 0x03 /* Bus State group mask. */ -#define TWI_MASTER_BUSSTATE_gp 0 /* Bus State group position. */ -#define TWI_MASTER_BUSSTATE0_bm (1<<0) /* Bus State bit 0 mask. */ -#define TWI_MASTER_BUSSTATE0_bp 0 /* Bus State bit 0 position. */ -#define TWI_MASTER_BUSSTATE1_bm (1<<1) /* Bus State bit 1 mask. */ -#define TWI_MASTER_BUSSTATE1_bp 1 /* Bus State bit 1 position. */ - -/* TWI_SLAVE.CTRLA bit masks and bit positions */ -#define TWI_SLAVE_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ -#define TWI_SLAVE_INTLVL_gp 6 /* Interrupt Level group position. */ -#define TWI_SLAVE_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ -#define TWI_SLAVE_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ -#define TWI_SLAVE_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ -#define TWI_SLAVE_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ - -#define TWI_SLAVE_DIEN_bm 0x20 /* Data Interrupt Enable bit mask. */ -#define TWI_SLAVE_DIEN_bp 5 /* Data Interrupt Enable bit position. */ - -#define TWI_SLAVE_APIEN_bm 0x10 /* Address/Stop Interrupt Enable bit mask. */ -#define TWI_SLAVE_APIEN_bp 4 /* Address/Stop Interrupt Enable bit position. */ - -#define TWI_SLAVE_ENABLE_bm 0x08 /* Enable TWI Slave bit mask. */ -#define TWI_SLAVE_ENABLE_bp 3 /* Enable TWI Slave bit position. */ - -#define TWI_SLAVE_PIEN_bm 0x04 /* Stop Interrupt Enable bit mask. */ -#define TWI_SLAVE_PIEN_bp 2 /* Stop Interrupt Enable bit position. */ - -#define TWI_SLAVE_PMEN_bm 0x02 /* Promiscuous Mode Enable bit mask. */ -#define TWI_SLAVE_PMEN_bp 1 /* Promiscuous Mode Enable bit position. */ - -#define TWI_SLAVE_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ -#define TWI_SLAVE_SMEN_bp 0 /* Smart Mode Enable bit position. */ - -/* TWI_SLAVE.CTRLB bit masks and bit positions */ -#define TWI_SLAVE_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ -#define TWI_SLAVE_ACKACT_bp 2 /* Acknowledge Action bit position. */ - -#define TWI_SLAVE_CMD_gm 0x03 /* Command group mask. */ -#define TWI_SLAVE_CMD_gp 0 /* Command group position. */ -#define TWI_SLAVE_CMD0_bm (1<<0) /* Command bit 0 mask. */ -#define TWI_SLAVE_CMD0_bp 0 /* Command bit 0 position. */ -#define TWI_SLAVE_CMD1_bm (1<<1) /* Command bit 1 mask. */ -#define TWI_SLAVE_CMD1_bp 1 /* Command bit 1 position. */ - -/* TWI_SLAVE.STATUS bit masks and bit positions */ -#define TWI_SLAVE_DIF_bm 0x80 /* Data Interrupt Flag bit mask. */ -#define TWI_SLAVE_DIF_bp 7 /* Data Interrupt Flag bit position. */ - -#define TWI_SLAVE_APIF_bm 0x40 /* Address/Stop Interrupt Flag bit mask. */ -#define TWI_SLAVE_APIF_bp 6 /* Address/Stop Interrupt Flag bit position. */ - -#define TWI_SLAVE_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ -#define TWI_SLAVE_CLKHOLD_bp 5 /* Clock Hold bit position. */ - -#define TWI_SLAVE_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ -#define TWI_SLAVE_RXACK_bp 4 /* Received Acknowledge bit position. */ - -#define TWI_SLAVE_COLL_bm 0x08 /* Collision bit mask. */ -#define TWI_SLAVE_COLL_bp 3 /* Collision bit position. */ - -#define TWI_SLAVE_BUSERR_bm 0x04 /* Bus Error bit mask. */ -#define TWI_SLAVE_BUSERR_bp 2 /* Bus Error bit position. */ - -#define TWI_SLAVE_DIR_bm 0x02 /* Read/Write Direction bit mask. */ -#define TWI_SLAVE_DIR_bp 1 /* Read/Write Direction bit position. */ - -#define TWI_SLAVE_AP_bm 0x01 /* Slave Address or Stop bit mask. */ -#define TWI_SLAVE_AP_bp 0 /* Slave Address or Stop bit position. */ - -/* TWI_SLAVE.ADDRMASK bit masks and bit positions */ -#define TWI_SLAVE_ADDRMASK_gm 0xFE /* Address Mask group mask. */ -#define TWI_SLAVE_ADDRMASK_gp 1 /* Address Mask group position. */ -#define TWI_SLAVE_ADDRMASK0_bm (1<<1) /* Address Mask bit 0 mask. */ -#define TWI_SLAVE_ADDRMASK0_bp 1 /* Address Mask bit 0 position. */ -#define TWI_SLAVE_ADDRMASK1_bm (1<<2) /* Address Mask bit 1 mask. */ -#define TWI_SLAVE_ADDRMASK1_bp 2 /* Address Mask bit 1 position. */ -#define TWI_SLAVE_ADDRMASK2_bm (1<<3) /* Address Mask bit 2 mask. */ -#define TWI_SLAVE_ADDRMASK2_bp 3 /* Address Mask bit 2 position. */ -#define TWI_SLAVE_ADDRMASK3_bm (1<<4) /* Address Mask bit 3 mask. */ -#define TWI_SLAVE_ADDRMASK3_bp 4 /* Address Mask bit 3 position. */ -#define TWI_SLAVE_ADDRMASK4_bm (1<<5) /* Address Mask bit 4 mask. */ -#define TWI_SLAVE_ADDRMASK4_bp 5 /* Address Mask bit 4 position. */ -#define TWI_SLAVE_ADDRMASK5_bm (1<<6) /* Address Mask bit 5 mask. */ -#define TWI_SLAVE_ADDRMASK5_bp 6 /* Address Mask bit 5 position. */ -#define TWI_SLAVE_ADDRMASK6_bm (1<<7) /* Address Mask bit 6 mask. */ -#define TWI_SLAVE_ADDRMASK6_bp 7 /* Address Mask bit 6 position. */ - -#define TWI_SLAVE_ADDREN_bm 0x01 /* Address Enable bit mask. */ -#define TWI_SLAVE_ADDREN_bp 0 /* Address Enable bit position. */ - -/* TWI.CTRL bit masks and bit positions */ -#define TWI_SDAHOLD_gm 0x06 /* SDA Hold Time Enable group mask. */ -#define TWI_SDAHOLD_gp 1 /* SDA Hold Time Enable group position. */ -#define TWI_SDAHOLD0_bm (1<<1) /* SDA Hold Time Enable bit 0 mask. */ -#define TWI_SDAHOLD0_bp 1 /* SDA Hold Time Enable bit 0 position. */ -#define TWI_SDAHOLD1_bm (1<<2) /* SDA Hold Time Enable bit 1 mask. */ -#define TWI_SDAHOLD1_bp 2 /* SDA Hold Time Enable bit 1 position. */ - -#define TWI_EDIEN_bm 0x01 /* External Driver Interface Enable bit mask. */ -#define TWI_EDIEN_bp 0 /* External Driver Interface Enable bit position. */ - -/* USB - USB */ -/* USB_EP.STATUS bit masks and bit positions */ -#define USB_EP_STALLF_bm 0x80 /* Endpoint Stall Flag bit mask. */ -#define USB_EP_STALLF_bp 7 /* Endpoint Stall Flag bit position. */ - -#define USB_EP_CRC_bm 0x80 /* CRC Error Flag bit mask. */ -#define USB_EP_CRC_bp 7 /* CRC Error Flag bit position. */ - -#define USB_EP_UNF_bm 0x40 /* Underflow Enpoint FLag bit mask. */ -#define USB_EP_UNF_bp 6 /* Underflow Enpoint FLag bit position. */ - -#define USB_EP_OVF_bm 0x40 /* Overflow Enpoint Flag for Output Endpoints bit mask. */ -#define USB_EP_OVF_bp 6 /* Overflow Enpoint Flag for Output Endpoints bit position. */ - -#define USB_EP_TRNCOMPL0_bm 0x20 /* Transaction Complete 0 Flag bit mask. */ -#define USB_EP_TRNCOMPL0_bp 5 /* Transaction Complete 0 Flag bit position. */ - -#define USB_EP_TRNCOMPL1_bm 0x10 /* Transaction Complete 1 Flag bit mask. */ -#define USB_EP_TRNCOMPL1_bp 4 /* Transaction Complete 1 Flag bit position. */ - -#define USB_EP_SETUP_bm 0x10 /* SETUP Transaction Complete Flag bit mask. */ -#define USB_EP_SETUP_bp 4 /* SETUP Transaction Complete Flag bit position. */ - -#define USB_EP_BANK_bm 0x08 /* Bank Select bit mask. */ -#define USB_EP_BANK_bp 3 /* Bank Select bit position. */ - -#define USB_EP_BUSNACK1_bm 0x04 /* Data Buffer 1 Not Acknowledge bit mask. */ -#define USB_EP_BUSNACK1_bp 2 /* Data Buffer 1 Not Acknowledge bit position. */ - -#define USB_EP_BUSNACK0_bm 0x02 /* Data Buffer 0 Not Acknowledge bit mask. */ -#define USB_EP_BUSNACK0_bp 1 /* Data Buffer 0 Not Acknowledge bit position. */ - -#define USB_EP_TOGGLE_bm 0x01 /* Data Toggle bit mask. */ -#define USB_EP_TOGGLE_bp 0 /* Data Toggle bit position. */ - -/* USB_EP.CTRL bit masks and bit positions */ -#define USB_EP_TYPE_gm 0xC0 /* Endpoint Type group mask. */ -#define USB_EP_TYPE_gp 6 /* Endpoint Type group position. */ -#define USB_EP_TYPE0_bm (1<<6) /* Endpoint Type bit 0 mask. */ -#define USB_EP_TYPE0_bp 6 /* Endpoint Type bit 0 position. */ -#define USB_EP_TYPE1_bm (1<<7) /* Endpoint Type bit 1 mask. */ -#define USB_EP_TYPE1_bp 7 /* Endpoint Type bit 1 position. */ - -#define USB_EP_MULTIPKT_bm 0x20 /* Multi Packet Transfer Enable bit mask. */ -#define USB_EP_MULTIPKT_bp 5 /* Multi Packet Transfer Enable bit position. */ - -#define USB_EP_PINGPONG_bm 0x10 /* Ping-Pong Enable bit mask. */ -#define USB_EP_PINGPONG_bp 4 /* Ping-Pong Enable bit position. */ - -#define USB_EP_INTDSBL_bm 0x08 /* Interrupt Disable bit mask. */ -#define USB_EP_INTDSBL_bp 3 /* Interrupt Disable bit position. */ - -#define USB_EP_STALL_bm 0x04 /* Data Stall bit mask. */ -#define USB_EP_STALL_bp 2 /* Data Stall bit position. */ - -#define USB_EP_BUFSIZE_gm 0x07 /* Data Buffer Size group mask. */ -#define USB_EP_BUFSIZE_gp 0 /* Data Buffer Size group position. */ -#define USB_EP_BUFSIZE0_bm (1<<0) /* Data Buffer Size bit 0 mask. */ -#define USB_EP_BUFSIZE0_bp 0 /* Data Buffer Size bit 0 position. */ -#define USB_EP_BUFSIZE1_bm (1<<1) /* Data Buffer Size bit 1 mask. */ -#define USB_EP_BUFSIZE1_bp 1 /* Data Buffer Size bit 1 position. */ -#define USB_EP_BUFSIZE2_bm (1<<2) /* Data Buffer Size bit 2 mask. */ -#define USB_EP_BUFSIZE2_bp 2 /* Data Buffer Size bit 2 position. */ - -/* USB_EP.CNT bit masks and bit positions */ -#define USB_EP_ZLP_bm 0x8000 /* Zero Length Packet bit mask. */ -#define USB_EP_ZLP_bp 15 /* Zero Length Packet bit position. */ - -/* USB.CTRLA bit masks and bit positions */ -#define USB_ENABLE_bm 0x80 /* USB Enable bit mask. */ -#define USB_ENABLE_bp 7 /* USB Enable bit position. */ - -#define USB_SPEED_bm 0x40 /* Speed Select bit mask. */ -#define USB_SPEED_bp 6 /* Speed Select bit position. */ - -#define USB_FIFOEN_bm 0x20 /* USB FIFO Enable bit mask. */ -#define USB_FIFOEN_bp 5 /* USB FIFO Enable bit position. */ - -#define USB_STFRNUM_bm 0x10 /* Store Frame Number Enable bit mask. */ -#define USB_STFRNUM_bp 4 /* Store Frame Number Enable bit position. */ - -#define USB_MAXEP_gm 0x0F /* Maximum Endpoint Addresses group mask. */ -#define USB_MAXEP_gp 0 /* Maximum Endpoint Addresses group position. */ -#define USB_MAXEP0_bm (1<<0) /* Maximum Endpoint Addresses bit 0 mask. */ -#define USB_MAXEP0_bp 0 /* Maximum Endpoint Addresses bit 0 position. */ -#define USB_MAXEP1_bm (1<<1) /* Maximum Endpoint Addresses bit 1 mask. */ -#define USB_MAXEP1_bp 1 /* Maximum Endpoint Addresses bit 1 position. */ -#define USB_MAXEP2_bm (1<<2) /* Maximum Endpoint Addresses bit 2 mask. */ -#define USB_MAXEP2_bp 2 /* Maximum Endpoint Addresses bit 2 position. */ -#define USB_MAXEP3_bm (1<<3) /* Maximum Endpoint Addresses bit 3 mask. */ -#define USB_MAXEP3_bp 3 /* Maximum Endpoint Addresses bit 3 position. */ - -/* USB.CTRLB bit masks and bit positions */ -#define USB_PULLRST_bm 0x10 /* Pull during Reset bit mask. */ -#define USB_PULLRST_bp 4 /* Pull during Reset bit position. */ - -#define USB_RWAKEUP_bm 0x04 /* Remote Wake-up bit mask. */ -#define USB_RWAKEUP_bp 2 /* Remote Wake-up bit position. */ - -#define USB_GNACK_bm 0x02 /* Global NACK bit mask. */ -#define USB_GNACK_bp 1 /* Global NACK bit position. */ - -#define USB_ATTACH_bm 0x01 /* Attach bit mask. */ -#define USB_ATTACH_bp 0 /* Attach bit position. */ - -/* USB.STATUS bit masks and bit positions */ -#define USB_URESUME_bm 0x08 /* Upstream Resume bit mask. */ -#define USB_URESUME_bp 3 /* Upstream Resume bit position. */ - -#define USB_RESUME_bm 0x04 /* Resume bit mask. */ -#define USB_RESUME_bp 2 /* Resume bit position. */ - -#define USB_SUSPEND_bm 0x02 /* Bus Suspended bit mask. */ -#define USB_SUSPEND_bp 1 /* Bus Suspended bit position. */ - -#define USB_BUSRST_bm 0x01 /* Bus Reset bit mask. */ -#define USB_BUSRST_bp 0 /* Bus Reset bit position. */ - -/* USB.ADDR bit masks and bit positions */ -#define USB_ADDR_gm 0x7F /* Device Address group mask. */ -#define USB_ADDR_gp 0 /* Device Address group position. */ -#define USB_ADDR0_bm (1<<0) /* Device Address bit 0 mask. */ -#define USB_ADDR0_bp 0 /* Device Address bit 0 position. */ -#define USB_ADDR1_bm (1<<1) /* Device Address bit 1 mask. */ -#define USB_ADDR1_bp 1 /* Device Address bit 1 position. */ -#define USB_ADDR2_bm (1<<2) /* Device Address bit 2 mask. */ -#define USB_ADDR2_bp 2 /* Device Address bit 2 position. */ -#define USB_ADDR3_bm (1<<3) /* Device Address bit 3 mask. */ -#define USB_ADDR3_bp 3 /* Device Address bit 3 position. */ -#define USB_ADDR4_bm (1<<4) /* Device Address bit 4 mask. */ -#define USB_ADDR4_bp 4 /* Device Address bit 4 position. */ -#define USB_ADDR5_bm (1<<5) /* Device Address bit 5 mask. */ -#define USB_ADDR5_bp 5 /* Device Address bit 5 position. */ -#define USB_ADDR6_bm (1<<6) /* Device Address bit 6 mask. */ -#define USB_ADDR6_bp 6 /* Device Address bit 6 position. */ - -/* USB.FIFOWP bit masks and bit positions */ -#define USB_FIFOWP_gm 0x1F /* FIFO Write Pointer group mask. */ -#define USB_FIFOWP_gp 0 /* FIFO Write Pointer group position. */ -#define USB_FIFOWP0_bm (1<<0) /* FIFO Write Pointer bit 0 mask. */ -#define USB_FIFOWP0_bp 0 /* FIFO Write Pointer bit 0 position. */ -#define USB_FIFOWP1_bm (1<<1) /* FIFO Write Pointer bit 1 mask. */ -#define USB_FIFOWP1_bp 1 /* FIFO Write Pointer bit 1 position. */ -#define USB_FIFOWP2_bm (1<<2) /* FIFO Write Pointer bit 2 mask. */ -#define USB_FIFOWP2_bp 2 /* FIFO Write Pointer bit 2 position. */ -#define USB_FIFOWP3_bm (1<<3) /* FIFO Write Pointer bit 3 mask. */ -#define USB_FIFOWP3_bp 3 /* FIFO Write Pointer bit 3 position. */ -#define USB_FIFOWP4_bm (1<<4) /* FIFO Write Pointer bit 4 mask. */ -#define USB_FIFOWP4_bp 4 /* FIFO Write Pointer bit 4 position. */ - -/* USB.FIFORP bit masks and bit positions */ -#define USB_FIFORP_gm 0x1F /* FIFO Read Pointer group mask. */ -#define USB_FIFORP_gp 0 /* FIFO Read Pointer group position. */ -#define USB_FIFORP0_bm (1<<0) /* FIFO Read Pointer bit 0 mask. */ -#define USB_FIFORP0_bp 0 /* FIFO Read Pointer bit 0 position. */ -#define USB_FIFORP1_bm (1<<1) /* FIFO Read Pointer bit 1 mask. */ -#define USB_FIFORP1_bp 1 /* FIFO Read Pointer bit 1 position. */ -#define USB_FIFORP2_bm (1<<2) /* FIFO Read Pointer bit 2 mask. */ -#define USB_FIFORP2_bp 2 /* FIFO Read Pointer bit 2 position. */ -#define USB_FIFORP3_bm (1<<3) /* FIFO Read Pointer bit 3 mask. */ -#define USB_FIFORP3_bp 3 /* FIFO Read Pointer bit 3 position. */ -#define USB_FIFORP4_bm (1<<4) /* FIFO Read Pointer bit 4 mask. */ -#define USB_FIFORP4_bp 4 /* FIFO Read Pointer bit 4 position. */ - -/* USB.INTCTRLA bit masks and bit positions */ -#define USB_SOFIE_bm 0x80 /* Start Of Frame Interrupt Enable bit mask. */ -#define USB_SOFIE_bp 7 /* Start Of Frame Interrupt Enable bit position. */ - -#define USB_BUSEVIE_bm 0x40 /* Bus Event Interrupt Enable bit mask. */ -#define USB_BUSEVIE_bp 6 /* Bus Event Interrupt Enable bit position. */ - -#define USB_BUSERRIE_bm 0x20 /* Bus Error Interrupt Enable bit mask. */ -#define USB_BUSERRIE_bp 5 /* Bus Error Interrupt Enable bit position. */ - -#define USB_STALLIE_bm 0x10 /* STALL Interrupt Enable bit mask. */ -#define USB_STALLIE_bp 4 /* STALL Interrupt Enable bit position. */ - -#define USB_INTLVL_gm 0x03 /* Interrupt Level group mask. */ -#define USB_INTLVL_gp 0 /* Interrupt Level group position. */ -#define USB_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */ -#define USB_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */ -#define USB_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ -#define USB_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */ - -/* USB.INTCTRLB bit masks and bit positions */ -#define USB_TRNIE_bm 0x02 /* Transaction Complete Interrupt Enable bit mask. */ -#define USB_TRNIE_bp 1 /* Transaction Complete Interrupt Enable bit position. */ - -#define USB_SETUPIE_bm 0x01 /* SETUP Transaction Complete Interrupt Enable bit mask. */ -#define USB_SETUPIE_bp 0 /* SETUP Transaction Complete Interrupt Enable bit position. */ - -/* USB.INTFLAGSACLR bit masks and bit positions */ -#define USB_SOFIF_bm 0x80 /* Start Of Frame Interrupt Flag bit mask. */ -#define USB_SOFIF_bp 7 /* Start Of Frame Interrupt Flag bit position. */ - -#define USB_SUSPENDIF_bm 0x40 /* Suspend Interrupt Flag bit mask. */ -#define USB_SUSPENDIF_bp 6 /* Suspend Interrupt Flag bit position. */ - -#define USB_RESUMEIF_bm 0x20 /* Resume Interrupt Flag bit mask. */ -#define USB_RESUMEIF_bp 5 /* Resume Interrupt Flag bit position. */ - -#define USB_RSTIF_bm 0x10 /* Reset Interrupt Flag bit mask. */ -#define USB_RSTIF_bp 4 /* Reset Interrupt Flag bit position. */ - -#define USB_CRCIF_bm 0x08 /* Isochronous CRC Error Interrupt Flag bit mask. */ -#define USB_CRCIF_bp 3 /* Isochronous CRC Error Interrupt Flag bit position. */ - -#define USB_UNFIF_bm 0x04 /* Underflow Interrupt Flag bit mask. */ -#define USB_UNFIF_bp 2 /* Underflow Interrupt Flag bit position. */ - -#define USB_OVFIF_bm 0x02 /* Overflow Interrupt Flag bit mask. */ -#define USB_OVFIF_bp 1 /* Overflow Interrupt Flag bit position. */ - -#define USB_STALLIF_bm 0x01 /* STALL Interrupt Flag bit mask. */ -#define USB_STALLIF_bp 0 /* STALL Interrupt Flag bit position. */ - -/* USB.INTFLAGSASET bit masks and bit positions */ -/* USB_SOFIF Predefined. */ -/* USB_SOFIF Predefined. */ - -/* USB_SUSPENDIF Predefined. */ -/* USB_SUSPENDIF Predefined. */ - -/* USB_RESUMEIF Predefined. */ -/* USB_RESUMEIF Predefined. */ - -/* USB_RSTIF Predefined. */ -/* USB_RSTIF Predefined. */ - -/* USB_CRCIF Predefined. */ -/* USB_CRCIF Predefined. */ - -/* USB_UNFIF Predefined. */ -/* USB_UNFIF Predefined. */ - -/* USB_OVFIF Predefined. */ -/* USB_OVFIF Predefined. */ - -/* USB_STALLIF Predefined. */ -/* USB_STALLIF Predefined. */ - -/* USB.INTFLAGSBCLR bit masks and bit positions */ -#define USB_TRNIF_bm 0x02 /* Transaction Complete Interrupt Flag bit mask. */ -#define USB_TRNIF_bp 1 /* Transaction Complete Interrupt Flag bit position. */ - -#define USB_SETUPIF_bm 0x01 /* SETUP Transaction Complete Interrupt Flag bit mask. */ -#define USB_SETUPIF_bp 0 /* SETUP Transaction Complete Interrupt Flag bit position. */ - -/* USB.INTFLAGSBSET bit masks and bit positions */ -/* USB_TRNIF Predefined. */ -/* USB_TRNIF Predefined. */ - -/* USB_SETUPIF Predefined. */ -/* USB_SETUPIF Predefined. */ - -/* PORT - I/O Port Configuration */ -/* PORT.INTCTRL bit masks and bit positions */ -#define PORT_INT1LVL_gm 0x0C /* Port Interrupt 1 Level group mask. */ -#define PORT_INT1LVL_gp 2 /* Port Interrupt 1 Level group position. */ -#define PORT_INT1LVL0_bm (1<<2) /* Port Interrupt 1 Level bit 0 mask. */ -#define PORT_INT1LVL0_bp 2 /* Port Interrupt 1 Level bit 0 position. */ -#define PORT_INT1LVL1_bm (1<<3) /* Port Interrupt 1 Level bit 1 mask. */ -#define PORT_INT1LVL1_bp 3 /* Port Interrupt 1 Level bit 1 position. */ - -#define PORT_INT0LVL_gm 0x03 /* Port Interrupt 0 Level group mask. */ -#define PORT_INT0LVL_gp 0 /* Port Interrupt 0 Level group position. */ -#define PORT_INT0LVL0_bm (1<<0) /* Port Interrupt 0 Level bit 0 mask. */ -#define PORT_INT0LVL0_bp 0 /* Port Interrupt 0 Level bit 0 position. */ -#define PORT_INT0LVL1_bm (1<<1) /* Port Interrupt 0 Level bit 1 mask. */ -#define PORT_INT0LVL1_bp 1 /* Port Interrupt 0 Level bit 1 position. */ - -/* PORT.INTFLAGS bit masks and bit positions */ -#define PORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ -#define PORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ - -#define PORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ -#define PORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ - -/* PORT.REMAP bit masks and bit positions */ -#define PORT_SPI_bm 0x20 /* SPI bit mask. */ -#define PORT_SPI_bp 5 /* SPI bit position. */ - -#define PORT_USART0_bm 0x10 /* USART0 bit mask. */ -#define PORT_USART0_bp 4 /* USART0 bit position. */ - -#define PORT_TC0D_bm 0x08 /* Timer/Counter 0 Output Compare D bit mask. */ -#define PORT_TC0D_bp 3 /* Timer/Counter 0 Output Compare D bit position. */ - -#define PORT_TC0C_bm 0x04 /* Timer/Counter 0 Output Compare C bit mask. */ -#define PORT_TC0C_bp 2 /* Timer/Counter 0 Output Compare C bit position. */ - -#define PORT_TC0B_bm 0x02 /* Timer/Counter 0 Output Compare B bit mask. */ -#define PORT_TC0B_bp 1 /* Timer/Counter 0 Output Compare B bit position. */ - -#define PORT_TC0A_bm 0x01 /* Timer/Counter 0 Output Compare A bit mask. */ -#define PORT_TC0A_bp 0 /* Timer/Counter 0 Output Compare A bit position. */ - -/* PORT.PIN0CTRL bit masks and bit positions */ -#define PORT_SRLEN_bm 0x80 /* Slew Rate Enable bit mask. */ -#define PORT_SRLEN_bp 7 /* Slew Rate Enable bit position. */ - -#define PORT_INVEN_bm 0x40 /* Inverted I/O Enable bit mask. */ -#define PORT_INVEN_bp 6 /* Inverted I/O Enable bit position. */ - -#define PORT_OPC_gm 0x38 /* Output/Pull Configuration group mask. */ -#define PORT_OPC_gp 3 /* Output/Pull Configuration group position. */ -#define PORT_OPC0_bm (1<<3) /* Output/Pull Configuration bit 0 mask. */ -#define PORT_OPC0_bp 3 /* Output/Pull Configuration bit 0 position. */ -#define PORT_OPC1_bm (1<<4) /* Output/Pull Configuration bit 1 mask. */ -#define PORT_OPC1_bp 4 /* Output/Pull Configuration bit 1 position. */ -#define PORT_OPC2_bm (1<<5) /* Output/Pull Configuration bit 2 mask. */ -#define PORT_OPC2_bp 5 /* Output/Pull Configuration bit 2 position. */ - -#define PORT_ISC_gm 0x07 /* Input/Sense Configuration group mask. */ -#define PORT_ISC_gp 0 /* Input/Sense Configuration group position. */ -#define PORT_ISC0_bm (1<<0) /* Input/Sense Configuration bit 0 mask. */ -#define PORT_ISC0_bp 0 /* Input/Sense Configuration bit 0 position. */ -#define PORT_ISC1_bm (1<<1) /* Input/Sense Configuration bit 1 mask. */ -#define PORT_ISC1_bp 1 /* Input/Sense Configuration bit 1 position. */ -#define PORT_ISC2_bm (1<<2) /* Input/Sense Configuration bit 2 mask. */ -#define PORT_ISC2_bp 2 /* Input/Sense Configuration bit 2 position. */ - -/* PORT.PIN1CTRL bit masks and bit positions */ -/* PORT_SRLEN Predefined. */ -/* PORT_SRLEN Predefined. */ - -/* PORT_INVEN Predefined. */ -/* PORT_INVEN Predefined. */ - -/* PORT_OPC Predefined. */ -/* PORT_OPC Predefined. */ - -/* PORT_ISC Predefined. */ -/* PORT_ISC Predefined. */ - -/* PORT.PIN2CTRL bit masks and bit positions */ -/* PORT_SRLEN Predefined. */ -/* PORT_SRLEN Predefined. */ - -/* PORT_INVEN Predefined. */ -/* PORT_INVEN Predefined. */ - -/* PORT_OPC Predefined. */ -/* PORT_OPC Predefined. */ - -/* PORT_ISC Predefined. */ -/* PORT_ISC Predefined. */ - -/* PORT.PIN3CTRL bit masks and bit positions */ -/* PORT_SRLEN Predefined. */ -/* PORT_SRLEN Predefined. */ - -/* PORT_INVEN Predefined. */ -/* PORT_INVEN Predefined. */ - -/* PORT_OPC Predefined. */ -/* PORT_OPC Predefined. */ - -/* PORT_ISC Predefined. */ -/* PORT_ISC Predefined. */ - -/* PORT.PIN4CTRL bit masks and bit positions */ -/* PORT_SRLEN Predefined. */ -/* PORT_SRLEN Predefined. */ - -/* PORT_INVEN Predefined. */ -/* PORT_INVEN Predefined. */ - -/* PORT_OPC Predefined. */ -/* PORT_OPC Predefined. */ - -/* PORT_ISC Predefined. */ -/* PORT_ISC Predefined. */ - -/* PORT.PIN5CTRL bit masks and bit positions */ -/* PORT_SRLEN Predefined. */ -/* PORT_SRLEN Predefined. */ - -/* PORT_INVEN Predefined. */ -/* PORT_INVEN Predefined. */ - -/* PORT_OPC Predefined. */ -/* PORT_OPC Predefined. */ - -/* PORT_ISC Predefined. */ -/* PORT_ISC Predefined. */ - -/* PORT.PIN6CTRL bit masks and bit positions */ -/* PORT_SRLEN Predefined. */ -/* PORT_SRLEN Predefined. */ - -/* PORT_INVEN Predefined. */ -/* PORT_INVEN Predefined. */ - -/* PORT_OPC Predefined. */ -/* PORT_OPC Predefined. */ - -/* PORT_ISC Predefined. */ -/* PORT_ISC Predefined. */ - -/* PORT.PIN7CTRL bit masks and bit positions */ -/* PORT_SRLEN Predefined. */ -/* PORT_SRLEN Predefined. */ - -/* PORT_INVEN Predefined. */ -/* PORT_INVEN Predefined. */ - -/* PORT_OPC Predefined. */ -/* PORT_OPC Predefined. */ - -/* PORT_ISC Predefined. */ -/* PORT_ISC Predefined. */ - -/* TC - 16-bit Timer/Counter With PWM */ -/* TC0.CTRLA bit masks and bit positions */ -#define TC0_CLKSEL_gm 0x0F /* Clock Selection group mask. */ -#define TC0_CLKSEL_gp 0 /* Clock Selection group position. */ -#define TC0_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ -#define TC0_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ -#define TC0_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ -#define TC0_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ -#define TC0_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ -#define TC0_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ -#define TC0_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ -#define TC0_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ - -/* TC0.CTRLB bit masks and bit positions */ -#define TC0_CCDEN_bm 0x80 /* Compare or Capture D Enable bit mask. */ -#define TC0_CCDEN_bp 7 /* Compare or Capture D Enable bit position. */ - -#define TC0_CCCEN_bm 0x40 /* Compare or Capture C Enable bit mask. */ -#define TC0_CCCEN_bp 6 /* Compare or Capture C Enable bit position. */ - -#define TC0_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ -#define TC0_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ - -#define TC0_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ -#define TC0_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ - -#define TC0_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ -#define TC0_WGMODE_gp 0 /* Waveform generation mode group position. */ -#define TC0_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ -#define TC0_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ -#define TC0_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ -#define TC0_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ -#define TC0_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ -#define TC0_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ - -/* TC0.CTRLC bit masks and bit positions */ -#define TC0_CMPD_bm 0x08 /* Compare D Output Value bit mask. */ -#define TC0_CMPD_bp 3 /* Compare D Output Value bit position. */ - -#define TC0_CMPC_bm 0x04 /* Compare C Output Value bit mask. */ -#define TC0_CMPC_bp 2 /* Compare C Output Value bit position. */ - -#define TC0_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ -#define TC0_CMPB_bp 1 /* Compare B Output Value bit position. */ - -#define TC0_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ -#define TC0_CMPA_bp 0 /* Compare A Output Value bit position. */ - -/* TC0.CTRLD bit masks and bit positions */ -#define TC0_EVACT_gm 0xE0 /* Event Action group mask. */ -#define TC0_EVACT_gp 5 /* Event Action group position. */ -#define TC0_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ -#define TC0_EVACT0_bp 5 /* Event Action bit 0 position. */ -#define TC0_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ -#define TC0_EVACT1_bp 6 /* Event Action bit 1 position. */ -#define TC0_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ -#define TC0_EVACT2_bp 7 /* Event Action bit 2 position. */ - -#define TC0_EVDLY_bm 0x10 /* Event Delay bit mask. */ -#define TC0_EVDLY_bp 4 /* Event Delay bit position. */ - -#define TC0_EVSEL_gm 0x0F /* Event Source Select group mask. */ -#define TC0_EVSEL_gp 0 /* Event Source Select group position. */ -#define TC0_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ -#define TC0_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ -#define TC0_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ -#define TC0_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ -#define TC0_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ -#define TC0_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ -#define TC0_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ -#define TC0_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ - -/* TC0.CTRLE bit masks and bit positions */ -#define TC0_BYTEM_gm 0x03 /* Byte Mode group mask. */ -#define TC0_BYTEM_gp 0 /* Byte Mode group position. */ -#define TC0_BYTEM0_bm (1<<0) /* Byte Mode bit 0 mask. */ -#define TC0_BYTEM0_bp 0 /* Byte Mode bit 0 position. */ -#define TC0_BYTEM1_bm (1<<1) /* Byte Mode bit 1 mask. */ -#define TC0_BYTEM1_bp 1 /* Byte Mode bit 1 position. */ - -/* TC0.INTCTRLA bit masks and bit positions */ -#define TC0_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ -#define TC0_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ -#define TC0_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ -#define TC0_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ -#define TC0_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ -#define TC0_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ - -#define TC0_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ -#define TC0_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ -#define TC0_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ -#define TC0_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ -#define TC0_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ -#define TC0_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ - -/* TC0.INTCTRLB bit masks and bit positions */ -#define TC0_CCDINTLVL_gm 0xC0 /* Compare or Capture D Interrupt Level group mask. */ -#define TC0_CCDINTLVL_gp 6 /* Compare or Capture D Interrupt Level group position. */ -#define TC0_CCDINTLVL0_bm (1<<6) /* Compare or Capture D Interrupt Level bit 0 mask. */ -#define TC0_CCDINTLVL0_bp 6 /* Compare or Capture D Interrupt Level bit 0 position. */ -#define TC0_CCDINTLVL1_bm (1<<7) /* Compare or Capture D Interrupt Level bit 1 mask. */ -#define TC0_CCDINTLVL1_bp 7 /* Compare or Capture D Interrupt Level bit 1 position. */ - -#define TC0_CCCINTLVL_gm 0x30 /* Compare or Capture C Interrupt Level group mask. */ -#define TC0_CCCINTLVL_gp 4 /* Compare or Capture C Interrupt Level group position. */ -#define TC0_CCCINTLVL0_bm (1<<4) /* Compare or Capture C Interrupt Level bit 0 mask. */ -#define TC0_CCCINTLVL0_bp 4 /* Compare or Capture C Interrupt Level bit 0 position. */ -#define TC0_CCCINTLVL1_bm (1<<5) /* Compare or Capture C Interrupt Level bit 1 mask. */ -#define TC0_CCCINTLVL1_bp 5 /* Compare or Capture C Interrupt Level bit 1 position. */ - -#define TC0_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ -#define TC0_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ -#define TC0_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ -#define TC0_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ -#define TC0_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ -#define TC0_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ - -#define TC0_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ -#define TC0_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ -#define TC0_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ -#define TC0_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ -#define TC0_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ -#define TC0_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ - -/* TC0.CTRLFCLR bit masks and bit positions */ -#define TC0_CMD_gm 0x0C /* Command group mask. */ -#define TC0_CMD_gp 2 /* Command group position. */ -#define TC0_CMD0_bm (1<<2) /* Command bit 0 mask. */ -#define TC0_CMD0_bp 2 /* Command bit 0 position. */ -#define TC0_CMD1_bm (1<<3) /* Command bit 1 mask. */ -#define TC0_CMD1_bp 3 /* Command bit 1 position. */ - -#define TC0_LUPD_bm 0x02 /* Lock Update bit mask. */ -#define TC0_LUPD_bp 1 /* Lock Update bit position. */ - -#define TC0_DIR_bm 0x01 /* Direction bit mask. */ -#define TC0_DIR_bp 0 /* Direction bit position. */ - -/* TC0.CTRLFSET bit masks and bit positions */ -/* TC0_CMD Predefined. */ -/* TC0_CMD Predefined. */ - -/* TC0_LUPD Predefined. */ -/* TC0_LUPD Predefined. */ - -/* TC0_DIR Predefined. */ -/* TC0_DIR Predefined. */ - -/* TC0.CTRLGCLR bit masks and bit positions */ -#define TC0_CCDBV_bm 0x10 /* Compare or Capture D Buffer Valid bit mask. */ -#define TC0_CCDBV_bp 4 /* Compare or Capture D Buffer Valid bit position. */ - -#define TC0_CCCBV_bm 0x08 /* Compare or Capture C Buffer Valid bit mask. */ -#define TC0_CCCBV_bp 3 /* Compare or Capture C Buffer Valid bit position. */ - -#define TC0_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ -#define TC0_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ - -#define TC0_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ -#define TC0_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ - -#define TC0_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ -#define TC0_PERBV_bp 0 /* Period Buffer Valid bit position. */ - -/* TC0.CTRLGSET bit masks and bit positions */ -/* TC0_CCDBV Predefined. */ -/* TC0_CCDBV Predefined. */ - -/* TC0_CCCBV Predefined. */ -/* TC0_CCCBV Predefined. */ - -/* TC0_CCBBV Predefined. */ -/* TC0_CCBBV Predefined. */ - -/* TC0_CCABV Predefined. */ -/* TC0_CCABV Predefined. */ - -/* TC0_PERBV Predefined. */ -/* TC0_PERBV Predefined. */ - -/* TC0.INTFLAGS bit masks and bit positions */ -#define TC0_CCDIF_bm 0x80 /* Compare or Capture D Interrupt Flag bit mask. */ -#define TC0_CCDIF_bp 7 /* Compare or Capture D Interrupt Flag bit position. */ - -#define TC0_CCCIF_bm 0x40 /* Compare or Capture C Interrupt Flag bit mask. */ -#define TC0_CCCIF_bp 6 /* Compare or Capture C Interrupt Flag bit position. */ - -#define TC0_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ -#define TC0_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ - -#define TC0_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ -#define TC0_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ - -#define TC0_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ -#define TC0_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ - -#define TC0_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ -#define TC0_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ - -/* TC1.CTRLA bit masks and bit positions */ -#define TC1_CLKSEL_gm 0x0F /* Clock Selection group mask. */ -#define TC1_CLKSEL_gp 0 /* Clock Selection group position. */ -#define TC1_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ -#define TC1_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ -#define TC1_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ -#define TC1_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ -#define TC1_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ -#define TC1_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ -#define TC1_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ -#define TC1_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ - -/* TC1.CTRLB bit masks and bit positions */ -#define TC1_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ -#define TC1_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ - -#define TC1_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ -#define TC1_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ - -#define TC1_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ -#define TC1_WGMODE_gp 0 /* Waveform generation mode group position. */ -#define TC1_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ -#define TC1_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ -#define TC1_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ -#define TC1_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ -#define TC1_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ -#define TC1_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ - -/* TC1.CTRLC bit masks and bit positions */ -#define TC1_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ -#define TC1_CMPB_bp 1 /* Compare B Output Value bit position. */ - -#define TC1_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ -#define TC1_CMPA_bp 0 /* Compare A Output Value bit position. */ - -/* TC1.CTRLD bit masks and bit positions */ -#define TC1_EVACT_gm 0xE0 /* Event Action group mask. */ -#define TC1_EVACT_gp 5 /* Event Action group position. */ -#define TC1_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ -#define TC1_EVACT0_bp 5 /* Event Action bit 0 position. */ -#define TC1_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ -#define TC1_EVACT1_bp 6 /* Event Action bit 1 position. */ -#define TC1_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ -#define TC1_EVACT2_bp 7 /* Event Action bit 2 position. */ - -#define TC1_EVDLY_bm 0x10 /* Event Delay bit mask. */ -#define TC1_EVDLY_bp 4 /* Event Delay bit position. */ - -#define TC1_EVSEL_gm 0x0F /* Event Source Select group mask. */ -#define TC1_EVSEL_gp 0 /* Event Source Select group position. */ -#define TC1_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ -#define TC1_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ -#define TC1_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ -#define TC1_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ -#define TC1_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ -#define TC1_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ -#define TC1_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ -#define TC1_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ - -/* TC1.CTRLE bit masks and bit positions */ -#define TC1_BYTEM_bm 0x01 /* Byte Mode bit mask. */ -#define TC1_BYTEM_bp 0 /* Byte Mode bit position. */ - -/* TC1.INTCTRLA bit masks and bit positions */ -#define TC1_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ -#define TC1_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ -#define TC1_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ -#define TC1_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ -#define TC1_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ -#define TC1_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ - -#define TC1_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ -#define TC1_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ -#define TC1_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ -#define TC1_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ -#define TC1_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ -#define TC1_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ - -/* TC1.INTCTRLB bit masks and bit positions */ -#define TC1_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ -#define TC1_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ -#define TC1_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ -#define TC1_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ -#define TC1_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ -#define TC1_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ - -#define TC1_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ -#define TC1_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ -#define TC1_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ -#define TC1_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ -#define TC1_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ -#define TC1_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ - -/* TC1.CTRLFCLR bit masks and bit positions */ -#define TC1_CMD_gm 0x0C /* Command group mask. */ -#define TC1_CMD_gp 2 /* Command group position. */ -#define TC1_CMD0_bm (1<<2) /* Command bit 0 mask. */ -#define TC1_CMD0_bp 2 /* Command bit 0 position. */ -#define TC1_CMD1_bm (1<<3) /* Command bit 1 mask. */ -#define TC1_CMD1_bp 3 /* Command bit 1 position. */ - -#define TC1_LUPD_bm 0x02 /* Lock Update bit mask. */ -#define TC1_LUPD_bp 1 /* Lock Update bit position. */ - -#define TC1_DIR_bm 0x01 /* Direction bit mask. */ -#define TC1_DIR_bp 0 /* Direction bit position. */ - -/* TC1.CTRLFSET bit masks and bit positions */ -/* TC1_CMD Predefined. */ -/* TC1_CMD Predefined. */ - -/* TC1_LUPD Predefined. */ -/* TC1_LUPD Predefined. */ - -/* TC1_DIR Predefined. */ -/* TC1_DIR Predefined. */ - -/* TC1.CTRLGCLR bit masks and bit positions */ -#define TC1_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ -#define TC1_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ - -#define TC1_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ -#define TC1_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ - -#define TC1_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ -#define TC1_PERBV_bp 0 /* Period Buffer Valid bit position. */ - -/* TC1.CTRLGSET bit masks and bit positions */ -/* TC1_CCBBV Predefined. */ -/* TC1_CCBBV Predefined. */ - -/* TC1_CCABV Predefined. */ -/* TC1_CCABV Predefined. */ - -/* TC1_PERBV Predefined. */ -/* TC1_PERBV Predefined. */ - -/* TC1.INTFLAGS bit masks and bit positions */ -#define TC1_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ -#define TC1_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ - -#define TC1_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ -#define TC1_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ - -#define TC1_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ -#define TC1_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ - -#define TC1_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ -#define TC1_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ - -/* TC2 - 16-bit Timer/Counter type 2 */ -/* TC2.CTRLA bit masks and bit positions */ -#define TC2_CLKSEL_gm 0x0F /* Clock Selection group mask. */ -#define TC2_CLKSEL_gp 0 /* Clock Selection group position. */ -#define TC2_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ -#define TC2_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ -#define TC2_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ -#define TC2_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ -#define TC2_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ -#define TC2_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ -#define TC2_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ -#define TC2_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ - -/* TC2.CTRLB bit masks and bit positions */ -#define TC2_HCMPDEN_bm 0x80 /* High Byte Compare D Enable bit mask. */ -#define TC2_HCMPDEN_bp 7 /* High Byte Compare D Enable bit position. */ - -#define TC2_HCMPCEN_bm 0x40 /* High Byte Compare C Enable bit mask. */ -#define TC2_HCMPCEN_bp 6 /* High Byte Compare C Enable bit position. */ - -#define TC2_HCMPBEN_bm 0x20 /* High Byte Compare B Enable bit mask. */ -#define TC2_HCMPBEN_bp 5 /* High Byte Compare B Enable bit position. */ - -#define TC2_HCMPAEN_bm 0x10 /* High Byte Compare A Enable bit mask. */ -#define TC2_HCMPAEN_bp 4 /* High Byte Compare A Enable bit position. */ - -#define TC2_LCMPDEN_bm 0x08 /* Low Byte Compare D Enable bit mask. */ -#define TC2_LCMPDEN_bp 3 /* Low Byte Compare D Enable bit position. */ - -#define TC2_LCMPCEN_bm 0x04 /* Low Byte Compare C Enable bit mask. */ -#define TC2_LCMPCEN_bp 2 /* Low Byte Compare C Enable bit position. */ - -#define TC2_LCMPBEN_bm 0x02 /* Low Byte Compare B Enable bit mask. */ -#define TC2_LCMPBEN_bp 1 /* Low Byte Compare B Enable bit position. */ - -#define TC2_LCMPAEN_bm 0x01 /* Low Byte Compare A Enable bit mask. */ -#define TC2_LCMPAEN_bp 0 /* Low Byte Compare A Enable bit position. */ - -/* TC2.CTRLC bit masks and bit positions */ -#define TC2_HCMPD_bm 0x80 /* High Byte Compare D Output Value bit mask. */ -#define TC2_HCMPD_bp 7 /* High Byte Compare D Output Value bit position. */ - -#define TC2_HCMPC_bm 0x40 /* High Byte Compare C Output Value bit mask. */ -#define TC2_HCMPC_bp 6 /* High Byte Compare C Output Value bit position. */ - -#define TC2_HCMPB_bm 0x20 /* High Byte Compare B Output Value bit mask. */ -#define TC2_HCMPB_bp 5 /* High Byte Compare B Output Value bit position. */ - -#define TC2_HCMPA_bm 0x10 /* High Byte Compare A Output Value bit mask. */ -#define TC2_HCMPA_bp 4 /* High Byte Compare A Output Value bit position. */ - -#define TC2_LCMPD_bm 0x08 /* Low Byte Compare D Output Value bit mask. */ -#define TC2_LCMPD_bp 3 /* Low Byte Compare D Output Value bit position. */ - -#define TC2_LCMPC_bm 0x04 /* Low Byte Compare C Output Value bit mask. */ -#define TC2_LCMPC_bp 2 /* Low Byte Compare C Output Value bit position. */ - -#define TC2_LCMPB_bm 0x02 /* Low Byte Compare B Output Value bit mask. */ -#define TC2_LCMPB_bp 1 /* Low Byte Compare B Output Value bit position. */ - -#define TC2_LCMPA_bm 0x01 /* Low Byte Compare A Output Value bit mask. */ -#define TC2_LCMPA_bp 0 /* Low Byte Compare A Output Value bit position. */ - -/* TC2.CTRLE bit masks and bit positions */ -#define TC2_BYTEM_gm 0x03 /* Byte Mode group mask. */ -#define TC2_BYTEM_gp 0 /* Byte Mode group position. */ -#define TC2_BYTEM0_bm (1<<0) /* Byte Mode bit 0 mask. */ -#define TC2_BYTEM0_bp 0 /* Byte Mode bit 0 position. */ -#define TC2_BYTEM1_bm (1<<1) /* Byte Mode bit 1 mask. */ -#define TC2_BYTEM1_bp 1 /* Byte Mode bit 1 position. */ - -/* TC2.INTCTRLA bit masks and bit positions */ -#define TC2_HUNFINTLVL_gm 0x0C /* High Byte Underflow Interrupt Level group mask. */ -#define TC2_HUNFINTLVL_gp 2 /* High Byte Underflow Interrupt Level group position. */ -#define TC2_HUNFINTLVL0_bm (1<<2) /* High Byte Underflow Interrupt Level bit 0 mask. */ -#define TC2_HUNFINTLVL0_bp 2 /* High Byte Underflow Interrupt Level bit 0 position. */ -#define TC2_HUNFINTLVL1_bm (1<<3) /* High Byte Underflow Interrupt Level bit 1 mask. */ -#define TC2_HUNFINTLVL1_bp 3 /* High Byte Underflow Interrupt Level bit 1 position. */ - -#define TC2_LUNFINTLVL_gm 0x03 /* Low Byte Underflow interrupt level group mask. */ -#define TC2_LUNFINTLVL_gp 0 /* Low Byte Underflow interrupt level group position. */ -#define TC2_LUNFINTLVL0_bm (1<<0) /* Low Byte Underflow interrupt level bit 0 mask. */ -#define TC2_LUNFINTLVL0_bp 0 /* Low Byte Underflow interrupt level bit 0 position. */ -#define TC2_LUNFINTLVL1_bm (1<<1) /* Low Byte Underflow interrupt level bit 1 mask. */ -#define TC2_LUNFINTLVL1_bp 1 /* Low Byte Underflow interrupt level bit 1 position. */ - -/* TC2.INTCTRLB bit masks and bit positions */ -#define TC2_LCMPDINTLVL_gm 0xC0 /* Low Byte Compare D Interrupt Level group mask. */ -#define TC2_LCMPDINTLVL_gp 6 /* Low Byte Compare D Interrupt Level group position. */ -#define TC2_LCMPDINTLVL0_bm (1<<6) /* Low Byte Compare D Interrupt Level bit 0 mask. */ -#define TC2_LCMPDINTLVL0_bp 6 /* Low Byte Compare D Interrupt Level bit 0 position. */ -#define TC2_LCMPDINTLVL1_bm (1<<7) /* Low Byte Compare D Interrupt Level bit 1 mask. */ -#define TC2_LCMPDINTLVL1_bp 7 /* Low Byte Compare D Interrupt Level bit 1 position. */ - -#define TC2_LCMPCINTLVL_gm 0x30 /* Low Byte Compare C Interrupt Level group mask. */ -#define TC2_LCMPCINTLVL_gp 4 /* Low Byte Compare C Interrupt Level group position. */ -#define TC2_LCMPCINTLVL0_bm (1<<4) /* Low Byte Compare C Interrupt Level bit 0 mask. */ -#define TC2_LCMPCINTLVL0_bp 4 /* Low Byte Compare C Interrupt Level bit 0 position. */ -#define TC2_LCMPCINTLVL1_bm (1<<5) /* Low Byte Compare C Interrupt Level bit 1 mask. */ -#define TC2_LCMPCINTLVL1_bp 5 /* Low Byte Compare C Interrupt Level bit 1 position. */ - -#define TC2_LCMPBINTLVL_gm 0x0C /* Low Byte Compare B Interrupt Level group mask. */ -#define TC2_LCMPBINTLVL_gp 2 /* Low Byte Compare B Interrupt Level group position. */ -#define TC2_LCMPBINTLVL0_bm (1<<2) /* Low Byte Compare B Interrupt Level bit 0 mask. */ -#define TC2_LCMPBINTLVL0_bp 2 /* Low Byte Compare B Interrupt Level bit 0 position. */ -#define TC2_LCMPBINTLVL1_bm (1<<3) /* Low Byte Compare B Interrupt Level bit 1 mask. */ -#define TC2_LCMPBINTLVL1_bp 3 /* Low Byte Compare B Interrupt Level bit 1 position. */ - -#define TC2_LCMPAINTLVL_gm 0x03 /* Low Byte Compare A Interrupt Level group mask. */ -#define TC2_LCMPAINTLVL_gp 0 /* Low Byte Compare A Interrupt Level group position. */ -#define TC2_LCMPAINTLVL0_bm (1<<0) /* Low Byte Compare A Interrupt Level bit 0 mask. */ -#define TC2_LCMPAINTLVL0_bp 0 /* Low Byte Compare A Interrupt Level bit 0 position. */ -#define TC2_LCMPAINTLVL1_bm (1<<1) /* Low Byte Compare A Interrupt Level bit 1 mask. */ -#define TC2_LCMPAINTLVL1_bp 1 /* Low Byte Compare A Interrupt Level bit 1 position. */ - -/* TC2.CTRLF bit masks and bit positions */ -#define TC2_CMD_gm 0x0C /* Command group mask. */ -#define TC2_CMD_gp 2 /* Command group position. */ -#define TC2_CMD0_bm (1<<2) /* Command bit 0 mask. */ -#define TC2_CMD0_bp 2 /* Command bit 0 position. */ -#define TC2_CMD1_bm (1<<3) /* Command bit 1 mask. */ -#define TC2_CMD1_bp 3 /* Command bit 1 position. */ - -#define TC2_CMDEN_gm 0x03 /* Command Enable group mask. */ -#define TC2_CMDEN_gp 0 /* Command Enable group position. */ -#define TC2_CMDEN0_bm (1<<0) /* Command Enable bit 0 mask. */ -#define TC2_CMDEN0_bp 0 /* Command Enable bit 0 position. */ -#define TC2_CMDEN1_bm (1<<1) /* Command Enable bit 1 mask. */ -#define TC2_CMDEN1_bp 1 /* Command Enable bit 1 position. */ - -/* TC2.INTFLAGS bit masks and bit positions */ -#define TC2_LCMPDIF_bm 0x80 /* Low Byte Compare D Interrupt Flag bit mask. */ -#define TC2_LCMPDIF_bp 7 /* Low Byte Compare D Interrupt Flag bit position. */ - -#define TC2_LCMPCIF_bm 0x40 /* Low Byte Compare C Interrupt Flag bit mask. */ -#define TC2_LCMPCIF_bp 6 /* Low Byte Compare C Interrupt Flag bit position. */ - -#define TC2_LCMPBIF_bm 0x20 /* Low Byte Compare B Interrupt Flag bit mask. */ -#define TC2_LCMPBIF_bp 5 /* Low Byte Compare B Interrupt Flag bit position. */ - -#define TC2_LCMPAIF_bm 0x10 /* Low Byte Compare A Interrupt Flag bit mask. */ -#define TC2_LCMPAIF_bp 4 /* Low Byte Compare A Interrupt Flag bit position. */ - -#define TC2_HUNFIF_bm 0x02 /* High Byte Underflow Interrupt Flag bit mask. */ -#define TC2_HUNFIF_bp 1 /* High Byte Underflow Interrupt Flag bit position. */ - -#define TC2_LUNFIF_bm 0x01 /* Low Byte Underflow Interrupt Flag bit mask. */ -#define TC2_LUNFIF_bp 0 /* Low Byte Underflow Interrupt Flag bit position. */ - -/* AWEX - Timer/Counter Advanced Waveform Extension */ -/* AWEX.CTRL bit masks and bit positions */ -#define AWEX_PGM_bm 0x20 /* Pattern Generation Mode bit mask. */ -#define AWEX_PGM_bp 5 /* Pattern Generation Mode bit position. */ - -#define AWEX_CWCM_bm 0x10 /* Common Waveform Channel Mode bit mask. */ -#define AWEX_CWCM_bp 4 /* Common Waveform Channel Mode bit position. */ - -#define AWEX_DTICCDEN_bm 0x08 /* Dead Time Insertion Compare Channel D Enable bit mask. */ -#define AWEX_DTICCDEN_bp 3 /* Dead Time Insertion Compare Channel D Enable bit position. */ - -#define AWEX_DTICCCEN_bm 0x04 /* Dead Time Insertion Compare Channel C Enable bit mask. */ -#define AWEX_DTICCCEN_bp 2 /* Dead Time Insertion Compare Channel C Enable bit position. */ - -#define AWEX_DTICCBEN_bm 0x02 /* Dead Time Insertion Compare Channel B Enable bit mask. */ -#define AWEX_DTICCBEN_bp 1 /* Dead Time Insertion Compare Channel B Enable bit position. */ - -#define AWEX_DTICCAEN_bm 0x01 /* Dead Time Insertion Compare Channel A Enable bit mask. */ -#define AWEX_DTICCAEN_bp 0 /* Dead Time Insertion Compare Channel A Enable bit position. */ - -/* AWEX.FDCTRL bit masks and bit positions */ -#define AWEX_FDDBD_bm 0x10 /* Fault Detect on Disable Break Disable bit mask. */ -#define AWEX_FDDBD_bp 4 /* Fault Detect on Disable Break Disable bit position. */ - -#define AWEX_FDMODE_bm 0x04 /* Fault Detect Mode bit mask. */ -#define AWEX_FDMODE_bp 2 /* Fault Detect Mode bit position. */ - -#define AWEX_FDACT_gm 0x03 /* Fault Detect Action group mask. */ -#define AWEX_FDACT_gp 0 /* Fault Detect Action group position. */ -#define AWEX_FDACT0_bm (1<<0) /* Fault Detect Action bit 0 mask. */ -#define AWEX_FDACT0_bp 0 /* Fault Detect Action bit 0 position. */ -#define AWEX_FDACT1_bm (1<<1) /* Fault Detect Action bit 1 mask. */ -#define AWEX_FDACT1_bp 1 /* Fault Detect Action bit 1 position. */ - -/* AWEX.STATUS bit masks and bit positions */ -#define AWEX_FDF_bm 0x04 /* Fault Detect Flag bit mask. */ -#define AWEX_FDF_bp 2 /* Fault Detect Flag bit position. */ - -#define AWEX_DTHSBUFV_bm 0x02 /* Dead Time High Side Buffer Valid bit mask. */ -#define AWEX_DTHSBUFV_bp 1 /* Dead Time High Side Buffer Valid bit position. */ - -#define AWEX_DTLSBUFV_bm 0x01 /* Dead Time Low Side Buffer Valid bit mask. */ -#define AWEX_DTLSBUFV_bp 0 /* Dead Time Low Side Buffer Valid bit position. */ - -/* AWEX.STATUSSET bit masks and bit positions */ -/* AWEX_FDF Predefined. */ -/* AWEX_FDF Predefined. */ - -/* AWEX_DTHSBUFV Predefined. */ -/* AWEX_DTHSBUFV Predefined. */ - -/* AWEX_DTLSBUFV Predefined. */ -/* AWEX_DTLSBUFV Predefined. */ - -/* HIRES - Timer/Counter High-Resolution Extension */ -/* HIRES.CTRLA bit masks and bit positions */ -#define HIRES_HREN_gm 0x03 /* High Resolution Enable group mask. */ -#define HIRES_HREN_gp 0 /* High Resolution Enable group position. */ -#define HIRES_HREN0_bm (1<<0) /* High Resolution Enable bit 0 mask. */ -#define HIRES_HREN0_bp 0 /* High Resolution Enable bit 0 position. */ -#define HIRES_HREN1_bm (1<<1) /* High Resolution Enable bit 1 mask. */ -#define HIRES_HREN1_bp 1 /* High Resolution Enable bit 1 position. */ - -/* USART - Universal Asynchronous Receiver-Transmitter */ -/* USART.STATUS bit masks and bit positions */ -#define USART_RXCIF_bm 0x80 /* Receive Interrupt Flag bit mask. */ -#define USART_RXCIF_bp 7 /* Receive Interrupt Flag bit position. */ - -#define USART_TXCIF_bm 0x40 /* Transmit Interrupt Flag bit mask. */ -#define USART_TXCIF_bp 6 /* Transmit Interrupt Flag bit position. */ - -#define USART_DREIF_bm 0x20 /* Data Register Empty Flag bit mask. */ -#define USART_DREIF_bp 5 /* Data Register Empty Flag bit position. */ - -#define USART_FERR_bm 0x10 /* Frame Error bit mask. */ -#define USART_FERR_bp 4 /* Frame Error bit position. */ - -#define USART_BUFOVF_bm 0x08 /* Buffer Overflow bit mask. */ -#define USART_BUFOVF_bp 3 /* Buffer Overflow bit position. */ - -#define USART_PERR_bm 0x04 /* Parity Error bit mask. */ -#define USART_PERR_bp 2 /* Parity Error bit position. */ - -#define USART_RXB8_bm 0x01 /* Receive Bit 8 bit mask. */ -#define USART_RXB8_bp 0 /* Receive Bit 8 bit position. */ - -/* USART.CTRLA bit masks and bit positions */ -#define USART_RXCINTLVL_gm 0x30 /* Receive Interrupt Level group mask. */ -#define USART_RXCINTLVL_gp 4 /* Receive Interrupt Level group position. */ -#define USART_RXCINTLVL0_bm (1<<4) /* Receive Interrupt Level bit 0 mask. */ -#define USART_RXCINTLVL0_bp 4 /* Receive Interrupt Level bit 0 position. */ -#define USART_RXCINTLVL1_bm (1<<5) /* Receive Interrupt Level bit 1 mask. */ -#define USART_RXCINTLVL1_bp 5 /* Receive Interrupt Level bit 1 position. */ - -#define USART_TXCINTLVL_gm 0x0C /* Transmit Interrupt Level group mask. */ -#define USART_TXCINTLVL_gp 2 /* Transmit Interrupt Level group position. */ -#define USART_TXCINTLVL0_bm (1<<2) /* Transmit Interrupt Level bit 0 mask. */ -#define USART_TXCINTLVL0_bp 2 /* Transmit Interrupt Level bit 0 position. */ -#define USART_TXCINTLVL1_bm (1<<3) /* Transmit Interrupt Level bit 1 mask. */ -#define USART_TXCINTLVL1_bp 3 /* Transmit Interrupt Level bit 1 position. */ - -#define USART_DREINTLVL_gm 0x03 /* Data Register Empty Interrupt Level group mask. */ -#define USART_DREINTLVL_gp 0 /* Data Register Empty Interrupt Level group position. */ -#define USART_DREINTLVL0_bm (1<<0) /* Data Register Empty Interrupt Level bit 0 mask. */ -#define USART_DREINTLVL0_bp 0 /* Data Register Empty Interrupt Level bit 0 position. */ -#define USART_DREINTLVL1_bm (1<<1) /* Data Register Empty Interrupt Level bit 1 mask. */ -#define USART_DREINTLVL1_bp 1 /* Data Register Empty Interrupt Level bit 1 position. */ - -/* USART.CTRLB bit masks and bit positions */ -#define USART_RXEN_bm 0x10 /* Receiver Enable bit mask. */ -#define USART_RXEN_bp 4 /* Receiver Enable bit position. */ - -#define USART_TXEN_bm 0x08 /* Transmitter Enable bit mask. */ -#define USART_TXEN_bp 3 /* Transmitter Enable bit position. */ - -#define USART_CLK2X_bm 0x04 /* Double transmission speed bit mask. */ -#define USART_CLK2X_bp 2 /* Double transmission speed bit position. */ - -#define USART_MPCM_bm 0x02 /* Multi-processor Communication Mode bit mask. */ -#define USART_MPCM_bp 1 /* Multi-processor Communication Mode bit position. */ - -#define USART_TXB8_bm 0x01 /* Transmit bit 8 bit mask. */ -#define USART_TXB8_bp 0 /* Transmit bit 8 bit position. */ - -/* USART.CTRLC bit masks and bit positions */ -#define USART_CMODE_gm 0xC0 /* Communication Mode group mask. */ -#define USART_CMODE_gp 6 /* Communication Mode group position. */ -#define USART_CMODE0_bm (1<<6) /* Communication Mode bit 0 mask. */ -#define USART_CMODE0_bp 6 /* Communication Mode bit 0 position. */ -#define USART_CMODE1_bm (1<<7) /* Communication Mode bit 1 mask. */ -#define USART_CMODE1_bp 7 /* Communication Mode bit 1 position. */ - -#define USART_PMODE_gm 0x30 /* Parity Mode group mask. */ -#define USART_PMODE_gp 4 /* Parity Mode group position. */ -#define USART_PMODE0_bm (1<<4) /* Parity Mode bit 0 mask. */ -#define USART_PMODE0_bp 4 /* Parity Mode bit 0 position. */ -#define USART_PMODE1_bm (1<<5) /* Parity Mode bit 1 mask. */ -#define USART_PMODE1_bp 5 /* Parity Mode bit 1 position. */ - -#define USART_SBMODE_bm 0x08 /* Stop Bit Mode bit mask. */ -#define USART_SBMODE_bp 3 /* Stop Bit Mode bit position. */ - -#define USART_CHSIZE_gm 0x07 /* Character Size group mask. */ -#define USART_CHSIZE_gp 0 /* Character Size group position. */ -#define USART_CHSIZE0_bm (1<<0) /* Character Size bit 0 mask. */ -#define USART_CHSIZE0_bp 0 /* Character Size bit 0 position. */ -#define USART_CHSIZE1_bm (1<<1) /* Character Size bit 1 mask. */ -#define USART_CHSIZE1_bp 1 /* Character Size bit 1 position. */ -#define USART_CHSIZE2_bm (1<<2) /* Character Size bit 2 mask. */ -#define USART_CHSIZE2_bp 2 /* Character Size bit 2 position. */ - -/* USART.BAUDCTRLA bit masks and bit positions */ -#define USART_BSEL_gm 0xFF /* Baud Rate Selection Bits [7:0] group mask. */ -#define USART_BSEL_gp 0 /* Baud Rate Selection Bits [7:0] group position. */ -#define USART_BSEL0_bm (1<<0) /* Baud Rate Selection Bits [7:0] bit 0 mask. */ -#define USART_BSEL0_bp 0 /* Baud Rate Selection Bits [7:0] bit 0 position. */ -#define USART_BSEL1_bm (1<<1) /* Baud Rate Selection Bits [7:0] bit 1 mask. */ -#define USART_BSEL1_bp 1 /* Baud Rate Selection Bits [7:0] bit 1 position. */ -#define USART_BSEL2_bm (1<<2) /* Baud Rate Selection Bits [7:0] bit 2 mask. */ -#define USART_BSEL2_bp 2 /* Baud Rate Selection Bits [7:0] bit 2 position. */ -#define USART_BSEL3_bm (1<<3) /* Baud Rate Selection Bits [7:0] bit 3 mask. */ -#define USART_BSEL3_bp 3 /* Baud Rate Selection Bits [7:0] bit 3 position. */ -#define USART_BSEL4_bm (1<<4) /* Baud Rate Selection Bits [7:0] bit 4 mask. */ -#define USART_BSEL4_bp 4 /* Baud Rate Selection Bits [7:0] bit 4 position. */ -#define USART_BSEL5_bm (1<<5) /* Baud Rate Selection Bits [7:0] bit 5 mask. */ -#define USART_BSEL5_bp 5 /* Baud Rate Selection Bits [7:0] bit 5 position. */ -#define USART_BSEL6_bm (1<<6) /* Baud Rate Selection Bits [7:0] bit 6 mask. */ -#define USART_BSEL6_bp 6 /* Baud Rate Selection Bits [7:0] bit 6 position. */ -#define USART_BSEL7_bm (1<<7) /* Baud Rate Selection Bits [7:0] bit 7 mask. */ -#define USART_BSEL7_bp 7 /* Baud Rate Selection Bits [7:0] bit 7 position. */ - -/* USART.BAUDCTRLB bit masks and bit positions */ -#define USART_BSCALE_gm 0xF0 /* Baud Rate Scale group mask. */ -#define USART_BSCALE_gp 4 /* Baud Rate Scale group position. */ -#define USART_BSCALE0_bm (1<<4) /* Baud Rate Scale bit 0 mask. */ -#define USART_BSCALE0_bp 4 /* Baud Rate Scale bit 0 position. */ -#define USART_BSCALE1_bm (1<<5) /* Baud Rate Scale bit 1 mask. */ -#define USART_BSCALE1_bp 5 /* Baud Rate Scale bit 1 position. */ -#define USART_BSCALE2_bm (1<<6) /* Baud Rate Scale bit 2 mask. */ -#define USART_BSCALE2_bp 6 /* Baud Rate Scale bit 2 position. */ -#define USART_BSCALE3_bm (1<<7) /* Baud Rate Scale bit 3 mask. */ -#define USART_BSCALE3_bp 7 /* Baud Rate Scale bit 3 position. */ - -/* USART_BSEL Predefined. */ -/* USART_BSEL Predefined. */ - -/* SPI - Serial Peripheral Interface */ -/* SPI.CTRL bit masks and bit positions */ -#define SPI_CLK2X_bm 0x80 /* Enable Double Speed bit mask. */ -#define SPI_CLK2X_bp 7 /* Enable Double Speed bit position. */ - -#define SPI_ENABLE_bm 0x40 /* Enable Module bit mask. */ -#define SPI_ENABLE_bp 6 /* Enable Module bit position. */ - -#define SPI_DORD_bm 0x20 /* Data Order Setting bit mask. */ -#define SPI_DORD_bp 5 /* Data Order Setting bit position. */ - -#define SPI_MASTER_bm 0x10 /* Master Operation Enable bit mask. */ -#define SPI_MASTER_bp 4 /* Master Operation Enable bit position. */ - -#define SPI_MODE_gm 0x0C /* SPI Mode group mask. */ -#define SPI_MODE_gp 2 /* SPI Mode group position. */ -#define SPI_MODE0_bm (1<<2) /* SPI Mode bit 0 mask. */ -#define SPI_MODE0_bp 2 /* SPI Mode bit 0 position. */ -#define SPI_MODE1_bm (1<<3) /* SPI Mode bit 1 mask. */ -#define SPI_MODE1_bp 3 /* SPI Mode bit 1 position. */ - -#define SPI_PRESCALER_gm 0x03 /* Prescaler group mask. */ -#define SPI_PRESCALER_gp 0 /* Prescaler group position. */ -#define SPI_PRESCALER0_bm (1<<0) /* Prescaler bit 0 mask. */ -#define SPI_PRESCALER0_bp 0 /* Prescaler bit 0 position. */ -#define SPI_PRESCALER1_bm (1<<1) /* Prescaler bit 1 mask. */ -#define SPI_PRESCALER1_bp 1 /* Prescaler bit 1 position. */ - -/* SPI.INTCTRL bit masks and bit positions */ -#define SPI_INTLVL_gm 0x03 /* Interrupt level group mask. */ -#define SPI_INTLVL_gp 0 /* Interrupt level group position. */ -#define SPI_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */ -#define SPI_INTLVL0_bp 0 /* Interrupt level bit 0 position. */ -#define SPI_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */ -#define SPI_INTLVL1_bp 1 /* Interrupt level bit 1 position. */ - -/* SPI.STATUS bit masks and bit positions */ -#define SPI_IF_bm 0x80 /* Interrupt Flag bit mask. */ -#define SPI_IF_bp 7 /* Interrupt Flag bit position. */ - -#define SPI_WRCOL_bm 0x40 /* Write Collision bit mask. */ -#define SPI_WRCOL_bp 6 /* Write Collision bit position. */ - -/* IRCOM - IR Communication Module */ -/* IRCOM.CTRL bit masks and bit positions */ -#define IRCOM_EVSEL_gm 0x0F /* Event Channel Select group mask. */ -#define IRCOM_EVSEL_gp 0 /* Event Channel Select group position. */ -#define IRCOM_EVSEL0_bm (1<<0) /* Event Channel Select bit 0 mask. */ -#define IRCOM_EVSEL0_bp 0 /* Event Channel Select bit 0 position. */ -#define IRCOM_EVSEL1_bm (1<<1) /* Event Channel Select bit 1 mask. */ -#define IRCOM_EVSEL1_bp 1 /* Event Channel Select bit 1 position. */ -#define IRCOM_EVSEL2_bm (1<<2) /* Event Channel Select bit 2 mask. */ -#define IRCOM_EVSEL2_bp 2 /* Event Channel Select bit 2 position. */ -#define IRCOM_EVSEL3_bm (1<<3) /* Event Channel Select bit 3 mask. */ -#define IRCOM_EVSEL3_bp 3 /* Event Channel Select bit 3 position. */ - -/* FUSE - Fuses and Lockbits */ -/* NVM_FUSES.FUSEBYTE0 bit masks and bit positions */ -#define NVM_FUSES_JTAGUSERID_gm 0xFF /* JTAG User ID group mask. */ -#define NVM_FUSES_JTAGUSERID_gp 0 /* JTAG User ID group position. */ -#define NVM_FUSES_JTAGUSERID0_bm (1<<0) /* JTAG User ID bit 0 mask. */ -#define NVM_FUSES_JTAGUSERID0_bp 0 /* JTAG User ID bit 0 position. */ -#define NVM_FUSES_JTAGUSERID1_bm (1<<1) /* JTAG User ID bit 1 mask. */ -#define NVM_FUSES_JTAGUSERID1_bp 1 /* JTAG User ID bit 1 position. */ -#define NVM_FUSES_JTAGUSERID2_bm (1<<2) /* JTAG User ID bit 2 mask. */ -#define NVM_FUSES_JTAGUSERID2_bp 2 /* JTAG User ID bit 2 position. */ -#define NVM_FUSES_JTAGUSERID3_bm (1<<3) /* JTAG User ID bit 3 mask. */ -#define NVM_FUSES_JTAGUSERID3_bp 3 /* JTAG User ID bit 3 position. */ -#define NVM_FUSES_JTAGUSERID4_bm (1<<4) /* JTAG User ID bit 4 mask. */ -#define NVM_FUSES_JTAGUSERID4_bp 4 /* JTAG User ID bit 4 position. */ -#define NVM_FUSES_JTAGUSERID5_bm (1<<5) /* JTAG User ID bit 5 mask. */ -#define NVM_FUSES_JTAGUSERID5_bp 5 /* JTAG User ID bit 5 position. */ -#define NVM_FUSES_JTAGUSERID6_bm (1<<6) /* JTAG User ID bit 6 mask. */ -#define NVM_FUSES_JTAGUSERID6_bp 6 /* JTAG User ID bit 6 position. */ -#define NVM_FUSES_JTAGUSERID7_bm (1<<7) /* JTAG User ID bit 7 mask. */ -#define NVM_FUSES_JTAGUSERID7_bp 7 /* JTAG User ID bit 7 position. */ - -/* NVM_FUSES.FUSEBYTE1 bit masks and bit positions */ -#define NVM_FUSES_WDWP_gm 0xF0 /* Watchdog Window Timeout Period group mask. */ -#define NVM_FUSES_WDWP_gp 4 /* Watchdog Window Timeout Period group position. */ -#define NVM_FUSES_WDWP0_bm (1<<4) /* Watchdog Window Timeout Period bit 0 mask. */ -#define NVM_FUSES_WDWP0_bp 4 /* Watchdog Window Timeout Period bit 0 position. */ -#define NVM_FUSES_WDWP1_bm (1<<5) /* Watchdog Window Timeout Period bit 1 mask. */ -#define NVM_FUSES_WDWP1_bp 5 /* Watchdog Window Timeout Period bit 1 position. */ -#define NVM_FUSES_WDWP2_bm (1<<6) /* Watchdog Window Timeout Period bit 2 mask. */ -#define NVM_FUSES_WDWP2_bp 6 /* Watchdog Window Timeout Period bit 2 position. */ -#define NVM_FUSES_WDWP3_bm (1<<7) /* Watchdog Window Timeout Period bit 3 mask. */ -#define NVM_FUSES_WDWP3_bp 7 /* Watchdog Window Timeout Period bit 3 position. */ - -#define NVM_FUSES_WDP_gm 0x0F /* Watchdog Timeout Period group mask. */ -#define NVM_FUSES_WDP_gp 0 /* Watchdog Timeout Period group position. */ -#define NVM_FUSES_WDP0_bm (1<<0) /* Watchdog Timeout Period bit 0 mask. */ -#define NVM_FUSES_WDP0_bp 0 /* Watchdog Timeout Period bit 0 position. */ -#define NVM_FUSES_WDP1_bm (1<<1) /* Watchdog Timeout Period bit 1 mask. */ -#define NVM_FUSES_WDP1_bp 1 /* Watchdog Timeout Period bit 1 position. */ -#define NVM_FUSES_WDP2_bm (1<<2) /* Watchdog Timeout Period bit 2 mask. */ -#define NVM_FUSES_WDP2_bp 2 /* Watchdog Timeout Period bit 2 position. */ -#define NVM_FUSES_WDP3_bm (1<<3) /* Watchdog Timeout Period bit 3 mask. */ -#define NVM_FUSES_WDP3_bp 3 /* Watchdog Timeout Period bit 3 position. */ - -/* NVM_FUSES.FUSEBYTE2 bit masks and bit positions */ -#define NVM_FUSES_BOOTRST_bm 0x40 /* Boot Loader Section Reset Vector bit mask. */ -#define NVM_FUSES_BOOTRST_bp 6 /* Boot Loader Section Reset Vector bit position. */ - -#define NVM_FUSES_TOSCSEL_bm 0x20 /* Timer Oscillator pin location bit mask. */ -#define NVM_FUSES_TOSCSEL_bp 5 /* Timer Oscillator pin location bit position. */ - -#define NVM_FUSES_BODPD_gm 0x03 /* BOD Operation in Power-Down Mode group mask. */ -#define NVM_FUSES_BODPD_gp 0 /* BOD Operation in Power-Down Mode group position. */ -#define NVM_FUSES_BODPD0_bm (1<<0) /* BOD Operation in Power-Down Mode bit 0 mask. */ -#define NVM_FUSES_BODPD0_bp 0 /* BOD Operation in Power-Down Mode bit 0 position. */ -#define NVM_FUSES_BODPD1_bm (1<<1) /* BOD Operation in Power-Down Mode bit 1 mask. */ -#define NVM_FUSES_BODPD1_bp 1 /* BOD Operation in Power-Down Mode bit 1 position. */ - -/* NVM_FUSES.FUSEBYTE4 bit masks and bit positions */ -#define NVM_FUSES_RSTDISBL_bm 0x10 /* External Reset Disable bit mask. */ -#define NVM_FUSES_RSTDISBL_bp 4 /* External Reset Disable bit position. */ - -#define NVM_FUSES_SUT_gm 0x0C /* Start-up Time group mask. */ -#define NVM_FUSES_SUT_gp 2 /* Start-up Time group position. */ -#define NVM_FUSES_SUT0_bm (1<<2) /* Start-up Time bit 0 mask. */ -#define NVM_FUSES_SUT0_bp 2 /* Start-up Time bit 0 position. */ -#define NVM_FUSES_SUT1_bm (1<<3) /* Start-up Time bit 1 mask. */ -#define NVM_FUSES_SUT1_bp 3 /* Start-up Time bit 1 position. */ - -#define NVM_FUSES_WDLOCK_bm 0x02 /* Watchdog Timer Lock bit mask. */ -#define NVM_FUSES_WDLOCK_bp 1 /* Watchdog Timer Lock bit position. */ - -#define NVM_FUSES_JTAGEN_bm 0x01 /* JTAG Interface Enable bit mask. */ -#define NVM_FUSES_JTAGEN_bp 0 /* JTAG Interface Enable bit position. */ - -/* NVM_FUSES.FUSEBYTE5 bit masks and bit positions */ -#define NVM_FUSES_BODACT_gm 0x30 /* BOD Operation in Active Mode group mask. */ -#define NVM_FUSES_BODACT_gp 4 /* BOD Operation in Active Mode group position. */ -#define NVM_FUSES_BODACT0_bm (1<<4) /* BOD Operation in Active Mode bit 0 mask. */ -#define NVM_FUSES_BODACT0_bp 4 /* BOD Operation in Active Mode bit 0 position. */ -#define NVM_FUSES_BODACT1_bm (1<<5) /* BOD Operation in Active Mode bit 1 mask. */ -#define NVM_FUSES_BODACT1_bp 5 /* BOD Operation in Active Mode bit 1 position. */ - -#define NVM_FUSES_EESAVE_bm 0x08 /* Preserve EEPROM Through Chip Erase bit mask. */ -#define NVM_FUSES_EESAVE_bp 3 /* Preserve EEPROM Through Chip Erase bit position. */ - -#define NVM_FUSES_BODLVL_gm 0x07 /* Brownout Detection Voltage Level group mask. */ -#define NVM_FUSES_BODLVL_gp 0 /* Brownout Detection Voltage Level group position. */ -#define NVM_FUSES_BODLVL0_bm (1<<0) /* Brownout Detection Voltage Level bit 0 mask. */ -#define NVM_FUSES_BODLVL0_bp 0 /* Brownout Detection Voltage Level bit 0 position. */ -#define NVM_FUSES_BODLVL1_bm (1<<1) /* Brownout Detection Voltage Level bit 1 mask. */ -#define NVM_FUSES_BODLVL1_bp 1 /* Brownout Detection Voltage Level bit 1 position. */ -#define NVM_FUSES_BODLVL2_bm (1<<2) /* Brownout Detection Voltage Level bit 2 mask. */ -#define NVM_FUSES_BODLVL2_bp 2 /* Brownout Detection Voltage Level bit 2 position. */ - -/* LOCKBIT - Fuses and Lockbits */ -/* NVM_LOCKBITS.LOCKBITS bit masks and bit positions */ -#define NVM_LOCKBITS_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ -#define NVM_LOCKBITS_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ -#define NVM_LOCKBITS_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ -#define NVM_LOCKBITS_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ -#define NVM_LOCKBITS_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ -#define NVM_LOCKBITS_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ - -#define NVM_LOCKBITS_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ -#define NVM_LOCKBITS_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ -#define NVM_LOCKBITS_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ -#define NVM_LOCKBITS_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ -#define NVM_LOCKBITS_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ -#define NVM_LOCKBITS_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ - -#define NVM_LOCKBITS_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ -#define NVM_LOCKBITS_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ -#define NVM_LOCKBITS_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ -#define NVM_LOCKBITS_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ -#define NVM_LOCKBITS_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ -#define NVM_LOCKBITS_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ - -#define NVM_LOCKBITS_LB_gm 0x03 /* Lock Bits group mask. */ -#define NVM_LOCKBITS_LB_gp 0 /* Lock Bits group position. */ -#define NVM_LOCKBITS_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ -#define NVM_LOCKBITS_LB0_bp 0 /* Lock Bits bit 0 position. */ -#define NVM_LOCKBITS_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ -#define NVM_LOCKBITS_LB1_bp 1 /* Lock Bits bit 1 position. */ - - - -// Generic Port Pins - -#define PIN0_bm 0x01 -#define PIN0_bp 0 -#define PIN1_bm 0x02 -#define PIN1_bp 1 -#define PIN2_bm 0x04 -#define PIN2_bp 2 -#define PIN3_bm 0x08 -#define PIN3_bp 3 -#define PIN4_bm 0x10 -#define PIN4_bp 4 -#define PIN5_bm 0x20 -#define PIN5_bp 5 -#define PIN6_bm 0x40 -#define PIN6_bp 6 -#define PIN7_bm 0x80 -#define PIN7_bp 7 - -/* ========== Interrupt Vector Definitions ========== */ -/* Vector 0 is the reset vector */ - -/* OSC interrupt vectors */ -#define OSC_OSCF_vect_num 1 -#define OSC_OSCF_vect _VECTOR(1) /* Oscillator Failure Interrupt (NMI) */ - -/* PORTC interrupt vectors */ -#define PORTC_INT0_vect_num 2 -#define PORTC_INT0_vect _VECTOR(2) /* External Interrupt 0 */ -#define PORTC_INT1_vect_num 3 -#define PORTC_INT1_vect _VECTOR(3) /* External Interrupt 1 */ - -/* PORTR interrupt vectors */ -#define PORTR_INT0_vect_num 4 -#define PORTR_INT0_vect _VECTOR(4) /* External Interrupt 0 */ -#define PORTR_INT1_vect_num 5 -#define PORTR_INT1_vect _VECTOR(5) /* External Interrupt 1 */ - -/* DMA interrupt vectors */ -#define DMA_CH0_vect_num 6 -#define DMA_CH0_vect _VECTOR(6) /* Channel 0 Interrupt */ -#define DMA_CH1_vect_num 7 -#define DMA_CH1_vect _VECTOR(7) /* Channel 1 Interrupt */ -#define DMA_CH2_vect_num 8 -#define DMA_CH2_vect _VECTOR(8) /* Channel 2 Interrupt */ -#define DMA_CH3_vect_num 9 -#define DMA_CH3_vect _VECTOR(9) /* Channel 3 Interrupt */ - -/* RTC interrupt vectors */ -#define RTC_OVF_vect_num 10 -#define RTC_OVF_vect _VECTOR(10) /* Overflow Interrupt */ -#define RTC_COMP_vect_num 11 -#define RTC_COMP_vect _VECTOR(11) /* Compare Interrupt */ - -/* TWIC interrupt vectors */ -#define TWIC_TWIS_vect_num 12 -#define TWIC_TWIS_vect _VECTOR(12) /* TWI Slave Interrupt */ -#define TWIC_TWIM_vect_num 13 -#define TWIC_TWIM_vect _VECTOR(13) /* TWI Master Interrupt */ - -/* TCC0 interrupt vectors */ -#define TCC0_OVF_vect_num 14 -#define TCC0_OVF_vect _VECTOR(14) /* Overflow Interrupt */ - -/* TCC2 interrupt vectors */ -#define TCC2_LUNF_vect_num 14 -#define TCC2_LUNF_vect _VECTOR(14) /* Low Byte Underflow Interrupt */ - -/* TCC0 interrupt vectors */ -#define TCC0_ERR_vect_num 15 -#define TCC0_ERR_vect _VECTOR(15) /* Error Interrupt */ - -/* TCC2 interrupt vectors */ -#define TCC2_HUNF_vect_num 15 -#define TCC2_HUNF_vect _VECTOR(15) /* High Byte Underflow Interrupt */ - -/* TCC0 interrupt vectors */ -#define TCC0_CCA_vect_num 16 -#define TCC0_CCA_vect _VECTOR(16) /* Compare or Capture A Interrupt */ - -/* TCC2 interrupt vectors */ -#define TCC2_LCMPA_vect_num 16 -#define TCC2_LCMPA_vect _VECTOR(16) /* Low Byte Compare A Interrupt */ - -/* TCC0 interrupt vectors */ -#define TCC0_CCB_vect_num 17 -#define TCC0_CCB_vect _VECTOR(17) /* Compare or Capture B Interrupt */ - -/* TCC2 interrupt vectors */ -#define TCC2_LCMPB_vect_num 17 -#define TCC2_LCMPB_vect _VECTOR(17) /* Low Byte Compare B Interrupt */ - -/* TCC0 interrupt vectors */ -#define TCC0_CCC_vect_num 18 -#define TCC0_CCC_vect _VECTOR(18) /* Compare or Capture C Interrupt */ - -/* TCC2 interrupt vectors */ -#define TCC2_LCMPC_vect_num 18 -#define TCC2_LCMPC_vect _VECTOR(18) /* Low Byte Compare C Interrupt */ - -/* TCC0 interrupt vectors */ -#define TCC0_CCD_vect_num 19 -#define TCC0_CCD_vect _VECTOR(19) /* Compare or Capture D Interrupt */ - -/* TCC2 interrupt vectors */ -#define TCC2_LCMPD_vect_num 19 -#define TCC2_LCMPD_vect _VECTOR(19) /* Low Byte Compare D Interrupt */ - -/* TCC1 interrupt vectors */ -#define TCC1_OVF_vect_num 20 -#define TCC1_OVF_vect _VECTOR(20) /* Overflow Interrupt */ -#define TCC1_ERR_vect_num 21 -#define TCC1_ERR_vect _VECTOR(21) /* Error Interrupt */ -#define TCC1_CCA_vect_num 22 -#define TCC1_CCA_vect _VECTOR(22) /* Compare or Capture A Interrupt */ -#define TCC1_CCB_vect_num 23 -#define TCC1_CCB_vect _VECTOR(23) /* Compare or Capture B Interrupt */ - -/* SPIC interrupt vectors */ -#define SPIC_INT_vect_num 24 -#define SPIC_INT_vect _VECTOR(24) /* SPI Interrupt */ - -/* USARTC0 interrupt vectors */ -#define USARTC0_RXC_vect_num 25 -#define USARTC0_RXC_vect _VECTOR(25) /* Reception Complete Interrupt */ -#define USARTC0_DRE_vect_num 26 -#define USARTC0_DRE_vect _VECTOR(26) /* Data Register Empty Interrupt */ -#define USARTC0_TXC_vect_num 27 -#define USARTC0_TXC_vect _VECTOR(27) /* Transmission Complete Interrupt */ - -/* USARTC1 interrupt vectors */ -#define USARTC1_RXC_vect_num 28 -#define USARTC1_RXC_vect _VECTOR(28) /* Reception Complete Interrupt */ -#define USARTC1_DRE_vect_num 29 -#define USARTC1_DRE_vect _VECTOR(29) /* Data Register Empty Interrupt */ -#define USARTC1_TXC_vect_num 30 -#define USARTC1_TXC_vect _VECTOR(30) /* Transmission Complete Interrupt */ - -/* AES interrupt vectors */ -#define AES_INT_vect_num 31 -#define AES_INT_vect _VECTOR(31) /* AES Interrupt */ - -/* NVM interrupt vectors */ -#define NVM_EE_vect_num 32 -#define NVM_EE_vect _VECTOR(32) /* EE Interrupt */ -#define NVM_SPM_vect_num 33 -#define NVM_SPM_vect _VECTOR(33) /* SPM Interrupt */ - -/* PORTB interrupt vectors */ -#define PORTB_INT0_vect_num 34 -#define PORTB_INT0_vect _VECTOR(34) /* External Interrupt 0 */ -#define PORTB_INT1_vect_num 35 -#define PORTB_INT1_vect _VECTOR(35) /* External Interrupt 1 */ - -/* ACB interrupt vectors */ -#define ACB_AC0_vect_num 36 -#define ACB_AC0_vect _VECTOR(36) /* AC0 Interrupt */ -#define ACB_AC1_vect_num 37 -#define ACB_AC1_vect _VECTOR(37) /* AC1 Interrupt */ -#define ACB_ACW_vect_num 38 -#define ACB_ACW_vect _VECTOR(38) /* ACW Window Mode Interrupt */ - -/* ADCB interrupt vectors */ -#define ADCB_CH0_vect_num 39 -#define ADCB_CH0_vect _VECTOR(39) /* Interrupt 0 */ -#define ADCB_CH1_vect_num 40 -#define ADCB_CH1_vect _VECTOR(40) /* Interrupt 1 */ -#define ADCB_CH2_vect_num 41 -#define ADCB_CH2_vect _VECTOR(41) /* Interrupt 2 */ -#define ADCB_CH3_vect_num 42 -#define ADCB_CH3_vect _VECTOR(42) /* Interrupt 3 */ - -/* PORTE interrupt vectors */ -#define PORTE_INT0_vect_num 43 -#define PORTE_INT0_vect _VECTOR(43) /* External Interrupt 0 */ -#define PORTE_INT1_vect_num 44 -#define PORTE_INT1_vect _VECTOR(44) /* External Interrupt 1 */ - -/* TWIE interrupt vectors */ -#define TWIE_TWIS_vect_num 45 -#define TWIE_TWIS_vect _VECTOR(45) /* TWI Slave Interrupt */ -#define TWIE_TWIM_vect_num 46 -#define TWIE_TWIM_vect _VECTOR(46) /* TWI Master Interrupt */ - -/* TCE0 interrupt vectors */ -#define TCE0_OVF_vect_num 47 -#define TCE0_OVF_vect _VECTOR(47) /* Overflow Interrupt */ - -/* TCE2 interrupt vectors */ -#define TCE2_LUNF_vect_num 47 -#define TCE2_LUNF_vect _VECTOR(47) /* Low Byte Underflow Interrupt */ - -/* TCE0 interrupt vectors */ -#define TCE0_ERR_vect_num 48 -#define TCE0_ERR_vect _VECTOR(48) /* Error Interrupt */ - -/* TCE2 interrupt vectors */ -#define TCE2_HUNF_vect_num 48 -#define TCE2_HUNF_vect _VECTOR(48) /* High Byte Underflow Interrupt */ - -/* TCE0 interrupt vectors */ -#define TCE0_CCA_vect_num 49 -#define TCE0_CCA_vect _VECTOR(49) /* Compare or Capture A Interrupt */ - -/* TCE2 interrupt vectors */ -#define TCE2_LCMPA_vect_num 49 -#define TCE2_LCMPA_vect _VECTOR(49) /* Low Byte Compare A Interrupt */ - -/* TCE0 interrupt vectors */ -#define TCE0_CCB_vect_num 50 -#define TCE0_CCB_vect _VECTOR(50) /* Compare or Capture B Interrupt */ - -/* TCE2 interrupt vectors */ -#define TCE2_LCMPB_vect_num 50 -#define TCE2_LCMPB_vect _VECTOR(50) /* Low Byte Compare B Interrupt */ - -/* TCE0 interrupt vectors */ -#define TCE0_CCC_vect_num 51 -#define TCE0_CCC_vect _VECTOR(51) /* Compare or Capture C Interrupt */ - -/* TCE2 interrupt vectors */ -#define TCE2_LCMPC_vect_num 51 -#define TCE2_LCMPC_vect _VECTOR(51) /* Low Byte Compare C Interrupt */ - -/* TCE0 interrupt vectors */ -#define TCE0_CCD_vect_num 52 -#define TCE0_CCD_vect _VECTOR(52) /* Compare or Capture D Interrupt */ - -/* TCE2 interrupt vectors */ -#define TCE2_LCMPD_vect_num 52 -#define TCE2_LCMPD_vect _VECTOR(52) /* Low Byte Compare D Interrupt */ - -/* TCE1 interrupt vectors */ -#define TCE1_OVF_vect_num 53 -#define TCE1_OVF_vect _VECTOR(53) /* Overflow Interrupt */ -#define TCE1_ERR_vect_num 54 -#define TCE1_ERR_vect _VECTOR(54) /* Error Interrupt */ -#define TCE1_CCA_vect_num 55 -#define TCE1_CCA_vect _VECTOR(55) /* Compare or Capture A Interrupt */ -#define TCE1_CCB_vect_num 56 -#define TCE1_CCB_vect _VECTOR(56) /* Compare or Capture B Interrupt */ - -/* SPIE interrupt vectors */ -#define SPIE_INT_vect_num 57 -#define SPIE_INT_vect _VECTOR(57) /* SPI Interrupt */ - -/* USARTE0 interrupt vectors */ -#define USARTE0_RXC_vect_num 58 -#define USARTE0_RXC_vect _VECTOR(58) /* Reception Complete Interrupt */ -#define USARTE0_DRE_vect_num 59 -#define USARTE0_DRE_vect _VECTOR(59) /* Data Register Empty Interrupt */ -#define USARTE0_TXC_vect_num 60 -#define USARTE0_TXC_vect _VECTOR(60) /* Transmission Complete Interrupt */ - -/* USARTE1 interrupt vectors */ -#define USARTE1_RXC_vect_num 61 -#define USARTE1_RXC_vect _VECTOR(61) /* Reception Complete Interrupt */ -#define USARTE1_DRE_vect_num 62 -#define USARTE1_DRE_vect _VECTOR(62) /* Data Register Empty Interrupt */ -#define USARTE1_TXC_vect_num 63 -#define USARTE1_TXC_vect _VECTOR(63) /* Transmission Complete Interrupt */ - -/* PORTD interrupt vectors */ -#define PORTD_INT0_vect_num 64 -#define PORTD_INT0_vect _VECTOR(64) /* External Interrupt 0 */ -#define PORTD_INT1_vect_num 65 -#define PORTD_INT1_vect _VECTOR(65) /* External Interrupt 1 */ - -/* PORTA interrupt vectors */ -#define PORTA_INT0_vect_num 66 -#define PORTA_INT0_vect _VECTOR(66) /* External Interrupt 0 */ -#define PORTA_INT1_vect_num 67 -#define PORTA_INT1_vect _VECTOR(67) /* External Interrupt 1 */ - -/* ACA interrupt vectors */ -#define ACA_AC0_vect_num 68 -#define ACA_AC0_vect _VECTOR(68) /* AC0 Interrupt */ -#define ACA_AC1_vect_num 69 -#define ACA_AC1_vect _VECTOR(69) /* AC1 Interrupt */ -#define ACA_ACW_vect_num 70 -#define ACA_ACW_vect _VECTOR(70) /* ACW Window Mode Interrupt */ - -/* ADCA interrupt vectors */ -#define ADCA_CH0_vect_num 71 -#define ADCA_CH0_vect _VECTOR(71) /* Interrupt 0 */ -#define ADCA_CH1_vect_num 72 -#define ADCA_CH1_vect _VECTOR(72) /* Interrupt 1 */ -#define ADCA_CH2_vect_num 73 -#define ADCA_CH2_vect _VECTOR(73) /* Interrupt 2 */ -#define ADCA_CH3_vect_num 74 -#define ADCA_CH3_vect _VECTOR(74) /* Interrupt 3 */ - -/* TWID interrupt vectors */ -#define TWID_TWIS_vect_num 75 -#define TWID_TWIS_vect _VECTOR(75) /* TWI Slave Interrupt */ -#define TWID_TWIM_vect_num 76 -#define TWID_TWIM_vect _VECTOR(76) /* TWI Master Interrupt */ - -/* TCD0 interrupt vectors */ -#define TCD0_OVF_vect_num 77 -#define TCD0_OVF_vect _VECTOR(77) /* Overflow Interrupt */ - -/* TCD2 interrupt vectors */ -#define TCD2_LUNF_vect_num 77 -#define TCD2_LUNF_vect _VECTOR(77) /* Low Byte Underflow Interrupt */ - -/* TCD0 interrupt vectors */ -#define TCD0_ERR_vect_num 78 -#define TCD0_ERR_vect _VECTOR(78) /* Error Interrupt */ - -/* TCD2 interrupt vectors */ -#define TCD2_HUNF_vect_num 78 -#define TCD2_HUNF_vect _VECTOR(78) /* High Byte Underflow Interrupt */ - -/* TCD0 interrupt vectors */ -#define TCD0_CCA_vect_num 79 -#define TCD0_CCA_vect _VECTOR(79) /* Compare or Capture A Interrupt */ - -/* TCD2 interrupt vectors */ -#define TCD2_LCMPA_vect_num 79 -#define TCD2_LCMPA_vect _VECTOR(79) /* Low Byte Compare A Interrupt */ - -/* TCD0 interrupt vectors */ -#define TCD0_CCB_vect_num 80 -#define TCD0_CCB_vect _VECTOR(80) /* Compare or Capture B Interrupt */ - -/* TCD2 interrupt vectors */ -#define TCD2_LCMPB_vect_num 80 -#define TCD2_LCMPB_vect _VECTOR(80) /* Low Byte Compare B Interrupt */ - -/* TCD0 interrupt vectors */ -#define TCD0_CCC_vect_num 81 -#define TCD0_CCC_vect _VECTOR(81) /* Compare or Capture C Interrupt */ - -/* TCD2 interrupt vectors */ -#define TCD2_LCMPC_vect_num 81 -#define TCD2_LCMPC_vect _VECTOR(81) /* Low Byte Compare C Interrupt */ - -/* TCD0 interrupt vectors */ -#define TCD0_CCD_vect_num 82 -#define TCD0_CCD_vect _VECTOR(82) /* Compare or Capture D Interrupt */ - -/* TCD2 interrupt vectors */ -#define TCD2_LCMPD_vect_num 82 -#define TCD2_LCMPD_vect _VECTOR(82) /* Low Byte Compare D Interrupt */ - -/* TCD1 interrupt vectors */ -#define TCD1_OVF_vect_num 83 -#define TCD1_OVF_vect _VECTOR(83) /* Overflow Interrupt */ -#define TCD1_ERR_vect_num 84 -#define TCD1_ERR_vect _VECTOR(84) /* Error Interrupt */ -#define TCD1_CCA_vect_num 85 -#define TCD1_CCA_vect _VECTOR(85) /* Compare or Capture A Interrupt */ -#define TCD1_CCB_vect_num 86 -#define TCD1_CCB_vect _VECTOR(86) /* Compare or Capture B Interrupt */ - -/* SPID interrupt vectors */ -#define SPID_INT_vect_num 87 -#define SPID_INT_vect _VECTOR(87) /* SPI Interrupt */ - -/* USARTD0 interrupt vectors */ -#define USARTD0_RXC_vect_num 88 -#define USARTD0_RXC_vect _VECTOR(88) /* Reception Complete Interrupt */ -#define USARTD0_DRE_vect_num 89 -#define USARTD0_DRE_vect _VECTOR(89) /* Data Register Empty Interrupt */ -#define USARTD0_TXC_vect_num 90 -#define USARTD0_TXC_vect _VECTOR(90) /* Transmission Complete Interrupt */ - -/* USARTD1 interrupt vectors */ -#define USARTD1_RXC_vect_num 91 -#define USARTD1_RXC_vect _VECTOR(91) /* Reception Complete Interrupt */ -#define USARTD1_DRE_vect_num 92 -#define USARTD1_DRE_vect _VECTOR(92) /* Data Register Empty Interrupt */ -#define USARTD1_TXC_vect_num 93 -#define USARTD1_TXC_vect _VECTOR(93) /* Transmission Complete Interrupt */ - -/* PORTQ interrupt vectors */ -#define PORTQ_INT0_vect_num 94 -#define PORTQ_INT0_vect _VECTOR(94) /* External Interrupt 0 */ -#define PORTQ_INT1_vect_num 95 -#define PORTQ_INT1_vect _VECTOR(95) /* External Interrupt 1 */ - -/* PORTH interrupt vectors */ -#define PORTH_INT0_vect_num 96 -#define PORTH_INT0_vect _VECTOR(96) /* External Interrupt 0 */ -#define PORTH_INT1_vect_num 97 -#define PORTH_INT1_vect _VECTOR(97) /* External Interrupt 1 */ - -/* PORTJ interrupt vectors */ -#define PORTJ_INT0_vect_num 98 -#define PORTJ_INT0_vect _VECTOR(98) /* External Interrupt 0 */ -#define PORTJ_INT1_vect_num 99 -#define PORTJ_INT1_vect _VECTOR(99) /* External Interrupt 1 */ - -/* PORTK interrupt vectors */ -#define PORTK_INT0_vect_num 100 -#define PORTK_INT0_vect _VECTOR(100) /* External Interrupt 0 */ -#define PORTK_INT1_vect_num 101 -#define PORTK_INT1_vect _VECTOR(101) /* External Interrupt 1 */ - -/* PORTF interrupt vectors */ -#define PORTF_INT0_vect_num 104 -#define PORTF_INT0_vect _VECTOR(104) /* External Interrupt 0 */ -#define PORTF_INT1_vect_num 105 -#define PORTF_INT1_vect _VECTOR(105) /* External Interrupt 1 */ - -/* TWIF interrupt vectors */ -#define TWIF_TWIS_vect_num 106 -#define TWIF_TWIS_vect _VECTOR(106) /* TWI Slave Interrupt */ -#define TWIF_TWIM_vect_num 107 -#define TWIF_TWIM_vect _VECTOR(107) /* TWI Master Interrupt */ - -/* TCF0 interrupt vectors */ -#define TCF0_OVF_vect_num 108 -#define TCF0_OVF_vect _VECTOR(108) /* Overflow Interrupt */ - -/* TCF2 interrupt vectors */ -#define TCF2_LUNF_vect_num 108 -#define TCF2_LUNF_vect _VECTOR(108) /* Low Byte Underflow Interrupt */ - -/* TCF0 interrupt vectors */ -#define TCF0_ERR_vect_num 109 -#define TCF0_ERR_vect _VECTOR(109) /* Error Interrupt */ - -/* TCF2 interrupt vectors */ -#define TCF2_HUNF_vect_num 109 -#define TCF2_HUNF_vect _VECTOR(109) /* High Byte Underflow Interrupt */ - -/* TCF0 interrupt vectors */ -#define TCF0_CCA_vect_num 110 -#define TCF0_CCA_vect _VECTOR(110) /* Compare or Capture A Interrupt */ - -/* TCF2 interrupt vectors */ -#define TCF2_LCMPA_vect_num 110 -#define TCF2_LCMPA_vect _VECTOR(110) /* Low Byte Compare A Interrupt */ - -/* TCF0 interrupt vectors */ -#define TCF0_CCB_vect_num 111 -#define TCF0_CCB_vect _VECTOR(111) /* Compare or Capture B Interrupt */ - -/* TCF2 interrupt vectors */ -#define TCF2_LCMPB_vect_num 111 -#define TCF2_LCMPB_vect _VECTOR(111) /* Low Byte Compare B Interrupt */ - -/* TCF0 interrupt vectors */ -#define TCF0_CCC_vect_num 112 -#define TCF0_CCC_vect _VECTOR(112) /* Compare or Capture C Interrupt */ - -/* TCF2 interrupt vectors */ -#define TCF2_LCMPC_vect_num 112 -#define TCF2_LCMPC_vect _VECTOR(112) /* Low Byte Compare C Interrupt */ - -/* TCF0 interrupt vectors */ -#define TCF0_CCD_vect_num 113 -#define TCF0_CCD_vect _VECTOR(113) /* Compare or Capture D Interrupt */ - -/* TCF2 interrupt vectors */ -#define TCF2_LCMPD_vect_num 113 -#define TCF2_LCMPD_vect _VECTOR(113) /* Low Byte Compare D Interrupt */ - -/* TCF1 interrupt vectors */ -#define TCF1_OVF_vect_num 114 -#define TCF1_OVF_vect _VECTOR(114) /* Overflow Interrupt */ -#define TCF1_ERR_vect_num 115 -#define TCF1_ERR_vect _VECTOR(115) /* Error Interrupt */ -#define TCF1_CCA_vect_num 116 -#define TCF1_CCA_vect _VECTOR(116) /* Compare or Capture A Interrupt */ -#define TCF1_CCB_vect_num 117 -#define TCF1_CCB_vect _VECTOR(117) /* Compare or Capture B Interrupt */ - -/* SPIF interrupt vectors */ -#define SPIF_INT_vect_num 118 -#define SPIF_INT_vect _VECTOR(118) /* SPI Interrupt */ - -/* USARTF0 interrupt vectors */ -#define USARTF0_RXC_vect_num 119 -#define USARTF0_RXC_vect _VECTOR(119) /* Reception Complete Interrupt */ -#define USARTF0_DRE_vect_num 120 -#define USARTF0_DRE_vect _VECTOR(120) /* Data Register Empty Interrupt */ -#define USARTF0_TXC_vect_num 121 -#define USARTF0_TXC_vect _VECTOR(121) /* Transmission Complete Interrupt */ - -/* USARTF1 interrupt vectors */ -#define USARTF1_RXC_vect_num 122 -#define USARTF1_RXC_vect _VECTOR(122) /* Reception Complete Interrupt */ -#define USARTF1_DRE_vect_num 123 -#define USARTF1_DRE_vect _VECTOR(123) /* Data Register Empty Interrupt */ -#define USARTF1_TXC_vect_num 124 -#define USARTF1_TXC_vect _VECTOR(124) /* Transmission Complete Interrupt */ - -/* USB interrupt vectors */ -#define USB_BUSEVENT_vect_num 125 -#define USB_BUSEVENT_vect _VECTOR(125) /* SOF, suspend, resume, reset bus event interrupts, crc, underflow, overflow and stall error interrupts */ -#define USB_TRNCOMPL_vect_num 126 -#define USB_TRNCOMPL_vect _VECTOR(126) /* Transaction complete interrupt */ - -#define _VECTOR_SIZE 4 /* Size of individual vector. */ -#define _VECTORS_SIZE (127 * _VECTOR_SIZE) - - -/* ========== Constants ========== */ - -#define PROGMEM_START (0x0000) -#define PROGMEM_SIZE (69632) -#define PROGMEM_END (PROGMEM_START + PROGMEM_SIZE - 1) - -#define APP_SECTION_START (0x0000) -#define APP_SECTION_SIZE (65536) -#define APP_SECTION_PAGE_SIZE (256) -#define APP_SECTION_END (APP_SECTION_START + APP_SECTION_SIZE - 1) - -#define APPTABLE_SECTION_START (0xF000) -#define APPTABLE_SECTION_SIZE (4096) -#define APPTABLE_SECTION_PAGE_SIZE (256) -#define APPTABLE_SECTION_END (APPTABLE_SECTION_START + APPTABLE_SECTION_SIZE - 1) - -#define BOOT_SECTION_START (0x10000) -#define BOOT_SECTION_SIZE (4096) -#define BOOT_SECTION_PAGE_SIZE (256) -#define BOOT_SECTION_END (BOOT_SECTION_START + BOOT_SECTION_SIZE - 1) - -#define DATAMEM_START (0x0000) -#define DATAMEM_SIZE (16777216) -#define DATAMEM_END (DATAMEM_START + DATAMEM_SIZE - 1) - -#define IO_START (0x0000) -#define IO_SIZE (4096) -#define IO_PAGE_SIZE (0) -#define IO_END (IO_START + IO_SIZE - 1) - -#define MAPPED_EEPROM_START (0x1000) -#define MAPPED_EEPROM_SIZE (2048) -#define MAPPED_EEPROM_PAGE_SIZE (0) -#define MAPPED_EEPROM_END (MAPPED_EEPROM_START + MAPPED_EEPROM_SIZE - 1) - -#define INTERNAL_SRAM_START (0x2000) -#define INTERNAL_SRAM_SIZE (4096) -#define INTERNAL_SRAM_PAGE_SIZE (0) -#define INTERNAL_SRAM_END (INTERNAL_SRAM_START + INTERNAL_SRAM_SIZE - 1) - -#define EEPROM_START (0x0000) -#define EEPROM_SIZE (2048) -#define EEPROM_PAGE_SIZE (32) -#define EEPROM_END (EEPROM_START + EEPROM_SIZE - 1) - -#define SIGNATURES_START (0x0000) -#define SIGNATURES_SIZE (3) -#define SIGNATURES_PAGE_SIZE (0) -#define SIGNATURES_END (SIGNATURES_START + SIGNATURES_SIZE - 1) - -#define FUSES_START (0x0000) -#define FUSES_SIZE (6) -#define FUSES_PAGE_SIZE (0) -#define FUSES_END (FUSES_START + FUSES_SIZE - 1) - -#define LOCKBITS_START (0x0000) -#define LOCKBITS_SIZE (1) -#define LOCKBITS_PAGE_SIZE (0) -#define LOCKBITS_END (LOCKBITS_START + LOCKBITS_SIZE - 1) - -#define USER_SIGNATURES_START (0x0000) -#define USER_SIGNATURES_SIZE (256) -#define USER_SIGNATURES_PAGE_SIZE (256) -#define USER_SIGNATURES_END (USER_SIGNATURES_START + USER_SIGNATURES_SIZE - 1) - -#define PROD_SIGNATURES_START (0x0000) -#define PROD_SIGNATURES_SIZE (64) -#define PROD_SIGNATURES_PAGE_SIZE (256) -#define PROD_SIGNATURES_END (PROD_SIGNATURES_START + PROD_SIGNATURES_SIZE - 1) - -#define FLASHSTART PROGMEM_START -#define FLASHEND PROGMEM_END -#define SPM_PAGESIZE 256 -#define RAMSTART INTERNAL_SRAM_START -#define RAMSIZE INTERNAL_SRAM_SIZE -#define RAMEND INTERNAL_SRAM_END -#define E2END EEPROM_END -#define E2PAGESIZE EEPROM_PAGE_SIZE - - -/* ========== Fuses ========== */ -#define FUSE_MEMORY_SIZE 6 - -/* Fuse Byte 0 */ -#define FUSE_JTAGUSERID0 (unsigned char)~_BV(0) /* JTAG User ID Bit 0 */ -#define FUSE_JTAGUSERID1 (unsigned char)~_BV(1) /* JTAG User ID Bit 1 */ -#define FUSE_JTAGUSERID2 (unsigned char)~_BV(2) /* JTAG User ID Bit 2 */ -#define FUSE_JTAGUSERID3 (unsigned char)~_BV(3) /* JTAG User ID Bit 3 */ -#define FUSE_JTAGUSERID4 (unsigned char)~_BV(4) /* JTAG User ID Bit 4 */ -#define FUSE_JTAGUSERID5 (unsigned char)~_BV(5) /* JTAG User ID Bit 5 */ -#define FUSE_JTAGUSERID6 (unsigned char)~_BV(6) /* JTAG User ID Bit 6 */ -#define FUSE_JTAGUSERID7 (unsigned char)~_BV(7) /* JTAG User ID Bit 7 */ -#define FUSE0_DEFAULT (0xFF) - -/* Fuse Byte 1 */ -#define FUSE_WDP0 (unsigned char)~_BV(0) /* Watchdog Timeout Period Bit 0 */ -#define FUSE_WDP1 (unsigned char)~_BV(1) /* Watchdog Timeout Period Bit 1 */ -#define FUSE_WDP2 (unsigned char)~_BV(2) /* Watchdog Timeout Period Bit 2 */ -#define FUSE_WDP3 (unsigned char)~_BV(3) /* Watchdog Timeout Period Bit 3 */ -#define FUSE_WDWP0 (unsigned char)~_BV(4) /* Watchdog Window Timeout Period Bit 0 */ -#define FUSE_WDWP1 (unsigned char)~_BV(5) /* Watchdog Window Timeout Period Bit 1 */ -#define FUSE_WDWP2 (unsigned char)~_BV(6) /* Watchdog Window Timeout Period Bit 2 */ -#define FUSE_WDWP3 (unsigned char)~_BV(7) /* Watchdog Window Timeout Period Bit 3 */ -#define FUSE1_DEFAULT (0xFF) - -/* Fuse Byte 2 */ -#define FUSE_BODPD0 (unsigned char)~_BV(0) /* BOD Operation in Power-Down Mode Bit 0 */ -#define FUSE_BODPD1 (unsigned char)~_BV(1) /* BOD Operation in Power-Down Mode Bit 1 */ -#define FUSE_TOSCSEL (unsigned char)~_BV(5) /* Timer Oscillator pin location */ -#define FUSE_BOOTRST (unsigned char)~_BV(6) /* Boot Loader Section Reset Vector */ -#define FUSE2_DEFAULT (0xFF) - -/* Fuse Byte 3 Reserved */ - -/* Fuse Byte 4 */ -#define FUSE_JTAGEN (unsigned char)~_BV(0) /* JTAG Interface Enable */ -#define FUSE_WDLOCK (unsigned char)~_BV(1) /* Watchdog Timer Lock */ -#define FUSE_SUT0 (unsigned char)~_BV(2) /* Start-up Time Bit 0 */ -#define FUSE_SUT1 (unsigned char)~_BV(3) /* Start-up Time Bit 1 */ -#define FUSE_RSTDISBL (unsigned char)~_BV(4) /* External Reset Disable */ -#define FUSE4_DEFAULT (0xFF) - -/* Fuse Byte 5 */ -#define FUSE_BODLVL0 (unsigned char)~_BV(0) /* Brownout Detection Voltage Level Bit 0 */ -#define FUSE_BODLVL1 (unsigned char)~_BV(1) /* Brownout Detection Voltage Level Bit 1 */ -#define FUSE_BODLVL2 (unsigned char)~_BV(2) /* Brownout Detection Voltage Level Bit 2 */ -#define FUSE_EESAVE (unsigned char)~_BV(3) /* Preserve EEPROM Through Chip Erase */ -#define FUSE_BODACT0 (unsigned char)~_BV(4) /* BOD Operation in Active Mode Bit 0 */ -#define FUSE_BODACT1 (unsigned char)~_BV(5) /* BOD Operation in Active Mode Bit 1 */ -#define FUSE5_DEFAULT (0xFF) - -/* ========== Lock Bits ========== */ -#define __LOCK_BITS_EXIST -#define __BOOT_LOCK_APPLICATION_TABLE_BITS_EXIST -#define __BOOT_LOCK_APPLICATION_BITS_EXIST -#define __BOOT_LOCK_BOOT_BITS_EXIST - -/* ========== Signature ========== */ -#define SIGNATURE_0 0x1E -#define SIGNATURE_1 0x96 -#define SIGNATURE_2 0x4E - -/* ========== Power Reduction Condition Definitions ========== */ - -/* PR.PRGEN */ -#define __AVR_HAVE_PRGEN (PR_USB_bm|PR_AES_bm|PR_EBI_bm|PR_RTC_bm|PR_EVSYS_bm|PR_DMA_bm) -#define __AVR_HAVE_PRGEN_USB -#define __AVR_HAVE_PRGEN_AES -#define __AVR_HAVE_PRGEN_EBI -#define __AVR_HAVE_PRGEN_RTC -#define __AVR_HAVE_PRGEN_EVSYS -#define __AVR_HAVE_PRGEN_DMA - -/* PR.PRPA */ -#define __AVR_HAVE_PRPA (PR_DAC_bm|PR_ADC_bm|PR_AC_bm) -#define __AVR_HAVE_PRPA_DAC -#define __AVR_HAVE_PRPA_ADC -#define __AVR_HAVE_PRPA_AC - -/* PR.PRPB */ -#define __AVR_HAVE_PRPB (PR_DAC_bm|PR_ADC_bm|PR_AC_bm) -#define __AVR_HAVE_PRPB_DAC -#define __AVR_HAVE_PRPB_ADC -#define __AVR_HAVE_PRPB_AC - -/* PR.PRPC */ -#define __AVR_HAVE_PRPC (PR_TWI_bm|PR_USART1_bm|PR_USART0_bm|PR_SPI_bm|PR_HIRES_bm|PR_TC1_bm|PR_TC0_bm) -#define __AVR_HAVE_PRPC_TWI -#define __AVR_HAVE_PRPC_USART1 -#define __AVR_HAVE_PRPC_USART0 -#define __AVR_HAVE_PRPC_SPI -#define __AVR_HAVE_PRPC_HIRES -#define __AVR_HAVE_PRPC_TC1 -#define __AVR_HAVE_PRPC_TC0 - -/* PR.PRPD */ -#define __AVR_HAVE_PRPD (PR_TWI_bm|PR_USART1_bm|PR_USART0_bm|PR_SPI_bm|PR_HIRES_bm|PR_TC1_bm|PR_TC0_bm) -#define __AVR_HAVE_PRPD_TWI -#define __AVR_HAVE_PRPD_USART1 -#define __AVR_HAVE_PRPD_USART0 -#define __AVR_HAVE_PRPD_SPI -#define __AVR_HAVE_PRPD_HIRES -#define __AVR_HAVE_PRPD_TC1 -#define __AVR_HAVE_PRPD_TC0 - -/* PR.PRPE */ -#define __AVR_HAVE_PRPE (PR_TWI_bm|PR_USART1_bm|PR_USART0_bm|PR_SPI_bm|PR_HIRES_bm|PR_TC1_bm|PR_TC0_bm) -#define __AVR_HAVE_PRPE_TWI -#define __AVR_HAVE_PRPE_USART1 -#define __AVR_HAVE_PRPE_USART0 -#define __AVR_HAVE_PRPE_SPI -#define __AVR_HAVE_PRPE_HIRES -#define __AVR_HAVE_PRPE_TC1 -#define __AVR_HAVE_PRPE_TC0 - -/* PR.PRPF */ -#define __AVR_HAVE_PRPF (PR_TWI_bm|PR_USART1_bm|PR_USART0_bm|PR_SPI_bm|PR_HIRES_bm|PR_TC1_bm|PR_TC0_bm) -#define __AVR_HAVE_PRPF_TWI -#define __AVR_HAVE_PRPF_USART1 -#define __AVR_HAVE_PRPF_USART0 -#define __AVR_HAVE_PRPF_SPI -#define __AVR_HAVE_PRPF_HIRES -#define __AVR_HAVE_PRPF_TC1 -#define __AVR_HAVE_PRPF_TC0 - - -#endif /* #ifdef _AVR_ATXMEGA64A1U_H_INCLUDED */ - diff --git a/arduino/hardware/tools/avr/avr/include/avr/iox64a3.h b/arduino/hardware/tools/avr/avr/include/avr/iox64a3.h deleted file mode 100644 index f656d85..0000000 --- a/arduino/hardware/tools/avr/avr/include/avr/iox64a3.h +++ /dev/null @@ -1,6987 +0,0 @@ -/* Copyright (c) 2009-2010 Atmel Corporation - All rights reserved. - - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - * Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - * Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in - the documentation and/or other materials provided with the - distribution. - - * Neither the name of the copyright holders nor the names of - contributors may be used to endorse or promote products derived - from this software without specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. */ - -/* $Id: iox64a3.h 2200 2010-12-14 04:24:24Z arcanum $ */ - -/* avr/iox64a3.h - definitions for ATxmega64A3 */ - -/* This file should only be included from , never directly. */ - -#ifndef _AVR_IO_H_ -# error "Include instead of this file." -#endif - -#ifndef _AVR_IOXXX_H_ -# define _AVR_IOXXX_H_ "iox64a3.h" -#else -# error "Attempt to include more than one file." -#endif - - -#ifndef _AVR_ATxmega64A3_H_ -#define _AVR_ATxmega64A3_H_ 1 - - -/* Ungrouped common registers */ -#define GPIOR0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ -#define GPIOR1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ -#define GPIOR2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ -#define GPIOR3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ -#define GPIOR4 _SFR_MEM8(0x0004) /* General Purpose IO Register 4 */ -#define GPIOR5 _SFR_MEM8(0x0005) /* General Purpose IO Register 5 */ -#define GPIOR6 _SFR_MEM8(0x0006) /* General Purpose IO Register 6 */ -#define GPIOR7 _SFR_MEM8(0x0007) /* General Purpose IO Register 7 */ -#define GPIOR8 _SFR_MEM8(0x0008) /* General Purpose IO Register 8 */ -#define GPIOR9 _SFR_MEM8(0x0009) /* General Purpose IO Register 9 */ -#define GPIORA _SFR_MEM8(0x000A) /* General Purpose IO Register 10 */ -#define GPIORB _SFR_MEM8(0x000B) /* General Purpose IO Register 11 */ -#define GPIORC _SFR_MEM8(0x000C) /* General Purpose IO Register 12 */ -#define GPIORD _SFR_MEM8(0x000D) /* General Purpose IO Register 13 */ -#define GPIORE _SFR_MEM8(0x000E) /* General Purpose IO Register 14 */ -#define GPIORF _SFR_MEM8(0x000F) /* General Purpose IO Register 15 */ - -/* Deprecated */ -#define GPIO0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ -#define GPIO1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ -#define GPIO2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ -#define GPIO3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ -#define GPIO4 _SFR_MEM8(0x0004) /* General Purpose IO Register 4 */ -#define GPIO5 _SFR_MEM8(0x0005) /* General Purpose IO Register 5 */ -#define GPIO6 _SFR_MEM8(0x0006) /* General Purpose IO Register 6 */ -#define GPIO7 _SFR_MEM8(0x0007) /* General Purpose IO Register 7 */ -#define GPIO8 _SFR_MEM8(0x0008) /* General Purpose IO Register 8 */ -#define GPIO9 _SFR_MEM8(0x0009) /* General Purpose IO Register 9 */ -#define GPIOA _SFR_MEM8(0x000A) /* General Purpose IO Register 10 */ -#define GPIOB _SFR_MEM8(0x000B) /* General Purpose IO Register 11 */ -#define GPIOC _SFR_MEM8(0x000C) /* General Purpose IO Register 12 */ -#define GPIOD _SFR_MEM8(0x000D) /* General Purpose IO Register 13 */ -#define GPIOE _SFR_MEM8(0x000E) /* General Purpose IO Register 14 */ -#define GPIOF _SFR_MEM8(0x000F) /* General Purpose IO Register 15 */ - -#define CCP _SFR_MEM8(0x0034) /* Configuration Change Protection */ -#define RAMPD _SFR_MEM8(0x0038) /* Ramp D */ -#define RAMPX _SFR_MEM8(0x0039) /* Ramp X */ -#define RAMPY _SFR_MEM8(0x003A) /* Ramp Y */ -#define RAMPZ _SFR_MEM8(0x003B) /* Ramp Z */ -#define EIND _SFR_MEM8(0x003C) /* Extended Indirect Jump */ -#define SPL _SFR_MEM8(0x003D) /* Stack Pointer Low */ -#define SPH _SFR_MEM8(0x003E) /* Stack Pointer High */ -#define SREG _SFR_MEM8(0x003F) /* Status Register */ - - -/* C Language Only */ -#if !defined (__ASSEMBLER__) - -#include - -typedef volatile uint8_t register8_t; -typedef volatile uint16_t register16_t; -typedef volatile uint32_t register32_t; - - -#ifdef _WORDREGISTER -#undef _WORDREGISTER -#endif -#define _WORDREGISTER(regname) \ - __extension__ union \ - { \ - register16_t regname; \ - struct \ - { \ - register8_t regname ## L; \ - register8_t regname ## H; \ - }; \ - } - -#ifdef _DWORDREGISTER -#undef _DWORDREGISTER -#endif -#define _DWORDREGISTER(regname) \ - __extension__ union \ - { \ - register32_t regname; \ - struct \ - { \ - register8_t regname ## 0; \ - register8_t regname ## 1; \ - register8_t regname ## 2; \ - register8_t regname ## 3; \ - }; \ - } - - -/* -========================================================================== -IO Module Structures -========================================================================== -*/ - - -/* --------------------------------------------------------------------------- -XOCD - On-Chip Debug System --------------------------------------------------------------------------- -*/ - -/* On-Chip Debug System */ -typedef struct OCD_struct -{ - register8_t OCDR0; /* OCD Register 0 */ - register8_t OCDR1; /* OCD Register 1 */ -} OCD_t; - - -/* CCP signatures */ -typedef enum CCP_enum -{ - CCP_SPM_gc = (0x9D<<0), /* SPM Instruction Protection */ - CCP_IOREG_gc = (0xD8<<0), /* IO Register Protection */ -} CCP_t; - - -/* --------------------------------------------------------------------------- -CLK - Clock System --------------------------------------------------------------------------- -*/ - -/* Clock System */ -typedef struct CLK_struct -{ - register8_t CTRL; /* Control Register */ - register8_t PSCTRL; /* Prescaler Control Register */ - register8_t LOCK; /* Lock register */ - register8_t RTCCTRL; /* RTC Control Register */ -} CLK_t; - -/* --------------------------------------------------------------------------- -CLK - Clock System --------------------------------------------------------------------------- -*/ - -/* Power Reduction */ -typedef struct PR_struct -{ - register8_t PRGEN; /* General Power Reduction */ - register8_t PRPA; /* Power Reduction Port A */ - register8_t PRPB; /* Power Reduction Port B */ - register8_t PRPC; /* Power Reduction Port C */ - register8_t PRPD; /* Power Reduction Port D */ - register8_t PRPE; /* Power Reduction Port E */ - register8_t PRPF; /* Power Reduction Port F */ -} PR_t; - -/* System Clock Selection */ -typedef enum CLK_SCLKSEL_enum -{ - CLK_SCLKSEL_RC2M_gc = (0x00<<0), /* Internal 2MHz RC Oscillator */ - CLK_SCLKSEL_RC32M_gc = (0x01<<0), /* Internal 32MHz RC Oscillator */ - CLK_SCLKSEL_RC32K_gc = (0x02<<0), /* Internal 32kHz RC Oscillator */ - CLK_SCLKSEL_XOSC_gc = (0x03<<0), /* External Crystal Oscillator or Clock */ - CLK_SCLKSEL_PLL_gc = (0x04<<0), /* Phase Locked Loop */ -} CLK_SCLKSEL_t; - -/* Prescaler A Division Factor */ -typedef enum CLK_PSADIV_enum -{ - CLK_PSADIV_1_gc = (0x00<<2), /* Divide by 1 */ - CLK_PSADIV_2_gc = (0x01<<2), /* Divide by 2 */ - CLK_PSADIV_4_gc = (0x03<<2), /* Divide by 4 */ - CLK_PSADIV_8_gc = (0x05<<2), /* Divide by 8 */ - CLK_PSADIV_16_gc = (0x07<<2), /* Divide by 16 */ - CLK_PSADIV_32_gc = (0x09<<2), /* Divide by 32 */ - CLK_PSADIV_64_gc = (0x0B<<2), /* Divide by 64 */ - CLK_PSADIV_128_gc = (0x0D<<2), /* Divide by 128 */ - CLK_PSADIV_256_gc = (0x0F<<2), /* Divide by 256 */ - CLK_PSADIV_512_gc = (0x11<<2), /* Divide by 512 */ -} CLK_PSADIV_t; - -/* Prescaler B and C Division Factor */ -typedef enum CLK_PSBCDIV_enum -{ - CLK_PSBCDIV_1_1_gc = (0x00<<0), /* Divide B by 1 and C by 1 */ - CLK_PSBCDIV_1_2_gc = (0x01<<0), /* Divide B by 1 and C by 2 */ - CLK_PSBCDIV_4_1_gc = (0x02<<0), /* Divide B by 4 and C by 1 */ - CLK_PSBCDIV_2_2_gc = (0x03<<0), /* Divide B by 2 and C by 2 */ -} CLK_PSBCDIV_t; - -/* RTC Clock Source */ -typedef enum CLK_RTCSRC_enum -{ - CLK_RTCSRC_ULP_gc = (0x00<<1), /* 1kHz from internal 32kHz ULP */ - CLK_RTCSRC_TOSC_gc = (0x01<<1), /* 1kHz from 32kHz crystal oscillator on TOSC */ - CLK_RTCSRC_RCOSC_gc = (0x02<<1), /* 1kHz from internal 32kHz RC oscillator */ - CLK_RTCSRC_TOSC32_gc = (0x05<<1), /* 32kHz from 32kHz crystal oscillator on TOSC */ -} CLK_RTCSRC_t; - - -/* --------------------------------------------------------------------------- -SLEEP - Sleep Controller --------------------------------------------------------------------------- -*/ - -/* Sleep Controller */ -typedef struct SLEEP_struct -{ - register8_t CTRL; /* Control Register */ -} SLEEP_t; - -/* Sleep Mode */ -typedef enum SLEEP_SMODE_enum -{ - SLEEP_SMODE_IDLE_gc = (0x00<<1), /* Idle mode */ - SLEEP_SMODE_PDOWN_gc = (0x02<<1), /* Power-down Mode */ - SLEEP_SMODE_PSAVE_gc = (0x03<<1), /* Power-save Mode */ - SLEEP_SMODE_STDBY_gc = (0x06<<1), /* Standby Mode */ - SLEEP_SMODE_ESTDBY_gc = (0x07<<1), /* Extended Standby Mode */ -} SLEEP_SMODE_t; - - -#define SLEEP_MODE_IDLE (0x00<<1) -#define SLEEP_MODE_PWR_DOWN (0x02<<1) -#define SLEEP_MODE_PWR_SAVE (0x03<<1) -#define SLEEP_MODE_STANDBY (0x06<<1) -#define SLEEP_MODE_EXT_STANDBY (0x07<<1) - - -/* --------------------------------------------------------------------------- -OSC - Oscillator --------------------------------------------------------------------------- -*/ - -/* Oscillator */ -typedef struct OSC_struct -{ - register8_t CTRL; /* Control Register */ - register8_t STATUS; /* Status Register */ - register8_t XOSCCTRL; /* External Oscillator Control Register */ - register8_t XOSCFAIL; /* External Oscillator Failure Detection Register */ - register8_t RC32KCAL; /* 32kHz Internal Oscillator Calibration Register */ - register8_t PLLCTRL; /* PLL Control REgister */ - register8_t DFLLCTRL; /* DFLL Control Register */ -} OSC_t; - -/* Oscillator Frequency Range */ -typedef enum OSC_FRQRANGE_enum -{ - OSC_FRQRANGE_04TO2_gc = (0x00<<6), /* 0.4 - 2 MHz */ - OSC_FRQRANGE_2TO9_gc = (0x01<<6), /* 2 - 9 MHz */ - OSC_FRQRANGE_9TO12_gc = (0x02<<6), /* 9 - 12 MHz */ - OSC_FRQRANGE_12TO16_gc = (0x03<<6), /* 12 - 16 MHz */ -} OSC_FRQRANGE_t; - -/* External Oscillator Selection and Startup Time */ -typedef enum OSC_XOSCSEL_enum -{ - OSC_XOSCSEL_EXTCLK_gc = (0x00<<0), /* External Clock - 6 CLK */ - OSC_XOSCSEL_32KHz_gc = (0x02<<0), /* 32kHz TOSC - 32K CLK */ - OSC_XOSCSEL_XTAL_256CLK_gc = (0x03<<0), /* 0.4-16MHz XTAL - 256 CLK */ - OSC_XOSCSEL_XTAL_1KCLK_gc = (0x07<<0), /* 0.4-16MHz XTAL - 1K CLK */ - OSC_XOSCSEL_XTAL_16KCLK_gc = (0x0B<<0), /* 0.4-16MHz XTAL - 16K CLK */ -} OSC_XOSCSEL_t; - -/* PLL Clock Source */ -typedef enum OSC_PLLSRC_enum -{ - OSC_PLLSRC_RC2M_gc = (0x00<<6), /* Internal 2MHz RC Oscillator */ - OSC_PLLSRC_RC32M_gc = (0x02<<6), /* Internal 32MHz RC Oscillator */ - OSC_PLLSRC_XOSC_gc = (0x03<<6), /* External Oscillator */ -} OSC_PLLSRC_t; - - -/* --------------------------------------------------------------------------- -DFLL - DFLL --------------------------------------------------------------------------- -*/ - -/* DFLL */ -typedef struct DFLL_struct -{ - register8_t CTRL; /* Control Register */ - register8_t reserved_0x01; - register8_t CALA; /* Calibration Register A */ - register8_t CALB; /* Calibration Register B */ - register8_t COMP0; /* Oscillator Compare Register 0 */ - register8_t COMP1; /* Oscillator Compare Register 1 */ - register8_t COMP2; /* Oscillator Compare Register 2 */ - register8_t reserved_0x07; -} DFLL_t; - - -/* --------------------------------------------------------------------------- -RST - Reset --------------------------------------------------------------------------- -*/ - -/* Reset */ -typedef struct RST_struct -{ - register8_t STATUS; /* Status Register */ - register8_t CTRL; /* Control Register */ -} RST_t; - - -/* --------------------------------------------------------------------------- -WDT - Watch-Dog Timer --------------------------------------------------------------------------- -*/ - -/* Watch-Dog Timer */ -typedef struct WDT_struct -{ - register8_t CTRL; /* Control */ - register8_t WINCTRL; /* Windowed Mode Control */ - register8_t STATUS; /* Status */ -} WDT_t; - -/* Period setting */ -typedef enum WDT_PER_enum -{ - WDT_PER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ - WDT_PER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ - WDT_PER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ - WDT_PER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ - WDT_PER_128CLK_gc = (0x04<<2), /* 128 cycles (0.125s @ 3.3V) */ - WDT_PER_256CLK_gc = (0x05<<2), /* 256 cycles (0.25s @ 3.3V) */ - WDT_PER_512CLK_gc = (0x06<<2), /* 512 cycles (0.5s @ 3.3V) */ - WDT_PER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ - WDT_PER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ - WDT_PER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ - WDT_PER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ -} WDT_PER_t; - -/* Closed window period */ -typedef enum WDT_WPER_enum -{ - WDT_WPER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ - WDT_WPER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ - WDT_WPER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ - WDT_WPER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ - WDT_WPER_128CLK_gc = (0x04<<2), /* 128 cycles (0.125s @ 3.3V) */ - WDT_WPER_256CLK_gc = (0x05<<2), /* 256 cycles (0.25s @ 3.3V) */ - WDT_WPER_512CLK_gc = (0x06<<2), /* 512 cycles (0.5s @ 3.3V) */ - WDT_WPER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ - WDT_WPER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ - WDT_WPER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ - WDT_WPER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ -} WDT_WPER_t; - - -/* --------------------------------------------------------------------------- -MCU - MCU Control --------------------------------------------------------------------------- -*/ - -/* MCU Control */ -typedef struct MCU_struct -{ - register8_t DEVID0; /* Device ID byte 0 */ - register8_t DEVID1; /* Device ID byte 1 */ - register8_t DEVID2; /* Device ID byte 2 */ - register8_t REVID; /* Revision ID */ - register8_t JTAGUID; /* JTAG User ID */ - register8_t reserved_0x05; - register8_t MCUCR; /* MCU Control */ - register8_t reserved_0x07; - register8_t EVSYSLOCK; /* Event System Lock */ - register8_t AWEXLOCK; /* AWEX Lock */ - register8_t reserved_0x0A; - register8_t reserved_0x0B; -} MCU_t; - - -/* --------------------------------------------------------------------------- -PMIC - Programmable Multi-level Interrupt Controller --------------------------------------------------------------------------- -*/ - -/* Programmable Multi-level Interrupt Controller */ -typedef struct PMIC_struct -{ - register8_t STATUS; /* Status Register */ - register8_t INTPRI; /* Interrupt Priority */ - register8_t CTRL; /* Control Register */ -} PMIC_t; - - -/* --------------------------------------------------------------------------- -DMA - DMA Controller --------------------------------------------------------------------------- -*/ - -/* DMA Channel */ -typedef struct DMA_CH_struct -{ - register8_t CTRLA; /* Channel Control */ - register8_t CTRLB; /* Channel Control */ - register8_t ADDRCTRL; /* Address Control */ - register8_t TRIGSRC; /* Channel Trigger Source */ - _WORDREGISTER(TRFCNT); /* Channel Block Transfer Count */ - register8_t REPCNT; /* Channel Repeat Count */ - register8_t reserved_0x07; - register8_t SRCADDR0; /* Channel Source Address 0 */ - register8_t SRCADDR1; /* Channel Source Address 1 */ - register8_t SRCADDR2; /* Channel Source Address 2 */ - register8_t reserved_0x0B; - register8_t DESTADDR0; /* Channel Destination Address 0 */ - register8_t DESTADDR1; /* Channel Destination Address 1 */ - register8_t DESTADDR2; /* Channel Destination Address 2 */ - register8_t reserved_0x0F; -} DMA_CH_t; - -/* --------------------------------------------------------------------------- -DMA - DMA Controller --------------------------------------------------------------------------- -*/ - -/* DMA Controller */ -typedef struct DMA_struct -{ - register8_t CTRL; /* Control */ - register8_t reserved_0x01; - register8_t reserved_0x02; - register8_t INTFLAGS; /* Transfer Interrupt Status */ - register8_t STATUS; /* Status */ - register8_t reserved_0x05; - _WORDREGISTER(TEMP); /* Temporary Register For 16/24-bit Access */ - register8_t reserved_0x08; - register8_t reserved_0x09; - register8_t reserved_0x0A; - register8_t reserved_0x0B; - register8_t reserved_0x0C; - register8_t reserved_0x0D; - register8_t reserved_0x0E; - register8_t reserved_0x0F; - DMA_CH_t CH0; /* DMA Channel 0 */ - DMA_CH_t CH1; /* DMA Channel 1 */ - DMA_CH_t CH2; /* DMA Channel 2 */ - DMA_CH_t CH3; /* DMA Channel 3 */ -} DMA_t; - -/* Burst mode */ -typedef enum DMA_CH_BURSTLEN_enum -{ - DMA_CH_BURSTLEN_1BYTE_gc = (0x00<<0), /* 1-byte burst mode */ - DMA_CH_BURSTLEN_2BYTE_gc = (0x01<<0), /* 2-byte burst mode */ - DMA_CH_BURSTLEN_4BYTE_gc = (0x02<<0), /* 4-byte burst mode */ - DMA_CH_BURSTLEN_8BYTE_gc = (0x03<<0), /* 8-byte burst mode */ -} DMA_CH_BURSTLEN_t; - -/* Source address reload mode */ -typedef enum DMA_CH_SRCRELOAD_enum -{ - DMA_CH_SRCRELOAD_NONE_gc = (0x00<<6), /* No reload */ - DMA_CH_SRCRELOAD_BLOCK_gc = (0x01<<6), /* Reload at end of block */ - DMA_CH_SRCRELOAD_BURST_gc = (0x02<<6), /* Reload at end of burst */ - DMA_CH_SRCRELOAD_TRANSACTION_gc = (0x03<<6), /* Reload at end of transaction */ -} DMA_CH_SRCRELOAD_t; - -/* Source addressing mode */ -typedef enum DMA_CH_SRCDIR_enum -{ - DMA_CH_SRCDIR_FIXED_gc = (0x00<<4), /* Fixed */ - DMA_CH_SRCDIR_INC_gc = (0x01<<4), /* Increment */ - DMA_CH_SRCDIR_DEC_gc = (0x02<<4), /* Decrement */ -} DMA_CH_SRCDIR_t; - -/* Destination adress reload mode */ -typedef enum DMA_CH_DESTRELOAD_enum -{ - DMA_CH_DESTRELOAD_NONE_gc = (0x00<<2), /* No reload */ - DMA_CH_DESTRELOAD_BLOCK_gc = (0x01<<2), /* Reload at end of block */ - DMA_CH_DESTRELOAD_BURST_gc = (0x02<<2), /* Reload at end of burst */ - DMA_CH_DESTRELOAD_TRANSACTION_gc = (0x03<<2), /* Reload at end of transaction */ -} DMA_CH_DESTRELOAD_t; - -/* Destination adressing mode */ -typedef enum DMA_CH_DESTDIR_enum -{ - DMA_CH_DESTDIR_FIXED_gc = (0x00<<0), /* Fixed */ - DMA_CH_DESTDIR_INC_gc = (0x01<<0), /* Increment */ - DMA_CH_DESTDIR_DEC_gc = (0x02<<0), /* Decrement */ -} DMA_CH_DESTDIR_t; - -/* Transfer trigger source */ -typedef enum DMA_CH_TRIGSRC_enum -{ - DMA_CH_TRIGSRC_OFF_gc = (0x00<<0), /* Off software triggers only */ - DMA_CH_TRIGSRC_EVSYS_CH0_gc = (0x01<<0), /* Event System Channel 0 */ - DMA_CH_TRIGSRC_EVSYS_CH1_gc = (0x02<<0), /* Event System Channel 1 */ - DMA_CH_TRIGSRC_EVSYS_CH2_gc = (0x03<<0), /* Event System Channel 2 */ - DMA_CH_TRIGSRC_ADCA_CH0_gc = (0x10<<0), /* ADCA Channel 0 */ - DMA_CH_TRIGSRC_ADCA_CH1_gc = (0x11<<0), /* ADCA Channel 1 */ - DMA_CH_TRIGSRC_ADCA_CH2_gc = (0x12<<0), /* ADCA Channel 2 */ - DMA_CH_TRIGSRC_ADCA_CH3_gc = (0x13<<0), /* ADCA Channel 3 */ - DMA_CH_TRIGSRC_ADCA_CH4_gc = (0x14<<0), /* ADCA Channel 0,1,2,3 combined */ - DMA_CH_TRIGSRC_DACA_CH0_gc = (0x15<<0), /* DACA Channel 0 */ - DMA_CH_TRIGSRC_DACA_CH1_gc = (0x16<<0), /* DACA Channel 1 */ - DMA_CH_TRIGSRC_ADCB_CH0_gc = (0x20<<0), /* ADCB Channel 0 */ - DMA_CH_TRIGSRC_ADCB_CH1_gc = (0x21<<0), /* ADCB Channel 1 */ - DMA_CH_TRIGSRC_ADCB_CH2_gc = (0x22<<0), /* ADCB Channel 2 */ - DMA_CH_TRIGSRC_ADCB_CH3_gc = (0x23<<0), /* ADCB Channel 3 */ - DMA_CH_TRIGSRC_ADCB_CH4_gc = (0x24<<0), /* ADCB Channel 0,1,2,3 combined */ - DMA_CH_TRIGSRC_DACB_CH0_gc = (0x25<<0), /* DACB Channel 0 */ - DMA_CH_TRIGSRC_DACB_CH1_gc = (0x26<<0), /* DACB Channel 1 */ - DMA_CH_TRIGSRC_TCC0_OVF_gc = (0x40<<0), /* Timer/Counter C0 Overflow */ - DMA_CH_TRIGSRC_TCC0_ERR_gc = (0x41<<0), /* Timer/Counter C0 Error */ - DMA_CH_TRIGSRC_TCC0_CCA_gc = (0x42<<0), /* Timer/Counter C0 Compare or Capture A */ - DMA_CH_TRIGSRC_TCC0_CCB_gc = (0x43<<0), /* Timer/Counter C0 Compare or Capture B */ - DMA_CH_TRIGSRC_TCC0_CCC_gc = (0x44<<0), /* Timer/Counter C0 Compare or Capture C */ - DMA_CH_TRIGSRC_TCC0_CCD_gc = (0x45<<0), /* Timer/Counter C0 Compare or Capture D */ - DMA_CH_TRIGSRC_TCC1_OVF_gc = (0x46<<0), /* Timer/Counter C1 Overflow */ - DMA_CH_TRIGSRC_TCC1_ERR_gc = (0x47<<0), /* Timer/Counter C1 Error */ - DMA_CH_TRIGSRC_TCC1_CCA_gc = (0x48<<0), /* Timer/Counter C1 Compare or Capture A */ - DMA_CH_TRIGSRC_TCC1_CCB_gc = (0x49<<0), /* Timer/Counter C1 Compare or Capture B */ - DMA_CH_TRIGSRC_SPIC_gc = (0x4A<<0), /* SPI C Transfer Complete */ - DMA_CH_TRIGSRC_USARTC0_RXC_gc = (0x4B<<0), /* USART C0 Receive Complete */ - DMA_CH_TRIGSRC_USARTC0_DRE_gc = (0x4C<<0), /* USART C0 Data Register Empty */ - DMA_CH_TRIGSRC_USARTC1_RXC_gc = (0x4E<<0), /* USART C1 Receive Complete */ - DMA_CH_TRIGSRC_USARTC1_DRE_gc = (0x4F<<0), /* USART C1 Data Register Empty */ - DMA_CH_TRIGSRC_TCD0_OVF_gc = (0x60<<0), /* Timer/Counter D0 Overflow */ - DMA_CH_TRIGSRC_TCD0_ERR_gc = (0x61<<0), /* Timer/Counter D0 Error */ - DMA_CH_TRIGSRC_TCD0_CCA_gc = (0x62<<0), /* Timer/Counter D0 Compare or Capture A */ - DMA_CH_TRIGSRC_TCD0_CCB_gc = (0x63<<0), /* Timer/Counter D0 Compare or Capture B */ - DMA_CH_TRIGSRC_TCD0_CCC_gc = (0x64<<0), /* Timer/Counter D0 Compare or Capture C */ - DMA_CH_TRIGSRC_TCD0_CCD_gc = (0x65<<0), /* Timer/Counter D0 Compare or Capture D */ - DMA_CH_TRIGSRC_TCD1_OVF_gc = (0x66<<0), /* Timer/Counter D1 Overflow */ - DMA_CH_TRIGSRC_TCD1_ERR_gc = (0x67<<0), /* Timer/Counter D1 Error */ - DMA_CH_TRIGSRC_TCD1_CCA_gc = (0x68<<0), /* Timer/Counter D1 Compare or Capture A */ - DMA_CH_TRIGSRC_TCD1_CCB_gc = (0x69<<0), /* Timer/Counter D1 Compare or Capture B */ - DMA_CH_TRIGSRC_SPID_gc = (0x6A<<0), /* SPI D Transfer Complete */ - DMA_CH_TRIGSRC_USARTD0_RXC_gc = (0x6B<<0), /* USART D0 Receive Complete */ - DMA_CH_TRIGSRC_USARTD0_DRE_gc = (0x6C<<0), /* USART D0 Data Register Empty */ - DMA_CH_TRIGSRC_USARTD1_RXC_gc = (0x6E<<0), /* USART D1 Receive Complete */ - DMA_CH_TRIGSRC_USARTD1_DRE_gc = (0x6F<<0), /* USART D1 Data Register Empty */ - DMA_CH_TRIGSRC_TCE0_OVF_gc = (0x80<<0), /* Timer/Counter E0 Overflow */ - DMA_CH_TRIGSRC_TCE0_ERR_gc = (0x81<<0), /* Timer/Counter E0 Error */ - DMA_CH_TRIGSRC_TCE0_CCA_gc = (0x82<<0), /* Timer/Counter E0 Compare or Capture A */ - DMA_CH_TRIGSRC_TCE0_CCB_gc = (0x83<<0), /* Timer/Counter E0 Compare or Capture B */ - DMA_CH_TRIGSRC_TCE0_CCC_gc = (0x84<<0), /* Timer/Counter E0 Compare or Capture C */ - DMA_CH_TRIGSRC_TCE0_CCD_gc = (0x85<<0), /* Timer/Counter E0 Compare or Capture D */ - DMA_CH_TRIGSRC_TCE1_OVF_gc = (0x86<<0), /* Timer/Counter E1 Overflow */ - DMA_CH_TRIGSRC_TCE1_ERR_gc = (0x87<<0), /* Timer/Counter E1 Error */ - DMA_CH_TRIGSRC_TCE1_CCA_gc = (0x88<<0), /* Timer/Counter E1 Compare or Capture A */ - DMA_CH_TRIGSRC_TCE1_CCB_gc = (0x89<<0), /* Timer/Counter E1 Compare or Capture B */ - DMA_CH_TRIGSRC_SPIE_gc = (0x8A<<0), /* SPI E Transfer Complete */ - DMA_CH_TRIGSRC_USARTE0_RXC_gc = (0x8B<<0), /* USART E0 Receive Complete */ - DMA_CH_TRIGSRC_USARTE0_DRE_gc = (0x8C<<0), /* USART E0 Data Register Empty */ - DMA_CH_TRIGSRC_USARTE1_RXC_gc = (0x8E<<0), /* USART E1 Receive Complete */ - DMA_CH_TRIGSRC_USARTE1_DRE_gc = (0x8F<<0), /* USART E1 Data Register Empty */ - DMA_CH_TRIGSRC_TCF0_OVF_gc = (0xA0<<0), /* Timer/Counter F0 Overflow */ - DMA_CH_TRIGSRC_TCF0_ERR_gc = (0xA1<<0), /* Timer/Counter F0 Error */ - DMA_CH_TRIGSRC_TCF0_CCA_gc = (0xA2<<0), /* Timer/Counter F0 Compare or Capture A */ - DMA_CH_TRIGSRC_TCF0_CCB_gc = (0xA3<<0), /* Timer/Counter F0 Compare or Capture B */ - DMA_CH_TRIGSRC_TCF0_CCC_gc = (0xA4<<0), /* Timer/Counter F0 Compare or Capture C */ - DMA_CH_TRIGSRC_TCF0_CCD_gc = (0xA5<<0), /* Timer/Counter F0 Compare or Capture D */ - DMA_CH_TRIGSRC_TCF1_OVF_gc = (0xA6<<0), /* Timer/Counter F1 Overflow */ - DMA_CH_TRIGSRC_TCF1_ERR_gc = (0xA7<<0), /* Timer/Counter F1 Error */ - DMA_CH_TRIGSRC_TCF1_CCA_gc = (0xA8<<0), /* Timer/Counter F1 Compare or Capture A */ - DMA_CH_TRIGSRC_TCF1_CCB_gc = (0xA9<<0), /* Timer/Counter F1 Compare or Capture B */ - DMA_CH_TRIGSRC_SPIF_gc = (0xAA<<0), /* SPI F Transfer Complete */ - DMA_CH_TRIGSRC_USARTF0_RXC_gc = (0xAB<<0), /* USART F0 Receive Complete */ - DMA_CH_TRIGSRC_USARTF0_DRE_gc = (0xAC<<0), /* USART F0 Data Register Empty */ - DMA_CH_TRIGSRC_USARTF1_RXC_gc = (0xAE<<0), /* USART F1 Receive Complete */ - DMA_CH_TRIGSRC_USARTF1_DRE_gc = (0xAF<<0), /* USART F1 Data Register Empty */ -} DMA_CH_TRIGSRC_t; - -/* Double buffering mode */ -typedef enum DMA_DBUFMODE_enum -{ - DMA_DBUFMODE_DISABLED_gc = (0x00<<2), /* Double buffering disabled */ - DMA_DBUFMODE_CH01_gc = (0x01<<2), /* Double buffering enabled on channel 0/1 */ - DMA_DBUFMODE_CH23_gc = (0x02<<2), /* Double buffering enabled on channel 2/3 */ - DMA_DBUFMODE_CH01CH23_gc = (0x03<<2), /* Double buffering enabled on ch. 0/1 and ch. 2/3 */ -} DMA_DBUFMODE_t; - -/* Priority mode */ -typedef enum DMA_PRIMODE_enum -{ - DMA_PRIMODE_RR0123_gc = (0x00<<0), /* Round Robin */ - DMA_PRIMODE_CH0RR123_gc = (0x01<<0), /* Channel 0 > Round Robin on channel 1/2/3 */ - DMA_PRIMODE_CH01RR23_gc = (0x02<<0), /* Channel 0 > channel 1 > Round Robin on channel 2/3 */ - DMA_PRIMODE_CH0123_gc = (0x03<<0), /* Channel 0 > channel 1 > channel 2 > channel 3 */ -} DMA_PRIMODE_t; - -/* Interrupt level */ -typedef enum DMA_CH_ERRINTLVL_enum -{ - DMA_CH_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ - DMA_CH_ERRINTLVL_LO_gc = (0x01<<2), /* Low level */ - DMA_CH_ERRINTLVL_MED_gc = (0x02<<2), /* Medium level */ - DMA_CH_ERRINTLVL_HI_gc = (0x03<<2), /* High level */ -} DMA_CH_ERRINTLVL_t; - -/* Interrupt level */ -typedef enum DMA_CH_TRNINTLVL_enum -{ - DMA_CH_TRNINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ - DMA_CH_TRNINTLVL_LO_gc = (0x01<<0), /* Low level */ - DMA_CH_TRNINTLVL_MED_gc = (0x02<<0), /* Medium level */ - DMA_CH_TRNINTLVL_HI_gc = (0x03<<0), /* High level */ -} DMA_CH_TRNINTLVL_t; - - -/* --------------------------------------------------------------------------- -EVSYS - Event System --------------------------------------------------------------------------- -*/ - -/* Event System */ -typedef struct EVSYS_struct -{ - register8_t CH0MUX; /* Event Channel 0 Multiplexer */ - register8_t CH1MUX; /* Event Channel 1 Multiplexer */ - register8_t CH2MUX; /* Event Channel 2 Multiplexer */ - register8_t CH3MUX; /* Event Channel 3 Multiplexer */ - register8_t CH4MUX; /* Event Channel 4 Multiplexer */ - register8_t CH5MUX; /* Event Channel 5 Multiplexer */ - register8_t CH6MUX; /* Event Channel 6 Multiplexer */ - register8_t CH7MUX; /* Event Channel 7 Multiplexer */ - register8_t CH0CTRL; /* Channel 0 Control Register */ - register8_t CH1CTRL; /* Channel 1 Control Register */ - register8_t CH2CTRL; /* Channel 2 Control Register */ - register8_t CH3CTRL; /* Channel 3 Control Register */ - register8_t CH4CTRL; /* Channel 4 Control Register */ - register8_t CH5CTRL; /* Channel 5 Control Register */ - register8_t CH6CTRL; /* Channel 6 Control Register */ - register8_t CH7CTRL; /* Channel 7 Control Register */ - register8_t STROBE; /* Event Strobe */ - register8_t DATA; /* Event Data */ -} EVSYS_t; - -/* Quadrature Decoder Index Recognition Mode */ -typedef enum EVSYS_QDIRM_enum -{ - EVSYS_QDIRM_00_gc = (0x00<<5), /* QDPH0 = 0, QDPH90 = 0 */ - EVSYS_QDIRM_01_gc = (0x01<<5), /* QDPH0 = 0, QDPH90 = 1 */ - EVSYS_QDIRM_10_gc = (0x02<<5), /* QDPH0 = 1, QDPH90 = 0 */ - EVSYS_QDIRM_11_gc = (0x03<<5), /* QDPH0 = 1, QDPH90 = 1 */ -} EVSYS_QDIRM_t; - -/* Digital filter coefficient */ -typedef enum EVSYS_DIGFILT_enum -{ - EVSYS_DIGFILT_1SAMPLE_gc = (0x00<<0), /* 1 SAMPLE */ - EVSYS_DIGFILT_2SAMPLES_gc = (0x01<<0), /* 2 SAMPLES */ - EVSYS_DIGFILT_3SAMPLES_gc = (0x02<<0), /* 3 SAMPLES */ - EVSYS_DIGFILT_4SAMPLES_gc = (0x03<<0), /* 4 SAMPLES */ - EVSYS_DIGFILT_5SAMPLES_gc = (0x04<<0), /* 5 SAMPLES */ - EVSYS_DIGFILT_6SAMPLES_gc = (0x05<<0), /* 6 SAMPLES */ - EVSYS_DIGFILT_7SAMPLES_gc = (0x06<<0), /* 7 SAMPLES */ - EVSYS_DIGFILT_8SAMPLES_gc = (0x07<<0), /* 8 SAMPLES */ -} EVSYS_DIGFILT_t; - -/* Event Channel multiplexer input selection */ -typedef enum EVSYS_CHMUX_enum -{ - EVSYS_CHMUX_OFF_gc = (0x00<<0), /* Off */ - EVSYS_CHMUX_RTC_OVF_gc = (0x08<<0), /* RTC Overflow */ - EVSYS_CHMUX_RTC_CMP_gc = (0x09<<0), /* RTC Compare Match */ - EVSYS_CHMUX_ACA_CH0_gc = (0x10<<0), /* Analog Comparator A Channel 0 */ - EVSYS_CHMUX_ACA_CH1_gc = (0x11<<0), /* Analog Comparator A Channel 1 */ - EVSYS_CHMUX_ACA_WIN_gc = (0x12<<0), /* Analog Comparator A Window */ - EVSYS_CHMUX_ACB_CH0_gc = (0x13<<0), /* Analog Comparator B Channel 0 */ - EVSYS_CHMUX_ACB_CH1_gc = (0x14<<0), /* Analog Comparator B Channel 1 */ - EVSYS_CHMUX_ACB_WIN_gc = (0x15<<0), /* Analog Comparator B Window */ - EVSYS_CHMUX_ADCA_CH0_gc = (0x20<<0), /* ADC A Channel 0 */ - EVSYS_CHMUX_ADCA_CH1_gc = (0x21<<0), /* ADC A Channel 1 */ - EVSYS_CHMUX_ADCA_CH2_gc = (0x22<<0), /* ADC A Channel 2 */ - EVSYS_CHMUX_ADCA_CH3_gc = (0x23<<0), /* ADC A Channel 3 */ - EVSYS_CHMUX_ADCB_CH0_gc = (0x24<<0), /* ADC B Channel 0 */ - EVSYS_CHMUX_ADCB_CH1_gc = (0x25<<0), /* ADC B Channel 1 */ - EVSYS_CHMUX_ADCB_CH2_gc = (0x26<<0), /* ADC B Channel 2 */ - EVSYS_CHMUX_ADCB_CH3_gc = (0x27<<0), /* ADC B Channel 3 */ - EVSYS_CHMUX_PORTA_PIN0_gc = (0x50<<0), /* Port A, Pin0 */ - EVSYS_CHMUX_PORTA_PIN1_gc = (0x51<<0), /* Port A, Pin1 */ - EVSYS_CHMUX_PORTA_PIN2_gc = (0x52<<0), /* Port A, Pin2 */ - EVSYS_CHMUX_PORTA_PIN3_gc = (0x53<<0), /* Port A, Pin3 */ - EVSYS_CHMUX_PORTA_PIN4_gc = (0x54<<0), /* Port A, Pin4 */ - EVSYS_CHMUX_PORTA_PIN5_gc = (0x55<<0), /* Port A, Pin5 */ - EVSYS_CHMUX_PORTA_PIN6_gc = (0x56<<0), /* Port A, Pin6 */ - EVSYS_CHMUX_PORTA_PIN7_gc = (0x57<<0), /* Port A, Pin7 */ - EVSYS_CHMUX_PORTB_PIN0_gc = (0x58<<0), /* Port B, Pin0 */ - EVSYS_CHMUX_PORTB_PIN1_gc = (0x59<<0), /* Port B, Pin1 */ - EVSYS_CHMUX_PORTB_PIN2_gc = (0x5A<<0), /* Port B, Pin2 */ - EVSYS_CHMUX_PORTB_PIN3_gc = (0x5B<<0), /* Port B, Pin3 */ - EVSYS_CHMUX_PORTB_PIN4_gc = (0x5C<<0), /* Port B, Pin4 */ - EVSYS_CHMUX_PORTB_PIN5_gc = (0x5D<<0), /* Port B, Pin5 */ - EVSYS_CHMUX_PORTB_PIN6_gc = (0x5E<<0), /* Port B, Pin6 */ - EVSYS_CHMUX_PORTB_PIN7_gc = (0x5F<<0), /* Port B, Pin7 */ - EVSYS_CHMUX_PORTC_PIN0_gc = (0x60<<0), /* Port C, Pin0 */ - EVSYS_CHMUX_PORTC_PIN1_gc = (0x61<<0), /* Port C, Pin1 */ - EVSYS_CHMUX_PORTC_PIN2_gc = (0x62<<0), /* Port C, Pin2 */ - EVSYS_CHMUX_PORTC_PIN3_gc = (0x63<<0), /* Port C, Pin3 */ - EVSYS_CHMUX_PORTC_PIN4_gc = (0x64<<0), /* Port C, Pin4 */ - EVSYS_CHMUX_PORTC_PIN5_gc = (0x65<<0), /* Port C, Pin5 */ - EVSYS_CHMUX_PORTC_PIN6_gc = (0x66<<0), /* Port C, Pin6 */ - EVSYS_CHMUX_PORTC_PIN7_gc = (0x67<<0), /* Port C, Pin7 */ - EVSYS_CHMUX_PORTD_PIN0_gc = (0x68<<0), /* Port D, Pin0 */ - EVSYS_CHMUX_PORTD_PIN1_gc = (0x69<<0), /* Port D, Pin1 */ - EVSYS_CHMUX_PORTD_PIN2_gc = (0x6A<<0), /* Port D, Pin2 */ - EVSYS_CHMUX_PORTD_PIN3_gc = (0x6B<<0), /* Port D, Pin3 */ - EVSYS_CHMUX_PORTD_PIN4_gc = (0x6C<<0), /* Port D, Pin4 */ - EVSYS_CHMUX_PORTD_PIN5_gc = (0x6D<<0), /* Port D, Pin5 */ - EVSYS_CHMUX_PORTD_PIN6_gc = (0x6E<<0), /* Port D, Pin6 */ - EVSYS_CHMUX_PORTD_PIN7_gc = (0x6F<<0), /* Port D, Pin7 */ - EVSYS_CHMUX_PORTE_PIN0_gc = (0x70<<0), /* Port E, Pin0 */ - EVSYS_CHMUX_PORTE_PIN1_gc = (0x71<<0), /* Port E, Pin1 */ - EVSYS_CHMUX_PORTE_PIN2_gc = (0x72<<0), /* Port E, Pin2 */ - EVSYS_CHMUX_PORTE_PIN3_gc = (0x73<<0), /* Port E, Pin3 */ - EVSYS_CHMUX_PORTE_PIN4_gc = (0x74<<0), /* Port E, Pin4 */ - EVSYS_CHMUX_PORTE_PIN5_gc = (0x75<<0), /* Port E, Pin5 */ - EVSYS_CHMUX_PORTE_PIN6_gc = (0x76<<0), /* Port E, Pin6 */ - EVSYS_CHMUX_PORTE_PIN7_gc = (0x77<<0), /* Port E, Pin7 */ - EVSYS_CHMUX_PORTF_PIN0_gc = (0x78<<0), /* Port F, Pin0 */ - EVSYS_CHMUX_PORTF_PIN1_gc = (0x79<<0), /* Port F, Pin1 */ - EVSYS_CHMUX_PORTF_PIN2_gc = (0x7A<<0), /* Port F, Pin2 */ - EVSYS_CHMUX_PORTF_PIN3_gc = (0x7B<<0), /* Port F, Pin3 */ - EVSYS_CHMUX_PORTF_PIN4_gc = (0x7C<<0), /* Port F, Pin4 */ - EVSYS_CHMUX_PORTF_PIN5_gc = (0x7D<<0), /* Port F, Pin5 */ - EVSYS_CHMUX_PORTF_PIN6_gc = (0x7E<<0), /* Port F, Pin6 */ - EVSYS_CHMUX_PORTF_PIN7_gc = (0x7F<<0), /* Port F, Pin7 */ - EVSYS_CHMUX_PRESCALER_1_gc = (0x80<<0), /* Prescaler, divide by 1 */ - EVSYS_CHMUX_PRESCALER_2_gc = (0x81<<0), /* Prescaler, divide by 2 */ - EVSYS_CHMUX_PRESCALER_4_gc = (0x82<<0), /* Prescaler, divide by 4 */ - EVSYS_CHMUX_PRESCALER_8_gc = (0x83<<0), /* Prescaler, divide by 8 */ - EVSYS_CHMUX_PRESCALER_16_gc = (0x84<<0), /* Prescaler, divide by 16 */ - EVSYS_CHMUX_PRESCALER_32_gc = (0x85<<0), /* Prescaler, divide by 32 */ - EVSYS_CHMUX_PRESCALER_64_gc = (0x86<<0), /* Prescaler, divide by 64 */ - EVSYS_CHMUX_PRESCALER_128_gc = (0x87<<0), /* Prescaler, divide by 128 */ - EVSYS_CHMUX_PRESCALER_256_gc = (0x88<<0), /* Prescaler, divide by 256 */ - EVSYS_CHMUX_PRESCALER_512_gc = (0x89<<0), /* Prescaler, divide by 512 */ - EVSYS_CHMUX_PRESCALER_1024_gc = (0x8A<<0), /* Prescaler, divide by 1024 */ - EVSYS_CHMUX_PRESCALER_2048_gc = (0x8B<<0), /* Prescaler, divide by 2048 */ - EVSYS_CHMUX_PRESCALER_4096_gc = (0x8C<<0), /* Prescaler, divide by 4096 */ - EVSYS_CHMUX_PRESCALER_8192_gc = (0x8D<<0), /* Prescaler, divide by 8192 */ - EVSYS_CHMUX_PRESCALER_16384_gc = (0x8E<<0), /* Prescaler, divide by 16384 */ - EVSYS_CHMUX_PRESCALER_32768_gc = (0x8F<<0), /* Prescaler, divide by 32768 */ - EVSYS_CHMUX_TCC0_OVF_gc = (0xC0<<0), /* Timer/Counter C0 Overflow */ - EVSYS_CHMUX_TCC0_ERR_gc = (0xC1<<0), /* Timer/Counter C0 Error */ - EVSYS_CHMUX_TCC0_CCA_gc = (0xC4<<0), /* Timer/Counter C0 Compare or Capture A */ - EVSYS_CHMUX_TCC0_CCB_gc = (0xC5<<0), /* Timer/Counter C0 Compare or Capture B */ - EVSYS_CHMUX_TCC0_CCC_gc = (0xC6<<0), /* Timer/Counter C0 Compare or Capture C */ - EVSYS_CHMUX_TCC0_CCD_gc = (0xC7<<0), /* Timer/Counter C0 Compare or Capture D */ - EVSYS_CHMUX_TCC1_OVF_gc = (0xC8<<0), /* Timer/Counter C1 Overflow */ - EVSYS_CHMUX_TCC1_ERR_gc = (0xC9<<0), /* Timer/Counter C1 Error */ - EVSYS_CHMUX_TCC1_CCA_gc = (0xCC<<0), /* Timer/Counter C1 Compare or Capture A */ - EVSYS_CHMUX_TCC1_CCB_gc = (0xCD<<0), /* Timer/Counter C1 Compare or Capture B */ - EVSYS_CHMUX_TCD0_OVF_gc = (0xD0<<0), /* Timer/Counter D0 Overflow */ - EVSYS_CHMUX_TCD0_ERR_gc = (0xD1<<0), /* Timer/Counter D0 Error */ - EVSYS_CHMUX_TCD0_CCA_gc = (0xD4<<0), /* Timer/Counter D0 Compare or Capture A */ - EVSYS_CHMUX_TCD0_CCB_gc = (0xD5<<0), /* Timer/Counter D0 Compare or Capture B */ - EVSYS_CHMUX_TCD0_CCC_gc = (0xD6<<0), /* Timer/Counter D0 Compare or Capture C */ - EVSYS_CHMUX_TCD0_CCD_gc = (0xD7<<0), /* Timer/Counter D0 Compare or Capture D */ - EVSYS_CHMUX_TCD1_OVF_gc = (0xD8<<0), /* Timer/Counter D1 Overflow */ - EVSYS_CHMUX_TCD1_ERR_gc = (0xD9<<0), /* Timer/Counter D1 Error */ - EVSYS_CHMUX_TCD1_CCA_gc = (0xDC<<0), /* Timer/Counter D1 Compare or Capture A */ - EVSYS_CHMUX_TCD1_CCB_gc = (0xDD<<0), /* Timer/Counter D1 Compare or Capture B */ - EVSYS_CHMUX_TCE0_OVF_gc = (0xE0<<0), /* Timer/Counter E0 Overflow */ - EVSYS_CHMUX_TCE0_ERR_gc = (0xE1<<0), /* Timer/Counter E0 Error */ - EVSYS_CHMUX_TCE0_CCA_gc = (0xE4<<0), /* Timer/Counter E0 Compare or Capture A */ - EVSYS_CHMUX_TCE0_CCB_gc = (0xE5<<0), /* Timer/Counter E0 Compare or Capture B */ - EVSYS_CHMUX_TCE0_CCC_gc = (0xE6<<0), /* Timer/Counter E0 Compare or Capture C */ - EVSYS_CHMUX_TCE0_CCD_gc = (0xE7<<0), /* Timer/Counter E0 Compare or Capture D */ - EVSYS_CHMUX_TCE1_OVF_gc = (0xE8<<0), /* Timer/Counter E1 Overflow */ - EVSYS_CHMUX_TCE1_ERR_gc = (0xE9<<0), /* Timer/Counter E1 Error */ - EVSYS_CHMUX_TCE1_CCA_gc = (0xEC<<0), /* Timer/Counter E1 Compare or Capture A */ - EVSYS_CHMUX_TCE1_CCB_gc = (0xED<<0), /* Timer/Counter E1 Compare or Capture B */ - EVSYS_CHMUX_TCF0_OVF_gc = (0xF0<<0), /* Timer/Counter F0 Overflow */ - EVSYS_CHMUX_TCF0_ERR_gc = (0xF1<<0), /* Timer/Counter F0 Error */ - EVSYS_CHMUX_TCF0_CCA_gc = (0xF4<<0), /* Timer/Counter F0 Compare or Capture A */ - EVSYS_CHMUX_TCF0_CCB_gc = (0xF5<<0), /* Timer/Counter F0 Compare or Capture B */ - EVSYS_CHMUX_TCF0_CCC_gc = (0xF6<<0), /* Timer/Counter F0 Compare or Capture C */ - EVSYS_CHMUX_TCF0_CCD_gc = (0xF7<<0), /* Timer/Counter F0 Compare or Capture D */ - EVSYS_CHMUX_TCF1_OVF_gc = (0xF8<<0), /* Timer/Counter F1 Overflow */ - EVSYS_CHMUX_TCF1_ERR_gc = (0xF9<<0), /* Timer/Counter F1 Error */ - EVSYS_CHMUX_TCF1_CCA_gc = (0xFC<<0), /* Timer/Counter F1 Compare or Capture A */ - EVSYS_CHMUX_TCF1_CCB_gc = (0xFD<<0), /* Timer/Counter F1 Compare or Capture B */ -} EVSYS_CHMUX_t; - - -/* --------------------------------------------------------------------------- -NVM - Non Volatile Memory Controller --------------------------------------------------------------------------- -*/ - -/* Non-volatile Memory Controller */ -typedef struct NVM_struct -{ - register8_t ADDR0; /* Address Register 0 */ - register8_t ADDR1; /* Address Register 1 */ - register8_t ADDR2; /* Address Register 2 */ - register8_t reserved_0x03; - register8_t DATA0; /* Data Register 0 */ - register8_t DATA1; /* Data Register 1 */ - register8_t DATA2; /* Data Register 2 */ - register8_t reserved_0x07; - register8_t reserved_0x08; - register8_t reserved_0x09; - register8_t CMD; /* Command */ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t INTCTRL; /* Interrupt Control */ - register8_t reserved_0x0E; - register8_t STATUS; /* Status */ - register8_t LOCK_BITS; /* Lock Bits */ -} NVM_t; - -/* --------------------------------------------------------------------------- -NVM - Non Volatile Memory Controller --------------------------------------------------------------------------- -*/ - -/* Lock Bits */ -typedef struct NVM_LOCKBITS_struct -{ - register8_t LOCKBITS; /* Lock Bits */ -} NVM_LOCKBITS_t; - -/* --------------------------------------------------------------------------- -NVM - Non Volatile Memory Controller --------------------------------------------------------------------------- -*/ - -/* Fuses */ -typedef struct NVM_FUSES_struct -{ - register8_t FUSEBYTE0; /* JTAG User ID */ - register8_t FUSEBYTE1; /* Watchdog Configuration */ - register8_t FUSEBYTE2; /* Reset Configuration */ - register8_t reserved_0x03; - register8_t FUSEBYTE4; /* Start-up Configuration */ - register8_t FUSEBYTE5; /* EESAVE and BOD Level */ -} NVM_FUSES_t; - -/* --------------------------------------------------------------------------- -NVM - Non Volatile Memory Controller --------------------------------------------------------------------------- -*/ - -/* Production Signatures */ -typedef struct NVM_PROD_SIGNATURES_struct -{ - register8_t RCOSC2M; /* RCOSC 2MHz Calibration Value */ - register8_t reserved_0x01; - register8_t RCOSC32K; /* RCOSC 32kHz Calibration Value */ - register8_t RCOSC32M; /* RCOSC 32MHz Calibration Value */ - register8_t reserved_0x04; - register8_t reserved_0x05; - register8_t reserved_0x06; - register8_t reserved_0x07; - register8_t LOTNUM0; /* Lot Number Byte 0, ASCII */ - register8_t LOTNUM1; /* Lot Number Byte 1, ASCII */ - register8_t LOTNUM2; /* Lot Number Byte 2, ASCII */ - register8_t LOTNUM3; /* Lot Number Byte 3, ASCII */ - register8_t LOTNUM4; /* Lot Number Byte 4, ASCII */ - register8_t LOTNUM5; /* Lot Number Byte 5, ASCII */ - register8_t reserved_0x0E; - register8_t reserved_0x0F; - register8_t WAFNUM; /* Wafer Number */ - register8_t reserved_0x11; - register8_t COORDX0; /* Wafer Coordinate X Byte 0 */ - register8_t COORDX1; /* Wafer Coordinate X Byte 1 */ - register8_t COORDY0; /* Wafer Coordinate Y Byte 0 */ - register8_t COORDY1; /* Wafer Coordinate Y Byte 1 */ - register8_t reserved_0x16; - register8_t reserved_0x17; - register8_t reserved_0x18; - register8_t reserved_0x19; - register8_t reserved_0x1A; - register8_t reserved_0x1B; - register8_t reserved_0x1C; - register8_t reserved_0x1D; - register8_t reserved_0x1E; - register8_t reserved_0x1F; - register8_t ADCACAL0; /* ADCA Calibration Byte 0 */ - register8_t ADCACAL1; /* ADCA Calibration Byte 1 */ - register8_t reserved_0x22; - register8_t reserved_0x23; - register8_t ADCBCAL0; /* ADCB Calibration Byte 0 */ - register8_t ADCBCAL1; /* ADCB Calibration Byte 1 */ - register8_t reserved_0x26; - register8_t reserved_0x27; - register8_t reserved_0x28; - register8_t reserved_0x29; - register8_t reserved_0x2A; - register8_t reserved_0x2B; - register8_t reserved_0x2C; - register8_t reserved_0x2D; - register8_t TEMPSENSE0; /* Temperature Sensor Calibration Byte 0 */ - register8_t TEMPSENSE1; /* Temperature Sensor Calibration Byte 0 */ - register8_t DACAOFFCAL; /* DACA Calibration Byte 0 */ - register8_t DACAGAINCAL; /* DACA Calibration Byte 1 */ - register8_t DACBOFFCAL; /* DACB Calibration Byte 0 */ - register8_t DACBGAINCAL; /* DACB Calibration Byte 1 */ - register8_t reserved_0x34; - register8_t reserved_0x35; - register8_t reserved_0x36; - register8_t reserved_0x37; - register8_t reserved_0x38; - register8_t reserved_0x39; - register8_t reserved_0x3A; - register8_t reserved_0x3B; - register8_t reserved_0x3C; - register8_t reserved_0x3D; - register8_t reserved_0x3E; -} NVM_PROD_SIGNATURES_t; - -/* NVM Command */ -typedef enum NVM_CMD_enum -{ - NVM_CMD_NO_OPERATION_gc = (0x00<<0), /* Noop/Ordinary LPM */ - NVM_CMD_READ_CALIB_ROW_gc = (0x02<<0), /* Read calibration row */ - NVM_CMD_READ_USER_SIG_ROW_gc = (0x01<<0), /* Read user signature row */ - NVM_CMD_READ_EEPROM_gc = (0x06<<0), /* Read EEPROM */ - NVM_CMD_READ_FUSES_gc = (0x07<<0), /* Read fuse byte */ - NVM_CMD_WRITE_LOCK_BITS_gc = (0x08<<0), /* Write lock bits */ - NVM_CMD_ERASE_USER_SIG_ROW_gc = (0x18<<0), /* Erase user signature row */ - NVM_CMD_WRITE_USER_SIG_ROW_gc = (0x1A<<0), /* Write user signature row */ - NVM_CMD_ERASE_APP_gc = (0x20<<0), /* Erase Application Section */ - NVM_CMD_ERASE_APP_PAGE_gc = (0x22<<0), /* Erase Application Section page */ - NVM_CMD_LOAD_FLASH_BUFFER_gc = (0x23<<0), /* Load Flash page buffer */ - NVM_CMD_WRITE_APP_PAGE_gc = (0x24<<0), /* Write Application Section page */ - NVM_CMD_ERASE_WRITE_APP_PAGE_gc = (0x25<<0), /* Erase-and-write Application Section page */ - NVM_CMD_ERASE_FLASH_BUFFER_gc = (0x26<<0), /* Erase/flush Flash page buffer */ - NVM_CMD_ERASE_BOOT_PAGE_gc = (0x2A<<0), /* Erase Boot Section page */ - NVM_CMD_WRITE_BOOT_PAGE_gc = (0x2C<<0), /* Write Boot Section page */ - NVM_CMD_ERASE_WRITE_BOOT_PAGE_gc = (0x2D<<0), /* Erase-and-write Boot Section page */ - NVM_CMD_ERASE_EEPROM_gc = (0x30<<0), /* Erase EEPROM */ - NVM_CMD_ERASE_EEPROM_PAGE_gc = (0x32<<0), /* Erase EEPROM page */ - NVM_CMD_LOAD_EEPROM_BUFFER_gc = (0x33<<0), /* Load EEPROM page buffer */ - NVM_CMD_WRITE_EEPROM_PAGE_gc = (0x34<<0), /* Write EEPROM page */ - NVM_CMD_ERASE_WRITE_EEPROM_PAGE_gc = (0x35<<0), /* Erase-and-write EEPROM page */ - NVM_CMD_ERASE_EEPROM_BUFFER_gc = (0x36<<0), /* Erase/flush EEPROM page buffer */ - NVM_CMD_APP_CRC_gc = (0x38<<0), /* Generate Application section CRC */ - NVM_CMD_BOOT_CRC_gc = (0x39<<0), /* Generate Boot Section CRC */ - NVM_CMD_FLASH_RANGE_CRC_gc = (0x3A<<0), /* Generate Flash Range CRC */ -} NVM_CMD_t; - -/* SPM ready interrupt level */ -typedef enum NVM_SPMLVL_enum -{ - NVM_SPMLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ - NVM_SPMLVL_LO_gc = (0x01<<2), /* Low level */ - NVM_SPMLVL_MED_gc = (0x02<<2), /* Medium level */ - NVM_SPMLVL_HI_gc = (0x03<<2), /* High level */ -} NVM_SPMLVL_t; - -/* EEPROM ready interrupt level */ -typedef enum NVM_EELVL_enum -{ - NVM_EELVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ - NVM_EELVL_LO_gc = (0x01<<0), /* Low level */ - NVM_EELVL_MED_gc = (0x02<<0), /* Medium level */ - NVM_EELVL_HI_gc = (0x03<<0), /* High level */ -} NVM_EELVL_t; - -/* Boot lock bits - boot setcion */ -typedef enum NVM_BLBB_enum -{ - NVM_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ - NVM_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ - NVM_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ - NVM_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ -} NVM_BLBB_t; - -/* Boot lock bits - application section */ -typedef enum NVM_BLBA_enum -{ - NVM_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ - NVM_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ - NVM_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ - NVM_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ -} NVM_BLBA_t; - -/* Boot lock bits - application table section */ -typedef enum NVM_BLBAT_enum -{ - NVM_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ - NVM_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ - NVM_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ - NVM_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ -} NVM_BLBAT_t; - -/* Lock bits */ -typedef enum NVM_LB_enum -{ - NVM_LB_NOLOCK_gc = (0x03<<0), /* No locks */ - NVM_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ - NVM_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ -} NVM_LB_t; - -/* Boot Loader Section Reset Vector */ -typedef enum BOOTRST_enum -{ - BOOTRST_BOOTLDR_gc = (0x00<<6), /* Boot Loader Reset */ - BOOTRST_APPLICATION_gc = (0x01<<6), /* Application Reset */ -} BOOTRST_t; - -/* BOD operation */ -typedef enum BOD_enum -{ - BOD_INSAMPLEDMODE_gc = (0x01<<0), /* BOD enabled in sampled mode */ - BOD_CONTINOUSLY_gc = (0x02<<0), /* BOD enabled continuously */ - BOD_DISABLED_gc = (0x03<<0), /* BOD Disabled */ -} BOD_t; - -/* Watchdog (Window) Timeout Period */ -typedef enum WD_enum -{ - WD_8CLK_gc = (0x00<<4), /* 8 cycles (8ms @ 3.3V) */ - WD_16CLK_gc = (0x01<<4), /* 16 cycles (16ms @ 3.3V) */ - WD_32CLK_gc = (0x02<<4), /* 32 cycles (32ms @ 3.3V) */ - WD_64CLK_gc = (0x03<<4), /* 64 cycles (64ms @ 3.3V) */ - WD_128CLK_gc = (0x04<<4), /* 128 cycles (0.125s @ 3.3V) */ - WD_256CLK_gc = (0x05<<4), /* 256 cycles (0.25s @ 3.3V) */ - WD_512CLK_gc = (0x06<<4), /* 512 cycles (0.5s @ 3.3V) */ - WD_1KCLK_gc = (0x07<<4), /* 1K cycles (1s @ 3.3V) */ - WD_2KCLK_gc = (0x08<<4), /* 2K cycles (2s @ 3.3V) */ - WD_4KCLK_gc = (0x09<<4), /* 4K cycles (4s @ 3.3V) */ - WD_8KCLK_gc = (0x0A<<4), /* 8K cycles (8s @ 3.3V) */ -} WD_t; - -/* Start-up Time */ -typedef enum SUT_enum -{ - SUT_0MS_gc = (0x03<<2), /* 0 ms */ - SUT_4MS_gc = (0x01<<2), /* 4 ms */ - SUT_64MS_gc = (0x00<<2), /* 64 ms */ -} SUT_t; - -/* Brown Out Detection Voltage Level */ -typedef enum BODLVL_enum -{ - BODLVL_1V6_gc = (0x07<<0), /* 1.6 V */ - BODLVL_1V9_gc = (0x06<<0), /* 1.8 V */ - BODLVL_2V1_gc = (0x05<<0), /* 2.0 V */ - BODLVL_2V4_gc = (0x04<<0), /* 2.2 V */ - BODLVL_2V6_gc = (0x03<<0), /* 2.4 V */ - BODLVL_2V9_gc = (0x02<<0), /* 2.7 V */ - BODLVL_3V2_gc = (0x01<<0), /* 2.9 V */ -} BODLVL_t; - - -/* --------------------------------------------------------------------------- -AC - Analog Comparator --------------------------------------------------------------------------- -*/ - -/* Analog Comparator */ -typedef struct AC_struct -{ - register8_t AC0CTRL; /* Comparator 0 Control */ - register8_t AC1CTRL; /* Comparator 1 Control */ - register8_t AC0MUXCTRL; /* Comparator 0 MUX Control */ - register8_t AC1MUXCTRL; /* Comparator 1 MUX Control */ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t WINCTRL; /* Window Mode Control */ - register8_t STATUS; /* Status */ -} AC_t; - -/* Interrupt mode */ -typedef enum AC_INTMODE_enum -{ - AC_INTMODE_BOTHEDGES_gc = (0x00<<6), /* Interrupt on both edges */ - AC_INTMODE_FALLING_gc = (0x02<<6), /* Interrupt on falling edge */ - AC_INTMODE_RISING_gc = (0x03<<6), /* Interrupt on rising edge */ -} AC_INTMODE_t; - -/* Interrupt level */ -typedef enum AC_INTLVL_enum -{ - AC_INTLVL_OFF_gc = (0x00<<4), /* Interrupt disabled */ - AC_INTLVL_LO_gc = (0x01<<4), /* Low level */ - AC_INTLVL_MED_gc = (0x02<<4), /* Medium level */ - AC_INTLVL_HI_gc = (0x03<<4), /* High level */ -} AC_INTLVL_t; - -/* Hysteresis mode selection */ -typedef enum AC_HYSMODE_enum -{ - AC_HYSMODE_NO_gc = (0x00<<1), /* No hysteresis */ - AC_HYSMODE_SMALL_gc = (0x01<<1), /* Small hysteresis */ - AC_HYSMODE_LARGE_gc = (0x02<<1), /* Large hysteresis */ -} AC_HYSMODE_t; - -/* Positive input multiplexer selection */ -typedef enum AC_MUXPOS_enum -{ - AC_MUXPOS_PIN0_gc = (0x00<<3), /* Pin 0 */ - AC_MUXPOS_PIN1_gc = (0x01<<3), /* Pin 1 */ - AC_MUXPOS_PIN2_gc = (0x02<<3), /* Pin 2 */ - AC_MUXPOS_PIN3_gc = (0x03<<3), /* Pin 3 */ - AC_MUXPOS_PIN4_gc = (0x04<<3), /* Pin 4 */ - AC_MUXPOS_PIN5_gc = (0x05<<3), /* Pin 5 */ - AC_MUXPOS_PIN6_gc = (0x06<<3), /* Pin 6 */ - AC_MUXPOS_DAC_gc = (0x07<<3), /* DAC output */ -} AC_MUXPOS_t; - -/* Negative input multiplexer selection */ -typedef enum AC_MUXNEG_enum -{ - AC_MUXNEG_PIN0_gc = (0x00<<0), /* Pin 0 */ - AC_MUXNEG_PIN1_gc = (0x01<<0), /* Pin 1 */ - AC_MUXNEG_PIN3_gc = (0x02<<0), /* Pin 3 */ - AC_MUXNEG_PIN5_gc = (0x03<<0), /* Pin 5 */ - AC_MUXNEG_PIN7_gc = (0x04<<0), /* Pin 7 */ - AC_MUXNEG_DAC_gc = (0x05<<0), /* DAC output */ - AC_MUXNEG_BANDGAP_gc = (0x06<<0), /* Bandgap Reference */ - AC_MUXNEG_SCALER_gc = (0x07<<0), /* Internal voltage scaler */ -} AC_MUXNEG_t; - -/* Windows interrupt mode */ -typedef enum AC_WINTMODE_enum -{ - AC_WINTMODE_ABOVE_gc = (0x00<<2), /* Interrupt on above window */ - AC_WINTMODE_INSIDE_gc = (0x01<<2), /* Interrupt on inside window */ - AC_WINTMODE_BELOW_gc = (0x02<<2), /* Interrupt on below window */ - AC_WINTMODE_OUTSIDE_gc = (0x03<<2), /* Interrupt on outside window */ -} AC_WINTMODE_t; - -/* Window interrupt level */ -typedef enum AC_WINTLVL_enum -{ - AC_WINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ - AC_WINTLVL_LO_gc = (0x01<<0), /* Low priority */ - AC_WINTLVL_MED_gc = (0x02<<0), /* Medium priority */ - AC_WINTLVL_HI_gc = (0x03<<0), /* High priority */ -} AC_WINTLVL_t; - -/* Window mode state */ -typedef enum AC_WSTATE_enum -{ - AC_WSTATE_ABOVE_gc = (0x00<<6), /* Signal above window */ - AC_WSTATE_INSIDE_gc = (0x01<<6), /* Signal inside window */ - AC_WSTATE_BELOW_gc = (0x02<<6), /* Signal below window */ -} AC_WSTATE_t; - - -/* --------------------------------------------------------------------------- -ADC - Analog/Digital Converter --------------------------------------------------------------------------- -*/ - -/* ADC Channel */ -typedef struct ADC_CH_struct -{ - register8_t CTRL; /* Control Register */ - register8_t MUXCTRL; /* MUX Control */ - register8_t INTCTRL; /* Channel Interrupt Control */ - register8_t INTFLAGS; /* Interrupt Flags */ - _WORDREGISTER(RES); /* Channel Result */ - register8_t reserved_0x6; - register8_t reserved_0x7; -} ADC_CH_t; - -/* --------------------------------------------------------------------------- -ADC - Analog/Digital Converter --------------------------------------------------------------------------- -*/ - -/* Analog-to-Digital Converter */ -typedef struct ADC_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t REFCTRL; /* Reference Control */ - register8_t EVCTRL; /* Event Control */ - register8_t PRESCALER; /* Clock Prescaler */ - register8_t reserved_0x05; - register8_t INTFLAGS; /* Interrupt Flags */ - register8_t reserved_0x07; - register8_t reserved_0x08; - register8_t reserved_0x09; - register8_t reserved_0x0A; - register8_t reserved_0x0B; - _WORDREGISTER(CAL); /* Calibration Value */ - register8_t reserved_0x0E; - register8_t reserved_0x0F; - _WORDREGISTER(CH0RES); /* Channel 0 Result */ - _WORDREGISTER(CH1RES); /* Channel 1 Result */ - _WORDREGISTER(CH2RES); /* Channel 2 Result */ - _WORDREGISTER(CH3RES); /* Channel 3 Result */ - _WORDREGISTER(CMP); /* Compare Value */ - register8_t reserved_0x1A; - register8_t reserved_0x1B; - register8_t reserved_0x1C; - register8_t reserved_0x1D; - register8_t reserved_0x1E; - register8_t reserved_0x1F; - ADC_CH_t CH0; /* ADC Channel 0 */ - ADC_CH_t CH1; /* ADC Channel 1 */ - ADC_CH_t CH2; /* ADC Channel 2 */ - ADC_CH_t CH3; /* ADC Channel 3 */ -} ADC_t; - -/* Positive input multiplexer selection */ -typedef enum ADC_CH_MUXPOS_enum -{ - ADC_CH_MUXPOS_PIN0_gc = (0x00<<3), /* Input pin 0 */ - ADC_CH_MUXPOS_PIN1_gc = (0x01<<3), /* Input pin 1 */ - ADC_CH_MUXPOS_PIN2_gc = (0x02<<3), /* Input pin 2 */ - ADC_CH_MUXPOS_PIN3_gc = (0x03<<3), /* Input pin 3 */ - ADC_CH_MUXPOS_PIN4_gc = (0x04<<3), /* Input pin 4 */ - ADC_CH_MUXPOS_PIN5_gc = (0x05<<3), /* Input pin 5 */ - ADC_CH_MUXPOS_PIN6_gc = (0x06<<3), /* Input pin 6 */ - ADC_CH_MUXPOS_PIN7_gc = (0x07<<3), /* Input pin 7 */ -} ADC_CH_MUXPOS_t; - -/* Internal input multiplexer selections */ -typedef enum ADC_CH_MUXINT_enum -{ - ADC_CH_MUXINT_TEMP_gc = (0x00<<3), /* Temperature Reference */ - ADC_CH_MUXINT_BANDGAP_gc = (0x01<<3), /* Bandgap Reference */ - ADC_CH_MUXINT_SCALEDVCC_gc = (0x02<<3), /* 1/10 scaled VCC */ - ADC_CH_MUXINT_DAC_gc = (0x03<<3), /* DAC output */ -} ADC_CH_MUXINT_t; - -/* Negative input multiplexer selection */ -typedef enum ADC_CH_MUXNEG_enum -{ - ADC_CH_MUXNEG_PIN0_gc = (0x00<<0), /* Input pin 0 */ - ADC_CH_MUXNEG_PIN1_gc = (0x01<<0), /* Input pin 1 */ - ADC_CH_MUXNEG_PIN2_gc = (0x02<<0), /* Input pin 2 */ - ADC_CH_MUXNEG_PIN3_gc = (0x03<<0), /* Input pin 3 */ - ADC_CH_MUXNEG_PIN4_gc = (0x04<<0), /* Input pin 4 */ - ADC_CH_MUXNEG_PIN5_gc = (0x05<<0), /* Input pin 5 */ - ADC_CH_MUXNEG_PIN6_gc = (0x06<<0), /* Input pin 6 */ - ADC_CH_MUXNEG_PIN7_gc = (0x07<<0), /* Input pin 7 */ -} ADC_CH_MUXNEG_t; - -/* Input mode */ -typedef enum ADC_CH_INPUTMODE_enum -{ - ADC_CH_INPUTMODE_INTERNAL_gc = (0x00<<0), /* Internal inputs, no gain */ - ADC_CH_INPUTMODE_SINGLEENDED_gc = (0x01<<0), /* Single-ended input, no gain */ - ADC_CH_INPUTMODE_DIFF_gc = (0x02<<0), /* Differential input, no gain */ - ADC_CH_INPUTMODE_DIFFWGAIN_gc = (0x03<<0), /* Differential input, with gain */ -} ADC_CH_INPUTMODE_t; - -/* Gain factor */ -typedef enum ADC_CH_GAIN_enum -{ - ADC_CH_GAIN_1X_gc = (0x00<<2), /* 1x gain */ - ADC_CH_GAIN_2X_gc = (0x01<<2), /* 2x gain */ - ADC_CH_GAIN_4X_gc = (0x02<<2), /* 4x gain */ - ADC_CH_GAIN_8X_gc = (0x03<<2), /* 8x gain */ - ADC_CH_GAIN_16X_gc = (0x04<<2), /* 16x gain */ - ADC_CH_GAIN_32X_gc = (0x05<<2), /* 32x gain */ - ADC_CH_GAIN_64X_gc = (0x06<<2), /* 64x gain */ -} ADC_CH_GAIN_t; - -/* Conversion result resolution */ -typedef enum ADC_RESOLUTION_enum -{ - ADC_RESOLUTION_12BIT_gc = (0x00<<1), /* 12-bit right-adjusted result */ - ADC_RESOLUTION_8BIT_gc = (0x02<<1), /* 8-bit right-adjusted result */ - ADC_RESOLUTION_LEFT12BIT_gc = (0x03<<1), /* 12-bit left-adjusted result */ -} ADC_RESOLUTION_t; - -/* Voltage reference selection */ -typedef enum ADC_REFSEL_enum -{ - ADC_REFSEL_INT1V_gc = (0x00<<4), /* Internal 1V */ - ADC_REFSEL_VCC_gc = (0x01<<4), /* Internal VCC / 1.6V */ - ADC_REFSEL_AREFA_gc = (0x02<<4), /* External reference on PORT A */ - ADC_REFSEL_AREFB_gc = (0x03<<4), /* External reference on PORT B */ -} ADC_REFSEL_t; - -/* Channel sweep selection */ -typedef enum ADC_SWEEP_enum -{ - ADC_SWEEP_0_gc = (0x00<<6), /* ADC Channel 0 */ - ADC_SWEEP_01_gc = (0x01<<6), /* ADC Channel 0,1 */ - ADC_SWEEP_012_gc = (0x02<<6), /* ADC Channel 0,1,2 */ - ADC_SWEEP_0123_gc = (0x03<<6), /* ADC Channel 0,1,2,3 */ -} ADC_SWEEP_t; - -/* Event channel input selection */ -typedef enum ADC_EVSEL_enum -{ - ADC_EVSEL_0123_gc = (0x00<<3), /* Event Channel 0,1,2,3 */ - ADC_EVSEL_1234_gc = (0x01<<3), /* Event Channel 1,2,3,4 */ - ADC_EVSEL_2345_gc = (0x02<<3), /* Event Channel 2,3,4,5 */ - ADC_EVSEL_3456_gc = (0x03<<3), /* Event Channel 3,4,5,6 */ - ADC_EVSEL_4567_gc = (0x04<<3), /* Event Channel 4,5,6,7 */ - ADC_EVSEL_567_gc = (0x05<<3), /* Event Channel 5,6,7 */ - ADC_EVSEL_67_gc = (0x06<<3), /* Event Channel 6,7 */ - ADC_EVSEL_7_gc = (0x07<<3), /* Event Channel 7 */ -} ADC_EVSEL_t; - -/* Event action selection */ -typedef enum ADC_EVACT_enum -{ - ADC_EVACT_NONE_gc = (0x00<<0), /* No event action */ - ADC_EVACT_CH0_gc = (0x01<<0), /* First event triggers channel 0 */ - ADC_EVACT_CH01_gc = (0x02<<0), /* First two events trigger channel 0,1 */ - ADC_EVACT_CH012_gc = (0x03<<0), /* First three events trigger channel 0,1,2 */ - ADC_EVACT_CH0123_gc = (0x04<<0), /* Events trigger channel 0,1,2,3 */ - ADC_EVACT_SWEEP_gc = (0x05<<0), /* First event triggers sweep */ - ADC_EVACT_SYNCHSWEEP_gc = (0x06<<0), /* First event triggers synchronized sweep */ -} ADC_EVACT_t; - -/* Interupt mode */ -typedef enum ADC_CH_INTMODE_enum -{ - ADC_CH_INTMODE_COMPLETE_gc = (0x00<<2), /* Interrupt on conversion complete */ - ADC_CH_INTMODE_BELOW_gc = (0x01<<2), /* Interrupt on result below compare value */ - ADC_CH_INTMODE_ABOVE_gc = (0x03<<2), /* Interrupt on result above compare value */ -} ADC_CH_INTMODE_t; - -/* Interrupt level */ -typedef enum ADC_CH_INTLVL_enum -{ - ADC_CH_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ - ADC_CH_INTLVL_LO_gc = (0x01<<0), /* Low level */ - ADC_CH_INTLVL_MED_gc = (0x02<<0), /* Medium level */ - ADC_CH_INTLVL_HI_gc = (0x03<<0), /* High level */ -} ADC_CH_INTLVL_t; - -/* DMA request selection */ -typedef enum ADC_DMASEL_enum -{ - ADC_DMASEL_OFF_gc = (0x00<<6), /* Combined DMA request OFF */ - ADC_DMASEL_CH01_gc = (0x01<<6), /* ADC Channel 0 or 1 */ - ADC_DMASEL_CH012_gc = (0x02<<6), /* ADC Channel 0 or 1 or 2 */ - ADC_DMASEL_CH0123_gc = (0x03<<6), /* ADC Channel 0 or 1 or 2 or 3 */ -} ADC_DMASEL_t; - -/* Clock prescaler */ -typedef enum ADC_PRESCALER_enum -{ - ADC_PRESCALER_DIV4_gc = (0x00<<0), /* Divide clock by 4 */ - ADC_PRESCALER_DIV8_gc = (0x01<<0), /* Divide clock by 8 */ - ADC_PRESCALER_DIV16_gc = (0x02<<0), /* Divide clock by 16 */ - ADC_PRESCALER_DIV32_gc = (0x03<<0), /* Divide clock by 32 */ - ADC_PRESCALER_DIV64_gc = (0x04<<0), /* Divide clock by 64 */ - ADC_PRESCALER_DIV128_gc = (0x05<<0), /* Divide clock by 128 */ - ADC_PRESCALER_DIV256_gc = (0x06<<0), /* Divide clock by 256 */ - ADC_PRESCALER_DIV512_gc = (0x07<<0), /* Divide clock by 512 */ -} ADC_PRESCALER_t; - - -/* --------------------------------------------------------------------------- -DAC - Digital/Analog Converter --------------------------------------------------------------------------- -*/ - -/* Digital-to-Analog Converter */ -typedef struct DAC_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t CTRLC; /* Control Register C */ - register8_t EVCTRL; /* Event Input Control */ - register8_t TIMCTRL; /* Timing Control */ - register8_t STATUS; /* Status */ - register8_t reserved_0x06; - register8_t reserved_0x07; - register8_t GAINCAL; /* Gain Calibration */ - register8_t OFFSETCAL; /* Offset Calibration */ - register8_t reserved_0x0A; - register8_t reserved_0x0B; - register8_t reserved_0x0C; - register8_t reserved_0x0D; - register8_t reserved_0x0E; - register8_t reserved_0x0F; - register8_t reserved_0x10; - register8_t reserved_0x11; - register8_t reserved_0x12; - register8_t reserved_0x13; - register8_t reserved_0x14; - register8_t reserved_0x15; - register8_t reserved_0x16; - register8_t reserved_0x17; - _WORDREGISTER(CH0DATA); /* Channel 0 Data */ - _WORDREGISTER(CH1DATA); /* Channel 1 Data */ -} DAC_t; - -/* Output channel selection */ -typedef enum DAC_CHSEL_enum -{ - DAC_CHSEL_SINGLE_gc = (0x00<<5), /* Single channel operation (Channel A only) */ - DAC_CHSEL_DUAL_gc = (0x02<<5), /* Dual channel operation (S/H on both channels) */ -} DAC_CHSEL_t; - -/* Reference voltage selection */ -typedef enum DAC_REFSEL_enum -{ - DAC_REFSEL_INT1V_gc = (0x00<<3), /* Internal 1V */ - DAC_REFSEL_AVCC_gc = (0x01<<3), /* Analog supply voltage */ - DAC_REFSEL_AREFA_gc = (0x02<<3), /* External reference on AREF on PORTA */ - DAC_REFSEL_AREFB_gc = (0x03<<3), /* External reference on AREF on PORTB */ -} DAC_REFSEL_t; - -/* Event channel selection */ -typedef enum DAC_EVSEL_enum -{ - DAC_EVSEL_0_gc = (0x00<<0), /* Event Channel 0 */ - DAC_EVSEL_1_gc = (0x01<<0), /* Event Channel 1 */ - DAC_EVSEL_2_gc = (0x02<<0), /* Event Channel 2 */ - DAC_EVSEL_3_gc = (0x03<<0), /* Event Channel 3 */ - DAC_EVSEL_4_gc = (0x04<<0), /* Event Channel 4 */ - DAC_EVSEL_5_gc = (0x05<<0), /* Event Channel 5 */ - DAC_EVSEL_6_gc = (0x06<<0), /* Event Channel 6 */ - DAC_EVSEL_7_gc = (0x07<<0), /* Event Channel 7 */ -} DAC_EVSEL_t; - -/* Conversion interval */ -typedef enum DAC_CONINTVAL_enum -{ - DAC_CONINTVAL_1CLK_gc = (0x00<<4), /* 1 CLK / 2 CLK in S/H mode */ - DAC_CONINTVAL_2CLK_gc = (0x01<<4), /* 2 CLK / 3 CLK in S/H mode */ - DAC_CONINTVAL_4CLK_gc = (0x02<<4), /* 4 CLK / 6 CLK in S/H mode */ - DAC_CONINTVAL_8CLK_gc = (0x03<<4), /* 8 CLK / 12 CLK in S/H mode */ - DAC_CONINTVAL_16CLK_gc = (0x04<<4), /* 16 CLK / 24 CLK in S/H mode */ - DAC_CONINTVAL_32CLK_gc = (0x05<<4), /* 32 CLK / 48 CLK in S/H mode */ - DAC_CONINTVAL_64CLK_gc = (0x06<<4), /* 64 CLK / 96 CLK in S/H mode */ - DAC_CONINTVAL_128CLK_gc = (0x07<<4), /* 128 CLK / 192 CLK in S/H mode */ -} DAC_CONINTVAL_t; - -/* Refresh rate */ -typedef enum DAC_REFRESH_enum -{ - DAC_REFRESH_16CLK_gc = (0x00<<0), /* 16 CLK */ - DAC_REFRESH_32CLK_gc = (0x01<<0), /* 32 CLK */ - DAC_REFRESH_64CLK_gc = (0x02<<0), /* 64 CLK */ - DAC_REFRESH_128CLK_gc = (0x03<<0), /* 128 CLK */ - DAC_REFRESH_256CLK_gc = (0x04<<0), /* 256 CLK */ - DAC_REFRESH_512CLK_gc = (0x05<<0), /* 512 CLK */ - DAC_REFRESH_1024CLK_gc = (0x06<<0), /* 1024 CLK */ - DAC_REFRESH_2048CLK_gc = (0x07<<0), /* 2048 CLK */ - DAC_REFRESH_4096CLK_gc = (0x08<<0), /* 4096 CLK */ - DAC_REFRESH_8192CLK_gc = (0x09<<0), /* 8192 CLK */ - DAC_REFRESH_16384CLK_gc = (0x0A<<0), /* 16384 CLK */ - DAC_REFRESH_32768CLK_gc = (0x0B<<0), /* 32768 CLK */ - DAC_REFRESH_65536CLK_gc = (0x0C<<0), /* 65536 CLK */ - DAC_REFRESH_OFF_gc = (0x0F<<0), /* Auto refresh OFF */ -} DAC_REFRESH_t; - - -/* --------------------------------------------------------------------------- -RTC - Real-Time Clounter --------------------------------------------------------------------------- -*/ - -/* Real-Time Counter */ -typedef struct RTC_struct -{ - register8_t CTRL; /* Control Register */ - register8_t STATUS; /* Status Register */ - register8_t INTCTRL; /* Interrupt Control Register */ - register8_t INTFLAGS; /* Interrupt Flags */ - register8_t TEMP; /* Temporary register */ - register8_t reserved_0x05; - register8_t reserved_0x06; - register8_t reserved_0x07; - _WORDREGISTER(CNT); /* Count Register */ - _WORDREGISTER(PER); /* Period Register */ - _WORDREGISTER(COMP); /* Compare Register */ -} RTC_t; - -/* Prescaler Factor */ -typedef enum RTC_PRESCALER_enum -{ - RTC_PRESCALER_OFF_gc = (0x00<<0), /* RTC Off */ - RTC_PRESCALER_DIV1_gc = (0x01<<0), /* RTC Clock */ - RTC_PRESCALER_DIV2_gc = (0x02<<0), /* RTC Clock / 2 */ - RTC_PRESCALER_DIV8_gc = (0x03<<0), /* RTC Clock / 8 */ - RTC_PRESCALER_DIV16_gc = (0x04<<0), /* RTC Clock / 16 */ - RTC_PRESCALER_DIV64_gc = (0x05<<0), /* RTC Clock / 64 */ - RTC_PRESCALER_DIV256_gc = (0x06<<0), /* RTC Clock / 256 */ - RTC_PRESCALER_DIV1024_gc = (0x07<<0), /* RTC Clock / 1024 */ -} RTC_PRESCALER_t; - -/* Compare Interrupt level */ -typedef enum RTC_COMPINTLVL_enum -{ - RTC_COMPINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ - RTC_COMPINTLVL_LO_gc = (0x01<<2), /* Low Level */ - RTC_COMPINTLVL_MED_gc = (0x02<<2), /* Medium Level */ - RTC_COMPINTLVL_HI_gc = (0x03<<2), /* High Level */ -} RTC_COMPINTLVL_t; - -/* Overflow Interrupt level */ -typedef enum RTC_OVFINTLVL_enum -{ - RTC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - RTC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ - RTC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ - RTC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ -} RTC_OVFINTLVL_t; - - -/* --------------------------------------------------------------------------- -EBI - External Bus Interface --------------------------------------------------------------------------- -*/ - -/* EBI Chip Select Module */ -typedef struct EBI_CS_struct -{ - register8_t CTRLA; /* Chip Select Control Register A */ - register8_t CTRLB; /* Chip Select Control Register B */ - _WORDREGISTER(BASEADDR); /* Chip Select Base Address */ -} EBI_CS_t; - -/* --------------------------------------------------------------------------- -EBI - External Bus Interface --------------------------------------------------------------------------- -*/ - -/* External Bus Interface */ -typedef struct EBI_struct -{ - register8_t CTRL; /* Control */ - register8_t SDRAMCTRLA; /* SDRAM Control Register A */ - register8_t reserved_0x02; - register8_t reserved_0x03; - _WORDREGISTER(REFRESH); /* SDRAM Refresh Period */ - _WORDREGISTER(INITDLY); /* SDRAM Initialization Delay */ - register8_t SDRAMCTRLB; /* SDRAM Control Register B */ - register8_t SDRAMCTRLC; /* SDRAM Control Register C */ - register8_t reserved_0x0A; - register8_t reserved_0x0B; - register8_t reserved_0x0C; - register8_t reserved_0x0D; - register8_t reserved_0x0E; - register8_t reserved_0x0F; - EBI_CS_t CS0; /* Chip Select 0 */ - EBI_CS_t CS1; /* Chip Select 1 */ - EBI_CS_t CS2; /* Chip Select 2 */ - EBI_CS_t CS3; /* Chip Select 3 */ -} EBI_t; - -/* Chip Select adress space */ -typedef enum EBI_CS_ASIZE_enum -{ - EBI_CS_ASIZE_256B_gc = (0x00<<2), /* 256 bytes */ - EBI_CS_ASIZE_512B_gc = (0x01<<2), /* 512 bytes */ - EBI_CS_ASIZE_1KB_gc = (0x02<<2), /* 1K bytes */ - EBI_CS_ASIZE_2KB_gc = (0x03<<2), /* 2K bytes */ - EBI_CS_ASIZE_4KB_gc = (0x04<<2), /* 4K bytes */ - EBI_CS_ASIZE_8KB_gc = (0x05<<2), /* 8K bytes */ - EBI_CS_ASIZE_16KB_gc = (0x06<<2), /* 16K bytes */ - EBI_CS_ASIZE_32KB_gc = (0x07<<2), /* 32K bytes */ - EBI_CS_ASIZE_64KB_gc = (0x08<<2), /* 64K bytes */ - EBI_CS_ASIZE_128KB_gc = (0x09<<2), /* 128K bytes */ - EBI_CS_ASIZE_256KB_gc = (0x0A<<2), /* 256K bytes */ - EBI_CS_ASIZE_512KB_gc = (0x0B<<2), /* 512K bytes */ - EBI_CS_ASIZE_1MB_gc = (0x0C<<2), /* 1M bytes */ - EBI_CS_ASIZE_2MB_gc = (0x0D<<2), /* 2M bytes */ - EBI_CS_ASIZE_4MB_gc = (0x0E<<2), /* 4M bytes */ - EBI_CS_ASIZE_8MB_gc = (0x0F<<2), /* 8M bytes */ - EBI_CS_ASIZE_16M_gc = (0x10<<2), /* 16M bytes */ -} EBI_CS_ASIZE_t; - -/* */ -typedef enum EBI_CS_SRWS_enum -{ - EBI_CS_SRWS_0CLK_gc = (0x00<<0), /* 0 cycles */ - EBI_CS_SRWS_1CLK_gc = (0x01<<0), /* 1 cycle */ - EBI_CS_SRWS_2CLK_gc = (0x02<<0), /* 2 cycles */ - EBI_CS_SRWS_3CLK_gc = (0x03<<0), /* 3 cycles */ - EBI_CS_SRWS_4CLK_gc = (0x04<<0), /* 4 cycles */ - EBI_CS_SRWS_5CLK_gc = (0x05<<0), /* 5 cycle */ - EBI_CS_SRWS_6CLK_gc = (0x06<<0), /* 6 cycles */ - EBI_CS_SRWS_7CLK_gc = (0x07<<0), /* 7 cycles */ -} EBI_CS_SRWS_t; - -/* Chip Select address mode */ -typedef enum EBI_CS_MODE_enum -{ - EBI_CS_MODE_DISABLED_gc = (0x00<<0), /* Chip Select Disabled */ - EBI_CS_MODE_SRAM_gc = (0x01<<0), /* Chip Select in SRAM mode */ - EBI_CS_MODE_LPC_gc = (0x02<<0), /* Chip Select in SRAM LPC mode */ - EBI_CS_MODE_SDRAM_gc = (0x03<<0), /* Chip Select in SDRAM mode */ -} EBI_CS_MODE_t; - -/* Chip Select SDRAM mode */ -typedef enum EBI_CS_SDMODE_enum -{ - EBI_CS_SDMODE_NORMAL_gc = (0x00<<0), /* Normal mode */ - EBI_CS_SDMODE_LOAD_gc = (0x01<<0), /* Load Mode Register command mode */ -} EBI_CS_SDMODE_t; - -/* */ -typedef enum EBI_SDDATAW_enum -{ - EBI_SDDATAW_4BIT_gc = (0x00<<6), /* 4-bit data bus */ - EBI_SDDATAW_8BIT_gc = (0x01<<6), /* 8-bit data bus */ -} EBI_SDDATAW_t; - -/* */ -typedef enum EBI_LPCMODE_enum -{ - EBI_LPCMODE_ALE1_gc = (0x00<<4), /* Data muxed with addr byte 0 */ - EBI_LPCMODE_ALE12_gc = (0x02<<4), /* Data muxed with addr byte 0 and 1 */ -} EBI_LPCMODE_t; - -/* */ -typedef enum EBI_SRMODE_enum -{ - EBI_SRMODE_ALE1_gc = (0x00<<2), /* Addr byte 0 muxed with 1 */ - EBI_SRMODE_ALE2_gc = (0x01<<2), /* Addr byte 0 muxed with 2 */ - EBI_SRMODE_ALE12_gc = (0x02<<2), /* Addr byte 0 muxed with 1 and 2 */ - EBI_SRMODE_NOALE_gc = (0x03<<2), /* No addr muxing */ -} EBI_SRMODE_t; - -/* */ -typedef enum EBI_IFMODE_enum -{ - EBI_IFMODE_DISABLED_gc = (0x00<<0), /* EBI Disabled */ - EBI_IFMODE_3PORT_gc = (0x01<<0), /* 3-port mode */ - EBI_IFMODE_4PORT_gc = (0x02<<0), /* 4-port mode */ - EBI_IFMODE_2PORT_gc = (0x03<<0), /* 2-port mode */ -} EBI_IFMODE_t; - -/* */ -typedef enum EBI_SDCOL_enum -{ - EBI_SDCOL_8BIT_gc = (0x00<<0), /* 8 column bits */ - EBI_SDCOL_9BIT_gc = (0x01<<0), /* 9 column bits */ - EBI_SDCOL_10BIT_gc = (0x02<<0), /* 10 column bits */ - EBI_SDCOL_11BIT_gc = (0x03<<0), /* 11 column bits */ -} EBI_SDCOL_t; - -/* */ -typedef enum EBI_MRDLY_enum -{ - EBI_MRDLY_0CLK_gc = (0x00<<6), /* 0 cycles */ - EBI_MRDLY_1CLK_gc = (0x01<<6), /* 1 cycle */ - EBI_MRDLY_2CLK_gc = (0x02<<6), /* 2 cycles */ - EBI_MRDLY_3CLK_gc = (0x03<<6), /* 3 cycles */ -} EBI_MRDLY_t; - -/* */ -typedef enum EBI_ROWCYCDLY_enum -{ - EBI_ROWCYCDLY_0CLK_gc = (0x00<<3), /* 0 cycles */ - EBI_ROWCYCDLY_1CLK_gc = (0x01<<3), /* 1 cycle */ - EBI_ROWCYCDLY_2CLK_gc = (0x02<<3), /* 2 cycles */ - EBI_ROWCYCDLY_3CLK_gc = (0x03<<3), /* 3 cycles */ - EBI_ROWCYCDLY_4CLK_gc = (0x04<<3), /* 4 cycles */ - EBI_ROWCYCDLY_5CLK_gc = (0x05<<3), /* 5 cycle */ - EBI_ROWCYCDLY_6CLK_gc = (0x06<<3), /* 6 cycles */ - EBI_ROWCYCDLY_7CLK_gc = (0x07<<3), /* 7 cycles */ -} EBI_ROWCYCDLY_t; - -/* */ -typedef enum EBI_RPDLY_enum -{ - EBI_RPDLY_0CLK_gc = (0x00<<0), /* 0 cycles */ - EBI_RPDLY_1CLK_gc = (0x01<<0), /* 1 cycle */ - EBI_RPDLY_2CLK_gc = (0x02<<0), /* 2 cycles */ - EBI_RPDLY_3CLK_gc = (0x03<<0), /* 3 cycles */ - EBI_RPDLY_4CLK_gc = (0x04<<0), /* 4 cycles */ - EBI_RPDLY_5CLK_gc = (0x05<<0), /* 5 cycle */ - EBI_RPDLY_6CLK_gc = (0x06<<0), /* 6 cycles */ - EBI_RPDLY_7CLK_gc = (0x07<<0), /* 7 cycles */ -} EBI_RPDLY_t; - -/* */ -typedef enum EBI_WRDLY_enum -{ - EBI_WRDLY_0CLK_gc = (0x00<<6), /* 0 cycles */ - EBI_WRDLY_1CLK_gc = (0x01<<6), /* 1 cycle */ - EBI_WRDLY_2CLK_gc = (0x02<<6), /* 2 cycles */ - EBI_WRDLY_3CLK_gc = (0x03<<6), /* 3 cycles */ -} EBI_WRDLY_t; - -/* */ -typedef enum EBI_ESRDLY_enum -{ - EBI_ESRDLY_0CLK_gc = (0x00<<3), /* 0 cycles */ - EBI_ESRDLY_1CLK_gc = (0x01<<3), /* 1 cycle */ - EBI_ESRDLY_2CLK_gc = (0x02<<3), /* 2 cycles */ - EBI_ESRDLY_3CLK_gc = (0x03<<3), /* 3 cycles */ - EBI_ESRDLY_4CLK_gc = (0x04<<3), /* 4 cycles */ - EBI_ESRDLY_5CLK_gc = (0x05<<3), /* 5 cycle */ - EBI_ESRDLY_6CLK_gc = (0x06<<3), /* 6 cycles */ - EBI_ESRDLY_7CLK_gc = (0x07<<3), /* 7 cycles */ -} EBI_ESRDLY_t; - -/* */ -typedef enum EBI_ROWCOLDLY_enum -{ - EBI_ROWCOLDLY_0CLK_gc = (0x00<<0), /* 0 cycles */ - EBI_ROWCOLDLY_1CLK_gc = (0x01<<0), /* 1 cycle */ - EBI_ROWCOLDLY_2CLK_gc = (0x02<<0), /* 2 cycles */ - EBI_ROWCOLDLY_3CLK_gc = (0x03<<0), /* 3 cycles */ - EBI_ROWCOLDLY_4CLK_gc = (0x04<<0), /* 4 cycles */ - EBI_ROWCOLDLY_5CLK_gc = (0x05<<0), /* 5 cycle */ - EBI_ROWCOLDLY_6CLK_gc = (0x06<<0), /* 6 cycles */ - EBI_ROWCOLDLY_7CLK_gc = (0x07<<0), /* 7 cycles */ -} EBI_ROWCOLDLY_t; - - -/* --------------------------------------------------------------------------- -TWI - Two-Wire Interface --------------------------------------------------------------------------- -*/ - -/* */ -typedef struct TWI_MASTER_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t CTRLC; /* Control Register C */ - register8_t STATUS; /* Status Register */ - register8_t BAUD; /* Baurd Rate Control Register */ - register8_t ADDR; /* Address Register */ - register8_t DATA; /* Data Register */ -} TWI_MASTER_t; - -/* --------------------------------------------------------------------------- -TWI - Two-Wire Interface --------------------------------------------------------------------------- -*/ - -/* */ -typedef struct TWI_SLAVE_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t STATUS; /* Status Register */ - register8_t ADDR; /* Address Register */ - register8_t DATA; /* Data Register */ - register8_t ADDRMASK; /* Address Mask Register */ -} TWI_SLAVE_t; - -/* --------------------------------------------------------------------------- -TWI - Two-Wire Interface --------------------------------------------------------------------------- -*/ - -/* Two-Wire Interface */ -typedef struct TWI_struct -{ - register8_t CTRL; /* TWI Common Control Register */ - TWI_MASTER_t MASTER; /* TWI master module */ - TWI_SLAVE_t SLAVE; /* TWI slave module */ -} TWI_t; - -/* Master Interrupt Level */ -typedef enum TWI_MASTER_INTLVL_enum -{ - TWI_MASTER_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ - TWI_MASTER_INTLVL_LO_gc = (0x01<<6), /* Low Level */ - TWI_MASTER_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ - TWI_MASTER_INTLVL_HI_gc = (0x03<<6), /* High Level */ -} TWI_MASTER_INTLVL_t; - -/* Inactive Timeout */ -typedef enum TWI_MASTER_TIMEOUT_enum -{ - TWI_MASTER_TIMEOUT_DISABLED_gc = (0x00<<2), /* Bus Timeout Disabled */ - TWI_MASTER_TIMEOUT_50US_gc = (0x01<<2), /* 50 Microseconds */ - TWI_MASTER_TIMEOUT_100US_gc = (0x02<<2), /* 100 Microseconds */ - TWI_MASTER_TIMEOUT_200US_gc = (0x03<<2), /* 200 Microseconds */ -} TWI_MASTER_TIMEOUT_t; - -/* Master Command */ -typedef enum TWI_MASTER_CMD_enum -{ - TWI_MASTER_CMD_NOACT_gc = (0x00<<0), /* No Action */ - TWI_MASTER_CMD_REPSTART_gc = (0x01<<0), /* Issue Repeated Start Condition */ - TWI_MASTER_CMD_RECVTRANS_gc = (0x02<<0), /* Receive or Transmit Data */ - TWI_MASTER_CMD_STOP_gc = (0x03<<0), /* Issue Stop Condition */ -} TWI_MASTER_CMD_t; - -/* Master Bus State */ -typedef enum TWI_MASTER_BUSSTATE_enum -{ - TWI_MASTER_BUSSTATE_UNKNOWN_gc = (0x00<<0), /* Unknown Bus State */ - TWI_MASTER_BUSSTATE_IDLE_gc = (0x01<<0), /* Bus is Idle */ - TWI_MASTER_BUSSTATE_OWNER_gc = (0x02<<0), /* This Module Controls The Bus */ - TWI_MASTER_BUSSTATE_BUSY_gc = (0x03<<0), /* The Bus is Busy */ -} TWI_MASTER_BUSSTATE_t; - -/* Slave Interrupt Level */ -typedef enum TWI_SLAVE_INTLVL_enum -{ - TWI_SLAVE_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ - TWI_SLAVE_INTLVL_LO_gc = (0x01<<6), /* Low Level */ - TWI_SLAVE_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ - TWI_SLAVE_INTLVL_HI_gc = (0x03<<6), /* High Level */ -} TWI_SLAVE_INTLVL_t; - -/* Slave Command */ -typedef enum TWI_SLAVE_CMD_enum -{ - TWI_SLAVE_CMD_NOACT_gc = (0x00<<0), /* No Action */ - TWI_SLAVE_CMD_COMPTRANS_gc = (0x02<<0), /* Used To Complete a Transaction */ - TWI_SLAVE_CMD_RESPONSE_gc = (0x03<<0), /* Used in Response to Address/Data Interrupt */ -} TWI_SLAVE_CMD_t; - - -/* --------------------------------------------------------------------------- -PORT - Port Configuration --------------------------------------------------------------------------- -*/ - -/* I/O port Configuration */ -typedef struct PORTCFG_struct -{ - register8_t MPCMASK; /* Multi-pin Configuration Mask */ - register8_t reserved_0x01; - register8_t VPCTRLA; /* Virtual Port Control Register A */ - register8_t VPCTRLB; /* Virtual Port Control Register B */ - register8_t CLKEVOUT; /* Clock and Event Out Register */ -} PORTCFG_t; - -/* --------------------------------------------------------------------------- -PORT - Port Configuration --------------------------------------------------------------------------- -*/ - -/* Virtual Port */ -typedef struct VPORT_struct -{ - register8_t DIR; /* I/O Port Data Direction */ - register8_t OUT; /* I/O Port Output */ - register8_t IN; /* I/O Port Input */ - register8_t INTFLAGS; /* Interrupt Flag Register */ -} VPORT_t; - -/* --------------------------------------------------------------------------- -PORT - Port Configuration --------------------------------------------------------------------------- -*/ - -/* I/O Ports */ -typedef struct PORT_struct -{ - register8_t DIR; /* I/O Port Data Direction */ - register8_t DIRSET; /* I/O Port Data Direction Set */ - register8_t DIRCLR; /* I/O Port Data Direction Clear */ - register8_t DIRTGL; /* I/O Port Data Direction Toggle */ - register8_t OUT; /* I/O Port Output */ - register8_t OUTSET; /* I/O Port Output Set */ - register8_t OUTCLR; /* I/O Port Output Clear */ - register8_t OUTTGL; /* I/O Port Output Toggle */ - register8_t IN; /* I/O port Input */ - register8_t INTCTRL; /* Interrupt Control Register */ - register8_t INT0MASK; /* Port Interrupt 0 Mask */ - register8_t INT1MASK; /* Port Interrupt 1 Mask */ - register8_t INTFLAGS; /* Interrupt Flag Register */ - register8_t reserved_0x0D; - register8_t reserved_0x0E; - register8_t reserved_0x0F; - register8_t PIN0CTRL; /* Pin 0 Control Register */ - register8_t PIN1CTRL; /* Pin 1 Control Register */ - register8_t PIN2CTRL; /* Pin 2 Control Register */ - register8_t PIN3CTRL; /* Pin 3 Control Register */ - register8_t PIN4CTRL; /* Pin 4 Control Register */ - register8_t PIN5CTRL; /* Pin 5 Control Register */ - register8_t PIN6CTRL; /* Pin 6 Control Register */ - register8_t PIN7CTRL; /* Pin 7 Control Register */ -} PORT_t; - -/* Virtual Port 0 Mapping */ -typedef enum PORTCFG_VP0MAP_enum -{ - PORTCFG_VP0MAP_PORTA_gc = (0x00<<0), /* Mapped To PORTA */ - PORTCFG_VP0MAP_PORTB_gc = (0x01<<0), /* Mapped To PORTB */ - PORTCFG_VP0MAP_PORTC_gc = (0x02<<0), /* Mapped To PORTC */ - PORTCFG_VP0MAP_PORTD_gc = (0x03<<0), /* Mapped To PORTD */ - PORTCFG_VP0MAP_PORTE_gc = (0x04<<0), /* Mapped To PORTE */ - PORTCFG_VP0MAP_PORTF_gc = (0x05<<0), /* Mapped To PORTF */ - PORTCFG_VP0MAP_PORTG_gc = (0x06<<0), /* Mapped To PORTG */ - PORTCFG_VP0MAP_PORTH_gc = (0x07<<0), /* Mapped To PORTH */ - PORTCFG_VP0MAP_PORTJ_gc = (0x08<<0), /* Mapped To PORTJ */ - PORTCFG_VP0MAP_PORTK_gc = (0x09<<0), /* Mapped To PORTK */ - PORTCFG_VP0MAP_PORTL_gc = (0x0A<<0), /* Mapped To PORTL */ - PORTCFG_VP0MAP_PORTM_gc = (0x0B<<0), /* Mapped To PORTM */ - PORTCFG_VP0MAP_PORTN_gc = (0x0C<<0), /* Mapped To PORTN */ - PORTCFG_VP0MAP_PORTP_gc = (0x0D<<0), /* Mapped To PORTP */ - PORTCFG_VP0MAP_PORTQ_gc = (0x0E<<0), /* Mapped To PORTQ */ - PORTCFG_VP0MAP_PORTR_gc = (0x0F<<0), /* Mapped To PORTR */ -} PORTCFG_VP0MAP_t; - -/* Virtual Port 1 Mapping */ -typedef enum PORTCFG_VP1MAP_enum -{ - PORTCFG_VP1MAP_PORTA_gc = (0x00<<4), /* Mapped To PORTA */ - PORTCFG_VP1MAP_PORTB_gc = (0x01<<4), /* Mapped To PORTB */ - PORTCFG_VP1MAP_PORTC_gc = (0x02<<4), /* Mapped To PORTC */ - PORTCFG_VP1MAP_PORTD_gc = (0x03<<4), /* Mapped To PORTD */ - PORTCFG_VP1MAP_PORTE_gc = (0x04<<4), /* Mapped To PORTE */ - PORTCFG_VP1MAP_PORTF_gc = (0x05<<4), /* Mapped To PORTF */ - PORTCFG_VP1MAP_PORTG_gc = (0x06<<4), /* Mapped To PORTG */ - PORTCFG_VP1MAP_PORTH_gc = (0x07<<4), /* Mapped To PORTH */ - PORTCFG_VP1MAP_PORTJ_gc = (0x08<<4), /* Mapped To PORTJ */ - PORTCFG_VP1MAP_PORTK_gc = (0x09<<4), /* Mapped To PORTK */ - PORTCFG_VP1MAP_PORTL_gc = (0x0A<<4), /* Mapped To PORTL */ - PORTCFG_VP1MAP_PORTM_gc = (0x0B<<4), /* Mapped To PORTM */ - PORTCFG_VP1MAP_PORTN_gc = (0x0C<<4), /* Mapped To PORTN */ - PORTCFG_VP1MAP_PORTP_gc = (0x0D<<4), /* Mapped To PORTP */ - PORTCFG_VP1MAP_PORTQ_gc = (0x0E<<4), /* Mapped To PORTQ */ - PORTCFG_VP1MAP_PORTR_gc = (0x0F<<4), /* Mapped To PORTR */ -} PORTCFG_VP1MAP_t; - -/* Virtual Port 2 Mapping */ -typedef enum PORTCFG_VP2MAP_enum -{ - PORTCFG_VP2MAP_PORTA_gc = (0x00<<0), /* Mapped To PORTA */ - PORTCFG_VP2MAP_PORTB_gc = (0x01<<0), /* Mapped To PORTB */ - PORTCFG_VP2MAP_PORTC_gc = (0x02<<0), /* Mapped To PORTC */ - PORTCFG_VP2MAP_PORTD_gc = (0x03<<0), /* Mapped To PORTD */ - PORTCFG_VP2MAP_PORTE_gc = (0x04<<0), /* Mapped To PORTE */ - PORTCFG_VP2MAP_PORTF_gc = (0x05<<0), /* Mapped To PORTF */ - PORTCFG_VP2MAP_PORTG_gc = (0x06<<0), /* Mapped To PORTG */ - PORTCFG_VP2MAP_PORTH_gc = (0x07<<0), /* Mapped To PORTH */ - PORTCFG_VP2MAP_PORTJ_gc = (0x08<<0), /* Mapped To PORTJ */ - PORTCFG_VP2MAP_PORTK_gc = (0x09<<0), /* Mapped To PORTK */ - PORTCFG_VP2MAP_PORTL_gc = (0x0A<<0), /* Mapped To PORTL */ - PORTCFG_VP2MAP_PORTM_gc = (0x0B<<0), /* Mapped To PORTM */ - PORTCFG_VP2MAP_PORTN_gc = (0x0C<<0), /* Mapped To PORTN */ - PORTCFG_VP2MAP_PORTP_gc = (0x0D<<0), /* Mapped To PORTP */ - PORTCFG_VP2MAP_PORTQ_gc = (0x0E<<0), /* Mapped To PORTQ */ - PORTCFG_VP2MAP_PORTR_gc = (0x0F<<0), /* Mapped To PORTR */ -} PORTCFG_VP2MAP_t; - -/* Virtual Port 3 Mapping */ -typedef enum PORTCFG_VP3MAP_enum -{ - PORTCFG_VP3MAP_PORTA_gc = (0x00<<4), /* Mapped To PORTA */ - PORTCFG_VP3MAP_PORTB_gc = (0x01<<4), /* Mapped To PORTB */ - PORTCFG_VP3MAP_PORTC_gc = (0x02<<4), /* Mapped To PORTC */ - PORTCFG_VP3MAP_PORTD_gc = (0x03<<4), /* Mapped To PORTD */ - PORTCFG_VP3MAP_PORTE_gc = (0x04<<4), /* Mapped To PORTE */ - PORTCFG_VP3MAP_PORTF_gc = (0x05<<4), /* Mapped To PORTF */ - PORTCFG_VP3MAP_PORTG_gc = (0x06<<4), /* Mapped To PORTG */ - PORTCFG_VP3MAP_PORTH_gc = (0x07<<4), /* Mapped To PORTH */ - PORTCFG_VP3MAP_PORTJ_gc = (0x08<<4), /* Mapped To PORTJ */ - PORTCFG_VP3MAP_PORTK_gc = (0x09<<4), /* Mapped To PORTK */ - PORTCFG_VP3MAP_PORTL_gc = (0x0A<<4), /* Mapped To PORTL */ - PORTCFG_VP3MAP_PORTM_gc = (0x0B<<4), /* Mapped To PORTM */ - PORTCFG_VP3MAP_PORTN_gc = (0x0C<<4), /* Mapped To PORTN */ - PORTCFG_VP3MAP_PORTP_gc = (0x0D<<4), /* Mapped To PORTP */ - PORTCFG_VP3MAP_PORTQ_gc = (0x0E<<4), /* Mapped To PORTQ */ - PORTCFG_VP3MAP_PORTR_gc = (0x0F<<4), /* Mapped To PORTR */ -} PORTCFG_VP3MAP_t; - -/* Clock Output Port */ -typedef enum PORTCFG_CLKOUT_enum -{ - PORTCFG_CLKOUT_OFF_gc = (0x00<<0), /* Clock Output Disabled */ - PORTCFG_CLKOUT_PC7_gc = (0x01<<0), /* Clock Output on Port C pin 7 */ - PORTCFG_CLKOUT_PD7_gc = (0x02<<0), /* Clock Output on Port D pin 7 */ - PORTCFG_CLKOUT_PE7_gc = (0x03<<0), /* Clock Output on Port E pin 7 */ -} PORTCFG_CLKOUT_t; - -/* Event Output Port */ -typedef enum PORTCFG_EVOUT_enum -{ - PORTCFG_EVOUT_OFF_gc = (0x00<<4), /* Event Output Disabled */ - PORTCFG_EVOUT_PC7_gc = (0x01<<4), /* Event Channel 7 Output on Port C pin 7 */ - PORTCFG_EVOUT_PD7_gc = (0x02<<4), /* Event Channel 7 Output on Port D pin 7 */ - PORTCFG_EVOUT_PE7_gc = (0x03<<4), /* Event Channel 7 Output on Port E pin 7 */ -} PORTCFG_EVOUT_t; - -/* Port Interrupt 0 Level */ -typedef enum PORT_INT0LVL_enum -{ - PORT_INT0LVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - PORT_INT0LVL_LO_gc = (0x01<<0), /* Low Level */ - PORT_INT0LVL_MED_gc = (0x02<<0), /* Medium Level */ - PORT_INT0LVL_HI_gc = (0x03<<0), /* High Level */ -} PORT_INT0LVL_t; - -/* Port Interrupt 1 Level */ -typedef enum PORT_INT1LVL_enum -{ - PORT_INT1LVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ - PORT_INT1LVL_LO_gc = (0x01<<2), /* Low Level */ - PORT_INT1LVL_MED_gc = (0x02<<2), /* Medium Level */ - PORT_INT1LVL_HI_gc = (0x03<<2), /* High Level */ -} PORT_INT1LVL_t; - -/* Output/Pull Configuration */ -typedef enum PORT_OPC_enum -{ - PORT_OPC_TOTEM_gc = (0x00<<3), /* Totempole */ - PORT_OPC_BUSKEEPER_gc = (0x01<<3), /* Totempole w/ Bus keeper on Input and Output */ - PORT_OPC_PULLDOWN_gc = (0x02<<3), /* Totempole w/ Pull-down on Input */ - PORT_OPC_PULLUP_gc = (0x03<<3), /* Totempole w/ Pull-up on Input */ - PORT_OPC_WIREDOR_gc = (0x04<<3), /* Wired OR */ - PORT_OPC_WIREDAND_gc = (0x05<<3), /* Wired AND */ - PORT_OPC_WIREDORPULL_gc = (0x06<<3), /* Wired OR w/ Pull-down */ - PORT_OPC_WIREDANDPULL_gc = (0x07<<3), /* Wired AND w/ Pull-up */ -} PORT_OPC_t; - -/* Input/Sense Configuration */ -typedef enum PORT_ISC_enum -{ - PORT_ISC_BOTHEDGES_gc = (0x00<<0), /* Sense Both Edges */ - PORT_ISC_RISING_gc = (0x01<<0), /* Sense Rising Edge */ - PORT_ISC_FALLING_gc = (0x02<<0), /* Sense Falling Edge */ - PORT_ISC_LEVEL_gc = (0x03<<0), /* Sense Level (Transparent For Events) */ - PORT_ISC_INPUT_DISABLE_gc = (0x07<<0), /* Disable Digital Input Buffer */ -} PORT_ISC_t; - - -/* --------------------------------------------------------------------------- -TC - 16-bit Timer/Counter With PWM --------------------------------------------------------------------------- -*/ - -/* 16-bit Timer/Counter 0 */ -typedef struct TC0_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t CTRLC; /* Control register C */ - register8_t CTRLD; /* Control Register D */ - register8_t CTRLE; /* Control Register E */ - register8_t reserved_0x05; - register8_t INTCTRLA; /* Interrupt Control Register A */ - register8_t INTCTRLB; /* Interrupt Control Register B */ - register8_t CTRLFCLR; /* Control Register F Clear */ - register8_t CTRLFSET; /* Control Register F Set */ - register8_t CTRLGCLR; /* Control Register G Clear */ - register8_t CTRLGSET; /* Control Register G Set */ - register8_t INTFLAGS; /* Interrupt Flag Register */ - register8_t reserved_0x0D; - register8_t reserved_0x0E; - register8_t TEMP; /* Temporary Register For 16-bit Access */ - register8_t reserved_0x10; - register8_t reserved_0x11; - register8_t reserved_0x12; - register8_t reserved_0x13; - register8_t reserved_0x14; - register8_t reserved_0x15; - register8_t reserved_0x16; - register8_t reserved_0x17; - register8_t reserved_0x18; - register8_t reserved_0x19; - register8_t reserved_0x1A; - register8_t reserved_0x1B; - register8_t reserved_0x1C; - register8_t reserved_0x1D; - register8_t reserved_0x1E; - register8_t reserved_0x1F; - _WORDREGISTER(CNT); /* Count */ - register8_t reserved_0x22; - register8_t reserved_0x23; - register8_t reserved_0x24; - register8_t reserved_0x25; - _WORDREGISTER(PER); /* Period */ - _WORDREGISTER(CCA); /* Compare or Capture A */ - _WORDREGISTER(CCB); /* Compare or Capture B */ - _WORDREGISTER(CCC); /* Compare or Capture C */ - _WORDREGISTER(CCD); /* Compare or Capture D */ - register8_t reserved_0x30; - register8_t reserved_0x31; - register8_t reserved_0x32; - register8_t reserved_0x33; - register8_t reserved_0x34; - register8_t reserved_0x35; - _WORDREGISTER(PERBUF); /* Period Buffer */ - _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ - _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ - _WORDREGISTER(CCCBUF); /* Compare Or Capture C Buffer */ - _WORDREGISTER(CCDBUF); /* Compare Or Capture D Buffer */ -} TC0_t; - -/* --------------------------------------------------------------------------- -TC - 16-bit Timer/Counter With PWM --------------------------------------------------------------------------- -*/ - -/* 16-bit Timer/Counter 1 */ -typedef struct TC1_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t CTRLC; /* Control register C */ - register8_t CTRLD; /* Control Register D */ - register8_t CTRLE; /* Control Register E */ - register8_t reserved_0x05; - register8_t INTCTRLA; /* Interrupt Control Register A */ - register8_t INTCTRLB; /* Interrupt Control Register B */ - register8_t CTRLFCLR; /* Control Register F Clear */ - register8_t CTRLFSET; /* Control Register F Set */ - register8_t CTRLGCLR; /* Control Register G Clear */ - register8_t CTRLGSET; /* Control Register G Set */ - register8_t INTFLAGS; /* Interrupt Flag Register */ - register8_t reserved_0x0D; - register8_t reserved_0x0E; - register8_t TEMP; /* Temporary Register For 16-bit Access */ - register8_t reserved_0x10; - register8_t reserved_0x11; - register8_t reserved_0x12; - register8_t reserved_0x13; - register8_t reserved_0x14; - register8_t reserved_0x15; - register8_t reserved_0x16; - register8_t reserved_0x17; - register8_t reserved_0x18; - register8_t reserved_0x19; - register8_t reserved_0x1A; - register8_t reserved_0x1B; - register8_t reserved_0x1C; - register8_t reserved_0x1D; - register8_t reserved_0x1E; - register8_t reserved_0x1F; - _WORDREGISTER(CNT); /* Count */ - register8_t reserved_0x22; - register8_t reserved_0x23; - register8_t reserved_0x24; - register8_t reserved_0x25; - _WORDREGISTER(PER); /* Period */ - _WORDREGISTER(CCA); /* Compare or Capture A */ - _WORDREGISTER(CCB); /* Compare or Capture B */ - register8_t reserved_0x2C; - register8_t reserved_0x2D; - register8_t reserved_0x2E; - register8_t reserved_0x2F; - register8_t reserved_0x30; - register8_t reserved_0x31; - register8_t reserved_0x32; - register8_t reserved_0x33; - register8_t reserved_0x34; - register8_t reserved_0x35; - _WORDREGISTER(PERBUF); /* Period Buffer */ - _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ - _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ -} TC1_t; - -/* --------------------------------------------------------------------------- -TC - 16-bit Timer/Counter With PWM --------------------------------------------------------------------------- -*/ - -/* Advanced Waveform Extension */ -typedef struct AWEX_struct -{ - register8_t CTRL; /* Control Register */ - register8_t reserved_0x01; - register8_t FDEMASK; /* Fault Detection Event Mask */ - register8_t FDCTRL; /* Fault Detection Control Register */ - register8_t STATUS; /* Status Register */ - register8_t reserved_0x05; - register8_t DTBOTH; /* Dead Time Both Sides */ - register8_t DTBOTHBUF; /* Dead Time Both Sides Buffer */ - register8_t DTLS; /* Dead Time Low Side */ - register8_t DTHS; /* Dead Time High Side */ - register8_t DTLSBUF; /* Dead Time Low Side Buffer */ - register8_t DTHSBUF; /* Dead Time High Side Buffer */ - register8_t OUTOVEN; /* Output Override Enable */ -} AWEX_t; - -/* --------------------------------------------------------------------------- -TC - 16-bit Timer/Counter With PWM --------------------------------------------------------------------------- -*/ - -/* High-Resolution Extension */ -typedef struct HIRES_struct -{ - register8_t CTRLA; /* Control Register */ -} HIRES_t; - -/* Clock Selection */ -typedef enum TC_CLKSEL_enum -{ - TC_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */ - TC_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */ - TC_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */ - TC_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */ - TC_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */ - TC_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */ - TC_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */ - TC_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */ - TC_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */ - TC_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */ - TC_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */ - TC_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */ - TC_CLKSEL_EVCH4_gc = (0x0C<<0), /* Event Channel 4 */ - TC_CLKSEL_EVCH5_gc = (0x0D<<0), /* Event Channel 5 */ - TC_CLKSEL_EVCH6_gc = (0x0E<<0), /* Event Channel 6 */ - TC_CLKSEL_EVCH7_gc = (0x0F<<0), /* Event Channel 7 */ -} TC_CLKSEL_t; - -/* Waveform Generation Mode */ -typedef enum TC_WGMODE_enum -{ - TC_WGMODE_NORMAL_gc = (0x00<<0), /* Normal Mode */ - TC_WGMODE_FRQ_gc = (0x01<<0), /* Frequency Generation Mode */ - TC_WGMODE_SS_gc = (0x03<<0), /* Single Slope */ - TC_WGMODE_DS_T_gc = (0x05<<0), /* Dual Slope, Update on TOP */ - TC_WGMODE_DS_TB_gc = (0x06<<0), /* Dual Slope, Update on TOP and BOTTOM */ - TC_WGMODE_DS_B_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */ -} TC_WGMODE_t; - -/* Event Action */ -typedef enum TC_EVACT_enum -{ - TC_EVACT_OFF_gc = (0x00<<5), /* No Event Action */ - TC_EVACT_CAPT_gc = (0x01<<5), /* Input Capture */ - TC_EVACT_UPDOWN_gc = (0x02<<5), /* Externally Controlled Up/Down Count */ - TC_EVACT_QDEC_gc = (0x03<<5), /* Quadrature Decode */ - TC_EVACT_RESTART_gc = (0x04<<5), /* Restart */ - TC_EVACT_FRQ_gc = (0x05<<5), /* Frequency Capture */ - TC_EVACT_FRW_gc = (0x05<<5), /* Frequency Capture (typo in earlier header file) */ - TC_EVACT_PW_gc = (0x06<<5), /* Pulse-width Capture */ -} TC_EVACT_t; - -/* Event Selection */ -typedef enum TC_EVSEL_enum -{ - TC_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ - TC_EVSEL_CH0_gc = (0x08<<0), /* Event Channel 0 */ - TC_EVSEL_CH1_gc = (0x09<<0), /* Event Channel 1 */ - TC_EVSEL_CH2_gc = (0x0A<<0), /* Event Channel 2 */ - TC_EVSEL_CH3_gc = (0x0B<<0), /* Event Channel 3 */ - TC_EVSEL_CH4_gc = (0x0C<<0), /* Event Channel 4 */ - TC_EVSEL_CH5_gc = (0x0D<<0), /* Event Channel 5 */ - TC_EVSEL_CH6_gc = (0x0E<<0), /* Event Channel 6 */ - TC_EVSEL_CH7_gc = (0x0F<<0), /* Event Channel 7 */ -} TC_EVSEL_t; - -/* Error Interrupt Level */ -typedef enum TC_ERRINTLVL_enum -{ - TC_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ - TC_ERRINTLVL_LO_gc = (0x01<<2), /* Low Level */ - TC_ERRINTLVL_MED_gc = (0x02<<2), /* Medium Level */ - TC_ERRINTLVL_HI_gc = (0x03<<2), /* High Level */ -} TC_ERRINTLVL_t; - -/* Overflow Interrupt Level */ -typedef enum TC_OVFINTLVL_enum -{ - TC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - TC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ - TC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ - TC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ -} TC_OVFINTLVL_t; - -/* Compare or Capture D Interrupt Level */ -typedef enum TC_CCDINTLVL_enum -{ - TC_CCDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ - TC_CCDINTLVL_LO_gc = (0x01<<6), /* Low Level */ - TC_CCDINTLVL_MED_gc = (0x02<<6), /* Medium Level */ - TC_CCDINTLVL_HI_gc = (0x03<<6), /* High Level */ -} TC_CCDINTLVL_t; - -/* Compare or Capture C Interrupt Level */ -typedef enum TC_CCCINTLVL_enum -{ - TC_CCCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ - TC_CCCINTLVL_LO_gc = (0x01<<4), /* Low Level */ - TC_CCCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ - TC_CCCINTLVL_HI_gc = (0x03<<4), /* High Level */ -} TC_CCCINTLVL_t; - -/* Compare or Capture B Interrupt Level */ -typedef enum TC_CCBINTLVL_enum -{ - TC_CCBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ - TC_CCBINTLVL_LO_gc = (0x01<<2), /* Low Level */ - TC_CCBINTLVL_MED_gc = (0x02<<2), /* Medium Level */ - TC_CCBINTLVL_HI_gc = (0x03<<2), /* High Level */ -} TC_CCBINTLVL_t; - -/* Compare or Capture A Interrupt Level */ -typedef enum TC_CCAINTLVL_enum -{ - TC_CCAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - TC_CCAINTLVL_LO_gc = (0x01<<0), /* Low Level */ - TC_CCAINTLVL_MED_gc = (0x02<<0), /* Medium Level */ - TC_CCAINTLVL_HI_gc = (0x03<<0), /* High Level */ -} TC_CCAINTLVL_t; - -/* Timer/Counter Command */ -typedef enum TC_CMD_enum -{ - TC_CMD_NONE_gc = (0x00<<2), /* No Command */ - TC_CMD_UPDATE_gc = (0x01<<2), /* Force Update */ - TC_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ - TC_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ -} TC_CMD_t; - -/* Fault Detect Action */ -typedef enum AWEX_FDACT_enum -{ - AWEX_FDACT_NONE_gc = (0x00<<0), /* No Fault Protection */ - AWEX_FDACT_CLEAROE_gc = (0x01<<0), /* Clear Output Enable Bits */ - AWEX_FDACT_CLEARDIR_gc = (0x03<<0), /* Clear I/O Port Direction Bits */ -} AWEX_FDACT_t; - -/* High Resolution Enable */ -typedef enum HIRES_HREN_enum -{ - HIRES_HREN_NONE_gc = (0x00<<0), /* No Fault Protection */ - HIRES_HREN_TC0_gc = (0x01<<0), /* Enable High Resolution on Timer/Counter 0 */ - HIRES_HREN_TC1_gc = (0x02<<0), /* Enable High Resolution on Timer/Counter 1 */ - HIRES_HREN_BOTH_gc = (0x03<<0), /* Enable High Resolution both Timer/Counters */ -} HIRES_HREN_t; - - -/* --------------------------------------------------------------------------- -USART - Universal Asynchronous Receiver-Transmitter --------------------------------------------------------------------------- -*/ - -/* Universal Synchronous/Asynchronous Receiver/Transmitter */ -typedef struct USART_struct -{ - register8_t DATA; /* Data Register */ - register8_t STATUS; /* Status Register */ - register8_t reserved_0x02; - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t CTRLC; /* Control Register C */ - register8_t BAUDCTRLA; /* Baud Rate Control Register A */ - register8_t BAUDCTRLB; /* Baud Rate Control Register B */ -} USART_t; - -/* Receive Complete Interrupt level */ -typedef enum USART_RXCINTLVL_enum -{ - USART_RXCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ - USART_RXCINTLVL_LO_gc = (0x01<<4), /* Low Level */ - USART_RXCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ - USART_RXCINTLVL_HI_gc = (0x03<<4), /* High Level */ -} USART_RXCINTLVL_t; - -/* Transmit Complete Interrupt level */ -typedef enum USART_TXCINTLVL_enum -{ - USART_TXCINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ - USART_TXCINTLVL_LO_gc = (0x01<<2), /* Low Level */ - USART_TXCINTLVL_MED_gc = (0x02<<2), /* Medium Level */ - USART_TXCINTLVL_HI_gc = (0x03<<2), /* High Level */ -} USART_TXCINTLVL_t; - -/* Data Register Empty Interrupt level */ -typedef enum USART_DREINTLVL_enum -{ - USART_DREINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - USART_DREINTLVL_LO_gc = (0x01<<0), /* Low Level */ - USART_DREINTLVL_MED_gc = (0x02<<0), /* Medium Level */ - USART_DREINTLVL_HI_gc = (0x03<<0), /* High Level */ -} USART_DREINTLVL_t; - -/* Character Size */ -typedef enum USART_CHSIZE_enum -{ - USART_CHSIZE_5BIT_gc = (0x00<<0), /* Character size: 5 bit */ - USART_CHSIZE_6BIT_gc = (0x01<<0), /* Character size: 6 bit */ - USART_CHSIZE_7BIT_gc = (0x02<<0), /* Character size: 7 bit */ - USART_CHSIZE_8BIT_gc = (0x03<<0), /* Character size: 8 bit */ - USART_CHSIZE_9BIT_gc = (0x07<<0), /* Character size: 9 bit */ -} USART_CHSIZE_t; - -/* Communication Mode */ -typedef enum USART_CMODE_enum -{ - USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6), /* Asynchronous Mode */ - USART_CMODE_SYNCHRONOUS_gc = (0x01<<6), /* Synchronous Mode */ - USART_CMODE_IRDA_gc = (0x02<<6), /* IrDA Mode */ - USART_CMODE_MSPI_gc = (0x03<<6), /* Master SPI Mode */ -} USART_CMODE_t; - -/* Parity Mode */ -typedef enum USART_PMODE_enum -{ - USART_PMODE_DISABLED_gc = (0x00<<4), /* No Parity */ - USART_PMODE_EVEN_gc = (0x02<<4), /* Even Parity */ - USART_PMODE_ODD_gc = (0x03<<4), /* Odd Parity */ -} USART_PMODE_t; - - -/* --------------------------------------------------------------------------- -SPI - Serial Peripheral Interface --------------------------------------------------------------------------- -*/ - -/* Serial Peripheral Interface */ -typedef struct SPI_struct -{ - register8_t CTRL; /* Control Register */ - register8_t INTCTRL; /* Interrupt Control Register */ - register8_t STATUS; /* Status Register */ - register8_t DATA; /* Data Register */ -} SPI_t; - -/* SPI Mode */ -typedef enum SPI_MODE_enum -{ - SPI_MODE_0_gc = (0x00<<2), /* SPI Mode 0 */ - SPI_MODE_1_gc = (0x01<<2), /* SPI Mode 1 */ - SPI_MODE_2_gc = (0x02<<2), /* SPI Mode 2 */ - SPI_MODE_3_gc = (0x03<<2), /* SPI Mode 3 */ -} SPI_MODE_t; - -/* Prescaler setting */ -typedef enum SPI_PRESCALER_enum -{ - SPI_PRESCALER_DIV4_gc = (0x00<<0), /* System Clock / 4 */ - SPI_PRESCALER_DIV16_gc = (0x01<<0), /* System Clock / 16 */ - SPI_PRESCALER_DIV64_gc = (0x02<<0), /* System Clock / 64 */ - SPI_PRESCALER_DIV128_gc = (0x03<<0), /* System Clock / 128 */ -} SPI_PRESCALER_t; - -/* Interrupt level */ -typedef enum SPI_INTLVL_enum -{ - SPI_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - SPI_INTLVL_LO_gc = (0x01<<0), /* Low Level */ - SPI_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ - SPI_INTLVL_HI_gc = (0x03<<0), /* High Level */ -} SPI_INTLVL_t; - - -/* --------------------------------------------------------------------------- -IRCOM - IR Communication Module --------------------------------------------------------------------------- -*/ - -/* IR Communication Module */ -typedef struct IRCOM_struct -{ - register8_t CTRL; /* Control Register */ - register8_t TXPLCTRL; /* IrDA Transmitter Pulse Length Control Register */ - register8_t RXPLCTRL; /* IrDA Receiver Pulse Length Control Register */ -} IRCOM_t; - -/* Event channel selection */ -typedef enum IRDA_EVSEL_enum -{ - IRDA_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ - IRDA_EVSEL_0_gc = (0x08<<0), /* Event Channel 0 */ - IRDA_EVSEL_1_gc = (0x09<<0), /* Event Channel 1 */ - IRDA_EVSEL_2_gc = (0x0A<<0), /* Event Channel 2 */ - IRDA_EVSEL_3_gc = (0x0B<<0), /* Event Channel 3 */ - IRDA_EVSEL_4_gc = (0x0C<<0), /* Event Channel 4 */ - IRDA_EVSEL_5_gc = (0x0D<<0), /* Event Channel 5 */ - IRDA_EVSEL_6_gc = (0x0E<<0), /* Event Channel 6 */ - IRDA_EVSEL_7_gc = (0x0F<<0), /* Event Channel 7 */ -} IRDA_EVSEL_t; - - -/* --------------------------------------------------------------------------- -AES - AES Module --------------------------------------------------------------------------- -*/ - -/* AES Module */ -typedef struct AES_struct -{ - register8_t CTRL; /* AES Control Register */ - register8_t STATUS; /* AES Status Register */ - register8_t STATE; /* AES State Register */ - register8_t KEY; /* AES Key Register */ - register8_t INTCTRL; /* AES Interrupt Control Register */ -} AES_t; - -/* Interrupt level */ -typedef enum AES_INTLVL_enum -{ - AES_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - AES_INTLVL_LO_gc = (0x01<<0), /* Low Level */ - AES_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ - AES_INTLVL_HI_gc = (0x03<<0), /* High Level */ -} AES_INTLVL_t; - - - -/* -========================================================================== -IO Module Instances. Mapped to memory. -========================================================================== -*/ - -#define VPORT0 (*(VPORT_t *) 0x0010) /* Virtual Port 0 */ -#define VPORT1 (*(VPORT_t *) 0x0014) /* Virtual Port 1 */ -#define VPORT2 (*(VPORT_t *) 0x0018) /* Virtual Port 2 */ -#define VPORT3 (*(VPORT_t *) 0x001C) /* Virtual Port 3 */ -#define OCD (*(OCD_t *) 0x002E) /* On-Chip Debug System */ -#define CLK (*(CLK_t *) 0x0040) /* Clock System */ -#define SLEEP (*(SLEEP_t *) 0x0048) /* Sleep Controller */ -#define OSC (*(OSC_t *) 0x0050) /* Oscillator Control */ -#define DFLLRC32M (*(DFLL_t *) 0x0060) /* DFLL for 32MHz RC Oscillator */ -#define DFLLRC2M (*(DFLL_t *) 0x0068) /* DFLL for 2MHz RC Oscillator */ -#define PR (*(PR_t *) 0x0070) /* Power Reduction */ -#define RST (*(RST_t *) 0x0078) /* Reset Controller */ -#define WDT (*(WDT_t *) 0x0080) /* Watch-Dog Timer */ -#define MCU (*(MCU_t *) 0x0090) /* MCU Control */ -#define PMIC (*(PMIC_t *) 0x00A0) /* Programmable Interrupt Controller */ -#define PORTCFG (*(PORTCFG_t *) 0x00B0) /* Port Configuration */ -#define AES (*(AES_t *) 0x00C0) /* AES Crypto Module */ -#define DMA (*(DMA_t *) 0x0100) /* DMA Controller */ -#define EVSYS (*(EVSYS_t *) 0x0180) /* Event System */ -#define NVM (*(NVM_t *) 0x01C0) /* Non Volatile Memory Controller */ -#define ADCA (*(ADC_t *) 0x0200) /* Analog to Digital Converter A */ -#define ADCB (*(ADC_t *) 0x0240) /* Analog to Digital Converter B */ -#define DACB (*(DAC_t *) 0x0320) /* Digital to Analog Converter B */ -#define ACA (*(AC_t *) 0x0380) /* Analog Comparator A */ -#define ACB (*(AC_t *) 0x0390) /* Analog Comparator B */ -#define RTC (*(RTC_t *) 0x0400) /* Real-Time Counter */ -#define TWIC (*(TWI_t *) 0x0480) /* Two-Wire Interface C */ -#define TWIE (*(TWI_t *) 0x04A0) /* Two-Wire Interface E */ -#define PORTA (*(PORT_t *) 0x0600) /* Port A */ -#define PORTB (*(PORT_t *) 0x0620) /* Port B */ -#define PORTC (*(PORT_t *) 0x0640) /* Port C */ -#define PORTD (*(PORT_t *) 0x0660) /* Port D */ -#define PORTE (*(PORT_t *) 0x0680) /* Port E */ -#define PORTF (*(PORT_t *) 0x06A0) /* Port F */ -#define PORTR (*(PORT_t *) 0x07E0) /* Port R */ -#define TCC0 (*(TC0_t *) 0x0800) /* Timer/Counter C0 */ -#define TCC1 (*(TC1_t *) 0x0840) /* Timer/Counter C1 */ -#define AWEXC (*(AWEX_t *) 0x0880) /* Advanced Waveform Extension C */ -#define HIRESC (*(HIRES_t *) 0x0890) /* High-Resolution Extension C */ -#define USARTC0 (*(USART_t *) 0x08A0) /* Universal Asynchronous Receiver-Transmitter C0 */ -#define USARTC1 (*(USART_t *) 0x08B0) /* Universal Asynchronous Receiver-Transmitter C1 */ -#define SPIC (*(SPI_t *) 0x08C0) /* Serial Peripheral Interface C */ -#define IRCOM (*(IRCOM_t *) 0x08F8) /* IR Communication Module */ -#define TCD0 (*(TC0_t *) 0x0900) /* Timer/Counter D0 */ -#define TCD1 (*(TC1_t *) 0x0940) /* Timer/Counter D1 */ -#define HIRESD (*(HIRES_t *) 0x0990) /* High-Resolution Extension D */ -#define USARTD0 (*(USART_t *) 0x09A0) /* Universal Asynchronous Receiver-Transmitter D0 */ -#define USARTD1 (*(USART_t *) 0x09B0) /* Universal Asynchronous Receiver-Transmitter D1 */ -#define SPID (*(SPI_t *) 0x09C0) /* Serial Peripheral Interface D */ -#define TCE0 (*(TC0_t *) 0x0A00) /* Timer/Counter E0 */ -#define TCE1 (*(TC1_t *) 0x0A40) /* Timer/Counter E1 */ -#define AWEXE (*(AWEX_t *) 0x0A80) /* Advanced Waveform Extension E */ -#define HIRESE (*(HIRES_t *) 0x0A90) /* High-Resolution Extension E */ -#define USARTE0 (*(USART_t *) 0x0AA0) /* Universal Asynchronous Receiver-Transmitter E0 */ -#define USARTE1 (*(USART_t *) 0x0AB0) /* Universal Asynchronous Receiver-Transmitter E1 */ -#define SPIE (*(SPI_t *) 0x0AC0) /* Serial Peripheral Interface E */ -#define TCF0 (*(TC0_t *) 0x0B00) /* Timer/Counter F0 */ -#define HIRESF (*(HIRES_t *) 0x0B90) /* High-Resolution Extension F */ -#define USARTF0 (*(USART_t *) 0x0BA0) /* Universal Asynchronous Receiver-Transmitter F0 */ -#define USARTF1 (*(USART_t *) 0x0BB0) /* Universal Asynchronous Receiver-Transmitter F1 */ -#define SPIF (*(SPI_t *) 0x0BC0) /* Serial Peripheral Interface F */ - - -#endif /* !defined (__ASSEMBLER__) */ - - -/* ========== Flattened fully qualified IO register names ========== */ - -/* GPIO - General Purpose IO Registers */ -#define GPIO_GPIOR0 _SFR_MEM8(0x0000) -#define GPIO_GPIOR1 _SFR_MEM8(0x0001) -#define GPIO_GPIOR2 _SFR_MEM8(0x0002) -#define GPIO_GPIOR3 _SFR_MEM8(0x0003) -#define GPIO_GPIOR4 _SFR_MEM8(0x0004) -#define GPIO_GPIOR5 _SFR_MEM8(0x0005) -#define GPIO_GPIOR6 _SFR_MEM8(0x0006) -#define GPIO_GPIOR7 _SFR_MEM8(0x0007) -#define GPIO_GPIOR8 _SFR_MEM8(0x0008) -#define GPIO_GPIOR9 _SFR_MEM8(0x0009) -#define GPIO_GPIORA _SFR_MEM8(0x000A) -#define GPIO_GPIORB _SFR_MEM8(0x000B) -#define GPIO_GPIORC _SFR_MEM8(0x000C) -#define GPIO_GPIORD _SFR_MEM8(0x000D) -#define GPIO_GPIORE _SFR_MEM8(0x000E) -#define GPIO_GPIORF _SFR_MEM8(0x000F) - -/* Deprecated */ -#define GPIO_GPIO0 _SFR_MEM8(0x0000) -#define GPIO_GPIO1 _SFR_MEM8(0x0001) -#define GPIO_GPIO2 _SFR_MEM8(0x0002) -#define GPIO_GPIO3 _SFR_MEM8(0x0003) -#define GPIO_GPIO4 _SFR_MEM8(0x0004) -#define GPIO_GPIO5 _SFR_MEM8(0x0005) -#define GPIO_GPIO6 _SFR_MEM8(0x0006) -#define GPIO_GPIO7 _SFR_MEM8(0x0007) -#define GPIO_GPIO8 _SFR_MEM8(0x0008) -#define GPIO_GPIO9 _SFR_MEM8(0x0009) -#define GPIO_GPIOA _SFR_MEM8(0x000A) -#define GPIO_GPIOB _SFR_MEM8(0x000B) -#define GPIO_GPIOC _SFR_MEM8(0x000C) -#define GPIO_GPIOD _SFR_MEM8(0x000D) -#define GPIO_GPIOE _SFR_MEM8(0x000E) -#define GPIO_GPIOF _SFR_MEM8(0x000F) - -/* VPORT0 - Virtual Port 0 */ -#define VPORT0_DIR _SFR_MEM8(0x0010) -#define VPORT0_OUT _SFR_MEM8(0x0011) -#define VPORT0_IN _SFR_MEM8(0x0012) -#define VPORT0_INTFLAGS _SFR_MEM8(0x0013) - -/* VPORT1 - Virtual Port 1 */ -#define VPORT1_DIR _SFR_MEM8(0x0014) -#define VPORT1_OUT _SFR_MEM8(0x0015) -#define VPORT1_IN _SFR_MEM8(0x0016) -#define VPORT1_INTFLAGS _SFR_MEM8(0x0017) - -/* VPORT2 - Virtual Port 2 */ -#define VPORT2_DIR _SFR_MEM8(0x0018) -#define VPORT2_OUT _SFR_MEM8(0x0019) -#define VPORT2_IN _SFR_MEM8(0x001A) -#define VPORT2_INTFLAGS _SFR_MEM8(0x001B) - -/* VPORT3 - Virtual Port 3 */ -#define VPORT3_DIR _SFR_MEM8(0x001C) -#define VPORT3_OUT _SFR_MEM8(0x001D) -#define VPORT3_IN _SFR_MEM8(0x001E) -#define VPORT3_INTFLAGS _SFR_MEM8(0x001F) - -/* OCD - On-Chip Debug System */ -#define OCD_OCDR0 _SFR_MEM8(0x002E) -#define OCD_OCDR1 _SFR_MEM8(0x002F) - -/* CPU - CPU Registers */ -#define CPU_CCP _SFR_MEM8(0x0034) -#define CPU_RAMPD _SFR_MEM8(0x0038) -#define CPU_RAMPX _SFR_MEM8(0x0039) -#define CPU_RAMPY _SFR_MEM8(0x003A) -#define CPU_RAMPZ _SFR_MEM8(0x003B) -#define CPU_EIND _SFR_MEM8(0x003C) -#define CPU_SPL _SFR_MEM8(0x003D) -#define CPU_SPH _SFR_MEM8(0x003E) -#define CPU_SREG _SFR_MEM8(0x003F) - -/* CLK - Clock System */ -#define CLK_CTRL _SFR_MEM8(0x0040) -#define CLK_PSCTRL _SFR_MEM8(0x0041) -#define CLK_LOCK _SFR_MEM8(0x0042) -#define CLK_RTCCTRL _SFR_MEM8(0x0043) - -/* SLEEP - Sleep Controller */ -#define SLEEP_CTRL _SFR_MEM8(0x0048) - -/* OSC - Oscillator Control */ -#define OSC_CTRL _SFR_MEM8(0x0050) -#define OSC_STATUS _SFR_MEM8(0x0051) -#define OSC_XOSCCTRL _SFR_MEM8(0x0052) -#define OSC_XOSCFAIL _SFR_MEM8(0x0053) -#define OSC_RC32KCAL _SFR_MEM8(0x0054) -#define OSC_PLLCTRL _SFR_MEM8(0x0055) -#define OSC_DFLLCTRL _SFR_MEM8(0x0056) - -/* DFLLRC32M - DFLL for 32MHz RC Oscillator */ -#define DFLLRC32M_CTRL _SFR_MEM8(0x0060) -#define DFLLRC32M_CALA _SFR_MEM8(0x0062) -#define DFLLRC32M_CALB _SFR_MEM8(0x0063) -#define DFLLRC32M_COMP0 _SFR_MEM8(0x0064) -#define DFLLRC32M_COMP1 _SFR_MEM8(0x0065) -#define DFLLRC32M_COMP2 _SFR_MEM8(0x0066) - -/* DFLLRC2M - DFLL for 2MHz RC Oscillator */ -#define DFLLRC2M_CTRL _SFR_MEM8(0x0068) -#define DFLLRC2M_CALA _SFR_MEM8(0x006A) -#define DFLLRC2M_CALB _SFR_MEM8(0x006B) -#define DFLLRC2M_COMP0 _SFR_MEM8(0x006C) -#define DFLLRC2M_COMP1 _SFR_MEM8(0x006D) -#define DFLLRC2M_COMP2 _SFR_MEM8(0x006E) - -/* PR - Power Reduction */ -#define PR_PRGEN _SFR_MEM8(0x0070) -#define PR_PRPA _SFR_MEM8(0x0071) -#define PR_PRPB _SFR_MEM8(0x0072) -#define PR_PRPC _SFR_MEM8(0x0073) -#define PR_PRPD _SFR_MEM8(0x0074) -#define PR_PRPE _SFR_MEM8(0x0075) -#define PR_PRPF _SFR_MEM8(0x0076) - -/* RST - Reset Controller */ -#define RST_STATUS _SFR_MEM8(0x0078) -#define RST_CTRL _SFR_MEM8(0x0079) - -/* WDT - Watch-Dog Timer */ -#define WDT_CTRL _SFR_MEM8(0x0080) -#define WDT_WINCTRL _SFR_MEM8(0x0081) -#define WDT_STATUS _SFR_MEM8(0x0082) - -/* MCU - MCU Control */ -#define MCU_DEVID0 _SFR_MEM8(0x0090) -#define MCU_DEVID1 _SFR_MEM8(0x0091) -#define MCU_DEVID2 _SFR_MEM8(0x0092) -#define MCU_REVID _SFR_MEM8(0x0093) -#define MCU_JTAGUID _SFR_MEM8(0x0094) -#define MCU_MCUCR _SFR_MEM8(0x0096) -#define MCU_EVSYSLOCK _SFR_MEM8(0x0098) -#define MCU_AWEXLOCK _SFR_MEM8(0x0099) - -/* PMIC - Programmable Interrupt Controller */ -#define PMIC_STATUS _SFR_MEM8(0x00A0) -#define PMIC_INTPRI _SFR_MEM8(0x00A1) -#define PMIC_CTRL _SFR_MEM8(0x00A2) - -/* PORTCFG - Port Configuration */ -#define PORTCFG_MPCMASK _SFR_MEM8(0x00B0) -#define PORTCFG_VPCTRLA _SFR_MEM8(0x00B2) -#define PORTCFG_VPCTRLB _SFR_MEM8(0x00B3) -#define PORTCFG_CLKEVOUT _SFR_MEM8(0x00B4) - -/* AES - AES Crypto Module */ -#define AES_CTRL _SFR_MEM8(0x00C0) -#define AES_STATUS _SFR_MEM8(0x00C1) -#define AES_STATE _SFR_MEM8(0x00C2) -#define AES_KEY _SFR_MEM8(0x00C3) -#define AES_INTCTRL _SFR_MEM8(0x00C4) - -/* DMA - DMA Controller */ -#define DMA_CTRL _SFR_MEM8(0x0100) -#define DMA_INTFLAGS _SFR_MEM8(0x0103) -#define DMA_STATUS _SFR_MEM8(0x0104) -#define DMA_TEMP _SFR_MEM16(0x0106) -#define DMA_CH0_CTRLA _SFR_MEM8(0x0110) -#define DMA_CH0_CTRLB _SFR_MEM8(0x0111) -#define DMA_CH0_ADDRCTRL _SFR_MEM8(0x0112) -#define DMA_CH0_TRIGSRC _SFR_MEM8(0x0113) -#define DMA_CH0_TRFCNT _SFR_MEM16(0x0114) -#define DMA_CH0_REPCNT _SFR_MEM8(0x0116) -#define DMA_CH0_SRCADDR0 _SFR_MEM8(0x0118) -#define DMA_CH0_SRCADDR1 _SFR_MEM8(0x0119) -#define DMA_CH0_SRCADDR2 _SFR_MEM8(0x011A) -#define DMA_CH0_DESTADDR0 _SFR_MEM8(0x011C) -#define DMA_CH0_DESTADDR1 _SFR_MEM8(0x011D) -#define DMA_CH0_DESTADDR2 _SFR_MEM8(0x011E) -#define DMA_CH1_CTRLA _SFR_MEM8(0x0120) -#define DMA_CH1_CTRLB _SFR_MEM8(0x0121) -#define DMA_CH1_ADDRCTRL _SFR_MEM8(0x0122) -#define DMA_CH1_TRIGSRC _SFR_MEM8(0x0123) -#define DMA_CH1_TRFCNT _SFR_MEM16(0x0124) -#define DMA_CH1_REPCNT _SFR_MEM8(0x0126) -#define DMA_CH1_SRCADDR0 _SFR_MEM8(0x0128) -#define DMA_CH1_SRCADDR1 _SFR_MEM8(0x0129) -#define DMA_CH1_SRCADDR2 _SFR_MEM8(0x012A) -#define DMA_CH1_DESTADDR0 _SFR_MEM8(0x012C) -#define DMA_CH1_DESTADDR1 _SFR_MEM8(0x012D) -#define DMA_CH1_DESTADDR2 _SFR_MEM8(0x012E) -#define DMA_CH2_CTRLA _SFR_MEM8(0x0130) -#define DMA_CH2_CTRLB _SFR_MEM8(0x0131) -#define DMA_CH2_ADDRCTRL _SFR_MEM8(0x0132) -#define DMA_CH2_TRIGSRC _SFR_MEM8(0x0133) -#define DMA_CH2_TRFCNT _SFR_MEM16(0x0134) -#define DMA_CH2_REPCNT _SFR_MEM8(0x0136) -#define DMA_CH2_SRCADDR0 _SFR_MEM8(0x0138) -#define DMA_CH2_SRCADDR1 _SFR_MEM8(0x0139) -#define DMA_CH2_SRCADDR2 _SFR_MEM8(0x013A) -#define DMA_CH2_DESTADDR0 _SFR_MEM8(0x013C) -#define DMA_CH2_DESTADDR1 _SFR_MEM8(0x013D) -#define DMA_CH2_DESTADDR2 _SFR_MEM8(0x013E) -#define DMA_CH3_CTRLA _SFR_MEM8(0x0140) -#define DMA_CH3_CTRLB _SFR_MEM8(0x0141) -#define DMA_CH3_ADDRCTRL _SFR_MEM8(0x0142) -#define DMA_CH3_TRIGSRC _SFR_MEM8(0x0143) -#define DMA_CH3_TRFCNT _SFR_MEM16(0x0144) -#define DMA_CH3_REPCNT _SFR_MEM8(0x0146) -#define DMA_CH3_SRCADDR0 _SFR_MEM8(0x0148) -#define DMA_CH3_SRCADDR1 _SFR_MEM8(0x0149) -#define DMA_CH3_SRCADDR2 _SFR_MEM8(0x014A) -#define DMA_CH3_DESTADDR0 _SFR_MEM8(0x014C) -#define DMA_CH3_DESTADDR1 _SFR_MEM8(0x014D) -#define DMA_CH3_DESTADDR2 _SFR_MEM8(0x014E) - -/* EVSYS - Event System */ -#define EVSYS_CH0MUX _SFR_MEM8(0x0180) -#define EVSYS_CH1MUX _SFR_MEM8(0x0181) -#define EVSYS_CH2MUX _SFR_MEM8(0x0182) -#define EVSYS_CH3MUX _SFR_MEM8(0x0183) -#define EVSYS_CH4MUX _SFR_MEM8(0x0184) -#define EVSYS_CH5MUX _SFR_MEM8(0x0185) -#define EVSYS_CH6MUX _SFR_MEM8(0x0186) -#define EVSYS_CH7MUX _SFR_MEM8(0x0187) -#define EVSYS_CH0CTRL _SFR_MEM8(0x0188) -#define EVSYS_CH1CTRL _SFR_MEM8(0x0189) -#define EVSYS_CH2CTRL _SFR_MEM8(0x018A) -#define EVSYS_CH3CTRL _SFR_MEM8(0x018B) -#define EVSYS_CH4CTRL _SFR_MEM8(0x018C) -#define EVSYS_CH5CTRL _SFR_MEM8(0x018D) -#define EVSYS_CH6CTRL _SFR_MEM8(0x018E) -#define EVSYS_CH7CTRL _SFR_MEM8(0x018F) -#define EVSYS_STROBE _SFR_MEM8(0x0190) -#define EVSYS_DATA _SFR_MEM8(0x0191) - -/* NVM - Non Volatile Memory Controller */ -#define NVM_ADDR0 _SFR_MEM8(0x01C0) -#define NVM_ADDR1 _SFR_MEM8(0x01C1) -#define NVM_ADDR2 _SFR_MEM8(0x01C2) -#define NVM_DATA0 _SFR_MEM8(0x01C4) -#define NVM_DATA1 _SFR_MEM8(0x01C5) -#define NVM_DATA2 _SFR_MEM8(0x01C6) -#define NVM_CMD _SFR_MEM8(0x01CA) -#define NVM_CTRLA _SFR_MEM8(0x01CB) -#define NVM_CTRLB _SFR_MEM8(0x01CC) -#define NVM_INTCTRL _SFR_MEM8(0x01CD) -#define NVM_STATUS _SFR_MEM8(0x01CF) -#define NVM_LOCKBITS _SFR_MEM8(0x01D0) - -/* ADCA - Analog to Digital Converter A */ -#define ADCA_CTRLA _SFR_MEM8(0x0200) -#define ADCA_CTRLB _SFR_MEM8(0x0201) -#define ADCA_REFCTRL _SFR_MEM8(0x0202) -#define ADCA_EVCTRL _SFR_MEM8(0x0203) -#define ADCA_PRESCALER _SFR_MEM8(0x0204) -#define ADCA_INTFLAGS _SFR_MEM8(0x0206) -#define ADCA_CAL _SFR_MEM16(0x020C) -#define ADCA_CH0RES _SFR_MEM16(0x0210) -#define ADCA_CH1RES _SFR_MEM16(0x0212) -#define ADCA_CH2RES _SFR_MEM16(0x0214) -#define ADCA_CH3RES _SFR_MEM16(0x0216) -#define ADCA_CMP _SFR_MEM16(0x0218) -#define ADCA_CH0_CTRL _SFR_MEM8(0x0220) -#define ADCA_CH0_MUXCTRL _SFR_MEM8(0x0221) -#define ADCA_CH0_INTCTRL _SFR_MEM8(0x0222) -#define ADCA_CH0_INTFLAGS _SFR_MEM8(0x0223) -#define ADCA_CH0_RES _SFR_MEM16(0x0224) -#define ADCA_CH1_CTRL _SFR_MEM8(0x0228) -#define ADCA_CH1_MUXCTRL _SFR_MEM8(0x0229) -#define ADCA_CH1_INTCTRL _SFR_MEM8(0x022A) -#define ADCA_CH1_INTFLAGS _SFR_MEM8(0x022B) -#define ADCA_CH1_RES _SFR_MEM16(0x022C) -#define ADCA_CH2_CTRL _SFR_MEM8(0x0230) -#define ADCA_CH2_MUXCTRL _SFR_MEM8(0x0231) -#define ADCA_CH2_INTCTRL _SFR_MEM8(0x0232) -#define ADCA_CH2_INTFLAGS _SFR_MEM8(0x0233) -#define ADCA_CH2_RES _SFR_MEM16(0x0234) -#define ADCA_CH3_CTRL _SFR_MEM8(0x0238) -#define ADCA_CH3_MUXCTRL _SFR_MEM8(0x0239) -#define ADCA_CH3_INTCTRL _SFR_MEM8(0x023A) -#define ADCA_CH3_INTFLAGS _SFR_MEM8(0x023B) -#define ADCA_CH3_RES _SFR_MEM16(0x023C) - -/* ADCB - Analog to Digital Converter B */ -#define ADCB_CTRLA _SFR_MEM8(0x0240) -#define ADCB_CTRLB _SFR_MEM8(0x0241) -#define ADCB_REFCTRL _SFR_MEM8(0x0242) -#define ADCB_EVCTRL _SFR_MEM8(0x0243) -#define ADCB_PRESCALER _SFR_MEM8(0x0244) -#define ADCB_INTFLAGS _SFR_MEM8(0x0246) -#define ADCB_CAL _SFR_MEM16(0x024C) -#define ADCB_CH0RES _SFR_MEM16(0x0250) -#define ADCB_CH1RES _SFR_MEM16(0x0252) -#define ADCB_CH2RES _SFR_MEM16(0x0254) -#define ADCB_CH3RES _SFR_MEM16(0x0256) -#define ADCB_CMP _SFR_MEM16(0x0258) -#define ADCB_CH0_CTRL _SFR_MEM8(0x0260) -#define ADCB_CH0_MUXCTRL _SFR_MEM8(0x0261) -#define ADCB_CH0_INTCTRL _SFR_MEM8(0x0262) -#define ADCB_CH0_INTFLAGS _SFR_MEM8(0x0263) -#define ADCB_CH0_RES _SFR_MEM16(0x0264) -#define ADCB_CH1_CTRL _SFR_MEM8(0x0268) -#define ADCB_CH1_MUXCTRL _SFR_MEM8(0x0269) -#define ADCB_CH1_INTCTRL _SFR_MEM8(0x026A) -#define ADCB_CH1_INTFLAGS _SFR_MEM8(0x026B) -#define ADCB_CH1_RES _SFR_MEM16(0x026C) -#define ADCB_CH2_CTRL _SFR_MEM8(0x0270) -#define ADCB_CH2_MUXCTRL _SFR_MEM8(0x0271) -#define ADCB_CH2_INTCTRL _SFR_MEM8(0x0272) -#define ADCB_CH2_INTFLAGS _SFR_MEM8(0x0273) -#define ADCB_CH2_RES _SFR_MEM16(0x0274) -#define ADCB_CH3_CTRL _SFR_MEM8(0x0278) -#define ADCB_CH3_MUXCTRL _SFR_MEM8(0x0279) -#define ADCB_CH3_INTCTRL _SFR_MEM8(0x027A) -#define ADCB_CH3_INTFLAGS _SFR_MEM8(0x027B) -#define ADCB_CH3_RES _SFR_MEM16(0x027C) - -/* DACB - Digital to Analog Converter B */ -#define DACB_CTRLA _SFR_MEM8(0x0320) -#define DACB_CTRLB _SFR_MEM8(0x0321) -#define DACB_CTRLC _SFR_MEM8(0x0322) -#define DACB_EVCTRL _SFR_MEM8(0x0323) -#define DACB_TIMCTRL _SFR_MEM8(0x0324) -#define DACB_STATUS _SFR_MEM8(0x0325) -#define DACB_GAINCAL _SFR_MEM8(0x0328) -#define DACB_OFFSETCAL _SFR_MEM8(0x0329) -#define DACB_CH0DATA _SFR_MEM16(0x0338) -#define DACB_CH1DATA _SFR_MEM16(0x033A) - -/* ACA - Analog Comparator A */ -#define ACA_AC0CTRL _SFR_MEM8(0x0380) -#define ACA_AC1CTRL _SFR_MEM8(0x0381) -#define ACA_AC0MUXCTRL _SFR_MEM8(0x0382) -#define ACA_AC1MUXCTRL _SFR_MEM8(0x0383) -#define ACA_CTRLA _SFR_MEM8(0x0384) -#define ACA_CTRLB _SFR_MEM8(0x0385) -#define ACA_WINCTRL _SFR_MEM8(0x0386) -#define ACA_STATUS _SFR_MEM8(0x0387) - -/* ACB - Analog Comparator B */ -#define ACB_AC0CTRL _SFR_MEM8(0x0390) -#define ACB_AC1CTRL _SFR_MEM8(0x0391) -#define ACB_AC0MUXCTRL _SFR_MEM8(0x0392) -#define ACB_AC1MUXCTRL _SFR_MEM8(0x0393) -#define ACB_CTRLA _SFR_MEM8(0x0394) -#define ACB_CTRLB _SFR_MEM8(0x0395) -#define ACB_WINCTRL _SFR_MEM8(0x0396) -#define ACB_STATUS _SFR_MEM8(0x0397) - -/* RTC - Real-Time Counter */ -#define RTC_CTRL _SFR_MEM8(0x0400) -#define RTC_STATUS _SFR_MEM8(0x0401) -#define RTC_INTCTRL _SFR_MEM8(0x0402) -#define RTC_INTFLAGS _SFR_MEM8(0x0403) -#define RTC_TEMP _SFR_MEM8(0x0404) -#define RTC_CNT _SFR_MEM16(0x0408) -#define RTC_PER _SFR_MEM16(0x040A) -#define RTC_COMP _SFR_MEM16(0x040C) - -/* TWIC - Two-Wire Interface C */ -#define TWIC_CTRL _SFR_MEM8(0x0480) -#define TWIC_MASTER_CTRLA _SFR_MEM8(0x0481) -#define TWIC_MASTER_CTRLB _SFR_MEM8(0x0482) -#define TWIC_MASTER_CTRLC _SFR_MEM8(0x0483) -#define TWIC_MASTER_STATUS _SFR_MEM8(0x0484) -#define TWIC_MASTER_BAUD _SFR_MEM8(0x0485) -#define TWIC_MASTER_ADDR _SFR_MEM8(0x0486) -#define TWIC_MASTER_DATA _SFR_MEM8(0x0487) -#define TWIC_SLAVE_CTRLA _SFR_MEM8(0x0488) -#define TWIC_SLAVE_CTRLB _SFR_MEM8(0x0489) -#define TWIC_SLAVE_STATUS _SFR_MEM8(0x048A) -#define TWIC_SLAVE_ADDR _SFR_MEM8(0x048B) -#define TWIC_SLAVE_DATA _SFR_MEM8(0x048C) -#define TWIC_SLAVE_ADDRMASK _SFR_MEM8(0x048D) - -/* TWIE - Two-Wire Interface E */ -#define TWIE_CTRL _SFR_MEM8(0x04A0) -#define TWIE_MASTER_CTRLA _SFR_MEM8(0x04A1) -#define TWIE_MASTER_CTRLB _SFR_MEM8(0x04A2) -#define TWIE_MASTER_CTRLC _SFR_MEM8(0x04A3) -#define TWIE_MASTER_STATUS _SFR_MEM8(0x04A4) -#define TWIE_MASTER_BAUD _SFR_MEM8(0x04A5) -#define TWIE_MASTER_ADDR _SFR_MEM8(0x04A6) -#define TWIE_MASTER_DATA _SFR_MEM8(0x04A7) -#define TWIE_SLAVE_CTRLA _SFR_MEM8(0x04A8) -#define TWIE_SLAVE_CTRLB _SFR_MEM8(0x04A9) -#define TWIE_SLAVE_STATUS _SFR_MEM8(0x04AA) -#define TWIE_SLAVE_ADDR _SFR_MEM8(0x04AB) -#define TWIE_SLAVE_DATA _SFR_MEM8(0x04AC) -#define TWIE_SLAVE_ADDRMASK _SFR_MEM8(0x04AD) - -/* PORTA - Port A */ -#define PORTA_DIR _SFR_MEM8(0x0600) -#define PORTA_DIRSET _SFR_MEM8(0x0601) -#define PORTA_DIRCLR _SFR_MEM8(0x0602) -#define PORTA_DIRTGL _SFR_MEM8(0x0603) -#define PORTA_OUT _SFR_MEM8(0x0604) -#define PORTA_OUTSET _SFR_MEM8(0x0605) -#define PORTA_OUTCLR _SFR_MEM8(0x0606) -#define PORTA_OUTTGL _SFR_MEM8(0x0607) -#define PORTA_IN _SFR_MEM8(0x0608) -#define PORTA_INTCTRL _SFR_MEM8(0x0609) -#define PORTA_INT0MASK _SFR_MEM8(0x060A) -#define PORTA_INT1MASK _SFR_MEM8(0x060B) -#define PORTA_INTFLAGS _SFR_MEM8(0x060C) -#define PORTA_PIN0CTRL _SFR_MEM8(0x0610) -#define PORTA_PIN1CTRL _SFR_MEM8(0x0611) -#define PORTA_PIN2CTRL _SFR_MEM8(0x0612) -#define PORTA_PIN3CTRL _SFR_MEM8(0x0613) -#define PORTA_PIN4CTRL _SFR_MEM8(0x0614) -#define PORTA_PIN5CTRL _SFR_MEM8(0x0615) -#define PORTA_PIN6CTRL _SFR_MEM8(0x0616) -#define PORTA_PIN7CTRL _SFR_MEM8(0x0617) - -/* PORTB - Port B */ -#define PORTB_DIR _SFR_MEM8(0x0620) -#define PORTB_DIRSET _SFR_MEM8(0x0621) -#define PORTB_DIRCLR _SFR_MEM8(0x0622) -#define PORTB_DIRTGL _SFR_MEM8(0x0623) -#define PORTB_OUT _SFR_MEM8(0x0624) -#define PORTB_OUTSET _SFR_MEM8(0x0625) -#define PORTB_OUTCLR _SFR_MEM8(0x0626) -#define PORTB_OUTTGL _SFR_MEM8(0x0627) -#define PORTB_IN _SFR_MEM8(0x0628) -#define PORTB_INTCTRL _SFR_MEM8(0x0629) -#define PORTB_INT0MASK _SFR_MEM8(0x062A) -#define PORTB_INT1MASK _SFR_MEM8(0x062B) -#define PORTB_INTFLAGS _SFR_MEM8(0x062C) -#define PORTB_PIN0CTRL _SFR_MEM8(0x0630) -#define PORTB_PIN1CTRL _SFR_MEM8(0x0631) -#define PORTB_PIN2CTRL _SFR_MEM8(0x0632) -#define PORTB_PIN3CTRL _SFR_MEM8(0x0633) -#define PORTB_PIN4CTRL _SFR_MEM8(0x0634) -#define PORTB_PIN5CTRL _SFR_MEM8(0x0635) -#define PORTB_PIN6CTRL _SFR_MEM8(0x0636) -#define PORTB_PIN7CTRL _SFR_MEM8(0x0637) - -/* PORTC - Port C */ -#define PORTC_DIR _SFR_MEM8(0x0640) -#define PORTC_DIRSET _SFR_MEM8(0x0641) -#define PORTC_DIRCLR _SFR_MEM8(0x0642) -#define PORTC_DIRTGL _SFR_MEM8(0x0643) -#define PORTC_OUT _SFR_MEM8(0x0644) -#define PORTC_OUTSET _SFR_MEM8(0x0645) -#define PORTC_OUTCLR _SFR_MEM8(0x0646) -#define PORTC_OUTTGL _SFR_MEM8(0x0647) -#define PORTC_IN _SFR_MEM8(0x0648) -#define PORTC_INTCTRL _SFR_MEM8(0x0649) -#define PORTC_INT0MASK _SFR_MEM8(0x064A) -#define PORTC_INT1MASK _SFR_MEM8(0x064B) -#define PORTC_INTFLAGS _SFR_MEM8(0x064C) -#define PORTC_PIN0CTRL _SFR_MEM8(0x0650) -#define PORTC_PIN1CTRL _SFR_MEM8(0x0651) -#define PORTC_PIN2CTRL _SFR_MEM8(0x0652) -#define PORTC_PIN3CTRL _SFR_MEM8(0x0653) -#define PORTC_PIN4CTRL _SFR_MEM8(0x0654) -#define PORTC_PIN5CTRL _SFR_MEM8(0x0655) -#define PORTC_PIN6CTRL _SFR_MEM8(0x0656) -#define PORTC_PIN7CTRL _SFR_MEM8(0x0657) - -/* PORTD - Port D */ -#define PORTD_DIR _SFR_MEM8(0x0660) -#define PORTD_DIRSET _SFR_MEM8(0x0661) -#define PORTD_DIRCLR _SFR_MEM8(0x0662) -#define PORTD_DIRTGL _SFR_MEM8(0x0663) -#define PORTD_OUT _SFR_MEM8(0x0664) -#define PORTD_OUTSET _SFR_MEM8(0x0665) -#define PORTD_OUTCLR _SFR_MEM8(0x0666) -#define PORTD_OUTTGL _SFR_MEM8(0x0667) -#define PORTD_IN _SFR_MEM8(0x0668) -#define PORTD_INTCTRL _SFR_MEM8(0x0669) -#define PORTD_INT0MASK _SFR_MEM8(0x066A) -#define PORTD_INT1MASK _SFR_MEM8(0x066B) -#define PORTD_INTFLAGS _SFR_MEM8(0x066C) -#define PORTD_PIN0CTRL _SFR_MEM8(0x0670) -#define PORTD_PIN1CTRL _SFR_MEM8(0x0671) -#define PORTD_PIN2CTRL _SFR_MEM8(0x0672) -#define PORTD_PIN3CTRL _SFR_MEM8(0x0673) -#define PORTD_PIN4CTRL _SFR_MEM8(0x0674) -#define PORTD_PIN5CTRL _SFR_MEM8(0x0675) -#define PORTD_PIN6CTRL _SFR_MEM8(0x0676) -#define PORTD_PIN7CTRL _SFR_MEM8(0x0677) - -/* PORTE - Port E */ -#define PORTE_DIR _SFR_MEM8(0x0680) -#define PORTE_DIRSET _SFR_MEM8(0x0681) -#define PORTE_DIRCLR _SFR_MEM8(0x0682) -#define PORTE_DIRTGL _SFR_MEM8(0x0683) -#define PORTE_OUT _SFR_MEM8(0x0684) -#define PORTE_OUTSET _SFR_MEM8(0x0685) -#define PORTE_OUTCLR _SFR_MEM8(0x0686) -#define PORTE_OUTTGL _SFR_MEM8(0x0687) -#define PORTE_IN _SFR_MEM8(0x0688) -#define PORTE_INTCTRL _SFR_MEM8(0x0689) -#define PORTE_INT0MASK _SFR_MEM8(0x068A) -#define PORTE_INT1MASK _SFR_MEM8(0x068B) -#define PORTE_INTFLAGS _SFR_MEM8(0x068C) -#define PORTE_PIN0CTRL _SFR_MEM8(0x0690) -#define PORTE_PIN1CTRL _SFR_MEM8(0x0691) -#define PORTE_PIN2CTRL _SFR_MEM8(0x0692) -#define PORTE_PIN3CTRL _SFR_MEM8(0x0693) -#define PORTE_PIN4CTRL _SFR_MEM8(0x0694) -#define PORTE_PIN5CTRL _SFR_MEM8(0x0695) -#define PORTE_PIN6CTRL _SFR_MEM8(0x0696) -#define PORTE_PIN7CTRL _SFR_MEM8(0x0697) - -/* PORTF - Port F */ -#define PORTF_DIR _SFR_MEM8(0x06A0) -#define PORTF_DIRSET _SFR_MEM8(0x06A1) -#define PORTF_DIRCLR _SFR_MEM8(0x06A2) -#define PORTF_DIRTGL _SFR_MEM8(0x06A3) -#define PORTF_OUT _SFR_MEM8(0x06A4) -#define PORTF_OUTSET _SFR_MEM8(0x06A5) -#define PORTF_OUTCLR _SFR_MEM8(0x06A6) -#define PORTF_OUTTGL _SFR_MEM8(0x06A7) -#define PORTF_IN _SFR_MEM8(0x06A8) -#define PORTF_INTCTRL _SFR_MEM8(0x06A9) -#define PORTF_INT0MASK _SFR_MEM8(0x06AA) -#define PORTF_INT1MASK _SFR_MEM8(0x06AB) -#define PORTF_INTFLAGS _SFR_MEM8(0x06AC) -#define PORTF_PIN0CTRL _SFR_MEM8(0x06B0) -#define PORTF_PIN1CTRL _SFR_MEM8(0x06B1) -#define PORTF_PIN2CTRL _SFR_MEM8(0x06B2) -#define PORTF_PIN3CTRL _SFR_MEM8(0x06B3) -#define PORTF_PIN4CTRL _SFR_MEM8(0x06B4) -#define PORTF_PIN5CTRL _SFR_MEM8(0x06B5) -#define PORTF_PIN6CTRL _SFR_MEM8(0x06B6) -#define PORTF_PIN7CTRL _SFR_MEM8(0x06B7) - -/* PORTR - Port R */ -#define PORTR_DIR _SFR_MEM8(0x07E0) -#define PORTR_DIRSET _SFR_MEM8(0x07E1) -#define PORTR_DIRCLR _SFR_MEM8(0x07E2) -#define PORTR_DIRTGL _SFR_MEM8(0x07E3) -#define PORTR_OUT _SFR_MEM8(0x07E4) -#define PORTR_OUTSET _SFR_MEM8(0x07E5) -#define PORTR_OUTCLR _SFR_MEM8(0x07E6) -#define PORTR_OUTTGL _SFR_MEM8(0x07E7) -#define PORTR_IN _SFR_MEM8(0x07E8) -#define PORTR_INTCTRL _SFR_MEM8(0x07E9) -#define PORTR_INT0MASK _SFR_MEM8(0x07EA) -#define PORTR_INT1MASK _SFR_MEM8(0x07EB) -#define PORTR_INTFLAGS _SFR_MEM8(0x07EC) -#define PORTR_PIN0CTRL _SFR_MEM8(0x07F0) -#define PORTR_PIN1CTRL _SFR_MEM8(0x07F1) -#define PORTR_PIN2CTRL _SFR_MEM8(0x07F2) -#define PORTR_PIN3CTRL _SFR_MEM8(0x07F3) -#define PORTR_PIN4CTRL _SFR_MEM8(0x07F4) -#define PORTR_PIN5CTRL _SFR_MEM8(0x07F5) -#define PORTR_PIN6CTRL _SFR_MEM8(0x07F6) -#define PORTR_PIN7CTRL _SFR_MEM8(0x07F7) - -/* TCC0 - Timer/Counter C0 */ -#define TCC0_CTRLA _SFR_MEM8(0x0800) -#define TCC0_CTRLB _SFR_MEM8(0x0801) -#define TCC0_CTRLC _SFR_MEM8(0x0802) -#define TCC0_CTRLD _SFR_MEM8(0x0803) -#define TCC0_CTRLE _SFR_MEM8(0x0804) -#define TCC0_INTCTRLA _SFR_MEM8(0x0806) -#define TCC0_INTCTRLB _SFR_MEM8(0x0807) -#define TCC0_CTRLFCLR _SFR_MEM8(0x0808) -#define TCC0_CTRLFSET _SFR_MEM8(0x0809) -#define TCC0_CTRLGCLR _SFR_MEM8(0x080A) -#define TCC0_CTRLGSET _SFR_MEM8(0x080B) -#define TCC0_INTFLAGS _SFR_MEM8(0x080C) -#define TCC0_TEMP _SFR_MEM8(0x080F) -#define TCC0_CNT _SFR_MEM16(0x0820) -#define TCC0_PER _SFR_MEM16(0x0826) -#define TCC0_CCA _SFR_MEM16(0x0828) -#define TCC0_CCB _SFR_MEM16(0x082A) -#define TCC0_CCC _SFR_MEM16(0x082C) -#define TCC0_CCD _SFR_MEM16(0x082E) -#define TCC0_PERBUF _SFR_MEM16(0x0836) -#define TCC0_CCABUF _SFR_MEM16(0x0838) -#define TCC0_CCBBUF _SFR_MEM16(0x083A) -#define TCC0_CCCBUF _SFR_MEM16(0x083C) -#define TCC0_CCDBUF _SFR_MEM16(0x083E) - -/* TCC1 - Timer/Counter C1 */ -#define TCC1_CTRLA _SFR_MEM8(0x0840) -#define TCC1_CTRLB _SFR_MEM8(0x0841) -#define TCC1_CTRLC _SFR_MEM8(0x0842) -#define TCC1_CTRLD _SFR_MEM8(0x0843) -#define TCC1_CTRLE _SFR_MEM8(0x0844) -#define TCC1_INTCTRLA _SFR_MEM8(0x0846) -#define TCC1_INTCTRLB _SFR_MEM8(0x0847) -#define TCC1_CTRLFCLR _SFR_MEM8(0x0848) -#define TCC1_CTRLFSET _SFR_MEM8(0x0849) -#define TCC1_CTRLGCLR _SFR_MEM8(0x084A) -#define TCC1_CTRLGSET _SFR_MEM8(0x084B) -#define TCC1_INTFLAGS _SFR_MEM8(0x084C) -#define TCC1_TEMP _SFR_MEM8(0x084F) -#define TCC1_CNT _SFR_MEM16(0x0860) -#define TCC1_PER _SFR_MEM16(0x0866) -#define TCC1_CCA _SFR_MEM16(0x0868) -#define TCC1_CCB _SFR_MEM16(0x086A) -#define TCC1_PERBUF _SFR_MEM16(0x0876) -#define TCC1_CCABUF _SFR_MEM16(0x0878) -#define TCC1_CCBBUF _SFR_MEM16(0x087A) - -/* AWEXC - Advanced Waveform Extension C */ -#define AWEXC_CTRL _SFR_MEM8(0x0880) -#define AWEXC_FDEMASK _SFR_MEM8(0x0882) -#define AWEXC_FDCTRL _SFR_MEM8(0x0883) -#define AWEXC_STATUS _SFR_MEM8(0x0884) -#define AWEXC_DTBOTH _SFR_MEM8(0x0886) -#define AWEXC_DTBOTHBUF _SFR_MEM8(0x0887) -#define AWEXC_DTLS _SFR_MEM8(0x0888) -#define AWEXC_DTHS _SFR_MEM8(0x0889) -#define AWEXC_DTLSBUF _SFR_MEM8(0x088A) -#define AWEXC_DTHSBUF _SFR_MEM8(0x088B) -#define AWEXC_OUTOVEN _SFR_MEM8(0x088C) - -/* HIRESC - High-Resolution Extension C */ -#define HIRESC_CTRLA _SFR_MEM8(0x0890) - -/* USARTC0 - Universal Asynchronous Receiver-Transmitter C0 */ -#define USARTC0_DATA _SFR_MEM8(0x08A0) -#define USARTC0_STATUS _SFR_MEM8(0x08A1) -#define USARTC0_CTRLA _SFR_MEM8(0x08A3) -#define USARTC0_CTRLB _SFR_MEM8(0x08A4) -#define USARTC0_CTRLC _SFR_MEM8(0x08A5) -#define USARTC0_BAUDCTRLA _SFR_MEM8(0x08A6) -#define USARTC0_BAUDCTRLB _SFR_MEM8(0x08A7) - -/* USARTC1 - Universal Asynchronous Receiver-Transmitter C1 */ -#define USARTC1_DATA _SFR_MEM8(0x08B0) -#define USARTC1_STATUS _SFR_MEM8(0x08B1) -#define USARTC1_CTRLA _SFR_MEM8(0x08B3) -#define USARTC1_CTRLB _SFR_MEM8(0x08B4) -#define USARTC1_CTRLC _SFR_MEM8(0x08B5) -#define USARTC1_BAUDCTRLA _SFR_MEM8(0x08B6) -#define USARTC1_BAUDCTRLB _SFR_MEM8(0x08B7) - -/* SPIC - Serial Peripheral Interface C */ -#define SPIC_CTRL _SFR_MEM8(0x08C0) -#define SPIC_INTCTRL _SFR_MEM8(0x08C1) -#define SPIC_STATUS _SFR_MEM8(0x08C2) -#define SPIC_DATA _SFR_MEM8(0x08C3) - -/* IRCOM - IR Communication Module */ -#define IRCOM_CTRL _SFR_MEM8(0x08F8) -#define IRCOM_TXPLCTRL _SFR_MEM8(0x08F9) -#define IRCOM_RXPLCTRL _SFR_MEM8(0x08FA) - -/* TCD0 - Timer/Counter D0 */ -#define TCD0_CTRLA _SFR_MEM8(0x0900) -#define TCD0_CTRLB _SFR_MEM8(0x0901) -#define TCD0_CTRLC _SFR_MEM8(0x0902) -#define TCD0_CTRLD _SFR_MEM8(0x0903) -#define TCD0_CTRLE _SFR_MEM8(0x0904) -#define TCD0_INTCTRLA _SFR_MEM8(0x0906) -#define TCD0_INTCTRLB _SFR_MEM8(0x0907) -#define TCD0_CTRLFCLR _SFR_MEM8(0x0908) -#define TCD0_CTRLFSET _SFR_MEM8(0x0909) -#define TCD0_CTRLGCLR _SFR_MEM8(0x090A) -#define TCD0_CTRLGSET _SFR_MEM8(0x090B) -#define TCD0_INTFLAGS _SFR_MEM8(0x090C) -#define TCD0_TEMP _SFR_MEM8(0x090F) -#define TCD0_CNT _SFR_MEM16(0x0920) -#define TCD0_PER _SFR_MEM16(0x0926) -#define TCD0_CCA _SFR_MEM16(0x0928) -#define TCD0_CCB _SFR_MEM16(0x092A) -#define TCD0_CCC _SFR_MEM16(0x092C) -#define TCD0_CCD _SFR_MEM16(0x092E) -#define TCD0_PERBUF _SFR_MEM16(0x0936) -#define TCD0_CCABUF _SFR_MEM16(0x0938) -#define TCD0_CCBBUF _SFR_MEM16(0x093A) -#define TCD0_CCCBUF _SFR_MEM16(0x093C) -#define TCD0_CCDBUF _SFR_MEM16(0x093E) - -/* TCD1 - Timer/Counter D1 */ -#define TCD1_CTRLA _SFR_MEM8(0x0940) -#define TCD1_CTRLB _SFR_MEM8(0x0941) -#define TCD1_CTRLC _SFR_MEM8(0x0942) -#define TCD1_CTRLD _SFR_MEM8(0x0943) -#define TCD1_CTRLE _SFR_MEM8(0x0944) -#define TCD1_INTCTRLA _SFR_MEM8(0x0946) -#define TCD1_INTCTRLB _SFR_MEM8(0x0947) -#define TCD1_CTRLFCLR _SFR_MEM8(0x0948) -#define TCD1_CTRLFSET _SFR_MEM8(0x0949) -#define TCD1_CTRLGCLR _SFR_MEM8(0x094A) -#define TCD1_CTRLGSET _SFR_MEM8(0x094B) -#define TCD1_INTFLAGS _SFR_MEM8(0x094C) -#define TCD1_TEMP _SFR_MEM8(0x094F) -#define TCD1_CNT _SFR_MEM16(0x0960) -#define TCD1_PER _SFR_MEM16(0x0966) -#define TCD1_CCA _SFR_MEM16(0x0968) -#define TCD1_CCB _SFR_MEM16(0x096A) -#define TCD1_PERBUF _SFR_MEM16(0x0976) -#define TCD1_CCABUF _SFR_MEM16(0x0978) -#define TCD1_CCBBUF _SFR_MEM16(0x097A) - -/* HIRESD - High-Resolution Extension D */ -#define HIRESD_CTRLA _SFR_MEM8(0x0990) - -/* USARTD0 - Universal Asynchronous Receiver-Transmitter D0 */ -#define USARTD0_DATA _SFR_MEM8(0x09A0) -#define USARTD0_STATUS _SFR_MEM8(0x09A1) -#define USARTD0_CTRLA _SFR_MEM8(0x09A3) -#define USARTD0_CTRLB _SFR_MEM8(0x09A4) -#define USARTD0_CTRLC _SFR_MEM8(0x09A5) -#define USARTD0_BAUDCTRLA _SFR_MEM8(0x09A6) -#define USARTD0_BAUDCTRLB _SFR_MEM8(0x09A7) - -/* USARTD1 - Universal Asynchronous Receiver-Transmitter D1 */ -#define USARTD1_DATA _SFR_MEM8(0x09B0) -#define USARTD1_STATUS _SFR_MEM8(0x09B1) -#define USARTD1_CTRLA _SFR_MEM8(0x09B3) -#define USARTD1_CTRLB _SFR_MEM8(0x09B4) -#define USARTD1_CTRLC _SFR_MEM8(0x09B5) -#define USARTD1_BAUDCTRLA _SFR_MEM8(0x09B6) -#define USARTD1_BAUDCTRLB _SFR_MEM8(0x09B7) - -/* SPID - Serial Peripheral Interface D */ -#define SPID_CTRL _SFR_MEM8(0x09C0) -#define SPID_INTCTRL _SFR_MEM8(0x09C1) -#define SPID_STATUS _SFR_MEM8(0x09C2) -#define SPID_DATA _SFR_MEM8(0x09C3) - -/* TCE0 - Timer/Counter E0 */ -#define TCE0_CTRLA _SFR_MEM8(0x0A00) -#define TCE0_CTRLB _SFR_MEM8(0x0A01) -#define TCE0_CTRLC _SFR_MEM8(0x0A02) -#define TCE0_CTRLD _SFR_MEM8(0x0A03) -#define TCE0_CTRLE _SFR_MEM8(0x0A04) -#define TCE0_INTCTRLA _SFR_MEM8(0x0A06) -#define TCE0_INTCTRLB _SFR_MEM8(0x0A07) -#define TCE0_CTRLFCLR _SFR_MEM8(0x0A08) -#define TCE0_CTRLFSET _SFR_MEM8(0x0A09) -#define TCE0_CTRLGCLR _SFR_MEM8(0x0A0A) -#define TCE0_CTRLGSET _SFR_MEM8(0x0A0B) -#define TCE0_INTFLAGS _SFR_MEM8(0x0A0C) -#define TCE0_TEMP _SFR_MEM8(0x0A0F) -#define TCE0_CNT _SFR_MEM16(0x0A20) -#define TCE0_PER _SFR_MEM16(0x0A26) -#define TCE0_CCA _SFR_MEM16(0x0A28) -#define TCE0_CCB _SFR_MEM16(0x0A2A) -#define TCE0_CCC _SFR_MEM16(0x0A2C) -#define TCE0_CCD _SFR_MEM16(0x0A2E) -#define TCE0_PERBUF _SFR_MEM16(0x0A36) -#define TCE0_CCABUF _SFR_MEM16(0x0A38) -#define TCE0_CCBBUF _SFR_MEM16(0x0A3A) -#define TCE0_CCCBUF _SFR_MEM16(0x0A3C) -#define TCE0_CCDBUF _SFR_MEM16(0x0A3E) - -/* TCE1 - Timer/Counter E1 */ -#define TCE1_CTRLA _SFR_MEM8(0x0A40) -#define TCE1_CTRLB _SFR_MEM8(0x0A41) -#define TCE1_CTRLC _SFR_MEM8(0x0A42) -#define TCE1_CTRLD _SFR_MEM8(0x0A43) -#define TCE1_CTRLE _SFR_MEM8(0x0A44) -#define TCE1_INTCTRLA _SFR_MEM8(0x0A46) -#define TCE1_INTCTRLB _SFR_MEM8(0x0A47) -#define TCE1_CTRLFCLR _SFR_MEM8(0x0A48) -#define TCE1_CTRLFSET _SFR_MEM8(0x0A49) -#define TCE1_CTRLGCLR _SFR_MEM8(0x0A4A) -#define TCE1_CTRLGSET _SFR_MEM8(0x0A4B) -#define TCE1_INTFLAGS _SFR_MEM8(0x0A4C) -#define TCE1_TEMP _SFR_MEM8(0x0A4F) -#define TCE1_CNT _SFR_MEM16(0x0A60) -#define TCE1_PER _SFR_MEM16(0x0A66) -#define TCE1_CCA _SFR_MEM16(0x0A68) -#define TCE1_CCB _SFR_MEM16(0x0A6A) -#define TCE1_PERBUF _SFR_MEM16(0x0A76) -#define TCE1_CCABUF _SFR_MEM16(0x0A78) -#define TCE1_CCBBUF _SFR_MEM16(0x0A7A) - -/* AWEXE - Advanced Waveform Extension E */ -#define AWEXE_CTRL _SFR_MEM8(0x0A80) -#define AWEXE_FDEMASK _SFR_MEM8(0x0A82) -#define AWEXE_FDCTRL _SFR_MEM8(0x0A83) -#define AWEXE_STATUS _SFR_MEM8(0x0A84) -#define AWEXE_DTBOTH _SFR_MEM8(0x0A86) -#define AWEXE_DTBOTHBUF _SFR_MEM8(0x0A87) -#define AWEXE_DTLS _SFR_MEM8(0x0A88) -#define AWEXE_DTHS _SFR_MEM8(0x0A89) -#define AWEXE_DTLSBUF _SFR_MEM8(0x0A8A) -#define AWEXE_DTHSBUF _SFR_MEM8(0x0A8B) -#define AWEXE_OUTOVEN _SFR_MEM8(0x0A8C) - -/* HIRESE - High-Resolution Extension E */ -#define HIRESE_CTRLA _SFR_MEM8(0x0A90) - -/* USARTE0 - Universal Asynchronous Receiver-Transmitter E0 */ -#define USARTE0_DATA _SFR_MEM8(0x0AA0) -#define USARTE0_STATUS _SFR_MEM8(0x0AA1) -#define USARTE0_CTRLA _SFR_MEM8(0x0AA3) -#define USARTE0_CTRLB _SFR_MEM8(0x0AA4) -#define USARTE0_CTRLC _SFR_MEM8(0x0AA5) -#define USARTE0_BAUDCTRLA _SFR_MEM8(0x0AA6) -#define USARTE0_BAUDCTRLB _SFR_MEM8(0x0AA7) - -/* USARTE1 - Universal Asynchronous Receiver-Transmitter E1 */ -#define USARTE1_DATA _SFR_MEM8(0x0AB0) -#define USARTE1_STATUS _SFR_MEM8(0x0AB1) -#define USARTE1_CTRLA _SFR_MEM8(0x0AB3) -#define USARTE1_CTRLB _SFR_MEM8(0x0AB4) -#define USARTE1_CTRLC _SFR_MEM8(0x0AB5) -#define USARTE1_BAUDCTRLA _SFR_MEM8(0x0AB6) -#define USARTE1_BAUDCTRLB _SFR_MEM8(0x0AB7) - -/* SPIE - Serial Peripheral Interface E */ -#define SPIE_CTRL _SFR_MEM8(0x0AC0) -#define SPIE_INTCTRL _SFR_MEM8(0x0AC1) -#define SPIE_STATUS _SFR_MEM8(0x0AC2) -#define SPIE_DATA _SFR_MEM8(0x0AC3) - -/* TCF0 - Timer/Counter F0 */ -#define TCF0_CTRLA _SFR_MEM8(0x0B00) -#define TCF0_CTRLB _SFR_MEM8(0x0B01) -#define TCF0_CTRLC _SFR_MEM8(0x0B02) -#define TCF0_CTRLD _SFR_MEM8(0x0B03) -#define TCF0_CTRLE _SFR_MEM8(0x0B04) -#define TCF0_INTCTRLA _SFR_MEM8(0x0B06) -#define TCF0_INTCTRLB _SFR_MEM8(0x0B07) -#define TCF0_CTRLFCLR _SFR_MEM8(0x0B08) -#define TCF0_CTRLFSET _SFR_MEM8(0x0B09) -#define TCF0_CTRLGCLR _SFR_MEM8(0x0B0A) -#define TCF0_CTRLGSET _SFR_MEM8(0x0B0B) -#define TCF0_INTFLAGS _SFR_MEM8(0x0B0C) -#define TCF0_TEMP _SFR_MEM8(0x0B0F) -#define TCF0_CNT _SFR_MEM16(0x0B20) -#define TCF0_PER _SFR_MEM16(0x0B26) -#define TCF0_CCA _SFR_MEM16(0x0B28) -#define TCF0_CCB _SFR_MEM16(0x0B2A) -#define TCF0_CCC _SFR_MEM16(0x0B2C) -#define TCF0_CCD _SFR_MEM16(0x0B2E) -#define TCF0_PERBUF _SFR_MEM16(0x0B36) -#define TCF0_CCABUF _SFR_MEM16(0x0B38) -#define TCF0_CCBBUF _SFR_MEM16(0x0B3A) -#define TCF0_CCCBUF _SFR_MEM16(0x0B3C) -#define TCF0_CCDBUF _SFR_MEM16(0x0B3E) - -/* HIRESF - High-Resolution Extension F */ -#define HIRESF_CTRLA _SFR_MEM8(0x0B90) - -/* USARTF0 - Universal Asynchronous Receiver-Transmitter F0 */ -#define USARTF0_DATA _SFR_MEM8(0x0BA0) -#define USARTF0_STATUS _SFR_MEM8(0x0BA1) -#define USARTF0_CTRLA _SFR_MEM8(0x0BA3) -#define USARTF0_CTRLB _SFR_MEM8(0x0BA4) -#define USARTF0_CTRLC _SFR_MEM8(0x0BA5) -#define USARTF0_BAUDCTRLA _SFR_MEM8(0x0BA6) -#define USARTF0_BAUDCTRLB _SFR_MEM8(0x0BA7) - -/* USARTF1 - Universal Asynchronous Receiver-Transmitter F1 */ -#define USARTF1_DATA _SFR_MEM8(0x0BB0) -#define USARTF1_STATUS _SFR_MEM8(0x0BB1) -#define USARTF1_CTRLA _SFR_MEM8(0x0BB3) -#define USARTF1_CTRLB _SFR_MEM8(0x0BB4) -#define USARTF1_CTRLC _SFR_MEM8(0x0BB5) -#define USARTF1_BAUDCTRLA _SFR_MEM8(0x0BB6) -#define USARTF1_BAUDCTRLB _SFR_MEM8(0x0BB7) - -/* SPIF - Serial Peripheral Interface F */ -#define SPIF_CTRL _SFR_MEM8(0x0BC0) -#define SPIF_INTCTRL _SFR_MEM8(0x0BC1) -#define SPIF_STATUS _SFR_MEM8(0x0BC2) -#define SPIF_DATA _SFR_MEM8(0x0BC3) - - - -/*================== Bitfield Definitions ================== */ - -/* XOCD - On-Chip Debug System */ -/* OCD.OCDR1 bit masks and bit positions */ -#define OCD_OCDRD_bm 0x01 /* OCDR Dirty bit mask. */ -#define OCD_OCDRD_bp 0 /* OCDR Dirty bit position. */ - - -/* CPU - CPU */ -/* CPU.CCP bit masks and bit positions */ -#define CPU_CCP_gm 0xFF /* CCP signature group mask. */ -#define CPU_CCP_gp 0 /* CCP signature group position. */ -#define CPU_CCP0_bm (1<<0) /* CCP signature bit 0 mask. */ -#define CPU_CCP0_bp 0 /* CCP signature bit 0 position. */ -#define CPU_CCP1_bm (1<<1) /* CCP signature bit 1 mask. */ -#define CPU_CCP1_bp 1 /* CCP signature bit 1 position. */ -#define CPU_CCP2_bm (1<<2) /* CCP signature bit 2 mask. */ -#define CPU_CCP2_bp 2 /* CCP signature bit 2 position. */ -#define CPU_CCP3_bm (1<<3) /* CCP signature bit 3 mask. */ -#define CPU_CCP3_bp 3 /* CCP signature bit 3 position. */ -#define CPU_CCP4_bm (1<<4) /* CCP signature bit 4 mask. */ -#define CPU_CCP4_bp 4 /* CCP signature bit 4 position. */ -#define CPU_CCP5_bm (1<<5) /* CCP signature bit 5 mask. */ -#define CPU_CCP5_bp 5 /* CCP signature bit 5 position. */ -#define CPU_CCP6_bm (1<<6) /* CCP signature bit 6 mask. */ -#define CPU_CCP6_bp 6 /* CCP signature bit 6 position. */ -#define CPU_CCP7_bm (1<<7) /* CCP signature bit 7 mask. */ -#define CPU_CCP7_bp 7 /* CCP signature bit 7 position. */ - - -/* CPU.SREG bit masks and bit positions */ -#define CPU_I_bm 0x80 /* Global Interrupt Enable Flag bit mask. */ -#define CPU_I_bp 7 /* Global Interrupt Enable Flag bit position. */ - -#define CPU_T_bm 0x40 /* Transfer Bit bit mask. */ -#define CPU_T_bp 6 /* Transfer Bit bit position. */ - -#define CPU_H_bm 0x20 /* Half Carry Flag bit mask. */ -#define CPU_H_bp 5 /* Half Carry Flag bit position. */ - -#define CPU_S_bm 0x10 /* N Exclusive Or V Flag bit mask. */ -#define CPU_S_bp 4 /* N Exclusive Or V Flag bit position. */ - -#define CPU_V_bm 0x08 /* Two's Complement Overflow Flag bit mask. */ -#define CPU_V_bp 3 /* Two's Complement Overflow Flag bit position. */ - -#define CPU_N_bm 0x04 /* Negative Flag bit mask. */ -#define CPU_N_bp 2 /* Negative Flag bit position. */ - -#define CPU_Z_bm 0x02 /* Zero Flag bit mask. */ -#define CPU_Z_bp 1 /* Zero Flag bit position. */ - -#define CPU_C_bm 0x01 /* Carry Flag bit mask. */ -#define CPU_C_bp 0 /* Carry Flag bit position. */ - - -/* CLK - Clock System */ -/* CLK.CTRL bit masks and bit positions */ -#define CLK_SCLKSEL_gm 0x07 /* System Clock Selection group mask. */ -#define CLK_SCLKSEL_gp 0 /* System Clock Selection group position. */ -#define CLK_SCLKSEL0_bm (1<<0) /* System Clock Selection bit 0 mask. */ -#define CLK_SCLKSEL0_bp 0 /* System Clock Selection bit 0 position. */ -#define CLK_SCLKSEL1_bm (1<<1) /* System Clock Selection bit 1 mask. */ -#define CLK_SCLKSEL1_bp 1 /* System Clock Selection bit 1 position. */ -#define CLK_SCLKSEL2_bm (1<<2) /* System Clock Selection bit 2 mask. */ -#define CLK_SCLKSEL2_bp 2 /* System Clock Selection bit 2 position. */ - - -/* CLK.PSCTRL bit masks and bit positions */ -#define CLK_PSADIV_gm 0x7C /* Prescaler A Division Factor group mask. */ -#define CLK_PSADIV_gp 2 /* Prescaler A Division Factor group position. */ -#define CLK_PSADIV0_bm (1<<2) /* Prescaler A Division Factor bit 0 mask. */ -#define CLK_PSADIV0_bp 2 /* Prescaler A Division Factor bit 0 position. */ -#define CLK_PSADIV1_bm (1<<3) /* Prescaler A Division Factor bit 1 mask. */ -#define CLK_PSADIV1_bp 3 /* Prescaler A Division Factor bit 1 position. */ -#define CLK_PSADIV2_bm (1<<4) /* Prescaler A Division Factor bit 2 mask. */ -#define CLK_PSADIV2_bp 4 /* Prescaler A Division Factor bit 2 position. */ -#define CLK_PSADIV3_bm (1<<5) /* Prescaler A Division Factor bit 3 mask. */ -#define CLK_PSADIV3_bp 5 /* Prescaler A Division Factor bit 3 position. */ -#define CLK_PSADIV4_bm (1<<6) /* Prescaler A Division Factor bit 4 mask. */ -#define CLK_PSADIV4_bp 6 /* Prescaler A Division Factor bit 4 position. */ - -#define CLK_PSBCDIV_gm 0x03 /* Prescaler B and C Division factor group mask. */ -#define CLK_PSBCDIV_gp 0 /* Prescaler B and C Division factor group position. */ -#define CLK_PSBCDIV0_bm (1<<0) /* Prescaler B and C Division factor bit 0 mask. */ -#define CLK_PSBCDIV0_bp 0 /* Prescaler B and C Division factor bit 0 position. */ -#define CLK_PSBCDIV1_bm (1<<1) /* Prescaler B and C Division factor bit 1 mask. */ -#define CLK_PSBCDIV1_bp 1 /* Prescaler B and C Division factor bit 1 position. */ - - -/* CLK.LOCK bit masks and bit positions */ -#define CLK_LOCK_bm 0x01 /* Clock System Lock bit mask. */ -#define CLK_LOCK_bp 0 /* Clock System Lock bit position. */ - - -/* CLK.RTCCTRL bit masks and bit positions */ -#define CLK_RTCSRC_gm 0x0E /* Clock Source group mask. */ -#define CLK_RTCSRC_gp 1 /* Clock Source group position. */ -#define CLK_RTCSRC0_bm (1<<1) /* Clock Source bit 0 mask. */ -#define CLK_RTCSRC0_bp 1 /* Clock Source bit 0 position. */ -#define CLK_RTCSRC1_bm (1<<2) /* Clock Source bit 1 mask. */ -#define CLK_RTCSRC1_bp 2 /* Clock Source bit 1 position. */ -#define CLK_RTCSRC2_bm (1<<3) /* Clock Source bit 2 mask. */ -#define CLK_RTCSRC2_bp 3 /* Clock Source bit 2 position. */ - -#define CLK_RTCEN_bm 0x01 /* RTC Clock Source Enable bit mask. */ -#define CLK_RTCEN_bp 0 /* RTC Clock Source Enable bit position. */ - - -/* PR.PRGEN bit masks and bit positions */ -#define PR_AES_bm 0x10 /* AES bit mask. */ -#define PR_AES_bp 4 /* AES bit position. */ - -#define PR_EBI_bm 0x08 /* External Bus Interface bit mask. */ -#define PR_EBI_bp 3 /* External Bus Interface bit position. */ - -#define PR_RTC_bm 0x04 /* Real-time Counter bit mask. */ -#define PR_RTC_bp 2 /* Real-time Counter bit position. */ - -#define PR_EVSYS_bm 0x02 /* Event System bit mask. */ -#define PR_EVSYS_bp 1 /* Event System bit position. */ - -#define PR_DMA_bm 0x01 /* DMA-Controller bit mask. */ -#define PR_DMA_bp 0 /* DMA-Controller bit position. */ - - -/* PR.PRPA bit masks and bit positions */ -#define PR_DAC_bm 0x04 /* Port A DAC bit mask. */ -#define PR_DAC_bp 2 /* Port A DAC bit position. */ - -#define PR_ADC_bm 0x02 /* Port A ADC bit mask. */ -#define PR_ADC_bp 1 /* Port A ADC bit position. */ - -#define PR_AC_bm 0x01 /* Port A Analog Comparator bit mask. */ -#define PR_AC_bp 0 /* Port A Analog Comparator bit position. */ - - -/* PR.PRPB bit masks and bit positions */ -/* PR_DAC_bm Predefined. */ -/* PR_DAC_bp Predefined. */ - -/* PR_ADC_bm Predefined. */ -/* PR_ADC_bp Predefined. */ - -/* PR_AC_bm Predefined. */ -/* PR_AC_bp Predefined. */ - - -/* PR.PRPC bit masks and bit positions */ -#define PR_TWI_bm 0x40 /* Port C Two-wire Interface bit mask. */ -#define PR_TWI_bp 6 /* Port C Two-wire Interface bit position. */ - -#define PR_USART1_bm 0x20 /* Port C USART1 bit mask. */ -#define PR_USART1_bp 5 /* Port C USART1 bit position. */ - -#define PR_USART0_bm 0x10 /* Port C USART0 bit mask. */ -#define PR_USART0_bp 4 /* Port C USART0 bit position. */ - -#define PR_SPI_bm 0x08 /* Port C SPI bit mask. */ -#define PR_SPI_bp 3 /* Port C SPI bit position. */ - -#define PR_HIRES_bm 0x04 /* Port C AWEX bit mask. */ -#define PR_HIRES_bp 2 /* Port C AWEX bit position. */ - -#define PR_TC1_bm 0x02 /* Port C Timer/Counter1 bit mask. */ -#define PR_TC1_bp 1 /* Port C Timer/Counter1 bit position. */ - -#define PR_TC0_bm 0x01 /* Port C Timer/Counter0 bit mask. */ -#define PR_TC0_bp 0 /* Port C Timer/Counter0 bit position. */ - - -/* PR.PRPD bit masks and bit positions */ -/* PR_TWI_bm Predefined. */ -/* PR_TWI_bp Predefined. */ - -/* PR_USART1_bm Predefined. */ -/* PR_USART1_bp Predefined. */ - -/* PR_USART0_bm Predefined. */ -/* PR_USART0_bp Predefined. */ - -/* PR_SPI_bm Predefined. */ -/* PR_SPI_bp Predefined. */ - -/* PR_HIRES_bm Predefined. */ -/* PR_HIRES_bp Predefined. */ - -/* PR_TC1_bm Predefined. */ -/* PR_TC1_bp Predefined. */ - -/* PR_TC0_bm Predefined. */ -/* PR_TC0_bp Predefined. */ - - -/* PR.PRPE bit masks and bit positions */ -/* PR_TWI_bm Predefined. */ -/* PR_TWI_bp Predefined. */ - -/* PR_USART1_bm Predefined. */ -/* PR_USART1_bp Predefined. */ - -/* PR_USART0_bm Predefined. */ -/* PR_USART0_bp Predefined. */ - -/* PR_SPI_bm Predefined. */ -/* PR_SPI_bp Predefined. */ - -/* PR_HIRES_bm Predefined. */ -/* PR_HIRES_bp Predefined. */ - -/* PR_TC1_bm Predefined. */ -/* PR_TC1_bp Predefined. */ - -/* PR_TC0_bm Predefined. */ -/* PR_TC0_bp Predefined. */ - - -/* PR.PRPF bit masks and bit positions */ -/* PR_TWI_bm Predefined. */ -/* PR_TWI_bp Predefined. */ - -/* PR_USART1_bm Predefined. */ -/* PR_USART1_bp Predefined. */ - -/* PR_USART0_bm Predefined. */ -/* PR_USART0_bp Predefined. */ - -/* PR_SPI_bm Predefined. */ -/* PR_SPI_bp Predefined. */ - -/* PR_HIRES_bm Predefined. */ -/* PR_HIRES_bp Predefined. */ - -/* PR_TC1_bm Predefined. */ -/* PR_TC1_bp Predefined. */ - -/* PR_TC0_bm Predefined. */ -/* PR_TC0_bp Predefined. */ - - -/* SLEEP - Sleep Controller */ -/* SLEEP.CTRL bit masks and bit positions */ -#define SLEEP_SMODE_gm 0x0E /* Sleep Mode group mask. */ -#define SLEEP_SMODE_gp 1 /* Sleep Mode group position. */ -#define SLEEP_SMODE0_bm (1<<1) /* Sleep Mode bit 0 mask. */ -#define SLEEP_SMODE0_bp 1 /* Sleep Mode bit 0 position. */ -#define SLEEP_SMODE1_bm (1<<2) /* Sleep Mode bit 1 mask. */ -#define SLEEP_SMODE1_bp 2 /* Sleep Mode bit 1 position. */ -#define SLEEP_SMODE2_bm (1<<3) /* Sleep Mode bit 2 mask. */ -#define SLEEP_SMODE2_bp 3 /* Sleep Mode bit 2 position. */ - -#define SLEEP_SEN_bm 0x01 /* Sleep Enable bit mask. */ -#define SLEEP_SEN_bp 0 /* Sleep Enable bit position. */ - - -/* OSC - Oscillator */ -/* OSC.CTRL bit masks and bit positions */ -#define OSC_PLLEN_bm 0x10 /* PLL Enable bit mask. */ -#define OSC_PLLEN_bp 4 /* PLL Enable bit position. */ - -#define OSC_XOSCEN_bm 0x08 /* External Oscillator Enable bit mask. */ -#define OSC_XOSCEN_bp 3 /* External Oscillator Enable bit position. */ - -#define OSC_RC32KEN_bm 0x04 /* Internal 32kHz RC Oscillator Enable bit mask. */ -#define OSC_RC32KEN_bp 2 /* Internal 32kHz RC Oscillator Enable bit position. */ - -#define OSC_RC32MEN_bm 0x02 /* Internal 32MHz RC Oscillator Enable bit mask. */ -#define OSC_RC32MEN_bp 1 /* Internal 32MHz RC Oscillator Enable bit position. */ - -#define OSC_RC2MEN_bm 0x01 /* Internal 2MHz RC Oscillator Enable bit mask. */ -#define OSC_RC2MEN_bp 0 /* Internal 2MHz RC Oscillator Enable bit position. */ - - -/* OSC.STATUS bit masks and bit positions */ -#define OSC_PLLRDY_bm 0x10 /* PLL Ready bit mask. */ -#define OSC_PLLRDY_bp 4 /* PLL Ready bit position. */ - -#define OSC_XOSCRDY_bm 0x08 /* External Oscillator Ready bit mask. */ -#define OSC_XOSCRDY_bp 3 /* External Oscillator Ready bit position. */ - -#define OSC_RC32KRDY_bm 0x04 /* Internal 32kHz RC Oscillator Ready bit mask. */ -#define OSC_RC32KRDY_bp 2 /* Internal 32kHz RC Oscillator Ready bit position. */ - -#define OSC_RC32MRDY_bm 0x02 /* Internal 32MHz RC Oscillator Ready bit mask. */ -#define OSC_RC32MRDY_bp 1 /* Internal 32MHz RC Oscillator Ready bit position. */ - -#define OSC_RC2MRDY_bm 0x01 /* Internal 2MHz RC Oscillator Ready bit mask. */ -#define OSC_RC2MRDY_bp 0 /* Internal 2MHz RC Oscillator Ready bit position. */ - - -/* OSC.XOSCCTRL bit masks and bit positions */ -#define OSC_FRQRANGE_gm 0xC0 /* Frequency Range group mask. */ -#define OSC_FRQRANGE_gp 6 /* Frequency Range group position. */ -#define OSC_FRQRANGE0_bm (1<<6) /* Frequency Range bit 0 mask. */ -#define OSC_FRQRANGE0_bp 6 /* Frequency Range bit 0 position. */ -#define OSC_FRQRANGE1_bm (1<<7) /* Frequency Range bit 1 mask. */ -#define OSC_FRQRANGE1_bp 7 /* Frequency Range bit 1 position. */ - -#define OSC_X32KLPM_bm 0x20 /* 32kHz XTAL OSC Low-power Mode bit mask. */ -#define OSC_X32KLPM_bp 5 /* 32kHz XTAL OSC Low-power Mode bit position. */ - -#define OSC_XOSCSEL_gm 0x0F /* External Oscillator Selection and Startup Time group mask. */ -#define OSC_XOSCSEL_gp 0 /* External Oscillator Selection and Startup Time group position. */ -#define OSC_XOSCSEL0_bm (1<<0) /* External Oscillator Selection and Startup Time bit 0 mask. */ -#define OSC_XOSCSEL0_bp 0 /* External Oscillator Selection and Startup Time bit 0 position. */ -#define OSC_XOSCSEL1_bm (1<<1) /* External Oscillator Selection and Startup Time bit 1 mask. */ -#define OSC_XOSCSEL1_bp 1 /* External Oscillator Selection and Startup Time bit 1 position. */ -#define OSC_XOSCSEL2_bm (1<<2) /* External Oscillator Selection and Startup Time bit 2 mask. */ -#define OSC_XOSCSEL2_bp 2 /* External Oscillator Selection and Startup Time bit 2 position. */ -#define OSC_XOSCSEL3_bm (1<<3) /* External Oscillator Selection and Startup Time bit 3 mask. */ -#define OSC_XOSCSEL3_bp 3 /* External Oscillator Selection and Startup Time bit 3 position. */ - - -/* OSC.XOSCFAIL bit masks and bit positions */ -#define OSC_XOSCFDIF_bm 0x02 /* Failure Detection Interrupt Flag bit mask. */ -#define OSC_XOSCFDIF_bp 1 /* Failure Detection Interrupt Flag bit position. */ - -#define OSC_XOSCFDEN_bm 0x01 /* Failure Detection Enable bit mask. */ -#define OSC_XOSCFDEN_bp 0 /* Failure Detection Enable bit position. */ - - -/* OSC.PLLCTRL bit masks and bit positions */ -#define OSC_PLLSRC_gm 0xC0 /* Clock Source group mask. */ -#define OSC_PLLSRC_gp 6 /* Clock Source group position. */ -#define OSC_PLLSRC0_bm (1<<6) /* Clock Source bit 0 mask. */ -#define OSC_PLLSRC0_bp 6 /* Clock Source bit 0 position. */ -#define OSC_PLLSRC1_bm (1<<7) /* Clock Source bit 1 mask. */ -#define OSC_PLLSRC1_bp 7 /* Clock Source bit 1 position. */ - -#define OSC_PLLFAC_gm 0x1F /* Multiplication Factor group mask. */ -#define OSC_PLLFAC_gp 0 /* Multiplication Factor group position. */ -#define OSC_PLLFAC0_bm (1<<0) /* Multiplication Factor bit 0 mask. */ -#define OSC_PLLFAC0_bp 0 /* Multiplication Factor bit 0 position. */ -#define OSC_PLLFAC1_bm (1<<1) /* Multiplication Factor bit 1 mask. */ -#define OSC_PLLFAC1_bp 1 /* Multiplication Factor bit 1 position. */ -#define OSC_PLLFAC2_bm (1<<2) /* Multiplication Factor bit 2 mask. */ -#define OSC_PLLFAC2_bp 2 /* Multiplication Factor bit 2 position. */ -#define OSC_PLLFAC3_bm (1<<3) /* Multiplication Factor bit 3 mask. */ -#define OSC_PLLFAC3_bp 3 /* Multiplication Factor bit 3 position. */ -#define OSC_PLLFAC4_bm (1<<4) /* Multiplication Factor bit 4 mask. */ -#define OSC_PLLFAC4_bp 4 /* Multiplication Factor bit 4 position. */ - - -/* OSC.DFLLCTRL bit masks and bit positions */ -#define OSC_RC32MCREF_bm 0x02 /* 32MHz Calibration Reference bit mask. */ -#define OSC_RC32MCREF_bp 1 /* 32MHz Calibration Reference bit position. */ - -#define OSC_RC2MCREF_bm 0x01 /* 2MHz Calibration Reference bit mask. */ -#define OSC_RC2MCREF_bp 0 /* 2MHz Calibration Reference bit position. */ - - -/* DFLL - DFLL */ -/* DFLL.CTRL bit masks and bit positions */ -#define DFLL_ENABLE_bm 0x01 /* DFLL Enable bit mask. */ -#define DFLL_ENABLE_bp 0 /* DFLL Enable bit position. */ - - -/* DFLL.CALA bit masks and bit positions */ -#define DFLL_CALL_gm 0x7F /* DFLL Calibration bits [6:0] group mask. */ -#define DFLL_CALL_gp 0 /* DFLL Calibration bits [6:0] group position. */ -#define DFLL_CALL0_bm (1<<0) /* DFLL Calibration bits [6:0] bit 0 mask. */ -#define DFLL_CALL0_bp 0 /* DFLL Calibration bits [6:0] bit 0 position. */ -#define DFLL_CALL1_bm (1<<1) /* DFLL Calibration bits [6:0] bit 1 mask. */ -#define DFLL_CALL1_bp 1 /* DFLL Calibration bits [6:0] bit 1 position. */ -#define DFLL_CALL2_bm (1<<2) /* DFLL Calibration bits [6:0] bit 2 mask. */ -#define DFLL_CALL2_bp 2 /* DFLL Calibration bits [6:0] bit 2 position. */ -#define DFLL_CALL3_bm (1<<3) /* DFLL Calibration bits [6:0] bit 3 mask. */ -#define DFLL_CALL3_bp 3 /* DFLL Calibration bits [6:0] bit 3 position. */ -#define DFLL_CALL4_bm (1<<4) /* DFLL Calibration bits [6:0] bit 4 mask. */ -#define DFLL_CALL4_bp 4 /* DFLL Calibration bits [6:0] bit 4 position. */ -#define DFLL_CALL5_bm (1<<5) /* DFLL Calibration bits [6:0] bit 5 mask. */ -#define DFLL_CALL5_bp 5 /* DFLL Calibration bits [6:0] bit 5 position. */ -#define DFLL_CALL6_bm (1<<6) /* DFLL Calibration bits [6:0] bit 6 mask. */ -#define DFLL_CALL6_bp 6 /* DFLL Calibration bits [6:0] bit 6 position. */ - - -/* DFLL.CALB bit masks and bit positions */ -#define DFLL_CALH_gm 0x3F /* DFLL Calibration bits [12:7] group mask. */ -#define DFLL_CALH_gp 0 /* DFLL Calibration bits [12:7] group position. */ -#define DFLL_CALH0_bm (1<<0) /* DFLL Calibration bits [12:7] bit 0 mask. */ -#define DFLL_CALH0_bp 0 /* DFLL Calibration bits [12:7] bit 0 position. */ -#define DFLL_CALH1_bm (1<<1) /* DFLL Calibration bits [12:7] bit 1 mask. */ -#define DFLL_CALH1_bp 1 /* DFLL Calibration bits [12:7] bit 1 position. */ -#define DFLL_CALH2_bm (1<<2) /* DFLL Calibration bits [12:7] bit 2 mask. */ -#define DFLL_CALH2_bp 2 /* DFLL Calibration bits [12:7] bit 2 position. */ -#define DFLL_CALH3_bm (1<<3) /* DFLL Calibration bits [12:7] bit 3 mask. */ -#define DFLL_CALH3_bp 3 /* DFLL Calibration bits [12:7] bit 3 position. */ -#define DFLL_CALH4_bm (1<<4) /* DFLL Calibration bits [12:7] bit 4 mask. */ -#define DFLL_CALH4_bp 4 /* DFLL Calibration bits [12:7] bit 4 position. */ -#define DFLL_CALH5_bm (1<<5) /* DFLL Calibration bits [12:7] bit 5 mask. */ -#define DFLL_CALH5_bp 5 /* DFLL Calibration bits [12:7] bit 5 position. */ - - -/* RST - Reset */ -/* RST.STATUS bit masks and bit positions */ -#define RST_SDRF_bm 0x40 /* Spike Detection Reset Flag bit mask. */ -#define RST_SDRF_bp 6 /* Spike Detection Reset Flag bit position. */ - -#define RST_SRF_bm 0x20 /* Software Reset Flag bit mask. */ -#define RST_SRF_bp 5 /* Software Reset Flag bit position. */ - -#define RST_PDIRF_bm 0x10 /* Programming and Debug Interface Interface Reset Flag bit mask. */ -#define RST_PDIRF_bp 4 /* Programming and Debug Interface Interface Reset Flag bit position. */ - -#define RST_WDRF_bm 0x08 /* Watchdog Reset Flag bit mask. */ -#define RST_WDRF_bp 3 /* Watchdog Reset Flag bit position. */ - -#define RST_BORF_bm 0x04 /* Brown-out Reset Flag bit mask. */ -#define RST_BORF_bp 2 /* Brown-out Reset Flag bit position. */ - -#define RST_EXTRF_bm 0x02 /* External Reset Flag bit mask. */ -#define RST_EXTRF_bp 1 /* External Reset Flag bit position. */ - -#define RST_PORF_bm 0x01 /* Power-on Reset Flag bit mask. */ -#define RST_PORF_bp 0 /* Power-on Reset Flag bit position. */ - - -/* RST.CTRL bit masks and bit positions */ -#define RST_SWRST_bm 0x01 /* Software Reset bit mask. */ -#define RST_SWRST_bp 0 /* Software Reset bit position. */ - - -/* WDT - Watch-Dog Timer */ -/* WDT.CTRL bit masks and bit positions */ -#define WDT_PER_gm 0x3C /* Period group mask. */ -#define WDT_PER_gp 2 /* Period group position. */ -#define WDT_PER0_bm (1<<2) /* Period bit 0 mask. */ -#define WDT_PER0_bp 2 /* Period bit 0 position. */ -#define WDT_PER1_bm (1<<3) /* Period bit 1 mask. */ -#define WDT_PER1_bp 3 /* Period bit 1 position. */ -#define WDT_PER2_bm (1<<4) /* Period bit 2 mask. */ -#define WDT_PER2_bp 4 /* Period bit 2 position. */ -#define WDT_PER3_bm (1<<5) /* Period bit 3 mask. */ -#define WDT_PER3_bp 5 /* Period bit 3 position. */ - -#define WDT_ENABLE_bm 0x02 /* Enable bit mask. */ -#define WDT_ENABLE_bp 1 /* Enable bit position. */ - -#define WDT_CEN_bm 0x01 /* Change Enable bit mask. */ -#define WDT_CEN_bp 0 /* Change Enable bit position. */ - - -/* WDT.WINCTRL bit masks and bit positions */ -#define WDT_WPER_gm 0x3C /* Windowed Mode Period group mask. */ -#define WDT_WPER_gp 2 /* Windowed Mode Period group position. */ -#define WDT_WPER0_bm (1<<2) /* Windowed Mode Period bit 0 mask. */ -#define WDT_WPER0_bp 2 /* Windowed Mode Period bit 0 position. */ -#define WDT_WPER1_bm (1<<3) /* Windowed Mode Period bit 1 mask. */ -#define WDT_WPER1_bp 3 /* Windowed Mode Period bit 1 position. */ -#define WDT_WPER2_bm (1<<4) /* Windowed Mode Period bit 2 mask. */ -#define WDT_WPER2_bp 4 /* Windowed Mode Period bit 2 position. */ -#define WDT_WPER3_bm (1<<5) /* Windowed Mode Period bit 3 mask. */ -#define WDT_WPER3_bp 5 /* Windowed Mode Period bit 3 position. */ - -#define WDT_WEN_bm 0x02 /* Windowed Mode Enable bit mask. */ -#define WDT_WEN_bp 1 /* Windowed Mode Enable bit position. */ - -#define WDT_WCEN_bm 0x01 /* Windowed Mode Change Enable bit mask. */ -#define WDT_WCEN_bp 0 /* Windowed Mode Change Enable bit position. */ - - -/* WDT.STATUS bit masks and bit positions */ -#define WDT_SYNCBUSY_bm 0x01 /* Syncronization busy bit mask. */ -#define WDT_SYNCBUSY_bp 0 /* Syncronization busy bit position. */ - - -/* MCU - MCU Control */ -/* MCU.MCUCR bit masks and bit positions */ -#define MCU_JTAGD_bm 0x01 /* JTAG Disable bit mask. */ -#define MCU_JTAGD_bp 0 /* JTAG Disable bit position. */ - - -/* MCU.EVSYSLOCK bit masks and bit positions */ -#define MCU_EVSYS1LOCK_bm 0x10 /* Event Channel 4-7 Lock bit mask. */ -#define MCU_EVSYS1LOCK_bp 4 /* Event Channel 4-7 Lock bit position. */ - -#define MCU_EVSYS0LOCK_bm 0x01 /* Event Channel 0-3 Lock bit mask. */ -#define MCU_EVSYS0LOCK_bp 0 /* Event Channel 0-3 Lock bit position. */ - - -/* MCU.AWEXLOCK bit masks and bit positions */ -#define MCU_AWEXELOCK_bm 0x04 /* AWeX on T/C E0 Lock bit mask. */ -#define MCU_AWEXELOCK_bp 2 /* AWeX on T/C E0 Lock bit position. */ - -#define MCU_AWEXCLOCK_bm 0x01 /* AWeX on T/C C0 Lock bit mask. */ -#define MCU_AWEXCLOCK_bp 0 /* AWeX on T/C C0 Lock bit position. */ - - -/* PMIC - Programmable Multi-level Interrupt Controller */ -/* PMIC.STATUS bit masks and bit positions */ -#define PMIC_NMIEX_bm 0x80 /* Non-maskable Interrupt Executing bit mask. */ -#define PMIC_NMIEX_bp 7 /* Non-maskable Interrupt Executing bit position. */ - -#define PMIC_HILVLEX_bm 0x04 /* High Level Interrupt Executing bit mask. */ -#define PMIC_HILVLEX_bp 2 /* High Level Interrupt Executing bit position. */ - -#define PMIC_MEDLVLEX_bm 0x02 /* Medium Level Interrupt Executing bit mask. */ -#define PMIC_MEDLVLEX_bp 1 /* Medium Level Interrupt Executing bit position. */ - -#define PMIC_LOLVLEX_bm 0x01 /* Low Level Interrupt Executing bit mask. */ -#define PMIC_LOLVLEX_bp 0 /* Low Level Interrupt Executing bit position. */ - - -/* PMIC.CTRL bit masks and bit positions */ -#define PMIC_RREN_bm 0x80 /* Round-Robin Priority Enable bit mask. */ -#define PMIC_RREN_bp 7 /* Round-Robin Priority Enable bit position. */ - -#define PMIC_IVSEL_bm 0x40 /* Interrupt Vector Select bit mask. */ -#define PMIC_IVSEL_bp 6 /* Interrupt Vector Select bit position. */ - -#define PMIC_HILVLEN_bm 0x04 /* High Level Enable bit mask. */ -#define PMIC_HILVLEN_bp 2 /* High Level Enable bit position. */ - -#define PMIC_MEDLVLEN_bm 0x02 /* Medium Level Enable bit mask. */ -#define PMIC_MEDLVLEN_bp 1 /* Medium Level Enable bit position. */ - -#define PMIC_LOLVLEN_bm 0x01 /* Low Level Enable bit mask. */ -#define PMIC_LOLVLEN_bp 0 /* Low Level Enable bit position. */ - - -/* DMA - DMA Controller */ -/* DMA_CH.CTRLA bit masks and bit positions */ -#define DMA_CH_ENABLE_bm 0x80 /* Channel Enable bit mask. */ -#define DMA_CH_ENABLE_bp 7 /* Channel Enable bit position. */ - -#define DMA_CH_RESET_bm 0x40 /* Channel Software Reset bit mask. */ -#define DMA_CH_RESET_bp 6 /* Channel Software Reset bit position. */ - -#define DMA_CH_REPEAT_bm 0x20 /* Channel Repeat Mode bit mask. */ -#define DMA_CH_REPEAT_bp 5 /* Channel Repeat Mode bit position. */ - -#define DMA_CH_TRFREQ_bm 0x10 /* Channel Transfer Request bit mask. */ -#define DMA_CH_TRFREQ_bp 4 /* Channel Transfer Request bit position. */ - -#define DMA_CH_SINGLE_bm 0x04 /* Channel Single Shot Data Transfer bit mask. */ -#define DMA_CH_SINGLE_bp 2 /* Channel Single Shot Data Transfer bit position. */ - -#define DMA_CH_BURSTLEN_gm 0x03 /* Channel Transfer Mode group mask. */ -#define DMA_CH_BURSTLEN_gp 0 /* Channel Transfer Mode group position. */ -#define DMA_CH_BURSTLEN0_bm (1<<0) /* Channel Transfer Mode bit 0 mask. */ -#define DMA_CH_BURSTLEN0_bp 0 /* Channel Transfer Mode bit 0 position. */ -#define DMA_CH_BURSTLEN1_bm (1<<1) /* Channel Transfer Mode bit 1 mask. */ -#define DMA_CH_BURSTLEN1_bp 1 /* Channel Transfer Mode bit 1 position. */ - - -/* DMA_CH.CTRLB bit masks and bit positions */ -#define DMA_CH_CHBUSY_bm 0x80 /* Block Transfer Busy bit mask. */ -#define DMA_CH_CHBUSY_bp 7 /* Block Transfer Busy bit position. */ - -#define DMA_CH_CHPEND_bm 0x40 /* Block Transfer Pending bit mask. */ -#define DMA_CH_CHPEND_bp 6 /* Block Transfer Pending bit position. */ - -#define DMA_CH_ERRIF_bm 0x20 /* Block Transfer Error Interrupt Flag bit mask. */ -#define DMA_CH_ERRIF_bp 5 /* Block Transfer Error Interrupt Flag bit position. */ - -#define DMA_CH_TRNIF_bm 0x10 /* Transaction Complete Interrup Flag bit mask. */ -#define DMA_CH_TRNIF_bp 4 /* Transaction Complete Interrup Flag bit position. */ - -#define DMA_CH_ERRINTLVL_gm 0x0C /* Transfer Error Interrupt Level group mask. */ -#define DMA_CH_ERRINTLVL_gp 2 /* Transfer Error Interrupt Level group position. */ -#define DMA_CH_ERRINTLVL0_bm (1<<2) /* Transfer Error Interrupt Level bit 0 mask. */ -#define DMA_CH_ERRINTLVL0_bp 2 /* Transfer Error Interrupt Level bit 0 position. */ -#define DMA_CH_ERRINTLVL1_bm (1<<3) /* Transfer Error Interrupt Level bit 1 mask. */ -#define DMA_CH_ERRINTLVL1_bp 3 /* Transfer Error Interrupt Level bit 1 position. */ - -#define DMA_CH_TRNINTLVL_gm 0x03 /* Transaction Complete Interrupt Level group mask. */ -#define DMA_CH_TRNINTLVL_gp 0 /* Transaction Complete Interrupt Level group position. */ -#define DMA_CH_TRNINTLVL0_bm (1<<0) /* Transaction Complete Interrupt Level bit 0 mask. */ -#define DMA_CH_TRNINTLVL0_bp 0 /* Transaction Complete Interrupt Level bit 0 position. */ -#define DMA_CH_TRNINTLVL1_bm (1<<1) /* Transaction Complete Interrupt Level bit 1 mask. */ -#define DMA_CH_TRNINTLVL1_bp 1 /* Transaction Complete Interrupt Level bit 1 position. */ - - -/* DMA_CH.ADDRCTRL bit masks and bit positions */ -#define DMA_CH_SRCRELOAD_gm 0xC0 /* Channel Source Address Reload group mask. */ -#define DMA_CH_SRCRELOAD_gp 6 /* Channel Source Address Reload group position. */ -#define DMA_CH_SRCRELOAD0_bm (1<<6) /* Channel Source Address Reload bit 0 mask. */ -#define DMA_CH_SRCRELOAD0_bp 6 /* Channel Source Address Reload bit 0 position. */ -#define DMA_CH_SRCRELOAD1_bm (1<<7) /* Channel Source Address Reload bit 1 mask. */ -#define DMA_CH_SRCRELOAD1_bp 7 /* Channel Source Address Reload bit 1 position. */ - -#define DMA_CH_SRCDIR_gm 0x30 /* Channel Source Address Mode group mask. */ -#define DMA_CH_SRCDIR_gp 4 /* Channel Source Address Mode group position. */ -#define DMA_CH_SRCDIR0_bm (1<<4) /* Channel Source Address Mode bit 0 mask. */ -#define DMA_CH_SRCDIR0_bp 4 /* Channel Source Address Mode bit 0 position. */ -#define DMA_CH_SRCDIR1_bm (1<<5) /* Channel Source Address Mode bit 1 mask. */ -#define DMA_CH_SRCDIR1_bp 5 /* Channel Source Address Mode bit 1 position. */ - -#define DMA_CH_DESTRELOAD_gm 0x0C /* Channel Destination Address Reload group mask. */ -#define DMA_CH_DESTRELOAD_gp 2 /* Channel Destination Address Reload group position. */ -#define DMA_CH_DESTRELOAD0_bm (1<<2) /* Channel Destination Address Reload bit 0 mask. */ -#define DMA_CH_DESTRELOAD0_bp 2 /* Channel Destination Address Reload bit 0 position. */ -#define DMA_CH_DESTRELOAD1_bm (1<<3) /* Channel Destination Address Reload bit 1 mask. */ -#define DMA_CH_DESTRELOAD1_bp 3 /* Channel Destination Address Reload bit 1 position. */ - -#define DMA_CH_DESTDIR_gm 0x03 /* Channel Destination Address Mode group mask. */ -#define DMA_CH_DESTDIR_gp 0 /* Channel Destination Address Mode group position. */ -#define DMA_CH_DESTDIR0_bm (1<<0) /* Channel Destination Address Mode bit 0 mask. */ -#define DMA_CH_DESTDIR0_bp 0 /* Channel Destination Address Mode bit 0 position. */ -#define DMA_CH_DESTDIR1_bm (1<<1) /* Channel Destination Address Mode bit 1 mask. */ -#define DMA_CH_DESTDIR1_bp 1 /* Channel Destination Address Mode bit 1 position. */ - - -/* DMA_CH.TRIGSRC bit masks and bit positions */ -#define DMA_CH_TRIGSRC_gm 0xFF /* Channel Trigger Source group mask. */ -#define DMA_CH_TRIGSRC_gp 0 /* Channel Trigger Source group position. */ -#define DMA_CH_TRIGSRC0_bm (1<<0) /* Channel Trigger Source bit 0 mask. */ -#define DMA_CH_TRIGSRC0_bp 0 /* Channel Trigger Source bit 0 position. */ -#define DMA_CH_TRIGSRC1_bm (1<<1) /* Channel Trigger Source bit 1 mask. */ -#define DMA_CH_TRIGSRC1_bp 1 /* Channel Trigger Source bit 1 position. */ -#define DMA_CH_TRIGSRC2_bm (1<<2) /* Channel Trigger Source bit 2 mask. */ -#define DMA_CH_TRIGSRC2_bp 2 /* Channel Trigger Source bit 2 position. */ -#define DMA_CH_TRIGSRC3_bm (1<<3) /* Channel Trigger Source bit 3 mask. */ -#define DMA_CH_TRIGSRC3_bp 3 /* Channel Trigger Source bit 3 position. */ -#define DMA_CH_TRIGSRC4_bm (1<<4) /* Channel Trigger Source bit 4 mask. */ -#define DMA_CH_TRIGSRC4_bp 4 /* Channel Trigger Source bit 4 position. */ -#define DMA_CH_TRIGSRC5_bm (1<<5) /* Channel Trigger Source bit 5 mask. */ -#define DMA_CH_TRIGSRC5_bp 5 /* Channel Trigger Source bit 5 position. */ -#define DMA_CH_TRIGSRC6_bm (1<<6) /* Channel Trigger Source bit 6 mask. */ -#define DMA_CH_TRIGSRC6_bp 6 /* Channel Trigger Source bit 6 position. */ -#define DMA_CH_TRIGSRC7_bm (1<<7) /* Channel Trigger Source bit 7 mask. */ -#define DMA_CH_TRIGSRC7_bp 7 /* Channel Trigger Source bit 7 position. */ - - -/* DMA.CTRL bit masks and bit positions */ -#define DMA_ENABLE_bm 0x80 /* Enable bit mask. */ -#define DMA_ENABLE_bp 7 /* Enable bit position. */ - -#define DMA_RESET_bm 0x40 /* Software Reset bit mask. */ -#define DMA_RESET_bp 6 /* Software Reset bit position. */ - -#define DMA_DBUFMODE_gm 0x0C /* Double Buffering Mode group mask. */ -#define DMA_DBUFMODE_gp 2 /* Double Buffering Mode group position. */ -#define DMA_DBUFMODE0_bm (1<<2) /* Double Buffering Mode bit 0 mask. */ -#define DMA_DBUFMODE0_bp 2 /* Double Buffering Mode bit 0 position. */ -#define DMA_DBUFMODE1_bm (1<<3) /* Double Buffering Mode bit 1 mask. */ -#define DMA_DBUFMODE1_bp 3 /* Double Buffering Mode bit 1 position. */ - -#define DMA_PRIMODE_gm 0x03 /* Channel Priority Mode group mask. */ -#define DMA_PRIMODE_gp 0 /* Channel Priority Mode group position. */ -#define DMA_PRIMODE0_bm (1<<0) /* Channel Priority Mode bit 0 mask. */ -#define DMA_PRIMODE0_bp 0 /* Channel Priority Mode bit 0 position. */ -#define DMA_PRIMODE1_bm (1<<1) /* Channel Priority Mode bit 1 mask. */ -#define DMA_PRIMODE1_bp 1 /* Channel Priority Mode bit 1 position. */ - - -/* DMA.INTFLAGS bit masks and bit positions */ -#define DMA_CH3ERRIF_bm 0x80 /* Channel 3 Block Transfer Error Interrupt Flag bit mask. */ -#define DMA_CH3ERRIF_bp 7 /* Channel 3 Block Transfer Error Interrupt Flag bit position. */ - -#define DMA_CH2ERRIF_bm 0x40 /* Channel 2 Block Transfer Error Interrupt Flag bit mask. */ -#define DMA_CH2ERRIF_bp 6 /* Channel 2 Block Transfer Error Interrupt Flag bit position. */ - -#define DMA_CH1ERRIF_bm 0x20 /* Channel 1 Block Transfer Error Interrupt Flag bit mask. */ -#define DMA_CH1ERRIF_bp 5 /* Channel 1 Block Transfer Error Interrupt Flag bit position. */ - -#define DMA_CH0ERRIF_bm 0x10 /* Channel 0 Block Transfer Error Interrupt Flag bit mask. */ -#define DMA_CH0ERRIF_bp 4 /* Channel 0 Block Transfer Error Interrupt Flag bit position. */ - -#define DMA_CH3TRNIF_bm 0x08 /* Channel 3 Transaction Complete Interrupt Flag bit mask. */ -#define DMA_CH3TRNIF_bp 3 /* Channel 3 Transaction Complete Interrupt Flag bit position. */ - -#define DMA_CH2TRNIF_bm 0x04 /* Channel 2 Transaction Complete Interrupt Flag bit mask. */ -#define DMA_CH2TRNIF_bp 2 /* Channel 2 Transaction Complete Interrupt Flag bit position. */ - -#define DMA_CH1TRNIF_bm 0x02 /* Channel 1 Transaction Complete Interrupt Flag bit mask. */ -#define DMA_CH1TRNIF_bp 1 /* Channel 1 Transaction Complete Interrupt Flag bit position. */ - -#define DMA_CH0TRNIF_bm 0x01 /* Channel 0 Transaction Complete Interrupt Flag bit mask. */ -#define DMA_CH0TRNIF_bp 0 /* Channel 0 Transaction Complete Interrupt Flag bit position. */ - - -/* DMA.STATUS bit masks and bit positions */ -#define DMA_CH3BUSY_bm 0x80 /* Channel 3 Block Transfer Busy bit mask. */ -#define DMA_CH3BUSY_bp 7 /* Channel 3 Block Transfer Busy bit position. */ - -#define DMA_CH2BUSY_bm 0x40 /* Channel 2 Block Transfer Busy bit mask. */ -#define DMA_CH2BUSY_bp 6 /* Channel 2 Block Transfer Busy bit position. */ - -#define DMA_CH1BUSY_bm 0x20 /* Channel 1 Block Transfer Busy bit mask. */ -#define DMA_CH1BUSY_bp 5 /* Channel 1 Block Transfer Busy bit position. */ - -#define DMA_CH0BUSY_bm 0x10 /* Channel 0 Block Transfer Busy bit mask. */ -#define DMA_CH0BUSY_bp 4 /* Channel 0 Block Transfer Busy bit position. */ - -#define DMA_CH3PEND_bm 0x08 /* Channel 3 Block Transfer Pending bit mask. */ -#define DMA_CH3PEND_bp 3 /* Channel 3 Block Transfer Pending bit position. */ - -#define DMA_CH2PEND_bm 0x04 /* Channel 2 Block Transfer Pending bit mask. */ -#define DMA_CH2PEND_bp 2 /* Channel 2 Block Transfer Pending bit position. */ - -#define DMA_CH1PEND_bm 0x02 /* Channel 1 Block Transfer Pending bit mask. */ -#define DMA_CH1PEND_bp 1 /* Channel 1 Block Transfer Pending bit position. */ - -#define DMA_CH0PEND_bm 0x01 /* Channel 0 Block Transfer Pending bit mask. */ -#define DMA_CH0PEND_bp 0 /* Channel 0 Block Transfer Pending bit position. */ - - -/* EVSYS - Event System */ -/* EVSYS.CH0MUX bit masks and bit positions */ -#define EVSYS_CHMUX_gm 0xFF /* Event Channel 0 Multiplexer group mask. */ -#define EVSYS_CHMUX_gp 0 /* Event Channel 0 Multiplexer group position. */ -#define EVSYS_CHMUX0_bm (1<<0) /* Event Channel 0 Multiplexer bit 0 mask. */ -#define EVSYS_CHMUX0_bp 0 /* Event Channel 0 Multiplexer bit 0 position. */ -#define EVSYS_CHMUX1_bm (1<<1) /* Event Channel 0 Multiplexer bit 1 mask. */ -#define EVSYS_CHMUX1_bp 1 /* Event Channel 0 Multiplexer bit 1 position. */ -#define EVSYS_CHMUX2_bm (1<<2) /* Event Channel 0 Multiplexer bit 2 mask. */ -#define EVSYS_CHMUX2_bp 2 /* Event Channel 0 Multiplexer bit 2 position. */ -#define EVSYS_CHMUX3_bm (1<<3) /* Event Channel 0 Multiplexer bit 3 mask. */ -#define EVSYS_CHMUX3_bp 3 /* Event Channel 0 Multiplexer bit 3 position. */ -#define EVSYS_CHMUX4_bm (1<<4) /* Event Channel 0 Multiplexer bit 4 mask. */ -#define EVSYS_CHMUX4_bp 4 /* Event Channel 0 Multiplexer bit 4 position. */ -#define EVSYS_CHMUX5_bm (1<<5) /* Event Channel 0 Multiplexer bit 5 mask. */ -#define EVSYS_CHMUX5_bp 5 /* Event Channel 0 Multiplexer bit 5 position. */ -#define EVSYS_CHMUX6_bm (1<<6) /* Event Channel 0 Multiplexer bit 6 mask. */ -#define EVSYS_CHMUX6_bp 6 /* Event Channel 0 Multiplexer bit 6 position. */ -#define EVSYS_CHMUX7_bm (1<<7) /* Event Channel 0 Multiplexer bit 7 mask. */ -#define EVSYS_CHMUX7_bp 7 /* Event Channel 0 Multiplexer bit 7 position. */ - - -/* EVSYS.CH1MUX bit masks and bit positions */ -/* EVSYS_CHMUX_gm Predefined. */ -/* EVSYS_CHMUX_gp Predefined. */ -/* EVSYS_CHMUX0_bm Predefined. */ -/* EVSYS_CHMUX0_bp Predefined. */ -/* EVSYS_CHMUX1_bm Predefined. */ -/* EVSYS_CHMUX1_bp Predefined. */ -/* EVSYS_CHMUX2_bm Predefined. */ -/* EVSYS_CHMUX2_bp Predefined. */ -/* EVSYS_CHMUX3_bm Predefined. */ -/* EVSYS_CHMUX3_bp Predefined. */ -/* EVSYS_CHMUX4_bm Predefined. */ -/* EVSYS_CHMUX4_bp Predefined. */ -/* EVSYS_CHMUX5_bm Predefined. */ -/* EVSYS_CHMUX5_bp Predefined. */ -/* EVSYS_CHMUX6_bm Predefined. */ -/* EVSYS_CHMUX6_bp Predefined. */ -/* EVSYS_CHMUX7_bm Predefined. */ -/* EVSYS_CHMUX7_bp Predefined. */ - - -/* EVSYS.CH2MUX bit masks and bit positions */ -/* EVSYS_CHMUX_gm Predefined. */ -/* EVSYS_CHMUX_gp Predefined. */ -/* EVSYS_CHMUX0_bm Predefined. */ -/* EVSYS_CHMUX0_bp Predefined. */ -/* EVSYS_CHMUX1_bm Predefined. */ -/* EVSYS_CHMUX1_bp Predefined. */ -/* EVSYS_CHMUX2_bm Predefined. */ -/* EVSYS_CHMUX2_bp Predefined. */ -/* EVSYS_CHMUX3_bm Predefined. */ -/* EVSYS_CHMUX3_bp Predefined. */ -/* EVSYS_CHMUX4_bm Predefined. */ -/* EVSYS_CHMUX4_bp Predefined. */ -/* EVSYS_CHMUX5_bm Predefined. */ -/* EVSYS_CHMUX5_bp Predefined. */ -/* EVSYS_CHMUX6_bm Predefined. */ -/* EVSYS_CHMUX6_bp Predefined. */ -/* EVSYS_CHMUX7_bm Predefined. */ -/* EVSYS_CHMUX7_bp Predefined. */ - - -/* EVSYS.CH3MUX bit masks and bit positions */ -/* EVSYS_CHMUX_gm Predefined. */ -/* EVSYS_CHMUX_gp Predefined. */ -/* EVSYS_CHMUX0_bm Predefined. */ -/* EVSYS_CHMUX0_bp Predefined. */ -/* EVSYS_CHMUX1_bm Predefined. */ -/* EVSYS_CHMUX1_bp Predefined. */ -/* EVSYS_CHMUX2_bm Predefined. */ -/* EVSYS_CHMUX2_bp Predefined. */ -/* EVSYS_CHMUX3_bm Predefined. */ -/* EVSYS_CHMUX3_bp Predefined. */ -/* EVSYS_CHMUX4_bm Predefined. */ -/* EVSYS_CHMUX4_bp Predefined. */ -/* EVSYS_CHMUX5_bm Predefined. */ -/* EVSYS_CHMUX5_bp Predefined. */ -/* EVSYS_CHMUX6_bm Predefined. */ -/* EVSYS_CHMUX6_bp Predefined. */ -/* EVSYS_CHMUX7_bm Predefined. */ -/* EVSYS_CHMUX7_bp Predefined. */ - - -/* EVSYS.CH4MUX bit masks and bit positions */ -/* EVSYS_CHMUX_gm Predefined. */ -/* EVSYS_CHMUX_gp Predefined. */ -/* EVSYS_CHMUX0_bm Predefined. */ -/* EVSYS_CHMUX0_bp Predefined. */ -/* EVSYS_CHMUX1_bm Predefined. */ -/* EVSYS_CHMUX1_bp Predefined. */ -/* EVSYS_CHMUX2_bm Predefined. */ -/* EVSYS_CHMUX2_bp Predefined. */ -/* EVSYS_CHMUX3_bm Predefined. */ -/* EVSYS_CHMUX3_bp Predefined. */ -/* EVSYS_CHMUX4_bm Predefined. */ -/* EVSYS_CHMUX4_bp Predefined. */ -/* EVSYS_CHMUX5_bm Predefined. */ -/* EVSYS_CHMUX5_bp Predefined. */ -/* EVSYS_CHMUX6_bm Predefined. */ -/* EVSYS_CHMUX6_bp Predefined. */ -/* EVSYS_CHMUX7_bm Predefined. */ -/* EVSYS_CHMUX7_bp Predefined. */ - - -/* EVSYS.CH5MUX bit masks and bit positions */ -/* EVSYS_CHMUX_gm Predefined. */ -/* EVSYS_CHMUX_gp Predefined. */ -/* EVSYS_CHMUX0_bm Predefined. */ -/* EVSYS_CHMUX0_bp Predefined. */ -/* EVSYS_CHMUX1_bm Predefined. */ -/* EVSYS_CHMUX1_bp Predefined. */ -/* EVSYS_CHMUX2_bm Predefined. */ -/* EVSYS_CHMUX2_bp Predefined. */ -/* EVSYS_CHMUX3_bm Predefined. */ -/* EVSYS_CHMUX3_bp Predefined. */ -/* EVSYS_CHMUX4_bm Predefined. */ -/* EVSYS_CHMUX4_bp Predefined. */ -/* EVSYS_CHMUX5_bm Predefined. */ -/* EVSYS_CHMUX5_bp Predefined. */ -/* EVSYS_CHMUX6_bm Predefined. */ -/* EVSYS_CHMUX6_bp Predefined. */ -/* EVSYS_CHMUX7_bm Predefined. */ -/* EVSYS_CHMUX7_bp Predefined. */ - - -/* EVSYS.CH6MUX bit masks and bit positions */ -/* EVSYS_CHMUX_gm Predefined. */ -/* EVSYS_CHMUX_gp Predefined. */ -/* EVSYS_CHMUX0_bm Predefined. */ -/* EVSYS_CHMUX0_bp Predefined. */ -/* EVSYS_CHMUX1_bm Predefined. */ -/* EVSYS_CHMUX1_bp Predefined. */ -/* EVSYS_CHMUX2_bm Predefined. */ -/* EVSYS_CHMUX2_bp Predefined. */ -/* EVSYS_CHMUX3_bm Predefined. */ -/* EVSYS_CHMUX3_bp Predefined. */ -/* EVSYS_CHMUX4_bm Predefined. */ -/* EVSYS_CHMUX4_bp Predefined. */ -/* EVSYS_CHMUX5_bm Predefined. */ -/* EVSYS_CHMUX5_bp Predefined. */ -/* EVSYS_CHMUX6_bm Predefined. */ -/* EVSYS_CHMUX6_bp Predefined. */ -/* EVSYS_CHMUX7_bm Predefined. */ -/* EVSYS_CHMUX7_bp Predefined. */ - - -/* EVSYS.CH7MUX bit masks and bit positions */ -/* EVSYS_CHMUX_gm Predefined. */ -/* EVSYS_CHMUX_gp Predefined. */ -/* EVSYS_CHMUX0_bm Predefined. */ -/* EVSYS_CHMUX0_bp Predefined. */ -/* EVSYS_CHMUX1_bm Predefined. */ -/* EVSYS_CHMUX1_bp Predefined. */ -/* EVSYS_CHMUX2_bm Predefined. */ -/* EVSYS_CHMUX2_bp Predefined. */ -/* EVSYS_CHMUX3_bm Predefined. */ -/* EVSYS_CHMUX3_bp Predefined. */ -/* EVSYS_CHMUX4_bm Predefined. */ -/* EVSYS_CHMUX4_bp Predefined. */ -/* EVSYS_CHMUX5_bm Predefined. */ -/* EVSYS_CHMUX5_bp Predefined. */ -/* EVSYS_CHMUX6_bm Predefined. */ -/* EVSYS_CHMUX6_bp Predefined. */ -/* EVSYS_CHMUX7_bm Predefined. */ -/* EVSYS_CHMUX7_bp Predefined. */ - - -/* EVSYS.CH0CTRL bit masks and bit positions */ -#define EVSYS_QDIRM_gm 0x60 /* Quadrature Decoder Index Recognition Mode group mask. */ -#define EVSYS_QDIRM_gp 5 /* Quadrature Decoder Index Recognition Mode group position. */ -#define EVSYS_QDIRM0_bm (1<<5) /* Quadrature Decoder Index Recognition Mode bit 0 mask. */ -#define EVSYS_QDIRM0_bp 5 /* Quadrature Decoder Index Recognition Mode bit 0 position. */ -#define EVSYS_QDIRM1_bm (1<<6) /* Quadrature Decoder Index Recognition Mode bit 1 mask. */ -#define EVSYS_QDIRM1_bp 6 /* Quadrature Decoder Index Recognition Mode bit 1 position. */ - -#define EVSYS_QDIEN_bm 0x10 /* Quadrature Decoder Index Enable bit mask. */ -#define EVSYS_QDIEN_bp 4 /* Quadrature Decoder Index Enable bit position. */ - -#define EVSYS_QDEN_bm 0x08 /* Quadrature Decoder Enable bit mask. */ -#define EVSYS_QDEN_bp 3 /* Quadrature Decoder Enable bit position. */ - -#define EVSYS_DIGFILT_gm 0x07 /* Digital Filter group mask. */ -#define EVSYS_DIGFILT_gp 0 /* Digital Filter group position. */ -#define EVSYS_DIGFILT0_bm (1<<0) /* Digital Filter bit 0 mask. */ -#define EVSYS_DIGFILT0_bp 0 /* Digital Filter bit 0 position. */ -#define EVSYS_DIGFILT1_bm (1<<1) /* Digital Filter bit 1 mask. */ -#define EVSYS_DIGFILT1_bp 1 /* Digital Filter bit 1 position. */ -#define EVSYS_DIGFILT2_bm (1<<2) /* Digital Filter bit 2 mask. */ -#define EVSYS_DIGFILT2_bp 2 /* Digital Filter bit 2 position. */ - - -/* EVSYS.CH1CTRL bit masks and bit positions */ -/* EVSYS_DIGFILT_gm Predefined. */ -/* EVSYS_DIGFILT_gp Predefined. */ -/* EVSYS_DIGFILT0_bm Predefined. */ -/* EVSYS_DIGFILT0_bp Predefined. */ -/* EVSYS_DIGFILT1_bm Predefined. */ -/* EVSYS_DIGFILT1_bp Predefined. */ -/* EVSYS_DIGFILT2_bm Predefined. */ -/* EVSYS_DIGFILT2_bp Predefined. */ - - -/* EVSYS.CH2CTRL bit masks and bit positions */ -/* EVSYS_QDIRM_gm Predefined. */ -/* EVSYS_QDIRM_gp Predefined. */ -/* EVSYS_QDIRM0_bm Predefined. */ -/* EVSYS_QDIRM0_bp Predefined. */ -/* EVSYS_QDIRM1_bm Predefined. */ -/* EVSYS_QDIRM1_bp Predefined. */ - -/* EVSYS_QDIEN_bm Predefined. */ -/* EVSYS_QDIEN_bp Predefined. */ - -/* EVSYS_QDEN_bm Predefined. */ -/* EVSYS_QDEN_bp Predefined. */ - -/* EVSYS_DIGFILT_gm Predefined. */ -/* EVSYS_DIGFILT_gp Predefined. */ -/* EVSYS_DIGFILT0_bm Predefined. */ -/* EVSYS_DIGFILT0_bp Predefined. */ -/* EVSYS_DIGFILT1_bm Predefined. */ -/* EVSYS_DIGFILT1_bp Predefined. */ -/* EVSYS_DIGFILT2_bm Predefined. */ -/* EVSYS_DIGFILT2_bp Predefined. */ - - -/* EVSYS.CH3CTRL bit masks and bit positions */ -/* EVSYS_DIGFILT_gm Predefined. */ -/* EVSYS_DIGFILT_gp Predefined. */ -/* EVSYS_DIGFILT0_bm Predefined. */ -/* EVSYS_DIGFILT0_bp Predefined. */ -/* EVSYS_DIGFILT1_bm Predefined. */ -/* EVSYS_DIGFILT1_bp Predefined. */ -/* EVSYS_DIGFILT2_bm Predefined. */ -/* EVSYS_DIGFILT2_bp Predefined. */ - - -/* EVSYS.CH4CTRL bit masks and bit positions */ -/* EVSYS_QDIRM_gm Predefined. */ -/* EVSYS_QDIRM_gp Predefined. */ -/* EVSYS_QDIRM0_bm Predefined. */ -/* EVSYS_QDIRM0_bp Predefined. */ -/* EVSYS_QDIRM1_bm Predefined. */ -/* EVSYS_QDIRM1_bp Predefined. */ - -/* EVSYS_QDIEN_bm Predefined. */ -/* EVSYS_QDIEN_bp Predefined. */ - -/* EVSYS_QDEN_bm Predefined. */ -/* EVSYS_QDEN_bp Predefined. */ - -/* EVSYS_DIGFILT_gm Predefined. */ -/* EVSYS_DIGFILT_gp Predefined. */ -/* EVSYS_DIGFILT0_bm Predefined. */ -/* EVSYS_DIGFILT0_bp Predefined. */ -/* EVSYS_DIGFILT1_bm Predefined. */ -/* EVSYS_DIGFILT1_bp Predefined. */ -/* EVSYS_DIGFILT2_bm Predefined. */ -/* EVSYS_DIGFILT2_bp Predefined. */ - - -/* EVSYS.CH5CTRL bit masks and bit positions */ -/* EVSYS_DIGFILT_gm Predefined. */ -/* EVSYS_DIGFILT_gp Predefined. */ -/* EVSYS_DIGFILT0_bm Predefined. */ -/* EVSYS_DIGFILT0_bp Predefined. */ -/* EVSYS_DIGFILT1_bm Predefined. */ -/* EVSYS_DIGFILT1_bp Predefined. */ -/* EVSYS_DIGFILT2_bm Predefined. */ -/* EVSYS_DIGFILT2_bp Predefined. */ - - -/* EVSYS.CH6CTRL bit masks and bit positions */ -/* EVSYS_DIGFILT_gm Predefined. */ -/* EVSYS_DIGFILT_gp Predefined. */ -/* EVSYS_DIGFILT0_bm Predefined. */ -/* EVSYS_DIGFILT0_bp Predefined. */ -/* EVSYS_DIGFILT1_bm Predefined. */ -/* EVSYS_DIGFILT1_bp Predefined. */ -/* EVSYS_DIGFILT2_bm Predefined. */ -/* EVSYS_DIGFILT2_bp Predefined. */ - - -/* EVSYS.CH7CTRL bit masks and bit positions */ -/* EVSYS_DIGFILT_gm Predefined. */ -/* EVSYS_DIGFILT_gp Predefined. */ -/* EVSYS_DIGFILT0_bm Predefined. */ -/* EVSYS_DIGFILT0_bp Predefined. */ -/* EVSYS_DIGFILT1_bm Predefined. */ -/* EVSYS_DIGFILT1_bp Predefined. */ -/* EVSYS_DIGFILT2_bm Predefined. */ -/* EVSYS_DIGFILT2_bp Predefined. */ - - -/* NVM - Non Volatile Memory Controller */ -/* NVM.CMD bit masks and bit positions */ -#define NVM_CMD_gm 0xFF /* Command group mask. */ -#define NVM_CMD_gp 0 /* Command group position. */ -#define NVM_CMD0_bm (1<<0) /* Command bit 0 mask. */ -#define NVM_CMD0_bp 0 /* Command bit 0 position. */ -#define NVM_CMD1_bm (1<<1) /* Command bit 1 mask. */ -#define NVM_CMD1_bp 1 /* Command bit 1 position. */ -#define NVM_CMD2_bm (1<<2) /* Command bit 2 mask. */ -#define NVM_CMD2_bp 2 /* Command bit 2 position. */ -#define NVM_CMD3_bm (1<<3) /* Command bit 3 mask. */ -#define NVM_CMD3_bp 3 /* Command bit 3 position. */ -#define NVM_CMD4_bm (1<<4) /* Command bit 4 mask. */ -#define NVM_CMD4_bp 4 /* Command bit 4 position. */ -#define NVM_CMD5_bm (1<<5) /* Command bit 5 mask. */ -#define NVM_CMD5_bp 5 /* Command bit 5 position. */ -#define NVM_CMD6_bm (1<<6) /* Command bit 6 mask. */ -#define NVM_CMD6_bp 6 /* Command bit 6 position. */ -#define NVM_CMD7_bm (1<<7) /* Command bit 7 mask. */ -#define NVM_CMD7_bp 7 /* Command bit 7 position. */ - - -/* NVM.CTRLA bit masks and bit positions */ -#define NVM_CMDEX_bm 0x01 /* Command Execute bit mask. */ -#define NVM_CMDEX_bp 0 /* Command Execute bit position. */ - - -/* NVM.CTRLB bit masks and bit positions */ -#define NVM_EEMAPEN_bm 0x08 /* EEPROM Mapping Enable bit mask. */ -#define NVM_EEMAPEN_bp 3 /* EEPROM Mapping Enable bit position. */ - -#define NVM_FPRM_bm 0x04 /* Flash Power Reduction Enable bit mask. */ -#define NVM_FPRM_bp 2 /* Flash Power Reduction Enable bit position. */ - -#define NVM_EPRM_bm 0x02 /* EEPROM Power Reduction Enable bit mask. */ -#define NVM_EPRM_bp 1 /* EEPROM Power Reduction Enable bit position. */ - -#define NVM_SPMLOCK_bm 0x01 /* SPM Lock bit mask. */ -#define NVM_SPMLOCK_bp 0 /* SPM Lock bit position. */ - - -/* NVM.INTCTRL bit masks and bit positions */ -#define NVM_SPMLVL_gm 0x0C /* SPM Interrupt Level group mask. */ -#define NVM_SPMLVL_gp 2 /* SPM Interrupt Level group position. */ -#define NVM_SPMLVL0_bm (1<<2) /* SPM Interrupt Level bit 0 mask. */ -#define NVM_SPMLVL0_bp 2 /* SPM Interrupt Level bit 0 position. */ -#define NVM_SPMLVL1_bm (1<<3) /* SPM Interrupt Level bit 1 mask. */ -#define NVM_SPMLVL1_bp 3 /* SPM Interrupt Level bit 1 position. */ - -#define NVM_EELVL_gm 0x03 /* EEPROM Interrupt Level group mask. */ -#define NVM_EELVL_gp 0 /* EEPROM Interrupt Level group position. */ -#define NVM_EELVL0_bm (1<<0) /* EEPROM Interrupt Level bit 0 mask. */ -#define NVM_EELVL0_bp 0 /* EEPROM Interrupt Level bit 0 position. */ -#define NVM_EELVL1_bm (1<<1) /* EEPROM Interrupt Level bit 1 mask. */ -#define NVM_EELVL1_bp 1 /* EEPROM Interrupt Level bit 1 position. */ - - -/* NVM.STATUS bit masks and bit positions */ -#define NVM_NVMBUSY_bm 0x80 /* Non-volatile Memory Busy bit mask. */ -#define NVM_NVMBUSY_bp 7 /* Non-volatile Memory Busy bit position. */ - -#define NVM_FBUSY_bm 0x40 /* Flash Memory Busy bit mask. */ -#define NVM_FBUSY_bp 6 /* Flash Memory Busy bit position. */ - -#define NVM_EELOAD_bm 0x02 /* EEPROM Page Buffer Active Loading bit mask. */ -#define NVM_EELOAD_bp 1 /* EEPROM Page Buffer Active Loading bit position. */ - -#define NVM_FLOAD_bm 0x01 /* Flash Page Buffer Active Loading bit mask. */ -#define NVM_FLOAD_bp 0 /* Flash Page Buffer Active Loading bit position. */ - - -/* NVM.LOCKBITS bit masks and bit positions */ -#define NVM_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ -#define NVM_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ -#define NVM_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ -#define NVM_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ -#define NVM_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ -#define NVM_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ - -#define NVM_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ -#define NVM_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ -#define NVM_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ -#define NVM_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ -#define NVM_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ -#define NVM_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ - -#define NVM_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ -#define NVM_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ -#define NVM_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ -#define NVM_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ -#define NVM_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ -#define NVM_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ - -#define NVM_LB_gm 0x03 /* Lock Bits group mask. */ -#define NVM_LB_gp 0 /* Lock Bits group position. */ -#define NVM_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ -#define NVM_LB0_bp 0 /* Lock Bits bit 0 position. */ -#define NVM_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ -#define NVM_LB1_bp 1 /* Lock Bits bit 1 position. */ - - -/* NVM_LOCKBITS.LOCKBITS bit masks and bit positions */ -#define NVM_LOCKBITS_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ -#define NVM_LOCKBITS_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ -#define NVM_LOCKBITS_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ -#define NVM_LOCKBITS_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ -#define NVM_LOCKBITS_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ -#define NVM_LOCKBITS_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ - -#define NVM_LOCKBITS_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ -#define NVM_LOCKBITS_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ -#define NVM_LOCKBITS_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ -#define NVM_LOCKBITS_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ -#define NVM_LOCKBITS_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ -#define NVM_LOCKBITS_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ - -#define NVM_LOCKBITS_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ -#define NVM_LOCKBITS_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ -#define NVM_LOCKBITS_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ -#define NVM_LOCKBITS_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ -#define NVM_LOCKBITS_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ -#define NVM_LOCKBITS_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ - -#define NVM_LOCKBITS_LB_gm 0x03 /* Lock Bits group mask. */ -#define NVM_LOCKBITS_LB_gp 0 /* Lock Bits group position. */ -#define NVM_LOCKBITS_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ -#define NVM_LOCKBITS_LB0_bp 0 /* Lock Bits bit 0 position. */ -#define NVM_LOCKBITS_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ -#define NVM_LOCKBITS_LB1_bp 1 /* Lock Bits bit 1 position. */ - - -/* NVM_FUSES.FUSEBYTE0 bit masks and bit positions */ -#define NVM_FUSES_JTAGUSERID_gm 0xFF /* JTAG User ID group mask. */ -#define NVM_FUSES_JTAGUSERID_gp 0 /* JTAG User ID group position. */ -#define NVM_FUSES_JTAGUSERID0_bm (1<<0) /* JTAG User ID bit 0 mask. */ -#define NVM_FUSES_JTAGUSERID0_bp 0 /* JTAG User ID bit 0 position. */ -#define NVM_FUSES_JTAGUSERID1_bm (1<<1) /* JTAG User ID bit 1 mask. */ -#define NVM_FUSES_JTAGUSERID1_bp 1 /* JTAG User ID bit 1 position. */ -#define NVM_FUSES_JTAGUSERID2_bm (1<<2) /* JTAG User ID bit 2 mask. */ -#define NVM_FUSES_JTAGUSERID2_bp 2 /* JTAG User ID bit 2 position. */ -#define NVM_FUSES_JTAGUSERID3_bm (1<<3) /* JTAG User ID bit 3 mask. */ -#define NVM_FUSES_JTAGUSERID3_bp 3 /* JTAG User ID bit 3 position. */ -#define NVM_FUSES_JTAGUSERID4_bm (1<<4) /* JTAG User ID bit 4 mask. */ -#define NVM_FUSES_JTAGUSERID4_bp 4 /* JTAG User ID bit 4 position. */ -#define NVM_FUSES_JTAGUSERID5_bm (1<<5) /* JTAG User ID bit 5 mask. */ -#define NVM_FUSES_JTAGUSERID5_bp 5 /* JTAG User ID bit 5 position. */ -#define NVM_FUSES_JTAGUSERID6_bm (1<<6) /* JTAG User ID bit 6 mask. */ -#define NVM_FUSES_JTAGUSERID6_bp 6 /* JTAG User ID bit 6 position. */ -#define NVM_FUSES_JTAGUSERID7_bm (1<<7) /* JTAG User ID bit 7 mask. */ -#define NVM_FUSES_JTAGUSERID7_bp 7 /* JTAG User ID bit 7 position. */ - - -/* NVM_FUSES.FUSEBYTE1 bit masks and bit positions */ -#define NVM_FUSES_WDWP_gm 0xF0 /* Watchdog Window Timeout Period group mask. */ -#define NVM_FUSES_WDWP_gp 4 /* Watchdog Window Timeout Period group position. */ -#define NVM_FUSES_WDWP0_bm (1<<4) /* Watchdog Window Timeout Period bit 0 mask. */ -#define NVM_FUSES_WDWP0_bp 4 /* Watchdog Window Timeout Period bit 0 position. */ -#define NVM_FUSES_WDWP1_bm (1<<5) /* Watchdog Window Timeout Period bit 1 mask. */ -#define NVM_FUSES_WDWP1_bp 5 /* Watchdog Window Timeout Period bit 1 position. */ -#define NVM_FUSES_WDWP2_bm (1<<6) /* Watchdog Window Timeout Period bit 2 mask. */ -#define NVM_FUSES_WDWP2_bp 6 /* Watchdog Window Timeout Period bit 2 position. */ -#define NVM_FUSES_WDWP3_bm (1<<7) /* Watchdog Window Timeout Period bit 3 mask. */ -#define NVM_FUSES_WDWP3_bp 7 /* Watchdog Window Timeout Period bit 3 position. */ - -#define NVM_FUSES_WDP_gm 0x0F /* Watchdog Timeout Period group mask. */ -#define NVM_FUSES_WDP_gp 0 /* Watchdog Timeout Period group position. */ -#define NVM_FUSES_WDP0_bm (1<<0) /* Watchdog Timeout Period bit 0 mask. */ -#define NVM_FUSES_WDP0_bp 0 /* Watchdog Timeout Period bit 0 position. */ -#define NVM_FUSES_WDP1_bm (1<<1) /* Watchdog Timeout Period bit 1 mask. */ -#define NVM_FUSES_WDP1_bp 1 /* Watchdog Timeout Period bit 1 position. */ -#define NVM_FUSES_WDP2_bm (1<<2) /* Watchdog Timeout Period bit 2 mask. */ -#define NVM_FUSES_WDP2_bp 2 /* Watchdog Timeout Period bit 2 position. */ -#define NVM_FUSES_WDP3_bm (1<<3) /* Watchdog Timeout Period bit 3 mask. */ -#define NVM_FUSES_WDP3_bp 3 /* Watchdog Timeout Period bit 3 position. */ - - -/* NVM_FUSES.FUSEBYTE2 bit masks and bit positions */ -#define NVM_FUSES_DVSDON_bm 0x80 /* Spike Detector Enable bit mask. */ -#define NVM_FUSES_DVSDON_bp 7 /* Spike Detector Enable bit position. */ - -#define NVM_FUSES_BOOTRST_bm 0x40 /* Boot Loader Section Reset Vector bit mask. */ -#define NVM_FUSES_BOOTRST_bp 6 /* Boot Loader Section Reset Vector bit position. */ - -#define NVM_FUSES_BODPD_gm 0x03 /* BOD Operation in Power-Down Mode group mask. */ -#define NVM_FUSES_BODPD_gp 0 /* BOD Operation in Power-Down Mode group position. */ -#define NVM_FUSES_BODPD0_bm (1<<0) /* BOD Operation in Power-Down Mode bit 0 mask. */ -#define NVM_FUSES_BODPD0_bp 0 /* BOD Operation in Power-Down Mode bit 0 position. */ -#define NVM_FUSES_BODPD1_bm (1<<1) /* BOD Operation in Power-Down Mode bit 1 mask. */ -#define NVM_FUSES_BODPD1_bp 1 /* BOD Operation in Power-Down Mode bit 1 position. */ - - -/* NVM_FUSES.FUSEBYTE4 bit masks and bit positions */ -#define NVM_FUSES_SUT_gm 0x0C /* Start-up Time group mask. */ -#define NVM_FUSES_SUT_gp 2 /* Start-up Time group position. */ -#define NVM_FUSES_SUT0_bm (1<<2) /* Start-up Time bit 0 mask. */ -#define NVM_FUSES_SUT0_bp 2 /* Start-up Time bit 0 position. */ -#define NVM_FUSES_SUT1_bm (1<<3) /* Start-up Time bit 1 mask. */ -#define NVM_FUSES_SUT1_bp 3 /* Start-up Time bit 1 position. */ - -#define NVM_FUSES_WDLOCK_bm 0x02 /* Watchdog Timer Lock bit mask. */ -#define NVM_FUSES_WDLOCK_bp 1 /* Watchdog Timer Lock bit position. */ - -#define NVM_FUSES_JTAGEN_bm 0x01 /* JTAG Interface Enable bit mask. */ -#define NVM_FUSES_JTAGEN_bp 0 /* JTAG Interface Enable bit position. */ - - -/* NVM_FUSES.FUSEBYTE5 bit masks and bit positions */ -#define NVM_FUSES_BODACT_gm 0x30 /* BOD Operation in Active Mode group mask. */ -#define NVM_FUSES_BODACT_gp 4 /* BOD Operation in Active Mode group position. */ -#define NVM_FUSES_BODACT0_bm (1<<4) /* BOD Operation in Active Mode bit 0 mask. */ -#define NVM_FUSES_BODACT0_bp 4 /* BOD Operation in Active Mode bit 0 position. */ -#define NVM_FUSES_BODACT1_bm (1<<5) /* BOD Operation in Active Mode bit 1 mask. */ -#define NVM_FUSES_BODACT1_bp 5 /* BOD Operation in Active Mode bit 1 position. */ - -#define NVM_FUSES_EESAVE_bm 0x08 /* Preserve EEPROM Through Chip Erase bit mask. */ -#define NVM_FUSES_EESAVE_bp 3 /* Preserve EEPROM Through Chip Erase bit position. */ - -#define NVM_FUSES_BODLVL_gm 0x07 /* Brown Out Detection Voltage Level group mask. */ -#define NVM_FUSES_BODLVL_gp 0 /* Brown Out Detection Voltage Level group position. */ -#define NVM_FUSES_BODLVL0_bm (1<<0) /* Brown Out Detection Voltage Level bit 0 mask. */ -#define NVM_FUSES_BODLVL0_bp 0 /* Brown Out Detection Voltage Level bit 0 position. */ -#define NVM_FUSES_BODLVL1_bm (1<<1) /* Brown Out Detection Voltage Level bit 1 mask. */ -#define NVM_FUSES_BODLVL1_bp 1 /* Brown Out Detection Voltage Level bit 1 position. */ -#define NVM_FUSES_BODLVL2_bm (1<<2) /* Brown Out Detection Voltage Level bit 2 mask. */ -#define NVM_FUSES_BODLVL2_bp 2 /* Brown Out Detection Voltage Level bit 2 position. */ - - -/* AC - Analog Comparator */ -/* AC.AC0CTRL bit masks and bit positions */ -#define AC_INTMODE_gm 0xC0 /* Interrupt Mode group mask. */ -#define AC_INTMODE_gp 6 /* Interrupt Mode group position. */ -#define AC_INTMODE0_bm (1<<6) /* Interrupt Mode bit 0 mask. */ -#define AC_INTMODE0_bp 6 /* Interrupt Mode bit 0 position. */ -#define AC_INTMODE1_bm (1<<7) /* Interrupt Mode bit 1 mask. */ -#define AC_INTMODE1_bp 7 /* Interrupt Mode bit 1 position. */ - -#define AC_INTLVL_gm 0x30 /* Interrupt Level group mask. */ -#define AC_INTLVL_gp 4 /* Interrupt Level group position. */ -#define AC_INTLVL0_bm (1<<4) /* Interrupt Level bit 0 mask. */ -#define AC_INTLVL0_bp 4 /* Interrupt Level bit 0 position. */ -#define AC_INTLVL1_bm (1<<5) /* Interrupt Level bit 1 mask. */ -#define AC_INTLVL1_bp 5 /* Interrupt Level bit 1 position. */ - -#define AC_HSMODE_bm 0x08 /* High-speed Mode bit mask. */ -#define AC_HSMODE_bp 3 /* High-speed Mode bit position. */ - -#define AC_HYSMODE_gm 0x06 /* Hysteresis Mode group mask. */ -#define AC_HYSMODE_gp 1 /* Hysteresis Mode group position. */ -#define AC_HYSMODE0_bm (1<<1) /* Hysteresis Mode bit 0 mask. */ -#define AC_HYSMODE0_bp 1 /* Hysteresis Mode bit 0 position. */ -#define AC_HYSMODE1_bm (1<<2) /* Hysteresis Mode bit 1 mask. */ -#define AC_HYSMODE1_bp 2 /* Hysteresis Mode bit 1 position. */ - -#define AC_ENABLE_bm 0x01 /* Enable bit mask. */ -#define AC_ENABLE_bp 0 /* Enable bit position. */ - - -/* AC.AC1CTRL bit masks and bit positions */ -/* AC_INTMODE_gm Predefined. */ -/* AC_INTMODE_gp Predefined. */ -/* AC_INTMODE0_bm Predefined. */ -/* AC_INTMODE0_bp Predefined. */ -/* AC_INTMODE1_bm Predefined. */ -/* AC_INTMODE1_bp Predefined. */ - -/* AC_INTLVL_gm Predefined. */ -/* AC_INTLVL_gp Predefined. */ -/* AC_INTLVL0_bm Predefined. */ -/* AC_INTLVL0_bp Predefined. */ -/* AC_INTLVL1_bm Predefined. */ -/* AC_INTLVL1_bp Predefined. */ - -/* AC_HSMODE_bm Predefined. */ -/* AC_HSMODE_bp Predefined. */ - -/* AC_HYSMODE_gm Predefined. */ -/* AC_HYSMODE_gp Predefined. */ -/* AC_HYSMODE0_bm Predefined. */ -/* AC_HYSMODE0_bp Predefined. */ -/* AC_HYSMODE1_bm Predefined. */ -/* AC_HYSMODE1_bp Predefined. */ - -/* AC_ENABLE_bm Predefined. */ -/* AC_ENABLE_bp Predefined. */ - - -/* AC.AC0MUXCTRL bit masks and bit positions */ -#define AC_MUXPOS_gm 0x38 /* MUX Positive Input group mask. */ -#define AC_MUXPOS_gp 3 /* MUX Positive Input group position. */ -#define AC_MUXPOS0_bm (1<<3) /* MUX Positive Input bit 0 mask. */ -#define AC_MUXPOS0_bp 3 /* MUX Positive Input bit 0 position. */ -#define AC_MUXPOS1_bm (1<<4) /* MUX Positive Input bit 1 mask. */ -#define AC_MUXPOS1_bp 4 /* MUX Positive Input bit 1 position. */ -#define AC_MUXPOS2_bm (1<<5) /* MUX Positive Input bit 2 mask. */ -#define AC_MUXPOS2_bp 5 /* MUX Positive Input bit 2 position. */ - -#define AC_MUXNEG_gm 0x07 /* MUX Negative Input group mask. */ -#define AC_MUXNEG_gp 0 /* MUX Negative Input group position. */ -#define AC_MUXNEG0_bm (1<<0) /* MUX Negative Input bit 0 mask. */ -#define AC_MUXNEG0_bp 0 /* MUX Negative Input bit 0 position. */ -#define AC_MUXNEG1_bm (1<<1) /* MUX Negative Input bit 1 mask. */ -#define AC_MUXNEG1_bp 1 /* MUX Negative Input bit 1 position. */ -#define AC_MUXNEG2_bm (1<<2) /* MUX Negative Input bit 2 mask. */ -#define AC_MUXNEG2_bp 2 /* MUX Negative Input bit 2 position. */ - - -/* AC.AC1MUXCTRL bit masks and bit positions */ -/* AC_MUXPOS_gm Predefined. */ -/* AC_MUXPOS_gp Predefined. */ -/* AC_MUXPOS0_bm Predefined. */ -/* AC_MUXPOS0_bp Predefined. */ -/* AC_MUXPOS1_bm Predefined. */ -/* AC_MUXPOS1_bp Predefined. */ -/* AC_MUXPOS2_bm Predefined. */ -/* AC_MUXPOS2_bp Predefined. */ - -/* AC_MUXNEG_gm Predefined. */ -/* AC_MUXNEG_gp Predefined. */ -/* AC_MUXNEG0_bm Predefined. */ -/* AC_MUXNEG0_bp Predefined. */ -/* AC_MUXNEG1_bm Predefined. */ -/* AC_MUXNEG1_bp Predefined. */ -/* AC_MUXNEG2_bm Predefined. */ -/* AC_MUXNEG2_bp Predefined. */ - - -/* AC.CTRLA bit masks and bit positions */ -#define AC_AC0OUT_bm 0x01 /* Comparator 0 Output Enable bit mask. */ -#define AC_AC0OUT_bp 0 /* Comparator 0 Output Enable bit position. */ - - -/* AC.CTRLB bit masks and bit positions */ -#define AC_SCALEFAC_gm 0x3F /* VCC Voltage Scaler Factor group mask. */ -#define AC_SCALEFAC_gp 0 /* VCC Voltage Scaler Factor group position. */ -#define AC_SCALEFAC0_bm (1<<0) /* VCC Voltage Scaler Factor bit 0 mask. */ -#define AC_SCALEFAC0_bp 0 /* VCC Voltage Scaler Factor bit 0 position. */ -#define AC_SCALEFAC1_bm (1<<1) /* VCC Voltage Scaler Factor bit 1 mask. */ -#define AC_SCALEFAC1_bp 1 /* VCC Voltage Scaler Factor bit 1 position. */ -#define AC_SCALEFAC2_bm (1<<2) /* VCC Voltage Scaler Factor bit 2 mask. */ -#define AC_SCALEFAC2_bp 2 /* VCC Voltage Scaler Factor bit 2 position. */ -#define AC_SCALEFAC3_bm (1<<3) /* VCC Voltage Scaler Factor bit 3 mask. */ -#define AC_SCALEFAC3_bp 3 /* VCC Voltage Scaler Factor bit 3 position. */ -#define AC_SCALEFAC4_bm (1<<4) /* VCC Voltage Scaler Factor bit 4 mask. */ -#define AC_SCALEFAC4_bp 4 /* VCC Voltage Scaler Factor bit 4 position. */ -#define AC_SCALEFAC5_bm (1<<5) /* VCC Voltage Scaler Factor bit 5 mask. */ -#define AC_SCALEFAC5_bp 5 /* VCC Voltage Scaler Factor bit 5 position. */ - - -/* AC.WINCTRL bit masks and bit positions */ -#define AC_WEN_bm 0x10 /* Window Mode Enable bit mask. */ -#define AC_WEN_bp 4 /* Window Mode Enable bit position. */ - -#define AC_WINTMODE_gm 0x0C /* Window Interrupt Mode group mask. */ -#define AC_WINTMODE_gp 2 /* Window Interrupt Mode group position. */ -#define AC_WINTMODE0_bm (1<<2) /* Window Interrupt Mode bit 0 mask. */ -#define AC_WINTMODE0_bp 2 /* Window Interrupt Mode bit 0 position. */ -#define AC_WINTMODE1_bm (1<<3) /* Window Interrupt Mode bit 1 mask. */ -#define AC_WINTMODE1_bp 3 /* Window Interrupt Mode bit 1 position. */ - -#define AC_WINTLVL_gm 0x03 /* Window Interrupt Level group mask. */ -#define AC_WINTLVL_gp 0 /* Window Interrupt Level group position. */ -#define AC_WINTLVL0_bm (1<<0) /* Window Interrupt Level bit 0 mask. */ -#define AC_WINTLVL0_bp 0 /* Window Interrupt Level bit 0 position. */ -#define AC_WINTLVL1_bm (1<<1) /* Window Interrupt Level bit 1 mask. */ -#define AC_WINTLVL1_bp 1 /* Window Interrupt Level bit 1 position. */ - - -/* AC.STATUS bit masks and bit positions */ -#define AC_WSTATE_gm 0xC0 /* Window Mode State group mask. */ -#define AC_WSTATE_gp 6 /* Window Mode State group position. */ -#define AC_WSTATE0_bm (1<<6) /* Window Mode State bit 0 mask. */ -#define AC_WSTATE0_bp 6 /* Window Mode State bit 0 position. */ -#define AC_WSTATE1_bm (1<<7) /* Window Mode State bit 1 mask. */ -#define AC_WSTATE1_bp 7 /* Window Mode State bit 1 position. */ - -#define AC_AC1STATE_bm 0x20 /* Comparator 1 State bit mask. */ -#define AC_AC1STATE_bp 5 /* Comparator 1 State bit position. */ - -#define AC_AC0STATE_bm 0x10 /* Comparator 0 State bit mask. */ -#define AC_AC0STATE_bp 4 /* Comparator 0 State bit position. */ - -#define AC_WIF_bm 0x04 /* Window Mode Interrupt Flag bit mask. */ -#define AC_WIF_bp 2 /* Window Mode Interrupt Flag bit position. */ - -#define AC_AC1IF_bm 0x02 /* Comparator 1 Interrupt Flag bit mask. */ -#define AC_AC1IF_bp 1 /* Comparator 1 Interrupt Flag bit position. */ - -#define AC_AC0IF_bm 0x01 /* Comparator 0 Interrupt Flag bit mask. */ -#define AC_AC0IF_bp 0 /* Comparator 0 Interrupt Flag bit position. */ - - -/* ADC - Analog/Digital Converter */ -/* ADC_CH.CTRL bit masks and bit positions */ -#define ADC_CH_START_bm 0x80 /* Channel Start Conversion bit mask. */ -#define ADC_CH_START_bp 7 /* Channel Start Conversion bit position. */ - -#define ADC_CH_GAINFAC_gm 0x1C /* Gain Factor group mask. */ -#define ADC_CH_GAINFAC_gp 2 /* Gain Factor group position. */ -#define ADC_CH_GAINFAC0_bm (1<<2) /* Gain Factor bit 0 mask. */ -#define ADC_CH_GAINFAC0_bp 2 /* Gain Factor bit 0 position. */ -#define ADC_CH_GAINFAC1_bm (1<<3) /* Gain Factor bit 1 mask. */ -#define ADC_CH_GAINFAC1_bp 3 /* Gain Factor bit 1 position. */ -#define ADC_CH_GAINFAC2_bm (1<<4) /* Gain Factor bit 2 mask. */ -#define ADC_CH_GAINFAC2_bp 4 /* Gain Factor bit 2 position. */ - -#define ADC_CH_INPUTMODE_gm 0x03 /* Input Mode Select group mask. */ -#define ADC_CH_INPUTMODE_gp 0 /* Input Mode Select group position. */ -#define ADC_CH_INPUTMODE0_bm (1<<0) /* Input Mode Select bit 0 mask. */ -#define ADC_CH_INPUTMODE0_bp 0 /* Input Mode Select bit 0 position. */ -#define ADC_CH_INPUTMODE1_bm (1<<1) /* Input Mode Select bit 1 mask. */ -#define ADC_CH_INPUTMODE1_bp 1 /* Input Mode Select bit 1 position. */ - - -/* ADC_CH.MUXCTRL bit masks and bit positions */ -#define ADC_CH_MUXPOS_gm 0x78 /* Positive Input Select group mask. */ -#define ADC_CH_MUXPOS_gp 3 /* Positive Input Select group position. */ -#define ADC_CH_MUXPOS0_bm (1<<3) /* Positive Input Select bit 0 mask. */ -#define ADC_CH_MUXPOS0_bp 3 /* Positive Input Select bit 0 position. */ -#define ADC_CH_MUXPOS1_bm (1<<4) /* Positive Input Select bit 1 mask. */ -#define ADC_CH_MUXPOS1_bp 4 /* Positive Input Select bit 1 position. */ -#define ADC_CH_MUXPOS2_bm (1<<5) /* Positive Input Select bit 2 mask. */ -#define ADC_CH_MUXPOS2_bp 5 /* Positive Input Select bit 2 position. */ -#define ADC_CH_MUXPOS3_bm (1<<6) /* Positive Input Select bit 3 mask. */ -#define ADC_CH_MUXPOS3_bp 6 /* Positive Input Select bit 3 position. */ - -#define ADC_CH_MUXINT_gm 0x78 /* Internal Input Select group mask. */ -#define ADC_CH_MUXINT_gp 3 /* Internal Input Select group position. */ -#define ADC_CH_MUXINT0_bm (1<<3) /* Internal Input Select bit 0 mask. */ -#define ADC_CH_MUXINT0_bp 3 /* Internal Input Select bit 0 position. */ -#define ADC_CH_MUXINT1_bm (1<<4) /* Internal Input Select bit 1 mask. */ -#define ADC_CH_MUXINT1_bp 4 /* Internal Input Select bit 1 position. */ -#define ADC_CH_MUXINT2_bm (1<<5) /* Internal Input Select bit 2 mask. */ -#define ADC_CH_MUXINT2_bp 5 /* Internal Input Select bit 2 position. */ -#define ADC_CH_MUXINT3_bm (1<<6) /* Internal Input Select bit 3 mask. */ -#define ADC_CH_MUXINT3_bp 6 /* Internal Input Select bit 3 position. */ - -#define ADC_CH_MUXNEG_gm 0x03 /* Negative Input Select group mask. */ -#define ADC_CH_MUXNEG_gp 0 /* Negative Input Select group position. */ -#define ADC_CH_MUXNEG0_bm (1<<0) /* Negative Input Select bit 0 mask. */ -#define ADC_CH_MUXNEG0_bp 0 /* Negative Input Select bit 0 position. */ -#define ADC_CH_MUXNEG1_bm (1<<1) /* Negative Input Select bit 1 mask. */ -#define ADC_CH_MUXNEG1_bp 1 /* Negative Input Select bit 1 position. */ - - -/* ADC_CH.INTCTRL bit masks and bit positions */ -#define ADC_CH_INTMODE_gm 0x0C /* Interrupt Mode group mask. */ -#define ADC_CH_INTMODE_gp 2 /* Interrupt Mode group position. */ -#define ADC_CH_INTMODE0_bm (1<<2) /* Interrupt Mode bit 0 mask. */ -#define ADC_CH_INTMODE0_bp 2 /* Interrupt Mode bit 0 position. */ -#define ADC_CH_INTMODE1_bm (1<<3) /* Interrupt Mode bit 1 mask. */ -#define ADC_CH_INTMODE1_bp 3 /* Interrupt Mode bit 1 position. */ - -#define ADC_CH_INTLVL_gm 0x03 /* Interrupt Level group mask. */ -#define ADC_CH_INTLVL_gp 0 /* Interrupt Level group position. */ -#define ADC_CH_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */ -#define ADC_CH_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */ -#define ADC_CH_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ -#define ADC_CH_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */ - - -/* ADC_CH.INTFLAGS bit masks and bit positions */ -#define ADC_CH_CHIF_bm 0x01 /* Channel Interrupt Flag bit mask. */ -#define ADC_CH_CHIF_bp 0 /* Channel Interrupt Flag bit position. */ - - -/* ADC.CTRLA bit masks and bit positions */ -#define ADC_DMASEL_gm 0xC0 /* DMA Selection group mask. */ -#define ADC_DMASEL_gp 6 /* DMA Selection group position. */ -#define ADC_DMASEL0_bm (1<<6) /* DMA Selection bit 0 mask. */ -#define ADC_DMASEL0_bp 6 /* DMA Selection bit 0 position. */ -#define ADC_DMASEL1_bm (1<<7) /* DMA Selection bit 1 mask. */ -#define ADC_DMASEL1_bp 7 /* DMA Selection bit 1 position. */ - -#define ADC_CH3START_bm 0x20 /* Channel 3 Start Conversion bit mask. */ -#define ADC_CH3START_bp 5 /* Channel 3 Start Conversion bit position. */ - -#define ADC_CH2START_bm 0x10 /* Channel 2 Start Conversion bit mask. */ -#define ADC_CH2START_bp 4 /* Channel 2 Start Conversion bit position. */ - -#define ADC_CH1START_bm 0x08 /* Channel 1 Start Conversion bit mask. */ -#define ADC_CH1START_bp 3 /* Channel 1 Start Conversion bit position. */ - -#define ADC_CH0START_bm 0x04 /* Channel 0 Start Conversion bit mask. */ -#define ADC_CH0START_bp 2 /* Channel 0 Start Conversion bit position. */ - -#define ADC_FLUSH_bm 0x02 /* Flush Pipeline bit mask. */ -#define ADC_FLUSH_bp 1 /* Flush Pipeline bit position. */ - -#define ADC_ENABLE_bm 0x01 /* Enable ADC bit mask. */ -#define ADC_ENABLE_bp 0 /* Enable ADC bit position. */ - - -/* ADC.CTRLB bit masks and bit positions */ -#define ADC_CONMODE_bm 0x10 /* Conversion Mode bit mask. */ -#define ADC_CONMODE_bp 4 /* Conversion Mode bit position. */ - -#define ADC_FREERUN_bm 0x08 /* Free Running Mode Enable bit mask. */ -#define ADC_FREERUN_bp 3 /* Free Running Mode Enable bit position. */ - -#define ADC_RESOLUTION_gm 0x06 /* Result Resolution group mask. */ -#define ADC_RESOLUTION_gp 1 /* Result Resolution group position. */ -#define ADC_RESOLUTION0_bm (1<<1) /* Result Resolution bit 0 mask. */ -#define ADC_RESOLUTION0_bp 1 /* Result Resolution bit 0 position. */ -#define ADC_RESOLUTION1_bm (1<<2) /* Result Resolution bit 1 mask. */ -#define ADC_RESOLUTION1_bp 2 /* Result Resolution bit 1 position. */ - - -/* ADC.REFCTRL bit masks and bit positions */ -#define ADC_REFSEL_gm 0x30 /* Reference Selection group mask. */ -#define ADC_REFSEL_gp 4 /* Reference Selection group position. */ -#define ADC_REFSEL0_bm (1<<4) /* Reference Selection bit 0 mask. */ -#define ADC_REFSEL0_bp 4 /* Reference Selection bit 0 position. */ -#define ADC_REFSEL1_bm (1<<5) /* Reference Selection bit 1 mask. */ -#define ADC_REFSEL1_bp 5 /* Reference Selection bit 1 position. */ - -#define ADC_BANDGAP_bm 0x02 /* Bandgap enable bit mask. */ -#define ADC_BANDGAP_bp 1 /* Bandgap enable bit position. */ - -#define ADC_TEMPREF_bm 0x01 /* Temperature Reference Enable bit mask. */ -#define ADC_TEMPREF_bp 0 /* Temperature Reference Enable bit position. */ - - -/* ADC.EVCTRL bit masks and bit positions */ -#define ADC_SWEEP_gm 0xC0 /* Channel Sweep Selection group mask. */ -#define ADC_SWEEP_gp 6 /* Channel Sweep Selection group position. */ -#define ADC_SWEEP0_bm (1<<6) /* Channel Sweep Selection bit 0 mask. */ -#define ADC_SWEEP0_bp 6 /* Channel Sweep Selection bit 0 position. */ -#define ADC_SWEEP1_bm (1<<7) /* Channel Sweep Selection bit 1 mask. */ -#define ADC_SWEEP1_bp 7 /* Channel Sweep Selection bit 1 position. */ - -#define ADC_EVSEL_gm 0x38 /* Event Input Select group mask. */ -#define ADC_EVSEL_gp 3 /* Event Input Select group position. */ -#define ADC_EVSEL0_bm (1<<3) /* Event Input Select bit 0 mask. */ -#define ADC_EVSEL0_bp 3 /* Event Input Select bit 0 position. */ -#define ADC_EVSEL1_bm (1<<4) /* Event Input Select bit 1 mask. */ -#define ADC_EVSEL1_bp 4 /* Event Input Select bit 1 position. */ -#define ADC_EVSEL2_bm (1<<5) /* Event Input Select bit 2 mask. */ -#define ADC_EVSEL2_bp 5 /* Event Input Select bit 2 position. */ - -#define ADC_EVACT_gm 0x07 /* Event Action Select group mask. */ -#define ADC_EVACT_gp 0 /* Event Action Select group position. */ -#define ADC_EVACT0_bm (1<<0) /* Event Action Select bit 0 mask. */ -#define ADC_EVACT0_bp 0 /* Event Action Select bit 0 position. */ -#define ADC_EVACT1_bm (1<<1) /* Event Action Select bit 1 mask. */ -#define ADC_EVACT1_bp 1 /* Event Action Select bit 1 position. */ -#define ADC_EVACT2_bm (1<<2) /* Event Action Select bit 2 mask. */ -#define ADC_EVACT2_bp 2 /* Event Action Select bit 2 position. */ - - -/* ADC.PRESCALER bit masks and bit positions */ -#define ADC_PRESCALER_gm 0x07 /* Clock Prescaler Selection group mask. */ -#define ADC_PRESCALER_gp 0 /* Clock Prescaler Selection group position. */ -#define ADC_PRESCALER0_bm (1<<0) /* Clock Prescaler Selection bit 0 mask. */ -#define ADC_PRESCALER0_bp 0 /* Clock Prescaler Selection bit 0 position. */ -#define ADC_PRESCALER1_bm (1<<1) /* Clock Prescaler Selection bit 1 mask. */ -#define ADC_PRESCALER1_bp 1 /* Clock Prescaler Selection bit 1 position. */ -#define ADC_PRESCALER2_bm (1<<2) /* Clock Prescaler Selection bit 2 mask. */ -#define ADC_PRESCALER2_bp 2 /* Clock Prescaler Selection bit 2 position. */ - - -/* ADC.INTFLAGS bit masks and bit positions */ -#define ADC_CH3IF_bm 0x08 /* Channel 3 Interrupt Flag bit mask. */ -#define ADC_CH3IF_bp 3 /* Channel 3 Interrupt Flag bit position. */ - -#define ADC_CH2IF_bm 0x04 /* Channel 2 Interrupt Flag bit mask. */ -#define ADC_CH2IF_bp 2 /* Channel 2 Interrupt Flag bit position. */ - -#define ADC_CH1IF_bm 0x02 /* Channel 1 Interrupt Flag bit mask. */ -#define ADC_CH1IF_bp 1 /* Channel 1 Interrupt Flag bit position. */ - -#define ADC_CH0IF_bm 0x01 /* Channel 0 Interrupt Flag bit mask. */ -#define ADC_CH0IF_bp 0 /* Channel 0 Interrupt Flag bit position. */ - - -/* DAC - Digital/Analog Converter */ -/* DAC.CTRLA bit masks and bit positions */ -#define DAC_IDOEN_bm 0x10 /* Internal Output Enable bit mask. */ -#define DAC_IDOEN_bp 4 /* Internal Output Enable bit position. */ - -#define DAC_CH1EN_bm 0x08 /* Channel 1 Output Enable bit mask. */ -#define DAC_CH1EN_bp 3 /* Channel 1 Output Enable bit position. */ - -#define DAC_CH0EN_bm 0x04 /* Channel 0 Output Enable bit mask. */ -#define DAC_CH0EN_bp 2 /* Channel 0 Output Enable bit position. */ - -#define DAC_LPMODE_bm 0x02 /* Low Power Mode bit mask. */ -#define DAC_LPMODE_bp 1 /* Low Power Mode bit position. */ - -#define DAC_ENABLE_bm 0x01 /* Enable bit mask. */ -#define DAC_ENABLE_bp 0 /* Enable bit position. */ - - -/* DAC.CTRLB bit masks and bit positions */ -#define DAC_CHSEL_gm 0x60 /* Channel Select group mask. */ -#define DAC_CHSEL_gp 5 /* Channel Select group position. */ -#define DAC_CHSEL0_bm (1<<5) /* Channel Select bit 0 mask. */ -#define DAC_CHSEL0_bp 5 /* Channel Select bit 0 position. */ -#define DAC_CHSEL1_bm (1<<6) /* Channel Select bit 1 mask. */ -#define DAC_CHSEL1_bp 6 /* Channel Select bit 1 position. */ - -#define DAC_CH1TRIG_bm 0x02 /* Channel 1 Event Trig Enable bit mask. */ -#define DAC_CH1TRIG_bp 1 /* Channel 1 Event Trig Enable bit position. */ - -#define DAC_CH0TRIG_bm 0x01 /* Channel 0 Event Trig Enable bit mask. */ -#define DAC_CH0TRIG_bp 0 /* Channel 0 Event Trig Enable bit position. */ - - -/* DAC.CTRLC bit masks and bit positions */ -#define DAC_REFSEL_gm 0x18 /* Reference Select group mask. */ -#define DAC_REFSEL_gp 3 /* Reference Select group position. */ -#define DAC_REFSEL0_bm (1<<3) /* Reference Select bit 0 mask. */ -#define DAC_REFSEL0_bp 3 /* Reference Select bit 0 position. */ -#define DAC_REFSEL1_bm (1<<4) /* Reference Select bit 1 mask. */ -#define DAC_REFSEL1_bp 4 /* Reference Select bit 1 position. */ - -#define DAC_LEFTADJ_bm 0x01 /* Left-adjust Result bit mask. */ -#define DAC_LEFTADJ_bp 0 /* Left-adjust Result bit position. */ - - -/* DAC.EVCTRL bit masks and bit positions */ -#define DAC_EVSEL_gm 0x07 /* Event Input Selection group mask. */ -#define DAC_EVSEL_gp 0 /* Event Input Selection group position. */ -#define DAC_EVSEL0_bm (1<<0) /* Event Input Selection bit 0 mask. */ -#define DAC_EVSEL0_bp 0 /* Event Input Selection bit 0 position. */ -#define DAC_EVSEL1_bm (1<<1) /* Event Input Selection bit 1 mask. */ -#define DAC_EVSEL1_bp 1 /* Event Input Selection bit 1 position. */ -#define DAC_EVSEL2_bm (1<<2) /* Event Input Selection bit 2 mask. */ -#define DAC_EVSEL2_bp 2 /* Event Input Selection bit 2 position. */ - - -/* DAC.TIMCTRL bit masks and bit positions */ -#define DAC_CONINTVAL_gm 0x70 /* Conversion Intercal group mask. */ -#define DAC_CONINTVAL_gp 4 /* Conversion Intercal group position. */ -#define DAC_CONINTVAL0_bm (1<<4) /* Conversion Intercal bit 0 mask. */ -#define DAC_CONINTVAL0_bp 4 /* Conversion Intercal bit 0 position. */ -#define DAC_CONINTVAL1_bm (1<<5) /* Conversion Intercal bit 1 mask. */ -#define DAC_CONINTVAL1_bp 5 /* Conversion Intercal bit 1 position. */ -#define DAC_CONINTVAL2_bm (1<<6) /* Conversion Intercal bit 2 mask. */ -#define DAC_CONINTVAL2_bp 6 /* Conversion Intercal bit 2 position. */ - -#define DAC_REFRESH_gm 0x0F /* Refresh Timing Control group mask. */ -#define DAC_REFRESH_gp 0 /* Refresh Timing Control group position. */ -#define DAC_REFRESH0_bm (1<<0) /* Refresh Timing Control bit 0 mask. */ -#define DAC_REFRESH0_bp 0 /* Refresh Timing Control bit 0 position. */ -#define DAC_REFRESH1_bm (1<<1) /* Refresh Timing Control bit 1 mask. */ -#define DAC_REFRESH1_bp 1 /* Refresh Timing Control bit 1 position. */ -#define DAC_REFRESH2_bm (1<<2) /* Refresh Timing Control bit 2 mask. */ -#define DAC_REFRESH2_bp 2 /* Refresh Timing Control bit 2 position. */ -#define DAC_REFRESH3_bm (1<<3) /* Refresh Timing Control bit 3 mask. */ -#define DAC_REFRESH3_bp 3 /* Refresh Timing Control bit 3 position. */ - - -/* DAC.STATUS bit masks and bit positions */ -#define DAC_CH1DRE_bm 0x02 /* Channel 1 Data Register Empty bit mask. */ -#define DAC_CH1DRE_bp 1 /* Channel 1 Data Register Empty bit position. */ - -#define DAC_CH0DRE_bm 0x01 /* Channel 0 Data Register Empty bit mask. */ -#define DAC_CH0DRE_bp 0 /* Channel 0 Data Register Empty bit position. */ - - -/* RTC - Real-Time Clounter */ -/* RTC.CTRL bit masks and bit positions */ -#define RTC_PRESCALER_gm 0x07 /* Prescaling Factor group mask. */ -#define RTC_PRESCALER_gp 0 /* Prescaling Factor group position. */ -#define RTC_PRESCALER0_bm (1<<0) /* Prescaling Factor bit 0 mask. */ -#define RTC_PRESCALER0_bp 0 /* Prescaling Factor bit 0 position. */ -#define RTC_PRESCALER1_bm (1<<1) /* Prescaling Factor bit 1 mask. */ -#define RTC_PRESCALER1_bp 1 /* Prescaling Factor bit 1 position. */ -#define RTC_PRESCALER2_bm (1<<2) /* Prescaling Factor bit 2 mask. */ -#define RTC_PRESCALER2_bp 2 /* Prescaling Factor bit 2 position. */ - - -/* RTC.STATUS bit masks and bit positions */ -#define RTC_SYNCBUSY_bm 0x01 /* Synchronization Busy Flag bit mask. */ -#define RTC_SYNCBUSY_bp 0 /* Synchronization Busy Flag bit position. */ - - -/* RTC.INTCTRL bit masks and bit positions */ -#define RTC_COMPINTLVL_gm 0x0C /* Compare Match Interrupt Level group mask. */ -#define RTC_COMPINTLVL_gp 2 /* Compare Match Interrupt Level group position. */ -#define RTC_COMPINTLVL0_bm (1<<2) /* Compare Match Interrupt Level bit 0 mask. */ -#define RTC_COMPINTLVL0_bp 2 /* Compare Match Interrupt Level bit 0 position. */ -#define RTC_COMPINTLVL1_bm (1<<3) /* Compare Match Interrupt Level bit 1 mask. */ -#define RTC_COMPINTLVL1_bp 3 /* Compare Match Interrupt Level bit 1 position. */ - -#define RTC_OVFINTLVL_gm 0x03 /* Overflow Interrupt Level group mask. */ -#define RTC_OVFINTLVL_gp 0 /* Overflow Interrupt Level group position. */ -#define RTC_OVFINTLVL0_bm (1<<0) /* Overflow Interrupt Level bit 0 mask. */ -#define RTC_OVFINTLVL0_bp 0 /* Overflow Interrupt Level bit 0 position. */ -#define RTC_OVFINTLVL1_bm (1<<1) /* Overflow Interrupt Level bit 1 mask. */ -#define RTC_OVFINTLVL1_bp 1 /* Overflow Interrupt Level bit 1 position. */ - - -/* RTC.INTFLAGS bit masks and bit positions */ -#define RTC_COMPIF_bm 0x02 /* Compare Match Interrupt Flag bit mask. */ -#define RTC_COMPIF_bp 1 /* Compare Match Interrupt Flag bit position. */ - -#define RTC_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ -#define RTC_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ - - -/* EBI - External Bus Interface */ -/* EBI_CS.CTRLA bit masks and bit positions */ -#define EBI_CS_ASIZE_gm 0x7C /* Address Size group mask. */ -#define EBI_CS_ASIZE_gp 2 /* Address Size group position. */ -#define EBI_CS_ASIZE0_bm (1<<2) /* Address Size bit 0 mask. */ -#define EBI_CS_ASIZE0_bp 2 /* Address Size bit 0 position. */ -#define EBI_CS_ASIZE1_bm (1<<3) /* Address Size bit 1 mask. */ -#define EBI_CS_ASIZE1_bp 3 /* Address Size bit 1 position. */ -#define EBI_CS_ASIZE2_bm (1<<4) /* Address Size bit 2 mask. */ -#define EBI_CS_ASIZE2_bp 4 /* Address Size bit 2 position. */ -#define EBI_CS_ASIZE3_bm (1<<5) /* Address Size bit 3 mask. */ -#define EBI_CS_ASIZE3_bp 5 /* Address Size bit 3 position. */ -#define EBI_CS_ASIZE4_bm (1<<6) /* Address Size bit 4 mask. */ -#define EBI_CS_ASIZE4_bp 6 /* Address Size bit 4 position. */ - -#define EBI_CS_MODE_gm 0x03 /* Memory Mode group mask. */ -#define EBI_CS_MODE_gp 0 /* Memory Mode group position. */ -#define EBI_CS_MODE0_bm (1<<0) /* Memory Mode bit 0 mask. */ -#define EBI_CS_MODE0_bp 0 /* Memory Mode bit 0 position. */ -#define EBI_CS_MODE1_bm (1<<1) /* Memory Mode bit 1 mask. */ -#define EBI_CS_MODE1_bp 1 /* Memory Mode bit 1 position. */ - - -/* EBI_CS.CTRLB bit masks and bit positions */ -#define EBI_CS_SRWS_gm 0x07 /* SRAM Wait State Cycles group mask. */ -#define EBI_CS_SRWS_gp 0 /* SRAM Wait State Cycles group position. */ -#define EBI_CS_SRWS0_bm (1<<0) /* SRAM Wait State Cycles bit 0 mask. */ -#define EBI_CS_SRWS0_bp 0 /* SRAM Wait State Cycles bit 0 position. */ -#define EBI_CS_SRWS1_bm (1<<1) /* SRAM Wait State Cycles bit 1 mask. */ -#define EBI_CS_SRWS1_bp 1 /* SRAM Wait State Cycles bit 1 position. */ -#define EBI_CS_SRWS2_bm (1<<2) /* SRAM Wait State Cycles bit 2 mask. */ -#define EBI_CS_SRWS2_bp 2 /* SRAM Wait State Cycles bit 2 position. */ - -#define EBI_CS_SDINITDONE_bm 0x80 /* SDRAM Initialization Done bit mask. */ -#define EBI_CS_SDINITDONE_bp 7 /* SDRAM Initialization Done bit position. */ - -#define EBI_CS_SDSREN_bm 0x04 /* SDRAM Self-refresh Enable bit mask. */ -#define EBI_CS_SDSREN_bp 2 /* SDRAM Self-refresh Enable bit position. */ - -#define EBI_CS_SDMODE_gm 0x03 /* SDRAM Mode group mask. */ -#define EBI_CS_SDMODE_gp 0 /* SDRAM Mode group position. */ -#define EBI_CS_SDMODE0_bm (1<<0) /* SDRAM Mode bit 0 mask. */ -#define EBI_CS_SDMODE0_bp 0 /* SDRAM Mode bit 0 position. */ -#define EBI_CS_SDMODE1_bm (1<<1) /* SDRAM Mode bit 1 mask. */ -#define EBI_CS_SDMODE1_bp 1 /* SDRAM Mode bit 1 position. */ - - -/* EBI.CTRL bit masks and bit positions */ -#define EBI_SDDATAW_gm 0xC0 /* SDRAM Data Width Setting group mask. */ -#define EBI_SDDATAW_gp 6 /* SDRAM Data Width Setting group position. */ -#define EBI_SDDATAW0_bm (1<<6) /* SDRAM Data Width Setting bit 0 mask. */ -#define EBI_SDDATAW0_bp 6 /* SDRAM Data Width Setting bit 0 position. */ -#define EBI_SDDATAW1_bm (1<<7) /* SDRAM Data Width Setting bit 1 mask. */ -#define EBI_SDDATAW1_bp 7 /* SDRAM Data Width Setting bit 1 position. */ - -#define EBI_LPCMODE_gm 0x30 /* SRAM LPC Mode group mask. */ -#define EBI_LPCMODE_gp 4 /* SRAM LPC Mode group position. */ -#define EBI_LPCMODE0_bm (1<<4) /* SRAM LPC Mode bit 0 mask. */ -#define EBI_LPCMODE0_bp 4 /* SRAM LPC Mode bit 0 position. */ -#define EBI_LPCMODE1_bm (1<<5) /* SRAM LPC Mode bit 1 mask. */ -#define EBI_LPCMODE1_bp 5 /* SRAM LPC Mode bit 1 position. */ - -#define EBI_SRMODE_gm 0x0C /* SRAM Mode group mask. */ -#define EBI_SRMODE_gp 2 /* SRAM Mode group position. */ -#define EBI_SRMODE0_bm (1<<2) /* SRAM Mode bit 0 mask. */ -#define EBI_SRMODE0_bp 2 /* SRAM Mode bit 0 position. */ -#define EBI_SRMODE1_bm (1<<3) /* SRAM Mode bit 1 mask. */ -#define EBI_SRMODE1_bp 3 /* SRAM Mode bit 1 position. */ - -#define EBI_IFMODE_gm 0x03 /* Interface Mode group mask. */ -#define EBI_IFMODE_gp 0 /* Interface Mode group position. */ -#define EBI_IFMODE0_bm (1<<0) /* Interface Mode bit 0 mask. */ -#define EBI_IFMODE0_bp 0 /* Interface Mode bit 0 position. */ -#define EBI_IFMODE1_bm (1<<1) /* Interface Mode bit 1 mask. */ -#define EBI_IFMODE1_bp 1 /* Interface Mode bit 1 position. */ - - -/* EBI.SDRAMCTRLA bit masks and bit positions */ -#define EBI_SDCAS_bm 0x08 /* SDRAM CAS Latency Setting bit mask. */ -#define EBI_SDCAS_bp 3 /* SDRAM CAS Latency Setting bit position. */ - -#define EBI_SDROW_bm 0x04 /* SDRAM ROW Bits Setting bit mask. */ -#define EBI_SDROW_bp 2 /* SDRAM ROW Bits Setting bit position. */ - -#define EBI_SDCOL_gm 0x03 /* SDRAM Column Bits Setting group mask. */ -#define EBI_SDCOL_gp 0 /* SDRAM Column Bits Setting group position. */ -#define EBI_SDCOL0_bm (1<<0) /* SDRAM Column Bits Setting bit 0 mask. */ -#define EBI_SDCOL0_bp 0 /* SDRAM Column Bits Setting bit 0 position. */ -#define EBI_SDCOL1_bm (1<<1) /* SDRAM Column Bits Setting bit 1 mask. */ -#define EBI_SDCOL1_bp 1 /* SDRAM Column Bits Setting bit 1 position. */ - - -/* EBI.SDRAMCTRLB bit masks and bit positions */ -#define EBI_MRDLY_gm 0xC0 /* SDRAM Mode Register Delay group mask. */ -#define EBI_MRDLY_gp 6 /* SDRAM Mode Register Delay group position. */ -#define EBI_MRDLY0_bm (1<<6) /* SDRAM Mode Register Delay bit 0 mask. */ -#define EBI_MRDLY0_bp 6 /* SDRAM Mode Register Delay bit 0 position. */ -#define EBI_MRDLY1_bm (1<<7) /* SDRAM Mode Register Delay bit 1 mask. */ -#define EBI_MRDLY1_bp 7 /* SDRAM Mode Register Delay bit 1 position. */ - -#define EBI_ROWCYCDLY_gm 0x38 /* SDRAM Row Cycle Delay group mask. */ -#define EBI_ROWCYCDLY_gp 3 /* SDRAM Row Cycle Delay group position. */ -#define EBI_ROWCYCDLY0_bm (1<<3) /* SDRAM Row Cycle Delay bit 0 mask. */ -#define EBI_ROWCYCDLY0_bp 3 /* SDRAM Row Cycle Delay bit 0 position. */ -#define EBI_ROWCYCDLY1_bm (1<<4) /* SDRAM Row Cycle Delay bit 1 mask. */ -#define EBI_ROWCYCDLY1_bp 4 /* SDRAM Row Cycle Delay bit 1 position. */ -#define EBI_ROWCYCDLY2_bm (1<<5) /* SDRAM Row Cycle Delay bit 2 mask. */ -#define EBI_ROWCYCDLY2_bp 5 /* SDRAM Row Cycle Delay bit 2 position. */ - -#define EBI_RPDLY_gm 0x07 /* SDRAM Row-to-Precharge Delay group mask. */ -#define EBI_RPDLY_gp 0 /* SDRAM Row-to-Precharge Delay group position. */ -#define EBI_RPDLY0_bm (1<<0) /* SDRAM Row-to-Precharge Delay bit 0 mask. */ -#define EBI_RPDLY0_bp 0 /* SDRAM Row-to-Precharge Delay bit 0 position. */ -#define EBI_RPDLY1_bm (1<<1) /* SDRAM Row-to-Precharge Delay bit 1 mask. */ -#define EBI_RPDLY1_bp 1 /* SDRAM Row-to-Precharge Delay bit 1 position. */ -#define EBI_RPDLY2_bm (1<<2) /* SDRAM Row-to-Precharge Delay bit 2 mask. */ -#define EBI_RPDLY2_bp 2 /* SDRAM Row-to-Precharge Delay bit 2 position. */ - - -/* EBI.SDRAMCTRLC bit masks and bit positions */ -#define EBI_WRDLY_gm 0xC0 /* SDRAM Write Recovery Delay group mask. */ -#define EBI_WRDLY_gp 6 /* SDRAM Write Recovery Delay group position. */ -#define EBI_WRDLY0_bm (1<<6) /* SDRAM Write Recovery Delay bit 0 mask. */ -#define EBI_WRDLY0_bp 6 /* SDRAM Write Recovery Delay bit 0 position. */ -#define EBI_WRDLY1_bm (1<<7) /* SDRAM Write Recovery Delay bit 1 mask. */ -#define EBI_WRDLY1_bp 7 /* SDRAM Write Recovery Delay bit 1 position. */ - -#define EBI_ESRDLY_gm 0x38 /* SDRAM Exit-Self-refresh-to-Active Delay group mask. */ -#define EBI_ESRDLY_gp 3 /* SDRAM Exit-Self-refresh-to-Active Delay group position. */ -#define EBI_ESRDLY0_bm (1<<3) /* SDRAM Exit-Self-refresh-to-Active Delay bit 0 mask. */ -#define EBI_ESRDLY0_bp 3 /* SDRAM Exit-Self-refresh-to-Active Delay bit 0 position. */ -#define EBI_ESRDLY1_bm (1<<4) /* SDRAM Exit-Self-refresh-to-Active Delay bit 1 mask. */ -#define EBI_ESRDLY1_bp 4 /* SDRAM Exit-Self-refresh-to-Active Delay bit 1 position. */ -#define EBI_ESRDLY2_bm (1<<5) /* SDRAM Exit-Self-refresh-to-Active Delay bit 2 mask. */ -#define EBI_ESRDLY2_bp 5 /* SDRAM Exit-Self-refresh-to-Active Delay bit 2 position. */ - -#define EBI_ROWCOLDLY_gm 0x07 /* SDRAM Row-to-Column Delay group mask. */ -#define EBI_ROWCOLDLY_gp 0 /* SDRAM Row-to-Column Delay group position. */ -#define EBI_ROWCOLDLY0_bm (1<<0) /* SDRAM Row-to-Column Delay bit 0 mask. */ -#define EBI_ROWCOLDLY0_bp 0 /* SDRAM Row-to-Column Delay bit 0 position. */ -#define EBI_ROWCOLDLY1_bm (1<<1) /* SDRAM Row-to-Column Delay bit 1 mask. */ -#define EBI_ROWCOLDLY1_bp 1 /* SDRAM Row-to-Column Delay bit 1 position. */ -#define EBI_ROWCOLDLY2_bm (1<<2) /* SDRAM Row-to-Column Delay bit 2 mask. */ -#define EBI_ROWCOLDLY2_bp 2 /* SDRAM Row-to-Column Delay bit 2 position. */ - - -/* TWI - Two-Wire Interface */ -/* TWI_MASTER.CTRLA bit masks and bit positions */ -#define TWI_MASTER_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ -#define TWI_MASTER_INTLVL_gp 6 /* Interrupt Level group position. */ -#define TWI_MASTER_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ -#define TWI_MASTER_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ -#define TWI_MASTER_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ -#define TWI_MASTER_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ - -#define TWI_MASTER_RIEN_bm 0x20 /* Read Interrupt Enable bit mask. */ -#define TWI_MASTER_RIEN_bp 5 /* Read Interrupt Enable bit position. */ - -#define TWI_MASTER_WIEN_bm 0x10 /* Write Interrupt Enable bit mask. */ -#define TWI_MASTER_WIEN_bp 4 /* Write Interrupt Enable bit position. */ - -#define TWI_MASTER_ENABLE_bm 0x08 /* Enable TWI Master bit mask. */ -#define TWI_MASTER_ENABLE_bp 3 /* Enable TWI Master bit position. */ - - -/* TWI_MASTER.CTRLB bit masks and bit positions */ -#define TWI_MASTER_TIMEOUT_gm 0x0C /* Inactive Bus Timeout group mask. */ -#define TWI_MASTER_TIMEOUT_gp 2 /* Inactive Bus Timeout group position. */ -#define TWI_MASTER_TIMEOUT0_bm (1<<2) /* Inactive Bus Timeout bit 0 mask. */ -#define TWI_MASTER_TIMEOUT0_bp 2 /* Inactive Bus Timeout bit 0 position. */ -#define TWI_MASTER_TIMEOUT1_bm (1<<3) /* Inactive Bus Timeout bit 1 mask. */ -#define TWI_MASTER_TIMEOUT1_bp 3 /* Inactive Bus Timeout bit 1 position. */ - -#define TWI_MASTER_QCEN_bm 0x02 /* Quick Command Enable bit mask. */ -#define TWI_MASTER_QCEN_bp 1 /* Quick Command Enable bit position. */ - -#define TWI_MASTER_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ -#define TWI_MASTER_SMEN_bp 0 /* Smart Mode Enable bit position. */ - - -/* TWI_MASTER.CTRLC bit masks and bit positions */ -#define TWI_MASTER_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ -#define TWI_MASTER_ACKACT_bp 2 /* Acknowledge Action bit position. */ - -#define TWI_MASTER_CMD_gm 0x03 /* Command group mask. */ -#define TWI_MASTER_CMD_gp 0 /* Command group position. */ -#define TWI_MASTER_CMD0_bm (1<<0) /* Command bit 0 mask. */ -#define TWI_MASTER_CMD0_bp 0 /* Command bit 0 position. */ -#define TWI_MASTER_CMD1_bm (1<<1) /* Command bit 1 mask. */ -#define TWI_MASTER_CMD1_bp 1 /* Command bit 1 position. */ - - -/* TWI_MASTER.STATUS bit masks and bit positions */ -#define TWI_MASTER_RIF_bm 0x80 /* Read Interrupt Flag bit mask. */ -#define TWI_MASTER_RIF_bp 7 /* Read Interrupt Flag bit position. */ - -#define TWI_MASTER_WIF_bm 0x40 /* Write Interrupt Flag bit mask. */ -#define TWI_MASTER_WIF_bp 6 /* Write Interrupt Flag bit position. */ - -#define TWI_MASTER_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ -#define TWI_MASTER_CLKHOLD_bp 5 /* Clock Hold bit position. */ - -#define TWI_MASTER_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ -#define TWI_MASTER_RXACK_bp 4 /* Received Acknowledge bit position. */ - -#define TWI_MASTER_ARBLOST_bm 0x08 /* Arbitration Lost bit mask. */ -#define TWI_MASTER_ARBLOST_bp 3 /* Arbitration Lost bit position. */ - -#define TWI_MASTER_BUSERR_bm 0x04 /* Bus Error bit mask. */ -#define TWI_MASTER_BUSERR_bp 2 /* Bus Error bit position. */ - -#define TWI_MASTER_BUSSTATE_gm 0x03 /* Bus State group mask. */ -#define TWI_MASTER_BUSSTATE_gp 0 /* Bus State group position. */ -#define TWI_MASTER_BUSSTATE0_bm (1<<0) /* Bus State bit 0 mask. */ -#define TWI_MASTER_BUSSTATE0_bp 0 /* Bus State bit 0 position. */ -#define TWI_MASTER_BUSSTATE1_bm (1<<1) /* Bus State bit 1 mask. */ -#define TWI_MASTER_BUSSTATE1_bp 1 /* Bus State bit 1 position. */ - - -/* TWI_SLAVE.CTRLA bit masks and bit positions */ -#define TWI_SLAVE_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ -#define TWI_SLAVE_INTLVL_gp 6 /* Interrupt Level group position. */ -#define TWI_SLAVE_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ -#define TWI_SLAVE_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ -#define TWI_SLAVE_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ -#define TWI_SLAVE_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ - -#define TWI_SLAVE_DIEN_bm 0x20 /* Data Interrupt Enable bit mask. */ -#define TWI_SLAVE_DIEN_bp 5 /* Data Interrupt Enable bit position. */ - -#define TWI_SLAVE_APIEN_bm 0x10 /* Address/Stop Interrupt Enable bit mask. */ -#define TWI_SLAVE_APIEN_bp 4 /* Address/Stop Interrupt Enable bit position. */ - -#define TWI_SLAVE_ENABLE_bm 0x08 /* Enable TWI Slave bit mask. */ -#define TWI_SLAVE_ENABLE_bp 3 /* Enable TWI Slave bit position. */ - -#define TWI_SLAVE_PIEN_bm 0x04 /* Stop Interrupt Enable bit mask. */ -#define TWI_SLAVE_PIEN_bp 2 /* Stop Interrupt Enable bit position. */ - -#define TWI_SLAVE_PMEN_bm 0x02 /* Promiscuous Mode Enable bit mask. */ -#define TWI_SLAVE_PMEN_bp 1 /* Promiscuous Mode Enable bit position. */ - -#define TWI_SLAVE_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ -#define TWI_SLAVE_SMEN_bp 0 /* Smart Mode Enable bit position. */ - - -/* TWI_SLAVE.CTRLB bit masks and bit positions */ -#define TWI_SLAVE_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ -#define TWI_SLAVE_ACKACT_bp 2 /* Acknowledge Action bit position. */ - -#define TWI_SLAVE_CMD_gm 0x03 /* Command group mask. */ -#define TWI_SLAVE_CMD_gp 0 /* Command group position. */ -#define TWI_SLAVE_CMD0_bm (1<<0) /* Command bit 0 mask. */ -#define TWI_SLAVE_CMD0_bp 0 /* Command bit 0 position. */ -#define TWI_SLAVE_CMD1_bm (1<<1) /* Command bit 1 mask. */ -#define TWI_SLAVE_CMD1_bp 1 /* Command bit 1 position. */ - - -/* TWI_SLAVE.STATUS bit masks and bit positions */ -#define TWI_SLAVE_DIF_bm 0x80 /* Data Interrupt Flag bit mask. */ -#define TWI_SLAVE_DIF_bp 7 /* Data Interrupt Flag bit position. */ - -#define TWI_SLAVE_APIF_bm 0x40 /* Address/Stop Interrupt Flag bit mask. */ -#define TWI_SLAVE_APIF_bp 6 /* Address/Stop Interrupt Flag bit position. */ - -#define TWI_SLAVE_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ -#define TWI_SLAVE_CLKHOLD_bp 5 /* Clock Hold bit position. */ - -#define TWI_SLAVE_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ -#define TWI_SLAVE_RXACK_bp 4 /* Received Acknowledge bit position. */ - -#define TWI_SLAVE_COLL_bm 0x08 /* Collision bit mask. */ -#define TWI_SLAVE_COLL_bp 3 /* Collision bit position. */ - -#define TWI_SLAVE_BUSERR_bm 0x04 /* Bus Error bit mask. */ -#define TWI_SLAVE_BUSERR_bp 2 /* Bus Error bit position. */ - -#define TWI_SLAVE_DIR_bm 0x02 /* Read/Write Direction bit mask. */ -#define TWI_SLAVE_DIR_bp 1 /* Read/Write Direction bit position. */ - -#define TWI_SLAVE_AP_bm 0x01 /* Slave Address or Stop bit mask. */ -#define TWI_SLAVE_AP_bp 0 /* Slave Address or Stop bit position. */ - - -/* TWI_SLAVE.ADDRMASK bit masks and bit positions */ -#define TWI_SLAVE_ADDRMASK_gm 0xFE /* Address Mask group mask. */ -#define TWI_SLAVE_ADDRMASK_gp 1 /* Address Mask group position. */ -#define TWI_SLAVE_ADDRMASK0_bm (1<<1) /* Address Mask bit 0 mask. */ -#define TWI_SLAVE_ADDRMASK0_bp 1 /* Address Mask bit 0 position. */ -#define TWI_SLAVE_ADDRMASK1_bm (1<<2) /* Address Mask bit 1 mask. */ -#define TWI_SLAVE_ADDRMASK1_bp 2 /* Address Mask bit 1 position. */ -#define TWI_SLAVE_ADDRMASK2_bm (1<<3) /* Address Mask bit 2 mask. */ -#define TWI_SLAVE_ADDRMASK2_bp 3 /* Address Mask bit 2 position. */ -#define TWI_SLAVE_ADDRMASK3_bm (1<<4) /* Address Mask bit 3 mask. */ -#define TWI_SLAVE_ADDRMASK3_bp 4 /* Address Mask bit 3 position. */ -#define TWI_SLAVE_ADDRMASK4_bm (1<<5) /* Address Mask bit 4 mask. */ -#define TWI_SLAVE_ADDRMASK4_bp 5 /* Address Mask bit 4 position. */ -#define TWI_SLAVE_ADDRMASK5_bm (1<<6) /* Address Mask bit 5 mask. */ -#define TWI_SLAVE_ADDRMASK5_bp 6 /* Address Mask bit 5 position. */ -#define TWI_SLAVE_ADDRMASK6_bm (1<<7) /* Address Mask bit 6 mask. */ -#define TWI_SLAVE_ADDRMASK6_bp 7 /* Address Mask bit 6 position. */ - -#define TWI_SLAVE_ADDREN_bm 0x01 /* Address Enable bit mask. */ -#define TWI_SLAVE_ADDREN_bp 0 /* Address Enable bit position. */ - - -/* TWI.CTRL bit masks and bit positions */ -#define TWI_SDAHOLD_bm 0x02 /* SDA Hold Time Enable bit mask. */ -#define TWI_SDAHOLD_bp 1 /* SDA Hold Time Enable bit position. */ - -#define TWI_EDIEN_bm 0x01 /* External Driver Interface Enable bit mask. */ -#define TWI_EDIEN_bp 0 /* External Driver Interface Enable bit position. */ - - -/* PORT - Port Configuration */ -/* PORTCFG.VPCTRLA bit masks and bit positions */ -#define PORTCFG_VP1MAP_gm 0xF0 /* Virtual Port 1 Mapping group mask. */ -#define PORTCFG_VP1MAP_gp 4 /* Virtual Port 1 Mapping group position. */ -#define PORTCFG_VP1MAP0_bm (1<<4) /* Virtual Port 1 Mapping bit 0 mask. */ -#define PORTCFG_VP1MAP0_bp 4 /* Virtual Port 1 Mapping bit 0 position. */ -#define PORTCFG_VP1MAP1_bm (1<<5) /* Virtual Port 1 Mapping bit 1 mask. */ -#define PORTCFG_VP1MAP1_bp 5 /* Virtual Port 1 Mapping bit 1 position. */ -#define PORTCFG_VP1MAP2_bm (1<<6) /* Virtual Port 1 Mapping bit 2 mask. */ -#define PORTCFG_VP1MAP2_bp 6 /* Virtual Port 1 Mapping bit 2 position. */ -#define PORTCFG_VP1MAP3_bm (1<<7) /* Virtual Port 1 Mapping bit 3 mask. */ -#define PORTCFG_VP1MAP3_bp 7 /* Virtual Port 1 Mapping bit 3 position. */ - -#define PORTCFG_VP0MAP_gm 0x0F /* Virtual Port 0 Mapping group mask. */ -#define PORTCFG_VP0MAP_gp 0 /* Virtual Port 0 Mapping group position. */ -#define PORTCFG_VP0MAP0_bm (1<<0) /* Virtual Port 0 Mapping bit 0 mask. */ -#define PORTCFG_VP0MAP0_bp 0 /* Virtual Port 0 Mapping bit 0 position. */ -#define PORTCFG_VP0MAP1_bm (1<<1) /* Virtual Port 0 Mapping bit 1 mask. */ -#define PORTCFG_VP0MAP1_bp 1 /* Virtual Port 0 Mapping bit 1 position. */ -#define PORTCFG_VP0MAP2_bm (1<<2) /* Virtual Port 0 Mapping bit 2 mask. */ -#define PORTCFG_VP0MAP2_bp 2 /* Virtual Port 0 Mapping bit 2 position. */ -#define PORTCFG_VP0MAP3_bm (1<<3) /* Virtual Port 0 Mapping bit 3 mask. */ -#define PORTCFG_VP0MAP3_bp 3 /* Virtual Port 0 Mapping bit 3 position. */ - - -/* PORTCFG.VPCTRLB bit masks and bit positions */ -#define PORTCFG_VP3MAP_gm 0xF0 /* Virtual Port 3 Mapping group mask. */ -#define PORTCFG_VP3MAP_gp 4 /* Virtual Port 3 Mapping group position. */ -#define PORTCFG_VP3MAP0_bm (1<<4) /* Virtual Port 3 Mapping bit 0 mask. */ -#define PORTCFG_VP3MAP0_bp 4 /* Virtual Port 3 Mapping bit 0 position. */ -#define PORTCFG_VP3MAP1_bm (1<<5) /* Virtual Port 3 Mapping bit 1 mask. */ -#define PORTCFG_VP3MAP1_bp 5 /* Virtual Port 3 Mapping bit 1 position. */ -#define PORTCFG_VP3MAP2_bm (1<<6) /* Virtual Port 3 Mapping bit 2 mask. */ -#define PORTCFG_VP3MAP2_bp 6 /* Virtual Port 3 Mapping bit 2 position. */ -#define PORTCFG_VP3MAP3_bm (1<<7) /* Virtual Port 3 Mapping bit 3 mask. */ -#define PORTCFG_VP3MAP3_bp 7 /* Virtual Port 3 Mapping bit 3 position. */ - -#define PORTCFG_VP2MAP_gm 0x0F /* Virtual Port 2 Mapping group mask. */ -#define PORTCFG_VP2MAP_gp 0 /* Virtual Port 2 Mapping group position. */ -#define PORTCFG_VP2MAP0_bm (1<<0) /* Virtual Port 2 Mapping bit 0 mask. */ -#define PORTCFG_VP2MAP0_bp 0 /* Virtual Port 2 Mapping bit 0 position. */ -#define PORTCFG_VP2MAP1_bm (1<<1) /* Virtual Port 2 Mapping bit 1 mask. */ -#define PORTCFG_VP2MAP1_bp 1 /* Virtual Port 2 Mapping bit 1 position. */ -#define PORTCFG_VP2MAP2_bm (1<<2) /* Virtual Port 2 Mapping bit 2 mask. */ -#define PORTCFG_VP2MAP2_bp 2 /* Virtual Port 2 Mapping bit 2 position. */ -#define PORTCFG_VP2MAP3_bm (1<<3) /* Virtual Port 2 Mapping bit 3 mask. */ -#define PORTCFG_VP2MAP3_bp 3 /* Virtual Port 2 Mapping bit 3 position. */ - - -/* PORTCFG.CLKEVOUT bit masks and bit positions */ -#define PORTCFG_CLKOUT_gm 0x03 /* Clock Output Port group mask. */ -#define PORTCFG_CLKOUT_gp 0 /* Clock Output Port group position. */ -#define PORTCFG_CLKOUT0_bm (1<<0) /* Clock Output Port bit 0 mask. */ -#define PORTCFG_CLKOUT0_bp 0 /* Clock Output Port bit 0 position. */ -#define PORTCFG_CLKOUT1_bm (1<<1) /* Clock Output Port bit 1 mask. */ -#define PORTCFG_CLKOUT1_bp 1 /* Clock Output Port bit 1 position. */ - -#define PORTCFG_EVOUT_gm 0x30 /* Event Output Port group mask. */ -#define PORTCFG_EVOUT_gp 4 /* Event Output Port group position. */ -#define PORTCFG_EVOUT0_bm (1<<4) /* Event Output Port bit 0 mask. */ -#define PORTCFG_EVOUT0_bp 4 /* Event Output Port bit 0 position. */ -#define PORTCFG_EVOUT1_bm (1<<5) /* Event Output Port bit 1 mask. */ -#define PORTCFG_EVOUT1_bp 5 /* Event Output Port bit 1 position. */ - - -/* VPORT.INTFLAGS bit masks and bit positions */ -#define VPORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ -#define VPORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ - -#define VPORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ -#define VPORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ - - -/* PORT.INTCTRL bit masks and bit positions */ -#define PORT_INT1LVL_gm 0x0C /* Port Interrupt 1 Level group mask. */ -#define PORT_INT1LVL_gp 2 /* Port Interrupt 1 Level group position. */ -#define PORT_INT1LVL0_bm (1<<2) /* Port Interrupt 1 Level bit 0 mask. */ -#define PORT_INT1LVL0_bp 2 /* Port Interrupt 1 Level bit 0 position. */ -#define PORT_INT1LVL1_bm (1<<3) /* Port Interrupt 1 Level bit 1 mask. */ -#define PORT_INT1LVL1_bp 3 /* Port Interrupt 1 Level bit 1 position. */ - -#define PORT_INT0LVL_gm 0x03 /* Port Interrupt 0 Level group mask. */ -#define PORT_INT0LVL_gp 0 /* Port Interrupt 0 Level group position. */ -#define PORT_INT0LVL0_bm (1<<0) /* Port Interrupt 0 Level bit 0 mask. */ -#define PORT_INT0LVL0_bp 0 /* Port Interrupt 0 Level bit 0 position. */ -#define PORT_INT0LVL1_bm (1<<1) /* Port Interrupt 0 Level bit 1 mask. */ -#define PORT_INT0LVL1_bp 1 /* Port Interrupt 0 Level bit 1 position. */ - - -/* PORT.INTFLAGS bit masks and bit positions */ -#define PORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ -#define PORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ - -#define PORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ -#define PORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ - - -/* PORT.PIN0CTRL bit masks and bit positions */ -#define PORT_SRLEN_bm 0x80 /* Slew Rate Enable bit mask. */ -#define PORT_SRLEN_bp 7 /* Slew Rate Enable bit position. */ - -#define PORT_INVEN_bm 0x40 /* Inverted I/O Enable bit mask. */ -#define PORT_INVEN_bp 6 /* Inverted I/O Enable bit position. */ - -#define PORT_OPC_gm 0x38 /* Output/Pull Configuration group mask. */ -#define PORT_OPC_gp 3 /* Output/Pull Configuration group position. */ -#define PORT_OPC0_bm (1<<3) /* Output/Pull Configuration bit 0 mask. */ -#define PORT_OPC0_bp 3 /* Output/Pull Configuration bit 0 position. */ -#define PORT_OPC1_bm (1<<4) /* Output/Pull Configuration bit 1 mask. */ -#define PORT_OPC1_bp 4 /* Output/Pull Configuration bit 1 position. */ -#define PORT_OPC2_bm (1<<5) /* Output/Pull Configuration bit 2 mask. */ -#define PORT_OPC2_bp 5 /* Output/Pull Configuration bit 2 position. */ - -#define PORT_ISC_gm 0x07 /* Input/Sense Configuration group mask. */ -#define PORT_ISC_gp 0 /* Input/Sense Configuration group position. */ -#define PORT_ISC0_bm (1<<0) /* Input/Sense Configuration bit 0 mask. */ -#define PORT_ISC0_bp 0 /* Input/Sense Configuration bit 0 position. */ -#define PORT_ISC1_bm (1<<1) /* Input/Sense Configuration bit 1 mask. */ -#define PORT_ISC1_bp 1 /* Input/Sense Configuration bit 1 position. */ -#define PORT_ISC2_bm (1<<2) /* Input/Sense Configuration bit 2 mask. */ -#define PORT_ISC2_bp 2 /* Input/Sense Configuration bit 2 position. */ - - -/* PORT.PIN1CTRL bit masks and bit positions */ -/* PORT_SRLEN_bm Predefined. */ -/* PORT_SRLEN_bp Predefined. */ - -/* PORT_INVEN_bm Predefined. */ -/* PORT_INVEN_bp Predefined. */ - -/* PORT_OPC_gm Predefined. */ -/* PORT_OPC_gp Predefined. */ -/* PORT_OPC0_bm Predefined. */ -/* PORT_OPC0_bp Predefined. */ -/* PORT_OPC1_bm Predefined. */ -/* PORT_OPC1_bp Predefined. */ -/* PORT_OPC2_bm Predefined. */ -/* PORT_OPC2_bp Predefined. */ - -/* PORT_ISC_gm Predefined. */ -/* PORT_ISC_gp Predefined. */ -/* PORT_ISC0_bm Predefined. */ -/* PORT_ISC0_bp Predefined. */ -/* PORT_ISC1_bm Predefined. */ -/* PORT_ISC1_bp Predefined. */ -/* PORT_ISC2_bm Predefined. */ -/* PORT_ISC2_bp Predefined. */ - - -/* PORT.PIN2CTRL bit masks and bit positions */ -/* PORT_SRLEN_bm Predefined. */ -/* PORT_SRLEN_bp Predefined. */ - -/* PORT_INVEN_bm Predefined. */ -/* PORT_INVEN_bp Predefined. */ - -/* PORT_OPC_gm Predefined. */ -/* PORT_OPC_gp Predefined. */ -/* PORT_OPC0_bm Predefined. */ -/* PORT_OPC0_bp Predefined. */ -/* PORT_OPC1_bm Predefined. */ -/* PORT_OPC1_bp Predefined. */ -/* PORT_OPC2_bm Predefined. */ -/* PORT_OPC2_bp Predefined. */ - -/* PORT_ISC_gm Predefined. */ -/* PORT_ISC_gp Predefined. */ -/* PORT_ISC0_bm Predefined. */ -/* PORT_ISC0_bp Predefined. */ -/* PORT_ISC1_bm Predefined. */ -/* PORT_ISC1_bp Predefined. */ -/* PORT_ISC2_bm Predefined. */ -/* PORT_ISC2_bp Predefined. */ - - -/* PORT.PIN3CTRL bit masks and bit positions */ -/* PORT_SRLEN_bm Predefined. */ -/* PORT_SRLEN_bp Predefined. */ - -/* PORT_INVEN_bm Predefined. */ -/* PORT_INVEN_bp Predefined. */ - -/* PORT_OPC_gm Predefined. */ -/* PORT_OPC_gp Predefined. */ -/* PORT_OPC0_bm Predefined. */ -/* PORT_OPC0_bp Predefined. */ -/* PORT_OPC1_bm Predefined. */ -/* PORT_OPC1_bp Predefined. */ -/* PORT_OPC2_bm Predefined. */ -/* PORT_OPC2_bp Predefined. */ - -/* PORT_ISC_gm Predefined. */ -/* PORT_ISC_gp Predefined. */ -/* PORT_ISC0_bm Predefined. */ -/* PORT_ISC0_bp Predefined. */ -/* PORT_ISC1_bm Predefined. */ -/* PORT_ISC1_bp Predefined. */ -/* PORT_ISC2_bm Predefined. */ -/* PORT_ISC2_bp Predefined. */ - - -/* PORT.PIN4CTRL bit masks and bit positions */ -/* PORT_SRLEN_bm Predefined. */ -/* PORT_SRLEN_bp Predefined. */ - -/* PORT_INVEN_bm Predefined. */ -/* PORT_INVEN_bp Predefined. */ - -/* PORT_OPC_gm Predefined. */ -/* PORT_OPC_gp Predefined. */ -/* PORT_OPC0_bm Predefined. */ -/* PORT_OPC0_bp Predefined. */ -/* PORT_OPC1_bm Predefined. */ -/* PORT_OPC1_bp Predefined. */ -/* PORT_OPC2_bm Predefined. */ -/* PORT_OPC2_bp Predefined. */ - -/* PORT_ISC_gm Predefined. */ -/* PORT_ISC_gp Predefined. */ -/* PORT_ISC0_bm Predefined. */ -/* PORT_ISC0_bp Predefined. */ -/* PORT_ISC1_bm Predefined. */ -/* PORT_ISC1_bp Predefined. */ -/* PORT_ISC2_bm Predefined. */ -/* PORT_ISC2_bp Predefined. */ - - -/* PORT.PIN5CTRL bit masks and bit positions */ -/* PORT_SRLEN_bm Predefined. */ -/* PORT_SRLEN_bp Predefined. */ - -/* PORT_INVEN_bm Predefined. */ -/* PORT_INVEN_bp Predefined. */ - -/* PORT_OPC_gm Predefined. */ -/* PORT_OPC_gp Predefined. */ -/* PORT_OPC0_bm Predefined. */ -/* PORT_OPC0_bp Predefined. */ -/* PORT_OPC1_bm Predefined. */ -/* PORT_OPC1_bp Predefined. */ -/* PORT_OPC2_bm Predefined. */ -/* PORT_OPC2_bp Predefined. */ - -/* PORT_ISC_gm Predefined. */ -/* PORT_ISC_gp Predefined. */ -/* PORT_ISC0_bm Predefined. */ -/* PORT_ISC0_bp Predefined. */ -/* PORT_ISC1_bm Predefined. */ -/* PORT_ISC1_bp Predefined. */ -/* PORT_ISC2_bm Predefined. */ -/* PORT_ISC2_bp Predefined. */ - - -/* PORT.PIN6CTRL bit masks and bit positions */ -/* PORT_SRLEN_bm Predefined. */ -/* PORT_SRLEN_bp Predefined. */ - -/* PORT_INVEN_bm Predefined. */ -/* PORT_INVEN_bp Predefined. */ - -/* PORT_OPC_gm Predefined. */ -/* PORT_OPC_gp Predefined. */ -/* PORT_OPC0_bm Predefined. */ -/* PORT_OPC0_bp Predefined. */ -/* PORT_OPC1_bm Predefined. */ -/* PORT_OPC1_bp Predefined. */ -/* PORT_OPC2_bm Predefined. */ -/* PORT_OPC2_bp Predefined. */ - -/* PORT_ISC_gm Predefined. */ -/* PORT_ISC_gp Predefined. */ -/* PORT_ISC0_bm Predefined. */ -/* PORT_ISC0_bp Predefined. */ -/* PORT_ISC1_bm Predefined. */ -/* PORT_ISC1_bp Predefined. */ -/* PORT_ISC2_bm Predefined. */ -/* PORT_ISC2_bp Predefined. */ - - -/* PORT.PIN7CTRL bit masks and bit positions */ -/* PORT_SRLEN_bm Predefined. */ -/* PORT_SRLEN_bp Predefined. */ - -/* PORT_INVEN_bm Predefined. */ -/* PORT_INVEN_bp Predefined. */ - -/* PORT_OPC_gm Predefined. */ -/* PORT_OPC_gp Predefined. */ -/* PORT_OPC0_bm Predefined. */ -/* PORT_OPC0_bp Predefined. */ -/* PORT_OPC1_bm Predefined. */ -/* PORT_OPC1_bp Predefined. */ -/* PORT_OPC2_bm Predefined. */ -/* PORT_OPC2_bp Predefined. */ - -/* PORT_ISC_gm Predefined. */ -/* PORT_ISC_gp Predefined. */ -/* PORT_ISC0_bm Predefined. */ -/* PORT_ISC0_bp Predefined. */ -/* PORT_ISC1_bm Predefined. */ -/* PORT_ISC1_bp Predefined. */ -/* PORT_ISC2_bm Predefined. */ -/* PORT_ISC2_bp Predefined. */ - - -/* TC - 16-bit Timer/Counter With PWM */ -/* TC0.CTRLA bit masks and bit positions */ -#define TC0_CLKSEL_gm 0x0F /* Clock Selection group mask. */ -#define TC0_CLKSEL_gp 0 /* Clock Selection group position. */ -#define TC0_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ -#define TC0_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ -#define TC0_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ -#define TC0_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ -#define TC0_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ -#define TC0_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ -#define TC0_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ -#define TC0_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ - - -/* TC0.CTRLB bit masks and bit positions */ -#define TC0_CCDEN_bm 0x80 /* Compare or Capture D Enable bit mask. */ -#define TC0_CCDEN_bp 7 /* Compare or Capture D Enable bit position. */ - -#define TC0_CCCEN_bm 0x40 /* Compare or Capture C Enable bit mask. */ -#define TC0_CCCEN_bp 6 /* Compare or Capture C Enable bit position. */ - -#define TC0_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ -#define TC0_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ - -#define TC0_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ -#define TC0_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ - -#define TC0_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ -#define TC0_WGMODE_gp 0 /* Waveform generation mode group position. */ -#define TC0_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ -#define TC0_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ -#define TC0_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ -#define TC0_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ -#define TC0_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ -#define TC0_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ - - -/* TC0.CTRLC bit masks and bit positions */ -#define TC0_CMPD_bm 0x08 /* Compare D Output Value bit mask. */ -#define TC0_CMPD_bp 3 /* Compare D Output Value bit position. */ - -#define TC0_CMPC_bm 0x04 /* Compare C Output Value bit mask. */ -#define TC0_CMPC_bp 2 /* Compare C Output Value bit position. */ - -#define TC0_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ -#define TC0_CMPB_bp 1 /* Compare B Output Value bit position. */ - -#define TC0_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ -#define TC0_CMPA_bp 0 /* Compare A Output Value bit position. */ - - -/* TC0.CTRLD bit masks and bit positions */ -#define TC0_EVACT_gm 0xE0 /* Event Action group mask. */ -#define TC0_EVACT_gp 5 /* Event Action group position. */ -#define TC0_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ -#define TC0_EVACT0_bp 5 /* Event Action bit 0 position. */ -#define TC0_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ -#define TC0_EVACT1_bp 6 /* Event Action bit 1 position. */ -#define TC0_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ -#define TC0_EVACT2_bp 7 /* Event Action bit 2 position. */ - -#define TC0_EVDLY_bm 0x10 /* Event Delay bit mask. */ -#define TC0_EVDLY_bp 4 /* Event Delay bit position. */ - -#define TC0_EVSEL_gm 0x0F /* Event Source Select group mask. */ -#define TC0_EVSEL_gp 0 /* Event Source Select group position. */ -#define TC0_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ -#define TC0_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ -#define TC0_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ -#define TC0_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ -#define TC0_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ -#define TC0_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ -#define TC0_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ -#define TC0_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ - - -/* TC0.CTRLE bit masks and bit positions */ -#define TC0_DTHM_bm 0x02 /* Dead Time Hold Mode bit mask. */ -#define TC0_DTHM_bp 1 /* Dead Time Hold Mode bit position. */ - -#define TC0_BYTEM_bm 0x01 /* Byte Mode bit mask. */ -#define TC0_BYTEM_bp 0 /* Byte Mode bit position. */ - - -/* TC0.INTCTRLA bit masks and bit positions */ -#define TC0_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ -#define TC0_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ -#define TC0_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ -#define TC0_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ -#define TC0_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ -#define TC0_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ - -#define TC0_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ -#define TC0_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ -#define TC0_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ -#define TC0_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ -#define TC0_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ -#define TC0_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ - - -/* TC0.INTCTRLB bit masks and bit positions */ -#define TC0_CCDINTLVL_gm 0xC0 /* Compare or Capture D Interrupt Level group mask. */ -#define TC0_CCDINTLVL_gp 6 /* Compare or Capture D Interrupt Level group position. */ -#define TC0_CCDINTLVL0_bm (1<<6) /* Compare or Capture D Interrupt Level bit 0 mask. */ -#define TC0_CCDINTLVL0_bp 6 /* Compare or Capture D Interrupt Level bit 0 position. */ -#define TC0_CCDINTLVL1_bm (1<<7) /* Compare or Capture D Interrupt Level bit 1 mask. */ -#define TC0_CCDINTLVL1_bp 7 /* Compare or Capture D Interrupt Level bit 1 position. */ - -#define TC0_CCCINTLVL_gm 0x30 /* Compare or Capture C Interrupt Level group mask. */ -#define TC0_CCCINTLVL_gp 4 /* Compare or Capture C Interrupt Level group position. */ -#define TC0_CCCINTLVL0_bm (1<<4) /* Compare or Capture C Interrupt Level bit 0 mask. */ -#define TC0_CCCINTLVL0_bp 4 /* Compare or Capture C Interrupt Level bit 0 position. */ -#define TC0_CCCINTLVL1_bm (1<<5) /* Compare or Capture C Interrupt Level bit 1 mask. */ -#define TC0_CCCINTLVL1_bp 5 /* Compare or Capture C Interrupt Level bit 1 position. */ - -#define TC0_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ -#define TC0_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ -#define TC0_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ -#define TC0_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ -#define TC0_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ -#define TC0_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ - -#define TC0_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ -#define TC0_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ -#define TC0_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ -#define TC0_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ -#define TC0_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ -#define TC0_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ - - -/* TC0.CTRLFCLR bit masks and bit positions */ -#define TC0_CMD_gm 0x0C /* Command group mask. */ -#define TC0_CMD_gp 2 /* Command group position. */ -#define TC0_CMD0_bm (1<<2) /* Command bit 0 mask. */ -#define TC0_CMD0_bp 2 /* Command bit 0 position. */ -#define TC0_CMD1_bm (1<<3) /* Command bit 1 mask. */ -#define TC0_CMD1_bp 3 /* Command bit 1 position. */ - -#define TC0_LUPD_bm 0x02 /* Lock Update bit mask. */ -#define TC0_LUPD_bp 1 /* Lock Update bit position. */ - -#define TC0_DIR_bm 0x01 /* Direction bit mask. */ -#define TC0_DIR_bp 0 /* Direction bit position. */ - - -/* TC0.CTRLFSET bit masks and bit positions */ -/* TC0_CMD_gm Predefined. */ -/* TC0_CMD_gp Predefined. */ -/* TC0_CMD0_bm Predefined. */ -/* TC0_CMD0_bp Predefined. */ -/* TC0_CMD1_bm Predefined. */ -/* TC0_CMD1_bp Predefined. */ - -/* TC0_LUPD_bm Predefined. */ -/* TC0_LUPD_bp Predefined. */ - -/* TC0_DIR_bm Predefined. */ -/* TC0_DIR_bp Predefined. */ - - -/* TC0.CTRLGCLR bit masks and bit positions */ -#define TC0_CCDBV_bm 0x10 /* Compare or Capture D Buffer Valid bit mask. */ -#define TC0_CCDBV_bp 4 /* Compare or Capture D Buffer Valid bit position. */ - -#define TC0_CCCBV_bm 0x08 /* Compare or Capture C Buffer Valid bit mask. */ -#define TC0_CCCBV_bp 3 /* Compare or Capture C Buffer Valid bit position. */ - -#define TC0_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ -#define TC0_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ - -#define TC0_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ -#define TC0_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ - -#define TC0_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ -#define TC0_PERBV_bp 0 /* Period Buffer Valid bit position. */ - - -/* TC0.CTRLGSET bit masks and bit positions */ -/* TC0_CCDBV_bm Predefined. */ -/* TC0_CCDBV_bp Predefined. */ - -/* TC0_CCCBV_bm Predefined. */ -/* TC0_CCCBV_bp Predefined. */ - -/* TC0_CCBBV_bm Predefined. */ -/* TC0_CCBBV_bp Predefined. */ - -/* TC0_CCABV_bm Predefined. */ -/* TC0_CCABV_bp Predefined. */ - -/* TC0_PERBV_bm Predefined. */ -/* TC0_PERBV_bp Predefined. */ - - -/* TC0.INTFLAGS bit masks and bit positions */ -#define TC0_CCDIF_bm 0x80 /* Compare or Capture D Interrupt Flag bit mask. */ -#define TC0_CCDIF_bp 7 /* Compare or Capture D Interrupt Flag bit position. */ - -#define TC0_CCCIF_bm 0x40 /* Compare or Capture C Interrupt Flag bit mask. */ -#define TC0_CCCIF_bp 6 /* Compare or Capture C Interrupt Flag bit position. */ - -#define TC0_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ -#define TC0_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ - -#define TC0_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ -#define TC0_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ - -#define TC0_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ -#define TC0_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ - -#define TC0_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ -#define TC0_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ - - -/* TC1.CTRLA bit masks and bit positions */ -#define TC1_CLKSEL_gm 0x0F /* Clock Selection group mask. */ -#define TC1_CLKSEL_gp 0 /* Clock Selection group position. */ -#define TC1_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ -#define TC1_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ -#define TC1_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ -#define TC1_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ -#define TC1_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ -#define TC1_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ -#define TC1_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ -#define TC1_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ - - -/* TC1.CTRLB bit masks and bit positions */ -#define TC1_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ -#define TC1_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ - -#define TC1_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ -#define TC1_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ - -#define TC1_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ -#define TC1_WGMODE_gp 0 /* Waveform generation mode group position. */ -#define TC1_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ -#define TC1_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ -#define TC1_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ -#define TC1_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ -#define TC1_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ -#define TC1_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ - - -/* TC1.CTRLC bit masks and bit positions */ -#define TC1_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ -#define TC1_CMPB_bp 1 /* Compare B Output Value bit position. */ - -#define TC1_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ -#define TC1_CMPA_bp 0 /* Compare A Output Value bit position. */ - - -/* TC1.CTRLD bit masks and bit positions */ -#define TC1_EVACT_gm 0xE0 /* Event Action group mask. */ -#define TC1_EVACT_gp 5 /* Event Action group position. */ -#define TC1_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ -#define TC1_EVACT0_bp 5 /* Event Action bit 0 position. */ -#define TC1_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ -#define TC1_EVACT1_bp 6 /* Event Action bit 1 position. */ -#define TC1_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ -#define TC1_EVACT2_bp 7 /* Event Action bit 2 position. */ - -#define TC1_EVDLY_bm 0x10 /* Event Delay bit mask. */ -#define TC1_EVDLY_bp 4 /* Event Delay bit position. */ - -#define TC1_EVSEL_gm 0x0F /* Event Source Select group mask. */ -#define TC1_EVSEL_gp 0 /* Event Source Select group position. */ -#define TC1_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ -#define TC1_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ -#define TC1_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ -#define TC1_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ -#define TC1_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ -#define TC1_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ -#define TC1_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ -#define TC1_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ - - -/* TC1.CTRLE bit masks and bit positions */ -#define TC1_DTHM_bm 0x02 /* Dead Time Hold Mode bit mask. */ -#define TC1_DTHM_bp 1 /* Dead Time Hold Mode bit position. */ - -#define TC1_BYTEM_bm 0x01 /* Byte Mode bit mask. */ -#define TC1_BYTEM_bp 0 /* Byte Mode bit position. */ - - -/* TC1.INTCTRLA bit masks and bit positions */ -#define TC1_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ -#define TC1_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ -#define TC1_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ -#define TC1_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ -#define TC1_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ -#define TC1_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ - -#define TC1_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ -#define TC1_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ -#define TC1_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ -#define TC1_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ -#define TC1_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ -#define TC1_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ - - -/* TC1.INTCTRLB bit masks and bit positions */ -#define TC1_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ -#define TC1_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ -#define TC1_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ -#define TC1_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ -#define TC1_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ -#define TC1_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ - -#define TC1_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ -#define TC1_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ -#define TC1_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ -#define TC1_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ -#define TC1_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ -#define TC1_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ - - -/* TC1.CTRLFCLR bit masks and bit positions */ -#define TC1_CMD_gm 0x0C /* Command group mask. */ -#define TC1_CMD_gp 2 /* Command group position. */ -#define TC1_CMD0_bm (1<<2) /* Command bit 0 mask. */ -#define TC1_CMD0_bp 2 /* Command bit 0 position. */ -#define TC1_CMD1_bm (1<<3) /* Command bit 1 mask. */ -#define TC1_CMD1_bp 3 /* Command bit 1 position. */ - -#define TC1_LUPD_bm 0x02 /* Lock Update bit mask. */ -#define TC1_LUPD_bp 1 /* Lock Update bit position. */ - -#define TC1_DIR_bm 0x01 /* Direction bit mask. */ -#define TC1_DIR_bp 0 /* Direction bit position. */ - - -/* TC1.CTRLFSET bit masks and bit positions */ -/* TC1_CMD_gm Predefined. */ -/* TC1_CMD_gp Predefined. */ -/* TC1_CMD0_bm Predefined. */ -/* TC1_CMD0_bp Predefined. */ -/* TC1_CMD1_bm Predefined. */ -/* TC1_CMD1_bp Predefined. */ - -/* TC1_LUPD_bm Predefined. */ -/* TC1_LUPD_bp Predefined. */ - -/* TC1_DIR_bm Predefined. */ -/* TC1_DIR_bp Predefined. */ - - -/* TC1.CTRLGCLR bit masks and bit positions */ -#define TC1_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ -#define TC1_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ - -#define TC1_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ -#define TC1_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ - -#define TC1_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ -#define TC1_PERBV_bp 0 /* Period Buffer Valid bit position. */ - - -/* TC1.CTRLGSET bit masks and bit positions */ -/* TC1_CCBBV_bm Predefined. */ -/* TC1_CCBBV_bp Predefined. */ - -/* TC1_CCABV_bm Predefined. */ -/* TC1_CCABV_bp Predefined. */ - -/* TC1_PERBV_bm Predefined. */ -/* TC1_PERBV_bp Predefined. */ - - -/* TC1.INTFLAGS bit masks and bit positions */ -#define TC1_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ -#define TC1_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ - -#define TC1_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ -#define TC1_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ - -#define TC1_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ -#define TC1_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ - -#define TC1_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ -#define TC1_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ - - -/* AWEX.CTRL bit masks and bit positions */ -#define AWEX_PGM_bm 0x20 /* Pattern Generation Mode bit mask. */ -#define AWEX_PGM_bp 5 /* Pattern Generation Mode bit position. */ - -#define AWEX_CWCM_bm 0x10 /* Common Waveform Channel Mode bit mask. */ -#define AWEX_CWCM_bp 4 /* Common Waveform Channel Mode bit position. */ - -#define AWEX_DTICCDEN_bm 0x08 /* Dead Time Insertion Compare Channel D Enable bit mask. */ -#define AWEX_DTICCDEN_bp 3 /* Dead Time Insertion Compare Channel D Enable bit position. */ - -#define AWEX_DTICCCEN_bm 0x04 /* Dead Time Insertion Compare Channel C Enable bit mask. */ -#define AWEX_DTICCCEN_bp 2 /* Dead Time Insertion Compare Channel C Enable bit position. */ - -#define AWEX_DTICCBEN_bm 0x02 /* Dead Time Insertion Compare Channel B Enable bit mask. */ -#define AWEX_DTICCBEN_bp 1 /* Dead Time Insertion Compare Channel B Enable bit position. */ - -#define AWEX_DTICCAEN_bm 0x01 /* Dead Time Insertion Compare Channel A Enable bit mask. */ -#define AWEX_DTICCAEN_bp 0 /* Dead Time Insertion Compare Channel A Enable bit position. */ - - -/* AWEX.FDCTRL bit masks and bit positions */ -#define AWEX_FDDBD_bm 0x10 /* Fault Detect on Disable Break Disable bit mask. */ -#define AWEX_FDDBD_bp 4 /* Fault Detect on Disable Break Disable bit position. */ - -#define AWEX_FDMODE_bm 0x04 /* Fault Detect Mode bit mask. */ -#define AWEX_FDMODE_bp 2 /* Fault Detect Mode bit position. */ - -#define AWEX_FDACT_gm 0x03 /* Fault Detect Action group mask. */ -#define AWEX_FDACT_gp 0 /* Fault Detect Action group position. */ -#define AWEX_FDACT0_bm (1<<0) /* Fault Detect Action bit 0 mask. */ -#define AWEX_FDACT0_bp 0 /* Fault Detect Action bit 0 position. */ -#define AWEX_FDACT1_bm (1<<1) /* Fault Detect Action bit 1 mask. */ -#define AWEX_FDACT1_bp 1 /* Fault Detect Action bit 1 position. */ - - -/* AWEX.STATUS bit masks and bit positions */ -#define AWEX_FDF_bm 0x04 /* Fault Detect Flag bit mask. */ -#define AWEX_FDF_bp 2 /* Fault Detect Flag bit position. */ - -#define AWEX_DTHSBUFV_bm 0x02 /* Dead Time High Side Buffer Valid bit mask. */ -#define AWEX_DTHSBUFV_bp 1 /* Dead Time High Side Buffer Valid bit position. */ - -#define AWEX_DTLSBUFV_bm 0x01 /* Dead Time Low Side Buffer Valid bit mask. */ -#define AWEX_DTLSBUFV_bp 0 /* Dead Time Low Side Buffer Valid bit position. */ - - -/* HIRES.CTRL bit masks and bit positions */ -#define HIRES_HREN_gm 0x03 /* High Resolution Enable group mask. */ -#define HIRES_HREN_gp 0 /* High Resolution Enable group position. */ -#define HIRES_HREN0_bm (1<<0) /* High Resolution Enable bit 0 mask. */ -#define HIRES_HREN0_bp 0 /* High Resolution Enable bit 0 position. */ -#define HIRES_HREN1_bm (1<<1) /* High Resolution Enable bit 1 mask. */ -#define HIRES_HREN1_bp 1 /* High Resolution Enable bit 1 position. */ - - -/* USART - Universal Asynchronous Receiver-Transmitter */ -/* USART.STATUS bit masks and bit positions */ -#define USART_RXCIF_bm 0x80 /* Receive Interrupt Flag bit mask. */ -#define USART_RXCIF_bp 7 /* Receive Interrupt Flag bit position. */ - -#define USART_TXCIF_bm 0x40 /* Transmit Interrupt Flag bit mask. */ -#define USART_TXCIF_bp 6 /* Transmit Interrupt Flag bit position. */ - -#define USART_DREIF_bm 0x20 /* Data Register Empty Flag bit mask. */ -#define USART_DREIF_bp 5 /* Data Register Empty Flag bit position. */ - -#define USART_FERR_bm 0x10 /* Frame Error bit mask. */ -#define USART_FERR_bp 4 /* Frame Error bit position. */ - -#define USART_BUFOVF_bm 0x08 /* Buffer Overflow bit mask. */ -#define USART_BUFOVF_bp 3 /* Buffer Overflow bit position. */ - -#define USART_PERR_bm 0x04 /* Parity Error bit mask. */ -#define USART_PERR_bp 2 /* Parity Error bit position. */ - -#define USART_RXB8_bm 0x01 /* Receive Bit 8 bit mask. */ -#define USART_RXB8_bp 0 /* Receive Bit 8 bit position. */ - - -/* USART.CTRLA bit masks and bit positions */ -#define USART_RXCINTLVL_gm 0x30 /* Receive Interrupt Level group mask. */ -#define USART_RXCINTLVL_gp 4 /* Receive Interrupt Level group position. */ -#define USART_RXCINTLVL0_bm (1<<4) /* Receive Interrupt Level bit 0 mask. */ -#define USART_RXCINTLVL0_bp 4 /* Receive Interrupt Level bit 0 position. */ -#define USART_RXCINTLVL1_bm (1<<5) /* Receive Interrupt Level bit 1 mask. */ -#define USART_RXCINTLVL1_bp 5 /* Receive Interrupt Level bit 1 position. */ - -#define USART_TXCINTLVL_gm 0x0C /* Transmit Interrupt Level group mask. */ -#define USART_TXCINTLVL_gp 2 /* Transmit Interrupt Level group position. */ -#define USART_TXCINTLVL0_bm (1<<2) /* Transmit Interrupt Level bit 0 mask. */ -#define USART_TXCINTLVL0_bp 2 /* Transmit Interrupt Level bit 0 position. */ -#define USART_TXCINTLVL1_bm (1<<3) /* Transmit Interrupt Level bit 1 mask. */ -#define USART_TXCINTLVL1_bp 3 /* Transmit Interrupt Level bit 1 position. */ - -#define USART_DREINTLVL_gm 0x03 /* Data Register Empty Interrupt Level group mask. */ -#define USART_DREINTLVL_gp 0 /* Data Register Empty Interrupt Level group position. */ -#define USART_DREINTLVL0_bm (1<<0) /* Data Register Empty Interrupt Level bit 0 mask. */ -#define USART_DREINTLVL0_bp 0 /* Data Register Empty Interrupt Level bit 0 position. */ -#define USART_DREINTLVL1_bm (1<<1) /* Data Register Empty Interrupt Level bit 1 mask. */ -#define USART_DREINTLVL1_bp 1 /* Data Register Empty Interrupt Level bit 1 position. */ - - -/* USART.CTRLB bit masks and bit positions */ -#define USART_RXEN_bm 0x10 /* Receiver Enable bit mask. */ -#define USART_RXEN_bp 4 /* Receiver Enable bit position. */ - -#define USART_TXEN_bm 0x08 /* Transmitter Enable bit mask. */ -#define USART_TXEN_bp 3 /* Transmitter Enable bit position. */ - -#define USART_CLK2X_bm 0x04 /* Double transmission speed bit mask. */ -#define USART_CLK2X_bp 2 /* Double transmission speed bit position. */ - -#define USART_MPCM_bm 0x02 /* Multi-processor Communication Mode bit mask. */ -#define USART_MPCM_bp 1 /* Multi-processor Communication Mode bit position. */ - -#define USART_TXB8_bm 0x01 /* Transmit bit 8 bit mask. */ -#define USART_TXB8_bp 0 /* Transmit bit 8 bit position. */ - - -/* USART.CTRLC bit masks and bit positions */ -#define USART_CMODE_gm 0xC0 /* Communication Mode group mask. */ -#define USART_CMODE_gp 6 /* Communication Mode group position. */ -#define USART_CMODE0_bm (1<<6) /* Communication Mode bit 0 mask. */ -#define USART_CMODE0_bp 6 /* Communication Mode bit 0 position. */ -#define USART_CMODE1_bm (1<<7) /* Communication Mode bit 1 mask. */ -#define USART_CMODE1_bp 7 /* Communication Mode bit 1 position. */ - -#define USART_PMODE_gm 0x30 /* Parity Mode group mask. */ -#define USART_PMODE_gp 4 /* Parity Mode group position. */ -#define USART_PMODE0_bm (1<<4) /* Parity Mode bit 0 mask. */ -#define USART_PMODE0_bp 4 /* Parity Mode bit 0 position. */ -#define USART_PMODE1_bm (1<<5) /* Parity Mode bit 1 mask. */ -#define USART_PMODE1_bp 5 /* Parity Mode bit 1 position. */ - -#define USART_SBMODE_bm 0x08 /* Stop Bit Mode bit mask. */ -#define USART_SBMODE_bp 3 /* Stop Bit Mode bit position. */ - -#define USART_CHSIZE_gm 0x07 /* Character Size group mask. */ -#define USART_CHSIZE_gp 0 /* Character Size group position. */ -#define USART_CHSIZE0_bm (1<<0) /* Character Size bit 0 mask. */ -#define USART_CHSIZE0_bp 0 /* Character Size bit 0 position. */ -#define USART_CHSIZE1_bm (1<<1) /* Character Size bit 1 mask. */ -#define USART_CHSIZE1_bp 1 /* Character Size bit 1 position. */ -#define USART_CHSIZE2_bm (1<<2) /* Character Size bit 2 mask. */ -#define USART_CHSIZE2_bp 2 /* Character Size bit 2 position. */ - - -/* USART.BAUDCTRLA bit masks and bit positions */ -#define USART_BSEL_gm 0xFF /* Baud Rate Selection Bits [7:0] group mask. */ -#define USART_BSEL_gp 0 /* Baud Rate Selection Bits [7:0] group position. */ -#define USART_BSEL0_bm (1<<0) /* Baud Rate Selection Bits [7:0] bit 0 mask. */ -#define USART_BSEL0_bp 0 /* Baud Rate Selection Bits [7:0] bit 0 position. */ -#define USART_BSEL1_bm (1<<1) /* Baud Rate Selection Bits [7:0] bit 1 mask. */ -#define USART_BSEL1_bp 1 /* Baud Rate Selection Bits [7:0] bit 1 position. */ -#define USART_BSEL2_bm (1<<2) /* Baud Rate Selection Bits [7:0] bit 2 mask. */ -#define USART_BSEL2_bp 2 /* Baud Rate Selection Bits [7:0] bit 2 position. */ -#define USART_BSEL3_bm (1<<3) /* Baud Rate Selection Bits [7:0] bit 3 mask. */ -#define USART_BSEL3_bp 3 /* Baud Rate Selection Bits [7:0] bit 3 position. */ -#define USART_BSEL4_bm (1<<4) /* Baud Rate Selection Bits [7:0] bit 4 mask. */ -#define USART_BSEL4_bp 4 /* Baud Rate Selection Bits [7:0] bit 4 position. */ -#define USART_BSEL5_bm (1<<5) /* Baud Rate Selection Bits [7:0] bit 5 mask. */ -#define USART_BSEL5_bp 5 /* Baud Rate Selection Bits [7:0] bit 5 position. */ -#define USART_BSEL6_bm (1<<6) /* Baud Rate Selection Bits [7:0] bit 6 mask. */ -#define USART_BSEL6_bp 6 /* Baud Rate Selection Bits [7:0] bit 6 position. */ -#define USART_BSEL7_bm (1<<7) /* Baud Rate Selection Bits [7:0] bit 7 mask. */ -#define USART_BSEL7_bp 7 /* Baud Rate Selection Bits [7:0] bit 7 position. */ - - -/* USART.BAUDCTRLB bit masks and bit positions */ -#define USART_BSCALE_gm 0xF0 /* Baud Rate Scale group mask. */ -#define USART_BSCALE_gp 4 /* Baud Rate Scale group position. */ -#define USART_BSCALE0_bm (1<<4) /* Baud Rate Scale bit 0 mask. */ -#define USART_BSCALE0_bp 4 /* Baud Rate Scale bit 0 position. */ -#define USART_BSCALE1_bm (1<<5) /* Baud Rate Scale bit 1 mask. */ -#define USART_BSCALE1_bp 5 /* Baud Rate Scale bit 1 position. */ -#define USART_BSCALE2_bm (1<<6) /* Baud Rate Scale bit 2 mask. */ -#define USART_BSCALE2_bp 6 /* Baud Rate Scale bit 2 position. */ -#define USART_BSCALE3_bm (1<<7) /* Baud Rate Scale bit 3 mask. */ -#define USART_BSCALE3_bp 7 /* Baud Rate Scale bit 3 position. */ - -/* USART_BSEL_gm Predefined. */ -/* USART_BSEL_gp Predefined. */ -/* USART_BSEL0_bm Predefined. */ -/* USART_BSEL0_bp Predefined. */ -/* USART_BSEL1_bm Predefined. */ -/* USART_BSEL1_bp Predefined. */ -/* USART_BSEL2_bm Predefined. */ -/* USART_BSEL2_bp Predefined. */ -/* USART_BSEL3_bm Predefined. */ -/* USART_BSEL3_bp Predefined. */ - - -/* SPI - Serial Peripheral Interface */ -/* SPI.CTRL bit masks and bit positions */ -#define SPI_CLK2X_bm 0x80 /* Enable Double Speed bit mask. */ -#define SPI_CLK2X_bp 7 /* Enable Double Speed bit position. */ - -#define SPI_ENABLE_bm 0x40 /* Enable Module bit mask. */ -#define SPI_ENABLE_bp 6 /* Enable Module bit position. */ - -#define SPI_DORD_bm 0x20 /* Data Order Setting bit mask. */ -#define SPI_DORD_bp 5 /* Data Order Setting bit position. */ - -#define SPI_MASTER_bm 0x10 /* Master Operation Enable bit mask. */ -#define SPI_MASTER_bp 4 /* Master Operation Enable bit position. */ - -#define SPI_MODE_gm 0x0C /* SPI Mode group mask. */ -#define SPI_MODE_gp 2 /* SPI Mode group position. */ -#define SPI_MODE0_bm (1<<2) /* SPI Mode bit 0 mask. */ -#define SPI_MODE0_bp 2 /* SPI Mode bit 0 position. */ -#define SPI_MODE1_bm (1<<3) /* SPI Mode bit 1 mask. */ -#define SPI_MODE1_bp 3 /* SPI Mode bit 1 position. */ - -#define SPI_PRESCALER_gm 0x03 /* Prescaler group mask. */ -#define SPI_PRESCALER_gp 0 /* Prescaler group position. */ -#define SPI_PRESCALER0_bm (1<<0) /* Prescaler bit 0 mask. */ -#define SPI_PRESCALER0_bp 0 /* Prescaler bit 0 position. */ -#define SPI_PRESCALER1_bm (1<<1) /* Prescaler bit 1 mask. */ -#define SPI_PRESCALER1_bp 1 /* Prescaler bit 1 position. */ - - -/* SPI.INTCTRL bit masks and bit positions */ -#define SPI_INTLVL_gm 0x03 /* Interrupt level group mask. */ -#define SPI_INTLVL_gp 0 /* Interrupt level group position. */ -#define SPI_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */ -#define SPI_INTLVL0_bp 0 /* Interrupt level bit 0 position. */ -#define SPI_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */ -#define SPI_INTLVL1_bp 1 /* Interrupt level bit 1 position. */ - - -/* SPI.STATUS bit masks and bit positions */ -#define SPI_IF_bm 0x80 /* Interrupt Flag bit mask. */ -#define SPI_IF_bp 7 /* Interrupt Flag bit position. */ - -#define SPI_WRCOL_bm 0x40 /* Write Collision bit mask. */ -#define SPI_WRCOL_bp 6 /* Write Collision bit position. */ - - -/* IRCOM - IR Communication Module */ -/* IRCOM.CTRL bit masks and bit positions */ -#define IRCOM_EVSEL_gm 0x0F /* Event Channel Select group mask. */ -#define IRCOM_EVSEL_gp 0 /* Event Channel Select group position. */ -#define IRCOM_EVSEL0_bm (1<<0) /* Event Channel Select bit 0 mask. */ -#define IRCOM_EVSEL0_bp 0 /* Event Channel Select bit 0 position. */ -#define IRCOM_EVSEL1_bm (1<<1) /* Event Channel Select bit 1 mask. */ -#define IRCOM_EVSEL1_bp 1 /* Event Channel Select bit 1 position. */ -#define IRCOM_EVSEL2_bm (1<<2) /* Event Channel Select bit 2 mask. */ -#define IRCOM_EVSEL2_bp 2 /* Event Channel Select bit 2 position. */ -#define IRCOM_EVSEL3_bm (1<<3) /* Event Channel Select bit 3 mask. */ -#define IRCOM_EVSEL3_bp 3 /* Event Channel Select bit 3 position. */ - - -/* AES - AES Module */ -/* AES.CTRL bit masks and bit positions */ -#define AES_START_bm 0x80 /* Start/Run bit mask. */ -#define AES_START_bp 7 /* Start/Run bit position. */ - -#define AES_AUTO_bm 0x40 /* Auto Start Trigger bit mask. */ -#define AES_AUTO_bp 6 /* Auto Start Trigger bit position. */ - -#define AES_RESET_bm 0x20 /* AES Software Reset bit mask. */ -#define AES_RESET_bp 5 /* AES Software Reset bit position. */ - -#define AES_DECRYPT_bm 0x10 /* Decryption / Direction bit mask. */ -#define AES_DECRYPT_bp 4 /* Decryption / Direction bit position. */ - -#define AES_XOR_bm 0x04 /* State XOR Load Enable bit mask. */ -#define AES_XOR_bp 2 /* State XOR Load Enable bit position. */ - - -/* AES.STATUS bit masks and bit positions */ -#define AES_ERROR_bm 0x80 /* AES Error bit mask. */ -#define AES_ERROR_bp 7 /* AES Error bit position. */ - -#define AES_SRIF_bm 0x01 /* State Ready Interrupt Flag bit mask. */ -#define AES_SRIF_bp 0 /* State Ready Interrupt Flag bit position. */ - - -/* AES.INTCTRL bit masks and bit positions */ -#define AES_INTLVL_gm 0x03 /* Interrupt level group mask. */ -#define AES_INTLVL_gp 0 /* Interrupt level group position. */ -#define AES_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */ -#define AES_INTLVL0_bp 0 /* Interrupt level bit 0 position. */ -#define AES_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */ -#define AES_INTLVL1_bp 1 /* Interrupt level bit 1 position. */ - - - -// Generic Port Pins - -#define PIN0_bm 0x01 -#define PIN0_bp 0 -#define PIN1_bm 0x02 -#define PIN1_bp 1 -#define PIN2_bm 0x04 -#define PIN2_bp 2 -#define PIN3_bm 0x08 -#define PIN3_bp 3 -#define PIN4_bm 0x10 -#define PIN4_bp 4 -#define PIN5_bm 0x20 -#define PIN5_bp 5 -#define PIN6_bm 0x40 -#define PIN6_bp 6 -#define PIN7_bm 0x80 -#define PIN7_bp 7 - - -/* ========== Interrupt Vector Definitions ========== */ -/* Vector 0 is the reset vector */ - -/* OSC interrupt vectors */ -#define OSC_XOSCF_vect_num 1 -#define OSC_XOSCF_vect _VECTOR(1) /* External Oscillator Failure Interrupt (NMI) */ - -/* PORTC interrupt vectors */ -#define PORTC_INT0_vect_num 2 -#define PORTC_INT0_vect _VECTOR(2) /* External Interrupt 0 */ -#define PORTC_INT1_vect_num 3 -#define PORTC_INT1_vect _VECTOR(3) /* External Interrupt 1 */ - -/* PORTR interrupt vectors */ -#define PORTR_INT0_vect_num 4 -#define PORTR_INT0_vect _VECTOR(4) /* External Interrupt 0 */ -#define PORTR_INT1_vect_num 5 -#define PORTR_INT1_vect _VECTOR(5) /* External Interrupt 1 */ - -/* DMA interrupt vectors */ -#define DMA_CH0_vect_num 6 -#define DMA_CH0_vect _VECTOR(6) /* Channel 0 Interrupt */ -#define DMA_CH1_vect_num 7 -#define DMA_CH1_vect _VECTOR(7) /* Channel 1 Interrupt */ -#define DMA_CH2_vect_num 8 -#define DMA_CH2_vect _VECTOR(8) /* Channel 2 Interrupt */ -#define DMA_CH3_vect_num 9 -#define DMA_CH3_vect _VECTOR(9) /* Channel 3 Interrupt */ - -/* RTC interrupt vectors */ -#define RTC_OVF_vect_num 10 -#define RTC_OVF_vect _VECTOR(10) /* Overflow Interrupt */ -#define RTC_COMP_vect_num 11 -#define RTC_COMP_vect _VECTOR(11) /* Compare Interrupt */ - -/* TWIC interrupt vectors */ -#define TWIC_TWIS_vect_num 12 -#define TWIC_TWIS_vect _VECTOR(12) /* TWI Slave Interrupt */ -#define TWIC_TWIM_vect_num 13 -#define TWIC_TWIM_vect _VECTOR(13) /* TWI Master Interrupt */ - -/* TCC0 interrupt vectors */ -#define TCC0_OVF_vect_num 14 -#define TCC0_OVF_vect _VECTOR(14) /* Overflow Interrupt */ -#define TCC0_ERR_vect_num 15 -#define TCC0_ERR_vect _VECTOR(15) /* Error Interrupt */ -#define TCC0_CCA_vect_num 16 -#define TCC0_CCA_vect _VECTOR(16) /* Compare or Capture A Interrupt */ -#define TCC0_CCB_vect_num 17 -#define TCC0_CCB_vect _VECTOR(17) /* Compare or Capture B Interrupt */ -#define TCC0_CCC_vect_num 18 -#define TCC0_CCC_vect _VECTOR(18) /* Compare or Capture C Interrupt */ -#define TCC0_CCD_vect_num 19 -#define TCC0_CCD_vect _VECTOR(19) /* Compare or Capture D Interrupt */ - -/* TCC1 interrupt vectors */ -#define TCC1_OVF_vect_num 20 -#define TCC1_OVF_vect _VECTOR(20) /* Overflow Interrupt */ -#define TCC1_ERR_vect_num 21 -#define TCC1_ERR_vect _VECTOR(21) /* Error Interrupt */ -#define TCC1_CCA_vect_num 22 -#define TCC1_CCA_vect _VECTOR(22) /* Compare or Capture A Interrupt */ -#define TCC1_CCB_vect_num 23 -#define TCC1_CCB_vect _VECTOR(23) /* Compare or Capture B Interrupt */ - -/* SPIC interrupt vectors */ -#define SPIC_INT_vect_num 24 -#define SPIC_INT_vect _VECTOR(24) /* SPI Interrupt */ - -/* USARTC0 interrupt vectors */ -#define USARTC0_RXC_vect_num 25 -#define USARTC0_RXC_vect _VECTOR(25) /* Reception Complete Interrupt */ -#define USARTC0_DRE_vect_num 26 -#define USARTC0_DRE_vect _VECTOR(26) /* Data Register Empty Interrupt */ -#define USARTC0_TXC_vect_num 27 -#define USARTC0_TXC_vect _VECTOR(27) /* Transmission Complete Interrupt */ - -/* USARTC1 interrupt vectors */ -#define USARTC1_RXC_vect_num 28 -#define USARTC1_RXC_vect _VECTOR(28) /* Reception Complete Interrupt */ -#define USARTC1_DRE_vect_num 29 -#define USARTC1_DRE_vect _VECTOR(29) /* Data Register Empty Interrupt */ -#define USARTC1_TXC_vect_num 30 -#define USARTC1_TXC_vect _VECTOR(30) /* Transmission Complete Interrupt */ - -/* AES interrupt vectors */ -#define AES_INT_vect_num 31 -#define AES_INT_vect _VECTOR(31) /* AES Interrupt */ - -/* NVM interrupt vectors */ -#define NVM_EE_vect_num 32 -#define NVM_EE_vect _VECTOR(32) /* EE Interrupt */ -#define NVM_SPM_vect_num 33 -#define NVM_SPM_vect _VECTOR(33) /* SPM Interrupt */ - -/* PORTB interrupt vectors */ -#define PORTB_INT0_vect_num 34 -#define PORTB_INT0_vect _VECTOR(34) /* External Interrupt 0 */ -#define PORTB_INT1_vect_num 35 -#define PORTB_INT1_vect _VECTOR(35) /* External Interrupt 1 */ - -/* ACB interrupt vectors */ -#define ACB_AC0_vect_num 36 -#define ACB_AC0_vect _VECTOR(36) /* AC0 Interrupt */ -#define ACB_AC1_vect_num 37 -#define ACB_AC1_vect _VECTOR(37) /* AC1 Interrupt */ -#define ACB_ACW_vect_num 38 -#define ACB_ACW_vect _VECTOR(38) /* ACW Window Mode Interrupt */ - -/* ADCB interrupt vectors */ -#define ADCB_CH0_vect_num 39 -#define ADCB_CH0_vect _VECTOR(39) /* Interrupt 0 */ -#define ADCB_CH1_vect_num 40 -#define ADCB_CH1_vect _VECTOR(40) /* Interrupt 1 */ -#define ADCB_CH2_vect_num 41 -#define ADCB_CH2_vect _VECTOR(41) /* Interrupt 2 */ -#define ADCB_CH3_vect_num 42 -#define ADCB_CH3_vect _VECTOR(42) /* Interrupt 3 */ - -/* PORTE interrupt vectors */ -#define PORTE_INT0_vect_num 43 -#define PORTE_INT0_vect _VECTOR(43) /* External Interrupt 0 */ -#define PORTE_INT1_vect_num 44 -#define PORTE_INT1_vect _VECTOR(44) /* External Interrupt 1 */ - -/* TWIE interrupt vectors */ -#define TWIE_TWIS_vect_num 45 -#define TWIE_TWIS_vect _VECTOR(45) /* TWI Slave Interrupt */ -#define TWIE_TWIM_vect_num 46 -#define TWIE_TWIM_vect _VECTOR(46) /* TWI Master Interrupt */ - -/* TCE0 interrupt vectors */ -#define TCE0_OVF_vect_num 47 -#define TCE0_OVF_vect _VECTOR(47) /* Overflow Interrupt */ -#define TCE0_ERR_vect_num 48 -#define TCE0_ERR_vect _VECTOR(48) /* Error Interrupt */ -#define TCE0_CCA_vect_num 49 -#define TCE0_CCA_vect _VECTOR(49) /* Compare or Capture A Interrupt */ -#define TCE0_CCB_vect_num 50 -#define TCE0_CCB_vect _VECTOR(50) /* Compare or Capture B Interrupt */ -#define TCE0_CCC_vect_num 51 -#define TCE0_CCC_vect _VECTOR(51) /* Compare or Capture C Interrupt */ -#define TCE0_CCD_vect_num 52 -#define TCE0_CCD_vect _VECTOR(52) /* Compare or Capture D Interrupt */ - -/* TCE1 interrupt vectors */ -#define TCE1_OVF_vect_num 53 -#define TCE1_OVF_vect _VECTOR(53) /* Overflow Interrupt */ -#define TCE1_ERR_vect_num 54 -#define TCE1_ERR_vect _VECTOR(54) /* Error Interrupt */ -#define TCE1_CCA_vect_num 55 -#define TCE1_CCA_vect _VECTOR(55) /* Compare or Capture A Interrupt */ -#define TCE1_CCB_vect_num 56 -#define TCE1_CCB_vect _VECTOR(56) /* Compare or Capture B Interrupt */ - -/* SPIE interrupt vectors */ -#define SPIE_INT_vect_num 57 -#define SPIE_INT_vect _VECTOR(57) /* SPI Interrupt */ - -/* USARTE0 interrupt vectors */ -#define USARTE0_RXC_vect_num 58 -#define USARTE0_RXC_vect _VECTOR(58) /* Reception Complete Interrupt */ -#define USARTE0_DRE_vect_num 59 -#define USARTE0_DRE_vect _VECTOR(59) /* Data Register Empty Interrupt */ -#define USARTE0_TXC_vect_num 60 -#define USARTE0_TXC_vect _VECTOR(60) /* Transmission Complete Interrupt */ - -/* USARTE1 interrupt vectors */ -#define USARTE1_RXC_vect_num 61 -#define USARTE1_RXC_vect _VECTOR(61) /* Reception Complete Interrupt */ -#define USARTE1_DRE_vect_num 62 -#define USARTE1_DRE_vect _VECTOR(62) /* Data Register Empty Interrupt */ -#define USARTE1_TXC_vect_num 63 -#define USARTE1_TXC_vect _VECTOR(63) /* Transmission Complete Interrupt */ - -/* PORTD interrupt vectors */ -#define PORTD_INT0_vect_num 64 -#define PORTD_INT0_vect _VECTOR(64) /* External Interrupt 0 */ -#define PORTD_INT1_vect_num 65 -#define PORTD_INT1_vect _VECTOR(65) /* External Interrupt 1 */ - -/* PORTA interrupt vectors */ -#define PORTA_INT0_vect_num 66 -#define PORTA_INT0_vect _VECTOR(66) /* External Interrupt 0 */ -#define PORTA_INT1_vect_num 67 -#define PORTA_INT1_vect _VECTOR(67) /* External Interrupt 1 */ - -/* ACA interrupt vectors */ -#define ACA_AC0_vect_num 68 -#define ACA_AC0_vect _VECTOR(68) /* AC0 Interrupt */ -#define ACA_AC1_vect_num 69 -#define ACA_AC1_vect _VECTOR(69) /* AC1 Interrupt */ -#define ACA_ACW_vect_num 70 -#define ACA_ACW_vect _VECTOR(70) /* ACW Window Mode Interrupt */ - -/* ADCA interrupt vectors */ -#define ADCA_CH0_vect_num 71 -#define ADCA_CH0_vect _VECTOR(71) /* Interrupt 0 */ -#define ADCA_CH1_vect_num 72 -#define ADCA_CH1_vect _VECTOR(72) /* Interrupt 1 */ -#define ADCA_CH2_vect_num 73 -#define ADCA_CH2_vect _VECTOR(73) /* Interrupt 2 */ -#define ADCA_CH3_vect_num 74 -#define ADCA_CH3_vect _VECTOR(74) /* Interrupt 3 */ - -/* TCD0 interrupt vectors */ -#define TCD0_OVF_vect_num 77 -#define TCD0_OVF_vect _VECTOR(77) /* Overflow Interrupt */ -#define TCD0_ERR_vect_num 78 -#define TCD0_ERR_vect _VECTOR(78) /* Error Interrupt */ -#define TCD0_CCA_vect_num 79 -#define TCD0_CCA_vect _VECTOR(79) /* Compare or Capture A Interrupt */ -#define TCD0_CCB_vect_num 80 -#define TCD0_CCB_vect _VECTOR(80) /* Compare or Capture B Interrupt */ -#define TCD0_CCC_vect_num 81 -#define TCD0_CCC_vect _VECTOR(81) /* Compare or Capture C Interrupt */ -#define TCD0_CCD_vect_num 82 -#define TCD0_CCD_vect _VECTOR(82) /* Compare or Capture D Interrupt */ - -/* TCD1 interrupt vectors */ -#define TCD1_OVF_vect_num 83 -#define TCD1_OVF_vect _VECTOR(83) /* Overflow Interrupt */ -#define TCD1_ERR_vect_num 84 -#define TCD1_ERR_vect _VECTOR(84) /* Error Interrupt */ -#define TCD1_CCA_vect_num 85 -#define TCD1_CCA_vect _VECTOR(85) /* Compare or Capture A Interrupt */ -#define TCD1_CCB_vect_num 86 -#define TCD1_CCB_vect _VECTOR(86) /* Compare or Capture B Interrupt */ - -/* SPID interrupt vectors */ -#define SPID_INT_vect_num 87 -#define SPID_INT_vect _VECTOR(87) /* SPI Interrupt */ - -/* USARTD0 interrupt vectors */ -#define USARTD0_RXC_vect_num 88 -#define USARTD0_RXC_vect _VECTOR(88) /* Reception Complete Interrupt */ -#define USARTD0_DRE_vect_num 89 -#define USARTD0_DRE_vect _VECTOR(89) /* Data Register Empty Interrupt */ -#define USARTD0_TXC_vect_num 90 -#define USARTD0_TXC_vect _VECTOR(90) /* Transmission Complete Interrupt */ - -/* USARTD1 interrupt vectors */ -#define USARTD1_RXC_vect_num 91 -#define USARTD1_RXC_vect _VECTOR(91) /* Reception Complete Interrupt */ -#define USARTD1_DRE_vect_num 92 -#define USARTD1_DRE_vect _VECTOR(92) /* Data Register Empty Interrupt */ -#define USARTD1_TXC_vect_num 93 -#define USARTD1_TXC_vect _VECTOR(93) /* Transmission Complete Interrupt */ - -/* PORTF interrupt vectors */ -#define PORTF_INT0_vect_num 104 -#define PORTF_INT0_vect _VECTOR(104) /* External Interrupt 0 */ -#define PORTF_INT1_vect_num 105 -#define PORTF_INT1_vect _VECTOR(105) /* External Interrupt 1 */ - -/* TCF0 interrupt vectors */ -#define TCF0_OVF_vect_num 108 -#define TCF0_OVF_vect _VECTOR(108) /* Overflow Interrupt */ -#define TCF0_ERR_vect_num 109 -#define TCF0_ERR_vect _VECTOR(109) /* Error Interrupt */ -#define TCF0_CCA_vect_num 110 -#define TCF0_CCA_vect _VECTOR(110) /* Compare or Capture A Interrupt */ -#define TCF0_CCB_vect_num 111 -#define TCF0_CCB_vect _VECTOR(111) /* Compare or Capture B Interrupt */ -#define TCF0_CCC_vect_num 112 -#define TCF0_CCC_vect _VECTOR(112) /* Compare or Capture C Interrupt */ -#define TCF0_CCD_vect_num 113 -#define TCF0_CCD_vect _VECTOR(113) /* Compare or Capture D Interrupt */ - -/* USARTF0 interrupt vectors */ -#define USARTF0_RXC_vect_num 119 -#define USARTF0_RXC_vect _VECTOR(119) /* Reception Complete Interrupt */ -#define USARTF0_DRE_vect_num 120 -#define USARTF0_DRE_vect _VECTOR(120) /* Data Register Empty Interrupt */ -#define USARTF0_TXC_vect_num 121 -#define USARTF0_TXC_vect _VECTOR(121) /* Transmission Complete Interrupt */ - - -#define _VECTOR_SIZE 4 /* Size of individual vector. */ -#define _VECTORS_SIZE (122 * _VECTOR_SIZE) - - -/* ========== Constants ========== */ - -#define PROGMEM_START (0x0000) -#define PROGMEM_SIZE (69632) -#define PROGMEM_PAGE_SIZE (256) -#define PROGMEM_END (PROGMEM_START + PROGMEM_SIZE - 1) - -#define APP_SECTION_START (0x0000) -#define APP_SECTION_SIZE (65536) -#define APP_SECTION_PAGE_SIZE (256) -#define APP_SECTION_END (APP_SECTION_START + APP_SECTION_SIZE - 1) - -#define APPTABLE_SECTION_START (0x0F000) -#define APPTABLE_SECTION_SIZE (4096) -#define APPTABLE_SECTION_PAGE_SIZE (256) -#define APPTABLE_SECTION_END (APPTABLE_SECTION_START + APPTABLE_SECTION_SIZE - 1) - -#define BOOT_SECTION_START (0x10000) -#define BOOT_SECTION_SIZE (4096) -#define BOOT_SECTION_PAGE_SIZE (256) -#define BOOT_SECTION_END (BOOT_SECTION_START + BOOT_SECTION_SIZE - 1) - -#define DATAMEM_START (0x0000) -#define DATAMEM_SIZE (12288) -#define DATAMEM_PAGE_SIZE (0) -#define DATAMEM_END (DATAMEM_START + DATAMEM_SIZE - 1) - -#define IO_START (0x0000) -#define IO_SIZE (4096) -#define IO_PAGE_SIZE (0) -#define IO_END (IO_START + IO_SIZE - 1) - -#define MAPPED_EEPROM_START (0x1000) -#define MAPPED_EEPROM_SIZE (2048) -#define MAPPED_EEPROM_PAGE_SIZE (0) -#define MAPPED_EEPROM_END (MAPPED_EEPROM_START + MAPPED_EEPROM_SIZE - 1) - -#define INTERNAL_SRAM_START (0x2000) -#define INTERNAL_SRAM_SIZE (4096) -#define INTERNAL_SRAM_PAGE_SIZE (0) -#define INTERNAL_SRAM_END (INTERNAL_SRAM_START + INTERNAL_SRAM_SIZE - 1) - -#define EEPROM_START (0x0000) -#define EEPROM_SIZE (2048) -#define EEPROM_PAGE_SIZE (32) -#define EEPROM_END (EEPROM_START + EEPROM_SIZE - 1) - -#define FUSE_START (0x0000) -#define FUSE_SIZE (6) -#define FUSE_PAGE_SIZE (0) -#define FUSE_END (FUSE_START + FUSE_SIZE - 1) - -#define LOCKBIT_START (0x0000) -#define LOCKBIT_SIZE (1) -#define LOCKBIT_PAGE_SIZE (0) -#define LOCKBIT_END (LOCKBIT_START + LOCKBIT_SIZE - 1) - -#define SIGNATURES_START (0x0000) -#define SIGNATURES_SIZE (3) -#define SIGNATURES_PAGE_SIZE (0) -#define SIGNATURES_END (SIGNATURES_START + SIGNATURES_SIZE - 1) - -#define USER_SIGNATURES_START (0x0000) -#define USER_SIGNATURES_SIZE (256) -#define USER_SIGNATURES_PAGE_SIZE (0) -#define USER_SIGNATURES_END (USER_SIGNATURES_START + USER_SIGNATURES_SIZE - 1) - -#define PROD_SIGNATURES_START (0x0000) -#define PROD_SIGNATURES_SIZE (52) -#define PROD_SIGNATURES_PAGE_SIZE (0) -#define PROD_SIGNATURES_END (PROD_SIGNATURES_START + PROD_SIGNATURES_SIZE - 1) - -#define FLASHEND PROGMEM_END -#define SPM_PAGESIZE PROGMEM_PAGE_SIZE -#define RAMSTART INTERNAL_SRAM_START -#define RAMSIZE INTERNAL_SRAM_SIZE -#define RAMEND INTERNAL_SRAM_END -#define XRAMSTART EXTERNAL_SRAM_START -#define XRAMSIZE EXTERNAL_SRAM_SIZE -#define XRAMEND INTERNAL_SRAM_END -#define E2END EEPROM_END -#define E2PAGESIZE EEPROM_PAGE_SIZE - - -/* ========== Fuses ========== */ -#define FUSE_MEMORY_SIZE 6 - -/* Fuse Byte 0 */ -#define FUSE_JTAGUSERID0 (unsigned char)~_BV(0) /* JTAG User ID Bit 0 */ -#define FUSE_JTAGUSERID1 (unsigned char)~_BV(1) /* JTAG User ID Bit 1 */ -#define FUSE_JTAGUSERID2 (unsigned char)~_BV(2) /* JTAG User ID Bit 2 */ -#define FUSE_JTAGUSERID3 (unsigned char)~_BV(3) /* JTAG User ID Bit 3 */ -#define FUSE_JTAGUSERID4 (unsigned char)~_BV(4) /* JTAG User ID Bit 4 */ -#define FUSE_JTAGUSERID5 (unsigned char)~_BV(5) /* JTAG User ID Bit 5 */ -#define FUSE_JTAGUSERID6 (unsigned char)~_BV(6) /* JTAG User ID Bit 6 */ -#define FUSE_JTAGUSERID7 (unsigned char)~_BV(7) /* JTAG User ID Bit 7 */ -#define FUSE0_DEFAULT (0xFF) - -/* Fuse Byte 1 */ -#define FUSE_WDP0 (unsigned char)~_BV(0) /* Watchdog Timeout Period Bit 0 */ -#define FUSE_WDP1 (unsigned char)~_BV(1) /* Watchdog Timeout Period Bit 1 */ -#define FUSE_WDP2 (unsigned char)~_BV(2) /* Watchdog Timeout Period Bit 2 */ -#define FUSE_WDP3 (unsigned char)~_BV(3) /* Watchdog Timeout Period Bit 3 */ -#define FUSE_WDWP0 (unsigned char)~_BV(4) /* Watchdog Window Timeout Period Bit 0 */ -#define FUSE_WDWP1 (unsigned char)~_BV(5) /* Watchdog Window Timeout Period Bit 1 */ -#define FUSE_WDWP2 (unsigned char)~_BV(6) /* Watchdog Window Timeout Period Bit 2 */ -#define FUSE_WDWP3 (unsigned char)~_BV(7) /* Watchdog Window Timeout Period Bit 3 */ -#define FUSE1_DEFAULT (0xFF) - -/* Fuse Byte 2 */ -#define FUSE_BODPD0 (unsigned char)~_BV(0) /* BOD Operation in Power-Down Mode Bit 0 */ -#define FUSE_BODPD1 (unsigned char)~_BV(1) /* BOD Operation in Power-Down Mode Bit 1 */ -#define FUSE_BOOTRST (unsigned char)~_BV(6) /* Boot Loader Section Reset Vector */ -#define FUSE_DVSDON (unsigned char)~_BV(7) /* Spike Detector Enable */ -#define FUSE2_DEFAULT (0xFF) - -/* Fuse Byte 3 Reserved */ - -/* Fuse Byte 4 */ -#define FUSE_JTAGEN (unsigned char)~_BV(0) /* JTAG Interface Enable */ -#define FUSE_WDLOCK (unsigned char)~_BV(1) /* Watchdog Timer Lock */ -#define FUSE_SUT0 (unsigned char)~_BV(2) /* Start-up Time Bit 0 */ -#define FUSE_SUT1 (unsigned char)~_BV(3) /* Start-up Time Bit 1 */ -#define FUSE4_DEFAULT (0xFF) - -/* Fuse Byte 5 */ -#define FUSE_BODLVL0 (unsigned char)~_BV(0) /* Brown Out Detection Voltage Level Bit 0 */ -#define FUSE_BODLVL1 (unsigned char)~_BV(1) /* Brown Out Detection Voltage Level Bit 1 */ -#define FUSE_BODLVL2 (unsigned char)~_BV(2) /* Brown Out Detection Voltage Level Bit 2 */ -#define FUSE_EESAVE (unsigned char)~_BV(3) /* Preserve EEPROM Through Chip Erase */ -#define FUSE_BODACT0 (unsigned char)~_BV(4) /* BOD Operation in Active Mode Bit 0 */ -#define FUSE_BODACT1 (unsigned char)~_BV(5) /* BOD Operation in Active Mode Bit 1 */ -#define FUSE5_DEFAULT (0xFF) - - -/* ========== Lock Bits ========== */ -#define __LOCK_BITS_EXIST -#define __BOOT_LOCK_APPLICATION_TABLE_BITS_EXIST -#define __BOOT_LOCK_APPLICATION_BITS_EXIST -#define __BOOT_LOCK_BOOT_BITS_EXIST - - -/* ========== Signature ========== */ -#define SIGNATURE_0 0x1E -#define SIGNATURE_1 0x96 -#define SIGNATURE_2 0x42 - -/* ========== Power Reduction Condition Definitions ========== */ - -/* PR.PRGEN */ -#define __AVR_HAVE_PRGEN (PR_AES_bm|PR_EBI_bm|PR_RTC_bm|PR_EVSYS_bm|PR_DMA_bm) -#define __AVR_HAVE_PRGEN_AES -#define __AVR_HAVE_PRGEN_EBI -#define __AVR_HAVE_PRGEN_RTC -#define __AVR_HAVE_PRGEN_EVSYS -#define __AVR_HAVE_PRGEN_DMA - -/* PR.PRPA */ -#define __AVR_HAVE_PRPA (PR_DAC_bm|PR_ADC_bm|PR_AC_bm) -#define __AVR_HAVE_PRPA_DAC -#define __AVR_HAVE_PRPA_ADC -#define __AVR_HAVE_PRPA_AC - -/* PR.PRPB */ -#define __AVR_HAVE_PRPB (PR_DAC_bm|PR_ADC_bm|PR_AC_bm) -#define __AVR_HAVE_PRPB_DAC -#define __AVR_HAVE_PRPB_ADC -#define __AVR_HAVE_PRPB_AC - -/* PR.PRPC */ -#define __AVR_HAVE_PRPC (PR_TWI_bm|PR_USART1_bm|PR_USART0_bm|PR_SPI_bm|PR_HIRES_bm|PR_TC1_bm|PR_TC0_bm) -#define __AVR_HAVE_PRPC_TWI -#define __AVR_HAVE_PRPC_USART1 -#define __AVR_HAVE_PRPC_USART0 -#define __AVR_HAVE_PRPC_SPI -#define __AVR_HAVE_PRPC_HIRES -#define __AVR_HAVE_PRPC_TC1 -#define __AVR_HAVE_PRPC_TC0 - -/* PR.PRPD */ -#define __AVR_HAVE_PRPD (PR_TWI_bm|PR_USART1_bm|PR_USART0_bm|PR_SPI_bm|PR_HIRES_bm|PR_TC1_bm|PR_TC0_bm) -#define __AVR_HAVE_PRPD_TWI -#define __AVR_HAVE_PRPD_USART1 -#define __AVR_HAVE_PRPD_USART0 -#define __AVR_HAVE_PRPD_SPI -#define __AVR_HAVE_PRPD_HIRES -#define __AVR_HAVE_PRPD_TC1 -#define __AVR_HAVE_PRPD_TC0 - -/* PR.PRPE */ -#define __AVR_HAVE_PRPE (PR_TWI_bm|PR_USART1_bm|PR_USART0_bm|PR_SPI_bm|PR_HIRES_bm|PR_TC1_bm|PR_TC0_bm) -#define __AVR_HAVE_PRPE_TWI -#define __AVR_HAVE_PRPE_USART1 -#define __AVR_HAVE_PRPE_USART0 -#define __AVR_HAVE_PRPE_SPI -#define __AVR_HAVE_PRPE_HIRES -#define __AVR_HAVE_PRPE_TC1 -#define __AVR_HAVE_PRPE_TC0 - -/* PR.PRPF */ -#define __AVR_HAVE_PRPF (PR_TWI_bm|PR_USART1_bm|PR_USART0_bm|PR_SPI_bm|PR_HIRES_bm|PR_TC1_bm|PR_TC0_bm) -#define __AVR_HAVE_PRPF_TWI -#define __AVR_HAVE_PRPF_USART1 -#define __AVR_HAVE_PRPF_USART0 -#define __AVR_HAVE_PRPF_SPI -#define __AVR_HAVE_PRPF_HIRES -#define __AVR_HAVE_PRPF_TC1 -#define __AVR_HAVE_PRPF_TC0 - - -#endif /* _AVR_ATxmega64A3_H_ */ - diff --git a/arduino/hardware/tools/avr/avr/include/avr/iox64a3u.h b/arduino/hardware/tools/avr/avr/include/avr/iox64a3u.h deleted file mode 100644 index 0d230d8..0000000 --- a/arduino/hardware/tools/avr/avr/include/avr/iox64a3u.h +++ /dev/null @@ -1,7697 +0,0 @@ -/***************************************************************************** - * - * Copyright (C) 2015 Atmel Corporation - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * - * * Neither the name of the copyright holders nor the names of - * contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - ****************************************************************************/ - - -#ifndef _AVR_IO_H_ -# error "Include instead of this file." -#endif - -#ifndef _AVR_IOXXX_H_ -# define _AVR_IOXXX_H_ "iox64a3u.h" -#else -# error "Attempt to include more than one file." -#endif - -#ifndef _AVR_ATXMEGA64A3U_H_INCLUDED -#define _AVR_ATXMEGA64A3U_H_INCLUDED - -/* Ungrouped common registers */ -#define GPIOR0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ -#define GPIOR1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ -#define GPIOR2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ -#define GPIOR3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ -#define GPIOR4 _SFR_MEM8(0x0004) /* General Purpose IO Register 4 */ -#define GPIOR5 _SFR_MEM8(0x0005) /* General Purpose IO Register 5 */ -#define GPIOR6 _SFR_MEM8(0x0006) /* General Purpose IO Register 6 */ -#define GPIOR7 _SFR_MEM8(0x0007) /* General Purpose IO Register 7 */ -#define GPIOR8 _SFR_MEM8(0x0008) /* General Purpose IO Register 8 */ -#define GPIOR9 _SFR_MEM8(0x0009) /* General Purpose IO Register 9 */ -#define GPIORA _SFR_MEM8(0x000A) /* General Purpose IO Register 10 */ -#define GPIORB _SFR_MEM8(0x000B) /* General Purpose IO Register 11 */ -#define GPIORC _SFR_MEM8(0x000C) /* General Purpose IO Register 12 */ -#define GPIORD _SFR_MEM8(0x000D) /* General Purpose IO Register 13 */ -#define GPIORE _SFR_MEM8(0x000E) /* General Purpose IO Register 14 */ -#define GPIORF _SFR_MEM8(0x000F) /* General Purpose IO Register 15 */ - -/* Deprecated */ -#define GPIO0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ -#define GPIO1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ -#define GPIO2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ -#define GPIO3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ -#define GPIO4 _SFR_MEM8(0x0004) /* General Purpose IO Register 4 */ -#define GPIO5 _SFR_MEM8(0x0005) /* General Purpose IO Register 5 */ -#define GPIO6 _SFR_MEM8(0x0006) /* General Purpose IO Register 6 */ -#define GPIO7 _SFR_MEM8(0x0007) /* General Purpose IO Register 7 */ -#define GPIO8 _SFR_MEM8(0x0008) /* General Purpose IO Register 8 */ -#define GPIO9 _SFR_MEM8(0x0009) /* General Purpose IO Register 9 */ -#define GPIOA _SFR_MEM8(0x000A) /* General Purpose IO Register 10 */ -#define GPIOB _SFR_MEM8(0x000B) /* General Purpose IO Register 11 */ -#define GPIOC _SFR_MEM8(0x000C) /* General Purpose IO Register 12 */ -#define GPIOD _SFR_MEM8(0x000D) /* General Purpose IO Register 13 */ -#define GPIOE _SFR_MEM8(0x000E) /* General Purpose IO Register 14 */ -#define GPIOF _SFR_MEM8(0x000F) /* General Purpose IO Register 15 */ - -#define CCP _SFR_MEM8(0x0034) /* Configuration Change Protection */ -#define RAMPD _SFR_MEM8(0x0038) /* Ramp D */ -#define RAMPX _SFR_MEM8(0x0039) /* Ramp X */ -#define RAMPY _SFR_MEM8(0x003A) /* Ramp Y */ -#define RAMPZ _SFR_MEM8(0x003B) /* Ramp Z */ -#define EIND _SFR_MEM8(0x003C) /* Extended Indirect Jump */ -#define SPL _SFR_MEM8(0x003D) /* Stack Pointer Low */ -#define SPH _SFR_MEM8(0x003E) /* Stack Pointer High */ -#define SREG _SFR_MEM8(0x003F) /* Status Register */ - -/* C Language Only */ -#if !defined (__ASSEMBLER__) - -#include - -typedef volatile uint8_t register8_t; -typedef volatile uint16_t register16_t; -typedef volatile uint32_t register32_t; - - -#ifdef _WORDREGISTER -#undef _WORDREGISTER -#endif -#define _WORDREGISTER(regname) \ - __extension__ union \ - { \ - register16_t regname; \ - struct \ - { \ - register8_t regname ## L; \ - register8_t regname ## H; \ - }; \ - } - -#ifdef _DWORDREGISTER -#undef _DWORDREGISTER -#endif -#define _DWORDREGISTER(regname) \ - __extension__ union \ - { \ - register32_t regname; \ - struct \ - { \ - register8_t regname ## 0; \ - register8_t regname ## 1; \ - register8_t regname ## 2; \ - register8_t regname ## 3; \ - }; \ - } - - -/* -========================================================================== -IO Module Structures -========================================================================== -*/ - - -/* --------------------------------------------------------------------------- -VPORT - Virtual Ports --------------------------------------------------------------------------- -*/ - -/* Virtual Port */ -typedef struct VPORT_struct -{ - register8_t DIR; /* I/O Port Data Direction */ - register8_t OUT; /* I/O Port Output */ - register8_t IN; /* I/O Port Input */ - register8_t INTFLAGS; /* Interrupt Flag Register */ -} VPORT_t; - - -/* --------------------------------------------------------------------------- -XOCD - On-Chip Debug System --------------------------------------------------------------------------- -*/ - -/* On-Chip Debug System */ -typedef struct OCD_struct -{ - register8_t OCDR0; /* OCD Register 0 */ - register8_t OCDR1; /* OCD Register 1 */ -} OCD_t; - - -/* --------------------------------------------------------------------------- -CPU - CPU --------------------------------------------------------------------------- -*/ - -/* CCP signatures */ -typedef enum CCP_enum -{ - CCP_SPM_gc = (0x9D<<0), /* SPM Instruction Protection */ - CCP_IOREG_gc = (0xD8<<0), /* IO Register Protection */ -} CCP_t; - - -/* --------------------------------------------------------------------------- -CLK - Clock System --------------------------------------------------------------------------- -*/ - -/* Clock System */ -typedef struct CLK_struct -{ - register8_t CTRL; /* Control Register */ - register8_t PSCTRL; /* Prescaler Control Register */ - register8_t LOCK; /* Lock register */ - register8_t RTCCTRL; /* RTC Control Register */ - register8_t USBCTRL; /* USB Control Register */ -} CLK_t; - - -/* Power Reduction */ -typedef struct PR_struct -{ - register8_t PRGEN; /* General Power Reduction */ - register8_t PRPA; /* Power Reduction Port A */ - register8_t PRPB; /* Power Reduction Port B */ - register8_t PRPC; /* Power Reduction Port C */ - register8_t PRPD; /* Power Reduction Port D */ - register8_t PRPE; /* Power Reduction Port E */ - register8_t PRPF; /* Power Reduction Port F */ -} PR_t; - -/* System Clock Selection */ -typedef enum CLK_SCLKSEL_enum -{ - CLK_SCLKSEL_RC2M_gc = (0x00<<0), /* Internal 2 MHz RC Oscillator */ - CLK_SCLKSEL_RC32M_gc = (0x01<<0), /* Internal 32 MHz RC Oscillator */ - CLK_SCLKSEL_RC32K_gc = (0x02<<0), /* Internal 32.768 kHz RC Oscillator */ - CLK_SCLKSEL_XOSC_gc = (0x03<<0), /* External Crystal Oscillator or Clock */ - CLK_SCLKSEL_PLL_gc = (0x04<<0), /* Phase Locked Loop */ -} CLK_SCLKSEL_t; - -/* Prescaler A Division Factor */ -typedef enum CLK_PSADIV_enum -{ - CLK_PSADIV_1_gc = (0x00<<2), /* Divide by 1 */ - CLK_PSADIV_2_gc = (0x01<<2), /* Divide by 2 */ - CLK_PSADIV_4_gc = (0x03<<2), /* Divide by 4 */ - CLK_PSADIV_8_gc = (0x05<<2), /* Divide by 8 */ - CLK_PSADIV_16_gc = (0x07<<2), /* Divide by 16 */ - CLK_PSADIV_32_gc = (0x09<<2), /* Divide by 32 */ - CLK_PSADIV_64_gc = (0x0B<<2), /* Divide by 64 */ - CLK_PSADIV_128_gc = (0x0D<<2), /* Divide by 128 */ - CLK_PSADIV_256_gc = (0x0F<<2), /* Divide by 256 */ - CLK_PSADIV_512_gc = (0x11<<2), /* Divide by 512 */ -} CLK_PSADIV_t; - -/* Prescaler B and C Division Factor */ -typedef enum CLK_PSBCDIV_enum -{ - CLK_PSBCDIV_1_1_gc = (0x00<<0), /* Divide B by 1 and C by 1 */ - CLK_PSBCDIV_1_2_gc = (0x01<<0), /* Divide B by 1 and C by 2 */ - CLK_PSBCDIV_4_1_gc = (0x02<<0), /* Divide B by 4 and C by 1 */ - CLK_PSBCDIV_2_2_gc = (0x03<<0), /* Divide B by 2 and C by 2 */ -} CLK_PSBCDIV_t; - -/* RTC Clock Source */ -typedef enum CLK_RTCSRC_enum -{ - CLK_RTCSRC_ULP_gc = (0x00<<1), /* 1.024 kHz from internal 32kHz ULP */ - CLK_RTCSRC_TOSC_gc = (0x01<<1), /* 1.024 kHz from 32.768 kHz crystal oscillator on TOSC */ - CLK_RTCSRC_RCOSC_gc = (0x02<<1), /* 1.024 kHz from internal 32.768 kHz RC oscillator */ - CLK_RTCSRC_TOSC32_gc = (0x05<<1), /* 32.768 kHz from 32.768 kHz crystal oscillator on TOSC */ - CLK_RTCSRC_RCOSC32_gc = (0x06<<1), /* 32.768 kHz from internal 32.768 kHz RC oscillator */ - CLK_RTCSRC_EXTCLK_gc = (0x07<<1), /* External Clock from TOSC1 */ -} CLK_RTCSRC_t; - -/* USB Prescaler Division Factor */ -typedef enum CLK_USBPSDIV_enum -{ - CLK_USBPSDIV_1_gc = (0x00<<3), /* Divide by 1 */ - CLK_USBPSDIV_2_gc = (0x01<<3), /* Divide by 2 */ - CLK_USBPSDIV_4_gc = (0x02<<3), /* Divide by 4 */ - CLK_USBPSDIV_8_gc = (0x03<<3), /* Divide by 8 */ - CLK_USBPSDIV_16_gc = (0x04<<3), /* Divide by 16 */ - CLK_USBPSDIV_32_gc = (0x05<<3), /* Divide by 32 */ -} CLK_USBPSDIV_t; - -/* USB Clock Source */ -typedef enum CLK_USBSRC_enum -{ - CLK_USBSRC_PLL_gc = (0x00<<1), /* PLL */ - CLK_USBSRC_RC32M_gc = (0x01<<1), /* Internal 32 MHz RC Oscillator */ -} CLK_USBSRC_t; - - -/* --------------------------------------------------------------------------- -SLEEP - Sleep Controller --------------------------------------------------------------------------- -*/ - -/* Sleep Controller */ -typedef struct SLEEP_struct -{ - register8_t CTRL; /* Control Register */ -} SLEEP_t; - -/* Sleep Mode */ -typedef enum SLEEP_SMODE_enum -{ - SLEEP_SMODE_IDLE_gc = (0x00<<1), /* Idle mode */ - SLEEP_SMODE_PDOWN_gc = (0x02<<1), /* Power-down Mode */ - SLEEP_SMODE_PSAVE_gc = (0x03<<1), /* Power-save Mode */ - SLEEP_SMODE_STDBY_gc = (0x06<<1), /* Standby Mode */ - SLEEP_SMODE_ESTDBY_gc = (0x07<<1), /* Extended Standby Mode */ -} SLEEP_SMODE_t; - - - -#define SLEEP_MODE_IDLE (0x00<<1) -#define SLEEP_MODE_PWR_DOWN (0x02<<1) -#define SLEEP_MODE_PWR_SAVE (0x03<<1) -#define SLEEP_MODE_STANDBY (0x06<<1) -#define SLEEP_MODE_EXT_STANDBY (0x07<<1) -/* --------------------------------------------------------------------------- -OSC - Oscillator --------------------------------------------------------------------------- -*/ - -/* Oscillator */ -typedef struct OSC_struct -{ - register8_t CTRL; /* Control Register */ - register8_t STATUS; /* Status Register */ - register8_t XOSCCTRL; /* External Oscillator Control Register */ - register8_t XOSCFAIL; /* Oscillator Failure Detection Register */ - register8_t RC32KCAL; /* 32.768 kHz Internal Oscillator Calibration Register */ - register8_t PLLCTRL; /* PLL Control Register */ - register8_t DFLLCTRL; /* DFLL Control Register */ -} OSC_t; - -/* Oscillator Frequency Range */ -typedef enum OSC_FRQRANGE_enum -{ - OSC_FRQRANGE_04TO2_gc = (0x00<<6), /* 0.4 - 2 MHz */ - OSC_FRQRANGE_2TO9_gc = (0x01<<6), /* 2 - 9 MHz */ - OSC_FRQRANGE_9TO12_gc = (0x02<<6), /* 9 - 12 MHz */ - OSC_FRQRANGE_12TO16_gc = (0x03<<6), /* 12 - 16 MHz */ -} OSC_FRQRANGE_t; - -/* External Oscillator Selection and Startup Time */ -typedef enum OSC_XOSCSEL_enum -{ - OSC_XOSCSEL_EXTCLK_gc = (0x00<<0), /* External Clock - 6 CLK */ - OSC_XOSCSEL_32KHz_gc = (0x02<<0), /* 32.768 kHz TOSC - 32K CLK */ - OSC_XOSCSEL_XTAL_256CLK_gc = (0x03<<0), /* 0.4-16 MHz XTAL - 256 CLK */ - OSC_XOSCSEL_XTAL_1KCLK_gc = (0x07<<0), /* 0.4-16 MHz XTAL - 1K CLK */ - OSC_XOSCSEL_XTAL_16KCLK_gc = (0x0B<<0), /* 0.4-16 MHz XTAL - 16K CLK */ -} OSC_XOSCSEL_t; - -/* PLL Clock Source */ -typedef enum OSC_PLLSRC_enum -{ - OSC_PLLSRC_RC2M_gc = (0x00<<6), /* Internal 2 MHz RC Oscillator */ - OSC_PLLSRC_RC32M_gc = (0x02<<6), /* Internal 32 MHz RC Oscillator */ - OSC_PLLSRC_XOSC_gc = (0x03<<6), /* External Oscillator */ -} OSC_PLLSRC_t; - -/* 2 MHz DFLL Calibration Reference */ -typedef enum OSC_RC2MCREF_enum -{ - OSC_RC2MCREF_RC32K_gc = (0x00<<0), /* Internal 32.768 kHz RC Oscillator */ - OSC_RC2MCREF_XOSC32K_gc = (0x01<<0), /* External 32.768 kHz Crystal Oscillator */ -} OSC_RC2MCREF_t; - -/* 32 MHz DFLL Calibration Reference */ -typedef enum OSC_RC32MCREF_enum -{ - OSC_RC32MCREF_RC32K_gc = (0x00<<1), /* Internal 32.768 kHz RC Oscillator */ - OSC_RC32MCREF_XOSC32K_gc = (0x01<<1), /* External 32.768 kHz Crystal Oscillator */ - OSC_RC32MCREF_USBSOF_gc = (0x02<<1), /* USB Start of Frame */ -} OSC_RC32MCREF_t; - - -/* --------------------------------------------------------------------------- -DFLL - DFLL --------------------------------------------------------------------------- -*/ - -/* DFLL */ -typedef struct DFLL_struct -{ - register8_t CTRL; /* Control Register */ - register8_t reserved_0x01; - register8_t CALA; /* Calibration Register A */ - register8_t CALB; /* Calibration Register B */ - register8_t COMP0; /* Oscillator Compare Register 0 */ - register8_t COMP1; /* Oscillator Compare Register 1 */ - register8_t COMP2; /* Oscillator Compare Register 2 */ - register8_t reserved_0x07; -} DFLL_t; - - -/* --------------------------------------------------------------------------- -RST - Reset --------------------------------------------------------------------------- -*/ - -/* Reset */ -typedef struct RST_struct -{ - register8_t STATUS; /* Status Register */ - register8_t CTRL; /* Control Register */ -} RST_t; - - -/* --------------------------------------------------------------------------- -WDT - Watch-Dog Timer --------------------------------------------------------------------------- -*/ - -/* Watch-Dog Timer */ -typedef struct WDT_struct -{ - register8_t CTRL; /* Control */ - register8_t WINCTRL; /* Windowed Mode Control */ - register8_t STATUS; /* Status */ -} WDT_t; - -/* Period setting */ -typedef enum WDT_PER_enum -{ - WDT_PER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ - WDT_PER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ - WDT_PER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ - WDT_PER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ - WDT_PER_128CLK_gc = (0x04<<2), /* 128 cycles (0.128s @ 3.3V) */ - WDT_PER_256CLK_gc = (0x05<<2), /* 256 cycles (0.256s @ 3.3V) */ - WDT_PER_512CLK_gc = (0x06<<2), /* 512 cycles (0.512s @ 3.3V) */ - WDT_PER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ - WDT_PER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ - WDT_PER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ - WDT_PER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ -} WDT_PER_t; - -/* Closed window period */ -typedef enum WDT_WPER_enum -{ - WDT_WPER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ - WDT_WPER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ - WDT_WPER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ - WDT_WPER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ - WDT_WPER_128CLK_gc = (0x04<<2), /* 128 cycles (0.128s @ 3.3V) */ - WDT_WPER_256CLK_gc = (0x05<<2), /* 256 cycles (0.256s @ 3.3V) */ - WDT_WPER_512CLK_gc = (0x06<<2), /* 512 cycles (0.512s @ 3.3V) */ - WDT_WPER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ - WDT_WPER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ - WDT_WPER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ - WDT_WPER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ -} WDT_WPER_t; - - -/* --------------------------------------------------------------------------- -MCU - MCU Control --------------------------------------------------------------------------- -*/ - -/* MCU Control */ -typedef struct MCU_struct -{ - register8_t DEVID0; /* Device ID byte 0 */ - register8_t DEVID1; /* Device ID byte 1 */ - register8_t DEVID2; /* Device ID byte 2 */ - register8_t REVID; /* Revision ID */ - register8_t JTAGUID; /* JTAG User ID */ - register8_t reserved_0x05; - register8_t MCUCR; /* MCU Control */ - register8_t ANAINIT; /* Analog Startup Delay */ - register8_t EVSYSLOCK; /* Event System Lock */ - register8_t AWEXLOCK; /* AWEX Lock */ - register8_t reserved_0x0A; - register8_t reserved_0x0B; -} MCU_t; - - -/* --------------------------------------------------------------------------- -PMIC - Programmable Multi-level Interrupt Controller --------------------------------------------------------------------------- -*/ - -/* Programmable Multi-level Interrupt Controller */ -typedef struct PMIC_struct -{ - register8_t STATUS; /* Status Register */ - register8_t INTPRI; /* Interrupt Priority */ - register8_t CTRL; /* Control Register */ - register8_t reserved_0x03; - register8_t reserved_0x04; - register8_t reserved_0x05; - register8_t reserved_0x06; - register8_t reserved_0x07; - register8_t reserved_0x08; - register8_t reserved_0x09; - register8_t reserved_0x0A; - register8_t reserved_0x0B; - register8_t reserved_0x0C; - register8_t reserved_0x0D; - register8_t reserved_0x0E; - register8_t reserved_0x0F; -} PMIC_t; - - -/* --------------------------------------------------------------------------- -PORTCFG - Port Configuration --------------------------------------------------------------------------- -*/ - -/* I/O port Configuration */ -typedef struct PORTCFG_struct -{ - register8_t MPCMASK; /* Multi-pin Configuration Mask */ - register8_t reserved_0x01; - register8_t VPCTRLA; /* Virtual Port Control Register A */ - register8_t VPCTRLB; /* Virtual Port Control Register B */ - register8_t CLKEVOUT; /* Clock and Event Out Register */ - register8_t EBIOUT; /* EBI Output register */ - register8_t EVOUTSEL; /* Event Output Select */ -} PORTCFG_t; - -/* Virtual Port Mapping */ -typedef enum PORTCFG_VP02MAP_enum -{ - PORTCFG_VP02MAP_PORTA_gc = (0x00<<0), /* Mapped To PORTA */ - PORTCFG_VP02MAP_PORTB_gc = (0x01<<0), /* Mapped To PORTB */ - PORTCFG_VP02MAP_PORTC_gc = (0x02<<0), /* Mapped To PORTC */ - PORTCFG_VP02MAP_PORTD_gc = (0x03<<0), /* Mapped To PORTD */ - PORTCFG_VP02MAP_PORTE_gc = (0x04<<0), /* Mapped To PORTE */ - PORTCFG_VP02MAP_PORTF_gc = (0x05<<0), /* Mapped To PORTF */ - PORTCFG_VP02MAP_PORTG_gc = (0x06<<0), /* Mapped To PORTG */ - PORTCFG_VP02MAP_PORTH_gc = (0x07<<0), /* Mapped To PORTH */ - PORTCFG_VP02MAP_PORTJ_gc = (0x08<<0), /* Mapped To PORTJ */ - PORTCFG_VP02MAP_PORTK_gc = (0x09<<0), /* Mapped To PORTK */ - PORTCFG_VP02MAP_PORTL_gc = (0x0A<<0), /* Mapped To PORTL */ - PORTCFG_VP02MAP_PORTM_gc = (0x0B<<0), /* Mapped To PORTM */ - PORTCFG_VP02MAP_PORTN_gc = (0x0C<<0), /* Mapped To PORTN */ - PORTCFG_VP02MAP_PORTP_gc = (0x0D<<0), /* Mapped To PORTP */ - PORTCFG_VP02MAP_PORTQ_gc = (0x0E<<0), /* Mapped To PORTQ */ - PORTCFG_VP02MAP_PORTR_gc = (0x0F<<0), /* Mapped To PORTR */ -} PORTCFG_VP02MAP_t; - -/* Virtual Port Mapping */ -typedef enum PORTCFG_VP13MAP_enum -{ - PORTCFG_VP13MAP_PORTA_gc = (0x00<<4), /* Mapped To PORTA */ - PORTCFG_VP13MAP_PORTB_gc = (0x01<<4), /* Mapped To PORTB */ - PORTCFG_VP13MAP_PORTC_gc = (0x02<<4), /* Mapped To PORTC */ - PORTCFG_VP13MAP_PORTD_gc = (0x03<<4), /* Mapped To PORTD */ - PORTCFG_VP13MAP_PORTE_gc = (0x04<<4), /* Mapped To PORTE */ - PORTCFG_VP13MAP_PORTF_gc = (0x05<<4), /* Mapped To PORTF */ - PORTCFG_VP13MAP_PORTG_gc = (0x06<<4), /* Mapped To PORTG */ - PORTCFG_VP13MAP_PORTH_gc = (0x07<<4), /* Mapped To PORTH */ - PORTCFG_VP13MAP_PORTJ_gc = (0x08<<4), /* Mapped To PORTJ */ - PORTCFG_VP13MAP_PORTK_gc = (0x09<<4), /* Mapped To PORTK */ - PORTCFG_VP13MAP_PORTL_gc = (0x0A<<4), /* Mapped To PORTL */ - PORTCFG_VP13MAP_PORTM_gc = (0x0B<<4), /* Mapped To PORTM */ - PORTCFG_VP13MAP_PORTN_gc = (0x0C<<4), /* Mapped To PORTN */ - PORTCFG_VP13MAP_PORTP_gc = (0x0D<<4), /* Mapped To PORTP */ - PORTCFG_VP13MAP_PORTQ_gc = (0x0E<<4), /* Mapped To PORTQ */ - PORTCFG_VP13MAP_PORTR_gc = (0x0F<<4), /* Mapped To PORTR */ -} PORTCFG_VP13MAP_t; - -/* System Clock Output Port */ -typedef enum PORTCFG_CLKOUT_enum -{ - PORTCFG_CLKOUT_OFF_gc = (0x00<<0), /* System Clock Output Disabled */ - PORTCFG_CLKOUT_PC7_gc = (0x01<<0), /* System Clock Output on Port C pin 7 */ - PORTCFG_CLKOUT_PD7_gc = (0x02<<0), /* System Clock Output on Port D pin 7 */ - PORTCFG_CLKOUT_PE7_gc = (0x03<<0), /* System Clock Output on Port E pin 7 */ -} PORTCFG_CLKOUT_t; - -/* Peripheral Clock Output Select */ -typedef enum PORTCFG_CLKOUTSEL_enum -{ - PORTCFG_CLKOUTSEL_CLK1X_gc = (0x00<<2), /* 1x Peripheral Clock Output to pin */ - PORTCFG_CLKOUTSEL_CLK2X_gc = (0x01<<2), /* 2x Peripheral Clock Output to pin */ - PORTCFG_CLKOUTSEL_CLK4X_gc = (0x02<<2), /* 4x Peripheral Clock Output to pin */ -} PORTCFG_CLKOUTSEL_t; - -/* Event Output Port */ -typedef enum PORTCFG_EVOUT_enum -{ - PORTCFG_EVOUT_OFF_gc = (0x00<<4), /* Event Output Disabled */ - PORTCFG_EVOUT_PC7_gc = (0x01<<4), /* Event Channel 7 Output on Port C pin 7 */ - PORTCFG_EVOUT_PD7_gc = (0x02<<4), /* Event Channel 7 Output on Port D pin 7 */ - PORTCFG_EVOUT_PE7_gc = (0x03<<4), /* Event Channel 7 Output on Port E pin 7 */ -} PORTCFG_EVOUT_t; - -/* Clock and Event Output Port */ -typedef enum PORTCFG_CLKEVPIN_enum -{ - PORTCFG_CLKEVPIN_PIN7_gc = (0x00<<7), /* Clock and Event Ouput on PIN 7 */ - PORTCFG_CLKEVPIN_PIN4_gc = (0x01<<7), /* Clock and Event Ouput on PIN 4 */ -} PORTCFG_CLKEVPIN_t; - -/* EBI Address Output Port */ -typedef enum PORTCFG_EBIADROUT_enum -{ - PORTCFG_EBIADROUT_PF_gc = (0x00<<2), /* EBI port 3 address output on PORTF pins 0 to 7 */ - PORTCFG_EBIADROUT_PE_gc = (0x01<<2), /* EBI port 3 address output on PORTE pins 0 to 7 */ - PORTCFG_EBIADROUT_PFH_gc = (0x02<<2), /* EBI port 3 address output on PORTF pins 4 to 7 */ - PORTCFG_EBIADROUT_PEH_gc = (0x03<<2), /* EBI port 3 address output on PORTE pins 4 to 7 */ -} PORTCFG_EBIADROUT_t; - -/* EBI Chip Select Output Port */ -typedef enum PORTCFG_EBICSOUT_enum -{ - PORTCFG_EBICSOUT_PH_gc = (0x00<<0), /* EBI chip select output to PORTH pin 4 to 7 */ - PORTCFG_EBICSOUT_PL_gc = (0x01<<0), /* EBI chip select output to PORTL pin 4 to 7 */ - PORTCFG_EBICSOUT_PF_gc = (0x02<<0), /* EBI chip select output to PORTF pin 4 to 7 */ - PORTCFG_EBICSOUT_PE_gc = (0x03<<0), /* EBI chip select output to PORTE pin 4 to 7 */ -} PORTCFG_EBICSOUT_t; - -/* Event Output Select */ -typedef enum PORTCFG_EVOUTSEL_enum -{ - PORTCFG_EVOUTSEL_0_gc = (0x00<<0), /* Event Channel 0 output to pin */ - PORTCFG_EVOUTSEL_1_gc = (0x01<<0), /* Event Channel 1 output to pin */ - PORTCFG_EVOUTSEL_2_gc = (0x02<<0), /* Event Channel 2 output to pin */ - PORTCFG_EVOUTSEL_3_gc = (0x03<<0), /* Event Channel 3 output to pin */ - PORTCFG_EVOUTSEL_4_gc = (0x04<<0), /* Event Channel 4 output to pin */ - PORTCFG_EVOUTSEL_5_gc = (0x05<<0), /* Event Channel 5 output to pin */ - PORTCFG_EVOUTSEL_6_gc = (0x06<<0), /* Event Channel 6 output to pin */ - PORTCFG_EVOUTSEL_7_gc = (0x07<<0), /* Event Channel 7 output to pin */ -} PORTCFG_EVOUTSEL_t; - - -/* --------------------------------------------------------------------------- -AES - AES Module --------------------------------------------------------------------------- -*/ - -/* AES Module */ -typedef struct AES_struct -{ - register8_t CTRL; /* AES Control Register */ - register8_t STATUS; /* AES Status Register */ - register8_t STATE; /* AES State Register */ - register8_t KEY; /* AES Key Register */ - register8_t INTCTRL; /* AES Interrupt Control Register */ -} AES_t; - -/* Interrupt level */ -typedef enum AES_INTLVL_enum -{ - AES_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - AES_INTLVL_LO_gc = (0x01<<0), /* Low Level */ - AES_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ - AES_INTLVL_HI_gc = (0x03<<0), /* High Level */ -} AES_INTLVL_t; - - -/* --------------------------------------------------------------------------- -CRC - Cyclic Redundancy Checker --------------------------------------------------------------------------- -*/ - -/* Cyclic Redundancy Checker */ -typedef struct CRC_struct -{ - register8_t CTRL; /* Control Register */ - register8_t STATUS; /* Status Register */ - register8_t reserved_0x02; - register8_t DATAIN; /* Data Input */ - register8_t CHECKSUM0; /* Checksum byte 0 */ - register8_t CHECKSUM1; /* Checksum byte 1 */ - register8_t CHECKSUM2; /* Checksum byte 2 */ - register8_t CHECKSUM3; /* Checksum byte 3 */ -} CRC_t; - -/* Reset */ -typedef enum CRC_RESET_enum -{ - CRC_RESET_NO_gc = (0x00<<6), /* No Reset */ - CRC_RESET_RESET0_gc = (0x02<<6), /* Reset CRC with CHECKSUM to all zeros */ - CRC_RESET_RESET1_gc = (0x03<<6), /* Reset CRC with CHECKSUM to all ones */ -} CRC_RESET_t; - -/* Input Source */ -typedef enum CRC_SOURCE_enum -{ - CRC_SOURCE_DISABLE_gc = (0x00<<0), /* Disabled */ - CRC_SOURCE_IO_gc = (0x01<<0), /* I/O Interface */ - CRC_SOURCE_FLASH_gc = (0x02<<0), /* Flash */ - CRC_SOURCE_DMAC0_gc = (0x04<<0), /* DMAC Channel 0 */ - CRC_SOURCE_DMAC1_gc = (0x05<<0), /* DMAC Channel 1 */ - CRC_SOURCE_DMAC2_gc = (0x06<<0), /* DMAC Channel 2 */ - CRC_SOURCE_DMAC3_gc = (0x07<<0), /* DMAC Channel 3 */ -} CRC_SOURCE_t; - - -/* --------------------------------------------------------------------------- -DMA - DMA Controller --------------------------------------------------------------------------- -*/ - -/* DMA Channel */ -typedef struct DMA_CH_struct -{ - register8_t CTRLA; /* Channel Control */ - register8_t CTRLB; /* Channel Control */ - register8_t ADDRCTRL; /* Address Control */ - register8_t TRIGSRC; /* Channel Trigger Source */ - _WORDREGISTER(TRFCNT); /* Channel Block Transfer Count */ - register8_t REPCNT; /* Channel Repeat Count */ - register8_t reserved_0x07; - register8_t SRCADDR0; /* Channel Source Address 0 */ - register8_t SRCADDR1; /* Channel Source Address 1 */ - register8_t SRCADDR2; /* Channel Source Address 2 */ - register8_t reserved_0x0B; - register8_t DESTADDR0; /* Channel Destination Address 0 */ - register8_t DESTADDR1; /* Channel Destination Address 1 */ - register8_t DESTADDR2; /* Channel Destination Address 2 */ - register8_t reserved_0x0F; -} DMA_CH_t; - - -/* DMA Controller */ -typedef struct DMA_struct -{ - register8_t CTRL; /* Control */ - register8_t reserved_0x01; - register8_t reserved_0x02; - register8_t INTFLAGS; /* Transfer Interrupt Status */ - register8_t STATUS; /* Status */ - register8_t reserved_0x05; - _WORDREGISTER(TEMP); /* Temporary Register For 16/24-bit Access */ - register8_t reserved_0x08; - register8_t reserved_0x09; - register8_t reserved_0x0A; - register8_t reserved_0x0B; - register8_t reserved_0x0C; - register8_t reserved_0x0D; - register8_t reserved_0x0E; - register8_t reserved_0x0F; - DMA_CH_t CH0; /* DMA Channel 0 */ - DMA_CH_t CH1; /* DMA Channel 1 */ - DMA_CH_t CH2; /* DMA Channel 2 */ - DMA_CH_t CH3; /* DMA Channel 3 */ -} DMA_t; - -/* Burst mode */ -typedef enum DMA_CH_BURSTLEN_enum -{ - DMA_CH_BURSTLEN_1BYTE_gc = (0x00<<0), /* 1-byte burst mode */ - DMA_CH_BURSTLEN_2BYTE_gc = (0x01<<0), /* 2-byte burst mode */ - DMA_CH_BURSTLEN_4BYTE_gc = (0x02<<0), /* 4-byte burst mode */ - DMA_CH_BURSTLEN_8BYTE_gc = (0x03<<0), /* 8-byte burst mode */ -} DMA_CH_BURSTLEN_t; - -/* Source address reload mode */ -typedef enum DMA_CH_SRCRELOAD_enum -{ - DMA_CH_SRCRELOAD_NONE_gc = (0x00<<6), /* No reload */ - DMA_CH_SRCRELOAD_BLOCK_gc = (0x01<<6), /* Reload at end of block */ - DMA_CH_SRCRELOAD_BURST_gc = (0x02<<6), /* Reload at end of burst */ - DMA_CH_SRCRELOAD_TRANSACTION_gc = (0x03<<6), /* Reload at end of transaction */ -} DMA_CH_SRCRELOAD_t; - -/* Source addressing mode */ -typedef enum DMA_CH_SRCDIR_enum -{ - DMA_CH_SRCDIR_FIXED_gc = (0x00<<4), /* Fixed */ - DMA_CH_SRCDIR_INC_gc = (0x01<<4), /* Increment */ - DMA_CH_SRCDIR_DEC_gc = (0x02<<4), /* Decrement */ -} DMA_CH_SRCDIR_t; - -/* Destination adress reload mode */ -typedef enum DMA_CH_DESTRELOAD_enum -{ - DMA_CH_DESTRELOAD_NONE_gc = (0x00<<2), /* No reload */ - DMA_CH_DESTRELOAD_BLOCK_gc = (0x01<<2), /* Reload at end of block */ - DMA_CH_DESTRELOAD_BURST_gc = (0x02<<2), /* Reload at end of burst */ - DMA_CH_DESTRELOAD_TRANSACTION_gc = (0x03<<2), /* Reload at end of transaction */ -} DMA_CH_DESTRELOAD_t; - -/* Destination adressing mode */ -typedef enum DMA_CH_DESTDIR_enum -{ - DMA_CH_DESTDIR_FIXED_gc = (0x00<<0), /* Fixed */ - DMA_CH_DESTDIR_INC_gc = (0x01<<0), /* Increment */ - DMA_CH_DESTDIR_DEC_gc = (0x02<<0), /* Decrement */ -} DMA_CH_DESTDIR_t; - -/* Transfer trigger source */ -typedef enum DMA_CH_TRIGSRC_enum -{ - DMA_CH_TRIGSRC_OFF_gc = (0x00<<0), /* Off software triggers only */ - DMA_CH_TRIGSRC_EVSYS_CH0_gc = (0x01<<0), /* Event System Channel 0 */ - DMA_CH_TRIGSRC_EVSYS_CH1_gc = (0x02<<0), /* Event System Channel 1 */ - DMA_CH_TRIGSRC_EVSYS_CH2_gc = (0x03<<0), /* Event System Channel 2 */ - DMA_CH_TRIGSRC_ADCA_CH0_gc = (0x10<<0), /* ADCA Channel 0 */ - DMA_CH_TRIGSRC_ADCA_CH1_gc = (0x11<<0), /* ADCA Channel 1 */ - DMA_CH_TRIGSRC_ADCA_CH2_gc = (0x12<<0), /* ADCA Channel 2 */ - DMA_CH_TRIGSRC_ADCA_CH3_gc = (0x13<<0), /* ADCA Channel 3 */ - DMA_CH_TRIGSRC_ADCA_CH4_gc = (0x14<<0), /* ADCA Channel 0,1,2,3 combined */ - DMA_CH_TRIGSRC_DACA_CH0_gc = (0x15<<0), /* DACA Channel 0 */ - DMA_CH_TRIGSRC_DACA_CH1_gc = (0x16<<0), /* DACA Channel 1 */ - DMA_CH_TRIGSRC_ADCB_CH0_gc = (0x20<<0), /* ADCB Channel 0 */ - DMA_CH_TRIGSRC_ADCB_CH1_gc = (0x21<<0), /* ADCB Channel 1 */ - DMA_CH_TRIGSRC_ADCB_CH2_gc = (0x22<<0), /* ADCB Channel 2 */ - DMA_CH_TRIGSRC_ADCB_CH3_gc = (0x23<<0), /* ADCB Channel 3 */ - DMA_CH_TRIGSRC_ADCB_CH4_gc = (0x24<<0), /* ADCB Channel 0,1,2,3 combined */ - DMA_CH_TRIGSRC_DACB_CH0_gc = (0x25<<0), /* DACB Channel 0 */ - DMA_CH_TRIGSRC_DACB_CH1_gc = (0x26<<0), /* DACB Channel 1 */ - DMA_CH_TRIGSRC_TCC0_OVF_gc = (0x40<<0), /* Timer/Counter C0 Overflow */ - DMA_CH_TRIGSRC_TCC0_ERR_gc = (0x41<<0), /* Timer/Counter C0 Error */ - DMA_CH_TRIGSRC_TCC0_CCA_gc = (0x42<<0), /* Timer/Counter C0 Compare or Capture A */ - DMA_CH_TRIGSRC_TCC0_CCB_gc = (0x43<<0), /* Timer/Counter C0 Compare or Capture B */ - DMA_CH_TRIGSRC_TCC0_CCC_gc = (0x44<<0), /* Timer/Counter C0 Compare or Capture C */ - DMA_CH_TRIGSRC_TCC0_CCD_gc = (0x45<<0), /* Timer/Counter C0 Compare or Capture D */ - DMA_CH_TRIGSRC_TCC1_OVF_gc = (0x46<<0), /* Timer/Counter C1 Overflow */ - DMA_CH_TRIGSRC_TCC1_ERR_gc = (0x47<<0), /* Timer/Counter C1 Error */ - DMA_CH_TRIGSRC_TCC1_CCA_gc = (0x48<<0), /* Timer/Counter C1 Compare or Capture A */ - DMA_CH_TRIGSRC_TCC1_CCB_gc = (0x49<<0), /* Timer/Counter C1 Compare or Capture B */ - DMA_CH_TRIGSRC_SPIC_gc = (0x4A<<0), /* SPI C Transfer Complete */ - DMA_CH_TRIGSRC_USARTC0_RXC_gc = (0x4B<<0), /* USART C0 Receive Complete */ - DMA_CH_TRIGSRC_USARTC0_DRE_gc = (0x4C<<0), /* USART C0 Data Register Empty */ - DMA_CH_TRIGSRC_USARTC1_RXC_gc = (0x4E<<0), /* USART C1 Receive Complete */ - DMA_CH_TRIGSRC_USARTC1_DRE_gc = (0x4F<<0), /* USART C1 Data Register Empty */ - DMA_CH_TRIGSRC_TCD0_OVF_gc = (0x60<<0), /* Timer/Counter D0 Overflow */ - DMA_CH_TRIGSRC_TCD0_ERR_gc = (0x61<<0), /* Timer/Counter D0 Error */ - DMA_CH_TRIGSRC_TCD0_CCA_gc = (0x62<<0), /* Timer/Counter D0 Compare or Capture A */ - DMA_CH_TRIGSRC_TCD0_CCB_gc = (0x63<<0), /* Timer/Counter D0 Compare or Capture B */ - DMA_CH_TRIGSRC_TCD0_CCC_gc = (0x64<<0), /* Timer/Counter D0 Compare or Capture C */ - DMA_CH_TRIGSRC_TCD0_CCD_gc = (0x65<<0), /* Timer/Counter D0 Compare or Capture D */ - DMA_CH_TRIGSRC_TCD1_OVF_gc = (0x66<<0), /* Timer/Counter D1 Overflow */ - DMA_CH_TRIGSRC_TCD1_ERR_gc = (0x67<<0), /* Timer/Counter D1 Error */ - DMA_CH_TRIGSRC_TCD1_CCA_gc = (0x68<<0), /* Timer/Counter D1 Compare or Capture A */ - DMA_CH_TRIGSRC_TCD1_CCB_gc = (0x69<<0), /* Timer/Counter D1 Compare or Capture B */ - DMA_CH_TRIGSRC_SPID_gc = (0x6A<<0), /* SPI D Transfer Complete */ - DMA_CH_TRIGSRC_USARTD0_RXC_gc = (0x6B<<0), /* USART D0 Receive Complete */ - DMA_CH_TRIGSRC_USARTD0_DRE_gc = (0x6C<<0), /* USART D0 Data Register Empty */ - DMA_CH_TRIGSRC_USARTD1_RXC_gc = (0x6E<<0), /* USART D1 Receive Complete */ - DMA_CH_TRIGSRC_USARTD1_DRE_gc = (0x6F<<0), /* USART D1 Data Register Empty */ - DMA_CH_TRIGSRC_TCE0_OVF_gc = (0x80<<0), /* Timer/Counter E0 Overflow */ - DMA_CH_TRIGSRC_TCE0_ERR_gc = (0x81<<0), /* Timer/Counter E0 Error */ - DMA_CH_TRIGSRC_TCE0_CCA_gc = (0x82<<0), /* Timer/Counter E0 Compare or Capture A */ - DMA_CH_TRIGSRC_TCE0_CCB_gc = (0x83<<0), /* Timer/Counter E0 Compare or Capture B */ - DMA_CH_TRIGSRC_TCE0_CCC_gc = (0x84<<0), /* Timer/Counter E0 Compare or Capture C */ - DMA_CH_TRIGSRC_TCE0_CCD_gc = (0x85<<0), /* Timer/Counter E0 Compare or Capture D */ - DMA_CH_TRIGSRC_TCE1_OVF_gc = (0x86<<0), /* Timer/Counter E1 Overflow */ - DMA_CH_TRIGSRC_TCE1_ERR_gc = (0x87<<0), /* Timer/Counter E1 Error */ - DMA_CH_TRIGSRC_TCE1_CCA_gc = (0x88<<0), /* Timer/Counter E1 Compare or Capture A */ - DMA_CH_TRIGSRC_TCE1_CCB_gc = (0x89<<0), /* Timer/Counter E1 Compare or Capture B */ - DMA_CH_TRIGSRC_SPIE_gc = (0x8A<<0), /* SPI E Transfer Complete */ - DMA_CH_TRIGSRC_USARTE0_RXC_gc = (0x8B<<0), /* USART E0 Receive Complete */ - DMA_CH_TRIGSRC_USARTE0_DRE_gc = (0x8C<<0), /* USART E0 Data Register Empty */ - DMA_CH_TRIGSRC_USARTE1_RXC_gc = (0x8E<<0), /* USART E1 Receive Complete */ - DMA_CH_TRIGSRC_USARTE1_DRE_gc = (0x8F<<0), /* USART E1 Data Register Empty */ - DMA_CH_TRIGSRC_TCF0_OVF_gc = (0xA0<<0), /* Timer/Counter F0 Overflow */ - DMA_CH_TRIGSRC_TCF0_ERR_gc = (0xA1<<0), /* Timer/Counter F0 Error */ - DMA_CH_TRIGSRC_TCF0_CCA_gc = (0xA2<<0), /* Timer/Counter F0 Compare or Capture A */ - DMA_CH_TRIGSRC_TCF0_CCB_gc = (0xA3<<0), /* Timer/Counter F0 Compare or Capture B */ - DMA_CH_TRIGSRC_TCF0_CCC_gc = (0xA4<<0), /* Timer/Counter F0 Compare or Capture C */ - DMA_CH_TRIGSRC_TCF0_CCD_gc = (0xA5<<0), /* Timer/Counter F0 Compare or Capture D */ - DMA_CH_TRIGSRC_TCF1_OVF_gc = (0xA6<<0), /* Timer/Counter F1 Overflow */ - DMA_CH_TRIGSRC_TCF1_ERR_gc = (0xA7<<0), /* Timer/Counter F1 Error */ - DMA_CH_TRIGSRC_TCF1_CCA_gc = (0xA8<<0), /* Timer/Counter F1 Compare or Capture A */ - DMA_CH_TRIGSRC_TCF1_CCB_gc = (0xA9<<0), /* Timer/Counter F1 Compare or Capture B */ - DMA_CH_TRIGSRC_SPIF_gc = (0xAA<<0), /* SPI F Transfer Complete */ - DMA_CH_TRIGSRC_USARTF0_RXC_gc = (0xAB<<0), /* USART F0 Receive Complete */ - DMA_CH_TRIGSRC_USARTF0_DRE_gc = (0xAC<<0), /* USART F0 Data Register Empty */ - DMA_CH_TRIGSRC_USARTF1_RXC_gc = (0xAE<<0), /* USART F1 Receive Complete */ - DMA_CH_TRIGSRC_USARTF1_DRE_gc = (0xAF<<0), /* USART F1 Data Register Empty */ -} DMA_CH_TRIGSRC_t; - -/* Double buffering mode */ -typedef enum DMA_DBUFMODE_enum -{ - DMA_DBUFMODE_DISABLED_gc = (0x00<<2), /* Double buffering disabled */ - DMA_DBUFMODE_CH01_gc = (0x01<<2), /* Double buffering enabled on channel 0/1 */ - DMA_DBUFMODE_CH23_gc = (0x02<<2), /* Double buffering enabled on channel 2/3 */ - DMA_DBUFMODE_CH01CH23_gc = (0x03<<2), /* Double buffering enabled on ch. 0/1 and ch. 2/3 */ -} DMA_DBUFMODE_t; - -/* Priority mode */ -typedef enum DMA_PRIMODE_enum -{ - DMA_PRIMODE_RR0123_gc = (0x00<<0), /* Round Robin */ - DMA_PRIMODE_CH0RR123_gc = (0x01<<0), /* Channel 0 > Round Robin on channel 1/2/3 */ - DMA_PRIMODE_CH01RR23_gc = (0x02<<0), /* Channel 0 > channel 1 > Round Robin on channel 2/3 */ - DMA_PRIMODE_CH0123_gc = (0x03<<0), /* Channel 0 > channel 1 > channel 2 > channel 3 */ -} DMA_PRIMODE_t; - -/* Interrupt level */ -typedef enum DMA_CH_ERRINTLVL_enum -{ - DMA_CH_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ - DMA_CH_ERRINTLVL_LO_gc = (0x01<<2), /* Low level */ - DMA_CH_ERRINTLVL_MED_gc = (0x02<<2), /* Medium level */ - DMA_CH_ERRINTLVL_HI_gc = (0x03<<2), /* High level */ -} DMA_CH_ERRINTLVL_t; - -/* Interrupt level */ -typedef enum DMA_CH_TRNINTLVL_enum -{ - DMA_CH_TRNINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ - DMA_CH_TRNINTLVL_LO_gc = (0x01<<0), /* Low level */ - DMA_CH_TRNINTLVL_MED_gc = (0x02<<0), /* Medium level */ - DMA_CH_TRNINTLVL_HI_gc = (0x03<<0), /* High level */ -} DMA_CH_TRNINTLVL_t; - - -/* --------------------------------------------------------------------------- -EVSYS - Event System --------------------------------------------------------------------------- -*/ - -/* Event System */ -typedef struct EVSYS_struct -{ - register8_t CH0MUX; /* Event Channel 0 Multiplexer */ - register8_t CH1MUX; /* Event Channel 1 Multiplexer */ - register8_t CH2MUX; /* Event Channel 2 Multiplexer */ - register8_t CH3MUX; /* Event Channel 3 Multiplexer */ - register8_t CH4MUX; /* Event Channel 4 Multiplexer */ - register8_t CH5MUX; /* Event Channel 5 Multiplexer */ - register8_t CH6MUX; /* Event Channel 6 Multiplexer */ - register8_t CH7MUX; /* Event Channel 7 Multiplexer */ - register8_t CH0CTRL; /* Channel 0 Control Register */ - register8_t CH1CTRL; /* Channel 1 Control Register */ - register8_t CH2CTRL; /* Channel 2 Control Register */ - register8_t CH3CTRL; /* Channel 3 Control Register */ - register8_t CH4CTRL; /* Channel 4 Control Register */ - register8_t CH5CTRL; /* Channel 5 Control Register */ - register8_t CH6CTRL; /* Channel 6 Control Register */ - register8_t CH7CTRL; /* Channel 7 Control Register */ - register8_t STROBE; /* Event Strobe */ - register8_t DATA; /* Event Data */ -} EVSYS_t; - -/* Quadrature Decoder Index Recognition Mode */ -typedef enum EVSYS_QDIRM_enum -{ - EVSYS_QDIRM_00_gc = (0x00<<5), /* QDPH0 = 0, QDPH90 = 0 */ - EVSYS_QDIRM_01_gc = (0x01<<5), /* QDPH0 = 0, QDPH90 = 1 */ - EVSYS_QDIRM_10_gc = (0x02<<5), /* QDPH0 = 1, QDPH90 = 0 */ - EVSYS_QDIRM_11_gc = (0x03<<5), /* QDPH0 = 1, QDPH90 = 1 */ -} EVSYS_QDIRM_t; - -/* Digital filter coefficient */ -typedef enum EVSYS_DIGFILT_enum -{ - EVSYS_DIGFILT_1SAMPLE_gc = (0x00<<0), /* 1 SAMPLE */ - EVSYS_DIGFILT_2SAMPLES_gc = (0x01<<0), /* 2 SAMPLES */ - EVSYS_DIGFILT_3SAMPLES_gc = (0x02<<0), /* 3 SAMPLES */ - EVSYS_DIGFILT_4SAMPLES_gc = (0x03<<0), /* 4 SAMPLES */ - EVSYS_DIGFILT_5SAMPLES_gc = (0x04<<0), /* 5 SAMPLES */ - EVSYS_DIGFILT_6SAMPLES_gc = (0x05<<0), /* 6 SAMPLES */ - EVSYS_DIGFILT_7SAMPLES_gc = (0x06<<0), /* 7 SAMPLES */ - EVSYS_DIGFILT_8SAMPLES_gc = (0x07<<0), /* 8 SAMPLES */ -} EVSYS_DIGFILT_t; - -/* Event Channel multiplexer input selection */ -typedef enum EVSYS_CHMUX_enum -{ - EVSYS_CHMUX_OFF_gc = (0x00<<0), /* Off */ - EVSYS_CHMUX_RTC_OVF_gc = (0x08<<0), /* RTC Overflow */ - EVSYS_CHMUX_RTC_CMP_gc = (0x09<<0), /* RTC Compare Match */ - EVSYS_CHMUX_USB_gc = (0x0A<<0), /* USB Setup, SOF, CRC error and UNF/OVF */ - EVSYS_CHMUX_ACA_CH0_gc = (0x10<<0), /* Analog Comparator A Channel 0 */ - EVSYS_CHMUX_ACA_CH1_gc = (0x11<<0), /* Analog Comparator A Channel 1 */ - EVSYS_CHMUX_ACA_WIN_gc = (0x12<<0), /* Analog Comparator A Window */ - EVSYS_CHMUX_ACB_CH0_gc = (0x13<<0), /* Analog Comparator B Channel 0 */ - EVSYS_CHMUX_ACB_CH1_gc = (0x14<<0), /* Analog Comparator B Channel 1 */ - EVSYS_CHMUX_ACB_WIN_gc = (0x15<<0), /* Analog Comparator B Window */ - EVSYS_CHMUX_ADCA_CH0_gc = (0x20<<0), /* ADC A Channel 0 */ - EVSYS_CHMUX_ADCA_CH1_gc = (0x21<<0), /* ADC A Channel 1 */ - EVSYS_CHMUX_ADCA_CH2_gc = (0x22<<0), /* ADC A Channel 2 */ - EVSYS_CHMUX_ADCA_CH3_gc = (0x23<<0), /* ADC A Channel 3 */ - EVSYS_CHMUX_ADCB_CH0_gc = (0x24<<0), /* ADC B Channel 0 */ - EVSYS_CHMUX_ADCB_CH1_gc = (0x25<<0), /* ADC B Channel 1 */ - EVSYS_CHMUX_ADCB_CH2_gc = (0x26<<0), /* ADC B Channel 2 */ - EVSYS_CHMUX_ADCB_CH3_gc = (0x27<<0), /* ADC B Channel 3 */ - EVSYS_CHMUX_PORTA_PIN0_gc = (0x50<<0), /* Port A, Pin0 */ - EVSYS_CHMUX_PORTA_PIN1_gc = (0x51<<0), /* Port A, Pin1 */ - EVSYS_CHMUX_PORTA_PIN2_gc = (0x52<<0), /* Port A, Pin2 */ - EVSYS_CHMUX_PORTA_PIN3_gc = (0x53<<0), /* Port A, Pin3 */ - EVSYS_CHMUX_PORTA_PIN4_gc = (0x54<<0), /* Port A, Pin4 */ - EVSYS_CHMUX_PORTA_PIN5_gc = (0x55<<0), /* Port A, Pin5 */ - EVSYS_CHMUX_PORTA_PIN6_gc = (0x56<<0), /* Port A, Pin6 */ - EVSYS_CHMUX_PORTA_PIN7_gc = (0x57<<0), /* Port A, Pin7 */ - EVSYS_CHMUX_PORTB_PIN0_gc = (0x58<<0), /* Port B, Pin0 */ - EVSYS_CHMUX_PORTB_PIN1_gc = (0x59<<0), /* Port B, Pin1 */ - EVSYS_CHMUX_PORTB_PIN2_gc = (0x5A<<0), /* Port B, Pin2 */ - EVSYS_CHMUX_PORTB_PIN3_gc = (0x5B<<0), /* Port B, Pin3 */ - EVSYS_CHMUX_PORTB_PIN4_gc = (0x5C<<0), /* Port B, Pin4 */ - EVSYS_CHMUX_PORTB_PIN5_gc = (0x5D<<0), /* Port B, Pin5 */ - EVSYS_CHMUX_PORTB_PIN6_gc = (0x5E<<0), /* Port B, Pin6 */ - EVSYS_CHMUX_PORTB_PIN7_gc = (0x5F<<0), /* Port B, Pin7 */ - EVSYS_CHMUX_PORTC_PIN0_gc = (0x60<<0), /* Port C, Pin0 */ - EVSYS_CHMUX_PORTC_PIN1_gc = (0x61<<0), /* Port C, Pin1 */ - EVSYS_CHMUX_PORTC_PIN2_gc = (0x62<<0), /* Port C, Pin2 */ - EVSYS_CHMUX_PORTC_PIN3_gc = (0x63<<0), /* Port C, Pin3 */ - EVSYS_CHMUX_PORTC_PIN4_gc = (0x64<<0), /* Port C, Pin4 */ - EVSYS_CHMUX_PORTC_PIN5_gc = (0x65<<0), /* Port C, Pin5 */ - EVSYS_CHMUX_PORTC_PIN6_gc = (0x66<<0), /* Port C, Pin6 */ - EVSYS_CHMUX_PORTC_PIN7_gc = (0x67<<0), /* Port C, Pin7 */ - EVSYS_CHMUX_PORTD_PIN0_gc = (0x68<<0), /* Port D, Pin0 */ - EVSYS_CHMUX_PORTD_PIN1_gc = (0x69<<0), /* Port D, Pin1 */ - EVSYS_CHMUX_PORTD_PIN2_gc = (0x6A<<0), /* Port D, Pin2 */ - EVSYS_CHMUX_PORTD_PIN3_gc = (0x6B<<0), /* Port D, Pin3 */ - EVSYS_CHMUX_PORTD_PIN4_gc = (0x6C<<0), /* Port D, Pin4 */ - EVSYS_CHMUX_PORTD_PIN5_gc = (0x6D<<0), /* Port D, Pin5 */ - EVSYS_CHMUX_PORTD_PIN6_gc = (0x6E<<0), /* Port D, Pin6 */ - EVSYS_CHMUX_PORTD_PIN7_gc = (0x6F<<0), /* Port D, Pin7 */ - EVSYS_CHMUX_PORTE_PIN0_gc = (0x70<<0), /* Port E, Pin0 */ - EVSYS_CHMUX_PORTE_PIN1_gc = (0x71<<0), /* Port E, Pin1 */ - EVSYS_CHMUX_PORTE_PIN2_gc = (0x72<<0), /* Port E, Pin2 */ - EVSYS_CHMUX_PORTE_PIN3_gc = (0x73<<0), /* Port E, Pin3 */ - EVSYS_CHMUX_PORTE_PIN4_gc = (0x74<<0), /* Port E, Pin4 */ - EVSYS_CHMUX_PORTE_PIN5_gc = (0x75<<0), /* Port E, Pin5 */ - EVSYS_CHMUX_PORTE_PIN6_gc = (0x76<<0), /* Port E, Pin6 */ - EVSYS_CHMUX_PORTE_PIN7_gc = (0x77<<0), /* Port E, Pin7 */ - EVSYS_CHMUX_PORTF_PIN0_gc = (0x78<<0), /* Port F, Pin0 */ - EVSYS_CHMUX_PORTF_PIN1_gc = (0x79<<0), /* Port F, Pin1 */ - EVSYS_CHMUX_PORTF_PIN2_gc = (0x7A<<0), /* Port F, Pin2 */ - EVSYS_CHMUX_PORTF_PIN3_gc = (0x7B<<0), /* Port F, Pin3 */ - EVSYS_CHMUX_PORTF_PIN4_gc = (0x7C<<0), /* Port F, Pin4 */ - EVSYS_CHMUX_PORTF_PIN5_gc = (0x7D<<0), /* Port F, Pin5 */ - EVSYS_CHMUX_PORTF_PIN6_gc = (0x7E<<0), /* Port F, Pin6 */ - EVSYS_CHMUX_PORTF_PIN7_gc = (0x7F<<0), /* Port F, Pin7 */ - EVSYS_CHMUX_PRESCALER_1_gc = (0x80<<0), /* Prescaler, divide by 1 */ - EVSYS_CHMUX_PRESCALER_2_gc = (0x81<<0), /* Prescaler, divide by 2 */ - EVSYS_CHMUX_PRESCALER_4_gc = (0x82<<0), /* Prescaler, divide by 4 */ - EVSYS_CHMUX_PRESCALER_8_gc = (0x83<<0), /* Prescaler, divide by 8 */ - EVSYS_CHMUX_PRESCALER_16_gc = (0x84<<0), /* Prescaler, divide by 16 */ - EVSYS_CHMUX_PRESCALER_32_gc = (0x85<<0), /* Prescaler, divide by 32 */ - EVSYS_CHMUX_PRESCALER_64_gc = (0x86<<0), /* Prescaler, divide by 64 */ - EVSYS_CHMUX_PRESCALER_128_gc = (0x87<<0), /* Prescaler, divide by 128 */ - EVSYS_CHMUX_PRESCALER_256_gc = (0x88<<0), /* Prescaler, divide by 256 */ - EVSYS_CHMUX_PRESCALER_512_gc = (0x89<<0), /* Prescaler, divide by 512 */ - EVSYS_CHMUX_PRESCALER_1024_gc = (0x8A<<0), /* Prescaler, divide by 1024 */ - EVSYS_CHMUX_PRESCALER_2048_gc = (0x8B<<0), /* Prescaler, divide by 2048 */ - EVSYS_CHMUX_PRESCALER_4096_gc = (0x8C<<0), /* Prescaler, divide by 4096 */ - EVSYS_CHMUX_PRESCALER_8192_gc = (0x8D<<0), /* Prescaler, divide by 8192 */ - EVSYS_CHMUX_PRESCALER_16384_gc = (0x8E<<0), /* Prescaler, divide by 16384 */ - EVSYS_CHMUX_PRESCALER_32768_gc = (0x8F<<0), /* Prescaler, divide by 32768 */ - EVSYS_CHMUX_TCC0_OVF_gc = (0xC0<<0), /* Timer/Counter C0 Overflow */ - EVSYS_CHMUX_TCC0_ERR_gc = (0xC1<<0), /* Timer/Counter C0 Error */ - EVSYS_CHMUX_TCC0_CCA_gc = (0xC4<<0), /* Timer/Counter C0 Compare or Capture A */ - EVSYS_CHMUX_TCC0_CCB_gc = (0xC5<<0), /* Timer/Counter C0 Compare or Capture B */ - EVSYS_CHMUX_TCC0_CCC_gc = (0xC6<<0), /* Timer/Counter C0 Compare or Capture C */ - EVSYS_CHMUX_TCC0_CCD_gc = (0xC7<<0), /* Timer/Counter C0 Compare or Capture D */ - EVSYS_CHMUX_TCC1_OVF_gc = (0xC8<<0), /* Timer/Counter C1 Overflow */ - EVSYS_CHMUX_TCC1_ERR_gc = (0xC9<<0), /* Timer/Counter C1 Error */ - EVSYS_CHMUX_TCC1_CCA_gc = (0xCC<<0), /* Timer/Counter C1 Compare or Capture A */ - EVSYS_CHMUX_TCC1_CCB_gc = (0xCD<<0), /* Timer/Counter C1 Compare or Capture B */ - EVSYS_CHMUX_TCD0_OVF_gc = (0xD0<<0), /* Timer/Counter D0 Overflow */ - EVSYS_CHMUX_TCD0_ERR_gc = (0xD1<<0), /* Timer/Counter D0 Error */ - EVSYS_CHMUX_TCD0_CCA_gc = (0xD4<<0), /* Timer/Counter D0 Compare or Capture A */ - EVSYS_CHMUX_TCD0_CCB_gc = (0xD5<<0), /* Timer/Counter D0 Compare or Capture B */ - EVSYS_CHMUX_TCD0_CCC_gc = (0xD6<<0), /* Timer/Counter D0 Compare or Capture C */ - EVSYS_CHMUX_TCD0_CCD_gc = (0xD7<<0), /* Timer/Counter D0 Compare or Capture D */ - EVSYS_CHMUX_TCD1_OVF_gc = (0xD8<<0), /* Timer/Counter D1 Overflow */ - EVSYS_CHMUX_TCD1_ERR_gc = (0xD9<<0), /* Timer/Counter D1 Error */ - EVSYS_CHMUX_TCD1_CCA_gc = (0xDC<<0), /* Timer/Counter D1 Compare or Capture A */ - EVSYS_CHMUX_TCD1_CCB_gc = (0xDD<<0), /* Timer/Counter D1 Compare or Capture B */ - EVSYS_CHMUX_TCE0_OVF_gc = (0xE0<<0), /* Timer/Counter E0 Overflow */ - EVSYS_CHMUX_TCE0_ERR_gc = (0xE1<<0), /* Timer/Counter E0 Error */ - EVSYS_CHMUX_TCE0_CCA_gc = (0xE4<<0), /* Timer/Counter E0 Compare or Capture A */ - EVSYS_CHMUX_TCE0_CCB_gc = (0xE5<<0), /* Timer/Counter E0 Compare or Capture B */ - EVSYS_CHMUX_TCE0_CCC_gc = (0xE6<<0), /* Timer/Counter E0 Compare or Capture C */ - EVSYS_CHMUX_TCE0_CCD_gc = (0xE7<<0), /* Timer/Counter E0 Compare or Capture D */ - EVSYS_CHMUX_TCE1_OVF_gc = (0xE8<<0), /* Timer/Counter E1 Overflow */ - EVSYS_CHMUX_TCE1_ERR_gc = (0xE9<<0), /* Timer/Counter E1 Error */ - EVSYS_CHMUX_TCE1_CCA_gc = (0xEC<<0), /* Timer/Counter E1 Compare or Capture A */ - EVSYS_CHMUX_TCE1_CCB_gc = (0xED<<0), /* Timer/Counter E1 Compare or Capture B */ - EVSYS_CHMUX_TCF0_OVF_gc = (0xF0<<0), /* Timer/Counter F0 Overflow */ - EVSYS_CHMUX_TCF0_ERR_gc = (0xF1<<0), /* Timer/Counter F0 Error */ - EVSYS_CHMUX_TCF0_CCA_gc = (0xF4<<0), /* Timer/Counter F0 Compare or Capture A */ - EVSYS_CHMUX_TCF0_CCB_gc = (0xF5<<0), /* Timer/Counter F0 Compare or Capture B */ - EVSYS_CHMUX_TCF0_CCC_gc = (0xF6<<0), /* Timer/Counter F0 Compare or Capture C */ - EVSYS_CHMUX_TCF0_CCD_gc = (0xF7<<0), /* Timer/Counter F0 Compare or Capture D */ - EVSYS_CHMUX_TCF1_OVF_gc = (0xF8<<0), /* Timer/Counter F1 Overflow */ - EVSYS_CHMUX_TCF1_ERR_gc = (0xF9<<0), /* Timer/Counter F1 Error */ - EVSYS_CHMUX_TCF1_CCA_gc = (0xFC<<0), /* Timer/Counter F1 Compare or Capture A */ - EVSYS_CHMUX_TCF1_CCB_gc = (0xFD<<0), /* Timer/Counter F1 Compare or Capture B */ -} EVSYS_CHMUX_t; - - -/* --------------------------------------------------------------------------- -NVM - Non Volatile Memory Controller --------------------------------------------------------------------------- -*/ - -/* Non-volatile Memory Controller */ -typedef struct NVM_struct -{ - register8_t ADDR0; /* Address Register 0 */ - register8_t ADDR1; /* Address Register 1 */ - register8_t ADDR2; /* Address Register 2 */ - register8_t reserved_0x03; - register8_t DATA0; /* Data Register 0 */ - register8_t DATA1; /* Data Register 1 */ - register8_t DATA2; /* Data Register 2 */ - register8_t reserved_0x07; - register8_t reserved_0x08; - register8_t reserved_0x09; - register8_t CMD; /* Command */ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t INTCTRL; /* Interrupt Control */ - register8_t reserved_0x0E; - register8_t STATUS; /* Status */ - register8_t LOCK_BITS; /* Lock Bits (Changed from LOCKBITS to avoid avr-libc collision) */ -} NVM_t; - -/* NVM Command */ -typedef enum NVM_CMD_enum -{ - NVM_CMD_NO_OPERATION_gc = (0x00<<0), /* Noop/Ordinary LPM */ - NVM_CMD_READ_USER_SIG_ROW_gc = (0x01<<0), /* Read user signature row */ - NVM_CMD_READ_CALIB_ROW_gc = (0x02<<0), /* Read calibration row */ - NVM_CMD_READ_EEPROM_gc = (0x06<<0), /* Read EEPROM */ - NVM_CMD_READ_FUSES_gc = (0x07<<0), /* Read fuse byte */ - NVM_CMD_WRITE_LOCK_BITS_gc = (0x08<<0), /* Write lock bits */ - NVM_CMD_ERASE_USER_SIG_ROW_gc = (0x18<<0), /* Erase user signature row */ - NVM_CMD_WRITE_USER_SIG_ROW_gc = (0x1A<<0), /* Write user signature row */ - NVM_CMD_ERASE_APP_gc = (0x20<<0), /* Erase Application Section */ - NVM_CMD_ERASE_APP_PAGE_gc = (0x22<<0), /* Erase Application Section page */ - NVM_CMD_LOAD_FLASH_BUFFER_gc = (0x23<<0), /* Load Flash page buffer */ - NVM_CMD_WRITE_APP_PAGE_gc = (0x24<<0), /* Write Application Section page */ - NVM_CMD_ERASE_WRITE_APP_PAGE_gc = (0x25<<0), /* Erase-and-write Application Section page */ - NVM_CMD_ERASE_FLASH_BUFFER_gc = (0x26<<0), /* Erase/flush Flash page buffer */ - NVM_CMD_ERASE_BOOT_PAGE_gc = (0x2A<<0), /* Erase Boot Section page */ - NVM_CMD_ERASE_FLASH_PAGE_gc = (0x2B<<0), /* Erase Flash Page */ - NVM_CMD_WRITE_BOOT_PAGE_gc = (0x2C<<0), /* Write Boot Section page */ - NVM_CMD_ERASE_WRITE_BOOT_PAGE_gc = (0x2D<<0), /* Erase-and-write Boot Section page */ - NVM_CMD_WRITE_FLASH_PAGE_gc = (0x2E<<0), /* Write Flash Page */ - NVM_CMD_ERASE_WRITE_FLASH_PAGE_gc = (0x2F<<0), /* Erase-and-write Flash Page */ - NVM_CMD_ERASE_EEPROM_gc = (0x30<<0), /* Erase EEPROM */ - NVM_CMD_ERASE_EEPROM_PAGE_gc = (0x32<<0), /* Erase EEPROM page */ - NVM_CMD_LOAD_EEPROM_BUFFER_gc = (0x33<<0), /* Load EEPROM page buffer */ - NVM_CMD_WRITE_EEPROM_PAGE_gc = (0x34<<0), /* Write EEPROM page */ - NVM_CMD_ERASE_WRITE_EEPROM_PAGE_gc = (0x35<<0), /* Erase-and-write EEPROM page */ - NVM_CMD_ERASE_EEPROM_BUFFER_gc = (0x36<<0), /* Erase/flush EEPROM page buffer */ - NVM_CMD_APP_CRC_gc = (0x38<<0), /* Application section CRC */ - NVM_CMD_BOOT_CRC_gc = (0x39<<0), /* Boot Section CRC */ - NVM_CMD_FLASH_RANGE_CRC_gc = (0x3A<<0), /* Flash Range CRC */ - NVM_CMD_CHIP_ERASE_gc = (0x40<<0), /* Erase Chip */ - NVM_CMD_READ_NVM_gc = (0x43<<0), /* Read NVM */ - NVM_CMD_WRITE_FUSE_gc = (0x4C<<0), /* Write Fuse byte */ - NVM_CMD_ERASE_BOOT_gc = (0x68<<0), /* Erase Boot Section */ - NVM_CMD_FLASH_CRC_gc = (0x78<<0), /* Flash CRC */ -} NVM_CMD_t; - -/* SPM ready interrupt level */ -typedef enum NVM_SPMLVL_enum -{ - NVM_SPMLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ - NVM_SPMLVL_LO_gc = (0x01<<2), /* Low level */ - NVM_SPMLVL_MED_gc = (0x02<<2), /* Medium level */ - NVM_SPMLVL_HI_gc = (0x03<<2), /* High level */ -} NVM_SPMLVL_t; - -/* EEPROM ready interrupt level */ -typedef enum NVM_EELVL_enum -{ - NVM_EELVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ - NVM_EELVL_LO_gc = (0x01<<0), /* Low level */ - NVM_EELVL_MED_gc = (0x02<<0), /* Medium level */ - NVM_EELVL_HI_gc = (0x03<<0), /* High level */ -} NVM_EELVL_t; - -/* Boot lock bits - boot setcion */ -typedef enum NVM_BLBB_enum -{ - NVM_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ - NVM_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ - NVM_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ - NVM_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ -} NVM_BLBB_t; - -/* Boot lock bits - application section */ -typedef enum NVM_BLBA_enum -{ - NVM_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ - NVM_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ - NVM_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ - NVM_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ -} NVM_BLBA_t; - -/* Boot lock bits - application table section */ -typedef enum NVM_BLBAT_enum -{ - NVM_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ - NVM_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ - NVM_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ - NVM_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ -} NVM_BLBAT_t; - -/* Lock bits */ -typedef enum NVM_LB_enum -{ - NVM_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ - NVM_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ - NVM_LB_NOLOCK_gc = (0x03<<0), /* No locks */ -} NVM_LB_t; - - -/* --------------------------------------------------------------------------- -ADC - Analog/Digital Converter --------------------------------------------------------------------------- -*/ - -/* ADC Channel */ -typedef struct ADC_CH_struct -{ - register8_t CTRL; /* Control Register */ - register8_t MUXCTRL; /* MUX Control */ - register8_t INTCTRL; /* Channel Interrupt Control Register */ - register8_t INTFLAGS; /* Interrupt Flags */ - _WORDREGISTER(RES); /* Channel Result */ - register8_t SCAN; /* Input Channel Scan */ - register8_t reserved_0x07; -} ADC_CH_t; - - -/* Analog-to-Digital Converter */ -typedef struct ADC_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t REFCTRL; /* Reference Control */ - register8_t EVCTRL; /* Event Control */ - register8_t PRESCALER; /* Clock Prescaler */ - register8_t reserved_0x05; - register8_t INTFLAGS; /* Interrupt Flags */ - register8_t TEMP; /* Temporary Register */ - register8_t reserved_0x08; - register8_t reserved_0x09; - register8_t reserved_0x0A; - register8_t reserved_0x0B; - _WORDREGISTER(CAL); /* Calibration Value */ - register8_t reserved_0x0E; - register8_t reserved_0x0F; - _WORDREGISTER(CH0RES); /* Channel 0 Result */ - _WORDREGISTER(CH1RES); /* Channel 1 Result */ - _WORDREGISTER(CH2RES); /* Channel 2 Result */ - _WORDREGISTER(CH3RES); /* Channel 3 Result */ - _WORDREGISTER(CMP); /* Compare Value */ - register8_t reserved_0x1A; - register8_t reserved_0x1B; - register8_t reserved_0x1C; - register8_t reserved_0x1D; - register8_t reserved_0x1E; - register8_t reserved_0x1F; - ADC_CH_t CH0; /* ADC Channel 0 */ - ADC_CH_t CH1; /* ADC Channel 1 */ - ADC_CH_t CH2; /* ADC Channel 2 */ - ADC_CH_t CH3; /* ADC Channel 3 */ -} ADC_t; - -/* Positive input multiplexer selection */ -typedef enum ADC_CH_MUXPOS_enum -{ - ADC_CH_MUXPOS_PIN0_gc = (0x00<<3), /* Input pin 0 */ - ADC_CH_MUXPOS_PIN1_gc = (0x01<<3), /* Input pin 1 */ - ADC_CH_MUXPOS_PIN2_gc = (0x02<<3), /* Input pin 2 */ - ADC_CH_MUXPOS_PIN3_gc = (0x03<<3), /* Input pin 3 */ - ADC_CH_MUXPOS_PIN4_gc = (0x04<<3), /* Input pin 4 */ - ADC_CH_MUXPOS_PIN5_gc = (0x05<<3), /* Input pin 5 */ - ADC_CH_MUXPOS_PIN6_gc = (0x06<<3), /* Input pin 6 */ - ADC_CH_MUXPOS_PIN7_gc = (0x07<<3), /* Input pin 7 */ - ADC_CH_MUXPOS_PIN8_gc = (0x08<<3), /* Input pin 8 */ - ADC_CH_MUXPOS_PIN9_gc = (0x09<<3), /* Input pin 9 */ - ADC_CH_MUXPOS_PIN10_gc = (0x0A<<3), /* Input pin 10 */ - ADC_CH_MUXPOS_PIN11_gc = (0x0B<<3), /* Input pin 11 */ - ADC_CH_MUXPOS_PIN12_gc = (0x0C<<3), /* Input pin 12 */ - ADC_CH_MUXPOS_PIN13_gc = (0x0D<<3), /* Input pin 13 */ - ADC_CH_MUXPOS_PIN14_gc = (0x0E<<3), /* Input pin 14 */ - ADC_CH_MUXPOS_PIN15_gc = (0x0F<<3), /* Input pin 15 */ -} ADC_CH_MUXPOS_t; - -/* Internal input multiplexer selections */ -typedef enum ADC_CH_MUXINT_enum -{ - ADC_CH_MUXINT_TEMP_gc = (0x00<<3), /* Temperature Reference */ - ADC_CH_MUXINT_BANDGAP_gc = (0x01<<3), /* Bandgap Reference */ - ADC_CH_MUXINT_SCALEDVCC_gc = (0x02<<3), /* 1/10 scaled VCC */ - ADC_CH_MUXINT_DAC_gc = (0x03<<3), /* DAC output */ -} ADC_CH_MUXINT_t; - -/* Negative input multiplexer selection */ -typedef enum ADC_CH_MUXNEG_enum -{ - ADC_CH_MUXNEG_PIN0_gc = (0x00<<0), /* Input pin 0 (Input Mode = 2) */ - ADC_CH_MUXNEG_PIN1_gc = (0x01<<0), /* Input pin 1 (Input Mode = 2) */ - ADC_CH_MUXNEG_PIN2_gc = (0x02<<0), /* Input pin 2 (Input Mode = 2) */ - ADC_CH_MUXNEG_PIN3_gc = (0x03<<0), /* Input pin 3 (Input Mode = 2) */ - ADC_CH_MUXNEG_PIN4_gc = (0x00<<0), /* Input pin 4 (Input Mode = 3) */ - ADC_CH_MUXNEG_PIN5_gc = (0x01<<0), /* Input pin 5 (Input Mode = 3) */ - ADC_CH_MUXNEG_PIN6_gc = (0x02<<0), /* Input pin 6 (Input Mode = 3) */ - ADC_CH_MUXNEG_PIN7_gc = (0x03<<0), /* Input pin 7 (Input Mode = 3) */ - ADC_CH_MUXNEG_GND_MODE3_gc = (0x05<<0), /* PAD Ground (Input Mode = 2) */ - ADC_CH_MUXNEG_INTGND_MODE3_gc = (0x07<<0), /* Internal Ground (Input Mode = 2) */ - ADC_CH_MUXNEG_INTGND_MODE4_gc = (0x04<<0), /* Internal Ground (Input Mode = 3) */ - ADC_CH_MUXNEG_GND_MODE4_gc = (0x07<<0), /* PAD Ground (Input Mode = 3) */ -} ADC_CH_MUXNEG_t; - -/* Input mode */ -typedef enum ADC_CH_INPUTMODE_enum -{ - ADC_CH_INPUTMODE_INTERNAL_gc = (0x00<<0), /* Internal inputs, no gain */ - ADC_CH_INPUTMODE_SINGLEENDED_gc = (0x01<<0), /* Single-ended input, no gain */ - ADC_CH_INPUTMODE_DIFF_gc = (0x02<<0), /* Differential input, no gain */ - ADC_CH_INPUTMODE_DIFFWGAIN_gc = (0x03<<0), /* Differential input, with gain */ -} ADC_CH_INPUTMODE_t; - -/* Gain factor */ -typedef enum ADC_CH_GAIN_enum -{ - ADC_CH_GAIN_1X_gc = (0x00<<2), /* 1x gain */ - ADC_CH_GAIN_2X_gc = (0x01<<2), /* 2x gain */ - ADC_CH_GAIN_4X_gc = (0x02<<2), /* 4x gain */ - ADC_CH_GAIN_8X_gc = (0x03<<2), /* 8x gain */ - ADC_CH_GAIN_16X_gc = (0x04<<2), /* 16x gain */ - ADC_CH_GAIN_32X_gc = (0x05<<2), /* 32x gain */ - ADC_CH_GAIN_64X_gc = (0x06<<2), /* 64x gain */ - ADC_CH_GAIN_DIV2_gc = (0x07<<2), /* x/2 gain */ -} ADC_CH_GAIN_t; - -/* Conversion result resolution */ -typedef enum ADC_RESOLUTION_enum -{ - ADC_RESOLUTION_12BIT_gc = (0x00<<1), /* 12-bit right-adjusted result */ - ADC_RESOLUTION_8BIT_gc = (0x02<<1), /* 8-bit right-adjusted result */ - ADC_RESOLUTION_LEFT12BIT_gc = (0x03<<1), /* 12-bit left-adjusted result */ -} ADC_RESOLUTION_t; - -/* Current Limitation Mode */ -typedef enum ADC_CURRLIMIT_enum -{ - ADC_CURRLIMIT_NO_gc = (0x00<<5), /* No limit */ - ADC_CURRLIMIT_LOW_gc = (0x01<<5), /* Low current limit, max. sampling rate 1.5MSPS */ - ADC_CURRLIMIT_MED_gc = (0x02<<5), /* Medium current limit, max. sampling rate 1MSPS */ - ADC_CURRLIMIT_HIGH_gc = (0x03<<5), /* High current limit, max. sampling rate 0.5MSPS */ -} ADC_CURRLIMIT_t; - -/* Voltage reference selection */ -typedef enum ADC_REFSEL_enum -{ - ADC_REFSEL_INT1V_gc = (0x00<<4), /* Internal 1V */ - ADC_REFSEL_INTVCC_gc = (0x01<<4), /* Internal VCC / 1.6 */ - ADC_REFSEL_AREFA_gc = (0x02<<4), /* External reference on PORT A */ - ADC_REFSEL_AREFB_gc = (0x03<<4), /* External reference on PORT B */ - ADC_REFSEL_INTVCC2_gc = (0x04<<4), /* Internal VCC / 2 */ -} ADC_REFSEL_t; - -/* Channel sweep selection */ -typedef enum ADC_SWEEP_enum -{ - ADC_SWEEP_0_gc = (0x00<<6), /* ADC Channel 0 */ - ADC_SWEEP_01_gc = (0x01<<6), /* ADC Channel 0,1 */ - ADC_SWEEP_012_gc = (0x02<<6), /* ADC Channel 0,1,2 */ - ADC_SWEEP_0123_gc = (0x03<<6), /* ADC Channel 0,1,2,3 */ -} ADC_SWEEP_t; - -/* Event channel input selection */ -typedef enum ADC_EVSEL_enum -{ - ADC_EVSEL_0123_gc = (0x00<<3), /* Event Channel 0,1,2,3 */ - ADC_EVSEL_1234_gc = (0x01<<3), /* Event Channel 1,2,3,4 */ - ADC_EVSEL_2345_gc = (0x02<<3), /* Event Channel 2,3,4,5 */ - ADC_EVSEL_3456_gc = (0x03<<3), /* Event Channel 3,4,5,6 */ - ADC_EVSEL_4567_gc = (0x04<<3), /* Event Channel 4,5,6,7 */ - ADC_EVSEL_567_gc = (0x05<<3), /* Event Channel 5,6,7 */ - ADC_EVSEL_67_gc = (0x06<<3), /* Event Channel 6,7 */ - ADC_EVSEL_7_gc = (0x07<<3), /* Event Channel 7 */ -} ADC_EVSEL_t; - -/* Event action selection */ -typedef enum ADC_EVACT_enum -{ - ADC_EVACT_NONE_gc = (0x00<<0), /* No event action */ - ADC_EVACT_CH0_gc = (0x01<<0), /* First event triggers channel 0 */ - ADC_EVACT_CH01_gc = (0x02<<0), /* First two events trigger channel 0,1 */ - ADC_EVACT_CH012_gc = (0x03<<0), /* First three events trigger channel 0,1,2 */ - ADC_EVACT_CH0123_gc = (0x04<<0), /* Events trigger channel 0,1,2,3 */ - ADC_EVACT_SWEEP_gc = (0x05<<0), /* First event triggers sweep */ - ADC_EVACT_SYNCSWEEP_gc = (0x06<<0), /* The ADC is flushed and restarted for accurate timing */ -} ADC_EVACT_t; - -/* Interupt mode */ -typedef enum ADC_CH_INTMODE_enum -{ - ADC_CH_INTMODE_COMPLETE_gc = (0x00<<2), /* Interrupt on conversion complete */ - ADC_CH_INTMODE_BELOW_gc = (0x01<<2), /* Interrupt on result below compare value */ - ADC_CH_INTMODE_ABOVE_gc = (0x03<<2), /* Interrupt on result above compare value */ -} ADC_CH_INTMODE_t; - -/* Interrupt level */ -typedef enum ADC_CH_INTLVL_enum -{ - ADC_CH_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ - ADC_CH_INTLVL_LO_gc = (0x01<<0), /* Low level */ - ADC_CH_INTLVL_MED_gc = (0x02<<0), /* Medium level */ - ADC_CH_INTLVL_HI_gc = (0x03<<0), /* High level */ -} ADC_CH_INTLVL_t; - -/* DMA request selection */ -typedef enum ADC_DMASEL_enum -{ - ADC_DMASEL_OFF_gc = (0x00<<6), /* Combined DMA request OFF */ - ADC_DMASEL_CH01_gc = (0x01<<6), /* ADC Channel 0 or 1 */ - ADC_DMASEL_CH012_gc = (0x02<<6), /* ADC Channel 0 or 1 or 2 */ - ADC_DMASEL_CH0123_gc = (0x03<<6), /* ADC Channel 0 or 1 or 2 or 3 */ -} ADC_DMASEL_t; - -/* Clock prescaler */ -typedef enum ADC_PRESCALER_enum -{ - ADC_PRESCALER_DIV4_gc = (0x00<<0), /* Divide clock by 4 */ - ADC_PRESCALER_DIV8_gc = (0x01<<0), /* Divide clock by 8 */ - ADC_PRESCALER_DIV16_gc = (0x02<<0), /* Divide clock by 16 */ - ADC_PRESCALER_DIV32_gc = (0x03<<0), /* Divide clock by 32 */ - ADC_PRESCALER_DIV64_gc = (0x04<<0), /* Divide clock by 64 */ - ADC_PRESCALER_DIV128_gc = (0x05<<0), /* Divide clock by 128 */ - ADC_PRESCALER_DIV256_gc = (0x06<<0), /* Divide clock by 256 */ - ADC_PRESCALER_DIV512_gc = (0x07<<0), /* Divide clock by 512 */ -} ADC_PRESCALER_t; - - -/* --------------------------------------------------------------------------- -DAC - Digital/Analog Converter --------------------------------------------------------------------------- -*/ - -/* Digital-to-Analog Converter */ -typedef struct DAC_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t CTRLC; /* Control Register C */ - register8_t EVCTRL; /* Event Input Control */ - register8_t reserved_0x04; - register8_t STATUS; /* Status */ - register8_t reserved_0x06; - register8_t reserved_0x07; - register8_t CH0GAINCAL; /* Gain Calibration */ - register8_t CH0OFFSETCAL; /* Offset Calibration */ - register8_t CH1GAINCAL; /* Gain Calibration */ - register8_t CH1OFFSETCAL; /* Offset Calibration */ - register8_t reserved_0x0C; - register8_t reserved_0x0D; - register8_t reserved_0x0E; - register8_t reserved_0x0F; - register8_t reserved_0x10; - register8_t reserved_0x11; - register8_t reserved_0x12; - register8_t reserved_0x13; - register8_t reserved_0x14; - register8_t reserved_0x15; - register8_t reserved_0x16; - register8_t reserved_0x17; - _WORDREGISTER(CH0DATA); /* Channel 0 Data */ - _WORDREGISTER(CH1DATA); /* Channel 1 Data */ -} DAC_t; - -/* Output channel selection */ -typedef enum DAC_CHSEL_enum -{ - DAC_CHSEL_SINGLE_gc = (0x00<<5), /* Single channel operation (Channel 0 only) */ - DAC_CHSEL_SINGLE1_gc = (0x01<<5), /* Single channel operation (Channel 1 only) */ - DAC_CHSEL_DUAL_gc = (0x02<<5), /* Dual channel operation (Channel 0 and channel 1) */ -} DAC_CHSEL_t; - -/* Reference voltage selection */ -typedef enum DAC_REFSEL_enum -{ - DAC_REFSEL_INT1V_gc = (0x00<<3), /* Internal 1V */ - DAC_REFSEL_AVCC_gc = (0x01<<3), /* Analog supply voltage */ - DAC_REFSEL_AREFA_gc = (0x02<<3), /* External reference on AREF on PORTA */ - DAC_REFSEL_AREFB_gc = (0x03<<3), /* External reference on AREF on PORTB */ -} DAC_REFSEL_t; - -/* Event channel selection */ -typedef enum DAC_EVSEL_enum -{ - DAC_EVSEL_0_gc = (0x00<<0), /* Event Channel 0 */ - DAC_EVSEL_1_gc = (0x01<<0), /* Event Channel 1 */ - DAC_EVSEL_2_gc = (0x02<<0), /* Event Channel 2 */ - DAC_EVSEL_3_gc = (0x03<<0), /* Event Channel 3 */ - DAC_EVSEL_4_gc = (0x04<<0), /* Event Channel 4 */ - DAC_EVSEL_5_gc = (0x05<<0), /* Event Channel 5 */ - DAC_EVSEL_6_gc = (0x06<<0), /* Event Channel 6 */ - DAC_EVSEL_7_gc = (0x07<<0), /* Event Channel 7 */ -} DAC_EVSEL_t; - - -/* --------------------------------------------------------------------------- -AC - Analog Comparator --------------------------------------------------------------------------- -*/ - -/* Analog Comparator */ -typedef struct AC_struct -{ - register8_t AC0CTRL; /* Analog Comparator 0 Control */ - register8_t AC1CTRL; /* Analog Comparator 1 Control */ - register8_t AC0MUXCTRL; /* Analog Comparator 0 MUX Control */ - register8_t AC1MUXCTRL; /* Analog Comparator 1 MUX Control */ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t WINCTRL; /* Window Mode Control */ - register8_t STATUS; /* Status */ -} AC_t; - -/* Interrupt mode */ -typedef enum AC_INTMODE_enum -{ - AC_INTMODE_BOTHEDGES_gc = (0x00<<6), /* Interrupt on both edges */ - AC_INTMODE_FALLING_gc = (0x02<<6), /* Interrupt on falling edge */ - AC_INTMODE_RISING_gc = (0x03<<6), /* Interrupt on rising edge */ -} AC_INTMODE_t; - -/* Interrupt level */ -typedef enum AC_INTLVL_enum -{ - AC_INTLVL_OFF_gc = (0x00<<4), /* Interrupt disabled */ - AC_INTLVL_LO_gc = (0x01<<4), /* Low level */ - AC_INTLVL_MED_gc = (0x02<<4), /* Medium level */ - AC_INTLVL_HI_gc = (0x03<<4), /* High level */ -} AC_INTLVL_t; - -/* Hysteresis mode selection */ -typedef enum AC_HYSMODE_enum -{ - AC_HYSMODE_NO_gc = (0x00<<1), /* No hysteresis */ - AC_HYSMODE_SMALL_gc = (0x01<<1), /* Small hysteresis */ - AC_HYSMODE_LARGE_gc = (0x02<<1), /* Large hysteresis */ -} AC_HYSMODE_t; - -/* Positive input multiplexer selection */ -typedef enum AC_MUXPOS_enum -{ - AC_MUXPOS_PIN0_gc = (0x00<<3), /* Pin 0 */ - AC_MUXPOS_PIN1_gc = (0x01<<3), /* Pin 1 */ - AC_MUXPOS_PIN2_gc = (0x02<<3), /* Pin 2 */ - AC_MUXPOS_PIN3_gc = (0x03<<3), /* Pin 3 */ - AC_MUXPOS_PIN4_gc = (0x04<<3), /* Pin 4 */ - AC_MUXPOS_PIN5_gc = (0x05<<3), /* Pin 5 */ - AC_MUXPOS_PIN6_gc = (0x06<<3), /* Pin 6 */ - AC_MUXPOS_DAC_gc = (0x07<<3), /* DAC output */ -} AC_MUXPOS_t; - -/* Negative input multiplexer selection */ -typedef enum AC_MUXNEG_enum -{ - AC_MUXNEG_PIN0_gc = (0x00<<0), /* Pin 0 */ - AC_MUXNEG_PIN1_gc = (0x01<<0), /* Pin 1 */ - AC_MUXNEG_PIN3_gc = (0x02<<0), /* Pin 3 */ - AC_MUXNEG_PIN5_gc = (0x03<<0), /* Pin 5 */ - AC_MUXNEG_PIN7_gc = (0x04<<0), /* Pin 7 */ - AC_MUXNEG_DAC_gc = (0x05<<0), /* DAC output */ - AC_MUXNEG_BANDGAP_gc = (0x06<<0), /* Bandgap Reference */ - AC_MUXNEG_SCALER_gc = (0x07<<0), /* Internal voltage scaler */ -} AC_MUXNEG_t; - -/* Windows interrupt mode */ -typedef enum AC_WINTMODE_enum -{ - AC_WINTMODE_ABOVE_gc = (0x00<<2), /* Interrupt on above window */ - AC_WINTMODE_INSIDE_gc = (0x01<<2), /* Interrupt on inside window */ - AC_WINTMODE_BELOW_gc = (0x02<<2), /* Interrupt on below window */ - AC_WINTMODE_OUTSIDE_gc = (0x03<<2), /* Interrupt on outside window */ -} AC_WINTMODE_t; - -/* Window interrupt level */ -typedef enum AC_WINTLVL_enum -{ - AC_WINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ - AC_WINTLVL_LO_gc = (0x01<<0), /* Low priority */ - AC_WINTLVL_MED_gc = (0x02<<0), /* Medium priority */ - AC_WINTLVL_HI_gc = (0x03<<0), /* High priority */ -} AC_WINTLVL_t; - -/* Window mode state */ -typedef enum AC_WSTATE_enum -{ - AC_WSTATE_ABOVE_gc = (0x00<<6), /* Signal above window */ - AC_WSTATE_INSIDE_gc = (0x01<<6), /* Signal inside window */ - AC_WSTATE_BELOW_gc = (0x02<<6), /* Signal below window */ -} AC_WSTATE_t; - - -/* --------------------------------------------------------------------------- -RTC - Real-Time Counter --------------------------------------------------------------------------- -*/ - -/* Real-Time Counter */ -typedef struct RTC_struct -{ - register8_t CTRL; /* Control Register */ - register8_t STATUS; /* Status Register */ - register8_t INTCTRL; /* Interrupt Control Register */ - register8_t INTFLAGS; /* Interrupt Flags */ - register8_t TEMP; /* Temporary register */ - register8_t reserved_0x05; - register8_t reserved_0x06; - register8_t reserved_0x07; - _WORDREGISTER(CNT); /* Count Register */ - _WORDREGISTER(PER); /* Period Register */ - _WORDREGISTER(COMP); /* Compare Register */ -} RTC_t; - -/* Prescaler Factor */ -typedef enum RTC_PRESCALER_enum -{ - RTC_PRESCALER_OFF_gc = (0x00<<0), /* RTC Off */ - RTC_PRESCALER_DIV1_gc = (0x01<<0), /* RTC Clock */ - RTC_PRESCALER_DIV2_gc = (0x02<<0), /* RTC Clock / 2 */ - RTC_PRESCALER_DIV8_gc = (0x03<<0), /* RTC Clock / 8 */ - RTC_PRESCALER_DIV16_gc = (0x04<<0), /* RTC Clock / 16 */ - RTC_PRESCALER_DIV64_gc = (0x05<<0), /* RTC Clock / 64 */ - RTC_PRESCALER_DIV256_gc = (0x06<<0), /* RTC Clock / 256 */ - RTC_PRESCALER_DIV1024_gc = (0x07<<0), /* RTC Clock / 1024 */ -} RTC_PRESCALER_t; - -/* Compare Interrupt level */ -typedef enum RTC_COMPINTLVL_enum -{ - RTC_COMPINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ - RTC_COMPINTLVL_LO_gc = (0x01<<2), /* Low Level */ - RTC_COMPINTLVL_MED_gc = (0x02<<2), /* Medium Level */ - RTC_COMPINTLVL_HI_gc = (0x03<<2), /* High Level */ -} RTC_COMPINTLVL_t; - -/* Overflow Interrupt level */ -typedef enum RTC_OVFINTLVL_enum -{ - RTC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - RTC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ - RTC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ - RTC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ -} RTC_OVFINTLVL_t; - - -/* --------------------------------------------------------------------------- -TWI - Two-Wire Interface --------------------------------------------------------------------------- -*/ - -/* */ -typedef struct TWI_MASTER_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t CTRLC; /* Control Register C */ - register8_t STATUS; /* Status Register */ - register8_t BAUD; /* Baurd Rate Control Register */ - register8_t ADDR; /* Address Register */ - register8_t DATA; /* Data Register */ -} TWI_MASTER_t; - - -/* */ -typedef struct TWI_SLAVE_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t STATUS; /* Status Register */ - register8_t ADDR; /* Address Register */ - register8_t DATA; /* Data Register */ - register8_t ADDRMASK; /* Address Mask Register */ -} TWI_SLAVE_t; - - -/* Two-Wire Interface */ -typedef struct TWI_struct -{ - register8_t CTRL; /* TWI Common Control Register */ - TWI_MASTER_t MASTER; /* TWI master module */ - TWI_SLAVE_t SLAVE; /* TWI slave module */ -} TWI_t; - -/* SDA Hold Time */ -typedef enum TWI_SDAHOLD_enum -{ - TWI_SDAHOLD_OFF_gc = (0x00<<1), /* SDA Hold Time off */ - TWI_SDAHOLD_50NS_gc = (0x01<<1), /* SDA Hold Time 50 ns */ - TWI_SDAHOLD_300NS_gc = (0x02<<1), /* SDA Hold Time 300 ns */ - TWI_SDAHOLD_400NS_gc = (0x03<<1), /* SDA Hold Time 400 ns */ -} TWI_SDAHOLD_t; - -/* Master Interrupt Level */ -typedef enum TWI_MASTER_INTLVL_enum -{ - TWI_MASTER_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ - TWI_MASTER_INTLVL_LO_gc = (0x01<<6), /* Low Level */ - TWI_MASTER_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ - TWI_MASTER_INTLVL_HI_gc = (0x03<<6), /* High Level */ -} TWI_MASTER_INTLVL_t; - -/* Inactive Timeout */ -typedef enum TWI_MASTER_TIMEOUT_enum -{ - TWI_MASTER_TIMEOUT_DISABLED_gc = (0x00<<2), /* Bus Timeout Disabled */ - TWI_MASTER_TIMEOUT_50US_gc = (0x01<<2), /* 50 Microseconds */ - TWI_MASTER_TIMEOUT_100US_gc = (0x02<<2), /* 100 Microseconds */ - TWI_MASTER_TIMEOUT_200US_gc = (0x03<<2), /* 200 Microseconds */ -} TWI_MASTER_TIMEOUT_t; - -/* Master Command */ -typedef enum TWI_MASTER_CMD_enum -{ - TWI_MASTER_CMD_NOACT_gc = (0x00<<0), /* No Action */ - TWI_MASTER_CMD_REPSTART_gc = (0x01<<0), /* Issue Repeated Start Condition */ - TWI_MASTER_CMD_RECVTRANS_gc = (0x02<<0), /* Receive or Transmit Data */ - TWI_MASTER_CMD_STOP_gc = (0x03<<0), /* Issue Stop Condition */ -} TWI_MASTER_CMD_t; - -/* Master Bus State */ -typedef enum TWI_MASTER_BUSSTATE_enum -{ - TWI_MASTER_BUSSTATE_UNKNOWN_gc = (0x00<<0), /* Unknown Bus State */ - TWI_MASTER_BUSSTATE_IDLE_gc = (0x01<<0), /* Bus is Idle */ - TWI_MASTER_BUSSTATE_OWNER_gc = (0x02<<0), /* This Module Controls The Bus */ - TWI_MASTER_BUSSTATE_BUSY_gc = (0x03<<0), /* The Bus is Busy */ -} TWI_MASTER_BUSSTATE_t; - -/* Slave Interrupt Level */ -typedef enum TWI_SLAVE_INTLVL_enum -{ - TWI_SLAVE_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ - TWI_SLAVE_INTLVL_LO_gc = (0x01<<6), /* Low Level */ - TWI_SLAVE_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ - TWI_SLAVE_INTLVL_HI_gc = (0x03<<6), /* High Level */ -} TWI_SLAVE_INTLVL_t; - -/* Slave Command */ -typedef enum TWI_SLAVE_CMD_enum -{ - TWI_SLAVE_CMD_NOACT_gc = (0x00<<0), /* No Action */ - TWI_SLAVE_CMD_COMPTRANS_gc = (0x02<<0), /* Used To Complete a Transaction */ - TWI_SLAVE_CMD_RESPONSE_gc = (0x03<<0), /* Used in Response to Address/Data Interrupt */ -} TWI_SLAVE_CMD_t; - - -/* --------------------------------------------------------------------------- -USB - USB --------------------------------------------------------------------------- -*/ - -/* USB Endpoint */ -typedef struct USB_EP_struct -{ - register8_t STATUS; /* Endpoint Status */ - register8_t CTRL; /* Endpoint Control */ - _WORDREGISTER(CNT); /* USB Endpoint Counter */ - _WORDREGISTER(DATAPTR); /* Data Pointer */ - _WORDREGISTER(AUXDATA); /* Auxiliary Data */ -} USB_EP_t; - - -/* Universal Serial Bus */ -typedef struct USB_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t STATUS; /* Status Register */ - register8_t ADDR; /* Address Register */ - register8_t FIFOWP; /* FIFO Write Pointer Register */ - register8_t FIFORP; /* FIFO Read Pointer Register */ - _WORDREGISTER(EPPTR); /* Endpoint Configuration Table Pointer */ - register8_t INTCTRLA; /* Interrupt Control Register A */ - register8_t INTCTRLB; /* Interrupt Control Register B */ - register8_t INTFLAGSACLR; /* Clear Interrupt Flag Register A */ - register8_t INTFLAGSASET; /* Set Interrupt Flag Register A */ - register8_t INTFLAGSBCLR; /* Clear Interrupt Flag Register B */ - register8_t INTFLAGSBSET; /* Set Interrupt Flag Register B */ - register8_t reserved_0x0E; - register8_t reserved_0x0F; - register8_t reserved_0x10; - register8_t reserved_0x11; - register8_t reserved_0x12; - register8_t reserved_0x13; - register8_t reserved_0x14; - register8_t reserved_0x15; - register8_t reserved_0x16; - register8_t reserved_0x17; - register8_t reserved_0x18; - register8_t reserved_0x19; - register8_t reserved_0x1A; - register8_t reserved_0x1B; - register8_t reserved_0x1C; - register8_t reserved_0x1D; - register8_t reserved_0x1E; - register8_t reserved_0x1F; - register8_t reserved_0x20; - register8_t reserved_0x21; - register8_t reserved_0x22; - register8_t reserved_0x23; - register8_t reserved_0x24; - register8_t reserved_0x25; - register8_t reserved_0x26; - register8_t reserved_0x27; - register8_t reserved_0x28; - register8_t reserved_0x29; - register8_t reserved_0x2A; - register8_t reserved_0x2B; - register8_t reserved_0x2C; - register8_t reserved_0x2D; - register8_t reserved_0x2E; - register8_t reserved_0x2F; - register8_t reserved_0x30; - register8_t reserved_0x31; - register8_t reserved_0x32; - register8_t reserved_0x33; - register8_t reserved_0x34; - register8_t reserved_0x35; - register8_t reserved_0x36; - register8_t reserved_0x37; - register8_t reserved_0x38; - register8_t reserved_0x39; - register8_t CAL0; /* Calibration Byte 0 */ - register8_t CAL1; /* Calibration Byte 1 */ -} USB_t; - - -/* USB Endpoint Table */ -typedef struct USB_EP_TABLE_struct -{ - USB_EP_t EP0OUT; /* Endpoint 0 */ - USB_EP_t EP0IN; /* Endpoint 0 */ - USB_EP_t EP1OUT; /* Endpoint 1 */ - USB_EP_t EP1IN; /* Endpoint 1 */ - USB_EP_t EP2OUT; /* Endpoint 2 */ - USB_EP_t EP2IN; /* Endpoint 2 */ - USB_EP_t EP3OUT; /* Endpoint 3 */ - USB_EP_t EP3IN; /* Endpoint 3 */ - USB_EP_t EP4OUT; /* Endpoint 4 */ - USB_EP_t EP4IN; /* Endpoint 4 */ - USB_EP_t EP5OUT; /* Endpoint 5 */ - USB_EP_t EP5IN; /* Endpoint 5 */ - USB_EP_t EP6OUT; /* Endpoint 6 */ - USB_EP_t EP6IN; /* Endpoint 6 */ - USB_EP_t EP7OUT; /* Endpoint 7 */ - USB_EP_t EP7IN; /* Endpoint 7 */ - USB_EP_t EP8OUT; /* Endpoint 8 */ - USB_EP_t EP8IN; /* Endpoint 8 */ - USB_EP_t EP9OUT; /* Endpoint 9 */ - USB_EP_t EP9IN; /* Endpoint 9 */ - USB_EP_t EP10OUT; /* Endpoint 10 */ - USB_EP_t EP10IN; /* Endpoint 10 */ - USB_EP_t EP11OUT; /* Endpoint 11 */ - USB_EP_t EP11IN; /* Endpoint 11 */ - USB_EP_t EP12OUT; /* Endpoint 12 */ - USB_EP_t EP12IN; /* Endpoint 12 */ - USB_EP_t EP13OUT; /* Endpoint 13 */ - USB_EP_t EP13IN; /* Endpoint 13 */ - USB_EP_t EP14OUT; /* Endpoint 14 */ - USB_EP_t EP14IN; /* Endpoint 14 */ - USB_EP_t EP15OUT; /* Endpoint 15 */ - USB_EP_t EP15IN; /* Endpoint 15 */ - register8_t reserved_0x100; - register8_t reserved_0x101; - register8_t reserved_0x102; - register8_t reserved_0x103; - register8_t reserved_0x104; - register8_t reserved_0x105; - register8_t reserved_0x106; - register8_t reserved_0x107; - register8_t reserved_0x108; - register8_t reserved_0x109; - register8_t reserved_0x10A; - register8_t reserved_0x10B; - register8_t reserved_0x10C; - register8_t reserved_0x10D; - register8_t reserved_0x10E; - register8_t reserved_0x10F; - register8_t FRAMENUML; /* Frame Number Low Byte */ - register8_t FRAMENUMH; /* Frame Number High Byte */ -} USB_EP_TABLE_t; - -/* Interrupt level */ -typedef enum USB_INTLVL_enum -{ - USB_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ - USB_INTLVL_LO_gc = (0x01<<0), /* Low level */ - USB_INTLVL_MED_gc = (0x02<<0), /* Medium level */ - USB_INTLVL_HI_gc = (0x03<<0), /* High level */ -} USB_INTLVL_t; - -/* USB Endpoint Type */ -typedef enum USB_EP_TYPE_enum -{ - USB_EP_TYPE_DISABLE_gc = (0x00<<6), /* Endpoint Disabled */ - USB_EP_TYPE_CONTROL_gc = (0x01<<6), /* Control */ - USB_EP_TYPE_BULK_gc = (0x02<<6), /* Bulk/Interrupt */ - USB_EP_TYPE_ISOCHRONOUS_gc = (0x03<<6), /* Isochronous */ -} USB_EP_TYPE_t; - -/* USB Endpoint Buffersize */ -typedef enum USB_EP_BUFSIZE_enum -{ - USB_EP_BUFSIZE_8_gc = (0x00<<0), /* 8 bytes buffer size */ - USB_EP_BUFSIZE_16_gc = (0x01<<0), /* 16 bytes buffer size */ - USB_EP_BUFSIZE_32_gc = (0x02<<0), /* 32 bytes buffer size */ - USB_EP_BUFSIZE_64_gc = (0x03<<0), /* 64 bytes buffer size */ - USB_EP_BUFSIZE_128_gc = (0x04<<0), /* 128 bytes buffer size */ - USB_EP_BUFSIZE_256_gc = (0x05<<0), /* 256 bytes buffer size */ - USB_EP_BUFSIZE_512_gc = (0x06<<0), /* 512 bytes buffer size */ - USB_EP_BUFSIZE_1023_gc = (0x07<<0), /* 1023 bytes buffer size */ -} USB_EP_BUFSIZE_t; - - -/* --------------------------------------------------------------------------- -PORT - I/O Port Configuration --------------------------------------------------------------------------- -*/ - -/* I/O Ports */ -typedef struct PORT_struct -{ - register8_t DIR; /* I/O Port Data Direction */ - register8_t DIRSET; /* I/O Port Data Direction Set */ - register8_t DIRCLR; /* I/O Port Data Direction Clear */ - register8_t DIRTGL; /* I/O Port Data Direction Toggle */ - register8_t OUT; /* I/O Port Output */ - register8_t OUTSET; /* I/O Port Output Set */ - register8_t OUTCLR; /* I/O Port Output Clear */ - register8_t OUTTGL; /* I/O Port Output Toggle */ - register8_t IN; /* I/O port Input */ - register8_t INTCTRL; /* Interrupt Control Register */ - register8_t INT0MASK; /* Port Interrupt 0 Mask */ - register8_t INT1MASK; /* Port Interrupt 1 Mask */ - register8_t INTFLAGS; /* Interrupt Flag Register */ - register8_t reserved_0x0D; - register8_t REMAP; /* I/O Port Pin Remap Register */ - register8_t reserved_0x0F; - register8_t PIN0CTRL; /* Pin 0 Control Register */ - register8_t PIN1CTRL; /* Pin 1 Control Register */ - register8_t PIN2CTRL; /* Pin 2 Control Register */ - register8_t PIN3CTRL; /* Pin 3 Control Register */ - register8_t PIN4CTRL; /* Pin 4 Control Register */ - register8_t PIN5CTRL; /* Pin 5 Control Register */ - register8_t PIN6CTRL; /* Pin 6 Control Register */ - register8_t PIN7CTRL; /* Pin 7 Control Register */ -} PORT_t; - -/* Port Interrupt 0 Level */ -typedef enum PORT_INT0LVL_enum -{ - PORT_INT0LVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - PORT_INT0LVL_LO_gc = (0x01<<0), /* Low Level */ - PORT_INT0LVL_MED_gc = (0x02<<0), /* Medium Level */ - PORT_INT0LVL_HI_gc = (0x03<<0), /* High Level */ -} PORT_INT0LVL_t; - -/* Port Interrupt 1 Level */ -typedef enum PORT_INT1LVL_enum -{ - PORT_INT1LVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ - PORT_INT1LVL_LO_gc = (0x01<<2), /* Low Level */ - PORT_INT1LVL_MED_gc = (0x02<<2), /* Medium Level */ - PORT_INT1LVL_HI_gc = (0x03<<2), /* High Level */ -} PORT_INT1LVL_t; - -/* Output/Pull Configuration */ -typedef enum PORT_OPC_enum -{ - PORT_OPC_TOTEM_gc = (0x00<<3), /* Totempole */ - PORT_OPC_BUSKEEPER_gc = (0x01<<3), /* Totempole w/ Bus keeper on Input and Output */ - PORT_OPC_PULLDOWN_gc = (0x02<<3), /* Totempole w/ Pull-down on Input */ - PORT_OPC_PULLUP_gc = (0x03<<3), /* Totempole w/ Pull-up on Input */ - PORT_OPC_WIREDOR_gc = (0x04<<3), /* Wired OR */ - PORT_OPC_WIREDAND_gc = (0x05<<3), /* Wired AND */ - PORT_OPC_WIREDORPULL_gc = (0x06<<3), /* Wired OR w/ Pull-down */ - PORT_OPC_WIREDANDPULL_gc = (0x07<<3), /* Wired AND w/ Pull-up */ -} PORT_OPC_t; - -/* Input/Sense Configuration */ -typedef enum PORT_ISC_enum -{ - PORT_ISC_BOTHEDGES_gc = (0x00<<0), /* Sense Both Edges */ - PORT_ISC_RISING_gc = (0x01<<0), /* Sense Rising Edge */ - PORT_ISC_FALLING_gc = (0x02<<0), /* Sense Falling Edge */ - PORT_ISC_LEVEL_gc = (0x03<<0), /* Sense Level (Transparent For Events) */ - PORT_ISC_INPUT_DISABLE_gc = (0x07<<0), /* Disable Digital Input Buffer */ -} PORT_ISC_t; - - -/* --------------------------------------------------------------------------- -TC - 16-bit Timer/Counter With PWM --------------------------------------------------------------------------- -*/ - -/* 16-bit Timer/Counter 0 */ -typedef struct TC0_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t CTRLC; /* Control register C */ - register8_t CTRLD; /* Control Register D */ - register8_t CTRLE; /* Control Register E */ - register8_t reserved_0x05; - register8_t INTCTRLA; /* Interrupt Control Register A */ - register8_t INTCTRLB; /* Interrupt Control Register B */ - register8_t CTRLFCLR; /* Control Register F Clear */ - register8_t CTRLFSET; /* Control Register F Set */ - register8_t CTRLGCLR; /* Control Register G Clear */ - register8_t CTRLGSET; /* Control Register G Set */ - register8_t INTFLAGS; /* Interrupt Flag Register */ - register8_t reserved_0x0D; - register8_t reserved_0x0E; - register8_t TEMP; /* Temporary Register For 16-bit Access */ - register8_t reserved_0x10; - register8_t reserved_0x11; - register8_t reserved_0x12; - register8_t reserved_0x13; - register8_t reserved_0x14; - register8_t reserved_0x15; - register8_t reserved_0x16; - register8_t reserved_0x17; - register8_t reserved_0x18; - register8_t reserved_0x19; - register8_t reserved_0x1A; - register8_t reserved_0x1B; - register8_t reserved_0x1C; - register8_t reserved_0x1D; - register8_t reserved_0x1E; - register8_t reserved_0x1F; - _WORDREGISTER(CNT); /* Count */ - register8_t reserved_0x22; - register8_t reserved_0x23; - register8_t reserved_0x24; - register8_t reserved_0x25; - _WORDREGISTER(PER); /* Period */ - _WORDREGISTER(CCA); /* Compare or Capture A */ - _WORDREGISTER(CCB); /* Compare or Capture B */ - _WORDREGISTER(CCC); /* Compare or Capture C */ - _WORDREGISTER(CCD); /* Compare or Capture D */ - register8_t reserved_0x30; - register8_t reserved_0x31; - register8_t reserved_0x32; - register8_t reserved_0x33; - register8_t reserved_0x34; - register8_t reserved_0x35; - _WORDREGISTER(PERBUF); /* Period Buffer */ - _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ - _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ - _WORDREGISTER(CCCBUF); /* Compare Or Capture C Buffer */ - _WORDREGISTER(CCDBUF); /* Compare Or Capture D Buffer */ -} TC0_t; - - -/* 16-bit Timer/Counter 1 */ -typedef struct TC1_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t CTRLC; /* Control register C */ - register8_t CTRLD; /* Control Register D */ - register8_t CTRLE; /* Control Register E */ - register8_t reserved_0x05; - register8_t INTCTRLA; /* Interrupt Control Register A */ - register8_t INTCTRLB; /* Interrupt Control Register B */ - register8_t CTRLFCLR; /* Control Register F Clear */ - register8_t CTRLFSET; /* Control Register F Set */ - register8_t CTRLGCLR; /* Control Register G Clear */ - register8_t CTRLGSET; /* Control Register G Set */ - register8_t INTFLAGS; /* Interrupt Flag Register */ - register8_t reserved_0x0D; - register8_t reserved_0x0E; - register8_t TEMP; /* Temporary Register For 16-bit Access */ - register8_t reserved_0x10; - register8_t reserved_0x11; - register8_t reserved_0x12; - register8_t reserved_0x13; - register8_t reserved_0x14; - register8_t reserved_0x15; - register8_t reserved_0x16; - register8_t reserved_0x17; - register8_t reserved_0x18; - register8_t reserved_0x19; - register8_t reserved_0x1A; - register8_t reserved_0x1B; - register8_t reserved_0x1C; - register8_t reserved_0x1D; - register8_t reserved_0x1E; - register8_t reserved_0x1F; - _WORDREGISTER(CNT); /* Count */ - register8_t reserved_0x22; - register8_t reserved_0x23; - register8_t reserved_0x24; - register8_t reserved_0x25; - _WORDREGISTER(PER); /* Period */ - _WORDREGISTER(CCA); /* Compare or Capture A */ - _WORDREGISTER(CCB); /* Compare or Capture B */ - register8_t reserved_0x2C; - register8_t reserved_0x2D; - register8_t reserved_0x2E; - register8_t reserved_0x2F; - register8_t reserved_0x30; - register8_t reserved_0x31; - register8_t reserved_0x32; - register8_t reserved_0x33; - register8_t reserved_0x34; - register8_t reserved_0x35; - _WORDREGISTER(PERBUF); /* Period Buffer */ - _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ - _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ -} TC1_t; - -/* Clock Selection */ -typedef enum TC_CLKSEL_enum -{ - TC_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */ - TC_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */ - TC_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */ - TC_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */ - TC_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */ - TC_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */ - TC_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */ - TC_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */ - TC_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */ - TC_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */ - TC_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */ - TC_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */ - TC_CLKSEL_EVCH4_gc = (0x0C<<0), /* Event Channel 4 */ - TC_CLKSEL_EVCH5_gc = (0x0D<<0), /* Event Channel 5 */ - TC_CLKSEL_EVCH6_gc = (0x0E<<0), /* Event Channel 6 */ - TC_CLKSEL_EVCH7_gc = (0x0F<<0), /* Event Channel 7 */ -} TC_CLKSEL_t; - -/* Waveform Generation Mode */ -typedef enum TC_WGMODE_enum -{ - TC_WGMODE_NORMAL_gc = (0x00<<0), /* Normal Mode */ - TC_WGMODE_FRQ_gc = (0x01<<0), /* Frequency Generation Mode */ - TC_WGMODE_SINGLESLOPE_gc = (0x03<<0), /* Single Slope */ - TC_WGMODE_SS_gc = (0x03<<0), /* Single Slope */ - TC_WGMODE_DSTOP_gc = (0x05<<0), /* Dual Slope, Update on TOP */ - TC_WGMODE_DS_T_gc = (0x05<<0), /* Dual Slope, Update on TOP */ - TC_WGMODE_DSBOTH_gc = (0x06<<0), /* Dual Slope, Update on both TOP and BOTTOM */ - TC_WGMODE_DS_TB_gc = (0x06<<0), /* Dual Slope, Update on both TOP and BOTTOM */ - TC_WGMODE_DSBOTTOM_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */ - TC_WGMODE_DS_B_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */ -} TC_WGMODE_t; - -/* Byte Mode */ -typedef enum TC_BYTEM_enum -{ - TC_BYTEM_NORMAL_gc = (0x00<<0), /* 16-bit mode */ - TC_BYTEM_BYTEMODE_gc = (0x01<<0), /* Timer/Counter operating in byte mode only */ - TC_BYTEM_SPLITMODE_gc = (0x02<<0), /* Timer/Counter split into two 8-bit Counters (TC2) */ -} TC_BYTEM_t; - -/* Event Action */ -typedef enum TC_EVACT_enum -{ - TC_EVACT_OFF_gc = (0x00<<5), /* No Event Action */ - TC_EVACT_CAPT_gc = (0x01<<5), /* Input Capture */ - TC_EVACT_UPDOWN_gc = (0x02<<5), /* Externally Controlled Up/Down Count */ - TC_EVACT_QDEC_gc = (0x03<<5), /* Quadrature Decode */ - TC_EVACT_RESTART_gc = (0x04<<5), /* Restart */ - TC_EVACT_FRQ_gc = (0x05<<5), /* Frequency Capture */ - TC_EVACT_PW_gc = (0x06<<5), /* Pulse-width Capture */ -} TC_EVACT_t; - -/* Event Selection */ -typedef enum TC_EVSEL_enum -{ - TC_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ - TC_EVSEL_CH0_gc = (0x08<<0), /* Event Channel 0 */ - TC_EVSEL_CH1_gc = (0x09<<0), /* Event Channel 1 */ - TC_EVSEL_CH2_gc = (0x0A<<0), /* Event Channel 2 */ - TC_EVSEL_CH3_gc = (0x0B<<0), /* Event Channel 3 */ - TC_EVSEL_CH4_gc = (0x0C<<0), /* Event Channel 4 */ - TC_EVSEL_CH5_gc = (0x0D<<0), /* Event Channel 5 */ - TC_EVSEL_CH6_gc = (0x0E<<0), /* Event Channel 6 */ - TC_EVSEL_CH7_gc = (0x0F<<0), /* Event Channel 7 */ -} TC_EVSEL_t; - -/* Error Interrupt Level */ -typedef enum TC_ERRINTLVL_enum -{ - TC_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ - TC_ERRINTLVL_LO_gc = (0x01<<2), /* Low Level */ - TC_ERRINTLVL_MED_gc = (0x02<<2), /* Medium Level */ - TC_ERRINTLVL_HI_gc = (0x03<<2), /* High Level */ -} TC_ERRINTLVL_t; - -/* Overflow Interrupt Level */ -typedef enum TC_OVFINTLVL_enum -{ - TC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - TC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ - TC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ - TC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ -} TC_OVFINTLVL_t; - -/* Compare or Capture D Interrupt Level */ -typedef enum TC_CCDINTLVL_enum -{ - TC_CCDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ - TC_CCDINTLVL_LO_gc = (0x01<<6), /* Low Level */ - TC_CCDINTLVL_MED_gc = (0x02<<6), /* Medium Level */ - TC_CCDINTLVL_HI_gc = (0x03<<6), /* High Level */ -} TC_CCDINTLVL_t; - -/* Compare or Capture C Interrupt Level */ -typedef enum TC_CCCINTLVL_enum -{ - TC_CCCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ - TC_CCCINTLVL_LO_gc = (0x01<<4), /* Low Level */ - TC_CCCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ - TC_CCCINTLVL_HI_gc = (0x03<<4), /* High Level */ -} TC_CCCINTLVL_t; - -/* Compare or Capture B Interrupt Level */ -typedef enum TC_CCBINTLVL_enum -{ - TC_CCBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ - TC_CCBINTLVL_LO_gc = (0x01<<2), /* Low Level */ - TC_CCBINTLVL_MED_gc = (0x02<<2), /* Medium Level */ - TC_CCBINTLVL_HI_gc = (0x03<<2), /* High Level */ -} TC_CCBINTLVL_t; - -/* Compare or Capture A Interrupt Level */ -typedef enum TC_CCAINTLVL_enum -{ - TC_CCAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - TC_CCAINTLVL_LO_gc = (0x01<<0), /* Low Level */ - TC_CCAINTLVL_MED_gc = (0x02<<0), /* Medium Level */ - TC_CCAINTLVL_HI_gc = (0x03<<0), /* High Level */ -} TC_CCAINTLVL_t; - -/* Timer/Counter Command */ -typedef enum TC_CMD_enum -{ - TC_CMD_NONE_gc = (0x00<<2), /* No Command */ - TC_CMD_UPDATE_gc = (0x01<<2), /* Force Update */ - TC_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ - TC_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ -} TC_CMD_t; - - -/* --------------------------------------------------------------------------- -TC2 - 16-bit Timer/Counter type 2 --------------------------------------------------------------------------- -*/ - -/* 16-bit Timer/Counter type 2 */ -typedef struct TC2_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t CTRLC; /* Control register C */ - register8_t reserved_0x03; - register8_t CTRLE; /* Control Register E */ - register8_t reserved_0x05; - register8_t INTCTRLA; /* Interrupt Control Register A */ - register8_t INTCTRLB; /* Interrupt Control Register B */ - register8_t reserved_0x08; - register8_t CTRLF; /* Control Register F */ - register8_t reserved_0x0A; - register8_t reserved_0x0B; - register8_t INTFLAGS; /* Interrupt Flag Register */ - register8_t reserved_0x0D; - register8_t reserved_0x0E; - register8_t reserved_0x0F; - register8_t reserved_0x10; - register8_t reserved_0x11; - register8_t reserved_0x12; - register8_t reserved_0x13; - register8_t reserved_0x14; - register8_t reserved_0x15; - register8_t reserved_0x16; - register8_t reserved_0x17; - register8_t reserved_0x18; - register8_t reserved_0x19; - register8_t reserved_0x1A; - register8_t reserved_0x1B; - register8_t reserved_0x1C; - register8_t reserved_0x1D; - register8_t reserved_0x1E; - register8_t reserved_0x1F; - register8_t LCNT; /* Low Byte Count */ - register8_t HCNT; /* High Byte Count */ - register8_t reserved_0x22; - register8_t reserved_0x23; - register8_t reserved_0x24; - register8_t reserved_0x25; - register8_t LPER; /* Low Byte Period */ - register8_t HPER; /* High Byte Period */ - register8_t LCMPA; /* Low Byte Compare A */ - register8_t HCMPA; /* High Byte Compare A */ - register8_t LCMPB; /* Low Byte Compare B */ - register8_t HCMPB; /* High Byte Compare B */ - register8_t LCMPC; /* Low Byte Compare C */ - register8_t HCMPC; /* High Byte Compare C */ - register8_t LCMPD; /* Low Byte Compare D */ - register8_t HCMPD; /* High Byte Compare D */ -} TC2_t; - -/* Clock Selection */ -typedef enum TC2_CLKSEL_enum -{ - TC2_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */ - TC2_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */ - TC2_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */ - TC2_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */ - TC2_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */ - TC2_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */ - TC2_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */ - TC2_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */ - TC2_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */ - TC2_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */ - TC2_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */ - TC2_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */ - TC2_CLKSEL_EVCH4_gc = (0x0C<<0), /* Event Channel 4 */ - TC2_CLKSEL_EVCH5_gc = (0x0D<<0), /* Event Channel 5 */ - TC2_CLKSEL_EVCH6_gc = (0x0E<<0), /* Event Channel 6 */ - TC2_CLKSEL_EVCH7_gc = (0x0F<<0), /* Event Channel 7 */ -} TC2_CLKSEL_t; - -/* Byte Mode */ -typedef enum TC2_BYTEM_enum -{ - TC2_BYTEM_NORMAL_gc = (0x00<<0), /* 16-bit mode */ - TC2_BYTEM_BYTEMODE_gc = (0x01<<0), /* Timer/Counter operating in byte mode only (TC2) */ - TC2_BYTEM_SPLITMODE_gc = (0x02<<0), /* Timer/Counter split into two 8-bit Counters */ -} TC2_BYTEM_t; - -/* High Byte Underflow Interrupt Level */ -typedef enum TC2_HUNFINTLVL_enum -{ - TC2_HUNFINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ - TC2_HUNFINTLVL_LO_gc = (0x01<<2), /* Low Level */ - TC2_HUNFINTLVL_MED_gc = (0x02<<2), /* Medium Level */ - TC2_HUNFINTLVL_HI_gc = (0x03<<2), /* High Level */ -} TC2_HUNFINTLVL_t; - -/* Low Byte Underflow Interrupt Level */ -typedef enum TC2_LUNFINTLVL_enum -{ - TC2_LUNFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - TC2_LUNFINTLVL_LO_gc = (0x01<<0), /* Low Level */ - TC2_LUNFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ - TC2_LUNFINTLVL_HI_gc = (0x03<<0), /* High Level */ -} TC2_LUNFINTLVL_t; - -/* Low Byte Compare D Interrupt Level */ -typedef enum TC2_LCMPDINTLVL_enum -{ - TC2_LCMPDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ - TC2_LCMPDINTLVL_LO_gc = (0x01<<6), /* Low Level */ - TC2_LCMPDINTLVL_MED_gc = (0x02<<6), /* Medium Level */ - TC2_LCMPDINTLVL_HI_gc = (0x03<<6), /* High Level */ -} TC2_LCMPDINTLVL_t; - -/* Low Byte Compare C Interrupt Level */ -typedef enum TC2_LCMPCINTLVL_enum -{ - TC2_LCMPCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ - TC2_LCMPCINTLVL_LO_gc = (0x01<<4), /* Low Level */ - TC2_LCMPCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ - TC2_LCMPCINTLVL_HI_gc = (0x03<<4), /* High Level */ -} TC2_LCMPCINTLVL_t; - -/* Low Byte Compare B Interrupt Level */ -typedef enum TC2_LCMPBINTLVL_enum -{ - TC2_LCMPBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ - TC2_LCMPBINTLVL_LO_gc = (0x01<<2), /* Low Level */ - TC2_LCMPBINTLVL_MED_gc = (0x02<<2), /* Medium Level */ - TC2_LCMPBINTLVL_HI_gc = (0x03<<2), /* High Level */ -} TC2_LCMPBINTLVL_t; - -/* Low Byte Compare A Interrupt Level */ -typedef enum TC2_LCMPAINTLVL_enum -{ - TC2_LCMPAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - TC2_LCMPAINTLVL_LO_gc = (0x01<<0), /* Low Level */ - TC2_LCMPAINTLVL_MED_gc = (0x02<<0), /* Medium Level */ - TC2_LCMPAINTLVL_HI_gc = (0x03<<0), /* High Level */ -} TC2_LCMPAINTLVL_t; - -/* Timer/Counter Command */ -typedef enum TC2_CMD_enum -{ - TC2_CMD_NONE_gc = (0x00<<2), /* No Command */ - TC2_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ - TC2_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ -} TC2_CMD_t; - -/* Timer/Counter Command */ -typedef enum TC2_CMDEN_enum -{ - TC2_CMDEN_LOW_gc = (0x01<<0), /* Low Byte Timer/Counter */ - TC2_CMDEN_HIGH_gc = (0x02<<0), /* High Byte Timer/Counter */ - TC2_CMDEN_BOTH_gc = (0x03<<0), /* Both Low Byte and High Byte Timer/Counters */ -} TC2_CMDEN_t; - - -/* --------------------------------------------------------------------------- -AWEX - Timer/Counter Advanced Waveform Extension --------------------------------------------------------------------------- -*/ - -/* Advanced Waveform Extension */ -typedef struct AWEX_struct -{ - register8_t CTRL; /* Control Register */ - register8_t reserved_0x01; - register8_t FDEMASK; /* Fault Detection Event Mask */ - register8_t FDCTRL; /* Fault Detection Control Register */ - register8_t STATUS; /* Status Register */ - register8_t STATUSSET; /* Status Set Register */ - register8_t DTBOTH; /* Dead Time Both Sides */ - register8_t DTBOTHBUF; /* Dead Time Both Sides Buffer */ - register8_t DTLS; /* Dead Time Low Side */ - register8_t DTHS; /* Dead Time High Side */ - register8_t DTLSBUF; /* Dead Time Low Side Buffer */ - register8_t DTHSBUF; /* Dead Time High Side Buffer */ - register8_t OUTOVEN; /* Output Override Enable */ -} AWEX_t; - -/* Fault Detect Action */ -typedef enum AWEX_FDACT_enum -{ - AWEX_FDACT_NONE_gc = (0x00<<0), /* No Fault Protection */ - AWEX_FDACT_CLEAROE_gc = (0x01<<0), /* Clear Output Enable Bits */ - AWEX_FDACT_CLEARDIR_gc = (0x03<<0), /* Clear I/O Port Direction Bits */ -} AWEX_FDACT_t; - - -/* --------------------------------------------------------------------------- -HIRES - Timer/Counter High-Resolution Extension --------------------------------------------------------------------------- -*/ - -/* High-Resolution Extension */ -typedef struct HIRES_struct -{ - register8_t CTRLA; /* Control Register */ -} HIRES_t; - -/* High Resolution Enable */ -typedef enum HIRES_HREN_enum -{ - HIRES_HREN_NONE_gc = (0x00<<0), /* No Fault Protection */ - HIRES_HREN_TC0_gc = (0x01<<0), /* Enable High Resolution on Timer/Counter 0 */ - HIRES_HREN_TC1_gc = (0x02<<0), /* Enable High Resolution on Timer/Counter 1 */ - HIRES_HREN_BOTH_gc = (0x03<<0), /* Enable High Resolution both Timer/Counters */ -} HIRES_HREN_t; - - -/* --------------------------------------------------------------------------- -USART - Universal Asynchronous Receiver-Transmitter --------------------------------------------------------------------------- -*/ - -/* Universal Synchronous/Asynchronous Receiver/Transmitter */ -typedef struct USART_struct -{ - register8_t DATA; /* Data Register */ - register8_t STATUS; /* Status Register */ - register8_t reserved_0x02; - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t CTRLC; /* Control Register C */ - register8_t BAUDCTRLA; /* Baud Rate Control Register A */ - register8_t BAUDCTRLB; /* Baud Rate Control Register B */ -} USART_t; - -/* Receive Complete Interrupt level */ -typedef enum USART_RXCINTLVL_enum -{ - USART_RXCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ - USART_RXCINTLVL_LO_gc = (0x01<<4), /* Low Level */ - USART_RXCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ - USART_RXCINTLVL_HI_gc = (0x03<<4), /* High Level */ -} USART_RXCINTLVL_t; - -/* Transmit Complete Interrupt level */ -typedef enum USART_TXCINTLVL_enum -{ - USART_TXCINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ - USART_TXCINTLVL_LO_gc = (0x01<<2), /* Low Level */ - USART_TXCINTLVL_MED_gc = (0x02<<2), /* Medium Level */ - USART_TXCINTLVL_HI_gc = (0x03<<2), /* High Level */ -} USART_TXCINTLVL_t; - -/* Data Register Empty Interrupt level */ -typedef enum USART_DREINTLVL_enum -{ - USART_DREINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - USART_DREINTLVL_LO_gc = (0x01<<0), /* Low Level */ - USART_DREINTLVL_MED_gc = (0x02<<0), /* Medium Level */ - USART_DREINTLVL_HI_gc = (0x03<<0), /* High Level */ -} USART_DREINTLVL_t; - -/* Character Size */ -typedef enum USART_CHSIZE_enum -{ - USART_CHSIZE_5BIT_gc = (0x00<<0), /* Character size: 5 bit */ - USART_CHSIZE_6BIT_gc = (0x01<<0), /* Character size: 6 bit */ - USART_CHSIZE_7BIT_gc = (0x02<<0), /* Character size: 7 bit */ - USART_CHSIZE_8BIT_gc = (0x03<<0), /* Character size: 8 bit */ - USART_CHSIZE_9BIT_gc = (0x07<<0), /* Character size: 9 bit */ -} USART_CHSIZE_t; - -/* Communication Mode */ -typedef enum USART_CMODE_enum -{ - USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6), /* Asynchronous Mode */ - USART_CMODE_SYNCHRONOUS_gc = (0x01<<6), /* Synchronous Mode */ - USART_CMODE_IRDA_gc = (0x02<<6), /* IrDA Mode */ - USART_CMODE_MSPI_gc = (0x03<<6), /* Master SPI Mode */ -} USART_CMODE_t; - -/* Parity Mode */ -typedef enum USART_PMODE_enum -{ - USART_PMODE_DISABLED_gc = (0x00<<4), /* No Parity */ - USART_PMODE_EVEN_gc = (0x02<<4), /* Even Parity */ - USART_PMODE_ODD_gc = (0x03<<4), /* Odd Parity */ -} USART_PMODE_t; - - -/* --------------------------------------------------------------------------- -SPI - Serial Peripheral Interface --------------------------------------------------------------------------- -*/ - -/* Serial Peripheral Interface */ -typedef struct SPI_struct -{ - register8_t CTRL; /* Control Register */ - register8_t INTCTRL; /* Interrupt Control Register */ - register8_t STATUS; /* Status Register */ - register8_t DATA; /* Data Register */ -} SPI_t; - -/* SPI Mode */ -typedef enum SPI_MODE_enum -{ - SPI_MODE_0_gc = (0x00<<2), /* SPI Mode 0 */ - SPI_MODE_1_gc = (0x01<<2), /* SPI Mode 1 */ - SPI_MODE_2_gc = (0x02<<2), /* SPI Mode 2 */ - SPI_MODE_3_gc = (0x03<<2), /* SPI Mode 3 */ -} SPI_MODE_t; - -/* Prescaler setting */ -typedef enum SPI_PRESCALER_enum -{ - SPI_PRESCALER_DIV4_gc = (0x00<<0), /* System Clock / 4 */ - SPI_PRESCALER_DIV16_gc = (0x01<<0), /* System Clock / 16 */ - SPI_PRESCALER_DIV64_gc = (0x02<<0), /* System Clock / 64 */ - SPI_PRESCALER_DIV128_gc = (0x03<<0), /* System Clock / 128 */ -} SPI_PRESCALER_t; - -/* Interrupt level */ -typedef enum SPI_INTLVL_enum -{ - SPI_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - SPI_INTLVL_LO_gc = (0x01<<0), /* Low Level */ - SPI_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ - SPI_INTLVL_HI_gc = (0x03<<0), /* High Level */ -} SPI_INTLVL_t; - - -/* --------------------------------------------------------------------------- -IRCOM - IR Communication Module --------------------------------------------------------------------------- -*/ - -/* IR Communication Module */ -typedef struct IRCOM_struct -{ - register8_t CTRL; /* Control Register */ - register8_t TXPLCTRL; /* IrDA Transmitter Pulse Length Control Register */ - register8_t RXPLCTRL; /* IrDA Receiver Pulse Length Control Register */ -} IRCOM_t; - -/* Event channel selection */ -typedef enum IRDA_EVSEL_enum -{ - IRDA_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ - IRDA_EVSEL_0_gc = (0x08<<0), /* Event Channel 0 */ - IRDA_EVSEL_1_gc = (0x09<<0), /* Event Channel 1 */ - IRDA_EVSEL_2_gc = (0x0A<<0), /* Event Channel 2 */ - IRDA_EVSEL_3_gc = (0x0B<<0), /* Event Channel 3 */ - IRDA_EVSEL_4_gc = (0x0C<<0), /* Event Channel 4 */ - IRDA_EVSEL_5_gc = (0x0D<<0), /* Event Channel 5 */ - IRDA_EVSEL_6_gc = (0x0E<<0), /* Event Channel 6 */ - IRDA_EVSEL_7_gc = (0x0F<<0), /* Event Channel 7 */ -} IRDA_EVSEL_t; - - -/* --------------------------------------------------------------------------- -FUSE - Fuses and Lockbits --------------------------------------------------------------------------- -*/ - -/* Fuses */ -typedef struct NVM_FUSES_struct -{ - register8_t FUSEBYTE0; /* JTAG User ID */ - register8_t FUSEBYTE1; /* Watchdog Configuration */ - register8_t FUSEBYTE2; /* Reset Configuration */ - register8_t reserved_0x03; - register8_t FUSEBYTE4; /* Start-up Configuration */ - register8_t FUSEBYTE5; /* EESAVE and BOD Level */ -} NVM_FUSES_t; - -/* Boot Loader Section Reset Vector */ -typedef enum BOOTRST_enum -{ - BOOTRST_BOOTLDR_gc = (0x00<<6), /* Boot Loader Reset */ - BOOTRST_APPLICATION_gc = (0x01<<6), /* Application Reset */ -} BOOTRST_t; - -/* Timer Oscillator pin location */ -typedef enum TOSCSEL_enum -{ - TOSCSEL_ALTERNATE_gc = (0x00<<5), /* TOSC1 / TOSC2 on separate pins */ - TOSCSEL_XTAL_gc = (0x01<<5), /* TOSC1 / TOSC2 shared with XTAL1 / XTAL2 */ -} TOSCSEL_t; - -/* BOD operation */ -typedef enum BOD_enum -{ - BOD_SAMPLED_gc = (0x01<<0), /* BOD enabled in sampled mode */ - BOD_CONTINUOUS_gc = (0x02<<0), /* BOD enabled continuously */ - BOD_DISABLED_gc = (0x03<<0), /* BOD Disabled */ -} BOD_t; - -/* BOD operation */ -typedef enum BODACT_enum -{ - BODACT_SAMPLED_gc = (0x01<<4), /* BOD enabled in sampled mode */ - BODACT_CONTINUOUS_gc = (0x02<<4), /* BOD enabled continuously */ - BODACT_DISABLED_gc = (0x03<<4), /* BOD Disabled */ -} BODACT_t; - -/* Watchdog (Window) Timeout Period */ -typedef enum WD_enum -{ - WD_8CLK_gc = (0x00<<4), /* 8 cycles (8ms @ 3.3V) */ - WD_16CLK_gc = (0x01<<4), /* 16 cycles (16ms @ 3.3V) */ - WD_32CLK_gc = (0x02<<4), /* 32 cycles (32ms @ 3.3V) */ - WD_64CLK_gc = (0x03<<4), /* 64 cycles (64ms @ 3.3V) */ - WD_128CLK_gc = (0x04<<4), /* 128 cycles (0.125s @ 3.3V) */ - WD_256CLK_gc = (0x05<<4), /* 256 cycles (0.25s @ 3.3V) */ - WD_512CLK_gc = (0x06<<4), /* 512 cycles (0.5s @ 3.3V) */ - WD_1KCLK_gc = (0x07<<4), /* 1K cycles (1s @ 3.3V) */ - WD_2KCLK_gc = (0x08<<4), /* 2K cycles (2s @ 3.3V) */ - WD_4KCLK_gc = (0x09<<4), /* 4K cycles (4s @ 3.3V) */ - WD_8KCLK_gc = (0x0A<<4), /* 8K cycles (8s @ 3.3V) */ -} WD_t; - -/* Watchdog (Window) Timeout Period */ -typedef enum WDP_enum -{ - WDP_8CLK_gc = (0x00<<0), /* 8 cycles (8ms @ 3.3V) */ - WDP_16CLK_gc = (0x01<<0), /* 16 cycles (16ms @ 3.3V) */ - WDP_32CLK_gc = (0x02<<0), /* 32 cycles (32ms @ 3.3V) */ - WDP_64CLK_gc = (0x03<<0), /* 64 cycles (64ms @ 3.3V) */ - WDP_128CLK_gc = (0x04<<0), /* 128 cycles (0.125s @ 3.3V) */ - WDP_256CLK_gc = (0x05<<0), /* 256 cycles (0.25s @ 3.3V) */ - WDP_512CLK_gc = (0x06<<0), /* 512 cycles (0.5s @ 3.3V) */ - WDP_1KCLK_gc = (0x07<<0), /* 1K cycles (1s @ 3.3V) */ - WDP_2KCLK_gc = (0x08<<0), /* 2K cycles (2s @ 3.3V) */ - WDP_4KCLK_gc = (0x09<<0), /* 4K cycles (4s @ 3.3V) */ - WDP_8KCLK_gc = (0x0A<<0), /* 8K cycles (8s @ 3.3V) */ -} WDP_t; - -/* Start-up Time */ -typedef enum SUT_enum -{ - SUT_0MS_gc = (0x03<<2), /* 0 ms */ - SUT_4MS_gc = (0x01<<2), /* 4 ms */ - SUT_64MS_gc = (0x00<<2), /* 64 ms */ -} SUT_t; - -/* Brownout Detection Voltage Level */ -typedef enum BODLVL_enum -{ - BODLVL_1V6_gc = (0x07<<0), /* 1.6 V */ - BODLVL_1V8_gc = (0x06<<0), /* 1.8 V */ - BODLVL_2V0_gc = (0x05<<0), /* 2.0 V */ - BODLVL_2V2_gc = (0x04<<0), /* 2.2 V */ - BODLVL_2V4_gc = (0x03<<0), /* 2.4 V */ - BODLVL_2V6_gc = (0x02<<0), /* 2.6 V */ - BODLVL_2V8_gc = (0x01<<0), /* 2.8 V */ - BODLVL_3V0_gc = (0x00<<0), /* 3.0 V */ -} BODLVL_t; - - -/* --------------------------------------------------------------------------- -LOCKBIT - Fuses and Lockbits --------------------------------------------------------------------------- -*/ - -/* Lock Bits */ -typedef struct NVM_LOCKBITS_struct -{ - register8_t LOCK_BITS; /* Lock Bits (Changed from LOCKBITS to avoid avr-libc collision) */ -} NVM_LOCKBITS_t; - -/* Boot lock bits - boot setcion */ -typedef enum FUSE_BLBB_enum -{ - FUSE_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ - FUSE_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ - FUSE_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ - FUSE_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ -} FUSE_BLBB_t; - -/* Boot lock bits - application section */ -typedef enum FUSE_BLBA_enum -{ - FUSE_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ - FUSE_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ - FUSE_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ - FUSE_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ -} FUSE_BLBA_t; - -/* Boot lock bits - application table section */ -typedef enum FUSE_BLBAT_enum -{ - FUSE_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ - FUSE_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ - FUSE_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ - FUSE_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ -} FUSE_BLBAT_t; - -/* Lock bits */ -typedef enum FUSE_LB_enum -{ - FUSE_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ - FUSE_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ - FUSE_LB_NOLOCK_gc = (0x03<<0), /* No locks */ -} FUSE_LB_t; - - -/* --------------------------------------------------------------------------- -SIGROW - Signature Row --------------------------------------------------------------------------- -*/ - -/* Production Signatures */ -typedef struct NVM_PROD_SIGNATURES_struct -{ - register8_t RCOSC2M; /* RCOSC 2 MHz Calibration Value B */ - register8_t RCOSC2MA; /* RCOSC 2 MHz Calibration Value A */ - register8_t RCOSC32K; /* RCOSC 32.768 kHz Calibration Value */ - register8_t RCOSC32M; /* RCOSC 32 MHz Calibration Value B */ - register8_t RCOSC32MA; /* RCOSC 32 MHz Calibration Value A */ - register8_t reserved_0x05; - register8_t reserved_0x06; - register8_t reserved_0x07; - register8_t LOTNUM0; /* Lot Number Byte 0, ASCII */ - register8_t LOTNUM1; /* Lot Number Byte 1, ASCII */ - register8_t LOTNUM2; /* Lot Number Byte 2, ASCII */ - register8_t LOTNUM3; /* Lot Number Byte 3, ASCII */ - register8_t LOTNUM4; /* Lot Number Byte 4, ASCII */ - register8_t LOTNUM5; /* Lot Number Byte 5, ASCII */ - register8_t reserved_0x0E; - register8_t reserved_0x0F; - register8_t WAFNUM; /* Wafer Number */ - register8_t reserved_0x11; - register8_t COORDX0; /* Wafer Coordinate X Byte 0 */ - register8_t COORDX1; /* Wafer Coordinate X Byte 1 */ - register8_t COORDY0; /* Wafer Coordinate Y Byte 0 */ - register8_t COORDY1; /* Wafer Coordinate Y Byte 1 */ - register8_t reserved_0x16; - register8_t reserved_0x17; - register8_t reserved_0x18; - register8_t reserved_0x19; - register8_t USBCAL0; /* USB Calibration Byte 0 */ - register8_t USBCAL1; /* USB Calibration Byte 1 */ - register8_t USBRCOSC; /* USB RCOSC Calibration Value B */ - register8_t USBRCOSCA; /* USB RCOSC Calibration Value A */ - register8_t reserved_0x1E; - register8_t reserved_0x1F; - register8_t ADCACAL0; /* ADCA Calibration Byte 0 */ - register8_t ADCACAL1; /* ADCA Calibration Byte 1 */ - register8_t reserved_0x22; - register8_t reserved_0x23; - register8_t ADCBCAL0; /* ADCB Calibration Byte 0 */ - register8_t ADCBCAL1; /* ADCB Calibration Byte 1 */ - register8_t reserved_0x26; - register8_t reserved_0x27; - register8_t reserved_0x28; - register8_t reserved_0x29; - register8_t reserved_0x2A; - register8_t reserved_0x2B; - register8_t reserved_0x2C; - register8_t reserved_0x2D; - register8_t TEMPSENSE0; /* Temperature Sensor Calibration Byte 0 */ - register8_t TEMPSENSE1; /* Temperature Sensor Calibration Byte 1 */ - register8_t DACA0OFFCAL; /* DACA0 Calibration Byte 0 */ - register8_t DACA0GAINCAL; /* DACA0 Calibration Byte 1 */ - register8_t DACB0OFFCAL; /* DACB0 Calibration Byte 0 */ - register8_t DACB0GAINCAL; /* DACB0 Calibration Byte 1 */ - register8_t DACA1OFFCAL; /* DACA1 Calibration Byte 0 */ - register8_t DACA1GAINCAL; /* DACA1 Calibration Byte 1 */ - register8_t DACB1OFFCAL; /* DACB1 Calibration Byte 0 */ - register8_t DACB1GAINCAL; /* DACB1 Calibration Byte 1 */ - register8_t reserved_0x38; - register8_t reserved_0x39; - register8_t reserved_0x3A; - register8_t reserved_0x3B; - register8_t reserved_0x3C; - register8_t reserved_0x3D; - register8_t reserved_0x3E; - register8_t reserved_0x3F; - register8_t reserved_0x40; - register8_t reserved_0x41; - register8_t reserved_0x42; - register8_t reserved_0x43; - register8_t reserved_0x44; - register8_t reserved_0x45; - register8_t reserved_0x46; - register8_t reserved_0x47; -} NVM_PROD_SIGNATURES_t; - -/* -========================================================================== -IO Module Instances. Mapped to memory. -========================================================================== -*/ - -#define VPORT0 (*(VPORT_t *) 0x0010) /* Virtual Port */ -#define VPORT1 (*(VPORT_t *) 0x0014) /* Virtual Port */ -#define VPORT2 (*(VPORT_t *) 0x0018) /* Virtual Port */ -#define VPORT3 (*(VPORT_t *) 0x001C) /* Virtual Port */ -#define OCD (*(OCD_t *) 0x002E) /* On-Chip Debug System */ -#define CLK (*(CLK_t *) 0x0040) /* Clock System */ -#define SLEEP (*(SLEEP_t *) 0x0048) /* Sleep Controller */ -#define OSC (*(OSC_t *) 0x0050) /* Oscillator */ -#define DFLLRC32M (*(DFLL_t *) 0x0060) /* DFLL */ -#define DFLLRC2M (*(DFLL_t *) 0x0068) /* DFLL */ -#define PR (*(PR_t *) 0x0070) /* Power Reduction */ -#define RST (*(RST_t *) 0x0078) /* Reset */ -#define WDT (*(WDT_t *) 0x0080) /* Watch-Dog Timer */ -#define MCU (*(MCU_t *) 0x0090) /* MCU Control */ -#define PMIC (*(PMIC_t *) 0x00A0) /* Programmable Multi-level Interrupt Controller */ -#define PORTCFG (*(PORTCFG_t *) 0x00B0) /* I/O port Configuration */ -#define AES (*(AES_t *) 0x00C0) /* AES Module */ -#define CRC (*(CRC_t *) 0x00D0) /* Cyclic Redundancy Checker */ -#define DMA (*(DMA_t *) 0x0100) /* DMA Controller */ -#define EVSYS (*(EVSYS_t *) 0x0180) /* Event System */ -#define NVM (*(NVM_t *) 0x01C0) /* Non-volatile Memory Controller */ -#define ADCA (*(ADC_t *) 0x0200) /* Analog-to-Digital Converter */ -#define ADCB (*(ADC_t *) 0x0240) /* Analog-to-Digital Converter */ -#define DACB (*(DAC_t *) 0x0320) /* Digital-to-Analog Converter */ -#define ACA (*(AC_t *) 0x0380) /* Analog Comparator */ -#define ACB (*(AC_t *) 0x0390) /* Analog Comparator */ -#define RTC (*(RTC_t *) 0x0400) /* Real-Time Counter */ -#define TWIC (*(TWI_t *) 0x0480) /* Two-Wire Interface */ -#define TWIE (*(TWI_t *) 0x04A0) /* Two-Wire Interface */ -#define USB (*(USB_t *) 0x04C0) /* Universal Serial Bus */ -#define PORTA (*(PORT_t *) 0x0600) /* I/O Ports */ -#define PORTB (*(PORT_t *) 0x0620) /* I/O Ports */ -#define PORTC (*(PORT_t *) 0x0640) /* I/O Ports */ -#define PORTD (*(PORT_t *) 0x0660) /* I/O Ports */ -#define PORTE (*(PORT_t *) 0x0680) /* I/O Ports */ -#define PORTF (*(PORT_t *) 0x06A0) /* I/O Ports */ -#define PORTR (*(PORT_t *) 0x07E0) /* I/O Ports */ -#define TCC0 (*(TC0_t *) 0x0800) /* 16-bit Timer/Counter 0 */ -#define TCC2 (*(TC2_t *) 0x0800) /* 16-bit Timer/Counter type 2 */ -#define TCC1 (*(TC1_t *) 0x0840) /* 16-bit Timer/Counter 1 */ -#define AWEXC (*(AWEX_t *) 0x0880) /* Advanced Waveform Extension */ -#define HIRESC (*(HIRES_t *) 0x0890) /* High-Resolution Extension */ -#define USARTC0 (*(USART_t *) 0x08A0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ -#define USARTC1 (*(USART_t *) 0x08B0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ -#define SPIC (*(SPI_t *) 0x08C0) /* Serial Peripheral Interface */ -#define IRCOM (*(IRCOM_t *) 0x08F8) /* IR Communication Module */ -#define TCD0 (*(TC0_t *) 0x0900) /* 16-bit Timer/Counter 0 */ -#define TCD2 (*(TC2_t *) 0x0900) /* 16-bit Timer/Counter type 2 */ -#define TCD1 (*(TC1_t *) 0x0940) /* 16-bit Timer/Counter 1 */ -#define HIRESD (*(HIRES_t *) 0x0990) /* High-Resolution Extension */ -#define USARTD0 (*(USART_t *) 0x09A0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ -#define USARTD1 (*(USART_t *) 0x09B0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ -#define SPID (*(SPI_t *) 0x09C0) /* Serial Peripheral Interface */ -#define TCE0 (*(TC0_t *) 0x0A00) /* 16-bit Timer/Counter 0 */ -#define TCE2 (*(TC2_t *) 0x0A00) /* 16-bit Timer/Counter type 2 */ -#define TCE1 (*(TC1_t *) 0x0A40) /* 16-bit Timer/Counter 1 */ -#define AWEXE (*(AWEX_t *) 0x0A80) /* Advanced Waveform Extension */ -#define HIRESE (*(HIRES_t *) 0x0A90) /* High-Resolution Extension */ -#define USARTE0 (*(USART_t *) 0x0AA0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ -#define USARTE1 (*(USART_t *) 0x0AB0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ -#define SPIE (*(SPI_t *) 0x0AC0) /* Serial Peripheral Interface */ -#define TCF0 (*(TC0_t *) 0x0B00) /* 16-bit Timer/Counter 0 */ -#define TCF2 (*(TC2_t *) 0x0B00) /* 16-bit Timer/Counter type 2 */ -#define HIRESF (*(HIRES_t *) 0x0B90) /* High-Resolution Extension */ -#define USARTF0 (*(USART_t *) 0x0BA0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ - - -#endif /* !defined (__ASSEMBLER__) */ - - -/* ========== Flattened fully qualified IO register names ========== */ - -/* GPIO - General Purpose IO Registers */ -#define GPIO_GPIOR0 _SFR_MEM8(0x0000) -#define GPIO_GPIOR1 _SFR_MEM8(0x0001) -#define GPIO_GPIOR2 _SFR_MEM8(0x0002) -#define GPIO_GPIOR3 _SFR_MEM8(0x0003) -#define GPIO_GPIOR4 _SFR_MEM8(0x0004) -#define GPIO_GPIOR5 _SFR_MEM8(0x0005) -#define GPIO_GPIOR6 _SFR_MEM8(0x0006) -#define GPIO_GPIOR7 _SFR_MEM8(0x0007) -#define GPIO_GPIOR8 _SFR_MEM8(0x0008) -#define GPIO_GPIOR9 _SFR_MEM8(0x0009) -#define GPIO_GPIORA _SFR_MEM8(0x000A) -#define GPIO_GPIORB _SFR_MEM8(0x000B) -#define GPIO_GPIORC _SFR_MEM8(0x000C) -#define GPIO_GPIORD _SFR_MEM8(0x000D) -#define GPIO_GPIORE _SFR_MEM8(0x000E) -#define GPIO_GPIORF _SFR_MEM8(0x000F) - -/* Deprecated */ -#define GPIO_GPIO0 _SFR_MEM8(0x0000) -#define GPIO_GPIO1 _SFR_MEM8(0x0001) -#define GPIO_GPIO2 _SFR_MEM8(0x0002) -#define GPIO_GPIO3 _SFR_MEM8(0x0003) -#define GPIO_GPIO4 _SFR_MEM8(0x0004) -#define GPIO_GPIO5 _SFR_MEM8(0x0005) -#define GPIO_GPIO6 _SFR_MEM8(0x0006) -#define GPIO_GPIO7 _SFR_MEM8(0x0007) -#define GPIO_GPIO8 _SFR_MEM8(0x0008) -#define GPIO_GPIO9 _SFR_MEM8(0x0009) -#define GPIO_GPIOA _SFR_MEM8(0x000A) -#define GPIO_GPIOB _SFR_MEM8(0x000B) -#define GPIO_GPIOC _SFR_MEM8(0x000C) -#define GPIO_GPIOD _SFR_MEM8(0x000D) -#define GPIO_GPIOE _SFR_MEM8(0x000E) -#define GPIO_GPIOF _SFR_MEM8(0x000F) - -/* NVM_FUSES - Fuses */ -#define FUSE_FUSEBYTE0 _SFR_MEM8(0x0000) -#define FUSE_FUSEBYTE1 _SFR_MEM8(0x0001) -#define FUSE_FUSEBYTE2 _SFR_MEM8(0x0002) -#define FUSE_FUSEBYTE4 _SFR_MEM8(0x0004) -#define FUSE_FUSEBYTE5 _SFR_MEM8(0x0005) - -/* NVM_LOCKBITS - Lock Bits */ -#define LOCKBIT_LOCKBITS _SFR_MEM8(0x0000) - -/* NVM_PROD_SIGNATURES - Production Signatures */ -#define PRODSIGNATURES_RCOSC2M _SFR_MEM8(0x0000) -#define PRODSIGNATURES_RCOSC2MA _SFR_MEM8(0x0001) -#define PRODSIGNATURES_RCOSC32K _SFR_MEM8(0x0002) -#define PRODSIGNATURES_RCOSC32M _SFR_MEM8(0x0003) -#define PRODSIGNATURES_RCOSC32MA _SFR_MEM8(0x0004) -#define PRODSIGNATURES_LOTNUM0 _SFR_MEM8(0x0008) -#define PRODSIGNATURES_LOTNUM1 _SFR_MEM8(0x0009) -#define PRODSIGNATURES_LOTNUM2 _SFR_MEM8(0x000A) -#define PRODSIGNATURES_LOTNUM3 _SFR_MEM8(0x000B) -#define PRODSIGNATURES_LOTNUM4 _SFR_MEM8(0x000C) -#define PRODSIGNATURES_LOTNUM5 _SFR_MEM8(0x000D) -#define PRODSIGNATURES_WAFNUM _SFR_MEM8(0x0010) -#define PRODSIGNATURES_COORDX0 _SFR_MEM8(0x0012) -#define PRODSIGNATURES_COORDX1 _SFR_MEM8(0x0013) -#define PRODSIGNATURES_COORDY0 _SFR_MEM8(0x0014) -#define PRODSIGNATURES_COORDY1 _SFR_MEM8(0x0015) -#define PRODSIGNATURES_USBCAL0 _SFR_MEM8(0x001A) -#define PRODSIGNATURES_USBCAL1 _SFR_MEM8(0x001B) -#define PRODSIGNATURES_USBRCOSC _SFR_MEM8(0x001C) -#define PRODSIGNATURES_USBRCOSCA _SFR_MEM8(0x001D) -#define PRODSIGNATURES_ADCACAL0 _SFR_MEM8(0x0020) -#define PRODSIGNATURES_ADCACAL1 _SFR_MEM8(0x0021) -#define PRODSIGNATURES_ADCBCAL0 _SFR_MEM8(0x0024) -#define PRODSIGNATURES_ADCBCAL1 _SFR_MEM8(0x0025) -#define PRODSIGNATURES_TEMPSENSE0 _SFR_MEM8(0x002E) -#define PRODSIGNATURES_TEMPSENSE1 _SFR_MEM8(0x002F) -#define PRODSIGNATURES_DACA0OFFCAL _SFR_MEM8(0x0030) -#define PRODSIGNATURES_DACA0GAINCAL _SFR_MEM8(0x0031) -#define PRODSIGNATURES_DACB0OFFCAL _SFR_MEM8(0x0032) -#define PRODSIGNATURES_DACB0GAINCAL _SFR_MEM8(0x0033) -#define PRODSIGNATURES_DACA1OFFCAL _SFR_MEM8(0x0034) -#define PRODSIGNATURES_DACA1GAINCAL _SFR_MEM8(0x0035) -#define PRODSIGNATURES_DACB1OFFCAL _SFR_MEM8(0x0036) -#define PRODSIGNATURES_DACB1GAINCAL _SFR_MEM8(0x0037) - -/* VPORT - Virtual Port */ -#define VPORT0_DIR _SFR_MEM8(0x0010) -#define VPORT0_OUT _SFR_MEM8(0x0011) -#define VPORT0_IN _SFR_MEM8(0x0012) -#define VPORT0_INTFLAGS _SFR_MEM8(0x0013) - -/* VPORT - Virtual Port */ -#define VPORT1_DIR _SFR_MEM8(0x0014) -#define VPORT1_OUT _SFR_MEM8(0x0015) -#define VPORT1_IN _SFR_MEM8(0x0016) -#define VPORT1_INTFLAGS _SFR_MEM8(0x0017) - -/* VPORT - Virtual Port */ -#define VPORT2_DIR _SFR_MEM8(0x0018) -#define VPORT2_OUT _SFR_MEM8(0x0019) -#define VPORT2_IN _SFR_MEM8(0x001A) -#define VPORT2_INTFLAGS _SFR_MEM8(0x001B) - -/* VPORT - Virtual Port */ -#define VPORT3_DIR _SFR_MEM8(0x001C) -#define VPORT3_OUT _SFR_MEM8(0x001D) -#define VPORT3_IN _SFR_MEM8(0x001E) -#define VPORT3_INTFLAGS _SFR_MEM8(0x001F) - -/* OCD - On-Chip Debug System */ -#define OCD_OCDR0 _SFR_MEM8(0x002E) -#define OCD_OCDR1 _SFR_MEM8(0x002F) - -/* CPU - CPU registers */ -#define CPU_CCP _SFR_MEM8(0x0034) -#define CPU_RAMPD _SFR_MEM8(0x0038) -#define CPU_RAMPX _SFR_MEM8(0x0039) -#define CPU_RAMPY _SFR_MEM8(0x003A) -#define CPU_RAMPZ _SFR_MEM8(0x003B) -#define CPU_EIND _SFR_MEM8(0x003C) -#define CPU_SPL _SFR_MEM8(0x003D) -#define CPU_SPH _SFR_MEM8(0x003E) -#define CPU_SREG _SFR_MEM8(0x003F) - -/* CLK - Clock System */ -#define CLK_CTRL _SFR_MEM8(0x0040) -#define CLK_PSCTRL _SFR_MEM8(0x0041) -#define CLK_LOCK _SFR_MEM8(0x0042) -#define CLK_RTCCTRL _SFR_MEM8(0x0043) -#define CLK_USBCTRL _SFR_MEM8(0x0044) - -/* SLEEP - Sleep Controller */ -#define SLEEP_CTRL _SFR_MEM8(0x0048) - -/* OSC - Oscillator */ -#define OSC_CTRL _SFR_MEM8(0x0050) -#define OSC_STATUS _SFR_MEM8(0x0051) -#define OSC_XOSCCTRL _SFR_MEM8(0x0052) -#define OSC_XOSCFAIL _SFR_MEM8(0x0053) -#define OSC_RC32KCAL _SFR_MEM8(0x0054) -#define OSC_PLLCTRL _SFR_MEM8(0x0055) -#define OSC_DFLLCTRL _SFR_MEM8(0x0056) - -/* DFLL - DFLL */ -#define DFLLRC32M_CTRL _SFR_MEM8(0x0060) -#define DFLLRC32M_CALA _SFR_MEM8(0x0062) -#define DFLLRC32M_CALB _SFR_MEM8(0x0063) -#define DFLLRC32M_COMP0 _SFR_MEM8(0x0064) -#define DFLLRC32M_COMP1 _SFR_MEM8(0x0065) -#define DFLLRC32M_COMP2 _SFR_MEM8(0x0066) - -/* DFLL - DFLL */ -#define DFLLRC2M_CTRL _SFR_MEM8(0x0068) -#define DFLLRC2M_CALA _SFR_MEM8(0x006A) -#define DFLLRC2M_CALB _SFR_MEM8(0x006B) -#define DFLLRC2M_COMP0 _SFR_MEM8(0x006C) -#define DFLLRC2M_COMP1 _SFR_MEM8(0x006D) -#define DFLLRC2M_COMP2 _SFR_MEM8(0x006E) - -/* PR - Power Reduction */ -#define PR_PRGEN _SFR_MEM8(0x0070) -#define PR_PRPA _SFR_MEM8(0x0071) -#define PR_PRPB _SFR_MEM8(0x0072) -#define PR_PRPC _SFR_MEM8(0x0073) -#define PR_PRPD _SFR_MEM8(0x0074) -#define PR_PRPE _SFR_MEM8(0x0075) -#define PR_PRPF _SFR_MEM8(0x0076) - -/* RST - Reset */ -#define RST_STATUS _SFR_MEM8(0x0078) -#define RST_CTRL _SFR_MEM8(0x0079) - -/* WDT - Watch-Dog Timer */ -#define WDT_CTRL _SFR_MEM8(0x0080) -#define WDT_WINCTRL _SFR_MEM8(0x0081) -#define WDT_STATUS _SFR_MEM8(0x0082) - -/* MCU - MCU Control */ -#define MCU_DEVID0 _SFR_MEM8(0x0090) -#define MCU_DEVID1 _SFR_MEM8(0x0091) -#define MCU_DEVID2 _SFR_MEM8(0x0092) -#define MCU_REVID _SFR_MEM8(0x0093) -#define MCU_JTAGUID _SFR_MEM8(0x0094) -#define MCU_MCUCR _SFR_MEM8(0x0096) -#define MCU_ANAINIT _SFR_MEM8(0x0097) -#define MCU_EVSYSLOCK _SFR_MEM8(0x0098) -#define MCU_AWEXLOCK _SFR_MEM8(0x0099) - -/* PMIC - Programmable Multi-level Interrupt Controller */ -#define PMIC_STATUS _SFR_MEM8(0x00A0) -#define PMIC_INTPRI _SFR_MEM8(0x00A1) -#define PMIC_CTRL _SFR_MEM8(0x00A2) - -/* PORTCFG - I/O port Configuration */ -#define PORTCFG_MPCMASK _SFR_MEM8(0x00B0) -#define PORTCFG_VPCTRLA _SFR_MEM8(0x00B2) -#define PORTCFG_VPCTRLB _SFR_MEM8(0x00B3) -#define PORTCFG_CLKEVOUT _SFR_MEM8(0x00B4) -#define PORTCFG_EBIOUT _SFR_MEM8(0x00B5) -#define PORTCFG_EVOUTSEL _SFR_MEM8(0x00B6) - -/* AES - AES Module */ -#define AES_CTRL _SFR_MEM8(0x00C0) -#define AES_STATUS _SFR_MEM8(0x00C1) -#define AES_STATE _SFR_MEM8(0x00C2) -#define AES_KEY _SFR_MEM8(0x00C3) -#define AES_INTCTRL _SFR_MEM8(0x00C4) - -/* CRC - Cyclic Redundancy Checker */ -#define CRC_CTRL _SFR_MEM8(0x00D0) -#define CRC_STATUS _SFR_MEM8(0x00D1) -#define CRC_DATAIN _SFR_MEM8(0x00D3) -#define CRC_CHECKSUM0 _SFR_MEM8(0x00D4) -#define CRC_CHECKSUM1 _SFR_MEM8(0x00D5) -#define CRC_CHECKSUM2 _SFR_MEM8(0x00D6) -#define CRC_CHECKSUM3 _SFR_MEM8(0x00D7) - -/* DMA - DMA Controller */ -#define DMA_CTRL _SFR_MEM8(0x0100) -#define DMA_INTFLAGS _SFR_MEM8(0x0103) -#define DMA_STATUS _SFR_MEM8(0x0104) -#define DMA_TEMP _SFR_MEM16(0x0106) -#define DMA_CH0_CTRLA _SFR_MEM8(0x0110) -#define DMA_CH0_CTRLB _SFR_MEM8(0x0111) -#define DMA_CH0_ADDRCTRL _SFR_MEM8(0x0112) -#define DMA_CH0_TRIGSRC _SFR_MEM8(0x0113) -#define DMA_CH0_TRFCNT _SFR_MEM16(0x0114) -#define DMA_CH0_REPCNT _SFR_MEM8(0x0116) -#define DMA_CH0_SRCADDR0 _SFR_MEM8(0x0118) -#define DMA_CH0_SRCADDR1 _SFR_MEM8(0x0119) -#define DMA_CH0_SRCADDR2 _SFR_MEM8(0x011A) -#define DMA_CH0_DESTADDR0 _SFR_MEM8(0x011C) -#define DMA_CH0_DESTADDR1 _SFR_MEM8(0x011D) -#define DMA_CH0_DESTADDR2 _SFR_MEM8(0x011E) -#define DMA_CH1_CTRLA _SFR_MEM8(0x0120) -#define DMA_CH1_CTRLB _SFR_MEM8(0x0121) -#define DMA_CH1_ADDRCTRL _SFR_MEM8(0x0122) -#define DMA_CH1_TRIGSRC _SFR_MEM8(0x0123) -#define DMA_CH1_TRFCNT _SFR_MEM16(0x0124) -#define DMA_CH1_REPCNT _SFR_MEM8(0x0126) -#define DMA_CH1_SRCADDR0 _SFR_MEM8(0x0128) -#define DMA_CH1_SRCADDR1 _SFR_MEM8(0x0129) -#define DMA_CH1_SRCADDR2 _SFR_MEM8(0x012A) -#define DMA_CH1_DESTADDR0 _SFR_MEM8(0x012C) -#define DMA_CH1_DESTADDR1 _SFR_MEM8(0x012D) -#define DMA_CH1_DESTADDR2 _SFR_MEM8(0x012E) -#define DMA_CH2_CTRLA _SFR_MEM8(0x0130) -#define DMA_CH2_CTRLB _SFR_MEM8(0x0131) -#define DMA_CH2_ADDRCTRL _SFR_MEM8(0x0132) -#define DMA_CH2_TRIGSRC _SFR_MEM8(0x0133) -#define DMA_CH2_TRFCNT _SFR_MEM16(0x0134) -#define DMA_CH2_REPCNT _SFR_MEM8(0x0136) -#define DMA_CH2_SRCADDR0 _SFR_MEM8(0x0138) -#define DMA_CH2_SRCADDR1 _SFR_MEM8(0x0139) -#define DMA_CH2_SRCADDR2 _SFR_MEM8(0x013A) -#define DMA_CH2_DESTADDR0 _SFR_MEM8(0x013C) -#define DMA_CH2_DESTADDR1 _SFR_MEM8(0x013D) -#define DMA_CH2_DESTADDR2 _SFR_MEM8(0x013E) -#define DMA_CH3_CTRLA _SFR_MEM8(0x0140) -#define DMA_CH3_CTRLB _SFR_MEM8(0x0141) -#define DMA_CH3_ADDRCTRL _SFR_MEM8(0x0142) -#define DMA_CH3_TRIGSRC _SFR_MEM8(0x0143) -#define DMA_CH3_TRFCNT _SFR_MEM16(0x0144) -#define DMA_CH3_REPCNT _SFR_MEM8(0x0146) -#define DMA_CH3_SRCADDR0 _SFR_MEM8(0x0148) -#define DMA_CH3_SRCADDR1 _SFR_MEM8(0x0149) -#define DMA_CH3_SRCADDR2 _SFR_MEM8(0x014A) -#define DMA_CH3_DESTADDR0 _SFR_MEM8(0x014C) -#define DMA_CH3_DESTADDR1 _SFR_MEM8(0x014D) -#define DMA_CH3_DESTADDR2 _SFR_MEM8(0x014E) - -/* EVSYS - Event System */ -#define EVSYS_CH0MUX _SFR_MEM8(0x0180) -#define EVSYS_CH1MUX _SFR_MEM8(0x0181) -#define EVSYS_CH2MUX _SFR_MEM8(0x0182) -#define EVSYS_CH3MUX _SFR_MEM8(0x0183) -#define EVSYS_CH4MUX _SFR_MEM8(0x0184) -#define EVSYS_CH5MUX _SFR_MEM8(0x0185) -#define EVSYS_CH6MUX _SFR_MEM8(0x0186) -#define EVSYS_CH7MUX _SFR_MEM8(0x0187) -#define EVSYS_CH0CTRL _SFR_MEM8(0x0188) -#define EVSYS_CH1CTRL _SFR_MEM8(0x0189) -#define EVSYS_CH2CTRL _SFR_MEM8(0x018A) -#define EVSYS_CH3CTRL _SFR_MEM8(0x018B) -#define EVSYS_CH4CTRL _SFR_MEM8(0x018C) -#define EVSYS_CH5CTRL _SFR_MEM8(0x018D) -#define EVSYS_CH6CTRL _SFR_MEM8(0x018E) -#define EVSYS_CH7CTRL _SFR_MEM8(0x018F) -#define EVSYS_STROBE _SFR_MEM8(0x0190) -#define EVSYS_DATA _SFR_MEM8(0x0191) - -/* NVM - Non-volatile Memory Controller */ -#define NVM_ADDR0 _SFR_MEM8(0x01C0) -#define NVM_ADDR1 _SFR_MEM8(0x01C1) -#define NVM_ADDR2 _SFR_MEM8(0x01C2) -#define NVM_DATA0 _SFR_MEM8(0x01C4) -#define NVM_DATA1 _SFR_MEM8(0x01C5) -#define NVM_DATA2 _SFR_MEM8(0x01C6) -#define NVM_CMD _SFR_MEM8(0x01CA) -#define NVM_CTRLA _SFR_MEM8(0x01CB) -#define NVM_CTRLB _SFR_MEM8(0x01CC) -#define NVM_INTCTRL _SFR_MEM8(0x01CD) -#define NVM_STATUS _SFR_MEM8(0x01CF) -#define NVM_LOCKBITS _SFR_MEM8(0x01D0) - -/* ADC - Analog-to-Digital Converter */ -#define ADCA_CTRLA _SFR_MEM8(0x0200) -#define ADCA_CTRLB _SFR_MEM8(0x0201) -#define ADCA_REFCTRL _SFR_MEM8(0x0202) -#define ADCA_EVCTRL _SFR_MEM8(0x0203) -#define ADCA_PRESCALER _SFR_MEM8(0x0204) -#define ADCA_INTFLAGS _SFR_MEM8(0x0206) -#define ADCA_TEMP _SFR_MEM8(0x0207) -#define ADCA_CAL _SFR_MEM16(0x020C) -#define ADCA_CH0RES _SFR_MEM16(0x0210) -#define ADCA_CH1RES _SFR_MEM16(0x0212) -#define ADCA_CH2RES _SFR_MEM16(0x0214) -#define ADCA_CH3RES _SFR_MEM16(0x0216) -#define ADCA_CMP _SFR_MEM16(0x0218) -#define ADCA_CH0_CTRL _SFR_MEM8(0x0220) -#define ADCA_CH0_MUXCTRL _SFR_MEM8(0x0221) -#define ADCA_CH0_INTCTRL _SFR_MEM8(0x0222) -#define ADCA_CH0_INTFLAGS _SFR_MEM8(0x0223) -#define ADCA_CH0_RES _SFR_MEM16(0x0224) -#define ADCA_CH0_SCAN _SFR_MEM8(0x0226) -#define ADCA_CH1_CTRL _SFR_MEM8(0x0228) -#define ADCA_CH1_MUXCTRL _SFR_MEM8(0x0229) -#define ADCA_CH1_INTCTRL _SFR_MEM8(0x022A) -#define ADCA_CH1_INTFLAGS _SFR_MEM8(0x022B) -#define ADCA_CH1_RES _SFR_MEM16(0x022C) -#define ADCA_CH1_SCAN _SFR_MEM8(0x022E) -#define ADCA_CH2_CTRL _SFR_MEM8(0x0230) -#define ADCA_CH2_MUXCTRL _SFR_MEM8(0x0231) -#define ADCA_CH2_INTCTRL _SFR_MEM8(0x0232) -#define ADCA_CH2_INTFLAGS _SFR_MEM8(0x0233) -#define ADCA_CH2_RES _SFR_MEM16(0x0234) -#define ADCA_CH2_SCAN _SFR_MEM8(0x0236) -#define ADCA_CH3_CTRL _SFR_MEM8(0x0238) -#define ADCA_CH3_MUXCTRL _SFR_MEM8(0x0239) -#define ADCA_CH3_INTCTRL _SFR_MEM8(0x023A) -#define ADCA_CH3_INTFLAGS _SFR_MEM8(0x023B) -#define ADCA_CH3_RES _SFR_MEM16(0x023C) -#define ADCA_CH3_SCAN _SFR_MEM8(0x023E) - -/* ADC - Analog-to-Digital Converter */ -#define ADCB_CTRLA _SFR_MEM8(0x0240) -#define ADCB_CTRLB _SFR_MEM8(0x0241) -#define ADCB_REFCTRL _SFR_MEM8(0x0242) -#define ADCB_EVCTRL _SFR_MEM8(0x0243) -#define ADCB_PRESCALER _SFR_MEM8(0x0244) -#define ADCB_INTFLAGS _SFR_MEM8(0x0246) -#define ADCB_TEMP _SFR_MEM8(0x0247) -#define ADCB_CAL _SFR_MEM16(0x024C) -#define ADCB_CH0RES _SFR_MEM16(0x0250) -#define ADCB_CH1RES _SFR_MEM16(0x0252) -#define ADCB_CH2RES _SFR_MEM16(0x0254) -#define ADCB_CH3RES _SFR_MEM16(0x0256) -#define ADCB_CMP _SFR_MEM16(0x0258) -#define ADCB_CH0_CTRL _SFR_MEM8(0x0260) -#define ADCB_CH0_MUXCTRL _SFR_MEM8(0x0261) -#define ADCB_CH0_INTCTRL _SFR_MEM8(0x0262) -#define ADCB_CH0_INTFLAGS _SFR_MEM8(0x0263) -#define ADCB_CH0_RES _SFR_MEM16(0x0264) -#define ADCB_CH0_SCAN _SFR_MEM8(0x0266) -#define ADCB_CH1_CTRL _SFR_MEM8(0x0268) -#define ADCB_CH1_MUXCTRL _SFR_MEM8(0x0269) -#define ADCB_CH1_INTCTRL _SFR_MEM8(0x026A) -#define ADCB_CH1_INTFLAGS _SFR_MEM8(0x026B) -#define ADCB_CH1_RES _SFR_MEM16(0x026C) -#define ADCB_CH1_SCAN _SFR_MEM8(0x026E) -#define ADCB_CH2_CTRL _SFR_MEM8(0x0270) -#define ADCB_CH2_MUXCTRL _SFR_MEM8(0x0271) -#define ADCB_CH2_INTCTRL _SFR_MEM8(0x0272) -#define ADCB_CH2_INTFLAGS _SFR_MEM8(0x0273) -#define ADCB_CH2_RES _SFR_MEM16(0x0274) -#define ADCB_CH2_SCAN _SFR_MEM8(0x0276) -#define ADCB_CH3_CTRL _SFR_MEM8(0x0278) -#define ADCB_CH3_MUXCTRL _SFR_MEM8(0x0279) -#define ADCB_CH3_INTCTRL _SFR_MEM8(0x027A) -#define ADCB_CH3_INTFLAGS _SFR_MEM8(0x027B) -#define ADCB_CH3_RES _SFR_MEM16(0x027C) -#define ADCB_CH3_SCAN _SFR_MEM8(0x027E) - -/* DAC - Digital-to-Analog Converter */ -#define DACB_CTRLA _SFR_MEM8(0x0320) -#define DACB_CTRLB _SFR_MEM8(0x0321) -#define DACB_CTRLC _SFR_MEM8(0x0322) -#define DACB_EVCTRL _SFR_MEM8(0x0323) -#define DACB_STATUS _SFR_MEM8(0x0325) -#define DACB_CH0GAINCAL _SFR_MEM8(0x0328) -#define DACB_CH0OFFSETCAL _SFR_MEM8(0x0329) -#define DACB_CH1GAINCAL _SFR_MEM8(0x032A) -#define DACB_CH1OFFSETCAL _SFR_MEM8(0x032B) -#define DACB_CH0DATA _SFR_MEM16(0x0338) -#define DACB_CH1DATA _SFR_MEM16(0x033A) - -/* AC - Analog Comparator */ -#define ACA_AC0CTRL _SFR_MEM8(0x0380) -#define ACA_AC1CTRL _SFR_MEM8(0x0381) -#define ACA_AC0MUXCTRL _SFR_MEM8(0x0382) -#define ACA_AC1MUXCTRL _SFR_MEM8(0x0383) -#define ACA_CTRLA _SFR_MEM8(0x0384) -#define ACA_CTRLB _SFR_MEM8(0x0385) -#define ACA_WINCTRL _SFR_MEM8(0x0386) -#define ACA_STATUS _SFR_MEM8(0x0387) - -/* AC - Analog Comparator */ -#define ACB_AC0CTRL _SFR_MEM8(0x0390) -#define ACB_AC1CTRL _SFR_MEM8(0x0391) -#define ACB_AC0MUXCTRL _SFR_MEM8(0x0392) -#define ACB_AC1MUXCTRL _SFR_MEM8(0x0393) -#define ACB_CTRLA _SFR_MEM8(0x0394) -#define ACB_CTRLB _SFR_MEM8(0x0395) -#define ACB_WINCTRL _SFR_MEM8(0x0396) -#define ACB_STATUS _SFR_MEM8(0x0397) - -/* RTC - Real-Time Counter */ -#define RTC_CTRL _SFR_MEM8(0x0400) -#define RTC_STATUS _SFR_MEM8(0x0401) -#define RTC_INTCTRL _SFR_MEM8(0x0402) -#define RTC_INTFLAGS _SFR_MEM8(0x0403) -#define RTC_TEMP _SFR_MEM8(0x0404) -#define RTC_CNT _SFR_MEM16(0x0408) -#define RTC_PER _SFR_MEM16(0x040A) -#define RTC_COMP _SFR_MEM16(0x040C) - -/* TWI - Two-Wire Interface */ -#define TWIC_CTRL _SFR_MEM8(0x0480) -#define TWIC_MASTER_CTRLA _SFR_MEM8(0x0481) -#define TWIC_MASTER_CTRLB _SFR_MEM8(0x0482) -#define TWIC_MASTER_CTRLC _SFR_MEM8(0x0483) -#define TWIC_MASTER_STATUS _SFR_MEM8(0x0484) -#define TWIC_MASTER_BAUD _SFR_MEM8(0x0485) -#define TWIC_MASTER_ADDR _SFR_MEM8(0x0486) -#define TWIC_MASTER_DATA _SFR_MEM8(0x0487) -#define TWIC_SLAVE_CTRLA _SFR_MEM8(0x0488) -#define TWIC_SLAVE_CTRLB _SFR_MEM8(0x0489) -#define TWIC_SLAVE_STATUS _SFR_MEM8(0x048A) -#define TWIC_SLAVE_ADDR _SFR_MEM8(0x048B) -#define TWIC_SLAVE_DATA _SFR_MEM8(0x048C) -#define TWIC_SLAVE_ADDRMASK _SFR_MEM8(0x048D) - -/* TWI - Two-Wire Interface */ -#define TWIE_CTRL _SFR_MEM8(0x04A0) -#define TWIE_MASTER_CTRLA _SFR_MEM8(0x04A1) -#define TWIE_MASTER_CTRLB _SFR_MEM8(0x04A2) -#define TWIE_MASTER_CTRLC _SFR_MEM8(0x04A3) -#define TWIE_MASTER_STATUS _SFR_MEM8(0x04A4) -#define TWIE_MASTER_BAUD _SFR_MEM8(0x04A5) -#define TWIE_MASTER_ADDR _SFR_MEM8(0x04A6) -#define TWIE_MASTER_DATA _SFR_MEM8(0x04A7) -#define TWIE_SLAVE_CTRLA _SFR_MEM8(0x04A8) -#define TWIE_SLAVE_CTRLB _SFR_MEM8(0x04A9) -#define TWIE_SLAVE_STATUS _SFR_MEM8(0x04AA) -#define TWIE_SLAVE_ADDR _SFR_MEM8(0x04AB) -#define TWIE_SLAVE_DATA _SFR_MEM8(0x04AC) -#define TWIE_SLAVE_ADDRMASK _SFR_MEM8(0x04AD) - -/* USB - Universal Serial Bus */ -#define USB_CTRLA _SFR_MEM8(0x04C0) -#define USB_CTRLB _SFR_MEM8(0x04C1) -#define USB_STATUS _SFR_MEM8(0x04C2) -#define USB_ADDR _SFR_MEM8(0x04C3) -#define USB_FIFOWP _SFR_MEM8(0x04C4) -#define USB_FIFORP _SFR_MEM8(0x04C5) -#define USB_EPPTR _SFR_MEM16(0x04C6) -#define USB_INTCTRLA _SFR_MEM8(0x04C8) -#define USB_INTCTRLB _SFR_MEM8(0x04C9) -#define USB_INTFLAGSACLR _SFR_MEM8(0x04CA) -#define USB_INTFLAGSASET _SFR_MEM8(0x04CB) -#define USB_INTFLAGSBCLR _SFR_MEM8(0x04CC) -#define USB_INTFLAGSBSET _SFR_MEM8(0x04CD) -#define USB_CAL0 _SFR_MEM8(0x04FA) -#define USB_CAL1 _SFR_MEM8(0x04FB) - -/* PORT - I/O Ports */ -#define PORTA_DIR _SFR_MEM8(0x0600) -#define PORTA_DIRSET _SFR_MEM8(0x0601) -#define PORTA_DIRCLR _SFR_MEM8(0x0602) -#define PORTA_DIRTGL _SFR_MEM8(0x0603) -#define PORTA_OUT _SFR_MEM8(0x0604) -#define PORTA_OUTSET _SFR_MEM8(0x0605) -#define PORTA_OUTCLR _SFR_MEM8(0x0606) -#define PORTA_OUTTGL _SFR_MEM8(0x0607) -#define PORTA_IN _SFR_MEM8(0x0608) -#define PORTA_INTCTRL _SFR_MEM8(0x0609) -#define PORTA_INT0MASK _SFR_MEM8(0x060A) -#define PORTA_INT1MASK _SFR_MEM8(0x060B) -#define PORTA_INTFLAGS _SFR_MEM8(0x060C) -#define PORTA_REMAP _SFR_MEM8(0x060E) -#define PORTA_PIN0CTRL _SFR_MEM8(0x0610) -#define PORTA_PIN1CTRL _SFR_MEM8(0x0611) -#define PORTA_PIN2CTRL _SFR_MEM8(0x0612) -#define PORTA_PIN3CTRL _SFR_MEM8(0x0613) -#define PORTA_PIN4CTRL _SFR_MEM8(0x0614) -#define PORTA_PIN5CTRL _SFR_MEM8(0x0615) -#define PORTA_PIN6CTRL _SFR_MEM8(0x0616) -#define PORTA_PIN7CTRL _SFR_MEM8(0x0617) - -/* PORT - I/O Ports */ -#define PORTB_DIR _SFR_MEM8(0x0620) -#define PORTB_DIRSET _SFR_MEM8(0x0621) -#define PORTB_DIRCLR _SFR_MEM8(0x0622) -#define PORTB_DIRTGL _SFR_MEM8(0x0623) -#define PORTB_OUT _SFR_MEM8(0x0624) -#define PORTB_OUTSET _SFR_MEM8(0x0625) -#define PORTB_OUTCLR _SFR_MEM8(0x0626) -#define PORTB_OUTTGL _SFR_MEM8(0x0627) -#define PORTB_IN _SFR_MEM8(0x0628) -#define PORTB_INTCTRL _SFR_MEM8(0x0629) -#define PORTB_INT0MASK _SFR_MEM8(0x062A) -#define PORTB_INT1MASK _SFR_MEM8(0x062B) -#define PORTB_INTFLAGS _SFR_MEM8(0x062C) -#define PORTB_REMAP _SFR_MEM8(0x062E) -#define PORTB_PIN0CTRL _SFR_MEM8(0x0630) -#define PORTB_PIN1CTRL _SFR_MEM8(0x0631) -#define PORTB_PIN2CTRL _SFR_MEM8(0x0632) -#define PORTB_PIN3CTRL _SFR_MEM8(0x0633) -#define PORTB_PIN4CTRL _SFR_MEM8(0x0634) -#define PORTB_PIN5CTRL _SFR_MEM8(0x0635) -#define PORTB_PIN6CTRL _SFR_MEM8(0x0636) -#define PORTB_PIN7CTRL _SFR_MEM8(0x0637) - -/* PORT - I/O Ports */ -#define PORTC_DIR _SFR_MEM8(0x0640) -#define PORTC_DIRSET _SFR_MEM8(0x0641) -#define PORTC_DIRCLR _SFR_MEM8(0x0642) -#define PORTC_DIRTGL _SFR_MEM8(0x0643) -#define PORTC_OUT _SFR_MEM8(0x0644) -#define PORTC_OUTSET _SFR_MEM8(0x0645) -#define PORTC_OUTCLR _SFR_MEM8(0x0646) -#define PORTC_OUTTGL _SFR_MEM8(0x0647) -#define PORTC_IN _SFR_MEM8(0x0648) -#define PORTC_INTCTRL _SFR_MEM8(0x0649) -#define PORTC_INT0MASK _SFR_MEM8(0x064A) -#define PORTC_INT1MASK _SFR_MEM8(0x064B) -#define PORTC_INTFLAGS _SFR_MEM8(0x064C) -#define PORTC_REMAP _SFR_MEM8(0x064E) -#define PORTC_PIN0CTRL _SFR_MEM8(0x0650) -#define PORTC_PIN1CTRL _SFR_MEM8(0x0651) -#define PORTC_PIN2CTRL _SFR_MEM8(0x0652) -#define PORTC_PIN3CTRL _SFR_MEM8(0x0653) -#define PORTC_PIN4CTRL _SFR_MEM8(0x0654) -#define PORTC_PIN5CTRL _SFR_MEM8(0x0655) -#define PORTC_PIN6CTRL _SFR_MEM8(0x0656) -#define PORTC_PIN7CTRL _SFR_MEM8(0x0657) - -/* PORT - I/O Ports */ -#define PORTD_DIR _SFR_MEM8(0x0660) -#define PORTD_DIRSET _SFR_MEM8(0x0661) -#define PORTD_DIRCLR _SFR_MEM8(0x0662) -#define PORTD_DIRTGL _SFR_MEM8(0x0663) -#define PORTD_OUT _SFR_MEM8(0x0664) -#define PORTD_OUTSET _SFR_MEM8(0x0665) -#define PORTD_OUTCLR _SFR_MEM8(0x0666) -#define PORTD_OUTTGL _SFR_MEM8(0x0667) -#define PORTD_IN _SFR_MEM8(0x0668) -#define PORTD_INTCTRL _SFR_MEM8(0x0669) -#define PORTD_INT0MASK _SFR_MEM8(0x066A) -#define PORTD_INT1MASK _SFR_MEM8(0x066B) -#define PORTD_INTFLAGS _SFR_MEM8(0x066C) -#define PORTD_REMAP _SFR_MEM8(0x066E) -#define PORTD_PIN0CTRL _SFR_MEM8(0x0670) -#define PORTD_PIN1CTRL _SFR_MEM8(0x0671) -#define PORTD_PIN2CTRL _SFR_MEM8(0x0672) -#define PORTD_PIN3CTRL _SFR_MEM8(0x0673) -#define PORTD_PIN4CTRL _SFR_MEM8(0x0674) -#define PORTD_PIN5CTRL _SFR_MEM8(0x0675) -#define PORTD_PIN6CTRL _SFR_MEM8(0x0676) -#define PORTD_PIN7CTRL _SFR_MEM8(0x0677) - -/* PORT - I/O Ports */ -#define PORTE_DIR _SFR_MEM8(0x0680) -#define PORTE_DIRSET _SFR_MEM8(0x0681) -#define PORTE_DIRCLR _SFR_MEM8(0x0682) -#define PORTE_DIRTGL _SFR_MEM8(0x0683) -#define PORTE_OUT _SFR_MEM8(0x0684) -#define PORTE_OUTSET _SFR_MEM8(0x0685) -#define PORTE_OUTCLR _SFR_MEM8(0x0686) -#define PORTE_OUTTGL _SFR_MEM8(0x0687) -#define PORTE_IN _SFR_MEM8(0x0688) -#define PORTE_INTCTRL _SFR_MEM8(0x0689) -#define PORTE_INT0MASK _SFR_MEM8(0x068A) -#define PORTE_INT1MASK _SFR_MEM8(0x068B) -#define PORTE_INTFLAGS _SFR_MEM8(0x068C) -#define PORTE_REMAP _SFR_MEM8(0x068E) -#define PORTE_PIN0CTRL _SFR_MEM8(0x0690) -#define PORTE_PIN1CTRL _SFR_MEM8(0x0691) -#define PORTE_PIN2CTRL _SFR_MEM8(0x0692) -#define PORTE_PIN3CTRL _SFR_MEM8(0x0693) -#define PORTE_PIN4CTRL _SFR_MEM8(0x0694) -#define PORTE_PIN5CTRL _SFR_MEM8(0x0695) -#define PORTE_PIN6CTRL _SFR_MEM8(0x0696) -#define PORTE_PIN7CTRL _SFR_MEM8(0x0697) - -/* PORT - I/O Ports */ -#define PORTF_DIR _SFR_MEM8(0x06A0) -#define PORTF_DIRSET _SFR_MEM8(0x06A1) -#define PORTF_DIRCLR _SFR_MEM8(0x06A2) -#define PORTF_DIRTGL _SFR_MEM8(0x06A3) -#define PORTF_OUT _SFR_MEM8(0x06A4) -#define PORTF_OUTSET _SFR_MEM8(0x06A5) -#define PORTF_OUTCLR _SFR_MEM8(0x06A6) -#define PORTF_OUTTGL _SFR_MEM8(0x06A7) -#define PORTF_IN _SFR_MEM8(0x06A8) -#define PORTF_INTCTRL _SFR_MEM8(0x06A9) -#define PORTF_INT0MASK _SFR_MEM8(0x06AA) -#define PORTF_INT1MASK _SFR_MEM8(0x06AB) -#define PORTF_INTFLAGS _SFR_MEM8(0x06AC) -#define PORTF_REMAP _SFR_MEM8(0x06AE) -#define PORTF_PIN0CTRL _SFR_MEM8(0x06B0) -#define PORTF_PIN1CTRL _SFR_MEM8(0x06B1) -#define PORTF_PIN2CTRL _SFR_MEM8(0x06B2) -#define PORTF_PIN3CTRL _SFR_MEM8(0x06B3) -#define PORTF_PIN4CTRL _SFR_MEM8(0x06B4) -#define PORTF_PIN5CTRL _SFR_MEM8(0x06B5) -#define PORTF_PIN6CTRL _SFR_MEM8(0x06B6) -#define PORTF_PIN7CTRL _SFR_MEM8(0x06B7) - -/* PORT - I/O Ports */ -#define PORTR_DIR _SFR_MEM8(0x07E0) -#define PORTR_DIRSET _SFR_MEM8(0x07E1) -#define PORTR_DIRCLR _SFR_MEM8(0x07E2) -#define PORTR_DIRTGL _SFR_MEM8(0x07E3) -#define PORTR_OUT _SFR_MEM8(0x07E4) -#define PORTR_OUTSET _SFR_MEM8(0x07E5) -#define PORTR_OUTCLR _SFR_MEM8(0x07E6) -#define PORTR_OUTTGL _SFR_MEM8(0x07E7) -#define PORTR_IN _SFR_MEM8(0x07E8) -#define PORTR_INTCTRL _SFR_MEM8(0x07E9) -#define PORTR_INT0MASK _SFR_MEM8(0x07EA) -#define PORTR_INT1MASK _SFR_MEM8(0x07EB) -#define PORTR_INTFLAGS _SFR_MEM8(0x07EC) -#define PORTR_REMAP _SFR_MEM8(0x07EE) -#define PORTR_PIN0CTRL _SFR_MEM8(0x07F0) -#define PORTR_PIN1CTRL _SFR_MEM8(0x07F1) -#define PORTR_PIN2CTRL _SFR_MEM8(0x07F2) -#define PORTR_PIN3CTRL _SFR_MEM8(0x07F3) -#define PORTR_PIN4CTRL _SFR_MEM8(0x07F4) -#define PORTR_PIN5CTRL _SFR_MEM8(0x07F5) -#define PORTR_PIN6CTRL _SFR_MEM8(0x07F6) -#define PORTR_PIN7CTRL _SFR_MEM8(0x07F7) - -/* TC0 - 16-bit Timer/Counter 0 */ -#define TCC0_CTRLA _SFR_MEM8(0x0800) -#define TCC0_CTRLB _SFR_MEM8(0x0801) -#define TCC0_CTRLC _SFR_MEM8(0x0802) -#define TCC0_CTRLD _SFR_MEM8(0x0803) -#define TCC0_CTRLE _SFR_MEM8(0x0804) -#define TCC0_INTCTRLA _SFR_MEM8(0x0806) -#define TCC0_INTCTRLB _SFR_MEM8(0x0807) -#define TCC0_CTRLFCLR _SFR_MEM8(0x0808) -#define TCC0_CTRLFSET _SFR_MEM8(0x0809) -#define TCC0_CTRLGCLR _SFR_MEM8(0x080A) -#define TCC0_CTRLGSET _SFR_MEM8(0x080B) -#define TCC0_INTFLAGS _SFR_MEM8(0x080C) -#define TCC0_TEMP _SFR_MEM8(0x080F) -#define TCC0_CNT _SFR_MEM16(0x0820) -#define TCC0_PER _SFR_MEM16(0x0826) -#define TCC0_CCA _SFR_MEM16(0x0828) -#define TCC0_CCB _SFR_MEM16(0x082A) -#define TCC0_CCC _SFR_MEM16(0x082C) -#define TCC0_CCD _SFR_MEM16(0x082E) -#define TCC0_PERBUF _SFR_MEM16(0x0836) -#define TCC0_CCABUF _SFR_MEM16(0x0838) -#define TCC0_CCBBUF _SFR_MEM16(0x083A) -#define TCC0_CCCBUF _SFR_MEM16(0x083C) -#define TCC0_CCDBUF _SFR_MEM16(0x083E) - -/* TC2 - 16-bit Timer/Counter type 2 */ -#define TCC2_CTRLA _SFR_MEM8(0x0800) -#define TCC2_CTRLB _SFR_MEM8(0x0801) -#define TCC2_CTRLC _SFR_MEM8(0x0802) -#define TCC2_CTRLE _SFR_MEM8(0x0804) -#define TCC2_INTCTRLA _SFR_MEM8(0x0806) -#define TCC2_INTCTRLB _SFR_MEM8(0x0807) -#define TCC2_CTRLF _SFR_MEM8(0x0809) -#define TCC2_INTFLAGS _SFR_MEM8(0x080C) -#define TCC2_LCNT _SFR_MEM8(0x0820) -#define TCC2_HCNT _SFR_MEM8(0x0821) -#define TCC2_LPER _SFR_MEM8(0x0826) -#define TCC2_HPER _SFR_MEM8(0x0827) -#define TCC2_LCMPA _SFR_MEM8(0x0828) -#define TCC2_HCMPA _SFR_MEM8(0x0829) -#define TCC2_LCMPB _SFR_MEM8(0x082A) -#define TCC2_HCMPB _SFR_MEM8(0x082B) -#define TCC2_LCMPC _SFR_MEM8(0x082C) -#define TCC2_HCMPC _SFR_MEM8(0x082D) -#define TCC2_LCMPD _SFR_MEM8(0x082E) -#define TCC2_HCMPD _SFR_MEM8(0x082F) - -/* TC1 - 16-bit Timer/Counter 1 */ -#define TCC1_CTRLA _SFR_MEM8(0x0840) -#define TCC1_CTRLB _SFR_MEM8(0x0841) -#define TCC1_CTRLC _SFR_MEM8(0x0842) -#define TCC1_CTRLD _SFR_MEM8(0x0843) -#define TCC1_CTRLE _SFR_MEM8(0x0844) -#define TCC1_INTCTRLA _SFR_MEM8(0x0846) -#define TCC1_INTCTRLB _SFR_MEM8(0x0847) -#define TCC1_CTRLFCLR _SFR_MEM8(0x0848) -#define TCC1_CTRLFSET _SFR_MEM8(0x0849) -#define TCC1_CTRLGCLR _SFR_MEM8(0x084A) -#define TCC1_CTRLGSET _SFR_MEM8(0x084B) -#define TCC1_INTFLAGS _SFR_MEM8(0x084C) -#define TCC1_TEMP _SFR_MEM8(0x084F) -#define TCC1_CNT _SFR_MEM16(0x0860) -#define TCC1_PER _SFR_MEM16(0x0866) -#define TCC1_CCA _SFR_MEM16(0x0868) -#define TCC1_CCB _SFR_MEM16(0x086A) -#define TCC1_PERBUF _SFR_MEM16(0x0876) -#define TCC1_CCABUF _SFR_MEM16(0x0878) -#define TCC1_CCBBUF _SFR_MEM16(0x087A) - -/* AWEX - Advanced Waveform Extension */ -#define AWEXC_CTRL _SFR_MEM8(0x0880) -#define AWEXC_FDEMASK _SFR_MEM8(0x0882) -#define AWEXC_FDCTRL _SFR_MEM8(0x0883) -#define AWEXC_STATUS _SFR_MEM8(0x0884) -#define AWEXC_STATUSSET _SFR_MEM8(0x0885) -#define AWEXC_DTBOTH _SFR_MEM8(0x0886) -#define AWEXC_DTBOTHBUF _SFR_MEM8(0x0887) -#define AWEXC_DTLS _SFR_MEM8(0x0888) -#define AWEXC_DTHS _SFR_MEM8(0x0889) -#define AWEXC_DTLSBUF _SFR_MEM8(0x088A) -#define AWEXC_DTHSBUF _SFR_MEM8(0x088B) -#define AWEXC_OUTOVEN _SFR_MEM8(0x088C) - -/* HIRES - High-Resolution Extension */ -#define HIRESC_CTRLA _SFR_MEM8(0x0890) - -/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ -#define USARTC0_DATA _SFR_MEM8(0x08A0) -#define USARTC0_STATUS _SFR_MEM8(0x08A1) -#define USARTC0_CTRLA _SFR_MEM8(0x08A3) -#define USARTC0_CTRLB _SFR_MEM8(0x08A4) -#define USARTC0_CTRLC _SFR_MEM8(0x08A5) -#define USARTC0_BAUDCTRLA _SFR_MEM8(0x08A6) -#define USARTC0_BAUDCTRLB _SFR_MEM8(0x08A7) - -/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ -#define USARTC1_DATA _SFR_MEM8(0x08B0) -#define USARTC1_STATUS _SFR_MEM8(0x08B1) -#define USARTC1_CTRLA _SFR_MEM8(0x08B3) -#define USARTC1_CTRLB _SFR_MEM8(0x08B4) -#define USARTC1_CTRLC _SFR_MEM8(0x08B5) -#define USARTC1_BAUDCTRLA _SFR_MEM8(0x08B6) -#define USARTC1_BAUDCTRLB _SFR_MEM8(0x08B7) - -/* SPI - Serial Peripheral Interface */ -#define SPIC_CTRL _SFR_MEM8(0x08C0) -#define SPIC_INTCTRL _SFR_MEM8(0x08C1) -#define SPIC_STATUS _SFR_MEM8(0x08C2) -#define SPIC_DATA _SFR_MEM8(0x08C3) - -/* IRCOM - IR Communication Module */ -#define IRCOM_CTRL _SFR_MEM8(0x08F8) -#define IRCOM_TXPLCTRL _SFR_MEM8(0x08F9) -#define IRCOM_RXPLCTRL _SFR_MEM8(0x08FA) - -/* TC0 - 16-bit Timer/Counter 0 */ -#define TCD0_CTRLA _SFR_MEM8(0x0900) -#define TCD0_CTRLB _SFR_MEM8(0x0901) -#define TCD0_CTRLC _SFR_MEM8(0x0902) -#define TCD0_CTRLD _SFR_MEM8(0x0903) -#define TCD0_CTRLE _SFR_MEM8(0x0904) -#define TCD0_INTCTRLA _SFR_MEM8(0x0906) -#define TCD0_INTCTRLB _SFR_MEM8(0x0907) -#define TCD0_CTRLFCLR _SFR_MEM8(0x0908) -#define TCD0_CTRLFSET _SFR_MEM8(0x0909) -#define TCD0_CTRLGCLR _SFR_MEM8(0x090A) -#define TCD0_CTRLGSET _SFR_MEM8(0x090B) -#define TCD0_INTFLAGS _SFR_MEM8(0x090C) -#define TCD0_TEMP _SFR_MEM8(0x090F) -#define TCD0_CNT _SFR_MEM16(0x0920) -#define TCD0_PER _SFR_MEM16(0x0926) -#define TCD0_CCA _SFR_MEM16(0x0928) -#define TCD0_CCB _SFR_MEM16(0x092A) -#define TCD0_CCC _SFR_MEM16(0x092C) -#define TCD0_CCD _SFR_MEM16(0x092E) -#define TCD0_PERBUF _SFR_MEM16(0x0936) -#define TCD0_CCABUF _SFR_MEM16(0x0938) -#define TCD0_CCBBUF _SFR_MEM16(0x093A) -#define TCD0_CCCBUF _SFR_MEM16(0x093C) -#define TCD0_CCDBUF _SFR_MEM16(0x093E) - -/* TC2 - 16-bit Timer/Counter type 2 */ -#define TCD2_CTRLA _SFR_MEM8(0x0900) -#define TCD2_CTRLB _SFR_MEM8(0x0901) -#define TCD2_CTRLC _SFR_MEM8(0x0902) -#define TCD2_CTRLE _SFR_MEM8(0x0904) -#define TCD2_INTCTRLA _SFR_MEM8(0x0906) -#define TCD2_INTCTRLB _SFR_MEM8(0x0907) -#define TCD2_CTRLF _SFR_MEM8(0x0909) -#define TCD2_INTFLAGS _SFR_MEM8(0x090C) -#define TCD2_LCNT _SFR_MEM8(0x0920) -#define TCD2_HCNT _SFR_MEM8(0x0921) -#define TCD2_LPER _SFR_MEM8(0x0926) -#define TCD2_HPER _SFR_MEM8(0x0927) -#define TCD2_LCMPA _SFR_MEM8(0x0928) -#define TCD2_HCMPA _SFR_MEM8(0x0929) -#define TCD2_LCMPB _SFR_MEM8(0x092A) -#define TCD2_HCMPB _SFR_MEM8(0x092B) -#define TCD2_LCMPC _SFR_MEM8(0x092C) -#define TCD2_HCMPC _SFR_MEM8(0x092D) -#define TCD2_LCMPD _SFR_MEM8(0x092E) -#define TCD2_HCMPD _SFR_MEM8(0x092F) - -/* TC1 - 16-bit Timer/Counter 1 */ -#define TCD1_CTRLA _SFR_MEM8(0x0940) -#define TCD1_CTRLB _SFR_MEM8(0x0941) -#define TCD1_CTRLC _SFR_MEM8(0x0942) -#define TCD1_CTRLD _SFR_MEM8(0x0943) -#define TCD1_CTRLE _SFR_MEM8(0x0944) -#define TCD1_INTCTRLA _SFR_MEM8(0x0946) -#define TCD1_INTCTRLB _SFR_MEM8(0x0947) -#define TCD1_CTRLFCLR _SFR_MEM8(0x0948) -#define TCD1_CTRLFSET _SFR_MEM8(0x0949) -#define TCD1_CTRLGCLR _SFR_MEM8(0x094A) -#define TCD1_CTRLGSET _SFR_MEM8(0x094B) -#define TCD1_INTFLAGS _SFR_MEM8(0x094C) -#define TCD1_TEMP _SFR_MEM8(0x094F) -#define TCD1_CNT _SFR_MEM16(0x0960) -#define TCD1_PER _SFR_MEM16(0x0966) -#define TCD1_CCA _SFR_MEM16(0x0968) -#define TCD1_CCB _SFR_MEM16(0x096A) -#define TCD1_PERBUF _SFR_MEM16(0x0976) -#define TCD1_CCABUF _SFR_MEM16(0x0978) -#define TCD1_CCBBUF _SFR_MEM16(0x097A) - -/* HIRES - High-Resolution Extension */ -#define HIRESD_CTRLA _SFR_MEM8(0x0990) - -/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ -#define USARTD0_DATA _SFR_MEM8(0x09A0) -#define USARTD0_STATUS _SFR_MEM8(0x09A1) -#define USARTD0_CTRLA _SFR_MEM8(0x09A3) -#define USARTD0_CTRLB _SFR_MEM8(0x09A4) -#define USARTD0_CTRLC _SFR_MEM8(0x09A5) -#define USARTD0_BAUDCTRLA _SFR_MEM8(0x09A6) -#define USARTD0_BAUDCTRLB _SFR_MEM8(0x09A7) - -/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ -#define USARTD1_DATA _SFR_MEM8(0x09B0) -#define USARTD1_STATUS _SFR_MEM8(0x09B1) -#define USARTD1_CTRLA _SFR_MEM8(0x09B3) -#define USARTD1_CTRLB _SFR_MEM8(0x09B4) -#define USARTD1_CTRLC _SFR_MEM8(0x09B5) -#define USARTD1_BAUDCTRLA _SFR_MEM8(0x09B6) -#define USARTD1_BAUDCTRLB _SFR_MEM8(0x09B7) - -/* SPI - Serial Peripheral Interface */ -#define SPID_CTRL _SFR_MEM8(0x09C0) -#define SPID_INTCTRL _SFR_MEM8(0x09C1) -#define SPID_STATUS _SFR_MEM8(0x09C2) -#define SPID_DATA _SFR_MEM8(0x09C3) - -/* TC0 - 16-bit Timer/Counter 0 */ -#define TCE0_CTRLA _SFR_MEM8(0x0A00) -#define TCE0_CTRLB _SFR_MEM8(0x0A01) -#define TCE0_CTRLC _SFR_MEM8(0x0A02) -#define TCE0_CTRLD _SFR_MEM8(0x0A03) -#define TCE0_CTRLE _SFR_MEM8(0x0A04) -#define TCE0_INTCTRLA _SFR_MEM8(0x0A06) -#define TCE0_INTCTRLB _SFR_MEM8(0x0A07) -#define TCE0_CTRLFCLR _SFR_MEM8(0x0A08) -#define TCE0_CTRLFSET _SFR_MEM8(0x0A09) -#define TCE0_CTRLGCLR _SFR_MEM8(0x0A0A) -#define TCE0_CTRLGSET _SFR_MEM8(0x0A0B) -#define TCE0_INTFLAGS _SFR_MEM8(0x0A0C) -#define TCE0_TEMP _SFR_MEM8(0x0A0F) -#define TCE0_CNT _SFR_MEM16(0x0A20) -#define TCE0_PER _SFR_MEM16(0x0A26) -#define TCE0_CCA _SFR_MEM16(0x0A28) -#define TCE0_CCB _SFR_MEM16(0x0A2A) -#define TCE0_CCC _SFR_MEM16(0x0A2C) -#define TCE0_CCD _SFR_MEM16(0x0A2E) -#define TCE0_PERBUF _SFR_MEM16(0x0A36) -#define TCE0_CCABUF _SFR_MEM16(0x0A38) -#define TCE0_CCBBUF _SFR_MEM16(0x0A3A) -#define TCE0_CCCBUF _SFR_MEM16(0x0A3C) -#define TCE0_CCDBUF _SFR_MEM16(0x0A3E) - -/* TC2 - 16-bit Timer/Counter type 2 */ -#define TCE2_CTRLA _SFR_MEM8(0x0A00) -#define TCE2_CTRLB _SFR_MEM8(0x0A01) -#define TCE2_CTRLC _SFR_MEM8(0x0A02) -#define TCE2_CTRLE _SFR_MEM8(0x0A04) -#define TCE2_INTCTRLA _SFR_MEM8(0x0A06) -#define TCE2_INTCTRLB _SFR_MEM8(0x0A07) -#define TCE2_CTRLF _SFR_MEM8(0x0A09) -#define TCE2_INTFLAGS _SFR_MEM8(0x0A0C) -#define TCE2_LCNT _SFR_MEM8(0x0A20) -#define TCE2_HCNT _SFR_MEM8(0x0A21) -#define TCE2_LPER _SFR_MEM8(0x0A26) -#define TCE2_HPER _SFR_MEM8(0x0A27) -#define TCE2_LCMPA _SFR_MEM8(0x0A28) -#define TCE2_HCMPA _SFR_MEM8(0x0A29) -#define TCE2_LCMPB _SFR_MEM8(0x0A2A) -#define TCE2_HCMPB _SFR_MEM8(0x0A2B) -#define TCE2_LCMPC _SFR_MEM8(0x0A2C) -#define TCE2_HCMPC _SFR_MEM8(0x0A2D) -#define TCE2_LCMPD _SFR_MEM8(0x0A2E) -#define TCE2_HCMPD _SFR_MEM8(0x0A2F) - -/* TC1 - 16-bit Timer/Counter 1 */ -#define TCE1_CTRLA _SFR_MEM8(0x0A40) -#define TCE1_CTRLB _SFR_MEM8(0x0A41) -#define TCE1_CTRLC _SFR_MEM8(0x0A42) -#define TCE1_CTRLD _SFR_MEM8(0x0A43) -#define TCE1_CTRLE _SFR_MEM8(0x0A44) -#define TCE1_INTCTRLA _SFR_MEM8(0x0A46) -#define TCE1_INTCTRLB _SFR_MEM8(0x0A47) -#define TCE1_CTRLFCLR _SFR_MEM8(0x0A48) -#define TCE1_CTRLFSET _SFR_MEM8(0x0A49) -#define TCE1_CTRLGCLR _SFR_MEM8(0x0A4A) -#define TCE1_CTRLGSET _SFR_MEM8(0x0A4B) -#define TCE1_INTFLAGS _SFR_MEM8(0x0A4C) -#define TCE1_TEMP _SFR_MEM8(0x0A4F) -#define TCE1_CNT _SFR_MEM16(0x0A60) -#define TCE1_PER _SFR_MEM16(0x0A66) -#define TCE1_CCA _SFR_MEM16(0x0A68) -#define TCE1_CCB _SFR_MEM16(0x0A6A) -#define TCE1_PERBUF _SFR_MEM16(0x0A76) -#define TCE1_CCABUF _SFR_MEM16(0x0A78) -#define TCE1_CCBBUF _SFR_MEM16(0x0A7A) - -/* AWEX - Advanced Waveform Extension */ -#define AWEXE_CTRL _SFR_MEM8(0x0A80) -#define AWEXE_FDEMASK _SFR_MEM8(0x0A82) -#define AWEXE_FDCTRL _SFR_MEM8(0x0A83) -#define AWEXE_STATUS _SFR_MEM8(0x0A84) -#define AWEXE_STATUSSET _SFR_MEM8(0x0A85) -#define AWEXE_DTBOTH _SFR_MEM8(0x0A86) -#define AWEXE_DTBOTHBUF _SFR_MEM8(0x0A87) -#define AWEXE_DTLS _SFR_MEM8(0x0A88) -#define AWEXE_DTHS _SFR_MEM8(0x0A89) -#define AWEXE_DTLSBUF _SFR_MEM8(0x0A8A) -#define AWEXE_DTHSBUF _SFR_MEM8(0x0A8B) -#define AWEXE_OUTOVEN _SFR_MEM8(0x0A8C) - -/* HIRES - High-Resolution Extension */ -#define HIRESE_CTRLA _SFR_MEM8(0x0A90) - -/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ -#define USARTE0_DATA _SFR_MEM8(0x0AA0) -#define USARTE0_STATUS _SFR_MEM8(0x0AA1) -#define USARTE0_CTRLA _SFR_MEM8(0x0AA3) -#define USARTE0_CTRLB _SFR_MEM8(0x0AA4) -#define USARTE0_CTRLC _SFR_MEM8(0x0AA5) -#define USARTE0_BAUDCTRLA _SFR_MEM8(0x0AA6) -#define USARTE0_BAUDCTRLB _SFR_MEM8(0x0AA7) - -/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ -#define USARTE1_DATA _SFR_MEM8(0x0AB0) -#define USARTE1_STATUS _SFR_MEM8(0x0AB1) -#define USARTE1_CTRLA _SFR_MEM8(0x0AB3) -#define USARTE1_CTRLB _SFR_MEM8(0x0AB4) -#define USARTE1_CTRLC _SFR_MEM8(0x0AB5) -#define USARTE1_BAUDCTRLA _SFR_MEM8(0x0AB6) -#define USARTE1_BAUDCTRLB _SFR_MEM8(0x0AB7) - -/* SPI - Serial Peripheral Interface */ -#define SPIE_CTRL _SFR_MEM8(0x0AC0) -#define SPIE_INTCTRL _SFR_MEM8(0x0AC1) -#define SPIE_STATUS _SFR_MEM8(0x0AC2) -#define SPIE_DATA _SFR_MEM8(0x0AC3) - -/* TC0 - 16-bit Timer/Counter 0 */ -#define TCF0_CTRLA _SFR_MEM8(0x0B00) -#define TCF0_CTRLB _SFR_MEM8(0x0B01) -#define TCF0_CTRLC _SFR_MEM8(0x0B02) -#define TCF0_CTRLD _SFR_MEM8(0x0B03) -#define TCF0_CTRLE _SFR_MEM8(0x0B04) -#define TCF0_INTCTRLA _SFR_MEM8(0x0B06) -#define TCF0_INTCTRLB _SFR_MEM8(0x0B07) -#define TCF0_CTRLFCLR _SFR_MEM8(0x0B08) -#define TCF0_CTRLFSET _SFR_MEM8(0x0B09) -#define TCF0_CTRLGCLR _SFR_MEM8(0x0B0A) -#define TCF0_CTRLGSET _SFR_MEM8(0x0B0B) -#define TCF0_INTFLAGS _SFR_MEM8(0x0B0C) -#define TCF0_TEMP _SFR_MEM8(0x0B0F) -#define TCF0_CNT _SFR_MEM16(0x0B20) -#define TCF0_PER _SFR_MEM16(0x0B26) -#define TCF0_CCA _SFR_MEM16(0x0B28) -#define TCF0_CCB _SFR_MEM16(0x0B2A) -#define TCF0_CCC _SFR_MEM16(0x0B2C) -#define TCF0_CCD _SFR_MEM16(0x0B2E) -#define TCF0_PERBUF _SFR_MEM16(0x0B36) -#define TCF0_CCABUF _SFR_MEM16(0x0B38) -#define TCF0_CCBBUF _SFR_MEM16(0x0B3A) -#define TCF0_CCCBUF _SFR_MEM16(0x0B3C) -#define TCF0_CCDBUF _SFR_MEM16(0x0B3E) - -/* TC2 - 16-bit Timer/Counter type 2 */ -#define TCF2_CTRLA _SFR_MEM8(0x0B00) -#define TCF2_CTRLB _SFR_MEM8(0x0B01) -#define TCF2_CTRLC _SFR_MEM8(0x0B02) -#define TCF2_CTRLE _SFR_MEM8(0x0B04) -#define TCF2_INTCTRLA _SFR_MEM8(0x0B06) -#define TCF2_INTCTRLB _SFR_MEM8(0x0B07) -#define TCF2_CTRLF _SFR_MEM8(0x0B09) -#define TCF2_INTFLAGS _SFR_MEM8(0x0B0C) -#define TCF2_LCNT _SFR_MEM8(0x0B20) -#define TCF2_HCNT _SFR_MEM8(0x0B21) -#define TCF2_LPER _SFR_MEM8(0x0B26) -#define TCF2_HPER _SFR_MEM8(0x0B27) -#define TCF2_LCMPA _SFR_MEM8(0x0B28) -#define TCF2_HCMPA _SFR_MEM8(0x0B29) -#define TCF2_LCMPB _SFR_MEM8(0x0B2A) -#define TCF2_HCMPB _SFR_MEM8(0x0B2B) -#define TCF2_LCMPC _SFR_MEM8(0x0B2C) -#define TCF2_HCMPC _SFR_MEM8(0x0B2D) -#define TCF2_LCMPD _SFR_MEM8(0x0B2E) -#define TCF2_HCMPD _SFR_MEM8(0x0B2F) - -/* HIRES - High-Resolution Extension */ -#define HIRESF_CTRLA _SFR_MEM8(0x0B90) - -/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ -#define USARTF0_DATA _SFR_MEM8(0x0BA0) -#define USARTF0_STATUS _SFR_MEM8(0x0BA1) -#define USARTF0_CTRLA _SFR_MEM8(0x0BA3) -#define USARTF0_CTRLB _SFR_MEM8(0x0BA4) -#define USARTF0_CTRLC _SFR_MEM8(0x0BA5) -#define USARTF0_BAUDCTRLA _SFR_MEM8(0x0BA6) -#define USARTF0_BAUDCTRLB _SFR_MEM8(0x0BA7) - - - -/*================== Bitfield Definitions ================== */ - -/* VPORT - Virtual Ports */ -/* VPORT.INTFLAGS bit masks and bit positions */ -#define VPORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ -#define VPORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ - -#define VPORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ -#define VPORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ - -/* XOCD - On-Chip Debug System */ -/* OCD.OCDR0 bit masks and bit positions */ -#define OCD_OCDRD_gm 0xFF /* OCDR Dirty group mask. */ -#define OCD_OCDRD_gp 0 /* OCDR Dirty group position. */ -#define OCD_OCDRD0_bm (1<<0) /* OCDR Dirty bit 0 mask. */ -#define OCD_OCDRD0_bp 0 /* OCDR Dirty bit 0 position. */ -#define OCD_OCDRD1_bm (1<<1) /* OCDR Dirty bit 1 mask. */ -#define OCD_OCDRD1_bp 1 /* OCDR Dirty bit 1 position. */ -#define OCD_OCDRD2_bm (1<<2) /* OCDR Dirty bit 2 mask. */ -#define OCD_OCDRD2_bp 2 /* OCDR Dirty bit 2 position. */ -#define OCD_OCDRD3_bm (1<<3) /* OCDR Dirty bit 3 mask. */ -#define OCD_OCDRD3_bp 3 /* OCDR Dirty bit 3 position. */ -#define OCD_OCDRD4_bm (1<<4) /* OCDR Dirty bit 4 mask. */ -#define OCD_OCDRD4_bp 4 /* OCDR Dirty bit 4 position. */ -#define OCD_OCDRD5_bm (1<<5) /* OCDR Dirty bit 5 mask. */ -#define OCD_OCDRD5_bp 5 /* OCDR Dirty bit 5 position. */ -#define OCD_OCDRD6_bm (1<<6) /* OCDR Dirty bit 6 mask. */ -#define OCD_OCDRD6_bp 6 /* OCDR Dirty bit 6 position. */ -#define OCD_OCDRD7_bm (1<<7) /* OCDR Dirty bit 7 mask. */ -#define OCD_OCDRD7_bp 7 /* OCDR Dirty bit 7 position. */ - -/* OCD.OCDR1 bit masks and bit positions */ -/* OCD_OCDRD Predefined. */ -/* OCD_OCDRD Predefined. */ - -/* CPU - CPU */ -/* CPU.CCP bit masks and bit positions */ -#define CPU_CCP_gm 0xFF /* CCP signature group mask. */ -#define CPU_CCP_gp 0 /* CCP signature group position. */ -#define CPU_CCP0_bm (1<<0) /* CCP signature bit 0 mask. */ -#define CPU_CCP0_bp 0 /* CCP signature bit 0 position. */ -#define CPU_CCP1_bm (1<<1) /* CCP signature bit 1 mask. */ -#define CPU_CCP1_bp 1 /* CCP signature bit 1 position. */ -#define CPU_CCP2_bm (1<<2) /* CCP signature bit 2 mask. */ -#define CPU_CCP2_bp 2 /* CCP signature bit 2 position. */ -#define CPU_CCP3_bm (1<<3) /* CCP signature bit 3 mask. */ -#define CPU_CCP3_bp 3 /* CCP signature bit 3 position. */ -#define CPU_CCP4_bm (1<<4) /* CCP signature bit 4 mask. */ -#define CPU_CCP4_bp 4 /* CCP signature bit 4 position. */ -#define CPU_CCP5_bm (1<<5) /* CCP signature bit 5 mask. */ -#define CPU_CCP5_bp 5 /* CCP signature bit 5 position. */ -#define CPU_CCP6_bm (1<<6) /* CCP signature bit 6 mask. */ -#define CPU_CCP6_bp 6 /* CCP signature bit 6 position. */ -#define CPU_CCP7_bm (1<<7) /* CCP signature bit 7 mask. */ -#define CPU_CCP7_bp 7 /* CCP signature bit 7 position. */ - -/* CPU.SREG bit masks and bit positions */ -#define CPU_I_bm 0x80 /* Global Interrupt Enable Flag bit mask. */ -#define CPU_I_bp 7 /* Global Interrupt Enable Flag bit position. */ - -#define CPU_T_bm 0x40 /* Transfer Bit bit mask. */ -#define CPU_T_bp 6 /* Transfer Bit bit position. */ - -#define CPU_H_bm 0x20 /* Half Carry Flag bit mask. */ -#define CPU_H_bp 5 /* Half Carry Flag bit position. */ - -#define CPU_S_bm 0x10 /* N Exclusive Or V Flag bit mask. */ -#define CPU_S_bp 4 /* N Exclusive Or V Flag bit position. */ - -#define CPU_V_bm 0x08 /* Two's Complement Overflow Flag bit mask. */ -#define CPU_V_bp 3 /* Two's Complement Overflow Flag bit position. */ - -#define CPU_N_bm 0x04 /* Negative Flag bit mask. */ -#define CPU_N_bp 2 /* Negative Flag bit position. */ - -#define CPU_Z_bm 0x02 /* Zero Flag bit mask. */ -#define CPU_Z_bp 1 /* Zero Flag bit position. */ - -#define CPU_C_bm 0x01 /* Carry Flag bit mask. */ -#define CPU_C_bp 0 /* Carry Flag bit position. */ - -/* CLK - Clock System */ -/* CLK.CTRL bit masks and bit positions */ -#define CLK_SCLKSEL_gm 0x07 /* System Clock Selection group mask. */ -#define CLK_SCLKSEL_gp 0 /* System Clock Selection group position. */ -#define CLK_SCLKSEL0_bm (1<<0) /* System Clock Selection bit 0 mask. */ -#define CLK_SCLKSEL0_bp 0 /* System Clock Selection bit 0 position. */ -#define CLK_SCLKSEL1_bm (1<<1) /* System Clock Selection bit 1 mask. */ -#define CLK_SCLKSEL1_bp 1 /* System Clock Selection bit 1 position. */ -#define CLK_SCLKSEL2_bm (1<<2) /* System Clock Selection bit 2 mask. */ -#define CLK_SCLKSEL2_bp 2 /* System Clock Selection bit 2 position. */ - -/* CLK.PSCTRL bit masks and bit positions */ -#define CLK_PSADIV_gm 0x7C /* Prescaler A Division Factor group mask. */ -#define CLK_PSADIV_gp 2 /* Prescaler A Division Factor group position. */ -#define CLK_PSADIV0_bm (1<<2) /* Prescaler A Division Factor bit 0 mask. */ -#define CLK_PSADIV0_bp 2 /* Prescaler A Division Factor bit 0 position. */ -#define CLK_PSADIV1_bm (1<<3) /* Prescaler A Division Factor bit 1 mask. */ -#define CLK_PSADIV1_bp 3 /* Prescaler A Division Factor bit 1 position. */ -#define CLK_PSADIV2_bm (1<<4) /* Prescaler A Division Factor bit 2 mask. */ -#define CLK_PSADIV2_bp 4 /* Prescaler A Division Factor bit 2 position. */ -#define CLK_PSADIV3_bm (1<<5) /* Prescaler A Division Factor bit 3 mask. */ -#define CLK_PSADIV3_bp 5 /* Prescaler A Division Factor bit 3 position. */ -#define CLK_PSADIV4_bm (1<<6) /* Prescaler A Division Factor bit 4 mask. */ -#define CLK_PSADIV4_bp 6 /* Prescaler A Division Factor bit 4 position. */ - -#define CLK_PSBCDIV_gm 0x03 /* Prescaler B and C Division factor group mask. */ -#define CLK_PSBCDIV_gp 0 /* Prescaler B and C Division factor group position. */ -#define CLK_PSBCDIV0_bm (1<<0) /* Prescaler B and C Division factor bit 0 mask. */ -#define CLK_PSBCDIV0_bp 0 /* Prescaler B and C Division factor bit 0 position. */ -#define CLK_PSBCDIV1_bm (1<<1) /* Prescaler B and C Division factor bit 1 mask. */ -#define CLK_PSBCDIV1_bp 1 /* Prescaler B and C Division factor bit 1 position. */ - -/* CLK.LOCK bit masks and bit positions */ -#define CLK_LOCK_bm 0x01 /* Clock System Lock bit mask. */ -#define CLK_LOCK_bp 0 /* Clock System Lock bit position. */ - -/* CLK.RTCCTRL bit masks and bit positions */ -#define CLK_RTCSRC_gm 0x0E /* Clock Source group mask. */ -#define CLK_RTCSRC_gp 1 /* Clock Source group position. */ -#define CLK_RTCSRC0_bm (1<<1) /* Clock Source bit 0 mask. */ -#define CLK_RTCSRC0_bp 1 /* Clock Source bit 0 position. */ -#define CLK_RTCSRC1_bm (1<<2) /* Clock Source bit 1 mask. */ -#define CLK_RTCSRC1_bp 2 /* Clock Source bit 1 position. */ -#define CLK_RTCSRC2_bm (1<<3) /* Clock Source bit 2 mask. */ -#define CLK_RTCSRC2_bp 3 /* Clock Source bit 2 position. */ - -#define CLK_RTCEN_bm 0x01 /* Clock Source Enable bit mask. */ -#define CLK_RTCEN_bp 0 /* Clock Source Enable bit position. */ - -/* CLK.USBCTRL bit masks and bit positions */ -#define CLK_USBPSDIV_gm 0x38 /* Prescaler Division Factor group mask. */ -#define CLK_USBPSDIV_gp 3 /* Prescaler Division Factor group position. */ -#define CLK_USBPSDIV0_bm (1<<3) /* Prescaler Division Factor bit 0 mask. */ -#define CLK_USBPSDIV0_bp 3 /* Prescaler Division Factor bit 0 position. */ -#define CLK_USBPSDIV1_bm (1<<4) /* Prescaler Division Factor bit 1 mask. */ -#define CLK_USBPSDIV1_bp 4 /* Prescaler Division Factor bit 1 position. */ -#define CLK_USBPSDIV2_bm (1<<5) /* Prescaler Division Factor bit 2 mask. */ -#define CLK_USBPSDIV2_bp 5 /* Prescaler Division Factor bit 2 position. */ - -#define CLK_USBSRC_gm 0x06 /* Clock Source group mask. */ -#define CLK_USBSRC_gp 1 /* Clock Source group position. */ -#define CLK_USBSRC0_bm (1<<1) /* Clock Source bit 0 mask. */ -#define CLK_USBSRC0_bp 1 /* Clock Source bit 0 position. */ -#define CLK_USBSRC1_bm (1<<2) /* Clock Source bit 1 mask. */ -#define CLK_USBSRC1_bp 2 /* Clock Source bit 1 position. */ - -#define CLK_USBSEN_bm 0x01 /* Clock Source Enable bit mask. */ -#define CLK_USBSEN_bp 0 /* Clock Source Enable bit position. */ - -/* PR.PRGEN bit masks and bit positions */ -#define PR_USB_bm 0x40 /* USB bit mask. */ -#define PR_USB_bp 6 /* USB bit position. */ - -#define PR_AES_bm 0x10 /* AES bit mask. */ -#define PR_AES_bp 4 /* AES bit position. */ - -#define PR_EBI_bm 0x08 /* External Bus Interface bit mask. */ -#define PR_EBI_bp 3 /* External Bus Interface bit position. */ - -#define PR_RTC_bm 0x04 /* Real-time Counter bit mask. */ -#define PR_RTC_bp 2 /* Real-time Counter bit position. */ - -#define PR_EVSYS_bm 0x02 /* Event System bit mask. */ -#define PR_EVSYS_bp 1 /* Event System bit position. */ - -#define PR_DMA_bm 0x01 /* DMA-Controller bit mask. */ -#define PR_DMA_bp 0 /* DMA-Controller bit position. */ - -/* PR.PRPA bit masks and bit positions */ -#define PR_DAC_bm 0x04 /* Port A DAC bit mask. */ -#define PR_DAC_bp 2 /* Port A DAC bit position. */ - -#define PR_ADC_bm 0x02 /* Port A ADC bit mask. */ -#define PR_ADC_bp 1 /* Port A ADC bit position. */ - -#define PR_AC_bm 0x01 /* Port A Analog Comparator bit mask. */ -#define PR_AC_bp 0 /* Port A Analog Comparator bit position. */ - -/* PR.PRPB bit masks and bit positions */ -/* PR_DAC Predefined. */ -/* PR_DAC Predefined. */ - -/* PR_ADC Predefined. */ -/* PR_ADC Predefined. */ - -/* PR_AC Predefined. */ -/* PR_AC Predefined. */ - -/* PR.PRPC bit masks and bit positions */ -#define PR_TWI_bm 0x40 /* Port C Two-wire Interface bit mask. */ -#define PR_TWI_bp 6 /* Port C Two-wire Interface bit position. */ - -#define PR_USART1_bm 0x20 /* Port C USART1 bit mask. */ -#define PR_USART1_bp 5 /* Port C USART1 bit position. */ - -#define PR_USART0_bm 0x10 /* Port C USART0 bit mask. */ -#define PR_USART0_bp 4 /* Port C USART0 bit position. */ - -#define PR_SPI_bm 0x08 /* Port C SPI bit mask. */ -#define PR_SPI_bp 3 /* Port C SPI bit position. */ - -#define PR_HIRES_bm 0x04 /* Port C AWEX bit mask. */ -#define PR_HIRES_bp 2 /* Port C AWEX bit position. */ - -#define PR_TC1_bm 0x02 /* Port C Timer/Counter1 bit mask. */ -#define PR_TC1_bp 1 /* Port C Timer/Counter1 bit position. */ - -#define PR_TC0_bm 0x01 /* Port C Timer/Counter0 bit mask. */ -#define PR_TC0_bp 0 /* Port C Timer/Counter0 bit position. */ - -/* PR.PRPD bit masks and bit positions */ -/* PR_TWI Predefined. */ -/* PR_TWI Predefined. */ - -/* PR_USART1 Predefined. */ -/* PR_USART1 Predefined. */ - -/* PR_USART0 Predefined. */ -/* PR_USART0 Predefined. */ - -/* PR_SPI Predefined. */ -/* PR_SPI Predefined. */ - -/* PR_HIRES Predefined. */ -/* PR_HIRES Predefined. */ - -/* PR_TC1 Predefined. */ -/* PR_TC1 Predefined. */ - -/* PR_TC0 Predefined. */ -/* PR_TC0 Predefined. */ - -/* PR.PRPE bit masks and bit positions */ -/* PR_TWI Predefined. */ -/* PR_TWI Predefined. */ - -/* PR_USART1 Predefined. */ -/* PR_USART1 Predefined. */ - -/* PR_USART0 Predefined. */ -/* PR_USART0 Predefined. */ - -/* PR_SPI Predefined. */ -/* PR_SPI Predefined. */ - -/* PR_HIRES Predefined. */ -/* PR_HIRES Predefined. */ - -/* PR_TC1 Predefined. */ -/* PR_TC1 Predefined. */ - -/* PR_TC0 Predefined. */ -/* PR_TC0 Predefined. */ - -/* PR.PRPF bit masks and bit positions */ -/* PR_TWI Predefined. */ -/* PR_TWI Predefined. */ - -/* PR_USART1 Predefined. */ -/* PR_USART1 Predefined. */ - -/* PR_USART0 Predefined. */ -/* PR_USART0 Predefined. */ - -/* PR_SPI Predefined. */ -/* PR_SPI Predefined. */ - -/* PR_HIRES Predefined. */ -/* PR_HIRES Predefined. */ - -/* PR_TC1 Predefined. */ -/* PR_TC1 Predefined. */ - -/* PR_TC0 Predefined. */ -/* PR_TC0 Predefined. */ - -/* SLEEP - Sleep Controller */ -/* SLEEP.CTRL bit masks and bit positions */ -#define SLEEP_SMODE_gm 0x0E /* Sleep Mode group mask. */ -#define SLEEP_SMODE_gp 1 /* Sleep Mode group position. */ -#define SLEEP_SMODE0_bm (1<<1) /* Sleep Mode bit 0 mask. */ -#define SLEEP_SMODE0_bp 1 /* Sleep Mode bit 0 position. */ -#define SLEEP_SMODE1_bm (1<<2) /* Sleep Mode bit 1 mask. */ -#define SLEEP_SMODE1_bp 2 /* Sleep Mode bit 1 position. */ -#define SLEEP_SMODE2_bm (1<<3) /* Sleep Mode bit 2 mask. */ -#define SLEEP_SMODE2_bp 3 /* Sleep Mode bit 2 position. */ - -#define SLEEP_SEN_bm 0x01 /* Sleep Enable bit mask. */ -#define SLEEP_SEN_bp 0 /* Sleep Enable bit position. */ - -/* OSC - Oscillator */ -/* OSC.CTRL bit masks and bit positions */ -#define OSC_PLLEN_bm 0x10 /* PLL Enable bit mask. */ -#define OSC_PLLEN_bp 4 /* PLL Enable bit position. */ - -#define OSC_XOSCEN_bm 0x08 /* External Oscillator Enable bit mask. */ -#define OSC_XOSCEN_bp 3 /* External Oscillator Enable bit position. */ - -#define OSC_RC32KEN_bm 0x04 /* Internal 32.768 kHz RC Oscillator Enable bit mask. */ -#define OSC_RC32KEN_bp 2 /* Internal 32.768 kHz RC Oscillator Enable bit position. */ - -#define OSC_RC32MEN_bm 0x02 /* Internal 32 MHz RC Oscillator Enable bit mask. */ -#define OSC_RC32MEN_bp 1 /* Internal 32 MHz RC Oscillator Enable bit position. */ - -#define OSC_RC2MEN_bm 0x01 /* Internal 2 MHz RC Oscillator Enable bit mask. */ -#define OSC_RC2MEN_bp 0 /* Internal 2 MHz RC Oscillator Enable bit position. */ - -/* OSC.STATUS bit masks and bit positions */ -#define OSC_PLLRDY_bm 0x10 /* PLL Ready bit mask. */ -#define OSC_PLLRDY_bp 4 /* PLL Ready bit position. */ - -#define OSC_XOSCRDY_bm 0x08 /* External Oscillator Ready bit mask. */ -#define OSC_XOSCRDY_bp 3 /* External Oscillator Ready bit position. */ - -#define OSC_RC32KRDY_bm 0x04 /* Internal 32.768 kHz RC Oscillator Ready bit mask. */ -#define OSC_RC32KRDY_bp 2 /* Internal 32.768 kHz RC Oscillator Ready bit position. */ - -#define OSC_RC32MRDY_bm 0x02 /* Internal 32 MHz RC Oscillator Ready bit mask. */ -#define OSC_RC32MRDY_bp 1 /* Internal 32 MHz RC Oscillator Ready bit position. */ - -#define OSC_RC2MRDY_bm 0x01 /* Internal 2 MHz RC Oscillator Ready bit mask. */ -#define OSC_RC2MRDY_bp 0 /* Internal 2 MHz RC Oscillator Ready bit position. */ - -/* OSC.XOSCCTRL bit masks and bit positions */ -#define OSC_FRQRANGE_gm 0xC0 /* Frequency Range group mask. */ -#define OSC_FRQRANGE_gp 6 /* Frequency Range group position. */ -#define OSC_FRQRANGE0_bm (1<<6) /* Frequency Range bit 0 mask. */ -#define OSC_FRQRANGE0_bp 6 /* Frequency Range bit 0 position. */ -#define OSC_FRQRANGE1_bm (1<<7) /* Frequency Range bit 1 mask. */ -#define OSC_FRQRANGE1_bp 7 /* Frequency Range bit 1 position. */ - -#define OSC_X32KLPM_bm 0x20 /* 32.768 kHz XTAL OSC Low-power Mode bit mask. */ -#define OSC_X32KLPM_bp 5 /* 32.768 kHz XTAL OSC Low-power Mode bit position. */ - -#define OSC_XOSCPWR_bm 0x10 /* 16 MHz Crystal Oscillator High Power mode bit mask. */ -#define OSC_XOSCPWR_bp 4 /* 16 MHz Crystal Oscillator High Power mode bit position. */ - -#define OSC_XOSCSEL_gm 0x0F /* External Oscillator Selection and Startup Time group mask. */ -#define OSC_XOSCSEL_gp 0 /* External Oscillator Selection and Startup Time group position. */ -#define OSC_XOSCSEL0_bm (1<<0) /* External Oscillator Selection and Startup Time bit 0 mask. */ -#define OSC_XOSCSEL0_bp 0 /* External Oscillator Selection and Startup Time bit 0 position. */ -#define OSC_XOSCSEL1_bm (1<<1) /* External Oscillator Selection and Startup Time bit 1 mask. */ -#define OSC_XOSCSEL1_bp 1 /* External Oscillator Selection and Startup Time bit 1 position. */ -#define OSC_XOSCSEL2_bm (1<<2) /* External Oscillator Selection and Startup Time bit 2 mask. */ -#define OSC_XOSCSEL2_bp 2 /* External Oscillator Selection and Startup Time bit 2 position. */ -#define OSC_XOSCSEL3_bm (1<<3) /* External Oscillator Selection and Startup Time bit 3 mask. */ -#define OSC_XOSCSEL3_bp 3 /* External Oscillator Selection and Startup Time bit 3 position. */ - -/* OSC.XOSCFAIL bit masks and bit positions */ -#define OSC_PLLFDIF_bm 0x08 /* PLL Failure Detection Interrupt Flag bit mask. */ -#define OSC_PLLFDIF_bp 3 /* PLL Failure Detection Interrupt Flag bit position. */ - -#define OSC_PLLFDEN_bm 0x04 /* PLL Failure Detection Enable bit mask. */ -#define OSC_PLLFDEN_bp 2 /* PLL Failure Detection Enable bit position. */ - -#define OSC_XOSCFDIF_bm 0x02 /* XOSC Failure Detection Interrupt Flag bit mask. */ -#define OSC_XOSCFDIF_bp 1 /* XOSC Failure Detection Interrupt Flag bit position. */ - -#define OSC_XOSCFDEN_bm 0x01 /* XOSC Failure Detection Enable bit mask. */ -#define OSC_XOSCFDEN_bp 0 /* XOSC Failure Detection Enable bit position. */ - -/* OSC.PLLCTRL bit masks and bit positions */ -#define OSC_PLLSRC_gm 0xC0 /* Clock Source group mask. */ -#define OSC_PLLSRC_gp 6 /* Clock Source group position. */ -#define OSC_PLLSRC0_bm (1<<6) /* Clock Source bit 0 mask. */ -#define OSC_PLLSRC0_bp 6 /* Clock Source bit 0 position. */ -#define OSC_PLLSRC1_bm (1<<7) /* Clock Source bit 1 mask. */ -#define OSC_PLLSRC1_bp 7 /* Clock Source bit 1 position. */ - -#define OSC_PLLDIV_bm 0x20 /* Divide by 2 bit mask. */ -#define OSC_PLLDIV_bp 5 /* Divide by 2 bit position. */ - -#define OSC_PLLFAC_gm 0x1F /* Multiplication Factor group mask. */ -#define OSC_PLLFAC_gp 0 /* Multiplication Factor group position. */ -#define OSC_PLLFAC0_bm (1<<0) /* Multiplication Factor bit 0 mask. */ -#define OSC_PLLFAC0_bp 0 /* Multiplication Factor bit 0 position. */ -#define OSC_PLLFAC1_bm (1<<1) /* Multiplication Factor bit 1 mask. */ -#define OSC_PLLFAC1_bp 1 /* Multiplication Factor bit 1 position. */ -#define OSC_PLLFAC2_bm (1<<2) /* Multiplication Factor bit 2 mask. */ -#define OSC_PLLFAC2_bp 2 /* Multiplication Factor bit 2 position. */ -#define OSC_PLLFAC3_bm (1<<3) /* Multiplication Factor bit 3 mask. */ -#define OSC_PLLFAC3_bp 3 /* Multiplication Factor bit 3 position. */ -#define OSC_PLLFAC4_bm (1<<4) /* Multiplication Factor bit 4 mask. */ -#define OSC_PLLFAC4_bp 4 /* Multiplication Factor bit 4 position. */ - -/* OSC.DFLLCTRL bit masks and bit positions */ -#define OSC_RC32MCREF_gm 0x06 /* 32 MHz DFLL Calibration Reference group mask. */ -#define OSC_RC32MCREF_gp 1 /* 32 MHz DFLL Calibration Reference group position. */ -#define OSC_RC32MCREF0_bm (1<<1) /* 32 MHz DFLL Calibration Reference bit 0 mask. */ -#define OSC_RC32MCREF0_bp 1 /* 32 MHz DFLL Calibration Reference bit 0 position. */ -#define OSC_RC32MCREF1_bm (1<<2) /* 32 MHz DFLL Calibration Reference bit 1 mask. */ -#define OSC_RC32MCREF1_bp 2 /* 32 MHz DFLL Calibration Reference bit 1 position. */ - -#define OSC_RC2MCREF_bm 0x01 /* 2 MHz DFLL Calibration Reference bit mask. */ -#define OSC_RC2MCREF_bp 0 /* 2 MHz DFLL Calibration Reference bit position. */ - -/* DFLL - DFLL */ -/* DFLL.CTRL bit masks and bit positions */ -#define DFLL_ENABLE_bm 0x01 /* DFLL Enable bit mask. */ -#define DFLL_ENABLE_bp 0 /* DFLL Enable bit position. */ - -/* DFLL.CALA bit masks and bit positions */ -#define DFLL_CALL_gm 0x7F /* DFLL Calibration Value A group mask. */ -#define DFLL_CALL_gp 0 /* DFLL Calibration Value A group position. */ -#define DFLL_CALL0_bm (1<<0) /* DFLL Calibration Value A bit 0 mask. */ -#define DFLL_CALL0_bp 0 /* DFLL Calibration Value A bit 0 position. */ -#define DFLL_CALL1_bm (1<<1) /* DFLL Calibration Value A bit 1 mask. */ -#define DFLL_CALL1_bp 1 /* DFLL Calibration Value A bit 1 position. */ -#define DFLL_CALL2_bm (1<<2) /* DFLL Calibration Value A bit 2 mask. */ -#define DFLL_CALL2_bp 2 /* DFLL Calibration Value A bit 2 position. */ -#define DFLL_CALL3_bm (1<<3) /* DFLL Calibration Value A bit 3 mask. */ -#define DFLL_CALL3_bp 3 /* DFLL Calibration Value A bit 3 position. */ -#define DFLL_CALL4_bm (1<<4) /* DFLL Calibration Value A bit 4 mask. */ -#define DFLL_CALL4_bp 4 /* DFLL Calibration Value A bit 4 position. */ -#define DFLL_CALL5_bm (1<<5) /* DFLL Calibration Value A bit 5 mask. */ -#define DFLL_CALL5_bp 5 /* DFLL Calibration Value A bit 5 position. */ -#define DFLL_CALL6_bm (1<<6) /* DFLL Calibration Value A bit 6 mask. */ -#define DFLL_CALL6_bp 6 /* DFLL Calibration Value A bit 6 position. */ - -/* DFLL.CALB bit masks and bit positions */ -#define DFLL_CALH_gm 0x3F /* DFLL Calibration Value B group mask. */ -#define DFLL_CALH_gp 0 /* DFLL Calibration Value B group position. */ -#define DFLL_CALH0_bm (1<<0) /* DFLL Calibration Value B bit 0 mask. */ -#define DFLL_CALH0_bp 0 /* DFLL Calibration Value B bit 0 position. */ -#define DFLL_CALH1_bm (1<<1) /* DFLL Calibration Value B bit 1 mask. */ -#define DFLL_CALH1_bp 1 /* DFLL Calibration Value B bit 1 position. */ -#define DFLL_CALH2_bm (1<<2) /* DFLL Calibration Value B bit 2 mask. */ -#define DFLL_CALH2_bp 2 /* DFLL Calibration Value B bit 2 position. */ -#define DFLL_CALH3_bm (1<<3) /* DFLL Calibration Value B bit 3 mask. */ -#define DFLL_CALH3_bp 3 /* DFLL Calibration Value B bit 3 position. */ -#define DFLL_CALH4_bm (1<<4) /* DFLL Calibration Value B bit 4 mask. */ -#define DFLL_CALH4_bp 4 /* DFLL Calibration Value B bit 4 position. */ -#define DFLL_CALH5_bm (1<<5) /* DFLL Calibration Value B bit 5 mask. */ -#define DFLL_CALH5_bp 5 /* DFLL Calibration Value B bit 5 position. */ - -/* RST - Reset */ -/* RST.STATUS bit masks and bit positions */ -#define RST_SDRF_bm 0x40 /* Spike Detection Reset Flag bit mask. */ -#define RST_SDRF_bp 6 /* Spike Detection Reset Flag bit position. */ - -#define RST_SRF_bm 0x20 /* Software Reset Flag bit mask. */ -#define RST_SRF_bp 5 /* Software Reset Flag bit position. */ - -#define RST_PDIRF_bm 0x10 /* Programming and Debug Interface Interface Reset Flag bit mask. */ -#define RST_PDIRF_bp 4 /* Programming and Debug Interface Interface Reset Flag bit position. */ - -#define RST_WDRF_bm 0x08 /* Watchdog Reset Flag bit mask. */ -#define RST_WDRF_bp 3 /* Watchdog Reset Flag bit position. */ - -#define RST_BORF_bm 0x04 /* Brown-out Reset Flag bit mask. */ -#define RST_BORF_bp 2 /* Brown-out Reset Flag bit position. */ - -#define RST_EXTRF_bm 0x02 /* External Reset Flag bit mask. */ -#define RST_EXTRF_bp 1 /* External Reset Flag bit position. */ - -#define RST_PORF_bm 0x01 /* Power-on Reset Flag bit mask. */ -#define RST_PORF_bp 0 /* Power-on Reset Flag bit position. */ - -/* RST.CTRL bit masks and bit positions */ -#define RST_SWRST_bm 0x01 /* Software Reset bit mask. */ -#define RST_SWRST_bp 0 /* Software Reset bit position. */ - -/* WDT - Watch-Dog Timer */ -/* WDT.CTRL bit masks and bit positions */ -#define WDT_PER_gm 0x3C /* Period group mask. */ -#define WDT_PER_gp 2 /* Period group position. */ -#define WDT_PER0_bm (1<<2) /* Period bit 0 mask. */ -#define WDT_PER0_bp 2 /* Period bit 0 position. */ -#define WDT_PER1_bm (1<<3) /* Period bit 1 mask. */ -#define WDT_PER1_bp 3 /* Period bit 1 position. */ -#define WDT_PER2_bm (1<<4) /* Period bit 2 mask. */ -#define WDT_PER2_bp 4 /* Period bit 2 position. */ -#define WDT_PER3_bm (1<<5) /* Period bit 3 mask. */ -#define WDT_PER3_bp 5 /* Period bit 3 position. */ - -#define WDT_ENABLE_bm 0x02 /* Enable bit mask. */ -#define WDT_ENABLE_bp 1 /* Enable bit position. */ - -#define WDT_CEN_bm 0x01 /* Change Enable bit mask. */ -#define WDT_CEN_bp 0 /* Change Enable bit position. */ - -/* WDT.WINCTRL bit masks and bit positions */ -#define WDT_WPER_gm 0x3C /* Windowed Mode Period group mask. */ -#define WDT_WPER_gp 2 /* Windowed Mode Period group position. */ -#define WDT_WPER0_bm (1<<2) /* Windowed Mode Period bit 0 mask. */ -#define WDT_WPER0_bp 2 /* Windowed Mode Period bit 0 position. */ -#define WDT_WPER1_bm (1<<3) /* Windowed Mode Period bit 1 mask. */ -#define WDT_WPER1_bp 3 /* Windowed Mode Period bit 1 position. */ -#define WDT_WPER2_bm (1<<4) /* Windowed Mode Period bit 2 mask. */ -#define WDT_WPER2_bp 4 /* Windowed Mode Period bit 2 position. */ -#define WDT_WPER3_bm (1<<5) /* Windowed Mode Period bit 3 mask. */ -#define WDT_WPER3_bp 5 /* Windowed Mode Period bit 3 position. */ - -#define WDT_WEN_bm 0x02 /* Windowed Mode Enable bit mask. */ -#define WDT_WEN_bp 1 /* Windowed Mode Enable bit position. */ - -#define WDT_WCEN_bm 0x01 /* Windowed Mode Change Enable bit mask. */ -#define WDT_WCEN_bp 0 /* Windowed Mode Change Enable bit position. */ - -/* WDT.STATUS bit masks and bit positions */ -#define WDT_SYNCBUSY_bm 0x01 /* Syncronization busy bit mask. */ -#define WDT_SYNCBUSY_bp 0 /* Syncronization busy bit position. */ - -/* MCU - MCU Control */ -/* MCU.MCUCR bit masks and bit positions */ -#define MCU_JTAGD_bm 0x01 /* JTAG Disable bit mask. */ -#define MCU_JTAGD_bp 0 /* JTAG Disable bit position. */ - -/* MCU.ANAINIT bit masks and bit positions */ -#define MCU_STARTUPDLYB_gm 0x0C /* Analog startup delay Port B group mask. */ -#define MCU_STARTUPDLYB_gp 2 /* Analog startup delay Port B group position. */ -#define MCU_STARTUPDLYB0_bm (1<<2) /* Analog startup delay Port B bit 0 mask. */ -#define MCU_STARTUPDLYB0_bp 2 /* Analog startup delay Port B bit 0 position. */ -#define MCU_STARTUPDLYB1_bm (1<<3) /* Analog startup delay Port B bit 1 mask. */ -#define MCU_STARTUPDLYB1_bp 3 /* Analog startup delay Port B bit 1 position. */ - -#define MCU_STARTUPDLYA_gm 0x03 /* Analog startup delay Port A group mask. */ -#define MCU_STARTUPDLYA_gp 0 /* Analog startup delay Port A group position. */ -#define MCU_STARTUPDLYA0_bm (1<<0) /* Analog startup delay Port A bit 0 mask. */ -#define MCU_STARTUPDLYA0_bp 0 /* Analog startup delay Port A bit 0 position. */ -#define MCU_STARTUPDLYA1_bm (1<<1) /* Analog startup delay Port A bit 1 mask. */ -#define MCU_STARTUPDLYA1_bp 1 /* Analog startup delay Port A bit 1 position. */ - -/* MCU.EVSYSLOCK bit masks and bit positions */ -#define MCU_EVSYS1LOCK_bm 0x10 /* Event Channel 4-7 Lock bit mask. */ -#define MCU_EVSYS1LOCK_bp 4 /* Event Channel 4-7 Lock bit position. */ - -#define MCU_EVSYS0LOCK_bm 0x01 /* Event Channel 0-3 Lock bit mask. */ -#define MCU_EVSYS0LOCK_bp 0 /* Event Channel 0-3 Lock bit position. */ - -/* MCU.AWEXLOCK bit masks and bit positions */ -#define MCU_AWEXFLOCK_bm 0x08 /* AWeX on T/C F0 Lock bit mask. */ -#define MCU_AWEXFLOCK_bp 3 /* AWeX on T/C F0 Lock bit position. */ - -#define MCU_AWEXELOCK_bm 0x04 /* AWeX on T/C E0 Lock bit mask. */ -#define MCU_AWEXELOCK_bp 2 /* AWeX on T/C E0 Lock bit position. */ - -#define MCU_AWEXDLOCK_bm 0x02 /* AWeX on T/C D0 Lock bit mask. */ -#define MCU_AWEXDLOCK_bp 1 /* AWeX on T/C D0 Lock bit position. */ - -#define MCU_AWEXCLOCK_bm 0x01 /* AWeX on T/C C0 Lock bit mask. */ -#define MCU_AWEXCLOCK_bp 0 /* AWeX on T/C C0 Lock bit position. */ - -/* PMIC - Programmable Multi-level Interrupt Controller */ -/* PMIC.STATUS bit masks and bit positions */ -#define PMIC_NMIEX_bm 0x80 /* Non-maskable Interrupt Executing bit mask. */ -#define PMIC_NMIEX_bp 7 /* Non-maskable Interrupt Executing bit position. */ - -#define PMIC_HILVLEX_bm 0x04 /* High Level Interrupt Executing bit mask. */ -#define PMIC_HILVLEX_bp 2 /* High Level Interrupt Executing bit position. */ - -#define PMIC_MEDLVLEX_bm 0x02 /* Medium Level Interrupt Executing bit mask. */ -#define PMIC_MEDLVLEX_bp 1 /* Medium Level Interrupt Executing bit position. */ - -#define PMIC_LOLVLEX_bm 0x01 /* Low Level Interrupt Executing bit mask. */ -#define PMIC_LOLVLEX_bp 0 /* Low Level Interrupt Executing bit position. */ - -/* PMIC.INTPRI bit masks and bit positions */ -#define PMIC_INTPRI_gm 0xFF /* Interrupt Priority group mask. */ -#define PMIC_INTPRI_gp 0 /* Interrupt Priority group position. */ -#define PMIC_INTPRI0_bm (1<<0) /* Interrupt Priority bit 0 mask. */ -#define PMIC_INTPRI0_bp 0 /* Interrupt Priority bit 0 position. */ -#define PMIC_INTPRI1_bm (1<<1) /* Interrupt Priority bit 1 mask. */ -#define PMIC_INTPRI1_bp 1 /* Interrupt Priority bit 1 position. */ -#define PMIC_INTPRI2_bm (1<<2) /* Interrupt Priority bit 2 mask. */ -#define PMIC_INTPRI2_bp 2 /* Interrupt Priority bit 2 position. */ -#define PMIC_INTPRI3_bm (1<<3) /* Interrupt Priority bit 3 mask. */ -#define PMIC_INTPRI3_bp 3 /* Interrupt Priority bit 3 position. */ -#define PMIC_INTPRI4_bm (1<<4) /* Interrupt Priority bit 4 mask. */ -#define PMIC_INTPRI4_bp 4 /* Interrupt Priority bit 4 position. */ -#define PMIC_INTPRI5_bm (1<<5) /* Interrupt Priority bit 5 mask. */ -#define PMIC_INTPRI5_bp 5 /* Interrupt Priority bit 5 position. */ -#define PMIC_INTPRI6_bm (1<<6) /* Interrupt Priority bit 6 mask. */ -#define PMIC_INTPRI6_bp 6 /* Interrupt Priority bit 6 position. */ -#define PMIC_INTPRI7_bm (1<<7) /* Interrupt Priority bit 7 mask. */ -#define PMIC_INTPRI7_bp 7 /* Interrupt Priority bit 7 position. */ - -/* PMIC.CTRL bit masks and bit positions */ -#define PMIC_RREN_bm 0x80 /* Round-Robin Priority Enable bit mask. */ -#define PMIC_RREN_bp 7 /* Round-Robin Priority Enable bit position. */ - -#define PMIC_IVSEL_bm 0x40 /* Interrupt Vector Select bit mask. */ -#define PMIC_IVSEL_bp 6 /* Interrupt Vector Select bit position. */ - -#define PMIC_HILVLEN_bm 0x04 /* High Level Enable bit mask. */ -#define PMIC_HILVLEN_bp 2 /* High Level Enable bit position. */ - -#define PMIC_MEDLVLEN_bm 0x02 /* Medium Level Enable bit mask. */ -#define PMIC_MEDLVLEN_bp 1 /* Medium Level Enable bit position. */ - -#define PMIC_LOLVLEN_bm 0x01 /* Low Level Enable bit mask. */ -#define PMIC_LOLVLEN_bp 0 /* Low Level Enable bit position. */ - -/* PORTCFG - Port Configuration */ -/* PORTCFG.VPCTRLA bit masks and bit positions */ -#define PORTCFG_VP1MAP_gm 0xF0 /* Virtual Port 1 Mapping group mask. */ -#define PORTCFG_VP1MAP_gp 4 /* Virtual Port 1 Mapping group position. */ -#define PORTCFG_VP1MAP0_bm (1<<4) /* Virtual Port 1 Mapping bit 0 mask. */ -#define PORTCFG_VP1MAP0_bp 4 /* Virtual Port 1 Mapping bit 0 position. */ -#define PORTCFG_VP1MAP1_bm (1<<5) /* Virtual Port 1 Mapping bit 1 mask. */ -#define PORTCFG_VP1MAP1_bp 5 /* Virtual Port 1 Mapping bit 1 position. */ -#define PORTCFG_VP1MAP2_bm (1<<6) /* Virtual Port 1 Mapping bit 2 mask. */ -#define PORTCFG_VP1MAP2_bp 6 /* Virtual Port 1 Mapping bit 2 position. */ -#define PORTCFG_VP1MAP3_bm (1<<7) /* Virtual Port 1 Mapping bit 3 mask. */ -#define PORTCFG_VP1MAP3_bp 7 /* Virtual Port 1 Mapping bit 3 position. */ - -#define PORTCFG_VP0MAP_gm 0x0F /* Virtual Port 0 Mapping group mask. */ -#define PORTCFG_VP0MAP_gp 0 /* Virtual Port 0 Mapping group position. */ -#define PORTCFG_VP0MAP0_bm (1<<0) /* Virtual Port 0 Mapping bit 0 mask. */ -#define PORTCFG_VP0MAP0_bp 0 /* Virtual Port 0 Mapping bit 0 position. */ -#define PORTCFG_VP0MAP1_bm (1<<1) /* Virtual Port 0 Mapping bit 1 mask. */ -#define PORTCFG_VP0MAP1_bp 1 /* Virtual Port 0 Mapping bit 1 position. */ -#define PORTCFG_VP0MAP2_bm (1<<2) /* Virtual Port 0 Mapping bit 2 mask. */ -#define PORTCFG_VP0MAP2_bp 2 /* Virtual Port 0 Mapping bit 2 position. */ -#define PORTCFG_VP0MAP3_bm (1<<3) /* Virtual Port 0 Mapping bit 3 mask. */ -#define PORTCFG_VP0MAP3_bp 3 /* Virtual Port 0 Mapping bit 3 position. */ - -/* PORTCFG.VPCTRLB bit masks and bit positions */ -#define PORTCFG_VP3MAP_gm 0xF0 /* Virtual Port 3 Mapping group mask. */ -#define PORTCFG_VP3MAP_gp 4 /* Virtual Port 3 Mapping group position. */ -#define PORTCFG_VP3MAP0_bm (1<<4) /* Virtual Port 3 Mapping bit 0 mask. */ -#define PORTCFG_VP3MAP0_bp 4 /* Virtual Port 3 Mapping bit 0 position. */ -#define PORTCFG_VP3MAP1_bm (1<<5) /* Virtual Port 3 Mapping bit 1 mask. */ -#define PORTCFG_VP3MAP1_bp 5 /* Virtual Port 3 Mapping bit 1 position. */ -#define PORTCFG_VP3MAP2_bm (1<<6) /* Virtual Port 3 Mapping bit 2 mask. */ -#define PORTCFG_VP3MAP2_bp 6 /* Virtual Port 3 Mapping bit 2 position. */ -#define PORTCFG_VP3MAP3_bm (1<<7) /* Virtual Port 3 Mapping bit 3 mask. */ -#define PORTCFG_VP3MAP3_bp 7 /* Virtual Port 3 Mapping bit 3 position. */ - -#define PORTCFG_VP2MAP_gm 0x0F /* Virtual Port 2 Mapping group mask. */ -#define PORTCFG_VP2MAP_gp 0 /* Virtual Port 2 Mapping group position. */ -#define PORTCFG_VP2MAP0_bm (1<<0) /* Virtual Port 2 Mapping bit 0 mask. */ -#define PORTCFG_VP2MAP0_bp 0 /* Virtual Port 2 Mapping bit 0 position. */ -#define PORTCFG_VP2MAP1_bm (1<<1) /* Virtual Port 2 Mapping bit 1 mask. */ -#define PORTCFG_VP2MAP1_bp 1 /* Virtual Port 2 Mapping bit 1 position. */ -#define PORTCFG_VP2MAP2_bm (1<<2) /* Virtual Port 2 Mapping bit 2 mask. */ -#define PORTCFG_VP2MAP2_bp 2 /* Virtual Port 2 Mapping bit 2 position. */ -#define PORTCFG_VP2MAP3_bm (1<<3) /* Virtual Port 2 Mapping bit 3 mask. */ -#define PORTCFG_VP2MAP3_bp 3 /* Virtual Port 2 Mapping bit 3 position. */ - -/* PORTCFG.CLKEVOUT bit masks and bit positions */ -#define PORTCFG_CLKOUT_gm 0x03 /* Peripheral Clock Output Port group mask. */ -#define PORTCFG_CLKOUT_gp 0 /* Peripheral Clock Output Port group position. */ -#define PORTCFG_CLKOUT0_bm (1<<0) /* Peripheral Clock Output Port bit 0 mask. */ -#define PORTCFG_CLKOUT0_bp 0 /* Peripheral Clock Output Port bit 0 position. */ -#define PORTCFG_CLKOUT1_bm (1<<1) /* Peripheral Clock Output Port bit 1 mask. */ -#define PORTCFG_CLKOUT1_bp 1 /* Peripheral Clock Output Port bit 1 position. */ - -#define PORTCFG_CLKOUTSEL_gm 0x0C /* Peripheral Clock Output Select group mask. */ -#define PORTCFG_CLKOUTSEL_gp 2 /* Peripheral Clock Output Select group position. */ -#define PORTCFG_CLKOUTSEL0_bm (1<<2) /* Peripheral Clock Output Select bit 0 mask. */ -#define PORTCFG_CLKOUTSEL0_bp 2 /* Peripheral Clock Output Select bit 0 position. */ -#define PORTCFG_CLKOUTSEL1_bm (1<<3) /* Peripheral Clock Output Select bit 1 mask. */ -#define PORTCFG_CLKOUTSEL1_bp 3 /* Peripheral Clock Output Select bit 1 position. */ - -#define PORTCFG_EVOUT_gm 0x30 /* Event Output Port group mask. */ -#define PORTCFG_EVOUT_gp 4 /* Event Output Port group position. */ -#define PORTCFG_EVOUT0_bm (1<<4) /* Event Output Port bit 0 mask. */ -#define PORTCFG_EVOUT0_bp 4 /* Event Output Port bit 0 position. */ -#define PORTCFG_EVOUT1_bm (1<<5) /* Event Output Port bit 1 mask. */ -#define PORTCFG_EVOUT1_bp 5 /* Event Output Port bit 1 position. */ - -#define PORTCFG_RTCOUT_bm 0x40 /* RTC Clock Output bit mask. */ -#define PORTCFG_RTCOUT_bp 6 /* RTC Clock Output bit position. */ - -#define PORTCFG_CLKEVPIN_bm 0x80 /* Peripheral Clock and Event Output pin Select bit mask. */ -#define PORTCFG_CLKEVPIN_bp 7 /* Peripheral Clock and Event Output pin Select bit position. */ - -/* PORTCFG.EBIOUT bit masks and bit positions */ -#define PORTCFG_EBICSOUT_gm 0x03 /* EBI Chip Select Output group mask. */ -#define PORTCFG_EBICSOUT_gp 0 /* EBI Chip Select Output group position. */ -#define PORTCFG_EBICSOUT0_bm (1<<0) /* EBI Chip Select Output bit 0 mask. */ -#define PORTCFG_EBICSOUT0_bp 0 /* EBI Chip Select Output bit 0 position. */ -#define PORTCFG_EBICSOUT1_bm (1<<1) /* EBI Chip Select Output bit 1 mask. */ -#define PORTCFG_EBICSOUT1_bp 1 /* EBI Chip Select Output bit 1 position. */ - -#define PORTCFG_EBIADROUT_gm 0x0C /* EBI Address Output group mask. */ -#define PORTCFG_EBIADROUT_gp 2 /* EBI Address Output group position. */ -#define PORTCFG_EBIADROUT0_bm (1<<2) /* EBI Address Output bit 0 mask. */ -#define PORTCFG_EBIADROUT0_bp 2 /* EBI Address Output bit 0 position. */ -#define PORTCFG_EBIADROUT1_bm (1<<3) /* EBI Address Output bit 1 mask. */ -#define PORTCFG_EBIADROUT1_bp 3 /* EBI Address Output bit 1 position. */ - -/* PORTCFG.EVOUTSEL bit masks and bit positions */ -#define PORTCFG_EVOUTSEL_gm 0x07 /* Event Output Select group mask. */ -#define PORTCFG_EVOUTSEL_gp 0 /* Event Output Select group position. */ -#define PORTCFG_EVOUTSEL0_bm (1<<0) /* Event Output Select bit 0 mask. */ -#define PORTCFG_EVOUTSEL0_bp 0 /* Event Output Select bit 0 position. */ -#define PORTCFG_EVOUTSEL1_bm (1<<1) /* Event Output Select bit 1 mask. */ -#define PORTCFG_EVOUTSEL1_bp 1 /* Event Output Select bit 1 position. */ -#define PORTCFG_EVOUTSEL2_bm (1<<2) /* Event Output Select bit 2 mask. */ -#define PORTCFG_EVOUTSEL2_bp 2 /* Event Output Select bit 2 position. */ - -/* AES - AES Module */ -/* AES.CTRL bit masks and bit positions */ -#define AES_START_bm 0x80 /* Start/Run bit mask. */ -#define AES_START_bp 7 /* Start/Run bit position. */ - -#define AES_AUTO_bm 0x40 /* Auto Start Trigger bit mask. */ -#define AES_AUTO_bp 6 /* Auto Start Trigger bit position. */ - -#define AES_RESET_bm 0x20 /* AES Software Reset bit mask. */ -#define AES_RESET_bp 5 /* AES Software Reset bit position. */ - -#define AES_DECRYPT_bm 0x10 /* Decryption / Direction bit mask. */ -#define AES_DECRYPT_bp 4 /* Decryption / Direction bit position. */ - -#define AES_XOR_bm 0x04 /* State XOR Load Enable bit mask. */ -#define AES_XOR_bp 2 /* State XOR Load Enable bit position. */ - -/* AES.STATUS bit masks and bit positions */ -#define AES_ERROR_bm 0x80 /* AES Error bit mask. */ -#define AES_ERROR_bp 7 /* AES Error bit position. */ - -#define AES_SRIF_bm 0x01 /* State Ready Interrupt Flag bit mask. */ -#define AES_SRIF_bp 0 /* State Ready Interrupt Flag bit position. */ - -/* AES.INTCTRL bit masks and bit positions */ -#define AES_INTLVL_gm 0x03 /* Interrupt level group mask. */ -#define AES_INTLVL_gp 0 /* Interrupt level group position. */ -#define AES_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */ -#define AES_INTLVL0_bp 0 /* Interrupt level bit 0 position. */ -#define AES_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */ -#define AES_INTLVL1_bp 1 /* Interrupt level bit 1 position. */ - -/* CRC - Cyclic Redundancy Checker */ -/* CRC.CTRL bit masks and bit positions */ -#define CRC_RESET_gm 0xC0 /* Reset group mask. */ -#define CRC_RESET_gp 6 /* Reset group position. */ -#define CRC_RESET0_bm (1<<6) /* Reset bit 0 mask. */ -#define CRC_RESET0_bp 6 /* Reset bit 0 position. */ -#define CRC_RESET1_bm (1<<7) /* Reset bit 1 mask. */ -#define CRC_RESET1_bp 7 /* Reset bit 1 position. */ - -#define CRC_CRC32_bm 0x20 /* CRC Mode bit mask. */ -#define CRC_CRC32_bp 5 /* CRC Mode bit position. */ - -#define CRC_SOURCE_gm 0x0F /* Input Source group mask. */ -#define CRC_SOURCE_gp 0 /* Input Source group position. */ -#define CRC_SOURCE0_bm (1<<0) /* Input Source bit 0 mask. */ -#define CRC_SOURCE0_bp 0 /* Input Source bit 0 position. */ -#define CRC_SOURCE1_bm (1<<1) /* Input Source bit 1 mask. */ -#define CRC_SOURCE1_bp 1 /* Input Source bit 1 position. */ -#define CRC_SOURCE2_bm (1<<2) /* Input Source bit 2 mask. */ -#define CRC_SOURCE2_bp 2 /* Input Source bit 2 position. */ -#define CRC_SOURCE3_bm (1<<3) /* Input Source bit 3 mask. */ -#define CRC_SOURCE3_bp 3 /* Input Source bit 3 position. */ - -/* CRC.STATUS bit masks and bit positions */ -#define CRC_ZERO_bm 0x02 /* Zero detection bit mask. */ -#define CRC_ZERO_bp 1 /* Zero detection bit position. */ - -#define CRC_BUSY_bm 0x01 /* Busy bit mask. */ -#define CRC_BUSY_bp 0 /* Busy bit position. */ - -/* DMA - DMA Controller */ -/* DMA_CH.CTRLA bit masks and bit positions */ -#define DMA_CH_ENABLE_bm 0x80 /* Channel Enable bit mask. */ -#define DMA_CH_ENABLE_bp 7 /* Channel Enable bit position. */ - -#define DMA_CH_RESET_bm 0x40 /* Channel Software Reset bit mask. */ -#define DMA_CH_RESET_bp 6 /* Channel Software Reset bit position. */ - -#define DMA_CH_REPEAT_bm 0x20 /* Channel Repeat Mode bit mask. */ -#define DMA_CH_REPEAT_bp 5 /* Channel Repeat Mode bit position. */ - -#define DMA_CH_TRFREQ_bm 0x10 /* Channel Transfer Request bit mask. */ -#define DMA_CH_TRFREQ_bp 4 /* Channel Transfer Request bit position. */ - -#define DMA_CH_SINGLE_bm 0x04 /* Channel Single Shot Data Transfer bit mask. */ -#define DMA_CH_SINGLE_bp 2 /* Channel Single Shot Data Transfer bit position. */ - -#define DMA_CH_BURSTLEN_gm 0x03 /* Channel Transfer Mode group mask. */ -#define DMA_CH_BURSTLEN_gp 0 /* Channel Transfer Mode group position. */ -#define DMA_CH_BURSTLEN0_bm (1<<0) /* Channel Transfer Mode bit 0 mask. */ -#define DMA_CH_BURSTLEN0_bp 0 /* Channel Transfer Mode bit 0 position. */ -#define DMA_CH_BURSTLEN1_bm (1<<1) /* Channel Transfer Mode bit 1 mask. */ -#define DMA_CH_BURSTLEN1_bp 1 /* Channel Transfer Mode bit 1 position. */ - -/* DMA_CH.CTRLB bit masks and bit positions */ -#define DMA_CH_CHBUSY_bm 0x80 /* Block Transfer Busy bit mask. */ -#define DMA_CH_CHBUSY_bp 7 /* Block Transfer Busy bit position. */ - -#define DMA_CH_CHPEND_bm 0x40 /* Block Transfer Pending bit mask. */ -#define DMA_CH_CHPEND_bp 6 /* Block Transfer Pending bit position. */ - -#define DMA_CH_ERRIF_bm 0x20 /* Block Transfer Error Interrupt Flag bit mask. */ -#define DMA_CH_ERRIF_bp 5 /* Block Transfer Error Interrupt Flag bit position. */ - -#define DMA_CH_TRNIF_bm 0x10 /* Transaction Complete Interrup Flag bit mask. */ -#define DMA_CH_TRNIF_bp 4 /* Transaction Complete Interrup Flag bit position. */ - -#define DMA_CH_ERRINTLVL_gm 0x0C /* Transfer Error Interrupt Level group mask. */ -#define DMA_CH_ERRINTLVL_gp 2 /* Transfer Error Interrupt Level group position. */ -#define DMA_CH_ERRINTLVL0_bm (1<<2) /* Transfer Error Interrupt Level bit 0 mask. */ -#define DMA_CH_ERRINTLVL0_bp 2 /* Transfer Error Interrupt Level bit 0 position. */ -#define DMA_CH_ERRINTLVL1_bm (1<<3) /* Transfer Error Interrupt Level bit 1 mask. */ -#define DMA_CH_ERRINTLVL1_bp 3 /* Transfer Error Interrupt Level bit 1 position. */ - -#define DMA_CH_TRNINTLVL_gm 0x03 /* Transaction Complete Interrupt Level group mask. */ -#define DMA_CH_TRNINTLVL_gp 0 /* Transaction Complete Interrupt Level group position. */ -#define DMA_CH_TRNINTLVL0_bm (1<<0) /* Transaction Complete Interrupt Level bit 0 mask. */ -#define DMA_CH_TRNINTLVL0_bp 0 /* Transaction Complete Interrupt Level bit 0 position. */ -#define DMA_CH_TRNINTLVL1_bm (1<<1) /* Transaction Complete Interrupt Level bit 1 mask. */ -#define DMA_CH_TRNINTLVL1_bp 1 /* Transaction Complete Interrupt Level bit 1 position. */ - -/* DMA_CH.ADDRCTRL bit masks and bit positions */ -#define DMA_CH_SRCRELOAD_gm 0xC0 /* Channel Source Address Reload group mask. */ -#define DMA_CH_SRCRELOAD_gp 6 /* Channel Source Address Reload group position. */ -#define DMA_CH_SRCRELOAD0_bm (1<<6) /* Channel Source Address Reload bit 0 mask. */ -#define DMA_CH_SRCRELOAD0_bp 6 /* Channel Source Address Reload bit 0 position. */ -#define DMA_CH_SRCRELOAD1_bm (1<<7) /* Channel Source Address Reload bit 1 mask. */ -#define DMA_CH_SRCRELOAD1_bp 7 /* Channel Source Address Reload bit 1 position. */ - -#define DMA_CH_SRCDIR_gm 0x30 /* Channel Source Address Mode group mask. */ -#define DMA_CH_SRCDIR_gp 4 /* Channel Source Address Mode group position. */ -#define DMA_CH_SRCDIR0_bm (1<<4) /* Channel Source Address Mode bit 0 mask. */ -#define DMA_CH_SRCDIR0_bp 4 /* Channel Source Address Mode bit 0 position. */ -#define DMA_CH_SRCDIR1_bm (1<<5) /* Channel Source Address Mode bit 1 mask. */ -#define DMA_CH_SRCDIR1_bp 5 /* Channel Source Address Mode bit 1 position. */ - -#define DMA_CH_DESTRELOAD_gm 0x0C /* Channel Destination Address Reload group mask. */ -#define DMA_CH_DESTRELOAD_gp 2 /* Channel Destination Address Reload group position. */ -#define DMA_CH_DESTRELOAD0_bm (1<<2) /* Channel Destination Address Reload bit 0 mask. */ -#define DMA_CH_DESTRELOAD0_bp 2 /* Channel Destination Address Reload bit 0 position. */ -#define DMA_CH_DESTRELOAD1_bm (1<<3) /* Channel Destination Address Reload bit 1 mask. */ -#define DMA_CH_DESTRELOAD1_bp 3 /* Channel Destination Address Reload bit 1 position. */ - -#define DMA_CH_DESTDIR_gm 0x03 /* Channel Destination Address Mode group mask. */ -#define DMA_CH_DESTDIR_gp 0 /* Channel Destination Address Mode group position. */ -#define DMA_CH_DESTDIR0_bm (1<<0) /* Channel Destination Address Mode bit 0 mask. */ -#define DMA_CH_DESTDIR0_bp 0 /* Channel Destination Address Mode bit 0 position. */ -#define DMA_CH_DESTDIR1_bm (1<<1) /* Channel Destination Address Mode bit 1 mask. */ -#define DMA_CH_DESTDIR1_bp 1 /* Channel Destination Address Mode bit 1 position. */ - -/* DMA_CH.TRIGSRC bit masks and bit positions */ -#define DMA_CH_TRIGSRC_gm 0xFF /* Channel Trigger Source group mask. */ -#define DMA_CH_TRIGSRC_gp 0 /* Channel Trigger Source group position. */ -#define DMA_CH_TRIGSRC0_bm (1<<0) /* Channel Trigger Source bit 0 mask. */ -#define DMA_CH_TRIGSRC0_bp 0 /* Channel Trigger Source bit 0 position. */ -#define DMA_CH_TRIGSRC1_bm (1<<1) /* Channel Trigger Source bit 1 mask. */ -#define DMA_CH_TRIGSRC1_bp 1 /* Channel Trigger Source bit 1 position. */ -#define DMA_CH_TRIGSRC2_bm (1<<2) /* Channel Trigger Source bit 2 mask. */ -#define DMA_CH_TRIGSRC2_bp 2 /* Channel Trigger Source bit 2 position. */ -#define DMA_CH_TRIGSRC3_bm (1<<3) /* Channel Trigger Source bit 3 mask. */ -#define DMA_CH_TRIGSRC3_bp 3 /* Channel Trigger Source bit 3 position. */ -#define DMA_CH_TRIGSRC4_bm (1<<4) /* Channel Trigger Source bit 4 mask. */ -#define DMA_CH_TRIGSRC4_bp 4 /* Channel Trigger Source bit 4 position. */ -#define DMA_CH_TRIGSRC5_bm (1<<5) /* Channel Trigger Source bit 5 mask. */ -#define DMA_CH_TRIGSRC5_bp 5 /* Channel Trigger Source bit 5 position. */ -#define DMA_CH_TRIGSRC6_bm (1<<6) /* Channel Trigger Source bit 6 mask. */ -#define DMA_CH_TRIGSRC6_bp 6 /* Channel Trigger Source bit 6 position. */ -#define DMA_CH_TRIGSRC7_bm (1<<7) /* Channel Trigger Source bit 7 mask. */ -#define DMA_CH_TRIGSRC7_bp 7 /* Channel Trigger Source bit 7 position. */ - -/* DMA.CTRL bit masks and bit positions */ -#define DMA_ENABLE_bm 0x80 /* Enable bit mask. */ -#define DMA_ENABLE_bp 7 /* Enable bit position. */ - -#define DMA_RESET_bm 0x40 /* Software Reset bit mask. */ -#define DMA_RESET_bp 6 /* Software Reset bit position. */ - -#define DMA_DBUFMODE_gm 0x0C /* Double Buffering Mode group mask. */ -#define DMA_DBUFMODE_gp 2 /* Double Buffering Mode group position. */ -#define DMA_DBUFMODE0_bm (1<<2) /* Double Buffering Mode bit 0 mask. */ -#define DMA_DBUFMODE0_bp 2 /* Double Buffering Mode bit 0 position. */ -#define DMA_DBUFMODE1_bm (1<<3) /* Double Buffering Mode bit 1 mask. */ -#define DMA_DBUFMODE1_bp 3 /* Double Buffering Mode bit 1 position. */ - -#define DMA_PRIMODE_gm 0x03 /* Channel Priority Mode group mask. */ -#define DMA_PRIMODE_gp 0 /* Channel Priority Mode group position. */ -#define DMA_PRIMODE0_bm (1<<0) /* Channel Priority Mode bit 0 mask. */ -#define DMA_PRIMODE0_bp 0 /* Channel Priority Mode bit 0 position. */ -#define DMA_PRIMODE1_bm (1<<1) /* Channel Priority Mode bit 1 mask. */ -#define DMA_PRIMODE1_bp 1 /* Channel Priority Mode bit 1 position. */ - -/* DMA.INTFLAGS bit masks and bit positions */ -#define DMA_CH3ERRIF_bm 0x80 /* Channel 3 Block Transfer Error Interrupt Flag bit mask. */ -#define DMA_CH3ERRIF_bp 7 /* Channel 3 Block Transfer Error Interrupt Flag bit position. */ - -#define DMA_CH2ERRIF_bm 0x40 /* Channel 2 Block Transfer Error Interrupt Flag bit mask. */ -#define DMA_CH2ERRIF_bp 6 /* Channel 2 Block Transfer Error Interrupt Flag bit position. */ - -#define DMA_CH1ERRIF_bm 0x20 /* Channel 1 Block Transfer Error Interrupt Flag bit mask. */ -#define DMA_CH1ERRIF_bp 5 /* Channel 1 Block Transfer Error Interrupt Flag bit position. */ - -#define DMA_CH0ERRIF_bm 0x10 /* Channel 0 Block Transfer Error Interrupt Flag bit mask. */ -#define DMA_CH0ERRIF_bp 4 /* Channel 0 Block Transfer Error Interrupt Flag bit position. */ - -#define DMA_CH3TRNIF_bm 0x08 /* Channel 3 Transaction Complete Interrupt Flag bit mask. */ -#define DMA_CH3TRNIF_bp 3 /* Channel 3 Transaction Complete Interrupt Flag bit position. */ - -#define DMA_CH2TRNIF_bm 0x04 /* Channel 2 Transaction Complete Interrupt Flag bit mask. */ -#define DMA_CH2TRNIF_bp 2 /* Channel 2 Transaction Complete Interrupt Flag bit position. */ - -#define DMA_CH1TRNIF_bm 0x02 /* Channel 1 Transaction Complete Interrupt Flag bit mask. */ -#define DMA_CH1TRNIF_bp 1 /* Channel 1 Transaction Complete Interrupt Flag bit position. */ - -#define DMA_CH0TRNIF_bm 0x01 /* Channel 0 Transaction Complete Interrupt Flag bit mask. */ -#define DMA_CH0TRNIF_bp 0 /* Channel 0 Transaction Complete Interrupt Flag bit position. */ - -/* DMA.STATUS bit masks and bit positions */ -#define DMA_CH3BUSY_bm 0x80 /* Channel 3 Block Transfer Busy bit mask. */ -#define DMA_CH3BUSY_bp 7 /* Channel 3 Block Transfer Busy bit position. */ - -#define DMA_CH2BUSY_bm 0x40 /* Channel 2 Block Transfer Busy bit mask. */ -#define DMA_CH2BUSY_bp 6 /* Channel 2 Block Transfer Busy bit position. */ - -#define DMA_CH1BUSY_bm 0x20 /* Channel 1 Block Transfer Busy bit mask. */ -#define DMA_CH1BUSY_bp 5 /* Channel 1 Block Transfer Busy bit position. */ - -#define DMA_CH0BUSY_bm 0x10 /* Channel 0 Block Transfer Busy bit mask. */ -#define DMA_CH0BUSY_bp 4 /* Channel 0 Block Transfer Busy bit position. */ - -#define DMA_CH3PEND_bm 0x08 /* Channel 3 Block Transfer Pending bit mask. */ -#define DMA_CH3PEND_bp 3 /* Channel 3 Block Transfer Pending bit position. */ - -#define DMA_CH2PEND_bm 0x04 /* Channel 2 Block Transfer Pending bit mask. */ -#define DMA_CH2PEND_bp 2 /* Channel 2 Block Transfer Pending bit position. */ - -#define DMA_CH1PEND_bm 0x02 /* Channel 1 Block Transfer Pending bit mask. */ -#define DMA_CH1PEND_bp 1 /* Channel 1 Block Transfer Pending bit position. */ - -#define DMA_CH0PEND_bm 0x01 /* Channel 0 Block Transfer Pending bit mask. */ -#define DMA_CH0PEND_bp 0 /* Channel 0 Block Transfer Pending bit position. */ - -/* EVSYS - Event System */ -/* EVSYS.CH0MUX bit masks and bit positions */ -#define EVSYS_CHMUX_gm 0xFF /* Event Channel 0 Multiplexer group mask. */ -#define EVSYS_CHMUX_gp 0 /* Event Channel 0 Multiplexer group position. */ -#define EVSYS_CHMUX0_bm (1<<0) /* Event Channel 0 Multiplexer bit 0 mask. */ -#define EVSYS_CHMUX0_bp 0 /* Event Channel 0 Multiplexer bit 0 position. */ -#define EVSYS_CHMUX1_bm (1<<1) /* Event Channel 0 Multiplexer bit 1 mask. */ -#define EVSYS_CHMUX1_bp 1 /* Event Channel 0 Multiplexer bit 1 position. */ -#define EVSYS_CHMUX2_bm (1<<2) /* Event Channel 0 Multiplexer bit 2 mask. */ -#define EVSYS_CHMUX2_bp 2 /* Event Channel 0 Multiplexer bit 2 position. */ -#define EVSYS_CHMUX3_bm (1<<3) /* Event Channel 0 Multiplexer bit 3 mask. */ -#define EVSYS_CHMUX3_bp 3 /* Event Channel 0 Multiplexer bit 3 position. */ -#define EVSYS_CHMUX4_bm (1<<4) /* Event Channel 0 Multiplexer bit 4 mask. */ -#define EVSYS_CHMUX4_bp 4 /* Event Channel 0 Multiplexer bit 4 position. */ -#define EVSYS_CHMUX5_bm (1<<5) /* Event Channel 0 Multiplexer bit 5 mask. */ -#define EVSYS_CHMUX5_bp 5 /* Event Channel 0 Multiplexer bit 5 position. */ -#define EVSYS_CHMUX6_bm (1<<6) /* Event Channel 0 Multiplexer bit 6 mask. */ -#define EVSYS_CHMUX6_bp 6 /* Event Channel 0 Multiplexer bit 6 position. */ -#define EVSYS_CHMUX7_bm (1<<7) /* Event Channel 0 Multiplexer bit 7 mask. */ -#define EVSYS_CHMUX7_bp 7 /* Event Channel 0 Multiplexer bit 7 position. */ - -/* EVSYS.CH1MUX bit masks and bit positions */ -/* EVSYS_CHMUX Predefined. */ -/* EVSYS_CHMUX Predefined. */ - -/* EVSYS.CH2MUX bit masks and bit positions */ -/* EVSYS_CHMUX Predefined. */ -/* EVSYS_CHMUX Predefined. */ - -/* EVSYS.CH3MUX bit masks and bit positions */ -/* EVSYS_CHMUX Predefined. */ -/* EVSYS_CHMUX Predefined. */ - -/* EVSYS.CH4MUX bit masks and bit positions */ -/* EVSYS_CHMUX Predefined. */ -/* EVSYS_CHMUX Predefined. */ - -/* EVSYS.CH5MUX bit masks and bit positions */ -/* EVSYS_CHMUX Predefined. */ -/* EVSYS_CHMUX Predefined. */ - -/* EVSYS.CH6MUX bit masks and bit positions */ -/* EVSYS_CHMUX Predefined. */ -/* EVSYS_CHMUX Predefined. */ - -/* EVSYS.CH7MUX bit masks and bit positions */ -/* EVSYS_CHMUX Predefined. */ -/* EVSYS_CHMUX Predefined. */ - -/* EVSYS.CH0CTRL bit masks and bit positions */ -#define EVSYS_QDIRM_gm 0x60 /* Quadrature Decoder Index Recognition Mode group mask. */ -#define EVSYS_QDIRM_gp 5 /* Quadrature Decoder Index Recognition Mode group position. */ -#define EVSYS_QDIRM0_bm (1<<5) /* Quadrature Decoder Index Recognition Mode bit 0 mask. */ -#define EVSYS_QDIRM0_bp 5 /* Quadrature Decoder Index Recognition Mode bit 0 position. */ -#define EVSYS_QDIRM1_bm (1<<6) /* Quadrature Decoder Index Recognition Mode bit 1 mask. */ -#define EVSYS_QDIRM1_bp 6 /* Quadrature Decoder Index Recognition Mode bit 1 position. */ - -#define EVSYS_QDIEN_bm 0x10 /* Quadrature Decoder Index Enable bit mask. */ -#define EVSYS_QDIEN_bp 4 /* Quadrature Decoder Index Enable bit position. */ - -#define EVSYS_QDEN_bm 0x08 /* Quadrature Decoder Enable bit mask. */ -#define EVSYS_QDEN_bp 3 /* Quadrature Decoder Enable bit position. */ - -#define EVSYS_DIGFILT_gm 0x07 /* Digital Filter group mask. */ -#define EVSYS_DIGFILT_gp 0 /* Digital Filter group position. */ -#define EVSYS_DIGFILT0_bm (1<<0) /* Digital Filter bit 0 mask. */ -#define EVSYS_DIGFILT0_bp 0 /* Digital Filter bit 0 position. */ -#define EVSYS_DIGFILT1_bm (1<<1) /* Digital Filter bit 1 mask. */ -#define EVSYS_DIGFILT1_bp 1 /* Digital Filter bit 1 position. */ -#define EVSYS_DIGFILT2_bm (1<<2) /* Digital Filter bit 2 mask. */ -#define EVSYS_DIGFILT2_bp 2 /* Digital Filter bit 2 position. */ - -/* EVSYS.CH1CTRL bit masks and bit positions */ -/* EVSYS_DIGFILT Predefined. */ -/* EVSYS_DIGFILT Predefined. */ - -/* EVSYS.CH2CTRL bit masks and bit positions */ -/* EVSYS_QDIRM Predefined. */ -/* EVSYS_QDIRM Predefined. */ - -/* EVSYS_QDIEN Predefined. */ -/* EVSYS_QDIEN Predefined. */ - -/* EVSYS_QDEN Predefined. */ -/* EVSYS_QDEN Predefined. */ - -/* EVSYS_DIGFILT Predefined. */ -/* EVSYS_DIGFILT Predefined. */ - -/* EVSYS.CH3CTRL bit masks and bit positions */ -/* EVSYS_DIGFILT Predefined. */ -/* EVSYS_DIGFILT Predefined. */ - -/* EVSYS.CH4CTRL bit masks and bit positions */ -/* EVSYS_QDIRM Predefined. */ -/* EVSYS_QDIRM Predefined. */ - -/* EVSYS_QDIEN Predefined. */ -/* EVSYS_QDIEN Predefined. */ - -/* EVSYS_QDEN Predefined. */ -/* EVSYS_QDEN Predefined. */ - -/* EVSYS_DIGFILT Predefined. */ -/* EVSYS_DIGFILT Predefined. */ - -/* EVSYS.CH5CTRL bit masks and bit positions */ -/* EVSYS_DIGFILT Predefined. */ -/* EVSYS_DIGFILT Predefined. */ - -/* EVSYS.CH6CTRL bit masks and bit positions */ -/* EVSYS_DIGFILT Predefined. */ -/* EVSYS_DIGFILT Predefined. */ - -/* EVSYS.CH7CTRL bit masks and bit positions */ -/* EVSYS_DIGFILT Predefined. */ -/* EVSYS_DIGFILT Predefined. */ - -/* NVM - Non Volatile Memory Controller */ -/* NVM.CMD bit masks and bit positions */ -#define NVM_CMD_gm 0x7F /* Command group mask. */ -#define NVM_CMD_gp 0 /* Command group position. */ -#define NVM_CMD0_bm (1<<0) /* Command bit 0 mask. */ -#define NVM_CMD0_bp 0 /* Command bit 0 position. */ -#define NVM_CMD1_bm (1<<1) /* Command bit 1 mask. */ -#define NVM_CMD1_bp 1 /* Command bit 1 position. */ -#define NVM_CMD2_bm (1<<2) /* Command bit 2 mask. */ -#define NVM_CMD2_bp 2 /* Command bit 2 position. */ -#define NVM_CMD3_bm (1<<3) /* Command bit 3 mask. */ -#define NVM_CMD3_bp 3 /* Command bit 3 position. */ -#define NVM_CMD4_bm (1<<4) /* Command bit 4 mask. */ -#define NVM_CMD4_bp 4 /* Command bit 4 position. */ -#define NVM_CMD5_bm (1<<5) /* Command bit 5 mask. */ -#define NVM_CMD5_bp 5 /* Command bit 5 position. */ -#define NVM_CMD6_bm (1<<6) /* Command bit 6 mask. */ -#define NVM_CMD6_bp 6 /* Command bit 6 position. */ - -/* NVM.CTRLA bit masks and bit positions */ -#define NVM_CMDEX_bm 0x01 /* Command Execute bit mask. */ -#define NVM_CMDEX_bp 0 /* Command Execute bit position. */ - -/* NVM.CTRLB bit masks and bit positions */ -#define NVM_EEMAPEN_bm 0x08 /* EEPROM Mapping Enable bit mask. */ -#define NVM_EEMAPEN_bp 3 /* EEPROM Mapping Enable bit position. */ - -#define NVM_FPRM_bm 0x04 /* Flash Power Reduction Enable bit mask. */ -#define NVM_FPRM_bp 2 /* Flash Power Reduction Enable bit position. */ - -#define NVM_EPRM_bm 0x02 /* EEPROM Power Reduction Enable bit mask. */ -#define NVM_EPRM_bp 1 /* EEPROM Power Reduction Enable bit position. */ - -#define NVM_SPMLOCK_bm 0x01 /* SPM Lock bit mask. */ -#define NVM_SPMLOCK_bp 0 /* SPM Lock bit position. */ - -/* NVM.INTCTRL bit masks and bit positions */ -#define NVM_SPMLVL_gm 0x0C /* SPM Interrupt Level group mask. */ -#define NVM_SPMLVL_gp 2 /* SPM Interrupt Level group position. */ -#define NVM_SPMLVL0_bm (1<<2) /* SPM Interrupt Level bit 0 mask. */ -#define NVM_SPMLVL0_bp 2 /* SPM Interrupt Level bit 0 position. */ -#define NVM_SPMLVL1_bm (1<<3) /* SPM Interrupt Level bit 1 mask. */ -#define NVM_SPMLVL1_bp 3 /* SPM Interrupt Level bit 1 position. */ - -#define NVM_EELVL_gm 0x03 /* EEPROM Interrupt Level group mask. */ -#define NVM_EELVL_gp 0 /* EEPROM Interrupt Level group position. */ -#define NVM_EELVL0_bm (1<<0) /* EEPROM Interrupt Level bit 0 mask. */ -#define NVM_EELVL0_bp 0 /* EEPROM Interrupt Level bit 0 position. */ -#define NVM_EELVL1_bm (1<<1) /* EEPROM Interrupt Level bit 1 mask. */ -#define NVM_EELVL1_bp 1 /* EEPROM Interrupt Level bit 1 position. */ - -/* NVM.STATUS bit masks and bit positions */ -#define NVM_NVMBUSY_bm 0x80 /* Non-volatile Memory Busy bit mask. */ -#define NVM_NVMBUSY_bp 7 /* Non-volatile Memory Busy bit position. */ - -#define NVM_FBUSY_bm 0x40 /* Flash Memory Busy bit mask. */ -#define NVM_FBUSY_bp 6 /* Flash Memory Busy bit position. */ - -#define NVM_EELOAD_bm 0x02 /* EEPROM Page Buffer Active Loading bit mask. */ -#define NVM_EELOAD_bp 1 /* EEPROM Page Buffer Active Loading bit position. */ - -#define NVM_FLOAD_bm 0x01 /* Flash Page Buffer Active Loading bit mask. */ -#define NVM_FLOAD_bp 0 /* Flash Page Buffer Active Loading bit position. */ - -/* NVM.LOCKBITS bit masks and bit positions */ -#define NVM_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ -#define NVM_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ -#define NVM_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ -#define NVM_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ -#define NVM_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ -#define NVM_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ - -#define NVM_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ -#define NVM_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ -#define NVM_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ -#define NVM_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ -#define NVM_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ -#define NVM_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ - -#define NVM_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ -#define NVM_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ -#define NVM_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ -#define NVM_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ -#define NVM_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ -#define NVM_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ - -#define NVM_LB_gm 0x03 /* Lock Bits group mask. */ -#define NVM_LB_gp 0 /* Lock Bits group position. */ -#define NVM_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ -#define NVM_LB0_bp 0 /* Lock Bits bit 0 position. */ -#define NVM_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ -#define NVM_LB1_bp 1 /* Lock Bits bit 1 position. */ - -/* ADC - Analog/Digital Converter */ -/* ADC_CH.CTRL bit masks and bit positions */ -#define ADC_CH_START_bm 0x80 /* Channel Start Conversion bit mask. */ -#define ADC_CH_START_bp 7 /* Channel Start Conversion bit position. */ - -#define ADC_CH_GAIN_gm 0x1C /* Gain Factor group mask. */ -#define ADC_CH_GAIN_gp 2 /* Gain Factor group position. */ -#define ADC_CH_GAIN0_bm (1<<2) /* Gain Factor bit 0 mask. */ -#define ADC_CH_GAIN0_bp 2 /* Gain Factor bit 0 position. */ -#define ADC_CH_GAIN1_bm (1<<3) /* Gain Factor bit 1 mask. */ -#define ADC_CH_GAIN1_bp 3 /* Gain Factor bit 1 position. */ -#define ADC_CH_GAIN2_bm (1<<4) /* Gain Factor bit 2 mask. */ -#define ADC_CH_GAIN2_bp 4 /* Gain Factor bit 2 position. */ - -#define ADC_CH_INPUTMODE_gm 0x03 /* Input Mode Select group mask. */ -#define ADC_CH_INPUTMODE_gp 0 /* Input Mode Select group position. */ -#define ADC_CH_INPUTMODE0_bm (1<<0) /* Input Mode Select bit 0 mask. */ -#define ADC_CH_INPUTMODE0_bp 0 /* Input Mode Select bit 0 position. */ -#define ADC_CH_INPUTMODE1_bm (1<<1) /* Input Mode Select bit 1 mask. */ -#define ADC_CH_INPUTMODE1_bp 1 /* Input Mode Select bit 1 position. */ - -/* ADC_CH.MUXCTRL bit masks and bit positions */ -#define ADC_CH_MUXPOS_gm 0x78 /* MUX selection on Positive ADC input group mask. */ -#define ADC_CH_MUXPOS_gp 3 /* MUX selection on Positive ADC input group position. */ -#define ADC_CH_MUXPOS0_bm (1<<3) /* MUX selection on Positive ADC input bit 0 mask. */ -#define ADC_CH_MUXPOS0_bp 3 /* MUX selection on Positive ADC input bit 0 position. */ -#define ADC_CH_MUXPOS1_bm (1<<4) /* MUX selection on Positive ADC input bit 1 mask. */ -#define ADC_CH_MUXPOS1_bp 4 /* MUX selection on Positive ADC input bit 1 position. */ -#define ADC_CH_MUXPOS2_bm (1<<5) /* MUX selection on Positive ADC input bit 2 mask. */ -#define ADC_CH_MUXPOS2_bp 5 /* MUX selection on Positive ADC input bit 2 position. */ -#define ADC_CH_MUXPOS3_bm (1<<6) /* MUX selection on Positive ADC input bit 3 mask. */ -#define ADC_CH_MUXPOS3_bp 6 /* MUX selection on Positive ADC input bit 3 position. */ - -#define ADC_CH_MUXINT_gm 0x78 /* MUX selection on Internal ADC input group mask. */ -#define ADC_CH_MUXINT_gp 3 /* MUX selection on Internal ADC input group position. */ -#define ADC_CH_MUXINT0_bm (1<<3) /* MUX selection on Internal ADC input bit 0 mask. */ -#define ADC_CH_MUXINT0_bp 3 /* MUX selection on Internal ADC input bit 0 position. */ -#define ADC_CH_MUXINT1_bm (1<<4) /* MUX selection on Internal ADC input bit 1 mask. */ -#define ADC_CH_MUXINT1_bp 4 /* MUX selection on Internal ADC input bit 1 position. */ -#define ADC_CH_MUXINT2_bm (1<<5) /* MUX selection on Internal ADC input bit 2 mask. */ -#define ADC_CH_MUXINT2_bp 5 /* MUX selection on Internal ADC input bit 2 position. */ -#define ADC_CH_MUXINT3_bm (1<<6) /* MUX selection on Internal ADC input bit 3 mask. */ -#define ADC_CH_MUXINT3_bp 6 /* MUX selection on Internal ADC input bit 3 position. */ - -#define ADC_CH_MUXNEG_gm 0x07 /* MUX selection on Negative ADC input group mask. */ -#define ADC_CH_MUXNEG_gp 0 /* MUX selection on Negative ADC input group position. */ -#define ADC_CH_MUXNEG0_bm (1<<0) /* MUX selection on Negative ADC input bit 0 mask. */ -#define ADC_CH_MUXNEG0_bp 0 /* MUX selection on Negative ADC input bit 0 position. */ -#define ADC_CH_MUXNEG1_bm (1<<1) /* MUX selection on Negative ADC input bit 1 mask. */ -#define ADC_CH_MUXNEG1_bp 1 /* MUX selection on Negative ADC input bit 1 position. */ -#define ADC_CH_MUXNEG2_bm (1<<2) /* MUX selection on Negative ADC input bit 2 mask. */ -#define ADC_CH_MUXNEG2_bp 2 /* MUX selection on Negative ADC input bit 2 position. */ - -/* ADC_CH.INTCTRL bit masks and bit positions */ -#define ADC_CH_INTMODE_gm 0x0C /* Interrupt Mode group mask. */ -#define ADC_CH_INTMODE_gp 2 /* Interrupt Mode group position. */ -#define ADC_CH_INTMODE0_bm (1<<2) /* Interrupt Mode bit 0 mask. */ -#define ADC_CH_INTMODE0_bp 2 /* Interrupt Mode bit 0 position. */ -#define ADC_CH_INTMODE1_bm (1<<3) /* Interrupt Mode bit 1 mask. */ -#define ADC_CH_INTMODE1_bp 3 /* Interrupt Mode bit 1 position. */ - -#define ADC_CH_INTLVL_gm 0x03 /* Interrupt Level group mask. */ -#define ADC_CH_INTLVL_gp 0 /* Interrupt Level group position. */ -#define ADC_CH_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */ -#define ADC_CH_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */ -#define ADC_CH_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ -#define ADC_CH_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */ - -/* ADC_CH.INTFLAGS bit masks and bit positions */ -#define ADC_CH_CHIF_bm 0x01 /* Channel Interrupt Flag bit mask. */ -#define ADC_CH_CHIF_bp 0 /* Channel Interrupt Flag bit position. */ - -/* ADC_CH.SCAN bit masks and bit positions */ -#define ADC_CH_OFFSET_gm 0xF0 /* Positive MUX setting offset group mask. */ -#define ADC_CH_OFFSET_gp 4 /* Positive MUX setting offset group position. */ -#define ADC_CH_OFFSET0_bm (1<<4) /* Positive MUX setting offset bit 0 mask. */ -#define ADC_CH_OFFSET0_bp 4 /* Positive MUX setting offset bit 0 position. */ -#define ADC_CH_OFFSET1_bm (1<<5) /* Positive MUX setting offset bit 1 mask. */ -#define ADC_CH_OFFSET1_bp 5 /* Positive MUX setting offset bit 1 position. */ -#define ADC_CH_OFFSET2_bm (1<<6) /* Positive MUX setting offset bit 2 mask. */ -#define ADC_CH_OFFSET2_bp 6 /* Positive MUX setting offset bit 2 position. */ -#define ADC_CH_OFFSET3_bm (1<<7) /* Positive MUX setting offset bit 3 mask. */ -#define ADC_CH_OFFSET3_bp 7 /* Positive MUX setting offset bit 3 position. */ - -#define ADC_CH_SCANNUM_gm 0x0F /* Number of Channels included in scan group mask. */ -#define ADC_CH_SCANNUM_gp 0 /* Number of Channels included in scan group position. */ -#define ADC_CH_SCANNUM0_bm (1<<0) /* Number of Channels included in scan bit 0 mask. */ -#define ADC_CH_SCANNUM0_bp 0 /* Number of Channels included in scan bit 0 position. */ -#define ADC_CH_SCANNUM1_bm (1<<1) /* Number of Channels included in scan bit 1 mask. */ -#define ADC_CH_SCANNUM1_bp 1 /* Number of Channels included in scan bit 1 position. */ -#define ADC_CH_SCANNUM2_bm (1<<2) /* Number of Channels included in scan bit 2 mask. */ -#define ADC_CH_SCANNUM2_bp 2 /* Number of Channels included in scan bit 2 position. */ -#define ADC_CH_SCANNUM3_bm (1<<3) /* Number of Channels included in scan bit 3 mask. */ -#define ADC_CH_SCANNUM3_bp 3 /* Number of Channels included in scan bit 3 position. */ - -/* ADC.CTRLA bit masks and bit positions */ -#define ADC_DMASEL_gm 0xC0 /* DMA Selection group mask. */ -#define ADC_DMASEL_gp 6 /* DMA Selection group position. */ -#define ADC_DMASEL0_bm (1<<6) /* DMA Selection bit 0 mask. */ -#define ADC_DMASEL0_bp 6 /* DMA Selection bit 0 position. */ -#define ADC_DMASEL1_bm (1<<7) /* DMA Selection bit 1 mask. */ -#define ADC_DMASEL1_bp 7 /* DMA Selection bit 1 position. */ - -#define ADC_CH3START_bm 0x20 /* Channel 3 Start Conversion bit mask. */ -#define ADC_CH3START_bp 5 /* Channel 3 Start Conversion bit position. */ - -#define ADC_CH2START_bm 0x10 /* Channel 2 Start Conversion bit mask. */ -#define ADC_CH2START_bp 4 /* Channel 2 Start Conversion bit position. */ - -#define ADC_CH1START_bm 0x08 /* Channel 1 Start Conversion bit mask. */ -#define ADC_CH1START_bp 3 /* Channel 1 Start Conversion bit position. */ - -#define ADC_CH0START_bm 0x04 /* Channel 0 Start Conversion bit mask. */ -#define ADC_CH0START_bp 2 /* Channel 0 Start Conversion bit position. */ - -#define ADC_FLUSH_bm 0x02 /* Flush Pipeline bit mask. */ -#define ADC_FLUSH_bp 1 /* Flush Pipeline bit position. */ - -#define ADC_ENABLE_bm 0x01 /* Enable ADC bit mask. */ -#define ADC_ENABLE_bp 0 /* Enable ADC bit position. */ - -/* ADC.CTRLB bit masks and bit positions */ -#define ADC_IMPMODE_bm 0x80 /* Gain Stage Impedance Mode bit mask. */ -#define ADC_IMPMODE_bp 7 /* Gain Stage Impedance Mode bit position. */ - -#define ADC_CURRLIMIT_gm 0x60 /* Current Limitation group mask. */ -#define ADC_CURRLIMIT_gp 5 /* Current Limitation group position. */ -#define ADC_CURRLIMIT0_bm (1<<5) /* Current Limitation bit 0 mask. */ -#define ADC_CURRLIMIT0_bp 5 /* Current Limitation bit 0 position. */ -#define ADC_CURRLIMIT1_bm (1<<6) /* Current Limitation bit 1 mask. */ -#define ADC_CURRLIMIT1_bp 6 /* Current Limitation bit 1 position. */ - -#define ADC_CONMODE_bm 0x10 /* Conversion Mode bit mask. */ -#define ADC_CONMODE_bp 4 /* Conversion Mode bit position. */ - -#define ADC_FREERUN_bm 0x08 /* Free Running Mode Enable bit mask. */ -#define ADC_FREERUN_bp 3 /* Free Running Mode Enable bit position. */ - -#define ADC_RESOLUTION_gm 0x06 /* Result Resolution group mask. */ -#define ADC_RESOLUTION_gp 1 /* Result Resolution group position. */ -#define ADC_RESOLUTION0_bm (1<<1) /* Result Resolution bit 0 mask. */ -#define ADC_RESOLUTION0_bp 1 /* Result Resolution bit 0 position. */ -#define ADC_RESOLUTION1_bm (1<<2) /* Result Resolution bit 1 mask. */ -#define ADC_RESOLUTION1_bp 2 /* Result Resolution bit 1 position. */ - -/* ADC.REFCTRL bit masks and bit positions */ -#define ADC_REFSEL_gm 0x70 /* Reference Selection group mask. */ -#define ADC_REFSEL_gp 4 /* Reference Selection group position. */ -#define ADC_REFSEL0_bm (1<<4) /* Reference Selection bit 0 mask. */ -#define ADC_REFSEL0_bp 4 /* Reference Selection bit 0 position. */ -#define ADC_REFSEL1_bm (1<<5) /* Reference Selection bit 1 mask. */ -#define ADC_REFSEL1_bp 5 /* Reference Selection bit 1 position. */ -#define ADC_REFSEL2_bm (1<<6) /* Reference Selection bit 2 mask. */ -#define ADC_REFSEL2_bp 6 /* Reference Selection bit 2 position. */ - -#define ADC_BANDGAP_bm 0x02 /* Bandgap enable bit mask. */ -#define ADC_BANDGAP_bp 1 /* Bandgap enable bit position. */ - -#define ADC_TEMPREF_bm 0x01 /* Temperature Reference Enable bit mask. */ -#define ADC_TEMPREF_bp 0 /* Temperature Reference Enable bit position. */ - -/* ADC.EVCTRL bit masks and bit positions */ -#define ADC_SWEEP_gm 0xC0 /* Channel Sweep Selection group mask. */ -#define ADC_SWEEP_gp 6 /* Channel Sweep Selection group position. */ -#define ADC_SWEEP0_bm (1<<6) /* Channel Sweep Selection bit 0 mask. */ -#define ADC_SWEEP0_bp 6 /* Channel Sweep Selection bit 0 position. */ -#define ADC_SWEEP1_bm (1<<7) /* Channel Sweep Selection bit 1 mask. */ -#define ADC_SWEEP1_bp 7 /* Channel Sweep Selection bit 1 position. */ - -#define ADC_EVSEL_gm 0x38 /* Event Input Select group mask. */ -#define ADC_EVSEL_gp 3 /* Event Input Select group position. */ -#define ADC_EVSEL0_bm (1<<3) /* Event Input Select bit 0 mask. */ -#define ADC_EVSEL0_bp 3 /* Event Input Select bit 0 position. */ -#define ADC_EVSEL1_bm (1<<4) /* Event Input Select bit 1 mask. */ -#define ADC_EVSEL1_bp 4 /* Event Input Select bit 1 position. */ -#define ADC_EVSEL2_bm (1<<5) /* Event Input Select bit 2 mask. */ -#define ADC_EVSEL2_bp 5 /* Event Input Select bit 2 position. */ - -#define ADC_EVACT_gm 0x07 /* Event Action Select group mask. */ -#define ADC_EVACT_gp 0 /* Event Action Select group position. */ -#define ADC_EVACT0_bm (1<<0) /* Event Action Select bit 0 mask. */ -#define ADC_EVACT0_bp 0 /* Event Action Select bit 0 position. */ -#define ADC_EVACT1_bm (1<<1) /* Event Action Select bit 1 mask. */ -#define ADC_EVACT1_bp 1 /* Event Action Select bit 1 position. */ -#define ADC_EVACT2_bm (1<<2) /* Event Action Select bit 2 mask. */ -#define ADC_EVACT2_bp 2 /* Event Action Select bit 2 position. */ - -/* ADC.PRESCALER bit masks and bit positions */ -#define ADC_PRESCALER_gm 0x07 /* Clock Prescaler Selection group mask. */ -#define ADC_PRESCALER_gp 0 /* Clock Prescaler Selection group position. */ -#define ADC_PRESCALER0_bm (1<<0) /* Clock Prescaler Selection bit 0 mask. */ -#define ADC_PRESCALER0_bp 0 /* Clock Prescaler Selection bit 0 position. */ -#define ADC_PRESCALER1_bm (1<<1) /* Clock Prescaler Selection bit 1 mask. */ -#define ADC_PRESCALER1_bp 1 /* Clock Prescaler Selection bit 1 position. */ -#define ADC_PRESCALER2_bm (1<<2) /* Clock Prescaler Selection bit 2 mask. */ -#define ADC_PRESCALER2_bp 2 /* Clock Prescaler Selection bit 2 position. */ - -/* ADC.INTFLAGS bit masks and bit positions */ -#define ADC_CH3IF_bm 0x08 /* Channel 3 Interrupt Flag bit mask. */ -#define ADC_CH3IF_bp 3 /* Channel 3 Interrupt Flag bit position. */ - -#define ADC_CH2IF_bm 0x04 /* Channel 2 Interrupt Flag bit mask. */ -#define ADC_CH2IF_bp 2 /* Channel 2 Interrupt Flag bit position. */ - -#define ADC_CH1IF_bm 0x02 /* Channel 1 Interrupt Flag bit mask. */ -#define ADC_CH1IF_bp 1 /* Channel 1 Interrupt Flag bit position. */ - -#define ADC_CH0IF_bm 0x01 /* Channel 0 Interrupt Flag bit mask. */ -#define ADC_CH0IF_bp 0 /* Channel 0 Interrupt Flag bit position. */ - -/* DAC - Digital/Analog Converter */ -/* DAC.CTRLA bit masks and bit positions */ -#define DAC_IDOEN_bm 0x10 /* Internal Output Enable bit mask. */ -#define DAC_IDOEN_bp 4 /* Internal Output Enable bit position. */ - -#define DAC_CH1EN_bm 0x08 /* Channel 1 Output Enable bit mask. */ -#define DAC_CH1EN_bp 3 /* Channel 1 Output Enable bit position. */ - -#define DAC_CH0EN_bm 0x04 /* Channel 0 Output Enable bit mask. */ -#define DAC_CH0EN_bp 2 /* Channel 0 Output Enable bit position. */ - -#define DAC_LPMODE_bm 0x02 /* Low Power Mode bit mask. */ -#define DAC_LPMODE_bp 1 /* Low Power Mode bit position. */ - -#define DAC_ENABLE_bm 0x01 /* Enable bit mask. */ -#define DAC_ENABLE_bp 0 /* Enable bit position. */ - -/* DAC.CTRLB bit masks and bit positions */ -#define DAC_CHSEL_gm 0x60 /* Channel Select group mask. */ -#define DAC_CHSEL_gp 5 /* Channel Select group position. */ -#define DAC_CHSEL0_bm (1<<5) /* Channel Select bit 0 mask. */ -#define DAC_CHSEL0_bp 5 /* Channel Select bit 0 position. */ -#define DAC_CHSEL1_bm (1<<6) /* Channel Select bit 1 mask. */ -#define DAC_CHSEL1_bp 6 /* Channel Select bit 1 position. */ - -#define DAC_CH1TRIG_bm 0x02 /* Channel 1 Event Trig Enable bit mask. */ -#define DAC_CH1TRIG_bp 1 /* Channel 1 Event Trig Enable bit position. */ - -#define DAC_CH0TRIG_bm 0x01 /* Channel 0 Event Trig Enable bit mask. */ -#define DAC_CH0TRIG_bp 0 /* Channel 0 Event Trig Enable bit position. */ - -/* DAC.CTRLC bit masks and bit positions */ -#define DAC_REFSEL_gm 0x18 /* Reference Select group mask. */ -#define DAC_REFSEL_gp 3 /* Reference Select group position. */ -#define DAC_REFSEL0_bm (1<<3) /* Reference Select bit 0 mask. */ -#define DAC_REFSEL0_bp 3 /* Reference Select bit 0 position. */ -#define DAC_REFSEL1_bm (1<<4) /* Reference Select bit 1 mask. */ -#define DAC_REFSEL1_bp 4 /* Reference Select bit 1 position. */ - -#define DAC_LEFTADJ_bm 0x01 /* Left-adjust Result bit mask. */ -#define DAC_LEFTADJ_bp 0 /* Left-adjust Result bit position. */ - -/* DAC.EVCTRL bit masks and bit positions */ -#define DAC_EVSPLIT_bm 0x08 /* Separate Event Channel Input for Channel 1 bit mask. */ -#define DAC_EVSPLIT_bp 3 /* Separate Event Channel Input for Channel 1 bit position. */ - -#define DAC_EVSEL_gm 0x07 /* Event Input Selection group mask. */ -#define DAC_EVSEL_gp 0 /* Event Input Selection group position. */ -#define DAC_EVSEL0_bm (1<<0) /* Event Input Selection bit 0 mask. */ -#define DAC_EVSEL0_bp 0 /* Event Input Selection bit 0 position. */ -#define DAC_EVSEL1_bm (1<<1) /* Event Input Selection bit 1 mask. */ -#define DAC_EVSEL1_bp 1 /* Event Input Selection bit 1 position. */ -#define DAC_EVSEL2_bm (1<<2) /* Event Input Selection bit 2 mask. */ -#define DAC_EVSEL2_bp 2 /* Event Input Selection bit 2 position. */ - -/* DAC.STATUS bit masks and bit positions */ -#define DAC_CH1DRE_bm 0x02 /* Channel 1 Data Register Empty bit mask. */ -#define DAC_CH1DRE_bp 1 /* Channel 1 Data Register Empty bit position. */ - -#define DAC_CH0DRE_bm 0x01 /* Channel 0 Data Register Empty bit mask. */ -#define DAC_CH0DRE_bp 0 /* Channel 0 Data Register Empty bit position. */ - -/* DAC.CH0GAINCAL bit masks and bit positions */ -#define DAC_CH0GAINCAL_gm 0x7F /* Gain Calibration group mask. */ -#define DAC_CH0GAINCAL_gp 0 /* Gain Calibration group position. */ -#define DAC_CH0GAINCAL0_bm (1<<0) /* Gain Calibration bit 0 mask. */ -#define DAC_CH0GAINCAL0_bp 0 /* Gain Calibration bit 0 position. */ -#define DAC_CH0GAINCAL1_bm (1<<1) /* Gain Calibration bit 1 mask. */ -#define DAC_CH0GAINCAL1_bp 1 /* Gain Calibration bit 1 position. */ -#define DAC_CH0GAINCAL2_bm (1<<2) /* Gain Calibration bit 2 mask. */ -#define DAC_CH0GAINCAL2_bp 2 /* Gain Calibration bit 2 position. */ -#define DAC_CH0GAINCAL3_bm (1<<3) /* Gain Calibration bit 3 mask. */ -#define DAC_CH0GAINCAL3_bp 3 /* Gain Calibration bit 3 position. */ -#define DAC_CH0GAINCAL4_bm (1<<4) /* Gain Calibration bit 4 mask. */ -#define DAC_CH0GAINCAL4_bp 4 /* Gain Calibration bit 4 position. */ -#define DAC_CH0GAINCAL5_bm (1<<5) /* Gain Calibration bit 5 mask. */ -#define DAC_CH0GAINCAL5_bp 5 /* Gain Calibration bit 5 position. */ -#define DAC_CH0GAINCAL6_bm (1<<6) /* Gain Calibration bit 6 mask. */ -#define DAC_CH0GAINCAL6_bp 6 /* Gain Calibration bit 6 position. */ - -/* DAC.CH0OFFSETCAL bit masks and bit positions */ -#define DAC_CH0OFFSETCAL_gm 0x7F /* Offset Calibration group mask. */ -#define DAC_CH0OFFSETCAL_gp 0 /* Offset Calibration group position. */ -#define DAC_CH0OFFSETCAL0_bm (1<<0) /* Offset Calibration bit 0 mask. */ -#define DAC_CH0OFFSETCAL0_bp 0 /* Offset Calibration bit 0 position. */ -#define DAC_CH0OFFSETCAL1_bm (1<<1) /* Offset Calibration bit 1 mask. */ -#define DAC_CH0OFFSETCAL1_bp 1 /* Offset Calibration bit 1 position. */ -#define DAC_CH0OFFSETCAL2_bm (1<<2) /* Offset Calibration bit 2 mask. */ -#define DAC_CH0OFFSETCAL2_bp 2 /* Offset Calibration bit 2 position. */ -#define DAC_CH0OFFSETCAL3_bm (1<<3) /* Offset Calibration bit 3 mask. */ -#define DAC_CH0OFFSETCAL3_bp 3 /* Offset Calibration bit 3 position. */ -#define DAC_CH0OFFSETCAL4_bm (1<<4) /* Offset Calibration bit 4 mask. */ -#define DAC_CH0OFFSETCAL4_bp 4 /* Offset Calibration bit 4 position. */ -#define DAC_CH0OFFSETCAL5_bm (1<<5) /* Offset Calibration bit 5 mask. */ -#define DAC_CH0OFFSETCAL5_bp 5 /* Offset Calibration bit 5 position. */ -#define DAC_CH0OFFSETCAL6_bm (1<<6) /* Offset Calibration bit 6 mask. */ -#define DAC_CH0OFFSETCAL6_bp 6 /* Offset Calibration bit 6 position. */ - -/* DAC.CH1GAINCAL bit masks and bit positions */ -#define DAC_CH1GAINCAL_gm 0x7F /* Gain Calibration group mask. */ -#define DAC_CH1GAINCAL_gp 0 /* Gain Calibration group position. */ -#define DAC_CH1GAINCAL0_bm (1<<0) /* Gain Calibration bit 0 mask. */ -#define DAC_CH1GAINCAL0_bp 0 /* Gain Calibration bit 0 position. */ -#define DAC_CH1GAINCAL1_bm (1<<1) /* Gain Calibration bit 1 mask. */ -#define DAC_CH1GAINCAL1_bp 1 /* Gain Calibration bit 1 position. */ -#define DAC_CH1GAINCAL2_bm (1<<2) /* Gain Calibration bit 2 mask. */ -#define DAC_CH1GAINCAL2_bp 2 /* Gain Calibration bit 2 position. */ -#define DAC_CH1GAINCAL3_bm (1<<3) /* Gain Calibration bit 3 mask. */ -#define DAC_CH1GAINCAL3_bp 3 /* Gain Calibration bit 3 position. */ -#define DAC_CH1GAINCAL4_bm (1<<4) /* Gain Calibration bit 4 mask. */ -#define DAC_CH1GAINCAL4_bp 4 /* Gain Calibration bit 4 position. */ -#define DAC_CH1GAINCAL5_bm (1<<5) /* Gain Calibration bit 5 mask. */ -#define DAC_CH1GAINCAL5_bp 5 /* Gain Calibration bit 5 position. */ -#define DAC_CH1GAINCAL6_bm (1<<6) /* Gain Calibration bit 6 mask. */ -#define DAC_CH1GAINCAL6_bp 6 /* Gain Calibration bit 6 position. */ - -/* DAC.CH1OFFSETCAL bit masks and bit positions */ -#define DAC_CH1OFFSETCAL_gm 0x7F /* Offset Calibration group mask. */ -#define DAC_CH1OFFSETCAL_gp 0 /* Offset Calibration group position. */ -#define DAC_CH1OFFSETCAL0_bm (1<<0) /* Offset Calibration bit 0 mask. */ -#define DAC_CH1OFFSETCAL0_bp 0 /* Offset Calibration bit 0 position. */ -#define DAC_CH1OFFSETCAL1_bm (1<<1) /* Offset Calibration bit 1 mask. */ -#define DAC_CH1OFFSETCAL1_bp 1 /* Offset Calibration bit 1 position. */ -#define DAC_CH1OFFSETCAL2_bm (1<<2) /* Offset Calibration bit 2 mask. */ -#define DAC_CH1OFFSETCAL2_bp 2 /* Offset Calibration bit 2 position. */ -#define DAC_CH1OFFSETCAL3_bm (1<<3) /* Offset Calibration bit 3 mask. */ -#define DAC_CH1OFFSETCAL3_bp 3 /* Offset Calibration bit 3 position. */ -#define DAC_CH1OFFSETCAL4_bm (1<<4) /* Offset Calibration bit 4 mask. */ -#define DAC_CH1OFFSETCAL4_bp 4 /* Offset Calibration bit 4 position. */ -#define DAC_CH1OFFSETCAL5_bm (1<<5) /* Offset Calibration bit 5 mask. */ -#define DAC_CH1OFFSETCAL5_bp 5 /* Offset Calibration bit 5 position. */ -#define DAC_CH1OFFSETCAL6_bm (1<<6) /* Offset Calibration bit 6 mask. */ -#define DAC_CH1OFFSETCAL6_bp 6 /* Offset Calibration bit 6 position. */ - -/* AC - Analog Comparator */ -/* AC.AC0CTRL bit masks and bit positions */ -#define AC_INTMODE_gm 0xC0 /* Interrupt Mode group mask. */ -#define AC_INTMODE_gp 6 /* Interrupt Mode group position. */ -#define AC_INTMODE0_bm (1<<6) /* Interrupt Mode bit 0 mask. */ -#define AC_INTMODE0_bp 6 /* Interrupt Mode bit 0 position. */ -#define AC_INTMODE1_bm (1<<7) /* Interrupt Mode bit 1 mask. */ -#define AC_INTMODE1_bp 7 /* Interrupt Mode bit 1 position. */ - -#define AC_INTLVL_gm 0x30 /* Interrupt Level group mask. */ -#define AC_INTLVL_gp 4 /* Interrupt Level group position. */ -#define AC_INTLVL0_bm (1<<4) /* Interrupt Level bit 0 mask. */ -#define AC_INTLVL0_bp 4 /* Interrupt Level bit 0 position. */ -#define AC_INTLVL1_bm (1<<5) /* Interrupt Level bit 1 mask. */ -#define AC_INTLVL1_bp 5 /* Interrupt Level bit 1 position. */ - -#define AC_HSMODE_bm 0x08 /* High-speed Mode bit mask. */ -#define AC_HSMODE_bp 3 /* High-speed Mode bit position. */ - -#define AC_HYSMODE_gm 0x06 /* Hysteresis Mode group mask. */ -#define AC_HYSMODE_gp 1 /* Hysteresis Mode group position. */ -#define AC_HYSMODE0_bm (1<<1) /* Hysteresis Mode bit 0 mask. */ -#define AC_HYSMODE0_bp 1 /* Hysteresis Mode bit 0 position. */ -#define AC_HYSMODE1_bm (1<<2) /* Hysteresis Mode bit 1 mask. */ -#define AC_HYSMODE1_bp 2 /* Hysteresis Mode bit 1 position. */ - -#define AC_ENABLE_bm 0x01 /* Enable bit mask. */ -#define AC_ENABLE_bp 0 /* Enable bit position. */ - -/* AC.AC1CTRL bit masks and bit positions */ -/* AC_INTMODE Predefined. */ -/* AC_INTMODE Predefined. */ - -/* AC_INTLVL Predefined. */ -/* AC_INTLVL Predefined. */ - -/* AC_HSMODE Predefined. */ -/* AC_HSMODE Predefined. */ - -/* AC_HYSMODE Predefined. */ -/* AC_HYSMODE Predefined. */ - -/* AC_ENABLE Predefined. */ -/* AC_ENABLE Predefined. */ - -/* AC.AC0MUXCTRL bit masks and bit positions */ -#define AC_MUXPOS_gm 0x38 /* MUX Positive Input group mask. */ -#define AC_MUXPOS_gp 3 /* MUX Positive Input group position. */ -#define AC_MUXPOS0_bm (1<<3) /* MUX Positive Input bit 0 mask. */ -#define AC_MUXPOS0_bp 3 /* MUX Positive Input bit 0 position. */ -#define AC_MUXPOS1_bm (1<<4) /* MUX Positive Input bit 1 mask. */ -#define AC_MUXPOS1_bp 4 /* MUX Positive Input bit 1 position. */ -#define AC_MUXPOS2_bm (1<<5) /* MUX Positive Input bit 2 mask. */ -#define AC_MUXPOS2_bp 5 /* MUX Positive Input bit 2 position. */ - -#define AC_MUXNEG_gm 0x07 /* MUX Negative Input group mask. */ -#define AC_MUXNEG_gp 0 /* MUX Negative Input group position. */ -#define AC_MUXNEG0_bm (1<<0) /* MUX Negative Input bit 0 mask. */ -#define AC_MUXNEG0_bp 0 /* MUX Negative Input bit 0 position. */ -#define AC_MUXNEG1_bm (1<<1) /* MUX Negative Input bit 1 mask. */ -#define AC_MUXNEG1_bp 1 /* MUX Negative Input bit 1 position. */ -#define AC_MUXNEG2_bm (1<<2) /* MUX Negative Input bit 2 mask. */ -#define AC_MUXNEG2_bp 2 /* MUX Negative Input bit 2 position. */ - -/* AC.AC1MUXCTRL bit masks and bit positions */ -/* AC_MUXPOS Predefined. */ -/* AC_MUXPOS Predefined. */ - -/* AC_MUXNEG Predefined. */ -/* AC_MUXNEG Predefined. */ - -/* AC.CTRLA bit masks and bit positions */ -#define AC_AC1OUT_bm 0x02 /* Analog Comparator 1 Output Enable bit mask. */ -#define AC_AC1OUT_bp 1 /* Analog Comparator 1 Output Enable bit position. */ - -#define AC_AC0OUT_bm 0x01 /* Analog Comparator 0 Output Enable bit mask. */ -#define AC_AC0OUT_bp 0 /* Analog Comparator 0 Output Enable bit position. */ - -/* AC.CTRLB bit masks and bit positions */ -#define AC_SCALEFAC_gm 0x3F /* VCC Voltage Scaler Factor group mask. */ -#define AC_SCALEFAC_gp 0 /* VCC Voltage Scaler Factor group position. */ -#define AC_SCALEFAC0_bm (1<<0) /* VCC Voltage Scaler Factor bit 0 mask. */ -#define AC_SCALEFAC0_bp 0 /* VCC Voltage Scaler Factor bit 0 position. */ -#define AC_SCALEFAC1_bm (1<<1) /* VCC Voltage Scaler Factor bit 1 mask. */ -#define AC_SCALEFAC1_bp 1 /* VCC Voltage Scaler Factor bit 1 position. */ -#define AC_SCALEFAC2_bm (1<<2) /* VCC Voltage Scaler Factor bit 2 mask. */ -#define AC_SCALEFAC2_bp 2 /* VCC Voltage Scaler Factor bit 2 position. */ -#define AC_SCALEFAC3_bm (1<<3) /* VCC Voltage Scaler Factor bit 3 mask. */ -#define AC_SCALEFAC3_bp 3 /* VCC Voltage Scaler Factor bit 3 position. */ -#define AC_SCALEFAC4_bm (1<<4) /* VCC Voltage Scaler Factor bit 4 mask. */ -#define AC_SCALEFAC4_bp 4 /* VCC Voltage Scaler Factor bit 4 position. */ -#define AC_SCALEFAC5_bm (1<<5) /* VCC Voltage Scaler Factor bit 5 mask. */ -#define AC_SCALEFAC5_bp 5 /* VCC Voltage Scaler Factor bit 5 position. */ - -/* AC.WINCTRL bit masks and bit positions */ -#define AC_WEN_bm 0x10 /* Window Mode Enable bit mask. */ -#define AC_WEN_bp 4 /* Window Mode Enable bit position. */ - -#define AC_WINTMODE_gm 0x0C /* Window Interrupt Mode group mask. */ -#define AC_WINTMODE_gp 2 /* Window Interrupt Mode group position. */ -#define AC_WINTMODE0_bm (1<<2) /* Window Interrupt Mode bit 0 mask. */ -#define AC_WINTMODE0_bp 2 /* Window Interrupt Mode bit 0 position. */ -#define AC_WINTMODE1_bm (1<<3) /* Window Interrupt Mode bit 1 mask. */ -#define AC_WINTMODE1_bp 3 /* Window Interrupt Mode bit 1 position. */ - -#define AC_WINTLVL_gm 0x03 /* Window Interrupt Level group mask. */ -#define AC_WINTLVL_gp 0 /* Window Interrupt Level group position. */ -#define AC_WINTLVL0_bm (1<<0) /* Window Interrupt Level bit 0 mask. */ -#define AC_WINTLVL0_bp 0 /* Window Interrupt Level bit 0 position. */ -#define AC_WINTLVL1_bm (1<<1) /* Window Interrupt Level bit 1 mask. */ -#define AC_WINTLVL1_bp 1 /* Window Interrupt Level bit 1 position. */ - -/* AC.STATUS bit masks and bit positions */ -#define AC_WSTATE_gm 0xC0 /* Window Mode State group mask. */ -#define AC_WSTATE_gp 6 /* Window Mode State group position. */ -#define AC_WSTATE0_bm (1<<6) /* Window Mode State bit 0 mask. */ -#define AC_WSTATE0_bp 6 /* Window Mode State bit 0 position. */ -#define AC_WSTATE1_bm (1<<7) /* Window Mode State bit 1 mask. */ -#define AC_WSTATE1_bp 7 /* Window Mode State bit 1 position. */ - -#define AC_AC1STATE_bm 0x20 /* Analog Comparator 1 State bit mask. */ -#define AC_AC1STATE_bp 5 /* Analog Comparator 1 State bit position. */ - -#define AC_AC0STATE_bm 0x10 /* Analog Comparator 0 State bit mask. */ -#define AC_AC0STATE_bp 4 /* Analog Comparator 0 State bit position. */ - -#define AC_WIF_bm 0x04 /* Window Mode Interrupt Flag bit mask. */ -#define AC_WIF_bp 2 /* Window Mode Interrupt Flag bit position. */ - -#define AC_AC1IF_bm 0x02 /* Analog Comparator 1 Interrupt Flag bit mask. */ -#define AC_AC1IF_bp 1 /* Analog Comparator 1 Interrupt Flag bit position. */ - -#define AC_AC0IF_bm 0x01 /* Analog Comparator 0 Interrupt Flag bit mask. */ -#define AC_AC0IF_bp 0 /* Analog Comparator 0 Interrupt Flag bit position. */ - -/* RTC - Real-Time Counter */ -/* RTC.CTRL bit masks and bit positions */ -#define RTC_PRESCALER_gm 0x07 /* Prescaling Factor group mask. */ -#define RTC_PRESCALER_gp 0 /* Prescaling Factor group position. */ -#define RTC_PRESCALER0_bm (1<<0) /* Prescaling Factor bit 0 mask. */ -#define RTC_PRESCALER0_bp 0 /* Prescaling Factor bit 0 position. */ -#define RTC_PRESCALER1_bm (1<<1) /* Prescaling Factor bit 1 mask. */ -#define RTC_PRESCALER1_bp 1 /* Prescaling Factor bit 1 position. */ -#define RTC_PRESCALER2_bm (1<<2) /* Prescaling Factor bit 2 mask. */ -#define RTC_PRESCALER2_bp 2 /* Prescaling Factor bit 2 position. */ - -/* RTC.STATUS bit masks and bit positions */ -#define RTC_SYNCBUSY_bm 0x01 /* Synchronization Busy Flag bit mask. */ -#define RTC_SYNCBUSY_bp 0 /* Synchronization Busy Flag bit position. */ - -/* RTC.INTCTRL bit masks and bit positions */ -#define RTC_COMPINTLVL_gm 0x0C /* Compare Match Interrupt Level group mask. */ -#define RTC_COMPINTLVL_gp 2 /* Compare Match Interrupt Level group position. */ -#define RTC_COMPINTLVL0_bm (1<<2) /* Compare Match Interrupt Level bit 0 mask. */ -#define RTC_COMPINTLVL0_bp 2 /* Compare Match Interrupt Level bit 0 position. */ -#define RTC_COMPINTLVL1_bm (1<<3) /* Compare Match Interrupt Level bit 1 mask. */ -#define RTC_COMPINTLVL1_bp 3 /* Compare Match Interrupt Level bit 1 position. */ - -#define RTC_OVFINTLVL_gm 0x03 /* Overflow Interrupt Level group mask. */ -#define RTC_OVFINTLVL_gp 0 /* Overflow Interrupt Level group position. */ -#define RTC_OVFINTLVL0_bm (1<<0) /* Overflow Interrupt Level bit 0 mask. */ -#define RTC_OVFINTLVL0_bp 0 /* Overflow Interrupt Level bit 0 position. */ -#define RTC_OVFINTLVL1_bm (1<<1) /* Overflow Interrupt Level bit 1 mask. */ -#define RTC_OVFINTLVL1_bp 1 /* Overflow Interrupt Level bit 1 position. */ - -/* RTC.INTFLAGS bit masks and bit positions */ -#define RTC_COMPIF_bm 0x02 /* Compare Match Interrupt Flag bit mask. */ -#define RTC_COMPIF_bp 1 /* Compare Match Interrupt Flag bit position. */ - -#define RTC_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ -#define RTC_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ - -/* TWI - Two-Wire Interface */ -/* TWI_MASTER.CTRLA bit masks and bit positions */ -#define TWI_MASTER_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ -#define TWI_MASTER_INTLVL_gp 6 /* Interrupt Level group position. */ -#define TWI_MASTER_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ -#define TWI_MASTER_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ -#define TWI_MASTER_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ -#define TWI_MASTER_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ - -#define TWI_MASTER_RIEN_bm 0x20 /* Read Interrupt Enable bit mask. */ -#define TWI_MASTER_RIEN_bp 5 /* Read Interrupt Enable bit position. */ - -#define TWI_MASTER_WIEN_bm 0x10 /* Write Interrupt Enable bit mask. */ -#define TWI_MASTER_WIEN_bp 4 /* Write Interrupt Enable bit position. */ - -#define TWI_MASTER_ENABLE_bm 0x08 /* Enable TWI Master bit mask. */ -#define TWI_MASTER_ENABLE_bp 3 /* Enable TWI Master bit position. */ - -/* TWI_MASTER.CTRLB bit masks and bit positions */ -#define TWI_MASTER_TIMEOUT_gm 0x0C /* Inactive Bus Timeout group mask. */ -#define TWI_MASTER_TIMEOUT_gp 2 /* Inactive Bus Timeout group position. */ -#define TWI_MASTER_TIMEOUT0_bm (1<<2) /* Inactive Bus Timeout bit 0 mask. */ -#define TWI_MASTER_TIMEOUT0_bp 2 /* Inactive Bus Timeout bit 0 position. */ -#define TWI_MASTER_TIMEOUT1_bm (1<<3) /* Inactive Bus Timeout bit 1 mask. */ -#define TWI_MASTER_TIMEOUT1_bp 3 /* Inactive Bus Timeout bit 1 position. */ - -#define TWI_MASTER_QCEN_bm 0x02 /* Quick Command Enable bit mask. */ -#define TWI_MASTER_QCEN_bp 1 /* Quick Command Enable bit position. */ - -#define TWI_MASTER_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ -#define TWI_MASTER_SMEN_bp 0 /* Smart Mode Enable bit position. */ - -/* TWI_MASTER.CTRLC bit masks and bit positions */ -#define TWI_MASTER_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ -#define TWI_MASTER_ACKACT_bp 2 /* Acknowledge Action bit position. */ - -#define TWI_MASTER_CMD_gm 0x03 /* Command group mask. */ -#define TWI_MASTER_CMD_gp 0 /* Command group position. */ -#define TWI_MASTER_CMD0_bm (1<<0) /* Command bit 0 mask. */ -#define TWI_MASTER_CMD0_bp 0 /* Command bit 0 position. */ -#define TWI_MASTER_CMD1_bm (1<<1) /* Command bit 1 mask. */ -#define TWI_MASTER_CMD1_bp 1 /* Command bit 1 position. */ - -/* TWI_MASTER.STATUS bit masks and bit positions */ -#define TWI_MASTER_RIF_bm 0x80 /* Read Interrupt Flag bit mask. */ -#define TWI_MASTER_RIF_bp 7 /* Read Interrupt Flag bit position. */ - -#define TWI_MASTER_WIF_bm 0x40 /* Write Interrupt Flag bit mask. */ -#define TWI_MASTER_WIF_bp 6 /* Write Interrupt Flag bit position. */ - -#define TWI_MASTER_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ -#define TWI_MASTER_CLKHOLD_bp 5 /* Clock Hold bit position. */ - -#define TWI_MASTER_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ -#define TWI_MASTER_RXACK_bp 4 /* Received Acknowledge bit position. */ - -#define TWI_MASTER_ARBLOST_bm 0x08 /* Arbitration Lost bit mask. */ -#define TWI_MASTER_ARBLOST_bp 3 /* Arbitration Lost bit position. */ - -#define TWI_MASTER_BUSERR_bm 0x04 /* Bus Error bit mask. */ -#define TWI_MASTER_BUSERR_bp 2 /* Bus Error bit position. */ - -#define TWI_MASTER_BUSSTATE_gm 0x03 /* Bus State group mask. */ -#define TWI_MASTER_BUSSTATE_gp 0 /* Bus State group position. */ -#define TWI_MASTER_BUSSTATE0_bm (1<<0) /* Bus State bit 0 mask. */ -#define TWI_MASTER_BUSSTATE0_bp 0 /* Bus State bit 0 position. */ -#define TWI_MASTER_BUSSTATE1_bm (1<<1) /* Bus State bit 1 mask. */ -#define TWI_MASTER_BUSSTATE1_bp 1 /* Bus State bit 1 position. */ - -/* TWI_SLAVE.CTRLA bit masks and bit positions */ -#define TWI_SLAVE_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ -#define TWI_SLAVE_INTLVL_gp 6 /* Interrupt Level group position. */ -#define TWI_SLAVE_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ -#define TWI_SLAVE_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ -#define TWI_SLAVE_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ -#define TWI_SLAVE_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ - -#define TWI_SLAVE_DIEN_bm 0x20 /* Data Interrupt Enable bit mask. */ -#define TWI_SLAVE_DIEN_bp 5 /* Data Interrupt Enable bit position. */ - -#define TWI_SLAVE_APIEN_bm 0x10 /* Address/Stop Interrupt Enable bit mask. */ -#define TWI_SLAVE_APIEN_bp 4 /* Address/Stop Interrupt Enable bit position. */ - -#define TWI_SLAVE_ENABLE_bm 0x08 /* Enable TWI Slave bit mask. */ -#define TWI_SLAVE_ENABLE_bp 3 /* Enable TWI Slave bit position. */ - -#define TWI_SLAVE_PIEN_bm 0x04 /* Stop Interrupt Enable bit mask. */ -#define TWI_SLAVE_PIEN_bp 2 /* Stop Interrupt Enable bit position. */ - -#define TWI_SLAVE_PMEN_bm 0x02 /* Promiscuous Mode Enable bit mask. */ -#define TWI_SLAVE_PMEN_bp 1 /* Promiscuous Mode Enable bit position. */ - -#define TWI_SLAVE_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ -#define TWI_SLAVE_SMEN_bp 0 /* Smart Mode Enable bit position. */ - -/* TWI_SLAVE.CTRLB bit masks and bit positions */ -#define TWI_SLAVE_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ -#define TWI_SLAVE_ACKACT_bp 2 /* Acknowledge Action bit position. */ - -#define TWI_SLAVE_CMD_gm 0x03 /* Command group mask. */ -#define TWI_SLAVE_CMD_gp 0 /* Command group position. */ -#define TWI_SLAVE_CMD0_bm (1<<0) /* Command bit 0 mask. */ -#define TWI_SLAVE_CMD0_bp 0 /* Command bit 0 position. */ -#define TWI_SLAVE_CMD1_bm (1<<1) /* Command bit 1 mask. */ -#define TWI_SLAVE_CMD1_bp 1 /* Command bit 1 position. */ - -/* TWI_SLAVE.STATUS bit masks and bit positions */ -#define TWI_SLAVE_DIF_bm 0x80 /* Data Interrupt Flag bit mask. */ -#define TWI_SLAVE_DIF_bp 7 /* Data Interrupt Flag bit position. */ - -#define TWI_SLAVE_APIF_bm 0x40 /* Address/Stop Interrupt Flag bit mask. */ -#define TWI_SLAVE_APIF_bp 6 /* Address/Stop Interrupt Flag bit position. */ - -#define TWI_SLAVE_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ -#define TWI_SLAVE_CLKHOLD_bp 5 /* Clock Hold bit position. */ - -#define TWI_SLAVE_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ -#define TWI_SLAVE_RXACK_bp 4 /* Received Acknowledge bit position. */ - -#define TWI_SLAVE_COLL_bm 0x08 /* Collision bit mask. */ -#define TWI_SLAVE_COLL_bp 3 /* Collision bit position. */ - -#define TWI_SLAVE_BUSERR_bm 0x04 /* Bus Error bit mask. */ -#define TWI_SLAVE_BUSERR_bp 2 /* Bus Error bit position. */ - -#define TWI_SLAVE_DIR_bm 0x02 /* Read/Write Direction bit mask. */ -#define TWI_SLAVE_DIR_bp 1 /* Read/Write Direction bit position. */ - -#define TWI_SLAVE_AP_bm 0x01 /* Slave Address or Stop bit mask. */ -#define TWI_SLAVE_AP_bp 0 /* Slave Address or Stop bit position. */ - -/* TWI_SLAVE.ADDRMASK bit masks and bit positions */ -#define TWI_SLAVE_ADDRMASK_gm 0xFE /* Address Mask group mask. */ -#define TWI_SLAVE_ADDRMASK_gp 1 /* Address Mask group position. */ -#define TWI_SLAVE_ADDRMASK0_bm (1<<1) /* Address Mask bit 0 mask. */ -#define TWI_SLAVE_ADDRMASK0_bp 1 /* Address Mask bit 0 position. */ -#define TWI_SLAVE_ADDRMASK1_bm (1<<2) /* Address Mask bit 1 mask. */ -#define TWI_SLAVE_ADDRMASK1_bp 2 /* Address Mask bit 1 position. */ -#define TWI_SLAVE_ADDRMASK2_bm (1<<3) /* Address Mask bit 2 mask. */ -#define TWI_SLAVE_ADDRMASK2_bp 3 /* Address Mask bit 2 position. */ -#define TWI_SLAVE_ADDRMASK3_bm (1<<4) /* Address Mask bit 3 mask. */ -#define TWI_SLAVE_ADDRMASK3_bp 4 /* Address Mask bit 3 position. */ -#define TWI_SLAVE_ADDRMASK4_bm (1<<5) /* Address Mask bit 4 mask. */ -#define TWI_SLAVE_ADDRMASK4_bp 5 /* Address Mask bit 4 position. */ -#define TWI_SLAVE_ADDRMASK5_bm (1<<6) /* Address Mask bit 5 mask. */ -#define TWI_SLAVE_ADDRMASK5_bp 6 /* Address Mask bit 5 position. */ -#define TWI_SLAVE_ADDRMASK6_bm (1<<7) /* Address Mask bit 6 mask. */ -#define TWI_SLAVE_ADDRMASK6_bp 7 /* Address Mask bit 6 position. */ - -#define TWI_SLAVE_ADDREN_bm 0x01 /* Address Enable bit mask. */ -#define TWI_SLAVE_ADDREN_bp 0 /* Address Enable bit position. */ - -/* TWI.CTRL bit masks and bit positions */ -#define TWI_SDAHOLD_gm 0x06 /* SDA Hold Time Enable group mask. */ -#define TWI_SDAHOLD_gp 1 /* SDA Hold Time Enable group position. */ -#define TWI_SDAHOLD0_bm (1<<1) /* SDA Hold Time Enable bit 0 mask. */ -#define TWI_SDAHOLD0_bp 1 /* SDA Hold Time Enable bit 0 position. */ -#define TWI_SDAHOLD1_bm (1<<2) /* SDA Hold Time Enable bit 1 mask. */ -#define TWI_SDAHOLD1_bp 2 /* SDA Hold Time Enable bit 1 position. */ - -#define TWI_EDIEN_bm 0x01 /* External Driver Interface Enable bit mask. */ -#define TWI_EDIEN_bp 0 /* External Driver Interface Enable bit position. */ - -/* USB - USB */ -/* USB_EP.STATUS bit masks and bit positions */ -#define USB_EP_STALLF_bm 0x80 /* Endpoint Stall Flag bit mask. */ -#define USB_EP_STALLF_bp 7 /* Endpoint Stall Flag bit position. */ - -#define USB_EP_CRC_bm 0x80 /* CRC Error Flag bit mask. */ -#define USB_EP_CRC_bp 7 /* CRC Error Flag bit position. */ - -#define USB_EP_UNF_bm 0x40 /* Underflow Enpoint FLag bit mask. */ -#define USB_EP_UNF_bp 6 /* Underflow Enpoint FLag bit position. */ - -#define USB_EP_OVF_bm 0x40 /* Overflow Enpoint Flag for Output Endpoints bit mask. */ -#define USB_EP_OVF_bp 6 /* Overflow Enpoint Flag for Output Endpoints bit position. */ - -#define USB_EP_TRNCOMPL0_bm 0x20 /* Transaction Complete 0 Flag bit mask. */ -#define USB_EP_TRNCOMPL0_bp 5 /* Transaction Complete 0 Flag bit position. */ - -#define USB_EP_TRNCOMPL1_bm 0x10 /* Transaction Complete 1 Flag bit mask. */ -#define USB_EP_TRNCOMPL1_bp 4 /* Transaction Complete 1 Flag bit position. */ - -#define USB_EP_SETUP_bm 0x10 /* SETUP Transaction Complete Flag bit mask. */ -#define USB_EP_SETUP_bp 4 /* SETUP Transaction Complete Flag bit position. */ - -#define USB_EP_BANK_bm 0x08 /* Bank Select bit mask. */ -#define USB_EP_BANK_bp 3 /* Bank Select bit position. */ - -#define USB_EP_BUSNACK1_bm 0x04 /* Data Buffer 1 Not Acknowledge bit mask. */ -#define USB_EP_BUSNACK1_bp 2 /* Data Buffer 1 Not Acknowledge bit position. */ - -#define USB_EP_BUSNACK0_bm 0x02 /* Data Buffer 0 Not Acknowledge bit mask. */ -#define USB_EP_BUSNACK0_bp 1 /* Data Buffer 0 Not Acknowledge bit position. */ - -#define USB_EP_TOGGLE_bm 0x01 /* Data Toggle bit mask. */ -#define USB_EP_TOGGLE_bp 0 /* Data Toggle bit position. */ - -/* USB_EP.CTRL bit masks and bit positions */ -#define USB_EP_TYPE_gm 0xC0 /* Endpoint Type group mask. */ -#define USB_EP_TYPE_gp 6 /* Endpoint Type group position. */ -#define USB_EP_TYPE0_bm (1<<6) /* Endpoint Type bit 0 mask. */ -#define USB_EP_TYPE0_bp 6 /* Endpoint Type bit 0 position. */ -#define USB_EP_TYPE1_bm (1<<7) /* Endpoint Type bit 1 mask. */ -#define USB_EP_TYPE1_bp 7 /* Endpoint Type bit 1 position. */ - -#define USB_EP_MULTIPKT_bm 0x20 /* Multi Packet Transfer Enable bit mask. */ -#define USB_EP_MULTIPKT_bp 5 /* Multi Packet Transfer Enable bit position. */ - -#define USB_EP_PINGPONG_bm 0x10 /* Ping-Pong Enable bit mask. */ -#define USB_EP_PINGPONG_bp 4 /* Ping-Pong Enable bit position. */ - -#define USB_EP_INTDSBL_bm 0x08 /* Interrupt Disable bit mask. */ -#define USB_EP_INTDSBL_bp 3 /* Interrupt Disable bit position. */ - -#define USB_EP_STALL_bm 0x04 /* Data Stall bit mask. */ -#define USB_EP_STALL_bp 2 /* Data Stall bit position. */ - -#define USB_EP_BUFSIZE_gm 0x07 /* Data Buffer Size group mask. */ -#define USB_EP_BUFSIZE_gp 0 /* Data Buffer Size group position. */ -#define USB_EP_BUFSIZE0_bm (1<<0) /* Data Buffer Size bit 0 mask. */ -#define USB_EP_BUFSIZE0_bp 0 /* Data Buffer Size bit 0 position. */ -#define USB_EP_BUFSIZE1_bm (1<<1) /* Data Buffer Size bit 1 mask. */ -#define USB_EP_BUFSIZE1_bp 1 /* Data Buffer Size bit 1 position. */ -#define USB_EP_BUFSIZE2_bm (1<<2) /* Data Buffer Size bit 2 mask. */ -#define USB_EP_BUFSIZE2_bp 2 /* Data Buffer Size bit 2 position. */ - -/* USB_EP.CNT bit masks and bit positions */ -#define USB_EP_ZLP_bm 0x8000 /* Zero Length Packet bit mask. */ -#define USB_EP_ZLP_bp 15 /* Zero Length Packet bit position. */ - -/* USB.CTRLA bit masks and bit positions */ -#define USB_ENABLE_bm 0x80 /* USB Enable bit mask. */ -#define USB_ENABLE_bp 7 /* USB Enable bit position. */ - -#define USB_SPEED_bm 0x40 /* Speed Select bit mask. */ -#define USB_SPEED_bp 6 /* Speed Select bit position. */ - -#define USB_FIFOEN_bm 0x20 /* USB FIFO Enable bit mask. */ -#define USB_FIFOEN_bp 5 /* USB FIFO Enable bit position. */ - -#define USB_STFRNUM_bm 0x10 /* Store Frame Number Enable bit mask. */ -#define USB_STFRNUM_bp 4 /* Store Frame Number Enable bit position. */ - -#define USB_MAXEP_gm 0x0F /* Maximum Endpoint Addresses group mask. */ -#define USB_MAXEP_gp 0 /* Maximum Endpoint Addresses group position. */ -#define USB_MAXEP0_bm (1<<0) /* Maximum Endpoint Addresses bit 0 mask. */ -#define USB_MAXEP0_bp 0 /* Maximum Endpoint Addresses bit 0 position. */ -#define USB_MAXEP1_bm (1<<1) /* Maximum Endpoint Addresses bit 1 mask. */ -#define USB_MAXEP1_bp 1 /* Maximum Endpoint Addresses bit 1 position. */ -#define USB_MAXEP2_bm (1<<2) /* Maximum Endpoint Addresses bit 2 mask. */ -#define USB_MAXEP2_bp 2 /* Maximum Endpoint Addresses bit 2 position. */ -#define USB_MAXEP3_bm (1<<3) /* Maximum Endpoint Addresses bit 3 mask. */ -#define USB_MAXEP3_bp 3 /* Maximum Endpoint Addresses bit 3 position. */ - -/* USB.CTRLB bit masks and bit positions */ -#define USB_PULLRST_bm 0x10 /* Pull during Reset bit mask. */ -#define USB_PULLRST_bp 4 /* Pull during Reset bit position. */ - -#define USB_RWAKEUP_bm 0x04 /* Remote Wake-up bit mask. */ -#define USB_RWAKEUP_bp 2 /* Remote Wake-up bit position. */ - -#define USB_GNACK_bm 0x02 /* Global NACK bit mask. */ -#define USB_GNACK_bp 1 /* Global NACK bit position. */ - -#define USB_ATTACH_bm 0x01 /* Attach bit mask. */ -#define USB_ATTACH_bp 0 /* Attach bit position. */ - -/* USB.STATUS bit masks and bit positions */ -#define USB_URESUME_bm 0x08 /* Upstream Resume bit mask. */ -#define USB_URESUME_bp 3 /* Upstream Resume bit position. */ - -#define USB_RESUME_bm 0x04 /* Resume bit mask. */ -#define USB_RESUME_bp 2 /* Resume bit position. */ - -#define USB_SUSPEND_bm 0x02 /* Bus Suspended bit mask. */ -#define USB_SUSPEND_bp 1 /* Bus Suspended bit position. */ - -#define USB_BUSRST_bm 0x01 /* Bus Reset bit mask. */ -#define USB_BUSRST_bp 0 /* Bus Reset bit position. */ - -/* USB.ADDR bit masks and bit positions */ -#define USB_ADDR_gm 0x7F /* Device Address group mask. */ -#define USB_ADDR_gp 0 /* Device Address group position. */ -#define USB_ADDR0_bm (1<<0) /* Device Address bit 0 mask. */ -#define USB_ADDR0_bp 0 /* Device Address bit 0 position. */ -#define USB_ADDR1_bm (1<<1) /* Device Address bit 1 mask. */ -#define USB_ADDR1_bp 1 /* Device Address bit 1 position. */ -#define USB_ADDR2_bm (1<<2) /* Device Address bit 2 mask. */ -#define USB_ADDR2_bp 2 /* Device Address bit 2 position. */ -#define USB_ADDR3_bm (1<<3) /* Device Address bit 3 mask. */ -#define USB_ADDR3_bp 3 /* Device Address bit 3 position. */ -#define USB_ADDR4_bm (1<<4) /* Device Address bit 4 mask. */ -#define USB_ADDR4_bp 4 /* Device Address bit 4 position. */ -#define USB_ADDR5_bm (1<<5) /* Device Address bit 5 mask. */ -#define USB_ADDR5_bp 5 /* Device Address bit 5 position. */ -#define USB_ADDR6_bm (1<<6) /* Device Address bit 6 mask. */ -#define USB_ADDR6_bp 6 /* Device Address bit 6 position. */ - -/* USB.FIFOWP bit masks and bit positions */ -#define USB_FIFOWP_gm 0x1F /* FIFO Write Pointer group mask. */ -#define USB_FIFOWP_gp 0 /* FIFO Write Pointer group position. */ -#define USB_FIFOWP0_bm (1<<0) /* FIFO Write Pointer bit 0 mask. */ -#define USB_FIFOWP0_bp 0 /* FIFO Write Pointer bit 0 position. */ -#define USB_FIFOWP1_bm (1<<1) /* FIFO Write Pointer bit 1 mask. */ -#define USB_FIFOWP1_bp 1 /* FIFO Write Pointer bit 1 position. */ -#define USB_FIFOWP2_bm (1<<2) /* FIFO Write Pointer bit 2 mask. */ -#define USB_FIFOWP2_bp 2 /* FIFO Write Pointer bit 2 position. */ -#define USB_FIFOWP3_bm (1<<3) /* FIFO Write Pointer bit 3 mask. */ -#define USB_FIFOWP3_bp 3 /* FIFO Write Pointer bit 3 position. */ -#define USB_FIFOWP4_bm (1<<4) /* FIFO Write Pointer bit 4 mask. */ -#define USB_FIFOWP4_bp 4 /* FIFO Write Pointer bit 4 position. */ - -/* USB.FIFORP bit masks and bit positions */ -#define USB_FIFORP_gm 0x1F /* FIFO Read Pointer group mask. */ -#define USB_FIFORP_gp 0 /* FIFO Read Pointer group position. */ -#define USB_FIFORP0_bm (1<<0) /* FIFO Read Pointer bit 0 mask. */ -#define USB_FIFORP0_bp 0 /* FIFO Read Pointer bit 0 position. */ -#define USB_FIFORP1_bm (1<<1) /* FIFO Read Pointer bit 1 mask. */ -#define USB_FIFORP1_bp 1 /* FIFO Read Pointer bit 1 position. */ -#define USB_FIFORP2_bm (1<<2) /* FIFO Read Pointer bit 2 mask. */ -#define USB_FIFORP2_bp 2 /* FIFO Read Pointer bit 2 position. */ -#define USB_FIFORP3_bm (1<<3) /* FIFO Read Pointer bit 3 mask. */ -#define USB_FIFORP3_bp 3 /* FIFO Read Pointer bit 3 position. */ -#define USB_FIFORP4_bm (1<<4) /* FIFO Read Pointer bit 4 mask. */ -#define USB_FIFORP4_bp 4 /* FIFO Read Pointer bit 4 position. */ - -/* USB.INTCTRLA bit masks and bit positions */ -#define USB_SOFIE_bm 0x80 /* Start Of Frame Interrupt Enable bit mask. */ -#define USB_SOFIE_bp 7 /* Start Of Frame Interrupt Enable bit position. */ - -#define USB_BUSEVIE_bm 0x40 /* Bus Event Interrupt Enable bit mask. */ -#define USB_BUSEVIE_bp 6 /* Bus Event Interrupt Enable bit position. */ - -#define USB_BUSERRIE_bm 0x20 /* Bus Error Interrupt Enable bit mask. */ -#define USB_BUSERRIE_bp 5 /* Bus Error Interrupt Enable bit position. */ - -#define USB_STALLIE_bm 0x10 /* STALL Interrupt Enable bit mask. */ -#define USB_STALLIE_bp 4 /* STALL Interrupt Enable bit position. */ - -#define USB_INTLVL_gm 0x03 /* Interrupt Level group mask. */ -#define USB_INTLVL_gp 0 /* Interrupt Level group position. */ -#define USB_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */ -#define USB_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */ -#define USB_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ -#define USB_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */ - -/* USB.INTCTRLB bit masks and bit positions */ -#define USB_TRNIE_bm 0x02 /* Transaction Complete Interrupt Enable bit mask. */ -#define USB_TRNIE_bp 1 /* Transaction Complete Interrupt Enable bit position. */ - -#define USB_SETUPIE_bm 0x01 /* SETUP Transaction Complete Interrupt Enable bit mask. */ -#define USB_SETUPIE_bp 0 /* SETUP Transaction Complete Interrupt Enable bit position. */ - -/* USB.INTFLAGSACLR bit masks and bit positions */ -#define USB_SOFIF_bm 0x80 /* Start Of Frame Interrupt Flag bit mask. */ -#define USB_SOFIF_bp 7 /* Start Of Frame Interrupt Flag bit position. */ - -#define USB_SUSPENDIF_bm 0x40 /* Suspend Interrupt Flag bit mask. */ -#define USB_SUSPENDIF_bp 6 /* Suspend Interrupt Flag bit position. */ - -#define USB_RESUMEIF_bm 0x20 /* Resume Interrupt Flag bit mask. */ -#define USB_RESUMEIF_bp 5 /* Resume Interrupt Flag bit position. */ - -#define USB_RSTIF_bm 0x10 /* Reset Interrupt Flag bit mask. */ -#define USB_RSTIF_bp 4 /* Reset Interrupt Flag bit position. */ - -#define USB_CRCIF_bm 0x08 /* Isochronous CRC Error Interrupt Flag bit mask. */ -#define USB_CRCIF_bp 3 /* Isochronous CRC Error Interrupt Flag bit position. */ - -#define USB_UNFIF_bm 0x04 /* Underflow Interrupt Flag bit mask. */ -#define USB_UNFIF_bp 2 /* Underflow Interrupt Flag bit position. */ - -#define USB_OVFIF_bm 0x02 /* Overflow Interrupt Flag bit mask. */ -#define USB_OVFIF_bp 1 /* Overflow Interrupt Flag bit position. */ - -#define USB_STALLIF_bm 0x01 /* STALL Interrupt Flag bit mask. */ -#define USB_STALLIF_bp 0 /* STALL Interrupt Flag bit position. */ - -/* USB.INTFLAGSASET bit masks and bit positions */ -/* USB_SOFIF Predefined. */ -/* USB_SOFIF Predefined. */ - -/* USB_SUSPENDIF Predefined. */ -/* USB_SUSPENDIF Predefined. */ - -/* USB_RESUMEIF Predefined. */ -/* USB_RESUMEIF Predefined. */ - -/* USB_RSTIF Predefined. */ -/* USB_RSTIF Predefined. */ - -/* USB_CRCIF Predefined. */ -/* USB_CRCIF Predefined. */ - -/* USB_UNFIF Predefined. */ -/* USB_UNFIF Predefined. */ - -/* USB_OVFIF Predefined. */ -/* USB_OVFIF Predefined. */ - -/* USB_STALLIF Predefined. */ -/* USB_STALLIF Predefined. */ - -/* USB.INTFLAGSBCLR bit masks and bit positions */ -#define USB_TRNIF_bm 0x02 /* Transaction Complete Interrupt Flag bit mask. */ -#define USB_TRNIF_bp 1 /* Transaction Complete Interrupt Flag bit position. */ - -#define USB_SETUPIF_bm 0x01 /* SETUP Transaction Complete Interrupt Flag bit mask. */ -#define USB_SETUPIF_bp 0 /* SETUP Transaction Complete Interrupt Flag bit position. */ - -/* USB.INTFLAGSBSET bit masks and bit positions */ -/* USB_TRNIF Predefined. */ -/* USB_TRNIF Predefined. */ - -/* USB_SETUPIF Predefined. */ -/* USB_SETUPIF Predefined. */ - -/* PORT - I/O Port Configuration */ -/* PORT.INTCTRL bit masks and bit positions */ -#define PORT_INT1LVL_gm 0x0C /* Port Interrupt 1 Level group mask. */ -#define PORT_INT1LVL_gp 2 /* Port Interrupt 1 Level group position. */ -#define PORT_INT1LVL0_bm (1<<2) /* Port Interrupt 1 Level bit 0 mask. */ -#define PORT_INT1LVL0_bp 2 /* Port Interrupt 1 Level bit 0 position. */ -#define PORT_INT1LVL1_bm (1<<3) /* Port Interrupt 1 Level bit 1 mask. */ -#define PORT_INT1LVL1_bp 3 /* Port Interrupt 1 Level bit 1 position. */ - -#define PORT_INT0LVL_gm 0x03 /* Port Interrupt 0 Level group mask. */ -#define PORT_INT0LVL_gp 0 /* Port Interrupt 0 Level group position. */ -#define PORT_INT0LVL0_bm (1<<0) /* Port Interrupt 0 Level bit 0 mask. */ -#define PORT_INT0LVL0_bp 0 /* Port Interrupt 0 Level bit 0 position. */ -#define PORT_INT0LVL1_bm (1<<1) /* Port Interrupt 0 Level bit 1 mask. */ -#define PORT_INT0LVL1_bp 1 /* Port Interrupt 0 Level bit 1 position. */ - -/* PORT.INTFLAGS bit masks and bit positions */ -#define PORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ -#define PORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ - -#define PORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ -#define PORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ - -/* PORT.REMAP bit masks and bit positions */ -#define PORT_SPI_bm 0x20 /* SPI bit mask. */ -#define PORT_SPI_bp 5 /* SPI bit position. */ - -#define PORT_USART0_bm 0x10 /* USART0 bit mask. */ -#define PORT_USART0_bp 4 /* USART0 bit position. */ - -#define PORT_TC0D_bm 0x08 /* Timer/Counter 0 Output Compare D bit mask. */ -#define PORT_TC0D_bp 3 /* Timer/Counter 0 Output Compare D bit position. */ - -#define PORT_TC0C_bm 0x04 /* Timer/Counter 0 Output Compare C bit mask. */ -#define PORT_TC0C_bp 2 /* Timer/Counter 0 Output Compare C bit position. */ - -#define PORT_TC0B_bm 0x02 /* Timer/Counter 0 Output Compare B bit mask. */ -#define PORT_TC0B_bp 1 /* Timer/Counter 0 Output Compare B bit position. */ - -#define PORT_TC0A_bm 0x01 /* Timer/Counter 0 Output Compare A bit mask. */ -#define PORT_TC0A_bp 0 /* Timer/Counter 0 Output Compare A bit position. */ - -/* PORT.PIN0CTRL bit masks and bit positions */ -#define PORT_SRLEN_bm 0x80 /* Slew Rate Enable bit mask. */ -#define PORT_SRLEN_bp 7 /* Slew Rate Enable bit position. */ - -#define PORT_INVEN_bm 0x40 /* Inverted I/O Enable bit mask. */ -#define PORT_INVEN_bp 6 /* Inverted I/O Enable bit position. */ - -#define PORT_OPC_gm 0x38 /* Output/Pull Configuration group mask. */ -#define PORT_OPC_gp 3 /* Output/Pull Configuration group position. */ -#define PORT_OPC0_bm (1<<3) /* Output/Pull Configuration bit 0 mask. */ -#define PORT_OPC0_bp 3 /* Output/Pull Configuration bit 0 position. */ -#define PORT_OPC1_bm (1<<4) /* Output/Pull Configuration bit 1 mask. */ -#define PORT_OPC1_bp 4 /* Output/Pull Configuration bit 1 position. */ -#define PORT_OPC2_bm (1<<5) /* Output/Pull Configuration bit 2 mask. */ -#define PORT_OPC2_bp 5 /* Output/Pull Configuration bit 2 position. */ - -#define PORT_ISC_gm 0x07 /* Input/Sense Configuration group mask. */ -#define PORT_ISC_gp 0 /* Input/Sense Configuration group position. */ -#define PORT_ISC0_bm (1<<0) /* Input/Sense Configuration bit 0 mask. */ -#define PORT_ISC0_bp 0 /* Input/Sense Configuration bit 0 position. */ -#define PORT_ISC1_bm (1<<1) /* Input/Sense Configuration bit 1 mask. */ -#define PORT_ISC1_bp 1 /* Input/Sense Configuration bit 1 position. */ -#define PORT_ISC2_bm (1<<2) /* Input/Sense Configuration bit 2 mask. */ -#define PORT_ISC2_bp 2 /* Input/Sense Configuration bit 2 position. */ - -/* PORT.PIN1CTRL bit masks and bit positions */ -/* PORT_SRLEN Predefined. */ -/* PORT_SRLEN Predefined. */ - -/* PORT_INVEN Predefined. */ -/* PORT_INVEN Predefined. */ - -/* PORT_OPC Predefined. */ -/* PORT_OPC Predefined. */ - -/* PORT_ISC Predefined. */ -/* PORT_ISC Predefined. */ - -/* PORT.PIN2CTRL bit masks and bit positions */ -/* PORT_SRLEN Predefined. */ -/* PORT_SRLEN Predefined. */ - -/* PORT_INVEN Predefined. */ -/* PORT_INVEN Predefined. */ - -/* PORT_OPC Predefined. */ -/* PORT_OPC Predefined. */ - -/* PORT_ISC Predefined. */ -/* PORT_ISC Predefined. */ - -/* PORT.PIN3CTRL bit masks and bit positions */ -/* PORT_SRLEN Predefined. */ -/* PORT_SRLEN Predefined. */ - -/* PORT_INVEN Predefined. */ -/* PORT_INVEN Predefined. */ - -/* PORT_OPC Predefined. */ -/* PORT_OPC Predefined. */ - -/* PORT_ISC Predefined. */ -/* PORT_ISC Predefined. */ - -/* PORT.PIN4CTRL bit masks and bit positions */ -/* PORT_SRLEN Predefined. */ -/* PORT_SRLEN Predefined. */ - -/* PORT_INVEN Predefined. */ -/* PORT_INVEN Predefined. */ - -/* PORT_OPC Predefined. */ -/* PORT_OPC Predefined. */ - -/* PORT_ISC Predefined. */ -/* PORT_ISC Predefined. */ - -/* PORT.PIN5CTRL bit masks and bit positions */ -/* PORT_SRLEN Predefined. */ -/* PORT_SRLEN Predefined. */ - -/* PORT_INVEN Predefined. */ -/* PORT_INVEN Predefined. */ - -/* PORT_OPC Predefined. */ -/* PORT_OPC Predefined. */ - -/* PORT_ISC Predefined. */ -/* PORT_ISC Predefined. */ - -/* PORT.PIN6CTRL bit masks and bit positions */ -/* PORT_SRLEN Predefined. */ -/* PORT_SRLEN Predefined. */ - -/* PORT_INVEN Predefined. */ -/* PORT_INVEN Predefined. */ - -/* PORT_OPC Predefined. */ -/* PORT_OPC Predefined. */ - -/* PORT_ISC Predefined. */ -/* PORT_ISC Predefined. */ - -/* PORT.PIN7CTRL bit masks and bit positions */ -/* PORT_SRLEN Predefined. */ -/* PORT_SRLEN Predefined. */ - -/* PORT_INVEN Predefined. */ -/* PORT_INVEN Predefined. */ - -/* PORT_OPC Predefined. */ -/* PORT_OPC Predefined. */ - -/* PORT_ISC Predefined. */ -/* PORT_ISC Predefined. */ - -/* TC - 16-bit Timer/Counter With PWM */ -/* TC0.CTRLA bit masks and bit positions */ -#define TC0_CLKSEL_gm 0x0F /* Clock Selection group mask. */ -#define TC0_CLKSEL_gp 0 /* Clock Selection group position. */ -#define TC0_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ -#define TC0_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ -#define TC0_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ -#define TC0_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ -#define TC0_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ -#define TC0_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ -#define TC0_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ -#define TC0_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ - -/* TC0.CTRLB bit masks and bit positions */ -#define TC0_CCDEN_bm 0x80 /* Compare or Capture D Enable bit mask. */ -#define TC0_CCDEN_bp 7 /* Compare or Capture D Enable bit position. */ - -#define TC0_CCCEN_bm 0x40 /* Compare or Capture C Enable bit mask. */ -#define TC0_CCCEN_bp 6 /* Compare or Capture C Enable bit position. */ - -#define TC0_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ -#define TC0_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ - -#define TC0_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ -#define TC0_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ - -#define TC0_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ -#define TC0_WGMODE_gp 0 /* Waveform generation mode group position. */ -#define TC0_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ -#define TC0_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ -#define TC0_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ -#define TC0_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ -#define TC0_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ -#define TC0_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ - -/* TC0.CTRLC bit masks and bit positions */ -#define TC0_CMPD_bm 0x08 /* Compare D Output Value bit mask. */ -#define TC0_CMPD_bp 3 /* Compare D Output Value bit position. */ - -#define TC0_CMPC_bm 0x04 /* Compare C Output Value bit mask. */ -#define TC0_CMPC_bp 2 /* Compare C Output Value bit position. */ - -#define TC0_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ -#define TC0_CMPB_bp 1 /* Compare B Output Value bit position. */ - -#define TC0_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ -#define TC0_CMPA_bp 0 /* Compare A Output Value bit position. */ - -/* TC0.CTRLD bit masks and bit positions */ -#define TC0_EVACT_gm 0xE0 /* Event Action group mask. */ -#define TC0_EVACT_gp 5 /* Event Action group position. */ -#define TC0_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ -#define TC0_EVACT0_bp 5 /* Event Action bit 0 position. */ -#define TC0_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ -#define TC0_EVACT1_bp 6 /* Event Action bit 1 position. */ -#define TC0_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ -#define TC0_EVACT2_bp 7 /* Event Action bit 2 position. */ - -#define TC0_EVDLY_bm 0x10 /* Event Delay bit mask. */ -#define TC0_EVDLY_bp 4 /* Event Delay bit position. */ - -#define TC0_EVSEL_gm 0x0F /* Event Source Select group mask. */ -#define TC0_EVSEL_gp 0 /* Event Source Select group position. */ -#define TC0_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ -#define TC0_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ -#define TC0_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ -#define TC0_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ -#define TC0_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ -#define TC0_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ -#define TC0_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ -#define TC0_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ - -/* TC0.CTRLE bit masks and bit positions */ -#define TC0_BYTEM_gm 0x03 /* Byte Mode group mask. */ -#define TC0_BYTEM_gp 0 /* Byte Mode group position. */ -#define TC0_BYTEM0_bm (1<<0) /* Byte Mode bit 0 mask. */ -#define TC0_BYTEM0_bp 0 /* Byte Mode bit 0 position. */ -#define TC0_BYTEM1_bm (1<<1) /* Byte Mode bit 1 mask. */ -#define TC0_BYTEM1_bp 1 /* Byte Mode bit 1 position. */ - -/* TC0.INTCTRLA bit masks and bit positions */ -#define TC0_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ -#define TC0_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ -#define TC0_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ -#define TC0_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ -#define TC0_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ -#define TC0_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ - -#define TC0_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ -#define TC0_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ -#define TC0_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ -#define TC0_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ -#define TC0_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ -#define TC0_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ - -/* TC0.INTCTRLB bit masks and bit positions */ -#define TC0_CCDINTLVL_gm 0xC0 /* Compare or Capture D Interrupt Level group mask. */ -#define TC0_CCDINTLVL_gp 6 /* Compare or Capture D Interrupt Level group position. */ -#define TC0_CCDINTLVL0_bm (1<<6) /* Compare or Capture D Interrupt Level bit 0 mask. */ -#define TC0_CCDINTLVL0_bp 6 /* Compare or Capture D Interrupt Level bit 0 position. */ -#define TC0_CCDINTLVL1_bm (1<<7) /* Compare or Capture D Interrupt Level bit 1 mask. */ -#define TC0_CCDINTLVL1_bp 7 /* Compare or Capture D Interrupt Level bit 1 position. */ - -#define TC0_CCCINTLVL_gm 0x30 /* Compare or Capture C Interrupt Level group mask. */ -#define TC0_CCCINTLVL_gp 4 /* Compare or Capture C Interrupt Level group position. */ -#define TC0_CCCINTLVL0_bm (1<<4) /* Compare or Capture C Interrupt Level bit 0 mask. */ -#define TC0_CCCINTLVL0_bp 4 /* Compare or Capture C Interrupt Level bit 0 position. */ -#define TC0_CCCINTLVL1_bm (1<<5) /* Compare or Capture C Interrupt Level bit 1 mask. */ -#define TC0_CCCINTLVL1_bp 5 /* Compare or Capture C Interrupt Level bit 1 position. */ - -#define TC0_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ -#define TC0_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ -#define TC0_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ -#define TC0_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ -#define TC0_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ -#define TC0_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ - -#define TC0_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ -#define TC0_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ -#define TC0_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ -#define TC0_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ -#define TC0_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ -#define TC0_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ - -/* TC0.CTRLFCLR bit masks and bit positions */ -#define TC0_CMD_gm 0x0C /* Command group mask. */ -#define TC0_CMD_gp 2 /* Command group position. */ -#define TC0_CMD0_bm (1<<2) /* Command bit 0 mask. */ -#define TC0_CMD0_bp 2 /* Command bit 0 position. */ -#define TC0_CMD1_bm (1<<3) /* Command bit 1 mask. */ -#define TC0_CMD1_bp 3 /* Command bit 1 position. */ - -#define TC0_LUPD_bm 0x02 /* Lock Update bit mask. */ -#define TC0_LUPD_bp 1 /* Lock Update bit position. */ - -#define TC0_DIR_bm 0x01 /* Direction bit mask. */ -#define TC0_DIR_bp 0 /* Direction bit position. */ - -/* TC0.CTRLFSET bit masks and bit positions */ -/* TC0_CMD Predefined. */ -/* TC0_CMD Predefined. */ - -/* TC0_LUPD Predefined. */ -/* TC0_LUPD Predefined. */ - -/* TC0_DIR Predefined. */ -/* TC0_DIR Predefined. */ - -/* TC0.CTRLGCLR bit masks and bit positions */ -#define TC0_CCDBV_bm 0x10 /* Compare or Capture D Buffer Valid bit mask. */ -#define TC0_CCDBV_bp 4 /* Compare or Capture D Buffer Valid bit position. */ - -#define TC0_CCCBV_bm 0x08 /* Compare or Capture C Buffer Valid bit mask. */ -#define TC0_CCCBV_bp 3 /* Compare or Capture C Buffer Valid bit position. */ - -#define TC0_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ -#define TC0_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ - -#define TC0_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ -#define TC0_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ - -#define TC0_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ -#define TC0_PERBV_bp 0 /* Period Buffer Valid bit position. */ - -/* TC0.CTRLGSET bit masks and bit positions */ -/* TC0_CCDBV Predefined. */ -/* TC0_CCDBV Predefined. */ - -/* TC0_CCCBV Predefined. */ -/* TC0_CCCBV Predefined. */ - -/* TC0_CCBBV Predefined. */ -/* TC0_CCBBV Predefined. */ - -/* TC0_CCABV Predefined. */ -/* TC0_CCABV Predefined. */ - -/* TC0_PERBV Predefined. */ -/* TC0_PERBV Predefined. */ - -/* TC0.INTFLAGS bit masks and bit positions */ -#define TC0_CCDIF_bm 0x80 /* Compare or Capture D Interrupt Flag bit mask. */ -#define TC0_CCDIF_bp 7 /* Compare or Capture D Interrupt Flag bit position. */ - -#define TC0_CCCIF_bm 0x40 /* Compare or Capture C Interrupt Flag bit mask. */ -#define TC0_CCCIF_bp 6 /* Compare or Capture C Interrupt Flag bit position. */ - -#define TC0_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ -#define TC0_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ - -#define TC0_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ -#define TC0_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ - -#define TC0_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ -#define TC0_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ - -#define TC0_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ -#define TC0_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ - -/* TC1.CTRLA bit masks and bit positions */ -#define TC1_CLKSEL_gm 0x0F /* Clock Selection group mask. */ -#define TC1_CLKSEL_gp 0 /* Clock Selection group position. */ -#define TC1_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ -#define TC1_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ -#define TC1_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ -#define TC1_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ -#define TC1_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ -#define TC1_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ -#define TC1_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ -#define TC1_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ - -/* TC1.CTRLB bit masks and bit positions */ -#define TC1_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ -#define TC1_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ - -#define TC1_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ -#define TC1_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ - -#define TC1_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ -#define TC1_WGMODE_gp 0 /* Waveform generation mode group position. */ -#define TC1_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ -#define TC1_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ -#define TC1_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ -#define TC1_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ -#define TC1_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ -#define TC1_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ - -/* TC1.CTRLC bit masks and bit positions */ -#define TC1_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ -#define TC1_CMPB_bp 1 /* Compare B Output Value bit position. */ - -#define TC1_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ -#define TC1_CMPA_bp 0 /* Compare A Output Value bit position. */ - -/* TC1.CTRLD bit masks and bit positions */ -#define TC1_EVACT_gm 0xE0 /* Event Action group mask. */ -#define TC1_EVACT_gp 5 /* Event Action group position. */ -#define TC1_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ -#define TC1_EVACT0_bp 5 /* Event Action bit 0 position. */ -#define TC1_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ -#define TC1_EVACT1_bp 6 /* Event Action bit 1 position. */ -#define TC1_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ -#define TC1_EVACT2_bp 7 /* Event Action bit 2 position. */ - -#define TC1_EVDLY_bm 0x10 /* Event Delay bit mask. */ -#define TC1_EVDLY_bp 4 /* Event Delay bit position. */ - -#define TC1_EVSEL_gm 0x0F /* Event Source Select group mask. */ -#define TC1_EVSEL_gp 0 /* Event Source Select group position. */ -#define TC1_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ -#define TC1_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ -#define TC1_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ -#define TC1_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ -#define TC1_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ -#define TC1_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ -#define TC1_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ -#define TC1_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ - -/* TC1.CTRLE bit masks and bit positions */ -#define TC1_BYTEM_bm 0x01 /* Byte Mode bit mask. */ -#define TC1_BYTEM_bp 0 /* Byte Mode bit position. */ - -/* TC1.INTCTRLA bit masks and bit positions */ -#define TC1_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ -#define TC1_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ -#define TC1_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ -#define TC1_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ -#define TC1_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ -#define TC1_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ - -#define TC1_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ -#define TC1_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ -#define TC1_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ -#define TC1_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ -#define TC1_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ -#define TC1_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ - -/* TC1.INTCTRLB bit masks and bit positions */ -#define TC1_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ -#define TC1_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ -#define TC1_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ -#define TC1_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ -#define TC1_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ -#define TC1_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ - -#define TC1_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ -#define TC1_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ -#define TC1_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ -#define TC1_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ -#define TC1_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ -#define TC1_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ - -/* TC1.CTRLFCLR bit masks and bit positions */ -#define TC1_CMD_gm 0x0C /* Command group mask. */ -#define TC1_CMD_gp 2 /* Command group position. */ -#define TC1_CMD0_bm (1<<2) /* Command bit 0 mask. */ -#define TC1_CMD0_bp 2 /* Command bit 0 position. */ -#define TC1_CMD1_bm (1<<3) /* Command bit 1 mask. */ -#define TC1_CMD1_bp 3 /* Command bit 1 position. */ - -#define TC1_LUPD_bm 0x02 /* Lock Update bit mask. */ -#define TC1_LUPD_bp 1 /* Lock Update bit position. */ - -#define TC1_DIR_bm 0x01 /* Direction bit mask. */ -#define TC1_DIR_bp 0 /* Direction bit position. */ - -/* TC1.CTRLFSET bit masks and bit positions */ -/* TC1_CMD Predefined. */ -/* TC1_CMD Predefined. */ - -/* TC1_LUPD Predefined. */ -/* TC1_LUPD Predefined. */ - -/* TC1_DIR Predefined. */ -/* TC1_DIR Predefined. */ - -/* TC1.CTRLGCLR bit masks and bit positions */ -#define TC1_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ -#define TC1_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ - -#define TC1_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ -#define TC1_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ - -#define TC1_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ -#define TC1_PERBV_bp 0 /* Period Buffer Valid bit position. */ - -/* TC1.CTRLGSET bit masks and bit positions */ -/* TC1_CCBBV Predefined. */ -/* TC1_CCBBV Predefined. */ - -/* TC1_CCABV Predefined. */ -/* TC1_CCABV Predefined. */ - -/* TC1_PERBV Predefined. */ -/* TC1_PERBV Predefined. */ - -/* TC1.INTFLAGS bit masks and bit positions */ -#define TC1_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ -#define TC1_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ - -#define TC1_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ -#define TC1_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ - -#define TC1_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ -#define TC1_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ - -#define TC1_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ -#define TC1_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ - -/* TC2 - 16-bit Timer/Counter type 2 */ -/* TC2.CTRLA bit masks and bit positions */ -#define TC2_CLKSEL_gm 0x0F /* Clock Selection group mask. */ -#define TC2_CLKSEL_gp 0 /* Clock Selection group position. */ -#define TC2_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ -#define TC2_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ -#define TC2_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ -#define TC2_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ -#define TC2_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ -#define TC2_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ -#define TC2_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ -#define TC2_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ - -/* TC2.CTRLB bit masks and bit positions */ -#define TC2_HCMPDEN_bm 0x80 /* High Byte Compare D Enable bit mask. */ -#define TC2_HCMPDEN_bp 7 /* High Byte Compare D Enable bit position. */ - -#define TC2_HCMPCEN_bm 0x40 /* High Byte Compare C Enable bit mask. */ -#define TC2_HCMPCEN_bp 6 /* High Byte Compare C Enable bit position. */ - -#define TC2_HCMPBEN_bm 0x20 /* High Byte Compare B Enable bit mask. */ -#define TC2_HCMPBEN_bp 5 /* High Byte Compare B Enable bit position. */ - -#define TC2_HCMPAEN_bm 0x10 /* High Byte Compare A Enable bit mask. */ -#define TC2_HCMPAEN_bp 4 /* High Byte Compare A Enable bit position. */ - -#define TC2_LCMPDEN_bm 0x08 /* Low Byte Compare D Enable bit mask. */ -#define TC2_LCMPDEN_bp 3 /* Low Byte Compare D Enable bit position. */ - -#define TC2_LCMPCEN_bm 0x04 /* Low Byte Compare C Enable bit mask. */ -#define TC2_LCMPCEN_bp 2 /* Low Byte Compare C Enable bit position. */ - -#define TC2_LCMPBEN_bm 0x02 /* Low Byte Compare B Enable bit mask. */ -#define TC2_LCMPBEN_bp 1 /* Low Byte Compare B Enable bit position. */ - -#define TC2_LCMPAEN_bm 0x01 /* Low Byte Compare A Enable bit mask. */ -#define TC2_LCMPAEN_bp 0 /* Low Byte Compare A Enable bit position. */ - -/* TC2.CTRLC bit masks and bit positions */ -#define TC2_HCMPD_bm 0x80 /* High Byte Compare D Output Value bit mask. */ -#define TC2_HCMPD_bp 7 /* High Byte Compare D Output Value bit position. */ - -#define TC2_HCMPC_bm 0x40 /* High Byte Compare C Output Value bit mask. */ -#define TC2_HCMPC_bp 6 /* High Byte Compare C Output Value bit position. */ - -#define TC2_HCMPB_bm 0x20 /* High Byte Compare B Output Value bit mask. */ -#define TC2_HCMPB_bp 5 /* High Byte Compare B Output Value bit position. */ - -#define TC2_HCMPA_bm 0x10 /* High Byte Compare A Output Value bit mask. */ -#define TC2_HCMPA_bp 4 /* High Byte Compare A Output Value bit position. */ - -#define TC2_LCMPD_bm 0x08 /* Low Byte Compare D Output Value bit mask. */ -#define TC2_LCMPD_bp 3 /* Low Byte Compare D Output Value bit position. */ - -#define TC2_LCMPC_bm 0x04 /* Low Byte Compare C Output Value bit mask. */ -#define TC2_LCMPC_bp 2 /* Low Byte Compare C Output Value bit position. */ - -#define TC2_LCMPB_bm 0x02 /* Low Byte Compare B Output Value bit mask. */ -#define TC2_LCMPB_bp 1 /* Low Byte Compare B Output Value bit position. */ - -#define TC2_LCMPA_bm 0x01 /* Low Byte Compare A Output Value bit mask. */ -#define TC2_LCMPA_bp 0 /* Low Byte Compare A Output Value bit position. */ - -/* TC2.CTRLE bit masks and bit positions */ -#define TC2_BYTEM_gm 0x03 /* Byte Mode group mask. */ -#define TC2_BYTEM_gp 0 /* Byte Mode group position. */ -#define TC2_BYTEM0_bm (1<<0) /* Byte Mode bit 0 mask. */ -#define TC2_BYTEM0_bp 0 /* Byte Mode bit 0 position. */ -#define TC2_BYTEM1_bm (1<<1) /* Byte Mode bit 1 mask. */ -#define TC2_BYTEM1_bp 1 /* Byte Mode bit 1 position. */ - -/* TC2.INTCTRLA bit masks and bit positions */ -#define TC2_HUNFINTLVL_gm 0x0C /* High Byte Underflow Interrupt Level group mask. */ -#define TC2_HUNFINTLVL_gp 2 /* High Byte Underflow Interrupt Level group position. */ -#define TC2_HUNFINTLVL0_bm (1<<2) /* High Byte Underflow Interrupt Level bit 0 mask. */ -#define TC2_HUNFINTLVL0_bp 2 /* High Byte Underflow Interrupt Level bit 0 position. */ -#define TC2_HUNFINTLVL1_bm (1<<3) /* High Byte Underflow Interrupt Level bit 1 mask. */ -#define TC2_HUNFINTLVL1_bp 3 /* High Byte Underflow Interrupt Level bit 1 position. */ - -#define TC2_LUNFINTLVL_gm 0x03 /* Low Byte Underflow interrupt level group mask. */ -#define TC2_LUNFINTLVL_gp 0 /* Low Byte Underflow interrupt level group position. */ -#define TC2_LUNFINTLVL0_bm (1<<0) /* Low Byte Underflow interrupt level bit 0 mask. */ -#define TC2_LUNFINTLVL0_bp 0 /* Low Byte Underflow interrupt level bit 0 position. */ -#define TC2_LUNFINTLVL1_bm (1<<1) /* Low Byte Underflow interrupt level bit 1 mask. */ -#define TC2_LUNFINTLVL1_bp 1 /* Low Byte Underflow interrupt level bit 1 position. */ - -/* TC2.INTCTRLB bit masks and bit positions */ -#define TC2_LCMPDINTLVL_gm 0xC0 /* Low Byte Compare D Interrupt Level group mask. */ -#define TC2_LCMPDINTLVL_gp 6 /* Low Byte Compare D Interrupt Level group position. */ -#define TC2_LCMPDINTLVL0_bm (1<<6) /* Low Byte Compare D Interrupt Level bit 0 mask. */ -#define TC2_LCMPDINTLVL0_bp 6 /* Low Byte Compare D Interrupt Level bit 0 position. */ -#define TC2_LCMPDINTLVL1_bm (1<<7) /* Low Byte Compare D Interrupt Level bit 1 mask. */ -#define TC2_LCMPDINTLVL1_bp 7 /* Low Byte Compare D Interrupt Level bit 1 position. */ - -#define TC2_LCMPCINTLVL_gm 0x30 /* Low Byte Compare C Interrupt Level group mask. */ -#define TC2_LCMPCINTLVL_gp 4 /* Low Byte Compare C Interrupt Level group position. */ -#define TC2_LCMPCINTLVL0_bm (1<<4) /* Low Byte Compare C Interrupt Level bit 0 mask. */ -#define TC2_LCMPCINTLVL0_bp 4 /* Low Byte Compare C Interrupt Level bit 0 position. */ -#define TC2_LCMPCINTLVL1_bm (1<<5) /* Low Byte Compare C Interrupt Level bit 1 mask. */ -#define TC2_LCMPCINTLVL1_bp 5 /* Low Byte Compare C Interrupt Level bit 1 position. */ - -#define TC2_LCMPBINTLVL_gm 0x0C /* Low Byte Compare B Interrupt Level group mask. */ -#define TC2_LCMPBINTLVL_gp 2 /* Low Byte Compare B Interrupt Level group position. */ -#define TC2_LCMPBINTLVL0_bm (1<<2) /* Low Byte Compare B Interrupt Level bit 0 mask. */ -#define TC2_LCMPBINTLVL0_bp 2 /* Low Byte Compare B Interrupt Level bit 0 position. */ -#define TC2_LCMPBINTLVL1_bm (1<<3) /* Low Byte Compare B Interrupt Level bit 1 mask. */ -#define TC2_LCMPBINTLVL1_bp 3 /* Low Byte Compare B Interrupt Level bit 1 position. */ - -#define TC2_LCMPAINTLVL_gm 0x03 /* Low Byte Compare A Interrupt Level group mask. */ -#define TC2_LCMPAINTLVL_gp 0 /* Low Byte Compare A Interrupt Level group position. */ -#define TC2_LCMPAINTLVL0_bm (1<<0) /* Low Byte Compare A Interrupt Level bit 0 mask. */ -#define TC2_LCMPAINTLVL0_bp 0 /* Low Byte Compare A Interrupt Level bit 0 position. */ -#define TC2_LCMPAINTLVL1_bm (1<<1) /* Low Byte Compare A Interrupt Level bit 1 mask. */ -#define TC2_LCMPAINTLVL1_bp 1 /* Low Byte Compare A Interrupt Level bit 1 position. */ - -/* TC2.CTRLF bit masks and bit positions */ -#define TC2_CMD_gm 0x0C /* Command group mask. */ -#define TC2_CMD_gp 2 /* Command group position. */ -#define TC2_CMD0_bm (1<<2) /* Command bit 0 mask. */ -#define TC2_CMD0_bp 2 /* Command bit 0 position. */ -#define TC2_CMD1_bm (1<<3) /* Command bit 1 mask. */ -#define TC2_CMD1_bp 3 /* Command bit 1 position. */ - -#define TC2_CMDEN_gm 0x03 /* Command Enable group mask. */ -#define TC2_CMDEN_gp 0 /* Command Enable group position. */ -#define TC2_CMDEN0_bm (1<<0) /* Command Enable bit 0 mask. */ -#define TC2_CMDEN0_bp 0 /* Command Enable bit 0 position. */ -#define TC2_CMDEN1_bm (1<<1) /* Command Enable bit 1 mask. */ -#define TC2_CMDEN1_bp 1 /* Command Enable bit 1 position. */ - -/* TC2.INTFLAGS bit masks and bit positions */ -#define TC2_LCMPDIF_bm 0x80 /* Low Byte Compare D Interrupt Flag bit mask. */ -#define TC2_LCMPDIF_bp 7 /* Low Byte Compare D Interrupt Flag bit position. */ - -#define TC2_LCMPCIF_bm 0x40 /* Low Byte Compare C Interrupt Flag bit mask. */ -#define TC2_LCMPCIF_bp 6 /* Low Byte Compare C Interrupt Flag bit position. */ - -#define TC2_LCMPBIF_bm 0x20 /* Low Byte Compare B Interrupt Flag bit mask. */ -#define TC2_LCMPBIF_bp 5 /* Low Byte Compare B Interrupt Flag bit position. */ - -#define TC2_LCMPAIF_bm 0x10 /* Low Byte Compare A Interrupt Flag bit mask. */ -#define TC2_LCMPAIF_bp 4 /* Low Byte Compare A Interrupt Flag bit position. */ - -#define TC2_HUNFIF_bm 0x02 /* High Byte Underflow Interrupt Flag bit mask. */ -#define TC2_HUNFIF_bp 1 /* High Byte Underflow Interrupt Flag bit position. */ - -#define TC2_LUNFIF_bm 0x01 /* Low Byte Underflow Interrupt Flag bit mask. */ -#define TC2_LUNFIF_bp 0 /* Low Byte Underflow Interrupt Flag bit position. */ - -/* AWEX - Timer/Counter Advanced Waveform Extension */ -/* AWEX.CTRL bit masks and bit positions */ -#define AWEX_PGM_bm 0x20 /* Pattern Generation Mode bit mask. */ -#define AWEX_PGM_bp 5 /* Pattern Generation Mode bit position. */ - -#define AWEX_CWCM_bm 0x10 /* Common Waveform Channel Mode bit mask. */ -#define AWEX_CWCM_bp 4 /* Common Waveform Channel Mode bit position. */ - -#define AWEX_DTICCDEN_bm 0x08 /* Dead Time Insertion Compare Channel D Enable bit mask. */ -#define AWEX_DTICCDEN_bp 3 /* Dead Time Insertion Compare Channel D Enable bit position. */ - -#define AWEX_DTICCCEN_bm 0x04 /* Dead Time Insertion Compare Channel C Enable bit mask. */ -#define AWEX_DTICCCEN_bp 2 /* Dead Time Insertion Compare Channel C Enable bit position. */ - -#define AWEX_DTICCBEN_bm 0x02 /* Dead Time Insertion Compare Channel B Enable bit mask. */ -#define AWEX_DTICCBEN_bp 1 /* Dead Time Insertion Compare Channel B Enable bit position. */ - -#define AWEX_DTICCAEN_bm 0x01 /* Dead Time Insertion Compare Channel A Enable bit mask. */ -#define AWEX_DTICCAEN_bp 0 /* Dead Time Insertion Compare Channel A Enable bit position. */ - -/* AWEX.FDCTRL bit masks and bit positions */ -#define AWEX_FDDBD_bm 0x10 /* Fault Detect on Disable Break Disable bit mask. */ -#define AWEX_FDDBD_bp 4 /* Fault Detect on Disable Break Disable bit position. */ - -#define AWEX_FDMODE_bm 0x04 /* Fault Detect Mode bit mask. */ -#define AWEX_FDMODE_bp 2 /* Fault Detect Mode bit position. */ - -#define AWEX_FDACT_gm 0x03 /* Fault Detect Action group mask. */ -#define AWEX_FDACT_gp 0 /* Fault Detect Action group position. */ -#define AWEX_FDACT0_bm (1<<0) /* Fault Detect Action bit 0 mask. */ -#define AWEX_FDACT0_bp 0 /* Fault Detect Action bit 0 position. */ -#define AWEX_FDACT1_bm (1<<1) /* Fault Detect Action bit 1 mask. */ -#define AWEX_FDACT1_bp 1 /* Fault Detect Action bit 1 position. */ - -/* AWEX.STATUS bit masks and bit positions */ -#define AWEX_FDF_bm 0x04 /* Fault Detect Flag bit mask. */ -#define AWEX_FDF_bp 2 /* Fault Detect Flag bit position. */ - -#define AWEX_DTHSBUFV_bm 0x02 /* Dead Time High Side Buffer Valid bit mask. */ -#define AWEX_DTHSBUFV_bp 1 /* Dead Time High Side Buffer Valid bit position. */ - -#define AWEX_DTLSBUFV_bm 0x01 /* Dead Time Low Side Buffer Valid bit mask. */ -#define AWEX_DTLSBUFV_bp 0 /* Dead Time Low Side Buffer Valid bit position. */ - -/* AWEX.STATUSSET bit masks and bit positions */ -/* AWEX_FDF Predefined. */ -/* AWEX_FDF Predefined. */ - -/* AWEX_DTHSBUFV Predefined. */ -/* AWEX_DTHSBUFV Predefined. */ - -/* AWEX_DTLSBUFV Predefined. */ -/* AWEX_DTLSBUFV Predefined. */ - -/* HIRES - Timer/Counter High-Resolution Extension */ -/* HIRES.CTRLA bit masks and bit positions */ -#define HIRES_HREN_gm 0x03 /* High Resolution Enable group mask. */ -#define HIRES_HREN_gp 0 /* High Resolution Enable group position. */ -#define HIRES_HREN0_bm (1<<0) /* High Resolution Enable bit 0 mask. */ -#define HIRES_HREN0_bp 0 /* High Resolution Enable bit 0 position. */ -#define HIRES_HREN1_bm (1<<1) /* High Resolution Enable bit 1 mask. */ -#define HIRES_HREN1_bp 1 /* High Resolution Enable bit 1 position. */ - -/* USART - Universal Asynchronous Receiver-Transmitter */ -/* USART.STATUS bit masks and bit positions */ -#define USART_RXCIF_bm 0x80 /* Receive Interrupt Flag bit mask. */ -#define USART_RXCIF_bp 7 /* Receive Interrupt Flag bit position. */ - -#define USART_TXCIF_bm 0x40 /* Transmit Interrupt Flag bit mask. */ -#define USART_TXCIF_bp 6 /* Transmit Interrupt Flag bit position. */ - -#define USART_DREIF_bm 0x20 /* Data Register Empty Flag bit mask. */ -#define USART_DREIF_bp 5 /* Data Register Empty Flag bit position. */ - -#define USART_FERR_bm 0x10 /* Frame Error bit mask. */ -#define USART_FERR_bp 4 /* Frame Error bit position. */ - -#define USART_BUFOVF_bm 0x08 /* Buffer Overflow bit mask. */ -#define USART_BUFOVF_bp 3 /* Buffer Overflow bit position. */ - -#define USART_PERR_bm 0x04 /* Parity Error bit mask. */ -#define USART_PERR_bp 2 /* Parity Error bit position. */ - -#define USART_RXB8_bm 0x01 /* Receive Bit 8 bit mask. */ -#define USART_RXB8_bp 0 /* Receive Bit 8 bit position. */ - -/* USART.CTRLA bit masks and bit positions */ -#define USART_RXCINTLVL_gm 0x30 /* Receive Interrupt Level group mask. */ -#define USART_RXCINTLVL_gp 4 /* Receive Interrupt Level group position. */ -#define USART_RXCINTLVL0_bm (1<<4) /* Receive Interrupt Level bit 0 mask. */ -#define USART_RXCINTLVL0_bp 4 /* Receive Interrupt Level bit 0 position. */ -#define USART_RXCINTLVL1_bm (1<<5) /* Receive Interrupt Level bit 1 mask. */ -#define USART_RXCINTLVL1_bp 5 /* Receive Interrupt Level bit 1 position. */ - -#define USART_TXCINTLVL_gm 0x0C /* Transmit Interrupt Level group mask. */ -#define USART_TXCINTLVL_gp 2 /* Transmit Interrupt Level group position. */ -#define USART_TXCINTLVL0_bm (1<<2) /* Transmit Interrupt Level bit 0 mask. */ -#define USART_TXCINTLVL0_bp 2 /* Transmit Interrupt Level bit 0 position. */ -#define USART_TXCINTLVL1_bm (1<<3) /* Transmit Interrupt Level bit 1 mask. */ -#define USART_TXCINTLVL1_bp 3 /* Transmit Interrupt Level bit 1 position. */ - -#define USART_DREINTLVL_gm 0x03 /* Data Register Empty Interrupt Level group mask. */ -#define USART_DREINTLVL_gp 0 /* Data Register Empty Interrupt Level group position. */ -#define USART_DREINTLVL0_bm (1<<0) /* Data Register Empty Interrupt Level bit 0 mask. */ -#define USART_DREINTLVL0_bp 0 /* Data Register Empty Interrupt Level bit 0 position. */ -#define USART_DREINTLVL1_bm (1<<1) /* Data Register Empty Interrupt Level bit 1 mask. */ -#define USART_DREINTLVL1_bp 1 /* Data Register Empty Interrupt Level bit 1 position. */ - -/* USART.CTRLB bit masks and bit positions */ -#define USART_RXEN_bm 0x10 /* Receiver Enable bit mask. */ -#define USART_RXEN_bp 4 /* Receiver Enable bit position. */ - -#define USART_TXEN_bm 0x08 /* Transmitter Enable bit mask. */ -#define USART_TXEN_bp 3 /* Transmitter Enable bit position. */ - -#define USART_CLK2X_bm 0x04 /* Double transmission speed bit mask. */ -#define USART_CLK2X_bp 2 /* Double transmission speed bit position. */ - -#define USART_MPCM_bm 0x02 /* Multi-processor Communication Mode bit mask. */ -#define USART_MPCM_bp 1 /* Multi-processor Communication Mode bit position. */ - -#define USART_TXB8_bm 0x01 /* Transmit bit 8 bit mask. */ -#define USART_TXB8_bp 0 /* Transmit bit 8 bit position. */ - -/* USART.CTRLC bit masks and bit positions */ -#define USART_CMODE_gm 0xC0 /* Communication Mode group mask. */ -#define USART_CMODE_gp 6 /* Communication Mode group position. */ -#define USART_CMODE0_bm (1<<6) /* Communication Mode bit 0 mask. */ -#define USART_CMODE0_bp 6 /* Communication Mode bit 0 position. */ -#define USART_CMODE1_bm (1<<7) /* Communication Mode bit 1 mask. */ -#define USART_CMODE1_bp 7 /* Communication Mode bit 1 position. */ - -#define USART_PMODE_gm 0x30 /* Parity Mode group mask. */ -#define USART_PMODE_gp 4 /* Parity Mode group position. */ -#define USART_PMODE0_bm (1<<4) /* Parity Mode bit 0 mask. */ -#define USART_PMODE0_bp 4 /* Parity Mode bit 0 position. */ -#define USART_PMODE1_bm (1<<5) /* Parity Mode bit 1 mask. */ -#define USART_PMODE1_bp 5 /* Parity Mode bit 1 position. */ - -#define USART_SBMODE_bm 0x08 /* Stop Bit Mode bit mask. */ -#define USART_SBMODE_bp 3 /* Stop Bit Mode bit position. */ - -#define USART_CHSIZE_gm 0x07 /* Character Size group mask. */ -#define USART_CHSIZE_gp 0 /* Character Size group position. */ -#define USART_CHSIZE0_bm (1<<0) /* Character Size bit 0 mask. */ -#define USART_CHSIZE0_bp 0 /* Character Size bit 0 position. */ -#define USART_CHSIZE1_bm (1<<1) /* Character Size bit 1 mask. */ -#define USART_CHSIZE1_bp 1 /* Character Size bit 1 position. */ -#define USART_CHSIZE2_bm (1<<2) /* Character Size bit 2 mask. */ -#define USART_CHSIZE2_bp 2 /* Character Size bit 2 position. */ - -/* USART.BAUDCTRLA bit masks and bit positions */ -#define USART_BSEL_gm 0xFF /* Baud Rate Selection Bits [7:0] group mask. */ -#define USART_BSEL_gp 0 /* Baud Rate Selection Bits [7:0] group position. */ -#define USART_BSEL0_bm (1<<0) /* Baud Rate Selection Bits [7:0] bit 0 mask. */ -#define USART_BSEL0_bp 0 /* Baud Rate Selection Bits [7:0] bit 0 position. */ -#define USART_BSEL1_bm (1<<1) /* Baud Rate Selection Bits [7:0] bit 1 mask. */ -#define USART_BSEL1_bp 1 /* Baud Rate Selection Bits [7:0] bit 1 position. */ -#define USART_BSEL2_bm (1<<2) /* Baud Rate Selection Bits [7:0] bit 2 mask. */ -#define USART_BSEL2_bp 2 /* Baud Rate Selection Bits [7:0] bit 2 position. */ -#define USART_BSEL3_bm (1<<3) /* Baud Rate Selection Bits [7:0] bit 3 mask. */ -#define USART_BSEL3_bp 3 /* Baud Rate Selection Bits [7:0] bit 3 position. */ -#define USART_BSEL4_bm (1<<4) /* Baud Rate Selection Bits [7:0] bit 4 mask. */ -#define USART_BSEL4_bp 4 /* Baud Rate Selection Bits [7:0] bit 4 position. */ -#define USART_BSEL5_bm (1<<5) /* Baud Rate Selection Bits [7:0] bit 5 mask. */ -#define USART_BSEL5_bp 5 /* Baud Rate Selection Bits [7:0] bit 5 position. */ -#define USART_BSEL6_bm (1<<6) /* Baud Rate Selection Bits [7:0] bit 6 mask. */ -#define USART_BSEL6_bp 6 /* Baud Rate Selection Bits [7:0] bit 6 position. */ -#define USART_BSEL7_bm (1<<7) /* Baud Rate Selection Bits [7:0] bit 7 mask. */ -#define USART_BSEL7_bp 7 /* Baud Rate Selection Bits [7:0] bit 7 position. */ - -/* USART.BAUDCTRLB bit masks and bit positions */ -#define USART_BSCALE_gm 0xF0 /* Baud Rate Scale group mask. */ -#define USART_BSCALE_gp 4 /* Baud Rate Scale group position. */ -#define USART_BSCALE0_bm (1<<4) /* Baud Rate Scale bit 0 mask. */ -#define USART_BSCALE0_bp 4 /* Baud Rate Scale bit 0 position. */ -#define USART_BSCALE1_bm (1<<5) /* Baud Rate Scale bit 1 mask. */ -#define USART_BSCALE1_bp 5 /* Baud Rate Scale bit 1 position. */ -#define USART_BSCALE2_bm (1<<6) /* Baud Rate Scale bit 2 mask. */ -#define USART_BSCALE2_bp 6 /* Baud Rate Scale bit 2 position. */ -#define USART_BSCALE3_bm (1<<7) /* Baud Rate Scale bit 3 mask. */ -#define USART_BSCALE3_bp 7 /* Baud Rate Scale bit 3 position. */ - -/* USART_BSEL Predefined. */ -/* USART_BSEL Predefined. */ - -/* SPI - Serial Peripheral Interface */ -/* SPI.CTRL bit masks and bit positions */ -#define SPI_CLK2X_bm 0x80 /* Enable Double Speed bit mask. */ -#define SPI_CLK2X_bp 7 /* Enable Double Speed bit position. */ - -#define SPI_ENABLE_bm 0x40 /* Enable Module bit mask. */ -#define SPI_ENABLE_bp 6 /* Enable Module bit position. */ - -#define SPI_DORD_bm 0x20 /* Data Order Setting bit mask. */ -#define SPI_DORD_bp 5 /* Data Order Setting bit position. */ - -#define SPI_MASTER_bm 0x10 /* Master Operation Enable bit mask. */ -#define SPI_MASTER_bp 4 /* Master Operation Enable bit position. */ - -#define SPI_MODE_gm 0x0C /* SPI Mode group mask. */ -#define SPI_MODE_gp 2 /* SPI Mode group position. */ -#define SPI_MODE0_bm (1<<2) /* SPI Mode bit 0 mask. */ -#define SPI_MODE0_bp 2 /* SPI Mode bit 0 position. */ -#define SPI_MODE1_bm (1<<3) /* SPI Mode bit 1 mask. */ -#define SPI_MODE1_bp 3 /* SPI Mode bit 1 position. */ - -#define SPI_PRESCALER_gm 0x03 /* Prescaler group mask. */ -#define SPI_PRESCALER_gp 0 /* Prescaler group position. */ -#define SPI_PRESCALER0_bm (1<<0) /* Prescaler bit 0 mask. */ -#define SPI_PRESCALER0_bp 0 /* Prescaler bit 0 position. */ -#define SPI_PRESCALER1_bm (1<<1) /* Prescaler bit 1 mask. */ -#define SPI_PRESCALER1_bp 1 /* Prescaler bit 1 position. */ - -/* SPI.INTCTRL bit masks and bit positions */ -#define SPI_INTLVL_gm 0x03 /* Interrupt level group mask. */ -#define SPI_INTLVL_gp 0 /* Interrupt level group position. */ -#define SPI_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */ -#define SPI_INTLVL0_bp 0 /* Interrupt level bit 0 position. */ -#define SPI_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */ -#define SPI_INTLVL1_bp 1 /* Interrupt level bit 1 position. */ - -/* SPI.STATUS bit masks and bit positions */ -#define SPI_IF_bm 0x80 /* Interrupt Flag bit mask. */ -#define SPI_IF_bp 7 /* Interrupt Flag bit position. */ - -#define SPI_WRCOL_bm 0x40 /* Write Collision bit mask. */ -#define SPI_WRCOL_bp 6 /* Write Collision bit position. */ - -/* IRCOM - IR Communication Module */ -/* IRCOM.CTRL bit masks and bit positions */ -#define IRCOM_EVSEL_gm 0x0F /* Event Channel Select group mask. */ -#define IRCOM_EVSEL_gp 0 /* Event Channel Select group position. */ -#define IRCOM_EVSEL0_bm (1<<0) /* Event Channel Select bit 0 mask. */ -#define IRCOM_EVSEL0_bp 0 /* Event Channel Select bit 0 position. */ -#define IRCOM_EVSEL1_bm (1<<1) /* Event Channel Select bit 1 mask. */ -#define IRCOM_EVSEL1_bp 1 /* Event Channel Select bit 1 position. */ -#define IRCOM_EVSEL2_bm (1<<2) /* Event Channel Select bit 2 mask. */ -#define IRCOM_EVSEL2_bp 2 /* Event Channel Select bit 2 position. */ -#define IRCOM_EVSEL3_bm (1<<3) /* Event Channel Select bit 3 mask. */ -#define IRCOM_EVSEL3_bp 3 /* Event Channel Select bit 3 position. */ - -/* FUSE - Fuses and Lockbits */ -/* NVM_FUSES.FUSEBYTE0 bit masks and bit positions */ -#define NVM_FUSES_JTAGUSERID_gm 0xFF /* JTAG User ID group mask. */ -#define NVM_FUSES_JTAGUSERID_gp 0 /* JTAG User ID group position. */ -#define NVM_FUSES_JTAGUSERID0_bm (1<<0) /* JTAG User ID bit 0 mask. */ -#define NVM_FUSES_JTAGUSERID0_bp 0 /* JTAG User ID bit 0 position. */ -#define NVM_FUSES_JTAGUSERID1_bm (1<<1) /* JTAG User ID bit 1 mask. */ -#define NVM_FUSES_JTAGUSERID1_bp 1 /* JTAG User ID bit 1 position. */ -#define NVM_FUSES_JTAGUSERID2_bm (1<<2) /* JTAG User ID bit 2 mask. */ -#define NVM_FUSES_JTAGUSERID2_bp 2 /* JTAG User ID bit 2 position. */ -#define NVM_FUSES_JTAGUSERID3_bm (1<<3) /* JTAG User ID bit 3 mask. */ -#define NVM_FUSES_JTAGUSERID3_bp 3 /* JTAG User ID bit 3 position. */ -#define NVM_FUSES_JTAGUSERID4_bm (1<<4) /* JTAG User ID bit 4 mask. */ -#define NVM_FUSES_JTAGUSERID4_bp 4 /* JTAG User ID bit 4 position. */ -#define NVM_FUSES_JTAGUSERID5_bm (1<<5) /* JTAG User ID bit 5 mask. */ -#define NVM_FUSES_JTAGUSERID5_bp 5 /* JTAG User ID bit 5 position. */ -#define NVM_FUSES_JTAGUSERID6_bm (1<<6) /* JTAG User ID bit 6 mask. */ -#define NVM_FUSES_JTAGUSERID6_bp 6 /* JTAG User ID bit 6 position. */ -#define NVM_FUSES_JTAGUSERID7_bm (1<<7) /* JTAG User ID bit 7 mask. */ -#define NVM_FUSES_JTAGUSERID7_bp 7 /* JTAG User ID bit 7 position. */ - -/* NVM_FUSES.FUSEBYTE1 bit masks and bit positions */ -#define NVM_FUSES_WDWP_gm 0xF0 /* Watchdog Window Timeout Period group mask. */ -#define NVM_FUSES_WDWP_gp 4 /* Watchdog Window Timeout Period group position. */ -#define NVM_FUSES_WDWP0_bm (1<<4) /* Watchdog Window Timeout Period bit 0 mask. */ -#define NVM_FUSES_WDWP0_bp 4 /* Watchdog Window Timeout Period bit 0 position. */ -#define NVM_FUSES_WDWP1_bm (1<<5) /* Watchdog Window Timeout Period bit 1 mask. */ -#define NVM_FUSES_WDWP1_bp 5 /* Watchdog Window Timeout Period bit 1 position. */ -#define NVM_FUSES_WDWP2_bm (1<<6) /* Watchdog Window Timeout Period bit 2 mask. */ -#define NVM_FUSES_WDWP2_bp 6 /* Watchdog Window Timeout Period bit 2 position. */ -#define NVM_FUSES_WDWP3_bm (1<<7) /* Watchdog Window Timeout Period bit 3 mask. */ -#define NVM_FUSES_WDWP3_bp 7 /* Watchdog Window Timeout Period bit 3 position. */ - -#define NVM_FUSES_WDP_gm 0x0F /* Watchdog Timeout Period group mask. */ -#define NVM_FUSES_WDP_gp 0 /* Watchdog Timeout Period group position. */ -#define NVM_FUSES_WDP0_bm (1<<0) /* Watchdog Timeout Period bit 0 mask. */ -#define NVM_FUSES_WDP0_bp 0 /* Watchdog Timeout Period bit 0 position. */ -#define NVM_FUSES_WDP1_bm (1<<1) /* Watchdog Timeout Period bit 1 mask. */ -#define NVM_FUSES_WDP1_bp 1 /* Watchdog Timeout Period bit 1 position. */ -#define NVM_FUSES_WDP2_bm (1<<2) /* Watchdog Timeout Period bit 2 mask. */ -#define NVM_FUSES_WDP2_bp 2 /* Watchdog Timeout Period bit 2 position. */ -#define NVM_FUSES_WDP3_bm (1<<3) /* Watchdog Timeout Period bit 3 mask. */ -#define NVM_FUSES_WDP3_bp 3 /* Watchdog Timeout Period bit 3 position. */ - -/* NVM_FUSES.FUSEBYTE2 bit masks and bit positions */ -#define NVM_FUSES_BOOTRST_bm 0x40 /* Boot Loader Section Reset Vector bit mask. */ -#define NVM_FUSES_BOOTRST_bp 6 /* Boot Loader Section Reset Vector bit position. */ - -#define NVM_FUSES_TOSCSEL_bm 0x20 /* Timer Oscillator pin location bit mask. */ -#define NVM_FUSES_TOSCSEL_bp 5 /* Timer Oscillator pin location bit position. */ - -#define NVM_FUSES_BODPD_gm 0x03 /* BOD Operation in Power-Down Mode group mask. */ -#define NVM_FUSES_BODPD_gp 0 /* BOD Operation in Power-Down Mode group position. */ -#define NVM_FUSES_BODPD0_bm (1<<0) /* BOD Operation in Power-Down Mode bit 0 mask. */ -#define NVM_FUSES_BODPD0_bp 0 /* BOD Operation in Power-Down Mode bit 0 position. */ -#define NVM_FUSES_BODPD1_bm (1<<1) /* BOD Operation in Power-Down Mode bit 1 mask. */ -#define NVM_FUSES_BODPD1_bp 1 /* BOD Operation in Power-Down Mode bit 1 position. */ - -/* NVM_FUSES.FUSEBYTE4 bit masks and bit positions */ -#define NVM_FUSES_RSTDISBL_bm 0x10 /* External Reset Disable bit mask. */ -#define NVM_FUSES_RSTDISBL_bp 4 /* External Reset Disable bit position. */ - -#define NVM_FUSES_SUT_gm 0x0C /* Start-up Time group mask. */ -#define NVM_FUSES_SUT_gp 2 /* Start-up Time group position. */ -#define NVM_FUSES_SUT0_bm (1<<2) /* Start-up Time bit 0 mask. */ -#define NVM_FUSES_SUT0_bp 2 /* Start-up Time bit 0 position. */ -#define NVM_FUSES_SUT1_bm (1<<3) /* Start-up Time bit 1 mask. */ -#define NVM_FUSES_SUT1_bp 3 /* Start-up Time bit 1 position. */ - -#define NVM_FUSES_WDLOCK_bm 0x02 /* Watchdog Timer Lock bit mask. */ -#define NVM_FUSES_WDLOCK_bp 1 /* Watchdog Timer Lock bit position. */ - -#define NVM_FUSES_JTAGEN_bm 0x01 /* JTAG Interface Enable bit mask. */ -#define NVM_FUSES_JTAGEN_bp 0 /* JTAG Interface Enable bit position. */ - -/* NVM_FUSES.FUSEBYTE5 bit masks and bit positions */ -#define NVM_FUSES_BODACT_gm 0x30 /* BOD Operation in Active Mode group mask. */ -#define NVM_FUSES_BODACT_gp 4 /* BOD Operation in Active Mode group position. */ -#define NVM_FUSES_BODACT0_bm (1<<4) /* BOD Operation in Active Mode bit 0 mask. */ -#define NVM_FUSES_BODACT0_bp 4 /* BOD Operation in Active Mode bit 0 position. */ -#define NVM_FUSES_BODACT1_bm (1<<5) /* BOD Operation in Active Mode bit 1 mask. */ -#define NVM_FUSES_BODACT1_bp 5 /* BOD Operation in Active Mode bit 1 position. */ - -#define NVM_FUSES_EESAVE_bm 0x08 /* Preserve EEPROM Through Chip Erase bit mask. */ -#define NVM_FUSES_EESAVE_bp 3 /* Preserve EEPROM Through Chip Erase bit position. */ - -#define NVM_FUSES_BODLVL_gm 0x07 /* Brownout Detection Voltage Level group mask. */ -#define NVM_FUSES_BODLVL_gp 0 /* Brownout Detection Voltage Level group position. */ -#define NVM_FUSES_BODLVL0_bm (1<<0) /* Brownout Detection Voltage Level bit 0 mask. */ -#define NVM_FUSES_BODLVL0_bp 0 /* Brownout Detection Voltage Level bit 0 position. */ -#define NVM_FUSES_BODLVL1_bm (1<<1) /* Brownout Detection Voltage Level bit 1 mask. */ -#define NVM_FUSES_BODLVL1_bp 1 /* Brownout Detection Voltage Level bit 1 position. */ -#define NVM_FUSES_BODLVL2_bm (1<<2) /* Brownout Detection Voltage Level bit 2 mask. */ -#define NVM_FUSES_BODLVL2_bp 2 /* Brownout Detection Voltage Level bit 2 position. */ - -/* LOCKBIT - Fuses and Lockbits */ -/* NVM_LOCKBITS.LOCKBITS bit masks and bit positions */ -#define NVM_LOCKBITS_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ -#define NVM_LOCKBITS_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ -#define NVM_LOCKBITS_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ -#define NVM_LOCKBITS_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ -#define NVM_LOCKBITS_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ -#define NVM_LOCKBITS_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ - -#define NVM_LOCKBITS_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ -#define NVM_LOCKBITS_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ -#define NVM_LOCKBITS_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ -#define NVM_LOCKBITS_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ -#define NVM_LOCKBITS_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ -#define NVM_LOCKBITS_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ - -#define NVM_LOCKBITS_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ -#define NVM_LOCKBITS_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ -#define NVM_LOCKBITS_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ -#define NVM_LOCKBITS_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ -#define NVM_LOCKBITS_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ -#define NVM_LOCKBITS_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ - -#define NVM_LOCKBITS_LB_gm 0x03 /* Lock Bits group mask. */ -#define NVM_LOCKBITS_LB_gp 0 /* Lock Bits group position. */ -#define NVM_LOCKBITS_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ -#define NVM_LOCKBITS_LB0_bp 0 /* Lock Bits bit 0 position. */ -#define NVM_LOCKBITS_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ -#define NVM_LOCKBITS_LB1_bp 1 /* Lock Bits bit 1 position. */ - - - -// Generic Port Pins - -#define PIN0_bm 0x01 -#define PIN0_bp 0 -#define PIN1_bm 0x02 -#define PIN1_bp 1 -#define PIN2_bm 0x04 -#define PIN2_bp 2 -#define PIN3_bm 0x08 -#define PIN3_bp 3 -#define PIN4_bm 0x10 -#define PIN4_bp 4 -#define PIN5_bm 0x20 -#define PIN5_bp 5 -#define PIN6_bm 0x40 -#define PIN6_bp 6 -#define PIN7_bm 0x80 -#define PIN7_bp 7 - -/* ========== Interrupt Vector Definitions ========== */ -/* Vector 0 is the reset vector */ - -/* OSC interrupt vectors */ -#define OSC_OSCF_vect_num 1 -#define OSC_OSCF_vect _VECTOR(1) /* Oscillator Failure Interrupt (NMI) */ - -/* PORTC interrupt vectors */ -#define PORTC_INT0_vect_num 2 -#define PORTC_INT0_vect _VECTOR(2) /* External Interrupt 0 */ -#define PORTC_INT1_vect_num 3 -#define PORTC_INT1_vect _VECTOR(3) /* External Interrupt 1 */ - -/* PORTR interrupt vectors */ -#define PORTR_INT0_vect_num 4 -#define PORTR_INT0_vect _VECTOR(4) /* External Interrupt 0 */ -#define PORTR_INT1_vect_num 5 -#define PORTR_INT1_vect _VECTOR(5) /* External Interrupt 1 */ - -/* DMA interrupt vectors */ -#define DMA_CH0_vect_num 6 -#define DMA_CH0_vect _VECTOR(6) /* Channel 0 Interrupt */ -#define DMA_CH1_vect_num 7 -#define DMA_CH1_vect _VECTOR(7) /* Channel 1 Interrupt */ -#define DMA_CH2_vect_num 8 -#define DMA_CH2_vect _VECTOR(8) /* Channel 2 Interrupt */ -#define DMA_CH3_vect_num 9 -#define DMA_CH3_vect _VECTOR(9) /* Channel 3 Interrupt */ - -/* RTC interrupt vectors */ -#define RTC_OVF_vect_num 10 -#define RTC_OVF_vect _VECTOR(10) /* Overflow Interrupt */ -#define RTC_COMP_vect_num 11 -#define RTC_COMP_vect _VECTOR(11) /* Compare Interrupt */ - -/* TWIC interrupt vectors */ -#define TWIC_TWIS_vect_num 12 -#define TWIC_TWIS_vect _VECTOR(12) /* TWI Slave Interrupt */ -#define TWIC_TWIM_vect_num 13 -#define TWIC_TWIM_vect _VECTOR(13) /* TWI Master Interrupt */ - -/* TCC0 interrupt vectors */ -#define TCC0_OVF_vect_num 14 -#define TCC0_OVF_vect _VECTOR(14) /* Overflow Interrupt */ - -/* TCC2 interrupt vectors */ -#define TCC2_LUNF_vect_num 14 -#define TCC2_LUNF_vect _VECTOR(14) /* Low Byte Underflow Interrupt */ - -/* TCC0 interrupt vectors */ -#define TCC0_ERR_vect_num 15 -#define TCC0_ERR_vect _VECTOR(15) /* Error Interrupt */ - -/* TCC2 interrupt vectors */ -#define TCC2_HUNF_vect_num 15 -#define TCC2_HUNF_vect _VECTOR(15) /* High Byte Underflow Interrupt */ - -/* TCC0 interrupt vectors */ -#define TCC0_CCA_vect_num 16 -#define TCC0_CCA_vect _VECTOR(16) /* Compare or Capture A Interrupt */ - -/* TCC2 interrupt vectors */ -#define TCC2_LCMPA_vect_num 16 -#define TCC2_LCMPA_vect _VECTOR(16) /* Low Byte Compare A Interrupt */ - -/* TCC0 interrupt vectors */ -#define TCC0_CCB_vect_num 17 -#define TCC0_CCB_vect _VECTOR(17) /* Compare or Capture B Interrupt */ - -/* TCC2 interrupt vectors */ -#define TCC2_LCMPB_vect_num 17 -#define TCC2_LCMPB_vect _VECTOR(17) /* Low Byte Compare B Interrupt */ - -/* TCC0 interrupt vectors */ -#define TCC0_CCC_vect_num 18 -#define TCC0_CCC_vect _VECTOR(18) /* Compare or Capture C Interrupt */ - -/* TCC2 interrupt vectors */ -#define TCC2_LCMPC_vect_num 18 -#define TCC2_LCMPC_vect _VECTOR(18) /* Low Byte Compare C Interrupt */ - -/* TCC0 interrupt vectors */ -#define TCC0_CCD_vect_num 19 -#define TCC0_CCD_vect _VECTOR(19) /* Compare or Capture D Interrupt */ - -/* TCC2 interrupt vectors */ -#define TCC2_LCMPD_vect_num 19 -#define TCC2_LCMPD_vect _VECTOR(19) /* Low Byte Compare D Interrupt */ - -/* TCC1 interrupt vectors */ -#define TCC1_OVF_vect_num 20 -#define TCC1_OVF_vect _VECTOR(20) /* Overflow Interrupt */ -#define TCC1_ERR_vect_num 21 -#define TCC1_ERR_vect _VECTOR(21) /* Error Interrupt */ -#define TCC1_CCA_vect_num 22 -#define TCC1_CCA_vect _VECTOR(22) /* Compare or Capture A Interrupt */ -#define TCC1_CCB_vect_num 23 -#define TCC1_CCB_vect _VECTOR(23) /* Compare or Capture B Interrupt */ - -/* SPIC interrupt vectors */ -#define SPIC_INT_vect_num 24 -#define SPIC_INT_vect _VECTOR(24) /* SPI Interrupt */ - -/* USARTC0 interrupt vectors */ -#define USARTC0_RXC_vect_num 25 -#define USARTC0_RXC_vect _VECTOR(25) /* Reception Complete Interrupt */ -#define USARTC0_DRE_vect_num 26 -#define USARTC0_DRE_vect _VECTOR(26) /* Data Register Empty Interrupt */ -#define USARTC0_TXC_vect_num 27 -#define USARTC0_TXC_vect _VECTOR(27) /* Transmission Complete Interrupt */ - -/* USARTC1 interrupt vectors */ -#define USARTC1_RXC_vect_num 28 -#define USARTC1_RXC_vect _VECTOR(28) /* Reception Complete Interrupt */ -#define USARTC1_DRE_vect_num 29 -#define USARTC1_DRE_vect _VECTOR(29) /* Data Register Empty Interrupt */ -#define USARTC1_TXC_vect_num 30 -#define USARTC1_TXC_vect _VECTOR(30) /* Transmission Complete Interrupt */ - -/* AES interrupt vectors */ -#define AES_INT_vect_num 31 -#define AES_INT_vect _VECTOR(31) /* AES Interrupt */ - -/* NVM interrupt vectors */ -#define NVM_EE_vect_num 32 -#define NVM_EE_vect _VECTOR(32) /* EE Interrupt */ -#define NVM_SPM_vect_num 33 -#define NVM_SPM_vect _VECTOR(33) /* SPM Interrupt */ - -/* PORTB interrupt vectors */ -#define PORTB_INT0_vect_num 34 -#define PORTB_INT0_vect _VECTOR(34) /* External Interrupt 0 */ -#define PORTB_INT1_vect_num 35 -#define PORTB_INT1_vect _VECTOR(35) /* External Interrupt 1 */ - -/* ACB interrupt vectors */ -#define ACB_AC0_vect_num 36 -#define ACB_AC0_vect _VECTOR(36) /* AC0 Interrupt */ -#define ACB_AC1_vect_num 37 -#define ACB_AC1_vect _VECTOR(37) /* AC1 Interrupt */ -#define ACB_ACW_vect_num 38 -#define ACB_ACW_vect _VECTOR(38) /* ACW Window Mode Interrupt */ - -/* ADCB interrupt vectors */ -#define ADCB_CH0_vect_num 39 -#define ADCB_CH0_vect _VECTOR(39) /* Interrupt 0 */ -#define ADCB_CH1_vect_num 40 -#define ADCB_CH1_vect _VECTOR(40) /* Interrupt 1 */ -#define ADCB_CH2_vect_num 41 -#define ADCB_CH2_vect _VECTOR(41) /* Interrupt 2 */ -#define ADCB_CH3_vect_num 42 -#define ADCB_CH3_vect _VECTOR(42) /* Interrupt 3 */ - -/* PORTE interrupt vectors */ -#define PORTE_INT0_vect_num 43 -#define PORTE_INT0_vect _VECTOR(43) /* External Interrupt 0 */ -#define PORTE_INT1_vect_num 44 -#define PORTE_INT1_vect _VECTOR(44) /* External Interrupt 1 */ - -/* TWIE interrupt vectors */ -#define TWIE_TWIS_vect_num 45 -#define TWIE_TWIS_vect _VECTOR(45) /* TWI Slave Interrupt */ -#define TWIE_TWIM_vect_num 46 -#define TWIE_TWIM_vect _VECTOR(46) /* TWI Master Interrupt */ - -/* TCE0 interrupt vectors */ -#define TCE0_OVF_vect_num 47 -#define TCE0_OVF_vect _VECTOR(47) /* Overflow Interrupt */ - -/* TCE2 interrupt vectors */ -#define TCE2_LUNF_vect_num 47 -#define TCE2_LUNF_vect _VECTOR(47) /* Low Byte Underflow Interrupt */ - -/* TCE0 interrupt vectors */ -#define TCE0_ERR_vect_num 48 -#define TCE0_ERR_vect _VECTOR(48) /* Error Interrupt */ - -/* TCE2 interrupt vectors */ -#define TCE2_HUNF_vect_num 48 -#define TCE2_HUNF_vect _VECTOR(48) /* High Byte Underflow Interrupt */ - -/* TCE0 interrupt vectors */ -#define TCE0_CCA_vect_num 49 -#define TCE0_CCA_vect _VECTOR(49) /* Compare or Capture A Interrupt */ - -/* TCE2 interrupt vectors */ -#define TCE2_LCMPA_vect_num 49 -#define TCE2_LCMPA_vect _VECTOR(49) /* Low Byte Compare A Interrupt */ - -/* TCE0 interrupt vectors */ -#define TCE0_CCB_vect_num 50 -#define TCE0_CCB_vect _VECTOR(50) /* Compare or Capture B Interrupt */ - -/* TCE2 interrupt vectors */ -#define TCE2_LCMPB_vect_num 50 -#define TCE2_LCMPB_vect _VECTOR(50) /* Low Byte Compare B Interrupt */ - -/* TCE0 interrupt vectors */ -#define TCE0_CCC_vect_num 51 -#define TCE0_CCC_vect _VECTOR(51) /* Compare or Capture C Interrupt */ - -/* TCE2 interrupt vectors */ -#define TCE2_LCMPC_vect_num 51 -#define TCE2_LCMPC_vect _VECTOR(51) /* Low Byte Compare C Interrupt */ - -/* TCE0 interrupt vectors */ -#define TCE0_CCD_vect_num 52 -#define TCE0_CCD_vect _VECTOR(52) /* Compare or Capture D Interrupt */ - -/* TCE2 interrupt vectors */ -#define TCE2_LCMPD_vect_num 52 -#define TCE2_LCMPD_vect _VECTOR(52) /* Low Byte Compare D Interrupt */ - -/* TCE1 interrupt vectors */ -#define TCE1_OVF_vect_num 53 -#define TCE1_OVF_vect _VECTOR(53) /* Overflow Interrupt */ -#define TCE1_ERR_vect_num 54 -#define TCE1_ERR_vect _VECTOR(54) /* Error Interrupt */ -#define TCE1_CCA_vect_num 55 -#define TCE1_CCA_vect _VECTOR(55) /* Compare or Capture A Interrupt */ -#define TCE1_CCB_vect_num 56 -#define TCE1_CCB_vect _VECTOR(56) /* Compare or Capture B Interrupt */ - -/* SPIE interrupt vectors */ -#define SPIE_INT_vect_num 57 -#define SPIE_INT_vect _VECTOR(57) /* SPI Interrupt */ - -/* USARTE0 interrupt vectors */ -#define USARTE0_RXC_vect_num 58 -#define USARTE0_RXC_vect _VECTOR(58) /* Reception Complete Interrupt */ -#define USARTE0_DRE_vect_num 59 -#define USARTE0_DRE_vect _VECTOR(59) /* Data Register Empty Interrupt */ -#define USARTE0_TXC_vect_num 60 -#define USARTE0_TXC_vect _VECTOR(60) /* Transmission Complete Interrupt */ - -/* USARTE1 interrupt vectors */ -#define USARTE1_RXC_vect_num 61 -#define USARTE1_RXC_vect _VECTOR(61) /* Reception Complete Interrupt */ -#define USARTE1_DRE_vect_num 62 -#define USARTE1_DRE_vect _VECTOR(62) /* Data Register Empty Interrupt */ -#define USARTE1_TXC_vect_num 63 -#define USARTE1_TXC_vect _VECTOR(63) /* Transmission Complete Interrupt */ - -/* PORTD interrupt vectors */ -#define PORTD_INT0_vect_num 64 -#define PORTD_INT0_vect _VECTOR(64) /* External Interrupt 0 */ -#define PORTD_INT1_vect_num 65 -#define PORTD_INT1_vect _VECTOR(65) /* External Interrupt 1 */ - -/* PORTA interrupt vectors */ -#define PORTA_INT0_vect_num 66 -#define PORTA_INT0_vect _VECTOR(66) /* External Interrupt 0 */ -#define PORTA_INT1_vect_num 67 -#define PORTA_INT1_vect _VECTOR(67) /* External Interrupt 1 */ - -/* ACA interrupt vectors */ -#define ACA_AC0_vect_num 68 -#define ACA_AC0_vect _VECTOR(68) /* AC0 Interrupt */ -#define ACA_AC1_vect_num 69 -#define ACA_AC1_vect _VECTOR(69) /* AC1 Interrupt */ -#define ACA_ACW_vect_num 70 -#define ACA_ACW_vect _VECTOR(70) /* ACW Window Mode Interrupt */ - -/* ADCA interrupt vectors */ -#define ADCA_CH0_vect_num 71 -#define ADCA_CH0_vect _VECTOR(71) /* Interrupt 0 */ -#define ADCA_CH1_vect_num 72 -#define ADCA_CH1_vect _VECTOR(72) /* Interrupt 1 */ -#define ADCA_CH2_vect_num 73 -#define ADCA_CH2_vect _VECTOR(73) /* Interrupt 2 */ -#define ADCA_CH3_vect_num 74 -#define ADCA_CH3_vect _VECTOR(74) /* Interrupt 3 */ - -/* TCD0 interrupt vectors */ -#define TCD0_OVF_vect_num 77 -#define TCD0_OVF_vect _VECTOR(77) /* Overflow Interrupt */ - -/* TCD2 interrupt vectors */ -#define TCD2_LUNF_vect_num 77 -#define TCD2_LUNF_vect _VECTOR(77) /* Low Byte Underflow Interrupt */ - -/* TCD0 interrupt vectors */ -#define TCD0_ERR_vect_num 78 -#define TCD0_ERR_vect _VECTOR(78) /* Error Interrupt */ - -/* TCD2 interrupt vectors */ -#define TCD2_HUNF_vect_num 78 -#define TCD2_HUNF_vect _VECTOR(78) /* High Byte Underflow Interrupt */ - -/* TCD0 interrupt vectors */ -#define TCD0_CCA_vect_num 79 -#define TCD0_CCA_vect _VECTOR(79) /* Compare or Capture A Interrupt */ - -/* TCD2 interrupt vectors */ -#define TCD2_LCMPA_vect_num 79 -#define TCD2_LCMPA_vect _VECTOR(79) /* Low Byte Compare A Interrupt */ - -/* TCD0 interrupt vectors */ -#define TCD0_CCB_vect_num 80 -#define TCD0_CCB_vect _VECTOR(80) /* Compare or Capture B Interrupt */ - -/* TCD2 interrupt vectors */ -#define TCD2_LCMPB_vect_num 80 -#define TCD2_LCMPB_vect _VECTOR(80) /* Low Byte Compare B Interrupt */ - -/* TCD0 interrupt vectors */ -#define TCD0_CCC_vect_num 81 -#define TCD0_CCC_vect _VECTOR(81) /* Compare or Capture C Interrupt */ - -/* TCD2 interrupt vectors */ -#define TCD2_LCMPC_vect_num 81 -#define TCD2_LCMPC_vect _VECTOR(81) /* Low Byte Compare C Interrupt */ - -/* TCD0 interrupt vectors */ -#define TCD0_CCD_vect_num 82 -#define TCD0_CCD_vect _VECTOR(82) /* Compare or Capture D Interrupt */ - -/* TCD2 interrupt vectors */ -#define TCD2_LCMPD_vect_num 82 -#define TCD2_LCMPD_vect _VECTOR(82) /* Low Byte Compare D Interrupt */ - -/* TCD1 interrupt vectors */ -#define TCD1_OVF_vect_num 83 -#define TCD1_OVF_vect _VECTOR(83) /* Overflow Interrupt */ -#define TCD1_ERR_vect_num 84 -#define TCD1_ERR_vect _VECTOR(84) /* Error Interrupt */ -#define TCD1_CCA_vect_num 85 -#define TCD1_CCA_vect _VECTOR(85) /* Compare or Capture A Interrupt */ -#define TCD1_CCB_vect_num 86 -#define TCD1_CCB_vect _VECTOR(86) /* Compare or Capture B Interrupt */ - -/* SPID interrupt vectors */ -#define SPID_INT_vect_num 87 -#define SPID_INT_vect _VECTOR(87) /* SPI Interrupt */ - -/* USARTD0 interrupt vectors */ -#define USARTD0_RXC_vect_num 88 -#define USARTD0_RXC_vect _VECTOR(88) /* Reception Complete Interrupt */ -#define USARTD0_DRE_vect_num 89 -#define USARTD0_DRE_vect _VECTOR(89) /* Data Register Empty Interrupt */ -#define USARTD0_TXC_vect_num 90 -#define USARTD0_TXC_vect _VECTOR(90) /* Transmission Complete Interrupt */ - -/* USARTD1 interrupt vectors */ -#define USARTD1_RXC_vect_num 91 -#define USARTD1_RXC_vect _VECTOR(91) /* Reception Complete Interrupt */ -#define USARTD1_DRE_vect_num 92 -#define USARTD1_DRE_vect _VECTOR(92) /* Data Register Empty Interrupt */ -#define USARTD1_TXC_vect_num 93 -#define USARTD1_TXC_vect _VECTOR(93) /* Transmission Complete Interrupt */ - -/* PORTF interrupt vectors */ -#define PORTF_INT0_vect_num 104 -#define PORTF_INT0_vect _VECTOR(104) /* External Interrupt 0 */ -#define PORTF_INT1_vect_num 105 -#define PORTF_INT1_vect _VECTOR(105) /* External Interrupt 1 */ - -/* TCF0 interrupt vectors */ -#define TCF0_OVF_vect_num 108 -#define TCF0_OVF_vect _VECTOR(108) /* Overflow Interrupt */ - -/* TCF2 interrupt vectors */ -#define TCF2_LUNF_vect_num 108 -#define TCF2_LUNF_vect _VECTOR(108) /* Low Byte Underflow Interrupt */ - -/* TCF0 interrupt vectors */ -#define TCF0_ERR_vect_num 109 -#define TCF0_ERR_vect _VECTOR(109) /* Error Interrupt */ - -/* TCF2 interrupt vectors */ -#define TCF2_HUNF_vect_num 109 -#define TCF2_HUNF_vect _VECTOR(109) /* High Byte Underflow Interrupt */ - -/* TCF0 interrupt vectors */ -#define TCF0_CCA_vect_num 110 -#define TCF0_CCA_vect _VECTOR(110) /* Compare or Capture A Interrupt */ - -/* TCF2 interrupt vectors */ -#define TCF2_LCMPA_vect_num 110 -#define TCF2_LCMPA_vect _VECTOR(110) /* Low Byte Compare A Interrupt */ - -/* TCF0 interrupt vectors */ -#define TCF0_CCB_vect_num 111 -#define TCF0_CCB_vect _VECTOR(111) /* Compare or Capture B Interrupt */ - -/* TCF2 interrupt vectors */ -#define TCF2_LCMPB_vect_num 111 -#define TCF2_LCMPB_vect _VECTOR(111) /* Low Byte Compare B Interrupt */ - -/* TCF0 interrupt vectors */ -#define TCF0_CCC_vect_num 112 -#define TCF0_CCC_vect _VECTOR(112) /* Compare or Capture C Interrupt */ - -/* TCF2 interrupt vectors */ -#define TCF2_LCMPC_vect_num 112 -#define TCF2_LCMPC_vect _VECTOR(112) /* Low Byte Compare C Interrupt */ - -/* TCF0 interrupt vectors */ -#define TCF0_CCD_vect_num 113 -#define TCF0_CCD_vect _VECTOR(113) /* Compare or Capture D Interrupt */ - -/* TCF2 interrupt vectors */ -#define TCF2_LCMPD_vect_num 113 -#define TCF2_LCMPD_vect _VECTOR(113) /* Low Byte Compare D Interrupt */ - -/* USARTF0 interrupt vectors */ -#define USARTF0_RXC_vect_num 119 -#define USARTF0_RXC_vect _VECTOR(119) /* Reception Complete Interrupt */ -#define USARTF0_DRE_vect_num 120 -#define USARTF0_DRE_vect _VECTOR(120) /* Data Register Empty Interrupt */ -#define USARTF0_TXC_vect_num 121 -#define USARTF0_TXC_vect _VECTOR(121) /* Transmission Complete Interrupt */ - -/* USB interrupt vectors */ -#define USB_BUSEVENT_vect_num 125 -#define USB_BUSEVENT_vect _VECTOR(125) /* SOF, suspend, resume, reset bus event interrupts, crc, underflow, overflow and stall error interrupts */ -#define USB_TRNCOMPL_vect_num 126 -#define USB_TRNCOMPL_vect _VECTOR(126) /* Transaction complete interrupt */ - -#define _VECTOR_SIZE 4 /* Size of individual vector. */ -#define _VECTORS_SIZE (127 * _VECTOR_SIZE) - - -/* ========== Constants ========== */ - -#define PROGMEM_START (0x0000) -#define PROGMEM_SIZE (69632) -#define PROGMEM_END (PROGMEM_START + PROGMEM_SIZE - 1) - -#define APP_SECTION_START (0x0000) -#define APP_SECTION_SIZE (65536) -#define APP_SECTION_PAGE_SIZE (256) -#define APP_SECTION_END (APP_SECTION_START + APP_SECTION_SIZE - 1) - -#define APPTABLE_SECTION_START (0xF000) -#define APPTABLE_SECTION_SIZE (4096) -#define APPTABLE_SECTION_PAGE_SIZE (256) -#define APPTABLE_SECTION_END (APPTABLE_SECTION_START + APPTABLE_SECTION_SIZE - 1) - -#define BOOT_SECTION_START (0x10000) -#define BOOT_SECTION_SIZE (4096) -#define BOOT_SECTION_PAGE_SIZE (256) -#define BOOT_SECTION_END (BOOT_SECTION_START + BOOT_SECTION_SIZE - 1) - -#define DATAMEM_START (0x0000) -#define DATAMEM_SIZE (12288) -#define DATAMEM_END (DATAMEM_START + DATAMEM_SIZE - 1) - -#define IO_START (0x0000) -#define IO_SIZE (4096) -#define IO_PAGE_SIZE (0) -#define IO_END (IO_START + IO_SIZE - 1) - -#define MAPPED_EEPROM_START (0x1000) -#define MAPPED_EEPROM_SIZE (2048) -#define MAPPED_EEPROM_PAGE_SIZE (0) -#define MAPPED_EEPROM_END (MAPPED_EEPROM_START + MAPPED_EEPROM_SIZE - 1) - -#define INTERNAL_SRAM_START (0x2000) -#define INTERNAL_SRAM_SIZE (4096) -#define INTERNAL_SRAM_PAGE_SIZE (0) -#define INTERNAL_SRAM_END (INTERNAL_SRAM_START + INTERNAL_SRAM_SIZE - 1) - -#define EEPROM_START (0x0000) -#define EEPROM_SIZE (2048) -#define EEPROM_PAGE_SIZE (32) -#define EEPROM_END (EEPROM_START + EEPROM_SIZE - 1) - -#define SIGNATURES_START (0x0000) -#define SIGNATURES_SIZE (3) -#define SIGNATURES_PAGE_SIZE (0) -#define SIGNATURES_END (SIGNATURES_START + SIGNATURES_SIZE - 1) - -#define FUSES_START (0x0000) -#define FUSES_SIZE (6) -#define FUSES_PAGE_SIZE (0) -#define FUSES_END (FUSES_START + FUSES_SIZE - 1) - -#define LOCKBITS_START (0x0000) -#define LOCKBITS_SIZE (1) -#define LOCKBITS_PAGE_SIZE (0) -#define LOCKBITS_END (LOCKBITS_START + LOCKBITS_SIZE - 1) - -#define USER_SIGNATURES_START (0x0000) -#define USER_SIGNATURES_SIZE (256) -#define USER_SIGNATURES_PAGE_SIZE (256) -#define USER_SIGNATURES_END (USER_SIGNATURES_START + USER_SIGNATURES_SIZE - 1) - -#define PROD_SIGNATURES_START (0x0000) -#define PROD_SIGNATURES_SIZE (52) -#define PROD_SIGNATURES_PAGE_SIZE (256) -#define PROD_SIGNATURES_END (PROD_SIGNATURES_START + PROD_SIGNATURES_SIZE - 1) - -#define FLASHSTART PROGMEM_START -#define FLASHEND PROGMEM_END -#define SPM_PAGESIZE 256 -#define RAMSTART INTERNAL_SRAM_START -#define RAMSIZE INTERNAL_SRAM_SIZE -#define RAMEND INTERNAL_SRAM_END -#define E2END EEPROM_END -#define E2PAGESIZE EEPROM_PAGE_SIZE - - -/* ========== Fuses ========== */ -#define FUSE_MEMORY_SIZE 6 - -/* Fuse Byte 0 */ -#define FUSE_JTAGUSERID0 (unsigned char)~_BV(0) /* JTAG User ID Bit 0 */ -#define FUSE_JTAGUSERID1 (unsigned char)~_BV(1) /* JTAG User ID Bit 1 */ -#define FUSE_JTAGUSERID2 (unsigned char)~_BV(2) /* JTAG User ID Bit 2 */ -#define FUSE_JTAGUSERID3 (unsigned char)~_BV(3) /* JTAG User ID Bit 3 */ -#define FUSE_JTAGUSERID4 (unsigned char)~_BV(4) /* JTAG User ID Bit 4 */ -#define FUSE_JTAGUSERID5 (unsigned char)~_BV(5) /* JTAG User ID Bit 5 */ -#define FUSE_JTAGUSERID6 (unsigned char)~_BV(6) /* JTAG User ID Bit 6 */ -#define FUSE_JTAGUSERID7 (unsigned char)~_BV(7) /* JTAG User ID Bit 7 */ -#define FUSE0_DEFAULT (0xFF) - -/* Fuse Byte 1 */ -#define FUSE_WDP0 (unsigned char)~_BV(0) /* Watchdog Timeout Period Bit 0 */ -#define FUSE_WDP1 (unsigned char)~_BV(1) /* Watchdog Timeout Period Bit 1 */ -#define FUSE_WDP2 (unsigned char)~_BV(2) /* Watchdog Timeout Period Bit 2 */ -#define FUSE_WDP3 (unsigned char)~_BV(3) /* Watchdog Timeout Period Bit 3 */ -#define FUSE_WDWP0 (unsigned char)~_BV(4) /* Watchdog Window Timeout Period Bit 0 */ -#define FUSE_WDWP1 (unsigned char)~_BV(5) /* Watchdog Window Timeout Period Bit 1 */ -#define FUSE_WDWP2 (unsigned char)~_BV(6) /* Watchdog Window Timeout Period Bit 2 */ -#define FUSE_WDWP3 (unsigned char)~_BV(7) /* Watchdog Window Timeout Period Bit 3 */ -#define FUSE1_DEFAULT (0xFF) - -/* Fuse Byte 2 */ -#define FUSE_BODPD0 (unsigned char)~_BV(0) /* BOD Operation in Power-Down Mode Bit 0 */ -#define FUSE_BODPD1 (unsigned char)~_BV(1) /* BOD Operation in Power-Down Mode Bit 1 */ -#define FUSE_TOSCSEL (unsigned char)~_BV(5) /* Timer Oscillator pin location */ -#define FUSE_BOOTRST (unsigned char)~_BV(6) /* Boot Loader Section Reset Vector */ -#define FUSE2_DEFAULT (0xFF) - -/* Fuse Byte 3 Reserved */ - -/* Fuse Byte 4 */ -#define FUSE_JTAGEN (unsigned char)~_BV(0) /* JTAG Interface Enable */ -#define FUSE_WDLOCK (unsigned char)~_BV(1) /* Watchdog Timer Lock */ -#define FUSE_SUT0 (unsigned char)~_BV(2) /* Start-up Time Bit 0 */ -#define FUSE_SUT1 (unsigned char)~_BV(3) /* Start-up Time Bit 1 */ -#define FUSE_RSTDISBL (unsigned char)~_BV(4) /* External Reset Disable */ -#define FUSE4_DEFAULT (0xFF) - -/* Fuse Byte 5 */ -#define FUSE_BODLVL0 (unsigned char)~_BV(0) /* Brownout Detection Voltage Level Bit 0 */ -#define FUSE_BODLVL1 (unsigned char)~_BV(1) /* Brownout Detection Voltage Level Bit 1 */ -#define FUSE_BODLVL2 (unsigned char)~_BV(2) /* Brownout Detection Voltage Level Bit 2 */ -#define FUSE_EESAVE (unsigned char)~_BV(3) /* Preserve EEPROM Through Chip Erase */ -#define FUSE_BODACT0 (unsigned char)~_BV(4) /* BOD Operation in Active Mode Bit 0 */ -#define FUSE_BODACT1 (unsigned char)~_BV(5) /* BOD Operation in Active Mode Bit 1 */ -#define FUSE5_DEFAULT (0xFF) - -/* ========== Lock Bits ========== */ -#define __LOCK_BITS_EXIST -#define __BOOT_LOCK_APPLICATION_TABLE_BITS_EXIST -#define __BOOT_LOCK_APPLICATION_BITS_EXIST -#define __BOOT_LOCK_BOOT_BITS_EXIST - -/* ========== Signature ========== */ -#define SIGNATURE_0 0x1E -#define SIGNATURE_1 0x96 -#define SIGNATURE_2 0x42 - -/* ========== Power Reduction Condition Definitions ========== */ - -/* PR.PRGEN */ -#define __AVR_HAVE_PRGEN (PR_USB_bm|PR_AES_bm|PR_EBI_bm|PR_RTC_bm|PR_EVSYS_bm|PR_DMA_bm) -#define __AVR_HAVE_PRGEN_USB -#define __AVR_HAVE_PRGEN_AES -#define __AVR_HAVE_PRGEN_EBI -#define __AVR_HAVE_PRGEN_RTC -#define __AVR_HAVE_PRGEN_EVSYS -#define __AVR_HAVE_PRGEN_DMA - -/* PR.PRPA */ -#define __AVR_HAVE_PRPA (PR_DAC_bm|PR_ADC_bm|PR_AC_bm) -#define __AVR_HAVE_PRPA_DAC -#define __AVR_HAVE_PRPA_ADC -#define __AVR_HAVE_PRPA_AC - -/* PR.PRPB */ -#define __AVR_HAVE_PRPB (PR_DAC_bm|PR_ADC_bm|PR_AC_bm) -#define __AVR_HAVE_PRPB_DAC -#define __AVR_HAVE_PRPB_ADC -#define __AVR_HAVE_PRPB_AC - -/* PR.PRPC */ -#define __AVR_HAVE_PRPC (PR_TWI_bm|PR_USART1_bm|PR_USART0_bm|PR_SPI_bm|PR_HIRES_bm|PR_TC1_bm|PR_TC0_bm) -#define __AVR_HAVE_PRPC_TWI -#define __AVR_HAVE_PRPC_USART1 -#define __AVR_HAVE_PRPC_USART0 -#define __AVR_HAVE_PRPC_SPI -#define __AVR_HAVE_PRPC_HIRES -#define __AVR_HAVE_PRPC_TC1 -#define __AVR_HAVE_PRPC_TC0 - -/* PR.PRPD */ -#define __AVR_HAVE_PRPD (PR_TWI_bm|PR_USART1_bm|PR_USART0_bm|PR_SPI_bm|PR_HIRES_bm|PR_TC1_bm|PR_TC0_bm) -#define __AVR_HAVE_PRPD_TWI -#define __AVR_HAVE_PRPD_USART1 -#define __AVR_HAVE_PRPD_USART0 -#define __AVR_HAVE_PRPD_SPI -#define __AVR_HAVE_PRPD_HIRES -#define __AVR_HAVE_PRPD_TC1 -#define __AVR_HAVE_PRPD_TC0 - -/* PR.PRPE */ -#define __AVR_HAVE_PRPE (PR_TWI_bm|PR_USART1_bm|PR_USART0_bm|PR_SPI_bm|PR_HIRES_bm|PR_TC1_bm|PR_TC0_bm) -#define __AVR_HAVE_PRPE_TWI -#define __AVR_HAVE_PRPE_USART1 -#define __AVR_HAVE_PRPE_USART0 -#define __AVR_HAVE_PRPE_SPI -#define __AVR_HAVE_PRPE_HIRES -#define __AVR_HAVE_PRPE_TC1 -#define __AVR_HAVE_PRPE_TC0 - -/* PR.PRPF */ -#define __AVR_HAVE_PRPF (PR_TWI_bm|PR_USART1_bm|PR_USART0_bm|PR_SPI_bm|PR_HIRES_bm|PR_TC1_bm|PR_TC0_bm) -#define __AVR_HAVE_PRPF_TWI -#define __AVR_HAVE_PRPF_USART1 -#define __AVR_HAVE_PRPF_USART0 -#define __AVR_HAVE_PRPF_SPI -#define __AVR_HAVE_PRPF_HIRES -#define __AVR_HAVE_PRPF_TC1 -#define __AVR_HAVE_PRPF_TC0 - - -#endif /* #ifdef _AVR_ATXMEGA64A3U_H_INCLUDED */ - diff --git a/arduino/hardware/tools/avr/avr/include/avr/iox64a4u.h b/arduino/hardware/tools/avr/avr/include/avr/iox64a4u.h deleted file mode 100644 index b8632ac..0000000 --- a/arduino/hardware/tools/avr/avr/include/avr/iox64a4u.h +++ /dev/null @@ -1,7309 +0,0 @@ -/***************************************************************************** - * - * Copyright (C) 2015 Atmel Corporation - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * - * * Neither the name of the copyright holders nor the names of - * contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - ****************************************************************************/ - - -#ifndef _AVR_IO_H_ -# error "Include instead of this file." -#endif - -#ifndef _AVR_IOXXX_H_ -# define _AVR_IOXXX_H_ "iox64a4u.h" -#else -# error "Attempt to include more than one file." -#endif - -#ifndef _AVR_ATXMEGA64A4U_H_INCLUDED -#define _AVR_ATXMEGA64A4U_H_INCLUDED - -/* Ungrouped common registers */ -#define GPIOR0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ -#define GPIOR1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ -#define GPIOR2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ -#define GPIOR3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ -#define GPIOR4 _SFR_MEM8(0x0004) /* General Purpose IO Register 4 */ -#define GPIOR5 _SFR_MEM8(0x0005) /* General Purpose IO Register 5 */ -#define GPIOR6 _SFR_MEM8(0x0006) /* General Purpose IO Register 6 */ -#define GPIOR7 _SFR_MEM8(0x0007) /* General Purpose IO Register 7 */ -#define GPIOR8 _SFR_MEM8(0x0008) /* General Purpose IO Register 8 */ -#define GPIOR9 _SFR_MEM8(0x0009) /* General Purpose IO Register 9 */ -#define GPIORA _SFR_MEM8(0x000A) /* General Purpose IO Register 10 */ -#define GPIORB _SFR_MEM8(0x000B) /* General Purpose IO Register 11 */ -#define GPIORC _SFR_MEM8(0x000C) /* General Purpose IO Register 12 */ -#define GPIORD _SFR_MEM8(0x000D) /* General Purpose IO Register 13 */ -#define GPIORE _SFR_MEM8(0x000E) /* General Purpose IO Register 14 */ -#define GPIORF _SFR_MEM8(0x000F) /* General Purpose IO Register 15 */ - -/* Deprecated */ -#define GPIO0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ -#define GPIO1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ -#define GPIO2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ -#define GPIO3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ -#define GPIO4 _SFR_MEM8(0x0004) /* General Purpose IO Register 4 */ -#define GPIO5 _SFR_MEM8(0x0005) /* General Purpose IO Register 5 */ -#define GPIO6 _SFR_MEM8(0x0006) /* General Purpose IO Register 6 */ -#define GPIO7 _SFR_MEM8(0x0007) /* General Purpose IO Register 7 */ -#define GPIO8 _SFR_MEM8(0x0008) /* General Purpose IO Register 8 */ -#define GPIO9 _SFR_MEM8(0x0009) /* General Purpose IO Register 9 */ -#define GPIOA _SFR_MEM8(0x000A) /* General Purpose IO Register 10 */ -#define GPIOB _SFR_MEM8(0x000B) /* General Purpose IO Register 11 */ -#define GPIOC _SFR_MEM8(0x000C) /* General Purpose IO Register 12 */ -#define GPIOD _SFR_MEM8(0x000D) /* General Purpose IO Register 13 */ -#define GPIOE _SFR_MEM8(0x000E) /* General Purpose IO Register 14 */ -#define GPIOF _SFR_MEM8(0x000F) /* General Purpose IO Register 15 */ - -#define CCP _SFR_MEM8(0x0034) /* Configuration Change Protection */ -#define RAMPD _SFR_MEM8(0x0038) /* Ramp D */ -#define RAMPX _SFR_MEM8(0x0039) /* Ramp X */ -#define RAMPY _SFR_MEM8(0x003A) /* Ramp Y */ -#define RAMPZ _SFR_MEM8(0x003B) /* Ramp Z */ -#define EIND _SFR_MEM8(0x003C) /* Extended Indirect Jump */ -#define SPL _SFR_MEM8(0x003D) /* Stack Pointer Low */ -#define SPH _SFR_MEM8(0x003E) /* Stack Pointer High */ -#define SREG _SFR_MEM8(0x003F) /* Status Register */ - -/* C Language Only */ -#if !defined (__ASSEMBLER__) - -#include - -typedef volatile uint8_t register8_t; -typedef volatile uint16_t register16_t; -typedef volatile uint32_t register32_t; - - -#ifdef _WORDREGISTER -#undef _WORDREGISTER -#endif -#define _WORDREGISTER(regname) \ - __extension__ union \ - { \ - register16_t regname; \ - struct \ - { \ - register8_t regname ## L; \ - register8_t regname ## H; \ - }; \ - } - -#ifdef _DWORDREGISTER -#undef _DWORDREGISTER -#endif -#define _DWORDREGISTER(regname) \ - __extension__ union \ - { \ - register32_t regname; \ - struct \ - { \ - register8_t regname ## 0; \ - register8_t regname ## 1; \ - register8_t regname ## 2; \ - register8_t regname ## 3; \ - }; \ - } - - -/* -========================================================================== -IO Module Structures -========================================================================== -*/ - - -/* --------------------------------------------------------------------------- -VPORT - Virtual Ports --------------------------------------------------------------------------- -*/ - -/* Virtual Port */ -typedef struct VPORT_struct -{ - register8_t DIR; /* I/O Port Data Direction */ - register8_t OUT; /* I/O Port Output */ - register8_t IN; /* I/O Port Input */ - register8_t INTFLAGS; /* Interrupt Flag Register */ -} VPORT_t; - - -/* --------------------------------------------------------------------------- -XOCD - On-Chip Debug System --------------------------------------------------------------------------- -*/ - -/* On-Chip Debug System */ -typedef struct OCD_struct -{ - register8_t OCDR0; /* OCD Register 0 */ - register8_t OCDR1; /* OCD Register 1 */ -} OCD_t; - - -/* --------------------------------------------------------------------------- -CPU - CPU --------------------------------------------------------------------------- -*/ - -/* CCP signatures */ -typedef enum CCP_enum -{ - CCP_SPM_gc = (0x9D<<0), /* SPM Instruction Protection */ - CCP_IOREG_gc = (0xD8<<0), /* IO Register Protection */ -} CCP_t; - - -/* --------------------------------------------------------------------------- -CLK - Clock System --------------------------------------------------------------------------- -*/ - -/* Clock System */ -typedef struct CLK_struct -{ - register8_t CTRL; /* Control Register */ - register8_t PSCTRL; /* Prescaler Control Register */ - register8_t LOCK; /* Lock register */ - register8_t RTCCTRL; /* RTC Control Register */ - register8_t USBCTRL; /* USB Control Register */ -} CLK_t; - - -/* Power Reduction */ -typedef struct PR_struct -{ - register8_t PRGEN; /* General Power Reduction */ - register8_t PRPA; /* Power Reduction Port A */ - register8_t PRPB; /* Power Reduction Port B */ - register8_t PRPC; /* Power Reduction Port C */ - register8_t PRPD; /* Power Reduction Port D */ - register8_t PRPE; /* Power Reduction Port E */ - register8_t PRPF; /* Power Reduction Port F */ -} PR_t; - -/* System Clock Selection */ -typedef enum CLK_SCLKSEL_enum -{ - CLK_SCLKSEL_RC2M_gc = (0x00<<0), /* Internal 2 MHz RC Oscillator */ - CLK_SCLKSEL_RC32M_gc = (0x01<<0), /* Internal 32 MHz RC Oscillator */ - CLK_SCLKSEL_RC32K_gc = (0x02<<0), /* Internal 32.768 kHz RC Oscillator */ - CLK_SCLKSEL_XOSC_gc = (0x03<<0), /* External Crystal Oscillator or Clock */ - CLK_SCLKSEL_PLL_gc = (0x04<<0), /* Phase Locked Loop */ -} CLK_SCLKSEL_t; - -/* Prescaler A Division Factor */ -typedef enum CLK_PSADIV_enum -{ - CLK_PSADIV_1_gc = (0x00<<2), /* Divide by 1 */ - CLK_PSADIV_2_gc = (0x01<<2), /* Divide by 2 */ - CLK_PSADIV_4_gc = (0x03<<2), /* Divide by 4 */ - CLK_PSADIV_8_gc = (0x05<<2), /* Divide by 8 */ - CLK_PSADIV_16_gc = (0x07<<2), /* Divide by 16 */ - CLK_PSADIV_32_gc = (0x09<<2), /* Divide by 32 */ - CLK_PSADIV_64_gc = (0x0B<<2), /* Divide by 64 */ - CLK_PSADIV_128_gc = (0x0D<<2), /* Divide by 128 */ - CLK_PSADIV_256_gc = (0x0F<<2), /* Divide by 256 */ - CLK_PSADIV_512_gc = (0x11<<2), /* Divide by 512 */ -} CLK_PSADIV_t; - -/* Prescaler B and C Division Factor */ -typedef enum CLK_PSBCDIV_enum -{ - CLK_PSBCDIV_1_1_gc = (0x00<<0), /* Divide B by 1 and C by 1 */ - CLK_PSBCDIV_1_2_gc = (0x01<<0), /* Divide B by 1 and C by 2 */ - CLK_PSBCDIV_4_1_gc = (0x02<<0), /* Divide B by 4 and C by 1 */ - CLK_PSBCDIV_2_2_gc = (0x03<<0), /* Divide B by 2 and C by 2 */ -} CLK_PSBCDIV_t; - -/* RTC Clock Source */ -typedef enum CLK_RTCSRC_enum -{ - CLK_RTCSRC_ULP_gc = (0x00<<1), /* 1.024 kHz from internal 32kHz ULP */ - CLK_RTCSRC_TOSC_gc = (0x01<<1), /* 1.024 kHz from 32.768 kHz crystal oscillator on TOSC */ - CLK_RTCSRC_RCOSC_gc = (0x02<<1), /* 1.024 kHz from internal 32.768 kHz RC oscillator */ - CLK_RTCSRC_TOSC32_gc = (0x05<<1), /* 32.768 kHz from 32.768 kHz crystal oscillator on TOSC */ - CLK_RTCSRC_RCOSC32_gc = (0x06<<1), /* 32.768 kHz from internal 32.768 kHz RC oscillator */ - CLK_RTCSRC_EXTCLK_gc = (0x07<<1), /* External Clock from TOSC1 */ -} CLK_RTCSRC_t; - -/* USB Prescaler Division Factor */ -typedef enum CLK_USBPSDIV_enum -{ - CLK_USBPSDIV_1_gc = (0x00<<3), /* Divide by 1 */ - CLK_USBPSDIV_2_gc = (0x01<<3), /* Divide by 2 */ - CLK_USBPSDIV_4_gc = (0x02<<3), /* Divide by 4 */ - CLK_USBPSDIV_8_gc = (0x03<<3), /* Divide by 8 */ - CLK_USBPSDIV_16_gc = (0x04<<3), /* Divide by 16 */ - CLK_USBPSDIV_32_gc = (0x05<<3), /* Divide by 32 */ -} CLK_USBPSDIV_t; - -/* USB Clock Source */ -typedef enum CLK_USBSRC_enum -{ - CLK_USBSRC_PLL_gc = (0x00<<1), /* PLL */ - CLK_USBSRC_RC32M_gc = (0x01<<1), /* Internal 32 MHz RC Oscillator */ -} CLK_USBSRC_t; - - -/* --------------------------------------------------------------------------- -SLEEP - Sleep Controller --------------------------------------------------------------------------- -*/ - -/* Sleep Controller */ -typedef struct SLEEP_struct -{ - register8_t CTRL; /* Control Register */ -} SLEEP_t; - -/* Sleep Mode */ -typedef enum SLEEP_SMODE_enum -{ - SLEEP_SMODE_IDLE_gc = (0x00<<1), /* Idle mode */ - SLEEP_SMODE_PDOWN_gc = (0x02<<1), /* Power-down Mode */ - SLEEP_SMODE_PSAVE_gc = (0x03<<1), /* Power-save Mode */ - SLEEP_SMODE_STDBY_gc = (0x06<<1), /* Standby Mode */ - SLEEP_SMODE_ESTDBY_gc = (0x07<<1), /* Extended Standby Mode */ -} SLEEP_SMODE_t; - - - -#define SLEEP_MODE_IDLE (0x00<<1) -#define SLEEP_MODE_PWR_DOWN (0x02<<1) -#define SLEEP_MODE_PWR_SAVE (0x03<<1) -#define SLEEP_MODE_STANDBY (0x06<<1) -#define SLEEP_MODE_EXT_STANDBY (0x07<<1) -/* --------------------------------------------------------------------------- -OSC - Oscillator --------------------------------------------------------------------------- -*/ - -/* Oscillator */ -typedef struct OSC_struct -{ - register8_t CTRL; /* Control Register */ - register8_t STATUS; /* Status Register */ - register8_t XOSCCTRL; /* External Oscillator Control Register */ - register8_t XOSCFAIL; /* Oscillator Failure Detection Register */ - register8_t RC32KCAL; /* 32.768 kHz Internal Oscillator Calibration Register */ - register8_t PLLCTRL; /* PLL Control Register */ - register8_t DFLLCTRL; /* DFLL Control Register */ -} OSC_t; - -/* Oscillator Frequency Range */ -typedef enum OSC_FRQRANGE_enum -{ - OSC_FRQRANGE_04TO2_gc = (0x00<<6), /* 0.4 - 2 MHz */ - OSC_FRQRANGE_2TO9_gc = (0x01<<6), /* 2 - 9 MHz */ - OSC_FRQRANGE_9TO12_gc = (0x02<<6), /* 9 - 12 MHz */ - OSC_FRQRANGE_12TO16_gc = (0x03<<6), /* 12 - 16 MHz */ -} OSC_FRQRANGE_t; - -/* External Oscillator Selection and Startup Time */ -typedef enum OSC_XOSCSEL_enum -{ - OSC_XOSCSEL_EXTCLK_gc = (0x00<<0), /* External Clock - 6 CLK */ - OSC_XOSCSEL_32KHz_gc = (0x02<<0), /* 32.768 kHz TOSC - 32K CLK */ - OSC_XOSCSEL_XTAL_256CLK_gc = (0x03<<0), /* 0.4-16 MHz XTAL - 256 CLK */ - OSC_XOSCSEL_XTAL_1KCLK_gc = (0x07<<0), /* 0.4-16 MHz XTAL - 1K CLK */ - OSC_XOSCSEL_XTAL_16KCLK_gc = (0x0B<<0), /* 0.4-16 MHz XTAL - 16K CLK */ -} OSC_XOSCSEL_t; - -/* PLL Clock Source */ -typedef enum OSC_PLLSRC_enum -{ - OSC_PLLSRC_RC2M_gc = (0x00<<6), /* Internal 2 MHz RC Oscillator */ - OSC_PLLSRC_RC32M_gc = (0x02<<6), /* Internal 32 MHz RC Oscillator */ - OSC_PLLSRC_XOSC_gc = (0x03<<6), /* External Oscillator */ -} OSC_PLLSRC_t; - -/* 2 MHz DFLL Calibration Reference */ -typedef enum OSC_RC2MCREF_enum -{ - OSC_RC2MCREF_RC32K_gc = (0x00<<0), /* Internal 32.768 kHz RC Oscillator */ - OSC_RC2MCREF_XOSC32K_gc = (0x01<<0), /* External 32.768 kHz Crystal Oscillator */ -} OSC_RC2MCREF_t; - -/* 32 MHz DFLL Calibration Reference */ -typedef enum OSC_RC32MCREF_enum -{ - OSC_RC32MCREF_RC32K_gc = (0x00<<1), /* Internal 32.768 kHz RC Oscillator */ - OSC_RC32MCREF_XOSC32K_gc = (0x01<<1), /* External 32.768 kHz Crystal Oscillator */ - OSC_RC32MCREF_USBSOF_gc = (0x02<<1), /* USB Start of Frame */ -} OSC_RC32MCREF_t; - - -/* --------------------------------------------------------------------------- -DFLL - DFLL --------------------------------------------------------------------------- -*/ - -/* DFLL */ -typedef struct DFLL_struct -{ - register8_t CTRL; /* Control Register */ - register8_t reserved_0x01; - register8_t CALA; /* Calibration Register A */ - register8_t CALB; /* Calibration Register B */ - register8_t COMP0; /* Oscillator Compare Register 0 */ - register8_t COMP1; /* Oscillator Compare Register 1 */ - register8_t COMP2; /* Oscillator Compare Register 2 */ - register8_t reserved_0x07; -} DFLL_t; - - -/* --------------------------------------------------------------------------- -RST - Reset --------------------------------------------------------------------------- -*/ - -/* Reset */ -typedef struct RST_struct -{ - register8_t STATUS; /* Status Register */ - register8_t CTRL; /* Control Register */ -} RST_t; - - -/* --------------------------------------------------------------------------- -WDT - Watch-Dog Timer --------------------------------------------------------------------------- -*/ - -/* Watch-Dog Timer */ -typedef struct WDT_struct -{ - register8_t CTRL; /* Control */ - register8_t WINCTRL; /* Windowed Mode Control */ - register8_t STATUS; /* Status */ -} WDT_t; - -/* Period setting */ -typedef enum WDT_PER_enum -{ - WDT_PER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ - WDT_PER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ - WDT_PER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ - WDT_PER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ - WDT_PER_128CLK_gc = (0x04<<2), /* 128 cycles (0.128s @ 3.3V) */ - WDT_PER_256CLK_gc = (0x05<<2), /* 256 cycles (0.256s @ 3.3V) */ - WDT_PER_512CLK_gc = (0x06<<2), /* 512 cycles (0.512s @ 3.3V) */ - WDT_PER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ - WDT_PER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ - WDT_PER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ - WDT_PER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ -} WDT_PER_t; - -/* Closed window period */ -typedef enum WDT_WPER_enum -{ - WDT_WPER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ - WDT_WPER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ - WDT_WPER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ - WDT_WPER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ - WDT_WPER_128CLK_gc = (0x04<<2), /* 128 cycles (0.128s @ 3.3V) */ - WDT_WPER_256CLK_gc = (0x05<<2), /* 256 cycles (0.256s @ 3.3V) */ - WDT_WPER_512CLK_gc = (0x06<<2), /* 512 cycles (0.512s @ 3.3V) */ - WDT_WPER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ - WDT_WPER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ - WDT_WPER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ - WDT_WPER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ -} WDT_WPER_t; - - -/* --------------------------------------------------------------------------- -MCU - MCU Control --------------------------------------------------------------------------- -*/ - -/* MCU Control */ -typedef struct MCU_struct -{ - register8_t DEVID0; /* Device ID byte 0 */ - register8_t DEVID1; /* Device ID byte 1 */ - register8_t DEVID2; /* Device ID byte 2 */ - register8_t REVID; /* Revision ID */ - register8_t JTAGUID; /* JTAG User ID */ - register8_t reserved_0x05; - register8_t MCUCR; /* MCU Control */ - register8_t ANAINIT; /* Analog Startup Delay */ - register8_t EVSYSLOCK; /* Event System Lock */ - register8_t AWEXLOCK; /* AWEX Lock */ - register8_t reserved_0x0A; - register8_t reserved_0x0B; -} MCU_t; - - -/* --------------------------------------------------------------------------- -PMIC - Programmable Multi-level Interrupt Controller --------------------------------------------------------------------------- -*/ - -/* Programmable Multi-level Interrupt Controller */ -typedef struct PMIC_struct -{ - register8_t STATUS; /* Status Register */ - register8_t INTPRI; /* Interrupt Priority */ - register8_t CTRL; /* Control Register */ - register8_t reserved_0x03; - register8_t reserved_0x04; - register8_t reserved_0x05; - register8_t reserved_0x06; - register8_t reserved_0x07; - register8_t reserved_0x08; - register8_t reserved_0x09; - register8_t reserved_0x0A; - register8_t reserved_0x0B; - register8_t reserved_0x0C; - register8_t reserved_0x0D; - register8_t reserved_0x0E; - register8_t reserved_0x0F; -} PMIC_t; - - -/* --------------------------------------------------------------------------- -PORTCFG - Port Configuration --------------------------------------------------------------------------- -*/ - -/* I/O port Configuration */ -typedef struct PORTCFG_struct -{ - register8_t MPCMASK; /* Multi-pin Configuration Mask */ - register8_t reserved_0x01; - register8_t VPCTRLA; /* Virtual Port Control Register A */ - register8_t VPCTRLB; /* Virtual Port Control Register B */ - register8_t CLKEVOUT; /* Clock and Event Out Register */ - register8_t EBIOUT; /* EBI Output register */ - register8_t EVOUTSEL; /* Event Output Select */ -} PORTCFG_t; - -/* Virtual Port Mapping */ -typedef enum PORTCFG_VP02MAP_enum -{ - PORTCFG_VP02MAP_PORTA_gc = (0x00<<0), /* Mapped To PORTA */ - PORTCFG_VP02MAP_PORTB_gc = (0x01<<0), /* Mapped To PORTB */ - PORTCFG_VP02MAP_PORTC_gc = (0x02<<0), /* Mapped To PORTC */ - PORTCFG_VP02MAP_PORTD_gc = (0x03<<0), /* Mapped To PORTD */ - PORTCFG_VP02MAP_PORTE_gc = (0x04<<0), /* Mapped To PORTE */ - PORTCFG_VP02MAP_PORTF_gc = (0x05<<0), /* Mapped To PORTF */ - PORTCFG_VP02MAP_PORTG_gc = (0x06<<0), /* Mapped To PORTG */ - PORTCFG_VP02MAP_PORTH_gc = (0x07<<0), /* Mapped To PORTH */ - PORTCFG_VP02MAP_PORTJ_gc = (0x08<<0), /* Mapped To PORTJ */ - PORTCFG_VP02MAP_PORTK_gc = (0x09<<0), /* Mapped To PORTK */ - PORTCFG_VP02MAP_PORTL_gc = (0x0A<<0), /* Mapped To PORTL */ - PORTCFG_VP02MAP_PORTM_gc = (0x0B<<0), /* Mapped To PORTM */ - PORTCFG_VP02MAP_PORTN_gc = (0x0C<<0), /* Mapped To PORTN */ - PORTCFG_VP02MAP_PORTP_gc = (0x0D<<0), /* Mapped To PORTP */ - PORTCFG_VP02MAP_PORTQ_gc = (0x0E<<0), /* Mapped To PORTQ */ - PORTCFG_VP02MAP_PORTR_gc = (0x0F<<0), /* Mapped To PORTR */ -} PORTCFG_VP02MAP_t; - -/* Virtual Port Mapping */ -typedef enum PORTCFG_VP13MAP_enum -{ - PORTCFG_VP13MAP_PORTA_gc = (0x00<<4), /* Mapped To PORTA */ - PORTCFG_VP13MAP_PORTB_gc = (0x01<<4), /* Mapped To PORTB */ - PORTCFG_VP13MAP_PORTC_gc = (0x02<<4), /* Mapped To PORTC */ - PORTCFG_VP13MAP_PORTD_gc = (0x03<<4), /* Mapped To PORTD */ - PORTCFG_VP13MAP_PORTE_gc = (0x04<<4), /* Mapped To PORTE */ - PORTCFG_VP13MAP_PORTF_gc = (0x05<<4), /* Mapped To PORTF */ - PORTCFG_VP13MAP_PORTG_gc = (0x06<<4), /* Mapped To PORTG */ - PORTCFG_VP13MAP_PORTH_gc = (0x07<<4), /* Mapped To PORTH */ - PORTCFG_VP13MAP_PORTJ_gc = (0x08<<4), /* Mapped To PORTJ */ - PORTCFG_VP13MAP_PORTK_gc = (0x09<<4), /* Mapped To PORTK */ - PORTCFG_VP13MAP_PORTL_gc = (0x0A<<4), /* Mapped To PORTL */ - PORTCFG_VP13MAP_PORTM_gc = (0x0B<<4), /* Mapped To PORTM */ - PORTCFG_VP13MAP_PORTN_gc = (0x0C<<4), /* Mapped To PORTN */ - PORTCFG_VP13MAP_PORTP_gc = (0x0D<<4), /* Mapped To PORTP */ - PORTCFG_VP13MAP_PORTQ_gc = (0x0E<<4), /* Mapped To PORTQ */ - PORTCFG_VP13MAP_PORTR_gc = (0x0F<<4), /* Mapped To PORTR */ -} PORTCFG_VP13MAP_t; - -/* System Clock Output Port */ -typedef enum PORTCFG_CLKOUT_enum -{ - PORTCFG_CLKOUT_OFF_gc = (0x00<<0), /* System Clock Output Disabled */ - PORTCFG_CLKOUT_PC7_gc = (0x01<<0), /* System Clock Output on Port C pin 7 */ - PORTCFG_CLKOUT_PD7_gc = (0x02<<0), /* System Clock Output on Port D pin 7 */ - PORTCFG_CLKOUT_PE7_gc = (0x03<<0), /* System Clock Output on Port E pin 7 */ -} PORTCFG_CLKOUT_t; - -/* Peripheral Clock Output Select */ -typedef enum PORTCFG_CLKOUTSEL_enum -{ - PORTCFG_CLKOUTSEL_CLK1X_gc = (0x00<<2), /* 1x Peripheral Clock Output to pin */ - PORTCFG_CLKOUTSEL_CLK2X_gc = (0x01<<2), /* 2x Peripheral Clock Output to pin */ - PORTCFG_CLKOUTSEL_CLK4X_gc = (0x02<<2), /* 4x Peripheral Clock Output to pin */ -} PORTCFG_CLKOUTSEL_t; - -/* Event Output Port */ -typedef enum PORTCFG_EVOUT_enum -{ - PORTCFG_EVOUT_OFF_gc = (0x00<<4), /* Event Output Disabled */ - PORTCFG_EVOUT_PC7_gc = (0x01<<4), /* Event Channel 7 Output on Port C pin 7 */ - PORTCFG_EVOUT_PD7_gc = (0x02<<4), /* Event Channel 7 Output on Port D pin 7 */ - PORTCFG_EVOUT_PE7_gc = (0x03<<4), /* Event Channel 7 Output on Port E pin 7 */ -} PORTCFG_EVOUT_t; - -/* Clock and Event Output Port */ -typedef enum PORTCFG_CLKEVPIN_enum -{ - PORTCFG_CLKEVPIN_PIN7_gc = (0x00<<7), /* Clock and Event Ouput on PIN 7 */ - PORTCFG_CLKEVPIN_PIN4_gc = (0x01<<7), /* Clock and Event Ouput on PIN 4 */ -} PORTCFG_CLKEVPIN_t; - -/* EBI Address Output Port */ -typedef enum PORTCFG_EBIADROUT_enum -{ - PORTCFG_EBIADROUT_PF_gc = (0x00<<2), /* EBI port 3 address output on PORTF pins 0 to 7 */ - PORTCFG_EBIADROUT_PE_gc = (0x01<<2), /* EBI port 3 address output on PORTE pins 0 to 7 */ - PORTCFG_EBIADROUT_PFH_gc = (0x02<<2), /* EBI port 3 address output on PORTF pins 4 to 7 */ - PORTCFG_EBIADROUT_PEH_gc = (0x03<<2), /* EBI port 3 address output on PORTE pins 4 to 7 */ -} PORTCFG_EBIADROUT_t; - -/* EBI Chip Select Output Port */ -typedef enum PORTCFG_EBICSOUT_enum -{ - PORTCFG_EBICSOUT_PH_gc = (0x00<<0), /* EBI chip select output to PORTH pin 4 to 7 */ - PORTCFG_EBICSOUT_PL_gc = (0x01<<0), /* EBI chip select output to PORTL pin 4 to 7 */ - PORTCFG_EBICSOUT_PF_gc = (0x02<<0), /* EBI chip select output to PORTF pin 4 to 7 */ - PORTCFG_EBICSOUT_PE_gc = (0x03<<0), /* EBI chip select output to PORTE pin 4 to 7 */ -} PORTCFG_EBICSOUT_t; - -/* Event Output Select */ -typedef enum PORTCFG_EVOUTSEL_enum -{ - PORTCFG_EVOUTSEL_0_gc = (0x00<<0), /* Event Channel 0 output to pin */ - PORTCFG_EVOUTSEL_1_gc = (0x01<<0), /* Event Channel 1 output to pin */ - PORTCFG_EVOUTSEL_2_gc = (0x02<<0), /* Event Channel 2 output to pin */ - PORTCFG_EVOUTSEL_3_gc = (0x03<<0), /* Event Channel 3 output to pin */ - PORTCFG_EVOUTSEL_4_gc = (0x04<<0), /* Event Channel 4 output to pin */ - PORTCFG_EVOUTSEL_5_gc = (0x05<<0), /* Event Channel 5 output to pin */ - PORTCFG_EVOUTSEL_6_gc = (0x06<<0), /* Event Channel 6 output to pin */ - PORTCFG_EVOUTSEL_7_gc = (0x07<<0), /* Event Channel 7 output to pin */ -} PORTCFG_EVOUTSEL_t; - - -/* --------------------------------------------------------------------------- -AES - AES Module --------------------------------------------------------------------------- -*/ - -/* AES Module */ -typedef struct AES_struct -{ - register8_t CTRL; /* AES Control Register */ - register8_t STATUS; /* AES Status Register */ - register8_t STATE; /* AES State Register */ - register8_t KEY; /* AES Key Register */ - register8_t INTCTRL; /* AES Interrupt Control Register */ -} AES_t; - -/* Interrupt level */ -typedef enum AES_INTLVL_enum -{ - AES_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - AES_INTLVL_LO_gc = (0x01<<0), /* Low Level */ - AES_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ - AES_INTLVL_HI_gc = (0x03<<0), /* High Level */ -} AES_INTLVL_t; - - -/* --------------------------------------------------------------------------- -CRC - Cyclic Redundancy Checker --------------------------------------------------------------------------- -*/ - -/* Cyclic Redundancy Checker */ -typedef struct CRC_struct -{ - register8_t CTRL; /* Control Register */ - register8_t STATUS; /* Status Register */ - register8_t reserved_0x02; - register8_t DATAIN; /* Data Input */ - register8_t CHECKSUM0; /* Checksum byte 0 */ - register8_t CHECKSUM1; /* Checksum byte 1 */ - register8_t CHECKSUM2; /* Checksum byte 2 */ - register8_t CHECKSUM3; /* Checksum byte 3 */ -} CRC_t; - -/* Reset */ -typedef enum CRC_RESET_enum -{ - CRC_RESET_NO_gc = (0x00<<6), /* No Reset */ - CRC_RESET_RESET0_gc = (0x02<<6), /* Reset CRC with CHECKSUM to all zeros */ - CRC_RESET_RESET1_gc = (0x03<<6), /* Reset CRC with CHECKSUM to all ones */ -} CRC_RESET_t; - -/* Input Source */ -typedef enum CRC_SOURCE_enum -{ - CRC_SOURCE_DISABLE_gc = (0x00<<0), /* Disabled */ - CRC_SOURCE_IO_gc = (0x01<<0), /* I/O Interface */ - CRC_SOURCE_FLASH_gc = (0x02<<0), /* Flash */ - CRC_SOURCE_DMAC0_gc = (0x04<<0), /* DMAC Channel 0 */ - CRC_SOURCE_DMAC1_gc = (0x05<<0), /* DMAC Channel 1 */ - CRC_SOURCE_DMAC2_gc = (0x06<<0), /* DMAC Channel 2 */ - CRC_SOURCE_DMAC3_gc = (0x07<<0), /* DMAC Channel 3 */ -} CRC_SOURCE_t; - - -/* --------------------------------------------------------------------------- -DMA - DMA Controller --------------------------------------------------------------------------- -*/ - -/* DMA Channel */ -typedef struct DMA_CH_struct -{ - register8_t CTRLA; /* Channel Control */ - register8_t CTRLB; /* Channel Control */ - register8_t ADDRCTRL; /* Address Control */ - register8_t TRIGSRC; /* Channel Trigger Source */ - _WORDREGISTER(TRFCNT); /* Channel Block Transfer Count */ - register8_t REPCNT; /* Channel Repeat Count */ - register8_t reserved_0x07; - register8_t SRCADDR0; /* Channel Source Address 0 */ - register8_t SRCADDR1; /* Channel Source Address 1 */ - register8_t SRCADDR2; /* Channel Source Address 2 */ - register8_t reserved_0x0B; - register8_t DESTADDR0; /* Channel Destination Address 0 */ - register8_t DESTADDR1; /* Channel Destination Address 1 */ - register8_t DESTADDR2; /* Channel Destination Address 2 */ - register8_t reserved_0x0F; -} DMA_CH_t; - - -/* DMA Controller */ -typedef struct DMA_struct -{ - register8_t CTRL; /* Control */ - register8_t reserved_0x01; - register8_t reserved_0x02; - register8_t INTFLAGS; /* Transfer Interrupt Status */ - register8_t STATUS; /* Status */ - register8_t reserved_0x05; - _WORDREGISTER(TEMP); /* Temporary Register For 16/24-bit Access */ - register8_t reserved_0x08; - register8_t reserved_0x09; - register8_t reserved_0x0A; - register8_t reserved_0x0B; - register8_t reserved_0x0C; - register8_t reserved_0x0D; - register8_t reserved_0x0E; - register8_t reserved_0x0F; - DMA_CH_t CH0; /* DMA Channel 0 */ - DMA_CH_t CH1; /* DMA Channel 1 */ - DMA_CH_t CH2; /* DMA Channel 2 */ - DMA_CH_t CH3; /* DMA Channel 3 */ -} DMA_t; - -/* Burst mode */ -typedef enum DMA_CH_BURSTLEN_enum -{ - DMA_CH_BURSTLEN_1BYTE_gc = (0x00<<0), /* 1-byte burst mode */ - DMA_CH_BURSTLEN_2BYTE_gc = (0x01<<0), /* 2-byte burst mode */ - DMA_CH_BURSTLEN_4BYTE_gc = (0x02<<0), /* 4-byte burst mode */ - DMA_CH_BURSTLEN_8BYTE_gc = (0x03<<0), /* 8-byte burst mode */ -} DMA_CH_BURSTLEN_t; - -/* Source address reload mode */ -typedef enum DMA_CH_SRCRELOAD_enum -{ - DMA_CH_SRCRELOAD_NONE_gc = (0x00<<6), /* No reload */ - DMA_CH_SRCRELOAD_BLOCK_gc = (0x01<<6), /* Reload at end of block */ - DMA_CH_SRCRELOAD_BURST_gc = (0x02<<6), /* Reload at end of burst */ - DMA_CH_SRCRELOAD_TRANSACTION_gc = (0x03<<6), /* Reload at end of transaction */ -} DMA_CH_SRCRELOAD_t; - -/* Source addressing mode */ -typedef enum DMA_CH_SRCDIR_enum -{ - DMA_CH_SRCDIR_FIXED_gc = (0x00<<4), /* Fixed */ - DMA_CH_SRCDIR_INC_gc = (0x01<<4), /* Increment */ - DMA_CH_SRCDIR_DEC_gc = (0x02<<4), /* Decrement */ -} DMA_CH_SRCDIR_t; - -/* Destination adress reload mode */ -typedef enum DMA_CH_DESTRELOAD_enum -{ - DMA_CH_DESTRELOAD_NONE_gc = (0x00<<2), /* No reload */ - DMA_CH_DESTRELOAD_BLOCK_gc = (0x01<<2), /* Reload at end of block */ - DMA_CH_DESTRELOAD_BURST_gc = (0x02<<2), /* Reload at end of burst */ - DMA_CH_DESTRELOAD_TRANSACTION_gc = (0x03<<2), /* Reload at end of transaction */ -} DMA_CH_DESTRELOAD_t; - -/* Destination adressing mode */ -typedef enum DMA_CH_DESTDIR_enum -{ - DMA_CH_DESTDIR_FIXED_gc = (0x00<<0), /* Fixed */ - DMA_CH_DESTDIR_INC_gc = (0x01<<0), /* Increment */ - DMA_CH_DESTDIR_DEC_gc = (0x02<<0), /* Decrement */ -} DMA_CH_DESTDIR_t; - -/* Transfer trigger source */ -typedef enum DMA_CH_TRIGSRC_enum -{ - DMA_CH_TRIGSRC_OFF_gc = (0x00<<0), /* Off software triggers only */ - DMA_CH_TRIGSRC_EVSYS_CH0_gc = (0x01<<0), /* Event System Channel 0 */ - DMA_CH_TRIGSRC_EVSYS_CH1_gc = (0x02<<0), /* Event System Channel 1 */ - DMA_CH_TRIGSRC_EVSYS_CH2_gc = (0x03<<0), /* Event System Channel 2 */ - DMA_CH_TRIGSRC_ADCA_CH0_gc = (0x10<<0), /* ADCA Channel 0 */ - DMA_CH_TRIGSRC_ADCA_CH1_gc = (0x11<<0), /* ADCA Channel 1 */ - DMA_CH_TRIGSRC_ADCA_CH2_gc = (0x12<<0), /* ADCA Channel 2 */ - DMA_CH_TRIGSRC_ADCA_CH3_gc = (0x13<<0), /* ADCA Channel 3 */ - DMA_CH_TRIGSRC_ADCA_CH4_gc = (0x14<<0), /* ADCA Channel 0,1,2,3 combined */ - DMA_CH_TRIGSRC_DACA_CH0_gc = (0x15<<0), /* DACA Channel 0 */ - DMA_CH_TRIGSRC_DACA_CH1_gc = (0x16<<0), /* DACA Channel 1 */ - DMA_CH_TRIGSRC_ADCB_CH0_gc = (0x20<<0), /* ADCB Channel 0 */ - DMA_CH_TRIGSRC_ADCB_CH1_gc = (0x21<<0), /* ADCB Channel 1 */ - DMA_CH_TRIGSRC_ADCB_CH2_gc = (0x22<<0), /* ADCB Channel 2 */ - DMA_CH_TRIGSRC_ADCB_CH3_gc = (0x23<<0), /* ADCB Channel 3 */ - DMA_CH_TRIGSRC_ADCB_CH4_gc = (0x24<<0), /* ADCB Channel 0,1,2,3 combined */ - DMA_CH_TRIGSRC_DACB_CH0_gc = (0x25<<0), /* DACB Channel 0 */ - DMA_CH_TRIGSRC_DACB_CH1_gc = (0x26<<0), /* DACB Channel 1 */ - DMA_CH_TRIGSRC_TCC0_OVF_gc = (0x40<<0), /* Timer/Counter C0 Overflow */ - DMA_CH_TRIGSRC_TCC0_ERR_gc = (0x41<<0), /* Timer/Counter C0 Error */ - DMA_CH_TRIGSRC_TCC0_CCA_gc = (0x42<<0), /* Timer/Counter C0 Compare or Capture A */ - DMA_CH_TRIGSRC_TCC0_CCB_gc = (0x43<<0), /* Timer/Counter C0 Compare or Capture B */ - DMA_CH_TRIGSRC_TCC0_CCC_gc = (0x44<<0), /* Timer/Counter C0 Compare or Capture C */ - DMA_CH_TRIGSRC_TCC0_CCD_gc = (0x45<<0), /* Timer/Counter C0 Compare or Capture D */ - DMA_CH_TRIGSRC_TCC1_OVF_gc = (0x46<<0), /* Timer/Counter C1 Overflow */ - DMA_CH_TRIGSRC_TCC1_ERR_gc = (0x47<<0), /* Timer/Counter C1 Error */ - DMA_CH_TRIGSRC_TCC1_CCA_gc = (0x48<<0), /* Timer/Counter C1 Compare or Capture A */ - DMA_CH_TRIGSRC_TCC1_CCB_gc = (0x49<<0), /* Timer/Counter C1 Compare or Capture B */ - DMA_CH_TRIGSRC_SPIC_gc = (0x4A<<0), /* SPI C Transfer Complete */ - DMA_CH_TRIGSRC_USARTC0_RXC_gc = (0x4B<<0), /* USART C0 Receive Complete */ - DMA_CH_TRIGSRC_USARTC0_DRE_gc = (0x4C<<0), /* USART C0 Data Register Empty */ - DMA_CH_TRIGSRC_USARTC1_RXC_gc = (0x4E<<0), /* USART C1 Receive Complete */ - DMA_CH_TRIGSRC_USARTC1_DRE_gc = (0x4F<<0), /* USART C1 Data Register Empty */ - DMA_CH_TRIGSRC_TCD0_OVF_gc = (0x60<<0), /* Timer/Counter D0 Overflow */ - DMA_CH_TRIGSRC_TCD0_ERR_gc = (0x61<<0), /* Timer/Counter D0 Error */ - DMA_CH_TRIGSRC_TCD0_CCA_gc = (0x62<<0), /* Timer/Counter D0 Compare or Capture A */ - DMA_CH_TRIGSRC_TCD0_CCB_gc = (0x63<<0), /* Timer/Counter D0 Compare or Capture B */ - DMA_CH_TRIGSRC_TCD0_CCC_gc = (0x64<<0), /* Timer/Counter D0 Compare or Capture C */ - DMA_CH_TRIGSRC_TCD0_CCD_gc = (0x65<<0), /* Timer/Counter D0 Compare or Capture D */ - DMA_CH_TRIGSRC_TCD1_OVF_gc = (0x66<<0), /* Timer/Counter D1 Overflow */ - DMA_CH_TRIGSRC_TCD1_ERR_gc = (0x67<<0), /* Timer/Counter D1 Error */ - DMA_CH_TRIGSRC_TCD1_CCA_gc = (0x68<<0), /* Timer/Counter D1 Compare or Capture A */ - DMA_CH_TRIGSRC_TCD1_CCB_gc = (0x69<<0), /* Timer/Counter D1 Compare or Capture B */ - DMA_CH_TRIGSRC_SPID_gc = (0x6A<<0), /* SPI D Transfer Complete */ - DMA_CH_TRIGSRC_USARTD0_RXC_gc = (0x6B<<0), /* USART D0 Receive Complete */ - DMA_CH_TRIGSRC_USARTD0_DRE_gc = (0x6C<<0), /* USART D0 Data Register Empty */ - DMA_CH_TRIGSRC_USARTD1_RXC_gc = (0x6E<<0), /* USART D1 Receive Complete */ - DMA_CH_TRIGSRC_USARTD1_DRE_gc = (0x6F<<0), /* USART D1 Data Register Empty */ - DMA_CH_TRIGSRC_TCE0_OVF_gc = (0x80<<0), /* Timer/Counter E0 Overflow */ - DMA_CH_TRIGSRC_TCE0_ERR_gc = (0x81<<0), /* Timer/Counter E0 Error */ - DMA_CH_TRIGSRC_TCE0_CCA_gc = (0x82<<0), /* Timer/Counter E0 Compare or Capture A */ - DMA_CH_TRIGSRC_TCE0_CCB_gc = (0x83<<0), /* Timer/Counter E0 Compare or Capture B */ - DMA_CH_TRIGSRC_TCE0_CCC_gc = (0x84<<0), /* Timer/Counter E0 Compare or Capture C */ - DMA_CH_TRIGSRC_TCE0_CCD_gc = (0x85<<0), /* Timer/Counter E0 Compare or Capture D */ - DMA_CH_TRIGSRC_TCE1_OVF_gc = (0x86<<0), /* Timer/Counter E1 Overflow */ - DMA_CH_TRIGSRC_TCE1_ERR_gc = (0x87<<0), /* Timer/Counter E1 Error */ - DMA_CH_TRIGSRC_TCE1_CCA_gc = (0x88<<0), /* Timer/Counter E1 Compare or Capture A */ - DMA_CH_TRIGSRC_TCE1_CCB_gc = (0x89<<0), /* Timer/Counter E1 Compare or Capture B */ - DMA_CH_TRIGSRC_SPIE_gc = (0x8A<<0), /* SPI E Transfer Complete */ - DMA_CH_TRIGSRC_USARTE0_RXC_gc = (0x8B<<0), /* USART E0 Receive Complete */ - DMA_CH_TRIGSRC_USARTE0_DRE_gc = (0x8C<<0), /* USART E0 Data Register Empty */ - DMA_CH_TRIGSRC_USARTE1_RXC_gc = (0x8E<<0), /* USART E1 Receive Complete */ - DMA_CH_TRIGSRC_USARTE1_DRE_gc = (0x8F<<0), /* USART E1 Data Register Empty */ - DMA_CH_TRIGSRC_TCF0_OVF_gc = (0xA0<<0), /* Timer/Counter F0 Overflow */ - DMA_CH_TRIGSRC_TCF0_ERR_gc = (0xA1<<0), /* Timer/Counter F0 Error */ - DMA_CH_TRIGSRC_TCF0_CCA_gc = (0xA2<<0), /* Timer/Counter F0 Compare or Capture A */ - DMA_CH_TRIGSRC_TCF0_CCB_gc = (0xA3<<0), /* Timer/Counter F0 Compare or Capture B */ - DMA_CH_TRIGSRC_TCF0_CCC_gc = (0xA4<<0), /* Timer/Counter F0 Compare or Capture C */ - DMA_CH_TRIGSRC_TCF0_CCD_gc = (0xA5<<0), /* Timer/Counter F0 Compare or Capture D */ - DMA_CH_TRIGSRC_TCF1_OVF_gc = (0xA6<<0), /* Timer/Counter F1 Overflow */ - DMA_CH_TRIGSRC_TCF1_ERR_gc = (0xA7<<0), /* Timer/Counter F1 Error */ - DMA_CH_TRIGSRC_TCF1_CCA_gc = (0xA8<<0), /* Timer/Counter F1 Compare or Capture A */ - DMA_CH_TRIGSRC_TCF1_CCB_gc = (0xA9<<0), /* Timer/Counter F1 Compare or Capture B */ - DMA_CH_TRIGSRC_SPIF_gc = (0xAA<<0), /* SPI F Transfer Complete */ - DMA_CH_TRIGSRC_USARTF0_RXC_gc = (0xAB<<0), /* USART F0 Receive Complete */ - DMA_CH_TRIGSRC_USARTF0_DRE_gc = (0xAC<<0), /* USART F0 Data Register Empty */ - DMA_CH_TRIGSRC_USARTF1_RXC_gc = (0xAE<<0), /* USART F1 Receive Complete */ - DMA_CH_TRIGSRC_USARTF1_DRE_gc = (0xAF<<0), /* USART F1 Data Register Empty */ -} DMA_CH_TRIGSRC_t; - -/* Double buffering mode */ -typedef enum DMA_DBUFMODE_enum -{ - DMA_DBUFMODE_DISABLED_gc = (0x00<<2), /* Double buffering disabled */ - DMA_DBUFMODE_CH01_gc = (0x01<<2), /* Double buffering enabled on channel 0/1 */ - DMA_DBUFMODE_CH23_gc = (0x02<<2), /* Double buffering enabled on channel 2/3 */ - DMA_DBUFMODE_CH01CH23_gc = (0x03<<2), /* Double buffering enabled on ch. 0/1 and ch. 2/3 */ -} DMA_DBUFMODE_t; - -/* Priority mode */ -typedef enum DMA_PRIMODE_enum -{ - DMA_PRIMODE_RR0123_gc = (0x00<<0), /* Round Robin */ - DMA_PRIMODE_CH0RR123_gc = (0x01<<0), /* Channel 0 > Round Robin on channel 1/2/3 */ - DMA_PRIMODE_CH01RR23_gc = (0x02<<0), /* Channel 0 > channel 1 > Round Robin on channel 2/3 */ - DMA_PRIMODE_CH0123_gc = (0x03<<0), /* Channel 0 > channel 1 > channel 2 > channel 3 */ -} DMA_PRIMODE_t; - -/* Interrupt level */ -typedef enum DMA_CH_ERRINTLVL_enum -{ - DMA_CH_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ - DMA_CH_ERRINTLVL_LO_gc = (0x01<<2), /* Low level */ - DMA_CH_ERRINTLVL_MED_gc = (0x02<<2), /* Medium level */ - DMA_CH_ERRINTLVL_HI_gc = (0x03<<2), /* High level */ -} DMA_CH_ERRINTLVL_t; - -/* Interrupt level */ -typedef enum DMA_CH_TRNINTLVL_enum -{ - DMA_CH_TRNINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ - DMA_CH_TRNINTLVL_LO_gc = (0x01<<0), /* Low level */ - DMA_CH_TRNINTLVL_MED_gc = (0x02<<0), /* Medium level */ - DMA_CH_TRNINTLVL_HI_gc = (0x03<<0), /* High level */ -} DMA_CH_TRNINTLVL_t; - - -/* --------------------------------------------------------------------------- -EVSYS - Event System --------------------------------------------------------------------------- -*/ - -/* Event System */ -typedef struct EVSYS_struct -{ - register8_t CH0MUX; /* Event Channel 0 Multiplexer */ - register8_t CH1MUX; /* Event Channel 1 Multiplexer */ - register8_t CH2MUX; /* Event Channel 2 Multiplexer */ - register8_t CH3MUX; /* Event Channel 3 Multiplexer */ - register8_t CH4MUX; /* Event Channel 4 Multiplexer */ - register8_t CH5MUX; /* Event Channel 5 Multiplexer */ - register8_t CH6MUX; /* Event Channel 6 Multiplexer */ - register8_t CH7MUX; /* Event Channel 7 Multiplexer */ - register8_t CH0CTRL; /* Channel 0 Control Register */ - register8_t CH1CTRL; /* Channel 1 Control Register */ - register8_t CH2CTRL; /* Channel 2 Control Register */ - register8_t CH3CTRL; /* Channel 3 Control Register */ - register8_t CH4CTRL; /* Channel 4 Control Register */ - register8_t CH5CTRL; /* Channel 5 Control Register */ - register8_t CH6CTRL; /* Channel 6 Control Register */ - register8_t CH7CTRL; /* Channel 7 Control Register */ - register8_t STROBE; /* Event Strobe */ - register8_t DATA; /* Event Data */ -} EVSYS_t; - -/* Quadrature Decoder Index Recognition Mode */ -typedef enum EVSYS_QDIRM_enum -{ - EVSYS_QDIRM_00_gc = (0x00<<5), /* QDPH0 = 0, QDPH90 = 0 */ - EVSYS_QDIRM_01_gc = (0x01<<5), /* QDPH0 = 0, QDPH90 = 1 */ - EVSYS_QDIRM_10_gc = (0x02<<5), /* QDPH0 = 1, QDPH90 = 0 */ - EVSYS_QDIRM_11_gc = (0x03<<5), /* QDPH0 = 1, QDPH90 = 1 */ -} EVSYS_QDIRM_t; - -/* Digital filter coefficient */ -typedef enum EVSYS_DIGFILT_enum -{ - EVSYS_DIGFILT_1SAMPLE_gc = (0x00<<0), /* 1 SAMPLE */ - EVSYS_DIGFILT_2SAMPLES_gc = (0x01<<0), /* 2 SAMPLES */ - EVSYS_DIGFILT_3SAMPLES_gc = (0x02<<0), /* 3 SAMPLES */ - EVSYS_DIGFILT_4SAMPLES_gc = (0x03<<0), /* 4 SAMPLES */ - EVSYS_DIGFILT_5SAMPLES_gc = (0x04<<0), /* 5 SAMPLES */ - EVSYS_DIGFILT_6SAMPLES_gc = (0x05<<0), /* 6 SAMPLES */ - EVSYS_DIGFILT_7SAMPLES_gc = (0x06<<0), /* 7 SAMPLES */ - EVSYS_DIGFILT_8SAMPLES_gc = (0x07<<0), /* 8 SAMPLES */ -} EVSYS_DIGFILT_t; - -/* Event Channel multiplexer input selection */ -typedef enum EVSYS_CHMUX_enum -{ - EVSYS_CHMUX_OFF_gc = (0x00<<0), /* Off */ - EVSYS_CHMUX_RTC_OVF_gc = (0x08<<0), /* RTC Overflow */ - EVSYS_CHMUX_RTC_CMP_gc = (0x09<<0), /* RTC Compare Match */ - EVSYS_CHMUX_USB_gc = (0x0A<<0), /* USB Setup, SOF, CRC error and UNF/OVF */ - EVSYS_CHMUX_ACA_CH0_gc = (0x10<<0), /* Analog Comparator A Channel 0 */ - EVSYS_CHMUX_ACA_CH1_gc = (0x11<<0), /* Analog Comparator A Channel 1 */ - EVSYS_CHMUX_ACA_WIN_gc = (0x12<<0), /* Analog Comparator A Window */ - EVSYS_CHMUX_ACB_CH0_gc = (0x13<<0), /* Analog Comparator B Channel 0 */ - EVSYS_CHMUX_ACB_CH1_gc = (0x14<<0), /* Analog Comparator B Channel 1 */ - EVSYS_CHMUX_ACB_WIN_gc = (0x15<<0), /* Analog Comparator B Window */ - EVSYS_CHMUX_ADCA_CH0_gc = (0x20<<0), /* ADC A Channel 0 */ - EVSYS_CHMUX_ADCA_CH1_gc = (0x21<<0), /* ADC A Channel 1 */ - EVSYS_CHMUX_ADCA_CH2_gc = (0x22<<0), /* ADC A Channel 2 */ - EVSYS_CHMUX_ADCA_CH3_gc = (0x23<<0), /* ADC A Channel 3 */ - EVSYS_CHMUX_ADCB_CH0_gc = (0x24<<0), /* ADC B Channel 0 */ - EVSYS_CHMUX_ADCB_CH1_gc = (0x25<<0), /* ADC B Channel 1 */ - EVSYS_CHMUX_ADCB_CH2_gc = (0x26<<0), /* ADC B Channel 2 */ - EVSYS_CHMUX_ADCB_CH3_gc = (0x27<<0), /* ADC B Channel 3 */ - EVSYS_CHMUX_PORTA_PIN0_gc = (0x50<<0), /* Port A, Pin0 */ - EVSYS_CHMUX_PORTA_PIN1_gc = (0x51<<0), /* Port A, Pin1 */ - EVSYS_CHMUX_PORTA_PIN2_gc = (0x52<<0), /* Port A, Pin2 */ - EVSYS_CHMUX_PORTA_PIN3_gc = (0x53<<0), /* Port A, Pin3 */ - EVSYS_CHMUX_PORTA_PIN4_gc = (0x54<<0), /* Port A, Pin4 */ - EVSYS_CHMUX_PORTA_PIN5_gc = (0x55<<0), /* Port A, Pin5 */ - EVSYS_CHMUX_PORTA_PIN6_gc = (0x56<<0), /* Port A, Pin6 */ - EVSYS_CHMUX_PORTA_PIN7_gc = (0x57<<0), /* Port A, Pin7 */ - EVSYS_CHMUX_PORTB_PIN0_gc = (0x58<<0), /* Port B, Pin0 */ - EVSYS_CHMUX_PORTB_PIN1_gc = (0x59<<0), /* Port B, Pin1 */ - EVSYS_CHMUX_PORTB_PIN2_gc = (0x5A<<0), /* Port B, Pin2 */ - EVSYS_CHMUX_PORTB_PIN3_gc = (0x5B<<0), /* Port B, Pin3 */ - EVSYS_CHMUX_PORTB_PIN4_gc = (0x5C<<0), /* Port B, Pin4 */ - EVSYS_CHMUX_PORTB_PIN5_gc = (0x5D<<0), /* Port B, Pin5 */ - EVSYS_CHMUX_PORTB_PIN6_gc = (0x5E<<0), /* Port B, Pin6 */ - EVSYS_CHMUX_PORTB_PIN7_gc = (0x5F<<0), /* Port B, Pin7 */ - EVSYS_CHMUX_PORTC_PIN0_gc = (0x60<<0), /* Port C, Pin0 */ - EVSYS_CHMUX_PORTC_PIN1_gc = (0x61<<0), /* Port C, Pin1 */ - EVSYS_CHMUX_PORTC_PIN2_gc = (0x62<<0), /* Port C, Pin2 */ - EVSYS_CHMUX_PORTC_PIN3_gc = (0x63<<0), /* Port C, Pin3 */ - EVSYS_CHMUX_PORTC_PIN4_gc = (0x64<<0), /* Port C, Pin4 */ - EVSYS_CHMUX_PORTC_PIN5_gc = (0x65<<0), /* Port C, Pin5 */ - EVSYS_CHMUX_PORTC_PIN6_gc = (0x66<<0), /* Port C, Pin6 */ - EVSYS_CHMUX_PORTC_PIN7_gc = (0x67<<0), /* Port C, Pin7 */ - EVSYS_CHMUX_PORTD_PIN0_gc = (0x68<<0), /* Port D, Pin0 */ - EVSYS_CHMUX_PORTD_PIN1_gc = (0x69<<0), /* Port D, Pin1 */ - EVSYS_CHMUX_PORTD_PIN2_gc = (0x6A<<0), /* Port D, Pin2 */ - EVSYS_CHMUX_PORTD_PIN3_gc = (0x6B<<0), /* Port D, Pin3 */ - EVSYS_CHMUX_PORTD_PIN4_gc = (0x6C<<0), /* Port D, Pin4 */ - EVSYS_CHMUX_PORTD_PIN5_gc = (0x6D<<0), /* Port D, Pin5 */ - EVSYS_CHMUX_PORTD_PIN6_gc = (0x6E<<0), /* Port D, Pin6 */ - EVSYS_CHMUX_PORTD_PIN7_gc = (0x6F<<0), /* Port D, Pin7 */ - EVSYS_CHMUX_PORTE_PIN0_gc = (0x70<<0), /* Port E, Pin0 */ - EVSYS_CHMUX_PORTE_PIN1_gc = (0x71<<0), /* Port E, Pin1 */ - EVSYS_CHMUX_PORTE_PIN2_gc = (0x72<<0), /* Port E, Pin2 */ - EVSYS_CHMUX_PORTE_PIN3_gc = (0x73<<0), /* Port E, Pin3 */ - EVSYS_CHMUX_PORTE_PIN4_gc = (0x74<<0), /* Port E, Pin4 */ - EVSYS_CHMUX_PORTE_PIN5_gc = (0x75<<0), /* Port E, Pin5 */ - EVSYS_CHMUX_PORTE_PIN6_gc = (0x76<<0), /* Port E, Pin6 */ - EVSYS_CHMUX_PORTE_PIN7_gc = (0x77<<0), /* Port E, Pin7 */ - EVSYS_CHMUX_PORTF_PIN0_gc = (0x78<<0), /* Port F, Pin0 */ - EVSYS_CHMUX_PORTF_PIN1_gc = (0x79<<0), /* Port F, Pin1 */ - EVSYS_CHMUX_PORTF_PIN2_gc = (0x7A<<0), /* Port F, Pin2 */ - EVSYS_CHMUX_PORTF_PIN3_gc = (0x7B<<0), /* Port F, Pin3 */ - EVSYS_CHMUX_PORTF_PIN4_gc = (0x7C<<0), /* Port F, Pin4 */ - EVSYS_CHMUX_PORTF_PIN5_gc = (0x7D<<0), /* Port F, Pin5 */ - EVSYS_CHMUX_PORTF_PIN6_gc = (0x7E<<0), /* Port F, Pin6 */ - EVSYS_CHMUX_PORTF_PIN7_gc = (0x7F<<0), /* Port F, Pin7 */ - EVSYS_CHMUX_PRESCALER_1_gc = (0x80<<0), /* Prescaler, divide by 1 */ - EVSYS_CHMUX_PRESCALER_2_gc = (0x81<<0), /* Prescaler, divide by 2 */ - EVSYS_CHMUX_PRESCALER_4_gc = (0x82<<0), /* Prescaler, divide by 4 */ - EVSYS_CHMUX_PRESCALER_8_gc = (0x83<<0), /* Prescaler, divide by 8 */ - EVSYS_CHMUX_PRESCALER_16_gc = (0x84<<0), /* Prescaler, divide by 16 */ - EVSYS_CHMUX_PRESCALER_32_gc = (0x85<<0), /* Prescaler, divide by 32 */ - EVSYS_CHMUX_PRESCALER_64_gc = (0x86<<0), /* Prescaler, divide by 64 */ - EVSYS_CHMUX_PRESCALER_128_gc = (0x87<<0), /* Prescaler, divide by 128 */ - EVSYS_CHMUX_PRESCALER_256_gc = (0x88<<0), /* Prescaler, divide by 256 */ - EVSYS_CHMUX_PRESCALER_512_gc = (0x89<<0), /* Prescaler, divide by 512 */ - EVSYS_CHMUX_PRESCALER_1024_gc = (0x8A<<0), /* Prescaler, divide by 1024 */ - EVSYS_CHMUX_PRESCALER_2048_gc = (0x8B<<0), /* Prescaler, divide by 2048 */ - EVSYS_CHMUX_PRESCALER_4096_gc = (0x8C<<0), /* Prescaler, divide by 4096 */ - EVSYS_CHMUX_PRESCALER_8192_gc = (0x8D<<0), /* Prescaler, divide by 8192 */ - EVSYS_CHMUX_PRESCALER_16384_gc = (0x8E<<0), /* Prescaler, divide by 16384 */ - EVSYS_CHMUX_PRESCALER_32768_gc = (0x8F<<0), /* Prescaler, divide by 32768 */ - EVSYS_CHMUX_TCC0_OVF_gc = (0xC0<<0), /* Timer/Counter C0 Overflow */ - EVSYS_CHMUX_TCC0_ERR_gc = (0xC1<<0), /* Timer/Counter C0 Error */ - EVSYS_CHMUX_TCC0_CCA_gc = (0xC4<<0), /* Timer/Counter C0 Compare or Capture A */ - EVSYS_CHMUX_TCC0_CCB_gc = (0xC5<<0), /* Timer/Counter C0 Compare or Capture B */ - EVSYS_CHMUX_TCC0_CCC_gc = (0xC6<<0), /* Timer/Counter C0 Compare or Capture C */ - EVSYS_CHMUX_TCC0_CCD_gc = (0xC7<<0), /* Timer/Counter C0 Compare or Capture D */ - EVSYS_CHMUX_TCC1_OVF_gc = (0xC8<<0), /* Timer/Counter C1 Overflow */ - EVSYS_CHMUX_TCC1_ERR_gc = (0xC9<<0), /* Timer/Counter C1 Error */ - EVSYS_CHMUX_TCC1_CCA_gc = (0xCC<<0), /* Timer/Counter C1 Compare or Capture A */ - EVSYS_CHMUX_TCC1_CCB_gc = (0xCD<<0), /* Timer/Counter C1 Compare or Capture B */ - EVSYS_CHMUX_TCD0_OVF_gc = (0xD0<<0), /* Timer/Counter D0 Overflow */ - EVSYS_CHMUX_TCD0_ERR_gc = (0xD1<<0), /* Timer/Counter D0 Error */ - EVSYS_CHMUX_TCD0_CCA_gc = (0xD4<<0), /* Timer/Counter D0 Compare or Capture A */ - EVSYS_CHMUX_TCD0_CCB_gc = (0xD5<<0), /* Timer/Counter D0 Compare or Capture B */ - EVSYS_CHMUX_TCD0_CCC_gc = (0xD6<<0), /* Timer/Counter D0 Compare or Capture C */ - EVSYS_CHMUX_TCD0_CCD_gc = (0xD7<<0), /* Timer/Counter D0 Compare or Capture D */ - EVSYS_CHMUX_TCD1_OVF_gc = (0xD8<<0), /* Timer/Counter D1 Overflow */ - EVSYS_CHMUX_TCD1_ERR_gc = (0xD9<<0), /* Timer/Counter D1 Error */ - EVSYS_CHMUX_TCD1_CCA_gc = (0xDC<<0), /* Timer/Counter D1 Compare or Capture A */ - EVSYS_CHMUX_TCD1_CCB_gc = (0xDD<<0), /* Timer/Counter D1 Compare or Capture B */ - EVSYS_CHMUX_TCE0_OVF_gc = (0xE0<<0), /* Timer/Counter E0 Overflow */ - EVSYS_CHMUX_TCE0_ERR_gc = (0xE1<<0), /* Timer/Counter E0 Error */ - EVSYS_CHMUX_TCE0_CCA_gc = (0xE4<<0), /* Timer/Counter E0 Compare or Capture A */ - EVSYS_CHMUX_TCE0_CCB_gc = (0xE5<<0), /* Timer/Counter E0 Compare or Capture B */ - EVSYS_CHMUX_TCE0_CCC_gc = (0xE6<<0), /* Timer/Counter E0 Compare or Capture C */ - EVSYS_CHMUX_TCE0_CCD_gc = (0xE7<<0), /* Timer/Counter E0 Compare or Capture D */ - EVSYS_CHMUX_TCE1_OVF_gc = (0xE8<<0), /* Timer/Counter E1 Overflow */ - EVSYS_CHMUX_TCE1_ERR_gc = (0xE9<<0), /* Timer/Counter E1 Error */ - EVSYS_CHMUX_TCE1_CCA_gc = (0xEC<<0), /* Timer/Counter E1 Compare or Capture A */ - EVSYS_CHMUX_TCE1_CCB_gc = (0xED<<0), /* Timer/Counter E1 Compare or Capture B */ - EVSYS_CHMUX_TCF0_OVF_gc = (0xF0<<0), /* Timer/Counter F0 Overflow */ - EVSYS_CHMUX_TCF0_ERR_gc = (0xF1<<0), /* Timer/Counter F0 Error */ - EVSYS_CHMUX_TCF0_CCA_gc = (0xF4<<0), /* Timer/Counter F0 Compare or Capture A */ - EVSYS_CHMUX_TCF0_CCB_gc = (0xF5<<0), /* Timer/Counter F0 Compare or Capture B */ - EVSYS_CHMUX_TCF0_CCC_gc = (0xF6<<0), /* Timer/Counter F0 Compare or Capture C */ - EVSYS_CHMUX_TCF0_CCD_gc = (0xF7<<0), /* Timer/Counter F0 Compare or Capture D */ - EVSYS_CHMUX_TCF1_OVF_gc = (0xF8<<0), /* Timer/Counter F1 Overflow */ - EVSYS_CHMUX_TCF1_ERR_gc = (0xF9<<0), /* Timer/Counter F1 Error */ - EVSYS_CHMUX_TCF1_CCA_gc = (0xFC<<0), /* Timer/Counter F1 Compare or Capture A */ - EVSYS_CHMUX_TCF1_CCB_gc = (0xFD<<0), /* Timer/Counter F1 Compare or Capture B */ -} EVSYS_CHMUX_t; - - -/* --------------------------------------------------------------------------- -NVM - Non Volatile Memory Controller --------------------------------------------------------------------------- -*/ - -/* Non-volatile Memory Controller */ -typedef struct NVM_struct -{ - register8_t ADDR0; /* Address Register 0 */ - register8_t ADDR1; /* Address Register 1 */ - register8_t ADDR2; /* Address Register 2 */ - register8_t reserved_0x03; - register8_t DATA0; /* Data Register 0 */ - register8_t DATA1; /* Data Register 1 */ - register8_t DATA2; /* Data Register 2 */ - register8_t reserved_0x07; - register8_t reserved_0x08; - register8_t reserved_0x09; - register8_t CMD; /* Command */ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t INTCTRL; /* Interrupt Control */ - register8_t reserved_0x0E; - register8_t STATUS; /* Status */ - register8_t LOCK_BITS; /* Lock Bits (Changed from LOCKBITS to avoid avr-libc collision) */ -} NVM_t; - -/* NVM Command */ -typedef enum NVM_CMD_enum -{ - NVM_CMD_NO_OPERATION_gc = (0x00<<0), /* Noop/Ordinary LPM */ - NVM_CMD_READ_USER_SIG_ROW_gc = (0x01<<0), /* Read user signature row */ - NVM_CMD_READ_CALIB_ROW_gc = (0x02<<0), /* Read calibration row */ - NVM_CMD_READ_EEPROM_gc = (0x06<<0), /* Read EEPROM */ - NVM_CMD_READ_FUSES_gc = (0x07<<0), /* Read fuse byte */ - NVM_CMD_WRITE_LOCK_BITS_gc = (0x08<<0), /* Write lock bits */ - NVM_CMD_ERASE_USER_SIG_ROW_gc = (0x18<<0), /* Erase user signature row */ - NVM_CMD_WRITE_USER_SIG_ROW_gc = (0x1A<<0), /* Write user signature row */ - NVM_CMD_ERASE_APP_gc = (0x20<<0), /* Erase Application Section */ - NVM_CMD_ERASE_APP_PAGE_gc = (0x22<<0), /* Erase Application Section page */ - NVM_CMD_LOAD_FLASH_BUFFER_gc = (0x23<<0), /* Load Flash page buffer */ - NVM_CMD_WRITE_APP_PAGE_gc = (0x24<<0), /* Write Application Section page */ - NVM_CMD_ERASE_WRITE_APP_PAGE_gc = (0x25<<0), /* Erase-and-write Application Section page */ - NVM_CMD_ERASE_FLASH_BUFFER_gc = (0x26<<0), /* Erase/flush Flash page buffer */ - NVM_CMD_ERASE_BOOT_PAGE_gc = (0x2A<<0), /* Erase Boot Section page */ - NVM_CMD_ERASE_FLASH_PAGE_gc = (0x2B<<0), /* Erase Flash Page */ - NVM_CMD_WRITE_BOOT_PAGE_gc = (0x2C<<0), /* Write Boot Section page */ - NVM_CMD_ERASE_WRITE_BOOT_PAGE_gc = (0x2D<<0), /* Erase-and-write Boot Section page */ - NVM_CMD_WRITE_FLASH_PAGE_gc = (0x2E<<0), /* Write Flash Page */ - NVM_CMD_ERASE_WRITE_FLASH_PAGE_gc = (0x2F<<0), /* Erase-and-write Flash Page */ - NVM_CMD_ERASE_EEPROM_gc = (0x30<<0), /* Erase EEPROM */ - NVM_CMD_ERASE_EEPROM_PAGE_gc = (0x32<<0), /* Erase EEPROM page */ - NVM_CMD_LOAD_EEPROM_BUFFER_gc = (0x33<<0), /* Load EEPROM page buffer */ - NVM_CMD_WRITE_EEPROM_PAGE_gc = (0x34<<0), /* Write EEPROM page */ - NVM_CMD_ERASE_WRITE_EEPROM_PAGE_gc = (0x35<<0), /* Erase-and-write EEPROM page */ - NVM_CMD_ERASE_EEPROM_BUFFER_gc = (0x36<<0), /* Erase/flush EEPROM page buffer */ - NVM_CMD_APP_CRC_gc = (0x38<<0), /* Application section CRC */ - NVM_CMD_BOOT_CRC_gc = (0x39<<0), /* Boot Section CRC */ - NVM_CMD_FLASH_RANGE_CRC_gc = (0x3A<<0), /* Flash Range CRC */ - NVM_CMD_CHIP_ERASE_gc = (0x40<<0), /* Erase Chip */ - NVM_CMD_READ_NVM_gc = (0x43<<0), /* Read NVM */ - NVM_CMD_WRITE_FUSE_gc = (0x4C<<0), /* Write Fuse byte */ - NVM_CMD_ERASE_BOOT_gc = (0x68<<0), /* Erase Boot Section */ - NVM_CMD_FLASH_CRC_gc = (0x78<<0), /* Flash CRC */ -} NVM_CMD_t; - -/* SPM ready interrupt level */ -typedef enum NVM_SPMLVL_enum -{ - NVM_SPMLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ - NVM_SPMLVL_LO_gc = (0x01<<2), /* Low level */ - NVM_SPMLVL_MED_gc = (0x02<<2), /* Medium level */ - NVM_SPMLVL_HI_gc = (0x03<<2), /* High level */ -} NVM_SPMLVL_t; - -/* EEPROM ready interrupt level */ -typedef enum NVM_EELVL_enum -{ - NVM_EELVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ - NVM_EELVL_LO_gc = (0x01<<0), /* Low level */ - NVM_EELVL_MED_gc = (0x02<<0), /* Medium level */ - NVM_EELVL_HI_gc = (0x03<<0), /* High level */ -} NVM_EELVL_t; - -/* Boot lock bits - boot setcion */ -typedef enum NVM_BLBB_enum -{ - NVM_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ - NVM_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ - NVM_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ - NVM_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ -} NVM_BLBB_t; - -/* Boot lock bits - application section */ -typedef enum NVM_BLBA_enum -{ - NVM_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ - NVM_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ - NVM_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ - NVM_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ -} NVM_BLBA_t; - -/* Boot lock bits - application table section */ -typedef enum NVM_BLBAT_enum -{ - NVM_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ - NVM_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ - NVM_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ - NVM_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ -} NVM_BLBAT_t; - -/* Lock bits */ -typedef enum NVM_LB_enum -{ - NVM_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ - NVM_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ - NVM_LB_NOLOCK_gc = (0x03<<0), /* No locks */ -} NVM_LB_t; - - -/* --------------------------------------------------------------------------- -ADC - Analog/Digital Converter --------------------------------------------------------------------------- -*/ - -/* ADC Channel */ -typedef struct ADC_CH_struct -{ - register8_t CTRL; /* Control Register */ - register8_t MUXCTRL; /* MUX Control */ - register8_t INTCTRL; /* Channel Interrupt Control Register */ - register8_t INTFLAGS; /* Interrupt Flags */ - _WORDREGISTER(RES); /* Channel Result */ - register8_t SCAN; /* Input Channel Scan */ - register8_t reserved_0x07; -} ADC_CH_t; - - -/* Analog-to-Digital Converter */ -typedef struct ADC_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t REFCTRL; /* Reference Control */ - register8_t EVCTRL; /* Event Control */ - register8_t PRESCALER; /* Clock Prescaler */ - register8_t reserved_0x05; - register8_t INTFLAGS; /* Interrupt Flags */ - register8_t TEMP; /* Temporary Register */ - register8_t reserved_0x08; - register8_t reserved_0x09; - register8_t reserved_0x0A; - register8_t reserved_0x0B; - _WORDREGISTER(CAL); /* Calibration Value */ - register8_t reserved_0x0E; - register8_t reserved_0x0F; - _WORDREGISTER(CH0RES); /* Channel 0 Result */ - _WORDREGISTER(CH1RES); /* Channel 1 Result */ - _WORDREGISTER(CH2RES); /* Channel 2 Result */ - _WORDREGISTER(CH3RES); /* Channel 3 Result */ - _WORDREGISTER(CMP); /* Compare Value */ - register8_t reserved_0x1A; - register8_t reserved_0x1B; - register8_t reserved_0x1C; - register8_t reserved_0x1D; - register8_t reserved_0x1E; - register8_t reserved_0x1F; - ADC_CH_t CH0; /* ADC Channel 0 */ - ADC_CH_t CH1; /* ADC Channel 1 */ - ADC_CH_t CH2; /* ADC Channel 2 */ - ADC_CH_t CH3; /* ADC Channel 3 */ -} ADC_t; - -/* Positive input multiplexer selection */ -typedef enum ADC_CH_MUXPOS_enum -{ - ADC_CH_MUXPOS_PIN0_gc = (0x00<<3), /* Input pin 0 */ - ADC_CH_MUXPOS_PIN1_gc = (0x01<<3), /* Input pin 1 */ - ADC_CH_MUXPOS_PIN2_gc = (0x02<<3), /* Input pin 2 */ - ADC_CH_MUXPOS_PIN3_gc = (0x03<<3), /* Input pin 3 */ - ADC_CH_MUXPOS_PIN4_gc = (0x04<<3), /* Input pin 4 */ - ADC_CH_MUXPOS_PIN5_gc = (0x05<<3), /* Input pin 5 */ - ADC_CH_MUXPOS_PIN6_gc = (0x06<<3), /* Input pin 6 */ - ADC_CH_MUXPOS_PIN7_gc = (0x07<<3), /* Input pin 7 */ - ADC_CH_MUXPOS_PIN8_gc = (0x08<<3), /* Input pin 8 */ - ADC_CH_MUXPOS_PIN9_gc = (0x09<<3), /* Input pin 9 */ - ADC_CH_MUXPOS_PIN10_gc = (0x0A<<3), /* Input pin 10 */ - ADC_CH_MUXPOS_PIN11_gc = (0x0B<<3), /* Input pin 11 */ - ADC_CH_MUXPOS_PIN12_gc = (0x0C<<3), /* Input pin 12 */ - ADC_CH_MUXPOS_PIN13_gc = (0x0D<<3), /* Input pin 13 */ - ADC_CH_MUXPOS_PIN14_gc = (0x0E<<3), /* Input pin 14 */ - ADC_CH_MUXPOS_PIN15_gc = (0x0F<<3), /* Input pin 15 */ -} ADC_CH_MUXPOS_t; - -/* Internal input multiplexer selections */ -typedef enum ADC_CH_MUXINT_enum -{ - ADC_CH_MUXINT_TEMP_gc = (0x00<<3), /* Temperature Reference */ - ADC_CH_MUXINT_BANDGAP_gc = (0x01<<3), /* Bandgap Reference */ - ADC_CH_MUXINT_SCALEDVCC_gc = (0x02<<3), /* 1/10 scaled VCC */ - ADC_CH_MUXINT_DAC_gc = (0x03<<3), /* DAC output */ -} ADC_CH_MUXINT_t; - -/* Negative input multiplexer selection */ -typedef enum ADC_CH_MUXNEG_enum -{ - ADC_CH_MUXNEG_PIN0_gc = (0x00<<0), /* Input pin 0 (Input Mode = 2) */ - ADC_CH_MUXNEG_PIN1_gc = (0x01<<0), /* Input pin 1 (Input Mode = 2) */ - ADC_CH_MUXNEG_PIN2_gc = (0x02<<0), /* Input pin 2 (Input Mode = 2) */ - ADC_CH_MUXNEG_PIN3_gc = (0x03<<0), /* Input pin 3 (Input Mode = 2) */ - ADC_CH_MUXNEG_PIN4_gc = (0x00<<0), /* Input pin 4 (Input Mode = 3) */ - ADC_CH_MUXNEG_PIN5_gc = (0x01<<0), /* Input pin 5 (Input Mode = 3) */ - ADC_CH_MUXNEG_PIN6_gc = (0x02<<0), /* Input pin 6 (Input Mode = 3) */ - ADC_CH_MUXNEG_PIN7_gc = (0x03<<0), /* Input pin 7 (Input Mode = 3) */ - ADC_CH_MUXNEG_GND_MODE3_gc = (0x05<<0), /* PAD Ground (Input Mode = 2) */ - ADC_CH_MUXNEG_INTGND_MODE3_gc = (0x07<<0), /* Internal Ground (Input Mode = 2) */ - ADC_CH_MUXNEG_INTGND_MODE4_gc = (0x04<<0), /* Internal Ground (Input Mode = 3) */ - ADC_CH_MUXNEG_GND_MODE4_gc = (0x07<<0), /* PAD Ground (Input Mode = 3) */ -} ADC_CH_MUXNEG_t; - -/* Input mode */ -typedef enum ADC_CH_INPUTMODE_enum -{ - ADC_CH_INPUTMODE_INTERNAL_gc = (0x00<<0), /* Internal inputs, no gain */ - ADC_CH_INPUTMODE_SINGLEENDED_gc = (0x01<<0), /* Single-ended input, no gain */ - ADC_CH_INPUTMODE_DIFF_gc = (0x02<<0), /* Differential input, no gain */ - ADC_CH_INPUTMODE_DIFFWGAIN_gc = (0x03<<0), /* Differential input, with gain */ -} ADC_CH_INPUTMODE_t; - -/* Gain factor */ -typedef enum ADC_CH_GAIN_enum -{ - ADC_CH_GAIN_1X_gc = (0x00<<2), /* 1x gain */ - ADC_CH_GAIN_2X_gc = (0x01<<2), /* 2x gain */ - ADC_CH_GAIN_4X_gc = (0x02<<2), /* 4x gain */ - ADC_CH_GAIN_8X_gc = (0x03<<2), /* 8x gain */ - ADC_CH_GAIN_16X_gc = (0x04<<2), /* 16x gain */ - ADC_CH_GAIN_32X_gc = (0x05<<2), /* 32x gain */ - ADC_CH_GAIN_64X_gc = (0x06<<2), /* 64x gain */ - ADC_CH_GAIN_DIV2_gc = (0x07<<2), /* x/2 gain */ -} ADC_CH_GAIN_t; - -/* Conversion result resolution */ -typedef enum ADC_RESOLUTION_enum -{ - ADC_RESOLUTION_12BIT_gc = (0x00<<1), /* 12-bit right-adjusted result */ - ADC_RESOLUTION_8BIT_gc = (0x02<<1), /* 8-bit right-adjusted result */ - ADC_RESOLUTION_LEFT12BIT_gc = (0x03<<1), /* 12-bit left-adjusted result */ -} ADC_RESOLUTION_t; - -/* Current Limitation Mode */ -typedef enum ADC_CURRLIMIT_enum -{ - ADC_CURRLIMIT_NO_gc = (0x00<<5), /* No limit */ - ADC_CURRLIMIT_LOW_gc = (0x01<<5), /* Low current limit, max. sampling rate 1.5MSPS */ - ADC_CURRLIMIT_MED_gc = (0x02<<5), /* Medium current limit, max. sampling rate 1MSPS */ - ADC_CURRLIMIT_HIGH_gc = (0x03<<5), /* High current limit, max. sampling rate 0.5MSPS */ -} ADC_CURRLIMIT_t; - -/* Voltage reference selection */ -typedef enum ADC_REFSEL_enum -{ - ADC_REFSEL_INT1V_gc = (0x00<<4), /* Internal 1V */ - ADC_REFSEL_INTVCC_gc = (0x01<<4), /* Internal VCC / 1.6 */ - ADC_REFSEL_AREFA_gc = (0x02<<4), /* External reference on PORT A */ - ADC_REFSEL_AREFB_gc = (0x03<<4), /* External reference on PORT B */ - ADC_REFSEL_INTVCC2_gc = (0x04<<4), /* Internal VCC / 2 */ -} ADC_REFSEL_t; - -/* Channel sweep selection */ -typedef enum ADC_SWEEP_enum -{ - ADC_SWEEP_0_gc = (0x00<<6), /* ADC Channel 0 */ - ADC_SWEEP_01_gc = (0x01<<6), /* ADC Channel 0,1 */ - ADC_SWEEP_012_gc = (0x02<<6), /* ADC Channel 0,1,2 */ - ADC_SWEEP_0123_gc = (0x03<<6), /* ADC Channel 0,1,2,3 */ -} ADC_SWEEP_t; - -/* Event channel input selection */ -typedef enum ADC_EVSEL_enum -{ - ADC_EVSEL_0123_gc = (0x00<<3), /* Event Channel 0,1,2,3 */ - ADC_EVSEL_1234_gc = (0x01<<3), /* Event Channel 1,2,3,4 */ - ADC_EVSEL_2345_gc = (0x02<<3), /* Event Channel 2,3,4,5 */ - ADC_EVSEL_3456_gc = (0x03<<3), /* Event Channel 3,4,5,6 */ - ADC_EVSEL_4567_gc = (0x04<<3), /* Event Channel 4,5,6,7 */ - ADC_EVSEL_567_gc = (0x05<<3), /* Event Channel 5,6,7 */ - ADC_EVSEL_67_gc = (0x06<<3), /* Event Channel 6,7 */ - ADC_EVSEL_7_gc = (0x07<<3), /* Event Channel 7 */ -} ADC_EVSEL_t; - -/* Event action selection */ -typedef enum ADC_EVACT_enum -{ - ADC_EVACT_NONE_gc = (0x00<<0), /* No event action */ - ADC_EVACT_CH0_gc = (0x01<<0), /* First event triggers channel 0 */ - ADC_EVACT_CH01_gc = (0x02<<0), /* First two events trigger channel 0,1 */ - ADC_EVACT_CH012_gc = (0x03<<0), /* First three events trigger channel 0,1,2 */ - ADC_EVACT_CH0123_gc = (0x04<<0), /* Events trigger channel 0,1,2,3 */ - ADC_EVACT_SWEEP_gc = (0x05<<0), /* First event triggers sweep */ - ADC_EVACT_SYNCSWEEP_gc = (0x06<<0), /* The ADC is flushed and restarted for accurate timing */ -} ADC_EVACT_t; - -/* Interupt mode */ -typedef enum ADC_CH_INTMODE_enum -{ - ADC_CH_INTMODE_COMPLETE_gc = (0x00<<2), /* Interrupt on conversion complete */ - ADC_CH_INTMODE_BELOW_gc = (0x01<<2), /* Interrupt on result below compare value */ - ADC_CH_INTMODE_ABOVE_gc = (0x03<<2), /* Interrupt on result above compare value */ -} ADC_CH_INTMODE_t; - -/* Interrupt level */ -typedef enum ADC_CH_INTLVL_enum -{ - ADC_CH_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ - ADC_CH_INTLVL_LO_gc = (0x01<<0), /* Low level */ - ADC_CH_INTLVL_MED_gc = (0x02<<0), /* Medium level */ - ADC_CH_INTLVL_HI_gc = (0x03<<0), /* High level */ -} ADC_CH_INTLVL_t; - -/* DMA request selection */ -typedef enum ADC_DMASEL_enum -{ - ADC_DMASEL_OFF_gc = (0x00<<6), /* Combined DMA request OFF */ - ADC_DMASEL_CH01_gc = (0x01<<6), /* ADC Channel 0 or 1 */ - ADC_DMASEL_CH012_gc = (0x02<<6), /* ADC Channel 0 or 1 or 2 */ - ADC_DMASEL_CH0123_gc = (0x03<<6), /* ADC Channel 0 or 1 or 2 or 3 */ -} ADC_DMASEL_t; - -/* Clock prescaler */ -typedef enum ADC_PRESCALER_enum -{ - ADC_PRESCALER_DIV4_gc = (0x00<<0), /* Divide clock by 4 */ - ADC_PRESCALER_DIV8_gc = (0x01<<0), /* Divide clock by 8 */ - ADC_PRESCALER_DIV16_gc = (0x02<<0), /* Divide clock by 16 */ - ADC_PRESCALER_DIV32_gc = (0x03<<0), /* Divide clock by 32 */ - ADC_PRESCALER_DIV64_gc = (0x04<<0), /* Divide clock by 64 */ - ADC_PRESCALER_DIV128_gc = (0x05<<0), /* Divide clock by 128 */ - ADC_PRESCALER_DIV256_gc = (0x06<<0), /* Divide clock by 256 */ - ADC_PRESCALER_DIV512_gc = (0x07<<0), /* Divide clock by 512 */ -} ADC_PRESCALER_t; - - -/* --------------------------------------------------------------------------- -DAC - Digital/Analog Converter --------------------------------------------------------------------------- -*/ - -/* Digital-to-Analog Converter */ -typedef struct DAC_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t CTRLC; /* Control Register C */ - register8_t EVCTRL; /* Event Input Control */ - register8_t reserved_0x04; - register8_t STATUS; /* Status */ - register8_t reserved_0x06; - register8_t reserved_0x07; - register8_t CH0GAINCAL; /* Gain Calibration */ - register8_t CH0OFFSETCAL; /* Offset Calibration */ - register8_t CH1GAINCAL; /* Gain Calibration */ - register8_t CH1OFFSETCAL; /* Offset Calibration */ - register8_t reserved_0x0C; - register8_t reserved_0x0D; - register8_t reserved_0x0E; - register8_t reserved_0x0F; - register8_t reserved_0x10; - register8_t reserved_0x11; - register8_t reserved_0x12; - register8_t reserved_0x13; - register8_t reserved_0x14; - register8_t reserved_0x15; - register8_t reserved_0x16; - register8_t reserved_0x17; - _WORDREGISTER(CH0DATA); /* Channel 0 Data */ - _WORDREGISTER(CH1DATA); /* Channel 1 Data */ -} DAC_t; - -/* Output channel selection */ -typedef enum DAC_CHSEL_enum -{ - DAC_CHSEL_SINGLE_gc = (0x00<<5), /* Single channel operation (Channel 0 only) */ - DAC_CHSEL_SINGLE1_gc = (0x01<<5), /* Single channel operation (Channel 1 only) */ - DAC_CHSEL_DUAL_gc = (0x02<<5), /* Dual channel operation (Channel 0 and channel 1) */ -} DAC_CHSEL_t; - -/* Reference voltage selection */ -typedef enum DAC_REFSEL_enum -{ - DAC_REFSEL_INT1V_gc = (0x00<<3), /* Internal 1V */ - DAC_REFSEL_AVCC_gc = (0x01<<3), /* Analog supply voltage */ - DAC_REFSEL_AREFA_gc = (0x02<<3), /* External reference on AREF on PORTA */ - DAC_REFSEL_AREFB_gc = (0x03<<3), /* External reference on AREF on PORTB */ -} DAC_REFSEL_t; - -/* Event channel selection */ -typedef enum DAC_EVSEL_enum -{ - DAC_EVSEL_0_gc = (0x00<<0), /* Event Channel 0 */ - DAC_EVSEL_1_gc = (0x01<<0), /* Event Channel 1 */ - DAC_EVSEL_2_gc = (0x02<<0), /* Event Channel 2 */ - DAC_EVSEL_3_gc = (0x03<<0), /* Event Channel 3 */ - DAC_EVSEL_4_gc = (0x04<<0), /* Event Channel 4 */ - DAC_EVSEL_5_gc = (0x05<<0), /* Event Channel 5 */ - DAC_EVSEL_6_gc = (0x06<<0), /* Event Channel 6 */ - DAC_EVSEL_7_gc = (0x07<<0), /* Event Channel 7 */ -} DAC_EVSEL_t; - - -/* --------------------------------------------------------------------------- -AC - Analog Comparator --------------------------------------------------------------------------- -*/ - -/* Analog Comparator */ -typedef struct AC_struct -{ - register8_t AC0CTRL; /* Analog Comparator 0 Control */ - register8_t AC1CTRL; /* Analog Comparator 1 Control */ - register8_t AC0MUXCTRL; /* Analog Comparator 0 MUX Control */ - register8_t AC1MUXCTRL; /* Analog Comparator 1 MUX Control */ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t WINCTRL; /* Window Mode Control */ - register8_t STATUS; /* Status */ -} AC_t; - -/* Interrupt mode */ -typedef enum AC_INTMODE_enum -{ - AC_INTMODE_BOTHEDGES_gc = (0x00<<6), /* Interrupt on both edges */ - AC_INTMODE_FALLING_gc = (0x02<<6), /* Interrupt on falling edge */ - AC_INTMODE_RISING_gc = (0x03<<6), /* Interrupt on rising edge */ -} AC_INTMODE_t; - -/* Interrupt level */ -typedef enum AC_INTLVL_enum -{ - AC_INTLVL_OFF_gc = (0x00<<4), /* Interrupt disabled */ - AC_INTLVL_LO_gc = (0x01<<4), /* Low level */ - AC_INTLVL_MED_gc = (0x02<<4), /* Medium level */ - AC_INTLVL_HI_gc = (0x03<<4), /* High level */ -} AC_INTLVL_t; - -/* Hysteresis mode selection */ -typedef enum AC_HYSMODE_enum -{ - AC_HYSMODE_NO_gc = (0x00<<1), /* No hysteresis */ - AC_HYSMODE_SMALL_gc = (0x01<<1), /* Small hysteresis */ - AC_HYSMODE_LARGE_gc = (0x02<<1), /* Large hysteresis */ -} AC_HYSMODE_t; - -/* Positive input multiplexer selection */ -typedef enum AC_MUXPOS_enum -{ - AC_MUXPOS_PIN0_gc = (0x00<<3), /* Pin 0 */ - AC_MUXPOS_PIN1_gc = (0x01<<3), /* Pin 1 */ - AC_MUXPOS_PIN2_gc = (0x02<<3), /* Pin 2 */ - AC_MUXPOS_PIN3_gc = (0x03<<3), /* Pin 3 */ - AC_MUXPOS_PIN4_gc = (0x04<<3), /* Pin 4 */ - AC_MUXPOS_PIN5_gc = (0x05<<3), /* Pin 5 */ - AC_MUXPOS_PIN6_gc = (0x06<<3), /* Pin 6 */ - AC_MUXPOS_DAC_gc = (0x07<<3), /* DAC output */ -} AC_MUXPOS_t; - -/* Negative input multiplexer selection */ -typedef enum AC_MUXNEG_enum -{ - AC_MUXNEG_PIN0_gc = (0x00<<0), /* Pin 0 */ - AC_MUXNEG_PIN1_gc = (0x01<<0), /* Pin 1 */ - AC_MUXNEG_PIN3_gc = (0x02<<0), /* Pin 3 */ - AC_MUXNEG_PIN5_gc = (0x03<<0), /* Pin 5 */ - AC_MUXNEG_PIN7_gc = (0x04<<0), /* Pin 7 */ - AC_MUXNEG_DAC_gc = (0x05<<0), /* DAC output */ - AC_MUXNEG_BANDGAP_gc = (0x06<<0), /* Bandgap Reference */ - AC_MUXNEG_SCALER_gc = (0x07<<0), /* Internal voltage scaler */ -} AC_MUXNEG_t; - -/* Windows interrupt mode */ -typedef enum AC_WINTMODE_enum -{ - AC_WINTMODE_ABOVE_gc = (0x00<<2), /* Interrupt on above window */ - AC_WINTMODE_INSIDE_gc = (0x01<<2), /* Interrupt on inside window */ - AC_WINTMODE_BELOW_gc = (0x02<<2), /* Interrupt on below window */ - AC_WINTMODE_OUTSIDE_gc = (0x03<<2), /* Interrupt on outside window */ -} AC_WINTMODE_t; - -/* Window interrupt level */ -typedef enum AC_WINTLVL_enum -{ - AC_WINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ - AC_WINTLVL_LO_gc = (0x01<<0), /* Low priority */ - AC_WINTLVL_MED_gc = (0x02<<0), /* Medium priority */ - AC_WINTLVL_HI_gc = (0x03<<0), /* High priority */ -} AC_WINTLVL_t; - -/* Window mode state */ -typedef enum AC_WSTATE_enum -{ - AC_WSTATE_ABOVE_gc = (0x00<<6), /* Signal above window */ - AC_WSTATE_INSIDE_gc = (0x01<<6), /* Signal inside window */ - AC_WSTATE_BELOW_gc = (0x02<<6), /* Signal below window */ -} AC_WSTATE_t; - - -/* --------------------------------------------------------------------------- -RTC - Real-Time Counter --------------------------------------------------------------------------- -*/ - -/* Real-Time Counter */ -typedef struct RTC_struct -{ - register8_t CTRL; /* Control Register */ - register8_t STATUS; /* Status Register */ - register8_t INTCTRL; /* Interrupt Control Register */ - register8_t INTFLAGS; /* Interrupt Flags */ - register8_t TEMP; /* Temporary register */ - register8_t reserved_0x05; - register8_t reserved_0x06; - register8_t reserved_0x07; - _WORDREGISTER(CNT); /* Count Register */ - _WORDREGISTER(PER); /* Period Register */ - _WORDREGISTER(COMP); /* Compare Register */ -} RTC_t; - -/* Prescaler Factor */ -typedef enum RTC_PRESCALER_enum -{ - RTC_PRESCALER_OFF_gc = (0x00<<0), /* RTC Off */ - RTC_PRESCALER_DIV1_gc = (0x01<<0), /* RTC Clock */ - RTC_PRESCALER_DIV2_gc = (0x02<<0), /* RTC Clock / 2 */ - RTC_PRESCALER_DIV8_gc = (0x03<<0), /* RTC Clock / 8 */ - RTC_PRESCALER_DIV16_gc = (0x04<<0), /* RTC Clock / 16 */ - RTC_PRESCALER_DIV64_gc = (0x05<<0), /* RTC Clock / 64 */ - RTC_PRESCALER_DIV256_gc = (0x06<<0), /* RTC Clock / 256 */ - RTC_PRESCALER_DIV1024_gc = (0x07<<0), /* RTC Clock / 1024 */ -} RTC_PRESCALER_t; - -/* Compare Interrupt level */ -typedef enum RTC_COMPINTLVL_enum -{ - RTC_COMPINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ - RTC_COMPINTLVL_LO_gc = (0x01<<2), /* Low Level */ - RTC_COMPINTLVL_MED_gc = (0x02<<2), /* Medium Level */ - RTC_COMPINTLVL_HI_gc = (0x03<<2), /* High Level */ -} RTC_COMPINTLVL_t; - -/* Overflow Interrupt level */ -typedef enum RTC_OVFINTLVL_enum -{ - RTC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - RTC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ - RTC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ - RTC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ -} RTC_OVFINTLVL_t; - - -/* --------------------------------------------------------------------------- -TWI - Two-Wire Interface --------------------------------------------------------------------------- -*/ - -/* */ -typedef struct TWI_MASTER_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t CTRLC; /* Control Register C */ - register8_t STATUS; /* Status Register */ - register8_t BAUD; /* Baurd Rate Control Register */ - register8_t ADDR; /* Address Register */ - register8_t DATA; /* Data Register */ -} TWI_MASTER_t; - - -/* */ -typedef struct TWI_SLAVE_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t STATUS; /* Status Register */ - register8_t ADDR; /* Address Register */ - register8_t DATA; /* Data Register */ - register8_t ADDRMASK; /* Address Mask Register */ -} TWI_SLAVE_t; - - -/* Two-Wire Interface */ -typedef struct TWI_struct -{ - register8_t CTRL; /* TWI Common Control Register */ - TWI_MASTER_t MASTER; /* TWI master module */ - TWI_SLAVE_t SLAVE; /* TWI slave module */ -} TWI_t; - -/* SDA Hold Time */ -typedef enum TWI_SDAHOLD_enum -{ - TWI_SDAHOLD_OFF_gc = (0x00<<1), /* SDA Hold Time off */ - TWI_SDAHOLD_50NS_gc = (0x01<<1), /* SDA Hold Time 50 ns */ - TWI_SDAHOLD_300NS_gc = (0x02<<1), /* SDA Hold Time 300 ns */ - TWI_SDAHOLD_400NS_gc = (0x03<<1), /* SDA Hold Time 400 ns */ -} TWI_SDAHOLD_t; - -/* Master Interrupt Level */ -typedef enum TWI_MASTER_INTLVL_enum -{ - TWI_MASTER_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ - TWI_MASTER_INTLVL_LO_gc = (0x01<<6), /* Low Level */ - TWI_MASTER_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ - TWI_MASTER_INTLVL_HI_gc = (0x03<<6), /* High Level */ -} TWI_MASTER_INTLVL_t; - -/* Inactive Timeout */ -typedef enum TWI_MASTER_TIMEOUT_enum -{ - TWI_MASTER_TIMEOUT_DISABLED_gc = (0x00<<2), /* Bus Timeout Disabled */ - TWI_MASTER_TIMEOUT_50US_gc = (0x01<<2), /* 50 Microseconds */ - TWI_MASTER_TIMEOUT_100US_gc = (0x02<<2), /* 100 Microseconds */ - TWI_MASTER_TIMEOUT_200US_gc = (0x03<<2), /* 200 Microseconds */ -} TWI_MASTER_TIMEOUT_t; - -/* Master Command */ -typedef enum TWI_MASTER_CMD_enum -{ - TWI_MASTER_CMD_NOACT_gc = (0x00<<0), /* No Action */ - TWI_MASTER_CMD_REPSTART_gc = (0x01<<0), /* Issue Repeated Start Condition */ - TWI_MASTER_CMD_RECVTRANS_gc = (0x02<<0), /* Receive or Transmit Data */ - TWI_MASTER_CMD_STOP_gc = (0x03<<0), /* Issue Stop Condition */ -} TWI_MASTER_CMD_t; - -/* Master Bus State */ -typedef enum TWI_MASTER_BUSSTATE_enum -{ - TWI_MASTER_BUSSTATE_UNKNOWN_gc = (0x00<<0), /* Unknown Bus State */ - TWI_MASTER_BUSSTATE_IDLE_gc = (0x01<<0), /* Bus is Idle */ - TWI_MASTER_BUSSTATE_OWNER_gc = (0x02<<0), /* This Module Controls The Bus */ - TWI_MASTER_BUSSTATE_BUSY_gc = (0x03<<0), /* The Bus is Busy */ -} TWI_MASTER_BUSSTATE_t; - -/* Slave Interrupt Level */ -typedef enum TWI_SLAVE_INTLVL_enum -{ - TWI_SLAVE_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ - TWI_SLAVE_INTLVL_LO_gc = (0x01<<6), /* Low Level */ - TWI_SLAVE_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ - TWI_SLAVE_INTLVL_HI_gc = (0x03<<6), /* High Level */ -} TWI_SLAVE_INTLVL_t; - -/* Slave Command */ -typedef enum TWI_SLAVE_CMD_enum -{ - TWI_SLAVE_CMD_NOACT_gc = (0x00<<0), /* No Action */ - TWI_SLAVE_CMD_COMPTRANS_gc = (0x02<<0), /* Used To Complete a Transaction */ - TWI_SLAVE_CMD_RESPONSE_gc = (0x03<<0), /* Used in Response to Address/Data Interrupt */ -} TWI_SLAVE_CMD_t; - - -/* --------------------------------------------------------------------------- -USB - USB --------------------------------------------------------------------------- -*/ - -/* USB Endpoint */ -typedef struct USB_EP_struct -{ - register8_t STATUS; /* Endpoint Status */ - register8_t CTRL; /* Endpoint Control */ - _WORDREGISTER(CNT); /* USB Endpoint Counter */ - _WORDREGISTER(DATAPTR); /* Data Pointer */ - _WORDREGISTER(AUXDATA); /* Auxiliary Data */ -} USB_EP_t; - - -/* Universal Serial Bus */ -typedef struct USB_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t STATUS; /* Status Register */ - register8_t ADDR; /* Address Register */ - register8_t FIFOWP; /* FIFO Write Pointer Register */ - register8_t FIFORP; /* FIFO Read Pointer Register */ - _WORDREGISTER(EPPTR); /* Endpoint Configuration Table Pointer */ - register8_t INTCTRLA; /* Interrupt Control Register A */ - register8_t INTCTRLB; /* Interrupt Control Register B */ - register8_t INTFLAGSACLR; /* Clear Interrupt Flag Register A */ - register8_t INTFLAGSASET; /* Set Interrupt Flag Register A */ - register8_t INTFLAGSBCLR; /* Clear Interrupt Flag Register B */ - register8_t INTFLAGSBSET; /* Set Interrupt Flag Register B */ - register8_t reserved_0x0E; - register8_t reserved_0x0F; - register8_t reserved_0x10; - register8_t reserved_0x11; - register8_t reserved_0x12; - register8_t reserved_0x13; - register8_t reserved_0x14; - register8_t reserved_0x15; - register8_t reserved_0x16; - register8_t reserved_0x17; - register8_t reserved_0x18; - register8_t reserved_0x19; - register8_t reserved_0x1A; - register8_t reserved_0x1B; - register8_t reserved_0x1C; - register8_t reserved_0x1D; - register8_t reserved_0x1E; - register8_t reserved_0x1F; - register8_t reserved_0x20; - register8_t reserved_0x21; - register8_t reserved_0x22; - register8_t reserved_0x23; - register8_t reserved_0x24; - register8_t reserved_0x25; - register8_t reserved_0x26; - register8_t reserved_0x27; - register8_t reserved_0x28; - register8_t reserved_0x29; - register8_t reserved_0x2A; - register8_t reserved_0x2B; - register8_t reserved_0x2C; - register8_t reserved_0x2D; - register8_t reserved_0x2E; - register8_t reserved_0x2F; - register8_t reserved_0x30; - register8_t reserved_0x31; - register8_t reserved_0x32; - register8_t reserved_0x33; - register8_t reserved_0x34; - register8_t reserved_0x35; - register8_t reserved_0x36; - register8_t reserved_0x37; - register8_t reserved_0x38; - register8_t reserved_0x39; - register8_t CAL0; /* Calibration Byte 0 */ - register8_t CAL1; /* Calibration Byte 1 */ -} USB_t; - - -/* USB Endpoint Table */ -typedef struct USB_EP_TABLE_struct -{ - USB_EP_t EP0OUT; /* Endpoint 0 */ - USB_EP_t EP0IN; /* Endpoint 0 */ - USB_EP_t EP1OUT; /* Endpoint 1 */ - USB_EP_t EP1IN; /* Endpoint 1 */ - USB_EP_t EP2OUT; /* Endpoint 2 */ - USB_EP_t EP2IN; /* Endpoint 2 */ - USB_EP_t EP3OUT; /* Endpoint 3 */ - USB_EP_t EP3IN; /* Endpoint 3 */ - USB_EP_t EP4OUT; /* Endpoint 4 */ - USB_EP_t EP4IN; /* Endpoint 4 */ - USB_EP_t EP5OUT; /* Endpoint 5 */ - USB_EP_t EP5IN; /* Endpoint 5 */ - USB_EP_t EP6OUT; /* Endpoint 6 */ - USB_EP_t EP6IN; /* Endpoint 6 */ - USB_EP_t EP7OUT; /* Endpoint 7 */ - USB_EP_t EP7IN; /* Endpoint 7 */ - USB_EP_t EP8OUT; /* Endpoint 8 */ - USB_EP_t EP8IN; /* Endpoint 8 */ - USB_EP_t EP9OUT; /* Endpoint 9 */ - USB_EP_t EP9IN; /* Endpoint 9 */ - USB_EP_t EP10OUT; /* Endpoint 10 */ - USB_EP_t EP10IN; /* Endpoint 10 */ - USB_EP_t EP11OUT; /* Endpoint 11 */ - USB_EP_t EP11IN; /* Endpoint 11 */ - USB_EP_t EP12OUT; /* Endpoint 12 */ - USB_EP_t EP12IN; /* Endpoint 12 */ - USB_EP_t EP13OUT; /* Endpoint 13 */ - USB_EP_t EP13IN; /* Endpoint 13 */ - USB_EP_t EP14OUT; /* Endpoint 14 */ - USB_EP_t EP14IN; /* Endpoint 14 */ - USB_EP_t EP15OUT; /* Endpoint 15 */ - USB_EP_t EP15IN; /* Endpoint 15 */ - register8_t reserved_0x100; - register8_t reserved_0x101; - register8_t reserved_0x102; - register8_t reserved_0x103; - register8_t reserved_0x104; - register8_t reserved_0x105; - register8_t reserved_0x106; - register8_t reserved_0x107; - register8_t reserved_0x108; - register8_t reserved_0x109; - register8_t reserved_0x10A; - register8_t reserved_0x10B; - register8_t reserved_0x10C; - register8_t reserved_0x10D; - register8_t reserved_0x10E; - register8_t reserved_0x10F; - register8_t FRAMENUML; /* Frame Number Low Byte */ - register8_t FRAMENUMH; /* Frame Number High Byte */ -} USB_EP_TABLE_t; - -/* Interrupt level */ -typedef enum USB_INTLVL_enum -{ - USB_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ - USB_INTLVL_LO_gc = (0x01<<0), /* Low level */ - USB_INTLVL_MED_gc = (0x02<<0), /* Medium level */ - USB_INTLVL_HI_gc = (0x03<<0), /* High level */ -} USB_INTLVL_t; - -/* USB Endpoint Type */ -typedef enum USB_EP_TYPE_enum -{ - USB_EP_TYPE_DISABLE_gc = (0x00<<6), /* Endpoint Disabled */ - USB_EP_TYPE_CONTROL_gc = (0x01<<6), /* Control */ - USB_EP_TYPE_BULK_gc = (0x02<<6), /* Bulk/Interrupt */ - USB_EP_TYPE_ISOCHRONOUS_gc = (0x03<<6), /* Isochronous */ -} USB_EP_TYPE_t; - -/* USB Endpoint Buffersize */ -typedef enum USB_EP_BUFSIZE_enum -{ - USB_EP_BUFSIZE_8_gc = (0x00<<0), /* 8 bytes buffer size */ - USB_EP_BUFSIZE_16_gc = (0x01<<0), /* 16 bytes buffer size */ - USB_EP_BUFSIZE_32_gc = (0x02<<0), /* 32 bytes buffer size */ - USB_EP_BUFSIZE_64_gc = (0x03<<0), /* 64 bytes buffer size */ - USB_EP_BUFSIZE_128_gc = (0x04<<0), /* 128 bytes buffer size */ - USB_EP_BUFSIZE_256_gc = (0x05<<0), /* 256 bytes buffer size */ - USB_EP_BUFSIZE_512_gc = (0x06<<0), /* 512 bytes buffer size */ - USB_EP_BUFSIZE_1023_gc = (0x07<<0), /* 1023 bytes buffer size */ -} USB_EP_BUFSIZE_t; - - -/* --------------------------------------------------------------------------- -PORT - I/O Port Configuration --------------------------------------------------------------------------- -*/ - -/* I/O Ports */ -typedef struct PORT_struct -{ - register8_t DIR; /* I/O Port Data Direction */ - register8_t DIRSET; /* I/O Port Data Direction Set */ - register8_t DIRCLR; /* I/O Port Data Direction Clear */ - register8_t DIRTGL; /* I/O Port Data Direction Toggle */ - register8_t OUT; /* I/O Port Output */ - register8_t OUTSET; /* I/O Port Output Set */ - register8_t OUTCLR; /* I/O Port Output Clear */ - register8_t OUTTGL; /* I/O Port Output Toggle */ - register8_t IN; /* I/O port Input */ - register8_t INTCTRL; /* Interrupt Control Register */ - register8_t INT0MASK; /* Port Interrupt 0 Mask */ - register8_t INT1MASK; /* Port Interrupt 1 Mask */ - register8_t INTFLAGS; /* Interrupt Flag Register */ - register8_t reserved_0x0D; - register8_t REMAP; /* I/O Port Pin Remap Register */ - register8_t reserved_0x0F; - register8_t PIN0CTRL; /* Pin 0 Control Register */ - register8_t PIN1CTRL; /* Pin 1 Control Register */ - register8_t PIN2CTRL; /* Pin 2 Control Register */ - register8_t PIN3CTRL; /* Pin 3 Control Register */ - register8_t PIN4CTRL; /* Pin 4 Control Register */ - register8_t PIN5CTRL; /* Pin 5 Control Register */ - register8_t PIN6CTRL; /* Pin 6 Control Register */ - register8_t PIN7CTRL; /* Pin 7 Control Register */ -} PORT_t; - -/* Port Interrupt 0 Level */ -typedef enum PORT_INT0LVL_enum -{ - PORT_INT0LVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - PORT_INT0LVL_LO_gc = (0x01<<0), /* Low Level */ - PORT_INT0LVL_MED_gc = (0x02<<0), /* Medium Level */ - PORT_INT0LVL_HI_gc = (0x03<<0), /* High Level */ -} PORT_INT0LVL_t; - -/* Port Interrupt 1 Level */ -typedef enum PORT_INT1LVL_enum -{ - PORT_INT1LVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ - PORT_INT1LVL_LO_gc = (0x01<<2), /* Low Level */ - PORT_INT1LVL_MED_gc = (0x02<<2), /* Medium Level */ - PORT_INT1LVL_HI_gc = (0x03<<2), /* High Level */ -} PORT_INT1LVL_t; - -/* Output/Pull Configuration */ -typedef enum PORT_OPC_enum -{ - PORT_OPC_TOTEM_gc = (0x00<<3), /* Totempole */ - PORT_OPC_BUSKEEPER_gc = (0x01<<3), /* Totempole w/ Bus keeper on Input and Output */ - PORT_OPC_PULLDOWN_gc = (0x02<<3), /* Totempole w/ Pull-down on Input */ - PORT_OPC_PULLUP_gc = (0x03<<3), /* Totempole w/ Pull-up on Input */ - PORT_OPC_WIREDOR_gc = (0x04<<3), /* Wired OR */ - PORT_OPC_WIREDAND_gc = (0x05<<3), /* Wired AND */ - PORT_OPC_WIREDORPULL_gc = (0x06<<3), /* Wired OR w/ Pull-down */ - PORT_OPC_WIREDANDPULL_gc = (0x07<<3), /* Wired AND w/ Pull-up */ -} PORT_OPC_t; - -/* Input/Sense Configuration */ -typedef enum PORT_ISC_enum -{ - PORT_ISC_BOTHEDGES_gc = (0x00<<0), /* Sense Both Edges */ - PORT_ISC_RISING_gc = (0x01<<0), /* Sense Rising Edge */ - PORT_ISC_FALLING_gc = (0x02<<0), /* Sense Falling Edge */ - PORT_ISC_LEVEL_gc = (0x03<<0), /* Sense Level (Transparent For Events) */ - PORT_ISC_INPUT_DISABLE_gc = (0x07<<0), /* Disable Digital Input Buffer */ -} PORT_ISC_t; - - -/* --------------------------------------------------------------------------- -TC - 16-bit Timer/Counter With PWM --------------------------------------------------------------------------- -*/ - -/* 16-bit Timer/Counter 0 */ -typedef struct TC0_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t CTRLC; /* Control register C */ - register8_t CTRLD; /* Control Register D */ - register8_t CTRLE; /* Control Register E */ - register8_t reserved_0x05; - register8_t INTCTRLA; /* Interrupt Control Register A */ - register8_t INTCTRLB; /* Interrupt Control Register B */ - register8_t CTRLFCLR; /* Control Register F Clear */ - register8_t CTRLFSET; /* Control Register F Set */ - register8_t CTRLGCLR; /* Control Register G Clear */ - register8_t CTRLGSET; /* Control Register G Set */ - register8_t INTFLAGS; /* Interrupt Flag Register */ - register8_t reserved_0x0D; - register8_t reserved_0x0E; - register8_t TEMP; /* Temporary Register For 16-bit Access */ - register8_t reserved_0x10; - register8_t reserved_0x11; - register8_t reserved_0x12; - register8_t reserved_0x13; - register8_t reserved_0x14; - register8_t reserved_0x15; - register8_t reserved_0x16; - register8_t reserved_0x17; - register8_t reserved_0x18; - register8_t reserved_0x19; - register8_t reserved_0x1A; - register8_t reserved_0x1B; - register8_t reserved_0x1C; - register8_t reserved_0x1D; - register8_t reserved_0x1E; - register8_t reserved_0x1F; - _WORDREGISTER(CNT); /* Count */ - register8_t reserved_0x22; - register8_t reserved_0x23; - register8_t reserved_0x24; - register8_t reserved_0x25; - _WORDREGISTER(PER); /* Period */ - _WORDREGISTER(CCA); /* Compare or Capture A */ - _WORDREGISTER(CCB); /* Compare or Capture B */ - _WORDREGISTER(CCC); /* Compare or Capture C */ - _WORDREGISTER(CCD); /* Compare or Capture D */ - register8_t reserved_0x30; - register8_t reserved_0x31; - register8_t reserved_0x32; - register8_t reserved_0x33; - register8_t reserved_0x34; - register8_t reserved_0x35; - _WORDREGISTER(PERBUF); /* Period Buffer */ - _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ - _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ - _WORDREGISTER(CCCBUF); /* Compare Or Capture C Buffer */ - _WORDREGISTER(CCDBUF); /* Compare Or Capture D Buffer */ -} TC0_t; - - -/* 16-bit Timer/Counter 1 */ -typedef struct TC1_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t CTRLC; /* Control register C */ - register8_t CTRLD; /* Control Register D */ - register8_t CTRLE; /* Control Register E */ - register8_t reserved_0x05; - register8_t INTCTRLA; /* Interrupt Control Register A */ - register8_t INTCTRLB; /* Interrupt Control Register B */ - register8_t CTRLFCLR; /* Control Register F Clear */ - register8_t CTRLFSET; /* Control Register F Set */ - register8_t CTRLGCLR; /* Control Register G Clear */ - register8_t CTRLGSET; /* Control Register G Set */ - register8_t INTFLAGS; /* Interrupt Flag Register */ - register8_t reserved_0x0D; - register8_t reserved_0x0E; - register8_t TEMP; /* Temporary Register For 16-bit Access */ - register8_t reserved_0x10; - register8_t reserved_0x11; - register8_t reserved_0x12; - register8_t reserved_0x13; - register8_t reserved_0x14; - register8_t reserved_0x15; - register8_t reserved_0x16; - register8_t reserved_0x17; - register8_t reserved_0x18; - register8_t reserved_0x19; - register8_t reserved_0x1A; - register8_t reserved_0x1B; - register8_t reserved_0x1C; - register8_t reserved_0x1D; - register8_t reserved_0x1E; - register8_t reserved_0x1F; - _WORDREGISTER(CNT); /* Count */ - register8_t reserved_0x22; - register8_t reserved_0x23; - register8_t reserved_0x24; - register8_t reserved_0x25; - _WORDREGISTER(PER); /* Period */ - _WORDREGISTER(CCA); /* Compare or Capture A */ - _WORDREGISTER(CCB); /* Compare or Capture B */ - register8_t reserved_0x2C; - register8_t reserved_0x2D; - register8_t reserved_0x2E; - register8_t reserved_0x2F; - register8_t reserved_0x30; - register8_t reserved_0x31; - register8_t reserved_0x32; - register8_t reserved_0x33; - register8_t reserved_0x34; - register8_t reserved_0x35; - _WORDREGISTER(PERBUF); /* Period Buffer */ - _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ - _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ -} TC1_t; - -/* Clock Selection */ -typedef enum TC_CLKSEL_enum -{ - TC_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */ - TC_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */ - TC_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */ - TC_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */ - TC_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */ - TC_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */ - TC_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */ - TC_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */ - TC_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */ - TC_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */ - TC_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */ - TC_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */ - TC_CLKSEL_EVCH4_gc = (0x0C<<0), /* Event Channel 4 */ - TC_CLKSEL_EVCH5_gc = (0x0D<<0), /* Event Channel 5 */ - TC_CLKSEL_EVCH6_gc = (0x0E<<0), /* Event Channel 6 */ - TC_CLKSEL_EVCH7_gc = (0x0F<<0), /* Event Channel 7 */ -} TC_CLKSEL_t; - -/* Waveform Generation Mode */ -typedef enum TC_WGMODE_enum -{ - TC_WGMODE_NORMAL_gc = (0x00<<0), /* Normal Mode */ - TC_WGMODE_FRQ_gc = (0x01<<0), /* Frequency Generation Mode */ - TC_WGMODE_SINGLESLOPE_gc = (0x03<<0), /* Single Slope */ - TC_WGMODE_SS_gc = (0x03<<0), /* Single Slope */ - TC_WGMODE_DSTOP_gc = (0x05<<0), /* Dual Slope, Update on TOP */ - TC_WGMODE_DS_T_gc = (0x05<<0), /* Dual Slope, Update on TOP */ - TC_WGMODE_DSBOTH_gc = (0x06<<0), /* Dual Slope, Update on both TOP and BOTTOM */ - TC_WGMODE_DS_TB_gc = (0x06<<0), /* Dual Slope, Update on both TOP and BOTTOM */ - TC_WGMODE_DSBOTTOM_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */ - TC_WGMODE_DS_B_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */ -} TC_WGMODE_t; - -/* Byte Mode */ -typedef enum TC_BYTEM_enum -{ - TC_BYTEM_NORMAL_gc = (0x00<<0), /* 16-bit mode */ - TC_BYTEM_BYTEMODE_gc = (0x01<<0), /* Timer/Counter operating in byte mode only */ - TC_BYTEM_SPLITMODE_gc = (0x02<<0), /* Timer/Counter split into two 8-bit Counters (TC2) */ -} TC_BYTEM_t; - -/* Event Action */ -typedef enum TC_EVACT_enum -{ - TC_EVACT_OFF_gc = (0x00<<5), /* No Event Action */ - TC_EVACT_CAPT_gc = (0x01<<5), /* Input Capture */ - TC_EVACT_UPDOWN_gc = (0x02<<5), /* Externally Controlled Up/Down Count */ - TC_EVACT_QDEC_gc = (0x03<<5), /* Quadrature Decode */ - TC_EVACT_RESTART_gc = (0x04<<5), /* Restart */ - TC_EVACT_FRQ_gc = (0x05<<5), /* Frequency Capture */ - TC_EVACT_PW_gc = (0x06<<5), /* Pulse-width Capture */ -} TC_EVACT_t; - -/* Event Selection */ -typedef enum TC_EVSEL_enum -{ - TC_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ - TC_EVSEL_CH0_gc = (0x08<<0), /* Event Channel 0 */ - TC_EVSEL_CH1_gc = (0x09<<0), /* Event Channel 1 */ - TC_EVSEL_CH2_gc = (0x0A<<0), /* Event Channel 2 */ - TC_EVSEL_CH3_gc = (0x0B<<0), /* Event Channel 3 */ - TC_EVSEL_CH4_gc = (0x0C<<0), /* Event Channel 4 */ - TC_EVSEL_CH5_gc = (0x0D<<0), /* Event Channel 5 */ - TC_EVSEL_CH6_gc = (0x0E<<0), /* Event Channel 6 */ - TC_EVSEL_CH7_gc = (0x0F<<0), /* Event Channel 7 */ -} TC_EVSEL_t; - -/* Error Interrupt Level */ -typedef enum TC_ERRINTLVL_enum -{ - TC_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ - TC_ERRINTLVL_LO_gc = (0x01<<2), /* Low Level */ - TC_ERRINTLVL_MED_gc = (0x02<<2), /* Medium Level */ - TC_ERRINTLVL_HI_gc = (0x03<<2), /* High Level */ -} TC_ERRINTLVL_t; - -/* Overflow Interrupt Level */ -typedef enum TC_OVFINTLVL_enum -{ - TC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - TC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ - TC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ - TC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ -} TC_OVFINTLVL_t; - -/* Compare or Capture D Interrupt Level */ -typedef enum TC_CCDINTLVL_enum -{ - TC_CCDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ - TC_CCDINTLVL_LO_gc = (0x01<<6), /* Low Level */ - TC_CCDINTLVL_MED_gc = (0x02<<6), /* Medium Level */ - TC_CCDINTLVL_HI_gc = (0x03<<6), /* High Level */ -} TC_CCDINTLVL_t; - -/* Compare or Capture C Interrupt Level */ -typedef enum TC_CCCINTLVL_enum -{ - TC_CCCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ - TC_CCCINTLVL_LO_gc = (0x01<<4), /* Low Level */ - TC_CCCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ - TC_CCCINTLVL_HI_gc = (0x03<<4), /* High Level */ -} TC_CCCINTLVL_t; - -/* Compare or Capture B Interrupt Level */ -typedef enum TC_CCBINTLVL_enum -{ - TC_CCBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ - TC_CCBINTLVL_LO_gc = (0x01<<2), /* Low Level */ - TC_CCBINTLVL_MED_gc = (0x02<<2), /* Medium Level */ - TC_CCBINTLVL_HI_gc = (0x03<<2), /* High Level */ -} TC_CCBINTLVL_t; - -/* Compare or Capture A Interrupt Level */ -typedef enum TC_CCAINTLVL_enum -{ - TC_CCAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - TC_CCAINTLVL_LO_gc = (0x01<<0), /* Low Level */ - TC_CCAINTLVL_MED_gc = (0x02<<0), /* Medium Level */ - TC_CCAINTLVL_HI_gc = (0x03<<0), /* High Level */ -} TC_CCAINTLVL_t; - -/* Timer/Counter Command */ -typedef enum TC_CMD_enum -{ - TC_CMD_NONE_gc = (0x00<<2), /* No Command */ - TC_CMD_UPDATE_gc = (0x01<<2), /* Force Update */ - TC_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ - TC_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ -} TC_CMD_t; - - -/* --------------------------------------------------------------------------- -TC2 - 16-bit Timer/Counter type 2 --------------------------------------------------------------------------- -*/ - -/* 16-bit Timer/Counter type 2 */ -typedef struct TC2_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t CTRLC; /* Control register C */ - register8_t reserved_0x03; - register8_t CTRLE; /* Control Register E */ - register8_t reserved_0x05; - register8_t INTCTRLA; /* Interrupt Control Register A */ - register8_t INTCTRLB; /* Interrupt Control Register B */ - register8_t reserved_0x08; - register8_t CTRLF; /* Control Register F */ - register8_t reserved_0x0A; - register8_t reserved_0x0B; - register8_t INTFLAGS; /* Interrupt Flag Register */ - register8_t reserved_0x0D; - register8_t reserved_0x0E; - register8_t reserved_0x0F; - register8_t reserved_0x10; - register8_t reserved_0x11; - register8_t reserved_0x12; - register8_t reserved_0x13; - register8_t reserved_0x14; - register8_t reserved_0x15; - register8_t reserved_0x16; - register8_t reserved_0x17; - register8_t reserved_0x18; - register8_t reserved_0x19; - register8_t reserved_0x1A; - register8_t reserved_0x1B; - register8_t reserved_0x1C; - register8_t reserved_0x1D; - register8_t reserved_0x1E; - register8_t reserved_0x1F; - register8_t LCNT; /* Low Byte Count */ - register8_t HCNT; /* High Byte Count */ - register8_t reserved_0x22; - register8_t reserved_0x23; - register8_t reserved_0x24; - register8_t reserved_0x25; - register8_t LPER; /* Low Byte Period */ - register8_t HPER; /* High Byte Period */ - register8_t LCMPA; /* Low Byte Compare A */ - register8_t HCMPA; /* High Byte Compare A */ - register8_t LCMPB; /* Low Byte Compare B */ - register8_t HCMPB; /* High Byte Compare B */ - register8_t LCMPC; /* Low Byte Compare C */ - register8_t HCMPC; /* High Byte Compare C */ - register8_t LCMPD; /* Low Byte Compare D */ - register8_t HCMPD; /* High Byte Compare D */ -} TC2_t; - -/* Clock Selection */ -typedef enum TC2_CLKSEL_enum -{ - TC2_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */ - TC2_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */ - TC2_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */ - TC2_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */ - TC2_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */ - TC2_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */ - TC2_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */ - TC2_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */ - TC2_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */ - TC2_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */ - TC2_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */ - TC2_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */ - TC2_CLKSEL_EVCH4_gc = (0x0C<<0), /* Event Channel 4 */ - TC2_CLKSEL_EVCH5_gc = (0x0D<<0), /* Event Channel 5 */ - TC2_CLKSEL_EVCH6_gc = (0x0E<<0), /* Event Channel 6 */ - TC2_CLKSEL_EVCH7_gc = (0x0F<<0), /* Event Channel 7 */ -} TC2_CLKSEL_t; - -/* Byte Mode */ -typedef enum TC2_BYTEM_enum -{ - TC2_BYTEM_NORMAL_gc = (0x00<<0), /* 16-bit mode */ - TC2_BYTEM_BYTEMODE_gc = (0x01<<0), /* Timer/Counter operating in byte mode only (TC2) */ - TC2_BYTEM_SPLITMODE_gc = (0x02<<0), /* Timer/Counter split into two 8-bit Counters */ -} TC2_BYTEM_t; - -/* High Byte Underflow Interrupt Level */ -typedef enum TC2_HUNFINTLVL_enum -{ - TC2_HUNFINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ - TC2_HUNFINTLVL_LO_gc = (0x01<<2), /* Low Level */ - TC2_HUNFINTLVL_MED_gc = (0x02<<2), /* Medium Level */ - TC2_HUNFINTLVL_HI_gc = (0x03<<2), /* High Level */ -} TC2_HUNFINTLVL_t; - -/* Low Byte Underflow Interrupt Level */ -typedef enum TC2_LUNFINTLVL_enum -{ - TC2_LUNFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - TC2_LUNFINTLVL_LO_gc = (0x01<<0), /* Low Level */ - TC2_LUNFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ - TC2_LUNFINTLVL_HI_gc = (0x03<<0), /* High Level */ -} TC2_LUNFINTLVL_t; - -/* Low Byte Compare D Interrupt Level */ -typedef enum TC2_LCMPDINTLVL_enum -{ - TC2_LCMPDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ - TC2_LCMPDINTLVL_LO_gc = (0x01<<6), /* Low Level */ - TC2_LCMPDINTLVL_MED_gc = (0x02<<6), /* Medium Level */ - TC2_LCMPDINTLVL_HI_gc = (0x03<<6), /* High Level */ -} TC2_LCMPDINTLVL_t; - -/* Low Byte Compare C Interrupt Level */ -typedef enum TC2_LCMPCINTLVL_enum -{ - TC2_LCMPCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ - TC2_LCMPCINTLVL_LO_gc = (0x01<<4), /* Low Level */ - TC2_LCMPCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ - TC2_LCMPCINTLVL_HI_gc = (0x03<<4), /* High Level */ -} TC2_LCMPCINTLVL_t; - -/* Low Byte Compare B Interrupt Level */ -typedef enum TC2_LCMPBINTLVL_enum -{ - TC2_LCMPBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ - TC2_LCMPBINTLVL_LO_gc = (0x01<<2), /* Low Level */ - TC2_LCMPBINTLVL_MED_gc = (0x02<<2), /* Medium Level */ - TC2_LCMPBINTLVL_HI_gc = (0x03<<2), /* High Level */ -} TC2_LCMPBINTLVL_t; - -/* Low Byte Compare A Interrupt Level */ -typedef enum TC2_LCMPAINTLVL_enum -{ - TC2_LCMPAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - TC2_LCMPAINTLVL_LO_gc = (0x01<<0), /* Low Level */ - TC2_LCMPAINTLVL_MED_gc = (0x02<<0), /* Medium Level */ - TC2_LCMPAINTLVL_HI_gc = (0x03<<0), /* High Level */ -} TC2_LCMPAINTLVL_t; - -/* Timer/Counter Command */ -typedef enum TC2_CMD_enum -{ - TC2_CMD_NONE_gc = (0x00<<2), /* No Command */ - TC2_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ - TC2_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ -} TC2_CMD_t; - -/* Timer/Counter Command */ -typedef enum TC2_CMDEN_enum -{ - TC2_CMDEN_LOW_gc = (0x01<<0), /* Low Byte Timer/Counter */ - TC2_CMDEN_HIGH_gc = (0x02<<0), /* High Byte Timer/Counter */ - TC2_CMDEN_BOTH_gc = (0x03<<0), /* Both Low Byte and High Byte Timer/Counters */ -} TC2_CMDEN_t; - - -/* --------------------------------------------------------------------------- -AWEX - Timer/Counter Advanced Waveform Extension --------------------------------------------------------------------------- -*/ - -/* Advanced Waveform Extension */ -typedef struct AWEX_struct -{ - register8_t CTRL; /* Control Register */ - register8_t reserved_0x01; - register8_t FDEMASK; /* Fault Detection Event Mask */ - register8_t FDCTRL; /* Fault Detection Control Register */ - register8_t STATUS; /* Status Register */ - register8_t STATUSSET; /* Status Set Register */ - register8_t DTBOTH; /* Dead Time Both Sides */ - register8_t DTBOTHBUF; /* Dead Time Both Sides Buffer */ - register8_t DTLS; /* Dead Time Low Side */ - register8_t DTHS; /* Dead Time High Side */ - register8_t DTLSBUF; /* Dead Time Low Side Buffer */ - register8_t DTHSBUF; /* Dead Time High Side Buffer */ - register8_t OUTOVEN; /* Output Override Enable */ -} AWEX_t; - -/* Fault Detect Action */ -typedef enum AWEX_FDACT_enum -{ - AWEX_FDACT_NONE_gc = (0x00<<0), /* No Fault Protection */ - AWEX_FDACT_CLEAROE_gc = (0x01<<0), /* Clear Output Enable Bits */ - AWEX_FDACT_CLEARDIR_gc = (0x03<<0), /* Clear I/O Port Direction Bits */ -} AWEX_FDACT_t; - - -/* --------------------------------------------------------------------------- -HIRES - Timer/Counter High-Resolution Extension --------------------------------------------------------------------------- -*/ - -/* High-Resolution Extension */ -typedef struct HIRES_struct -{ - register8_t CTRLA; /* Control Register */ -} HIRES_t; - -/* High Resolution Enable */ -typedef enum HIRES_HREN_enum -{ - HIRES_HREN_NONE_gc = (0x00<<0), /* No Fault Protection */ - HIRES_HREN_TC0_gc = (0x01<<0), /* Enable High Resolution on Timer/Counter 0 */ - HIRES_HREN_TC1_gc = (0x02<<0), /* Enable High Resolution on Timer/Counter 1 */ - HIRES_HREN_BOTH_gc = (0x03<<0), /* Enable High Resolution both Timer/Counters */ -} HIRES_HREN_t; - - -/* --------------------------------------------------------------------------- -USART - Universal Asynchronous Receiver-Transmitter --------------------------------------------------------------------------- -*/ - -/* Universal Synchronous/Asynchronous Receiver/Transmitter */ -typedef struct USART_struct -{ - register8_t DATA; /* Data Register */ - register8_t STATUS; /* Status Register */ - register8_t reserved_0x02; - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t CTRLC; /* Control Register C */ - register8_t BAUDCTRLA; /* Baud Rate Control Register A */ - register8_t BAUDCTRLB; /* Baud Rate Control Register B */ -} USART_t; - -/* Receive Complete Interrupt level */ -typedef enum USART_RXCINTLVL_enum -{ - USART_RXCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ - USART_RXCINTLVL_LO_gc = (0x01<<4), /* Low Level */ - USART_RXCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ - USART_RXCINTLVL_HI_gc = (0x03<<4), /* High Level */ -} USART_RXCINTLVL_t; - -/* Transmit Complete Interrupt level */ -typedef enum USART_TXCINTLVL_enum -{ - USART_TXCINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ - USART_TXCINTLVL_LO_gc = (0x01<<2), /* Low Level */ - USART_TXCINTLVL_MED_gc = (0x02<<2), /* Medium Level */ - USART_TXCINTLVL_HI_gc = (0x03<<2), /* High Level */ -} USART_TXCINTLVL_t; - -/* Data Register Empty Interrupt level */ -typedef enum USART_DREINTLVL_enum -{ - USART_DREINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - USART_DREINTLVL_LO_gc = (0x01<<0), /* Low Level */ - USART_DREINTLVL_MED_gc = (0x02<<0), /* Medium Level */ - USART_DREINTLVL_HI_gc = (0x03<<0), /* High Level */ -} USART_DREINTLVL_t; - -/* Character Size */ -typedef enum USART_CHSIZE_enum -{ - USART_CHSIZE_5BIT_gc = (0x00<<0), /* Character size: 5 bit */ - USART_CHSIZE_6BIT_gc = (0x01<<0), /* Character size: 6 bit */ - USART_CHSIZE_7BIT_gc = (0x02<<0), /* Character size: 7 bit */ - USART_CHSIZE_8BIT_gc = (0x03<<0), /* Character size: 8 bit */ - USART_CHSIZE_9BIT_gc = (0x07<<0), /* Character size: 9 bit */ -} USART_CHSIZE_t; - -/* Communication Mode */ -typedef enum USART_CMODE_enum -{ - USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6), /* Asynchronous Mode */ - USART_CMODE_SYNCHRONOUS_gc = (0x01<<6), /* Synchronous Mode */ - USART_CMODE_IRDA_gc = (0x02<<6), /* IrDA Mode */ - USART_CMODE_MSPI_gc = (0x03<<6), /* Master SPI Mode */ -} USART_CMODE_t; - -/* Parity Mode */ -typedef enum USART_PMODE_enum -{ - USART_PMODE_DISABLED_gc = (0x00<<4), /* No Parity */ - USART_PMODE_EVEN_gc = (0x02<<4), /* Even Parity */ - USART_PMODE_ODD_gc = (0x03<<4), /* Odd Parity */ -} USART_PMODE_t; - - -/* --------------------------------------------------------------------------- -SPI - Serial Peripheral Interface --------------------------------------------------------------------------- -*/ - -/* Serial Peripheral Interface */ -typedef struct SPI_struct -{ - register8_t CTRL; /* Control Register */ - register8_t INTCTRL; /* Interrupt Control Register */ - register8_t STATUS; /* Status Register */ - register8_t DATA; /* Data Register */ -} SPI_t; - -/* SPI Mode */ -typedef enum SPI_MODE_enum -{ - SPI_MODE_0_gc = (0x00<<2), /* SPI Mode 0 */ - SPI_MODE_1_gc = (0x01<<2), /* SPI Mode 1 */ - SPI_MODE_2_gc = (0x02<<2), /* SPI Mode 2 */ - SPI_MODE_3_gc = (0x03<<2), /* SPI Mode 3 */ -} SPI_MODE_t; - -/* Prescaler setting */ -typedef enum SPI_PRESCALER_enum -{ - SPI_PRESCALER_DIV4_gc = (0x00<<0), /* System Clock / 4 */ - SPI_PRESCALER_DIV16_gc = (0x01<<0), /* System Clock / 16 */ - SPI_PRESCALER_DIV64_gc = (0x02<<0), /* System Clock / 64 */ - SPI_PRESCALER_DIV128_gc = (0x03<<0), /* System Clock / 128 */ -} SPI_PRESCALER_t; - -/* Interrupt level */ -typedef enum SPI_INTLVL_enum -{ - SPI_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - SPI_INTLVL_LO_gc = (0x01<<0), /* Low Level */ - SPI_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ - SPI_INTLVL_HI_gc = (0x03<<0), /* High Level */ -} SPI_INTLVL_t; - - -/* --------------------------------------------------------------------------- -IRCOM - IR Communication Module --------------------------------------------------------------------------- -*/ - -/* IR Communication Module */ -typedef struct IRCOM_struct -{ - register8_t CTRL; /* Control Register */ - register8_t TXPLCTRL; /* IrDA Transmitter Pulse Length Control Register */ - register8_t RXPLCTRL; /* IrDA Receiver Pulse Length Control Register */ -} IRCOM_t; - -/* Event channel selection */ -typedef enum IRDA_EVSEL_enum -{ - IRDA_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ - IRDA_EVSEL_0_gc = (0x08<<0), /* Event Channel 0 */ - IRDA_EVSEL_1_gc = (0x09<<0), /* Event Channel 1 */ - IRDA_EVSEL_2_gc = (0x0A<<0), /* Event Channel 2 */ - IRDA_EVSEL_3_gc = (0x0B<<0), /* Event Channel 3 */ - IRDA_EVSEL_4_gc = (0x0C<<0), /* Event Channel 4 */ - IRDA_EVSEL_5_gc = (0x0D<<0), /* Event Channel 5 */ - IRDA_EVSEL_6_gc = (0x0E<<0), /* Event Channel 6 */ - IRDA_EVSEL_7_gc = (0x0F<<0), /* Event Channel 7 */ -} IRDA_EVSEL_t; - - -/* --------------------------------------------------------------------------- -FUSE - Fuses and Lockbits --------------------------------------------------------------------------- -*/ - -/* Fuses */ -typedef struct NVM_FUSES_struct -{ - register8_t reserved_0x00; - register8_t FUSEBYTE1; /* Watchdog Configuration */ - register8_t FUSEBYTE2; /* Reset Configuration */ - register8_t reserved_0x03; - register8_t FUSEBYTE4; /* Start-up Configuration */ - register8_t FUSEBYTE5; /* EESAVE and BOD Level */ -} NVM_FUSES_t; - -/* Boot Loader Section Reset Vector */ -typedef enum BOOTRST_enum -{ - BOOTRST_BOOTLDR_gc = (0x00<<6), /* Boot Loader Reset */ - BOOTRST_APPLICATION_gc = (0x01<<6), /* Application Reset */ -} BOOTRST_t; - -/* Timer Oscillator pin location */ -typedef enum TOSCSEL_enum -{ - TOSCSEL_ALTERNATE_gc = (0x00<<5), /* TOSC1 / TOSC2 on separate pins */ - TOSCSEL_XTAL_gc = (0x01<<5), /* TOSC1 / TOSC2 shared with XTAL1 / XTAL2 */ -} TOSCSEL_t; - -/* BOD operation */ -typedef enum BOD_enum -{ - BOD_SAMPLED_gc = (0x01<<0), /* BOD enabled in sampled mode */ - BOD_CONTINUOUS_gc = (0x02<<0), /* BOD enabled continuously */ - BOD_DISABLED_gc = (0x03<<0), /* BOD Disabled */ -} BOD_t; - -/* BOD operation */ -typedef enum BODACT_enum -{ - BODACT_SAMPLED_gc = (0x01<<4), /* BOD enabled in sampled mode */ - BODACT_CONTINUOUS_gc = (0x02<<4), /* BOD enabled continuously */ - BODACT_DISABLED_gc = (0x03<<4), /* BOD Disabled */ -} BODACT_t; - -/* Watchdog (Window) Timeout Period */ -typedef enum WD_enum -{ - WD_8CLK_gc = (0x00<<4), /* 8 cycles (8ms @ 3.3V) */ - WD_16CLK_gc = (0x01<<4), /* 16 cycles (16ms @ 3.3V) */ - WD_32CLK_gc = (0x02<<4), /* 32 cycles (32ms @ 3.3V) */ - WD_64CLK_gc = (0x03<<4), /* 64 cycles (64ms @ 3.3V) */ - WD_128CLK_gc = (0x04<<4), /* 128 cycles (0.125s @ 3.3V) */ - WD_256CLK_gc = (0x05<<4), /* 256 cycles (0.25s @ 3.3V) */ - WD_512CLK_gc = (0x06<<4), /* 512 cycles (0.5s @ 3.3V) */ - WD_1KCLK_gc = (0x07<<4), /* 1K cycles (1s @ 3.3V) */ - WD_2KCLK_gc = (0x08<<4), /* 2K cycles (2s @ 3.3V) */ - WD_4KCLK_gc = (0x09<<4), /* 4K cycles (4s @ 3.3V) */ - WD_8KCLK_gc = (0x0A<<4), /* 8K cycles (8s @ 3.3V) */ -} WD_t; - -/* Watchdog (Window) Timeout Period */ -typedef enum WDP_enum -{ - WDP_8CLK_gc = (0x00<<0), /* 8 cycles (8ms @ 3.3V) */ - WDP_16CLK_gc = (0x01<<0), /* 16 cycles (16ms @ 3.3V) */ - WDP_32CLK_gc = (0x02<<0), /* 32 cycles (32ms @ 3.3V) */ - WDP_64CLK_gc = (0x03<<0), /* 64 cycles (64ms @ 3.3V) */ - WDP_128CLK_gc = (0x04<<0), /* 128 cycles (0.125s @ 3.3V) */ - WDP_256CLK_gc = (0x05<<0), /* 256 cycles (0.25s @ 3.3V) */ - WDP_512CLK_gc = (0x06<<0), /* 512 cycles (0.5s @ 3.3V) */ - WDP_1KCLK_gc = (0x07<<0), /* 1K cycles (1s @ 3.3V) */ - WDP_2KCLK_gc = (0x08<<0), /* 2K cycles (2s @ 3.3V) */ - WDP_4KCLK_gc = (0x09<<0), /* 4K cycles (4s @ 3.3V) */ - WDP_8KCLK_gc = (0x0A<<0), /* 8K cycles (8s @ 3.3V) */ -} WDP_t; - -/* Start-up Time */ -typedef enum SUT_enum -{ - SUT_0MS_gc = (0x03<<2), /* 0 ms */ - SUT_4MS_gc = (0x01<<2), /* 4 ms */ - SUT_64MS_gc = (0x00<<2), /* 64 ms */ -} SUT_t; - -/* Brownout Detection Voltage Level */ -typedef enum BODLVL_enum -{ - BODLVL_1V6_gc = (0x07<<0), /* 1.6 V */ - BODLVL_1V8_gc = (0x06<<0), /* 1.8 V */ - BODLVL_2V0_gc = (0x05<<0), /* 2.0 V */ - BODLVL_2V2_gc = (0x04<<0), /* 2.2 V */ - BODLVL_2V4_gc = (0x03<<0), /* 2.4 V */ - BODLVL_2V6_gc = (0x02<<0), /* 2.6 V */ - BODLVL_2V8_gc = (0x01<<0), /* 2.8 V */ - BODLVL_3V0_gc = (0x00<<0), /* 3.0 V */ -} BODLVL_t; - - -/* --------------------------------------------------------------------------- -LOCKBIT - Fuses and Lockbits --------------------------------------------------------------------------- -*/ - -/* Lock Bits */ -typedef struct NVM_LOCKBITS_struct -{ - register8_t LOCK_BITS; /* Lock Bits (Changed from LOCKBITS to avoid avr-libc collision) */ -} NVM_LOCKBITS_t; - -/* Boot lock bits - boot setcion */ -typedef enum FUSE_BLBB_enum -{ - FUSE_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ - FUSE_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ - FUSE_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ - FUSE_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ -} FUSE_BLBB_t; - -/* Boot lock bits - application section */ -typedef enum FUSE_BLBA_enum -{ - FUSE_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ - FUSE_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ - FUSE_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ - FUSE_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ -} FUSE_BLBA_t; - -/* Boot lock bits - application table section */ -typedef enum FUSE_BLBAT_enum -{ - FUSE_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ - FUSE_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ - FUSE_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ - FUSE_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ -} FUSE_BLBAT_t; - -/* Lock bits */ -typedef enum FUSE_LB_enum -{ - FUSE_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ - FUSE_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ - FUSE_LB_NOLOCK_gc = (0x03<<0), /* No locks */ -} FUSE_LB_t; - - -/* --------------------------------------------------------------------------- -SIGROW - Signature Row --------------------------------------------------------------------------- -*/ - -/* Production Signatures */ -typedef struct NVM_PROD_SIGNATURES_struct -{ - register8_t RCOSC2M; /* RCOSC 2 MHz Calibration Value B */ - register8_t RCOSC2MA; /* RCOSC 2 MHz Calibration Value A */ - register8_t RCOSC32K; /* RCOSC 32.768 kHz Calibration Value */ - register8_t RCOSC32M; /* RCOSC 32 MHz Calibration Value B */ - register8_t RCOSC32MA; /* RCOSC 32 MHz Calibration Value A */ - register8_t reserved_0x05; - register8_t reserved_0x06; - register8_t reserved_0x07; - register8_t LOTNUM0; /* Lot Number Byte 0, ASCII */ - register8_t LOTNUM1; /* Lot Number Byte 1, ASCII */ - register8_t LOTNUM2; /* Lot Number Byte 2, ASCII */ - register8_t LOTNUM3; /* Lot Number Byte 3, ASCII */ - register8_t LOTNUM4; /* Lot Number Byte 4, ASCII */ - register8_t LOTNUM5; /* Lot Number Byte 5, ASCII */ - register8_t reserved_0x0E; - register8_t reserved_0x0F; - register8_t WAFNUM; /* Wafer Number */ - register8_t reserved_0x11; - register8_t COORDX0; /* Wafer Coordinate X Byte 0 */ - register8_t COORDX1; /* Wafer Coordinate X Byte 1 */ - register8_t COORDY0; /* Wafer Coordinate Y Byte 0 */ - register8_t COORDY1; /* Wafer Coordinate Y Byte 1 */ - register8_t reserved_0x16; - register8_t reserved_0x17; - register8_t reserved_0x18; - register8_t reserved_0x19; - register8_t USBCAL0; /* USB Calibration Byte 0 */ - register8_t USBCAL1; /* USB Calibration Byte 1 */ - register8_t USBRCOSC; /* USB RCOSC Calibration Value B */ - register8_t USBRCOSCA; /* USB RCOSC Calibration Value A */ - register8_t reserved_0x1E; - register8_t reserved_0x1F; - register8_t ADCACAL0; /* ADCA Calibration Byte 0 */ - register8_t ADCACAL1; /* ADCA Calibration Byte 1 */ - register8_t reserved_0x22; - register8_t reserved_0x23; - register8_t ADCBCAL0; /* ADCB Calibration Byte 0 */ - register8_t ADCBCAL1; /* ADCB Calibration Byte 1 */ - register8_t reserved_0x26; - register8_t reserved_0x27; - register8_t reserved_0x28; - register8_t reserved_0x29; - register8_t reserved_0x2A; - register8_t reserved_0x2B; - register8_t reserved_0x2C; - register8_t reserved_0x2D; - register8_t TEMPSENSE0; /* Temperature Sensor Calibration Byte 0 */ - register8_t TEMPSENSE1; /* Temperature Sensor Calibration Byte 1 */ - register8_t DACA0OFFCAL; /* DACA0 Calibration Byte 0 */ - register8_t DACA0GAINCAL; /* DACA0 Calibration Byte 1 */ - register8_t DACB0OFFCAL; /* DACB0 Calibration Byte 0 */ - register8_t DACB0GAINCAL; /* DACB0 Calibration Byte 1 */ - register8_t DACA1OFFCAL; /* DACA1 Calibration Byte 0 */ - register8_t DACA1GAINCAL; /* DACA1 Calibration Byte 1 */ - register8_t DACB1OFFCAL; /* DACB1 Calibration Byte 0 */ - register8_t DACB1GAINCAL; /* DACB1 Calibration Byte 1 */ - register8_t reserved_0x38; - register8_t reserved_0x39; - register8_t reserved_0x3A; - register8_t reserved_0x3B; - register8_t reserved_0x3C; - register8_t reserved_0x3D; - register8_t reserved_0x3E; - register8_t reserved_0x3F; - register8_t reserved_0x40; - register8_t reserved_0x41; - register8_t reserved_0x42; - register8_t reserved_0x43; - register8_t reserved_0x44; - register8_t reserved_0x45; - register8_t reserved_0x46; - register8_t reserved_0x47; -} NVM_PROD_SIGNATURES_t; - -/* -========================================================================== -IO Module Instances. Mapped to memory. -========================================================================== -*/ - -#define VPORT0 (*(VPORT_t *) 0x0010) /* Virtual Port */ -#define VPORT1 (*(VPORT_t *) 0x0014) /* Virtual Port */ -#define VPORT2 (*(VPORT_t *) 0x0018) /* Virtual Port */ -#define VPORT3 (*(VPORT_t *) 0x001C) /* Virtual Port */ -#define OCD (*(OCD_t *) 0x002E) /* On-Chip Debug System */ -#define CLK (*(CLK_t *) 0x0040) /* Clock System */ -#define SLEEP (*(SLEEP_t *) 0x0048) /* Sleep Controller */ -#define OSC (*(OSC_t *) 0x0050) /* Oscillator */ -#define DFLLRC32M (*(DFLL_t *) 0x0060) /* DFLL */ -#define DFLLRC2M (*(DFLL_t *) 0x0068) /* DFLL */ -#define PR (*(PR_t *) 0x0070) /* Power Reduction */ -#define RST (*(RST_t *) 0x0078) /* Reset */ -#define WDT (*(WDT_t *) 0x0080) /* Watch-Dog Timer */ -#define MCU (*(MCU_t *) 0x0090) /* MCU Control */ -#define PMIC (*(PMIC_t *) 0x00A0) /* Programmable Multi-level Interrupt Controller */ -#define PORTCFG (*(PORTCFG_t *) 0x00B0) /* I/O port Configuration */ -#define AES (*(AES_t *) 0x00C0) /* AES Module */ -#define CRC (*(CRC_t *) 0x00D0) /* Cyclic Redundancy Checker */ -#define DMA (*(DMA_t *) 0x0100) /* DMA Controller */ -#define EVSYS (*(EVSYS_t *) 0x0180) /* Event System */ -#define NVM (*(NVM_t *) 0x01C0) /* Non-volatile Memory Controller */ -#define ADCA (*(ADC_t *) 0x0200) /* Analog-to-Digital Converter */ -#define DACB (*(DAC_t *) 0x0320) /* Digital-to-Analog Converter */ -#define ACA (*(AC_t *) 0x0380) /* Analog Comparator */ -#define RTC (*(RTC_t *) 0x0400) /* Real-Time Counter */ -#define TWIC (*(TWI_t *) 0x0480) /* Two-Wire Interface */ -#define TWIE (*(TWI_t *) 0x04A0) /* Two-Wire Interface */ -#define USB (*(USB_t *) 0x04C0) /* Universal Serial Bus */ -#define PORTA (*(PORT_t *) 0x0600) /* I/O Ports */ -#define PORTB (*(PORT_t *) 0x0620) /* I/O Ports */ -#define PORTC (*(PORT_t *) 0x0640) /* I/O Ports */ -#define PORTD (*(PORT_t *) 0x0660) /* I/O Ports */ -#define PORTE (*(PORT_t *) 0x0680) /* I/O Ports */ -#define PORTR (*(PORT_t *) 0x07E0) /* I/O Ports */ -#define TCC0 (*(TC0_t *) 0x0800) /* 16-bit Timer/Counter 0 */ -#define TCC2 (*(TC2_t *) 0x0800) /* 16-bit Timer/Counter type 2 */ -#define TCC1 (*(TC1_t *) 0x0840) /* 16-bit Timer/Counter 1 */ -#define AWEXC (*(AWEX_t *) 0x0880) /* Advanced Waveform Extension */ -#define HIRESC (*(HIRES_t *) 0x0890) /* High-Resolution Extension */ -#define USARTC0 (*(USART_t *) 0x08A0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ -#define USARTC1 (*(USART_t *) 0x08B0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ -#define SPIC (*(SPI_t *) 0x08C0) /* Serial Peripheral Interface */ -#define IRCOM (*(IRCOM_t *) 0x08F8) /* IR Communication Module */ -#define TCD0 (*(TC0_t *) 0x0900) /* 16-bit Timer/Counter 0 */ -#define TCD2 (*(TC2_t *) 0x0900) /* 16-bit Timer/Counter type 2 */ -#define TCD1 (*(TC1_t *) 0x0940) /* 16-bit Timer/Counter 1 */ -#define HIRESD (*(HIRES_t *) 0x0990) /* High-Resolution Extension */ -#define USARTD0 (*(USART_t *) 0x09A0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ -#define USARTD1 (*(USART_t *) 0x09B0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ -#define SPID (*(SPI_t *) 0x09C0) /* Serial Peripheral Interface */ -#define TCE0 (*(TC0_t *) 0x0A00) /* 16-bit Timer/Counter 0 */ -#define HIRESE (*(HIRES_t *) 0x0A90) /* High-Resolution Extension */ -#define USARTE0 (*(USART_t *) 0x0AA0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ - - -#endif /* !defined (__ASSEMBLER__) */ - - -/* ========== Flattened fully qualified IO register names ========== */ - -/* GPIO - General Purpose IO Registers */ -#define GPIO_GPIOR0 _SFR_MEM8(0x0000) -#define GPIO_GPIOR1 _SFR_MEM8(0x0001) -#define GPIO_GPIOR2 _SFR_MEM8(0x0002) -#define GPIO_GPIOR3 _SFR_MEM8(0x0003) -#define GPIO_GPIOR4 _SFR_MEM8(0x0004) -#define GPIO_GPIOR5 _SFR_MEM8(0x0005) -#define GPIO_GPIOR6 _SFR_MEM8(0x0006) -#define GPIO_GPIOR7 _SFR_MEM8(0x0007) -#define GPIO_GPIOR8 _SFR_MEM8(0x0008) -#define GPIO_GPIOR9 _SFR_MEM8(0x0009) -#define GPIO_GPIORA _SFR_MEM8(0x000A) -#define GPIO_GPIORB _SFR_MEM8(0x000B) -#define GPIO_GPIORC _SFR_MEM8(0x000C) -#define GPIO_GPIORD _SFR_MEM8(0x000D) -#define GPIO_GPIORE _SFR_MEM8(0x000E) -#define GPIO_GPIORF _SFR_MEM8(0x000F) - -/* Deprecated */ -#define GPIO_GPIO0 _SFR_MEM8(0x0000) -#define GPIO_GPIO1 _SFR_MEM8(0x0001) -#define GPIO_GPIO2 _SFR_MEM8(0x0002) -#define GPIO_GPIO3 _SFR_MEM8(0x0003) -#define GPIO_GPIO4 _SFR_MEM8(0x0004) -#define GPIO_GPIO5 _SFR_MEM8(0x0005) -#define GPIO_GPIO6 _SFR_MEM8(0x0006) -#define GPIO_GPIO7 _SFR_MEM8(0x0007) -#define GPIO_GPIO8 _SFR_MEM8(0x0008) -#define GPIO_GPIO9 _SFR_MEM8(0x0009) -#define GPIO_GPIOA _SFR_MEM8(0x000A) -#define GPIO_GPIOB _SFR_MEM8(0x000B) -#define GPIO_GPIOC _SFR_MEM8(0x000C) -#define GPIO_GPIOD _SFR_MEM8(0x000D) -#define GPIO_GPIOE _SFR_MEM8(0x000E) -#define GPIO_GPIOF _SFR_MEM8(0x000F) - -/* NVM_FUSES - Fuses */ -#define FUSE_FUSEBYTE1 _SFR_MEM8(0x0001) -#define FUSE_FUSEBYTE2 _SFR_MEM8(0x0002) -#define FUSE_FUSEBYTE4 _SFR_MEM8(0x0004) -#define FUSE_FUSEBYTE5 _SFR_MEM8(0x0005) - -/* NVM_LOCKBITS - Lock Bits */ -#define LOCKBIT_LOCKBITS _SFR_MEM8(0x0000) - -/* NVM_PROD_SIGNATURES - Production Signatures */ -#define PRODSIGNATURES_RCOSC2M _SFR_MEM8(0x0000) -#define PRODSIGNATURES_RCOSC2MA _SFR_MEM8(0x0001) -#define PRODSIGNATURES_RCOSC32K _SFR_MEM8(0x0002) -#define PRODSIGNATURES_RCOSC32M _SFR_MEM8(0x0003) -#define PRODSIGNATURES_RCOSC32MA _SFR_MEM8(0x0004) -#define PRODSIGNATURES_LOTNUM0 _SFR_MEM8(0x0008) -#define PRODSIGNATURES_LOTNUM1 _SFR_MEM8(0x0009) -#define PRODSIGNATURES_LOTNUM2 _SFR_MEM8(0x000A) -#define PRODSIGNATURES_LOTNUM3 _SFR_MEM8(0x000B) -#define PRODSIGNATURES_LOTNUM4 _SFR_MEM8(0x000C) -#define PRODSIGNATURES_LOTNUM5 _SFR_MEM8(0x000D) -#define PRODSIGNATURES_WAFNUM _SFR_MEM8(0x0010) -#define PRODSIGNATURES_COORDX0 _SFR_MEM8(0x0012) -#define PRODSIGNATURES_COORDX1 _SFR_MEM8(0x0013) -#define PRODSIGNATURES_COORDY0 _SFR_MEM8(0x0014) -#define PRODSIGNATURES_COORDY1 _SFR_MEM8(0x0015) -#define PRODSIGNATURES_USBCAL0 _SFR_MEM8(0x001A) -#define PRODSIGNATURES_USBCAL1 _SFR_MEM8(0x001B) -#define PRODSIGNATURES_USBRCOSC _SFR_MEM8(0x001C) -#define PRODSIGNATURES_USBRCOSCA _SFR_MEM8(0x001D) -#define PRODSIGNATURES_ADCACAL0 _SFR_MEM8(0x0020) -#define PRODSIGNATURES_ADCACAL1 _SFR_MEM8(0x0021) -#define PRODSIGNATURES_ADCBCAL0 _SFR_MEM8(0x0024) -#define PRODSIGNATURES_ADCBCAL1 _SFR_MEM8(0x0025) -#define PRODSIGNATURES_TEMPSENSE0 _SFR_MEM8(0x002E) -#define PRODSIGNATURES_TEMPSENSE1 _SFR_MEM8(0x002F) -#define PRODSIGNATURES_DACA0OFFCAL _SFR_MEM8(0x0030) -#define PRODSIGNATURES_DACA0GAINCAL _SFR_MEM8(0x0031) -#define PRODSIGNATURES_DACB0OFFCAL _SFR_MEM8(0x0032) -#define PRODSIGNATURES_DACB0GAINCAL _SFR_MEM8(0x0033) -#define PRODSIGNATURES_DACA1OFFCAL _SFR_MEM8(0x0034) -#define PRODSIGNATURES_DACA1GAINCAL _SFR_MEM8(0x0035) -#define PRODSIGNATURES_DACB1OFFCAL _SFR_MEM8(0x0036) -#define PRODSIGNATURES_DACB1GAINCAL _SFR_MEM8(0x0037) - -/* VPORT - Virtual Port */ -#define VPORT0_DIR _SFR_MEM8(0x0010) -#define VPORT0_OUT _SFR_MEM8(0x0011) -#define VPORT0_IN _SFR_MEM8(0x0012) -#define VPORT0_INTFLAGS _SFR_MEM8(0x0013) - -/* VPORT - Virtual Port */ -#define VPORT1_DIR _SFR_MEM8(0x0014) -#define VPORT1_OUT _SFR_MEM8(0x0015) -#define VPORT1_IN _SFR_MEM8(0x0016) -#define VPORT1_INTFLAGS _SFR_MEM8(0x0017) - -/* VPORT - Virtual Port */ -#define VPORT2_DIR _SFR_MEM8(0x0018) -#define VPORT2_OUT _SFR_MEM8(0x0019) -#define VPORT2_IN _SFR_MEM8(0x001A) -#define VPORT2_INTFLAGS _SFR_MEM8(0x001B) - -/* VPORT - Virtual Port */ -#define VPORT3_DIR _SFR_MEM8(0x001C) -#define VPORT3_OUT _SFR_MEM8(0x001D) -#define VPORT3_IN _SFR_MEM8(0x001E) -#define VPORT3_INTFLAGS _SFR_MEM8(0x001F) - -/* OCD - On-Chip Debug System */ -#define OCD_OCDR0 _SFR_MEM8(0x002E) -#define OCD_OCDR1 _SFR_MEM8(0x002F) - -/* CPU - CPU registers */ -#define CPU_CCP _SFR_MEM8(0x0034) -#define CPU_RAMPD _SFR_MEM8(0x0038) -#define CPU_RAMPX _SFR_MEM8(0x0039) -#define CPU_RAMPY _SFR_MEM8(0x003A) -#define CPU_RAMPZ _SFR_MEM8(0x003B) -#define CPU_EIND _SFR_MEM8(0x003C) -#define CPU_SPL _SFR_MEM8(0x003D) -#define CPU_SPH _SFR_MEM8(0x003E) -#define CPU_SREG _SFR_MEM8(0x003F) - -/* CLK - Clock System */ -#define CLK_CTRL _SFR_MEM8(0x0040) -#define CLK_PSCTRL _SFR_MEM8(0x0041) -#define CLK_LOCK _SFR_MEM8(0x0042) -#define CLK_RTCCTRL _SFR_MEM8(0x0043) -#define CLK_USBCTRL _SFR_MEM8(0x0044) - -/* SLEEP - Sleep Controller */ -#define SLEEP_CTRL _SFR_MEM8(0x0048) - -/* OSC - Oscillator */ -#define OSC_CTRL _SFR_MEM8(0x0050) -#define OSC_STATUS _SFR_MEM8(0x0051) -#define OSC_XOSCCTRL _SFR_MEM8(0x0052) -#define OSC_XOSCFAIL _SFR_MEM8(0x0053) -#define OSC_RC32KCAL _SFR_MEM8(0x0054) -#define OSC_PLLCTRL _SFR_MEM8(0x0055) -#define OSC_DFLLCTRL _SFR_MEM8(0x0056) - -/* DFLL - DFLL */ -#define DFLLRC32M_CTRL _SFR_MEM8(0x0060) -#define DFLLRC32M_CALA _SFR_MEM8(0x0062) -#define DFLLRC32M_CALB _SFR_MEM8(0x0063) -#define DFLLRC32M_COMP0 _SFR_MEM8(0x0064) -#define DFLLRC32M_COMP1 _SFR_MEM8(0x0065) -#define DFLLRC32M_COMP2 _SFR_MEM8(0x0066) - -/* DFLL - DFLL */ -#define DFLLRC2M_CTRL _SFR_MEM8(0x0068) -#define DFLLRC2M_CALA _SFR_MEM8(0x006A) -#define DFLLRC2M_CALB _SFR_MEM8(0x006B) -#define DFLLRC2M_COMP0 _SFR_MEM8(0x006C) -#define DFLLRC2M_COMP1 _SFR_MEM8(0x006D) -#define DFLLRC2M_COMP2 _SFR_MEM8(0x006E) - -/* PR - Power Reduction */ -#define PR_PRGEN _SFR_MEM8(0x0070) -#define PR_PRPA _SFR_MEM8(0x0071) -#define PR_PRPB _SFR_MEM8(0x0072) -#define PR_PRPC _SFR_MEM8(0x0073) -#define PR_PRPD _SFR_MEM8(0x0074) -#define PR_PRPE _SFR_MEM8(0x0075) -#define PR_PRPF _SFR_MEM8(0x0076) - -/* RST - Reset */ -#define RST_STATUS _SFR_MEM8(0x0078) -#define RST_CTRL _SFR_MEM8(0x0079) - -/* WDT - Watch-Dog Timer */ -#define WDT_CTRL _SFR_MEM8(0x0080) -#define WDT_WINCTRL _SFR_MEM8(0x0081) -#define WDT_STATUS _SFR_MEM8(0x0082) - -/* MCU - MCU Control */ -#define MCU_DEVID0 _SFR_MEM8(0x0090) -#define MCU_DEVID1 _SFR_MEM8(0x0091) -#define MCU_DEVID2 _SFR_MEM8(0x0092) -#define MCU_REVID _SFR_MEM8(0x0093) -#define MCU_JTAGUID _SFR_MEM8(0x0094) -#define MCU_MCUCR _SFR_MEM8(0x0096) -#define MCU_ANAINIT _SFR_MEM8(0x0097) -#define MCU_EVSYSLOCK _SFR_MEM8(0x0098) -#define MCU_AWEXLOCK _SFR_MEM8(0x0099) - -/* PMIC - Programmable Multi-level Interrupt Controller */ -#define PMIC_STATUS _SFR_MEM8(0x00A0) -#define PMIC_INTPRI _SFR_MEM8(0x00A1) -#define PMIC_CTRL _SFR_MEM8(0x00A2) - -/* PORTCFG - I/O port Configuration */ -#define PORTCFG_MPCMASK _SFR_MEM8(0x00B0) -#define PORTCFG_VPCTRLA _SFR_MEM8(0x00B2) -#define PORTCFG_VPCTRLB _SFR_MEM8(0x00B3) -#define PORTCFG_CLKEVOUT _SFR_MEM8(0x00B4) -#define PORTCFG_EBIOUT _SFR_MEM8(0x00B5) -#define PORTCFG_EVOUTSEL _SFR_MEM8(0x00B6) - -/* AES - AES Module */ -#define AES_CTRL _SFR_MEM8(0x00C0) -#define AES_STATUS _SFR_MEM8(0x00C1) -#define AES_STATE _SFR_MEM8(0x00C2) -#define AES_KEY _SFR_MEM8(0x00C3) -#define AES_INTCTRL _SFR_MEM8(0x00C4) - -/* CRC - Cyclic Redundancy Checker */ -#define CRC_CTRL _SFR_MEM8(0x00D0) -#define CRC_STATUS _SFR_MEM8(0x00D1) -#define CRC_DATAIN _SFR_MEM8(0x00D3) -#define CRC_CHECKSUM0 _SFR_MEM8(0x00D4) -#define CRC_CHECKSUM1 _SFR_MEM8(0x00D5) -#define CRC_CHECKSUM2 _SFR_MEM8(0x00D6) -#define CRC_CHECKSUM3 _SFR_MEM8(0x00D7) - -/* DMA - DMA Controller */ -#define DMA_CTRL _SFR_MEM8(0x0100) -#define DMA_INTFLAGS _SFR_MEM8(0x0103) -#define DMA_STATUS _SFR_MEM8(0x0104) -#define DMA_TEMP _SFR_MEM16(0x0106) -#define DMA_CH0_CTRLA _SFR_MEM8(0x0110) -#define DMA_CH0_CTRLB _SFR_MEM8(0x0111) -#define DMA_CH0_ADDRCTRL _SFR_MEM8(0x0112) -#define DMA_CH0_TRIGSRC _SFR_MEM8(0x0113) -#define DMA_CH0_TRFCNT _SFR_MEM16(0x0114) -#define DMA_CH0_REPCNT _SFR_MEM8(0x0116) -#define DMA_CH0_SRCADDR0 _SFR_MEM8(0x0118) -#define DMA_CH0_SRCADDR1 _SFR_MEM8(0x0119) -#define DMA_CH0_SRCADDR2 _SFR_MEM8(0x011A) -#define DMA_CH0_DESTADDR0 _SFR_MEM8(0x011C) -#define DMA_CH0_DESTADDR1 _SFR_MEM8(0x011D) -#define DMA_CH0_DESTADDR2 _SFR_MEM8(0x011E) -#define DMA_CH1_CTRLA _SFR_MEM8(0x0120) -#define DMA_CH1_CTRLB _SFR_MEM8(0x0121) -#define DMA_CH1_ADDRCTRL _SFR_MEM8(0x0122) -#define DMA_CH1_TRIGSRC _SFR_MEM8(0x0123) -#define DMA_CH1_TRFCNT _SFR_MEM16(0x0124) -#define DMA_CH1_REPCNT _SFR_MEM8(0x0126) -#define DMA_CH1_SRCADDR0 _SFR_MEM8(0x0128) -#define DMA_CH1_SRCADDR1 _SFR_MEM8(0x0129) -#define DMA_CH1_SRCADDR2 _SFR_MEM8(0x012A) -#define DMA_CH1_DESTADDR0 _SFR_MEM8(0x012C) -#define DMA_CH1_DESTADDR1 _SFR_MEM8(0x012D) -#define DMA_CH1_DESTADDR2 _SFR_MEM8(0x012E) -#define DMA_CH2_CTRLA _SFR_MEM8(0x0130) -#define DMA_CH2_CTRLB _SFR_MEM8(0x0131) -#define DMA_CH2_ADDRCTRL _SFR_MEM8(0x0132) -#define DMA_CH2_TRIGSRC _SFR_MEM8(0x0133) -#define DMA_CH2_TRFCNT _SFR_MEM16(0x0134) -#define DMA_CH2_REPCNT _SFR_MEM8(0x0136) -#define DMA_CH2_SRCADDR0 _SFR_MEM8(0x0138) -#define DMA_CH2_SRCADDR1 _SFR_MEM8(0x0139) -#define DMA_CH2_SRCADDR2 _SFR_MEM8(0x013A) -#define DMA_CH2_DESTADDR0 _SFR_MEM8(0x013C) -#define DMA_CH2_DESTADDR1 _SFR_MEM8(0x013D) -#define DMA_CH2_DESTADDR2 _SFR_MEM8(0x013E) -#define DMA_CH3_CTRLA _SFR_MEM8(0x0140) -#define DMA_CH3_CTRLB _SFR_MEM8(0x0141) -#define DMA_CH3_ADDRCTRL _SFR_MEM8(0x0142) -#define DMA_CH3_TRIGSRC _SFR_MEM8(0x0143) -#define DMA_CH3_TRFCNT _SFR_MEM16(0x0144) -#define DMA_CH3_REPCNT _SFR_MEM8(0x0146) -#define DMA_CH3_SRCADDR0 _SFR_MEM8(0x0148) -#define DMA_CH3_SRCADDR1 _SFR_MEM8(0x0149) -#define DMA_CH3_SRCADDR2 _SFR_MEM8(0x014A) -#define DMA_CH3_DESTADDR0 _SFR_MEM8(0x014C) -#define DMA_CH3_DESTADDR1 _SFR_MEM8(0x014D) -#define DMA_CH3_DESTADDR2 _SFR_MEM8(0x014E) - -/* EVSYS - Event System */ -#define EVSYS_CH0MUX _SFR_MEM8(0x0180) -#define EVSYS_CH1MUX _SFR_MEM8(0x0181) -#define EVSYS_CH2MUX _SFR_MEM8(0x0182) -#define EVSYS_CH3MUX _SFR_MEM8(0x0183) -#define EVSYS_CH4MUX _SFR_MEM8(0x0184) -#define EVSYS_CH5MUX _SFR_MEM8(0x0185) -#define EVSYS_CH6MUX _SFR_MEM8(0x0186) -#define EVSYS_CH7MUX _SFR_MEM8(0x0187) -#define EVSYS_CH0CTRL _SFR_MEM8(0x0188) -#define EVSYS_CH1CTRL _SFR_MEM8(0x0189) -#define EVSYS_CH2CTRL _SFR_MEM8(0x018A) -#define EVSYS_CH3CTRL _SFR_MEM8(0x018B) -#define EVSYS_CH4CTRL _SFR_MEM8(0x018C) -#define EVSYS_CH5CTRL _SFR_MEM8(0x018D) -#define EVSYS_CH6CTRL _SFR_MEM8(0x018E) -#define EVSYS_CH7CTRL _SFR_MEM8(0x018F) -#define EVSYS_STROBE _SFR_MEM8(0x0190) -#define EVSYS_DATA _SFR_MEM8(0x0191) - -/* NVM - Non-volatile Memory Controller */ -#define NVM_ADDR0 _SFR_MEM8(0x01C0) -#define NVM_ADDR1 _SFR_MEM8(0x01C1) -#define NVM_ADDR2 _SFR_MEM8(0x01C2) -#define NVM_DATA0 _SFR_MEM8(0x01C4) -#define NVM_DATA1 _SFR_MEM8(0x01C5) -#define NVM_DATA2 _SFR_MEM8(0x01C6) -#define NVM_CMD _SFR_MEM8(0x01CA) -#define NVM_CTRLA _SFR_MEM8(0x01CB) -#define NVM_CTRLB _SFR_MEM8(0x01CC) -#define NVM_INTCTRL _SFR_MEM8(0x01CD) -#define NVM_STATUS _SFR_MEM8(0x01CF) -#define NVM_LOCKBITS _SFR_MEM8(0x01D0) - -/* ADC - Analog-to-Digital Converter */ -#define ADCA_CTRLA _SFR_MEM8(0x0200) -#define ADCA_CTRLB _SFR_MEM8(0x0201) -#define ADCA_REFCTRL _SFR_MEM8(0x0202) -#define ADCA_EVCTRL _SFR_MEM8(0x0203) -#define ADCA_PRESCALER _SFR_MEM8(0x0204) -#define ADCA_INTFLAGS _SFR_MEM8(0x0206) -#define ADCA_TEMP _SFR_MEM8(0x0207) -#define ADCA_CAL _SFR_MEM16(0x020C) -#define ADCA_CH0RES _SFR_MEM16(0x0210) -#define ADCA_CH1RES _SFR_MEM16(0x0212) -#define ADCA_CH2RES _SFR_MEM16(0x0214) -#define ADCA_CH3RES _SFR_MEM16(0x0216) -#define ADCA_CMP _SFR_MEM16(0x0218) -#define ADCA_CH0_CTRL _SFR_MEM8(0x0220) -#define ADCA_CH0_MUXCTRL _SFR_MEM8(0x0221) -#define ADCA_CH0_INTCTRL _SFR_MEM8(0x0222) -#define ADCA_CH0_INTFLAGS _SFR_MEM8(0x0223) -#define ADCA_CH0_RES _SFR_MEM16(0x0224) -#define ADCA_CH0_SCAN _SFR_MEM8(0x0226) -#define ADCA_CH1_CTRL _SFR_MEM8(0x0228) -#define ADCA_CH1_MUXCTRL _SFR_MEM8(0x0229) -#define ADCA_CH1_INTCTRL _SFR_MEM8(0x022A) -#define ADCA_CH1_INTFLAGS _SFR_MEM8(0x022B) -#define ADCA_CH1_RES _SFR_MEM16(0x022C) -#define ADCA_CH1_SCAN _SFR_MEM8(0x022E) -#define ADCA_CH2_CTRL _SFR_MEM8(0x0230) -#define ADCA_CH2_MUXCTRL _SFR_MEM8(0x0231) -#define ADCA_CH2_INTCTRL _SFR_MEM8(0x0232) -#define ADCA_CH2_INTFLAGS _SFR_MEM8(0x0233) -#define ADCA_CH2_RES _SFR_MEM16(0x0234) -#define ADCA_CH2_SCAN _SFR_MEM8(0x0236) -#define ADCA_CH3_CTRL _SFR_MEM8(0x0238) -#define ADCA_CH3_MUXCTRL _SFR_MEM8(0x0239) -#define ADCA_CH3_INTCTRL _SFR_MEM8(0x023A) -#define ADCA_CH3_INTFLAGS _SFR_MEM8(0x023B) -#define ADCA_CH3_RES _SFR_MEM16(0x023C) -#define ADCA_CH3_SCAN _SFR_MEM8(0x023E) - -/* DAC - Digital-to-Analog Converter */ -#define DACB_CTRLA _SFR_MEM8(0x0320) -#define DACB_CTRLB _SFR_MEM8(0x0321) -#define DACB_CTRLC _SFR_MEM8(0x0322) -#define DACB_EVCTRL _SFR_MEM8(0x0323) -#define DACB_STATUS _SFR_MEM8(0x0325) -#define DACB_CH0GAINCAL _SFR_MEM8(0x0328) -#define DACB_CH0OFFSETCAL _SFR_MEM8(0x0329) -#define DACB_CH1GAINCAL _SFR_MEM8(0x032A) -#define DACB_CH1OFFSETCAL _SFR_MEM8(0x032B) -#define DACB_CH0DATA _SFR_MEM16(0x0338) -#define DACB_CH1DATA _SFR_MEM16(0x033A) - -/* AC - Analog Comparator */ -#define ACA_AC0CTRL _SFR_MEM8(0x0380) -#define ACA_AC1CTRL _SFR_MEM8(0x0381) -#define ACA_AC0MUXCTRL _SFR_MEM8(0x0382) -#define ACA_AC1MUXCTRL _SFR_MEM8(0x0383) -#define ACA_CTRLA _SFR_MEM8(0x0384) -#define ACA_CTRLB _SFR_MEM8(0x0385) -#define ACA_WINCTRL _SFR_MEM8(0x0386) -#define ACA_STATUS _SFR_MEM8(0x0387) - -/* RTC - Real-Time Counter */ -#define RTC_CTRL _SFR_MEM8(0x0400) -#define RTC_STATUS _SFR_MEM8(0x0401) -#define RTC_INTCTRL _SFR_MEM8(0x0402) -#define RTC_INTFLAGS _SFR_MEM8(0x0403) -#define RTC_TEMP _SFR_MEM8(0x0404) -#define RTC_CNT _SFR_MEM16(0x0408) -#define RTC_PER _SFR_MEM16(0x040A) -#define RTC_COMP _SFR_MEM16(0x040C) - -/* TWI - Two-Wire Interface */ -#define TWIC_CTRL _SFR_MEM8(0x0480) -#define TWIC_MASTER_CTRLA _SFR_MEM8(0x0481) -#define TWIC_MASTER_CTRLB _SFR_MEM8(0x0482) -#define TWIC_MASTER_CTRLC _SFR_MEM8(0x0483) -#define TWIC_MASTER_STATUS _SFR_MEM8(0x0484) -#define TWIC_MASTER_BAUD _SFR_MEM8(0x0485) -#define TWIC_MASTER_ADDR _SFR_MEM8(0x0486) -#define TWIC_MASTER_DATA _SFR_MEM8(0x0487) -#define TWIC_SLAVE_CTRLA _SFR_MEM8(0x0488) -#define TWIC_SLAVE_CTRLB _SFR_MEM8(0x0489) -#define TWIC_SLAVE_STATUS _SFR_MEM8(0x048A) -#define TWIC_SLAVE_ADDR _SFR_MEM8(0x048B) -#define TWIC_SLAVE_DATA _SFR_MEM8(0x048C) -#define TWIC_SLAVE_ADDRMASK _SFR_MEM8(0x048D) - -/* TWI - Two-Wire Interface */ -#define TWIE_CTRL _SFR_MEM8(0x04A0) -#define TWIE_MASTER_CTRLA _SFR_MEM8(0x04A1) -#define TWIE_MASTER_CTRLB _SFR_MEM8(0x04A2) -#define TWIE_MASTER_CTRLC _SFR_MEM8(0x04A3) -#define TWIE_MASTER_STATUS _SFR_MEM8(0x04A4) -#define TWIE_MASTER_BAUD _SFR_MEM8(0x04A5) -#define TWIE_MASTER_ADDR _SFR_MEM8(0x04A6) -#define TWIE_MASTER_DATA _SFR_MEM8(0x04A7) -#define TWIE_SLAVE_CTRLA _SFR_MEM8(0x04A8) -#define TWIE_SLAVE_CTRLB _SFR_MEM8(0x04A9) -#define TWIE_SLAVE_STATUS _SFR_MEM8(0x04AA) -#define TWIE_SLAVE_ADDR _SFR_MEM8(0x04AB) -#define TWIE_SLAVE_DATA _SFR_MEM8(0x04AC) -#define TWIE_SLAVE_ADDRMASK _SFR_MEM8(0x04AD) - -/* USB - Universal Serial Bus */ -#define USB_CTRLA _SFR_MEM8(0x04C0) -#define USB_CTRLB _SFR_MEM8(0x04C1) -#define USB_STATUS _SFR_MEM8(0x04C2) -#define USB_ADDR _SFR_MEM8(0x04C3) -#define USB_FIFOWP _SFR_MEM8(0x04C4) -#define USB_FIFORP _SFR_MEM8(0x04C5) -#define USB_EPPTR _SFR_MEM16(0x04C6) -#define USB_INTCTRLA _SFR_MEM8(0x04C8) -#define USB_INTCTRLB _SFR_MEM8(0x04C9) -#define USB_INTFLAGSACLR _SFR_MEM8(0x04CA) -#define USB_INTFLAGSASET _SFR_MEM8(0x04CB) -#define USB_INTFLAGSBCLR _SFR_MEM8(0x04CC) -#define USB_INTFLAGSBSET _SFR_MEM8(0x04CD) -#define USB_CAL0 _SFR_MEM8(0x04FA) -#define USB_CAL1 _SFR_MEM8(0x04FB) - -/* PORT - I/O Ports */ -#define PORTA_DIR _SFR_MEM8(0x0600) -#define PORTA_DIRSET _SFR_MEM8(0x0601) -#define PORTA_DIRCLR _SFR_MEM8(0x0602) -#define PORTA_DIRTGL _SFR_MEM8(0x0603) -#define PORTA_OUT _SFR_MEM8(0x0604) -#define PORTA_OUTSET _SFR_MEM8(0x0605) -#define PORTA_OUTCLR _SFR_MEM8(0x0606) -#define PORTA_OUTTGL _SFR_MEM8(0x0607) -#define PORTA_IN _SFR_MEM8(0x0608) -#define PORTA_INTCTRL _SFR_MEM8(0x0609) -#define PORTA_INT0MASK _SFR_MEM8(0x060A) -#define PORTA_INT1MASK _SFR_MEM8(0x060B) -#define PORTA_INTFLAGS _SFR_MEM8(0x060C) -#define PORTA_REMAP _SFR_MEM8(0x060E) -#define PORTA_PIN0CTRL _SFR_MEM8(0x0610) -#define PORTA_PIN1CTRL _SFR_MEM8(0x0611) -#define PORTA_PIN2CTRL _SFR_MEM8(0x0612) -#define PORTA_PIN3CTRL _SFR_MEM8(0x0613) -#define PORTA_PIN4CTRL _SFR_MEM8(0x0614) -#define PORTA_PIN5CTRL _SFR_MEM8(0x0615) -#define PORTA_PIN6CTRL _SFR_MEM8(0x0616) -#define PORTA_PIN7CTRL _SFR_MEM8(0x0617) - -/* PORT - I/O Ports */ -#define PORTB_DIR _SFR_MEM8(0x0620) -#define PORTB_DIRSET _SFR_MEM8(0x0621) -#define PORTB_DIRCLR _SFR_MEM8(0x0622) -#define PORTB_DIRTGL _SFR_MEM8(0x0623) -#define PORTB_OUT _SFR_MEM8(0x0624) -#define PORTB_OUTSET _SFR_MEM8(0x0625) -#define PORTB_OUTCLR _SFR_MEM8(0x0626) -#define PORTB_OUTTGL _SFR_MEM8(0x0627) -#define PORTB_IN _SFR_MEM8(0x0628) -#define PORTB_INTCTRL _SFR_MEM8(0x0629) -#define PORTB_INT0MASK _SFR_MEM8(0x062A) -#define PORTB_INT1MASK _SFR_MEM8(0x062B) -#define PORTB_INTFLAGS _SFR_MEM8(0x062C) -#define PORTB_REMAP _SFR_MEM8(0x062E) -#define PORTB_PIN0CTRL _SFR_MEM8(0x0630) -#define PORTB_PIN1CTRL _SFR_MEM8(0x0631) -#define PORTB_PIN2CTRL _SFR_MEM8(0x0632) -#define PORTB_PIN3CTRL _SFR_MEM8(0x0633) -#define PORTB_PIN4CTRL _SFR_MEM8(0x0634) -#define PORTB_PIN5CTRL _SFR_MEM8(0x0635) -#define PORTB_PIN6CTRL _SFR_MEM8(0x0636) -#define PORTB_PIN7CTRL _SFR_MEM8(0x0637) - -/* PORT - I/O Ports */ -#define PORTC_DIR _SFR_MEM8(0x0640) -#define PORTC_DIRSET _SFR_MEM8(0x0641) -#define PORTC_DIRCLR _SFR_MEM8(0x0642) -#define PORTC_DIRTGL _SFR_MEM8(0x0643) -#define PORTC_OUT _SFR_MEM8(0x0644) -#define PORTC_OUTSET _SFR_MEM8(0x0645) -#define PORTC_OUTCLR _SFR_MEM8(0x0646) -#define PORTC_OUTTGL _SFR_MEM8(0x0647) -#define PORTC_IN _SFR_MEM8(0x0648) -#define PORTC_INTCTRL _SFR_MEM8(0x0649) -#define PORTC_INT0MASK _SFR_MEM8(0x064A) -#define PORTC_INT1MASK _SFR_MEM8(0x064B) -#define PORTC_INTFLAGS _SFR_MEM8(0x064C) -#define PORTC_REMAP _SFR_MEM8(0x064E) -#define PORTC_PIN0CTRL _SFR_MEM8(0x0650) -#define PORTC_PIN1CTRL _SFR_MEM8(0x0651) -#define PORTC_PIN2CTRL _SFR_MEM8(0x0652) -#define PORTC_PIN3CTRL _SFR_MEM8(0x0653) -#define PORTC_PIN4CTRL _SFR_MEM8(0x0654) -#define PORTC_PIN5CTRL _SFR_MEM8(0x0655) -#define PORTC_PIN6CTRL _SFR_MEM8(0x0656) -#define PORTC_PIN7CTRL _SFR_MEM8(0x0657) - -/* PORT - I/O Ports */ -#define PORTD_DIR _SFR_MEM8(0x0660) -#define PORTD_DIRSET _SFR_MEM8(0x0661) -#define PORTD_DIRCLR _SFR_MEM8(0x0662) -#define PORTD_DIRTGL _SFR_MEM8(0x0663) -#define PORTD_OUT _SFR_MEM8(0x0664) -#define PORTD_OUTSET _SFR_MEM8(0x0665) -#define PORTD_OUTCLR _SFR_MEM8(0x0666) -#define PORTD_OUTTGL _SFR_MEM8(0x0667) -#define PORTD_IN _SFR_MEM8(0x0668) -#define PORTD_INTCTRL _SFR_MEM8(0x0669) -#define PORTD_INT0MASK _SFR_MEM8(0x066A) -#define PORTD_INT1MASK _SFR_MEM8(0x066B) -#define PORTD_INTFLAGS _SFR_MEM8(0x066C) -#define PORTD_REMAP _SFR_MEM8(0x066E) -#define PORTD_PIN0CTRL _SFR_MEM8(0x0670) -#define PORTD_PIN1CTRL _SFR_MEM8(0x0671) -#define PORTD_PIN2CTRL _SFR_MEM8(0x0672) -#define PORTD_PIN3CTRL _SFR_MEM8(0x0673) -#define PORTD_PIN4CTRL _SFR_MEM8(0x0674) -#define PORTD_PIN5CTRL _SFR_MEM8(0x0675) -#define PORTD_PIN6CTRL _SFR_MEM8(0x0676) -#define PORTD_PIN7CTRL _SFR_MEM8(0x0677) - -/* PORT - I/O Ports */ -#define PORTE_DIR _SFR_MEM8(0x0680) -#define PORTE_DIRSET _SFR_MEM8(0x0681) -#define PORTE_DIRCLR _SFR_MEM8(0x0682) -#define PORTE_DIRTGL _SFR_MEM8(0x0683) -#define PORTE_OUT _SFR_MEM8(0x0684) -#define PORTE_OUTSET _SFR_MEM8(0x0685) -#define PORTE_OUTCLR _SFR_MEM8(0x0686) -#define PORTE_OUTTGL _SFR_MEM8(0x0687) -#define PORTE_IN _SFR_MEM8(0x0688) -#define PORTE_INTCTRL _SFR_MEM8(0x0689) -#define PORTE_INT0MASK _SFR_MEM8(0x068A) -#define PORTE_INT1MASK _SFR_MEM8(0x068B) -#define PORTE_INTFLAGS _SFR_MEM8(0x068C) -#define PORTE_REMAP _SFR_MEM8(0x068E) -#define PORTE_PIN0CTRL _SFR_MEM8(0x0690) -#define PORTE_PIN1CTRL _SFR_MEM8(0x0691) -#define PORTE_PIN2CTRL _SFR_MEM8(0x0692) -#define PORTE_PIN3CTRL _SFR_MEM8(0x0693) -#define PORTE_PIN4CTRL _SFR_MEM8(0x0694) -#define PORTE_PIN5CTRL _SFR_MEM8(0x0695) -#define PORTE_PIN6CTRL _SFR_MEM8(0x0696) -#define PORTE_PIN7CTRL _SFR_MEM8(0x0697) - -/* PORT - I/O Ports */ -#define PORTR_DIR _SFR_MEM8(0x07E0) -#define PORTR_DIRSET _SFR_MEM8(0x07E1) -#define PORTR_DIRCLR _SFR_MEM8(0x07E2) -#define PORTR_DIRTGL _SFR_MEM8(0x07E3) -#define PORTR_OUT _SFR_MEM8(0x07E4) -#define PORTR_OUTSET _SFR_MEM8(0x07E5) -#define PORTR_OUTCLR _SFR_MEM8(0x07E6) -#define PORTR_OUTTGL _SFR_MEM8(0x07E7) -#define PORTR_IN _SFR_MEM8(0x07E8) -#define PORTR_INTCTRL _SFR_MEM8(0x07E9) -#define PORTR_INT0MASK _SFR_MEM8(0x07EA) -#define PORTR_INT1MASK _SFR_MEM8(0x07EB) -#define PORTR_INTFLAGS _SFR_MEM8(0x07EC) -#define PORTR_REMAP _SFR_MEM8(0x07EE) -#define PORTR_PIN0CTRL _SFR_MEM8(0x07F0) -#define PORTR_PIN1CTRL _SFR_MEM8(0x07F1) -#define PORTR_PIN2CTRL _SFR_MEM8(0x07F2) -#define PORTR_PIN3CTRL _SFR_MEM8(0x07F3) -#define PORTR_PIN4CTRL _SFR_MEM8(0x07F4) -#define PORTR_PIN5CTRL _SFR_MEM8(0x07F5) -#define PORTR_PIN6CTRL _SFR_MEM8(0x07F6) -#define PORTR_PIN7CTRL _SFR_MEM8(0x07F7) - -/* TC0 - 16-bit Timer/Counter 0 */ -#define TCC0_CTRLA _SFR_MEM8(0x0800) -#define TCC0_CTRLB _SFR_MEM8(0x0801) -#define TCC0_CTRLC _SFR_MEM8(0x0802) -#define TCC0_CTRLD _SFR_MEM8(0x0803) -#define TCC0_CTRLE _SFR_MEM8(0x0804) -#define TCC0_INTCTRLA _SFR_MEM8(0x0806) -#define TCC0_INTCTRLB _SFR_MEM8(0x0807) -#define TCC0_CTRLFCLR _SFR_MEM8(0x0808) -#define TCC0_CTRLFSET _SFR_MEM8(0x0809) -#define TCC0_CTRLGCLR _SFR_MEM8(0x080A) -#define TCC0_CTRLGSET _SFR_MEM8(0x080B) -#define TCC0_INTFLAGS _SFR_MEM8(0x080C) -#define TCC0_TEMP _SFR_MEM8(0x080F) -#define TCC0_CNT _SFR_MEM16(0x0820) -#define TCC0_PER _SFR_MEM16(0x0826) -#define TCC0_CCA _SFR_MEM16(0x0828) -#define TCC0_CCB _SFR_MEM16(0x082A) -#define TCC0_CCC _SFR_MEM16(0x082C) -#define TCC0_CCD _SFR_MEM16(0x082E) -#define TCC0_PERBUF _SFR_MEM16(0x0836) -#define TCC0_CCABUF _SFR_MEM16(0x0838) -#define TCC0_CCBBUF _SFR_MEM16(0x083A) -#define TCC0_CCCBUF _SFR_MEM16(0x083C) -#define TCC0_CCDBUF _SFR_MEM16(0x083E) - -/* TC2 - 16-bit Timer/Counter type 2 */ -#define TCC2_CTRLA _SFR_MEM8(0x0800) -#define TCC2_CTRLB _SFR_MEM8(0x0801) -#define TCC2_CTRLC _SFR_MEM8(0x0802) -#define TCC2_CTRLE _SFR_MEM8(0x0804) -#define TCC2_INTCTRLA _SFR_MEM8(0x0806) -#define TCC2_INTCTRLB _SFR_MEM8(0x0807) -#define TCC2_CTRLF _SFR_MEM8(0x0809) -#define TCC2_INTFLAGS _SFR_MEM8(0x080C) -#define TCC2_LCNT _SFR_MEM8(0x0820) -#define TCC2_HCNT _SFR_MEM8(0x0821) -#define TCC2_LPER _SFR_MEM8(0x0826) -#define TCC2_HPER _SFR_MEM8(0x0827) -#define TCC2_LCMPA _SFR_MEM8(0x0828) -#define TCC2_HCMPA _SFR_MEM8(0x0829) -#define TCC2_LCMPB _SFR_MEM8(0x082A) -#define TCC2_HCMPB _SFR_MEM8(0x082B) -#define TCC2_LCMPC _SFR_MEM8(0x082C) -#define TCC2_HCMPC _SFR_MEM8(0x082D) -#define TCC2_LCMPD _SFR_MEM8(0x082E) -#define TCC2_HCMPD _SFR_MEM8(0x082F) - -/* TC1 - 16-bit Timer/Counter 1 */ -#define TCC1_CTRLA _SFR_MEM8(0x0840) -#define TCC1_CTRLB _SFR_MEM8(0x0841) -#define TCC1_CTRLC _SFR_MEM8(0x0842) -#define TCC1_CTRLD _SFR_MEM8(0x0843) -#define TCC1_CTRLE _SFR_MEM8(0x0844) -#define TCC1_INTCTRLA _SFR_MEM8(0x0846) -#define TCC1_INTCTRLB _SFR_MEM8(0x0847) -#define TCC1_CTRLFCLR _SFR_MEM8(0x0848) -#define TCC1_CTRLFSET _SFR_MEM8(0x0849) -#define TCC1_CTRLGCLR _SFR_MEM8(0x084A) -#define TCC1_CTRLGSET _SFR_MEM8(0x084B) -#define TCC1_INTFLAGS _SFR_MEM8(0x084C) -#define TCC1_TEMP _SFR_MEM8(0x084F) -#define TCC1_CNT _SFR_MEM16(0x0860) -#define TCC1_PER _SFR_MEM16(0x0866) -#define TCC1_CCA _SFR_MEM16(0x0868) -#define TCC1_CCB _SFR_MEM16(0x086A) -#define TCC1_PERBUF _SFR_MEM16(0x0876) -#define TCC1_CCABUF _SFR_MEM16(0x0878) -#define TCC1_CCBBUF _SFR_MEM16(0x087A) - -/* AWEX - Advanced Waveform Extension */ -#define AWEXC_CTRL _SFR_MEM8(0x0880) -#define AWEXC_FDEMASK _SFR_MEM8(0x0882) -#define AWEXC_FDCTRL _SFR_MEM8(0x0883) -#define AWEXC_STATUS _SFR_MEM8(0x0884) -#define AWEXC_STATUSSET _SFR_MEM8(0x0885) -#define AWEXC_DTBOTH _SFR_MEM8(0x0886) -#define AWEXC_DTBOTHBUF _SFR_MEM8(0x0887) -#define AWEXC_DTLS _SFR_MEM8(0x0888) -#define AWEXC_DTHS _SFR_MEM8(0x0889) -#define AWEXC_DTLSBUF _SFR_MEM8(0x088A) -#define AWEXC_DTHSBUF _SFR_MEM8(0x088B) -#define AWEXC_OUTOVEN _SFR_MEM8(0x088C) - -/* HIRES - High-Resolution Extension */ -#define HIRESC_CTRLA _SFR_MEM8(0x0890) - -/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ -#define USARTC0_DATA _SFR_MEM8(0x08A0) -#define USARTC0_STATUS _SFR_MEM8(0x08A1) -#define USARTC0_CTRLA _SFR_MEM8(0x08A3) -#define USARTC0_CTRLB _SFR_MEM8(0x08A4) -#define USARTC0_CTRLC _SFR_MEM8(0x08A5) -#define USARTC0_BAUDCTRLA _SFR_MEM8(0x08A6) -#define USARTC0_BAUDCTRLB _SFR_MEM8(0x08A7) - -/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ -#define USARTC1_DATA _SFR_MEM8(0x08B0) -#define USARTC1_STATUS _SFR_MEM8(0x08B1) -#define USARTC1_CTRLA _SFR_MEM8(0x08B3) -#define USARTC1_CTRLB _SFR_MEM8(0x08B4) -#define USARTC1_CTRLC _SFR_MEM8(0x08B5) -#define USARTC1_BAUDCTRLA _SFR_MEM8(0x08B6) -#define USARTC1_BAUDCTRLB _SFR_MEM8(0x08B7) - -/* SPI - Serial Peripheral Interface */ -#define SPIC_CTRL _SFR_MEM8(0x08C0) -#define SPIC_INTCTRL _SFR_MEM8(0x08C1) -#define SPIC_STATUS _SFR_MEM8(0x08C2) -#define SPIC_DATA _SFR_MEM8(0x08C3) - -/* IRCOM - IR Communication Module */ -#define IRCOM_CTRL _SFR_MEM8(0x08F8) -#define IRCOM_TXPLCTRL _SFR_MEM8(0x08F9) -#define IRCOM_RXPLCTRL _SFR_MEM8(0x08FA) - -/* TC0 - 16-bit Timer/Counter 0 */ -#define TCD0_CTRLA _SFR_MEM8(0x0900) -#define TCD0_CTRLB _SFR_MEM8(0x0901) -#define TCD0_CTRLC _SFR_MEM8(0x0902) -#define TCD0_CTRLD _SFR_MEM8(0x0903) -#define TCD0_CTRLE _SFR_MEM8(0x0904) -#define TCD0_INTCTRLA _SFR_MEM8(0x0906) -#define TCD0_INTCTRLB _SFR_MEM8(0x0907) -#define TCD0_CTRLFCLR _SFR_MEM8(0x0908) -#define TCD0_CTRLFSET _SFR_MEM8(0x0909) -#define TCD0_CTRLGCLR _SFR_MEM8(0x090A) -#define TCD0_CTRLGSET _SFR_MEM8(0x090B) -#define TCD0_INTFLAGS _SFR_MEM8(0x090C) -#define TCD0_TEMP _SFR_MEM8(0x090F) -#define TCD0_CNT _SFR_MEM16(0x0920) -#define TCD0_PER _SFR_MEM16(0x0926) -#define TCD0_CCA _SFR_MEM16(0x0928) -#define TCD0_CCB _SFR_MEM16(0x092A) -#define TCD0_CCC _SFR_MEM16(0x092C) -#define TCD0_CCD _SFR_MEM16(0x092E) -#define TCD0_PERBUF _SFR_MEM16(0x0936) -#define TCD0_CCABUF _SFR_MEM16(0x0938) -#define TCD0_CCBBUF _SFR_MEM16(0x093A) -#define TCD0_CCCBUF _SFR_MEM16(0x093C) -#define TCD0_CCDBUF _SFR_MEM16(0x093E) - -/* TC2 - 16-bit Timer/Counter type 2 */ -#define TCD2_CTRLA _SFR_MEM8(0x0900) -#define TCD2_CTRLB _SFR_MEM8(0x0901) -#define TCD2_CTRLC _SFR_MEM8(0x0902) -#define TCD2_CTRLE _SFR_MEM8(0x0904) -#define TCD2_INTCTRLA _SFR_MEM8(0x0906) -#define TCD2_INTCTRLB _SFR_MEM8(0x0907) -#define TCD2_CTRLF _SFR_MEM8(0x0909) -#define TCD2_INTFLAGS _SFR_MEM8(0x090C) -#define TCD2_LCNT _SFR_MEM8(0x0920) -#define TCD2_HCNT _SFR_MEM8(0x0921) -#define TCD2_LPER _SFR_MEM8(0x0926) -#define TCD2_HPER _SFR_MEM8(0x0927) -#define TCD2_LCMPA _SFR_MEM8(0x0928) -#define TCD2_HCMPA _SFR_MEM8(0x0929) -#define TCD2_LCMPB _SFR_MEM8(0x092A) -#define TCD2_HCMPB _SFR_MEM8(0x092B) -#define TCD2_LCMPC _SFR_MEM8(0x092C) -#define TCD2_HCMPC _SFR_MEM8(0x092D) -#define TCD2_LCMPD _SFR_MEM8(0x092E) -#define TCD2_HCMPD _SFR_MEM8(0x092F) - -/* TC1 - 16-bit Timer/Counter 1 */ -#define TCD1_CTRLA _SFR_MEM8(0x0940) -#define TCD1_CTRLB _SFR_MEM8(0x0941) -#define TCD1_CTRLC _SFR_MEM8(0x0942) -#define TCD1_CTRLD _SFR_MEM8(0x0943) -#define TCD1_CTRLE _SFR_MEM8(0x0944) -#define TCD1_INTCTRLA _SFR_MEM8(0x0946) -#define TCD1_INTCTRLB _SFR_MEM8(0x0947) -#define TCD1_CTRLFCLR _SFR_MEM8(0x0948) -#define TCD1_CTRLFSET _SFR_MEM8(0x0949) -#define TCD1_CTRLGCLR _SFR_MEM8(0x094A) -#define TCD1_CTRLGSET _SFR_MEM8(0x094B) -#define TCD1_INTFLAGS _SFR_MEM8(0x094C) -#define TCD1_TEMP _SFR_MEM8(0x094F) -#define TCD1_CNT _SFR_MEM16(0x0960) -#define TCD1_PER _SFR_MEM16(0x0966) -#define TCD1_CCA _SFR_MEM16(0x0968) -#define TCD1_CCB _SFR_MEM16(0x096A) -#define TCD1_PERBUF _SFR_MEM16(0x0976) -#define TCD1_CCABUF _SFR_MEM16(0x0978) -#define TCD1_CCBBUF _SFR_MEM16(0x097A) - -/* HIRES - High-Resolution Extension */ -#define HIRESD_CTRLA _SFR_MEM8(0x0990) - -/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ -#define USARTD0_DATA _SFR_MEM8(0x09A0) -#define USARTD0_STATUS _SFR_MEM8(0x09A1) -#define USARTD0_CTRLA _SFR_MEM8(0x09A3) -#define USARTD0_CTRLB _SFR_MEM8(0x09A4) -#define USARTD0_CTRLC _SFR_MEM8(0x09A5) -#define USARTD0_BAUDCTRLA _SFR_MEM8(0x09A6) -#define USARTD0_BAUDCTRLB _SFR_MEM8(0x09A7) - -/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ -#define USARTD1_DATA _SFR_MEM8(0x09B0) -#define USARTD1_STATUS _SFR_MEM8(0x09B1) -#define USARTD1_CTRLA _SFR_MEM8(0x09B3) -#define USARTD1_CTRLB _SFR_MEM8(0x09B4) -#define USARTD1_CTRLC _SFR_MEM8(0x09B5) -#define USARTD1_BAUDCTRLA _SFR_MEM8(0x09B6) -#define USARTD1_BAUDCTRLB _SFR_MEM8(0x09B7) - -/* SPI - Serial Peripheral Interface */ -#define SPID_CTRL _SFR_MEM8(0x09C0) -#define SPID_INTCTRL _SFR_MEM8(0x09C1) -#define SPID_STATUS _SFR_MEM8(0x09C2) -#define SPID_DATA _SFR_MEM8(0x09C3) - -/* TC0 - 16-bit Timer/Counter 0 */ -#define TCE0_CTRLA _SFR_MEM8(0x0A00) -#define TCE0_CTRLB _SFR_MEM8(0x0A01) -#define TCE0_CTRLC _SFR_MEM8(0x0A02) -#define TCE0_CTRLD _SFR_MEM8(0x0A03) -#define TCE0_CTRLE _SFR_MEM8(0x0A04) -#define TCE0_INTCTRLA _SFR_MEM8(0x0A06) -#define TCE0_INTCTRLB _SFR_MEM8(0x0A07) -#define TCE0_CTRLFCLR _SFR_MEM8(0x0A08) -#define TCE0_CTRLFSET _SFR_MEM8(0x0A09) -#define TCE0_CTRLGCLR _SFR_MEM8(0x0A0A) -#define TCE0_CTRLGSET _SFR_MEM8(0x0A0B) -#define TCE0_INTFLAGS _SFR_MEM8(0x0A0C) -#define TCE0_TEMP _SFR_MEM8(0x0A0F) -#define TCE0_CNT _SFR_MEM16(0x0A20) -#define TCE0_PER _SFR_MEM16(0x0A26) -#define TCE0_CCA _SFR_MEM16(0x0A28) -#define TCE0_CCB _SFR_MEM16(0x0A2A) -#define TCE0_CCC _SFR_MEM16(0x0A2C) -#define TCE0_CCD _SFR_MEM16(0x0A2E) -#define TCE0_PERBUF _SFR_MEM16(0x0A36) -#define TCE0_CCABUF _SFR_MEM16(0x0A38) -#define TCE0_CCBBUF _SFR_MEM16(0x0A3A) -#define TCE0_CCCBUF _SFR_MEM16(0x0A3C) -#define TCE0_CCDBUF _SFR_MEM16(0x0A3E) - -/* HIRES - High-Resolution Extension */ -#define HIRESE_CTRLA _SFR_MEM8(0x0A90) - -/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ -#define USARTE0_DATA _SFR_MEM8(0x0AA0) -#define USARTE0_STATUS _SFR_MEM8(0x0AA1) -#define USARTE0_CTRLA _SFR_MEM8(0x0AA3) -#define USARTE0_CTRLB _SFR_MEM8(0x0AA4) -#define USARTE0_CTRLC _SFR_MEM8(0x0AA5) -#define USARTE0_BAUDCTRLA _SFR_MEM8(0x0AA6) -#define USARTE0_BAUDCTRLB _SFR_MEM8(0x0AA7) - - - -/*================== Bitfield Definitions ================== */ - -/* VPORT - Virtual Ports */ -/* VPORT.INTFLAGS bit masks and bit positions */ -#define VPORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ -#define VPORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ - -#define VPORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ -#define VPORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ - -/* XOCD - On-Chip Debug System */ -/* OCD.OCDR0 bit masks and bit positions */ -#define OCD_OCDRD_gm 0xFF /* OCDR Dirty group mask. */ -#define OCD_OCDRD_gp 0 /* OCDR Dirty group position. */ -#define OCD_OCDRD0_bm (1<<0) /* OCDR Dirty bit 0 mask. */ -#define OCD_OCDRD0_bp 0 /* OCDR Dirty bit 0 position. */ -#define OCD_OCDRD1_bm (1<<1) /* OCDR Dirty bit 1 mask. */ -#define OCD_OCDRD1_bp 1 /* OCDR Dirty bit 1 position. */ -#define OCD_OCDRD2_bm (1<<2) /* OCDR Dirty bit 2 mask. */ -#define OCD_OCDRD2_bp 2 /* OCDR Dirty bit 2 position. */ -#define OCD_OCDRD3_bm (1<<3) /* OCDR Dirty bit 3 mask. */ -#define OCD_OCDRD3_bp 3 /* OCDR Dirty bit 3 position. */ -#define OCD_OCDRD4_bm (1<<4) /* OCDR Dirty bit 4 mask. */ -#define OCD_OCDRD4_bp 4 /* OCDR Dirty bit 4 position. */ -#define OCD_OCDRD5_bm (1<<5) /* OCDR Dirty bit 5 mask. */ -#define OCD_OCDRD5_bp 5 /* OCDR Dirty bit 5 position. */ -#define OCD_OCDRD6_bm (1<<6) /* OCDR Dirty bit 6 mask. */ -#define OCD_OCDRD6_bp 6 /* OCDR Dirty bit 6 position. */ -#define OCD_OCDRD7_bm (1<<7) /* OCDR Dirty bit 7 mask. */ -#define OCD_OCDRD7_bp 7 /* OCDR Dirty bit 7 position. */ - -/* OCD.OCDR1 bit masks and bit positions */ -/* OCD_OCDRD Predefined. */ -/* OCD_OCDRD Predefined. */ - -/* CPU - CPU */ -/* CPU.CCP bit masks and bit positions */ -#define CPU_CCP_gm 0xFF /* CCP signature group mask. */ -#define CPU_CCP_gp 0 /* CCP signature group position. */ -#define CPU_CCP0_bm (1<<0) /* CCP signature bit 0 mask. */ -#define CPU_CCP0_bp 0 /* CCP signature bit 0 position. */ -#define CPU_CCP1_bm (1<<1) /* CCP signature bit 1 mask. */ -#define CPU_CCP1_bp 1 /* CCP signature bit 1 position. */ -#define CPU_CCP2_bm (1<<2) /* CCP signature bit 2 mask. */ -#define CPU_CCP2_bp 2 /* CCP signature bit 2 position. */ -#define CPU_CCP3_bm (1<<3) /* CCP signature bit 3 mask. */ -#define CPU_CCP3_bp 3 /* CCP signature bit 3 position. */ -#define CPU_CCP4_bm (1<<4) /* CCP signature bit 4 mask. */ -#define CPU_CCP4_bp 4 /* CCP signature bit 4 position. */ -#define CPU_CCP5_bm (1<<5) /* CCP signature bit 5 mask. */ -#define CPU_CCP5_bp 5 /* CCP signature bit 5 position. */ -#define CPU_CCP6_bm (1<<6) /* CCP signature bit 6 mask. */ -#define CPU_CCP6_bp 6 /* CCP signature bit 6 position. */ -#define CPU_CCP7_bm (1<<7) /* CCP signature bit 7 mask. */ -#define CPU_CCP7_bp 7 /* CCP signature bit 7 position. */ - -/* CPU.SREG bit masks and bit positions */ -#define CPU_I_bm 0x80 /* Global Interrupt Enable Flag bit mask. */ -#define CPU_I_bp 7 /* Global Interrupt Enable Flag bit position. */ - -#define CPU_T_bm 0x40 /* Transfer Bit bit mask. */ -#define CPU_T_bp 6 /* Transfer Bit bit position. */ - -#define CPU_H_bm 0x20 /* Half Carry Flag bit mask. */ -#define CPU_H_bp 5 /* Half Carry Flag bit position. */ - -#define CPU_S_bm 0x10 /* N Exclusive Or V Flag bit mask. */ -#define CPU_S_bp 4 /* N Exclusive Or V Flag bit position. */ - -#define CPU_V_bm 0x08 /* Two's Complement Overflow Flag bit mask. */ -#define CPU_V_bp 3 /* Two's Complement Overflow Flag bit position. */ - -#define CPU_N_bm 0x04 /* Negative Flag bit mask. */ -#define CPU_N_bp 2 /* Negative Flag bit position. */ - -#define CPU_Z_bm 0x02 /* Zero Flag bit mask. */ -#define CPU_Z_bp 1 /* Zero Flag bit position. */ - -#define CPU_C_bm 0x01 /* Carry Flag bit mask. */ -#define CPU_C_bp 0 /* Carry Flag bit position. */ - -/* CLK - Clock System */ -/* CLK.CTRL bit masks and bit positions */ -#define CLK_SCLKSEL_gm 0x07 /* System Clock Selection group mask. */ -#define CLK_SCLKSEL_gp 0 /* System Clock Selection group position. */ -#define CLK_SCLKSEL0_bm (1<<0) /* System Clock Selection bit 0 mask. */ -#define CLK_SCLKSEL0_bp 0 /* System Clock Selection bit 0 position. */ -#define CLK_SCLKSEL1_bm (1<<1) /* System Clock Selection bit 1 mask. */ -#define CLK_SCLKSEL1_bp 1 /* System Clock Selection bit 1 position. */ -#define CLK_SCLKSEL2_bm (1<<2) /* System Clock Selection bit 2 mask. */ -#define CLK_SCLKSEL2_bp 2 /* System Clock Selection bit 2 position. */ - -/* CLK.PSCTRL bit masks and bit positions */ -#define CLK_PSADIV_gm 0x7C /* Prescaler A Division Factor group mask. */ -#define CLK_PSADIV_gp 2 /* Prescaler A Division Factor group position. */ -#define CLK_PSADIV0_bm (1<<2) /* Prescaler A Division Factor bit 0 mask. */ -#define CLK_PSADIV0_bp 2 /* Prescaler A Division Factor bit 0 position. */ -#define CLK_PSADIV1_bm (1<<3) /* Prescaler A Division Factor bit 1 mask. */ -#define CLK_PSADIV1_bp 3 /* Prescaler A Division Factor bit 1 position. */ -#define CLK_PSADIV2_bm (1<<4) /* Prescaler A Division Factor bit 2 mask. */ -#define CLK_PSADIV2_bp 4 /* Prescaler A Division Factor bit 2 position. */ -#define CLK_PSADIV3_bm (1<<5) /* Prescaler A Division Factor bit 3 mask. */ -#define CLK_PSADIV3_bp 5 /* Prescaler A Division Factor bit 3 position. */ -#define CLK_PSADIV4_bm (1<<6) /* Prescaler A Division Factor bit 4 mask. */ -#define CLK_PSADIV4_bp 6 /* Prescaler A Division Factor bit 4 position. */ - -#define CLK_PSBCDIV_gm 0x03 /* Prescaler B and C Division factor group mask. */ -#define CLK_PSBCDIV_gp 0 /* Prescaler B and C Division factor group position. */ -#define CLK_PSBCDIV0_bm (1<<0) /* Prescaler B and C Division factor bit 0 mask. */ -#define CLK_PSBCDIV0_bp 0 /* Prescaler B and C Division factor bit 0 position. */ -#define CLK_PSBCDIV1_bm (1<<1) /* Prescaler B and C Division factor bit 1 mask. */ -#define CLK_PSBCDIV1_bp 1 /* Prescaler B and C Division factor bit 1 position. */ - -/* CLK.LOCK bit masks and bit positions */ -#define CLK_LOCK_bm 0x01 /* Clock System Lock bit mask. */ -#define CLK_LOCK_bp 0 /* Clock System Lock bit position. */ - -/* CLK.RTCCTRL bit masks and bit positions */ -#define CLK_RTCSRC_gm 0x0E /* Clock Source group mask. */ -#define CLK_RTCSRC_gp 1 /* Clock Source group position. */ -#define CLK_RTCSRC0_bm (1<<1) /* Clock Source bit 0 mask. */ -#define CLK_RTCSRC0_bp 1 /* Clock Source bit 0 position. */ -#define CLK_RTCSRC1_bm (1<<2) /* Clock Source bit 1 mask. */ -#define CLK_RTCSRC1_bp 2 /* Clock Source bit 1 position. */ -#define CLK_RTCSRC2_bm (1<<3) /* Clock Source bit 2 mask. */ -#define CLK_RTCSRC2_bp 3 /* Clock Source bit 2 position. */ - -#define CLK_RTCEN_bm 0x01 /* Clock Source Enable bit mask. */ -#define CLK_RTCEN_bp 0 /* Clock Source Enable bit position. */ - -/* CLK.USBCTRL bit masks and bit positions */ -#define CLK_USBPSDIV_gm 0x38 /* Prescaler Division Factor group mask. */ -#define CLK_USBPSDIV_gp 3 /* Prescaler Division Factor group position. */ -#define CLK_USBPSDIV0_bm (1<<3) /* Prescaler Division Factor bit 0 mask. */ -#define CLK_USBPSDIV0_bp 3 /* Prescaler Division Factor bit 0 position. */ -#define CLK_USBPSDIV1_bm (1<<4) /* Prescaler Division Factor bit 1 mask. */ -#define CLK_USBPSDIV1_bp 4 /* Prescaler Division Factor bit 1 position. */ -#define CLK_USBPSDIV2_bm (1<<5) /* Prescaler Division Factor bit 2 mask. */ -#define CLK_USBPSDIV2_bp 5 /* Prescaler Division Factor bit 2 position. */ - -#define CLK_USBSRC_gm 0x06 /* Clock Source group mask. */ -#define CLK_USBSRC_gp 1 /* Clock Source group position. */ -#define CLK_USBSRC0_bm (1<<1) /* Clock Source bit 0 mask. */ -#define CLK_USBSRC0_bp 1 /* Clock Source bit 0 position. */ -#define CLK_USBSRC1_bm (1<<2) /* Clock Source bit 1 mask. */ -#define CLK_USBSRC1_bp 2 /* Clock Source bit 1 position. */ - -#define CLK_USBSEN_bm 0x01 /* Clock Source Enable bit mask. */ -#define CLK_USBSEN_bp 0 /* Clock Source Enable bit position. */ - -/* PR.PRGEN bit masks and bit positions */ -#define PR_USB_bm 0x40 /* USB bit mask. */ -#define PR_USB_bp 6 /* USB bit position. */ - -#define PR_AES_bm 0x10 /* AES bit mask. */ -#define PR_AES_bp 4 /* AES bit position. */ - -#define PR_EBI_bm 0x08 /* External Bus Interface bit mask. */ -#define PR_EBI_bp 3 /* External Bus Interface bit position. */ - -#define PR_RTC_bm 0x04 /* Real-time Counter bit mask. */ -#define PR_RTC_bp 2 /* Real-time Counter bit position. */ - -#define PR_EVSYS_bm 0x02 /* Event System bit mask. */ -#define PR_EVSYS_bp 1 /* Event System bit position. */ - -#define PR_DMA_bm 0x01 /* DMA-Controller bit mask. */ -#define PR_DMA_bp 0 /* DMA-Controller bit position. */ - -/* PR.PRPA bit masks and bit positions */ -#define PR_DAC_bm 0x04 /* Port A DAC bit mask. */ -#define PR_DAC_bp 2 /* Port A DAC bit position. */ - -#define PR_ADC_bm 0x02 /* Port A ADC bit mask. */ -#define PR_ADC_bp 1 /* Port A ADC bit position. */ - -#define PR_AC_bm 0x01 /* Port A Analog Comparator bit mask. */ -#define PR_AC_bp 0 /* Port A Analog Comparator bit position. */ - -/* PR.PRPB bit masks and bit positions */ -/* PR_DAC Predefined. */ -/* PR_DAC Predefined. */ - -/* PR_ADC Predefined. */ -/* PR_ADC Predefined. */ - -/* PR_AC Predefined. */ -/* PR_AC Predefined. */ - -/* PR.PRPC bit masks and bit positions */ -#define PR_TWI_bm 0x40 /* Port C Two-wire Interface bit mask. */ -#define PR_TWI_bp 6 /* Port C Two-wire Interface bit position. */ - -#define PR_USART1_bm 0x20 /* Port C USART1 bit mask. */ -#define PR_USART1_bp 5 /* Port C USART1 bit position. */ - -#define PR_USART0_bm 0x10 /* Port C USART0 bit mask. */ -#define PR_USART0_bp 4 /* Port C USART0 bit position. */ - -#define PR_SPI_bm 0x08 /* Port C SPI bit mask. */ -#define PR_SPI_bp 3 /* Port C SPI bit position. */ - -#define PR_HIRES_bm 0x04 /* Port C AWEX bit mask. */ -#define PR_HIRES_bp 2 /* Port C AWEX bit position. */ - -#define PR_TC1_bm 0x02 /* Port C Timer/Counter1 bit mask. */ -#define PR_TC1_bp 1 /* Port C Timer/Counter1 bit position. */ - -#define PR_TC0_bm 0x01 /* Port C Timer/Counter0 bit mask. */ -#define PR_TC0_bp 0 /* Port C Timer/Counter0 bit position. */ - -/* PR.PRPD bit masks and bit positions */ -/* PR_TWI Predefined. */ -/* PR_TWI Predefined. */ - -/* PR_USART1 Predefined. */ -/* PR_USART1 Predefined. */ - -/* PR_USART0 Predefined. */ -/* PR_USART0 Predefined. */ - -/* PR_SPI Predefined. */ -/* PR_SPI Predefined. */ - -/* PR_HIRES Predefined. */ -/* PR_HIRES Predefined. */ - -/* PR_TC1 Predefined. */ -/* PR_TC1 Predefined. */ - -/* PR_TC0 Predefined. */ -/* PR_TC0 Predefined. */ - -/* PR.PRPE bit masks and bit positions */ -/* PR_TWI Predefined. */ -/* PR_TWI Predefined. */ - -/* PR_USART1 Predefined. */ -/* PR_USART1 Predefined. */ - -/* PR_USART0 Predefined. */ -/* PR_USART0 Predefined. */ - -/* PR_SPI Predefined. */ -/* PR_SPI Predefined. */ - -/* PR_HIRES Predefined. */ -/* PR_HIRES Predefined. */ - -/* PR_TC1 Predefined. */ -/* PR_TC1 Predefined. */ - -/* PR_TC0 Predefined. */ -/* PR_TC0 Predefined. */ - -/* PR.PRPF bit masks and bit positions */ -/* PR_TWI Predefined. */ -/* PR_TWI Predefined. */ - -/* PR_USART1 Predefined. */ -/* PR_USART1 Predefined. */ - -/* PR_USART0 Predefined. */ -/* PR_USART0 Predefined. */ - -/* PR_SPI Predefined. */ -/* PR_SPI Predefined. */ - -/* PR_HIRES Predefined. */ -/* PR_HIRES Predefined. */ - -/* PR_TC1 Predefined. */ -/* PR_TC1 Predefined. */ - -/* PR_TC0 Predefined. */ -/* PR_TC0 Predefined. */ - -/* SLEEP - Sleep Controller */ -/* SLEEP.CTRL bit masks and bit positions */ -#define SLEEP_SMODE_gm 0x0E /* Sleep Mode group mask. */ -#define SLEEP_SMODE_gp 1 /* Sleep Mode group position. */ -#define SLEEP_SMODE0_bm (1<<1) /* Sleep Mode bit 0 mask. */ -#define SLEEP_SMODE0_bp 1 /* Sleep Mode bit 0 position. */ -#define SLEEP_SMODE1_bm (1<<2) /* Sleep Mode bit 1 mask. */ -#define SLEEP_SMODE1_bp 2 /* Sleep Mode bit 1 position. */ -#define SLEEP_SMODE2_bm (1<<3) /* Sleep Mode bit 2 mask. */ -#define SLEEP_SMODE2_bp 3 /* Sleep Mode bit 2 position. */ - -#define SLEEP_SEN_bm 0x01 /* Sleep Enable bit mask. */ -#define SLEEP_SEN_bp 0 /* Sleep Enable bit position. */ - -/* OSC - Oscillator */ -/* OSC.CTRL bit masks and bit positions */ -#define OSC_PLLEN_bm 0x10 /* PLL Enable bit mask. */ -#define OSC_PLLEN_bp 4 /* PLL Enable bit position. */ - -#define OSC_XOSCEN_bm 0x08 /* External Oscillator Enable bit mask. */ -#define OSC_XOSCEN_bp 3 /* External Oscillator Enable bit position. */ - -#define OSC_RC32KEN_bm 0x04 /* Internal 32.768 kHz RC Oscillator Enable bit mask. */ -#define OSC_RC32KEN_bp 2 /* Internal 32.768 kHz RC Oscillator Enable bit position. */ - -#define OSC_RC32MEN_bm 0x02 /* Internal 32 MHz RC Oscillator Enable bit mask. */ -#define OSC_RC32MEN_bp 1 /* Internal 32 MHz RC Oscillator Enable bit position. */ - -#define OSC_RC2MEN_bm 0x01 /* Internal 2 MHz RC Oscillator Enable bit mask. */ -#define OSC_RC2MEN_bp 0 /* Internal 2 MHz RC Oscillator Enable bit position. */ - -/* OSC.STATUS bit masks and bit positions */ -#define OSC_PLLRDY_bm 0x10 /* PLL Ready bit mask. */ -#define OSC_PLLRDY_bp 4 /* PLL Ready bit position. */ - -#define OSC_XOSCRDY_bm 0x08 /* External Oscillator Ready bit mask. */ -#define OSC_XOSCRDY_bp 3 /* External Oscillator Ready bit position. */ - -#define OSC_RC32KRDY_bm 0x04 /* Internal 32.768 kHz RC Oscillator Ready bit mask. */ -#define OSC_RC32KRDY_bp 2 /* Internal 32.768 kHz RC Oscillator Ready bit position. */ - -#define OSC_RC32MRDY_bm 0x02 /* Internal 32 MHz RC Oscillator Ready bit mask. */ -#define OSC_RC32MRDY_bp 1 /* Internal 32 MHz RC Oscillator Ready bit position. */ - -#define OSC_RC2MRDY_bm 0x01 /* Internal 2 MHz RC Oscillator Ready bit mask. */ -#define OSC_RC2MRDY_bp 0 /* Internal 2 MHz RC Oscillator Ready bit position. */ - -/* OSC.XOSCCTRL bit masks and bit positions */ -#define OSC_FRQRANGE_gm 0xC0 /* Frequency Range group mask. */ -#define OSC_FRQRANGE_gp 6 /* Frequency Range group position. */ -#define OSC_FRQRANGE0_bm (1<<6) /* Frequency Range bit 0 mask. */ -#define OSC_FRQRANGE0_bp 6 /* Frequency Range bit 0 position. */ -#define OSC_FRQRANGE1_bm (1<<7) /* Frequency Range bit 1 mask. */ -#define OSC_FRQRANGE1_bp 7 /* Frequency Range bit 1 position. */ - -#define OSC_X32KLPM_bm 0x20 /* 32.768 kHz XTAL OSC Low-power Mode bit mask. */ -#define OSC_X32KLPM_bp 5 /* 32.768 kHz XTAL OSC Low-power Mode bit position. */ - -#define OSC_XOSCPWR_bm 0x10 /* 16 MHz Crystal Oscillator High Power mode bit mask. */ -#define OSC_XOSCPWR_bp 4 /* 16 MHz Crystal Oscillator High Power mode bit position. */ - -#define OSC_XOSCSEL_gm 0x0F /* External Oscillator Selection and Startup Time group mask. */ -#define OSC_XOSCSEL_gp 0 /* External Oscillator Selection and Startup Time group position. */ -#define OSC_XOSCSEL0_bm (1<<0) /* External Oscillator Selection and Startup Time bit 0 mask. */ -#define OSC_XOSCSEL0_bp 0 /* External Oscillator Selection and Startup Time bit 0 position. */ -#define OSC_XOSCSEL1_bm (1<<1) /* External Oscillator Selection and Startup Time bit 1 mask. */ -#define OSC_XOSCSEL1_bp 1 /* External Oscillator Selection and Startup Time bit 1 position. */ -#define OSC_XOSCSEL2_bm (1<<2) /* External Oscillator Selection and Startup Time bit 2 mask. */ -#define OSC_XOSCSEL2_bp 2 /* External Oscillator Selection and Startup Time bit 2 position. */ -#define OSC_XOSCSEL3_bm (1<<3) /* External Oscillator Selection and Startup Time bit 3 mask. */ -#define OSC_XOSCSEL3_bp 3 /* External Oscillator Selection and Startup Time bit 3 position. */ - -/* OSC.XOSCFAIL bit masks and bit positions */ -#define OSC_PLLFDIF_bm 0x08 /* PLL Failure Detection Interrupt Flag bit mask. */ -#define OSC_PLLFDIF_bp 3 /* PLL Failure Detection Interrupt Flag bit position. */ - -#define OSC_PLLFDEN_bm 0x04 /* PLL Failure Detection Enable bit mask. */ -#define OSC_PLLFDEN_bp 2 /* PLL Failure Detection Enable bit position. */ - -#define OSC_XOSCFDIF_bm 0x02 /* XOSC Failure Detection Interrupt Flag bit mask. */ -#define OSC_XOSCFDIF_bp 1 /* XOSC Failure Detection Interrupt Flag bit position. */ - -#define OSC_XOSCFDEN_bm 0x01 /* XOSC Failure Detection Enable bit mask. */ -#define OSC_XOSCFDEN_bp 0 /* XOSC Failure Detection Enable bit position. */ - -/* OSC.PLLCTRL bit masks and bit positions */ -#define OSC_PLLSRC_gm 0xC0 /* Clock Source group mask. */ -#define OSC_PLLSRC_gp 6 /* Clock Source group position. */ -#define OSC_PLLSRC0_bm (1<<6) /* Clock Source bit 0 mask. */ -#define OSC_PLLSRC0_bp 6 /* Clock Source bit 0 position. */ -#define OSC_PLLSRC1_bm (1<<7) /* Clock Source bit 1 mask. */ -#define OSC_PLLSRC1_bp 7 /* Clock Source bit 1 position. */ - -#define OSC_PLLDIV_bm 0x20 /* Divide by 2 bit mask. */ -#define OSC_PLLDIV_bp 5 /* Divide by 2 bit position. */ - -#define OSC_PLLFAC_gm 0x1F /* Multiplication Factor group mask. */ -#define OSC_PLLFAC_gp 0 /* Multiplication Factor group position. */ -#define OSC_PLLFAC0_bm (1<<0) /* Multiplication Factor bit 0 mask. */ -#define OSC_PLLFAC0_bp 0 /* Multiplication Factor bit 0 position. */ -#define OSC_PLLFAC1_bm (1<<1) /* Multiplication Factor bit 1 mask. */ -#define OSC_PLLFAC1_bp 1 /* Multiplication Factor bit 1 position. */ -#define OSC_PLLFAC2_bm (1<<2) /* Multiplication Factor bit 2 mask. */ -#define OSC_PLLFAC2_bp 2 /* Multiplication Factor bit 2 position. */ -#define OSC_PLLFAC3_bm (1<<3) /* Multiplication Factor bit 3 mask. */ -#define OSC_PLLFAC3_bp 3 /* Multiplication Factor bit 3 position. */ -#define OSC_PLLFAC4_bm (1<<4) /* Multiplication Factor bit 4 mask. */ -#define OSC_PLLFAC4_bp 4 /* Multiplication Factor bit 4 position. */ - -/* OSC.DFLLCTRL bit masks and bit positions */ -#define OSC_RC32MCREF_gm 0x06 /* 32 MHz DFLL Calibration Reference group mask. */ -#define OSC_RC32MCREF_gp 1 /* 32 MHz DFLL Calibration Reference group position. */ -#define OSC_RC32MCREF0_bm (1<<1) /* 32 MHz DFLL Calibration Reference bit 0 mask. */ -#define OSC_RC32MCREF0_bp 1 /* 32 MHz DFLL Calibration Reference bit 0 position. */ -#define OSC_RC32MCREF1_bm (1<<2) /* 32 MHz DFLL Calibration Reference bit 1 mask. */ -#define OSC_RC32MCREF1_bp 2 /* 32 MHz DFLL Calibration Reference bit 1 position. */ - -#define OSC_RC2MCREF_bm 0x01 /* 2 MHz DFLL Calibration Reference bit mask. */ -#define OSC_RC2MCREF_bp 0 /* 2 MHz DFLL Calibration Reference bit position. */ - -/* DFLL - DFLL */ -/* DFLL.CTRL bit masks and bit positions */ -#define DFLL_ENABLE_bm 0x01 /* DFLL Enable bit mask. */ -#define DFLL_ENABLE_bp 0 /* DFLL Enable bit position. */ - -/* DFLL.CALA bit masks and bit positions */ -#define DFLL_CALL_gm 0x7F /* DFLL Calibration Value A group mask. */ -#define DFLL_CALL_gp 0 /* DFLL Calibration Value A group position. */ -#define DFLL_CALL0_bm (1<<0) /* DFLL Calibration Value A bit 0 mask. */ -#define DFLL_CALL0_bp 0 /* DFLL Calibration Value A bit 0 position. */ -#define DFLL_CALL1_bm (1<<1) /* DFLL Calibration Value A bit 1 mask. */ -#define DFLL_CALL1_bp 1 /* DFLL Calibration Value A bit 1 position. */ -#define DFLL_CALL2_bm (1<<2) /* DFLL Calibration Value A bit 2 mask. */ -#define DFLL_CALL2_bp 2 /* DFLL Calibration Value A bit 2 position. */ -#define DFLL_CALL3_bm (1<<3) /* DFLL Calibration Value A bit 3 mask. */ -#define DFLL_CALL3_bp 3 /* DFLL Calibration Value A bit 3 position. */ -#define DFLL_CALL4_bm (1<<4) /* DFLL Calibration Value A bit 4 mask. */ -#define DFLL_CALL4_bp 4 /* DFLL Calibration Value A bit 4 position. */ -#define DFLL_CALL5_bm (1<<5) /* DFLL Calibration Value A bit 5 mask. */ -#define DFLL_CALL5_bp 5 /* DFLL Calibration Value A bit 5 position. */ -#define DFLL_CALL6_bm (1<<6) /* DFLL Calibration Value A bit 6 mask. */ -#define DFLL_CALL6_bp 6 /* DFLL Calibration Value A bit 6 position. */ - -/* DFLL.CALB bit masks and bit positions */ -#define DFLL_CALH_gm 0x3F /* DFLL Calibration Value B group mask. */ -#define DFLL_CALH_gp 0 /* DFLL Calibration Value B group position. */ -#define DFLL_CALH0_bm (1<<0) /* DFLL Calibration Value B bit 0 mask. */ -#define DFLL_CALH0_bp 0 /* DFLL Calibration Value B bit 0 position. */ -#define DFLL_CALH1_bm (1<<1) /* DFLL Calibration Value B bit 1 mask. */ -#define DFLL_CALH1_bp 1 /* DFLL Calibration Value B bit 1 position. */ -#define DFLL_CALH2_bm (1<<2) /* DFLL Calibration Value B bit 2 mask. */ -#define DFLL_CALH2_bp 2 /* DFLL Calibration Value B bit 2 position. */ -#define DFLL_CALH3_bm (1<<3) /* DFLL Calibration Value B bit 3 mask. */ -#define DFLL_CALH3_bp 3 /* DFLL Calibration Value B bit 3 position. */ -#define DFLL_CALH4_bm (1<<4) /* DFLL Calibration Value B bit 4 mask. */ -#define DFLL_CALH4_bp 4 /* DFLL Calibration Value B bit 4 position. */ -#define DFLL_CALH5_bm (1<<5) /* DFLL Calibration Value B bit 5 mask. */ -#define DFLL_CALH5_bp 5 /* DFLL Calibration Value B bit 5 position. */ - -/* RST - Reset */ -/* RST.STATUS bit masks and bit positions */ -#define RST_SDRF_bm 0x40 /* Spike Detection Reset Flag bit mask. */ -#define RST_SDRF_bp 6 /* Spike Detection Reset Flag bit position. */ - -#define RST_SRF_bm 0x20 /* Software Reset Flag bit mask. */ -#define RST_SRF_bp 5 /* Software Reset Flag bit position. */ - -#define RST_PDIRF_bm 0x10 /* Programming and Debug Interface Interface Reset Flag bit mask. */ -#define RST_PDIRF_bp 4 /* Programming and Debug Interface Interface Reset Flag bit position. */ - -#define RST_WDRF_bm 0x08 /* Watchdog Reset Flag bit mask. */ -#define RST_WDRF_bp 3 /* Watchdog Reset Flag bit position. */ - -#define RST_BORF_bm 0x04 /* Brown-out Reset Flag bit mask. */ -#define RST_BORF_bp 2 /* Brown-out Reset Flag bit position. */ - -#define RST_EXTRF_bm 0x02 /* External Reset Flag bit mask. */ -#define RST_EXTRF_bp 1 /* External Reset Flag bit position. */ - -#define RST_PORF_bm 0x01 /* Power-on Reset Flag bit mask. */ -#define RST_PORF_bp 0 /* Power-on Reset Flag bit position. */ - -/* RST.CTRL bit masks and bit positions */ -#define RST_SWRST_bm 0x01 /* Software Reset bit mask. */ -#define RST_SWRST_bp 0 /* Software Reset bit position. */ - -/* WDT - Watch-Dog Timer */ -/* WDT.CTRL bit masks and bit positions */ -#define WDT_PER_gm 0x3C /* Period group mask. */ -#define WDT_PER_gp 2 /* Period group position. */ -#define WDT_PER0_bm (1<<2) /* Period bit 0 mask. */ -#define WDT_PER0_bp 2 /* Period bit 0 position. */ -#define WDT_PER1_bm (1<<3) /* Period bit 1 mask. */ -#define WDT_PER1_bp 3 /* Period bit 1 position. */ -#define WDT_PER2_bm (1<<4) /* Period bit 2 mask. */ -#define WDT_PER2_bp 4 /* Period bit 2 position. */ -#define WDT_PER3_bm (1<<5) /* Period bit 3 mask. */ -#define WDT_PER3_bp 5 /* Period bit 3 position. */ - -#define WDT_ENABLE_bm 0x02 /* Enable bit mask. */ -#define WDT_ENABLE_bp 1 /* Enable bit position. */ - -#define WDT_CEN_bm 0x01 /* Change Enable bit mask. */ -#define WDT_CEN_bp 0 /* Change Enable bit position. */ - -/* WDT.WINCTRL bit masks and bit positions */ -#define WDT_WPER_gm 0x3C /* Windowed Mode Period group mask. */ -#define WDT_WPER_gp 2 /* Windowed Mode Period group position. */ -#define WDT_WPER0_bm (1<<2) /* Windowed Mode Period bit 0 mask. */ -#define WDT_WPER0_bp 2 /* Windowed Mode Period bit 0 position. */ -#define WDT_WPER1_bm (1<<3) /* Windowed Mode Period bit 1 mask. */ -#define WDT_WPER1_bp 3 /* Windowed Mode Period bit 1 position. */ -#define WDT_WPER2_bm (1<<4) /* Windowed Mode Period bit 2 mask. */ -#define WDT_WPER2_bp 4 /* Windowed Mode Period bit 2 position. */ -#define WDT_WPER3_bm (1<<5) /* Windowed Mode Period bit 3 mask. */ -#define WDT_WPER3_bp 5 /* Windowed Mode Period bit 3 position. */ - -#define WDT_WEN_bm 0x02 /* Windowed Mode Enable bit mask. */ -#define WDT_WEN_bp 1 /* Windowed Mode Enable bit position. */ - -#define WDT_WCEN_bm 0x01 /* Windowed Mode Change Enable bit mask. */ -#define WDT_WCEN_bp 0 /* Windowed Mode Change Enable bit position. */ - -/* WDT.STATUS bit masks and bit positions */ -#define WDT_SYNCBUSY_bm 0x01 /* Syncronization busy bit mask. */ -#define WDT_SYNCBUSY_bp 0 /* Syncronization busy bit position. */ - -/* MCU - MCU Control */ -/* MCU.MCUCR bit masks and bit positions */ -#define MCU_JTAGD_bm 0x01 /* JTAG Disable bit mask. */ -#define MCU_JTAGD_bp 0 /* JTAG Disable bit position. */ - -/* MCU.ANAINIT bit masks and bit positions */ -#define MCU_STARTUPDLYB_gm 0x0C /* Analog startup delay Port B group mask. */ -#define MCU_STARTUPDLYB_gp 2 /* Analog startup delay Port B group position. */ -#define MCU_STARTUPDLYB0_bm (1<<2) /* Analog startup delay Port B bit 0 mask. */ -#define MCU_STARTUPDLYB0_bp 2 /* Analog startup delay Port B bit 0 position. */ -#define MCU_STARTUPDLYB1_bm (1<<3) /* Analog startup delay Port B bit 1 mask. */ -#define MCU_STARTUPDLYB1_bp 3 /* Analog startup delay Port B bit 1 position. */ - -#define MCU_STARTUPDLYA_gm 0x03 /* Analog startup delay Port A group mask. */ -#define MCU_STARTUPDLYA_gp 0 /* Analog startup delay Port A group position. */ -#define MCU_STARTUPDLYA0_bm (1<<0) /* Analog startup delay Port A bit 0 mask. */ -#define MCU_STARTUPDLYA0_bp 0 /* Analog startup delay Port A bit 0 position. */ -#define MCU_STARTUPDLYA1_bm (1<<1) /* Analog startup delay Port A bit 1 mask. */ -#define MCU_STARTUPDLYA1_bp 1 /* Analog startup delay Port A bit 1 position. */ - -/* MCU.EVSYSLOCK bit masks and bit positions */ -#define MCU_EVSYS1LOCK_bm 0x10 /* Event Channel 4-7 Lock bit mask. */ -#define MCU_EVSYS1LOCK_bp 4 /* Event Channel 4-7 Lock bit position. */ - -#define MCU_EVSYS0LOCK_bm 0x01 /* Event Channel 0-3 Lock bit mask. */ -#define MCU_EVSYS0LOCK_bp 0 /* Event Channel 0-3 Lock bit position. */ - -/* MCU.AWEXLOCK bit masks and bit positions */ -#define MCU_AWEXFLOCK_bm 0x08 /* AWeX on T/C F0 Lock bit mask. */ -#define MCU_AWEXFLOCK_bp 3 /* AWeX on T/C F0 Lock bit position. */ - -#define MCU_AWEXELOCK_bm 0x04 /* AWeX on T/C E0 Lock bit mask. */ -#define MCU_AWEXELOCK_bp 2 /* AWeX on T/C E0 Lock bit position. */ - -#define MCU_AWEXDLOCK_bm 0x02 /* AWeX on T/C D0 Lock bit mask. */ -#define MCU_AWEXDLOCK_bp 1 /* AWeX on T/C D0 Lock bit position. */ - -#define MCU_AWEXCLOCK_bm 0x01 /* AWeX on T/C C0 Lock bit mask. */ -#define MCU_AWEXCLOCK_bp 0 /* AWeX on T/C C0 Lock bit position. */ - -/* PMIC - Programmable Multi-level Interrupt Controller */ -/* PMIC.STATUS bit masks and bit positions */ -#define PMIC_NMIEX_bm 0x80 /* Non-maskable Interrupt Executing bit mask. */ -#define PMIC_NMIEX_bp 7 /* Non-maskable Interrupt Executing bit position. */ - -#define PMIC_HILVLEX_bm 0x04 /* High Level Interrupt Executing bit mask. */ -#define PMIC_HILVLEX_bp 2 /* High Level Interrupt Executing bit position. */ - -#define PMIC_MEDLVLEX_bm 0x02 /* Medium Level Interrupt Executing bit mask. */ -#define PMIC_MEDLVLEX_bp 1 /* Medium Level Interrupt Executing bit position. */ - -#define PMIC_LOLVLEX_bm 0x01 /* Low Level Interrupt Executing bit mask. */ -#define PMIC_LOLVLEX_bp 0 /* Low Level Interrupt Executing bit position. */ - -/* PMIC.INTPRI bit masks and bit positions */ -#define PMIC_INTPRI_gm 0xFF /* Interrupt Priority group mask. */ -#define PMIC_INTPRI_gp 0 /* Interrupt Priority group position. */ -#define PMIC_INTPRI0_bm (1<<0) /* Interrupt Priority bit 0 mask. */ -#define PMIC_INTPRI0_bp 0 /* Interrupt Priority bit 0 position. */ -#define PMIC_INTPRI1_bm (1<<1) /* Interrupt Priority bit 1 mask. */ -#define PMIC_INTPRI1_bp 1 /* Interrupt Priority bit 1 position. */ -#define PMIC_INTPRI2_bm (1<<2) /* Interrupt Priority bit 2 mask. */ -#define PMIC_INTPRI2_bp 2 /* Interrupt Priority bit 2 position. */ -#define PMIC_INTPRI3_bm (1<<3) /* Interrupt Priority bit 3 mask. */ -#define PMIC_INTPRI3_bp 3 /* Interrupt Priority bit 3 position. */ -#define PMIC_INTPRI4_bm (1<<4) /* Interrupt Priority bit 4 mask. */ -#define PMIC_INTPRI4_bp 4 /* Interrupt Priority bit 4 position. */ -#define PMIC_INTPRI5_bm (1<<5) /* Interrupt Priority bit 5 mask. */ -#define PMIC_INTPRI5_bp 5 /* Interrupt Priority bit 5 position. */ -#define PMIC_INTPRI6_bm (1<<6) /* Interrupt Priority bit 6 mask. */ -#define PMIC_INTPRI6_bp 6 /* Interrupt Priority bit 6 position. */ -#define PMIC_INTPRI7_bm (1<<7) /* Interrupt Priority bit 7 mask. */ -#define PMIC_INTPRI7_bp 7 /* Interrupt Priority bit 7 position. */ - -/* PMIC.CTRL bit masks and bit positions */ -#define PMIC_RREN_bm 0x80 /* Round-Robin Priority Enable bit mask. */ -#define PMIC_RREN_bp 7 /* Round-Robin Priority Enable bit position. */ - -#define PMIC_IVSEL_bm 0x40 /* Interrupt Vector Select bit mask. */ -#define PMIC_IVSEL_bp 6 /* Interrupt Vector Select bit position. */ - -#define PMIC_HILVLEN_bm 0x04 /* High Level Enable bit mask. */ -#define PMIC_HILVLEN_bp 2 /* High Level Enable bit position. */ - -#define PMIC_MEDLVLEN_bm 0x02 /* Medium Level Enable bit mask. */ -#define PMIC_MEDLVLEN_bp 1 /* Medium Level Enable bit position. */ - -#define PMIC_LOLVLEN_bm 0x01 /* Low Level Enable bit mask. */ -#define PMIC_LOLVLEN_bp 0 /* Low Level Enable bit position. */ - -/* PORTCFG - Port Configuration */ -/* PORTCFG.VPCTRLA bit masks and bit positions */ -#define PORTCFG_VP1MAP_gm 0xF0 /* Virtual Port 1 Mapping group mask. */ -#define PORTCFG_VP1MAP_gp 4 /* Virtual Port 1 Mapping group position. */ -#define PORTCFG_VP1MAP0_bm (1<<4) /* Virtual Port 1 Mapping bit 0 mask. */ -#define PORTCFG_VP1MAP0_bp 4 /* Virtual Port 1 Mapping bit 0 position. */ -#define PORTCFG_VP1MAP1_bm (1<<5) /* Virtual Port 1 Mapping bit 1 mask. */ -#define PORTCFG_VP1MAP1_bp 5 /* Virtual Port 1 Mapping bit 1 position. */ -#define PORTCFG_VP1MAP2_bm (1<<6) /* Virtual Port 1 Mapping bit 2 mask. */ -#define PORTCFG_VP1MAP2_bp 6 /* Virtual Port 1 Mapping bit 2 position. */ -#define PORTCFG_VP1MAP3_bm (1<<7) /* Virtual Port 1 Mapping bit 3 mask. */ -#define PORTCFG_VP1MAP3_bp 7 /* Virtual Port 1 Mapping bit 3 position. */ - -#define PORTCFG_VP0MAP_gm 0x0F /* Virtual Port 0 Mapping group mask. */ -#define PORTCFG_VP0MAP_gp 0 /* Virtual Port 0 Mapping group position. */ -#define PORTCFG_VP0MAP0_bm (1<<0) /* Virtual Port 0 Mapping bit 0 mask. */ -#define PORTCFG_VP0MAP0_bp 0 /* Virtual Port 0 Mapping bit 0 position. */ -#define PORTCFG_VP0MAP1_bm (1<<1) /* Virtual Port 0 Mapping bit 1 mask. */ -#define PORTCFG_VP0MAP1_bp 1 /* Virtual Port 0 Mapping bit 1 position. */ -#define PORTCFG_VP0MAP2_bm (1<<2) /* Virtual Port 0 Mapping bit 2 mask. */ -#define PORTCFG_VP0MAP2_bp 2 /* Virtual Port 0 Mapping bit 2 position. */ -#define PORTCFG_VP0MAP3_bm (1<<3) /* Virtual Port 0 Mapping bit 3 mask. */ -#define PORTCFG_VP0MAP3_bp 3 /* Virtual Port 0 Mapping bit 3 position. */ - -/* PORTCFG.VPCTRLB bit masks and bit positions */ -#define PORTCFG_VP3MAP_gm 0xF0 /* Virtual Port 3 Mapping group mask. */ -#define PORTCFG_VP3MAP_gp 4 /* Virtual Port 3 Mapping group position. */ -#define PORTCFG_VP3MAP0_bm (1<<4) /* Virtual Port 3 Mapping bit 0 mask. */ -#define PORTCFG_VP3MAP0_bp 4 /* Virtual Port 3 Mapping bit 0 position. */ -#define PORTCFG_VP3MAP1_bm (1<<5) /* Virtual Port 3 Mapping bit 1 mask. */ -#define PORTCFG_VP3MAP1_bp 5 /* Virtual Port 3 Mapping bit 1 position. */ -#define PORTCFG_VP3MAP2_bm (1<<6) /* Virtual Port 3 Mapping bit 2 mask. */ -#define PORTCFG_VP3MAP2_bp 6 /* Virtual Port 3 Mapping bit 2 position. */ -#define PORTCFG_VP3MAP3_bm (1<<7) /* Virtual Port 3 Mapping bit 3 mask. */ -#define PORTCFG_VP3MAP3_bp 7 /* Virtual Port 3 Mapping bit 3 position. */ - -#define PORTCFG_VP2MAP_gm 0x0F /* Virtual Port 2 Mapping group mask. */ -#define PORTCFG_VP2MAP_gp 0 /* Virtual Port 2 Mapping group position. */ -#define PORTCFG_VP2MAP0_bm (1<<0) /* Virtual Port 2 Mapping bit 0 mask. */ -#define PORTCFG_VP2MAP0_bp 0 /* Virtual Port 2 Mapping bit 0 position. */ -#define PORTCFG_VP2MAP1_bm (1<<1) /* Virtual Port 2 Mapping bit 1 mask. */ -#define PORTCFG_VP2MAP1_bp 1 /* Virtual Port 2 Mapping bit 1 position. */ -#define PORTCFG_VP2MAP2_bm (1<<2) /* Virtual Port 2 Mapping bit 2 mask. */ -#define PORTCFG_VP2MAP2_bp 2 /* Virtual Port 2 Mapping bit 2 position. */ -#define PORTCFG_VP2MAP3_bm (1<<3) /* Virtual Port 2 Mapping bit 3 mask. */ -#define PORTCFG_VP2MAP3_bp 3 /* Virtual Port 2 Mapping bit 3 position. */ - -/* PORTCFG.CLKEVOUT bit masks and bit positions */ -#define PORTCFG_CLKOUT_gm 0x03 /* Peripheral Clock Output Port group mask. */ -#define PORTCFG_CLKOUT_gp 0 /* Peripheral Clock Output Port group position. */ -#define PORTCFG_CLKOUT0_bm (1<<0) /* Peripheral Clock Output Port bit 0 mask. */ -#define PORTCFG_CLKOUT0_bp 0 /* Peripheral Clock Output Port bit 0 position. */ -#define PORTCFG_CLKOUT1_bm (1<<1) /* Peripheral Clock Output Port bit 1 mask. */ -#define PORTCFG_CLKOUT1_bp 1 /* Peripheral Clock Output Port bit 1 position. */ - -#define PORTCFG_CLKOUTSEL_gm 0x0C /* Peripheral Clock Output Select group mask. */ -#define PORTCFG_CLKOUTSEL_gp 2 /* Peripheral Clock Output Select group position. */ -#define PORTCFG_CLKOUTSEL0_bm (1<<2) /* Peripheral Clock Output Select bit 0 mask. */ -#define PORTCFG_CLKOUTSEL0_bp 2 /* Peripheral Clock Output Select bit 0 position. */ -#define PORTCFG_CLKOUTSEL1_bm (1<<3) /* Peripheral Clock Output Select bit 1 mask. */ -#define PORTCFG_CLKOUTSEL1_bp 3 /* Peripheral Clock Output Select bit 1 position. */ - -#define PORTCFG_EVOUT_gm 0x30 /* Event Output Port group mask. */ -#define PORTCFG_EVOUT_gp 4 /* Event Output Port group position. */ -#define PORTCFG_EVOUT0_bm (1<<4) /* Event Output Port bit 0 mask. */ -#define PORTCFG_EVOUT0_bp 4 /* Event Output Port bit 0 position. */ -#define PORTCFG_EVOUT1_bm (1<<5) /* Event Output Port bit 1 mask. */ -#define PORTCFG_EVOUT1_bp 5 /* Event Output Port bit 1 position. */ - -#define PORTCFG_RTCOUT_bm 0x40 /* RTC Clock Output bit mask. */ -#define PORTCFG_RTCOUT_bp 6 /* RTC Clock Output bit position. */ - -#define PORTCFG_CLKEVPIN_bm 0x80 /* Peripheral Clock and Event Output pin Select bit mask. */ -#define PORTCFG_CLKEVPIN_bp 7 /* Peripheral Clock and Event Output pin Select bit position. */ - -/* PORTCFG.EBIOUT bit masks and bit positions */ -#define PORTCFG_EBICSOUT_gm 0x03 /* EBI Chip Select Output group mask. */ -#define PORTCFG_EBICSOUT_gp 0 /* EBI Chip Select Output group position. */ -#define PORTCFG_EBICSOUT0_bm (1<<0) /* EBI Chip Select Output bit 0 mask. */ -#define PORTCFG_EBICSOUT0_bp 0 /* EBI Chip Select Output bit 0 position. */ -#define PORTCFG_EBICSOUT1_bm (1<<1) /* EBI Chip Select Output bit 1 mask. */ -#define PORTCFG_EBICSOUT1_bp 1 /* EBI Chip Select Output bit 1 position. */ - -#define PORTCFG_EBIADROUT_gm 0x0C /* EBI Address Output group mask. */ -#define PORTCFG_EBIADROUT_gp 2 /* EBI Address Output group position. */ -#define PORTCFG_EBIADROUT0_bm (1<<2) /* EBI Address Output bit 0 mask. */ -#define PORTCFG_EBIADROUT0_bp 2 /* EBI Address Output bit 0 position. */ -#define PORTCFG_EBIADROUT1_bm (1<<3) /* EBI Address Output bit 1 mask. */ -#define PORTCFG_EBIADROUT1_bp 3 /* EBI Address Output bit 1 position. */ - -/* PORTCFG.EVOUTSEL bit masks and bit positions */ -#define PORTCFG_EVOUTSEL_gm 0x07 /* Event Output Select group mask. */ -#define PORTCFG_EVOUTSEL_gp 0 /* Event Output Select group position. */ -#define PORTCFG_EVOUTSEL0_bm (1<<0) /* Event Output Select bit 0 mask. */ -#define PORTCFG_EVOUTSEL0_bp 0 /* Event Output Select bit 0 position. */ -#define PORTCFG_EVOUTSEL1_bm (1<<1) /* Event Output Select bit 1 mask. */ -#define PORTCFG_EVOUTSEL1_bp 1 /* Event Output Select bit 1 position. */ -#define PORTCFG_EVOUTSEL2_bm (1<<2) /* Event Output Select bit 2 mask. */ -#define PORTCFG_EVOUTSEL2_bp 2 /* Event Output Select bit 2 position. */ - -/* AES - AES Module */ -/* AES.CTRL bit masks and bit positions */ -#define AES_START_bm 0x80 /* Start/Run bit mask. */ -#define AES_START_bp 7 /* Start/Run bit position. */ - -#define AES_AUTO_bm 0x40 /* Auto Start Trigger bit mask. */ -#define AES_AUTO_bp 6 /* Auto Start Trigger bit position. */ - -#define AES_RESET_bm 0x20 /* AES Software Reset bit mask. */ -#define AES_RESET_bp 5 /* AES Software Reset bit position. */ - -#define AES_DECRYPT_bm 0x10 /* Decryption / Direction bit mask. */ -#define AES_DECRYPT_bp 4 /* Decryption / Direction bit position. */ - -#define AES_XOR_bm 0x04 /* State XOR Load Enable bit mask. */ -#define AES_XOR_bp 2 /* State XOR Load Enable bit position. */ - -/* AES.STATUS bit masks and bit positions */ -#define AES_ERROR_bm 0x80 /* AES Error bit mask. */ -#define AES_ERROR_bp 7 /* AES Error bit position. */ - -#define AES_SRIF_bm 0x01 /* State Ready Interrupt Flag bit mask. */ -#define AES_SRIF_bp 0 /* State Ready Interrupt Flag bit position. */ - -/* AES.INTCTRL bit masks and bit positions */ -#define AES_INTLVL_gm 0x03 /* Interrupt level group mask. */ -#define AES_INTLVL_gp 0 /* Interrupt level group position. */ -#define AES_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */ -#define AES_INTLVL0_bp 0 /* Interrupt level bit 0 position. */ -#define AES_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */ -#define AES_INTLVL1_bp 1 /* Interrupt level bit 1 position. */ - -/* CRC - Cyclic Redundancy Checker */ -/* CRC.CTRL bit masks and bit positions */ -#define CRC_RESET_gm 0xC0 /* Reset group mask. */ -#define CRC_RESET_gp 6 /* Reset group position. */ -#define CRC_RESET0_bm (1<<6) /* Reset bit 0 mask. */ -#define CRC_RESET0_bp 6 /* Reset bit 0 position. */ -#define CRC_RESET1_bm (1<<7) /* Reset bit 1 mask. */ -#define CRC_RESET1_bp 7 /* Reset bit 1 position. */ - -#define CRC_CRC32_bm 0x20 /* CRC Mode bit mask. */ -#define CRC_CRC32_bp 5 /* CRC Mode bit position. */ - -#define CRC_SOURCE_gm 0x0F /* Input Source group mask. */ -#define CRC_SOURCE_gp 0 /* Input Source group position. */ -#define CRC_SOURCE0_bm (1<<0) /* Input Source bit 0 mask. */ -#define CRC_SOURCE0_bp 0 /* Input Source bit 0 position. */ -#define CRC_SOURCE1_bm (1<<1) /* Input Source bit 1 mask. */ -#define CRC_SOURCE1_bp 1 /* Input Source bit 1 position. */ -#define CRC_SOURCE2_bm (1<<2) /* Input Source bit 2 mask. */ -#define CRC_SOURCE2_bp 2 /* Input Source bit 2 position. */ -#define CRC_SOURCE3_bm (1<<3) /* Input Source bit 3 mask. */ -#define CRC_SOURCE3_bp 3 /* Input Source bit 3 position. */ - -/* CRC.STATUS bit masks and bit positions */ -#define CRC_ZERO_bm 0x02 /* Zero detection bit mask. */ -#define CRC_ZERO_bp 1 /* Zero detection bit position. */ - -#define CRC_BUSY_bm 0x01 /* Busy bit mask. */ -#define CRC_BUSY_bp 0 /* Busy bit position. */ - -/* DMA - DMA Controller */ -/* DMA_CH.CTRLA bit masks and bit positions */ -#define DMA_CH_ENABLE_bm 0x80 /* Channel Enable bit mask. */ -#define DMA_CH_ENABLE_bp 7 /* Channel Enable bit position. */ - -#define DMA_CH_RESET_bm 0x40 /* Channel Software Reset bit mask. */ -#define DMA_CH_RESET_bp 6 /* Channel Software Reset bit position. */ - -#define DMA_CH_REPEAT_bm 0x20 /* Channel Repeat Mode bit mask. */ -#define DMA_CH_REPEAT_bp 5 /* Channel Repeat Mode bit position. */ - -#define DMA_CH_TRFREQ_bm 0x10 /* Channel Transfer Request bit mask. */ -#define DMA_CH_TRFREQ_bp 4 /* Channel Transfer Request bit position. */ - -#define DMA_CH_SINGLE_bm 0x04 /* Channel Single Shot Data Transfer bit mask. */ -#define DMA_CH_SINGLE_bp 2 /* Channel Single Shot Data Transfer bit position. */ - -#define DMA_CH_BURSTLEN_gm 0x03 /* Channel Transfer Mode group mask. */ -#define DMA_CH_BURSTLEN_gp 0 /* Channel Transfer Mode group position. */ -#define DMA_CH_BURSTLEN0_bm (1<<0) /* Channel Transfer Mode bit 0 mask. */ -#define DMA_CH_BURSTLEN0_bp 0 /* Channel Transfer Mode bit 0 position. */ -#define DMA_CH_BURSTLEN1_bm (1<<1) /* Channel Transfer Mode bit 1 mask. */ -#define DMA_CH_BURSTLEN1_bp 1 /* Channel Transfer Mode bit 1 position. */ - -/* DMA_CH.CTRLB bit masks and bit positions */ -#define DMA_CH_CHBUSY_bm 0x80 /* Block Transfer Busy bit mask. */ -#define DMA_CH_CHBUSY_bp 7 /* Block Transfer Busy bit position. */ - -#define DMA_CH_CHPEND_bm 0x40 /* Block Transfer Pending bit mask. */ -#define DMA_CH_CHPEND_bp 6 /* Block Transfer Pending bit position. */ - -#define DMA_CH_ERRIF_bm 0x20 /* Block Transfer Error Interrupt Flag bit mask. */ -#define DMA_CH_ERRIF_bp 5 /* Block Transfer Error Interrupt Flag bit position. */ - -#define DMA_CH_TRNIF_bm 0x10 /* Transaction Complete Interrup Flag bit mask. */ -#define DMA_CH_TRNIF_bp 4 /* Transaction Complete Interrup Flag bit position. */ - -#define DMA_CH_ERRINTLVL_gm 0x0C /* Transfer Error Interrupt Level group mask. */ -#define DMA_CH_ERRINTLVL_gp 2 /* Transfer Error Interrupt Level group position. */ -#define DMA_CH_ERRINTLVL0_bm (1<<2) /* Transfer Error Interrupt Level bit 0 mask. */ -#define DMA_CH_ERRINTLVL0_bp 2 /* Transfer Error Interrupt Level bit 0 position. */ -#define DMA_CH_ERRINTLVL1_bm (1<<3) /* Transfer Error Interrupt Level bit 1 mask. */ -#define DMA_CH_ERRINTLVL1_bp 3 /* Transfer Error Interrupt Level bit 1 position. */ - -#define DMA_CH_TRNINTLVL_gm 0x03 /* Transaction Complete Interrupt Level group mask. */ -#define DMA_CH_TRNINTLVL_gp 0 /* Transaction Complete Interrupt Level group position. */ -#define DMA_CH_TRNINTLVL0_bm (1<<0) /* Transaction Complete Interrupt Level bit 0 mask. */ -#define DMA_CH_TRNINTLVL0_bp 0 /* Transaction Complete Interrupt Level bit 0 position. */ -#define DMA_CH_TRNINTLVL1_bm (1<<1) /* Transaction Complete Interrupt Level bit 1 mask. */ -#define DMA_CH_TRNINTLVL1_bp 1 /* Transaction Complete Interrupt Level bit 1 position. */ - -/* DMA_CH.ADDRCTRL bit masks and bit positions */ -#define DMA_CH_SRCRELOAD_gm 0xC0 /* Channel Source Address Reload group mask. */ -#define DMA_CH_SRCRELOAD_gp 6 /* Channel Source Address Reload group position. */ -#define DMA_CH_SRCRELOAD0_bm (1<<6) /* Channel Source Address Reload bit 0 mask. */ -#define DMA_CH_SRCRELOAD0_bp 6 /* Channel Source Address Reload bit 0 position. */ -#define DMA_CH_SRCRELOAD1_bm (1<<7) /* Channel Source Address Reload bit 1 mask. */ -#define DMA_CH_SRCRELOAD1_bp 7 /* Channel Source Address Reload bit 1 position. */ - -#define DMA_CH_SRCDIR_gm 0x30 /* Channel Source Address Mode group mask. */ -#define DMA_CH_SRCDIR_gp 4 /* Channel Source Address Mode group position. */ -#define DMA_CH_SRCDIR0_bm (1<<4) /* Channel Source Address Mode bit 0 mask. */ -#define DMA_CH_SRCDIR0_bp 4 /* Channel Source Address Mode bit 0 position. */ -#define DMA_CH_SRCDIR1_bm (1<<5) /* Channel Source Address Mode bit 1 mask. */ -#define DMA_CH_SRCDIR1_bp 5 /* Channel Source Address Mode bit 1 position. */ - -#define DMA_CH_DESTRELOAD_gm 0x0C /* Channel Destination Address Reload group mask. */ -#define DMA_CH_DESTRELOAD_gp 2 /* Channel Destination Address Reload group position. */ -#define DMA_CH_DESTRELOAD0_bm (1<<2) /* Channel Destination Address Reload bit 0 mask. */ -#define DMA_CH_DESTRELOAD0_bp 2 /* Channel Destination Address Reload bit 0 position. */ -#define DMA_CH_DESTRELOAD1_bm (1<<3) /* Channel Destination Address Reload bit 1 mask. */ -#define DMA_CH_DESTRELOAD1_bp 3 /* Channel Destination Address Reload bit 1 position. */ - -#define DMA_CH_DESTDIR_gm 0x03 /* Channel Destination Address Mode group mask. */ -#define DMA_CH_DESTDIR_gp 0 /* Channel Destination Address Mode group position. */ -#define DMA_CH_DESTDIR0_bm (1<<0) /* Channel Destination Address Mode bit 0 mask. */ -#define DMA_CH_DESTDIR0_bp 0 /* Channel Destination Address Mode bit 0 position. */ -#define DMA_CH_DESTDIR1_bm (1<<1) /* Channel Destination Address Mode bit 1 mask. */ -#define DMA_CH_DESTDIR1_bp 1 /* Channel Destination Address Mode bit 1 position. */ - -/* DMA_CH.TRIGSRC bit masks and bit positions */ -#define DMA_CH_TRIGSRC_gm 0xFF /* Channel Trigger Source group mask. */ -#define DMA_CH_TRIGSRC_gp 0 /* Channel Trigger Source group position. */ -#define DMA_CH_TRIGSRC0_bm (1<<0) /* Channel Trigger Source bit 0 mask. */ -#define DMA_CH_TRIGSRC0_bp 0 /* Channel Trigger Source bit 0 position. */ -#define DMA_CH_TRIGSRC1_bm (1<<1) /* Channel Trigger Source bit 1 mask. */ -#define DMA_CH_TRIGSRC1_bp 1 /* Channel Trigger Source bit 1 position. */ -#define DMA_CH_TRIGSRC2_bm (1<<2) /* Channel Trigger Source bit 2 mask. */ -#define DMA_CH_TRIGSRC2_bp 2 /* Channel Trigger Source bit 2 position. */ -#define DMA_CH_TRIGSRC3_bm (1<<3) /* Channel Trigger Source bit 3 mask. */ -#define DMA_CH_TRIGSRC3_bp 3 /* Channel Trigger Source bit 3 position. */ -#define DMA_CH_TRIGSRC4_bm (1<<4) /* Channel Trigger Source bit 4 mask. */ -#define DMA_CH_TRIGSRC4_bp 4 /* Channel Trigger Source bit 4 position. */ -#define DMA_CH_TRIGSRC5_bm (1<<5) /* Channel Trigger Source bit 5 mask. */ -#define DMA_CH_TRIGSRC5_bp 5 /* Channel Trigger Source bit 5 position. */ -#define DMA_CH_TRIGSRC6_bm (1<<6) /* Channel Trigger Source bit 6 mask. */ -#define DMA_CH_TRIGSRC6_bp 6 /* Channel Trigger Source bit 6 position. */ -#define DMA_CH_TRIGSRC7_bm (1<<7) /* Channel Trigger Source bit 7 mask. */ -#define DMA_CH_TRIGSRC7_bp 7 /* Channel Trigger Source bit 7 position. */ - -/* DMA.CTRL bit masks and bit positions */ -#define DMA_ENABLE_bm 0x80 /* Enable bit mask. */ -#define DMA_ENABLE_bp 7 /* Enable bit position. */ - -#define DMA_RESET_bm 0x40 /* Software Reset bit mask. */ -#define DMA_RESET_bp 6 /* Software Reset bit position. */ - -#define DMA_DBUFMODE_gm 0x0C /* Double Buffering Mode group mask. */ -#define DMA_DBUFMODE_gp 2 /* Double Buffering Mode group position. */ -#define DMA_DBUFMODE0_bm (1<<2) /* Double Buffering Mode bit 0 mask. */ -#define DMA_DBUFMODE0_bp 2 /* Double Buffering Mode bit 0 position. */ -#define DMA_DBUFMODE1_bm (1<<3) /* Double Buffering Mode bit 1 mask. */ -#define DMA_DBUFMODE1_bp 3 /* Double Buffering Mode bit 1 position. */ - -#define DMA_PRIMODE_gm 0x03 /* Channel Priority Mode group mask. */ -#define DMA_PRIMODE_gp 0 /* Channel Priority Mode group position. */ -#define DMA_PRIMODE0_bm (1<<0) /* Channel Priority Mode bit 0 mask. */ -#define DMA_PRIMODE0_bp 0 /* Channel Priority Mode bit 0 position. */ -#define DMA_PRIMODE1_bm (1<<1) /* Channel Priority Mode bit 1 mask. */ -#define DMA_PRIMODE1_bp 1 /* Channel Priority Mode bit 1 position. */ - -/* DMA.INTFLAGS bit masks and bit positions */ -#define DMA_CH3ERRIF_bm 0x80 /* Channel 3 Block Transfer Error Interrupt Flag bit mask. */ -#define DMA_CH3ERRIF_bp 7 /* Channel 3 Block Transfer Error Interrupt Flag bit position. */ - -#define DMA_CH2ERRIF_bm 0x40 /* Channel 2 Block Transfer Error Interrupt Flag bit mask. */ -#define DMA_CH2ERRIF_bp 6 /* Channel 2 Block Transfer Error Interrupt Flag bit position. */ - -#define DMA_CH1ERRIF_bm 0x20 /* Channel 1 Block Transfer Error Interrupt Flag bit mask. */ -#define DMA_CH1ERRIF_bp 5 /* Channel 1 Block Transfer Error Interrupt Flag bit position. */ - -#define DMA_CH0ERRIF_bm 0x10 /* Channel 0 Block Transfer Error Interrupt Flag bit mask. */ -#define DMA_CH0ERRIF_bp 4 /* Channel 0 Block Transfer Error Interrupt Flag bit position. */ - -#define DMA_CH3TRNIF_bm 0x08 /* Channel 3 Transaction Complete Interrupt Flag bit mask. */ -#define DMA_CH3TRNIF_bp 3 /* Channel 3 Transaction Complete Interrupt Flag bit position. */ - -#define DMA_CH2TRNIF_bm 0x04 /* Channel 2 Transaction Complete Interrupt Flag bit mask. */ -#define DMA_CH2TRNIF_bp 2 /* Channel 2 Transaction Complete Interrupt Flag bit position. */ - -#define DMA_CH1TRNIF_bm 0x02 /* Channel 1 Transaction Complete Interrupt Flag bit mask. */ -#define DMA_CH1TRNIF_bp 1 /* Channel 1 Transaction Complete Interrupt Flag bit position. */ - -#define DMA_CH0TRNIF_bm 0x01 /* Channel 0 Transaction Complete Interrupt Flag bit mask. */ -#define DMA_CH0TRNIF_bp 0 /* Channel 0 Transaction Complete Interrupt Flag bit position. */ - -/* DMA.STATUS bit masks and bit positions */ -#define DMA_CH3BUSY_bm 0x80 /* Channel 3 Block Transfer Busy bit mask. */ -#define DMA_CH3BUSY_bp 7 /* Channel 3 Block Transfer Busy bit position. */ - -#define DMA_CH2BUSY_bm 0x40 /* Channel 2 Block Transfer Busy bit mask. */ -#define DMA_CH2BUSY_bp 6 /* Channel 2 Block Transfer Busy bit position. */ - -#define DMA_CH1BUSY_bm 0x20 /* Channel 1 Block Transfer Busy bit mask. */ -#define DMA_CH1BUSY_bp 5 /* Channel 1 Block Transfer Busy bit position. */ - -#define DMA_CH0BUSY_bm 0x10 /* Channel 0 Block Transfer Busy bit mask. */ -#define DMA_CH0BUSY_bp 4 /* Channel 0 Block Transfer Busy bit position. */ - -#define DMA_CH3PEND_bm 0x08 /* Channel 3 Block Transfer Pending bit mask. */ -#define DMA_CH3PEND_bp 3 /* Channel 3 Block Transfer Pending bit position. */ - -#define DMA_CH2PEND_bm 0x04 /* Channel 2 Block Transfer Pending bit mask. */ -#define DMA_CH2PEND_bp 2 /* Channel 2 Block Transfer Pending bit position. */ - -#define DMA_CH1PEND_bm 0x02 /* Channel 1 Block Transfer Pending bit mask. */ -#define DMA_CH1PEND_bp 1 /* Channel 1 Block Transfer Pending bit position. */ - -#define DMA_CH0PEND_bm 0x01 /* Channel 0 Block Transfer Pending bit mask. */ -#define DMA_CH0PEND_bp 0 /* Channel 0 Block Transfer Pending bit position. */ - -/* EVSYS - Event System */ -/* EVSYS.CH0MUX bit masks and bit positions */ -#define EVSYS_CHMUX_gm 0xFF /* Event Channel 0 Multiplexer group mask. */ -#define EVSYS_CHMUX_gp 0 /* Event Channel 0 Multiplexer group position. */ -#define EVSYS_CHMUX0_bm (1<<0) /* Event Channel 0 Multiplexer bit 0 mask. */ -#define EVSYS_CHMUX0_bp 0 /* Event Channel 0 Multiplexer bit 0 position. */ -#define EVSYS_CHMUX1_bm (1<<1) /* Event Channel 0 Multiplexer bit 1 mask. */ -#define EVSYS_CHMUX1_bp 1 /* Event Channel 0 Multiplexer bit 1 position. */ -#define EVSYS_CHMUX2_bm (1<<2) /* Event Channel 0 Multiplexer bit 2 mask. */ -#define EVSYS_CHMUX2_bp 2 /* Event Channel 0 Multiplexer bit 2 position. */ -#define EVSYS_CHMUX3_bm (1<<3) /* Event Channel 0 Multiplexer bit 3 mask. */ -#define EVSYS_CHMUX3_bp 3 /* Event Channel 0 Multiplexer bit 3 position. */ -#define EVSYS_CHMUX4_bm (1<<4) /* Event Channel 0 Multiplexer bit 4 mask. */ -#define EVSYS_CHMUX4_bp 4 /* Event Channel 0 Multiplexer bit 4 position. */ -#define EVSYS_CHMUX5_bm (1<<5) /* Event Channel 0 Multiplexer bit 5 mask. */ -#define EVSYS_CHMUX5_bp 5 /* Event Channel 0 Multiplexer bit 5 position. */ -#define EVSYS_CHMUX6_bm (1<<6) /* Event Channel 0 Multiplexer bit 6 mask. */ -#define EVSYS_CHMUX6_bp 6 /* Event Channel 0 Multiplexer bit 6 position. */ -#define EVSYS_CHMUX7_bm (1<<7) /* Event Channel 0 Multiplexer bit 7 mask. */ -#define EVSYS_CHMUX7_bp 7 /* Event Channel 0 Multiplexer bit 7 position. */ - -/* EVSYS.CH1MUX bit masks and bit positions */ -/* EVSYS_CHMUX Predefined. */ -/* EVSYS_CHMUX Predefined. */ - -/* EVSYS.CH2MUX bit masks and bit positions */ -/* EVSYS_CHMUX Predefined. */ -/* EVSYS_CHMUX Predefined. */ - -/* EVSYS.CH3MUX bit masks and bit positions */ -/* EVSYS_CHMUX Predefined. */ -/* EVSYS_CHMUX Predefined. */ - -/* EVSYS.CH4MUX bit masks and bit positions */ -/* EVSYS_CHMUX Predefined. */ -/* EVSYS_CHMUX Predefined. */ - -/* EVSYS.CH5MUX bit masks and bit positions */ -/* EVSYS_CHMUX Predefined. */ -/* EVSYS_CHMUX Predefined. */ - -/* EVSYS.CH6MUX bit masks and bit positions */ -/* EVSYS_CHMUX Predefined. */ -/* EVSYS_CHMUX Predefined. */ - -/* EVSYS.CH7MUX bit masks and bit positions */ -/* EVSYS_CHMUX Predefined. */ -/* EVSYS_CHMUX Predefined. */ - -/* EVSYS.CH0CTRL bit masks and bit positions */ -#define EVSYS_QDIRM_gm 0x60 /* Quadrature Decoder Index Recognition Mode group mask. */ -#define EVSYS_QDIRM_gp 5 /* Quadrature Decoder Index Recognition Mode group position. */ -#define EVSYS_QDIRM0_bm (1<<5) /* Quadrature Decoder Index Recognition Mode bit 0 mask. */ -#define EVSYS_QDIRM0_bp 5 /* Quadrature Decoder Index Recognition Mode bit 0 position. */ -#define EVSYS_QDIRM1_bm (1<<6) /* Quadrature Decoder Index Recognition Mode bit 1 mask. */ -#define EVSYS_QDIRM1_bp 6 /* Quadrature Decoder Index Recognition Mode bit 1 position. */ - -#define EVSYS_QDIEN_bm 0x10 /* Quadrature Decoder Index Enable bit mask. */ -#define EVSYS_QDIEN_bp 4 /* Quadrature Decoder Index Enable bit position. */ - -#define EVSYS_QDEN_bm 0x08 /* Quadrature Decoder Enable bit mask. */ -#define EVSYS_QDEN_bp 3 /* Quadrature Decoder Enable bit position. */ - -#define EVSYS_DIGFILT_gm 0x07 /* Digital Filter group mask. */ -#define EVSYS_DIGFILT_gp 0 /* Digital Filter group position. */ -#define EVSYS_DIGFILT0_bm (1<<0) /* Digital Filter bit 0 mask. */ -#define EVSYS_DIGFILT0_bp 0 /* Digital Filter bit 0 position. */ -#define EVSYS_DIGFILT1_bm (1<<1) /* Digital Filter bit 1 mask. */ -#define EVSYS_DIGFILT1_bp 1 /* Digital Filter bit 1 position. */ -#define EVSYS_DIGFILT2_bm (1<<2) /* Digital Filter bit 2 mask. */ -#define EVSYS_DIGFILT2_bp 2 /* Digital Filter bit 2 position. */ - -/* EVSYS.CH1CTRL bit masks and bit positions */ -/* EVSYS_DIGFILT Predefined. */ -/* EVSYS_DIGFILT Predefined. */ - -/* EVSYS.CH2CTRL bit masks and bit positions */ -/* EVSYS_QDIRM Predefined. */ -/* EVSYS_QDIRM Predefined. */ - -/* EVSYS_QDIEN Predefined. */ -/* EVSYS_QDIEN Predefined. */ - -/* EVSYS_QDEN Predefined. */ -/* EVSYS_QDEN Predefined. */ - -/* EVSYS_DIGFILT Predefined. */ -/* EVSYS_DIGFILT Predefined. */ - -/* EVSYS.CH3CTRL bit masks and bit positions */ -/* EVSYS_DIGFILT Predefined. */ -/* EVSYS_DIGFILT Predefined. */ - -/* EVSYS.CH4CTRL bit masks and bit positions */ -/* EVSYS_QDIRM Predefined. */ -/* EVSYS_QDIRM Predefined. */ - -/* EVSYS_QDIEN Predefined. */ -/* EVSYS_QDIEN Predefined. */ - -/* EVSYS_QDEN Predefined. */ -/* EVSYS_QDEN Predefined. */ - -/* EVSYS_DIGFILT Predefined. */ -/* EVSYS_DIGFILT Predefined. */ - -/* EVSYS.CH5CTRL bit masks and bit positions */ -/* EVSYS_DIGFILT Predefined. */ -/* EVSYS_DIGFILT Predefined. */ - -/* EVSYS.CH6CTRL bit masks and bit positions */ -/* EVSYS_DIGFILT Predefined. */ -/* EVSYS_DIGFILT Predefined. */ - -/* EVSYS.CH7CTRL bit masks and bit positions */ -/* EVSYS_DIGFILT Predefined. */ -/* EVSYS_DIGFILT Predefined. */ - -/* NVM - Non Volatile Memory Controller */ -/* NVM.CMD bit masks and bit positions */ -#define NVM_CMD_gm 0x7F /* Command group mask. */ -#define NVM_CMD_gp 0 /* Command group position. */ -#define NVM_CMD0_bm (1<<0) /* Command bit 0 mask. */ -#define NVM_CMD0_bp 0 /* Command bit 0 position. */ -#define NVM_CMD1_bm (1<<1) /* Command bit 1 mask. */ -#define NVM_CMD1_bp 1 /* Command bit 1 position. */ -#define NVM_CMD2_bm (1<<2) /* Command bit 2 mask. */ -#define NVM_CMD2_bp 2 /* Command bit 2 position. */ -#define NVM_CMD3_bm (1<<3) /* Command bit 3 mask. */ -#define NVM_CMD3_bp 3 /* Command bit 3 position. */ -#define NVM_CMD4_bm (1<<4) /* Command bit 4 mask. */ -#define NVM_CMD4_bp 4 /* Command bit 4 position. */ -#define NVM_CMD5_bm (1<<5) /* Command bit 5 mask. */ -#define NVM_CMD5_bp 5 /* Command bit 5 position. */ -#define NVM_CMD6_bm (1<<6) /* Command bit 6 mask. */ -#define NVM_CMD6_bp 6 /* Command bit 6 position. */ - -/* NVM.CTRLA bit masks and bit positions */ -#define NVM_CMDEX_bm 0x01 /* Command Execute bit mask. */ -#define NVM_CMDEX_bp 0 /* Command Execute bit position. */ - -/* NVM.CTRLB bit masks and bit positions */ -#define NVM_EEMAPEN_bm 0x08 /* EEPROM Mapping Enable bit mask. */ -#define NVM_EEMAPEN_bp 3 /* EEPROM Mapping Enable bit position. */ - -#define NVM_FPRM_bm 0x04 /* Flash Power Reduction Enable bit mask. */ -#define NVM_FPRM_bp 2 /* Flash Power Reduction Enable bit position. */ - -#define NVM_EPRM_bm 0x02 /* EEPROM Power Reduction Enable bit mask. */ -#define NVM_EPRM_bp 1 /* EEPROM Power Reduction Enable bit position. */ - -#define NVM_SPMLOCK_bm 0x01 /* SPM Lock bit mask. */ -#define NVM_SPMLOCK_bp 0 /* SPM Lock bit position. */ - -/* NVM.INTCTRL bit masks and bit positions */ -#define NVM_SPMLVL_gm 0x0C /* SPM Interrupt Level group mask. */ -#define NVM_SPMLVL_gp 2 /* SPM Interrupt Level group position. */ -#define NVM_SPMLVL0_bm (1<<2) /* SPM Interrupt Level bit 0 mask. */ -#define NVM_SPMLVL0_bp 2 /* SPM Interrupt Level bit 0 position. */ -#define NVM_SPMLVL1_bm (1<<3) /* SPM Interrupt Level bit 1 mask. */ -#define NVM_SPMLVL1_bp 3 /* SPM Interrupt Level bit 1 position. */ - -#define NVM_EELVL_gm 0x03 /* EEPROM Interrupt Level group mask. */ -#define NVM_EELVL_gp 0 /* EEPROM Interrupt Level group position. */ -#define NVM_EELVL0_bm (1<<0) /* EEPROM Interrupt Level bit 0 mask. */ -#define NVM_EELVL0_bp 0 /* EEPROM Interrupt Level bit 0 position. */ -#define NVM_EELVL1_bm (1<<1) /* EEPROM Interrupt Level bit 1 mask. */ -#define NVM_EELVL1_bp 1 /* EEPROM Interrupt Level bit 1 position. */ - -/* NVM.STATUS bit masks and bit positions */ -#define NVM_NVMBUSY_bm 0x80 /* Non-volatile Memory Busy bit mask. */ -#define NVM_NVMBUSY_bp 7 /* Non-volatile Memory Busy bit position. */ - -#define NVM_FBUSY_bm 0x40 /* Flash Memory Busy bit mask. */ -#define NVM_FBUSY_bp 6 /* Flash Memory Busy bit position. */ - -#define NVM_EELOAD_bm 0x02 /* EEPROM Page Buffer Active Loading bit mask. */ -#define NVM_EELOAD_bp 1 /* EEPROM Page Buffer Active Loading bit position. */ - -#define NVM_FLOAD_bm 0x01 /* Flash Page Buffer Active Loading bit mask. */ -#define NVM_FLOAD_bp 0 /* Flash Page Buffer Active Loading bit position. */ - -/* NVM.LOCKBITS bit masks and bit positions */ -#define NVM_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ -#define NVM_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ -#define NVM_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ -#define NVM_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ -#define NVM_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ -#define NVM_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ - -#define NVM_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ -#define NVM_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ -#define NVM_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ -#define NVM_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ -#define NVM_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ -#define NVM_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ - -#define NVM_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ -#define NVM_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ -#define NVM_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ -#define NVM_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ -#define NVM_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ -#define NVM_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ - -#define NVM_LB_gm 0x03 /* Lock Bits group mask. */ -#define NVM_LB_gp 0 /* Lock Bits group position. */ -#define NVM_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ -#define NVM_LB0_bp 0 /* Lock Bits bit 0 position. */ -#define NVM_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ -#define NVM_LB1_bp 1 /* Lock Bits bit 1 position. */ - -/* ADC - Analog/Digital Converter */ -/* ADC_CH.CTRL bit masks and bit positions */ -#define ADC_CH_START_bm 0x80 /* Channel Start Conversion bit mask. */ -#define ADC_CH_START_bp 7 /* Channel Start Conversion bit position. */ - -#define ADC_CH_GAIN_gm 0x1C /* Gain Factor group mask. */ -#define ADC_CH_GAIN_gp 2 /* Gain Factor group position. */ -#define ADC_CH_GAIN0_bm (1<<2) /* Gain Factor bit 0 mask. */ -#define ADC_CH_GAIN0_bp 2 /* Gain Factor bit 0 position. */ -#define ADC_CH_GAIN1_bm (1<<3) /* Gain Factor bit 1 mask. */ -#define ADC_CH_GAIN1_bp 3 /* Gain Factor bit 1 position. */ -#define ADC_CH_GAIN2_bm (1<<4) /* Gain Factor bit 2 mask. */ -#define ADC_CH_GAIN2_bp 4 /* Gain Factor bit 2 position. */ - -#define ADC_CH_INPUTMODE_gm 0x03 /* Input Mode Select group mask. */ -#define ADC_CH_INPUTMODE_gp 0 /* Input Mode Select group position. */ -#define ADC_CH_INPUTMODE0_bm (1<<0) /* Input Mode Select bit 0 mask. */ -#define ADC_CH_INPUTMODE0_bp 0 /* Input Mode Select bit 0 position. */ -#define ADC_CH_INPUTMODE1_bm (1<<1) /* Input Mode Select bit 1 mask. */ -#define ADC_CH_INPUTMODE1_bp 1 /* Input Mode Select bit 1 position. */ - -/* ADC_CH.MUXCTRL bit masks and bit positions */ -#define ADC_CH_MUXPOS_gm 0x78 /* MUX selection on Positive ADC input group mask. */ -#define ADC_CH_MUXPOS_gp 3 /* MUX selection on Positive ADC input group position. */ -#define ADC_CH_MUXPOS0_bm (1<<3) /* MUX selection on Positive ADC input bit 0 mask. */ -#define ADC_CH_MUXPOS0_bp 3 /* MUX selection on Positive ADC input bit 0 position. */ -#define ADC_CH_MUXPOS1_bm (1<<4) /* MUX selection on Positive ADC input bit 1 mask. */ -#define ADC_CH_MUXPOS1_bp 4 /* MUX selection on Positive ADC input bit 1 position. */ -#define ADC_CH_MUXPOS2_bm (1<<5) /* MUX selection on Positive ADC input bit 2 mask. */ -#define ADC_CH_MUXPOS2_bp 5 /* MUX selection on Positive ADC input bit 2 position. */ -#define ADC_CH_MUXPOS3_bm (1<<6) /* MUX selection on Positive ADC input bit 3 mask. */ -#define ADC_CH_MUXPOS3_bp 6 /* MUX selection on Positive ADC input bit 3 position. */ - -#define ADC_CH_MUXINT_gm 0x78 /* MUX selection on Internal ADC input group mask. */ -#define ADC_CH_MUXINT_gp 3 /* MUX selection on Internal ADC input group position. */ -#define ADC_CH_MUXINT0_bm (1<<3) /* MUX selection on Internal ADC input bit 0 mask. */ -#define ADC_CH_MUXINT0_bp 3 /* MUX selection on Internal ADC input bit 0 position. */ -#define ADC_CH_MUXINT1_bm (1<<4) /* MUX selection on Internal ADC input bit 1 mask. */ -#define ADC_CH_MUXINT1_bp 4 /* MUX selection on Internal ADC input bit 1 position. */ -#define ADC_CH_MUXINT2_bm (1<<5) /* MUX selection on Internal ADC input bit 2 mask. */ -#define ADC_CH_MUXINT2_bp 5 /* MUX selection on Internal ADC input bit 2 position. */ -#define ADC_CH_MUXINT3_bm (1<<6) /* MUX selection on Internal ADC input bit 3 mask. */ -#define ADC_CH_MUXINT3_bp 6 /* MUX selection on Internal ADC input bit 3 position. */ - -#define ADC_CH_MUXNEG_gm 0x07 /* MUX selection on Negative ADC input group mask. */ -#define ADC_CH_MUXNEG_gp 0 /* MUX selection on Negative ADC input group position. */ -#define ADC_CH_MUXNEG0_bm (1<<0) /* MUX selection on Negative ADC input bit 0 mask. */ -#define ADC_CH_MUXNEG0_bp 0 /* MUX selection on Negative ADC input bit 0 position. */ -#define ADC_CH_MUXNEG1_bm (1<<1) /* MUX selection on Negative ADC input bit 1 mask. */ -#define ADC_CH_MUXNEG1_bp 1 /* MUX selection on Negative ADC input bit 1 position. */ -#define ADC_CH_MUXNEG2_bm (1<<2) /* MUX selection on Negative ADC input bit 2 mask. */ -#define ADC_CH_MUXNEG2_bp 2 /* MUX selection on Negative ADC input bit 2 position. */ - -/* ADC_CH.INTCTRL bit masks and bit positions */ -#define ADC_CH_INTMODE_gm 0x0C /* Interrupt Mode group mask. */ -#define ADC_CH_INTMODE_gp 2 /* Interrupt Mode group position. */ -#define ADC_CH_INTMODE0_bm (1<<2) /* Interrupt Mode bit 0 mask. */ -#define ADC_CH_INTMODE0_bp 2 /* Interrupt Mode bit 0 position. */ -#define ADC_CH_INTMODE1_bm (1<<3) /* Interrupt Mode bit 1 mask. */ -#define ADC_CH_INTMODE1_bp 3 /* Interrupt Mode bit 1 position. */ - -#define ADC_CH_INTLVL_gm 0x03 /* Interrupt Level group mask. */ -#define ADC_CH_INTLVL_gp 0 /* Interrupt Level group position. */ -#define ADC_CH_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */ -#define ADC_CH_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */ -#define ADC_CH_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ -#define ADC_CH_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */ - -/* ADC_CH.INTFLAGS bit masks and bit positions */ -#define ADC_CH_CHIF_bm 0x01 /* Channel Interrupt Flag bit mask. */ -#define ADC_CH_CHIF_bp 0 /* Channel Interrupt Flag bit position. */ - -/* ADC_CH.SCAN bit masks and bit positions */ -#define ADC_CH_OFFSET_gm 0xF0 /* Positive MUX setting offset group mask. */ -#define ADC_CH_OFFSET_gp 4 /* Positive MUX setting offset group position. */ -#define ADC_CH_OFFSET0_bm (1<<4) /* Positive MUX setting offset bit 0 mask. */ -#define ADC_CH_OFFSET0_bp 4 /* Positive MUX setting offset bit 0 position. */ -#define ADC_CH_OFFSET1_bm (1<<5) /* Positive MUX setting offset bit 1 mask. */ -#define ADC_CH_OFFSET1_bp 5 /* Positive MUX setting offset bit 1 position. */ -#define ADC_CH_OFFSET2_bm (1<<6) /* Positive MUX setting offset bit 2 mask. */ -#define ADC_CH_OFFSET2_bp 6 /* Positive MUX setting offset bit 2 position. */ -#define ADC_CH_OFFSET3_bm (1<<7) /* Positive MUX setting offset bit 3 mask. */ -#define ADC_CH_OFFSET3_bp 7 /* Positive MUX setting offset bit 3 position. */ - -#define ADC_CH_SCANNUM_gm 0x0F /* Number of Channels included in scan group mask. */ -#define ADC_CH_SCANNUM_gp 0 /* Number of Channels included in scan group position. */ -#define ADC_CH_SCANNUM0_bm (1<<0) /* Number of Channels included in scan bit 0 mask. */ -#define ADC_CH_SCANNUM0_bp 0 /* Number of Channels included in scan bit 0 position. */ -#define ADC_CH_SCANNUM1_bm (1<<1) /* Number of Channels included in scan bit 1 mask. */ -#define ADC_CH_SCANNUM1_bp 1 /* Number of Channels included in scan bit 1 position. */ -#define ADC_CH_SCANNUM2_bm (1<<2) /* Number of Channels included in scan bit 2 mask. */ -#define ADC_CH_SCANNUM2_bp 2 /* Number of Channels included in scan bit 2 position. */ -#define ADC_CH_SCANNUM3_bm (1<<3) /* Number of Channels included in scan bit 3 mask. */ -#define ADC_CH_SCANNUM3_bp 3 /* Number of Channels included in scan bit 3 position. */ - -/* ADC.CTRLA bit masks and bit positions */ -#define ADC_DMASEL_gm 0xC0 /* DMA Selection group mask. */ -#define ADC_DMASEL_gp 6 /* DMA Selection group position. */ -#define ADC_DMASEL0_bm (1<<6) /* DMA Selection bit 0 mask. */ -#define ADC_DMASEL0_bp 6 /* DMA Selection bit 0 position. */ -#define ADC_DMASEL1_bm (1<<7) /* DMA Selection bit 1 mask. */ -#define ADC_DMASEL1_bp 7 /* DMA Selection bit 1 position. */ - -#define ADC_CH3START_bm 0x20 /* Channel 3 Start Conversion bit mask. */ -#define ADC_CH3START_bp 5 /* Channel 3 Start Conversion bit position. */ - -#define ADC_CH2START_bm 0x10 /* Channel 2 Start Conversion bit mask. */ -#define ADC_CH2START_bp 4 /* Channel 2 Start Conversion bit position. */ - -#define ADC_CH1START_bm 0x08 /* Channel 1 Start Conversion bit mask. */ -#define ADC_CH1START_bp 3 /* Channel 1 Start Conversion bit position. */ - -#define ADC_CH0START_bm 0x04 /* Channel 0 Start Conversion bit mask. */ -#define ADC_CH0START_bp 2 /* Channel 0 Start Conversion bit position. */ - -#define ADC_FLUSH_bm 0x02 /* Flush Pipeline bit mask. */ -#define ADC_FLUSH_bp 1 /* Flush Pipeline bit position. */ - -#define ADC_ENABLE_bm 0x01 /* Enable ADC bit mask. */ -#define ADC_ENABLE_bp 0 /* Enable ADC bit position. */ - -/* ADC.CTRLB bit masks and bit positions */ -#define ADC_IMPMODE_bm 0x80 /* Gain Stage Impedance Mode bit mask. */ -#define ADC_IMPMODE_bp 7 /* Gain Stage Impedance Mode bit position. */ - -#define ADC_CURRLIMIT_gm 0x60 /* Current Limitation group mask. */ -#define ADC_CURRLIMIT_gp 5 /* Current Limitation group position. */ -#define ADC_CURRLIMIT0_bm (1<<5) /* Current Limitation bit 0 mask. */ -#define ADC_CURRLIMIT0_bp 5 /* Current Limitation bit 0 position. */ -#define ADC_CURRLIMIT1_bm (1<<6) /* Current Limitation bit 1 mask. */ -#define ADC_CURRLIMIT1_bp 6 /* Current Limitation bit 1 position. */ - -#define ADC_CONMODE_bm 0x10 /* Conversion Mode bit mask. */ -#define ADC_CONMODE_bp 4 /* Conversion Mode bit position. */ - -#define ADC_FREERUN_bm 0x08 /* Free Running Mode Enable bit mask. */ -#define ADC_FREERUN_bp 3 /* Free Running Mode Enable bit position. */ - -#define ADC_RESOLUTION_gm 0x06 /* Result Resolution group mask. */ -#define ADC_RESOLUTION_gp 1 /* Result Resolution group position. */ -#define ADC_RESOLUTION0_bm (1<<1) /* Result Resolution bit 0 mask. */ -#define ADC_RESOLUTION0_bp 1 /* Result Resolution bit 0 position. */ -#define ADC_RESOLUTION1_bm (1<<2) /* Result Resolution bit 1 mask. */ -#define ADC_RESOLUTION1_bp 2 /* Result Resolution bit 1 position. */ - -/* ADC.REFCTRL bit masks and bit positions */ -#define ADC_REFSEL_gm 0x70 /* Reference Selection group mask. */ -#define ADC_REFSEL_gp 4 /* Reference Selection group position. */ -#define ADC_REFSEL0_bm (1<<4) /* Reference Selection bit 0 mask. */ -#define ADC_REFSEL0_bp 4 /* Reference Selection bit 0 position. */ -#define ADC_REFSEL1_bm (1<<5) /* Reference Selection bit 1 mask. */ -#define ADC_REFSEL1_bp 5 /* Reference Selection bit 1 position. */ -#define ADC_REFSEL2_bm (1<<6) /* Reference Selection bit 2 mask. */ -#define ADC_REFSEL2_bp 6 /* Reference Selection bit 2 position. */ - -#define ADC_BANDGAP_bm 0x02 /* Bandgap enable bit mask. */ -#define ADC_BANDGAP_bp 1 /* Bandgap enable bit position. */ - -#define ADC_TEMPREF_bm 0x01 /* Temperature Reference Enable bit mask. */ -#define ADC_TEMPREF_bp 0 /* Temperature Reference Enable bit position. */ - -/* ADC.EVCTRL bit masks and bit positions */ -#define ADC_SWEEP_gm 0xC0 /* Channel Sweep Selection group mask. */ -#define ADC_SWEEP_gp 6 /* Channel Sweep Selection group position. */ -#define ADC_SWEEP0_bm (1<<6) /* Channel Sweep Selection bit 0 mask. */ -#define ADC_SWEEP0_bp 6 /* Channel Sweep Selection bit 0 position. */ -#define ADC_SWEEP1_bm (1<<7) /* Channel Sweep Selection bit 1 mask. */ -#define ADC_SWEEP1_bp 7 /* Channel Sweep Selection bit 1 position. */ - -#define ADC_EVSEL_gm 0x38 /* Event Input Select group mask. */ -#define ADC_EVSEL_gp 3 /* Event Input Select group position. */ -#define ADC_EVSEL0_bm (1<<3) /* Event Input Select bit 0 mask. */ -#define ADC_EVSEL0_bp 3 /* Event Input Select bit 0 position. */ -#define ADC_EVSEL1_bm (1<<4) /* Event Input Select bit 1 mask. */ -#define ADC_EVSEL1_bp 4 /* Event Input Select bit 1 position. */ -#define ADC_EVSEL2_bm (1<<5) /* Event Input Select bit 2 mask. */ -#define ADC_EVSEL2_bp 5 /* Event Input Select bit 2 position. */ - -#define ADC_EVACT_gm 0x07 /* Event Action Select group mask. */ -#define ADC_EVACT_gp 0 /* Event Action Select group position. */ -#define ADC_EVACT0_bm (1<<0) /* Event Action Select bit 0 mask. */ -#define ADC_EVACT0_bp 0 /* Event Action Select bit 0 position. */ -#define ADC_EVACT1_bm (1<<1) /* Event Action Select bit 1 mask. */ -#define ADC_EVACT1_bp 1 /* Event Action Select bit 1 position. */ -#define ADC_EVACT2_bm (1<<2) /* Event Action Select bit 2 mask. */ -#define ADC_EVACT2_bp 2 /* Event Action Select bit 2 position. */ - -/* ADC.PRESCALER bit masks and bit positions */ -#define ADC_PRESCALER_gm 0x07 /* Clock Prescaler Selection group mask. */ -#define ADC_PRESCALER_gp 0 /* Clock Prescaler Selection group position. */ -#define ADC_PRESCALER0_bm (1<<0) /* Clock Prescaler Selection bit 0 mask. */ -#define ADC_PRESCALER0_bp 0 /* Clock Prescaler Selection bit 0 position. */ -#define ADC_PRESCALER1_bm (1<<1) /* Clock Prescaler Selection bit 1 mask. */ -#define ADC_PRESCALER1_bp 1 /* Clock Prescaler Selection bit 1 position. */ -#define ADC_PRESCALER2_bm (1<<2) /* Clock Prescaler Selection bit 2 mask. */ -#define ADC_PRESCALER2_bp 2 /* Clock Prescaler Selection bit 2 position. */ - -/* ADC.INTFLAGS bit masks and bit positions */ -#define ADC_CH3IF_bm 0x08 /* Channel 3 Interrupt Flag bit mask. */ -#define ADC_CH3IF_bp 3 /* Channel 3 Interrupt Flag bit position. */ - -#define ADC_CH2IF_bm 0x04 /* Channel 2 Interrupt Flag bit mask. */ -#define ADC_CH2IF_bp 2 /* Channel 2 Interrupt Flag bit position. */ - -#define ADC_CH1IF_bm 0x02 /* Channel 1 Interrupt Flag bit mask. */ -#define ADC_CH1IF_bp 1 /* Channel 1 Interrupt Flag bit position. */ - -#define ADC_CH0IF_bm 0x01 /* Channel 0 Interrupt Flag bit mask. */ -#define ADC_CH0IF_bp 0 /* Channel 0 Interrupt Flag bit position. */ - -/* DAC - Digital/Analog Converter */ -/* DAC.CTRLA bit masks and bit positions */ -#define DAC_IDOEN_bm 0x10 /* Internal Output Enable bit mask. */ -#define DAC_IDOEN_bp 4 /* Internal Output Enable bit position. */ - -#define DAC_CH1EN_bm 0x08 /* Channel 1 Output Enable bit mask. */ -#define DAC_CH1EN_bp 3 /* Channel 1 Output Enable bit position. */ - -#define DAC_CH0EN_bm 0x04 /* Channel 0 Output Enable bit mask. */ -#define DAC_CH0EN_bp 2 /* Channel 0 Output Enable bit position. */ - -#define DAC_LPMODE_bm 0x02 /* Low Power Mode bit mask. */ -#define DAC_LPMODE_bp 1 /* Low Power Mode bit position. */ - -#define DAC_ENABLE_bm 0x01 /* Enable bit mask. */ -#define DAC_ENABLE_bp 0 /* Enable bit position. */ - -/* DAC.CTRLB bit masks and bit positions */ -#define DAC_CHSEL_gm 0x60 /* Channel Select group mask. */ -#define DAC_CHSEL_gp 5 /* Channel Select group position. */ -#define DAC_CHSEL0_bm (1<<5) /* Channel Select bit 0 mask. */ -#define DAC_CHSEL0_bp 5 /* Channel Select bit 0 position. */ -#define DAC_CHSEL1_bm (1<<6) /* Channel Select bit 1 mask. */ -#define DAC_CHSEL1_bp 6 /* Channel Select bit 1 position. */ - -#define DAC_CH1TRIG_bm 0x02 /* Channel 1 Event Trig Enable bit mask. */ -#define DAC_CH1TRIG_bp 1 /* Channel 1 Event Trig Enable bit position. */ - -#define DAC_CH0TRIG_bm 0x01 /* Channel 0 Event Trig Enable bit mask. */ -#define DAC_CH0TRIG_bp 0 /* Channel 0 Event Trig Enable bit position. */ - -/* DAC.CTRLC bit masks and bit positions */ -#define DAC_REFSEL_gm 0x18 /* Reference Select group mask. */ -#define DAC_REFSEL_gp 3 /* Reference Select group position. */ -#define DAC_REFSEL0_bm (1<<3) /* Reference Select bit 0 mask. */ -#define DAC_REFSEL0_bp 3 /* Reference Select bit 0 position. */ -#define DAC_REFSEL1_bm (1<<4) /* Reference Select bit 1 mask. */ -#define DAC_REFSEL1_bp 4 /* Reference Select bit 1 position. */ - -#define DAC_LEFTADJ_bm 0x01 /* Left-adjust Result bit mask. */ -#define DAC_LEFTADJ_bp 0 /* Left-adjust Result bit position. */ - -/* DAC.EVCTRL bit masks and bit positions */ -#define DAC_EVSPLIT_bm 0x08 /* Separate Event Channel Input for Channel 1 bit mask. */ -#define DAC_EVSPLIT_bp 3 /* Separate Event Channel Input for Channel 1 bit position. */ - -#define DAC_EVSEL_gm 0x07 /* Event Input Selection group mask. */ -#define DAC_EVSEL_gp 0 /* Event Input Selection group position. */ -#define DAC_EVSEL0_bm (1<<0) /* Event Input Selection bit 0 mask. */ -#define DAC_EVSEL0_bp 0 /* Event Input Selection bit 0 position. */ -#define DAC_EVSEL1_bm (1<<1) /* Event Input Selection bit 1 mask. */ -#define DAC_EVSEL1_bp 1 /* Event Input Selection bit 1 position. */ -#define DAC_EVSEL2_bm (1<<2) /* Event Input Selection bit 2 mask. */ -#define DAC_EVSEL2_bp 2 /* Event Input Selection bit 2 position. */ - -/* DAC.STATUS bit masks and bit positions */ -#define DAC_CH1DRE_bm 0x02 /* Channel 1 Data Register Empty bit mask. */ -#define DAC_CH1DRE_bp 1 /* Channel 1 Data Register Empty bit position. */ - -#define DAC_CH0DRE_bm 0x01 /* Channel 0 Data Register Empty bit mask. */ -#define DAC_CH0DRE_bp 0 /* Channel 0 Data Register Empty bit position. */ - -/* DAC.CH0GAINCAL bit masks and bit positions */ -#define DAC_CH0GAINCAL_gm 0x7F /* Gain Calibration group mask. */ -#define DAC_CH0GAINCAL_gp 0 /* Gain Calibration group position. */ -#define DAC_CH0GAINCAL0_bm (1<<0) /* Gain Calibration bit 0 mask. */ -#define DAC_CH0GAINCAL0_bp 0 /* Gain Calibration bit 0 position. */ -#define DAC_CH0GAINCAL1_bm (1<<1) /* Gain Calibration bit 1 mask. */ -#define DAC_CH0GAINCAL1_bp 1 /* Gain Calibration bit 1 position. */ -#define DAC_CH0GAINCAL2_bm (1<<2) /* Gain Calibration bit 2 mask. */ -#define DAC_CH0GAINCAL2_bp 2 /* Gain Calibration bit 2 position. */ -#define DAC_CH0GAINCAL3_bm (1<<3) /* Gain Calibration bit 3 mask. */ -#define DAC_CH0GAINCAL3_bp 3 /* Gain Calibration bit 3 position. */ -#define DAC_CH0GAINCAL4_bm (1<<4) /* Gain Calibration bit 4 mask. */ -#define DAC_CH0GAINCAL4_bp 4 /* Gain Calibration bit 4 position. */ -#define DAC_CH0GAINCAL5_bm (1<<5) /* Gain Calibration bit 5 mask. */ -#define DAC_CH0GAINCAL5_bp 5 /* Gain Calibration bit 5 position. */ -#define DAC_CH0GAINCAL6_bm (1<<6) /* Gain Calibration bit 6 mask. */ -#define DAC_CH0GAINCAL6_bp 6 /* Gain Calibration bit 6 position. */ - -/* DAC.CH0OFFSETCAL bit masks and bit positions */ -#define DAC_CH0OFFSETCAL_gm 0x7F /* Offset Calibration group mask. */ -#define DAC_CH0OFFSETCAL_gp 0 /* Offset Calibration group position. */ -#define DAC_CH0OFFSETCAL0_bm (1<<0) /* Offset Calibration bit 0 mask. */ -#define DAC_CH0OFFSETCAL0_bp 0 /* Offset Calibration bit 0 position. */ -#define DAC_CH0OFFSETCAL1_bm (1<<1) /* Offset Calibration bit 1 mask. */ -#define DAC_CH0OFFSETCAL1_bp 1 /* Offset Calibration bit 1 position. */ -#define DAC_CH0OFFSETCAL2_bm (1<<2) /* Offset Calibration bit 2 mask. */ -#define DAC_CH0OFFSETCAL2_bp 2 /* Offset Calibration bit 2 position. */ -#define DAC_CH0OFFSETCAL3_bm (1<<3) /* Offset Calibration bit 3 mask. */ -#define DAC_CH0OFFSETCAL3_bp 3 /* Offset Calibration bit 3 position. */ -#define DAC_CH0OFFSETCAL4_bm (1<<4) /* Offset Calibration bit 4 mask. */ -#define DAC_CH0OFFSETCAL4_bp 4 /* Offset Calibration bit 4 position. */ -#define DAC_CH0OFFSETCAL5_bm (1<<5) /* Offset Calibration bit 5 mask. */ -#define DAC_CH0OFFSETCAL5_bp 5 /* Offset Calibration bit 5 position. */ -#define DAC_CH0OFFSETCAL6_bm (1<<6) /* Offset Calibration bit 6 mask. */ -#define DAC_CH0OFFSETCAL6_bp 6 /* Offset Calibration bit 6 position. */ - -/* DAC.CH1GAINCAL bit masks and bit positions */ -#define DAC_CH1GAINCAL_gm 0x7F /* Gain Calibration group mask. */ -#define DAC_CH1GAINCAL_gp 0 /* Gain Calibration group position. */ -#define DAC_CH1GAINCAL0_bm (1<<0) /* Gain Calibration bit 0 mask. */ -#define DAC_CH1GAINCAL0_bp 0 /* Gain Calibration bit 0 position. */ -#define DAC_CH1GAINCAL1_bm (1<<1) /* Gain Calibration bit 1 mask. */ -#define DAC_CH1GAINCAL1_bp 1 /* Gain Calibration bit 1 position. */ -#define DAC_CH1GAINCAL2_bm (1<<2) /* Gain Calibration bit 2 mask. */ -#define DAC_CH1GAINCAL2_bp 2 /* Gain Calibration bit 2 position. */ -#define DAC_CH1GAINCAL3_bm (1<<3) /* Gain Calibration bit 3 mask. */ -#define DAC_CH1GAINCAL3_bp 3 /* Gain Calibration bit 3 position. */ -#define DAC_CH1GAINCAL4_bm (1<<4) /* Gain Calibration bit 4 mask. */ -#define DAC_CH1GAINCAL4_bp 4 /* Gain Calibration bit 4 position. */ -#define DAC_CH1GAINCAL5_bm (1<<5) /* Gain Calibration bit 5 mask. */ -#define DAC_CH1GAINCAL5_bp 5 /* Gain Calibration bit 5 position. */ -#define DAC_CH1GAINCAL6_bm (1<<6) /* Gain Calibration bit 6 mask. */ -#define DAC_CH1GAINCAL6_bp 6 /* Gain Calibration bit 6 position. */ - -/* DAC.CH1OFFSETCAL bit masks and bit positions */ -#define DAC_CH1OFFSETCAL_gm 0x7F /* Offset Calibration group mask. */ -#define DAC_CH1OFFSETCAL_gp 0 /* Offset Calibration group position. */ -#define DAC_CH1OFFSETCAL0_bm (1<<0) /* Offset Calibration bit 0 mask. */ -#define DAC_CH1OFFSETCAL0_bp 0 /* Offset Calibration bit 0 position. */ -#define DAC_CH1OFFSETCAL1_bm (1<<1) /* Offset Calibration bit 1 mask. */ -#define DAC_CH1OFFSETCAL1_bp 1 /* Offset Calibration bit 1 position. */ -#define DAC_CH1OFFSETCAL2_bm (1<<2) /* Offset Calibration bit 2 mask. */ -#define DAC_CH1OFFSETCAL2_bp 2 /* Offset Calibration bit 2 position. */ -#define DAC_CH1OFFSETCAL3_bm (1<<3) /* Offset Calibration bit 3 mask. */ -#define DAC_CH1OFFSETCAL3_bp 3 /* Offset Calibration bit 3 position. */ -#define DAC_CH1OFFSETCAL4_bm (1<<4) /* Offset Calibration bit 4 mask. */ -#define DAC_CH1OFFSETCAL4_bp 4 /* Offset Calibration bit 4 position. */ -#define DAC_CH1OFFSETCAL5_bm (1<<5) /* Offset Calibration bit 5 mask. */ -#define DAC_CH1OFFSETCAL5_bp 5 /* Offset Calibration bit 5 position. */ -#define DAC_CH1OFFSETCAL6_bm (1<<6) /* Offset Calibration bit 6 mask. */ -#define DAC_CH1OFFSETCAL6_bp 6 /* Offset Calibration bit 6 position. */ - -/* AC - Analog Comparator */ -/* AC.AC0CTRL bit masks and bit positions */ -#define AC_INTMODE_gm 0xC0 /* Interrupt Mode group mask. */ -#define AC_INTMODE_gp 6 /* Interrupt Mode group position. */ -#define AC_INTMODE0_bm (1<<6) /* Interrupt Mode bit 0 mask. */ -#define AC_INTMODE0_bp 6 /* Interrupt Mode bit 0 position. */ -#define AC_INTMODE1_bm (1<<7) /* Interrupt Mode bit 1 mask. */ -#define AC_INTMODE1_bp 7 /* Interrupt Mode bit 1 position. */ - -#define AC_INTLVL_gm 0x30 /* Interrupt Level group mask. */ -#define AC_INTLVL_gp 4 /* Interrupt Level group position. */ -#define AC_INTLVL0_bm (1<<4) /* Interrupt Level bit 0 mask. */ -#define AC_INTLVL0_bp 4 /* Interrupt Level bit 0 position. */ -#define AC_INTLVL1_bm (1<<5) /* Interrupt Level bit 1 mask. */ -#define AC_INTLVL1_bp 5 /* Interrupt Level bit 1 position. */ - -#define AC_HSMODE_bm 0x08 /* High-speed Mode bit mask. */ -#define AC_HSMODE_bp 3 /* High-speed Mode bit position. */ - -#define AC_HYSMODE_gm 0x06 /* Hysteresis Mode group mask. */ -#define AC_HYSMODE_gp 1 /* Hysteresis Mode group position. */ -#define AC_HYSMODE0_bm (1<<1) /* Hysteresis Mode bit 0 mask. */ -#define AC_HYSMODE0_bp 1 /* Hysteresis Mode bit 0 position. */ -#define AC_HYSMODE1_bm (1<<2) /* Hysteresis Mode bit 1 mask. */ -#define AC_HYSMODE1_bp 2 /* Hysteresis Mode bit 1 position. */ - -#define AC_ENABLE_bm 0x01 /* Enable bit mask. */ -#define AC_ENABLE_bp 0 /* Enable bit position. */ - -/* AC.AC1CTRL bit masks and bit positions */ -/* AC_INTMODE Predefined. */ -/* AC_INTMODE Predefined. */ - -/* AC_INTLVL Predefined. */ -/* AC_INTLVL Predefined. */ - -/* AC_HSMODE Predefined. */ -/* AC_HSMODE Predefined. */ - -/* AC_HYSMODE Predefined. */ -/* AC_HYSMODE Predefined. */ - -/* AC_ENABLE Predefined. */ -/* AC_ENABLE Predefined. */ - -/* AC.AC0MUXCTRL bit masks and bit positions */ -#define AC_MUXPOS_gm 0x38 /* MUX Positive Input group mask. */ -#define AC_MUXPOS_gp 3 /* MUX Positive Input group position. */ -#define AC_MUXPOS0_bm (1<<3) /* MUX Positive Input bit 0 mask. */ -#define AC_MUXPOS0_bp 3 /* MUX Positive Input bit 0 position. */ -#define AC_MUXPOS1_bm (1<<4) /* MUX Positive Input bit 1 mask. */ -#define AC_MUXPOS1_bp 4 /* MUX Positive Input bit 1 position. */ -#define AC_MUXPOS2_bm (1<<5) /* MUX Positive Input bit 2 mask. */ -#define AC_MUXPOS2_bp 5 /* MUX Positive Input bit 2 position. */ - -#define AC_MUXNEG_gm 0x07 /* MUX Negative Input group mask. */ -#define AC_MUXNEG_gp 0 /* MUX Negative Input group position. */ -#define AC_MUXNEG0_bm (1<<0) /* MUX Negative Input bit 0 mask. */ -#define AC_MUXNEG0_bp 0 /* MUX Negative Input bit 0 position. */ -#define AC_MUXNEG1_bm (1<<1) /* MUX Negative Input bit 1 mask. */ -#define AC_MUXNEG1_bp 1 /* MUX Negative Input bit 1 position. */ -#define AC_MUXNEG2_bm (1<<2) /* MUX Negative Input bit 2 mask. */ -#define AC_MUXNEG2_bp 2 /* MUX Negative Input bit 2 position. */ - -/* AC.AC1MUXCTRL bit masks and bit positions */ -/* AC_MUXPOS Predefined. */ -/* AC_MUXPOS Predefined. */ - -/* AC_MUXNEG Predefined. */ -/* AC_MUXNEG Predefined. */ - -/* AC.CTRLA bit masks and bit positions */ -#define AC_AC1OUT_bm 0x02 /* Analog Comparator 1 Output Enable bit mask. */ -#define AC_AC1OUT_bp 1 /* Analog Comparator 1 Output Enable bit position. */ - -#define AC_AC0OUT_bm 0x01 /* Analog Comparator 0 Output Enable bit mask. */ -#define AC_AC0OUT_bp 0 /* Analog Comparator 0 Output Enable bit position. */ - -/* AC.CTRLB bit masks and bit positions */ -#define AC_SCALEFAC_gm 0x3F /* VCC Voltage Scaler Factor group mask. */ -#define AC_SCALEFAC_gp 0 /* VCC Voltage Scaler Factor group position. */ -#define AC_SCALEFAC0_bm (1<<0) /* VCC Voltage Scaler Factor bit 0 mask. */ -#define AC_SCALEFAC0_bp 0 /* VCC Voltage Scaler Factor bit 0 position. */ -#define AC_SCALEFAC1_bm (1<<1) /* VCC Voltage Scaler Factor bit 1 mask. */ -#define AC_SCALEFAC1_bp 1 /* VCC Voltage Scaler Factor bit 1 position. */ -#define AC_SCALEFAC2_bm (1<<2) /* VCC Voltage Scaler Factor bit 2 mask. */ -#define AC_SCALEFAC2_bp 2 /* VCC Voltage Scaler Factor bit 2 position. */ -#define AC_SCALEFAC3_bm (1<<3) /* VCC Voltage Scaler Factor bit 3 mask. */ -#define AC_SCALEFAC3_bp 3 /* VCC Voltage Scaler Factor bit 3 position. */ -#define AC_SCALEFAC4_bm (1<<4) /* VCC Voltage Scaler Factor bit 4 mask. */ -#define AC_SCALEFAC4_bp 4 /* VCC Voltage Scaler Factor bit 4 position. */ -#define AC_SCALEFAC5_bm (1<<5) /* VCC Voltage Scaler Factor bit 5 mask. */ -#define AC_SCALEFAC5_bp 5 /* VCC Voltage Scaler Factor bit 5 position. */ - -/* AC.WINCTRL bit masks and bit positions */ -#define AC_WEN_bm 0x10 /* Window Mode Enable bit mask. */ -#define AC_WEN_bp 4 /* Window Mode Enable bit position. */ - -#define AC_WINTMODE_gm 0x0C /* Window Interrupt Mode group mask. */ -#define AC_WINTMODE_gp 2 /* Window Interrupt Mode group position. */ -#define AC_WINTMODE0_bm (1<<2) /* Window Interrupt Mode bit 0 mask. */ -#define AC_WINTMODE0_bp 2 /* Window Interrupt Mode bit 0 position. */ -#define AC_WINTMODE1_bm (1<<3) /* Window Interrupt Mode bit 1 mask. */ -#define AC_WINTMODE1_bp 3 /* Window Interrupt Mode bit 1 position. */ - -#define AC_WINTLVL_gm 0x03 /* Window Interrupt Level group mask. */ -#define AC_WINTLVL_gp 0 /* Window Interrupt Level group position. */ -#define AC_WINTLVL0_bm (1<<0) /* Window Interrupt Level bit 0 mask. */ -#define AC_WINTLVL0_bp 0 /* Window Interrupt Level bit 0 position. */ -#define AC_WINTLVL1_bm (1<<1) /* Window Interrupt Level bit 1 mask. */ -#define AC_WINTLVL1_bp 1 /* Window Interrupt Level bit 1 position. */ - -/* AC.STATUS bit masks and bit positions */ -#define AC_WSTATE_gm 0xC0 /* Window Mode State group mask. */ -#define AC_WSTATE_gp 6 /* Window Mode State group position. */ -#define AC_WSTATE0_bm (1<<6) /* Window Mode State bit 0 mask. */ -#define AC_WSTATE0_bp 6 /* Window Mode State bit 0 position. */ -#define AC_WSTATE1_bm (1<<7) /* Window Mode State bit 1 mask. */ -#define AC_WSTATE1_bp 7 /* Window Mode State bit 1 position. */ - -#define AC_AC1STATE_bm 0x20 /* Analog Comparator 1 State bit mask. */ -#define AC_AC1STATE_bp 5 /* Analog Comparator 1 State bit position. */ - -#define AC_AC0STATE_bm 0x10 /* Analog Comparator 0 State bit mask. */ -#define AC_AC0STATE_bp 4 /* Analog Comparator 0 State bit position. */ - -#define AC_WIF_bm 0x04 /* Window Mode Interrupt Flag bit mask. */ -#define AC_WIF_bp 2 /* Window Mode Interrupt Flag bit position. */ - -#define AC_AC1IF_bm 0x02 /* Analog Comparator 1 Interrupt Flag bit mask. */ -#define AC_AC1IF_bp 1 /* Analog Comparator 1 Interrupt Flag bit position. */ - -#define AC_AC0IF_bm 0x01 /* Analog Comparator 0 Interrupt Flag bit mask. */ -#define AC_AC0IF_bp 0 /* Analog Comparator 0 Interrupt Flag bit position. */ - -/* RTC - Real-Time Counter */ -/* RTC.CTRL bit masks and bit positions */ -#define RTC_PRESCALER_gm 0x07 /* Prescaling Factor group mask. */ -#define RTC_PRESCALER_gp 0 /* Prescaling Factor group position. */ -#define RTC_PRESCALER0_bm (1<<0) /* Prescaling Factor bit 0 mask. */ -#define RTC_PRESCALER0_bp 0 /* Prescaling Factor bit 0 position. */ -#define RTC_PRESCALER1_bm (1<<1) /* Prescaling Factor bit 1 mask. */ -#define RTC_PRESCALER1_bp 1 /* Prescaling Factor bit 1 position. */ -#define RTC_PRESCALER2_bm (1<<2) /* Prescaling Factor bit 2 mask. */ -#define RTC_PRESCALER2_bp 2 /* Prescaling Factor bit 2 position. */ - -/* RTC.STATUS bit masks and bit positions */ -#define RTC_SYNCBUSY_bm 0x01 /* Synchronization Busy Flag bit mask. */ -#define RTC_SYNCBUSY_bp 0 /* Synchronization Busy Flag bit position. */ - -/* RTC.INTCTRL bit masks and bit positions */ -#define RTC_COMPINTLVL_gm 0x0C /* Compare Match Interrupt Level group mask. */ -#define RTC_COMPINTLVL_gp 2 /* Compare Match Interrupt Level group position. */ -#define RTC_COMPINTLVL0_bm (1<<2) /* Compare Match Interrupt Level bit 0 mask. */ -#define RTC_COMPINTLVL0_bp 2 /* Compare Match Interrupt Level bit 0 position. */ -#define RTC_COMPINTLVL1_bm (1<<3) /* Compare Match Interrupt Level bit 1 mask. */ -#define RTC_COMPINTLVL1_bp 3 /* Compare Match Interrupt Level bit 1 position. */ - -#define RTC_OVFINTLVL_gm 0x03 /* Overflow Interrupt Level group mask. */ -#define RTC_OVFINTLVL_gp 0 /* Overflow Interrupt Level group position. */ -#define RTC_OVFINTLVL0_bm (1<<0) /* Overflow Interrupt Level bit 0 mask. */ -#define RTC_OVFINTLVL0_bp 0 /* Overflow Interrupt Level bit 0 position. */ -#define RTC_OVFINTLVL1_bm (1<<1) /* Overflow Interrupt Level bit 1 mask. */ -#define RTC_OVFINTLVL1_bp 1 /* Overflow Interrupt Level bit 1 position. */ - -/* RTC.INTFLAGS bit masks and bit positions */ -#define RTC_COMPIF_bm 0x02 /* Compare Match Interrupt Flag bit mask. */ -#define RTC_COMPIF_bp 1 /* Compare Match Interrupt Flag bit position. */ - -#define RTC_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ -#define RTC_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ - -/* TWI - Two-Wire Interface */ -/* TWI_MASTER.CTRLA bit masks and bit positions */ -#define TWI_MASTER_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ -#define TWI_MASTER_INTLVL_gp 6 /* Interrupt Level group position. */ -#define TWI_MASTER_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ -#define TWI_MASTER_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ -#define TWI_MASTER_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ -#define TWI_MASTER_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ - -#define TWI_MASTER_RIEN_bm 0x20 /* Read Interrupt Enable bit mask. */ -#define TWI_MASTER_RIEN_bp 5 /* Read Interrupt Enable bit position. */ - -#define TWI_MASTER_WIEN_bm 0x10 /* Write Interrupt Enable bit mask. */ -#define TWI_MASTER_WIEN_bp 4 /* Write Interrupt Enable bit position. */ - -#define TWI_MASTER_ENABLE_bm 0x08 /* Enable TWI Master bit mask. */ -#define TWI_MASTER_ENABLE_bp 3 /* Enable TWI Master bit position. */ - -/* TWI_MASTER.CTRLB bit masks and bit positions */ -#define TWI_MASTER_TIMEOUT_gm 0x0C /* Inactive Bus Timeout group mask. */ -#define TWI_MASTER_TIMEOUT_gp 2 /* Inactive Bus Timeout group position. */ -#define TWI_MASTER_TIMEOUT0_bm (1<<2) /* Inactive Bus Timeout bit 0 mask. */ -#define TWI_MASTER_TIMEOUT0_bp 2 /* Inactive Bus Timeout bit 0 position. */ -#define TWI_MASTER_TIMEOUT1_bm (1<<3) /* Inactive Bus Timeout bit 1 mask. */ -#define TWI_MASTER_TIMEOUT1_bp 3 /* Inactive Bus Timeout bit 1 position. */ - -#define TWI_MASTER_QCEN_bm 0x02 /* Quick Command Enable bit mask. */ -#define TWI_MASTER_QCEN_bp 1 /* Quick Command Enable bit position. */ - -#define TWI_MASTER_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ -#define TWI_MASTER_SMEN_bp 0 /* Smart Mode Enable bit position. */ - -/* TWI_MASTER.CTRLC bit masks and bit positions */ -#define TWI_MASTER_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ -#define TWI_MASTER_ACKACT_bp 2 /* Acknowledge Action bit position. */ - -#define TWI_MASTER_CMD_gm 0x03 /* Command group mask. */ -#define TWI_MASTER_CMD_gp 0 /* Command group position. */ -#define TWI_MASTER_CMD0_bm (1<<0) /* Command bit 0 mask. */ -#define TWI_MASTER_CMD0_bp 0 /* Command bit 0 position. */ -#define TWI_MASTER_CMD1_bm (1<<1) /* Command bit 1 mask. */ -#define TWI_MASTER_CMD1_bp 1 /* Command bit 1 position. */ - -/* TWI_MASTER.STATUS bit masks and bit positions */ -#define TWI_MASTER_RIF_bm 0x80 /* Read Interrupt Flag bit mask. */ -#define TWI_MASTER_RIF_bp 7 /* Read Interrupt Flag bit position. */ - -#define TWI_MASTER_WIF_bm 0x40 /* Write Interrupt Flag bit mask. */ -#define TWI_MASTER_WIF_bp 6 /* Write Interrupt Flag bit position. */ - -#define TWI_MASTER_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ -#define TWI_MASTER_CLKHOLD_bp 5 /* Clock Hold bit position. */ - -#define TWI_MASTER_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ -#define TWI_MASTER_RXACK_bp 4 /* Received Acknowledge bit position. */ - -#define TWI_MASTER_ARBLOST_bm 0x08 /* Arbitration Lost bit mask. */ -#define TWI_MASTER_ARBLOST_bp 3 /* Arbitration Lost bit position. */ - -#define TWI_MASTER_BUSERR_bm 0x04 /* Bus Error bit mask. */ -#define TWI_MASTER_BUSERR_bp 2 /* Bus Error bit position. */ - -#define TWI_MASTER_BUSSTATE_gm 0x03 /* Bus State group mask. */ -#define TWI_MASTER_BUSSTATE_gp 0 /* Bus State group position. */ -#define TWI_MASTER_BUSSTATE0_bm (1<<0) /* Bus State bit 0 mask. */ -#define TWI_MASTER_BUSSTATE0_bp 0 /* Bus State bit 0 position. */ -#define TWI_MASTER_BUSSTATE1_bm (1<<1) /* Bus State bit 1 mask. */ -#define TWI_MASTER_BUSSTATE1_bp 1 /* Bus State bit 1 position. */ - -/* TWI_SLAVE.CTRLA bit masks and bit positions */ -#define TWI_SLAVE_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ -#define TWI_SLAVE_INTLVL_gp 6 /* Interrupt Level group position. */ -#define TWI_SLAVE_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ -#define TWI_SLAVE_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ -#define TWI_SLAVE_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ -#define TWI_SLAVE_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ - -#define TWI_SLAVE_DIEN_bm 0x20 /* Data Interrupt Enable bit mask. */ -#define TWI_SLAVE_DIEN_bp 5 /* Data Interrupt Enable bit position. */ - -#define TWI_SLAVE_APIEN_bm 0x10 /* Address/Stop Interrupt Enable bit mask. */ -#define TWI_SLAVE_APIEN_bp 4 /* Address/Stop Interrupt Enable bit position. */ - -#define TWI_SLAVE_ENABLE_bm 0x08 /* Enable TWI Slave bit mask. */ -#define TWI_SLAVE_ENABLE_bp 3 /* Enable TWI Slave bit position. */ - -#define TWI_SLAVE_PIEN_bm 0x04 /* Stop Interrupt Enable bit mask. */ -#define TWI_SLAVE_PIEN_bp 2 /* Stop Interrupt Enable bit position. */ - -#define TWI_SLAVE_PMEN_bm 0x02 /* Promiscuous Mode Enable bit mask. */ -#define TWI_SLAVE_PMEN_bp 1 /* Promiscuous Mode Enable bit position. */ - -#define TWI_SLAVE_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ -#define TWI_SLAVE_SMEN_bp 0 /* Smart Mode Enable bit position. */ - -/* TWI_SLAVE.CTRLB bit masks and bit positions */ -#define TWI_SLAVE_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ -#define TWI_SLAVE_ACKACT_bp 2 /* Acknowledge Action bit position. */ - -#define TWI_SLAVE_CMD_gm 0x03 /* Command group mask. */ -#define TWI_SLAVE_CMD_gp 0 /* Command group position. */ -#define TWI_SLAVE_CMD0_bm (1<<0) /* Command bit 0 mask. */ -#define TWI_SLAVE_CMD0_bp 0 /* Command bit 0 position. */ -#define TWI_SLAVE_CMD1_bm (1<<1) /* Command bit 1 mask. */ -#define TWI_SLAVE_CMD1_bp 1 /* Command bit 1 position. */ - -/* TWI_SLAVE.STATUS bit masks and bit positions */ -#define TWI_SLAVE_DIF_bm 0x80 /* Data Interrupt Flag bit mask. */ -#define TWI_SLAVE_DIF_bp 7 /* Data Interrupt Flag bit position. */ - -#define TWI_SLAVE_APIF_bm 0x40 /* Address/Stop Interrupt Flag bit mask. */ -#define TWI_SLAVE_APIF_bp 6 /* Address/Stop Interrupt Flag bit position. */ - -#define TWI_SLAVE_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ -#define TWI_SLAVE_CLKHOLD_bp 5 /* Clock Hold bit position. */ - -#define TWI_SLAVE_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ -#define TWI_SLAVE_RXACK_bp 4 /* Received Acknowledge bit position. */ - -#define TWI_SLAVE_COLL_bm 0x08 /* Collision bit mask. */ -#define TWI_SLAVE_COLL_bp 3 /* Collision bit position. */ - -#define TWI_SLAVE_BUSERR_bm 0x04 /* Bus Error bit mask. */ -#define TWI_SLAVE_BUSERR_bp 2 /* Bus Error bit position. */ - -#define TWI_SLAVE_DIR_bm 0x02 /* Read/Write Direction bit mask. */ -#define TWI_SLAVE_DIR_bp 1 /* Read/Write Direction bit position. */ - -#define TWI_SLAVE_AP_bm 0x01 /* Slave Address or Stop bit mask. */ -#define TWI_SLAVE_AP_bp 0 /* Slave Address or Stop bit position. */ - -/* TWI_SLAVE.ADDRMASK bit masks and bit positions */ -#define TWI_SLAVE_ADDRMASK_gm 0xFE /* Address Mask group mask. */ -#define TWI_SLAVE_ADDRMASK_gp 1 /* Address Mask group position. */ -#define TWI_SLAVE_ADDRMASK0_bm (1<<1) /* Address Mask bit 0 mask. */ -#define TWI_SLAVE_ADDRMASK0_bp 1 /* Address Mask bit 0 position. */ -#define TWI_SLAVE_ADDRMASK1_bm (1<<2) /* Address Mask bit 1 mask. */ -#define TWI_SLAVE_ADDRMASK1_bp 2 /* Address Mask bit 1 position. */ -#define TWI_SLAVE_ADDRMASK2_bm (1<<3) /* Address Mask bit 2 mask. */ -#define TWI_SLAVE_ADDRMASK2_bp 3 /* Address Mask bit 2 position. */ -#define TWI_SLAVE_ADDRMASK3_bm (1<<4) /* Address Mask bit 3 mask. */ -#define TWI_SLAVE_ADDRMASK3_bp 4 /* Address Mask bit 3 position. */ -#define TWI_SLAVE_ADDRMASK4_bm (1<<5) /* Address Mask bit 4 mask. */ -#define TWI_SLAVE_ADDRMASK4_bp 5 /* Address Mask bit 4 position. */ -#define TWI_SLAVE_ADDRMASK5_bm (1<<6) /* Address Mask bit 5 mask. */ -#define TWI_SLAVE_ADDRMASK5_bp 6 /* Address Mask bit 5 position. */ -#define TWI_SLAVE_ADDRMASK6_bm (1<<7) /* Address Mask bit 6 mask. */ -#define TWI_SLAVE_ADDRMASK6_bp 7 /* Address Mask bit 6 position. */ - -#define TWI_SLAVE_ADDREN_bm 0x01 /* Address Enable bit mask. */ -#define TWI_SLAVE_ADDREN_bp 0 /* Address Enable bit position. */ - -/* TWI.CTRL bit masks and bit positions */ -#define TWI_SDAHOLD_gm 0x06 /* SDA Hold Time Enable group mask. */ -#define TWI_SDAHOLD_gp 1 /* SDA Hold Time Enable group position. */ -#define TWI_SDAHOLD0_bm (1<<1) /* SDA Hold Time Enable bit 0 mask. */ -#define TWI_SDAHOLD0_bp 1 /* SDA Hold Time Enable bit 0 position. */ -#define TWI_SDAHOLD1_bm (1<<2) /* SDA Hold Time Enable bit 1 mask. */ -#define TWI_SDAHOLD1_bp 2 /* SDA Hold Time Enable bit 1 position. */ - -#define TWI_EDIEN_bm 0x01 /* External Driver Interface Enable bit mask. */ -#define TWI_EDIEN_bp 0 /* External Driver Interface Enable bit position. */ - -/* USB - USB */ -/* USB_EP.STATUS bit masks and bit positions */ -#define USB_EP_STALLF_bm 0x80 /* Endpoint Stall Flag bit mask. */ -#define USB_EP_STALLF_bp 7 /* Endpoint Stall Flag bit position. */ - -#define USB_EP_CRC_bm 0x80 /* CRC Error Flag bit mask. */ -#define USB_EP_CRC_bp 7 /* CRC Error Flag bit position. */ - -#define USB_EP_UNF_bm 0x40 /* Underflow Enpoint FLag bit mask. */ -#define USB_EP_UNF_bp 6 /* Underflow Enpoint FLag bit position. */ - -#define USB_EP_OVF_bm 0x40 /* Overflow Enpoint Flag for Output Endpoints bit mask. */ -#define USB_EP_OVF_bp 6 /* Overflow Enpoint Flag for Output Endpoints bit position. */ - -#define USB_EP_TRNCOMPL0_bm 0x20 /* Transaction Complete 0 Flag bit mask. */ -#define USB_EP_TRNCOMPL0_bp 5 /* Transaction Complete 0 Flag bit position. */ - -#define USB_EP_TRNCOMPL1_bm 0x10 /* Transaction Complete 1 Flag bit mask. */ -#define USB_EP_TRNCOMPL1_bp 4 /* Transaction Complete 1 Flag bit position. */ - -#define USB_EP_SETUP_bm 0x10 /* SETUP Transaction Complete Flag bit mask. */ -#define USB_EP_SETUP_bp 4 /* SETUP Transaction Complete Flag bit position. */ - -#define USB_EP_BANK_bm 0x08 /* Bank Select bit mask. */ -#define USB_EP_BANK_bp 3 /* Bank Select bit position. */ - -#define USB_EP_BUSNACK1_bm 0x04 /* Data Buffer 1 Not Acknowledge bit mask. */ -#define USB_EP_BUSNACK1_bp 2 /* Data Buffer 1 Not Acknowledge bit position. */ - -#define USB_EP_BUSNACK0_bm 0x02 /* Data Buffer 0 Not Acknowledge bit mask. */ -#define USB_EP_BUSNACK0_bp 1 /* Data Buffer 0 Not Acknowledge bit position. */ - -#define USB_EP_TOGGLE_bm 0x01 /* Data Toggle bit mask. */ -#define USB_EP_TOGGLE_bp 0 /* Data Toggle bit position. */ - -/* USB_EP.CTRL bit masks and bit positions */ -#define USB_EP_TYPE_gm 0xC0 /* Endpoint Type group mask. */ -#define USB_EP_TYPE_gp 6 /* Endpoint Type group position. */ -#define USB_EP_TYPE0_bm (1<<6) /* Endpoint Type bit 0 mask. */ -#define USB_EP_TYPE0_bp 6 /* Endpoint Type bit 0 position. */ -#define USB_EP_TYPE1_bm (1<<7) /* Endpoint Type bit 1 mask. */ -#define USB_EP_TYPE1_bp 7 /* Endpoint Type bit 1 position. */ - -#define USB_EP_MULTIPKT_bm 0x20 /* Multi Packet Transfer Enable bit mask. */ -#define USB_EP_MULTIPKT_bp 5 /* Multi Packet Transfer Enable bit position. */ - -#define USB_EP_PINGPONG_bm 0x10 /* Ping-Pong Enable bit mask. */ -#define USB_EP_PINGPONG_bp 4 /* Ping-Pong Enable bit position. */ - -#define USB_EP_INTDSBL_bm 0x08 /* Interrupt Disable bit mask. */ -#define USB_EP_INTDSBL_bp 3 /* Interrupt Disable bit position. */ - -#define USB_EP_STALL_bm 0x04 /* Data Stall bit mask. */ -#define USB_EP_STALL_bp 2 /* Data Stall bit position. */ - -#define USB_EP_BUFSIZE_gm 0x07 /* Data Buffer Size group mask. */ -#define USB_EP_BUFSIZE_gp 0 /* Data Buffer Size group position. */ -#define USB_EP_BUFSIZE0_bm (1<<0) /* Data Buffer Size bit 0 mask. */ -#define USB_EP_BUFSIZE0_bp 0 /* Data Buffer Size bit 0 position. */ -#define USB_EP_BUFSIZE1_bm (1<<1) /* Data Buffer Size bit 1 mask. */ -#define USB_EP_BUFSIZE1_bp 1 /* Data Buffer Size bit 1 position. */ -#define USB_EP_BUFSIZE2_bm (1<<2) /* Data Buffer Size bit 2 mask. */ -#define USB_EP_BUFSIZE2_bp 2 /* Data Buffer Size bit 2 position. */ - -/* USB_EP.CNT bit masks and bit positions */ -#define USB_EP_ZLP_bm 0x8000 /* Zero Length Packet bit mask. */ -#define USB_EP_ZLP_bp 15 /* Zero Length Packet bit position. */ - -/* USB.CTRLA bit masks and bit positions */ -#define USB_ENABLE_bm 0x80 /* USB Enable bit mask. */ -#define USB_ENABLE_bp 7 /* USB Enable bit position. */ - -#define USB_SPEED_bm 0x40 /* Speed Select bit mask. */ -#define USB_SPEED_bp 6 /* Speed Select bit position. */ - -#define USB_FIFOEN_bm 0x20 /* USB FIFO Enable bit mask. */ -#define USB_FIFOEN_bp 5 /* USB FIFO Enable bit position. */ - -#define USB_STFRNUM_bm 0x10 /* Store Frame Number Enable bit mask. */ -#define USB_STFRNUM_bp 4 /* Store Frame Number Enable bit position. */ - -#define USB_MAXEP_gm 0x0F /* Maximum Endpoint Addresses group mask. */ -#define USB_MAXEP_gp 0 /* Maximum Endpoint Addresses group position. */ -#define USB_MAXEP0_bm (1<<0) /* Maximum Endpoint Addresses bit 0 mask. */ -#define USB_MAXEP0_bp 0 /* Maximum Endpoint Addresses bit 0 position. */ -#define USB_MAXEP1_bm (1<<1) /* Maximum Endpoint Addresses bit 1 mask. */ -#define USB_MAXEP1_bp 1 /* Maximum Endpoint Addresses bit 1 position. */ -#define USB_MAXEP2_bm (1<<2) /* Maximum Endpoint Addresses bit 2 mask. */ -#define USB_MAXEP2_bp 2 /* Maximum Endpoint Addresses bit 2 position. */ -#define USB_MAXEP3_bm (1<<3) /* Maximum Endpoint Addresses bit 3 mask. */ -#define USB_MAXEP3_bp 3 /* Maximum Endpoint Addresses bit 3 position. */ - -/* USB.CTRLB bit masks and bit positions */ -#define USB_PULLRST_bm 0x10 /* Pull during Reset bit mask. */ -#define USB_PULLRST_bp 4 /* Pull during Reset bit position. */ - -#define USB_RWAKEUP_bm 0x04 /* Remote Wake-up bit mask. */ -#define USB_RWAKEUP_bp 2 /* Remote Wake-up bit position. */ - -#define USB_GNACK_bm 0x02 /* Global NACK bit mask. */ -#define USB_GNACK_bp 1 /* Global NACK bit position. */ - -#define USB_ATTACH_bm 0x01 /* Attach bit mask. */ -#define USB_ATTACH_bp 0 /* Attach bit position. */ - -/* USB.STATUS bit masks and bit positions */ -#define USB_URESUME_bm 0x08 /* Upstream Resume bit mask. */ -#define USB_URESUME_bp 3 /* Upstream Resume bit position. */ - -#define USB_RESUME_bm 0x04 /* Resume bit mask. */ -#define USB_RESUME_bp 2 /* Resume bit position. */ - -#define USB_SUSPEND_bm 0x02 /* Bus Suspended bit mask. */ -#define USB_SUSPEND_bp 1 /* Bus Suspended bit position. */ - -#define USB_BUSRST_bm 0x01 /* Bus Reset bit mask. */ -#define USB_BUSRST_bp 0 /* Bus Reset bit position. */ - -/* USB.ADDR bit masks and bit positions */ -#define USB_ADDR_gm 0x7F /* Device Address group mask. */ -#define USB_ADDR_gp 0 /* Device Address group position. */ -#define USB_ADDR0_bm (1<<0) /* Device Address bit 0 mask. */ -#define USB_ADDR0_bp 0 /* Device Address bit 0 position. */ -#define USB_ADDR1_bm (1<<1) /* Device Address bit 1 mask. */ -#define USB_ADDR1_bp 1 /* Device Address bit 1 position. */ -#define USB_ADDR2_bm (1<<2) /* Device Address bit 2 mask. */ -#define USB_ADDR2_bp 2 /* Device Address bit 2 position. */ -#define USB_ADDR3_bm (1<<3) /* Device Address bit 3 mask. */ -#define USB_ADDR3_bp 3 /* Device Address bit 3 position. */ -#define USB_ADDR4_bm (1<<4) /* Device Address bit 4 mask. */ -#define USB_ADDR4_bp 4 /* Device Address bit 4 position. */ -#define USB_ADDR5_bm (1<<5) /* Device Address bit 5 mask. */ -#define USB_ADDR5_bp 5 /* Device Address bit 5 position. */ -#define USB_ADDR6_bm (1<<6) /* Device Address bit 6 mask. */ -#define USB_ADDR6_bp 6 /* Device Address bit 6 position. */ - -/* USB.FIFOWP bit masks and bit positions */ -#define USB_FIFOWP_gm 0x1F /* FIFO Write Pointer group mask. */ -#define USB_FIFOWP_gp 0 /* FIFO Write Pointer group position. */ -#define USB_FIFOWP0_bm (1<<0) /* FIFO Write Pointer bit 0 mask. */ -#define USB_FIFOWP0_bp 0 /* FIFO Write Pointer bit 0 position. */ -#define USB_FIFOWP1_bm (1<<1) /* FIFO Write Pointer bit 1 mask. */ -#define USB_FIFOWP1_bp 1 /* FIFO Write Pointer bit 1 position. */ -#define USB_FIFOWP2_bm (1<<2) /* FIFO Write Pointer bit 2 mask. */ -#define USB_FIFOWP2_bp 2 /* FIFO Write Pointer bit 2 position. */ -#define USB_FIFOWP3_bm (1<<3) /* FIFO Write Pointer bit 3 mask. */ -#define USB_FIFOWP3_bp 3 /* FIFO Write Pointer bit 3 position. */ -#define USB_FIFOWP4_bm (1<<4) /* FIFO Write Pointer bit 4 mask. */ -#define USB_FIFOWP4_bp 4 /* FIFO Write Pointer bit 4 position. */ - -/* USB.FIFORP bit masks and bit positions */ -#define USB_FIFORP_gm 0x1F /* FIFO Read Pointer group mask. */ -#define USB_FIFORP_gp 0 /* FIFO Read Pointer group position. */ -#define USB_FIFORP0_bm (1<<0) /* FIFO Read Pointer bit 0 mask. */ -#define USB_FIFORP0_bp 0 /* FIFO Read Pointer bit 0 position. */ -#define USB_FIFORP1_bm (1<<1) /* FIFO Read Pointer bit 1 mask. */ -#define USB_FIFORP1_bp 1 /* FIFO Read Pointer bit 1 position. */ -#define USB_FIFORP2_bm (1<<2) /* FIFO Read Pointer bit 2 mask. */ -#define USB_FIFORP2_bp 2 /* FIFO Read Pointer bit 2 position. */ -#define USB_FIFORP3_bm (1<<3) /* FIFO Read Pointer bit 3 mask. */ -#define USB_FIFORP3_bp 3 /* FIFO Read Pointer bit 3 position. */ -#define USB_FIFORP4_bm (1<<4) /* FIFO Read Pointer bit 4 mask. */ -#define USB_FIFORP4_bp 4 /* FIFO Read Pointer bit 4 position. */ - -/* USB.INTCTRLA bit masks and bit positions */ -#define USB_SOFIE_bm 0x80 /* Start Of Frame Interrupt Enable bit mask. */ -#define USB_SOFIE_bp 7 /* Start Of Frame Interrupt Enable bit position. */ - -#define USB_BUSEVIE_bm 0x40 /* Bus Event Interrupt Enable bit mask. */ -#define USB_BUSEVIE_bp 6 /* Bus Event Interrupt Enable bit position. */ - -#define USB_BUSERRIE_bm 0x20 /* Bus Error Interrupt Enable bit mask. */ -#define USB_BUSERRIE_bp 5 /* Bus Error Interrupt Enable bit position. */ - -#define USB_STALLIE_bm 0x10 /* STALL Interrupt Enable bit mask. */ -#define USB_STALLIE_bp 4 /* STALL Interrupt Enable bit position. */ - -#define USB_INTLVL_gm 0x03 /* Interrupt Level group mask. */ -#define USB_INTLVL_gp 0 /* Interrupt Level group position. */ -#define USB_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */ -#define USB_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */ -#define USB_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ -#define USB_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */ - -/* USB.INTCTRLB bit masks and bit positions */ -#define USB_TRNIE_bm 0x02 /* Transaction Complete Interrupt Enable bit mask. */ -#define USB_TRNIE_bp 1 /* Transaction Complete Interrupt Enable bit position. */ - -#define USB_SETUPIE_bm 0x01 /* SETUP Transaction Complete Interrupt Enable bit mask. */ -#define USB_SETUPIE_bp 0 /* SETUP Transaction Complete Interrupt Enable bit position. */ - -/* USB.INTFLAGSACLR bit masks and bit positions */ -#define USB_SOFIF_bm 0x80 /* Start Of Frame Interrupt Flag bit mask. */ -#define USB_SOFIF_bp 7 /* Start Of Frame Interrupt Flag bit position. */ - -#define USB_SUSPENDIF_bm 0x40 /* Suspend Interrupt Flag bit mask. */ -#define USB_SUSPENDIF_bp 6 /* Suspend Interrupt Flag bit position. */ - -#define USB_RESUMEIF_bm 0x20 /* Resume Interrupt Flag bit mask. */ -#define USB_RESUMEIF_bp 5 /* Resume Interrupt Flag bit position. */ - -#define USB_RSTIF_bm 0x10 /* Reset Interrupt Flag bit mask. */ -#define USB_RSTIF_bp 4 /* Reset Interrupt Flag bit position. */ - -#define USB_CRCIF_bm 0x08 /* Isochronous CRC Error Interrupt Flag bit mask. */ -#define USB_CRCIF_bp 3 /* Isochronous CRC Error Interrupt Flag bit position. */ - -#define USB_UNFIF_bm 0x04 /* Underflow Interrupt Flag bit mask. */ -#define USB_UNFIF_bp 2 /* Underflow Interrupt Flag bit position. */ - -#define USB_OVFIF_bm 0x02 /* Overflow Interrupt Flag bit mask. */ -#define USB_OVFIF_bp 1 /* Overflow Interrupt Flag bit position. */ - -#define USB_STALLIF_bm 0x01 /* STALL Interrupt Flag bit mask. */ -#define USB_STALLIF_bp 0 /* STALL Interrupt Flag bit position. */ - -/* USB.INTFLAGSASET bit masks and bit positions */ -/* USB_SOFIF Predefined. */ -/* USB_SOFIF Predefined. */ - -/* USB_SUSPENDIF Predefined. */ -/* USB_SUSPENDIF Predefined. */ - -/* USB_RESUMEIF Predefined. */ -/* USB_RESUMEIF Predefined. */ - -/* USB_RSTIF Predefined. */ -/* USB_RSTIF Predefined. */ - -/* USB_CRCIF Predefined. */ -/* USB_CRCIF Predefined. */ - -/* USB_UNFIF Predefined. */ -/* USB_UNFIF Predefined. */ - -/* USB_OVFIF Predefined. */ -/* USB_OVFIF Predefined. */ - -/* USB_STALLIF Predefined. */ -/* USB_STALLIF Predefined. */ - -/* USB.INTFLAGSBCLR bit masks and bit positions */ -#define USB_TRNIF_bm 0x02 /* Transaction Complete Interrupt Flag bit mask. */ -#define USB_TRNIF_bp 1 /* Transaction Complete Interrupt Flag bit position. */ - -#define USB_SETUPIF_bm 0x01 /* SETUP Transaction Complete Interrupt Flag bit mask. */ -#define USB_SETUPIF_bp 0 /* SETUP Transaction Complete Interrupt Flag bit position. */ - -/* USB.INTFLAGSBSET bit masks and bit positions */ -/* USB_TRNIF Predefined. */ -/* USB_TRNIF Predefined. */ - -/* USB_SETUPIF Predefined. */ -/* USB_SETUPIF Predefined. */ - -/* PORT - I/O Port Configuration */ -/* PORT.INTCTRL bit masks and bit positions */ -#define PORT_INT1LVL_gm 0x0C /* Port Interrupt 1 Level group mask. */ -#define PORT_INT1LVL_gp 2 /* Port Interrupt 1 Level group position. */ -#define PORT_INT1LVL0_bm (1<<2) /* Port Interrupt 1 Level bit 0 mask. */ -#define PORT_INT1LVL0_bp 2 /* Port Interrupt 1 Level bit 0 position. */ -#define PORT_INT1LVL1_bm (1<<3) /* Port Interrupt 1 Level bit 1 mask. */ -#define PORT_INT1LVL1_bp 3 /* Port Interrupt 1 Level bit 1 position. */ - -#define PORT_INT0LVL_gm 0x03 /* Port Interrupt 0 Level group mask. */ -#define PORT_INT0LVL_gp 0 /* Port Interrupt 0 Level group position. */ -#define PORT_INT0LVL0_bm (1<<0) /* Port Interrupt 0 Level bit 0 mask. */ -#define PORT_INT0LVL0_bp 0 /* Port Interrupt 0 Level bit 0 position. */ -#define PORT_INT0LVL1_bm (1<<1) /* Port Interrupt 0 Level bit 1 mask. */ -#define PORT_INT0LVL1_bp 1 /* Port Interrupt 0 Level bit 1 position. */ - -/* PORT.INTFLAGS bit masks and bit positions */ -#define PORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ -#define PORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ - -#define PORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ -#define PORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ - -/* PORT.REMAP bit masks and bit positions */ -#define PORT_SPI_bm 0x20 /* SPI bit mask. */ -#define PORT_SPI_bp 5 /* SPI bit position. */ - -#define PORT_USART0_bm 0x10 /* USART0 bit mask. */ -#define PORT_USART0_bp 4 /* USART0 bit position. */ - -#define PORT_TC0D_bm 0x08 /* Timer/Counter 0 Output Compare D bit mask. */ -#define PORT_TC0D_bp 3 /* Timer/Counter 0 Output Compare D bit position. */ - -#define PORT_TC0C_bm 0x04 /* Timer/Counter 0 Output Compare C bit mask. */ -#define PORT_TC0C_bp 2 /* Timer/Counter 0 Output Compare C bit position. */ - -#define PORT_TC0B_bm 0x02 /* Timer/Counter 0 Output Compare B bit mask. */ -#define PORT_TC0B_bp 1 /* Timer/Counter 0 Output Compare B bit position. */ - -#define PORT_TC0A_bm 0x01 /* Timer/Counter 0 Output Compare A bit mask. */ -#define PORT_TC0A_bp 0 /* Timer/Counter 0 Output Compare A bit position. */ - -/* PORT.PIN0CTRL bit masks and bit positions */ -#define PORT_SRLEN_bm 0x80 /* Slew Rate Enable bit mask. */ -#define PORT_SRLEN_bp 7 /* Slew Rate Enable bit position. */ - -#define PORT_INVEN_bm 0x40 /* Inverted I/O Enable bit mask. */ -#define PORT_INVEN_bp 6 /* Inverted I/O Enable bit position. */ - -#define PORT_OPC_gm 0x38 /* Output/Pull Configuration group mask. */ -#define PORT_OPC_gp 3 /* Output/Pull Configuration group position. */ -#define PORT_OPC0_bm (1<<3) /* Output/Pull Configuration bit 0 mask. */ -#define PORT_OPC0_bp 3 /* Output/Pull Configuration bit 0 position. */ -#define PORT_OPC1_bm (1<<4) /* Output/Pull Configuration bit 1 mask. */ -#define PORT_OPC1_bp 4 /* Output/Pull Configuration bit 1 position. */ -#define PORT_OPC2_bm (1<<5) /* Output/Pull Configuration bit 2 mask. */ -#define PORT_OPC2_bp 5 /* Output/Pull Configuration bit 2 position. */ - -#define PORT_ISC_gm 0x07 /* Input/Sense Configuration group mask. */ -#define PORT_ISC_gp 0 /* Input/Sense Configuration group position. */ -#define PORT_ISC0_bm (1<<0) /* Input/Sense Configuration bit 0 mask. */ -#define PORT_ISC0_bp 0 /* Input/Sense Configuration bit 0 position. */ -#define PORT_ISC1_bm (1<<1) /* Input/Sense Configuration bit 1 mask. */ -#define PORT_ISC1_bp 1 /* Input/Sense Configuration bit 1 position. */ -#define PORT_ISC2_bm (1<<2) /* Input/Sense Configuration bit 2 mask. */ -#define PORT_ISC2_bp 2 /* Input/Sense Configuration bit 2 position. */ - -/* PORT.PIN1CTRL bit masks and bit positions */ -/* PORT_SRLEN Predefined. */ -/* PORT_SRLEN Predefined. */ - -/* PORT_INVEN Predefined. */ -/* PORT_INVEN Predefined. */ - -/* PORT_OPC Predefined. */ -/* PORT_OPC Predefined. */ - -/* PORT_ISC Predefined. */ -/* PORT_ISC Predefined. */ - -/* PORT.PIN2CTRL bit masks and bit positions */ -/* PORT_SRLEN Predefined. */ -/* PORT_SRLEN Predefined. */ - -/* PORT_INVEN Predefined. */ -/* PORT_INVEN Predefined. */ - -/* PORT_OPC Predefined. */ -/* PORT_OPC Predefined. */ - -/* PORT_ISC Predefined. */ -/* PORT_ISC Predefined. */ - -/* PORT.PIN3CTRL bit masks and bit positions */ -/* PORT_SRLEN Predefined. */ -/* PORT_SRLEN Predefined. */ - -/* PORT_INVEN Predefined. */ -/* PORT_INVEN Predefined. */ - -/* PORT_OPC Predefined. */ -/* PORT_OPC Predefined. */ - -/* PORT_ISC Predefined. */ -/* PORT_ISC Predefined. */ - -/* PORT.PIN4CTRL bit masks and bit positions */ -/* PORT_SRLEN Predefined. */ -/* PORT_SRLEN Predefined. */ - -/* PORT_INVEN Predefined. */ -/* PORT_INVEN Predefined. */ - -/* PORT_OPC Predefined. */ -/* PORT_OPC Predefined. */ - -/* PORT_ISC Predefined. */ -/* PORT_ISC Predefined. */ - -/* PORT.PIN5CTRL bit masks and bit positions */ -/* PORT_SRLEN Predefined. */ -/* PORT_SRLEN Predefined. */ - -/* PORT_INVEN Predefined. */ -/* PORT_INVEN Predefined. */ - -/* PORT_OPC Predefined. */ -/* PORT_OPC Predefined. */ - -/* PORT_ISC Predefined. */ -/* PORT_ISC Predefined. */ - -/* PORT.PIN6CTRL bit masks and bit positions */ -/* PORT_SRLEN Predefined. */ -/* PORT_SRLEN Predefined. */ - -/* PORT_INVEN Predefined. */ -/* PORT_INVEN Predefined. */ - -/* PORT_OPC Predefined. */ -/* PORT_OPC Predefined. */ - -/* PORT_ISC Predefined. */ -/* PORT_ISC Predefined. */ - -/* PORT.PIN7CTRL bit masks and bit positions */ -/* PORT_SRLEN Predefined. */ -/* PORT_SRLEN Predefined. */ - -/* PORT_INVEN Predefined. */ -/* PORT_INVEN Predefined. */ - -/* PORT_OPC Predefined. */ -/* PORT_OPC Predefined. */ - -/* PORT_ISC Predefined. */ -/* PORT_ISC Predefined. */ - -/* TC - 16-bit Timer/Counter With PWM */ -/* TC0.CTRLA bit masks and bit positions */ -#define TC0_CLKSEL_gm 0x0F /* Clock Selection group mask. */ -#define TC0_CLKSEL_gp 0 /* Clock Selection group position. */ -#define TC0_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ -#define TC0_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ -#define TC0_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ -#define TC0_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ -#define TC0_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ -#define TC0_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ -#define TC0_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ -#define TC0_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ - -/* TC0.CTRLB bit masks and bit positions */ -#define TC0_CCDEN_bm 0x80 /* Compare or Capture D Enable bit mask. */ -#define TC0_CCDEN_bp 7 /* Compare or Capture D Enable bit position. */ - -#define TC0_CCCEN_bm 0x40 /* Compare or Capture C Enable bit mask. */ -#define TC0_CCCEN_bp 6 /* Compare or Capture C Enable bit position. */ - -#define TC0_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ -#define TC0_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ - -#define TC0_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ -#define TC0_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ - -#define TC0_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ -#define TC0_WGMODE_gp 0 /* Waveform generation mode group position. */ -#define TC0_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ -#define TC0_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ -#define TC0_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ -#define TC0_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ -#define TC0_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ -#define TC0_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ - -/* TC0.CTRLC bit masks and bit positions */ -#define TC0_CMPD_bm 0x08 /* Compare D Output Value bit mask. */ -#define TC0_CMPD_bp 3 /* Compare D Output Value bit position. */ - -#define TC0_CMPC_bm 0x04 /* Compare C Output Value bit mask. */ -#define TC0_CMPC_bp 2 /* Compare C Output Value bit position. */ - -#define TC0_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ -#define TC0_CMPB_bp 1 /* Compare B Output Value bit position. */ - -#define TC0_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ -#define TC0_CMPA_bp 0 /* Compare A Output Value bit position. */ - -/* TC0.CTRLD bit masks and bit positions */ -#define TC0_EVACT_gm 0xE0 /* Event Action group mask. */ -#define TC0_EVACT_gp 5 /* Event Action group position. */ -#define TC0_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ -#define TC0_EVACT0_bp 5 /* Event Action bit 0 position. */ -#define TC0_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ -#define TC0_EVACT1_bp 6 /* Event Action bit 1 position. */ -#define TC0_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ -#define TC0_EVACT2_bp 7 /* Event Action bit 2 position. */ - -#define TC0_EVDLY_bm 0x10 /* Event Delay bit mask. */ -#define TC0_EVDLY_bp 4 /* Event Delay bit position. */ - -#define TC0_EVSEL_gm 0x0F /* Event Source Select group mask. */ -#define TC0_EVSEL_gp 0 /* Event Source Select group position. */ -#define TC0_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ -#define TC0_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ -#define TC0_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ -#define TC0_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ -#define TC0_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ -#define TC0_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ -#define TC0_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ -#define TC0_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ - -/* TC0.CTRLE bit masks and bit positions */ -#define TC0_BYTEM_gm 0x03 /* Byte Mode group mask. */ -#define TC0_BYTEM_gp 0 /* Byte Mode group position. */ -#define TC0_BYTEM0_bm (1<<0) /* Byte Mode bit 0 mask. */ -#define TC0_BYTEM0_bp 0 /* Byte Mode bit 0 position. */ -#define TC0_BYTEM1_bm (1<<1) /* Byte Mode bit 1 mask. */ -#define TC0_BYTEM1_bp 1 /* Byte Mode bit 1 position. */ - -/* TC0.INTCTRLA bit masks and bit positions */ -#define TC0_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ -#define TC0_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ -#define TC0_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ -#define TC0_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ -#define TC0_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ -#define TC0_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ - -#define TC0_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ -#define TC0_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ -#define TC0_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ -#define TC0_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ -#define TC0_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ -#define TC0_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ - -/* TC0.INTCTRLB bit masks and bit positions */ -#define TC0_CCDINTLVL_gm 0xC0 /* Compare or Capture D Interrupt Level group mask. */ -#define TC0_CCDINTLVL_gp 6 /* Compare or Capture D Interrupt Level group position. */ -#define TC0_CCDINTLVL0_bm (1<<6) /* Compare or Capture D Interrupt Level bit 0 mask. */ -#define TC0_CCDINTLVL0_bp 6 /* Compare or Capture D Interrupt Level bit 0 position. */ -#define TC0_CCDINTLVL1_bm (1<<7) /* Compare or Capture D Interrupt Level bit 1 mask. */ -#define TC0_CCDINTLVL1_bp 7 /* Compare or Capture D Interrupt Level bit 1 position. */ - -#define TC0_CCCINTLVL_gm 0x30 /* Compare or Capture C Interrupt Level group mask. */ -#define TC0_CCCINTLVL_gp 4 /* Compare or Capture C Interrupt Level group position. */ -#define TC0_CCCINTLVL0_bm (1<<4) /* Compare or Capture C Interrupt Level bit 0 mask. */ -#define TC0_CCCINTLVL0_bp 4 /* Compare or Capture C Interrupt Level bit 0 position. */ -#define TC0_CCCINTLVL1_bm (1<<5) /* Compare or Capture C Interrupt Level bit 1 mask. */ -#define TC0_CCCINTLVL1_bp 5 /* Compare or Capture C Interrupt Level bit 1 position. */ - -#define TC0_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ -#define TC0_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ -#define TC0_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ -#define TC0_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ -#define TC0_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ -#define TC0_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ - -#define TC0_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ -#define TC0_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ -#define TC0_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ -#define TC0_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ -#define TC0_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ -#define TC0_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ - -/* TC0.CTRLFCLR bit masks and bit positions */ -#define TC0_CMD_gm 0x0C /* Command group mask. */ -#define TC0_CMD_gp 2 /* Command group position. */ -#define TC0_CMD0_bm (1<<2) /* Command bit 0 mask. */ -#define TC0_CMD0_bp 2 /* Command bit 0 position. */ -#define TC0_CMD1_bm (1<<3) /* Command bit 1 mask. */ -#define TC0_CMD1_bp 3 /* Command bit 1 position. */ - -#define TC0_LUPD_bm 0x02 /* Lock Update bit mask. */ -#define TC0_LUPD_bp 1 /* Lock Update bit position. */ - -#define TC0_DIR_bm 0x01 /* Direction bit mask. */ -#define TC0_DIR_bp 0 /* Direction bit position. */ - -/* TC0.CTRLFSET bit masks and bit positions */ -/* TC0_CMD Predefined. */ -/* TC0_CMD Predefined. */ - -/* TC0_LUPD Predefined. */ -/* TC0_LUPD Predefined. */ - -/* TC0_DIR Predefined. */ -/* TC0_DIR Predefined. */ - -/* TC0.CTRLGCLR bit masks and bit positions */ -#define TC0_CCDBV_bm 0x10 /* Compare or Capture D Buffer Valid bit mask. */ -#define TC0_CCDBV_bp 4 /* Compare or Capture D Buffer Valid bit position. */ - -#define TC0_CCCBV_bm 0x08 /* Compare or Capture C Buffer Valid bit mask. */ -#define TC0_CCCBV_bp 3 /* Compare or Capture C Buffer Valid bit position. */ - -#define TC0_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ -#define TC0_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ - -#define TC0_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ -#define TC0_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ - -#define TC0_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ -#define TC0_PERBV_bp 0 /* Period Buffer Valid bit position. */ - -/* TC0.CTRLGSET bit masks and bit positions */ -/* TC0_CCDBV Predefined. */ -/* TC0_CCDBV Predefined. */ - -/* TC0_CCCBV Predefined. */ -/* TC0_CCCBV Predefined. */ - -/* TC0_CCBBV Predefined. */ -/* TC0_CCBBV Predefined. */ - -/* TC0_CCABV Predefined. */ -/* TC0_CCABV Predefined. */ - -/* TC0_PERBV Predefined. */ -/* TC0_PERBV Predefined. */ - -/* TC0.INTFLAGS bit masks and bit positions */ -#define TC0_CCDIF_bm 0x80 /* Compare or Capture D Interrupt Flag bit mask. */ -#define TC0_CCDIF_bp 7 /* Compare or Capture D Interrupt Flag bit position. */ - -#define TC0_CCCIF_bm 0x40 /* Compare or Capture C Interrupt Flag bit mask. */ -#define TC0_CCCIF_bp 6 /* Compare or Capture C Interrupt Flag bit position. */ - -#define TC0_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ -#define TC0_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ - -#define TC0_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ -#define TC0_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ - -#define TC0_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ -#define TC0_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ - -#define TC0_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ -#define TC0_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ - -/* TC1.CTRLA bit masks and bit positions */ -#define TC1_CLKSEL_gm 0x0F /* Clock Selection group mask. */ -#define TC1_CLKSEL_gp 0 /* Clock Selection group position. */ -#define TC1_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ -#define TC1_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ -#define TC1_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ -#define TC1_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ -#define TC1_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ -#define TC1_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ -#define TC1_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ -#define TC1_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ - -/* TC1.CTRLB bit masks and bit positions */ -#define TC1_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ -#define TC1_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ - -#define TC1_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ -#define TC1_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ - -#define TC1_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ -#define TC1_WGMODE_gp 0 /* Waveform generation mode group position. */ -#define TC1_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ -#define TC1_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ -#define TC1_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ -#define TC1_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ -#define TC1_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ -#define TC1_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ - -/* TC1.CTRLC bit masks and bit positions */ -#define TC1_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ -#define TC1_CMPB_bp 1 /* Compare B Output Value bit position. */ - -#define TC1_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ -#define TC1_CMPA_bp 0 /* Compare A Output Value bit position. */ - -/* TC1.CTRLD bit masks and bit positions */ -#define TC1_EVACT_gm 0xE0 /* Event Action group mask. */ -#define TC1_EVACT_gp 5 /* Event Action group position. */ -#define TC1_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ -#define TC1_EVACT0_bp 5 /* Event Action bit 0 position. */ -#define TC1_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ -#define TC1_EVACT1_bp 6 /* Event Action bit 1 position. */ -#define TC1_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ -#define TC1_EVACT2_bp 7 /* Event Action bit 2 position. */ - -#define TC1_EVDLY_bm 0x10 /* Event Delay bit mask. */ -#define TC1_EVDLY_bp 4 /* Event Delay bit position. */ - -#define TC1_EVSEL_gm 0x0F /* Event Source Select group mask. */ -#define TC1_EVSEL_gp 0 /* Event Source Select group position. */ -#define TC1_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ -#define TC1_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ -#define TC1_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ -#define TC1_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ -#define TC1_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ -#define TC1_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ -#define TC1_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ -#define TC1_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ - -/* TC1.CTRLE bit masks and bit positions */ -#define TC1_BYTEM_bm 0x01 /* Byte Mode bit mask. */ -#define TC1_BYTEM_bp 0 /* Byte Mode bit position. */ - -/* TC1.INTCTRLA bit masks and bit positions */ -#define TC1_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ -#define TC1_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ -#define TC1_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ -#define TC1_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ -#define TC1_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ -#define TC1_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ - -#define TC1_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ -#define TC1_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ -#define TC1_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ -#define TC1_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ -#define TC1_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ -#define TC1_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ - -/* TC1.INTCTRLB bit masks and bit positions */ -#define TC1_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ -#define TC1_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ -#define TC1_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ -#define TC1_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ -#define TC1_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ -#define TC1_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ - -#define TC1_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ -#define TC1_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ -#define TC1_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ -#define TC1_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ -#define TC1_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ -#define TC1_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ - -/* TC1.CTRLFCLR bit masks and bit positions */ -#define TC1_CMD_gm 0x0C /* Command group mask. */ -#define TC1_CMD_gp 2 /* Command group position. */ -#define TC1_CMD0_bm (1<<2) /* Command bit 0 mask. */ -#define TC1_CMD0_bp 2 /* Command bit 0 position. */ -#define TC1_CMD1_bm (1<<3) /* Command bit 1 mask. */ -#define TC1_CMD1_bp 3 /* Command bit 1 position. */ - -#define TC1_LUPD_bm 0x02 /* Lock Update bit mask. */ -#define TC1_LUPD_bp 1 /* Lock Update bit position. */ - -#define TC1_DIR_bm 0x01 /* Direction bit mask. */ -#define TC1_DIR_bp 0 /* Direction bit position. */ - -/* TC1.CTRLFSET bit masks and bit positions */ -/* TC1_CMD Predefined. */ -/* TC1_CMD Predefined. */ - -/* TC1_LUPD Predefined. */ -/* TC1_LUPD Predefined. */ - -/* TC1_DIR Predefined. */ -/* TC1_DIR Predefined. */ - -/* TC1.CTRLGCLR bit masks and bit positions */ -#define TC1_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ -#define TC1_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ - -#define TC1_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ -#define TC1_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ - -#define TC1_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ -#define TC1_PERBV_bp 0 /* Period Buffer Valid bit position. */ - -/* TC1.CTRLGSET bit masks and bit positions */ -/* TC1_CCBBV Predefined. */ -/* TC1_CCBBV Predefined. */ - -/* TC1_CCABV Predefined. */ -/* TC1_CCABV Predefined. */ - -/* TC1_PERBV Predefined. */ -/* TC1_PERBV Predefined. */ - -/* TC1.INTFLAGS bit masks and bit positions */ -#define TC1_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ -#define TC1_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ - -#define TC1_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ -#define TC1_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ - -#define TC1_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ -#define TC1_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ - -#define TC1_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ -#define TC1_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ - -/* TC2 - 16-bit Timer/Counter type 2 */ -/* TC2.CTRLA bit masks and bit positions */ -#define TC2_CLKSEL_gm 0x0F /* Clock Selection group mask. */ -#define TC2_CLKSEL_gp 0 /* Clock Selection group position. */ -#define TC2_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ -#define TC2_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ -#define TC2_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ -#define TC2_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ -#define TC2_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ -#define TC2_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ -#define TC2_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ -#define TC2_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ - -/* TC2.CTRLB bit masks and bit positions */ -#define TC2_HCMPDEN_bm 0x80 /* High Byte Compare D Enable bit mask. */ -#define TC2_HCMPDEN_bp 7 /* High Byte Compare D Enable bit position. */ - -#define TC2_HCMPCEN_bm 0x40 /* High Byte Compare C Enable bit mask. */ -#define TC2_HCMPCEN_bp 6 /* High Byte Compare C Enable bit position. */ - -#define TC2_HCMPBEN_bm 0x20 /* High Byte Compare B Enable bit mask. */ -#define TC2_HCMPBEN_bp 5 /* High Byte Compare B Enable bit position. */ - -#define TC2_HCMPAEN_bm 0x10 /* High Byte Compare A Enable bit mask. */ -#define TC2_HCMPAEN_bp 4 /* High Byte Compare A Enable bit position. */ - -#define TC2_LCMPDEN_bm 0x08 /* Low Byte Compare D Enable bit mask. */ -#define TC2_LCMPDEN_bp 3 /* Low Byte Compare D Enable bit position. */ - -#define TC2_LCMPCEN_bm 0x04 /* Low Byte Compare C Enable bit mask. */ -#define TC2_LCMPCEN_bp 2 /* Low Byte Compare C Enable bit position. */ - -#define TC2_LCMPBEN_bm 0x02 /* Low Byte Compare B Enable bit mask. */ -#define TC2_LCMPBEN_bp 1 /* Low Byte Compare B Enable bit position. */ - -#define TC2_LCMPAEN_bm 0x01 /* Low Byte Compare A Enable bit mask. */ -#define TC2_LCMPAEN_bp 0 /* Low Byte Compare A Enable bit position. */ - -/* TC2.CTRLC bit masks and bit positions */ -#define TC2_HCMPD_bm 0x80 /* High Byte Compare D Output Value bit mask. */ -#define TC2_HCMPD_bp 7 /* High Byte Compare D Output Value bit position. */ - -#define TC2_HCMPC_bm 0x40 /* High Byte Compare C Output Value bit mask. */ -#define TC2_HCMPC_bp 6 /* High Byte Compare C Output Value bit position. */ - -#define TC2_HCMPB_bm 0x20 /* High Byte Compare B Output Value bit mask. */ -#define TC2_HCMPB_bp 5 /* High Byte Compare B Output Value bit position. */ - -#define TC2_HCMPA_bm 0x10 /* High Byte Compare A Output Value bit mask. */ -#define TC2_HCMPA_bp 4 /* High Byte Compare A Output Value bit position. */ - -#define TC2_LCMPD_bm 0x08 /* Low Byte Compare D Output Value bit mask. */ -#define TC2_LCMPD_bp 3 /* Low Byte Compare D Output Value bit position. */ - -#define TC2_LCMPC_bm 0x04 /* Low Byte Compare C Output Value bit mask. */ -#define TC2_LCMPC_bp 2 /* Low Byte Compare C Output Value bit position. */ - -#define TC2_LCMPB_bm 0x02 /* Low Byte Compare B Output Value bit mask. */ -#define TC2_LCMPB_bp 1 /* Low Byte Compare B Output Value bit position. */ - -#define TC2_LCMPA_bm 0x01 /* Low Byte Compare A Output Value bit mask. */ -#define TC2_LCMPA_bp 0 /* Low Byte Compare A Output Value bit position. */ - -/* TC2.CTRLE bit masks and bit positions */ -#define TC2_BYTEM_gm 0x03 /* Byte Mode group mask. */ -#define TC2_BYTEM_gp 0 /* Byte Mode group position. */ -#define TC2_BYTEM0_bm (1<<0) /* Byte Mode bit 0 mask. */ -#define TC2_BYTEM0_bp 0 /* Byte Mode bit 0 position. */ -#define TC2_BYTEM1_bm (1<<1) /* Byte Mode bit 1 mask. */ -#define TC2_BYTEM1_bp 1 /* Byte Mode bit 1 position. */ - -/* TC2.INTCTRLA bit masks and bit positions */ -#define TC2_HUNFINTLVL_gm 0x0C /* High Byte Underflow Interrupt Level group mask. */ -#define TC2_HUNFINTLVL_gp 2 /* High Byte Underflow Interrupt Level group position. */ -#define TC2_HUNFINTLVL0_bm (1<<2) /* High Byte Underflow Interrupt Level bit 0 mask. */ -#define TC2_HUNFINTLVL0_bp 2 /* High Byte Underflow Interrupt Level bit 0 position. */ -#define TC2_HUNFINTLVL1_bm (1<<3) /* High Byte Underflow Interrupt Level bit 1 mask. */ -#define TC2_HUNFINTLVL1_bp 3 /* High Byte Underflow Interrupt Level bit 1 position. */ - -#define TC2_LUNFINTLVL_gm 0x03 /* Low Byte Underflow interrupt level group mask. */ -#define TC2_LUNFINTLVL_gp 0 /* Low Byte Underflow interrupt level group position. */ -#define TC2_LUNFINTLVL0_bm (1<<0) /* Low Byte Underflow interrupt level bit 0 mask. */ -#define TC2_LUNFINTLVL0_bp 0 /* Low Byte Underflow interrupt level bit 0 position. */ -#define TC2_LUNFINTLVL1_bm (1<<1) /* Low Byte Underflow interrupt level bit 1 mask. */ -#define TC2_LUNFINTLVL1_bp 1 /* Low Byte Underflow interrupt level bit 1 position. */ - -/* TC2.INTCTRLB bit masks and bit positions */ -#define TC2_LCMPDINTLVL_gm 0xC0 /* Low Byte Compare D Interrupt Level group mask. */ -#define TC2_LCMPDINTLVL_gp 6 /* Low Byte Compare D Interrupt Level group position. */ -#define TC2_LCMPDINTLVL0_bm (1<<6) /* Low Byte Compare D Interrupt Level bit 0 mask. */ -#define TC2_LCMPDINTLVL0_bp 6 /* Low Byte Compare D Interrupt Level bit 0 position. */ -#define TC2_LCMPDINTLVL1_bm (1<<7) /* Low Byte Compare D Interrupt Level bit 1 mask. */ -#define TC2_LCMPDINTLVL1_bp 7 /* Low Byte Compare D Interrupt Level bit 1 position. */ - -#define TC2_LCMPCINTLVL_gm 0x30 /* Low Byte Compare C Interrupt Level group mask. */ -#define TC2_LCMPCINTLVL_gp 4 /* Low Byte Compare C Interrupt Level group position. */ -#define TC2_LCMPCINTLVL0_bm (1<<4) /* Low Byte Compare C Interrupt Level bit 0 mask. */ -#define TC2_LCMPCINTLVL0_bp 4 /* Low Byte Compare C Interrupt Level bit 0 position. */ -#define TC2_LCMPCINTLVL1_bm (1<<5) /* Low Byte Compare C Interrupt Level bit 1 mask. */ -#define TC2_LCMPCINTLVL1_bp 5 /* Low Byte Compare C Interrupt Level bit 1 position. */ - -#define TC2_LCMPBINTLVL_gm 0x0C /* Low Byte Compare B Interrupt Level group mask. */ -#define TC2_LCMPBINTLVL_gp 2 /* Low Byte Compare B Interrupt Level group position. */ -#define TC2_LCMPBINTLVL0_bm (1<<2) /* Low Byte Compare B Interrupt Level bit 0 mask. */ -#define TC2_LCMPBINTLVL0_bp 2 /* Low Byte Compare B Interrupt Level bit 0 position. */ -#define TC2_LCMPBINTLVL1_bm (1<<3) /* Low Byte Compare B Interrupt Level bit 1 mask. */ -#define TC2_LCMPBINTLVL1_bp 3 /* Low Byte Compare B Interrupt Level bit 1 position. */ - -#define TC2_LCMPAINTLVL_gm 0x03 /* Low Byte Compare A Interrupt Level group mask. */ -#define TC2_LCMPAINTLVL_gp 0 /* Low Byte Compare A Interrupt Level group position. */ -#define TC2_LCMPAINTLVL0_bm (1<<0) /* Low Byte Compare A Interrupt Level bit 0 mask. */ -#define TC2_LCMPAINTLVL0_bp 0 /* Low Byte Compare A Interrupt Level bit 0 position. */ -#define TC2_LCMPAINTLVL1_bm (1<<1) /* Low Byte Compare A Interrupt Level bit 1 mask. */ -#define TC2_LCMPAINTLVL1_bp 1 /* Low Byte Compare A Interrupt Level bit 1 position. */ - -/* TC2.CTRLF bit masks and bit positions */ -#define TC2_CMD_gm 0x0C /* Command group mask. */ -#define TC2_CMD_gp 2 /* Command group position. */ -#define TC2_CMD0_bm (1<<2) /* Command bit 0 mask. */ -#define TC2_CMD0_bp 2 /* Command bit 0 position. */ -#define TC2_CMD1_bm (1<<3) /* Command bit 1 mask. */ -#define TC2_CMD1_bp 3 /* Command bit 1 position. */ - -#define TC2_CMDEN_gm 0x03 /* Command Enable group mask. */ -#define TC2_CMDEN_gp 0 /* Command Enable group position. */ -#define TC2_CMDEN0_bm (1<<0) /* Command Enable bit 0 mask. */ -#define TC2_CMDEN0_bp 0 /* Command Enable bit 0 position. */ -#define TC2_CMDEN1_bm (1<<1) /* Command Enable bit 1 mask. */ -#define TC2_CMDEN1_bp 1 /* Command Enable bit 1 position. */ - -/* TC2.INTFLAGS bit masks and bit positions */ -#define TC2_LCMPDIF_bm 0x80 /* Low Byte Compare D Interrupt Flag bit mask. */ -#define TC2_LCMPDIF_bp 7 /* Low Byte Compare D Interrupt Flag bit position. */ - -#define TC2_LCMPCIF_bm 0x40 /* Low Byte Compare C Interrupt Flag bit mask. */ -#define TC2_LCMPCIF_bp 6 /* Low Byte Compare C Interrupt Flag bit position. */ - -#define TC2_LCMPBIF_bm 0x20 /* Low Byte Compare B Interrupt Flag bit mask. */ -#define TC2_LCMPBIF_bp 5 /* Low Byte Compare B Interrupt Flag bit position. */ - -#define TC2_LCMPAIF_bm 0x10 /* Low Byte Compare A Interrupt Flag bit mask. */ -#define TC2_LCMPAIF_bp 4 /* Low Byte Compare A Interrupt Flag bit position. */ - -#define TC2_HUNFIF_bm 0x02 /* High Byte Underflow Interrupt Flag bit mask. */ -#define TC2_HUNFIF_bp 1 /* High Byte Underflow Interrupt Flag bit position. */ - -#define TC2_LUNFIF_bm 0x01 /* Low Byte Underflow Interrupt Flag bit mask. */ -#define TC2_LUNFIF_bp 0 /* Low Byte Underflow Interrupt Flag bit position. */ - -/* AWEX - Timer/Counter Advanced Waveform Extension */ -/* AWEX.CTRL bit masks and bit positions */ -#define AWEX_PGM_bm 0x20 /* Pattern Generation Mode bit mask. */ -#define AWEX_PGM_bp 5 /* Pattern Generation Mode bit position. */ - -#define AWEX_CWCM_bm 0x10 /* Common Waveform Channel Mode bit mask. */ -#define AWEX_CWCM_bp 4 /* Common Waveform Channel Mode bit position. */ - -#define AWEX_DTICCDEN_bm 0x08 /* Dead Time Insertion Compare Channel D Enable bit mask. */ -#define AWEX_DTICCDEN_bp 3 /* Dead Time Insertion Compare Channel D Enable bit position. */ - -#define AWEX_DTICCCEN_bm 0x04 /* Dead Time Insertion Compare Channel C Enable bit mask. */ -#define AWEX_DTICCCEN_bp 2 /* Dead Time Insertion Compare Channel C Enable bit position. */ - -#define AWEX_DTICCBEN_bm 0x02 /* Dead Time Insertion Compare Channel B Enable bit mask. */ -#define AWEX_DTICCBEN_bp 1 /* Dead Time Insertion Compare Channel B Enable bit position. */ - -#define AWEX_DTICCAEN_bm 0x01 /* Dead Time Insertion Compare Channel A Enable bit mask. */ -#define AWEX_DTICCAEN_bp 0 /* Dead Time Insertion Compare Channel A Enable bit position. */ - -/* AWEX.FDCTRL bit masks and bit positions */ -#define AWEX_FDDBD_bm 0x10 /* Fault Detect on Disable Break Disable bit mask. */ -#define AWEX_FDDBD_bp 4 /* Fault Detect on Disable Break Disable bit position. */ - -#define AWEX_FDMODE_bm 0x04 /* Fault Detect Mode bit mask. */ -#define AWEX_FDMODE_bp 2 /* Fault Detect Mode bit position. */ - -#define AWEX_FDACT_gm 0x03 /* Fault Detect Action group mask. */ -#define AWEX_FDACT_gp 0 /* Fault Detect Action group position. */ -#define AWEX_FDACT0_bm (1<<0) /* Fault Detect Action bit 0 mask. */ -#define AWEX_FDACT0_bp 0 /* Fault Detect Action bit 0 position. */ -#define AWEX_FDACT1_bm (1<<1) /* Fault Detect Action bit 1 mask. */ -#define AWEX_FDACT1_bp 1 /* Fault Detect Action bit 1 position. */ - -/* AWEX.STATUS bit masks and bit positions */ -#define AWEX_FDF_bm 0x04 /* Fault Detect Flag bit mask. */ -#define AWEX_FDF_bp 2 /* Fault Detect Flag bit position. */ - -#define AWEX_DTHSBUFV_bm 0x02 /* Dead Time High Side Buffer Valid bit mask. */ -#define AWEX_DTHSBUFV_bp 1 /* Dead Time High Side Buffer Valid bit position. */ - -#define AWEX_DTLSBUFV_bm 0x01 /* Dead Time Low Side Buffer Valid bit mask. */ -#define AWEX_DTLSBUFV_bp 0 /* Dead Time Low Side Buffer Valid bit position. */ - -/* AWEX.STATUSSET bit masks and bit positions */ -/* AWEX_FDF Predefined. */ -/* AWEX_FDF Predefined. */ - -/* AWEX_DTHSBUFV Predefined. */ -/* AWEX_DTHSBUFV Predefined. */ - -/* AWEX_DTLSBUFV Predefined. */ -/* AWEX_DTLSBUFV Predefined. */ - -/* HIRES - Timer/Counter High-Resolution Extension */ -/* HIRES.CTRLA bit masks and bit positions */ -#define HIRES_HREN_gm 0x03 /* High Resolution Enable group mask. */ -#define HIRES_HREN_gp 0 /* High Resolution Enable group position. */ -#define HIRES_HREN0_bm (1<<0) /* High Resolution Enable bit 0 mask. */ -#define HIRES_HREN0_bp 0 /* High Resolution Enable bit 0 position. */ -#define HIRES_HREN1_bm (1<<1) /* High Resolution Enable bit 1 mask. */ -#define HIRES_HREN1_bp 1 /* High Resolution Enable bit 1 position. */ - -/* USART - Universal Asynchronous Receiver-Transmitter */ -/* USART.STATUS bit masks and bit positions */ -#define USART_RXCIF_bm 0x80 /* Receive Interrupt Flag bit mask. */ -#define USART_RXCIF_bp 7 /* Receive Interrupt Flag bit position. */ - -#define USART_TXCIF_bm 0x40 /* Transmit Interrupt Flag bit mask. */ -#define USART_TXCIF_bp 6 /* Transmit Interrupt Flag bit position. */ - -#define USART_DREIF_bm 0x20 /* Data Register Empty Flag bit mask. */ -#define USART_DREIF_bp 5 /* Data Register Empty Flag bit position. */ - -#define USART_FERR_bm 0x10 /* Frame Error bit mask. */ -#define USART_FERR_bp 4 /* Frame Error bit position. */ - -#define USART_BUFOVF_bm 0x08 /* Buffer Overflow bit mask. */ -#define USART_BUFOVF_bp 3 /* Buffer Overflow bit position. */ - -#define USART_PERR_bm 0x04 /* Parity Error bit mask. */ -#define USART_PERR_bp 2 /* Parity Error bit position. */ - -#define USART_RXB8_bm 0x01 /* Receive Bit 8 bit mask. */ -#define USART_RXB8_bp 0 /* Receive Bit 8 bit position. */ - -/* USART.CTRLA bit masks and bit positions */ -#define USART_RXCINTLVL_gm 0x30 /* Receive Interrupt Level group mask. */ -#define USART_RXCINTLVL_gp 4 /* Receive Interrupt Level group position. */ -#define USART_RXCINTLVL0_bm (1<<4) /* Receive Interrupt Level bit 0 mask. */ -#define USART_RXCINTLVL0_bp 4 /* Receive Interrupt Level bit 0 position. */ -#define USART_RXCINTLVL1_bm (1<<5) /* Receive Interrupt Level bit 1 mask. */ -#define USART_RXCINTLVL1_bp 5 /* Receive Interrupt Level bit 1 position. */ - -#define USART_TXCINTLVL_gm 0x0C /* Transmit Interrupt Level group mask. */ -#define USART_TXCINTLVL_gp 2 /* Transmit Interrupt Level group position. */ -#define USART_TXCINTLVL0_bm (1<<2) /* Transmit Interrupt Level bit 0 mask. */ -#define USART_TXCINTLVL0_bp 2 /* Transmit Interrupt Level bit 0 position. */ -#define USART_TXCINTLVL1_bm (1<<3) /* Transmit Interrupt Level bit 1 mask. */ -#define USART_TXCINTLVL1_bp 3 /* Transmit Interrupt Level bit 1 position. */ - -#define USART_DREINTLVL_gm 0x03 /* Data Register Empty Interrupt Level group mask. */ -#define USART_DREINTLVL_gp 0 /* Data Register Empty Interrupt Level group position. */ -#define USART_DREINTLVL0_bm (1<<0) /* Data Register Empty Interrupt Level bit 0 mask. */ -#define USART_DREINTLVL0_bp 0 /* Data Register Empty Interrupt Level bit 0 position. */ -#define USART_DREINTLVL1_bm (1<<1) /* Data Register Empty Interrupt Level bit 1 mask. */ -#define USART_DREINTLVL1_bp 1 /* Data Register Empty Interrupt Level bit 1 position. */ - -/* USART.CTRLB bit masks and bit positions */ -#define USART_RXEN_bm 0x10 /* Receiver Enable bit mask. */ -#define USART_RXEN_bp 4 /* Receiver Enable bit position. */ - -#define USART_TXEN_bm 0x08 /* Transmitter Enable bit mask. */ -#define USART_TXEN_bp 3 /* Transmitter Enable bit position. */ - -#define USART_CLK2X_bm 0x04 /* Double transmission speed bit mask. */ -#define USART_CLK2X_bp 2 /* Double transmission speed bit position. */ - -#define USART_MPCM_bm 0x02 /* Multi-processor Communication Mode bit mask. */ -#define USART_MPCM_bp 1 /* Multi-processor Communication Mode bit position. */ - -#define USART_TXB8_bm 0x01 /* Transmit bit 8 bit mask. */ -#define USART_TXB8_bp 0 /* Transmit bit 8 bit position. */ - -/* USART.CTRLC bit masks and bit positions */ -#define USART_CMODE_gm 0xC0 /* Communication Mode group mask. */ -#define USART_CMODE_gp 6 /* Communication Mode group position. */ -#define USART_CMODE0_bm (1<<6) /* Communication Mode bit 0 mask. */ -#define USART_CMODE0_bp 6 /* Communication Mode bit 0 position. */ -#define USART_CMODE1_bm (1<<7) /* Communication Mode bit 1 mask. */ -#define USART_CMODE1_bp 7 /* Communication Mode bit 1 position. */ - -#define USART_PMODE_gm 0x30 /* Parity Mode group mask. */ -#define USART_PMODE_gp 4 /* Parity Mode group position. */ -#define USART_PMODE0_bm (1<<4) /* Parity Mode bit 0 mask. */ -#define USART_PMODE0_bp 4 /* Parity Mode bit 0 position. */ -#define USART_PMODE1_bm (1<<5) /* Parity Mode bit 1 mask. */ -#define USART_PMODE1_bp 5 /* Parity Mode bit 1 position. */ - -#define USART_SBMODE_bm 0x08 /* Stop Bit Mode bit mask. */ -#define USART_SBMODE_bp 3 /* Stop Bit Mode bit position. */ - -#define USART_CHSIZE_gm 0x07 /* Character Size group mask. */ -#define USART_CHSIZE_gp 0 /* Character Size group position. */ -#define USART_CHSIZE0_bm (1<<0) /* Character Size bit 0 mask. */ -#define USART_CHSIZE0_bp 0 /* Character Size bit 0 position. */ -#define USART_CHSIZE1_bm (1<<1) /* Character Size bit 1 mask. */ -#define USART_CHSIZE1_bp 1 /* Character Size bit 1 position. */ -#define USART_CHSIZE2_bm (1<<2) /* Character Size bit 2 mask. */ -#define USART_CHSIZE2_bp 2 /* Character Size bit 2 position. */ - -/* USART.BAUDCTRLA bit masks and bit positions */ -#define USART_BSEL_gm 0xFF /* Baud Rate Selection Bits [7:0] group mask. */ -#define USART_BSEL_gp 0 /* Baud Rate Selection Bits [7:0] group position. */ -#define USART_BSEL0_bm (1<<0) /* Baud Rate Selection Bits [7:0] bit 0 mask. */ -#define USART_BSEL0_bp 0 /* Baud Rate Selection Bits [7:0] bit 0 position. */ -#define USART_BSEL1_bm (1<<1) /* Baud Rate Selection Bits [7:0] bit 1 mask. */ -#define USART_BSEL1_bp 1 /* Baud Rate Selection Bits [7:0] bit 1 position. */ -#define USART_BSEL2_bm (1<<2) /* Baud Rate Selection Bits [7:0] bit 2 mask. */ -#define USART_BSEL2_bp 2 /* Baud Rate Selection Bits [7:0] bit 2 position. */ -#define USART_BSEL3_bm (1<<3) /* Baud Rate Selection Bits [7:0] bit 3 mask. */ -#define USART_BSEL3_bp 3 /* Baud Rate Selection Bits [7:0] bit 3 position. */ -#define USART_BSEL4_bm (1<<4) /* Baud Rate Selection Bits [7:0] bit 4 mask. */ -#define USART_BSEL4_bp 4 /* Baud Rate Selection Bits [7:0] bit 4 position. */ -#define USART_BSEL5_bm (1<<5) /* Baud Rate Selection Bits [7:0] bit 5 mask. */ -#define USART_BSEL5_bp 5 /* Baud Rate Selection Bits [7:0] bit 5 position. */ -#define USART_BSEL6_bm (1<<6) /* Baud Rate Selection Bits [7:0] bit 6 mask. */ -#define USART_BSEL6_bp 6 /* Baud Rate Selection Bits [7:0] bit 6 position. */ -#define USART_BSEL7_bm (1<<7) /* Baud Rate Selection Bits [7:0] bit 7 mask. */ -#define USART_BSEL7_bp 7 /* Baud Rate Selection Bits [7:0] bit 7 position. */ - -/* USART.BAUDCTRLB bit masks and bit positions */ -#define USART_BSCALE_gm 0xF0 /* Baud Rate Scale group mask. */ -#define USART_BSCALE_gp 4 /* Baud Rate Scale group position. */ -#define USART_BSCALE0_bm (1<<4) /* Baud Rate Scale bit 0 mask. */ -#define USART_BSCALE0_bp 4 /* Baud Rate Scale bit 0 position. */ -#define USART_BSCALE1_bm (1<<5) /* Baud Rate Scale bit 1 mask. */ -#define USART_BSCALE1_bp 5 /* Baud Rate Scale bit 1 position. */ -#define USART_BSCALE2_bm (1<<6) /* Baud Rate Scale bit 2 mask. */ -#define USART_BSCALE2_bp 6 /* Baud Rate Scale bit 2 position. */ -#define USART_BSCALE3_bm (1<<7) /* Baud Rate Scale bit 3 mask. */ -#define USART_BSCALE3_bp 7 /* Baud Rate Scale bit 3 position. */ - -/* USART_BSEL Predefined. */ -/* USART_BSEL Predefined. */ - -/* SPI - Serial Peripheral Interface */ -/* SPI.CTRL bit masks and bit positions */ -#define SPI_CLK2X_bm 0x80 /* Enable Double Speed bit mask. */ -#define SPI_CLK2X_bp 7 /* Enable Double Speed bit position. */ - -#define SPI_ENABLE_bm 0x40 /* Enable Module bit mask. */ -#define SPI_ENABLE_bp 6 /* Enable Module bit position. */ - -#define SPI_DORD_bm 0x20 /* Data Order Setting bit mask. */ -#define SPI_DORD_bp 5 /* Data Order Setting bit position. */ - -#define SPI_MASTER_bm 0x10 /* Master Operation Enable bit mask. */ -#define SPI_MASTER_bp 4 /* Master Operation Enable bit position. */ - -#define SPI_MODE_gm 0x0C /* SPI Mode group mask. */ -#define SPI_MODE_gp 2 /* SPI Mode group position. */ -#define SPI_MODE0_bm (1<<2) /* SPI Mode bit 0 mask. */ -#define SPI_MODE0_bp 2 /* SPI Mode bit 0 position. */ -#define SPI_MODE1_bm (1<<3) /* SPI Mode bit 1 mask. */ -#define SPI_MODE1_bp 3 /* SPI Mode bit 1 position. */ - -#define SPI_PRESCALER_gm 0x03 /* Prescaler group mask. */ -#define SPI_PRESCALER_gp 0 /* Prescaler group position. */ -#define SPI_PRESCALER0_bm (1<<0) /* Prescaler bit 0 mask. */ -#define SPI_PRESCALER0_bp 0 /* Prescaler bit 0 position. */ -#define SPI_PRESCALER1_bm (1<<1) /* Prescaler bit 1 mask. */ -#define SPI_PRESCALER1_bp 1 /* Prescaler bit 1 position. */ - -/* SPI.INTCTRL bit masks and bit positions */ -#define SPI_INTLVL_gm 0x03 /* Interrupt level group mask. */ -#define SPI_INTLVL_gp 0 /* Interrupt level group position. */ -#define SPI_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */ -#define SPI_INTLVL0_bp 0 /* Interrupt level bit 0 position. */ -#define SPI_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */ -#define SPI_INTLVL1_bp 1 /* Interrupt level bit 1 position. */ - -/* SPI.STATUS bit masks and bit positions */ -#define SPI_IF_bm 0x80 /* Interrupt Flag bit mask. */ -#define SPI_IF_bp 7 /* Interrupt Flag bit position. */ - -#define SPI_WRCOL_bm 0x40 /* Write Collision bit mask. */ -#define SPI_WRCOL_bp 6 /* Write Collision bit position. */ - -/* IRCOM - IR Communication Module */ -/* IRCOM.CTRL bit masks and bit positions */ -#define IRCOM_EVSEL_gm 0x0F /* Event Channel Select group mask. */ -#define IRCOM_EVSEL_gp 0 /* Event Channel Select group position. */ -#define IRCOM_EVSEL0_bm (1<<0) /* Event Channel Select bit 0 mask. */ -#define IRCOM_EVSEL0_bp 0 /* Event Channel Select bit 0 position. */ -#define IRCOM_EVSEL1_bm (1<<1) /* Event Channel Select bit 1 mask. */ -#define IRCOM_EVSEL1_bp 1 /* Event Channel Select bit 1 position. */ -#define IRCOM_EVSEL2_bm (1<<2) /* Event Channel Select bit 2 mask. */ -#define IRCOM_EVSEL2_bp 2 /* Event Channel Select bit 2 position. */ -#define IRCOM_EVSEL3_bm (1<<3) /* Event Channel Select bit 3 mask. */ -#define IRCOM_EVSEL3_bp 3 /* Event Channel Select bit 3 position. */ - -/* FUSE - Fuses and Lockbits */ -/* NVM_FUSES.FUSEBYTE1 bit masks and bit positions */ -#define NVM_FUSES_WDWP_gm 0xF0 /* Watchdog Window Timeout Period group mask. */ -#define NVM_FUSES_WDWP_gp 4 /* Watchdog Window Timeout Period group position. */ -#define NVM_FUSES_WDWP0_bm (1<<4) /* Watchdog Window Timeout Period bit 0 mask. */ -#define NVM_FUSES_WDWP0_bp 4 /* Watchdog Window Timeout Period bit 0 position. */ -#define NVM_FUSES_WDWP1_bm (1<<5) /* Watchdog Window Timeout Period bit 1 mask. */ -#define NVM_FUSES_WDWP1_bp 5 /* Watchdog Window Timeout Period bit 1 position. */ -#define NVM_FUSES_WDWP2_bm (1<<6) /* Watchdog Window Timeout Period bit 2 mask. */ -#define NVM_FUSES_WDWP2_bp 6 /* Watchdog Window Timeout Period bit 2 position. */ -#define NVM_FUSES_WDWP3_bm (1<<7) /* Watchdog Window Timeout Period bit 3 mask. */ -#define NVM_FUSES_WDWP3_bp 7 /* Watchdog Window Timeout Period bit 3 position. */ - -#define NVM_FUSES_WDP_gm 0x0F /* Watchdog Timeout Period group mask. */ -#define NVM_FUSES_WDP_gp 0 /* Watchdog Timeout Period group position. */ -#define NVM_FUSES_WDP0_bm (1<<0) /* Watchdog Timeout Period bit 0 mask. */ -#define NVM_FUSES_WDP0_bp 0 /* Watchdog Timeout Period bit 0 position. */ -#define NVM_FUSES_WDP1_bm (1<<1) /* Watchdog Timeout Period bit 1 mask. */ -#define NVM_FUSES_WDP1_bp 1 /* Watchdog Timeout Period bit 1 position. */ -#define NVM_FUSES_WDP2_bm (1<<2) /* Watchdog Timeout Period bit 2 mask. */ -#define NVM_FUSES_WDP2_bp 2 /* Watchdog Timeout Period bit 2 position. */ -#define NVM_FUSES_WDP3_bm (1<<3) /* Watchdog Timeout Period bit 3 mask. */ -#define NVM_FUSES_WDP3_bp 3 /* Watchdog Timeout Period bit 3 position. */ - -/* NVM_FUSES.FUSEBYTE2 bit masks and bit positions */ -#define NVM_FUSES_BOOTRST_bm 0x40 /* Boot Loader Section Reset Vector bit mask. */ -#define NVM_FUSES_BOOTRST_bp 6 /* Boot Loader Section Reset Vector bit position. */ - -#define NVM_FUSES_TOSCSEL_bm 0x20 /* Timer Oscillator pin location bit mask. */ -#define NVM_FUSES_TOSCSEL_bp 5 /* Timer Oscillator pin location bit position. */ - -#define NVM_FUSES_BODPD_gm 0x03 /* BOD Operation in Power-Down Mode group mask. */ -#define NVM_FUSES_BODPD_gp 0 /* BOD Operation in Power-Down Mode group position. */ -#define NVM_FUSES_BODPD0_bm (1<<0) /* BOD Operation in Power-Down Mode bit 0 mask. */ -#define NVM_FUSES_BODPD0_bp 0 /* BOD Operation in Power-Down Mode bit 0 position. */ -#define NVM_FUSES_BODPD1_bm (1<<1) /* BOD Operation in Power-Down Mode bit 1 mask. */ -#define NVM_FUSES_BODPD1_bp 1 /* BOD Operation in Power-Down Mode bit 1 position. */ - -/* NVM_FUSES.FUSEBYTE4 bit masks and bit positions */ -#define NVM_FUSES_RSTDISBL_bm 0x10 /* External Reset Disable bit mask. */ -#define NVM_FUSES_RSTDISBL_bp 4 /* External Reset Disable bit position. */ - -#define NVM_FUSES_SUT_gm 0x0C /* Start-up Time group mask. */ -#define NVM_FUSES_SUT_gp 2 /* Start-up Time group position. */ -#define NVM_FUSES_SUT0_bm (1<<2) /* Start-up Time bit 0 mask. */ -#define NVM_FUSES_SUT0_bp 2 /* Start-up Time bit 0 position. */ -#define NVM_FUSES_SUT1_bm (1<<3) /* Start-up Time bit 1 mask. */ -#define NVM_FUSES_SUT1_bp 3 /* Start-up Time bit 1 position. */ - -#define NVM_FUSES_WDLOCK_bm 0x02 /* Watchdog Timer Lock bit mask. */ -#define NVM_FUSES_WDLOCK_bp 1 /* Watchdog Timer Lock bit position. */ - -/* NVM_FUSES.FUSEBYTE5 bit masks and bit positions */ -#define NVM_FUSES_BODACT_gm 0x30 /* BOD Operation in Active Mode group mask. */ -#define NVM_FUSES_BODACT_gp 4 /* BOD Operation in Active Mode group position. */ -#define NVM_FUSES_BODACT0_bm (1<<4) /* BOD Operation in Active Mode bit 0 mask. */ -#define NVM_FUSES_BODACT0_bp 4 /* BOD Operation in Active Mode bit 0 position. */ -#define NVM_FUSES_BODACT1_bm (1<<5) /* BOD Operation in Active Mode bit 1 mask. */ -#define NVM_FUSES_BODACT1_bp 5 /* BOD Operation in Active Mode bit 1 position. */ - -#define NVM_FUSES_EESAVE_bm 0x08 /* Preserve EEPROM Through Chip Erase bit mask. */ -#define NVM_FUSES_EESAVE_bp 3 /* Preserve EEPROM Through Chip Erase bit position. */ - -#define NVM_FUSES_BODLVL_gm 0x07 /* Brownout Detection Voltage Level group mask. */ -#define NVM_FUSES_BODLVL_gp 0 /* Brownout Detection Voltage Level group position. */ -#define NVM_FUSES_BODLVL0_bm (1<<0) /* Brownout Detection Voltage Level bit 0 mask. */ -#define NVM_FUSES_BODLVL0_bp 0 /* Brownout Detection Voltage Level bit 0 position. */ -#define NVM_FUSES_BODLVL1_bm (1<<1) /* Brownout Detection Voltage Level bit 1 mask. */ -#define NVM_FUSES_BODLVL1_bp 1 /* Brownout Detection Voltage Level bit 1 position. */ -#define NVM_FUSES_BODLVL2_bm (1<<2) /* Brownout Detection Voltage Level bit 2 mask. */ -#define NVM_FUSES_BODLVL2_bp 2 /* Brownout Detection Voltage Level bit 2 position. */ - -/* LOCKBIT - Fuses and Lockbits */ -/* NVM_LOCKBITS.LOCKBITS bit masks and bit positions */ -#define NVM_LOCKBITS_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ -#define NVM_LOCKBITS_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ -#define NVM_LOCKBITS_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ -#define NVM_LOCKBITS_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ -#define NVM_LOCKBITS_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ -#define NVM_LOCKBITS_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ - -#define NVM_LOCKBITS_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ -#define NVM_LOCKBITS_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ -#define NVM_LOCKBITS_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ -#define NVM_LOCKBITS_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ -#define NVM_LOCKBITS_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ -#define NVM_LOCKBITS_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ - -#define NVM_LOCKBITS_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ -#define NVM_LOCKBITS_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ -#define NVM_LOCKBITS_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ -#define NVM_LOCKBITS_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ -#define NVM_LOCKBITS_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ -#define NVM_LOCKBITS_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ - -#define NVM_LOCKBITS_LB_gm 0x03 /* Lock Bits group mask. */ -#define NVM_LOCKBITS_LB_gp 0 /* Lock Bits group position. */ -#define NVM_LOCKBITS_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ -#define NVM_LOCKBITS_LB0_bp 0 /* Lock Bits bit 0 position. */ -#define NVM_LOCKBITS_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ -#define NVM_LOCKBITS_LB1_bp 1 /* Lock Bits bit 1 position. */ - - - -// Generic Port Pins - -#define PIN0_bm 0x01 -#define PIN0_bp 0 -#define PIN1_bm 0x02 -#define PIN1_bp 1 -#define PIN2_bm 0x04 -#define PIN2_bp 2 -#define PIN3_bm 0x08 -#define PIN3_bp 3 -#define PIN4_bm 0x10 -#define PIN4_bp 4 -#define PIN5_bm 0x20 -#define PIN5_bp 5 -#define PIN6_bm 0x40 -#define PIN6_bp 6 -#define PIN7_bm 0x80 -#define PIN7_bp 7 - -/* ========== Interrupt Vector Definitions ========== */ -/* Vector 0 is the reset vector */ - -/* OSC interrupt vectors */ -#define OSC_OSCF_vect_num 1 -#define OSC_OSCF_vect _VECTOR(1) /* Oscillator Failure Interrupt (NMI) */ - -/* PORTC interrupt vectors */ -#define PORTC_INT0_vect_num 2 -#define PORTC_INT0_vect _VECTOR(2) /* External Interrupt 0 */ -#define PORTC_INT1_vect_num 3 -#define PORTC_INT1_vect _VECTOR(3) /* External Interrupt 1 */ - -/* PORTR interrupt vectors */ -#define PORTR_INT0_vect_num 4 -#define PORTR_INT0_vect _VECTOR(4) /* External Interrupt 0 */ -#define PORTR_INT1_vect_num 5 -#define PORTR_INT1_vect _VECTOR(5) /* External Interrupt 1 */ - -/* DMA interrupt vectors */ -#define DMA_CH0_vect_num 6 -#define DMA_CH0_vect _VECTOR(6) /* Channel 0 Interrupt */ -#define DMA_CH1_vect_num 7 -#define DMA_CH1_vect _VECTOR(7) /* Channel 1 Interrupt */ -#define DMA_CH2_vect_num 8 -#define DMA_CH2_vect _VECTOR(8) /* Channel 2 Interrupt */ -#define DMA_CH3_vect_num 9 -#define DMA_CH3_vect _VECTOR(9) /* Channel 3 Interrupt */ - -/* RTC interrupt vectors */ -#define RTC_OVF_vect_num 10 -#define RTC_OVF_vect _VECTOR(10) /* Overflow Interrupt */ -#define RTC_COMP_vect_num 11 -#define RTC_COMP_vect _VECTOR(11) /* Compare Interrupt */ - -/* TWIC interrupt vectors */ -#define TWIC_TWIS_vect_num 12 -#define TWIC_TWIS_vect _VECTOR(12) /* TWI Slave Interrupt */ -#define TWIC_TWIM_vect_num 13 -#define TWIC_TWIM_vect _VECTOR(13) /* TWI Master Interrupt */ - -/* TCC0 interrupt vectors */ -#define TCC0_OVF_vect_num 14 -#define TCC0_OVF_vect _VECTOR(14) /* Overflow Interrupt */ - -/* TCC2 interrupt vectors */ -#define TCC2_LUNF_vect_num 14 -#define TCC2_LUNF_vect _VECTOR(14) /* Low Byte Underflow Interrupt */ - -/* TCC0 interrupt vectors */ -#define TCC0_ERR_vect_num 15 -#define TCC0_ERR_vect _VECTOR(15) /* Error Interrupt */ - -/* TCC2 interrupt vectors */ -#define TCC2_HUNF_vect_num 15 -#define TCC2_HUNF_vect _VECTOR(15) /* High Byte Underflow Interrupt */ - -/* TCC0 interrupt vectors */ -#define TCC0_CCA_vect_num 16 -#define TCC0_CCA_vect _VECTOR(16) /* Compare or Capture A Interrupt */ - -/* TCC2 interrupt vectors */ -#define TCC2_LCMPA_vect_num 16 -#define TCC2_LCMPA_vect _VECTOR(16) /* Low Byte Compare A Interrupt */ - -/* TCC0 interrupt vectors */ -#define TCC0_CCB_vect_num 17 -#define TCC0_CCB_vect _VECTOR(17) /* Compare or Capture B Interrupt */ - -/* TCC2 interrupt vectors */ -#define TCC2_LCMPB_vect_num 17 -#define TCC2_LCMPB_vect _VECTOR(17) /* Low Byte Compare B Interrupt */ - -/* TCC0 interrupt vectors */ -#define TCC0_CCC_vect_num 18 -#define TCC0_CCC_vect _VECTOR(18) /* Compare or Capture C Interrupt */ - -/* TCC2 interrupt vectors */ -#define TCC2_LCMPC_vect_num 18 -#define TCC2_LCMPC_vect _VECTOR(18) /* Low Byte Compare C Interrupt */ - -/* TCC0 interrupt vectors */ -#define TCC0_CCD_vect_num 19 -#define TCC0_CCD_vect _VECTOR(19) /* Compare or Capture D Interrupt */ - -/* TCC2 interrupt vectors */ -#define TCC2_LCMPD_vect_num 19 -#define TCC2_LCMPD_vect _VECTOR(19) /* Low Byte Compare D Interrupt */ - -/* TCC1 interrupt vectors */ -#define TCC1_OVF_vect_num 20 -#define TCC1_OVF_vect _VECTOR(20) /* Overflow Interrupt */ -#define TCC1_ERR_vect_num 21 -#define TCC1_ERR_vect _VECTOR(21) /* Error Interrupt */ -#define TCC1_CCA_vect_num 22 -#define TCC1_CCA_vect _VECTOR(22) /* Compare or Capture A Interrupt */ -#define TCC1_CCB_vect_num 23 -#define TCC1_CCB_vect _VECTOR(23) /* Compare or Capture B Interrupt */ - -/* SPIC interrupt vectors */ -#define SPIC_INT_vect_num 24 -#define SPIC_INT_vect _VECTOR(24) /* SPI Interrupt */ - -/* USARTC0 interrupt vectors */ -#define USARTC0_RXC_vect_num 25 -#define USARTC0_RXC_vect _VECTOR(25) /* Reception Complete Interrupt */ -#define USARTC0_DRE_vect_num 26 -#define USARTC0_DRE_vect _VECTOR(26) /* Data Register Empty Interrupt */ -#define USARTC0_TXC_vect_num 27 -#define USARTC0_TXC_vect _VECTOR(27) /* Transmission Complete Interrupt */ - -/* USARTC1 interrupt vectors */ -#define USARTC1_RXC_vect_num 28 -#define USARTC1_RXC_vect _VECTOR(28) /* Reception Complete Interrupt */ -#define USARTC1_DRE_vect_num 29 -#define USARTC1_DRE_vect _VECTOR(29) /* Data Register Empty Interrupt */ -#define USARTC1_TXC_vect_num 30 -#define USARTC1_TXC_vect _VECTOR(30) /* Transmission Complete Interrupt */ - -/* AES interrupt vectors */ -#define AES_INT_vect_num 31 -#define AES_INT_vect _VECTOR(31) /* AES Interrupt */ - -/* NVM interrupt vectors */ -#define NVM_EE_vect_num 32 -#define NVM_EE_vect _VECTOR(32) /* EE Interrupt */ -#define NVM_SPM_vect_num 33 -#define NVM_SPM_vect _VECTOR(33) /* SPM Interrupt */ - -/* PORTB interrupt vectors */ -#define PORTB_INT0_vect_num 34 -#define PORTB_INT0_vect _VECTOR(34) /* External Interrupt 0 */ -#define PORTB_INT1_vect_num 35 -#define PORTB_INT1_vect _VECTOR(35) /* External Interrupt 1 */ - -/* PORTE interrupt vectors */ -#define PORTE_INT0_vect_num 43 -#define PORTE_INT0_vect _VECTOR(43) /* External Interrupt 0 */ -#define PORTE_INT1_vect_num 44 -#define PORTE_INT1_vect _VECTOR(44) /* External Interrupt 1 */ - -/* TWIE interrupt vectors */ -#define TWIE_TWIS_vect_num 45 -#define TWIE_TWIS_vect _VECTOR(45) /* TWI Slave Interrupt */ -#define TWIE_TWIM_vect_num 46 -#define TWIE_TWIM_vect _VECTOR(46) /* TWI Master Interrupt */ - -/* TCE0 interrupt vectors */ -#define TCE0_OVF_vect_num 47 -#define TCE0_OVF_vect _VECTOR(47) /* Overflow Interrupt */ -#define TCE0_ERR_vect_num 48 -#define TCE0_ERR_vect _VECTOR(48) /* Error Interrupt */ -#define TCE0_CCA_vect_num 49 -#define TCE0_CCA_vect _VECTOR(49) /* Compare or Capture A Interrupt */ -#define TCE0_CCB_vect_num 50 -#define TCE0_CCB_vect _VECTOR(50) /* Compare or Capture B Interrupt */ -#define TCE0_CCC_vect_num 51 -#define TCE0_CCC_vect _VECTOR(51) /* Compare or Capture C Interrupt */ -#define TCE0_CCD_vect_num 52 -#define TCE0_CCD_vect _VECTOR(52) /* Compare or Capture D Interrupt */ - -/* USARTE0 interrupt vectors */ -#define USARTE0_RXC_vect_num 58 -#define USARTE0_RXC_vect _VECTOR(58) /* Reception Complete Interrupt */ -#define USARTE0_DRE_vect_num 59 -#define USARTE0_DRE_vect _VECTOR(59) /* Data Register Empty Interrupt */ -#define USARTE0_TXC_vect_num 60 -#define USARTE0_TXC_vect _VECTOR(60) /* Transmission Complete Interrupt */ - -/* PORTD interrupt vectors */ -#define PORTD_INT0_vect_num 64 -#define PORTD_INT0_vect _VECTOR(64) /* External Interrupt 0 */ -#define PORTD_INT1_vect_num 65 -#define PORTD_INT1_vect _VECTOR(65) /* External Interrupt 1 */ - -/* PORTA interrupt vectors */ -#define PORTA_INT0_vect_num 66 -#define PORTA_INT0_vect _VECTOR(66) /* External Interrupt 0 */ -#define PORTA_INT1_vect_num 67 -#define PORTA_INT1_vect _VECTOR(67) /* External Interrupt 1 */ - -/* ACA interrupt vectors */ -#define ACA_AC0_vect_num 68 -#define ACA_AC0_vect _VECTOR(68) /* AC0 Interrupt */ -#define ACA_AC1_vect_num 69 -#define ACA_AC1_vect _VECTOR(69) /* AC1 Interrupt */ -#define ACA_ACW_vect_num 70 -#define ACA_ACW_vect _VECTOR(70) /* ACW Window Mode Interrupt */ - -/* ADCA interrupt vectors */ -#define ADCA_CH0_vect_num 71 -#define ADCA_CH0_vect _VECTOR(71) /* Interrupt 0 */ -#define ADCA_CH1_vect_num 72 -#define ADCA_CH1_vect _VECTOR(72) /* Interrupt 1 */ -#define ADCA_CH2_vect_num 73 -#define ADCA_CH2_vect _VECTOR(73) /* Interrupt 2 */ -#define ADCA_CH3_vect_num 74 -#define ADCA_CH3_vect _VECTOR(74) /* Interrupt 3 */ - -/* TCD0 interrupt vectors */ -#define TCD0_OVF_vect_num 77 -#define TCD0_OVF_vect _VECTOR(77) /* Overflow Interrupt */ - -/* TCD2 interrupt vectors */ -#define TCD2_LUNF_vect_num 77 -#define TCD2_LUNF_vect _VECTOR(77) /* Low Byte Underflow Interrupt */ - -/* TCD0 interrupt vectors */ -#define TCD0_ERR_vect_num 78 -#define TCD0_ERR_vect _VECTOR(78) /* Error Interrupt */ - -/* TCD2 interrupt vectors */ -#define TCD2_HUNF_vect_num 78 -#define TCD2_HUNF_vect _VECTOR(78) /* High Byte Underflow Interrupt */ - -/* TCD0 interrupt vectors */ -#define TCD0_CCA_vect_num 79 -#define TCD0_CCA_vect _VECTOR(79) /* Compare or Capture A Interrupt */ - -/* TCD2 interrupt vectors */ -#define TCD2_LCMPA_vect_num 79 -#define TCD2_LCMPA_vect _VECTOR(79) /* Low Byte Compare A Interrupt */ - -/* TCD0 interrupt vectors */ -#define TCD0_CCB_vect_num 80 -#define TCD0_CCB_vect _VECTOR(80) /* Compare or Capture B Interrupt */ - -/* TCD2 interrupt vectors */ -#define TCD2_LCMPB_vect_num 80 -#define TCD2_LCMPB_vect _VECTOR(80) /* Low Byte Compare B Interrupt */ - -/* TCD0 interrupt vectors */ -#define TCD0_CCC_vect_num 81 -#define TCD0_CCC_vect _VECTOR(81) /* Compare or Capture C Interrupt */ - -/* TCD2 interrupt vectors */ -#define TCD2_LCMPC_vect_num 81 -#define TCD2_LCMPC_vect _VECTOR(81) /* Low Byte Compare C Interrupt */ - -/* TCD0 interrupt vectors */ -#define TCD0_CCD_vect_num 82 -#define TCD0_CCD_vect _VECTOR(82) /* Compare or Capture D Interrupt */ - -/* TCD2 interrupt vectors */ -#define TCD2_LCMPD_vect_num 82 -#define TCD2_LCMPD_vect _VECTOR(82) /* Low Byte Compare D Interrupt */ - -/* TCD1 interrupt vectors */ -#define TCD1_OVF_vect_num 83 -#define TCD1_OVF_vect _VECTOR(83) /* Overflow Interrupt */ -#define TCD1_ERR_vect_num 84 -#define TCD1_ERR_vect _VECTOR(84) /* Error Interrupt */ -#define TCD1_CCA_vect_num 85 -#define TCD1_CCA_vect _VECTOR(85) /* Compare or Capture A Interrupt */ -#define TCD1_CCB_vect_num 86 -#define TCD1_CCB_vect _VECTOR(86) /* Compare or Capture B Interrupt */ - -/* SPID interrupt vectors */ -#define SPID_INT_vect_num 87 -#define SPID_INT_vect _VECTOR(87) /* SPI Interrupt */ - -/* USARTD0 interrupt vectors */ -#define USARTD0_RXC_vect_num 88 -#define USARTD0_RXC_vect _VECTOR(88) /* Reception Complete Interrupt */ -#define USARTD0_DRE_vect_num 89 -#define USARTD0_DRE_vect _VECTOR(89) /* Data Register Empty Interrupt */ -#define USARTD0_TXC_vect_num 90 -#define USARTD0_TXC_vect _VECTOR(90) /* Transmission Complete Interrupt */ - -/* USARTD1 interrupt vectors */ -#define USARTD1_RXC_vect_num 91 -#define USARTD1_RXC_vect _VECTOR(91) /* Reception Complete Interrupt */ -#define USARTD1_DRE_vect_num 92 -#define USARTD1_DRE_vect _VECTOR(92) /* Data Register Empty Interrupt */ -#define USARTD1_TXC_vect_num 93 -#define USARTD1_TXC_vect _VECTOR(93) /* Transmission Complete Interrupt */ - -/* USB interrupt vectors */ -#define USB_BUSEVENT_vect_num 125 -#define USB_BUSEVENT_vect _VECTOR(125) /* SOF, suspend, resume, reset bus event interrupts, crc, underflow, overflow and stall error interrupts */ -#define USB_TRNCOMPL_vect_num 126 -#define USB_TRNCOMPL_vect _VECTOR(126) /* Transaction complete interrupt */ - -#define _VECTOR_SIZE 4 /* Size of individual vector. */ -#define _VECTORS_SIZE (127 * _VECTOR_SIZE) - - -/* ========== Constants ========== */ - -#define PROGMEM_START (0x0000) -#define PROGMEM_SIZE (69632) -#define PROGMEM_END (PROGMEM_START + PROGMEM_SIZE - 1) - -#define APP_SECTION_START (0x0000) -#define APP_SECTION_SIZE (65536) -#define APP_SECTION_PAGE_SIZE (256) -#define APP_SECTION_END (APP_SECTION_START + APP_SECTION_SIZE - 1) - -#define APPTABLE_SECTION_START (0xF000) -#define APPTABLE_SECTION_SIZE (4096) -#define APPTABLE_SECTION_PAGE_SIZE (256) -#define APPTABLE_SECTION_END (APPTABLE_SECTION_START + APPTABLE_SECTION_SIZE - 1) - -#define BOOT_SECTION_START (0x10000) -#define BOOT_SECTION_SIZE (4096) -#define BOOT_SECTION_PAGE_SIZE (256) -#define BOOT_SECTION_END (BOOT_SECTION_START + BOOT_SECTION_SIZE - 1) - -#define DATAMEM_START (0x0000) -#define DATAMEM_SIZE (12288) -#define DATAMEM_END (DATAMEM_START + DATAMEM_SIZE - 1) - -#define IO_START (0x0000) -#define IO_SIZE (4096) -#define IO_PAGE_SIZE (0) -#define IO_END (IO_START + IO_SIZE - 1) - -#define MAPPED_EEPROM_START (0x1000) -#define MAPPED_EEPROM_SIZE (2048) -#define MAPPED_EEPROM_PAGE_SIZE (0) -#define MAPPED_EEPROM_END (MAPPED_EEPROM_START + MAPPED_EEPROM_SIZE - 1) - -#define INTERNAL_SRAM_START (0x2000) -#define INTERNAL_SRAM_SIZE (4096) -#define INTERNAL_SRAM_PAGE_SIZE (0) -#define INTERNAL_SRAM_END (INTERNAL_SRAM_START + INTERNAL_SRAM_SIZE - 1) - -#define EEPROM_START (0x0000) -#define EEPROM_SIZE (2048) -#define EEPROM_PAGE_SIZE (32) -#define EEPROM_END (EEPROM_START + EEPROM_SIZE - 1) - -#define SIGNATURES_START (0x0000) -#define SIGNATURES_SIZE (3) -#define SIGNATURES_PAGE_SIZE (0) -#define SIGNATURES_END (SIGNATURES_START + SIGNATURES_SIZE - 1) - -#define FUSES_START (0x0000) -#define FUSES_SIZE (6) -#define FUSES_PAGE_SIZE (0) -#define FUSES_END (FUSES_START + FUSES_SIZE - 1) - -#define LOCKBITS_START (0x0000) -#define LOCKBITS_SIZE (1) -#define LOCKBITS_PAGE_SIZE (0) -#define LOCKBITS_END (LOCKBITS_START + LOCKBITS_SIZE - 1) - -#define USER_SIGNATURES_START (0x0000) -#define USER_SIGNATURES_SIZE (256) -#define USER_SIGNATURES_PAGE_SIZE (256) -#define USER_SIGNATURES_END (USER_SIGNATURES_START + USER_SIGNATURES_SIZE - 1) - -#define PROD_SIGNATURES_START (0x0000) -#define PROD_SIGNATURES_SIZE (64) -#define PROD_SIGNATURES_PAGE_SIZE (256) -#define PROD_SIGNATURES_END (PROD_SIGNATURES_START + PROD_SIGNATURES_SIZE - 1) - -#define FLASHSTART PROGMEM_START -#define FLASHEND PROGMEM_END -#define SPM_PAGESIZE 256 -#define RAMSTART INTERNAL_SRAM_START -#define RAMSIZE INTERNAL_SRAM_SIZE -#define RAMEND INTERNAL_SRAM_END -#define E2END EEPROM_END -#define E2PAGESIZE EEPROM_PAGE_SIZE - - -/* ========== Fuses ========== */ -#define FUSE_MEMORY_SIZE 6 - -/* Fuse Byte 0 Reserved */ - -/* Fuse Byte 1 */ -#define FUSE_WDP0 (unsigned char)~_BV(0) /* Watchdog Timeout Period Bit 0 */ -#define FUSE_WDP1 (unsigned char)~_BV(1) /* Watchdog Timeout Period Bit 1 */ -#define FUSE_WDP2 (unsigned char)~_BV(2) /* Watchdog Timeout Period Bit 2 */ -#define FUSE_WDP3 (unsigned char)~_BV(3) /* Watchdog Timeout Period Bit 3 */ -#define FUSE_WDWP0 (unsigned char)~_BV(4) /* Watchdog Window Timeout Period Bit 0 */ -#define FUSE_WDWP1 (unsigned char)~_BV(5) /* Watchdog Window Timeout Period Bit 1 */ -#define FUSE_WDWP2 (unsigned char)~_BV(6) /* Watchdog Window Timeout Period Bit 2 */ -#define FUSE_WDWP3 (unsigned char)~_BV(7) /* Watchdog Window Timeout Period Bit 3 */ -#define FUSE1_DEFAULT (0xFF) - -/* Fuse Byte 2 */ -#define FUSE_BODPD0 (unsigned char)~_BV(0) /* BOD Operation in Power-Down Mode Bit 0 */ -#define FUSE_BODPD1 (unsigned char)~_BV(1) /* BOD Operation in Power-Down Mode Bit 1 */ -#define FUSE_TOSCSEL (unsigned char)~_BV(5) /* Timer Oscillator pin location */ -#define FUSE_BOOTRST (unsigned char)~_BV(6) /* Boot Loader Section Reset Vector */ -#define FUSE2_DEFAULT (0xFF) - -/* Fuse Byte 3 Reserved */ - -/* Fuse Byte 4 */ -#define FUSE_WDLOCK (unsigned char)~_BV(1) /* Watchdog Timer Lock */ -#define FUSE_SUT0 (unsigned char)~_BV(2) /* Start-up Time Bit 0 */ -#define FUSE_SUT1 (unsigned char)~_BV(3) /* Start-up Time Bit 1 */ -#define FUSE_RSTDISBL (unsigned char)~_BV(4) /* External Reset Disable */ -#define FUSE4_DEFAULT (0xFF) - -/* Fuse Byte 5 */ -#define FUSE_BODLVL0 (unsigned char)~_BV(0) /* Brownout Detection Voltage Level Bit 0 */ -#define FUSE_BODLVL1 (unsigned char)~_BV(1) /* Brownout Detection Voltage Level Bit 1 */ -#define FUSE_BODLVL2 (unsigned char)~_BV(2) /* Brownout Detection Voltage Level Bit 2 */ -#define FUSE_EESAVE (unsigned char)~_BV(3) /* Preserve EEPROM Through Chip Erase */ -#define FUSE_BODACT0 (unsigned char)~_BV(4) /* BOD Operation in Active Mode Bit 0 */ -#define FUSE_BODACT1 (unsigned char)~_BV(5) /* BOD Operation in Active Mode Bit 1 */ -#define FUSE5_DEFAULT (0xFF) - -/* ========== Lock Bits ========== */ -#define __LOCK_BITS_EXIST -#define __BOOT_LOCK_APPLICATION_TABLE_BITS_EXIST -#define __BOOT_LOCK_APPLICATION_BITS_EXIST -#define __BOOT_LOCK_BOOT_BITS_EXIST - -/* ========== Signature ========== */ -#define SIGNATURE_0 0x1E -#define SIGNATURE_1 0x96 -#define SIGNATURE_2 0x46 - -/* ========== Power Reduction Condition Definitions ========== */ - -/* PR.PRGEN */ -#define __AVR_HAVE_PRGEN (PR_USB_bm|PR_AES_bm|PR_EBI_bm|PR_RTC_bm|PR_EVSYS_bm|PR_DMA_bm) -#define __AVR_HAVE_PRGEN_USB -#define __AVR_HAVE_PRGEN_AES -#define __AVR_HAVE_PRGEN_EBI -#define __AVR_HAVE_PRGEN_RTC -#define __AVR_HAVE_PRGEN_EVSYS -#define __AVR_HAVE_PRGEN_DMA - -/* PR.PRPA */ -#define __AVR_HAVE_PRPA (PR_DAC_bm|PR_ADC_bm|PR_AC_bm) -#define __AVR_HAVE_PRPA_DAC -#define __AVR_HAVE_PRPA_ADC -#define __AVR_HAVE_PRPA_AC - -/* PR.PRPB */ -#define __AVR_HAVE_PRPB (PR_DAC_bm|PR_ADC_bm|PR_AC_bm) -#define __AVR_HAVE_PRPB_DAC -#define __AVR_HAVE_PRPB_ADC -#define __AVR_HAVE_PRPB_AC - -/* PR.PRPC */ -#define __AVR_HAVE_PRPC (PR_TWI_bm|PR_USART1_bm|PR_USART0_bm|PR_SPI_bm|PR_HIRES_bm|PR_TC1_bm|PR_TC0_bm) -#define __AVR_HAVE_PRPC_TWI -#define __AVR_HAVE_PRPC_USART1 -#define __AVR_HAVE_PRPC_USART0 -#define __AVR_HAVE_PRPC_SPI -#define __AVR_HAVE_PRPC_HIRES -#define __AVR_HAVE_PRPC_TC1 -#define __AVR_HAVE_PRPC_TC0 - -/* PR.PRPD */ -#define __AVR_HAVE_PRPD (PR_TWI_bm|PR_USART1_bm|PR_USART0_bm|PR_SPI_bm|PR_HIRES_bm|PR_TC1_bm|PR_TC0_bm) -#define __AVR_HAVE_PRPD_TWI -#define __AVR_HAVE_PRPD_USART1 -#define __AVR_HAVE_PRPD_USART0 -#define __AVR_HAVE_PRPD_SPI -#define __AVR_HAVE_PRPD_HIRES -#define __AVR_HAVE_PRPD_TC1 -#define __AVR_HAVE_PRPD_TC0 - -/* PR.PRPE */ -#define __AVR_HAVE_PRPE (PR_TWI_bm|PR_USART1_bm|PR_USART0_bm|PR_SPI_bm|PR_HIRES_bm|PR_TC1_bm|PR_TC0_bm) -#define __AVR_HAVE_PRPE_TWI -#define __AVR_HAVE_PRPE_USART1 -#define __AVR_HAVE_PRPE_USART0 -#define __AVR_HAVE_PRPE_SPI -#define __AVR_HAVE_PRPE_HIRES -#define __AVR_HAVE_PRPE_TC1 -#define __AVR_HAVE_PRPE_TC0 - -/* PR.PRPF */ -#define __AVR_HAVE_PRPF (PR_TWI_bm|PR_USART1_bm|PR_USART0_bm|PR_SPI_bm|PR_HIRES_bm|PR_TC1_bm|PR_TC0_bm) -#define __AVR_HAVE_PRPF_TWI -#define __AVR_HAVE_PRPF_USART1 -#define __AVR_HAVE_PRPF_USART0 -#define __AVR_HAVE_PRPF_SPI -#define __AVR_HAVE_PRPF_HIRES -#define __AVR_HAVE_PRPF_TC1 -#define __AVR_HAVE_PRPF_TC0 - - -#endif /* #ifdef _AVR_ATXMEGA64A4U_H_INCLUDED */ - diff --git a/arduino/hardware/tools/avr/avr/include/avr/iox64b1.h b/arduino/hardware/tools/avr/avr/include/avr/iox64b1.h deleted file mode 100644 index 6f44899..0000000 --- a/arduino/hardware/tools/avr/avr/include/avr/iox64b1.h +++ /dev/null @@ -1,6454 +0,0 @@ -/***************************************************************************** - * - * Copyright (C) 2015 Atmel Corporation - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * - * * Neither the name of the copyright holders nor the names of - * contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - ****************************************************************************/ - - -#ifndef _AVR_IO_H_ -# error "Include instead of this file." -#endif - -#ifndef _AVR_IOXXX_H_ -# define _AVR_IOXXX_H_ "iox64b1.h" -#else -# error "Attempt to include more than one file." -#endif - -#ifndef _AVR_ATXMEGA64B1_H_INCLUDED -#define _AVR_ATXMEGA64B1_H_INCLUDED - -/* Ungrouped common registers */ -#define GPIOR0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ -#define GPIOR1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ -#define GPIOR2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ -#define GPIOR3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ - -/* Deprecated */ -#define GPIO0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ -#define GPIO1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ -#define GPIO2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ -#define GPIO3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ - -#define CCP _SFR_MEM8(0x0034) /* Configuration Change Protection */ -#define RAMPD _SFR_MEM8(0x0038) /* Ramp D */ -#define RAMPX _SFR_MEM8(0x0039) /* Ramp X */ -#define RAMPY _SFR_MEM8(0x003A) /* Ramp Y */ -#define RAMPZ _SFR_MEM8(0x003B) /* Ramp Z */ -#define EIND _SFR_MEM8(0x003C) /* Extended Indirect Jump */ -#define SPL _SFR_MEM8(0x003D) /* Stack Pointer Low */ -#define SPH _SFR_MEM8(0x003E) /* Stack Pointer High */ -#define SREG _SFR_MEM8(0x003F) /* Status Register */ - -/* C Language Only */ -#if !defined (__ASSEMBLER__) - -#include - -typedef volatile uint8_t register8_t; -typedef volatile uint16_t register16_t; -typedef volatile uint32_t register32_t; - - -#ifdef _WORDREGISTER -#undef _WORDREGISTER -#endif -#define _WORDREGISTER(regname) \ - __extension__ union \ - { \ - register16_t regname; \ - struct \ - { \ - register8_t regname ## L; \ - register8_t regname ## H; \ - }; \ - } - -#ifdef _DWORDREGISTER -#undef _DWORDREGISTER -#endif -#define _DWORDREGISTER(regname) \ - __extension__ union \ - { \ - register32_t regname; \ - struct \ - { \ - register8_t regname ## 0; \ - register8_t regname ## 1; \ - register8_t regname ## 2; \ - register8_t regname ## 3; \ - }; \ - } - - -/* -========================================================================== -IO Module Structures -========================================================================== -*/ - - -/* --------------------------------------------------------------------------- -VPORT - Virtual Ports --------------------------------------------------------------------------- -*/ - -/* Virtual Port */ -typedef struct VPORT_struct -{ - register8_t DIR; /* I/O Port Data Direction */ - register8_t OUT; /* I/O Port Output */ - register8_t IN; /* I/O Port Input */ - register8_t INTFLAGS; /* Interrupt Flag Register */ -} VPORT_t; - - -/* --------------------------------------------------------------------------- -XOCD - On-Chip Debug System --------------------------------------------------------------------------- -*/ - -/* On-Chip Debug System */ -typedef struct OCD_struct -{ - register8_t OCDR0; /* OCD Register 0 */ - register8_t OCDR1; /* OCD Register 1 */ -} OCD_t; - - -/* --------------------------------------------------------------------------- -CPU - CPU --------------------------------------------------------------------------- -*/ - -/* CCP signatures */ -typedef enum CCP_enum -{ - CCP_SPM_gc = (0x9D<<0), /* SPM Instruction Protection */ - CCP_IOREG_gc = (0xD8<<0), /* IO Register Protection */ -} CCP_t; - - -/* --------------------------------------------------------------------------- -CLK - Clock System --------------------------------------------------------------------------- -*/ - -/* Clock System */ -typedef struct CLK_struct -{ - register8_t CTRL; /* Control Register */ - register8_t PSCTRL; /* Prescaler Control Register */ - register8_t LOCK; /* Lock register */ - register8_t RTCCTRL; /* RTC Control Register */ - register8_t USBCTRL; /* USB Control Register */ -} CLK_t; - -/* System Clock Selection */ -typedef enum CLK_SCLKSEL_enum -{ - CLK_SCLKSEL_RC2M_gc = (0x00<<0), /* Internal 2 MHz RC Oscillator */ - CLK_SCLKSEL_RC32M_gc = (0x01<<0), /* Internal 32 MHz RC Oscillator */ - CLK_SCLKSEL_RC32K_gc = (0x02<<0), /* Internal 32.768 kHz RC Oscillator */ - CLK_SCLKSEL_XOSC_gc = (0x03<<0), /* External Crystal Oscillator or Clock */ - CLK_SCLKSEL_PLL_gc = (0x04<<0), /* Phase Locked Loop */ -} CLK_SCLKSEL_t; - -/* Prescaler A Division Factor */ -typedef enum CLK_PSADIV_enum -{ - CLK_PSADIV_1_gc = (0x00<<2), /* Divide by 1 */ - CLK_PSADIV_2_gc = (0x01<<2), /* Divide by 2 */ - CLK_PSADIV_4_gc = (0x03<<2), /* Divide by 4 */ - CLK_PSADIV_8_gc = (0x05<<2), /* Divide by 8 */ - CLK_PSADIV_16_gc = (0x07<<2), /* Divide by 16 */ - CLK_PSADIV_32_gc = (0x09<<2), /* Divide by 32 */ - CLK_PSADIV_64_gc = (0x0B<<2), /* Divide by 64 */ - CLK_PSADIV_128_gc = (0x0D<<2), /* Divide by 128 */ - CLK_PSADIV_256_gc = (0x0F<<2), /* Divide by 256 */ - CLK_PSADIV_512_gc = (0x11<<2), /* Divide by 512 */ -} CLK_PSADIV_t; - -/* Prescaler B and C Division Factor */ -typedef enum CLK_PSBCDIV_enum -{ - CLK_PSBCDIV_1_1_gc = (0x00<<0), /* Divide B by 1 and C by 1 */ - CLK_PSBCDIV_1_2_gc = (0x01<<0), /* Divide B by 1 and C by 2 */ - CLK_PSBCDIV_4_1_gc = (0x02<<0), /* Divide B by 4 and C by 1 */ - CLK_PSBCDIV_2_2_gc = (0x03<<0), /* Divide B by 2 and C by 2 */ -} CLK_PSBCDIV_t; - -/* RTC Clock Source */ -typedef enum CLK_RTCSRC_enum -{ - CLK_RTCSRC_ULP_gc = (0x00<<1), /* 1.024 kHz from internal 32kHz ULP */ - CLK_RTCSRC_TOSC_gc = (0x01<<1), /* 1.024 kHz from 32.768 kHz crystal oscillator on TOSC */ - CLK_RTCSRC_RCOSC_gc = (0x02<<1), /* 1.024 kHz from internal 32.768 kHz RC oscillator */ - CLK_RTCSRC_TOSC32_gc = (0x05<<1), /* 32.768 kHz from 32.768 kHz crystal oscillator on TOSC */ - CLK_RTCSRC_RCOSC32_gc = (0x06<<1), /* 32.768 kHz from internal 32.768 kHz RC oscillator */ - CLK_RTCSRC_EXTCLK_gc = (0x07<<1), /* External Clock from TOSC1 */ -} CLK_RTCSRC_t; - -/* USB Prescaler Division Factor */ -typedef enum CLK_USBPSDIV_enum -{ - CLK_USBPSDIV_1_gc = (0x00<<3), /* Divide by 1 */ - CLK_USBPSDIV_2_gc = (0x01<<3), /* Divide by 2 */ - CLK_USBPSDIV_4_gc = (0x02<<3), /* Divide by 4 */ - CLK_USBPSDIV_8_gc = (0x03<<3), /* Divide by 8 */ - CLK_USBPSDIV_16_gc = (0x04<<3), /* Divide by 16 */ - CLK_USBPSDIV_32_gc = (0x05<<3), /* Divide by 32 */ -} CLK_USBPSDIV_t; - -/* USB Clock Source */ -typedef enum CLK_USBSRC_enum -{ - CLK_USBSRC_PLL_gc = (0x00<<1), /* PLL */ - CLK_USBSRC_RC32M_gc = (0x01<<1), /* Internal 32 MHz RC Oscillator */ -} CLK_USBSRC_t; - - -/* --------------------------------------------------------------------------- -SLEEP - Sleep Controller --------------------------------------------------------------------------- -*/ - -/* Sleep Controller */ -typedef struct SLEEP_struct -{ - register8_t CTRL; /* Control Register */ -} SLEEP_t; - -/* Sleep Mode */ -typedef enum SLEEP_SMODE_enum -{ - SLEEP_SMODE_IDLE_gc = (0x00<<1), /* Idle mode */ - SLEEP_SMODE_PDOWN_gc = (0x02<<1), /* Power-down Mode */ - SLEEP_SMODE_PSAVE_gc = (0x03<<1), /* Power-save Mode */ - SLEEP_SMODE_STDBY_gc = (0x06<<1), /* Standby Mode */ - SLEEP_SMODE_ESTDBY_gc = (0x07<<1), /* Extended Standby Mode */ -} SLEEP_SMODE_t; - - - -#define SLEEP_MODE_IDLE (0x00<<1) -#define SLEEP_MODE_PWR_DOWN (0x02<<1) -#define SLEEP_MODE_PWR_SAVE (0x03<<1) -#define SLEEP_MODE_STANDBY (0x06<<1) -#define SLEEP_MODE_EXT_STANDBY (0x07<<1) -/* --------------------------------------------------------------------------- -OSC - Oscillator --------------------------------------------------------------------------- -*/ - -/* Oscillator */ -typedef struct OSC_struct -{ - register8_t CTRL; /* Control Register */ - register8_t STATUS; /* Status Register */ - register8_t XOSCCTRL; /* External Oscillator Control Register */ - register8_t XOSCFAIL; /* Oscillator Failure Detection Register */ - register8_t RC32KCAL; /* 32.768 kHz Internal Oscillator Calibration Register */ - register8_t PLLCTRL; /* PLL Control Register */ - register8_t DFLLCTRL; /* DFLL Control Register */ -} OSC_t; - -/* Oscillator Frequency Range */ -typedef enum OSC_FRQRANGE_enum -{ - OSC_FRQRANGE_04TO2_gc = (0x00<<6), /* 0.4 - 2 MHz */ - OSC_FRQRANGE_2TO9_gc = (0x01<<6), /* 2 - 9 MHz */ - OSC_FRQRANGE_9TO12_gc = (0x02<<6), /* 9 - 12 MHz */ - OSC_FRQRANGE_12TO16_gc = (0x03<<6), /* 12 - 16 MHz */ -} OSC_FRQRANGE_t; - -/* External Oscillator Selection and Startup Time */ -typedef enum OSC_XOSCSEL_enum -{ - OSC_XOSCSEL_EXTCLK_gc = (0x00<<0), /* External Clock on port R1 - 6 CLK */ - OSC_XOSCSEL_EXTCLK_C0_gc = (0x01<<0), /* External Clock on port C0 - 6 CLK */ - OSC_XOSCSEL_EXTCLK_C1_gc = (0x05<<0), /* External Clock on port C1 - 6 CLK */ - OSC_XOSCSEL_EXTCLK_C2_gc = (0x09<<0), /* External Clock on port C2 - 6 CLK */ - OSC_XOSCSEL_EXTCLK_C3_gc = (0x0D<<0), /* External Clock on port C3 - 6 CLK */ - OSC_XOSCSEL_EXTCLK_C4_gc = (0x11<<0), /* External Clock on port C4 - 6 CLK */ - OSC_XOSCSEL_EXTCLK_C5_gc = (0x15<<0), /* External Clock on port C5 - 6 CLK */ - OSC_XOSCSEL_EXTCLK_C6_gc = (0x19<<0), /* External Clock on port C6 - 6 CLK */ - OSC_XOSCSEL_EXTCLK_C7_gc = (0x1D<<0), /* External Clock on port C7 - 6 CLK */ - OSC_XOSCSEL_32KHz_gc = (0x02<<0), /* 32kHz TOSC - 32K CLK */ - OSC_XOSCSEL_XTAL_256CLK_gc = (0x03<<0), /* 0.4-16MHz XTAL - 256 CLK */ - OSC_XOSCSEL_XTAL_1KCLK_gc = (0x07<<0), /* 0.4-16MHz XTAL - 1K CLK */ - OSC_XOSCSEL_XTAL_16KCLK_gc = (0x0B<<0), /* 0.4-16MHz XTAL - 16K CLK */ -} OSC_XOSCSEL_t; - -/* PLL Clock Source */ -typedef enum OSC_PLLSRC_enum -{ - OSC_PLLSRC_RC2M_gc = (0x00<<6), /* Internal 2 MHz RC Oscillator */ - OSC_PLLSRC_RC32M_gc = (0x02<<6), /* Internal 32 MHz RC Oscillator */ - OSC_PLLSRC_XOSC_gc = (0x03<<6), /* External Oscillator */ -} OSC_PLLSRC_t; - -/* 2 MHz DFLL Calibration Reference */ -typedef enum OSC_RC2MCREF_enum -{ - OSC_RC2MCREF_RC32K_gc = (0x00<<0), /* Internal 32.768 kHz RC Oscillator */ - OSC_RC2MCREF_XOSC32K_gc = (0x01<<0), /* External 32.768 kHz Crystal Oscillator */ -} OSC_RC2MCREF_t; - -/* 32 MHz DFLL Calibration Reference */ -typedef enum OSC_RC32MCREF_enum -{ - OSC_RC32MCREF_RC32K_gc = (0x00<<1), /* Internal 32.768 kHz RC Oscillator */ - OSC_RC32MCREF_XOSC32K_gc = (0x01<<1), /* External 32.768 kHz Crystal Oscillator */ - OSC_RC32MCREF_USBSOF_gc = (0x02<<1), /* USB Start of Frame */ -} OSC_RC32MCREF_t; - - -/* --------------------------------------------------------------------------- -DFLL - DFLL --------------------------------------------------------------------------- -*/ - -/* DFLL */ -typedef struct DFLL_struct -{ - register8_t CTRL; /* Control Register */ - register8_t reserved_0x01; - register8_t CALA; /* Calibration Register A */ - register8_t CALB; /* Calibration Register B */ - register8_t COMP0; /* Oscillator Compare Register 0 */ - register8_t COMP1; /* Oscillator Compare Register 1 */ - register8_t COMP2; /* Oscillator Compare Register 2 */ - register8_t reserved_0x07; -} DFLL_t; - - -/* --------------------------------------------------------------------------- -PR - Power Reduction --------------------------------------------------------------------------- -*/ - -/* Power Reduction */ -typedef struct PR_struct -{ - register8_t PRGEN; /* General Power Reduction */ - register8_t PRPA; /* Power Reduction Port A */ - register8_t PRPB; /* Power Reduction Port B */ - register8_t PRPC; /* Power Reduction Port C */ - register8_t reserved_0x04; - register8_t PRPE; /* Power Reduction Port E */ -} PR_t; - - -/* --------------------------------------------------------------------------- -RST - Reset --------------------------------------------------------------------------- -*/ - -/* Reset */ -typedef struct RST_struct -{ - register8_t STATUS; /* Status Register */ - register8_t CTRL; /* Control Register */ -} RST_t; - - -/* --------------------------------------------------------------------------- -WDT - Watch-Dog Timer --------------------------------------------------------------------------- -*/ - -/* Watch-Dog Timer */ -typedef struct WDT_struct -{ - register8_t CTRL; /* Control */ - register8_t WINCTRL; /* Windowed Mode Control */ - register8_t STATUS; /* Status */ -} WDT_t; - -/* Period setting */ -typedef enum WDT_PER_enum -{ - WDT_PER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ - WDT_PER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ - WDT_PER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ - WDT_PER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ - WDT_PER_128CLK_gc = (0x04<<2), /* 128 cycles (0.128s @ 3.3V) */ - WDT_PER_256CLK_gc = (0x05<<2), /* 256 cycles (0.256s @ 3.3V) */ - WDT_PER_512CLK_gc = (0x06<<2), /* 512 cycles (0.512s @ 3.3V) */ - WDT_PER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ - WDT_PER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ - WDT_PER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ - WDT_PER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ -} WDT_PER_t; - -/* Closed window period */ -typedef enum WDT_WPER_enum -{ - WDT_WPER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ - WDT_WPER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ - WDT_WPER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ - WDT_WPER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ - WDT_WPER_128CLK_gc = (0x04<<2), /* 128 cycles (0.128s @ 3.3V) */ - WDT_WPER_256CLK_gc = (0x05<<2), /* 256 cycles (0.256s @ 3.3V) */ - WDT_WPER_512CLK_gc = (0x06<<2), /* 512 cycles (0.512s @ 3.3V) */ - WDT_WPER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ - WDT_WPER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ - WDT_WPER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ - WDT_WPER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ -} WDT_WPER_t; - - -/* --------------------------------------------------------------------------- -MCU - MCU Control --------------------------------------------------------------------------- -*/ - -/* MCU Control */ -typedef struct MCU_struct -{ - register8_t DEVID0; /* Device ID byte 0 */ - register8_t DEVID1; /* Device ID byte 1 */ - register8_t DEVID2; /* Device ID byte 2 */ - register8_t REVID; /* Revision ID */ - register8_t JTAGUID; /* JTAG User ID */ - register8_t reserved_0x05; - register8_t MCUCR; /* MCU Control */ - register8_t ANAINIT; /* Analog Startup Delay */ - register8_t EVSYSLOCK; /* Event System Lock */ - register8_t AWEXLOCK; /* AWEX Lock */ - register8_t reserved_0x0A; - register8_t reserved_0x0B; -} MCU_t; - - -/* --------------------------------------------------------------------------- -PMIC - Programmable Multi-level Interrupt Controller --------------------------------------------------------------------------- -*/ - -/* Programmable Multi-level Interrupt Controller */ -typedef struct PMIC_struct -{ - register8_t STATUS; /* Status Register */ - register8_t INTPRI; /* Interrupt Priority */ - register8_t CTRL; /* Control Register */ - register8_t reserved_0x03; - register8_t reserved_0x04; - register8_t reserved_0x05; - register8_t reserved_0x06; - register8_t reserved_0x07; - register8_t reserved_0x08; - register8_t reserved_0x09; - register8_t reserved_0x0A; - register8_t reserved_0x0B; - register8_t reserved_0x0C; - register8_t reserved_0x0D; - register8_t reserved_0x0E; - register8_t reserved_0x0F; -} PMIC_t; - - -/* --------------------------------------------------------------------------- -PORTCFG - Port Configuration --------------------------------------------------------------------------- -*/ - -/* I/O port Configuration */ -typedef struct PORTCFG_struct -{ - register8_t MPCMASK; /* Multi-pin Configuration Mask */ - register8_t reserved_0x01; - register8_t VPCTRLA; /* Virtual Port Control Register A */ - register8_t VPCTRLB; /* Virtual Port Control Register B */ - register8_t CLKEVOUT; /* Clock and Event Out Register */ - register8_t reserved_0x05; - register8_t EVOUTSEL; /* Event Output Select */ -} PORTCFG_t; - -/* Virtual Port Mapping */ -typedef enum PORTCFG_VP02MAP_enum -{ - PORTCFG_VP02MAP_PORTA_gc = (0x00<<0), /* Mapped To PORTA */ - PORTCFG_VP02MAP_PORTB_gc = (0x01<<0), /* Mapped To PORTB */ - PORTCFG_VP02MAP_PORTC_gc = (0x02<<0), /* Mapped To PORTC */ - PORTCFG_VP02MAP_PORTD_gc = (0x03<<0), /* Mapped To PORTD */ - PORTCFG_VP02MAP_PORTE_gc = (0x04<<0), /* Mapped To PORTE */ - PORTCFG_VP02MAP_PORTG_gc = (0x06<<0), /* Mapped To PORTG */ - PORTCFG_VP02MAP_PORTM_gc = (0x0B<<0), /* Mapped To PORTM */ - PORTCFG_VP02MAP_PORTR_gc = (0x0F<<0), /* Mapped To PORTR */ -} PORTCFG_VP02MAP_t; - -/* Virtual Port Mapping */ -typedef enum PORTCFG_VP13MAP_enum -{ - PORTCFG_VP13MAP_PORTA_gc = (0x00<<4), /* Mapped To PORTA */ - PORTCFG_VP13MAP_PORTB_gc = (0x01<<4), /* Mapped To PORTB */ - PORTCFG_VP13MAP_PORTC_gc = (0x02<<4), /* Mapped To PORTC */ - PORTCFG_VP13MAP_PORTD_gc = (0x03<<4), /* Mapped To PORTD */ - PORTCFG_VP13MAP_PORTE_gc = (0x04<<4), /* Mapped To PORTE */ - PORTCFG_VP13MAP_PORTG_gc = (0x06<<4), /* Mapped To PORTG */ - PORTCFG_VP13MAP_PORTM_gc = (0x0B<<4), /* Mapped To PORTM */ - PORTCFG_VP13MAP_PORTR_gc = (0x0F<<4), /* Mapped To PORTR */ -} PORTCFG_VP13MAP_t; - -/* System Clock Output Port */ -typedef enum PORTCFG_CLKOUT_enum -{ - PORTCFG_CLKOUT_OFF_gc = (0x00<<0), /* System Clock Output Disabled */ - PORTCFG_CLKOUT_PC_gc = (0x01<<0), /* System Clock Output on Port C */ - PORTCFG_CLKOUT_PE_gc = (0x03<<0), /* System Clock Output on Port E */ -} PORTCFG_CLKOUT_t; - -/* Peripheral Clock Output Select */ -typedef enum PORTCFG_CLKOUTSEL_enum -{ - PORTCFG_CLKOUTSEL_CLK1X_gc = (0x00<<2), /* 1x Peripheral Clock Output to pin */ - PORTCFG_CLKOUTSEL_CLK2X_gc = (0x01<<2), /* 2x Peripheral Clock Output to pin */ - PORTCFG_CLKOUTSEL_CLK4X_gc = (0x02<<2), /* 4x Peripheral Clock Output to pin */ -} PORTCFG_CLKOUTSEL_t; - -/* Event Output Port */ -typedef enum PORTCFG_EVOUT_enum -{ - PORTCFG_EVOUT_OFF_gc = (0x00<<4), /* Event Output Disabled */ - PORTCFG_EVOUT_PC_gc = (0x01<<4), /* Event Channel 0 Output on Port C */ - PORTCFG_EVOUT_PE_gc = (0x03<<4), /* Event Channel 0 Output on Port E */ -} PORTCFG_EVOUT_t; - -/* Clock and Event Output Port */ -typedef enum PORTCFG_CLKEVPIN_enum -{ - PORTCFG_CLKEVPIN_PIN7_gc = (0x00<<7), /* Clock and Event Ouput on PIN 7 */ - PORTCFG_CLKEVPIN_PIN4_gc = (0x01<<7), /* Clock and Event Ouput on PIN 4 */ -} PORTCFG_CLKEVPIN_t; - -/* Event Output Select */ -typedef enum PORTCFG_EVOUTSEL_enum -{ - PORTCFG_EVOUTSEL_0_gc = (0x00<<2), /* Event Channel 0 output to pin */ - PORTCFG_EVOUTSEL_1_gc = (0x01<<2), /* Event Channel 1 output to pin */ - PORTCFG_EVOUTSEL_2_gc = (0x02<<2), /* Event Channel 2 output to pin */ - PORTCFG_EVOUTSEL_3_gc = (0x03<<2), /* Event Channel 3 output to pin */ -} PORTCFG_EVOUTSEL_t; - - -/* --------------------------------------------------------------------------- -AES - AES Module --------------------------------------------------------------------------- -*/ - -/* AES Module */ -typedef struct AES_struct -{ - register8_t CTRL; /* AES Control Register */ - register8_t STATUS; /* AES Status Register */ - register8_t STATE; /* AES State Register */ - register8_t KEY; /* AES Key Register */ - register8_t INTCTRL; /* AES Interrupt Control Register */ -} AES_t; - -/* Interrupt level */ -typedef enum AES_INTLVL_enum -{ - AES_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - AES_INTLVL_LO_gc = (0x01<<0), /* Low Level */ - AES_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ - AES_INTLVL_HI_gc = (0x03<<0), /* High Level */ -} AES_INTLVL_t; - - -/* --------------------------------------------------------------------------- -CRC - Cyclic Redundancy Checker --------------------------------------------------------------------------- -*/ - -/* Cyclic Redundancy Checker */ -typedef struct CRC_struct -{ - register8_t CTRL; /* Control Register */ - register8_t STATUS; /* Status Register */ - register8_t reserved_0x02; - register8_t DATAIN; /* Data Input */ - register8_t CHECKSUM0; /* Checksum byte 0 */ - register8_t CHECKSUM1; /* Checksum byte 1 */ - register8_t CHECKSUM2; /* Checksum byte 2 */ - register8_t CHECKSUM3; /* Checksum byte 3 */ -} CRC_t; - -/* Reset */ -typedef enum CRC_RESET_enum -{ - CRC_RESET_NO_gc = (0x00<<6), /* No Reset */ - CRC_RESET_RESET0_gc = (0x02<<6), /* Reset CRC with CHECKSUM to all zeros */ - CRC_RESET_RESET1_gc = (0x03<<6), /* Reset CRC with CHECKSUM to all ones */ -} CRC_RESET_t; - -/* Input Source */ -typedef enum CRC_SOURCE_enum -{ - CRC_SOURCE_DISABLE_gc = (0x00<<0), /* Disabled */ - CRC_SOURCE_IO_gc = (0x01<<0), /* I/O Interface */ - CRC_SOURCE_FLASH_gc = (0x02<<0), /* Flash */ - CRC_SOURCE_DMAC0_gc = (0x04<<0), /* DMAC Channel 0 */ - CRC_SOURCE_DMAC1_gc = (0x05<<0), /* DMAC Channel 1 */ -} CRC_SOURCE_t; - - -/* --------------------------------------------------------------------------- -DMA - DMA Controller --------------------------------------------------------------------------- -*/ - -/* DMA Channel */ -typedef struct DMA_CH_struct -{ - register8_t CTRLA; /* Channel Control */ - register8_t CTRLB; /* Channel Control */ - register8_t ADDRCTRL; /* Address Control */ - register8_t TRIGSRC; /* Channel Trigger Source */ - _WORDREGISTER(TRFCNT); /* Channel Block Transfer Count */ - register8_t REPCNT; /* Channel Repeat Count */ - register8_t reserved_0x07; - register8_t SRCADDR0; /* Channel Source Address 0 */ - register8_t SRCADDR1; /* Channel Source Address 1 */ - register8_t reserved_0x0A; - register8_t reserved_0x0B; - register8_t DESTADDR0; /* Channel Destination Address 0 */ - register8_t DESTADDR1; /* Channel Destination Address 1 */ - register8_t reserved_0x0E; - register8_t reserved_0x0F; -} DMA_CH_t; - - -/* DMA Controller */ -typedef struct DMA_struct -{ - register8_t CTRL; /* Control */ - register8_t reserved_0x01; - register8_t reserved_0x02; - register8_t INTFLAGS; /* Transfer Interrupt Status */ - register8_t STATUS; /* Status */ - register8_t reserved_0x05; - _WORDREGISTER(TEMP); /* Temporary Register For 16-bit Access */ - register8_t reserved_0x08; - register8_t reserved_0x09; - register8_t reserved_0x0A; - register8_t reserved_0x0B; - register8_t reserved_0x0C; - register8_t reserved_0x0D; - register8_t reserved_0x0E; - register8_t reserved_0x0F; - DMA_CH_t CH0; /* DMA Channel 0 */ - DMA_CH_t CH1; /* DMA Channel 1 */ -} DMA_t; - -/* Burst mode */ -typedef enum DMA_CH_BURSTLEN_enum -{ - DMA_CH_BURSTLEN_1BYTE_gc = (0x00<<0), /* 1-byte burst mode */ - DMA_CH_BURSTLEN_2BYTE_gc = (0x01<<0), /* 2-byte burst mode */ - DMA_CH_BURSTLEN_4BYTE_gc = (0x02<<0), /* 4-byte burst mode */ - DMA_CH_BURSTLEN_8BYTE_gc = (0x03<<0), /* 8-byte burst mode */ -} DMA_CH_BURSTLEN_t; - -/* Source address reload mode */ -typedef enum DMA_CH_SRCRELOAD_enum -{ - DMA_CH_SRCRELOAD_NONE_gc = (0x00<<6), /* No reload */ - DMA_CH_SRCRELOAD_BLOCK_gc = (0x01<<6), /* Reload at end of block */ - DMA_CH_SRCRELOAD_BURST_gc = (0x02<<6), /* Reload at end of burst */ - DMA_CH_SRCRELOAD_TRANSACTION_gc = (0x03<<6), /* Reload at end of transaction */ -} DMA_CH_SRCRELOAD_t; - -/* Source addressing mode */ -typedef enum DMA_CH_SRCDIR_enum -{ - DMA_CH_SRCDIR_FIXED_gc = (0x00<<4), /* Fixed */ - DMA_CH_SRCDIR_INC_gc = (0x01<<4), /* Increment */ - DMA_CH_SRCDIR_DEC_gc = (0x02<<4), /* Decrement */ -} DMA_CH_SRCDIR_t; - -/* Destination adress reload mode */ -typedef enum DMA_CH_DESTRELOAD_enum -{ - DMA_CH_DESTRELOAD_NONE_gc = (0x00<<2), /* No reload */ - DMA_CH_DESTRELOAD_BLOCK_gc = (0x01<<2), /* Reload at end of block */ - DMA_CH_DESTRELOAD_BURST_gc = (0x02<<2), /* Reload at end of burst */ - DMA_CH_DESTRELOAD_TRANSACTION_gc = (0x03<<2), /* Reload at end of transaction */ -} DMA_CH_DESTRELOAD_t; - -/* Destination adressing mode */ -typedef enum DMA_CH_DESTDIR_enum -{ - DMA_CH_DESTDIR_FIXED_gc = (0x00<<0), /* Fixed */ - DMA_CH_DESTDIR_INC_gc = (0x01<<0), /* Increment */ - DMA_CH_DESTDIR_DEC_gc = (0x02<<0), /* Decrement */ -} DMA_CH_DESTDIR_t; - -/* Transfer trigger source */ -typedef enum DMA_CH_TRIGSRC_enum -{ - DMA_CH_TRIGSRC_OFF_gc = (0x00<<0), /* Off software triggers only */ - DMA_CH_TRIGSRC_EVSYS_CH0_gc = (0x01<<0), /* Event System Channel 0 */ - DMA_CH_TRIGSRC_EVSYS_CH1_gc = (0x02<<0), /* Event System Channel 1 */ - DMA_CH_TRIGSRC_EVSYS_CH2_gc = (0x03<<0), /* Event System Channel 2 */ - DMA_CH_TRIGSRC_ADCA_CH0_gc = (0x10<<0), /* ADCA Channel 0 */ - DMA_CH_TRIGSRC_ADCB_CH0_gc = (0x20<<0), /* ADCB Channel 0 */ - DMA_CH_TRIGSRC_TCC0_OVF_gc = (0x40<<0), /* Timer/Counter C0 Overflow */ - DMA_CH_TRIGSRC_TCC0_ERR_gc = (0x41<<0), /* Timer/Counter C0 Error */ - DMA_CH_TRIGSRC_TCC0_CCA_gc = (0x42<<0), /* Timer/Counter C0 Compare or Capture A */ - DMA_CH_TRIGSRC_TCC0_CCB_gc = (0x43<<0), /* Timer/Counter C0 Compare or Capture B */ - DMA_CH_TRIGSRC_TCC0_CCC_gc = (0x44<<0), /* Timer/Counter C0 Compare or Capture C */ - DMA_CH_TRIGSRC_TCC0_CCD_gc = (0x45<<0), /* Timer/Counter C0 Compare or Capture D */ - DMA_CH_TRIGSRC_TCC1_OVF_gc = (0x46<<0), /* Timer/Counter C1 Overflow */ - DMA_CH_TRIGSRC_TCC1_ERR_gc = (0x47<<0), /* Timer/Counter C1 Error */ - DMA_CH_TRIGSRC_TCC1_CCA_gc = (0x48<<0), /* Timer/Counter C1 Compare or Capture A */ - DMA_CH_TRIGSRC_TCC1_CCB_gc = (0x49<<0), /* Timer/Counter C1 Compare or Capture B */ - DMA_CH_TRIGSRC_SPIC_gc = (0x4A<<0), /* SPI C Transfer Complete */ - DMA_CH_TRIGSRC_USARTC0_RXC_gc = (0x4B<<0), /* USART C0 Receive Complete */ - DMA_CH_TRIGSRC_USARTC0_DRE_gc = (0x4C<<0), /* USART C0 Data Register Empty */ - DMA_CH_TRIGSRC_TCE0_OVF_gc = (0x80<<0), /* Timer/Counter E0 Overflow */ - DMA_CH_TRIGSRC_TCE0_ERR_gc = (0x81<<0), /* Timer/Counter E0 Error */ - DMA_CH_TRIGSRC_TCE0_CCA_gc = (0x82<<0), /* Timer/Counter E0 Compare or Capture A */ - DMA_CH_TRIGSRC_TCE0_CCB_gc = (0x83<<0), /* Timer/Counter E0 Compare or Capture B */ - DMA_CH_TRIGSRC_TCE0_CCC_gc = (0x84<<0), /* Timer/Counter E0 Compare or Capture C */ - DMA_CH_TRIGSRC_TCE0_CCD_gc = (0x85<<0), /* Timer/Counter E0 Compare or Capture D */ - DMA_CH_TRIGSRC_USARTE0_RXC_gc = (0x8B<<0), /* USART E0 Receive Complete */ - DMA_CH_TRIGSRC_USARTE0_DRE_gc = (0x8C<<0), /* USART E0 Data Register Empty */ -} DMA_CH_TRIGSRC_t; - -/* Double buffering mode */ -typedef enum DMA_DBUFMODE_enum -{ - DMA_DBUFMODE_DISABLED_gc = (0x00<<2), /* Double buffering disabled */ - DMA_DBUFMODE_CH01_gc = (0x01<<2), /* Double buffering enabled on channel 0/1 */ -} DMA_DBUFMODE_t; - -/* Priority mode */ -typedef enum DMA_PRIMODE_enum -{ - DMA_PRIMODE_RR01_gc = (0x00<<0), /* Round Robin */ - DMA_PRIMODE_CH0RR1_gc = (0x01<<0), /* Channel 0 > channel 1 */ -} DMA_PRIMODE_t; - -/* Interrupt level */ -typedef enum DMA_CH_ERRINTLVL_enum -{ - DMA_CH_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ - DMA_CH_ERRINTLVL_LO_gc = (0x01<<2), /* Low level */ - DMA_CH_ERRINTLVL_MED_gc = (0x02<<2), /* Medium level */ - DMA_CH_ERRINTLVL_HI_gc = (0x03<<2), /* High level */ -} DMA_CH_ERRINTLVL_t; - -/* Interrupt level */ -typedef enum DMA_CH_TRNINTLVL_enum -{ - DMA_CH_TRNINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ - DMA_CH_TRNINTLVL_LO_gc = (0x01<<0), /* Low level */ - DMA_CH_TRNINTLVL_MED_gc = (0x02<<0), /* Medium level */ - DMA_CH_TRNINTLVL_HI_gc = (0x03<<0), /* High level */ -} DMA_CH_TRNINTLVL_t; - - -/* --------------------------------------------------------------------------- -EVSYS - Event System --------------------------------------------------------------------------- -*/ - -/* Event System */ -typedef struct EVSYS_struct -{ - register8_t CH0MUX; /* Event Channel 0 Multiplexer */ - register8_t CH1MUX; /* Event Channel 1 Multiplexer */ - register8_t CH2MUX; /* Event Channel 2 Multiplexer */ - register8_t CH3MUX; /* Event Channel 3 Multiplexer */ - register8_t reserved_0x04; - register8_t reserved_0x05; - register8_t reserved_0x06; - register8_t reserved_0x07; - register8_t CH0CTRL; /* Channel 0 Control Register */ - register8_t CH1CTRL; /* Channel 1 Control Register */ - register8_t CH2CTRL; /* Channel 2 Control Register */ - register8_t CH3CTRL; /* Channel 3 Control Register */ - register8_t reserved_0x0C; - register8_t reserved_0x0D; - register8_t reserved_0x0E; - register8_t reserved_0x0F; - register8_t STROBE; /* Event Strobe */ - register8_t DATA; /* Event Data */ -} EVSYS_t; - -/* Quadrature Decoder Index Recognition Mode */ -typedef enum EVSYS_QDIRM_enum -{ - EVSYS_QDIRM_00_gc = (0x00<<5), /* QDPH0 = 0, QDPH90 = 0 */ - EVSYS_QDIRM_01_gc = (0x01<<5), /* QDPH0 = 0, QDPH90 = 1 */ - EVSYS_QDIRM_10_gc = (0x02<<5), /* QDPH0 = 1, QDPH90 = 0 */ - EVSYS_QDIRM_11_gc = (0x03<<5), /* QDPH0 = 1, QDPH90 = 1 */ -} EVSYS_QDIRM_t; - -/* Digital filter coefficient */ -typedef enum EVSYS_DIGFILT_enum -{ - EVSYS_DIGFILT_1SAMPLE_gc = (0x00<<0), /* 1 SAMPLE */ - EVSYS_DIGFILT_2SAMPLES_gc = (0x01<<0), /* 2 SAMPLES */ - EVSYS_DIGFILT_3SAMPLES_gc = (0x02<<0), /* 3 SAMPLES */ - EVSYS_DIGFILT_4SAMPLES_gc = (0x03<<0), /* 4 SAMPLES */ - EVSYS_DIGFILT_5SAMPLES_gc = (0x04<<0), /* 5 SAMPLES */ - EVSYS_DIGFILT_6SAMPLES_gc = (0x05<<0), /* 6 SAMPLES */ - EVSYS_DIGFILT_7SAMPLES_gc = (0x06<<0), /* 7 SAMPLES */ - EVSYS_DIGFILT_8SAMPLES_gc = (0x07<<0), /* 8 SAMPLES */ -} EVSYS_DIGFILT_t; - -/* Event Channel multiplexer input selection */ -typedef enum EVSYS_CHMUX_enum -{ - EVSYS_CHMUX_OFF_gc = (0x00<<0), /* Off */ - EVSYS_CHMUX_RTC_OVF_gc = (0x08<<0), /* RTC Overflow */ - EVSYS_CHMUX_RTC_CMP_gc = (0x09<<0), /* RTC Compare Match */ - EVSYS_CHMUX_USB_gc = (0x0A<<0), /* USB Setup, SOF, CRC error and UNF/OVF */ - EVSYS_CHMUX_ACA_CH0_gc = (0x10<<0), /* Analog Comparator A Channel 0 */ - EVSYS_CHMUX_ACA_CH1_gc = (0x11<<0), /* Analog Comparator A Channel 1 */ - EVSYS_CHMUX_ACA_WIN_gc = (0x12<<0), /* Analog Comparator A Window */ - EVSYS_CHMUX_ACB_CH0_gc = (0x13<<0), /* Analog Comparator B Channel 0 */ - EVSYS_CHMUX_ACB_CH1_gc = (0x14<<0), /* Analog Comparator B Channel 1 */ - EVSYS_CHMUX_ACB_WIN_gc = (0x15<<0), /* Analog Comparator B Window */ - EVSYS_CHMUX_ADCA_CH0_gc = (0x20<<0), /* ADC A Channel */ - EVSYS_CHMUX_ADCB_CH0_gc = (0x24<<0), /* ADC B Channel */ - EVSYS_CHMUX_PORTA_PIN0_gc = (0x50<<0), /* Port A, Pin0 */ - EVSYS_CHMUX_PORTA_PIN1_gc = (0x51<<0), /* Port A, Pin1 */ - EVSYS_CHMUX_PORTA_PIN2_gc = (0x52<<0), /* Port A, Pin2 */ - EVSYS_CHMUX_PORTA_PIN3_gc = (0x53<<0), /* Port A, Pin3 */ - EVSYS_CHMUX_PORTA_PIN4_gc = (0x54<<0), /* Port A, Pin4 */ - EVSYS_CHMUX_PORTA_PIN5_gc = (0x55<<0), /* Port A, Pin5 */ - EVSYS_CHMUX_PORTA_PIN6_gc = (0x56<<0), /* Port A, Pin6 */ - EVSYS_CHMUX_PORTA_PIN7_gc = (0x57<<0), /* Port A, Pin7 */ - EVSYS_CHMUX_PORTB_PIN0_gc = (0x58<<0), /* Port B, Pin0 */ - EVSYS_CHMUX_PORTB_PIN1_gc = (0x59<<0), /* Port B, Pin1 */ - EVSYS_CHMUX_PORTB_PIN2_gc = (0x5A<<0), /* Port B, Pin2 */ - EVSYS_CHMUX_PORTB_PIN3_gc = (0x5B<<0), /* Port B, Pin3 */ - EVSYS_CHMUX_PORTB_PIN4_gc = (0x5C<<0), /* Port B, Pin4 */ - EVSYS_CHMUX_PORTB_PIN5_gc = (0x5D<<0), /* Port B, Pin5 */ - EVSYS_CHMUX_PORTB_PIN6_gc = (0x5E<<0), /* Port B, Pin6 */ - EVSYS_CHMUX_PORTB_PIN7_gc = (0x5F<<0), /* Port B, Pin7 */ - EVSYS_CHMUX_PORTC_PIN0_gc = (0x60<<0), /* Port C, Pin0 */ - EVSYS_CHMUX_PORTC_PIN1_gc = (0x61<<0), /* Port C, Pin1 */ - EVSYS_CHMUX_PORTC_PIN2_gc = (0x62<<0), /* Port C, Pin2 */ - EVSYS_CHMUX_PORTC_PIN3_gc = (0x63<<0), /* Port C, Pin3 */ - EVSYS_CHMUX_PORTC_PIN4_gc = (0x64<<0), /* Port C, Pin4 */ - EVSYS_CHMUX_PORTC_PIN5_gc = (0x65<<0), /* Port C, Pin5 */ - EVSYS_CHMUX_PORTC_PIN6_gc = (0x66<<0), /* Port C, Pin6 */ - EVSYS_CHMUX_PORTC_PIN7_gc = (0x67<<0), /* Port C, Pin7 */ - EVSYS_CHMUX_PORTD_PIN0_gc = (0x68<<0), /* Port D, Pin0 */ - EVSYS_CHMUX_PORTD_PIN1_gc = (0x69<<0), /* Port D, Pin1 */ - EVSYS_CHMUX_PORTD_PIN2_gc = (0x6A<<0), /* Port D, Pin2 */ - EVSYS_CHMUX_PORTE_PIN0_gc = (0x70<<0), /* Port E, Pin0 */ - EVSYS_CHMUX_PORTE_PIN1_gc = (0x71<<0), /* Port E, Pin1 */ - EVSYS_CHMUX_PORTE_PIN2_gc = (0x72<<0), /* Port E, Pin2 */ - EVSYS_CHMUX_PORTE_PIN3_gc = (0x73<<0), /* Port E, Pin3 */ - EVSYS_CHMUX_PORTE_PIN4_gc = (0x74<<0), /* Port E, Pin4 */ - EVSYS_CHMUX_PORTE_PIN5_gc = (0x75<<0), /* Port E, Pin5 */ - EVSYS_CHMUX_PORTE_PIN6_gc = (0x76<<0), /* Port E, Pin6 */ - EVSYS_CHMUX_PORTE_PIN7_gc = (0x77<<0), /* Port E, Pin7 */ - EVSYS_CHMUX_PRESCALER_1_gc = (0x80<<0), /* Prescaler, divide by 1 */ - EVSYS_CHMUX_PRESCALER_2_gc = (0x81<<0), /* Prescaler, divide by 2 */ - EVSYS_CHMUX_PRESCALER_4_gc = (0x82<<0), /* Prescaler, divide by 4 */ - EVSYS_CHMUX_PRESCALER_8_gc = (0x83<<0), /* Prescaler, divide by 8 */ - EVSYS_CHMUX_PRESCALER_16_gc = (0x84<<0), /* Prescaler, divide by 16 */ - EVSYS_CHMUX_PRESCALER_32_gc = (0x85<<0), /* Prescaler, divide by 32 */ - EVSYS_CHMUX_PRESCALER_64_gc = (0x86<<0), /* Prescaler, divide by 64 */ - EVSYS_CHMUX_PRESCALER_128_gc = (0x87<<0), /* Prescaler, divide by 128 */ - EVSYS_CHMUX_PRESCALER_256_gc = (0x88<<0), /* Prescaler, divide by 256 */ - EVSYS_CHMUX_PRESCALER_512_gc = (0x89<<0), /* Prescaler, divide by 512 */ - EVSYS_CHMUX_PRESCALER_1024_gc = (0x8A<<0), /* Prescaler, divide by 1024 */ - EVSYS_CHMUX_PRESCALER_2048_gc = (0x8B<<0), /* Prescaler, divide by 2048 */ - EVSYS_CHMUX_PRESCALER_4096_gc = (0x8C<<0), /* Prescaler, divide by 4096 */ - EVSYS_CHMUX_PRESCALER_8192_gc = (0x8D<<0), /* Prescaler, divide by 8192 */ - EVSYS_CHMUX_PRESCALER_16384_gc = (0x8E<<0), /* Prescaler, divide by 16384 */ - EVSYS_CHMUX_PRESCALER_32768_gc = (0x8F<<0), /* Prescaler, divide by 32768 */ - EVSYS_CHMUX_TCC0_OVF_gc = (0xC0<<0), /* Timer/Counter C0 Overflow */ - EVSYS_CHMUX_TCC0_ERR_gc = (0xC1<<0), /* Timer/Counter C0 Error */ - EVSYS_CHMUX_TCC0_CCA_gc = (0xC4<<0), /* Timer/Counter C0 Compare or Capture A */ - EVSYS_CHMUX_TCC0_CCB_gc = (0xC5<<0), /* Timer/Counter C0 Compare or Capture B */ - EVSYS_CHMUX_TCC0_CCC_gc = (0xC6<<0), /* Timer/Counter C0 Compare or Capture C */ - EVSYS_CHMUX_TCC0_CCD_gc = (0xC7<<0), /* Timer/Counter C0 Compare or Capture D */ - EVSYS_CHMUX_TCC1_OVF_gc = (0xC8<<0), /* Timer/Counter C1 Overflow */ - EVSYS_CHMUX_TCC1_ERR_gc = (0xC9<<0), /* Timer/Counter C1 Error */ - EVSYS_CHMUX_TCC1_CCA_gc = (0xCC<<0), /* Timer/Counter C1 Compare or Capture A */ - EVSYS_CHMUX_TCC1_CCB_gc = (0xCD<<0), /* Timer/Counter C1 Compare or Capture B */ - EVSYS_CHMUX_TCE0_OVF_gc = (0xE0<<0), /* Timer/Counter E0 Overflow */ - EVSYS_CHMUX_TCE0_ERR_gc = (0xE1<<0), /* Timer/Counter E0 Error */ - EVSYS_CHMUX_TCE0_CCA_gc = (0xE4<<0), /* Timer/Counter E0 Compare or Capture A */ - EVSYS_CHMUX_TCE0_CCB_gc = (0xE5<<0), /* Timer/Counter E0 Compare or Capture B */ - EVSYS_CHMUX_TCE0_CCC_gc = (0xE6<<0), /* Timer/Counter E0 Compare or Capture C */ - EVSYS_CHMUX_TCE0_CCD_gc = (0xE7<<0), /* Timer/Counter E0 Compare or Capture D */ -} EVSYS_CHMUX_t; - - -/* --------------------------------------------------------------------------- -NVM - Non Volatile Memory Controller --------------------------------------------------------------------------- -*/ - -/* Non-volatile Memory Controller */ -typedef struct NVM_struct -{ - register8_t ADDR0; /* Address Register 0 */ - register8_t ADDR1; /* Address Register 1 */ - register8_t ADDR2; /* Address Register 2 */ - register8_t reserved_0x03; - register8_t DATA0; /* Data Register 0 */ - register8_t DATA1; /* Data Register 1 */ - register8_t DATA2; /* Data Register 2 */ - register8_t reserved_0x07; - register8_t reserved_0x08; - register8_t reserved_0x09; - register8_t CMD; /* Command */ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t INTCTRL; /* Interrupt Control */ - register8_t reserved_0x0E; - register8_t STATUS; /* Status */ - register8_t LOCK_BITS; /* Lock Bits (Changed from LOCKBITS to avoid avr-libc collision) */ -} NVM_t; - -/* NVM Command */ -typedef enum NVM_CMD_enum -{ - NVM_CMD_NO_OPERATION_gc = (0x00<<0), /* Noop/Ordinary LPM */ - NVM_CMD_READ_USER_SIG_ROW_gc = (0x01<<0), /* Read user signature row */ - NVM_CMD_READ_CALIB_ROW_gc = (0x02<<0), /* Read calibration row */ - NVM_CMD_READ_EEPROM_gc = (0x06<<0), /* Read EEPROM */ - NVM_CMD_READ_FUSES_gc = (0x07<<0), /* Read fuse byte */ - NVM_CMD_WRITE_LOCK_BITS_gc = (0x08<<0), /* Write lock bits */ - NVM_CMD_ERASE_USER_SIG_ROW_gc = (0x18<<0), /* Erase user signature row */ - NVM_CMD_WRITE_USER_SIG_ROW_gc = (0x1A<<0), /* Write user signature row */ - NVM_CMD_ERASE_APP_gc = (0x20<<0), /* Erase Application Section */ - NVM_CMD_ERASE_APP_PAGE_gc = (0x22<<0), /* Erase Application Section page */ - NVM_CMD_LOAD_FLASH_BUFFER_gc = (0x23<<0), /* Load Flash page buffer */ - NVM_CMD_WRITE_APP_PAGE_gc = (0x24<<0), /* Write Application Section page */ - NVM_CMD_ERASE_WRITE_APP_PAGE_gc = (0x25<<0), /* Erase-and-write Application Section page */ - NVM_CMD_ERASE_FLASH_BUFFER_gc = (0x26<<0), /* Erase/flush Flash page buffer */ - NVM_CMD_ERASE_BOOT_PAGE_gc = (0x2A<<0), /* Erase Boot Section page */ - NVM_CMD_ERASE_FLASH_PAGE_gc = (0x2B<<0), /* Erase Flash Page */ - NVM_CMD_WRITE_BOOT_PAGE_gc = (0x2C<<0), /* Write Boot Section page */ - NVM_CMD_ERASE_WRITE_BOOT_PAGE_gc = (0x2D<<0), /* Erase-and-write Boot Section page */ - NVM_CMD_WRITE_FLASH_PAGE_gc = (0x2E<<0), /* Write Flash Page */ - NVM_CMD_ERASE_WRITE_FLASH_PAGE_gc = (0x2F<<0), /* Erase-and-write Flash Page */ - NVM_CMD_ERASE_EEPROM_gc = (0x30<<0), /* Erase EEPROM */ - NVM_CMD_ERASE_EEPROM_PAGE_gc = (0x32<<0), /* Erase EEPROM page */ - NVM_CMD_LOAD_EEPROM_BUFFER_gc = (0x33<<0), /* Load EEPROM page buffer */ - NVM_CMD_WRITE_EEPROM_PAGE_gc = (0x34<<0), /* Write EEPROM page */ - NVM_CMD_ERASE_WRITE_EEPROM_PAGE_gc = (0x35<<0), /* Erase-and-write EEPROM page */ - NVM_CMD_ERASE_EEPROM_BUFFER_gc = (0x36<<0), /* Erase/flush EEPROM page buffer */ - NVM_CMD_APP_CRC_gc = (0x38<<0), /* Application section CRC */ - NVM_CMD_BOOT_CRC_gc = (0x39<<0), /* Boot Section CRC */ - NVM_CMD_FLASH_RANGE_CRC_gc = (0x3A<<0), /* Flash Range CRC */ - NVM_CMD_CHIP_ERASE_gc = (0x40<<0), /* Erase Chip */ - NVM_CMD_READ_NVM_gc = (0x43<<0), /* Read NVM */ - NVM_CMD_WRITE_FUSE_gc = (0x4C<<0), /* Write Fuse byte */ - NVM_CMD_ERASE_BOOT_gc = (0x68<<0), /* Erase Boot Section */ - NVM_CMD_FLASH_CRC_gc = (0x78<<0), /* Flash CRC */ -} NVM_CMD_t; - -/* SPM ready interrupt level */ -typedef enum NVM_SPMLVL_enum -{ - NVM_SPMLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ - NVM_SPMLVL_LO_gc = (0x01<<2), /* Low level */ - NVM_SPMLVL_MED_gc = (0x02<<2), /* Medium level */ - NVM_SPMLVL_HI_gc = (0x03<<2), /* High level */ -} NVM_SPMLVL_t; - -/* EEPROM ready interrupt level */ -typedef enum NVM_EELVL_enum -{ - NVM_EELVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ - NVM_EELVL_LO_gc = (0x01<<0), /* Low level */ - NVM_EELVL_MED_gc = (0x02<<0), /* Medium level */ - NVM_EELVL_HI_gc = (0x03<<0), /* High level */ -} NVM_EELVL_t; - -/* Boot lock bits - boot setcion */ -typedef enum NVM_BLBB_enum -{ - NVM_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ - NVM_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ - NVM_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ - NVM_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ -} NVM_BLBB_t; - -/* Boot lock bits - application section */ -typedef enum NVM_BLBA_enum -{ - NVM_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ - NVM_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ - NVM_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ - NVM_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ -} NVM_BLBA_t; - -/* Boot lock bits - application table section */ -typedef enum NVM_BLBAT_enum -{ - NVM_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ - NVM_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ - NVM_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ - NVM_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ -} NVM_BLBAT_t; - -/* Lock bits */ -typedef enum NVM_LB_enum -{ - NVM_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ - NVM_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ - NVM_LB_NOLOCK_gc = (0x03<<0), /* No locks */ -} NVM_LB_t; - - -/* --------------------------------------------------------------------------- -ADC - Analog/Digital Converter --------------------------------------------------------------------------- -*/ - -/* ADC Channel */ -typedef struct ADC_CH_struct -{ - register8_t CTRL; /* Control Register */ - register8_t MUXCTRL; /* MUX Control */ - register8_t INTCTRL; /* Channel Interrupt Control Register */ - register8_t INTFLAGS; /* Interrupt Flags */ - _WORDREGISTER(RES); /* Channel Result */ - register8_t SCAN; /* Input Channel Scan */ - register8_t reserved_0x07; -} ADC_CH_t; - - -/* Analog-to-Digital Converter */ -typedef struct ADC_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t REFCTRL; /* Reference Control */ - register8_t EVCTRL; /* Event Control */ - register8_t PRESCALER; /* Clock Prescaler */ - register8_t reserved_0x05; - register8_t INTFLAGS; /* Interrupt Flags */ - register8_t TEMP; /* Temporary Register */ - register8_t SAMPCTRL; /* ADC Sampling Time Control Register */ - register8_t reserved_0x09; - register8_t reserved_0x0A; - register8_t reserved_0x0B; - _WORDREGISTER(CAL); /* Calibration Value */ - register8_t reserved_0x0E; - register8_t reserved_0x0F; - _WORDREGISTER(CH0RES); /* Channel 0 Result */ - register8_t reserved_0x12; - register8_t reserved_0x13; - register8_t reserved_0x14; - register8_t reserved_0x15; - register8_t reserved_0x16; - register8_t reserved_0x17; - _WORDREGISTER(CMP); /* Compare Value */ - register8_t reserved_0x1A; - register8_t reserved_0x1B; - register8_t reserved_0x1C; - register8_t reserved_0x1D; - register8_t reserved_0x1E; - register8_t reserved_0x1F; - ADC_CH_t CH0; /* ADC Channel 0 */ -} ADC_t; - -/* Current Limitation */ -typedef enum ADC_CURRLIMIT_enum -{ - ADC_CURRLIMIT_NO_gc = (0x00<<5), /* No current limit, 300ksps max sampling rate */ - ADC_CURRLIMIT_LOW_gc = (0x01<<5), /* Low current limit, 250ksps max sampling rate */ - ADC_CURRLIMIT_MED_gc = (0x02<<5), /* Medium current limit, 150ksps max sampling rate */ - ADC_CURRLIMIT_HIGH_gc = (0x03<<5), /* High current limit, 50ksps max sampling rate */ -} ADC_CURRLIMIT_t; - -/* Positive input multiplexer selection */ -typedef enum ADC_CH_MUXPOS_enum -{ - ADC_CH_MUXPOS_PIN0_gc = (0x00<<3), /* Input pin 0 */ - ADC_CH_MUXPOS_PIN1_gc = (0x01<<3), /* Input pin 1 */ - ADC_CH_MUXPOS_PIN2_gc = (0x02<<3), /* Input pin 2 */ - ADC_CH_MUXPOS_PIN3_gc = (0x03<<3), /* Input pin 3 */ - ADC_CH_MUXPOS_PIN4_gc = (0x04<<3), /* Input pin 4 */ - ADC_CH_MUXPOS_PIN5_gc = (0x05<<3), /* Input pin 5 */ - ADC_CH_MUXPOS_PIN6_gc = (0x06<<3), /* Input pin 6 */ - ADC_CH_MUXPOS_PIN7_gc = (0x07<<3), /* Input pin 7 */ - ADC_CH_MUXPOS_PIN8_gc = (0x08<<3), /* Input pin 8 */ - ADC_CH_MUXPOS_PIN9_gc = (0x09<<3), /* Input pin 9 */ - ADC_CH_MUXPOS_PIN10_gc = (0x0A<<3), /* Input pin 10 */ - ADC_CH_MUXPOS_PIN11_gc = (0x0B<<3), /* Input pin 11 */ - ADC_CH_MUXPOS_PIN12_gc = (0x0C<<3), /* Input pin 12 */ - ADC_CH_MUXPOS_PIN13_gc = (0x0D<<3), /* Input pin 13 */ - ADC_CH_MUXPOS_PIN14_gc = (0x0E<<3), /* Input pin 14 */ - ADC_CH_MUXPOS_PIN15_gc = (0x0F<<3), /* Input pin 15 */ -} ADC_CH_MUXPOS_t; - -/* Internal input multiplexer selections */ -typedef enum ADC_CH_MUXINT_enum -{ - ADC_CH_MUXINT_TEMP_gc = (0x00<<3), /* Temperature Reference */ - ADC_CH_MUXINT_BANDGAP_gc = (0x01<<3), /* Bandgap Reference */ - ADC_CH_MUXINT_SCALEDVCC_gc = (0x02<<3), /* 1/10 scaled VCC */ -} ADC_CH_MUXINT_t; - -/* Negative input multiplexer selection */ -typedef enum ADC_CH_MUXNEG_enum -{ - ADC_CH_MUXNEG_PIN0_gc = (0x00<<0), /* Input pin 0 */ - ADC_CH_MUXNEG_PIN1_gc = (0x01<<0), /* Input pin 1 */ - ADC_CH_MUXNEG_PIN2_gc = (0x02<<0), /* Input pin 2 */ - ADC_CH_MUXNEG_PIN3_gc = (0x03<<0), /* Input pin 3 */ - ADC_CH_MUXNEG_PIN4_gc = (0x00<<0), /* Input pin 4 */ - ADC_CH_MUXNEG_PIN5_gc = (0x01<<0), /* Input pin 5 */ - ADC_CH_MUXNEG_PIN6_gc = (0x02<<0), /* Input pin 6 */ - ADC_CH_MUXNEG_PIN7_gc = (0x03<<0), /* Input pin 7 */ -} ADC_CH_MUXNEG_t; - -/* Input mode */ -typedef enum ADC_CH_INPUTMODE_enum -{ - ADC_CH_INPUTMODE_INTERNAL_gc = (0x00<<0), /* Internal inputs, no gain */ - ADC_CH_INPUTMODE_SINGLEENDED_gc = (0x01<<0), /* Single-ended input, no gain */ - ADC_CH_INPUTMODE_DIFF_gc = (0x02<<0), /* Differential input, no gain */ - ADC_CH_INPUTMODE_DIFFWGAIN_gc = (0x03<<0), /* Differential input, with gain */ -} ADC_CH_INPUTMODE_t; - -/* Gain factor */ -typedef enum ADC_CH_GAIN_enum -{ - ADC_CH_GAIN_1X_gc = (0x00<<2), /* 1x gain */ - ADC_CH_GAIN_2X_gc = (0x01<<2), /* 2x gain */ - ADC_CH_GAIN_4X_gc = (0x02<<2), /* 4x gain */ - ADC_CH_GAIN_8X_gc = (0x03<<2), /* 8x gain */ - ADC_CH_GAIN_16X_gc = (0x04<<2), /* 16x gain */ - ADC_CH_GAIN_32X_gc = (0x05<<2), /* 32x gain */ - ADC_CH_GAIN_64X_gc = (0x06<<2), /* 64x gain */ - ADC_CH_GAIN_DIV2_gc = (0x07<<2), /* x/2 gain */ -} ADC_CH_GAIN_t; - -/* Conversion result resolution */ -typedef enum ADC_RESOLUTION_enum -{ - ADC_RESOLUTION_12BIT_gc = (0x00<<1), /* 12-bit right-adjusted result */ - ADC_RESOLUTION_8BIT_gc = (0x02<<1), /* 8-bit right-adjusted result */ - ADC_RESOLUTION_LEFT12BIT_gc = (0x03<<1), /* 12-bit left-adjusted result */ -} ADC_RESOLUTION_t; - -/* Voltage reference selection */ -typedef enum ADC_REFSEL_enum -{ - ADC_REFSEL_INT1V_gc = (0x00<<4), /* Internal 1V */ - ADC_REFSEL_INTVCC_gc = (0x01<<4), /* Internal VCC / 1.6 */ - ADC_REFSEL_AREFA_gc = (0x02<<4), /* External reference on PORT A */ - ADC_REFSEL_AREFB_gc = (0x03<<4), /* External reference on PORT B */ - ADC_REFSEL_INTVCC2_gc = (0x04<<4), /* Internal VCC / 2 */ -} ADC_REFSEL_t; - -/* Event channel input selection */ -typedef enum ADC_EVSEL_enum -{ - ADC_EVSEL_0_gc = (0x00<<3), /* Event Channel 0 */ - ADC_EVSEL_1_gc = (0x01<<3), /* Event Channel 1 */ - ADC_EVSEL_2_gc = (0x02<<3), /* Event Channel 2 */ - ADC_EVSEL_3_gc = (0x03<<3), /* Event Channel 3 */ -} ADC_EVSEL_t; - -/* Event action selection */ -typedef enum ADC_EVACT_enum -{ - ADC_EVACT_NONE_gc = (0x00<<0), /* No event action */ - ADC_EVACT_CH0_gc = (0x01<<0), /* First event triggers channel 0 */ - ADC_EVACT_SYNCSWEEP_gc = (0x06<<0), /* The ADC is flushed and restarted for accurate timing */ -} ADC_EVACT_t; - -/* Interupt mode */ -typedef enum ADC_CH_INTMODE_enum -{ - ADC_CH_INTMODE_COMPLETE_gc = (0x00<<2), /* Interrupt on conversion complete */ - ADC_CH_INTMODE_BELOW_gc = (0x01<<2), /* Interrupt on result below compare value */ - ADC_CH_INTMODE_ABOVE_gc = (0x03<<2), /* Interrupt on result above compare value */ -} ADC_CH_INTMODE_t; - -/* Interrupt level */ -typedef enum ADC_CH_INTLVL_enum -{ - ADC_CH_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ - ADC_CH_INTLVL_LO_gc = (0x01<<0), /* Low level */ - ADC_CH_INTLVL_MED_gc = (0x02<<0), /* Medium level */ - ADC_CH_INTLVL_HI_gc = (0x03<<0), /* High level */ -} ADC_CH_INTLVL_t; - -/* Clock prescaler */ -typedef enum ADC_PRESCALER_enum -{ - ADC_PRESCALER_DIV4_gc = (0x00<<0), /* Divide clock by 4 */ - ADC_PRESCALER_DIV8_gc = (0x01<<0), /* Divide clock by 8 */ - ADC_PRESCALER_DIV16_gc = (0x02<<0), /* Divide clock by 16 */ - ADC_PRESCALER_DIV32_gc = (0x03<<0), /* Divide clock by 32 */ - ADC_PRESCALER_DIV64_gc = (0x04<<0), /* Divide clock by 64 */ - ADC_PRESCALER_DIV128_gc = (0x05<<0), /* Divide clock by 128 */ - ADC_PRESCALER_DIV256_gc = (0x06<<0), /* Divide clock by 256 */ - ADC_PRESCALER_DIV512_gc = (0x07<<0), /* Divide clock by 512 */ -} ADC_PRESCALER_t; - - -/* --------------------------------------------------------------------------- -AC - Analog Comparator --------------------------------------------------------------------------- -*/ - -/* Analog Comparator */ -typedef struct AC_struct -{ - register8_t AC0CTRL; /* Analog Comparator 0 Control */ - register8_t AC1CTRL; /* Analog Comparator 1 Control */ - register8_t AC0MUXCTRL; /* Analog Comparator 0 MUX Control */ - register8_t AC1MUXCTRL; /* Analog Comparator 1 MUX Control */ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t WINCTRL; /* Window Mode Control */ - register8_t STATUS; /* Status */ - register8_t CURRCTRL; /* Current Source Control Register */ - register8_t CURRCALIB; /* Current Source Calibration Register */ -} AC_t; - -/* Interrupt mode */ -typedef enum AC_INTMODE_enum -{ - AC_INTMODE_BOTHEDGES_gc = (0x00<<6), /* Interrupt on both edges */ - AC_INTMODE_FALLING_gc = (0x02<<6), /* Interrupt on falling edge */ - AC_INTMODE_RISING_gc = (0x03<<6), /* Interrupt on rising edge */ -} AC_INTMODE_t; - -/* Interrupt level */ -typedef enum AC_INTLVL_enum -{ - AC_INTLVL_OFF_gc = (0x00<<4), /* Interrupt disabled */ - AC_INTLVL_LO_gc = (0x01<<4), /* Low level */ - AC_INTLVL_MED_gc = (0x02<<4), /* Medium level */ - AC_INTLVL_HI_gc = (0x03<<4), /* High level */ -} AC_INTLVL_t; - -/* Hysteresis mode selection */ -typedef enum AC_HYSMODE_enum -{ - AC_HYSMODE_NO_gc = (0x00<<1), /* No hysteresis */ - AC_HYSMODE_SMALL_gc = (0x01<<1), /* Small hysteresis */ - AC_HYSMODE_LARGE_gc = (0x02<<1), /* Large hysteresis */ -} AC_HYSMODE_t; - -/* Positive input multiplexer selection */ -typedef enum AC_MUXPOS_enum -{ - AC_MUXPOS_PIN0_gc = (0x00<<3), /* Pin 0 */ - AC_MUXPOS_PIN1_gc = (0x01<<3), /* Pin 1 */ - AC_MUXPOS_PIN2_gc = (0x02<<3), /* Pin 2 */ - AC_MUXPOS_PIN3_gc = (0x03<<3), /* Pin 3 */ - AC_MUXPOS_PIN4_gc = (0x04<<3), /* Pin 4 */ - AC_MUXPOS_PIN5_gc = (0x05<<3), /* Pin 5 */ - AC_MUXPOS_PIN6_gc = (0x06<<3), /* Pin 6 */ -} AC_MUXPOS_t; - -/* Negative input multiplexer selection */ -typedef enum AC_MUXNEG_enum -{ - AC_MUXNEG_PIN0_gc = (0x00<<0), /* Pin 0 */ - AC_MUXNEG_PIN1_gc = (0x01<<0), /* Pin 1 */ - AC_MUXNEG_PIN3_gc = (0x02<<0), /* Pin 3 */ - AC_MUXNEG_PIN5_gc = (0x03<<0), /* Pin 5 */ - AC_MUXNEG_PIN7_gc = (0x04<<0), /* Pin 7 */ - AC_MUXNEG_BANDGAP_gc = (0x06<<0), /* Bandgap Reference */ - AC_MUXNEG_SCALER_gc = (0x07<<0), /* Internal voltage scaler */ -} AC_MUXNEG_t; - -/* Windows interrupt mode */ -typedef enum AC_WINTMODE_enum -{ - AC_WINTMODE_ABOVE_gc = (0x00<<2), /* Interrupt on above window */ - AC_WINTMODE_INSIDE_gc = (0x01<<2), /* Interrupt on inside window */ - AC_WINTMODE_BELOW_gc = (0x02<<2), /* Interrupt on below window */ - AC_WINTMODE_OUTSIDE_gc = (0x03<<2), /* Interrupt on outside window */ -} AC_WINTMODE_t; - -/* Window interrupt level */ -typedef enum AC_WINTLVL_enum -{ - AC_WINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ - AC_WINTLVL_LO_gc = (0x01<<0), /* Low priority */ - AC_WINTLVL_MED_gc = (0x02<<0), /* Medium priority */ - AC_WINTLVL_HI_gc = (0x03<<0), /* High priority */ -} AC_WINTLVL_t; - -/* Window mode state */ -typedef enum AC_WSTATE_enum -{ - AC_WSTATE_ABOVE_gc = (0x00<<6), /* Signal above window */ - AC_WSTATE_INSIDE_gc = (0x01<<6), /* Signal inside window */ - AC_WSTATE_BELOW_gc = (0x02<<6), /* Signal below window */ -} AC_WSTATE_t; - - -/* --------------------------------------------------------------------------- -RTC - Real-Time Counter --------------------------------------------------------------------------- -*/ - -/* Real-Time Counter */ -typedef struct RTC_struct -{ - register8_t CTRL; /* Control Register */ - register8_t STATUS; /* Status Register */ - register8_t INTCTRL; /* Interrupt Control Register */ - register8_t INTFLAGS; /* Interrupt Flags */ - register8_t TEMP; /* Temporary register */ - register8_t reserved_0x05; - register8_t reserved_0x06; - register8_t reserved_0x07; - _WORDREGISTER(CNT); /* Count Register */ - _WORDREGISTER(PER); /* Period Register */ - _WORDREGISTER(COMP); /* Compare Register */ -} RTC_t; - -/* Prescaler Factor */ -typedef enum RTC_PRESCALER_enum -{ - RTC_PRESCALER_OFF_gc = (0x00<<0), /* RTC Off */ - RTC_PRESCALER_DIV1_gc = (0x01<<0), /* RTC Clock */ - RTC_PRESCALER_DIV2_gc = (0x02<<0), /* RTC Clock / 2 */ - RTC_PRESCALER_DIV8_gc = (0x03<<0), /* RTC Clock / 8 */ - RTC_PRESCALER_DIV16_gc = (0x04<<0), /* RTC Clock / 16 */ - RTC_PRESCALER_DIV64_gc = (0x05<<0), /* RTC Clock / 64 */ - RTC_PRESCALER_DIV256_gc = (0x06<<0), /* RTC Clock / 256 */ - RTC_PRESCALER_DIV1024_gc = (0x07<<0), /* RTC Clock / 1024 */ -} RTC_PRESCALER_t; - -/* Compare Interrupt level */ -typedef enum RTC_COMPINTLVL_enum -{ - RTC_COMPINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ - RTC_COMPINTLVL_LO_gc = (0x01<<2), /* Low Level */ - RTC_COMPINTLVL_MED_gc = (0x02<<2), /* Medium Level */ - RTC_COMPINTLVL_HI_gc = (0x03<<2), /* High Level */ -} RTC_COMPINTLVL_t; - -/* Overflow Interrupt level */ -typedef enum RTC_OVFINTLVL_enum -{ - RTC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - RTC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ - RTC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ - RTC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ -} RTC_OVFINTLVL_t; - - -/* --------------------------------------------------------------------------- -TWI - Two-Wire Interface --------------------------------------------------------------------------- -*/ - -/* */ -typedef struct TWI_MASTER_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t CTRLC; /* Control Register C */ - register8_t STATUS; /* Status Register */ - register8_t BAUD; /* Baurd Rate Control Register */ - register8_t ADDR; /* Address Register */ - register8_t DATA; /* Data Register */ -} TWI_MASTER_t; - - -/* */ -typedef struct TWI_SLAVE_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t STATUS; /* Status Register */ - register8_t ADDR; /* Address Register */ - register8_t DATA; /* Data Register */ - register8_t ADDRMASK; /* Address Mask Register */ -} TWI_SLAVE_t; - - -/* Two-Wire Interface */ -typedef struct TWI_struct -{ - register8_t CTRL; /* TWI Common Control Register */ - TWI_MASTER_t MASTER; /* TWI master module */ - TWI_SLAVE_t SLAVE; /* TWI slave module */ -} TWI_t; - -/* SDA Hold Time */ -typedef enum TWI_SDAHOLD_enum -{ - TWI_SDAHOLD_OFF_gc = (0x00<<1), /* SDA Hold Time off */ - TWI_SDAHOLD_50NS_gc = (0x01<<1), /* SDA Hold Time 50 ns */ - TWI_SDAHOLD_300NS_gc = (0x02<<1), /* SDA Hold Time 300 ns */ - TWI_SDAHOLD_400NS_gc = (0x03<<1), /* SDA Hold Time 400 ns */ -} TWI_SDAHOLD_t; - -/* Master Interrupt Level */ -typedef enum TWI_MASTER_INTLVL_enum -{ - TWI_MASTER_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ - TWI_MASTER_INTLVL_LO_gc = (0x01<<6), /* Low Level */ - TWI_MASTER_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ - TWI_MASTER_INTLVL_HI_gc = (0x03<<6), /* High Level */ -} TWI_MASTER_INTLVL_t; - -/* Inactive Timeout */ -typedef enum TWI_MASTER_TIMEOUT_enum -{ - TWI_MASTER_TIMEOUT_DISABLED_gc = (0x00<<2), /* Bus Timeout Disabled */ - TWI_MASTER_TIMEOUT_50US_gc = (0x01<<2), /* 50 Microseconds */ - TWI_MASTER_TIMEOUT_100US_gc = (0x02<<2), /* 100 Microseconds */ - TWI_MASTER_TIMEOUT_200US_gc = (0x03<<2), /* 200 Microseconds */ -} TWI_MASTER_TIMEOUT_t; - -/* Master Command */ -typedef enum TWI_MASTER_CMD_enum -{ - TWI_MASTER_CMD_NOACT_gc = (0x00<<0), /* No Action */ - TWI_MASTER_CMD_REPSTART_gc = (0x01<<0), /* Issue Repeated Start Condition */ - TWI_MASTER_CMD_RECVTRANS_gc = (0x02<<0), /* Receive or Transmit Data */ - TWI_MASTER_CMD_STOP_gc = (0x03<<0), /* Issue Stop Condition */ -} TWI_MASTER_CMD_t; - -/* Master Bus State */ -typedef enum TWI_MASTER_BUSSTATE_enum -{ - TWI_MASTER_BUSSTATE_UNKNOWN_gc = (0x00<<0), /* Unknown Bus State */ - TWI_MASTER_BUSSTATE_IDLE_gc = (0x01<<0), /* Bus is Idle */ - TWI_MASTER_BUSSTATE_OWNER_gc = (0x02<<0), /* This Module Controls The Bus */ - TWI_MASTER_BUSSTATE_BUSY_gc = (0x03<<0), /* The Bus is Busy */ -} TWI_MASTER_BUSSTATE_t; - -/* Slave Interrupt Level */ -typedef enum TWI_SLAVE_INTLVL_enum -{ - TWI_SLAVE_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ - TWI_SLAVE_INTLVL_LO_gc = (0x01<<6), /* Low Level */ - TWI_SLAVE_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ - TWI_SLAVE_INTLVL_HI_gc = (0x03<<6), /* High Level */ -} TWI_SLAVE_INTLVL_t; - -/* Slave Command */ -typedef enum TWI_SLAVE_CMD_enum -{ - TWI_SLAVE_CMD_NOACT_gc = (0x00<<0), /* No Action */ - TWI_SLAVE_CMD_COMPTRANS_gc = (0x02<<0), /* Used To Complete a Transaction */ - TWI_SLAVE_CMD_RESPONSE_gc = (0x03<<0), /* Used in Response to Address/Data Interrupt */ -} TWI_SLAVE_CMD_t; - - -/* --------------------------------------------------------------------------- -USB - USB --------------------------------------------------------------------------- -*/ - -/* USB Endpoint */ -typedef struct USB_EP_struct -{ - register8_t STATUS; /* Endpoint Status */ - register8_t CTRL; /* Endpoint Control */ - _WORDREGISTER(CNT); /* USB Endpoint Counter */ - _WORDREGISTER(DATAPTR); /* Data Pointer */ - _WORDREGISTER(AUXDATA); /* Auxiliary Data */ -} USB_EP_t; - - -/* Universal Serial Bus */ -typedef struct USB_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t STATUS; /* Status Register */ - register8_t ADDR; /* Address Register */ - register8_t FIFOWP; /* FIFO Write Pointer Register */ - register8_t FIFORP; /* FIFO Read Pointer Register */ - _WORDREGISTER(EPPTR); /* Endpoint Configuration Table Pointer */ - register8_t INTCTRLA; /* Interrupt Control Register A */ - register8_t INTCTRLB; /* Interrupt Control Register B */ - register8_t INTFLAGSACLR; /* Clear Interrupt Flag Register A */ - register8_t INTFLAGSASET; /* Set Interrupt Flag Register A */ - register8_t INTFLAGSBCLR; /* Clear Interrupt Flag Register B */ - register8_t INTFLAGSBSET; /* Set Interrupt Flag Register B */ - register8_t reserved_0x0E; - register8_t reserved_0x0F; - register8_t reserved_0x10; - register8_t reserved_0x11; - register8_t reserved_0x12; - register8_t reserved_0x13; - register8_t reserved_0x14; - register8_t reserved_0x15; - register8_t reserved_0x16; - register8_t reserved_0x17; - register8_t reserved_0x18; - register8_t reserved_0x19; - register8_t reserved_0x1A; - register8_t reserved_0x1B; - register8_t reserved_0x1C; - register8_t reserved_0x1D; - register8_t reserved_0x1E; - register8_t reserved_0x1F; - register8_t reserved_0x20; - register8_t reserved_0x21; - register8_t reserved_0x22; - register8_t reserved_0x23; - register8_t reserved_0x24; - register8_t reserved_0x25; - register8_t reserved_0x26; - register8_t reserved_0x27; - register8_t reserved_0x28; - register8_t reserved_0x29; - register8_t reserved_0x2A; - register8_t reserved_0x2B; - register8_t reserved_0x2C; - register8_t reserved_0x2D; - register8_t reserved_0x2E; - register8_t reserved_0x2F; - register8_t reserved_0x30; - register8_t reserved_0x31; - register8_t reserved_0x32; - register8_t reserved_0x33; - register8_t reserved_0x34; - register8_t reserved_0x35; - register8_t reserved_0x36; - register8_t reserved_0x37; - register8_t reserved_0x38; - register8_t reserved_0x39; - register8_t CAL0; /* Calibration Byte 0 */ - register8_t CAL1; /* Calibration Byte 1 */ -} USB_t; - - -/* USB Endpoint Table */ -typedef struct USB_EP_TABLE_struct -{ - USB_EP_t EP0OUT; /* Endpoint 0 */ - USB_EP_t EP0IN; /* Endpoint 0 */ - USB_EP_t EP1OUT; /* Endpoint 1 */ - USB_EP_t EP1IN; /* Endpoint 1 */ - USB_EP_t EP2OUT; /* Endpoint 2 */ - USB_EP_t EP2IN; /* Endpoint 2 */ - USB_EP_t EP3OUT; /* Endpoint 3 */ - USB_EP_t EP3IN; /* Endpoint 3 */ - USB_EP_t EP4OUT; /* Endpoint 4 */ - USB_EP_t EP4IN; /* Endpoint 4 */ - USB_EP_t EP5OUT; /* Endpoint 5 */ - USB_EP_t EP5IN; /* Endpoint 5 */ - USB_EP_t EP6OUT; /* Endpoint 6 */ - USB_EP_t EP6IN; /* Endpoint 6 */ - USB_EP_t EP7OUT; /* Endpoint 7 */ - USB_EP_t EP7IN; /* Endpoint 7 */ - USB_EP_t EP8OUT; /* Endpoint 8 */ - USB_EP_t EP8IN; /* Endpoint 8 */ - USB_EP_t EP9OUT; /* Endpoint 9 */ - USB_EP_t EP9IN; /* Endpoint 9 */ - USB_EP_t EP10OUT; /* Endpoint 10 */ - USB_EP_t EP10IN; /* Endpoint 10 */ - USB_EP_t EP11OUT; /* Endpoint 11 */ - USB_EP_t EP11IN; /* Endpoint 11 */ - USB_EP_t EP12OUT; /* Endpoint 12 */ - USB_EP_t EP12IN; /* Endpoint 12 */ - USB_EP_t EP13OUT; /* Endpoint 13 */ - USB_EP_t EP13IN; /* Endpoint 13 */ - USB_EP_t EP14OUT; /* Endpoint 14 */ - USB_EP_t EP14IN; /* Endpoint 14 */ - USB_EP_t EP15OUT; /* Endpoint 15 */ - USB_EP_t EP15IN; /* Endpoint 15 */ - register8_t reserved_0x100; - register8_t reserved_0x101; - register8_t reserved_0x102; - register8_t reserved_0x103; - register8_t reserved_0x104; - register8_t reserved_0x105; - register8_t reserved_0x106; - register8_t reserved_0x107; - register8_t reserved_0x108; - register8_t reserved_0x109; - register8_t reserved_0x10A; - register8_t reserved_0x10B; - register8_t reserved_0x10C; - register8_t reserved_0x10D; - register8_t reserved_0x10E; - register8_t reserved_0x10F; - register8_t FRAMENUML; /* Frame Number Low Byte */ - register8_t FRAMENUMH; /* Frame Number High Byte */ -} USB_EP_TABLE_t; - -/* Interrupt level */ -typedef enum USB_INTLVL_enum -{ - USB_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ - USB_INTLVL_LO_gc = (0x01<<0), /* Low level */ - USB_INTLVL_MED_gc = (0x02<<0), /* Medium level */ - USB_INTLVL_HI_gc = (0x03<<0), /* High level */ -} USB_INTLVL_t; - -/* USB Endpoint Type */ -typedef enum USB_EP_TYPE_enum -{ - USB_EP_TYPE_DISABLE_gc = (0x00<<6), /* Endpoint Disabled */ - USB_EP_TYPE_CONTROL_gc = (0x01<<6), /* Control */ - USB_EP_TYPE_BULK_gc = (0x02<<6), /* Bulk/Interrupt */ - USB_EP_TYPE_ISOCHRONOUS_gc = (0x03<<6), /* Isochronous */ -} USB_EP_TYPE_t; - -/* USB Endpoint Buffersize */ -typedef enum USB_EP_BUFSIZE_enum -{ - USB_EP_BUFSIZE_8_gc = (0x00<<0), /* 8 bytes buffer size */ - USB_EP_BUFSIZE_16_gc = (0x01<<0), /* 16 bytes buffer size */ - USB_EP_BUFSIZE_32_gc = (0x02<<0), /* 32 bytes buffer size */ - USB_EP_BUFSIZE_64_gc = (0x03<<0), /* 64 bytes buffer size */ - USB_EP_BUFSIZE_128_gc = (0x04<<0), /* 128 bytes buffer size */ - USB_EP_BUFSIZE_256_gc = (0x05<<0), /* 256 bytes buffer size */ - USB_EP_BUFSIZE_512_gc = (0x06<<0), /* 512 bytes buffer size */ - USB_EP_BUFSIZE_1023_gc = (0x07<<0), /* 1023 bytes buffer size */ -} USB_EP_BUFSIZE_t; - - -/* --------------------------------------------------------------------------- -PORT - I/O Port Configuration --------------------------------------------------------------------------- -*/ - -/* I/O Ports */ -typedef struct PORT_struct -{ - register8_t DIR; /* I/O Port Data Direction */ - register8_t DIRSET; /* I/O Port Data Direction Set */ - register8_t DIRCLR; /* I/O Port Data Direction Clear */ - register8_t DIRTGL; /* I/O Port Data Direction Toggle */ - register8_t OUT; /* I/O Port Output */ - register8_t OUTSET; /* I/O Port Output Set */ - register8_t OUTCLR; /* I/O Port Output Clear */ - register8_t OUTTGL; /* I/O Port Output Toggle */ - register8_t IN; /* I/O port Input */ - register8_t INTCTRL; /* Interrupt Control Register */ - register8_t INT0MASK; /* Port Interrupt 0 Mask */ - register8_t INT1MASK; /* Port Interrupt 1 Mask */ - register8_t INTFLAGS; /* Interrupt Flag Register */ - register8_t reserved_0x0D; - register8_t REMAP; /* I/O Port Pin Remap Register */ - register8_t reserved_0x0F; - register8_t PIN0CTRL; /* Pin 0 Control Register */ - register8_t PIN1CTRL; /* Pin 1 Control Register */ - register8_t PIN2CTRL; /* Pin 2 Control Register */ - register8_t PIN3CTRL; /* Pin 3 Control Register */ - register8_t PIN4CTRL; /* Pin 4 Control Register */ - register8_t PIN5CTRL; /* Pin 5 Control Register */ - register8_t PIN6CTRL; /* Pin 6 Control Register */ - register8_t PIN7CTRL; /* Pin 7 Control Register */ -} PORT_t; - -/* Port Interrupt 0 Level */ -typedef enum PORT_INT0LVL_enum -{ - PORT_INT0LVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - PORT_INT0LVL_LO_gc = (0x01<<0), /* Low Level */ - PORT_INT0LVL_MED_gc = (0x02<<0), /* Medium Level */ - PORT_INT0LVL_HI_gc = (0x03<<0), /* High Level */ -} PORT_INT0LVL_t; - -/* Port Interrupt 1 Level */ -typedef enum PORT_INT1LVL_enum -{ - PORT_INT1LVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ - PORT_INT1LVL_LO_gc = (0x01<<2), /* Low Level */ - PORT_INT1LVL_MED_gc = (0x02<<2), /* Medium Level */ - PORT_INT1LVL_HI_gc = (0x03<<2), /* High Level */ -} PORT_INT1LVL_t; - -/* Output/Pull Configuration */ -typedef enum PORT_OPC_enum -{ - PORT_OPC_TOTEM_gc = (0x00<<3), /* Totempole */ - PORT_OPC_BUSKEEPER_gc = (0x01<<3), /* Totempole w/ Bus keeper on Input and Output */ - PORT_OPC_PULLDOWN_gc = (0x02<<3), /* Totempole w/ Pull-down on Input */ - PORT_OPC_PULLUP_gc = (0x03<<3), /* Totempole w/ Pull-up on Input */ - PORT_OPC_WIREDOR_gc = (0x04<<3), /* Wired OR */ - PORT_OPC_WIREDAND_gc = (0x05<<3), /* Wired AND */ - PORT_OPC_WIREDORPULL_gc = (0x06<<3), /* Wired OR w/ Pull-down */ - PORT_OPC_WIREDANDPULL_gc = (0x07<<3), /* Wired AND w/ Pull-up */ -} PORT_OPC_t; - -/* Input/Sense Configuration */ -typedef enum PORT_ISC_enum -{ - PORT_ISC_BOTHEDGES_gc = (0x00<<0), /* Sense Both Edges */ - PORT_ISC_RISING_gc = (0x01<<0), /* Sense Rising Edge */ - PORT_ISC_FALLING_gc = (0x02<<0), /* Sense Falling Edge */ - PORT_ISC_LEVEL_gc = (0x03<<0), /* Sense Level (Transparent For Events) */ - PORT_ISC_INPUT_DISABLE_gc = (0x07<<0), /* Disable Digital Input Buffer */ -} PORT_ISC_t; - - -/* --------------------------------------------------------------------------- -TC - 16-bit Timer/Counter With PWM --------------------------------------------------------------------------- -*/ - -/* 16-bit Timer/Counter 0 */ -typedef struct TC0_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t CTRLC; /* Control register C */ - register8_t CTRLD; /* Control Register D */ - register8_t CTRLE; /* Control Register E */ - register8_t reserved_0x05; - register8_t INTCTRLA; /* Interrupt Control Register A */ - register8_t INTCTRLB; /* Interrupt Control Register B */ - register8_t CTRLFCLR; /* Control Register F Clear */ - register8_t CTRLFSET; /* Control Register F Set */ - register8_t CTRLGCLR; /* Control Register G Clear */ - register8_t CTRLGSET; /* Control Register G Set */ - register8_t INTFLAGS; /* Interrupt Flag Register */ - register8_t reserved_0x0D; - register8_t reserved_0x0E; - register8_t TEMP; /* Temporary Register For 16-bit Access */ - register8_t reserved_0x10; - register8_t reserved_0x11; - register8_t reserved_0x12; - register8_t reserved_0x13; - register8_t reserved_0x14; - register8_t reserved_0x15; - register8_t reserved_0x16; - register8_t reserved_0x17; - register8_t reserved_0x18; - register8_t reserved_0x19; - register8_t reserved_0x1A; - register8_t reserved_0x1B; - register8_t reserved_0x1C; - register8_t reserved_0x1D; - register8_t reserved_0x1E; - register8_t reserved_0x1F; - _WORDREGISTER(CNT); /* Count */ - register8_t reserved_0x22; - register8_t reserved_0x23; - register8_t reserved_0x24; - register8_t reserved_0x25; - _WORDREGISTER(PER); /* Period */ - _WORDREGISTER(CCA); /* Compare or Capture A */ - _WORDREGISTER(CCB); /* Compare or Capture B */ - _WORDREGISTER(CCC); /* Compare or Capture C */ - _WORDREGISTER(CCD); /* Compare or Capture D */ - register8_t reserved_0x30; - register8_t reserved_0x31; - register8_t reserved_0x32; - register8_t reserved_0x33; - register8_t reserved_0x34; - register8_t reserved_0x35; - _WORDREGISTER(PERBUF); /* Period Buffer */ - _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ - _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ - _WORDREGISTER(CCCBUF); /* Compare Or Capture C Buffer */ - _WORDREGISTER(CCDBUF); /* Compare Or Capture D Buffer */ -} TC0_t; - - -/* 16-bit Timer/Counter 1 */ -typedef struct TC1_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t CTRLC; /* Control register C */ - register8_t CTRLD; /* Control Register D */ - register8_t CTRLE; /* Control Register E */ - register8_t reserved_0x05; - register8_t INTCTRLA; /* Interrupt Control Register A */ - register8_t INTCTRLB; /* Interrupt Control Register B */ - register8_t CTRLFCLR; /* Control Register F Clear */ - register8_t CTRLFSET; /* Control Register F Set */ - register8_t CTRLGCLR; /* Control Register G Clear */ - register8_t CTRLGSET; /* Control Register G Set */ - register8_t INTFLAGS; /* Interrupt Flag Register */ - register8_t reserved_0x0D; - register8_t reserved_0x0E; - register8_t TEMP; /* Temporary Register For 16-bit Access */ - register8_t reserved_0x10; - register8_t reserved_0x11; - register8_t reserved_0x12; - register8_t reserved_0x13; - register8_t reserved_0x14; - register8_t reserved_0x15; - register8_t reserved_0x16; - register8_t reserved_0x17; - register8_t reserved_0x18; - register8_t reserved_0x19; - register8_t reserved_0x1A; - register8_t reserved_0x1B; - register8_t reserved_0x1C; - register8_t reserved_0x1D; - register8_t reserved_0x1E; - register8_t reserved_0x1F; - _WORDREGISTER(CNT); /* Count */ - register8_t reserved_0x22; - register8_t reserved_0x23; - register8_t reserved_0x24; - register8_t reserved_0x25; - _WORDREGISTER(PER); /* Period */ - _WORDREGISTER(CCA); /* Compare or Capture A */ - _WORDREGISTER(CCB); /* Compare or Capture B */ - register8_t reserved_0x2C; - register8_t reserved_0x2D; - register8_t reserved_0x2E; - register8_t reserved_0x2F; - register8_t reserved_0x30; - register8_t reserved_0x31; - register8_t reserved_0x32; - register8_t reserved_0x33; - register8_t reserved_0x34; - register8_t reserved_0x35; - _WORDREGISTER(PERBUF); /* Period Buffer */ - _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ - _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ -} TC1_t; - -/* Clock Selection */ -typedef enum TC_CLKSEL_enum -{ - TC_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */ - TC_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */ - TC_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */ - TC_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */ - TC_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */ - TC_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */ - TC_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */ - TC_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */ - TC_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */ - TC_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */ - TC_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */ - TC_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */ -} TC_CLKSEL_t; - -/* Waveform Generation Mode */ -typedef enum TC_WGMODE_enum -{ - TC_WGMODE_NORMAL_gc = (0x00<<0), /* Normal Mode */ - TC_WGMODE_FRQ_gc = (0x01<<0), /* Frequency Generation Mode */ - TC_WGMODE_SINGLESLOPE_gc = (0x03<<0), /* Single Slope */ - TC_WGMODE_SS_gc = (0x03<<0), /* Single Slope */ - TC_WGMODE_DSTOP_gc = (0x05<<0), /* Dual Slope, Update on TOP */ - TC_WGMODE_DS_T_gc = (0x05<<0), /* Dual Slope, Update on TOP */ - TC_WGMODE_DSBOTH_gc = (0x06<<0), /* Dual Slope, Update on both TOP and BOTTOM */ - TC_WGMODE_DS_TB_gc = (0x06<<0), /* Dual Slope, Update on both TOP and BOTTOM */ - TC_WGMODE_DSBOTTOM_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */ - TC_WGMODE_DS_B_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */ -} TC_WGMODE_t; - -/* Byte Mode */ -typedef enum TC_BYTEM_enum -{ - TC_BYTEM_NORMAL_gc = (0x00<<0), /* 16-bit mode */ - TC_BYTEM_BYTEMODE_gc = (0x01<<0), /* Timer/Counter operating in byte mode only */ - TC_BYTEM_SPLITMODE_gc = (0x02<<0), /* Timer/Counter split into two 8-bit Counters */ -} TC_BYTEM_t; - -/* Event Action */ -typedef enum TC_EVACT_enum -{ - TC_EVACT_OFF_gc = (0x00<<5), /* No Event Action */ - TC_EVACT_CAPT_gc = (0x01<<5), /* Input Capture */ - TC_EVACT_UPDOWN_gc = (0x02<<5), /* Externally Controlled Up/Down Count */ - TC_EVACT_QDEC_gc = (0x03<<5), /* Quadrature Decode */ - TC_EVACT_RESTART_gc = (0x04<<5), /* Restart */ - TC_EVACT_FRQ_gc = (0x05<<5), /* Frequency Capture */ - TC_EVACT_PW_gc = (0x06<<5), /* Pulse-width Capture */ -} TC_EVACT_t; - -/* Event Selection */ -typedef enum TC_EVSEL_enum -{ - TC_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ - TC_EVSEL_CH0_gc = (0x08<<0), /* Event Channel 0 */ - TC_EVSEL_CH1_gc = (0x09<<0), /* Event Channel 1 */ - TC_EVSEL_CH2_gc = (0x0A<<0), /* Event Channel 2 */ - TC_EVSEL_CH3_gc = (0x0B<<0), /* Event Channel 3 */ -} TC_EVSEL_t; - -/* Error Interrupt Level */ -typedef enum TC_ERRINTLVL_enum -{ - TC_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ - TC_ERRINTLVL_LO_gc = (0x01<<2), /* Low Level */ - TC_ERRINTLVL_MED_gc = (0x02<<2), /* Medium Level */ - TC_ERRINTLVL_HI_gc = (0x03<<2), /* High Level */ -} TC_ERRINTLVL_t; - -/* Overflow Interrupt Level */ -typedef enum TC_OVFINTLVL_enum -{ - TC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - TC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ - TC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ - TC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ -} TC_OVFINTLVL_t; - -/* Compare or Capture D Interrupt Level */ -typedef enum TC_CCDINTLVL_enum -{ - TC_CCDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ - TC_CCDINTLVL_LO_gc = (0x01<<6), /* Low Level */ - TC_CCDINTLVL_MED_gc = (0x02<<6), /* Medium Level */ - TC_CCDINTLVL_HI_gc = (0x03<<6), /* High Level */ -} TC_CCDINTLVL_t; - -/* Compare or Capture C Interrupt Level */ -typedef enum TC_CCCINTLVL_enum -{ - TC_CCCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ - TC_CCCINTLVL_LO_gc = (0x01<<4), /* Low Level */ - TC_CCCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ - TC_CCCINTLVL_HI_gc = (0x03<<4), /* High Level */ -} TC_CCCINTLVL_t; - -/* Compare or Capture B Interrupt Level */ -typedef enum TC_CCBINTLVL_enum -{ - TC_CCBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ - TC_CCBINTLVL_LO_gc = (0x01<<2), /* Low Level */ - TC_CCBINTLVL_MED_gc = (0x02<<2), /* Medium Level */ - TC_CCBINTLVL_HI_gc = (0x03<<2), /* High Level */ -} TC_CCBINTLVL_t; - -/* Compare or Capture A Interrupt Level */ -typedef enum TC_CCAINTLVL_enum -{ - TC_CCAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - TC_CCAINTLVL_LO_gc = (0x01<<0), /* Low Level */ - TC_CCAINTLVL_MED_gc = (0x02<<0), /* Medium Level */ - TC_CCAINTLVL_HI_gc = (0x03<<0), /* High Level */ -} TC_CCAINTLVL_t; - -/* Timer/Counter Command */ -typedef enum TC_CMD_enum -{ - TC_CMD_NONE_gc = (0x00<<2), /* No Command */ - TC_CMD_UPDATE_gc = (0x01<<2), /* Force Update */ - TC_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ - TC_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ -} TC_CMD_t; - - -/* --------------------------------------------------------------------------- -AWEX - Timer/Counter Advanced Waveform Extension --------------------------------------------------------------------------- -*/ - -/* Advanced Waveform Extension */ -typedef struct AWEX_struct -{ - register8_t CTRL; /* Control Register */ - register8_t reserved_0x01; - register8_t FDEMASK; /* Fault Detection Event Mask */ - register8_t FDCTRL; /* Fault Detection Control Register */ - register8_t STATUS; /* Status Register */ - register8_t STATUSSET; /* Status Set Register */ - register8_t DTBOTH; /* Dead Time Both Sides */ - register8_t DTBOTHBUF; /* Dead Time Both Sides Buffer */ - register8_t DTLS; /* Dead Time Low Side */ - register8_t DTHS; /* Dead Time High Side */ - register8_t DTLSBUF; /* Dead Time Low Side Buffer */ - register8_t DTHSBUF; /* Dead Time High Side Buffer */ - register8_t OUTOVEN; /* Output Override Enable */ -} AWEX_t; - -/* Fault Detect Action */ -typedef enum AWEX_FDACT_enum -{ - AWEX_FDACT_NONE_gc = (0x00<<0), /* No Fault Protection */ - AWEX_FDACT_CLEAROE_gc = (0x01<<0), /* Clear Output Enable Bits */ - AWEX_FDACT_CLEARDIR_gc = (0x03<<0), /* Clear I/O Port Direction Bits */ -} AWEX_FDACT_t; - - -/* --------------------------------------------------------------------------- -HIRES - Timer/Counter High-Resolution Extension --------------------------------------------------------------------------- -*/ - -/* High-Resolution Extension */ -typedef struct HIRES_struct -{ - register8_t CTRLA; /* Control Register */ -} HIRES_t; - -/* High Resolution Enable */ -typedef enum HIRES_HREN_enum -{ - HIRES_HREN_NONE_gc = (0x00<<0), /* No Fault Protection */ - HIRES_HREN_TC0_gc = (0x01<<0), /* Enable High Resolution on Timer/Counter 0 */ - HIRES_HREN_TC1_gc = (0x02<<0), /* Enable High Resolution on Timer/Counter 1 */ - HIRES_HREN_BOTH_gc = (0x03<<0), /* Enable High Resolution both Timer/Counters */ -} HIRES_HREN_t; - - -/* --------------------------------------------------------------------------- -USART - Universal Asynchronous Receiver-Transmitter --------------------------------------------------------------------------- -*/ - -/* Universal Synchronous/Asynchronous Receiver/Transmitter */ -typedef struct USART_struct -{ - register8_t DATA; /* Data Register */ - register8_t STATUS; /* Status Register */ - register8_t reserved_0x02; - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t CTRLC; /* Control Register C */ - register8_t BAUDCTRLA; /* Baud Rate Control Register A */ - register8_t BAUDCTRLB; /* Baud Rate Control Register B */ -} USART_t; - -/* Receive Complete Interrupt level */ -typedef enum USART_RXCINTLVL_enum -{ - USART_RXCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ - USART_RXCINTLVL_LO_gc = (0x01<<4), /* Low Level */ - USART_RXCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ - USART_RXCINTLVL_HI_gc = (0x03<<4), /* High Level */ -} USART_RXCINTLVL_t; - -/* Transmit Complete Interrupt level */ -typedef enum USART_TXCINTLVL_enum -{ - USART_TXCINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ - USART_TXCINTLVL_LO_gc = (0x01<<2), /* Low Level */ - USART_TXCINTLVL_MED_gc = (0x02<<2), /* Medium Level */ - USART_TXCINTLVL_HI_gc = (0x03<<2), /* High Level */ -} USART_TXCINTLVL_t; - -/* Data Register Empty Interrupt level */ -typedef enum USART_DREINTLVL_enum -{ - USART_DREINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - USART_DREINTLVL_LO_gc = (0x01<<0), /* Low Level */ - USART_DREINTLVL_MED_gc = (0x02<<0), /* Medium Level */ - USART_DREINTLVL_HI_gc = (0x03<<0), /* High Level */ -} USART_DREINTLVL_t; - -/* Character Size */ -typedef enum USART_CHSIZE_enum -{ - USART_CHSIZE_5BIT_gc = (0x00<<0), /* Character size: 5 bit */ - USART_CHSIZE_6BIT_gc = (0x01<<0), /* Character size: 6 bit */ - USART_CHSIZE_7BIT_gc = (0x02<<0), /* Character size: 7 bit */ - USART_CHSIZE_8BIT_gc = (0x03<<0), /* Character size: 8 bit */ - USART_CHSIZE_9BIT_gc = (0x07<<0), /* Character size: 9 bit */ -} USART_CHSIZE_t; - -/* Communication Mode */ -typedef enum USART_CMODE_enum -{ - USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6), /* Asynchronous Mode */ - USART_CMODE_SYNCHRONOUS_gc = (0x01<<6), /* Synchronous Mode */ - USART_CMODE_IRDA_gc = (0x02<<6), /* IrDA Mode */ - USART_CMODE_MSPI_gc = (0x03<<6), /* Master SPI Mode */ -} USART_CMODE_t; - -/* Parity Mode */ -typedef enum USART_PMODE_enum -{ - USART_PMODE_DISABLED_gc = (0x00<<4), /* No Parity */ - USART_PMODE_EVEN_gc = (0x02<<4), /* Even Parity */ - USART_PMODE_ODD_gc = (0x03<<4), /* Odd Parity */ -} USART_PMODE_t; - - -/* --------------------------------------------------------------------------- -SPI - Serial Peripheral Interface --------------------------------------------------------------------------- -*/ - -/* Serial Peripheral Interface */ -typedef struct SPI_struct -{ - register8_t CTRL; /* Control Register */ - register8_t INTCTRL; /* Interrupt Control Register */ - register8_t STATUS; /* Status Register */ - register8_t DATA; /* Data Register */ -} SPI_t; - -/* SPI Mode */ -typedef enum SPI_MODE_enum -{ - SPI_MODE_0_gc = (0x00<<2), /* SPI Mode 0 */ - SPI_MODE_1_gc = (0x01<<2), /* SPI Mode 1 */ - SPI_MODE_2_gc = (0x02<<2), /* SPI Mode 2 */ - SPI_MODE_3_gc = (0x03<<2), /* SPI Mode 3 */ -} SPI_MODE_t; - -/* Prescaler setting */ -typedef enum SPI_PRESCALER_enum -{ - SPI_PRESCALER_DIV4_gc = (0x00<<0), /* System Clock / 4 */ - SPI_PRESCALER_DIV16_gc = (0x01<<0), /* System Clock / 16 */ - SPI_PRESCALER_DIV64_gc = (0x02<<0), /* System Clock / 64 */ - SPI_PRESCALER_DIV128_gc = (0x03<<0), /* System Clock / 128 */ -} SPI_PRESCALER_t; - -/* Interrupt level */ -typedef enum SPI_INTLVL_enum -{ - SPI_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - SPI_INTLVL_LO_gc = (0x01<<0), /* Low Level */ - SPI_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ - SPI_INTLVL_HI_gc = (0x03<<0), /* High Level */ -} SPI_INTLVL_t; - - -/* --------------------------------------------------------------------------- -IRCOM - IR Communication Module --------------------------------------------------------------------------- -*/ - -/* IR Communication Module */ -typedef struct IRCOM_struct -{ - register8_t CTRL; /* Control Register */ - register8_t TXPLCTRL; /* IrDA Transmitter Pulse Length Control Register */ - register8_t RXPLCTRL; /* IrDA Receiver Pulse Length Control Register */ -} IRCOM_t; - -/* Event channel selection */ -typedef enum IRDA_EVSEL_enum -{ - IRDA_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ - IRDA_EVSEL_0_gc = (0x08<<0), /* Event Channel 0 */ - IRDA_EVSEL_1_gc = (0x09<<0), /* Event Channel 1 */ - IRDA_EVSEL_2_gc = (0x0A<<0), /* Event Channel 2 */ - IRDA_EVSEL_3_gc = (0x0B<<0), /* Event Channel 3 */ -} IRDA_EVSEL_t; - - -/* --------------------------------------------------------------------------- -LCD - LCD Controller --------------------------------------------------------------------------- -*/ - -/* LCD Controller */ -typedef struct LCD_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t CTRLC; /* Control Register C */ - register8_t INTCTRL; /* Interrupt Enable Register */ - register8_t INTFLAG; /* Interrupt Flag Register */ - register8_t CTRLD; /* Control Register D */ - register8_t CTRLE; /* Control Register E */ - register8_t CTRLF; /* Control Register F */ - register8_t CTRLG; /* Control Register G */ - register8_t CTRLH; /* Control Register H */ - register8_t reserved_0x0A; - register8_t reserved_0x0B; - register8_t reserved_0x0C; - register8_t reserved_0x0D; - register8_t reserved_0x0E; - register8_t reserved_0x0F; - register8_t DATA0; /* LCD Data Register 0 */ - register8_t DATA1; /* LCD Data Register 1 */ - register8_t DATA2; /* LCD Data Register 2 */ - register8_t DATA3; /* LCD Data Register 3 */ - register8_t DATA4; /* LCD Data Register 4 */ - register8_t DATA5; /* LCD Data Register 5 */ - register8_t DATA6; /* LCD Data Register 6 */ - register8_t DATA7; /* LCD Data Register 7 */ - register8_t DATA8; /* LCD Data Register 8 */ - register8_t DATA9; /* LCD Data Register 9 */ - register8_t DATA10; /* LCD Data Register 10 */ - register8_t DATA11; /* LCD Data Register 11 */ - register8_t DATA12; /* LCD Data Register 12 */ - register8_t DATA13; /* LCD Data Register 13 */ - register8_t DATA14; /* LCD Data Register 14 */ - register8_t DATA15; /* LCD Data Register 15 */ - register8_t DATA16; /* LCD Data Register 16 */ - register8_t DATA17; /* LCD Data Register 17 */ - register8_t DATA18; /* LCD Data Register 18 */ - register8_t DATA19; /* LCD Data Register 19 */ -} LCD_t; - -/* LCD Blink Rate */ -typedef enum LCD_BLINKRATE_enum -{ - LCD_BLINKRATE_4Hz_gc = (0x00<<0), /* 4Hz Blink Rate */ - LCD_BLINKRATE_2Hz_gc = (0x01<<0), /* 2Hz Blink Rate */ - LCD_BLINKRATE_1Hz_gc = (0x02<<0), /* 1Hz Blink Rate */ - LCD_BLINKRATE_0Hz5_gc = (0x03<<0), /* 0.5Hz Blink Rate */ -} LCD_BLINKRATE_t; - -/* LCD Clock Divide */ -typedef enum LCD_CLKDIV_enum -{ - LCD_CLKDIV_DivBy1_gc = (0x00<<4), /* frame rate of 256 Hz */ - LCD_CLKDIV_DivBy2_gc = (0x01<<4), /* frame rate of 128 Hz */ - LCD_CLKDIV_DivBy3_gc = (0x02<<4), /* frame rate of 83.5 Hz */ - LCD_CLKDIV_DivBy4_gc = (0x03<<4), /* frame rate of 64 Hz */ - LCD_CLKDIV_DivBy5_gc = (0x04<<4), /* frame rate of 51.2 Hz */ - LCD_CLKDIV_DivBy6_gc = (0x05<<4), /* frame rate of 42.7 Hz */ - LCD_CLKDIV_DivBy7_gc = (0x06<<4), /* frame rate of 36.6 Hz */ - LCD_CLKDIV_DivBy8_gc = (0x07<<4), /* frame rate of 32 Hz */ -} LCD_CLKDIV_t; - -/* Duty Select */ -typedef enum LCD_DUTY_enum -{ - LCD_DUTY_1_4_gc = (0x00<<0), /* Duty=1/4, Bias=1/3, COM0:3 */ - LCD_DUTY_Static_gc = (0x01<<0), /* Duty=Static, Bias=Static, COM0 */ - LCD_DUTY_1_2_gc = (0x02<<0), /* Duty=1/2, Bias=1/3, COM0:1 */ - LCD_DUTY_1_3_gc = (0x03<<0), /* Duty=1/3, Bias=1/3, COM0:2 */ -} LCD_DUTY_t; - -/* LCD Prescaler Select */ -typedef enum LCD_PRESC_enum -{ - LCD_PRESC_8_gc = (0x00<<7), /* clk_lcd/8 */ - LCD_PRESC_16_gc = (0x01<<7), /* clk_lcd/16 */ -} LCD_PRESC_t; - -/* Type of Digit */ -typedef enum LCD_TDG_enum -{ - LCD_TDG_7S_3C_gc = (0x00<<6), /* 7-segment with 3 COMs */ - LCD_TDG_7S_4C_gc = (0x01<<6), /* 7-segment with 4 COMs */ - LCD_TDG_14S_4C_gc = (0x02<<6), /* 14-segment with 4 COMs */ - LCD_TDG_16S_3C_gc = (0x03<<6), /* 16-segment with 3 COMs */ -} LCD_TDG_t; - - -/* --------------------------------------------------------------------------- -FUSE - Fuses and Lockbits --------------------------------------------------------------------------- -*/ - -/* Fuses */ -typedef struct NVM_FUSES_struct -{ - register8_t FUSEBYTE0; /* JTAG User ID */ - register8_t FUSEBYTE1; /* Watchdog Configuration */ - register8_t FUSEBYTE2; /* Reset Configuration */ - register8_t reserved_0x03; - register8_t FUSEBYTE4; /* Start-up Configuration */ - register8_t FUSEBYTE5; /* EESAVE and BOD Level */ -} NVM_FUSES_t; - -/* Boot Loader Section Reset Vector */ -typedef enum BOOTRST_enum -{ - BOOTRST_BOOTLDR_gc = (0x00<<6), /* Boot Loader Reset */ - BOOTRST_APPLICATION_gc = (0x01<<6), /* Application Reset */ -} BOOTRST_t; - -/* Timer Oscillator pin location */ -typedef enum TOSCSEL_enum -{ - TOSCSEL_ALTERNATE_gc = (0x00<<5), /* TOSC1 / TOSC2 on separate pins */ - TOSCSEL_XTAL_gc = (0x01<<5), /* TOSC1 / TOSC2 shared with XTAL1 / XTAL2 */ -} TOSCSEL_t; - -/* BOD operation */ -typedef enum BOD_enum -{ - BOD_SAMPLED_gc = (0x01<<0), /* BOD enabled in sampled mode */ - BOD_CONTINUOUS_gc = (0x02<<0), /* BOD enabled continuously */ - BOD_DISABLED_gc = (0x03<<0), /* BOD Disabled */ -} BOD_t; - -/* BOD operation */ -typedef enum BODACT_enum -{ - BODACT_SAMPLED_gc = (0x01<<4), /* BOD enabled in sampled mode */ - BODACT_CONTINUOUS_gc = (0x02<<4), /* BOD enabled continuously */ - BODACT_DISABLED_gc = (0x03<<4), /* BOD Disabled */ -} BODACT_t; - -/* Watchdog (Window) Timeout Period */ -typedef enum WD_enum -{ - WD_8CLK_gc = (0x00<<4), /* 8 cycles (8ms @ 3.3V) */ - WD_16CLK_gc = (0x01<<4), /* 16 cycles (16ms @ 3.3V) */ - WD_32CLK_gc = (0x02<<4), /* 32 cycles (32ms @ 3.3V) */ - WD_64CLK_gc = (0x03<<4), /* 64 cycles (64ms @ 3.3V) */ - WD_128CLK_gc = (0x04<<4), /* 128 cycles (0.125s @ 3.3V) */ - WD_256CLK_gc = (0x05<<4), /* 256 cycles (0.25s @ 3.3V) */ - WD_512CLK_gc = (0x06<<4), /* 512 cycles (0.5s @ 3.3V) */ - WD_1KCLK_gc = (0x07<<4), /* 1K cycles (1s @ 3.3V) */ - WD_2KCLK_gc = (0x08<<4), /* 2K cycles (2s @ 3.3V) */ - WD_4KCLK_gc = (0x09<<4), /* 4K cycles (4s @ 3.3V) */ - WD_8KCLK_gc = (0x0A<<4), /* 8K cycles (8s @ 3.3V) */ -} WD_t; - -/* Watchdog (Window) Timeout Period */ -typedef enum WDP_enum -{ - WDP_8CLK_gc = (0x00<<0), /* 8 cycles (8ms @ 3.3V) */ - WDP_16CLK_gc = (0x01<<0), /* 16 cycles (16ms @ 3.3V) */ - WDP_32CLK_gc = (0x02<<0), /* 32 cycles (32ms @ 3.3V) */ - WDP_64CLK_gc = (0x03<<0), /* 64 cycles (64ms @ 3.3V) */ - WDP_128CLK_gc = (0x04<<0), /* 128 cycles (0.125s @ 3.3V) */ - WDP_256CLK_gc = (0x05<<0), /* 256 cycles (0.25s @ 3.3V) */ - WDP_512CLK_gc = (0x06<<0), /* 512 cycles (0.5s @ 3.3V) */ - WDP_1KCLK_gc = (0x07<<0), /* 1K cycles (1s @ 3.3V) */ - WDP_2KCLK_gc = (0x08<<0), /* 2K cycles (2s @ 3.3V) */ - WDP_4KCLK_gc = (0x09<<0), /* 4K cycles (4s @ 3.3V) */ - WDP_8KCLK_gc = (0x0A<<0), /* 8K cycles (8s @ 3.3V) */ -} WDP_t; - -/* Start-up Time */ -typedef enum SUT_enum -{ - SUT_0MS_gc = (0x03<<2), /* 0 ms */ - SUT_4MS_gc = (0x01<<2), /* 4 ms */ - SUT_64MS_gc = (0x00<<2), /* 64 ms */ -} SUT_t; - -/* Brownout Detection Voltage Level */ -typedef enum BODLVL_enum -{ - BODLVL_1V6_gc = (0x07<<0), /* 1.6 V */ - BODLVL_1V8_gc = (0x06<<0), /* 1.8 V */ - BODLVL_2V0_gc = (0x05<<0), /* 2.0 V */ - BODLVL_2V2_gc = (0x04<<0), /* 2.2 V */ - BODLVL_2V4_gc = (0x03<<0), /* 2.4 V */ - BODLVL_2V6_gc = (0x02<<0), /* 2.6 V */ - BODLVL_2V8_gc = (0x01<<0), /* 2.8 V */ - BODLVL_3V0_gc = (0x00<<0), /* 3.0 V */ -} BODLVL_t; - - -/* --------------------------------------------------------------------------- -LOCKBIT - Fuses and Lockbits --------------------------------------------------------------------------- -*/ - -/* Lock Bits */ -typedef struct NVM_LOCKBITS_struct -{ - register8_t LOCK_BITS; /* Lock Bits (Changed from LOCKBITS to avoid avr-libc collision) */ -} NVM_LOCKBITS_t; - -/* Boot lock bits - boot setcion */ -typedef enum FUSE_BLBB_enum -{ - FUSE_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ - FUSE_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ - FUSE_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ - FUSE_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ -} FUSE_BLBB_t; - -/* Boot lock bits - application section */ -typedef enum FUSE_BLBA_enum -{ - FUSE_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ - FUSE_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ - FUSE_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ - FUSE_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ -} FUSE_BLBA_t; - -/* Boot lock bits - application table section */ -typedef enum FUSE_BLBAT_enum -{ - FUSE_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ - FUSE_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ - FUSE_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ - FUSE_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ -} FUSE_BLBAT_t; - -/* Lock bits */ -typedef enum FUSE_LB_enum -{ - FUSE_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ - FUSE_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ - FUSE_LB_NOLOCK_gc = (0x03<<0), /* No locks */ -} FUSE_LB_t; - - -/* --------------------------------------------------------------------------- -SIGROW - Signature Row --------------------------------------------------------------------------- -*/ - -/* Production Signatures */ -typedef struct NVM_PROD_SIGNATURES_struct -{ - register8_t RCOSC2M; /* RCOSC 2 MHz Calibration Value B */ - register8_t RCOSC2MA; /* RCOSC 2 MHz Calibration Value A */ - register8_t RCOSC32K; /* RCOSC 32.768 kHz Calibration Value */ - register8_t RCOSC32M; /* RCOSC 32 MHz Calibration Value B */ - register8_t RCOSC32MA; /* RCOSC 32 MHz Calibration Value A */ - register8_t reserved_0x05; - register8_t reserved_0x06; - register8_t reserved_0x07; - register8_t LOTNUM0; /* Lot Number Byte 0, ASCII */ - register8_t LOTNUM1; /* Lot Number Byte 1, ASCII */ - register8_t LOTNUM2; /* Lot Number Byte 2, ASCII */ - register8_t LOTNUM3; /* Lot Number Byte 3, ASCII */ - register8_t LOTNUM4; /* Lot Number Byte 4, ASCII */ - register8_t LOTNUM5; /* Lot Number Byte 5, ASCII */ - register8_t reserved_0x0E; - register8_t reserved_0x0F; - register8_t WAFNUM; /* Wafer Number */ - register8_t reserved_0x11; - register8_t COORDX0; /* Wafer Coordinate X Byte 0 */ - register8_t COORDX1; /* Wafer Coordinate X Byte 1 */ - register8_t COORDY0; /* Wafer Coordinate Y Byte 0 */ - register8_t COORDY1; /* Wafer Coordinate Y Byte 1 */ - register8_t reserved_0x16; - register8_t reserved_0x17; - register8_t reserved_0x18; - register8_t reserved_0x19; - register8_t USBCAL0; /* USB Calibration Byte 0 */ - register8_t USBCAL1; /* USB Calibration Byte 1 */ - register8_t USBRCOSC; /* USB RCOSC Calibration Value B */ - register8_t USBRCOSCA; /* USB RCOSC Calibration Value A */ - register8_t reserved_0x1E; - register8_t reserved_0x1F; - register8_t ADCACAL0; /* ADCA Calibration Byte 0 */ - register8_t ADCACAL1; /* ADCA Calibration Byte 1 */ - register8_t reserved_0x22; - register8_t reserved_0x23; - register8_t ADCBCAL0; /* ADCB Calibration Byte 0 */ - register8_t ADCBCAL1; /* ADCB Calibration Byte 1 */ - register8_t reserved_0x26; - register8_t reserved_0x27; - register8_t reserved_0x28; - register8_t reserved_0x29; - register8_t reserved_0x2A; - register8_t reserved_0x2B; - register8_t reserved_0x2C; - register8_t reserved_0x2D; - register8_t TEMPSENSE0; /* Temperature Sensor Calibration Byte 0 */ - register8_t TEMPSENSE1; /* Temperature Sensor Calibration Byte 1 */ - register8_t reserved_0x30; - register8_t reserved_0x31; - register8_t reserved_0x32; - register8_t reserved_0x33; - register8_t reserved_0x34; - register8_t reserved_0x35; - register8_t reserved_0x36; - register8_t reserved_0x37; - register8_t reserved_0x38; - register8_t reserved_0x39; - register8_t reserved_0x3A; - register8_t reserved_0x3B; - register8_t reserved_0x3C; - register8_t reserved_0x3D; - register8_t reserved_0x3E; - register8_t reserved_0x3F; - register8_t reserved_0x40; - register8_t reserved_0x41; - register8_t reserved_0x42; - register8_t reserved_0x43; - register8_t reserved_0x44; - register8_t reserved_0x45; - register8_t reserved_0x46; - register8_t reserved_0x47; -} NVM_PROD_SIGNATURES_t; - -/* -========================================================================== -IO Module Instances. Mapped to memory. -========================================================================== -*/ - -#define VPORT0 (*(VPORT_t *) 0x0010) /* Virtual Port */ -#define VPORT1 (*(VPORT_t *) 0x0014) /* Virtual Port */ -#define VPORT2 (*(VPORT_t *) 0x0018) /* Virtual Port */ -#define VPORT3 (*(VPORT_t *) 0x001C) /* Virtual Port */ -#define OCD (*(OCD_t *) 0x002E) /* On-Chip Debug System */ -#define CLK (*(CLK_t *) 0x0040) /* Clock System */ -#define SLEEP (*(SLEEP_t *) 0x0048) /* Sleep Controller */ -#define OSC (*(OSC_t *) 0x0050) /* Oscillator */ -#define DFLLRC32M (*(DFLL_t *) 0x0060) /* DFLL */ -#define DFLLRC2M (*(DFLL_t *) 0x0068) /* DFLL */ -#define PR (*(PR_t *) 0x0070) /* Power Reduction */ -#define RST (*(RST_t *) 0x0078) /* Reset */ -#define WDT (*(WDT_t *) 0x0080) /* Watch-Dog Timer */ -#define MCU (*(MCU_t *) 0x0090) /* MCU Control */ -#define PMIC (*(PMIC_t *) 0x00A0) /* Programmable Multi-level Interrupt Controller */ -#define PORTCFG (*(PORTCFG_t *) 0x00B0) /* I/O port Configuration */ -#define AES (*(AES_t *) 0x00C0) /* AES Module */ -#define CRC (*(CRC_t *) 0x00D0) /* Cyclic Redundancy Checker */ -#define DMA (*(DMA_t *) 0x0100) /* DMA Controller */ -#define EVSYS (*(EVSYS_t *) 0x0180) /* Event System */ -#define NVM (*(NVM_t *) 0x01C0) /* Non-volatile Memory Controller */ -#define ADCA (*(ADC_t *) 0x0200) /* Analog-to-Digital Converter */ -#define ADCB (*(ADC_t *) 0x0240) /* Analog-to-Digital Converter */ -#define ACA (*(AC_t *) 0x0380) /* Analog Comparator */ -#define ACB (*(AC_t *) 0x0390) /* Analog Comparator */ -#define RTC (*(RTC_t *) 0x0400) /* Real-Time Counter */ -#define TWIC (*(TWI_t *) 0x0480) /* Two-Wire Interface */ -#define USB (*(USB_t *) 0x04C0) /* Universal Serial Bus */ -#define PORTA (*(PORT_t *) 0x0600) /* I/O Ports */ -#define PORTB (*(PORT_t *) 0x0620) /* I/O Ports */ -#define PORTC (*(PORT_t *) 0x0640) /* I/O Ports */ -#define PORTD (*(PORT_t *) 0x0660) /* I/O Ports */ -#define PORTE (*(PORT_t *) 0x0680) /* I/O Ports */ -#define PORTG (*(PORT_t *) 0x06C0) /* I/O Ports */ -#define PORTM (*(PORT_t *) 0x0760) /* I/O Ports */ -#define PORTR (*(PORT_t *) 0x07E0) /* I/O Ports */ -#define TCC0 (*(TC0_t *) 0x0800) /* 16-bit Timer/Counter 0 */ -#define TCC1 (*(TC1_t *) 0x0840) /* 16-bit Timer/Counter 1 */ -#define AWEXC (*(AWEX_t *) 0x0880) /* Advanced Waveform Extension */ -#define HIRESC (*(HIRES_t *) 0x0890) /* High-Resolution Extension */ -#define USARTC0 (*(USART_t *) 0x08A0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ -#define SPIC (*(SPI_t *) 0x08C0) /* Serial Peripheral Interface */ -#define IRCOM (*(IRCOM_t *) 0x08F8) /* IR Communication Module */ -#define TCE0 (*(TC0_t *) 0x0A00) /* 16-bit Timer/Counter 0 */ -#define USARTE0 (*(USART_t *) 0x0AA0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ -#define LCD (*(LCD_t *) 0x0D00) /* LCD Controller */ - - -#endif /* !defined (__ASSEMBLER__) */ - - -/* ========== Flattened fully qualified IO register names ========== */ - -/* GPIO - General Purpose IO Registers */ -#define GPIO_GPIOR0 _SFR_MEM8(0x0000) -#define GPIO_GPIOR1 _SFR_MEM8(0x0001) -#define GPIO_GPIOR2 _SFR_MEM8(0x0002) -#define GPIO_GPIOR3 _SFR_MEM8(0x0003) - -/* Deprecated */ -#define GPIO_GPIO0 _SFR_MEM8(0x0000) -#define GPIO_GPIO1 _SFR_MEM8(0x0001) -#define GPIO_GPIO2 _SFR_MEM8(0x0002) -#define GPIO_GPIO3 _SFR_MEM8(0x0003) - -/* NVM_FUSES - Fuses */ -#define FUSE_FUSEBYTE0 _SFR_MEM8(0x0000) -#define FUSE_FUSEBYTE1 _SFR_MEM8(0x0001) -#define FUSE_FUSEBYTE2 _SFR_MEM8(0x0002) -#define FUSE_FUSEBYTE4 _SFR_MEM8(0x0004) -#define FUSE_FUSEBYTE5 _SFR_MEM8(0x0005) - -/* NVM_LOCKBITS - Lock Bits */ -#define LOCKBIT_LOCKBITS _SFR_MEM8(0x0000) - -/* NVM_PROD_SIGNATURES - Production Signatures */ -#define PRODSIGNATURES_RCOSC2M _SFR_MEM8(0x0000) -#define PRODSIGNATURES_RCOSC2MA _SFR_MEM8(0x0001) -#define PRODSIGNATURES_RCOSC32K _SFR_MEM8(0x0002) -#define PRODSIGNATURES_RCOSC32M _SFR_MEM8(0x0003) -#define PRODSIGNATURES_RCOSC32MA _SFR_MEM8(0x0004) -#define PRODSIGNATURES_LOTNUM0 _SFR_MEM8(0x0008) -#define PRODSIGNATURES_LOTNUM1 _SFR_MEM8(0x0009) -#define PRODSIGNATURES_LOTNUM2 _SFR_MEM8(0x000A) -#define PRODSIGNATURES_LOTNUM3 _SFR_MEM8(0x000B) -#define PRODSIGNATURES_LOTNUM4 _SFR_MEM8(0x000C) -#define PRODSIGNATURES_LOTNUM5 _SFR_MEM8(0x000D) -#define PRODSIGNATURES_WAFNUM _SFR_MEM8(0x0010) -#define PRODSIGNATURES_COORDX0 _SFR_MEM8(0x0012) -#define PRODSIGNATURES_COORDX1 _SFR_MEM8(0x0013) -#define PRODSIGNATURES_COORDY0 _SFR_MEM8(0x0014) -#define PRODSIGNATURES_COORDY1 _SFR_MEM8(0x0015) -#define PRODSIGNATURES_USBCAL0 _SFR_MEM8(0x001A) -#define PRODSIGNATURES_USBCAL1 _SFR_MEM8(0x001B) -#define PRODSIGNATURES_USBRCOSC _SFR_MEM8(0x001C) -#define PRODSIGNATURES_USBRCOSCA _SFR_MEM8(0x001D) -#define PRODSIGNATURES_ADCACAL0 _SFR_MEM8(0x0020) -#define PRODSIGNATURES_ADCACAL1 _SFR_MEM8(0x0021) -#define PRODSIGNATURES_ADCBCAL0 _SFR_MEM8(0x0024) -#define PRODSIGNATURES_ADCBCAL1 _SFR_MEM8(0x0025) -#define PRODSIGNATURES_TEMPSENSE0 _SFR_MEM8(0x002E) -#define PRODSIGNATURES_TEMPSENSE1 _SFR_MEM8(0x002F) - -/* VPORT - Virtual Port */ -#define VPORT0_DIR _SFR_MEM8(0x0010) -#define VPORT0_OUT _SFR_MEM8(0x0011) -#define VPORT0_IN _SFR_MEM8(0x0012) -#define VPORT0_INTFLAGS _SFR_MEM8(0x0013) - -/* VPORT - Virtual Port */ -#define VPORT1_DIR _SFR_MEM8(0x0014) -#define VPORT1_OUT _SFR_MEM8(0x0015) -#define VPORT1_IN _SFR_MEM8(0x0016) -#define VPORT1_INTFLAGS _SFR_MEM8(0x0017) - -/* VPORT - Virtual Port */ -#define VPORT2_DIR _SFR_MEM8(0x0018) -#define VPORT2_OUT _SFR_MEM8(0x0019) -#define VPORT2_IN _SFR_MEM8(0x001A) -#define VPORT2_INTFLAGS _SFR_MEM8(0x001B) - -/* VPORT - Virtual Port */ -#define VPORT3_DIR _SFR_MEM8(0x001C) -#define VPORT3_OUT _SFR_MEM8(0x001D) -#define VPORT3_IN _SFR_MEM8(0x001E) -#define VPORT3_INTFLAGS _SFR_MEM8(0x001F) - -/* OCD - On-Chip Debug System */ -#define OCD_OCDR0 _SFR_MEM8(0x002E) -#define OCD_OCDR1 _SFR_MEM8(0x002F) - -/* CPU - CPU registers */ -#define CPU_CCP _SFR_MEM8(0x0034) -#define CPU_RAMPD _SFR_MEM8(0x0038) -#define CPU_RAMPX _SFR_MEM8(0x0039) -#define CPU_RAMPY _SFR_MEM8(0x003A) -#define CPU_RAMPZ _SFR_MEM8(0x003B) -#define CPU_EIND _SFR_MEM8(0x003C) -#define CPU_SPL _SFR_MEM8(0x003D) -#define CPU_SPH _SFR_MEM8(0x003E) -#define CPU_SREG _SFR_MEM8(0x003F) - -/* CLK - Clock System */ -#define CLK_CTRL _SFR_MEM8(0x0040) -#define CLK_PSCTRL _SFR_MEM8(0x0041) -#define CLK_LOCK _SFR_MEM8(0x0042) -#define CLK_RTCCTRL _SFR_MEM8(0x0043) -#define CLK_USBCTRL _SFR_MEM8(0x0044) - -/* SLEEP - Sleep Controller */ -#define SLEEP_CTRL _SFR_MEM8(0x0048) - -/* OSC - Oscillator */ -#define OSC_CTRL _SFR_MEM8(0x0050) -#define OSC_STATUS _SFR_MEM8(0x0051) -#define OSC_XOSCCTRL _SFR_MEM8(0x0052) -#define OSC_XOSCFAIL _SFR_MEM8(0x0053) -#define OSC_RC32KCAL _SFR_MEM8(0x0054) -#define OSC_PLLCTRL _SFR_MEM8(0x0055) -#define OSC_DFLLCTRL _SFR_MEM8(0x0056) - -/* DFLL - DFLL */ -#define DFLLRC32M_CTRL _SFR_MEM8(0x0060) -#define DFLLRC32M_CALA _SFR_MEM8(0x0062) -#define DFLLRC32M_CALB _SFR_MEM8(0x0063) -#define DFLLRC32M_COMP0 _SFR_MEM8(0x0064) -#define DFLLRC32M_COMP1 _SFR_MEM8(0x0065) -#define DFLLRC32M_COMP2 _SFR_MEM8(0x0066) - -/* DFLL - DFLL */ -#define DFLLRC2M_CTRL _SFR_MEM8(0x0068) -#define DFLLRC2M_CALA _SFR_MEM8(0x006A) -#define DFLLRC2M_CALB _SFR_MEM8(0x006B) -#define DFLLRC2M_COMP0 _SFR_MEM8(0x006C) -#define DFLLRC2M_COMP1 _SFR_MEM8(0x006D) -#define DFLLRC2M_COMP2 _SFR_MEM8(0x006E) - -/* PR - Power Reduction */ -#define PR_PRGEN _SFR_MEM8(0x0070) -#define PR_PRPA _SFR_MEM8(0x0071) -#define PR_PRPB _SFR_MEM8(0x0072) -#define PR_PRPC _SFR_MEM8(0x0073) -#define PR_PRPE _SFR_MEM8(0x0075) - -/* RST - Reset */ -#define RST_STATUS _SFR_MEM8(0x0078) -#define RST_CTRL _SFR_MEM8(0x0079) - -/* WDT - Watch-Dog Timer */ -#define WDT_CTRL _SFR_MEM8(0x0080) -#define WDT_WINCTRL _SFR_MEM8(0x0081) -#define WDT_STATUS _SFR_MEM8(0x0082) - -/* MCU - MCU Control */ -#define MCU_DEVID0 _SFR_MEM8(0x0090) -#define MCU_DEVID1 _SFR_MEM8(0x0091) -#define MCU_DEVID2 _SFR_MEM8(0x0092) -#define MCU_REVID _SFR_MEM8(0x0093) -#define MCU_JTAGUID _SFR_MEM8(0x0094) -#define MCU_MCUCR _SFR_MEM8(0x0096) -#define MCU_ANAINIT _SFR_MEM8(0x0097) -#define MCU_EVSYSLOCK _SFR_MEM8(0x0098) -#define MCU_AWEXLOCK _SFR_MEM8(0x0099) - -/* PMIC - Programmable Multi-level Interrupt Controller */ -#define PMIC_STATUS _SFR_MEM8(0x00A0) -#define PMIC_INTPRI _SFR_MEM8(0x00A1) -#define PMIC_CTRL _SFR_MEM8(0x00A2) - -/* PORTCFG - I/O port Configuration */ -#define PORTCFG_MPCMASK _SFR_MEM8(0x00B0) -#define PORTCFG_VPCTRLA _SFR_MEM8(0x00B2) -#define PORTCFG_VPCTRLB _SFR_MEM8(0x00B3) -#define PORTCFG_CLKEVOUT _SFR_MEM8(0x00B4) -#define PORTCFG_EVOUTSEL _SFR_MEM8(0x00B6) - -/* AES - AES Module */ -#define AES_CTRL _SFR_MEM8(0x00C0) -#define AES_STATUS _SFR_MEM8(0x00C1) -#define AES_STATE _SFR_MEM8(0x00C2) -#define AES_KEY _SFR_MEM8(0x00C3) -#define AES_INTCTRL _SFR_MEM8(0x00C4) - -/* CRC - Cyclic Redundancy Checker */ -#define CRC_CTRL _SFR_MEM8(0x00D0) -#define CRC_STATUS _SFR_MEM8(0x00D1) -#define CRC_DATAIN _SFR_MEM8(0x00D3) -#define CRC_CHECKSUM0 _SFR_MEM8(0x00D4) -#define CRC_CHECKSUM1 _SFR_MEM8(0x00D5) -#define CRC_CHECKSUM2 _SFR_MEM8(0x00D6) -#define CRC_CHECKSUM3 _SFR_MEM8(0x00D7) - -/* DMA - DMA Controller */ -#define DMA_CTRL _SFR_MEM8(0x0100) -#define DMA_INTFLAGS _SFR_MEM8(0x0103) -#define DMA_STATUS _SFR_MEM8(0x0104) -#define DMA_TEMP _SFR_MEM16(0x0106) -#define DMA_CH0_CTRLA _SFR_MEM8(0x0110) -#define DMA_CH0_CTRLB _SFR_MEM8(0x0111) -#define DMA_CH0_ADDRCTRL _SFR_MEM8(0x0112) -#define DMA_CH0_TRIGSRC _SFR_MEM8(0x0113) -#define DMA_CH0_TRFCNT _SFR_MEM16(0x0114) -#define DMA_CH0_REPCNT _SFR_MEM8(0x0116) -#define DMA_CH0_SRCADDR0 _SFR_MEM8(0x0118) -#define DMA_CH0_SRCADDR1 _SFR_MEM8(0x0119) -#define DMA_CH0_DESTADDR0 _SFR_MEM8(0x011C) -#define DMA_CH0_DESTADDR1 _SFR_MEM8(0x011D) -#define DMA_CH1_CTRLA _SFR_MEM8(0x0120) -#define DMA_CH1_CTRLB _SFR_MEM8(0x0121) -#define DMA_CH1_ADDRCTRL _SFR_MEM8(0x0122) -#define DMA_CH1_TRIGSRC _SFR_MEM8(0x0123) -#define DMA_CH1_TRFCNT _SFR_MEM16(0x0124) -#define DMA_CH1_REPCNT _SFR_MEM8(0x0126) -#define DMA_CH1_SRCADDR0 _SFR_MEM8(0x0128) -#define DMA_CH1_SRCADDR1 _SFR_MEM8(0x0129) -#define DMA_CH1_DESTADDR0 _SFR_MEM8(0x012C) -#define DMA_CH1_DESTADDR1 _SFR_MEM8(0x012D) - -/* EVSYS - Event System */ -#define EVSYS_CH0MUX _SFR_MEM8(0x0180) -#define EVSYS_CH1MUX _SFR_MEM8(0x0181) -#define EVSYS_CH2MUX _SFR_MEM8(0x0182) -#define EVSYS_CH3MUX _SFR_MEM8(0x0183) -#define EVSYS_CH0CTRL _SFR_MEM8(0x0188) -#define EVSYS_CH1CTRL _SFR_MEM8(0x0189) -#define EVSYS_CH2CTRL _SFR_MEM8(0x018A) -#define EVSYS_CH3CTRL _SFR_MEM8(0x018B) -#define EVSYS_STROBE _SFR_MEM8(0x0190) -#define EVSYS_DATA _SFR_MEM8(0x0191) - -/* NVM - Non-volatile Memory Controller */ -#define NVM_ADDR0 _SFR_MEM8(0x01C0) -#define NVM_ADDR1 _SFR_MEM8(0x01C1) -#define NVM_ADDR2 _SFR_MEM8(0x01C2) -#define NVM_DATA0 _SFR_MEM8(0x01C4) -#define NVM_DATA1 _SFR_MEM8(0x01C5) -#define NVM_DATA2 _SFR_MEM8(0x01C6) -#define NVM_CMD _SFR_MEM8(0x01CA) -#define NVM_CTRLA _SFR_MEM8(0x01CB) -#define NVM_CTRLB _SFR_MEM8(0x01CC) -#define NVM_INTCTRL _SFR_MEM8(0x01CD) -#define NVM_STATUS _SFR_MEM8(0x01CF) -#define NVM_LOCKBITS _SFR_MEM8(0x01D0) - -/* ADC - Analog-to-Digital Converter */ -#define ADCA_CTRLA _SFR_MEM8(0x0200) -#define ADCA_CTRLB _SFR_MEM8(0x0201) -#define ADCA_REFCTRL _SFR_MEM8(0x0202) -#define ADCA_EVCTRL _SFR_MEM8(0x0203) -#define ADCA_PRESCALER _SFR_MEM8(0x0204) -#define ADCA_INTFLAGS _SFR_MEM8(0x0206) -#define ADCA_TEMP _SFR_MEM8(0x0207) -#define ADCA_SAMPCTRL _SFR_MEM8(0x0208) -#define ADCA_CAL _SFR_MEM16(0x020C) -#define ADCA_CH0RES _SFR_MEM16(0x0210) -#define ADCA_CMP _SFR_MEM16(0x0218) -#define ADCA_CH0_CTRL _SFR_MEM8(0x0220) -#define ADCA_CH0_MUXCTRL _SFR_MEM8(0x0221) -#define ADCA_CH0_INTCTRL _SFR_MEM8(0x0222) -#define ADCA_CH0_INTFLAGS _SFR_MEM8(0x0223) -#define ADCA_CH0_RES _SFR_MEM16(0x0224) -#define ADCA_CH0_SCAN _SFR_MEM8(0x0226) - -/* ADC - Analog-to-Digital Converter */ -#define ADCB_CTRLA _SFR_MEM8(0x0240) -#define ADCB_CTRLB _SFR_MEM8(0x0241) -#define ADCB_REFCTRL _SFR_MEM8(0x0242) -#define ADCB_EVCTRL _SFR_MEM8(0x0243) -#define ADCB_PRESCALER _SFR_MEM8(0x0244) -#define ADCB_INTFLAGS _SFR_MEM8(0x0246) -#define ADCB_TEMP _SFR_MEM8(0x0247) -#define ADCB_SAMPCTRL _SFR_MEM8(0x0248) -#define ADCB_CAL _SFR_MEM16(0x024C) -#define ADCB_CH0RES _SFR_MEM16(0x0250) -#define ADCB_CMP _SFR_MEM16(0x0258) -#define ADCB_CH0_CTRL _SFR_MEM8(0x0260) -#define ADCB_CH0_MUXCTRL _SFR_MEM8(0x0261) -#define ADCB_CH0_INTCTRL _SFR_MEM8(0x0262) -#define ADCB_CH0_INTFLAGS _SFR_MEM8(0x0263) -#define ADCB_CH0_RES _SFR_MEM16(0x0264) -#define ADCB_CH0_SCAN _SFR_MEM8(0x0266) - -/* AC - Analog Comparator */ -#define ACA_AC0CTRL _SFR_MEM8(0x0380) -#define ACA_AC1CTRL _SFR_MEM8(0x0381) -#define ACA_AC0MUXCTRL _SFR_MEM8(0x0382) -#define ACA_AC1MUXCTRL _SFR_MEM8(0x0383) -#define ACA_CTRLA _SFR_MEM8(0x0384) -#define ACA_CTRLB _SFR_MEM8(0x0385) -#define ACA_WINCTRL _SFR_MEM8(0x0386) -#define ACA_STATUS _SFR_MEM8(0x0387) -#define ACA_CURRCTRL _SFR_MEM8(0x0388) -#define ACA_CURRCALIB _SFR_MEM8(0x0389) - -/* AC - Analog Comparator */ -#define ACB_AC0CTRL _SFR_MEM8(0x0390) -#define ACB_AC1CTRL _SFR_MEM8(0x0391) -#define ACB_AC0MUXCTRL _SFR_MEM8(0x0392) -#define ACB_AC1MUXCTRL _SFR_MEM8(0x0393) -#define ACB_CTRLA _SFR_MEM8(0x0394) -#define ACB_CTRLB _SFR_MEM8(0x0395) -#define ACB_WINCTRL _SFR_MEM8(0x0396) -#define ACB_STATUS _SFR_MEM8(0x0397) -#define ACB_CURRCTRL _SFR_MEM8(0x0398) -#define ACB_CURRCALIB _SFR_MEM8(0x0399) - -/* RTC - Real-Time Counter */ -#define RTC_CTRL _SFR_MEM8(0x0400) -#define RTC_STATUS _SFR_MEM8(0x0401) -#define RTC_INTCTRL _SFR_MEM8(0x0402) -#define RTC_INTFLAGS _SFR_MEM8(0x0403) -#define RTC_TEMP _SFR_MEM8(0x0404) -#define RTC_CNT _SFR_MEM16(0x0408) -#define RTC_PER _SFR_MEM16(0x040A) -#define RTC_COMP _SFR_MEM16(0x040C) - -/* TWI - Two-Wire Interface */ -#define TWIC_CTRL _SFR_MEM8(0x0480) -#define TWIC_MASTER_CTRLA _SFR_MEM8(0x0481) -#define TWIC_MASTER_CTRLB _SFR_MEM8(0x0482) -#define TWIC_MASTER_CTRLC _SFR_MEM8(0x0483) -#define TWIC_MASTER_STATUS _SFR_MEM8(0x0484) -#define TWIC_MASTER_BAUD _SFR_MEM8(0x0485) -#define TWIC_MASTER_ADDR _SFR_MEM8(0x0486) -#define TWIC_MASTER_DATA _SFR_MEM8(0x0487) -#define TWIC_SLAVE_CTRLA _SFR_MEM8(0x0488) -#define TWIC_SLAVE_CTRLB _SFR_MEM8(0x0489) -#define TWIC_SLAVE_STATUS _SFR_MEM8(0x048A) -#define TWIC_SLAVE_ADDR _SFR_MEM8(0x048B) -#define TWIC_SLAVE_DATA _SFR_MEM8(0x048C) -#define TWIC_SLAVE_ADDRMASK _SFR_MEM8(0x048D) - -/* USB - Universal Serial Bus */ -#define USB_CTRLA _SFR_MEM8(0x04C0) -#define USB_CTRLB _SFR_MEM8(0x04C1) -#define USB_STATUS _SFR_MEM8(0x04C2) -#define USB_ADDR _SFR_MEM8(0x04C3) -#define USB_FIFOWP _SFR_MEM8(0x04C4) -#define USB_FIFORP _SFR_MEM8(0x04C5) -#define USB_EPPTR _SFR_MEM16(0x04C6) -#define USB_INTCTRLA _SFR_MEM8(0x04C8) -#define USB_INTCTRLB _SFR_MEM8(0x04C9) -#define USB_INTFLAGSACLR _SFR_MEM8(0x04CA) -#define USB_INTFLAGSASET _SFR_MEM8(0x04CB) -#define USB_INTFLAGSBCLR _SFR_MEM8(0x04CC) -#define USB_INTFLAGSBSET _SFR_MEM8(0x04CD) -#define USB_CAL0 _SFR_MEM8(0x04FA) -#define USB_CAL1 _SFR_MEM8(0x04FB) - -/* PORT - I/O Ports */ -#define PORTA_DIR _SFR_MEM8(0x0600) -#define PORTA_DIRSET _SFR_MEM8(0x0601) -#define PORTA_DIRCLR _SFR_MEM8(0x0602) -#define PORTA_DIRTGL _SFR_MEM8(0x0603) -#define PORTA_OUT _SFR_MEM8(0x0604) -#define PORTA_OUTSET _SFR_MEM8(0x0605) -#define PORTA_OUTCLR _SFR_MEM8(0x0606) -#define PORTA_OUTTGL _SFR_MEM8(0x0607) -#define PORTA_IN _SFR_MEM8(0x0608) -#define PORTA_INTCTRL _SFR_MEM8(0x0609) -#define PORTA_INT0MASK _SFR_MEM8(0x060A) -#define PORTA_INT1MASK _SFR_MEM8(0x060B) -#define PORTA_INTFLAGS _SFR_MEM8(0x060C) -#define PORTA_REMAP _SFR_MEM8(0x060E) -#define PORTA_PIN0CTRL _SFR_MEM8(0x0610) -#define PORTA_PIN1CTRL _SFR_MEM8(0x0611) -#define PORTA_PIN2CTRL _SFR_MEM8(0x0612) -#define PORTA_PIN3CTRL _SFR_MEM8(0x0613) -#define PORTA_PIN4CTRL _SFR_MEM8(0x0614) -#define PORTA_PIN5CTRL _SFR_MEM8(0x0615) -#define PORTA_PIN6CTRL _SFR_MEM8(0x0616) -#define PORTA_PIN7CTRL _SFR_MEM8(0x0617) - -/* PORT - I/O Ports */ -#define PORTB_DIR _SFR_MEM8(0x0620) -#define PORTB_DIRSET _SFR_MEM8(0x0621) -#define PORTB_DIRCLR _SFR_MEM8(0x0622) -#define PORTB_DIRTGL _SFR_MEM8(0x0623) -#define PORTB_OUT _SFR_MEM8(0x0624) -#define PORTB_OUTSET _SFR_MEM8(0x0625) -#define PORTB_OUTCLR _SFR_MEM8(0x0626) -#define PORTB_OUTTGL _SFR_MEM8(0x0627) -#define PORTB_IN _SFR_MEM8(0x0628) -#define PORTB_INTCTRL _SFR_MEM8(0x0629) -#define PORTB_INT0MASK _SFR_MEM8(0x062A) -#define PORTB_INT1MASK _SFR_MEM8(0x062B) -#define PORTB_INTFLAGS _SFR_MEM8(0x062C) -#define PORTB_REMAP _SFR_MEM8(0x062E) -#define PORTB_PIN0CTRL _SFR_MEM8(0x0630) -#define PORTB_PIN1CTRL _SFR_MEM8(0x0631) -#define PORTB_PIN2CTRL _SFR_MEM8(0x0632) -#define PORTB_PIN3CTRL _SFR_MEM8(0x0633) -#define PORTB_PIN4CTRL _SFR_MEM8(0x0634) -#define PORTB_PIN5CTRL _SFR_MEM8(0x0635) -#define PORTB_PIN6CTRL _SFR_MEM8(0x0636) -#define PORTB_PIN7CTRL _SFR_MEM8(0x0637) - -/* PORT - I/O Ports */ -#define PORTC_DIR _SFR_MEM8(0x0640) -#define PORTC_DIRSET _SFR_MEM8(0x0641) -#define PORTC_DIRCLR _SFR_MEM8(0x0642) -#define PORTC_DIRTGL _SFR_MEM8(0x0643) -#define PORTC_OUT _SFR_MEM8(0x0644) -#define PORTC_OUTSET _SFR_MEM8(0x0645) -#define PORTC_OUTCLR _SFR_MEM8(0x0646) -#define PORTC_OUTTGL _SFR_MEM8(0x0647) -#define PORTC_IN _SFR_MEM8(0x0648) -#define PORTC_INTCTRL _SFR_MEM8(0x0649) -#define PORTC_INT0MASK _SFR_MEM8(0x064A) -#define PORTC_INT1MASK _SFR_MEM8(0x064B) -#define PORTC_INTFLAGS _SFR_MEM8(0x064C) -#define PORTC_REMAP _SFR_MEM8(0x064E) -#define PORTC_PIN0CTRL _SFR_MEM8(0x0650) -#define PORTC_PIN1CTRL _SFR_MEM8(0x0651) -#define PORTC_PIN2CTRL _SFR_MEM8(0x0652) -#define PORTC_PIN3CTRL _SFR_MEM8(0x0653) -#define PORTC_PIN4CTRL _SFR_MEM8(0x0654) -#define PORTC_PIN5CTRL _SFR_MEM8(0x0655) -#define PORTC_PIN6CTRL _SFR_MEM8(0x0656) -#define PORTC_PIN7CTRL _SFR_MEM8(0x0657) - -/* PORT - I/O Ports */ -#define PORTD_DIR _SFR_MEM8(0x0660) -#define PORTD_DIRSET _SFR_MEM8(0x0661) -#define PORTD_DIRCLR _SFR_MEM8(0x0662) -#define PORTD_DIRTGL _SFR_MEM8(0x0663) -#define PORTD_OUT _SFR_MEM8(0x0664) -#define PORTD_OUTSET _SFR_MEM8(0x0665) -#define PORTD_OUTCLR _SFR_MEM8(0x0666) -#define PORTD_OUTTGL _SFR_MEM8(0x0667) -#define PORTD_IN _SFR_MEM8(0x0668) -#define PORTD_INTCTRL _SFR_MEM8(0x0669) -#define PORTD_INT0MASK _SFR_MEM8(0x066A) -#define PORTD_INT1MASK _SFR_MEM8(0x066B) -#define PORTD_INTFLAGS _SFR_MEM8(0x066C) -#define PORTD_REMAP _SFR_MEM8(0x066E) -#define PORTD_PIN0CTRL _SFR_MEM8(0x0670) -#define PORTD_PIN1CTRL _SFR_MEM8(0x0671) -#define PORTD_PIN2CTRL _SFR_MEM8(0x0672) -#define PORTD_PIN3CTRL _SFR_MEM8(0x0673) -#define PORTD_PIN4CTRL _SFR_MEM8(0x0674) -#define PORTD_PIN5CTRL _SFR_MEM8(0x0675) -#define PORTD_PIN6CTRL _SFR_MEM8(0x0676) -#define PORTD_PIN7CTRL _SFR_MEM8(0x0677) - -/* PORT - I/O Ports */ -#define PORTE_DIR _SFR_MEM8(0x0680) -#define PORTE_DIRSET _SFR_MEM8(0x0681) -#define PORTE_DIRCLR _SFR_MEM8(0x0682) -#define PORTE_DIRTGL _SFR_MEM8(0x0683) -#define PORTE_OUT _SFR_MEM8(0x0684) -#define PORTE_OUTSET _SFR_MEM8(0x0685) -#define PORTE_OUTCLR _SFR_MEM8(0x0686) -#define PORTE_OUTTGL _SFR_MEM8(0x0687) -#define PORTE_IN _SFR_MEM8(0x0688) -#define PORTE_INTCTRL _SFR_MEM8(0x0689) -#define PORTE_INT0MASK _SFR_MEM8(0x068A) -#define PORTE_INT1MASK _SFR_MEM8(0x068B) -#define PORTE_INTFLAGS _SFR_MEM8(0x068C) -#define PORTE_REMAP _SFR_MEM8(0x068E) -#define PORTE_PIN0CTRL _SFR_MEM8(0x0690) -#define PORTE_PIN1CTRL _SFR_MEM8(0x0691) -#define PORTE_PIN2CTRL _SFR_MEM8(0x0692) -#define PORTE_PIN3CTRL _SFR_MEM8(0x0693) -#define PORTE_PIN4CTRL _SFR_MEM8(0x0694) -#define PORTE_PIN5CTRL _SFR_MEM8(0x0695) -#define PORTE_PIN6CTRL _SFR_MEM8(0x0696) -#define PORTE_PIN7CTRL _SFR_MEM8(0x0697) - -/* PORT - I/O Ports */ -#define PORTG_DIR _SFR_MEM8(0x06C0) -#define PORTG_DIRSET _SFR_MEM8(0x06C1) -#define PORTG_DIRCLR _SFR_MEM8(0x06C2) -#define PORTG_DIRTGL _SFR_MEM8(0x06C3) -#define PORTG_OUT _SFR_MEM8(0x06C4) -#define PORTG_OUTSET _SFR_MEM8(0x06C5) -#define PORTG_OUTCLR _SFR_MEM8(0x06C6) -#define PORTG_OUTTGL _SFR_MEM8(0x06C7) -#define PORTG_IN _SFR_MEM8(0x06C8) -#define PORTG_INTCTRL _SFR_MEM8(0x06C9) -#define PORTG_INT0MASK _SFR_MEM8(0x06CA) -#define PORTG_INT1MASK _SFR_MEM8(0x06CB) -#define PORTG_INTFLAGS _SFR_MEM8(0x06CC) -#define PORTG_REMAP _SFR_MEM8(0x06CE) -#define PORTG_PIN0CTRL _SFR_MEM8(0x06D0) -#define PORTG_PIN1CTRL _SFR_MEM8(0x06D1) -#define PORTG_PIN2CTRL _SFR_MEM8(0x06D2) -#define PORTG_PIN3CTRL _SFR_MEM8(0x06D3) -#define PORTG_PIN4CTRL _SFR_MEM8(0x06D4) -#define PORTG_PIN5CTRL _SFR_MEM8(0x06D5) -#define PORTG_PIN6CTRL _SFR_MEM8(0x06D6) -#define PORTG_PIN7CTRL _SFR_MEM8(0x06D7) - -/* PORT - I/O Ports */ -#define PORTM_DIR _SFR_MEM8(0x0760) -#define PORTM_DIRSET _SFR_MEM8(0x0761) -#define PORTM_DIRCLR _SFR_MEM8(0x0762) -#define PORTM_DIRTGL _SFR_MEM8(0x0763) -#define PORTM_OUT _SFR_MEM8(0x0764) -#define PORTM_OUTSET _SFR_MEM8(0x0765) -#define PORTM_OUTCLR _SFR_MEM8(0x0766) -#define PORTM_OUTTGL _SFR_MEM8(0x0767) -#define PORTM_IN _SFR_MEM8(0x0768) -#define PORTM_INTCTRL _SFR_MEM8(0x0769) -#define PORTM_INT0MASK _SFR_MEM8(0x076A) -#define PORTM_INT1MASK _SFR_MEM8(0x076B) -#define PORTM_INTFLAGS _SFR_MEM8(0x076C) -#define PORTM_REMAP _SFR_MEM8(0x076E) -#define PORTM_PIN0CTRL _SFR_MEM8(0x0770) -#define PORTM_PIN1CTRL _SFR_MEM8(0x0771) -#define PORTM_PIN2CTRL _SFR_MEM8(0x0772) -#define PORTM_PIN3CTRL _SFR_MEM8(0x0773) -#define PORTM_PIN4CTRL _SFR_MEM8(0x0774) -#define PORTM_PIN5CTRL _SFR_MEM8(0x0775) -#define PORTM_PIN6CTRL _SFR_MEM8(0x0776) -#define PORTM_PIN7CTRL _SFR_MEM8(0x0777) - -/* PORT - I/O Ports */ -#define PORTR_DIR _SFR_MEM8(0x07E0) -#define PORTR_DIRSET _SFR_MEM8(0x07E1) -#define PORTR_DIRCLR _SFR_MEM8(0x07E2) -#define PORTR_DIRTGL _SFR_MEM8(0x07E3) -#define PORTR_OUT _SFR_MEM8(0x07E4) -#define PORTR_OUTSET _SFR_MEM8(0x07E5) -#define PORTR_OUTCLR _SFR_MEM8(0x07E6) -#define PORTR_OUTTGL _SFR_MEM8(0x07E7) -#define PORTR_IN _SFR_MEM8(0x07E8) -#define PORTR_INTCTRL _SFR_MEM8(0x07E9) -#define PORTR_INT0MASK _SFR_MEM8(0x07EA) -#define PORTR_INT1MASK _SFR_MEM8(0x07EB) -#define PORTR_INTFLAGS _SFR_MEM8(0x07EC) -#define PORTR_REMAP _SFR_MEM8(0x07EE) -#define PORTR_PIN0CTRL _SFR_MEM8(0x07F0) -#define PORTR_PIN1CTRL _SFR_MEM8(0x07F1) -#define PORTR_PIN2CTRL _SFR_MEM8(0x07F2) -#define PORTR_PIN3CTRL _SFR_MEM8(0x07F3) -#define PORTR_PIN4CTRL _SFR_MEM8(0x07F4) -#define PORTR_PIN5CTRL _SFR_MEM8(0x07F5) -#define PORTR_PIN6CTRL _SFR_MEM8(0x07F6) -#define PORTR_PIN7CTRL _SFR_MEM8(0x07F7) - -/* TC0 - 16-bit Timer/Counter 0 */ -#define TCC0_CTRLA _SFR_MEM8(0x0800) -#define TCC0_CTRLB _SFR_MEM8(0x0801) -#define TCC0_CTRLC _SFR_MEM8(0x0802) -#define TCC0_CTRLD _SFR_MEM8(0x0803) -#define TCC0_CTRLE _SFR_MEM8(0x0804) -#define TCC0_INTCTRLA _SFR_MEM8(0x0806) -#define TCC0_INTCTRLB _SFR_MEM8(0x0807) -#define TCC0_CTRLFCLR _SFR_MEM8(0x0808) -#define TCC0_CTRLFSET _SFR_MEM8(0x0809) -#define TCC0_CTRLGCLR _SFR_MEM8(0x080A) -#define TCC0_CTRLGSET _SFR_MEM8(0x080B) -#define TCC0_INTFLAGS _SFR_MEM8(0x080C) -#define TCC0_TEMP _SFR_MEM8(0x080F) -#define TCC0_CNT _SFR_MEM16(0x0820) -#define TCC0_PER _SFR_MEM16(0x0826) -#define TCC0_CCA _SFR_MEM16(0x0828) -#define TCC0_CCB _SFR_MEM16(0x082A) -#define TCC0_CCC _SFR_MEM16(0x082C) -#define TCC0_CCD _SFR_MEM16(0x082E) -#define TCC0_PERBUF _SFR_MEM16(0x0836) -#define TCC0_CCABUF _SFR_MEM16(0x0838) -#define TCC0_CCBBUF _SFR_MEM16(0x083A) -#define TCC0_CCCBUF _SFR_MEM16(0x083C) -#define TCC0_CCDBUF _SFR_MEM16(0x083E) - -/* TC1 - 16-bit Timer/Counter 1 */ -#define TCC1_CTRLA _SFR_MEM8(0x0840) -#define TCC1_CTRLB _SFR_MEM8(0x0841) -#define TCC1_CTRLC _SFR_MEM8(0x0842) -#define TCC1_CTRLD _SFR_MEM8(0x0843) -#define TCC1_CTRLE _SFR_MEM8(0x0844) -#define TCC1_INTCTRLA _SFR_MEM8(0x0846) -#define TCC1_INTCTRLB _SFR_MEM8(0x0847) -#define TCC1_CTRLFCLR _SFR_MEM8(0x0848) -#define TCC1_CTRLFSET _SFR_MEM8(0x0849) -#define TCC1_CTRLGCLR _SFR_MEM8(0x084A) -#define TCC1_CTRLGSET _SFR_MEM8(0x084B) -#define TCC1_INTFLAGS _SFR_MEM8(0x084C) -#define TCC1_TEMP _SFR_MEM8(0x084F) -#define TCC1_CNT _SFR_MEM16(0x0860) -#define TCC1_PER _SFR_MEM16(0x0866) -#define TCC1_CCA _SFR_MEM16(0x0868) -#define TCC1_CCB _SFR_MEM16(0x086A) -#define TCC1_PERBUF _SFR_MEM16(0x0876) -#define TCC1_CCABUF _SFR_MEM16(0x0878) -#define TCC1_CCBBUF _SFR_MEM16(0x087A) - -/* AWEX - Advanced Waveform Extension */ -#define AWEXC_CTRL _SFR_MEM8(0x0880) -#define AWEXC_FDEMASK _SFR_MEM8(0x0882) -#define AWEXC_FDCTRL _SFR_MEM8(0x0883) -#define AWEXC_STATUS _SFR_MEM8(0x0884) -#define AWEXC_STATUSSET _SFR_MEM8(0x0885) -#define AWEXC_DTBOTH _SFR_MEM8(0x0886) -#define AWEXC_DTBOTHBUF _SFR_MEM8(0x0887) -#define AWEXC_DTLS _SFR_MEM8(0x0888) -#define AWEXC_DTHS _SFR_MEM8(0x0889) -#define AWEXC_DTLSBUF _SFR_MEM8(0x088A) -#define AWEXC_DTHSBUF _SFR_MEM8(0x088B) -#define AWEXC_OUTOVEN _SFR_MEM8(0x088C) - -/* HIRES - High-Resolution Extension */ -#define HIRESC_CTRLA _SFR_MEM8(0x0890) - -/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ -#define USARTC0_DATA _SFR_MEM8(0x08A0) -#define USARTC0_STATUS _SFR_MEM8(0x08A1) -#define USARTC0_CTRLA _SFR_MEM8(0x08A3) -#define USARTC0_CTRLB _SFR_MEM8(0x08A4) -#define USARTC0_CTRLC _SFR_MEM8(0x08A5) -#define USARTC0_BAUDCTRLA _SFR_MEM8(0x08A6) -#define USARTC0_BAUDCTRLB _SFR_MEM8(0x08A7) - -/* SPI - Serial Peripheral Interface */ -#define SPIC_CTRL _SFR_MEM8(0x08C0) -#define SPIC_INTCTRL _SFR_MEM8(0x08C1) -#define SPIC_STATUS _SFR_MEM8(0x08C2) -#define SPIC_DATA _SFR_MEM8(0x08C3) - -/* IRCOM - IR Communication Module */ -#define IRCOM_CTRL _SFR_MEM8(0x08F8) -#define IRCOM_TXPLCTRL _SFR_MEM8(0x08F9) -#define IRCOM_RXPLCTRL _SFR_MEM8(0x08FA) - -/* TC0 - 16-bit Timer/Counter 0 */ -#define TCE0_CTRLA _SFR_MEM8(0x0A00) -#define TCE0_CTRLB _SFR_MEM8(0x0A01) -#define TCE0_CTRLC _SFR_MEM8(0x0A02) -#define TCE0_CTRLD _SFR_MEM8(0x0A03) -#define TCE0_CTRLE _SFR_MEM8(0x0A04) -#define TCE0_INTCTRLA _SFR_MEM8(0x0A06) -#define TCE0_INTCTRLB _SFR_MEM8(0x0A07) -#define TCE0_CTRLFCLR _SFR_MEM8(0x0A08) -#define TCE0_CTRLFSET _SFR_MEM8(0x0A09) -#define TCE0_CTRLGCLR _SFR_MEM8(0x0A0A) -#define TCE0_CTRLGSET _SFR_MEM8(0x0A0B) -#define TCE0_INTFLAGS _SFR_MEM8(0x0A0C) -#define TCE0_TEMP _SFR_MEM8(0x0A0F) -#define TCE0_CNT _SFR_MEM16(0x0A20) -#define TCE0_PER _SFR_MEM16(0x0A26) -#define TCE0_CCA _SFR_MEM16(0x0A28) -#define TCE0_CCB _SFR_MEM16(0x0A2A) -#define TCE0_CCC _SFR_MEM16(0x0A2C) -#define TCE0_CCD _SFR_MEM16(0x0A2E) -#define TCE0_PERBUF _SFR_MEM16(0x0A36) -#define TCE0_CCABUF _SFR_MEM16(0x0A38) -#define TCE0_CCBBUF _SFR_MEM16(0x0A3A) -#define TCE0_CCCBUF _SFR_MEM16(0x0A3C) -#define TCE0_CCDBUF _SFR_MEM16(0x0A3E) - -/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ -#define USARTE0_DATA _SFR_MEM8(0x0AA0) -#define USARTE0_STATUS _SFR_MEM8(0x0AA1) -#define USARTE0_CTRLA _SFR_MEM8(0x0AA3) -#define USARTE0_CTRLB _SFR_MEM8(0x0AA4) -#define USARTE0_CTRLC _SFR_MEM8(0x0AA5) -#define USARTE0_BAUDCTRLA _SFR_MEM8(0x0AA6) -#define USARTE0_BAUDCTRLB _SFR_MEM8(0x0AA7) - -/* LCD - LCD Controller */ -#define LCD_CTRLA _SFR_MEM8(0x0D00) -#define LCD_CTRLB _SFR_MEM8(0x0D01) -#define LCD_CTRLC _SFR_MEM8(0x0D02) -#define LCD_INTCTRL _SFR_MEM8(0x0D03) -#define LCD_INTFLAG _SFR_MEM8(0x0D04) -#define LCD_CTRLD _SFR_MEM8(0x0D05) -#define LCD_CTRLE _SFR_MEM8(0x0D06) -#define LCD_CTRLF _SFR_MEM8(0x0D07) -#define LCD_CTRLG _SFR_MEM8(0x0D08) -#define LCD_CTRLH _SFR_MEM8(0x0D09) -#define LCD_DATA0 _SFR_MEM8(0x0D10) -#define LCD_DATA1 _SFR_MEM8(0x0D11) -#define LCD_DATA2 _SFR_MEM8(0x0D12) -#define LCD_DATA3 _SFR_MEM8(0x0D13) -#define LCD_DATA4 _SFR_MEM8(0x0D14) -#define LCD_DATA5 _SFR_MEM8(0x0D15) -#define LCD_DATA6 _SFR_MEM8(0x0D16) -#define LCD_DATA7 _SFR_MEM8(0x0D17) -#define LCD_DATA8 _SFR_MEM8(0x0D18) -#define LCD_DATA9 _SFR_MEM8(0x0D19) -#define LCD_DATA10 _SFR_MEM8(0x0D1A) -#define LCD_DATA11 _SFR_MEM8(0x0D1B) -#define LCD_DATA12 _SFR_MEM8(0x0D1C) -#define LCD_DATA13 _SFR_MEM8(0x0D1D) -#define LCD_DATA14 _SFR_MEM8(0x0D1E) -#define LCD_DATA15 _SFR_MEM8(0x0D1F) -#define LCD_DATA16 _SFR_MEM8(0x0D20) -#define LCD_DATA17 _SFR_MEM8(0x0D21) -#define LCD_DATA18 _SFR_MEM8(0x0D22) -#define LCD_DATA19 _SFR_MEM8(0x0D23) - - - -/*================== Bitfield Definitions ================== */ - -/* VPORT - Virtual Ports */ -/* VPORT.INTFLAGS bit masks and bit positions */ -#define VPORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ -#define VPORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ - -#define VPORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ -#define VPORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ - -/* XOCD - On-Chip Debug System */ -/* OCD.OCDR0 bit masks and bit positions */ -#define OCD_OCDRD_gm 0xFF /* OCDR Dirty group mask. */ -#define OCD_OCDRD_gp 0 /* OCDR Dirty group position. */ -#define OCD_OCDRD0_bm (1<<0) /* OCDR Dirty bit 0 mask. */ -#define OCD_OCDRD0_bp 0 /* OCDR Dirty bit 0 position. */ -#define OCD_OCDRD1_bm (1<<1) /* OCDR Dirty bit 1 mask. */ -#define OCD_OCDRD1_bp 1 /* OCDR Dirty bit 1 position. */ -#define OCD_OCDRD2_bm (1<<2) /* OCDR Dirty bit 2 mask. */ -#define OCD_OCDRD2_bp 2 /* OCDR Dirty bit 2 position. */ -#define OCD_OCDRD3_bm (1<<3) /* OCDR Dirty bit 3 mask. */ -#define OCD_OCDRD3_bp 3 /* OCDR Dirty bit 3 position. */ -#define OCD_OCDRD4_bm (1<<4) /* OCDR Dirty bit 4 mask. */ -#define OCD_OCDRD4_bp 4 /* OCDR Dirty bit 4 position. */ -#define OCD_OCDRD5_bm (1<<5) /* OCDR Dirty bit 5 mask. */ -#define OCD_OCDRD5_bp 5 /* OCDR Dirty bit 5 position. */ -#define OCD_OCDRD6_bm (1<<6) /* OCDR Dirty bit 6 mask. */ -#define OCD_OCDRD6_bp 6 /* OCDR Dirty bit 6 position. */ -#define OCD_OCDRD7_bm (1<<7) /* OCDR Dirty bit 7 mask. */ -#define OCD_OCDRD7_bp 7 /* OCDR Dirty bit 7 position. */ - -/* OCD.OCDR1 bit masks and bit positions */ -/* OCD_OCDRD Predefined. */ -/* OCD_OCDRD Predefined. */ - -/* CPU - CPU */ -/* CPU.CCP bit masks and bit positions */ -#define CPU_CCP_gm 0xFF /* CCP signature group mask. */ -#define CPU_CCP_gp 0 /* CCP signature group position. */ -#define CPU_CCP0_bm (1<<0) /* CCP signature bit 0 mask. */ -#define CPU_CCP0_bp 0 /* CCP signature bit 0 position. */ -#define CPU_CCP1_bm (1<<1) /* CCP signature bit 1 mask. */ -#define CPU_CCP1_bp 1 /* CCP signature bit 1 position. */ -#define CPU_CCP2_bm (1<<2) /* CCP signature bit 2 mask. */ -#define CPU_CCP2_bp 2 /* CCP signature bit 2 position. */ -#define CPU_CCP3_bm (1<<3) /* CCP signature bit 3 mask. */ -#define CPU_CCP3_bp 3 /* CCP signature bit 3 position. */ -#define CPU_CCP4_bm (1<<4) /* CCP signature bit 4 mask. */ -#define CPU_CCP4_bp 4 /* CCP signature bit 4 position. */ -#define CPU_CCP5_bm (1<<5) /* CCP signature bit 5 mask. */ -#define CPU_CCP5_bp 5 /* CCP signature bit 5 position. */ -#define CPU_CCP6_bm (1<<6) /* CCP signature bit 6 mask. */ -#define CPU_CCP6_bp 6 /* CCP signature bit 6 position. */ -#define CPU_CCP7_bm (1<<7) /* CCP signature bit 7 mask. */ -#define CPU_CCP7_bp 7 /* CCP signature bit 7 position. */ - -/* CPU.SREG bit masks and bit positions */ -#define CPU_I_bm 0x80 /* Global Interrupt Enable Flag bit mask. */ -#define CPU_I_bp 7 /* Global Interrupt Enable Flag bit position. */ - -#define CPU_T_bm 0x40 /* Transfer Bit bit mask. */ -#define CPU_T_bp 6 /* Transfer Bit bit position. */ - -#define CPU_H_bm 0x20 /* Half Carry Flag bit mask. */ -#define CPU_H_bp 5 /* Half Carry Flag bit position. */ - -#define CPU_S_bm 0x10 /* N Exclusive Or V Flag bit mask. */ -#define CPU_S_bp 4 /* N Exclusive Or V Flag bit position. */ - -#define CPU_V_bm 0x08 /* Two's Complement Overflow Flag bit mask. */ -#define CPU_V_bp 3 /* Two's Complement Overflow Flag bit position. */ - -#define CPU_N_bm 0x04 /* Negative Flag bit mask. */ -#define CPU_N_bp 2 /* Negative Flag bit position. */ - -#define CPU_Z_bm 0x02 /* Zero Flag bit mask. */ -#define CPU_Z_bp 1 /* Zero Flag bit position. */ - -#define CPU_C_bm 0x01 /* Carry Flag bit mask. */ -#define CPU_C_bp 0 /* Carry Flag bit position. */ - -/* CLK - Clock System */ -/* CLK.CTRL bit masks and bit positions */ -#define CLK_SCLKSEL_gm 0x07 /* System Clock Selection group mask. */ -#define CLK_SCLKSEL_gp 0 /* System Clock Selection group position. */ -#define CLK_SCLKSEL0_bm (1<<0) /* System Clock Selection bit 0 mask. */ -#define CLK_SCLKSEL0_bp 0 /* System Clock Selection bit 0 position. */ -#define CLK_SCLKSEL1_bm (1<<1) /* System Clock Selection bit 1 mask. */ -#define CLK_SCLKSEL1_bp 1 /* System Clock Selection bit 1 position. */ -#define CLK_SCLKSEL2_bm (1<<2) /* System Clock Selection bit 2 mask. */ -#define CLK_SCLKSEL2_bp 2 /* System Clock Selection bit 2 position. */ - -/* CLK.PSCTRL bit masks and bit positions */ -#define CLK_PSADIV_gm 0x7C /* Prescaler A Division Factor group mask. */ -#define CLK_PSADIV_gp 2 /* Prescaler A Division Factor group position. */ -#define CLK_PSADIV0_bm (1<<2) /* Prescaler A Division Factor bit 0 mask. */ -#define CLK_PSADIV0_bp 2 /* Prescaler A Division Factor bit 0 position. */ -#define CLK_PSADIV1_bm (1<<3) /* Prescaler A Division Factor bit 1 mask. */ -#define CLK_PSADIV1_bp 3 /* Prescaler A Division Factor bit 1 position. */ -#define CLK_PSADIV2_bm (1<<4) /* Prescaler A Division Factor bit 2 mask. */ -#define CLK_PSADIV2_bp 4 /* Prescaler A Division Factor bit 2 position. */ -#define CLK_PSADIV3_bm (1<<5) /* Prescaler A Division Factor bit 3 mask. */ -#define CLK_PSADIV3_bp 5 /* Prescaler A Division Factor bit 3 position. */ -#define CLK_PSADIV4_bm (1<<6) /* Prescaler A Division Factor bit 4 mask. */ -#define CLK_PSADIV4_bp 6 /* Prescaler A Division Factor bit 4 position. */ - -#define CLK_PSBCDIV_gm 0x03 /* Prescaler B and C Division factor group mask. */ -#define CLK_PSBCDIV_gp 0 /* Prescaler B and C Division factor group position. */ -#define CLK_PSBCDIV0_bm (1<<0) /* Prescaler B and C Division factor bit 0 mask. */ -#define CLK_PSBCDIV0_bp 0 /* Prescaler B and C Division factor bit 0 position. */ -#define CLK_PSBCDIV1_bm (1<<1) /* Prescaler B and C Division factor bit 1 mask. */ -#define CLK_PSBCDIV1_bp 1 /* Prescaler B and C Division factor bit 1 position. */ - -/* CLK.LOCK bit masks and bit positions */ -#define CLK_LOCK_bm 0x01 /* Clock System Lock bit mask. */ -#define CLK_LOCK_bp 0 /* Clock System Lock bit position. */ - -/* CLK.RTCCTRL bit masks and bit positions */ -#define CLK_RTCSRC_gm 0x0E /* Clock Source group mask. */ -#define CLK_RTCSRC_gp 1 /* Clock Source group position. */ -#define CLK_RTCSRC0_bm (1<<1) /* Clock Source bit 0 mask. */ -#define CLK_RTCSRC0_bp 1 /* Clock Source bit 0 position. */ -#define CLK_RTCSRC1_bm (1<<2) /* Clock Source bit 1 mask. */ -#define CLK_RTCSRC1_bp 2 /* Clock Source bit 1 position. */ -#define CLK_RTCSRC2_bm (1<<3) /* Clock Source bit 2 mask. */ -#define CLK_RTCSRC2_bp 3 /* Clock Source bit 2 position. */ - -#define CLK_RTCEN_bm 0x01 /* Clock Source Enable bit mask. */ -#define CLK_RTCEN_bp 0 /* Clock Source Enable bit position. */ - -/* CLK.USBCTRL bit masks and bit positions */ -#define CLK_USBPSDIV_gm 0x38 /* Prescaler Division Factor group mask. */ -#define CLK_USBPSDIV_gp 3 /* Prescaler Division Factor group position. */ -#define CLK_USBPSDIV0_bm (1<<3) /* Prescaler Division Factor bit 0 mask. */ -#define CLK_USBPSDIV0_bp 3 /* Prescaler Division Factor bit 0 position. */ -#define CLK_USBPSDIV1_bm (1<<4) /* Prescaler Division Factor bit 1 mask. */ -#define CLK_USBPSDIV1_bp 4 /* Prescaler Division Factor bit 1 position. */ -#define CLK_USBPSDIV2_bm (1<<5) /* Prescaler Division Factor bit 2 mask. */ -#define CLK_USBPSDIV2_bp 5 /* Prescaler Division Factor bit 2 position. */ - -#define CLK_USBSRC_gm 0x06 /* Clock Source group mask. */ -#define CLK_USBSRC_gp 1 /* Clock Source group position. */ -#define CLK_USBSRC0_bm (1<<1) /* Clock Source bit 0 mask. */ -#define CLK_USBSRC0_bp 1 /* Clock Source bit 0 position. */ -#define CLK_USBSRC1_bm (1<<2) /* Clock Source bit 1 mask. */ -#define CLK_USBSRC1_bp 2 /* Clock Source bit 1 position. */ - -#define CLK_USBSEN_bm 0x01 /* Clock Source Enable bit mask. */ -#define CLK_USBSEN_bp 0 /* Clock Source Enable bit position. */ - -/* SLEEP - Sleep Controller */ -/* SLEEP.CTRL bit masks and bit positions */ -#define SLEEP_SMODE_gm 0x0E /* Sleep Mode group mask. */ -#define SLEEP_SMODE_gp 1 /* Sleep Mode group position. */ -#define SLEEP_SMODE0_bm (1<<1) /* Sleep Mode bit 0 mask. */ -#define SLEEP_SMODE0_bp 1 /* Sleep Mode bit 0 position. */ -#define SLEEP_SMODE1_bm (1<<2) /* Sleep Mode bit 1 mask. */ -#define SLEEP_SMODE1_bp 2 /* Sleep Mode bit 1 position. */ -#define SLEEP_SMODE2_bm (1<<3) /* Sleep Mode bit 2 mask. */ -#define SLEEP_SMODE2_bp 3 /* Sleep Mode bit 2 position. */ - -#define SLEEP_SEN_bm 0x01 /* Sleep Enable bit mask. */ -#define SLEEP_SEN_bp 0 /* Sleep Enable bit position. */ - -/* OSC - Oscillator */ -/* OSC.CTRL bit masks and bit positions */ -#define OSC_PLLEN_bm 0x10 /* PLL Enable bit mask. */ -#define OSC_PLLEN_bp 4 /* PLL Enable bit position. */ - -#define OSC_XOSCEN_bm 0x08 /* External Oscillator Enable bit mask. */ -#define OSC_XOSCEN_bp 3 /* External Oscillator Enable bit position. */ - -#define OSC_RC32KEN_bm 0x04 /* Internal 32.768 kHz RC Oscillator Enable bit mask. */ -#define OSC_RC32KEN_bp 2 /* Internal 32.768 kHz RC Oscillator Enable bit position. */ - -#define OSC_RC32MEN_bm 0x02 /* Internal 32 MHz RC Oscillator Enable bit mask. */ -#define OSC_RC32MEN_bp 1 /* Internal 32 MHz RC Oscillator Enable bit position. */ - -#define OSC_RC2MEN_bm 0x01 /* Internal 2 MHz RC Oscillator Enable bit mask. */ -#define OSC_RC2MEN_bp 0 /* Internal 2 MHz RC Oscillator Enable bit position. */ - -/* OSC.STATUS bit masks and bit positions */ -#define OSC_PLLRDY_bm 0x10 /* PLL Ready bit mask. */ -#define OSC_PLLRDY_bp 4 /* PLL Ready bit position. */ - -#define OSC_XOSCRDY_bm 0x08 /* External Oscillator Ready bit mask. */ -#define OSC_XOSCRDY_bp 3 /* External Oscillator Ready bit position. */ - -#define OSC_RC32KRDY_bm 0x04 /* Internal 32.768 kHz RC Oscillator Ready bit mask. */ -#define OSC_RC32KRDY_bp 2 /* Internal 32.768 kHz RC Oscillator Ready bit position. */ - -#define OSC_RC32MRDY_bm 0x02 /* Internal 32 MHz RC Oscillator Ready bit mask. */ -#define OSC_RC32MRDY_bp 1 /* Internal 32 MHz RC Oscillator Ready bit position. */ - -#define OSC_RC2MRDY_bm 0x01 /* Internal 2 MHz RC Oscillator Ready bit mask. */ -#define OSC_RC2MRDY_bp 0 /* Internal 2 MHz RC Oscillator Ready bit position. */ - -/* OSC.XOSCCTRL bit masks and bit positions */ -#define OSC_FRQRANGE_gm 0xC0 /* Frequency Range group mask. */ -#define OSC_FRQRANGE_gp 6 /* Frequency Range group position. */ -#define OSC_FRQRANGE0_bm (1<<6) /* Frequency Range bit 0 mask. */ -#define OSC_FRQRANGE0_bp 6 /* Frequency Range bit 0 position. */ -#define OSC_FRQRANGE1_bm (1<<7) /* Frequency Range bit 1 mask. */ -#define OSC_FRQRANGE1_bp 7 /* Frequency Range bit 1 position. */ - -#define OSC_X32KLPM_bm 0x20 /* 32.768 kHz XTAL OSC Low-power Mode bit mask. */ -#define OSC_X32KLPM_bp 5 /* 32.768 kHz XTAL OSC Low-power Mode bit position. */ - -#define OSC_XOSCPWR_bm 0x10 /* 16 MHz Crystal Oscillator High Power mode bit mask. */ -#define OSC_XOSCPWR_bp 4 /* 16 MHz Crystal Oscillator High Power mode bit position. */ - -#define OSC_XOSCSEL_gm 0x1F /* External Oscillator Selection and Startup Time group mask. */ -#define OSC_XOSCSEL_gp 0 /* External Oscillator Selection and Startup Time group position. */ -#define OSC_XOSCSEL0_bm (1<<0) /* External Oscillator Selection and Startup Time bit 0 mask. */ -#define OSC_XOSCSEL0_bp 0 /* External Oscillator Selection and Startup Time bit 0 position. */ -#define OSC_XOSCSEL1_bm (1<<1) /* External Oscillator Selection and Startup Time bit 1 mask. */ -#define OSC_XOSCSEL1_bp 1 /* External Oscillator Selection and Startup Time bit 1 position. */ -#define OSC_XOSCSEL2_bm (1<<2) /* External Oscillator Selection and Startup Time bit 2 mask. */ -#define OSC_XOSCSEL2_bp 2 /* External Oscillator Selection and Startup Time bit 2 position. */ -#define OSC_XOSCSEL3_bm (1<<3) /* External Oscillator Selection and Startup Time bit 3 mask. */ -#define OSC_XOSCSEL3_bp 3 /* External Oscillator Selection and Startup Time bit 3 position. */ -#define OSC_XOSCSEL4_bm (1<<4) /* External Oscillator Selection and Startup Time bit 4 mask. */ -#define OSC_XOSCSEL4_bp 4 /* External Oscillator Selection and Startup Time bit 4 position. */ - -/* OSC.XOSCFAIL bit masks and bit positions */ -#define OSC_PLLFDIF_bm 0x08 /* PLL Failure Detection Interrupt Flag bit mask. */ -#define OSC_PLLFDIF_bp 3 /* PLL Failure Detection Interrupt Flag bit position. */ - -#define OSC_PLLFDEN_bm 0x04 /* PLL Failure Detection Enable bit mask. */ -#define OSC_PLLFDEN_bp 2 /* PLL Failure Detection Enable bit position. */ - -#define OSC_XOSCFDIF_bm 0x02 /* XOSC Failure Detection Interrupt Flag bit mask. */ -#define OSC_XOSCFDIF_bp 1 /* XOSC Failure Detection Interrupt Flag bit position. */ - -#define OSC_XOSCFDEN_bm 0x01 /* XOSC Failure Detection Enable bit mask. */ -#define OSC_XOSCFDEN_bp 0 /* XOSC Failure Detection Enable bit position. */ - -/* OSC.PLLCTRL bit masks and bit positions */ -#define OSC_PLLSRC_gm 0xC0 /* Clock Source group mask. */ -#define OSC_PLLSRC_gp 6 /* Clock Source group position. */ -#define OSC_PLLSRC0_bm (1<<6) /* Clock Source bit 0 mask. */ -#define OSC_PLLSRC0_bp 6 /* Clock Source bit 0 position. */ -#define OSC_PLLSRC1_bm (1<<7) /* Clock Source bit 1 mask. */ -#define OSC_PLLSRC1_bp 7 /* Clock Source bit 1 position. */ - -#define OSC_PLLDIV_bm 0x20 /* Divide by 2 bit mask. */ -#define OSC_PLLDIV_bp 5 /* Divide by 2 bit position. */ - -#define OSC_PLLFAC_gm 0x1F /* Multiplication Factor group mask. */ -#define OSC_PLLFAC_gp 0 /* Multiplication Factor group position. */ -#define OSC_PLLFAC0_bm (1<<0) /* Multiplication Factor bit 0 mask. */ -#define OSC_PLLFAC0_bp 0 /* Multiplication Factor bit 0 position. */ -#define OSC_PLLFAC1_bm (1<<1) /* Multiplication Factor bit 1 mask. */ -#define OSC_PLLFAC1_bp 1 /* Multiplication Factor bit 1 position. */ -#define OSC_PLLFAC2_bm (1<<2) /* Multiplication Factor bit 2 mask. */ -#define OSC_PLLFAC2_bp 2 /* Multiplication Factor bit 2 position. */ -#define OSC_PLLFAC3_bm (1<<3) /* Multiplication Factor bit 3 mask. */ -#define OSC_PLLFAC3_bp 3 /* Multiplication Factor bit 3 position. */ -#define OSC_PLLFAC4_bm (1<<4) /* Multiplication Factor bit 4 mask. */ -#define OSC_PLLFAC4_bp 4 /* Multiplication Factor bit 4 position. */ - -/* OSC.DFLLCTRL bit masks and bit positions */ -#define OSC_RC32MCREF_gm 0x06 /* 32 MHz DFLL Calibration Reference group mask. */ -#define OSC_RC32MCREF_gp 1 /* 32 MHz DFLL Calibration Reference group position. */ -#define OSC_RC32MCREF0_bm (1<<1) /* 32 MHz DFLL Calibration Reference bit 0 mask. */ -#define OSC_RC32MCREF0_bp 1 /* 32 MHz DFLL Calibration Reference bit 0 position. */ -#define OSC_RC32MCREF1_bm (1<<2) /* 32 MHz DFLL Calibration Reference bit 1 mask. */ -#define OSC_RC32MCREF1_bp 2 /* 32 MHz DFLL Calibration Reference bit 1 position. */ - -#define OSC_RC2MCREF_bm 0x01 /* 2 MHz DFLL Calibration Reference bit mask. */ -#define OSC_RC2MCREF_bp 0 /* 2 MHz DFLL Calibration Reference bit position. */ - -/* DFLL - DFLL */ -/* DFLL.CTRL bit masks and bit positions */ -#define DFLL_ENABLE_bm 0x01 /* DFLL Enable bit mask. */ -#define DFLL_ENABLE_bp 0 /* DFLL Enable bit position. */ - -/* DFLL.CALA bit masks and bit positions */ -#define DFLL_CALL_gm 0x7F /* DFLL Calibration Value A group mask. */ -#define DFLL_CALL_gp 0 /* DFLL Calibration Value A group position. */ -#define DFLL_CALL0_bm (1<<0) /* DFLL Calibration Value A bit 0 mask. */ -#define DFLL_CALL0_bp 0 /* DFLL Calibration Value A bit 0 position. */ -#define DFLL_CALL1_bm (1<<1) /* DFLL Calibration Value A bit 1 mask. */ -#define DFLL_CALL1_bp 1 /* DFLL Calibration Value A bit 1 position. */ -#define DFLL_CALL2_bm (1<<2) /* DFLL Calibration Value A bit 2 mask. */ -#define DFLL_CALL2_bp 2 /* DFLL Calibration Value A bit 2 position. */ -#define DFLL_CALL3_bm (1<<3) /* DFLL Calibration Value A bit 3 mask. */ -#define DFLL_CALL3_bp 3 /* DFLL Calibration Value A bit 3 position. */ -#define DFLL_CALL4_bm (1<<4) /* DFLL Calibration Value A bit 4 mask. */ -#define DFLL_CALL4_bp 4 /* DFLL Calibration Value A bit 4 position. */ -#define DFLL_CALL5_bm (1<<5) /* DFLL Calibration Value A bit 5 mask. */ -#define DFLL_CALL5_bp 5 /* DFLL Calibration Value A bit 5 position. */ -#define DFLL_CALL6_bm (1<<6) /* DFLL Calibration Value A bit 6 mask. */ -#define DFLL_CALL6_bp 6 /* DFLL Calibration Value A bit 6 position. */ - -/* DFLL.CALB bit masks and bit positions */ -#define DFLL_CALH_gm 0x3F /* DFLL Calibration Value B group mask. */ -#define DFLL_CALH_gp 0 /* DFLL Calibration Value B group position. */ -#define DFLL_CALH0_bm (1<<0) /* DFLL Calibration Value B bit 0 mask. */ -#define DFLL_CALH0_bp 0 /* DFLL Calibration Value B bit 0 position. */ -#define DFLL_CALH1_bm (1<<1) /* DFLL Calibration Value B bit 1 mask. */ -#define DFLL_CALH1_bp 1 /* DFLL Calibration Value B bit 1 position. */ -#define DFLL_CALH2_bm (1<<2) /* DFLL Calibration Value B bit 2 mask. */ -#define DFLL_CALH2_bp 2 /* DFLL Calibration Value B bit 2 position. */ -#define DFLL_CALH3_bm (1<<3) /* DFLL Calibration Value B bit 3 mask. */ -#define DFLL_CALH3_bp 3 /* DFLL Calibration Value B bit 3 position. */ -#define DFLL_CALH4_bm (1<<4) /* DFLL Calibration Value B bit 4 mask. */ -#define DFLL_CALH4_bp 4 /* DFLL Calibration Value B bit 4 position. */ -#define DFLL_CALH5_bm (1<<5) /* DFLL Calibration Value B bit 5 mask. */ -#define DFLL_CALH5_bp 5 /* DFLL Calibration Value B bit 5 position. */ - -/* PR - Power Reduction */ -/* PR.PRGEN bit masks and bit positions */ -#define PR_LCD_bm 0x80 /* LCD Module bit mask. */ -#define PR_LCD_bp 7 /* LCD Module bit position. */ - -#define PR_USB_bm 0x40 /* USB bit mask. */ -#define PR_USB_bp 6 /* USB bit position. */ - -#define PR_AES_bm 0x10 /* AES bit mask. */ -#define PR_AES_bp 4 /* AES bit position. */ - -#define PR_RTC_bm 0x04 /* Real-time Counter bit mask. */ -#define PR_RTC_bp 2 /* Real-time Counter bit position. */ - -#define PR_EVSYS_bm 0x02 /* Event System bit mask. */ -#define PR_EVSYS_bp 1 /* Event System bit position. */ - -#define PR_DMA_bm 0x01 /* DMA-Controller bit mask. */ -#define PR_DMA_bp 0 /* DMA-Controller bit position. */ - -/* PR.PRPA bit masks and bit positions */ -#define PR_ADC_bm 0x02 /* Port A ADC bit mask. */ -#define PR_ADC_bp 1 /* Port A ADC bit position. */ - -#define PR_AC_bm 0x01 /* Port A Analog Comparator bit mask. */ -#define PR_AC_bp 0 /* Port A Analog Comparator bit position. */ - -/* PR.PRPB bit masks and bit positions */ -/* PR_ADC Predefined. */ -/* PR_ADC Predefined. */ - -/* PR_AC Predefined. */ -/* PR_AC Predefined. */ - -/* PR.PRPC bit masks and bit positions */ -#define PR_TWI_bm 0x40 /* Port C Two-wire Interface bit mask. */ -#define PR_TWI_bp 6 /* Port C Two-wire Interface bit position. */ - -#define PR_USART0_bm 0x10 /* Port C USART0 bit mask. */ -#define PR_USART0_bp 4 /* Port C USART0 bit position. */ - -#define PR_SPI_bm 0x08 /* Port C SPI bit mask. */ -#define PR_SPI_bp 3 /* Port C SPI bit position. */ - -#define PR_HIRES_bm 0x04 /* Port C AWEX bit mask. */ -#define PR_HIRES_bp 2 /* Port C AWEX bit position. */ - -#define PR_TC1_bm 0x02 /* Port C Timer/Counter1 bit mask. */ -#define PR_TC1_bp 1 /* Port C Timer/Counter1 bit position. */ - -#define PR_TC0_bm 0x01 /* Port C Timer/Counter0 bit mask. */ -#define PR_TC0_bp 0 /* Port C Timer/Counter0 bit position. */ - -/* PR.PRPE bit masks and bit positions */ -/* PR_USART0 Predefined. */ -/* PR_USART0 Predefined. */ - -/* PR_TC0 Predefined. */ -/* PR_TC0 Predefined. */ - -/* RST - Reset */ -/* RST.STATUS bit masks and bit positions */ -#define RST_SDRF_bm 0x40 /* Spike Detection Reset Flag bit mask. */ -#define RST_SDRF_bp 6 /* Spike Detection Reset Flag bit position. */ - -#define RST_SRF_bm 0x20 /* Software Reset Flag bit mask. */ -#define RST_SRF_bp 5 /* Software Reset Flag bit position. */ - -#define RST_PDIRF_bm 0x10 /* Programming and Debug Interface Interface Reset Flag bit mask. */ -#define RST_PDIRF_bp 4 /* Programming and Debug Interface Interface Reset Flag bit position. */ - -#define RST_WDRF_bm 0x08 /* Watchdog Reset Flag bit mask. */ -#define RST_WDRF_bp 3 /* Watchdog Reset Flag bit position. */ - -#define RST_BORF_bm 0x04 /* Brown-out Reset Flag bit mask. */ -#define RST_BORF_bp 2 /* Brown-out Reset Flag bit position. */ - -#define RST_EXTRF_bm 0x02 /* External Reset Flag bit mask. */ -#define RST_EXTRF_bp 1 /* External Reset Flag bit position. */ - -#define RST_PORF_bm 0x01 /* Power-on Reset Flag bit mask. */ -#define RST_PORF_bp 0 /* Power-on Reset Flag bit position. */ - -/* RST.CTRL bit masks and bit positions */ -#define RST_SWRST_bm 0x01 /* Software Reset bit mask. */ -#define RST_SWRST_bp 0 /* Software Reset bit position. */ - -/* WDT - Watch-Dog Timer */ -/* WDT.CTRL bit masks and bit positions */ -#define WDT_PER_gm 0x3C /* Period group mask. */ -#define WDT_PER_gp 2 /* Period group position. */ -#define WDT_PER0_bm (1<<2) /* Period bit 0 mask. */ -#define WDT_PER0_bp 2 /* Period bit 0 position. */ -#define WDT_PER1_bm (1<<3) /* Period bit 1 mask. */ -#define WDT_PER1_bp 3 /* Period bit 1 position. */ -#define WDT_PER2_bm (1<<4) /* Period bit 2 mask. */ -#define WDT_PER2_bp 4 /* Period bit 2 position. */ -#define WDT_PER3_bm (1<<5) /* Period bit 3 mask. */ -#define WDT_PER3_bp 5 /* Period bit 3 position. */ - -#define WDT_ENABLE_bm 0x02 /* Enable bit mask. */ -#define WDT_ENABLE_bp 1 /* Enable bit position. */ - -#define WDT_CEN_bm 0x01 /* Change Enable bit mask. */ -#define WDT_CEN_bp 0 /* Change Enable bit position. */ - -/* WDT.WINCTRL bit masks and bit positions */ -#define WDT_WPER_gm 0x3C /* Windowed Mode Period group mask. */ -#define WDT_WPER_gp 2 /* Windowed Mode Period group position. */ -#define WDT_WPER0_bm (1<<2) /* Windowed Mode Period bit 0 mask. */ -#define WDT_WPER0_bp 2 /* Windowed Mode Period bit 0 position. */ -#define WDT_WPER1_bm (1<<3) /* Windowed Mode Period bit 1 mask. */ -#define WDT_WPER1_bp 3 /* Windowed Mode Period bit 1 position. */ -#define WDT_WPER2_bm (1<<4) /* Windowed Mode Period bit 2 mask. */ -#define WDT_WPER2_bp 4 /* Windowed Mode Period bit 2 position. */ -#define WDT_WPER3_bm (1<<5) /* Windowed Mode Period bit 3 mask. */ -#define WDT_WPER3_bp 5 /* Windowed Mode Period bit 3 position. */ - -#define WDT_WEN_bm 0x02 /* Windowed Mode Enable bit mask. */ -#define WDT_WEN_bp 1 /* Windowed Mode Enable bit position. */ - -#define WDT_WCEN_bm 0x01 /* Windowed Mode Change Enable bit mask. */ -#define WDT_WCEN_bp 0 /* Windowed Mode Change Enable bit position. */ - -/* WDT.STATUS bit masks and bit positions */ -#define WDT_SYNCBUSY_bm 0x01 /* Syncronization busy bit mask. */ -#define WDT_SYNCBUSY_bp 0 /* Syncronization busy bit position. */ - -/* MCU - MCU Control */ -/* MCU.MCUCR bit masks and bit positions */ -#define MCU_JTAGD_bm 0x01 /* JTAG Disable bit mask. */ -#define MCU_JTAGD_bp 0 /* JTAG Disable bit position. */ - -/* MCU.ANAINIT bit masks and bit positions */ -#define MCU_STARTUPDLYB_gm 0x0C /* Analog startup delay Port B group mask. */ -#define MCU_STARTUPDLYB_gp 2 /* Analog startup delay Port B group position. */ -#define MCU_STARTUPDLYB0_bm (1<<2) /* Analog startup delay Port B bit 0 mask. */ -#define MCU_STARTUPDLYB0_bp 2 /* Analog startup delay Port B bit 0 position. */ -#define MCU_STARTUPDLYB1_bm (1<<3) /* Analog startup delay Port B bit 1 mask. */ -#define MCU_STARTUPDLYB1_bp 3 /* Analog startup delay Port B bit 1 position. */ - -#define MCU_STARTUPDLYA_gm 0x03 /* Analog startup delay Port A group mask. */ -#define MCU_STARTUPDLYA_gp 0 /* Analog startup delay Port A group position. */ -#define MCU_STARTUPDLYA0_bm (1<<0) /* Analog startup delay Port A bit 0 mask. */ -#define MCU_STARTUPDLYA0_bp 0 /* Analog startup delay Port A bit 0 position. */ -#define MCU_STARTUPDLYA1_bm (1<<1) /* Analog startup delay Port A bit 1 mask. */ -#define MCU_STARTUPDLYA1_bp 1 /* Analog startup delay Port A bit 1 position. */ - -/* MCU.EVSYSLOCK bit masks and bit positions */ -#define MCU_EVSYS1LOCK_bm 0x10 /* Event Channel 4-7 Lock bit mask. */ -#define MCU_EVSYS1LOCK_bp 4 /* Event Channel 4-7 Lock bit position. */ - -#define MCU_EVSYS0LOCK_bm 0x01 /* Event Channel 0-3 Lock bit mask. */ -#define MCU_EVSYS0LOCK_bp 0 /* Event Channel 0-3 Lock bit position. */ - -/* MCU.AWEXLOCK bit masks and bit positions */ -#define MCU_AWEXCLOCK_bm 0x01 /* AWeX on T/C C0 Lock bit mask. */ -#define MCU_AWEXCLOCK_bp 0 /* AWeX on T/C C0 Lock bit position. */ - -/* PMIC - Programmable Multi-level Interrupt Controller */ -/* PMIC.STATUS bit masks and bit positions */ -#define PMIC_NMIEX_bm 0x80 /* Non-maskable Interrupt Executing bit mask. */ -#define PMIC_NMIEX_bp 7 /* Non-maskable Interrupt Executing bit position. */ - -#define PMIC_HILVLEX_bm 0x04 /* High Level Interrupt Executing bit mask. */ -#define PMIC_HILVLEX_bp 2 /* High Level Interrupt Executing bit position. */ - -#define PMIC_MEDLVLEX_bm 0x02 /* Medium Level Interrupt Executing bit mask. */ -#define PMIC_MEDLVLEX_bp 1 /* Medium Level Interrupt Executing bit position. */ - -#define PMIC_LOLVLEX_bm 0x01 /* Low Level Interrupt Executing bit mask. */ -#define PMIC_LOLVLEX_bp 0 /* Low Level Interrupt Executing bit position. */ - -/* PMIC.INTPRI bit masks and bit positions */ -#define PMIC_INTPRI_gm 0xFF /* Interrupt Priority group mask. */ -#define PMIC_INTPRI_gp 0 /* Interrupt Priority group position. */ -#define PMIC_INTPRI0_bm (1<<0) /* Interrupt Priority bit 0 mask. */ -#define PMIC_INTPRI0_bp 0 /* Interrupt Priority bit 0 position. */ -#define PMIC_INTPRI1_bm (1<<1) /* Interrupt Priority bit 1 mask. */ -#define PMIC_INTPRI1_bp 1 /* Interrupt Priority bit 1 position. */ -#define PMIC_INTPRI2_bm (1<<2) /* Interrupt Priority bit 2 mask. */ -#define PMIC_INTPRI2_bp 2 /* Interrupt Priority bit 2 position. */ -#define PMIC_INTPRI3_bm (1<<3) /* Interrupt Priority bit 3 mask. */ -#define PMIC_INTPRI3_bp 3 /* Interrupt Priority bit 3 position. */ -#define PMIC_INTPRI4_bm (1<<4) /* Interrupt Priority bit 4 mask. */ -#define PMIC_INTPRI4_bp 4 /* Interrupt Priority bit 4 position. */ -#define PMIC_INTPRI5_bm (1<<5) /* Interrupt Priority bit 5 mask. */ -#define PMIC_INTPRI5_bp 5 /* Interrupt Priority bit 5 position. */ -#define PMIC_INTPRI6_bm (1<<6) /* Interrupt Priority bit 6 mask. */ -#define PMIC_INTPRI6_bp 6 /* Interrupt Priority bit 6 position. */ -#define PMIC_INTPRI7_bm (1<<7) /* Interrupt Priority bit 7 mask. */ -#define PMIC_INTPRI7_bp 7 /* Interrupt Priority bit 7 position. */ - -/* PMIC.CTRL bit masks and bit positions */ -#define PMIC_RREN_bm 0x80 /* Round-Robin Priority Enable bit mask. */ -#define PMIC_RREN_bp 7 /* Round-Robin Priority Enable bit position. */ - -#define PMIC_IVSEL_bm 0x40 /* Interrupt Vector Select bit mask. */ -#define PMIC_IVSEL_bp 6 /* Interrupt Vector Select bit position. */ - -#define PMIC_HILVLEN_bm 0x04 /* High Level Enable bit mask. */ -#define PMIC_HILVLEN_bp 2 /* High Level Enable bit position. */ - -#define PMIC_MEDLVLEN_bm 0x02 /* Medium Level Enable bit mask. */ -#define PMIC_MEDLVLEN_bp 1 /* Medium Level Enable bit position. */ - -#define PMIC_LOLVLEN_bm 0x01 /* Low Level Enable bit mask. */ -#define PMIC_LOLVLEN_bp 0 /* Low Level Enable bit position. */ - -/* PORTCFG - Port Configuration */ -/* PORTCFG.VPCTRLA bit masks and bit positions */ -#define PORTCFG_VP1MAP_gm 0xF0 /* Virtual Port 1 Mapping group mask. */ -#define PORTCFG_VP1MAP_gp 4 /* Virtual Port 1 Mapping group position. */ -#define PORTCFG_VP1MAP0_bm (1<<4) /* Virtual Port 1 Mapping bit 0 mask. */ -#define PORTCFG_VP1MAP0_bp 4 /* Virtual Port 1 Mapping bit 0 position. */ -#define PORTCFG_VP1MAP1_bm (1<<5) /* Virtual Port 1 Mapping bit 1 mask. */ -#define PORTCFG_VP1MAP1_bp 5 /* Virtual Port 1 Mapping bit 1 position. */ -#define PORTCFG_VP1MAP2_bm (1<<6) /* Virtual Port 1 Mapping bit 2 mask. */ -#define PORTCFG_VP1MAP2_bp 6 /* Virtual Port 1 Mapping bit 2 position. */ -#define PORTCFG_VP1MAP3_bm (1<<7) /* Virtual Port 1 Mapping bit 3 mask. */ -#define PORTCFG_VP1MAP3_bp 7 /* Virtual Port 1 Mapping bit 3 position. */ - -#define PORTCFG_VP0MAP_gm 0x0F /* Virtual Port 0 Mapping group mask. */ -#define PORTCFG_VP0MAP_gp 0 /* Virtual Port 0 Mapping group position. */ -#define PORTCFG_VP0MAP0_bm (1<<0) /* Virtual Port 0 Mapping bit 0 mask. */ -#define PORTCFG_VP0MAP0_bp 0 /* Virtual Port 0 Mapping bit 0 position. */ -#define PORTCFG_VP0MAP1_bm (1<<1) /* Virtual Port 0 Mapping bit 1 mask. */ -#define PORTCFG_VP0MAP1_bp 1 /* Virtual Port 0 Mapping bit 1 position. */ -#define PORTCFG_VP0MAP2_bm (1<<2) /* Virtual Port 0 Mapping bit 2 mask. */ -#define PORTCFG_VP0MAP2_bp 2 /* Virtual Port 0 Mapping bit 2 position. */ -#define PORTCFG_VP0MAP3_bm (1<<3) /* Virtual Port 0 Mapping bit 3 mask. */ -#define PORTCFG_VP0MAP3_bp 3 /* Virtual Port 0 Mapping bit 3 position. */ - -/* PORTCFG.VPCTRLB bit masks and bit positions */ -#define PORTCFG_VP3MAP_gm 0xF0 /* Virtual Port 3 Mapping group mask. */ -#define PORTCFG_VP3MAP_gp 4 /* Virtual Port 3 Mapping group position. */ -#define PORTCFG_VP3MAP0_bm (1<<4) /* Virtual Port 3 Mapping bit 0 mask. */ -#define PORTCFG_VP3MAP0_bp 4 /* Virtual Port 3 Mapping bit 0 position. */ -#define PORTCFG_VP3MAP1_bm (1<<5) /* Virtual Port 3 Mapping bit 1 mask. */ -#define PORTCFG_VP3MAP1_bp 5 /* Virtual Port 3 Mapping bit 1 position. */ -#define PORTCFG_VP3MAP2_bm (1<<6) /* Virtual Port 3 Mapping bit 2 mask. */ -#define PORTCFG_VP3MAP2_bp 6 /* Virtual Port 3 Mapping bit 2 position. */ -#define PORTCFG_VP3MAP3_bm (1<<7) /* Virtual Port 3 Mapping bit 3 mask. */ -#define PORTCFG_VP3MAP3_bp 7 /* Virtual Port 3 Mapping bit 3 position. */ - -#define PORTCFG_VP2MAP_gm 0x0F /* Virtual Port 2 Mapping group mask. */ -#define PORTCFG_VP2MAP_gp 0 /* Virtual Port 2 Mapping group position. */ -#define PORTCFG_VP2MAP0_bm (1<<0) /* Virtual Port 2 Mapping bit 0 mask. */ -#define PORTCFG_VP2MAP0_bp 0 /* Virtual Port 2 Mapping bit 0 position. */ -#define PORTCFG_VP2MAP1_bm (1<<1) /* Virtual Port 2 Mapping bit 1 mask. */ -#define PORTCFG_VP2MAP1_bp 1 /* Virtual Port 2 Mapping bit 1 position. */ -#define PORTCFG_VP2MAP2_bm (1<<2) /* Virtual Port 2 Mapping bit 2 mask. */ -#define PORTCFG_VP2MAP2_bp 2 /* Virtual Port 2 Mapping bit 2 position. */ -#define PORTCFG_VP2MAP3_bm (1<<3) /* Virtual Port 2 Mapping bit 3 mask. */ -#define PORTCFG_VP2MAP3_bp 3 /* Virtual Port 2 Mapping bit 3 position. */ - -/* PORTCFG.CLKEVOUT bit masks and bit positions */ -#define PORTCFG_CLKOUT_gm 0x03 /* Peripheral Clock Output Port group mask. */ -#define PORTCFG_CLKOUT_gp 0 /* Peripheral Clock Output Port group position. */ -#define PORTCFG_CLKOUT0_bm (1<<0) /* Peripheral Clock Output Port bit 0 mask. */ -#define PORTCFG_CLKOUT0_bp 0 /* Peripheral Clock Output Port bit 0 position. */ -#define PORTCFG_CLKOUT1_bm (1<<1) /* Peripheral Clock Output Port bit 1 mask. */ -#define PORTCFG_CLKOUT1_bp 1 /* Peripheral Clock Output Port bit 1 position. */ - -#define PORTCFG_CLKOUTSEL_gm 0x0C /* Peripheral Clock Output Select group mask. */ -#define PORTCFG_CLKOUTSEL_gp 2 /* Peripheral Clock Output Select group position. */ -#define PORTCFG_CLKOUTSEL0_bm (1<<2) /* Peripheral Clock Output Select bit 0 mask. */ -#define PORTCFG_CLKOUTSEL0_bp 2 /* Peripheral Clock Output Select bit 0 position. */ -#define PORTCFG_CLKOUTSEL1_bm (1<<3) /* Peripheral Clock Output Select bit 1 mask. */ -#define PORTCFG_CLKOUTSEL1_bp 3 /* Peripheral Clock Output Select bit 1 position. */ - -#define PORTCFG_EVOUT_gm 0x30 /* Event Output Port group mask. */ -#define PORTCFG_EVOUT_gp 4 /* Event Output Port group position. */ -#define PORTCFG_EVOUT0_bm (1<<4) /* Event Output Port bit 0 mask. */ -#define PORTCFG_EVOUT0_bp 4 /* Event Output Port bit 0 position. */ -#define PORTCFG_EVOUT1_bm (1<<5) /* Event Output Port bit 1 mask. */ -#define PORTCFG_EVOUT1_bp 5 /* Event Output Port bit 1 position. */ - -#define PORTCFG_RTCOUT_bm 0x40 /* RTC Clock Output bit mask. */ -#define PORTCFG_RTCOUT_bp 6 /* RTC Clock Output bit position. */ - -#define PORTCFG_CLKEVPIN_bm 0x80 /* Peripheral Clock and Event Output pin Select bit mask. */ -#define PORTCFG_CLKEVPIN_bp 7 /* Peripheral Clock and Event Output pin Select bit position. */ - -/* PORTCFG.EVOUTSEL bit masks and bit positions */ -#define PORTCFG_EVOUTSEL_bm 0x04 /* Event Output Select bit mask. */ -#define PORTCFG_EVOUTSEL_bp 2 /* Event Output Select bit position. */ - -/* AES - AES Module */ -/* AES.CTRL bit masks and bit positions */ -#define AES_START_bm 0x80 /* Start/Run bit mask. */ -#define AES_START_bp 7 /* Start/Run bit position. */ - -#define AES_AUTO_bm 0x40 /* Auto Start Trigger bit mask. */ -#define AES_AUTO_bp 6 /* Auto Start Trigger bit position. */ - -#define AES_RESET_bm 0x20 /* AES Software Reset bit mask. */ -#define AES_RESET_bp 5 /* AES Software Reset bit position. */ - -#define AES_DECRYPT_bm 0x10 /* Decryption / Direction bit mask. */ -#define AES_DECRYPT_bp 4 /* Decryption / Direction bit position. */ - -#define AES_XOR_bm 0x04 /* State XOR Load Enable bit mask. */ -#define AES_XOR_bp 2 /* State XOR Load Enable bit position. */ - -/* AES.STATUS bit masks and bit positions */ -#define AES_ERROR_bm 0x80 /* AES Error bit mask. */ -#define AES_ERROR_bp 7 /* AES Error bit position. */ - -#define AES_SRIF_bm 0x01 /* State Ready Interrupt Flag bit mask. */ -#define AES_SRIF_bp 0 /* State Ready Interrupt Flag bit position. */ - -/* AES.INTCTRL bit masks and bit positions */ -#define AES_INTLVL_gm 0x03 /* Interrupt level group mask. */ -#define AES_INTLVL_gp 0 /* Interrupt level group position. */ -#define AES_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */ -#define AES_INTLVL0_bp 0 /* Interrupt level bit 0 position. */ -#define AES_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */ -#define AES_INTLVL1_bp 1 /* Interrupt level bit 1 position. */ - -/* CRC - Cyclic Redundancy Checker */ -/* CRC.CTRL bit masks and bit positions */ -#define CRC_RESET_gm 0xC0 /* Reset group mask. */ -#define CRC_RESET_gp 6 /* Reset group position. */ -#define CRC_RESET0_bm (1<<6) /* Reset bit 0 mask. */ -#define CRC_RESET0_bp 6 /* Reset bit 0 position. */ -#define CRC_RESET1_bm (1<<7) /* Reset bit 1 mask. */ -#define CRC_RESET1_bp 7 /* Reset bit 1 position. */ - -#define CRC_CRC32_bm 0x20 /* CRC Mode bit mask. */ -#define CRC_CRC32_bp 5 /* CRC Mode bit position. */ - -#define CRC_SOURCE_gm 0x0F /* Input Source group mask. */ -#define CRC_SOURCE_gp 0 /* Input Source group position. */ -#define CRC_SOURCE0_bm (1<<0) /* Input Source bit 0 mask. */ -#define CRC_SOURCE0_bp 0 /* Input Source bit 0 position. */ -#define CRC_SOURCE1_bm (1<<1) /* Input Source bit 1 mask. */ -#define CRC_SOURCE1_bp 1 /* Input Source bit 1 position. */ -#define CRC_SOURCE2_bm (1<<2) /* Input Source bit 2 mask. */ -#define CRC_SOURCE2_bp 2 /* Input Source bit 2 position. */ -#define CRC_SOURCE3_bm (1<<3) /* Input Source bit 3 mask. */ -#define CRC_SOURCE3_bp 3 /* Input Source bit 3 position. */ - -/* CRC.STATUS bit masks and bit positions */ -#define CRC_ZERO_bm 0x02 /* Zero detection bit mask. */ -#define CRC_ZERO_bp 1 /* Zero detection bit position. */ - -#define CRC_BUSY_bm 0x01 /* Busy bit mask. */ -#define CRC_BUSY_bp 0 /* Busy bit position. */ - -/* DMA - DMA Controller */ -/* DMA_CH.CTRLA bit masks and bit positions */ -#define DMA_CH_CHEN_bm 0x80 /* Channel Enable bit mask. */ -#define DMA_CH_CHEN_bp 7 /* Channel Enable bit position. */ - -#define DMA_CH_CHRST_bm 0x40 /* Channel Software Reset bit mask. */ -#define DMA_CH_CHRST_bp 6 /* Channel Software Reset bit position. */ - -#define DMA_CH_REPEAT_bm 0x20 /* Channel Repeat Mode bit mask. */ -#define DMA_CH_REPEAT_bp 5 /* Channel Repeat Mode bit position. */ - -#define DMA_CH_TRFREQ_bm 0x10 /* Channel Transfer Request bit mask. */ -#define DMA_CH_TRFREQ_bp 4 /* Channel Transfer Request bit position. */ - -#define DMA_CH_SINGLE_bm 0x04 /* Channel Single Shot Data Transfer bit mask. */ -#define DMA_CH_SINGLE_bp 2 /* Channel Single Shot Data Transfer bit position. */ - -#define DMA_CH_BURSTLEN_gm 0x03 /* Channel Transfer Mode group mask. */ -#define DMA_CH_BURSTLEN_gp 0 /* Channel Transfer Mode group position. */ -#define DMA_CH_BURSTLEN0_bm (1<<0) /* Channel Transfer Mode bit 0 mask. */ -#define DMA_CH_BURSTLEN0_bp 0 /* Channel Transfer Mode bit 0 position. */ -#define DMA_CH_BURSTLEN1_bm (1<<1) /* Channel Transfer Mode bit 1 mask. */ -#define DMA_CH_BURSTLEN1_bp 1 /* Channel Transfer Mode bit 1 position. */ - -/* DMA_CH.CTRLB bit masks and bit positions */ -#define DMA_CH_CHBUSY_bm 0x80 /* Block Transfer Busy bit mask. */ -#define DMA_CH_CHBUSY_bp 7 /* Block Transfer Busy bit position. */ - -#define DMA_CH_CHPEND_bm 0x40 /* Block Transfer Pending bit mask. */ -#define DMA_CH_CHPEND_bp 6 /* Block Transfer Pending bit position. */ - -#define DMA_CH_ERRIF_bm 0x20 /* Block Transfer Error Interrupt Flag bit mask. */ -#define DMA_CH_ERRIF_bp 5 /* Block Transfer Error Interrupt Flag bit position. */ - -#define DMA_CH_TRNIF_bm 0x10 /* Transaction Complete Interrup Flag bit mask. */ -#define DMA_CH_TRNIF_bp 4 /* Transaction Complete Interrup Flag bit position. */ - -#define DMA_CH_ERRINTLVL_gm 0x0C /* Transfer Error Interrupt Level group mask. */ -#define DMA_CH_ERRINTLVL_gp 2 /* Transfer Error Interrupt Level group position. */ -#define DMA_CH_ERRINTLVL0_bm (1<<2) /* Transfer Error Interrupt Level bit 0 mask. */ -#define DMA_CH_ERRINTLVL0_bp 2 /* Transfer Error Interrupt Level bit 0 position. */ -#define DMA_CH_ERRINTLVL1_bm (1<<3) /* Transfer Error Interrupt Level bit 1 mask. */ -#define DMA_CH_ERRINTLVL1_bp 3 /* Transfer Error Interrupt Level bit 1 position. */ - -#define DMA_CH_TRNINTLVL_gm 0x03 /* Transaction Complete Interrupt Level group mask. */ -#define DMA_CH_TRNINTLVL_gp 0 /* Transaction Complete Interrupt Level group position. */ -#define DMA_CH_TRNINTLVL0_bm (1<<0) /* Transaction Complete Interrupt Level bit 0 mask. */ -#define DMA_CH_TRNINTLVL0_bp 0 /* Transaction Complete Interrupt Level bit 0 position. */ -#define DMA_CH_TRNINTLVL1_bm (1<<1) /* Transaction Complete Interrupt Level bit 1 mask. */ -#define DMA_CH_TRNINTLVL1_bp 1 /* Transaction Complete Interrupt Level bit 1 position. */ - -/* DMA_CH.ADDRCTRL bit masks and bit positions */ -#define DMA_CH_SRCRELOAD_gm 0xC0 /* Channel Source Address Reload group mask. */ -#define DMA_CH_SRCRELOAD_gp 6 /* Channel Source Address Reload group position. */ -#define DMA_CH_SRCRELOAD0_bm (1<<6) /* Channel Source Address Reload bit 0 mask. */ -#define DMA_CH_SRCRELOAD0_bp 6 /* Channel Source Address Reload bit 0 position. */ -#define DMA_CH_SRCRELOAD1_bm (1<<7) /* Channel Source Address Reload bit 1 mask. */ -#define DMA_CH_SRCRELOAD1_bp 7 /* Channel Source Address Reload bit 1 position. */ - -#define DMA_CH_SRCDIR_gm 0x30 /* Channel Source Address Mode group mask. */ -#define DMA_CH_SRCDIR_gp 4 /* Channel Source Address Mode group position. */ -#define DMA_CH_SRCDIR0_bm (1<<4) /* Channel Source Address Mode bit 0 mask. */ -#define DMA_CH_SRCDIR0_bp 4 /* Channel Source Address Mode bit 0 position. */ -#define DMA_CH_SRCDIR1_bm (1<<5) /* Channel Source Address Mode bit 1 mask. */ -#define DMA_CH_SRCDIR1_bp 5 /* Channel Source Address Mode bit 1 position. */ - -#define DMA_CH_DESTRELOAD_gm 0x0C /* Channel Destination Address Reload group mask. */ -#define DMA_CH_DESTRELOAD_gp 2 /* Channel Destination Address Reload group position. */ -#define DMA_CH_DESTRELOAD0_bm (1<<2) /* Channel Destination Address Reload bit 0 mask. */ -#define DMA_CH_DESTRELOAD0_bp 2 /* Channel Destination Address Reload bit 0 position. */ -#define DMA_CH_DESTRELOAD1_bm (1<<3) /* Channel Destination Address Reload bit 1 mask. */ -#define DMA_CH_DESTRELOAD1_bp 3 /* Channel Destination Address Reload bit 1 position. */ - -#define DMA_CH_DESTDIR_gm 0x03 /* Channel Destination Address Mode group mask. */ -#define DMA_CH_DESTDIR_gp 0 /* Channel Destination Address Mode group position. */ -#define DMA_CH_DESTDIR0_bm (1<<0) /* Channel Destination Address Mode bit 0 mask. */ -#define DMA_CH_DESTDIR0_bp 0 /* Channel Destination Address Mode bit 0 position. */ -#define DMA_CH_DESTDIR1_bm (1<<1) /* Channel Destination Address Mode bit 1 mask. */ -#define DMA_CH_DESTDIR1_bp 1 /* Channel Destination Address Mode bit 1 position. */ - -/* DMA_CH.TRIGSRC bit masks and bit positions */ -#define DMA_CH_TRIGSRC_gm 0xFF /* Channel Trigger Source group mask. */ -#define DMA_CH_TRIGSRC_gp 0 /* Channel Trigger Source group position. */ -#define DMA_CH_TRIGSRC0_bm (1<<0) /* Channel Trigger Source bit 0 mask. */ -#define DMA_CH_TRIGSRC0_bp 0 /* Channel Trigger Source bit 0 position. */ -#define DMA_CH_TRIGSRC1_bm (1<<1) /* Channel Trigger Source bit 1 mask. */ -#define DMA_CH_TRIGSRC1_bp 1 /* Channel Trigger Source bit 1 position. */ -#define DMA_CH_TRIGSRC2_bm (1<<2) /* Channel Trigger Source bit 2 mask. */ -#define DMA_CH_TRIGSRC2_bp 2 /* Channel Trigger Source bit 2 position. */ -#define DMA_CH_TRIGSRC3_bm (1<<3) /* Channel Trigger Source bit 3 mask. */ -#define DMA_CH_TRIGSRC3_bp 3 /* Channel Trigger Source bit 3 position. */ -#define DMA_CH_TRIGSRC4_bm (1<<4) /* Channel Trigger Source bit 4 mask. */ -#define DMA_CH_TRIGSRC4_bp 4 /* Channel Trigger Source bit 4 position. */ -#define DMA_CH_TRIGSRC5_bm (1<<5) /* Channel Trigger Source bit 5 mask. */ -#define DMA_CH_TRIGSRC5_bp 5 /* Channel Trigger Source bit 5 position. */ -#define DMA_CH_TRIGSRC6_bm (1<<6) /* Channel Trigger Source bit 6 mask. */ -#define DMA_CH_TRIGSRC6_bp 6 /* Channel Trigger Source bit 6 position. */ -#define DMA_CH_TRIGSRC7_bm (1<<7) /* Channel Trigger Source bit 7 mask. */ -#define DMA_CH_TRIGSRC7_bp 7 /* Channel Trigger Source bit 7 position. */ - -/* DMA.CTRL bit masks and bit positions */ -#define DMA_ENABLE_bm 0x80 /* Enable bit mask. */ -#define DMA_ENABLE_bp 7 /* Enable bit position. */ - -#define DMA_RESET_bm 0x40 /* Software Reset bit mask. */ -#define DMA_RESET_bp 6 /* Software Reset bit position. */ - -#define DMA_DBUFMODE_bm 0x04 /* Double Buffering Mode bit mask. */ -#define DMA_DBUFMODE_bp 2 /* Double Buffering Mode bit position. */ - -#define DMA_PRIMODE_bm 0x01 /* Channel Priority Mode bit mask. */ -#define DMA_PRIMODE_bp 0 /* Channel Priority Mode bit position. */ - -/* DMA.INTFLAGS bit masks and bit positions */ -#define DMA_CH1ERRIF_bm 0x20 /* Channel 1 Block Transfer Error Interrupt Flag bit mask. */ -#define DMA_CH1ERRIF_bp 5 /* Channel 1 Block Transfer Error Interrupt Flag bit position. */ - -#define DMA_CH0ERRIF_bm 0x10 /* Channel 0 Block Transfer Error Interrupt Flag bit mask. */ -#define DMA_CH0ERRIF_bp 4 /* Channel 0 Block Transfer Error Interrupt Flag bit position. */ - -#define DMA_CH1TRNIF_bm 0x02 /* Channel 1 Transaction Complete Interrupt Flag bit mask. */ -#define DMA_CH1TRNIF_bp 1 /* Channel 1 Transaction Complete Interrupt Flag bit position. */ - -#define DMA_CH0TRNIF_bm 0x01 /* Channel 0 Transaction Complete Interrupt Flag bit mask. */ -#define DMA_CH0TRNIF_bp 0 /* Channel 0 Transaction Complete Interrupt Flag bit position. */ - -/* DMA.STATUS bit masks and bit positions */ -#define DMA_CH1BUSY_bm 0x20 /* Channel 1 Block Transfer Busy bit mask. */ -#define DMA_CH1BUSY_bp 5 /* Channel 1 Block Transfer Busy bit position. */ - -#define DMA_CH0BUSY_bm 0x10 /* Channel 0 Block Transfer Busy bit mask. */ -#define DMA_CH0BUSY_bp 4 /* Channel 0 Block Transfer Busy bit position. */ - -#define DMA_CH1PEND_bm 0x02 /* Channel 1 Block Transfer Pending bit mask. */ -#define DMA_CH1PEND_bp 1 /* Channel 1 Block Transfer Pending bit position. */ - -#define DMA_CH0PEND_bm 0x01 /* Channel 0 Block Transfer Pending bit mask. */ -#define DMA_CH0PEND_bp 0 /* Channel 0 Block Transfer Pending bit position. */ - -/* EVSYS - Event System */ -/* EVSYS.CH0MUX bit masks and bit positions */ -#define EVSYS_CHMUX_gm 0xFF /* Event Channel 0 Multiplexer group mask. */ -#define EVSYS_CHMUX_gp 0 /* Event Channel 0 Multiplexer group position. */ -#define EVSYS_CHMUX0_bm (1<<0) /* Event Channel 0 Multiplexer bit 0 mask. */ -#define EVSYS_CHMUX0_bp 0 /* Event Channel 0 Multiplexer bit 0 position. */ -#define EVSYS_CHMUX1_bm (1<<1) /* Event Channel 0 Multiplexer bit 1 mask. */ -#define EVSYS_CHMUX1_bp 1 /* Event Channel 0 Multiplexer bit 1 position. */ -#define EVSYS_CHMUX2_bm (1<<2) /* Event Channel 0 Multiplexer bit 2 mask. */ -#define EVSYS_CHMUX2_bp 2 /* Event Channel 0 Multiplexer bit 2 position. */ -#define EVSYS_CHMUX3_bm (1<<3) /* Event Channel 0 Multiplexer bit 3 mask. */ -#define EVSYS_CHMUX3_bp 3 /* Event Channel 0 Multiplexer bit 3 position. */ -#define EVSYS_CHMUX4_bm (1<<4) /* Event Channel 0 Multiplexer bit 4 mask. */ -#define EVSYS_CHMUX4_bp 4 /* Event Channel 0 Multiplexer bit 4 position. */ -#define EVSYS_CHMUX5_bm (1<<5) /* Event Channel 0 Multiplexer bit 5 mask. */ -#define EVSYS_CHMUX5_bp 5 /* Event Channel 0 Multiplexer bit 5 position. */ -#define EVSYS_CHMUX6_bm (1<<6) /* Event Channel 0 Multiplexer bit 6 mask. */ -#define EVSYS_CHMUX6_bp 6 /* Event Channel 0 Multiplexer bit 6 position. */ -#define EVSYS_CHMUX7_bm (1<<7) /* Event Channel 0 Multiplexer bit 7 mask. */ -#define EVSYS_CHMUX7_bp 7 /* Event Channel 0 Multiplexer bit 7 position. */ - -/* EVSYS.CH1MUX bit masks and bit positions */ -/* EVSYS_CHMUX Predefined. */ -/* EVSYS_CHMUX Predefined. */ - -/* EVSYS.CH2MUX bit masks and bit positions */ -/* EVSYS_CHMUX Predefined. */ -/* EVSYS_CHMUX Predefined. */ - -/* EVSYS.CH3MUX bit masks and bit positions */ -/* EVSYS_CHMUX Predefined. */ -/* EVSYS_CHMUX Predefined. */ - -/* EVSYS.CH0CTRL bit masks and bit positions */ -#define EVSYS_QDIRM_gm 0x60 /* Quadrature Decoder Index Recognition Mode group mask. */ -#define EVSYS_QDIRM_gp 5 /* Quadrature Decoder Index Recognition Mode group position. */ -#define EVSYS_QDIRM0_bm (1<<5) /* Quadrature Decoder Index Recognition Mode bit 0 mask. */ -#define EVSYS_QDIRM0_bp 5 /* Quadrature Decoder Index Recognition Mode bit 0 position. */ -#define EVSYS_QDIRM1_bm (1<<6) /* Quadrature Decoder Index Recognition Mode bit 1 mask. */ -#define EVSYS_QDIRM1_bp 6 /* Quadrature Decoder Index Recognition Mode bit 1 position. */ - -#define EVSYS_QDIEN_bm 0x10 /* Quadrature Decoder Index Enable bit mask. */ -#define EVSYS_QDIEN_bp 4 /* Quadrature Decoder Index Enable bit position. */ - -#define EVSYS_QDEN_bm 0x08 /* Quadrature Decoder Enable bit mask. */ -#define EVSYS_QDEN_bp 3 /* Quadrature Decoder Enable bit position. */ - -#define EVSYS_DIGFILT_gm 0x07 /* Digital Filter group mask. */ -#define EVSYS_DIGFILT_gp 0 /* Digital Filter group position. */ -#define EVSYS_DIGFILT0_bm (1<<0) /* Digital Filter bit 0 mask. */ -#define EVSYS_DIGFILT0_bp 0 /* Digital Filter bit 0 position. */ -#define EVSYS_DIGFILT1_bm (1<<1) /* Digital Filter bit 1 mask. */ -#define EVSYS_DIGFILT1_bp 1 /* Digital Filter bit 1 position. */ -#define EVSYS_DIGFILT2_bm (1<<2) /* Digital Filter bit 2 mask. */ -#define EVSYS_DIGFILT2_bp 2 /* Digital Filter bit 2 position. */ - -/* EVSYS.CH1CTRL bit masks and bit positions */ -/* EVSYS_DIGFILT Predefined. */ -/* EVSYS_DIGFILT Predefined. */ - -/* EVSYS.CH2CTRL bit masks and bit positions */ -/* EVSYS_DIGFILT Predefined. */ -/* EVSYS_DIGFILT Predefined. */ - -/* EVSYS.CH3CTRL bit masks and bit positions */ -/* EVSYS_DIGFILT Predefined. */ -/* EVSYS_DIGFILT Predefined. */ - -/* NVM - Non Volatile Memory Controller */ -/* NVM.CMD bit masks and bit positions */ -#define NVM_CMD_gm 0x7F /* Command group mask. */ -#define NVM_CMD_gp 0 /* Command group position. */ -#define NVM_CMD0_bm (1<<0) /* Command bit 0 mask. */ -#define NVM_CMD0_bp 0 /* Command bit 0 position. */ -#define NVM_CMD1_bm (1<<1) /* Command bit 1 mask. */ -#define NVM_CMD1_bp 1 /* Command bit 1 position. */ -#define NVM_CMD2_bm (1<<2) /* Command bit 2 mask. */ -#define NVM_CMD2_bp 2 /* Command bit 2 position. */ -#define NVM_CMD3_bm (1<<3) /* Command bit 3 mask. */ -#define NVM_CMD3_bp 3 /* Command bit 3 position. */ -#define NVM_CMD4_bm (1<<4) /* Command bit 4 mask. */ -#define NVM_CMD4_bp 4 /* Command bit 4 position. */ -#define NVM_CMD5_bm (1<<5) /* Command bit 5 mask. */ -#define NVM_CMD5_bp 5 /* Command bit 5 position. */ -#define NVM_CMD6_bm (1<<6) /* Command bit 6 mask. */ -#define NVM_CMD6_bp 6 /* Command bit 6 position. */ - -/* NVM.CTRLA bit masks and bit positions */ -#define NVM_CMDEX_bm 0x01 /* Command Execute bit mask. */ -#define NVM_CMDEX_bp 0 /* Command Execute bit position. */ - -/* NVM.CTRLB bit masks and bit positions */ -#define NVM_EEMAPEN_bm 0x08 /* EEPROM Mapping Enable bit mask. */ -#define NVM_EEMAPEN_bp 3 /* EEPROM Mapping Enable bit position. */ - -#define NVM_FPRM_bm 0x04 /* Flash Power Reduction Enable bit mask. */ -#define NVM_FPRM_bp 2 /* Flash Power Reduction Enable bit position. */ - -#define NVM_EPRM_bm 0x02 /* EEPROM Power Reduction Enable bit mask. */ -#define NVM_EPRM_bp 1 /* EEPROM Power Reduction Enable bit position. */ - -#define NVM_SPMLOCK_bm 0x01 /* SPM Lock bit mask. */ -#define NVM_SPMLOCK_bp 0 /* SPM Lock bit position. */ - -/* NVM.INTCTRL bit masks and bit positions */ -#define NVM_SPMLVL_gm 0x0C /* SPM Interrupt Level group mask. */ -#define NVM_SPMLVL_gp 2 /* SPM Interrupt Level group position. */ -#define NVM_SPMLVL0_bm (1<<2) /* SPM Interrupt Level bit 0 mask. */ -#define NVM_SPMLVL0_bp 2 /* SPM Interrupt Level bit 0 position. */ -#define NVM_SPMLVL1_bm (1<<3) /* SPM Interrupt Level bit 1 mask. */ -#define NVM_SPMLVL1_bp 3 /* SPM Interrupt Level bit 1 position. */ - -#define NVM_EELVL_gm 0x03 /* EEPROM Interrupt Level group mask. */ -#define NVM_EELVL_gp 0 /* EEPROM Interrupt Level group position. */ -#define NVM_EELVL0_bm (1<<0) /* EEPROM Interrupt Level bit 0 mask. */ -#define NVM_EELVL0_bp 0 /* EEPROM Interrupt Level bit 0 position. */ -#define NVM_EELVL1_bm (1<<1) /* EEPROM Interrupt Level bit 1 mask. */ -#define NVM_EELVL1_bp 1 /* EEPROM Interrupt Level bit 1 position. */ - -/* NVM.STATUS bit masks and bit positions */ -#define NVM_NVMBUSY_bm 0x80 /* Non-volatile Memory Busy bit mask. */ -#define NVM_NVMBUSY_bp 7 /* Non-volatile Memory Busy bit position. */ - -#define NVM_FBUSY_bm 0x40 /* Flash Memory Busy bit mask. */ -#define NVM_FBUSY_bp 6 /* Flash Memory Busy bit position. */ - -#define NVM_EELOAD_bm 0x02 /* EEPROM Page Buffer Active Loading bit mask. */ -#define NVM_EELOAD_bp 1 /* EEPROM Page Buffer Active Loading bit position. */ - -#define NVM_FLOAD_bm 0x01 /* Flash Page Buffer Active Loading bit mask. */ -#define NVM_FLOAD_bp 0 /* Flash Page Buffer Active Loading bit position. */ - -/* NVM.LOCKBITS bit masks and bit positions */ -#define NVM_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ -#define NVM_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ -#define NVM_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ -#define NVM_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ -#define NVM_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ -#define NVM_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ - -#define NVM_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ -#define NVM_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ -#define NVM_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ -#define NVM_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ -#define NVM_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ -#define NVM_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ - -#define NVM_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ -#define NVM_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ -#define NVM_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ -#define NVM_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ -#define NVM_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ -#define NVM_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ - -#define NVM_LB_gm 0x03 /* Lock Bits group mask. */ -#define NVM_LB_gp 0 /* Lock Bits group position. */ -#define NVM_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ -#define NVM_LB0_bp 0 /* Lock Bits bit 0 position. */ -#define NVM_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ -#define NVM_LB1_bp 1 /* Lock Bits bit 1 position. */ - -/* ADC - Analog/Digital Converter */ -/* ADC_CH.CTRL bit masks and bit positions */ -#define ADC_CH_START_bm 0x80 /* Channel Start Conversion bit mask. */ -#define ADC_CH_START_bp 7 /* Channel Start Conversion bit position. */ - -#define ADC_CH_GAIN_gm 0x1C /* Gain Factor group mask. */ -#define ADC_CH_GAIN_gp 2 /* Gain Factor group position. */ -#define ADC_CH_GAIN0_bm (1<<2) /* Gain Factor bit 0 mask. */ -#define ADC_CH_GAIN0_bp 2 /* Gain Factor bit 0 position. */ -#define ADC_CH_GAIN1_bm (1<<3) /* Gain Factor bit 1 mask. */ -#define ADC_CH_GAIN1_bp 3 /* Gain Factor bit 1 position. */ -#define ADC_CH_GAIN2_bm (1<<4) /* Gain Factor bit 2 mask. */ -#define ADC_CH_GAIN2_bp 4 /* Gain Factor bit 2 position. */ - -#define ADC_CH_INPUTMODE_gm 0x03 /* Input Mode Select group mask. */ -#define ADC_CH_INPUTMODE_gp 0 /* Input Mode Select group position. */ -#define ADC_CH_INPUTMODE0_bm (1<<0) /* Input Mode Select bit 0 mask. */ -#define ADC_CH_INPUTMODE0_bp 0 /* Input Mode Select bit 0 position. */ -#define ADC_CH_INPUTMODE1_bm (1<<1) /* Input Mode Select bit 1 mask. */ -#define ADC_CH_INPUTMODE1_bp 1 /* Input Mode Select bit 1 position. */ - -/* ADC_CH.MUXCTRL bit masks and bit positions */ -#define ADC_CH_MUXPOS_gm 0x78 /* MUX selection on Positive ADC input group mask. */ -#define ADC_CH_MUXPOS_gp 3 /* MUX selection on Positive ADC input group position. */ -#define ADC_CH_MUXPOS0_bm (1<<3) /* MUX selection on Positive ADC input bit 0 mask. */ -#define ADC_CH_MUXPOS0_bp 3 /* MUX selection on Positive ADC input bit 0 position. */ -#define ADC_CH_MUXPOS1_bm (1<<4) /* MUX selection on Positive ADC input bit 1 mask. */ -#define ADC_CH_MUXPOS1_bp 4 /* MUX selection on Positive ADC input bit 1 position. */ -#define ADC_CH_MUXPOS2_bm (1<<5) /* MUX selection on Positive ADC input bit 2 mask. */ -#define ADC_CH_MUXPOS2_bp 5 /* MUX selection on Positive ADC input bit 2 position. */ -#define ADC_CH_MUXPOS3_bm (1<<6) /* MUX selection on Positive ADC input bit 3 mask. */ -#define ADC_CH_MUXPOS3_bp 6 /* MUX selection on Positive ADC input bit 3 position. */ - -#define ADC_CH_MUXINT_gm 0x78 /* MUX selection on Internal ADC input group mask. */ -#define ADC_CH_MUXINT_gp 3 /* MUX selection on Internal ADC input group position. */ -#define ADC_CH_MUXINT0_bm (1<<3) /* MUX selection on Internal ADC input bit 0 mask. */ -#define ADC_CH_MUXINT0_bp 3 /* MUX selection on Internal ADC input bit 0 position. */ -#define ADC_CH_MUXINT1_bm (1<<4) /* MUX selection on Internal ADC input bit 1 mask. */ -#define ADC_CH_MUXINT1_bp 4 /* MUX selection on Internal ADC input bit 1 position. */ -#define ADC_CH_MUXINT2_bm (1<<5) /* MUX selection on Internal ADC input bit 2 mask. */ -#define ADC_CH_MUXINT2_bp 5 /* MUX selection on Internal ADC input bit 2 position. */ -#define ADC_CH_MUXINT3_bm (1<<6) /* MUX selection on Internal ADC input bit 3 mask. */ -#define ADC_CH_MUXINT3_bp 6 /* MUX selection on Internal ADC input bit 3 position. */ - -#define ADC_CH_MUXNEG_gm 0x03 /* MUX selection on Negative ADC input group mask. */ -#define ADC_CH_MUXNEG_gp 0 /* MUX selection on Negative ADC input group position. */ -#define ADC_CH_MUXNEG0_bm (1<<0) /* MUX selection on Negative ADC input bit 0 mask. */ -#define ADC_CH_MUXNEG0_bp 0 /* MUX selection on Negative ADC input bit 0 position. */ -#define ADC_CH_MUXNEG1_bm (1<<1) /* MUX selection on Negative ADC input bit 1 mask. */ -#define ADC_CH_MUXNEG1_bp 1 /* MUX selection on Negative ADC input bit 1 position. */ - -/* ADC_CH.INTCTRL bit masks and bit positions */ -#define ADC_CH_INTMODE_gm 0x0C /* Interrupt Mode group mask. */ -#define ADC_CH_INTMODE_gp 2 /* Interrupt Mode group position. */ -#define ADC_CH_INTMODE0_bm (1<<2) /* Interrupt Mode bit 0 mask. */ -#define ADC_CH_INTMODE0_bp 2 /* Interrupt Mode bit 0 position. */ -#define ADC_CH_INTMODE1_bm (1<<3) /* Interrupt Mode bit 1 mask. */ -#define ADC_CH_INTMODE1_bp 3 /* Interrupt Mode bit 1 position. */ - -#define ADC_CH_INTLVL_gm 0x03 /* Interrupt Level group mask. */ -#define ADC_CH_INTLVL_gp 0 /* Interrupt Level group position. */ -#define ADC_CH_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */ -#define ADC_CH_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */ -#define ADC_CH_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ -#define ADC_CH_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */ - -/* ADC_CH.INTFLAGS bit masks and bit positions */ -#define ADC_CH_CHIF_bm 0x01 /* Channel Interrupt Flag bit mask. */ -#define ADC_CH_CHIF_bp 0 /* Channel Interrupt Flag bit position. */ - -/* ADC_CH.SCAN bit masks and bit positions */ -#define ADC_CH_OFFSET_gm 0xF0 /* Positive MUX setting offset group mask. */ -#define ADC_CH_OFFSET_gp 4 /* Positive MUX setting offset group position. */ -#define ADC_CH_OFFSET0_bm (1<<4) /* Positive MUX setting offset bit 0 mask. */ -#define ADC_CH_OFFSET0_bp 4 /* Positive MUX setting offset bit 0 position. */ -#define ADC_CH_OFFSET1_bm (1<<5) /* Positive MUX setting offset bit 1 mask. */ -#define ADC_CH_OFFSET1_bp 5 /* Positive MUX setting offset bit 1 position. */ -#define ADC_CH_OFFSET2_bm (1<<6) /* Positive MUX setting offset bit 2 mask. */ -#define ADC_CH_OFFSET2_bp 6 /* Positive MUX setting offset bit 2 position. */ -#define ADC_CH_OFFSET3_bm (1<<7) /* Positive MUX setting offset bit 3 mask. */ -#define ADC_CH_OFFSET3_bp 7 /* Positive MUX setting offset bit 3 position. */ - -#define ADC_CH_COUNT_gm 0x0F /* Number of Channels included in scan group mask. */ -#define ADC_CH_COUNT_gp 0 /* Number of Channels included in scan group position. */ -#define ADC_CH_COUNT0_bm (1<<0) /* Number of Channels included in scan bit 0 mask. */ -#define ADC_CH_COUNT0_bp 0 /* Number of Channels included in scan bit 0 position. */ -#define ADC_CH_COUNT1_bm (1<<1) /* Number of Channels included in scan bit 1 mask. */ -#define ADC_CH_COUNT1_bp 1 /* Number of Channels included in scan bit 1 position. */ -#define ADC_CH_COUNT2_bm (1<<2) /* Number of Channels included in scan bit 2 mask. */ -#define ADC_CH_COUNT2_bp 2 /* Number of Channels included in scan bit 2 position. */ -#define ADC_CH_COUNT3_bm (1<<3) /* Number of Channels included in scan bit 3 mask. */ -#define ADC_CH_COUNT3_bp 3 /* Number of Channels included in scan bit 3 position. */ - -/* ADC.CTRLA bit masks and bit positions */ -#define ADC_CH0START_bm 0x04 /* Channel 0 Start Conversion bit mask. */ -#define ADC_CH0START_bp 2 /* Channel 0 Start Conversion bit position. */ - -#define ADC_FLUSH_bm 0x02 /* ADC Flush bit mask. */ -#define ADC_FLUSH_bp 1 /* ADC Flush bit position. */ - -#define ADC_ENABLE_bm 0x01 /* Enable ADC bit mask. */ -#define ADC_ENABLE_bp 0 /* Enable ADC bit position. */ - -/* ADC.CTRLB bit masks and bit positions */ -#define ADC_CURRLIMIT_gm 0x60 /* Current limit group mask. */ -#define ADC_CURRLIMIT_gp 5 /* Current limit group position. */ -#define ADC_CURRLIMIT0_bm (1<<5) /* Current limit bit 0 mask. */ -#define ADC_CURRLIMIT0_bp 5 /* Current limit bit 0 position. */ -#define ADC_CURRLIMIT1_bm (1<<6) /* Current limit bit 1 mask. */ -#define ADC_CURRLIMIT1_bp 6 /* Current limit bit 1 position. */ - -#define ADC_CONMODE_bm 0x10 /* Conversion Mode bit mask. */ -#define ADC_CONMODE_bp 4 /* Conversion Mode bit position. */ - -#define ADC_FREERUN_bm 0x08 /* Free Running Mode Enable bit mask. */ -#define ADC_FREERUN_bp 3 /* Free Running Mode Enable bit position. */ - -#define ADC_RESOLUTION_gm 0x06 /* Result Resolution group mask. */ -#define ADC_RESOLUTION_gp 1 /* Result Resolution group position. */ -#define ADC_RESOLUTION0_bm (1<<1) /* Result Resolution bit 0 mask. */ -#define ADC_RESOLUTION0_bp 1 /* Result Resolution bit 0 position. */ -#define ADC_RESOLUTION1_bm (1<<2) /* Result Resolution bit 1 mask. */ -#define ADC_RESOLUTION1_bp 2 /* Result Resolution bit 1 position. */ - -/* ADC.REFCTRL bit masks and bit positions */ -#define ADC_REFSEL_gm 0x70 /* Reference Selection group mask. */ -#define ADC_REFSEL_gp 4 /* Reference Selection group position. */ -#define ADC_REFSEL0_bm (1<<4) /* Reference Selection bit 0 mask. */ -#define ADC_REFSEL0_bp 4 /* Reference Selection bit 0 position. */ -#define ADC_REFSEL1_bm (1<<5) /* Reference Selection bit 1 mask. */ -#define ADC_REFSEL1_bp 5 /* Reference Selection bit 1 position. */ -#define ADC_REFSEL2_bm (1<<6) /* Reference Selection bit 2 mask. */ -#define ADC_REFSEL2_bp 6 /* Reference Selection bit 2 position. */ - -#define ADC_BANDGAP_bm 0x02 /* Bandgap enable bit mask. */ -#define ADC_BANDGAP_bp 1 /* Bandgap enable bit position. */ - -#define ADC_TEMPREF_bm 0x01 /* Temperature Reference Enable bit mask. */ -#define ADC_TEMPREF_bp 0 /* Temperature Reference Enable bit position. */ - -/* ADC.EVCTRL bit masks and bit positions */ -#define ADC_EVSEL_gm 0x18 /* Event Input Select group mask. */ -#define ADC_EVSEL_gp 3 /* Event Input Select group position. */ -#define ADC_EVSEL0_bm (1<<3) /* Event Input Select bit 0 mask. */ -#define ADC_EVSEL0_bp 3 /* Event Input Select bit 0 position. */ -#define ADC_EVSEL1_bm (1<<4) /* Event Input Select bit 1 mask. */ -#define ADC_EVSEL1_bp 4 /* Event Input Select bit 1 position. */ - -#define ADC_EVACT_gm 0x07 /* Event Action Select group mask. */ -#define ADC_EVACT_gp 0 /* Event Action Select group position. */ -#define ADC_EVACT0_bm (1<<0) /* Event Action Select bit 0 mask. */ -#define ADC_EVACT0_bp 0 /* Event Action Select bit 0 position. */ -#define ADC_EVACT1_bm (1<<1) /* Event Action Select bit 1 mask. */ -#define ADC_EVACT1_bp 1 /* Event Action Select bit 1 position. */ -#define ADC_EVACT2_bm (1<<2) /* Event Action Select bit 2 mask. */ -#define ADC_EVACT2_bp 2 /* Event Action Select bit 2 position. */ - -/* ADC.PRESCALER bit masks and bit positions */ -#define ADC_PRESCALER_gm 0x07 /* Clock Prescaler Selection group mask. */ -#define ADC_PRESCALER_gp 0 /* Clock Prescaler Selection group position. */ -#define ADC_PRESCALER0_bm (1<<0) /* Clock Prescaler Selection bit 0 mask. */ -#define ADC_PRESCALER0_bp 0 /* Clock Prescaler Selection bit 0 position. */ -#define ADC_PRESCALER1_bm (1<<1) /* Clock Prescaler Selection bit 1 mask. */ -#define ADC_PRESCALER1_bp 1 /* Clock Prescaler Selection bit 1 position. */ -#define ADC_PRESCALER2_bm (1<<2) /* Clock Prescaler Selection bit 2 mask. */ -#define ADC_PRESCALER2_bp 2 /* Clock Prescaler Selection bit 2 position. */ - -/* ADC.INTFLAGS bit masks and bit positions */ -#define ADC_CH0IF_bm 0x01 /* Channel 0 Interrupt Flag bit mask. */ -#define ADC_CH0IF_bp 0 /* Channel 0 Interrupt Flag bit position. */ - -/* ADC.SAMPCTRL bit masks and bit positions */ -#define ADC_SAMPVAL_gm 0x3F /* Sampling time control register group mask. */ -#define ADC_SAMPVAL_gp 0 /* Sampling time control register group position. */ -#define ADC_SAMPVAL0_bm (1<<0) /* Sampling time control register bit 0 mask. */ -#define ADC_SAMPVAL0_bp 0 /* Sampling time control register bit 0 position. */ -#define ADC_SAMPVAL1_bm (1<<1) /* Sampling time control register bit 1 mask. */ -#define ADC_SAMPVAL1_bp 1 /* Sampling time control register bit 1 position. */ -#define ADC_SAMPVAL2_bm (1<<2) /* Sampling time control register bit 2 mask. */ -#define ADC_SAMPVAL2_bp 2 /* Sampling time control register bit 2 position. */ -#define ADC_SAMPVAL3_bm (1<<3) /* Sampling time control register bit 3 mask. */ -#define ADC_SAMPVAL3_bp 3 /* Sampling time control register bit 3 position. */ -#define ADC_SAMPVAL4_bm (1<<4) /* Sampling time control register bit 4 mask. */ -#define ADC_SAMPVAL4_bp 4 /* Sampling time control register bit 4 position. */ -#define ADC_SAMPVAL5_bm (1<<5) /* Sampling time control register bit 5 mask. */ -#define ADC_SAMPVAL5_bp 5 /* Sampling time control register bit 5 position. */ - -/* AC - Analog Comparator */ -/* AC.AC0CTRL bit masks and bit positions */ -#define AC_INTMODE_gm 0xC0 /* Interrupt Mode group mask. */ -#define AC_INTMODE_gp 6 /* Interrupt Mode group position. */ -#define AC_INTMODE0_bm (1<<6) /* Interrupt Mode bit 0 mask. */ -#define AC_INTMODE0_bp 6 /* Interrupt Mode bit 0 position. */ -#define AC_INTMODE1_bm (1<<7) /* Interrupt Mode bit 1 mask. */ -#define AC_INTMODE1_bp 7 /* Interrupt Mode bit 1 position. */ - -#define AC_INTLVL_gm 0x30 /* Interrupt Level group mask. */ -#define AC_INTLVL_gp 4 /* Interrupt Level group position. */ -#define AC_INTLVL0_bm (1<<4) /* Interrupt Level bit 0 mask. */ -#define AC_INTLVL0_bp 4 /* Interrupt Level bit 0 position. */ -#define AC_INTLVL1_bm (1<<5) /* Interrupt Level bit 1 mask. */ -#define AC_INTLVL1_bp 5 /* Interrupt Level bit 1 position. */ - -#define AC_HYSMODE_gm 0x06 /* Hysteresis Mode group mask. */ -#define AC_HYSMODE_gp 1 /* Hysteresis Mode group position. */ -#define AC_HYSMODE0_bm (1<<1) /* Hysteresis Mode bit 0 mask. */ -#define AC_HYSMODE0_bp 1 /* Hysteresis Mode bit 0 position. */ -#define AC_HYSMODE1_bm (1<<2) /* Hysteresis Mode bit 1 mask. */ -#define AC_HYSMODE1_bp 2 /* Hysteresis Mode bit 1 position. */ - -#define AC_ENABLE_bm 0x01 /* Enable bit mask. */ -#define AC_ENABLE_bp 0 /* Enable bit position. */ - -/* AC.AC1CTRL bit masks and bit positions */ -/* AC_INTMODE Predefined. */ -/* AC_INTMODE Predefined. */ - -/* AC_INTLVL Predefined. */ -/* AC_INTLVL Predefined. */ - -/* AC_HYSMODE Predefined. */ -/* AC_HYSMODE Predefined. */ - -/* AC_ENABLE Predefined. */ -/* AC_ENABLE Predefined. */ - -/* AC.AC0MUXCTRL bit masks and bit positions */ -#define AC_MUXPOS_gm 0x38 /* MUX Positive Input group mask. */ -#define AC_MUXPOS_gp 3 /* MUX Positive Input group position. */ -#define AC_MUXPOS0_bm (1<<3) /* MUX Positive Input bit 0 mask. */ -#define AC_MUXPOS0_bp 3 /* MUX Positive Input bit 0 position. */ -#define AC_MUXPOS1_bm (1<<4) /* MUX Positive Input bit 1 mask. */ -#define AC_MUXPOS1_bp 4 /* MUX Positive Input bit 1 position. */ -#define AC_MUXPOS2_bm (1<<5) /* MUX Positive Input bit 2 mask. */ -#define AC_MUXPOS2_bp 5 /* MUX Positive Input bit 2 position. */ - -#define AC_MUXNEG_gm 0x07 /* MUX Negative Input group mask. */ -#define AC_MUXNEG_gp 0 /* MUX Negative Input group position. */ -#define AC_MUXNEG0_bm (1<<0) /* MUX Negative Input bit 0 mask. */ -#define AC_MUXNEG0_bp 0 /* MUX Negative Input bit 0 position. */ -#define AC_MUXNEG1_bm (1<<1) /* MUX Negative Input bit 1 mask. */ -#define AC_MUXNEG1_bp 1 /* MUX Negative Input bit 1 position. */ -#define AC_MUXNEG2_bm (1<<2) /* MUX Negative Input bit 2 mask. */ -#define AC_MUXNEG2_bp 2 /* MUX Negative Input bit 2 position. */ - -/* AC.AC1MUXCTRL bit masks and bit positions */ -/* AC_MUXPOS Predefined. */ -/* AC_MUXPOS Predefined. */ - -/* AC_MUXNEG Predefined. */ -/* AC_MUXNEG Predefined. */ - -/* AC.CTRLA bit masks and bit positions */ -#define AC_AC1OUT_bm 0x02 /* Analog Comparator 1 Output Enable bit mask. */ -#define AC_AC1OUT_bp 1 /* Analog Comparator 1 Output Enable bit position. */ - -#define AC_AC0OUT_bm 0x01 /* Analog Comparator 0 Output Enable bit mask. */ -#define AC_AC0OUT_bp 0 /* Analog Comparator 0 Output Enable bit position. */ - -/* AC.CTRLB bit masks and bit positions */ -#define AC_SCALEFAC_gm 0x3F /* VCC Voltage Scaler Factor group mask. */ -#define AC_SCALEFAC_gp 0 /* VCC Voltage Scaler Factor group position. */ -#define AC_SCALEFAC0_bm (1<<0) /* VCC Voltage Scaler Factor bit 0 mask. */ -#define AC_SCALEFAC0_bp 0 /* VCC Voltage Scaler Factor bit 0 position. */ -#define AC_SCALEFAC1_bm (1<<1) /* VCC Voltage Scaler Factor bit 1 mask. */ -#define AC_SCALEFAC1_bp 1 /* VCC Voltage Scaler Factor bit 1 position. */ -#define AC_SCALEFAC2_bm (1<<2) /* VCC Voltage Scaler Factor bit 2 mask. */ -#define AC_SCALEFAC2_bp 2 /* VCC Voltage Scaler Factor bit 2 position. */ -#define AC_SCALEFAC3_bm (1<<3) /* VCC Voltage Scaler Factor bit 3 mask. */ -#define AC_SCALEFAC3_bp 3 /* VCC Voltage Scaler Factor bit 3 position. */ -#define AC_SCALEFAC4_bm (1<<4) /* VCC Voltage Scaler Factor bit 4 mask. */ -#define AC_SCALEFAC4_bp 4 /* VCC Voltage Scaler Factor bit 4 position. */ -#define AC_SCALEFAC5_bm (1<<5) /* VCC Voltage Scaler Factor bit 5 mask. */ -#define AC_SCALEFAC5_bp 5 /* VCC Voltage Scaler Factor bit 5 position. */ - -/* AC.WINCTRL bit masks and bit positions */ -#define AC_WEN_bm 0x10 /* Window Mode Enable bit mask. */ -#define AC_WEN_bp 4 /* Window Mode Enable bit position. */ - -#define AC_WINTMODE_gm 0x0C /* Window Interrupt Mode group mask. */ -#define AC_WINTMODE_gp 2 /* Window Interrupt Mode group position. */ -#define AC_WINTMODE0_bm (1<<2) /* Window Interrupt Mode bit 0 mask. */ -#define AC_WINTMODE0_bp 2 /* Window Interrupt Mode bit 0 position. */ -#define AC_WINTMODE1_bm (1<<3) /* Window Interrupt Mode bit 1 mask. */ -#define AC_WINTMODE1_bp 3 /* Window Interrupt Mode bit 1 position. */ - -#define AC_WINTLVL_gm 0x03 /* Window Interrupt Level group mask. */ -#define AC_WINTLVL_gp 0 /* Window Interrupt Level group position. */ -#define AC_WINTLVL0_bm (1<<0) /* Window Interrupt Level bit 0 mask. */ -#define AC_WINTLVL0_bp 0 /* Window Interrupt Level bit 0 position. */ -#define AC_WINTLVL1_bm (1<<1) /* Window Interrupt Level bit 1 mask. */ -#define AC_WINTLVL1_bp 1 /* Window Interrupt Level bit 1 position. */ - -/* AC.STATUS bit masks and bit positions */ -#define AC_WSTATE_gm 0xC0 /* Window Mode State group mask. */ -#define AC_WSTATE_gp 6 /* Window Mode State group position. */ -#define AC_WSTATE0_bm (1<<6) /* Window Mode State bit 0 mask. */ -#define AC_WSTATE0_bp 6 /* Window Mode State bit 0 position. */ -#define AC_WSTATE1_bm (1<<7) /* Window Mode State bit 1 mask. */ -#define AC_WSTATE1_bp 7 /* Window Mode State bit 1 position. */ - -#define AC_AC1STATE_bm 0x20 /* Analog Comparator 1 State bit mask. */ -#define AC_AC1STATE_bp 5 /* Analog Comparator 1 State bit position. */ - -#define AC_AC0STATE_bm 0x10 /* Analog Comparator 0 State bit mask. */ -#define AC_AC0STATE_bp 4 /* Analog Comparator 0 State bit position. */ - -#define AC_WIF_bm 0x04 /* Window Mode Interrupt Flag bit mask. */ -#define AC_WIF_bp 2 /* Window Mode Interrupt Flag bit position. */ - -#define AC_AC1IF_bm 0x02 /* Analog Comparator 1 Interrupt Flag bit mask. */ -#define AC_AC1IF_bp 1 /* Analog Comparator 1 Interrupt Flag bit position. */ - -#define AC_AC0IF_bm 0x01 /* Analog Comparator 0 Interrupt Flag bit mask. */ -#define AC_AC0IF_bp 0 /* Analog Comparator 0 Interrupt Flag bit position. */ - -/* AC.CURRCTRL bit masks and bit positions */ -#define AC_CURREN_bm 0x80 /* Current Source Enable bit mask. */ -#define AC_CURREN_bp 7 /* Current Source Enable bit position. */ - -#define AC_CURRMODE_bm 0x40 /* Current Mode bit mask. */ -#define AC_CURRMODE_bp 6 /* Current Mode bit position. */ - -#define AC_AC1CURR_bm 0x02 /* Analog Comparator 1 current source output bit mask. */ -#define AC_AC1CURR_bp 1 /* Analog Comparator 1 current source output bit position. */ - -#define AC_AC0CURR_bm 0x01 /* Analog Comparator 0 current source output bit mask. */ -#define AC_AC0CURR_bp 0 /* Analog Comparator 0 current source output bit position. */ - -/* AC.CURRCALIB bit masks and bit positions */ -#define AC_CALIB_gm 0x0F /* Current Source Calibration group mask. */ -#define AC_CALIB_gp 0 /* Current Source Calibration group position. */ -#define AC_CALIB0_bm (1<<0) /* Current Source Calibration bit 0 mask. */ -#define AC_CALIB0_bp 0 /* Current Source Calibration bit 0 position. */ -#define AC_CALIB1_bm (1<<1) /* Current Source Calibration bit 1 mask. */ -#define AC_CALIB1_bp 1 /* Current Source Calibration bit 1 position. */ -#define AC_CALIB2_bm (1<<2) /* Current Source Calibration bit 2 mask. */ -#define AC_CALIB2_bp 2 /* Current Source Calibration bit 2 position. */ -#define AC_CALIB3_bm (1<<3) /* Current Source Calibration bit 3 mask. */ -#define AC_CALIB3_bp 3 /* Current Source Calibration bit 3 position. */ - -/* RTC - Real-Time Counter */ -/* RTC.CTRL bit masks and bit positions */ -#define RTC_PRESCALER_gm 0x07 /* Prescaling Factor group mask. */ -#define RTC_PRESCALER_gp 0 /* Prescaling Factor group position. */ -#define RTC_PRESCALER0_bm (1<<0) /* Prescaling Factor bit 0 mask. */ -#define RTC_PRESCALER0_bp 0 /* Prescaling Factor bit 0 position. */ -#define RTC_PRESCALER1_bm (1<<1) /* Prescaling Factor bit 1 mask. */ -#define RTC_PRESCALER1_bp 1 /* Prescaling Factor bit 1 position. */ -#define RTC_PRESCALER2_bm (1<<2) /* Prescaling Factor bit 2 mask. */ -#define RTC_PRESCALER2_bp 2 /* Prescaling Factor bit 2 position. */ - -/* RTC.STATUS bit masks and bit positions */ -#define RTC_SYNCBUSY_bm 0x01 /* Synchronization Busy Flag bit mask. */ -#define RTC_SYNCBUSY_bp 0 /* Synchronization Busy Flag bit position. */ - -/* RTC.INTCTRL bit masks and bit positions */ -#define RTC_COMPINTLVL_gm 0x0C /* Compare Match Interrupt Level group mask. */ -#define RTC_COMPINTLVL_gp 2 /* Compare Match Interrupt Level group position. */ -#define RTC_COMPINTLVL0_bm (1<<2) /* Compare Match Interrupt Level bit 0 mask. */ -#define RTC_COMPINTLVL0_bp 2 /* Compare Match Interrupt Level bit 0 position. */ -#define RTC_COMPINTLVL1_bm (1<<3) /* Compare Match Interrupt Level bit 1 mask. */ -#define RTC_COMPINTLVL1_bp 3 /* Compare Match Interrupt Level bit 1 position. */ - -#define RTC_OVFINTLVL_gm 0x03 /* Overflow Interrupt Level group mask. */ -#define RTC_OVFINTLVL_gp 0 /* Overflow Interrupt Level group position. */ -#define RTC_OVFINTLVL0_bm (1<<0) /* Overflow Interrupt Level bit 0 mask. */ -#define RTC_OVFINTLVL0_bp 0 /* Overflow Interrupt Level bit 0 position. */ -#define RTC_OVFINTLVL1_bm (1<<1) /* Overflow Interrupt Level bit 1 mask. */ -#define RTC_OVFINTLVL1_bp 1 /* Overflow Interrupt Level bit 1 position. */ - -/* RTC.INTFLAGS bit masks and bit positions */ -#define RTC_COMPIF_bm 0x02 /* Compare Match Interrupt Flag bit mask. */ -#define RTC_COMPIF_bp 1 /* Compare Match Interrupt Flag bit position. */ - -#define RTC_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ -#define RTC_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ - -/* TWI - Two-Wire Interface */ -/* TWI_MASTER.CTRLA bit masks and bit positions */ -#define TWI_MASTER_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ -#define TWI_MASTER_INTLVL_gp 6 /* Interrupt Level group position. */ -#define TWI_MASTER_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ -#define TWI_MASTER_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ -#define TWI_MASTER_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ -#define TWI_MASTER_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ - -#define TWI_MASTER_RIEN_bm 0x20 /* Read Interrupt Enable bit mask. */ -#define TWI_MASTER_RIEN_bp 5 /* Read Interrupt Enable bit position. */ - -#define TWI_MASTER_WIEN_bm 0x10 /* Write Interrupt Enable bit mask. */ -#define TWI_MASTER_WIEN_bp 4 /* Write Interrupt Enable bit position. */ - -#define TWI_MASTER_ENABLE_bm 0x08 /* Enable TWI Master bit mask. */ -#define TWI_MASTER_ENABLE_bp 3 /* Enable TWI Master bit position. */ - -/* TWI_MASTER.CTRLB bit masks and bit positions */ -#define TWI_MASTER_TIMEOUT_gm 0x0C /* Inactive Bus Timeout group mask. */ -#define TWI_MASTER_TIMEOUT_gp 2 /* Inactive Bus Timeout group position. */ -#define TWI_MASTER_TIMEOUT0_bm (1<<2) /* Inactive Bus Timeout bit 0 mask. */ -#define TWI_MASTER_TIMEOUT0_bp 2 /* Inactive Bus Timeout bit 0 position. */ -#define TWI_MASTER_TIMEOUT1_bm (1<<3) /* Inactive Bus Timeout bit 1 mask. */ -#define TWI_MASTER_TIMEOUT1_bp 3 /* Inactive Bus Timeout bit 1 position. */ - -#define TWI_MASTER_QCEN_bm 0x02 /* Quick Command Enable bit mask. */ -#define TWI_MASTER_QCEN_bp 1 /* Quick Command Enable bit position. */ - -#define TWI_MASTER_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ -#define TWI_MASTER_SMEN_bp 0 /* Smart Mode Enable bit position. */ - -/* TWI_MASTER.CTRLC bit masks and bit positions */ -#define TWI_MASTER_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ -#define TWI_MASTER_ACKACT_bp 2 /* Acknowledge Action bit position. */ - -#define TWI_MASTER_CMD_gm 0x03 /* Command group mask. */ -#define TWI_MASTER_CMD_gp 0 /* Command group position. */ -#define TWI_MASTER_CMD0_bm (1<<0) /* Command bit 0 mask. */ -#define TWI_MASTER_CMD0_bp 0 /* Command bit 0 position. */ -#define TWI_MASTER_CMD1_bm (1<<1) /* Command bit 1 mask. */ -#define TWI_MASTER_CMD1_bp 1 /* Command bit 1 position. */ - -/* TWI_MASTER.STATUS bit masks and bit positions */ -#define TWI_MASTER_RIF_bm 0x80 /* Read Interrupt Flag bit mask. */ -#define TWI_MASTER_RIF_bp 7 /* Read Interrupt Flag bit position. */ - -#define TWI_MASTER_WIF_bm 0x40 /* Write Interrupt Flag bit mask. */ -#define TWI_MASTER_WIF_bp 6 /* Write Interrupt Flag bit position. */ - -#define TWI_MASTER_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ -#define TWI_MASTER_CLKHOLD_bp 5 /* Clock Hold bit position. */ - -#define TWI_MASTER_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ -#define TWI_MASTER_RXACK_bp 4 /* Received Acknowledge bit position. */ - -#define TWI_MASTER_ARBLOST_bm 0x08 /* Arbitration Lost bit mask. */ -#define TWI_MASTER_ARBLOST_bp 3 /* Arbitration Lost bit position. */ - -#define TWI_MASTER_BUSERR_bm 0x04 /* Bus Error bit mask. */ -#define TWI_MASTER_BUSERR_bp 2 /* Bus Error bit position. */ - -#define TWI_MASTER_BUSSTATE_gm 0x03 /* Bus State group mask. */ -#define TWI_MASTER_BUSSTATE_gp 0 /* Bus State group position. */ -#define TWI_MASTER_BUSSTATE0_bm (1<<0) /* Bus State bit 0 mask. */ -#define TWI_MASTER_BUSSTATE0_bp 0 /* Bus State bit 0 position. */ -#define TWI_MASTER_BUSSTATE1_bm (1<<1) /* Bus State bit 1 mask. */ -#define TWI_MASTER_BUSSTATE1_bp 1 /* Bus State bit 1 position. */ - -/* TWI_SLAVE.CTRLA bit masks and bit positions */ -#define TWI_SLAVE_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ -#define TWI_SLAVE_INTLVL_gp 6 /* Interrupt Level group position. */ -#define TWI_SLAVE_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ -#define TWI_SLAVE_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ -#define TWI_SLAVE_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ -#define TWI_SLAVE_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ - -#define TWI_SLAVE_DIEN_bm 0x20 /* Data Interrupt Enable bit mask. */ -#define TWI_SLAVE_DIEN_bp 5 /* Data Interrupt Enable bit position. */ - -#define TWI_SLAVE_APIEN_bm 0x10 /* Address/Stop Interrupt Enable bit mask. */ -#define TWI_SLAVE_APIEN_bp 4 /* Address/Stop Interrupt Enable bit position. */ - -#define TWI_SLAVE_ENABLE_bm 0x08 /* Enable TWI Slave bit mask. */ -#define TWI_SLAVE_ENABLE_bp 3 /* Enable TWI Slave bit position. */ - -#define TWI_SLAVE_PIEN_bm 0x04 /* Stop Interrupt Enable bit mask. */ -#define TWI_SLAVE_PIEN_bp 2 /* Stop Interrupt Enable bit position. */ - -#define TWI_SLAVE_PMEN_bm 0x02 /* Promiscuous Mode Enable bit mask. */ -#define TWI_SLAVE_PMEN_bp 1 /* Promiscuous Mode Enable bit position. */ - -#define TWI_SLAVE_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ -#define TWI_SLAVE_SMEN_bp 0 /* Smart Mode Enable bit position. */ - -/* TWI_SLAVE.CTRLB bit masks and bit positions */ -#define TWI_SLAVE_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ -#define TWI_SLAVE_ACKACT_bp 2 /* Acknowledge Action bit position. */ - -#define TWI_SLAVE_CMD_gm 0x03 /* Command group mask. */ -#define TWI_SLAVE_CMD_gp 0 /* Command group position. */ -#define TWI_SLAVE_CMD0_bm (1<<0) /* Command bit 0 mask. */ -#define TWI_SLAVE_CMD0_bp 0 /* Command bit 0 position. */ -#define TWI_SLAVE_CMD1_bm (1<<1) /* Command bit 1 mask. */ -#define TWI_SLAVE_CMD1_bp 1 /* Command bit 1 position. */ - -/* TWI_SLAVE.STATUS bit masks and bit positions */ -#define TWI_SLAVE_DIF_bm 0x80 /* Data Interrupt Flag bit mask. */ -#define TWI_SLAVE_DIF_bp 7 /* Data Interrupt Flag bit position. */ - -#define TWI_SLAVE_APIF_bm 0x40 /* Address/Stop Interrupt Flag bit mask. */ -#define TWI_SLAVE_APIF_bp 6 /* Address/Stop Interrupt Flag bit position. */ - -#define TWI_SLAVE_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ -#define TWI_SLAVE_CLKHOLD_bp 5 /* Clock Hold bit position. */ - -#define TWI_SLAVE_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ -#define TWI_SLAVE_RXACK_bp 4 /* Received Acknowledge bit position. */ - -#define TWI_SLAVE_COLL_bm 0x08 /* Collision bit mask. */ -#define TWI_SLAVE_COLL_bp 3 /* Collision bit position. */ - -#define TWI_SLAVE_BUSERR_bm 0x04 /* Bus Error bit mask. */ -#define TWI_SLAVE_BUSERR_bp 2 /* Bus Error bit position. */ - -#define TWI_SLAVE_DIR_bm 0x02 /* Read/Write Direction bit mask. */ -#define TWI_SLAVE_DIR_bp 1 /* Read/Write Direction bit position. */ - -#define TWI_SLAVE_AP_bm 0x01 /* Slave Address or Stop bit mask. */ -#define TWI_SLAVE_AP_bp 0 /* Slave Address or Stop bit position. */ - -/* TWI_SLAVE.ADDRMASK bit masks and bit positions */ -#define TWI_SLAVE_ADDRMASK_gm 0xFE /* Address Mask group mask. */ -#define TWI_SLAVE_ADDRMASK_gp 1 /* Address Mask group position. */ -#define TWI_SLAVE_ADDRMASK0_bm (1<<1) /* Address Mask bit 0 mask. */ -#define TWI_SLAVE_ADDRMASK0_bp 1 /* Address Mask bit 0 position. */ -#define TWI_SLAVE_ADDRMASK1_bm (1<<2) /* Address Mask bit 1 mask. */ -#define TWI_SLAVE_ADDRMASK1_bp 2 /* Address Mask bit 1 position. */ -#define TWI_SLAVE_ADDRMASK2_bm (1<<3) /* Address Mask bit 2 mask. */ -#define TWI_SLAVE_ADDRMASK2_bp 3 /* Address Mask bit 2 position. */ -#define TWI_SLAVE_ADDRMASK3_bm (1<<4) /* Address Mask bit 3 mask. */ -#define TWI_SLAVE_ADDRMASK3_bp 4 /* Address Mask bit 3 position. */ -#define TWI_SLAVE_ADDRMASK4_bm (1<<5) /* Address Mask bit 4 mask. */ -#define TWI_SLAVE_ADDRMASK4_bp 5 /* Address Mask bit 4 position. */ -#define TWI_SLAVE_ADDRMASK5_bm (1<<6) /* Address Mask bit 5 mask. */ -#define TWI_SLAVE_ADDRMASK5_bp 6 /* Address Mask bit 5 position. */ -#define TWI_SLAVE_ADDRMASK6_bm (1<<7) /* Address Mask bit 6 mask. */ -#define TWI_SLAVE_ADDRMASK6_bp 7 /* Address Mask bit 6 position. */ - -#define TWI_SLAVE_ADDREN_bm 0x01 /* Address Enable bit mask. */ -#define TWI_SLAVE_ADDREN_bp 0 /* Address Enable bit position. */ - -/* TWI.CTRL bit masks and bit positions */ -#define TWI_SDAHOLD_gm 0x06 /* SDA Hold Time Enable group mask. */ -#define TWI_SDAHOLD_gp 1 /* SDA Hold Time Enable group position. */ -#define TWI_SDAHOLD0_bm (1<<1) /* SDA Hold Time Enable bit 0 mask. */ -#define TWI_SDAHOLD0_bp 1 /* SDA Hold Time Enable bit 0 position. */ -#define TWI_SDAHOLD1_bm (1<<2) /* SDA Hold Time Enable bit 1 mask. */ -#define TWI_SDAHOLD1_bp 2 /* SDA Hold Time Enable bit 1 position. */ - -#define TWI_EDIEN_bm 0x01 /* External Driver Interface Enable bit mask. */ -#define TWI_EDIEN_bp 0 /* External Driver Interface Enable bit position. */ - -/* USB - USB */ -/* USB_EP.STATUS bit masks and bit positions */ -#define USB_EP_STALLF_bm 0x80 /* Endpoint Stall Flag bit mask. */ -#define USB_EP_STALLF_bp 7 /* Endpoint Stall Flag bit position. */ - -#define USB_EP_CRC_bm 0x80 /* CRC Error Flag bit mask. */ -#define USB_EP_CRC_bp 7 /* CRC Error Flag bit position. */ - -#define USB_EP_UNF_bm 0x40 /* Underflow Enpoint FLag bit mask. */ -#define USB_EP_UNF_bp 6 /* Underflow Enpoint FLag bit position. */ - -#define USB_EP_OVF_bm 0x40 /* Overflow Enpoint Flag for Output Endpoints bit mask. */ -#define USB_EP_OVF_bp 6 /* Overflow Enpoint Flag for Output Endpoints bit position. */ - -#define USB_EP_TRNCOMPL0_bm 0x20 /* Transaction Complete 0 Flag bit mask. */ -#define USB_EP_TRNCOMPL0_bp 5 /* Transaction Complete 0 Flag bit position. */ - -#define USB_EP_TRNCOMPL1_bm 0x10 /* Transaction Complete 1 Flag bit mask. */ -#define USB_EP_TRNCOMPL1_bp 4 /* Transaction Complete 1 Flag bit position. */ - -#define USB_EP_SETUP_bm 0x10 /* SETUP Transaction Complete Flag bit mask. */ -#define USB_EP_SETUP_bp 4 /* SETUP Transaction Complete Flag bit position. */ - -#define USB_EP_BANK_bm 0x08 /* Bank Select bit mask. */ -#define USB_EP_BANK_bp 3 /* Bank Select bit position. */ - -#define USB_EP_BUSNACK1_bm 0x04 /* Data Buffer 1 Not Acknowledge bit mask. */ -#define USB_EP_BUSNACK1_bp 2 /* Data Buffer 1 Not Acknowledge bit position. */ - -#define USB_EP_BUSNACK0_bm 0x02 /* Data Buffer 0 Not Acknowledge bit mask. */ -#define USB_EP_BUSNACK0_bp 1 /* Data Buffer 0 Not Acknowledge bit position. */ - -#define USB_EP_TOGGLE_bm 0x01 /* Data Toggle bit mask. */ -#define USB_EP_TOGGLE_bp 0 /* Data Toggle bit position. */ - -/* USB_EP.CTRL bit masks and bit positions */ -#define USB_EP_TYPE_gm 0xC0 /* Endpoint Type group mask. */ -#define USB_EP_TYPE_gp 6 /* Endpoint Type group position. */ -#define USB_EP_TYPE0_bm (1<<6) /* Endpoint Type bit 0 mask. */ -#define USB_EP_TYPE0_bp 6 /* Endpoint Type bit 0 position. */ -#define USB_EP_TYPE1_bm (1<<7) /* Endpoint Type bit 1 mask. */ -#define USB_EP_TYPE1_bp 7 /* Endpoint Type bit 1 position. */ - -#define USB_EP_MULTIPKT_bm 0x20 /* Multi Packet Transfer Enable bit mask. */ -#define USB_EP_MULTIPKT_bp 5 /* Multi Packet Transfer Enable bit position. */ - -#define USB_EP_PINGPONG_bm 0x10 /* Ping-Pong Enable bit mask. */ -#define USB_EP_PINGPONG_bp 4 /* Ping-Pong Enable bit position. */ - -#define USB_EP_INTDSBL_bm 0x08 /* Interrupt Disable bit mask. */ -#define USB_EP_INTDSBL_bp 3 /* Interrupt Disable bit position. */ - -#define USB_EP_STALL_bm 0x04 /* Data Stall bit mask. */ -#define USB_EP_STALL_bp 2 /* Data Stall bit position. */ - -#define USB_EP_BUFSIZE_gm 0x07 /* Data Buffer Size group mask. */ -#define USB_EP_BUFSIZE_gp 0 /* Data Buffer Size group position. */ -#define USB_EP_BUFSIZE0_bm (1<<0) /* Data Buffer Size bit 0 mask. */ -#define USB_EP_BUFSIZE0_bp 0 /* Data Buffer Size bit 0 position. */ -#define USB_EP_BUFSIZE1_bm (1<<1) /* Data Buffer Size bit 1 mask. */ -#define USB_EP_BUFSIZE1_bp 1 /* Data Buffer Size bit 1 position. */ -#define USB_EP_BUFSIZE2_bm (1<<2) /* Data Buffer Size bit 2 mask. */ -#define USB_EP_BUFSIZE2_bp 2 /* Data Buffer Size bit 2 position. */ - -/* USB_EP.CNT bit masks and bit positions */ -#define USB_EP_ZLP_bm 0x8000 /* Zero Length Packet bit mask. */ -#define USB_EP_ZLP_bp 15 /* Zero Length Packet bit position. */ - -/* USB.CTRLA bit masks and bit positions */ -#define USB_ENABLE_bm 0x80 /* USB Enable bit mask. */ -#define USB_ENABLE_bp 7 /* USB Enable bit position. */ - -#define USB_SPEED_bm 0x40 /* Speed Select bit mask. */ -#define USB_SPEED_bp 6 /* Speed Select bit position. */ - -#define USB_FIFOEN_bm 0x20 /* USB FIFO Enable bit mask. */ -#define USB_FIFOEN_bp 5 /* USB FIFO Enable bit position. */ - -#define USB_STFRNUM_bm 0x10 /* Store Frame Number Enable bit mask. */ -#define USB_STFRNUM_bp 4 /* Store Frame Number Enable bit position. */ - -#define USB_MAXEP_gm 0x0F /* Maximum Endpoint Addresses group mask. */ -#define USB_MAXEP_gp 0 /* Maximum Endpoint Addresses group position. */ -#define USB_MAXEP0_bm (1<<0) /* Maximum Endpoint Addresses bit 0 mask. */ -#define USB_MAXEP0_bp 0 /* Maximum Endpoint Addresses bit 0 position. */ -#define USB_MAXEP1_bm (1<<1) /* Maximum Endpoint Addresses bit 1 mask. */ -#define USB_MAXEP1_bp 1 /* Maximum Endpoint Addresses bit 1 position. */ -#define USB_MAXEP2_bm (1<<2) /* Maximum Endpoint Addresses bit 2 mask. */ -#define USB_MAXEP2_bp 2 /* Maximum Endpoint Addresses bit 2 position. */ -#define USB_MAXEP3_bm (1<<3) /* Maximum Endpoint Addresses bit 3 mask. */ -#define USB_MAXEP3_bp 3 /* Maximum Endpoint Addresses bit 3 position. */ - -/* USB.CTRLB bit masks and bit positions */ -#define USB_PULLRST_bm 0x10 /* Pull during Reset bit mask. */ -#define USB_PULLRST_bp 4 /* Pull during Reset bit position. */ - -#define USB_RWAKEUP_bm 0x04 /* Remote Wake-up bit mask. */ -#define USB_RWAKEUP_bp 2 /* Remote Wake-up bit position. */ - -#define USB_GNACK_bm 0x02 /* Global NACK bit mask. */ -#define USB_GNACK_bp 1 /* Global NACK bit position. */ - -#define USB_ATTACH_bm 0x01 /* Attach bit mask. */ -#define USB_ATTACH_bp 0 /* Attach bit position. */ - -/* USB.STATUS bit masks and bit positions */ -#define USB_URESUME_bm 0x08 /* Upstream Resume bit mask. */ -#define USB_URESUME_bp 3 /* Upstream Resume bit position. */ - -#define USB_RESUME_bm 0x04 /* Resume bit mask. */ -#define USB_RESUME_bp 2 /* Resume bit position. */ - -#define USB_SUSPEND_bm 0x02 /* Bus Suspended bit mask. */ -#define USB_SUSPEND_bp 1 /* Bus Suspended bit position. */ - -#define USB_BUSRST_bm 0x01 /* Bus Reset bit mask. */ -#define USB_BUSRST_bp 0 /* Bus Reset bit position. */ - -/* USB.ADDR bit masks and bit positions */ -#define USB_ADDR_gm 0x7F /* Device Address group mask. */ -#define USB_ADDR_gp 0 /* Device Address group position. */ -#define USB_ADDR0_bm (1<<0) /* Device Address bit 0 mask. */ -#define USB_ADDR0_bp 0 /* Device Address bit 0 position. */ -#define USB_ADDR1_bm (1<<1) /* Device Address bit 1 mask. */ -#define USB_ADDR1_bp 1 /* Device Address bit 1 position. */ -#define USB_ADDR2_bm (1<<2) /* Device Address bit 2 mask. */ -#define USB_ADDR2_bp 2 /* Device Address bit 2 position. */ -#define USB_ADDR3_bm (1<<3) /* Device Address bit 3 mask. */ -#define USB_ADDR3_bp 3 /* Device Address bit 3 position. */ -#define USB_ADDR4_bm (1<<4) /* Device Address bit 4 mask. */ -#define USB_ADDR4_bp 4 /* Device Address bit 4 position. */ -#define USB_ADDR5_bm (1<<5) /* Device Address bit 5 mask. */ -#define USB_ADDR5_bp 5 /* Device Address bit 5 position. */ -#define USB_ADDR6_bm (1<<6) /* Device Address bit 6 mask. */ -#define USB_ADDR6_bp 6 /* Device Address bit 6 position. */ - -/* USB.FIFOWP bit masks and bit positions */ -#define USB_FIFOWP_gm 0x1F /* FIFO Write Pointer group mask. */ -#define USB_FIFOWP_gp 0 /* FIFO Write Pointer group position. */ -#define USB_FIFOWP0_bm (1<<0) /* FIFO Write Pointer bit 0 mask. */ -#define USB_FIFOWP0_bp 0 /* FIFO Write Pointer bit 0 position. */ -#define USB_FIFOWP1_bm (1<<1) /* FIFO Write Pointer bit 1 mask. */ -#define USB_FIFOWP1_bp 1 /* FIFO Write Pointer bit 1 position. */ -#define USB_FIFOWP2_bm (1<<2) /* FIFO Write Pointer bit 2 mask. */ -#define USB_FIFOWP2_bp 2 /* FIFO Write Pointer bit 2 position. */ -#define USB_FIFOWP3_bm (1<<3) /* FIFO Write Pointer bit 3 mask. */ -#define USB_FIFOWP3_bp 3 /* FIFO Write Pointer bit 3 position. */ -#define USB_FIFOWP4_bm (1<<4) /* FIFO Write Pointer bit 4 mask. */ -#define USB_FIFOWP4_bp 4 /* FIFO Write Pointer bit 4 position. */ - -/* USB.FIFORP bit masks and bit positions */ -#define USB_FIFORP_gm 0x1F /* FIFO Read Pointer group mask. */ -#define USB_FIFORP_gp 0 /* FIFO Read Pointer group position. */ -#define USB_FIFORP0_bm (1<<0) /* FIFO Read Pointer bit 0 mask. */ -#define USB_FIFORP0_bp 0 /* FIFO Read Pointer bit 0 position. */ -#define USB_FIFORP1_bm (1<<1) /* FIFO Read Pointer bit 1 mask. */ -#define USB_FIFORP1_bp 1 /* FIFO Read Pointer bit 1 position. */ -#define USB_FIFORP2_bm (1<<2) /* FIFO Read Pointer bit 2 mask. */ -#define USB_FIFORP2_bp 2 /* FIFO Read Pointer bit 2 position. */ -#define USB_FIFORP3_bm (1<<3) /* FIFO Read Pointer bit 3 mask. */ -#define USB_FIFORP3_bp 3 /* FIFO Read Pointer bit 3 position. */ -#define USB_FIFORP4_bm (1<<4) /* FIFO Read Pointer bit 4 mask. */ -#define USB_FIFORP4_bp 4 /* FIFO Read Pointer bit 4 position. */ - -/* USB.INTCTRLA bit masks and bit positions */ -#define USB_SOFIE_bm 0x80 /* Start Of Frame Interrupt Enable bit mask. */ -#define USB_SOFIE_bp 7 /* Start Of Frame Interrupt Enable bit position. */ - -#define USB_BUSEVIE_bm 0x40 /* Bus Event Interrupt Enable bit mask. */ -#define USB_BUSEVIE_bp 6 /* Bus Event Interrupt Enable bit position. */ - -#define USB_BUSERRIE_bm 0x20 /* Bus Error Interrupt Enable bit mask. */ -#define USB_BUSERRIE_bp 5 /* Bus Error Interrupt Enable bit position. */ - -#define USB_STALLIE_bm 0x10 /* STALL Interrupt Enable bit mask. */ -#define USB_STALLIE_bp 4 /* STALL Interrupt Enable bit position. */ - -#define USB_INTLVL_gm 0x03 /* Interrupt Level group mask. */ -#define USB_INTLVL_gp 0 /* Interrupt Level group position. */ -#define USB_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */ -#define USB_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */ -#define USB_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ -#define USB_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */ - -/* USB.INTCTRLB bit masks and bit positions */ -#define USB_TRNIE_bm 0x02 /* Transaction Complete Interrupt Enable bit mask. */ -#define USB_TRNIE_bp 1 /* Transaction Complete Interrupt Enable bit position. */ - -#define USB_SETUPIE_bm 0x01 /* SETUP Transaction Complete Interrupt Enable bit mask. */ -#define USB_SETUPIE_bp 0 /* SETUP Transaction Complete Interrupt Enable bit position. */ - -/* USB.INTFLAGSACLR bit masks and bit positions */ -#define USB_SOFIF_bm 0x80 /* Start Of Frame Interrupt Flag bit mask. */ -#define USB_SOFIF_bp 7 /* Start Of Frame Interrupt Flag bit position. */ - -#define USB_SUSPENDIF_bm 0x40 /* Suspend Interrupt Flag bit mask. */ -#define USB_SUSPENDIF_bp 6 /* Suspend Interrupt Flag bit position. */ - -#define USB_RESUMEIF_bm 0x20 /* Resume Interrupt Flag bit mask. */ -#define USB_RESUMEIF_bp 5 /* Resume Interrupt Flag bit position. */ - -#define USB_RSTIF_bm 0x10 /* Reset Interrupt Flag bit mask. */ -#define USB_RSTIF_bp 4 /* Reset Interrupt Flag bit position. */ - -#define USB_CRCIF_bm 0x08 /* Isochronous CRC Error Interrupt Flag bit mask. */ -#define USB_CRCIF_bp 3 /* Isochronous CRC Error Interrupt Flag bit position. */ - -#define USB_UNFIF_bm 0x04 /* Underflow Interrupt Flag bit mask. */ -#define USB_UNFIF_bp 2 /* Underflow Interrupt Flag bit position. */ - -#define USB_OVFIF_bm 0x02 /* Overflow Interrupt Flag bit mask. */ -#define USB_OVFIF_bp 1 /* Overflow Interrupt Flag bit position. */ - -#define USB_STALLIF_bm 0x01 /* STALL Interrupt Flag bit mask. */ -#define USB_STALLIF_bp 0 /* STALL Interrupt Flag bit position. */ - -/* USB.INTFLAGSASET bit masks and bit positions */ -/* USB_SOFIF Predefined. */ -/* USB_SOFIF Predefined. */ - -/* USB_SUSPENDIF Predefined. */ -/* USB_SUSPENDIF Predefined. */ - -/* USB_RESUMEIF Predefined. */ -/* USB_RESUMEIF Predefined. */ - -/* USB_RSTIF Predefined. */ -/* USB_RSTIF Predefined. */ - -/* USB_CRCIF Predefined. */ -/* USB_CRCIF Predefined. */ - -/* USB_UNFIF Predefined. */ -/* USB_UNFIF Predefined. */ - -/* USB_OVFIF Predefined. */ -/* USB_OVFIF Predefined. */ - -/* USB_STALLIF Predefined. */ -/* USB_STALLIF Predefined. */ - -/* USB.INTFLAGSBCLR bit masks and bit positions */ -#define USB_TRNIF_bm 0x02 /* Transaction Complete Interrupt Flag bit mask. */ -#define USB_TRNIF_bp 1 /* Transaction Complete Interrupt Flag bit position. */ - -#define USB_SETUPIF_bm 0x01 /* SETUP Transaction Complete Interrupt Flag bit mask. */ -#define USB_SETUPIF_bp 0 /* SETUP Transaction Complete Interrupt Flag bit position. */ - -/* USB.INTFLAGSBSET bit masks and bit positions */ -/* USB_TRNIF Predefined. */ -/* USB_TRNIF Predefined. */ - -/* USB_SETUPIF Predefined. */ -/* USB_SETUPIF Predefined. */ - -/* PORT - I/O Port Configuration */ -/* PORT.INTCTRL bit masks and bit positions */ -#define PORT_INT1LVL_gm 0x0C /* Port Interrupt 1 Level group mask. */ -#define PORT_INT1LVL_gp 2 /* Port Interrupt 1 Level group position. */ -#define PORT_INT1LVL0_bm (1<<2) /* Port Interrupt 1 Level bit 0 mask. */ -#define PORT_INT1LVL0_bp 2 /* Port Interrupt 1 Level bit 0 position. */ -#define PORT_INT1LVL1_bm (1<<3) /* Port Interrupt 1 Level bit 1 mask. */ -#define PORT_INT1LVL1_bp 3 /* Port Interrupt 1 Level bit 1 position. */ - -#define PORT_INT0LVL_gm 0x03 /* Port Interrupt 0 Level group mask. */ -#define PORT_INT0LVL_gp 0 /* Port Interrupt 0 Level group position. */ -#define PORT_INT0LVL0_bm (1<<0) /* Port Interrupt 0 Level bit 0 mask. */ -#define PORT_INT0LVL0_bp 0 /* Port Interrupt 0 Level bit 0 position. */ -#define PORT_INT0LVL1_bm (1<<1) /* Port Interrupt 0 Level bit 1 mask. */ -#define PORT_INT0LVL1_bp 1 /* Port Interrupt 0 Level bit 1 position. */ - -/* PORT.INTFLAGS bit masks and bit positions */ -#define PORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ -#define PORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ - -#define PORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ -#define PORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ - -/* PORT.REMAP bit masks and bit positions */ -#define PORT_SPI_bm 0x20 /* SPI bit mask. */ -#define PORT_SPI_bp 5 /* SPI bit position. */ - -#define PORT_USART0_bm 0x10 /* USART0 bit mask. */ -#define PORT_USART0_bp 4 /* USART0 bit position. */ - -#define PORT_TC0D_bm 0x08 /* Timer/Counter 0 Output Compare D bit mask. */ -#define PORT_TC0D_bp 3 /* Timer/Counter 0 Output Compare D bit position. */ - -#define PORT_TC0C_bm 0x04 /* Timer/Counter 0 Output Compare C bit mask. */ -#define PORT_TC0C_bp 2 /* Timer/Counter 0 Output Compare C bit position. */ - -#define PORT_TC0B_bm 0x02 /* Timer/Counter 0 Output Compare B bit mask. */ -#define PORT_TC0B_bp 1 /* Timer/Counter 0 Output Compare B bit position. */ - -#define PORT_TC0A_bm 0x01 /* Timer/Counter 0 Output Compare A bit mask. */ -#define PORT_TC0A_bp 0 /* Timer/Counter 0 Output Compare A bit position. */ - -/* PORT.PIN0CTRL bit masks and bit positions */ -#define PORT_SRLEN_bm 0x80 /* Slew Rate Enable bit mask. */ -#define PORT_SRLEN_bp 7 /* Slew Rate Enable bit position. */ - -#define PORT_INVEN_bm 0x40 /* Inverted I/O Enable bit mask. */ -#define PORT_INVEN_bp 6 /* Inverted I/O Enable bit position. */ - -#define PORT_OPC_gm 0x38 /* Output/Pull Configuration group mask. */ -#define PORT_OPC_gp 3 /* Output/Pull Configuration group position. */ -#define PORT_OPC0_bm (1<<3) /* Output/Pull Configuration bit 0 mask. */ -#define PORT_OPC0_bp 3 /* Output/Pull Configuration bit 0 position. */ -#define PORT_OPC1_bm (1<<4) /* Output/Pull Configuration bit 1 mask. */ -#define PORT_OPC1_bp 4 /* Output/Pull Configuration bit 1 position. */ -#define PORT_OPC2_bm (1<<5) /* Output/Pull Configuration bit 2 mask. */ -#define PORT_OPC2_bp 5 /* Output/Pull Configuration bit 2 position. */ - -#define PORT_ISC_gm 0x07 /* Input/Sense Configuration group mask. */ -#define PORT_ISC_gp 0 /* Input/Sense Configuration group position. */ -#define PORT_ISC0_bm (1<<0) /* Input/Sense Configuration bit 0 mask. */ -#define PORT_ISC0_bp 0 /* Input/Sense Configuration bit 0 position. */ -#define PORT_ISC1_bm (1<<1) /* Input/Sense Configuration bit 1 mask. */ -#define PORT_ISC1_bp 1 /* Input/Sense Configuration bit 1 position. */ -#define PORT_ISC2_bm (1<<2) /* Input/Sense Configuration bit 2 mask. */ -#define PORT_ISC2_bp 2 /* Input/Sense Configuration bit 2 position. */ - -/* PORT.PIN1CTRL bit masks and bit positions */ -/* PORT_SRLEN Predefined. */ -/* PORT_SRLEN Predefined. */ - -/* PORT_INVEN Predefined. */ -/* PORT_INVEN Predefined. */ - -/* PORT_OPC Predefined. */ -/* PORT_OPC Predefined. */ - -/* PORT_ISC Predefined. */ -/* PORT_ISC Predefined. */ - -/* PORT.PIN2CTRL bit masks and bit positions */ -/* PORT_SRLEN Predefined. */ -/* PORT_SRLEN Predefined. */ - -/* PORT_INVEN Predefined. */ -/* PORT_INVEN Predefined. */ - -/* PORT_OPC Predefined. */ -/* PORT_OPC Predefined. */ - -/* PORT_ISC Predefined. */ -/* PORT_ISC Predefined. */ - -/* PORT.PIN3CTRL bit masks and bit positions */ -/* PORT_SRLEN Predefined. */ -/* PORT_SRLEN Predefined. */ - -/* PORT_INVEN Predefined. */ -/* PORT_INVEN Predefined. */ - -/* PORT_OPC Predefined. */ -/* PORT_OPC Predefined. */ - -/* PORT_ISC Predefined. */ -/* PORT_ISC Predefined. */ - -/* PORT.PIN4CTRL bit masks and bit positions */ -/* PORT_SRLEN Predefined. */ -/* PORT_SRLEN Predefined. */ - -/* PORT_INVEN Predefined. */ -/* PORT_INVEN Predefined. */ - -/* PORT_OPC Predefined. */ -/* PORT_OPC Predefined. */ - -/* PORT_ISC Predefined. */ -/* PORT_ISC Predefined. */ - -/* PORT.PIN5CTRL bit masks and bit positions */ -/* PORT_SRLEN Predefined. */ -/* PORT_SRLEN Predefined. */ - -/* PORT_INVEN Predefined. */ -/* PORT_INVEN Predefined. */ - -/* PORT_OPC Predefined. */ -/* PORT_OPC Predefined. */ - -/* PORT_ISC Predefined. */ -/* PORT_ISC Predefined. */ - -/* PORT.PIN6CTRL bit masks and bit positions */ -/* PORT_SRLEN Predefined. */ -/* PORT_SRLEN Predefined. */ - -/* PORT_INVEN Predefined. */ -/* PORT_INVEN Predefined. */ - -/* PORT_OPC Predefined. */ -/* PORT_OPC Predefined. */ - -/* PORT_ISC Predefined. */ -/* PORT_ISC Predefined. */ - -/* PORT.PIN7CTRL bit masks and bit positions */ -/* PORT_SRLEN Predefined. */ -/* PORT_SRLEN Predefined. */ - -/* PORT_INVEN Predefined. */ -/* PORT_INVEN Predefined. */ - -/* PORT_OPC Predefined. */ -/* PORT_OPC Predefined. */ - -/* PORT_ISC Predefined. */ -/* PORT_ISC Predefined. */ - -/* TC - 16-bit Timer/Counter With PWM */ -/* TC0.CTRLA bit masks and bit positions */ -#define TC0_CLKSEL_gm 0x0F /* Clock Selection group mask. */ -#define TC0_CLKSEL_gp 0 /* Clock Selection group position. */ -#define TC0_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ -#define TC0_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ -#define TC0_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ -#define TC0_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ -#define TC0_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ -#define TC0_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ -#define TC0_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ -#define TC0_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ - -/* TC0.CTRLB bit masks and bit positions */ -#define TC0_CCDEN_bm 0x80 /* Compare or Capture D Enable bit mask. */ -#define TC0_CCDEN_bp 7 /* Compare or Capture D Enable bit position. */ - -#define TC0_CCCEN_bm 0x40 /* Compare or Capture C Enable bit mask. */ -#define TC0_CCCEN_bp 6 /* Compare or Capture C Enable bit position. */ - -#define TC0_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ -#define TC0_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ - -#define TC0_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ -#define TC0_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ - -#define TC0_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ -#define TC0_WGMODE_gp 0 /* Waveform generation mode group position. */ -#define TC0_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ -#define TC0_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ -#define TC0_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ -#define TC0_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ -#define TC0_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ -#define TC0_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ - -/* TC0.CTRLC bit masks and bit positions */ -#define TC0_CMPD_bm 0x08 /* Compare D Output Value bit mask. */ -#define TC0_CMPD_bp 3 /* Compare D Output Value bit position. */ - -#define TC0_CMPC_bm 0x04 /* Compare C Output Value bit mask. */ -#define TC0_CMPC_bp 2 /* Compare C Output Value bit position. */ - -#define TC0_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ -#define TC0_CMPB_bp 1 /* Compare B Output Value bit position. */ - -#define TC0_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ -#define TC0_CMPA_bp 0 /* Compare A Output Value bit position. */ - -/* TC0.CTRLD bit masks and bit positions */ -#define TC0_EVACT_gm 0xE0 /* Event Action group mask. */ -#define TC0_EVACT_gp 5 /* Event Action group position. */ -#define TC0_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ -#define TC0_EVACT0_bp 5 /* Event Action bit 0 position. */ -#define TC0_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ -#define TC0_EVACT1_bp 6 /* Event Action bit 1 position. */ -#define TC0_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ -#define TC0_EVACT2_bp 7 /* Event Action bit 2 position. */ - -#define TC0_EVDLY_bm 0x10 /* Event Delay bit mask. */ -#define TC0_EVDLY_bp 4 /* Event Delay bit position. */ - -#define TC0_EVSEL_gm 0x0F /* Event Source Select group mask. */ -#define TC0_EVSEL_gp 0 /* Event Source Select group position. */ -#define TC0_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ -#define TC0_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ -#define TC0_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ -#define TC0_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ -#define TC0_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ -#define TC0_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ -#define TC0_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ -#define TC0_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ - -/* TC0.CTRLE bit masks and bit positions */ -#define TC0_BYTEM_gm 0x03 /* Byte Mode group mask. */ -#define TC0_BYTEM_gp 0 /* Byte Mode group position. */ -#define TC0_BYTEM0_bm (1<<0) /* Byte Mode bit 0 mask. */ -#define TC0_BYTEM0_bp 0 /* Byte Mode bit 0 position. */ -#define TC0_BYTEM1_bm (1<<1) /* Byte Mode bit 1 mask. */ -#define TC0_BYTEM1_bp 1 /* Byte Mode bit 1 position. */ - -/* TC0.INTCTRLA bit masks and bit positions */ -#define TC0_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ -#define TC0_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ -#define TC0_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ -#define TC0_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ -#define TC0_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ -#define TC0_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ - -#define TC0_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ -#define TC0_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ -#define TC0_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ -#define TC0_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ -#define TC0_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ -#define TC0_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ - -/* TC0.INTCTRLB bit masks and bit positions */ -#define TC0_CCDINTLVL_gm 0xC0 /* Compare or Capture D Interrupt Level group mask. */ -#define TC0_CCDINTLVL_gp 6 /* Compare or Capture D Interrupt Level group position. */ -#define TC0_CCDINTLVL0_bm (1<<6) /* Compare or Capture D Interrupt Level bit 0 mask. */ -#define TC0_CCDINTLVL0_bp 6 /* Compare or Capture D Interrupt Level bit 0 position. */ -#define TC0_CCDINTLVL1_bm (1<<7) /* Compare or Capture D Interrupt Level bit 1 mask. */ -#define TC0_CCDINTLVL1_bp 7 /* Compare or Capture D Interrupt Level bit 1 position. */ - -#define TC0_CCCINTLVL_gm 0x30 /* Compare or Capture C Interrupt Level group mask. */ -#define TC0_CCCINTLVL_gp 4 /* Compare or Capture C Interrupt Level group position. */ -#define TC0_CCCINTLVL0_bm (1<<4) /* Compare or Capture C Interrupt Level bit 0 mask. */ -#define TC0_CCCINTLVL0_bp 4 /* Compare or Capture C Interrupt Level bit 0 position. */ -#define TC0_CCCINTLVL1_bm (1<<5) /* Compare or Capture C Interrupt Level bit 1 mask. */ -#define TC0_CCCINTLVL1_bp 5 /* Compare or Capture C Interrupt Level bit 1 position. */ - -#define TC0_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ -#define TC0_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ -#define TC0_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ -#define TC0_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ -#define TC0_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ -#define TC0_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ - -#define TC0_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ -#define TC0_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ -#define TC0_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ -#define TC0_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ -#define TC0_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ -#define TC0_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ - -/* TC0.CTRLFCLR bit masks and bit positions */ -#define TC0_CMD_gm 0x0C /* Command group mask. */ -#define TC0_CMD_gp 2 /* Command group position. */ -#define TC0_CMD0_bm (1<<2) /* Command bit 0 mask. */ -#define TC0_CMD0_bp 2 /* Command bit 0 position. */ -#define TC0_CMD1_bm (1<<3) /* Command bit 1 mask. */ -#define TC0_CMD1_bp 3 /* Command bit 1 position. */ - -#define TC0_LUPD_bm 0x02 /* Lock Update bit mask. */ -#define TC0_LUPD_bp 1 /* Lock Update bit position. */ - -#define TC0_DIR_bm 0x01 /* Direction bit mask. */ -#define TC0_DIR_bp 0 /* Direction bit position. */ - -/* TC0.CTRLFSET bit masks and bit positions */ -/* TC0_CMD Predefined. */ -/* TC0_CMD Predefined. */ - -/* TC0_LUPD Predefined. */ -/* TC0_LUPD Predefined. */ - -/* TC0_DIR Predefined. */ -/* TC0_DIR Predefined. */ - -/* TC0.CTRLGCLR bit masks and bit positions */ -#define TC0_CCDBV_bm 0x10 /* Compare or Capture D Buffer Valid bit mask. */ -#define TC0_CCDBV_bp 4 /* Compare or Capture D Buffer Valid bit position. */ - -#define TC0_CCCBV_bm 0x08 /* Compare or Capture C Buffer Valid bit mask. */ -#define TC0_CCCBV_bp 3 /* Compare or Capture C Buffer Valid bit position. */ - -#define TC0_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ -#define TC0_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ - -#define TC0_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ -#define TC0_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ - -#define TC0_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ -#define TC0_PERBV_bp 0 /* Period Buffer Valid bit position. */ - -/* TC0.CTRLGSET bit masks and bit positions */ -/* TC0_CCDBV Predefined. */ -/* TC0_CCDBV Predefined. */ - -/* TC0_CCCBV Predefined. */ -/* TC0_CCCBV Predefined. */ - -/* TC0_CCBBV Predefined. */ -/* TC0_CCBBV Predefined. */ - -/* TC0_CCABV Predefined. */ -/* TC0_CCABV Predefined. */ - -/* TC0_PERBV Predefined. */ -/* TC0_PERBV Predefined. */ - -/* TC0.INTFLAGS bit masks and bit positions */ -#define TC0_CCDIF_bm 0x80 /* Compare or Capture D Interrupt Flag bit mask. */ -#define TC0_CCDIF_bp 7 /* Compare or Capture D Interrupt Flag bit position. */ - -#define TC0_CCCIF_bm 0x40 /* Compare or Capture C Interrupt Flag bit mask. */ -#define TC0_CCCIF_bp 6 /* Compare or Capture C Interrupt Flag bit position. */ - -#define TC0_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ -#define TC0_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ - -#define TC0_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ -#define TC0_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ - -#define TC0_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ -#define TC0_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ - -#define TC0_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ -#define TC0_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ - -/* TC1.CTRLA bit masks and bit positions */ -#define TC1_CLKSEL_gm 0x0F /* Clock Selection group mask. */ -#define TC1_CLKSEL_gp 0 /* Clock Selection group position. */ -#define TC1_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ -#define TC1_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ -#define TC1_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ -#define TC1_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ -#define TC1_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ -#define TC1_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ -#define TC1_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ -#define TC1_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ - -/* TC1.CTRLB bit masks and bit positions */ -#define TC1_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ -#define TC1_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ - -#define TC1_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ -#define TC1_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ - -#define TC1_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ -#define TC1_WGMODE_gp 0 /* Waveform generation mode group position. */ -#define TC1_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ -#define TC1_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ -#define TC1_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ -#define TC1_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ -#define TC1_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ -#define TC1_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ - -/* TC1.CTRLC bit masks and bit positions */ -#define TC1_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ -#define TC1_CMPB_bp 1 /* Compare B Output Value bit position. */ - -#define TC1_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ -#define TC1_CMPA_bp 0 /* Compare A Output Value bit position. */ - -/* TC1.CTRLD bit masks and bit positions */ -#define TC1_EVACT_gm 0xE0 /* Event Action group mask. */ -#define TC1_EVACT_gp 5 /* Event Action group position. */ -#define TC1_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ -#define TC1_EVACT0_bp 5 /* Event Action bit 0 position. */ -#define TC1_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ -#define TC1_EVACT1_bp 6 /* Event Action bit 1 position. */ -#define TC1_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ -#define TC1_EVACT2_bp 7 /* Event Action bit 2 position. */ - -#define TC1_EVDLY_bm 0x10 /* Event Delay bit mask. */ -#define TC1_EVDLY_bp 4 /* Event Delay bit position. */ - -#define TC1_EVSEL_gm 0x0F /* Event Source Select group mask. */ -#define TC1_EVSEL_gp 0 /* Event Source Select group position. */ -#define TC1_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ -#define TC1_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ -#define TC1_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ -#define TC1_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ -#define TC1_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ -#define TC1_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ -#define TC1_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ -#define TC1_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ - -/* TC1.CTRLE bit masks and bit positions */ -#define TC1_BYTEM_bm 0x01 /* Byte Mode bit mask. */ -#define TC1_BYTEM_bp 0 /* Byte Mode bit position. */ - -/* TC1.INTCTRLA bit masks and bit positions */ -#define TC1_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ -#define TC1_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ -#define TC1_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ -#define TC1_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ -#define TC1_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ -#define TC1_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ - -#define TC1_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ -#define TC1_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ -#define TC1_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ -#define TC1_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ -#define TC1_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ -#define TC1_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ - -/* TC1.INTCTRLB bit masks and bit positions */ -#define TC1_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ -#define TC1_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ -#define TC1_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ -#define TC1_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ -#define TC1_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ -#define TC1_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ - -#define TC1_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ -#define TC1_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ -#define TC1_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ -#define TC1_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ -#define TC1_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ -#define TC1_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ - -/* TC1.CTRLFCLR bit masks and bit positions */ -#define TC1_CMD_gm 0x0C /* Command group mask. */ -#define TC1_CMD_gp 2 /* Command group position. */ -#define TC1_CMD0_bm (1<<2) /* Command bit 0 mask. */ -#define TC1_CMD0_bp 2 /* Command bit 0 position. */ -#define TC1_CMD1_bm (1<<3) /* Command bit 1 mask. */ -#define TC1_CMD1_bp 3 /* Command bit 1 position. */ - -#define TC1_LUPD_bm 0x02 /* Lock Update bit mask. */ -#define TC1_LUPD_bp 1 /* Lock Update bit position. */ - -#define TC1_DIR_bm 0x01 /* Direction bit mask. */ -#define TC1_DIR_bp 0 /* Direction bit position. */ - -/* TC1.CTRLFSET bit masks and bit positions */ -/* TC1_CMD Predefined. */ -/* TC1_CMD Predefined. */ - -/* TC1_LUPD Predefined. */ -/* TC1_LUPD Predefined. */ - -/* TC1_DIR Predefined. */ -/* TC1_DIR Predefined. */ - -/* TC1.CTRLGCLR bit masks and bit positions */ -#define TC1_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ -#define TC1_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ - -#define TC1_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ -#define TC1_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ - -#define TC1_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ -#define TC1_PERBV_bp 0 /* Period Buffer Valid bit position. */ - -/* TC1.CTRLGSET bit masks and bit positions */ -/* TC1_CCBBV Predefined. */ -/* TC1_CCBBV Predefined. */ - -/* TC1_CCABV Predefined. */ -/* TC1_CCABV Predefined. */ - -/* TC1_PERBV Predefined. */ -/* TC1_PERBV Predefined. */ - -/* TC1.INTFLAGS bit masks and bit positions */ -#define TC1_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ -#define TC1_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ - -#define TC1_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ -#define TC1_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ - -#define TC1_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ -#define TC1_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ - -#define TC1_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ -#define TC1_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ - -/* AWEX - Timer/Counter Advanced Waveform Extension */ -/* AWEX.CTRL bit masks and bit positions */ -#define AWEX_PGM_bm 0x20 /* Pattern Generation Mode bit mask. */ -#define AWEX_PGM_bp 5 /* Pattern Generation Mode bit position. */ - -#define AWEX_CWCM_bm 0x10 /* Common Waveform Channel Mode bit mask. */ -#define AWEX_CWCM_bp 4 /* Common Waveform Channel Mode bit position. */ - -#define AWEX_DTICCDEN_bm 0x08 /* Dead Time Insertion Compare Channel D Enable bit mask. */ -#define AWEX_DTICCDEN_bp 3 /* Dead Time Insertion Compare Channel D Enable bit position. */ - -#define AWEX_DTICCCEN_bm 0x04 /* Dead Time Insertion Compare Channel C Enable bit mask. */ -#define AWEX_DTICCCEN_bp 2 /* Dead Time Insertion Compare Channel C Enable bit position. */ - -#define AWEX_DTICCBEN_bm 0x02 /* Dead Time Insertion Compare Channel B Enable bit mask. */ -#define AWEX_DTICCBEN_bp 1 /* Dead Time Insertion Compare Channel B Enable bit position. */ - -#define AWEX_DTICCAEN_bm 0x01 /* Dead Time Insertion Compare Channel A Enable bit mask. */ -#define AWEX_DTICCAEN_bp 0 /* Dead Time Insertion Compare Channel A Enable bit position. */ - -/* AWEX.FDCTRL bit masks and bit positions */ -#define AWEX_FDDBD_bm 0x10 /* Fault Detect on Disable Break Disable bit mask. */ -#define AWEX_FDDBD_bp 4 /* Fault Detect on Disable Break Disable bit position. */ - -#define AWEX_FDMODE_bm 0x04 /* Fault Detect Mode bit mask. */ -#define AWEX_FDMODE_bp 2 /* Fault Detect Mode bit position. */ - -#define AWEX_FDACT_gm 0x03 /* Fault Detect Action group mask. */ -#define AWEX_FDACT_gp 0 /* Fault Detect Action group position. */ -#define AWEX_FDACT0_bm (1<<0) /* Fault Detect Action bit 0 mask. */ -#define AWEX_FDACT0_bp 0 /* Fault Detect Action bit 0 position. */ -#define AWEX_FDACT1_bm (1<<1) /* Fault Detect Action bit 1 mask. */ -#define AWEX_FDACT1_bp 1 /* Fault Detect Action bit 1 position. */ - -/* AWEX.STATUS bit masks and bit positions */ -#define AWEX_FDF_bm 0x04 /* Fault Detect Flag bit mask. */ -#define AWEX_FDF_bp 2 /* Fault Detect Flag bit position. */ - -#define AWEX_DTHSBUFV_bm 0x02 /* Dead Time High Side Buffer Valid bit mask. */ -#define AWEX_DTHSBUFV_bp 1 /* Dead Time High Side Buffer Valid bit position. */ - -#define AWEX_DTLSBUFV_bm 0x01 /* Dead Time Low Side Buffer Valid bit mask. */ -#define AWEX_DTLSBUFV_bp 0 /* Dead Time Low Side Buffer Valid bit position. */ - -/* AWEX.STATUSSET bit masks and bit positions */ -/* AWEX_FDF Predefined. */ -/* AWEX_FDF Predefined. */ - -/* AWEX_DTHSBUFV Predefined. */ -/* AWEX_DTHSBUFV Predefined. */ - -/* AWEX_DTLSBUFV Predefined. */ -/* AWEX_DTLSBUFV Predefined. */ - -/* HIRES - Timer/Counter High-Resolution Extension */ -/* HIRES.CTRLA bit masks and bit positions */ -#define HIRES_HREN_gm 0x03 /* High Resolution Enable group mask. */ -#define HIRES_HREN_gp 0 /* High Resolution Enable group position. */ -#define HIRES_HREN0_bm (1<<0) /* High Resolution Enable bit 0 mask. */ -#define HIRES_HREN0_bp 0 /* High Resolution Enable bit 0 position. */ -#define HIRES_HREN1_bm (1<<1) /* High Resolution Enable bit 1 mask. */ -#define HIRES_HREN1_bp 1 /* High Resolution Enable bit 1 position. */ - -/* USART - Universal Asynchronous Receiver-Transmitter */ -/* USART.STATUS bit masks and bit positions */ -#define USART_RXCIF_bm 0x80 /* Receive Interrupt Flag bit mask. */ -#define USART_RXCIF_bp 7 /* Receive Interrupt Flag bit position. */ - -#define USART_TXCIF_bm 0x40 /* Transmit Interrupt Flag bit mask. */ -#define USART_TXCIF_bp 6 /* Transmit Interrupt Flag bit position. */ - -#define USART_DREIF_bm 0x20 /* Data Register Empty Flag bit mask. */ -#define USART_DREIF_bp 5 /* Data Register Empty Flag bit position. */ - -#define USART_FERR_bm 0x10 /* Frame Error bit mask. */ -#define USART_FERR_bp 4 /* Frame Error bit position. */ - -#define USART_BUFOVF_bm 0x08 /* Buffer Overflow bit mask. */ -#define USART_BUFOVF_bp 3 /* Buffer Overflow bit position. */ - -#define USART_PERR_bm 0x04 /* Parity Error bit mask. */ -#define USART_PERR_bp 2 /* Parity Error bit position. */ - -#define USART_RXB8_bm 0x01 /* Receive Bit 8 bit mask. */ -#define USART_RXB8_bp 0 /* Receive Bit 8 bit position. */ - -/* USART.CTRLA bit masks and bit positions */ -#define USART_RXCINTLVL_gm 0x30 /* Receive Interrupt Level group mask. */ -#define USART_RXCINTLVL_gp 4 /* Receive Interrupt Level group position. */ -#define USART_RXCINTLVL0_bm (1<<4) /* Receive Interrupt Level bit 0 mask. */ -#define USART_RXCINTLVL0_bp 4 /* Receive Interrupt Level bit 0 position. */ -#define USART_RXCINTLVL1_bm (1<<5) /* Receive Interrupt Level bit 1 mask. */ -#define USART_RXCINTLVL1_bp 5 /* Receive Interrupt Level bit 1 position. */ - -#define USART_TXCINTLVL_gm 0x0C /* Transmit Interrupt Level group mask. */ -#define USART_TXCINTLVL_gp 2 /* Transmit Interrupt Level group position. */ -#define USART_TXCINTLVL0_bm (1<<2) /* Transmit Interrupt Level bit 0 mask. */ -#define USART_TXCINTLVL0_bp 2 /* Transmit Interrupt Level bit 0 position. */ -#define USART_TXCINTLVL1_bm (1<<3) /* Transmit Interrupt Level bit 1 mask. */ -#define USART_TXCINTLVL1_bp 3 /* Transmit Interrupt Level bit 1 position. */ - -#define USART_DREINTLVL_gm 0x03 /* Data Register Empty Interrupt Level group mask. */ -#define USART_DREINTLVL_gp 0 /* Data Register Empty Interrupt Level group position. */ -#define USART_DREINTLVL0_bm (1<<0) /* Data Register Empty Interrupt Level bit 0 mask. */ -#define USART_DREINTLVL0_bp 0 /* Data Register Empty Interrupt Level bit 0 position. */ -#define USART_DREINTLVL1_bm (1<<1) /* Data Register Empty Interrupt Level bit 1 mask. */ -#define USART_DREINTLVL1_bp 1 /* Data Register Empty Interrupt Level bit 1 position. */ - -/* USART.CTRLB bit masks and bit positions */ -#define USART_RXEN_bm 0x10 /* Receiver Enable bit mask. */ -#define USART_RXEN_bp 4 /* Receiver Enable bit position. */ - -#define USART_TXEN_bm 0x08 /* Transmitter Enable bit mask. */ -#define USART_TXEN_bp 3 /* Transmitter Enable bit position. */ - -#define USART_CLK2X_bm 0x04 /* Double transmission speed bit mask. */ -#define USART_CLK2X_bp 2 /* Double transmission speed bit position. */ - -#define USART_MPCM_bm 0x02 /* Multi-processor Communication Mode bit mask. */ -#define USART_MPCM_bp 1 /* Multi-processor Communication Mode bit position. */ - -#define USART_TXB8_bm 0x01 /* Transmit bit 8 bit mask. */ -#define USART_TXB8_bp 0 /* Transmit bit 8 bit position. */ - -/* USART.CTRLC bit masks and bit positions */ -#define USART_CMODE_gm 0xC0 /* Communication Mode group mask. */ -#define USART_CMODE_gp 6 /* Communication Mode group position. */ -#define USART_CMODE0_bm (1<<6) /* Communication Mode bit 0 mask. */ -#define USART_CMODE0_bp 6 /* Communication Mode bit 0 position. */ -#define USART_CMODE1_bm (1<<7) /* Communication Mode bit 1 mask. */ -#define USART_CMODE1_bp 7 /* Communication Mode bit 1 position. */ - -#define USART_PMODE_gm 0x30 /* Parity Mode group mask. */ -#define USART_PMODE_gp 4 /* Parity Mode group position. */ -#define USART_PMODE0_bm (1<<4) /* Parity Mode bit 0 mask. */ -#define USART_PMODE0_bp 4 /* Parity Mode bit 0 position. */ -#define USART_PMODE1_bm (1<<5) /* Parity Mode bit 1 mask. */ -#define USART_PMODE1_bp 5 /* Parity Mode bit 1 position. */ - -#define USART_SBMODE_bm 0x08 /* Stop Bit Mode bit mask. */ -#define USART_SBMODE_bp 3 /* Stop Bit Mode bit position. */ - -#define USART_CHSIZE_gm 0x07 /* Character Size group mask. */ -#define USART_CHSIZE_gp 0 /* Character Size group position. */ -#define USART_CHSIZE0_bm (1<<0) /* Character Size bit 0 mask. */ -#define USART_CHSIZE0_bp 0 /* Character Size bit 0 position. */ -#define USART_CHSIZE1_bm (1<<1) /* Character Size bit 1 mask. */ -#define USART_CHSIZE1_bp 1 /* Character Size bit 1 position. */ -#define USART_CHSIZE2_bm (1<<2) /* Character Size bit 2 mask. */ -#define USART_CHSIZE2_bp 2 /* Character Size bit 2 position. */ - -/* USART.BAUDCTRLA bit masks and bit positions */ -#define USART_BSEL_gm 0xFF /* Baud Rate Selection Bits [7:0] group mask. */ -#define USART_BSEL_gp 0 /* Baud Rate Selection Bits [7:0] group position. */ -#define USART_BSEL0_bm (1<<0) /* Baud Rate Selection Bits [7:0] bit 0 mask. */ -#define USART_BSEL0_bp 0 /* Baud Rate Selection Bits [7:0] bit 0 position. */ -#define USART_BSEL1_bm (1<<1) /* Baud Rate Selection Bits [7:0] bit 1 mask. */ -#define USART_BSEL1_bp 1 /* Baud Rate Selection Bits [7:0] bit 1 position. */ -#define USART_BSEL2_bm (1<<2) /* Baud Rate Selection Bits [7:0] bit 2 mask. */ -#define USART_BSEL2_bp 2 /* Baud Rate Selection Bits [7:0] bit 2 position. */ -#define USART_BSEL3_bm (1<<3) /* Baud Rate Selection Bits [7:0] bit 3 mask. */ -#define USART_BSEL3_bp 3 /* Baud Rate Selection Bits [7:0] bit 3 position. */ -#define USART_BSEL4_bm (1<<4) /* Baud Rate Selection Bits [7:0] bit 4 mask. */ -#define USART_BSEL4_bp 4 /* Baud Rate Selection Bits [7:0] bit 4 position. */ -#define USART_BSEL5_bm (1<<5) /* Baud Rate Selection Bits [7:0] bit 5 mask. */ -#define USART_BSEL5_bp 5 /* Baud Rate Selection Bits [7:0] bit 5 position. */ -#define USART_BSEL6_bm (1<<6) /* Baud Rate Selection Bits [7:0] bit 6 mask. */ -#define USART_BSEL6_bp 6 /* Baud Rate Selection Bits [7:0] bit 6 position. */ -#define USART_BSEL7_bm (1<<7) /* Baud Rate Selection Bits [7:0] bit 7 mask. */ -#define USART_BSEL7_bp 7 /* Baud Rate Selection Bits [7:0] bit 7 position. */ - -/* USART.BAUDCTRLB bit masks and bit positions */ -#define USART_BSCALE_gm 0xF0 /* Baud Rate Scale group mask. */ -#define USART_BSCALE_gp 4 /* Baud Rate Scale group position. */ -#define USART_BSCALE0_bm (1<<4) /* Baud Rate Scale bit 0 mask. */ -#define USART_BSCALE0_bp 4 /* Baud Rate Scale bit 0 position. */ -#define USART_BSCALE1_bm (1<<5) /* Baud Rate Scale bit 1 mask. */ -#define USART_BSCALE1_bp 5 /* Baud Rate Scale bit 1 position. */ -#define USART_BSCALE2_bm (1<<6) /* Baud Rate Scale bit 2 mask. */ -#define USART_BSCALE2_bp 6 /* Baud Rate Scale bit 2 position. */ -#define USART_BSCALE3_bm (1<<7) /* Baud Rate Scale bit 3 mask. */ -#define USART_BSCALE3_bp 7 /* Baud Rate Scale bit 3 position. */ - -/* USART_BSEL Predefined. */ -/* USART_BSEL Predefined. */ - -/* SPI - Serial Peripheral Interface */ -/* SPI.CTRL bit masks and bit positions */ -#define SPI_CLK2X_bm 0x80 /* Enable Double Speed bit mask. */ -#define SPI_CLK2X_bp 7 /* Enable Double Speed bit position. */ - -#define SPI_ENABLE_bm 0x40 /* Enable Module bit mask. */ -#define SPI_ENABLE_bp 6 /* Enable Module bit position. */ - -#define SPI_DORD_bm 0x20 /* Data Order Setting bit mask. */ -#define SPI_DORD_bp 5 /* Data Order Setting bit position. */ - -#define SPI_MASTER_bm 0x10 /* Master Operation Enable bit mask. */ -#define SPI_MASTER_bp 4 /* Master Operation Enable bit position. */ - -#define SPI_MODE_gm 0x0C /* SPI Mode group mask. */ -#define SPI_MODE_gp 2 /* SPI Mode group position. */ -#define SPI_MODE0_bm (1<<2) /* SPI Mode bit 0 mask. */ -#define SPI_MODE0_bp 2 /* SPI Mode bit 0 position. */ -#define SPI_MODE1_bm (1<<3) /* SPI Mode bit 1 mask. */ -#define SPI_MODE1_bp 3 /* SPI Mode bit 1 position. */ - -#define SPI_PRESCALER_gm 0x03 /* Prescaler group mask. */ -#define SPI_PRESCALER_gp 0 /* Prescaler group position. */ -#define SPI_PRESCALER0_bm (1<<0) /* Prescaler bit 0 mask. */ -#define SPI_PRESCALER0_bp 0 /* Prescaler bit 0 position. */ -#define SPI_PRESCALER1_bm (1<<1) /* Prescaler bit 1 mask. */ -#define SPI_PRESCALER1_bp 1 /* Prescaler bit 1 position. */ - -/* SPI.INTCTRL bit masks and bit positions */ -#define SPI_INTLVL_gm 0x03 /* Interrupt level group mask. */ -#define SPI_INTLVL_gp 0 /* Interrupt level group position. */ -#define SPI_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */ -#define SPI_INTLVL0_bp 0 /* Interrupt level bit 0 position. */ -#define SPI_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */ -#define SPI_INTLVL1_bp 1 /* Interrupt level bit 1 position. */ - -/* SPI.STATUS bit masks and bit positions */ -#define SPI_IF_bm 0x80 /* Interrupt Flag bit mask. */ -#define SPI_IF_bp 7 /* Interrupt Flag bit position. */ - -#define SPI_WRCOL_bm 0x40 /* Write Collision bit mask. */ -#define SPI_WRCOL_bp 6 /* Write Collision bit position. */ - -/* IRCOM - IR Communication Module */ -/* IRCOM.CTRL bit masks and bit positions */ -#define IRCOM_EVSEL_gm 0x0F /* Event Channel Select group mask. */ -#define IRCOM_EVSEL_gp 0 /* Event Channel Select group position. */ -#define IRCOM_EVSEL0_bm (1<<0) /* Event Channel Select bit 0 mask. */ -#define IRCOM_EVSEL0_bp 0 /* Event Channel Select bit 0 position. */ -#define IRCOM_EVSEL1_bm (1<<1) /* Event Channel Select bit 1 mask. */ -#define IRCOM_EVSEL1_bp 1 /* Event Channel Select bit 1 position. */ -#define IRCOM_EVSEL2_bm (1<<2) /* Event Channel Select bit 2 mask. */ -#define IRCOM_EVSEL2_bp 2 /* Event Channel Select bit 2 position. */ -#define IRCOM_EVSEL3_bm (1<<3) /* Event Channel Select bit 3 mask. */ -#define IRCOM_EVSEL3_bp 3 /* Event Channel Select bit 3 position. */ - -/* LCD - LCD Controller */ -/* LCD.CTRLA bit masks and bit positions */ -#define LCD_ENABLE_bm 0x80 /* LCD Enable bit mask. */ -#define LCD_ENABLE_bp 7 /* LCD Enable bit position. */ - -#define LCD_XBIAS_bm 0x40 /* External Register Bias Generation bit mask. */ -#define LCD_XBIAS_bp 6 /* External Register Bias Generation bit position. */ - -#define LCD_DATCLK_bm 0x20 /* Data Register Lock bit mask. */ -#define LCD_DATCLK_bp 5 /* Data Register Lock bit position. */ - -#define LCD_COMSWP_bm 0x10 /* Common Bus Swap bit mask. */ -#define LCD_COMSWP_bp 4 /* Common Bus Swap bit position. */ - -#define LCD_SEGSWP_bm 0x08 /* Segment Bus Swap bit mask. */ -#define LCD_SEGSWP_bp 3 /* Segment Bus Swap bit position. */ - -#define LCD_CLRDT_bm 0x04 /* Clear Data Register bit mask. */ -#define LCD_CLRDT_bp 2 /* Clear Data Register bit position. */ - -#define LCD_SEGON_bm 0x02 /* Segments On bit mask. */ -#define LCD_SEGON_bp 1 /* Segments On bit position. */ - -#define LCD_BLANK_bm 0x01 /* Blanking Display Mode bit mask. */ -#define LCD_BLANK_bp 0 /* Blanking Display Mode bit position. */ - -/* LCD.CTRLB bit masks and bit positions */ -#define LCD_PRESC_bm 0x80 /* LCD Prescaler Select bit mask. */ -#define LCD_PRESC_bp 7 /* LCD Prescaler Select bit position. */ - -#define LCD_CLKDIV_gm 0x70 /* LCD Clock Divide group mask. */ -#define LCD_CLKDIV_gp 4 /* LCD Clock Divide group position. */ -#define LCD_CLKDIV0_bm (1<<4) /* LCD Clock Divide bit 0 mask. */ -#define LCD_CLKDIV0_bp 4 /* LCD Clock Divide bit 0 position. */ -#define LCD_CLKDIV1_bm (1<<5) /* LCD Clock Divide bit 1 mask. */ -#define LCD_CLKDIV1_bp 5 /* LCD Clock Divide bit 1 position. */ -#define LCD_CLKDIV2_bm (1<<6) /* LCD Clock Divide bit 2 mask. */ -#define LCD_CLKDIV2_bp 6 /* LCD Clock Divide bit 2 position. */ - -#define LCD_LPWAV_bm 0x08 /* Low Power Waveform bit mask. */ -#define LCD_LPWAV_bp 3 /* Low Power Waveform bit position. */ - -#define LCD_DUTY_gm 0x03 /* Duty Select group mask. */ -#define LCD_DUTY_gp 0 /* Duty Select group position. */ -#define LCD_DUTY0_bm (1<<0) /* Duty Select bit 0 mask. */ -#define LCD_DUTY0_bp 0 /* Duty Select bit 0 position. */ -#define LCD_DUTY1_bm (1<<1) /* Duty Select bit 1 mask. */ -#define LCD_DUTY1_bp 1 /* Duty Select bit 1 position. */ - -/* LCD.CTRLC bit masks and bit positions */ -#define LCD_PMSK_gm 0x3F /* LCD Port Mask group mask. */ -#define LCD_PMSK_gp 0 /* LCD Port Mask group position. */ -#define LCD_PMSK0_bm (1<<0) /* LCD Port Mask bit 0 mask. */ -#define LCD_PMSK0_bp 0 /* LCD Port Mask bit 0 position. */ -#define LCD_PMSK1_bm (1<<1) /* LCD Port Mask bit 1 mask. */ -#define LCD_PMSK1_bp 1 /* LCD Port Mask bit 1 position. */ -#define LCD_PMSK2_bm (1<<2) /* LCD Port Mask bit 2 mask. */ -#define LCD_PMSK2_bp 2 /* LCD Port Mask bit 2 position. */ -#define LCD_PMSK3_bm (1<<3) /* LCD Port Mask bit 3 mask. */ -#define LCD_PMSK3_bp 3 /* LCD Port Mask bit 3 position. */ -#define LCD_PMSK4_bm (1<<4) /* LCD Port Mask bit 4 mask. */ -#define LCD_PMSK4_bp 4 /* LCD Port Mask bit 4 position. */ -#define LCD_PMSK5_bm (1<<5) /* LCD Port Mask bit 5 mask. */ -#define LCD_PMSK5_bp 5 /* LCD Port Mask bit 5 position. */ - -/* LCD.INTCTRL bit masks and bit positions */ -#define LCD_XIME_gm 0xF8 /* eXtended Interrupt Mode Enable group mask. */ -#define LCD_XIME_gp 3 /* eXtended Interrupt Mode Enable group position. */ -#define LCD_XIME0_bm (1<<3) /* eXtended Interrupt Mode Enable bit 0 mask. */ -#define LCD_XIME0_bp 3 /* eXtended Interrupt Mode Enable bit 0 position. */ -#define LCD_XIME1_bm (1<<4) /* eXtended Interrupt Mode Enable bit 1 mask. */ -#define LCD_XIME1_bp 4 /* eXtended Interrupt Mode Enable bit 1 position. */ -#define LCD_XIME2_bm (1<<5) /* eXtended Interrupt Mode Enable bit 2 mask. */ -#define LCD_XIME2_bp 5 /* eXtended Interrupt Mode Enable bit 2 position. */ -#define LCD_XIME3_bm (1<<6) /* eXtended Interrupt Mode Enable bit 3 mask. */ -#define LCD_XIME3_bp 6 /* eXtended Interrupt Mode Enable bit 3 position. */ -#define LCD_XIME4_bm (1<<7) /* eXtended Interrupt Mode Enable bit 4 mask. */ -#define LCD_XIME4_bp 7 /* eXtended Interrupt Mode Enable bit 4 position. */ - -#define LCD_FCINTLVL_gm 0x03 /* Interrupt Level group mask. */ -#define LCD_FCINTLVL_gp 0 /* Interrupt Level group position. */ -#define LCD_FCINTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */ -#define LCD_FCINTLVL0_bp 0 /* Interrupt Level bit 0 position. */ -#define LCD_FCINTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ -#define LCD_FCINTLVL1_bp 1 /* Interrupt Level bit 1 position. */ - -/* LCD.INTFLAG bit masks and bit positions */ -#define LCD_FCIF_bm 0x01 /* LCD Frame Completed Interrupt Flag bit mask. */ -#define LCD_FCIF_bp 0 /* LCD Frame Completed Interrupt Flag bit position. */ - -/* LCD.CTRLD bit masks and bit positions */ -#define LCD_BLINKEN_bm 0x08 /* Blink Enable bit mask. */ -#define LCD_BLINKEN_bp 3 /* Blink Enable bit position. */ - -#define LCD_BLINKRATE_gm 0x03 /* LCD Blink Rate group mask. */ -#define LCD_BLINKRATE_gp 0 /* LCD Blink Rate group position. */ -#define LCD_BLINKRATE0_bm (1<<0) /* LCD Blink Rate bit 0 mask. */ -#define LCD_BLINKRATE0_bp 0 /* LCD Blink Rate bit 0 position. */ -#define LCD_BLINKRATE1_bm (1<<1) /* LCD Blink Rate bit 1 mask. */ -#define LCD_BLINKRATE1_bp 1 /* LCD Blink Rate bit 1 position. */ - -/* LCD.CTRLE bit masks and bit positions */ -#define LCD_BPS1_gm 0xF0 /* Blink Pixel Selection 1 group mask. */ -#define LCD_BPS1_gp 4 /* Blink Pixel Selection 1 group position. */ -#define LCD_BPS10_bm (1<<4) /* Blink Pixel Selection 1 bit 0 mask. */ -#define LCD_BPS10_bp 4 /* Blink Pixel Selection 1 bit 0 position. */ -#define LCD_BPS11_bm (1<<5) /* Blink Pixel Selection 1 bit 1 mask. */ -#define LCD_BPS11_bp 5 /* Blink Pixel Selection 1 bit 1 position. */ -#define LCD_BPS12_bm (1<<6) /* Blink Pixel Selection 1 bit 2 mask. */ -#define LCD_BPS12_bp 6 /* Blink Pixel Selection 1 bit 2 position. */ -#define LCD_BPS13_bm (1<<7) /* Blink Pixel Selection 1 bit 3 mask. */ -#define LCD_BPS13_bp 7 /* Blink Pixel Selection 1 bit 3 position. */ - -#define LCD_BPS0_gm 0x0F /* Blink Pixel Selection 0 group mask. */ -#define LCD_BPS0_gp 0 /* Blink Pixel Selection 0 group position. */ -#define LCD_BPS00_bm (1<<0) /* Blink Pixel Selection 0 bit 0 mask. */ -#define LCD_BPS00_bp 0 /* Blink Pixel Selection 0 bit 0 position. */ -#define LCD_BPS01_bm (1<<1) /* Blink Pixel Selection 0 bit 1 mask. */ -#define LCD_BPS01_bp 1 /* Blink Pixel Selection 0 bit 1 position. */ -#define LCD_BPS02_bm (1<<2) /* Blink Pixel Selection 0 bit 2 mask. */ -#define LCD_BPS02_bp 2 /* Blink Pixel Selection 0 bit 2 position. */ -#define LCD_BPS03_bm (1<<3) /* Blink Pixel Selection 0 bit 3 mask. */ -#define LCD_BPS03_bp 3 /* Blink Pixel Selection 0 bit 3 position. */ - -/* LCD.CTRLF bit masks and bit positions */ -#define LCD_FCONT_gm 0x3F /* Fine Contrast group mask. */ -#define LCD_FCONT_gp 0 /* Fine Contrast group position. */ -#define LCD_FCONT0_bm (1<<0) /* Fine Contrast bit 0 mask. */ -#define LCD_FCONT0_bp 0 /* Fine Contrast bit 0 position. */ -#define LCD_FCONT1_bm (1<<1) /* Fine Contrast bit 1 mask. */ -#define LCD_FCONT1_bp 1 /* Fine Contrast bit 1 position. */ -#define LCD_FCONT2_bm (1<<2) /* Fine Contrast bit 2 mask. */ -#define LCD_FCONT2_bp 2 /* Fine Contrast bit 2 position. */ -#define LCD_FCONT3_bm (1<<3) /* Fine Contrast bit 3 mask. */ -#define LCD_FCONT3_bp 3 /* Fine Contrast bit 3 position. */ -#define LCD_FCONT4_bm (1<<4) /* Fine Contrast bit 4 mask. */ -#define LCD_FCONT4_bp 4 /* Fine Contrast bit 4 position. */ -#define LCD_FCONT5_bm (1<<5) /* Fine Contrast bit 5 mask. */ -#define LCD_FCONT5_bp 5 /* Fine Contrast bit 5 position. */ - -/* LCD.CTRLG bit masks and bit positions */ -#define LCD_TDG_gm 0xC0 /* Type of Digit group mask. */ -#define LCD_TDG_gp 6 /* Type of Digit group position. */ -#define LCD_TDG0_bm (1<<6) /* Type of Digit bit 0 mask. */ -#define LCD_TDG0_bp 6 /* Type of Digit bit 0 position. */ -#define LCD_TDG1_bm (1<<7) /* Type of Digit bit 1 mask. */ -#define LCD_TDG1_bp 7 /* Type of Digit bit 1 position. */ - -#define LCD_STSEG_gm 0x3F /* Start Segment group mask. */ -#define LCD_STSEG_gp 0 /* Start Segment group position. */ -#define LCD_STSEG0_bm (1<<0) /* Start Segment bit 0 mask. */ -#define LCD_STSEG0_bp 0 /* Start Segment bit 0 position. */ -#define LCD_STSEG1_bm (1<<1) /* Start Segment bit 1 mask. */ -#define LCD_STSEG1_bp 1 /* Start Segment bit 1 position. */ -#define LCD_STSEG2_bm (1<<2) /* Start Segment bit 2 mask. */ -#define LCD_STSEG2_bp 2 /* Start Segment bit 2 position. */ -#define LCD_STSEG3_bm (1<<3) /* Start Segment bit 3 mask. */ -#define LCD_STSEG3_bp 3 /* Start Segment bit 3 position. */ -#define LCD_STSEG4_bm (1<<4) /* Start Segment bit 4 mask. */ -#define LCD_STSEG4_bp 4 /* Start Segment bit 4 position. */ -#define LCD_STSEG5_bm (1<<5) /* Start Segment bit 5 mask. */ -#define LCD_STSEG5_bp 5 /* Start Segment bit 5 position. */ - -/* LCD.CTRLH bit masks and bit positions */ -#define LCD_DEC_bm 0x80 /* Decrement of Start Segment bit mask. */ -#define LCD_DEC_bp 7 /* Decrement of Start Segment bit position. */ - -#define LCD_DCODE_gm 0x7F /* Display Code group mask. */ -#define LCD_DCODE_gp 0 /* Display Code group position. */ -#define LCD_DCODE0_bm (1<<0) /* Display Code bit 0 mask. */ -#define LCD_DCODE0_bp 0 /* Display Code bit 0 position. */ -#define LCD_DCODE1_bm (1<<1) /* Display Code bit 1 mask. */ -#define LCD_DCODE1_bp 1 /* Display Code bit 1 position. */ -#define LCD_DCODE2_bm (1<<2) /* Display Code bit 2 mask. */ -#define LCD_DCODE2_bp 2 /* Display Code bit 2 position. */ -#define LCD_DCODE3_bm (1<<3) /* Display Code bit 3 mask. */ -#define LCD_DCODE3_bp 3 /* Display Code bit 3 position. */ -#define LCD_DCODE4_bm (1<<4) /* Display Code bit 4 mask. */ -#define LCD_DCODE4_bp 4 /* Display Code bit 4 position. */ -#define LCD_DCODE5_bm (1<<5) /* Display Code bit 5 mask. */ -#define LCD_DCODE5_bp 5 /* Display Code bit 5 position. */ -#define LCD_DCODE6_bm (1<<6) /* Display Code bit 6 mask. */ -#define LCD_DCODE6_bp 6 /* Display Code bit 6 position. */ - -/* FUSE - Fuses and Lockbits */ -/* NVM_FUSES.FUSEBYTE0 bit masks and bit positions */ -#define NVM_FUSES_JTAGUSERID_gm 0xFF /* JTAG User ID group mask. */ -#define NVM_FUSES_JTAGUSERID_gp 0 /* JTAG User ID group position. */ -#define NVM_FUSES_JTAGUSERID0_bm (1<<0) /* JTAG User ID bit 0 mask. */ -#define NVM_FUSES_JTAGUSERID0_bp 0 /* JTAG User ID bit 0 position. */ -#define NVM_FUSES_JTAGUSERID1_bm (1<<1) /* JTAG User ID bit 1 mask. */ -#define NVM_FUSES_JTAGUSERID1_bp 1 /* JTAG User ID bit 1 position. */ -#define NVM_FUSES_JTAGUSERID2_bm (1<<2) /* JTAG User ID bit 2 mask. */ -#define NVM_FUSES_JTAGUSERID2_bp 2 /* JTAG User ID bit 2 position. */ -#define NVM_FUSES_JTAGUSERID3_bm (1<<3) /* JTAG User ID bit 3 mask. */ -#define NVM_FUSES_JTAGUSERID3_bp 3 /* JTAG User ID bit 3 position. */ -#define NVM_FUSES_JTAGUSERID4_bm (1<<4) /* JTAG User ID bit 4 mask. */ -#define NVM_FUSES_JTAGUSERID4_bp 4 /* JTAG User ID bit 4 position. */ -#define NVM_FUSES_JTAGUSERID5_bm (1<<5) /* JTAG User ID bit 5 mask. */ -#define NVM_FUSES_JTAGUSERID5_bp 5 /* JTAG User ID bit 5 position. */ -#define NVM_FUSES_JTAGUSERID6_bm (1<<6) /* JTAG User ID bit 6 mask. */ -#define NVM_FUSES_JTAGUSERID6_bp 6 /* JTAG User ID bit 6 position. */ -#define NVM_FUSES_JTAGUSERID7_bm (1<<7) /* JTAG User ID bit 7 mask. */ -#define NVM_FUSES_JTAGUSERID7_bp 7 /* JTAG User ID bit 7 position. */ - -/* NVM_FUSES.FUSEBYTE1 bit masks and bit positions */ -#define NVM_FUSES_WDWP_gm 0xF0 /* Watchdog Window Timeout Period group mask. */ -#define NVM_FUSES_WDWP_gp 4 /* Watchdog Window Timeout Period group position. */ -#define NVM_FUSES_WDWP0_bm (1<<4) /* Watchdog Window Timeout Period bit 0 mask. */ -#define NVM_FUSES_WDWP0_bp 4 /* Watchdog Window Timeout Period bit 0 position. */ -#define NVM_FUSES_WDWP1_bm (1<<5) /* Watchdog Window Timeout Period bit 1 mask. */ -#define NVM_FUSES_WDWP1_bp 5 /* Watchdog Window Timeout Period bit 1 position. */ -#define NVM_FUSES_WDWP2_bm (1<<6) /* Watchdog Window Timeout Period bit 2 mask. */ -#define NVM_FUSES_WDWP2_bp 6 /* Watchdog Window Timeout Period bit 2 position. */ -#define NVM_FUSES_WDWP3_bm (1<<7) /* Watchdog Window Timeout Period bit 3 mask. */ -#define NVM_FUSES_WDWP3_bp 7 /* Watchdog Window Timeout Period bit 3 position. */ - -#define NVM_FUSES_WDP_gm 0x0F /* Watchdog Timeout Period group mask. */ -#define NVM_FUSES_WDP_gp 0 /* Watchdog Timeout Period group position. */ -#define NVM_FUSES_WDP0_bm (1<<0) /* Watchdog Timeout Period bit 0 mask. */ -#define NVM_FUSES_WDP0_bp 0 /* Watchdog Timeout Period bit 0 position. */ -#define NVM_FUSES_WDP1_bm (1<<1) /* Watchdog Timeout Period bit 1 mask. */ -#define NVM_FUSES_WDP1_bp 1 /* Watchdog Timeout Period bit 1 position. */ -#define NVM_FUSES_WDP2_bm (1<<2) /* Watchdog Timeout Period bit 2 mask. */ -#define NVM_FUSES_WDP2_bp 2 /* Watchdog Timeout Period bit 2 position. */ -#define NVM_FUSES_WDP3_bm (1<<3) /* Watchdog Timeout Period bit 3 mask. */ -#define NVM_FUSES_WDP3_bp 3 /* Watchdog Timeout Period bit 3 position. */ - -/* NVM_FUSES.FUSEBYTE2 bit masks and bit positions */ -#define NVM_FUSES_BOOTRST_bm 0x40 /* Boot Loader Section Reset Vector bit mask. */ -#define NVM_FUSES_BOOTRST_bp 6 /* Boot Loader Section Reset Vector bit position. */ - -#define NVM_FUSES_TOSCSEL_bm 0x20 /* Timer Oscillator pin location bit mask. */ -#define NVM_FUSES_TOSCSEL_bp 5 /* Timer Oscillator pin location bit position. */ - -#define NVM_FUSES_BODPD_gm 0x03 /* BOD Operation in Power-Down Mode group mask. */ -#define NVM_FUSES_BODPD_gp 0 /* BOD Operation in Power-Down Mode group position. */ -#define NVM_FUSES_BODPD0_bm (1<<0) /* BOD Operation in Power-Down Mode bit 0 mask. */ -#define NVM_FUSES_BODPD0_bp 0 /* BOD Operation in Power-Down Mode bit 0 position. */ -#define NVM_FUSES_BODPD1_bm (1<<1) /* BOD Operation in Power-Down Mode bit 1 mask. */ -#define NVM_FUSES_BODPD1_bp 1 /* BOD Operation in Power-Down Mode bit 1 position. */ - -/* NVM_FUSES.FUSEBYTE4 bit masks and bit positions */ -#define NVM_FUSES_RSTDISBL_bm 0x10 /* External Reset Disable bit mask. */ -#define NVM_FUSES_RSTDISBL_bp 4 /* External Reset Disable bit position. */ - -#define NVM_FUSES_SUT_gm 0x0C /* Start-up Time group mask. */ -#define NVM_FUSES_SUT_gp 2 /* Start-up Time group position. */ -#define NVM_FUSES_SUT0_bm (1<<2) /* Start-up Time bit 0 mask. */ -#define NVM_FUSES_SUT0_bp 2 /* Start-up Time bit 0 position. */ -#define NVM_FUSES_SUT1_bm (1<<3) /* Start-up Time bit 1 mask. */ -#define NVM_FUSES_SUT1_bp 3 /* Start-up Time bit 1 position. */ - -#define NVM_FUSES_WDLOCK_bm 0x02 /* Watchdog Timer Lock bit mask. */ -#define NVM_FUSES_WDLOCK_bp 1 /* Watchdog Timer Lock bit position. */ - -#define NVM_FUSES_JTAGEN_bm 0x01 /* JTAG Interface Enable bit mask. */ -#define NVM_FUSES_JTAGEN_bp 0 /* JTAG Interface Enable bit position. */ - -/* NVM_FUSES.FUSEBYTE5 bit masks and bit positions */ -#define NVM_FUSES_BODACT_gm 0x30 /* BOD Operation in Active Mode group mask. */ -#define NVM_FUSES_BODACT_gp 4 /* BOD Operation in Active Mode group position. */ -#define NVM_FUSES_BODACT0_bm (1<<4) /* BOD Operation in Active Mode bit 0 mask. */ -#define NVM_FUSES_BODACT0_bp 4 /* BOD Operation in Active Mode bit 0 position. */ -#define NVM_FUSES_BODACT1_bm (1<<5) /* BOD Operation in Active Mode bit 1 mask. */ -#define NVM_FUSES_BODACT1_bp 5 /* BOD Operation in Active Mode bit 1 position. */ - -#define NVM_FUSES_EESAVE_bm 0x08 /* Preserve EEPROM Through Chip Erase bit mask. */ -#define NVM_FUSES_EESAVE_bp 3 /* Preserve EEPROM Through Chip Erase bit position. */ - -#define NVM_FUSES_BODLVL_gm 0x07 /* Brownout Detection Voltage Level group mask. */ -#define NVM_FUSES_BODLVL_gp 0 /* Brownout Detection Voltage Level group position. */ -#define NVM_FUSES_BODLVL0_bm (1<<0) /* Brownout Detection Voltage Level bit 0 mask. */ -#define NVM_FUSES_BODLVL0_bp 0 /* Brownout Detection Voltage Level bit 0 position. */ -#define NVM_FUSES_BODLVL1_bm (1<<1) /* Brownout Detection Voltage Level bit 1 mask. */ -#define NVM_FUSES_BODLVL1_bp 1 /* Brownout Detection Voltage Level bit 1 position. */ -#define NVM_FUSES_BODLVL2_bm (1<<2) /* Brownout Detection Voltage Level bit 2 mask. */ -#define NVM_FUSES_BODLVL2_bp 2 /* Brownout Detection Voltage Level bit 2 position. */ - -/* LOCKBIT - Fuses and Lockbits */ -/* NVM_LOCKBITS.LOCKBITS bit masks and bit positions */ -#define NVM_LOCKBITS_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ -#define NVM_LOCKBITS_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ -#define NVM_LOCKBITS_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ -#define NVM_LOCKBITS_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ -#define NVM_LOCKBITS_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ -#define NVM_LOCKBITS_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ - -#define NVM_LOCKBITS_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ -#define NVM_LOCKBITS_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ -#define NVM_LOCKBITS_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ -#define NVM_LOCKBITS_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ -#define NVM_LOCKBITS_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ -#define NVM_LOCKBITS_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ - -#define NVM_LOCKBITS_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ -#define NVM_LOCKBITS_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ -#define NVM_LOCKBITS_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ -#define NVM_LOCKBITS_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ -#define NVM_LOCKBITS_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ -#define NVM_LOCKBITS_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ - -#define NVM_LOCKBITS_LB_gm 0x03 /* Lock Bits group mask. */ -#define NVM_LOCKBITS_LB_gp 0 /* Lock Bits group position. */ -#define NVM_LOCKBITS_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ -#define NVM_LOCKBITS_LB0_bp 0 /* Lock Bits bit 0 position. */ -#define NVM_LOCKBITS_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ -#define NVM_LOCKBITS_LB1_bp 1 /* Lock Bits bit 1 position. */ - - - -// Generic Port Pins - -#define PIN0_bm 0x01 -#define PIN0_bp 0 -#define PIN1_bm 0x02 -#define PIN1_bp 1 -#define PIN2_bm 0x04 -#define PIN2_bp 2 -#define PIN3_bm 0x08 -#define PIN3_bp 3 -#define PIN4_bm 0x10 -#define PIN4_bp 4 -#define PIN5_bm 0x20 -#define PIN5_bp 5 -#define PIN6_bm 0x40 -#define PIN6_bp 6 -#define PIN7_bm 0x80 -#define PIN7_bp 7 - -/* ========== Interrupt Vector Definitions ========== */ -/* Vector 0 is the reset vector */ - -/* OSC interrupt vectors */ -#define OSC_OSCF_vect_num 1 -#define OSC_OSCF_vect _VECTOR(1) /* Oscillator Failure Interrupt (NMI) */ - -/* PORTC interrupt vectors */ -#define PORTC_INT0_vect_num 2 -#define PORTC_INT0_vect _VECTOR(2) /* External Interrupt 0 */ -#define PORTC_INT1_vect_num 3 -#define PORTC_INT1_vect _VECTOR(3) /* External Interrupt 1 */ - -/* PORTR interrupt vectors */ -#define PORTR_INT0_vect_num 4 -#define PORTR_INT0_vect _VECTOR(4) /* External Interrupt 0 */ -#define PORTR_INT1_vect_num 5 -#define PORTR_INT1_vect _VECTOR(5) /* External Interrupt 1 */ - -/* DMA interrupt vectors */ -#define DMA_CH0_vect_num 6 -#define DMA_CH0_vect _VECTOR(6) /* Channel 0 Interrupt */ -#define DMA_CH1_vect_num 7 -#define DMA_CH1_vect _VECTOR(7) /* Channel 1 Interrupt */ - -/* RTC interrupt vectors */ -#define RTC_OVF_vect_num 10 -#define RTC_OVF_vect _VECTOR(10) /* Overflow Interrupt */ -#define RTC_COMP_vect_num 11 -#define RTC_COMP_vect _VECTOR(11) /* Compare Interrupt */ - -/* TWIC interrupt vectors */ -#define TWIC_TWIS_vect_num 12 -#define TWIC_TWIS_vect _VECTOR(12) /* TWI Slave Interrupt */ -#define TWIC_TWIM_vect_num 13 -#define TWIC_TWIM_vect _VECTOR(13) /* TWI Master Interrupt */ - -/* TCC0 interrupt vectors */ -#define TCC0_OVF_vect_num 14 -#define TCC0_OVF_vect _VECTOR(14) /* Overflow Interrupt */ -#define TCC0_ERR_vect_num 15 -#define TCC0_ERR_vect _VECTOR(15) /* Error Interrupt */ -#define TCC0_CCA_vect_num 16 -#define TCC0_CCA_vect _VECTOR(16) /* Compare or Capture A Interrupt */ -#define TCC0_CCB_vect_num 17 -#define TCC0_CCB_vect _VECTOR(17) /* Compare or Capture B Interrupt */ -#define TCC0_CCC_vect_num 18 -#define TCC0_CCC_vect _VECTOR(18) /* Compare or Capture C Interrupt */ -#define TCC0_CCD_vect_num 19 -#define TCC0_CCD_vect _VECTOR(19) /* Compare or Capture D Interrupt */ - -/* TCC1 interrupt vectors */ -#define TCC1_OVF_vect_num 20 -#define TCC1_OVF_vect _VECTOR(20) /* Overflow Interrupt */ -#define TCC1_ERR_vect_num 21 -#define TCC1_ERR_vect _VECTOR(21) /* Error Interrupt */ -#define TCC1_CCA_vect_num 22 -#define TCC1_CCA_vect _VECTOR(22) /* Compare or Capture A Interrupt */ -#define TCC1_CCB_vect_num 23 -#define TCC1_CCB_vect _VECTOR(23) /* Compare or Capture B Interrupt */ - -/* SPIC interrupt vectors */ -#define SPIC_INT_vect_num 24 -#define SPIC_INT_vect _VECTOR(24) /* SPI Interrupt */ - -/* USARTC0 interrupt vectors */ -#define USARTC0_RXC_vect_num 25 -#define USARTC0_RXC_vect _VECTOR(25) /* Reception Complete Interrupt */ -#define USARTC0_DRE_vect_num 26 -#define USARTC0_DRE_vect _VECTOR(26) /* Data Register Empty Interrupt */ -#define USARTC0_TXC_vect_num 27 -#define USARTC0_TXC_vect _VECTOR(27) /* Transmission Complete Interrupt */ - -/* USB interrupt vectors */ -#define USB_BUSEVENT_vect_num 31 -#define USB_BUSEVENT_vect _VECTOR(31) /* SOF, suspend, resume, reset bus event interrupts, crc, underflow, overflow and stall error interrupts */ -#define USB_TRNCOMPL_vect_num 32 -#define USB_TRNCOMPL_vect _VECTOR(32) /* Transaction complete interrupt */ - -/* LCD interrupt vectors */ -#define LCD_INT_vect_num 35 -#define LCD_INT_vect _VECTOR(35) /* LCD Interrupt */ - -/* AES interrupt vectors */ -#define AES_INT_vect_num 36 -#define AES_INT_vect _VECTOR(36) /* AES Interrupt */ - -/* NVM interrupt vectors */ -#define NVM_EE_vect_num 37 -#define NVM_EE_vect _VECTOR(37) /* EE Interrupt */ -#define NVM_SPM_vect_num 38 -#define NVM_SPM_vect _VECTOR(38) /* SPM Interrupt */ - -/* PORTB interrupt vectors */ -#define PORTB_INT0_vect_num 39 -#define PORTB_INT0_vect _VECTOR(39) /* External Interrupt 0 */ -#define PORTB_INT1_vect_num 40 -#define PORTB_INT1_vect _VECTOR(40) /* External Interrupt 1 */ - -/* ACB interrupt vectors */ -#define ACB_AC0_vect_num 41 -#define ACB_AC0_vect _VECTOR(41) /* AC0 Interrupt */ -#define ACB_AC1_vect_num 42 -#define ACB_AC1_vect _VECTOR(42) /* AC1 Interrupt */ -#define ACB_ACW_vect_num 43 -#define ACB_ACW_vect _VECTOR(43) /* ACW Window Mode Interrupt */ - -/* ADCB interrupt vectors */ -#define ADCB_CH0_vect_num 44 -#define ADCB_CH0_vect _VECTOR(44) /* Interrupt 0 */ - -/* PORTD interrupt vectors */ -#define PORTD_INT0_vect_num 48 -#define PORTD_INT0_vect _VECTOR(48) /* External Interrupt 0 */ -#define PORTD_INT1_vect_num 49 -#define PORTD_INT1_vect _VECTOR(49) /* External Interrupt 1 */ - -/* PORTG interrupt vectors */ -#define PORTG_INT0_vect_num 50 -#define PORTG_INT0_vect _VECTOR(50) /* External Interrupt 0 */ -#define PORTG_INT1_vect_num 51 -#define PORTG_INT1_vect _VECTOR(51) /* External Interrupt 1 */ - -/* PORTM interrupt vectors */ -#define PORTM_INT0_vect_num 52 -#define PORTM_INT0_vect _VECTOR(52) /* External Interrupt 0 */ -#define PORTM_INT1_vect_num 53 -#define PORTM_INT1_vect _VECTOR(53) /* External Interrupt 1 */ - -/* PORTE interrupt vectors */ -#define PORTE_INT0_vect_num 54 -#define PORTE_INT0_vect _VECTOR(54) /* External Interrupt 0 */ -#define PORTE_INT1_vect_num 55 -#define PORTE_INT1_vect _VECTOR(55) /* External Interrupt 1 */ - -/* TCE0 interrupt vectors */ -#define TCE0_OVF_vect_num 58 -#define TCE0_OVF_vect _VECTOR(58) /* Overflow Interrupt */ -#define TCE0_ERR_vect_num 59 -#define TCE0_ERR_vect _VECTOR(59) /* Error Interrupt */ -#define TCE0_CCA_vect_num 60 -#define TCE0_CCA_vect _VECTOR(60) /* Compare or Capture A Interrupt */ -#define TCE0_CCB_vect_num 61 -#define TCE0_CCB_vect _VECTOR(61) /* Compare or Capture B Interrupt */ -#define TCE0_CCC_vect_num 62 -#define TCE0_CCC_vect _VECTOR(62) /* Compare or Capture C Interrupt */ -#define TCE0_CCD_vect_num 63 -#define TCE0_CCD_vect _VECTOR(63) /* Compare or Capture D Interrupt */ - -/* USARTE0 interrupt vectors */ -#define USARTE0_RXC_vect_num 69 -#define USARTE0_RXC_vect _VECTOR(69) /* Reception Complete Interrupt */ -#define USARTE0_DRE_vect_num 70 -#define USARTE0_DRE_vect _VECTOR(70) /* Data Register Empty Interrupt */ -#define USARTE0_TXC_vect_num 71 -#define USARTE0_TXC_vect _VECTOR(71) /* Transmission Complete Interrupt */ - -/* PORTA interrupt vectors */ -#define PORTA_INT0_vect_num 75 -#define PORTA_INT0_vect _VECTOR(75) /* External Interrupt 0 */ -#define PORTA_INT1_vect_num 76 -#define PORTA_INT1_vect _VECTOR(76) /* External Interrupt 1 */ - -/* ACA interrupt vectors */ -#define ACA_AC0_vect_num 77 -#define ACA_AC0_vect _VECTOR(77) /* AC0 Interrupt */ -#define ACA_AC1_vect_num 78 -#define ACA_AC1_vect _VECTOR(78) /* AC1 Interrupt */ -#define ACA_ACW_vect_num 79 -#define ACA_ACW_vect _VECTOR(79) /* ACW Window Mode Interrupt */ - -/* ADCA interrupt vectors */ -#define ADCA_CH0_vect_num 80 -#define ADCA_CH0_vect _VECTOR(80) /* Interrupt 0 */ - -#define _VECTOR_SIZE 4 /* Size of individual vector. */ -#define _VECTORS_SIZE (81 * _VECTOR_SIZE) - - -/* ========== Constants ========== */ - -#define PROGMEM_START (0x0000) -#define PROGMEM_SIZE (69632) -#define PROGMEM_END (PROGMEM_START + PROGMEM_SIZE - 1) - -#define APP_SECTION_START (0x0000) -#define APP_SECTION_SIZE (65536) -#define APP_SECTION_PAGE_SIZE (256) -#define APP_SECTION_END (APP_SECTION_START + APP_SECTION_SIZE - 1) - -#define APPTABLE_SECTION_START (0xF000) -#define APPTABLE_SECTION_SIZE (4096) -#define APPTABLE_SECTION_PAGE_SIZE (256) -#define APPTABLE_SECTION_END (APPTABLE_SECTION_START + APPTABLE_SECTION_SIZE - 1) - -#define BOOT_SECTION_START (0x10000) -#define BOOT_SECTION_SIZE (4096) -#define BOOT_SECTION_PAGE_SIZE (256) -#define BOOT_SECTION_END (BOOT_SECTION_START + BOOT_SECTION_SIZE - 1) - -#define DATAMEM_START (0x0000) -#define DATAMEM_SIZE (12288) -#define DATAMEM_END (DATAMEM_START + DATAMEM_SIZE - 1) - -#define IO_START (0x0000) -#define IO_SIZE (4096) -#define IO_PAGE_SIZE (0) -#define IO_END (IO_START + IO_SIZE - 1) - -#define MAPPED_EEPROM_START (0x1000) -#define MAPPED_EEPROM_SIZE (2048) -#define MAPPED_EEPROM_PAGE_SIZE (0) -#define MAPPED_EEPROM_END (MAPPED_EEPROM_START + MAPPED_EEPROM_SIZE - 1) - -#define INTERNAL_SRAM_START (0x2000) -#define INTERNAL_SRAM_SIZE (4096) -#define INTERNAL_SRAM_PAGE_SIZE (0) -#define INTERNAL_SRAM_END (INTERNAL_SRAM_START + INTERNAL_SRAM_SIZE - 1) - -#define EEPROM_START (0x0000) -#define EEPROM_SIZE (2048) -#define EEPROM_PAGE_SIZE (32) -#define EEPROM_END (EEPROM_START + EEPROM_SIZE - 1) - -#define SIGNATURES_START (0x0000) -#define SIGNATURES_SIZE (3) -#define SIGNATURES_PAGE_SIZE (0) -#define SIGNATURES_END (SIGNATURES_START + SIGNATURES_SIZE - 1) - -#define FUSES_START (0x0000) -#define FUSES_SIZE (6) -#define FUSES_PAGE_SIZE (0) -#define FUSES_END (FUSES_START + FUSES_SIZE - 1) - -#define LOCKBITS_START (0x0000) -#define LOCKBITS_SIZE (1) -#define LOCKBITS_PAGE_SIZE (0) -#define LOCKBITS_END (LOCKBITS_START + LOCKBITS_SIZE - 1) - -#define USER_SIGNATURES_START (0x0000) -#define USER_SIGNATURES_SIZE (256) -#define USER_SIGNATURES_PAGE_SIZE (256) -#define USER_SIGNATURES_END (USER_SIGNATURES_START + USER_SIGNATURES_SIZE - 1) - -#define PROD_SIGNATURES_START (0x0000) -#define PROD_SIGNATURES_SIZE (52) -#define PROD_SIGNATURES_PAGE_SIZE (256) -#define PROD_SIGNATURES_END (PROD_SIGNATURES_START + PROD_SIGNATURES_SIZE - 1) - -#define FLASHSTART PROGMEM_START -#define FLASHEND PROGMEM_END -#define SPM_PAGESIZE 256 -#define RAMSTART INTERNAL_SRAM_START -#define RAMSIZE INTERNAL_SRAM_SIZE -#define RAMEND INTERNAL_SRAM_END -#define E2END EEPROM_END -#define E2PAGESIZE EEPROM_PAGE_SIZE - - -/* ========== Fuses ========== */ -#define FUSE_MEMORY_SIZE 6 - -/* Fuse Byte 0 */ -#define FUSE_JTAGUSERID0 (unsigned char)~_BV(0) /* JTAG User ID Bit 0 */ -#define FUSE_JTAGUSERID1 (unsigned char)~_BV(1) /* JTAG User ID Bit 1 */ -#define FUSE_JTAGUSERID2 (unsigned char)~_BV(2) /* JTAG User ID Bit 2 */ -#define FUSE_JTAGUSERID3 (unsigned char)~_BV(3) /* JTAG User ID Bit 3 */ -#define FUSE_JTAGUSERID4 (unsigned char)~_BV(4) /* JTAG User ID Bit 4 */ -#define FUSE_JTAGUSERID5 (unsigned char)~_BV(5) /* JTAG User ID Bit 5 */ -#define FUSE_JTAGUSERID6 (unsigned char)~_BV(6) /* JTAG User ID Bit 6 */ -#define FUSE_JTAGUSERID7 (unsigned char)~_BV(7) /* JTAG User ID Bit 7 */ -#define FUSE0_DEFAULT (0xFF) - -/* Fuse Byte 1 */ -#define FUSE_WDP0 (unsigned char)~_BV(0) /* Watchdog Timeout Period Bit 0 */ -#define FUSE_WDP1 (unsigned char)~_BV(1) /* Watchdog Timeout Period Bit 1 */ -#define FUSE_WDP2 (unsigned char)~_BV(2) /* Watchdog Timeout Period Bit 2 */ -#define FUSE_WDP3 (unsigned char)~_BV(3) /* Watchdog Timeout Period Bit 3 */ -#define FUSE_WDWP0 (unsigned char)~_BV(4) /* Watchdog Window Timeout Period Bit 0 */ -#define FUSE_WDWP1 (unsigned char)~_BV(5) /* Watchdog Window Timeout Period Bit 1 */ -#define FUSE_WDWP2 (unsigned char)~_BV(6) /* Watchdog Window Timeout Period Bit 2 */ -#define FUSE_WDWP3 (unsigned char)~_BV(7) /* Watchdog Window Timeout Period Bit 3 */ -#define FUSE1_DEFAULT (0xFF) - -/* Fuse Byte 2 */ -#define FUSE_BODPD0 (unsigned char)~_BV(0) /* BOD Operation in Power-Down Mode Bit 0 */ -#define FUSE_BODPD1 (unsigned char)~_BV(1) /* BOD Operation in Power-Down Mode Bit 1 */ -#define FUSE_TOSCSEL (unsigned char)~_BV(5) /* Timer Oscillator pin location */ -#define FUSE_BOOTRST (unsigned char)~_BV(6) /* Boot Loader Section Reset Vector */ -#define FUSE2_DEFAULT (0xFF) - -/* Fuse Byte 3 Reserved */ - -/* Fuse Byte 4 */ -#define FUSE_JTAGEN (unsigned char)~_BV(0) /* JTAG Interface Enable */ -#define FUSE_WDLOCK (unsigned char)~_BV(1) /* Watchdog Timer Lock */ -#define FUSE_SUT0 (unsigned char)~_BV(2) /* Start-up Time Bit 0 */ -#define FUSE_SUT1 (unsigned char)~_BV(3) /* Start-up Time Bit 1 */ -#define FUSE_RSTDISBL (unsigned char)~_BV(4) /* External Reset Disable */ -#define FUSE4_DEFAULT (0xFF) - -/* Fuse Byte 5 */ -#define FUSE_BODLVL0 (unsigned char)~_BV(0) /* Brownout Detection Voltage Level Bit 0 */ -#define FUSE_BODLVL1 (unsigned char)~_BV(1) /* Brownout Detection Voltage Level Bit 1 */ -#define FUSE_BODLVL2 (unsigned char)~_BV(2) /* Brownout Detection Voltage Level Bit 2 */ -#define FUSE_EESAVE (unsigned char)~_BV(3) /* Preserve EEPROM Through Chip Erase */ -#define FUSE_BODACT0 (unsigned char)~_BV(4) /* BOD Operation in Active Mode Bit 0 */ -#define FUSE_BODACT1 (unsigned char)~_BV(5) /* BOD Operation in Active Mode Bit 1 */ -#define FUSE5_DEFAULT (0xFF) - -/* ========== Lock Bits ========== */ -#define __LOCK_BITS_EXIST -#define __BOOT_LOCK_APPLICATION_TABLE_BITS_EXIST -#define __BOOT_LOCK_APPLICATION_BITS_EXIST -#define __BOOT_LOCK_BOOT_BITS_EXIST - -/* ========== Signature ========== */ -#define SIGNATURE_0 0x1E -#define SIGNATURE_1 0x96 -#define SIGNATURE_2 0x52 - -/* ========== Power Reduction Condition Definitions ========== */ - -/* PR.PRGEN */ -#define __AVR_HAVE_PRGEN (PR_LCD_bm|PR_USB_bm|PR_AES_bm|PR_RTC_bm|PR_EVSYS_bm|PR_DMA_bm) -#define __AVR_HAVE_PRGEN_LCD -#define __AVR_HAVE_PRGEN_USB -#define __AVR_HAVE_PRGEN_AES -#define __AVR_HAVE_PRGEN_RTC -#define __AVR_HAVE_PRGEN_EVSYS -#define __AVR_HAVE_PRGEN_DMA - -/* PR.PRPA */ -#define __AVR_HAVE_PRPA (PR_ADC_bm|PR_AC_bm) -#define __AVR_HAVE_PRPA_ADC -#define __AVR_HAVE_PRPA_AC - -/* PR.PRPB */ -#define __AVR_HAVE_PRPB (PR_ADC_bm|PR_AC_bm) -#define __AVR_HAVE_PRPB_ADC -#define __AVR_HAVE_PRPB_AC - -/* PR.PRPC */ -#define __AVR_HAVE_PRPC (PR_TWI_bm|PR_USART0_bm|PR_SPI_bm|PR_HIRES_bm|PR_TC1_bm|PR_TC0_bm) -#define __AVR_HAVE_PRPC_TWI -#define __AVR_HAVE_PRPC_USART0 -#define __AVR_HAVE_PRPC_SPI -#define __AVR_HAVE_PRPC_HIRES -#define __AVR_HAVE_PRPC_TC1 -#define __AVR_HAVE_PRPC_TC0 - -/* PR.PRPE */ -#define __AVR_HAVE_PRPE (PR_USART0_bm|PR_TC0_bm) -#define __AVR_HAVE_PRPE_USART0 -#define __AVR_HAVE_PRPE_TC0 - - -#endif /* #ifdef _AVR_ATXMEGA64B1_H_INCLUDED */ - diff --git a/arduino/hardware/tools/avr/avr/include/avr/iox64b3.h b/arduino/hardware/tools/avr/avr/include/avr/iox64b3.h deleted file mode 100644 index 1cdf5de..0000000 --- a/arduino/hardware/tools/avr/avr/include/avr/iox64b3.h +++ /dev/null @@ -1,6288 +0,0 @@ -/***************************************************************************** - * - * Copyright (C) 2015 Atmel Corporation - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * - * * Neither the name of the copyright holders nor the names of - * contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - ****************************************************************************/ - - -#ifndef _AVR_IO_H_ -# error "Include instead of this file." -#endif - -#ifndef _AVR_IOXXX_H_ -# define _AVR_IOXXX_H_ "iox64b3.h" -#else -# error "Attempt to include more than one file." -#endif - -#ifndef _AVR_ATXMEGA64B3_H_INCLUDED -#define _AVR_ATXMEGA64B3_H_INCLUDED - -/* Ungrouped common registers */ -#define GPIOR0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ -#define GPIOR1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ -#define GPIOR2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ -#define GPIOR3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ - -/* Deprecated */ -#define GPIO0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ -#define GPIO1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ -#define GPIO2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ -#define GPIO3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ - -#define CCP _SFR_MEM8(0x0034) /* Configuration Change Protection */ -#define RAMPD _SFR_MEM8(0x0038) /* Ramp D */ -#define RAMPX _SFR_MEM8(0x0039) /* Ramp X */ -#define RAMPY _SFR_MEM8(0x003A) /* Ramp Y */ -#define RAMPZ _SFR_MEM8(0x003B) /* Ramp Z */ -#define EIND _SFR_MEM8(0x003C) /* Extended Indirect Jump */ -#define SPL _SFR_MEM8(0x003D) /* Stack Pointer Low */ -#define SPH _SFR_MEM8(0x003E) /* Stack Pointer High */ -#define SREG _SFR_MEM8(0x003F) /* Status Register */ - -/* C Language Only */ -#if !defined (__ASSEMBLER__) - -#include - -typedef volatile uint8_t register8_t; -typedef volatile uint16_t register16_t; -typedef volatile uint32_t register32_t; - - -#ifdef _WORDREGISTER -#undef _WORDREGISTER -#endif -#define _WORDREGISTER(regname) \ - __extension__ union \ - { \ - register16_t regname; \ - struct \ - { \ - register8_t regname ## L; \ - register8_t regname ## H; \ - }; \ - } - -#ifdef _DWORDREGISTER -#undef _DWORDREGISTER -#endif -#define _DWORDREGISTER(regname) \ - __extension__ union \ - { \ - register32_t regname; \ - struct \ - { \ - register8_t regname ## 0; \ - register8_t regname ## 1; \ - register8_t regname ## 2; \ - register8_t regname ## 3; \ - }; \ - } - - -/* -========================================================================== -IO Module Structures -========================================================================== -*/ - - -/* --------------------------------------------------------------------------- -VPORT - Virtual Ports --------------------------------------------------------------------------- -*/ - -/* Virtual Port */ -typedef struct VPORT_struct -{ - register8_t DIR; /* I/O Port Data Direction */ - register8_t OUT; /* I/O Port Output */ - register8_t IN; /* I/O Port Input */ - register8_t INTFLAGS; /* Interrupt Flag Register */ -} VPORT_t; - - -/* --------------------------------------------------------------------------- -XOCD - On-Chip Debug System --------------------------------------------------------------------------- -*/ - -/* On-Chip Debug System */ -typedef struct OCD_struct -{ - register8_t OCDR0; /* OCD Register 0 */ - register8_t OCDR1; /* OCD Register 1 */ -} OCD_t; - - -/* --------------------------------------------------------------------------- -CPU - CPU --------------------------------------------------------------------------- -*/ - -/* CCP signatures */ -typedef enum CCP_enum -{ - CCP_SPM_gc = (0x9D<<0), /* SPM Instruction Protection */ - CCP_IOREG_gc = (0xD8<<0), /* IO Register Protection */ -} CCP_t; - - -/* --------------------------------------------------------------------------- -CLK - Clock System --------------------------------------------------------------------------- -*/ - -/* Clock System */ -typedef struct CLK_struct -{ - register8_t CTRL; /* Control Register */ - register8_t PSCTRL; /* Prescaler Control Register */ - register8_t LOCK; /* Lock register */ - register8_t RTCCTRL; /* RTC Control Register */ - register8_t USBCTRL; /* USB Control Register */ -} CLK_t; - -/* System Clock Selection */ -typedef enum CLK_SCLKSEL_enum -{ - CLK_SCLKSEL_RC2M_gc = (0x00<<0), /* Internal 2 MHz RC Oscillator */ - CLK_SCLKSEL_RC32M_gc = (0x01<<0), /* Internal 32 MHz RC Oscillator */ - CLK_SCLKSEL_RC32K_gc = (0x02<<0), /* Internal 32.768 kHz RC Oscillator */ - CLK_SCLKSEL_XOSC_gc = (0x03<<0), /* External Crystal Oscillator or Clock */ - CLK_SCLKSEL_PLL_gc = (0x04<<0), /* Phase Locked Loop */ -} CLK_SCLKSEL_t; - -/* Prescaler A Division Factor */ -typedef enum CLK_PSADIV_enum -{ - CLK_PSADIV_1_gc = (0x00<<2), /* Divide by 1 */ - CLK_PSADIV_2_gc = (0x01<<2), /* Divide by 2 */ - CLK_PSADIV_4_gc = (0x03<<2), /* Divide by 4 */ - CLK_PSADIV_8_gc = (0x05<<2), /* Divide by 8 */ - CLK_PSADIV_16_gc = (0x07<<2), /* Divide by 16 */ - CLK_PSADIV_32_gc = (0x09<<2), /* Divide by 32 */ - CLK_PSADIV_64_gc = (0x0B<<2), /* Divide by 64 */ - CLK_PSADIV_128_gc = (0x0D<<2), /* Divide by 128 */ - CLK_PSADIV_256_gc = (0x0F<<2), /* Divide by 256 */ - CLK_PSADIV_512_gc = (0x11<<2), /* Divide by 512 */ -} CLK_PSADIV_t; - -/* Prescaler B and C Division Factor */ -typedef enum CLK_PSBCDIV_enum -{ - CLK_PSBCDIV_1_1_gc = (0x00<<0), /* Divide B by 1 and C by 1 */ - CLK_PSBCDIV_1_2_gc = (0x01<<0), /* Divide B by 1 and C by 2 */ - CLK_PSBCDIV_4_1_gc = (0x02<<0), /* Divide B by 4 and C by 1 */ - CLK_PSBCDIV_2_2_gc = (0x03<<0), /* Divide B by 2 and C by 2 */ -} CLK_PSBCDIV_t; - -/* RTC Clock Source */ -typedef enum CLK_RTCSRC_enum -{ - CLK_RTCSRC_ULP_gc = (0x00<<1), /* 1.024 kHz from internal 32kHz ULP */ - CLK_RTCSRC_TOSC_gc = (0x01<<1), /* 1.024 kHz from 32.768 kHz crystal oscillator on TOSC */ - CLK_RTCSRC_RCOSC_gc = (0x02<<1), /* 1.024 kHz from internal 32.768 kHz RC oscillator */ - CLK_RTCSRC_TOSC32_gc = (0x05<<1), /* 32.768 kHz from 32.768 kHz crystal oscillator on TOSC */ - CLK_RTCSRC_RCOSC32_gc = (0x06<<1), /* 32.768 kHz from internal 32.768 kHz RC oscillator */ - CLK_RTCSRC_EXTCLK_gc = (0x07<<1), /* External Clock from TOSC1 */ -} CLK_RTCSRC_t; - -/* USB Prescaler Division Factor */ -typedef enum CLK_USBPSDIV_enum -{ - CLK_USBPSDIV_1_gc = (0x00<<3), /* Divide by 1 */ - CLK_USBPSDIV_2_gc = (0x01<<3), /* Divide by 2 */ - CLK_USBPSDIV_4_gc = (0x02<<3), /* Divide by 4 */ - CLK_USBPSDIV_8_gc = (0x03<<3), /* Divide by 8 */ - CLK_USBPSDIV_16_gc = (0x04<<3), /* Divide by 16 */ - CLK_USBPSDIV_32_gc = (0x05<<3), /* Divide by 32 */ -} CLK_USBPSDIV_t; - -/* USB Clock Source */ -typedef enum CLK_USBSRC_enum -{ - CLK_USBSRC_PLL_gc = (0x00<<1), /* PLL */ - CLK_USBSRC_RC32M_gc = (0x01<<1), /* Internal 32 MHz RC Oscillator */ -} CLK_USBSRC_t; - - -/* --------------------------------------------------------------------------- -SLEEP - Sleep Controller --------------------------------------------------------------------------- -*/ - -/* Sleep Controller */ -typedef struct SLEEP_struct -{ - register8_t CTRL; /* Control Register */ -} SLEEP_t; - -/* Sleep Mode */ -typedef enum SLEEP_SMODE_enum -{ - SLEEP_SMODE_IDLE_gc = (0x00<<1), /* Idle mode */ - SLEEP_SMODE_PDOWN_gc = (0x02<<1), /* Power-down Mode */ - SLEEP_SMODE_PSAVE_gc = (0x03<<1), /* Power-save Mode */ - SLEEP_SMODE_STDBY_gc = (0x06<<1), /* Standby Mode */ - SLEEP_SMODE_ESTDBY_gc = (0x07<<1), /* Extended Standby Mode */ -} SLEEP_SMODE_t; - - - -#define SLEEP_MODE_IDLE (0x00<<1) -#define SLEEP_MODE_PWR_DOWN (0x02<<1) -#define SLEEP_MODE_PWR_SAVE (0x03<<1) -#define SLEEP_MODE_STANDBY (0x06<<1) -#define SLEEP_MODE_EXT_STANDBY (0x07<<1) -/* --------------------------------------------------------------------------- -OSC - Oscillator --------------------------------------------------------------------------- -*/ - -/* Oscillator */ -typedef struct OSC_struct -{ - register8_t CTRL; /* Control Register */ - register8_t STATUS; /* Status Register */ - register8_t XOSCCTRL; /* External Oscillator Control Register */ - register8_t XOSCFAIL; /* Oscillator Failure Detection Register */ - register8_t RC32KCAL; /* 32.768 kHz Internal Oscillator Calibration Register */ - register8_t PLLCTRL; /* PLL Control Register */ - register8_t DFLLCTRL; /* DFLL Control Register */ -} OSC_t; - -/* Oscillator Frequency Range */ -typedef enum OSC_FRQRANGE_enum -{ - OSC_FRQRANGE_04TO2_gc = (0x00<<6), /* 0.4 - 2 MHz */ - OSC_FRQRANGE_2TO9_gc = (0x01<<6), /* 2 - 9 MHz */ - OSC_FRQRANGE_9TO12_gc = (0x02<<6), /* 9 - 12 MHz */ - OSC_FRQRANGE_12TO16_gc = (0x03<<6), /* 12 - 16 MHz */ -} OSC_FRQRANGE_t; - -/* External Oscillator Selection and Startup Time */ -typedef enum OSC_XOSCSEL_enum -{ - OSC_XOSCSEL_EXTCLK_gc = (0x00<<0), /* External Clock on port R1 - 6 CLK */ - OSC_XOSCSEL_EXTCLK_C0_gc = (0x01<<0), /* External Clock on port C0 - 6 CLK */ - OSC_XOSCSEL_EXTCLK_C1_gc = (0x05<<0), /* External Clock on port C1 - 6 CLK */ - OSC_XOSCSEL_EXTCLK_C2_gc = (0x09<<0), /* External Clock on port C2 - 6 CLK */ - OSC_XOSCSEL_EXTCLK_C3_gc = (0x0D<<0), /* External Clock on port C3 - 6 CLK */ - OSC_XOSCSEL_EXTCLK_C4_gc = (0x11<<0), /* External Clock on port C4 - 6 CLK */ - OSC_XOSCSEL_EXTCLK_C5_gc = (0x15<<0), /* External Clock on port C5 - 6 CLK */ - OSC_XOSCSEL_EXTCLK_C6_gc = (0x19<<0), /* External Clock on port C6 - 6 CLK */ - OSC_XOSCSEL_EXTCLK_C7_gc = (0x1D<<0), /* External Clock on port C7 - 6 CLK */ - OSC_XOSCSEL_32KHz_gc = (0x02<<0), /* 32kHz TOSC - 32K CLK */ - OSC_XOSCSEL_XTAL_256CLK_gc = (0x03<<0), /* 0.4-16MHz XTAL - 256 CLK */ - OSC_XOSCSEL_XTAL_1KCLK_gc = (0x07<<0), /* 0.4-16MHz XTAL - 1K CLK */ - OSC_XOSCSEL_XTAL_16KCLK_gc = (0x0B<<0), /* 0.4-16MHz XTAL - 16K CLK */ -} OSC_XOSCSEL_t; - -/* PLL Clock Source */ -typedef enum OSC_PLLSRC_enum -{ - OSC_PLLSRC_RC2M_gc = (0x00<<6), /* Internal 2 MHz RC Oscillator */ - OSC_PLLSRC_RC32M_gc = (0x02<<6), /* Internal 32 MHz RC Oscillator */ - OSC_PLLSRC_XOSC_gc = (0x03<<6), /* External Oscillator */ -} OSC_PLLSRC_t; - -/* 2 MHz DFLL Calibration Reference */ -typedef enum OSC_RC2MCREF_enum -{ - OSC_RC2MCREF_RC32K_gc = (0x00<<0), /* Internal 32.768 kHz RC Oscillator */ - OSC_RC2MCREF_XOSC32K_gc = (0x01<<0), /* External 32.768 kHz Crystal Oscillator */ -} OSC_RC2MCREF_t; - -/* 32 MHz DFLL Calibration Reference */ -typedef enum OSC_RC32MCREF_enum -{ - OSC_RC32MCREF_RC32K_gc = (0x00<<1), /* Internal 32.768 kHz RC Oscillator */ - OSC_RC32MCREF_XOSC32K_gc = (0x01<<1), /* External 32.768 kHz Crystal Oscillator */ - OSC_RC32MCREF_USBSOF_gc = (0x02<<1), /* USB Start of Frame */ -} OSC_RC32MCREF_t; - - -/* --------------------------------------------------------------------------- -DFLL - DFLL --------------------------------------------------------------------------- -*/ - -/* DFLL */ -typedef struct DFLL_struct -{ - register8_t CTRL; /* Control Register */ - register8_t reserved_0x01; - register8_t CALA; /* Calibration Register A */ - register8_t CALB; /* Calibration Register B */ - register8_t COMP0; /* Oscillator Compare Register 0 */ - register8_t COMP1; /* Oscillator Compare Register 1 */ - register8_t COMP2; /* Oscillator Compare Register 2 */ - register8_t reserved_0x07; -} DFLL_t; - - -/* --------------------------------------------------------------------------- -PR - Power Reduction --------------------------------------------------------------------------- -*/ - -/* Power Reduction */ -typedef struct PR_struct -{ - register8_t PRGEN; /* General Power Reduction */ - register8_t PRPA; /* Power Reduction Port A */ - register8_t PRPB; /* Power Reduction Port B */ - register8_t PRPC; /* Power Reduction Port C */ - register8_t reserved_0x04; - register8_t PRPE; /* Power Reduction Port E */ -} PR_t; - - -/* --------------------------------------------------------------------------- -RST - Reset --------------------------------------------------------------------------- -*/ - -/* Reset */ -typedef struct RST_struct -{ - register8_t STATUS; /* Status Register */ - register8_t CTRL; /* Control Register */ -} RST_t; - - -/* --------------------------------------------------------------------------- -WDT - Watch-Dog Timer --------------------------------------------------------------------------- -*/ - -/* Watch-Dog Timer */ -typedef struct WDT_struct -{ - register8_t CTRL; /* Control */ - register8_t WINCTRL; /* Windowed Mode Control */ - register8_t STATUS; /* Status */ -} WDT_t; - -/* Period setting */ -typedef enum WDT_PER_enum -{ - WDT_PER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ - WDT_PER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ - WDT_PER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ - WDT_PER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ - WDT_PER_128CLK_gc = (0x04<<2), /* 128 cycles (0.128s @ 3.3V) */ - WDT_PER_256CLK_gc = (0x05<<2), /* 256 cycles (0.256s @ 3.3V) */ - WDT_PER_512CLK_gc = (0x06<<2), /* 512 cycles (0.512s @ 3.3V) */ - WDT_PER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ - WDT_PER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ - WDT_PER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ - WDT_PER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ -} WDT_PER_t; - -/* Closed window period */ -typedef enum WDT_WPER_enum -{ - WDT_WPER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ - WDT_WPER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ - WDT_WPER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ - WDT_WPER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ - WDT_WPER_128CLK_gc = (0x04<<2), /* 128 cycles (0.128s @ 3.3V) */ - WDT_WPER_256CLK_gc = (0x05<<2), /* 256 cycles (0.256s @ 3.3V) */ - WDT_WPER_512CLK_gc = (0x06<<2), /* 512 cycles (0.512s @ 3.3V) */ - WDT_WPER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ - WDT_WPER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ - WDT_WPER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ - WDT_WPER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ -} WDT_WPER_t; - - -/* --------------------------------------------------------------------------- -MCU - MCU Control --------------------------------------------------------------------------- -*/ - -/* MCU Control */ -typedef struct MCU_struct -{ - register8_t DEVID0; /* Device ID byte 0 */ - register8_t DEVID1; /* Device ID byte 1 */ - register8_t DEVID2; /* Device ID byte 2 */ - register8_t REVID; /* Revision ID */ - register8_t JTAGUID; /* JTAG User ID */ - register8_t reserved_0x05; - register8_t MCUCR; /* MCU Control */ - register8_t ANAINIT; /* Analog Startup Delay */ - register8_t EVSYSLOCK; /* Event System Lock */ - register8_t AWEXLOCK; /* AWEX Lock */ - register8_t reserved_0x0A; - register8_t reserved_0x0B; -} MCU_t; - - -/* --------------------------------------------------------------------------- -PMIC - Programmable Multi-level Interrupt Controller --------------------------------------------------------------------------- -*/ - -/* Programmable Multi-level Interrupt Controller */ -typedef struct PMIC_struct -{ - register8_t STATUS; /* Status Register */ - register8_t INTPRI; /* Interrupt Priority */ - register8_t CTRL; /* Control Register */ - register8_t reserved_0x03; - register8_t reserved_0x04; - register8_t reserved_0x05; - register8_t reserved_0x06; - register8_t reserved_0x07; - register8_t reserved_0x08; - register8_t reserved_0x09; - register8_t reserved_0x0A; - register8_t reserved_0x0B; - register8_t reserved_0x0C; - register8_t reserved_0x0D; - register8_t reserved_0x0E; - register8_t reserved_0x0F; -} PMIC_t; - - -/* --------------------------------------------------------------------------- -PORTCFG - Port Configuration --------------------------------------------------------------------------- -*/ - -/* I/O port Configuration */ -typedef struct PORTCFG_struct -{ - register8_t MPCMASK; /* Multi-pin Configuration Mask */ - register8_t reserved_0x01; - register8_t VPCTRLA; /* Virtual Port Control Register A */ - register8_t VPCTRLB; /* Virtual Port Control Register B */ - register8_t CLKEVOUT; /* Clock and Event Out Register */ - register8_t reserved_0x05; - register8_t EVOUTSEL; /* Event Output Select */ -} PORTCFG_t; - -/* Virtual Port Mapping */ -typedef enum PORTCFG_VP02MAP_enum -{ - PORTCFG_VP02MAP_PORTA_gc = (0x00<<0), /* Mapped To PORTA */ - PORTCFG_VP02MAP_PORTB_gc = (0x01<<0), /* Mapped To PORTB */ - PORTCFG_VP02MAP_PORTC_gc = (0x02<<0), /* Mapped To PORTC */ - PORTCFG_VP02MAP_PORTD_gc = (0x03<<0), /* Mapped To PORTD */ - PORTCFG_VP02MAP_PORTE_gc = (0x04<<0), /* Mapped To PORTE */ - PORTCFG_VP02MAP_PORTG_gc = (0x06<<0), /* Mapped To PORTG */ - PORTCFG_VP02MAP_PORTM_gc = (0x0B<<0), /* Mapped To PORTM */ - PORTCFG_VP02MAP_PORTR_gc = (0x0F<<0), /* Mapped To PORTR */ -} PORTCFG_VP02MAP_t; - -/* Virtual Port Mapping */ -typedef enum PORTCFG_VP13MAP_enum -{ - PORTCFG_VP13MAP_PORTA_gc = (0x00<<4), /* Mapped To PORTA */ - PORTCFG_VP13MAP_PORTB_gc = (0x01<<4), /* Mapped To PORTB */ - PORTCFG_VP13MAP_PORTC_gc = (0x02<<4), /* Mapped To PORTC */ - PORTCFG_VP13MAP_PORTD_gc = (0x03<<4), /* Mapped To PORTD */ - PORTCFG_VP13MAP_PORTE_gc = (0x04<<4), /* Mapped To PORTE */ - PORTCFG_VP13MAP_PORTG_gc = (0x06<<4), /* Mapped To PORTG */ - PORTCFG_VP13MAP_PORTM_gc = (0x0B<<4), /* Mapped To PORTM */ - PORTCFG_VP13MAP_PORTR_gc = (0x0F<<4), /* Mapped To PORTR */ -} PORTCFG_VP13MAP_t; - -/* System Clock Output Port */ -typedef enum PORTCFG_CLKOUT_enum -{ - PORTCFG_CLKOUT_OFF_gc = (0x00<<0), /* System Clock Output Disabled */ - PORTCFG_CLKOUT_PC_gc = (0x01<<0), /* System Clock Output on Port C */ - PORTCFG_CLKOUT_PE_gc = (0x03<<0), /* System Clock Output on Port E */ -} PORTCFG_CLKOUT_t; - -/* Peripheral Clock Output Select */ -typedef enum PORTCFG_CLKOUTSEL_enum -{ - PORTCFG_CLKOUTSEL_CLK1X_gc = (0x00<<2), /* 1x Peripheral Clock Output to pin */ - PORTCFG_CLKOUTSEL_CLK2X_gc = (0x01<<2), /* 2x Peripheral Clock Output to pin */ - PORTCFG_CLKOUTSEL_CLK4X_gc = (0x02<<2), /* 4x Peripheral Clock Output to pin */ -} PORTCFG_CLKOUTSEL_t; - -/* Event Output Port */ -typedef enum PORTCFG_EVOUT_enum -{ - PORTCFG_EVOUT_OFF_gc = (0x00<<4), /* Event Output Disabled */ - PORTCFG_EVOUT_PC_gc = (0x01<<4), /* Event Channel 0 Output on Port C */ - PORTCFG_EVOUT_PE_gc = (0x03<<4), /* Event Channel 0 Output on Port E */ -} PORTCFG_EVOUT_t; - -/* Clock and Event Output Port */ -typedef enum PORTCFG_CLKEVPIN_enum -{ - PORTCFG_CLKEVPIN_PIN7_gc = (0x00<<7), /* Clock and Event Ouput on PIN 7 */ - PORTCFG_CLKEVPIN_PIN4_gc = (0x01<<7), /* Clock and Event Ouput on PIN 4 */ -} PORTCFG_CLKEVPIN_t; - -/* Event Output Select */ -typedef enum PORTCFG_EVOUTSEL_enum -{ - PORTCFG_EVOUTSEL_0_gc = (0x00<<2), /* Event Channel 0 output to pin */ - PORTCFG_EVOUTSEL_1_gc = (0x01<<2), /* Event Channel 1 output to pin */ - PORTCFG_EVOUTSEL_2_gc = (0x02<<2), /* Event Channel 2 output to pin */ - PORTCFG_EVOUTSEL_3_gc = (0x03<<2), /* Event Channel 3 output to pin */ -} PORTCFG_EVOUTSEL_t; - - -/* --------------------------------------------------------------------------- -AES - AES Module --------------------------------------------------------------------------- -*/ - -/* AES Module */ -typedef struct AES_struct -{ - register8_t CTRL; /* AES Control Register */ - register8_t STATUS; /* AES Status Register */ - register8_t STATE; /* AES State Register */ - register8_t KEY; /* AES Key Register */ - register8_t INTCTRL; /* AES Interrupt Control Register */ -} AES_t; - -/* Interrupt level */ -typedef enum AES_INTLVL_enum -{ - AES_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - AES_INTLVL_LO_gc = (0x01<<0), /* Low Level */ - AES_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ - AES_INTLVL_HI_gc = (0x03<<0), /* High Level */ -} AES_INTLVL_t; - - -/* --------------------------------------------------------------------------- -CRC - Cyclic Redundancy Checker --------------------------------------------------------------------------- -*/ - -/* Cyclic Redundancy Checker */ -typedef struct CRC_struct -{ - register8_t CTRL; /* Control Register */ - register8_t STATUS; /* Status Register */ - register8_t reserved_0x02; - register8_t DATAIN; /* Data Input */ - register8_t CHECKSUM0; /* Checksum byte 0 */ - register8_t CHECKSUM1; /* Checksum byte 1 */ - register8_t CHECKSUM2; /* Checksum byte 2 */ - register8_t CHECKSUM3; /* Checksum byte 3 */ -} CRC_t; - -/* Reset */ -typedef enum CRC_RESET_enum -{ - CRC_RESET_NO_gc = (0x00<<6), /* No Reset */ - CRC_RESET_RESET0_gc = (0x02<<6), /* Reset CRC with CHECKSUM to all zeros */ - CRC_RESET_RESET1_gc = (0x03<<6), /* Reset CRC with CHECKSUM to all ones */ -} CRC_RESET_t; - -/* Input Source */ -typedef enum CRC_SOURCE_enum -{ - CRC_SOURCE_DISABLE_gc = (0x00<<0), /* Disabled */ - CRC_SOURCE_IO_gc = (0x01<<0), /* I/O Interface */ - CRC_SOURCE_FLASH_gc = (0x02<<0), /* Flash */ - CRC_SOURCE_DMAC0_gc = (0x04<<0), /* DMAC Channel 0 */ - CRC_SOURCE_DMAC1_gc = (0x05<<0), /* DMAC Channel 1 */ -} CRC_SOURCE_t; - - -/* --------------------------------------------------------------------------- -DMA - DMA Controller --------------------------------------------------------------------------- -*/ - -/* DMA Channel */ -typedef struct DMA_CH_struct -{ - register8_t CTRLA; /* Channel Control */ - register8_t CTRLB; /* Channel Control */ - register8_t ADDRCTRL; /* Address Control */ - register8_t TRIGSRC; /* Channel Trigger Source */ - _WORDREGISTER(TRFCNT); /* Channel Block Transfer Count */ - register8_t REPCNT; /* Channel Repeat Count */ - register8_t reserved_0x07; - register8_t SRCADDR0; /* Channel Source Address 0 */ - register8_t SRCADDR1; /* Channel Source Address 1 */ - register8_t reserved_0x0A; - register8_t reserved_0x0B; - register8_t DESTADDR0; /* Channel Destination Address 0 */ - register8_t DESTADDR1; /* Channel Destination Address 1 */ - register8_t reserved_0x0E; - register8_t reserved_0x0F; -} DMA_CH_t; - - -/* DMA Controller */ -typedef struct DMA_struct -{ - register8_t CTRL; /* Control */ - register8_t reserved_0x01; - register8_t reserved_0x02; - register8_t INTFLAGS; /* Transfer Interrupt Status */ - register8_t STATUS; /* Status */ - register8_t reserved_0x05; - _WORDREGISTER(TEMP); /* Temporary Register For 16-bit Access */ - register8_t reserved_0x08; - register8_t reserved_0x09; - register8_t reserved_0x0A; - register8_t reserved_0x0B; - register8_t reserved_0x0C; - register8_t reserved_0x0D; - register8_t reserved_0x0E; - register8_t reserved_0x0F; - DMA_CH_t CH0; /* DMA Channel 0 */ - DMA_CH_t CH1; /* DMA Channel 1 */ -} DMA_t; - -/* Burst mode */ -typedef enum DMA_CH_BURSTLEN_enum -{ - DMA_CH_BURSTLEN_1BYTE_gc = (0x00<<0), /* 1-byte burst mode */ - DMA_CH_BURSTLEN_2BYTE_gc = (0x01<<0), /* 2-byte burst mode */ - DMA_CH_BURSTLEN_4BYTE_gc = (0x02<<0), /* 4-byte burst mode */ - DMA_CH_BURSTLEN_8BYTE_gc = (0x03<<0), /* 8-byte burst mode */ -} DMA_CH_BURSTLEN_t; - -/* Source address reload mode */ -typedef enum DMA_CH_SRCRELOAD_enum -{ - DMA_CH_SRCRELOAD_NONE_gc = (0x00<<6), /* No reload */ - DMA_CH_SRCRELOAD_BLOCK_gc = (0x01<<6), /* Reload at end of block */ - DMA_CH_SRCRELOAD_BURST_gc = (0x02<<6), /* Reload at end of burst */ - DMA_CH_SRCRELOAD_TRANSACTION_gc = (0x03<<6), /* Reload at end of transaction */ -} DMA_CH_SRCRELOAD_t; - -/* Source addressing mode */ -typedef enum DMA_CH_SRCDIR_enum -{ - DMA_CH_SRCDIR_FIXED_gc = (0x00<<4), /* Fixed */ - DMA_CH_SRCDIR_INC_gc = (0x01<<4), /* Increment */ - DMA_CH_SRCDIR_DEC_gc = (0x02<<4), /* Decrement */ -} DMA_CH_SRCDIR_t; - -/* Destination adress reload mode */ -typedef enum DMA_CH_DESTRELOAD_enum -{ - DMA_CH_DESTRELOAD_NONE_gc = (0x00<<2), /* No reload */ - DMA_CH_DESTRELOAD_BLOCK_gc = (0x01<<2), /* Reload at end of block */ - DMA_CH_DESTRELOAD_BURST_gc = (0x02<<2), /* Reload at end of burst */ - DMA_CH_DESTRELOAD_TRANSACTION_gc = (0x03<<2), /* Reload at end of transaction */ -} DMA_CH_DESTRELOAD_t; - -/* Destination adressing mode */ -typedef enum DMA_CH_DESTDIR_enum -{ - DMA_CH_DESTDIR_FIXED_gc = (0x00<<0), /* Fixed */ - DMA_CH_DESTDIR_INC_gc = (0x01<<0), /* Increment */ - DMA_CH_DESTDIR_DEC_gc = (0x02<<0), /* Decrement */ -} DMA_CH_DESTDIR_t; - -/* Transfer trigger source */ -typedef enum DMA_CH_TRIGSRC_enum -{ - DMA_CH_TRIGSRC_OFF_gc = (0x00<<0), /* Off software triggers only */ - DMA_CH_TRIGSRC_EVSYS_CH0_gc = (0x01<<0), /* Event System Channel 0 */ - DMA_CH_TRIGSRC_EVSYS_CH1_gc = (0x02<<0), /* Event System Channel 1 */ - DMA_CH_TRIGSRC_EVSYS_CH2_gc = (0x03<<0), /* Event System Channel 2 */ - DMA_CH_TRIGSRC_ADCA_CH0_gc = (0x10<<0), /* ADCA Channel 0 */ - DMA_CH_TRIGSRC_ADCB_CH0_gc = (0x20<<0), /* ADCB Channel 0 */ - DMA_CH_TRIGSRC_TCC0_OVF_gc = (0x40<<0), /* Timer/Counter C0 Overflow */ - DMA_CH_TRIGSRC_TCC0_ERR_gc = (0x41<<0), /* Timer/Counter C0 Error */ - DMA_CH_TRIGSRC_TCC0_CCA_gc = (0x42<<0), /* Timer/Counter C0 Compare or Capture A */ - DMA_CH_TRIGSRC_TCC0_CCB_gc = (0x43<<0), /* Timer/Counter C0 Compare or Capture B */ - DMA_CH_TRIGSRC_TCC0_CCC_gc = (0x44<<0), /* Timer/Counter C0 Compare or Capture C */ - DMA_CH_TRIGSRC_TCC0_CCD_gc = (0x45<<0), /* Timer/Counter C0 Compare or Capture D */ - DMA_CH_TRIGSRC_TCC1_OVF_gc = (0x46<<0), /* Timer/Counter C1 Overflow */ - DMA_CH_TRIGSRC_TCC1_ERR_gc = (0x47<<0), /* Timer/Counter C1 Error */ - DMA_CH_TRIGSRC_TCC1_CCA_gc = (0x48<<0), /* Timer/Counter C1 Compare or Capture A */ - DMA_CH_TRIGSRC_TCC1_CCB_gc = (0x49<<0), /* Timer/Counter C1 Compare or Capture B */ - DMA_CH_TRIGSRC_SPIC_gc = (0x4A<<0), /* SPI C Transfer Complete */ - DMA_CH_TRIGSRC_USARTC0_RXC_gc = (0x4B<<0), /* USART C0 Receive Complete */ - DMA_CH_TRIGSRC_USARTC0_DRE_gc = (0x4C<<0), /* USART C0 Data Register Empty */ - DMA_CH_TRIGSRC_TCE0_OVF_gc = (0x80<<0), /* Timer/Counter E0 Overflow */ - DMA_CH_TRIGSRC_TCE0_ERR_gc = (0x81<<0), /* Timer/Counter E0 Error */ - DMA_CH_TRIGSRC_TCE0_CCA_gc = (0x82<<0), /* Timer/Counter E0 Compare or Capture A */ - DMA_CH_TRIGSRC_TCE0_CCB_gc = (0x83<<0), /* Timer/Counter E0 Compare or Capture B */ - DMA_CH_TRIGSRC_TCE0_CCC_gc = (0x84<<0), /* Timer/Counter E0 Compare or Capture C */ - DMA_CH_TRIGSRC_TCE0_CCD_gc = (0x85<<0), /* Timer/Counter E0 Compare or Capture D */ - DMA_CH_TRIGSRC_USARTE0_RXC_gc = (0x8B<<0), /* USART E0 Receive Complete */ - DMA_CH_TRIGSRC_USARTE0_DRE_gc = (0x8C<<0), /* USART E0 Data Register Empty */ -} DMA_CH_TRIGSRC_t; - -/* Double buffering mode */ -typedef enum DMA_DBUFMODE_enum -{ - DMA_DBUFMODE_DISABLED_gc = (0x00<<2), /* Double buffering disabled */ - DMA_DBUFMODE_CH01_gc = (0x01<<2), /* Double buffering enabled on channel 0/1 */ -} DMA_DBUFMODE_t; - -/* Priority mode */ -typedef enum DMA_PRIMODE_enum -{ - DMA_PRIMODE_RR01_gc = (0x00<<0), /* Round Robin */ - DMA_PRIMODE_CH0RR1_gc = (0x01<<0), /* Channel 0 > channel 1 */ -} DMA_PRIMODE_t; - -/* Interrupt level */ -typedef enum DMA_CH_ERRINTLVL_enum -{ - DMA_CH_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ - DMA_CH_ERRINTLVL_LO_gc = (0x01<<2), /* Low level */ - DMA_CH_ERRINTLVL_MED_gc = (0x02<<2), /* Medium level */ - DMA_CH_ERRINTLVL_HI_gc = (0x03<<2), /* High level */ -} DMA_CH_ERRINTLVL_t; - -/* Interrupt level */ -typedef enum DMA_CH_TRNINTLVL_enum -{ - DMA_CH_TRNINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ - DMA_CH_TRNINTLVL_LO_gc = (0x01<<0), /* Low level */ - DMA_CH_TRNINTLVL_MED_gc = (0x02<<0), /* Medium level */ - DMA_CH_TRNINTLVL_HI_gc = (0x03<<0), /* High level */ -} DMA_CH_TRNINTLVL_t; - - -/* --------------------------------------------------------------------------- -EVSYS - Event System --------------------------------------------------------------------------- -*/ - -/* Event System */ -typedef struct EVSYS_struct -{ - register8_t CH0MUX; /* Event Channel 0 Multiplexer */ - register8_t CH1MUX; /* Event Channel 1 Multiplexer */ - register8_t CH2MUX; /* Event Channel 2 Multiplexer */ - register8_t CH3MUX; /* Event Channel 3 Multiplexer */ - register8_t reserved_0x04; - register8_t reserved_0x05; - register8_t reserved_0x06; - register8_t reserved_0x07; - register8_t CH0CTRL; /* Channel 0 Control Register */ - register8_t CH1CTRL; /* Channel 1 Control Register */ - register8_t CH2CTRL; /* Channel 2 Control Register */ - register8_t CH3CTRL; /* Channel 3 Control Register */ - register8_t reserved_0x0C; - register8_t reserved_0x0D; - register8_t reserved_0x0E; - register8_t reserved_0x0F; - register8_t STROBE; /* Event Strobe */ - register8_t DATA; /* Event Data */ -} EVSYS_t; - -/* Quadrature Decoder Index Recognition Mode */ -typedef enum EVSYS_QDIRM_enum -{ - EVSYS_QDIRM_00_gc = (0x00<<5), /* QDPH0 = 0, QDPH90 = 0 */ - EVSYS_QDIRM_01_gc = (0x01<<5), /* QDPH0 = 0, QDPH90 = 1 */ - EVSYS_QDIRM_10_gc = (0x02<<5), /* QDPH0 = 1, QDPH90 = 0 */ - EVSYS_QDIRM_11_gc = (0x03<<5), /* QDPH0 = 1, QDPH90 = 1 */ -} EVSYS_QDIRM_t; - -/* Digital filter coefficient */ -typedef enum EVSYS_DIGFILT_enum -{ - EVSYS_DIGFILT_1SAMPLE_gc = (0x00<<0), /* 1 SAMPLE */ - EVSYS_DIGFILT_2SAMPLES_gc = (0x01<<0), /* 2 SAMPLES */ - EVSYS_DIGFILT_3SAMPLES_gc = (0x02<<0), /* 3 SAMPLES */ - EVSYS_DIGFILT_4SAMPLES_gc = (0x03<<0), /* 4 SAMPLES */ - EVSYS_DIGFILT_5SAMPLES_gc = (0x04<<0), /* 5 SAMPLES */ - EVSYS_DIGFILT_6SAMPLES_gc = (0x05<<0), /* 6 SAMPLES */ - EVSYS_DIGFILT_7SAMPLES_gc = (0x06<<0), /* 7 SAMPLES */ - EVSYS_DIGFILT_8SAMPLES_gc = (0x07<<0), /* 8 SAMPLES */ -} EVSYS_DIGFILT_t; - -/* Event Channel multiplexer input selection */ -typedef enum EVSYS_CHMUX_enum -{ - EVSYS_CHMUX_OFF_gc = (0x00<<0), /* Off */ - EVSYS_CHMUX_RTC_OVF_gc = (0x08<<0), /* RTC Overflow */ - EVSYS_CHMUX_RTC_CMP_gc = (0x09<<0), /* RTC Compare Match */ - EVSYS_CHMUX_USB_gc = (0x0A<<0), /* USB Setup, SOF, CRC error and UNF/OVF */ - EVSYS_CHMUX_ACA_CH0_gc = (0x10<<0), /* Analog Comparator A Channel 0 */ - EVSYS_CHMUX_ACA_CH1_gc = (0x11<<0), /* Analog Comparator A Channel 1 */ - EVSYS_CHMUX_ACA_WIN_gc = (0x12<<0), /* Analog Comparator A Window */ - EVSYS_CHMUX_ACB_CH0_gc = (0x13<<0), /* Analog Comparator B Channel 0 */ - EVSYS_CHMUX_ACB_CH1_gc = (0x14<<0), /* Analog Comparator B Channel 1 */ - EVSYS_CHMUX_ACB_WIN_gc = (0x15<<0), /* Analog Comparator B Window */ - EVSYS_CHMUX_ADCA_CH0_gc = (0x20<<0), /* ADC A Channel */ - EVSYS_CHMUX_ADCB_CH0_gc = (0x24<<0), /* ADC B Channel */ - EVSYS_CHMUX_PORTA_PIN0_gc = (0x50<<0), /* Port A, Pin0 */ - EVSYS_CHMUX_PORTA_PIN1_gc = (0x51<<0), /* Port A, Pin1 */ - EVSYS_CHMUX_PORTA_PIN2_gc = (0x52<<0), /* Port A, Pin2 */ - EVSYS_CHMUX_PORTA_PIN3_gc = (0x53<<0), /* Port A, Pin3 */ - EVSYS_CHMUX_PORTA_PIN4_gc = (0x54<<0), /* Port A, Pin4 */ - EVSYS_CHMUX_PORTA_PIN5_gc = (0x55<<0), /* Port A, Pin5 */ - EVSYS_CHMUX_PORTA_PIN6_gc = (0x56<<0), /* Port A, Pin6 */ - EVSYS_CHMUX_PORTA_PIN7_gc = (0x57<<0), /* Port A, Pin7 */ - EVSYS_CHMUX_PORTB_PIN0_gc = (0x58<<0), /* Port B, Pin0 */ - EVSYS_CHMUX_PORTB_PIN1_gc = (0x59<<0), /* Port B, Pin1 */ - EVSYS_CHMUX_PORTB_PIN2_gc = (0x5A<<0), /* Port B, Pin2 */ - EVSYS_CHMUX_PORTB_PIN3_gc = (0x5B<<0), /* Port B, Pin3 */ - EVSYS_CHMUX_PORTB_PIN4_gc = (0x5C<<0), /* Port B, Pin4 */ - EVSYS_CHMUX_PORTB_PIN5_gc = (0x5D<<0), /* Port B, Pin5 */ - EVSYS_CHMUX_PORTB_PIN6_gc = (0x5E<<0), /* Port B, Pin6 */ - EVSYS_CHMUX_PORTB_PIN7_gc = (0x5F<<0), /* Port B, Pin7 */ - EVSYS_CHMUX_PORTC_PIN0_gc = (0x60<<0), /* Port C, Pin0 */ - EVSYS_CHMUX_PORTC_PIN1_gc = (0x61<<0), /* Port C, Pin1 */ - EVSYS_CHMUX_PORTC_PIN2_gc = (0x62<<0), /* Port C, Pin2 */ - EVSYS_CHMUX_PORTC_PIN3_gc = (0x63<<0), /* Port C, Pin3 */ - EVSYS_CHMUX_PORTC_PIN4_gc = (0x64<<0), /* Port C, Pin4 */ - EVSYS_CHMUX_PORTC_PIN5_gc = (0x65<<0), /* Port C, Pin5 */ - EVSYS_CHMUX_PORTC_PIN6_gc = (0x66<<0), /* Port C, Pin6 */ - EVSYS_CHMUX_PORTC_PIN7_gc = (0x67<<0), /* Port C, Pin7 */ - EVSYS_CHMUX_PORTD_PIN0_gc = (0x68<<0), /* Port D, Pin0 */ - EVSYS_CHMUX_PORTD_PIN1_gc = (0x69<<0), /* Port D, Pin1 */ - EVSYS_CHMUX_PORTD_PIN2_gc = (0x6A<<0), /* Port D, Pin2 */ - EVSYS_CHMUX_PORTE_PIN0_gc = (0x70<<0), /* Port E, Pin0 */ - EVSYS_CHMUX_PORTE_PIN1_gc = (0x71<<0), /* Port E, Pin1 */ - EVSYS_CHMUX_PORTE_PIN2_gc = (0x72<<0), /* Port E, Pin2 */ - EVSYS_CHMUX_PORTE_PIN3_gc = (0x73<<0), /* Port E, Pin3 */ - EVSYS_CHMUX_PORTE_PIN4_gc = (0x74<<0), /* Port E, Pin4 */ - EVSYS_CHMUX_PORTE_PIN5_gc = (0x75<<0), /* Port E, Pin5 */ - EVSYS_CHMUX_PORTE_PIN6_gc = (0x76<<0), /* Port E, Pin6 */ - EVSYS_CHMUX_PORTE_PIN7_gc = (0x77<<0), /* Port E, Pin7 */ - EVSYS_CHMUX_PRESCALER_1_gc = (0x80<<0), /* Prescaler, divide by 1 */ - EVSYS_CHMUX_PRESCALER_2_gc = (0x81<<0), /* Prescaler, divide by 2 */ - EVSYS_CHMUX_PRESCALER_4_gc = (0x82<<0), /* Prescaler, divide by 4 */ - EVSYS_CHMUX_PRESCALER_8_gc = (0x83<<0), /* Prescaler, divide by 8 */ - EVSYS_CHMUX_PRESCALER_16_gc = (0x84<<0), /* Prescaler, divide by 16 */ - EVSYS_CHMUX_PRESCALER_32_gc = (0x85<<0), /* Prescaler, divide by 32 */ - EVSYS_CHMUX_PRESCALER_64_gc = (0x86<<0), /* Prescaler, divide by 64 */ - EVSYS_CHMUX_PRESCALER_128_gc = (0x87<<0), /* Prescaler, divide by 128 */ - EVSYS_CHMUX_PRESCALER_256_gc = (0x88<<0), /* Prescaler, divide by 256 */ - EVSYS_CHMUX_PRESCALER_512_gc = (0x89<<0), /* Prescaler, divide by 512 */ - EVSYS_CHMUX_PRESCALER_1024_gc = (0x8A<<0), /* Prescaler, divide by 1024 */ - EVSYS_CHMUX_PRESCALER_2048_gc = (0x8B<<0), /* Prescaler, divide by 2048 */ - EVSYS_CHMUX_PRESCALER_4096_gc = (0x8C<<0), /* Prescaler, divide by 4096 */ - EVSYS_CHMUX_PRESCALER_8192_gc = (0x8D<<0), /* Prescaler, divide by 8192 */ - EVSYS_CHMUX_PRESCALER_16384_gc = (0x8E<<0), /* Prescaler, divide by 16384 */ - EVSYS_CHMUX_PRESCALER_32768_gc = (0x8F<<0), /* Prescaler, divide by 32768 */ - EVSYS_CHMUX_TCC0_OVF_gc = (0xC0<<0), /* Timer/Counter C0 Overflow */ - EVSYS_CHMUX_TCC0_ERR_gc = (0xC1<<0), /* Timer/Counter C0 Error */ - EVSYS_CHMUX_TCC0_CCA_gc = (0xC4<<0), /* Timer/Counter C0 Compare or Capture A */ - EVSYS_CHMUX_TCC0_CCB_gc = (0xC5<<0), /* Timer/Counter C0 Compare or Capture B */ - EVSYS_CHMUX_TCC0_CCC_gc = (0xC6<<0), /* Timer/Counter C0 Compare or Capture C */ - EVSYS_CHMUX_TCC0_CCD_gc = (0xC7<<0), /* Timer/Counter C0 Compare or Capture D */ - EVSYS_CHMUX_TCC1_OVF_gc = (0xC8<<0), /* Timer/Counter C1 Overflow */ - EVSYS_CHMUX_TCC1_ERR_gc = (0xC9<<0), /* Timer/Counter C1 Error */ - EVSYS_CHMUX_TCC1_CCA_gc = (0xCC<<0), /* Timer/Counter C1 Compare or Capture A */ - EVSYS_CHMUX_TCC1_CCB_gc = (0xCD<<0), /* Timer/Counter C1 Compare or Capture B */ - EVSYS_CHMUX_TCE0_OVF_gc = (0xE0<<0), /* Timer/Counter E0 Overflow */ - EVSYS_CHMUX_TCE0_ERR_gc = (0xE1<<0), /* Timer/Counter E0 Error */ - EVSYS_CHMUX_TCE0_CCA_gc = (0xE4<<0), /* Timer/Counter E0 Compare or Capture A */ - EVSYS_CHMUX_TCE0_CCB_gc = (0xE5<<0), /* Timer/Counter E0 Compare or Capture B */ - EVSYS_CHMUX_TCE0_CCC_gc = (0xE6<<0), /* Timer/Counter E0 Compare or Capture C */ - EVSYS_CHMUX_TCE0_CCD_gc = (0xE7<<0), /* Timer/Counter E0 Compare or Capture D */ -} EVSYS_CHMUX_t; - - -/* --------------------------------------------------------------------------- -NVM - Non Volatile Memory Controller --------------------------------------------------------------------------- -*/ - -/* Non-volatile Memory Controller */ -typedef struct NVM_struct -{ - register8_t ADDR0; /* Address Register 0 */ - register8_t ADDR1; /* Address Register 1 */ - register8_t ADDR2; /* Address Register 2 */ - register8_t reserved_0x03; - register8_t DATA0; /* Data Register 0 */ - register8_t DATA1; /* Data Register 1 */ - register8_t DATA2; /* Data Register 2 */ - register8_t reserved_0x07; - register8_t reserved_0x08; - register8_t reserved_0x09; - register8_t CMD; /* Command */ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t INTCTRL; /* Interrupt Control */ - register8_t reserved_0x0E; - register8_t STATUS; /* Status */ - register8_t LOCK_BITS; /* Lock Bits (Changed from LOCKBITS to avoid avr-libc collision) */ -} NVM_t; - -/* NVM Command */ -typedef enum NVM_CMD_enum -{ - NVM_CMD_NO_OPERATION_gc = (0x00<<0), /* Noop/Ordinary LPM */ - NVM_CMD_READ_USER_SIG_ROW_gc = (0x01<<0), /* Read user signature row */ - NVM_CMD_READ_CALIB_ROW_gc = (0x02<<0), /* Read calibration row */ - NVM_CMD_READ_EEPROM_gc = (0x06<<0), /* Read EEPROM */ - NVM_CMD_READ_FUSES_gc = (0x07<<0), /* Read fuse byte */ - NVM_CMD_WRITE_LOCK_BITS_gc = (0x08<<0), /* Write lock bits */ - NVM_CMD_ERASE_USER_SIG_ROW_gc = (0x18<<0), /* Erase user signature row */ - NVM_CMD_WRITE_USER_SIG_ROW_gc = (0x1A<<0), /* Write user signature row */ - NVM_CMD_ERASE_APP_gc = (0x20<<0), /* Erase Application Section */ - NVM_CMD_ERASE_APP_PAGE_gc = (0x22<<0), /* Erase Application Section page */ - NVM_CMD_LOAD_FLASH_BUFFER_gc = (0x23<<0), /* Load Flash page buffer */ - NVM_CMD_WRITE_APP_PAGE_gc = (0x24<<0), /* Write Application Section page */ - NVM_CMD_ERASE_WRITE_APP_PAGE_gc = (0x25<<0), /* Erase-and-write Application Section page */ - NVM_CMD_ERASE_FLASH_BUFFER_gc = (0x26<<0), /* Erase/flush Flash page buffer */ - NVM_CMD_ERASE_BOOT_PAGE_gc = (0x2A<<0), /* Erase Boot Section page */ - NVM_CMD_ERASE_FLASH_PAGE_gc = (0x2B<<0), /* Erase Flash Page */ - NVM_CMD_WRITE_BOOT_PAGE_gc = (0x2C<<0), /* Write Boot Section page */ - NVM_CMD_ERASE_WRITE_BOOT_PAGE_gc = (0x2D<<0), /* Erase-and-write Boot Section page */ - NVM_CMD_WRITE_FLASH_PAGE_gc = (0x2E<<0), /* Write Flash Page */ - NVM_CMD_ERASE_WRITE_FLASH_PAGE_gc = (0x2F<<0), /* Erase-and-write Flash Page */ - NVM_CMD_ERASE_EEPROM_gc = (0x30<<0), /* Erase EEPROM */ - NVM_CMD_ERASE_EEPROM_PAGE_gc = (0x32<<0), /* Erase EEPROM page */ - NVM_CMD_LOAD_EEPROM_BUFFER_gc = (0x33<<0), /* Load EEPROM page buffer */ - NVM_CMD_WRITE_EEPROM_PAGE_gc = (0x34<<0), /* Write EEPROM page */ - NVM_CMD_ERASE_WRITE_EEPROM_PAGE_gc = (0x35<<0), /* Erase-and-write EEPROM page */ - NVM_CMD_ERASE_EEPROM_BUFFER_gc = (0x36<<0), /* Erase/flush EEPROM page buffer */ - NVM_CMD_APP_CRC_gc = (0x38<<0), /* Application section CRC */ - NVM_CMD_BOOT_CRC_gc = (0x39<<0), /* Boot Section CRC */ - NVM_CMD_FLASH_RANGE_CRC_gc = (0x3A<<0), /* Flash Range CRC */ - NVM_CMD_CHIP_ERASE_gc = (0x40<<0), /* Erase Chip */ - NVM_CMD_READ_NVM_gc = (0x43<<0), /* Read NVM */ - NVM_CMD_WRITE_FUSE_gc = (0x4C<<0), /* Write Fuse byte */ - NVM_CMD_ERASE_BOOT_gc = (0x68<<0), /* Erase Boot Section */ - NVM_CMD_FLASH_CRC_gc = (0x78<<0), /* Flash CRC */ -} NVM_CMD_t; - -/* SPM ready interrupt level */ -typedef enum NVM_SPMLVL_enum -{ - NVM_SPMLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ - NVM_SPMLVL_LO_gc = (0x01<<2), /* Low level */ - NVM_SPMLVL_MED_gc = (0x02<<2), /* Medium level */ - NVM_SPMLVL_HI_gc = (0x03<<2), /* High level */ -} NVM_SPMLVL_t; - -/* EEPROM ready interrupt level */ -typedef enum NVM_EELVL_enum -{ - NVM_EELVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ - NVM_EELVL_LO_gc = (0x01<<0), /* Low level */ - NVM_EELVL_MED_gc = (0x02<<0), /* Medium level */ - NVM_EELVL_HI_gc = (0x03<<0), /* High level */ -} NVM_EELVL_t; - -/* Boot lock bits - boot setcion */ -typedef enum NVM_BLBB_enum -{ - NVM_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ - NVM_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ - NVM_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ - NVM_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ -} NVM_BLBB_t; - -/* Boot lock bits - application section */ -typedef enum NVM_BLBA_enum -{ - NVM_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ - NVM_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ - NVM_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ - NVM_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ -} NVM_BLBA_t; - -/* Boot lock bits - application table section */ -typedef enum NVM_BLBAT_enum -{ - NVM_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ - NVM_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ - NVM_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ - NVM_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ -} NVM_BLBAT_t; - -/* Lock bits */ -typedef enum NVM_LB_enum -{ - NVM_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ - NVM_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ - NVM_LB_NOLOCK_gc = (0x03<<0), /* No locks */ -} NVM_LB_t; - - -/* --------------------------------------------------------------------------- -ADC - Analog/Digital Converter --------------------------------------------------------------------------- -*/ - -/* ADC Channel */ -typedef struct ADC_CH_struct -{ - register8_t CTRL; /* Control Register */ - register8_t MUXCTRL; /* MUX Control */ - register8_t INTCTRL; /* Channel Interrupt Control Register */ - register8_t INTFLAGS; /* Interrupt Flags */ - _WORDREGISTER(RES); /* Channel Result */ - register8_t SCAN; /* Input Channel Scan */ - register8_t reserved_0x07; -} ADC_CH_t; - - -/* Analog-to-Digital Converter */ -typedef struct ADC_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t REFCTRL; /* Reference Control */ - register8_t EVCTRL; /* Event Control */ - register8_t PRESCALER; /* Clock Prescaler */ - register8_t reserved_0x05; - register8_t INTFLAGS; /* Interrupt Flags */ - register8_t TEMP; /* Temporary Register */ - register8_t SAMPCTRL; /* ADC Sampling Time Control Register */ - register8_t reserved_0x09; - register8_t reserved_0x0A; - register8_t reserved_0x0B; - _WORDREGISTER(CAL); /* Calibration Value */ - register8_t reserved_0x0E; - register8_t reserved_0x0F; - _WORDREGISTER(CH0RES); /* Channel 0 Result */ - register8_t reserved_0x12; - register8_t reserved_0x13; - register8_t reserved_0x14; - register8_t reserved_0x15; - register8_t reserved_0x16; - register8_t reserved_0x17; - _WORDREGISTER(CMP); /* Compare Value */ - register8_t reserved_0x1A; - register8_t reserved_0x1B; - register8_t reserved_0x1C; - register8_t reserved_0x1D; - register8_t reserved_0x1E; - register8_t reserved_0x1F; - ADC_CH_t CH0; /* ADC Channel 0 */ -} ADC_t; - -/* Current Limitation */ -typedef enum ADC_CURRLIMIT_enum -{ - ADC_CURRLIMIT_NO_gc = (0x00<<5), /* No current limit, 300ksps max sampling rate */ - ADC_CURRLIMIT_LOW_gc = (0x01<<5), /* Low current limit, 250ksps max sampling rate */ - ADC_CURRLIMIT_MED_gc = (0x02<<5), /* Medium current limit, 150ksps max sampling rate */ - ADC_CURRLIMIT_HIGH_gc = (0x03<<5), /* High current limit, 50ksps max sampling rate */ -} ADC_CURRLIMIT_t; - -/* Positive input multiplexer selection */ -typedef enum ADC_CH_MUXPOS_enum -{ - ADC_CH_MUXPOS_PIN0_gc = (0x00<<3), /* Input pin 0 */ - ADC_CH_MUXPOS_PIN1_gc = (0x01<<3), /* Input pin 1 */ - ADC_CH_MUXPOS_PIN2_gc = (0x02<<3), /* Input pin 2 */ - ADC_CH_MUXPOS_PIN3_gc = (0x03<<3), /* Input pin 3 */ - ADC_CH_MUXPOS_PIN4_gc = (0x04<<3), /* Input pin 4 */ - ADC_CH_MUXPOS_PIN5_gc = (0x05<<3), /* Input pin 5 */ - ADC_CH_MUXPOS_PIN6_gc = (0x06<<3), /* Input pin 6 */ - ADC_CH_MUXPOS_PIN7_gc = (0x07<<3), /* Input pin 7 */ - ADC_CH_MUXPOS_PIN8_gc = (0x08<<3), /* Input pin 8 */ - ADC_CH_MUXPOS_PIN9_gc = (0x09<<3), /* Input pin 9 */ - ADC_CH_MUXPOS_PIN10_gc = (0x0A<<3), /* Input pin 10 */ - ADC_CH_MUXPOS_PIN11_gc = (0x0B<<3), /* Input pin 11 */ - ADC_CH_MUXPOS_PIN12_gc = (0x0C<<3), /* Input pin 12 */ - ADC_CH_MUXPOS_PIN13_gc = (0x0D<<3), /* Input pin 13 */ - ADC_CH_MUXPOS_PIN14_gc = (0x0E<<3), /* Input pin 14 */ - ADC_CH_MUXPOS_PIN15_gc = (0x0F<<3), /* Input pin 15 */ -} ADC_CH_MUXPOS_t; - -/* Internal input multiplexer selections */ -typedef enum ADC_CH_MUXINT_enum -{ - ADC_CH_MUXINT_TEMP_gc = (0x00<<3), /* Temperature Reference */ - ADC_CH_MUXINT_BANDGAP_gc = (0x01<<3), /* Bandgap Reference */ - ADC_CH_MUXINT_SCALEDVCC_gc = (0x02<<3), /* 1/10 scaled VCC */ -} ADC_CH_MUXINT_t; - -/* Negative input multiplexer selection */ -typedef enum ADC_CH_MUXNEG_enum -{ - ADC_CH_MUXNEG_PIN0_gc = (0x00<<0), /* Input pin 0 */ - ADC_CH_MUXNEG_PIN1_gc = (0x01<<0), /* Input pin 1 */ - ADC_CH_MUXNEG_PIN2_gc = (0x02<<0), /* Input pin 2 */ - ADC_CH_MUXNEG_PIN3_gc = (0x03<<0), /* Input pin 3 */ - ADC_CH_MUXNEG_PIN4_gc = (0x00<<0), /* Input pin 4 */ - ADC_CH_MUXNEG_PIN5_gc = (0x01<<0), /* Input pin 5 */ - ADC_CH_MUXNEG_PIN6_gc = (0x02<<0), /* Input pin 6 */ - ADC_CH_MUXNEG_PIN7_gc = (0x03<<0), /* Input pin 7 */ -} ADC_CH_MUXNEG_t; - -/* Input mode */ -typedef enum ADC_CH_INPUTMODE_enum -{ - ADC_CH_INPUTMODE_INTERNAL_gc = (0x00<<0), /* Internal inputs, no gain */ - ADC_CH_INPUTMODE_SINGLEENDED_gc = (0x01<<0), /* Single-ended input, no gain */ - ADC_CH_INPUTMODE_DIFF_gc = (0x02<<0), /* Differential input, no gain */ - ADC_CH_INPUTMODE_DIFFWGAIN_gc = (0x03<<0), /* Differential input, with gain */ -} ADC_CH_INPUTMODE_t; - -/* Gain factor */ -typedef enum ADC_CH_GAIN_enum -{ - ADC_CH_GAIN_1X_gc = (0x00<<2), /* 1x gain */ - ADC_CH_GAIN_2X_gc = (0x01<<2), /* 2x gain */ - ADC_CH_GAIN_4X_gc = (0x02<<2), /* 4x gain */ - ADC_CH_GAIN_8X_gc = (0x03<<2), /* 8x gain */ - ADC_CH_GAIN_16X_gc = (0x04<<2), /* 16x gain */ - ADC_CH_GAIN_32X_gc = (0x05<<2), /* 32x gain */ - ADC_CH_GAIN_64X_gc = (0x06<<2), /* 64x gain */ - ADC_CH_GAIN_DIV2_gc = (0x07<<2), /* x/2 gain */ -} ADC_CH_GAIN_t; - -/* Conversion result resolution */ -typedef enum ADC_RESOLUTION_enum -{ - ADC_RESOLUTION_12BIT_gc = (0x00<<1), /* 12-bit right-adjusted result */ - ADC_RESOLUTION_8BIT_gc = (0x02<<1), /* 8-bit right-adjusted result */ - ADC_RESOLUTION_LEFT12BIT_gc = (0x03<<1), /* 12-bit left-adjusted result */ -} ADC_RESOLUTION_t; - -/* Voltage reference selection */ -typedef enum ADC_REFSEL_enum -{ - ADC_REFSEL_INT1V_gc = (0x00<<4), /* Internal 1V */ - ADC_REFSEL_INTVCC_gc = (0x01<<4), /* Internal VCC / 1.6 */ - ADC_REFSEL_AREFA_gc = (0x02<<4), /* External reference on PORT A */ - ADC_REFSEL_AREFB_gc = (0x03<<4), /* External reference on PORT B */ - ADC_REFSEL_INTVCC2_gc = (0x04<<4), /* Internal VCC / 2 */ -} ADC_REFSEL_t; - -/* Event channel input selection */ -typedef enum ADC_EVSEL_enum -{ - ADC_EVSEL_0_gc = (0x00<<3), /* Event Channel 0 */ - ADC_EVSEL_1_gc = (0x01<<3), /* Event Channel 1 */ - ADC_EVSEL_2_gc = (0x02<<3), /* Event Channel 2 */ - ADC_EVSEL_3_gc = (0x03<<3), /* Event Channel 3 */ -} ADC_EVSEL_t; - -/* Event action selection */ -typedef enum ADC_EVACT_enum -{ - ADC_EVACT_NONE_gc = (0x00<<0), /* No event action */ - ADC_EVACT_CH0_gc = (0x01<<0), /* First event triggers channel 0 */ - ADC_EVACT_SYNCSWEEP_gc = (0x06<<0), /* The ADC is flushed and restarted for accurate timing */ -} ADC_EVACT_t; - -/* Interupt mode */ -typedef enum ADC_CH_INTMODE_enum -{ - ADC_CH_INTMODE_COMPLETE_gc = (0x00<<2), /* Interrupt on conversion complete */ - ADC_CH_INTMODE_BELOW_gc = (0x01<<2), /* Interrupt on result below compare value */ - ADC_CH_INTMODE_ABOVE_gc = (0x03<<2), /* Interrupt on result above compare value */ -} ADC_CH_INTMODE_t; - -/* Interrupt level */ -typedef enum ADC_CH_INTLVL_enum -{ - ADC_CH_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ - ADC_CH_INTLVL_LO_gc = (0x01<<0), /* Low level */ - ADC_CH_INTLVL_MED_gc = (0x02<<0), /* Medium level */ - ADC_CH_INTLVL_HI_gc = (0x03<<0), /* High level */ -} ADC_CH_INTLVL_t; - -/* Clock prescaler */ -typedef enum ADC_PRESCALER_enum -{ - ADC_PRESCALER_DIV4_gc = (0x00<<0), /* Divide clock by 4 */ - ADC_PRESCALER_DIV8_gc = (0x01<<0), /* Divide clock by 8 */ - ADC_PRESCALER_DIV16_gc = (0x02<<0), /* Divide clock by 16 */ - ADC_PRESCALER_DIV32_gc = (0x03<<0), /* Divide clock by 32 */ - ADC_PRESCALER_DIV64_gc = (0x04<<0), /* Divide clock by 64 */ - ADC_PRESCALER_DIV128_gc = (0x05<<0), /* Divide clock by 128 */ - ADC_PRESCALER_DIV256_gc = (0x06<<0), /* Divide clock by 256 */ - ADC_PRESCALER_DIV512_gc = (0x07<<0), /* Divide clock by 512 */ -} ADC_PRESCALER_t; - - -/* --------------------------------------------------------------------------- -AC - Analog Comparator --------------------------------------------------------------------------- -*/ - -/* Analog Comparator */ -typedef struct AC_struct -{ - register8_t AC0CTRL; /* Analog Comparator 0 Control */ - register8_t AC1CTRL; /* Analog Comparator 1 Control */ - register8_t AC0MUXCTRL; /* Analog Comparator 0 MUX Control */ - register8_t AC1MUXCTRL; /* Analog Comparator 1 MUX Control */ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t WINCTRL; /* Window Mode Control */ - register8_t STATUS; /* Status */ - register8_t CURRCTRL; /* Current Source Control Register */ - register8_t CURRCALIB; /* Current Source Calibration Register */ -} AC_t; - -/* Interrupt mode */ -typedef enum AC_INTMODE_enum -{ - AC_INTMODE_BOTHEDGES_gc = (0x00<<6), /* Interrupt on both edges */ - AC_INTMODE_FALLING_gc = (0x02<<6), /* Interrupt on falling edge */ - AC_INTMODE_RISING_gc = (0x03<<6), /* Interrupt on rising edge */ -} AC_INTMODE_t; - -/* Interrupt level */ -typedef enum AC_INTLVL_enum -{ - AC_INTLVL_OFF_gc = (0x00<<4), /* Interrupt disabled */ - AC_INTLVL_LO_gc = (0x01<<4), /* Low level */ - AC_INTLVL_MED_gc = (0x02<<4), /* Medium level */ - AC_INTLVL_HI_gc = (0x03<<4), /* High level */ -} AC_INTLVL_t; - -/* Hysteresis mode selection */ -typedef enum AC_HYSMODE_enum -{ - AC_HYSMODE_NO_gc = (0x00<<1), /* No hysteresis */ - AC_HYSMODE_SMALL_gc = (0x01<<1), /* Small hysteresis */ - AC_HYSMODE_LARGE_gc = (0x02<<1), /* Large hysteresis */ -} AC_HYSMODE_t; - -/* Positive input multiplexer selection */ -typedef enum AC_MUXPOS_enum -{ - AC_MUXPOS_PIN0_gc = (0x00<<3), /* Pin 0 */ - AC_MUXPOS_PIN1_gc = (0x01<<3), /* Pin 1 */ - AC_MUXPOS_PIN2_gc = (0x02<<3), /* Pin 2 */ - AC_MUXPOS_PIN3_gc = (0x03<<3), /* Pin 3 */ - AC_MUXPOS_PIN4_gc = (0x04<<3), /* Pin 4 */ - AC_MUXPOS_PIN5_gc = (0x05<<3), /* Pin 5 */ - AC_MUXPOS_PIN6_gc = (0x06<<3), /* Pin 6 */ -} AC_MUXPOS_t; - -/* Negative input multiplexer selection */ -typedef enum AC_MUXNEG_enum -{ - AC_MUXNEG_PIN0_gc = (0x00<<0), /* Pin 0 */ - AC_MUXNEG_PIN1_gc = (0x01<<0), /* Pin 1 */ - AC_MUXNEG_PIN3_gc = (0x02<<0), /* Pin 3 */ - AC_MUXNEG_PIN5_gc = (0x03<<0), /* Pin 5 */ - AC_MUXNEG_PIN7_gc = (0x04<<0), /* Pin 7 */ - AC_MUXNEG_BANDGAP_gc = (0x06<<0), /* Bandgap Reference */ - AC_MUXNEG_SCALER_gc = (0x07<<0), /* Internal voltage scaler */ -} AC_MUXNEG_t; - -/* Windows interrupt mode */ -typedef enum AC_WINTMODE_enum -{ - AC_WINTMODE_ABOVE_gc = (0x00<<2), /* Interrupt on above window */ - AC_WINTMODE_INSIDE_gc = (0x01<<2), /* Interrupt on inside window */ - AC_WINTMODE_BELOW_gc = (0x02<<2), /* Interrupt on below window */ - AC_WINTMODE_OUTSIDE_gc = (0x03<<2), /* Interrupt on outside window */ -} AC_WINTMODE_t; - -/* Window interrupt level */ -typedef enum AC_WINTLVL_enum -{ - AC_WINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ - AC_WINTLVL_LO_gc = (0x01<<0), /* Low priority */ - AC_WINTLVL_MED_gc = (0x02<<0), /* Medium priority */ - AC_WINTLVL_HI_gc = (0x03<<0), /* High priority */ -} AC_WINTLVL_t; - -/* Window mode state */ -typedef enum AC_WSTATE_enum -{ - AC_WSTATE_ABOVE_gc = (0x00<<6), /* Signal above window */ - AC_WSTATE_INSIDE_gc = (0x01<<6), /* Signal inside window */ - AC_WSTATE_BELOW_gc = (0x02<<6), /* Signal below window */ -} AC_WSTATE_t; - - -/* --------------------------------------------------------------------------- -RTC - Real-Time Counter --------------------------------------------------------------------------- -*/ - -/* Real-Time Counter */ -typedef struct RTC_struct -{ - register8_t CTRL; /* Control Register */ - register8_t STATUS; /* Status Register */ - register8_t INTCTRL; /* Interrupt Control Register */ - register8_t INTFLAGS; /* Interrupt Flags */ - register8_t TEMP; /* Temporary register */ - register8_t reserved_0x05; - register8_t reserved_0x06; - register8_t reserved_0x07; - _WORDREGISTER(CNT); /* Count Register */ - _WORDREGISTER(PER); /* Period Register */ - _WORDREGISTER(COMP); /* Compare Register */ -} RTC_t; - -/* Prescaler Factor */ -typedef enum RTC_PRESCALER_enum -{ - RTC_PRESCALER_OFF_gc = (0x00<<0), /* RTC Off */ - RTC_PRESCALER_DIV1_gc = (0x01<<0), /* RTC Clock */ - RTC_PRESCALER_DIV2_gc = (0x02<<0), /* RTC Clock / 2 */ - RTC_PRESCALER_DIV8_gc = (0x03<<0), /* RTC Clock / 8 */ - RTC_PRESCALER_DIV16_gc = (0x04<<0), /* RTC Clock / 16 */ - RTC_PRESCALER_DIV64_gc = (0x05<<0), /* RTC Clock / 64 */ - RTC_PRESCALER_DIV256_gc = (0x06<<0), /* RTC Clock / 256 */ - RTC_PRESCALER_DIV1024_gc = (0x07<<0), /* RTC Clock / 1024 */ -} RTC_PRESCALER_t; - -/* Compare Interrupt level */ -typedef enum RTC_COMPINTLVL_enum -{ - RTC_COMPINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ - RTC_COMPINTLVL_LO_gc = (0x01<<2), /* Low Level */ - RTC_COMPINTLVL_MED_gc = (0x02<<2), /* Medium Level */ - RTC_COMPINTLVL_HI_gc = (0x03<<2), /* High Level */ -} RTC_COMPINTLVL_t; - -/* Overflow Interrupt level */ -typedef enum RTC_OVFINTLVL_enum -{ - RTC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - RTC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ - RTC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ - RTC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ -} RTC_OVFINTLVL_t; - - -/* --------------------------------------------------------------------------- -TWI - Two-Wire Interface --------------------------------------------------------------------------- -*/ - -/* */ -typedef struct TWI_MASTER_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t CTRLC; /* Control Register C */ - register8_t STATUS; /* Status Register */ - register8_t BAUD; /* Baurd Rate Control Register */ - register8_t ADDR; /* Address Register */ - register8_t DATA; /* Data Register */ -} TWI_MASTER_t; - - -/* */ -typedef struct TWI_SLAVE_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t STATUS; /* Status Register */ - register8_t ADDR; /* Address Register */ - register8_t DATA; /* Data Register */ - register8_t ADDRMASK; /* Address Mask Register */ -} TWI_SLAVE_t; - - -/* Two-Wire Interface */ -typedef struct TWI_struct -{ - register8_t CTRL; /* TWI Common Control Register */ - TWI_MASTER_t MASTER; /* TWI master module */ - TWI_SLAVE_t SLAVE; /* TWI slave module */ -} TWI_t; - -/* SDA Hold Time */ -typedef enum TWI_SDAHOLD_enum -{ - TWI_SDAHOLD_OFF_gc = (0x00<<1), /* SDA Hold Time off */ - TWI_SDAHOLD_50NS_gc = (0x01<<1), /* SDA Hold Time 50 ns */ - TWI_SDAHOLD_300NS_gc = (0x02<<1), /* SDA Hold Time 300 ns */ - TWI_SDAHOLD_400NS_gc = (0x03<<1), /* SDA Hold Time 400 ns */ -} TWI_SDAHOLD_t; - -/* Master Interrupt Level */ -typedef enum TWI_MASTER_INTLVL_enum -{ - TWI_MASTER_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ - TWI_MASTER_INTLVL_LO_gc = (0x01<<6), /* Low Level */ - TWI_MASTER_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ - TWI_MASTER_INTLVL_HI_gc = (0x03<<6), /* High Level */ -} TWI_MASTER_INTLVL_t; - -/* Inactive Timeout */ -typedef enum TWI_MASTER_TIMEOUT_enum -{ - TWI_MASTER_TIMEOUT_DISABLED_gc = (0x00<<2), /* Bus Timeout Disabled */ - TWI_MASTER_TIMEOUT_50US_gc = (0x01<<2), /* 50 Microseconds */ - TWI_MASTER_TIMEOUT_100US_gc = (0x02<<2), /* 100 Microseconds */ - TWI_MASTER_TIMEOUT_200US_gc = (0x03<<2), /* 200 Microseconds */ -} TWI_MASTER_TIMEOUT_t; - -/* Master Command */ -typedef enum TWI_MASTER_CMD_enum -{ - TWI_MASTER_CMD_NOACT_gc = (0x00<<0), /* No Action */ - TWI_MASTER_CMD_REPSTART_gc = (0x01<<0), /* Issue Repeated Start Condition */ - TWI_MASTER_CMD_RECVTRANS_gc = (0x02<<0), /* Receive or Transmit Data */ - TWI_MASTER_CMD_STOP_gc = (0x03<<0), /* Issue Stop Condition */ -} TWI_MASTER_CMD_t; - -/* Master Bus State */ -typedef enum TWI_MASTER_BUSSTATE_enum -{ - TWI_MASTER_BUSSTATE_UNKNOWN_gc = (0x00<<0), /* Unknown Bus State */ - TWI_MASTER_BUSSTATE_IDLE_gc = (0x01<<0), /* Bus is Idle */ - TWI_MASTER_BUSSTATE_OWNER_gc = (0x02<<0), /* This Module Controls The Bus */ - TWI_MASTER_BUSSTATE_BUSY_gc = (0x03<<0), /* The Bus is Busy */ -} TWI_MASTER_BUSSTATE_t; - -/* Slave Interrupt Level */ -typedef enum TWI_SLAVE_INTLVL_enum -{ - TWI_SLAVE_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ - TWI_SLAVE_INTLVL_LO_gc = (0x01<<6), /* Low Level */ - TWI_SLAVE_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ - TWI_SLAVE_INTLVL_HI_gc = (0x03<<6), /* High Level */ -} TWI_SLAVE_INTLVL_t; - -/* Slave Command */ -typedef enum TWI_SLAVE_CMD_enum -{ - TWI_SLAVE_CMD_NOACT_gc = (0x00<<0), /* No Action */ - TWI_SLAVE_CMD_COMPTRANS_gc = (0x02<<0), /* Used To Complete a Transaction */ - TWI_SLAVE_CMD_RESPONSE_gc = (0x03<<0), /* Used in Response to Address/Data Interrupt */ -} TWI_SLAVE_CMD_t; - - -/* --------------------------------------------------------------------------- -USB - USB --------------------------------------------------------------------------- -*/ - -/* USB Endpoint */ -typedef struct USB_EP_struct -{ - register8_t STATUS; /* Endpoint Status */ - register8_t CTRL; /* Endpoint Control */ - _WORDREGISTER(CNT); /* USB Endpoint Counter */ - _WORDREGISTER(DATAPTR); /* Data Pointer */ - _WORDREGISTER(AUXDATA); /* Auxiliary Data */ -} USB_EP_t; - - -/* Universal Serial Bus */ -typedef struct USB_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t STATUS; /* Status Register */ - register8_t ADDR; /* Address Register */ - register8_t FIFOWP; /* FIFO Write Pointer Register */ - register8_t FIFORP; /* FIFO Read Pointer Register */ - _WORDREGISTER(EPPTR); /* Endpoint Configuration Table Pointer */ - register8_t INTCTRLA; /* Interrupt Control Register A */ - register8_t INTCTRLB; /* Interrupt Control Register B */ - register8_t INTFLAGSACLR; /* Clear Interrupt Flag Register A */ - register8_t INTFLAGSASET; /* Set Interrupt Flag Register A */ - register8_t INTFLAGSBCLR; /* Clear Interrupt Flag Register B */ - register8_t INTFLAGSBSET; /* Set Interrupt Flag Register B */ - register8_t reserved_0x0E; - register8_t reserved_0x0F; - register8_t reserved_0x10; - register8_t reserved_0x11; - register8_t reserved_0x12; - register8_t reserved_0x13; - register8_t reserved_0x14; - register8_t reserved_0x15; - register8_t reserved_0x16; - register8_t reserved_0x17; - register8_t reserved_0x18; - register8_t reserved_0x19; - register8_t reserved_0x1A; - register8_t reserved_0x1B; - register8_t reserved_0x1C; - register8_t reserved_0x1D; - register8_t reserved_0x1E; - register8_t reserved_0x1F; - register8_t reserved_0x20; - register8_t reserved_0x21; - register8_t reserved_0x22; - register8_t reserved_0x23; - register8_t reserved_0x24; - register8_t reserved_0x25; - register8_t reserved_0x26; - register8_t reserved_0x27; - register8_t reserved_0x28; - register8_t reserved_0x29; - register8_t reserved_0x2A; - register8_t reserved_0x2B; - register8_t reserved_0x2C; - register8_t reserved_0x2D; - register8_t reserved_0x2E; - register8_t reserved_0x2F; - register8_t reserved_0x30; - register8_t reserved_0x31; - register8_t reserved_0x32; - register8_t reserved_0x33; - register8_t reserved_0x34; - register8_t reserved_0x35; - register8_t reserved_0x36; - register8_t reserved_0x37; - register8_t reserved_0x38; - register8_t reserved_0x39; - register8_t CAL0; /* Calibration Byte 0 */ - register8_t CAL1; /* Calibration Byte 1 */ -} USB_t; - - -/* USB Endpoint Table */ -typedef struct USB_EP_TABLE_struct -{ - USB_EP_t EP0OUT; /* Endpoint 0 */ - USB_EP_t EP0IN; /* Endpoint 0 */ - USB_EP_t EP1OUT; /* Endpoint 1 */ - USB_EP_t EP1IN; /* Endpoint 1 */ - USB_EP_t EP2OUT; /* Endpoint 2 */ - USB_EP_t EP2IN; /* Endpoint 2 */ - USB_EP_t EP3OUT; /* Endpoint 3 */ - USB_EP_t EP3IN; /* Endpoint 3 */ - USB_EP_t EP4OUT; /* Endpoint 4 */ - USB_EP_t EP4IN; /* Endpoint 4 */ - USB_EP_t EP5OUT; /* Endpoint 5 */ - USB_EP_t EP5IN; /* Endpoint 5 */ - USB_EP_t EP6OUT; /* Endpoint 6 */ - USB_EP_t EP6IN; /* Endpoint 6 */ - USB_EP_t EP7OUT; /* Endpoint 7 */ - USB_EP_t EP7IN; /* Endpoint 7 */ - USB_EP_t EP8OUT; /* Endpoint 8 */ - USB_EP_t EP8IN; /* Endpoint 8 */ - USB_EP_t EP9OUT; /* Endpoint 9 */ - USB_EP_t EP9IN; /* Endpoint 9 */ - USB_EP_t EP10OUT; /* Endpoint 10 */ - USB_EP_t EP10IN; /* Endpoint 10 */ - USB_EP_t EP11OUT; /* Endpoint 11 */ - USB_EP_t EP11IN; /* Endpoint 11 */ - USB_EP_t EP12OUT; /* Endpoint 12 */ - USB_EP_t EP12IN; /* Endpoint 12 */ - USB_EP_t EP13OUT; /* Endpoint 13 */ - USB_EP_t EP13IN; /* Endpoint 13 */ - USB_EP_t EP14OUT; /* Endpoint 14 */ - USB_EP_t EP14IN; /* Endpoint 14 */ - USB_EP_t EP15OUT; /* Endpoint 15 */ - USB_EP_t EP15IN; /* Endpoint 15 */ - register8_t reserved_0x100; - register8_t reserved_0x101; - register8_t reserved_0x102; - register8_t reserved_0x103; - register8_t reserved_0x104; - register8_t reserved_0x105; - register8_t reserved_0x106; - register8_t reserved_0x107; - register8_t reserved_0x108; - register8_t reserved_0x109; - register8_t reserved_0x10A; - register8_t reserved_0x10B; - register8_t reserved_0x10C; - register8_t reserved_0x10D; - register8_t reserved_0x10E; - register8_t reserved_0x10F; - register8_t FRAMENUML; /* Frame Number Low Byte */ - register8_t FRAMENUMH; /* Frame Number High Byte */ -} USB_EP_TABLE_t; - -/* Interrupt level */ -typedef enum USB_INTLVL_enum -{ - USB_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ - USB_INTLVL_LO_gc = (0x01<<0), /* Low level */ - USB_INTLVL_MED_gc = (0x02<<0), /* Medium level */ - USB_INTLVL_HI_gc = (0x03<<0), /* High level */ -} USB_INTLVL_t; - -/* USB Endpoint Type */ -typedef enum USB_EP_TYPE_enum -{ - USB_EP_TYPE_DISABLE_gc = (0x00<<6), /* Endpoint Disabled */ - USB_EP_TYPE_CONTROL_gc = (0x01<<6), /* Control */ - USB_EP_TYPE_BULK_gc = (0x02<<6), /* Bulk/Interrupt */ - USB_EP_TYPE_ISOCHRONOUS_gc = (0x03<<6), /* Isochronous */ -} USB_EP_TYPE_t; - -/* USB Endpoint Buffersize */ -typedef enum USB_EP_BUFSIZE_enum -{ - USB_EP_BUFSIZE_8_gc = (0x00<<0), /* 8 bytes buffer size */ - USB_EP_BUFSIZE_16_gc = (0x01<<0), /* 16 bytes buffer size */ - USB_EP_BUFSIZE_32_gc = (0x02<<0), /* 32 bytes buffer size */ - USB_EP_BUFSIZE_64_gc = (0x03<<0), /* 64 bytes buffer size */ - USB_EP_BUFSIZE_128_gc = (0x04<<0), /* 128 bytes buffer size */ - USB_EP_BUFSIZE_256_gc = (0x05<<0), /* 256 bytes buffer size */ - USB_EP_BUFSIZE_512_gc = (0x06<<0), /* 512 bytes buffer size */ - USB_EP_BUFSIZE_1023_gc = (0x07<<0), /* 1023 bytes buffer size */ -} USB_EP_BUFSIZE_t; - - -/* --------------------------------------------------------------------------- -PORT - I/O Port Configuration --------------------------------------------------------------------------- -*/ - -/* I/O Ports */ -typedef struct PORT_struct -{ - register8_t DIR; /* I/O Port Data Direction */ - register8_t DIRSET; /* I/O Port Data Direction Set */ - register8_t DIRCLR; /* I/O Port Data Direction Clear */ - register8_t DIRTGL; /* I/O Port Data Direction Toggle */ - register8_t OUT; /* I/O Port Output */ - register8_t OUTSET; /* I/O Port Output Set */ - register8_t OUTCLR; /* I/O Port Output Clear */ - register8_t OUTTGL; /* I/O Port Output Toggle */ - register8_t IN; /* I/O port Input */ - register8_t INTCTRL; /* Interrupt Control Register */ - register8_t INT0MASK; /* Port Interrupt 0 Mask */ - register8_t INT1MASK; /* Port Interrupt 1 Mask */ - register8_t INTFLAGS; /* Interrupt Flag Register */ - register8_t reserved_0x0D; - register8_t REMAP; /* I/O Port Pin Remap Register */ - register8_t reserved_0x0F; - register8_t PIN0CTRL; /* Pin 0 Control Register */ - register8_t PIN1CTRL; /* Pin 1 Control Register */ - register8_t PIN2CTRL; /* Pin 2 Control Register */ - register8_t PIN3CTRL; /* Pin 3 Control Register */ - register8_t PIN4CTRL; /* Pin 4 Control Register */ - register8_t PIN5CTRL; /* Pin 5 Control Register */ - register8_t PIN6CTRL; /* Pin 6 Control Register */ - register8_t PIN7CTRL; /* Pin 7 Control Register */ -} PORT_t; - -/* Port Interrupt 0 Level */ -typedef enum PORT_INT0LVL_enum -{ - PORT_INT0LVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - PORT_INT0LVL_LO_gc = (0x01<<0), /* Low Level */ - PORT_INT0LVL_MED_gc = (0x02<<0), /* Medium Level */ - PORT_INT0LVL_HI_gc = (0x03<<0), /* High Level */ -} PORT_INT0LVL_t; - -/* Port Interrupt 1 Level */ -typedef enum PORT_INT1LVL_enum -{ - PORT_INT1LVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ - PORT_INT1LVL_LO_gc = (0x01<<2), /* Low Level */ - PORT_INT1LVL_MED_gc = (0x02<<2), /* Medium Level */ - PORT_INT1LVL_HI_gc = (0x03<<2), /* High Level */ -} PORT_INT1LVL_t; - -/* Output/Pull Configuration */ -typedef enum PORT_OPC_enum -{ - PORT_OPC_TOTEM_gc = (0x00<<3), /* Totempole */ - PORT_OPC_BUSKEEPER_gc = (0x01<<3), /* Totempole w/ Bus keeper on Input and Output */ - PORT_OPC_PULLDOWN_gc = (0x02<<3), /* Totempole w/ Pull-down on Input */ - PORT_OPC_PULLUP_gc = (0x03<<3), /* Totempole w/ Pull-up on Input */ - PORT_OPC_WIREDOR_gc = (0x04<<3), /* Wired OR */ - PORT_OPC_WIREDAND_gc = (0x05<<3), /* Wired AND */ - PORT_OPC_WIREDORPULL_gc = (0x06<<3), /* Wired OR w/ Pull-down */ - PORT_OPC_WIREDANDPULL_gc = (0x07<<3), /* Wired AND w/ Pull-up */ -} PORT_OPC_t; - -/* Input/Sense Configuration */ -typedef enum PORT_ISC_enum -{ - PORT_ISC_BOTHEDGES_gc = (0x00<<0), /* Sense Both Edges */ - PORT_ISC_RISING_gc = (0x01<<0), /* Sense Rising Edge */ - PORT_ISC_FALLING_gc = (0x02<<0), /* Sense Falling Edge */ - PORT_ISC_LEVEL_gc = (0x03<<0), /* Sense Level (Transparent For Events) */ - PORT_ISC_INPUT_DISABLE_gc = (0x07<<0), /* Disable Digital Input Buffer */ -} PORT_ISC_t; - - -/* --------------------------------------------------------------------------- -TC - 16-bit Timer/Counter With PWM --------------------------------------------------------------------------- -*/ - -/* 16-bit Timer/Counter 0 */ -typedef struct TC0_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t CTRLC; /* Control register C */ - register8_t CTRLD; /* Control Register D */ - register8_t CTRLE; /* Control Register E */ - register8_t reserved_0x05; - register8_t INTCTRLA; /* Interrupt Control Register A */ - register8_t INTCTRLB; /* Interrupt Control Register B */ - register8_t CTRLFCLR; /* Control Register F Clear */ - register8_t CTRLFSET; /* Control Register F Set */ - register8_t CTRLGCLR; /* Control Register G Clear */ - register8_t CTRLGSET; /* Control Register G Set */ - register8_t INTFLAGS; /* Interrupt Flag Register */ - register8_t reserved_0x0D; - register8_t reserved_0x0E; - register8_t TEMP; /* Temporary Register For 16-bit Access */ - register8_t reserved_0x10; - register8_t reserved_0x11; - register8_t reserved_0x12; - register8_t reserved_0x13; - register8_t reserved_0x14; - register8_t reserved_0x15; - register8_t reserved_0x16; - register8_t reserved_0x17; - register8_t reserved_0x18; - register8_t reserved_0x19; - register8_t reserved_0x1A; - register8_t reserved_0x1B; - register8_t reserved_0x1C; - register8_t reserved_0x1D; - register8_t reserved_0x1E; - register8_t reserved_0x1F; - _WORDREGISTER(CNT); /* Count */ - register8_t reserved_0x22; - register8_t reserved_0x23; - register8_t reserved_0x24; - register8_t reserved_0x25; - _WORDREGISTER(PER); /* Period */ - _WORDREGISTER(CCA); /* Compare or Capture A */ - _WORDREGISTER(CCB); /* Compare or Capture B */ - _WORDREGISTER(CCC); /* Compare or Capture C */ - _WORDREGISTER(CCD); /* Compare or Capture D */ - register8_t reserved_0x30; - register8_t reserved_0x31; - register8_t reserved_0x32; - register8_t reserved_0x33; - register8_t reserved_0x34; - register8_t reserved_0x35; - _WORDREGISTER(PERBUF); /* Period Buffer */ - _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ - _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ - _WORDREGISTER(CCCBUF); /* Compare Or Capture C Buffer */ - _WORDREGISTER(CCDBUF); /* Compare Or Capture D Buffer */ -} TC0_t; - - -/* 16-bit Timer/Counter 1 */ -typedef struct TC1_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t CTRLC; /* Control register C */ - register8_t CTRLD; /* Control Register D */ - register8_t CTRLE; /* Control Register E */ - register8_t reserved_0x05; - register8_t INTCTRLA; /* Interrupt Control Register A */ - register8_t INTCTRLB; /* Interrupt Control Register B */ - register8_t CTRLFCLR; /* Control Register F Clear */ - register8_t CTRLFSET; /* Control Register F Set */ - register8_t CTRLGCLR; /* Control Register G Clear */ - register8_t CTRLGSET; /* Control Register G Set */ - register8_t INTFLAGS; /* Interrupt Flag Register */ - register8_t reserved_0x0D; - register8_t reserved_0x0E; - register8_t TEMP; /* Temporary Register For 16-bit Access */ - register8_t reserved_0x10; - register8_t reserved_0x11; - register8_t reserved_0x12; - register8_t reserved_0x13; - register8_t reserved_0x14; - register8_t reserved_0x15; - register8_t reserved_0x16; - register8_t reserved_0x17; - register8_t reserved_0x18; - register8_t reserved_0x19; - register8_t reserved_0x1A; - register8_t reserved_0x1B; - register8_t reserved_0x1C; - register8_t reserved_0x1D; - register8_t reserved_0x1E; - register8_t reserved_0x1F; - _WORDREGISTER(CNT); /* Count */ - register8_t reserved_0x22; - register8_t reserved_0x23; - register8_t reserved_0x24; - register8_t reserved_0x25; - _WORDREGISTER(PER); /* Period */ - _WORDREGISTER(CCA); /* Compare or Capture A */ - _WORDREGISTER(CCB); /* Compare or Capture B */ - register8_t reserved_0x2C; - register8_t reserved_0x2D; - register8_t reserved_0x2E; - register8_t reserved_0x2F; - register8_t reserved_0x30; - register8_t reserved_0x31; - register8_t reserved_0x32; - register8_t reserved_0x33; - register8_t reserved_0x34; - register8_t reserved_0x35; - _WORDREGISTER(PERBUF); /* Period Buffer */ - _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ - _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ -} TC1_t; - -/* Clock Selection */ -typedef enum TC_CLKSEL_enum -{ - TC_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */ - TC_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */ - TC_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */ - TC_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */ - TC_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */ - TC_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */ - TC_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */ - TC_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */ - TC_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */ - TC_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */ - TC_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */ - TC_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */ -} TC_CLKSEL_t; - -/* Waveform Generation Mode */ -typedef enum TC_WGMODE_enum -{ - TC_WGMODE_NORMAL_gc = (0x00<<0), /* Normal Mode */ - TC_WGMODE_FRQ_gc = (0x01<<0), /* Frequency Generation Mode */ - TC_WGMODE_SINGLESLOPE_gc = (0x03<<0), /* Single Slope */ - TC_WGMODE_SS_gc = (0x03<<0), /* Single Slope */ - TC_WGMODE_DSTOP_gc = (0x05<<0), /* Dual Slope, Update on TOP */ - TC_WGMODE_DS_T_gc = (0x05<<0), /* Dual Slope, Update on TOP */ - TC_WGMODE_DSBOTH_gc = (0x06<<0), /* Dual Slope, Update on both TOP and BOTTOM */ - TC_WGMODE_DS_TB_gc = (0x06<<0), /* Dual Slope, Update on both TOP and BOTTOM */ - TC_WGMODE_DSBOTTOM_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */ - TC_WGMODE_DS_B_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */ -} TC_WGMODE_t; - -/* Byte Mode */ -typedef enum TC_BYTEM_enum -{ - TC_BYTEM_NORMAL_gc = (0x00<<0), /* 16-bit mode */ - TC_BYTEM_BYTEMODE_gc = (0x01<<0), /* Timer/Counter operating in byte mode only */ - TC_BYTEM_SPLITMODE_gc = (0x02<<0), /* Timer/Counter split into two 8-bit Counters */ -} TC_BYTEM_t; - -/* Event Action */ -typedef enum TC_EVACT_enum -{ - TC_EVACT_OFF_gc = (0x00<<5), /* No Event Action */ - TC_EVACT_CAPT_gc = (0x01<<5), /* Input Capture */ - TC_EVACT_UPDOWN_gc = (0x02<<5), /* Externally Controlled Up/Down Count */ - TC_EVACT_QDEC_gc = (0x03<<5), /* Quadrature Decode */ - TC_EVACT_RESTART_gc = (0x04<<5), /* Restart */ - TC_EVACT_FRQ_gc = (0x05<<5), /* Frequency Capture */ - TC_EVACT_PW_gc = (0x06<<5), /* Pulse-width Capture */ -} TC_EVACT_t; - -/* Event Selection */ -typedef enum TC_EVSEL_enum -{ - TC_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ - TC_EVSEL_CH0_gc = (0x08<<0), /* Event Channel 0 */ - TC_EVSEL_CH1_gc = (0x09<<0), /* Event Channel 1 */ - TC_EVSEL_CH2_gc = (0x0A<<0), /* Event Channel 2 */ - TC_EVSEL_CH3_gc = (0x0B<<0), /* Event Channel 3 */ -} TC_EVSEL_t; - -/* Error Interrupt Level */ -typedef enum TC_ERRINTLVL_enum -{ - TC_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ - TC_ERRINTLVL_LO_gc = (0x01<<2), /* Low Level */ - TC_ERRINTLVL_MED_gc = (0x02<<2), /* Medium Level */ - TC_ERRINTLVL_HI_gc = (0x03<<2), /* High Level */ -} TC_ERRINTLVL_t; - -/* Overflow Interrupt Level */ -typedef enum TC_OVFINTLVL_enum -{ - TC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - TC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ - TC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ - TC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ -} TC_OVFINTLVL_t; - -/* Compare or Capture D Interrupt Level */ -typedef enum TC_CCDINTLVL_enum -{ - TC_CCDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ - TC_CCDINTLVL_LO_gc = (0x01<<6), /* Low Level */ - TC_CCDINTLVL_MED_gc = (0x02<<6), /* Medium Level */ - TC_CCDINTLVL_HI_gc = (0x03<<6), /* High Level */ -} TC_CCDINTLVL_t; - -/* Compare or Capture C Interrupt Level */ -typedef enum TC_CCCINTLVL_enum -{ - TC_CCCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ - TC_CCCINTLVL_LO_gc = (0x01<<4), /* Low Level */ - TC_CCCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ - TC_CCCINTLVL_HI_gc = (0x03<<4), /* High Level */ -} TC_CCCINTLVL_t; - -/* Compare or Capture B Interrupt Level */ -typedef enum TC_CCBINTLVL_enum -{ - TC_CCBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ - TC_CCBINTLVL_LO_gc = (0x01<<2), /* Low Level */ - TC_CCBINTLVL_MED_gc = (0x02<<2), /* Medium Level */ - TC_CCBINTLVL_HI_gc = (0x03<<2), /* High Level */ -} TC_CCBINTLVL_t; - -/* Compare or Capture A Interrupt Level */ -typedef enum TC_CCAINTLVL_enum -{ - TC_CCAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - TC_CCAINTLVL_LO_gc = (0x01<<0), /* Low Level */ - TC_CCAINTLVL_MED_gc = (0x02<<0), /* Medium Level */ - TC_CCAINTLVL_HI_gc = (0x03<<0), /* High Level */ -} TC_CCAINTLVL_t; - -/* Timer/Counter Command */ -typedef enum TC_CMD_enum -{ - TC_CMD_NONE_gc = (0x00<<2), /* No Command */ - TC_CMD_UPDATE_gc = (0x01<<2), /* Force Update */ - TC_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ - TC_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ -} TC_CMD_t; - - -/* --------------------------------------------------------------------------- -AWEX - Timer/Counter Advanced Waveform Extension --------------------------------------------------------------------------- -*/ - -/* Advanced Waveform Extension */ -typedef struct AWEX_struct -{ - register8_t CTRL; /* Control Register */ - register8_t reserved_0x01; - register8_t FDEMASK; /* Fault Detection Event Mask */ - register8_t FDCTRL; /* Fault Detection Control Register */ - register8_t STATUS; /* Status Register */ - register8_t STATUSSET; /* Status Set Register */ - register8_t DTBOTH; /* Dead Time Both Sides */ - register8_t DTBOTHBUF; /* Dead Time Both Sides Buffer */ - register8_t DTLS; /* Dead Time Low Side */ - register8_t DTHS; /* Dead Time High Side */ - register8_t DTLSBUF; /* Dead Time Low Side Buffer */ - register8_t DTHSBUF; /* Dead Time High Side Buffer */ - register8_t OUTOVEN; /* Output Override Enable */ -} AWEX_t; - -/* Fault Detect Action */ -typedef enum AWEX_FDACT_enum -{ - AWEX_FDACT_NONE_gc = (0x00<<0), /* No Fault Protection */ - AWEX_FDACT_CLEAROE_gc = (0x01<<0), /* Clear Output Enable Bits */ - AWEX_FDACT_CLEARDIR_gc = (0x03<<0), /* Clear I/O Port Direction Bits */ -} AWEX_FDACT_t; - - -/* --------------------------------------------------------------------------- -HIRES - Timer/Counter High-Resolution Extension --------------------------------------------------------------------------- -*/ - -/* High-Resolution Extension */ -typedef struct HIRES_struct -{ - register8_t CTRLA; /* Control Register */ -} HIRES_t; - -/* High Resolution Enable */ -typedef enum HIRES_HREN_enum -{ - HIRES_HREN_NONE_gc = (0x00<<0), /* No Fault Protection */ - HIRES_HREN_TC0_gc = (0x01<<0), /* Enable High Resolution on Timer/Counter 0 */ - HIRES_HREN_TC1_gc = (0x02<<0), /* Enable High Resolution on Timer/Counter 1 */ - HIRES_HREN_BOTH_gc = (0x03<<0), /* Enable High Resolution both Timer/Counters */ -} HIRES_HREN_t; - - -/* --------------------------------------------------------------------------- -USART - Universal Asynchronous Receiver-Transmitter --------------------------------------------------------------------------- -*/ - -/* Universal Synchronous/Asynchronous Receiver/Transmitter */ -typedef struct USART_struct -{ - register8_t DATA; /* Data Register */ - register8_t STATUS; /* Status Register */ - register8_t reserved_0x02; - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t CTRLC; /* Control Register C */ - register8_t BAUDCTRLA; /* Baud Rate Control Register A */ - register8_t BAUDCTRLB; /* Baud Rate Control Register B */ -} USART_t; - -/* Receive Complete Interrupt level */ -typedef enum USART_RXCINTLVL_enum -{ - USART_RXCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ - USART_RXCINTLVL_LO_gc = (0x01<<4), /* Low Level */ - USART_RXCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ - USART_RXCINTLVL_HI_gc = (0x03<<4), /* High Level */ -} USART_RXCINTLVL_t; - -/* Transmit Complete Interrupt level */ -typedef enum USART_TXCINTLVL_enum -{ - USART_TXCINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ - USART_TXCINTLVL_LO_gc = (0x01<<2), /* Low Level */ - USART_TXCINTLVL_MED_gc = (0x02<<2), /* Medium Level */ - USART_TXCINTLVL_HI_gc = (0x03<<2), /* High Level */ -} USART_TXCINTLVL_t; - -/* Data Register Empty Interrupt level */ -typedef enum USART_DREINTLVL_enum -{ - USART_DREINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - USART_DREINTLVL_LO_gc = (0x01<<0), /* Low Level */ - USART_DREINTLVL_MED_gc = (0x02<<0), /* Medium Level */ - USART_DREINTLVL_HI_gc = (0x03<<0), /* High Level */ -} USART_DREINTLVL_t; - -/* Character Size */ -typedef enum USART_CHSIZE_enum -{ - USART_CHSIZE_5BIT_gc = (0x00<<0), /* Character size: 5 bit */ - USART_CHSIZE_6BIT_gc = (0x01<<0), /* Character size: 6 bit */ - USART_CHSIZE_7BIT_gc = (0x02<<0), /* Character size: 7 bit */ - USART_CHSIZE_8BIT_gc = (0x03<<0), /* Character size: 8 bit */ - USART_CHSIZE_9BIT_gc = (0x07<<0), /* Character size: 9 bit */ -} USART_CHSIZE_t; - -/* Communication Mode */ -typedef enum USART_CMODE_enum -{ - USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6), /* Asynchronous Mode */ - USART_CMODE_SYNCHRONOUS_gc = (0x01<<6), /* Synchronous Mode */ - USART_CMODE_IRDA_gc = (0x02<<6), /* IrDA Mode */ - USART_CMODE_MSPI_gc = (0x03<<6), /* Master SPI Mode */ -} USART_CMODE_t; - -/* Parity Mode */ -typedef enum USART_PMODE_enum -{ - USART_PMODE_DISABLED_gc = (0x00<<4), /* No Parity */ - USART_PMODE_EVEN_gc = (0x02<<4), /* Even Parity */ - USART_PMODE_ODD_gc = (0x03<<4), /* Odd Parity */ -} USART_PMODE_t; - - -/* --------------------------------------------------------------------------- -SPI - Serial Peripheral Interface --------------------------------------------------------------------------- -*/ - -/* Serial Peripheral Interface */ -typedef struct SPI_struct -{ - register8_t CTRL; /* Control Register */ - register8_t INTCTRL; /* Interrupt Control Register */ - register8_t STATUS; /* Status Register */ - register8_t DATA; /* Data Register */ -} SPI_t; - -/* SPI Mode */ -typedef enum SPI_MODE_enum -{ - SPI_MODE_0_gc = (0x00<<2), /* SPI Mode 0 */ - SPI_MODE_1_gc = (0x01<<2), /* SPI Mode 1 */ - SPI_MODE_2_gc = (0x02<<2), /* SPI Mode 2 */ - SPI_MODE_3_gc = (0x03<<2), /* SPI Mode 3 */ -} SPI_MODE_t; - -/* Prescaler setting */ -typedef enum SPI_PRESCALER_enum -{ - SPI_PRESCALER_DIV4_gc = (0x00<<0), /* System Clock / 4 */ - SPI_PRESCALER_DIV16_gc = (0x01<<0), /* System Clock / 16 */ - SPI_PRESCALER_DIV64_gc = (0x02<<0), /* System Clock / 64 */ - SPI_PRESCALER_DIV128_gc = (0x03<<0), /* System Clock / 128 */ -} SPI_PRESCALER_t; - -/* Interrupt level */ -typedef enum SPI_INTLVL_enum -{ - SPI_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - SPI_INTLVL_LO_gc = (0x01<<0), /* Low Level */ - SPI_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ - SPI_INTLVL_HI_gc = (0x03<<0), /* High Level */ -} SPI_INTLVL_t; - - -/* --------------------------------------------------------------------------- -IRCOM - IR Communication Module --------------------------------------------------------------------------- -*/ - -/* IR Communication Module */ -typedef struct IRCOM_struct -{ - register8_t CTRL; /* Control Register */ - register8_t TXPLCTRL; /* IrDA Transmitter Pulse Length Control Register */ - register8_t RXPLCTRL; /* IrDA Receiver Pulse Length Control Register */ -} IRCOM_t; - -/* Event channel selection */ -typedef enum IRDA_EVSEL_enum -{ - IRDA_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ - IRDA_EVSEL_0_gc = (0x08<<0), /* Event Channel 0 */ - IRDA_EVSEL_1_gc = (0x09<<0), /* Event Channel 1 */ - IRDA_EVSEL_2_gc = (0x0A<<0), /* Event Channel 2 */ - IRDA_EVSEL_3_gc = (0x0B<<0), /* Event Channel 3 */ -} IRDA_EVSEL_t; - - -/* --------------------------------------------------------------------------- -LCD - LCD Controller --------------------------------------------------------------------------- -*/ - -/* LCD Controller */ -typedef struct LCD_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t CTRLC; /* Control Register C */ - register8_t INTCTRL; /* Interrupt Enable Register */ - register8_t INTFLAG; /* Interrupt Flag Register */ - register8_t CTRLD; /* Control Register D */ - register8_t CTRLE; /* Control Register E */ - register8_t CTRLF; /* Control Register F */ - register8_t CTRLG; /* Control Register G */ - register8_t CTRLH; /* Control Register H */ - register8_t reserved_0x0A; - register8_t reserved_0x0B; - register8_t reserved_0x0C; - register8_t reserved_0x0D; - register8_t reserved_0x0E; - register8_t reserved_0x0F; - register8_t DATA0; /* LCD Data Register 0 */ - register8_t DATA1; /* LCD Data Register 1 */ - register8_t DATA2; /* LCD Data Register 2 */ - register8_t DATA3; /* LCD Data Register 3 */ - register8_t DATA4; /* LCD Data Register 4 */ - register8_t DATA5; /* LCD Data Register 5 */ - register8_t DATA6; /* LCD Data Register 6 */ - register8_t DATA7; /* LCD Data Register 7 */ - register8_t DATA8; /* LCD Data Register 8 */ - register8_t DATA9; /* LCD Data Register 9 */ - register8_t DATA10; /* LCD Data Register 10 */ - register8_t DATA11; /* LCD Data Register 11 */ - register8_t DATA12; /* LCD Data Register 12 */ - register8_t DATA13; /* LCD Data Register 13 */ - register8_t DATA14; /* LCD Data Register 14 */ - register8_t DATA15; /* LCD Data Register 15 */ - register8_t DATA16; /* LCD Data Register 16 */ - register8_t DATA17; /* LCD Data Register 17 */ - register8_t DATA18; /* LCD Data Register 18 */ - register8_t DATA19; /* LCD Data Register 19 */ -} LCD_t; - -/* LCD Blink Rate */ -typedef enum LCD_BLINKRATE_enum -{ - LCD_BLINKRATE_4Hz_gc = (0x00<<0), /* 4Hz Blink Rate */ - LCD_BLINKRATE_2Hz_gc = (0x01<<0), /* 2Hz Blink Rate */ - LCD_BLINKRATE_1Hz_gc = (0x02<<0), /* 1Hz Blink Rate */ - LCD_BLINKRATE_0Hz5_gc = (0x03<<0), /* 0.5Hz Blink Rate */ -} LCD_BLINKRATE_t; - -/* LCD Clock Divide */ -typedef enum LCD_CLKDIV_enum -{ - LCD_CLKDIV_DivBy1_gc = (0x00<<4), /* frame rate of 256 Hz */ - LCD_CLKDIV_DivBy2_gc = (0x01<<4), /* frame rate of 128 Hz */ - LCD_CLKDIV_DivBy3_gc = (0x02<<4), /* frame rate of 83.5 Hz */ - LCD_CLKDIV_DivBy4_gc = (0x03<<4), /* frame rate of 64 Hz */ - LCD_CLKDIV_DivBy5_gc = (0x04<<4), /* frame rate of 51.2 Hz */ - LCD_CLKDIV_DivBy6_gc = (0x05<<4), /* frame rate of 42.7 Hz */ - LCD_CLKDIV_DivBy7_gc = (0x06<<4), /* frame rate of 36.6 Hz */ - LCD_CLKDIV_DivBy8_gc = (0x07<<4), /* frame rate of 32 Hz */ -} LCD_CLKDIV_t; - -/* Duty Select */ -typedef enum LCD_DUTY_enum -{ - LCD_DUTY_1_4_gc = (0x00<<0), /* Duty=1/4, Bias=1/3, COM0:3 */ - LCD_DUTY_Static_gc = (0x01<<0), /* Duty=Static, Bias=Static, COM0 */ - LCD_DUTY_1_2_gc = (0x02<<0), /* Duty=1/2, Bias=1/3, COM0:1 */ - LCD_DUTY_1_3_gc = (0x03<<0), /* Duty=1/3, Bias=1/3, COM0:2 */ -} LCD_DUTY_t; - -/* LCD Prescaler Select */ -typedef enum LCD_PRESC_enum -{ - LCD_PRESC_8_gc = (0x00<<7), /* clk_lcd/8 */ - LCD_PRESC_16_gc = (0x01<<7), /* clk_lcd/16 */ -} LCD_PRESC_t; - -/* Type of Digit */ -typedef enum LCD_TDG_enum -{ - LCD_TDG_7S_3C_gc = (0x00<<6), /* 7-segment with 3 COMs */ - LCD_TDG_7S_4C_gc = (0x01<<6), /* 7-segment with 4 COMs */ - LCD_TDG_14S_4C_gc = (0x02<<6), /* 14-segment with 4 COMs */ - LCD_TDG_16S_3C_gc = (0x03<<6), /* 16-segment with 3 COMs */ -} LCD_TDG_t; - - -/* --------------------------------------------------------------------------- -FUSE - Fuses and Lockbits --------------------------------------------------------------------------- -*/ - -/* Fuses */ -typedef struct NVM_FUSES_struct -{ - register8_t FUSEBYTE0; /* JTAG User ID */ - register8_t FUSEBYTE1; /* Watchdog Configuration */ - register8_t FUSEBYTE2; /* Reset Configuration */ - register8_t reserved_0x03; - register8_t FUSEBYTE4; /* Start-up Configuration */ - register8_t FUSEBYTE5; /* EESAVE and BOD Level */ -} NVM_FUSES_t; - -/* Boot Loader Section Reset Vector */ -typedef enum BOOTRST_enum -{ - BOOTRST_BOOTLDR_gc = (0x00<<6), /* Boot Loader Reset */ - BOOTRST_APPLICATION_gc = (0x01<<6), /* Application Reset */ -} BOOTRST_t; - -/* Timer Oscillator pin location */ -typedef enum TOSCSEL_enum -{ - TOSCSEL_ALTERNATE_gc = (0x00<<5), /* TOSC1 / TOSC2 on separate pins */ - TOSCSEL_XTAL_gc = (0x01<<5), /* TOSC1 / TOSC2 shared with XTAL1 / XTAL2 */ -} TOSCSEL_t; - -/* BOD operation */ -typedef enum BOD_enum -{ - BOD_SAMPLED_gc = (0x01<<0), /* BOD enabled in sampled mode */ - BOD_CONTINUOUS_gc = (0x02<<0), /* BOD enabled continuously */ - BOD_DISABLED_gc = (0x03<<0), /* BOD Disabled */ -} BOD_t; - -/* BOD operation */ -typedef enum BODACT_enum -{ - BODACT_SAMPLED_gc = (0x01<<4), /* BOD enabled in sampled mode */ - BODACT_CONTINUOUS_gc = (0x02<<4), /* BOD enabled continuously */ - BODACT_DISABLED_gc = (0x03<<4), /* BOD Disabled */ -} BODACT_t; - -/* Watchdog (Window) Timeout Period */ -typedef enum WD_enum -{ - WD_8CLK_gc = (0x00<<4), /* 8 cycles (8ms @ 3.3V) */ - WD_16CLK_gc = (0x01<<4), /* 16 cycles (16ms @ 3.3V) */ - WD_32CLK_gc = (0x02<<4), /* 32 cycles (32ms @ 3.3V) */ - WD_64CLK_gc = (0x03<<4), /* 64 cycles (64ms @ 3.3V) */ - WD_128CLK_gc = (0x04<<4), /* 128 cycles (0.125s @ 3.3V) */ - WD_256CLK_gc = (0x05<<4), /* 256 cycles (0.25s @ 3.3V) */ - WD_512CLK_gc = (0x06<<4), /* 512 cycles (0.5s @ 3.3V) */ - WD_1KCLK_gc = (0x07<<4), /* 1K cycles (1s @ 3.3V) */ - WD_2KCLK_gc = (0x08<<4), /* 2K cycles (2s @ 3.3V) */ - WD_4KCLK_gc = (0x09<<4), /* 4K cycles (4s @ 3.3V) */ - WD_8KCLK_gc = (0x0A<<4), /* 8K cycles (8s @ 3.3V) */ -} WD_t; - -/* Watchdog (Window) Timeout Period */ -typedef enum WDP_enum -{ - WDP_8CLK_gc = (0x00<<0), /* 8 cycles (8ms @ 3.3V) */ - WDP_16CLK_gc = (0x01<<0), /* 16 cycles (16ms @ 3.3V) */ - WDP_32CLK_gc = (0x02<<0), /* 32 cycles (32ms @ 3.3V) */ - WDP_64CLK_gc = (0x03<<0), /* 64 cycles (64ms @ 3.3V) */ - WDP_128CLK_gc = (0x04<<0), /* 128 cycles (0.125s @ 3.3V) */ - WDP_256CLK_gc = (0x05<<0), /* 256 cycles (0.25s @ 3.3V) */ - WDP_512CLK_gc = (0x06<<0), /* 512 cycles (0.5s @ 3.3V) */ - WDP_1KCLK_gc = (0x07<<0), /* 1K cycles (1s @ 3.3V) */ - WDP_2KCLK_gc = (0x08<<0), /* 2K cycles (2s @ 3.3V) */ - WDP_4KCLK_gc = (0x09<<0), /* 4K cycles (4s @ 3.3V) */ - WDP_8KCLK_gc = (0x0A<<0), /* 8K cycles (8s @ 3.3V) */ -} WDP_t; - -/* Start-up Time */ -typedef enum SUT_enum -{ - SUT_0MS_gc = (0x03<<2), /* 0 ms */ - SUT_4MS_gc = (0x01<<2), /* 4 ms */ - SUT_64MS_gc = (0x00<<2), /* 64 ms */ -} SUT_t; - -/* Brownout Detection Voltage Level */ -typedef enum BODLVL_enum -{ - BODLVL_1V6_gc = (0x07<<0), /* 1.6 V */ - BODLVL_1V8_gc = (0x06<<0), /* 1.8 V */ - BODLVL_2V0_gc = (0x05<<0), /* 2.0 V */ - BODLVL_2V2_gc = (0x04<<0), /* 2.2 V */ - BODLVL_2V4_gc = (0x03<<0), /* 2.4 V */ - BODLVL_2V6_gc = (0x02<<0), /* 2.6 V */ - BODLVL_2V8_gc = (0x01<<0), /* 2.8 V */ - BODLVL_3V0_gc = (0x00<<0), /* 3.0 V */ -} BODLVL_t; - - -/* --------------------------------------------------------------------------- -LOCKBIT - Fuses and Lockbits --------------------------------------------------------------------------- -*/ - -/* Lock Bits */ -typedef struct NVM_LOCKBITS_struct -{ - register8_t LOCK_BITS; /* Lock Bits (Changed from LOCKBITS to avoid avr-libc collision) */ -} NVM_LOCKBITS_t; - -/* Boot lock bits - boot setcion */ -typedef enum FUSE_BLBB_enum -{ - FUSE_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ - FUSE_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ - FUSE_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ - FUSE_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ -} FUSE_BLBB_t; - -/* Boot lock bits - application section */ -typedef enum FUSE_BLBA_enum -{ - FUSE_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ - FUSE_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ - FUSE_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ - FUSE_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ -} FUSE_BLBA_t; - -/* Boot lock bits - application table section */ -typedef enum FUSE_BLBAT_enum -{ - FUSE_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ - FUSE_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ - FUSE_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ - FUSE_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ -} FUSE_BLBAT_t; - -/* Lock bits */ -typedef enum FUSE_LB_enum -{ - FUSE_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ - FUSE_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ - FUSE_LB_NOLOCK_gc = (0x03<<0), /* No locks */ -} FUSE_LB_t; - - -/* --------------------------------------------------------------------------- -SIGROW - Signature Row --------------------------------------------------------------------------- -*/ - -/* Production Signatures */ -typedef struct NVM_PROD_SIGNATURES_struct -{ - register8_t RCOSC2M; /* RCOSC 2 MHz Calibration Value B */ - register8_t RCOSC2MA; /* RCOSC 2 MHz Calibration Value A */ - register8_t RCOSC32K; /* RCOSC 32.768 kHz Calibration Value */ - register8_t RCOSC32M; /* RCOSC 32 MHz Calibration Value B */ - register8_t RCOSC32MA; /* RCOSC 32 MHz Calibration Value A */ - register8_t reserved_0x05; - register8_t reserved_0x06; - register8_t reserved_0x07; - register8_t LOTNUM0; /* Lot Number Byte 0, ASCII */ - register8_t LOTNUM1; /* Lot Number Byte 1, ASCII */ - register8_t LOTNUM2; /* Lot Number Byte 2, ASCII */ - register8_t LOTNUM3; /* Lot Number Byte 3, ASCII */ - register8_t LOTNUM4; /* Lot Number Byte 4, ASCII */ - register8_t LOTNUM5; /* Lot Number Byte 5, ASCII */ - register8_t reserved_0x0E; - register8_t reserved_0x0F; - register8_t WAFNUM; /* Wafer Number */ - register8_t reserved_0x11; - register8_t COORDX0; /* Wafer Coordinate X Byte 0 */ - register8_t COORDX1; /* Wafer Coordinate X Byte 1 */ - register8_t COORDY0; /* Wafer Coordinate Y Byte 0 */ - register8_t COORDY1; /* Wafer Coordinate Y Byte 1 */ - register8_t reserved_0x16; - register8_t reserved_0x17; - register8_t reserved_0x18; - register8_t reserved_0x19; - register8_t USBCAL0; /* USB Calibration Byte 0 */ - register8_t USBCAL1; /* USB Calibration Byte 1 */ - register8_t USBRCOSC; /* USB RCOSC Calibration Value B */ - register8_t USBRCOSCA; /* USB RCOSC Calibration Value A */ - register8_t reserved_0x1E; - register8_t reserved_0x1F; - register8_t ADCACAL0; /* ADCA Calibration Byte 0 */ - register8_t ADCACAL1; /* ADCA Calibration Byte 1 */ - register8_t reserved_0x22; - register8_t reserved_0x23; - register8_t ADCBCAL0; /* ADCB Calibration Byte 0 */ - register8_t ADCBCAL1; /* ADCB Calibration Byte 1 */ - register8_t reserved_0x26; - register8_t reserved_0x27; - register8_t reserved_0x28; - register8_t reserved_0x29; - register8_t reserved_0x2A; - register8_t reserved_0x2B; - register8_t reserved_0x2C; - register8_t reserved_0x2D; - register8_t TEMPSENSE0; /* Temperature Sensor Calibration Byte 0 */ - register8_t TEMPSENSE1; /* Temperature Sensor Calibration Byte 1 */ - register8_t reserved_0x30; - register8_t reserved_0x31; - register8_t reserved_0x32; - register8_t reserved_0x33; - register8_t reserved_0x34; - register8_t reserved_0x35; - register8_t reserved_0x36; - register8_t reserved_0x37; - register8_t reserved_0x38; - register8_t reserved_0x39; - register8_t reserved_0x3A; - register8_t reserved_0x3B; - register8_t reserved_0x3C; - register8_t reserved_0x3D; - register8_t reserved_0x3E; - register8_t reserved_0x3F; - register8_t reserved_0x40; - register8_t reserved_0x41; - register8_t reserved_0x42; - register8_t reserved_0x43; - register8_t reserved_0x44; - register8_t reserved_0x45; - register8_t reserved_0x46; - register8_t reserved_0x47; -} NVM_PROD_SIGNATURES_t; - -/* -========================================================================== -IO Module Instances. Mapped to memory. -========================================================================== -*/ - -#define VPORT0 (*(VPORT_t *) 0x0010) /* Virtual Port */ -#define VPORT1 (*(VPORT_t *) 0x0014) /* Virtual Port */ -#define VPORT2 (*(VPORT_t *) 0x0018) /* Virtual Port */ -#define VPORT3 (*(VPORT_t *) 0x001C) /* Virtual Port */ -#define OCD (*(OCD_t *) 0x002E) /* On-Chip Debug System */ -#define CLK (*(CLK_t *) 0x0040) /* Clock System */ -#define SLEEP (*(SLEEP_t *) 0x0048) /* Sleep Controller */ -#define OSC (*(OSC_t *) 0x0050) /* Oscillator */ -#define DFLLRC32M (*(DFLL_t *) 0x0060) /* DFLL */ -#define DFLLRC2M (*(DFLL_t *) 0x0068) /* DFLL */ -#define PR (*(PR_t *) 0x0070) /* Power Reduction */ -#define RST (*(RST_t *) 0x0078) /* Reset */ -#define WDT (*(WDT_t *) 0x0080) /* Watch-Dog Timer */ -#define MCU (*(MCU_t *) 0x0090) /* MCU Control */ -#define PMIC (*(PMIC_t *) 0x00A0) /* Programmable Multi-level Interrupt Controller */ -#define PORTCFG (*(PORTCFG_t *) 0x00B0) /* I/O port Configuration */ -#define AES (*(AES_t *) 0x00C0) /* AES Module */ -#define CRC (*(CRC_t *) 0x00D0) /* Cyclic Redundancy Checker */ -#define DMA (*(DMA_t *) 0x0100) /* DMA Controller */ -#define EVSYS (*(EVSYS_t *) 0x0180) /* Event System */ -#define NVM (*(NVM_t *) 0x01C0) /* Non-volatile Memory Controller */ -#define ADCB (*(ADC_t *) 0x0240) /* Analog-to-Digital Converter */ -#define ACB (*(AC_t *) 0x0390) /* Analog Comparator */ -#define RTC (*(RTC_t *) 0x0400) /* Real-Time Counter */ -#define TWIC (*(TWI_t *) 0x0480) /* Two-Wire Interface */ -#define USB (*(USB_t *) 0x04C0) /* Universal Serial Bus */ -#define PORTB (*(PORT_t *) 0x0620) /* I/O Ports */ -#define PORTC (*(PORT_t *) 0x0640) /* I/O Ports */ -#define PORTD (*(PORT_t *) 0x0660) /* I/O Ports */ -#define PORTG (*(PORT_t *) 0x06C0) /* I/O Ports */ -#define PORTM (*(PORT_t *) 0x0760) /* I/O Ports */ -#define PORTR (*(PORT_t *) 0x07E0) /* I/O Ports */ -#define TCC0 (*(TC0_t *) 0x0800) /* 16-bit Timer/Counter 0 */ -#define TCC1 (*(TC1_t *) 0x0840) /* 16-bit Timer/Counter 1 */ -#define AWEXC (*(AWEX_t *) 0x0880) /* Advanced Waveform Extension */ -#define HIRESC (*(HIRES_t *) 0x0890) /* High-Resolution Extension */ -#define USARTC0 (*(USART_t *) 0x08A0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ -#define SPIC (*(SPI_t *) 0x08C0) /* Serial Peripheral Interface */ -#define IRCOM (*(IRCOM_t *) 0x08F8) /* IR Communication Module */ -#define LCD (*(LCD_t *) 0x0D00) /* LCD Controller */ - - -#endif /* !defined (__ASSEMBLER__) */ - - -/* ========== Flattened fully qualified IO register names ========== */ - -/* GPIO - General Purpose IO Registers */ -#define GPIO_GPIOR0 _SFR_MEM8(0x0000) -#define GPIO_GPIOR1 _SFR_MEM8(0x0001) -#define GPIO_GPIOR2 _SFR_MEM8(0x0002) -#define GPIO_GPIOR3 _SFR_MEM8(0x0003) - -/* Deprecated */ -#define GPIO_GPIO0 _SFR_MEM8(0x0000) -#define GPIO_GPIO1 _SFR_MEM8(0x0001) -#define GPIO_GPIO2 _SFR_MEM8(0x0002) -#define GPIO_GPIO3 _SFR_MEM8(0x0003) - -/* NVM_FUSES - Fuses */ -#define FUSE_FUSEBYTE0 _SFR_MEM8(0x0000) -#define FUSE_FUSEBYTE1 _SFR_MEM8(0x0001) -#define FUSE_FUSEBYTE2 _SFR_MEM8(0x0002) -#define FUSE_FUSEBYTE4 _SFR_MEM8(0x0004) -#define FUSE_FUSEBYTE5 _SFR_MEM8(0x0005) - -/* NVM_LOCKBITS - Lock Bits */ -#define LOCKBIT_LOCKBITS _SFR_MEM8(0x0000) - -/* NVM_PROD_SIGNATURES - Production Signatures */ -#define PRODSIGNATURES_RCOSC2M _SFR_MEM8(0x0000) -#define PRODSIGNATURES_RCOSC2MA _SFR_MEM8(0x0001) -#define PRODSIGNATURES_RCOSC32K _SFR_MEM8(0x0002) -#define PRODSIGNATURES_RCOSC32M _SFR_MEM8(0x0003) -#define PRODSIGNATURES_RCOSC32MA _SFR_MEM8(0x0004) -#define PRODSIGNATURES_LOTNUM0 _SFR_MEM8(0x0008) -#define PRODSIGNATURES_LOTNUM1 _SFR_MEM8(0x0009) -#define PRODSIGNATURES_LOTNUM2 _SFR_MEM8(0x000A) -#define PRODSIGNATURES_LOTNUM3 _SFR_MEM8(0x000B) -#define PRODSIGNATURES_LOTNUM4 _SFR_MEM8(0x000C) -#define PRODSIGNATURES_LOTNUM5 _SFR_MEM8(0x000D) -#define PRODSIGNATURES_WAFNUM _SFR_MEM8(0x0010) -#define PRODSIGNATURES_COORDX0 _SFR_MEM8(0x0012) -#define PRODSIGNATURES_COORDX1 _SFR_MEM8(0x0013) -#define PRODSIGNATURES_COORDY0 _SFR_MEM8(0x0014) -#define PRODSIGNATURES_COORDY1 _SFR_MEM8(0x0015) -#define PRODSIGNATURES_USBCAL0 _SFR_MEM8(0x001A) -#define PRODSIGNATURES_USBCAL1 _SFR_MEM8(0x001B) -#define PRODSIGNATURES_USBRCOSC _SFR_MEM8(0x001C) -#define PRODSIGNATURES_USBRCOSCA _SFR_MEM8(0x001D) -#define PRODSIGNATURES_ADCACAL0 _SFR_MEM8(0x0020) -#define PRODSIGNATURES_ADCACAL1 _SFR_MEM8(0x0021) -#define PRODSIGNATURES_ADCBCAL0 _SFR_MEM8(0x0024) -#define PRODSIGNATURES_ADCBCAL1 _SFR_MEM8(0x0025) -#define PRODSIGNATURES_TEMPSENSE0 _SFR_MEM8(0x002E) -#define PRODSIGNATURES_TEMPSENSE1 _SFR_MEM8(0x002F) - -/* VPORT - Virtual Port */ -#define VPORT0_DIR _SFR_MEM8(0x0010) -#define VPORT0_OUT _SFR_MEM8(0x0011) -#define VPORT0_IN _SFR_MEM8(0x0012) -#define VPORT0_INTFLAGS _SFR_MEM8(0x0013) - -/* VPORT - Virtual Port */ -#define VPORT1_DIR _SFR_MEM8(0x0014) -#define VPORT1_OUT _SFR_MEM8(0x0015) -#define VPORT1_IN _SFR_MEM8(0x0016) -#define VPORT1_INTFLAGS _SFR_MEM8(0x0017) - -/* VPORT - Virtual Port */ -#define VPORT2_DIR _SFR_MEM8(0x0018) -#define VPORT2_OUT _SFR_MEM8(0x0019) -#define VPORT2_IN _SFR_MEM8(0x001A) -#define VPORT2_INTFLAGS _SFR_MEM8(0x001B) - -/* VPORT - Virtual Port */ -#define VPORT3_DIR _SFR_MEM8(0x001C) -#define VPORT3_OUT _SFR_MEM8(0x001D) -#define VPORT3_IN _SFR_MEM8(0x001E) -#define VPORT3_INTFLAGS _SFR_MEM8(0x001F) - -/* OCD - On-Chip Debug System */ -#define OCD_OCDR0 _SFR_MEM8(0x002E) -#define OCD_OCDR1 _SFR_MEM8(0x002F) - -/* CPU - CPU registers */ -#define CPU_CCP _SFR_MEM8(0x0034) -#define CPU_RAMPD _SFR_MEM8(0x0038) -#define CPU_RAMPX _SFR_MEM8(0x0039) -#define CPU_RAMPY _SFR_MEM8(0x003A) -#define CPU_RAMPZ _SFR_MEM8(0x003B) -#define CPU_EIND _SFR_MEM8(0x003C) -#define CPU_SPL _SFR_MEM8(0x003D) -#define CPU_SPH _SFR_MEM8(0x003E) -#define CPU_SREG _SFR_MEM8(0x003F) - -/* CLK - Clock System */ -#define CLK_CTRL _SFR_MEM8(0x0040) -#define CLK_PSCTRL _SFR_MEM8(0x0041) -#define CLK_LOCK _SFR_MEM8(0x0042) -#define CLK_RTCCTRL _SFR_MEM8(0x0043) -#define CLK_USBCTRL _SFR_MEM8(0x0044) - -/* SLEEP - Sleep Controller */ -#define SLEEP_CTRL _SFR_MEM8(0x0048) - -/* OSC - Oscillator */ -#define OSC_CTRL _SFR_MEM8(0x0050) -#define OSC_STATUS _SFR_MEM8(0x0051) -#define OSC_XOSCCTRL _SFR_MEM8(0x0052) -#define OSC_XOSCFAIL _SFR_MEM8(0x0053) -#define OSC_RC32KCAL _SFR_MEM8(0x0054) -#define OSC_PLLCTRL _SFR_MEM8(0x0055) -#define OSC_DFLLCTRL _SFR_MEM8(0x0056) - -/* DFLL - DFLL */ -#define DFLLRC32M_CTRL _SFR_MEM8(0x0060) -#define DFLLRC32M_CALA _SFR_MEM8(0x0062) -#define DFLLRC32M_CALB _SFR_MEM8(0x0063) -#define DFLLRC32M_COMP0 _SFR_MEM8(0x0064) -#define DFLLRC32M_COMP1 _SFR_MEM8(0x0065) -#define DFLLRC32M_COMP2 _SFR_MEM8(0x0066) - -/* DFLL - DFLL */ -#define DFLLRC2M_CTRL _SFR_MEM8(0x0068) -#define DFLLRC2M_CALA _SFR_MEM8(0x006A) -#define DFLLRC2M_CALB _SFR_MEM8(0x006B) -#define DFLLRC2M_COMP0 _SFR_MEM8(0x006C) -#define DFLLRC2M_COMP1 _SFR_MEM8(0x006D) -#define DFLLRC2M_COMP2 _SFR_MEM8(0x006E) - -/* PR - Power Reduction */ -#define PR_PRGEN _SFR_MEM8(0x0070) -#define PR_PRPA _SFR_MEM8(0x0071) -#define PR_PRPB _SFR_MEM8(0x0072) -#define PR_PRPC _SFR_MEM8(0x0073) -#define PR_PRPE _SFR_MEM8(0x0075) - -/* RST - Reset */ -#define RST_STATUS _SFR_MEM8(0x0078) -#define RST_CTRL _SFR_MEM8(0x0079) - -/* WDT - Watch-Dog Timer */ -#define WDT_CTRL _SFR_MEM8(0x0080) -#define WDT_WINCTRL _SFR_MEM8(0x0081) -#define WDT_STATUS _SFR_MEM8(0x0082) - -/* MCU - MCU Control */ -#define MCU_DEVID0 _SFR_MEM8(0x0090) -#define MCU_DEVID1 _SFR_MEM8(0x0091) -#define MCU_DEVID2 _SFR_MEM8(0x0092) -#define MCU_REVID _SFR_MEM8(0x0093) -#define MCU_JTAGUID _SFR_MEM8(0x0094) -#define MCU_MCUCR _SFR_MEM8(0x0096) -#define MCU_ANAINIT _SFR_MEM8(0x0097) -#define MCU_EVSYSLOCK _SFR_MEM8(0x0098) -#define MCU_AWEXLOCK _SFR_MEM8(0x0099) - -/* PMIC - Programmable Multi-level Interrupt Controller */ -#define PMIC_STATUS _SFR_MEM8(0x00A0) -#define PMIC_INTPRI _SFR_MEM8(0x00A1) -#define PMIC_CTRL _SFR_MEM8(0x00A2) - -/* PORTCFG - I/O port Configuration */ -#define PORTCFG_MPCMASK _SFR_MEM8(0x00B0) -#define PORTCFG_VPCTRLA _SFR_MEM8(0x00B2) -#define PORTCFG_VPCTRLB _SFR_MEM8(0x00B3) -#define PORTCFG_CLKEVOUT _SFR_MEM8(0x00B4) -#define PORTCFG_EVOUTSEL _SFR_MEM8(0x00B6) - -/* AES - AES Module */ -#define AES_CTRL _SFR_MEM8(0x00C0) -#define AES_STATUS _SFR_MEM8(0x00C1) -#define AES_STATE _SFR_MEM8(0x00C2) -#define AES_KEY _SFR_MEM8(0x00C3) -#define AES_INTCTRL _SFR_MEM8(0x00C4) - -/* CRC - Cyclic Redundancy Checker */ -#define CRC_CTRL _SFR_MEM8(0x00D0) -#define CRC_STATUS _SFR_MEM8(0x00D1) -#define CRC_DATAIN _SFR_MEM8(0x00D3) -#define CRC_CHECKSUM0 _SFR_MEM8(0x00D4) -#define CRC_CHECKSUM1 _SFR_MEM8(0x00D5) -#define CRC_CHECKSUM2 _SFR_MEM8(0x00D6) -#define CRC_CHECKSUM3 _SFR_MEM8(0x00D7) - -/* DMA - DMA Controller */ -#define DMA_CTRL _SFR_MEM8(0x0100) -#define DMA_INTFLAGS _SFR_MEM8(0x0103) -#define DMA_STATUS _SFR_MEM8(0x0104) -#define DMA_TEMP _SFR_MEM16(0x0106) -#define DMA_CH0_CTRLA _SFR_MEM8(0x0110) -#define DMA_CH0_CTRLB _SFR_MEM8(0x0111) -#define DMA_CH0_ADDRCTRL _SFR_MEM8(0x0112) -#define DMA_CH0_TRIGSRC _SFR_MEM8(0x0113) -#define DMA_CH0_TRFCNT _SFR_MEM16(0x0114) -#define DMA_CH0_REPCNT _SFR_MEM8(0x0116) -#define DMA_CH0_SRCADDR0 _SFR_MEM8(0x0118) -#define DMA_CH0_SRCADDR1 _SFR_MEM8(0x0119) -#define DMA_CH0_DESTADDR0 _SFR_MEM8(0x011C) -#define DMA_CH0_DESTADDR1 _SFR_MEM8(0x011D) -#define DMA_CH1_CTRLA _SFR_MEM8(0x0120) -#define DMA_CH1_CTRLB _SFR_MEM8(0x0121) -#define DMA_CH1_ADDRCTRL _SFR_MEM8(0x0122) -#define DMA_CH1_TRIGSRC _SFR_MEM8(0x0123) -#define DMA_CH1_TRFCNT _SFR_MEM16(0x0124) -#define DMA_CH1_REPCNT _SFR_MEM8(0x0126) -#define DMA_CH1_SRCADDR0 _SFR_MEM8(0x0128) -#define DMA_CH1_SRCADDR1 _SFR_MEM8(0x0129) -#define DMA_CH1_DESTADDR0 _SFR_MEM8(0x012C) -#define DMA_CH1_DESTADDR1 _SFR_MEM8(0x012D) - -/* EVSYS - Event System */ -#define EVSYS_CH0MUX _SFR_MEM8(0x0180) -#define EVSYS_CH1MUX _SFR_MEM8(0x0181) -#define EVSYS_CH2MUX _SFR_MEM8(0x0182) -#define EVSYS_CH3MUX _SFR_MEM8(0x0183) -#define EVSYS_CH0CTRL _SFR_MEM8(0x0188) -#define EVSYS_CH1CTRL _SFR_MEM8(0x0189) -#define EVSYS_CH2CTRL _SFR_MEM8(0x018A) -#define EVSYS_CH3CTRL _SFR_MEM8(0x018B) -#define EVSYS_STROBE _SFR_MEM8(0x0190) -#define EVSYS_DATA _SFR_MEM8(0x0191) - -/* NVM - Non-volatile Memory Controller */ -#define NVM_ADDR0 _SFR_MEM8(0x01C0) -#define NVM_ADDR1 _SFR_MEM8(0x01C1) -#define NVM_ADDR2 _SFR_MEM8(0x01C2) -#define NVM_DATA0 _SFR_MEM8(0x01C4) -#define NVM_DATA1 _SFR_MEM8(0x01C5) -#define NVM_DATA2 _SFR_MEM8(0x01C6) -#define NVM_CMD _SFR_MEM8(0x01CA) -#define NVM_CTRLA _SFR_MEM8(0x01CB) -#define NVM_CTRLB _SFR_MEM8(0x01CC) -#define NVM_INTCTRL _SFR_MEM8(0x01CD) -#define NVM_STATUS _SFR_MEM8(0x01CF) -#define NVM_LOCKBITS _SFR_MEM8(0x01D0) - -/* ADC - Analog-to-Digital Converter */ -#define ADCB_CTRLA _SFR_MEM8(0x0240) -#define ADCB_CTRLB _SFR_MEM8(0x0241) -#define ADCB_REFCTRL _SFR_MEM8(0x0242) -#define ADCB_EVCTRL _SFR_MEM8(0x0243) -#define ADCB_PRESCALER _SFR_MEM8(0x0244) -#define ADCB_INTFLAGS _SFR_MEM8(0x0246) -#define ADCB_TEMP _SFR_MEM8(0x0247) -#define ADCB_SAMPCTRL _SFR_MEM8(0x0248) -#define ADCB_CAL _SFR_MEM16(0x024C) -#define ADCB_CH0RES _SFR_MEM16(0x0250) -#define ADCB_CMP _SFR_MEM16(0x0258) -#define ADCB_CH0_CTRL _SFR_MEM8(0x0260) -#define ADCB_CH0_MUXCTRL _SFR_MEM8(0x0261) -#define ADCB_CH0_INTCTRL _SFR_MEM8(0x0262) -#define ADCB_CH0_INTFLAGS _SFR_MEM8(0x0263) -#define ADCB_CH0_RES _SFR_MEM16(0x0264) -#define ADCB_CH0_SCAN _SFR_MEM8(0x0266) - -/* AC - Analog Comparator */ -#define ACB_AC0CTRL _SFR_MEM8(0x0390) -#define ACB_AC1CTRL _SFR_MEM8(0x0391) -#define ACB_AC0MUXCTRL _SFR_MEM8(0x0392) -#define ACB_AC1MUXCTRL _SFR_MEM8(0x0393) -#define ACB_CTRLA _SFR_MEM8(0x0394) -#define ACB_CTRLB _SFR_MEM8(0x0395) -#define ACB_WINCTRL _SFR_MEM8(0x0396) -#define ACB_STATUS _SFR_MEM8(0x0397) -#define ACB_CURRCTRL _SFR_MEM8(0x0398) -#define ACB_CURRCALIB _SFR_MEM8(0x0399) - -/* RTC - Real-Time Counter */ -#define RTC_CTRL _SFR_MEM8(0x0400) -#define RTC_STATUS _SFR_MEM8(0x0401) -#define RTC_INTCTRL _SFR_MEM8(0x0402) -#define RTC_INTFLAGS _SFR_MEM8(0x0403) -#define RTC_TEMP _SFR_MEM8(0x0404) -#define RTC_CNT _SFR_MEM16(0x0408) -#define RTC_PER _SFR_MEM16(0x040A) -#define RTC_COMP _SFR_MEM16(0x040C) - -/* TWI - Two-Wire Interface */ -#define TWIC_CTRL _SFR_MEM8(0x0480) -#define TWIC_MASTER_CTRLA _SFR_MEM8(0x0481) -#define TWIC_MASTER_CTRLB _SFR_MEM8(0x0482) -#define TWIC_MASTER_CTRLC _SFR_MEM8(0x0483) -#define TWIC_MASTER_STATUS _SFR_MEM8(0x0484) -#define TWIC_MASTER_BAUD _SFR_MEM8(0x0485) -#define TWIC_MASTER_ADDR _SFR_MEM8(0x0486) -#define TWIC_MASTER_DATA _SFR_MEM8(0x0487) -#define TWIC_SLAVE_CTRLA _SFR_MEM8(0x0488) -#define TWIC_SLAVE_CTRLB _SFR_MEM8(0x0489) -#define TWIC_SLAVE_STATUS _SFR_MEM8(0x048A) -#define TWIC_SLAVE_ADDR _SFR_MEM8(0x048B) -#define TWIC_SLAVE_DATA _SFR_MEM8(0x048C) -#define TWIC_SLAVE_ADDRMASK _SFR_MEM8(0x048D) - -/* USB - Universal Serial Bus */ -#define USB_CTRLA _SFR_MEM8(0x04C0) -#define USB_CTRLB _SFR_MEM8(0x04C1) -#define USB_STATUS _SFR_MEM8(0x04C2) -#define USB_ADDR _SFR_MEM8(0x04C3) -#define USB_FIFOWP _SFR_MEM8(0x04C4) -#define USB_FIFORP _SFR_MEM8(0x04C5) -#define USB_EPPTR _SFR_MEM16(0x04C6) -#define USB_INTCTRLA _SFR_MEM8(0x04C8) -#define USB_INTCTRLB _SFR_MEM8(0x04C9) -#define USB_INTFLAGSACLR _SFR_MEM8(0x04CA) -#define USB_INTFLAGSASET _SFR_MEM8(0x04CB) -#define USB_INTFLAGSBCLR _SFR_MEM8(0x04CC) -#define USB_INTFLAGSBSET _SFR_MEM8(0x04CD) -#define USB_CAL0 _SFR_MEM8(0x04FA) -#define USB_CAL1 _SFR_MEM8(0x04FB) - -/* PORT - I/O Ports */ -#define PORTB_DIR _SFR_MEM8(0x0620) -#define PORTB_DIRSET _SFR_MEM8(0x0621) -#define PORTB_DIRCLR _SFR_MEM8(0x0622) -#define PORTB_DIRTGL _SFR_MEM8(0x0623) -#define PORTB_OUT _SFR_MEM8(0x0624) -#define PORTB_OUTSET _SFR_MEM8(0x0625) -#define PORTB_OUTCLR _SFR_MEM8(0x0626) -#define PORTB_OUTTGL _SFR_MEM8(0x0627) -#define PORTB_IN _SFR_MEM8(0x0628) -#define PORTB_INTCTRL _SFR_MEM8(0x0629) -#define PORTB_INT0MASK _SFR_MEM8(0x062A) -#define PORTB_INT1MASK _SFR_MEM8(0x062B) -#define PORTB_INTFLAGS _SFR_MEM8(0x062C) -#define PORTB_REMAP _SFR_MEM8(0x062E) -#define PORTB_PIN0CTRL _SFR_MEM8(0x0630) -#define PORTB_PIN1CTRL _SFR_MEM8(0x0631) -#define PORTB_PIN2CTRL _SFR_MEM8(0x0632) -#define PORTB_PIN3CTRL _SFR_MEM8(0x0633) -#define PORTB_PIN4CTRL _SFR_MEM8(0x0634) -#define PORTB_PIN5CTRL _SFR_MEM8(0x0635) -#define PORTB_PIN6CTRL _SFR_MEM8(0x0636) -#define PORTB_PIN7CTRL _SFR_MEM8(0x0637) - -/* PORT - I/O Ports */ -#define PORTC_DIR _SFR_MEM8(0x0640) -#define PORTC_DIRSET _SFR_MEM8(0x0641) -#define PORTC_DIRCLR _SFR_MEM8(0x0642) -#define PORTC_DIRTGL _SFR_MEM8(0x0643) -#define PORTC_OUT _SFR_MEM8(0x0644) -#define PORTC_OUTSET _SFR_MEM8(0x0645) -#define PORTC_OUTCLR _SFR_MEM8(0x0646) -#define PORTC_OUTTGL _SFR_MEM8(0x0647) -#define PORTC_IN _SFR_MEM8(0x0648) -#define PORTC_INTCTRL _SFR_MEM8(0x0649) -#define PORTC_INT0MASK _SFR_MEM8(0x064A) -#define PORTC_INT1MASK _SFR_MEM8(0x064B) -#define PORTC_INTFLAGS _SFR_MEM8(0x064C) -#define PORTC_REMAP _SFR_MEM8(0x064E) -#define PORTC_PIN0CTRL _SFR_MEM8(0x0650) -#define PORTC_PIN1CTRL _SFR_MEM8(0x0651) -#define PORTC_PIN2CTRL _SFR_MEM8(0x0652) -#define PORTC_PIN3CTRL _SFR_MEM8(0x0653) -#define PORTC_PIN4CTRL _SFR_MEM8(0x0654) -#define PORTC_PIN5CTRL _SFR_MEM8(0x0655) -#define PORTC_PIN6CTRL _SFR_MEM8(0x0656) -#define PORTC_PIN7CTRL _SFR_MEM8(0x0657) - -/* PORT - I/O Ports */ -#define PORTD_DIR _SFR_MEM8(0x0660) -#define PORTD_DIRSET _SFR_MEM8(0x0661) -#define PORTD_DIRCLR _SFR_MEM8(0x0662) -#define PORTD_DIRTGL _SFR_MEM8(0x0663) -#define PORTD_OUT _SFR_MEM8(0x0664) -#define PORTD_OUTSET _SFR_MEM8(0x0665) -#define PORTD_OUTCLR _SFR_MEM8(0x0666) -#define PORTD_OUTTGL _SFR_MEM8(0x0667) -#define PORTD_IN _SFR_MEM8(0x0668) -#define PORTD_INTCTRL _SFR_MEM8(0x0669) -#define PORTD_INT0MASK _SFR_MEM8(0x066A) -#define PORTD_INT1MASK _SFR_MEM8(0x066B) -#define PORTD_INTFLAGS _SFR_MEM8(0x066C) -#define PORTD_REMAP _SFR_MEM8(0x066E) -#define PORTD_PIN0CTRL _SFR_MEM8(0x0670) -#define PORTD_PIN1CTRL _SFR_MEM8(0x0671) -#define PORTD_PIN2CTRL _SFR_MEM8(0x0672) -#define PORTD_PIN3CTRL _SFR_MEM8(0x0673) -#define PORTD_PIN4CTRL _SFR_MEM8(0x0674) -#define PORTD_PIN5CTRL _SFR_MEM8(0x0675) -#define PORTD_PIN6CTRL _SFR_MEM8(0x0676) -#define PORTD_PIN7CTRL _SFR_MEM8(0x0677) - -/* PORT - I/O Ports */ -#define PORTG_DIR _SFR_MEM8(0x06C0) -#define PORTG_DIRSET _SFR_MEM8(0x06C1) -#define PORTG_DIRCLR _SFR_MEM8(0x06C2) -#define PORTG_DIRTGL _SFR_MEM8(0x06C3) -#define PORTG_OUT _SFR_MEM8(0x06C4) -#define PORTG_OUTSET _SFR_MEM8(0x06C5) -#define PORTG_OUTCLR _SFR_MEM8(0x06C6) -#define PORTG_OUTTGL _SFR_MEM8(0x06C7) -#define PORTG_IN _SFR_MEM8(0x06C8) -#define PORTG_INTCTRL _SFR_MEM8(0x06C9) -#define PORTG_INT0MASK _SFR_MEM8(0x06CA) -#define PORTG_INT1MASK _SFR_MEM8(0x06CB) -#define PORTG_INTFLAGS _SFR_MEM8(0x06CC) -#define PORTG_REMAP _SFR_MEM8(0x06CE) -#define PORTG_PIN0CTRL _SFR_MEM8(0x06D0) -#define PORTG_PIN1CTRL _SFR_MEM8(0x06D1) -#define PORTG_PIN2CTRL _SFR_MEM8(0x06D2) -#define PORTG_PIN3CTRL _SFR_MEM8(0x06D3) -#define PORTG_PIN4CTRL _SFR_MEM8(0x06D4) -#define PORTG_PIN5CTRL _SFR_MEM8(0x06D5) -#define PORTG_PIN6CTRL _SFR_MEM8(0x06D6) -#define PORTG_PIN7CTRL _SFR_MEM8(0x06D7) - -/* PORT - I/O Ports */ -#define PORTM_DIR _SFR_MEM8(0x0760) -#define PORTM_DIRSET _SFR_MEM8(0x0761) -#define PORTM_DIRCLR _SFR_MEM8(0x0762) -#define PORTM_DIRTGL _SFR_MEM8(0x0763) -#define PORTM_OUT _SFR_MEM8(0x0764) -#define PORTM_OUTSET _SFR_MEM8(0x0765) -#define PORTM_OUTCLR _SFR_MEM8(0x0766) -#define PORTM_OUTTGL _SFR_MEM8(0x0767) -#define PORTM_IN _SFR_MEM8(0x0768) -#define PORTM_INTCTRL _SFR_MEM8(0x0769) -#define PORTM_INT0MASK _SFR_MEM8(0x076A) -#define PORTM_INT1MASK _SFR_MEM8(0x076B) -#define PORTM_INTFLAGS _SFR_MEM8(0x076C) -#define PORTM_REMAP _SFR_MEM8(0x076E) -#define PORTM_PIN0CTRL _SFR_MEM8(0x0770) -#define PORTM_PIN1CTRL _SFR_MEM8(0x0771) -#define PORTM_PIN2CTRL _SFR_MEM8(0x0772) -#define PORTM_PIN3CTRL _SFR_MEM8(0x0773) -#define PORTM_PIN4CTRL _SFR_MEM8(0x0774) -#define PORTM_PIN5CTRL _SFR_MEM8(0x0775) -#define PORTM_PIN6CTRL _SFR_MEM8(0x0776) -#define PORTM_PIN7CTRL _SFR_MEM8(0x0777) - -/* PORT - I/O Ports */ -#define PORTR_DIR _SFR_MEM8(0x07E0) -#define PORTR_DIRSET _SFR_MEM8(0x07E1) -#define PORTR_DIRCLR _SFR_MEM8(0x07E2) -#define PORTR_DIRTGL _SFR_MEM8(0x07E3) -#define PORTR_OUT _SFR_MEM8(0x07E4) -#define PORTR_OUTSET _SFR_MEM8(0x07E5) -#define PORTR_OUTCLR _SFR_MEM8(0x07E6) -#define PORTR_OUTTGL _SFR_MEM8(0x07E7) -#define PORTR_IN _SFR_MEM8(0x07E8) -#define PORTR_INTCTRL _SFR_MEM8(0x07E9) -#define PORTR_INT0MASK _SFR_MEM8(0x07EA) -#define PORTR_INT1MASK _SFR_MEM8(0x07EB) -#define PORTR_INTFLAGS _SFR_MEM8(0x07EC) -#define PORTR_REMAP _SFR_MEM8(0x07EE) -#define PORTR_PIN0CTRL _SFR_MEM8(0x07F0) -#define PORTR_PIN1CTRL _SFR_MEM8(0x07F1) -#define PORTR_PIN2CTRL _SFR_MEM8(0x07F2) -#define PORTR_PIN3CTRL _SFR_MEM8(0x07F3) -#define PORTR_PIN4CTRL _SFR_MEM8(0x07F4) -#define PORTR_PIN5CTRL _SFR_MEM8(0x07F5) -#define PORTR_PIN6CTRL _SFR_MEM8(0x07F6) -#define PORTR_PIN7CTRL _SFR_MEM8(0x07F7) - -/* TC0 - 16-bit Timer/Counter 0 */ -#define TCC0_CTRLA _SFR_MEM8(0x0800) -#define TCC0_CTRLB _SFR_MEM8(0x0801) -#define TCC0_CTRLC _SFR_MEM8(0x0802) -#define TCC0_CTRLD _SFR_MEM8(0x0803) -#define TCC0_CTRLE _SFR_MEM8(0x0804) -#define TCC0_INTCTRLA _SFR_MEM8(0x0806) -#define TCC0_INTCTRLB _SFR_MEM8(0x0807) -#define TCC0_CTRLFCLR _SFR_MEM8(0x0808) -#define TCC0_CTRLFSET _SFR_MEM8(0x0809) -#define TCC0_CTRLGCLR _SFR_MEM8(0x080A) -#define TCC0_CTRLGSET _SFR_MEM8(0x080B) -#define TCC0_INTFLAGS _SFR_MEM8(0x080C) -#define TCC0_TEMP _SFR_MEM8(0x080F) -#define TCC0_CNT _SFR_MEM16(0x0820) -#define TCC0_PER _SFR_MEM16(0x0826) -#define TCC0_CCA _SFR_MEM16(0x0828) -#define TCC0_CCB _SFR_MEM16(0x082A) -#define TCC0_CCC _SFR_MEM16(0x082C) -#define TCC0_CCD _SFR_MEM16(0x082E) -#define TCC0_PERBUF _SFR_MEM16(0x0836) -#define TCC0_CCABUF _SFR_MEM16(0x0838) -#define TCC0_CCBBUF _SFR_MEM16(0x083A) -#define TCC0_CCCBUF _SFR_MEM16(0x083C) -#define TCC0_CCDBUF _SFR_MEM16(0x083E) - -/* TC1 - 16-bit Timer/Counter 1 */ -#define TCC1_CTRLA _SFR_MEM8(0x0840) -#define TCC1_CTRLB _SFR_MEM8(0x0841) -#define TCC1_CTRLC _SFR_MEM8(0x0842) -#define TCC1_CTRLD _SFR_MEM8(0x0843) -#define TCC1_CTRLE _SFR_MEM8(0x0844) -#define TCC1_INTCTRLA _SFR_MEM8(0x0846) -#define TCC1_INTCTRLB _SFR_MEM8(0x0847) -#define TCC1_CTRLFCLR _SFR_MEM8(0x0848) -#define TCC1_CTRLFSET _SFR_MEM8(0x0849) -#define TCC1_CTRLGCLR _SFR_MEM8(0x084A) -#define TCC1_CTRLGSET _SFR_MEM8(0x084B) -#define TCC1_INTFLAGS _SFR_MEM8(0x084C) -#define TCC1_TEMP _SFR_MEM8(0x084F) -#define TCC1_CNT _SFR_MEM16(0x0860) -#define TCC1_PER _SFR_MEM16(0x0866) -#define TCC1_CCA _SFR_MEM16(0x0868) -#define TCC1_CCB _SFR_MEM16(0x086A) -#define TCC1_PERBUF _SFR_MEM16(0x0876) -#define TCC1_CCABUF _SFR_MEM16(0x0878) -#define TCC1_CCBBUF _SFR_MEM16(0x087A) - -/* AWEX - Advanced Waveform Extension */ -#define AWEXC_CTRL _SFR_MEM8(0x0880) -#define AWEXC_FDEMASK _SFR_MEM8(0x0882) -#define AWEXC_FDCTRL _SFR_MEM8(0x0883) -#define AWEXC_STATUS _SFR_MEM8(0x0884) -#define AWEXC_STATUSSET _SFR_MEM8(0x0885) -#define AWEXC_DTBOTH _SFR_MEM8(0x0886) -#define AWEXC_DTBOTHBUF _SFR_MEM8(0x0887) -#define AWEXC_DTLS _SFR_MEM8(0x0888) -#define AWEXC_DTHS _SFR_MEM8(0x0889) -#define AWEXC_DTLSBUF _SFR_MEM8(0x088A) -#define AWEXC_DTHSBUF _SFR_MEM8(0x088B) -#define AWEXC_OUTOVEN _SFR_MEM8(0x088C) - -/* HIRES - High-Resolution Extension */ -#define HIRESC_CTRLA _SFR_MEM8(0x0890) - -/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ -#define USARTC0_DATA _SFR_MEM8(0x08A0) -#define USARTC0_STATUS _SFR_MEM8(0x08A1) -#define USARTC0_CTRLA _SFR_MEM8(0x08A3) -#define USARTC0_CTRLB _SFR_MEM8(0x08A4) -#define USARTC0_CTRLC _SFR_MEM8(0x08A5) -#define USARTC0_BAUDCTRLA _SFR_MEM8(0x08A6) -#define USARTC0_BAUDCTRLB _SFR_MEM8(0x08A7) - -/* SPI - Serial Peripheral Interface */ -#define SPIC_CTRL _SFR_MEM8(0x08C0) -#define SPIC_INTCTRL _SFR_MEM8(0x08C1) -#define SPIC_STATUS _SFR_MEM8(0x08C2) -#define SPIC_DATA _SFR_MEM8(0x08C3) - -/* IRCOM - IR Communication Module */ -#define IRCOM_CTRL _SFR_MEM8(0x08F8) -#define IRCOM_TXPLCTRL _SFR_MEM8(0x08F9) -#define IRCOM_RXPLCTRL _SFR_MEM8(0x08FA) - -/* LCD - LCD Controller */ -#define LCD_CTRLA _SFR_MEM8(0x0D00) -#define LCD_CTRLB _SFR_MEM8(0x0D01) -#define LCD_CTRLC _SFR_MEM8(0x0D02) -#define LCD_INTCTRL _SFR_MEM8(0x0D03) -#define LCD_INTFLAG _SFR_MEM8(0x0D04) -#define LCD_CTRLD _SFR_MEM8(0x0D05) -#define LCD_CTRLE _SFR_MEM8(0x0D06) -#define LCD_CTRLF _SFR_MEM8(0x0D07) -#define LCD_CTRLG _SFR_MEM8(0x0D08) -#define LCD_CTRLH _SFR_MEM8(0x0D09) -#define LCD_DATA0 _SFR_MEM8(0x0D10) -#define LCD_DATA1 _SFR_MEM8(0x0D11) -#define LCD_DATA2 _SFR_MEM8(0x0D12) -#define LCD_DATA3 _SFR_MEM8(0x0D13) -#define LCD_DATA4 _SFR_MEM8(0x0D14) -#define LCD_DATA5 _SFR_MEM8(0x0D15) -#define LCD_DATA6 _SFR_MEM8(0x0D16) -#define LCD_DATA7 _SFR_MEM8(0x0D17) -#define LCD_DATA8 _SFR_MEM8(0x0D18) -#define LCD_DATA9 _SFR_MEM8(0x0D19) -#define LCD_DATA10 _SFR_MEM8(0x0D1A) -#define LCD_DATA11 _SFR_MEM8(0x0D1B) -#define LCD_DATA12 _SFR_MEM8(0x0D1C) -#define LCD_DATA13 _SFR_MEM8(0x0D1D) -#define LCD_DATA14 _SFR_MEM8(0x0D1E) -#define LCD_DATA15 _SFR_MEM8(0x0D1F) -#define LCD_DATA16 _SFR_MEM8(0x0D20) -#define LCD_DATA17 _SFR_MEM8(0x0D21) -#define LCD_DATA18 _SFR_MEM8(0x0D22) -#define LCD_DATA19 _SFR_MEM8(0x0D23) - - - -/*================== Bitfield Definitions ================== */ - -/* VPORT - Virtual Ports */ -/* VPORT.INTFLAGS bit masks and bit positions */ -#define VPORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ -#define VPORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ - -#define VPORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ -#define VPORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ - -/* XOCD - On-Chip Debug System */ -/* OCD.OCDR0 bit masks and bit positions */ -#define OCD_OCDRD_gm 0xFF /* OCDR Dirty group mask. */ -#define OCD_OCDRD_gp 0 /* OCDR Dirty group position. */ -#define OCD_OCDRD0_bm (1<<0) /* OCDR Dirty bit 0 mask. */ -#define OCD_OCDRD0_bp 0 /* OCDR Dirty bit 0 position. */ -#define OCD_OCDRD1_bm (1<<1) /* OCDR Dirty bit 1 mask. */ -#define OCD_OCDRD1_bp 1 /* OCDR Dirty bit 1 position. */ -#define OCD_OCDRD2_bm (1<<2) /* OCDR Dirty bit 2 mask. */ -#define OCD_OCDRD2_bp 2 /* OCDR Dirty bit 2 position. */ -#define OCD_OCDRD3_bm (1<<3) /* OCDR Dirty bit 3 mask. */ -#define OCD_OCDRD3_bp 3 /* OCDR Dirty bit 3 position. */ -#define OCD_OCDRD4_bm (1<<4) /* OCDR Dirty bit 4 mask. */ -#define OCD_OCDRD4_bp 4 /* OCDR Dirty bit 4 position. */ -#define OCD_OCDRD5_bm (1<<5) /* OCDR Dirty bit 5 mask. */ -#define OCD_OCDRD5_bp 5 /* OCDR Dirty bit 5 position. */ -#define OCD_OCDRD6_bm (1<<6) /* OCDR Dirty bit 6 mask. */ -#define OCD_OCDRD6_bp 6 /* OCDR Dirty bit 6 position. */ -#define OCD_OCDRD7_bm (1<<7) /* OCDR Dirty bit 7 mask. */ -#define OCD_OCDRD7_bp 7 /* OCDR Dirty bit 7 position. */ - -/* OCD.OCDR1 bit masks and bit positions */ -/* OCD_OCDRD Predefined. */ -/* OCD_OCDRD Predefined. */ - -/* CPU - CPU */ -/* CPU.CCP bit masks and bit positions */ -#define CPU_CCP_gm 0xFF /* CCP signature group mask. */ -#define CPU_CCP_gp 0 /* CCP signature group position. */ -#define CPU_CCP0_bm (1<<0) /* CCP signature bit 0 mask. */ -#define CPU_CCP0_bp 0 /* CCP signature bit 0 position. */ -#define CPU_CCP1_bm (1<<1) /* CCP signature bit 1 mask. */ -#define CPU_CCP1_bp 1 /* CCP signature bit 1 position. */ -#define CPU_CCP2_bm (1<<2) /* CCP signature bit 2 mask. */ -#define CPU_CCP2_bp 2 /* CCP signature bit 2 position. */ -#define CPU_CCP3_bm (1<<3) /* CCP signature bit 3 mask. */ -#define CPU_CCP3_bp 3 /* CCP signature bit 3 position. */ -#define CPU_CCP4_bm (1<<4) /* CCP signature bit 4 mask. */ -#define CPU_CCP4_bp 4 /* CCP signature bit 4 position. */ -#define CPU_CCP5_bm (1<<5) /* CCP signature bit 5 mask. */ -#define CPU_CCP5_bp 5 /* CCP signature bit 5 position. */ -#define CPU_CCP6_bm (1<<6) /* CCP signature bit 6 mask. */ -#define CPU_CCP6_bp 6 /* CCP signature bit 6 position. */ -#define CPU_CCP7_bm (1<<7) /* CCP signature bit 7 mask. */ -#define CPU_CCP7_bp 7 /* CCP signature bit 7 position. */ - -/* CPU.SREG bit masks and bit positions */ -#define CPU_I_bm 0x80 /* Global Interrupt Enable Flag bit mask. */ -#define CPU_I_bp 7 /* Global Interrupt Enable Flag bit position. */ - -#define CPU_T_bm 0x40 /* Transfer Bit bit mask. */ -#define CPU_T_bp 6 /* Transfer Bit bit position. */ - -#define CPU_H_bm 0x20 /* Half Carry Flag bit mask. */ -#define CPU_H_bp 5 /* Half Carry Flag bit position. */ - -#define CPU_S_bm 0x10 /* N Exclusive Or V Flag bit mask. */ -#define CPU_S_bp 4 /* N Exclusive Or V Flag bit position. */ - -#define CPU_V_bm 0x08 /* Two's Complement Overflow Flag bit mask. */ -#define CPU_V_bp 3 /* Two's Complement Overflow Flag bit position. */ - -#define CPU_N_bm 0x04 /* Negative Flag bit mask. */ -#define CPU_N_bp 2 /* Negative Flag bit position. */ - -#define CPU_Z_bm 0x02 /* Zero Flag bit mask. */ -#define CPU_Z_bp 1 /* Zero Flag bit position. */ - -#define CPU_C_bm 0x01 /* Carry Flag bit mask. */ -#define CPU_C_bp 0 /* Carry Flag bit position. */ - -/* CLK - Clock System */ -/* CLK.CTRL bit masks and bit positions */ -#define CLK_SCLKSEL_gm 0x07 /* System Clock Selection group mask. */ -#define CLK_SCLKSEL_gp 0 /* System Clock Selection group position. */ -#define CLK_SCLKSEL0_bm (1<<0) /* System Clock Selection bit 0 mask. */ -#define CLK_SCLKSEL0_bp 0 /* System Clock Selection bit 0 position. */ -#define CLK_SCLKSEL1_bm (1<<1) /* System Clock Selection bit 1 mask. */ -#define CLK_SCLKSEL1_bp 1 /* System Clock Selection bit 1 position. */ -#define CLK_SCLKSEL2_bm (1<<2) /* System Clock Selection bit 2 mask. */ -#define CLK_SCLKSEL2_bp 2 /* System Clock Selection bit 2 position. */ - -/* CLK.PSCTRL bit masks and bit positions */ -#define CLK_PSADIV_gm 0x7C /* Prescaler A Division Factor group mask. */ -#define CLK_PSADIV_gp 2 /* Prescaler A Division Factor group position. */ -#define CLK_PSADIV0_bm (1<<2) /* Prescaler A Division Factor bit 0 mask. */ -#define CLK_PSADIV0_bp 2 /* Prescaler A Division Factor bit 0 position. */ -#define CLK_PSADIV1_bm (1<<3) /* Prescaler A Division Factor bit 1 mask. */ -#define CLK_PSADIV1_bp 3 /* Prescaler A Division Factor bit 1 position. */ -#define CLK_PSADIV2_bm (1<<4) /* Prescaler A Division Factor bit 2 mask. */ -#define CLK_PSADIV2_bp 4 /* Prescaler A Division Factor bit 2 position. */ -#define CLK_PSADIV3_bm (1<<5) /* Prescaler A Division Factor bit 3 mask. */ -#define CLK_PSADIV3_bp 5 /* Prescaler A Division Factor bit 3 position. */ -#define CLK_PSADIV4_bm (1<<6) /* Prescaler A Division Factor bit 4 mask. */ -#define CLK_PSADIV4_bp 6 /* Prescaler A Division Factor bit 4 position. */ - -#define CLK_PSBCDIV_gm 0x03 /* Prescaler B and C Division factor group mask. */ -#define CLK_PSBCDIV_gp 0 /* Prescaler B and C Division factor group position. */ -#define CLK_PSBCDIV0_bm (1<<0) /* Prescaler B and C Division factor bit 0 mask. */ -#define CLK_PSBCDIV0_bp 0 /* Prescaler B and C Division factor bit 0 position. */ -#define CLK_PSBCDIV1_bm (1<<1) /* Prescaler B and C Division factor bit 1 mask. */ -#define CLK_PSBCDIV1_bp 1 /* Prescaler B and C Division factor bit 1 position. */ - -/* CLK.LOCK bit masks and bit positions */ -#define CLK_LOCK_bm 0x01 /* Clock System Lock bit mask. */ -#define CLK_LOCK_bp 0 /* Clock System Lock bit position. */ - -/* CLK.RTCCTRL bit masks and bit positions */ -#define CLK_RTCSRC_gm 0x0E /* Clock Source group mask. */ -#define CLK_RTCSRC_gp 1 /* Clock Source group position. */ -#define CLK_RTCSRC0_bm (1<<1) /* Clock Source bit 0 mask. */ -#define CLK_RTCSRC0_bp 1 /* Clock Source bit 0 position. */ -#define CLK_RTCSRC1_bm (1<<2) /* Clock Source bit 1 mask. */ -#define CLK_RTCSRC1_bp 2 /* Clock Source bit 1 position. */ -#define CLK_RTCSRC2_bm (1<<3) /* Clock Source bit 2 mask. */ -#define CLK_RTCSRC2_bp 3 /* Clock Source bit 2 position. */ - -#define CLK_RTCEN_bm 0x01 /* Clock Source Enable bit mask. */ -#define CLK_RTCEN_bp 0 /* Clock Source Enable bit position. */ - -/* CLK.USBCTRL bit masks and bit positions */ -#define CLK_USBPSDIV_gm 0x38 /* Prescaler Division Factor group mask. */ -#define CLK_USBPSDIV_gp 3 /* Prescaler Division Factor group position. */ -#define CLK_USBPSDIV0_bm (1<<3) /* Prescaler Division Factor bit 0 mask. */ -#define CLK_USBPSDIV0_bp 3 /* Prescaler Division Factor bit 0 position. */ -#define CLK_USBPSDIV1_bm (1<<4) /* Prescaler Division Factor bit 1 mask. */ -#define CLK_USBPSDIV1_bp 4 /* Prescaler Division Factor bit 1 position. */ -#define CLK_USBPSDIV2_bm (1<<5) /* Prescaler Division Factor bit 2 mask. */ -#define CLK_USBPSDIV2_bp 5 /* Prescaler Division Factor bit 2 position. */ - -#define CLK_USBSRC_gm 0x06 /* Clock Source group mask. */ -#define CLK_USBSRC_gp 1 /* Clock Source group position. */ -#define CLK_USBSRC0_bm (1<<1) /* Clock Source bit 0 mask. */ -#define CLK_USBSRC0_bp 1 /* Clock Source bit 0 position. */ -#define CLK_USBSRC1_bm (1<<2) /* Clock Source bit 1 mask. */ -#define CLK_USBSRC1_bp 2 /* Clock Source bit 1 position. */ - -#define CLK_USBSEN_bm 0x01 /* Clock Source Enable bit mask. */ -#define CLK_USBSEN_bp 0 /* Clock Source Enable bit position. */ - -/* SLEEP - Sleep Controller */ -/* SLEEP.CTRL bit masks and bit positions */ -#define SLEEP_SMODE_gm 0x0E /* Sleep Mode group mask. */ -#define SLEEP_SMODE_gp 1 /* Sleep Mode group position. */ -#define SLEEP_SMODE0_bm (1<<1) /* Sleep Mode bit 0 mask. */ -#define SLEEP_SMODE0_bp 1 /* Sleep Mode bit 0 position. */ -#define SLEEP_SMODE1_bm (1<<2) /* Sleep Mode bit 1 mask. */ -#define SLEEP_SMODE1_bp 2 /* Sleep Mode bit 1 position. */ -#define SLEEP_SMODE2_bm (1<<3) /* Sleep Mode bit 2 mask. */ -#define SLEEP_SMODE2_bp 3 /* Sleep Mode bit 2 position. */ - -#define SLEEP_SEN_bm 0x01 /* Sleep Enable bit mask. */ -#define SLEEP_SEN_bp 0 /* Sleep Enable bit position. */ - -/* OSC - Oscillator */ -/* OSC.CTRL bit masks and bit positions */ -#define OSC_PLLEN_bm 0x10 /* PLL Enable bit mask. */ -#define OSC_PLLEN_bp 4 /* PLL Enable bit position. */ - -#define OSC_XOSCEN_bm 0x08 /* External Oscillator Enable bit mask. */ -#define OSC_XOSCEN_bp 3 /* External Oscillator Enable bit position. */ - -#define OSC_RC32KEN_bm 0x04 /* Internal 32.768 kHz RC Oscillator Enable bit mask. */ -#define OSC_RC32KEN_bp 2 /* Internal 32.768 kHz RC Oscillator Enable bit position. */ - -#define OSC_RC32MEN_bm 0x02 /* Internal 32 MHz RC Oscillator Enable bit mask. */ -#define OSC_RC32MEN_bp 1 /* Internal 32 MHz RC Oscillator Enable bit position. */ - -#define OSC_RC2MEN_bm 0x01 /* Internal 2 MHz RC Oscillator Enable bit mask. */ -#define OSC_RC2MEN_bp 0 /* Internal 2 MHz RC Oscillator Enable bit position. */ - -/* OSC.STATUS bit masks and bit positions */ -#define OSC_PLLRDY_bm 0x10 /* PLL Ready bit mask. */ -#define OSC_PLLRDY_bp 4 /* PLL Ready bit position. */ - -#define OSC_XOSCRDY_bm 0x08 /* External Oscillator Ready bit mask. */ -#define OSC_XOSCRDY_bp 3 /* External Oscillator Ready bit position. */ - -#define OSC_RC32KRDY_bm 0x04 /* Internal 32.768 kHz RC Oscillator Ready bit mask. */ -#define OSC_RC32KRDY_bp 2 /* Internal 32.768 kHz RC Oscillator Ready bit position. */ - -#define OSC_RC32MRDY_bm 0x02 /* Internal 32 MHz RC Oscillator Ready bit mask. */ -#define OSC_RC32MRDY_bp 1 /* Internal 32 MHz RC Oscillator Ready bit position. */ - -#define OSC_RC2MRDY_bm 0x01 /* Internal 2 MHz RC Oscillator Ready bit mask. */ -#define OSC_RC2MRDY_bp 0 /* Internal 2 MHz RC Oscillator Ready bit position. */ - -/* OSC.XOSCCTRL bit masks and bit positions */ -#define OSC_FRQRANGE_gm 0xC0 /* Frequency Range group mask. */ -#define OSC_FRQRANGE_gp 6 /* Frequency Range group position. */ -#define OSC_FRQRANGE0_bm (1<<6) /* Frequency Range bit 0 mask. */ -#define OSC_FRQRANGE0_bp 6 /* Frequency Range bit 0 position. */ -#define OSC_FRQRANGE1_bm (1<<7) /* Frequency Range bit 1 mask. */ -#define OSC_FRQRANGE1_bp 7 /* Frequency Range bit 1 position. */ - -#define OSC_X32KLPM_bm 0x20 /* 32.768 kHz XTAL OSC Low-power Mode bit mask. */ -#define OSC_X32KLPM_bp 5 /* 32.768 kHz XTAL OSC Low-power Mode bit position. */ - -#define OSC_XOSCPWR_bm 0x10 /* 16 MHz Crystal Oscillator High Power mode bit mask. */ -#define OSC_XOSCPWR_bp 4 /* 16 MHz Crystal Oscillator High Power mode bit position. */ - -#define OSC_XOSCSEL_gm 0x1F /* External Oscillator Selection and Startup Time group mask. */ -#define OSC_XOSCSEL_gp 0 /* External Oscillator Selection and Startup Time group position. */ -#define OSC_XOSCSEL0_bm (1<<0) /* External Oscillator Selection and Startup Time bit 0 mask. */ -#define OSC_XOSCSEL0_bp 0 /* External Oscillator Selection and Startup Time bit 0 position. */ -#define OSC_XOSCSEL1_bm (1<<1) /* External Oscillator Selection and Startup Time bit 1 mask. */ -#define OSC_XOSCSEL1_bp 1 /* External Oscillator Selection and Startup Time bit 1 position. */ -#define OSC_XOSCSEL2_bm (1<<2) /* External Oscillator Selection and Startup Time bit 2 mask. */ -#define OSC_XOSCSEL2_bp 2 /* External Oscillator Selection and Startup Time bit 2 position. */ -#define OSC_XOSCSEL3_bm (1<<3) /* External Oscillator Selection and Startup Time bit 3 mask. */ -#define OSC_XOSCSEL3_bp 3 /* External Oscillator Selection and Startup Time bit 3 position. */ -#define OSC_XOSCSEL4_bm (1<<4) /* External Oscillator Selection and Startup Time bit 4 mask. */ -#define OSC_XOSCSEL4_bp 4 /* External Oscillator Selection and Startup Time bit 4 position. */ - -/* OSC.XOSCFAIL bit masks and bit positions */ -#define OSC_PLLFDIF_bm 0x08 /* PLL Failure Detection Interrupt Flag bit mask. */ -#define OSC_PLLFDIF_bp 3 /* PLL Failure Detection Interrupt Flag bit position. */ - -#define OSC_PLLFDEN_bm 0x04 /* PLL Failure Detection Enable bit mask. */ -#define OSC_PLLFDEN_bp 2 /* PLL Failure Detection Enable bit position. */ - -#define OSC_XOSCFDIF_bm 0x02 /* XOSC Failure Detection Interrupt Flag bit mask. */ -#define OSC_XOSCFDIF_bp 1 /* XOSC Failure Detection Interrupt Flag bit position. */ - -#define OSC_XOSCFDEN_bm 0x01 /* XOSC Failure Detection Enable bit mask. */ -#define OSC_XOSCFDEN_bp 0 /* XOSC Failure Detection Enable bit position. */ - -/* OSC.PLLCTRL bit masks and bit positions */ -#define OSC_PLLSRC_gm 0xC0 /* Clock Source group mask. */ -#define OSC_PLLSRC_gp 6 /* Clock Source group position. */ -#define OSC_PLLSRC0_bm (1<<6) /* Clock Source bit 0 mask. */ -#define OSC_PLLSRC0_bp 6 /* Clock Source bit 0 position. */ -#define OSC_PLLSRC1_bm (1<<7) /* Clock Source bit 1 mask. */ -#define OSC_PLLSRC1_bp 7 /* Clock Source bit 1 position. */ - -#define OSC_PLLDIV_bm 0x20 /* Divide by 2 bit mask. */ -#define OSC_PLLDIV_bp 5 /* Divide by 2 bit position. */ - -#define OSC_PLLFAC_gm 0x1F /* Multiplication Factor group mask. */ -#define OSC_PLLFAC_gp 0 /* Multiplication Factor group position. */ -#define OSC_PLLFAC0_bm (1<<0) /* Multiplication Factor bit 0 mask. */ -#define OSC_PLLFAC0_bp 0 /* Multiplication Factor bit 0 position. */ -#define OSC_PLLFAC1_bm (1<<1) /* Multiplication Factor bit 1 mask. */ -#define OSC_PLLFAC1_bp 1 /* Multiplication Factor bit 1 position. */ -#define OSC_PLLFAC2_bm (1<<2) /* Multiplication Factor bit 2 mask. */ -#define OSC_PLLFAC2_bp 2 /* Multiplication Factor bit 2 position. */ -#define OSC_PLLFAC3_bm (1<<3) /* Multiplication Factor bit 3 mask. */ -#define OSC_PLLFAC3_bp 3 /* Multiplication Factor bit 3 position. */ -#define OSC_PLLFAC4_bm (1<<4) /* Multiplication Factor bit 4 mask. */ -#define OSC_PLLFAC4_bp 4 /* Multiplication Factor bit 4 position. */ - -/* OSC.DFLLCTRL bit masks and bit positions */ -#define OSC_RC32MCREF_gm 0x06 /* 32 MHz DFLL Calibration Reference group mask. */ -#define OSC_RC32MCREF_gp 1 /* 32 MHz DFLL Calibration Reference group position. */ -#define OSC_RC32MCREF0_bm (1<<1) /* 32 MHz DFLL Calibration Reference bit 0 mask. */ -#define OSC_RC32MCREF0_bp 1 /* 32 MHz DFLL Calibration Reference bit 0 position. */ -#define OSC_RC32MCREF1_bm (1<<2) /* 32 MHz DFLL Calibration Reference bit 1 mask. */ -#define OSC_RC32MCREF1_bp 2 /* 32 MHz DFLL Calibration Reference bit 1 position. */ - -#define OSC_RC2MCREF_bm 0x01 /* 2 MHz DFLL Calibration Reference bit mask. */ -#define OSC_RC2MCREF_bp 0 /* 2 MHz DFLL Calibration Reference bit position. */ - -/* DFLL - DFLL */ -/* DFLL.CTRL bit masks and bit positions */ -#define DFLL_ENABLE_bm 0x01 /* DFLL Enable bit mask. */ -#define DFLL_ENABLE_bp 0 /* DFLL Enable bit position. */ - -/* DFLL.CALA bit masks and bit positions */ -#define DFLL_CALL_gm 0x7F /* DFLL Calibration Value A group mask. */ -#define DFLL_CALL_gp 0 /* DFLL Calibration Value A group position. */ -#define DFLL_CALL0_bm (1<<0) /* DFLL Calibration Value A bit 0 mask. */ -#define DFLL_CALL0_bp 0 /* DFLL Calibration Value A bit 0 position. */ -#define DFLL_CALL1_bm (1<<1) /* DFLL Calibration Value A bit 1 mask. */ -#define DFLL_CALL1_bp 1 /* DFLL Calibration Value A bit 1 position. */ -#define DFLL_CALL2_bm (1<<2) /* DFLL Calibration Value A bit 2 mask. */ -#define DFLL_CALL2_bp 2 /* DFLL Calibration Value A bit 2 position. */ -#define DFLL_CALL3_bm (1<<3) /* DFLL Calibration Value A bit 3 mask. */ -#define DFLL_CALL3_bp 3 /* DFLL Calibration Value A bit 3 position. */ -#define DFLL_CALL4_bm (1<<4) /* DFLL Calibration Value A bit 4 mask. */ -#define DFLL_CALL4_bp 4 /* DFLL Calibration Value A bit 4 position. */ -#define DFLL_CALL5_bm (1<<5) /* DFLL Calibration Value A bit 5 mask. */ -#define DFLL_CALL5_bp 5 /* DFLL Calibration Value A bit 5 position. */ -#define DFLL_CALL6_bm (1<<6) /* DFLL Calibration Value A bit 6 mask. */ -#define DFLL_CALL6_bp 6 /* DFLL Calibration Value A bit 6 position. */ - -/* DFLL.CALB bit masks and bit positions */ -#define DFLL_CALH_gm 0x3F /* DFLL Calibration Value B group mask. */ -#define DFLL_CALH_gp 0 /* DFLL Calibration Value B group position. */ -#define DFLL_CALH0_bm (1<<0) /* DFLL Calibration Value B bit 0 mask. */ -#define DFLL_CALH0_bp 0 /* DFLL Calibration Value B bit 0 position. */ -#define DFLL_CALH1_bm (1<<1) /* DFLL Calibration Value B bit 1 mask. */ -#define DFLL_CALH1_bp 1 /* DFLL Calibration Value B bit 1 position. */ -#define DFLL_CALH2_bm (1<<2) /* DFLL Calibration Value B bit 2 mask. */ -#define DFLL_CALH2_bp 2 /* DFLL Calibration Value B bit 2 position. */ -#define DFLL_CALH3_bm (1<<3) /* DFLL Calibration Value B bit 3 mask. */ -#define DFLL_CALH3_bp 3 /* DFLL Calibration Value B bit 3 position. */ -#define DFLL_CALH4_bm (1<<4) /* DFLL Calibration Value B bit 4 mask. */ -#define DFLL_CALH4_bp 4 /* DFLL Calibration Value B bit 4 position. */ -#define DFLL_CALH5_bm (1<<5) /* DFLL Calibration Value B bit 5 mask. */ -#define DFLL_CALH5_bp 5 /* DFLL Calibration Value B bit 5 position. */ - -/* PR - Power Reduction */ -/* PR.PRGEN bit masks and bit positions */ -#define PR_LCD_bm 0x80 /* LCD Module bit mask. */ -#define PR_LCD_bp 7 /* LCD Module bit position. */ - -#define PR_USB_bm 0x40 /* USB bit mask. */ -#define PR_USB_bp 6 /* USB bit position. */ - -#define PR_AES_bm 0x10 /* AES bit mask. */ -#define PR_AES_bp 4 /* AES bit position. */ - -#define PR_RTC_bm 0x04 /* Real-time Counter bit mask. */ -#define PR_RTC_bp 2 /* Real-time Counter bit position. */ - -#define PR_EVSYS_bm 0x02 /* Event System bit mask. */ -#define PR_EVSYS_bp 1 /* Event System bit position. */ - -#define PR_DMA_bm 0x01 /* DMA-Controller bit mask. */ -#define PR_DMA_bp 0 /* DMA-Controller bit position. */ - -/* PR.PRPA bit masks and bit positions */ -#define PR_ADC_bm 0x02 /* Port A ADC bit mask. */ -#define PR_ADC_bp 1 /* Port A ADC bit position. */ - -#define PR_AC_bm 0x01 /* Port A Analog Comparator bit mask. */ -#define PR_AC_bp 0 /* Port A Analog Comparator bit position. */ - -/* PR.PRPB bit masks and bit positions */ -/* PR_ADC Predefined. */ -/* PR_ADC Predefined. */ - -/* PR_AC Predefined. */ -/* PR_AC Predefined. */ - -/* PR.PRPC bit masks and bit positions */ -#define PR_TWI_bm 0x40 /* Port C Two-wire Interface bit mask. */ -#define PR_TWI_bp 6 /* Port C Two-wire Interface bit position. */ - -#define PR_USART0_bm 0x10 /* Port C USART0 bit mask. */ -#define PR_USART0_bp 4 /* Port C USART0 bit position. */ - -#define PR_SPI_bm 0x08 /* Port C SPI bit mask. */ -#define PR_SPI_bp 3 /* Port C SPI bit position. */ - -#define PR_HIRES_bm 0x04 /* Port C AWEX bit mask. */ -#define PR_HIRES_bp 2 /* Port C AWEX bit position. */ - -#define PR_TC1_bm 0x02 /* Port C Timer/Counter1 bit mask. */ -#define PR_TC1_bp 1 /* Port C Timer/Counter1 bit position. */ - -#define PR_TC0_bm 0x01 /* Port C Timer/Counter0 bit mask. */ -#define PR_TC0_bp 0 /* Port C Timer/Counter0 bit position. */ - -/* PR.PRPE bit masks and bit positions */ -/* PR_USART0 Predefined. */ -/* PR_USART0 Predefined. */ - -/* PR_TC0 Predefined. */ -/* PR_TC0 Predefined. */ - -/* RST - Reset */ -/* RST.STATUS bit masks and bit positions */ -#define RST_SDRF_bm 0x40 /* Spike Detection Reset Flag bit mask. */ -#define RST_SDRF_bp 6 /* Spike Detection Reset Flag bit position. */ - -#define RST_SRF_bm 0x20 /* Software Reset Flag bit mask. */ -#define RST_SRF_bp 5 /* Software Reset Flag bit position. */ - -#define RST_PDIRF_bm 0x10 /* Programming and Debug Interface Interface Reset Flag bit mask. */ -#define RST_PDIRF_bp 4 /* Programming and Debug Interface Interface Reset Flag bit position. */ - -#define RST_WDRF_bm 0x08 /* Watchdog Reset Flag bit mask. */ -#define RST_WDRF_bp 3 /* Watchdog Reset Flag bit position. */ - -#define RST_BORF_bm 0x04 /* Brown-out Reset Flag bit mask. */ -#define RST_BORF_bp 2 /* Brown-out Reset Flag bit position. */ - -#define RST_EXTRF_bm 0x02 /* External Reset Flag bit mask. */ -#define RST_EXTRF_bp 1 /* External Reset Flag bit position. */ - -#define RST_PORF_bm 0x01 /* Power-on Reset Flag bit mask. */ -#define RST_PORF_bp 0 /* Power-on Reset Flag bit position. */ - -/* RST.CTRL bit masks and bit positions */ -#define RST_SWRST_bm 0x01 /* Software Reset bit mask. */ -#define RST_SWRST_bp 0 /* Software Reset bit position. */ - -/* WDT - Watch-Dog Timer */ -/* WDT.CTRL bit masks and bit positions */ -#define WDT_PER_gm 0x3C /* Period group mask. */ -#define WDT_PER_gp 2 /* Period group position. */ -#define WDT_PER0_bm (1<<2) /* Period bit 0 mask. */ -#define WDT_PER0_bp 2 /* Period bit 0 position. */ -#define WDT_PER1_bm (1<<3) /* Period bit 1 mask. */ -#define WDT_PER1_bp 3 /* Period bit 1 position. */ -#define WDT_PER2_bm (1<<4) /* Period bit 2 mask. */ -#define WDT_PER2_bp 4 /* Period bit 2 position. */ -#define WDT_PER3_bm (1<<5) /* Period bit 3 mask. */ -#define WDT_PER3_bp 5 /* Period bit 3 position. */ - -#define WDT_ENABLE_bm 0x02 /* Enable bit mask. */ -#define WDT_ENABLE_bp 1 /* Enable bit position. */ - -#define WDT_CEN_bm 0x01 /* Change Enable bit mask. */ -#define WDT_CEN_bp 0 /* Change Enable bit position. */ - -/* WDT.WINCTRL bit masks and bit positions */ -#define WDT_WPER_gm 0x3C /* Windowed Mode Period group mask. */ -#define WDT_WPER_gp 2 /* Windowed Mode Period group position. */ -#define WDT_WPER0_bm (1<<2) /* Windowed Mode Period bit 0 mask. */ -#define WDT_WPER0_bp 2 /* Windowed Mode Period bit 0 position. */ -#define WDT_WPER1_bm (1<<3) /* Windowed Mode Period bit 1 mask. */ -#define WDT_WPER1_bp 3 /* Windowed Mode Period bit 1 position. */ -#define WDT_WPER2_bm (1<<4) /* Windowed Mode Period bit 2 mask. */ -#define WDT_WPER2_bp 4 /* Windowed Mode Period bit 2 position. */ -#define WDT_WPER3_bm (1<<5) /* Windowed Mode Period bit 3 mask. */ -#define WDT_WPER3_bp 5 /* Windowed Mode Period bit 3 position. */ - -#define WDT_WEN_bm 0x02 /* Windowed Mode Enable bit mask. */ -#define WDT_WEN_bp 1 /* Windowed Mode Enable bit position. */ - -#define WDT_WCEN_bm 0x01 /* Windowed Mode Change Enable bit mask. */ -#define WDT_WCEN_bp 0 /* Windowed Mode Change Enable bit position. */ - -/* WDT.STATUS bit masks and bit positions */ -#define WDT_SYNCBUSY_bm 0x01 /* Syncronization busy bit mask. */ -#define WDT_SYNCBUSY_bp 0 /* Syncronization busy bit position. */ - -/* MCU - MCU Control */ -/* MCU.MCUCR bit masks and bit positions */ -#define MCU_JTAGD_bm 0x01 /* JTAG Disable bit mask. */ -#define MCU_JTAGD_bp 0 /* JTAG Disable bit position. */ - -/* MCU.ANAINIT bit masks and bit positions */ -#define MCU_STARTUPDLYB_gm 0x0C /* Analog startup delay Port B group mask. */ -#define MCU_STARTUPDLYB_gp 2 /* Analog startup delay Port B group position. */ -#define MCU_STARTUPDLYB0_bm (1<<2) /* Analog startup delay Port B bit 0 mask. */ -#define MCU_STARTUPDLYB0_bp 2 /* Analog startup delay Port B bit 0 position. */ -#define MCU_STARTUPDLYB1_bm (1<<3) /* Analog startup delay Port B bit 1 mask. */ -#define MCU_STARTUPDLYB1_bp 3 /* Analog startup delay Port B bit 1 position. */ - -#define MCU_STARTUPDLYA_gm 0x03 /* Analog startup delay Port A group mask. */ -#define MCU_STARTUPDLYA_gp 0 /* Analog startup delay Port A group position. */ -#define MCU_STARTUPDLYA0_bm (1<<0) /* Analog startup delay Port A bit 0 mask. */ -#define MCU_STARTUPDLYA0_bp 0 /* Analog startup delay Port A bit 0 position. */ -#define MCU_STARTUPDLYA1_bm (1<<1) /* Analog startup delay Port A bit 1 mask. */ -#define MCU_STARTUPDLYA1_bp 1 /* Analog startup delay Port A bit 1 position. */ - -/* MCU.EVSYSLOCK bit masks and bit positions */ -#define MCU_EVSYS1LOCK_bm 0x10 /* Event Channel 4-7 Lock bit mask. */ -#define MCU_EVSYS1LOCK_bp 4 /* Event Channel 4-7 Lock bit position. */ - -#define MCU_EVSYS0LOCK_bm 0x01 /* Event Channel 0-3 Lock bit mask. */ -#define MCU_EVSYS0LOCK_bp 0 /* Event Channel 0-3 Lock bit position. */ - -/* MCU.AWEXLOCK bit masks and bit positions */ -#define MCU_AWEXCLOCK_bm 0x01 /* AWeX on T/C C0 Lock bit mask. */ -#define MCU_AWEXCLOCK_bp 0 /* AWeX on T/C C0 Lock bit position. */ - -/* PMIC - Programmable Multi-level Interrupt Controller */ -/* PMIC.STATUS bit masks and bit positions */ -#define PMIC_NMIEX_bm 0x80 /* Non-maskable Interrupt Executing bit mask. */ -#define PMIC_NMIEX_bp 7 /* Non-maskable Interrupt Executing bit position. */ - -#define PMIC_HILVLEX_bm 0x04 /* High Level Interrupt Executing bit mask. */ -#define PMIC_HILVLEX_bp 2 /* High Level Interrupt Executing bit position. */ - -#define PMIC_MEDLVLEX_bm 0x02 /* Medium Level Interrupt Executing bit mask. */ -#define PMIC_MEDLVLEX_bp 1 /* Medium Level Interrupt Executing bit position. */ - -#define PMIC_LOLVLEX_bm 0x01 /* Low Level Interrupt Executing bit mask. */ -#define PMIC_LOLVLEX_bp 0 /* Low Level Interrupt Executing bit position. */ - -/* PMIC.INTPRI bit masks and bit positions */ -#define PMIC_INTPRI_gm 0xFF /* Interrupt Priority group mask. */ -#define PMIC_INTPRI_gp 0 /* Interrupt Priority group position. */ -#define PMIC_INTPRI0_bm (1<<0) /* Interrupt Priority bit 0 mask. */ -#define PMIC_INTPRI0_bp 0 /* Interrupt Priority bit 0 position. */ -#define PMIC_INTPRI1_bm (1<<1) /* Interrupt Priority bit 1 mask. */ -#define PMIC_INTPRI1_bp 1 /* Interrupt Priority bit 1 position. */ -#define PMIC_INTPRI2_bm (1<<2) /* Interrupt Priority bit 2 mask. */ -#define PMIC_INTPRI2_bp 2 /* Interrupt Priority bit 2 position. */ -#define PMIC_INTPRI3_bm (1<<3) /* Interrupt Priority bit 3 mask. */ -#define PMIC_INTPRI3_bp 3 /* Interrupt Priority bit 3 position. */ -#define PMIC_INTPRI4_bm (1<<4) /* Interrupt Priority bit 4 mask. */ -#define PMIC_INTPRI4_bp 4 /* Interrupt Priority bit 4 position. */ -#define PMIC_INTPRI5_bm (1<<5) /* Interrupt Priority bit 5 mask. */ -#define PMIC_INTPRI5_bp 5 /* Interrupt Priority bit 5 position. */ -#define PMIC_INTPRI6_bm (1<<6) /* Interrupt Priority bit 6 mask. */ -#define PMIC_INTPRI6_bp 6 /* Interrupt Priority bit 6 position. */ -#define PMIC_INTPRI7_bm (1<<7) /* Interrupt Priority bit 7 mask. */ -#define PMIC_INTPRI7_bp 7 /* Interrupt Priority bit 7 position. */ - -/* PMIC.CTRL bit masks and bit positions */ -#define PMIC_RREN_bm 0x80 /* Round-Robin Priority Enable bit mask. */ -#define PMIC_RREN_bp 7 /* Round-Robin Priority Enable bit position. */ - -#define PMIC_IVSEL_bm 0x40 /* Interrupt Vector Select bit mask. */ -#define PMIC_IVSEL_bp 6 /* Interrupt Vector Select bit position. */ - -#define PMIC_HILVLEN_bm 0x04 /* High Level Enable bit mask. */ -#define PMIC_HILVLEN_bp 2 /* High Level Enable bit position. */ - -#define PMIC_MEDLVLEN_bm 0x02 /* Medium Level Enable bit mask. */ -#define PMIC_MEDLVLEN_bp 1 /* Medium Level Enable bit position. */ - -#define PMIC_LOLVLEN_bm 0x01 /* Low Level Enable bit mask. */ -#define PMIC_LOLVLEN_bp 0 /* Low Level Enable bit position. */ - -/* PORTCFG - Port Configuration */ -/* PORTCFG.VPCTRLA bit masks and bit positions */ -#define PORTCFG_VP1MAP_gm 0xF0 /* Virtual Port 1 Mapping group mask. */ -#define PORTCFG_VP1MAP_gp 4 /* Virtual Port 1 Mapping group position. */ -#define PORTCFG_VP1MAP0_bm (1<<4) /* Virtual Port 1 Mapping bit 0 mask. */ -#define PORTCFG_VP1MAP0_bp 4 /* Virtual Port 1 Mapping bit 0 position. */ -#define PORTCFG_VP1MAP1_bm (1<<5) /* Virtual Port 1 Mapping bit 1 mask. */ -#define PORTCFG_VP1MAP1_bp 5 /* Virtual Port 1 Mapping bit 1 position. */ -#define PORTCFG_VP1MAP2_bm (1<<6) /* Virtual Port 1 Mapping bit 2 mask. */ -#define PORTCFG_VP1MAP2_bp 6 /* Virtual Port 1 Mapping bit 2 position. */ -#define PORTCFG_VP1MAP3_bm (1<<7) /* Virtual Port 1 Mapping bit 3 mask. */ -#define PORTCFG_VP1MAP3_bp 7 /* Virtual Port 1 Mapping bit 3 position. */ - -#define PORTCFG_VP0MAP_gm 0x0F /* Virtual Port 0 Mapping group mask. */ -#define PORTCFG_VP0MAP_gp 0 /* Virtual Port 0 Mapping group position. */ -#define PORTCFG_VP0MAP0_bm (1<<0) /* Virtual Port 0 Mapping bit 0 mask. */ -#define PORTCFG_VP0MAP0_bp 0 /* Virtual Port 0 Mapping bit 0 position. */ -#define PORTCFG_VP0MAP1_bm (1<<1) /* Virtual Port 0 Mapping bit 1 mask. */ -#define PORTCFG_VP0MAP1_bp 1 /* Virtual Port 0 Mapping bit 1 position. */ -#define PORTCFG_VP0MAP2_bm (1<<2) /* Virtual Port 0 Mapping bit 2 mask. */ -#define PORTCFG_VP0MAP2_bp 2 /* Virtual Port 0 Mapping bit 2 position. */ -#define PORTCFG_VP0MAP3_bm (1<<3) /* Virtual Port 0 Mapping bit 3 mask. */ -#define PORTCFG_VP0MAP3_bp 3 /* Virtual Port 0 Mapping bit 3 position. */ - -/* PORTCFG.VPCTRLB bit masks and bit positions */ -#define PORTCFG_VP3MAP_gm 0xF0 /* Virtual Port 3 Mapping group mask. */ -#define PORTCFG_VP3MAP_gp 4 /* Virtual Port 3 Mapping group position. */ -#define PORTCFG_VP3MAP0_bm (1<<4) /* Virtual Port 3 Mapping bit 0 mask. */ -#define PORTCFG_VP3MAP0_bp 4 /* Virtual Port 3 Mapping bit 0 position. */ -#define PORTCFG_VP3MAP1_bm (1<<5) /* Virtual Port 3 Mapping bit 1 mask. */ -#define PORTCFG_VP3MAP1_bp 5 /* Virtual Port 3 Mapping bit 1 position. */ -#define PORTCFG_VP3MAP2_bm (1<<6) /* Virtual Port 3 Mapping bit 2 mask. */ -#define PORTCFG_VP3MAP2_bp 6 /* Virtual Port 3 Mapping bit 2 position. */ -#define PORTCFG_VP3MAP3_bm (1<<7) /* Virtual Port 3 Mapping bit 3 mask. */ -#define PORTCFG_VP3MAP3_bp 7 /* Virtual Port 3 Mapping bit 3 position. */ - -#define PORTCFG_VP2MAP_gm 0x0F /* Virtual Port 2 Mapping group mask. */ -#define PORTCFG_VP2MAP_gp 0 /* Virtual Port 2 Mapping group position. */ -#define PORTCFG_VP2MAP0_bm (1<<0) /* Virtual Port 2 Mapping bit 0 mask. */ -#define PORTCFG_VP2MAP0_bp 0 /* Virtual Port 2 Mapping bit 0 position. */ -#define PORTCFG_VP2MAP1_bm (1<<1) /* Virtual Port 2 Mapping bit 1 mask. */ -#define PORTCFG_VP2MAP1_bp 1 /* Virtual Port 2 Mapping bit 1 position. */ -#define PORTCFG_VP2MAP2_bm (1<<2) /* Virtual Port 2 Mapping bit 2 mask. */ -#define PORTCFG_VP2MAP2_bp 2 /* Virtual Port 2 Mapping bit 2 position. */ -#define PORTCFG_VP2MAP3_bm (1<<3) /* Virtual Port 2 Mapping bit 3 mask. */ -#define PORTCFG_VP2MAP3_bp 3 /* Virtual Port 2 Mapping bit 3 position. */ - -/* PORTCFG.CLKEVOUT bit masks and bit positions */ -#define PORTCFG_CLKOUT_gm 0x03 /* Peripheral Clock Output Port group mask. */ -#define PORTCFG_CLKOUT_gp 0 /* Peripheral Clock Output Port group position. */ -#define PORTCFG_CLKOUT0_bm (1<<0) /* Peripheral Clock Output Port bit 0 mask. */ -#define PORTCFG_CLKOUT0_bp 0 /* Peripheral Clock Output Port bit 0 position. */ -#define PORTCFG_CLKOUT1_bm (1<<1) /* Peripheral Clock Output Port bit 1 mask. */ -#define PORTCFG_CLKOUT1_bp 1 /* Peripheral Clock Output Port bit 1 position. */ - -#define PORTCFG_CLKOUTSEL_gm 0x0C /* Peripheral Clock Output Select group mask. */ -#define PORTCFG_CLKOUTSEL_gp 2 /* Peripheral Clock Output Select group position. */ -#define PORTCFG_CLKOUTSEL0_bm (1<<2) /* Peripheral Clock Output Select bit 0 mask. */ -#define PORTCFG_CLKOUTSEL0_bp 2 /* Peripheral Clock Output Select bit 0 position. */ -#define PORTCFG_CLKOUTSEL1_bm (1<<3) /* Peripheral Clock Output Select bit 1 mask. */ -#define PORTCFG_CLKOUTSEL1_bp 3 /* Peripheral Clock Output Select bit 1 position. */ - -#define PORTCFG_EVOUT_gm 0x30 /* Event Output Port group mask. */ -#define PORTCFG_EVOUT_gp 4 /* Event Output Port group position. */ -#define PORTCFG_EVOUT0_bm (1<<4) /* Event Output Port bit 0 mask. */ -#define PORTCFG_EVOUT0_bp 4 /* Event Output Port bit 0 position. */ -#define PORTCFG_EVOUT1_bm (1<<5) /* Event Output Port bit 1 mask. */ -#define PORTCFG_EVOUT1_bp 5 /* Event Output Port bit 1 position. */ - -#define PORTCFG_RTCOUT_bm 0x40 /* RTC Clock Output bit mask. */ -#define PORTCFG_RTCOUT_bp 6 /* RTC Clock Output bit position. */ - -#define PORTCFG_CLKEVPIN_bm 0x80 /* Peripheral Clock and Event Output pin Select bit mask. */ -#define PORTCFG_CLKEVPIN_bp 7 /* Peripheral Clock and Event Output pin Select bit position. */ - -/* PORTCFG.EVOUTSEL bit masks and bit positions */ -#define PORTCFG_EVOUTSEL_bm 0x04 /* Event Output Select bit mask. */ -#define PORTCFG_EVOUTSEL_bp 2 /* Event Output Select bit position. */ - -/* AES - AES Module */ -/* AES.CTRL bit masks and bit positions */ -#define AES_START_bm 0x80 /* Start/Run bit mask. */ -#define AES_START_bp 7 /* Start/Run bit position. */ - -#define AES_AUTO_bm 0x40 /* Auto Start Trigger bit mask. */ -#define AES_AUTO_bp 6 /* Auto Start Trigger bit position. */ - -#define AES_RESET_bm 0x20 /* AES Software Reset bit mask. */ -#define AES_RESET_bp 5 /* AES Software Reset bit position. */ - -#define AES_DECRYPT_bm 0x10 /* Decryption / Direction bit mask. */ -#define AES_DECRYPT_bp 4 /* Decryption / Direction bit position. */ - -#define AES_XOR_bm 0x04 /* State XOR Load Enable bit mask. */ -#define AES_XOR_bp 2 /* State XOR Load Enable bit position. */ - -/* AES.STATUS bit masks and bit positions */ -#define AES_ERROR_bm 0x80 /* AES Error bit mask. */ -#define AES_ERROR_bp 7 /* AES Error bit position. */ - -#define AES_SRIF_bm 0x01 /* State Ready Interrupt Flag bit mask. */ -#define AES_SRIF_bp 0 /* State Ready Interrupt Flag bit position. */ - -/* AES.INTCTRL bit masks and bit positions */ -#define AES_INTLVL_gm 0x03 /* Interrupt level group mask. */ -#define AES_INTLVL_gp 0 /* Interrupt level group position. */ -#define AES_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */ -#define AES_INTLVL0_bp 0 /* Interrupt level bit 0 position. */ -#define AES_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */ -#define AES_INTLVL1_bp 1 /* Interrupt level bit 1 position. */ - -/* CRC - Cyclic Redundancy Checker */ -/* CRC.CTRL bit masks and bit positions */ -#define CRC_RESET_gm 0xC0 /* Reset group mask. */ -#define CRC_RESET_gp 6 /* Reset group position. */ -#define CRC_RESET0_bm (1<<6) /* Reset bit 0 mask. */ -#define CRC_RESET0_bp 6 /* Reset bit 0 position. */ -#define CRC_RESET1_bm (1<<7) /* Reset bit 1 mask. */ -#define CRC_RESET1_bp 7 /* Reset bit 1 position. */ - -#define CRC_CRC32_bm 0x20 /* CRC Mode bit mask. */ -#define CRC_CRC32_bp 5 /* CRC Mode bit position. */ - -#define CRC_SOURCE_gm 0x0F /* Input Source group mask. */ -#define CRC_SOURCE_gp 0 /* Input Source group position. */ -#define CRC_SOURCE0_bm (1<<0) /* Input Source bit 0 mask. */ -#define CRC_SOURCE0_bp 0 /* Input Source bit 0 position. */ -#define CRC_SOURCE1_bm (1<<1) /* Input Source bit 1 mask. */ -#define CRC_SOURCE1_bp 1 /* Input Source bit 1 position. */ -#define CRC_SOURCE2_bm (1<<2) /* Input Source bit 2 mask. */ -#define CRC_SOURCE2_bp 2 /* Input Source bit 2 position. */ -#define CRC_SOURCE3_bm (1<<3) /* Input Source bit 3 mask. */ -#define CRC_SOURCE3_bp 3 /* Input Source bit 3 position. */ - -/* CRC.STATUS bit masks and bit positions */ -#define CRC_ZERO_bm 0x02 /* Zero detection bit mask. */ -#define CRC_ZERO_bp 1 /* Zero detection bit position. */ - -#define CRC_BUSY_bm 0x01 /* Busy bit mask. */ -#define CRC_BUSY_bp 0 /* Busy bit position. */ - -/* DMA - DMA Controller */ -/* DMA_CH.CTRLA bit masks and bit positions */ -#define DMA_CH_CHEN_bm 0x80 /* Channel Enable bit mask. */ -#define DMA_CH_CHEN_bp 7 /* Channel Enable bit position. */ - -#define DMA_CH_CHRST_bm 0x40 /* Channel Software Reset bit mask. */ -#define DMA_CH_CHRST_bp 6 /* Channel Software Reset bit position. */ - -#define DMA_CH_REPEAT_bm 0x20 /* Channel Repeat Mode bit mask. */ -#define DMA_CH_REPEAT_bp 5 /* Channel Repeat Mode bit position. */ - -#define DMA_CH_TRFREQ_bm 0x10 /* Channel Transfer Request bit mask. */ -#define DMA_CH_TRFREQ_bp 4 /* Channel Transfer Request bit position. */ - -#define DMA_CH_SINGLE_bm 0x04 /* Channel Single Shot Data Transfer bit mask. */ -#define DMA_CH_SINGLE_bp 2 /* Channel Single Shot Data Transfer bit position. */ - -#define DMA_CH_BURSTLEN_gm 0x03 /* Channel Transfer Mode group mask. */ -#define DMA_CH_BURSTLEN_gp 0 /* Channel Transfer Mode group position. */ -#define DMA_CH_BURSTLEN0_bm (1<<0) /* Channel Transfer Mode bit 0 mask. */ -#define DMA_CH_BURSTLEN0_bp 0 /* Channel Transfer Mode bit 0 position. */ -#define DMA_CH_BURSTLEN1_bm (1<<1) /* Channel Transfer Mode bit 1 mask. */ -#define DMA_CH_BURSTLEN1_bp 1 /* Channel Transfer Mode bit 1 position. */ - -/* DMA_CH.CTRLB bit masks and bit positions */ -#define DMA_CH_CHBUSY_bm 0x80 /* Block Transfer Busy bit mask. */ -#define DMA_CH_CHBUSY_bp 7 /* Block Transfer Busy bit position. */ - -#define DMA_CH_CHPEND_bm 0x40 /* Block Transfer Pending bit mask. */ -#define DMA_CH_CHPEND_bp 6 /* Block Transfer Pending bit position. */ - -#define DMA_CH_ERRIF_bm 0x20 /* Block Transfer Error Interrupt Flag bit mask. */ -#define DMA_CH_ERRIF_bp 5 /* Block Transfer Error Interrupt Flag bit position. */ - -#define DMA_CH_TRNIF_bm 0x10 /* Transaction Complete Interrup Flag bit mask. */ -#define DMA_CH_TRNIF_bp 4 /* Transaction Complete Interrup Flag bit position. */ - -#define DMA_CH_ERRINTLVL_gm 0x0C /* Transfer Error Interrupt Level group mask. */ -#define DMA_CH_ERRINTLVL_gp 2 /* Transfer Error Interrupt Level group position. */ -#define DMA_CH_ERRINTLVL0_bm (1<<2) /* Transfer Error Interrupt Level bit 0 mask. */ -#define DMA_CH_ERRINTLVL0_bp 2 /* Transfer Error Interrupt Level bit 0 position. */ -#define DMA_CH_ERRINTLVL1_bm (1<<3) /* Transfer Error Interrupt Level bit 1 mask. */ -#define DMA_CH_ERRINTLVL1_bp 3 /* Transfer Error Interrupt Level bit 1 position. */ - -#define DMA_CH_TRNINTLVL_gm 0x03 /* Transaction Complete Interrupt Level group mask. */ -#define DMA_CH_TRNINTLVL_gp 0 /* Transaction Complete Interrupt Level group position. */ -#define DMA_CH_TRNINTLVL0_bm (1<<0) /* Transaction Complete Interrupt Level bit 0 mask. */ -#define DMA_CH_TRNINTLVL0_bp 0 /* Transaction Complete Interrupt Level bit 0 position. */ -#define DMA_CH_TRNINTLVL1_bm (1<<1) /* Transaction Complete Interrupt Level bit 1 mask. */ -#define DMA_CH_TRNINTLVL1_bp 1 /* Transaction Complete Interrupt Level bit 1 position. */ - -/* DMA_CH.ADDRCTRL bit masks and bit positions */ -#define DMA_CH_SRCRELOAD_gm 0xC0 /* Channel Source Address Reload group mask. */ -#define DMA_CH_SRCRELOAD_gp 6 /* Channel Source Address Reload group position. */ -#define DMA_CH_SRCRELOAD0_bm (1<<6) /* Channel Source Address Reload bit 0 mask. */ -#define DMA_CH_SRCRELOAD0_bp 6 /* Channel Source Address Reload bit 0 position. */ -#define DMA_CH_SRCRELOAD1_bm (1<<7) /* Channel Source Address Reload bit 1 mask. */ -#define DMA_CH_SRCRELOAD1_bp 7 /* Channel Source Address Reload bit 1 position. */ - -#define DMA_CH_SRCDIR_gm 0x30 /* Channel Source Address Mode group mask. */ -#define DMA_CH_SRCDIR_gp 4 /* Channel Source Address Mode group position. */ -#define DMA_CH_SRCDIR0_bm (1<<4) /* Channel Source Address Mode bit 0 mask. */ -#define DMA_CH_SRCDIR0_bp 4 /* Channel Source Address Mode bit 0 position. */ -#define DMA_CH_SRCDIR1_bm (1<<5) /* Channel Source Address Mode bit 1 mask. */ -#define DMA_CH_SRCDIR1_bp 5 /* Channel Source Address Mode bit 1 position. */ - -#define DMA_CH_DESTRELOAD_gm 0x0C /* Channel Destination Address Reload group mask. */ -#define DMA_CH_DESTRELOAD_gp 2 /* Channel Destination Address Reload group position. */ -#define DMA_CH_DESTRELOAD0_bm (1<<2) /* Channel Destination Address Reload bit 0 mask. */ -#define DMA_CH_DESTRELOAD0_bp 2 /* Channel Destination Address Reload bit 0 position. */ -#define DMA_CH_DESTRELOAD1_bm (1<<3) /* Channel Destination Address Reload bit 1 mask. */ -#define DMA_CH_DESTRELOAD1_bp 3 /* Channel Destination Address Reload bit 1 position. */ - -#define DMA_CH_DESTDIR_gm 0x03 /* Channel Destination Address Mode group mask. */ -#define DMA_CH_DESTDIR_gp 0 /* Channel Destination Address Mode group position. */ -#define DMA_CH_DESTDIR0_bm (1<<0) /* Channel Destination Address Mode bit 0 mask. */ -#define DMA_CH_DESTDIR0_bp 0 /* Channel Destination Address Mode bit 0 position. */ -#define DMA_CH_DESTDIR1_bm (1<<1) /* Channel Destination Address Mode bit 1 mask. */ -#define DMA_CH_DESTDIR1_bp 1 /* Channel Destination Address Mode bit 1 position. */ - -/* DMA_CH.TRIGSRC bit masks and bit positions */ -#define DMA_CH_TRIGSRC_gm 0xFF /* Channel Trigger Source group mask. */ -#define DMA_CH_TRIGSRC_gp 0 /* Channel Trigger Source group position. */ -#define DMA_CH_TRIGSRC0_bm (1<<0) /* Channel Trigger Source bit 0 mask. */ -#define DMA_CH_TRIGSRC0_bp 0 /* Channel Trigger Source bit 0 position. */ -#define DMA_CH_TRIGSRC1_bm (1<<1) /* Channel Trigger Source bit 1 mask. */ -#define DMA_CH_TRIGSRC1_bp 1 /* Channel Trigger Source bit 1 position. */ -#define DMA_CH_TRIGSRC2_bm (1<<2) /* Channel Trigger Source bit 2 mask. */ -#define DMA_CH_TRIGSRC2_bp 2 /* Channel Trigger Source bit 2 position. */ -#define DMA_CH_TRIGSRC3_bm (1<<3) /* Channel Trigger Source bit 3 mask. */ -#define DMA_CH_TRIGSRC3_bp 3 /* Channel Trigger Source bit 3 position. */ -#define DMA_CH_TRIGSRC4_bm (1<<4) /* Channel Trigger Source bit 4 mask. */ -#define DMA_CH_TRIGSRC4_bp 4 /* Channel Trigger Source bit 4 position. */ -#define DMA_CH_TRIGSRC5_bm (1<<5) /* Channel Trigger Source bit 5 mask. */ -#define DMA_CH_TRIGSRC5_bp 5 /* Channel Trigger Source bit 5 position. */ -#define DMA_CH_TRIGSRC6_bm (1<<6) /* Channel Trigger Source bit 6 mask. */ -#define DMA_CH_TRIGSRC6_bp 6 /* Channel Trigger Source bit 6 position. */ -#define DMA_CH_TRIGSRC7_bm (1<<7) /* Channel Trigger Source bit 7 mask. */ -#define DMA_CH_TRIGSRC7_bp 7 /* Channel Trigger Source bit 7 position. */ - -/* DMA.CTRL bit masks and bit positions */ -#define DMA_ENABLE_bm 0x80 /* Enable bit mask. */ -#define DMA_ENABLE_bp 7 /* Enable bit position. */ - -#define DMA_RESET_bm 0x40 /* Software Reset bit mask. */ -#define DMA_RESET_bp 6 /* Software Reset bit position. */ - -#define DMA_DBUFMODE_bm 0x04 /* Double Buffering Mode bit mask. */ -#define DMA_DBUFMODE_bp 2 /* Double Buffering Mode bit position. */ - -#define DMA_PRIMODE_bm 0x01 /* Channel Priority Mode bit mask. */ -#define DMA_PRIMODE_bp 0 /* Channel Priority Mode bit position. */ - -/* DMA.INTFLAGS bit masks and bit positions */ -#define DMA_CH1ERRIF_bm 0x20 /* Channel 1 Block Transfer Error Interrupt Flag bit mask. */ -#define DMA_CH1ERRIF_bp 5 /* Channel 1 Block Transfer Error Interrupt Flag bit position. */ - -#define DMA_CH0ERRIF_bm 0x10 /* Channel 0 Block Transfer Error Interrupt Flag bit mask. */ -#define DMA_CH0ERRIF_bp 4 /* Channel 0 Block Transfer Error Interrupt Flag bit position. */ - -#define DMA_CH1TRNIF_bm 0x02 /* Channel 1 Transaction Complete Interrupt Flag bit mask. */ -#define DMA_CH1TRNIF_bp 1 /* Channel 1 Transaction Complete Interrupt Flag bit position. */ - -#define DMA_CH0TRNIF_bm 0x01 /* Channel 0 Transaction Complete Interrupt Flag bit mask. */ -#define DMA_CH0TRNIF_bp 0 /* Channel 0 Transaction Complete Interrupt Flag bit position. */ - -/* DMA.STATUS bit masks and bit positions */ -#define DMA_CH1BUSY_bm 0x20 /* Channel 1 Block Transfer Busy bit mask. */ -#define DMA_CH1BUSY_bp 5 /* Channel 1 Block Transfer Busy bit position. */ - -#define DMA_CH0BUSY_bm 0x10 /* Channel 0 Block Transfer Busy bit mask. */ -#define DMA_CH0BUSY_bp 4 /* Channel 0 Block Transfer Busy bit position. */ - -#define DMA_CH1PEND_bm 0x02 /* Channel 1 Block Transfer Pending bit mask. */ -#define DMA_CH1PEND_bp 1 /* Channel 1 Block Transfer Pending bit position. */ - -#define DMA_CH0PEND_bm 0x01 /* Channel 0 Block Transfer Pending bit mask. */ -#define DMA_CH0PEND_bp 0 /* Channel 0 Block Transfer Pending bit position. */ - -/* EVSYS - Event System */ -/* EVSYS.CH0MUX bit masks and bit positions */ -#define EVSYS_CHMUX_gm 0xFF /* Event Channel 0 Multiplexer group mask. */ -#define EVSYS_CHMUX_gp 0 /* Event Channel 0 Multiplexer group position. */ -#define EVSYS_CHMUX0_bm (1<<0) /* Event Channel 0 Multiplexer bit 0 mask. */ -#define EVSYS_CHMUX0_bp 0 /* Event Channel 0 Multiplexer bit 0 position. */ -#define EVSYS_CHMUX1_bm (1<<1) /* Event Channel 0 Multiplexer bit 1 mask. */ -#define EVSYS_CHMUX1_bp 1 /* Event Channel 0 Multiplexer bit 1 position. */ -#define EVSYS_CHMUX2_bm (1<<2) /* Event Channel 0 Multiplexer bit 2 mask. */ -#define EVSYS_CHMUX2_bp 2 /* Event Channel 0 Multiplexer bit 2 position. */ -#define EVSYS_CHMUX3_bm (1<<3) /* Event Channel 0 Multiplexer bit 3 mask. */ -#define EVSYS_CHMUX3_bp 3 /* Event Channel 0 Multiplexer bit 3 position. */ -#define EVSYS_CHMUX4_bm (1<<4) /* Event Channel 0 Multiplexer bit 4 mask. */ -#define EVSYS_CHMUX4_bp 4 /* Event Channel 0 Multiplexer bit 4 position. */ -#define EVSYS_CHMUX5_bm (1<<5) /* Event Channel 0 Multiplexer bit 5 mask. */ -#define EVSYS_CHMUX5_bp 5 /* Event Channel 0 Multiplexer bit 5 position. */ -#define EVSYS_CHMUX6_bm (1<<6) /* Event Channel 0 Multiplexer bit 6 mask. */ -#define EVSYS_CHMUX6_bp 6 /* Event Channel 0 Multiplexer bit 6 position. */ -#define EVSYS_CHMUX7_bm (1<<7) /* Event Channel 0 Multiplexer bit 7 mask. */ -#define EVSYS_CHMUX7_bp 7 /* Event Channel 0 Multiplexer bit 7 position. */ - -/* EVSYS.CH1MUX bit masks and bit positions */ -/* EVSYS_CHMUX Predefined. */ -/* EVSYS_CHMUX Predefined. */ - -/* EVSYS.CH2MUX bit masks and bit positions */ -/* EVSYS_CHMUX Predefined. */ -/* EVSYS_CHMUX Predefined. */ - -/* EVSYS.CH3MUX bit masks and bit positions */ -/* EVSYS_CHMUX Predefined. */ -/* EVSYS_CHMUX Predefined. */ - -/* EVSYS.CH0CTRL bit masks and bit positions */ -#define EVSYS_QDIRM_gm 0x60 /* Quadrature Decoder Index Recognition Mode group mask. */ -#define EVSYS_QDIRM_gp 5 /* Quadrature Decoder Index Recognition Mode group position. */ -#define EVSYS_QDIRM0_bm (1<<5) /* Quadrature Decoder Index Recognition Mode bit 0 mask. */ -#define EVSYS_QDIRM0_bp 5 /* Quadrature Decoder Index Recognition Mode bit 0 position. */ -#define EVSYS_QDIRM1_bm (1<<6) /* Quadrature Decoder Index Recognition Mode bit 1 mask. */ -#define EVSYS_QDIRM1_bp 6 /* Quadrature Decoder Index Recognition Mode bit 1 position. */ - -#define EVSYS_QDIEN_bm 0x10 /* Quadrature Decoder Index Enable bit mask. */ -#define EVSYS_QDIEN_bp 4 /* Quadrature Decoder Index Enable bit position. */ - -#define EVSYS_QDEN_bm 0x08 /* Quadrature Decoder Enable bit mask. */ -#define EVSYS_QDEN_bp 3 /* Quadrature Decoder Enable bit position. */ - -#define EVSYS_DIGFILT_gm 0x07 /* Digital Filter group mask. */ -#define EVSYS_DIGFILT_gp 0 /* Digital Filter group position. */ -#define EVSYS_DIGFILT0_bm (1<<0) /* Digital Filter bit 0 mask. */ -#define EVSYS_DIGFILT0_bp 0 /* Digital Filter bit 0 position. */ -#define EVSYS_DIGFILT1_bm (1<<1) /* Digital Filter bit 1 mask. */ -#define EVSYS_DIGFILT1_bp 1 /* Digital Filter bit 1 position. */ -#define EVSYS_DIGFILT2_bm (1<<2) /* Digital Filter bit 2 mask. */ -#define EVSYS_DIGFILT2_bp 2 /* Digital Filter bit 2 position. */ - -/* EVSYS.CH1CTRL bit masks and bit positions */ -/* EVSYS_DIGFILT Predefined. */ -/* EVSYS_DIGFILT Predefined. */ - -/* EVSYS.CH2CTRL bit masks and bit positions */ -/* EVSYS_DIGFILT Predefined. */ -/* EVSYS_DIGFILT Predefined. */ - -/* EVSYS.CH3CTRL bit masks and bit positions */ -/* EVSYS_DIGFILT Predefined. */ -/* EVSYS_DIGFILT Predefined. */ - -/* NVM - Non Volatile Memory Controller */ -/* NVM.CMD bit masks and bit positions */ -#define NVM_CMD_gm 0x7F /* Command group mask. */ -#define NVM_CMD_gp 0 /* Command group position. */ -#define NVM_CMD0_bm (1<<0) /* Command bit 0 mask. */ -#define NVM_CMD0_bp 0 /* Command bit 0 position. */ -#define NVM_CMD1_bm (1<<1) /* Command bit 1 mask. */ -#define NVM_CMD1_bp 1 /* Command bit 1 position. */ -#define NVM_CMD2_bm (1<<2) /* Command bit 2 mask. */ -#define NVM_CMD2_bp 2 /* Command bit 2 position. */ -#define NVM_CMD3_bm (1<<3) /* Command bit 3 mask. */ -#define NVM_CMD3_bp 3 /* Command bit 3 position. */ -#define NVM_CMD4_bm (1<<4) /* Command bit 4 mask. */ -#define NVM_CMD4_bp 4 /* Command bit 4 position. */ -#define NVM_CMD5_bm (1<<5) /* Command bit 5 mask. */ -#define NVM_CMD5_bp 5 /* Command bit 5 position. */ -#define NVM_CMD6_bm (1<<6) /* Command bit 6 mask. */ -#define NVM_CMD6_bp 6 /* Command bit 6 position. */ - -/* NVM.CTRLA bit masks and bit positions */ -#define NVM_CMDEX_bm 0x01 /* Command Execute bit mask. */ -#define NVM_CMDEX_bp 0 /* Command Execute bit position. */ - -/* NVM.CTRLB bit masks and bit positions */ -#define NVM_EEMAPEN_bm 0x08 /* EEPROM Mapping Enable bit mask. */ -#define NVM_EEMAPEN_bp 3 /* EEPROM Mapping Enable bit position. */ - -#define NVM_FPRM_bm 0x04 /* Flash Power Reduction Enable bit mask. */ -#define NVM_FPRM_bp 2 /* Flash Power Reduction Enable bit position. */ - -#define NVM_EPRM_bm 0x02 /* EEPROM Power Reduction Enable bit mask. */ -#define NVM_EPRM_bp 1 /* EEPROM Power Reduction Enable bit position. */ - -#define NVM_SPMLOCK_bm 0x01 /* SPM Lock bit mask. */ -#define NVM_SPMLOCK_bp 0 /* SPM Lock bit position. */ - -/* NVM.INTCTRL bit masks and bit positions */ -#define NVM_SPMLVL_gm 0x0C /* SPM Interrupt Level group mask. */ -#define NVM_SPMLVL_gp 2 /* SPM Interrupt Level group position. */ -#define NVM_SPMLVL0_bm (1<<2) /* SPM Interrupt Level bit 0 mask. */ -#define NVM_SPMLVL0_bp 2 /* SPM Interrupt Level bit 0 position. */ -#define NVM_SPMLVL1_bm (1<<3) /* SPM Interrupt Level bit 1 mask. */ -#define NVM_SPMLVL1_bp 3 /* SPM Interrupt Level bit 1 position. */ - -#define NVM_EELVL_gm 0x03 /* EEPROM Interrupt Level group mask. */ -#define NVM_EELVL_gp 0 /* EEPROM Interrupt Level group position. */ -#define NVM_EELVL0_bm (1<<0) /* EEPROM Interrupt Level bit 0 mask. */ -#define NVM_EELVL0_bp 0 /* EEPROM Interrupt Level bit 0 position. */ -#define NVM_EELVL1_bm (1<<1) /* EEPROM Interrupt Level bit 1 mask. */ -#define NVM_EELVL1_bp 1 /* EEPROM Interrupt Level bit 1 position. */ - -/* NVM.STATUS bit masks and bit positions */ -#define NVM_NVMBUSY_bm 0x80 /* Non-volatile Memory Busy bit mask. */ -#define NVM_NVMBUSY_bp 7 /* Non-volatile Memory Busy bit position. */ - -#define NVM_FBUSY_bm 0x40 /* Flash Memory Busy bit mask. */ -#define NVM_FBUSY_bp 6 /* Flash Memory Busy bit position. */ - -#define NVM_EELOAD_bm 0x02 /* EEPROM Page Buffer Active Loading bit mask. */ -#define NVM_EELOAD_bp 1 /* EEPROM Page Buffer Active Loading bit position. */ - -#define NVM_FLOAD_bm 0x01 /* Flash Page Buffer Active Loading bit mask. */ -#define NVM_FLOAD_bp 0 /* Flash Page Buffer Active Loading bit position. */ - -/* NVM.LOCKBITS bit masks and bit positions */ -#define NVM_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ -#define NVM_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ -#define NVM_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ -#define NVM_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ -#define NVM_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ -#define NVM_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ - -#define NVM_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ -#define NVM_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ -#define NVM_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ -#define NVM_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ -#define NVM_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ -#define NVM_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ - -#define NVM_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ -#define NVM_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ -#define NVM_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ -#define NVM_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ -#define NVM_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ -#define NVM_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ - -#define NVM_LB_gm 0x03 /* Lock Bits group mask. */ -#define NVM_LB_gp 0 /* Lock Bits group position. */ -#define NVM_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ -#define NVM_LB0_bp 0 /* Lock Bits bit 0 position. */ -#define NVM_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ -#define NVM_LB1_bp 1 /* Lock Bits bit 1 position. */ - -/* ADC - Analog/Digital Converter */ -/* ADC_CH.CTRL bit masks and bit positions */ -#define ADC_CH_START_bm 0x80 /* Channel Start Conversion bit mask. */ -#define ADC_CH_START_bp 7 /* Channel Start Conversion bit position. */ - -#define ADC_CH_GAIN_gm 0x1C /* Gain Factor group mask. */ -#define ADC_CH_GAIN_gp 2 /* Gain Factor group position. */ -#define ADC_CH_GAIN0_bm (1<<2) /* Gain Factor bit 0 mask. */ -#define ADC_CH_GAIN0_bp 2 /* Gain Factor bit 0 position. */ -#define ADC_CH_GAIN1_bm (1<<3) /* Gain Factor bit 1 mask. */ -#define ADC_CH_GAIN1_bp 3 /* Gain Factor bit 1 position. */ -#define ADC_CH_GAIN2_bm (1<<4) /* Gain Factor bit 2 mask. */ -#define ADC_CH_GAIN2_bp 4 /* Gain Factor bit 2 position. */ - -#define ADC_CH_INPUTMODE_gm 0x03 /* Input Mode Select group mask. */ -#define ADC_CH_INPUTMODE_gp 0 /* Input Mode Select group position. */ -#define ADC_CH_INPUTMODE0_bm (1<<0) /* Input Mode Select bit 0 mask. */ -#define ADC_CH_INPUTMODE0_bp 0 /* Input Mode Select bit 0 position. */ -#define ADC_CH_INPUTMODE1_bm (1<<1) /* Input Mode Select bit 1 mask. */ -#define ADC_CH_INPUTMODE1_bp 1 /* Input Mode Select bit 1 position. */ - -/* ADC_CH.MUXCTRL bit masks and bit positions */ -#define ADC_CH_MUXPOS_gm 0x78 /* MUX selection on Positive ADC input group mask. */ -#define ADC_CH_MUXPOS_gp 3 /* MUX selection on Positive ADC input group position. */ -#define ADC_CH_MUXPOS0_bm (1<<3) /* MUX selection on Positive ADC input bit 0 mask. */ -#define ADC_CH_MUXPOS0_bp 3 /* MUX selection on Positive ADC input bit 0 position. */ -#define ADC_CH_MUXPOS1_bm (1<<4) /* MUX selection on Positive ADC input bit 1 mask. */ -#define ADC_CH_MUXPOS1_bp 4 /* MUX selection on Positive ADC input bit 1 position. */ -#define ADC_CH_MUXPOS2_bm (1<<5) /* MUX selection on Positive ADC input bit 2 mask. */ -#define ADC_CH_MUXPOS2_bp 5 /* MUX selection on Positive ADC input bit 2 position. */ -#define ADC_CH_MUXPOS3_bm (1<<6) /* MUX selection on Positive ADC input bit 3 mask. */ -#define ADC_CH_MUXPOS3_bp 6 /* MUX selection on Positive ADC input bit 3 position. */ - -#define ADC_CH_MUXINT_gm 0x78 /* MUX selection on Internal ADC input group mask. */ -#define ADC_CH_MUXINT_gp 3 /* MUX selection on Internal ADC input group position. */ -#define ADC_CH_MUXINT0_bm (1<<3) /* MUX selection on Internal ADC input bit 0 mask. */ -#define ADC_CH_MUXINT0_bp 3 /* MUX selection on Internal ADC input bit 0 position. */ -#define ADC_CH_MUXINT1_bm (1<<4) /* MUX selection on Internal ADC input bit 1 mask. */ -#define ADC_CH_MUXINT1_bp 4 /* MUX selection on Internal ADC input bit 1 position. */ -#define ADC_CH_MUXINT2_bm (1<<5) /* MUX selection on Internal ADC input bit 2 mask. */ -#define ADC_CH_MUXINT2_bp 5 /* MUX selection on Internal ADC input bit 2 position. */ -#define ADC_CH_MUXINT3_bm (1<<6) /* MUX selection on Internal ADC input bit 3 mask. */ -#define ADC_CH_MUXINT3_bp 6 /* MUX selection on Internal ADC input bit 3 position. */ - -#define ADC_CH_MUXNEG_gm 0x03 /* MUX selection on Negative ADC input group mask. */ -#define ADC_CH_MUXNEG_gp 0 /* MUX selection on Negative ADC input group position. */ -#define ADC_CH_MUXNEG0_bm (1<<0) /* MUX selection on Negative ADC input bit 0 mask. */ -#define ADC_CH_MUXNEG0_bp 0 /* MUX selection on Negative ADC input bit 0 position. */ -#define ADC_CH_MUXNEG1_bm (1<<1) /* MUX selection on Negative ADC input bit 1 mask. */ -#define ADC_CH_MUXNEG1_bp 1 /* MUX selection on Negative ADC input bit 1 position. */ - -/* ADC_CH.INTCTRL bit masks and bit positions */ -#define ADC_CH_INTMODE_gm 0x0C /* Interrupt Mode group mask. */ -#define ADC_CH_INTMODE_gp 2 /* Interrupt Mode group position. */ -#define ADC_CH_INTMODE0_bm (1<<2) /* Interrupt Mode bit 0 mask. */ -#define ADC_CH_INTMODE0_bp 2 /* Interrupt Mode bit 0 position. */ -#define ADC_CH_INTMODE1_bm (1<<3) /* Interrupt Mode bit 1 mask. */ -#define ADC_CH_INTMODE1_bp 3 /* Interrupt Mode bit 1 position. */ - -#define ADC_CH_INTLVL_gm 0x03 /* Interrupt Level group mask. */ -#define ADC_CH_INTLVL_gp 0 /* Interrupt Level group position. */ -#define ADC_CH_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */ -#define ADC_CH_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */ -#define ADC_CH_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ -#define ADC_CH_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */ - -/* ADC_CH.INTFLAGS bit masks and bit positions */ -#define ADC_CH_CHIF_bm 0x01 /* Channel Interrupt Flag bit mask. */ -#define ADC_CH_CHIF_bp 0 /* Channel Interrupt Flag bit position. */ - -/* ADC_CH.SCAN bit masks and bit positions */ -#define ADC_CH_OFFSET_gm 0xF0 /* Positive MUX setting offset group mask. */ -#define ADC_CH_OFFSET_gp 4 /* Positive MUX setting offset group position. */ -#define ADC_CH_OFFSET0_bm (1<<4) /* Positive MUX setting offset bit 0 mask. */ -#define ADC_CH_OFFSET0_bp 4 /* Positive MUX setting offset bit 0 position. */ -#define ADC_CH_OFFSET1_bm (1<<5) /* Positive MUX setting offset bit 1 mask. */ -#define ADC_CH_OFFSET1_bp 5 /* Positive MUX setting offset bit 1 position. */ -#define ADC_CH_OFFSET2_bm (1<<6) /* Positive MUX setting offset bit 2 mask. */ -#define ADC_CH_OFFSET2_bp 6 /* Positive MUX setting offset bit 2 position. */ -#define ADC_CH_OFFSET3_bm (1<<7) /* Positive MUX setting offset bit 3 mask. */ -#define ADC_CH_OFFSET3_bp 7 /* Positive MUX setting offset bit 3 position. */ - -#define ADC_CH_COUNT_gm 0x0F /* Number of Channels included in scan group mask. */ -#define ADC_CH_COUNT_gp 0 /* Number of Channels included in scan group position. */ -#define ADC_CH_COUNT0_bm (1<<0) /* Number of Channels included in scan bit 0 mask. */ -#define ADC_CH_COUNT0_bp 0 /* Number of Channels included in scan bit 0 position. */ -#define ADC_CH_COUNT1_bm (1<<1) /* Number of Channels included in scan bit 1 mask. */ -#define ADC_CH_COUNT1_bp 1 /* Number of Channels included in scan bit 1 position. */ -#define ADC_CH_COUNT2_bm (1<<2) /* Number of Channels included in scan bit 2 mask. */ -#define ADC_CH_COUNT2_bp 2 /* Number of Channels included in scan bit 2 position. */ -#define ADC_CH_COUNT3_bm (1<<3) /* Number of Channels included in scan bit 3 mask. */ -#define ADC_CH_COUNT3_bp 3 /* Number of Channels included in scan bit 3 position. */ - -/* ADC.CTRLA bit masks and bit positions */ -#define ADC_CH0START_bm 0x04 /* Channel 0 Start Conversion bit mask. */ -#define ADC_CH0START_bp 2 /* Channel 0 Start Conversion bit position. */ - -#define ADC_FLUSH_bm 0x02 /* ADC Flush bit mask. */ -#define ADC_FLUSH_bp 1 /* ADC Flush bit position. */ - -#define ADC_ENABLE_bm 0x01 /* Enable ADC bit mask. */ -#define ADC_ENABLE_bp 0 /* Enable ADC bit position. */ - -/* ADC.CTRLB bit masks and bit positions */ -#define ADC_CURRLIMIT_gm 0x60 /* Current limit group mask. */ -#define ADC_CURRLIMIT_gp 5 /* Current limit group position. */ -#define ADC_CURRLIMIT0_bm (1<<5) /* Current limit bit 0 mask. */ -#define ADC_CURRLIMIT0_bp 5 /* Current limit bit 0 position. */ -#define ADC_CURRLIMIT1_bm (1<<6) /* Current limit bit 1 mask. */ -#define ADC_CURRLIMIT1_bp 6 /* Current limit bit 1 position. */ - -#define ADC_CONMODE_bm 0x10 /* Conversion Mode bit mask. */ -#define ADC_CONMODE_bp 4 /* Conversion Mode bit position. */ - -#define ADC_FREERUN_bm 0x08 /* Free Running Mode Enable bit mask. */ -#define ADC_FREERUN_bp 3 /* Free Running Mode Enable bit position. */ - -#define ADC_RESOLUTION_gm 0x06 /* Result Resolution group mask. */ -#define ADC_RESOLUTION_gp 1 /* Result Resolution group position. */ -#define ADC_RESOLUTION0_bm (1<<1) /* Result Resolution bit 0 mask. */ -#define ADC_RESOLUTION0_bp 1 /* Result Resolution bit 0 position. */ -#define ADC_RESOLUTION1_bm (1<<2) /* Result Resolution bit 1 mask. */ -#define ADC_RESOLUTION1_bp 2 /* Result Resolution bit 1 position. */ - -/* ADC.REFCTRL bit masks and bit positions */ -#define ADC_REFSEL_gm 0x70 /* Reference Selection group mask. */ -#define ADC_REFSEL_gp 4 /* Reference Selection group position. */ -#define ADC_REFSEL0_bm (1<<4) /* Reference Selection bit 0 mask. */ -#define ADC_REFSEL0_bp 4 /* Reference Selection bit 0 position. */ -#define ADC_REFSEL1_bm (1<<5) /* Reference Selection bit 1 mask. */ -#define ADC_REFSEL1_bp 5 /* Reference Selection bit 1 position. */ -#define ADC_REFSEL2_bm (1<<6) /* Reference Selection bit 2 mask. */ -#define ADC_REFSEL2_bp 6 /* Reference Selection bit 2 position. */ - -#define ADC_BANDGAP_bm 0x02 /* Bandgap enable bit mask. */ -#define ADC_BANDGAP_bp 1 /* Bandgap enable bit position. */ - -#define ADC_TEMPREF_bm 0x01 /* Temperature Reference Enable bit mask. */ -#define ADC_TEMPREF_bp 0 /* Temperature Reference Enable bit position. */ - -/* ADC.EVCTRL bit masks and bit positions */ -#define ADC_EVSEL_gm 0x18 /* Event Input Select group mask. */ -#define ADC_EVSEL_gp 3 /* Event Input Select group position. */ -#define ADC_EVSEL0_bm (1<<3) /* Event Input Select bit 0 mask. */ -#define ADC_EVSEL0_bp 3 /* Event Input Select bit 0 position. */ -#define ADC_EVSEL1_bm (1<<4) /* Event Input Select bit 1 mask. */ -#define ADC_EVSEL1_bp 4 /* Event Input Select bit 1 position. */ - -#define ADC_EVACT_gm 0x07 /* Event Action Select group mask. */ -#define ADC_EVACT_gp 0 /* Event Action Select group position. */ -#define ADC_EVACT0_bm (1<<0) /* Event Action Select bit 0 mask. */ -#define ADC_EVACT0_bp 0 /* Event Action Select bit 0 position. */ -#define ADC_EVACT1_bm (1<<1) /* Event Action Select bit 1 mask. */ -#define ADC_EVACT1_bp 1 /* Event Action Select bit 1 position. */ -#define ADC_EVACT2_bm (1<<2) /* Event Action Select bit 2 mask. */ -#define ADC_EVACT2_bp 2 /* Event Action Select bit 2 position. */ - -/* ADC.PRESCALER bit masks and bit positions */ -#define ADC_PRESCALER_gm 0x07 /* Clock Prescaler Selection group mask. */ -#define ADC_PRESCALER_gp 0 /* Clock Prescaler Selection group position. */ -#define ADC_PRESCALER0_bm (1<<0) /* Clock Prescaler Selection bit 0 mask. */ -#define ADC_PRESCALER0_bp 0 /* Clock Prescaler Selection bit 0 position. */ -#define ADC_PRESCALER1_bm (1<<1) /* Clock Prescaler Selection bit 1 mask. */ -#define ADC_PRESCALER1_bp 1 /* Clock Prescaler Selection bit 1 position. */ -#define ADC_PRESCALER2_bm (1<<2) /* Clock Prescaler Selection bit 2 mask. */ -#define ADC_PRESCALER2_bp 2 /* Clock Prescaler Selection bit 2 position. */ - -/* ADC.INTFLAGS bit masks and bit positions */ -#define ADC_CH0IF_bm 0x01 /* Channel 0 Interrupt Flag bit mask. */ -#define ADC_CH0IF_bp 0 /* Channel 0 Interrupt Flag bit position. */ - -/* ADC.SAMPCTRL bit masks and bit positions */ -#define ADC_SAMPVAL_gm 0x3F /* Sampling time control register group mask. */ -#define ADC_SAMPVAL_gp 0 /* Sampling time control register group position. */ -#define ADC_SAMPVAL0_bm (1<<0) /* Sampling time control register bit 0 mask. */ -#define ADC_SAMPVAL0_bp 0 /* Sampling time control register bit 0 position. */ -#define ADC_SAMPVAL1_bm (1<<1) /* Sampling time control register bit 1 mask. */ -#define ADC_SAMPVAL1_bp 1 /* Sampling time control register bit 1 position. */ -#define ADC_SAMPVAL2_bm (1<<2) /* Sampling time control register bit 2 mask. */ -#define ADC_SAMPVAL2_bp 2 /* Sampling time control register bit 2 position. */ -#define ADC_SAMPVAL3_bm (1<<3) /* Sampling time control register bit 3 mask. */ -#define ADC_SAMPVAL3_bp 3 /* Sampling time control register bit 3 position. */ -#define ADC_SAMPVAL4_bm (1<<4) /* Sampling time control register bit 4 mask. */ -#define ADC_SAMPVAL4_bp 4 /* Sampling time control register bit 4 position. */ -#define ADC_SAMPVAL5_bm (1<<5) /* Sampling time control register bit 5 mask. */ -#define ADC_SAMPVAL5_bp 5 /* Sampling time control register bit 5 position. */ - -/* AC - Analog Comparator */ -/* AC.AC0CTRL bit masks and bit positions */ -#define AC_INTMODE_gm 0xC0 /* Interrupt Mode group mask. */ -#define AC_INTMODE_gp 6 /* Interrupt Mode group position. */ -#define AC_INTMODE0_bm (1<<6) /* Interrupt Mode bit 0 mask. */ -#define AC_INTMODE0_bp 6 /* Interrupt Mode bit 0 position. */ -#define AC_INTMODE1_bm (1<<7) /* Interrupt Mode bit 1 mask. */ -#define AC_INTMODE1_bp 7 /* Interrupt Mode bit 1 position. */ - -#define AC_INTLVL_gm 0x30 /* Interrupt Level group mask. */ -#define AC_INTLVL_gp 4 /* Interrupt Level group position. */ -#define AC_INTLVL0_bm (1<<4) /* Interrupt Level bit 0 mask. */ -#define AC_INTLVL0_bp 4 /* Interrupt Level bit 0 position. */ -#define AC_INTLVL1_bm (1<<5) /* Interrupt Level bit 1 mask. */ -#define AC_INTLVL1_bp 5 /* Interrupt Level bit 1 position. */ - -#define AC_HYSMODE_gm 0x06 /* Hysteresis Mode group mask. */ -#define AC_HYSMODE_gp 1 /* Hysteresis Mode group position. */ -#define AC_HYSMODE0_bm (1<<1) /* Hysteresis Mode bit 0 mask. */ -#define AC_HYSMODE0_bp 1 /* Hysteresis Mode bit 0 position. */ -#define AC_HYSMODE1_bm (1<<2) /* Hysteresis Mode bit 1 mask. */ -#define AC_HYSMODE1_bp 2 /* Hysteresis Mode bit 1 position. */ - -#define AC_ENABLE_bm 0x01 /* Enable bit mask. */ -#define AC_ENABLE_bp 0 /* Enable bit position. */ - -/* AC.AC1CTRL bit masks and bit positions */ -/* AC_INTMODE Predefined. */ -/* AC_INTMODE Predefined. */ - -/* AC_INTLVL Predefined. */ -/* AC_INTLVL Predefined. */ - -/* AC_HYSMODE Predefined. */ -/* AC_HYSMODE Predefined. */ - -/* AC_ENABLE Predefined. */ -/* AC_ENABLE Predefined. */ - -/* AC.AC0MUXCTRL bit masks and bit positions */ -#define AC_MUXPOS_gm 0x38 /* MUX Positive Input group mask. */ -#define AC_MUXPOS_gp 3 /* MUX Positive Input group position. */ -#define AC_MUXPOS0_bm (1<<3) /* MUX Positive Input bit 0 mask. */ -#define AC_MUXPOS0_bp 3 /* MUX Positive Input bit 0 position. */ -#define AC_MUXPOS1_bm (1<<4) /* MUX Positive Input bit 1 mask. */ -#define AC_MUXPOS1_bp 4 /* MUX Positive Input bit 1 position. */ -#define AC_MUXPOS2_bm (1<<5) /* MUX Positive Input bit 2 mask. */ -#define AC_MUXPOS2_bp 5 /* MUX Positive Input bit 2 position. */ - -#define AC_MUXNEG_gm 0x07 /* MUX Negative Input group mask. */ -#define AC_MUXNEG_gp 0 /* MUX Negative Input group position. */ -#define AC_MUXNEG0_bm (1<<0) /* MUX Negative Input bit 0 mask. */ -#define AC_MUXNEG0_bp 0 /* MUX Negative Input bit 0 position. */ -#define AC_MUXNEG1_bm (1<<1) /* MUX Negative Input bit 1 mask. */ -#define AC_MUXNEG1_bp 1 /* MUX Negative Input bit 1 position. */ -#define AC_MUXNEG2_bm (1<<2) /* MUX Negative Input bit 2 mask. */ -#define AC_MUXNEG2_bp 2 /* MUX Negative Input bit 2 position. */ - -/* AC.AC1MUXCTRL bit masks and bit positions */ -/* AC_MUXPOS Predefined. */ -/* AC_MUXPOS Predefined. */ - -/* AC_MUXNEG Predefined. */ -/* AC_MUXNEG Predefined. */ - -/* AC.CTRLA bit masks and bit positions */ -#define AC_AC1OUT_bm 0x02 /* Analog Comparator 1 Output Enable bit mask. */ -#define AC_AC1OUT_bp 1 /* Analog Comparator 1 Output Enable bit position. */ - -#define AC_AC0OUT_bm 0x01 /* Analog Comparator 0 Output Enable bit mask. */ -#define AC_AC0OUT_bp 0 /* Analog Comparator 0 Output Enable bit position. */ - -/* AC.CTRLB bit masks and bit positions */ -#define AC_SCALEFAC_gm 0x3F /* VCC Voltage Scaler Factor group mask. */ -#define AC_SCALEFAC_gp 0 /* VCC Voltage Scaler Factor group position. */ -#define AC_SCALEFAC0_bm (1<<0) /* VCC Voltage Scaler Factor bit 0 mask. */ -#define AC_SCALEFAC0_bp 0 /* VCC Voltage Scaler Factor bit 0 position. */ -#define AC_SCALEFAC1_bm (1<<1) /* VCC Voltage Scaler Factor bit 1 mask. */ -#define AC_SCALEFAC1_bp 1 /* VCC Voltage Scaler Factor bit 1 position. */ -#define AC_SCALEFAC2_bm (1<<2) /* VCC Voltage Scaler Factor bit 2 mask. */ -#define AC_SCALEFAC2_bp 2 /* VCC Voltage Scaler Factor bit 2 position. */ -#define AC_SCALEFAC3_bm (1<<3) /* VCC Voltage Scaler Factor bit 3 mask. */ -#define AC_SCALEFAC3_bp 3 /* VCC Voltage Scaler Factor bit 3 position. */ -#define AC_SCALEFAC4_bm (1<<4) /* VCC Voltage Scaler Factor bit 4 mask. */ -#define AC_SCALEFAC4_bp 4 /* VCC Voltage Scaler Factor bit 4 position. */ -#define AC_SCALEFAC5_bm (1<<5) /* VCC Voltage Scaler Factor bit 5 mask. */ -#define AC_SCALEFAC5_bp 5 /* VCC Voltage Scaler Factor bit 5 position. */ - -/* AC.WINCTRL bit masks and bit positions */ -#define AC_WEN_bm 0x10 /* Window Mode Enable bit mask. */ -#define AC_WEN_bp 4 /* Window Mode Enable bit position. */ - -#define AC_WINTMODE_gm 0x0C /* Window Interrupt Mode group mask. */ -#define AC_WINTMODE_gp 2 /* Window Interrupt Mode group position. */ -#define AC_WINTMODE0_bm (1<<2) /* Window Interrupt Mode bit 0 mask. */ -#define AC_WINTMODE0_bp 2 /* Window Interrupt Mode bit 0 position. */ -#define AC_WINTMODE1_bm (1<<3) /* Window Interrupt Mode bit 1 mask. */ -#define AC_WINTMODE1_bp 3 /* Window Interrupt Mode bit 1 position. */ - -#define AC_WINTLVL_gm 0x03 /* Window Interrupt Level group mask. */ -#define AC_WINTLVL_gp 0 /* Window Interrupt Level group position. */ -#define AC_WINTLVL0_bm (1<<0) /* Window Interrupt Level bit 0 mask. */ -#define AC_WINTLVL0_bp 0 /* Window Interrupt Level bit 0 position. */ -#define AC_WINTLVL1_bm (1<<1) /* Window Interrupt Level bit 1 mask. */ -#define AC_WINTLVL1_bp 1 /* Window Interrupt Level bit 1 position. */ - -/* AC.STATUS bit masks and bit positions */ -#define AC_WSTATE_gm 0xC0 /* Window Mode State group mask. */ -#define AC_WSTATE_gp 6 /* Window Mode State group position. */ -#define AC_WSTATE0_bm (1<<6) /* Window Mode State bit 0 mask. */ -#define AC_WSTATE0_bp 6 /* Window Mode State bit 0 position. */ -#define AC_WSTATE1_bm (1<<7) /* Window Mode State bit 1 mask. */ -#define AC_WSTATE1_bp 7 /* Window Mode State bit 1 position. */ - -#define AC_AC1STATE_bm 0x20 /* Analog Comparator 1 State bit mask. */ -#define AC_AC1STATE_bp 5 /* Analog Comparator 1 State bit position. */ - -#define AC_AC0STATE_bm 0x10 /* Analog Comparator 0 State bit mask. */ -#define AC_AC0STATE_bp 4 /* Analog Comparator 0 State bit position. */ - -#define AC_WIF_bm 0x04 /* Window Mode Interrupt Flag bit mask. */ -#define AC_WIF_bp 2 /* Window Mode Interrupt Flag bit position. */ - -#define AC_AC1IF_bm 0x02 /* Analog Comparator 1 Interrupt Flag bit mask. */ -#define AC_AC1IF_bp 1 /* Analog Comparator 1 Interrupt Flag bit position. */ - -#define AC_AC0IF_bm 0x01 /* Analog Comparator 0 Interrupt Flag bit mask. */ -#define AC_AC0IF_bp 0 /* Analog Comparator 0 Interrupt Flag bit position. */ - -/* AC.CURRCTRL bit masks and bit positions */ -#define AC_CURREN_bm 0x80 /* Current Source Enable bit mask. */ -#define AC_CURREN_bp 7 /* Current Source Enable bit position. */ - -#define AC_CURRMODE_bm 0x40 /* Current Mode bit mask. */ -#define AC_CURRMODE_bp 6 /* Current Mode bit position. */ - -#define AC_AC1CURR_bm 0x02 /* Analog Comparator 1 current source output bit mask. */ -#define AC_AC1CURR_bp 1 /* Analog Comparator 1 current source output bit position. */ - -#define AC_AC0CURR_bm 0x01 /* Analog Comparator 0 current source output bit mask. */ -#define AC_AC0CURR_bp 0 /* Analog Comparator 0 current source output bit position. */ - -/* AC.CURRCALIB bit masks and bit positions */ -#define AC_CALIB_gm 0x0F /* Current Source Calibration group mask. */ -#define AC_CALIB_gp 0 /* Current Source Calibration group position. */ -#define AC_CALIB0_bm (1<<0) /* Current Source Calibration bit 0 mask. */ -#define AC_CALIB0_bp 0 /* Current Source Calibration bit 0 position. */ -#define AC_CALIB1_bm (1<<1) /* Current Source Calibration bit 1 mask. */ -#define AC_CALIB1_bp 1 /* Current Source Calibration bit 1 position. */ -#define AC_CALIB2_bm (1<<2) /* Current Source Calibration bit 2 mask. */ -#define AC_CALIB2_bp 2 /* Current Source Calibration bit 2 position. */ -#define AC_CALIB3_bm (1<<3) /* Current Source Calibration bit 3 mask. */ -#define AC_CALIB3_bp 3 /* Current Source Calibration bit 3 position. */ - -/* RTC - Real-Time Counter */ -/* RTC.CTRL bit masks and bit positions */ -#define RTC_PRESCALER_gm 0x07 /* Prescaling Factor group mask. */ -#define RTC_PRESCALER_gp 0 /* Prescaling Factor group position. */ -#define RTC_PRESCALER0_bm (1<<0) /* Prescaling Factor bit 0 mask. */ -#define RTC_PRESCALER0_bp 0 /* Prescaling Factor bit 0 position. */ -#define RTC_PRESCALER1_bm (1<<1) /* Prescaling Factor bit 1 mask. */ -#define RTC_PRESCALER1_bp 1 /* Prescaling Factor bit 1 position. */ -#define RTC_PRESCALER2_bm (1<<2) /* Prescaling Factor bit 2 mask. */ -#define RTC_PRESCALER2_bp 2 /* Prescaling Factor bit 2 position. */ - -/* RTC.STATUS bit masks and bit positions */ -#define RTC_SYNCBUSY_bm 0x01 /* Synchronization Busy Flag bit mask. */ -#define RTC_SYNCBUSY_bp 0 /* Synchronization Busy Flag bit position. */ - -/* RTC.INTCTRL bit masks and bit positions */ -#define RTC_COMPINTLVL_gm 0x0C /* Compare Match Interrupt Level group mask. */ -#define RTC_COMPINTLVL_gp 2 /* Compare Match Interrupt Level group position. */ -#define RTC_COMPINTLVL0_bm (1<<2) /* Compare Match Interrupt Level bit 0 mask. */ -#define RTC_COMPINTLVL0_bp 2 /* Compare Match Interrupt Level bit 0 position. */ -#define RTC_COMPINTLVL1_bm (1<<3) /* Compare Match Interrupt Level bit 1 mask. */ -#define RTC_COMPINTLVL1_bp 3 /* Compare Match Interrupt Level bit 1 position. */ - -#define RTC_OVFINTLVL_gm 0x03 /* Overflow Interrupt Level group mask. */ -#define RTC_OVFINTLVL_gp 0 /* Overflow Interrupt Level group position. */ -#define RTC_OVFINTLVL0_bm (1<<0) /* Overflow Interrupt Level bit 0 mask. */ -#define RTC_OVFINTLVL0_bp 0 /* Overflow Interrupt Level bit 0 position. */ -#define RTC_OVFINTLVL1_bm (1<<1) /* Overflow Interrupt Level bit 1 mask. */ -#define RTC_OVFINTLVL1_bp 1 /* Overflow Interrupt Level bit 1 position. */ - -/* RTC.INTFLAGS bit masks and bit positions */ -#define RTC_COMPIF_bm 0x02 /* Compare Match Interrupt Flag bit mask. */ -#define RTC_COMPIF_bp 1 /* Compare Match Interrupt Flag bit position. */ - -#define RTC_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ -#define RTC_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ - -/* TWI - Two-Wire Interface */ -/* TWI_MASTER.CTRLA bit masks and bit positions */ -#define TWI_MASTER_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ -#define TWI_MASTER_INTLVL_gp 6 /* Interrupt Level group position. */ -#define TWI_MASTER_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ -#define TWI_MASTER_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ -#define TWI_MASTER_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ -#define TWI_MASTER_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ - -#define TWI_MASTER_RIEN_bm 0x20 /* Read Interrupt Enable bit mask. */ -#define TWI_MASTER_RIEN_bp 5 /* Read Interrupt Enable bit position. */ - -#define TWI_MASTER_WIEN_bm 0x10 /* Write Interrupt Enable bit mask. */ -#define TWI_MASTER_WIEN_bp 4 /* Write Interrupt Enable bit position. */ - -#define TWI_MASTER_ENABLE_bm 0x08 /* Enable TWI Master bit mask. */ -#define TWI_MASTER_ENABLE_bp 3 /* Enable TWI Master bit position. */ - -/* TWI_MASTER.CTRLB bit masks and bit positions */ -#define TWI_MASTER_TIMEOUT_gm 0x0C /* Inactive Bus Timeout group mask. */ -#define TWI_MASTER_TIMEOUT_gp 2 /* Inactive Bus Timeout group position. */ -#define TWI_MASTER_TIMEOUT0_bm (1<<2) /* Inactive Bus Timeout bit 0 mask. */ -#define TWI_MASTER_TIMEOUT0_bp 2 /* Inactive Bus Timeout bit 0 position. */ -#define TWI_MASTER_TIMEOUT1_bm (1<<3) /* Inactive Bus Timeout bit 1 mask. */ -#define TWI_MASTER_TIMEOUT1_bp 3 /* Inactive Bus Timeout bit 1 position. */ - -#define TWI_MASTER_QCEN_bm 0x02 /* Quick Command Enable bit mask. */ -#define TWI_MASTER_QCEN_bp 1 /* Quick Command Enable bit position. */ - -#define TWI_MASTER_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ -#define TWI_MASTER_SMEN_bp 0 /* Smart Mode Enable bit position. */ - -/* TWI_MASTER.CTRLC bit masks and bit positions */ -#define TWI_MASTER_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ -#define TWI_MASTER_ACKACT_bp 2 /* Acknowledge Action bit position. */ - -#define TWI_MASTER_CMD_gm 0x03 /* Command group mask. */ -#define TWI_MASTER_CMD_gp 0 /* Command group position. */ -#define TWI_MASTER_CMD0_bm (1<<0) /* Command bit 0 mask. */ -#define TWI_MASTER_CMD0_bp 0 /* Command bit 0 position. */ -#define TWI_MASTER_CMD1_bm (1<<1) /* Command bit 1 mask. */ -#define TWI_MASTER_CMD1_bp 1 /* Command bit 1 position. */ - -/* TWI_MASTER.STATUS bit masks and bit positions */ -#define TWI_MASTER_RIF_bm 0x80 /* Read Interrupt Flag bit mask. */ -#define TWI_MASTER_RIF_bp 7 /* Read Interrupt Flag bit position. */ - -#define TWI_MASTER_WIF_bm 0x40 /* Write Interrupt Flag bit mask. */ -#define TWI_MASTER_WIF_bp 6 /* Write Interrupt Flag bit position. */ - -#define TWI_MASTER_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ -#define TWI_MASTER_CLKHOLD_bp 5 /* Clock Hold bit position. */ - -#define TWI_MASTER_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ -#define TWI_MASTER_RXACK_bp 4 /* Received Acknowledge bit position. */ - -#define TWI_MASTER_ARBLOST_bm 0x08 /* Arbitration Lost bit mask. */ -#define TWI_MASTER_ARBLOST_bp 3 /* Arbitration Lost bit position. */ - -#define TWI_MASTER_BUSERR_bm 0x04 /* Bus Error bit mask. */ -#define TWI_MASTER_BUSERR_bp 2 /* Bus Error bit position. */ - -#define TWI_MASTER_BUSSTATE_gm 0x03 /* Bus State group mask. */ -#define TWI_MASTER_BUSSTATE_gp 0 /* Bus State group position. */ -#define TWI_MASTER_BUSSTATE0_bm (1<<0) /* Bus State bit 0 mask. */ -#define TWI_MASTER_BUSSTATE0_bp 0 /* Bus State bit 0 position. */ -#define TWI_MASTER_BUSSTATE1_bm (1<<1) /* Bus State bit 1 mask. */ -#define TWI_MASTER_BUSSTATE1_bp 1 /* Bus State bit 1 position. */ - -/* TWI_SLAVE.CTRLA bit masks and bit positions */ -#define TWI_SLAVE_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ -#define TWI_SLAVE_INTLVL_gp 6 /* Interrupt Level group position. */ -#define TWI_SLAVE_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ -#define TWI_SLAVE_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ -#define TWI_SLAVE_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ -#define TWI_SLAVE_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ - -#define TWI_SLAVE_DIEN_bm 0x20 /* Data Interrupt Enable bit mask. */ -#define TWI_SLAVE_DIEN_bp 5 /* Data Interrupt Enable bit position. */ - -#define TWI_SLAVE_APIEN_bm 0x10 /* Address/Stop Interrupt Enable bit mask. */ -#define TWI_SLAVE_APIEN_bp 4 /* Address/Stop Interrupt Enable bit position. */ - -#define TWI_SLAVE_ENABLE_bm 0x08 /* Enable TWI Slave bit mask. */ -#define TWI_SLAVE_ENABLE_bp 3 /* Enable TWI Slave bit position. */ - -#define TWI_SLAVE_PIEN_bm 0x04 /* Stop Interrupt Enable bit mask. */ -#define TWI_SLAVE_PIEN_bp 2 /* Stop Interrupt Enable bit position. */ - -#define TWI_SLAVE_PMEN_bm 0x02 /* Promiscuous Mode Enable bit mask. */ -#define TWI_SLAVE_PMEN_bp 1 /* Promiscuous Mode Enable bit position. */ - -#define TWI_SLAVE_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ -#define TWI_SLAVE_SMEN_bp 0 /* Smart Mode Enable bit position. */ - -/* TWI_SLAVE.CTRLB bit masks and bit positions */ -#define TWI_SLAVE_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ -#define TWI_SLAVE_ACKACT_bp 2 /* Acknowledge Action bit position. */ - -#define TWI_SLAVE_CMD_gm 0x03 /* Command group mask. */ -#define TWI_SLAVE_CMD_gp 0 /* Command group position. */ -#define TWI_SLAVE_CMD0_bm (1<<0) /* Command bit 0 mask. */ -#define TWI_SLAVE_CMD0_bp 0 /* Command bit 0 position. */ -#define TWI_SLAVE_CMD1_bm (1<<1) /* Command bit 1 mask. */ -#define TWI_SLAVE_CMD1_bp 1 /* Command bit 1 position. */ - -/* TWI_SLAVE.STATUS bit masks and bit positions */ -#define TWI_SLAVE_DIF_bm 0x80 /* Data Interrupt Flag bit mask. */ -#define TWI_SLAVE_DIF_bp 7 /* Data Interrupt Flag bit position. */ - -#define TWI_SLAVE_APIF_bm 0x40 /* Address/Stop Interrupt Flag bit mask. */ -#define TWI_SLAVE_APIF_bp 6 /* Address/Stop Interrupt Flag bit position. */ - -#define TWI_SLAVE_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ -#define TWI_SLAVE_CLKHOLD_bp 5 /* Clock Hold bit position. */ - -#define TWI_SLAVE_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ -#define TWI_SLAVE_RXACK_bp 4 /* Received Acknowledge bit position. */ - -#define TWI_SLAVE_COLL_bm 0x08 /* Collision bit mask. */ -#define TWI_SLAVE_COLL_bp 3 /* Collision bit position. */ - -#define TWI_SLAVE_BUSERR_bm 0x04 /* Bus Error bit mask. */ -#define TWI_SLAVE_BUSERR_bp 2 /* Bus Error bit position. */ - -#define TWI_SLAVE_DIR_bm 0x02 /* Read/Write Direction bit mask. */ -#define TWI_SLAVE_DIR_bp 1 /* Read/Write Direction bit position. */ - -#define TWI_SLAVE_AP_bm 0x01 /* Slave Address or Stop bit mask. */ -#define TWI_SLAVE_AP_bp 0 /* Slave Address or Stop bit position. */ - -/* TWI_SLAVE.ADDRMASK bit masks and bit positions */ -#define TWI_SLAVE_ADDRMASK_gm 0xFE /* Address Mask group mask. */ -#define TWI_SLAVE_ADDRMASK_gp 1 /* Address Mask group position. */ -#define TWI_SLAVE_ADDRMASK0_bm (1<<1) /* Address Mask bit 0 mask. */ -#define TWI_SLAVE_ADDRMASK0_bp 1 /* Address Mask bit 0 position. */ -#define TWI_SLAVE_ADDRMASK1_bm (1<<2) /* Address Mask bit 1 mask. */ -#define TWI_SLAVE_ADDRMASK1_bp 2 /* Address Mask bit 1 position. */ -#define TWI_SLAVE_ADDRMASK2_bm (1<<3) /* Address Mask bit 2 mask. */ -#define TWI_SLAVE_ADDRMASK2_bp 3 /* Address Mask bit 2 position. */ -#define TWI_SLAVE_ADDRMASK3_bm (1<<4) /* Address Mask bit 3 mask. */ -#define TWI_SLAVE_ADDRMASK3_bp 4 /* Address Mask bit 3 position. */ -#define TWI_SLAVE_ADDRMASK4_bm (1<<5) /* Address Mask bit 4 mask. */ -#define TWI_SLAVE_ADDRMASK4_bp 5 /* Address Mask bit 4 position. */ -#define TWI_SLAVE_ADDRMASK5_bm (1<<6) /* Address Mask bit 5 mask. */ -#define TWI_SLAVE_ADDRMASK5_bp 6 /* Address Mask bit 5 position. */ -#define TWI_SLAVE_ADDRMASK6_bm (1<<7) /* Address Mask bit 6 mask. */ -#define TWI_SLAVE_ADDRMASK6_bp 7 /* Address Mask bit 6 position. */ - -#define TWI_SLAVE_ADDREN_bm 0x01 /* Address Enable bit mask. */ -#define TWI_SLAVE_ADDREN_bp 0 /* Address Enable bit position. */ - -/* TWI.CTRL bit masks and bit positions */ -#define TWI_SDAHOLD_gm 0x06 /* SDA Hold Time Enable group mask. */ -#define TWI_SDAHOLD_gp 1 /* SDA Hold Time Enable group position. */ -#define TWI_SDAHOLD0_bm (1<<1) /* SDA Hold Time Enable bit 0 mask. */ -#define TWI_SDAHOLD0_bp 1 /* SDA Hold Time Enable bit 0 position. */ -#define TWI_SDAHOLD1_bm (1<<2) /* SDA Hold Time Enable bit 1 mask. */ -#define TWI_SDAHOLD1_bp 2 /* SDA Hold Time Enable bit 1 position. */ - -#define TWI_EDIEN_bm 0x01 /* External Driver Interface Enable bit mask. */ -#define TWI_EDIEN_bp 0 /* External Driver Interface Enable bit position. */ - -/* USB - USB */ -/* USB_EP.STATUS bit masks and bit positions */ -#define USB_EP_STALLF_bm 0x80 /* Endpoint Stall Flag bit mask. */ -#define USB_EP_STALLF_bp 7 /* Endpoint Stall Flag bit position. */ - -#define USB_EP_CRC_bm 0x80 /* CRC Error Flag bit mask. */ -#define USB_EP_CRC_bp 7 /* CRC Error Flag bit position. */ - -#define USB_EP_UNF_bm 0x40 /* Underflow Enpoint FLag bit mask. */ -#define USB_EP_UNF_bp 6 /* Underflow Enpoint FLag bit position. */ - -#define USB_EP_OVF_bm 0x40 /* Overflow Enpoint Flag for Output Endpoints bit mask. */ -#define USB_EP_OVF_bp 6 /* Overflow Enpoint Flag for Output Endpoints bit position. */ - -#define USB_EP_TRNCOMPL0_bm 0x20 /* Transaction Complete 0 Flag bit mask. */ -#define USB_EP_TRNCOMPL0_bp 5 /* Transaction Complete 0 Flag bit position. */ - -#define USB_EP_TRNCOMPL1_bm 0x10 /* Transaction Complete 1 Flag bit mask. */ -#define USB_EP_TRNCOMPL1_bp 4 /* Transaction Complete 1 Flag bit position. */ - -#define USB_EP_SETUP_bm 0x10 /* SETUP Transaction Complete Flag bit mask. */ -#define USB_EP_SETUP_bp 4 /* SETUP Transaction Complete Flag bit position. */ - -#define USB_EP_BANK_bm 0x08 /* Bank Select bit mask. */ -#define USB_EP_BANK_bp 3 /* Bank Select bit position. */ - -#define USB_EP_BUSNACK1_bm 0x04 /* Data Buffer 1 Not Acknowledge bit mask. */ -#define USB_EP_BUSNACK1_bp 2 /* Data Buffer 1 Not Acknowledge bit position. */ - -#define USB_EP_BUSNACK0_bm 0x02 /* Data Buffer 0 Not Acknowledge bit mask. */ -#define USB_EP_BUSNACK0_bp 1 /* Data Buffer 0 Not Acknowledge bit position. */ - -#define USB_EP_TOGGLE_bm 0x01 /* Data Toggle bit mask. */ -#define USB_EP_TOGGLE_bp 0 /* Data Toggle bit position. */ - -/* USB_EP.CTRL bit masks and bit positions */ -#define USB_EP_TYPE_gm 0xC0 /* Endpoint Type group mask. */ -#define USB_EP_TYPE_gp 6 /* Endpoint Type group position. */ -#define USB_EP_TYPE0_bm (1<<6) /* Endpoint Type bit 0 mask. */ -#define USB_EP_TYPE0_bp 6 /* Endpoint Type bit 0 position. */ -#define USB_EP_TYPE1_bm (1<<7) /* Endpoint Type bit 1 mask. */ -#define USB_EP_TYPE1_bp 7 /* Endpoint Type bit 1 position. */ - -#define USB_EP_MULTIPKT_bm 0x20 /* Multi Packet Transfer Enable bit mask. */ -#define USB_EP_MULTIPKT_bp 5 /* Multi Packet Transfer Enable bit position. */ - -#define USB_EP_PINGPONG_bm 0x10 /* Ping-Pong Enable bit mask. */ -#define USB_EP_PINGPONG_bp 4 /* Ping-Pong Enable bit position. */ - -#define USB_EP_INTDSBL_bm 0x08 /* Interrupt Disable bit mask. */ -#define USB_EP_INTDSBL_bp 3 /* Interrupt Disable bit position. */ - -#define USB_EP_STALL_bm 0x04 /* Data Stall bit mask. */ -#define USB_EP_STALL_bp 2 /* Data Stall bit position. */ - -#define USB_EP_BUFSIZE_gm 0x07 /* Data Buffer Size group mask. */ -#define USB_EP_BUFSIZE_gp 0 /* Data Buffer Size group position. */ -#define USB_EP_BUFSIZE0_bm (1<<0) /* Data Buffer Size bit 0 mask. */ -#define USB_EP_BUFSIZE0_bp 0 /* Data Buffer Size bit 0 position. */ -#define USB_EP_BUFSIZE1_bm (1<<1) /* Data Buffer Size bit 1 mask. */ -#define USB_EP_BUFSIZE1_bp 1 /* Data Buffer Size bit 1 position. */ -#define USB_EP_BUFSIZE2_bm (1<<2) /* Data Buffer Size bit 2 mask. */ -#define USB_EP_BUFSIZE2_bp 2 /* Data Buffer Size bit 2 position. */ - -/* USB_EP.CNT bit masks and bit positions */ -#define USB_EP_ZLP_bm 0x8000 /* Zero Length Packet bit mask. */ -#define USB_EP_ZLP_bp 15 /* Zero Length Packet bit position. */ - -/* USB.CTRLA bit masks and bit positions */ -#define USB_ENABLE_bm 0x80 /* USB Enable bit mask. */ -#define USB_ENABLE_bp 7 /* USB Enable bit position. */ - -#define USB_SPEED_bm 0x40 /* Speed Select bit mask. */ -#define USB_SPEED_bp 6 /* Speed Select bit position. */ - -#define USB_FIFOEN_bm 0x20 /* USB FIFO Enable bit mask. */ -#define USB_FIFOEN_bp 5 /* USB FIFO Enable bit position. */ - -#define USB_STFRNUM_bm 0x10 /* Store Frame Number Enable bit mask. */ -#define USB_STFRNUM_bp 4 /* Store Frame Number Enable bit position. */ - -#define USB_MAXEP_gm 0x0F /* Maximum Endpoint Addresses group mask. */ -#define USB_MAXEP_gp 0 /* Maximum Endpoint Addresses group position. */ -#define USB_MAXEP0_bm (1<<0) /* Maximum Endpoint Addresses bit 0 mask. */ -#define USB_MAXEP0_bp 0 /* Maximum Endpoint Addresses bit 0 position. */ -#define USB_MAXEP1_bm (1<<1) /* Maximum Endpoint Addresses bit 1 mask. */ -#define USB_MAXEP1_bp 1 /* Maximum Endpoint Addresses bit 1 position. */ -#define USB_MAXEP2_bm (1<<2) /* Maximum Endpoint Addresses bit 2 mask. */ -#define USB_MAXEP2_bp 2 /* Maximum Endpoint Addresses bit 2 position. */ -#define USB_MAXEP3_bm (1<<3) /* Maximum Endpoint Addresses bit 3 mask. */ -#define USB_MAXEP3_bp 3 /* Maximum Endpoint Addresses bit 3 position. */ - -/* USB.CTRLB bit masks and bit positions */ -#define USB_PULLRST_bm 0x10 /* Pull during Reset bit mask. */ -#define USB_PULLRST_bp 4 /* Pull during Reset bit position. */ - -#define USB_RWAKEUP_bm 0x04 /* Remote Wake-up bit mask. */ -#define USB_RWAKEUP_bp 2 /* Remote Wake-up bit position. */ - -#define USB_GNACK_bm 0x02 /* Global NACK bit mask. */ -#define USB_GNACK_bp 1 /* Global NACK bit position. */ - -#define USB_ATTACH_bm 0x01 /* Attach bit mask. */ -#define USB_ATTACH_bp 0 /* Attach bit position. */ - -/* USB.STATUS bit masks and bit positions */ -#define USB_URESUME_bm 0x08 /* Upstream Resume bit mask. */ -#define USB_URESUME_bp 3 /* Upstream Resume bit position. */ - -#define USB_RESUME_bm 0x04 /* Resume bit mask. */ -#define USB_RESUME_bp 2 /* Resume bit position. */ - -#define USB_SUSPEND_bm 0x02 /* Bus Suspended bit mask. */ -#define USB_SUSPEND_bp 1 /* Bus Suspended bit position. */ - -#define USB_BUSRST_bm 0x01 /* Bus Reset bit mask. */ -#define USB_BUSRST_bp 0 /* Bus Reset bit position. */ - -/* USB.ADDR bit masks and bit positions */ -#define USB_ADDR_gm 0x7F /* Device Address group mask. */ -#define USB_ADDR_gp 0 /* Device Address group position. */ -#define USB_ADDR0_bm (1<<0) /* Device Address bit 0 mask. */ -#define USB_ADDR0_bp 0 /* Device Address bit 0 position. */ -#define USB_ADDR1_bm (1<<1) /* Device Address bit 1 mask. */ -#define USB_ADDR1_bp 1 /* Device Address bit 1 position. */ -#define USB_ADDR2_bm (1<<2) /* Device Address bit 2 mask. */ -#define USB_ADDR2_bp 2 /* Device Address bit 2 position. */ -#define USB_ADDR3_bm (1<<3) /* Device Address bit 3 mask. */ -#define USB_ADDR3_bp 3 /* Device Address bit 3 position. */ -#define USB_ADDR4_bm (1<<4) /* Device Address bit 4 mask. */ -#define USB_ADDR4_bp 4 /* Device Address bit 4 position. */ -#define USB_ADDR5_bm (1<<5) /* Device Address bit 5 mask. */ -#define USB_ADDR5_bp 5 /* Device Address bit 5 position. */ -#define USB_ADDR6_bm (1<<6) /* Device Address bit 6 mask. */ -#define USB_ADDR6_bp 6 /* Device Address bit 6 position. */ - -/* USB.FIFOWP bit masks and bit positions */ -#define USB_FIFOWP_gm 0x1F /* FIFO Write Pointer group mask. */ -#define USB_FIFOWP_gp 0 /* FIFO Write Pointer group position. */ -#define USB_FIFOWP0_bm (1<<0) /* FIFO Write Pointer bit 0 mask. */ -#define USB_FIFOWP0_bp 0 /* FIFO Write Pointer bit 0 position. */ -#define USB_FIFOWP1_bm (1<<1) /* FIFO Write Pointer bit 1 mask. */ -#define USB_FIFOWP1_bp 1 /* FIFO Write Pointer bit 1 position. */ -#define USB_FIFOWP2_bm (1<<2) /* FIFO Write Pointer bit 2 mask. */ -#define USB_FIFOWP2_bp 2 /* FIFO Write Pointer bit 2 position. */ -#define USB_FIFOWP3_bm (1<<3) /* FIFO Write Pointer bit 3 mask. */ -#define USB_FIFOWP3_bp 3 /* FIFO Write Pointer bit 3 position. */ -#define USB_FIFOWP4_bm (1<<4) /* FIFO Write Pointer bit 4 mask. */ -#define USB_FIFOWP4_bp 4 /* FIFO Write Pointer bit 4 position. */ - -/* USB.FIFORP bit masks and bit positions */ -#define USB_FIFORP_gm 0x1F /* FIFO Read Pointer group mask. */ -#define USB_FIFORP_gp 0 /* FIFO Read Pointer group position. */ -#define USB_FIFORP0_bm (1<<0) /* FIFO Read Pointer bit 0 mask. */ -#define USB_FIFORP0_bp 0 /* FIFO Read Pointer bit 0 position. */ -#define USB_FIFORP1_bm (1<<1) /* FIFO Read Pointer bit 1 mask. */ -#define USB_FIFORP1_bp 1 /* FIFO Read Pointer bit 1 position. */ -#define USB_FIFORP2_bm (1<<2) /* FIFO Read Pointer bit 2 mask. */ -#define USB_FIFORP2_bp 2 /* FIFO Read Pointer bit 2 position. */ -#define USB_FIFORP3_bm (1<<3) /* FIFO Read Pointer bit 3 mask. */ -#define USB_FIFORP3_bp 3 /* FIFO Read Pointer bit 3 position. */ -#define USB_FIFORP4_bm (1<<4) /* FIFO Read Pointer bit 4 mask. */ -#define USB_FIFORP4_bp 4 /* FIFO Read Pointer bit 4 position. */ - -/* USB.INTCTRLA bit masks and bit positions */ -#define USB_SOFIE_bm 0x80 /* Start Of Frame Interrupt Enable bit mask. */ -#define USB_SOFIE_bp 7 /* Start Of Frame Interrupt Enable bit position. */ - -#define USB_BUSEVIE_bm 0x40 /* Bus Event Interrupt Enable bit mask. */ -#define USB_BUSEVIE_bp 6 /* Bus Event Interrupt Enable bit position. */ - -#define USB_BUSERRIE_bm 0x20 /* Bus Error Interrupt Enable bit mask. */ -#define USB_BUSERRIE_bp 5 /* Bus Error Interrupt Enable bit position. */ - -#define USB_STALLIE_bm 0x10 /* STALL Interrupt Enable bit mask. */ -#define USB_STALLIE_bp 4 /* STALL Interrupt Enable bit position. */ - -#define USB_INTLVL_gm 0x03 /* Interrupt Level group mask. */ -#define USB_INTLVL_gp 0 /* Interrupt Level group position. */ -#define USB_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */ -#define USB_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */ -#define USB_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ -#define USB_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */ - -/* USB.INTCTRLB bit masks and bit positions */ -#define USB_TRNIE_bm 0x02 /* Transaction Complete Interrupt Enable bit mask. */ -#define USB_TRNIE_bp 1 /* Transaction Complete Interrupt Enable bit position. */ - -#define USB_SETUPIE_bm 0x01 /* SETUP Transaction Complete Interrupt Enable bit mask. */ -#define USB_SETUPIE_bp 0 /* SETUP Transaction Complete Interrupt Enable bit position. */ - -/* USB.INTFLAGSACLR bit masks and bit positions */ -#define USB_SOFIF_bm 0x80 /* Start Of Frame Interrupt Flag bit mask. */ -#define USB_SOFIF_bp 7 /* Start Of Frame Interrupt Flag bit position. */ - -#define USB_SUSPENDIF_bm 0x40 /* Suspend Interrupt Flag bit mask. */ -#define USB_SUSPENDIF_bp 6 /* Suspend Interrupt Flag bit position. */ - -#define USB_RESUMEIF_bm 0x20 /* Resume Interrupt Flag bit mask. */ -#define USB_RESUMEIF_bp 5 /* Resume Interrupt Flag bit position. */ - -#define USB_RSTIF_bm 0x10 /* Reset Interrupt Flag bit mask. */ -#define USB_RSTIF_bp 4 /* Reset Interrupt Flag bit position. */ - -#define USB_CRCIF_bm 0x08 /* Isochronous CRC Error Interrupt Flag bit mask. */ -#define USB_CRCIF_bp 3 /* Isochronous CRC Error Interrupt Flag bit position. */ - -#define USB_UNFIF_bm 0x04 /* Underflow Interrupt Flag bit mask. */ -#define USB_UNFIF_bp 2 /* Underflow Interrupt Flag bit position. */ - -#define USB_OVFIF_bm 0x02 /* Overflow Interrupt Flag bit mask. */ -#define USB_OVFIF_bp 1 /* Overflow Interrupt Flag bit position. */ - -#define USB_STALLIF_bm 0x01 /* STALL Interrupt Flag bit mask. */ -#define USB_STALLIF_bp 0 /* STALL Interrupt Flag bit position. */ - -/* USB.INTFLAGSASET bit masks and bit positions */ -/* USB_SOFIF Predefined. */ -/* USB_SOFIF Predefined. */ - -/* USB_SUSPENDIF Predefined. */ -/* USB_SUSPENDIF Predefined. */ - -/* USB_RESUMEIF Predefined. */ -/* USB_RESUMEIF Predefined. */ - -/* USB_RSTIF Predefined. */ -/* USB_RSTIF Predefined. */ - -/* USB_CRCIF Predefined. */ -/* USB_CRCIF Predefined. */ - -/* USB_UNFIF Predefined. */ -/* USB_UNFIF Predefined. */ - -/* USB_OVFIF Predefined. */ -/* USB_OVFIF Predefined. */ - -/* USB_STALLIF Predefined. */ -/* USB_STALLIF Predefined. */ - -/* USB.INTFLAGSBCLR bit masks and bit positions */ -#define USB_TRNIF_bm 0x02 /* Transaction Complete Interrupt Flag bit mask. */ -#define USB_TRNIF_bp 1 /* Transaction Complete Interrupt Flag bit position. */ - -#define USB_SETUPIF_bm 0x01 /* SETUP Transaction Complete Interrupt Flag bit mask. */ -#define USB_SETUPIF_bp 0 /* SETUP Transaction Complete Interrupt Flag bit position. */ - -/* USB.INTFLAGSBSET bit masks and bit positions */ -/* USB_TRNIF Predefined. */ -/* USB_TRNIF Predefined. */ - -/* USB_SETUPIF Predefined. */ -/* USB_SETUPIF Predefined. */ - -/* PORT - I/O Port Configuration */ -/* PORT.INTCTRL bit masks and bit positions */ -#define PORT_INT1LVL_gm 0x0C /* Port Interrupt 1 Level group mask. */ -#define PORT_INT1LVL_gp 2 /* Port Interrupt 1 Level group position. */ -#define PORT_INT1LVL0_bm (1<<2) /* Port Interrupt 1 Level bit 0 mask. */ -#define PORT_INT1LVL0_bp 2 /* Port Interrupt 1 Level bit 0 position. */ -#define PORT_INT1LVL1_bm (1<<3) /* Port Interrupt 1 Level bit 1 mask. */ -#define PORT_INT1LVL1_bp 3 /* Port Interrupt 1 Level bit 1 position. */ - -#define PORT_INT0LVL_gm 0x03 /* Port Interrupt 0 Level group mask. */ -#define PORT_INT0LVL_gp 0 /* Port Interrupt 0 Level group position. */ -#define PORT_INT0LVL0_bm (1<<0) /* Port Interrupt 0 Level bit 0 mask. */ -#define PORT_INT0LVL0_bp 0 /* Port Interrupt 0 Level bit 0 position. */ -#define PORT_INT0LVL1_bm (1<<1) /* Port Interrupt 0 Level bit 1 mask. */ -#define PORT_INT0LVL1_bp 1 /* Port Interrupt 0 Level bit 1 position. */ - -/* PORT.INTFLAGS bit masks and bit positions */ -#define PORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ -#define PORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ - -#define PORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ -#define PORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ - -/* PORT.REMAP bit masks and bit positions */ -#define PORT_SPI_bm 0x20 /* SPI bit mask. */ -#define PORT_SPI_bp 5 /* SPI bit position. */ - -#define PORT_USART0_bm 0x10 /* USART0 bit mask. */ -#define PORT_USART0_bp 4 /* USART0 bit position. */ - -#define PORT_TC0D_bm 0x08 /* Timer/Counter 0 Output Compare D bit mask. */ -#define PORT_TC0D_bp 3 /* Timer/Counter 0 Output Compare D bit position. */ - -#define PORT_TC0C_bm 0x04 /* Timer/Counter 0 Output Compare C bit mask. */ -#define PORT_TC0C_bp 2 /* Timer/Counter 0 Output Compare C bit position. */ - -#define PORT_TC0B_bm 0x02 /* Timer/Counter 0 Output Compare B bit mask. */ -#define PORT_TC0B_bp 1 /* Timer/Counter 0 Output Compare B bit position. */ - -#define PORT_TC0A_bm 0x01 /* Timer/Counter 0 Output Compare A bit mask. */ -#define PORT_TC0A_bp 0 /* Timer/Counter 0 Output Compare A bit position. */ - -/* PORT.PIN0CTRL bit masks and bit positions */ -#define PORT_SRLEN_bm 0x80 /* Slew Rate Enable bit mask. */ -#define PORT_SRLEN_bp 7 /* Slew Rate Enable bit position. */ - -#define PORT_INVEN_bm 0x40 /* Inverted I/O Enable bit mask. */ -#define PORT_INVEN_bp 6 /* Inverted I/O Enable bit position. */ - -#define PORT_OPC_gm 0x38 /* Output/Pull Configuration group mask. */ -#define PORT_OPC_gp 3 /* Output/Pull Configuration group position. */ -#define PORT_OPC0_bm (1<<3) /* Output/Pull Configuration bit 0 mask. */ -#define PORT_OPC0_bp 3 /* Output/Pull Configuration bit 0 position. */ -#define PORT_OPC1_bm (1<<4) /* Output/Pull Configuration bit 1 mask. */ -#define PORT_OPC1_bp 4 /* Output/Pull Configuration bit 1 position. */ -#define PORT_OPC2_bm (1<<5) /* Output/Pull Configuration bit 2 mask. */ -#define PORT_OPC2_bp 5 /* Output/Pull Configuration bit 2 position. */ - -#define PORT_ISC_gm 0x07 /* Input/Sense Configuration group mask. */ -#define PORT_ISC_gp 0 /* Input/Sense Configuration group position. */ -#define PORT_ISC0_bm (1<<0) /* Input/Sense Configuration bit 0 mask. */ -#define PORT_ISC0_bp 0 /* Input/Sense Configuration bit 0 position. */ -#define PORT_ISC1_bm (1<<1) /* Input/Sense Configuration bit 1 mask. */ -#define PORT_ISC1_bp 1 /* Input/Sense Configuration bit 1 position. */ -#define PORT_ISC2_bm (1<<2) /* Input/Sense Configuration bit 2 mask. */ -#define PORT_ISC2_bp 2 /* Input/Sense Configuration bit 2 position. */ - -/* PORT.PIN1CTRL bit masks and bit positions */ -/* PORT_SRLEN Predefined. */ -/* PORT_SRLEN Predefined. */ - -/* PORT_INVEN Predefined. */ -/* PORT_INVEN Predefined. */ - -/* PORT_OPC Predefined. */ -/* PORT_OPC Predefined. */ - -/* PORT_ISC Predefined. */ -/* PORT_ISC Predefined. */ - -/* PORT.PIN2CTRL bit masks and bit positions */ -/* PORT_SRLEN Predefined. */ -/* PORT_SRLEN Predefined. */ - -/* PORT_INVEN Predefined. */ -/* PORT_INVEN Predefined. */ - -/* PORT_OPC Predefined. */ -/* PORT_OPC Predefined. */ - -/* PORT_ISC Predefined. */ -/* PORT_ISC Predefined. */ - -/* PORT.PIN3CTRL bit masks and bit positions */ -/* PORT_SRLEN Predefined. */ -/* PORT_SRLEN Predefined. */ - -/* PORT_INVEN Predefined. */ -/* PORT_INVEN Predefined. */ - -/* PORT_OPC Predefined. */ -/* PORT_OPC Predefined. */ - -/* PORT_ISC Predefined. */ -/* PORT_ISC Predefined. */ - -/* PORT.PIN4CTRL bit masks and bit positions */ -/* PORT_SRLEN Predefined. */ -/* PORT_SRLEN Predefined. */ - -/* PORT_INVEN Predefined. */ -/* PORT_INVEN Predefined. */ - -/* PORT_OPC Predefined. */ -/* PORT_OPC Predefined. */ - -/* PORT_ISC Predefined. */ -/* PORT_ISC Predefined. */ - -/* PORT.PIN5CTRL bit masks and bit positions */ -/* PORT_SRLEN Predefined. */ -/* PORT_SRLEN Predefined. */ - -/* PORT_INVEN Predefined. */ -/* PORT_INVEN Predefined. */ - -/* PORT_OPC Predefined. */ -/* PORT_OPC Predefined. */ - -/* PORT_ISC Predefined. */ -/* PORT_ISC Predefined. */ - -/* PORT.PIN6CTRL bit masks and bit positions */ -/* PORT_SRLEN Predefined. */ -/* PORT_SRLEN Predefined. */ - -/* PORT_INVEN Predefined. */ -/* PORT_INVEN Predefined. */ - -/* PORT_OPC Predefined. */ -/* PORT_OPC Predefined. */ - -/* PORT_ISC Predefined. */ -/* PORT_ISC Predefined. */ - -/* PORT.PIN7CTRL bit masks and bit positions */ -/* PORT_SRLEN Predefined. */ -/* PORT_SRLEN Predefined. */ - -/* PORT_INVEN Predefined. */ -/* PORT_INVEN Predefined. */ - -/* PORT_OPC Predefined. */ -/* PORT_OPC Predefined. */ - -/* PORT_ISC Predefined. */ -/* PORT_ISC Predefined. */ - -/* TC - 16-bit Timer/Counter With PWM */ -/* TC0.CTRLA bit masks and bit positions */ -#define TC0_CLKSEL_gm 0x0F /* Clock Selection group mask. */ -#define TC0_CLKSEL_gp 0 /* Clock Selection group position. */ -#define TC0_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ -#define TC0_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ -#define TC0_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ -#define TC0_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ -#define TC0_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ -#define TC0_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ -#define TC0_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ -#define TC0_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ - -/* TC0.CTRLB bit masks and bit positions */ -#define TC0_CCDEN_bm 0x80 /* Compare or Capture D Enable bit mask. */ -#define TC0_CCDEN_bp 7 /* Compare or Capture D Enable bit position. */ - -#define TC0_CCCEN_bm 0x40 /* Compare or Capture C Enable bit mask. */ -#define TC0_CCCEN_bp 6 /* Compare or Capture C Enable bit position. */ - -#define TC0_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ -#define TC0_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ - -#define TC0_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ -#define TC0_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ - -#define TC0_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ -#define TC0_WGMODE_gp 0 /* Waveform generation mode group position. */ -#define TC0_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ -#define TC0_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ -#define TC0_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ -#define TC0_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ -#define TC0_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ -#define TC0_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ - -/* TC0.CTRLC bit masks and bit positions */ -#define TC0_CMPD_bm 0x08 /* Compare D Output Value bit mask. */ -#define TC0_CMPD_bp 3 /* Compare D Output Value bit position. */ - -#define TC0_CMPC_bm 0x04 /* Compare C Output Value bit mask. */ -#define TC0_CMPC_bp 2 /* Compare C Output Value bit position. */ - -#define TC0_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ -#define TC0_CMPB_bp 1 /* Compare B Output Value bit position. */ - -#define TC0_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ -#define TC0_CMPA_bp 0 /* Compare A Output Value bit position. */ - -/* TC0.CTRLD bit masks and bit positions */ -#define TC0_EVACT_gm 0xE0 /* Event Action group mask. */ -#define TC0_EVACT_gp 5 /* Event Action group position. */ -#define TC0_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ -#define TC0_EVACT0_bp 5 /* Event Action bit 0 position. */ -#define TC0_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ -#define TC0_EVACT1_bp 6 /* Event Action bit 1 position. */ -#define TC0_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ -#define TC0_EVACT2_bp 7 /* Event Action bit 2 position. */ - -#define TC0_EVDLY_bm 0x10 /* Event Delay bit mask. */ -#define TC0_EVDLY_bp 4 /* Event Delay bit position. */ - -#define TC0_EVSEL_gm 0x0F /* Event Source Select group mask. */ -#define TC0_EVSEL_gp 0 /* Event Source Select group position. */ -#define TC0_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ -#define TC0_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ -#define TC0_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ -#define TC0_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ -#define TC0_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ -#define TC0_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ -#define TC0_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ -#define TC0_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ - -/* TC0.CTRLE bit masks and bit positions */ -#define TC0_BYTEM_gm 0x03 /* Byte Mode group mask. */ -#define TC0_BYTEM_gp 0 /* Byte Mode group position. */ -#define TC0_BYTEM0_bm (1<<0) /* Byte Mode bit 0 mask. */ -#define TC0_BYTEM0_bp 0 /* Byte Mode bit 0 position. */ -#define TC0_BYTEM1_bm (1<<1) /* Byte Mode bit 1 mask. */ -#define TC0_BYTEM1_bp 1 /* Byte Mode bit 1 position. */ - -/* TC0.INTCTRLA bit masks and bit positions */ -#define TC0_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ -#define TC0_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ -#define TC0_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ -#define TC0_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ -#define TC0_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ -#define TC0_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ - -#define TC0_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ -#define TC0_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ -#define TC0_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ -#define TC0_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ -#define TC0_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ -#define TC0_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ - -/* TC0.INTCTRLB bit masks and bit positions */ -#define TC0_CCDINTLVL_gm 0xC0 /* Compare or Capture D Interrupt Level group mask. */ -#define TC0_CCDINTLVL_gp 6 /* Compare or Capture D Interrupt Level group position. */ -#define TC0_CCDINTLVL0_bm (1<<6) /* Compare or Capture D Interrupt Level bit 0 mask. */ -#define TC0_CCDINTLVL0_bp 6 /* Compare or Capture D Interrupt Level bit 0 position. */ -#define TC0_CCDINTLVL1_bm (1<<7) /* Compare or Capture D Interrupt Level bit 1 mask. */ -#define TC0_CCDINTLVL1_bp 7 /* Compare or Capture D Interrupt Level bit 1 position. */ - -#define TC0_CCCINTLVL_gm 0x30 /* Compare or Capture C Interrupt Level group mask. */ -#define TC0_CCCINTLVL_gp 4 /* Compare or Capture C Interrupt Level group position. */ -#define TC0_CCCINTLVL0_bm (1<<4) /* Compare or Capture C Interrupt Level bit 0 mask. */ -#define TC0_CCCINTLVL0_bp 4 /* Compare or Capture C Interrupt Level bit 0 position. */ -#define TC0_CCCINTLVL1_bm (1<<5) /* Compare or Capture C Interrupt Level bit 1 mask. */ -#define TC0_CCCINTLVL1_bp 5 /* Compare or Capture C Interrupt Level bit 1 position. */ - -#define TC0_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ -#define TC0_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ -#define TC0_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ -#define TC0_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ -#define TC0_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ -#define TC0_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ - -#define TC0_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ -#define TC0_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ -#define TC0_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ -#define TC0_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ -#define TC0_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ -#define TC0_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ - -/* TC0.CTRLFCLR bit masks and bit positions */ -#define TC0_CMD_gm 0x0C /* Command group mask. */ -#define TC0_CMD_gp 2 /* Command group position. */ -#define TC0_CMD0_bm (1<<2) /* Command bit 0 mask. */ -#define TC0_CMD0_bp 2 /* Command bit 0 position. */ -#define TC0_CMD1_bm (1<<3) /* Command bit 1 mask. */ -#define TC0_CMD1_bp 3 /* Command bit 1 position. */ - -#define TC0_LUPD_bm 0x02 /* Lock Update bit mask. */ -#define TC0_LUPD_bp 1 /* Lock Update bit position. */ - -#define TC0_DIR_bm 0x01 /* Direction bit mask. */ -#define TC0_DIR_bp 0 /* Direction bit position. */ - -/* TC0.CTRLFSET bit masks and bit positions */ -/* TC0_CMD Predefined. */ -/* TC0_CMD Predefined. */ - -/* TC0_LUPD Predefined. */ -/* TC0_LUPD Predefined. */ - -/* TC0_DIR Predefined. */ -/* TC0_DIR Predefined. */ - -/* TC0.CTRLGCLR bit masks and bit positions */ -#define TC0_CCDBV_bm 0x10 /* Compare or Capture D Buffer Valid bit mask. */ -#define TC0_CCDBV_bp 4 /* Compare or Capture D Buffer Valid bit position. */ - -#define TC0_CCCBV_bm 0x08 /* Compare or Capture C Buffer Valid bit mask. */ -#define TC0_CCCBV_bp 3 /* Compare or Capture C Buffer Valid bit position. */ - -#define TC0_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ -#define TC0_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ - -#define TC0_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ -#define TC0_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ - -#define TC0_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ -#define TC0_PERBV_bp 0 /* Period Buffer Valid bit position. */ - -/* TC0.CTRLGSET bit masks and bit positions */ -/* TC0_CCDBV Predefined. */ -/* TC0_CCDBV Predefined. */ - -/* TC0_CCCBV Predefined. */ -/* TC0_CCCBV Predefined. */ - -/* TC0_CCBBV Predefined. */ -/* TC0_CCBBV Predefined. */ - -/* TC0_CCABV Predefined. */ -/* TC0_CCABV Predefined. */ - -/* TC0_PERBV Predefined. */ -/* TC0_PERBV Predefined. */ - -/* TC0.INTFLAGS bit masks and bit positions */ -#define TC0_CCDIF_bm 0x80 /* Compare or Capture D Interrupt Flag bit mask. */ -#define TC0_CCDIF_bp 7 /* Compare or Capture D Interrupt Flag bit position. */ - -#define TC0_CCCIF_bm 0x40 /* Compare or Capture C Interrupt Flag bit mask. */ -#define TC0_CCCIF_bp 6 /* Compare or Capture C Interrupt Flag bit position. */ - -#define TC0_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ -#define TC0_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ - -#define TC0_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ -#define TC0_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ - -#define TC0_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ -#define TC0_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ - -#define TC0_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ -#define TC0_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ - -/* TC1.CTRLA bit masks and bit positions */ -#define TC1_CLKSEL_gm 0x0F /* Clock Selection group mask. */ -#define TC1_CLKSEL_gp 0 /* Clock Selection group position. */ -#define TC1_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ -#define TC1_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ -#define TC1_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ -#define TC1_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ -#define TC1_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ -#define TC1_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ -#define TC1_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ -#define TC1_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ - -/* TC1.CTRLB bit masks and bit positions */ -#define TC1_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ -#define TC1_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ - -#define TC1_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ -#define TC1_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ - -#define TC1_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ -#define TC1_WGMODE_gp 0 /* Waveform generation mode group position. */ -#define TC1_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ -#define TC1_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ -#define TC1_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ -#define TC1_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ -#define TC1_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ -#define TC1_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ - -/* TC1.CTRLC bit masks and bit positions */ -#define TC1_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ -#define TC1_CMPB_bp 1 /* Compare B Output Value bit position. */ - -#define TC1_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ -#define TC1_CMPA_bp 0 /* Compare A Output Value bit position. */ - -/* TC1.CTRLD bit masks and bit positions */ -#define TC1_EVACT_gm 0xE0 /* Event Action group mask. */ -#define TC1_EVACT_gp 5 /* Event Action group position. */ -#define TC1_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ -#define TC1_EVACT0_bp 5 /* Event Action bit 0 position. */ -#define TC1_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ -#define TC1_EVACT1_bp 6 /* Event Action bit 1 position. */ -#define TC1_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ -#define TC1_EVACT2_bp 7 /* Event Action bit 2 position. */ - -#define TC1_EVDLY_bm 0x10 /* Event Delay bit mask. */ -#define TC1_EVDLY_bp 4 /* Event Delay bit position. */ - -#define TC1_EVSEL_gm 0x0F /* Event Source Select group mask. */ -#define TC1_EVSEL_gp 0 /* Event Source Select group position. */ -#define TC1_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ -#define TC1_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ -#define TC1_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ -#define TC1_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ -#define TC1_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ -#define TC1_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ -#define TC1_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ -#define TC1_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ - -/* TC1.CTRLE bit masks and bit positions */ -#define TC1_BYTEM_bm 0x01 /* Byte Mode bit mask. */ -#define TC1_BYTEM_bp 0 /* Byte Mode bit position. */ - -/* TC1.INTCTRLA bit masks and bit positions */ -#define TC1_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ -#define TC1_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ -#define TC1_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ -#define TC1_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ -#define TC1_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ -#define TC1_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ - -#define TC1_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ -#define TC1_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ -#define TC1_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ -#define TC1_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ -#define TC1_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ -#define TC1_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ - -/* TC1.INTCTRLB bit masks and bit positions */ -#define TC1_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ -#define TC1_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ -#define TC1_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ -#define TC1_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ -#define TC1_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ -#define TC1_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ - -#define TC1_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ -#define TC1_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ -#define TC1_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ -#define TC1_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ -#define TC1_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ -#define TC1_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ - -/* TC1.CTRLFCLR bit masks and bit positions */ -#define TC1_CMD_gm 0x0C /* Command group mask. */ -#define TC1_CMD_gp 2 /* Command group position. */ -#define TC1_CMD0_bm (1<<2) /* Command bit 0 mask. */ -#define TC1_CMD0_bp 2 /* Command bit 0 position. */ -#define TC1_CMD1_bm (1<<3) /* Command bit 1 mask. */ -#define TC1_CMD1_bp 3 /* Command bit 1 position. */ - -#define TC1_LUPD_bm 0x02 /* Lock Update bit mask. */ -#define TC1_LUPD_bp 1 /* Lock Update bit position. */ - -#define TC1_DIR_bm 0x01 /* Direction bit mask. */ -#define TC1_DIR_bp 0 /* Direction bit position. */ - -/* TC1.CTRLFSET bit masks and bit positions */ -/* TC1_CMD Predefined. */ -/* TC1_CMD Predefined. */ - -/* TC1_LUPD Predefined. */ -/* TC1_LUPD Predefined. */ - -/* TC1_DIR Predefined. */ -/* TC1_DIR Predefined. */ - -/* TC1.CTRLGCLR bit masks and bit positions */ -#define TC1_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ -#define TC1_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ - -#define TC1_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ -#define TC1_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ - -#define TC1_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ -#define TC1_PERBV_bp 0 /* Period Buffer Valid bit position. */ - -/* TC1.CTRLGSET bit masks and bit positions */ -/* TC1_CCBBV Predefined. */ -/* TC1_CCBBV Predefined. */ - -/* TC1_CCABV Predefined. */ -/* TC1_CCABV Predefined. */ - -/* TC1_PERBV Predefined. */ -/* TC1_PERBV Predefined. */ - -/* TC1.INTFLAGS bit masks and bit positions */ -#define TC1_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ -#define TC1_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ - -#define TC1_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ -#define TC1_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ - -#define TC1_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ -#define TC1_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ - -#define TC1_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ -#define TC1_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ - -/* AWEX - Timer/Counter Advanced Waveform Extension */ -/* AWEX.CTRL bit masks and bit positions */ -#define AWEX_PGM_bm 0x20 /* Pattern Generation Mode bit mask. */ -#define AWEX_PGM_bp 5 /* Pattern Generation Mode bit position. */ - -#define AWEX_CWCM_bm 0x10 /* Common Waveform Channel Mode bit mask. */ -#define AWEX_CWCM_bp 4 /* Common Waveform Channel Mode bit position. */ - -#define AWEX_DTICCDEN_bm 0x08 /* Dead Time Insertion Compare Channel D Enable bit mask. */ -#define AWEX_DTICCDEN_bp 3 /* Dead Time Insertion Compare Channel D Enable bit position. */ - -#define AWEX_DTICCCEN_bm 0x04 /* Dead Time Insertion Compare Channel C Enable bit mask. */ -#define AWEX_DTICCCEN_bp 2 /* Dead Time Insertion Compare Channel C Enable bit position. */ - -#define AWEX_DTICCBEN_bm 0x02 /* Dead Time Insertion Compare Channel B Enable bit mask. */ -#define AWEX_DTICCBEN_bp 1 /* Dead Time Insertion Compare Channel B Enable bit position. */ - -#define AWEX_DTICCAEN_bm 0x01 /* Dead Time Insertion Compare Channel A Enable bit mask. */ -#define AWEX_DTICCAEN_bp 0 /* Dead Time Insertion Compare Channel A Enable bit position. */ - -/* AWEX.FDCTRL bit masks and bit positions */ -#define AWEX_FDDBD_bm 0x10 /* Fault Detect on Disable Break Disable bit mask. */ -#define AWEX_FDDBD_bp 4 /* Fault Detect on Disable Break Disable bit position. */ - -#define AWEX_FDMODE_bm 0x04 /* Fault Detect Mode bit mask. */ -#define AWEX_FDMODE_bp 2 /* Fault Detect Mode bit position. */ - -#define AWEX_FDACT_gm 0x03 /* Fault Detect Action group mask. */ -#define AWEX_FDACT_gp 0 /* Fault Detect Action group position. */ -#define AWEX_FDACT0_bm (1<<0) /* Fault Detect Action bit 0 mask. */ -#define AWEX_FDACT0_bp 0 /* Fault Detect Action bit 0 position. */ -#define AWEX_FDACT1_bm (1<<1) /* Fault Detect Action bit 1 mask. */ -#define AWEX_FDACT1_bp 1 /* Fault Detect Action bit 1 position. */ - -/* AWEX.STATUS bit masks and bit positions */ -#define AWEX_FDF_bm 0x04 /* Fault Detect Flag bit mask. */ -#define AWEX_FDF_bp 2 /* Fault Detect Flag bit position. */ - -#define AWEX_DTHSBUFV_bm 0x02 /* Dead Time High Side Buffer Valid bit mask. */ -#define AWEX_DTHSBUFV_bp 1 /* Dead Time High Side Buffer Valid bit position. */ - -#define AWEX_DTLSBUFV_bm 0x01 /* Dead Time Low Side Buffer Valid bit mask. */ -#define AWEX_DTLSBUFV_bp 0 /* Dead Time Low Side Buffer Valid bit position. */ - -/* AWEX.STATUSSET bit masks and bit positions */ -/* AWEX_FDF Predefined. */ -/* AWEX_FDF Predefined. */ - -/* AWEX_DTHSBUFV Predefined. */ -/* AWEX_DTHSBUFV Predefined. */ - -/* AWEX_DTLSBUFV Predefined. */ -/* AWEX_DTLSBUFV Predefined. */ - -/* HIRES - Timer/Counter High-Resolution Extension */ -/* HIRES.CTRLA bit masks and bit positions */ -#define HIRES_HREN_gm 0x03 /* High Resolution Enable group mask. */ -#define HIRES_HREN_gp 0 /* High Resolution Enable group position. */ -#define HIRES_HREN0_bm (1<<0) /* High Resolution Enable bit 0 mask. */ -#define HIRES_HREN0_bp 0 /* High Resolution Enable bit 0 position. */ -#define HIRES_HREN1_bm (1<<1) /* High Resolution Enable bit 1 mask. */ -#define HIRES_HREN1_bp 1 /* High Resolution Enable bit 1 position. */ - -/* USART - Universal Asynchronous Receiver-Transmitter */ -/* USART.STATUS bit masks and bit positions */ -#define USART_RXCIF_bm 0x80 /* Receive Interrupt Flag bit mask. */ -#define USART_RXCIF_bp 7 /* Receive Interrupt Flag bit position. */ - -#define USART_TXCIF_bm 0x40 /* Transmit Interrupt Flag bit mask. */ -#define USART_TXCIF_bp 6 /* Transmit Interrupt Flag bit position. */ - -#define USART_DREIF_bm 0x20 /* Data Register Empty Flag bit mask. */ -#define USART_DREIF_bp 5 /* Data Register Empty Flag bit position. */ - -#define USART_FERR_bm 0x10 /* Frame Error bit mask. */ -#define USART_FERR_bp 4 /* Frame Error bit position. */ - -#define USART_BUFOVF_bm 0x08 /* Buffer Overflow bit mask. */ -#define USART_BUFOVF_bp 3 /* Buffer Overflow bit position. */ - -#define USART_PERR_bm 0x04 /* Parity Error bit mask. */ -#define USART_PERR_bp 2 /* Parity Error bit position. */ - -#define USART_RXB8_bm 0x01 /* Receive Bit 8 bit mask. */ -#define USART_RXB8_bp 0 /* Receive Bit 8 bit position. */ - -/* USART.CTRLA bit masks and bit positions */ -#define USART_RXCINTLVL_gm 0x30 /* Receive Interrupt Level group mask. */ -#define USART_RXCINTLVL_gp 4 /* Receive Interrupt Level group position. */ -#define USART_RXCINTLVL0_bm (1<<4) /* Receive Interrupt Level bit 0 mask. */ -#define USART_RXCINTLVL0_bp 4 /* Receive Interrupt Level bit 0 position. */ -#define USART_RXCINTLVL1_bm (1<<5) /* Receive Interrupt Level bit 1 mask. */ -#define USART_RXCINTLVL1_bp 5 /* Receive Interrupt Level bit 1 position. */ - -#define USART_TXCINTLVL_gm 0x0C /* Transmit Interrupt Level group mask. */ -#define USART_TXCINTLVL_gp 2 /* Transmit Interrupt Level group position. */ -#define USART_TXCINTLVL0_bm (1<<2) /* Transmit Interrupt Level bit 0 mask. */ -#define USART_TXCINTLVL0_bp 2 /* Transmit Interrupt Level bit 0 position. */ -#define USART_TXCINTLVL1_bm (1<<3) /* Transmit Interrupt Level bit 1 mask. */ -#define USART_TXCINTLVL1_bp 3 /* Transmit Interrupt Level bit 1 position. */ - -#define USART_DREINTLVL_gm 0x03 /* Data Register Empty Interrupt Level group mask. */ -#define USART_DREINTLVL_gp 0 /* Data Register Empty Interrupt Level group position. */ -#define USART_DREINTLVL0_bm (1<<0) /* Data Register Empty Interrupt Level bit 0 mask. */ -#define USART_DREINTLVL0_bp 0 /* Data Register Empty Interrupt Level bit 0 position. */ -#define USART_DREINTLVL1_bm (1<<1) /* Data Register Empty Interrupt Level bit 1 mask. */ -#define USART_DREINTLVL1_bp 1 /* Data Register Empty Interrupt Level bit 1 position. */ - -/* USART.CTRLB bit masks and bit positions */ -#define USART_RXEN_bm 0x10 /* Receiver Enable bit mask. */ -#define USART_RXEN_bp 4 /* Receiver Enable bit position. */ - -#define USART_TXEN_bm 0x08 /* Transmitter Enable bit mask. */ -#define USART_TXEN_bp 3 /* Transmitter Enable bit position. */ - -#define USART_CLK2X_bm 0x04 /* Double transmission speed bit mask. */ -#define USART_CLK2X_bp 2 /* Double transmission speed bit position. */ - -#define USART_MPCM_bm 0x02 /* Multi-processor Communication Mode bit mask. */ -#define USART_MPCM_bp 1 /* Multi-processor Communication Mode bit position. */ - -#define USART_TXB8_bm 0x01 /* Transmit bit 8 bit mask. */ -#define USART_TXB8_bp 0 /* Transmit bit 8 bit position. */ - -/* USART.CTRLC bit masks and bit positions */ -#define USART_CMODE_gm 0xC0 /* Communication Mode group mask. */ -#define USART_CMODE_gp 6 /* Communication Mode group position. */ -#define USART_CMODE0_bm (1<<6) /* Communication Mode bit 0 mask. */ -#define USART_CMODE0_bp 6 /* Communication Mode bit 0 position. */ -#define USART_CMODE1_bm (1<<7) /* Communication Mode bit 1 mask. */ -#define USART_CMODE1_bp 7 /* Communication Mode bit 1 position. */ - -#define USART_PMODE_gm 0x30 /* Parity Mode group mask. */ -#define USART_PMODE_gp 4 /* Parity Mode group position. */ -#define USART_PMODE0_bm (1<<4) /* Parity Mode bit 0 mask. */ -#define USART_PMODE0_bp 4 /* Parity Mode bit 0 position. */ -#define USART_PMODE1_bm (1<<5) /* Parity Mode bit 1 mask. */ -#define USART_PMODE1_bp 5 /* Parity Mode bit 1 position. */ - -#define USART_SBMODE_bm 0x08 /* Stop Bit Mode bit mask. */ -#define USART_SBMODE_bp 3 /* Stop Bit Mode bit position. */ - -#define USART_CHSIZE_gm 0x07 /* Character Size group mask. */ -#define USART_CHSIZE_gp 0 /* Character Size group position. */ -#define USART_CHSIZE0_bm (1<<0) /* Character Size bit 0 mask. */ -#define USART_CHSIZE0_bp 0 /* Character Size bit 0 position. */ -#define USART_CHSIZE1_bm (1<<1) /* Character Size bit 1 mask. */ -#define USART_CHSIZE1_bp 1 /* Character Size bit 1 position. */ -#define USART_CHSIZE2_bm (1<<2) /* Character Size bit 2 mask. */ -#define USART_CHSIZE2_bp 2 /* Character Size bit 2 position. */ - -/* USART.BAUDCTRLA bit masks and bit positions */ -#define USART_BSEL_gm 0xFF /* Baud Rate Selection Bits [7:0] group mask. */ -#define USART_BSEL_gp 0 /* Baud Rate Selection Bits [7:0] group position. */ -#define USART_BSEL0_bm (1<<0) /* Baud Rate Selection Bits [7:0] bit 0 mask. */ -#define USART_BSEL0_bp 0 /* Baud Rate Selection Bits [7:0] bit 0 position. */ -#define USART_BSEL1_bm (1<<1) /* Baud Rate Selection Bits [7:0] bit 1 mask. */ -#define USART_BSEL1_bp 1 /* Baud Rate Selection Bits [7:0] bit 1 position. */ -#define USART_BSEL2_bm (1<<2) /* Baud Rate Selection Bits [7:0] bit 2 mask. */ -#define USART_BSEL2_bp 2 /* Baud Rate Selection Bits [7:0] bit 2 position. */ -#define USART_BSEL3_bm (1<<3) /* Baud Rate Selection Bits [7:0] bit 3 mask. */ -#define USART_BSEL3_bp 3 /* Baud Rate Selection Bits [7:0] bit 3 position. */ -#define USART_BSEL4_bm (1<<4) /* Baud Rate Selection Bits [7:0] bit 4 mask. */ -#define USART_BSEL4_bp 4 /* Baud Rate Selection Bits [7:0] bit 4 position. */ -#define USART_BSEL5_bm (1<<5) /* Baud Rate Selection Bits [7:0] bit 5 mask. */ -#define USART_BSEL5_bp 5 /* Baud Rate Selection Bits [7:0] bit 5 position. */ -#define USART_BSEL6_bm (1<<6) /* Baud Rate Selection Bits [7:0] bit 6 mask. */ -#define USART_BSEL6_bp 6 /* Baud Rate Selection Bits [7:0] bit 6 position. */ -#define USART_BSEL7_bm (1<<7) /* Baud Rate Selection Bits [7:0] bit 7 mask. */ -#define USART_BSEL7_bp 7 /* Baud Rate Selection Bits [7:0] bit 7 position. */ - -/* USART.BAUDCTRLB bit masks and bit positions */ -#define USART_BSCALE_gm 0xF0 /* Baud Rate Scale group mask. */ -#define USART_BSCALE_gp 4 /* Baud Rate Scale group position. */ -#define USART_BSCALE0_bm (1<<4) /* Baud Rate Scale bit 0 mask. */ -#define USART_BSCALE0_bp 4 /* Baud Rate Scale bit 0 position. */ -#define USART_BSCALE1_bm (1<<5) /* Baud Rate Scale bit 1 mask. */ -#define USART_BSCALE1_bp 5 /* Baud Rate Scale bit 1 position. */ -#define USART_BSCALE2_bm (1<<6) /* Baud Rate Scale bit 2 mask. */ -#define USART_BSCALE2_bp 6 /* Baud Rate Scale bit 2 position. */ -#define USART_BSCALE3_bm (1<<7) /* Baud Rate Scale bit 3 mask. */ -#define USART_BSCALE3_bp 7 /* Baud Rate Scale bit 3 position. */ - -/* USART_BSEL Predefined. */ -/* USART_BSEL Predefined. */ - -/* SPI - Serial Peripheral Interface */ -/* SPI.CTRL bit masks and bit positions */ -#define SPI_CLK2X_bm 0x80 /* Enable Double Speed bit mask. */ -#define SPI_CLK2X_bp 7 /* Enable Double Speed bit position. */ - -#define SPI_ENABLE_bm 0x40 /* Enable Module bit mask. */ -#define SPI_ENABLE_bp 6 /* Enable Module bit position. */ - -#define SPI_DORD_bm 0x20 /* Data Order Setting bit mask. */ -#define SPI_DORD_bp 5 /* Data Order Setting bit position. */ - -#define SPI_MASTER_bm 0x10 /* Master Operation Enable bit mask. */ -#define SPI_MASTER_bp 4 /* Master Operation Enable bit position. */ - -#define SPI_MODE_gm 0x0C /* SPI Mode group mask. */ -#define SPI_MODE_gp 2 /* SPI Mode group position. */ -#define SPI_MODE0_bm (1<<2) /* SPI Mode bit 0 mask. */ -#define SPI_MODE0_bp 2 /* SPI Mode bit 0 position. */ -#define SPI_MODE1_bm (1<<3) /* SPI Mode bit 1 mask. */ -#define SPI_MODE1_bp 3 /* SPI Mode bit 1 position. */ - -#define SPI_PRESCALER_gm 0x03 /* Prescaler group mask. */ -#define SPI_PRESCALER_gp 0 /* Prescaler group position. */ -#define SPI_PRESCALER0_bm (1<<0) /* Prescaler bit 0 mask. */ -#define SPI_PRESCALER0_bp 0 /* Prescaler bit 0 position. */ -#define SPI_PRESCALER1_bm (1<<1) /* Prescaler bit 1 mask. */ -#define SPI_PRESCALER1_bp 1 /* Prescaler bit 1 position. */ - -/* SPI.INTCTRL bit masks and bit positions */ -#define SPI_INTLVL_gm 0x03 /* Interrupt level group mask. */ -#define SPI_INTLVL_gp 0 /* Interrupt level group position. */ -#define SPI_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */ -#define SPI_INTLVL0_bp 0 /* Interrupt level bit 0 position. */ -#define SPI_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */ -#define SPI_INTLVL1_bp 1 /* Interrupt level bit 1 position. */ - -/* SPI.STATUS bit masks and bit positions */ -#define SPI_IF_bm 0x80 /* Interrupt Flag bit mask. */ -#define SPI_IF_bp 7 /* Interrupt Flag bit position. */ - -#define SPI_WRCOL_bm 0x40 /* Write Collision bit mask. */ -#define SPI_WRCOL_bp 6 /* Write Collision bit position. */ - -/* IRCOM - IR Communication Module */ -/* IRCOM.CTRL bit masks and bit positions */ -#define IRCOM_EVSEL_gm 0x0F /* Event Channel Select group mask. */ -#define IRCOM_EVSEL_gp 0 /* Event Channel Select group position. */ -#define IRCOM_EVSEL0_bm (1<<0) /* Event Channel Select bit 0 mask. */ -#define IRCOM_EVSEL0_bp 0 /* Event Channel Select bit 0 position. */ -#define IRCOM_EVSEL1_bm (1<<1) /* Event Channel Select bit 1 mask. */ -#define IRCOM_EVSEL1_bp 1 /* Event Channel Select bit 1 position. */ -#define IRCOM_EVSEL2_bm (1<<2) /* Event Channel Select bit 2 mask. */ -#define IRCOM_EVSEL2_bp 2 /* Event Channel Select bit 2 position. */ -#define IRCOM_EVSEL3_bm (1<<3) /* Event Channel Select bit 3 mask. */ -#define IRCOM_EVSEL3_bp 3 /* Event Channel Select bit 3 position. */ - -/* LCD - LCD Controller */ -/* LCD.CTRLA bit masks and bit positions */ -#define LCD_ENABLE_bm 0x80 /* LCD Enable bit mask. */ -#define LCD_ENABLE_bp 7 /* LCD Enable bit position. */ - -#define LCD_XBIAS_bm 0x40 /* External Register Bias Generation bit mask. */ -#define LCD_XBIAS_bp 6 /* External Register Bias Generation bit position. */ - -#define LCD_DATCLK_bm 0x20 /* Data Register Lock bit mask. */ -#define LCD_DATCLK_bp 5 /* Data Register Lock bit position. */ - -#define LCD_COMSWP_bm 0x10 /* Common Bus Swap bit mask. */ -#define LCD_COMSWP_bp 4 /* Common Bus Swap bit position. */ - -#define LCD_SEGSWP_bm 0x08 /* Segment Bus Swap bit mask. */ -#define LCD_SEGSWP_bp 3 /* Segment Bus Swap bit position. */ - -#define LCD_CLRDT_bm 0x04 /* Clear Data Register bit mask. */ -#define LCD_CLRDT_bp 2 /* Clear Data Register bit position. */ - -#define LCD_SEGON_bm 0x02 /* Segments On bit mask. */ -#define LCD_SEGON_bp 1 /* Segments On bit position. */ - -#define LCD_BLANK_bm 0x01 /* Blanking Display Mode bit mask. */ -#define LCD_BLANK_bp 0 /* Blanking Display Mode bit position. */ - -/* LCD.CTRLB bit masks and bit positions */ -#define LCD_PRESC_bm 0x80 /* LCD Prescaler Select bit mask. */ -#define LCD_PRESC_bp 7 /* LCD Prescaler Select bit position. */ - -#define LCD_CLKDIV_gm 0x70 /* LCD Clock Divide group mask. */ -#define LCD_CLKDIV_gp 4 /* LCD Clock Divide group position. */ -#define LCD_CLKDIV0_bm (1<<4) /* LCD Clock Divide bit 0 mask. */ -#define LCD_CLKDIV0_bp 4 /* LCD Clock Divide bit 0 position. */ -#define LCD_CLKDIV1_bm (1<<5) /* LCD Clock Divide bit 1 mask. */ -#define LCD_CLKDIV1_bp 5 /* LCD Clock Divide bit 1 position. */ -#define LCD_CLKDIV2_bm (1<<6) /* LCD Clock Divide bit 2 mask. */ -#define LCD_CLKDIV2_bp 6 /* LCD Clock Divide bit 2 position. */ - -#define LCD_LPWAV_bm 0x08 /* Low Power Waveform bit mask. */ -#define LCD_LPWAV_bp 3 /* Low Power Waveform bit position. */ - -#define LCD_DUTY_gm 0x03 /* Duty Select group mask. */ -#define LCD_DUTY_gp 0 /* Duty Select group position. */ -#define LCD_DUTY0_bm (1<<0) /* Duty Select bit 0 mask. */ -#define LCD_DUTY0_bp 0 /* Duty Select bit 0 position. */ -#define LCD_DUTY1_bm (1<<1) /* Duty Select bit 1 mask. */ -#define LCD_DUTY1_bp 1 /* Duty Select bit 1 position. */ - -/* LCD.CTRLC bit masks and bit positions */ -#define LCD_PMSK_gm 0x3F /* LCD Port Mask group mask. */ -#define LCD_PMSK_gp 0 /* LCD Port Mask group position. */ -#define LCD_PMSK0_bm (1<<0) /* LCD Port Mask bit 0 mask. */ -#define LCD_PMSK0_bp 0 /* LCD Port Mask bit 0 position. */ -#define LCD_PMSK1_bm (1<<1) /* LCD Port Mask bit 1 mask. */ -#define LCD_PMSK1_bp 1 /* LCD Port Mask bit 1 position. */ -#define LCD_PMSK2_bm (1<<2) /* LCD Port Mask bit 2 mask. */ -#define LCD_PMSK2_bp 2 /* LCD Port Mask bit 2 position. */ -#define LCD_PMSK3_bm (1<<3) /* LCD Port Mask bit 3 mask. */ -#define LCD_PMSK3_bp 3 /* LCD Port Mask bit 3 position. */ -#define LCD_PMSK4_bm (1<<4) /* LCD Port Mask bit 4 mask. */ -#define LCD_PMSK4_bp 4 /* LCD Port Mask bit 4 position. */ -#define LCD_PMSK5_bm (1<<5) /* LCD Port Mask bit 5 mask. */ -#define LCD_PMSK5_bp 5 /* LCD Port Mask bit 5 position. */ - -/* LCD.INTCTRL bit masks and bit positions */ -#define LCD_XIME_gm 0xF8 /* eXtended Interrupt Mode Enable group mask. */ -#define LCD_XIME_gp 3 /* eXtended Interrupt Mode Enable group position. */ -#define LCD_XIME0_bm (1<<3) /* eXtended Interrupt Mode Enable bit 0 mask. */ -#define LCD_XIME0_bp 3 /* eXtended Interrupt Mode Enable bit 0 position. */ -#define LCD_XIME1_bm (1<<4) /* eXtended Interrupt Mode Enable bit 1 mask. */ -#define LCD_XIME1_bp 4 /* eXtended Interrupt Mode Enable bit 1 position. */ -#define LCD_XIME2_bm (1<<5) /* eXtended Interrupt Mode Enable bit 2 mask. */ -#define LCD_XIME2_bp 5 /* eXtended Interrupt Mode Enable bit 2 position. */ -#define LCD_XIME3_bm (1<<6) /* eXtended Interrupt Mode Enable bit 3 mask. */ -#define LCD_XIME3_bp 6 /* eXtended Interrupt Mode Enable bit 3 position. */ -#define LCD_XIME4_bm (1<<7) /* eXtended Interrupt Mode Enable bit 4 mask. */ -#define LCD_XIME4_bp 7 /* eXtended Interrupt Mode Enable bit 4 position. */ - -#define LCD_FCINTLVL_gm 0x03 /* Interrupt Level group mask. */ -#define LCD_FCINTLVL_gp 0 /* Interrupt Level group position. */ -#define LCD_FCINTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */ -#define LCD_FCINTLVL0_bp 0 /* Interrupt Level bit 0 position. */ -#define LCD_FCINTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ -#define LCD_FCINTLVL1_bp 1 /* Interrupt Level bit 1 position. */ - -/* LCD.INTFLAG bit masks and bit positions */ -#define LCD_FCIF_bm 0x01 /* LCD Frame Completed Interrupt Flag bit mask. */ -#define LCD_FCIF_bp 0 /* LCD Frame Completed Interrupt Flag bit position. */ - -/* LCD.CTRLD bit masks and bit positions */ -#define LCD_BLINKEN_bm 0x08 /* Blink Enable bit mask. */ -#define LCD_BLINKEN_bp 3 /* Blink Enable bit position. */ - -#define LCD_BLINKRATE_gm 0x03 /* LCD Blink Rate group mask. */ -#define LCD_BLINKRATE_gp 0 /* LCD Blink Rate group position. */ -#define LCD_BLINKRATE0_bm (1<<0) /* LCD Blink Rate bit 0 mask. */ -#define LCD_BLINKRATE0_bp 0 /* LCD Blink Rate bit 0 position. */ -#define LCD_BLINKRATE1_bm (1<<1) /* LCD Blink Rate bit 1 mask. */ -#define LCD_BLINKRATE1_bp 1 /* LCD Blink Rate bit 1 position. */ - -/* LCD.CTRLE bit masks and bit positions */ -#define LCD_BPS1_gm 0xF0 /* Blink Pixel Selection 1 group mask. */ -#define LCD_BPS1_gp 4 /* Blink Pixel Selection 1 group position. */ -#define LCD_BPS10_bm (1<<4) /* Blink Pixel Selection 1 bit 0 mask. */ -#define LCD_BPS10_bp 4 /* Blink Pixel Selection 1 bit 0 position. */ -#define LCD_BPS11_bm (1<<5) /* Blink Pixel Selection 1 bit 1 mask. */ -#define LCD_BPS11_bp 5 /* Blink Pixel Selection 1 bit 1 position. */ -#define LCD_BPS12_bm (1<<6) /* Blink Pixel Selection 1 bit 2 mask. */ -#define LCD_BPS12_bp 6 /* Blink Pixel Selection 1 bit 2 position. */ -#define LCD_BPS13_bm (1<<7) /* Blink Pixel Selection 1 bit 3 mask. */ -#define LCD_BPS13_bp 7 /* Blink Pixel Selection 1 bit 3 position. */ - -#define LCD_BPS0_gm 0x0F /* Blink Pixel Selection 0 group mask. */ -#define LCD_BPS0_gp 0 /* Blink Pixel Selection 0 group position. */ -#define LCD_BPS00_bm (1<<0) /* Blink Pixel Selection 0 bit 0 mask. */ -#define LCD_BPS00_bp 0 /* Blink Pixel Selection 0 bit 0 position. */ -#define LCD_BPS01_bm (1<<1) /* Blink Pixel Selection 0 bit 1 mask. */ -#define LCD_BPS01_bp 1 /* Blink Pixel Selection 0 bit 1 position. */ -#define LCD_BPS02_bm (1<<2) /* Blink Pixel Selection 0 bit 2 mask. */ -#define LCD_BPS02_bp 2 /* Blink Pixel Selection 0 bit 2 position. */ -#define LCD_BPS03_bm (1<<3) /* Blink Pixel Selection 0 bit 3 mask. */ -#define LCD_BPS03_bp 3 /* Blink Pixel Selection 0 bit 3 position. */ - -/* LCD.CTRLF bit masks and bit positions */ -#define LCD_FCONT_gm 0x3F /* Fine Contrast group mask. */ -#define LCD_FCONT_gp 0 /* Fine Contrast group position. */ -#define LCD_FCONT0_bm (1<<0) /* Fine Contrast bit 0 mask. */ -#define LCD_FCONT0_bp 0 /* Fine Contrast bit 0 position. */ -#define LCD_FCONT1_bm (1<<1) /* Fine Contrast bit 1 mask. */ -#define LCD_FCONT1_bp 1 /* Fine Contrast bit 1 position. */ -#define LCD_FCONT2_bm (1<<2) /* Fine Contrast bit 2 mask. */ -#define LCD_FCONT2_bp 2 /* Fine Contrast bit 2 position. */ -#define LCD_FCONT3_bm (1<<3) /* Fine Contrast bit 3 mask. */ -#define LCD_FCONT3_bp 3 /* Fine Contrast bit 3 position. */ -#define LCD_FCONT4_bm (1<<4) /* Fine Contrast bit 4 mask. */ -#define LCD_FCONT4_bp 4 /* Fine Contrast bit 4 position. */ -#define LCD_FCONT5_bm (1<<5) /* Fine Contrast bit 5 mask. */ -#define LCD_FCONT5_bp 5 /* Fine Contrast bit 5 position. */ - -/* LCD.CTRLG bit masks and bit positions */ -#define LCD_TDG_gm 0xC0 /* Type of Digit group mask. */ -#define LCD_TDG_gp 6 /* Type of Digit group position. */ -#define LCD_TDG0_bm (1<<6) /* Type of Digit bit 0 mask. */ -#define LCD_TDG0_bp 6 /* Type of Digit bit 0 position. */ -#define LCD_TDG1_bm (1<<7) /* Type of Digit bit 1 mask. */ -#define LCD_TDG1_bp 7 /* Type of Digit bit 1 position. */ - -#define LCD_STSEG_gm 0x3F /* Start Segment group mask. */ -#define LCD_STSEG_gp 0 /* Start Segment group position. */ -#define LCD_STSEG0_bm (1<<0) /* Start Segment bit 0 mask. */ -#define LCD_STSEG0_bp 0 /* Start Segment bit 0 position. */ -#define LCD_STSEG1_bm (1<<1) /* Start Segment bit 1 mask. */ -#define LCD_STSEG1_bp 1 /* Start Segment bit 1 position. */ -#define LCD_STSEG2_bm (1<<2) /* Start Segment bit 2 mask. */ -#define LCD_STSEG2_bp 2 /* Start Segment bit 2 position. */ -#define LCD_STSEG3_bm (1<<3) /* Start Segment bit 3 mask. */ -#define LCD_STSEG3_bp 3 /* Start Segment bit 3 position. */ -#define LCD_STSEG4_bm (1<<4) /* Start Segment bit 4 mask. */ -#define LCD_STSEG4_bp 4 /* Start Segment bit 4 position. */ -#define LCD_STSEG5_bm (1<<5) /* Start Segment bit 5 mask. */ -#define LCD_STSEG5_bp 5 /* Start Segment bit 5 position. */ - -/* LCD.CTRLH bit masks and bit positions */ -#define LCD_DEC_bm 0x80 /* Decrement of Start Segment bit mask. */ -#define LCD_DEC_bp 7 /* Decrement of Start Segment bit position. */ - -#define LCD_DCODE_gm 0x7F /* Display Code group mask. */ -#define LCD_DCODE_gp 0 /* Display Code group position. */ -#define LCD_DCODE0_bm (1<<0) /* Display Code bit 0 mask. */ -#define LCD_DCODE0_bp 0 /* Display Code bit 0 position. */ -#define LCD_DCODE1_bm (1<<1) /* Display Code bit 1 mask. */ -#define LCD_DCODE1_bp 1 /* Display Code bit 1 position. */ -#define LCD_DCODE2_bm (1<<2) /* Display Code bit 2 mask. */ -#define LCD_DCODE2_bp 2 /* Display Code bit 2 position. */ -#define LCD_DCODE3_bm (1<<3) /* Display Code bit 3 mask. */ -#define LCD_DCODE3_bp 3 /* Display Code bit 3 position. */ -#define LCD_DCODE4_bm (1<<4) /* Display Code bit 4 mask. */ -#define LCD_DCODE4_bp 4 /* Display Code bit 4 position. */ -#define LCD_DCODE5_bm (1<<5) /* Display Code bit 5 mask. */ -#define LCD_DCODE5_bp 5 /* Display Code bit 5 position. */ -#define LCD_DCODE6_bm (1<<6) /* Display Code bit 6 mask. */ -#define LCD_DCODE6_bp 6 /* Display Code bit 6 position. */ - -/* FUSE - Fuses and Lockbits */ -/* NVM_FUSES.FUSEBYTE0 bit masks and bit positions */ -#define NVM_FUSES_JTAGUSERID_gm 0xFF /* JTAG User ID group mask. */ -#define NVM_FUSES_JTAGUSERID_gp 0 /* JTAG User ID group position. */ -#define NVM_FUSES_JTAGUSERID0_bm (1<<0) /* JTAG User ID bit 0 mask. */ -#define NVM_FUSES_JTAGUSERID0_bp 0 /* JTAG User ID bit 0 position. */ -#define NVM_FUSES_JTAGUSERID1_bm (1<<1) /* JTAG User ID bit 1 mask. */ -#define NVM_FUSES_JTAGUSERID1_bp 1 /* JTAG User ID bit 1 position. */ -#define NVM_FUSES_JTAGUSERID2_bm (1<<2) /* JTAG User ID bit 2 mask. */ -#define NVM_FUSES_JTAGUSERID2_bp 2 /* JTAG User ID bit 2 position. */ -#define NVM_FUSES_JTAGUSERID3_bm (1<<3) /* JTAG User ID bit 3 mask. */ -#define NVM_FUSES_JTAGUSERID3_bp 3 /* JTAG User ID bit 3 position. */ -#define NVM_FUSES_JTAGUSERID4_bm (1<<4) /* JTAG User ID bit 4 mask. */ -#define NVM_FUSES_JTAGUSERID4_bp 4 /* JTAG User ID bit 4 position. */ -#define NVM_FUSES_JTAGUSERID5_bm (1<<5) /* JTAG User ID bit 5 mask. */ -#define NVM_FUSES_JTAGUSERID5_bp 5 /* JTAG User ID bit 5 position. */ -#define NVM_FUSES_JTAGUSERID6_bm (1<<6) /* JTAG User ID bit 6 mask. */ -#define NVM_FUSES_JTAGUSERID6_bp 6 /* JTAG User ID bit 6 position. */ -#define NVM_FUSES_JTAGUSERID7_bm (1<<7) /* JTAG User ID bit 7 mask. */ -#define NVM_FUSES_JTAGUSERID7_bp 7 /* JTAG User ID bit 7 position. */ - -/* NVM_FUSES.FUSEBYTE1 bit masks and bit positions */ -#define NVM_FUSES_WDWP_gm 0xF0 /* Watchdog Window Timeout Period group mask. */ -#define NVM_FUSES_WDWP_gp 4 /* Watchdog Window Timeout Period group position. */ -#define NVM_FUSES_WDWP0_bm (1<<4) /* Watchdog Window Timeout Period bit 0 mask. */ -#define NVM_FUSES_WDWP0_bp 4 /* Watchdog Window Timeout Period bit 0 position. */ -#define NVM_FUSES_WDWP1_bm (1<<5) /* Watchdog Window Timeout Period bit 1 mask. */ -#define NVM_FUSES_WDWP1_bp 5 /* Watchdog Window Timeout Period bit 1 position. */ -#define NVM_FUSES_WDWP2_bm (1<<6) /* Watchdog Window Timeout Period bit 2 mask. */ -#define NVM_FUSES_WDWP2_bp 6 /* Watchdog Window Timeout Period bit 2 position. */ -#define NVM_FUSES_WDWP3_bm (1<<7) /* Watchdog Window Timeout Period bit 3 mask. */ -#define NVM_FUSES_WDWP3_bp 7 /* Watchdog Window Timeout Period bit 3 position. */ - -#define NVM_FUSES_WDP_gm 0x0F /* Watchdog Timeout Period group mask. */ -#define NVM_FUSES_WDP_gp 0 /* Watchdog Timeout Period group position. */ -#define NVM_FUSES_WDP0_bm (1<<0) /* Watchdog Timeout Period bit 0 mask. */ -#define NVM_FUSES_WDP0_bp 0 /* Watchdog Timeout Period bit 0 position. */ -#define NVM_FUSES_WDP1_bm (1<<1) /* Watchdog Timeout Period bit 1 mask. */ -#define NVM_FUSES_WDP1_bp 1 /* Watchdog Timeout Period bit 1 position. */ -#define NVM_FUSES_WDP2_bm (1<<2) /* Watchdog Timeout Period bit 2 mask. */ -#define NVM_FUSES_WDP2_bp 2 /* Watchdog Timeout Period bit 2 position. */ -#define NVM_FUSES_WDP3_bm (1<<3) /* Watchdog Timeout Period bit 3 mask. */ -#define NVM_FUSES_WDP3_bp 3 /* Watchdog Timeout Period bit 3 position. */ - -/* NVM_FUSES.FUSEBYTE2 bit masks and bit positions */ -#define NVM_FUSES_BOOTRST_bm 0x40 /* Boot Loader Section Reset Vector bit mask. */ -#define NVM_FUSES_BOOTRST_bp 6 /* Boot Loader Section Reset Vector bit position. */ - -#define NVM_FUSES_TOSCSEL_bm 0x20 /* Timer Oscillator pin location bit mask. */ -#define NVM_FUSES_TOSCSEL_bp 5 /* Timer Oscillator pin location bit position. */ - -#define NVM_FUSES_BODPD_gm 0x03 /* BOD Operation in Power-Down Mode group mask. */ -#define NVM_FUSES_BODPD_gp 0 /* BOD Operation in Power-Down Mode group position. */ -#define NVM_FUSES_BODPD0_bm (1<<0) /* BOD Operation in Power-Down Mode bit 0 mask. */ -#define NVM_FUSES_BODPD0_bp 0 /* BOD Operation in Power-Down Mode bit 0 position. */ -#define NVM_FUSES_BODPD1_bm (1<<1) /* BOD Operation in Power-Down Mode bit 1 mask. */ -#define NVM_FUSES_BODPD1_bp 1 /* BOD Operation in Power-Down Mode bit 1 position. */ - -/* NVM_FUSES.FUSEBYTE4 bit masks and bit positions */ -#define NVM_FUSES_RSTDISBL_bm 0x10 /* External Reset Disable bit mask. */ -#define NVM_FUSES_RSTDISBL_bp 4 /* External Reset Disable bit position. */ - -#define NVM_FUSES_SUT_gm 0x0C /* Start-up Time group mask. */ -#define NVM_FUSES_SUT_gp 2 /* Start-up Time group position. */ -#define NVM_FUSES_SUT0_bm (1<<2) /* Start-up Time bit 0 mask. */ -#define NVM_FUSES_SUT0_bp 2 /* Start-up Time bit 0 position. */ -#define NVM_FUSES_SUT1_bm (1<<3) /* Start-up Time bit 1 mask. */ -#define NVM_FUSES_SUT1_bp 3 /* Start-up Time bit 1 position. */ - -#define NVM_FUSES_WDLOCK_bm 0x02 /* Watchdog Timer Lock bit mask. */ -#define NVM_FUSES_WDLOCK_bp 1 /* Watchdog Timer Lock bit position. */ - -#define NVM_FUSES_JTAGEN_bm 0x01 /* JTAG Interface Enable bit mask. */ -#define NVM_FUSES_JTAGEN_bp 0 /* JTAG Interface Enable bit position. */ - -/* NVM_FUSES.FUSEBYTE5 bit masks and bit positions */ -#define NVM_FUSES_BODACT_gm 0x30 /* BOD Operation in Active Mode group mask. */ -#define NVM_FUSES_BODACT_gp 4 /* BOD Operation in Active Mode group position. */ -#define NVM_FUSES_BODACT0_bm (1<<4) /* BOD Operation in Active Mode bit 0 mask. */ -#define NVM_FUSES_BODACT0_bp 4 /* BOD Operation in Active Mode bit 0 position. */ -#define NVM_FUSES_BODACT1_bm (1<<5) /* BOD Operation in Active Mode bit 1 mask. */ -#define NVM_FUSES_BODACT1_bp 5 /* BOD Operation in Active Mode bit 1 position. */ - -#define NVM_FUSES_EESAVE_bm 0x08 /* Preserve EEPROM Through Chip Erase bit mask. */ -#define NVM_FUSES_EESAVE_bp 3 /* Preserve EEPROM Through Chip Erase bit position. */ - -#define NVM_FUSES_BODLVL_gm 0x07 /* Brownout Detection Voltage Level group mask. */ -#define NVM_FUSES_BODLVL_gp 0 /* Brownout Detection Voltage Level group position. */ -#define NVM_FUSES_BODLVL0_bm (1<<0) /* Brownout Detection Voltage Level bit 0 mask. */ -#define NVM_FUSES_BODLVL0_bp 0 /* Brownout Detection Voltage Level bit 0 position. */ -#define NVM_FUSES_BODLVL1_bm (1<<1) /* Brownout Detection Voltage Level bit 1 mask. */ -#define NVM_FUSES_BODLVL1_bp 1 /* Brownout Detection Voltage Level bit 1 position. */ -#define NVM_FUSES_BODLVL2_bm (1<<2) /* Brownout Detection Voltage Level bit 2 mask. */ -#define NVM_FUSES_BODLVL2_bp 2 /* Brownout Detection Voltage Level bit 2 position. */ - -/* LOCKBIT - Fuses and Lockbits */ -/* NVM_LOCKBITS.LOCKBITS bit masks and bit positions */ -#define NVM_LOCKBITS_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ -#define NVM_LOCKBITS_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ -#define NVM_LOCKBITS_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ -#define NVM_LOCKBITS_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ -#define NVM_LOCKBITS_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ -#define NVM_LOCKBITS_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ - -#define NVM_LOCKBITS_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ -#define NVM_LOCKBITS_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ -#define NVM_LOCKBITS_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ -#define NVM_LOCKBITS_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ -#define NVM_LOCKBITS_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ -#define NVM_LOCKBITS_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ - -#define NVM_LOCKBITS_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ -#define NVM_LOCKBITS_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ -#define NVM_LOCKBITS_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ -#define NVM_LOCKBITS_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ -#define NVM_LOCKBITS_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ -#define NVM_LOCKBITS_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ - -#define NVM_LOCKBITS_LB_gm 0x03 /* Lock Bits group mask. */ -#define NVM_LOCKBITS_LB_gp 0 /* Lock Bits group position. */ -#define NVM_LOCKBITS_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ -#define NVM_LOCKBITS_LB0_bp 0 /* Lock Bits bit 0 position. */ -#define NVM_LOCKBITS_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ -#define NVM_LOCKBITS_LB1_bp 1 /* Lock Bits bit 1 position. */ - - - -// Generic Port Pins - -#define PIN0_bm 0x01 -#define PIN0_bp 0 -#define PIN1_bm 0x02 -#define PIN1_bp 1 -#define PIN2_bm 0x04 -#define PIN2_bp 2 -#define PIN3_bm 0x08 -#define PIN3_bp 3 -#define PIN4_bm 0x10 -#define PIN4_bp 4 -#define PIN5_bm 0x20 -#define PIN5_bp 5 -#define PIN6_bm 0x40 -#define PIN6_bp 6 -#define PIN7_bm 0x80 -#define PIN7_bp 7 - -/* ========== Interrupt Vector Definitions ========== */ -/* Vector 0 is the reset vector */ - -/* OSC interrupt vectors */ -#define OSC_OSCF_vect_num 1 -#define OSC_OSCF_vect _VECTOR(1) /* Oscillator Failure Interrupt (NMI) */ - -/* PORTC interrupt vectors */ -#define PORTC_INT0_vect_num 2 -#define PORTC_INT0_vect _VECTOR(2) /* External Interrupt 0 */ -#define PORTC_INT1_vect_num 3 -#define PORTC_INT1_vect _VECTOR(3) /* External Interrupt 1 */ - -/* PORTR interrupt vectors */ -#define PORTR_INT0_vect_num 4 -#define PORTR_INT0_vect _VECTOR(4) /* External Interrupt 0 */ -#define PORTR_INT1_vect_num 5 -#define PORTR_INT1_vect _VECTOR(5) /* External Interrupt 1 */ - -/* DMA interrupt vectors */ -#define DMA_CH0_vect_num 6 -#define DMA_CH0_vect _VECTOR(6) /* Channel 0 Interrupt */ -#define DMA_CH1_vect_num 7 -#define DMA_CH1_vect _VECTOR(7) /* Channel 1 Interrupt */ - -/* RTC interrupt vectors */ -#define RTC_OVF_vect_num 10 -#define RTC_OVF_vect _VECTOR(10) /* Overflow Interrupt */ -#define RTC_COMP_vect_num 11 -#define RTC_COMP_vect _VECTOR(11) /* Compare Interrupt */ - -/* TWIC interrupt vectors */ -#define TWIC_TWIS_vect_num 12 -#define TWIC_TWIS_vect _VECTOR(12) /* TWI Slave Interrupt */ -#define TWIC_TWIM_vect_num 13 -#define TWIC_TWIM_vect _VECTOR(13) /* TWI Master Interrupt */ - -/* TCC0 interrupt vectors */ -#define TCC0_OVF_vect_num 14 -#define TCC0_OVF_vect _VECTOR(14) /* Overflow Interrupt */ -#define TCC0_ERR_vect_num 15 -#define TCC0_ERR_vect _VECTOR(15) /* Error Interrupt */ -#define TCC0_CCA_vect_num 16 -#define TCC0_CCA_vect _VECTOR(16) /* Compare or Capture A Interrupt */ -#define TCC0_CCB_vect_num 17 -#define TCC0_CCB_vect _VECTOR(17) /* Compare or Capture B Interrupt */ -#define TCC0_CCC_vect_num 18 -#define TCC0_CCC_vect _VECTOR(18) /* Compare or Capture C Interrupt */ -#define TCC0_CCD_vect_num 19 -#define TCC0_CCD_vect _VECTOR(19) /* Compare or Capture D Interrupt */ - -/* TCC1 interrupt vectors */ -#define TCC1_OVF_vect_num 20 -#define TCC1_OVF_vect _VECTOR(20) /* Overflow Interrupt */ -#define TCC1_ERR_vect_num 21 -#define TCC1_ERR_vect _VECTOR(21) /* Error Interrupt */ -#define TCC1_CCA_vect_num 22 -#define TCC1_CCA_vect _VECTOR(22) /* Compare or Capture A Interrupt */ -#define TCC1_CCB_vect_num 23 -#define TCC1_CCB_vect _VECTOR(23) /* Compare or Capture B Interrupt */ - -/* SPIC interrupt vectors */ -#define SPIC_INT_vect_num 24 -#define SPIC_INT_vect _VECTOR(24) /* SPI Interrupt */ - -/* USARTC0 interrupt vectors */ -#define USARTC0_RXC_vect_num 25 -#define USARTC0_RXC_vect _VECTOR(25) /* Reception Complete Interrupt */ -#define USARTC0_DRE_vect_num 26 -#define USARTC0_DRE_vect _VECTOR(26) /* Data Register Empty Interrupt */ -#define USARTC0_TXC_vect_num 27 -#define USARTC0_TXC_vect _VECTOR(27) /* Transmission Complete Interrupt */ - -/* USB interrupt vectors */ -#define USB_BUSEVENT_vect_num 31 -#define USB_BUSEVENT_vect _VECTOR(31) /* SOF, suspend, resume, reset bus event interrupts, crc, underflow, overflow and stall error interrupts */ -#define USB_TRNCOMPL_vect_num 32 -#define USB_TRNCOMPL_vect _VECTOR(32) /* Transaction complete interrupt */ - -/* LCD interrupt vectors */ -#define LCD_INT_vect_num 35 -#define LCD_INT_vect _VECTOR(35) /* LCD Interrupt */ - -/* AES interrupt vectors */ -#define AES_INT_vect_num 36 -#define AES_INT_vect _VECTOR(36) /* AES Interrupt */ - -/* NVM interrupt vectors */ -#define NVM_EE_vect_num 37 -#define NVM_EE_vect _VECTOR(37) /* EE Interrupt */ -#define NVM_SPM_vect_num 38 -#define NVM_SPM_vect _VECTOR(38) /* SPM Interrupt */ - -/* PORTB interrupt vectors */ -#define PORTB_INT0_vect_num 39 -#define PORTB_INT0_vect _VECTOR(39) /* External Interrupt 0 */ -#define PORTB_INT1_vect_num 40 -#define PORTB_INT1_vect _VECTOR(40) /* External Interrupt 1 */ - -/* ACB interrupt vectors */ -#define ACB_AC0_vect_num 41 -#define ACB_AC0_vect _VECTOR(41) /* AC0 Interrupt */ -#define ACB_AC1_vect_num 42 -#define ACB_AC1_vect _VECTOR(42) /* AC1 Interrupt */ -#define ACB_ACW_vect_num 43 -#define ACB_ACW_vect _VECTOR(43) /* ACW Window Mode Interrupt */ - -/* ADCB interrupt vectors */ -#define ADCB_CH0_vect_num 44 -#define ADCB_CH0_vect _VECTOR(44) /* Interrupt 0 */ - -/* PORTD interrupt vectors */ -#define PORTD_INT0_vect_num 48 -#define PORTD_INT0_vect _VECTOR(48) /* External Interrupt 0 */ -#define PORTD_INT1_vect_num 49 -#define PORTD_INT1_vect _VECTOR(49) /* External Interrupt 1 */ - -/* PORTG interrupt vectors */ -#define PORTG_INT0_vect_num 50 -#define PORTG_INT0_vect _VECTOR(50) /* External Interrupt 0 */ -#define PORTG_INT1_vect_num 51 -#define PORTG_INT1_vect _VECTOR(51) /* External Interrupt 1 */ - -/* PORTM interrupt vectors */ -#define PORTM_INT0_vect_num 52 -#define PORTM_INT0_vect _VECTOR(52) /* External Interrupt 0 */ -#define PORTM_INT1_vect_num 53 -#define PORTM_INT1_vect _VECTOR(53) /* External Interrupt 1 */ - -#define _VECTOR_SIZE 4 /* Size of individual vector. */ -#define _VECTORS_SIZE (54 * _VECTOR_SIZE) - - -/* ========== Constants ========== */ - -#define PROGMEM_START (0x0000) -#define PROGMEM_SIZE (69632) -#define PROGMEM_END (PROGMEM_START + PROGMEM_SIZE - 1) - -#define APP_SECTION_START (0x0000) -#define APP_SECTION_SIZE (65536) -#define APP_SECTION_PAGE_SIZE (256) -#define APP_SECTION_END (APP_SECTION_START + APP_SECTION_SIZE - 1) - -#define APPTABLE_SECTION_START (0xF000) -#define APPTABLE_SECTION_SIZE (4096) -#define APPTABLE_SECTION_PAGE_SIZE (256) -#define APPTABLE_SECTION_END (APPTABLE_SECTION_START + APPTABLE_SECTION_SIZE - 1) - -#define BOOT_SECTION_START (0x10000) -#define BOOT_SECTION_SIZE (4096) -#define BOOT_SECTION_PAGE_SIZE (256) -#define BOOT_SECTION_END (BOOT_SECTION_START + BOOT_SECTION_SIZE - 1) - -#define DATAMEM_START (0x0000) -#define DATAMEM_SIZE (12288) -#define DATAMEM_END (DATAMEM_START + DATAMEM_SIZE - 1) - -#define IO_START (0x0000) -#define IO_SIZE (4096) -#define IO_PAGE_SIZE (0) -#define IO_END (IO_START + IO_SIZE - 1) - -#define MAPPED_EEPROM_START (0x1000) -#define MAPPED_EEPROM_SIZE (2048) -#define MAPPED_EEPROM_PAGE_SIZE (0) -#define MAPPED_EEPROM_END (MAPPED_EEPROM_START + MAPPED_EEPROM_SIZE - 1) - -#define INTERNAL_SRAM_START (0x2000) -#define INTERNAL_SRAM_SIZE (4096) -#define INTERNAL_SRAM_PAGE_SIZE (0) -#define INTERNAL_SRAM_END (INTERNAL_SRAM_START + INTERNAL_SRAM_SIZE - 1) - -#define EEPROM_START (0x0000) -#define EEPROM_SIZE (2048) -#define EEPROM_PAGE_SIZE (32) -#define EEPROM_END (EEPROM_START + EEPROM_SIZE - 1) - -#define SIGNATURES_START (0x0000) -#define SIGNATURES_SIZE (3) -#define SIGNATURES_PAGE_SIZE (0) -#define SIGNATURES_END (SIGNATURES_START + SIGNATURES_SIZE - 1) - -#define FUSES_START (0x0000) -#define FUSES_SIZE (6) -#define FUSES_PAGE_SIZE (0) -#define FUSES_END (FUSES_START + FUSES_SIZE - 1) - -#define LOCKBITS_START (0x0000) -#define LOCKBITS_SIZE (1) -#define LOCKBITS_PAGE_SIZE (0) -#define LOCKBITS_END (LOCKBITS_START + LOCKBITS_SIZE - 1) - -#define USER_SIGNATURES_START (0x0000) -#define USER_SIGNATURES_SIZE (256) -#define USER_SIGNATURES_PAGE_SIZE (256) -#define USER_SIGNATURES_END (USER_SIGNATURES_START + USER_SIGNATURES_SIZE - 1) - -#define PROD_SIGNATURES_START (0x0000) -#define PROD_SIGNATURES_SIZE (52) -#define PROD_SIGNATURES_PAGE_SIZE (256) -#define PROD_SIGNATURES_END (PROD_SIGNATURES_START + PROD_SIGNATURES_SIZE - 1) - -#define FLASHSTART PROGMEM_START -#define FLASHEND PROGMEM_END -#define SPM_PAGESIZE 256 -#define RAMSTART INTERNAL_SRAM_START -#define RAMSIZE INTERNAL_SRAM_SIZE -#define RAMEND INTERNAL_SRAM_END -#define E2END EEPROM_END -#define E2PAGESIZE EEPROM_PAGE_SIZE - - -/* ========== Fuses ========== */ -#define FUSE_MEMORY_SIZE 6 - -/* Fuse Byte 0 */ -#define FUSE_JTAGUSERID0 (unsigned char)~_BV(0) /* JTAG User ID Bit 0 */ -#define FUSE_JTAGUSERID1 (unsigned char)~_BV(1) /* JTAG User ID Bit 1 */ -#define FUSE_JTAGUSERID2 (unsigned char)~_BV(2) /* JTAG User ID Bit 2 */ -#define FUSE_JTAGUSERID3 (unsigned char)~_BV(3) /* JTAG User ID Bit 3 */ -#define FUSE_JTAGUSERID4 (unsigned char)~_BV(4) /* JTAG User ID Bit 4 */ -#define FUSE_JTAGUSERID5 (unsigned char)~_BV(5) /* JTAG User ID Bit 5 */ -#define FUSE_JTAGUSERID6 (unsigned char)~_BV(6) /* JTAG User ID Bit 6 */ -#define FUSE_JTAGUSERID7 (unsigned char)~_BV(7) /* JTAG User ID Bit 7 */ -#define FUSE0_DEFAULT (0xFF) - -/* Fuse Byte 1 */ -#define FUSE_WDP0 (unsigned char)~_BV(0) /* Watchdog Timeout Period Bit 0 */ -#define FUSE_WDP1 (unsigned char)~_BV(1) /* Watchdog Timeout Period Bit 1 */ -#define FUSE_WDP2 (unsigned char)~_BV(2) /* Watchdog Timeout Period Bit 2 */ -#define FUSE_WDP3 (unsigned char)~_BV(3) /* Watchdog Timeout Period Bit 3 */ -#define FUSE_WDWP0 (unsigned char)~_BV(4) /* Watchdog Window Timeout Period Bit 0 */ -#define FUSE_WDWP1 (unsigned char)~_BV(5) /* Watchdog Window Timeout Period Bit 1 */ -#define FUSE_WDWP2 (unsigned char)~_BV(6) /* Watchdog Window Timeout Period Bit 2 */ -#define FUSE_WDWP3 (unsigned char)~_BV(7) /* Watchdog Window Timeout Period Bit 3 */ -#define FUSE1_DEFAULT (0xFF) - -/* Fuse Byte 2 */ -#define FUSE_BODPD0 (unsigned char)~_BV(0) /* BOD Operation in Power-Down Mode Bit 0 */ -#define FUSE_BODPD1 (unsigned char)~_BV(1) /* BOD Operation in Power-Down Mode Bit 1 */ -#define FUSE_TOSCSEL (unsigned char)~_BV(5) /* Timer Oscillator pin location */ -#define FUSE_BOOTRST (unsigned char)~_BV(6) /* Boot Loader Section Reset Vector */ -#define FUSE2_DEFAULT (0xFF) - -/* Fuse Byte 3 Reserved */ - -/* Fuse Byte 4 */ -#define FUSE_JTAGEN (unsigned char)~_BV(0) /* JTAG Interface Enable */ -#define FUSE_WDLOCK (unsigned char)~_BV(1) /* Watchdog Timer Lock */ -#define FUSE_SUT0 (unsigned char)~_BV(2) /* Start-up Time Bit 0 */ -#define FUSE_SUT1 (unsigned char)~_BV(3) /* Start-up Time Bit 1 */ -#define FUSE_RSTDISBL (unsigned char)~_BV(4) /* External Reset Disable */ -#define FUSE4_DEFAULT (0xFF) - -/* Fuse Byte 5 */ -#define FUSE_BODLVL0 (unsigned char)~_BV(0) /* Brownout Detection Voltage Level Bit 0 */ -#define FUSE_BODLVL1 (unsigned char)~_BV(1) /* Brownout Detection Voltage Level Bit 1 */ -#define FUSE_BODLVL2 (unsigned char)~_BV(2) /* Brownout Detection Voltage Level Bit 2 */ -#define FUSE_EESAVE (unsigned char)~_BV(3) /* Preserve EEPROM Through Chip Erase */ -#define FUSE_BODACT0 (unsigned char)~_BV(4) /* BOD Operation in Active Mode Bit 0 */ -#define FUSE_BODACT1 (unsigned char)~_BV(5) /* BOD Operation in Active Mode Bit 1 */ -#define FUSE5_DEFAULT (0xFF) - -/* ========== Lock Bits ========== */ -#define __LOCK_BITS_EXIST -#define __BOOT_LOCK_APPLICATION_TABLE_BITS_EXIST -#define __BOOT_LOCK_APPLICATION_BITS_EXIST -#define __BOOT_LOCK_BOOT_BITS_EXIST - -/* ========== Signature ========== */ -#define SIGNATURE_0 0x1E -#define SIGNATURE_1 0x96 -#define SIGNATURE_2 0x51 - -/* ========== Power Reduction Condition Definitions ========== */ - -/* PR.PRGEN */ -#define __AVR_HAVE_PRGEN (PR_LCD_bm|PR_USB_bm|PR_AES_bm|PR_RTC_bm|PR_EVSYS_bm|PR_DMA_bm) -#define __AVR_HAVE_PRGEN_LCD -#define __AVR_HAVE_PRGEN_USB -#define __AVR_HAVE_PRGEN_AES -#define __AVR_HAVE_PRGEN_RTC -#define __AVR_HAVE_PRGEN_EVSYS -#define __AVR_HAVE_PRGEN_DMA - -/* PR.PRPA */ -#define __AVR_HAVE_PRPA (PR_ADC_bm|PR_AC_bm) -#define __AVR_HAVE_PRPA_ADC -#define __AVR_HAVE_PRPA_AC - -/* PR.PRPB */ -#define __AVR_HAVE_PRPB (PR_ADC_bm|PR_AC_bm) -#define __AVR_HAVE_PRPB_ADC -#define __AVR_HAVE_PRPB_AC - -/* PR.PRPC */ -#define __AVR_HAVE_PRPC (PR_TWI_bm|PR_USART0_bm|PR_SPI_bm|PR_HIRES_bm|PR_TC1_bm|PR_TC0_bm) -#define __AVR_HAVE_PRPC_TWI -#define __AVR_HAVE_PRPC_USART0 -#define __AVR_HAVE_PRPC_SPI -#define __AVR_HAVE_PRPC_HIRES -#define __AVR_HAVE_PRPC_TC1 -#define __AVR_HAVE_PRPC_TC0 - -/* PR.PRPE */ -#define __AVR_HAVE_PRPE (PR_USART0_bm|PR_TC0_bm) -#define __AVR_HAVE_PRPE_USART0 -#define __AVR_HAVE_PRPE_TC0 - - -#endif /* #ifdef _AVR_ATXMEGA64B3_H_INCLUDED */ - diff --git a/arduino/hardware/tools/avr/avr/include/avr/iox64c3.h b/arduino/hardware/tools/avr/avr/include/avr/iox64c3.h deleted file mode 100644 index c6c1d68..0000000 --- a/arduino/hardware/tools/avr/avr/include/avr/iox64c3.h +++ /dev/null @@ -1,6264 +0,0 @@ -/***************************************************************************** - * - * Copyright (C) 2015 Atmel Corporation - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * - * * Neither the name of the copyright holders nor the names of - * contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - ****************************************************************************/ - - -#ifndef _AVR_IO_H_ -# error "Include instead of this file." -#endif - -#ifndef _AVR_IOXXX_H_ -# define _AVR_IOXXX_H_ "iox64c3.h" -#else -# error "Attempt to include more than one file." -#endif - -#ifndef _AVR_ATXMEGA64C3_H_INCLUDED -#define _AVR_ATXMEGA64C3_H_INCLUDED - -/* Ungrouped common registers */ -#define GPIOR0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ -#define GPIOR1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ -#define GPIOR2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ -#define GPIOR3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ - -/* Deprecated */ -#define GPIO0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ -#define GPIO1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ -#define GPIO2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ -#define GPIO3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ - -#define CCP _SFR_MEM8(0x0034) /* Configuration Change Protection */ -#define RAMPD _SFR_MEM8(0x0038) /* Ramp D */ -#define RAMPX _SFR_MEM8(0x0039) /* Ramp X */ -#define RAMPY _SFR_MEM8(0x003A) /* Ramp Y */ -#define RAMPZ _SFR_MEM8(0x003B) /* Ramp Z */ -#define EIND _SFR_MEM8(0x003C) /* Extended Indirect Jump */ -#define SPL _SFR_MEM8(0x003D) /* Stack Pointer Low */ -#define SPH _SFR_MEM8(0x003E) /* Stack Pointer High */ -#define SREG _SFR_MEM8(0x003F) /* Status Register */ - -/* C Language Only */ -#if !defined (__ASSEMBLER__) - -#include - -typedef volatile uint8_t register8_t; -typedef volatile uint16_t register16_t; -typedef volatile uint32_t register32_t; - - -#ifdef _WORDREGISTER -#undef _WORDREGISTER -#endif -#define _WORDREGISTER(regname) \ - __extension__ union \ - { \ - register16_t regname; \ - struct \ - { \ - register8_t regname ## L; \ - register8_t regname ## H; \ - }; \ - } - -#ifdef _DWORDREGISTER -#undef _DWORDREGISTER -#endif -#define _DWORDREGISTER(regname) \ - __extension__ union \ - { \ - register32_t regname; \ - struct \ - { \ - register8_t regname ## 0; \ - register8_t regname ## 1; \ - register8_t regname ## 2; \ - register8_t regname ## 3; \ - }; \ - } - - -/* -========================================================================== -IO Module Structures -========================================================================== -*/ - - -/* --------------------------------------------------------------------------- -VPORT - Virtual Ports --------------------------------------------------------------------------- -*/ - -/* Virtual Port */ -typedef struct VPORT_struct -{ - register8_t DIR; /* I/O Port Data Direction */ - register8_t OUT; /* I/O Port Output */ - register8_t IN; /* I/O Port Input */ - register8_t INTFLAGS; /* Interrupt Flag Register */ -} VPORT_t; - - -/* --------------------------------------------------------------------------- -XOCD - On-Chip Debug System --------------------------------------------------------------------------- -*/ - -/* On-Chip Debug System */ -typedef struct OCD_struct -{ - register8_t OCDR0; /* OCD Register 0 */ - register8_t OCDR1; /* OCD Register 1 */ -} OCD_t; - - -/* --------------------------------------------------------------------------- -CPU - CPU --------------------------------------------------------------------------- -*/ - -/* CCP signatures */ -typedef enum CCP_enum -{ - CCP_SPM_gc = (0x9D<<0), /* SPM Instruction Protection */ - CCP_IOREG_gc = (0xD8<<0), /* IO Register Protection */ -} CCP_t; - - -/* --------------------------------------------------------------------------- -CLK - Clock System --------------------------------------------------------------------------- -*/ - -/* Clock System */ -typedef struct CLK_struct -{ - register8_t CTRL; /* Control Register */ - register8_t PSCTRL; /* Prescaler Control Register */ - register8_t LOCK; /* Lock register */ - register8_t RTCCTRL; /* RTC Control Register */ - register8_t USBCTRL; /* USB Control Register */ -} CLK_t; - - -/* Power Reduction */ -typedef struct PR_struct -{ - register8_t PRGEN; /* General Power Reduction */ - register8_t PRPA; /* Power Reduction Port A */ - register8_t reserved_0x02; - register8_t PRPC; /* Power Reduction Port C */ - register8_t PRPD; /* Power Reduction Port D */ - register8_t PRPE; /* Power Reduction Port E */ - register8_t PRPF; /* Power Reduction Port F */ -} PR_t; - -/* System Clock Selection */ -typedef enum CLK_SCLKSEL_enum -{ - CLK_SCLKSEL_RC2M_gc = (0x00<<0), /* Internal 2 MHz RC Oscillator */ - CLK_SCLKSEL_RC32M_gc = (0x01<<0), /* Internal 32 MHz RC Oscillator */ - CLK_SCLKSEL_RC32K_gc = (0x02<<0), /* Internal 32.768 kHz RC Oscillator */ - CLK_SCLKSEL_XOSC_gc = (0x03<<0), /* External Crystal Oscillator or Clock */ - CLK_SCLKSEL_PLL_gc = (0x04<<0), /* Phase Locked Loop */ -} CLK_SCLKSEL_t; - -/* Prescaler A Division Factor */ -typedef enum CLK_PSADIV_enum -{ - CLK_PSADIV_1_gc = (0x00<<2), /* Divide by 1 */ - CLK_PSADIV_2_gc = (0x01<<2), /* Divide by 2 */ - CLK_PSADIV_4_gc = (0x03<<2), /* Divide by 4 */ - CLK_PSADIV_8_gc = (0x05<<2), /* Divide by 8 */ - CLK_PSADIV_16_gc = (0x07<<2), /* Divide by 16 */ - CLK_PSADIV_32_gc = (0x09<<2), /* Divide by 32 */ - CLK_PSADIV_64_gc = (0x0B<<2), /* Divide by 64 */ - CLK_PSADIV_128_gc = (0x0D<<2), /* Divide by 128 */ - CLK_PSADIV_256_gc = (0x0F<<2), /* Divide by 256 */ - CLK_PSADIV_512_gc = (0x11<<2), /* Divide by 512 */ -} CLK_PSADIV_t; - -/* Prescaler B and C Division Factor */ -typedef enum CLK_PSBCDIV_enum -{ - CLK_PSBCDIV_1_1_gc = (0x00<<0), /* Divide B by 1 and C by 1 */ - CLK_PSBCDIV_1_2_gc = (0x01<<0), /* Divide B by 1 and C by 2 */ - CLK_PSBCDIV_4_1_gc = (0x02<<0), /* Divide B by 4 and C by 1 */ - CLK_PSBCDIV_2_2_gc = (0x03<<0), /* Divide B by 2 and C by 2 */ -} CLK_PSBCDIV_t; - -/* RTC Clock Source */ -typedef enum CLK_RTCSRC_enum -{ - CLK_RTCSRC_ULP_gc = (0x00<<1), /* 1.024 kHz from internal 32kHz ULP */ - CLK_RTCSRC_TOSC_gc = (0x01<<1), /* 1.024 kHz from 32.768 kHz crystal oscillator on TOSC */ - CLK_RTCSRC_RCOSC_gc = (0x02<<1), /* 1.024 kHz from internal 32.768 kHz RC oscillator */ - CLK_RTCSRC_TOSC32_gc = (0x05<<1), /* 32.768 kHz from 32.768 kHz crystal oscillator on TOSC */ - CLK_RTCSRC_RCOSC32_gc = (0x06<<1), /* 32.768 kHz from internal 32.768 kHz RC oscillator */ - CLK_RTCSRC_EXTCLK_gc = (0x07<<1), /* External Clock from TOSC1 */ -} CLK_RTCSRC_t; - -/* USB Prescaler Division Factor */ -typedef enum CLK_USBPSDIV_enum -{ - CLK_USBPSDIV_1_gc = (0x00<<3), /* Divide by 1 */ - CLK_USBPSDIV_2_gc = (0x01<<3), /* Divide by 2 */ - CLK_USBPSDIV_4_gc = (0x02<<3), /* Divide by 4 */ - CLK_USBPSDIV_8_gc = (0x03<<3), /* Divide by 8 */ - CLK_USBPSDIV_16_gc = (0x04<<3), /* Divide by 16 */ - CLK_USBPSDIV_32_gc = (0x05<<3), /* Divide by 32 */ -} CLK_USBPSDIV_t; - -/* USB Clock Source */ -typedef enum CLK_USBSRC_enum -{ - CLK_USBSRC_PLL_gc = (0x00<<1), /* PLL */ - CLK_USBSRC_RC32M_gc = (0x01<<1), /* Internal 32 MHz RC Oscillator */ -} CLK_USBSRC_t; - - -/* --------------------------------------------------------------------------- -SLEEP - Sleep Controller --------------------------------------------------------------------------- -*/ - -/* Sleep Controller */ -typedef struct SLEEP_struct -{ - register8_t CTRL; /* Control Register */ -} SLEEP_t; - -/* Sleep Mode */ -typedef enum SLEEP_SMODE_enum -{ - SLEEP_SMODE_IDLE_gc = (0x00<<1), /* Idle mode */ - SLEEP_SMODE_PDOWN_gc = (0x02<<1), /* Power-down Mode */ - SLEEP_SMODE_PSAVE_gc = (0x03<<1), /* Power-save Mode */ - SLEEP_SMODE_STDBY_gc = (0x06<<1), /* Standby Mode */ - SLEEP_SMODE_ESTDBY_gc = (0x07<<1), /* Extended Standby Mode */ -} SLEEP_SMODE_t; - - - -#define SLEEP_MODE_IDLE (0x00<<1) -#define SLEEP_MODE_PWR_DOWN (0x02<<1) -#define SLEEP_MODE_PWR_SAVE (0x03<<1) -#define SLEEP_MODE_STANDBY (0x06<<1) -#define SLEEP_MODE_EXT_STANDBY (0x07<<1) -/* --------------------------------------------------------------------------- -OSC - Oscillator --------------------------------------------------------------------------- -*/ - -/* Oscillator */ -typedef struct OSC_struct -{ - register8_t CTRL; /* Control Register */ - register8_t STATUS; /* Status Register */ - register8_t XOSCCTRL; /* External Oscillator Control Register */ - register8_t XOSCFAIL; /* Oscillator Failure Detection Register */ - register8_t RC32KCAL; /* 32.768 kHz Internal Oscillator Calibration Register */ - register8_t PLLCTRL; /* PLL Control Register */ - register8_t DFLLCTRL; /* DFLL Control Register */ -} OSC_t; - -/* Oscillator Frequency Range */ -typedef enum OSC_FRQRANGE_enum -{ - OSC_FRQRANGE_04TO2_gc = (0x00<<6), /* 0.4 - 2 MHz */ - OSC_FRQRANGE_2TO9_gc = (0x01<<6), /* 2 - 9 MHz */ - OSC_FRQRANGE_9TO12_gc = (0x02<<6), /* 9 - 12 MHz */ - OSC_FRQRANGE_12TO16_gc = (0x03<<6), /* 12 - 16 MHz */ -} OSC_FRQRANGE_t; - -/* External Oscillator Selection and Startup Time */ -typedef enum OSC_XOSCSEL_enum -{ - OSC_XOSCSEL_EXTCLK_gc = (0x00<<0), /* External Clock - 6 CLK */ - OSC_XOSCSEL_32KHz_gc = (0x02<<0), /* 32.768 kHz TOSC - 32K CLK */ - OSC_XOSCSEL_XTAL_256CLK_gc = (0x03<<0), /* 0.4-16 MHz XTAL - 256 CLK */ - OSC_XOSCSEL_XTAL_1KCLK_gc = (0x07<<0), /* 0.4-16 MHz XTAL - 1K CLK */ - OSC_XOSCSEL_XTAL_16KCLK_gc = (0x0B<<0), /* 0.4-16 MHz XTAL - 16K CLK */ -} OSC_XOSCSEL_t; - -/* PLL Clock Source */ -typedef enum OSC_PLLSRC_enum -{ - OSC_PLLSRC_RC2M_gc = (0x00<<6), /* Internal 2 MHz RC Oscillator */ - OSC_PLLSRC_RC32M_gc = (0x02<<6), /* Internal 32 MHz RC Oscillator */ - OSC_PLLSRC_XOSC_gc = (0x03<<6), /* External Oscillator */ -} OSC_PLLSRC_t; - -/* 2 MHz DFLL Calibration Reference */ -typedef enum OSC_RC2MCREF_enum -{ - OSC_RC2MCREF_RC32K_gc = (0x00<<0), /* Internal 32.768 kHz RC Oscillator */ - OSC_RC2MCREF_XOSC32K_gc = (0x01<<0), /* External 32.768 kHz Crystal Oscillator */ -} OSC_RC2MCREF_t; - -/* 32 MHz DFLL Calibration Reference */ -typedef enum OSC_RC32MCREF_enum -{ - OSC_RC32MCREF_RC32K_gc = (0x00<<1), /* Internal 32.768 kHz RC Oscillator */ - OSC_RC32MCREF_XOSC32K_gc = (0x01<<1), /* External 32.768 kHz Crystal Oscillator */ - OSC_RC32MCREF_USBSOF_gc = (0x02<<1), /* USB Start of Frame */ -} OSC_RC32MCREF_t; - - -/* --------------------------------------------------------------------------- -DFLL - DFLL --------------------------------------------------------------------------- -*/ - -/* DFLL */ -typedef struct DFLL_struct -{ - register8_t CTRL; /* Control Register */ - register8_t reserved_0x01; - register8_t CALA; /* Calibration Register A */ - register8_t CALB; /* Calibration Register B */ - register8_t COMP0; /* Oscillator Compare Register 0 */ - register8_t COMP1; /* Oscillator Compare Register 1 */ - register8_t COMP2; /* Oscillator Compare Register 2 */ - register8_t reserved_0x07; -} DFLL_t; - - -/* --------------------------------------------------------------------------- -RST - Reset --------------------------------------------------------------------------- -*/ - -/* Reset */ -typedef struct RST_struct -{ - register8_t STATUS; /* Status Register */ - register8_t CTRL; /* Control Register */ -} RST_t; - - -/* --------------------------------------------------------------------------- -WDT - Watch-Dog Timer --------------------------------------------------------------------------- -*/ - -/* Watch-Dog Timer */ -typedef struct WDT_struct -{ - register8_t CTRL; /* Control */ - register8_t WINCTRL; /* Windowed Mode Control */ - register8_t STATUS; /* Status */ -} WDT_t; - -/* Period setting */ -typedef enum WDT_PER_enum -{ - WDT_PER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ - WDT_PER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ - WDT_PER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ - WDT_PER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ - WDT_PER_128CLK_gc = (0x04<<2), /* 128 cycles (0.128s @ 3.3V) */ - WDT_PER_256CLK_gc = (0x05<<2), /* 256 cycles (0.256s @ 3.3V) */ - WDT_PER_512CLK_gc = (0x06<<2), /* 512 cycles (0.512s @ 3.3V) */ - WDT_PER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ - WDT_PER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ - WDT_PER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ - WDT_PER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ -} WDT_PER_t; - -/* Closed window period */ -typedef enum WDT_WPER_enum -{ - WDT_WPER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ - WDT_WPER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ - WDT_WPER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ - WDT_WPER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ - WDT_WPER_128CLK_gc = (0x04<<2), /* 128 cycles (0.128s @ 3.3V) */ - WDT_WPER_256CLK_gc = (0x05<<2), /* 256 cycles (0.256s @ 3.3V) */ - WDT_WPER_512CLK_gc = (0x06<<2), /* 512 cycles (0.512s @ 3.3V) */ - WDT_WPER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ - WDT_WPER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ - WDT_WPER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ - WDT_WPER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ -} WDT_WPER_t; - - -/* --------------------------------------------------------------------------- -MCU - MCU Control --------------------------------------------------------------------------- -*/ - -/* MCU Control */ -typedef struct MCU_struct -{ - register8_t DEVID0; /* Device ID byte 0 */ - register8_t DEVID1; /* Device ID byte 1 */ - register8_t DEVID2; /* Device ID byte 2 */ - register8_t REVID; /* Revision ID */ - register8_t reserved_0x04; - register8_t reserved_0x05; - register8_t reserved_0x06; - register8_t ANAINIT; /* Analog Startup Delay */ - register8_t EVSYSLOCK; /* Event System Lock */ - register8_t AWEXLOCK; /* AWEX Lock */ - register8_t reserved_0x0A; - register8_t reserved_0x0B; -} MCU_t; - - -/* --------------------------------------------------------------------------- -PMIC - Programmable Multi-level Interrupt Controller --------------------------------------------------------------------------- -*/ - -/* Programmable Multi-level Interrupt Controller */ -typedef struct PMIC_struct -{ - register8_t STATUS; /* Status Register */ - register8_t INTPRI; /* Interrupt Priority */ - register8_t CTRL; /* Control Register */ - register8_t reserved_0x03; - register8_t reserved_0x04; - register8_t reserved_0x05; - register8_t reserved_0x06; - register8_t reserved_0x07; - register8_t reserved_0x08; - register8_t reserved_0x09; - register8_t reserved_0x0A; - register8_t reserved_0x0B; - register8_t reserved_0x0C; - register8_t reserved_0x0D; - register8_t reserved_0x0E; - register8_t reserved_0x0F; -} PMIC_t; - - -/* --------------------------------------------------------------------------- -PORTCFG - Port Configuration --------------------------------------------------------------------------- -*/ - -/* I/O port Configuration */ -typedef struct PORTCFG_struct -{ - register8_t MPCMASK; /* Multi-pin Configuration Mask */ - register8_t reserved_0x01; - register8_t VPCTRLA; /* Virtual Port Control Register A */ - register8_t VPCTRLB; /* Virtual Port Control Register B */ - register8_t CLKEVOUT; /* Clock and Event Out Register */ - register8_t reserved_0x05; - register8_t EVOUTSEL; /* Event Output Select */ -} PORTCFG_t; - -/* Virtual Port Mapping */ -typedef enum PORTCFG_VP02MAP_enum -{ - PORTCFG_VP02MAP_PORTA_gc = (0x00<<0), /* Mapped To PORTA */ - PORTCFG_VP02MAP_PORTB_gc = (0x01<<0), /* Mapped To PORTB */ - PORTCFG_VP02MAP_PORTC_gc = (0x02<<0), /* Mapped To PORTC */ - PORTCFG_VP02MAP_PORTD_gc = (0x03<<0), /* Mapped To PORTD */ - PORTCFG_VP02MAP_PORTE_gc = (0x04<<0), /* Mapped To PORTE */ - PORTCFG_VP02MAP_PORTF_gc = (0x05<<0), /* Mapped To PORTF */ - PORTCFG_VP02MAP_PORTG_gc = (0x06<<0), /* Mapped To PORTG */ - PORTCFG_VP02MAP_PORTH_gc = (0x07<<0), /* Mapped To PORTH */ - PORTCFG_VP02MAP_PORTJ_gc = (0x08<<0), /* Mapped To PORTJ */ - PORTCFG_VP02MAP_PORTK_gc = (0x09<<0), /* Mapped To PORTK */ - PORTCFG_VP02MAP_PORTL_gc = (0x0A<<0), /* Mapped To PORTL */ - PORTCFG_VP02MAP_PORTM_gc = (0x0B<<0), /* Mapped To PORTM */ - PORTCFG_VP02MAP_PORTN_gc = (0x0C<<0), /* Mapped To PORTN */ - PORTCFG_VP02MAP_PORTP_gc = (0x0D<<0), /* Mapped To PORTP */ - PORTCFG_VP02MAP_PORTQ_gc = (0x0E<<0), /* Mapped To PORTQ */ - PORTCFG_VP02MAP_PORTR_gc = (0x0F<<0), /* Mapped To PORTR */ -} PORTCFG_VP02MAP_t; - -/* Virtual Port Mapping */ -typedef enum PORTCFG_VP13MAP_enum -{ - PORTCFG_VP13MAP_PORTA_gc = (0x00<<4), /* Mapped To PORTA */ - PORTCFG_VP13MAP_PORTB_gc = (0x01<<4), /* Mapped To PORTB */ - PORTCFG_VP13MAP_PORTC_gc = (0x02<<4), /* Mapped To PORTC */ - PORTCFG_VP13MAP_PORTD_gc = (0x03<<4), /* Mapped To PORTD */ - PORTCFG_VP13MAP_PORTE_gc = (0x04<<4), /* Mapped To PORTE */ - PORTCFG_VP13MAP_PORTF_gc = (0x05<<4), /* Mapped To PORTF */ - PORTCFG_VP13MAP_PORTG_gc = (0x06<<4), /* Mapped To PORTG */ - PORTCFG_VP13MAP_PORTH_gc = (0x07<<4), /* Mapped To PORTH */ - PORTCFG_VP13MAP_PORTJ_gc = (0x08<<4), /* Mapped To PORTJ */ - PORTCFG_VP13MAP_PORTK_gc = (0x09<<4), /* Mapped To PORTK */ - PORTCFG_VP13MAP_PORTL_gc = (0x0A<<4), /* Mapped To PORTL */ - PORTCFG_VP13MAP_PORTM_gc = (0x0B<<4), /* Mapped To PORTM */ - PORTCFG_VP13MAP_PORTN_gc = (0x0C<<4), /* Mapped To PORTN */ - PORTCFG_VP13MAP_PORTP_gc = (0x0D<<4), /* Mapped To PORTP */ - PORTCFG_VP13MAP_PORTQ_gc = (0x0E<<4), /* Mapped To PORTQ */ - PORTCFG_VP13MAP_PORTR_gc = (0x0F<<4), /* Mapped To PORTR */ -} PORTCFG_VP13MAP_t; - -/* System Clock Output Port */ -typedef enum PORTCFG_CLKOUT_enum -{ - PORTCFG_CLKOUT_OFF_gc = (0x00<<0), /* System Clock Output Disabled */ - PORTCFG_CLKOUT_PC7_gc = (0x01<<0), /* System Clock Output on Port C pin 7 */ - PORTCFG_CLKOUT_PD7_gc = (0x02<<0), /* System Clock Output on Port D pin 7 */ - PORTCFG_CLKOUT_PE7_gc = (0x03<<0), /* System Clock Output on Port E pin 7 */ -} PORTCFG_CLKOUT_t; - -/* Peripheral Clock Output Select */ -typedef enum PORTCFG_CLKOUTSEL_enum -{ - PORTCFG_CLKOUTSEL_CLK1X_gc = (0x00<<2), /* 1x Peripheral Clock Output to pin */ - PORTCFG_CLKOUTSEL_CLK2X_gc = (0x01<<2), /* 2x Peripheral Clock Output to pin */ - PORTCFG_CLKOUTSEL_CLK4X_gc = (0x02<<2), /* 4x Peripheral Clock Output to pin */ -} PORTCFG_CLKOUTSEL_t; - -/* Event Output Port */ -typedef enum PORTCFG_EVOUT_enum -{ - PORTCFG_EVOUT_OFF_gc = (0x00<<4), /* Event Output Disabled */ - PORTCFG_EVOUT_PC7_gc = (0x01<<4), /* Event Channel 7 Output on Port C pin 7 */ - PORTCFG_EVOUT_PD7_gc = (0x02<<4), /* Event Channel 7 Output on Port D pin 7 */ - PORTCFG_EVOUT_PE7_gc = (0x03<<4), /* Event Channel 7 Output on Port E pin 7 */ -} PORTCFG_EVOUT_t; - -/* Event Output Select */ -typedef enum PORTCFG_EVOUTSEL_enum -{ - PORTCFG_EVOUTSEL_0_gc = (0x00<<0), /* Event Channel 0 output to pin */ - PORTCFG_EVOUTSEL_1_gc = (0x01<<0), /* Event Channel 1 output to pin */ - PORTCFG_EVOUTSEL_2_gc = (0x02<<0), /* Event Channel 2 output to pin */ - PORTCFG_EVOUTSEL_3_gc = (0x03<<0), /* Event Channel 3 output to pin */ -} PORTCFG_EVOUTSEL_t; - - -/* --------------------------------------------------------------------------- -CRC - Cyclic Redundancy Checker --------------------------------------------------------------------------- -*/ - -/* Cyclic Redundancy Checker */ -typedef struct CRC_struct -{ - register8_t CTRL; /* Control Register */ - register8_t STATUS; /* Status Register */ - register8_t reserved_0x02; - register8_t DATAIN; /* Data Input */ - register8_t CHECKSUM0; /* Checksum byte 0 */ - register8_t CHECKSUM1; /* Checksum byte 1 */ - register8_t CHECKSUM2; /* Checksum byte 2 */ - register8_t CHECKSUM3; /* Checksum byte 3 */ -} CRC_t; - -/* Reset */ -typedef enum CRC_RESET_enum -{ - CRC_RESET_NO_gc = (0x00<<6), /* No Reset */ - CRC_RESET_RESET0_gc = (0x02<<6), /* Reset CRC with CHECKSUM to all zeros */ - CRC_RESET_RESET1_gc = (0x03<<6), /* Reset CRC with CHECKSUM to all ones */ -} CRC_RESET_t; - -/* Input Source */ -typedef enum CRC_SOURCE_enum -{ - CRC_SOURCE_DISABLE_gc = (0x00<<0), /* Disabled */ - CRC_SOURCE_IO_gc = (0x01<<0), /* I/O Interface */ - CRC_SOURCE_FLASH_gc = (0x02<<0), /* Flash */ -} CRC_SOURCE_t; - - -/* --------------------------------------------------------------------------- -EVSYS - Event System --------------------------------------------------------------------------- -*/ - -/* Event System */ -typedef struct EVSYS_struct -{ - register8_t CH0MUX; /* Event Channel 0 Multiplexer */ - register8_t CH1MUX; /* Event Channel 1 Multiplexer */ - register8_t CH2MUX; /* Event Channel 2 Multiplexer */ - register8_t CH3MUX; /* Event Channel 3 Multiplexer */ - register8_t reserved_0x04; - register8_t reserved_0x05; - register8_t reserved_0x06; - register8_t reserved_0x07; - register8_t CH0CTRL; /* Channel 0 Control Register */ - register8_t CH1CTRL; /* Channel 1 Control Register */ - register8_t CH2CTRL; /* Channel 2 Control Register */ - register8_t CH3CTRL; /* Channel 3 Control Register */ - register8_t reserved_0x0C; - register8_t reserved_0x0D; - register8_t reserved_0x0E; - register8_t reserved_0x0F; - register8_t STROBE; /* Event Strobe */ - register8_t DATA; /* Event Data */ -} EVSYS_t; - -/* Quadrature Decoder Index Recognition Mode */ -typedef enum EVSYS_QDIRM_enum -{ - EVSYS_QDIRM_00_gc = (0x00<<5), /* QDPH0 = 0, QDPH90 = 0 */ - EVSYS_QDIRM_01_gc = (0x01<<5), /* QDPH0 = 0, QDPH90 = 1 */ - EVSYS_QDIRM_10_gc = (0x02<<5), /* QDPH0 = 1, QDPH90 = 0 */ - EVSYS_QDIRM_11_gc = (0x03<<5), /* QDPH0 = 1, QDPH90 = 1 */ -} EVSYS_QDIRM_t; - -/* Digital filter coefficient */ -typedef enum EVSYS_DIGFILT_enum -{ - EVSYS_DIGFILT_1SAMPLE_gc = (0x00<<0), /* 1 SAMPLE */ - EVSYS_DIGFILT_2SAMPLES_gc = (0x01<<0), /* 2 SAMPLES */ - EVSYS_DIGFILT_3SAMPLES_gc = (0x02<<0), /* 3 SAMPLES */ - EVSYS_DIGFILT_4SAMPLES_gc = (0x03<<0), /* 4 SAMPLES */ - EVSYS_DIGFILT_5SAMPLES_gc = (0x04<<0), /* 5 SAMPLES */ - EVSYS_DIGFILT_6SAMPLES_gc = (0x05<<0), /* 6 SAMPLES */ - EVSYS_DIGFILT_7SAMPLES_gc = (0x06<<0), /* 7 SAMPLES */ - EVSYS_DIGFILT_8SAMPLES_gc = (0x07<<0), /* 8 SAMPLES */ -} EVSYS_DIGFILT_t; - -/* Event Channel multiplexer input selection */ -typedef enum EVSYS_CHMUX_enum -{ - EVSYS_CHMUX_OFF_gc = (0x00<<0), /* Off */ - EVSYS_CHMUX_RTC_OVF_gc = (0x08<<0), /* RTC Overflow */ - EVSYS_CHMUX_RTC_CMP_gc = (0x09<<0), /* RTC Compare Match */ - EVSYS_CHMUX_USB_gc = (0x0A<<0), /* USB Setup, SOF, CRC error and UNF/OVF */ - EVSYS_CHMUX_ACA_CH0_gc = (0x10<<0), /* Analog Comparator A Channel 0 */ - EVSYS_CHMUX_ACA_CH1_gc = (0x11<<0), /* Analog Comparator A Channel 1 */ - EVSYS_CHMUX_ACA_WIN_gc = (0x12<<0), /* Analog Comparator A Window */ - EVSYS_CHMUX_ADCA_CH0_gc = (0x20<<0), /* ADC A Channel */ - EVSYS_CHMUX_PORTA_PIN0_gc = (0x50<<0), /* Port A, Pin0 */ - EVSYS_CHMUX_PORTA_PIN1_gc = (0x51<<0), /* Port A, Pin1 */ - EVSYS_CHMUX_PORTA_PIN2_gc = (0x52<<0), /* Port A, Pin2 */ - EVSYS_CHMUX_PORTA_PIN3_gc = (0x53<<0), /* Port A, Pin3 */ - EVSYS_CHMUX_PORTA_PIN4_gc = (0x54<<0), /* Port A, Pin4 */ - EVSYS_CHMUX_PORTA_PIN5_gc = (0x55<<0), /* Port A, Pin5 */ - EVSYS_CHMUX_PORTA_PIN6_gc = (0x56<<0), /* Port A, Pin6 */ - EVSYS_CHMUX_PORTA_PIN7_gc = (0x57<<0), /* Port A, Pin7 */ - EVSYS_CHMUX_PORTB_PIN0_gc = (0x58<<0), /* Port B, Pin0 */ - EVSYS_CHMUX_PORTB_PIN1_gc = (0x59<<0), /* Port B, Pin1 */ - EVSYS_CHMUX_PORTB_PIN2_gc = (0x5A<<0), /* Port B, Pin2 */ - EVSYS_CHMUX_PORTB_PIN3_gc = (0x5B<<0), /* Port B, Pin3 */ - EVSYS_CHMUX_PORTB_PIN4_gc = (0x5C<<0), /* Port B, Pin4 */ - EVSYS_CHMUX_PORTB_PIN5_gc = (0x5D<<0), /* Port B, Pin5 */ - EVSYS_CHMUX_PORTB_PIN6_gc = (0x5E<<0), /* Port B, Pin6 */ - EVSYS_CHMUX_PORTB_PIN7_gc = (0x5F<<0), /* Port B, Pin7 */ - EVSYS_CHMUX_PORTC_PIN0_gc = (0x60<<0), /* Port C, Pin0 */ - EVSYS_CHMUX_PORTC_PIN1_gc = (0x61<<0), /* Port C, Pin1 */ - EVSYS_CHMUX_PORTC_PIN2_gc = (0x62<<0), /* Port C, Pin2 */ - EVSYS_CHMUX_PORTC_PIN3_gc = (0x63<<0), /* Port C, Pin3 */ - EVSYS_CHMUX_PORTC_PIN4_gc = (0x64<<0), /* Port C, Pin4 */ - EVSYS_CHMUX_PORTC_PIN5_gc = (0x65<<0), /* Port C, Pin5 */ - EVSYS_CHMUX_PORTC_PIN6_gc = (0x66<<0), /* Port C, Pin6 */ - EVSYS_CHMUX_PORTC_PIN7_gc = (0x67<<0), /* Port C, Pin7 */ - EVSYS_CHMUX_PORTD_PIN0_gc = (0x68<<0), /* Port D, Pin0 */ - EVSYS_CHMUX_PORTD_PIN1_gc = (0x69<<0), /* Port D, Pin1 */ - EVSYS_CHMUX_PORTD_PIN2_gc = (0x6A<<0), /* Port D, Pin2 */ - EVSYS_CHMUX_PORTD_PIN3_gc = (0x6B<<0), /* Port D, Pin3 */ - EVSYS_CHMUX_PORTD_PIN4_gc = (0x6C<<0), /* Port D, Pin4 */ - EVSYS_CHMUX_PORTD_PIN5_gc = (0x6D<<0), /* Port D, Pin5 */ - EVSYS_CHMUX_PORTD_PIN6_gc = (0x6E<<0), /* Port D, Pin6 */ - EVSYS_CHMUX_PORTD_PIN7_gc = (0x6F<<0), /* Port D, Pin7 */ - EVSYS_CHMUX_PORTE_PIN0_gc = (0x70<<0), /* Port E, Pin0 */ - EVSYS_CHMUX_PORTE_PIN1_gc = (0x71<<0), /* Port E, Pin1 */ - EVSYS_CHMUX_PORTE_PIN2_gc = (0x72<<0), /* Port E, Pin2 */ - EVSYS_CHMUX_PORTE_PIN3_gc = (0x73<<0), /* Port E, Pin3 */ - EVSYS_CHMUX_PORTE_PIN4_gc = (0x74<<0), /* Port E, Pin4 */ - EVSYS_CHMUX_PORTE_PIN5_gc = (0x75<<0), /* Port E, Pin5 */ - EVSYS_CHMUX_PORTE_PIN6_gc = (0x76<<0), /* Port E, Pin6 */ - EVSYS_CHMUX_PORTE_PIN7_gc = (0x77<<0), /* Port E, Pin7 */ - EVSYS_CHMUX_PORTF_PIN0_gc = (0x78<<0), /* Port F, Pin0 */ - EVSYS_CHMUX_PORTF_PIN1_gc = (0x79<<0), /* Port F, Pin1 */ - EVSYS_CHMUX_PORTF_PIN2_gc = (0x7A<<0), /* Port F, Pin2 */ - EVSYS_CHMUX_PORTF_PIN3_gc = (0x7B<<0), /* Port F, Pin3 */ - EVSYS_CHMUX_PORTF_PIN4_gc = (0x7C<<0), /* Port F, Pin4 */ - EVSYS_CHMUX_PORTF_PIN5_gc = (0x7D<<0), /* Port F, Pin5 */ - EVSYS_CHMUX_PORTF_PIN6_gc = (0x7E<<0), /* Port F, Pin6 */ - EVSYS_CHMUX_PORTF_PIN7_gc = (0x7F<<0), /* Port F, Pin7 */ - EVSYS_CHMUX_PRESCALER_1_gc = (0x80<<0), /* Prescaler, divide by 1 */ - EVSYS_CHMUX_PRESCALER_2_gc = (0x81<<0), /* Prescaler, divide by 2 */ - EVSYS_CHMUX_PRESCALER_4_gc = (0x82<<0), /* Prescaler, divide by 4 */ - EVSYS_CHMUX_PRESCALER_8_gc = (0x83<<0), /* Prescaler, divide by 8 */ - EVSYS_CHMUX_PRESCALER_16_gc = (0x84<<0), /* Prescaler, divide by 16 */ - EVSYS_CHMUX_PRESCALER_32_gc = (0x85<<0), /* Prescaler, divide by 32 */ - EVSYS_CHMUX_PRESCALER_64_gc = (0x86<<0), /* Prescaler, divide by 64 */ - EVSYS_CHMUX_PRESCALER_128_gc = (0x87<<0), /* Prescaler, divide by 128 */ - EVSYS_CHMUX_PRESCALER_256_gc = (0x88<<0), /* Prescaler, divide by 256 */ - EVSYS_CHMUX_PRESCALER_512_gc = (0x89<<0), /* Prescaler, divide by 512 */ - EVSYS_CHMUX_PRESCALER_1024_gc = (0x8A<<0), /* Prescaler, divide by 1024 */ - EVSYS_CHMUX_PRESCALER_2048_gc = (0x8B<<0), /* Prescaler, divide by 2048 */ - EVSYS_CHMUX_PRESCALER_4096_gc = (0x8C<<0), /* Prescaler, divide by 4096 */ - EVSYS_CHMUX_PRESCALER_8192_gc = (0x8D<<0), /* Prescaler, divide by 8192 */ - EVSYS_CHMUX_PRESCALER_16384_gc = (0x8E<<0), /* Prescaler, divide by 16384 */ - EVSYS_CHMUX_PRESCALER_32768_gc = (0x8F<<0), /* Prescaler, divide by 32768 */ - EVSYS_CHMUX_TCC0_OVF_gc = (0xC0<<0), /* Timer/Counter C0 Overflow */ - EVSYS_CHMUX_TCC0_ERR_gc = (0xC1<<0), /* Timer/Counter C0 Error */ - EVSYS_CHMUX_TCC0_CCA_gc = (0xC4<<0), /* Timer/Counter C0 Compare or Capture A */ - EVSYS_CHMUX_TCC0_CCB_gc = (0xC5<<0), /* Timer/Counter C0 Compare or Capture B */ - EVSYS_CHMUX_TCC0_CCC_gc = (0xC6<<0), /* Timer/Counter C0 Compare or Capture C */ - EVSYS_CHMUX_TCC0_CCD_gc = (0xC7<<0), /* Timer/Counter C0 Compare or Capture D */ - EVSYS_CHMUX_TCC1_OVF_gc = (0xC8<<0), /* Timer/Counter C1 Overflow */ - EVSYS_CHMUX_TCC1_ERR_gc = (0xC9<<0), /* Timer/Counter C1 Error */ - EVSYS_CHMUX_TCC1_CCA_gc = (0xCC<<0), /* Timer/Counter C1 Compare or Capture A */ - EVSYS_CHMUX_TCC1_CCB_gc = (0xCD<<0), /* Timer/Counter C1 Compare or Capture B */ - EVSYS_CHMUX_TCD0_OVF_gc = (0xD0<<0), /* Timer/Counter D0 Overflow */ - EVSYS_CHMUX_TCD0_ERR_gc = (0xD1<<0), /* Timer/Counter D0 Error */ - EVSYS_CHMUX_TCD0_CCA_gc = (0xD4<<0), /* Timer/Counter D0 Compare or Capture A */ - EVSYS_CHMUX_TCD0_CCB_gc = (0xD5<<0), /* Timer/Counter D0 Compare or Capture B */ - EVSYS_CHMUX_TCD0_CCC_gc = (0xD6<<0), /* Timer/Counter D0 Compare or Capture C */ - EVSYS_CHMUX_TCD0_CCD_gc = (0xD7<<0), /* Timer/Counter D0 Compare or Capture D */ - EVSYS_CHMUX_TCE0_OVF_gc = (0xE0<<0), /* Timer/Counter E0 Overflow */ - EVSYS_CHMUX_TCE0_ERR_gc = (0xE1<<0), /* Timer/Counter E0 Error */ - EVSYS_CHMUX_TCE0_CCA_gc = (0xE4<<0), /* Timer/Counter E0 Compare or Capture A */ - EVSYS_CHMUX_TCE0_CCB_gc = (0xE5<<0), /* Timer/Counter E0 Compare or Capture B */ - EVSYS_CHMUX_TCE0_CCC_gc = (0xE6<<0), /* Timer/Counter E0 Compare or Capture C */ - EVSYS_CHMUX_TCE0_CCD_gc = (0xE7<<0), /* Timer/Counter E0 Compare or Capture D */ - EVSYS_CHMUX_TCF0_OVF_gc = (0xF0<<0), /* Timer/Counter F0 Overflow */ - EVSYS_CHMUX_TCF0_ERR_gc = (0xF1<<0), /* Timer/Counter F0 Error */ - EVSYS_CHMUX_TCF0_CCA_gc = (0xF4<<0), /* Timer/Counter F0 Compare or Capture A */ - EVSYS_CHMUX_TCF0_CCB_gc = (0xF5<<0), /* Timer/Counter F0 Compare or Capture B */ - EVSYS_CHMUX_TCF0_CCC_gc = (0xF6<<0), /* Timer/Counter F0 Compare or Capture C */ - EVSYS_CHMUX_TCF0_CCD_gc = (0xF7<<0), /* Timer/Counter F0 Compare or Capture D */ -} EVSYS_CHMUX_t; - - -/* --------------------------------------------------------------------------- -NVM - Non Volatile Memory Controller --------------------------------------------------------------------------- -*/ - -/* Non-volatile Memory Controller */ -typedef struct NVM_struct -{ - register8_t ADDR0; /* Address Register 0 */ - register8_t ADDR1; /* Address Register 1 */ - register8_t ADDR2; /* Address Register 2 */ - register8_t reserved_0x03; - register8_t DATA0; /* Data Register 0 */ - register8_t DATA1; /* Data Register 1 */ - register8_t DATA2; /* Data Register 2 */ - register8_t reserved_0x07; - register8_t reserved_0x08; - register8_t reserved_0x09; - register8_t CMD; /* Command */ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t INTCTRL; /* Interrupt Control */ - register8_t reserved_0x0E; - register8_t STATUS; /* Status */ - register8_t LOCK_BITS; /* Lock Bits (Changed from LOCKBITS to avoid avr-libc collision) */ -} NVM_t; - -/* NVM Command */ -typedef enum NVM_CMD_enum -{ - NVM_CMD_NO_OPERATION_gc = (0x00<<0), /* Noop/Ordinary LPM */ - NVM_CMD_READ_USER_SIG_ROW_gc = (0x01<<0), /* Read user signature row */ - NVM_CMD_READ_CALIB_ROW_gc = (0x02<<0), /* Read calibration row */ - NVM_CMD_READ_EEPROM_gc = (0x06<<0), /* Read EEPROM */ - NVM_CMD_READ_FUSES_gc = (0x07<<0), /* Read fuse byte */ - NVM_CMD_WRITE_LOCK_BITS_gc = (0x08<<0), /* Write lock bits */ - NVM_CMD_ERASE_USER_SIG_ROW_gc = (0x18<<0), /* Erase user signature row */ - NVM_CMD_WRITE_USER_SIG_ROW_gc = (0x1A<<0), /* Write user signature row */ - NVM_CMD_ERASE_APP_gc = (0x20<<0), /* Erase Application Section */ - NVM_CMD_ERASE_APP_PAGE_gc = (0x22<<0), /* Erase Application Section page */ - NVM_CMD_LOAD_FLASH_BUFFER_gc = (0x23<<0), /* Load Flash page buffer */ - NVM_CMD_WRITE_APP_PAGE_gc = (0x24<<0), /* Write Application Section page */ - NVM_CMD_ERASE_WRITE_APP_PAGE_gc = (0x25<<0), /* Erase-and-write Application Section page */ - NVM_CMD_ERASE_FLASH_BUFFER_gc = (0x26<<0), /* Erase/flush Flash page buffer */ - NVM_CMD_ERASE_BOOT_PAGE_gc = (0x2A<<0), /* Erase Boot Section page */ - NVM_CMD_ERASE_FLASH_PAGE_gc = (0x2B<<0), /* Erase Flash Page */ - NVM_CMD_WRITE_BOOT_PAGE_gc = (0x2C<<0), /* Write Boot Section page */ - NVM_CMD_ERASE_WRITE_BOOT_PAGE_gc = (0x2D<<0), /* Erase-and-write Boot Section page */ - NVM_CMD_WRITE_FLASH_PAGE_gc = (0x2E<<0), /* Write Flash Page */ - NVM_CMD_ERASE_WRITE_FLASH_PAGE_gc = (0x2F<<0), /* Erase-and-write Flash Page */ - NVM_CMD_ERASE_EEPROM_gc = (0x30<<0), /* Erase EEPROM */ - NVM_CMD_ERASE_EEPROM_PAGE_gc = (0x32<<0), /* Erase EEPROM page */ - NVM_CMD_LOAD_EEPROM_BUFFER_gc = (0x33<<0), /* Load EEPROM page buffer */ - NVM_CMD_WRITE_EEPROM_PAGE_gc = (0x34<<0), /* Write EEPROM page */ - NVM_CMD_ERASE_WRITE_EEPROM_PAGE_gc = (0x35<<0), /* Erase-and-write EEPROM page */ - NVM_CMD_ERASE_EEPROM_BUFFER_gc = (0x36<<0), /* Erase/flush EEPROM page buffer */ - NVM_CMD_APP_CRC_gc = (0x38<<0), /* Application section CRC */ - NVM_CMD_BOOT_CRC_gc = (0x39<<0), /* Boot Section CRC */ - NVM_CMD_FLASH_RANGE_CRC_gc = (0x3A<<0), /* Flash Range CRC */ - NVM_CMD_CHIP_ERASE_gc = (0x40<<0), /* Erase Chip */ - NVM_CMD_READ_NVM_gc = (0x43<<0), /* Read NVM */ - NVM_CMD_WRITE_FUSE_gc = (0x4C<<0), /* Write Fuse byte */ - NVM_CMD_ERASE_BOOT_gc = (0x68<<0), /* Erase Boot Section */ - NVM_CMD_FLASH_CRC_gc = (0x78<<0), /* Flash CRC */ -} NVM_CMD_t; - -/* SPM ready interrupt level */ -typedef enum NVM_SPMLVL_enum -{ - NVM_SPMLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ - NVM_SPMLVL_LO_gc = (0x01<<2), /* Low level */ - NVM_SPMLVL_MED_gc = (0x02<<2), /* Medium level */ - NVM_SPMLVL_HI_gc = (0x03<<2), /* High level */ -} NVM_SPMLVL_t; - -/* EEPROM ready interrupt level */ -typedef enum NVM_EELVL_enum -{ - NVM_EELVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ - NVM_EELVL_LO_gc = (0x01<<0), /* Low level */ - NVM_EELVL_MED_gc = (0x02<<0), /* Medium level */ - NVM_EELVL_HI_gc = (0x03<<0), /* High level */ -} NVM_EELVL_t; - -/* Boot lock bits - boot setcion */ -typedef enum NVM_BLBB_enum -{ - NVM_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ - NVM_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ - NVM_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ - NVM_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ -} NVM_BLBB_t; - -/* Boot lock bits - application section */ -typedef enum NVM_BLBA_enum -{ - NVM_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ - NVM_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ - NVM_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ - NVM_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ -} NVM_BLBA_t; - -/* Boot lock bits - application table section */ -typedef enum NVM_BLBAT_enum -{ - NVM_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ - NVM_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ - NVM_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ - NVM_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ -} NVM_BLBAT_t; - -/* Lock bits */ -typedef enum NVM_LB_enum -{ - NVM_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ - NVM_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ - NVM_LB_NOLOCK_gc = (0x03<<0), /* No locks */ -} NVM_LB_t; - - -/* --------------------------------------------------------------------------- -ADC - Analog/Digital Converter --------------------------------------------------------------------------- -*/ - -/* ADC Channel */ -typedef struct ADC_CH_struct -{ - register8_t CTRL; /* Control Register */ - register8_t MUXCTRL; /* MUX Control */ - register8_t INTCTRL; /* Channel Interrupt Control Register */ - register8_t INTFLAGS; /* Interrupt Flags */ - _WORDREGISTER(RES); /* Channel Result */ - register8_t SCAN; /* Input Channel Scan */ - register8_t reserved_0x07; -} ADC_CH_t; - - -/* Analog-to-Digital Converter */ -typedef struct ADC_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t REFCTRL; /* Reference Control */ - register8_t EVCTRL; /* Event Control */ - register8_t PRESCALER; /* Clock Prescaler */ - register8_t reserved_0x05; - register8_t INTFLAGS; /* Interrupt Flags */ - register8_t TEMP; /* Temporary Register */ - register8_t reserved_0x08; - register8_t reserved_0x09; - register8_t reserved_0x0A; - register8_t reserved_0x0B; - _WORDREGISTER(CAL); /* Calibration Value */ - register8_t reserved_0x0E; - register8_t reserved_0x0F; - _WORDREGISTER(CH0RES); /* Channel 0 Result */ - register8_t reserved_0x12; - register8_t reserved_0x13; - register8_t reserved_0x14; - register8_t reserved_0x15; - register8_t reserved_0x16; - register8_t reserved_0x17; - _WORDREGISTER(CMP); /* Compare Value */ - register8_t reserved_0x1A; - register8_t reserved_0x1B; - register8_t reserved_0x1C; - register8_t reserved_0x1D; - register8_t reserved_0x1E; - register8_t reserved_0x1F; - ADC_CH_t CH0; /* ADC Channel 0 */ -} ADC_t; - -/* Current Limitation */ -typedef enum ADC_CURRLIMIT_enum -{ - ADC_CURRLIMIT_NO_gc = (0x00<<5), /* No current limit, 300ksps max sampling rate */ - ADC_CURRLIMIT_LOW_gc = (0x01<<5), /* Low current limit, 250ksps max sampling rate */ - ADC_CURRLIMIT_MED_gc = (0x02<<5), /* Medium current limit, 150ksps max sampling rate */ - ADC_CURRLIMIT_HIGH_gc = (0x03<<5), /* High current limit, 50ksps max sampling rate */ -} ADC_CURRLIMIT_t; - -/* Positive input multiplexer selection */ -typedef enum ADC_CH_MUXPOS_enum -{ - ADC_CH_MUXPOS_PIN0_gc = (0x00<<3), /* Input pin 0 */ - ADC_CH_MUXPOS_PIN1_gc = (0x01<<3), /* Input pin 1 */ - ADC_CH_MUXPOS_PIN2_gc = (0x02<<3), /* Input pin 2 */ - ADC_CH_MUXPOS_PIN3_gc = (0x03<<3), /* Input pin 3 */ - ADC_CH_MUXPOS_PIN4_gc = (0x04<<3), /* Input pin 4 */ - ADC_CH_MUXPOS_PIN5_gc = (0x05<<3), /* Input pin 5 */ - ADC_CH_MUXPOS_PIN6_gc = (0x06<<3), /* Input pin 6 */ - ADC_CH_MUXPOS_PIN7_gc = (0x07<<3), /* Input pin 7 */ - ADC_CH_MUXPOS_PIN8_gc = (0x08<<3), /* Input pin 8 */ - ADC_CH_MUXPOS_PIN9_gc = (0x09<<3), /* Input pin 9 */ - ADC_CH_MUXPOS_PIN10_gc = (0x0A<<3), /* Input pin 10 */ - ADC_CH_MUXPOS_PIN11_gc = (0x0B<<3), /* Input pin 11 */ - ADC_CH_MUXPOS_PIN12_gc = (0x0C<<3), /* Input pin 12 */ - ADC_CH_MUXPOS_PIN13_gc = (0x0D<<3), /* Input pin 13 */ - ADC_CH_MUXPOS_PIN14_gc = (0x0E<<3), /* Input pin 14 */ - ADC_CH_MUXPOS_PIN15_gc = (0x0F<<3), /* Input pin 15 */ -} ADC_CH_MUXPOS_t; - -/* Internal input multiplexer selections */ -typedef enum ADC_CH_MUXINT_enum -{ - ADC_CH_MUXINT_TEMP_gc = (0x00<<3), /* Temperature Reference */ - ADC_CH_MUXINT_BANDGAP_gc = (0x01<<3), /* Bandgap Reference */ - ADC_CH_MUXINT_SCALEDVCC_gc = (0x02<<3), /* 1/10 scaled VCC */ -} ADC_CH_MUXINT_t; - -/* Negative input multiplexer selection */ -typedef enum ADC_CH_MUXNEG_enum -{ - ADC_CH_MUXNEG_PIN0_gc = (0x00<<0), /* Input pin 0 */ - ADC_CH_MUXNEG_PIN1_gc = (0x01<<0), /* Input pin 1 */ - ADC_CH_MUXNEG_PIN2_gc = (0x02<<0), /* Input pin 2 */ - ADC_CH_MUXNEG_PIN3_gc = (0x03<<0), /* Input pin 3 */ - ADC_CH_MUXNEG_PIN4_gc = (0x00<<0), /* Input pin 4 */ - ADC_CH_MUXNEG_PIN5_gc = (0x01<<0), /* Input pin 5 */ - ADC_CH_MUXNEG_PIN6_gc = (0x02<<0), /* Input pin 6 */ - ADC_CH_MUXNEG_PIN7_gc = (0x03<<0), /* Input pin 7 */ -} ADC_CH_MUXNEG_t; - -/* Input mode */ -typedef enum ADC_CH_INPUTMODE_enum -{ - ADC_CH_INPUTMODE_INTERNAL_gc = (0x00<<0), /* Internal inputs, no gain */ - ADC_CH_INPUTMODE_SINGLEENDED_gc = (0x01<<0), /* Single-ended input, no gain */ - ADC_CH_INPUTMODE_DIFF_gc = (0x02<<0), /* Differential input, no gain */ - ADC_CH_INPUTMODE_DIFFWGAIN_gc = (0x03<<0), /* Differential input, with gain */ -} ADC_CH_INPUTMODE_t; - -/* Gain factor */ -typedef enum ADC_CH_GAIN_enum -{ - ADC_CH_GAIN_1X_gc = (0x00<<2), /* 1x gain */ - ADC_CH_GAIN_2X_gc = (0x01<<2), /* 2x gain */ - ADC_CH_GAIN_4X_gc = (0x02<<2), /* 4x gain */ - ADC_CH_GAIN_8X_gc = (0x03<<2), /* 8x gain */ - ADC_CH_GAIN_16X_gc = (0x04<<2), /* 16x gain */ - ADC_CH_GAIN_32X_gc = (0x05<<2), /* 32x gain */ - ADC_CH_GAIN_64X_gc = (0x06<<2), /* 64x gain */ - ADC_CH_GAIN_DIV2_gc = (0x07<<2), /* x/2 gain */ -} ADC_CH_GAIN_t; - -/* Conversion result resolution */ -typedef enum ADC_RESOLUTION_enum -{ - ADC_RESOLUTION_12BIT_gc = (0x00<<1), /* 12-bit right-adjusted result */ - ADC_RESOLUTION_8BIT_gc = (0x02<<1), /* 8-bit right-adjusted result */ - ADC_RESOLUTION_LEFT12BIT_gc = (0x03<<1), /* 12-bit left-adjusted result */ -} ADC_RESOLUTION_t; - -/* Voltage reference selection */ -typedef enum ADC_REFSEL_enum -{ - ADC_REFSEL_INT1V_gc = (0x00<<4), /* Internal 1V */ - ADC_REFSEL_INTVCC_gc = (0x01<<4), /* Internal VCC / 1.6 */ - ADC_REFSEL_AREFA_gc = (0x02<<4), /* External reference on PORT A */ - ADC_REFSEL_AREFB_gc = (0x03<<4), /* External reference on PORT B */ - ADC_REFSEL_INTVCC2_gc = (0x04<<4), /* Internal VCC / 2 */ -} ADC_REFSEL_t; - -/* Event channel input selection */ -typedef enum ADC_EVSEL_enum -{ - ADC_EVSEL_0_gc = (0x00<<3), /* Event Channel 0 */ - ADC_EVSEL_1_gc = (0x01<<3), /* Event Channel 1 */ - ADC_EVSEL_2_gc = (0x02<<3), /* Event Channel 2 */ - ADC_EVSEL_3_gc = (0x03<<3), /* Event Channel 3 */ -} ADC_EVSEL_t; - -/* Event action selection */ -typedef enum ADC_EVACT_enum -{ - ADC_EVACT_NONE_gc = (0x00<<0), /* No event action */ - ADC_EVACT_CH0_gc = (0x01<<0), /* First event triggers channel 0 */ - ADC_EVACT_SYNCSWEEP_gc = (0x06<<0), /* The ADC is flushed and restarted for accurate timing */ -} ADC_EVACT_t; - -/* Interupt mode */ -typedef enum ADC_CH_INTMODE_enum -{ - ADC_CH_INTMODE_COMPLETE_gc = (0x00<<2), /* Interrupt on conversion complete */ - ADC_CH_INTMODE_BELOW_gc = (0x01<<2), /* Interrupt on result below compare value */ - ADC_CH_INTMODE_ABOVE_gc = (0x03<<2), /* Interrupt on result above compare value */ -} ADC_CH_INTMODE_t; - -/* Interrupt level */ -typedef enum ADC_CH_INTLVL_enum -{ - ADC_CH_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ - ADC_CH_INTLVL_LO_gc = (0x01<<0), /* Low level */ - ADC_CH_INTLVL_MED_gc = (0x02<<0), /* Medium level */ - ADC_CH_INTLVL_HI_gc = (0x03<<0), /* High level */ -} ADC_CH_INTLVL_t; - -/* Clock prescaler */ -typedef enum ADC_PRESCALER_enum -{ - ADC_PRESCALER_DIV4_gc = (0x00<<0), /* Divide clock by 4 */ - ADC_PRESCALER_DIV8_gc = (0x01<<0), /* Divide clock by 8 */ - ADC_PRESCALER_DIV16_gc = (0x02<<0), /* Divide clock by 16 */ - ADC_PRESCALER_DIV32_gc = (0x03<<0), /* Divide clock by 32 */ - ADC_PRESCALER_DIV64_gc = (0x04<<0), /* Divide clock by 64 */ - ADC_PRESCALER_DIV128_gc = (0x05<<0), /* Divide clock by 128 */ - ADC_PRESCALER_DIV256_gc = (0x06<<0), /* Divide clock by 256 */ - ADC_PRESCALER_DIV512_gc = (0x07<<0), /* Divide clock by 512 */ -} ADC_PRESCALER_t; - - -/* --------------------------------------------------------------------------- -AC - Analog Comparator --------------------------------------------------------------------------- -*/ - -/* Analog Comparator */ -typedef struct AC_struct -{ - register8_t AC0CTRL; /* Analog Comparator 0 Control */ - register8_t AC1CTRL; /* Analog Comparator 1 Control */ - register8_t AC0MUXCTRL; /* Analog Comparator 0 MUX Control */ - register8_t AC1MUXCTRL; /* Analog Comparator 1 MUX Control */ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t WINCTRL; /* Window Mode Control */ - register8_t STATUS; /* Status */ -} AC_t; - -/* Interrupt mode */ -typedef enum AC_INTMODE_enum -{ - AC_INTMODE_BOTHEDGES_gc = (0x00<<6), /* Interrupt on both edges */ - AC_INTMODE_FALLING_gc = (0x02<<6), /* Interrupt on falling edge */ - AC_INTMODE_RISING_gc = (0x03<<6), /* Interrupt on rising edge */ -} AC_INTMODE_t; - -/* Interrupt level */ -typedef enum AC_INTLVL_enum -{ - AC_INTLVL_OFF_gc = (0x00<<4), /* Interrupt disabled */ - AC_INTLVL_LO_gc = (0x01<<4), /* Low level */ - AC_INTLVL_MED_gc = (0x02<<4), /* Medium level */ - AC_INTLVL_HI_gc = (0x03<<4), /* High level */ -} AC_INTLVL_t; - -/* Hysteresis mode selection */ -typedef enum AC_HYSMODE_enum -{ - AC_HYSMODE_NO_gc = (0x00<<1), /* No hysteresis */ - AC_HYSMODE_SMALL_gc = (0x01<<1), /* Small hysteresis */ - AC_HYSMODE_LARGE_gc = (0x02<<1), /* Large hysteresis */ -} AC_HYSMODE_t; - -/* Positive input multiplexer selection */ -typedef enum AC_MUXPOS_enum -{ - AC_MUXPOS_PIN0_gc = (0x00<<3), /* Pin 0 */ - AC_MUXPOS_PIN1_gc = (0x01<<3), /* Pin 1 */ - AC_MUXPOS_PIN2_gc = (0x02<<3), /* Pin 2 */ - AC_MUXPOS_PIN3_gc = (0x03<<3), /* Pin 3 */ - AC_MUXPOS_PIN4_gc = (0x04<<3), /* Pin 4 */ - AC_MUXPOS_PIN5_gc = (0x05<<3), /* Pin 5 */ - AC_MUXPOS_PIN6_gc = (0x06<<3), /* Pin 6 */ -} AC_MUXPOS_t; - -/* Negative input multiplexer selection */ -typedef enum AC_MUXNEG_enum -{ - AC_MUXNEG_PIN0_gc = (0x00<<0), /* Pin 0 */ - AC_MUXNEG_PIN1_gc = (0x01<<0), /* Pin 1 */ - AC_MUXNEG_PIN3_gc = (0x02<<0), /* Pin 3 */ - AC_MUXNEG_PIN5_gc = (0x03<<0), /* Pin 5 */ - AC_MUXNEG_PIN7_gc = (0x04<<0), /* Pin 7 */ - AC_MUXNEG_BANDGAP_gc = (0x06<<0), /* Bandgap Reference */ - AC_MUXNEG_SCALER_gc = (0x07<<0), /* Internal voltage scaler */ -} AC_MUXNEG_t; - -/* Windows interrupt mode */ -typedef enum AC_WINTMODE_enum -{ - AC_WINTMODE_ABOVE_gc = (0x00<<2), /* Interrupt on above window */ - AC_WINTMODE_INSIDE_gc = (0x01<<2), /* Interrupt on inside window */ - AC_WINTMODE_BELOW_gc = (0x02<<2), /* Interrupt on below window */ - AC_WINTMODE_OUTSIDE_gc = (0x03<<2), /* Interrupt on outside window */ -} AC_WINTMODE_t; - -/* Window interrupt level */ -typedef enum AC_WINTLVL_enum -{ - AC_WINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ - AC_WINTLVL_LO_gc = (0x01<<0), /* Low priority */ - AC_WINTLVL_MED_gc = (0x02<<0), /* Medium priority */ - AC_WINTLVL_HI_gc = (0x03<<0), /* High priority */ -} AC_WINTLVL_t; - -/* Window mode state */ -typedef enum AC_WSTATE_enum -{ - AC_WSTATE_ABOVE_gc = (0x00<<6), /* Signal above window */ - AC_WSTATE_INSIDE_gc = (0x01<<6), /* Signal inside window */ - AC_WSTATE_BELOW_gc = (0x02<<6), /* Signal below window */ -} AC_WSTATE_t; - - -/* --------------------------------------------------------------------------- -RTC - Real-Time Counter --------------------------------------------------------------------------- -*/ - -/* Real-Time Counter */ -typedef struct RTC_struct -{ - register8_t CTRL; /* Control Register */ - register8_t STATUS; /* Status Register */ - register8_t INTCTRL; /* Interrupt Control Register */ - register8_t INTFLAGS; /* Interrupt Flags */ - register8_t TEMP; /* Temporary register */ - register8_t reserved_0x05; - register8_t reserved_0x06; - register8_t reserved_0x07; - _WORDREGISTER(CNT); /* Count Register */ - _WORDREGISTER(PER); /* Period Register */ - _WORDREGISTER(COMP); /* Compare Register */ -} RTC_t; - -/* Prescaler Factor */ -typedef enum RTC_PRESCALER_enum -{ - RTC_PRESCALER_OFF_gc = (0x00<<0), /* RTC Off */ - RTC_PRESCALER_DIV1_gc = (0x01<<0), /* RTC Clock */ - RTC_PRESCALER_DIV2_gc = (0x02<<0), /* RTC Clock / 2 */ - RTC_PRESCALER_DIV8_gc = (0x03<<0), /* RTC Clock / 8 */ - RTC_PRESCALER_DIV16_gc = (0x04<<0), /* RTC Clock / 16 */ - RTC_PRESCALER_DIV64_gc = (0x05<<0), /* RTC Clock / 64 */ - RTC_PRESCALER_DIV256_gc = (0x06<<0), /* RTC Clock / 256 */ - RTC_PRESCALER_DIV1024_gc = (0x07<<0), /* RTC Clock / 1024 */ -} RTC_PRESCALER_t; - -/* Compare Interrupt level */ -typedef enum RTC_COMPINTLVL_enum -{ - RTC_COMPINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ - RTC_COMPINTLVL_LO_gc = (0x01<<2), /* Low Level */ - RTC_COMPINTLVL_MED_gc = (0x02<<2), /* Medium Level */ - RTC_COMPINTLVL_HI_gc = (0x03<<2), /* High Level */ -} RTC_COMPINTLVL_t; - -/* Overflow Interrupt level */ -typedef enum RTC_OVFINTLVL_enum -{ - RTC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - RTC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ - RTC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ - RTC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ -} RTC_OVFINTLVL_t; - - -/* --------------------------------------------------------------------------- -TWI - Two-Wire Interface --------------------------------------------------------------------------- -*/ - -/* */ -typedef struct TWI_MASTER_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t CTRLC; /* Control Register C */ - register8_t STATUS; /* Status Register */ - register8_t BAUD; /* Baurd Rate Control Register */ - register8_t ADDR; /* Address Register */ - register8_t DATA; /* Data Register */ -} TWI_MASTER_t; - - -/* */ -typedef struct TWI_SLAVE_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t STATUS; /* Status Register */ - register8_t ADDR; /* Address Register */ - register8_t DATA; /* Data Register */ - register8_t ADDRMASK; /* Address Mask Register */ -} TWI_SLAVE_t; - - -/* Two-Wire Interface */ -typedef struct TWI_struct -{ - register8_t CTRL; /* TWI Common Control Register */ - TWI_MASTER_t MASTER; /* TWI master module */ - TWI_SLAVE_t SLAVE; /* TWI slave module */ -} TWI_t; - -/* SDA Hold Time */ -typedef enum TWI_SDAHOLD_enum -{ - TWI_SDAHOLD_OFF_gc = (0x00<<1), /* SDA Hold Time off */ - TWI_SDAHOLD_50NS_gc = (0x01<<1), /* SDA Hold Time 50 ns */ - TWI_SDAHOLD_300NS_gc = (0x02<<1), /* SDA Hold Time 300 ns */ - TWI_SDAHOLD_400NS_gc = (0x03<<1), /* SDA Hold Time 400 ns */ -} TWI_SDAHOLD_t; - -/* Master Interrupt Level */ -typedef enum TWI_MASTER_INTLVL_enum -{ - TWI_MASTER_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ - TWI_MASTER_INTLVL_LO_gc = (0x01<<6), /* Low Level */ - TWI_MASTER_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ - TWI_MASTER_INTLVL_HI_gc = (0x03<<6), /* High Level */ -} TWI_MASTER_INTLVL_t; - -/* Inactive Timeout */ -typedef enum TWI_MASTER_TIMEOUT_enum -{ - TWI_MASTER_TIMEOUT_DISABLED_gc = (0x00<<2), /* Bus Timeout Disabled */ - TWI_MASTER_TIMEOUT_50US_gc = (0x01<<2), /* 50 Microseconds */ - TWI_MASTER_TIMEOUT_100US_gc = (0x02<<2), /* 100 Microseconds */ - TWI_MASTER_TIMEOUT_200US_gc = (0x03<<2), /* 200 Microseconds */ -} TWI_MASTER_TIMEOUT_t; - -/* Master Command */ -typedef enum TWI_MASTER_CMD_enum -{ - TWI_MASTER_CMD_NOACT_gc = (0x00<<0), /* No Action */ - TWI_MASTER_CMD_REPSTART_gc = (0x01<<0), /* Issue Repeated Start Condition */ - TWI_MASTER_CMD_RECVTRANS_gc = (0x02<<0), /* Receive or Transmit Data */ - TWI_MASTER_CMD_STOP_gc = (0x03<<0), /* Issue Stop Condition */ -} TWI_MASTER_CMD_t; - -/* Master Bus State */ -typedef enum TWI_MASTER_BUSSTATE_enum -{ - TWI_MASTER_BUSSTATE_UNKNOWN_gc = (0x00<<0), /* Unknown Bus State */ - TWI_MASTER_BUSSTATE_IDLE_gc = (0x01<<0), /* Bus is Idle */ - TWI_MASTER_BUSSTATE_OWNER_gc = (0x02<<0), /* This Module Controls The Bus */ - TWI_MASTER_BUSSTATE_BUSY_gc = (0x03<<0), /* The Bus is Busy */ -} TWI_MASTER_BUSSTATE_t; - -/* Slave Interrupt Level */ -typedef enum TWI_SLAVE_INTLVL_enum -{ - TWI_SLAVE_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ - TWI_SLAVE_INTLVL_LO_gc = (0x01<<6), /* Low Level */ - TWI_SLAVE_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ - TWI_SLAVE_INTLVL_HI_gc = (0x03<<6), /* High Level */ -} TWI_SLAVE_INTLVL_t; - -/* Slave Command */ -typedef enum TWI_SLAVE_CMD_enum -{ - TWI_SLAVE_CMD_NOACT_gc = (0x00<<0), /* No Action */ - TWI_SLAVE_CMD_COMPTRANS_gc = (0x02<<0), /* Used To Complete a Transaction */ - TWI_SLAVE_CMD_RESPONSE_gc = (0x03<<0), /* Used in Response to Address/Data Interrupt */ -} TWI_SLAVE_CMD_t; - - -/* --------------------------------------------------------------------------- -USB - USB --------------------------------------------------------------------------- -*/ - -/* USB Endpoint */ -typedef struct USB_EP_struct -{ - register8_t STATUS; /* Endpoint Status */ - register8_t CTRL; /* Endpoint Control */ - _WORDREGISTER(CNT); /* USB Endpoint Counter */ - _WORDREGISTER(DATAPTR); /* Data Pointer */ - _WORDREGISTER(AUXDATA); /* Auxiliary Data */ -} USB_EP_t; - - -/* Universal Serial Bus */ -typedef struct USB_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t STATUS; /* Status Register */ - register8_t ADDR; /* Address Register */ - register8_t FIFOWP; /* FIFO Write Pointer Register */ - register8_t FIFORP; /* FIFO Read Pointer Register */ - _WORDREGISTER(EPPTR); /* Endpoint Configuration Table Pointer */ - register8_t INTCTRLA; /* Interrupt Control Register A */ - register8_t INTCTRLB; /* Interrupt Control Register B */ - register8_t INTFLAGSACLR; /* Clear Interrupt Flag Register A */ - register8_t INTFLAGSASET; /* Set Interrupt Flag Register A */ - register8_t INTFLAGSBCLR; /* Clear Interrupt Flag Register B */ - register8_t INTFLAGSBSET; /* Set Interrupt Flag Register B */ - register8_t reserved_0x0E; - register8_t reserved_0x0F; - register8_t reserved_0x10; - register8_t reserved_0x11; - register8_t reserved_0x12; - register8_t reserved_0x13; - register8_t reserved_0x14; - register8_t reserved_0x15; - register8_t reserved_0x16; - register8_t reserved_0x17; - register8_t reserved_0x18; - register8_t reserved_0x19; - register8_t reserved_0x1A; - register8_t reserved_0x1B; - register8_t reserved_0x1C; - register8_t reserved_0x1D; - register8_t reserved_0x1E; - register8_t reserved_0x1F; - register8_t reserved_0x20; - register8_t reserved_0x21; - register8_t reserved_0x22; - register8_t reserved_0x23; - register8_t reserved_0x24; - register8_t reserved_0x25; - register8_t reserved_0x26; - register8_t reserved_0x27; - register8_t reserved_0x28; - register8_t reserved_0x29; - register8_t reserved_0x2A; - register8_t reserved_0x2B; - register8_t reserved_0x2C; - register8_t reserved_0x2D; - register8_t reserved_0x2E; - register8_t reserved_0x2F; - register8_t reserved_0x30; - register8_t reserved_0x31; - register8_t reserved_0x32; - register8_t reserved_0x33; - register8_t reserved_0x34; - register8_t reserved_0x35; - register8_t reserved_0x36; - register8_t reserved_0x37; - register8_t reserved_0x38; - register8_t reserved_0x39; - register8_t CAL0; /* Calibration Byte 0 */ - register8_t CAL1; /* Calibration Byte 1 */ -} USB_t; - - -/* USB Endpoint Table */ -typedef struct USB_EP_TABLE_struct -{ - USB_EP_t EP0OUT; /* Endpoint 0 */ - USB_EP_t EP0IN; /* Endpoint 0 */ - USB_EP_t EP1OUT; /* Endpoint 1 */ - USB_EP_t EP1IN; /* Endpoint 1 */ - USB_EP_t EP2OUT; /* Endpoint 2 */ - USB_EP_t EP2IN; /* Endpoint 2 */ - USB_EP_t EP3OUT; /* Endpoint 3 */ - USB_EP_t EP3IN; /* Endpoint 3 */ - USB_EP_t EP4OUT; /* Endpoint 4 */ - USB_EP_t EP4IN; /* Endpoint 4 */ - USB_EP_t EP5OUT; /* Endpoint 5 */ - USB_EP_t EP5IN; /* Endpoint 5 */ - USB_EP_t EP6OUT; /* Endpoint 6 */ - USB_EP_t EP6IN; /* Endpoint 6 */ - USB_EP_t EP7OUT; /* Endpoint 7 */ - USB_EP_t EP7IN; /* Endpoint 7 */ - USB_EP_t EP8OUT; /* Endpoint 8 */ - USB_EP_t EP8IN; /* Endpoint 8 */ - USB_EP_t EP9OUT; /* Endpoint 9 */ - USB_EP_t EP9IN; /* Endpoint 9 */ - USB_EP_t EP10OUT; /* Endpoint 10 */ - USB_EP_t EP10IN; /* Endpoint 10 */ - USB_EP_t EP11OUT; /* Endpoint 11 */ - USB_EP_t EP11IN; /* Endpoint 11 */ - USB_EP_t EP12OUT; /* Endpoint 12 */ - USB_EP_t EP12IN; /* Endpoint 12 */ - USB_EP_t EP13OUT; /* Endpoint 13 */ - USB_EP_t EP13IN; /* Endpoint 13 */ - USB_EP_t EP14OUT; /* Endpoint 14 */ - USB_EP_t EP14IN; /* Endpoint 14 */ - USB_EP_t EP15OUT; /* Endpoint 15 */ - USB_EP_t EP15IN; /* Endpoint 15 */ - register8_t reserved_0x100; - register8_t reserved_0x101; - register8_t reserved_0x102; - register8_t reserved_0x103; - register8_t reserved_0x104; - register8_t reserved_0x105; - register8_t reserved_0x106; - register8_t reserved_0x107; - register8_t reserved_0x108; - register8_t reserved_0x109; - register8_t reserved_0x10A; - register8_t reserved_0x10B; - register8_t reserved_0x10C; - register8_t reserved_0x10D; - register8_t reserved_0x10E; - register8_t reserved_0x10F; - register8_t FRAMENUML; /* Frame Number Low Byte */ - register8_t FRAMENUMH; /* Frame Number High Byte */ -} USB_EP_TABLE_t; - -/* Interrupt level */ -typedef enum USB_INTLVL_enum -{ - USB_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ - USB_INTLVL_LO_gc = (0x01<<0), /* Low level */ - USB_INTLVL_MED_gc = (0x02<<0), /* Medium level */ - USB_INTLVL_HI_gc = (0x03<<0), /* High level */ -} USB_INTLVL_t; - -/* USB Endpoint Type */ -typedef enum USB_EP_TYPE_enum -{ - USB_EP_TYPE_DISABLE_gc = (0x00<<6), /* Endpoint Disabled */ - USB_EP_TYPE_CONTROL_gc = (0x01<<6), /* Control */ - USB_EP_TYPE_BULK_gc = (0x02<<6), /* Bulk/Interrupt */ - USB_EP_TYPE_ISOCHRONOUS_gc = (0x03<<6), /* Isochronous */ -} USB_EP_TYPE_t; - -/* USB Endpoint Buffersize */ -typedef enum USB_EP_BUFSIZE_enum -{ - USB_EP_BUFSIZE_8_gc = (0x00<<0), /* 8 bytes buffer size */ - USB_EP_BUFSIZE_16_gc = (0x01<<0), /* 16 bytes buffer size */ - USB_EP_BUFSIZE_32_gc = (0x02<<0), /* 32 bytes buffer size */ - USB_EP_BUFSIZE_64_gc = (0x03<<0), /* 64 bytes buffer size */ - USB_EP_BUFSIZE_128_gc = (0x04<<0), /* 128 bytes buffer size */ - USB_EP_BUFSIZE_256_gc = (0x05<<0), /* 256 bytes buffer size */ - USB_EP_BUFSIZE_512_gc = (0x06<<0), /* 512 bytes buffer size */ - USB_EP_BUFSIZE_1023_gc = (0x07<<0), /* 1023 bytes buffer size */ -} USB_EP_BUFSIZE_t; - - -/* --------------------------------------------------------------------------- -PORT - I/O Port Configuration --------------------------------------------------------------------------- -*/ - -/* I/O Ports */ -typedef struct PORT_struct -{ - register8_t DIR; /* I/O Port Data Direction */ - register8_t DIRSET; /* I/O Port Data Direction Set */ - register8_t DIRCLR; /* I/O Port Data Direction Clear */ - register8_t DIRTGL; /* I/O Port Data Direction Toggle */ - register8_t OUT; /* I/O Port Output */ - register8_t OUTSET; /* I/O Port Output Set */ - register8_t OUTCLR; /* I/O Port Output Clear */ - register8_t OUTTGL; /* I/O Port Output Toggle */ - register8_t IN; /* I/O port Input */ - register8_t INTCTRL; /* Interrupt Control Register */ - register8_t INT0MASK; /* Port Interrupt 0 Mask */ - register8_t INT1MASK; /* Port Interrupt 1 Mask */ - register8_t INTFLAGS; /* Interrupt Flag Register */ - register8_t reserved_0x0D; - register8_t REMAP; /* I/O Port Pin Remap Register */ - register8_t reserved_0x0F; - register8_t PIN0CTRL; /* Pin 0 Control Register */ - register8_t PIN1CTRL; /* Pin 1 Control Register */ - register8_t PIN2CTRL; /* Pin 2 Control Register */ - register8_t PIN3CTRL; /* Pin 3 Control Register */ - register8_t PIN4CTRL; /* Pin 4 Control Register */ - register8_t PIN5CTRL; /* Pin 5 Control Register */ - register8_t PIN6CTRL; /* Pin 6 Control Register */ - register8_t PIN7CTRL; /* Pin 7 Control Register */ -} PORT_t; - -/* Port Interrupt 0 Level */ -typedef enum PORT_INT0LVL_enum -{ - PORT_INT0LVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - PORT_INT0LVL_LO_gc = (0x01<<0), /* Low Level */ - PORT_INT0LVL_MED_gc = (0x02<<0), /* Medium Level */ - PORT_INT0LVL_HI_gc = (0x03<<0), /* High Level */ -} PORT_INT0LVL_t; - -/* Port Interrupt 1 Level */ -typedef enum PORT_INT1LVL_enum -{ - PORT_INT1LVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ - PORT_INT1LVL_LO_gc = (0x01<<2), /* Low Level */ - PORT_INT1LVL_MED_gc = (0x02<<2), /* Medium Level */ - PORT_INT1LVL_HI_gc = (0x03<<2), /* High Level */ -} PORT_INT1LVL_t; - -/* Output/Pull Configuration */ -typedef enum PORT_OPC_enum -{ - PORT_OPC_TOTEM_gc = (0x00<<3), /* Totempole */ - PORT_OPC_BUSKEEPER_gc = (0x01<<3), /* Totempole w/ Bus keeper on Input and Output */ - PORT_OPC_PULLDOWN_gc = (0x02<<3), /* Totempole w/ Pull-down on Input */ - PORT_OPC_PULLUP_gc = (0x03<<3), /* Totempole w/ Pull-up on Input */ - PORT_OPC_WIREDOR_gc = (0x04<<3), /* Wired OR */ - PORT_OPC_WIREDAND_gc = (0x05<<3), /* Wired AND */ - PORT_OPC_WIREDORPULL_gc = (0x06<<3), /* Wired OR w/ Pull-down */ - PORT_OPC_WIREDANDPULL_gc = (0x07<<3), /* Wired AND w/ Pull-up */ -} PORT_OPC_t; - -/* Input/Sense Configuration */ -typedef enum PORT_ISC_enum -{ - PORT_ISC_BOTHEDGES_gc = (0x00<<0), /* Sense Both Edges */ - PORT_ISC_RISING_gc = (0x01<<0), /* Sense Rising Edge */ - PORT_ISC_FALLING_gc = (0x02<<0), /* Sense Falling Edge */ - PORT_ISC_LEVEL_gc = (0x03<<0), /* Sense Level (Transparent For Events) */ - PORT_ISC_INPUT_DISABLE_gc = (0x07<<0), /* Disable Digital Input Buffer */ -} PORT_ISC_t; - - -/* --------------------------------------------------------------------------- -TC - 16-bit Timer/Counter With PWM --------------------------------------------------------------------------- -*/ - -/* 16-bit Timer/Counter 0 */ -typedef struct TC0_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t CTRLC; /* Control register C */ - register8_t CTRLD; /* Control Register D */ - register8_t CTRLE; /* Control Register E */ - register8_t reserved_0x05; - register8_t INTCTRLA; /* Interrupt Control Register A */ - register8_t INTCTRLB; /* Interrupt Control Register B */ - register8_t CTRLFCLR; /* Control Register F Clear */ - register8_t CTRLFSET; /* Control Register F Set */ - register8_t CTRLGCLR; /* Control Register G Clear */ - register8_t CTRLGSET; /* Control Register G Set */ - register8_t INTFLAGS; /* Interrupt Flag Register */ - register8_t reserved_0x0D; - register8_t reserved_0x0E; - register8_t TEMP; /* Temporary Register For 16-bit Access */ - register8_t reserved_0x10; - register8_t reserved_0x11; - register8_t reserved_0x12; - register8_t reserved_0x13; - register8_t reserved_0x14; - register8_t reserved_0x15; - register8_t reserved_0x16; - register8_t reserved_0x17; - register8_t reserved_0x18; - register8_t reserved_0x19; - register8_t reserved_0x1A; - register8_t reserved_0x1B; - register8_t reserved_0x1C; - register8_t reserved_0x1D; - register8_t reserved_0x1E; - register8_t reserved_0x1F; - _WORDREGISTER(CNT); /* Count */ - register8_t reserved_0x22; - register8_t reserved_0x23; - register8_t reserved_0x24; - register8_t reserved_0x25; - _WORDREGISTER(PER); /* Period */ - _WORDREGISTER(CCA); /* Compare or Capture A */ - _WORDREGISTER(CCB); /* Compare or Capture B */ - _WORDREGISTER(CCC); /* Compare or Capture C */ - _WORDREGISTER(CCD); /* Compare or Capture D */ - register8_t reserved_0x30; - register8_t reserved_0x31; - register8_t reserved_0x32; - register8_t reserved_0x33; - register8_t reserved_0x34; - register8_t reserved_0x35; - _WORDREGISTER(PERBUF); /* Period Buffer */ - _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ - _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ - _WORDREGISTER(CCCBUF); /* Compare Or Capture C Buffer */ - _WORDREGISTER(CCDBUF); /* Compare Or Capture D Buffer */ -} TC0_t; - - -/* 16-bit Timer/Counter 1 */ -typedef struct TC1_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t CTRLC; /* Control register C */ - register8_t CTRLD; /* Control Register D */ - register8_t CTRLE; /* Control Register E */ - register8_t reserved_0x05; - register8_t INTCTRLA; /* Interrupt Control Register A */ - register8_t INTCTRLB; /* Interrupt Control Register B */ - register8_t CTRLFCLR; /* Control Register F Clear */ - register8_t CTRLFSET; /* Control Register F Set */ - register8_t CTRLGCLR; /* Control Register G Clear */ - register8_t CTRLGSET; /* Control Register G Set */ - register8_t INTFLAGS; /* Interrupt Flag Register */ - register8_t reserved_0x0D; - register8_t reserved_0x0E; - register8_t TEMP; /* Temporary Register For 16-bit Access */ - register8_t reserved_0x10; - register8_t reserved_0x11; - register8_t reserved_0x12; - register8_t reserved_0x13; - register8_t reserved_0x14; - register8_t reserved_0x15; - register8_t reserved_0x16; - register8_t reserved_0x17; - register8_t reserved_0x18; - register8_t reserved_0x19; - register8_t reserved_0x1A; - register8_t reserved_0x1B; - register8_t reserved_0x1C; - register8_t reserved_0x1D; - register8_t reserved_0x1E; - register8_t reserved_0x1F; - _WORDREGISTER(CNT); /* Count */ - register8_t reserved_0x22; - register8_t reserved_0x23; - register8_t reserved_0x24; - register8_t reserved_0x25; - _WORDREGISTER(PER); /* Period */ - _WORDREGISTER(CCA); /* Compare or Capture A */ - _WORDREGISTER(CCB); /* Compare or Capture B */ - register8_t reserved_0x2C; - register8_t reserved_0x2D; - register8_t reserved_0x2E; - register8_t reserved_0x2F; - register8_t reserved_0x30; - register8_t reserved_0x31; - register8_t reserved_0x32; - register8_t reserved_0x33; - register8_t reserved_0x34; - register8_t reserved_0x35; - _WORDREGISTER(PERBUF); /* Period Buffer */ - _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ - _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ -} TC1_t; - -/* Clock Selection */ -typedef enum TC_CLKSEL_enum -{ - TC_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */ - TC_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */ - TC_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */ - TC_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */ - TC_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */ - TC_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */ - TC_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */ - TC_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */ - TC_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */ - TC_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */ - TC_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */ - TC_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */ -} TC_CLKSEL_t; - -/* Waveform Generation Mode */ -typedef enum TC_WGMODE_enum -{ - TC_WGMODE_NORMAL_gc = (0x00<<0), /* Normal Mode */ - TC_WGMODE_FRQ_gc = (0x01<<0), /* Frequency Generation Mode */ - TC_WGMODE_SINGLESLOPE_gc = (0x03<<0), /* Single Slope */ - TC_WGMODE_SS_gc = (0x03<<0), /* Single Slope */ - TC_WGMODE_DSTOP_gc = (0x05<<0), /* Dual Slope, Update on TOP */ - TC_WGMODE_DS_T_gc = (0x05<<0), /* Dual Slope, Update on TOP */ - TC_WGMODE_DSBOTH_gc = (0x06<<0), /* Dual Slope, Update on both TOP and BOTTOM */ - TC_WGMODE_DS_TB_gc = (0x06<<0), /* Dual Slope, Update on both TOP and BOTTOM */ - TC_WGMODE_DSBOTTOM_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */ - TC_WGMODE_DS_B_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */ -} TC_WGMODE_t; - -/* Byte Mode */ -typedef enum TC_BYTEM_enum -{ - TC_BYTEM_NORMAL_gc = (0x00<<0), /* 16-bit mode */ - TC_BYTEM_BYTEMODE_gc = (0x01<<0), /* Timer/Counter operating in byte mode only */ - TC_BYTEM_SPLITMODE_gc = (0x02<<0), /* Timer/Counter split into two 8-bit Counters (TC2) */ -} TC_BYTEM_t; - -/* Event Action */ -typedef enum TC_EVACT_enum -{ - TC_EVACT_OFF_gc = (0x00<<5), /* No Event Action */ - TC_EVACT_CAPT_gc = (0x01<<5), /* Input Capture */ - TC_EVACT_UPDOWN_gc = (0x02<<5), /* Externally Controlled Up/Down Count */ - TC_EVACT_QDEC_gc = (0x03<<5), /* Quadrature Decode */ - TC_EVACT_RESTART_gc = (0x04<<5), /* Restart */ - TC_EVACT_FRQ_gc = (0x05<<5), /* Frequency Capture */ - TC_EVACT_PW_gc = (0x06<<5), /* Pulse-width Capture */ -} TC_EVACT_t; - -/* Event Selection */ -typedef enum TC_EVSEL_enum -{ - TC_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ - TC_EVSEL_CH0_gc = (0x08<<0), /* Event Channel 0 */ - TC_EVSEL_CH1_gc = (0x09<<0), /* Event Channel 1 */ - TC_EVSEL_CH2_gc = (0x0A<<0), /* Event Channel 2 */ - TC_EVSEL_CH3_gc = (0x0B<<0), /* Event Channel 3 */ -} TC_EVSEL_t; - -/* Error Interrupt Level */ -typedef enum TC_ERRINTLVL_enum -{ - TC_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ - TC_ERRINTLVL_LO_gc = (0x01<<2), /* Low Level */ - TC_ERRINTLVL_MED_gc = (0x02<<2), /* Medium Level */ - TC_ERRINTLVL_HI_gc = (0x03<<2), /* High Level */ -} TC_ERRINTLVL_t; - -/* Overflow Interrupt Level */ -typedef enum TC_OVFINTLVL_enum -{ - TC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - TC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ - TC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ - TC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ -} TC_OVFINTLVL_t; - -/* Compare or Capture D Interrupt Level */ -typedef enum TC_CCDINTLVL_enum -{ - TC_CCDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ - TC_CCDINTLVL_LO_gc = (0x01<<6), /* Low Level */ - TC_CCDINTLVL_MED_gc = (0x02<<6), /* Medium Level */ - TC_CCDINTLVL_HI_gc = (0x03<<6), /* High Level */ -} TC_CCDINTLVL_t; - -/* Compare or Capture C Interrupt Level */ -typedef enum TC_CCCINTLVL_enum -{ - TC_CCCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ - TC_CCCINTLVL_LO_gc = (0x01<<4), /* Low Level */ - TC_CCCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ - TC_CCCINTLVL_HI_gc = (0x03<<4), /* High Level */ -} TC_CCCINTLVL_t; - -/* Compare or Capture B Interrupt Level */ -typedef enum TC_CCBINTLVL_enum -{ - TC_CCBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ - TC_CCBINTLVL_LO_gc = (0x01<<2), /* Low Level */ - TC_CCBINTLVL_MED_gc = (0x02<<2), /* Medium Level */ - TC_CCBINTLVL_HI_gc = (0x03<<2), /* High Level */ -} TC_CCBINTLVL_t; - -/* Compare or Capture A Interrupt Level */ -typedef enum TC_CCAINTLVL_enum -{ - TC_CCAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - TC_CCAINTLVL_LO_gc = (0x01<<0), /* Low Level */ - TC_CCAINTLVL_MED_gc = (0x02<<0), /* Medium Level */ - TC_CCAINTLVL_HI_gc = (0x03<<0), /* High Level */ -} TC_CCAINTLVL_t; - -/* Timer/Counter Command */ -typedef enum TC_CMD_enum -{ - TC_CMD_NONE_gc = (0x00<<2), /* No Command */ - TC_CMD_UPDATE_gc = (0x01<<2), /* Force Update */ - TC_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ - TC_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ -} TC_CMD_t; - - -/* --------------------------------------------------------------------------- -TC2 - 16-bit Timer/Counter type 2 --------------------------------------------------------------------------- -*/ - -/* 16-bit Timer/Counter type 2 */ -typedef struct TC2_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t CTRLC; /* Control register C */ - register8_t reserved_0x03; - register8_t CTRLE; /* Control Register E */ - register8_t reserved_0x05; - register8_t INTCTRLA; /* Interrupt Control Register A */ - register8_t INTCTRLB; /* Interrupt Control Register B */ - register8_t reserved_0x08; - register8_t CTRLF; /* Control Register F */ - register8_t reserved_0x0A; - register8_t reserved_0x0B; - register8_t INTFLAGS; /* Interrupt Flag Register */ - register8_t reserved_0x0D; - register8_t reserved_0x0E; - register8_t reserved_0x0F; - register8_t reserved_0x10; - register8_t reserved_0x11; - register8_t reserved_0x12; - register8_t reserved_0x13; - register8_t reserved_0x14; - register8_t reserved_0x15; - register8_t reserved_0x16; - register8_t reserved_0x17; - register8_t reserved_0x18; - register8_t reserved_0x19; - register8_t reserved_0x1A; - register8_t reserved_0x1B; - register8_t reserved_0x1C; - register8_t reserved_0x1D; - register8_t reserved_0x1E; - register8_t reserved_0x1F; - register8_t LCNT; /* Low Byte Count */ - register8_t HCNT; /* High Byte Count */ - register8_t reserved_0x22; - register8_t reserved_0x23; - register8_t reserved_0x24; - register8_t reserved_0x25; - register8_t LPER; /* Low Byte Period */ - register8_t HPER; /* High Byte Period */ - register8_t LCMPA; /* Low Byte Compare A */ - register8_t HCMPA; /* High Byte Compare A */ - register8_t LCMPB; /* Low Byte Compare B */ - register8_t HCMPB; /* High Byte Compare B */ - register8_t LCMPC; /* Low Byte Compare C */ - register8_t HCMPC; /* High Byte Compare C */ - register8_t LCMPD; /* Low Byte Compare D */ - register8_t HCMPD; /* High Byte Compare D */ -} TC2_t; - -/* Clock Selection */ -typedef enum TC2_CLKSEL_enum -{ - TC2_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */ - TC2_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */ - TC2_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */ - TC2_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */ - TC2_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */ - TC2_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */ - TC2_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */ - TC2_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */ - TC2_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */ - TC2_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */ - TC2_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */ - TC2_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */ -} TC2_CLKSEL_t; - -/* Byte Mode */ -typedef enum TC2_BYTEM_enum -{ - TC2_BYTEM_NORMAL_gc = (0x00<<0), /* 16-bit mode */ - TC2_BYTEM_BYTEMODE_gc = (0x01<<0), /* Timer/Counter operating in byte mode only (TC2) */ - TC2_BYTEM_SPLITMODE_gc = (0x02<<0), /* Timer/Counter split into two 8-bit Counters */ -} TC2_BYTEM_t; - -/* High Byte Underflow Interrupt Level */ -typedef enum TC2_HUNFINTLVL_enum -{ - TC2_HUNFINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ - TC2_HUNFINTLVL_LO_gc = (0x01<<2), /* Low Level */ - TC2_HUNFINTLVL_MED_gc = (0x02<<2), /* Medium Level */ - TC2_HUNFINTLVL_HI_gc = (0x03<<2), /* High Level */ -} TC2_HUNFINTLVL_t; - -/* Low Byte Underflow Interrupt Level */ -typedef enum TC2_LUNFINTLVL_enum -{ - TC2_LUNFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - TC2_LUNFINTLVL_LO_gc = (0x01<<0), /* Low Level */ - TC2_LUNFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ - TC2_LUNFINTLVL_HI_gc = (0x03<<0), /* High Level */ -} TC2_LUNFINTLVL_t; - -/* Low Byte Compare D Interrupt Level */ -typedef enum TC2_LCMPDINTLVL_enum -{ - TC2_LCMPDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ - TC2_LCMPDINTLVL_LO_gc = (0x01<<6), /* Low Level */ - TC2_LCMPDINTLVL_MED_gc = (0x02<<6), /* Medium Level */ - TC2_LCMPDINTLVL_HI_gc = (0x03<<6), /* High Level */ -} TC2_LCMPDINTLVL_t; - -/* Low Byte Compare C Interrupt Level */ -typedef enum TC2_LCMPCINTLVL_enum -{ - TC2_LCMPCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ - TC2_LCMPCINTLVL_LO_gc = (0x01<<4), /* Low Level */ - TC2_LCMPCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ - TC2_LCMPCINTLVL_HI_gc = (0x03<<4), /* High Level */ -} TC2_LCMPCINTLVL_t; - -/* Low Byte Compare B Interrupt Level */ -typedef enum TC2_LCMPBINTLVL_enum -{ - TC2_LCMPBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ - TC2_LCMPBINTLVL_LO_gc = (0x01<<2), /* Low Level */ - TC2_LCMPBINTLVL_MED_gc = (0x02<<2), /* Medium Level */ - TC2_LCMPBINTLVL_HI_gc = (0x03<<2), /* High Level */ -} TC2_LCMPBINTLVL_t; - -/* Low Byte Compare A Interrupt Level */ -typedef enum TC2_LCMPAINTLVL_enum -{ - TC2_LCMPAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - TC2_LCMPAINTLVL_LO_gc = (0x01<<0), /* Low Level */ - TC2_LCMPAINTLVL_MED_gc = (0x02<<0), /* Medium Level */ - TC2_LCMPAINTLVL_HI_gc = (0x03<<0), /* High Level */ -} TC2_LCMPAINTLVL_t; - -/* Timer/Counter Command */ -typedef enum TC2_CMD_enum -{ - TC2_CMD_NONE_gc = (0x00<<2), /* No Command */ - TC2_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ - TC2_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ -} TC2_CMD_t; - -/* Timer/Counter Command */ -typedef enum TC2_CMDEN_enum -{ - TC2_CMDEN_LOW_gc = (0x01<<0), /* Low Byte Timer/Counter */ - TC2_CMDEN_HIGH_gc = (0x02<<0), /* High Byte Timer/Counter */ - TC2_CMDEN_BOTH_gc = (0x03<<0), /* Both Low Byte and High Byte Timer/Counters */ -} TC2_CMDEN_t; - - -/* --------------------------------------------------------------------------- -AWEX - Timer/Counter Advanced Waveform Extension --------------------------------------------------------------------------- -*/ - -/* Advanced Waveform Extension */ -typedef struct AWEX_struct -{ - register8_t CTRL; /* Control Register */ - register8_t reserved_0x01; - register8_t FDEMASK; /* Fault Detection Event Mask */ - register8_t FDCTRL; /* Fault Detection Control Register */ - register8_t STATUS; /* Status Register */ - register8_t STATUSSET; /* Status Set Register */ - register8_t DTBOTH; /* Dead Time Both Sides */ - register8_t DTBOTHBUF; /* Dead Time Both Sides Buffer */ - register8_t DTLS; /* Dead Time Low Side */ - register8_t DTHS; /* Dead Time High Side */ - register8_t DTLSBUF; /* Dead Time Low Side Buffer */ - register8_t DTHSBUF; /* Dead Time High Side Buffer */ - register8_t OUTOVEN; /* Output Override Enable */ -} AWEX_t; - -/* Fault Detect Action */ -typedef enum AWEX_FDACT_enum -{ - AWEX_FDACT_NONE_gc = (0x00<<0), /* No Fault Protection */ - AWEX_FDACT_CLEAROE_gc = (0x01<<0), /* Clear Output Enable Bits */ - AWEX_FDACT_CLEARDIR_gc = (0x03<<0), /* Clear I/O Port Direction Bits */ -} AWEX_FDACT_t; - - -/* --------------------------------------------------------------------------- -HIRES - Timer/Counter High-Resolution Extension --------------------------------------------------------------------------- -*/ - -/* High-Resolution Extension */ -typedef struct HIRES_struct -{ - register8_t CTRLA; /* Control Register */ -} HIRES_t; - -/* High Resolution Enable */ -typedef enum HIRES_HREN_enum -{ - HIRES_HREN_NONE_gc = (0x00<<0), /* No Fault Protection */ - HIRES_HREN_TC0_gc = (0x01<<0), /* Enable High Resolution on Timer/Counter 0 */ - HIRES_HREN_TC1_gc = (0x02<<0), /* Enable High Resolution on Timer/Counter 1 */ - HIRES_HREN_BOTH_gc = (0x03<<0), /* Enable High Resolution both Timer/Counters */ -} HIRES_HREN_t; - - -/* --------------------------------------------------------------------------- -USART - Universal Asynchronous Receiver-Transmitter --------------------------------------------------------------------------- -*/ - -/* Universal Synchronous/Asynchronous Receiver/Transmitter */ -typedef struct USART_struct -{ - register8_t DATA; /* Data Register */ - register8_t STATUS; /* Status Register */ - register8_t reserved_0x02; - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t CTRLC; /* Control Register C */ - register8_t BAUDCTRLA; /* Baud Rate Control Register A */ - register8_t BAUDCTRLB; /* Baud Rate Control Register B */ -} USART_t; - -/* Receive Complete Interrupt level */ -typedef enum USART_RXCINTLVL_enum -{ - USART_RXCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ - USART_RXCINTLVL_LO_gc = (0x01<<4), /* Low Level */ - USART_RXCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ - USART_RXCINTLVL_HI_gc = (0x03<<4), /* High Level */ -} USART_RXCINTLVL_t; - -/* Transmit Complete Interrupt level */ -typedef enum USART_TXCINTLVL_enum -{ - USART_TXCINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ - USART_TXCINTLVL_LO_gc = (0x01<<2), /* Low Level */ - USART_TXCINTLVL_MED_gc = (0x02<<2), /* Medium Level */ - USART_TXCINTLVL_HI_gc = (0x03<<2), /* High Level */ -} USART_TXCINTLVL_t; - -/* Data Register Empty Interrupt level */ -typedef enum USART_DREINTLVL_enum -{ - USART_DREINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - USART_DREINTLVL_LO_gc = (0x01<<0), /* Low Level */ - USART_DREINTLVL_MED_gc = (0x02<<0), /* Medium Level */ - USART_DREINTLVL_HI_gc = (0x03<<0), /* High Level */ -} USART_DREINTLVL_t; - -/* Character Size */ -typedef enum USART_CHSIZE_enum -{ - USART_CHSIZE_5BIT_gc = (0x00<<0), /* Character size: 5 bit */ - USART_CHSIZE_6BIT_gc = (0x01<<0), /* Character size: 6 bit */ - USART_CHSIZE_7BIT_gc = (0x02<<0), /* Character size: 7 bit */ - USART_CHSIZE_8BIT_gc = (0x03<<0), /* Character size: 8 bit */ - USART_CHSIZE_9BIT_gc = (0x07<<0), /* Character size: 9 bit */ -} USART_CHSIZE_t; - -/* Communication Mode */ -typedef enum USART_CMODE_enum -{ - USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6), /* Asynchronous Mode */ - USART_CMODE_SYNCHRONOUS_gc = (0x01<<6), /* Synchronous Mode */ - USART_CMODE_IRDA_gc = (0x02<<6), /* IrDA Mode */ - USART_CMODE_MSPI_gc = (0x03<<6), /* Master SPI Mode */ -} USART_CMODE_t; - -/* Parity Mode */ -typedef enum USART_PMODE_enum -{ - USART_PMODE_DISABLED_gc = (0x00<<4), /* No Parity */ - USART_PMODE_EVEN_gc = (0x02<<4), /* Even Parity */ - USART_PMODE_ODD_gc = (0x03<<4), /* Odd Parity */ -} USART_PMODE_t; - - -/* --------------------------------------------------------------------------- -SPI - Serial Peripheral Interface --------------------------------------------------------------------------- -*/ - -/* Serial Peripheral Interface */ -typedef struct SPI_struct -{ - register8_t CTRL; /* Control Register */ - register8_t INTCTRL; /* Interrupt Control Register */ - register8_t STATUS; /* Status Register */ - register8_t DATA; /* Data Register */ -} SPI_t; - -/* SPI Mode */ -typedef enum SPI_MODE_enum -{ - SPI_MODE_0_gc = (0x00<<2), /* SPI Mode 0 */ - SPI_MODE_1_gc = (0x01<<2), /* SPI Mode 1 */ - SPI_MODE_2_gc = (0x02<<2), /* SPI Mode 2 */ - SPI_MODE_3_gc = (0x03<<2), /* SPI Mode 3 */ -} SPI_MODE_t; - -/* Prescaler setting */ -typedef enum SPI_PRESCALER_enum -{ - SPI_PRESCALER_DIV4_gc = (0x00<<0), /* System Clock / 4 */ - SPI_PRESCALER_DIV16_gc = (0x01<<0), /* System Clock / 16 */ - SPI_PRESCALER_DIV64_gc = (0x02<<0), /* System Clock / 64 */ - SPI_PRESCALER_DIV128_gc = (0x03<<0), /* System Clock / 128 */ -} SPI_PRESCALER_t; - -/* Interrupt level */ -typedef enum SPI_INTLVL_enum -{ - SPI_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - SPI_INTLVL_LO_gc = (0x01<<0), /* Low Level */ - SPI_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ - SPI_INTLVL_HI_gc = (0x03<<0), /* High Level */ -} SPI_INTLVL_t; - - -/* --------------------------------------------------------------------------- -IRCOM - IR Communication Module --------------------------------------------------------------------------- -*/ - -/* IR Communication Module */ -typedef struct IRCOM_struct -{ - register8_t CTRL; /* Control Register */ - register8_t TXPLCTRL; /* IrDA Transmitter Pulse Length Control Register */ - register8_t RXPLCTRL; /* IrDA Receiver Pulse Length Control Register */ -} IRCOM_t; - -/* Event channel selection */ -typedef enum IRDA_EVSEL_enum -{ - IRDA_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ - IRDA_EVSEL_0_gc = (0x08<<0), /* Event Channel 0 */ - IRDA_EVSEL_1_gc = (0x09<<0), /* Event Channel 1 */ - IRDA_EVSEL_2_gc = (0x0A<<0), /* Event Channel 2 */ - IRDA_EVSEL_3_gc = (0x0B<<0), /* Event Channel 3 */ -} IRDA_EVSEL_t; - - -/* --------------------------------------------------------------------------- -FUSE - Fuses and Lockbits --------------------------------------------------------------------------- -*/ - -/* Fuses */ -typedef struct NVM_FUSES_struct -{ - register8_t reserved_0x00; - register8_t FUSEBYTE1; /* Watchdog Configuration */ - register8_t FUSEBYTE2; /* Reset Configuration */ - register8_t reserved_0x03; - register8_t FUSEBYTE4; /* Start-up Configuration */ - register8_t FUSEBYTE5; /* EESAVE and BOD Level */ -} NVM_FUSES_t; - -/* Boot Loader Section Reset Vector */ -typedef enum BOOTRST_enum -{ - BOOTRST_BOOTLDR_gc = (0x00<<6), /* Boot Loader Reset */ - BOOTRST_APPLICATION_gc = (0x01<<6), /* Application Reset */ -} BOOTRST_t; - -/* Timer Oscillator pin location */ -typedef enum TOSCSEL_enum -{ - TOSCSEL_ALTERNATE_gc = (0x00<<5), /* TOSC1 / TOSC2 on separate pins */ - TOSCSEL_XTAL_gc = (0x01<<5), /* TOSC1 / TOSC2 shared with XTAL1 / XTAL2 */ -} TOSCSEL_t; - -/* BOD operation */ -typedef enum BOD_enum -{ - BOD_SAMPLED_gc = (0x01<<0), /* BOD enabled in sampled mode */ - BOD_CONTINUOUS_gc = (0x02<<0), /* BOD enabled continuously */ - BOD_DISABLED_gc = (0x03<<0), /* BOD Disabled */ -} BOD_t; - -/* BOD operation */ -typedef enum BODACT_enum -{ - BODACT_SAMPLED_gc = (0x01<<4), /* BOD enabled in sampled mode */ - BODACT_CONTINUOUS_gc = (0x02<<4), /* BOD enabled continuously */ - BODACT_DISABLED_gc = (0x03<<4), /* BOD Disabled */ -} BODACT_t; - -/* Watchdog (Window) Timeout Period */ -typedef enum WD_enum -{ - WD_8CLK_gc = (0x00<<4), /* 8 cycles (8ms @ 3.3V) */ - WD_16CLK_gc = (0x01<<4), /* 16 cycles (16ms @ 3.3V) */ - WD_32CLK_gc = (0x02<<4), /* 32 cycles (32ms @ 3.3V) */ - WD_64CLK_gc = (0x03<<4), /* 64 cycles (64ms @ 3.3V) */ - WD_128CLK_gc = (0x04<<4), /* 128 cycles (0.125s @ 3.3V) */ - WD_256CLK_gc = (0x05<<4), /* 256 cycles (0.25s @ 3.3V) */ - WD_512CLK_gc = (0x06<<4), /* 512 cycles (0.5s @ 3.3V) */ - WD_1KCLK_gc = (0x07<<4), /* 1K cycles (1s @ 3.3V) */ - WD_2KCLK_gc = (0x08<<4), /* 2K cycles (2s @ 3.3V) */ - WD_4KCLK_gc = (0x09<<4), /* 4K cycles (4s @ 3.3V) */ - WD_8KCLK_gc = (0x0A<<4), /* 8K cycles (8s @ 3.3V) */ -} WD_t; - -/* Watchdog (Window) Timeout Period */ -typedef enum WDP_enum -{ - WDP_8CLK_gc = (0x00<<0), /* 8 cycles (8ms @ 3.3V) */ - WDP_16CLK_gc = (0x01<<0), /* 16 cycles (16ms @ 3.3V) */ - WDP_32CLK_gc = (0x02<<0), /* 32 cycles (32ms @ 3.3V) */ - WDP_64CLK_gc = (0x03<<0), /* 64 cycles (64ms @ 3.3V) */ - WDP_128CLK_gc = (0x04<<0), /* 128 cycles (0.125s @ 3.3V) */ - WDP_256CLK_gc = (0x05<<0), /* 256 cycles (0.25s @ 3.3V) */ - WDP_512CLK_gc = (0x06<<0), /* 512 cycles (0.5s @ 3.3V) */ - WDP_1KCLK_gc = (0x07<<0), /* 1K cycles (1s @ 3.3V) */ - WDP_2KCLK_gc = (0x08<<0), /* 2K cycles (2s @ 3.3V) */ - WDP_4KCLK_gc = (0x09<<0), /* 4K cycles (4s @ 3.3V) */ - WDP_8KCLK_gc = (0x0A<<0), /* 8K cycles (8s @ 3.3V) */ -} WDP_t; - -/* Start-up Time */ -typedef enum SUT_enum -{ - SUT_0MS_gc = (0x03<<2), /* 0 ms */ - SUT_4MS_gc = (0x01<<2), /* 4 ms */ - SUT_64MS_gc = (0x00<<2), /* 64 ms */ -} SUT_t; - -/* Brownout Detection Voltage Level */ -typedef enum BODLVL_enum -{ - BODLVL_1V6_gc = (0x07<<0), /* 1.6 V */ - BODLVL_1V8_gc = (0x06<<0), /* 1.8 V */ - BODLVL_2V0_gc = (0x05<<0), /* 2.0 V */ - BODLVL_2V2_gc = (0x04<<0), /* 2.2 V */ - BODLVL_2V4_gc = (0x03<<0), /* 2.4 V */ - BODLVL_2V6_gc = (0x02<<0), /* 2.6 V */ - BODLVL_2V8_gc = (0x01<<0), /* 2.8 V */ - BODLVL_3V0_gc = (0x00<<0), /* 3.0 V */ -} BODLVL_t; - - -/* --------------------------------------------------------------------------- -LOCKBIT - Fuses and Lockbits --------------------------------------------------------------------------- -*/ - -/* Lock Bits */ -typedef struct NVM_LOCKBITS_struct -{ - register8_t LOCK_BITS; /* Lock Bits (Changed from LOCKBITS to avoid avr-libc collision) */ -} NVM_LOCKBITS_t; - -/* Boot lock bits - boot setcion */ -typedef enum FUSE_BLBB_enum -{ - FUSE_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ - FUSE_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ - FUSE_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ - FUSE_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ -} FUSE_BLBB_t; - -/* Boot lock bits - application section */ -typedef enum FUSE_BLBA_enum -{ - FUSE_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ - FUSE_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ - FUSE_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ - FUSE_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ -} FUSE_BLBA_t; - -/* Boot lock bits - application table section */ -typedef enum FUSE_BLBAT_enum -{ - FUSE_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ - FUSE_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ - FUSE_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ - FUSE_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ -} FUSE_BLBAT_t; - -/* Lock bits */ -typedef enum FUSE_LB_enum -{ - FUSE_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ - FUSE_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ - FUSE_LB_NOLOCK_gc = (0x03<<0), /* No locks */ -} FUSE_LB_t; - - -/* --------------------------------------------------------------------------- -SIGROW - Signature Row --------------------------------------------------------------------------- -*/ - -/* Production Signatures */ -typedef struct NVM_PROD_SIGNATURES_struct -{ - register8_t RCOSC2M; /* RCOSC 2 MHz Calibration Value B */ - register8_t RCOSC2MA; /* RCOSC 2 MHz Calibration Value A */ - register8_t RCOSC32K; /* RCOSC 32.768 kHz Calibration Value */ - register8_t RCOSC32M; /* RCOSC 32 MHz Calibration Value B */ - register8_t RCOSC32MA; /* RCOSC 32 MHz Calibration Value A */ - register8_t reserved_0x05; - register8_t reserved_0x06; - register8_t reserved_0x07; - register8_t LOTNUM0; /* Lot Number Byte 0, ASCII */ - register8_t LOTNUM1; /* Lot Number Byte 1, ASCII */ - register8_t LOTNUM2; /* Lot Number Byte 2, ASCII */ - register8_t LOTNUM3; /* Lot Number Byte 3, ASCII */ - register8_t LOTNUM4; /* Lot Number Byte 4, ASCII */ - register8_t LOTNUM5; /* Lot Number Byte 5, ASCII */ - register8_t reserved_0x0E; - register8_t reserved_0x0F; - register8_t WAFNUM; /* Wafer Number */ - register8_t reserved_0x11; - register8_t COORDX0; /* Wafer Coordinate X Byte 0 */ - register8_t COORDX1; /* Wafer Coordinate X Byte 1 */ - register8_t COORDY0; /* Wafer Coordinate Y Byte 0 */ - register8_t COORDY1; /* Wafer Coordinate Y Byte 1 */ - register8_t reserved_0x16; - register8_t reserved_0x17; - register8_t reserved_0x18; - register8_t reserved_0x19; - register8_t USBCAL0; /* USB Calibration Byte 0 */ - register8_t USBCAL1; /* USB Calibration Byte 1 */ - register8_t USBRCOSC; /* USB RCOSC Calibration Value B */ - register8_t USBRCOSCA; /* USB RCOSC Calibration Value A */ - register8_t reserved_0x1E; - register8_t reserved_0x1F; - register8_t ADCACAL0; /* ADCA Calibration Byte 0 */ - register8_t ADCACAL1; /* ADCA Calibration Byte 1 */ - register8_t reserved_0x22; - register8_t reserved_0x23; - register8_t reserved_0x24; - register8_t reserved_0x25; - register8_t reserved_0x26; - register8_t reserved_0x27; - register8_t reserved_0x28; - register8_t reserved_0x29; - register8_t reserved_0x2A; - register8_t reserved_0x2B; - register8_t reserved_0x2C; - register8_t reserved_0x2D; - register8_t TEMPSENSE0; /* Temperature Sensor Calibration Byte 0 */ - register8_t TEMPSENSE1; /* Temperature Sensor Calibration Byte 1 */ - register8_t reserved_0x30; - register8_t reserved_0x31; - register8_t reserved_0x32; - register8_t reserved_0x33; - register8_t reserved_0x34; - register8_t reserved_0x35; - register8_t reserved_0x36; - register8_t reserved_0x37; - register8_t reserved_0x38; - register8_t reserved_0x39; - register8_t reserved_0x3A; - register8_t reserved_0x3B; - register8_t reserved_0x3C; - register8_t reserved_0x3D; - register8_t reserved_0x3E; - register8_t reserved_0x3F; -} NVM_PROD_SIGNATURES_t; - -/* -========================================================================== -IO Module Instances. Mapped to memory. -========================================================================== -*/ - -#define VPORT0 (*(VPORT_t *) 0x0010) /* Virtual Port */ -#define VPORT1 (*(VPORT_t *) 0x0014) /* Virtual Port */ -#define VPORT2 (*(VPORT_t *) 0x0018) /* Virtual Port */ -#define VPORT3 (*(VPORT_t *) 0x001C) /* Virtual Port */ -#define OCD (*(OCD_t *) 0x002E) /* On-Chip Debug System */ -#define CLK (*(CLK_t *) 0x0040) /* Clock System */ -#define SLEEP (*(SLEEP_t *) 0x0048) /* Sleep Controller */ -#define OSC (*(OSC_t *) 0x0050) /* Oscillator */ -#define DFLLRC32M (*(DFLL_t *) 0x0060) /* DFLL */ -#define DFLLRC2M (*(DFLL_t *) 0x0068) /* DFLL */ -#define PR (*(PR_t *) 0x0070) /* Power Reduction */ -#define RST (*(RST_t *) 0x0078) /* Reset */ -#define WDT (*(WDT_t *) 0x0080) /* Watch-Dog Timer */ -#define MCU (*(MCU_t *) 0x0090) /* MCU Control */ -#define PMIC (*(PMIC_t *) 0x00A0) /* Programmable Multi-level Interrupt Controller */ -#define PORTCFG (*(PORTCFG_t *) 0x00B0) /* I/O port Configuration */ -#define CRC (*(CRC_t *) 0x00D0) /* Cyclic Redundancy Checker */ -#define EVSYS (*(EVSYS_t *) 0x0180) /* Event System */ -#define NVM (*(NVM_t *) 0x01C0) /* Non-volatile Memory Controller */ -#define ADCA (*(ADC_t *) 0x0200) /* Analog-to-Digital Converter */ -#define ACA (*(AC_t *) 0x0380) /* Analog Comparator */ -#define RTC (*(RTC_t *) 0x0400) /* Real-Time Counter */ -#define TWIC (*(TWI_t *) 0x0480) /* Two-Wire Interface */ -#define TWIE (*(TWI_t *) 0x04A0) /* Two-Wire Interface */ -#define USB (*(USB_t *) 0x04C0) /* Universal Serial Bus */ -#define PORTA (*(PORT_t *) 0x0600) /* I/O Ports */ -#define PORTB (*(PORT_t *) 0x0620) /* I/O Ports */ -#define PORTC (*(PORT_t *) 0x0640) /* I/O Ports */ -#define PORTD (*(PORT_t *) 0x0660) /* I/O Ports */ -#define PORTE (*(PORT_t *) 0x0680) /* I/O Ports */ -#define PORTF (*(PORT_t *) 0x06A0) /* I/O Ports */ -#define PORTR (*(PORT_t *) 0x07E0) /* I/O Ports */ -#define TCC0 (*(TC0_t *) 0x0800) /* 16-bit Timer/Counter 0 */ -#define TCC2 (*(TC2_t *) 0x0800) /* 16-bit Timer/Counter type 2 */ -#define TCC1 (*(TC1_t *) 0x0840) /* 16-bit Timer/Counter 1 */ -#define AWEXC (*(AWEX_t *) 0x0880) /* Advanced Waveform Extension */ -#define HIRESC (*(HIRES_t *) 0x0890) /* High-Resolution Extension */ -#define USARTC0 (*(USART_t *) 0x08A0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ -#define SPIC (*(SPI_t *) 0x08C0) /* Serial Peripheral Interface */ -#define IRCOM (*(IRCOM_t *) 0x08F8) /* IR Communication Module */ -#define TCD0 (*(TC0_t *) 0x0900) /* 16-bit Timer/Counter 0 */ -#define TCD2 (*(TC2_t *) 0x0900) /* 16-bit Timer/Counter type 2 */ -#define USARTD0 (*(USART_t *) 0x09A0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ -#define SPID (*(SPI_t *) 0x09C0) /* Serial Peripheral Interface */ -#define TCE0 (*(TC0_t *) 0x0A00) /* 16-bit Timer/Counter 0 */ -#define TCE2 (*(TC2_t *) 0x0A00) /* 16-bit Timer/Counter type 2 */ -#define USARTE0 (*(USART_t *) 0x0AA0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ -#define TCF0 (*(TC0_t *) 0x0B00) /* 16-bit Timer/Counter 0 */ -#define TCF2 (*(TC2_t *) 0x0B00) /* 16-bit Timer/Counter type 2 */ - - -#endif /* !defined (__ASSEMBLER__) */ - - -/* ========== Flattened fully qualified IO register names ========== */ - -/* GPIO - General Purpose IO Registers */ -#define GPIO_GPIOR0 _SFR_MEM8(0x0000) -#define GPIO_GPIOR1 _SFR_MEM8(0x0001) -#define GPIO_GPIOR2 _SFR_MEM8(0x0002) -#define GPIO_GPIOR3 _SFR_MEM8(0x0003) - -/* Deprecated */ -#define GPIO_GPIO0 _SFR_MEM8(0x0000) -#define GPIO_GPIO1 _SFR_MEM8(0x0001) -#define GPIO_GPIO2 _SFR_MEM8(0x0002) -#define GPIO_GPIO3 _SFR_MEM8(0x0003) - -/* NVM_FUSES - Fuses */ -#define FUSE_FUSEBYTE1 _SFR_MEM8(0x0001) -#define FUSE_FUSEBYTE2 _SFR_MEM8(0x0002) -#define FUSE_FUSEBYTE4 _SFR_MEM8(0x0004) -#define FUSE_FUSEBYTE5 _SFR_MEM8(0x0005) - -/* NVM_LOCKBITS - Lock Bits */ -#define LOCKBIT_LOCKBITS _SFR_MEM8(0x0000) - -/* NVM_PROD_SIGNATURES - Production Signatures */ -#define PRODSIGNATURES_RCOSC2M _SFR_MEM8(0x0000) -#define PRODSIGNATURES_RCOSC2MA _SFR_MEM8(0x0001) -#define PRODSIGNATURES_RCOSC32K _SFR_MEM8(0x0002) -#define PRODSIGNATURES_RCOSC32M _SFR_MEM8(0x0003) -#define PRODSIGNATURES_RCOSC32MA _SFR_MEM8(0x0004) -#define PRODSIGNATURES_LOTNUM0 _SFR_MEM8(0x0008) -#define PRODSIGNATURES_LOTNUM1 _SFR_MEM8(0x0009) -#define PRODSIGNATURES_LOTNUM2 _SFR_MEM8(0x000A) -#define PRODSIGNATURES_LOTNUM3 _SFR_MEM8(0x000B) -#define PRODSIGNATURES_LOTNUM4 _SFR_MEM8(0x000C) -#define PRODSIGNATURES_LOTNUM5 _SFR_MEM8(0x000D) -#define PRODSIGNATURES_WAFNUM _SFR_MEM8(0x0010) -#define PRODSIGNATURES_COORDX0 _SFR_MEM8(0x0012) -#define PRODSIGNATURES_COORDX1 _SFR_MEM8(0x0013) -#define PRODSIGNATURES_COORDY0 _SFR_MEM8(0x0014) -#define PRODSIGNATURES_COORDY1 _SFR_MEM8(0x0015) -#define PRODSIGNATURES_USBCAL0 _SFR_MEM8(0x001A) -#define PRODSIGNATURES_USBCAL1 _SFR_MEM8(0x001B) -#define PRODSIGNATURES_USBRCOSC _SFR_MEM8(0x001C) -#define PRODSIGNATURES_USBRCOSCA _SFR_MEM8(0x001D) -#define PRODSIGNATURES_ADCACAL0 _SFR_MEM8(0x0020) -#define PRODSIGNATURES_ADCACAL1 _SFR_MEM8(0x0021) -#define PRODSIGNATURES_TEMPSENSE0 _SFR_MEM8(0x002E) -#define PRODSIGNATURES_TEMPSENSE1 _SFR_MEM8(0x002F) - -/* VPORT - Virtual Port */ -#define VPORT0_DIR _SFR_MEM8(0x0010) -#define VPORT0_OUT _SFR_MEM8(0x0011) -#define VPORT0_IN _SFR_MEM8(0x0012) -#define VPORT0_INTFLAGS _SFR_MEM8(0x0013) - -/* VPORT - Virtual Port */ -#define VPORT1_DIR _SFR_MEM8(0x0014) -#define VPORT1_OUT _SFR_MEM8(0x0015) -#define VPORT1_IN _SFR_MEM8(0x0016) -#define VPORT1_INTFLAGS _SFR_MEM8(0x0017) - -/* VPORT - Virtual Port */ -#define VPORT2_DIR _SFR_MEM8(0x0018) -#define VPORT2_OUT _SFR_MEM8(0x0019) -#define VPORT2_IN _SFR_MEM8(0x001A) -#define VPORT2_INTFLAGS _SFR_MEM8(0x001B) - -/* VPORT - Virtual Port */ -#define VPORT3_DIR _SFR_MEM8(0x001C) -#define VPORT3_OUT _SFR_MEM8(0x001D) -#define VPORT3_IN _SFR_MEM8(0x001E) -#define VPORT3_INTFLAGS _SFR_MEM8(0x001F) - -/* OCD - On-Chip Debug System */ -#define OCD_OCDR0 _SFR_MEM8(0x002E) -#define OCD_OCDR1 _SFR_MEM8(0x002F) - -/* CPU - CPU registers */ -#define CPU_CCP _SFR_MEM8(0x0034) -#define CPU_RAMPD _SFR_MEM8(0x0038) -#define CPU_RAMPX _SFR_MEM8(0x0039) -#define CPU_RAMPY _SFR_MEM8(0x003A) -#define CPU_RAMPZ _SFR_MEM8(0x003B) -#define CPU_EIND _SFR_MEM8(0x003C) -#define CPU_SPL _SFR_MEM8(0x003D) -#define CPU_SPH _SFR_MEM8(0x003E) -#define CPU_SREG _SFR_MEM8(0x003F) - -/* CLK - Clock System */ -#define CLK_CTRL _SFR_MEM8(0x0040) -#define CLK_PSCTRL _SFR_MEM8(0x0041) -#define CLK_LOCK _SFR_MEM8(0x0042) -#define CLK_RTCCTRL _SFR_MEM8(0x0043) -#define CLK_USBCTRL _SFR_MEM8(0x0044) - -/* SLEEP - Sleep Controller */ -#define SLEEP_CTRL _SFR_MEM8(0x0048) - -/* OSC - Oscillator */ -#define OSC_CTRL _SFR_MEM8(0x0050) -#define OSC_STATUS _SFR_MEM8(0x0051) -#define OSC_XOSCCTRL _SFR_MEM8(0x0052) -#define OSC_XOSCFAIL _SFR_MEM8(0x0053) -#define OSC_RC32KCAL _SFR_MEM8(0x0054) -#define OSC_PLLCTRL _SFR_MEM8(0x0055) -#define OSC_DFLLCTRL _SFR_MEM8(0x0056) - -/* DFLL - DFLL */ -#define DFLLRC32M_CTRL _SFR_MEM8(0x0060) -#define DFLLRC32M_CALA _SFR_MEM8(0x0062) -#define DFLLRC32M_CALB _SFR_MEM8(0x0063) -#define DFLLRC32M_COMP0 _SFR_MEM8(0x0064) -#define DFLLRC32M_COMP1 _SFR_MEM8(0x0065) -#define DFLLRC32M_COMP2 _SFR_MEM8(0x0066) - -/* DFLL - DFLL */ -#define DFLLRC2M_CTRL _SFR_MEM8(0x0068) -#define DFLLRC2M_CALA _SFR_MEM8(0x006A) -#define DFLLRC2M_CALB _SFR_MEM8(0x006B) -#define DFLLRC2M_COMP0 _SFR_MEM8(0x006C) -#define DFLLRC2M_COMP1 _SFR_MEM8(0x006D) -#define DFLLRC2M_COMP2 _SFR_MEM8(0x006E) - -/* PR - Power Reduction */ -#define PR_PRGEN _SFR_MEM8(0x0070) -#define PR_PRPA _SFR_MEM8(0x0071) -#define PR_PRPC _SFR_MEM8(0x0073) -#define PR_PRPD _SFR_MEM8(0x0074) -#define PR_PRPE _SFR_MEM8(0x0075) -#define PR_PRPF _SFR_MEM8(0x0076) - -/* RST - Reset */ -#define RST_STATUS _SFR_MEM8(0x0078) -#define RST_CTRL _SFR_MEM8(0x0079) - -/* WDT - Watch-Dog Timer */ -#define WDT_CTRL _SFR_MEM8(0x0080) -#define WDT_WINCTRL _SFR_MEM8(0x0081) -#define WDT_STATUS _SFR_MEM8(0x0082) - -/* MCU - MCU Control */ -#define MCU_DEVID0 _SFR_MEM8(0x0090) -#define MCU_DEVID1 _SFR_MEM8(0x0091) -#define MCU_DEVID2 _SFR_MEM8(0x0092) -#define MCU_REVID _SFR_MEM8(0x0093) -#define MCU_ANAINIT _SFR_MEM8(0x0097) -#define MCU_EVSYSLOCK _SFR_MEM8(0x0098) -#define MCU_AWEXLOCK _SFR_MEM8(0x0099) - -/* PMIC - Programmable Multi-level Interrupt Controller */ -#define PMIC_STATUS _SFR_MEM8(0x00A0) -#define PMIC_INTPRI _SFR_MEM8(0x00A1) -#define PMIC_CTRL _SFR_MEM8(0x00A2) - -/* PORTCFG - I/O port Configuration */ -#define PORTCFG_MPCMASK _SFR_MEM8(0x00B0) -#define PORTCFG_VPCTRLA _SFR_MEM8(0x00B2) -#define PORTCFG_VPCTRLB _SFR_MEM8(0x00B3) -#define PORTCFG_CLKEVOUT _SFR_MEM8(0x00B4) -#define PORTCFG_EVOUTSEL _SFR_MEM8(0x00B6) - -/* CRC - Cyclic Redundancy Checker */ -#define CRC_CTRL _SFR_MEM8(0x00D0) -#define CRC_STATUS _SFR_MEM8(0x00D1) -#define CRC_DATAIN _SFR_MEM8(0x00D3) -#define CRC_CHECKSUM0 _SFR_MEM8(0x00D4) -#define CRC_CHECKSUM1 _SFR_MEM8(0x00D5) -#define CRC_CHECKSUM2 _SFR_MEM8(0x00D6) -#define CRC_CHECKSUM3 _SFR_MEM8(0x00D7) - -/* EVSYS - Event System */ -#define EVSYS_CH0MUX _SFR_MEM8(0x0180) -#define EVSYS_CH1MUX _SFR_MEM8(0x0181) -#define EVSYS_CH2MUX _SFR_MEM8(0x0182) -#define EVSYS_CH3MUX _SFR_MEM8(0x0183) -#define EVSYS_CH0CTRL _SFR_MEM8(0x0188) -#define EVSYS_CH1CTRL _SFR_MEM8(0x0189) -#define EVSYS_CH2CTRL _SFR_MEM8(0x018A) -#define EVSYS_CH3CTRL _SFR_MEM8(0x018B) -#define EVSYS_STROBE _SFR_MEM8(0x0190) -#define EVSYS_DATA _SFR_MEM8(0x0191) - -/* NVM - Non-volatile Memory Controller */ -#define NVM_ADDR0 _SFR_MEM8(0x01C0) -#define NVM_ADDR1 _SFR_MEM8(0x01C1) -#define NVM_ADDR2 _SFR_MEM8(0x01C2) -#define NVM_DATA0 _SFR_MEM8(0x01C4) -#define NVM_DATA1 _SFR_MEM8(0x01C5) -#define NVM_DATA2 _SFR_MEM8(0x01C6) -#define NVM_CMD _SFR_MEM8(0x01CA) -#define NVM_CTRLA _SFR_MEM8(0x01CB) -#define NVM_CTRLB _SFR_MEM8(0x01CC) -#define NVM_INTCTRL _SFR_MEM8(0x01CD) -#define NVM_STATUS _SFR_MEM8(0x01CF) -#define NVM_LOCKBITS _SFR_MEM8(0x01D0) - -/* ADC - Analog-to-Digital Converter */ -#define ADCA_CTRLA _SFR_MEM8(0x0200) -#define ADCA_CTRLB _SFR_MEM8(0x0201) -#define ADCA_REFCTRL _SFR_MEM8(0x0202) -#define ADCA_EVCTRL _SFR_MEM8(0x0203) -#define ADCA_PRESCALER _SFR_MEM8(0x0204) -#define ADCA_INTFLAGS _SFR_MEM8(0x0206) -#define ADCA_TEMP _SFR_MEM8(0x0207) -#define ADCA_CAL _SFR_MEM16(0x020C) -#define ADCA_CH0RES _SFR_MEM16(0x0210) -#define ADCA_CMP _SFR_MEM16(0x0218) -#define ADCA_CH0_CTRL _SFR_MEM8(0x0220) -#define ADCA_CH0_MUXCTRL _SFR_MEM8(0x0221) -#define ADCA_CH0_INTCTRL _SFR_MEM8(0x0222) -#define ADCA_CH0_INTFLAGS _SFR_MEM8(0x0223) -#define ADCA_CH0_RES _SFR_MEM16(0x0224) -#define ADCA_CH0_SCAN _SFR_MEM8(0x0226) - -/* AC - Analog Comparator */ -#define ACA_AC0CTRL _SFR_MEM8(0x0380) -#define ACA_AC1CTRL _SFR_MEM8(0x0381) -#define ACA_AC0MUXCTRL _SFR_MEM8(0x0382) -#define ACA_AC1MUXCTRL _SFR_MEM8(0x0383) -#define ACA_CTRLA _SFR_MEM8(0x0384) -#define ACA_CTRLB _SFR_MEM8(0x0385) -#define ACA_WINCTRL _SFR_MEM8(0x0386) -#define ACA_STATUS _SFR_MEM8(0x0387) - -/* RTC - Real-Time Counter */ -#define RTC_CTRL _SFR_MEM8(0x0400) -#define RTC_STATUS _SFR_MEM8(0x0401) -#define RTC_INTCTRL _SFR_MEM8(0x0402) -#define RTC_INTFLAGS _SFR_MEM8(0x0403) -#define RTC_TEMP _SFR_MEM8(0x0404) -#define RTC_CNT _SFR_MEM16(0x0408) -#define RTC_PER _SFR_MEM16(0x040A) -#define RTC_COMP _SFR_MEM16(0x040C) - -/* TWI - Two-Wire Interface */ -#define TWIC_CTRL _SFR_MEM8(0x0480) -#define TWIC_MASTER_CTRLA _SFR_MEM8(0x0481) -#define TWIC_MASTER_CTRLB _SFR_MEM8(0x0482) -#define TWIC_MASTER_CTRLC _SFR_MEM8(0x0483) -#define TWIC_MASTER_STATUS _SFR_MEM8(0x0484) -#define TWIC_MASTER_BAUD _SFR_MEM8(0x0485) -#define TWIC_MASTER_ADDR _SFR_MEM8(0x0486) -#define TWIC_MASTER_DATA _SFR_MEM8(0x0487) -#define TWIC_SLAVE_CTRLA _SFR_MEM8(0x0488) -#define TWIC_SLAVE_CTRLB _SFR_MEM8(0x0489) -#define TWIC_SLAVE_STATUS _SFR_MEM8(0x048A) -#define TWIC_SLAVE_ADDR _SFR_MEM8(0x048B) -#define TWIC_SLAVE_DATA _SFR_MEM8(0x048C) -#define TWIC_SLAVE_ADDRMASK _SFR_MEM8(0x048D) - -/* TWI - Two-Wire Interface */ -#define TWIE_CTRL _SFR_MEM8(0x04A0) -#define TWIE_MASTER_CTRLA _SFR_MEM8(0x04A1) -#define TWIE_MASTER_CTRLB _SFR_MEM8(0x04A2) -#define TWIE_MASTER_CTRLC _SFR_MEM8(0x04A3) -#define TWIE_MASTER_STATUS _SFR_MEM8(0x04A4) -#define TWIE_MASTER_BAUD _SFR_MEM8(0x04A5) -#define TWIE_MASTER_ADDR _SFR_MEM8(0x04A6) -#define TWIE_MASTER_DATA _SFR_MEM8(0x04A7) -#define TWIE_SLAVE_CTRLA _SFR_MEM8(0x04A8) -#define TWIE_SLAVE_CTRLB _SFR_MEM8(0x04A9) -#define TWIE_SLAVE_STATUS _SFR_MEM8(0x04AA) -#define TWIE_SLAVE_ADDR _SFR_MEM8(0x04AB) -#define TWIE_SLAVE_DATA _SFR_MEM8(0x04AC) -#define TWIE_SLAVE_ADDRMASK _SFR_MEM8(0x04AD) - -/* USB - Universal Serial Bus */ -#define USB_CTRLA _SFR_MEM8(0x04C0) -#define USB_CTRLB _SFR_MEM8(0x04C1) -#define USB_STATUS _SFR_MEM8(0x04C2) -#define USB_ADDR _SFR_MEM8(0x04C3) -#define USB_FIFOWP _SFR_MEM8(0x04C4) -#define USB_FIFORP _SFR_MEM8(0x04C5) -#define USB_EPPTR _SFR_MEM16(0x04C6) -#define USB_INTCTRLA _SFR_MEM8(0x04C8) -#define USB_INTCTRLB _SFR_MEM8(0x04C9) -#define USB_INTFLAGSACLR _SFR_MEM8(0x04CA) -#define USB_INTFLAGSASET _SFR_MEM8(0x04CB) -#define USB_INTFLAGSBCLR _SFR_MEM8(0x04CC) -#define USB_INTFLAGSBSET _SFR_MEM8(0x04CD) -#define USB_CAL0 _SFR_MEM8(0x04FA) -#define USB_CAL1 _SFR_MEM8(0x04FB) - -/* PORT - I/O Ports */ -#define PORTA_DIR _SFR_MEM8(0x0600) -#define PORTA_DIRSET _SFR_MEM8(0x0601) -#define PORTA_DIRCLR _SFR_MEM8(0x0602) -#define PORTA_DIRTGL _SFR_MEM8(0x0603) -#define PORTA_OUT _SFR_MEM8(0x0604) -#define PORTA_OUTSET _SFR_MEM8(0x0605) -#define PORTA_OUTCLR _SFR_MEM8(0x0606) -#define PORTA_OUTTGL _SFR_MEM8(0x0607) -#define PORTA_IN _SFR_MEM8(0x0608) -#define PORTA_INTCTRL _SFR_MEM8(0x0609) -#define PORTA_INT0MASK _SFR_MEM8(0x060A) -#define PORTA_INT1MASK _SFR_MEM8(0x060B) -#define PORTA_INTFLAGS _SFR_MEM8(0x060C) -#define PORTA_REMAP _SFR_MEM8(0x060E) -#define PORTA_PIN0CTRL _SFR_MEM8(0x0610) -#define PORTA_PIN1CTRL _SFR_MEM8(0x0611) -#define PORTA_PIN2CTRL _SFR_MEM8(0x0612) -#define PORTA_PIN3CTRL _SFR_MEM8(0x0613) -#define PORTA_PIN4CTRL _SFR_MEM8(0x0614) -#define PORTA_PIN5CTRL _SFR_MEM8(0x0615) -#define PORTA_PIN6CTRL _SFR_MEM8(0x0616) -#define PORTA_PIN7CTRL _SFR_MEM8(0x0617) - -/* PORT - I/O Ports */ -#define PORTB_DIR _SFR_MEM8(0x0620) -#define PORTB_DIRSET _SFR_MEM8(0x0621) -#define PORTB_DIRCLR _SFR_MEM8(0x0622) -#define PORTB_DIRTGL _SFR_MEM8(0x0623) -#define PORTB_OUT _SFR_MEM8(0x0624) -#define PORTB_OUTSET _SFR_MEM8(0x0625) -#define PORTB_OUTCLR _SFR_MEM8(0x0626) -#define PORTB_OUTTGL _SFR_MEM8(0x0627) -#define PORTB_IN _SFR_MEM8(0x0628) -#define PORTB_INTCTRL _SFR_MEM8(0x0629) -#define PORTB_INT0MASK _SFR_MEM8(0x062A) -#define PORTB_INT1MASK _SFR_MEM8(0x062B) -#define PORTB_INTFLAGS _SFR_MEM8(0x062C) -#define PORTB_REMAP _SFR_MEM8(0x062E) -#define PORTB_PIN0CTRL _SFR_MEM8(0x0630) -#define PORTB_PIN1CTRL _SFR_MEM8(0x0631) -#define PORTB_PIN2CTRL _SFR_MEM8(0x0632) -#define PORTB_PIN3CTRL _SFR_MEM8(0x0633) -#define PORTB_PIN4CTRL _SFR_MEM8(0x0634) -#define PORTB_PIN5CTRL _SFR_MEM8(0x0635) -#define PORTB_PIN6CTRL _SFR_MEM8(0x0636) -#define PORTB_PIN7CTRL _SFR_MEM8(0x0637) - -/* PORT - I/O Ports */ -#define PORTC_DIR _SFR_MEM8(0x0640) -#define PORTC_DIRSET _SFR_MEM8(0x0641) -#define PORTC_DIRCLR _SFR_MEM8(0x0642) -#define PORTC_DIRTGL _SFR_MEM8(0x0643) -#define PORTC_OUT _SFR_MEM8(0x0644) -#define PORTC_OUTSET _SFR_MEM8(0x0645) -#define PORTC_OUTCLR _SFR_MEM8(0x0646) -#define PORTC_OUTTGL _SFR_MEM8(0x0647) -#define PORTC_IN _SFR_MEM8(0x0648) -#define PORTC_INTCTRL _SFR_MEM8(0x0649) -#define PORTC_INT0MASK _SFR_MEM8(0x064A) -#define PORTC_INT1MASK _SFR_MEM8(0x064B) -#define PORTC_INTFLAGS _SFR_MEM8(0x064C) -#define PORTC_REMAP _SFR_MEM8(0x064E) -#define PORTC_PIN0CTRL _SFR_MEM8(0x0650) -#define PORTC_PIN1CTRL _SFR_MEM8(0x0651) -#define PORTC_PIN2CTRL _SFR_MEM8(0x0652) -#define PORTC_PIN3CTRL _SFR_MEM8(0x0653) -#define PORTC_PIN4CTRL _SFR_MEM8(0x0654) -#define PORTC_PIN5CTRL _SFR_MEM8(0x0655) -#define PORTC_PIN6CTRL _SFR_MEM8(0x0656) -#define PORTC_PIN7CTRL _SFR_MEM8(0x0657) - -/* PORT - I/O Ports */ -#define PORTD_DIR _SFR_MEM8(0x0660) -#define PORTD_DIRSET _SFR_MEM8(0x0661) -#define PORTD_DIRCLR _SFR_MEM8(0x0662) -#define PORTD_DIRTGL _SFR_MEM8(0x0663) -#define PORTD_OUT _SFR_MEM8(0x0664) -#define PORTD_OUTSET _SFR_MEM8(0x0665) -#define PORTD_OUTCLR _SFR_MEM8(0x0666) -#define PORTD_OUTTGL _SFR_MEM8(0x0667) -#define PORTD_IN _SFR_MEM8(0x0668) -#define PORTD_INTCTRL _SFR_MEM8(0x0669) -#define PORTD_INT0MASK _SFR_MEM8(0x066A) -#define PORTD_INT1MASK _SFR_MEM8(0x066B) -#define PORTD_INTFLAGS _SFR_MEM8(0x066C) -#define PORTD_REMAP _SFR_MEM8(0x066E) -#define PORTD_PIN0CTRL _SFR_MEM8(0x0670) -#define PORTD_PIN1CTRL _SFR_MEM8(0x0671) -#define PORTD_PIN2CTRL _SFR_MEM8(0x0672) -#define PORTD_PIN3CTRL _SFR_MEM8(0x0673) -#define PORTD_PIN4CTRL _SFR_MEM8(0x0674) -#define PORTD_PIN5CTRL _SFR_MEM8(0x0675) -#define PORTD_PIN6CTRL _SFR_MEM8(0x0676) -#define PORTD_PIN7CTRL _SFR_MEM8(0x0677) - -/* PORT - I/O Ports */ -#define PORTE_DIR _SFR_MEM8(0x0680) -#define PORTE_DIRSET _SFR_MEM8(0x0681) -#define PORTE_DIRCLR _SFR_MEM8(0x0682) -#define PORTE_DIRTGL _SFR_MEM8(0x0683) -#define PORTE_OUT _SFR_MEM8(0x0684) -#define PORTE_OUTSET _SFR_MEM8(0x0685) -#define PORTE_OUTCLR _SFR_MEM8(0x0686) -#define PORTE_OUTTGL _SFR_MEM8(0x0687) -#define PORTE_IN _SFR_MEM8(0x0688) -#define PORTE_INTCTRL _SFR_MEM8(0x0689) -#define PORTE_INT0MASK _SFR_MEM8(0x068A) -#define PORTE_INT1MASK _SFR_MEM8(0x068B) -#define PORTE_INTFLAGS _SFR_MEM8(0x068C) -#define PORTE_REMAP _SFR_MEM8(0x068E) -#define PORTE_PIN0CTRL _SFR_MEM8(0x0690) -#define PORTE_PIN1CTRL _SFR_MEM8(0x0691) -#define PORTE_PIN2CTRL _SFR_MEM8(0x0692) -#define PORTE_PIN3CTRL _SFR_MEM8(0x0693) -#define PORTE_PIN4CTRL _SFR_MEM8(0x0694) -#define PORTE_PIN5CTRL _SFR_MEM8(0x0695) -#define PORTE_PIN6CTRL _SFR_MEM8(0x0696) -#define PORTE_PIN7CTRL _SFR_MEM8(0x0697) - -/* PORT - I/O Ports */ -#define PORTF_DIR _SFR_MEM8(0x06A0) -#define PORTF_DIRSET _SFR_MEM8(0x06A1) -#define PORTF_DIRCLR _SFR_MEM8(0x06A2) -#define PORTF_DIRTGL _SFR_MEM8(0x06A3) -#define PORTF_OUT _SFR_MEM8(0x06A4) -#define PORTF_OUTSET _SFR_MEM8(0x06A5) -#define PORTF_OUTCLR _SFR_MEM8(0x06A6) -#define PORTF_OUTTGL _SFR_MEM8(0x06A7) -#define PORTF_IN _SFR_MEM8(0x06A8) -#define PORTF_INTCTRL _SFR_MEM8(0x06A9) -#define PORTF_INT0MASK _SFR_MEM8(0x06AA) -#define PORTF_INT1MASK _SFR_MEM8(0x06AB) -#define PORTF_INTFLAGS _SFR_MEM8(0x06AC) -#define PORTF_REMAP _SFR_MEM8(0x06AE) -#define PORTF_PIN0CTRL _SFR_MEM8(0x06B0) -#define PORTF_PIN1CTRL _SFR_MEM8(0x06B1) -#define PORTF_PIN2CTRL _SFR_MEM8(0x06B2) -#define PORTF_PIN3CTRL _SFR_MEM8(0x06B3) -#define PORTF_PIN4CTRL _SFR_MEM8(0x06B4) -#define PORTF_PIN5CTRL _SFR_MEM8(0x06B5) -#define PORTF_PIN6CTRL _SFR_MEM8(0x06B6) -#define PORTF_PIN7CTRL _SFR_MEM8(0x06B7) - -/* PORT - I/O Ports */ -#define PORTR_DIR _SFR_MEM8(0x07E0) -#define PORTR_DIRSET _SFR_MEM8(0x07E1) -#define PORTR_DIRCLR _SFR_MEM8(0x07E2) -#define PORTR_DIRTGL _SFR_MEM8(0x07E3) -#define PORTR_OUT _SFR_MEM8(0x07E4) -#define PORTR_OUTSET _SFR_MEM8(0x07E5) -#define PORTR_OUTCLR _SFR_MEM8(0x07E6) -#define PORTR_OUTTGL _SFR_MEM8(0x07E7) -#define PORTR_IN _SFR_MEM8(0x07E8) -#define PORTR_INTCTRL _SFR_MEM8(0x07E9) -#define PORTR_INT0MASK _SFR_MEM8(0x07EA) -#define PORTR_INT1MASK _SFR_MEM8(0x07EB) -#define PORTR_INTFLAGS _SFR_MEM8(0x07EC) -#define PORTR_REMAP _SFR_MEM8(0x07EE) -#define PORTR_PIN0CTRL _SFR_MEM8(0x07F0) -#define PORTR_PIN1CTRL _SFR_MEM8(0x07F1) -#define PORTR_PIN2CTRL _SFR_MEM8(0x07F2) -#define PORTR_PIN3CTRL _SFR_MEM8(0x07F3) -#define PORTR_PIN4CTRL _SFR_MEM8(0x07F4) -#define PORTR_PIN5CTRL _SFR_MEM8(0x07F5) -#define PORTR_PIN6CTRL _SFR_MEM8(0x07F6) -#define PORTR_PIN7CTRL _SFR_MEM8(0x07F7) - -/* TC0 - 16-bit Timer/Counter 0 */ -#define TCC0_CTRLA _SFR_MEM8(0x0800) -#define TCC0_CTRLB _SFR_MEM8(0x0801) -#define TCC0_CTRLC _SFR_MEM8(0x0802) -#define TCC0_CTRLD _SFR_MEM8(0x0803) -#define TCC0_CTRLE _SFR_MEM8(0x0804) -#define TCC0_INTCTRLA _SFR_MEM8(0x0806) -#define TCC0_INTCTRLB _SFR_MEM8(0x0807) -#define TCC0_CTRLFCLR _SFR_MEM8(0x0808) -#define TCC0_CTRLFSET _SFR_MEM8(0x0809) -#define TCC0_CTRLGCLR _SFR_MEM8(0x080A) -#define TCC0_CTRLGSET _SFR_MEM8(0x080B) -#define TCC0_INTFLAGS _SFR_MEM8(0x080C) -#define TCC0_TEMP _SFR_MEM8(0x080F) -#define TCC0_CNT _SFR_MEM16(0x0820) -#define TCC0_PER _SFR_MEM16(0x0826) -#define TCC0_CCA _SFR_MEM16(0x0828) -#define TCC0_CCB _SFR_MEM16(0x082A) -#define TCC0_CCC _SFR_MEM16(0x082C) -#define TCC0_CCD _SFR_MEM16(0x082E) -#define TCC0_PERBUF _SFR_MEM16(0x0836) -#define TCC0_CCABUF _SFR_MEM16(0x0838) -#define TCC0_CCBBUF _SFR_MEM16(0x083A) -#define TCC0_CCCBUF _SFR_MEM16(0x083C) -#define TCC0_CCDBUF _SFR_MEM16(0x083E) - -/* TC2 - 16-bit Timer/Counter type 2 */ -#define TCC2_CTRLA _SFR_MEM8(0x0800) -#define TCC2_CTRLB _SFR_MEM8(0x0801) -#define TCC2_CTRLC _SFR_MEM8(0x0802) -#define TCC2_CTRLE _SFR_MEM8(0x0804) -#define TCC2_INTCTRLA _SFR_MEM8(0x0806) -#define TCC2_INTCTRLB _SFR_MEM8(0x0807) -#define TCC2_CTRLF _SFR_MEM8(0x0809) -#define TCC2_INTFLAGS _SFR_MEM8(0x080C) -#define TCC2_LCNT _SFR_MEM8(0x0820) -#define TCC2_HCNT _SFR_MEM8(0x0821) -#define TCC2_LPER _SFR_MEM8(0x0826) -#define TCC2_HPER _SFR_MEM8(0x0827) -#define TCC2_LCMPA _SFR_MEM8(0x0828) -#define TCC2_HCMPA _SFR_MEM8(0x0829) -#define TCC2_LCMPB _SFR_MEM8(0x082A) -#define TCC2_HCMPB _SFR_MEM8(0x082B) -#define TCC2_LCMPC _SFR_MEM8(0x082C) -#define TCC2_HCMPC _SFR_MEM8(0x082D) -#define TCC2_LCMPD _SFR_MEM8(0x082E) -#define TCC2_HCMPD _SFR_MEM8(0x082F) - -/* TC1 - 16-bit Timer/Counter 1 */ -#define TCC1_CTRLA _SFR_MEM8(0x0840) -#define TCC1_CTRLB _SFR_MEM8(0x0841) -#define TCC1_CTRLC _SFR_MEM8(0x0842) -#define TCC1_CTRLD _SFR_MEM8(0x0843) -#define TCC1_CTRLE _SFR_MEM8(0x0844) -#define TCC1_INTCTRLA _SFR_MEM8(0x0846) -#define TCC1_INTCTRLB _SFR_MEM8(0x0847) -#define TCC1_CTRLFCLR _SFR_MEM8(0x0848) -#define TCC1_CTRLFSET _SFR_MEM8(0x0849) -#define TCC1_CTRLGCLR _SFR_MEM8(0x084A) -#define TCC1_CTRLGSET _SFR_MEM8(0x084B) -#define TCC1_INTFLAGS _SFR_MEM8(0x084C) -#define TCC1_TEMP _SFR_MEM8(0x084F) -#define TCC1_CNT _SFR_MEM16(0x0860) -#define TCC1_PER _SFR_MEM16(0x0866) -#define TCC1_CCA _SFR_MEM16(0x0868) -#define TCC1_CCB _SFR_MEM16(0x086A) -#define TCC1_PERBUF _SFR_MEM16(0x0876) -#define TCC1_CCABUF _SFR_MEM16(0x0878) -#define TCC1_CCBBUF _SFR_MEM16(0x087A) - -/* AWEX - Advanced Waveform Extension */ -#define AWEXC_CTRL _SFR_MEM8(0x0880) -#define AWEXC_FDEMASK _SFR_MEM8(0x0882) -#define AWEXC_FDCTRL _SFR_MEM8(0x0883) -#define AWEXC_STATUS _SFR_MEM8(0x0884) -#define AWEXC_STATUSSET _SFR_MEM8(0x0885) -#define AWEXC_DTBOTH _SFR_MEM8(0x0886) -#define AWEXC_DTBOTHBUF _SFR_MEM8(0x0887) -#define AWEXC_DTLS _SFR_MEM8(0x0888) -#define AWEXC_DTHS _SFR_MEM8(0x0889) -#define AWEXC_DTLSBUF _SFR_MEM8(0x088A) -#define AWEXC_DTHSBUF _SFR_MEM8(0x088B) -#define AWEXC_OUTOVEN _SFR_MEM8(0x088C) - -/* HIRES - High-Resolution Extension */ -#define HIRESC_CTRLA _SFR_MEM8(0x0890) - -/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ -#define USARTC0_DATA _SFR_MEM8(0x08A0) -#define USARTC0_STATUS _SFR_MEM8(0x08A1) -#define USARTC0_CTRLA _SFR_MEM8(0x08A3) -#define USARTC0_CTRLB _SFR_MEM8(0x08A4) -#define USARTC0_CTRLC _SFR_MEM8(0x08A5) -#define USARTC0_BAUDCTRLA _SFR_MEM8(0x08A6) -#define USARTC0_BAUDCTRLB _SFR_MEM8(0x08A7) - -/* SPI - Serial Peripheral Interface */ -#define SPIC_CTRL _SFR_MEM8(0x08C0) -#define SPIC_INTCTRL _SFR_MEM8(0x08C1) -#define SPIC_STATUS _SFR_MEM8(0x08C2) -#define SPIC_DATA _SFR_MEM8(0x08C3) - -/* IRCOM - IR Communication Module */ -#define IRCOM_CTRL _SFR_MEM8(0x08F8) -#define IRCOM_TXPLCTRL _SFR_MEM8(0x08F9) -#define IRCOM_RXPLCTRL _SFR_MEM8(0x08FA) - -/* TC0 - 16-bit Timer/Counter 0 */ -#define TCD0_CTRLA _SFR_MEM8(0x0900) -#define TCD0_CTRLB _SFR_MEM8(0x0901) -#define TCD0_CTRLC _SFR_MEM8(0x0902) -#define TCD0_CTRLD _SFR_MEM8(0x0903) -#define TCD0_CTRLE _SFR_MEM8(0x0904) -#define TCD0_INTCTRLA _SFR_MEM8(0x0906) -#define TCD0_INTCTRLB _SFR_MEM8(0x0907) -#define TCD0_CTRLFCLR _SFR_MEM8(0x0908) -#define TCD0_CTRLFSET _SFR_MEM8(0x0909) -#define TCD0_CTRLGCLR _SFR_MEM8(0x090A) -#define TCD0_CTRLGSET _SFR_MEM8(0x090B) -#define TCD0_INTFLAGS _SFR_MEM8(0x090C) -#define TCD0_TEMP _SFR_MEM8(0x090F) -#define TCD0_CNT _SFR_MEM16(0x0920) -#define TCD0_PER _SFR_MEM16(0x0926) -#define TCD0_CCA _SFR_MEM16(0x0928) -#define TCD0_CCB _SFR_MEM16(0x092A) -#define TCD0_CCC _SFR_MEM16(0x092C) -#define TCD0_CCD _SFR_MEM16(0x092E) -#define TCD0_PERBUF _SFR_MEM16(0x0936) -#define TCD0_CCABUF _SFR_MEM16(0x0938) -#define TCD0_CCBBUF _SFR_MEM16(0x093A) -#define TCD0_CCCBUF _SFR_MEM16(0x093C) -#define TCD0_CCDBUF _SFR_MEM16(0x093E) - -/* TC2 - 16-bit Timer/Counter type 2 */ -#define TCD2_CTRLA _SFR_MEM8(0x0900) -#define TCD2_CTRLB _SFR_MEM8(0x0901) -#define TCD2_CTRLC _SFR_MEM8(0x0902) -#define TCD2_CTRLE _SFR_MEM8(0x0904) -#define TCD2_INTCTRLA _SFR_MEM8(0x0906) -#define TCD2_INTCTRLB _SFR_MEM8(0x0907) -#define TCD2_CTRLF _SFR_MEM8(0x0909) -#define TCD2_INTFLAGS _SFR_MEM8(0x090C) -#define TCD2_LCNT _SFR_MEM8(0x0920) -#define TCD2_HCNT _SFR_MEM8(0x0921) -#define TCD2_LPER _SFR_MEM8(0x0926) -#define TCD2_HPER _SFR_MEM8(0x0927) -#define TCD2_LCMPA _SFR_MEM8(0x0928) -#define TCD2_HCMPA _SFR_MEM8(0x0929) -#define TCD2_LCMPB _SFR_MEM8(0x092A) -#define TCD2_HCMPB _SFR_MEM8(0x092B) -#define TCD2_LCMPC _SFR_MEM8(0x092C) -#define TCD2_HCMPC _SFR_MEM8(0x092D) -#define TCD2_LCMPD _SFR_MEM8(0x092E) -#define TCD2_HCMPD _SFR_MEM8(0x092F) - -/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ -#define USARTD0_DATA _SFR_MEM8(0x09A0) -#define USARTD0_STATUS _SFR_MEM8(0x09A1) -#define USARTD0_CTRLA _SFR_MEM8(0x09A3) -#define USARTD0_CTRLB _SFR_MEM8(0x09A4) -#define USARTD0_CTRLC _SFR_MEM8(0x09A5) -#define USARTD0_BAUDCTRLA _SFR_MEM8(0x09A6) -#define USARTD0_BAUDCTRLB _SFR_MEM8(0x09A7) - -/* SPI - Serial Peripheral Interface */ -#define SPID_CTRL _SFR_MEM8(0x09C0) -#define SPID_INTCTRL _SFR_MEM8(0x09C1) -#define SPID_STATUS _SFR_MEM8(0x09C2) -#define SPID_DATA _SFR_MEM8(0x09C3) - -/* TC0 - 16-bit Timer/Counter 0 */ -#define TCE0_CTRLA _SFR_MEM8(0x0A00) -#define TCE0_CTRLB _SFR_MEM8(0x0A01) -#define TCE0_CTRLC _SFR_MEM8(0x0A02) -#define TCE0_CTRLD _SFR_MEM8(0x0A03) -#define TCE0_CTRLE _SFR_MEM8(0x0A04) -#define TCE0_INTCTRLA _SFR_MEM8(0x0A06) -#define TCE0_INTCTRLB _SFR_MEM8(0x0A07) -#define TCE0_CTRLFCLR _SFR_MEM8(0x0A08) -#define TCE0_CTRLFSET _SFR_MEM8(0x0A09) -#define TCE0_CTRLGCLR _SFR_MEM8(0x0A0A) -#define TCE0_CTRLGSET _SFR_MEM8(0x0A0B) -#define TCE0_INTFLAGS _SFR_MEM8(0x0A0C) -#define TCE0_TEMP _SFR_MEM8(0x0A0F) -#define TCE0_CNT _SFR_MEM16(0x0A20) -#define TCE0_PER _SFR_MEM16(0x0A26) -#define TCE0_CCA _SFR_MEM16(0x0A28) -#define TCE0_CCB _SFR_MEM16(0x0A2A) -#define TCE0_CCC _SFR_MEM16(0x0A2C) -#define TCE0_CCD _SFR_MEM16(0x0A2E) -#define TCE0_PERBUF _SFR_MEM16(0x0A36) -#define TCE0_CCABUF _SFR_MEM16(0x0A38) -#define TCE0_CCBBUF _SFR_MEM16(0x0A3A) -#define TCE0_CCCBUF _SFR_MEM16(0x0A3C) -#define TCE0_CCDBUF _SFR_MEM16(0x0A3E) - -/* TC2 - 16-bit Timer/Counter type 2 */ -#define TCE2_CTRLA _SFR_MEM8(0x0A00) -#define TCE2_CTRLB _SFR_MEM8(0x0A01) -#define TCE2_CTRLC _SFR_MEM8(0x0A02) -#define TCE2_CTRLE _SFR_MEM8(0x0A04) -#define TCE2_INTCTRLA _SFR_MEM8(0x0A06) -#define TCE2_INTCTRLB _SFR_MEM8(0x0A07) -#define TCE2_CTRLF _SFR_MEM8(0x0A09) -#define TCE2_INTFLAGS _SFR_MEM8(0x0A0C) -#define TCE2_LCNT _SFR_MEM8(0x0A20) -#define TCE2_HCNT _SFR_MEM8(0x0A21) -#define TCE2_LPER _SFR_MEM8(0x0A26) -#define TCE2_HPER _SFR_MEM8(0x0A27) -#define TCE2_LCMPA _SFR_MEM8(0x0A28) -#define TCE2_HCMPA _SFR_MEM8(0x0A29) -#define TCE2_LCMPB _SFR_MEM8(0x0A2A) -#define TCE2_HCMPB _SFR_MEM8(0x0A2B) -#define TCE2_LCMPC _SFR_MEM8(0x0A2C) -#define TCE2_HCMPC _SFR_MEM8(0x0A2D) -#define TCE2_LCMPD _SFR_MEM8(0x0A2E) -#define TCE2_HCMPD _SFR_MEM8(0x0A2F) - -/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ -#define USARTE0_DATA _SFR_MEM8(0x0AA0) -#define USARTE0_STATUS _SFR_MEM8(0x0AA1) -#define USARTE0_CTRLA _SFR_MEM8(0x0AA3) -#define USARTE0_CTRLB _SFR_MEM8(0x0AA4) -#define USARTE0_CTRLC _SFR_MEM8(0x0AA5) -#define USARTE0_BAUDCTRLA _SFR_MEM8(0x0AA6) -#define USARTE0_BAUDCTRLB _SFR_MEM8(0x0AA7) - -/* TC0 - 16-bit Timer/Counter 0 */ -#define TCF0_CTRLA _SFR_MEM8(0x0B00) -#define TCF0_CTRLB _SFR_MEM8(0x0B01) -#define TCF0_CTRLC _SFR_MEM8(0x0B02) -#define TCF0_CTRLD _SFR_MEM8(0x0B03) -#define TCF0_CTRLE _SFR_MEM8(0x0B04) -#define TCF0_INTCTRLA _SFR_MEM8(0x0B06) -#define TCF0_INTCTRLB _SFR_MEM8(0x0B07) -#define TCF0_CTRLFCLR _SFR_MEM8(0x0B08) -#define TCF0_CTRLFSET _SFR_MEM8(0x0B09) -#define TCF0_CTRLGCLR _SFR_MEM8(0x0B0A) -#define TCF0_CTRLGSET _SFR_MEM8(0x0B0B) -#define TCF0_INTFLAGS _SFR_MEM8(0x0B0C) -#define TCF0_TEMP _SFR_MEM8(0x0B0F) -#define TCF0_CNT _SFR_MEM16(0x0B20) -#define TCF0_PER _SFR_MEM16(0x0B26) -#define TCF0_CCA _SFR_MEM16(0x0B28) -#define TCF0_CCB _SFR_MEM16(0x0B2A) -#define TCF0_CCC _SFR_MEM16(0x0B2C) -#define TCF0_CCD _SFR_MEM16(0x0B2E) -#define TCF0_PERBUF _SFR_MEM16(0x0B36) -#define TCF0_CCABUF _SFR_MEM16(0x0B38) -#define TCF0_CCBBUF _SFR_MEM16(0x0B3A) -#define TCF0_CCCBUF _SFR_MEM16(0x0B3C) -#define TCF0_CCDBUF _SFR_MEM16(0x0B3E) - -/* TC2 - 16-bit Timer/Counter type 2 */ -#define TCF2_CTRLA _SFR_MEM8(0x0B00) -#define TCF2_CTRLB _SFR_MEM8(0x0B01) -#define TCF2_CTRLC _SFR_MEM8(0x0B02) -#define TCF2_CTRLE _SFR_MEM8(0x0B04) -#define TCF2_INTCTRLA _SFR_MEM8(0x0B06) -#define TCF2_INTCTRLB _SFR_MEM8(0x0B07) -#define TCF2_CTRLF _SFR_MEM8(0x0B09) -#define TCF2_INTFLAGS _SFR_MEM8(0x0B0C) -#define TCF2_LCNT _SFR_MEM8(0x0B20) -#define TCF2_HCNT _SFR_MEM8(0x0B21) -#define TCF2_LPER _SFR_MEM8(0x0B26) -#define TCF2_HPER _SFR_MEM8(0x0B27) -#define TCF2_LCMPA _SFR_MEM8(0x0B28) -#define TCF2_HCMPA _SFR_MEM8(0x0B29) -#define TCF2_LCMPB _SFR_MEM8(0x0B2A) -#define TCF2_HCMPB _SFR_MEM8(0x0B2B) -#define TCF2_LCMPC _SFR_MEM8(0x0B2C) -#define TCF2_HCMPC _SFR_MEM8(0x0B2D) -#define TCF2_LCMPD _SFR_MEM8(0x0B2E) -#define TCF2_HCMPD _SFR_MEM8(0x0B2F) - - - -/*================== Bitfield Definitions ================== */ - -/* VPORT - Virtual Ports */ -/* VPORT.INTFLAGS bit masks and bit positions */ -#define VPORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ -#define VPORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ - -#define VPORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ -#define VPORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ - -/* XOCD - On-Chip Debug System */ -/* OCD.OCDR0 bit masks and bit positions */ -#define OCD_OCDRD_gm 0xFF /* OCDR Dirty group mask. */ -#define OCD_OCDRD_gp 0 /* OCDR Dirty group position. */ -#define OCD_OCDRD0_bm (1<<0) /* OCDR Dirty bit 0 mask. */ -#define OCD_OCDRD0_bp 0 /* OCDR Dirty bit 0 position. */ -#define OCD_OCDRD1_bm (1<<1) /* OCDR Dirty bit 1 mask. */ -#define OCD_OCDRD1_bp 1 /* OCDR Dirty bit 1 position. */ -#define OCD_OCDRD2_bm (1<<2) /* OCDR Dirty bit 2 mask. */ -#define OCD_OCDRD2_bp 2 /* OCDR Dirty bit 2 position. */ -#define OCD_OCDRD3_bm (1<<3) /* OCDR Dirty bit 3 mask. */ -#define OCD_OCDRD3_bp 3 /* OCDR Dirty bit 3 position. */ -#define OCD_OCDRD4_bm (1<<4) /* OCDR Dirty bit 4 mask. */ -#define OCD_OCDRD4_bp 4 /* OCDR Dirty bit 4 position. */ -#define OCD_OCDRD5_bm (1<<5) /* OCDR Dirty bit 5 mask. */ -#define OCD_OCDRD5_bp 5 /* OCDR Dirty bit 5 position. */ -#define OCD_OCDRD6_bm (1<<6) /* OCDR Dirty bit 6 mask. */ -#define OCD_OCDRD6_bp 6 /* OCDR Dirty bit 6 position. */ -#define OCD_OCDRD7_bm (1<<7) /* OCDR Dirty bit 7 mask. */ -#define OCD_OCDRD7_bp 7 /* OCDR Dirty bit 7 position. */ - -/* OCD.OCDR1 bit masks and bit positions */ -/* OCD_OCDRD Predefined. */ -/* OCD_OCDRD Predefined. */ - -/* CPU - CPU */ -/* CPU.CCP bit masks and bit positions */ -#define CPU_CCP_gm 0xFF /* CCP signature group mask. */ -#define CPU_CCP_gp 0 /* CCP signature group position. */ -#define CPU_CCP0_bm (1<<0) /* CCP signature bit 0 mask. */ -#define CPU_CCP0_bp 0 /* CCP signature bit 0 position. */ -#define CPU_CCP1_bm (1<<1) /* CCP signature bit 1 mask. */ -#define CPU_CCP1_bp 1 /* CCP signature bit 1 position. */ -#define CPU_CCP2_bm (1<<2) /* CCP signature bit 2 mask. */ -#define CPU_CCP2_bp 2 /* CCP signature bit 2 position. */ -#define CPU_CCP3_bm (1<<3) /* CCP signature bit 3 mask. */ -#define CPU_CCP3_bp 3 /* CCP signature bit 3 position. */ -#define CPU_CCP4_bm (1<<4) /* CCP signature bit 4 mask. */ -#define CPU_CCP4_bp 4 /* CCP signature bit 4 position. */ -#define CPU_CCP5_bm (1<<5) /* CCP signature bit 5 mask. */ -#define CPU_CCP5_bp 5 /* CCP signature bit 5 position. */ -#define CPU_CCP6_bm (1<<6) /* CCP signature bit 6 mask. */ -#define CPU_CCP6_bp 6 /* CCP signature bit 6 position. */ -#define CPU_CCP7_bm (1<<7) /* CCP signature bit 7 mask. */ -#define CPU_CCP7_bp 7 /* CCP signature bit 7 position. */ - -/* CPU.SREG bit masks and bit positions */ -#define CPU_I_bm 0x80 /* Global Interrupt Enable Flag bit mask. */ -#define CPU_I_bp 7 /* Global Interrupt Enable Flag bit position. */ - -#define CPU_T_bm 0x40 /* Transfer Bit bit mask. */ -#define CPU_T_bp 6 /* Transfer Bit bit position. */ - -#define CPU_H_bm 0x20 /* Half Carry Flag bit mask. */ -#define CPU_H_bp 5 /* Half Carry Flag bit position. */ - -#define CPU_S_bm 0x10 /* N Exclusive Or V Flag bit mask. */ -#define CPU_S_bp 4 /* N Exclusive Or V Flag bit position. */ - -#define CPU_V_bm 0x08 /* Two's Complement Overflow Flag bit mask. */ -#define CPU_V_bp 3 /* Two's Complement Overflow Flag bit position. */ - -#define CPU_N_bm 0x04 /* Negative Flag bit mask. */ -#define CPU_N_bp 2 /* Negative Flag bit position. */ - -#define CPU_Z_bm 0x02 /* Zero Flag bit mask. */ -#define CPU_Z_bp 1 /* Zero Flag bit position. */ - -#define CPU_C_bm 0x01 /* Carry Flag bit mask. */ -#define CPU_C_bp 0 /* Carry Flag bit position. */ - -/* CLK - Clock System */ -/* CLK.CTRL bit masks and bit positions */ -#define CLK_SCLKSEL_gm 0x07 /* System Clock Selection group mask. */ -#define CLK_SCLKSEL_gp 0 /* System Clock Selection group position. */ -#define CLK_SCLKSEL0_bm (1<<0) /* System Clock Selection bit 0 mask. */ -#define CLK_SCLKSEL0_bp 0 /* System Clock Selection bit 0 position. */ -#define CLK_SCLKSEL1_bm (1<<1) /* System Clock Selection bit 1 mask. */ -#define CLK_SCLKSEL1_bp 1 /* System Clock Selection bit 1 position. */ -#define CLK_SCLKSEL2_bm (1<<2) /* System Clock Selection bit 2 mask. */ -#define CLK_SCLKSEL2_bp 2 /* System Clock Selection bit 2 position. */ - -/* CLK.PSCTRL bit masks and bit positions */ -#define CLK_PSADIV_gm 0x7C /* Prescaler A Division Factor group mask. */ -#define CLK_PSADIV_gp 2 /* Prescaler A Division Factor group position. */ -#define CLK_PSADIV0_bm (1<<2) /* Prescaler A Division Factor bit 0 mask. */ -#define CLK_PSADIV0_bp 2 /* Prescaler A Division Factor bit 0 position. */ -#define CLK_PSADIV1_bm (1<<3) /* Prescaler A Division Factor bit 1 mask. */ -#define CLK_PSADIV1_bp 3 /* Prescaler A Division Factor bit 1 position. */ -#define CLK_PSADIV2_bm (1<<4) /* Prescaler A Division Factor bit 2 mask. */ -#define CLK_PSADIV2_bp 4 /* Prescaler A Division Factor bit 2 position. */ -#define CLK_PSADIV3_bm (1<<5) /* Prescaler A Division Factor bit 3 mask. */ -#define CLK_PSADIV3_bp 5 /* Prescaler A Division Factor bit 3 position. */ -#define CLK_PSADIV4_bm (1<<6) /* Prescaler A Division Factor bit 4 mask. */ -#define CLK_PSADIV4_bp 6 /* Prescaler A Division Factor bit 4 position. */ - -#define CLK_PSBCDIV_gm 0x03 /* Prescaler B and C Division factor group mask. */ -#define CLK_PSBCDIV_gp 0 /* Prescaler B and C Division factor group position. */ -#define CLK_PSBCDIV0_bm (1<<0) /* Prescaler B and C Division factor bit 0 mask. */ -#define CLK_PSBCDIV0_bp 0 /* Prescaler B and C Division factor bit 0 position. */ -#define CLK_PSBCDIV1_bm (1<<1) /* Prescaler B and C Division factor bit 1 mask. */ -#define CLK_PSBCDIV1_bp 1 /* Prescaler B and C Division factor bit 1 position. */ - -/* CLK.LOCK bit masks and bit positions */ -#define CLK_LOCK_bm 0x01 /* Clock System Lock bit mask. */ -#define CLK_LOCK_bp 0 /* Clock System Lock bit position. */ - -/* CLK.RTCCTRL bit masks and bit positions */ -#define CLK_RTCSRC_gm 0x0E /* Clock Source group mask. */ -#define CLK_RTCSRC_gp 1 /* Clock Source group position. */ -#define CLK_RTCSRC0_bm (1<<1) /* Clock Source bit 0 mask. */ -#define CLK_RTCSRC0_bp 1 /* Clock Source bit 0 position. */ -#define CLK_RTCSRC1_bm (1<<2) /* Clock Source bit 1 mask. */ -#define CLK_RTCSRC1_bp 2 /* Clock Source bit 1 position. */ -#define CLK_RTCSRC2_bm (1<<3) /* Clock Source bit 2 mask. */ -#define CLK_RTCSRC2_bp 3 /* Clock Source bit 2 position. */ - -#define CLK_RTCEN_bm 0x01 /* Clock Source Enable bit mask. */ -#define CLK_RTCEN_bp 0 /* Clock Source Enable bit position. */ - -/* CLK.USBCTRL bit masks and bit positions */ -#define CLK_USBPSDIV_gm 0x38 /* Prescaler Division Factor group mask. */ -#define CLK_USBPSDIV_gp 3 /* Prescaler Division Factor group position. */ -#define CLK_USBPSDIV0_bm (1<<3) /* Prescaler Division Factor bit 0 mask. */ -#define CLK_USBPSDIV0_bp 3 /* Prescaler Division Factor bit 0 position. */ -#define CLK_USBPSDIV1_bm (1<<4) /* Prescaler Division Factor bit 1 mask. */ -#define CLK_USBPSDIV1_bp 4 /* Prescaler Division Factor bit 1 position. */ -#define CLK_USBPSDIV2_bm (1<<5) /* Prescaler Division Factor bit 2 mask. */ -#define CLK_USBPSDIV2_bp 5 /* Prescaler Division Factor bit 2 position. */ - -#define CLK_USBSRC_gm 0x06 /* Clock Source group mask. */ -#define CLK_USBSRC_gp 1 /* Clock Source group position. */ -#define CLK_USBSRC0_bm (1<<1) /* Clock Source bit 0 mask. */ -#define CLK_USBSRC0_bp 1 /* Clock Source bit 0 position. */ -#define CLK_USBSRC1_bm (1<<2) /* Clock Source bit 1 mask. */ -#define CLK_USBSRC1_bp 2 /* Clock Source bit 1 position. */ - -#define CLK_USBSEN_bm 0x01 /* Clock Source Enable bit mask. */ -#define CLK_USBSEN_bp 0 /* Clock Source Enable bit position. */ - -/* PR.PRGEN bit masks and bit positions */ -#define PR_USB_bm 0x40 /* USB bit mask. */ -#define PR_USB_bp 6 /* USB bit position. */ - -#define PR_AES_bm 0x10 /* AES bit mask. */ -#define PR_AES_bp 4 /* AES bit position. */ - -#define PR_RTC_bm 0x04 /* Real-time Counter bit mask. */ -#define PR_RTC_bp 2 /* Real-time Counter bit position. */ - -#define PR_EVSYS_bm 0x02 /* Event System bit mask. */ -#define PR_EVSYS_bp 1 /* Event System bit position. */ - -#define PR_DMA_bm 0x01 /* DMA-Controller bit mask. */ -#define PR_DMA_bp 0 /* DMA-Controller bit position. */ - -/* PR.PRPA bit masks and bit positions */ -#define PR_ADC_bm 0x02 /* Port A ADC bit mask. */ -#define PR_ADC_bp 1 /* Port A ADC bit position. */ - -#define PR_AC_bm 0x01 /* Port A Analog Comparator bit mask. */ -#define PR_AC_bp 0 /* Port A Analog Comparator bit position. */ - -/* PR.PRPC bit masks and bit positions */ -#define PR_TWI_bm 0x40 /* Port C Two-wire Interface bit mask. */ -#define PR_TWI_bp 6 /* Port C Two-wire Interface bit position. */ - -#define PR_USART1_bm 0x20 /* Port C USART1 bit mask. */ -#define PR_USART1_bp 5 /* Port C USART1 bit position. */ - -#define PR_USART0_bm 0x10 /* Port C USART0 bit mask. */ -#define PR_USART0_bp 4 /* Port C USART0 bit position. */ - -#define PR_SPI_bm 0x08 /* Port C SPI bit mask. */ -#define PR_SPI_bp 3 /* Port C SPI bit position. */ - -#define PR_HIRES_bm 0x04 /* Port C AWEX bit mask. */ -#define PR_HIRES_bp 2 /* Port C AWEX bit position. */ - -#define PR_TC1_bm 0x02 /* Port C Timer/Counter1 bit mask. */ -#define PR_TC1_bp 1 /* Port C Timer/Counter1 bit position. */ - -#define PR_TC0_bm 0x01 /* Port C Timer/Counter0 bit mask. */ -#define PR_TC0_bp 0 /* Port C Timer/Counter0 bit position. */ - -/* PR.PRPD bit masks and bit positions */ -/* PR_USART0 Predefined. */ -/* PR_USART0 Predefined. */ - -/* PR_SPI Predefined. */ -/* PR_SPI Predefined. */ - -/* PR_TC0 Predefined. */ -/* PR_TC0 Predefined. */ - -/* PR.PRPE bit masks and bit positions */ -/* PR_TWI Predefined. */ -/* PR_TWI Predefined. */ - -/* PR_USART0 Predefined. */ -/* PR_USART0 Predefined. */ - -/* PR_TC0 Predefined. */ -/* PR_TC0 Predefined. */ - -/* PR.PRPF bit masks and bit positions */ -/* PR_USART0 Predefined. */ -/* PR_USART0 Predefined. */ - -/* PR_TC0 Predefined. */ -/* PR_TC0 Predefined. */ - -/* SLEEP - Sleep Controller */ -/* SLEEP.CTRL bit masks and bit positions */ -#define SLEEP_SMODE_gm 0x0E /* Sleep Mode group mask. */ -#define SLEEP_SMODE_gp 1 /* Sleep Mode group position. */ -#define SLEEP_SMODE0_bm (1<<1) /* Sleep Mode bit 0 mask. */ -#define SLEEP_SMODE0_bp 1 /* Sleep Mode bit 0 position. */ -#define SLEEP_SMODE1_bm (1<<2) /* Sleep Mode bit 1 mask. */ -#define SLEEP_SMODE1_bp 2 /* Sleep Mode bit 1 position. */ -#define SLEEP_SMODE2_bm (1<<3) /* Sleep Mode bit 2 mask. */ -#define SLEEP_SMODE2_bp 3 /* Sleep Mode bit 2 position. */ - -#define SLEEP_SEN_bm 0x01 /* Sleep Enable bit mask. */ -#define SLEEP_SEN_bp 0 /* Sleep Enable bit position. */ - -/* OSC - Oscillator */ -/* OSC.CTRL bit masks and bit positions */ -#define OSC_PLLEN_bm 0x10 /* PLL Enable bit mask. */ -#define OSC_PLLEN_bp 4 /* PLL Enable bit position. */ - -#define OSC_XOSCEN_bm 0x08 /* External Oscillator Enable bit mask. */ -#define OSC_XOSCEN_bp 3 /* External Oscillator Enable bit position. */ - -#define OSC_RC32KEN_bm 0x04 /* Internal 32.768 kHz RC Oscillator Enable bit mask. */ -#define OSC_RC32KEN_bp 2 /* Internal 32.768 kHz RC Oscillator Enable bit position. */ - -#define OSC_RC32MEN_bm 0x02 /* Internal 32 MHz RC Oscillator Enable bit mask. */ -#define OSC_RC32MEN_bp 1 /* Internal 32 MHz RC Oscillator Enable bit position. */ - -#define OSC_RC2MEN_bm 0x01 /* Internal 2 MHz RC Oscillator Enable bit mask. */ -#define OSC_RC2MEN_bp 0 /* Internal 2 MHz RC Oscillator Enable bit position. */ - -/* OSC.STATUS bit masks and bit positions */ -#define OSC_PLLRDY_bm 0x10 /* PLL Ready bit mask. */ -#define OSC_PLLRDY_bp 4 /* PLL Ready bit position. */ - -#define OSC_XOSCRDY_bm 0x08 /* External Oscillator Ready bit mask. */ -#define OSC_XOSCRDY_bp 3 /* External Oscillator Ready bit position. */ - -#define OSC_RC32KRDY_bm 0x04 /* Internal 32.768 kHz RC Oscillator Ready bit mask. */ -#define OSC_RC32KRDY_bp 2 /* Internal 32.768 kHz RC Oscillator Ready bit position. */ - -#define OSC_RC32MRDY_bm 0x02 /* Internal 32 MHz RC Oscillator Ready bit mask. */ -#define OSC_RC32MRDY_bp 1 /* Internal 32 MHz RC Oscillator Ready bit position. */ - -#define OSC_RC2MRDY_bm 0x01 /* Internal 2 MHz RC Oscillator Ready bit mask. */ -#define OSC_RC2MRDY_bp 0 /* Internal 2 MHz RC Oscillator Ready bit position. */ - -/* OSC.XOSCCTRL bit masks and bit positions */ -#define OSC_FRQRANGE_gm 0xC0 /* Frequency Range group mask. */ -#define OSC_FRQRANGE_gp 6 /* Frequency Range group position. */ -#define OSC_FRQRANGE0_bm (1<<6) /* Frequency Range bit 0 mask. */ -#define OSC_FRQRANGE0_bp 6 /* Frequency Range bit 0 position. */ -#define OSC_FRQRANGE1_bm (1<<7) /* Frequency Range bit 1 mask. */ -#define OSC_FRQRANGE1_bp 7 /* Frequency Range bit 1 position. */ - -#define OSC_X32KLPM_bm 0x20 /* 32.768 kHz XTAL OSC Low-power Mode bit mask. */ -#define OSC_X32KLPM_bp 5 /* 32.768 kHz XTAL OSC Low-power Mode bit position. */ - -#define OSC_XOSCPWR_bm 0x10 /* 16 MHz Crystal Oscillator High Power mode bit mask. */ -#define OSC_XOSCPWR_bp 4 /* 16 MHz Crystal Oscillator High Power mode bit position. */ - -#define OSC_XOSCSEL_gm 0x0F /* External Oscillator Selection and Startup Time group mask. */ -#define OSC_XOSCSEL_gp 0 /* External Oscillator Selection and Startup Time group position. */ -#define OSC_XOSCSEL0_bm (1<<0) /* External Oscillator Selection and Startup Time bit 0 mask. */ -#define OSC_XOSCSEL0_bp 0 /* External Oscillator Selection and Startup Time bit 0 position. */ -#define OSC_XOSCSEL1_bm (1<<1) /* External Oscillator Selection and Startup Time bit 1 mask. */ -#define OSC_XOSCSEL1_bp 1 /* External Oscillator Selection and Startup Time bit 1 position. */ -#define OSC_XOSCSEL2_bm (1<<2) /* External Oscillator Selection and Startup Time bit 2 mask. */ -#define OSC_XOSCSEL2_bp 2 /* External Oscillator Selection and Startup Time bit 2 position. */ -#define OSC_XOSCSEL3_bm (1<<3) /* External Oscillator Selection and Startup Time bit 3 mask. */ -#define OSC_XOSCSEL3_bp 3 /* External Oscillator Selection and Startup Time bit 3 position. */ - -/* OSC.XOSCFAIL bit masks and bit positions */ -#define OSC_PLLFDIF_bm 0x08 /* PLL Failure Detection Interrupt Flag bit mask. */ -#define OSC_PLLFDIF_bp 3 /* PLL Failure Detection Interrupt Flag bit position. */ - -#define OSC_PLLFDEN_bm 0x04 /* PLL Failure Detection Enable bit mask. */ -#define OSC_PLLFDEN_bp 2 /* PLL Failure Detection Enable bit position. */ - -#define OSC_XOSCFDIF_bm 0x02 /* XOSC Failure Detection Interrupt Flag bit mask. */ -#define OSC_XOSCFDIF_bp 1 /* XOSC Failure Detection Interrupt Flag bit position. */ - -#define OSC_XOSCFDEN_bm 0x01 /* XOSC Failure Detection Enable bit mask. */ -#define OSC_XOSCFDEN_bp 0 /* XOSC Failure Detection Enable bit position. */ - -/* OSC.PLLCTRL bit masks and bit positions */ -#define OSC_PLLSRC_gm 0xC0 /* Clock Source group mask. */ -#define OSC_PLLSRC_gp 6 /* Clock Source group position. */ -#define OSC_PLLSRC0_bm (1<<6) /* Clock Source bit 0 mask. */ -#define OSC_PLLSRC0_bp 6 /* Clock Source bit 0 position. */ -#define OSC_PLLSRC1_bm (1<<7) /* Clock Source bit 1 mask. */ -#define OSC_PLLSRC1_bp 7 /* Clock Source bit 1 position. */ - -#define OSC_PLLDIV_bm 0x20 /* Divide by 2 bit mask. */ -#define OSC_PLLDIV_bp 5 /* Divide by 2 bit position. */ - -#define OSC_PLLFAC_gm 0x1F /* Multiplication Factor group mask. */ -#define OSC_PLLFAC_gp 0 /* Multiplication Factor group position. */ -#define OSC_PLLFAC0_bm (1<<0) /* Multiplication Factor bit 0 mask. */ -#define OSC_PLLFAC0_bp 0 /* Multiplication Factor bit 0 position. */ -#define OSC_PLLFAC1_bm (1<<1) /* Multiplication Factor bit 1 mask. */ -#define OSC_PLLFAC1_bp 1 /* Multiplication Factor bit 1 position. */ -#define OSC_PLLFAC2_bm (1<<2) /* Multiplication Factor bit 2 mask. */ -#define OSC_PLLFAC2_bp 2 /* Multiplication Factor bit 2 position. */ -#define OSC_PLLFAC3_bm (1<<3) /* Multiplication Factor bit 3 mask. */ -#define OSC_PLLFAC3_bp 3 /* Multiplication Factor bit 3 position. */ -#define OSC_PLLFAC4_bm (1<<4) /* Multiplication Factor bit 4 mask. */ -#define OSC_PLLFAC4_bp 4 /* Multiplication Factor bit 4 position. */ - -/* OSC.DFLLCTRL bit masks and bit positions */ -#define OSC_RC32MCREF_gm 0x06 /* 32 MHz DFLL Calibration Reference group mask. */ -#define OSC_RC32MCREF_gp 1 /* 32 MHz DFLL Calibration Reference group position. */ -#define OSC_RC32MCREF0_bm (1<<1) /* 32 MHz DFLL Calibration Reference bit 0 mask. */ -#define OSC_RC32MCREF0_bp 1 /* 32 MHz DFLL Calibration Reference bit 0 position. */ -#define OSC_RC32MCREF1_bm (1<<2) /* 32 MHz DFLL Calibration Reference bit 1 mask. */ -#define OSC_RC32MCREF1_bp 2 /* 32 MHz DFLL Calibration Reference bit 1 position. */ - -#define OSC_RC2MCREF_bm 0x01 /* 2 MHz DFLL Calibration Reference bit mask. */ -#define OSC_RC2MCREF_bp 0 /* 2 MHz DFLL Calibration Reference bit position. */ - -/* DFLL - DFLL */ -/* DFLL.CTRL bit masks and bit positions */ -#define DFLL_ENABLE_bm 0x01 /* DFLL Enable bit mask. */ -#define DFLL_ENABLE_bp 0 /* DFLL Enable bit position. */ - -/* DFLL.CALA bit masks and bit positions */ -#define DFLL_CALL_gm 0x7F /* DFLL Calibration Value A group mask. */ -#define DFLL_CALL_gp 0 /* DFLL Calibration Value A group position. */ -#define DFLL_CALL0_bm (1<<0) /* DFLL Calibration Value A bit 0 mask. */ -#define DFLL_CALL0_bp 0 /* DFLL Calibration Value A bit 0 position. */ -#define DFLL_CALL1_bm (1<<1) /* DFLL Calibration Value A bit 1 mask. */ -#define DFLL_CALL1_bp 1 /* DFLL Calibration Value A bit 1 position. */ -#define DFLL_CALL2_bm (1<<2) /* DFLL Calibration Value A bit 2 mask. */ -#define DFLL_CALL2_bp 2 /* DFLL Calibration Value A bit 2 position. */ -#define DFLL_CALL3_bm (1<<3) /* DFLL Calibration Value A bit 3 mask. */ -#define DFLL_CALL3_bp 3 /* DFLL Calibration Value A bit 3 position. */ -#define DFLL_CALL4_bm (1<<4) /* DFLL Calibration Value A bit 4 mask. */ -#define DFLL_CALL4_bp 4 /* DFLL Calibration Value A bit 4 position. */ -#define DFLL_CALL5_bm (1<<5) /* DFLL Calibration Value A bit 5 mask. */ -#define DFLL_CALL5_bp 5 /* DFLL Calibration Value A bit 5 position. */ -#define DFLL_CALL6_bm (1<<6) /* DFLL Calibration Value A bit 6 mask. */ -#define DFLL_CALL6_bp 6 /* DFLL Calibration Value A bit 6 position. */ - -/* DFLL.CALB bit masks and bit positions */ -#define DFLL_CALH_gm 0x3F /* DFLL Calibration Value B group mask. */ -#define DFLL_CALH_gp 0 /* DFLL Calibration Value B group position. */ -#define DFLL_CALH0_bm (1<<0) /* DFLL Calibration Value B bit 0 mask. */ -#define DFLL_CALH0_bp 0 /* DFLL Calibration Value B bit 0 position. */ -#define DFLL_CALH1_bm (1<<1) /* DFLL Calibration Value B bit 1 mask. */ -#define DFLL_CALH1_bp 1 /* DFLL Calibration Value B bit 1 position. */ -#define DFLL_CALH2_bm (1<<2) /* DFLL Calibration Value B bit 2 mask. */ -#define DFLL_CALH2_bp 2 /* DFLL Calibration Value B bit 2 position. */ -#define DFLL_CALH3_bm (1<<3) /* DFLL Calibration Value B bit 3 mask. */ -#define DFLL_CALH3_bp 3 /* DFLL Calibration Value B bit 3 position. */ -#define DFLL_CALH4_bm (1<<4) /* DFLL Calibration Value B bit 4 mask. */ -#define DFLL_CALH4_bp 4 /* DFLL Calibration Value B bit 4 position. */ -#define DFLL_CALH5_bm (1<<5) /* DFLL Calibration Value B bit 5 mask. */ -#define DFLL_CALH5_bp 5 /* DFLL Calibration Value B bit 5 position. */ - -/* RST - Reset */ -/* RST.STATUS bit masks and bit positions */ -#define RST_SDRF_bm 0x40 /* Spike Detection Reset Flag bit mask. */ -#define RST_SDRF_bp 6 /* Spike Detection Reset Flag bit position. */ - -#define RST_SRF_bm 0x20 /* Software Reset Flag bit mask. */ -#define RST_SRF_bp 5 /* Software Reset Flag bit position. */ - -#define RST_PDIRF_bm 0x10 /* Programming and Debug Interface Interface Reset Flag bit mask. */ -#define RST_PDIRF_bp 4 /* Programming and Debug Interface Interface Reset Flag bit position. */ - -#define RST_WDRF_bm 0x08 /* Watchdog Reset Flag bit mask. */ -#define RST_WDRF_bp 3 /* Watchdog Reset Flag bit position. */ - -#define RST_BORF_bm 0x04 /* Brown-out Reset Flag bit mask. */ -#define RST_BORF_bp 2 /* Brown-out Reset Flag bit position. */ - -#define RST_EXTRF_bm 0x02 /* External Reset Flag bit mask. */ -#define RST_EXTRF_bp 1 /* External Reset Flag bit position. */ - -#define RST_PORF_bm 0x01 /* Power-on Reset Flag bit mask. */ -#define RST_PORF_bp 0 /* Power-on Reset Flag bit position. */ - -/* RST.CTRL bit masks and bit positions */ -#define RST_SWRST_bm 0x01 /* Software Reset bit mask. */ -#define RST_SWRST_bp 0 /* Software Reset bit position. */ - -/* WDT - Watch-Dog Timer */ -/* WDT.CTRL bit masks and bit positions */ -#define WDT_PER_gm 0x3C /* Period group mask. */ -#define WDT_PER_gp 2 /* Period group position. */ -#define WDT_PER0_bm (1<<2) /* Period bit 0 mask. */ -#define WDT_PER0_bp 2 /* Period bit 0 position. */ -#define WDT_PER1_bm (1<<3) /* Period bit 1 mask. */ -#define WDT_PER1_bp 3 /* Period bit 1 position. */ -#define WDT_PER2_bm (1<<4) /* Period bit 2 mask. */ -#define WDT_PER2_bp 4 /* Period bit 2 position. */ -#define WDT_PER3_bm (1<<5) /* Period bit 3 mask. */ -#define WDT_PER3_bp 5 /* Period bit 3 position. */ - -#define WDT_ENABLE_bm 0x02 /* Enable bit mask. */ -#define WDT_ENABLE_bp 1 /* Enable bit position. */ - -#define WDT_CEN_bm 0x01 /* Change Enable bit mask. */ -#define WDT_CEN_bp 0 /* Change Enable bit position. */ - -/* WDT.WINCTRL bit masks and bit positions */ -#define WDT_WPER_gm 0x3C /* Windowed Mode Period group mask. */ -#define WDT_WPER_gp 2 /* Windowed Mode Period group position. */ -#define WDT_WPER0_bm (1<<2) /* Windowed Mode Period bit 0 mask. */ -#define WDT_WPER0_bp 2 /* Windowed Mode Period bit 0 position. */ -#define WDT_WPER1_bm (1<<3) /* Windowed Mode Period bit 1 mask. */ -#define WDT_WPER1_bp 3 /* Windowed Mode Period bit 1 position. */ -#define WDT_WPER2_bm (1<<4) /* Windowed Mode Period bit 2 mask. */ -#define WDT_WPER2_bp 4 /* Windowed Mode Period bit 2 position. */ -#define WDT_WPER3_bm (1<<5) /* Windowed Mode Period bit 3 mask. */ -#define WDT_WPER3_bp 5 /* Windowed Mode Period bit 3 position. */ - -#define WDT_WEN_bm 0x02 /* Windowed Mode Enable bit mask. */ -#define WDT_WEN_bp 1 /* Windowed Mode Enable bit position. */ - -#define WDT_WCEN_bm 0x01 /* Windowed Mode Change Enable bit mask. */ -#define WDT_WCEN_bp 0 /* Windowed Mode Change Enable bit position. */ - -/* WDT.STATUS bit masks and bit positions */ -#define WDT_SYNCBUSY_bm 0x01 /* Syncronization busy bit mask. */ -#define WDT_SYNCBUSY_bp 0 /* Syncronization busy bit position. */ - -/* MCU - MCU Control */ -/* MCU.ANAINIT bit masks and bit positions */ -#define MCU_STARTUPDLYA_gm 0x03 /* Analog startup delay Port A group mask. */ -#define MCU_STARTUPDLYA_gp 0 /* Analog startup delay Port A group position. */ -#define MCU_STARTUPDLYA0_bm (1<<0) /* Analog startup delay Port A bit 0 mask. */ -#define MCU_STARTUPDLYA0_bp 0 /* Analog startup delay Port A bit 0 position. */ -#define MCU_STARTUPDLYA1_bm (1<<1) /* Analog startup delay Port A bit 1 mask. */ -#define MCU_STARTUPDLYA1_bp 1 /* Analog startup delay Port A bit 1 position. */ - -/* MCU.EVSYSLOCK bit masks and bit positions */ -#define MCU_EVSYS0LOCK_bm 0x01 /* Event Channel 0-3 Lock bit mask. */ -#define MCU_EVSYS0LOCK_bp 0 /* Event Channel 0-3 Lock bit position. */ - -/* MCU.AWEXLOCK bit masks and bit positions */ -#define MCU_AWEXCLOCK_bm 0x01 /* AWeX on T/C C0 Lock bit mask. */ -#define MCU_AWEXCLOCK_bp 0 /* AWeX on T/C C0 Lock bit position. */ - -/* PMIC - Programmable Multi-level Interrupt Controller */ -/* PMIC.STATUS bit masks and bit positions */ -#define PMIC_NMIEX_bm 0x80 /* Non-maskable Interrupt Executing bit mask. */ -#define PMIC_NMIEX_bp 7 /* Non-maskable Interrupt Executing bit position. */ - -#define PMIC_HILVLEX_bm 0x04 /* High Level Interrupt Executing bit mask. */ -#define PMIC_HILVLEX_bp 2 /* High Level Interrupt Executing bit position. */ - -#define PMIC_MEDLVLEX_bm 0x02 /* Medium Level Interrupt Executing bit mask. */ -#define PMIC_MEDLVLEX_bp 1 /* Medium Level Interrupt Executing bit position. */ - -#define PMIC_LOLVLEX_bm 0x01 /* Low Level Interrupt Executing bit mask. */ -#define PMIC_LOLVLEX_bp 0 /* Low Level Interrupt Executing bit position. */ - -/* PMIC.INTPRI bit masks and bit positions */ -#define PMIC_INTPRI_gm 0xFF /* Interrupt Priority group mask. */ -#define PMIC_INTPRI_gp 0 /* Interrupt Priority group position. */ -#define PMIC_INTPRI0_bm (1<<0) /* Interrupt Priority bit 0 mask. */ -#define PMIC_INTPRI0_bp 0 /* Interrupt Priority bit 0 position. */ -#define PMIC_INTPRI1_bm (1<<1) /* Interrupt Priority bit 1 mask. */ -#define PMIC_INTPRI1_bp 1 /* Interrupt Priority bit 1 position. */ -#define PMIC_INTPRI2_bm (1<<2) /* Interrupt Priority bit 2 mask. */ -#define PMIC_INTPRI2_bp 2 /* Interrupt Priority bit 2 position. */ -#define PMIC_INTPRI3_bm (1<<3) /* Interrupt Priority bit 3 mask. */ -#define PMIC_INTPRI3_bp 3 /* Interrupt Priority bit 3 position. */ -#define PMIC_INTPRI4_bm (1<<4) /* Interrupt Priority bit 4 mask. */ -#define PMIC_INTPRI4_bp 4 /* Interrupt Priority bit 4 position. */ -#define PMIC_INTPRI5_bm (1<<5) /* Interrupt Priority bit 5 mask. */ -#define PMIC_INTPRI5_bp 5 /* Interrupt Priority bit 5 position. */ -#define PMIC_INTPRI6_bm (1<<6) /* Interrupt Priority bit 6 mask. */ -#define PMIC_INTPRI6_bp 6 /* Interrupt Priority bit 6 position. */ -#define PMIC_INTPRI7_bm (1<<7) /* Interrupt Priority bit 7 mask. */ -#define PMIC_INTPRI7_bp 7 /* Interrupt Priority bit 7 position. */ - -/* PMIC.CTRL bit masks and bit positions */ -#define PMIC_RREN_bm 0x80 /* Round-Robin Priority Enable bit mask. */ -#define PMIC_RREN_bp 7 /* Round-Robin Priority Enable bit position. */ - -#define PMIC_IVSEL_bm 0x40 /* Interrupt Vector Select bit mask. */ -#define PMIC_IVSEL_bp 6 /* Interrupt Vector Select bit position. */ - -#define PMIC_HILVLEN_bm 0x04 /* High Level Enable bit mask. */ -#define PMIC_HILVLEN_bp 2 /* High Level Enable bit position. */ - -#define PMIC_MEDLVLEN_bm 0x02 /* Medium Level Enable bit mask. */ -#define PMIC_MEDLVLEN_bp 1 /* Medium Level Enable bit position. */ - -#define PMIC_LOLVLEN_bm 0x01 /* Low Level Enable bit mask. */ -#define PMIC_LOLVLEN_bp 0 /* Low Level Enable bit position. */ - -/* PORTCFG - Port Configuration */ -/* PORTCFG.VPCTRLA bit masks and bit positions */ -#define PORTCFG_VP1MAP_gm 0xF0 /* Virtual Port 1 Mapping group mask. */ -#define PORTCFG_VP1MAP_gp 4 /* Virtual Port 1 Mapping group position. */ -#define PORTCFG_VP1MAP0_bm (1<<4) /* Virtual Port 1 Mapping bit 0 mask. */ -#define PORTCFG_VP1MAP0_bp 4 /* Virtual Port 1 Mapping bit 0 position. */ -#define PORTCFG_VP1MAP1_bm (1<<5) /* Virtual Port 1 Mapping bit 1 mask. */ -#define PORTCFG_VP1MAP1_bp 5 /* Virtual Port 1 Mapping bit 1 position. */ -#define PORTCFG_VP1MAP2_bm (1<<6) /* Virtual Port 1 Mapping bit 2 mask. */ -#define PORTCFG_VP1MAP2_bp 6 /* Virtual Port 1 Mapping bit 2 position. */ -#define PORTCFG_VP1MAP3_bm (1<<7) /* Virtual Port 1 Mapping bit 3 mask. */ -#define PORTCFG_VP1MAP3_bp 7 /* Virtual Port 1 Mapping bit 3 position. */ - -#define PORTCFG_VP0MAP_gm 0x0F /* Virtual Port 0 Mapping group mask. */ -#define PORTCFG_VP0MAP_gp 0 /* Virtual Port 0 Mapping group position. */ -#define PORTCFG_VP0MAP0_bm (1<<0) /* Virtual Port 0 Mapping bit 0 mask. */ -#define PORTCFG_VP0MAP0_bp 0 /* Virtual Port 0 Mapping bit 0 position. */ -#define PORTCFG_VP0MAP1_bm (1<<1) /* Virtual Port 0 Mapping bit 1 mask. */ -#define PORTCFG_VP0MAP1_bp 1 /* Virtual Port 0 Mapping bit 1 position. */ -#define PORTCFG_VP0MAP2_bm (1<<2) /* Virtual Port 0 Mapping bit 2 mask. */ -#define PORTCFG_VP0MAP2_bp 2 /* Virtual Port 0 Mapping bit 2 position. */ -#define PORTCFG_VP0MAP3_bm (1<<3) /* Virtual Port 0 Mapping bit 3 mask. */ -#define PORTCFG_VP0MAP3_bp 3 /* Virtual Port 0 Mapping bit 3 position. */ - -/* PORTCFG.VPCTRLB bit masks and bit positions */ -#define PORTCFG_VP3MAP_gm 0xF0 /* Virtual Port 3 Mapping group mask. */ -#define PORTCFG_VP3MAP_gp 4 /* Virtual Port 3 Mapping group position. */ -#define PORTCFG_VP3MAP0_bm (1<<4) /* Virtual Port 3 Mapping bit 0 mask. */ -#define PORTCFG_VP3MAP0_bp 4 /* Virtual Port 3 Mapping bit 0 position. */ -#define PORTCFG_VP3MAP1_bm (1<<5) /* Virtual Port 3 Mapping bit 1 mask. */ -#define PORTCFG_VP3MAP1_bp 5 /* Virtual Port 3 Mapping bit 1 position. */ -#define PORTCFG_VP3MAP2_bm (1<<6) /* Virtual Port 3 Mapping bit 2 mask. */ -#define PORTCFG_VP3MAP2_bp 6 /* Virtual Port 3 Mapping bit 2 position. */ -#define PORTCFG_VP3MAP3_bm (1<<7) /* Virtual Port 3 Mapping bit 3 mask. */ -#define PORTCFG_VP3MAP3_bp 7 /* Virtual Port 3 Mapping bit 3 position. */ - -#define PORTCFG_VP2MAP_gm 0x0F /* Virtual Port 2 Mapping group mask. */ -#define PORTCFG_VP2MAP_gp 0 /* Virtual Port 2 Mapping group position. */ -#define PORTCFG_VP2MAP0_bm (1<<0) /* Virtual Port 2 Mapping bit 0 mask. */ -#define PORTCFG_VP2MAP0_bp 0 /* Virtual Port 2 Mapping bit 0 position. */ -#define PORTCFG_VP2MAP1_bm (1<<1) /* Virtual Port 2 Mapping bit 1 mask. */ -#define PORTCFG_VP2MAP1_bp 1 /* Virtual Port 2 Mapping bit 1 position. */ -#define PORTCFG_VP2MAP2_bm (1<<2) /* Virtual Port 2 Mapping bit 2 mask. */ -#define PORTCFG_VP2MAP2_bp 2 /* Virtual Port 2 Mapping bit 2 position. */ -#define PORTCFG_VP2MAP3_bm (1<<3) /* Virtual Port 2 Mapping bit 3 mask. */ -#define PORTCFG_VP2MAP3_bp 3 /* Virtual Port 2 Mapping bit 3 position. */ - -/* PORTCFG.CLKEVOUT bit masks and bit positions */ -#define PORTCFG_CLKOUT_gm 0x03 /* Peripheral Clock Output Port group mask. */ -#define PORTCFG_CLKOUT_gp 0 /* Peripheral Clock Output Port group position. */ -#define PORTCFG_CLKOUT0_bm (1<<0) /* Peripheral Clock Output Port bit 0 mask. */ -#define PORTCFG_CLKOUT0_bp 0 /* Peripheral Clock Output Port bit 0 position. */ -#define PORTCFG_CLKOUT1_bm (1<<1) /* Peripheral Clock Output Port bit 1 mask. */ -#define PORTCFG_CLKOUT1_bp 1 /* Peripheral Clock Output Port bit 1 position. */ - -#define PORTCFG_CLKOUTSEL_gm 0x0C /* Peripheral Clock Output Select group mask. */ -#define PORTCFG_CLKOUTSEL_gp 2 /* Peripheral Clock Output Select group position. */ -#define PORTCFG_CLKOUTSEL0_bm (1<<2) /* Peripheral Clock Output Select bit 0 mask. */ -#define PORTCFG_CLKOUTSEL0_bp 2 /* Peripheral Clock Output Select bit 0 position. */ -#define PORTCFG_CLKOUTSEL1_bm (1<<3) /* Peripheral Clock Output Select bit 1 mask. */ -#define PORTCFG_CLKOUTSEL1_bp 3 /* Peripheral Clock Output Select bit 1 position. */ - -#define PORTCFG_EVOUT_gm 0x30 /* Event Output Port group mask. */ -#define PORTCFG_EVOUT_gp 4 /* Event Output Port group position. */ -#define PORTCFG_EVOUT0_bm (1<<4) /* Event Output Port bit 0 mask. */ -#define PORTCFG_EVOUT0_bp 4 /* Event Output Port bit 0 position. */ -#define PORTCFG_EVOUT1_bm (1<<5) /* Event Output Port bit 1 mask. */ -#define PORTCFG_EVOUT1_bp 5 /* Event Output Port bit 1 position. */ - -#define PORTCFG_RTCOUT_bm 0x40 /* RTC Clock Output bit mask. */ -#define PORTCFG_RTCOUT_bp 6 /* RTC Clock Output bit position. */ - -#define PORTCFG_CLKEVPIN_bm 0x80 /* Peripheral Clock and Event Output pin Select bit mask. */ -#define PORTCFG_CLKEVPIN_bp 7 /* Peripheral Clock and Event Output pin Select bit position. */ - -/* PORTCFG.EVOUTSEL bit masks and bit positions */ -#define PORTCFG_EVOUTSEL_gm 0x07 /* Event Output Select group mask. */ -#define PORTCFG_EVOUTSEL_gp 0 /* Event Output Select group position. */ -#define PORTCFG_EVOUTSEL0_bm (1<<0) /* Event Output Select bit 0 mask. */ -#define PORTCFG_EVOUTSEL0_bp 0 /* Event Output Select bit 0 position. */ -#define PORTCFG_EVOUTSEL1_bm (1<<1) /* Event Output Select bit 1 mask. */ -#define PORTCFG_EVOUTSEL1_bp 1 /* Event Output Select bit 1 position. */ -#define PORTCFG_EVOUTSEL2_bm (1<<2) /* Event Output Select bit 2 mask. */ -#define PORTCFG_EVOUTSEL2_bp 2 /* Event Output Select bit 2 position. */ - -/* CRC - Cyclic Redundancy Checker */ -/* CRC.CTRL bit masks and bit positions */ -#define CRC_RESET_gm 0xC0 /* Reset group mask. */ -#define CRC_RESET_gp 6 /* Reset group position. */ -#define CRC_RESET0_bm (1<<6) /* Reset bit 0 mask. */ -#define CRC_RESET0_bp 6 /* Reset bit 0 position. */ -#define CRC_RESET1_bm (1<<7) /* Reset bit 1 mask. */ -#define CRC_RESET1_bp 7 /* Reset bit 1 position. */ - -#define CRC_CRC32_bm 0x20 /* CRC Mode bit mask. */ -#define CRC_CRC32_bp 5 /* CRC Mode bit position. */ - -#define CRC_SOURCE_gm 0x0F /* Input Source group mask. */ -#define CRC_SOURCE_gp 0 /* Input Source group position. */ -#define CRC_SOURCE0_bm (1<<0) /* Input Source bit 0 mask. */ -#define CRC_SOURCE0_bp 0 /* Input Source bit 0 position. */ -#define CRC_SOURCE1_bm (1<<1) /* Input Source bit 1 mask. */ -#define CRC_SOURCE1_bp 1 /* Input Source bit 1 position. */ -#define CRC_SOURCE2_bm (1<<2) /* Input Source bit 2 mask. */ -#define CRC_SOURCE2_bp 2 /* Input Source bit 2 position. */ -#define CRC_SOURCE3_bm (1<<3) /* Input Source bit 3 mask. */ -#define CRC_SOURCE3_bp 3 /* Input Source bit 3 position. */ - -/* CRC.STATUS bit masks and bit positions */ -#define CRC_ZERO_bm 0x02 /* Zero detection bit mask. */ -#define CRC_ZERO_bp 1 /* Zero detection bit position. */ - -#define CRC_BUSY_bm 0x01 /* Busy bit mask. */ -#define CRC_BUSY_bp 0 /* Busy bit position. */ - -/* EVSYS - Event System */ -/* EVSYS.CH0MUX bit masks and bit positions */ -#define EVSYS_CHMUX_gm 0xFF /* Event Channel 0 Multiplexer group mask. */ -#define EVSYS_CHMUX_gp 0 /* Event Channel 0 Multiplexer group position. */ -#define EVSYS_CHMUX0_bm (1<<0) /* Event Channel 0 Multiplexer bit 0 mask. */ -#define EVSYS_CHMUX0_bp 0 /* Event Channel 0 Multiplexer bit 0 position. */ -#define EVSYS_CHMUX1_bm (1<<1) /* Event Channel 0 Multiplexer bit 1 mask. */ -#define EVSYS_CHMUX1_bp 1 /* Event Channel 0 Multiplexer bit 1 position. */ -#define EVSYS_CHMUX2_bm (1<<2) /* Event Channel 0 Multiplexer bit 2 mask. */ -#define EVSYS_CHMUX2_bp 2 /* Event Channel 0 Multiplexer bit 2 position. */ -#define EVSYS_CHMUX3_bm (1<<3) /* Event Channel 0 Multiplexer bit 3 mask. */ -#define EVSYS_CHMUX3_bp 3 /* Event Channel 0 Multiplexer bit 3 position. */ -#define EVSYS_CHMUX4_bm (1<<4) /* Event Channel 0 Multiplexer bit 4 mask. */ -#define EVSYS_CHMUX4_bp 4 /* Event Channel 0 Multiplexer bit 4 position. */ -#define EVSYS_CHMUX5_bm (1<<5) /* Event Channel 0 Multiplexer bit 5 mask. */ -#define EVSYS_CHMUX5_bp 5 /* Event Channel 0 Multiplexer bit 5 position. */ -#define EVSYS_CHMUX6_bm (1<<6) /* Event Channel 0 Multiplexer bit 6 mask. */ -#define EVSYS_CHMUX6_bp 6 /* Event Channel 0 Multiplexer bit 6 position. */ -#define EVSYS_CHMUX7_bm (1<<7) /* Event Channel 0 Multiplexer bit 7 mask. */ -#define EVSYS_CHMUX7_bp 7 /* Event Channel 0 Multiplexer bit 7 position. */ - -/* EVSYS.CH1MUX bit masks and bit positions */ -/* EVSYS_CHMUX Predefined. */ -/* EVSYS_CHMUX Predefined. */ - -/* EVSYS.CH2MUX bit masks and bit positions */ -/* EVSYS_CHMUX Predefined. */ -/* EVSYS_CHMUX Predefined. */ - -/* EVSYS.CH3MUX bit masks and bit positions */ -/* EVSYS_CHMUX Predefined. */ -/* EVSYS_CHMUX Predefined. */ - -/* EVSYS.CH0CTRL bit masks and bit positions */ -#define EVSYS_QDIRM_gm 0x60 /* Quadrature Decoder Index Recognition Mode group mask. */ -#define EVSYS_QDIRM_gp 5 /* Quadrature Decoder Index Recognition Mode group position. */ -#define EVSYS_QDIRM0_bm (1<<5) /* Quadrature Decoder Index Recognition Mode bit 0 mask. */ -#define EVSYS_QDIRM0_bp 5 /* Quadrature Decoder Index Recognition Mode bit 0 position. */ -#define EVSYS_QDIRM1_bm (1<<6) /* Quadrature Decoder Index Recognition Mode bit 1 mask. */ -#define EVSYS_QDIRM1_bp 6 /* Quadrature Decoder Index Recognition Mode bit 1 position. */ - -#define EVSYS_QDIEN_bm 0x10 /* Quadrature Decoder Index Enable bit mask. */ -#define EVSYS_QDIEN_bp 4 /* Quadrature Decoder Index Enable bit position. */ - -#define EVSYS_QDEN_bm 0x08 /* Quadrature Decoder Enable bit mask. */ -#define EVSYS_QDEN_bp 3 /* Quadrature Decoder Enable bit position. */ - -#define EVSYS_DIGFILT_gm 0x07 /* Digital Filter group mask. */ -#define EVSYS_DIGFILT_gp 0 /* Digital Filter group position. */ -#define EVSYS_DIGFILT0_bm (1<<0) /* Digital Filter bit 0 mask. */ -#define EVSYS_DIGFILT0_bp 0 /* Digital Filter bit 0 position. */ -#define EVSYS_DIGFILT1_bm (1<<1) /* Digital Filter bit 1 mask. */ -#define EVSYS_DIGFILT1_bp 1 /* Digital Filter bit 1 position. */ -#define EVSYS_DIGFILT2_bm (1<<2) /* Digital Filter bit 2 mask. */ -#define EVSYS_DIGFILT2_bp 2 /* Digital Filter bit 2 position. */ - -/* EVSYS.CH1CTRL bit masks and bit positions */ -/* EVSYS_DIGFILT Predefined. */ -/* EVSYS_DIGFILT Predefined. */ - -/* EVSYS.CH2CTRL bit masks and bit positions */ -/* EVSYS_DIGFILT Predefined. */ -/* EVSYS_DIGFILT Predefined. */ - -/* EVSYS.CH3CTRL bit masks and bit positions */ -/* EVSYS_DIGFILT Predefined. */ -/* EVSYS_DIGFILT Predefined. */ - -/* NVM - Non Volatile Memory Controller */ -/* NVM.CMD bit masks and bit positions */ -#define NVM_CMD_gm 0x7F /* Command group mask. */ -#define NVM_CMD_gp 0 /* Command group position. */ -#define NVM_CMD0_bm (1<<0) /* Command bit 0 mask. */ -#define NVM_CMD0_bp 0 /* Command bit 0 position. */ -#define NVM_CMD1_bm (1<<1) /* Command bit 1 mask. */ -#define NVM_CMD1_bp 1 /* Command bit 1 position. */ -#define NVM_CMD2_bm (1<<2) /* Command bit 2 mask. */ -#define NVM_CMD2_bp 2 /* Command bit 2 position. */ -#define NVM_CMD3_bm (1<<3) /* Command bit 3 mask. */ -#define NVM_CMD3_bp 3 /* Command bit 3 position. */ -#define NVM_CMD4_bm (1<<4) /* Command bit 4 mask. */ -#define NVM_CMD4_bp 4 /* Command bit 4 position. */ -#define NVM_CMD5_bm (1<<5) /* Command bit 5 mask. */ -#define NVM_CMD5_bp 5 /* Command bit 5 position. */ -#define NVM_CMD6_bm (1<<6) /* Command bit 6 mask. */ -#define NVM_CMD6_bp 6 /* Command bit 6 position. */ - -/* NVM.CTRLA bit masks and bit positions */ -#define NVM_CMDEX_bm 0x01 /* Command Execute bit mask. */ -#define NVM_CMDEX_bp 0 /* Command Execute bit position. */ - -/* NVM.CTRLB bit masks and bit positions */ -#define NVM_EEMAPEN_bm 0x08 /* EEPROM Mapping Enable bit mask. */ -#define NVM_EEMAPEN_bp 3 /* EEPROM Mapping Enable bit position. */ - -#define NVM_FPRM_bm 0x04 /* Flash Power Reduction Enable bit mask. */ -#define NVM_FPRM_bp 2 /* Flash Power Reduction Enable bit position. */ - -#define NVM_EPRM_bm 0x02 /* EEPROM Power Reduction Enable bit mask. */ -#define NVM_EPRM_bp 1 /* EEPROM Power Reduction Enable bit position. */ - -#define NVM_SPMLOCK_bm 0x01 /* SPM Lock bit mask. */ -#define NVM_SPMLOCK_bp 0 /* SPM Lock bit position. */ - -/* NVM.INTCTRL bit masks and bit positions */ -#define NVM_SPMLVL_gm 0x0C /* SPM Interrupt Level group mask. */ -#define NVM_SPMLVL_gp 2 /* SPM Interrupt Level group position. */ -#define NVM_SPMLVL0_bm (1<<2) /* SPM Interrupt Level bit 0 mask. */ -#define NVM_SPMLVL0_bp 2 /* SPM Interrupt Level bit 0 position. */ -#define NVM_SPMLVL1_bm (1<<3) /* SPM Interrupt Level bit 1 mask. */ -#define NVM_SPMLVL1_bp 3 /* SPM Interrupt Level bit 1 position. */ - -#define NVM_EELVL_gm 0x03 /* EEPROM Interrupt Level group mask. */ -#define NVM_EELVL_gp 0 /* EEPROM Interrupt Level group position. */ -#define NVM_EELVL0_bm (1<<0) /* EEPROM Interrupt Level bit 0 mask. */ -#define NVM_EELVL0_bp 0 /* EEPROM Interrupt Level bit 0 position. */ -#define NVM_EELVL1_bm (1<<1) /* EEPROM Interrupt Level bit 1 mask. */ -#define NVM_EELVL1_bp 1 /* EEPROM Interrupt Level bit 1 position. */ - -/* NVM.STATUS bit masks and bit positions */ -#define NVM_NVMBUSY_bm 0x80 /* Non-volatile Memory Busy bit mask. */ -#define NVM_NVMBUSY_bp 7 /* Non-volatile Memory Busy bit position. */ - -#define NVM_FBUSY_bm 0x40 /* Flash Memory Busy bit mask. */ -#define NVM_FBUSY_bp 6 /* Flash Memory Busy bit position. */ - -#define NVM_EELOAD_bm 0x02 /* EEPROM Page Buffer Active Loading bit mask. */ -#define NVM_EELOAD_bp 1 /* EEPROM Page Buffer Active Loading bit position. */ - -#define NVM_FLOAD_bm 0x01 /* Flash Page Buffer Active Loading bit mask. */ -#define NVM_FLOAD_bp 0 /* Flash Page Buffer Active Loading bit position. */ - -/* NVM.LOCKBITS bit masks and bit positions */ -#define NVM_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ -#define NVM_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ -#define NVM_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ -#define NVM_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ -#define NVM_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ -#define NVM_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ - -#define NVM_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ -#define NVM_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ -#define NVM_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ -#define NVM_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ -#define NVM_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ -#define NVM_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ - -#define NVM_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ -#define NVM_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ -#define NVM_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ -#define NVM_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ -#define NVM_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ -#define NVM_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ - -#define NVM_LB_gm 0x03 /* Lock Bits group mask. */ -#define NVM_LB_gp 0 /* Lock Bits group position. */ -#define NVM_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ -#define NVM_LB0_bp 0 /* Lock Bits bit 0 position. */ -#define NVM_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ -#define NVM_LB1_bp 1 /* Lock Bits bit 1 position. */ - -/* ADC - Analog/Digital Converter */ -/* ADC_CH.CTRL bit masks and bit positions */ -#define ADC_CH_START_bm 0x80 /* Channel Start Conversion bit mask. */ -#define ADC_CH_START_bp 7 /* Channel Start Conversion bit position. */ - -#define ADC_CH_GAIN_gm 0x1C /* Gain Factor group mask. */ -#define ADC_CH_GAIN_gp 2 /* Gain Factor group position. */ -#define ADC_CH_GAIN0_bm (1<<2) /* Gain Factor bit 0 mask. */ -#define ADC_CH_GAIN0_bp 2 /* Gain Factor bit 0 position. */ -#define ADC_CH_GAIN1_bm (1<<3) /* Gain Factor bit 1 mask. */ -#define ADC_CH_GAIN1_bp 3 /* Gain Factor bit 1 position. */ -#define ADC_CH_GAIN2_bm (1<<4) /* Gain Factor bit 2 mask. */ -#define ADC_CH_GAIN2_bp 4 /* Gain Factor bit 2 position. */ - -#define ADC_CH_INPUTMODE_gm 0x03 /* Input Mode Select group mask. */ -#define ADC_CH_INPUTMODE_gp 0 /* Input Mode Select group position. */ -#define ADC_CH_INPUTMODE0_bm (1<<0) /* Input Mode Select bit 0 mask. */ -#define ADC_CH_INPUTMODE0_bp 0 /* Input Mode Select bit 0 position. */ -#define ADC_CH_INPUTMODE1_bm (1<<1) /* Input Mode Select bit 1 mask. */ -#define ADC_CH_INPUTMODE1_bp 1 /* Input Mode Select bit 1 position. */ - -/* ADC_CH.MUXCTRL bit masks and bit positions */ -#define ADC_CH_MUXPOS_gm 0x78 /* MUX selection on Positive ADC input group mask. */ -#define ADC_CH_MUXPOS_gp 3 /* MUX selection on Positive ADC input group position. */ -#define ADC_CH_MUXPOS0_bm (1<<3) /* MUX selection on Positive ADC input bit 0 mask. */ -#define ADC_CH_MUXPOS0_bp 3 /* MUX selection on Positive ADC input bit 0 position. */ -#define ADC_CH_MUXPOS1_bm (1<<4) /* MUX selection on Positive ADC input bit 1 mask. */ -#define ADC_CH_MUXPOS1_bp 4 /* MUX selection on Positive ADC input bit 1 position. */ -#define ADC_CH_MUXPOS2_bm (1<<5) /* MUX selection on Positive ADC input bit 2 mask. */ -#define ADC_CH_MUXPOS2_bp 5 /* MUX selection on Positive ADC input bit 2 position. */ -#define ADC_CH_MUXPOS3_bm (1<<6) /* MUX selection on Positive ADC input bit 3 mask. */ -#define ADC_CH_MUXPOS3_bp 6 /* MUX selection on Positive ADC input bit 3 position. */ - -#define ADC_CH_MUXINT_gm 0x78 /* MUX selection on Internal ADC input group mask. */ -#define ADC_CH_MUXINT_gp 3 /* MUX selection on Internal ADC input group position. */ -#define ADC_CH_MUXINT0_bm (1<<3) /* MUX selection on Internal ADC input bit 0 mask. */ -#define ADC_CH_MUXINT0_bp 3 /* MUX selection on Internal ADC input bit 0 position. */ -#define ADC_CH_MUXINT1_bm (1<<4) /* MUX selection on Internal ADC input bit 1 mask. */ -#define ADC_CH_MUXINT1_bp 4 /* MUX selection on Internal ADC input bit 1 position. */ -#define ADC_CH_MUXINT2_bm (1<<5) /* MUX selection on Internal ADC input bit 2 mask. */ -#define ADC_CH_MUXINT2_bp 5 /* MUX selection on Internal ADC input bit 2 position. */ -#define ADC_CH_MUXINT3_bm (1<<6) /* MUX selection on Internal ADC input bit 3 mask. */ -#define ADC_CH_MUXINT3_bp 6 /* MUX selection on Internal ADC input bit 3 position. */ - -#define ADC_CH_MUXNEG_gm 0x03 /* MUX selection on Negative ADC input group mask. */ -#define ADC_CH_MUXNEG_gp 0 /* MUX selection on Negative ADC input group position. */ -#define ADC_CH_MUXNEG0_bm (1<<0) /* MUX selection on Negative ADC input bit 0 mask. */ -#define ADC_CH_MUXNEG0_bp 0 /* MUX selection on Negative ADC input bit 0 position. */ -#define ADC_CH_MUXNEG1_bm (1<<1) /* MUX selection on Negative ADC input bit 1 mask. */ -#define ADC_CH_MUXNEG1_bp 1 /* MUX selection on Negative ADC input bit 1 position. */ - -/* ADC_CH.INTCTRL bit masks and bit positions */ -#define ADC_CH_INTMODE_gm 0x0C /* Interrupt Mode group mask. */ -#define ADC_CH_INTMODE_gp 2 /* Interrupt Mode group position. */ -#define ADC_CH_INTMODE0_bm (1<<2) /* Interrupt Mode bit 0 mask. */ -#define ADC_CH_INTMODE0_bp 2 /* Interrupt Mode bit 0 position. */ -#define ADC_CH_INTMODE1_bm (1<<3) /* Interrupt Mode bit 1 mask. */ -#define ADC_CH_INTMODE1_bp 3 /* Interrupt Mode bit 1 position. */ - -#define ADC_CH_INTLVL_gm 0x03 /* Interrupt Level group mask. */ -#define ADC_CH_INTLVL_gp 0 /* Interrupt Level group position. */ -#define ADC_CH_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */ -#define ADC_CH_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */ -#define ADC_CH_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ -#define ADC_CH_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */ - -/* ADC_CH.INTFLAGS bit masks and bit positions */ -#define ADC_CH_CHIF_bm 0x01 /* Channel Interrupt Flag bit mask. */ -#define ADC_CH_CHIF_bp 0 /* Channel Interrupt Flag bit position. */ - -/* ADC_CH.SCAN bit masks and bit positions */ -#define ADC_CH_OFFSET_gm 0xF0 /* Positive MUX setting offset group mask. */ -#define ADC_CH_OFFSET_gp 4 /* Positive MUX setting offset group position. */ -#define ADC_CH_OFFSET0_bm (1<<4) /* Positive MUX setting offset bit 0 mask. */ -#define ADC_CH_OFFSET0_bp 4 /* Positive MUX setting offset bit 0 position. */ -#define ADC_CH_OFFSET1_bm (1<<5) /* Positive MUX setting offset bit 1 mask. */ -#define ADC_CH_OFFSET1_bp 5 /* Positive MUX setting offset bit 1 position. */ -#define ADC_CH_OFFSET2_bm (1<<6) /* Positive MUX setting offset bit 2 mask. */ -#define ADC_CH_OFFSET2_bp 6 /* Positive MUX setting offset bit 2 position. */ -#define ADC_CH_OFFSET3_bm (1<<7) /* Positive MUX setting offset bit 3 mask. */ -#define ADC_CH_OFFSET3_bp 7 /* Positive MUX setting offset bit 3 position. */ - -#define ADC_CH_SCANNUM_gm 0x0F /* Number of Channels included in scan group mask. */ -#define ADC_CH_SCANNUM_gp 0 /* Number of Channels included in scan group position. */ -#define ADC_CH_SCANNUM0_bm (1<<0) /* Number of Channels included in scan bit 0 mask. */ -#define ADC_CH_SCANNUM0_bp 0 /* Number of Channels included in scan bit 0 position. */ -#define ADC_CH_SCANNUM1_bm (1<<1) /* Number of Channels included in scan bit 1 mask. */ -#define ADC_CH_SCANNUM1_bp 1 /* Number of Channels included in scan bit 1 position. */ -#define ADC_CH_SCANNUM2_bm (1<<2) /* Number of Channels included in scan bit 2 mask. */ -#define ADC_CH_SCANNUM2_bp 2 /* Number of Channels included in scan bit 2 position. */ -#define ADC_CH_SCANNUM3_bm (1<<3) /* Number of Channels included in scan bit 3 mask. */ -#define ADC_CH_SCANNUM3_bp 3 /* Number of Channels included in scan bit 3 position. */ - -/* ADC.CTRLA bit masks and bit positions */ -#define ADC_CH0START_bm 0x04 /* Channel 0 Start Conversion bit mask. */ -#define ADC_CH0START_bp 2 /* Channel 0 Start Conversion bit position. */ - -#define ADC_FLUSH_bm 0x02 /* ADC Flush bit mask. */ -#define ADC_FLUSH_bp 1 /* ADC Flush bit position. */ - -#define ADC_ENABLE_bm 0x01 /* Enable ADC bit mask. */ -#define ADC_ENABLE_bp 0 /* Enable ADC bit position. */ - -/* ADC.CTRLB bit masks and bit positions */ -#define ADC_CURRLIMIT_gm 0x60 /* Current Limitation group mask. */ -#define ADC_CURRLIMIT_gp 5 /* Current Limitation group position. */ -#define ADC_CURRLIMIT0_bm (1<<5) /* Current Limitation bit 0 mask. */ -#define ADC_CURRLIMIT0_bp 5 /* Current Limitation bit 0 position. */ -#define ADC_CURRLIMIT1_bm (1<<6) /* Current Limitation bit 1 mask. */ -#define ADC_CURRLIMIT1_bp 6 /* Current Limitation bit 1 position. */ - -#define ADC_CONMODE_bm 0x10 /* Conversion Mode bit mask. */ -#define ADC_CONMODE_bp 4 /* Conversion Mode bit position. */ - -#define ADC_FREERUN_bm 0x08 /* Free Running Mode Enable bit mask. */ -#define ADC_FREERUN_bp 3 /* Free Running Mode Enable bit position. */ - -#define ADC_RESOLUTION_gm 0x06 /* Result Resolution group mask. */ -#define ADC_RESOLUTION_gp 1 /* Result Resolution group position. */ -#define ADC_RESOLUTION0_bm (1<<1) /* Result Resolution bit 0 mask. */ -#define ADC_RESOLUTION0_bp 1 /* Result Resolution bit 0 position. */ -#define ADC_RESOLUTION1_bm (1<<2) /* Result Resolution bit 1 mask. */ -#define ADC_RESOLUTION1_bp 2 /* Result Resolution bit 1 position. */ - -/* ADC.REFCTRL bit masks and bit positions */ -#define ADC_REFSEL_gm 0x70 /* Reference Selection group mask. */ -#define ADC_REFSEL_gp 4 /* Reference Selection group position. */ -#define ADC_REFSEL0_bm (1<<4) /* Reference Selection bit 0 mask. */ -#define ADC_REFSEL0_bp 4 /* Reference Selection bit 0 position. */ -#define ADC_REFSEL1_bm (1<<5) /* Reference Selection bit 1 mask. */ -#define ADC_REFSEL1_bp 5 /* Reference Selection bit 1 position. */ -#define ADC_REFSEL2_bm (1<<6) /* Reference Selection bit 2 mask. */ -#define ADC_REFSEL2_bp 6 /* Reference Selection bit 2 position. */ - -#define ADC_BANDGAP_bm 0x02 /* Bandgap enable bit mask. */ -#define ADC_BANDGAP_bp 1 /* Bandgap enable bit position. */ - -#define ADC_TEMPREF_bm 0x01 /* Temperature Reference Enable bit mask. */ -#define ADC_TEMPREF_bp 0 /* Temperature Reference Enable bit position. */ - -/* ADC.EVCTRL bit masks and bit positions */ -#define ADC_EVSEL_gm 0x18 /* Event Input Select group mask. */ -#define ADC_EVSEL_gp 3 /* Event Input Select group position. */ -#define ADC_EVSEL0_bm (1<<3) /* Event Input Select bit 0 mask. */ -#define ADC_EVSEL0_bp 3 /* Event Input Select bit 0 position. */ -#define ADC_EVSEL1_bm (1<<4) /* Event Input Select bit 1 mask. */ -#define ADC_EVSEL1_bp 4 /* Event Input Select bit 1 position. */ - -#define ADC_EVACT_gm 0x07 /* Event Action Select group mask. */ -#define ADC_EVACT_gp 0 /* Event Action Select group position. */ -#define ADC_EVACT0_bm (1<<0) /* Event Action Select bit 0 mask. */ -#define ADC_EVACT0_bp 0 /* Event Action Select bit 0 position. */ -#define ADC_EVACT1_bm (1<<1) /* Event Action Select bit 1 mask. */ -#define ADC_EVACT1_bp 1 /* Event Action Select bit 1 position. */ -#define ADC_EVACT2_bm (1<<2) /* Event Action Select bit 2 mask. */ -#define ADC_EVACT2_bp 2 /* Event Action Select bit 2 position. */ - -/* ADC.PRESCALER bit masks and bit positions */ -#define ADC_PRESCALER_gm 0x07 /* Clock Prescaler Selection group mask. */ -#define ADC_PRESCALER_gp 0 /* Clock Prescaler Selection group position. */ -#define ADC_PRESCALER0_bm (1<<0) /* Clock Prescaler Selection bit 0 mask. */ -#define ADC_PRESCALER0_bp 0 /* Clock Prescaler Selection bit 0 position. */ -#define ADC_PRESCALER1_bm (1<<1) /* Clock Prescaler Selection bit 1 mask. */ -#define ADC_PRESCALER1_bp 1 /* Clock Prescaler Selection bit 1 position. */ -#define ADC_PRESCALER2_bm (1<<2) /* Clock Prescaler Selection bit 2 mask. */ -#define ADC_PRESCALER2_bp 2 /* Clock Prescaler Selection bit 2 position. */ - -/* ADC.INTFLAGS bit masks and bit positions */ -#define ADC_CH0IF_bm 0x01 /* Channel 0 Interrupt Flag bit mask. */ -#define ADC_CH0IF_bp 0 /* Channel 0 Interrupt Flag bit position. */ - -/* AC - Analog Comparator */ -/* AC.AC0CTRL bit masks and bit positions */ -#define AC_INTMODE_gm 0xC0 /* Interrupt Mode group mask. */ -#define AC_INTMODE_gp 6 /* Interrupt Mode group position. */ -#define AC_INTMODE0_bm (1<<6) /* Interrupt Mode bit 0 mask. */ -#define AC_INTMODE0_bp 6 /* Interrupt Mode bit 0 position. */ -#define AC_INTMODE1_bm (1<<7) /* Interrupt Mode bit 1 mask. */ -#define AC_INTMODE1_bp 7 /* Interrupt Mode bit 1 position. */ - -#define AC_INTLVL_gm 0x30 /* Interrupt Level group mask. */ -#define AC_INTLVL_gp 4 /* Interrupt Level group position. */ -#define AC_INTLVL0_bm (1<<4) /* Interrupt Level bit 0 mask. */ -#define AC_INTLVL0_bp 4 /* Interrupt Level bit 0 position. */ -#define AC_INTLVL1_bm (1<<5) /* Interrupt Level bit 1 mask. */ -#define AC_INTLVL1_bp 5 /* Interrupt Level bit 1 position. */ - -#define AC_HYSMODE_gm 0x06 /* Hysteresis Mode group mask. */ -#define AC_HYSMODE_gp 1 /* Hysteresis Mode group position. */ -#define AC_HYSMODE0_bm (1<<1) /* Hysteresis Mode bit 0 mask. */ -#define AC_HYSMODE0_bp 1 /* Hysteresis Mode bit 0 position. */ -#define AC_HYSMODE1_bm (1<<2) /* Hysteresis Mode bit 1 mask. */ -#define AC_HYSMODE1_bp 2 /* Hysteresis Mode bit 1 position. */ - -#define AC_ENABLE_bm 0x01 /* Enable bit mask. */ -#define AC_ENABLE_bp 0 /* Enable bit position. */ - -/* AC.AC1CTRL bit masks and bit positions */ -/* AC_INTMODE Predefined. */ -/* AC_INTMODE Predefined. */ - -/* AC_INTLVL Predefined. */ -/* AC_INTLVL Predefined. */ - -/* AC_HYSMODE Predefined. */ -/* AC_HYSMODE Predefined. */ - -/* AC_ENABLE Predefined. */ -/* AC_ENABLE Predefined. */ - -/* AC.AC0MUXCTRL bit masks and bit positions */ -#define AC_MUXPOS_gm 0x38 /* MUX Positive Input group mask. */ -#define AC_MUXPOS_gp 3 /* MUX Positive Input group position. */ -#define AC_MUXPOS0_bm (1<<3) /* MUX Positive Input bit 0 mask. */ -#define AC_MUXPOS0_bp 3 /* MUX Positive Input bit 0 position. */ -#define AC_MUXPOS1_bm (1<<4) /* MUX Positive Input bit 1 mask. */ -#define AC_MUXPOS1_bp 4 /* MUX Positive Input bit 1 position. */ -#define AC_MUXPOS2_bm (1<<5) /* MUX Positive Input bit 2 mask. */ -#define AC_MUXPOS2_bp 5 /* MUX Positive Input bit 2 position. */ - -#define AC_MUXNEG_gm 0x07 /* MUX Negative Input group mask. */ -#define AC_MUXNEG_gp 0 /* MUX Negative Input group position. */ -#define AC_MUXNEG0_bm (1<<0) /* MUX Negative Input bit 0 mask. */ -#define AC_MUXNEG0_bp 0 /* MUX Negative Input bit 0 position. */ -#define AC_MUXNEG1_bm (1<<1) /* MUX Negative Input bit 1 mask. */ -#define AC_MUXNEG1_bp 1 /* MUX Negative Input bit 1 position. */ -#define AC_MUXNEG2_bm (1<<2) /* MUX Negative Input bit 2 mask. */ -#define AC_MUXNEG2_bp 2 /* MUX Negative Input bit 2 position. */ - -/* AC.AC1MUXCTRL bit masks and bit positions */ -/* AC_MUXPOS Predefined. */ -/* AC_MUXPOS Predefined. */ - -/* AC_MUXNEG Predefined. */ -/* AC_MUXNEG Predefined. */ - -/* AC.CTRLA bit masks and bit positions */ -#define AC_AC1OUT_bm 0x02 /* Analog Comparator 1 Output Enable bit mask. */ -#define AC_AC1OUT_bp 1 /* Analog Comparator 1 Output Enable bit position. */ - -#define AC_AC0OUT_bm 0x01 /* Analog Comparator 0 Output Enable bit mask. */ -#define AC_AC0OUT_bp 0 /* Analog Comparator 0 Output Enable bit position. */ - -/* AC.CTRLB bit masks and bit positions */ -#define AC_SCALEFAC_gm 0x3F /* VCC Voltage Scaler Factor group mask. */ -#define AC_SCALEFAC_gp 0 /* VCC Voltage Scaler Factor group position. */ -#define AC_SCALEFAC0_bm (1<<0) /* VCC Voltage Scaler Factor bit 0 mask. */ -#define AC_SCALEFAC0_bp 0 /* VCC Voltage Scaler Factor bit 0 position. */ -#define AC_SCALEFAC1_bm (1<<1) /* VCC Voltage Scaler Factor bit 1 mask. */ -#define AC_SCALEFAC1_bp 1 /* VCC Voltage Scaler Factor bit 1 position. */ -#define AC_SCALEFAC2_bm (1<<2) /* VCC Voltage Scaler Factor bit 2 mask. */ -#define AC_SCALEFAC2_bp 2 /* VCC Voltage Scaler Factor bit 2 position. */ -#define AC_SCALEFAC3_bm (1<<3) /* VCC Voltage Scaler Factor bit 3 mask. */ -#define AC_SCALEFAC3_bp 3 /* VCC Voltage Scaler Factor bit 3 position. */ -#define AC_SCALEFAC4_bm (1<<4) /* VCC Voltage Scaler Factor bit 4 mask. */ -#define AC_SCALEFAC4_bp 4 /* VCC Voltage Scaler Factor bit 4 position. */ -#define AC_SCALEFAC5_bm (1<<5) /* VCC Voltage Scaler Factor bit 5 mask. */ -#define AC_SCALEFAC5_bp 5 /* VCC Voltage Scaler Factor bit 5 position. */ - -/* AC.WINCTRL bit masks and bit positions */ -#define AC_WEN_bm 0x10 /* Window Mode Enable bit mask. */ -#define AC_WEN_bp 4 /* Window Mode Enable bit position. */ - -#define AC_WINTMODE_gm 0x0C /* Window Interrupt Mode group mask. */ -#define AC_WINTMODE_gp 2 /* Window Interrupt Mode group position. */ -#define AC_WINTMODE0_bm (1<<2) /* Window Interrupt Mode bit 0 mask. */ -#define AC_WINTMODE0_bp 2 /* Window Interrupt Mode bit 0 position. */ -#define AC_WINTMODE1_bm (1<<3) /* Window Interrupt Mode bit 1 mask. */ -#define AC_WINTMODE1_bp 3 /* Window Interrupt Mode bit 1 position. */ - -#define AC_WINTLVL_gm 0x03 /* Window Interrupt Level group mask. */ -#define AC_WINTLVL_gp 0 /* Window Interrupt Level group position. */ -#define AC_WINTLVL0_bm (1<<0) /* Window Interrupt Level bit 0 mask. */ -#define AC_WINTLVL0_bp 0 /* Window Interrupt Level bit 0 position. */ -#define AC_WINTLVL1_bm (1<<1) /* Window Interrupt Level bit 1 mask. */ -#define AC_WINTLVL1_bp 1 /* Window Interrupt Level bit 1 position. */ - -/* AC.STATUS bit masks and bit positions */ -#define AC_WSTATE_gm 0xC0 /* Window Mode State group mask. */ -#define AC_WSTATE_gp 6 /* Window Mode State group position. */ -#define AC_WSTATE0_bm (1<<6) /* Window Mode State bit 0 mask. */ -#define AC_WSTATE0_bp 6 /* Window Mode State bit 0 position. */ -#define AC_WSTATE1_bm (1<<7) /* Window Mode State bit 1 mask. */ -#define AC_WSTATE1_bp 7 /* Window Mode State bit 1 position. */ - -#define AC_AC1STATE_bm 0x20 /* Analog Comparator 1 State bit mask. */ -#define AC_AC1STATE_bp 5 /* Analog Comparator 1 State bit position. */ - -#define AC_AC0STATE_bm 0x10 /* Analog Comparator 0 State bit mask. */ -#define AC_AC0STATE_bp 4 /* Analog Comparator 0 State bit position. */ - -#define AC_WIF_bm 0x04 /* Window Mode Interrupt Flag bit mask. */ -#define AC_WIF_bp 2 /* Window Mode Interrupt Flag bit position. */ - -#define AC_AC1IF_bm 0x02 /* Analog Comparator 1 Interrupt Flag bit mask. */ -#define AC_AC1IF_bp 1 /* Analog Comparator 1 Interrupt Flag bit position. */ - -#define AC_AC0IF_bm 0x01 /* Analog Comparator 0 Interrupt Flag bit mask. */ -#define AC_AC0IF_bp 0 /* Analog Comparator 0 Interrupt Flag bit position. */ - -/* RTC - Real-Time Counter */ -/* RTC.CTRL bit masks and bit positions */ -#define RTC_PRESCALER_gm 0x07 /* Prescaling Factor group mask. */ -#define RTC_PRESCALER_gp 0 /* Prescaling Factor group position. */ -#define RTC_PRESCALER0_bm (1<<0) /* Prescaling Factor bit 0 mask. */ -#define RTC_PRESCALER0_bp 0 /* Prescaling Factor bit 0 position. */ -#define RTC_PRESCALER1_bm (1<<1) /* Prescaling Factor bit 1 mask. */ -#define RTC_PRESCALER1_bp 1 /* Prescaling Factor bit 1 position. */ -#define RTC_PRESCALER2_bm (1<<2) /* Prescaling Factor bit 2 mask. */ -#define RTC_PRESCALER2_bp 2 /* Prescaling Factor bit 2 position. */ - -/* RTC.STATUS bit masks and bit positions */ -#define RTC_SYNCBUSY_bm 0x01 /* Synchronization Busy Flag bit mask. */ -#define RTC_SYNCBUSY_bp 0 /* Synchronization Busy Flag bit position. */ - -/* RTC.INTCTRL bit masks and bit positions */ -#define RTC_COMPINTLVL_gm 0x0C /* Compare Match Interrupt Level group mask. */ -#define RTC_COMPINTLVL_gp 2 /* Compare Match Interrupt Level group position. */ -#define RTC_COMPINTLVL0_bm (1<<2) /* Compare Match Interrupt Level bit 0 mask. */ -#define RTC_COMPINTLVL0_bp 2 /* Compare Match Interrupt Level bit 0 position. */ -#define RTC_COMPINTLVL1_bm (1<<3) /* Compare Match Interrupt Level bit 1 mask. */ -#define RTC_COMPINTLVL1_bp 3 /* Compare Match Interrupt Level bit 1 position. */ - -#define RTC_OVFINTLVL_gm 0x03 /* Overflow Interrupt Level group mask. */ -#define RTC_OVFINTLVL_gp 0 /* Overflow Interrupt Level group position. */ -#define RTC_OVFINTLVL0_bm (1<<0) /* Overflow Interrupt Level bit 0 mask. */ -#define RTC_OVFINTLVL0_bp 0 /* Overflow Interrupt Level bit 0 position. */ -#define RTC_OVFINTLVL1_bm (1<<1) /* Overflow Interrupt Level bit 1 mask. */ -#define RTC_OVFINTLVL1_bp 1 /* Overflow Interrupt Level bit 1 position. */ - -/* RTC.INTFLAGS bit masks and bit positions */ -#define RTC_COMPIF_bm 0x02 /* Compare Match Interrupt Flag bit mask. */ -#define RTC_COMPIF_bp 1 /* Compare Match Interrupt Flag bit position. */ - -#define RTC_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ -#define RTC_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ - -/* TWI - Two-Wire Interface */ -/* TWI_MASTER.CTRLA bit masks and bit positions */ -#define TWI_MASTER_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ -#define TWI_MASTER_INTLVL_gp 6 /* Interrupt Level group position. */ -#define TWI_MASTER_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ -#define TWI_MASTER_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ -#define TWI_MASTER_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ -#define TWI_MASTER_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ - -#define TWI_MASTER_RIEN_bm 0x20 /* Read Interrupt Enable bit mask. */ -#define TWI_MASTER_RIEN_bp 5 /* Read Interrupt Enable bit position. */ - -#define TWI_MASTER_WIEN_bm 0x10 /* Write Interrupt Enable bit mask. */ -#define TWI_MASTER_WIEN_bp 4 /* Write Interrupt Enable bit position. */ - -#define TWI_MASTER_ENABLE_bm 0x08 /* Enable TWI Master bit mask. */ -#define TWI_MASTER_ENABLE_bp 3 /* Enable TWI Master bit position. */ - -/* TWI_MASTER.CTRLB bit masks and bit positions */ -#define TWI_MASTER_TIMEOUT_gm 0x0C /* Inactive Bus Timeout group mask. */ -#define TWI_MASTER_TIMEOUT_gp 2 /* Inactive Bus Timeout group position. */ -#define TWI_MASTER_TIMEOUT0_bm (1<<2) /* Inactive Bus Timeout bit 0 mask. */ -#define TWI_MASTER_TIMEOUT0_bp 2 /* Inactive Bus Timeout bit 0 position. */ -#define TWI_MASTER_TIMEOUT1_bm (1<<3) /* Inactive Bus Timeout bit 1 mask. */ -#define TWI_MASTER_TIMEOUT1_bp 3 /* Inactive Bus Timeout bit 1 position. */ - -#define TWI_MASTER_QCEN_bm 0x02 /* Quick Command Enable bit mask. */ -#define TWI_MASTER_QCEN_bp 1 /* Quick Command Enable bit position. */ - -#define TWI_MASTER_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ -#define TWI_MASTER_SMEN_bp 0 /* Smart Mode Enable bit position. */ - -/* TWI_MASTER.CTRLC bit masks and bit positions */ -#define TWI_MASTER_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ -#define TWI_MASTER_ACKACT_bp 2 /* Acknowledge Action bit position. */ - -#define TWI_MASTER_CMD_gm 0x03 /* Command group mask. */ -#define TWI_MASTER_CMD_gp 0 /* Command group position. */ -#define TWI_MASTER_CMD0_bm (1<<0) /* Command bit 0 mask. */ -#define TWI_MASTER_CMD0_bp 0 /* Command bit 0 position. */ -#define TWI_MASTER_CMD1_bm (1<<1) /* Command bit 1 mask. */ -#define TWI_MASTER_CMD1_bp 1 /* Command bit 1 position. */ - -/* TWI_MASTER.STATUS bit masks and bit positions */ -#define TWI_MASTER_RIF_bm 0x80 /* Read Interrupt Flag bit mask. */ -#define TWI_MASTER_RIF_bp 7 /* Read Interrupt Flag bit position. */ - -#define TWI_MASTER_WIF_bm 0x40 /* Write Interrupt Flag bit mask. */ -#define TWI_MASTER_WIF_bp 6 /* Write Interrupt Flag bit position. */ - -#define TWI_MASTER_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ -#define TWI_MASTER_CLKHOLD_bp 5 /* Clock Hold bit position. */ - -#define TWI_MASTER_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ -#define TWI_MASTER_RXACK_bp 4 /* Received Acknowledge bit position. */ - -#define TWI_MASTER_ARBLOST_bm 0x08 /* Arbitration Lost bit mask. */ -#define TWI_MASTER_ARBLOST_bp 3 /* Arbitration Lost bit position. */ - -#define TWI_MASTER_BUSERR_bm 0x04 /* Bus Error bit mask. */ -#define TWI_MASTER_BUSERR_bp 2 /* Bus Error bit position. */ - -#define TWI_MASTER_BUSSTATE_gm 0x03 /* Bus State group mask. */ -#define TWI_MASTER_BUSSTATE_gp 0 /* Bus State group position. */ -#define TWI_MASTER_BUSSTATE0_bm (1<<0) /* Bus State bit 0 mask. */ -#define TWI_MASTER_BUSSTATE0_bp 0 /* Bus State bit 0 position. */ -#define TWI_MASTER_BUSSTATE1_bm (1<<1) /* Bus State bit 1 mask. */ -#define TWI_MASTER_BUSSTATE1_bp 1 /* Bus State bit 1 position. */ - -/* TWI_SLAVE.CTRLA bit masks and bit positions */ -#define TWI_SLAVE_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ -#define TWI_SLAVE_INTLVL_gp 6 /* Interrupt Level group position. */ -#define TWI_SLAVE_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ -#define TWI_SLAVE_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ -#define TWI_SLAVE_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ -#define TWI_SLAVE_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ - -#define TWI_SLAVE_DIEN_bm 0x20 /* Data Interrupt Enable bit mask. */ -#define TWI_SLAVE_DIEN_bp 5 /* Data Interrupt Enable bit position. */ - -#define TWI_SLAVE_APIEN_bm 0x10 /* Address/Stop Interrupt Enable bit mask. */ -#define TWI_SLAVE_APIEN_bp 4 /* Address/Stop Interrupt Enable bit position. */ - -#define TWI_SLAVE_ENABLE_bm 0x08 /* Enable TWI Slave bit mask. */ -#define TWI_SLAVE_ENABLE_bp 3 /* Enable TWI Slave bit position. */ - -#define TWI_SLAVE_PIEN_bm 0x04 /* Stop Interrupt Enable bit mask. */ -#define TWI_SLAVE_PIEN_bp 2 /* Stop Interrupt Enable bit position. */ - -#define TWI_SLAVE_PMEN_bm 0x02 /* Promiscuous Mode Enable bit mask. */ -#define TWI_SLAVE_PMEN_bp 1 /* Promiscuous Mode Enable bit position. */ - -#define TWI_SLAVE_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ -#define TWI_SLAVE_SMEN_bp 0 /* Smart Mode Enable bit position. */ - -/* TWI_SLAVE.CTRLB bit masks and bit positions */ -#define TWI_SLAVE_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ -#define TWI_SLAVE_ACKACT_bp 2 /* Acknowledge Action bit position. */ - -#define TWI_SLAVE_CMD_gm 0x03 /* Command group mask. */ -#define TWI_SLAVE_CMD_gp 0 /* Command group position. */ -#define TWI_SLAVE_CMD0_bm (1<<0) /* Command bit 0 mask. */ -#define TWI_SLAVE_CMD0_bp 0 /* Command bit 0 position. */ -#define TWI_SLAVE_CMD1_bm (1<<1) /* Command bit 1 mask. */ -#define TWI_SLAVE_CMD1_bp 1 /* Command bit 1 position. */ - -/* TWI_SLAVE.STATUS bit masks and bit positions */ -#define TWI_SLAVE_DIF_bm 0x80 /* Data Interrupt Flag bit mask. */ -#define TWI_SLAVE_DIF_bp 7 /* Data Interrupt Flag bit position. */ - -#define TWI_SLAVE_APIF_bm 0x40 /* Address/Stop Interrupt Flag bit mask. */ -#define TWI_SLAVE_APIF_bp 6 /* Address/Stop Interrupt Flag bit position. */ - -#define TWI_SLAVE_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ -#define TWI_SLAVE_CLKHOLD_bp 5 /* Clock Hold bit position. */ - -#define TWI_SLAVE_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ -#define TWI_SLAVE_RXACK_bp 4 /* Received Acknowledge bit position. */ - -#define TWI_SLAVE_COLL_bm 0x08 /* Collision bit mask. */ -#define TWI_SLAVE_COLL_bp 3 /* Collision bit position. */ - -#define TWI_SLAVE_BUSERR_bm 0x04 /* Bus Error bit mask. */ -#define TWI_SLAVE_BUSERR_bp 2 /* Bus Error bit position. */ - -#define TWI_SLAVE_DIR_bm 0x02 /* Read/Write Direction bit mask. */ -#define TWI_SLAVE_DIR_bp 1 /* Read/Write Direction bit position. */ - -#define TWI_SLAVE_AP_bm 0x01 /* Slave Address or Stop bit mask. */ -#define TWI_SLAVE_AP_bp 0 /* Slave Address or Stop bit position. */ - -/* TWI_SLAVE.ADDRMASK bit masks and bit positions */ -#define TWI_SLAVE_ADDRMASK_gm 0xFE /* Address Mask group mask. */ -#define TWI_SLAVE_ADDRMASK_gp 1 /* Address Mask group position. */ -#define TWI_SLAVE_ADDRMASK0_bm (1<<1) /* Address Mask bit 0 mask. */ -#define TWI_SLAVE_ADDRMASK0_bp 1 /* Address Mask bit 0 position. */ -#define TWI_SLAVE_ADDRMASK1_bm (1<<2) /* Address Mask bit 1 mask. */ -#define TWI_SLAVE_ADDRMASK1_bp 2 /* Address Mask bit 1 position. */ -#define TWI_SLAVE_ADDRMASK2_bm (1<<3) /* Address Mask bit 2 mask. */ -#define TWI_SLAVE_ADDRMASK2_bp 3 /* Address Mask bit 2 position. */ -#define TWI_SLAVE_ADDRMASK3_bm (1<<4) /* Address Mask bit 3 mask. */ -#define TWI_SLAVE_ADDRMASK3_bp 4 /* Address Mask bit 3 position. */ -#define TWI_SLAVE_ADDRMASK4_bm (1<<5) /* Address Mask bit 4 mask. */ -#define TWI_SLAVE_ADDRMASK4_bp 5 /* Address Mask bit 4 position. */ -#define TWI_SLAVE_ADDRMASK5_bm (1<<6) /* Address Mask bit 5 mask. */ -#define TWI_SLAVE_ADDRMASK5_bp 6 /* Address Mask bit 5 position. */ -#define TWI_SLAVE_ADDRMASK6_bm (1<<7) /* Address Mask bit 6 mask. */ -#define TWI_SLAVE_ADDRMASK6_bp 7 /* Address Mask bit 6 position. */ - -#define TWI_SLAVE_ADDREN_bm 0x01 /* Address Enable bit mask. */ -#define TWI_SLAVE_ADDREN_bp 0 /* Address Enable bit position. */ - -/* TWI.CTRL bit masks and bit positions */ -#define TWI_SDAHOLD_gm 0x06 /* SDA Hold Time Enable group mask. */ -#define TWI_SDAHOLD_gp 1 /* SDA Hold Time Enable group position. */ -#define TWI_SDAHOLD0_bm (1<<1) /* SDA Hold Time Enable bit 0 mask. */ -#define TWI_SDAHOLD0_bp 1 /* SDA Hold Time Enable bit 0 position. */ -#define TWI_SDAHOLD1_bm (1<<2) /* SDA Hold Time Enable bit 1 mask. */ -#define TWI_SDAHOLD1_bp 2 /* SDA Hold Time Enable bit 1 position. */ - -#define TWI_EDIEN_bm 0x01 /* External Driver Interface Enable bit mask. */ -#define TWI_EDIEN_bp 0 /* External Driver Interface Enable bit position. */ - -/* USB - USB */ -/* USB_EP.STATUS bit masks and bit positions */ -#define USB_EP_STALLF_bm 0x80 /* Endpoint Stall Flag bit mask. */ -#define USB_EP_STALLF_bp 7 /* Endpoint Stall Flag bit position. */ - -#define USB_EP_CRC_bm 0x80 /* CRC Error Flag bit mask. */ -#define USB_EP_CRC_bp 7 /* CRC Error Flag bit position. */ - -#define USB_EP_UNF_bm 0x40 /* Underflow Enpoint FLag bit mask. */ -#define USB_EP_UNF_bp 6 /* Underflow Enpoint FLag bit position. */ - -#define USB_EP_OVF_bm 0x40 /* Overflow Enpoint Flag for Output Endpoints bit mask. */ -#define USB_EP_OVF_bp 6 /* Overflow Enpoint Flag for Output Endpoints bit position. */ - -#define USB_EP_TRNCOMPL0_bm 0x20 /* Transaction Complete 0 Flag bit mask. */ -#define USB_EP_TRNCOMPL0_bp 5 /* Transaction Complete 0 Flag bit position. */ - -#define USB_EP_TRNCOMPL1_bm 0x10 /* Transaction Complete 1 Flag bit mask. */ -#define USB_EP_TRNCOMPL1_bp 4 /* Transaction Complete 1 Flag bit position. */ - -#define USB_EP_SETUP_bm 0x10 /* SETUP Transaction Complete Flag bit mask. */ -#define USB_EP_SETUP_bp 4 /* SETUP Transaction Complete Flag bit position. */ - -#define USB_EP_BANK_bm 0x08 /* Bank Select bit mask. */ -#define USB_EP_BANK_bp 3 /* Bank Select bit position. */ - -#define USB_EP_BUSNACK1_bm 0x04 /* Data Buffer 1 Not Acknowledge bit mask. */ -#define USB_EP_BUSNACK1_bp 2 /* Data Buffer 1 Not Acknowledge bit position. */ - -#define USB_EP_BUSNACK0_bm 0x02 /* Data Buffer 0 Not Acknowledge bit mask. */ -#define USB_EP_BUSNACK0_bp 1 /* Data Buffer 0 Not Acknowledge bit position. */ - -#define USB_EP_TOGGLE_bm 0x01 /* Data Toggle bit mask. */ -#define USB_EP_TOGGLE_bp 0 /* Data Toggle bit position. */ - -/* USB_EP.CTRL bit masks and bit positions */ -#define USB_EP_TYPE_gm 0xC0 /* Endpoint Type group mask. */ -#define USB_EP_TYPE_gp 6 /* Endpoint Type group position. */ -#define USB_EP_TYPE0_bm (1<<6) /* Endpoint Type bit 0 mask. */ -#define USB_EP_TYPE0_bp 6 /* Endpoint Type bit 0 position. */ -#define USB_EP_TYPE1_bm (1<<7) /* Endpoint Type bit 1 mask. */ -#define USB_EP_TYPE1_bp 7 /* Endpoint Type bit 1 position. */ - -#define USB_EP_MULTIPKT_bm 0x20 /* Multi Packet Transfer Enable bit mask. */ -#define USB_EP_MULTIPKT_bp 5 /* Multi Packet Transfer Enable bit position. */ - -#define USB_EP_PINGPONG_bm 0x10 /* Ping-Pong Enable bit mask. */ -#define USB_EP_PINGPONG_bp 4 /* Ping-Pong Enable bit position. */ - -#define USB_EP_INTDSBL_bm 0x08 /* Interrupt Disable bit mask. */ -#define USB_EP_INTDSBL_bp 3 /* Interrupt Disable bit position. */ - -#define USB_EP_STALL_bm 0x04 /* Data Stall bit mask. */ -#define USB_EP_STALL_bp 2 /* Data Stall bit position. */ - -#define USB_EP_BUFSIZE_gm 0x07 /* Data Buffer Size group mask. */ -#define USB_EP_BUFSIZE_gp 0 /* Data Buffer Size group position. */ -#define USB_EP_BUFSIZE0_bm (1<<0) /* Data Buffer Size bit 0 mask. */ -#define USB_EP_BUFSIZE0_bp 0 /* Data Buffer Size bit 0 position. */ -#define USB_EP_BUFSIZE1_bm (1<<1) /* Data Buffer Size bit 1 mask. */ -#define USB_EP_BUFSIZE1_bp 1 /* Data Buffer Size bit 1 position. */ -#define USB_EP_BUFSIZE2_bm (1<<2) /* Data Buffer Size bit 2 mask. */ -#define USB_EP_BUFSIZE2_bp 2 /* Data Buffer Size bit 2 position. */ - -/* USB_EP.CNT bit masks and bit positions */ -#define USB_EP_ZLP_bm 0x8000 /* Zero Length Packet bit mask. */ -#define USB_EP_ZLP_bp 15 /* Zero Length Packet bit position. */ - -/* USB.CTRLA bit masks and bit positions */ -#define USB_ENABLE_bm 0x80 /* USB Enable bit mask. */ -#define USB_ENABLE_bp 7 /* USB Enable bit position. */ - -#define USB_SPEED_bm 0x40 /* Speed Select bit mask. */ -#define USB_SPEED_bp 6 /* Speed Select bit position. */ - -#define USB_FIFOEN_bm 0x20 /* USB FIFO Enable bit mask. */ -#define USB_FIFOEN_bp 5 /* USB FIFO Enable bit position. */ - -#define USB_STFRNUM_bm 0x10 /* Store Frame Number Enable bit mask. */ -#define USB_STFRNUM_bp 4 /* Store Frame Number Enable bit position. */ - -#define USB_MAXEP_gm 0x0F /* Maximum Endpoint Addresses group mask. */ -#define USB_MAXEP_gp 0 /* Maximum Endpoint Addresses group position. */ -#define USB_MAXEP0_bm (1<<0) /* Maximum Endpoint Addresses bit 0 mask. */ -#define USB_MAXEP0_bp 0 /* Maximum Endpoint Addresses bit 0 position. */ -#define USB_MAXEP1_bm (1<<1) /* Maximum Endpoint Addresses bit 1 mask. */ -#define USB_MAXEP1_bp 1 /* Maximum Endpoint Addresses bit 1 position. */ -#define USB_MAXEP2_bm (1<<2) /* Maximum Endpoint Addresses bit 2 mask. */ -#define USB_MAXEP2_bp 2 /* Maximum Endpoint Addresses bit 2 position. */ -#define USB_MAXEP3_bm (1<<3) /* Maximum Endpoint Addresses bit 3 mask. */ -#define USB_MAXEP3_bp 3 /* Maximum Endpoint Addresses bit 3 position. */ - -/* USB.CTRLB bit masks and bit positions */ -#define USB_PULLRST_bm 0x10 /* Pull during Reset bit mask. */ -#define USB_PULLRST_bp 4 /* Pull during Reset bit position. */ - -#define USB_RWAKEUP_bm 0x04 /* Remote Wake-up bit mask. */ -#define USB_RWAKEUP_bp 2 /* Remote Wake-up bit position. */ - -#define USB_GNACK_bm 0x02 /* Global NACK bit mask. */ -#define USB_GNACK_bp 1 /* Global NACK bit position. */ - -#define USB_ATTACH_bm 0x01 /* Attach bit mask. */ -#define USB_ATTACH_bp 0 /* Attach bit position. */ - -/* USB.STATUS bit masks and bit positions */ -#define USB_URESUME_bm 0x08 /* Upstream Resume bit mask. */ -#define USB_URESUME_bp 3 /* Upstream Resume bit position. */ - -#define USB_RESUME_bm 0x04 /* Resume bit mask. */ -#define USB_RESUME_bp 2 /* Resume bit position. */ - -#define USB_SUSPEND_bm 0x02 /* Bus Suspended bit mask. */ -#define USB_SUSPEND_bp 1 /* Bus Suspended bit position. */ - -#define USB_BUSRST_bm 0x01 /* Bus Reset bit mask. */ -#define USB_BUSRST_bp 0 /* Bus Reset bit position. */ - -/* USB.ADDR bit masks and bit positions */ -#define USB_ADDR_gm 0x7F /* Device Address group mask. */ -#define USB_ADDR_gp 0 /* Device Address group position. */ -#define USB_ADDR0_bm (1<<0) /* Device Address bit 0 mask. */ -#define USB_ADDR0_bp 0 /* Device Address bit 0 position. */ -#define USB_ADDR1_bm (1<<1) /* Device Address bit 1 mask. */ -#define USB_ADDR1_bp 1 /* Device Address bit 1 position. */ -#define USB_ADDR2_bm (1<<2) /* Device Address bit 2 mask. */ -#define USB_ADDR2_bp 2 /* Device Address bit 2 position. */ -#define USB_ADDR3_bm (1<<3) /* Device Address bit 3 mask. */ -#define USB_ADDR3_bp 3 /* Device Address bit 3 position. */ -#define USB_ADDR4_bm (1<<4) /* Device Address bit 4 mask. */ -#define USB_ADDR4_bp 4 /* Device Address bit 4 position. */ -#define USB_ADDR5_bm (1<<5) /* Device Address bit 5 mask. */ -#define USB_ADDR5_bp 5 /* Device Address bit 5 position. */ -#define USB_ADDR6_bm (1<<6) /* Device Address bit 6 mask. */ -#define USB_ADDR6_bp 6 /* Device Address bit 6 position. */ - -/* USB.FIFOWP bit masks and bit positions */ -#define USB_FIFOWP_gm 0x1F /* FIFO Write Pointer group mask. */ -#define USB_FIFOWP_gp 0 /* FIFO Write Pointer group position. */ -#define USB_FIFOWP0_bm (1<<0) /* FIFO Write Pointer bit 0 mask. */ -#define USB_FIFOWP0_bp 0 /* FIFO Write Pointer bit 0 position. */ -#define USB_FIFOWP1_bm (1<<1) /* FIFO Write Pointer bit 1 mask. */ -#define USB_FIFOWP1_bp 1 /* FIFO Write Pointer bit 1 position. */ -#define USB_FIFOWP2_bm (1<<2) /* FIFO Write Pointer bit 2 mask. */ -#define USB_FIFOWP2_bp 2 /* FIFO Write Pointer bit 2 position. */ -#define USB_FIFOWP3_bm (1<<3) /* FIFO Write Pointer bit 3 mask. */ -#define USB_FIFOWP3_bp 3 /* FIFO Write Pointer bit 3 position. */ -#define USB_FIFOWP4_bm (1<<4) /* FIFO Write Pointer bit 4 mask. */ -#define USB_FIFOWP4_bp 4 /* FIFO Write Pointer bit 4 position. */ - -/* USB.FIFORP bit masks and bit positions */ -#define USB_FIFORP_gm 0x1F /* FIFO Read Pointer group mask. */ -#define USB_FIFORP_gp 0 /* FIFO Read Pointer group position. */ -#define USB_FIFORP0_bm (1<<0) /* FIFO Read Pointer bit 0 mask. */ -#define USB_FIFORP0_bp 0 /* FIFO Read Pointer bit 0 position. */ -#define USB_FIFORP1_bm (1<<1) /* FIFO Read Pointer bit 1 mask. */ -#define USB_FIFORP1_bp 1 /* FIFO Read Pointer bit 1 position. */ -#define USB_FIFORP2_bm (1<<2) /* FIFO Read Pointer bit 2 mask. */ -#define USB_FIFORP2_bp 2 /* FIFO Read Pointer bit 2 position. */ -#define USB_FIFORP3_bm (1<<3) /* FIFO Read Pointer bit 3 mask. */ -#define USB_FIFORP3_bp 3 /* FIFO Read Pointer bit 3 position. */ -#define USB_FIFORP4_bm (1<<4) /* FIFO Read Pointer bit 4 mask. */ -#define USB_FIFORP4_bp 4 /* FIFO Read Pointer bit 4 position. */ - -/* USB.INTCTRLA bit masks and bit positions */ -#define USB_SOFIE_bm 0x80 /* Start Of Frame Interrupt Enable bit mask. */ -#define USB_SOFIE_bp 7 /* Start Of Frame Interrupt Enable bit position. */ - -#define USB_BUSEVIE_bm 0x40 /* Bus Event Interrupt Enable bit mask. */ -#define USB_BUSEVIE_bp 6 /* Bus Event Interrupt Enable bit position. */ - -#define USB_BUSERRIE_bm 0x20 /* Bus Error Interrupt Enable bit mask. */ -#define USB_BUSERRIE_bp 5 /* Bus Error Interrupt Enable bit position. */ - -#define USB_STALLIE_bm 0x10 /* STALL Interrupt Enable bit mask. */ -#define USB_STALLIE_bp 4 /* STALL Interrupt Enable bit position. */ - -#define USB_INTLVL_gm 0x03 /* Interrupt Level group mask. */ -#define USB_INTLVL_gp 0 /* Interrupt Level group position. */ -#define USB_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */ -#define USB_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */ -#define USB_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ -#define USB_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */ - -/* USB.INTCTRLB bit masks and bit positions */ -#define USB_TRNIE_bm 0x02 /* Transaction Complete Interrupt Enable bit mask. */ -#define USB_TRNIE_bp 1 /* Transaction Complete Interrupt Enable bit position. */ - -#define USB_SETUPIE_bm 0x01 /* SETUP Transaction Complete Interrupt Enable bit mask. */ -#define USB_SETUPIE_bp 0 /* SETUP Transaction Complete Interrupt Enable bit position. */ - -/* USB.INTFLAGSACLR bit masks and bit positions */ -#define USB_SOFIF_bm 0x80 /* Start Of Frame Interrupt Flag bit mask. */ -#define USB_SOFIF_bp 7 /* Start Of Frame Interrupt Flag bit position. */ - -#define USB_SUSPENDIF_bm 0x40 /* Suspend Interrupt Flag bit mask. */ -#define USB_SUSPENDIF_bp 6 /* Suspend Interrupt Flag bit position. */ - -#define USB_RESUMEIF_bm 0x20 /* Resume Interrupt Flag bit mask. */ -#define USB_RESUMEIF_bp 5 /* Resume Interrupt Flag bit position. */ - -#define USB_RSTIF_bm 0x10 /* Reset Interrupt Flag bit mask. */ -#define USB_RSTIF_bp 4 /* Reset Interrupt Flag bit position. */ - -#define USB_CRCIF_bm 0x08 /* Isochronous CRC Error Interrupt Flag bit mask. */ -#define USB_CRCIF_bp 3 /* Isochronous CRC Error Interrupt Flag bit position. */ - -#define USB_UNFIF_bm 0x04 /* Underflow Interrupt Flag bit mask. */ -#define USB_UNFIF_bp 2 /* Underflow Interrupt Flag bit position. */ - -#define USB_OVFIF_bm 0x02 /* Overflow Interrupt Flag bit mask. */ -#define USB_OVFIF_bp 1 /* Overflow Interrupt Flag bit position. */ - -#define USB_STALLIF_bm 0x01 /* STALL Interrupt Flag bit mask. */ -#define USB_STALLIF_bp 0 /* STALL Interrupt Flag bit position. */ - -/* USB.INTFLAGSASET bit masks and bit positions */ -/* USB_SOFIF Predefined. */ -/* USB_SOFIF Predefined. */ - -/* USB_SUSPENDIF Predefined. */ -/* USB_SUSPENDIF Predefined. */ - -/* USB_RESUMEIF Predefined. */ -/* USB_RESUMEIF Predefined. */ - -/* USB_RSTIF Predefined. */ -/* USB_RSTIF Predefined. */ - -/* USB_CRCIF Predefined. */ -/* USB_CRCIF Predefined. */ - -/* USB_UNFIF Predefined. */ -/* USB_UNFIF Predefined. */ - -/* USB_OVFIF Predefined. */ -/* USB_OVFIF Predefined. */ - -/* USB_STALLIF Predefined. */ -/* USB_STALLIF Predefined. */ - -/* USB.INTFLAGSBCLR bit masks and bit positions */ -#define USB_TRNIF_bm 0x02 /* Transaction Complete Interrupt Flag bit mask. */ -#define USB_TRNIF_bp 1 /* Transaction Complete Interrupt Flag bit position. */ - -#define USB_SETUPIF_bm 0x01 /* SETUP Transaction Complete Interrupt Flag bit mask. */ -#define USB_SETUPIF_bp 0 /* SETUP Transaction Complete Interrupt Flag bit position. */ - -/* USB.INTFLAGSBSET bit masks and bit positions */ -/* USB_TRNIF Predefined. */ -/* USB_TRNIF Predefined. */ - -/* USB_SETUPIF Predefined. */ -/* USB_SETUPIF Predefined. */ - -/* PORT - I/O Port Configuration */ -/* PORT.INTCTRL bit masks and bit positions */ -#define PORT_INT1LVL_gm 0x0C /* Port Interrupt 1 Level group mask. */ -#define PORT_INT1LVL_gp 2 /* Port Interrupt 1 Level group position. */ -#define PORT_INT1LVL0_bm (1<<2) /* Port Interrupt 1 Level bit 0 mask. */ -#define PORT_INT1LVL0_bp 2 /* Port Interrupt 1 Level bit 0 position. */ -#define PORT_INT1LVL1_bm (1<<3) /* Port Interrupt 1 Level bit 1 mask. */ -#define PORT_INT1LVL1_bp 3 /* Port Interrupt 1 Level bit 1 position. */ - -#define PORT_INT0LVL_gm 0x03 /* Port Interrupt 0 Level group mask. */ -#define PORT_INT0LVL_gp 0 /* Port Interrupt 0 Level group position. */ -#define PORT_INT0LVL0_bm (1<<0) /* Port Interrupt 0 Level bit 0 mask. */ -#define PORT_INT0LVL0_bp 0 /* Port Interrupt 0 Level bit 0 position. */ -#define PORT_INT0LVL1_bm (1<<1) /* Port Interrupt 0 Level bit 1 mask. */ -#define PORT_INT0LVL1_bp 1 /* Port Interrupt 0 Level bit 1 position. */ - -/* PORT.INTFLAGS bit masks and bit positions */ -#define PORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ -#define PORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ - -#define PORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ -#define PORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ - -/* PORT.REMAP bit masks and bit positions */ -#define PORT_SPI_bm 0x20 /* SPI bit mask. */ -#define PORT_SPI_bp 5 /* SPI bit position. */ - -#define PORT_USART0_bm 0x10 /* USART0 bit mask. */ -#define PORT_USART0_bp 4 /* USART0 bit position. */ - -#define PORT_TC0D_bm 0x08 /* Timer/Counter 0 Output Compare D bit mask. */ -#define PORT_TC0D_bp 3 /* Timer/Counter 0 Output Compare D bit position. */ - -#define PORT_TC0C_bm 0x04 /* Timer/Counter 0 Output Compare C bit mask. */ -#define PORT_TC0C_bp 2 /* Timer/Counter 0 Output Compare C bit position. */ - -#define PORT_TC0B_bm 0x02 /* Timer/Counter 0 Output Compare B bit mask. */ -#define PORT_TC0B_bp 1 /* Timer/Counter 0 Output Compare B bit position. */ - -#define PORT_TC0A_bm 0x01 /* Timer/Counter 0 Output Compare A bit mask. */ -#define PORT_TC0A_bp 0 /* Timer/Counter 0 Output Compare A bit position. */ - -/* PORT.PIN0CTRL bit masks and bit positions */ -#define PORT_SRLEN_bm 0x80 /* Slew Rate Enable bit mask. */ -#define PORT_SRLEN_bp 7 /* Slew Rate Enable bit position. */ - -#define PORT_INVEN_bm 0x40 /* Inverted I/O Enable bit mask. */ -#define PORT_INVEN_bp 6 /* Inverted I/O Enable bit position. */ - -#define PORT_OPC_gm 0x38 /* Output/Pull Configuration group mask. */ -#define PORT_OPC_gp 3 /* Output/Pull Configuration group position. */ -#define PORT_OPC0_bm (1<<3) /* Output/Pull Configuration bit 0 mask. */ -#define PORT_OPC0_bp 3 /* Output/Pull Configuration bit 0 position. */ -#define PORT_OPC1_bm (1<<4) /* Output/Pull Configuration bit 1 mask. */ -#define PORT_OPC1_bp 4 /* Output/Pull Configuration bit 1 position. */ -#define PORT_OPC2_bm (1<<5) /* Output/Pull Configuration bit 2 mask. */ -#define PORT_OPC2_bp 5 /* Output/Pull Configuration bit 2 position. */ - -#define PORT_ISC_gm 0x07 /* Input/Sense Configuration group mask. */ -#define PORT_ISC_gp 0 /* Input/Sense Configuration group position. */ -#define PORT_ISC0_bm (1<<0) /* Input/Sense Configuration bit 0 mask. */ -#define PORT_ISC0_bp 0 /* Input/Sense Configuration bit 0 position. */ -#define PORT_ISC1_bm (1<<1) /* Input/Sense Configuration bit 1 mask. */ -#define PORT_ISC1_bp 1 /* Input/Sense Configuration bit 1 position. */ -#define PORT_ISC2_bm (1<<2) /* Input/Sense Configuration bit 2 mask. */ -#define PORT_ISC2_bp 2 /* Input/Sense Configuration bit 2 position. */ - -/* PORT.PIN1CTRL bit masks and bit positions */ -/* PORT_SRLEN Predefined. */ -/* PORT_SRLEN Predefined. */ - -/* PORT_INVEN Predefined. */ -/* PORT_INVEN Predefined. */ - -/* PORT_OPC Predefined. */ -/* PORT_OPC Predefined. */ - -/* PORT_ISC Predefined. */ -/* PORT_ISC Predefined. */ - -/* PORT.PIN2CTRL bit masks and bit positions */ -/* PORT_SRLEN Predefined. */ -/* PORT_SRLEN Predefined. */ - -/* PORT_INVEN Predefined. */ -/* PORT_INVEN Predefined. */ - -/* PORT_OPC Predefined. */ -/* PORT_OPC Predefined. */ - -/* PORT_ISC Predefined. */ -/* PORT_ISC Predefined. */ - -/* PORT.PIN3CTRL bit masks and bit positions */ -/* PORT_SRLEN Predefined. */ -/* PORT_SRLEN Predefined. */ - -/* PORT_INVEN Predefined. */ -/* PORT_INVEN Predefined. */ - -/* PORT_OPC Predefined. */ -/* PORT_OPC Predefined. */ - -/* PORT_ISC Predefined. */ -/* PORT_ISC Predefined. */ - -/* PORT.PIN4CTRL bit masks and bit positions */ -/* PORT_SRLEN Predefined. */ -/* PORT_SRLEN Predefined. */ - -/* PORT_INVEN Predefined. */ -/* PORT_INVEN Predefined. */ - -/* PORT_OPC Predefined. */ -/* PORT_OPC Predefined. */ - -/* PORT_ISC Predefined. */ -/* PORT_ISC Predefined. */ - -/* PORT.PIN5CTRL bit masks and bit positions */ -/* PORT_SRLEN Predefined. */ -/* PORT_SRLEN Predefined. */ - -/* PORT_INVEN Predefined. */ -/* PORT_INVEN Predefined. */ - -/* PORT_OPC Predefined. */ -/* PORT_OPC Predefined. */ - -/* PORT_ISC Predefined. */ -/* PORT_ISC Predefined. */ - -/* PORT.PIN6CTRL bit masks and bit positions */ -/* PORT_SRLEN Predefined. */ -/* PORT_SRLEN Predefined. */ - -/* PORT_INVEN Predefined. */ -/* PORT_INVEN Predefined. */ - -/* PORT_OPC Predefined. */ -/* PORT_OPC Predefined. */ - -/* PORT_ISC Predefined. */ -/* PORT_ISC Predefined. */ - -/* PORT.PIN7CTRL bit masks and bit positions */ -/* PORT_SRLEN Predefined. */ -/* PORT_SRLEN Predefined. */ - -/* PORT_INVEN Predefined. */ -/* PORT_INVEN Predefined. */ - -/* PORT_OPC Predefined. */ -/* PORT_OPC Predefined. */ - -/* PORT_ISC Predefined. */ -/* PORT_ISC Predefined. */ - -/* TC - 16-bit Timer/Counter With PWM */ -/* TC0.CTRLA bit masks and bit positions */ -#define TC0_CLKSEL_gm 0x0F /* Clock Selection group mask. */ -#define TC0_CLKSEL_gp 0 /* Clock Selection group position. */ -#define TC0_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ -#define TC0_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ -#define TC0_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ -#define TC0_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ -#define TC0_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ -#define TC0_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ -#define TC0_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ -#define TC0_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ - -/* TC0.CTRLB bit masks and bit positions */ -#define TC0_CCDEN_bm 0x80 /* Compare or Capture D Enable bit mask. */ -#define TC0_CCDEN_bp 7 /* Compare or Capture D Enable bit position. */ - -#define TC0_CCCEN_bm 0x40 /* Compare or Capture C Enable bit mask. */ -#define TC0_CCCEN_bp 6 /* Compare or Capture C Enable bit position. */ - -#define TC0_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ -#define TC0_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ - -#define TC0_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ -#define TC0_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ - -#define TC0_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ -#define TC0_WGMODE_gp 0 /* Waveform generation mode group position. */ -#define TC0_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ -#define TC0_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ -#define TC0_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ -#define TC0_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ -#define TC0_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ -#define TC0_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ - -/* TC0.CTRLC bit masks and bit positions */ -#define TC0_CMPD_bm 0x08 /* Compare D Output Value bit mask. */ -#define TC0_CMPD_bp 3 /* Compare D Output Value bit position. */ - -#define TC0_CMPC_bm 0x04 /* Compare C Output Value bit mask. */ -#define TC0_CMPC_bp 2 /* Compare C Output Value bit position. */ - -#define TC0_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ -#define TC0_CMPB_bp 1 /* Compare B Output Value bit position. */ - -#define TC0_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ -#define TC0_CMPA_bp 0 /* Compare A Output Value bit position. */ - -/* TC0.CTRLD bit masks and bit positions */ -#define TC0_EVACT_gm 0xE0 /* Event Action group mask. */ -#define TC0_EVACT_gp 5 /* Event Action group position. */ -#define TC0_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ -#define TC0_EVACT0_bp 5 /* Event Action bit 0 position. */ -#define TC0_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ -#define TC0_EVACT1_bp 6 /* Event Action bit 1 position. */ -#define TC0_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ -#define TC0_EVACT2_bp 7 /* Event Action bit 2 position. */ - -#define TC0_EVDLY_bm 0x10 /* Event Delay bit mask. */ -#define TC0_EVDLY_bp 4 /* Event Delay bit position. */ - -#define TC0_EVSEL_gm 0x0F /* Event Source Select group mask. */ -#define TC0_EVSEL_gp 0 /* Event Source Select group position. */ -#define TC0_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ -#define TC0_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ -#define TC0_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ -#define TC0_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ -#define TC0_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ -#define TC0_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ -#define TC0_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ -#define TC0_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ - -/* TC0.CTRLE bit masks and bit positions */ -#define TC0_BYTEM_gm 0x03 /* Byte Mode group mask. */ -#define TC0_BYTEM_gp 0 /* Byte Mode group position. */ -#define TC0_BYTEM0_bm (1<<0) /* Byte Mode bit 0 mask. */ -#define TC0_BYTEM0_bp 0 /* Byte Mode bit 0 position. */ -#define TC0_BYTEM1_bm (1<<1) /* Byte Mode bit 1 mask. */ -#define TC0_BYTEM1_bp 1 /* Byte Mode bit 1 position. */ - -/* TC0.INTCTRLA bit masks and bit positions */ -#define TC0_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ -#define TC0_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ -#define TC0_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ -#define TC0_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ -#define TC0_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ -#define TC0_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ - -#define TC0_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ -#define TC0_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ -#define TC0_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ -#define TC0_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ -#define TC0_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ -#define TC0_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ - -/* TC0.INTCTRLB bit masks and bit positions */ -#define TC0_CCDINTLVL_gm 0xC0 /* Compare or Capture D Interrupt Level group mask. */ -#define TC0_CCDINTLVL_gp 6 /* Compare or Capture D Interrupt Level group position. */ -#define TC0_CCDINTLVL0_bm (1<<6) /* Compare or Capture D Interrupt Level bit 0 mask. */ -#define TC0_CCDINTLVL0_bp 6 /* Compare or Capture D Interrupt Level bit 0 position. */ -#define TC0_CCDINTLVL1_bm (1<<7) /* Compare or Capture D Interrupt Level bit 1 mask. */ -#define TC0_CCDINTLVL1_bp 7 /* Compare or Capture D Interrupt Level bit 1 position. */ - -#define TC0_CCCINTLVL_gm 0x30 /* Compare or Capture C Interrupt Level group mask. */ -#define TC0_CCCINTLVL_gp 4 /* Compare or Capture C Interrupt Level group position. */ -#define TC0_CCCINTLVL0_bm (1<<4) /* Compare or Capture C Interrupt Level bit 0 mask. */ -#define TC0_CCCINTLVL0_bp 4 /* Compare or Capture C Interrupt Level bit 0 position. */ -#define TC0_CCCINTLVL1_bm (1<<5) /* Compare or Capture C Interrupt Level bit 1 mask. */ -#define TC0_CCCINTLVL1_bp 5 /* Compare or Capture C Interrupt Level bit 1 position. */ - -#define TC0_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ -#define TC0_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ -#define TC0_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ -#define TC0_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ -#define TC0_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ -#define TC0_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ - -#define TC0_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ -#define TC0_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ -#define TC0_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ -#define TC0_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ -#define TC0_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ -#define TC0_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ - -/* TC0.CTRLFCLR bit masks and bit positions */ -#define TC0_CMD_gm 0x0C /* Command group mask. */ -#define TC0_CMD_gp 2 /* Command group position. */ -#define TC0_CMD0_bm (1<<2) /* Command bit 0 mask. */ -#define TC0_CMD0_bp 2 /* Command bit 0 position. */ -#define TC0_CMD1_bm (1<<3) /* Command bit 1 mask. */ -#define TC0_CMD1_bp 3 /* Command bit 1 position. */ - -#define TC0_LUPD_bm 0x02 /* Lock Update bit mask. */ -#define TC0_LUPD_bp 1 /* Lock Update bit position. */ - -#define TC0_DIR_bm 0x01 /* Direction bit mask. */ -#define TC0_DIR_bp 0 /* Direction bit position. */ - -/* TC0.CTRLFSET bit masks and bit positions */ -/* TC0_CMD Predefined. */ -/* TC0_CMD Predefined. */ - -/* TC0_LUPD Predefined. */ -/* TC0_LUPD Predefined. */ - -/* TC0_DIR Predefined. */ -/* TC0_DIR Predefined. */ - -/* TC0.CTRLGCLR bit masks and bit positions */ -#define TC0_CCDBV_bm 0x10 /* Compare or Capture D Buffer Valid bit mask. */ -#define TC0_CCDBV_bp 4 /* Compare or Capture D Buffer Valid bit position. */ - -#define TC0_CCCBV_bm 0x08 /* Compare or Capture C Buffer Valid bit mask. */ -#define TC0_CCCBV_bp 3 /* Compare or Capture C Buffer Valid bit position. */ - -#define TC0_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ -#define TC0_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ - -#define TC0_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ -#define TC0_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ - -#define TC0_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ -#define TC0_PERBV_bp 0 /* Period Buffer Valid bit position. */ - -/* TC0.CTRLGSET bit masks and bit positions */ -/* TC0_CCDBV Predefined. */ -/* TC0_CCDBV Predefined. */ - -/* TC0_CCCBV Predefined. */ -/* TC0_CCCBV Predefined. */ - -/* TC0_CCBBV Predefined. */ -/* TC0_CCBBV Predefined. */ - -/* TC0_CCABV Predefined. */ -/* TC0_CCABV Predefined. */ - -/* TC0_PERBV Predefined. */ -/* TC0_PERBV Predefined. */ - -/* TC0.INTFLAGS bit masks and bit positions */ -#define TC0_CCDIF_bm 0x80 /* Compare or Capture D Interrupt Flag bit mask. */ -#define TC0_CCDIF_bp 7 /* Compare or Capture D Interrupt Flag bit position. */ - -#define TC0_CCCIF_bm 0x40 /* Compare or Capture C Interrupt Flag bit mask. */ -#define TC0_CCCIF_bp 6 /* Compare or Capture C Interrupt Flag bit position. */ - -#define TC0_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ -#define TC0_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ - -#define TC0_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ -#define TC0_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ - -#define TC0_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ -#define TC0_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ - -#define TC0_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ -#define TC0_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ - -/* TC1.CTRLA bit masks and bit positions */ -#define TC1_CLKSEL_gm 0x0F /* Clock Selection group mask. */ -#define TC1_CLKSEL_gp 0 /* Clock Selection group position. */ -#define TC1_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ -#define TC1_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ -#define TC1_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ -#define TC1_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ -#define TC1_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ -#define TC1_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ -#define TC1_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ -#define TC1_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ - -/* TC1.CTRLB bit masks and bit positions */ -#define TC1_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ -#define TC1_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ - -#define TC1_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ -#define TC1_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ - -#define TC1_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ -#define TC1_WGMODE_gp 0 /* Waveform generation mode group position. */ -#define TC1_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ -#define TC1_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ -#define TC1_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ -#define TC1_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ -#define TC1_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ -#define TC1_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ - -/* TC1.CTRLC bit masks and bit positions */ -#define TC1_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ -#define TC1_CMPB_bp 1 /* Compare B Output Value bit position. */ - -#define TC1_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ -#define TC1_CMPA_bp 0 /* Compare A Output Value bit position. */ - -/* TC1.CTRLD bit masks and bit positions */ -#define TC1_EVACT_gm 0xE0 /* Event Action group mask. */ -#define TC1_EVACT_gp 5 /* Event Action group position. */ -#define TC1_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ -#define TC1_EVACT0_bp 5 /* Event Action bit 0 position. */ -#define TC1_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ -#define TC1_EVACT1_bp 6 /* Event Action bit 1 position. */ -#define TC1_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ -#define TC1_EVACT2_bp 7 /* Event Action bit 2 position. */ - -#define TC1_EVDLY_bm 0x10 /* Event Delay bit mask. */ -#define TC1_EVDLY_bp 4 /* Event Delay bit position. */ - -#define TC1_EVSEL_gm 0x0F /* Event Source Select group mask. */ -#define TC1_EVSEL_gp 0 /* Event Source Select group position. */ -#define TC1_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ -#define TC1_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ -#define TC1_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ -#define TC1_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ -#define TC1_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ -#define TC1_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ -#define TC1_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ -#define TC1_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ - -/* TC1.CTRLE bit masks and bit positions */ -#define TC1_BYTEM_bm 0x01 /* Byte Mode bit mask. */ -#define TC1_BYTEM_bp 0 /* Byte Mode bit position. */ - -/* TC1.INTCTRLA bit masks and bit positions */ -#define TC1_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ -#define TC1_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ -#define TC1_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ -#define TC1_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ -#define TC1_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ -#define TC1_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ - -#define TC1_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ -#define TC1_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ -#define TC1_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ -#define TC1_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ -#define TC1_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ -#define TC1_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ - -/* TC1.INTCTRLB bit masks and bit positions */ -#define TC1_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ -#define TC1_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ -#define TC1_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ -#define TC1_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ -#define TC1_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ -#define TC1_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ - -#define TC1_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ -#define TC1_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ -#define TC1_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ -#define TC1_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ -#define TC1_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ -#define TC1_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ - -/* TC1.CTRLFCLR bit masks and bit positions */ -#define TC1_CMD_gm 0x0C /* Command group mask. */ -#define TC1_CMD_gp 2 /* Command group position. */ -#define TC1_CMD0_bm (1<<2) /* Command bit 0 mask. */ -#define TC1_CMD0_bp 2 /* Command bit 0 position. */ -#define TC1_CMD1_bm (1<<3) /* Command bit 1 mask. */ -#define TC1_CMD1_bp 3 /* Command bit 1 position. */ - -#define TC1_LUPD_bm 0x02 /* Lock Update bit mask. */ -#define TC1_LUPD_bp 1 /* Lock Update bit position. */ - -#define TC1_DIR_bm 0x01 /* Direction bit mask. */ -#define TC1_DIR_bp 0 /* Direction bit position. */ - -/* TC1.CTRLFSET bit masks and bit positions */ -/* TC1_CMD Predefined. */ -/* TC1_CMD Predefined. */ - -/* TC1_LUPD Predefined. */ -/* TC1_LUPD Predefined. */ - -/* TC1_DIR Predefined. */ -/* TC1_DIR Predefined. */ - -/* TC1.CTRLGCLR bit masks and bit positions */ -#define TC1_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ -#define TC1_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ - -#define TC1_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ -#define TC1_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ - -#define TC1_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ -#define TC1_PERBV_bp 0 /* Period Buffer Valid bit position. */ - -/* TC1.CTRLGSET bit masks and bit positions */ -/* TC1_CCBBV Predefined. */ -/* TC1_CCBBV Predefined. */ - -/* TC1_CCABV Predefined. */ -/* TC1_CCABV Predefined. */ - -/* TC1_PERBV Predefined. */ -/* TC1_PERBV Predefined. */ - -/* TC1.INTFLAGS bit masks and bit positions */ -#define TC1_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ -#define TC1_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ - -#define TC1_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ -#define TC1_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ - -#define TC1_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ -#define TC1_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ - -#define TC1_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ -#define TC1_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ - -/* TC2 - 16-bit Timer/Counter type 2 */ -/* TC2.CTRLA bit masks and bit positions */ -#define TC2_CLKSEL_gm 0x0F /* Clock Selection group mask. */ -#define TC2_CLKSEL_gp 0 /* Clock Selection group position. */ -#define TC2_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ -#define TC2_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ -#define TC2_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ -#define TC2_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ -#define TC2_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ -#define TC2_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ -#define TC2_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ -#define TC2_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ - -/* TC2.CTRLB bit masks and bit positions */ -#define TC2_HCMPDEN_bm 0x80 /* High Byte Compare D Enable bit mask. */ -#define TC2_HCMPDEN_bp 7 /* High Byte Compare D Enable bit position. */ - -#define TC2_HCMPCEN_bm 0x40 /* High Byte Compare C Enable bit mask. */ -#define TC2_HCMPCEN_bp 6 /* High Byte Compare C Enable bit position. */ - -#define TC2_HCMPBEN_bm 0x20 /* High Byte Compare B Enable bit mask. */ -#define TC2_HCMPBEN_bp 5 /* High Byte Compare B Enable bit position. */ - -#define TC2_HCMPAEN_bm 0x10 /* High Byte Compare A Enable bit mask. */ -#define TC2_HCMPAEN_bp 4 /* High Byte Compare A Enable bit position. */ - -#define TC2_LCMPDEN_bm 0x08 /* Low Byte Compare D Enable bit mask. */ -#define TC2_LCMPDEN_bp 3 /* Low Byte Compare D Enable bit position. */ - -#define TC2_LCMPCEN_bm 0x04 /* Low Byte Compare C Enable bit mask. */ -#define TC2_LCMPCEN_bp 2 /* Low Byte Compare C Enable bit position. */ - -#define TC2_LCMPBEN_bm 0x02 /* Low Byte Compare B Enable bit mask. */ -#define TC2_LCMPBEN_bp 1 /* Low Byte Compare B Enable bit position. */ - -#define TC2_LCMPAEN_bm 0x01 /* Low Byte Compare A Enable bit mask. */ -#define TC2_LCMPAEN_bp 0 /* Low Byte Compare A Enable bit position. */ - -/* TC2.CTRLC bit masks and bit positions */ -#define TC2_HCMPD_bm 0x80 /* High Byte Compare D Output Value bit mask. */ -#define TC2_HCMPD_bp 7 /* High Byte Compare D Output Value bit position. */ - -#define TC2_HCMPC_bm 0x40 /* High Byte Compare C Output Value bit mask. */ -#define TC2_HCMPC_bp 6 /* High Byte Compare C Output Value bit position. */ - -#define TC2_HCMPB_bm 0x20 /* High Byte Compare B Output Value bit mask. */ -#define TC2_HCMPB_bp 5 /* High Byte Compare B Output Value bit position. */ - -#define TC2_HCMPA_bm 0x10 /* High Byte Compare A Output Value bit mask. */ -#define TC2_HCMPA_bp 4 /* High Byte Compare A Output Value bit position. */ - -#define TC2_LCMPD_bm 0x08 /* Low Byte Compare D Output Value bit mask. */ -#define TC2_LCMPD_bp 3 /* Low Byte Compare D Output Value bit position. */ - -#define TC2_LCMPC_bm 0x04 /* Low Byte Compare C Output Value bit mask. */ -#define TC2_LCMPC_bp 2 /* Low Byte Compare C Output Value bit position. */ - -#define TC2_LCMPB_bm 0x02 /* Low Byte Compare B Output Value bit mask. */ -#define TC2_LCMPB_bp 1 /* Low Byte Compare B Output Value bit position. */ - -#define TC2_LCMPA_bm 0x01 /* Low Byte Compare A Output Value bit mask. */ -#define TC2_LCMPA_bp 0 /* Low Byte Compare A Output Value bit position. */ - -/* TC2.CTRLE bit masks and bit positions */ -#define TC2_BYTEM_gm 0x03 /* Byte Mode group mask. */ -#define TC2_BYTEM_gp 0 /* Byte Mode group position. */ -#define TC2_BYTEM0_bm (1<<0) /* Byte Mode bit 0 mask. */ -#define TC2_BYTEM0_bp 0 /* Byte Mode bit 0 position. */ -#define TC2_BYTEM1_bm (1<<1) /* Byte Mode bit 1 mask. */ -#define TC2_BYTEM1_bp 1 /* Byte Mode bit 1 position. */ - -/* TC2.INTCTRLA bit masks and bit positions */ -#define TC2_HUNFINTLVL_gm 0x0C /* High Byte Underflow Interrupt Level group mask. */ -#define TC2_HUNFINTLVL_gp 2 /* High Byte Underflow Interrupt Level group position. */ -#define TC2_HUNFINTLVL0_bm (1<<2) /* High Byte Underflow Interrupt Level bit 0 mask. */ -#define TC2_HUNFINTLVL0_bp 2 /* High Byte Underflow Interrupt Level bit 0 position. */ -#define TC2_HUNFINTLVL1_bm (1<<3) /* High Byte Underflow Interrupt Level bit 1 mask. */ -#define TC2_HUNFINTLVL1_bp 3 /* High Byte Underflow Interrupt Level bit 1 position. */ - -#define TC2_LUNFINTLVL_gm 0x03 /* Low Byte Underflow interrupt level group mask. */ -#define TC2_LUNFINTLVL_gp 0 /* Low Byte Underflow interrupt level group position. */ -#define TC2_LUNFINTLVL0_bm (1<<0) /* Low Byte Underflow interrupt level bit 0 mask. */ -#define TC2_LUNFINTLVL0_bp 0 /* Low Byte Underflow interrupt level bit 0 position. */ -#define TC2_LUNFINTLVL1_bm (1<<1) /* Low Byte Underflow interrupt level bit 1 mask. */ -#define TC2_LUNFINTLVL1_bp 1 /* Low Byte Underflow interrupt level bit 1 position. */ - -/* TC2.INTCTRLB bit masks and bit positions */ -#define TC2_LCMPDINTLVL_gm 0xC0 /* Low Byte Compare D Interrupt Level group mask. */ -#define TC2_LCMPDINTLVL_gp 6 /* Low Byte Compare D Interrupt Level group position. */ -#define TC2_LCMPDINTLVL0_bm (1<<6) /* Low Byte Compare D Interrupt Level bit 0 mask. */ -#define TC2_LCMPDINTLVL0_bp 6 /* Low Byte Compare D Interrupt Level bit 0 position. */ -#define TC2_LCMPDINTLVL1_bm (1<<7) /* Low Byte Compare D Interrupt Level bit 1 mask. */ -#define TC2_LCMPDINTLVL1_bp 7 /* Low Byte Compare D Interrupt Level bit 1 position. */ - -#define TC2_LCMPCINTLVL_gm 0x30 /* Low Byte Compare C Interrupt Level group mask. */ -#define TC2_LCMPCINTLVL_gp 4 /* Low Byte Compare C Interrupt Level group position. */ -#define TC2_LCMPCINTLVL0_bm (1<<4) /* Low Byte Compare C Interrupt Level bit 0 mask. */ -#define TC2_LCMPCINTLVL0_bp 4 /* Low Byte Compare C Interrupt Level bit 0 position. */ -#define TC2_LCMPCINTLVL1_bm (1<<5) /* Low Byte Compare C Interrupt Level bit 1 mask. */ -#define TC2_LCMPCINTLVL1_bp 5 /* Low Byte Compare C Interrupt Level bit 1 position. */ - -#define TC2_LCMPBINTLVL_gm 0x0C /* Low Byte Compare B Interrupt Level group mask. */ -#define TC2_LCMPBINTLVL_gp 2 /* Low Byte Compare B Interrupt Level group position. */ -#define TC2_LCMPBINTLVL0_bm (1<<2) /* Low Byte Compare B Interrupt Level bit 0 mask. */ -#define TC2_LCMPBINTLVL0_bp 2 /* Low Byte Compare B Interrupt Level bit 0 position. */ -#define TC2_LCMPBINTLVL1_bm (1<<3) /* Low Byte Compare B Interrupt Level bit 1 mask. */ -#define TC2_LCMPBINTLVL1_bp 3 /* Low Byte Compare B Interrupt Level bit 1 position. */ - -#define TC2_LCMPAINTLVL_gm 0x03 /* Low Byte Compare A Interrupt Level group mask. */ -#define TC2_LCMPAINTLVL_gp 0 /* Low Byte Compare A Interrupt Level group position. */ -#define TC2_LCMPAINTLVL0_bm (1<<0) /* Low Byte Compare A Interrupt Level bit 0 mask. */ -#define TC2_LCMPAINTLVL0_bp 0 /* Low Byte Compare A Interrupt Level bit 0 position. */ -#define TC2_LCMPAINTLVL1_bm (1<<1) /* Low Byte Compare A Interrupt Level bit 1 mask. */ -#define TC2_LCMPAINTLVL1_bp 1 /* Low Byte Compare A Interrupt Level bit 1 position. */ - -/* TC2.CTRLF bit masks and bit positions */ -#define TC2_CMD_gm 0x0C /* Command group mask. */ -#define TC2_CMD_gp 2 /* Command group position. */ -#define TC2_CMD0_bm (1<<2) /* Command bit 0 mask. */ -#define TC2_CMD0_bp 2 /* Command bit 0 position. */ -#define TC2_CMD1_bm (1<<3) /* Command bit 1 mask. */ -#define TC2_CMD1_bp 3 /* Command bit 1 position. */ - -#define TC2_CMDEN_gm 0x03 /* Command Enable group mask. */ -#define TC2_CMDEN_gp 0 /* Command Enable group position. */ -#define TC2_CMDEN0_bm (1<<0) /* Command Enable bit 0 mask. */ -#define TC2_CMDEN0_bp 0 /* Command Enable bit 0 position. */ -#define TC2_CMDEN1_bm (1<<1) /* Command Enable bit 1 mask. */ -#define TC2_CMDEN1_bp 1 /* Command Enable bit 1 position. */ - -/* TC2.INTFLAGS bit masks and bit positions */ -#define TC2_LCMPDIF_bm 0x80 /* Low Byte Compare D Interrupt Flag bit mask. */ -#define TC2_LCMPDIF_bp 7 /* Low Byte Compare D Interrupt Flag bit position. */ - -#define TC2_LCMPCIF_bm 0x40 /* Low Byte Compare C Interrupt Flag bit mask. */ -#define TC2_LCMPCIF_bp 6 /* Low Byte Compare C Interrupt Flag bit position. */ - -#define TC2_LCMPBIF_bm 0x20 /* Low Byte Compare B Interrupt Flag bit mask. */ -#define TC2_LCMPBIF_bp 5 /* Low Byte Compare B Interrupt Flag bit position. */ - -#define TC2_LCMPAIF_bm 0x10 /* Low Byte Compare A Interrupt Flag bit mask. */ -#define TC2_LCMPAIF_bp 4 /* Low Byte Compare A Interrupt Flag bit position. */ - -#define TC2_HUNFIF_bm 0x02 /* High Byte Underflow Interrupt Flag bit mask. */ -#define TC2_HUNFIF_bp 1 /* High Byte Underflow Interrupt Flag bit position. */ - -#define TC2_LUNFIF_bm 0x01 /* Low Byte Underflow Interrupt Flag bit mask. */ -#define TC2_LUNFIF_bp 0 /* Low Byte Underflow Interrupt Flag bit position. */ - -/* AWEX - Timer/Counter Advanced Waveform Extension */ -/* AWEX.CTRL bit masks and bit positions */ -#define AWEX_PGM_bm 0x20 /* Pattern Generation Mode bit mask. */ -#define AWEX_PGM_bp 5 /* Pattern Generation Mode bit position. */ - -#define AWEX_CWCM_bm 0x10 /* Common Waveform Channel Mode bit mask. */ -#define AWEX_CWCM_bp 4 /* Common Waveform Channel Mode bit position. */ - -#define AWEX_DTICCDEN_bm 0x08 /* Dead Time Insertion Compare Channel D Enable bit mask. */ -#define AWEX_DTICCDEN_bp 3 /* Dead Time Insertion Compare Channel D Enable bit position. */ - -#define AWEX_DTICCCEN_bm 0x04 /* Dead Time Insertion Compare Channel C Enable bit mask. */ -#define AWEX_DTICCCEN_bp 2 /* Dead Time Insertion Compare Channel C Enable bit position. */ - -#define AWEX_DTICCBEN_bm 0x02 /* Dead Time Insertion Compare Channel B Enable bit mask. */ -#define AWEX_DTICCBEN_bp 1 /* Dead Time Insertion Compare Channel B Enable bit position. */ - -#define AWEX_DTICCAEN_bm 0x01 /* Dead Time Insertion Compare Channel A Enable bit mask. */ -#define AWEX_DTICCAEN_bp 0 /* Dead Time Insertion Compare Channel A Enable bit position. */ - -/* AWEX.FDCTRL bit masks and bit positions */ -#define AWEX_FDDBD_bm 0x10 /* Fault Detect on Disable Break Disable bit mask. */ -#define AWEX_FDDBD_bp 4 /* Fault Detect on Disable Break Disable bit position. */ - -#define AWEX_FDMODE_bm 0x04 /* Fault Detect Mode bit mask. */ -#define AWEX_FDMODE_bp 2 /* Fault Detect Mode bit position. */ - -#define AWEX_FDACT_gm 0x03 /* Fault Detect Action group mask. */ -#define AWEX_FDACT_gp 0 /* Fault Detect Action group position. */ -#define AWEX_FDACT0_bm (1<<0) /* Fault Detect Action bit 0 mask. */ -#define AWEX_FDACT0_bp 0 /* Fault Detect Action bit 0 position. */ -#define AWEX_FDACT1_bm (1<<1) /* Fault Detect Action bit 1 mask. */ -#define AWEX_FDACT1_bp 1 /* Fault Detect Action bit 1 position. */ - -/* AWEX.STATUS bit masks and bit positions */ -#define AWEX_FDF_bm 0x04 /* Fault Detect Flag bit mask. */ -#define AWEX_FDF_bp 2 /* Fault Detect Flag bit position. */ - -#define AWEX_DTHSBUFV_bm 0x02 /* Dead Time High Side Buffer Valid bit mask. */ -#define AWEX_DTHSBUFV_bp 1 /* Dead Time High Side Buffer Valid bit position. */ - -#define AWEX_DTLSBUFV_bm 0x01 /* Dead Time Low Side Buffer Valid bit mask. */ -#define AWEX_DTLSBUFV_bp 0 /* Dead Time Low Side Buffer Valid bit position. */ - -/* AWEX.STATUSSET bit masks and bit positions */ -/* AWEX_FDF Predefined. */ -/* AWEX_FDF Predefined. */ - -/* AWEX_DTHSBUFV Predefined. */ -/* AWEX_DTHSBUFV Predefined. */ - -/* AWEX_DTLSBUFV Predefined. */ -/* AWEX_DTLSBUFV Predefined. */ - -/* HIRES - Timer/Counter High-Resolution Extension */ -/* HIRES.CTRLA bit masks and bit positions */ -#define HIRES_HREN_gm 0x03 /* High Resolution Enable group mask. */ -#define HIRES_HREN_gp 0 /* High Resolution Enable group position. */ -#define HIRES_HREN0_bm (1<<0) /* High Resolution Enable bit 0 mask. */ -#define HIRES_HREN0_bp 0 /* High Resolution Enable bit 0 position. */ -#define HIRES_HREN1_bm (1<<1) /* High Resolution Enable bit 1 mask. */ -#define HIRES_HREN1_bp 1 /* High Resolution Enable bit 1 position. */ - -/* USART - Universal Asynchronous Receiver-Transmitter */ -/* USART.STATUS bit masks and bit positions */ -#define USART_RXCIF_bm 0x80 /* Receive Interrupt Flag bit mask. */ -#define USART_RXCIF_bp 7 /* Receive Interrupt Flag bit position. */ - -#define USART_TXCIF_bm 0x40 /* Transmit Interrupt Flag bit mask. */ -#define USART_TXCIF_bp 6 /* Transmit Interrupt Flag bit position. */ - -#define USART_DREIF_bm 0x20 /* Data Register Empty Flag bit mask. */ -#define USART_DREIF_bp 5 /* Data Register Empty Flag bit position. */ - -#define USART_FERR_bm 0x10 /* Frame Error bit mask. */ -#define USART_FERR_bp 4 /* Frame Error bit position. */ - -#define USART_BUFOVF_bm 0x08 /* Buffer Overflow bit mask. */ -#define USART_BUFOVF_bp 3 /* Buffer Overflow bit position. */ - -#define USART_PERR_bm 0x04 /* Parity Error bit mask. */ -#define USART_PERR_bp 2 /* Parity Error bit position. */ - -#define USART_RXB8_bm 0x01 /* Receive Bit 8 bit mask. */ -#define USART_RXB8_bp 0 /* Receive Bit 8 bit position. */ - -/* USART.CTRLA bit masks and bit positions */ -#define USART_RXCINTLVL_gm 0x30 /* Receive Interrupt Level group mask. */ -#define USART_RXCINTLVL_gp 4 /* Receive Interrupt Level group position. */ -#define USART_RXCINTLVL0_bm (1<<4) /* Receive Interrupt Level bit 0 mask. */ -#define USART_RXCINTLVL0_bp 4 /* Receive Interrupt Level bit 0 position. */ -#define USART_RXCINTLVL1_bm (1<<5) /* Receive Interrupt Level bit 1 mask. */ -#define USART_RXCINTLVL1_bp 5 /* Receive Interrupt Level bit 1 position. */ - -#define USART_TXCINTLVL_gm 0x0C /* Transmit Interrupt Level group mask. */ -#define USART_TXCINTLVL_gp 2 /* Transmit Interrupt Level group position. */ -#define USART_TXCINTLVL0_bm (1<<2) /* Transmit Interrupt Level bit 0 mask. */ -#define USART_TXCINTLVL0_bp 2 /* Transmit Interrupt Level bit 0 position. */ -#define USART_TXCINTLVL1_bm (1<<3) /* Transmit Interrupt Level bit 1 mask. */ -#define USART_TXCINTLVL1_bp 3 /* Transmit Interrupt Level bit 1 position. */ - -#define USART_DREINTLVL_gm 0x03 /* Data Register Empty Interrupt Level group mask. */ -#define USART_DREINTLVL_gp 0 /* Data Register Empty Interrupt Level group position. */ -#define USART_DREINTLVL0_bm (1<<0) /* Data Register Empty Interrupt Level bit 0 mask. */ -#define USART_DREINTLVL0_bp 0 /* Data Register Empty Interrupt Level bit 0 position. */ -#define USART_DREINTLVL1_bm (1<<1) /* Data Register Empty Interrupt Level bit 1 mask. */ -#define USART_DREINTLVL1_bp 1 /* Data Register Empty Interrupt Level bit 1 position. */ - -/* USART.CTRLB bit masks and bit positions */ -#define USART_RXEN_bm 0x10 /* Receiver Enable bit mask. */ -#define USART_RXEN_bp 4 /* Receiver Enable bit position. */ - -#define USART_TXEN_bm 0x08 /* Transmitter Enable bit mask. */ -#define USART_TXEN_bp 3 /* Transmitter Enable bit position. */ - -#define USART_CLK2X_bm 0x04 /* Double transmission speed bit mask. */ -#define USART_CLK2X_bp 2 /* Double transmission speed bit position. */ - -#define USART_MPCM_bm 0x02 /* Multi-processor Communication Mode bit mask. */ -#define USART_MPCM_bp 1 /* Multi-processor Communication Mode bit position. */ - -#define USART_TXB8_bm 0x01 /* Transmit bit 8 bit mask. */ -#define USART_TXB8_bp 0 /* Transmit bit 8 bit position. */ - -/* USART.CTRLC bit masks and bit positions */ -#define USART_CMODE_gm 0xC0 /* Communication Mode group mask. */ -#define USART_CMODE_gp 6 /* Communication Mode group position. */ -#define USART_CMODE0_bm (1<<6) /* Communication Mode bit 0 mask. */ -#define USART_CMODE0_bp 6 /* Communication Mode bit 0 position. */ -#define USART_CMODE1_bm (1<<7) /* Communication Mode bit 1 mask. */ -#define USART_CMODE1_bp 7 /* Communication Mode bit 1 position. */ - -#define USART_PMODE_gm 0x30 /* Parity Mode group mask. */ -#define USART_PMODE_gp 4 /* Parity Mode group position. */ -#define USART_PMODE0_bm (1<<4) /* Parity Mode bit 0 mask. */ -#define USART_PMODE0_bp 4 /* Parity Mode bit 0 position. */ -#define USART_PMODE1_bm (1<<5) /* Parity Mode bit 1 mask. */ -#define USART_PMODE1_bp 5 /* Parity Mode bit 1 position. */ - -#define USART_SBMODE_bm 0x08 /* Stop Bit Mode bit mask. */ -#define USART_SBMODE_bp 3 /* Stop Bit Mode bit position. */ - -#define USART_CHSIZE_gm 0x07 /* Character Size group mask. */ -#define USART_CHSIZE_gp 0 /* Character Size group position. */ -#define USART_CHSIZE0_bm (1<<0) /* Character Size bit 0 mask. */ -#define USART_CHSIZE0_bp 0 /* Character Size bit 0 position. */ -#define USART_CHSIZE1_bm (1<<1) /* Character Size bit 1 mask. */ -#define USART_CHSIZE1_bp 1 /* Character Size bit 1 position. */ -#define USART_CHSIZE2_bm (1<<2) /* Character Size bit 2 mask. */ -#define USART_CHSIZE2_bp 2 /* Character Size bit 2 position. */ - -/* USART.BAUDCTRLA bit masks and bit positions */ -#define USART_BSEL_gm 0xFF /* Baud Rate Selection Bits [7:0] group mask. */ -#define USART_BSEL_gp 0 /* Baud Rate Selection Bits [7:0] group position. */ -#define USART_BSEL0_bm (1<<0) /* Baud Rate Selection Bits [7:0] bit 0 mask. */ -#define USART_BSEL0_bp 0 /* Baud Rate Selection Bits [7:0] bit 0 position. */ -#define USART_BSEL1_bm (1<<1) /* Baud Rate Selection Bits [7:0] bit 1 mask. */ -#define USART_BSEL1_bp 1 /* Baud Rate Selection Bits [7:0] bit 1 position. */ -#define USART_BSEL2_bm (1<<2) /* Baud Rate Selection Bits [7:0] bit 2 mask. */ -#define USART_BSEL2_bp 2 /* Baud Rate Selection Bits [7:0] bit 2 position. */ -#define USART_BSEL3_bm (1<<3) /* Baud Rate Selection Bits [7:0] bit 3 mask. */ -#define USART_BSEL3_bp 3 /* Baud Rate Selection Bits [7:0] bit 3 position. */ -#define USART_BSEL4_bm (1<<4) /* Baud Rate Selection Bits [7:0] bit 4 mask. */ -#define USART_BSEL4_bp 4 /* Baud Rate Selection Bits [7:0] bit 4 position. */ -#define USART_BSEL5_bm (1<<5) /* Baud Rate Selection Bits [7:0] bit 5 mask. */ -#define USART_BSEL5_bp 5 /* Baud Rate Selection Bits [7:0] bit 5 position. */ -#define USART_BSEL6_bm (1<<6) /* Baud Rate Selection Bits [7:0] bit 6 mask. */ -#define USART_BSEL6_bp 6 /* Baud Rate Selection Bits [7:0] bit 6 position. */ -#define USART_BSEL7_bm (1<<7) /* Baud Rate Selection Bits [7:0] bit 7 mask. */ -#define USART_BSEL7_bp 7 /* Baud Rate Selection Bits [7:0] bit 7 position. */ - -/* USART.BAUDCTRLB bit masks and bit positions */ -#define USART_BSCALE_gm 0xF0 /* Baud Rate Scale group mask. */ -#define USART_BSCALE_gp 4 /* Baud Rate Scale group position. */ -#define USART_BSCALE0_bm (1<<4) /* Baud Rate Scale bit 0 mask. */ -#define USART_BSCALE0_bp 4 /* Baud Rate Scale bit 0 position. */ -#define USART_BSCALE1_bm (1<<5) /* Baud Rate Scale bit 1 mask. */ -#define USART_BSCALE1_bp 5 /* Baud Rate Scale bit 1 position. */ -#define USART_BSCALE2_bm (1<<6) /* Baud Rate Scale bit 2 mask. */ -#define USART_BSCALE2_bp 6 /* Baud Rate Scale bit 2 position. */ -#define USART_BSCALE3_bm (1<<7) /* Baud Rate Scale bit 3 mask. */ -#define USART_BSCALE3_bp 7 /* Baud Rate Scale bit 3 position. */ - -/* USART_BSEL Predefined. */ -/* USART_BSEL Predefined. */ - -/* SPI - Serial Peripheral Interface */ -/* SPI.CTRL bit masks and bit positions */ -#define SPI_CLK2X_bm 0x80 /* Enable Double Speed bit mask. */ -#define SPI_CLK2X_bp 7 /* Enable Double Speed bit position. */ - -#define SPI_ENABLE_bm 0x40 /* Enable Module bit mask. */ -#define SPI_ENABLE_bp 6 /* Enable Module bit position. */ - -#define SPI_DORD_bm 0x20 /* Data Order Setting bit mask. */ -#define SPI_DORD_bp 5 /* Data Order Setting bit position. */ - -#define SPI_MASTER_bm 0x10 /* Master Operation Enable bit mask. */ -#define SPI_MASTER_bp 4 /* Master Operation Enable bit position. */ - -#define SPI_MODE_gm 0x0C /* SPI Mode group mask. */ -#define SPI_MODE_gp 2 /* SPI Mode group position. */ -#define SPI_MODE0_bm (1<<2) /* SPI Mode bit 0 mask. */ -#define SPI_MODE0_bp 2 /* SPI Mode bit 0 position. */ -#define SPI_MODE1_bm (1<<3) /* SPI Mode bit 1 mask. */ -#define SPI_MODE1_bp 3 /* SPI Mode bit 1 position. */ - -#define SPI_PRESCALER_gm 0x03 /* Prescaler group mask. */ -#define SPI_PRESCALER_gp 0 /* Prescaler group position. */ -#define SPI_PRESCALER0_bm (1<<0) /* Prescaler bit 0 mask. */ -#define SPI_PRESCALER0_bp 0 /* Prescaler bit 0 position. */ -#define SPI_PRESCALER1_bm (1<<1) /* Prescaler bit 1 mask. */ -#define SPI_PRESCALER1_bp 1 /* Prescaler bit 1 position. */ - -/* SPI.INTCTRL bit masks and bit positions */ -#define SPI_INTLVL_gm 0x03 /* Interrupt level group mask. */ -#define SPI_INTLVL_gp 0 /* Interrupt level group position. */ -#define SPI_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */ -#define SPI_INTLVL0_bp 0 /* Interrupt level bit 0 position. */ -#define SPI_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */ -#define SPI_INTLVL1_bp 1 /* Interrupt level bit 1 position. */ - -/* SPI.STATUS bit masks and bit positions */ -#define SPI_IF_bm 0x80 /* Interrupt Flag bit mask. */ -#define SPI_IF_bp 7 /* Interrupt Flag bit position. */ - -#define SPI_WRCOL_bm 0x40 /* Write Collision bit mask. */ -#define SPI_WRCOL_bp 6 /* Write Collision bit position. */ - -/* IRCOM - IR Communication Module */ -/* IRCOM.CTRL bit masks and bit positions */ -#define IRCOM_EVSEL_gm 0x0F /* Event Channel Select group mask. */ -#define IRCOM_EVSEL_gp 0 /* Event Channel Select group position. */ -#define IRCOM_EVSEL0_bm (1<<0) /* Event Channel Select bit 0 mask. */ -#define IRCOM_EVSEL0_bp 0 /* Event Channel Select bit 0 position. */ -#define IRCOM_EVSEL1_bm (1<<1) /* Event Channel Select bit 1 mask. */ -#define IRCOM_EVSEL1_bp 1 /* Event Channel Select bit 1 position. */ -#define IRCOM_EVSEL2_bm (1<<2) /* Event Channel Select bit 2 mask. */ -#define IRCOM_EVSEL2_bp 2 /* Event Channel Select bit 2 position. */ -#define IRCOM_EVSEL3_bm (1<<3) /* Event Channel Select bit 3 mask. */ -#define IRCOM_EVSEL3_bp 3 /* Event Channel Select bit 3 position. */ - -/* FUSE - Fuses and Lockbits */ -/* NVM_FUSES.FUSEBYTE1 bit masks and bit positions */ -#define NVM_FUSES_WDWP_gm 0xF0 /* Watchdog Window Timeout Period group mask. */ -#define NVM_FUSES_WDWP_gp 4 /* Watchdog Window Timeout Period group position. */ -#define NVM_FUSES_WDWP0_bm (1<<4) /* Watchdog Window Timeout Period bit 0 mask. */ -#define NVM_FUSES_WDWP0_bp 4 /* Watchdog Window Timeout Period bit 0 position. */ -#define NVM_FUSES_WDWP1_bm (1<<5) /* Watchdog Window Timeout Period bit 1 mask. */ -#define NVM_FUSES_WDWP1_bp 5 /* Watchdog Window Timeout Period bit 1 position. */ -#define NVM_FUSES_WDWP2_bm (1<<6) /* Watchdog Window Timeout Period bit 2 mask. */ -#define NVM_FUSES_WDWP2_bp 6 /* Watchdog Window Timeout Period bit 2 position. */ -#define NVM_FUSES_WDWP3_bm (1<<7) /* Watchdog Window Timeout Period bit 3 mask. */ -#define NVM_FUSES_WDWP3_bp 7 /* Watchdog Window Timeout Period bit 3 position. */ - -#define NVM_FUSES_WDP_gm 0x0F /* Watchdog Timeout Period group mask. */ -#define NVM_FUSES_WDP_gp 0 /* Watchdog Timeout Period group position. */ -#define NVM_FUSES_WDP0_bm (1<<0) /* Watchdog Timeout Period bit 0 mask. */ -#define NVM_FUSES_WDP0_bp 0 /* Watchdog Timeout Period bit 0 position. */ -#define NVM_FUSES_WDP1_bm (1<<1) /* Watchdog Timeout Period bit 1 mask. */ -#define NVM_FUSES_WDP1_bp 1 /* Watchdog Timeout Period bit 1 position. */ -#define NVM_FUSES_WDP2_bm (1<<2) /* Watchdog Timeout Period bit 2 mask. */ -#define NVM_FUSES_WDP2_bp 2 /* Watchdog Timeout Period bit 2 position. */ -#define NVM_FUSES_WDP3_bm (1<<3) /* Watchdog Timeout Period bit 3 mask. */ -#define NVM_FUSES_WDP3_bp 3 /* Watchdog Timeout Period bit 3 position. */ - -/* NVM_FUSES.FUSEBYTE2 bit masks and bit positions */ -#define NVM_FUSES_BOOTRST_bm 0x40 /* Boot Loader Section Reset Vector bit mask. */ -#define NVM_FUSES_BOOTRST_bp 6 /* Boot Loader Section Reset Vector bit position. */ - -#define NVM_FUSES_TOSCSEL_bm 0x20 /* Timer Oscillator pin location bit mask. */ -#define NVM_FUSES_TOSCSEL_bp 5 /* Timer Oscillator pin location bit position. */ - -#define NVM_FUSES_BODPD_gm 0x03 /* BOD Operation in Power-Down Mode group mask. */ -#define NVM_FUSES_BODPD_gp 0 /* BOD Operation in Power-Down Mode group position. */ -#define NVM_FUSES_BODPD0_bm (1<<0) /* BOD Operation in Power-Down Mode bit 0 mask. */ -#define NVM_FUSES_BODPD0_bp 0 /* BOD Operation in Power-Down Mode bit 0 position. */ -#define NVM_FUSES_BODPD1_bm (1<<1) /* BOD Operation in Power-Down Mode bit 1 mask. */ -#define NVM_FUSES_BODPD1_bp 1 /* BOD Operation in Power-Down Mode bit 1 position. */ - -/* NVM_FUSES.FUSEBYTE4 bit masks and bit positions */ -#define NVM_FUSES_RSTDISBL_bm 0x10 /* External Reset Disable bit mask. */ -#define NVM_FUSES_RSTDISBL_bp 4 /* External Reset Disable bit position. */ - -#define NVM_FUSES_SUT_gm 0x0C /* Start-up Time group mask. */ -#define NVM_FUSES_SUT_gp 2 /* Start-up Time group position. */ -#define NVM_FUSES_SUT0_bm (1<<2) /* Start-up Time bit 0 mask. */ -#define NVM_FUSES_SUT0_bp 2 /* Start-up Time bit 0 position. */ -#define NVM_FUSES_SUT1_bm (1<<3) /* Start-up Time bit 1 mask. */ -#define NVM_FUSES_SUT1_bp 3 /* Start-up Time bit 1 position. */ - -#define NVM_FUSES_WDLOCK_bm 0x02 /* Watchdog Timer Lock bit mask. */ -#define NVM_FUSES_WDLOCK_bp 1 /* Watchdog Timer Lock bit position. */ - -/* NVM_FUSES.FUSEBYTE5 bit masks and bit positions */ -#define NVM_FUSES_BODACT_gm 0x30 /* BOD Operation in Active Mode group mask. */ -#define NVM_FUSES_BODACT_gp 4 /* BOD Operation in Active Mode group position. */ -#define NVM_FUSES_BODACT0_bm (1<<4) /* BOD Operation in Active Mode bit 0 mask. */ -#define NVM_FUSES_BODACT0_bp 4 /* BOD Operation in Active Mode bit 0 position. */ -#define NVM_FUSES_BODACT1_bm (1<<5) /* BOD Operation in Active Mode bit 1 mask. */ -#define NVM_FUSES_BODACT1_bp 5 /* BOD Operation in Active Mode bit 1 position. */ - -#define NVM_FUSES_EESAVE_bm 0x08 /* Preserve EEPROM Through Chip Erase bit mask. */ -#define NVM_FUSES_EESAVE_bp 3 /* Preserve EEPROM Through Chip Erase bit position. */ - -#define NVM_FUSES_BODLVL_gm 0x07 /* Brownout Detection Voltage Level group mask. */ -#define NVM_FUSES_BODLVL_gp 0 /* Brownout Detection Voltage Level group position. */ -#define NVM_FUSES_BODLVL0_bm (1<<0) /* Brownout Detection Voltage Level bit 0 mask. */ -#define NVM_FUSES_BODLVL0_bp 0 /* Brownout Detection Voltage Level bit 0 position. */ -#define NVM_FUSES_BODLVL1_bm (1<<1) /* Brownout Detection Voltage Level bit 1 mask. */ -#define NVM_FUSES_BODLVL1_bp 1 /* Brownout Detection Voltage Level bit 1 position. */ -#define NVM_FUSES_BODLVL2_bm (1<<2) /* Brownout Detection Voltage Level bit 2 mask. */ -#define NVM_FUSES_BODLVL2_bp 2 /* Brownout Detection Voltage Level bit 2 position. */ - -/* LOCKBIT - Fuses and Lockbits */ -/* NVM_LOCKBITS.LOCKBITS bit masks and bit positions */ -#define NVM_LOCKBITS_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ -#define NVM_LOCKBITS_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ -#define NVM_LOCKBITS_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ -#define NVM_LOCKBITS_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ -#define NVM_LOCKBITS_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ -#define NVM_LOCKBITS_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ - -#define NVM_LOCKBITS_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ -#define NVM_LOCKBITS_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ -#define NVM_LOCKBITS_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ -#define NVM_LOCKBITS_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ -#define NVM_LOCKBITS_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ -#define NVM_LOCKBITS_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ - -#define NVM_LOCKBITS_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ -#define NVM_LOCKBITS_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ -#define NVM_LOCKBITS_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ -#define NVM_LOCKBITS_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ -#define NVM_LOCKBITS_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ -#define NVM_LOCKBITS_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ - -#define NVM_LOCKBITS_LB_gm 0x03 /* Lock Bits group mask. */ -#define NVM_LOCKBITS_LB_gp 0 /* Lock Bits group position. */ -#define NVM_LOCKBITS_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ -#define NVM_LOCKBITS_LB0_bp 0 /* Lock Bits bit 0 position. */ -#define NVM_LOCKBITS_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ -#define NVM_LOCKBITS_LB1_bp 1 /* Lock Bits bit 1 position. */ - - - -// Generic Port Pins - -#define PIN0_bm 0x01 -#define PIN0_bp 0 -#define PIN1_bm 0x02 -#define PIN1_bp 1 -#define PIN2_bm 0x04 -#define PIN2_bp 2 -#define PIN3_bm 0x08 -#define PIN3_bp 3 -#define PIN4_bm 0x10 -#define PIN4_bp 4 -#define PIN5_bm 0x20 -#define PIN5_bp 5 -#define PIN6_bm 0x40 -#define PIN6_bp 6 -#define PIN7_bm 0x80 -#define PIN7_bp 7 - -/* ========== Interrupt Vector Definitions ========== */ -/* Vector 0 is the reset vector */ - -/* OSC interrupt vectors */ -#define OSC_OSCF_vect_num 1 -#define OSC_OSCF_vect _VECTOR(1) /* Oscillator Failure Interrupt (NMI) */ - -/* PORTC interrupt vectors */ -#define PORTC_INT0_vect_num 2 -#define PORTC_INT0_vect _VECTOR(2) /* External Interrupt 0 */ -#define PORTC_INT1_vect_num 3 -#define PORTC_INT1_vect _VECTOR(3) /* External Interrupt 1 */ - -/* PORTR interrupt vectors */ -#define PORTR_INT0_vect_num 4 -#define PORTR_INT0_vect _VECTOR(4) /* External Interrupt 0 */ -#define PORTR_INT1_vect_num 5 -#define PORTR_INT1_vect _VECTOR(5) /* External Interrupt 1 */ - -/* RTC interrupt vectors */ -#define RTC_OVF_vect_num 10 -#define RTC_OVF_vect _VECTOR(10) /* Overflow Interrupt */ -#define RTC_COMP_vect_num 11 -#define RTC_COMP_vect _VECTOR(11) /* Compare Interrupt */ - -/* TWIC interrupt vectors */ -#define TWIC_TWIS_vect_num 12 -#define TWIC_TWIS_vect _VECTOR(12) /* TWI Slave Interrupt */ -#define TWIC_TWIM_vect_num 13 -#define TWIC_TWIM_vect _VECTOR(13) /* TWI Master Interrupt */ - -/* TCC0 interrupt vectors */ -#define TCC0_OVF_vect_num 14 -#define TCC0_OVF_vect _VECTOR(14) /* Overflow Interrupt */ - -/* TCC2 interrupt vectors */ -#define TCC2_LUNF_vect_num 14 -#define TCC2_LUNF_vect _VECTOR(14) /* Low Byte Underflow Interrupt */ - -/* TCC0 interrupt vectors */ -#define TCC0_ERR_vect_num 15 -#define TCC0_ERR_vect _VECTOR(15) /* Error Interrupt */ - -/* TCC2 interrupt vectors */ -#define TCC2_HUNF_vect_num 15 -#define TCC2_HUNF_vect _VECTOR(15) /* High Byte Underflow Interrupt */ - -/* TCC0 interrupt vectors */ -#define TCC0_CCA_vect_num 16 -#define TCC0_CCA_vect _VECTOR(16) /* Compare or Capture A Interrupt */ - -/* TCC2 interrupt vectors */ -#define TCC2_LCMPA_vect_num 16 -#define TCC2_LCMPA_vect _VECTOR(16) /* Low Byte Compare A Interrupt */ - -/* TCC0 interrupt vectors */ -#define TCC0_CCB_vect_num 17 -#define TCC0_CCB_vect _VECTOR(17) /* Compare or Capture B Interrupt */ - -/* TCC2 interrupt vectors */ -#define TCC2_LCMPB_vect_num 17 -#define TCC2_LCMPB_vect _VECTOR(17) /* Low Byte Compare B Interrupt */ - -/* TCC0 interrupt vectors */ -#define TCC0_CCC_vect_num 18 -#define TCC0_CCC_vect _VECTOR(18) /* Compare or Capture C Interrupt */ - -/* TCC2 interrupt vectors */ -#define TCC2_LCMPC_vect_num 18 -#define TCC2_LCMPC_vect _VECTOR(18) /* Low Byte Compare C Interrupt */ - -/* TCC0 interrupt vectors */ -#define TCC0_CCD_vect_num 19 -#define TCC0_CCD_vect _VECTOR(19) /* Compare or Capture D Interrupt */ - -/* TCC2 interrupt vectors */ -#define TCC2_LCMPD_vect_num 19 -#define TCC2_LCMPD_vect _VECTOR(19) /* Low Byte Compare D Interrupt */ - -/* TCC1 interrupt vectors */ -#define TCC1_OVF_vect_num 20 -#define TCC1_OVF_vect _VECTOR(20) /* Overflow Interrupt */ -#define TCC1_ERR_vect_num 21 -#define TCC1_ERR_vect _VECTOR(21) /* Error Interrupt */ -#define TCC1_CCA_vect_num 22 -#define TCC1_CCA_vect _VECTOR(22) /* Compare or Capture A Interrupt */ -#define TCC1_CCB_vect_num 23 -#define TCC1_CCB_vect _VECTOR(23) /* Compare or Capture B Interrupt */ - -/* SPIC interrupt vectors */ -#define SPIC_INT_vect_num 24 -#define SPIC_INT_vect _VECTOR(24) /* SPI Interrupt */ - -/* USARTC0 interrupt vectors */ -#define USARTC0_RXC_vect_num 25 -#define USARTC0_RXC_vect _VECTOR(25) /* Reception Complete Interrupt */ -#define USARTC0_DRE_vect_num 26 -#define USARTC0_DRE_vect _VECTOR(26) /* Data Register Empty Interrupt */ -#define USARTC0_TXC_vect_num 27 -#define USARTC0_TXC_vect _VECTOR(27) /* Transmission Complete Interrupt */ - -/* NVM interrupt vectors */ -#define NVM_EE_vect_num 32 -#define NVM_EE_vect _VECTOR(32) /* EE Interrupt */ -#define NVM_SPM_vect_num 33 -#define NVM_SPM_vect _VECTOR(33) /* SPM Interrupt */ - -/* PORTB interrupt vectors */ -#define PORTB_INT0_vect_num 34 -#define PORTB_INT0_vect _VECTOR(34) /* External Interrupt 0 */ -#define PORTB_INT1_vect_num 35 -#define PORTB_INT1_vect _VECTOR(35) /* External Interrupt 1 */ - -/* PORTE interrupt vectors */ -#define PORTE_INT0_vect_num 43 -#define PORTE_INT0_vect _VECTOR(43) /* External Interrupt 0 */ -#define PORTE_INT1_vect_num 44 -#define PORTE_INT1_vect _VECTOR(44) /* External Interrupt 1 */ - -/* TWIE interrupt vectors */ -#define TWIE_TWIS_vect_num 45 -#define TWIE_TWIS_vect _VECTOR(45) /* TWI Slave Interrupt */ -#define TWIE_TWIM_vect_num 46 -#define TWIE_TWIM_vect _VECTOR(46) /* TWI Master Interrupt */ - -/* TCE0 interrupt vectors */ -#define TCE0_OVF_vect_num 47 -#define TCE0_OVF_vect _VECTOR(47) /* Overflow Interrupt */ - -/* TCE2 interrupt vectors */ -#define TCE2_LUNF_vect_num 47 -#define TCE2_LUNF_vect _VECTOR(47) /* Low Byte Underflow Interrupt */ - -/* TCE0 interrupt vectors */ -#define TCE0_ERR_vect_num 48 -#define TCE0_ERR_vect _VECTOR(48) /* Error Interrupt */ - -/* TCE2 interrupt vectors */ -#define TCE2_HUNF_vect_num 48 -#define TCE2_HUNF_vect _VECTOR(48) /* High Byte Underflow Interrupt */ - -/* TCE0 interrupt vectors */ -#define TCE0_CCA_vect_num 49 -#define TCE0_CCA_vect _VECTOR(49) /* Compare or Capture A Interrupt */ - -/* TCE2 interrupt vectors */ -#define TCE2_LCMPA_vect_num 49 -#define TCE2_LCMPA_vect _VECTOR(49) /* Low Byte Compare A Interrupt */ - -/* TCE0 interrupt vectors */ -#define TCE0_CCB_vect_num 50 -#define TCE0_CCB_vect _VECTOR(50) /* Compare or Capture B Interrupt */ - -/* TCE2 interrupt vectors */ -#define TCE2_LCMPB_vect_num 50 -#define TCE2_LCMPB_vect _VECTOR(50) /* Low Byte Compare B Interrupt */ - -/* TCE0 interrupt vectors */ -#define TCE0_CCC_vect_num 51 -#define TCE0_CCC_vect _VECTOR(51) /* Compare or Capture C Interrupt */ - -/* TCE2 interrupt vectors */ -#define TCE2_LCMPC_vect_num 51 -#define TCE2_LCMPC_vect _VECTOR(51) /* Low Byte Compare C Interrupt */ - -/* TCE0 interrupt vectors */ -#define TCE0_CCD_vect_num 52 -#define TCE0_CCD_vect _VECTOR(52) /* Compare or Capture D Interrupt */ - -/* TCE2 interrupt vectors */ -#define TCE2_LCMPD_vect_num 52 -#define TCE2_LCMPD_vect _VECTOR(52) /* Low Byte Compare D Interrupt */ - -/* USARTE0 interrupt vectors */ -#define USARTE0_RXC_vect_num 58 -#define USARTE0_RXC_vect _VECTOR(58) /* Reception Complete Interrupt */ -#define USARTE0_DRE_vect_num 59 -#define USARTE0_DRE_vect _VECTOR(59) /* Data Register Empty Interrupt */ -#define USARTE0_TXC_vect_num 60 -#define USARTE0_TXC_vect _VECTOR(60) /* Transmission Complete Interrupt */ - -/* PORTD interrupt vectors */ -#define PORTD_INT0_vect_num 64 -#define PORTD_INT0_vect _VECTOR(64) /* External Interrupt 0 */ -#define PORTD_INT1_vect_num 65 -#define PORTD_INT1_vect _VECTOR(65) /* External Interrupt 1 */ - -/* PORTA interrupt vectors */ -#define PORTA_INT0_vect_num 66 -#define PORTA_INT0_vect _VECTOR(66) /* External Interrupt 0 */ -#define PORTA_INT1_vect_num 67 -#define PORTA_INT1_vect _VECTOR(67) /* External Interrupt 1 */ - -/* ACA interrupt vectors */ -#define ACA_AC0_vect_num 68 -#define ACA_AC0_vect _VECTOR(68) /* AC0 Interrupt */ -#define ACA_AC1_vect_num 69 -#define ACA_AC1_vect _VECTOR(69) /* AC1 Interrupt */ -#define ACA_ACW_vect_num 70 -#define ACA_ACW_vect _VECTOR(70) /* ACW Window Mode Interrupt */ - -/* ADCA interrupt vectors */ -#define ADCA_CH0_vect_num 71 -#define ADCA_CH0_vect _VECTOR(71) /* Interrupt 0 */ - -/* TCD0 interrupt vectors */ -#define TCD0_OVF_vect_num 77 -#define TCD0_OVF_vect _VECTOR(77) /* Overflow Interrupt */ - -/* TCD2 interrupt vectors */ -#define TCD2_LUNF_vect_num 77 -#define TCD2_LUNF_vect _VECTOR(77) /* Low Byte Underflow Interrupt */ - -/* TCD0 interrupt vectors */ -#define TCD0_ERR_vect_num 78 -#define TCD0_ERR_vect _VECTOR(78) /* Error Interrupt */ - -/* TCD2 interrupt vectors */ -#define TCD2_HUNF_vect_num 78 -#define TCD2_HUNF_vect _VECTOR(78) /* High Byte Underflow Interrupt */ - -/* TCD0 interrupt vectors */ -#define TCD0_CCA_vect_num 79 -#define TCD0_CCA_vect _VECTOR(79) /* Compare or Capture A Interrupt */ - -/* TCD2 interrupt vectors */ -#define TCD2_LCMPA_vect_num 79 -#define TCD2_LCMPA_vect _VECTOR(79) /* Low Byte Compare A Interrupt */ - -/* TCD0 interrupt vectors */ -#define TCD0_CCB_vect_num 80 -#define TCD0_CCB_vect _VECTOR(80) /* Compare or Capture B Interrupt */ - -/* TCD2 interrupt vectors */ -#define TCD2_LCMPB_vect_num 80 -#define TCD2_LCMPB_vect _VECTOR(80) /* Low Byte Compare B Interrupt */ - -/* TCD0 interrupt vectors */ -#define TCD0_CCC_vect_num 81 -#define TCD0_CCC_vect _VECTOR(81) /* Compare or Capture C Interrupt */ - -/* TCD2 interrupt vectors */ -#define TCD2_LCMPC_vect_num 81 -#define TCD2_LCMPC_vect _VECTOR(81) /* Low Byte Compare C Interrupt */ - -/* TCD0 interrupt vectors */ -#define TCD0_CCD_vect_num 82 -#define TCD0_CCD_vect _VECTOR(82) /* Compare or Capture D Interrupt */ - -/* TCD2 interrupt vectors */ -#define TCD2_LCMPD_vect_num 82 -#define TCD2_LCMPD_vect _VECTOR(82) /* Low Byte Compare D Interrupt */ - -/* SPID interrupt vectors */ -#define SPID_INT_vect_num 87 -#define SPID_INT_vect _VECTOR(87) /* SPI Interrupt */ - -/* USARTD0 interrupt vectors */ -#define USARTD0_RXC_vect_num 88 -#define USARTD0_RXC_vect _VECTOR(88) /* Reception Complete Interrupt */ -#define USARTD0_DRE_vect_num 89 -#define USARTD0_DRE_vect _VECTOR(89) /* Data Register Empty Interrupt */ -#define USARTD0_TXC_vect_num 90 -#define USARTD0_TXC_vect _VECTOR(90) /* Transmission Complete Interrupt */ - -/* PORTF interrupt vectors */ -#define PORTF_INT0_vect_num 104 -#define PORTF_INT0_vect _VECTOR(104) /* External Interrupt 0 */ -#define PORTF_INT1_vect_num 105 -#define PORTF_INT1_vect _VECTOR(105) /* External Interrupt 1 */ - -/* TCF0 interrupt vectors */ -#define TCF0_OVF_vect_num 108 -#define TCF0_OVF_vect _VECTOR(108) /* Overflow Interrupt */ - -/* TCF2 interrupt vectors */ -#define TCF2_LUNF_vect_num 108 -#define TCF2_LUNF_vect _VECTOR(108) /* Low Byte Underflow Interrupt */ - -/* TCF0 interrupt vectors */ -#define TCF0_ERR_vect_num 109 -#define TCF0_ERR_vect _VECTOR(109) /* Error Interrupt */ - -/* TCF2 interrupt vectors */ -#define TCF2_HUNF_vect_num 109 -#define TCF2_HUNF_vect _VECTOR(109) /* High Byte Underflow Interrupt */ - -/* TCF0 interrupt vectors */ -#define TCF0_CCA_vect_num 110 -#define TCF0_CCA_vect _VECTOR(110) /* Compare or Capture A Interrupt */ - -/* TCF2 interrupt vectors */ -#define TCF2_LCMPA_vect_num 110 -#define TCF2_LCMPA_vect _VECTOR(110) /* Low Byte Compare A Interrupt */ - -/* TCF0 interrupt vectors */ -#define TCF0_CCB_vect_num 111 -#define TCF0_CCB_vect _VECTOR(111) /* Compare or Capture B Interrupt */ - -/* TCF2 interrupt vectors */ -#define TCF2_LCMPB_vect_num 111 -#define TCF2_LCMPB_vect _VECTOR(111) /* Low Byte Compare B Interrupt */ - -/* TCF0 interrupt vectors */ -#define TCF0_CCC_vect_num 112 -#define TCF0_CCC_vect _VECTOR(112) /* Compare or Capture C Interrupt */ - -/* TCF2 interrupt vectors */ -#define TCF2_LCMPC_vect_num 112 -#define TCF2_LCMPC_vect _VECTOR(112) /* Low Byte Compare C Interrupt */ - -/* TCF0 interrupt vectors */ -#define TCF0_CCD_vect_num 113 -#define TCF0_CCD_vect _VECTOR(113) /* Compare or Capture D Interrupt */ - -/* TCF2 interrupt vectors */ -#define TCF2_LCMPD_vect_num 113 -#define TCF2_LCMPD_vect _VECTOR(113) /* Low Byte Compare D Interrupt */ - -/* USB interrupt vectors */ -#define USB_BUSEVENT_vect_num 125 -#define USB_BUSEVENT_vect _VECTOR(125) /* SOF, suspend, resume, reset bus event interrupts, crc, underflow, overflow and stall error interrupts */ -#define USB_TRNCOMPL_vect_num 126 -#define USB_TRNCOMPL_vect _VECTOR(126) /* Transaction complete interrupt */ - -#define _VECTOR_SIZE 4 /* Size of individual vector. */ -#define _VECTORS_SIZE (127 * _VECTOR_SIZE) - - -/* ========== Constants ========== */ - -#define PROGMEM_START (0x0000) -#define PROGMEM_SIZE (69632) -#define PROGMEM_END (PROGMEM_START + PROGMEM_SIZE - 1) - -#define APP_SECTION_START (0x0000) -#define APP_SECTION_SIZE (65536) -#define APP_SECTION_PAGE_SIZE (256) -#define APP_SECTION_END (APP_SECTION_START + APP_SECTION_SIZE - 1) - -#define APPTABLE_SECTION_START (0xE000) -#define APPTABLE_SECTION_SIZE (4096) -#define APPTABLE_SECTION_PAGE_SIZE (256) -#define APPTABLE_SECTION_END (APPTABLE_SECTION_START + APPTABLE_SECTION_SIZE - 1) - -#define BOOT_SECTION_START (0x10000) -#define BOOT_SECTION_SIZE (4096) -#define BOOT_SECTION_PAGE_SIZE (256) -#define BOOT_SECTION_END (BOOT_SECTION_START + BOOT_SECTION_SIZE - 1) - -#define DATAMEM_START (0x0000) -#define DATAMEM_SIZE (12288) -#define DATAMEM_END (DATAMEM_START + DATAMEM_SIZE - 1) - -#define IO_START (0x0000) -#define IO_SIZE (4096) -#define IO_PAGE_SIZE (0) -#define IO_END (IO_START + IO_SIZE - 1) - -#define MAPPED_EEPROM_START (0x1000) -#define MAPPED_EEPROM_SIZE (2048) -#define MAPPED_EEPROM_PAGE_SIZE (0) -#define MAPPED_EEPROM_END (MAPPED_EEPROM_START + MAPPED_EEPROM_SIZE - 1) - -#define INTERNAL_SRAM_START (0x2000) -#define INTERNAL_SRAM_SIZE (4096) -#define INTERNAL_SRAM_PAGE_SIZE (0) -#define INTERNAL_SRAM_END (INTERNAL_SRAM_START + INTERNAL_SRAM_SIZE - 1) - -#define EEPROM_START (0x0000) -#define EEPROM_SIZE (2048) -#define EEPROM_PAGE_SIZE (32) -#define EEPROM_END (EEPROM_START + EEPROM_SIZE - 1) - -#define SIGNATURES_START (0x0000) -#define SIGNATURES_SIZE (3) -#define SIGNATURES_PAGE_SIZE (0) -#define SIGNATURES_END (SIGNATURES_START + SIGNATURES_SIZE - 1) - -#define FUSES_START (0x0000) -#define FUSES_SIZE (6) -#define FUSES_PAGE_SIZE (0) -#define FUSES_END (FUSES_START + FUSES_SIZE - 1) - -#define LOCKBITS_START (0x0000) -#define LOCKBITS_SIZE (1) -#define LOCKBITS_PAGE_SIZE (0) -#define LOCKBITS_END (LOCKBITS_START + LOCKBITS_SIZE - 1) - -#define USER_SIGNATURES_START (0x0000) -#define USER_SIGNATURES_SIZE (256) -#define USER_SIGNATURES_PAGE_SIZE (256) -#define USER_SIGNATURES_END (USER_SIGNATURES_START + USER_SIGNATURES_SIZE - 1) - -#define PROD_SIGNATURES_START (0x0000) -#define PROD_SIGNATURES_SIZE (64) -#define PROD_SIGNATURES_PAGE_SIZE (256) -#define PROD_SIGNATURES_END (PROD_SIGNATURES_START + PROD_SIGNATURES_SIZE - 1) - -#define FLASHSTART PROGMEM_START -#define FLASHEND PROGMEM_END -#define SPM_PAGESIZE 256 -#define RAMSTART INTERNAL_SRAM_START -#define RAMSIZE INTERNAL_SRAM_SIZE -#define RAMEND INTERNAL_SRAM_END -#define E2END EEPROM_END -#define E2PAGESIZE EEPROM_PAGE_SIZE - - -/* ========== Fuses ========== */ -#define FUSE_MEMORY_SIZE 6 - -/* Fuse Byte 0 Reserved */ - -/* Fuse Byte 1 */ -#define FUSE_WDP0 (unsigned char)~_BV(0) /* Watchdog Timeout Period Bit 0 */ -#define FUSE_WDP1 (unsigned char)~_BV(1) /* Watchdog Timeout Period Bit 1 */ -#define FUSE_WDP2 (unsigned char)~_BV(2) /* Watchdog Timeout Period Bit 2 */ -#define FUSE_WDP3 (unsigned char)~_BV(3) /* Watchdog Timeout Period Bit 3 */ -#define FUSE_WDWP0 (unsigned char)~_BV(4) /* Watchdog Window Timeout Period Bit 0 */ -#define FUSE_WDWP1 (unsigned char)~_BV(5) /* Watchdog Window Timeout Period Bit 1 */ -#define FUSE_WDWP2 (unsigned char)~_BV(6) /* Watchdog Window Timeout Period Bit 2 */ -#define FUSE_WDWP3 (unsigned char)~_BV(7) /* Watchdog Window Timeout Period Bit 3 */ -#define FUSE1_DEFAULT (0xFF) - -/* Fuse Byte 2 */ -#define FUSE_BODPD0 (unsigned char)~_BV(0) /* BOD Operation in Power-Down Mode Bit 0 */ -#define FUSE_BODPD1 (unsigned char)~_BV(1) /* BOD Operation in Power-Down Mode Bit 1 */ -#define FUSE_TOSCSEL (unsigned char)~_BV(5) /* Timer Oscillator pin location */ -#define FUSE_BOOTRST (unsigned char)~_BV(6) /* Boot Loader Section Reset Vector */ -#define FUSE2_DEFAULT (0xFF) - -/* Fuse Byte 3 Reserved */ - -/* Fuse Byte 4 */ -#define FUSE_WDLOCK (unsigned char)~_BV(1) /* Watchdog Timer Lock */ -#define FUSE_SUT0 (unsigned char)~_BV(2) /* Start-up Time Bit 0 */ -#define FUSE_SUT1 (unsigned char)~_BV(3) /* Start-up Time Bit 1 */ -#define FUSE_RSTDISBL (unsigned char)~_BV(4) /* External Reset Disable */ -#define FUSE4_DEFAULT (0xFF) - -/* Fuse Byte 5 */ -#define FUSE_BODLVL0 (unsigned char)~_BV(0) /* Brownout Detection Voltage Level Bit 0 */ -#define FUSE_BODLVL1 (unsigned char)~_BV(1) /* Brownout Detection Voltage Level Bit 1 */ -#define FUSE_BODLVL2 (unsigned char)~_BV(2) /* Brownout Detection Voltage Level Bit 2 */ -#define FUSE_EESAVE (unsigned char)~_BV(3) /* Preserve EEPROM Through Chip Erase */ -#define FUSE_BODACT0 (unsigned char)~_BV(4) /* BOD Operation in Active Mode Bit 0 */ -#define FUSE_BODACT1 (unsigned char)~_BV(5) /* BOD Operation in Active Mode Bit 1 */ -#define FUSE5_DEFAULT (0xFF) - -/* ========== Lock Bits ========== */ -#define __LOCK_BITS_EXIST -#define __BOOT_LOCK_APPLICATION_TABLE_BITS_EXIST -#define __BOOT_LOCK_APPLICATION_BITS_EXIST -#define __BOOT_LOCK_BOOT_BITS_EXIST - -/* ========== Signature ========== */ -#define SIGNATURE_0 0x1E -#define SIGNATURE_1 0x96 -#define SIGNATURE_2 0x49 - -/* ========== Power Reduction Condition Definitions ========== */ - -/* PR.PRGEN */ -#define __AVR_HAVE_PRGEN (PR_USB_bm|PR_AES_bm|PR_RTC_bm|PR_EVSYS_bm|PR_DMA_bm) -#define __AVR_HAVE_PRGEN_USB -#define __AVR_HAVE_PRGEN_AES -#define __AVR_HAVE_PRGEN_RTC -#define __AVR_HAVE_PRGEN_EVSYS -#define __AVR_HAVE_PRGEN_DMA - -/* PR.PRPA */ -#define __AVR_HAVE_PRPA (PR_ADC_bm|PR_AC_bm) -#define __AVR_HAVE_PRPA_ADC -#define __AVR_HAVE_PRPA_AC - -/* PR.PRPC */ -#define __AVR_HAVE_PRPC (PR_TWI_bm|PR_USART1_bm|PR_USART0_bm|PR_SPI_bm|PR_HIRES_bm|PR_TC1_bm|PR_TC0_bm) -#define __AVR_HAVE_PRPC_TWI -#define __AVR_HAVE_PRPC_USART1 -#define __AVR_HAVE_PRPC_USART0 -#define __AVR_HAVE_PRPC_SPI -#define __AVR_HAVE_PRPC_HIRES -#define __AVR_HAVE_PRPC_TC1 -#define __AVR_HAVE_PRPC_TC0 - -/* PR.PRPD */ -#define __AVR_HAVE_PRPD (PR_USART0_bm|PR_SPI_bm|PR_TC0_bm) -#define __AVR_HAVE_PRPD_USART0 -#define __AVR_HAVE_PRPD_SPI -#define __AVR_HAVE_PRPD_TC0 - -/* PR.PRPE */ -#define __AVR_HAVE_PRPE (PR_TWI_bm|PR_USART0_bm|PR_TC0_bm) -#define __AVR_HAVE_PRPE_TWI -#define __AVR_HAVE_PRPE_USART0 -#define __AVR_HAVE_PRPE_TC0 - -/* PR.PRPF */ -#define __AVR_HAVE_PRPF (PR_USART0_bm|PR_TC0_bm) -#define __AVR_HAVE_PRPF_USART0 -#define __AVR_HAVE_PRPF_TC0 - - -#endif /* #ifdef _AVR_ATXMEGA64C3_H_INCLUDED */ - diff --git a/arduino/hardware/tools/avr/avr/include/avr/iox64d3.h b/arduino/hardware/tools/avr/avr/include/avr/iox64d3.h deleted file mode 100644 index 5c3ff34..0000000 --- a/arduino/hardware/tools/avr/avr/include/avr/iox64d3.h +++ /dev/null @@ -1,5764 +0,0 @@ -/* Copyright (c) 2009-2010 Atmel Corporation - All rights reserved. - - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - * Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - * Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in - the documentation and/or other materials provided with the - distribution. - - * Neither the name of the copyright holders nor the names of - contributors may be used to endorse or promote products derived - from this software without specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. */ - -/* $Id: iox64d3.h 2194 2010-11-16 15:10:51Z arcanum $ */ - -/* avr/iox64d3.h - definitions for ATxmega64D3 */ - -/* This file should only be included from , never directly. */ - -#ifndef _AVR_IO_H_ -# error "Include instead of this file." -#endif - -#ifndef _AVR_IOXXX_H_ -# define _AVR_IOXXX_H_ "iox64d3.h" -#else -# error "Attempt to include more than one file." -#endif - - -#ifndef _AVR_ATxmega64D3_H_ -#define _AVR_ATxmega64D3_H_ 1 - - -/* Ungrouped common registers */ -#define GPIOR0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ -#define GPIOR1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ -#define GPIOR2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ -#define GPIOR3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ -#define GPIOR4 _SFR_MEM8(0x0004) /* General Purpose IO Register 4 */ -#define GPIOR5 _SFR_MEM8(0x0005) /* General Purpose IO Register 5 */ -#define GPIOR6 _SFR_MEM8(0x0006) /* General Purpose IO Register 6 */ -#define GPIOR7 _SFR_MEM8(0x0007) /* General Purpose IO Register 7 */ -#define GPIOR8 _SFR_MEM8(0x0008) /* General Purpose IO Register 8 */ -#define GPIOR9 _SFR_MEM8(0x0009) /* General Purpose IO Register 9 */ -#define GPIORA _SFR_MEM8(0x000A) /* General Purpose IO Register 10 */ -#define GPIORB _SFR_MEM8(0x000B) /* General Purpose IO Register 11 */ -#define GPIORC _SFR_MEM8(0x000C) /* General Purpose IO Register 12 */ -#define GPIORD _SFR_MEM8(0x000D) /* General Purpose IO Register 13 */ -#define GPIORE _SFR_MEM8(0x000E) /* General Purpose IO Register 14 */ -#define GPIORF _SFR_MEM8(0x000F) /* General Purpose IO Register 15 */ - -#define CCP _SFR_MEM8(0x0034) /* Configuration Change Protection */ -#define RAMPD _SFR_MEM8(0x0038) /* Ramp D */ -#define RAMPX _SFR_MEM8(0x0039) /* Ramp X */ -#define RAMPY _SFR_MEM8(0x003A) /* Ramp Y */ -#define RAMPZ _SFR_MEM8(0x003B) /* Ramp Z */ -#define EIND _SFR_MEM8(0x003C) /* Extended Indirect Jump */ -#define SPL _SFR_MEM8(0x003D) /* Stack Pointer Low */ -#define SPH _SFR_MEM8(0x003E) /* Stack Pointer High */ -#define SREG _SFR_MEM8(0x003F) /* Status Register */ - - -/* C Language Only */ -#if !defined (__ASSEMBLER__) - -#include - -typedef volatile uint8_t register8_t; -typedef volatile uint16_t register16_t; -typedef volatile uint32_t register32_t; - - -#ifdef _WORDREGISTER -#undef _WORDREGISTER -#endif -#define _WORDREGISTER(regname) \ - __extension__ union \ - { \ - register16_t regname; \ - struct \ - { \ - register8_t regname ## L; \ - register8_t regname ## H; \ - }; \ - } - -#ifdef _DWORDREGISTER -#undef _DWORDREGISTER -#endif -#define _DWORDREGISTER(regname) \ - __extension__ union \ - { \ - register32_t regname; \ - struct \ - { \ - register8_t regname ## 0; \ - register8_t regname ## 1; \ - register8_t regname ## 2; \ - register8_t regname ## 3; \ - }; \ - } - - -/* -========================================================================== -IO Module Structures -========================================================================== -*/ - - -/* --------------------------------------------------------------------------- -XOCD - On-Chip Debug System --------------------------------------------------------------------------- -*/ - -/* On-Chip Debug System */ -typedef struct OCD_struct -{ - register8_t OCDR0; /* OCD Register 0 */ - register8_t OCDR1; /* OCD Register 1 */ -} OCD_t; - - -/* CCP signatures */ -typedef enum CCP_enum -{ - CCP_SPM_gc = (0x9D<<0), /* SPM Instruction Protection */ - CCP_IOREG_gc = (0xD8<<0), /* IO Register Protection */ -} CCP_t; - - -/* --------------------------------------------------------------------------- -CLK - Clock System --------------------------------------------------------------------------- -*/ - -/* Clock System */ -typedef struct CLK_struct -{ - register8_t CTRL; /* Control Register */ - register8_t PSCTRL; /* Prescaler Control Register */ - register8_t LOCK; /* Lock register */ - register8_t RTCCTRL; /* RTC Control Register */ -} CLK_t; - -/* --------------------------------------------------------------------------- -CLK - Clock System --------------------------------------------------------------------------- -*/ - -/* Power Reduction */ -typedef struct PR_struct -{ - register8_t PRGEN; /* General Power Reduction */ - register8_t PRPA; /* Power Reduction Port A */ - register8_t reserved_0x02; - register8_t PRPC; /* Power Reduction Port C */ - register8_t PRPD; /* Power Reduction Port D */ - register8_t PRPE; /* Power Reduction Port E */ - register8_t PRPF; /* Power Reduction Port F */ -} PR_t; - -/* System Clock Selection */ -typedef enum CLK_SCLKSEL_enum -{ - CLK_SCLKSEL_RC2M_gc = (0x00<<0), /* Internal 2MHz RC Oscillator */ - CLK_SCLKSEL_RC32M_gc = (0x01<<0), /* Internal 32MHz RC Oscillator */ - CLK_SCLKSEL_RC32K_gc = (0x02<<0), /* Internal 32kHz RC Oscillator */ - CLK_SCLKSEL_XOSC_gc = (0x03<<0), /* External Crystal Oscillator or Clock */ - CLK_SCLKSEL_PLL_gc = (0x04<<0), /* Phase Locked Loop */ -} CLK_SCLKSEL_t; - -/* Prescaler A Division Factor */ -typedef enum CLK_PSADIV_enum -{ - CLK_PSADIV_1_gc = (0x00<<2), /* Divide by 1 */ - CLK_PSADIV_2_gc = (0x01<<2), /* Divide by 2 */ - CLK_PSADIV_4_gc = (0x03<<2), /* Divide by 4 */ - CLK_PSADIV_8_gc = (0x05<<2), /* Divide by 8 */ - CLK_PSADIV_16_gc = (0x07<<2), /* Divide by 16 */ - CLK_PSADIV_32_gc = (0x09<<2), /* Divide by 32 */ - CLK_PSADIV_64_gc = (0x0B<<2), /* Divide by 64 */ - CLK_PSADIV_128_gc = (0x0D<<2), /* Divide by 128 */ - CLK_PSADIV_256_gc = (0x0F<<2), /* Divide by 256 */ - CLK_PSADIV_512_gc = (0x11<<2), /* Divide by 512 */ -} CLK_PSADIV_t; - -/* Prescaler B and C Division Factor */ -typedef enum CLK_PSBCDIV_enum -{ - CLK_PSBCDIV_1_1_gc = (0x00<<0), /* Divide B by 1 and C by 1 */ - CLK_PSBCDIV_1_2_gc = (0x01<<0), /* Divide B by 1 and C by 2 */ - CLK_PSBCDIV_4_1_gc = (0x02<<0), /* Divide B by 4 and C by 1 */ - CLK_PSBCDIV_2_2_gc = (0x03<<0), /* Divide B by 2 and C by 2 */ -} CLK_PSBCDIV_t; - -/* RTC Clock Source */ -typedef enum CLK_RTCSRC_enum -{ - CLK_RTCSRC_ULP_gc = (0x00<<1), /* 1kHz from internal 32kHz ULP */ - CLK_RTCSRC_TOSC_gc = (0x01<<1), /* 1kHz from 32kHz crystal oscillator on TOSC */ - CLK_RTCSRC_RCOSC_gc = (0x02<<1), /* 1kHz from internal 32kHz RC oscillator */ - CLK_RTCSRC_TOSC32_gc = (0x05<<1), /* 32kHz from 32kHz crystal oscillator on TOSC */ -} CLK_RTCSRC_t; - - -/* --------------------------------------------------------------------------- -SLEEP - Sleep Controller --------------------------------------------------------------------------- -*/ - -/* Sleep Controller */ -typedef struct SLEEP_struct -{ - register8_t CTRL; /* Control Register */ -} SLEEP_t; - -/* Sleep Mode */ -typedef enum SLEEP_SMODE_enum -{ - SLEEP_SMODE_IDLE_gc = (0x00<<1), /* Idle mode */ - SLEEP_SMODE_PDOWN_gc = (0x02<<1), /* Power-down Mode */ - SLEEP_SMODE_PSAVE_gc = (0x03<<1), /* Power-save Mode */ - SLEEP_SMODE_STDBY_gc = (0x06<<1), /* Standby Mode */ - SLEEP_SMODE_ESTDBY_gc = (0x07<<1), /* Extended Standby Mode */ -} SLEEP_SMODE_t; - - -#define SLEEP_MODE_IDLE (0x00<<1) -#define SLEEP_MODE_PWR_DOWN (0x02<<1) -#define SLEEP_MODE_PWR_SAVE (0x03<<1) -#define SLEEP_MODE_STANDBY (0x06<<1) -#define SLEEP_MODE_EXT_STANDBY (0x07<<1) - - -/* --------------------------------------------------------------------------- -OSC - Oscillator --------------------------------------------------------------------------- -*/ - -/* Oscillator */ -typedef struct OSC_struct -{ - register8_t CTRL; /* Control Register */ - register8_t STATUS; /* Status Register */ - register8_t XOSCCTRL; /* External Oscillator Control Register */ - register8_t XOSCFAIL; /* External Oscillator Failure Detection Register */ - register8_t RC32KCAL; /* 32kHz Internal Oscillator Calibration Register */ - register8_t PLLCTRL; /* PLL Control REgister */ - register8_t DFLLCTRL; /* DFLL Control Register */ -} OSC_t; - -/* Oscillator Frequency Range */ -typedef enum OSC_FRQRANGE_enum -{ - OSC_FRQRANGE_04TO2_gc = (0x00<<6), /* 0.4 - 2 MHz */ - OSC_FRQRANGE_2TO9_gc = (0x01<<6), /* 2 - 9 MHz */ - OSC_FRQRANGE_9TO12_gc = (0x02<<6), /* 9 - 12 MHz */ - OSC_FRQRANGE_12TO16_gc = (0x03<<6), /* 12 - 16 MHz */ -} OSC_FRQRANGE_t; - -/* External Oscillator Selection and Startup Time */ -typedef enum OSC_XOSCSEL_enum -{ - OSC_XOSCSEL_EXTCLK_gc = (0x00<<0), /* External Clock - 6 CLK */ - OSC_XOSCSEL_32KHz_gc = (0x02<<0), /* 32kHz TOSC - 32K CLK */ - OSC_XOSCSEL_XTAL_256CLK_gc = (0x03<<0), /* 0.4-16MHz XTAL - 256 CLK */ - OSC_XOSCSEL_XTAL_1KCLK_gc = (0x07<<0), /* 0.4-16MHz XTAL - 1K CLK */ - OSC_XOSCSEL_XTAL_16KCLK_gc = (0x0B<<0), /* 0.4-16MHz XTAL - 16K CLK */ -} OSC_XOSCSEL_t; - -/* PLL Clock Source */ -typedef enum OSC_PLLSRC_enum -{ - OSC_PLLSRC_RC2M_gc = (0x00<<6), /* Internal 2MHz RC Oscillator */ - OSC_PLLSRC_RC32M_gc = (0x02<<6), /* Internal 32MHz RC Oscillator */ - OSC_PLLSRC_XOSC_gc = (0x03<<6), /* External Oscillator */ -} OSC_PLLSRC_t; - - -/* --------------------------------------------------------------------------- -DFLL - DFLL --------------------------------------------------------------------------- -*/ - -/* DFLL */ -typedef struct DFLL_struct -{ - register8_t CTRL; /* Control Register */ - register8_t reserved_0x01; - register8_t CALA; /* Calibration Register A */ - register8_t CALB; /* Calibration Register B */ - register8_t COMP0; /* Oscillator Compare Register 0 */ - register8_t COMP1; /* Oscillator Compare Register 1 */ - register8_t COMP2; /* Oscillator Compare Register 2 */ - register8_t reserved_0x07; -} DFLL_t; - - -/* --------------------------------------------------------------------------- -RST - Reset --------------------------------------------------------------------------- -*/ - -/* Reset */ -typedef struct RST_struct -{ - register8_t STATUS; /* Status Register */ - register8_t CTRL; /* Control Register */ -} RST_t; - - -/* --------------------------------------------------------------------------- -WDT - Watch-Dog Timer --------------------------------------------------------------------------- -*/ - -/* Watch-Dog Timer */ -typedef struct WDT_struct -{ - register8_t CTRL; /* Control */ - register8_t WINCTRL; /* Windowed Mode Control */ - register8_t STATUS; /* Status */ -} WDT_t; - -/* Period setting */ -typedef enum WDT_PER_enum -{ - WDT_PER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ - WDT_PER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ - WDT_PER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ - WDT_PER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ - WDT_PER_125CLK_gc = (0x04<<2), /* 125 cycles (0.125s @ 3.3V) */ - WDT_PER_250CLK_gc = (0x05<<2), /* 250 cycles (0.25s @ 3.3V) */ - WDT_PER_500CLK_gc = (0x06<<2), /* 500 cycles (0.5s @ 3.3V) */ - WDT_PER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ - WDT_PER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ - WDT_PER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ - WDT_PER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ -} WDT_PER_t; - -/* Closed window period */ -typedef enum WDT_WPER_enum -{ - WDT_WPER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ - WDT_WPER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ - WDT_WPER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ - WDT_WPER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ - WDT_WPER_125CLK_gc = (0x04<<2), /* 125 cycles (0.125s @ 3.3V) */ - WDT_WPER_250CLK_gc = (0x05<<2), /* 250 cycles (0.25s @ 3.3V) */ - WDT_WPER_500CLK_gc = (0x06<<2), /* 500 cycles (0.5s @ 3.3V) */ - WDT_WPER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ - WDT_WPER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ - WDT_WPER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ - WDT_WPER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ -} WDT_WPER_t; - - -/* --------------------------------------------------------------------------- -MCU - MCU Control --------------------------------------------------------------------------- -*/ - -/* MCU Control */ -typedef struct MCU_struct -{ - register8_t DEVID0; /* Device ID byte 0 */ - register8_t DEVID1; /* Device ID byte 1 */ - register8_t DEVID2; /* Device ID byte 2 */ - register8_t REVID; /* Revision ID */ - register8_t JTAGUID; /* JTAG User ID */ - register8_t reserved_0x05; - register8_t MCUCR; /* MCU Control */ - register8_t reserved_0x07; - register8_t EVSYSLOCK; /* Event System Lock */ - register8_t AWEXLOCK; /* AWEX Lock */ - register8_t reserved_0x0A; - register8_t reserved_0x0B; -} MCU_t; - - -/* --------------------------------------------------------------------------- -PMIC - Programmable Multi-level Interrupt Controller --------------------------------------------------------------------------- -*/ - -/* Programmable Multi-level Interrupt Controller */ -typedef struct PMIC_struct -{ - register8_t STATUS; /* Status Register */ - register8_t INTPRI; /* Interrupt Priority */ - register8_t CTRL; /* Control Register */ -} PMIC_t; - - -/* --------------------------------------------------------------------------- -CRC - Cyclic Redundancy Checker --------------------------------------------------------------------------- -*/ - -/* Cyclic Redundancy Checker */ -typedef struct CRC_struct -{ - register8_t CTRL; /* Control Register */ - register8_t STATUS; /* Status Register */ - register8_t reserved_0x02; - register8_t DATAIN; /* Data Input */ - register8_t CHECKSUM0; /* Checksum byte 0 */ - register8_t CHECKSUM1; /* Checksum byte 1 */ - register8_t CHECKSUM2; /* Checksum byte 2 */ - register8_t CHECKSUM3; /* Checksum byte 3 */ -} CRC_t; - -/* Reset */ -typedef enum CRC_RESET_enum -{ - CRC_RESET_NO_gc = (0x00<<6), /* No Reset */ - CRC_RESET_RESET0_gc = (0x02<<6), /* Reset CRC with CHECKSUM to all zeros */ - CRC_RESET_RESET1_gc = (0x03<<6), /* Reset CRC with CHECKSUM to all ones */ -} CRC_RESET_t; - -/* Input Source */ -typedef enum CRC_SOURCE_enum -{ - CRC_SOURCE_DISABLE_gc = (0x00<<0), /* Disabled */ - CRC_SOURCE_IO_gc = (0x01<<0), /* I/O Interface */ - CRC_SOURCE_FLASH_gc = (0x02<<0), /* Flash */ - CRC_SOURCE_DMAC0_gc = (0x04<<0), /* DMAC Channel 0 */ - CRC_SOURCE_DMAC1_gc = (0x05<<0), /* DMAC Channel 1 */ - CRC_SOURCE_DMAC2_gc = (0x06<<0), /* DMAC Channel 2 */ - CRC_SOURCE_DMAC3_gc = (0x07<<0), /* DMAC Channel 3 */ -} CRC_SOURCE_t; - - -/* --------------------------------------------------------------------------- -EVSYS - Event System --------------------------------------------------------------------------- -*/ - -/* Event System */ -typedef struct EVSYS_struct -{ - register8_t CH0MUX; /* Event Channel 0 Multiplexer */ - register8_t CH1MUX; /* Event Channel 1 Multiplexer */ - register8_t CH2MUX; /* Event Channel 2 Multiplexer */ - register8_t CH3MUX; /* Event Channel 3 Multiplexer */ - register8_t reserved_0x04; - register8_t reserved_0x05; - register8_t reserved_0x06; - register8_t reserved_0x07; - register8_t CH0CTRL; /* Channel 0 Control Register */ - register8_t CH1CTRL; /* Channel 1 Control Register */ - register8_t CH2CTRL; /* Channel 2 Control Register */ - register8_t CH3CTRL; /* Channel 3 Control Register */ - register8_t reserved_0x0C; - register8_t reserved_0x0D; - register8_t reserved_0x0E; - register8_t reserved_0x0F; - register8_t STROBE; /* Event Strobe */ - register8_t DATA; /* Event Data */ -} EVSYS_t; - -/* Quadrature Decoder Index Recognition Mode */ -typedef enum EVSYS_QDIRM_enum -{ - EVSYS_QDIRM_00_gc = (0x00<<5), /* QDPH0 = 0, QDPH90 = 0 */ - EVSYS_QDIRM_01_gc = (0x01<<5), /* QDPH0 = 0, QDPH90 = 1 */ - EVSYS_QDIRM_10_gc = (0x02<<5), /* QDPH0 = 1, QDPH90 = 0 */ - EVSYS_QDIRM_11_gc = (0x03<<5), /* QDPH0 = 1, QDPH90 = 1 */ -} EVSYS_QDIRM_t; - -/* Digital filter coefficient */ -typedef enum EVSYS_DIGFILT_enum -{ - EVSYS_DIGFILT_1SAMPLE_gc = (0x00<<0), /* 1 SAMPLE */ - EVSYS_DIGFILT_2SAMPLES_gc = (0x01<<0), /* 2 SAMPLES */ - EVSYS_DIGFILT_3SAMPLES_gc = (0x02<<0), /* 3 SAMPLES */ - EVSYS_DIGFILT_4SAMPLES_gc = (0x03<<0), /* 4 SAMPLES */ - EVSYS_DIGFILT_5SAMPLES_gc = (0x04<<0), /* 5 SAMPLES */ - EVSYS_DIGFILT_6SAMPLES_gc = (0x05<<0), /* 6 SAMPLES */ - EVSYS_DIGFILT_7SAMPLES_gc = (0x06<<0), /* 7 SAMPLES */ - EVSYS_DIGFILT_8SAMPLES_gc = (0x07<<0), /* 8 SAMPLES */ -} EVSYS_DIGFILT_t; - -/* Event Channel multiplexer input selection */ -typedef enum EVSYS_CHMUX_enum -{ - EVSYS_CHMUX_OFF_gc = (0x00<<0), /* Off */ - EVSYS_CHMUX_RTC_OVF_gc = (0x08<<0), /* RTC Overflow */ - EVSYS_CHMUX_RTC_CMP_gc = (0x09<<0), /* RTC Compare Match */ - EVSYS_CHMUX_ACA_CH0_gc = (0x10<<0), /* Analog Comparator A Channel 0 */ - EVSYS_CHMUX_ACA_CH1_gc = (0x11<<0), /* Analog Comparator A Channel 1 */ - EVSYS_CHMUX_ACA_WIN_gc = (0x12<<0), /* Analog Comparator A Window */ - EVSYS_CHMUX_ADCA_CH0_gc = (0x20<<0), /* ADC A Channel 0 */ - EVSYS_CHMUX_PORTA_PIN0_gc = (0x50<<0), /* Port A, Pin0 */ - EVSYS_CHMUX_PORTA_PIN1_gc = (0x51<<0), /* Port A, Pin1 */ - EVSYS_CHMUX_PORTA_PIN2_gc = (0x52<<0), /* Port A, Pin2 */ - EVSYS_CHMUX_PORTA_PIN3_gc = (0x53<<0), /* Port A, Pin3 */ - EVSYS_CHMUX_PORTA_PIN4_gc = (0x54<<0), /* Port A, Pin4 */ - EVSYS_CHMUX_PORTA_PIN5_gc = (0x55<<0), /* Port A, Pin5 */ - EVSYS_CHMUX_PORTA_PIN6_gc = (0x56<<0), /* Port A, Pin6 */ - EVSYS_CHMUX_PORTA_PIN7_gc = (0x57<<0), /* Port A, Pin7 */ - EVSYS_CHMUX_PORTB_PIN0_gc = (0x58<<0), /* Port B, Pin0 */ - EVSYS_CHMUX_PORTB_PIN1_gc = (0x59<<0), /* Port B, Pin1 */ - EVSYS_CHMUX_PORTB_PIN2_gc = (0x5A<<0), /* Port B, Pin2 */ - EVSYS_CHMUX_PORTB_PIN3_gc = (0x5B<<0), /* Port B, Pin3 */ - EVSYS_CHMUX_PORTB_PIN4_gc = (0x5C<<0), /* Port B, Pin4 */ - EVSYS_CHMUX_PORTB_PIN5_gc = (0x5D<<0), /* Port B, Pin5 */ - EVSYS_CHMUX_PORTB_PIN6_gc = (0x5E<<0), /* Port B, Pin6 */ - EVSYS_CHMUX_PORTB_PIN7_gc = (0x5F<<0), /* Port B, Pin7 */ - EVSYS_CHMUX_PORTC_PIN0_gc = (0x60<<0), /* Port C, Pin0 */ - EVSYS_CHMUX_PORTC_PIN1_gc = (0x61<<0), /* Port C, Pin1 */ - EVSYS_CHMUX_PORTC_PIN2_gc = (0x62<<0), /* Port C, Pin2 */ - EVSYS_CHMUX_PORTC_PIN3_gc = (0x63<<0), /* Port C, Pin3 */ - EVSYS_CHMUX_PORTC_PIN4_gc = (0x64<<0), /* Port C, Pin4 */ - EVSYS_CHMUX_PORTC_PIN5_gc = (0x65<<0), /* Port C, Pin5 */ - EVSYS_CHMUX_PORTC_PIN6_gc = (0x66<<0), /* Port C, Pin6 */ - EVSYS_CHMUX_PORTC_PIN7_gc = (0x67<<0), /* Port C, Pin7 */ - EVSYS_CHMUX_PORTD_PIN0_gc = (0x68<<0), /* Port D, Pin0 */ - EVSYS_CHMUX_PORTD_PIN1_gc = (0x69<<0), /* Port D, Pin1 */ - EVSYS_CHMUX_PORTD_PIN2_gc = (0x6A<<0), /* Port D, Pin2 */ - EVSYS_CHMUX_PORTD_PIN3_gc = (0x6B<<0), /* Port D, Pin3 */ - EVSYS_CHMUX_PORTD_PIN4_gc = (0x6C<<0), /* Port D, Pin4 */ - EVSYS_CHMUX_PORTD_PIN5_gc = (0x6D<<0), /* Port D, Pin5 */ - EVSYS_CHMUX_PORTD_PIN6_gc = (0x6E<<0), /* Port D, Pin6 */ - EVSYS_CHMUX_PORTD_PIN7_gc = (0x6F<<0), /* Port D, Pin7 */ - EVSYS_CHMUX_PORTE_PIN0_gc = (0x70<<0), /* Port E, Pin0 */ - EVSYS_CHMUX_PORTE_PIN1_gc = (0x71<<0), /* Port E, Pin1 */ - EVSYS_CHMUX_PORTE_PIN2_gc = (0x72<<0), /* Port E, Pin2 */ - EVSYS_CHMUX_PORTE_PIN3_gc = (0x73<<0), /* Port E, Pin3 */ - EVSYS_CHMUX_PORTE_PIN4_gc = (0x74<<0), /* Port E, Pin4 */ - EVSYS_CHMUX_PORTE_PIN5_gc = (0x75<<0), /* Port E, Pin5 */ - EVSYS_CHMUX_PORTE_PIN6_gc = (0x76<<0), /* Port E, Pin6 */ - EVSYS_CHMUX_PORTE_PIN7_gc = (0x77<<0), /* Port E, Pin7 */ - EVSYS_CHMUX_PORTF_PIN0_gc = (0x78<<0), /* Port F, Pin0 */ - EVSYS_CHMUX_PORTF_PIN1_gc = (0x79<<0), /* Port F, Pin1 */ - EVSYS_CHMUX_PORTF_PIN2_gc = (0x7A<<0), /* Port F, Pin2 */ - EVSYS_CHMUX_PORTF_PIN3_gc = (0x7B<<0), /* Port F, Pin3 */ - EVSYS_CHMUX_PORTF_PIN4_gc = (0x7C<<0), /* Port F, Pin4 */ - EVSYS_CHMUX_PORTF_PIN5_gc = (0x7D<<0), /* Port F, Pin5 */ - EVSYS_CHMUX_PORTF_PIN6_gc = (0x7E<<0), /* Port F, Pin6 */ - EVSYS_CHMUX_PORTF_PIN7_gc = (0x7F<<0), /* Port F, Pin7 */ - EVSYS_CHMUX_PRESCALER_1_gc = (0x80<<0), /* Prescaler, divide by 1 */ - EVSYS_CHMUX_PRESCALER_2_gc = (0x81<<0), /* Prescaler, divide by 2 */ - EVSYS_CHMUX_PRESCALER_4_gc = (0x82<<0), /* Prescaler, divide by 4 */ - EVSYS_CHMUX_PRESCALER_8_gc = (0x83<<0), /* Prescaler, divide by 8 */ - EVSYS_CHMUX_PRESCALER_16_gc = (0x84<<0), /* Prescaler, divide by 16 */ - EVSYS_CHMUX_PRESCALER_32_gc = (0x85<<0), /* Prescaler, divide by 32 */ - EVSYS_CHMUX_PRESCALER_64_gc = (0x86<<0), /* Prescaler, divide by 64 */ - EVSYS_CHMUX_PRESCALER_128_gc = (0x87<<0), /* Prescaler, divide by 128 */ - EVSYS_CHMUX_PRESCALER_256_gc = (0x88<<0), /* Prescaler, divide by 256 */ - EVSYS_CHMUX_PRESCALER_512_gc = (0x89<<0), /* Prescaler, divide by 512 */ - EVSYS_CHMUX_PRESCALER_1024_gc = (0x8A<<0), /* Prescaler, divide by 1024 */ - EVSYS_CHMUX_PRESCALER_2048_gc = (0x8B<<0), /* Prescaler, divide by 2048 */ - EVSYS_CHMUX_PRESCALER_4096_gc = (0x8C<<0), /* Prescaler, divide by 4096 */ - EVSYS_CHMUX_PRESCALER_8192_gc = (0x8D<<0), /* Prescaler, divide by 8192 */ - EVSYS_CHMUX_PRESCALER_16384_gc = (0x8E<<0), /* Prescaler, divide by 16384 */ - EVSYS_CHMUX_PRESCALER_32768_gc = (0x8F<<0), /* Prescaler, divide by 32768 */ - EVSYS_CHMUX_TCC0_OVF_gc = (0xC0<<0), /* Timer/Counter C0 Overflow */ - EVSYS_CHMUX_TCC0_ERR_gc = (0xC1<<0), /* Timer/Counter C0 Error */ - EVSYS_CHMUX_TCC0_CCA_gc = (0xC4<<0), /* Timer/Counter C0 Compare or Capture A */ - EVSYS_CHMUX_TCC0_CCB_gc = (0xC5<<0), /* Timer/Counter C0 Compare or Capture B */ - EVSYS_CHMUX_TCC0_CCC_gc = (0xC6<<0), /* Timer/Counter C0 Compare or Capture C */ - EVSYS_CHMUX_TCC0_CCD_gc = (0xC7<<0), /* Timer/Counter C0 Compare or Capture D */ - EVSYS_CHMUX_TCC1_OVF_gc = (0xC8<<0), /* Timer/Counter C1 Overflow */ - EVSYS_CHMUX_TCC1_ERR_gc = (0xC9<<0), /* Timer/Counter C1 Error */ - EVSYS_CHMUX_TCC1_CCA_gc = (0xCC<<0), /* Timer/Counter C1 Compare or Capture A */ - EVSYS_CHMUX_TCC1_CCB_gc = (0xCD<<0), /* Timer/Counter C1 Compare or Capture B */ - EVSYS_CHMUX_TCD0_OVF_gc = (0xD0<<0), /* Timer/Counter D0 Overflow */ - EVSYS_CHMUX_TCD0_ERR_gc = (0xD1<<0), /* Timer/Counter D0 Error */ - EVSYS_CHMUX_TCD0_CCA_gc = (0xD4<<0), /* Timer/Counter D0 Compare or Capture A */ - EVSYS_CHMUX_TCD0_CCB_gc = (0xD5<<0), /* Timer/Counter D0 Compare or Capture B */ - EVSYS_CHMUX_TCD0_CCC_gc = (0xD6<<0), /* Timer/Counter D0 Compare or Capture C */ - EVSYS_CHMUX_TCD0_CCD_gc = (0xD7<<0), /* Timer/Counter D0 Compare or Capture D */ - EVSYS_CHMUX_TCD1_OVF_gc = (0xD8<<0), /* Timer/Counter D1 Overflow */ - EVSYS_CHMUX_TCD1_ERR_gc = (0xD9<<0), /* Timer/Counter D1 Error */ - EVSYS_CHMUX_TCD1_CCA_gc = (0xDC<<0), /* Timer/Counter D1 Compare or Capture A */ - EVSYS_CHMUX_TCD1_CCB_gc = (0xDD<<0), /* Timer/Counter D1 Compare or Capture B */ - EVSYS_CHMUX_TCE0_OVF_gc = (0xE0<<0), /* Timer/Counter E0 Overflow */ - EVSYS_CHMUX_TCE0_ERR_gc = (0xE1<<0), /* Timer/Counter E0 Error */ - EVSYS_CHMUX_TCE0_CCA_gc = (0xE4<<0), /* Timer/Counter E0 Compare or Capture A */ - EVSYS_CHMUX_TCE0_CCB_gc = (0xE5<<0), /* Timer/Counter E0 Compare or Capture B */ - EVSYS_CHMUX_TCE0_CCC_gc = (0xE6<<0), /* Timer/Counter E0 Compare or Capture C */ - EVSYS_CHMUX_TCE0_CCD_gc = (0xE7<<0), /* Timer/Counter E0 Compare or Capture D */ - EVSYS_CHMUX_TCE1_OVF_gc = (0xE8<<0), /* Timer/Counter E1 Overflow */ - EVSYS_CHMUX_TCE1_ERR_gc = (0xE9<<0), /* Timer/Counter E1 Error */ - EVSYS_CHMUX_TCE1_CCA_gc = (0xEC<<0), /* Timer/Counter E1 Compare or Capture A */ - EVSYS_CHMUX_TCE1_CCB_gc = (0xED<<0), /* Timer/Counter E1 Compare or Capture B */ - EVSYS_CHMUX_TCF0_OVF_gc = (0xF0<<0), /* Timer/Counter F0 Overflow */ - EVSYS_CHMUX_TCF0_ERR_gc = (0xF1<<0), /* Timer/Counter F0 Error */ - EVSYS_CHMUX_TCF0_CCA_gc = (0xF4<<0), /* Timer/Counter F0 Compare or Capture A */ - EVSYS_CHMUX_TCF0_CCB_gc = (0xF5<<0), /* Timer/Counter F0 Compare or Capture B */ - EVSYS_CHMUX_TCF0_CCC_gc = (0xF6<<0), /* Timer/Counter F0 Compare or Capture C */ - EVSYS_CHMUX_TCF0_CCD_gc = (0xF7<<0), /* Timer/Counter F0 Compare or Capture D */ - EVSYS_CHMUX_TCF1_OVF_gc = (0xF8<<0), /* Timer/Counter F1 Overflow */ - EVSYS_CHMUX_TCF1_ERR_gc = (0xF9<<0), /* Timer/Counter F1 Error */ - EVSYS_CHMUX_TCF1_CCA_gc = (0xFC<<0), /* Timer/Counter F1 Compare or Capture A */ - EVSYS_CHMUX_TCF1_CCB_gc = (0xFD<<0), /* Timer/Counter F1 Compare or Capture B */ -} EVSYS_CHMUX_t; - - -/* --------------------------------------------------------------------------- -NVM - Non Volatile Memory Controller --------------------------------------------------------------------------- -*/ - -/* Non-volatile Memory Controller */ -typedef struct NVM_struct -{ - register8_t ADDR0; /* Address Register 0 */ - register8_t ADDR1; /* Address Register 1 */ - register8_t ADDR2; /* Address Register 2 */ - register8_t reserved_0x03; - register8_t DATA0; /* Data Register 0 */ - register8_t DATA1; /* Data Register 1 */ - register8_t DATA2; /* Data Register 2 */ - register8_t reserved_0x07; - register8_t reserved_0x08; - register8_t reserved_0x09; - register8_t CMD; /* Command */ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t INTCTRL; /* Interrupt Control */ - register8_t reserved_0x0E; - register8_t STATUS; /* Status */ - register8_t LOCK_BITS; /* Lock Bits */ -} NVM_t; - -/* --------------------------------------------------------------------------- -NVM - Non Volatile Memory Controller --------------------------------------------------------------------------- -*/ - -/* Lock Bits */ -typedef struct NVM_LOCKBITS_struct -{ - register8_t LOCKBITS; /* Lock Bits */ -} NVM_LOCKBITS_t; - -/* --------------------------------------------------------------------------- -NVM - Non Volatile Memory Controller --------------------------------------------------------------------------- -*/ - -/* Fuses */ -typedef struct NVM_FUSES_struct -{ - register8_t FUSEBYTE0; /* User ID */ - register8_t FUSEBYTE1; /* Watchdog Configuration */ - register8_t FUSEBYTE2; /* Reset Configuration */ - register8_t reserved_0x03; - register8_t FUSEBYTE4; /* Start-up Configuration */ - register8_t FUSEBYTE5; /* EESAVE and BOD Level */ -} NVM_FUSES_t; - -/* --------------------------------------------------------------------------- -NVM - Non Volatile Memory Controller --------------------------------------------------------------------------- -*/ - -/* Production Signatures */ -typedef struct NVM_PROD_SIGNATURES_struct -{ - register8_t RCOSC2M; /* RCOSC 2MHz Calibration Value */ - register8_t reserved_0x01; - register8_t RCOSC32K; /* RCOSC 32kHz Calibration Value */ - register8_t RCOSC32M; /* RCOSC 32MHz Calibration Value */ - register8_t reserved_0x04; - register8_t reserved_0x05; - register8_t reserved_0x06; - register8_t reserved_0x07; - register8_t LOTNUM0; /* Lot Number Byte 0, ASCII */ - register8_t LOTNUM1; /* Lot Number Byte 1, ASCII */ - register8_t LOTNUM2; /* Lot Number Byte 2, ASCII */ - register8_t LOTNUM3; /* Lot Number Byte 3, ASCII */ - register8_t LOTNUM4; /* Lot Number Byte 4, ASCII */ - register8_t LOTNUM5; /* Lot Number Byte 5, ASCII */ - register8_t reserved_0x0E; - register8_t reserved_0x0F; - register8_t WAFNUM; /* Wafer Number */ - register8_t reserved_0x11; - register8_t COORDX0; /* Wafer Coordinate X Byte 0 */ - register8_t COORDX1; /* Wafer Coordinate X Byte 1 */ - register8_t COORDY0; /* Wafer Coordinate Y Byte 0 */ - register8_t COORDY1; /* Wafer Coordinate Y Byte 1 */ - register8_t reserved_0x16; - register8_t reserved_0x17; - register8_t reserved_0x18; - register8_t reserved_0x19; - register8_t reserved_0x1A; - register8_t reserved_0x1B; - register8_t reserved_0x1C; - register8_t reserved_0x1D; - register8_t reserved_0x1E; - register8_t reserved_0x1F; - register8_t ADCACAL0; /* ADCA Calibration Byte 0 */ - register8_t ADCACAL1; /* ADCA Calibration Byte 1 */ - register8_t reserved_0x22; - register8_t reserved_0x23; - register8_t ADCBCAL0; /* ADCB Calibration Byte 0 */ - register8_t ADCBCAL1; /* ADCB Calibration Byte 1 */ - register8_t reserved_0x26; - register8_t reserved_0x27; - register8_t reserved_0x28; - register8_t reserved_0x29; - register8_t reserved_0x2A; - register8_t reserved_0x2B; - register8_t reserved_0x2C; - register8_t reserved_0x2D; - register8_t TEMPSENSE0; /* Temperature Sensor Calibration Byte 0 */ - register8_t TEMPSENSE1; /* Temperature Sensor Calibration Byte 0 */ - register8_t DACAOFFCAL; /* DACA Calibration Byte 0 */ - register8_t DACAGAINCAL; /* DACA Calibration Byte 1 */ - register8_t DACBOFFCAL; /* DACB Calibration Byte 0 */ - register8_t DACBGAINCAL; /* DACB Calibration Byte 1 */ - register8_t reserved_0x34; - register8_t reserved_0x35; - register8_t reserved_0x36; - register8_t reserved_0x37; - register8_t reserved_0x38; - register8_t reserved_0x39; - register8_t reserved_0x3A; - register8_t reserved_0x3B; - register8_t reserved_0x3C; - register8_t reserved_0x3D; - register8_t reserved_0x3E; -} NVM_PROD_SIGNATURES_t; - -/* NVM Command */ -typedef enum NVM_CMD_enum -{ - NVM_CMD_NO_OPERATION_gc = (0x00<<0), /* Noop/Ordinary LPM */ - NVM_CMD_READ_CALIB_ROW_gc = (0x02<<0), /* Read calibration row */ - NVM_CMD_READ_USER_SIG_ROW_gc = (0x01<<0), /* Read user signature row */ - NVM_CMD_READ_EEPROM_gc = (0x06<<0), /* Read EEPROM */ - NVM_CMD_READ_FUSES_gc = (0x07<<0), /* Read fuse byte */ - NVM_CMD_WRITE_LOCK_BITS_gc = (0x08<<0), /* Write lock bits */ - NVM_CMD_ERASE_USER_SIG_ROW_gc = (0x18<<0), /* Erase user signature row */ - NVM_CMD_WRITE_USER_SIG_ROW_gc = (0x1A<<0), /* Write user signature row */ - NVM_CMD_ERASE_APP_gc = (0x20<<0), /* Erase Application Section */ - NVM_CMD_ERASE_APP_PAGE_gc = (0x22<<0), /* Erase Application Section page */ - NVM_CMD_LOAD_FLASH_BUFFER_gc = (0x23<<0), /* Load Flash page buffer */ - NVM_CMD_WRITE_APP_PAGE_gc = (0x24<<0), /* Write Application Section page */ - NVM_CMD_ERASE_WRITE_APP_PAGE_gc = (0x25<<0), /* Erase-and-write Application Section page */ - NVM_CMD_ERASE_FLASH_BUFFER_gc = (0x26<<0), /* Erase/flush Flash page buffer */ - NVM_CMD_ERASE_BOOT_PAGE_gc = (0x2A<<0), /* Erase Boot Section page */ - NVM_CMD_WRITE_BOOT_PAGE_gc = (0x2C<<0), /* Write Boot Section page */ - NVM_CMD_ERASE_WRITE_BOOT_PAGE_gc = (0x2D<<0), /* Erase-and-write Boot Section page */ - NVM_CMD_ERASE_EEPROM_gc = (0x30<<0), /* Erase EEPROM */ - NVM_CMD_ERASE_EEPROM_PAGE_gc = (0x32<<0), /* Erase EEPROM page */ - NVM_CMD_LOAD_EEPROM_BUFFER_gc = (0x33<<0), /* Load EEPROM page buffer */ - NVM_CMD_WRITE_EEPROM_PAGE_gc = (0x34<<0), /* Write EEPROM page */ - NVM_CMD_ERASE_WRITE_EEPROM_PAGE_gc = (0x35<<0), /* Erase-and-write EEPROM page */ - NVM_CMD_ERASE_EEPROM_BUFFER_gc = (0x36<<0), /* Erase/flush EEPROM page buffer */ - NVM_CMD_APP_CRC_gc = (0x38<<0), /* Generate Application section CRC */ - NVM_CMD_BOOT_CRC_gc = (0x39<<0), /* Generate Boot Section CRC */ - NVM_CMD_FLASH_RANGE_CRC_gc = (0x3A<<0), /* Generate Flash Range CRC */ -} NVM_CMD_t; - -/* SPM ready interrupt level */ -typedef enum NVM_SPMLVL_enum -{ - NVM_SPMLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ - NVM_SPMLVL_LO_gc = (0x01<<2), /* Low level */ - NVM_SPMLVL_MED_gc = (0x02<<2), /* Medium level */ - NVM_SPMLVL_HI_gc = (0x03<<2), /* High level */ -} NVM_SPMLVL_t; - -/* EEPROM ready interrupt level */ -typedef enum NVM_EELVL_enum -{ - NVM_EELVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ - NVM_EELVL_LO_gc = (0x01<<0), /* Low level */ - NVM_EELVL_MED_gc = (0x02<<0), /* Medium level */ - NVM_EELVL_HI_gc = (0x03<<0), /* High level */ -} NVM_EELVL_t; - -/* Boot lock bits - boot setcion */ -typedef enum NVM_BLBB_enum -{ - NVM_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ - NVM_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ - NVM_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ - NVM_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ -} NVM_BLBB_t; - -/* Boot lock bits - application section */ -typedef enum NVM_BLBA_enum -{ - NVM_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ - NVM_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ - NVM_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ - NVM_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ -} NVM_BLBA_t; - -/* Boot lock bits - application table section */ -typedef enum NVM_BLBAT_enum -{ - NVM_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ - NVM_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ - NVM_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ - NVM_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ -} NVM_BLBAT_t; - -/* Lock bits */ -typedef enum NVM_LB_enum -{ - NVM_LB_NOLOCK_gc = (0x03<<0), /* No locks */ - NVM_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ - NVM_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ -} NVM_LB_t; - -/* Boot Loader Section Reset Vector */ -typedef enum BOOTRST_enum -{ - BOOTRST_BOOTLDR_gc = (0x00<<6), /* Boot Loader Reset */ - BOOTRST_APPLICATION_gc = (0x01<<6), /* Application Reset */ -} BOOTRST_t; - -/* BOD operation */ -typedef enum BOD_enum -{ - BOD_INSAMPLEDMODE_gc = (0x01<<0), /* BOD enabled in sampled mode */ - BOD_CONTINOUSLY_gc = (0x02<<0), /* BOD enabled continuously */ - BOD_DISABLED_gc = (0x03<<0), /* BOD Disabled */ -} BOD_t; - -/* Watchdog (Window) Timeout Period */ -typedef enum WD_enum -{ - WD_8CLK_gc = (0x00<<4), /* 8 cycles (8ms @ 3.3V) */ - WD_16CLK_gc = (0x01<<4), /* 16 cycles (16ms @ 3.3V) */ - WD_32CLK_gc = (0x02<<4), /* 32 cycles (32ms @ 3.3V) */ - WD_64CLK_gc = (0x03<<4), /* 64 cycles (64ms @ 3.3V) */ - WD_128CLK_gc = (0x04<<4), /* 128 cycles (0.125s @ 3.3V) */ - WD_256CLK_gc = (0x05<<4), /* 256 cycles (0.25s @ 3.3V) */ - WD_512CLK_gc = (0x06<<4), /* 512 cycles (0.5s @ 3.3V) */ - WD_1KCLK_gc = (0x07<<4), /* 1K cycles (1s @ 3.3V) */ - WD_2KCLK_gc = (0x08<<4), /* 2K cycles (2s @ 3.3V) */ - WD_4KCLK_gc = (0x09<<4), /* 4K cycles (4s @ 3.3V) */ - WD_8KCLK_gc = (0x0A<<4), /* 8K cycles (8s @ 3.3V) */ -} WD_t; - -/* Start-up Time */ -typedef enum SUT_enum -{ - SUT_0MS_gc = (0x03<<2), /* 0 ms */ - SUT_4MS_gc = (0x01<<2), /* 4 ms */ - SUT_64MS_gc = (0x00<<2), /* 64 ms */ -} SUT_t; - -/* Brown Out Detection Voltage Level */ -typedef enum BODLVL_enum -{ - BODLVL_1V6_gc = (0x07<<0), /* 1.6 V */ - BODLVL_1V8_gc = (0x06<<0), /* 1.8 V */ - BODLVL_2V0_gc = (0x05<<0), /* 2.0 V */ - BODLVL_2V2_gc = (0x04<<0), /* 2.2 V */ - BODLVL_2V4_gc = (0x03<<0), /* 2.4 V */ - BODLVL_2V6_gc = (0x02<<0), /* 2.6 V */ - BODLVL_2V8_gc = (0x01<<0), /* 2.8 V */ - BODLVL_3V0_gc = (0x00<<0), /* 3.0 V */ -} BODLVL_t; - - -/* --------------------------------------------------------------------------- -AC - Analog Comparator --------------------------------------------------------------------------- -*/ - -/* Analog Comparator */ -typedef struct AC_struct -{ - register8_t AC0CTRL; /* Comparator 0 Control */ - register8_t AC1CTRL; /* Comparator 1 Control */ - register8_t AC0MUXCTRL; /* Comparator 0 MUX Control */ - register8_t AC1MUXCTRL; /* Comparator 1 MUX Control */ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t WINCTRL; /* Window Mode Control */ - register8_t STATUS; /* Status */ -} AC_t; - -/* Interrupt mode */ -typedef enum AC_INTMODE_enum -{ - AC_INTMODE_BOTHEDGES_gc = (0x00<<6), /* Interrupt on both edges */ - AC_INTMODE_FALLING_gc = (0x02<<6), /* Interrupt on falling edge */ - AC_INTMODE_RISING_gc = (0x03<<6), /* Interrupt on rising edge */ -} AC_INTMODE_t; - -/* Interrupt level */ -typedef enum AC_INTLVL_enum -{ - AC_INTLVL_OFF_gc = (0x00<<4), /* Interrupt disabled */ - AC_INTLVL_LO_gc = (0x01<<4), /* Low level */ - AC_INTLVL_MED_gc = (0x02<<4), /* Medium level */ - AC_INTLVL_HI_gc = (0x03<<4), /* High level */ -} AC_INTLVL_t; - -/* Hysteresis mode selection */ -typedef enum AC_HYSMODE_enum -{ - AC_HYSMODE_NO_gc = (0x00<<1), /* No hysteresis */ - AC_HYSMODE_SMALL_gc = (0x01<<1), /* Small hysteresis */ - AC_HYSMODE_LARGE_gc = (0x02<<1), /* Large hysteresis */ -} AC_HYSMODE_t; - -/* Positive input multiplexer selection */ -typedef enum AC_MUXPOS_enum -{ - AC_MUXPOS_PIN0_gc = (0x00<<3), /* Pin 0 */ - AC_MUXPOS_PIN1_gc = (0x01<<3), /* Pin 1 */ - AC_MUXPOS_PIN2_gc = (0x02<<3), /* Pin 2 */ - AC_MUXPOS_PIN3_gc = (0x03<<3), /* Pin 3 */ - AC_MUXPOS_PIN4_gc = (0x04<<3), /* Pin 4 */ - AC_MUXPOS_PIN5_gc = (0x05<<3), /* Pin 5 */ - AC_MUXPOS_PIN6_gc = (0x06<<3), /* Pin 6 */ - AC_MUXPOS_DAC_gc = (0x07<<3), /* DAC output */ -} AC_MUXPOS_t; - -/* Negative input multiplexer selection */ -typedef enum AC_MUXNEG_enum -{ - AC_MUXNEG_PIN0_gc = (0x00<<0), /* Pin 0 */ - AC_MUXNEG_PIN1_gc = (0x01<<0), /* Pin 1 */ - AC_MUXNEG_PIN3_gc = (0x02<<0), /* Pin 3 */ - AC_MUXNEG_PIN5_gc = (0x03<<0), /* Pin 5 */ - AC_MUXNEG_PIN7_gc = (0x04<<0), /* Pin 7 */ - AC_MUXNEG_DAC_gc = (0x05<<0), /* DAC output */ - AC_MUXNEG_BANDGAP_gc = (0x06<<0), /* Bandgap Reference */ - AC_MUXNEG_SCALER_gc = (0x07<<0), /* Internal voltage scaler */ -} AC_MUXNEG_t; - -/* Windows interrupt mode */ -typedef enum AC_WINTMODE_enum -{ - AC_WINTMODE_ABOVE_gc = (0x00<<2), /* Interrupt on above window */ - AC_WINTMODE_INSIDE_gc = (0x01<<2), /* Interrupt on inside window */ - AC_WINTMODE_BELOW_gc = (0x02<<2), /* Interrupt on below window */ - AC_WINTMODE_OUTSIDE_gc = (0x03<<2), /* Interrupt on outside window */ -} AC_WINTMODE_t; - -/* Window interrupt level */ -typedef enum AC_WINTLVL_enum -{ - AC_WINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ - AC_WINTLVL_LO_gc = (0x01<<0), /* Low priority */ - AC_WINTLVL_MED_gc = (0x02<<0), /* Medium priority */ - AC_WINTLVL_HI_gc = (0x03<<0), /* High priority */ -} AC_WINTLVL_t; - -/* Window mode state */ -typedef enum AC_WSTATE_enum -{ - AC_WSTATE_ABOVE_gc = (0x00<<6), /* Signal above window */ - AC_WSTATE_INSIDE_gc = (0x01<<6), /* Signal inside window */ - AC_WSTATE_BELOW_gc = (0x02<<6), /* Signal below window */ -} AC_WSTATE_t; - - -/* --------------------------------------------------------------------------- -ADC - Analog/Digital Converter --------------------------------------------------------------------------- -*/ - -/* ADC Channel */ -typedef struct ADC_CH_struct -{ - register8_t CTRL; /* Control Register */ - register8_t MUXCTRL; /* MUX Control */ - register8_t INTCTRL; /* Channel Interrupt Control */ - register8_t INTFLAGS; /* Interrupt Flags */ - _WORDREGISTER(RES); /* Channel Result */ - register8_t reserved_0x6; - register8_t reserved_0x7; -} ADC_CH_t; - -/* --------------------------------------------------------------------------- -ADC - Analog/Digital Converter --------------------------------------------------------------------------- -*/ - -/* Analog-to-Digital Converter */ -typedef struct ADC_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t REFCTRL; /* Reference Control */ - register8_t EVCTRL; /* Event Control */ - register8_t PRESCALER; /* Clock Prescaler */ - register8_t reserved_0x05; - register8_t INTFLAGS; /* Interrupt Flags */ - register8_t reserved_0x07; - register8_t reserved_0x08; - register8_t reserved_0x09; - register8_t reserved_0x0A; - register8_t reserved_0x0B; - _WORDREGISTER(CAL); /* Calibration Value */ - register8_t reserved_0x0E; - register8_t reserved_0x0F; - _WORDREGISTER(CH0RES); /* Channel 0 Result */ - register8_t reserved_0x12; - register8_t reserved_0x13; - register8_t reserved_0x14; - register8_t reserved_0x15; - register8_t reserved_0x16; - register8_t reserved_0x17; - _WORDREGISTER(CMP); /* Compare Value */ - register8_t reserved_0x1A; - register8_t reserved_0x1B; - register8_t reserved_0x1C; - register8_t reserved_0x1D; - register8_t reserved_0x1E; - register8_t reserved_0x1F; - ADC_CH_t CH0; /* ADC Channel 0 */ -} ADC_t; - -/* Current Limitation */ -typedef enum ADC_CURRLIMIT_enum -{ - ADC_CURRLIMIT_NO_gc = (0x00<<5), /* No current limit, 300ksps max sampling rate */ - ADC_CURRLIMIT_LOW_gc = (0x01<<5), /* Low current limit, 225ksps max sampling rate */ - ADC_CURRLIMIT_MED_gc = (0x02<<5), /* Medium current limit, 150ksps max sampling rate */ - ADC_CURRLIMIT_HIGH_gc = (0x03<<5), /* High current limit, 75ksps max sampling rate */ -} ADC_CURRLIMIT_t; - -/* Positive input multiplexer selection */ -typedef enum ADC_CH_MUXPOS_enum -{ - ADC_CH_MUXPOS_PIN0_gc = (0x00<<3), /* Input pin 0 */ - ADC_CH_MUXPOS_PIN1_gc = (0x01<<3), /* Input pin 1 */ - ADC_CH_MUXPOS_PIN2_gc = (0x02<<3), /* Input pin 2 */ - ADC_CH_MUXPOS_PIN3_gc = (0x03<<3), /* Input pin 3 */ - ADC_CH_MUXPOS_PIN4_gc = (0x04<<3), /* Input pin 4 */ - ADC_CH_MUXPOS_PIN5_gc = (0x05<<3), /* Input pin 5 */ - ADC_CH_MUXPOS_PIN6_gc = (0x06<<3), /* Input pin 6 */ - ADC_CH_MUXPOS_PIN7_gc = (0x07<<3), /* Input pin 7 */ -} ADC_CH_MUXPOS_t; - -/* Internal input multiplexer selections */ -typedef enum ADC_CH_MUXINT_enum -{ - ADC_CH_MUXINT_TEMP_gc = (0x00<<3), /* Temperature Reference */ - ADC_CH_MUXINT_BANDGAP_gc = (0x01<<3), /* Bandgap Reference */ - ADC_CH_MUXINT_SCALEDVCC_gc = (0x02<<3), /* 1/10 scaled VCC */ - ADC_CH_MUXINT_DAC_gc = (0x03<<3), /* DAC output */ -} ADC_CH_MUXINT_t; - -/* Negative input multiplexer selection */ -typedef enum ADC_CH_MUXNEG_enum -{ - ADC_CH_MUXNEG_PIN0_gc = (0x00<<0), /* Input pin 0 */ - ADC_CH_MUXNEG_PIN1_gc = (0x01<<0), /* Input pin 1 */ - ADC_CH_MUXNEG_PIN2_gc = (0x02<<0), /* Input pin 2 */ - ADC_CH_MUXNEG_PIN3_gc = (0x03<<0), /* Input pin 3 */ - ADC_CH_MUXNEG_PIN4_gc = (0x04<<0), /* Input pin 4 */ - ADC_CH_MUXNEG_PIN5_gc = (0x05<<0), /* Input pin 5 */ - ADC_CH_MUXNEG_PIN6_gc = (0x06<<0), /* Input pin 6 */ - ADC_CH_MUXNEG_PIN7_gc = (0x07<<0), /* Input pin 7 */ -} ADC_CH_MUXNEG_t; - -/* Input mode */ -typedef enum ADC_CH_INPUTMODE_enum -{ - ADC_CH_INPUTMODE_INTERNAL_gc = (0x00<<0), /* Internal inputs, no gain */ - ADC_CH_INPUTMODE_SINGLEENDED_gc = (0x01<<0), /* Single-ended input, no gain */ - ADC_CH_INPUTMODE_DIFF_gc = (0x02<<0), /* Differential input, no gain */ - ADC_CH_INPUTMODE_DIFFWGAIN_gc = (0x03<<0), /* Differential input, with gain */ -} ADC_CH_INPUTMODE_t; - -/* Gain factor */ -typedef enum ADC_CH_GAIN_enum -{ - ADC_CH_GAIN_1X_gc = (0x00<<2), /* 1x gain */ - ADC_CH_GAIN_2X_gc = (0x01<<2), /* 2x gain */ - ADC_CH_GAIN_4X_gc = (0x02<<2), /* 4x gain */ - ADC_CH_GAIN_8X_gc = (0x03<<2), /* 8x gain */ - ADC_CH_GAIN_16X_gc = (0x04<<2), /* 16x gain */ - ADC_CH_GAIN_32X_gc = (0x05<<2), /* 32x gain */ - ADC_CH_GAIN_64X_gc = (0x06<<2), /* 64x gain */ - ADC_CH_GAIN_DIV2_gc = (0x07<<2), /* x/2 gain */ -} ADC_CH_GAIN_t; - -/* Conversion result resolution */ -typedef enum ADC_RESOLUTION_enum -{ - ADC_RESOLUTION_12BIT_gc = (0x00<<1), /* 12-bit right-adjusted result */ - ADC_RESOLUTION_8BIT_gc = (0x02<<1), /* 8-bit right-adjusted result */ - ADC_RESOLUTION_LEFT12BIT_gc = (0x03<<1), /* 12-bit left-adjusted result */ -} ADC_RESOLUTION_t; - -/* Voltage reference selection */ -typedef enum ADC_REFSEL_enum -{ - ADC_REFSEL_INT1V_gc = (0x00<<4), /* Internal 1V */ - ADC_REFSEL_VCC_gc = (0x01<<4), /* Internal VCC/1.6V */ - ADC_REFSEL_AREFA_gc = (0x02<<4), /* External reference on PORT A */ - ADC_REFSEL_AREFB_gc = (0x03<<4), /* External reference on PORT B */ -} ADC_REFSEL_t; - -/* Channel sweep selection */ -typedef enum ADC_SWEEP_enum -{ - ADC_SWEEP_0_gc = (0x00<<6), /* ADC Channel 0 */ -} ADC_SWEEP_t; - -/* Event channel input selection */ -typedef enum ADC_EVSEL_enum -{ - ADC_EVSEL_0123_gc = (0x00<<3), /* Event Channel 0,1,2,3 */ - ADC_EVSEL_1234_gc = (0x01<<3), /* Event Channel 1,2,3,4 */ - ADC_EVSEL_2345_gc = (0x02<<3), /* Event Channel 2,3,4,5 */ - ADC_EVSEL_3456_gc = (0x03<<3), /* Event Channel 3,4,5,6 */ - ADC_EVSEL_4567_gc = (0x04<<3), /* Event Channel 4,5,6,7 */ - ADC_EVSEL_567_gc = (0x05<<3), /* Event Channel 5,6,7 */ - ADC_EVSEL_67_gc = (0x06<<3), /* Event Channel 6,7 */ - ADC_EVSEL_7_gc = (0x07<<3), /* Event Channel 7 */ -} ADC_EVSEL_t; - -/* Event action selection */ -typedef enum ADC_EVACT_enum -{ - ADC_EVACT_NONE_gc = (0x00<<0), /* No event action */ - ADC_EVACT_CH0_gc = (0x01<<0), /* First event triggers channel 0 */ -} ADC_EVACT_t; - -/* Interupt mode */ -typedef enum ADC_CH_INTMODE_enum -{ - ADC_CH_INTMODE_COMPLETE_gc = (0x00<<2), /* Interrupt on conversion complete */ - ADC_CH_INTMODE_BELOW_gc = (0x01<<2), /* Interrupt on result below compare value */ - ADC_CH_INTMODE_ABOVE_gc = (0x03<<2), /* Interrupt on result above compare value */ -} ADC_CH_INTMODE_t; - -/* Interrupt level */ -typedef enum ADC_CH_INTLVL_enum -{ - ADC_CH_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ - ADC_CH_INTLVL_LO_gc = (0x01<<0), /* Low level */ - ADC_CH_INTLVL_MED_gc = (0x02<<0), /* Medium level */ - ADC_CH_INTLVL_HI_gc = (0x03<<0), /* High level */ -} ADC_CH_INTLVL_t; - -/* Clock prescaler */ -typedef enum ADC_PRESCALER_enum -{ - ADC_PRESCALER_DIV4_gc = (0x00<<0), /* Divide clock by 4 */ - ADC_PRESCALER_DIV8_gc = (0x01<<0), /* Divide clock by 8 */ - ADC_PRESCALER_DIV16_gc = (0x02<<0), /* Divide clock by 16 */ - ADC_PRESCALER_DIV32_gc = (0x03<<0), /* Divide clock by 32 */ - ADC_PRESCALER_DIV64_gc = (0x04<<0), /* Divide clock by 64 */ - ADC_PRESCALER_DIV128_gc = (0x05<<0), /* Divide clock by 128 */ - ADC_PRESCALER_DIV256_gc = (0x06<<0), /* Divide clock by 256 */ - ADC_PRESCALER_DIV512_gc = (0x07<<0), /* Divide clock by 512 */ -} ADC_PRESCALER_t; - - -/* --------------------------------------------------------------------------- -RTC - Real-Time Clounter --------------------------------------------------------------------------- -*/ - -/* Real-Time Counter */ -typedef struct RTC_struct -{ - register8_t CTRL; /* Control Register */ - register8_t STATUS; /* Status Register */ - register8_t INTCTRL; /* Interrupt Control Register */ - register8_t INTFLAGS; /* Interrupt Flags */ - register8_t TEMP; /* Temporary register */ - register8_t reserved_0x05; - register8_t reserved_0x06; - register8_t reserved_0x07; - _WORDREGISTER(CNT); /* Count Register */ - _WORDREGISTER(PER); /* Period Register */ - _WORDREGISTER(COMP); /* Compare Register */ -} RTC_t; - -/* Prescaler Factor */ -typedef enum RTC_PRESCALER_enum -{ - RTC_PRESCALER_OFF_gc = (0x00<<0), /* RTC Off */ - RTC_PRESCALER_DIV1_gc = (0x01<<0), /* RTC Clock */ - RTC_PRESCALER_DIV2_gc = (0x02<<0), /* RTC Clock / 2 */ - RTC_PRESCALER_DIV8_gc = (0x03<<0), /* RTC Clock / 8 */ - RTC_PRESCALER_DIV16_gc = (0x04<<0), /* RTC Clock / 16 */ - RTC_PRESCALER_DIV64_gc = (0x05<<0), /* RTC Clock / 64 */ - RTC_PRESCALER_DIV256_gc = (0x06<<0), /* RTC Clock / 256 */ - RTC_PRESCALER_DIV1024_gc = (0x07<<0), /* RTC Clock / 1024 */ -} RTC_PRESCALER_t; - -/* Compare Interrupt level */ -typedef enum RTC_COMPINTLVL_enum -{ - RTC_COMPINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ - RTC_COMPINTLVL_LO_gc = (0x01<<2), /* Low Level */ - RTC_COMPINTLVL_MED_gc = (0x02<<2), /* Medium Level */ - RTC_COMPINTLVL_HI_gc = (0x03<<2), /* High Level */ -} RTC_COMPINTLVL_t; - -/* Overflow Interrupt level */ -typedef enum RTC_OVFINTLVL_enum -{ - RTC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - RTC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ - RTC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ - RTC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ -} RTC_OVFINTLVL_t; - - -/* --------------------------------------------------------------------------- -EBI - External Bus Interface --------------------------------------------------------------------------- -*/ - -/* EBI Chip Select Module */ -typedef struct EBI_CS_struct -{ - register8_t CTRLA; /* Chip Select Control Register A */ - register8_t CTRLB; /* Chip Select Control Register B */ - _WORDREGISTER(BASEADDR); /* Chip Select Base Address */ -} EBI_CS_t; - -/* --------------------------------------------------------------------------- -EBI - External Bus Interface --------------------------------------------------------------------------- -*/ - -/* External Bus Interface */ -typedef struct EBI_struct -{ - register8_t CTRL; /* Control */ - register8_t SDRAMCTRLA; /* SDRAM Control Register A */ - register8_t reserved_0x02; - register8_t reserved_0x03; - _WORDREGISTER(REFRESH); /* SDRAM Refresh Period */ - _WORDREGISTER(INITDLY); /* SDRAM Initialization Delay */ - register8_t SDRAMCTRLB; /* SDRAM Control Register B */ - register8_t SDRAMCTRLC; /* SDRAM Control Register C */ - register8_t reserved_0x0A; - register8_t reserved_0x0B; - register8_t reserved_0x0C; - register8_t reserved_0x0D; - register8_t reserved_0x0E; - register8_t reserved_0x0F; - EBI_CS_t CS0; /* Chip Select 0 */ - EBI_CS_t CS1; /* Chip Select 1 */ - EBI_CS_t CS2; /* Chip Select 2 */ - EBI_CS_t CS3; /* Chip Select 3 */ -} EBI_t; - -/* Chip Select adress space */ -typedef enum EBI_CS_ASIZE_enum -{ - EBI_CS_ASIZE_256B_gc = (0x00<<2), /* 256 bytes */ - EBI_CS_ASIZE_512B_gc = (0x01<<2), /* 512 bytes */ - EBI_CS_ASIZE_1KB_gc = (0x02<<2), /* 1K bytes */ - EBI_CS_ASIZE_2KB_gc = (0x03<<2), /* 2K bytes */ - EBI_CS_ASIZE_4KB_gc = (0x04<<2), /* 4K bytes */ - EBI_CS_ASIZE_8KB_gc = (0x05<<2), /* 8K bytes */ - EBI_CS_ASIZE_16KB_gc = (0x06<<2), /* 16K bytes */ - EBI_CS_ASIZE_32KB_gc = (0x07<<2), /* 32K bytes */ - EBI_CS_ASIZE_64KB_gc = (0x08<<2), /* 64K bytes */ - EBI_CS_ASIZE_128KB_gc = (0x09<<2), /* 128K bytes */ - EBI_CS_ASIZE_256KB_gc = (0x0A<<2), /* 256K bytes */ - EBI_CS_ASIZE_512KB_gc = (0x0B<<2), /* 512K bytes */ - EBI_CS_ASIZE_1MB_gc = (0x0C<<2), /* 1M bytes */ - EBI_CS_ASIZE_2MB_gc = (0x0D<<2), /* 2M bytes */ - EBI_CS_ASIZE_4MB_gc = (0x0E<<2), /* 4M bytes */ - EBI_CS_ASIZE_8MB_gc = (0x0F<<2), /* 8M bytes */ - EBI_CS_ASIZE_16M_gc = (0x10<<2), /* 16M bytes */ -} EBI_CS_ASIZE_t; - -/* */ -typedef enum EBI_CS_SRWS_enum -{ - EBI_CS_SRWS_0CLK_gc = (0x00<<0), /* 0 cycles */ - EBI_CS_SRWS_1CLK_gc = (0x01<<0), /* 1 cycle */ - EBI_CS_SRWS_2CLK_gc = (0x02<<0), /* 2 cycles */ - EBI_CS_SRWS_3CLK_gc = (0x03<<0), /* 3 cycles */ - EBI_CS_SRWS_4CLK_gc = (0x04<<0), /* 4 cycles */ - EBI_CS_SRWS_5CLK_gc = (0x05<<0), /* 5 cycle */ - EBI_CS_SRWS_6CLK_gc = (0x06<<0), /* 6 cycles */ - EBI_CS_SRWS_7CLK_gc = (0x07<<0), /* 7 cycles */ -} EBI_CS_SRWS_t; - -/* Chip Select address mode */ -typedef enum EBI_CS_MODE_enum -{ - EBI_CS_MODE_DISABLED_gc = (0x00<<0), /* Chip Select Disabled */ - EBI_CS_MODE_SRAM_gc = (0x01<<0), /* Chip Select in SRAM mode */ - EBI_CS_MODE_LPC_gc = (0x02<<0), /* Chip Select in SRAM LPC mode */ - EBI_CS_MODE_SDRAM_gc = (0x03<<0), /* Chip Select in SDRAM mode */ -} EBI_CS_MODE_t; - -/* Chip Select SDRAM mode */ -typedef enum EBI_CS_SDMODE_enum -{ - EBI_CS_SDMODE_NORMAL_gc = (0x00<<0), /* Normal mode */ - EBI_CS_SDMODE_LOAD_gc = (0x01<<0), /* Load Mode Register command mode */ -} EBI_CS_SDMODE_t; - -/* */ -typedef enum EBI_SDDATAW_enum -{ - EBI_SDDATAW_4BIT_gc = (0x00<<6), /* 4-bit data bus */ - EBI_SDDATAW_8BIT_gc = (0x01<<6), /* 8-bit data bus */ -} EBI_SDDATAW_t; - -/* */ -typedef enum EBI_LPCMODE_enum -{ - EBI_LPCMODE_ALE1_gc = (0x00<<4), /* Data muxed with addr byte 0 */ - EBI_LPCMODE_ALE12_gc = (0x02<<4), /* Data muxed with addr byte 0 and 1 */ -} EBI_LPCMODE_t; - -/* */ -typedef enum EBI_SRMODE_enum -{ - EBI_SRMODE_ALE1_gc = (0x00<<2), /* Addr byte 0 muxed with 1 */ - EBI_SRMODE_ALE2_gc = (0x01<<2), /* Addr byte 0 muxed with 2 */ - EBI_SRMODE_ALE12_gc = (0x02<<2), /* Addr byte 0 muxed with 1 and 2 */ - EBI_SRMODE_NOALE_gc = (0x03<<2), /* No addr muxing */ -} EBI_SRMODE_t; - -/* */ -typedef enum EBI_IFMODE_enum -{ - EBI_IFMODE_DISABLED_gc = (0x00<<0), /* EBI Disabled */ - EBI_IFMODE_3PORT_gc = (0x01<<0), /* 3-port mode */ - EBI_IFMODE_4PORT_gc = (0x02<<0), /* 4-port mode */ - EBI_IFMODE_2PORT_gc = (0x03<<0), /* 2-port mode */ -} EBI_IFMODE_t; - -/* */ -typedef enum EBI_SDCOL_enum -{ - EBI_SDCOL_8BIT_gc = (0x00<<0), /* 8 column bits */ - EBI_SDCOL_9BIT_gc = (0x01<<0), /* 9 column bits */ - EBI_SDCOL_10BIT_gc = (0x02<<0), /* 10 column bits */ - EBI_SDCOL_11BIT_gc = (0x03<<0), /* 11 column bits */ -} EBI_SDCOL_t; - -/* */ -typedef enum EBI_MRDLY_enum -{ - EBI_MRDLY_0CLK_gc = (0x00<<6), /* 0 cycles */ - EBI_MRDLY_1CLK_gc = (0x01<<6), /* 1 cycle */ - EBI_MRDLY_2CLK_gc = (0x02<<6), /* 2 cycles */ - EBI_MRDLY_3CLK_gc = (0x03<<6), /* 3 cycles */ -} EBI_MRDLY_t; - -/* */ -typedef enum EBI_ROWCYCDLY_enum -{ - EBI_ROWCYCDLY_0CLK_gc = (0x00<<3), /* 0 cycles */ - EBI_ROWCYCDLY_1CLK_gc = (0x01<<3), /* 1 cycle */ - EBI_ROWCYCDLY_2CLK_gc = (0x02<<3), /* 2 cycles */ - EBI_ROWCYCDLY_3CLK_gc = (0x03<<3), /* 3 cycles */ - EBI_ROWCYCDLY_4CLK_gc = (0x04<<3), /* 4 cycles */ - EBI_ROWCYCDLY_5CLK_gc = (0x05<<3), /* 5 cycle */ - EBI_ROWCYCDLY_6CLK_gc = (0x06<<3), /* 6 cycles */ - EBI_ROWCYCDLY_7CLK_gc = (0x07<<3), /* 7 cycles */ -} EBI_ROWCYCDLY_t; - -/* */ -typedef enum EBI_RPDLY_enum -{ - EBI_RPDLY_0CLK_gc = (0x00<<0), /* 0 cycles */ - EBI_RPDLY_1CLK_gc = (0x01<<0), /* 1 cycle */ - EBI_RPDLY_2CLK_gc = (0x02<<0), /* 2 cycles */ - EBI_RPDLY_3CLK_gc = (0x03<<0), /* 3 cycles */ - EBI_RPDLY_4CLK_gc = (0x04<<0), /* 4 cycles */ - EBI_RPDLY_5CLK_gc = (0x05<<0), /* 5 cycle */ - EBI_RPDLY_6CLK_gc = (0x06<<0), /* 6 cycles */ - EBI_RPDLY_7CLK_gc = (0x07<<0), /* 7 cycles */ -} EBI_RPDLY_t; - -/* */ -typedef enum EBI_WRDLY_enum -{ - EBI_WRDLY_0CLK_gc = (0x00<<6), /* 0 cycles */ - EBI_WRDLY_1CLK_gc = (0x01<<6), /* 1 cycle */ - EBI_WRDLY_2CLK_gc = (0x02<<6), /* 2 cycles */ - EBI_WRDLY_3CLK_gc = (0x03<<6), /* 3 cycles */ -} EBI_WRDLY_t; - -/* */ -typedef enum EBI_ESRDLY_enum -{ - EBI_ESRDLY_0CLK_gc = (0x00<<3), /* 0 cycles */ - EBI_ESRDLY_1CLK_gc = (0x01<<3), /* 1 cycle */ - EBI_ESRDLY_2CLK_gc = (0x02<<3), /* 2 cycles */ - EBI_ESRDLY_3CLK_gc = (0x03<<3), /* 3 cycles */ - EBI_ESRDLY_4CLK_gc = (0x04<<3), /* 4 cycles */ - EBI_ESRDLY_5CLK_gc = (0x05<<3), /* 5 cycle */ - EBI_ESRDLY_6CLK_gc = (0x06<<3), /* 6 cycles */ - EBI_ESRDLY_7CLK_gc = (0x07<<3), /* 7 cycles */ -} EBI_ESRDLY_t; - -/* */ -typedef enum EBI_ROWCOLDLY_enum -{ - EBI_ROWCOLDLY_0CLK_gc = (0x00<<0), /* 0 cycles */ - EBI_ROWCOLDLY_1CLK_gc = (0x01<<0), /* 1 cycle */ - EBI_ROWCOLDLY_2CLK_gc = (0x02<<0), /* 2 cycles */ - EBI_ROWCOLDLY_3CLK_gc = (0x03<<0), /* 3 cycles */ - EBI_ROWCOLDLY_4CLK_gc = (0x04<<0), /* 4 cycles */ - EBI_ROWCOLDLY_5CLK_gc = (0x05<<0), /* 5 cycle */ - EBI_ROWCOLDLY_6CLK_gc = (0x06<<0), /* 6 cycles */ - EBI_ROWCOLDLY_7CLK_gc = (0x07<<0), /* 7 cycles */ -} EBI_ROWCOLDLY_t; - - -/* --------------------------------------------------------------------------- -TWI - Two-Wire Interface --------------------------------------------------------------------------- -*/ - -/* */ -typedef struct TWI_MASTER_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t CTRLC; /* Control Register C */ - register8_t STATUS; /* Status Register */ - register8_t BAUD; /* Baurd Rate Control Register */ - register8_t ADDR; /* Address Register */ - register8_t DATA; /* Data Register */ -} TWI_MASTER_t; - -/* --------------------------------------------------------------------------- -TWI - Two-Wire Interface --------------------------------------------------------------------------- -*/ - -/* */ -typedef struct TWI_SLAVE_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t STATUS; /* Status Register */ - register8_t ADDR; /* Address Register */ - register8_t DATA; /* Data Register */ - register8_t ADDRMASK; /* Address Mask Register */ -} TWI_SLAVE_t; - -/* --------------------------------------------------------------------------- -TWI - Two-Wire Interface --------------------------------------------------------------------------- -*/ - -/* Two-Wire Interface */ -typedef struct TWI_struct -{ - register8_t CTRL; /* TWI Common Control Register */ - TWI_MASTER_t MASTER; /* TWI master module */ - TWI_SLAVE_t SLAVE; /* TWI slave module */ -} TWI_t; - -/* Master Interrupt Level */ -typedef enum TWI_MASTER_INTLVL_enum -{ - TWI_MASTER_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ - TWI_MASTER_INTLVL_LO_gc = (0x01<<6), /* Low Level */ - TWI_MASTER_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ - TWI_MASTER_INTLVL_HI_gc = (0x03<<6), /* High Level */ -} TWI_MASTER_INTLVL_t; - -/* Inactive Timeout */ -typedef enum TWI_MASTER_TIMEOUT_enum -{ - TWI_MASTER_TIMEOUT_DISABLED_gc = (0x00<<2), /* Bus Timeout Disabled */ - TWI_MASTER_TIMEOUT_50US_gc = (0x01<<2), /* 50 Microseconds */ - TWI_MASTER_TIMEOUT_100US_gc = (0x02<<2), /* 100 Microseconds */ - TWI_MASTER_TIMEOUT_200US_gc = (0x03<<2), /* 200 Microseconds */ -} TWI_MASTER_TIMEOUT_t; - -/* Master Command */ -typedef enum TWI_MASTER_CMD_enum -{ - TWI_MASTER_CMD_NOACT_gc = (0x00<<0), /* No Action */ - TWI_MASTER_CMD_REPSTART_gc = (0x01<<0), /* Issue Repeated Start Condition */ - TWI_MASTER_CMD_RECVTRANS_gc = (0x02<<0), /* Receive or Transmit Data */ - TWI_MASTER_CMD_STOP_gc = (0x03<<0), /* Issue Stop Condition */ -} TWI_MASTER_CMD_t; - -/* Master Bus State */ -typedef enum TWI_MASTER_BUSSTATE_enum -{ - TWI_MASTER_BUSSTATE_UNKNOWN_gc = (0x00<<0), /* Unknown Bus State */ - TWI_MASTER_BUSSTATE_IDLE_gc = (0x01<<0), /* Bus is Idle */ - TWI_MASTER_BUSSTATE_OWNER_gc = (0x02<<0), /* This Module Controls The Bus */ - TWI_MASTER_BUSSTATE_BUSY_gc = (0x03<<0), /* The Bus is Busy */ -} TWI_MASTER_BUSSTATE_t; - -/* Slave Interrupt Level */ -typedef enum TWI_SLAVE_INTLVL_enum -{ - TWI_SLAVE_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ - TWI_SLAVE_INTLVL_LO_gc = (0x01<<6), /* Low Level */ - TWI_SLAVE_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ - TWI_SLAVE_INTLVL_HI_gc = (0x03<<6), /* High Level */ -} TWI_SLAVE_INTLVL_t; - -/* Slave Command */ -typedef enum TWI_SLAVE_CMD_enum -{ - TWI_SLAVE_CMD_NOACT_gc = (0x00<<0), /* No Action */ - TWI_SLAVE_CMD_COMPTRANS_gc = (0x02<<0), /* Used To Complete a Transaction */ - TWI_SLAVE_CMD_RESPONSE_gc = (0x03<<0), /* Used in Response to Address/Data Interrupt */ -} TWI_SLAVE_CMD_t; - - -/* --------------------------------------------------------------------------- -PORT - Port Configuration --------------------------------------------------------------------------- -*/ - -/* I/O port Configuration */ -typedef struct PORTCFG_struct -{ - register8_t MPCMASK; /* Multi-pin Configuration Mask */ - register8_t reserved_0x01; - register8_t VPCTRLA; /* Virtual Port Control Register A */ - register8_t VPCTRLB; /* Virtual Port Control Register B */ - register8_t CLKEVOUT; /* Clock and Event Out Register */ -} PORTCFG_t; - -/* --------------------------------------------------------------------------- -PORT - Port Configuration --------------------------------------------------------------------------- -*/ - -/* Virtual Port */ -typedef struct VPORT_struct -{ - register8_t DIR; /* I/O Port Data Direction */ - register8_t OUT; /* I/O Port Output */ - register8_t IN; /* I/O Port Input */ - register8_t INTFLAGS; /* Interrupt Flag Register */ -} VPORT_t; - -/* --------------------------------------------------------------------------- -PORT - Port Configuration --------------------------------------------------------------------------- -*/ - -/* I/O Ports */ -typedef struct PORT_struct -{ - register8_t DIR; /* I/O Port Data Direction */ - register8_t DIRSET; /* I/O Port Data Direction Set */ - register8_t DIRCLR; /* I/O Port Data Direction Clear */ - register8_t DIRTGL; /* I/O Port Data Direction Toggle */ - register8_t OUT; /* I/O Port Output */ - register8_t OUTSET; /* I/O Port Output Set */ - register8_t OUTCLR; /* I/O Port Output Clear */ - register8_t OUTTGL; /* I/O Port Output Toggle */ - register8_t IN; /* I/O port Input */ - register8_t INTCTRL; /* Interrupt Control Register */ - register8_t INT0MASK; /* Port Interrupt 0 Mask */ - register8_t INT1MASK; /* Port Interrupt 1 Mask */ - register8_t INTFLAGS; /* Interrupt Flag Register */ - register8_t reserved_0x0D; - register8_t reserved_0x0E; - register8_t reserved_0x0F; - register8_t PIN0CTRL; /* Pin 0 Control Register */ - register8_t PIN1CTRL; /* Pin 1 Control Register */ - register8_t PIN2CTRL; /* Pin 2 Control Register */ - register8_t PIN3CTRL; /* Pin 3 Control Register */ - register8_t PIN4CTRL; /* Pin 4 Control Register */ - register8_t PIN5CTRL; /* Pin 5 Control Register */ - register8_t PIN6CTRL; /* Pin 6 Control Register */ - register8_t PIN7CTRL; /* Pin 7 Control Register */ -} PORT_t; - -/* Virtual Port 0 Mapping */ -typedef enum PORTCFG_VP0MAP_enum -{ - PORTCFG_VP0MAP_PORTA_gc = (0x00<<0), /* Mapped To PORTA */ - PORTCFG_VP0MAP_PORTB_gc = (0x01<<0), /* Mapped To PORTB */ - PORTCFG_VP0MAP_PORTC_gc = (0x02<<0), /* Mapped To PORTC */ - PORTCFG_VP0MAP_PORTD_gc = (0x03<<0), /* Mapped To PORTD */ - PORTCFG_VP0MAP_PORTE_gc = (0x04<<0), /* Mapped To PORTE */ - PORTCFG_VP0MAP_PORTF_gc = (0x05<<0), /* Mapped To PORTF */ - PORTCFG_VP0MAP_PORTG_gc = (0x06<<0), /* Mapped To PORTG */ - PORTCFG_VP0MAP_PORTH_gc = (0x07<<0), /* Mapped To PORTH */ - PORTCFG_VP0MAP_PORTJ_gc = (0x08<<0), /* Mapped To PORTJ */ - PORTCFG_VP0MAP_PORTK_gc = (0x09<<0), /* Mapped To PORTK */ - PORTCFG_VP0MAP_PORTL_gc = (0x0A<<0), /* Mapped To PORTL */ - PORTCFG_VP0MAP_PORTM_gc = (0x0B<<0), /* Mapped To PORTM */ - PORTCFG_VP0MAP_PORTN_gc = (0x0C<<0), /* Mapped To PORTN */ - PORTCFG_VP0MAP_PORTP_gc = (0x0D<<0), /* Mapped To PORTP */ - PORTCFG_VP0MAP_PORTQ_gc = (0x0E<<0), /* Mapped To PORTQ */ - PORTCFG_VP0MAP_PORTR_gc = (0x0F<<0), /* Mapped To PORTR */ -} PORTCFG_VP0MAP_t; - -/* Virtual Port 1 Mapping */ -typedef enum PORTCFG_VP1MAP_enum -{ - PORTCFG_VP1MAP_PORTA_gc = (0x00<<4), /* Mapped To PORTA */ - PORTCFG_VP1MAP_PORTB_gc = (0x01<<4), /* Mapped To PORTB */ - PORTCFG_VP1MAP_PORTC_gc = (0x02<<4), /* Mapped To PORTC */ - PORTCFG_VP1MAP_PORTD_gc = (0x03<<4), /* Mapped To PORTD */ - PORTCFG_VP1MAP_PORTE_gc = (0x04<<4), /* Mapped To PORTE */ - PORTCFG_VP1MAP_PORTF_gc = (0x05<<4), /* Mapped To PORTF */ - PORTCFG_VP1MAP_PORTG_gc = (0x06<<4), /* Mapped To PORTG */ - PORTCFG_VP1MAP_PORTH_gc = (0x07<<4), /* Mapped To PORTH */ - PORTCFG_VP1MAP_PORTJ_gc = (0x08<<4), /* Mapped To PORTJ */ - PORTCFG_VP1MAP_PORTK_gc = (0x09<<4), /* Mapped To PORTK */ - PORTCFG_VP1MAP_PORTL_gc = (0x0A<<4), /* Mapped To PORTL */ - PORTCFG_VP1MAP_PORTM_gc = (0x0B<<4), /* Mapped To PORTM */ - PORTCFG_VP1MAP_PORTN_gc = (0x0C<<4), /* Mapped To PORTN */ - PORTCFG_VP1MAP_PORTP_gc = (0x0D<<4), /* Mapped To PORTP */ - PORTCFG_VP1MAP_PORTQ_gc = (0x0E<<4), /* Mapped To PORTQ */ - PORTCFG_VP1MAP_PORTR_gc = (0x0F<<4), /* Mapped To PORTR */ -} PORTCFG_VP1MAP_t; - -/* Virtual Port 2 Mapping */ -typedef enum PORTCFG_VP2MAP_enum -{ - PORTCFG_VP2MAP_PORTA_gc = (0x00<<0), /* Mapped To PORTA */ - PORTCFG_VP2MAP_PORTB_gc = (0x01<<0), /* Mapped To PORTB */ - PORTCFG_VP2MAP_PORTC_gc = (0x02<<0), /* Mapped To PORTC */ - PORTCFG_VP2MAP_PORTD_gc = (0x03<<0), /* Mapped To PORTD */ - PORTCFG_VP2MAP_PORTE_gc = (0x04<<0), /* Mapped To PORTE */ - PORTCFG_VP2MAP_PORTF_gc = (0x05<<0), /* Mapped To PORTF */ - PORTCFG_VP2MAP_PORTG_gc = (0x06<<0), /* Mapped To PORTG */ - PORTCFG_VP2MAP_PORTH_gc = (0x07<<0), /* Mapped To PORTH */ - PORTCFG_VP2MAP_PORTJ_gc = (0x08<<0), /* Mapped To PORTJ */ - PORTCFG_VP2MAP_PORTK_gc = (0x09<<0), /* Mapped To PORTK */ - PORTCFG_VP2MAP_PORTL_gc = (0x0A<<0), /* Mapped To PORTL */ - PORTCFG_VP2MAP_PORTM_gc = (0x0B<<0), /* Mapped To PORTM */ - PORTCFG_VP2MAP_PORTN_gc = (0x0C<<0), /* Mapped To PORTN */ - PORTCFG_VP2MAP_PORTP_gc = (0x0D<<0), /* Mapped To PORTP */ - PORTCFG_VP2MAP_PORTQ_gc = (0x0E<<0), /* Mapped To PORTQ */ - PORTCFG_VP2MAP_PORTR_gc = (0x0F<<0), /* Mapped To PORTR */ -} PORTCFG_VP2MAP_t; - -/* Virtual Port 3 Mapping */ -typedef enum PORTCFG_VP3MAP_enum -{ - PORTCFG_VP3MAP_PORTA_gc = (0x00<<4), /* Mapped To PORTA */ - PORTCFG_VP3MAP_PORTB_gc = (0x01<<4), /* Mapped To PORTB */ - PORTCFG_VP3MAP_PORTC_gc = (0x02<<4), /* Mapped To PORTC */ - PORTCFG_VP3MAP_PORTD_gc = (0x03<<4), /* Mapped To PORTD */ - PORTCFG_VP3MAP_PORTE_gc = (0x04<<4), /* Mapped To PORTE */ - PORTCFG_VP3MAP_PORTF_gc = (0x05<<4), /* Mapped To PORTF */ - PORTCFG_VP3MAP_PORTG_gc = (0x06<<4), /* Mapped To PORTG */ - PORTCFG_VP3MAP_PORTH_gc = (0x07<<4), /* Mapped To PORTH */ - PORTCFG_VP3MAP_PORTJ_gc = (0x08<<4), /* Mapped To PORTJ */ - PORTCFG_VP3MAP_PORTK_gc = (0x09<<4), /* Mapped To PORTK */ - PORTCFG_VP3MAP_PORTL_gc = (0x0A<<4), /* Mapped To PORTL */ - PORTCFG_VP3MAP_PORTM_gc = (0x0B<<4), /* Mapped To PORTM */ - PORTCFG_VP3MAP_PORTN_gc = (0x0C<<4), /* Mapped To PORTN */ - PORTCFG_VP3MAP_PORTP_gc = (0x0D<<4), /* Mapped To PORTP */ - PORTCFG_VP3MAP_PORTQ_gc = (0x0E<<4), /* Mapped To PORTQ */ - PORTCFG_VP3MAP_PORTR_gc = (0x0F<<4), /* Mapped To PORTR */ -} PORTCFG_VP3MAP_t; - -/* Clock Output Port */ -typedef enum PORTCFG_CLKOUT_enum -{ - PORTCFG_CLKOUT_OFF_gc = (0x00<<0), /* Clock Output Disabled */ - PORTCFG_CLKOUT_PC7_gc = (0x01<<0), /* Clock Output on Port C pin 7 */ - PORTCFG_CLKOUT_PD7_gc = (0x02<<0), /* Clock Output on Port D pin 7 */ - PORTCFG_CLKOUT_PE7_gc = (0x03<<0), /* Clock Output on Port E pin 7 */ -} PORTCFG_CLKOUT_t; - -/* Event Output Port */ -typedef enum PORTCFG_EVOUT_enum -{ - PORTCFG_EVOUT_OFF_gc = (0x00<<4), /* Event Output Disabled */ - PORTCFG_EVOUT_PC7_gc = (0x01<<4), /* Event Channel 7 Output on Port C pin 7 */ - PORTCFG_EVOUT_PD7_gc = (0x02<<4), /* Event Channel 7 Output on Port D pin 7 */ - PORTCFG_EVOUT_PE7_gc = (0x03<<4), /* Event Channel 7 Output on Port E pin 7 */ -} PORTCFG_EVOUT_t; - -/* Port Interrupt 0 Level */ -typedef enum PORT_INT0LVL_enum -{ - PORT_INT0LVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - PORT_INT0LVL_LO_gc = (0x01<<0), /* Low Level */ - PORT_INT0LVL_MED_gc = (0x02<<0), /* Medium Level */ - PORT_INT0LVL_HI_gc = (0x03<<0), /* High Level */ -} PORT_INT0LVL_t; - -/* Port Interrupt 1 Level */ -typedef enum PORT_INT1LVL_enum -{ - PORT_INT1LVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ - PORT_INT1LVL_LO_gc = (0x01<<2), /* Low Level */ - PORT_INT1LVL_MED_gc = (0x02<<2), /* Medium Level */ - PORT_INT1LVL_HI_gc = (0x03<<2), /* High Level */ -} PORT_INT1LVL_t; - -/* Output/Pull Configuration */ -typedef enum PORT_OPC_enum -{ - PORT_OPC_TOTEM_gc = (0x00<<3), /* Totempole */ - PORT_OPC_BUSKEEPER_gc = (0x01<<3), /* Totempole w/ Bus keeper on Input and Output */ - PORT_OPC_PULLDOWN_gc = (0x02<<3), /* Totempole w/ Pull-down on Input */ - PORT_OPC_PULLUP_gc = (0x03<<3), /* Totempole w/ Pull-up on Input */ - PORT_OPC_WIREDOR_gc = (0x04<<3), /* Wired OR */ - PORT_OPC_WIREDAND_gc = (0x05<<3), /* Wired AND */ - PORT_OPC_WIREDORPULL_gc = (0x06<<3), /* Wired OR w/ Pull-down */ - PORT_OPC_WIREDANDPULL_gc = (0x07<<3), /* Wired AND w/ Pull-up */ -} PORT_OPC_t; - -/* Input/Sense Configuration */ -typedef enum PORT_ISC_enum -{ - PORT_ISC_BOTHEDGES_gc = (0x00<<0), /* Sense Both Edges */ - PORT_ISC_RISING_gc = (0x01<<0), /* Sense Rising Edge */ - PORT_ISC_FALLING_gc = (0x02<<0), /* Sense Falling Edge */ - PORT_ISC_LEVEL_gc = (0x03<<0), /* Sense Level (Transparent For Events) */ - PORT_ISC_INPUT_DISABLE_gc = (0x07<<0), /* Disable Digital Input Buffer */ -} PORT_ISC_t; - - -/* --------------------------------------------------------------------------- -TC - 16-bit Timer/Counter With PWM --------------------------------------------------------------------------- -*/ - -/* 16-bit Timer/Counter 0 */ -typedef struct TC0_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t CTRLC; /* Control register C */ - register8_t CTRLD; /* Control Register D */ - register8_t CTRLE; /* Control Register E */ - register8_t reserved_0x05; - register8_t INTCTRLA; /* Interrupt Control Register A */ - register8_t INTCTRLB; /* Interrupt Control Register B */ - register8_t CTRLFCLR; /* Control Register F Clear */ - register8_t CTRLFSET; /* Control Register F Set */ - register8_t CTRLGCLR; /* Control Register G Clear */ - register8_t CTRLGSET; /* Control Register G Set */ - register8_t INTFLAGS; /* Interrupt Flag Register */ - register8_t reserved_0x0D; - register8_t reserved_0x0E; - register8_t TEMP; /* Temporary Register For 16-bit Access */ - register8_t reserved_0x10; - register8_t reserved_0x11; - register8_t reserved_0x12; - register8_t reserved_0x13; - register8_t reserved_0x14; - register8_t reserved_0x15; - register8_t reserved_0x16; - register8_t reserved_0x17; - register8_t reserved_0x18; - register8_t reserved_0x19; - register8_t reserved_0x1A; - register8_t reserved_0x1B; - register8_t reserved_0x1C; - register8_t reserved_0x1D; - register8_t reserved_0x1E; - register8_t reserved_0x1F; - _WORDREGISTER(CNT); /* Count */ - register8_t reserved_0x22; - register8_t reserved_0x23; - register8_t reserved_0x24; - register8_t reserved_0x25; - _WORDREGISTER(PER); /* Period */ - _WORDREGISTER(CCA); /* Compare or Capture A */ - _WORDREGISTER(CCB); /* Compare or Capture B */ - _WORDREGISTER(CCC); /* Compare or Capture C */ - _WORDREGISTER(CCD); /* Compare or Capture D */ - register8_t reserved_0x30; - register8_t reserved_0x31; - register8_t reserved_0x32; - register8_t reserved_0x33; - register8_t reserved_0x34; - register8_t reserved_0x35; - _WORDREGISTER(PERBUF); /* Period Buffer */ - _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ - _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ - _WORDREGISTER(CCCBUF); /* Compare Or Capture C Buffer */ - _WORDREGISTER(CCDBUF); /* Compare Or Capture D Buffer */ -} TC0_t; - -/* --------------------------------------------------------------------------- -TC - 16-bit Timer/Counter With PWM --------------------------------------------------------------------------- -*/ - -/* 16-bit Timer/Counter 1 */ -typedef struct TC1_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t CTRLC; /* Control register C */ - register8_t CTRLD; /* Control Register D */ - register8_t CTRLE; /* Control Register E */ - register8_t reserved_0x05; - register8_t INTCTRLA; /* Interrupt Control Register A */ - register8_t INTCTRLB; /* Interrupt Control Register B */ - register8_t CTRLFCLR; /* Control Register F Clear */ - register8_t CTRLFSET; /* Control Register F Set */ - register8_t CTRLGCLR; /* Control Register G Clear */ - register8_t CTRLGSET; /* Control Register G Set */ - register8_t INTFLAGS; /* Interrupt Flag Register */ - register8_t reserved_0x0D; - register8_t reserved_0x0E; - register8_t TEMP; /* Temporary Register For 16-bit Access */ - register8_t reserved_0x10; - register8_t reserved_0x11; - register8_t reserved_0x12; - register8_t reserved_0x13; - register8_t reserved_0x14; - register8_t reserved_0x15; - register8_t reserved_0x16; - register8_t reserved_0x17; - register8_t reserved_0x18; - register8_t reserved_0x19; - register8_t reserved_0x1A; - register8_t reserved_0x1B; - register8_t reserved_0x1C; - register8_t reserved_0x1D; - register8_t reserved_0x1E; - register8_t reserved_0x1F; - _WORDREGISTER(CNT); /* Count */ - register8_t reserved_0x22; - register8_t reserved_0x23; - register8_t reserved_0x24; - register8_t reserved_0x25; - _WORDREGISTER(PER); /* Period */ - _WORDREGISTER(CCA); /* Compare or Capture A */ - _WORDREGISTER(CCB); /* Compare or Capture B */ - register8_t reserved_0x2C; - register8_t reserved_0x2D; - register8_t reserved_0x2E; - register8_t reserved_0x2F; - register8_t reserved_0x30; - register8_t reserved_0x31; - register8_t reserved_0x32; - register8_t reserved_0x33; - register8_t reserved_0x34; - register8_t reserved_0x35; - _WORDREGISTER(PERBUF); /* Period Buffer */ - _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ - _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ -} TC1_t; - -/* --------------------------------------------------------------------------- -TC - 16-bit Timer/Counter With PWM --------------------------------------------------------------------------- -*/ - -/* Advanced Waveform Extension */ -typedef struct AWEX_struct -{ - register8_t CTRL; /* Control Register */ - register8_t reserved_0x01; - register8_t FDEMASK; /* Fault Detection Event Mask */ - register8_t FDCTRL; /* Fault Detection Control Register */ - register8_t STATUS; /* Status Register */ - register8_t reserved_0x05; - register8_t DTBOTH; /* Dead Time Both Sides */ - register8_t DTBOTHBUF; /* Dead Time Both Sides Buffer */ - register8_t DTLS; /* Dead Time Low Side */ - register8_t DTHS; /* Dead Time High Side */ - register8_t DTLSBUF; /* Dead Time Low Side Buffer */ - register8_t DTHSBUF; /* Dead Time High Side Buffer */ - register8_t OUTOVEN; /* Output Override Enable */ -} AWEX_t; - -/* --------------------------------------------------------------------------- -TC - 16-bit Timer/Counter With PWM --------------------------------------------------------------------------- -*/ - -/* High-Resolution Extension */ -typedef struct HIRES_struct -{ - register8_t CTRLA; /* Control Register */ -} HIRES_t; - -/* Clock Selection */ -typedef enum TC_CLKSEL_enum -{ - TC_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */ - TC_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */ - TC_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */ - TC_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */ - TC_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */ - TC_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */ - TC_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */ - TC_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */ - TC_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */ - TC_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */ - TC_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */ - TC_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */ - TC_CLKSEL_EVCH4_gc = (0x0C<<0), /* Event Channel 4 */ - TC_CLKSEL_EVCH5_gc = (0x0D<<0), /* Event Channel 5 */ - TC_CLKSEL_EVCH6_gc = (0x0E<<0), /* Event Channel 6 */ - TC_CLKSEL_EVCH7_gc = (0x0F<<0), /* Event Channel 7 */ -} TC_CLKSEL_t; - -/* Waveform Generation Mode */ -typedef enum TC_WGMODE_enum -{ - TC_WGMODE_NORMAL_gc = (0x00<<0), /* Normal Mode */ - TC_WGMODE_FRQ_gc = (0x01<<0), /* Frequency Generation Mode */ - TC_WGMODE_SS_gc = (0x03<<0), /* Single Slope */ - TC_WGMODE_DS_T_gc = (0x05<<0), /* Dual Slope, Update on TOP */ - TC_WGMODE_DS_TB_gc = (0x06<<0), /* Dual Slope, Update on TOP and BOTTOM */ - TC_WGMODE_DS_B_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */ -} TC_WGMODE_t; - -/* Event Action */ -typedef enum TC_EVACT_enum -{ - TC_EVACT_OFF_gc = (0x00<<5), /* No Event Action */ - TC_EVACT_CAPT_gc = (0x01<<5), /* Input Capture */ - TC_EVACT_UPDOWN_gc = (0x02<<5), /* Externally Controlled Up/Down Count */ - TC_EVACT_QDEC_gc = (0x03<<5), /* Quadrature Decode */ - TC_EVACT_RESTART_gc = (0x04<<5), /* Restart */ - TC_EVACT_FRQ_gc = (0x05<<5), /* Frequency Capture */ - TC_EVACT_PW_gc = (0x06<<5), /* Pulse-width Capture */ -} TC_EVACT_t; - -/* Event Selection */ -typedef enum TC_EVSEL_enum -{ - TC_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ - TC_EVSEL_CH0_gc = (0x08<<0), /* Event Channel 0 */ - TC_EVSEL_CH1_gc = (0x09<<0), /* Event Channel 1 */ - TC_EVSEL_CH2_gc = (0x0A<<0), /* Event Channel 2 */ - TC_EVSEL_CH3_gc = (0x0B<<0), /* Event Channel 3 */ - TC_EVSEL_CH4_gc = (0x0C<<0), /* Event Channel 4 */ - TC_EVSEL_CH5_gc = (0x0D<<0), /* Event Channel 5 */ - TC_EVSEL_CH6_gc = (0x0E<<0), /* Event Channel 6 */ - TC_EVSEL_CH7_gc = (0x0F<<0), /* Event Channel 7 */ -} TC_EVSEL_t; - -/* Error Interrupt Level */ -typedef enum TC_ERRINTLVL_enum -{ - TC_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ - TC_ERRINTLVL_LO_gc = (0x01<<2), /* Low Level */ - TC_ERRINTLVL_MED_gc = (0x02<<2), /* Medium Level */ - TC_ERRINTLVL_HI_gc = (0x03<<2), /* High Level */ -} TC_ERRINTLVL_t; - -/* Overflow Interrupt Level */ -typedef enum TC_OVFINTLVL_enum -{ - TC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - TC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ - TC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ - TC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ -} TC_OVFINTLVL_t; - -/* Compare or Capture D Interrupt Level */ -typedef enum TC_CCDINTLVL_enum -{ - TC_CCDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ - TC_CCDINTLVL_LO_gc = (0x01<<6), /* Low Level */ - TC_CCDINTLVL_MED_gc = (0x02<<6), /* Medium Level */ - TC_CCDINTLVL_HI_gc = (0x03<<6), /* High Level */ -} TC_CCDINTLVL_t; - -/* Compare or Capture C Interrupt Level */ -typedef enum TC_CCCINTLVL_enum -{ - TC_CCCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ - TC_CCCINTLVL_LO_gc = (0x01<<4), /* Low Level */ - TC_CCCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ - TC_CCCINTLVL_HI_gc = (0x03<<4), /* High Level */ -} TC_CCCINTLVL_t; - -/* Compare or Capture B Interrupt Level */ -typedef enum TC_CCBINTLVL_enum -{ - TC_CCBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ - TC_CCBINTLVL_LO_gc = (0x01<<2), /* Low Level */ - TC_CCBINTLVL_MED_gc = (0x02<<2), /* Medium Level */ - TC_CCBINTLVL_HI_gc = (0x03<<2), /* High Level */ -} TC_CCBINTLVL_t; - -/* Compare or Capture A Interrupt Level */ -typedef enum TC_CCAINTLVL_enum -{ - TC_CCAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - TC_CCAINTLVL_LO_gc = (0x01<<0), /* Low Level */ - TC_CCAINTLVL_MED_gc = (0x02<<0), /* Medium Level */ - TC_CCAINTLVL_HI_gc = (0x03<<0), /* High Level */ -} TC_CCAINTLVL_t; - -/* Timer/Counter Command */ -typedef enum TC_CMD_enum -{ - TC_CMD_NONE_gc = (0x00<<2), /* No Command */ - TC_CMD_UPDATE_gc = (0x01<<2), /* Force Update */ - TC_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ - TC_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ -} TC_CMD_t; - -/* Fault Detect Action */ -typedef enum AWEX_FDACT_enum -{ - AWEX_FDACT_NONE_gc = (0x00<<0), /* No Fault Protection */ - AWEX_FDACT_CLEAROE_gc = (0x01<<0), /* Clear Output Enable Bits */ - AWEX_FDACT_CLEARDIR_gc = (0x03<<0), /* Clear I/O Port Direction Bits */ -} AWEX_FDACT_t; - -/* High Resolution Enable */ -typedef enum HIRES_HREN_enum -{ - HIRES_HREN_NONE_gc = (0x00<<0), /* No Fault Protection */ - HIRES_HREN_TC0_gc = (0x01<<0), /* Enable High Resolution on Timer/Counter 0 */ - HIRES_HREN_TC1_gc = (0x02<<0), /* Enable High Resolution on Timer/Counter 1 */ - HIRES_HREN_BOTH_gc = (0x03<<0), /* Enable High Resolution both Timer/Counters */ -} HIRES_HREN_t; - - -/* --------------------------------------------------------------------------- -USART - Universal Asynchronous Receiver-Transmitter --------------------------------------------------------------------------- -*/ - -/* Universal Synchronous/Asynchronous Receiver/Transmitter */ -typedef struct USART_struct -{ - register8_t DATA; /* Data Register */ - register8_t STATUS; /* Status Register */ - register8_t reserved_0x02; - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t CTRLC; /* Control Register C */ - register8_t BAUDCTRLA; /* Baud Rate Control Register A */ - register8_t BAUDCTRLB; /* Baud Rate Control Register B */ -} USART_t; - -/* Receive Complete Interrupt level */ -typedef enum USART_RXCINTLVL_enum -{ - USART_RXCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ - USART_RXCINTLVL_LO_gc = (0x01<<4), /* Low Level */ - USART_RXCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ - USART_RXCINTLVL_HI_gc = (0x03<<4), /* High Level */ -} USART_RXCINTLVL_t; - -/* Transmit Complete Interrupt level */ -typedef enum USART_TXCINTLVL_enum -{ - USART_TXCINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ - USART_TXCINTLVL_LO_gc = (0x01<<2), /* Low Level */ - USART_TXCINTLVL_MED_gc = (0x02<<2), /* Medium Level */ - USART_TXCINTLVL_HI_gc = (0x03<<2), /* High Level */ -} USART_TXCINTLVL_t; - -/* Data Register Empty Interrupt level */ -typedef enum USART_DREINTLVL_enum -{ - USART_DREINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - USART_DREINTLVL_LO_gc = (0x01<<0), /* Low Level */ - USART_DREINTLVL_MED_gc = (0x02<<0), /* Medium Level */ - USART_DREINTLVL_HI_gc = (0x03<<0), /* High Level */ -} USART_DREINTLVL_t; - -/* Character Size */ -typedef enum USART_CHSIZE_enum -{ - USART_CHSIZE_5BIT_gc = (0x00<<0), /* Character size: 5 bit */ - USART_CHSIZE_6BIT_gc = (0x01<<0), /* Character size: 6 bit */ - USART_CHSIZE_7BIT_gc = (0x02<<0), /* Character size: 7 bit */ - USART_CHSIZE_8BIT_gc = (0x03<<0), /* Character size: 8 bit */ - USART_CHSIZE_9BIT_gc = (0x07<<0), /* Character size: 9 bit */ -} USART_CHSIZE_t; - -/* Communication Mode */ -typedef enum USART_CMODE_enum -{ - USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6), /* Asynchronous Mode */ - USART_CMODE_SYNCHRONOUS_gc = (0x01<<6), /* Synchronous Mode */ - USART_CMODE_IRDA_gc = (0x02<<6), /* IrDA Mode */ - USART_CMODE_MSPI_gc = (0x03<<6), /* Master SPI Mode */ -} USART_CMODE_t; - -/* Parity Mode */ -typedef enum USART_PMODE_enum -{ - USART_PMODE_DISABLED_gc = (0x00<<4), /* No Parity */ - USART_PMODE_EVEN_gc = (0x02<<4), /* Even Parity */ - USART_PMODE_ODD_gc = (0x03<<4), /* Odd Parity */ -} USART_PMODE_t; - - -/* --------------------------------------------------------------------------- -SPI - Serial Peripheral Interface --------------------------------------------------------------------------- -*/ - -/* Serial Peripheral Interface */ -typedef struct SPI_struct -{ - register8_t CTRL; /* Control Register */ - register8_t INTCTRL; /* Interrupt Control Register */ - register8_t STATUS; /* Status Register */ - register8_t DATA; /* Data Register */ -} SPI_t; - -/* SPI Mode */ -typedef enum SPI_MODE_enum -{ - SPI_MODE_0_gc = (0x00<<2), /* SPI Mode 0 */ - SPI_MODE_1_gc = (0x01<<2), /* SPI Mode 1 */ - SPI_MODE_2_gc = (0x02<<2), /* SPI Mode 2 */ - SPI_MODE_3_gc = (0x03<<2), /* SPI Mode 3 */ -} SPI_MODE_t; - -/* Prescaler setting */ -typedef enum SPI_PRESCALER_enum -{ - SPI_PRESCALER_DIV4_gc = (0x00<<0), /* System Clock / 4 */ - SPI_PRESCALER_DIV16_gc = (0x01<<0), /* System Clock / 16 */ - SPI_PRESCALER_DIV64_gc = (0x02<<0), /* System Clock / 64 */ - SPI_PRESCALER_DIV128_gc = (0x03<<0), /* System Clock / 128 */ -} SPI_PRESCALER_t; - -/* Interrupt level */ -typedef enum SPI_INTLVL_enum -{ - SPI_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - SPI_INTLVL_LO_gc = (0x01<<0), /* Low Level */ - SPI_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ - SPI_INTLVL_HI_gc = (0x03<<0), /* High Level */ -} SPI_INTLVL_t; - - -/* --------------------------------------------------------------------------- -IRCOM - IR Communication Module --------------------------------------------------------------------------- -*/ - -/* IR Communication Module */ -typedef struct IRCOM_struct -{ - register8_t TXPLCTRL; /* IrDA Transmitter Pulse Length Control Register */ - register8_t RXPLCTRL; /* IrDA Receiver Pulse Length Control Register */ - register8_t CTRL; /* Control Register */ -} IRCOM_t; - -/* Event channel selection */ -typedef enum IRDA_EVSEL_enum -{ - IRDA_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ - IRDA_EVSEL_0_gc = (0x08<<0), /* Event Channel 0 */ - IRDA_EVSEL_1_gc = (0x09<<0), /* Event Channel 1 */ - IRDA_EVSEL_2_gc = (0x0A<<0), /* Event Channel 2 */ - IRDA_EVSEL_3_gc = (0x0B<<0), /* Event Channel 3 */ - IRDA_EVSEL_4_gc = (0x0C<<0), /* Event Channel 4 */ - IRDA_EVSEL_5_gc = (0x0D<<0), /* Event Channel 5 */ - IRDA_EVSEL_6_gc = (0x0E<<0), /* Event Channel 6 */ - IRDA_EVSEL_7_gc = (0x0F<<0), /* Event Channel 7 */ -} IRDA_EVSEL_t; - - - -/* -========================================================================== -IO Module Instances. Mapped to memory. -========================================================================== -*/ - -#define VPORT0 (*(VPORT_t *) 0x0010) /* Virtual Port 0 */ -#define VPORT1 (*(VPORT_t *) 0x0014) /* Virtual Port 1 */ -#define VPORT2 (*(VPORT_t *) 0x0018) /* Virtual Port 2 */ -#define VPORT3 (*(VPORT_t *) 0x001C) /* Virtual Port 3 */ -#define OCD (*(OCD_t *) 0x002E) /* On-Chip Debug System */ -#define CLK (*(CLK_t *) 0x0040) /* Clock System */ -#define SLEEP (*(SLEEP_t *) 0x0048) /* Sleep Controller */ -#define OSC (*(OSC_t *) 0x0050) /* Oscillator Control */ -#define DFLLRC32M (*(DFLL_t *) 0x0060) /* DFLL for 32MHz RC Oscillator */ -#define DFLLRC2M (*(DFLL_t *) 0x0068) /* DFLL for 2MHz RC Oscillator */ -#define PR (*(PR_t *) 0x0070) /* Power Reduction */ -#define RST (*(RST_t *) 0x0078) /* Reset Controller */ -#define WDT (*(WDT_t *) 0x0080) /* Watch-Dog Timer */ -#define MCU (*(MCU_t *) 0x0090) /* MCU Control */ -#define PMIC (*(PMIC_t *) 0x00A0) /* Programmable Interrupt Controller */ -#define PORTCFG (*(PORTCFG_t *) 0x00B0) /* Port Configuration */ -#define CRC (*(CRC_t *) 0x00D0) /* Cyclic Redundancy Checker */ -#define EVSYS (*(EVSYS_t *) 0x0180) /* Event System */ -#define NVM (*(NVM_t *) 0x01C0) /* Non Volatile Memory Controller */ -#define ADCA (*(ADC_t *) 0x0200) /* Analog to Digital Converter A */ -#define DACB (*(DAC_t *) 0x0320) /* Digital to Analog Converter B */ -#define ACA (*(AC_t *) 0x0380) /* Analog Comparator A */ -#define ACB (*(AC_t *) 0x0390) /* Analog Comparator B */ -#define RTC (*(RTC_t *) 0x0400) /* Real-Time Counter */ -#define TWIC (*(TWI_t *) 0x0480) /* Two-Wire Interface C */ -#define TWIE (*(TWI_t *) 0x04A0) /* Two-Wire Interface */ -#define PORTA (*(PORT_t *) 0x0600) /* Port A */ -#define PORTB (*(PORT_t *) 0x0620) /* Port B */ -#define PORTC (*(PORT_t *) 0x0640) /* Port C */ -#define PORTD (*(PORT_t *) 0x0660) /* Port D */ -#define PORTE (*(PORT_t *) 0x0680) /* Port E */ -#define PORTF (*(PORT_t *) 0x06A0) /* Port F */ -#define PORTR (*(PORT_t *) 0x07E0) /* Port R */ -#define TCC0 (*(TC0_t *) 0x0800) /* Timer/Counter C0 */ -#define TCC1 (*(TC1_t *) 0x0840) /* Timer/Counter C1 */ -#define AWEXC (*(AWEX_t *) 0x0880) /* Advanced Waveform Extension C */ -#define HIRESC (*(HIRES_t *) 0x0890) /* High-Resolution Extension C */ -#define USARTC0 (*(USART_t *) 0x08A0) /* Universal Asynchronous Receiver-Transmitter C0 */ -#define SPIC (*(SPI_t *) 0x08C0) /* Serial Peripheral Interface C */ -#define IRCOM (*(IRCOM_t *) 0x08F8) /* IR Communication Module */ -#define TCD0 (*(TC0_t *) 0x0900) /* Timer/Counter D0 */ -#define USARTD0 (*(USART_t *) 0x09A0) /* Universal Asynchronous Receiver-Transmitter D0 */ -#define SPID (*(SPI_t *) 0x09C0) /* Serial Peripheral Interface D */ -#define TCE0 (*(TC0_t *) 0x0A00) /* Timer/Counter E0 */ -#define AWEXE (*(AWEX_t *) 0x0A80) /* Advanced Waveform Extension E */ -#define USARTE0 (*(USART_t *) 0x0AA0) /* Universal Asynchronous Receiver-Transmitter E0 */ -#define SPIE (*(SPI_t *) 0x0AC0) /* Serial Peripheral Interface E */ -#define TCF0 (*(TC0_t *) 0x0B00) /* Timer/Counter F0 */ - - -#endif /* !defined (__ASSEMBLER__) */ - - -/* ========== Flattened fully qualified IO register names ========== */ - -/* GPIO - General Purpose IO Registers */ -#define GPIO_GPIOR0 _SFR_MEM8(0x0000) -#define GPIO_GPIOR1 _SFR_MEM8(0x0001) -#define GPIO_GPIOR2 _SFR_MEM8(0x0002) -#define GPIO_GPIOR3 _SFR_MEM8(0x0003) -#define GPIO_GPIOR4 _SFR_MEM8(0x0004) -#define GPIO_GPIOR5 _SFR_MEM8(0x0005) -#define GPIO_GPIOR6 _SFR_MEM8(0x0006) -#define GPIO_GPIOR7 _SFR_MEM8(0x0007) -#define GPIO_GPIOR8 _SFR_MEM8(0x0008) -#define GPIO_GPIOR9 _SFR_MEM8(0x0009) -#define GPIO_GPIORA _SFR_MEM8(0x000A) -#define GPIO_GPIORB _SFR_MEM8(0x000B) -#define GPIO_GPIORC _SFR_MEM8(0x000C) -#define GPIO_GPIORD _SFR_MEM8(0x000D) -#define GPIO_GPIORE _SFR_MEM8(0x000E) -#define GPIO_GPIORF _SFR_MEM8(0x000F) - -/* VPORT0 - Virtual Port 0 */ -#define VPORT0_DIR _SFR_MEM8(0x0010) -#define VPORT0_OUT _SFR_MEM8(0x0011) -#define VPORT0_IN _SFR_MEM8(0x0012) -#define VPORT0_INTFLAGS _SFR_MEM8(0x0013) - -/* VPORT1 - Virtual Port 1 */ -#define VPORT1_DIR _SFR_MEM8(0x0014) -#define VPORT1_OUT _SFR_MEM8(0x0015) -#define VPORT1_IN _SFR_MEM8(0x0016) -#define VPORT1_INTFLAGS _SFR_MEM8(0x0017) - -/* VPORT2 - Virtual Port 2 */ -#define VPORT2_DIR _SFR_MEM8(0x0018) -#define VPORT2_OUT _SFR_MEM8(0x0019) -#define VPORT2_IN _SFR_MEM8(0x001A) -#define VPORT2_INTFLAGS _SFR_MEM8(0x001B) - -/* VPORT3 - Virtual Port 3 */ -#define VPORT3_DIR _SFR_MEM8(0x001C) -#define VPORT3_OUT _SFR_MEM8(0x001D) -#define VPORT3_IN _SFR_MEM8(0x001E) -#define VPORT3_INTFLAGS _SFR_MEM8(0x001F) - -/* OCD - On-Chip Debug System */ -#define OCD_OCDR0 _SFR_MEM8(0x002E) -#define OCD_OCDR1 _SFR_MEM8(0x002F) - -/* CPU - CPU Registers */ -#define CPU_CCP _SFR_MEM8(0x0034) -#define CPU_RAMPD _SFR_MEM8(0x0038) -#define CPU_RAMPX _SFR_MEM8(0x0039) -#define CPU_RAMPY _SFR_MEM8(0x003A) -#define CPU_RAMPZ _SFR_MEM8(0x003B) -#define CPU_EIND _SFR_MEM8(0x003C) -#define CPU_SPL _SFR_MEM8(0x003D) -#define CPU_SPH _SFR_MEM8(0x003E) -#define CPU_SREG _SFR_MEM8(0x003F) - -/* CLK - Clock System */ -#define CLK_CTRL _SFR_MEM8(0x0040) -#define CLK_PSCTRL _SFR_MEM8(0x0041) -#define CLK_LOCK _SFR_MEM8(0x0042) -#define CLK_RTCCTRL _SFR_MEM8(0x0043) - -/* SLEEP - Sleep Controller */ -#define SLEEP_CTRL _SFR_MEM8(0x0048) - -/* OSC - Oscillator Control */ -#define OSC_CTRL _SFR_MEM8(0x0050) -#define OSC_STATUS _SFR_MEM8(0x0051) -#define OSC_XOSCCTRL _SFR_MEM8(0x0052) -#define OSC_XOSCFAIL _SFR_MEM8(0x0053) -#define OSC_RC32KCAL _SFR_MEM8(0x0054) -#define OSC_PLLCTRL _SFR_MEM8(0x0055) -#define OSC_DFLLCTRL _SFR_MEM8(0x0056) - -/* DFLLRC32M - DFLL for 32MHz RC Oscillator */ -#define DFLLRC32M_CTRL _SFR_MEM8(0x0060) -#define DFLLRC32M_CALA _SFR_MEM8(0x0062) -#define DFLLRC32M_CALB _SFR_MEM8(0x0063) -#define DFLLRC32M_COMP0 _SFR_MEM8(0x0064) -#define DFLLRC32M_COMP1 _SFR_MEM8(0x0065) -#define DFLLRC32M_COMP2 _SFR_MEM8(0x0066) - -/* DFLLRC2M - DFLL for 2MHz RC Oscillator */ -#define DFLLRC2M_CTRL _SFR_MEM8(0x0068) -#define DFLLRC2M_CALA _SFR_MEM8(0x006A) -#define DFLLRC2M_CALB _SFR_MEM8(0x006B) -#define DFLLRC2M_COMP0 _SFR_MEM8(0x006C) -#define DFLLRC2M_COMP1 _SFR_MEM8(0x006D) -#define DFLLRC2M_COMP2 _SFR_MEM8(0x006E) - -/* PR - Power Reduction */ -#define PR_PRGEN _SFR_MEM8(0x0070) -#define PR_PRPA _SFR_MEM8(0x0071) -#define PR_PRPC _SFR_MEM8(0x0073) -#define PR_PRPD _SFR_MEM8(0x0074) -#define PR_PRPE _SFR_MEM8(0x0075) -#define PR_PRPF _SFR_MEM8(0x0076) - -/* RST - Reset Controller */ -#define RST_STATUS _SFR_MEM8(0x0078) -#define RST_CTRL _SFR_MEM8(0x0079) - -/* WDT - Watch-Dog Timer */ -#define WDT_CTRL _SFR_MEM8(0x0080) -#define WDT_WINCTRL _SFR_MEM8(0x0081) -#define WDT_STATUS _SFR_MEM8(0x0082) - -/* MCU - MCU Control */ -#define MCU_DEVID0 _SFR_MEM8(0x0090) -#define MCU_DEVID1 _SFR_MEM8(0x0091) -#define MCU_DEVID2 _SFR_MEM8(0x0092) -#define MCU_REVID _SFR_MEM8(0x0093) -#define MCU_JTAGUID _SFR_MEM8(0x0094) -#define MCU_MCUCR _SFR_MEM8(0x0096) -#define MCU_EVSYSLOCK _SFR_MEM8(0x0098) -#define MCU_AWEXLOCK _SFR_MEM8(0x0099) - -/* PMIC - Programmable Interrupt Controller */ -#define PMIC_STATUS _SFR_MEM8(0x00A0) -#define PMIC_INTPRI _SFR_MEM8(0x00A1) -#define PMIC_CTRL _SFR_MEM8(0x00A2) - -/* PORTCFG - Port Configuration */ -#define PORTCFG_MPCMASK _SFR_MEM8(0x00B0) -#define PORTCFG_VPCTRLA _SFR_MEM8(0x00B2) -#define PORTCFG_VPCTRLB _SFR_MEM8(0x00B3) -#define PORTCFG_CLKEVOUT _SFR_MEM8(0x00B4) - -/* CRC - Cyclic Redundancy Checker */ -#define CRC_CTRL _SFR_MEM8(0x00D0) -#define CRC_STATUS _SFR_MEM8(0x00D1) -#define CRC_DATAIN _SFR_MEM8(0x00D3) -#define CRC_CHECKSUM0 _SFR_MEM8(0x00D4) -#define CRC_CHECKSUM1 _SFR_MEM8(0x00D5) -#define CRC_CHECKSUM2 _SFR_MEM8(0x00D6) -#define CRC_CHECKSUM3 _SFR_MEM8(0x00D7) - -/* EVSYS - Event System */ -#define EVSYS_CH0MUX _SFR_MEM8(0x0180) -#define EVSYS_CH1MUX _SFR_MEM8(0x0181) -#define EVSYS_CH2MUX _SFR_MEM8(0x0182) -#define EVSYS_CH3MUX _SFR_MEM8(0x0183) -#define EVSYS_CH0CTRL _SFR_MEM8(0x0188) -#define EVSYS_CH1CTRL _SFR_MEM8(0x0189) -#define EVSYS_CH2CTRL _SFR_MEM8(0x018A) -#define EVSYS_CH3CTRL _SFR_MEM8(0x018B) -#define EVSYS_STROBE _SFR_MEM8(0x0190) -#define EVSYS_DATA _SFR_MEM8(0x0191) - -/* NVM - Non Volatile Memory Controller */ -#define NVM_ADDR0 _SFR_MEM8(0x01C0) -#define NVM_ADDR1 _SFR_MEM8(0x01C1) -#define NVM_ADDR2 _SFR_MEM8(0x01C2) -#define NVM_DATA0 _SFR_MEM8(0x01C4) -#define NVM_DATA1 _SFR_MEM8(0x01C5) -#define NVM_DATA2 _SFR_MEM8(0x01C6) -#define NVM_CMD _SFR_MEM8(0x01CA) -#define NVM_CTRLA _SFR_MEM8(0x01CB) -#define NVM_CTRLB _SFR_MEM8(0x01CC) -#define NVM_INTCTRL _SFR_MEM8(0x01CD) -#define NVM_STATUS _SFR_MEM8(0x01CF) -#define NVM_LOCKBITS _SFR_MEM8(0x01D0) - -/* ADCA - Analog to Digital Converter A */ -#define ADCA_CTRLA _SFR_MEM8(0x0200) -#define ADCA_CTRLB _SFR_MEM8(0x0201) -#define ADCA_REFCTRL _SFR_MEM8(0x0202) -#define ADCA_EVCTRL _SFR_MEM8(0x0203) -#define ADCA_PRESCALER _SFR_MEM8(0x0204) -#define ADCA_INTFLAGS _SFR_MEM8(0x0206) -#define ADCA_CAL _SFR_MEM16(0x020C) -#define ADCA_CH0RES _SFR_MEM16(0x0210) -#define ADCA_CMP _SFR_MEM16(0x0218) -#define ADCA_CH0_CTRL _SFR_MEM8(0x0220) -#define ADCA_CH0_MUXCTRL _SFR_MEM8(0x0221) -#define ADCA_CH0_INTCTRL _SFR_MEM8(0x0222) -#define ADCA_CH0_INTFLAGS _SFR_MEM8(0x0223) -#define ADCA_CH0_RES _SFR_MEM16(0x0224) - -/* DACB - Digital to Analog Converter B */ - -/* ACA - Analog Comparator A */ -#define ACA_AC0CTRL _SFR_MEM8(0x0380) -#define ACA_AC1CTRL _SFR_MEM8(0x0381) -#define ACA_AC0MUXCTRL _SFR_MEM8(0x0382) -#define ACA_AC1MUXCTRL _SFR_MEM8(0x0383) -#define ACA_CTRLA _SFR_MEM8(0x0384) -#define ACA_CTRLB _SFR_MEM8(0x0385) -#define ACA_WINCTRL _SFR_MEM8(0x0386) -#define ACA_STATUS _SFR_MEM8(0x0387) - -/* ACB - Analog Comparator B */ -#define ACB_AC0CTRL _SFR_MEM8(0x0390) -#define ACB_AC1CTRL _SFR_MEM8(0x0391) -#define ACB_AC0MUXCTRL _SFR_MEM8(0x0392) -#define ACB_AC1MUXCTRL _SFR_MEM8(0x0393) -#define ACB_CTRLA _SFR_MEM8(0x0394) -#define ACB_CTRLB _SFR_MEM8(0x0395) -#define ACB_WINCTRL _SFR_MEM8(0x0396) -#define ACB_STATUS _SFR_MEM8(0x0397) - -/* RTC - Real-Time Counter */ -#define RTC_CTRL _SFR_MEM8(0x0400) -#define RTC_STATUS _SFR_MEM8(0x0401) -#define RTC_INTCTRL _SFR_MEM8(0x0402) -#define RTC_INTFLAGS _SFR_MEM8(0x0403) -#define RTC_TEMP _SFR_MEM8(0x0404) -#define RTC_CNT _SFR_MEM16(0x0408) -#define RTC_PER _SFR_MEM16(0x040A) -#define RTC_COMP _SFR_MEM16(0x040C) - -/* TWIC - Two-Wire Interface C */ -#define TWIC_CTRL _SFR_MEM8(0x0480) -#define TWIC_MASTER_CTRLA _SFR_MEM8(0x0482) -#define TWIC_MASTER_CTRLB _SFR_MEM8(0x0483) -#define TWIC_MASTER_CTRLC _SFR_MEM8(0x0484) -#define TWIC_MASTER_STATUS _SFR_MEM8(0x0485) -#define TWIC_MASTER_BAUD _SFR_MEM8(0x0486) -#define TWIC_MASTER_ADDR _SFR_MEM8(0x0487) -#define TWIC_MASTER_DATA _SFR_MEM8(0x0488) -#define TWIC_SLAVE_CTRLA _SFR_MEM8(0x0488) -#define TWIC_SLAVE_CTRLB _SFR_MEM8(0x0489) -#define TWIC_SLAVE_STATUS _SFR_MEM8(0x048A) -#define TWIC_SLAVE_ADDR _SFR_MEM8(0x048B) -#define TWIC_SLAVE_DATA _SFR_MEM8(0x048C) -#define TWIC_SLAVE_ADDRMASK _SFR_MEM8(0x048D) - -/* TWIE - Two-Wire Interface E */ -#define TWIE_CTRL _SFR_MEM8(0x04A0) -#define TWIE_MASTER_CTRLA _SFR_MEM8(0x04A1) -#define TWIE_MASTER_CTRLB _SFR_MEM8(0x04A2) -#define TWIE_MASTER_CTRLC _SFR_MEM8(0x04A3) -#define TWIE_MASTER_STATUS _SFR_MEM8(0x04A4) -#define TWIE_MASTER_BAUD _SFR_MEM8(0x04A5) -#define TWIE_MASTER_ADDR _SFR_MEM8(0x04A6) -#define TWIE_MASTER_DATA _SFR_MEM8(0x04A7) -#define TWIE_SLAVE_CTRLA _SFR_MEM8(0x04A8) -#define TWIE_SLAVE_CTRLB _SFR_MEM8(0x04A9) -#define TWIE_SLAVE_STATUS _SFR_MEM8(0x04AA) -#define TWIE_SLAVE_ADDR _SFR_MEM8(0x04AB) -#define TWIE_SLAVE_DATA _SFR_MEM8(0x04AC) -#define TWIE_SLAVE_ADDRMASK _SFR_MEM8(0x04AD) - -/* PORTA - Port A */ -#define PORTA_DIR _SFR_MEM8(0x0600) -#define PORTA_DIRSET _SFR_MEM8(0x0601) -#define PORTA_DIRCLR _SFR_MEM8(0x0602) -#define PORTA_DIRTGL _SFR_MEM8(0x0603) -#define PORTA_OUT _SFR_MEM8(0x0604) -#define PORTA_OUTSET _SFR_MEM8(0x0605) -#define PORTA_OUTCLR _SFR_MEM8(0x0606) -#define PORTA_OUTTGL _SFR_MEM8(0x0607) -#define PORTA_IN _SFR_MEM8(0x0608) -#define PORTA_INTCTRL _SFR_MEM8(0x0609) -#define PORTA_INT0MASK _SFR_MEM8(0x060A) -#define PORTA_INT1MASK _SFR_MEM8(0x060B) -#define PORTA_INTFLAGS _SFR_MEM8(0x060C) -#define PORTA_PIN0CTRL _SFR_MEM8(0x0610) -#define PORTA_PIN1CTRL _SFR_MEM8(0x0611) -#define PORTA_PIN2CTRL _SFR_MEM8(0x0612) -#define PORTA_PIN3CTRL _SFR_MEM8(0x0613) -#define PORTA_PIN4CTRL _SFR_MEM8(0x0614) -#define PORTA_PIN5CTRL _SFR_MEM8(0x0615) -#define PORTA_PIN6CTRL _SFR_MEM8(0x0616) -#define PORTA_PIN7CTRL _SFR_MEM8(0x0617) - -/* PORTB - Port B */ -#define PORTB_DIR _SFR_MEM8(0x0620) -#define PORTB_DIRSET _SFR_MEM8(0x0621) -#define PORTB_DIRCLR _SFR_MEM8(0x0622) -#define PORTB_DIRTGL _SFR_MEM8(0x0623) -#define PORTB_OUT _SFR_MEM8(0x0624) -#define PORTB_OUTSET _SFR_MEM8(0x0625) -#define PORTB_OUTCLR _SFR_MEM8(0x0626) -#define PORTB_OUTTGL _SFR_MEM8(0x0627) -#define PORTB_IN _SFR_MEM8(0x0628) -#define PORTB_INTCTRL _SFR_MEM8(0x0629) -#define PORTB_INT0MASK _SFR_MEM8(0x062A) -#define PORTB_INT1MASK _SFR_MEM8(0x062B) -#define PORTB_INTFLAGS _SFR_MEM8(0x062C) -#define PORTB_PIN0CTRL _SFR_MEM8(0x0630) -#define PORTB_PIN1CTRL _SFR_MEM8(0x0631) -#define PORTB_PIN2CTRL _SFR_MEM8(0x0632) -#define PORTB_PIN3CTRL _SFR_MEM8(0x0633) -#define PORTB_PIN4CTRL _SFR_MEM8(0x0634) -#define PORTB_PIN5CTRL _SFR_MEM8(0x0635) -#define PORTB_PIN6CTRL _SFR_MEM8(0x0636) -#define PORTB_PIN7CTRL _SFR_MEM8(0x0637) - -/* PORTC - Port C */ -#define PORTC_DIR _SFR_MEM8(0x0640) -#define PORTC_DIRSET _SFR_MEM8(0x0641) -#define PORTC_DIRCLR _SFR_MEM8(0x0642) -#define PORTC_DIRTGL _SFR_MEM8(0x0643) -#define PORTC_OUT _SFR_MEM8(0x0644) -#define PORTC_OUTSET _SFR_MEM8(0x0645) -#define PORTC_OUTCLR _SFR_MEM8(0x0646) -#define PORTC_OUTTGL _SFR_MEM8(0x0647) -#define PORTC_IN _SFR_MEM8(0x0648) -#define PORTC_INTCTRL _SFR_MEM8(0x0649) -#define PORTC_INT0MASK _SFR_MEM8(0x064A) -#define PORTC_INT1MASK _SFR_MEM8(0x064B) -#define PORTC_INTFLAGS _SFR_MEM8(0x064C) -#define PORTC_PIN0CTRL _SFR_MEM8(0x0650) -#define PORTC_PIN1CTRL _SFR_MEM8(0x0651) -#define PORTC_PIN2CTRL _SFR_MEM8(0x0652) -#define PORTC_PIN3CTRL _SFR_MEM8(0x0653) -#define PORTC_PIN4CTRL _SFR_MEM8(0x0654) -#define PORTC_PIN5CTRL _SFR_MEM8(0x0655) -#define PORTC_PIN6CTRL _SFR_MEM8(0x0656) -#define PORTC_PIN7CTRL _SFR_MEM8(0x0657) - -/* PORTD - Port D */ -#define PORTD_DIR _SFR_MEM8(0x0660) -#define PORTD_DIRSET _SFR_MEM8(0x0661) -#define PORTD_DIRCLR _SFR_MEM8(0x0662) -#define PORTD_DIRTGL _SFR_MEM8(0x0663) -#define PORTD_OUT _SFR_MEM8(0x0664) -#define PORTD_OUTSET _SFR_MEM8(0x0665) -#define PORTD_OUTCLR _SFR_MEM8(0x0666) -#define PORTD_OUTTGL _SFR_MEM8(0x0667) -#define PORTD_IN _SFR_MEM8(0x0668) -#define PORTD_INTCTRL _SFR_MEM8(0x0669) -#define PORTD_INT0MASK _SFR_MEM8(0x066A) -#define PORTD_INT1MASK _SFR_MEM8(0x066B) -#define PORTD_INTFLAGS _SFR_MEM8(0x066C) -#define PORTD_PIN0CTRL _SFR_MEM8(0x0670) -#define PORTD_PIN1CTRL _SFR_MEM8(0x0671) -#define PORTD_PIN2CTRL _SFR_MEM8(0x0672) -#define PORTD_PIN3CTRL _SFR_MEM8(0x0673) -#define PORTD_PIN4CTRL _SFR_MEM8(0x0674) -#define PORTD_PIN5CTRL _SFR_MEM8(0x0675) -#define PORTD_PIN6CTRL _SFR_MEM8(0x0676) -#define PORTD_PIN7CTRL _SFR_MEM8(0x0677) - -/* PORTE - Port E */ -#define PORTE_DIR _SFR_MEM8(0x0680) -#define PORTE_DIRSET _SFR_MEM8(0x0681) -#define PORTE_DIRCLR _SFR_MEM8(0x0682) -#define PORTE_DIRTGL _SFR_MEM8(0x0683) -#define PORTE_OUT _SFR_MEM8(0x0684) -#define PORTE_OUTSET _SFR_MEM8(0x0685) -#define PORTE_OUTCLR _SFR_MEM8(0x0686) -#define PORTE_OUTTGL _SFR_MEM8(0x0687) -#define PORTE_IN _SFR_MEM8(0x0688) -#define PORTE_INTCTRL _SFR_MEM8(0x0689) -#define PORTE_INT0MASK _SFR_MEM8(0x068A) -#define PORTE_INT1MASK _SFR_MEM8(0x068B) -#define PORTE_INTFLAGS _SFR_MEM8(0x068C) -#define PORTE_PIN0CTRL _SFR_MEM8(0x0690) -#define PORTE_PIN1CTRL _SFR_MEM8(0x0691) -#define PORTE_PIN2CTRL _SFR_MEM8(0x0692) -#define PORTE_PIN3CTRL _SFR_MEM8(0x0693) -#define PORTE_PIN4CTRL _SFR_MEM8(0x0694) -#define PORTE_PIN5CTRL _SFR_MEM8(0x0695) -#define PORTE_PIN6CTRL _SFR_MEM8(0x0696) -#define PORTE_PIN7CTRL _SFR_MEM8(0x0697) - -/* PORTF - Port F */ -#define PORTF_DIR _SFR_MEM8(0x06A0) -#define PORTF_DIRSET _SFR_MEM8(0x06A1) -#define PORTF_DIRCLR _SFR_MEM8(0x06A2) -#define PORTF_DIRTGL _SFR_MEM8(0x06A3) -#define PORTF_OUT _SFR_MEM8(0x06A4) -#define PORTF_OUTSET _SFR_MEM8(0x06A5) -#define PORTF_OUTCLR _SFR_MEM8(0x06A6) -#define PORTF_OUTTGL _SFR_MEM8(0x06A7) -#define PORTF_IN _SFR_MEM8(0x06A8) -#define PORTF_INTCTRL _SFR_MEM8(0x06A9) -#define PORTF_INT0MASK _SFR_MEM8(0x06AA) -#define PORTF_INT1MASK _SFR_MEM8(0x06AB) -#define PORTF_INTFLAGS _SFR_MEM8(0x06AC) -#define PORTF_PIN0CTRL _SFR_MEM8(0x06B0) -#define PORTF_PIN1CTRL _SFR_MEM8(0x06B1) -#define PORTF_PIN2CTRL _SFR_MEM8(0x06B2) -#define PORTF_PIN3CTRL _SFR_MEM8(0x06B3) -#define PORTF_PIN4CTRL _SFR_MEM8(0x06B4) -#define PORTF_PIN5CTRL _SFR_MEM8(0x06B5) -#define PORTF_PIN6CTRL _SFR_MEM8(0x06B6) -#define PORTF_PIN7CTRL _SFR_MEM8(0x06B7) - -/* PORTR - Port R */ -#define PORTR_DIR _SFR_MEM8(0x07E0) -#define PORTR_DIRSET _SFR_MEM8(0x07E1) -#define PORTR_DIRCLR _SFR_MEM8(0x07E2) -#define PORTR_DIRTGL _SFR_MEM8(0x07E3) -#define PORTR_OUT _SFR_MEM8(0x07E4) -#define PORTR_OUTSET _SFR_MEM8(0x07E5) -#define PORTR_OUTCLR _SFR_MEM8(0x07E6) -#define PORTR_OUTTGL _SFR_MEM8(0x07E7) -#define PORTR_IN _SFR_MEM8(0x07E8) -#define PORTR_INTCTRL _SFR_MEM8(0x07E9) -#define PORTR_INT0MASK _SFR_MEM8(0x07EA) -#define PORTR_INT1MASK _SFR_MEM8(0x07EB) -#define PORTR_INTFLAGS _SFR_MEM8(0x07EC) -#define PORTR_PIN0CTRL _SFR_MEM8(0x07F0) -#define PORTR_PIN1CTRL _SFR_MEM8(0x07F1) -#define PORTR_PIN2CTRL _SFR_MEM8(0x07F2) -#define PORTR_PIN3CTRL _SFR_MEM8(0x07F3) -#define PORTR_PIN4CTRL _SFR_MEM8(0x07F4) -#define PORTR_PIN5CTRL _SFR_MEM8(0x07F5) -#define PORTR_PIN6CTRL _SFR_MEM8(0x07F6) -#define PORTR_PIN7CTRL _SFR_MEM8(0x07F7) - -/* TCC0 - Timer/Counter C0 */ -#define TCC0_CTRLA _SFR_MEM8(0x0800) -#define TCC0_CTRLB _SFR_MEM8(0x0801) -#define TCC0_CTRLC _SFR_MEM8(0x0802) -#define TCC0_CTRLD _SFR_MEM8(0x0803) -#define TCC0_CTRLE _SFR_MEM8(0x0804) -#define TCC0_INTCTRLA _SFR_MEM8(0x0806) -#define TCC0_INTCTRLB _SFR_MEM8(0x0807) -#define TCC0_CTRLFCLR _SFR_MEM8(0x0808) -#define TCC0_CTRLFSET _SFR_MEM8(0x0809) -#define TCC0_CTRLGCLR _SFR_MEM8(0x080A) -#define TCC0_CTRLGSET _SFR_MEM8(0x080B) -#define TCC0_INTFLAGS _SFR_MEM8(0x080C) -#define TCC0_TEMP _SFR_MEM8(0x080F) -#define TCC0_CNT _SFR_MEM16(0x0820) -#define TCC0_PER _SFR_MEM16(0x0826) -#define TCC0_CCA _SFR_MEM16(0x0828) -#define TCC0_CCB _SFR_MEM16(0x082A) -#define TCC0_CCC _SFR_MEM16(0x082C) -#define TCC0_CCD _SFR_MEM16(0x082E) -#define TCC0_PERBUF _SFR_MEM16(0x0836) -#define TCC0_CCABUF _SFR_MEM16(0x0838) -#define TCC0_CCBBUF _SFR_MEM16(0x083A) -#define TCC0_CCCBUF _SFR_MEM16(0x083C) -#define TCC0_CCDBUF _SFR_MEM16(0x083E) - -/* TCC1 - Timer/Counter C1 */ -#define TCC1_CTRLA _SFR_MEM8(0x0840) -#define TCC1_CTRLB _SFR_MEM8(0x0841) -#define TCC1_CTRLC _SFR_MEM8(0x0842) -#define TCC1_CTRLD _SFR_MEM8(0x0843) -#define TCC1_CTRLE _SFR_MEM8(0x0844) -#define TCC1_INTCTRLA _SFR_MEM8(0x0846) -#define TCC1_INTCTRLB _SFR_MEM8(0x0847) -#define TCC1_CTRLFCLR _SFR_MEM8(0x0848) -#define TCC1_CTRLFSET _SFR_MEM8(0x0849) -#define TCC1_CTRLGCLR _SFR_MEM8(0x084A) -#define TCC1_CTRLGSET _SFR_MEM8(0x084B) -#define TCC1_INTFLAGS _SFR_MEM8(0x084C) -#define TCC1_TEMP _SFR_MEM8(0x084F) -#define TCC1_CNT _SFR_MEM16(0x0860) -#define TCC1_PER _SFR_MEM16(0x0866) -#define TCC1_CCA _SFR_MEM16(0x0868) -#define TCC1_CCB _SFR_MEM16(0x086A) -#define TCC1_PERBUF _SFR_MEM16(0x0876) -#define TCC1_CCABUF _SFR_MEM16(0x0878) -#define TCC1_CCBBUF _SFR_MEM16(0x087A) - -/* AWEXC - Advanced Waveform Extension C */ -#define AWEXC_CTRL _SFR_MEM8(0x0880) -#define AWEXC_FDEMASK _SFR_MEM8(0x0882) -#define AWEXC_FDCTRL _SFR_MEM8(0x0883) -#define AWEXC_STATUS _SFR_MEM8(0x0884) -#define AWEXC_DTBOTH _SFR_MEM8(0x0886) -#define AWEXC_DTBOTHBUF _SFR_MEM8(0x0887) -#define AWEXC_DTLS _SFR_MEM8(0x0888) -#define AWEXC_DTHS _SFR_MEM8(0x0889) -#define AWEXC_DTLSBUF _SFR_MEM8(0x088A) -#define AWEXC_DTHSBUF _SFR_MEM8(0x088B) -#define AWEXC_OUTOVEN _SFR_MEM8(0x088C) - -/* HIRESC - High-Resolution Extension C */ -#define HIRESC_CTRLA _SFR_MEM8(0x0890) - -/* USARTC0 - Universal Asynchronous Receiver-Transmitter C0 */ -#define USARTC0_DATA _SFR_MEM8(0x08A0) -#define USARTC0_STATUS _SFR_MEM8(0x08A1) -#define USARTC0_CTRLA _SFR_MEM8(0x08A3) -#define USARTC0_CTRLB _SFR_MEM8(0x08A4) -#define USARTC0_CTRLC _SFR_MEM8(0x08A5) -#define USARTC0_BAUDCTRLA _SFR_MEM8(0x08A6) -#define USARTC0_BAUDCTRLB _SFR_MEM8(0x08A7) - -/* SPIC - Serial Peripheral Interface C */ -#define SPIC_CTRL _SFR_MEM8(0x08C0) -#define SPIC_INTCTRL _SFR_MEM8(0x08C1) -#define SPIC_STATUS _SFR_MEM8(0x08C2) -#define SPIC_DATA _SFR_MEM8(0x08C3) - -/* IRCOM - IR Communication Module */ -#define IRCOM_TXPLCTRL _SFR_MEM8(0x08F8) -#define IRCOM_RXPLCTRL _SFR_MEM8(0x08F9) -#define IRCOM_CTRL _SFR_MEM8(0x08FA) - -/* TCD0 - Timer/Counter D0 */ -#define TCD0_CTRLA _SFR_MEM8(0x0900) -#define TCD0_CTRLB _SFR_MEM8(0x0901) -#define TCD0_CTRLC _SFR_MEM8(0x0902) -#define TCD0_CTRLD _SFR_MEM8(0x0903) -#define TCD0_CTRLE _SFR_MEM8(0x0904) -#define TCD0_INTCTRLA _SFR_MEM8(0x0906) -#define TCD0_INTCTRLB _SFR_MEM8(0x0907) -#define TCD0_CTRLFCLR _SFR_MEM8(0x0908) -#define TCD0_CTRLFSET _SFR_MEM8(0x0909) -#define TCD0_CTRLGCLR _SFR_MEM8(0x090A) -#define TCD0_CTRLGSET _SFR_MEM8(0x090B) -#define TCD0_INTFLAGS _SFR_MEM8(0x090C) -#define TCD0_TEMP _SFR_MEM8(0x090F) -#define TCD0_CNT _SFR_MEM16(0x0920) -#define TCD0_PER _SFR_MEM16(0x0926) -#define TCD0_CCA _SFR_MEM16(0x0928) -#define TCD0_CCB _SFR_MEM16(0x092A) -#define TCD0_CCC _SFR_MEM16(0x092C) -#define TCD0_CCD _SFR_MEM16(0x092E) -#define TCD0_PERBUF _SFR_MEM16(0x0936) -#define TCD0_CCABUF _SFR_MEM16(0x0938) -#define TCD0_CCBBUF _SFR_MEM16(0x093A) -#define TCD0_CCCBUF _SFR_MEM16(0x093C) -#define TCD0_CCDBUF _SFR_MEM16(0x093E) - -/* USARTD0 - Universal Asynchronous Receiver-Transmitter D0 */ -#define USARTD0_DATA _SFR_MEM8(0x09A0) -#define USARTD0_STATUS _SFR_MEM8(0x09A1) -#define USARTD0_CTRLA _SFR_MEM8(0x09A3) -#define USARTD0_CTRLB _SFR_MEM8(0x09A4) -#define USARTD0_CTRLC _SFR_MEM8(0x09A5) -#define USARTD0_BAUDCTRLA _SFR_MEM8(0x09A6) -#define USARTD0_BAUDCTRLB _SFR_MEM8(0x09A7) - -/* SPID - Serial Peripheral Interface D */ -#define SPID_CTRL _SFR_MEM8(0x09C0) -#define SPID_INTCTRL _SFR_MEM8(0x09C1) -#define SPID_STATUS _SFR_MEM8(0x09C2) -#define SPID_DATA _SFR_MEM8(0x09C3) - -/* TCE0 - Timer/Counter E0 */ -#define TCE0_CTRLA _SFR_MEM8(0x0A00) -#define TCE0_CTRLB _SFR_MEM8(0x0A01) -#define TCE0_CTRLC _SFR_MEM8(0x0A02) -#define TCE0_CTRLD _SFR_MEM8(0x0A03) -#define TCE0_CTRLE _SFR_MEM8(0x0A04) -#define TCE0_INTCTRLA _SFR_MEM8(0x0A06) -#define TCE0_INTCTRLB _SFR_MEM8(0x0A07) -#define TCE0_CTRLFCLR _SFR_MEM8(0x0A08) -#define TCE0_CTRLFSET _SFR_MEM8(0x0A09) -#define TCE0_CTRLGCLR _SFR_MEM8(0x0A0A) -#define TCE0_CTRLGSET _SFR_MEM8(0x0A0B) -#define TCE0_INTFLAGS _SFR_MEM8(0x0A0C) -#define TCE0_TEMP _SFR_MEM8(0x0A0F) -#define TCE0_CNT _SFR_MEM16(0x0A20) -#define TCE0_PER _SFR_MEM16(0x0A26) -#define TCE0_CCA _SFR_MEM16(0x0A28) -#define TCE0_CCB _SFR_MEM16(0x0A2A) -#define TCE0_CCC _SFR_MEM16(0x0A2C) -#define TCE0_CCD _SFR_MEM16(0x0A2E) -#define TCE0_PERBUF _SFR_MEM16(0x0A36) -#define TCE0_CCABUF _SFR_MEM16(0x0A38) -#define TCE0_CCBBUF _SFR_MEM16(0x0A3A) -#define TCE0_CCCBUF _SFR_MEM16(0x0A3C) -#define TCE0_CCDBUF _SFR_MEM16(0x0A3E) - -/* AWEXE - Advanced Waveform Extension E */ -#define AWEXE_CTRL _SFR_MEM8(0x0A80) -#define AWEXE_FDEMASK _SFR_MEM8(0x0A82) -#define AWEXE_FDCTRL _SFR_MEM8(0x0A83) -#define AWEXE_STATUS _SFR_MEM8(0x0A84) -#define AWEXE_DTBOTH _SFR_MEM8(0x0A86) -#define AWEXE_DTBOTHBUF _SFR_MEM8(0x0A87) -#define AWEXE_DTLS _SFR_MEM8(0x0A88) -#define AWEXE_DTHS _SFR_MEM8(0x0A89) -#define AWEXE_DTLSBUF _SFR_MEM8(0x0A8A) -#define AWEXE_DTHSBUF _SFR_MEM8(0x0A8B) -#define AWEXE_OUTOVEN _SFR_MEM8(0x0A8C) - -/* USARTE0 - Universal Asynchronous Receiver-Transmitter E0 */ -#define USARTE0_DATA _SFR_MEM8(0x0AA0) -#define USARTE0_STATUS _SFR_MEM8(0x0AA1) -#define USARTE0_CTRLA _SFR_MEM8(0x0AA3) -#define USARTE0_CTRLB _SFR_MEM8(0x0AA4) -#define USARTE0_CTRLC _SFR_MEM8(0x0AA5) -#define USARTE0_BAUDCTRLA _SFR_MEM8(0x0AA6) -#define USARTE0_BAUDCTRLB _SFR_MEM8(0x0AA7) - -/* SPIE - Serial Peripheral Interface E */ -#define SPIE_CTRL _SFR_MEM8(0x0AC0) -#define SPIE_INTCTRL _SFR_MEM8(0x0AC1) -#define SPIE_STATUS _SFR_MEM8(0x0AC2) -#define SPIE_DATA _SFR_MEM8(0x0AC3) - -/* TCF0 - Timer/Counter F0 */ -#define TCF0_CTRLA _SFR_MEM8(0x0B00) -#define TCF0_CTRLB _SFR_MEM8(0x0B01) -#define TCF0_CTRLC _SFR_MEM8(0x0B02) -#define TCF0_CTRLD _SFR_MEM8(0x0B03) -#define TCF0_CTRLE _SFR_MEM8(0x0B04) -#define TCF0_INTCTRLA _SFR_MEM8(0x0B06) -#define TCF0_INTCTRLB _SFR_MEM8(0x0B07) -#define TCF0_CTRLFCLR _SFR_MEM8(0x0B08) -#define TCF0_CTRLFSET _SFR_MEM8(0x0B09) -#define TCF0_CTRLGCLR _SFR_MEM8(0x0B0A) -#define TCF0_CTRLGSET _SFR_MEM8(0x0B0B) -#define TCF0_INTFLAGS _SFR_MEM8(0x0B0C) -#define TCF0_TEMP _SFR_MEM8(0x0B0F) -#define TCF0_CNT _SFR_MEM16(0x0B20) -#define TCF0_PER _SFR_MEM16(0x0B26) -#define TCF0_CCA _SFR_MEM16(0x0B28) -#define TCF0_CCB _SFR_MEM16(0x0B2A) -#define TCF0_CCC _SFR_MEM16(0x0B2C) -#define TCF0_CCD _SFR_MEM16(0x0B2E) -#define TCF0_PERBUF _SFR_MEM16(0x0B36) -#define TCF0_CCABUF _SFR_MEM16(0x0B38) -#define TCF0_CCBBUF _SFR_MEM16(0x0B3A) -#define TCF0_CCCBUF _SFR_MEM16(0x0B3C) -#define TCF0_CCDBUF _SFR_MEM16(0x0B3E) - - - -/*================== Bitfield Definitions ================== */ - -/* XOCD - On-Chip Debug System */ -/* OCD.OCDR1 bit masks and bit positions */ -#define OCD_OCDRD_bm 0x01 /* OCDR Dirty bit mask. */ -#define OCD_OCDRD_bp 0 /* OCDR Dirty bit position. */ - - -/* CPU - CPU */ -/* CPU.CCP bit masks and bit positions */ -#define CPU_CCP_gm 0xFF /* CCP signature group mask. */ -#define CPU_CCP_gp 0 /* CCP signature group position. */ -#define CPU_CCP0_bm (1<<0) /* CCP signature bit 0 mask. */ -#define CPU_CCP0_bp 0 /* CCP signature bit 0 position. */ -#define CPU_CCP1_bm (1<<1) /* CCP signature bit 1 mask. */ -#define CPU_CCP1_bp 1 /* CCP signature bit 1 position. */ -#define CPU_CCP2_bm (1<<2) /* CCP signature bit 2 mask. */ -#define CPU_CCP2_bp 2 /* CCP signature bit 2 position. */ -#define CPU_CCP3_bm (1<<3) /* CCP signature bit 3 mask. */ -#define CPU_CCP3_bp 3 /* CCP signature bit 3 position. */ -#define CPU_CCP4_bm (1<<4) /* CCP signature bit 4 mask. */ -#define CPU_CCP4_bp 4 /* CCP signature bit 4 position. */ -#define CPU_CCP5_bm (1<<5) /* CCP signature bit 5 mask. */ -#define CPU_CCP5_bp 5 /* CCP signature bit 5 position. */ -#define CPU_CCP6_bm (1<<6) /* CCP signature bit 6 mask. */ -#define CPU_CCP6_bp 6 /* CCP signature bit 6 position. */ -#define CPU_CCP7_bm (1<<7) /* CCP signature bit 7 mask. */ -#define CPU_CCP7_bp 7 /* CCP signature bit 7 position. */ - - -/* CPU.SREG bit masks and bit positions */ -#define CPU_I_bm 0x80 /* Global Interrupt Enable Flag bit mask. */ -#define CPU_I_bp 7 /* Global Interrupt Enable Flag bit position. */ - -#define CPU_T_bm 0x40 /* Transfer Bit bit mask. */ -#define CPU_T_bp 6 /* Transfer Bit bit position. */ - -#define CPU_H_bm 0x20 /* Half Carry Flag bit mask. */ -#define CPU_H_bp 5 /* Half Carry Flag bit position. */ - -#define CPU_S_bm 0x10 /* N Exclusive Or V Flag bit mask. */ -#define CPU_S_bp 4 /* N Exclusive Or V Flag bit position. */ - -#define CPU_V_bm 0x08 /* Two's Complement Overflow Flag bit mask. */ -#define CPU_V_bp 3 /* Two's Complement Overflow Flag bit position. */ - -#define CPU_N_bm 0x04 /* Negative Flag bit mask. */ -#define CPU_N_bp 2 /* Negative Flag bit position. */ - -#define CPU_Z_bm 0x02 /* Zero Flag bit mask. */ -#define CPU_Z_bp 1 /* Zero Flag bit position. */ - -#define CPU_C_bm 0x01 /* Carry Flag bit mask. */ -#define CPU_C_bp 0 /* Carry Flag bit position. */ - - -/* CLK - Clock System */ -/* CLK.CTRL bit masks and bit positions */ -#define CLK_SCLKSEL_gm 0x07 /* System Clock Selection group mask. */ -#define CLK_SCLKSEL_gp 0 /* System Clock Selection group position. */ -#define CLK_SCLKSEL0_bm (1<<0) /* System Clock Selection bit 0 mask. */ -#define CLK_SCLKSEL0_bp 0 /* System Clock Selection bit 0 position. */ -#define CLK_SCLKSEL1_bm (1<<1) /* System Clock Selection bit 1 mask. */ -#define CLK_SCLKSEL1_bp 1 /* System Clock Selection bit 1 position. */ -#define CLK_SCLKSEL2_bm (1<<2) /* System Clock Selection bit 2 mask. */ -#define CLK_SCLKSEL2_bp 2 /* System Clock Selection bit 2 position. */ - - -/* CLK.PSCTRL bit masks and bit positions */ -#define CLK_PSADIV_gm 0x7C /* Prescaler A Division Factor group mask. */ -#define CLK_PSADIV_gp 2 /* Prescaler A Division Factor group position. */ -#define CLK_PSADIV0_bm (1<<2) /* Prescaler A Division Factor bit 0 mask. */ -#define CLK_PSADIV0_bp 2 /* Prescaler A Division Factor bit 0 position. */ -#define CLK_PSADIV1_bm (1<<3) /* Prescaler A Division Factor bit 1 mask. */ -#define CLK_PSADIV1_bp 3 /* Prescaler A Division Factor bit 1 position. */ -#define CLK_PSADIV2_bm (1<<4) /* Prescaler A Division Factor bit 2 mask. */ -#define CLK_PSADIV2_bp 4 /* Prescaler A Division Factor bit 2 position. */ -#define CLK_PSADIV3_bm (1<<5) /* Prescaler A Division Factor bit 3 mask. */ -#define CLK_PSADIV3_bp 5 /* Prescaler A Division Factor bit 3 position. */ -#define CLK_PSADIV4_bm (1<<6) /* Prescaler A Division Factor bit 4 mask. */ -#define CLK_PSADIV4_bp 6 /* Prescaler A Division Factor bit 4 position. */ - -#define CLK_PSBCDIV_gm 0x03 /* Prescaler B and C Division factor group mask. */ -#define CLK_PSBCDIV_gp 0 /* Prescaler B and C Division factor group position. */ -#define CLK_PSBCDIV0_bm (1<<0) /* Prescaler B and C Division factor bit 0 mask. */ -#define CLK_PSBCDIV0_bp 0 /* Prescaler B and C Division factor bit 0 position. */ -#define CLK_PSBCDIV1_bm (1<<1) /* Prescaler B and C Division factor bit 1 mask. */ -#define CLK_PSBCDIV1_bp 1 /* Prescaler B and C Division factor bit 1 position. */ - - -/* CLK.LOCK bit masks and bit positions */ -#define CLK_LOCK_bm 0x01 /* Clock System Lock bit mask. */ -#define CLK_LOCK_bp 0 /* Clock System Lock bit position. */ - - -/* CLK.RTCCTRL bit masks and bit positions */ -#define CLK_RTCSRC_gm 0x0E /* Clock Source group mask. */ -#define CLK_RTCSRC_gp 1 /* Clock Source group position. */ -#define CLK_RTCSRC0_bm (1<<1) /* Clock Source bit 0 mask. */ -#define CLK_RTCSRC0_bp 1 /* Clock Source bit 0 position. */ -#define CLK_RTCSRC1_bm (1<<2) /* Clock Source bit 1 mask. */ -#define CLK_RTCSRC1_bp 2 /* Clock Source bit 1 position. */ -#define CLK_RTCSRC2_bm (1<<3) /* Clock Source bit 2 mask. */ -#define CLK_RTCSRC2_bp 3 /* Clock Source bit 2 position. */ - -#define CLK_RTCEN_bm 0x01 /* RTC Clock Source Enable bit mask. */ -#define CLK_RTCEN_bp 0 /* RTC Clock Source Enable bit position. */ - - -/* PR.PRGEN bit masks and bit positions */ -#define PR_RTC_bm 0x04 /* Real-time Counter bit mask. */ -#define PR_RTC_bp 2 /* Real-time Counter bit position. */ - -#define PR_EVSYS_bm 0x02 /* Event System bit mask. */ -#define PR_EVSYS_bp 1 /* Event System bit position. */ - -/* PR.PRPA bit masks and bit positions */ -#define PR_ADC_bm 0x02 /* Port A ADC bit mask. */ -#define PR_ADC_bp 1 /* Port A ADC bit position. */ - -#define PR_AC_bm 0x01 /* Port A Analog Comparator bit mask. */ -#define PR_AC_bp 0 /* Port A Analog Comparator bit position. */ - -/* PR.PRPC bit masks and bit positions */ -#define PR_TWI_bm 0x40 /* Port C Two-wire Interface bit mask. */ -#define PR_TWI_bp 6 /* Port C Two-wire Interface bit position. */ - -#define PR_USART0_bm 0x10 /* Port C USART0 bit mask. */ -#define PR_USART0_bp 4 /* Port C USART0 bit position. */ - -#define PR_SPI_bm 0x08 /* Port C SPI bit mask. */ -#define PR_SPI_bp 3 /* Port C SPI bit position. */ - -#define PR_HIRES_bm 0x04 /* Port C HIRES bit mask. */ -#define PR_HIRES_bp 2 /* Port C HIRES bit position. */ - -#define PR_TC1_bm 0x02 /* Port C Timer/Counter1 bit mask. */ -#define PR_TC1_bp 1 /* Port C Timer/Counter1 bit position. */ - -#define PR_TC0_bm 0x01 /* Port C Timer/Counter0 bit mask. */ -#define PR_TC0_bp 0 /* Port C Timer/Counter0 bit position. */ - -/* PR.PRPD bit masks and bit positions */ -/* PR_USART0_bm Predefined. */ -/* PR_USART0_bp Predefined. */ - -/* PR_SPI_bm Predefined. */ -/* PR_SPI_bp Predefined. */ - -/* PR_TC0_bm Predefined. */ -/* PR_TC0_bp Predefined. */ - -/* PR.PRPE bit masks and bit positions */ -/* PR_TWI_bm Predefined. */ -/* PR_TWI_bp Predefined. */ - -/* PR_USART0_bm Predefined. */ -/* PR_USART0_bp Predefined. */ - -/* PR_TC0_bm Predefined. */ -/* PR_TC0_bp Predefined. */ - -/* PR.PRPF bit masks and bit positions */ -/* PR_USART0_bm Predefined. */ -/* PR_USART0_bp Predefined. */ - -/* PR_TC0_bm Predefined. */ -/* PR_TC0_bp Predefined. */ - -/* SLEEP - Sleep Controller */ -/* SLEEP.CTRL bit masks and bit positions */ -#define SLEEP_SMODE_gm 0x0E /* Sleep Mode group mask. */ -#define SLEEP_SMODE_gp 1 /* Sleep Mode group position. */ -#define SLEEP_SMODE0_bm (1<<1) /* Sleep Mode bit 0 mask. */ -#define SLEEP_SMODE0_bp 1 /* Sleep Mode bit 0 position. */ -#define SLEEP_SMODE1_bm (1<<2) /* Sleep Mode bit 1 mask. */ -#define SLEEP_SMODE1_bp 2 /* Sleep Mode bit 1 position. */ -#define SLEEP_SMODE2_bm (1<<3) /* Sleep Mode bit 2 mask. */ -#define SLEEP_SMODE2_bp 3 /* Sleep Mode bit 2 position. */ - -#define SLEEP_SEN_bm 0x01 /* Sleep Enable bit mask. */ -#define SLEEP_SEN_bp 0 /* Sleep Enable bit position. */ - - -/* OSC - Oscillator */ -/* OSC.CTRL bit masks and bit positions */ -#define OSC_PLLEN_bm 0x10 /* PLL Enable bit mask. */ -#define OSC_PLLEN_bp 4 /* PLL Enable bit position. */ - -#define OSC_XOSCEN_bm 0x08 /* External Oscillator Enable bit mask. */ -#define OSC_XOSCEN_bp 3 /* External Oscillator Enable bit position. */ - -#define OSC_RC32KEN_bm 0x04 /* Internal 32kHz RC Oscillator Enable bit mask. */ -#define OSC_RC32KEN_bp 2 /* Internal 32kHz RC Oscillator Enable bit position. */ - -#define OSC_RC32MEN_bm 0x02 /* Internal 32MHz RC Oscillator Enable bit mask. */ -#define OSC_RC32MEN_bp 1 /* Internal 32MHz RC Oscillator Enable bit position. */ - -#define OSC_RC2MEN_bm 0x01 /* Internal 2MHz RC Oscillator Enable bit mask. */ -#define OSC_RC2MEN_bp 0 /* Internal 2MHz RC Oscillator Enable bit position. */ - - -/* OSC.STATUS bit masks and bit positions */ -#define OSC_PLLRDY_bm 0x10 /* PLL Ready bit mask. */ -#define OSC_PLLRDY_bp 4 /* PLL Ready bit position. */ - -#define OSC_XOSCRDY_bm 0x08 /* External Oscillator Ready bit mask. */ -#define OSC_XOSCRDY_bp 3 /* External Oscillator Ready bit position. */ - -#define OSC_RC32KRDY_bm 0x04 /* Internal 32kHz RC Oscillator Ready bit mask. */ -#define OSC_RC32KRDY_bp 2 /* Internal 32kHz RC Oscillator Ready bit position. */ - -#define OSC_RC32MRDY_bm 0x02 /* Internal 32MHz RC Oscillator Ready bit mask. */ -#define OSC_RC32MRDY_bp 1 /* Internal 32MHz RC Oscillator Ready bit position. */ - -#define OSC_RC2MRDY_bm 0x01 /* Internal 2MHz RC Oscillator Ready bit mask. */ -#define OSC_RC2MRDY_bp 0 /* Internal 2MHz RC Oscillator Ready bit position. */ - - -/* OSC.XOSCCTRL bit masks and bit positions */ -#define OSC_FRQRANGE_gm 0xC0 /* Frequency Range group mask. */ -#define OSC_FRQRANGE_gp 6 /* Frequency Range group position. */ -#define OSC_FRQRANGE0_bm (1<<6) /* Frequency Range bit 0 mask. */ -#define OSC_FRQRANGE0_bp 6 /* Frequency Range bit 0 position. */ -#define OSC_FRQRANGE1_bm (1<<7) /* Frequency Range bit 1 mask. */ -#define OSC_FRQRANGE1_bp 7 /* Frequency Range bit 1 position. */ - -#define OSC_X32KLPM_bm 0x20 /* 32kHz XTAL OSC Low-power Mode bit mask. */ -#define OSC_X32KLPM_bp 5 /* 32kHz XTAL OSC Low-power Mode bit position. */ - -#define OSC_XOSCSEL_gm 0x0F /* External Oscillator Selection and Startup Time group mask. */ -#define OSC_XOSCSEL_gp 0 /* External Oscillator Selection and Startup Time group position. */ -#define OSC_XOSCSEL0_bm (1<<0) /* External Oscillator Selection and Startup Time bit 0 mask. */ -#define OSC_XOSCSEL0_bp 0 /* External Oscillator Selection and Startup Time bit 0 position. */ -#define OSC_XOSCSEL1_bm (1<<1) /* External Oscillator Selection and Startup Time bit 1 mask. */ -#define OSC_XOSCSEL1_bp 1 /* External Oscillator Selection and Startup Time bit 1 position. */ -#define OSC_XOSCSEL2_bm (1<<2) /* External Oscillator Selection and Startup Time bit 2 mask. */ -#define OSC_XOSCSEL2_bp 2 /* External Oscillator Selection and Startup Time bit 2 position. */ -#define OSC_XOSCSEL3_bm (1<<3) /* External Oscillator Selection and Startup Time bit 3 mask. */ -#define OSC_XOSCSEL3_bp 3 /* External Oscillator Selection and Startup Time bit 3 position. */ - - -/* OSC.XOSCFAIL bit masks and bit positions */ -#define OSC_XOSCFDIF_bm 0x02 /* Failure Detection Interrupt Flag bit mask. */ -#define OSC_XOSCFDIF_bp 1 /* Failure Detection Interrupt Flag bit position. */ - -#define OSC_XOSCFDEN_bm 0x01 /* Failure Detection Enable bit mask. */ -#define OSC_XOSCFDEN_bp 0 /* Failure Detection Enable bit position. */ - - -/* OSC.PLLCTRL bit masks and bit positions */ -#define OSC_PLLSRC_gm 0xC0 /* Clock Source group mask. */ -#define OSC_PLLSRC_gp 6 /* Clock Source group position. */ -#define OSC_PLLSRC0_bm (1<<6) /* Clock Source bit 0 mask. */ -#define OSC_PLLSRC0_bp 6 /* Clock Source bit 0 position. */ -#define OSC_PLLSRC1_bm (1<<7) /* Clock Source bit 1 mask. */ -#define OSC_PLLSRC1_bp 7 /* Clock Source bit 1 position. */ - -#define OSC_PLLFAC_gm 0x1F /* Multiplication Factor group mask. */ -#define OSC_PLLFAC_gp 0 /* Multiplication Factor group position. */ -#define OSC_PLLFAC0_bm (1<<0) /* Multiplication Factor bit 0 mask. */ -#define OSC_PLLFAC0_bp 0 /* Multiplication Factor bit 0 position. */ -#define OSC_PLLFAC1_bm (1<<1) /* Multiplication Factor bit 1 mask. */ -#define OSC_PLLFAC1_bp 1 /* Multiplication Factor bit 1 position. */ -#define OSC_PLLFAC2_bm (1<<2) /* Multiplication Factor bit 2 mask. */ -#define OSC_PLLFAC2_bp 2 /* Multiplication Factor bit 2 position. */ -#define OSC_PLLFAC3_bm (1<<3) /* Multiplication Factor bit 3 mask. */ -#define OSC_PLLFAC3_bp 3 /* Multiplication Factor bit 3 position. */ -#define OSC_PLLFAC4_bm (1<<4) /* Multiplication Factor bit 4 mask. */ -#define OSC_PLLFAC4_bp 4 /* Multiplication Factor bit 4 position. */ - - -/* OSC.DFLLCTRL bit masks and bit positions */ -#define OSC_RC32MCREF_bm 0x02 /* 32MHz Calibration Reference bit mask. */ -#define OSC_RC32MCREF_bp 1 /* 32MHz Calibration Reference bit position. */ - -#define OSC_RC2MCREF_bm 0x01 /* 2MHz Calibration Reference bit mask. */ -#define OSC_RC2MCREF_bp 0 /* 2MHz Calibration Reference bit position. */ - - -/* DFLL - DFLL */ -/* DFLL.CTRL bit masks and bit positions */ -#define DFLL_ENABLE_bm 0x01 /* DFLL Enable bit mask. */ -#define DFLL_ENABLE_bp 0 /* DFLL Enable bit position. */ - - -/* DFLL.CALA bit masks and bit positions */ -#define DFLL_CALL_gm 0x7F /* DFLL Calibration bits [6:0] group mask. */ -#define DFLL_CALL_gp 0 /* DFLL Calibration bits [6:0] group position. */ -#define DFLL_CALL0_bm (1<<0) /* DFLL Calibration bits [6:0] bit 0 mask. */ -#define DFLL_CALL0_bp 0 /* DFLL Calibration bits [6:0] bit 0 position. */ -#define DFLL_CALL1_bm (1<<1) /* DFLL Calibration bits [6:0] bit 1 mask. */ -#define DFLL_CALL1_bp 1 /* DFLL Calibration bits [6:0] bit 1 position. */ -#define DFLL_CALL2_bm (1<<2) /* DFLL Calibration bits [6:0] bit 2 mask. */ -#define DFLL_CALL2_bp 2 /* DFLL Calibration bits [6:0] bit 2 position. */ -#define DFLL_CALL3_bm (1<<3) /* DFLL Calibration bits [6:0] bit 3 mask. */ -#define DFLL_CALL3_bp 3 /* DFLL Calibration bits [6:0] bit 3 position. */ -#define DFLL_CALL4_bm (1<<4) /* DFLL Calibration bits [6:0] bit 4 mask. */ -#define DFLL_CALL4_bp 4 /* DFLL Calibration bits [6:0] bit 4 position. */ -#define DFLL_CALL5_bm (1<<5) /* DFLL Calibration bits [6:0] bit 5 mask. */ -#define DFLL_CALL5_bp 5 /* DFLL Calibration bits [6:0] bit 5 position. */ -#define DFLL_CALL6_bm (1<<6) /* DFLL Calibration bits [6:0] bit 6 mask. */ -#define DFLL_CALL6_bp 6 /* DFLL Calibration bits [6:0] bit 6 position. */ - - -/* DFLL.CALB bit masks and bit positions */ -#define DFLL_CALH_gm 0x3F /* DFLL Calibration bits [12:7] group mask. */ -#define DFLL_CALH_gp 0 /* DFLL Calibration bits [12:7] group position. */ -#define DFLL_CALH0_bm (1<<0) /* DFLL Calibration bits [12:7] bit 0 mask. */ -#define DFLL_CALH0_bp 0 /* DFLL Calibration bits [12:7] bit 0 position. */ -#define DFLL_CALH1_bm (1<<1) /* DFLL Calibration bits [12:7] bit 1 mask. */ -#define DFLL_CALH1_bp 1 /* DFLL Calibration bits [12:7] bit 1 position. */ -#define DFLL_CALH2_bm (1<<2) /* DFLL Calibration bits [12:7] bit 2 mask. */ -#define DFLL_CALH2_bp 2 /* DFLL Calibration bits [12:7] bit 2 position. */ -#define DFLL_CALH3_bm (1<<3) /* DFLL Calibration bits [12:7] bit 3 mask. */ -#define DFLL_CALH3_bp 3 /* DFLL Calibration bits [12:7] bit 3 position. */ -#define DFLL_CALH4_bm (1<<4) /* DFLL Calibration bits [12:7] bit 4 mask. */ -#define DFLL_CALH4_bp 4 /* DFLL Calibration bits [12:7] bit 4 position. */ -#define DFLL_CALH5_bm (1<<5) /* DFLL Calibration bits [12:7] bit 5 mask. */ -#define DFLL_CALH5_bp 5 /* DFLL Calibration bits [12:7] bit 5 position. */ - - -/* RST - Reset */ -/* RST.STATUS bit masks and bit positions */ -#define RST_SDRF_bm 0x40 /* Spike Detection Reset Flag bit mask. */ -#define RST_SDRF_bp 6 /* Spike Detection Reset Flag bit position. */ - -#define RST_SRF_bm 0x20 /* Software Reset Flag bit mask. */ -#define RST_SRF_bp 5 /* Software Reset Flag bit position. */ - -#define RST_PDIRF_bm 0x10 /* Programming and Debug Interface Interface Reset Flag bit mask. */ -#define RST_PDIRF_bp 4 /* Programming and Debug Interface Interface Reset Flag bit position. */ - -#define RST_WDRF_bm 0x08 /* Watchdog Reset Flag bit mask. */ -#define RST_WDRF_bp 3 /* Watchdog Reset Flag bit position. */ - -#define RST_BORF_bm 0x04 /* Brown-out Reset Flag bit mask. */ -#define RST_BORF_bp 2 /* Brown-out Reset Flag bit position. */ - -#define RST_EXTRF_bm 0x02 /* External Reset Flag bit mask. */ -#define RST_EXTRF_bp 1 /* External Reset Flag bit position. */ - -#define RST_PORF_bm 0x01 /* Power-on Reset Flag bit mask. */ -#define RST_PORF_bp 0 /* Power-on Reset Flag bit position. */ - - -/* RST.CTRL bit masks and bit positions */ -#define RST_SWRST_bm 0x01 /* Software Reset bit mask. */ -#define RST_SWRST_bp 0 /* Software Reset bit position. */ - - -/* WDT - Watch-Dog Timer */ -/* WDT.CTRL bit masks and bit positions */ -#define WDT_PER_gm 0x3C /* Period group mask. */ -#define WDT_PER_gp 2 /* Period group position. */ -#define WDT_PER0_bm (1<<2) /* Period bit 0 mask. */ -#define WDT_PER0_bp 2 /* Period bit 0 position. */ -#define WDT_PER1_bm (1<<3) /* Period bit 1 mask. */ -#define WDT_PER1_bp 3 /* Period bit 1 position. */ -#define WDT_PER2_bm (1<<4) /* Period bit 2 mask. */ -#define WDT_PER2_bp 4 /* Period bit 2 position. */ -#define WDT_PER3_bm (1<<5) /* Period bit 3 mask. */ -#define WDT_PER3_bp 5 /* Period bit 3 position. */ - -#define WDT_ENABLE_bm 0x02 /* Enable bit mask. */ -#define WDT_ENABLE_bp 1 /* Enable bit position. */ - -#define WDT_CEN_bm 0x01 /* Change Enable bit mask. */ -#define WDT_CEN_bp 0 /* Change Enable bit position. */ - - -/* WDT.WINCTRL bit masks and bit positions */ -#define WDT_WPER_gm 0x3C /* Windowed Mode Period group mask. */ -#define WDT_WPER_gp 2 /* Windowed Mode Period group position. */ -#define WDT_WPER0_bm (1<<2) /* Windowed Mode Period bit 0 mask. */ -#define WDT_WPER0_bp 2 /* Windowed Mode Period bit 0 position. */ -#define WDT_WPER1_bm (1<<3) /* Windowed Mode Period bit 1 mask. */ -#define WDT_WPER1_bp 3 /* Windowed Mode Period bit 1 position. */ -#define WDT_WPER2_bm (1<<4) /* Windowed Mode Period bit 2 mask. */ -#define WDT_WPER2_bp 4 /* Windowed Mode Period bit 2 position. */ -#define WDT_WPER3_bm (1<<5) /* Windowed Mode Period bit 3 mask. */ -#define WDT_WPER3_bp 5 /* Windowed Mode Period bit 3 position. */ - -#define WDT_WEN_bm 0x02 /* Windowed Mode Enable bit mask. */ -#define WDT_WEN_bp 1 /* Windowed Mode Enable bit position. */ - -#define WDT_WCEN_bm 0x01 /* Windowed Mode Change Enable bit mask. */ -#define WDT_WCEN_bp 0 /* Windowed Mode Change Enable bit position. */ - - -/* WDT.STATUS bit masks and bit positions */ -#define WDT_SYNCBUSY_bm 0x01 /* Syncronization busy bit mask. */ -#define WDT_SYNCBUSY_bp 0 /* Syncronization busy bit position. */ - - -/* MCU - MCU Control */ -/* MCU.MCUCR bit masks and bit positions */ -#define MCU_JTAGD_bm 0x01 /* JTAG Disable bit mask. */ -#define MCU_JTAGD_bp 0 /* JTAG Disable bit position. */ - - -/* MCU.EVSYSLOCK bit masks and bit positions */ -#define MCU_EVSYS1LOCK_bm 0x10 /* Event Channel 4-7 Lock bit mask. */ -#define MCU_EVSYS1LOCK_bp 4 /* Event Channel 4-7 Lock bit position. */ - -#define MCU_EVSYS0LOCK_bm 0x01 /* Event Channel 0-3 Lock bit mask. */ -#define MCU_EVSYS0LOCK_bp 0 /* Event Channel 0-3 Lock bit position. */ - - -/* MCU.AWEXLOCK bit masks and bit positions */ -#define MCU_AWEXELOCK_bm 0x04 /* AWeX on T/C E0 Lock bit mask. */ -#define MCU_AWEXELOCK_bp 2 /* AWeX on T/C E0 Lock bit position. */ - -#define MCU_AWEXCLOCK_bm 0x01 /* AWeX on T/C C0 Lock bit mask. */ -#define MCU_AWEXCLOCK_bp 0 /* AWeX on T/C C0 Lock bit position. */ - - -/* PMIC - Programmable Multi-level Interrupt Controller */ -/* PMIC.STATUS bit masks and bit positions */ -#define PMIC_NMIEX_bm 0x80 /* Non-maskable Interrupt Executing bit mask. */ -#define PMIC_NMIEX_bp 7 /* Non-maskable Interrupt Executing bit position. */ - -#define PMIC_HILVLEX_bm 0x04 /* High Level Interrupt Executing bit mask. */ -#define PMIC_HILVLEX_bp 2 /* High Level Interrupt Executing bit position. */ - -#define PMIC_MEDLVLEX_bm 0x02 /* Medium Level Interrupt Executing bit mask. */ -#define PMIC_MEDLVLEX_bp 1 /* Medium Level Interrupt Executing bit position. */ - -#define PMIC_LOLVLEX_bm 0x01 /* Low Level Interrupt Executing bit mask. */ -#define PMIC_LOLVLEX_bp 0 /* Low Level Interrupt Executing bit position. */ - - -/* PMIC.CTRL bit masks and bit positions */ -#define PMIC_RREN_bm 0x80 /* Round-Robin Priority Enable bit mask. */ -#define PMIC_RREN_bp 7 /* Round-Robin Priority Enable bit position. */ - -#define PMIC_IVSEL_bm 0x40 /* Interrupt Vector Select bit mask. */ -#define PMIC_IVSEL_bp 6 /* Interrupt Vector Select bit position. */ - -#define PMIC_HILVLEN_bm 0x04 /* High Level Enable bit mask. */ -#define PMIC_HILVLEN_bp 2 /* High Level Enable bit position. */ - -#define PMIC_MEDLVLEN_bm 0x02 /* Medium Level Enable bit mask. */ -#define PMIC_MEDLVLEN_bp 1 /* Medium Level Enable bit position. */ - -#define PMIC_LOLVLEN_bm 0x01 /* Low Level Enable bit mask. */ -#define PMIC_LOLVLEN_bp 0 /* Low Level Enable bit position. */ - - -/* CRC - Cyclic Redundancy Checker */ -/* CRC.CTRL bit masks and bit positions */ -#define CRC_RESET_gm 0xC0 /* Reset group mask. */ -#define CRC_RESET_gp 6 /* Reset group position. */ -#define CRC_RESET0_bm (1<<6) /* Reset bit 0 mask. */ -#define CRC_RESET0_bp 6 /* Reset bit 0 position. */ -#define CRC_RESET1_bm (1<<7) /* Reset bit 1 mask. */ -#define CRC_RESET1_bp 7 /* Reset bit 1 position. */ - -#define CRC_CRC32_bm 0x20 /* CRC Mode bit mask. */ -#define CRC_CRC32_bp 5 /* CRC Mode bit position. */ - -#define CRC_SOURCE_gm 0x0F /* Input Source group mask. */ -#define CRC_SOURCE_gp 0 /* Input Source group position. */ -#define CRC_SOURCE0_bm (1<<0) /* Input Source bit 0 mask. */ -#define CRC_SOURCE0_bp 0 /* Input Source bit 0 position. */ -#define CRC_SOURCE1_bm (1<<1) /* Input Source bit 1 mask. */ -#define CRC_SOURCE1_bp 1 /* Input Source bit 1 position. */ -#define CRC_SOURCE2_bm (1<<2) /* Input Source bit 2 mask. */ -#define CRC_SOURCE2_bp 2 /* Input Source bit 2 position. */ -#define CRC_SOURCE3_bm (1<<3) /* Input Source bit 3 mask. */ -#define CRC_SOURCE3_bp 3 /* Input Source bit 3 position. */ - -/* CRC.STATUS bit masks and bit positions */ -#define CRC_ZERO_bm 0x02 /* Zero detection bit mask. */ -#define CRC_ZERO_bp 1 /* Zero detection bit position. */ - -#define CRC_BUSY_bm 0x01 /* Busy bit mask. */ -#define CRC_BUSY_bp 0 /* Busy bit position. */ - - -/* EVSYS - Event System */ -/* EVSYS.CH0MUX bit masks and bit positions */ -#define EVSYS_CHMUX_gm 0xFF /* Event Channel 0 Multiplexer group mask. */ -#define EVSYS_CHMUX_gp 0 /* Event Channel 0 Multiplexer group position. */ -#define EVSYS_CHMUX0_bm (1<<0) /* Event Channel 0 Multiplexer bit 0 mask. */ -#define EVSYS_CHMUX0_bp 0 /* Event Channel 0 Multiplexer bit 0 position. */ -#define EVSYS_CHMUX1_bm (1<<1) /* Event Channel 0 Multiplexer bit 1 mask. */ -#define EVSYS_CHMUX1_bp 1 /* Event Channel 0 Multiplexer bit 1 position. */ -#define EVSYS_CHMUX2_bm (1<<2) /* Event Channel 0 Multiplexer bit 2 mask. */ -#define EVSYS_CHMUX2_bp 2 /* Event Channel 0 Multiplexer bit 2 position. */ -#define EVSYS_CHMUX3_bm (1<<3) /* Event Channel 0 Multiplexer bit 3 mask. */ -#define EVSYS_CHMUX3_bp 3 /* Event Channel 0 Multiplexer bit 3 position. */ -#define EVSYS_CHMUX4_bm (1<<4) /* Event Channel 0 Multiplexer bit 4 mask. */ -#define EVSYS_CHMUX4_bp 4 /* Event Channel 0 Multiplexer bit 4 position. */ -#define EVSYS_CHMUX5_bm (1<<5) /* Event Channel 0 Multiplexer bit 5 mask. */ -#define EVSYS_CHMUX5_bp 5 /* Event Channel 0 Multiplexer bit 5 position. */ -#define EVSYS_CHMUX6_bm (1<<6) /* Event Channel 0 Multiplexer bit 6 mask. */ -#define EVSYS_CHMUX6_bp 6 /* Event Channel 0 Multiplexer bit 6 position. */ -#define EVSYS_CHMUX7_bm (1<<7) /* Event Channel 0 Multiplexer bit 7 mask. */ -#define EVSYS_CHMUX7_bp 7 /* Event Channel 0 Multiplexer bit 7 position. */ - - -/* EVSYS.CH1MUX bit masks and bit positions */ -/* EVSYS_CHMUX_gm Predefined. */ -/* EVSYS_CHMUX_gp Predefined. */ -/* EVSYS_CHMUX0_bm Predefined. */ -/* EVSYS_CHMUX0_bp Predefined. */ -/* EVSYS_CHMUX1_bm Predefined. */ -/* EVSYS_CHMUX1_bp Predefined. */ -/* EVSYS_CHMUX2_bm Predefined. */ -/* EVSYS_CHMUX2_bp Predefined. */ -/* EVSYS_CHMUX3_bm Predefined. */ -/* EVSYS_CHMUX3_bp Predefined. */ -/* EVSYS_CHMUX4_bm Predefined. */ -/* EVSYS_CHMUX4_bp Predefined. */ -/* EVSYS_CHMUX5_bm Predefined. */ -/* EVSYS_CHMUX5_bp Predefined. */ -/* EVSYS_CHMUX6_bm Predefined. */ -/* EVSYS_CHMUX6_bp Predefined. */ -/* EVSYS_CHMUX7_bm Predefined. */ -/* EVSYS_CHMUX7_bp Predefined. */ - - -/* EVSYS.CH2MUX bit masks and bit positions */ -/* EVSYS_CHMUX_gm Predefined. */ -/* EVSYS_CHMUX_gp Predefined. */ -/* EVSYS_CHMUX0_bm Predefined. */ -/* EVSYS_CHMUX0_bp Predefined. */ -/* EVSYS_CHMUX1_bm Predefined. */ -/* EVSYS_CHMUX1_bp Predefined. */ -/* EVSYS_CHMUX2_bm Predefined. */ -/* EVSYS_CHMUX2_bp Predefined. */ -/* EVSYS_CHMUX3_bm Predefined. */ -/* EVSYS_CHMUX3_bp Predefined. */ -/* EVSYS_CHMUX4_bm Predefined. */ -/* EVSYS_CHMUX4_bp Predefined. */ -/* EVSYS_CHMUX5_bm Predefined. */ -/* EVSYS_CHMUX5_bp Predefined. */ -/* EVSYS_CHMUX6_bm Predefined. */ -/* EVSYS_CHMUX6_bp Predefined. */ -/* EVSYS_CHMUX7_bm Predefined. */ -/* EVSYS_CHMUX7_bp Predefined. */ - - -/* EVSYS.CH3MUX bit masks and bit positions */ -/* EVSYS_CHMUX_gm Predefined. */ -/* EVSYS_CHMUX_gp Predefined. */ -/* EVSYS_CHMUX0_bm Predefined. */ -/* EVSYS_CHMUX0_bp Predefined. */ -/* EVSYS_CHMUX1_bm Predefined. */ -/* EVSYS_CHMUX1_bp Predefined. */ -/* EVSYS_CHMUX2_bm Predefined. */ -/* EVSYS_CHMUX2_bp Predefined. */ -/* EVSYS_CHMUX3_bm Predefined. */ -/* EVSYS_CHMUX3_bp Predefined. */ -/* EVSYS_CHMUX4_bm Predefined. */ -/* EVSYS_CHMUX4_bp Predefined. */ -/* EVSYS_CHMUX5_bm Predefined. */ -/* EVSYS_CHMUX5_bp Predefined. */ -/* EVSYS_CHMUX6_bm Predefined. */ -/* EVSYS_CHMUX6_bp Predefined. */ -/* EVSYS_CHMUX7_bm Predefined. */ -/* EVSYS_CHMUX7_bp Predefined. */ - - -/* EVSYS.CH0CTRL bit masks and bit positions */ -#define EVSYS_QDIRM_gm 0x60 /* Quadrature Decoder Index Recognition Mode group mask. */ -#define EVSYS_QDIRM_gp 5 /* Quadrature Decoder Index Recognition Mode group position. */ -#define EVSYS_QDIRM0_bm (1<<5) /* Quadrature Decoder Index Recognition Mode bit 0 mask. */ -#define EVSYS_QDIRM0_bp 5 /* Quadrature Decoder Index Recognition Mode bit 0 position. */ -#define EVSYS_QDIRM1_bm (1<<6) /* Quadrature Decoder Index Recognition Mode bit 1 mask. */ -#define EVSYS_QDIRM1_bp 6 /* Quadrature Decoder Index Recognition Mode bit 1 position. */ - -#define EVSYS_QDIEN_bm 0x10 /* Quadrature Decoder Index Enable bit mask. */ -#define EVSYS_QDIEN_bp 4 /* Quadrature Decoder Index Enable bit position. */ - -#define EVSYS_QDEN_bm 0x08 /* Quadrature Decoder Enable bit mask. */ -#define EVSYS_QDEN_bp 3 /* Quadrature Decoder Enable bit position. */ - -#define EVSYS_DIGFILT_gm 0x07 /* Digital Filter group mask. */ -#define EVSYS_DIGFILT_gp 0 /* Digital Filter group position. */ -#define EVSYS_DIGFILT0_bm (1<<0) /* Digital Filter bit 0 mask. */ -#define EVSYS_DIGFILT0_bp 0 /* Digital Filter bit 0 position. */ -#define EVSYS_DIGFILT1_bm (1<<1) /* Digital Filter bit 1 mask. */ -#define EVSYS_DIGFILT1_bp 1 /* Digital Filter bit 1 position. */ -#define EVSYS_DIGFILT2_bm (1<<2) /* Digital Filter bit 2 mask. */ -#define EVSYS_DIGFILT2_bp 2 /* Digital Filter bit 2 position. */ - - -/* EVSYS.CH1CTRL bit masks and bit positions */ -/* EVSYS_DIGFILT_gm Predefined. */ -/* EVSYS_DIGFILT_gp Predefined. */ -/* EVSYS_DIGFILT0_bm Predefined. */ -/* EVSYS_DIGFILT0_bp Predefined. */ -/* EVSYS_DIGFILT1_bm Predefined. */ -/* EVSYS_DIGFILT1_bp Predefined. */ -/* EVSYS_DIGFILT2_bm Predefined. */ -/* EVSYS_DIGFILT2_bp Predefined. */ - - -/* EVSYS.CH2CTRL bit masks and bit positions */ -/* EVSYS_QDIRM_gm Predefined. */ -/* EVSYS_QDIRM_gp Predefined. */ -/* EVSYS_QDIRM0_bm Predefined. */ -/* EVSYS_QDIRM0_bp Predefined. */ -/* EVSYS_QDIRM1_bm Predefined. */ -/* EVSYS_QDIRM1_bp Predefined. */ - -/* EVSYS_QDIEN_bm Predefined. */ -/* EVSYS_QDIEN_bp Predefined. */ - -/* EVSYS_QDEN_bm Predefined. */ -/* EVSYS_QDEN_bp Predefined. */ - -/* EVSYS_DIGFILT_gm Predefined. */ -/* EVSYS_DIGFILT_gp Predefined. */ -/* EVSYS_DIGFILT0_bm Predefined. */ -/* EVSYS_DIGFILT0_bp Predefined. */ -/* EVSYS_DIGFILT1_bm Predefined. */ -/* EVSYS_DIGFILT1_bp Predefined. */ -/* EVSYS_DIGFILT2_bm Predefined. */ -/* EVSYS_DIGFILT2_bp Predefined. */ - - -/* EVSYS.CH3CTRL bit masks and bit positions */ -/* EVSYS_DIGFILT_gm Predefined. */ -/* EVSYS_DIGFILT_gp Predefined. */ -/* EVSYS_DIGFILT0_bm Predefined. */ -/* EVSYS_DIGFILT0_bp Predefined. */ -/* EVSYS_DIGFILT1_bm Predefined. */ -/* EVSYS_DIGFILT1_bp Predefined. */ -/* EVSYS_DIGFILT2_bm Predefined. */ -/* EVSYS_DIGFILT2_bp Predefined. */ - - -/* NVM - Non Volatile Memory Controller */ -/* NVM.CMD bit masks and bit positions */ -#define NVM_CMD_gm 0xFF /* Command group mask. */ -#define NVM_CMD_gp 0 /* Command group position. */ -#define NVM_CMD0_bm (1<<0) /* Command bit 0 mask. */ -#define NVM_CMD0_bp 0 /* Command bit 0 position. */ -#define NVM_CMD1_bm (1<<1) /* Command bit 1 mask. */ -#define NVM_CMD1_bp 1 /* Command bit 1 position. */ -#define NVM_CMD2_bm (1<<2) /* Command bit 2 mask. */ -#define NVM_CMD2_bp 2 /* Command bit 2 position. */ -#define NVM_CMD3_bm (1<<3) /* Command bit 3 mask. */ -#define NVM_CMD3_bp 3 /* Command bit 3 position. */ -#define NVM_CMD4_bm (1<<4) /* Command bit 4 mask. */ -#define NVM_CMD4_bp 4 /* Command bit 4 position. */ -#define NVM_CMD5_bm (1<<5) /* Command bit 5 mask. */ -#define NVM_CMD5_bp 5 /* Command bit 5 position. */ -#define NVM_CMD6_bm (1<<6) /* Command bit 6 mask. */ -#define NVM_CMD6_bp 6 /* Command bit 6 position. */ -#define NVM_CMD7_bm (1<<7) /* Command bit 7 mask. */ -#define NVM_CMD7_bp 7 /* Command bit 7 position. */ - - -/* NVM.CTRLA bit masks and bit positions */ -#define NVM_CMDEX_bm 0x01 /* Command Execute bit mask. */ -#define NVM_CMDEX_bp 0 /* Command Execute bit position. */ - - -/* NVM.CTRLB bit masks and bit positions */ -#define NVM_EEMAPEN_bm 0x08 /* EEPROM Mapping Enable bit mask. */ -#define NVM_EEMAPEN_bp 3 /* EEPROM Mapping Enable bit position. */ - -#define NVM_FPRM_bm 0x04 /* Flash Power Reduction Enable bit mask. */ -#define NVM_FPRM_bp 2 /* Flash Power Reduction Enable bit position. */ - -#define NVM_EPRM_bm 0x02 /* EEPROM Power Reduction Enable bit mask. */ -#define NVM_EPRM_bp 1 /* EEPROM Power Reduction Enable bit position. */ - -#define NVM_SPMLOCK_bm 0x01 /* SPM Lock bit mask. */ -#define NVM_SPMLOCK_bp 0 /* SPM Lock bit position. */ - - -/* NVM.INTCTRL bit masks and bit positions */ -#define NVM_SPMLVL_gm 0x0C /* SPM Interrupt Level group mask. */ -#define NVM_SPMLVL_gp 2 /* SPM Interrupt Level group position. */ -#define NVM_SPMLVL0_bm (1<<2) /* SPM Interrupt Level bit 0 mask. */ -#define NVM_SPMLVL0_bp 2 /* SPM Interrupt Level bit 0 position. */ -#define NVM_SPMLVL1_bm (1<<3) /* SPM Interrupt Level bit 1 mask. */ -#define NVM_SPMLVL1_bp 3 /* SPM Interrupt Level bit 1 position. */ - -#define NVM_EELVL_gm 0x03 /* EEPROM Interrupt Level group mask. */ -#define NVM_EELVL_gp 0 /* EEPROM Interrupt Level group position. */ -#define NVM_EELVL0_bm (1<<0) /* EEPROM Interrupt Level bit 0 mask. */ -#define NVM_EELVL0_bp 0 /* EEPROM Interrupt Level bit 0 position. */ -#define NVM_EELVL1_bm (1<<1) /* EEPROM Interrupt Level bit 1 mask. */ -#define NVM_EELVL1_bp 1 /* EEPROM Interrupt Level bit 1 position. */ - - -/* NVM.STATUS bit masks and bit positions */ -#define NVM_NVMBUSY_bm 0x80 /* Non-volatile Memory Busy bit mask. */ -#define NVM_NVMBUSY_bp 7 /* Non-volatile Memory Busy bit position. */ - -#define NVM_FBUSY_bm 0x40 /* Flash Memory Busy bit mask. */ -#define NVM_FBUSY_bp 6 /* Flash Memory Busy bit position. */ - -#define NVM_EELOAD_bm 0x02 /* EEPROM Page Buffer Active Loading bit mask. */ -#define NVM_EELOAD_bp 1 /* EEPROM Page Buffer Active Loading bit position. */ - -#define NVM_FLOAD_bm 0x01 /* Flash Page Buffer Active Loading bit mask. */ -#define NVM_FLOAD_bp 0 /* Flash Page Buffer Active Loading bit position. */ - - -/* NVM.LOCKBITS bit masks and bit positions */ -#define NVM_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ -#define NVM_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ -#define NVM_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ -#define NVM_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ -#define NVM_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ -#define NVM_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ - -#define NVM_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ -#define NVM_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ -#define NVM_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ -#define NVM_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ -#define NVM_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ -#define NVM_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ - -#define NVM_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ -#define NVM_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ -#define NVM_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ -#define NVM_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ -#define NVM_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ -#define NVM_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ - -#define NVM_LB_gm 0x03 /* Lock Bits group mask. */ -#define NVM_LB_gp 0 /* Lock Bits group position. */ -#define NVM_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ -#define NVM_LB0_bp 0 /* Lock Bits bit 0 position. */ -#define NVM_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ -#define NVM_LB1_bp 1 /* Lock Bits bit 1 position. */ - - -/* NVM_LOCKBITS.LOCKBITS bit masks and bit positions */ -#define NVM_LOCKBITS_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ -#define NVM_LOCKBITS_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ -#define NVM_LOCKBITS_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ -#define NVM_LOCKBITS_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ -#define NVM_LOCKBITS_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ -#define NVM_LOCKBITS_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ - -#define NVM_LOCKBITS_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ -#define NVM_LOCKBITS_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ -#define NVM_LOCKBITS_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ -#define NVM_LOCKBITS_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ -#define NVM_LOCKBITS_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ -#define NVM_LOCKBITS_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ - -#define NVM_LOCKBITS_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ -#define NVM_LOCKBITS_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ -#define NVM_LOCKBITS_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ -#define NVM_LOCKBITS_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ -#define NVM_LOCKBITS_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ -#define NVM_LOCKBITS_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ - -#define NVM_LOCKBITS_LB_gm 0x03 /* Lock Bits group mask. */ -#define NVM_LOCKBITS_LB_gp 0 /* Lock Bits group position. */ -#define NVM_LOCKBITS_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ -#define NVM_LOCKBITS_LB0_bp 0 /* Lock Bits bit 0 position. */ -#define NVM_LOCKBITS_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ -#define NVM_LOCKBITS_LB1_bp 1 /* Lock Bits bit 1 position. */ - - -/* NVM_FUSES.FUSEBYTE0 bit masks and bit positions */ -#define NVM_FUSES_USERID_gm 0xFF /* User ID group mask. */ -#define NVM_FUSES_USERID_gp 0 /* User ID group position. */ -#define NVM_FUSES_USERID0_bm (1<<0) /* User ID bit 0 mask. */ -#define NVM_FUSES_USERID0_bp 0 /* User ID bit 0 position. */ -#define NVM_FUSES_USERID1_bm (1<<1) /* User ID bit 1 mask. */ -#define NVM_FUSES_USERID1_bp 1 /* User ID bit 1 position. */ -#define NVM_FUSES_USERID2_bm (1<<2) /* User ID bit 2 mask. */ -#define NVM_FUSES_USERID2_bp 2 /* User ID bit 2 position. */ -#define NVM_FUSES_USERID3_bm (1<<3) /* User ID bit 3 mask. */ -#define NVM_FUSES_USERID3_bp 3 /* User ID bit 3 position. */ -#define NVM_FUSES_USERID4_bm (1<<4) /* User ID bit 4 mask. */ -#define NVM_FUSES_USERID4_bp 4 /* User ID bit 4 position. */ -#define NVM_FUSES_USERID5_bm (1<<5) /* User ID bit 5 mask. */ -#define NVM_FUSES_USERID5_bp 5 /* User ID bit 5 position. */ -#define NVM_FUSES_USERID6_bm (1<<6) /* User ID bit 6 mask. */ -#define NVM_FUSES_USERID6_bp 6 /* User ID bit 6 position. */ -#define NVM_FUSES_USERID7_bm (1<<7) /* User ID bit 7 mask. */ -#define NVM_FUSES_USERID7_bp 7 /* User ID bit 7 position. */ - - -/* NVM_FUSES.FUSEBYTE1 bit masks and bit positions */ -#define NVM_FUSES_WDWP_gm 0xF0 /* Watchdog Window Timeout Period group mask. */ -#define NVM_FUSES_WDWP_gp 4 /* Watchdog Window Timeout Period group position. */ -#define NVM_FUSES_WDWP0_bm (1<<4) /* Watchdog Window Timeout Period bit 0 mask. */ -#define NVM_FUSES_WDWP0_bp 4 /* Watchdog Window Timeout Period bit 0 position. */ -#define NVM_FUSES_WDWP1_bm (1<<5) /* Watchdog Window Timeout Period bit 1 mask. */ -#define NVM_FUSES_WDWP1_bp 5 /* Watchdog Window Timeout Period bit 1 position. */ -#define NVM_FUSES_WDWP2_bm (1<<6) /* Watchdog Window Timeout Period bit 2 mask. */ -#define NVM_FUSES_WDWP2_bp 6 /* Watchdog Window Timeout Period bit 2 position. */ -#define NVM_FUSES_WDWP3_bm (1<<7) /* Watchdog Window Timeout Period bit 3 mask. */ -#define NVM_FUSES_WDWP3_bp 7 /* Watchdog Window Timeout Period bit 3 position. */ - -#define NVM_FUSES_WDP_gm 0x0F /* Watchdog Timeout Period group mask. */ -#define NVM_FUSES_WDP_gp 0 /* Watchdog Timeout Period group position. */ -#define NVM_FUSES_WDP0_bm (1<<0) /* Watchdog Timeout Period bit 0 mask. */ -#define NVM_FUSES_WDP0_bp 0 /* Watchdog Timeout Period bit 0 position. */ -#define NVM_FUSES_WDP1_bm (1<<1) /* Watchdog Timeout Period bit 1 mask. */ -#define NVM_FUSES_WDP1_bp 1 /* Watchdog Timeout Period bit 1 position. */ -#define NVM_FUSES_WDP2_bm (1<<2) /* Watchdog Timeout Period bit 2 mask. */ -#define NVM_FUSES_WDP2_bp 2 /* Watchdog Timeout Period bit 2 position. */ -#define NVM_FUSES_WDP3_bm (1<<3) /* Watchdog Timeout Period bit 3 mask. */ -#define NVM_FUSES_WDP3_bp 3 /* Watchdog Timeout Period bit 3 position. */ - - -/* NVM_FUSES.FUSEBYTE2 bit masks and bit positions */ -#define NVM_FUSES_DVSDON_bm 0x80 /* Spike Detector Enable bit mask. */ -#define NVM_FUSES_DVSDON_bp 7 /* Spike Detector Enable bit position. */ - -#define NVM_FUSES_BOOTRST_bm 0x40 /* Boot Loader Section Reset Vector bit mask. */ -#define NVM_FUSES_BOOTRST_bp 6 /* Boot Loader Section Reset Vector bit position. */ - -#define NVM_FUSES_BODPD_gm 0x03 /* BOD Operation in Power-Down Mode group mask. */ -#define NVM_FUSES_BODPD_gp 0 /* BOD Operation in Power-Down Mode group position. */ -#define NVM_FUSES_BODPD0_bm (1<<0) /* BOD Operation in Power-Down Mode bit 0 mask. */ -#define NVM_FUSES_BODPD0_bp 0 /* BOD Operation in Power-Down Mode bit 0 position. */ -#define NVM_FUSES_BODPD1_bm (1<<1) /* BOD Operation in Power-Down Mode bit 1 mask. */ -#define NVM_FUSES_BODPD1_bp 1 /* BOD Operation in Power-Down Mode bit 1 position. */ - - -/* NVM_FUSES.FUSEBYTE4 bit masks and bit positions */ -#define NVM_FUSES_SUT_gm 0x0C /* Start-up Time group mask. */ -#define NVM_FUSES_SUT_gp 2 /* Start-up Time group position. */ -#define NVM_FUSES_SUT0_bm (1<<2) /* Start-up Time bit 0 mask. */ -#define NVM_FUSES_SUT0_bp 2 /* Start-up Time bit 0 position. */ -#define NVM_FUSES_SUT1_bm (1<<3) /* Start-up Time bit 1 mask. */ -#define NVM_FUSES_SUT1_bp 3 /* Start-up Time bit 1 position. */ - -#define NVM_FUSES_WDLOCK_bm 0x02 /* Watchdog Timer Lock bit mask. */ -#define NVM_FUSES_WDLOCK_bp 1 /* Watchdog Timer Lock bit position. */ - - -/* NVM_FUSES.FUSEBYTE5 bit masks and bit positions */ -#define NVM_FUSES_BODACT_gm 0x30 /* BOD Operation in Active Mode group mask. */ -#define NVM_FUSES_BODACT_gp 4 /* BOD Operation in Active Mode group position. */ -#define NVM_FUSES_BODACT0_bm (1<<4) /* BOD Operation in Active Mode bit 0 mask. */ -#define NVM_FUSES_BODACT0_bp 4 /* BOD Operation in Active Mode bit 0 position. */ -#define NVM_FUSES_BODACT1_bm (1<<5) /* BOD Operation in Active Mode bit 1 mask. */ -#define NVM_FUSES_BODACT1_bp 5 /* BOD Operation in Active Mode bit 1 position. */ - -#define NVM_FUSES_EESAVE_bm 0x08 /* Preserve EEPROM Through Chip Erase bit mask. */ -#define NVM_FUSES_EESAVE_bp 3 /* Preserve EEPROM Through Chip Erase bit position. */ - -#define NVM_FUSES_BODLVL_gm 0x07 /* Brown Out Detection Voltage Level group mask. */ -#define NVM_FUSES_BODLVL_gp 0 /* Brown Out Detection Voltage Level group position. */ -#define NVM_FUSES_BODLVL0_bm (1<<0) /* Brown Out Detection Voltage Level bit 0 mask. */ -#define NVM_FUSES_BODLVL0_bp 0 /* Brown Out Detection Voltage Level bit 0 position. */ -#define NVM_FUSES_BODLVL1_bm (1<<1) /* Brown Out Detection Voltage Level bit 1 mask. */ -#define NVM_FUSES_BODLVL1_bp 1 /* Brown Out Detection Voltage Level bit 1 position. */ -#define NVM_FUSES_BODLVL2_bm (1<<2) /* Brown Out Detection Voltage Level bit 2 mask. */ -#define NVM_FUSES_BODLVL2_bp 2 /* Brown Out Detection Voltage Level bit 2 position. */ - - -/* AC - Analog Comparator */ -/* AC.AC0CTRL bit masks and bit positions */ -#define AC_INTMODE_gm 0xC0 /* Interrupt Mode group mask. */ -#define AC_INTMODE_gp 6 /* Interrupt Mode group position. */ -#define AC_INTMODE0_bm (1<<6) /* Interrupt Mode bit 0 mask. */ -#define AC_INTMODE0_bp 6 /* Interrupt Mode bit 0 position. */ -#define AC_INTMODE1_bm (1<<7) /* Interrupt Mode bit 1 mask. */ -#define AC_INTMODE1_bp 7 /* Interrupt Mode bit 1 position. */ - -#define AC_INTLVL_gm 0x30 /* Interrupt Level group mask. */ -#define AC_INTLVL_gp 4 /* Interrupt Level group position. */ -#define AC_INTLVL0_bm (1<<4) /* Interrupt Level bit 0 mask. */ -#define AC_INTLVL0_bp 4 /* Interrupt Level bit 0 position. */ -#define AC_INTLVL1_bm (1<<5) /* Interrupt Level bit 1 mask. */ -#define AC_INTLVL1_bp 5 /* Interrupt Level bit 1 position. */ - -#define AC_HSMODE_bm 0x08 /* High-speed Mode bit mask. */ -#define AC_HSMODE_bp 3 /* High-speed Mode bit position. */ - -#define AC_HYSMODE_gm 0x06 /* Hysteresis Mode group mask. */ -#define AC_HYSMODE_gp 1 /* Hysteresis Mode group position. */ -#define AC_HYSMODE0_bm (1<<1) /* Hysteresis Mode bit 0 mask. */ -#define AC_HYSMODE0_bp 1 /* Hysteresis Mode bit 0 position. */ -#define AC_HYSMODE1_bm (1<<2) /* Hysteresis Mode bit 1 mask. */ -#define AC_HYSMODE1_bp 2 /* Hysteresis Mode bit 1 position. */ - -#define AC_ENABLE_bm 0x01 /* Enable bit mask. */ -#define AC_ENABLE_bp 0 /* Enable bit position. */ - - -/* AC.AC1CTRL bit masks and bit positions */ -/* AC_INTMODE_gm Predefined. */ -/* AC_INTMODE_gp Predefined. */ -/* AC_INTMODE0_bm Predefined. */ -/* AC_INTMODE0_bp Predefined. */ -/* AC_INTMODE1_bm Predefined. */ -/* AC_INTMODE1_bp Predefined. */ - -/* AC_INTLVL_gm Predefined. */ -/* AC_INTLVL_gp Predefined. */ -/* AC_INTLVL0_bm Predefined. */ -/* AC_INTLVL0_bp Predefined. */ -/* AC_INTLVL1_bm Predefined. */ -/* AC_INTLVL1_bp Predefined. */ - -/* AC_HSMODE_bm Predefined. */ -/* AC_HSMODE_bp Predefined. */ - -/* AC_HYSMODE_gm Predefined. */ -/* AC_HYSMODE_gp Predefined. */ -/* AC_HYSMODE0_bm Predefined. */ -/* AC_HYSMODE0_bp Predefined. */ -/* AC_HYSMODE1_bm Predefined. */ -/* AC_HYSMODE1_bp Predefined. */ - -/* AC_ENABLE_bm Predefined. */ -/* AC_ENABLE_bp Predefined. */ - - -/* AC.AC0MUXCTRL bit masks and bit positions */ -#define AC_MUXPOS_gm 0x38 /* MUX Positive Input group mask. */ -#define AC_MUXPOS_gp 3 /* MUX Positive Input group position. */ -#define AC_MUXPOS0_bm (1<<3) /* MUX Positive Input bit 0 mask. */ -#define AC_MUXPOS0_bp 3 /* MUX Positive Input bit 0 position. */ -#define AC_MUXPOS1_bm (1<<4) /* MUX Positive Input bit 1 mask. */ -#define AC_MUXPOS1_bp 4 /* MUX Positive Input bit 1 position. */ -#define AC_MUXPOS2_bm (1<<5) /* MUX Positive Input bit 2 mask. */ -#define AC_MUXPOS2_bp 5 /* MUX Positive Input bit 2 position. */ - -#define AC_MUXNEG_gm 0x07 /* MUX Negative Input group mask. */ -#define AC_MUXNEG_gp 0 /* MUX Negative Input group position. */ -#define AC_MUXNEG0_bm (1<<0) /* MUX Negative Input bit 0 mask. */ -#define AC_MUXNEG0_bp 0 /* MUX Negative Input bit 0 position. */ -#define AC_MUXNEG1_bm (1<<1) /* MUX Negative Input bit 1 mask. */ -#define AC_MUXNEG1_bp 1 /* MUX Negative Input bit 1 position. */ -#define AC_MUXNEG2_bm (1<<2) /* MUX Negative Input bit 2 mask. */ -#define AC_MUXNEG2_bp 2 /* MUX Negative Input bit 2 position. */ - - -/* AC.AC1MUXCTRL bit masks and bit positions */ -/* AC_MUXPOS_gm Predefined. */ -/* AC_MUXPOS_gp Predefined. */ -/* AC_MUXPOS0_bm Predefined. */ -/* AC_MUXPOS0_bp Predefined. */ -/* AC_MUXPOS1_bm Predefined. */ -/* AC_MUXPOS1_bp Predefined. */ -/* AC_MUXPOS2_bm Predefined. */ -/* AC_MUXPOS2_bp Predefined. */ - -/* AC_MUXNEG_gm Predefined. */ -/* AC_MUXNEG_gp Predefined. */ -/* AC_MUXNEG0_bm Predefined. */ -/* AC_MUXNEG0_bp Predefined. */ -/* AC_MUXNEG1_bm Predefined. */ -/* AC_MUXNEG1_bp Predefined. */ -/* AC_MUXNEG2_bm Predefined. */ -/* AC_MUXNEG2_bp Predefined. */ - - -/* AC.CTRLA bit masks and bit positions */ -#define AC_AC0OUT_bm 0x01 /* Comparator 0 Output Enable bit mask. */ -#define AC_AC0OUT_bp 0 /* Comparator 0 Output Enable bit position. */ - - -/* AC.CTRLB bit masks and bit positions */ -#define AC_SCALEFAC_gm 0x3F /* VCC Voltage Scaler Factor group mask. */ -#define AC_SCALEFAC_gp 0 /* VCC Voltage Scaler Factor group position. */ -#define AC_SCALEFAC0_bm (1<<0) /* VCC Voltage Scaler Factor bit 0 mask. */ -#define AC_SCALEFAC0_bp 0 /* VCC Voltage Scaler Factor bit 0 position. */ -#define AC_SCALEFAC1_bm (1<<1) /* VCC Voltage Scaler Factor bit 1 mask. */ -#define AC_SCALEFAC1_bp 1 /* VCC Voltage Scaler Factor bit 1 position. */ -#define AC_SCALEFAC2_bm (1<<2) /* VCC Voltage Scaler Factor bit 2 mask. */ -#define AC_SCALEFAC2_bp 2 /* VCC Voltage Scaler Factor bit 2 position. */ -#define AC_SCALEFAC3_bm (1<<3) /* VCC Voltage Scaler Factor bit 3 mask. */ -#define AC_SCALEFAC3_bp 3 /* VCC Voltage Scaler Factor bit 3 position. */ -#define AC_SCALEFAC4_bm (1<<4) /* VCC Voltage Scaler Factor bit 4 mask. */ -#define AC_SCALEFAC4_bp 4 /* VCC Voltage Scaler Factor bit 4 position. */ -#define AC_SCALEFAC5_bm (1<<5) /* VCC Voltage Scaler Factor bit 5 mask. */ -#define AC_SCALEFAC5_bp 5 /* VCC Voltage Scaler Factor bit 5 position. */ - - -/* AC.WINCTRL bit masks and bit positions */ -#define AC_WEN_bm 0x10 /* Window Mode Enable bit mask. */ -#define AC_WEN_bp 4 /* Window Mode Enable bit position. */ - -#define AC_WINTMODE_gm 0x0C /* Window Interrupt Mode group mask. */ -#define AC_WINTMODE_gp 2 /* Window Interrupt Mode group position. */ -#define AC_WINTMODE0_bm (1<<2) /* Window Interrupt Mode bit 0 mask. */ -#define AC_WINTMODE0_bp 2 /* Window Interrupt Mode bit 0 position. */ -#define AC_WINTMODE1_bm (1<<3) /* Window Interrupt Mode bit 1 mask. */ -#define AC_WINTMODE1_bp 3 /* Window Interrupt Mode bit 1 position. */ - -#define AC_WINTLVL_gm 0x03 /* Window Interrupt Level group mask. */ -#define AC_WINTLVL_gp 0 /* Window Interrupt Level group position. */ -#define AC_WINTLVL0_bm (1<<0) /* Window Interrupt Level bit 0 mask. */ -#define AC_WINTLVL0_bp 0 /* Window Interrupt Level bit 0 position. */ -#define AC_WINTLVL1_bm (1<<1) /* Window Interrupt Level bit 1 mask. */ -#define AC_WINTLVL1_bp 1 /* Window Interrupt Level bit 1 position. */ - - -/* AC.STATUS bit masks and bit positions */ -#define AC_WSTATE_gm 0xC0 /* Window Mode State group mask. */ -#define AC_WSTATE_gp 6 /* Window Mode State group position. */ -#define AC_WSTATE0_bm (1<<6) /* Window Mode State bit 0 mask. */ -#define AC_WSTATE0_bp 6 /* Window Mode State bit 0 position. */ -#define AC_WSTATE1_bm (1<<7) /* Window Mode State bit 1 mask. */ -#define AC_WSTATE1_bp 7 /* Window Mode State bit 1 position. */ - -#define AC_AC1STATE_bm 0x20 /* Comparator 1 State bit mask. */ -#define AC_AC1STATE_bp 5 /* Comparator 1 State bit position. */ - -#define AC_AC0STATE_bm 0x10 /* Comparator 0 State bit mask. */ -#define AC_AC0STATE_bp 4 /* Comparator 0 State bit position. */ - -#define AC_WIF_bm 0x04 /* Window Mode Interrupt Flag bit mask. */ -#define AC_WIF_bp 2 /* Window Mode Interrupt Flag bit position. */ - -#define AC_AC1IF_bm 0x02 /* Comparator 1 Interrupt Flag bit mask. */ -#define AC_AC1IF_bp 1 /* Comparator 1 Interrupt Flag bit position. */ - -#define AC_AC0IF_bm 0x01 /* Comparator 0 Interrupt Flag bit mask. */ -#define AC_AC0IF_bp 0 /* Comparator 0 Interrupt Flag bit position. */ - - -/* ADC - Analog/Digital Converter */ -/* ADC_CH.CTRL bit masks and bit positions */ -#define ADC_CH_START_bm 0x80 /* Channel Start Conversion bit mask. */ -#define ADC_CH_START_bp 7 /* Channel Start Conversion bit position. */ - -#define ADC_CH_GAINFAC_gm 0x1C /* Gain Factor group mask. */ -#define ADC_CH_GAINFAC_gp 2 /* Gain Factor group position. */ -#define ADC_CH_GAINFAC0_bm (1<<2) /* Gain Factor bit 0 mask. */ -#define ADC_CH_GAINFAC0_bp 2 /* Gain Factor bit 0 position. */ -#define ADC_CH_GAINFAC1_bm (1<<3) /* Gain Factor bit 1 mask. */ -#define ADC_CH_GAINFAC1_bp 3 /* Gain Factor bit 1 position. */ -#define ADC_CH_GAINFAC2_bm (1<<4) /* Gain Factor bit 2 mask. */ -#define ADC_CH_GAINFAC2_bp 4 /* Gain Factor bit 2 position. */ - -#define ADC_CH_INPUTMODE_gm 0x03 /* Input Mode Select group mask. */ -#define ADC_CH_INPUTMODE_gp 0 /* Input Mode Select group position. */ -#define ADC_CH_INPUTMODE0_bm (1<<0) /* Input Mode Select bit 0 mask. */ -#define ADC_CH_INPUTMODE0_bp 0 /* Input Mode Select bit 0 position. */ -#define ADC_CH_INPUTMODE1_bm (1<<1) /* Input Mode Select bit 1 mask. */ -#define ADC_CH_INPUTMODE1_bp 1 /* Input Mode Select bit 1 position. */ - - -/* ADC_CH.MUXCTRL bit masks and bit positions */ -#define ADC_CH_MUXPOS_gm 0x78 /* Positive Input Select group mask. */ -#define ADC_CH_MUXPOS_gp 3 /* Positive Input Select group position. */ -#define ADC_CH_MUXPOS0_bm (1<<3) /* Positive Input Select bit 0 mask. */ -#define ADC_CH_MUXPOS0_bp 3 /* Positive Input Select bit 0 position. */ -#define ADC_CH_MUXPOS1_bm (1<<4) /* Positive Input Select bit 1 mask. */ -#define ADC_CH_MUXPOS1_bp 4 /* Positive Input Select bit 1 position. */ -#define ADC_CH_MUXPOS2_bm (1<<5) /* Positive Input Select bit 2 mask. */ -#define ADC_CH_MUXPOS2_bp 5 /* Positive Input Select bit 2 position. */ -#define ADC_CH_MUXPOS3_bm (1<<6) /* Positive Input Select bit 3 mask. */ -#define ADC_CH_MUXPOS3_bp 6 /* Positive Input Select bit 3 position. */ - -#define ADC_CH_MUXINT_gm 0x78 /* Internal Input Select group mask. */ -#define ADC_CH_MUXINT_gp 3 /* Internal Input Select group position. */ -#define ADC_CH_MUXINT0_bm (1<<3) /* Internal Input Select bit 0 mask. */ -#define ADC_CH_MUXINT0_bp 3 /* Internal Input Select bit 0 position. */ -#define ADC_CH_MUXINT1_bm (1<<4) /* Internal Input Select bit 1 mask. */ -#define ADC_CH_MUXINT1_bp 4 /* Internal Input Select bit 1 position. */ -#define ADC_CH_MUXINT2_bm (1<<5) /* Internal Input Select bit 2 mask. */ -#define ADC_CH_MUXINT2_bp 5 /* Internal Input Select bit 2 position. */ -#define ADC_CH_MUXINT3_bm (1<<6) /* Internal Input Select bit 3 mask. */ -#define ADC_CH_MUXINT3_bp 6 /* Internal Input Select bit 3 position. */ - -#define ADC_CH_MUXNEG_gm 0x03 /* Negative Input Select group mask. */ -#define ADC_CH_MUXNEG_gp 0 /* Negative Input Select group position. */ -#define ADC_CH_MUXNEG0_bm (1<<0) /* Negative Input Select bit 0 mask. */ -#define ADC_CH_MUXNEG0_bp 0 /* Negative Input Select bit 0 position. */ -#define ADC_CH_MUXNEG1_bm (1<<1) /* Negative Input Select bit 1 mask. */ -#define ADC_CH_MUXNEG1_bp 1 /* Negative Input Select bit 1 position. */ - - -/* ADC_CH.INTCTRL bit masks and bit positions */ -#define ADC_CH_INTMODE_gm 0x0C /* Interrupt Mode group mask. */ -#define ADC_CH_INTMODE_gp 2 /* Interrupt Mode group position. */ -#define ADC_CH_INTMODE0_bm (1<<2) /* Interrupt Mode bit 0 mask. */ -#define ADC_CH_INTMODE0_bp 2 /* Interrupt Mode bit 0 position. */ -#define ADC_CH_INTMODE1_bm (1<<3) /* Interrupt Mode bit 1 mask. */ -#define ADC_CH_INTMODE1_bp 3 /* Interrupt Mode bit 1 position. */ - -#define ADC_CH_INTLVL_gm 0x03 /* Interrupt Level group mask. */ -#define ADC_CH_INTLVL_gp 0 /* Interrupt Level group position. */ -#define ADC_CH_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */ -#define ADC_CH_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */ -#define ADC_CH_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ -#define ADC_CH_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */ - - -/* ADC_CH.INTFLAGS bit masks and bit positions */ -#define ADC_CH_CHIF_bm 0x01 /* Channel Interrupt Flag bit mask. */ -#define ADC_CH_CHIF_bp 0 /* Channel Interrupt Flag bit position. */ - - -/* ADC.CTRLA bit masks and bit positions */ -#define ADC_CH0START_bm 0x04 /* Channel 0 Start Conversion bit mask. */ -#define ADC_CH0START_bp 2 /* Channel 0 Start Conversion bit position. */ - -#define ADC_FLUSH_bm 0x02 /* ADC Flush bit mask. */ -#define ADC_FLUSH_bp 1 /* ADC Flush bit position. */ - -#define ADC_ENABLE_bm 0x01 /* Enable ADC bit mask. */ -#define ADC_ENABLE_bp 0 /* Enable ADC bit position. */ - - -/* ADC.CTRLB bit masks and bit positions */ -#define ADC_CURRLIMIT_gm 0x60 /* Current Limitation group mask. */ -#define ADC_CURRLIMIT_gp 5 /* Current Limitation group position. */ -#define ADC_CURRLIMIT0_bm (1<<5) /* Current Limitation bit 0 mask. */ -#define ADC_CURRLIMIT0_bp 5 /* Current Limitation bit 0 position. */ -#define ADC_CURRLIMIT1_bm (1<<6) /* Current Limitation bit 1 mask. */ -#define ADC_CURRLIMIT1_bp 6 /* Current Limitation bit 1 position. */ - -#define ADC_CONMODE_bm 0x10 /* Conversion Mode bit mask. */ -#define ADC_CONMODE_bp 4 /* Conversion Mode bit position. */ - -#define ADC_FREERUN_bm 0x08 /* Free Running Mode Enable bit mask. */ -#define ADC_FREERUN_bp 3 /* Free Running Mode Enable bit position. */ - -#define ADC_RESOLUTION_gm 0x06 /* Result Resolution group mask. */ -#define ADC_RESOLUTION_gp 1 /* Result Resolution group position. */ -#define ADC_RESOLUTION0_bm (1<<1) /* Result Resolution bit 0 mask. */ -#define ADC_RESOLUTION0_bp 1 /* Result Resolution bit 0 position. */ -#define ADC_RESOLUTION1_bm (1<<2) /* Result Resolution bit 1 mask. */ -#define ADC_RESOLUTION1_bp 2 /* Result Resolution bit 1 position. */ - - -/* ADC.REFCTRL bit masks and bit positions */ -#define ADC_REFSEL_gm 0x30 /* Reference Selection group mask. */ -#define ADC_REFSEL_gp 4 /* Reference Selection group position. */ -#define ADC_REFSEL0_bm (1<<4) /* Reference Selection bit 0 mask. */ -#define ADC_REFSEL0_bp 4 /* Reference Selection bit 0 position. */ -#define ADC_REFSEL1_bm (1<<5) /* Reference Selection bit 1 mask. */ -#define ADC_REFSEL1_bp 5 /* Reference Selection bit 1 position. */ - -#define ADC_BANDGAP_bm 0x02 /* Bandgap enable bit mask. */ -#define ADC_BANDGAP_bp 1 /* Bandgap enable bit position. */ - -#define ADC_TEMPREF_bm 0x01 /* Temperature Reference Enable bit mask. */ -#define ADC_TEMPREF_bp 0 /* Temperature Reference Enable bit position. */ - - -/* ADC.EVCTRL bit masks and bit positions */ -#define ADC_SWEEP_gm 0xC0 /* Channel Sweep Selection group mask. */ -#define ADC_SWEEP_gp 6 /* Channel Sweep Selection group position. */ -#define ADC_SWEEP0_bm (1<<6) /* Channel Sweep Selection bit 0 mask. */ -#define ADC_SWEEP0_bp 6 /* Channel Sweep Selection bit 0 position. */ -#define ADC_SWEEP1_bm (1<<7) /* Channel Sweep Selection bit 1 mask. */ -#define ADC_SWEEP1_bp 7 /* Channel Sweep Selection bit 1 position. */ - -#define ADC_EVSEL_gm 0x38 /* Event Input Select group mask. */ -#define ADC_EVSEL_gp 3 /* Event Input Select group position. */ -#define ADC_EVSEL0_bm (1<<3) /* Event Input Select bit 0 mask. */ -#define ADC_EVSEL0_bp 3 /* Event Input Select bit 0 position. */ -#define ADC_EVSEL1_bm (1<<4) /* Event Input Select bit 1 mask. */ -#define ADC_EVSEL1_bp 4 /* Event Input Select bit 1 position. */ -#define ADC_EVSEL2_bm (1<<5) /* Event Input Select bit 2 mask. */ -#define ADC_EVSEL2_bp 5 /* Event Input Select bit 2 position. */ - -#define ADC_EVACT_gm 0x07 /* Event Action Select group mask. */ -#define ADC_EVACT_gp 0 /* Event Action Select group position. */ -#define ADC_EVACT0_bm (1<<0) /* Event Action Select bit 0 mask. */ -#define ADC_EVACT0_bp 0 /* Event Action Select bit 0 position. */ -#define ADC_EVACT1_bm (1<<1) /* Event Action Select bit 1 mask. */ -#define ADC_EVACT1_bp 1 /* Event Action Select bit 1 position. */ -#define ADC_EVACT2_bm (1<<2) /* Event Action Select bit 2 mask. */ -#define ADC_EVACT2_bp 2 /* Event Action Select bit 2 position. */ - - -/* ADC.PRESCALER bit masks and bit positions */ -#define ADC_PRESCALER_gm 0x07 /* Clock Prescaler Selection group mask. */ -#define ADC_PRESCALER_gp 0 /* Clock Prescaler Selection group position. */ -#define ADC_PRESCALER0_bm (1<<0) /* Clock Prescaler Selection bit 0 mask. */ -#define ADC_PRESCALER0_bp 0 /* Clock Prescaler Selection bit 0 position. */ -#define ADC_PRESCALER1_bm (1<<1) /* Clock Prescaler Selection bit 1 mask. */ -#define ADC_PRESCALER1_bp 1 /* Clock Prescaler Selection bit 1 position. */ -#define ADC_PRESCALER2_bm (1<<2) /* Clock Prescaler Selection bit 2 mask. */ -#define ADC_PRESCALER2_bp 2 /* Clock Prescaler Selection bit 2 position. */ - - -/* ADC.INTFLAGS bit masks and bit positions */ -#define ADC_CH0IF_bm 0x01 /* Channel 0 Interrupt Flag bit mask. */ -#define ADC_CH0IF_bp 0 /* Channel 0 Interrupt Flag bit position. */ - - -/* RTC - Real-Time Clounter */ -/* RTC.CTRL bit masks and bit positions */ -#define RTC_PRESCALER_gm 0x07 /* Prescaling Factor group mask. */ -#define RTC_PRESCALER_gp 0 /* Prescaling Factor group position. */ -#define RTC_PRESCALER0_bm (1<<0) /* Prescaling Factor bit 0 mask. */ -#define RTC_PRESCALER0_bp 0 /* Prescaling Factor bit 0 position. */ -#define RTC_PRESCALER1_bm (1<<1) /* Prescaling Factor bit 1 mask. */ -#define RTC_PRESCALER1_bp 1 /* Prescaling Factor bit 1 position. */ -#define RTC_PRESCALER2_bm (1<<2) /* Prescaling Factor bit 2 mask. */ -#define RTC_PRESCALER2_bp 2 /* Prescaling Factor bit 2 position. */ - - -/* RTC.STATUS bit masks and bit positions */ -#define RTC_SYNCBUSY_bm 0x01 /* Synchronization Busy Flag bit mask. */ -#define RTC_SYNCBUSY_bp 0 /* Synchronization Busy Flag bit position. */ - - -/* RTC.INTCTRL bit masks and bit positions */ -#define RTC_COMPINTLVL_gm 0x0C /* Compare Match Interrupt Level group mask. */ -#define RTC_COMPINTLVL_gp 2 /* Compare Match Interrupt Level group position. */ -#define RTC_COMPINTLVL0_bm (1<<2) /* Compare Match Interrupt Level bit 0 mask. */ -#define RTC_COMPINTLVL0_bp 2 /* Compare Match Interrupt Level bit 0 position. */ -#define RTC_COMPINTLVL1_bm (1<<3) /* Compare Match Interrupt Level bit 1 mask. */ -#define RTC_COMPINTLVL1_bp 3 /* Compare Match Interrupt Level bit 1 position. */ - -#define RTC_OVFINTLVL_gm 0x03 /* Overflow Interrupt Level group mask. */ -#define RTC_OVFINTLVL_gp 0 /* Overflow Interrupt Level group position. */ -#define RTC_OVFINTLVL0_bm (1<<0) /* Overflow Interrupt Level bit 0 mask. */ -#define RTC_OVFINTLVL0_bp 0 /* Overflow Interrupt Level bit 0 position. */ -#define RTC_OVFINTLVL1_bm (1<<1) /* Overflow Interrupt Level bit 1 mask. */ -#define RTC_OVFINTLVL1_bp 1 /* Overflow Interrupt Level bit 1 position. */ - - -/* RTC.INTFLAGS bit masks and bit positions */ -#define RTC_COMPIF_bm 0x02 /* Compare Match Interrupt Flag bit mask. */ -#define RTC_COMPIF_bp 1 /* Compare Match Interrupt Flag bit position. */ - -#define RTC_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ -#define RTC_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ - - -/* EBI - External Bus Interface */ -/* EBI_CS.CTRLA bit masks and bit positions */ -#define EBI_CS_ASIZE_gm 0x7C /* Address Size group mask. */ -#define EBI_CS_ASIZE_gp 2 /* Address Size group position. */ -#define EBI_CS_ASIZE0_bm (1<<2) /* Address Size bit 0 mask. */ -#define EBI_CS_ASIZE0_bp 2 /* Address Size bit 0 position. */ -#define EBI_CS_ASIZE1_bm (1<<3) /* Address Size bit 1 mask. */ -#define EBI_CS_ASIZE1_bp 3 /* Address Size bit 1 position. */ -#define EBI_CS_ASIZE2_bm (1<<4) /* Address Size bit 2 mask. */ -#define EBI_CS_ASIZE2_bp 4 /* Address Size bit 2 position. */ -#define EBI_CS_ASIZE3_bm (1<<5) /* Address Size bit 3 mask. */ -#define EBI_CS_ASIZE3_bp 5 /* Address Size bit 3 position. */ -#define EBI_CS_ASIZE4_bm (1<<6) /* Address Size bit 4 mask. */ -#define EBI_CS_ASIZE4_bp 6 /* Address Size bit 4 position. */ - -#define EBI_CS_MODE_gm 0x03 /* Memory Mode group mask. */ -#define EBI_CS_MODE_gp 0 /* Memory Mode group position. */ -#define EBI_CS_MODE0_bm (1<<0) /* Memory Mode bit 0 mask. */ -#define EBI_CS_MODE0_bp 0 /* Memory Mode bit 0 position. */ -#define EBI_CS_MODE1_bm (1<<1) /* Memory Mode bit 1 mask. */ -#define EBI_CS_MODE1_bp 1 /* Memory Mode bit 1 position. */ - - -/* EBI_CS.CTRLB bit masks and bit positions */ -#define EBI_CS_SRWS_gm 0x07 /* SRAM Wait State Cycles group mask. */ -#define EBI_CS_SRWS_gp 0 /* SRAM Wait State Cycles group position. */ -#define EBI_CS_SRWS0_bm (1<<0) /* SRAM Wait State Cycles bit 0 mask. */ -#define EBI_CS_SRWS0_bp 0 /* SRAM Wait State Cycles bit 0 position. */ -#define EBI_CS_SRWS1_bm (1<<1) /* SRAM Wait State Cycles bit 1 mask. */ -#define EBI_CS_SRWS1_bp 1 /* SRAM Wait State Cycles bit 1 position. */ -#define EBI_CS_SRWS2_bm (1<<2) /* SRAM Wait State Cycles bit 2 mask. */ -#define EBI_CS_SRWS2_bp 2 /* SRAM Wait State Cycles bit 2 position. */ - -#define EBI_CS_SDINITDONE_bm 0x80 /* SDRAM Initialization Done bit mask. */ -#define EBI_CS_SDINITDONE_bp 7 /* SDRAM Initialization Done bit position. */ - -#define EBI_CS_SDSREN_bm 0x04 /* SDRAM Self-refresh Enable bit mask. */ -#define EBI_CS_SDSREN_bp 2 /* SDRAM Self-refresh Enable bit position. */ - -#define EBI_CS_SDMODE_gm 0x03 /* SDRAM Mode group mask. */ -#define EBI_CS_SDMODE_gp 0 /* SDRAM Mode group position. */ -#define EBI_CS_SDMODE0_bm (1<<0) /* SDRAM Mode bit 0 mask. */ -#define EBI_CS_SDMODE0_bp 0 /* SDRAM Mode bit 0 position. */ -#define EBI_CS_SDMODE1_bm (1<<1) /* SDRAM Mode bit 1 mask. */ -#define EBI_CS_SDMODE1_bp 1 /* SDRAM Mode bit 1 position. */ - - -/* EBI.CTRL bit masks and bit positions */ -#define EBI_SDDATAW_gm 0xC0 /* SDRAM Data Width Setting group mask. */ -#define EBI_SDDATAW_gp 6 /* SDRAM Data Width Setting group position. */ -#define EBI_SDDATAW0_bm (1<<6) /* SDRAM Data Width Setting bit 0 mask. */ -#define EBI_SDDATAW0_bp 6 /* SDRAM Data Width Setting bit 0 position. */ -#define EBI_SDDATAW1_bm (1<<7) /* SDRAM Data Width Setting bit 1 mask. */ -#define EBI_SDDATAW1_bp 7 /* SDRAM Data Width Setting bit 1 position. */ - -#define EBI_LPCMODE_gm 0x30 /* SRAM LPC Mode group mask. */ -#define EBI_LPCMODE_gp 4 /* SRAM LPC Mode group position. */ -#define EBI_LPCMODE0_bm (1<<4) /* SRAM LPC Mode bit 0 mask. */ -#define EBI_LPCMODE0_bp 4 /* SRAM LPC Mode bit 0 position. */ -#define EBI_LPCMODE1_bm (1<<5) /* SRAM LPC Mode bit 1 mask. */ -#define EBI_LPCMODE1_bp 5 /* SRAM LPC Mode bit 1 position. */ - -#define EBI_SRMODE_gm 0x0C /* SRAM Mode group mask. */ -#define EBI_SRMODE_gp 2 /* SRAM Mode group position. */ -#define EBI_SRMODE0_bm (1<<2) /* SRAM Mode bit 0 mask. */ -#define EBI_SRMODE0_bp 2 /* SRAM Mode bit 0 position. */ -#define EBI_SRMODE1_bm (1<<3) /* SRAM Mode bit 1 mask. */ -#define EBI_SRMODE1_bp 3 /* SRAM Mode bit 1 position. */ - -#define EBI_IFMODE_gm 0x03 /* Interface Mode group mask. */ -#define EBI_IFMODE_gp 0 /* Interface Mode group position. */ -#define EBI_IFMODE0_bm (1<<0) /* Interface Mode bit 0 mask. */ -#define EBI_IFMODE0_bp 0 /* Interface Mode bit 0 position. */ -#define EBI_IFMODE1_bm (1<<1) /* Interface Mode bit 1 mask. */ -#define EBI_IFMODE1_bp 1 /* Interface Mode bit 1 position. */ - - -/* EBI.SDRAMCTRLA bit masks and bit positions */ -#define EBI_SDCAS_bm 0x08 /* SDRAM CAS Latency Setting bit mask. */ -#define EBI_SDCAS_bp 3 /* SDRAM CAS Latency Setting bit position. */ - -#define EBI_SDROW_bm 0x04 /* SDRAM ROW Bits Setting bit mask. */ -#define EBI_SDROW_bp 2 /* SDRAM ROW Bits Setting bit position. */ - -#define EBI_SDCOL_gm 0x03 /* SDRAM Column Bits Setting group mask. */ -#define EBI_SDCOL_gp 0 /* SDRAM Column Bits Setting group position. */ -#define EBI_SDCOL0_bm (1<<0) /* SDRAM Column Bits Setting bit 0 mask. */ -#define EBI_SDCOL0_bp 0 /* SDRAM Column Bits Setting bit 0 position. */ -#define EBI_SDCOL1_bm (1<<1) /* SDRAM Column Bits Setting bit 1 mask. */ -#define EBI_SDCOL1_bp 1 /* SDRAM Column Bits Setting bit 1 position. */ - - -/* EBI.SDRAMCTRLB bit masks and bit positions */ -#define EBI_MRDLY_gm 0xC0 /* SDRAM Mode Register Delay group mask. */ -#define EBI_MRDLY_gp 6 /* SDRAM Mode Register Delay group position. */ -#define EBI_MRDLY0_bm (1<<6) /* SDRAM Mode Register Delay bit 0 mask. */ -#define EBI_MRDLY0_bp 6 /* SDRAM Mode Register Delay bit 0 position. */ -#define EBI_MRDLY1_bm (1<<7) /* SDRAM Mode Register Delay bit 1 mask. */ -#define EBI_MRDLY1_bp 7 /* SDRAM Mode Register Delay bit 1 position. */ - -#define EBI_ROWCYCDLY_gm 0x38 /* SDRAM Row Cycle Delay group mask. */ -#define EBI_ROWCYCDLY_gp 3 /* SDRAM Row Cycle Delay group position. */ -#define EBI_ROWCYCDLY0_bm (1<<3) /* SDRAM Row Cycle Delay bit 0 mask. */ -#define EBI_ROWCYCDLY0_bp 3 /* SDRAM Row Cycle Delay bit 0 position. */ -#define EBI_ROWCYCDLY1_bm (1<<4) /* SDRAM Row Cycle Delay bit 1 mask. */ -#define EBI_ROWCYCDLY1_bp 4 /* SDRAM Row Cycle Delay bit 1 position. */ -#define EBI_ROWCYCDLY2_bm (1<<5) /* SDRAM Row Cycle Delay bit 2 mask. */ -#define EBI_ROWCYCDLY2_bp 5 /* SDRAM Row Cycle Delay bit 2 position. */ - -#define EBI_RPDLY_gm 0x07 /* SDRAM Row-to-Precharge Delay group mask. */ -#define EBI_RPDLY_gp 0 /* SDRAM Row-to-Precharge Delay group position. */ -#define EBI_RPDLY0_bm (1<<0) /* SDRAM Row-to-Precharge Delay bit 0 mask. */ -#define EBI_RPDLY0_bp 0 /* SDRAM Row-to-Precharge Delay bit 0 position. */ -#define EBI_RPDLY1_bm (1<<1) /* SDRAM Row-to-Precharge Delay bit 1 mask. */ -#define EBI_RPDLY1_bp 1 /* SDRAM Row-to-Precharge Delay bit 1 position. */ -#define EBI_RPDLY2_bm (1<<2) /* SDRAM Row-to-Precharge Delay bit 2 mask. */ -#define EBI_RPDLY2_bp 2 /* SDRAM Row-to-Precharge Delay bit 2 position. */ - - -/* EBI.SDRAMCTRLC bit masks and bit positions */ -#define EBI_WRDLY_gm 0xC0 /* SDRAM Write Recovery Delay group mask. */ -#define EBI_WRDLY_gp 6 /* SDRAM Write Recovery Delay group position. */ -#define EBI_WRDLY0_bm (1<<6) /* SDRAM Write Recovery Delay bit 0 mask. */ -#define EBI_WRDLY0_bp 6 /* SDRAM Write Recovery Delay bit 0 position. */ -#define EBI_WRDLY1_bm (1<<7) /* SDRAM Write Recovery Delay bit 1 mask. */ -#define EBI_WRDLY1_bp 7 /* SDRAM Write Recovery Delay bit 1 position. */ - -#define EBI_ESRDLY_gm 0x38 /* SDRAM Exit-Self-refresh-to-Active Delay group mask. */ -#define EBI_ESRDLY_gp 3 /* SDRAM Exit-Self-refresh-to-Active Delay group position. */ -#define EBI_ESRDLY0_bm (1<<3) /* SDRAM Exit-Self-refresh-to-Active Delay bit 0 mask. */ -#define EBI_ESRDLY0_bp 3 /* SDRAM Exit-Self-refresh-to-Active Delay bit 0 position. */ -#define EBI_ESRDLY1_bm (1<<4) /* SDRAM Exit-Self-refresh-to-Active Delay bit 1 mask. */ -#define EBI_ESRDLY1_bp 4 /* SDRAM Exit-Self-refresh-to-Active Delay bit 1 position. */ -#define EBI_ESRDLY2_bm (1<<5) /* SDRAM Exit-Self-refresh-to-Active Delay bit 2 mask. */ -#define EBI_ESRDLY2_bp 5 /* SDRAM Exit-Self-refresh-to-Active Delay bit 2 position. */ - -#define EBI_ROWCOLDLY_gm 0x07 /* SDRAM Row-to-Column Delay group mask. */ -#define EBI_ROWCOLDLY_gp 0 /* SDRAM Row-to-Column Delay group position. */ -#define EBI_ROWCOLDLY0_bm (1<<0) /* SDRAM Row-to-Column Delay bit 0 mask. */ -#define EBI_ROWCOLDLY0_bp 0 /* SDRAM Row-to-Column Delay bit 0 position. */ -#define EBI_ROWCOLDLY1_bm (1<<1) /* SDRAM Row-to-Column Delay bit 1 mask. */ -#define EBI_ROWCOLDLY1_bp 1 /* SDRAM Row-to-Column Delay bit 1 position. */ -#define EBI_ROWCOLDLY2_bm (1<<2) /* SDRAM Row-to-Column Delay bit 2 mask. */ -#define EBI_ROWCOLDLY2_bp 2 /* SDRAM Row-to-Column Delay bit 2 position. */ - - -/* TWI - Two-Wire Interface */ -/* TWI_MASTER.CTRLA bit masks and bit positions */ -#define TWI_MASTER_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ -#define TWI_MASTER_INTLVL_gp 6 /* Interrupt Level group position. */ -#define TWI_MASTER_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ -#define TWI_MASTER_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ -#define TWI_MASTER_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ -#define TWI_MASTER_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ - -#define TWI_MASTER_RIEN_bm 0x20 /* Read Interrupt Enable bit mask. */ -#define TWI_MASTER_RIEN_bp 5 /* Read Interrupt Enable bit position. */ - -#define TWI_MASTER_WIEN_bm 0x10 /* Write Interrupt Enable bit mask. */ -#define TWI_MASTER_WIEN_bp 4 /* Write Interrupt Enable bit position. */ - -#define TWI_MASTER_ENABLE_bm 0x08 /* Enable TWI Master bit mask. */ -#define TWI_MASTER_ENABLE_bp 3 /* Enable TWI Master bit position. */ - - -/* TWI_MASTER.CTRLB bit masks and bit positions */ -#define TWI_MASTER_TIMEOUT_gm 0x0C /* Inactive Bus Timeout group mask. */ -#define TWI_MASTER_TIMEOUT_gp 2 /* Inactive Bus Timeout group position. */ -#define TWI_MASTER_TIMEOUT0_bm (1<<2) /* Inactive Bus Timeout bit 0 mask. */ -#define TWI_MASTER_TIMEOUT0_bp 2 /* Inactive Bus Timeout bit 0 position. */ -#define TWI_MASTER_TIMEOUT1_bm (1<<3) /* Inactive Bus Timeout bit 1 mask. */ -#define TWI_MASTER_TIMEOUT1_bp 3 /* Inactive Bus Timeout bit 1 position. */ - -#define TWI_MASTER_QCEN_bm 0x02 /* Quick Command Enable bit mask. */ -#define TWI_MASTER_QCEN_bp 1 /* Quick Command Enable bit position. */ - -#define TWI_MASTER_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ -#define TWI_MASTER_SMEN_bp 0 /* Smart Mode Enable bit position. */ - - -/* TWI_MASTER.CTRLC bit masks and bit positions */ -#define TWI_MASTER_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ -#define TWI_MASTER_ACKACT_bp 2 /* Acknowledge Action bit position. */ - -#define TWI_MASTER_CMD_gm 0x03 /* Command group mask. */ -#define TWI_MASTER_CMD_gp 0 /* Command group position. */ -#define TWI_MASTER_CMD0_bm (1<<0) /* Command bit 0 mask. */ -#define TWI_MASTER_CMD0_bp 0 /* Command bit 0 position. */ -#define TWI_MASTER_CMD1_bm (1<<1) /* Command bit 1 mask. */ -#define TWI_MASTER_CMD1_bp 1 /* Command bit 1 position. */ - - -/* TWI_MASTER.STATUS bit masks and bit positions */ -#define TWI_MASTER_RIF_bm 0x80 /* Read Interrupt Flag bit mask. */ -#define TWI_MASTER_RIF_bp 7 /* Read Interrupt Flag bit position. */ - -#define TWI_MASTER_WIF_bm 0x40 /* Write Interrupt Flag bit mask. */ -#define TWI_MASTER_WIF_bp 6 /* Write Interrupt Flag bit position. */ - -#define TWI_MASTER_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ -#define TWI_MASTER_CLKHOLD_bp 5 /* Clock Hold bit position. */ - -#define TWI_MASTER_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ -#define TWI_MASTER_RXACK_bp 4 /* Received Acknowledge bit position. */ - -#define TWI_MASTER_ARBLOST_bm 0x08 /* Arbitration Lost bit mask. */ -#define TWI_MASTER_ARBLOST_bp 3 /* Arbitration Lost bit position. */ - -#define TWI_MASTER_BUSERR_bm 0x04 /* Bus Error bit mask. */ -#define TWI_MASTER_BUSERR_bp 2 /* Bus Error bit position. */ - -#define TWI_MASTER_BUSSTATE_gm 0x03 /* Bus State group mask. */ -#define TWI_MASTER_BUSSTATE_gp 0 /* Bus State group position. */ -#define TWI_MASTER_BUSSTATE0_bm (1<<0) /* Bus State bit 0 mask. */ -#define TWI_MASTER_BUSSTATE0_bp 0 /* Bus State bit 0 position. */ -#define TWI_MASTER_BUSSTATE1_bm (1<<1) /* Bus State bit 1 mask. */ -#define TWI_MASTER_BUSSTATE1_bp 1 /* Bus State bit 1 position. */ - - -/* TWI_SLAVE.CTRLA bit masks and bit positions */ -#define TWI_SLAVE_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ -#define TWI_SLAVE_INTLVL_gp 6 /* Interrupt Level group position. */ -#define TWI_SLAVE_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ -#define TWI_SLAVE_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ -#define TWI_SLAVE_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ -#define TWI_SLAVE_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ - -#define TWI_SLAVE_DIEN_bm 0x20 /* Data Interrupt Enable bit mask. */ -#define TWI_SLAVE_DIEN_bp 5 /* Data Interrupt Enable bit position. */ - -#define TWI_SLAVE_APIEN_bm 0x10 /* Address/Stop Interrupt Enable bit mask. */ -#define TWI_SLAVE_APIEN_bp 4 /* Address/Stop Interrupt Enable bit position. */ - -#define TWI_SLAVE_ENABLE_bm 0x08 /* Enable TWI Slave bit mask. */ -#define TWI_SLAVE_ENABLE_bp 3 /* Enable TWI Slave bit position. */ - -#define TWI_SLAVE_PIEN_bm 0x04 /* Stop Interrupt Enable bit mask. */ -#define TWI_SLAVE_PIEN_bp 2 /* Stop Interrupt Enable bit position. */ - -#define TWI_SLAVE_PMEN_bm 0x02 /* Promiscuous Mode Enable bit mask. */ -#define TWI_SLAVE_PMEN_bp 1 /* Promiscuous Mode Enable bit position. */ - -#define TWI_SLAVE_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ -#define TWI_SLAVE_SMEN_bp 0 /* Smart Mode Enable bit position. */ - - -/* TWI_SLAVE.CTRLB bit masks and bit positions */ -#define TWI_SLAVE_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ -#define TWI_SLAVE_ACKACT_bp 2 /* Acknowledge Action bit position. */ - -#define TWI_SLAVE_CMD_gm 0x03 /* Command group mask. */ -#define TWI_SLAVE_CMD_gp 0 /* Command group position. */ -#define TWI_SLAVE_CMD0_bm (1<<0) /* Command bit 0 mask. */ -#define TWI_SLAVE_CMD0_bp 0 /* Command bit 0 position. */ -#define TWI_SLAVE_CMD1_bm (1<<1) /* Command bit 1 mask. */ -#define TWI_SLAVE_CMD1_bp 1 /* Command bit 1 position. */ - - -/* TWI_SLAVE.STATUS bit masks and bit positions */ -#define TWI_SLAVE_DIF_bm 0x80 /* Data Interrupt Flag bit mask. */ -#define TWI_SLAVE_DIF_bp 7 /* Data Interrupt Flag bit position. */ - -#define TWI_SLAVE_APIF_bm 0x40 /* Address/Stop Interrupt Flag bit mask. */ -#define TWI_SLAVE_APIF_bp 6 /* Address/Stop Interrupt Flag bit position. */ - -#define TWI_SLAVE_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ -#define TWI_SLAVE_CLKHOLD_bp 5 /* Clock Hold bit position. */ - -#define TWI_SLAVE_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ -#define TWI_SLAVE_RXACK_bp 4 /* Received Acknowledge bit position. */ - -#define TWI_SLAVE_COLL_bm 0x08 /* Collision bit mask. */ -#define TWI_SLAVE_COLL_bp 3 /* Collision bit position. */ - -#define TWI_SLAVE_BUSERR_bm 0x04 /* Bus Error bit mask. */ -#define TWI_SLAVE_BUSERR_bp 2 /* Bus Error bit position. */ - -#define TWI_SLAVE_DIR_bm 0x02 /* Read/Write Direction bit mask. */ -#define TWI_SLAVE_DIR_bp 1 /* Read/Write Direction bit position. */ - -#define TWI_SLAVE_AP_bm 0x01 /* Slave Address or Stop bit mask. */ -#define TWI_SLAVE_AP_bp 0 /* Slave Address or Stop bit position. */ - - -/* TWI_SLAVE.ADDRMASK bit masks and bit positions */ -#define TWI_SLAVE_ADDRMASK_gm 0xFE /* Address Mask group mask. */ -#define TWI_SLAVE_ADDRMASK_gp 1 /* Address Mask group position. */ -#define TWI_SLAVE_ADDRMASK0_bm (1<<1) /* Address Mask bit 0 mask. */ -#define TWI_SLAVE_ADDRMASK0_bp 1 /* Address Mask bit 0 position. */ -#define TWI_SLAVE_ADDRMASK1_bm (1<<2) /* Address Mask bit 1 mask. */ -#define TWI_SLAVE_ADDRMASK1_bp 2 /* Address Mask bit 1 position. */ -#define TWI_SLAVE_ADDRMASK2_bm (1<<3) /* Address Mask bit 2 mask. */ -#define TWI_SLAVE_ADDRMASK2_bp 3 /* Address Mask bit 2 position. */ -#define TWI_SLAVE_ADDRMASK3_bm (1<<4) /* Address Mask bit 3 mask. */ -#define TWI_SLAVE_ADDRMASK3_bp 4 /* Address Mask bit 3 position. */ -#define TWI_SLAVE_ADDRMASK4_bm (1<<5) /* Address Mask bit 4 mask. */ -#define TWI_SLAVE_ADDRMASK4_bp 5 /* Address Mask bit 4 position. */ -#define TWI_SLAVE_ADDRMASK5_bm (1<<6) /* Address Mask bit 5 mask. */ -#define TWI_SLAVE_ADDRMASK5_bp 6 /* Address Mask bit 5 position. */ -#define TWI_SLAVE_ADDRMASK6_bm (1<<7) /* Address Mask bit 6 mask. */ -#define TWI_SLAVE_ADDRMASK6_bp 7 /* Address Mask bit 6 position. */ - -#define TWI_SLAVE_ADDREN_bm 0x01 /* Address Enable bit mask. */ -#define TWI_SLAVE_ADDREN_bp 0 /* Address Enable bit position. */ - - -/* TWI.CTRL bit masks and bit positions */ -#define TWI_SDAHOLD_bm 0x02 /* SDA Hold Time Enable bit mask. */ -#define TWI_SDAHOLD_bp 1 /* SDA Hold Time Enable bit position. */ - -#define TWI_EDIEN_bm 0x01 /* External Driver Interface Enable bit mask. */ -#define TWI_EDIEN_bp 0 /* External Driver Interface Enable bit position. */ - - -/* PORT - Port Configuration */ -/* PORTCFG.VPCTRLA bit masks and bit positions */ -#define PORTCFG_VP1MAP_gm 0xF0 /* Virtual Port 1 Mapping group mask. */ -#define PORTCFG_VP1MAP_gp 4 /* Virtual Port 1 Mapping group position. */ -#define PORTCFG_VP1MAP0_bm (1<<4) /* Virtual Port 1 Mapping bit 0 mask. */ -#define PORTCFG_VP1MAP0_bp 4 /* Virtual Port 1 Mapping bit 0 position. */ -#define PORTCFG_VP1MAP1_bm (1<<5) /* Virtual Port 1 Mapping bit 1 mask. */ -#define PORTCFG_VP1MAP1_bp 5 /* Virtual Port 1 Mapping bit 1 position. */ -#define PORTCFG_VP1MAP2_bm (1<<6) /* Virtual Port 1 Mapping bit 2 mask. */ -#define PORTCFG_VP1MAP2_bp 6 /* Virtual Port 1 Mapping bit 2 position. */ -#define PORTCFG_VP1MAP3_bm (1<<7) /* Virtual Port 1 Mapping bit 3 mask. */ -#define PORTCFG_VP1MAP3_bp 7 /* Virtual Port 1 Mapping bit 3 position. */ - -#define PORTCFG_VP0MAP_gm 0x0F /* Virtual Port 0 Mapping group mask. */ -#define PORTCFG_VP0MAP_gp 0 /* Virtual Port 0 Mapping group position. */ -#define PORTCFG_VP0MAP0_bm (1<<0) /* Virtual Port 0 Mapping bit 0 mask. */ -#define PORTCFG_VP0MAP0_bp 0 /* Virtual Port 0 Mapping bit 0 position. */ -#define PORTCFG_VP0MAP1_bm (1<<1) /* Virtual Port 0 Mapping bit 1 mask. */ -#define PORTCFG_VP0MAP1_bp 1 /* Virtual Port 0 Mapping bit 1 position. */ -#define PORTCFG_VP0MAP2_bm (1<<2) /* Virtual Port 0 Mapping bit 2 mask. */ -#define PORTCFG_VP0MAP2_bp 2 /* Virtual Port 0 Mapping bit 2 position. */ -#define PORTCFG_VP0MAP3_bm (1<<3) /* Virtual Port 0 Mapping bit 3 mask. */ -#define PORTCFG_VP0MAP3_bp 3 /* Virtual Port 0 Mapping bit 3 position. */ - - -/* PORTCFG.VPCTRLB bit masks and bit positions */ -#define PORTCFG_VP3MAP_gm 0xF0 /* Virtual Port 3 Mapping group mask. */ -#define PORTCFG_VP3MAP_gp 4 /* Virtual Port 3 Mapping group position. */ -#define PORTCFG_VP3MAP0_bm (1<<4) /* Virtual Port 3 Mapping bit 0 mask. */ -#define PORTCFG_VP3MAP0_bp 4 /* Virtual Port 3 Mapping bit 0 position. */ -#define PORTCFG_VP3MAP1_bm (1<<5) /* Virtual Port 3 Mapping bit 1 mask. */ -#define PORTCFG_VP3MAP1_bp 5 /* Virtual Port 3 Mapping bit 1 position. */ -#define PORTCFG_VP3MAP2_bm (1<<6) /* Virtual Port 3 Mapping bit 2 mask. */ -#define PORTCFG_VP3MAP2_bp 6 /* Virtual Port 3 Mapping bit 2 position. */ -#define PORTCFG_VP3MAP3_bm (1<<7) /* Virtual Port 3 Mapping bit 3 mask. */ -#define PORTCFG_VP3MAP3_bp 7 /* Virtual Port 3 Mapping bit 3 position. */ - -#define PORTCFG_VP2MAP_gm 0x0F /* Virtual Port 2 Mapping group mask. */ -#define PORTCFG_VP2MAP_gp 0 /* Virtual Port 2 Mapping group position. */ -#define PORTCFG_VP2MAP0_bm (1<<0) /* Virtual Port 2 Mapping bit 0 mask. */ -#define PORTCFG_VP2MAP0_bp 0 /* Virtual Port 2 Mapping bit 0 position. */ -#define PORTCFG_VP2MAP1_bm (1<<1) /* Virtual Port 2 Mapping bit 1 mask. */ -#define PORTCFG_VP2MAP1_bp 1 /* Virtual Port 2 Mapping bit 1 position. */ -#define PORTCFG_VP2MAP2_bm (1<<2) /* Virtual Port 2 Mapping bit 2 mask. */ -#define PORTCFG_VP2MAP2_bp 2 /* Virtual Port 2 Mapping bit 2 position. */ -#define PORTCFG_VP2MAP3_bm (1<<3) /* Virtual Port 2 Mapping bit 3 mask. */ -#define PORTCFG_VP2MAP3_bp 3 /* Virtual Port 2 Mapping bit 3 position. */ - - -/* PORTCFG.CLKEVOUT bit masks and bit positions */ -#define PORTCFG_CLKOUT_gm 0x03 /* Clock Output Port group mask. */ -#define PORTCFG_CLKOUT_gp 0 /* Clock Output Port group position. */ -#define PORTCFG_CLKOUT0_bm (1<<0) /* Clock Output Port bit 0 mask. */ -#define PORTCFG_CLKOUT0_bp 0 /* Clock Output Port bit 0 position. */ -#define PORTCFG_CLKOUT1_bm (1<<1) /* Clock Output Port bit 1 mask. */ -#define PORTCFG_CLKOUT1_bp 1 /* Clock Output Port bit 1 position. */ - -#define PORTCFG_EVOUT_gm 0x30 /* Event Output Port group mask. */ -#define PORTCFG_EVOUT_gp 4 /* Event Output Port group position. */ -#define PORTCFG_EVOUT0_bm (1<<4) /* Event Output Port bit 0 mask. */ -#define PORTCFG_EVOUT0_bp 4 /* Event Output Port bit 0 position. */ -#define PORTCFG_EVOUT1_bm (1<<5) /* Event Output Port bit 1 mask. */ -#define PORTCFG_EVOUT1_bp 5 /* Event Output Port bit 1 position. */ - - -/* VPORT.INTFLAGS bit masks and bit positions */ -#define VPORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ -#define VPORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ - -#define VPORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ -#define VPORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ - - -/* PORT.INTCTRL bit masks and bit positions */ -#define PORT_INT1LVL_gm 0x0C /* Port Interrupt 1 Level group mask. */ -#define PORT_INT1LVL_gp 2 /* Port Interrupt 1 Level group position. */ -#define PORT_INT1LVL0_bm (1<<2) /* Port Interrupt 1 Level bit 0 mask. */ -#define PORT_INT1LVL0_bp 2 /* Port Interrupt 1 Level bit 0 position. */ -#define PORT_INT1LVL1_bm (1<<3) /* Port Interrupt 1 Level bit 1 mask. */ -#define PORT_INT1LVL1_bp 3 /* Port Interrupt 1 Level bit 1 position. */ - -#define PORT_INT0LVL_gm 0x03 /* Port Interrupt 0 Level group mask. */ -#define PORT_INT0LVL_gp 0 /* Port Interrupt 0 Level group position. */ -#define PORT_INT0LVL0_bm (1<<0) /* Port Interrupt 0 Level bit 0 mask. */ -#define PORT_INT0LVL0_bp 0 /* Port Interrupt 0 Level bit 0 position. */ -#define PORT_INT0LVL1_bm (1<<1) /* Port Interrupt 0 Level bit 1 mask. */ -#define PORT_INT0LVL1_bp 1 /* Port Interrupt 0 Level bit 1 position. */ - - -/* PORT.INTFLAGS bit masks and bit positions */ -#define PORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ -#define PORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ - -#define PORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ -#define PORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ - - -/* PORT.PIN0CTRL bit masks and bit positions */ -#define PORT_SRLEN_bm 0x80 /* Slew Rate Enable bit mask. */ -#define PORT_SRLEN_bp 7 /* Slew Rate Enable bit position. */ - -#define PORT_INVEN_bm 0x40 /* Inverted I/O Enable bit mask. */ -#define PORT_INVEN_bp 6 /* Inverted I/O Enable bit position. */ - -#define PORT_OPC_gm 0x38 /* Output/Pull Configuration group mask. */ -#define PORT_OPC_gp 3 /* Output/Pull Configuration group position. */ -#define PORT_OPC0_bm (1<<3) /* Output/Pull Configuration bit 0 mask. */ -#define PORT_OPC0_bp 3 /* Output/Pull Configuration bit 0 position. */ -#define PORT_OPC1_bm (1<<4) /* Output/Pull Configuration bit 1 mask. */ -#define PORT_OPC1_bp 4 /* Output/Pull Configuration bit 1 position. */ -#define PORT_OPC2_bm (1<<5) /* Output/Pull Configuration bit 2 mask. */ -#define PORT_OPC2_bp 5 /* Output/Pull Configuration bit 2 position. */ - -#define PORT_ISC_gm 0x07 /* Input/Sense Configuration group mask. */ -#define PORT_ISC_gp 0 /* Input/Sense Configuration group position. */ -#define PORT_ISC0_bm (1<<0) /* Input/Sense Configuration bit 0 mask. */ -#define PORT_ISC0_bp 0 /* Input/Sense Configuration bit 0 position. */ -#define PORT_ISC1_bm (1<<1) /* Input/Sense Configuration bit 1 mask. */ -#define PORT_ISC1_bp 1 /* Input/Sense Configuration bit 1 position. */ -#define PORT_ISC2_bm (1<<2) /* Input/Sense Configuration bit 2 mask. */ -#define PORT_ISC2_bp 2 /* Input/Sense Configuration bit 2 position. */ - - -/* PORT.PIN1CTRL bit masks and bit positions */ -/* PORT_SRLEN_bm Predefined. */ -/* PORT_SRLEN_bp Predefined. */ - -/* PORT_INVEN_bm Predefined. */ -/* PORT_INVEN_bp Predefined. */ - -/* PORT_OPC_gm Predefined. */ -/* PORT_OPC_gp Predefined. */ -/* PORT_OPC0_bm Predefined. */ -/* PORT_OPC0_bp Predefined. */ -/* PORT_OPC1_bm Predefined. */ -/* PORT_OPC1_bp Predefined. */ -/* PORT_OPC2_bm Predefined. */ -/* PORT_OPC2_bp Predefined. */ - -/* PORT_ISC_gm Predefined. */ -/* PORT_ISC_gp Predefined. */ -/* PORT_ISC0_bm Predefined. */ -/* PORT_ISC0_bp Predefined. */ -/* PORT_ISC1_bm Predefined. */ -/* PORT_ISC1_bp Predefined. */ -/* PORT_ISC2_bm Predefined. */ -/* PORT_ISC2_bp Predefined. */ - - -/* PORT.PIN2CTRL bit masks and bit positions */ -/* PORT_SRLEN_bm Predefined. */ -/* PORT_SRLEN_bp Predefined. */ - -/* PORT_INVEN_bm Predefined. */ -/* PORT_INVEN_bp Predefined. */ - -/* PORT_OPC_gm Predefined. */ -/* PORT_OPC_gp Predefined. */ -/* PORT_OPC0_bm Predefined. */ -/* PORT_OPC0_bp Predefined. */ -/* PORT_OPC1_bm Predefined. */ -/* PORT_OPC1_bp Predefined. */ -/* PORT_OPC2_bm Predefined. */ -/* PORT_OPC2_bp Predefined. */ - -/* PORT_ISC_gm Predefined. */ -/* PORT_ISC_gp Predefined. */ -/* PORT_ISC0_bm Predefined. */ -/* PORT_ISC0_bp Predefined. */ -/* PORT_ISC1_bm Predefined. */ -/* PORT_ISC1_bp Predefined. */ -/* PORT_ISC2_bm Predefined. */ -/* PORT_ISC2_bp Predefined. */ - - -/* PORT.PIN3CTRL bit masks and bit positions */ -/* PORT_SRLEN_bm Predefined. */ -/* PORT_SRLEN_bp Predefined. */ - -/* PORT_INVEN_bm Predefined. */ -/* PORT_INVEN_bp Predefined. */ - -/* PORT_OPC_gm Predefined. */ -/* PORT_OPC_gp Predefined. */ -/* PORT_OPC0_bm Predefined. */ -/* PORT_OPC0_bp Predefined. */ -/* PORT_OPC1_bm Predefined. */ -/* PORT_OPC1_bp Predefined. */ -/* PORT_OPC2_bm Predefined. */ -/* PORT_OPC2_bp Predefined. */ - -/* PORT_ISC_gm Predefined. */ -/* PORT_ISC_gp Predefined. */ -/* PORT_ISC0_bm Predefined. */ -/* PORT_ISC0_bp Predefined. */ -/* PORT_ISC1_bm Predefined. */ -/* PORT_ISC1_bp Predefined. */ -/* PORT_ISC2_bm Predefined. */ -/* PORT_ISC2_bp Predefined. */ - - -/* PORT.PIN4CTRL bit masks and bit positions */ -/* PORT_SRLEN_bm Predefined. */ -/* PORT_SRLEN_bp Predefined. */ - -/* PORT_INVEN_bm Predefined. */ -/* PORT_INVEN_bp Predefined. */ - -/* PORT_OPC_gm Predefined. */ -/* PORT_OPC_gp Predefined. */ -/* PORT_OPC0_bm Predefined. */ -/* PORT_OPC0_bp Predefined. */ -/* PORT_OPC1_bm Predefined. */ -/* PORT_OPC1_bp Predefined. */ -/* PORT_OPC2_bm Predefined. */ -/* PORT_OPC2_bp Predefined. */ - -/* PORT_ISC_gm Predefined. */ -/* PORT_ISC_gp Predefined. */ -/* PORT_ISC0_bm Predefined. */ -/* PORT_ISC0_bp Predefined. */ -/* PORT_ISC1_bm Predefined. */ -/* PORT_ISC1_bp Predefined. */ -/* PORT_ISC2_bm Predefined. */ -/* PORT_ISC2_bp Predefined. */ - - -/* PORT.PIN5CTRL bit masks and bit positions */ -/* PORT_SRLEN_bm Predefined. */ -/* PORT_SRLEN_bp Predefined. */ - -/* PORT_INVEN_bm Predefined. */ -/* PORT_INVEN_bp Predefined. */ - -/* PORT_OPC_gm Predefined. */ -/* PORT_OPC_gp Predefined. */ -/* PORT_OPC0_bm Predefined. */ -/* PORT_OPC0_bp Predefined. */ -/* PORT_OPC1_bm Predefined. */ -/* PORT_OPC1_bp Predefined. */ -/* PORT_OPC2_bm Predefined. */ -/* PORT_OPC2_bp Predefined. */ - -/* PORT_ISC_gm Predefined. */ -/* PORT_ISC_gp Predefined. */ -/* PORT_ISC0_bm Predefined. */ -/* PORT_ISC0_bp Predefined. */ -/* PORT_ISC1_bm Predefined. */ -/* PORT_ISC1_bp Predefined. */ -/* PORT_ISC2_bm Predefined. */ -/* PORT_ISC2_bp Predefined. */ - - -/* PORT.PIN6CTRL bit masks and bit positions */ -/* PORT_SRLEN_bm Predefined. */ -/* PORT_SRLEN_bp Predefined. */ - -/* PORT_INVEN_bm Predefined. */ -/* PORT_INVEN_bp Predefined. */ - -/* PORT_OPC_gm Predefined. */ -/* PORT_OPC_gp Predefined. */ -/* PORT_OPC0_bm Predefined. */ -/* PORT_OPC0_bp Predefined. */ -/* PORT_OPC1_bm Predefined. */ -/* PORT_OPC1_bp Predefined. */ -/* PORT_OPC2_bm Predefined. */ -/* PORT_OPC2_bp Predefined. */ - -/* PORT_ISC_gm Predefined. */ -/* PORT_ISC_gp Predefined. */ -/* PORT_ISC0_bm Predefined. */ -/* PORT_ISC0_bp Predefined. */ -/* PORT_ISC1_bm Predefined. */ -/* PORT_ISC1_bp Predefined. */ -/* PORT_ISC2_bm Predefined. */ -/* PORT_ISC2_bp Predefined. */ - - -/* PORT.PIN7CTRL bit masks and bit positions */ -/* PORT_SRLEN_bm Predefined. */ -/* PORT_SRLEN_bp Predefined. */ - -/* PORT_INVEN_bm Predefined. */ -/* PORT_INVEN_bp Predefined. */ - -/* PORT_OPC_gm Predefined. */ -/* PORT_OPC_gp Predefined. */ -/* PORT_OPC0_bm Predefined. */ -/* PORT_OPC0_bp Predefined. */ -/* PORT_OPC1_bm Predefined. */ -/* PORT_OPC1_bp Predefined. */ -/* PORT_OPC2_bm Predefined. */ -/* PORT_OPC2_bp Predefined. */ - -/* PORT_ISC_gm Predefined. */ -/* PORT_ISC_gp Predefined. */ -/* PORT_ISC0_bm Predefined. */ -/* PORT_ISC0_bp Predefined. */ -/* PORT_ISC1_bm Predefined. */ -/* PORT_ISC1_bp Predefined. */ -/* PORT_ISC2_bm Predefined. */ -/* PORT_ISC2_bp Predefined. */ - - -/* TC - 16-bit Timer/Counter With PWM */ -/* TC0.CTRLA bit masks and bit positions */ -#define TC0_CLKSEL_gm 0x0F /* Clock Selection group mask. */ -#define TC0_CLKSEL_gp 0 /* Clock Selection group position. */ -#define TC0_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ -#define TC0_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ -#define TC0_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ -#define TC0_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ -#define TC0_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ -#define TC0_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ -#define TC0_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ -#define TC0_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ - - -/* TC0.CTRLB bit masks and bit positions */ -#define TC0_CCDEN_bm 0x80 /* Compare or Capture D Enable bit mask. */ -#define TC0_CCDEN_bp 7 /* Compare or Capture D Enable bit position. */ - -#define TC0_CCCEN_bm 0x40 /* Compare or Capture C Enable bit mask. */ -#define TC0_CCCEN_bp 6 /* Compare or Capture C Enable bit position. */ - -#define TC0_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ -#define TC0_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ - -#define TC0_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ -#define TC0_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ - -#define TC0_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ -#define TC0_WGMODE_gp 0 /* Waveform generation mode group position. */ -#define TC0_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ -#define TC0_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ -#define TC0_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ -#define TC0_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ -#define TC0_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ -#define TC0_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ - - -/* TC0.CTRLC bit masks and bit positions */ -#define TC0_CMPD_bm 0x08 /* Compare D Output Value bit mask. */ -#define TC0_CMPD_bp 3 /* Compare D Output Value bit position. */ - -#define TC0_CMPC_bm 0x04 /* Compare C Output Value bit mask. */ -#define TC0_CMPC_bp 2 /* Compare C Output Value bit position. */ - -#define TC0_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ -#define TC0_CMPB_bp 1 /* Compare B Output Value bit position. */ - -#define TC0_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ -#define TC0_CMPA_bp 0 /* Compare A Output Value bit position. */ - - -/* TC0.CTRLD bit masks and bit positions */ -#define TC0_EVACT_gm 0xE0 /* Event Action group mask. */ -#define TC0_EVACT_gp 5 /* Event Action group position. */ -#define TC0_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ -#define TC0_EVACT0_bp 5 /* Event Action bit 0 position. */ -#define TC0_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ -#define TC0_EVACT1_bp 6 /* Event Action bit 1 position. */ -#define TC0_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ -#define TC0_EVACT2_bp 7 /* Event Action bit 2 position. */ - -#define TC0_EVDLY_bm 0x10 /* Event Delay bit mask. */ -#define TC0_EVDLY_bp 4 /* Event Delay bit position. */ - -#define TC0_EVSEL_gm 0x0F /* Event Source Select group mask. */ -#define TC0_EVSEL_gp 0 /* Event Source Select group position. */ -#define TC0_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ -#define TC0_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ -#define TC0_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ -#define TC0_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ -#define TC0_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ -#define TC0_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ -#define TC0_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ -#define TC0_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ - - -/* TC0.CTRLE bit masks and bit positions */ -#define TC0_BYTEM_bm 0x01 /* Byte Mode bit mask. */ -#define TC0_BYTEM_bp 0 /* Byte Mode bit position. */ - - -/* TC0.INTCTRLA bit masks and bit positions */ -#define TC0_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ -#define TC0_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ -#define TC0_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ -#define TC0_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ -#define TC0_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ -#define TC0_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ - -#define TC0_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ -#define TC0_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ -#define TC0_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ -#define TC0_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ -#define TC0_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ -#define TC0_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ - - -/* TC0.INTCTRLB bit masks and bit positions */ -#define TC0_CCDINTLVL_gm 0xC0 /* Compare or Capture D Interrupt Level group mask. */ -#define TC0_CCDINTLVL_gp 6 /* Compare or Capture D Interrupt Level group position. */ -#define TC0_CCDINTLVL0_bm (1<<6) /* Compare or Capture D Interrupt Level bit 0 mask. */ -#define TC0_CCDINTLVL0_bp 6 /* Compare or Capture D Interrupt Level bit 0 position. */ -#define TC0_CCDINTLVL1_bm (1<<7) /* Compare or Capture D Interrupt Level bit 1 mask. */ -#define TC0_CCDINTLVL1_bp 7 /* Compare or Capture D Interrupt Level bit 1 position. */ - -#define TC0_CCCINTLVL_gm 0x30 /* Compare or Capture C Interrupt Level group mask. */ -#define TC0_CCCINTLVL_gp 4 /* Compare or Capture C Interrupt Level group position. */ -#define TC0_CCCINTLVL0_bm (1<<4) /* Compare or Capture C Interrupt Level bit 0 mask. */ -#define TC0_CCCINTLVL0_bp 4 /* Compare or Capture C Interrupt Level bit 0 position. */ -#define TC0_CCCINTLVL1_bm (1<<5) /* Compare or Capture C Interrupt Level bit 1 mask. */ -#define TC0_CCCINTLVL1_bp 5 /* Compare or Capture C Interrupt Level bit 1 position. */ - -#define TC0_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ -#define TC0_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ -#define TC0_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ -#define TC0_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ -#define TC0_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ -#define TC0_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ - -#define TC0_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ -#define TC0_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ -#define TC0_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ -#define TC0_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ -#define TC0_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ -#define TC0_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ - - -/* TC0.CTRLFCLR bit masks and bit positions */ -#define TC0_CMD_gm 0x0C /* Command group mask. */ -#define TC0_CMD_gp 2 /* Command group position. */ -#define TC0_CMD0_bm (1<<2) /* Command bit 0 mask. */ -#define TC0_CMD0_bp 2 /* Command bit 0 position. */ -#define TC0_CMD1_bm (1<<3) /* Command bit 1 mask. */ -#define TC0_CMD1_bp 3 /* Command bit 1 position. */ - -#define TC0_LUPD_bm 0x02 /* Lock Update bit mask. */ -#define TC0_LUPD_bp 1 /* Lock Update bit position. */ - -#define TC0_DIR_bm 0x01 /* Direction bit mask. */ -#define TC0_DIR_bp 0 /* Direction bit position. */ - - -/* TC0.CTRLFSET bit masks and bit positions */ -/* TC0_CMD_gm Predefined. */ -/* TC0_CMD_gp Predefined. */ -/* TC0_CMD0_bm Predefined. */ -/* TC0_CMD0_bp Predefined. */ -/* TC0_CMD1_bm Predefined. */ -/* TC0_CMD1_bp Predefined. */ - -/* TC0_LUPD_bm Predefined. */ -/* TC0_LUPD_bp Predefined. */ - -/* TC0_DIR_bm Predefined. */ -/* TC0_DIR_bp Predefined. */ - - -/* TC0.CTRLGCLR bit masks and bit positions */ -#define TC0_CCDBV_bm 0x10 /* Compare or Capture D Buffer Valid bit mask. */ -#define TC0_CCDBV_bp 4 /* Compare or Capture D Buffer Valid bit position. */ - -#define TC0_CCCBV_bm 0x08 /* Compare or Capture C Buffer Valid bit mask. */ -#define TC0_CCCBV_bp 3 /* Compare or Capture C Buffer Valid bit position. */ - -#define TC0_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ -#define TC0_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ - -#define TC0_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ -#define TC0_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ - -#define TC0_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ -#define TC0_PERBV_bp 0 /* Period Buffer Valid bit position. */ - - -/* TC0.CTRLGSET bit masks and bit positions */ -/* TC0_CCDBV_bm Predefined. */ -/* TC0_CCDBV_bp Predefined. */ - -/* TC0_CCCBV_bm Predefined. */ -/* TC0_CCCBV_bp Predefined. */ - -/* TC0_CCBBV_bm Predefined. */ -/* TC0_CCBBV_bp Predefined. */ - -/* TC0_CCABV_bm Predefined. */ -/* TC0_CCABV_bp Predefined. */ - -/* TC0_PERBV_bm Predefined. */ -/* TC0_PERBV_bp Predefined. */ - - -/* TC0.INTFLAGS bit masks and bit positions */ -#define TC0_CCDIF_bm 0x80 /* Compare or Capture D Interrupt Flag bit mask. */ -#define TC0_CCDIF_bp 7 /* Compare or Capture D Interrupt Flag bit position. */ - -#define TC0_CCCIF_bm 0x40 /* Compare or Capture C Interrupt Flag bit mask. */ -#define TC0_CCCIF_bp 6 /* Compare or Capture C Interrupt Flag bit position. */ - -#define TC0_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ -#define TC0_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ - -#define TC0_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ -#define TC0_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ - -#define TC0_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ -#define TC0_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ - -#define TC0_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ -#define TC0_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ - - -/* TC1.CTRLA bit masks and bit positions */ -#define TC1_CLKSEL_gm 0x0F /* Clock Selection group mask. */ -#define TC1_CLKSEL_gp 0 /* Clock Selection group position. */ -#define TC1_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ -#define TC1_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ -#define TC1_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ -#define TC1_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ -#define TC1_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ -#define TC1_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ -#define TC1_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ -#define TC1_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ - - -/* TC1.CTRLB bit masks and bit positions */ -#define TC1_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ -#define TC1_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ - -#define TC1_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ -#define TC1_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ - -#define TC1_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ -#define TC1_WGMODE_gp 0 /* Waveform generation mode group position. */ -#define TC1_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ -#define TC1_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ -#define TC1_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ -#define TC1_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ -#define TC1_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ -#define TC1_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ - - -/* TC1.CTRLC bit masks and bit positions */ -#define TC1_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ -#define TC1_CMPB_bp 1 /* Compare B Output Value bit position. */ - -#define TC1_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ -#define TC1_CMPA_bp 0 /* Compare A Output Value bit position. */ - - -/* TC1.CTRLD bit masks and bit positions */ -#define TC1_EVACT_gm 0xE0 /* Event Action group mask. */ -#define TC1_EVACT_gp 5 /* Event Action group position. */ -#define TC1_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ -#define TC1_EVACT0_bp 5 /* Event Action bit 0 position. */ -#define TC1_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ -#define TC1_EVACT1_bp 6 /* Event Action bit 1 position. */ -#define TC1_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ -#define TC1_EVACT2_bp 7 /* Event Action bit 2 position. */ - -#define TC1_EVDLY_bm 0x10 /* Event Delay bit mask. */ -#define TC1_EVDLY_bp 4 /* Event Delay bit position. */ - -#define TC1_EVSEL_gm 0x0F /* Event Source Select group mask. */ -#define TC1_EVSEL_gp 0 /* Event Source Select group position. */ -#define TC1_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ -#define TC1_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ -#define TC1_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ -#define TC1_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ -#define TC1_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ -#define TC1_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ -#define TC1_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ -#define TC1_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ - - -/* TC1.CTRLE bit masks and bit positions */ -#define TC1_BYTEM_bm 0x01 /* Byte Mode bit mask. */ -#define TC1_BYTEM_bp 0 /* Byte Mode bit position. */ - - -/* TC1.INTCTRLA bit masks and bit positions */ -#define TC1_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ -#define TC1_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ -#define TC1_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ -#define TC1_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ -#define TC1_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ -#define TC1_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ - -#define TC1_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ -#define TC1_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ -#define TC1_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ -#define TC1_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ -#define TC1_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ -#define TC1_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ - - -/* TC1.INTCTRLB bit masks and bit positions */ -#define TC1_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ -#define TC1_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ -#define TC1_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ -#define TC1_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ -#define TC1_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ -#define TC1_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ - -#define TC1_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ -#define TC1_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ -#define TC1_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ -#define TC1_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ -#define TC1_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ -#define TC1_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ - - -/* TC1.CTRLFCLR bit masks and bit positions */ -#define TC1_CMD_gm 0x0C /* Command group mask. */ -#define TC1_CMD_gp 2 /* Command group position. */ -#define TC1_CMD0_bm (1<<2) /* Command bit 0 mask. */ -#define TC1_CMD0_bp 2 /* Command bit 0 position. */ -#define TC1_CMD1_bm (1<<3) /* Command bit 1 mask. */ -#define TC1_CMD1_bp 3 /* Command bit 1 position. */ - -#define TC1_LUPD_bm 0x02 /* Lock Update bit mask. */ -#define TC1_LUPD_bp 1 /* Lock Update bit position. */ - -#define TC1_DIR_bm 0x01 /* Direction bit mask. */ -#define TC1_DIR_bp 0 /* Direction bit position. */ - - -/* TC1.CTRLFSET bit masks and bit positions */ -/* TC1_CMD_gm Predefined. */ -/* TC1_CMD_gp Predefined. */ -/* TC1_CMD0_bm Predefined. */ -/* TC1_CMD0_bp Predefined. */ -/* TC1_CMD1_bm Predefined. */ -/* TC1_CMD1_bp Predefined. */ - -/* TC1_LUPD_bm Predefined. */ -/* TC1_LUPD_bp Predefined. */ - -/* TC1_DIR_bm Predefined. */ -/* TC1_DIR_bp Predefined. */ - - -/* TC1.CTRLGCLR bit masks and bit positions */ -#define TC1_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ -#define TC1_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ - -#define TC1_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ -#define TC1_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ - -#define TC1_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ -#define TC1_PERBV_bp 0 /* Period Buffer Valid bit position. */ - - -/* TC1.CTRLGSET bit masks and bit positions */ -/* TC1_CCBBV_bm Predefined. */ -/* TC1_CCBBV_bp Predefined. */ - -/* TC1_CCABV_bm Predefined. */ -/* TC1_CCABV_bp Predefined. */ - -/* TC1_PERBV_bm Predefined. */ -/* TC1_PERBV_bp Predefined. */ - - -/* TC1.INTFLAGS bit masks and bit positions */ -#define TC1_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ -#define TC1_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ - -#define TC1_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ -#define TC1_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ - -#define TC1_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ -#define TC1_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ - -#define TC1_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ -#define TC1_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ - - -/* AWEX.CTRL bit masks and bit positions */ -#define AWEX_PGM_bm 0x20 /* Pattern Generation Mode bit mask. */ -#define AWEX_PGM_bp 5 /* Pattern Generation Mode bit position. */ - -#define AWEX_CWCM_bm 0x10 /* Common Waveform Channel Mode bit mask. */ -#define AWEX_CWCM_bp 4 /* Common Waveform Channel Mode bit position. */ - -#define AWEX_DTICCDEN_bm 0x08 /* Dead Time Insertion Compare Channel D Enable bit mask. */ -#define AWEX_DTICCDEN_bp 3 /* Dead Time Insertion Compare Channel D Enable bit position. */ - -#define AWEX_DTICCCEN_bm 0x04 /* Dead Time Insertion Compare Channel C Enable bit mask. */ -#define AWEX_DTICCCEN_bp 2 /* Dead Time Insertion Compare Channel C Enable bit position. */ - -#define AWEX_DTICCBEN_bm 0x02 /* Dead Time Insertion Compare Channel B Enable bit mask. */ -#define AWEX_DTICCBEN_bp 1 /* Dead Time Insertion Compare Channel B Enable bit position. */ - -#define AWEX_DTICCAEN_bm 0x01 /* Dead Time Insertion Compare Channel A Enable bit mask. */ -#define AWEX_DTICCAEN_bp 0 /* Dead Time Insertion Compare Channel A Enable bit position. */ - - -/* AWEX.FDCTRL bit masks and bit positions */ -#define AWEX_FDDBD_bm 0x10 /* Fault Detect on Disable Break Disable bit mask. */ -#define AWEX_FDDBD_bp 4 /* Fault Detect on Disable Break Disable bit position. */ - -#define AWEX_FDMODE_bm 0x04 /* Fault Detect Mode bit mask. */ -#define AWEX_FDMODE_bp 2 /* Fault Detect Mode bit position. */ - -#define AWEX_FDACT_gm 0x03 /* Fault Detect Action group mask. */ -#define AWEX_FDACT_gp 0 /* Fault Detect Action group position. */ -#define AWEX_FDACT0_bm (1<<0) /* Fault Detect Action bit 0 mask. */ -#define AWEX_FDACT0_bp 0 /* Fault Detect Action bit 0 position. */ -#define AWEX_FDACT1_bm (1<<1) /* Fault Detect Action bit 1 mask. */ -#define AWEX_FDACT1_bp 1 /* Fault Detect Action bit 1 position. */ - - -/* AWEX.STATUS bit masks and bit positions */ -#define AWEX_FDF_bm 0x04 /* Fault Detect Flag bit mask. */ -#define AWEX_FDF_bp 2 /* Fault Detect Flag bit position. */ - -#define AWEX_DTHSBUFV_bm 0x02 /* Dead Time High Side Buffer Valid bit mask. */ -#define AWEX_DTHSBUFV_bp 1 /* Dead Time High Side Buffer Valid bit position. */ - -#define AWEX_DTLSBUFV_bm 0x01 /* Dead Time Low Side Buffer Valid bit mask. */ -#define AWEX_DTLSBUFV_bp 0 /* Dead Time Low Side Buffer Valid bit position. */ - - -/* HIRES.CTRLA bit masks and bit positions */ -#define HIRES_HREN_gm 0x03 /* High Resolution Enable group mask. */ -#define HIRES_HREN_gp 0 /* High Resolution Enable group position. */ -#define HIRES_HREN0_bm (1<<0) /* High Resolution Enable bit 0 mask. */ -#define HIRES_HREN0_bp 0 /* High Resolution Enable bit 0 position. */ -#define HIRES_HREN1_bm (1<<1) /* High Resolution Enable bit 1 mask. */ -#define HIRES_HREN1_bp 1 /* High Resolution Enable bit 1 position. */ - - -/* USART - Universal Asynchronous Receiver-Transmitter */ -/* USART.STATUS bit masks and bit positions */ -#define USART_RXCIF_bm 0x80 /* Receive Interrupt Flag bit mask. */ -#define USART_RXCIF_bp 7 /* Receive Interrupt Flag bit position. */ - -#define USART_TXCIF_bm 0x40 /* Transmit Interrupt Flag bit mask. */ -#define USART_TXCIF_bp 6 /* Transmit Interrupt Flag bit position. */ - -#define USART_DREIF_bm 0x20 /* Data Register Empty Flag bit mask. */ -#define USART_DREIF_bp 5 /* Data Register Empty Flag bit position. */ - -#define USART_FERR_bm 0x10 /* Frame Error bit mask. */ -#define USART_FERR_bp 4 /* Frame Error bit position. */ - -#define USART_BUFOVF_bm 0x08 /* Buffer Overflow bit mask. */ -#define USART_BUFOVF_bp 3 /* Buffer Overflow bit position. */ - -#define USART_PERR_bm 0x04 /* Parity Error bit mask. */ -#define USART_PERR_bp 2 /* Parity Error bit position. */ - -#define USART_RXB8_bm 0x01 /* Receive Bit 8 bit mask. */ -#define USART_RXB8_bp 0 /* Receive Bit 8 bit position. */ - - -/* USART.CTRLA bit masks and bit positions */ -#define USART_RXCINTLVL_gm 0x30 /* Receive Interrupt Level group mask. */ -#define USART_RXCINTLVL_gp 4 /* Receive Interrupt Level group position. */ -#define USART_RXCINTLVL0_bm (1<<4) /* Receive Interrupt Level bit 0 mask. */ -#define USART_RXCINTLVL0_bp 4 /* Receive Interrupt Level bit 0 position. */ -#define USART_RXCINTLVL1_bm (1<<5) /* Receive Interrupt Level bit 1 mask. */ -#define USART_RXCINTLVL1_bp 5 /* Receive Interrupt Level bit 1 position. */ - -#define USART_TXCINTLVL_gm 0x0C /* Transmit Interrupt Level group mask. */ -#define USART_TXCINTLVL_gp 2 /* Transmit Interrupt Level group position. */ -#define USART_TXCINTLVL0_bm (1<<2) /* Transmit Interrupt Level bit 0 mask. */ -#define USART_TXCINTLVL0_bp 2 /* Transmit Interrupt Level bit 0 position. */ -#define USART_TXCINTLVL1_bm (1<<3) /* Transmit Interrupt Level bit 1 mask. */ -#define USART_TXCINTLVL1_bp 3 /* Transmit Interrupt Level bit 1 position. */ - -#define USART_DREINTLVL_gm 0x03 /* Data Register Empty Interrupt Level group mask. */ -#define USART_DREINTLVL_gp 0 /* Data Register Empty Interrupt Level group position. */ -#define USART_DREINTLVL0_bm (1<<0) /* Data Register Empty Interrupt Level bit 0 mask. */ -#define USART_DREINTLVL0_bp 0 /* Data Register Empty Interrupt Level bit 0 position. */ -#define USART_DREINTLVL1_bm (1<<1) /* Data Register Empty Interrupt Level bit 1 mask. */ -#define USART_DREINTLVL1_bp 1 /* Data Register Empty Interrupt Level bit 1 position. */ - - -/* USART.CTRLB bit masks and bit positions */ -#define USART_RXEN_bm 0x10 /* Receiver Enable bit mask. */ -#define USART_RXEN_bp 4 /* Receiver Enable bit position. */ - -#define USART_TXEN_bm 0x08 /* Transmitter Enable bit mask. */ -#define USART_TXEN_bp 3 /* Transmitter Enable bit position. */ - -#define USART_CLK2X_bm 0x04 /* Double transmission speed bit mask. */ -#define USART_CLK2X_bp 2 /* Double transmission speed bit position. */ - -#define USART_MPCM_bm 0x02 /* Multi-processor Communication Mode bit mask. */ -#define USART_MPCM_bp 1 /* Multi-processor Communication Mode bit position. */ - -#define USART_TXB8_bm 0x01 /* Transmit bit 8 bit mask. */ -#define USART_TXB8_bp 0 /* Transmit bit 8 bit position. */ - - -/* USART.CTRLC bit masks and bit positions */ -#define USART_CMODE_gm 0xC0 /* Communication Mode group mask. */ -#define USART_CMODE_gp 6 /* Communication Mode group position. */ -#define USART_CMODE0_bm (1<<6) /* Communication Mode bit 0 mask. */ -#define USART_CMODE0_bp 6 /* Communication Mode bit 0 position. */ -#define USART_CMODE1_bm (1<<7) /* Communication Mode bit 1 mask. */ -#define USART_CMODE1_bp 7 /* Communication Mode bit 1 position. */ - -#define USART_PMODE_gm 0x30 /* Parity Mode group mask. */ -#define USART_PMODE_gp 4 /* Parity Mode group position. */ -#define USART_PMODE0_bm (1<<4) /* Parity Mode bit 0 mask. */ -#define USART_PMODE0_bp 4 /* Parity Mode bit 0 position. */ -#define USART_PMODE1_bm (1<<5) /* Parity Mode bit 1 mask. */ -#define USART_PMODE1_bp 5 /* Parity Mode bit 1 position. */ - -#define USART_SBMODE_bm 0x08 /* Stop Bit Mode bit mask. */ -#define USART_SBMODE_bp 3 /* Stop Bit Mode bit position. */ - -#define USART_CHSIZE_gm 0x07 /* Character Size group mask. */ -#define USART_CHSIZE_gp 0 /* Character Size group position. */ -#define USART_CHSIZE0_bm (1<<0) /* Character Size bit 0 mask. */ -#define USART_CHSIZE0_bp 0 /* Character Size bit 0 position. */ -#define USART_CHSIZE1_bm (1<<1) /* Character Size bit 1 mask. */ -#define USART_CHSIZE1_bp 1 /* Character Size bit 1 position. */ -#define USART_CHSIZE2_bm (1<<2) /* Character Size bit 2 mask. */ -#define USART_CHSIZE2_bp 2 /* Character Size bit 2 position. */ - - -/* USART.BAUDCTRLA bit masks and bit positions */ -#define USART_BSEL_gm 0xFF /* Baud Rate Selection Bits [7:0] group mask. */ -#define USART_BSEL_gp 0 /* Baud Rate Selection Bits [7:0] group position. */ -#define USART_BSEL0_bm (1<<0) /* Baud Rate Selection Bits [7:0] bit 0 mask. */ -#define USART_BSEL0_bp 0 /* Baud Rate Selection Bits [7:0] bit 0 position. */ -#define USART_BSEL1_bm (1<<1) /* Baud Rate Selection Bits [7:0] bit 1 mask. */ -#define USART_BSEL1_bp 1 /* Baud Rate Selection Bits [7:0] bit 1 position. */ -#define USART_BSEL2_bm (1<<2) /* Baud Rate Selection Bits [7:0] bit 2 mask. */ -#define USART_BSEL2_bp 2 /* Baud Rate Selection Bits [7:0] bit 2 position. */ -#define USART_BSEL3_bm (1<<3) /* Baud Rate Selection Bits [7:0] bit 3 mask. */ -#define USART_BSEL3_bp 3 /* Baud Rate Selection Bits [7:0] bit 3 position. */ -#define USART_BSEL4_bm (1<<4) /* Baud Rate Selection Bits [7:0] bit 4 mask. */ -#define USART_BSEL4_bp 4 /* Baud Rate Selection Bits [7:0] bit 4 position. */ -#define USART_BSEL5_bm (1<<5) /* Baud Rate Selection Bits [7:0] bit 5 mask. */ -#define USART_BSEL5_bp 5 /* Baud Rate Selection Bits [7:0] bit 5 position. */ -#define USART_BSEL6_bm (1<<6) /* Baud Rate Selection Bits [7:0] bit 6 mask. */ -#define USART_BSEL6_bp 6 /* Baud Rate Selection Bits [7:0] bit 6 position. */ -#define USART_BSEL7_bm (1<<7) /* Baud Rate Selection Bits [7:0] bit 7 mask. */ -#define USART_BSEL7_bp 7 /* Baud Rate Selection Bits [7:0] bit 7 position. */ - - -/* USART.BAUDCTRLB bit masks and bit positions */ -#define USART_BSCALE_gm 0xF0 /* Baud Rate Scale group mask. */ -#define USART_BSCALE_gp 4 /* Baud Rate Scale group position. */ -#define USART_BSCALE0_bm (1<<4) /* Baud Rate Scale bit 0 mask. */ -#define USART_BSCALE0_bp 4 /* Baud Rate Scale bit 0 position. */ -#define USART_BSCALE1_bm (1<<5) /* Baud Rate Scale bit 1 mask. */ -#define USART_BSCALE1_bp 5 /* Baud Rate Scale bit 1 position. */ -#define USART_BSCALE2_bm (1<<6) /* Baud Rate Scale bit 2 mask. */ -#define USART_BSCALE2_bp 6 /* Baud Rate Scale bit 2 position. */ -#define USART_BSCALE3_bm (1<<7) /* Baud Rate Scale bit 3 mask. */ -#define USART_BSCALE3_bp 7 /* Baud Rate Scale bit 3 position. */ - -/* USART_BSEL_gm Predefined. */ -/* USART_BSEL_gp Predefined. */ -/* USART_BSEL0_bm Predefined. */ -/* USART_BSEL0_bp Predefined. */ -/* USART_BSEL1_bm Predefined. */ -/* USART_BSEL1_bp Predefined. */ -/* USART_BSEL2_bm Predefined. */ -/* USART_BSEL2_bp Predefined. */ -/* USART_BSEL3_bm Predefined. */ -/* USART_BSEL3_bp Predefined. */ - - -/* SPI - Serial Peripheral Interface */ -/* SPI.CTRL bit masks and bit positions */ -#define SPI_CLK2X_bm 0x80 /* Enable Double Speed bit mask. */ -#define SPI_CLK2X_bp 7 /* Enable Double Speed bit position. */ - -#define SPI_ENABLE_bm 0x40 /* Enable Module bit mask. */ -#define SPI_ENABLE_bp 6 /* Enable Module bit position. */ - -#define SPI_DORD_bm 0x20 /* Data Order Setting bit mask. */ -#define SPI_DORD_bp 5 /* Data Order Setting bit position. */ - -#define SPI_MASTER_bm 0x10 /* Master Operation Enable bit mask. */ -#define SPI_MASTER_bp 4 /* Master Operation Enable bit position. */ - -#define SPI_MODE_gm 0x0C /* SPI Mode group mask. */ -#define SPI_MODE_gp 2 /* SPI Mode group position. */ -#define SPI_MODE0_bm (1<<2) /* SPI Mode bit 0 mask. */ -#define SPI_MODE0_bp 2 /* SPI Mode bit 0 position. */ -#define SPI_MODE1_bm (1<<3) /* SPI Mode bit 1 mask. */ -#define SPI_MODE1_bp 3 /* SPI Mode bit 1 position. */ - -#define SPI_PRESCALER_gm 0x03 /* Prescaler group mask. */ -#define SPI_PRESCALER_gp 0 /* Prescaler group position. */ -#define SPI_PRESCALER0_bm (1<<0) /* Prescaler bit 0 mask. */ -#define SPI_PRESCALER0_bp 0 /* Prescaler bit 0 position. */ -#define SPI_PRESCALER1_bm (1<<1) /* Prescaler bit 1 mask. */ -#define SPI_PRESCALER1_bp 1 /* Prescaler bit 1 position. */ - - -/* SPI.INTCTRL bit masks and bit positions */ -#define SPI_INTLVL_gm 0x03 /* Interrupt level group mask. */ -#define SPI_INTLVL_gp 0 /* Interrupt level group position. */ -#define SPI_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */ -#define SPI_INTLVL0_bp 0 /* Interrupt level bit 0 position. */ -#define SPI_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */ -#define SPI_INTLVL1_bp 1 /* Interrupt level bit 1 position. */ - - -/* SPI.STATUS bit masks and bit positions */ -#define SPI_IF_bm 0x80 /* Interrupt Flag bit mask. */ -#define SPI_IF_bp 7 /* Interrupt Flag bit position. */ - -#define SPI_WRCOL_bm 0x40 /* Write Collision bit mask. */ -#define SPI_WRCOL_bp 6 /* Write Collision bit position. */ - - -/* IRCOM - IR Communication Module */ -/* IRCOM.CTRL bit masks and bit positions */ -#define IRCOM_EVSEL_gm 0x0F /* Event Channel Select group mask. */ -#define IRCOM_EVSEL_gp 0 /* Event Channel Select group position. */ -#define IRCOM_EVSEL0_bm (1<<0) /* Event Channel Select bit 0 mask. */ -#define IRCOM_EVSEL0_bp 0 /* Event Channel Select bit 0 position. */ -#define IRCOM_EVSEL1_bm (1<<1) /* Event Channel Select bit 1 mask. */ -#define IRCOM_EVSEL1_bp 1 /* Event Channel Select bit 1 position. */ -#define IRCOM_EVSEL2_bm (1<<2) /* Event Channel Select bit 2 mask. */ -#define IRCOM_EVSEL2_bp 2 /* Event Channel Select bit 2 position. */ -#define IRCOM_EVSEL3_bm (1<<3) /* Event Channel Select bit 3 mask. */ -#define IRCOM_EVSEL3_bp 3 /* Event Channel Select bit 3 position. */ - - - -// Generic Port Pins - -#define PIN0_bm 0x01 -#define PIN0_bp 0 -#define PIN1_bm 0x02 -#define PIN1_bp 1 -#define PIN2_bm 0x04 -#define PIN2_bp 2 -#define PIN3_bm 0x08 -#define PIN3_bp 3 -#define PIN4_bm 0x10 -#define PIN4_bp 4 -#define PIN5_bm 0x20 -#define PIN5_bp 5 -#define PIN6_bm 0x40 -#define PIN6_bp 6 -#define PIN7_bm 0x80 -#define PIN7_bp 7 - - -/* ========== Interrupt Vector Definitions ========== */ -/* Vector 0 is the reset vector */ - -/* OSC interrupt vectors */ -#define OSC_XOSCF_vect_num 1 -#define OSC_XOSCF_vect _VECTOR(1) /* External Oscillator Failure Interrupt (NMI) */ - -/* PORTC interrupt vectors */ -#define PORTC_INT0_vect_num 2 -#define PORTC_INT0_vect _VECTOR(2) /* External Interrupt 0 */ -#define PORTC_INT1_vect_num 3 -#define PORTC_INT1_vect _VECTOR(3) /* External Interrupt 1 */ - -/* PORTR interrupt vectors */ -#define PORTR_INT0_vect_num 4 -#define PORTR_INT0_vect _VECTOR(4) /* External Interrupt 0 */ -#define PORTR_INT1_vect_num 5 -#define PORTR_INT1_vect _VECTOR(5) /* External Interrupt 1 */ - -/* RTC interrupt vectors */ -#define RTC_OVF_vect_num 10 -#define RTC_OVF_vect _VECTOR(10) /* Overflow Interrupt */ -#define RTC_COMP_vect_num 11 -#define RTC_COMP_vect _VECTOR(11) /* Compare Interrupt */ - -/* TWIC interrupt vectors */ -#define TWIC_TWIS_vect_num 12 -#define TWIC_TWIS_vect _VECTOR(12) /* TWI Slave Interrupt */ -#define TWIC_TWIM_vect_num 13 -#define TWIC_TWIM_vect _VECTOR(13) /* TWI Master Interrupt */ - -/* TCC0 interrupt vectors */ -#define TCC0_OVF_vect_num 14 -#define TCC0_OVF_vect _VECTOR(14) /* Overflow Interrupt */ -#define TCC0_ERR_vect_num 15 -#define TCC0_ERR_vect _VECTOR(15) /* Error Interrupt */ -#define TCC0_CCA_vect_num 16 -#define TCC0_CCA_vect _VECTOR(16) /* Compare or Capture A Interrupt */ -#define TCC0_CCB_vect_num 17 -#define TCC0_CCB_vect _VECTOR(17) /* Compare or Capture B Interrupt */ -#define TCC0_CCC_vect_num 18 -#define TCC0_CCC_vect _VECTOR(18) /* Compare or Capture C Interrupt */ -#define TCC0_CCD_vect_num 19 -#define TCC0_CCD_vect _VECTOR(19) /* Compare or Capture D Interrupt */ - -/* TCC1 interrupt vectors */ -#define TCC1_OVF_vect_num 20 -#define TCC1_OVF_vect _VECTOR(20) /* Overflow Interrupt */ -#define TCC1_ERR_vect_num 21 -#define TCC1_ERR_vect _VECTOR(21) /* Error Interrupt */ -#define TCC1_CCA_vect_num 22 -#define TCC1_CCA_vect _VECTOR(22) /* Compare or Capture A Interrupt */ -#define TCC1_CCB_vect_num 23 -#define TCC1_CCB_vect _VECTOR(23) /* Compare or Capture B Interrupt */ - -/* SPIC interrupt vectors */ -#define SPIC_INT_vect_num 24 -#define SPIC_INT_vect _VECTOR(24) /* SPI Interrupt */ - -/* USARTC0 interrupt vectors */ -#define USARTC0_RXC_vect_num 25 -#define USARTC0_RXC_vect _VECTOR(25) /* Reception Complete Interrupt */ -#define USARTC0_DRE_vect_num 26 -#define USARTC0_DRE_vect _VECTOR(26) /* Data Register Empty Interrupt */ -#define USARTC0_TXC_vect_num 27 -#define USARTC0_TXC_vect _VECTOR(27) /* Transmission Complete Interrupt */ - -/* NVM interrupt vectors */ -#define NVM_EE_vect_num 32 -#define NVM_EE_vect _VECTOR(32) /* EE Interrupt */ -#define NVM_SPM_vect_num 33 -#define NVM_SPM_vect _VECTOR(33) /* SPM Interrupt */ - -/* PORTB interrupt vectors */ -#define PORTB_INT0_vect_num 34 -#define PORTB_INT0_vect _VECTOR(34) /* External Interrupt 0 */ -#define PORTB_INT1_vect_num 35 -#define PORTB_INT1_vect _VECTOR(35) /* External Interrupt 1 */ - -/* PORTE interrupt vectors */ -#define PORTE_INT0_vect_num 43 -#define PORTE_INT0_vect _VECTOR(43) /* External Interrupt 0 */ -#define PORTE_INT1_vect_num 44 -#define PORTE_INT1_vect _VECTOR(44) /* External Interrupt 1 */ - -/* TWIE interrupt vectors */ -#define TWIE_TWIS_vect_num 45 -#define TWIE_TWIS_vect _VECTOR(45) /* TWI Slave Interrupt */ -#define TWIE_TWIM_vect_num 46 -#define TWIE_TWIM_vect _VECTOR(46) /* TWI Master Interrupt */ - -/* TCE0 interrupt vectors */ -#define TCE0_OVF_vect_num 47 -#define TCE0_OVF_vect _VECTOR(47) /* Overflow Interrupt */ -#define TCE0_ERR_vect_num 48 -#define TCE0_ERR_vect _VECTOR(48) /* Error Interrupt */ -#define TCE0_CCA_vect_num 49 -#define TCE0_CCA_vect _VECTOR(49) /* Compare or Capture A Interrupt */ -#define TCE0_CCB_vect_num 50 -#define TCE0_CCB_vect _VECTOR(50) /* Compare or Capture B Interrupt */ -#define TCE0_CCC_vect_num 51 -#define TCE0_CCC_vect _VECTOR(51) /* Compare or Capture C Interrupt */ -#define TCE0_CCD_vect_num 52 -#define TCE0_CCD_vect _VECTOR(52) /* Compare or Capture D Interrupt */ - -/* USARTE0 interrupt vectors */ -#define USARTE0_RXC_vect_num 58 -#define USARTE0_RXC_vect _VECTOR(58) /* Reception Complete Interrupt */ -#define USARTE0_DRE_vect_num 59 -#define USARTE0_DRE_vect _VECTOR(59) /* Data Register Empty Interrupt */ -#define USARTE0_TXC_vect_num 60 -#define USARTE0_TXC_vect _VECTOR(60) /* Transmission Complete Interrupt */ - -/* PORTD interrupt vectors */ -#define PORTD_INT0_vect_num 64 -#define PORTD_INT0_vect _VECTOR(64) /* External Interrupt 0 */ -#define PORTD_INT1_vect_num 65 -#define PORTD_INT1_vect _VECTOR(65) /* External Interrupt 1 */ - -/* PORTA interrupt vectors */ -#define PORTA_INT0_vect_num 66 -#define PORTA_INT0_vect _VECTOR(66) /* External Interrupt 0 */ -#define PORTA_INT1_vect_num 67 -#define PORTA_INT1_vect _VECTOR(67) /* External Interrupt 1 */ - -/* ACA interrupt vectors */ -#define ACA_AC0_vect_num 68 -#define ACA_AC0_vect _VECTOR(68) /* AC0 Interrupt */ -#define ACA_AC1_vect_num 69 -#define ACA_AC1_vect _VECTOR(69) /* AC1 Interrupt */ -#define ACA_ACW_vect_num 70 -#define ACA_ACW_vect _VECTOR(70) /* ACW Window Mode Interrupt */ - -/* ADCA interrupt vectors */ -#define ADCA_CH0_vect_num 71 -#define ADCA_CH0_vect _VECTOR(71) /* Interrupt 0 */ - -/* TCD0 interrupt vectors */ -#define TCD0_OVF_vect_num 77 -#define TCD0_OVF_vect _VECTOR(77) /* Overflow Interrupt */ -#define TCD0_ERR_vect_num 78 -#define TCD0_ERR_vect _VECTOR(78) /* Error Interrupt */ -#define TCD0_CCA_vect_num 79 -#define TCD0_CCA_vect _VECTOR(79) /* Compare or Capture A Interrupt */ -#define TCD0_CCB_vect_num 80 -#define TCD0_CCB_vect _VECTOR(80) /* Compare or Capture B Interrupt */ -#define TCD0_CCC_vect_num 81 -#define TCD0_CCC_vect _VECTOR(81) /* Compare or Capture C Interrupt */ -#define TCD0_CCD_vect_num 82 -#define TCD0_CCD_vect _VECTOR(82) /* Compare or Capture D Interrupt */ - -/* SPID interrupt vectors */ -#define SPID_INT_vect_num 87 -#define SPID_INT_vect _VECTOR(87) /* SPI Interrupt */ - -/* USARTD0 interrupt vectors */ -#define USARTD0_RXC_vect_num 88 -#define USARTD0_RXC_vect _VECTOR(88) /* Reception Complete Interrupt */ -#define USARTD0_DRE_vect_num 89 -#define USARTD0_DRE_vect _VECTOR(89) /* Data Register Empty Interrupt */ -#define USARTD0_TXC_vect_num 90 -#define USARTD0_TXC_vect _VECTOR(90) /* Transmission Complete Interrupt */ - -/* PORTF interrupt vectors */ -#define PORTF_INT0_vect_num 104 -#define PORTF_INT0_vect _VECTOR(104) /* External Interrupt 0 */ -#define PORTF_INT1_vect_num 105 -#define PORTF_INT1_vect _VECTOR(105) /* External Interrupt 1 */ - -/* TCF0 interrupt vectors */ -#define TCF0_OVF_vect_num 108 -#define TCF0_OVF_vect _VECTOR(108) /* Overflow Interrupt */ -#define TCF0_ERR_vect_num 109 -#define TCF0_ERR_vect _VECTOR(109) /* Error Interrupt */ -#define TCF0_CCA_vect_num 110 -#define TCF0_CCA_vect _VECTOR(110) /* Compare or Capture A Interrupt */ -#define TCF0_CCB_vect_num 111 -#define TCF0_CCB_vect _VECTOR(111) /* Compare or Capture B Interrupt */ -#define TCF0_CCC_vect_num 112 -#define TCF0_CCC_vect _VECTOR(112) /* Compare or Capture C Interrupt */ -#define TCF0_CCD_vect_num 113 -#define TCF0_CCD_vect _VECTOR(113) /* Compare or Capture D Interrupt */ - - -#define _VECTOR_SIZE 4 /* Size of individual vector. */ -#define _VECTORS_SIZE (114 * _VECTOR_SIZE) - - -/* ========== Constants ========== */ - -#define PROGMEM_START (0x0000) -#define PROGMEM_SIZE (69632) -#define PROGMEM_PAGE_SIZE (256) -#define PROGMEM_END (PROGMEM_START + PROGMEM_SIZE - 1) - -#define APP_SECTION_START (0x0000) -#define APP_SECTION_SIZE (65536) -#define APP_SECTION_PAGE_SIZE (256) -#define APP_SECTION_END (APP_SECTION_START + APP_SECTION_SIZE - 1) - -#define APPTABLE_SECTION_START (0x0F000) -#define APPTABLE_SECTION_SIZE (4096) -#define APPTABLE_SECTION_PAGE_SIZE (256) -#define APPTABLE_SECTION_END (APPTABLE_SECTION_START + APPTABLE_SECTION_SIZE - 1) - -#define BOOT_SECTION_START (0x10000) -#define BOOT_SECTION_SIZE (4096) -#define BOOT_SECTION_PAGE_SIZE (256) -#define BOOT_SECTION_END (BOOT_SECTION_START + BOOT_SECTION_SIZE - 1) - -#define DATAMEM_START (0x0000) -#define DATAMEM_SIZE (12288) -#define DATAMEM_PAGE_SIZE (0) -#define DATAMEM_END (DATAMEM_START + DATAMEM_SIZE - 1) - -#define IO_START (0x0000) -#define IO_SIZE (4096) -#define IO_PAGE_SIZE (0) -#define IO_END (IO_START + IO_SIZE - 1) - -#define MAPPED_EEPROM_START (0x1000) -#define MAPPED_EEPROM_SIZE (2048) -#define MAPPED_EEPROM_PAGE_SIZE (0) -#define MAPPED_EEPROM_END (MAPPED_EEPROM_START + MAPPED_EEPROM_SIZE - 1) - -#define INTERNAL_SRAM_START (0x2000) -#define INTERNAL_SRAM_SIZE (4096) -#define INTERNAL_SRAM_PAGE_SIZE (0) -#define INTERNAL_SRAM_END (INTERNAL_SRAM_START + INTERNAL_SRAM_SIZE - 1) - -#define EEPROM_START (0x0000) -#define EEPROM_SIZE (2048) -#define EEPROM_PAGE_SIZE (32) -#define EEPROM_END (EEPROM_START + EEPROM_SIZE - 1) - -#define FUSE_START (0x0000) -#define FUSE_SIZE (6) -#define FUSE_PAGE_SIZE (0) -#define FUSE_END (FUSE_START + FUSE_SIZE - 1) - -#define LOCKBIT_START (0x0000) -#define LOCKBIT_SIZE (1) -#define LOCKBIT_PAGE_SIZE (0) -#define LOCKBIT_END (LOCKBIT_START + LOCKBIT_SIZE - 1) - -#define SIGNATURES_START (0x0000) -#define SIGNATURES_SIZE (3) -#define SIGNATURES_PAGE_SIZE (0) -#define SIGNATURES_END (SIGNATURES_START + SIGNATURES_SIZE - 1) - -#define USER_SIGNATURES_START (0x0000) -#define USER_SIGNATURES_SIZE (256) -#define USER_SIGNATURES_PAGE_SIZE (0) -#define USER_SIGNATURES_END (USER_SIGNATURES_START + USER_SIGNATURES_SIZE - 1) - -#define PROD_SIGNATURES_START (0x0000) -#define PROD_SIGNATURES_SIZE (52) -#define PROD_SIGNATURES_PAGE_SIZE (0) -#define PROD_SIGNATURES_END (PROD_SIGNATURES_START + PROD_SIGNATURES_SIZE - 1) - -#define FLASHEND PROGMEM_END -#define SPM_PAGESIZE PROGMEM_PAGE_SIZE -#define RAMSTART INTERNAL_SRAM_START -#define RAMSIZE INTERNAL_SRAM_SIZE -#define RAMEND INTERNAL_SRAM_END -#define XRAMSTART EXTERNAL_SRAM_START -#define XRAMSIZE EXTERNAL_SRAM_SIZE -#define XRAMEND INTERNAL_SRAM_END -#define E2END EEPROM_END -#define E2PAGESIZE EEPROM_PAGE_SIZE - - -/* ========== Fuses ========== */ -#define FUSE_MEMORY_SIZE 6 - -/* Fuse Byte 0 */ -#define FUSE_USERID0 (unsigned char)~_BV(0) /* User ID Bit 0 */ -#define FUSE_USERID1 (unsigned char)~_BV(1) /* User ID Bit 1 */ -#define FUSE_USERID2 (unsigned char)~_BV(2) /* User ID Bit 2 */ -#define FUSE_USERID3 (unsigned char)~_BV(3) /* User ID Bit 3 */ -#define FUSE_USERID4 (unsigned char)~_BV(4) /* User ID Bit 4 */ -#define FUSE_USERID5 (unsigned char)~_BV(5) /* User ID Bit 5 */ -#define FUSE_USERID6 (unsigned char)~_BV(6) /* User ID Bit 6 */ -#define FUSE_USERID7 (unsigned char)~_BV(7) /* User ID Bit 7 */ -#define FUSE0_DEFAULT (0xFF) - -/* Fuse Byte 1 */ -#define FUSE_WDP0 (unsigned char)~_BV(0) /* Watchdog Timeout Period Bit 0 */ -#define FUSE_WDP1 (unsigned char)~_BV(1) /* Watchdog Timeout Period Bit 1 */ -#define FUSE_WDP2 (unsigned char)~_BV(2) /* Watchdog Timeout Period Bit 2 */ -#define FUSE_WDP3 (unsigned char)~_BV(3) /* Watchdog Timeout Period Bit 3 */ -#define FUSE_WDWP0 (unsigned char)~_BV(4) /* Watchdog Window Timeout Period Bit 0 */ -#define FUSE_WDWP1 (unsigned char)~_BV(5) /* Watchdog Window Timeout Period Bit 1 */ -#define FUSE_WDWP2 (unsigned char)~_BV(6) /* Watchdog Window Timeout Period Bit 2 */ -#define FUSE_WDWP3 (unsigned char)~_BV(7) /* Watchdog Window Timeout Period Bit 3 */ -#define FUSE1_DEFAULT (0xFF) - -/* Fuse Byte 2 */ -#define FUSE_BODPD0 (unsigned char)~_BV(0) /* BOD Operation in Power-Down Mode Bit 0 */ -#define FUSE_BODPD1 (unsigned char)~_BV(1) /* BOD Operation in Power-Down Mode Bit 1 */ -#define FUSE_BOOTRST (unsigned char)~_BV(6) /* Boot Loader Section Reset Vector */ -#define FUSE_DVSDON (unsigned char)~_BV(7) /* Spike Detector Enable */ -#define FUSE2_DEFAULT (0xFF) - -/* Fuse Byte 3 Reserved */ - -/* Fuse Byte 4 */ -#define FUSE_WDLOCK (unsigned char)~_BV(1) /* Watchdog Timer Lock */ -#define FUSE_SUT0 (unsigned char)~_BV(2) /* Start-up Time Bit 0 */ -#define FUSE_SUT1 (unsigned char)~_BV(3) /* Start-up Time Bit 1 */ -#define FUSE4_DEFAULT (0xFF) - -/* Fuse Byte 5 */ -#define FUSE_BODLVL0 (unsigned char)~_BV(0) /* Brown Out Detection Voltage Level Bit 0 */ -#define FUSE_BODLVL1 (unsigned char)~_BV(1) /* Brown Out Detection Voltage Level Bit 1 */ -#define FUSE_BODLVL2 (unsigned char)~_BV(2) /* Brown Out Detection Voltage Level Bit 2 */ -#define FUSE_EESAVE (unsigned char)~_BV(3) /* Preserve EEPROM Through Chip Erase */ -#define FUSE_BODACT0 (unsigned char)~_BV(4) /* BOD Operation in Active Mode Bit 0 */ -#define FUSE_BODACT1 (unsigned char)~_BV(5) /* BOD Operation in Active Mode Bit 1 */ -#define FUSE5_DEFAULT (0xFF) - - -/* ========== Lock Bits ========== */ -#define __LOCK_BITS_EXIST -#define __BOOT_LOCK_APPLICATION_TABLE_BITS_EXIST -#define __BOOT_LOCK_APPLICATION_BITS_EXIST -#define __BOOT_LOCK_BOOT_BITS_EXIST - - -/* ========== Signature ========== */ -#define SIGNATURE_0 0x1E -#define SIGNATURE_1 0x96 -#define SIGNATURE_2 0x4A - -/* ========== Power Reduction Condition Definitions ========== */ - -/* PR.PRGEN */ -#define __AVR_HAVE_PRGEN (PR_RTC_bm|PR_EVSYS_bm) -#define __AVR_HAVE_PRGEN_RTC -#define __AVR_HAVE_PRGEN_EVSYS - -/* PR.PRPA */ -#define __AVR_HAVE_PRPA (PR_ADC_bm|PR_AC_bm) -#define __AVR_HAVE_PRPA_ADC -#define __AVR_HAVE_PRPA_AC - -/* PR.PRPC */ -#define __AVR_HAVE_PRPC (PR_TWI_bm|PR_USART0_bm|PR_SPI_bm|PR_HIRES_bm|PR_TC1_bm|PR_TC0_bm) -#define __AVR_HAVE_PRPC_TWI -#define __AVR_HAVE_PRPC_USART0 -#define __AVR_HAVE_PRPC_SPI -#define __AVR_HAVE_PRPC_HIRES -#define __AVR_HAVE_PRPC_TC1 -#define __AVR_HAVE_PRPC_TC0 - -/* PR.PRPD */ -#define __AVR_HAVE_PRPD (PR_USART0_bm|PR_SPI_bm|PR_TC0_bm) -#define __AVR_HAVE_PRPD_USART0 -#define __AVR_HAVE_PRPD_SPI -#define __AVR_HAVE_PRPD_TC0 - -/* PR.PRPE */ -#define __AVR_HAVE_PRPE (PR_TWI_bm|PR_USART0_bm|PR_TC0_bm) -#define __AVR_HAVE_PRPE_TWI -#define __AVR_HAVE_PRPE_USART0 -#define __AVR_HAVE_PRPE_TC0 - -/* PR.PRPF */ -#define __AVR_HAVE_PRPF (PR_USART0_bm|PR_TC0_bm) -#define __AVR_HAVE_PRPF_USART0 -#define __AVR_HAVE_PRPF_TC0 - - -#endif /* _AVR_ATxmega64D3_H_ */ - diff --git a/arduino/hardware/tools/avr/avr/include/avr/iox64d4.h b/arduino/hardware/tools/avr/avr/include/avr/iox64d4.h deleted file mode 100644 index 26c9d5e..0000000 --- a/arduino/hardware/tools/avr/avr/include/avr/iox64d4.h +++ /dev/null @@ -1,5555 +0,0 @@ -/***************************************************************************** - * - * Copyright (C) 2015 Atmel Corporation - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * - * * Neither the name of the copyright holders nor the names of - * contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - ****************************************************************************/ - - -#ifndef _AVR_IO_H_ -# error "Include instead of this file." -#endif - -#ifndef _AVR_IOXXX_H_ -# define _AVR_IOXXX_H_ "iox64d4.h" -#else -# error "Attempt to include more than one file." -#endif - -#ifndef _AVR_ATXMEGA64D4_H_INCLUDED -#define _AVR_ATXMEGA64D4_H_INCLUDED - -/* Ungrouped common registers */ -#define GPIOR0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ -#define GPIOR1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ -#define GPIOR2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ -#define GPIOR3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ - -/* Deprecated */ -#define GPIO0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ -#define GPIO1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ -#define GPIO2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ -#define GPIO3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ - -#define CCP _SFR_MEM8(0x0034) /* Configuration Change Protection */ -#define RAMPD _SFR_MEM8(0x0038) /* Ramp D */ -#define RAMPX _SFR_MEM8(0x0039) /* Ramp X */ -#define RAMPY _SFR_MEM8(0x003A) /* Ramp Y */ -#define RAMPZ _SFR_MEM8(0x003B) /* Ramp Z */ -#define EIND _SFR_MEM8(0x003C) /* Extended Indirect Jump */ -#define SPL _SFR_MEM8(0x003D) /* Stack Pointer Low */ -#define SPH _SFR_MEM8(0x003E) /* Stack Pointer High */ -#define SREG _SFR_MEM8(0x003F) /* Status Register */ - -/* C Language Only */ -#if !defined (__ASSEMBLER__) - -#include - -typedef volatile uint8_t register8_t; -typedef volatile uint16_t register16_t; -typedef volatile uint32_t register32_t; - - -#ifdef _WORDREGISTER -#undef _WORDREGISTER -#endif -#define _WORDREGISTER(regname) \ - __extension__ union \ - { \ - register16_t regname; \ - struct \ - { \ - register8_t regname ## L; \ - register8_t regname ## H; \ - }; \ - } - -#ifdef _DWORDREGISTER -#undef _DWORDREGISTER -#endif -#define _DWORDREGISTER(regname) \ - __extension__ union \ - { \ - register32_t regname; \ - struct \ - { \ - register8_t regname ## 0; \ - register8_t regname ## 1; \ - register8_t regname ## 2; \ - register8_t regname ## 3; \ - }; \ - } - - -/* -========================================================================== -IO Module Structures -========================================================================== -*/ - - -/* --------------------------------------------------------------------------- -VPORT - Virtual Ports --------------------------------------------------------------------------- -*/ - -/* Virtual Port */ -typedef struct VPORT_struct -{ - register8_t DIR; /* I/O Port Data Direction */ - register8_t OUT; /* I/O Port Output */ - register8_t IN; /* I/O Port Input */ - register8_t INTFLAGS; /* Interrupt Flag Register */ -} VPORT_t; - - -/* --------------------------------------------------------------------------- -XOCD - On-Chip Debug System --------------------------------------------------------------------------- -*/ - -/* On-Chip Debug System */ -typedef struct OCD_struct -{ - register8_t OCDR0; /* OCD Register 0 */ - register8_t OCDR1; /* OCD Register 1 */ -} OCD_t; - - -/* --------------------------------------------------------------------------- -CPU - CPU --------------------------------------------------------------------------- -*/ - -/* CCP signatures */ -typedef enum CCP_enum -{ - CCP_SPM_gc = (0x9D<<0), /* SPM Instruction Protection */ - CCP_IOREG_gc = (0xD8<<0), /* IO Register Protection */ -} CCP_t; - - -/* --------------------------------------------------------------------------- -CLK - Clock System --------------------------------------------------------------------------- -*/ - -/* Clock System */ -typedef struct CLK_struct -{ - register8_t CTRL; /* Control Register */ - register8_t PSCTRL; /* Prescaler Control Register */ - register8_t LOCK; /* Lock register */ - register8_t RTCCTRL; /* RTC Control Register */ - register8_t reserved_0x04; -} CLK_t; - - -/* Power Reduction */ -typedef struct PR_struct -{ - register8_t PRGEN; /* General Power Reduction */ - register8_t PRPA; /* Power Reduction Port A */ - register8_t reserved_0x02; - register8_t PRPC; /* Power Reduction Port C */ - register8_t PRPD; /* Power Reduction Port D */ - register8_t PRPE; /* Power Reduction Port E */ - register8_t PRPF; /* Power Reduction Port F */ -} PR_t; - -/* System Clock Selection */ -typedef enum CLK_SCLKSEL_enum -{ - CLK_SCLKSEL_RC2M_gc = (0x00<<0), /* Internal 2 MHz RC Oscillator */ - CLK_SCLKSEL_RC32M_gc = (0x01<<0), /* Internal 32 MHz RC Oscillator */ - CLK_SCLKSEL_RC32K_gc = (0x02<<0), /* Internal 32.768 kHz RC Oscillator */ - CLK_SCLKSEL_XOSC_gc = (0x03<<0), /* External Crystal Oscillator or Clock */ - CLK_SCLKSEL_PLL_gc = (0x04<<0), /* Phase Locked Loop */ -} CLK_SCLKSEL_t; - -/* Prescaler A Division Factor */ -typedef enum CLK_PSADIV_enum -{ - CLK_PSADIV_1_gc = (0x00<<2), /* Divide by 1 */ - CLK_PSADIV_2_gc = (0x01<<2), /* Divide by 2 */ - CLK_PSADIV_4_gc = (0x03<<2), /* Divide by 4 */ - CLK_PSADIV_8_gc = (0x05<<2), /* Divide by 8 */ - CLK_PSADIV_16_gc = (0x07<<2), /* Divide by 16 */ - CLK_PSADIV_32_gc = (0x09<<2), /* Divide by 32 */ - CLK_PSADIV_64_gc = (0x0B<<2), /* Divide by 64 */ - CLK_PSADIV_128_gc = (0x0D<<2), /* Divide by 128 */ - CLK_PSADIV_256_gc = (0x0F<<2), /* Divide by 256 */ - CLK_PSADIV_512_gc = (0x11<<2), /* Divide by 512 */ -} CLK_PSADIV_t; - -/* Prescaler B and C Division Factor */ -typedef enum CLK_PSBCDIV_enum -{ - CLK_PSBCDIV_1_1_gc = (0x00<<0), /* Divide B by 1 and C by 1 */ - CLK_PSBCDIV_1_2_gc = (0x01<<0), /* Divide B by 1 and C by 2 */ - CLK_PSBCDIV_4_1_gc = (0x02<<0), /* Divide B by 4 and C by 1 */ - CLK_PSBCDIV_2_2_gc = (0x03<<0), /* Divide B by 2 and C by 2 */ -} CLK_PSBCDIV_t; - -/* RTC Clock Source */ -typedef enum CLK_RTCSRC_enum -{ - CLK_RTCSRC_ULP_gc = (0x00<<1), /* 1 kHz from internal 32kHz ULP */ - CLK_RTCSRC_TOSC_gc = (0x01<<1), /* 1.024 kHz from 32.768 kHz crystal oscillator on TOSC */ - CLK_RTCSRC_RCOSC_gc = (0x02<<1), /* 1.024 kHz from 32.768 kHz internal oscillator */ - CLK_RTCSRC_TOSC32_gc = (0x05<<1), /* 32.768 kHz from 32.768 kHz crystal oscillator on TOSC */ - CLK_RTCSRC_RCOSC32_gc = (0x06<<1), /* 32.768 kHz from 32.768 kHz internal oscillator */ - CLK_RTCSRC_EXTCLK_gc = (0x07<<1), /* External Clock from TOSC1 */ -} CLK_RTCSRC_t; - - -/* --------------------------------------------------------------------------- -SLEEP - Sleep Controller --------------------------------------------------------------------------- -*/ - -/* Sleep Controller */ -typedef struct SLEEP_struct -{ - register8_t CTRL; /* Control Register */ -} SLEEP_t; - -/* Sleep Mode */ -typedef enum SLEEP_SMODE_enum -{ - SLEEP_SMODE_IDLE_gc = (0x00<<1), /* Idle mode */ - SLEEP_SMODE_PDOWN_gc = (0x02<<1), /* Power-down Mode */ - SLEEP_SMODE_PSAVE_gc = (0x03<<1), /* Power-save Mode */ - SLEEP_SMODE_STDBY_gc = (0x06<<1), /* Standby Mode */ - SLEEP_SMODE_ESTDBY_gc = (0x07<<1), /* Extended Standby Mode */ -} SLEEP_SMODE_t; - - - -#define SLEEP_MODE_IDLE (0x00<<1) -#define SLEEP_MODE_PWR_DOWN (0x02<<1) -#define SLEEP_MODE_PWR_SAVE (0x03<<1) -#define SLEEP_MODE_STANDBY (0x06<<1) -#define SLEEP_MODE_EXT_STANDBY (0x07<<1) -/* --------------------------------------------------------------------------- -OSC - Oscillator --------------------------------------------------------------------------- -*/ - -/* Oscillator */ -typedef struct OSC_struct -{ - register8_t CTRL; /* Control Register */ - register8_t STATUS; /* Status Register */ - register8_t XOSCCTRL; /* External Oscillator Control Register */ - register8_t XOSCFAIL; /* Oscillator Failure Detection Register */ - register8_t RC32KCAL; /* 32.768 kHz Internal Oscillator Calibration Register */ - register8_t PLLCTRL; /* PLL Control Register */ - register8_t DFLLCTRL; /* DFLL Control Register */ -} OSC_t; - -/* Oscillator Frequency Range */ -typedef enum OSC_FRQRANGE_enum -{ - OSC_FRQRANGE_04TO2_gc = (0x00<<6), /* 0.4 - 2 MHz */ - OSC_FRQRANGE_2TO9_gc = (0x01<<6), /* 2 - 9 MHz */ - OSC_FRQRANGE_9TO12_gc = (0x02<<6), /* 9 - 12 MHz */ - OSC_FRQRANGE_12TO16_gc = (0x03<<6), /* 12 - 16 MHz */ -} OSC_FRQRANGE_t; - -/* External Oscillator Selection and Startup Time */ -typedef enum OSC_XOSCSEL_enum -{ - OSC_XOSCSEL_EXTCLK_gc = (0x00<<0), /* External Clock - 6 CLK */ - OSC_XOSCSEL_32KHz_gc = (0x02<<0), /* 32.768 kHz TOSC - 32K CLK */ - OSC_XOSCSEL_XTAL_256CLK_gc = (0x03<<0), /* 0.4-16 MHz XTAL - 256 CLK */ - OSC_XOSCSEL_XTAL_1KCLK_gc = (0x07<<0), /* 0.4-16 MHz XTAL - 1K CLK */ - OSC_XOSCSEL_XTAL_16KCLK_gc = (0x0B<<0), /* 0.4-16 MHz XTAL - 16K CLK */ -} OSC_XOSCSEL_t; - -/* PLL Clock Source */ -typedef enum OSC_PLLSRC_enum -{ - OSC_PLLSRC_RC2M_gc = (0x00<<6), /* Internal 2 MHz RC Oscillator */ - OSC_PLLSRC_RC32M_gc = (0x02<<6), /* Internal 32 MHz RC Oscillator */ - OSC_PLLSRC_XOSC_gc = (0x03<<6), /* External Oscillator */ -} OSC_PLLSRC_t; - -/* 2 MHz DFLL Calibration Reference */ -typedef enum OSC_RC2MCREF_enum -{ - OSC_RC2MCREF_RC32K_gc = (0x00<<0), /* Internal 32.768 kHz RC Oscillator */ - OSC_RC2MCREF_XOSC32K_gc = (0x01<<0), /* External 32.768 kHz Crystal Oscillator */ -} OSC_RC2MCREF_t; - -/* 32 MHz DFLL Calibration Reference */ -typedef enum OSC_RC32MCREF_enum -{ - OSC_RC32MCREF_RC32K_gc = (0x00<<1), /* Internal 32.768 kHz RC Oscillator */ - OSC_RC32MCREF_XOSC32K_gc = (0x01<<1), /* External 32.768 kHz Crystal Oscillator */ -} OSC_RC32MCREF_t; - - -/* --------------------------------------------------------------------------- -DFLL - DFLL --------------------------------------------------------------------------- -*/ - -/* DFLL */ -typedef struct DFLL_struct -{ - register8_t CTRL; /* Control Register */ - register8_t reserved_0x01; - register8_t CALA; /* Calibration Register A */ - register8_t CALB; /* Calibration Register B */ - register8_t COMP0; /* Oscillator Compare Register 0 */ - register8_t COMP1; /* Oscillator Compare Register 1 */ - register8_t COMP2; /* Oscillator Compare Register 2 */ - register8_t reserved_0x07; -} DFLL_t; - - -/* --------------------------------------------------------------------------- -RST - Reset --------------------------------------------------------------------------- -*/ - -/* Reset */ -typedef struct RST_struct -{ - register8_t STATUS; /* Status Register */ - register8_t CTRL; /* Control Register */ -} RST_t; - - -/* --------------------------------------------------------------------------- -WDT - Watch-Dog Timer --------------------------------------------------------------------------- -*/ - -/* Watch-Dog Timer */ -typedef struct WDT_struct -{ - register8_t CTRL; /* Control */ - register8_t WINCTRL; /* Windowed Mode Control */ - register8_t STATUS; /* Status */ -} WDT_t; - -/* Period setting */ -typedef enum WDT_PER_enum -{ - WDT_PER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ - WDT_PER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ - WDT_PER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ - WDT_PER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ - WDT_PER_128CLK_gc = (0x04<<2), /* 128 cycles (0.128s @ 3.3V) */ - WDT_PER_256CLK_gc = (0x05<<2), /* 256 cycles (0.256s @ 3.3V) */ - WDT_PER_512CLK_gc = (0x06<<2), /* 512 cycles (0.512s @ 3.3V) */ - WDT_PER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ - WDT_PER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ - WDT_PER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ - WDT_PER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ -} WDT_PER_t; - -/* Closed window period */ -typedef enum WDT_WPER_enum -{ - WDT_WPER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ - WDT_WPER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ - WDT_WPER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ - WDT_WPER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ - WDT_WPER_128CLK_gc = (0x04<<2), /* 128 cycles (0.128s @ 3.3V) */ - WDT_WPER_256CLK_gc = (0x05<<2), /* 256 cycles (0.256s @ 3.3V) */ - WDT_WPER_512CLK_gc = (0x06<<2), /* 512 cycles (0.512s @ 3.3V) */ - WDT_WPER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ - WDT_WPER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ - WDT_WPER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ - WDT_WPER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ -} WDT_WPER_t; - - -/* --------------------------------------------------------------------------- -MCU - MCU Control --------------------------------------------------------------------------- -*/ - -/* MCU Control */ -typedef struct MCU_struct -{ - register8_t DEVID0; /* Device ID byte 0 */ - register8_t DEVID1; /* Device ID byte 1 */ - register8_t DEVID2; /* Device ID byte 2 */ - register8_t REVID; /* Revision ID */ - register8_t reserved_0x04; - register8_t reserved_0x05; - register8_t reserved_0x06; - register8_t ANAINIT; /* Analog Startup Delay */ - register8_t EVSYSLOCK; /* Event System Lock */ - register8_t AWEXLOCK; /* AWEX Lock */ - register8_t reserved_0x0A; - register8_t reserved_0x0B; -} MCU_t; - - -/* --------------------------------------------------------------------------- -PMIC - Programmable Multi-level Interrupt Controller --------------------------------------------------------------------------- -*/ - -/* Programmable Multi-level Interrupt Controller */ -typedef struct PMIC_struct -{ - register8_t STATUS; /* Status Register */ - register8_t INTPRI; /* Interrupt Priority */ - register8_t CTRL; /* Control Register */ - register8_t reserved_0x03; - register8_t reserved_0x04; - register8_t reserved_0x05; - register8_t reserved_0x06; - register8_t reserved_0x07; - register8_t reserved_0x08; - register8_t reserved_0x09; - register8_t reserved_0x0A; - register8_t reserved_0x0B; - register8_t reserved_0x0C; - register8_t reserved_0x0D; - register8_t reserved_0x0E; - register8_t reserved_0x0F; -} PMIC_t; - - -/* --------------------------------------------------------------------------- -PORTCFG - Port Configuration --------------------------------------------------------------------------- -*/ - -/* I/O port Configuration */ -typedef struct PORTCFG_struct -{ - register8_t MPCMASK; /* Multi-pin Configuration Mask */ - register8_t reserved_0x01; - register8_t VPCTRLA; /* Virtual Port Control Register A */ - register8_t VPCTRLB; /* Virtual Port Control Register B */ - register8_t CLKEVOUT; /* Clock and Event Out Register */ - register8_t reserved_0x05; - register8_t EVOUTSEL; /* Event Output Select */ -} PORTCFG_t; - -/* Virtual Port Mapping */ -typedef enum PORTCFG_VP02MAP_enum -{ - PORTCFG_VP02MAP_PORTA_gc = (0x00<<0), /* Mapped To PORTA */ - PORTCFG_VP02MAP_PORTB_gc = (0x01<<0), /* Mapped To PORTB */ - PORTCFG_VP02MAP_PORTC_gc = (0x02<<0), /* Mapped To PORTC */ - PORTCFG_VP02MAP_PORTD_gc = (0x03<<0), /* Mapped To PORTD */ - PORTCFG_VP02MAP_PORTE_gc = (0x04<<0), /* Mapped To PORTE */ - PORTCFG_VP02MAP_PORTF_gc = (0x05<<0), /* Mapped To PORTF */ - PORTCFG_VP02MAP_PORTG_gc = (0x06<<0), /* Mapped To PORTG */ - PORTCFG_VP02MAP_PORTH_gc = (0x07<<0), /* Mapped To PORTH */ - PORTCFG_VP02MAP_PORTJ_gc = (0x08<<0), /* Mapped To PORTJ */ - PORTCFG_VP02MAP_PORTK_gc = (0x09<<0), /* Mapped To PORTK */ - PORTCFG_VP02MAP_PORTL_gc = (0x0A<<0), /* Mapped To PORTL */ - PORTCFG_VP02MAP_PORTM_gc = (0x0B<<0), /* Mapped To PORTM */ - PORTCFG_VP02MAP_PORTN_gc = (0x0C<<0), /* Mapped To PORTN */ - PORTCFG_VP02MAP_PORTP_gc = (0x0D<<0), /* Mapped To PORTP */ - PORTCFG_VP02MAP_PORTQ_gc = (0x0E<<0), /* Mapped To PORTQ */ - PORTCFG_VP02MAP_PORTR_gc = (0x0F<<0), /* Mapped To PORTR */ -} PORTCFG_VP02MAP_t; - -/* Virtual Port Mapping */ -typedef enum PORTCFG_VP13MAP_enum -{ - PORTCFG_VP13MAP_PORTA_gc = (0x00<<4), /* Mapped To PORTA */ - PORTCFG_VP13MAP_PORTB_gc = (0x01<<4), /* Mapped To PORTB */ - PORTCFG_VP13MAP_PORTC_gc = (0x02<<4), /* Mapped To PORTC */ - PORTCFG_VP13MAP_PORTD_gc = (0x03<<4), /* Mapped To PORTD */ - PORTCFG_VP13MAP_PORTE_gc = (0x04<<4), /* Mapped To PORTE */ - PORTCFG_VP13MAP_PORTF_gc = (0x05<<4), /* Mapped To PORTF */ - PORTCFG_VP13MAP_PORTG_gc = (0x06<<4), /* Mapped To PORTG */ - PORTCFG_VP13MAP_PORTH_gc = (0x07<<4), /* Mapped To PORTH */ - PORTCFG_VP13MAP_PORTJ_gc = (0x08<<4), /* Mapped To PORTJ */ - PORTCFG_VP13MAP_PORTK_gc = (0x09<<4), /* Mapped To PORTK */ - PORTCFG_VP13MAP_PORTL_gc = (0x0A<<4), /* Mapped To PORTL */ - PORTCFG_VP13MAP_PORTM_gc = (0x0B<<4), /* Mapped To PORTM */ - PORTCFG_VP13MAP_PORTN_gc = (0x0C<<4), /* Mapped To PORTN */ - PORTCFG_VP13MAP_PORTP_gc = (0x0D<<4), /* Mapped To PORTP */ - PORTCFG_VP13MAP_PORTQ_gc = (0x0E<<4), /* Mapped To PORTQ */ - PORTCFG_VP13MAP_PORTR_gc = (0x0F<<4), /* Mapped To PORTR */ -} PORTCFG_VP13MAP_t; - -/* System Clock Output Port */ -typedef enum PORTCFG_CLKOUT_enum -{ - PORTCFG_CLKOUT_OFF_gc = (0x00<<0), /* System Clock Output Disabled */ - PORTCFG_CLKOUT_PC7_gc = (0x01<<0), /* System Clock Output on Port C pin 7 */ - PORTCFG_CLKOUT_PD7_gc = (0x02<<0), /* System Clock Output on Port D pin 7 */ - PORTCFG_CLKOUT_PE7_gc = (0x03<<0), /* System Clock Output on Port E pin 7 */ -} PORTCFG_CLKOUT_t; - -/* Peripheral Clock Output Select */ -typedef enum PORTCFG_CLKOUTSEL_enum -{ - PORTCFG_CLKOUTSEL_CLK1X_gc = (0x00<<2), /* 1x Peripheral Clock Output to pin */ - PORTCFG_CLKOUTSEL_CLK2X_gc = (0x01<<2), /* 2x Peripheral Clock Output to pin */ - PORTCFG_CLKOUTSEL_CLK4X_gc = (0x02<<2), /* 4x Peripheral Clock Output to pin */ -} PORTCFG_CLKOUTSEL_t; - -/* Event Output Port */ -typedef enum PORTCFG_EVOUT_enum -{ - PORTCFG_EVOUT_OFF_gc = (0x00<<4), /* Event Output Disabled */ - PORTCFG_EVOUT_PC7_gc = (0x01<<4), /* Event Channel 7 Output on Port C pin 7 */ - PORTCFG_EVOUT_PD7_gc = (0x02<<4), /* Event Channel 7 Output on Port D pin 7 */ - PORTCFG_EVOUT_PE7_gc = (0x03<<4), /* Event Channel 7 Output on Port E pin 7 */ -} PORTCFG_EVOUT_t; - -/* Event Output Select */ -typedef enum PORTCFG_EVOUTSEL_enum -{ - PORTCFG_EVOUTSEL_0_gc = (0x00<<0), /* Event Channel 0 output to pin */ - PORTCFG_EVOUTSEL_1_gc = (0x01<<0), /* Event Channel 1 output to pin */ - PORTCFG_EVOUTSEL_2_gc = (0x02<<0), /* Event Channel 2 output to pin */ - PORTCFG_EVOUTSEL_3_gc = (0x03<<0), /* Event Channel 3 output to pin */ -} PORTCFG_EVOUTSEL_t; - - -/* --------------------------------------------------------------------------- -CRC - Cyclic Redundancy Checker --------------------------------------------------------------------------- -*/ - -/* Cyclic Redundancy Checker */ -typedef struct CRC_struct -{ - register8_t CTRL; /* Control Register */ - register8_t STATUS; /* Status Register */ - register8_t reserved_0x02; - register8_t DATAIN; /* Data Input */ - register8_t CHECKSUM0; /* Checksum byte 0 */ - register8_t CHECKSUM1; /* Checksum byte 1 */ - register8_t CHECKSUM2; /* Checksum byte 2 */ - register8_t CHECKSUM3; /* Checksum byte 3 */ -} CRC_t; - -/* Reset */ -typedef enum CRC_RESET_enum -{ - CRC_RESET_NO_gc = (0x00<<6), /* No Reset */ - CRC_RESET_RESET0_gc = (0x02<<6), /* Reset CRC with CHECKSUM to all zeros */ - CRC_RESET_RESET1_gc = (0x03<<6), /* Reset CRC with CHECKSUM to all ones */ -} CRC_RESET_t; - -/* Input Source */ -typedef enum CRC_SOURCE_enum -{ - CRC_SOURCE_DISABLE_gc = (0x00<<0), /* Disabled */ - CRC_SOURCE_IO_gc = (0x01<<0), /* I/O Interface */ - CRC_SOURCE_FLASH_gc = (0x02<<0), /* Flash */ -} CRC_SOURCE_t; - - -/* --------------------------------------------------------------------------- -EVSYS - Event System --------------------------------------------------------------------------- -*/ - -/* Event System */ -typedef struct EVSYS_struct -{ - register8_t CH0MUX; /* Event Channel 0 Multiplexer */ - register8_t CH1MUX; /* Event Channel 1 Multiplexer */ - register8_t CH2MUX; /* Event Channel 2 Multiplexer */ - register8_t CH3MUX; /* Event Channel 3 Multiplexer */ - register8_t reserved_0x04; - register8_t reserved_0x05; - register8_t reserved_0x06; - register8_t reserved_0x07; - register8_t CH0CTRL; /* Channel 0 Control Register */ - register8_t CH1CTRL; /* Channel 1 Control Register */ - register8_t CH2CTRL; /* Channel 2 Control Register */ - register8_t CH3CTRL; /* Channel 3 Control Register */ - register8_t reserved_0x0C; - register8_t reserved_0x0D; - register8_t reserved_0x0E; - register8_t reserved_0x0F; - register8_t STROBE; /* Event Strobe */ - register8_t DATA; /* Event Data */ -} EVSYS_t; - -/* Quadrature Decoder Index Recognition Mode */ -typedef enum EVSYS_QDIRM_enum -{ - EVSYS_QDIRM_00_gc = (0x00<<5), /* QDPH0 = 0, QDPH90 = 0 */ - EVSYS_QDIRM_01_gc = (0x01<<5), /* QDPH0 = 0, QDPH90 = 1 */ - EVSYS_QDIRM_10_gc = (0x02<<5), /* QDPH0 = 1, QDPH90 = 0 */ - EVSYS_QDIRM_11_gc = (0x03<<5), /* QDPH0 = 1, QDPH90 = 1 */ -} EVSYS_QDIRM_t; - -/* Digital filter coefficient */ -typedef enum EVSYS_DIGFILT_enum -{ - EVSYS_DIGFILT_1SAMPLE_gc = (0x00<<0), /* 1 SAMPLE */ - EVSYS_DIGFILT_2SAMPLES_gc = (0x01<<0), /* 2 SAMPLES */ - EVSYS_DIGFILT_3SAMPLES_gc = (0x02<<0), /* 3 SAMPLES */ - EVSYS_DIGFILT_4SAMPLES_gc = (0x03<<0), /* 4 SAMPLES */ - EVSYS_DIGFILT_5SAMPLES_gc = (0x04<<0), /* 5 SAMPLES */ - EVSYS_DIGFILT_6SAMPLES_gc = (0x05<<0), /* 6 SAMPLES */ - EVSYS_DIGFILT_7SAMPLES_gc = (0x06<<0), /* 7 SAMPLES */ - EVSYS_DIGFILT_8SAMPLES_gc = (0x07<<0), /* 8 SAMPLES */ -} EVSYS_DIGFILT_t; - -/* Event Channel multiplexer input selection */ -typedef enum EVSYS_CHMUX_enum -{ - EVSYS_CHMUX_OFF_gc = (0x00<<0), /* Off */ - EVSYS_CHMUX_RTC_OVF_gc = (0x08<<0), /* RTC Overflow */ - EVSYS_CHMUX_RTC_CMP_gc = (0x09<<0), /* RTC Compare Match */ - EVSYS_CHMUX_ACA_CH0_gc = (0x10<<0), /* Analog Comparator A Channel 0 */ - EVSYS_CHMUX_ACA_CH1_gc = (0x11<<0), /* Analog Comparator A Channel 1 */ - EVSYS_CHMUX_ACA_WIN_gc = (0x12<<0), /* Analog Comparator A Window */ - EVSYS_CHMUX_ADCA_CH0_gc = (0x20<<0), /* ADC A Channel 0 */ - EVSYS_CHMUX_PORTA_PIN0_gc = (0x50<<0), /* Port A, Pin0 */ - EVSYS_CHMUX_PORTA_PIN1_gc = (0x51<<0), /* Port A, Pin1 */ - EVSYS_CHMUX_PORTA_PIN2_gc = (0x52<<0), /* Port A, Pin2 */ - EVSYS_CHMUX_PORTA_PIN3_gc = (0x53<<0), /* Port A, Pin3 */ - EVSYS_CHMUX_PORTA_PIN4_gc = (0x54<<0), /* Port A, Pin4 */ - EVSYS_CHMUX_PORTA_PIN5_gc = (0x55<<0), /* Port A, Pin5 */ - EVSYS_CHMUX_PORTA_PIN6_gc = (0x56<<0), /* Port A, Pin6 */ - EVSYS_CHMUX_PORTA_PIN7_gc = (0x57<<0), /* Port A, Pin7 */ - EVSYS_CHMUX_PORTB_PIN0_gc = (0x58<<0), /* Port B, Pin0 */ - EVSYS_CHMUX_PORTB_PIN1_gc = (0x59<<0), /* Port B, Pin1 */ - EVSYS_CHMUX_PORTB_PIN2_gc = (0x5A<<0), /* Port B, Pin2 */ - EVSYS_CHMUX_PORTB_PIN3_gc = (0x5B<<0), /* Port B, Pin3 */ - EVSYS_CHMUX_PORTB_PIN4_gc = (0x5C<<0), /* Port B, Pin4 */ - EVSYS_CHMUX_PORTB_PIN5_gc = (0x5D<<0), /* Port B, Pin5 */ - EVSYS_CHMUX_PORTB_PIN6_gc = (0x5E<<0), /* Port B, Pin6 */ - EVSYS_CHMUX_PORTB_PIN7_gc = (0x5F<<0), /* Port B, Pin7 */ - EVSYS_CHMUX_PORTC_PIN0_gc = (0x60<<0), /* Port C, Pin0 */ - EVSYS_CHMUX_PORTC_PIN1_gc = (0x61<<0), /* Port C, Pin1 */ - EVSYS_CHMUX_PORTC_PIN2_gc = (0x62<<0), /* Port C, Pin2 */ - EVSYS_CHMUX_PORTC_PIN3_gc = (0x63<<0), /* Port C, Pin3 */ - EVSYS_CHMUX_PORTC_PIN4_gc = (0x64<<0), /* Port C, Pin4 */ - EVSYS_CHMUX_PORTC_PIN5_gc = (0x65<<0), /* Port C, Pin5 */ - EVSYS_CHMUX_PORTC_PIN6_gc = (0x66<<0), /* Port C, Pin6 */ - EVSYS_CHMUX_PORTC_PIN7_gc = (0x67<<0), /* Port C, Pin7 */ - EVSYS_CHMUX_PORTD_PIN0_gc = (0x68<<0), /* Port D, Pin0 */ - EVSYS_CHMUX_PORTD_PIN1_gc = (0x69<<0), /* Port D, Pin1 */ - EVSYS_CHMUX_PORTD_PIN2_gc = (0x6A<<0), /* Port D, Pin2 */ - EVSYS_CHMUX_PORTD_PIN3_gc = (0x6B<<0), /* Port D, Pin3 */ - EVSYS_CHMUX_PORTD_PIN4_gc = (0x6C<<0), /* Port D, Pin4 */ - EVSYS_CHMUX_PORTD_PIN5_gc = (0x6D<<0), /* Port D, Pin5 */ - EVSYS_CHMUX_PORTD_PIN6_gc = (0x6E<<0), /* Port D, Pin6 */ - EVSYS_CHMUX_PORTD_PIN7_gc = (0x6F<<0), /* Port D, Pin7 */ - EVSYS_CHMUX_PORTE_PIN0_gc = (0x70<<0), /* Port E, Pin0 */ - EVSYS_CHMUX_PORTE_PIN1_gc = (0x71<<0), /* Port E, Pin1 */ - EVSYS_CHMUX_PORTE_PIN2_gc = (0x72<<0), /* Port E, Pin2 */ - EVSYS_CHMUX_PORTE_PIN3_gc = (0x73<<0), /* Port E, Pin3 */ - EVSYS_CHMUX_PORTE_PIN4_gc = (0x74<<0), /* Port E, Pin4 */ - EVSYS_CHMUX_PORTE_PIN5_gc = (0x75<<0), /* Port E, Pin5 */ - EVSYS_CHMUX_PORTE_PIN6_gc = (0x76<<0), /* Port E, Pin6 */ - EVSYS_CHMUX_PORTE_PIN7_gc = (0x77<<0), /* Port E, Pin7 */ - EVSYS_CHMUX_PORTF_PIN0_gc = (0x78<<0), /* Port F, Pin0 */ - EVSYS_CHMUX_PORTF_PIN1_gc = (0x79<<0), /* Port F, Pin1 */ - EVSYS_CHMUX_PORTF_PIN2_gc = (0x7A<<0), /* Port F, Pin2 */ - EVSYS_CHMUX_PORTF_PIN3_gc = (0x7B<<0), /* Port F, Pin3 */ - EVSYS_CHMUX_PORTF_PIN4_gc = (0x7C<<0), /* Port F, Pin4 */ - EVSYS_CHMUX_PORTF_PIN5_gc = (0x7D<<0), /* Port F, Pin5 */ - EVSYS_CHMUX_PORTF_PIN6_gc = (0x7E<<0), /* Port F, Pin6 */ - EVSYS_CHMUX_PORTF_PIN7_gc = (0x7F<<0), /* Port F, Pin7 */ - EVSYS_CHMUX_PRESCALER_1_gc = (0x80<<0), /* Prescaler, divide by 1 */ - EVSYS_CHMUX_PRESCALER_2_gc = (0x81<<0), /* Prescaler, divide by 2 */ - EVSYS_CHMUX_PRESCALER_4_gc = (0x82<<0), /* Prescaler, divide by 4 */ - EVSYS_CHMUX_PRESCALER_8_gc = (0x83<<0), /* Prescaler, divide by 8 */ - EVSYS_CHMUX_PRESCALER_16_gc = (0x84<<0), /* Prescaler, divide by 16 */ - EVSYS_CHMUX_PRESCALER_32_gc = (0x85<<0), /* Prescaler, divide by 32 */ - EVSYS_CHMUX_PRESCALER_64_gc = (0x86<<0), /* Prescaler, divide by 64 */ - EVSYS_CHMUX_PRESCALER_128_gc = (0x87<<0), /* Prescaler, divide by 128 */ - EVSYS_CHMUX_PRESCALER_256_gc = (0x88<<0), /* Prescaler, divide by 256 */ - EVSYS_CHMUX_PRESCALER_512_gc = (0x89<<0), /* Prescaler, divide by 512 */ - EVSYS_CHMUX_PRESCALER_1024_gc = (0x8A<<0), /* Prescaler, divide by 1024 */ - EVSYS_CHMUX_PRESCALER_2048_gc = (0x8B<<0), /* Prescaler, divide by 2048 */ - EVSYS_CHMUX_PRESCALER_4096_gc = (0x8C<<0), /* Prescaler, divide by 4096 */ - EVSYS_CHMUX_PRESCALER_8192_gc = (0x8D<<0), /* Prescaler, divide by 8192 */ - EVSYS_CHMUX_PRESCALER_16384_gc = (0x8E<<0), /* Prescaler, divide by 16384 */ - EVSYS_CHMUX_PRESCALER_32768_gc = (0x8F<<0), /* Prescaler, divide by 32768 */ - EVSYS_CHMUX_TCC0_OVF_gc = (0xC0<<0), /* Timer/Counter C0 Overflow */ - EVSYS_CHMUX_TCC0_ERR_gc = (0xC1<<0), /* Timer/Counter C0 Error */ - EVSYS_CHMUX_TCC0_CCA_gc = (0xC4<<0), /* Timer/Counter C0 Compare or Capture A */ - EVSYS_CHMUX_TCC0_CCB_gc = (0xC5<<0), /* Timer/Counter C0 Compare or Capture B */ - EVSYS_CHMUX_TCC0_CCC_gc = (0xC6<<0), /* Timer/Counter C0 Compare or Capture C */ - EVSYS_CHMUX_TCC0_CCD_gc = (0xC7<<0), /* Timer/Counter C0 Compare or Capture D */ - EVSYS_CHMUX_TCC1_OVF_gc = (0xC8<<0), /* Timer/Counter C1 Overflow */ - EVSYS_CHMUX_TCC1_ERR_gc = (0xC9<<0), /* Timer/Counter C1 Error */ - EVSYS_CHMUX_TCC1_CCA_gc = (0xCC<<0), /* Timer/Counter C1 Compare or Capture A */ - EVSYS_CHMUX_TCC1_CCB_gc = (0xCD<<0), /* Timer/Counter C1 Compare or Capture B */ - EVSYS_CHMUX_TCD0_OVF_gc = (0xD0<<0), /* Timer/Counter D0 Overflow */ - EVSYS_CHMUX_TCD0_ERR_gc = (0xD1<<0), /* Timer/Counter D0 Error */ - EVSYS_CHMUX_TCD0_CCA_gc = (0xD4<<0), /* Timer/Counter D0 Compare or Capture A */ - EVSYS_CHMUX_TCD0_CCB_gc = (0xD5<<0), /* Timer/Counter D0 Compare or Capture B */ - EVSYS_CHMUX_TCD0_CCC_gc = (0xD6<<0), /* Timer/Counter D0 Compare or Capture C */ - EVSYS_CHMUX_TCD0_CCD_gc = (0xD7<<0), /* Timer/Counter D0 Compare or Capture D */ - EVSYS_CHMUX_TCE0_OVF_gc = (0xE0<<0), /* Timer/Counter E0 Overflow */ - EVSYS_CHMUX_TCE0_ERR_gc = (0xE1<<0), /* Timer/Counter E0 Error */ - EVSYS_CHMUX_TCE0_CCA_gc = (0xE4<<0), /* Timer/Counter E0 Compare or Capture A */ - EVSYS_CHMUX_TCE0_CCB_gc = (0xE5<<0), /* Timer/Counter E0 Compare or Capture B */ - EVSYS_CHMUX_TCE0_CCC_gc = (0xE6<<0), /* Timer/Counter E0 Compare or Capture C */ - EVSYS_CHMUX_TCE0_CCD_gc = (0xE7<<0), /* Timer/Counter E0 Compare or Capture D */ - EVSYS_CHMUX_TCF0_OVF_gc = (0xF0<<0), /* Timer/Counter F0 Overflow */ - EVSYS_CHMUX_TCF0_ERR_gc = (0xF1<<0), /* Timer/Counter F0 Error */ - EVSYS_CHMUX_TCF0_CCA_gc = (0xF4<<0), /* Timer/Counter F0 Compare or Capture A */ - EVSYS_CHMUX_TCF0_CCB_gc = (0xF5<<0), /* Timer/Counter F0 Compare or Capture B */ - EVSYS_CHMUX_TCF0_CCC_gc = (0xF6<<0), /* Timer/Counter F0 Compare or Capture C */ - EVSYS_CHMUX_TCF0_CCD_gc = (0xF7<<0), /* Timer/Counter F0 Compare or Capture D */ -} EVSYS_CHMUX_t; - - -/* --------------------------------------------------------------------------- -NVM - Non Volatile Memory Controller --------------------------------------------------------------------------- -*/ - -/* Non-volatile Memory Controller */ -typedef struct NVM_struct -{ - register8_t ADDR0; /* Address Register 0 */ - register8_t ADDR1; /* Address Register 1 */ - register8_t ADDR2; /* Address Register 2 */ - register8_t reserved_0x03; - register8_t DATA0; /* Data Register 0 */ - register8_t DATA1; /* Data Register 1 */ - register8_t DATA2; /* Data Register 2 */ - register8_t reserved_0x07; - register8_t reserved_0x08; - register8_t reserved_0x09; - register8_t CMD; /* Command */ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t INTCTRL; /* Interrupt Control */ - register8_t reserved_0x0E; - register8_t STATUS; /* Status */ - register8_t LOCK_BITS; /* Lock Bits (Changed from LOCKBITS to avoid avr-libc collision) */ -} NVM_t; - -/* NVM Command */ -typedef enum NVM_CMD_enum -{ - NVM_CMD_NO_OPERATION_gc = (0x00<<0), /* Noop/Ordinary LPM */ - NVM_CMD_READ_USER_SIG_ROW_gc = (0x01<<0), /* Read user signature row */ - NVM_CMD_READ_CALIB_ROW_gc = (0x02<<0), /* Read calibration row */ - NVM_CMD_READ_EEPROM_gc = (0x06<<0), /* Read EEPROM */ - NVM_CMD_READ_FUSES_gc = (0x07<<0), /* Read fuse byte */ - NVM_CMD_WRITE_LOCK_BITS_gc = (0x08<<0), /* Write lock bits */ - NVM_CMD_ERASE_USER_SIG_ROW_gc = (0x18<<0), /* Erase user signature row */ - NVM_CMD_WRITE_USER_SIG_ROW_gc = (0x1A<<0), /* Write user signature row */ - NVM_CMD_ERASE_APP_gc = (0x20<<0), /* Erase Application Section */ - NVM_CMD_ERASE_APP_PAGE_gc = (0x22<<0), /* Erase Application Section page */ - NVM_CMD_LOAD_FLASH_BUFFER_gc = (0x23<<0), /* Load Flash page buffer */ - NVM_CMD_WRITE_APP_PAGE_gc = (0x24<<0), /* Write Application Section page */ - NVM_CMD_ERASE_WRITE_APP_PAGE_gc = (0x25<<0), /* Erase-and-write Application Section page */ - NVM_CMD_ERASE_FLASH_BUFFER_gc = (0x26<<0), /* Erase/flush Flash page buffer */ - NVM_CMD_ERASE_BOOT_PAGE_gc = (0x2A<<0), /* Erase Boot Section page */ - NVM_CMD_ERASE_FLASH_PAGE_gc = (0x2B<<0), /* Erase Flash Page */ - NVM_CMD_WRITE_BOOT_PAGE_gc = (0x2C<<0), /* Write Boot Section page */ - NVM_CMD_ERASE_WRITE_BOOT_PAGE_gc = (0x2D<<0), /* Erase-and-write Boot Section page */ - NVM_CMD_WRITE_FLASH_PAGE_gc = (0x2E<<0), /* Write Flash Page */ - NVM_CMD_ERASE_WRITE_FLASH_PAGE_gc = (0x2F<<0), /* Erase-and-write Flash Page */ - NVM_CMD_ERASE_EEPROM_gc = (0x30<<0), /* Erase EEPROM */ - NVM_CMD_ERASE_EEPROM_PAGE_gc = (0x32<<0), /* Erase EEPROM page */ - NVM_CMD_LOAD_EEPROM_BUFFER_gc = (0x33<<0), /* Load EEPROM page buffer */ - NVM_CMD_WRITE_EEPROM_PAGE_gc = (0x34<<0), /* Write EEPROM page */ - NVM_CMD_ERASE_WRITE_EEPROM_PAGE_gc = (0x35<<0), /* Erase-and-write EEPROM page */ - NVM_CMD_ERASE_EEPROM_BUFFER_gc = (0x36<<0), /* Erase/flush EEPROM page buffer */ - NVM_CMD_APP_CRC_gc = (0x38<<0), /* Application section CRC */ - NVM_CMD_BOOT_CRC_gc = (0x39<<0), /* Boot Section CRC */ - NVM_CMD_FLASH_RANGE_CRC_gc = (0x3A<<0), /* Flash Range CRC */ - NVM_CMD_CHIP_ERASE_gc = (0x40<<0), /* Erase Chip */ - NVM_CMD_READ_NVM_gc = (0x43<<0), /* Read NVM */ - NVM_CMD_WRITE_FUSE_gc = (0x4C<<0), /* Write Fuse byte */ - NVM_CMD_ERASE_BOOT_gc = (0x68<<0), /* Erase Boot Section */ - NVM_CMD_FLASH_CRC_gc = (0x78<<0), /* Flash CRC */ -} NVM_CMD_t; - -/* SPM ready interrupt level */ -typedef enum NVM_SPMLVL_enum -{ - NVM_SPMLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ - NVM_SPMLVL_LO_gc = (0x01<<2), /* Low level */ - NVM_SPMLVL_MED_gc = (0x02<<2), /* Medium level */ - NVM_SPMLVL_HI_gc = (0x03<<2), /* High level */ -} NVM_SPMLVL_t; - -/* EEPROM ready interrupt level */ -typedef enum NVM_EELVL_enum -{ - NVM_EELVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ - NVM_EELVL_LO_gc = (0x01<<0), /* Low level */ - NVM_EELVL_MED_gc = (0x02<<0), /* Medium level */ - NVM_EELVL_HI_gc = (0x03<<0), /* High level */ -} NVM_EELVL_t; - -/* Boot lock bits - boot setcion */ -typedef enum NVM_BLBB_enum -{ - NVM_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ - NVM_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ - NVM_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ - NVM_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ -} NVM_BLBB_t; - -/* Boot lock bits - application section */ -typedef enum NVM_BLBA_enum -{ - NVM_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ - NVM_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ - NVM_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ - NVM_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ -} NVM_BLBA_t; - -/* Boot lock bits - application table section */ -typedef enum NVM_BLBAT_enum -{ - NVM_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ - NVM_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ - NVM_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ - NVM_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ -} NVM_BLBAT_t; - -/* Lock bits */ -typedef enum NVM_LB_enum -{ - NVM_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ - NVM_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ - NVM_LB_NOLOCK_gc = (0x03<<0), /* No locks */ -} NVM_LB_t; - - -/* --------------------------------------------------------------------------- -ADC - Analog/Digital Converter --------------------------------------------------------------------------- -*/ - -/* ADC Channel */ -typedef struct ADC_CH_struct -{ - register8_t CTRL; /* Control Register */ - register8_t MUXCTRL; /* MUX Control */ - register8_t INTCTRL; /* Channel Interrupt Control Register */ - register8_t INTFLAGS; /* Interrupt Flags */ - _WORDREGISTER(RES); /* Channel Result */ - register8_t SCAN; /* Input Channel Scan */ - register8_t reserved_0x07; -} ADC_CH_t; - - -/* Analog-to-Digital Converter */ -typedef struct ADC_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t REFCTRL; /* Reference Control */ - register8_t EVCTRL; /* Event Control */ - register8_t PRESCALER; /* Clock Prescaler */ - register8_t reserved_0x05; - register8_t INTFLAGS; /* Interrupt Flags */ - register8_t TEMP; /* Temporary Register */ - register8_t reserved_0x08; - register8_t reserved_0x09; - register8_t reserved_0x0A; - register8_t reserved_0x0B; - _WORDREGISTER(CAL); /* Calibration Value */ - register8_t reserved_0x0E; - register8_t reserved_0x0F; - _WORDREGISTER(CH0RES); /* Channel 0 Result */ - register8_t reserved_0x12; - register8_t reserved_0x13; - register8_t reserved_0x14; - register8_t reserved_0x15; - register8_t reserved_0x16; - register8_t reserved_0x17; - _WORDREGISTER(CMP); /* Compare Value */ - register8_t reserved_0x1A; - register8_t reserved_0x1B; - register8_t reserved_0x1C; - register8_t reserved_0x1D; - register8_t reserved_0x1E; - register8_t reserved_0x1F; - ADC_CH_t CH0; /* ADC Channel 0 */ -} ADC_t; - -/* Current Limitation */ -typedef enum ADC_CURRLIMIT_enum -{ - ADC_CURRLIMIT_NO_gc = (0x00<<5), /* No current limit, 300ksps max sampling rate */ - ADC_CURRLIMIT_LOW_gc = (0x01<<5), /* Low current limit, 250ksps max sampling rate */ - ADC_CURRLIMIT_MED_gc = (0x02<<5), /* Medium current limit, 150ksps max sampling rate */ - ADC_CURRLIMIT_HIGH_gc = (0x03<<5), /* High current limit, 50ksps max sampling rate */ -} ADC_CURRLIMIT_t; - -/* Positive input multiplexer selection */ -typedef enum ADC_CH_MUXPOS_enum -{ - ADC_CH_MUXPOS_PIN0_gc = (0x00<<3), /* Input pin 0 */ - ADC_CH_MUXPOS_PIN1_gc = (0x01<<3), /* Input pin 1 */ - ADC_CH_MUXPOS_PIN2_gc = (0x02<<3), /* Input pin 2 */ - ADC_CH_MUXPOS_PIN3_gc = (0x03<<3), /* Input pin 3 */ - ADC_CH_MUXPOS_PIN4_gc = (0x04<<3), /* Input pin 4 */ - ADC_CH_MUXPOS_PIN5_gc = (0x05<<3), /* Input pin 5 */ - ADC_CH_MUXPOS_PIN6_gc = (0x06<<3), /* Input pin 6 */ - ADC_CH_MUXPOS_PIN7_gc = (0x07<<3), /* Input pin 7 */ - ADC_CH_MUXPOS_PIN8_gc = (0x08<<3), /* Input pin 8 */ - ADC_CH_MUXPOS_PIN9_gc = (0x09<<3), /* Input pin 9 */ - ADC_CH_MUXPOS_PIN10_gc = (0x0A<<3), /* Input pin 10 */ - ADC_CH_MUXPOS_PIN11_gc = (0x0B<<3), /* Input pin 11 */ -} ADC_CH_MUXPOS_t; - -/* Internal input multiplexer selections */ -typedef enum ADC_CH_MUXINT_enum -{ - ADC_CH_MUXINT_TEMP_gc = (0x00<<3), /* Temperature Reference */ - ADC_CH_MUXINT_BANDGAP_gc = (0x01<<3), /* Bandgap Reference */ - ADC_CH_MUXINT_SCALEDVCC_gc = (0x02<<3), /* 1/10 scaled VCC */ -} ADC_CH_MUXINT_t; - -/* Negative input multiplexer selection */ -typedef enum ADC_CH_MUXNEG_enum -{ - ADC_CH_MUXNEG_PIN0_gc = (0x00<<0), /* Input pin 0 */ - ADC_CH_MUXNEG_PIN1_gc = (0x01<<0), /* Input pin 1 */ - ADC_CH_MUXNEG_PIN2_gc = (0x02<<0), /* Input pin 2 */ - ADC_CH_MUXNEG_PIN3_gc = (0x03<<0), /* Input pin 3 */ - ADC_CH_MUXNEG_PIN4_gc = (0x00<<0), /* Input pin 4 */ - ADC_CH_MUXNEG_PIN5_gc = (0x01<<0), /* Input pin 5 */ - ADC_CH_MUXNEG_PIN6_gc = (0x02<<0), /* Input pin 6 */ - ADC_CH_MUXNEG_PIN7_gc = (0x03<<0), /* Input pin 7 */ -} ADC_CH_MUXNEG_t; - -/* Input mode */ -typedef enum ADC_CH_INPUTMODE_enum -{ - ADC_CH_INPUTMODE_INTERNAL_gc = (0x00<<0), /* Internal inputs, no gain */ - ADC_CH_INPUTMODE_SINGLEENDED_gc = (0x01<<0), /* Single-ended input, no gain */ - ADC_CH_INPUTMODE_DIFF_gc = (0x02<<0), /* Differential input, no gain */ - ADC_CH_INPUTMODE_DIFFWGAIN_gc = (0x03<<0), /* Differential input, with gain */ -} ADC_CH_INPUTMODE_t; - -/* Gain factor */ -typedef enum ADC_CH_GAIN_enum -{ - ADC_CH_GAIN_1X_gc = (0x00<<2), /* 1x gain */ - ADC_CH_GAIN_2X_gc = (0x01<<2), /* 2x gain */ - ADC_CH_GAIN_4X_gc = (0x02<<2), /* 4x gain */ - ADC_CH_GAIN_8X_gc = (0x03<<2), /* 8x gain */ - ADC_CH_GAIN_16X_gc = (0x04<<2), /* 16x gain */ - ADC_CH_GAIN_32X_gc = (0x05<<2), /* 32x gain */ - ADC_CH_GAIN_64X_gc = (0x06<<2), /* 64x gain */ - ADC_CH_GAIN_DIV2_gc = (0x07<<2), /* x/2 gain */ -} ADC_CH_GAIN_t; - -/* Conversion result resolution */ -typedef enum ADC_RESOLUTION_enum -{ - ADC_RESOLUTION_12BIT_gc = (0x00<<1), /* 12-bit right-adjusted result */ - ADC_RESOLUTION_8BIT_gc = (0x02<<1), /* 8-bit right-adjusted result */ - ADC_RESOLUTION_LEFT12BIT_gc = (0x03<<1), /* 12-bit left-adjusted result */ -} ADC_RESOLUTION_t; - -/* Voltage reference selection */ -typedef enum ADC_REFSEL_enum -{ - ADC_REFSEL_INT1V_gc = (0x00<<4), /* Internal 1V */ - ADC_REFSEL_INTVCC_gc = (0x01<<4), /* Internal VCC / 1.6 */ - ADC_REFSEL_AREFA_gc = (0x02<<4), /* External reference on PORT A */ - ADC_REFSEL_AREFB_gc = (0x03<<4), /* External reference on PORT B */ - ADC_REFSEL_INTVCC2_gc = (0x04<<4), /* Internal VCC / 2 */ -} ADC_REFSEL_t; - -/* Event channel input selection */ -typedef enum ADC_EVSEL_enum -{ - ADC_EVSEL_0_gc = (0x00<<3), /* Event Channel 0 */ - ADC_EVSEL_1_gc = (0x01<<3), /* Event Channel 1 */ - ADC_EVSEL_2_gc = (0x02<<3), /* Event Channel 2 */ - ADC_EVSEL_3_gc = (0x03<<3), /* Event Channel 3 */ -} ADC_EVSEL_t; - -/* Event action selection */ -typedef enum ADC_EVACT_enum -{ - ADC_EVACT_NONE_gc = (0x00<<0), /* No event action */ - ADC_EVACT_CH0_gc = (0x01<<0), /* First event triggers channel 0 */ - ADC_EVACT_SYNCSWEEP_gc = (0x06<<0), /* The ADC is flushed and restarted for accurate timing */ -} ADC_EVACT_t; - -/* Interupt mode */ -typedef enum ADC_CH_INTMODE_enum -{ - ADC_CH_INTMODE_COMPLETE_gc = (0x00<<2), /* Interrupt on conversion complete */ - ADC_CH_INTMODE_BELOW_gc = (0x01<<2), /* Interrupt on result below compare value */ - ADC_CH_INTMODE_ABOVE_gc = (0x03<<2), /* Interrupt on result above compare value */ -} ADC_CH_INTMODE_t; - -/* Interrupt level */ -typedef enum ADC_CH_INTLVL_enum -{ - ADC_CH_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ - ADC_CH_INTLVL_LO_gc = (0x01<<0), /* Low level */ - ADC_CH_INTLVL_MED_gc = (0x02<<0), /* Medium level */ - ADC_CH_INTLVL_HI_gc = (0x03<<0), /* High level */ -} ADC_CH_INTLVL_t; - -/* Clock prescaler */ -typedef enum ADC_PRESCALER_enum -{ - ADC_PRESCALER_DIV4_gc = (0x00<<0), /* Divide clock by 4 */ - ADC_PRESCALER_DIV8_gc = (0x01<<0), /* Divide clock by 8 */ - ADC_PRESCALER_DIV16_gc = (0x02<<0), /* Divide clock by 16 */ - ADC_PRESCALER_DIV32_gc = (0x03<<0), /* Divide clock by 32 */ - ADC_PRESCALER_DIV64_gc = (0x04<<0), /* Divide clock by 64 */ - ADC_PRESCALER_DIV128_gc = (0x05<<0), /* Divide clock by 128 */ - ADC_PRESCALER_DIV256_gc = (0x06<<0), /* Divide clock by 256 */ - ADC_PRESCALER_DIV512_gc = (0x07<<0), /* Divide clock by 512 */ -} ADC_PRESCALER_t; - - -/* --------------------------------------------------------------------------- -AC - Analog Comparator --------------------------------------------------------------------------- -*/ - -/* Analog Comparator */ -typedef struct AC_struct -{ - register8_t AC0CTRL; /* Analog Comparator 0 Control */ - register8_t AC1CTRL; /* Analog Comparator 1 Control */ - register8_t AC0MUXCTRL; /* Analog Comparator 0 MUX Control */ - register8_t AC1MUXCTRL; /* Analog Comparator 1 MUX Control */ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t WINCTRL; /* Window Mode Control */ - register8_t STATUS; /* Status */ -} AC_t; - -/* Interrupt mode */ -typedef enum AC_INTMODE_enum -{ - AC_INTMODE_BOTHEDGES_gc = (0x00<<6), /* Interrupt on both edges */ - AC_INTMODE_FALLING_gc = (0x02<<6), /* Interrupt on falling edge */ - AC_INTMODE_RISING_gc = (0x03<<6), /* Interrupt on rising edge */ -} AC_INTMODE_t; - -/* Interrupt level */ -typedef enum AC_INTLVL_enum -{ - AC_INTLVL_OFF_gc = (0x00<<4), /* Interrupt disabled */ - AC_INTLVL_LO_gc = (0x01<<4), /* Low level */ - AC_INTLVL_MED_gc = (0x02<<4), /* Medium level */ - AC_INTLVL_HI_gc = (0x03<<4), /* High level */ -} AC_INTLVL_t; - -/* Hysteresis mode selection */ -typedef enum AC_HYSMODE_enum -{ - AC_HYSMODE_NO_gc = (0x00<<1), /* No hysteresis */ - AC_HYSMODE_SMALL_gc = (0x01<<1), /* Small hysteresis */ - AC_HYSMODE_LARGE_gc = (0x02<<1), /* Large hysteresis */ -} AC_HYSMODE_t; - -/* Positive input multiplexer selection */ -typedef enum AC_MUXPOS_enum -{ - AC_MUXPOS_PIN0_gc = (0x00<<3), /* Pin 0 */ - AC_MUXPOS_PIN1_gc = (0x01<<3), /* Pin 1 */ - AC_MUXPOS_PIN2_gc = (0x02<<3), /* Pin 2 */ - AC_MUXPOS_PIN3_gc = (0x03<<3), /* Pin 3 */ - AC_MUXPOS_PIN4_gc = (0x04<<3), /* Pin 4 */ - AC_MUXPOS_PIN5_gc = (0x05<<3), /* Pin 5 */ - AC_MUXPOS_PIN6_gc = (0x06<<3), /* Pin 6 */ -} AC_MUXPOS_t; - -/* Negative input multiplexer selection */ -typedef enum AC_MUXNEG_enum -{ - AC_MUXNEG_PIN0_gc = (0x00<<0), /* Pin 0 */ - AC_MUXNEG_PIN1_gc = (0x01<<0), /* Pin 1 */ - AC_MUXNEG_PIN3_gc = (0x02<<0), /* Pin 3 */ - AC_MUXNEG_PIN5_gc = (0x03<<0), /* Pin 5 */ - AC_MUXNEG_PIN7_gc = (0x04<<0), /* Pin 7 */ - AC_MUXNEG_BANDGAP_gc = (0x06<<0), /* Bandgap Reference */ - AC_MUXNEG_SCALER_gc = (0x07<<0), /* Internal voltage scaler */ -} AC_MUXNEG_t; - -/* Windows interrupt mode */ -typedef enum AC_WINTMODE_enum -{ - AC_WINTMODE_ABOVE_gc = (0x00<<2), /* Interrupt on above window */ - AC_WINTMODE_INSIDE_gc = (0x01<<2), /* Interrupt on inside window */ - AC_WINTMODE_BELOW_gc = (0x02<<2), /* Interrupt on below window */ - AC_WINTMODE_OUTSIDE_gc = (0x03<<2), /* Interrupt on outside window */ -} AC_WINTMODE_t; - -/* Window interrupt level */ -typedef enum AC_WINTLVL_enum -{ - AC_WINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ - AC_WINTLVL_LO_gc = (0x01<<0), /* Low priority */ - AC_WINTLVL_MED_gc = (0x02<<0), /* Medium priority */ - AC_WINTLVL_HI_gc = (0x03<<0), /* High priority */ -} AC_WINTLVL_t; - -/* Window mode state */ -typedef enum AC_WSTATE_enum -{ - AC_WSTATE_ABOVE_gc = (0x00<<6), /* Signal above window */ - AC_WSTATE_INSIDE_gc = (0x01<<6), /* Signal inside window */ - AC_WSTATE_BELOW_gc = (0x02<<6), /* Signal below window */ -} AC_WSTATE_t; - - -/* --------------------------------------------------------------------------- -RTC - Real-Time Counter --------------------------------------------------------------------------- -*/ - -/* Real-Time Counter */ -typedef struct RTC_struct -{ - register8_t CTRL; /* Control Register */ - register8_t STATUS; /* Status Register */ - register8_t INTCTRL; /* Interrupt Control Register */ - register8_t INTFLAGS; /* Interrupt Flags */ - register8_t TEMP; /* Temporary register */ - register8_t reserved_0x05; - register8_t reserved_0x06; - register8_t reserved_0x07; - _WORDREGISTER(CNT); /* Count Register */ - _WORDREGISTER(PER); /* Period Register */ - _WORDREGISTER(COMP); /* Compare Register */ -} RTC_t; - -/* Prescaler Factor */ -typedef enum RTC_PRESCALER_enum -{ - RTC_PRESCALER_OFF_gc = (0x00<<0), /* RTC Off */ - RTC_PRESCALER_DIV1_gc = (0x01<<0), /* RTC Clock */ - RTC_PRESCALER_DIV2_gc = (0x02<<0), /* RTC Clock / 2 */ - RTC_PRESCALER_DIV8_gc = (0x03<<0), /* RTC Clock / 8 */ - RTC_PRESCALER_DIV16_gc = (0x04<<0), /* RTC Clock / 16 */ - RTC_PRESCALER_DIV64_gc = (0x05<<0), /* RTC Clock / 64 */ - RTC_PRESCALER_DIV256_gc = (0x06<<0), /* RTC Clock / 256 */ - RTC_PRESCALER_DIV1024_gc = (0x07<<0), /* RTC Clock / 1024 */ -} RTC_PRESCALER_t; - -/* Compare Interrupt level */ -typedef enum RTC_COMPINTLVL_enum -{ - RTC_COMPINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ - RTC_COMPINTLVL_LO_gc = (0x01<<2), /* Low Level */ - RTC_COMPINTLVL_MED_gc = (0x02<<2), /* Medium Level */ - RTC_COMPINTLVL_HI_gc = (0x03<<2), /* High Level */ -} RTC_COMPINTLVL_t; - -/* Overflow Interrupt level */ -typedef enum RTC_OVFINTLVL_enum -{ - RTC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - RTC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ - RTC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ - RTC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ -} RTC_OVFINTLVL_t; - - -/* --------------------------------------------------------------------------- -TWI - Two-Wire Interface --------------------------------------------------------------------------- -*/ - -/* */ -typedef struct TWI_MASTER_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t CTRLC; /* Control Register C */ - register8_t STATUS; /* Status Register */ - register8_t BAUD; /* Baurd Rate Control Register */ - register8_t ADDR; /* Address Register */ - register8_t DATA; /* Data Register */ -} TWI_MASTER_t; - - -/* */ -typedef struct TWI_SLAVE_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t STATUS; /* Status Register */ - register8_t ADDR; /* Address Register */ - register8_t DATA; /* Data Register */ - register8_t ADDRMASK; /* Address Mask Register */ -} TWI_SLAVE_t; - - -/* Two-Wire Interface */ -typedef struct TWI_struct -{ - register8_t CTRL; /* TWI Common Control Register */ - TWI_MASTER_t MASTER; /* TWI master module */ - TWI_SLAVE_t SLAVE; /* TWI slave module */ -} TWI_t; - -/* SDA Hold Time */ -typedef enum TWI_SDAHOLD_enum -{ - TWI_SDAHOLD_OFF_gc = (0x00<<1), /* SDA Hold Time off */ - TWI_SDAHOLD_50NS_gc = (0x01<<1), /* SDA Hold Time 50 ns */ - TWI_SDAHOLD_300NS_gc = (0x02<<1), /* SDA Hold Time 300 ns */ - TWI_SDAHOLD_400NS_gc = (0x03<<1), /* SDA Hold Time 400 ns */ -} TWI_SDAHOLD_t; - -/* Master Interrupt Level */ -typedef enum TWI_MASTER_INTLVL_enum -{ - TWI_MASTER_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ - TWI_MASTER_INTLVL_LO_gc = (0x01<<6), /* Low Level */ - TWI_MASTER_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ - TWI_MASTER_INTLVL_HI_gc = (0x03<<6), /* High Level */ -} TWI_MASTER_INTLVL_t; - -/* Inactive Timeout */ -typedef enum TWI_MASTER_TIMEOUT_enum -{ - TWI_MASTER_TIMEOUT_DISABLED_gc = (0x00<<2), /* Bus Timeout Disabled */ - TWI_MASTER_TIMEOUT_50US_gc = (0x01<<2), /* 50 Microseconds */ - TWI_MASTER_TIMEOUT_100US_gc = (0x02<<2), /* 100 Microseconds */ - TWI_MASTER_TIMEOUT_200US_gc = (0x03<<2), /* 200 Microseconds */ -} TWI_MASTER_TIMEOUT_t; - -/* Master Command */ -typedef enum TWI_MASTER_CMD_enum -{ - TWI_MASTER_CMD_NOACT_gc = (0x00<<0), /* No Action */ - TWI_MASTER_CMD_REPSTART_gc = (0x01<<0), /* Issue Repeated Start Condition */ - TWI_MASTER_CMD_RECVTRANS_gc = (0x02<<0), /* Receive or Transmit Data */ - TWI_MASTER_CMD_STOP_gc = (0x03<<0), /* Issue Stop Condition */ -} TWI_MASTER_CMD_t; - -/* Master Bus State */ -typedef enum TWI_MASTER_BUSSTATE_enum -{ - TWI_MASTER_BUSSTATE_UNKNOWN_gc = (0x00<<0), /* Unknown Bus State */ - TWI_MASTER_BUSSTATE_IDLE_gc = (0x01<<0), /* Bus is Idle */ - TWI_MASTER_BUSSTATE_OWNER_gc = (0x02<<0), /* This Module Controls The Bus */ - TWI_MASTER_BUSSTATE_BUSY_gc = (0x03<<0), /* The Bus is Busy */ -} TWI_MASTER_BUSSTATE_t; - -/* Slave Interrupt Level */ -typedef enum TWI_SLAVE_INTLVL_enum -{ - TWI_SLAVE_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ - TWI_SLAVE_INTLVL_LO_gc = (0x01<<6), /* Low Level */ - TWI_SLAVE_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ - TWI_SLAVE_INTLVL_HI_gc = (0x03<<6), /* High Level */ -} TWI_SLAVE_INTLVL_t; - -/* Slave Command */ -typedef enum TWI_SLAVE_CMD_enum -{ - TWI_SLAVE_CMD_NOACT_gc = (0x00<<0), /* No Action */ - TWI_SLAVE_CMD_COMPTRANS_gc = (0x02<<0), /* Used To Complete a Transaction */ - TWI_SLAVE_CMD_RESPONSE_gc = (0x03<<0), /* Used in Response to Address/Data Interrupt */ -} TWI_SLAVE_CMD_t; - - -/* --------------------------------------------------------------------------- -PORT - I/O Port Configuration --------------------------------------------------------------------------- -*/ - -/* I/O Ports */ -typedef struct PORT_struct -{ - register8_t DIR; /* I/O Port Data Direction */ - register8_t DIRSET; /* I/O Port Data Direction Set */ - register8_t DIRCLR; /* I/O Port Data Direction Clear */ - register8_t DIRTGL; /* I/O Port Data Direction Toggle */ - register8_t OUT; /* I/O Port Output */ - register8_t OUTSET; /* I/O Port Output Set */ - register8_t OUTCLR; /* I/O Port Output Clear */ - register8_t OUTTGL; /* I/O Port Output Toggle */ - register8_t IN; /* I/O port Input */ - register8_t INTCTRL; /* Interrupt Control Register */ - register8_t INT0MASK; /* Port Interrupt 0 Mask */ - register8_t INT1MASK; /* Port Interrupt 1 Mask */ - register8_t INTFLAGS; /* Interrupt Flag Register */ - register8_t reserved_0x0D; - register8_t REMAP; /* I/O Port Pin Remap Register */ - register8_t reserved_0x0F; - register8_t PIN0CTRL; /* Pin 0 Control Register */ - register8_t PIN1CTRL; /* Pin 1 Control Register */ - register8_t PIN2CTRL; /* Pin 2 Control Register */ - register8_t PIN3CTRL; /* Pin 3 Control Register */ - register8_t PIN4CTRL; /* Pin 4 Control Register */ - register8_t PIN5CTRL; /* Pin 5 Control Register */ - register8_t PIN6CTRL; /* Pin 6 Control Register */ - register8_t PIN7CTRL; /* Pin 7 Control Register */ -} PORT_t; - -/* Port Interrupt 0 Level */ -typedef enum PORT_INT0LVL_enum -{ - PORT_INT0LVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - PORT_INT0LVL_LO_gc = (0x01<<0), /* Low Level */ - PORT_INT0LVL_MED_gc = (0x02<<0), /* Medium Level */ - PORT_INT0LVL_HI_gc = (0x03<<0), /* High Level */ -} PORT_INT0LVL_t; - -/* Port Interrupt 1 Level */ -typedef enum PORT_INT1LVL_enum -{ - PORT_INT1LVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ - PORT_INT1LVL_LO_gc = (0x01<<2), /* Low Level */ - PORT_INT1LVL_MED_gc = (0x02<<2), /* Medium Level */ - PORT_INT1LVL_HI_gc = (0x03<<2), /* High Level */ -} PORT_INT1LVL_t; - -/* Output/Pull Configuration */ -typedef enum PORT_OPC_enum -{ - PORT_OPC_TOTEM_gc = (0x00<<3), /* Totempole */ - PORT_OPC_BUSKEEPER_gc = (0x01<<3), /* Totempole w/ Bus keeper on Input and Output */ - PORT_OPC_PULLDOWN_gc = (0x02<<3), /* Totempole w/ Pull-down on Input */ - PORT_OPC_PULLUP_gc = (0x03<<3), /* Totempole w/ Pull-up on Input */ - PORT_OPC_WIREDOR_gc = (0x04<<3), /* Wired OR */ - PORT_OPC_WIREDAND_gc = (0x05<<3), /* Wired AND */ - PORT_OPC_WIREDORPULL_gc = (0x06<<3), /* Wired OR w/ Pull-down */ - PORT_OPC_WIREDANDPULL_gc = (0x07<<3), /* Wired AND w/ Pull-up */ -} PORT_OPC_t; - -/* Input/Sense Configuration */ -typedef enum PORT_ISC_enum -{ - PORT_ISC_BOTHEDGES_gc = (0x00<<0), /* Sense Both Edges */ - PORT_ISC_RISING_gc = (0x01<<0), /* Sense Rising Edge */ - PORT_ISC_FALLING_gc = (0x02<<0), /* Sense Falling Edge */ - PORT_ISC_LEVEL_gc = (0x03<<0), /* Sense Level (Transparent For Events) */ - PORT_ISC_INPUT_DISABLE_gc = (0x07<<0), /* Disable Digital Input Buffer */ -} PORT_ISC_t; - - -/* --------------------------------------------------------------------------- -TC - 16-bit Timer/Counter With PWM --------------------------------------------------------------------------- -*/ - -/* 16-bit Timer/Counter 0 */ -typedef struct TC0_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t CTRLC; /* Control register C */ - register8_t CTRLD; /* Control Register D */ - register8_t CTRLE; /* Control Register E */ - register8_t reserved_0x05; - register8_t INTCTRLA; /* Interrupt Control Register A */ - register8_t INTCTRLB; /* Interrupt Control Register B */ - register8_t CTRLFCLR; /* Control Register F Clear */ - register8_t CTRLFSET; /* Control Register F Set */ - register8_t CTRLGCLR; /* Control Register G Clear */ - register8_t CTRLGSET; /* Control Register G Set */ - register8_t INTFLAGS; /* Interrupt Flag Register */ - register8_t reserved_0x0D; - register8_t reserved_0x0E; - register8_t TEMP; /* Temporary Register For 16-bit Access */ - register8_t reserved_0x10; - register8_t reserved_0x11; - register8_t reserved_0x12; - register8_t reserved_0x13; - register8_t reserved_0x14; - register8_t reserved_0x15; - register8_t reserved_0x16; - register8_t reserved_0x17; - register8_t reserved_0x18; - register8_t reserved_0x19; - register8_t reserved_0x1A; - register8_t reserved_0x1B; - register8_t reserved_0x1C; - register8_t reserved_0x1D; - register8_t reserved_0x1E; - register8_t reserved_0x1F; - _WORDREGISTER(CNT); /* Count */ - register8_t reserved_0x22; - register8_t reserved_0x23; - register8_t reserved_0x24; - register8_t reserved_0x25; - _WORDREGISTER(PER); /* Period */ - _WORDREGISTER(CCA); /* Compare or Capture A */ - _WORDREGISTER(CCB); /* Compare or Capture B */ - _WORDREGISTER(CCC); /* Compare or Capture C */ - _WORDREGISTER(CCD); /* Compare or Capture D */ - register8_t reserved_0x30; - register8_t reserved_0x31; - register8_t reserved_0x32; - register8_t reserved_0x33; - register8_t reserved_0x34; - register8_t reserved_0x35; - _WORDREGISTER(PERBUF); /* Period Buffer */ - _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ - _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ - _WORDREGISTER(CCCBUF); /* Compare Or Capture C Buffer */ - _WORDREGISTER(CCDBUF); /* Compare Or Capture D Buffer */ -} TC0_t; - - -/* 16-bit Timer/Counter 1 */ -typedef struct TC1_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t CTRLC; /* Control register C */ - register8_t CTRLD; /* Control Register D */ - register8_t CTRLE; /* Control Register E */ - register8_t reserved_0x05; - register8_t INTCTRLA; /* Interrupt Control Register A */ - register8_t INTCTRLB; /* Interrupt Control Register B */ - register8_t CTRLFCLR; /* Control Register F Clear */ - register8_t CTRLFSET; /* Control Register F Set */ - register8_t CTRLGCLR; /* Control Register G Clear */ - register8_t CTRLGSET; /* Control Register G Set */ - register8_t INTFLAGS; /* Interrupt Flag Register */ - register8_t reserved_0x0D; - register8_t reserved_0x0E; - register8_t TEMP; /* Temporary Register For 16-bit Access */ - register8_t reserved_0x10; - register8_t reserved_0x11; - register8_t reserved_0x12; - register8_t reserved_0x13; - register8_t reserved_0x14; - register8_t reserved_0x15; - register8_t reserved_0x16; - register8_t reserved_0x17; - register8_t reserved_0x18; - register8_t reserved_0x19; - register8_t reserved_0x1A; - register8_t reserved_0x1B; - register8_t reserved_0x1C; - register8_t reserved_0x1D; - register8_t reserved_0x1E; - register8_t reserved_0x1F; - _WORDREGISTER(CNT); /* Count */ - register8_t reserved_0x22; - register8_t reserved_0x23; - register8_t reserved_0x24; - register8_t reserved_0x25; - _WORDREGISTER(PER); /* Period */ - _WORDREGISTER(CCA); /* Compare or Capture A */ - _WORDREGISTER(CCB); /* Compare or Capture B */ - register8_t reserved_0x2C; - register8_t reserved_0x2D; - register8_t reserved_0x2E; - register8_t reserved_0x2F; - register8_t reserved_0x30; - register8_t reserved_0x31; - register8_t reserved_0x32; - register8_t reserved_0x33; - register8_t reserved_0x34; - register8_t reserved_0x35; - _WORDREGISTER(PERBUF); /* Period Buffer */ - _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ - _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ -} TC1_t; - -/* Clock Selection */ -typedef enum TC_CLKSEL_enum -{ - TC_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */ - TC_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */ - TC_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */ - TC_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */ - TC_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */ - TC_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */ - TC_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */ - TC_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */ - TC_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */ - TC_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */ - TC_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */ - TC_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */ -} TC_CLKSEL_t; - -/* Waveform Generation Mode */ -typedef enum TC_WGMODE_enum -{ - TC_WGMODE_NORMAL_gc = (0x00<<0), /* Normal Mode */ - TC_WGMODE_FRQ_gc = (0x01<<0), /* Frequency Generation Mode */ - TC_WGMODE_SINGLESLOPE_gc = (0x03<<0), /* Single Slope */ - TC_WGMODE_SS_gc = (0x03<<0), /* Single Slope */ - TC_WGMODE_DSTOP_gc = (0x05<<0), /* Dual Slope, Update on TOP */ - TC_WGMODE_DS_T_gc = (0x05<<0), /* Dual Slope, Update on TOP */ - TC_WGMODE_DSBOTH_gc = (0x06<<0), /* Dual Slope, Update on both TOP and BOTTOM */ - TC_WGMODE_DS_TB_gc = (0x06<<0), /* Dual Slope, Update on both TOP and BOTTOM */ - TC_WGMODE_DSBOTTOM_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */ - TC_WGMODE_DS_B_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */ -} TC_WGMODE_t; - -/* Byte Mode */ -typedef enum TC_BYTEM_enum -{ - TC_BYTEM_NORMAL_gc = (0x00<<0), /* 16-bit mode */ - TC_BYTEM_BYTEMODE_gc = (0x01<<0), /* Timer/Counter operating in byte mode only */ - TC_BYTEM_SPLITMODE_gc = (0x02<<0), /* Timer/Counter split into two 8-bit Counters (TC2) */ -} TC_BYTEM_t; - -/* Event Action */ -typedef enum TC_EVACT_enum -{ - TC_EVACT_OFF_gc = (0x00<<5), /* No Event Action */ - TC_EVACT_CAPT_gc = (0x01<<5), /* Input Capture */ - TC_EVACT_UPDOWN_gc = (0x02<<5), /* Externally Controlled Up/Down Count */ - TC_EVACT_QDEC_gc = (0x03<<5), /* Quadrature Decode */ - TC_EVACT_RESTART_gc = (0x04<<5), /* Restart */ - TC_EVACT_FRQ_gc = (0x05<<5), /* Frequency Capture */ - TC_EVACT_PW_gc = (0x06<<5), /* Pulse-width Capture */ -} TC_EVACT_t; - -/* Event Selection */ -typedef enum TC_EVSEL_enum -{ - TC_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ - TC_EVSEL_CH0_gc = (0x08<<0), /* Event Channel 0 */ - TC_EVSEL_CH1_gc = (0x09<<0), /* Event Channel 1 */ - TC_EVSEL_CH2_gc = (0x0A<<0), /* Event Channel 2 */ - TC_EVSEL_CH3_gc = (0x0B<<0), /* Event Channel 3 */ -} TC_EVSEL_t; - -/* Error Interrupt Level */ -typedef enum TC_ERRINTLVL_enum -{ - TC_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ - TC_ERRINTLVL_LO_gc = (0x01<<2), /* Low Level */ - TC_ERRINTLVL_MED_gc = (0x02<<2), /* Medium Level */ - TC_ERRINTLVL_HI_gc = (0x03<<2), /* High Level */ -} TC_ERRINTLVL_t; - -/* Overflow Interrupt Level */ -typedef enum TC_OVFINTLVL_enum -{ - TC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - TC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ - TC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ - TC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ -} TC_OVFINTLVL_t; - -/* Compare or Capture D Interrupt Level */ -typedef enum TC_CCDINTLVL_enum -{ - TC_CCDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ - TC_CCDINTLVL_LO_gc = (0x01<<6), /* Low Level */ - TC_CCDINTLVL_MED_gc = (0x02<<6), /* Medium Level */ - TC_CCDINTLVL_HI_gc = (0x03<<6), /* High Level */ -} TC_CCDINTLVL_t; - -/* Compare or Capture C Interrupt Level */ -typedef enum TC_CCCINTLVL_enum -{ - TC_CCCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ - TC_CCCINTLVL_LO_gc = (0x01<<4), /* Low Level */ - TC_CCCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ - TC_CCCINTLVL_HI_gc = (0x03<<4), /* High Level */ -} TC_CCCINTLVL_t; - -/* Compare or Capture B Interrupt Level */ -typedef enum TC_CCBINTLVL_enum -{ - TC_CCBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ - TC_CCBINTLVL_LO_gc = (0x01<<2), /* Low Level */ - TC_CCBINTLVL_MED_gc = (0x02<<2), /* Medium Level */ - TC_CCBINTLVL_HI_gc = (0x03<<2), /* High Level */ -} TC_CCBINTLVL_t; - -/* Compare or Capture A Interrupt Level */ -typedef enum TC_CCAINTLVL_enum -{ - TC_CCAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - TC_CCAINTLVL_LO_gc = (0x01<<0), /* Low Level */ - TC_CCAINTLVL_MED_gc = (0x02<<0), /* Medium Level */ - TC_CCAINTLVL_HI_gc = (0x03<<0), /* High Level */ -} TC_CCAINTLVL_t; - -/* Timer/Counter Command */ -typedef enum TC_CMD_enum -{ - TC_CMD_NONE_gc = (0x00<<2), /* No Command */ - TC_CMD_UPDATE_gc = (0x01<<2), /* Force Update */ - TC_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ - TC_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ -} TC_CMD_t; - - -/* --------------------------------------------------------------------------- -TC2 - 16-bit Timer/Counter type 2 --------------------------------------------------------------------------- -*/ - -/* 16-bit Timer/Counter type 2 */ -typedef struct TC2_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t CTRLC; /* Control register C */ - register8_t reserved_0x03; - register8_t CTRLE; /* Control Register E */ - register8_t reserved_0x05; - register8_t INTCTRLA; /* Interrupt Control Register A */ - register8_t INTCTRLB; /* Interrupt Control Register B */ - register8_t reserved_0x08; - register8_t CTRLF; /* Control Register F */ - register8_t reserved_0x0A; - register8_t reserved_0x0B; - register8_t INTFLAGS; /* Interrupt Flag Register */ - register8_t reserved_0x0D; - register8_t reserved_0x0E; - register8_t reserved_0x0F; - register8_t reserved_0x10; - register8_t reserved_0x11; - register8_t reserved_0x12; - register8_t reserved_0x13; - register8_t reserved_0x14; - register8_t reserved_0x15; - register8_t reserved_0x16; - register8_t reserved_0x17; - register8_t reserved_0x18; - register8_t reserved_0x19; - register8_t reserved_0x1A; - register8_t reserved_0x1B; - register8_t reserved_0x1C; - register8_t reserved_0x1D; - register8_t reserved_0x1E; - register8_t reserved_0x1F; - register8_t LCNT; /* Low Byte Count */ - register8_t HCNT; /* High Byte Count */ - register8_t reserved_0x22; - register8_t reserved_0x23; - register8_t reserved_0x24; - register8_t reserved_0x25; - register8_t LPER; /* Low Byte Period */ - register8_t HPER; /* High Byte Period */ - register8_t LCMPA; /* Low Byte Compare A */ - register8_t HCMPA; /* High Byte Compare A */ - register8_t LCMPB; /* Low Byte Compare B */ - register8_t HCMPB; /* High Byte Compare B */ - register8_t LCMPC; /* Low Byte Compare C */ - register8_t HCMPC; /* High Byte Compare C */ - register8_t LCMPD; /* Low Byte Compare D */ - register8_t HCMPD; /* High Byte Compare D */ -} TC2_t; - -/* Clock Selection */ -typedef enum TC2_CLKSEL_enum -{ - TC2_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */ - TC2_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */ - TC2_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */ - TC2_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */ - TC2_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */ - TC2_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */ - TC2_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */ - TC2_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */ - TC2_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */ - TC2_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */ - TC2_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */ - TC2_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */ -} TC2_CLKSEL_t; - -/* Byte Mode */ -typedef enum TC2_BYTEM_enum -{ - TC2_BYTEM_NORMAL_gc = (0x00<<0), /* 16-bit mode */ - TC2_BYTEM_BYTEMODE_gc = (0x01<<0), /* Timer/Counter operating in byte mode only (TC2) */ - TC2_BYTEM_SPLITMODE_gc = (0x02<<0), /* Timer/Counter split into two 8-bit Counters */ -} TC2_BYTEM_t; - -/* High Byte Underflow Interrupt Level */ -typedef enum TC2_HUNFINTLVL_enum -{ - TC2_HUNFINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ - TC2_HUNFINTLVL_LO_gc = (0x01<<2), /* Low Level */ - TC2_HUNFINTLVL_MED_gc = (0x02<<2), /* Medium Level */ - TC2_HUNFINTLVL_HI_gc = (0x03<<2), /* High Level */ -} TC2_HUNFINTLVL_t; - -/* Low Byte Underflow Interrupt Level */ -typedef enum TC2_LUNFINTLVL_enum -{ - TC2_LUNFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - TC2_LUNFINTLVL_LO_gc = (0x01<<0), /* Low Level */ - TC2_LUNFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ - TC2_LUNFINTLVL_HI_gc = (0x03<<0), /* High Level */ -} TC2_LUNFINTLVL_t; - -/* Low Byte Compare D Interrupt Level */ -typedef enum TC2_LCMPDINTLVL_enum -{ - TC2_LCMPDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ - TC2_LCMPDINTLVL_LO_gc = (0x01<<6), /* Low Level */ - TC2_LCMPDINTLVL_MED_gc = (0x02<<6), /* Medium Level */ - TC2_LCMPDINTLVL_HI_gc = (0x03<<6), /* High Level */ -} TC2_LCMPDINTLVL_t; - -/* Low Byte Compare C Interrupt Level */ -typedef enum TC2_LCMPCINTLVL_enum -{ - TC2_LCMPCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ - TC2_LCMPCINTLVL_LO_gc = (0x01<<4), /* Low Level */ - TC2_LCMPCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ - TC2_LCMPCINTLVL_HI_gc = (0x03<<4), /* High Level */ -} TC2_LCMPCINTLVL_t; - -/* Low Byte Compare B Interrupt Level */ -typedef enum TC2_LCMPBINTLVL_enum -{ - TC2_LCMPBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ - TC2_LCMPBINTLVL_LO_gc = (0x01<<2), /* Low Level */ - TC2_LCMPBINTLVL_MED_gc = (0x02<<2), /* Medium Level */ - TC2_LCMPBINTLVL_HI_gc = (0x03<<2), /* High Level */ -} TC2_LCMPBINTLVL_t; - -/* Low Byte Compare A Interrupt Level */ -typedef enum TC2_LCMPAINTLVL_enum -{ - TC2_LCMPAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - TC2_LCMPAINTLVL_LO_gc = (0x01<<0), /* Low Level */ - TC2_LCMPAINTLVL_MED_gc = (0x02<<0), /* Medium Level */ - TC2_LCMPAINTLVL_HI_gc = (0x03<<0), /* High Level */ -} TC2_LCMPAINTLVL_t; - -/* Timer/Counter Command */ -typedef enum TC2_CMD_enum -{ - TC2_CMD_NONE_gc = (0x00<<2), /* No Command */ - TC2_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ - TC2_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ -} TC2_CMD_t; - -/* Timer/Counter Command */ -typedef enum TC2_CMDEN_enum -{ - TC2_CMDEN_LOW_gc = (0x01<<0), /* Low Byte Timer/Counter */ - TC2_CMDEN_HIGH_gc = (0x02<<0), /* High Byte Timer/Counter */ - TC2_CMDEN_BOTH_gc = (0x03<<0), /* Both Low Byte and High Byte Timer/Counters */ -} TC2_CMDEN_t; - - -/* --------------------------------------------------------------------------- -AWEX - Timer/Counter Advanced Waveform Extension --------------------------------------------------------------------------- -*/ - -/* Advanced Waveform Extension */ -typedef struct AWEX_struct -{ - register8_t CTRL; /* Control Register */ - register8_t reserved_0x01; - register8_t FDEMASK; /* Fault Detection Event Mask */ - register8_t FDCTRL; /* Fault Detection Control Register */ - register8_t STATUS; /* Status Register */ - register8_t STATUSSET; /* Status Set Register */ - register8_t DTBOTH; /* Dead Time Both Sides */ - register8_t DTBOTHBUF; /* Dead Time Both Sides Buffer */ - register8_t DTLS; /* Dead Time Low Side */ - register8_t DTHS; /* Dead Time High Side */ - register8_t DTLSBUF; /* Dead Time Low Side Buffer */ - register8_t DTHSBUF; /* Dead Time High Side Buffer */ - register8_t OUTOVEN; /* Output Override Enable */ -} AWEX_t; - -/* Fault Detect Action */ -typedef enum AWEX_FDACT_enum -{ - AWEX_FDACT_NONE_gc = (0x00<<0), /* No Fault Protection */ - AWEX_FDACT_CLEAROE_gc = (0x01<<0), /* Clear Output Enable Bits */ - AWEX_FDACT_CLEARDIR_gc = (0x03<<0), /* Clear I/O Port Direction Bits */ -} AWEX_FDACT_t; - - -/* --------------------------------------------------------------------------- -HIRES - Timer/Counter High-Resolution Extension --------------------------------------------------------------------------- -*/ - -/* High-Resolution Extension */ -typedef struct HIRES_struct -{ - register8_t CTRLA; /* Control Register */ -} HIRES_t; - -/* High Resolution Enable */ -typedef enum HIRES_HREN_enum -{ - HIRES_HREN_NONE_gc = (0x00<<0), /* No Fault Protection */ - HIRES_HREN_TC0_gc = (0x01<<0), /* Enable High Resolution on Timer/Counter 0 */ - HIRES_HREN_TC1_gc = (0x02<<0), /* Enable High Resolution on Timer/Counter 1 */ - HIRES_HREN_BOTH_gc = (0x03<<0), /* Enable High Resolution both Timer/Counters */ -} HIRES_HREN_t; - - -/* --------------------------------------------------------------------------- -USART - Universal Asynchronous Receiver-Transmitter --------------------------------------------------------------------------- -*/ - -/* Universal Synchronous/Asynchronous Receiver/Transmitter */ -typedef struct USART_struct -{ - register8_t DATA; /* Data Register */ - register8_t STATUS; /* Status Register */ - register8_t reserved_0x02; - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t CTRLC; /* Control Register C */ - register8_t BAUDCTRLA; /* Baud Rate Control Register A */ - register8_t BAUDCTRLB; /* Baud Rate Control Register B */ -} USART_t; - -/* Receive Complete Interrupt level */ -typedef enum USART_RXCINTLVL_enum -{ - USART_RXCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ - USART_RXCINTLVL_LO_gc = (0x01<<4), /* Low Level */ - USART_RXCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ - USART_RXCINTLVL_HI_gc = (0x03<<4), /* High Level */ -} USART_RXCINTLVL_t; - -/* Transmit Complete Interrupt level */ -typedef enum USART_TXCINTLVL_enum -{ - USART_TXCINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ - USART_TXCINTLVL_LO_gc = (0x01<<2), /* Low Level */ - USART_TXCINTLVL_MED_gc = (0x02<<2), /* Medium Level */ - USART_TXCINTLVL_HI_gc = (0x03<<2), /* High Level */ -} USART_TXCINTLVL_t; - -/* Data Register Empty Interrupt level */ -typedef enum USART_DREINTLVL_enum -{ - USART_DREINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - USART_DREINTLVL_LO_gc = (0x01<<0), /* Low Level */ - USART_DREINTLVL_MED_gc = (0x02<<0), /* Medium Level */ - USART_DREINTLVL_HI_gc = (0x03<<0), /* High Level */ -} USART_DREINTLVL_t; - -/* Character Size */ -typedef enum USART_CHSIZE_enum -{ - USART_CHSIZE_5BIT_gc = (0x00<<0), /* Character size: 5 bit */ - USART_CHSIZE_6BIT_gc = (0x01<<0), /* Character size: 6 bit */ - USART_CHSIZE_7BIT_gc = (0x02<<0), /* Character size: 7 bit */ - USART_CHSIZE_8BIT_gc = (0x03<<0), /* Character size: 8 bit */ - USART_CHSIZE_9BIT_gc = (0x07<<0), /* Character size: 9 bit */ -} USART_CHSIZE_t; - -/* Communication Mode */ -typedef enum USART_CMODE_enum -{ - USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6), /* Asynchronous Mode */ - USART_CMODE_SYNCHRONOUS_gc = (0x01<<6), /* Synchronous Mode */ - USART_CMODE_IRDA_gc = (0x02<<6), /* IrDA Mode */ - USART_CMODE_MSPI_gc = (0x03<<6), /* Master SPI Mode */ -} USART_CMODE_t; - -/* Parity Mode */ -typedef enum USART_PMODE_enum -{ - USART_PMODE_DISABLED_gc = (0x00<<4), /* No Parity */ - USART_PMODE_EVEN_gc = (0x02<<4), /* Even Parity */ - USART_PMODE_ODD_gc = (0x03<<4), /* Odd Parity */ -} USART_PMODE_t; - - -/* --------------------------------------------------------------------------- -SPI - Serial Peripheral Interface --------------------------------------------------------------------------- -*/ - -/* Serial Peripheral Interface */ -typedef struct SPI_struct -{ - register8_t CTRL; /* Control Register */ - register8_t INTCTRL; /* Interrupt Control Register */ - register8_t STATUS; /* Status Register */ - register8_t DATA; /* Data Register */ -} SPI_t; - -/* SPI Mode */ -typedef enum SPI_MODE_enum -{ - SPI_MODE_0_gc = (0x00<<2), /* SPI Mode 0 */ - SPI_MODE_1_gc = (0x01<<2), /* SPI Mode 1 */ - SPI_MODE_2_gc = (0x02<<2), /* SPI Mode 2 */ - SPI_MODE_3_gc = (0x03<<2), /* SPI Mode 3 */ -} SPI_MODE_t; - -/* Prescaler setting */ -typedef enum SPI_PRESCALER_enum -{ - SPI_PRESCALER_DIV4_gc = (0x00<<0), /* System Clock / 4 */ - SPI_PRESCALER_DIV16_gc = (0x01<<0), /* System Clock / 16 */ - SPI_PRESCALER_DIV64_gc = (0x02<<0), /* System Clock / 64 */ - SPI_PRESCALER_DIV128_gc = (0x03<<0), /* System Clock / 128 */ -} SPI_PRESCALER_t; - -/* Interrupt level */ -typedef enum SPI_INTLVL_enum -{ - SPI_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - SPI_INTLVL_LO_gc = (0x01<<0), /* Low Level */ - SPI_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ - SPI_INTLVL_HI_gc = (0x03<<0), /* High Level */ -} SPI_INTLVL_t; - - -/* --------------------------------------------------------------------------- -IRCOM - IR Communication Module --------------------------------------------------------------------------- -*/ - -/* IR Communication Module */ -typedef struct IRCOM_struct -{ - register8_t CTRL; /* Control Register */ - register8_t TXPLCTRL; /* IrDA Transmitter Pulse Length Control Register */ - register8_t RXPLCTRL; /* IrDA Receiver Pulse Length Control Register */ -} IRCOM_t; - -/* Event channel selection */ -typedef enum IRDA_EVSEL_enum -{ - IRDA_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ - IRDA_EVSEL_0_gc = (0x08<<0), /* Event Channel 0 */ - IRDA_EVSEL_1_gc = (0x09<<0), /* Event Channel 1 */ - IRDA_EVSEL_2_gc = (0x0A<<0), /* Event Channel 2 */ - IRDA_EVSEL_3_gc = (0x0B<<0), /* Event Channel 3 */ -} IRDA_EVSEL_t; - - -/* --------------------------------------------------------------------------- -FUSE - Fuses and Lockbits --------------------------------------------------------------------------- -*/ - -/* Fuses */ -typedef struct NVM_FUSES_struct -{ - register8_t reserved_0x00; - register8_t FUSEBYTE1; /* Watchdog Configuration */ - register8_t FUSEBYTE2; /* Reset Configuration */ - register8_t reserved_0x03; - register8_t FUSEBYTE4; /* Start-up Configuration */ - register8_t FUSEBYTE5; /* EESAVE and BOD Level */ -} NVM_FUSES_t; - -/* Boot Loader Section Reset Vector */ -typedef enum BOOTRST_enum -{ - BOOTRST_BOOTLDR_gc = (0x00<<6), /* Boot Loader Reset */ - BOOTRST_APPLICATION_gc = (0x01<<6), /* Application Reset */ -} BOOTRST_t; - -/* Timer Oscillator pin location */ -typedef enum TOSCSEL_enum -{ - TOSCSEL_ALTERNATE_gc = (0x00<<5), /* TOSC1 / TOSC2 on separate pins */ - TOSCSEL_XTAL_gc = (0x01<<5), /* TOSC1 / TOSC2 shared with XTAL1 / XTAL2 */ -} TOSCSEL_t; - -/* BOD operation */ -typedef enum BOD_enum -{ - BOD_SAMPLED_gc = (0x01<<0), /* BOD enabled in sampled mode */ - BOD_CONTINUOUS_gc = (0x02<<0), /* BOD enabled continuously */ - BOD_DISABLED_gc = (0x03<<0), /* BOD Disabled */ -} BOD_t; - -/* BOD operation */ -typedef enum BODACT_enum -{ - BODACT_SAMPLED_gc = (0x01<<4), /* BOD enabled in sampled mode */ - BODACT_CONTINUOUS_gc = (0x02<<4), /* BOD enabled continuously */ - BODACT_DISABLED_gc = (0x03<<4), /* BOD Disabled */ -} BODACT_t; - -/* Watchdog (Window) Timeout Period */ -typedef enum WD_enum -{ - WD_8CLK_gc = (0x00<<4), /* 8 cycles (8ms @ 3.3V) */ - WD_16CLK_gc = (0x01<<4), /* 16 cycles (16ms @ 3.3V) */ - WD_32CLK_gc = (0x02<<4), /* 32 cycles (32ms @ 3.3V) */ - WD_64CLK_gc = (0x03<<4), /* 64 cycles (64ms @ 3.3V) */ - WD_128CLK_gc = (0x04<<4), /* 128 cycles (0.125s @ 3.3V) */ - WD_256CLK_gc = (0x05<<4), /* 256 cycles (0.25s @ 3.3V) */ - WD_512CLK_gc = (0x06<<4), /* 512 cycles (0.5s @ 3.3V) */ - WD_1KCLK_gc = (0x07<<4), /* 1K cycles (1s @ 3.3V) */ - WD_2KCLK_gc = (0x08<<4), /* 2K cycles (2s @ 3.3V) */ - WD_4KCLK_gc = (0x09<<4), /* 4K cycles (4s @ 3.3V) */ - WD_8KCLK_gc = (0x0A<<4), /* 8K cycles (8s @ 3.3V) */ -} WD_t; - -/* Watchdog (Window) Timeout Period */ -typedef enum WDP_enum -{ - WDP_8CLK_gc = (0x00<<0), /* 8 cycles (8ms @ 3.3V) */ - WDP_16CLK_gc = (0x01<<0), /* 16 cycles (16ms @ 3.3V) */ - WDP_32CLK_gc = (0x02<<0), /* 32 cycles (32ms @ 3.3V) */ - WDP_64CLK_gc = (0x03<<0), /* 64 cycles (64ms @ 3.3V) */ - WDP_128CLK_gc = (0x04<<0), /* 128 cycles (0.125s @ 3.3V) */ - WDP_256CLK_gc = (0x05<<0), /* 256 cycles (0.25s @ 3.3V) */ - WDP_512CLK_gc = (0x06<<0), /* 512 cycles (0.5s @ 3.3V) */ - WDP_1KCLK_gc = (0x07<<0), /* 1K cycles (1s @ 3.3V) */ - WDP_2KCLK_gc = (0x08<<0), /* 2K cycles (2s @ 3.3V) */ - WDP_4KCLK_gc = (0x09<<0), /* 4K cycles (4s @ 3.3V) */ - WDP_8KCLK_gc = (0x0A<<0), /* 8K cycles (8s @ 3.3V) */ -} WDP_t; - -/* Start-up Time */ -typedef enum SUT_enum -{ - SUT_0MS_gc = (0x03<<2), /* 0 ms */ - SUT_4MS_gc = (0x01<<2), /* 4 ms */ - SUT_64MS_gc = (0x00<<2), /* 64 ms */ -} SUT_t; - -/* Brownout Detection Voltage Level */ -typedef enum BODLVL_enum -{ - BODLVL_1V6_gc = (0x07<<0), /* 1.6 V */ - BODLVL_1V8_gc = (0x06<<0), /* 1.8 V */ - BODLVL_2V0_gc = (0x05<<0), /* 2.0 V */ - BODLVL_2V2_gc = (0x04<<0), /* 2.2 V */ - BODLVL_2V4_gc = (0x03<<0), /* 2.4 V */ - BODLVL_2V6_gc = (0x02<<0), /* 2.6 V */ - BODLVL_2V8_gc = (0x01<<0), /* 2.8 V */ - BODLVL_3V0_gc = (0x00<<0), /* 3.0 V */ -} BODLVL_t; - - -/* --------------------------------------------------------------------------- -LOCKBIT - Fuses and Lockbits --------------------------------------------------------------------------- -*/ - -/* Lock Bits */ -typedef struct NVM_LOCKBITS_struct -{ - register8_t LOCK_BITS; /* Lock Bits (Changed from LOCKBITS to avoid avr-libc collision) */ -} NVM_LOCKBITS_t; - -/* Boot lock bits - boot setcion */ -typedef enum FUSE_BLBB_enum -{ - FUSE_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ - FUSE_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ - FUSE_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ - FUSE_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ -} FUSE_BLBB_t; - -/* Boot lock bits - application section */ -typedef enum FUSE_BLBA_enum -{ - FUSE_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ - FUSE_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ - FUSE_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ - FUSE_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ -} FUSE_BLBA_t; - -/* Boot lock bits - application table section */ -typedef enum FUSE_BLBAT_enum -{ - FUSE_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ - FUSE_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ - FUSE_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ - FUSE_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ -} FUSE_BLBAT_t; - -/* Lock bits */ -typedef enum FUSE_LB_enum -{ - FUSE_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ - FUSE_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ - FUSE_LB_NOLOCK_gc = (0x03<<0), /* No locks */ -} FUSE_LB_t; - - -/* --------------------------------------------------------------------------- -SIGROW - Signature Row --------------------------------------------------------------------------- -*/ - -/* Production Signatures */ -typedef struct NVM_PROD_SIGNATURES_struct -{ - register8_t RCOSC2M; /* RCOSC 2 MHz Calibration Value B */ - register8_t RCOSC2MA; /* RCOSC 2 MHz Calibration Value A */ - register8_t RCOSC32K; /* RCOSC 32.768 kHz Calibration Value */ - register8_t RCOSC32M; /* RCOSC 32 MHz Calibration Value B */ - register8_t RCOSC32MA; /* RCOSC 32 MHz Calibration Value A */ - register8_t reserved_0x05; - register8_t reserved_0x06; - register8_t reserved_0x07; - register8_t LOTNUM0; /* Lot Number Byte 0, ASCII */ - register8_t LOTNUM1; /* Lot Number Byte 1, ASCII */ - register8_t LOTNUM2; /* Lot Number Byte 2, ASCII */ - register8_t LOTNUM3; /* Lot Number Byte 3, ASCII */ - register8_t LOTNUM4; /* Lot Number Byte 4, ASCII */ - register8_t LOTNUM5; /* Lot Number Byte 5, ASCII */ - register8_t reserved_0x0E; - register8_t reserved_0x0F; - register8_t WAFNUM; /* Wafer Number */ - register8_t reserved_0x11; - register8_t COORDX0; /* Wafer Coordinate X Byte 0 */ - register8_t COORDX1; /* Wafer Coordinate X Byte 1 */ - register8_t COORDY0; /* Wafer Coordinate Y Byte 0 */ - register8_t COORDY1; /* Wafer Coordinate Y Byte 1 */ - register8_t reserved_0x16; - register8_t reserved_0x17; - register8_t reserved_0x18; - register8_t reserved_0x19; - register8_t reserved_0x1A; - register8_t reserved_0x1B; - register8_t reserved_0x1C; - register8_t reserved_0x1D; - register8_t reserved_0x1E; - register8_t reserved_0x1F; - register8_t ADCACAL0; /* ADCA Calibration Byte 0 */ - register8_t ADCACAL1; /* ADCA Calibration Byte 1 */ - register8_t reserved_0x22; - register8_t reserved_0x23; - register8_t reserved_0x24; - register8_t reserved_0x25; - register8_t reserved_0x26; - register8_t reserved_0x27; - register8_t reserved_0x28; - register8_t reserved_0x29; - register8_t reserved_0x2A; - register8_t reserved_0x2B; - register8_t reserved_0x2C; - register8_t reserved_0x2D; - register8_t TEMPSENSE0; /* Temperature Sensor Calibration Byte 0 */ - register8_t TEMPSENSE1; /* Temperature Sensor Calibration Byte 1 */ - register8_t reserved_0x30; - register8_t reserved_0x31; - register8_t reserved_0x32; - register8_t reserved_0x33; - register8_t reserved_0x34; - register8_t reserved_0x35; - register8_t reserved_0x36; - register8_t reserved_0x37; - register8_t reserved_0x38; - register8_t reserved_0x39; - register8_t reserved_0x3A; - register8_t reserved_0x3B; - register8_t reserved_0x3C; - register8_t reserved_0x3D; - register8_t reserved_0x3E; - register8_t reserved_0x3F; -} NVM_PROD_SIGNATURES_t; - -/* -========================================================================== -IO Module Instances. Mapped to memory. -========================================================================== -*/ - -#define VPORT0 (*(VPORT_t *) 0x0010) /* Virtual Port */ -#define VPORT1 (*(VPORT_t *) 0x0014) /* Virtual Port */ -#define VPORT2 (*(VPORT_t *) 0x0018) /* Virtual Port */ -#define VPORT3 (*(VPORT_t *) 0x001C) /* Virtual Port */ -#define OCD (*(OCD_t *) 0x002E) /* On-Chip Debug System */ -#define CLK (*(CLK_t *) 0x0040) /* Clock System */ -#define SLEEP (*(SLEEP_t *) 0x0048) /* Sleep Controller */ -#define OSC (*(OSC_t *) 0x0050) /* Oscillator */ -#define DFLLRC32M (*(DFLL_t *) 0x0060) /* DFLL */ -#define DFLLRC2M (*(DFLL_t *) 0x0068) /* DFLL */ -#define PR (*(PR_t *) 0x0070) /* Power Reduction */ -#define RST (*(RST_t *) 0x0078) /* Reset */ -#define WDT (*(WDT_t *) 0x0080) /* Watch-Dog Timer */ -#define MCU (*(MCU_t *) 0x0090) /* MCU Control */ -#define PMIC (*(PMIC_t *) 0x00A0) /* Programmable Multi-level Interrupt Controller */ -#define PORTCFG (*(PORTCFG_t *) 0x00B0) /* I/O port Configuration */ -#define CRC (*(CRC_t *) 0x00D0) /* Cyclic Redundancy Checker */ -#define EVSYS (*(EVSYS_t *) 0x0180) /* Event System */ -#define NVM (*(NVM_t *) 0x01C0) /* Non-volatile Memory Controller */ -#define ADCA (*(ADC_t *) 0x0200) /* Analog-to-Digital Converter */ -#define ACA (*(AC_t *) 0x0380) /* Analog Comparator */ -#define RTC (*(RTC_t *) 0x0400) /* Real-Time Counter */ -#define TWIC (*(TWI_t *) 0x0480) /* Two-Wire Interface */ -#define TWIE (*(TWI_t *) 0x04A0) /* Two-Wire Interface */ -#define PORTA (*(PORT_t *) 0x0600) /* I/O Ports */ -#define PORTB (*(PORT_t *) 0x0620) /* I/O Ports */ -#define PORTC (*(PORT_t *) 0x0640) /* I/O Ports */ -#define PORTD (*(PORT_t *) 0x0660) /* I/O Ports */ -#define PORTE (*(PORT_t *) 0x0680) /* I/O Ports */ -#define PORTR (*(PORT_t *) 0x07E0) /* I/O Ports */ -#define TCC0 (*(TC0_t *) 0x0800) /* 16-bit Timer/Counter 0 */ -#define TCC2 (*(TC2_t *) 0x0800) /* 16-bit Timer/Counter type 2 */ -#define TCC1 (*(TC1_t *) 0x0840) /* 16-bit Timer/Counter 1 */ -#define AWEXC (*(AWEX_t *) 0x0880) /* Advanced Waveform Extension */ -#define HIRESC (*(HIRES_t *) 0x0890) /* High-Resolution Extension */ -#define USARTC0 (*(USART_t *) 0x08A0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ -#define SPIC (*(SPI_t *) 0x08C0) /* Serial Peripheral Interface */ -#define IRCOM (*(IRCOM_t *) 0x08F8) /* IR Communication Module */ -#define TCD0 (*(TC0_t *) 0x0900) /* 16-bit Timer/Counter 0 */ -#define TCD2 (*(TC2_t *) 0x0900) /* 16-bit Timer/Counter type 2 */ -#define USARTD0 (*(USART_t *) 0x09A0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ -#define SPID (*(SPI_t *) 0x09C0) /* Serial Peripheral Interface */ -#define TCE0 (*(TC0_t *) 0x0A00) /* 16-bit Timer/Counter 0 */ - - -#endif /* !defined (__ASSEMBLER__) */ - - -/* ========== Flattened fully qualified IO register names ========== */ - -/* GPIO - General Purpose IO Registers */ -#define GPIO_GPIOR0 _SFR_MEM8(0x0000) -#define GPIO_GPIOR1 _SFR_MEM8(0x0001) -#define GPIO_GPIOR2 _SFR_MEM8(0x0002) -#define GPIO_GPIOR3 _SFR_MEM8(0x0003) - -/* Deprecated */ -#define GPIO_GPIO0 _SFR_MEM8(0x0000) -#define GPIO_GPIO1 _SFR_MEM8(0x0001) -#define GPIO_GPIO2 _SFR_MEM8(0x0002) -#define GPIO_GPIO3 _SFR_MEM8(0x0003) - -/* NVM_FUSES - Fuses */ -#define FUSE_FUSEBYTE1 _SFR_MEM8(0x0001) -#define FUSE_FUSEBYTE2 _SFR_MEM8(0x0002) -#define FUSE_FUSEBYTE4 _SFR_MEM8(0x0004) -#define FUSE_FUSEBYTE5 _SFR_MEM8(0x0005) - -/* NVM_LOCKBITS - Lock Bits */ -#define LOCKBIT_LOCKBITS _SFR_MEM8(0x0000) - -/* NVM_PROD_SIGNATURES - Production Signatures */ -#define PRODSIGNATURES_RCOSC2M _SFR_MEM8(0x0000) -#define PRODSIGNATURES_RCOSC2MA _SFR_MEM8(0x0001) -#define PRODSIGNATURES_RCOSC32K _SFR_MEM8(0x0002) -#define PRODSIGNATURES_RCOSC32M _SFR_MEM8(0x0003) -#define PRODSIGNATURES_RCOSC32MA _SFR_MEM8(0x0004) -#define PRODSIGNATURES_LOTNUM0 _SFR_MEM8(0x0008) -#define PRODSIGNATURES_LOTNUM1 _SFR_MEM8(0x0009) -#define PRODSIGNATURES_LOTNUM2 _SFR_MEM8(0x000A) -#define PRODSIGNATURES_LOTNUM3 _SFR_MEM8(0x000B) -#define PRODSIGNATURES_LOTNUM4 _SFR_MEM8(0x000C) -#define PRODSIGNATURES_LOTNUM5 _SFR_MEM8(0x000D) -#define PRODSIGNATURES_WAFNUM _SFR_MEM8(0x0010) -#define PRODSIGNATURES_COORDX0 _SFR_MEM8(0x0012) -#define PRODSIGNATURES_COORDX1 _SFR_MEM8(0x0013) -#define PRODSIGNATURES_COORDY0 _SFR_MEM8(0x0014) -#define PRODSIGNATURES_COORDY1 _SFR_MEM8(0x0015) -#define PRODSIGNATURES_ADCACAL0 _SFR_MEM8(0x0020) -#define PRODSIGNATURES_ADCACAL1 _SFR_MEM8(0x0021) -#define PRODSIGNATURES_TEMPSENSE0 _SFR_MEM8(0x002E) -#define PRODSIGNATURES_TEMPSENSE1 _SFR_MEM8(0x002F) - -/* VPORT - Virtual Port */ -#define VPORT0_DIR _SFR_MEM8(0x0010) -#define VPORT0_OUT _SFR_MEM8(0x0011) -#define VPORT0_IN _SFR_MEM8(0x0012) -#define VPORT0_INTFLAGS _SFR_MEM8(0x0013) - -/* VPORT - Virtual Port */ -#define VPORT1_DIR _SFR_MEM8(0x0014) -#define VPORT1_OUT _SFR_MEM8(0x0015) -#define VPORT1_IN _SFR_MEM8(0x0016) -#define VPORT1_INTFLAGS _SFR_MEM8(0x0017) - -/* VPORT - Virtual Port */ -#define VPORT2_DIR _SFR_MEM8(0x0018) -#define VPORT2_OUT _SFR_MEM8(0x0019) -#define VPORT2_IN _SFR_MEM8(0x001A) -#define VPORT2_INTFLAGS _SFR_MEM8(0x001B) - -/* VPORT - Virtual Port */ -#define VPORT3_DIR _SFR_MEM8(0x001C) -#define VPORT3_OUT _SFR_MEM8(0x001D) -#define VPORT3_IN _SFR_MEM8(0x001E) -#define VPORT3_INTFLAGS _SFR_MEM8(0x001F) - -/* OCD - On-Chip Debug System */ -#define OCD_OCDR0 _SFR_MEM8(0x002E) -#define OCD_OCDR1 _SFR_MEM8(0x002F) - -/* CPU - CPU registers */ -#define CPU_CCP _SFR_MEM8(0x0034) -#define CPU_RAMPD _SFR_MEM8(0x0038) -#define CPU_RAMPX _SFR_MEM8(0x0039) -#define CPU_RAMPY _SFR_MEM8(0x003A) -#define CPU_RAMPZ _SFR_MEM8(0x003B) -#define CPU_EIND _SFR_MEM8(0x003C) -#define CPU_SPL _SFR_MEM8(0x003D) -#define CPU_SPH _SFR_MEM8(0x003E) -#define CPU_SREG _SFR_MEM8(0x003F) - -/* CLK - Clock System */ -#define CLK_CTRL _SFR_MEM8(0x0040) -#define CLK_PSCTRL _SFR_MEM8(0x0041) -#define CLK_LOCK _SFR_MEM8(0x0042) -#define CLK_RTCCTRL _SFR_MEM8(0x0043) - -/* SLEEP - Sleep Controller */ -#define SLEEP_CTRL _SFR_MEM8(0x0048) - -/* OSC - Oscillator */ -#define OSC_CTRL _SFR_MEM8(0x0050) -#define OSC_STATUS _SFR_MEM8(0x0051) -#define OSC_XOSCCTRL _SFR_MEM8(0x0052) -#define OSC_XOSCFAIL _SFR_MEM8(0x0053) -#define OSC_RC32KCAL _SFR_MEM8(0x0054) -#define OSC_PLLCTRL _SFR_MEM8(0x0055) -#define OSC_DFLLCTRL _SFR_MEM8(0x0056) - -/* DFLL - DFLL */ -#define DFLLRC32M_CTRL _SFR_MEM8(0x0060) -#define DFLLRC32M_CALA _SFR_MEM8(0x0062) -#define DFLLRC32M_CALB _SFR_MEM8(0x0063) -#define DFLLRC32M_COMP0 _SFR_MEM8(0x0064) -#define DFLLRC32M_COMP1 _SFR_MEM8(0x0065) -#define DFLLRC32M_COMP2 _SFR_MEM8(0x0066) - -/* DFLL - DFLL */ -#define DFLLRC2M_CTRL _SFR_MEM8(0x0068) -#define DFLLRC2M_CALA _SFR_MEM8(0x006A) -#define DFLLRC2M_CALB _SFR_MEM8(0x006B) -#define DFLLRC2M_COMP0 _SFR_MEM8(0x006C) -#define DFLLRC2M_COMP1 _SFR_MEM8(0x006D) -#define DFLLRC2M_COMP2 _SFR_MEM8(0x006E) - -/* PR - Power Reduction */ -#define PR_PRGEN _SFR_MEM8(0x0070) -#define PR_PRPA _SFR_MEM8(0x0071) -#define PR_PRPC _SFR_MEM8(0x0073) -#define PR_PRPD _SFR_MEM8(0x0074) -#define PR_PRPE _SFR_MEM8(0x0075) -#define PR_PRPF _SFR_MEM8(0x0076) - -/* RST - Reset */ -#define RST_STATUS _SFR_MEM8(0x0078) -#define RST_CTRL _SFR_MEM8(0x0079) - -/* WDT - Watch-Dog Timer */ -#define WDT_CTRL _SFR_MEM8(0x0080) -#define WDT_WINCTRL _SFR_MEM8(0x0081) -#define WDT_STATUS _SFR_MEM8(0x0082) - -/* MCU - MCU Control */ -#define MCU_DEVID0 _SFR_MEM8(0x0090) -#define MCU_DEVID1 _SFR_MEM8(0x0091) -#define MCU_DEVID2 _SFR_MEM8(0x0092) -#define MCU_REVID _SFR_MEM8(0x0093) -#define MCU_ANAINIT _SFR_MEM8(0x0097) -#define MCU_EVSYSLOCK _SFR_MEM8(0x0098) -#define MCU_AWEXLOCK _SFR_MEM8(0x0099) - -/* PMIC - Programmable Multi-level Interrupt Controller */ -#define PMIC_STATUS _SFR_MEM8(0x00A0) -#define PMIC_INTPRI _SFR_MEM8(0x00A1) -#define PMIC_CTRL _SFR_MEM8(0x00A2) - -/* PORTCFG - I/O port Configuration */ -#define PORTCFG_MPCMASK _SFR_MEM8(0x00B0) -#define PORTCFG_VPCTRLA _SFR_MEM8(0x00B2) -#define PORTCFG_VPCTRLB _SFR_MEM8(0x00B3) -#define PORTCFG_CLKEVOUT _SFR_MEM8(0x00B4) -#define PORTCFG_EVOUTSEL _SFR_MEM8(0x00B6) - -/* CRC - Cyclic Redundancy Checker */ -#define CRC_CTRL _SFR_MEM8(0x00D0) -#define CRC_STATUS _SFR_MEM8(0x00D1) -#define CRC_DATAIN _SFR_MEM8(0x00D3) -#define CRC_CHECKSUM0 _SFR_MEM8(0x00D4) -#define CRC_CHECKSUM1 _SFR_MEM8(0x00D5) -#define CRC_CHECKSUM2 _SFR_MEM8(0x00D6) -#define CRC_CHECKSUM3 _SFR_MEM8(0x00D7) - -/* EVSYS - Event System */ -#define EVSYS_CH0MUX _SFR_MEM8(0x0180) -#define EVSYS_CH1MUX _SFR_MEM8(0x0181) -#define EVSYS_CH2MUX _SFR_MEM8(0x0182) -#define EVSYS_CH3MUX _SFR_MEM8(0x0183) -#define EVSYS_CH0CTRL _SFR_MEM8(0x0188) -#define EVSYS_CH1CTRL _SFR_MEM8(0x0189) -#define EVSYS_CH2CTRL _SFR_MEM8(0x018A) -#define EVSYS_CH3CTRL _SFR_MEM8(0x018B) -#define EVSYS_STROBE _SFR_MEM8(0x0190) -#define EVSYS_DATA _SFR_MEM8(0x0191) - -/* NVM - Non-volatile Memory Controller */ -#define NVM_ADDR0 _SFR_MEM8(0x01C0) -#define NVM_ADDR1 _SFR_MEM8(0x01C1) -#define NVM_ADDR2 _SFR_MEM8(0x01C2) -#define NVM_DATA0 _SFR_MEM8(0x01C4) -#define NVM_DATA1 _SFR_MEM8(0x01C5) -#define NVM_DATA2 _SFR_MEM8(0x01C6) -#define NVM_CMD _SFR_MEM8(0x01CA) -#define NVM_CTRLA _SFR_MEM8(0x01CB) -#define NVM_CTRLB _SFR_MEM8(0x01CC) -#define NVM_INTCTRL _SFR_MEM8(0x01CD) -#define NVM_STATUS _SFR_MEM8(0x01CF) -#define NVM_LOCKBITS _SFR_MEM8(0x01D0) - -/* ADC - Analog-to-Digital Converter */ -#define ADCA_CTRLA _SFR_MEM8(0x0200) -#define ADCA_CTRLB _SFR_MEM8(0x0201) -#define ADCA_REFCTRL _SFR_MEM8(0x0202) -#define ADCA_EVCTRL _SFR_MEM8(0x0203) -#define ADCA_PRESCALER _SFR_MEM8(0x0204) -#define ADCA_INTFLAGS _SFR_MEM8(0x0206) -#define ADCA_TEMP _SFR_MEM8(0x0207) -#define ADCA_CAL _SFR_MEM16(0x020C) -#define ADCA_CH0RES _SFR_MEM16(0x0210) -#define ADCA_CMP _SFR_MEM16(0x0218) -#define ADCA_CH0_CTRL _SFR_MEM8(0x0220) -#define ADCA_CH0_MUXCTRL _SFR_MEM8(0x0221) -#define ADCA_CH0_INTCTRL _SFR_MEM8(0x0222) -#define ADCA_CH0_INTFLAGS _SFR_MEM8(0x0223) -#define ADCA_CH0_RES _SFR_MEM16(0x0224) -#define ADCA_CH0_SCAN _SFR_MEM8(0x0226) - -/* AC - Analog Comparator */ -#define ACA_AC0CTRL _SFR_MEM8(0x0380) -#define ACA_AC1CTRL _SFR_MEM8(0x0381) -#define ACA_AC0MUXCTRL _SFR_MEM8(0x0382) -#define ACA_AC1MUXCTRL _SFR_MEM8(0x0383) -#define ACA_CTRLA _SFR_MEM8(0x0384) -#define ACA_CTRLB _SFR_MEM8(0x0385) -#define ACA_WINCTRL _SFR_MEM8(0x0386) -#define ACA_STATUS _SFR_MEM8(0x0387) - -/* RTC - Real-Time Counter */ -#define RTC_CTRL _SFR_MEM8(0x0400) -#define RTC_STATUS _SFR_MEM8(0x0401) -#define RTC_INTCTRL _SFR_MEM8(0x0402) -#define RTC_INTFLAGS _SFR_MEM8(0x0403) -#define RTC_TEMP _SFR_MEM8(0x0404) -#define RTC_CNT _SFR_MEM16(0x0408) -#define RTC_PER _SFR_MEM16(0x040A) -#define RTC_COMP _SFR_MEM16(0x040C) - -/* TWI - Two-Wire Interface */ -#define TWIC_CTRL _SFR_MEM8(0x0480) -#define TWIC_MASTER_CTRLA _SFR_MEM8(0x0481) -#define TWIC_MASTER_CTRLB _SFR_MEM8(0x0482) -#define TWIC_MASTER_CTRLC _SFR_MEM8(0x0483) -#define TWIC_MASTER_STATUS _SFR_MEM8(0x0484) -#define TWIC_MASTER_BAUD _SFR_MEM8(0x0485) -#define TWIC_MASTER_ADDR _SFR_MEM8(0x0486) -#define TWIC_MASTER_DATA _SFR_MEM8(0x0487) -#define TWIC_SLAVE_CTRLA _SFR_MEM8(0x0488) -#define TWIC_SLAVE_CTRLB _SFR_MEM8(0x0489) -#define TWIC_SLAVE_STATUS _SFR_MEM8(0x048A) -#define TWIC_SLAVE_ADDR _SFR_MEM8(0x048B) -#define TWIC_SLAVE_DATA _SFR_MEM8(0x048C) -#define TWIC_SLAVE_ADDRMASK _SFR_MEM8(0x048D) - -/* TWI - Two-Wire Interface */ -#define TWIE_CTRL _SFR_MEM8(0x04A0) -#define TWIE_MASTER_CTRLA _SFR_MEM8(0x04A1) -#define TWIE_MASTER_CTRLB _SFR_MEM8(0x04A2) -#define TWIE_MASTER_CTRLC _SFR_MEM8(0x04A3) -#define TWIE_MASTER_STATUS _SFR_MEM8(0x04A4) -#define TWIE_MASTER_BAUD _SFR_MEM8(0x04A5) -#define TWIE_MASTER_ADDR _SFR_MEM8(0x04A6) -#define TWIE_MASTER_DATA _SFR_MEM8(0x04A7) -#define TWIE_SLAVE_CTRLA _SFR_MEM8(0x04A8) -#define TWIE_SLAVE_CTRLB _SFR_MEM8(0x04A9) -#define TWIE_SLAVE_STATUS _SFR_MEM8(0x04AA) -#define TWIE_SLAVE_ADDR _SFR_MEM8(0x04AB) -#define TWIE_SLAVE_DATA _SFR_MEM8(0x04AC) -#define TWIE_SLAVE_ADDRMASK _SFR_MEM8(0x04AD) - -/* PORT - I/O Ports */ -#define PORTA_DIR _SFR_MEM8(0x0600) -#define PORTA_DIRSET _SFR_MEM8(0x0601) -#define PORTA_DIRCLR _SFR_MEM8(0x0602) -#define PORTA_DIRTGL _SFR_MEM8(0x0603) -#define PORTA_OUT _SFR_MEM8(0x0604) -#define PORTA_OUTSET _SFR_MEM8(0x0605) -#define PORTA_OUTCLR _SFR_MEM8(0x0606) -#define PORTA_OUTTGL _SFR_MEM8(0x0607) -#define PORTA_IN _SFR_MEM8(0x0608) -#define PORTA_INTCTRL _SFR_MEM8(0x0609) -#define PORTA_INT0MASK _SFR_MEM8(0x060A) -#define PORTA_INT1MASK _SFR_MEM8(0x060B) -#define PORTA_INTFLAGS _SFR_MEM8(0x060C) -#define PORTA_REMAP _SFR_MEM8(0x060E) -#define PORTA_PIN0CTRL _SFR_MEM8(0x0610) -#define PORTA_PIN1CTRL _SFR_MEM8(0x0611) -#define PORTA_PIN2CTRL _SFR_MEM8(0x0612) -#define PORTA_PIN3CTRL _SFR_MEM8(0x0613) -#define PORTA_PIN4CTRL _SFR_MEM8(0x0614) -#define PORTA_PIN5CTRL _SFR_MEM8(0x0615) -#define PORTA_PIN6CTRL _SFR_MEM8(0x0616) -#define PORTA_PIN7CTRL _SFR_MEM8(0x0617) - -/* PORT - I/O Ports */ -#define PORTB_DIR _SFR_MEM8(0x0620) -#define PORTB_DIRSET _SFR_MEM8(0x0621) -#define PORTB_DIRCLR _SFR_MEM8(0x0622) -#define PORTB_DIRTGL _SFR_MEM8(0x0623) -#define PORTB_OUT _SFR_MEM8(0x0624) -#define PORTB_OUTSET _SFR_MEM8(0x0625) -#define PORTB_OUTCLR _SFR_MEM8(0x0626) -#define PORTB_OUTTGL _SFR_MEM8(0x0627) -#define PORTB_IN _SFR_MEM8(0x0628) -#define PORTB_INTCTRL _SFR_MEM8(0x0629) -#define PORTB_INT0MASK _SFR_MEM8(0x062A) -#define PORTB_INT1MASK _SFR_MEM8(0x062B) -#define PORTB_INTFLAGS _SFR_MEM8(0x062C) -#define PORTB_REMAP _SFR_MEM8(0x062E) -#define PORTB_PIN0CTRL _SFR_MEM8(0x0630) -#define PORTB_PIN1CTRL _SFR_MEM8(0x0631) -#define PORTB_PIN2CTRL _SFR_MEM8(0x0632) -#define PORTB_PIN3CTRL _SFR_MEM8(0x0633) -#define PORTB_PIN4CTRL _SFR_MEM8(0x0634) -#define PORTB_PIN5CTRL _SFR_MEM8(0x0635) -#define PORTB_PIN6CTRL _SFR_MEM8(0x0636) -#define PORTB_PIN7CTRL _SFR_MEM8(0x0637) - -/* PORT - I/O Ports */ -#define PORTC_DIR _SFR_MEM8(0x0640) -#define PORTC_DIRSET _SFR_MEM8(0x0641) -#define PORTC_DIRCLR _SFR_MEM8(0x0642) -#define PORTC_DIRTGL _SFR_MEM8(0x0643) -#define PORTC_OUT _SFR_MEM8(0x0644) -#define PORTC_OUTSET _SFR_MEM8(0x0645) -#define PORTC_OUTCLR _SFR_MEM8(0x0646) -#define PORTC_OUTTGL _SFR_MEM8(0x0647) -#define PORTC_IN _SFR_MEM8(0x0648) -#define PORTC_INTCTRL _SFR_MEM8(0x0649) -#define PORTC_INT0MASK _SFR_MEM8(0x064A) -#define PORTC_INT1MASK _SFR_MEM8(0x064B) -#define PORTC_INTFLAGS _SFR_MEM8(0x064C) -#define PORTC_REMAP _SFR_MEM8(0x064E) -#define PORTC_PIN0CTRL _SFR_MEM8(0x0650) -#define PORTC_PIN1CTRL _SFR_MEM8(0x0651) -#define PORTC_PIN2CTRL _SFR_MEM8(0x0652) -#define PORTC_PIN3CTRL _SFR_MEM8(0x0653) -#define PORTC_PIN4CTRL _SFR_MEM8(0x0654) -#define PORTC_PIN5CTRL _SFR_MEM8(0x0655) -#define PORTC_PIN6CTRL _SFR_MEM8(0x0656) -#define PORTC_PIN7CTRL _SFR_MEM8(0x0657) - -/* PORT - I/O Ports */ -#define PORTD_DIR _SFR_MEM8(0x0660) -#define PORTD_DIRSET _SFR_MEM8(0x0661) -#define PORTD_DIRCLR _SFR_MEM8(0x0662) -#define PORTD_DIRTGL _SFR_MEM8(0x0663) -#define PORTD_OUT _SFR_MEM8(0x0664) -#define PORTD_OUTSET _SFR_MEM8(0x0665) -#define PORTD_OUTCLR _SFR_MEM8(0x0666) -#define PORTD_OUTTGL _SFR_MEM8(0x0667) -#define PORTD_IN _SFR_MEM8(0x0668) -#define PORTD_INTCTRL _SFR_MEM8(0x0669) -#define PORTD_INT0MASK _SFR_MEM8(0x066A) -#define PORTD_INT1MASK _SFR_MEM8(0x066B) -#define PORTD_INTFLAGS _SFR_MEM8(0x066C) -#define PORTD_REMAP _SFR_MEM8(0x066E) -#define PORTD_PIN0CTRL _SFR_MEM8(0x0670) -#define PORTD_PIN1CTRL _SFR_MEM8(0x0671) -#define PORTD_PIN2CTRL _SFR_MEM8(0x0672) -#define PORTD_PIN3CTRL _SFR_MEM8(0x0673) -#define PORTD_PIN4CTRL _SFR_MEM8(0x0674) -#define PORTD_PIN5CTRL _SFR_MEM8(0x0675) -#define PORTD_PIN6CTRL _SFR_MEM8(0x0676) -#define PORTD_PIN7CTRL _SFR_MEM8(0x0677) - -/* PORT - I/O Ports */ -#define PORTE_DIR _SFR_MEM8(0x0680) -#define PORTE_DIRSET _SFR_MEM8(0x0681) -#define PORTE_DIRCLR _SFR_MEM8(0x0682) -#define PORTE_DIRTGL _SFR_MEM8(0x0683) -#define PORTE_OUT _SFR_MEM8(0x0684) -#define PORTE_OUTSET _SFR_MEM8(0x0685) -#define PORTE_OUTCLR _SFR_MEM8(0x0686) -#define PORTE_OUTTGL _SFR_MEM8(0x0687) -#define PORTE_IN _SFR_MEM8(0x0688) -#define PORTE_INTCTRL _SFR_MEM8(0x0689) -#define PORTE_INT0MASK _SFR_MEM8(0x068A) -#define PORTE_INT1MASK _SFR_MEM8(0x068B) -#define PORTE_INTFLAGS _SFR_MEM8(0x068C) -#define PORTE_REMAP _SFR_MEM8(0x068E) -#define PORTE_PIN0CTRL _SFR_MEM8(0x0690) -#define PORTE_PIN1CTRL _SFR_MEM8(0x0691) -#define PORTE_PIN2CTRL _SFR_MEM8(0x0692) -#define PORTE_PIN3CTRL _SFR_MEM8(0x0693) -#define PORTE_PIN4CTRL _SFR_MEM8(0x0694) -#define PORTE_PIN5CTRL _SFR_MEM8(0x0695) -#define PORTE_PIN6CTRL _SFR_MEM8(0x0696) -#define PORTE_PIN7CTRL _SFR_MEM8(0x0697) - -/* PORT - I/O Ports */ -#define PORTR_DIR _SFR_MEM8(0x07E0) -#define PORTR_DIRSET _SFR_MEM8(0x07E1) -#define PORTR_DIRCLR _SFR_MEM8(0x07E2) -#define PORTR_DIRTGL _SFR_MEM8(0x07E3) -#define PORTR_OUT _SFR_MEM8(0x07E4) -#define PORTR_OUTSET _SFR_MEM8(0x07E5) -#define PORTR_OUTCLR _SFR_MEM8(0x07E6) -#define PORTR_OUTTGL _SFR_MEM8(0x07E7) -#define PORTR_IN _SFR_MEM8(0x07E8) -#define PORTR_INTCTRL _SFR_MEM8(0x07E9) -#define PORTR_INT0MASK _SFR_MEM8(0x07EA) -#define PORTR_INT1MASK _SFR_MEM8(0x07EB) -#define PORTR_INTFLAGS _SFR_MEM8(0x07EC) -#define PORTR_REMAP _SFR_MEM8(0x07EE) -#define PORTR_PIN0CTRL _SFR_MEM8(0x07F0) -#define PORTR_PIN1CTRL _SFR_MEM8(0x07F1) -#define PORTR_PIN2CTRL _SFR_MEM8(0x07F2) -#define PORTR_PIN3CTRL _SFR_MEM8(0x07F3) -#define PORTR_PIN4CTRL _SFR_MEM8(0x07F4) -#define PORTR_PIN5CTRL _SFR_MEM8(0x07F5) -#define PORTR_PIN6CTRL _SFR_MEM8(0x07F6) -#define PORTR_PIN7CTRL _SFR_MEM8(0x07F7) - -/* TC0 - 16-bit Timer/Counter 0 */ -#define TCC0_CTRLA _SFR_MEM8(0x0800) -#define TCC0_CTRLB _SFR_MEM8(0x0801) -#define TCC0_CTRLC _SFR_MEM8(0x0802) -#define TCC0_CTRLD _SFR_MEM8(0x0803) -#define TCC0_CTRLE _SFR_MEM8(0x0804) -#define TCC0_INTCTRLA _SFR_MEM8(0x0806) -#define TCC0_INTCTRLB _SFR_MEM8(0x0807) -#define TCC0_CTRLFCLR _SFR_MEM8(0x0808) -#define TCC0_CTRLFSET _SFR_MEM8(0x0809) -#define TCC0_CTRLGCLR _SFR_MEM8(0x080A) -#define TCC0_CTRLGSET _SFR_MEM8(0x080B) -#define TCC0_INTFLAGS _SFR_MEM8(0x080C) -#define TCC0_TEMP _SFR_MEM8(0x080F) -#define TCC0_CNT _SFR_MEM16(0x0820) -#define TCC0_PER _SFR_MEM16(0x0826) -#define TCC0_CCA _SFR_MEM16(0x0828) -#define TCC0_CCB _SFR_MEM16(0x082A) -#define TCC0_CCC _SFR_MEM16(0x082C) -#define TCC0_CCD _SFR_MEM16(0x082E) -#define TCC0_PERBUF _SFR_MEM16(0x0836) -#define TCC0_CCABUF _SFR_MEM16(0x0838) -#define TCC0_CCBBUF _SFR_MEM16(0x083A) -#define TCC0_CCCBUF _SFR_MEM16(0x083C) -#define TCC0_CCDBUF _SFR_MEM16(0x083E) - -/* TC2 - 16-bit Timer/Counter type 2 */ -#define TCC2_CTRLA _SFR_MEM8(0x0800) -#define TCC2_CTRLB _SFR_MEM8(0x0801) -#define TCC2_CTRLC _SFR_MEM8(0x0802) -#define TCC2_CTRLE _SFR_MEM8(0x0804) -#define TCC2_INTCTRLA _SFR_MEM8(0x0806) -#define TCC2_INTCTRLB _SFR_MEM8(0x0807) -#define TCC2_CTRLF _SFR_MEM8(0x0809) -#define TCC2_INTFLAGS _SFR_MEM8(0x080C) -#define TCC2_LCNT _SFR_MEM8(0x0820) -#define TCC2_HCNT _SFR_MEM8(0x0821) -#define TCC2_LPER _SFR_MEM8(0x0826) -#define TCC2_HPER _SFR_MEM8(0x0827) -#define TCC2_LCMPA _SFR_MEM8(0x0828) -#define TCC2_HCMPA _SFR_MEM8(0x0829) -#define TCC2_LCMPB _SFR_MEM8(0x082A) -#define TCC2_HCMPB _SFR_MEM8(0x082B) -#define TCC2_LCMPC _SFR_MEM8(0x082C) -#define TCC2_HCMPC _SFR_MEM8(0x082D) -#define TCC2_LCMPD _SFR_MEM8(0x082E) -#define TCC2_HCMPD _SFR_MEM8(0x082F) - -/* TC1 - 16-bit Timer/Counter 1 */ -#define TCC1_CTRLA _SFR_MEM8(0x0840) -#define TCC1_CTRLB _SFR_MEM8(0x0841) -#define TCC1_CTRLC _SFR_MEM8(0x0842) -#define TCC1_CTRLD _SFR_MEM8(0x0843) -#define TCC1_CTRLE _SFR_MEM8(0x0844) -#define TCC1_INTCTRLA _SFR_MEM8(0x0846) -#define TCC1_INTCTRLB _SFR_MEM8(0x0847) -#define TCC1_CTRLFCLR _SFR_MEM8(0x0848) -#define TCC1_CTRLFSET _SFR_MEM8(0x0849) -#define TCC1_CTRLGCLR _SFR_MEM8(0x084A) -#define TCC1_CTRLGSET _SFR_MEM8(0x084B) -#define TCC1_INTFLAGS _SFR_MEM8(0x084C) -#define TCC1_TEMP _SFR_MEM8(0x084F) -#define TCC1_CNT _SFR_MEM16(0x0860) -#define TCC1_PER _SFR_MEM16(0x0866) -#define TCC1_CCA _SFR_MEM16(0x0868) -#define TCC1_CCB _SFR_MEM16(0x086A) -#define TCC1_PERBUF _SFR_MEM16(0x0876) -#define TCC1_CCABUF _SFR_MEM16(0x0878) -#define TCC1_CCBBUF _SFR_MEM16(0x087A) - -/* AWEX - Advanced Waveform Extension */ -#define AWEXC_CTRL _SFR_MEM8(0x0880) -#define AWEXC_FDEMASK _SFR_MEM8(0x0882) -#define AWEXC_FDCTRL _SFR_MEM8(0x0883) -#define AWEXC_STATUS _SFR_MEM8(0x0884) -#define AWEXC_STATUSSET _SFR_MEM8(0x0885) -#define AWEXC_DTBOTH _SFR_MEM8(0x0886) -#define AWEXC_DTBOTHBUF _SFR_MEM8(0x0887) -#define AWEXC_DTLS _SFR_MEM8(0x0888) -#define AWEXC_DTHS _SFR_MEM8(0x0889) -#define AWEXC_DTLSBUF _SFR_MEM8(0x088A) -#define AWEXC_DTHSBUF _SFR_MEM8(0x088B) -#define AWEXC_OUTOVEN _SFR_MEM8(0x088C) - -/* HIRES - High-Resolution Extension */ -#define HIRESC_CTRLA _SFR_MEM8(0x0890) - -/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ -#define USARTC0_DATA _SFR_MEM8(0x08A0) -#define USARTC0_STATUS _SFR_MEM8(0x08A1) -#define USARTC0_CTRLA _SFR_MEM8(0x08A3) -#define USARTC0_CTRLB _SFR_MEM8(0x08A4) -#define USARTC0_CTRLC _SFR_MEM8(0x08A5) -#define USARTC0_BAUDCTRLA _SFR_MEM8(0x08A6) -#define USARTC0_BAUDCTRLB _SFR_MEM8(0x08A7) - -/* SPI - Serial Peripheral Interface */ -#define SPIC_CTRL _SFR_MEM8(0x08C0) -#define SPIC_INTCTRL _SFR_MEM8(0x08C1) -#define SPIC_STATUS _SFR_MEM8(0x08C2) -#define SPIC_DATA _SFR_MEM8(0x08C3) - -/* IRCOM - IR Communication Module */ -#define IRCOM_CTRL _SFR_MEM8(0x08F8) -#define IRCOM_TXPLCTRL _SFR_MEM8(0x08F9) -#define IRCOM_RXPLCTRL _SFR_MEM8(0x08FA) - -/* TC0 - 16-bit Timer/Counter 0 */ -#define TCD0_CTRLA _SFR_MEM8(0x0900) -#define TCD0_CTRLB _SFR_MEM8(0x0901) -#define TCD0_CTRLC _SFR_MEM8(0x0902) -#define TCD0_CTRLD _SFR_MEM8(0x0903) -#define TCD0_CTRLE _SFR_MEM8(0x0904) -#define TCD0_INTCTRLA _SFR_MEM8(0x0906) -#define TCD0_INTCTRLB _SFR_MEM8(0x0907) -#define TCD0_CTRLFCLR _SFR_MEM8(0x0908) -#define TCD0_CTRLFSET _SFR_MEM8(0x0909) -#define TCD0_CTRLGCLR _SFR_MEM8(0x090A) -#define TCD0_CTRLGSET _SFR_MEM8(0x090B) -#define TCD0_INTFLAGS _SFR_MEM8(0x090C) -#define TCD0_TEMP _SFR_MEM8(0x090F) -#define TCD0_CNT _SFR_MEM16(0x0920) -#define TCD0_PER _SFR_MEM16(0x0926) -#define TCD0_CCA _SFR_MEM16(0x0928) -#define TCD0_CCB _SFR_MEM16(0x092A) -#define TCD0_CCC _SFR_MEM16(0x092C) -#define TCD0_CCD _SFR_MEM16(0x092E) -#define TCD0_PERBUF _SFR_MEM16(0x0936) -#define TCD0_CCABUF _SFR_MEM16(0x0938) -#define TCD0_CCBBUF _SFR_MEM16(0x093A) -#define TCD0_CCCBUF _SFR_MEM16(0x093C) -#define TCD0_CCDBUF _SFR_MEM16(0x093E) - -/* TC2 - 16-bit Timer/Counter type 2 */ -#define TCD2_CTRLA _SFR_MEM8(0x0900) -#define TCD2_CTRLB _SFR_MEM8(0x0901) -#define TCD2_CTRLC _SFR_MEM8(0x0902) -#define TCD2_CTRLE _SFR_MEM8(0x0904) -#define TCD2_INTCTRLA _SFR_MEM8(0x0906) -#define TCD2_INTCTRLB _SFR_MEM8(0x0907) -#define TCD2_CTRLF _SFR_MEM8(0x0909) -#define TCD2_INTFLAGS _SFR_MEM8(0x090C) -#define TCD2_LCNT _SFR_MEM8(0x0920) -#define TCD2_HCNT _SFR_MEM8(0x0921) -#define TCD2_LPER _SFR_MEM8(0x0926) -#define TCD2_HPER _SFR_MEM8(0x0927) -#define TCD2_LCMPA _SFR_MEM8(0x0928) -#define TCD2_HCMPA _SFR_MEM8(0x0929) -#define TCD2_LCMPB _SFR_MEM8(0x092A) -#define TCD2_HCMPB _SFR_MEM8(0x092B) -#define TCD2_LCMPC _SFR_MEM8(0x092C) -#define TCD2_HCMPC _SFR_MEM8(0x092D) -#define TCD2_LCMPD _SFR_MEM8(0x092E) -#define TCD2_HCMPD _SFR_MEM8(0x092F) - -/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ -#define USARTD0_DATA _SFR_MEM8(0x09A0) -#define USARTD0_STATUS _SFR_MEM8(0x09A1) -#define USARTD0_CTRLA _SFR_MEM8(0x09A3) -#define USARTD0_CTRLB _SFR_MEM8(0x09A4) -#define USARTD0_CTRLC _SFR_MEM8(0x09A5) -#define USARTD0_BAUDCTRLA _SFR_MEM8(0x09A6) -#define USARTD0_BAUDCTRLB _SFR_MEM8(0x09A7) - -/* SPI - Serial Peripheral Interface */ -#define SPID_CTRL _SFR_MEM8(0x09C0) -#define SPID_INTCTRL _SFR_MEM8(0x09C1) -#define SPID_STATUS _SFR_MEM8(0x09C2) -#define SPID_DATA _SFR_MEM8(0x09C3) - -/* TC0 - 16-bit Timer/Counter 0 */ -#define TCE0_CTRLA _SFR_MEM8(0x0A00) -#define TCE0_CTRLB _SFR_MEM8(0x0A01) -#define TCE0_CTRLC _SFR_MEM8(0x0A02) -#define TCE0_CTRLD _SFR_MEM8(0x0A03) -#define TCE0_CTRLE _SFR_MEM8(0x0A04) -#define TCE0_INTCTRLA _SFR_MEM8(0x0A06) -#define TCE0_INTCTRLB _SFR_MEM8(0x0A07) -#define TCE0_CTRLFCLR _SFR_MEM8(0x0A08) -#define TCE0_CTRLFSET _SFR_MEM8(0x0A09) -#define TCE0_CTRLGCLR _SFR_MEM8(0x0A0A) -#define TCE0_CTRLGSET _SFR_MEM8(0x0A0B) -#define TCE0_INTFLAGS _SFR_MEM8(0x0A0C) -#define TCE0_TEMP _SFR_MEM8(0x0A0F) -#define TCE0_CNT _SFR_MEM16(0x0A20) -#define TCE0_PER _SFR_MEM16(0x0A26) -#define TCE0_CCA _SFR_MEM16(0x0A28) -#define TCE0_CCB _SFR_MEM16(0x0A2A) -#define TCE0_CCC _SFR_MEM16(0x0A2C) -#define TCE0_CCD _SFR_MEM16(0x0A2E) -#define TCE0_PERBUF _SFR_MEM16(0x0A36) -#define TCE0_CCABUF _SFR_MEM16(0x0A38) -#define TCE0_CCBBUF _SFR_MEM16(0x0A3A) -#define TCE0_CCCBUF _SFR_MEM16(0x0A3C) -#define TCE0_CCDBUF _SFR_MEM16(0x0A3E) - - - -/*================== Bitfield Definitions ================== */ - -/* VPORT - Virtual Ports */ -/* VPORT.INTFLAGS bit masks and bit positions */ -#define VPORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ -#define VPORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ - -#define VPORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ -#define VPORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ - -/* XOCD - On-Chip Debug System */ -/* OCD.OCDR0 bit masks and bit positions */ -#define OCD_OCDRD_gm 0xFF /* OCDR Dirty group mask. */ -#define OCD_OCDRD_gp 0 /* OCDR Dirty group position. */ -#define OCD_OCDRD0_bm (1<<0) /* OCDR Dirty bit 0 mask. */ -#define OCD_OCDRD0_bp 0 /* OCDR Dirty bit 0 position. */ -#define OCD_OCDRD1_bm (1<<1) /* OCDR Dirty bit 1 mask. */ -#define OCD_OCDRD1_bp 1 /* OCDR Dirty bit 1 position. */ -#define OCD_OCDRD2_bm (1<<2) /* OCDR Dirty bit 2 mask. */ -#define OCD_OCDRD2_bp 2 /* OCDR Dirty bit 2 position. */ -#define OCD_OCDRD3_bm (1<<3) /* OCDR Dirty bit 3 mask. */ -#define OCD_OCDRD3_bp 3 /* OCDR Dirty bit 3 position. */ -#define OCD_OCDRD4_bm (1<<4) /* OCDR Dirty bit 4 mask. */ -#define OCD_OCDRD4_bp 4 /* OCDR Dirty bit 4 position. */ -#define OCD_OCDRD5_bm (1<<5) /* OCDR Dirty bit 5 mask. */ -#define OCD_OCDRD5_bp 5 /* OCDR Dirty bit 5 position. */ -#define OCD_OCDRD6_bm (1<<6) /* OCDR Dirty bit 6 mask. */ -#define OCD_OCDRD6_bp 6 /* OCDR Dirty bit 6 position. */ -#define OCD_OCDRD7_bm (1<<7) /* OCDR Dirty bit 7 mask. */ -#define OCD_OCDRD7_bp 7 /* OCDR Dirty bit 7 position. */ - -/* OCD.OCDR1 bit masks and bit positions */ -/* OCD_OCDRD Predefined. */ -/* OCD_OCDRD Predefined. */ - -/* CPU - CPU */ -/* CPU.CCP bit masks and bit positions */ -#define CPU_CCP_gm 0xFF /* CCP signature group mask. */ -#define CPU_CCP_gp 0 /* CCP signature group position. */ -#define CPU_CCP0_bm (1<<0) /* CCP signature bit 0 mask. */ -#define CPU_CCP0_bp 0 /* CCP signature bit 0 position. */ -#define CPU_CCP1_bm (1<<1) /* CCP signature bit 1 mask. */ -#define CPU_CCP1_bp 1 /* CCP signature bit 1 position. */ -#define CPU_CCP2_bm (1<<2) /* CCP signature bit 2 mask. */ -#define CPU_CCP2_bp 2 /* CCP signature bit 2 position. */ -#define CPU_CCP3_bm (1<<3) /* CCP signature bit 3 mask. */ -#define CPU_CCP3_bp 3 /* CCP signature bit 3 position. */ -#define CPU_CCP4_bm (1<<4) /* CCP signature bit 4 mask. */ -#define CPU_CCP4_bp 4 /* CCP signature bit 4 position. */ -#define CPU_CCP5_bm (1<<5) /* CCP signature bit 5 mask. */ -#define CPU_CCP5_bp 5 /* CCP signature bit 5 position. */ -#define CPU_CCP6_bm (1<<6) /* CCP signature bit 6 mask. */ -#define CPU_CCP6_bp 6 /* CCP signature bit 6 position. */ -#define CPU_CCP7_bm (1<<7) /* CCP signature bit 7 mask. */ -#define CPU_CCP7_bp 7 /* CCP signature bit 7 position. */ - -/* CPU.SREG bit masks and bit positions */ -#define CPU_I_bm 0x80 /* Global Interrupt Enable Flag bit mask. */ -#define CPU_I_bp 7 /* Global Interrupt Enable Flag bit position. */ - -#define CPU_T_bm 0x40 /* Transfer Bit bit mask. */ -#define CPU_T_bp 6 /* Transfer Bit bit position. */ - -#define CPU_H_bm 0x20 /* Half Carry Flag bit mask. */ -#define CPU_H_bp 5 /* Half Carry Flag bit position. */ - -#define CPU_S_bm 0x10 /* N Exclusive Or V Flag bit mask. */ -#define CPU_S_bp 4 /* N Exclusive Or V Flag bit position. */ - -#define CPU_V_bm 0x08 /* Two's Complement Overflow Flag bit mask. */ -#define CPU_V_bp 3 /* Two's Complement Overflow Flag bit position. */ - -#define CPU_N_bm 0x04 /* Negative Flag bit mask. */ -#define CPU_N_bp 2 /* Negative Flag bit position. */ - -#define CPU_Z_bm 0x02 /* Zero Flag bit mask. */ -#define CPU_Z_bp 1 /* Zero Flag bit position. */ - -#define CPU_C_bm 0x01 /* Carry Flag bit mask. */ -#define CPU_C_bp 0 /* Carry Flag bit position. */ - -/* CLK - Clock System */ -/* CLK.CTRL bit masks and bit positions */ -#define CLK_SCLKSEL_gm 0x07 /* System Clock Selection group mask. */ -#define CLK_SCLKSEL_gp 0 /* System Clock Selection group position. */ -#define CLK_SCLKSEL0_bm (1<<0) /* System Clock Selection bit 0 mask. */ -#define CLK_SCLKSEL0_bp 0 /* System Clock Selection bit 0 position. */ -#define CLK_SCLKSEL1_bm (1<<1) /* System Clock Selection bit 1 mask. */ -#define CLK_SCLKSEL1_bp 1 /* System Clock Selection bit 1 position. */ -#define CLK_SCLKSEL2_bm (1<<2) /* System Clock Selection bit 2 mask. */ -#define CLK_SCLKSEL2_bp 2 /* System Clock Selection bit 2 position. */ - -/* CLK.PSCTRL bit masks and bit positions */ -#define CLK_PSADIV_gm 0x7C /* Prescaler A Division Factor group mask. */ -#define CLK_PSADIV_gp 2 /* Prescaler A Division Factor group position. */ -#define CLK_PSADIV0_bm (1<<2) /* Prescaler A Division Factor bit 0 mask. */ -#define CLK_PSADIV0_bp 2 /* Prescaler A Division Factor bit 0 position. */ -#define CLK_PSADIV1_bm (1<<3) /* Prescaler A Division Factor bit 1 mask. */ -#define CLK_PSADIV1_bp 3 /* Prescaler A Division Factor bit 1 position. */ -#define CLK_PSADIV2_bm (1<<4) /* Prescaler A Division Factor bit 2 mask. */ -#define CLK_PSADIV2_bp 4 /* Prescaler A Division Factor bit 2 position. */ -#define CLK_PSADIV3_bm (1<<5) /* Prescaler A Division Factor bit 3 mask. */ -#define CLK_PSADIV3_bp 5 /* Prescaler A Division Factor bit 3 position. */ -#define CLK_PSADIV4_bm (1<<6) /* Prescaler A Division Factor bit 4 mask. */ -#define CLK_PSADIV4_bp 6 /* Prescaler A Division Factor bit 4 position. */ - -#define CLK_PSBCDIV_gm 0x03 /* Prescaler B and C Division factor group mask. */ -#define CLK_PSBCDIV_gp 0 /* Prescaler B and C Division factor group position. */ -#define CLK_PSBCDIV0_bm (1<<0) /* Prescaler B and C Division factor bit 0 mask. */ -#define CLK_PSBCDIV0_bp 0 /* Prescaler B and C Division factor bit 0 position. */ -#define CLK_PSBCDIV1_bm (1<<1) /* Prescaler B and C Division factor bit 1 mask. */ -#define CLK_PSBCDIV1_bp 1 /* Prescaler B and C Division factor bit 1 position. */ - -/* CLK.LOCK bit masks and bit positions */ -#define CLK_LOCK_bm 0x01 /* Clock System Lock bit mask. */ -#define CLK_LOCK_bp 0 /* Clock System Lock bit position. */ - -/* CLK.RTCCTRL bit masks and bit positions */ -#define CLK_RTCSRC_gm 0x0E /* Clock Source group mask. */ -#define CLK_RTCSRC_gp 1 /* Clock Source group position. */ -#define CLK_RTCSRC0_bm (1<<1) /* Clock Source bit 0 mask. */ -#define CLK_RTCSRC0_bp 1 /* Clock Source bit 0 position. */ -#define CLK_RTCSRC1_bm (1<<2) /* Clock Source bit 1 mask. */ -#define CLK_RTCSRC1_bp 2 /* Clock Source bit 1 position. */ -#define CLK_RTCSRC2_bm (1<<3) /* Clock Source bit 2 mask. */ -#define CLK_RTCSRC2_bp 3 /* Clock Source bit 2 position. */ - -#define CLK_RTCEN_bm 0x01 /* Clock Source Enable bit mask. */ -#define CLK_RTCEN_bp 0 /* Clock Source Enable bit position. */ - -/* PR.PRGEN bit masks and bit positions */ -#define PR_RTC_bm 0x04 /* Real-time Counter bit mask. */ -#define PR_RTC_bp 2 /* Real-time Counter bit position. */ - -#define PR_EVSYS_bm 0x02 /* Event System bit mask. */ -#define PR_EVSYS_bp 1 /* Event System bit position. */ - -/* PR.PRPA bit masks and bit positions */ -#define PR_ADC_bm 0x02 /* Port A ADC bit mask. */ -#define PR_ADC_bp 1 /* Port A ADC bit position. */ - -#define PR_AC_bm 0x01 /* Port A Analog Comparator bit mask. */ -#define PR_AC_bp 0 /* Port A Analog Comparator bit position. */ - -/* PR.PRPC bit masks and bit positions */ -#define PR_TWI_bm 0x40 /* Port C Two-wire Interface bit mask. */ -#define PR_TWI_bp 6 /* Port C Two-wire Interface bit position. */ - -#define PR_USART0_bm 0x10 /* Port C USART0 bit mask. */ -#define PR_USART0_bp 4 /* Port C USART0 bit position. */ - -#define PR_SPI_bm 0x08 /* Port C SPI bit mask. */ -#define PR_SPI_bp 3 /* Port C SPI bit position. */ - -#define PR_HIRES_bm 0x04 /* Port C HIRES bit mask. */ -#define PR_HIRES_bp 2 /* Port C HIRES bit position. */ - -#define PR_TC1_bm 0x02 /* Port C Timer/Counter1 bit mask. */ -#define PR_TC1_bp 1 /* Port C Timer/Counter1 bit position. */ - -#define PR_TC0_bm 0x01 /* Port C Timer/Counter0 bit mask. */ -#define PR_TC0_bp 0 /* Port C Timer/Counter0 bit position. */ - -/* PR.PRPD bit masks and bit positions */ -/* PR_USART0 Predefined. */ -/* PR_USART0 Predefined. */ - -/* PR_SPI Predefined. */ -/* PR_SPI Predefined. */ - -/* PR_TC0 Predefined. */ -/* PR_TC0 Predefined. */ - -/* PR.PRPE bit masks and bit positions */ -/* PR_TWI Predefined. */ -/* PR_TWI Predefined. */ - -/* PR_USART0 Predefined. */ -/* PR_USART0 Predefined. */ - -/* PR_TC0 Predefined. */ -/* PR_TC0 Predefined. */ - -/* PR.PRPF bit masks and bit positions */ -/* PR_USART0 Predefined. */ -/* PR_USART0 Predefined. */ - -/* PR_TC0 Predefined. */ -/* PR_TC0 Predefined. */ - -/* SLEEP - Sleep Controller */ -/* SLEEP.CTRL bit masks and bit positions */ -#define SLEEP_SMODE_gm 0x0E /* Sleep Mode group mask. */ -#define SLEEP_SMODE_gp 1 /* Sleep Mode group position. */ -#define SLEEP_SMODE0_bm (1<<1) /* Sleep Mode bit 0 mask. */ -#define SLEEP_SMODE0_bp 1 /* Sleep Mode bit 0 position. */ -#define SLEEP_SMODE1_bm (1<<2) /* Sleep Mode bit 1 mask. */ -#define SLEEP_SMODE1_bp 2 /* Sleep Mode bit 1 position. */ -#define SLEEP_SMODE2_bm (1<<3) /* Sleep Mode bit 2 mask. */ -#define SLEEP_SMODE2_bp 3 /* Sleep Mode bit 2 position. */ - -#define SLEEP_SEN_bm 0x01 /* Sleep Enable bit mask. */ -#define SLEEP_SEN_bp 0 /* Sleep Enable bit position. */ - -/* OSC - Oscillator */ -/* OSC.CTRL bit masks and bit positions */ -#define OSC_PLLEN_bm 0x10 /* PLL Enable bit mask. */ -#define OSC_PLLEN_bp 4 /* PLL Enable bit position. */ - -#define OSC_XOSCEN_bm 0x08 /* External Oscillator Enable bit mask. */ -#define OSC_XOSCEN_bp 3 /* External Oscillator Enable bit position. */ - -#define OSC_RC32KEN_bm 0x04 /* Internal 32.768 kHz RC Oscillator Enable bit mask. */ -#define OSC_RC32KEN_bp 2 /* Internal 32.768 kHz RC Oscillator Enable bit position. */ - -#define OSC_RC32MEN_bm 0x02 /* Internal 32 MHz RC Oscillator Enable bit mask. */ -#define OSC_RC32MEN_bp 1 /* Internal 32 MHz RC Oscillator Enable bit position. */ - -#define OSC_RC2MEN_bm 0x01 /* Internal 2 MHz RC Oscillator Enable bit mask. */ -#define OSC_RC2MEN_bp 0 /* Internal 2 MHz RC Oscillator Enable bit position. */ - -/* OSC.STATUS bit masks and bit positions */ -#define OSC_PLLRDY_bm 0x10 /* PLL Ready bit mask. */ -#define OSC_PLLRDY_bp 4 /* PLL Ready bit position. */ - -#define OSC_XOSCRDY_bm 0x08 /* External Oscillator Ready bit mask. */ -#define OSC_XOSCRDY_bp 3 /* External Oscillator Ready bit position. */ - -#define OSC_RC32KRDY_bm 0x04 /* Internal 32.768 kHz RC Oscillator Ready bit mask. */ -#define OSC_RC32KRDY_bp 2 /* Internal 32.768 kHz RC Oscillator Ready bit position. */ - -#define OSC_RC32MRDY_bm 0x02 /* Internal 32 MHz RC Oscillator Ready bit mask. */ -#define OSC_RC32MRDY_bp 1 /* Internal 32 MHz RC Oscillator Ready bit position. */ - -#define OSC_RC2MRDY_bm 0x01 /* Internal 2 MHz RC Oscillator Ready bit mask. */ -#define OSC_RC2MRDY_bp 0 /* Internal 2 MHz RC Oscillator Ready bit position. */ - -/* OSC.XOSCCTRL bit masks and bit positions */ -#define OSC_FRQRANGE_gm 0xC0 /* Frequency Range group mask. */ -#define OSC_FRQRANGE_gp 6 /* Frequency Range group position. */ -#define OSC_FRQRANGE0_bm (1<<6) /* Frequency Range bit 0 mask. */ -#define OSC_FRQRANGE0_bp 6 /* Frequency Range bit 0 position. */ -#define OSC_FRQRANGE1_bm (1<<7) /* Frequency Range bit 1 mask. */ -#define OSC_FRQRANGE1_bp 7 /* Frequency Range bit 1 position. */ - -#define OSC_X32KLPM_bm 0x20 /* 32.768 kHz XTAL OSC Low-power Mode bit mask. */ -#define OSC_X32KLPM_bp 5 /* 32.768 kHz XTAL OSC Low-power Mode bit position. */ - -#define OSC_XOSCPWR_bm 0x10 /* 16 MHz Crystal Oscillator High Power mode bit mask. */ -#define OSC_XOSCPWR_bp 4 /* 16 MHz Crystal Oscillator High Power mode bit position. */ - -#define OSC_XOSCSEL_gm 0x0F /* External Oscillator Selection and Startup Time group mask. */ -#define OSC_XOSCSEL_gp 0 /* External Oscillator Selection and Startup Time group position. */ -#define OSC_XOSCSEL0_bm (1<<0) /* External Oscillator Selection and Startup Time bit 0 mask. */ -#define OSC_XOSCSEL0_bp 0 /* External Oscillator Selection and Startup Time bit 0 position. */ -#define OSC_XOSCSEL1_bm (1<<1) /* External Oscillator Selection and Startup Time bit 1 mask. */ -#define OSC_XOSCSEL1_bp 1 /* External Oscillator Selection and Startup Time bit 1 position. */ -#define OSC_XOSCSEL2_bm (1<<2) /* External Oscillator Selection and Startup Time bit 2 mask. */ -#define OSC_XOSCSEL2_bp 2 /* External Oscillator Selection and Startup Time bit 2 position. */ -#define OSC_XOSCSEL3_bm (1<<3) /* External Oscillator Selection and Startup Time bit 3 mask. */ -#define OSC_XOSCSEL3_bp 3 /* External Oscillator Selection and Startup Time bit 3 position. */ - -/* OSC.XOSCFAIL bit masks and bit positions */ -#define OSC_PLLFDIF_bm 0x08 /* PLL Failure Detection Interrupt Flag bit mask. */ -#define OSC_PLLFDIF_bp 3 /* PLL Failure Detection Interrupt Flag bit position. */ - -#define OSC_PLLFDEN_bm 0x04 /* PLL Failure Detection Enable bit mask. */ -#define OSC_PLLFDEN_bp 2 /* PLL Failure Detection Enable bit position. */ - -#define OSC_XOSCFDIF_bm 0x02 /* XOSC Failure Detection Interrupt Flag bit mask. */ -#define OSC_XOSCFDIF_bp 1 /* XOSC Failure Detection Interrupt Flag bit position. */ - -#define OSC_XOSCFDEN_bm 0x01 /* XOSC Failure Detection Enable bit mask. */ -#define OSC_XOSCFDEN_bp 0 /* XOSC Failure Detection Enable bit position. */ - -/* OSC.PLLCTRL bit masks and bit positions */ -#define OSC_PLLSRC_gm 0xC0 /* Clock Source group mask. */ -#define OSC_PLLSRC_gp 6 /* Clock Source group position. */ -#define OSC_PLLSRC0_bm (1<<6) /* Clock Source bit 0 mask. */ -#define OSC_PLLSRC0_bp 6 /* Clock Source bit 0 position. */ -#define OSC_PLLSRC1_bm (1<<7) /* Clock Source bit 1 mask. */ -#define OSC_PLLSRC1_bp 7 /* Clock Source bit 1 position. */ - -#define OSC_PLLDIV_bm 0x20 /* Divide by 2 bit mask. */ -#define OSC_PLLDIV_bp 5 /* Divide by 2 bit position. */ - -#define OSC_PLLFAC_gm 0x1F /* Multiplication Factor group mask. */ -#define OSC_PLLFAC_gp 0 /* Multiplication Factor group position. */ -#define OSC_PLLFAC0_bm (1<<0) /* Multiplication Factor bit 0 mask. */ -#define OSC_PLLFAC0_bp 0 /* Multiplication Factor bit 0 position. */ -#define OSC_PLLFAC1_bm (1<<1) /* Multiplication Factor bit 1 mask. */ -#define OSC_PLLFAC1_bp 1 /* Multiplication Factor bit 1 position. */ -#define OSC_PLLFAC2_bm (1<<2) /* Multiplication Factor bit 2 mask. */ -#define OSC_PLLFAC2_bp 2 /* Multiplication Factor bit 2 position. */ -#define OSC_PLLFAC3_bm (1<<3) /* Multiplication Factor bit 3 mask. */ -#define OSC_PLLFAC3_bp 3 /* Multiplication Factor bit 3 position. */ -#define OSC_PLLFAC4_bm (1<<4) /* Multiplication Factor bit 4 mask. */ -#define OSC_PLLFAC4_bp 4 /* Multiplication Factor bit 4 position. */ - -/* OSC.DFLLCTRL bit masks and bit positions */ -#define OSC_RC32MCREF_gm 0x06 /* 32 MHz DFLL Calibration Reference group mask. */ -#define OSC_RC32MCREF_gp 1 /* 32 MHz DFLL Calibration Reference group position. */ -#define OSC_RC32MCREF0_bm (1<<1) /* 32 MHz DFLL Calibration Reference bit 0 mask. */ -#define OSC_RC32MCREF0_bp 1 /* 32 MHz DFLL Calibration Reference bit 0 position. */ -#define OSC_RC32MCREF1_bm (1<<2) /* 32 MHz DFLL Calibration Reference bit 1 mask. */ -#define OSC_RC32MCREF1_bp 2 /* 32 MHz DFLL Calibration Reference bit 1 position. */ - -#define OSC_RC2MCREF_bm 0x01 /* 2 MHz DFLL Calibration Reference bit mask. */ -#define OSC_RC2MCREF_bp 0 /* 2 MHz DFLL Calibration Reference bit position. */ - -/* DFLL - DFLL */ -/* DFLL.CTRL bit masks and bit positions */ -#define DFLL_ENABLE_bm 0x01 /* DFLL Enable bit mask. */ -#define DFLL_ENABLE_bp 0 /* DFLL Enable bit position. */ - -/* DFLL.CALA bit masks and bit positions */ -#define DFLL_CALL_gm 0x7F /* DFLL Calibration Value A group mask. */ -#define DFLL_CALL_gp 0 /* DFLL Calibration Value A group position. */ -#define DFLL_CALL0_bm (1<<0) /* DFLL Calibration Value A bit 0 mask. */ -#define DFLL_CALL0_bp 0 /* DFLL Calibration Value A bit 0 position. */ -#define DFLL_CALL1_bm (1<<1) /* DFLL Calibration Value A bit 1 mask. */ -#define DFLL_CALL1_bp 1 /* DFLL Calibration Value A bit 1 position. */ -#define DFLL_CALL2_bm (1<<2) /* DFLL Calibration Value A bit 2 mask. */ -#define DFLL_CALL2_bp 2 /* DFLL Calibration Value A bit 2 position. */ -#define DFLL_CALL3_bm (1<<3) /* DFLL Calibration Value A bit 3 mask. */ -#define DFLL_CALL3_bp 3 /* DFLL Calibration Value A bit 3 position. */ -#define DFLL_CALL4_bm (1<<4) /* DFLL Calibration Value A bit 4 mask. */ -#define DFLL_CALL4_bp 4 /* DFLL Calibration Value A bit 4 position. */ -#define DFLL_CALL5_bm (1<<5) /* DFLL Calibration Value A bit 5 mask. */ -#define DFLL_CALL5_bp 5 /* DFLL Calibration Value A bit 5 position. */ -#define DFLL_CALL6_bm (1<<6) /* DFLL Calibration Value A bit 6 mask. */ -#define DFLL_CALL6_bp 6 /* DFLL Calibration Value A bit 6 position. */ - -/* DFLL.CALB bit masks and bit positions */ -#define DFLL_CALH_gm 0x3F /* DFLL Calibration Value B group mask. */ -#define DFLL_CALH_gp 0 /* DFLL Calibration Value B group position. */ -#define DFLL_CALH0_bm (1<<0) /* DFLL Calibration Value B bit 0 mask. */ -#define DFLL_CALH0_bp 0 /* DFLL Calibration Value B bit 0 position. */ -#define DFLL_CALH1_bm (1<<1) /* DFLL Calibration Value B bit 1 mask. */ -#define DFLL_CALH1_bp 1 /* DFLL Calibration Value B bit 1 position. */ -#define DFLL_CALH2_bm (1<<2) /* DFLL Calibration Value B bit 2 mask. */ -#define DFLL_CALH2_bp 2 /* DFLL Calibration Value B bit 2 position. */ -#define DFLL_CALH3_bm (1<<3) /* DFLL Calibration Value B bit 3 mask. */ -#define DFLL_CALH3_bp 3 /* DFLL Calibration Value B bit 3 position. */ -#define DFLL_CALH4_bm (1<<4) /* DFLL Calibration Value B bit 4 mask. */ -#define DFLL_CALH4_bp 4 /* DFLL Calibration Value B bit 4 position. */ -#define DFLL_CALH5_bm (1<<5) /* DFLL Calibration Value B bit 5 mask. */ -#define DFLL_CALH5_bp 5 /* DFLL Calibration Value B bit 5 position. */ - -/* RST - Reset */ -/* RST.STATUS bit masks and bit positions */ -#define RST_SDRF_bm 0x40 /* Spike Detection Reset Flag bit mask. */ -#define RST_SDRF_bp 6 /* Spike Detection Reset Flag bit position. */ - -#define RST_SRF_bm 0x20 /* Software Reset Flag bit mask. */ -#define RST_SRF_bp 5 /* Software Reset Flag bit position. */ - -#define RST_PDIRF_bm 0x10 /* Programming and Debug Interface Interface Reset Flag bit mask. */ -#define RST_PDIRF_bp 4 /* Programming and Debug Interface Interface Reset Flag bit position. */ - -#define RST_WDRF_bm 0x08 /* Watchdog Reset Flag bit mask. */ -#define RST_WDRF_bp 3 /* Watchdog Reset Flag bit position. */ - -#define RST_BORF_bm 0x04 /* Brown-out Reset Flag bit mask. */ -#define RST_BORF_bp 2 /* Brown-out Reset Flag bit position. */ - -#define RST_EXTRF_bm 0x02 /* External Reset Flag bit mask. */ -#define RST_EXTRF_bp 1 /* External Reset Flag bit position. */ - -#define RST_PORF_bm 0x01 /* Power-on Reset Flag bit mask. */ -#define RST_PORF_bp 0 /* Power-on Reset Flag bit position. */ - -/* RST.CTRL bit masks and bit positions */ -#define RST_SWRST_bm 0x01 /* Software Reset bit mask. */ -#define RST_SWRST_bp 0 /* Software Reset bit position. */ - -/* WDT - Watch-Dog Timer */ -/* WDT.CTRL bit masks and bit positions */ -#define WDT_PER_gm 0x3C /* Period group mask. */ -#define WDT_PER_gp 2 /* Period group position. */ -#define WDT_PER0_bm (1<<2) /* Period bit 0 mask. */ -#define WDT_PER0_bp 2 /* Period bit 0 position. */ -#define WDT_PER1_bm (1<<3) /* Period bit 1 mask. */ -#define WDT_PER1_bp 3 /* Period bit 1 position. */ -#define WDT_PER2_bm (1<<4) /* Period bit 2 mask. */ -#define WDT_PER2_bp 4 /* Period bit 2 position. */ -#define WDT_PER3_bm (1<<5) /* Period bit 3 mask. */ -#define WDT_PER3_bp 5 /* Period bit 3 position. */ - -#define WDT_ENABLE_bm 0x02 /* Enable bit mask. */ -#define WDT_ENABLE_bp 1 /* Enable bit position. */ - -#define WDT_CEN_bm 0x01 /* Change Enable bit mask. */ -#define WDT_CEN_bp 0 /* Change Enable bit position. */ - -/* WDT.WINCTRL bit masks and bit positions */ -#define WDT_WPER_gm 0x3C /* Windowed Mode Period group mask. */ -#define WDT_WPER_gp 2 /* Windowed Mode Period group position. */ -#define WDT_WPER0_bm (1<<2) /* Windowed Mode Period bit 0 mask. */ -#define WDT_WPER0_bp 2 /* Windowed Mode Period bit 0 position. */ -#define WDT_WPER1_bm (1<<3) /* Windowed Mode Period bit 1 mask. */ -#define WDT_WPER1_bp 3 /* Windowed Mode Period bit 1 position. */ -#define WDT_WPER2_bm (1<<4) /* Windowed Mode Period bit 2 mask. */ -#define WDT_WPER2_bp 4 /* Windowed Mode Period bit 2 position. */ -#define WDT_WPER3_bm (1<<5) /* Windowed Mode Period bit 3 mask. */ -#define WDT_WPER3_bp 5 /* Windowed Mode Period bit 3 position. */ - -#define WDT_WEN_bm 0x02 /* Windowed Mode Enable bit mask. */ -#define WDT_WEN_bp 1 /* Windowed Mode Enable bit position. */ - -#define WDT_WCEN_bm 0x01 /* Windowed Mode Change Enable bit mask. */ -#define WDT_WCEN_bp 0 /* Windowed Mode Change Enable bit position. */ - -/* WDT.STATUS bit masks and bit positions */ -#define WDT_SYNCBUSY_bm 0x01 /* Syncronization busy bit mask. */ -#define WDT_SYNCBUSY_bp 0 /* Syncronization busy bit position. */ - -/* MCU - MCU Control */ -/* MCU.ANAINIT bit masks and bit positions */ -#define MCU_STARTUPDLYA_gm 0x03 /* Analog startup delay Port A group mask. */ -#define MCU_STARTUPDLYA_gp 0 /* Analog startup delay Port A group position. */ -#define MCU_STARTUPDLYA0_bm (1<<0) /* Analog startup delay Port A bit 0 mask. */ -#define MCU_STARTUPDLYA0_bp 0 /* Analog startup delay Port A bit 0 position. */ -#define MCU_STARTUPDLYA1_bm (1<<1) /* Analog startup delay Port A bit 1 mask. */ -#define MCU_STARTUPDLYA1_bp 1 /* Analog startup delay Port A bit 1 position. */ - -/* MCU.EVSYSLOCK bit masks and bit positions */ -#define MCU_EVSYS0LOCK_bm 0x01 /* Event Channel 0-3 Lock bit mask. */ -#define MCU_EVSYS0LOCK_bp 0 /* Event Channel 0-3 Lock bit position. */ - -/* MCU.AWEXLOCK bit masks and bit positions */ -#define MCU_AWEXCLOCK_bm 0x01 /* AWeX on T/C C0 Lock bit mask. */ -#define MCU_AWEXCLOCK_bp 0 /* AWeX on T/C C0 Lock bit position. */ - -/* PMIC - Programmable Multi-level Interrupt Controller */ -/* PMIC.STATUS bit masks and bit positions */ -#define PMIC_NMIEX_bm 0x80 /* Non-maskable Interrupt Executing bit mask. */ -#define PMIC_NMIEX_bp 7 /* Non-maskable Interrupt Executing bit position. */ - -#define PMIC_HILVLEX_bm 0x04 /* High Level Interrupt Executing bit mask. */ -#define PMIC_HILVLEX_bp 2 /* High Level Interrupt Executing bit position. */ - -#define PMIC_MEDLVLEX_bm 0x02 /* Medium Level Interrupt Executing bit mask. */ -#define PMIC_MEDLVLEX_bp 1 /* Medium Level Interrupt Executing bit position. */ - -#define PMIC_LOLVLEX_bm 0x01 /* Low Level Interrupt Executing bit mask. */ -#define PMIC_LOLVLEX_bp 0 /* Low Level Interrupt Executing bit position. */ - -/* PMIC.INTPRI bit masks and bit positions */ -#define PMIC_INTPRI_gm 0xFF /* Interrupt Priority group mask. */ -#define PMIC_INTPRI_gp 0 /* Interrupt Priority group position. */ -#define PMIC_INTPRI0_bm (1<<0) /* Interrupt Priority bit 0 mask. */ -#define PMIC_INTPRI0_bp 0 /* Interrupt Priority bit 0 position. */ -#define PMIC_INTPRI1_bm (1<<1) /* Interrupt Priority bit 1 mask. */ -#define PMIC_INTPRI1_bp 1 /* Interrupt Priority bit 1 position. */ -#define PMIC_INTPRI2_bm (1<<2) /* Interrupt Priority bit 2 mask. */ -#define PMIC_INTPRI2_bp 2 /* Interrupt Priority bit 2 position. */ -#define PMIC_INTPRI3_bm (1<<3) /* Interrupt Priority bit 3 mask. */ -#define PMIC_INTPRI3_bp 3 /* Interrupt Priority bit 3 position. */ -#define PMIC_INTPRI4_bm (1<<4) /* Interrupt Priority bit 4 mask. */ -#define PMIC_INTPRI4_bp 4 /* Interrupt Priority bit 4 position. */ -#define PMIC_INTPRI5_bm (1<<5) /* Interrupt Priority bit 5 mask. */ -#define PMIC_INTPRI5_bp 5 /* Interrupt Priority bit 5 position. */ -#define PMIC_INTPRI6_bm (1<<6) /* Interrupt Priority bit 6 mask. */ -#define PMIC_INTPRI6_bp 6 /* Interrupt Priority bit 6 position. */ -#define PMIC_INTPRI7_bm (1<<7) /* Interrupt Priority bit 7 mask. */ -#define PMIC_INTPRI7_bp 7 /* Interrupt Priority bit 7 position. */ - -/* PMIC.CTRL bit masks and bit positions */ -#define PMIC_RREN_bm 0x80 /* Round-Robin Priority Enable bit mask. */ -#define PMIC_RREN_bp 7 /* Round-Robin Priority Enable bit position. */ - -#define PMIC_IVSEL_bm 0x40 /* Interrupt Vector Select bit mask. */ -#define PMIC_IVSEL_bp 6 /* Interrupt Vector Select bit position. */ - -#define PMIC_HILVLEN_bm 0x04 /* High Level Enable bit mask. */ -#define PMIC_HILVLEN_bp 2 /* High Level Enable bit position. */ - -#define PMIC_MEDLVLEN_bm 0x02 /* Medium Level Enable bit mask. */ -#define PMIC_MEDLVLEN_bp 1 /* Medium Level Enable bit position. */ - -#define PMIC_LOLVLEN_bm 0x01 /* Low Level Enable bit mask. */ -#define PMIC_LOLVLEN_bp 0 /* Low Level Enable bit position. */ - -/* PORTCFG - Port Configuration */ -/* PORTCFG.VPCTRLA bit masks and bit positions */ -#define PORTCFG_VP1MAP_gm 0xF0 /* Virtual Port 1 Mapping group mask. */ -#define PORTCFG_VP1MAP_gp 4 /* Virtual Port 1 Mapping group position. */ -#define PORTCFG_VP1MAP0_bm (1<<4) /* Virtual Port 1 Mapping bit 0 mask. */ -#define PORTCFG_VP1MAP0_bp 4 /* Virtual Port 1 Mapping bit 0 position. */ -#define PORTCFG_VP1MAP1_bm (1<<5) /* Virtual Port 1 Mapping bit 1 mask. */ -#define PORTCFG_VP1MAP1_bp 5 /* Virtual Port 1 Mapping bit 1 position. */ -#define PORTCFG_VP1MAP2_bm (1<<6) /* Virtual Port 1 Mapping bit 2 mask. */ -#define PORTCFG_VP1MAP2_bp 6 /* Virtual Port 1 Mapping bit 2 position. */ -#define PORTCFG_VP1MAP3_bm (1<<7) /* Virtual Port 1 Mapping bit 3 mask. */ -#define PORTCFG_VP1MAP3_bp 7 /* Virtual Port 1 Mapping bit 3 position. */ - -#define PORTCFG_VP0MAP_gm 0x0F /* Virtual Port 0 Mapping group mask. */ -#define PORTCFG_VP0MAP_gp 0 /* Virtual Port 0 Mapping group position. */ -#define PORTCFG_VP0MAP0_bm (1<<0) /* Virtual Port 0 Mapping bit 0 mask. */ -#define PORTCFG_VP0MAP0_bp 0 /* Virtual Port 0 Mapping bit 0 position. */ -#define PORTCFG_VP0MAP1_bm (1<<1) /* Virtual Port 0 Mapping bit 1 mask. */ -#define PORTCFG_VP0MAP1_bp 1 /* Virtual Port 0 Mapping bit 1 position. */ -#define PORTCFG_VP0MAP2_bm (1<<2) /* Virtual Port 0 Mapping bit 2 mask. */ -#define PORTCFG_VP0MAP2_bp 2 /* Virtual Port 0 Mapping bit 2 position. */ -#define PORTCFG_VP0MAP3_bm (1<<3) /* Virtual Port 0 Mapping bit 3 mask. */ -#define PORTCFG_VP0MAP3_bp 3 /* Virtual Port 0 Mapping bit 3 position. */ - -/* PORTCFG.VPCTRLB bit masks and bit positions */ -#define PORTCFG_VP3MAP_gm 0xF0 /* Virtual Port 3 Mapping group mask. */ -#define PORTCFG_VP3MAP_gp 4 /* Virtual Port 3 Mapping group position. */ -#define PORTCFG_VP3MAP0_bm (1<<4) /* Virtual Port 3 Mapping bit 0 mask. */ -#define PORTCFG_VP3MAP0_bp 4 /* Virtual Port 3 Mapping bit 0 position. */ -#define PORTCFG_VP3MAP1_bm (1<<5) /* Virtual Port 3 Mapping bit 1 mask. */ -#define PORTCFG_VP3MAP1_bp 5 /* Virtual Port 3 Mapping bit 1 position. */ -#define PORTCFG_VP3MAP2_bm (1<<6) /* Virtual Port 3 Mapping bit 2 mask. */ -#define PORTCFG_VP3MAP2_bp 6 /* Virtual Port 3 Mapping bit 2 position. */ -#define PORTCFG_VP3MAP3_bm (1<<7) /* Virtual Port 3 Mapping bit 3 mask. */ -#define PORTCFG_VP3MAP3_bp 7 /* Virtual Port 3 Mapping bit 3 position. */ - -#define PORTCFG_VP2MAP_gm 0x0F /* Virtual Port 2 Mapping group mask. */ -#define PORTCFG_VP2MAP_gp 0 /* Virtual Port 2 Mapping group position. */ -#define PORTCFG_VP2MAP0_bm (1<<0) /* Virtual Port 2 Mapping bit 0 mask. */ -#define PORTCFG_VP2MAP0_bp 0 /* Virtual Port 2 Mapping bit 0 position. */ -#define PORTCFG_VP2MAP1_bm (1<<1) /* Virtual Port 2 Mapping bit 1 mask. */ -#define PORTCFG_VP2MAP1_bp 1 /* Virtual Port 2 Mapping bit 1 position. */ -#define PORTCFG_VP2MAP2_bm (1<<2) /* Virtual Port 2 Mapping bit 2 mask. */ -#define PORTCFG_VP2MAP2_bp 2 /* Virtual Port 2 Mapping bit 2 position. */ -#define PORTCFG_VP2MAP3_bm (1<<3) /* Virtual Port 2 Mapping bit 3 mask. */ -#define PORTCFG_VP2MAP3_bp 3 /* Virtual Port 2 Mapping bit 3 position. */ - -/* PORTCFG.CLKEVOUT bit masks and bit positions */ -#define PORTCFG_CLKOUT_gm 0x03 /* Peripheral Clock Output Port group mask. */ -#define PORTCFG_CLKOUT_gp 0 /* Peripheral Clock Output Port group position. */ -#define PORTCFG_CLKOUT0_bm (1<<0) /* Peripheral Clock Output Port bit 0 mask. */ -#define PORTCFG_CLKOUT0_bp 0 /* Peripheral Clock Output Port bit 0 position. */ -#define PORTCFG_CLKOUT1_bm (1<<1) /* Peripheral Clock Output Port bit 1 mask. */ -#define PORTCFG_CLKOUT1_bp 1 /* Peripheral Clock Output Port bit 1 position. */ - -#define PORTCFG_CLKOUTSEL_gm 0x0C /* Peripheral Clock Output Select group mask. */ -#define PORTCFG_CLKOUTSEL_gp 2 /* Peripheral Clock Output Select group position. */ -#define PORTCFG_CLKOUTSEL0_bm (1<<2) /* Peripheral Clock Output Select bit 0 mask. */ -#define PORTCFG_CLKOUTSEL0_bp 2 /* Peripheral Clock Output Select bit 0 position. */ -#define PORTCFG_CLKOUTSEL1_bm (1<<3) /* Peripheral Clock Output Select bit 1 mask. */ -#define PORTCFG_CLKOUTSEL1_bp 3 /* Peripheral Clock Output Select bit 1 position. */ - -#define PORTCFG_EVOUT_gm 0x30 /* Event Output Port group mask. */ -#define PORTCFG_EVOUT_gp 4 /* Event Output Port group position. */ -#define PORTCFG_EVOUT0_bm (1<<4) /* Event Output Port bit 0 mask. */ -#define PORTCFG_EVOUT0_bp 4 /* Event Output Port bit 0 position. */ -#define PORTCFG_EVOUT1_bm (1<<5) /* Event Output Port bit 1 mask. */ -#define PORTCFG_EVOUT1_bp 5 /* Event Output Port bit 1 position. */ - -#define PORTCFG_RTCOUT_bm 0x40 /* RTC Clock Output bit mask. */ -#define PORTCFG_RTCOUT_bp 6 /* RTC Clock Output bit position. */ - -#define PORTCFG_CLKEVPIN_bm 0x80 /* Peripheral Clock and Event Output pin Select bit mask. */ -#define PORTCFG_CLKEVPIN_bp 7 /* Peripheral Clock and Event Output pin Select bit position. */ - -/* PORTCFG.EVOUTSEL bit masks and bit positions */ -#define PORTCFG_EVOUTSEL_gm 0x07 /* Event Output Select group mask. */ -#define PORTCFG_EVOUTSEL_gp 0 /* Event Output Select group position. */ -#define PORTCFG_EVOUTSEL0_bm (1<<0) /* Event Output Select bit 0 mask. */ -#define PORTCFG_EVOUTSEL0_bp 0 /* Event Output Select bit 0 position. */ -#define PORTCFG_EVOUTSEL1_bm (1<<1) /* Event Output Select bit 1 mask. */ -#define PORTCFG_EVOUTSEL1_bp 1 /* Event Output Select bit 1 position. */ -#define PORTCFG_EVOUTSEL2_bm (1<<2) /* Event Output Select bit 2 mask. */ -#define PORTCFG_EVOUTSEL2_bp 2 /* Event Output Select bit 2 position. */ - -/* CRC - Cyclic Redundancy Checker */ -/* CRC.CTRL bit masks and bit positions */ -#define CRC_RESET_gm 0xC0 /* Reset group mask. */ -#define CRC_RESET_gp 6 /* Reset group position. */ -#define CRC_RESET0_bm (1<<6) /* Reset bit 0 mask. */ -#define CRC_RESET0_bp 6 /* Reset bit 0 position. */ -#define CRC_RESET1_bm (1<<7) /* Reset bit 1 mask. */ -#define CRC_RESET1_bp 7 /* Reset bit 1 position. */ - -#define CRC_CRC32_bm 0x20 /* CRC Mode bit mask. */ -#define CRC_CRC32_bp 5 /* CRC Mode bit position. */ - -#define CRC_SOURCE_gm 0x0F /* Input Source group mask. */ -#define CRC_SOURCE_gp 0 /* Input Source group position. */ -#define CRC_SOURCE0_bm (1<<0) /* Input Source bit 0 mask. */ -#define CRC_SOURCE0_bp 0 /* Input Source bit 0 position. */ -#define CRC_SOURCE1_bm (1<<1) /* Input Source bit 1 mask. */ -#define CRC_SOURCE1_bp 1 /* Input Source bit 1 position. */ -#define CRC_SOURCE2_bm (1<<2) /* Input Source bit 2 mask. */ -#define CRC_SOURCE2_bp 2 /* Input Source bit 2 position. */ -#define CRC_SOURCE3_bm (1<<3) /* Input Source bit 3 mask. */ -#define CRC_SOURCE3_bp 3 /* Input Source bit 3 position. */ - -/* CRC.STATUS bit masks and bit positions */ -#define CRC_ZERO_bm 0x02 /* Zero detection bit mask. */ -#define CRC_ZERO_bp 1 /* Zero detection bit position. */ - -#define CRC_BUSY_bm 0x01 /* Busy bit mask. */ -#define CRC_BUSY_bp 0 /* Busy bit position. */ - -/* EVSYS - Event System */ -/* EVSYS.CH0MUX bit masks and bit positions */ -#define EVSYS_CHMUX_gm 0xFF /* Event Channel 0 Multiplexer group mask. */ -#define EVSYS_CHMUX_gp 0 /* Event Channel 0 Multiplexer group position. */ -#define EVSYS_CHMUX0_bm (1<<0) /* Event Channel 0 Multiplexer bit 0 mask. */ -#define EVSYS_CHMUX0_bp 0 /* Event Channel 0 Multiplexer bit 0 position. */ -#define EVSYS_CHMUX1_bm (1<<1) /* Event Channel 0 Multiplexer bit 1 mask. */ -#define EVSYS_CHMUX1_bp 1 /* Event Channel 0 Multiplexer bit 1 position. */ -#define EVSYS_CHMUX2_bm (1<<2) /* Event Channel 0 Multiplexer bit 2 mask. */ -#define EVSYS_CHMUX2_bp 2 /* Event Channel 0 Multiplexer bit 2 position. */ -#define EVSYS_CHMUX3_bm (1<<3) /* Event Channel 0 Multiplexer bit 3 mask. */ -#define EVSYS_CHMUX3_bp 3 /* Event Channel 0 Multiplexer bit 3 position. */ -#define EVSYS_CHMUX4_bm (1<<4) /* Event Channel 0 Multiplexer bit 4 mask. */ -#define EVSYS_CHMUX4_bp 4 /* Event Channel 0 Multiplexer bit 4 position. */ -#define EVSYS_CHMUX5_bm (1<<5) /* Event Channel 0 Multiplexer bit 5 mask. */ -#define EVSYS_CHMUX5_bp 5 /* Event Channel 0 Multiplexer bit 5 position. */ -#define EVSYS_CHMUX6_bm (1<<6) /* Event Channel 0 Multiplexer bit 6 mask. */ -#define EVSYS_CHMUX6_bp 6 /* Event Channel 0 Multiplexer bit 6 position. */ -#define EVSYS_CHMUX7_bm (1<<7) /* Event Channel 0 Multiplexer bit 7 mask. */ -#define EVSYS_CHMUX7_bp 7 /* Event Channel 0 Multiplexer bit 7 position. */ - -/* EVSYS.CH1MUX bit masks and bit positions */ -/* EVSYS_CHMUX Predefined. */ -/* EVSYS_CHMUX Predefined. */ - -/* EVSYS.CH2MUX bit masks and bit positions */ -/* EVSYS_CHMUX Predefined. */ -/* EVSYS_CHMUX Predefined. */ - -/* EVSYS.CH3MUX bit masks and bit positions */ -/* EVSYS_CHMUX Predefined. */ -/* EVSYS_CHMUX Predefined. */ - -/* EVSYS.CH0CTRL bit masks and bit positions */ -#define EVSYS_QDIRM_gm 0x60 /* Quadrature Decoder Index Recognition Mode group mask. */ -#define EVSYS_QDIRM_gp 5 /* Quadrature Decoder Index Recognition Mode group position. */ -#define EVSYS_QDIRM0_bm (1<<5) /* Quadrature Decoder Index Recognition Mode bit 0 mask. */ -#define EVSYS_QDIRM0_bp 5 /* Quadrature Decoder Index Recognition Mode bit 0 position. */ -#define EVSYS_QDIRM1_bm (1<<6) /* Quadrature Decoder Index Recognition Mode bit 1 mask. */ -#define EVSYS_QDIRM1_bp 6 /* Quadrature Decoder Index Recognition Mode bit 1 position. */ - -#define EVSYS_QDIEN_bm 0x10 /* Quadrature Decoder Index Enable bit mask. */ -#define EVSYS_QDIEN_bp 4 /* Quadrature Decoder Index Enable bit position. */ - -#define EVSYS_QDEN_bm 0x08 /* Quadrature Decoder Enable bit mask. */ -#define EVSYS_QDEN_bp 3 /* Quadrature Decoder Enable bit position. */ - -#define EVSYS_DIGFILT_gm 0x07 /* Digital Filter group mask. */ -#define EVSYS_DIGFILT_gp 0 /* Digital Filter group position. */ -#define EVSYS_DIGFILT0_bm (1<<0) /* Digital Filter bit 0 mask. */ -#define EVSYS_DIGFILT0_bp 0 /* Digital Filter bit 0 position. */ -#define EVSYS_DIGFILT1_bm (1<<1) /* Digital Filter bit 1 mask. */ -#define EVSYS_DIGFILT1_bp 1 /* Digital Filter bit 1 position. */ -#define EVSYS_DIGFILT2_bm (1<<2) /* Digital Filter bit 2 mask. */ -#define EVSYS_DIGFILT2_bp 2 /* Digital Filter bit 2 position. */ - -/* EVSYS.CH1CTRL bit masks and bit positions */ -/* EVSYS_DIGFILT Predefined. */ -/* EVSYS_DIGFILT Predefined. */ - -/* EVSYS.CH2CTRL bit masks and bit positions */ -/* EVSYS_DIGFILT Predefined. */ -/* EVSYS_DIGFILT Predefined. */ - -/* EVSYS.CH3CTRL bit masks and bit positions */ -/* EVSYS_DIGFILT Predefined. */ -/* EVSYS_DIGFILT Predefined. */ - -/* NVM - Non Volatile Memory Controller */ -/* NVM.CMD bit masks and bit positions */ -#define NVM_CMD_gm 0x7F /* Command group mask. */ -#define NVM_CMD_gp 0 /* Command group position. */ -#define NVM_CMD0_bm (1<<0) /* Command bit 0 mask. */ -#define NVM_CMD0_bp 0 /* Command bit 0 position. */ -#define NVM_CMD1_bm (1<<1) /* Command bit 1 mask. */ -#define NVM_CMD1_bp 1 /* Command bit 1 position. */ -#define NVM_CMD2_bm (1<<2) /* Command bit 2 mask. */ -#define NVM_CMD2_bp 2 /* Command bit 2 position. */ -#define NVM_CMD3_bm (1<<3) /* Command bit 3 mask. */ -#define NVM_CMD3_bp 3 /* Command bit 3 position. */ -#define NVM_CMD4_bm (1<<4) /* Command bit 4 mask. */ -#define NVM_CMD4_bp 4 /* Command bit 4 position. */ -#define NVM_CMD5_bm (1<<5) /* Command bit 5 mask. */ -#define NVM_CMD5_bp 5 /* Command bit 5 position. */ -#define NVM_CMD6_bm (1<<6) /* Command bit 6 mask. */ -#define NVM_CMD6_bp 6 /* Command bit 6 position. */ - -/* NVM.CTRLA bit masks and bit positions */ -#define NVM_CMDEX_bm 0x01 /* Command Execute bit mask. */ -#define NVM_CMDEX_bp 0 /* Command Execute bit position. */ - -/* NVM.CTRLB bit masks and bit positions */ -#define NVM_EEMAPEN_bm 0x08 /* EEPROM Mapping Enable bit mask. */ -#define NVM_EEMAPEN_bp 3 /* EEPROM Mapping Enable bit position. */ - -#define NVM_FPRM_bm 0x04 /* Flash Power Reduction Enable bit mask. */ -#define NVM_FPRM_bp 2 /* Flash Power Reduction Enable bit position. */ - -#define NVM_EPRM_bm 0x02 /* EEPROM Power Reduction Enable bit mask. */ -#define NVM_EPRM_bp 1 /* EEPROM Power Reduction Enable bit position. */ - -#define NVM_SPMLOCK_bm 0x01 /* SPM Lock bit mask. */ -#define NVM_SPMLOCK_bp 0 /* SPM Lock bit position. */ - -/* NVM.INTCTRL bit masks and bit positions */ -#define NVM_SPMLVL_gm 0x0C /* SPM Interrupt Level group mask. */ -#define NVM_SPMLVL_gp 2 /* SPM Interrupt Level group position. */ -#define NVM_SPMLVL0_bm (1<<2) /* SPM Interrupt Level bit 0 mask. */ -#define NVM_SPMLVL0_bp 2 /* SPM Interrupt Level bit 0 position. */ -#define NVM_SPMLVL1_bm (1<<3) /* SPM Interrupt Level bit 1 mask. */ -#define NVM_SPMLVL1_bp 3 /* SPM Interrupt Level bit 1 position. */ - -#define NVM_EELVL_gm 0x03 /* EEPROM Interrupt Level group mask. */ -#define NVM_EELVL_gp 0 /* EEPROM Interrupt Level group position. */ -#define NVM_EELVL0_bm (1<<0) /* EEPROM Interrupt Level bit 0 mask. */ -#define NVM_EELVL0_bp 0 /* EEPROM Interrupt Level bit 0 position. */ -#define NVM_EELVL1_bm (1<<1) /* EEPROM Interrupt Level bit 1 mask. */ -#define NVM_EELVL1_bp 1 /* EEPROM Interrupt Level bit 1 position. */ - -/* NVM.STATUS bit masks and bit positions */ -#define NVM_NVMBUSY_bm 0x80 /* Non-volatile Memory Busy bit mask. */ -#define NVM_NVMBUSY_bp 7 /* Non-volatile Memory Busy bit position. */ - -#define NVM_FBUSY_bm 0x40 /* Flash Memory Busy bit mask. */ -#define NVM_FBUSY_bp 6 /* Flash Memory Busy bit position. */ - -#define NVM_EELOAD_bm 0x02 /* EEPROM Page Buffer Active Loading bit mask. */ -#define NVM_EELOAD_bp 1 /* EEPROM Page Buffer Active Loading bit position. */ - -#define NVM_FLOAD_bm 0x01 /* Flash Page Buffer Active Loading bit mask. */ -#define NVM_FLOAD_bp 0 /* Flash Page Buffer Active Loading bit position. */ - -/* NVM.LOCKBITS bit masks and bit positions */ -#define NVM_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ -#define NVM_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ -#define NVM_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ -#define NVM_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ -#define NVM_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ -#define NVM_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ - -#define NVM_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ -#define NVM_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ -#define NVM_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ -#define NVM_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ -#define NVM_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ -#define NVM_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ - -#define NVM_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ -#define NVM_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ -#define NVM_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ -#define NVM_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ -#define NVM_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ -#define NVM_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ - -#define NVM_LB_gm 0x03 /* Lock Bits group mask. */ -#define NVM_LB_gp 0 /* Lock Bits group position. */ -#define NVM_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ -#define NVM_LB0_bp 0 /* Lock Bits bit 0 position. */ -#define NVM_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ -#define NVM_LB1_bp 1 /* Lock Bits bit 1 position. */ - -/* ADC - Analog/Digital Converter */ -/* ADC_CH.CTRL bit masks and bit positions */ -#define ADC_CH_START_bm 0x80 /* Channel Start Conversion bit mask. */ -#define ADC_CH_START_bp 7 /* Channel Start Conversion bit position. */ - -#define ADC_CH_GAIN_gm 0x1C /* Gain Factor group mask. */ -#define ADC_CH_GAIN_gp 2 /* Gain Factor group position. */ -#define ADC_CH_GAIN0_bm (1<<2) /* Gain Factor bit 0 mask. */ -#define ADC_CH_GAIN0_bp 2 /* Gain Factor bit 0 position. */ -#define ADC_CH_GAIN1_bm (1<<3) /* Gain Factor bit 1 mask. */ -#define ADC_CH_GAIN1_bp 3 /* Gain Factor bit 1 position. */ -#define ADC_CH_GAIN2_bm (1<<4) /* Gain Factor bit 2 mask. */ -#define ADC_CH_GAIN2_bp 4 /* Gain Factor bit 2 position. */ - -#define ADC_CH_INPUTMODE_gm 0x03 /* Input Mode Select group mask. */ -#define ADC_CH_INPUTMODE_gp 0 /* Input Mode Select group position. */ -#define ADC_CH_INPUTMODE0_bm (1<<0) /* Input Mode Select bit 0 mask. */ -#define ADC_CH_INPUTMODE0_bp 0 /* Input Mode Select bit 0 position. */ -#define ADC_CH_INPUTMODE1_bm (1<<1) /* Input Mode Select bit 1 mask. */ -#define ADC_CH_INPUTMODE1_bp 1 /* Input Mode Select bit 1 position. */ - -/* ADC_CH.MUXCTRL bit masks and bit positions */ -#define ADC_CH_MUXPOS_gm 0x78 /* MUX selection on Positive ADC input group mask. */ -#define ADC_CH_MUXPOS_gp 3 /* MUX selection on Positive ADC input group position. */ -#define ADC_CH_MUXPOS0_bm (1<<3) /* MUX selection on Positive ADC input bit 0 mask. */ -#define ADC_CH_MUXPOS0_bp 3 /* MUX selection on Positive ADC input bit 0 position. */ -#define ADC_CH_MUXPOS1_bm (1<<4) /* MUX selection on Positive ADC input bit 1 mask. */ -#define ADC_CH_MUXPOS1_bp 4 /* MUX selection on Positive ADC input bit 1 position. */ -#define ADC_CH_MUXPOS2_bm (1<<5) /* MUX selection on Positive ADC input bit 2 mask. */ -#define ADC_CH_MUXPOS2_bp 5 /* MUX selection on Positive ADC input bit 2 position. */ -#define ADC_CH_MUXPOS3_bm (1<<6) /* MUX selection on Positive ADC input bit 3 mask. */ -#define ADC_CH_MUXPOS3_bp 6 /* MUX selection on Positive ADC input bit 3 position. */ - -#define ADC_CH_MUXINT_gm 0x78 /* MUX selection on Internal ADC input group mask. */ -#define ADC_CH_MUXINT_gp 3 /* MUX selection on Internal ADC input group position. */ -#define ADC_CH_MUXINT0_bm (1<<3) /* MUX selection on Internal ADC input bit 0 mask. */ -#define ADC_CH_MUXINT0_bp 3 /* MUX selection on Internal ADC input bit 0 position. */ -#define ADC_CH_MUXINT1_bm (1<<4) /* MUX selection on Internal ADC input bit 1 mask. */ -#define ADC_CH_MUXINT1_bp 4 /* MUX selection on Internal ADC input bit 1 position. */ -#define ADC_CH_MUXINT2_bm (1<<5) /* MUX selection on Internal ADC input bit 2 mask. */ -#define ADC_CH_MUXINT2_bp 5 /* MUX selection on Internal ADC input bit 2 position. */ -#define ADC_CH_MUXINT3_bm (1<<6) /* MUX selection on Internal ADC input bit 3 mask. */ -#define ADC_CH_MUXINT3_bp 6 /* MUX selection on Internal ADC input bit 3 position. */ - -#define ADC_CH_MUXNEG_gm 0x03 /* MUX selection on Negative ADC input group mask. */ -#define ADC_CH_MUXNEG_gp 0 /* MUX selection on Negative ADC input group position. */ -#define ADC_CH_MUXNEG0_bm (1<<0) /* MUX selection on Negative ADC input bit 0 mask. */ -#define ADC_CH_MUXNEG0_bp 0 /* MUX selection on Negative ADC input bit 0 position. */ -#define ADC_CH_MUXNEG1_bm (1<<1) /* MUX selection on Negative ADC input bit 1 mask. */ -#define ADC_CH_MUXNEG1_bp 1 /* MUX selection on Negative ADC input bit 1 position. */ - -/* ADC_CH.INTCTRL bit masks and bit positions */ -#define ADC_CH_INTMODE_gm 0x0C /* Interrupt Mode group mask. */ -#define ADC_CH_INTMODE_gp 2 /* Interrupt Mode group position. */ -#define ADC_CH_INTMODE0_bm (1<<2) /* Interrupt Mode bit 0 mask. */ -#define ADC_CH_INTMODE0_bp 2 /* Interrupt Mode bit 0 position. */ -#define ADC_CH_INTMODE1_bm (1<<3) /* Interrupt Mode bit 1 mask. */ -#define ADC_CH_INTMODE1_bp 3 /* Interrupt Mode bit 1 position. */ - -#define ADC_CH_INTLVL_gm 0x03 /* Interrupt Level group mask. */ -#define ADC_CH_INTLVL_gp 0 /* Interrupt Level group position. */ -#define ADC_CH_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */ -#define ADC_CH_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */ -#define ADC_CH_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ -#define ADC_CH_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */ - -/* ADC_CH.INTFLAGS bit masks and bit positions */ -#define ADC_CH_CHIF_bm 0x01 /* Channel Interrupt Flag bit mask. */ -#define ADC_CH_CHIF_bp 0 /* Channel Interrupt Flag bit position. */ - -/* ADC_CH.SCAN bit masks and bit positions */ -#define ADC_CH_OFFSET_gm 0xF0 /* Positive MUX setting offset group mask. */ -#define ADC_CH_OFFSET_gp 4 /* Positive MUX setting offset group position. */ -#define ADC_CH_OFFSET0_bm (1<<4) /* Positive MUX setting offset bit 0 mask. */ -#define ADC_CH_OFFSET0_bp 4 /* Positive MUX setting offset bit 0 position. */ -#define ADC_CH_OFFSET1_bm (1<<5) /* Positive MUX setting offset bit 1 mask. */ -#define ADC_CH_OFFSET1_bp 5 /* Positive MUX setting offset bit 1 position. */ -#define ADC_CH_OFFSET2_bm (1<<6) /* Positive MUX setting offset bit 2 mask. */ -#define ADC_CH_OFFSET2_bp 6 /* Positive MUX setting offset bit 2 position. */ -#define ADC_CH_OFFSET3_bm (1<<7) /* Positive MUX setting offset bit 3 mask. */ -#define ADC_CH_OFFSET3_bp 7 /* Positive MUX setting offset bit 3 position. */ - -#define ADC_CH_SCANNUM_gm 0x0F /* Number of Channels included in scan group mask. */ -#define ADC_CH_SCANNUM_gp 0 /* Number of Channels included in scan group position. */ -#define ADC_CH_SCANNUM0_bm (1<<0) /* Number of Channels included in scan bit 0 mask. */ -#define ADC_CH_SCANNUM0_bp 0 /* Number of Channels included in scan bit 0 position. */ -#define ADC_CH_SCANNUM1_bm (1<<1) /* Number of Channels included in scan bit 1 mask. */ -#define ADC_CH_SCANNUM1_bp 1 /* Number of Channels included in scan bit 1 position. */ -#define ADC_CH_SCANNUM2_bm (1<<2) /* Number of Channels included in scan bit 2 mask. */ -#define ADC_CH_SCANNUM2_bp 2 /* Number of Channels included in scan bit 2 position. */ -#define ADC_CH_SCANNUM3_bm (1<<3) /* Number of Channels included in scan bit 3 mask. */ -#define ADC_CH_SCANNUM3_bp 3 /* Number of Channels included in scan bit 3 position. */ - -/* ADC.CTRLA bit masks and bit positions */ -#define ADC_CH0START_bm 0x04 /* Channel 0 Start Conversion bit mask. */ -#define ADC_CH0START_bp 2 /* Channel 0 Start Conversion bit position. */ - -#define ADC_FLUSH_bm 0x02 /* ADC Flush bit mask. */ -#define ADC_FLUSH_bp 1 /* ADC Flush bit position. */ - -#define ADC_ENABLE_bm 0x01 /* Enable ADC bit mask. */ -#define ADC_ENABLE_bp 0 /* Enable ADC bit position. */ - -/* ADC.CTRLB bit masks and bit positions */ -#define ADC_CURRLIMIT_gm 0x60 /* Current Limitation group mask. */ -#define ADC_CURRLIMIT_gp 5 /* Current Limitation group position. */ -#define ADC_CURRLIMIT0_bm (1<<5) /* Current Limitation bit 0 mask. */ -#define ADC_CURRLIMIT0_bp 5 /* Current Limitation bit 0 position. */ -#define ADC_CURRLIMIT1_bm (1<<6) /* Current Limitation bit 1 mask. */ -#define ADC_CURRLIMIT1_bp 6 /* Current Limitation bit 1 position. */ - -#define ADC_CONMODE_bm 0x10 /* Conversion Mode bit mask. */ -#define ADC_CONMODE_bp 4 /* Conversion Mode bit position. */ - -#define ADC_FREERUN_bm 0x08 /* Free Running Mode Enable bit mask. */ -#define ADC_FREERUN_bp 3 /* Free Running Mode Enable bit position. */ - -#define ADC_RESOLUTION_gm 0x06 /* Result Resolution group mask. */ -#define ADC_RESOLUTION_gp 1 /* Result Resolution group position. */ -#define ADC_RESOLUTION0_bm (1<<1) /* Result Resolution bit 0 mask. */ -#define ADC_RESOLUTION0_bp 1 /* Result Resolution bit 0 position. */ -#define ADC_RESOLUTION1_bm (1<<2) /* Result Resolution bit 1 mask. */ -#define ADC_RESOLUTION1_bp 2 /* Result Resolution bit 1 position. */ - -/* ADC.REFCTRL bit masks and bit positions */ -#define ADC_REFSEL_gm 0x70 /* Reference Selection group mask. */ -#define ADC_REFSEL_gp 4 /* Reference Selection group position. */ -#define ADC_REFSEL0_bm (1<<4) /* Reference Selection bit 0 mask. */ -#define ADC_REFSEL0_bp 4 /* Reference Selection bit 0 position. */ -#define ADC_REFSEL1_bm (1<<5) /* Reference Selection bit 1 mask. */ -#define ADC_REFSEL1_bp 5 /* Reference Selection bit 1 position. */ -#define ADC_REFSEL2_bm (1<<6) /* Reference Selection bit 2 mask. */ -#define ADC_REFSEL2_bp 6 /* Reference Selection bit 2 position. */ - -#define ADC_BANDGAP_bm 0x02 /* Bandgap enable bit mask. */ -#define ADC_BANDGAP_bp 1 /* Bandgap enable bit position. */ - -#define ADC_TEMPREF_bm 0x01 /* Temperature Reference Enable bit mask. */ -#define ADC_TEMPREF_bp 0 /* Temperature Reference Enable bit position. */ - -/* ADC.EVCTRL bit masks and bit positions */ -#define ADC_EVSEL_gm 0x18 /* Event Input Select group mask. */ -#define ADC_EVSEL_gp 3 /* Event Input Select group position. */ -#define ADC_EVSEL0_bm (1<<3) /* Event Input Select bit 0 mask. */ -#define ADC_EVSEL0_bp 3 /* Event Input Select bit 0 position. */ -#define ADC_EVSEL1_bm (1<<4) /* Event Input Select bit 1 mask. */ -#define ADC_EVSEL1_bp 4 /* Event Input Select bit 1 position. */ - -#define ADC_EVACT_gm 0x07 /* Event Action Select group mask. */ -#define ADC_EVACT_gp 0 /* Event Action Select group position. */ -#define ADC_EVACT0_bm (1<<0) /* Event Action Select bit 0 mask. */ -#define ADC_EVACT0_bp 0 /* Event Action Select bit 0 position. */ -#define ADC_EVACT1_bm (1<<1) /* Event Action Select bit 1 mask. */ -#define ADC_EVACT1_bp 1 /* Event Action Select bit 1 position. */ -#define ADC_EVACT2_bm (1<<2) /* Event Action Select bit 2 mask. */ -#define ADC_EVACT2_bp 2 /* Event Action Select bit 2 position. */ - -/* ADC.PRESCALER bit masks and bit positions */ -#define ADC_PRESCALER_gm 0x07 /* Clock Prescaler Selection group mask. */ -#define ADC_PRESCALER_gp 0 /* Clock Prescaler Selection group position. */ -#define ADC_PRESCALER0_bm (1<<0) /* Clock Prescaler Selection bit 0 mask. */ -#define ADC_PRESCALER0_bp 0 /* Clock Prescaler Selection bit 0 position. */ -#define ADC_PRESCALER1_bm (1<<1) /* Clock Prescaler Selection bit 1 mask. */ -#define ADC_PRESCALER1_bp 1 /* Clock Prescaler Selection bit 1 position. */ -#define ADC_PRESCALER2_bm (1<<2) /* Clock Prescaler Selection bit 2 mask. */ -#define ADC_PRESCALER2_bp 2 /* Clock Prescaler Selection bit 2 position. */ - -/* ADC.INTFLAGS bit masks and bit positions */ -#define ADC_CH0IF_bm 0x01 /* Channel 0 Interrupt Flag bit mask. */ -#define ADC_CH0IF_bp 0 /* Channel 0 Interrupt Flag bit position. */ - -/* AC - Analog Comparator */ -/* AC.AC0CTRL bit masks and bit positions */ -#define AC_INTMODE_gm 0xC0 /* Interrupt Mode group mask. */ -#define AC_INTMODE_gp 6 /* Interrupt Mode group position. */ -#define AC_INTMODE0_bm (1<<6) /* Interrupt Mode bit 0 mask. */ -#define AC_INTMODE0_bp 6 /* Interrupt Mode bit 0 position. */ -#define AC_INTMODE1_bm (1<<7) /* Interrupt Mode bit 1 mask. */ -#define AC_INTMODE1_bp 7 /* Interrupt Mode bit 1 position. */ - -#define AC_INTLVL_gm 0x30 /* Interrupt Level group mask. */ -#define AC_INTLVL_gp 4 /* Interrupt Level group position. */ -#define AC_INTLVL0_bm (1<<4) /* Interrupt Level bit 0 mask. */ -#define AC_INTLVL0_bp 4 /* Interrupt Level bit 0 position. */ -#define AC_INTLVL1_bm (1<<5) /* Interrupt Level bit 1 mask. */ -#define AC_INTLVL1_bp 5 /* Interrupt Level bit 1 position. */ - -#define AC_HYSMODE_gm 0x06 /* Hysteresis Mode group mask. */ -#define AC_HYSMODE_gp 1 /* Hysteresis Mode group position. */ -#define AC_HYSMODE0_bm (1<<1) /* Hysteresis Mode bit 0 mask. */ -#define AC_HYSMODE0_bp 1 /* Hysteresis Mode bit 0 position. */ -#define AC_HYSMODE1_bm (1<<2) /* Hysteresis Mode bit 1 mask. */ -#define AC_HYSMODE1_bp 2 /* Hysteresis Mode bit 1 position. */ - -#define AC_ENABLE_bm 0x01 /* Enable bit mask. */ -#define AC_ENABLE_bp 0 /* Enable bit position. */ - -/* AC.AC1CTRL bit masks and bit positions */ -/* AC_INTMODE Predefined. */ -/* AC_INTMODE Predefined. */ - -/* AC_INTLVL Predefined. */ -/* AC_INTLVL Predefined. */ - -/* AC_HYSMODE Predefined. */ -/* AC_HYSMODE Predefined. */ - -/* AC_ENABLE Predefined. */ -/* AC_ENABLE Predefined. */ - -/* AC.AC0MUXCTRL bit masks and bit positions */ -#define AC_MUXPOS_gm 0x38 /* MUX Positive Input group mask. */ -#define AC_MUXPOS_gp 3 /* MUX Positive Input group position. */ -#define AC_MUXPOS0_bm (1<<3) /* MUX Positive Input bit 0 mask. */ -#define AC_MUXPOS0_bp 3 /* MUX Positive Input bit 0 position. */ -#define AC_MUXPOS1_bm (1<<4) /* MUX Positive Input bit 1 mask. */ -#define AC_MUXPOS1_bp 4 /* MUX Positive Input bit 1 position. */ -#define AC_MUXPOS2_bm (1<<5) /* MUX Positive Input bit 2 mask. */ -#define AC_MUXPOS2_bp 5 /* MUX Positive Input bit 2 position. */ - -#define AC_MUXNEG_gm 0x07 /* MUX Negative Input group mask. */ -#define AC_MUXNEG_gp 0 /* MUX Negative Input group position. */ -#define AC_MUXNEG0_bm (1<<0) /* MUX Negative Input bit 0 mask. */ -#define AC_MUXNEG0_bp 0 /* MUX Negative Input bit 0 position. */ -#define AC_MUXNEG1_bm (1<<1) /* MUX Negative Input bit 1 mask. */ -#define AC_MUXNEG1_bp 1 /* MUX Negative Input bit 1 position. */ -#define AC_MUXNEG2_bm (1<<2) /* MUX Negative Input bit 2 mask. */ -#define AC_MUXNEG2_bp 2 /* MUX Negative Input bit 2 position. */ - -/* AC.AC1MUXCTRL bit masks and bit positions */ -/* AC_MUXPOS Predefined. */ -/* AC_MUXPOS Predefined. */ - -/* AC_MUXNEG Predefined. */ -/* AC_MUXNEG Predefined. */ - -/* AC.CTRLA bit masks and bit positions */ -#define AC_AC1OUT_bm 0x02 /* Analog Comparator 1 Output Enable bit mask. */ -#define AC_AC1OUT_bp 1 /* Analog Comparator 1 Output Enable bit position. */ - -#define AC_AC0OUT_bm 0x01 /* Analog Comparator 0 Output Enable bit mask. */ -#define AC_AC0OUT_bp 0 /* Analog Comparator 0 Output Enable bit position. */ - -/* AC.CTRLB bit masks and bit positions */ -#define AC_SCALEFAC_gm 0x3F /* VCC Voltage Scaler Factor group mask. */ -#define AC_SCALEFAC_gp 0 /* VCC Voltage Scaler Factor group position. */ -#define AC_SCALEFAC0_bm (1<<0) /* VCC Voltage Scaler Factor bit 0 mask. */ -#define AC_SCALEFAC0_bp 0 /* VCC Voltage Scaler Factor bit 0 position. */ -#define AC_SCALEFAC1_bm (1<<1) /* VCC Voltage Scaler Factor bit 1 mask. */ -#define AC_SCALEFAC1_bp 1 /* VCC Voltage Scaler Factor bit 1 position. */ -#define AC_SCALEFAC2_bm (1<<2) /* VCC Voltage Scaler Factor bit 2 mask. */ -#define AC_SCALEFAC2_bp 2 /* VCC Voltage Scaler Factor bit 2 position. */ -#define AC_SCALEFAC3_bm (1<<3) /* VCC Voltage Scaler Factor bit 3 mask. */ -#define AC_SCALEFAC3_bp 3 /* VCC Voltage Scaler Factor bit 3 position. */ -#define AC_SCALEFAC4_bm (1<<4) /* VCC Voltage Scaler Factor bit 4 mask. */ -#define AC_SCALEFAC4_bp 4 /* VCC Voltage Scaler Factor bit 4 position. */ -#define AC_SCALEFAC5_bm (1<<5) /* VCC Voltage Scaler Factor bit 5 mask. */ -#define AC_SCALEFAC5_bp 5 /* VCC Voltage Scaler Factor bit 5 position. */ - -/* AC.WINCTRL bit masks and bit positions */ -#define AC_WEN_bm 0x10 /* Window Mode Enable bit mask. */ -#define AC_WEN_bp 4 /* Window Mode Enable bit position. */ - -#define AC_WINTMODE_gm 0x0C /* Window Interrupt Mode group mask. */ -#define AC_WINTMODE_gp 2 /* Window Interrupt Mode group position. */ -#define AC_WINTMODE0_bm (1<<2) /* Window Interrupt Mode bit 0 mask. */ -#define AC_WINTMODE0_bp 2 /* Window Interrupt Mode bit 0 position. */ -#define AC_WINTMODE1_bm (1<<3) /* Window Interrupt Mode bit 1 mask. */ -#define AC_WINTMODE1_bp 3 /* Window Interrupt Mode bit 1 position. */ - -#define AC_WINTLVL_gm 0x03 /* Window Interrupt Level group mask. */ -#define AC_WINTLVL_gp 0 /* Window Interrupt Level group position. */ -#define AC_WINTLVL0_bm (1<<0) /* Window Interrupt Level bit 0 mask. */ -#define AC_WINTLVL0_bp 0 /* Window Interrupt Level bit 0 position. */ -#define AC_WINTLVL1_bm (1<<1) /* Window Interrupt Level bit 1 mask. */ -#define AC_WINTLVL1_bp 1 /* Window Interrupt Level bit 1 position. */ - -/* AC.STATUS bit masks and bit positions */ -#define AC_WSTATE_gm 0xC0 /* Window Mode State group mask. */ -#define AC_WSTATE_gp 6 /* Window Mode State group position. */ -#define AC_WSTATE0_bm (1<<6) /* Window Mode State bit 0 mask. */ -#define AC_WSTATE0_bp 6 /* Window Mode State bit 0 position. */ -#define AC_WSTATE1_bm (1<<7) /* Window Mode State bit 1 mask. */ -#define AC_WSTATE1_bp 7 /* Window Mode State bit 1 position. */ - -#define AC_AC1STATE_bm 0x20 /* Analog Comparator 1 State bit mask. */ -#define AC_AC1STATE_bp 5 /* Analog Comparator 1 State bit position. */ - -#define AC_AC0STATE_bm 0x10 /* Analog Comparator 0 State bit mask. */ -#define AC_AC0STATE_bp 4 /* Analog Comparator 0 State bit position. */ - -#define AC_WIF_bm 0x04 /* Window Mode Interrupt Flag bit mask. */ -#define AC_WIF_bp 2 /* Window Mode Interrupt Flag bit position. */ - -#define AC_AC1IF_bm 0x02 /* Analog Comparator 1 Interrupt Flag bit mask. */ -#define AC_AC1IF_bp 1 /* Analog Comparator 1 Interrupt Flag bit position. */ - -#define AC_AC0IF_bm 0x01 /* Analog Comparator 0 Interrupt Flag bit mask. */ -#define AC_AC0IF_bp 0 /* Analog Comparator 0 Interrupt Flag bit position. */ - -/* RTC - Real-Time Counter */ -/* RTC.CTRL bit masks and bit positions */ -#define RTC_PRESCALER_gm 0x07 /* Prescaling Factor group mask. */ -#define RTC_PRESCALER_gp 0 /* Prescaling Factor group position. */ -#define RTC_PRESCALER0_bm (1<<0) /* Prescaling Factor bit 0 mask. */ -#define RTC_PRESCALER0_bp 0 /* Prescaling Factor bit 0 position. */ -#define RTC_PRESCALER1_bm (1<<1) /* Prescaling Factor bit 1 mask. */ -#define RTC_PRESCALER1_bp 1 /* Prescaling Factor bit 1 position. */ -#define RTC_PRESCALER2_bm (1<<2) /* Prescaling Factor bit 2 mask. */ -#define RTC_PRESCALER2_bp 2 /* Prescaling Factor bit 2 position. */ - -/* RTC.STATUS bit masks and bit positions */ -#define RTC_SYNCBUSY_bm 0x01 /* Synchronization Busy Flag bit mask. */ -#define RTC_SYNCBUSY_bp 0 /* Synchronization Busy Flag bit position. */ - -/* RTC.INTCTRL bit masks and bit positions */ -#define RTC_COMPINTLVL_gm 0x0C /* Compare Match Interrupt Level group mask. */ -#define RTC_COMPINTLVL_gp 2 /* Compare Match Interrupt Level group position. */ -#define RTC_COMPINTLVL0_bm (1<<2) /* Compare Match Interrupt Level bit 0 mask. */ -#define RTC_COMPINTLVL0_bp 2 /* Compare Match Interrupt Level bit 0 position. */ -#define RTC_COMPINTLVL1_bm (1<<3) /* Compare Match Interrupt Level bit 1 mask. */ -#define RTC_COMPINTLVL1_bp 3 /* Compare Match Interrupt Level bit 1 position. */ - -#define RTC_OVFINTLVL_gm 0x03 /* Overflow Interrupt Level group mask. */ -#define RTC_OVFINTLVL_gp 0 /* Overflow Interrupt Level group position. */ -#define RTC_OVFINTLVL0_bm (1<<0) /* Overflow Interrupt Level bit 0 mask. */ -#define RTC_OVFINTLVL0_bp 0 /* Overflow Interrupt Level bit 0 position. */ -#define RTC_OVFINTLVL1_bm (1<<1) /* Overflow Interrupt Level bit 1 mask. */ -#define RTC_OVFINTLVL1_bp 1 /* Overflow Interrupt Level bit 1 position. */ - -/* RTC.INTFLAGS bit masks and bit positions */ -#define RTC_COMPIF_bm 0x02 /* Compare Match Interrupt Flag bit mask. */ -#define RTC_COMPIF_bp 1 /* Compare Match Interrupt Flag bit position. */ - -#define RTC_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ -#define RTC_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ - -/* TWI - Two-Wire Interface */ -/* TWI_MASTER.CTRLA bit masks and bit positions */ -#define TWI_MASTER_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ -#define TWI_MASTER_INTLVL_gp 6 /* Interrupt Level group position. */ -#define TWI_MASTER_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ -#define TWI_MASTER_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ -#define TWI_MASTER_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ -#define TWI_MASTER_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ - -#define TWI_MASTER_RIEN_bm 0x20 /* Read Interrupt Enable bit mask. */ -#define TWI_MASTER_RIEN_bp 5 /* Read Interrupt Enable bit position. */ - -#define TWI_MASTER_WIEN_bm 0x10 /* Write Interrupt Enable bit mask. */ -#define TWI_MASTER_WIEN_bp 4 /* Write Interrupt Enable bit position. */ - -#define TWI_MASTER_ENABLE_bm 0x08 /* Enable TWI Master bit mask. */ -#define TWI_MASTER_ENABLE_bp 3 /* Enable TWI Master bit position. */ - -/* TWI_MASTER.CTRLB bit masks and bit positions */ -#define TWI_MASTER_TIMEOUT_gm 0x0C /* Inactive Bus Timeout group mask. */ -#define TWI_MASTER_TIMEOUT_gp 2 /* Inactive Bus Timeout group position. */ -#define TWI_MASTER_TIMEOUT0_bm (1<<2) /* Inactive Bus Timeout bit 0 mask. */ -#define TWI_MASTER_TIMEOUT0_bp 2 /* Inactive Bus Timeout bit 0 position. */ -#define TWI_MASTER_TIMEOUT1_bm (1<<3) /* Inactive Bus Timeout bit 1 mask. */ -#define TWI_MASTER_TIMEOUT1_bp 3 /* Inactive Bus Timeout bit 1 position. */ - -#define TWI_MASTER_QCEN_bm 0x02 /* Quick Command Enable bit mask. */ -#define TWI_MASTER_QCEN_bp 1 /* Quick Command Enable bit position. */ - -#define TWI_MASTER_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ -#define TWI_MASTER_SMEN_bp 0 /* Smart Mode Enable bit position. */ - -/* TWI_MASTER.CTRLC bit masks and bit positions */ -#define TWI_MASTER_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ -#define TWI_MASTER_ACKACT_bp 2 /* Acknowledge Action bit position. */ - -#define TWI_MASTER_CMD_gm 0x03 /* Command group mask. */ -#define TWI_MASTER_CMD_gp 0 /* Command group position. */ -#define TWI_MASTER_CMD0_bm (1<<0) /* Command bit 0 mask. */ -#define TWI_MASTER_CMD0_bp 0 /* Command bit 0 position. */ -#define TWI_MASTER_CMD1_bm (1<<1) /* Command bit 1 mask. */ -#define TWI_MASTER_CMD1_bp 1 /* Command bit 1 position. */ - -/* TWI_MASTER.STATUS bit masks and bit positions */ -#define TWI_MASTER_RIF_bm 0x80 /* Read Interrupt Flag bit mask. */ -#define TWI_MASTER_RIF_bp 7 /* Read Interrupt Flag bit position. */ - -#define TWI_MASTER_WIF_bm 0x40 /* Write Interrupt Flag bit mask. */ -#define TWI_MASTER_WIF_bp 6 /* Write Interrupt Flag bit position. */ - -#define TWI_MASTER_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ -#define TWI_MASTER_CLKHOLD_bp 5 /* Clock Hold bit position. */ - -#define TWI_MASTER_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ -#define TWI_MASTER_RXACK_bp 4 /* Received Acknowledge bit position. */ - -#define TWI_MASTER_ARBLOST_bm 0x08 /* Arbitration Lost bit mask. */ -#define TWI_MASTER_ARBLOST_bp 3 /* Arbitration Lost bit position. */ - -#define TWI_MASTER_BUSERR_bm 0x04 /* Bus Error bit mask. */ -#define TWI_MASTER_BUSERR_bp 2 /* Bus Error bit position. */ - -#define TWI_MASTER_BUSSTATE_gm 0x03 /* Bus State group mask. */ -#define TWI_MASTER_BUSSTATE_gp 0 /* Bus State group position. */ -#define TWI_MASTER_BUSSTATE0_bm (1<<0) /* Bus State bit 0 mask. */ -#define TWI_MASTER_BUSSTATE0_bp 0 /* Bus State bit 0 position. */ -#define TWI_MASTER_BUSSTATE1_bm (1<<1) /* Bus State bit 1 mask. */ -#define TWI_MASTER_BUSSTATE1_bp 1 /* Bus State bit 1 position. */ - -/* TWI_SLAVE.CTRLA bit masks and bit positions */ -#define TWI_SLAVE_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ -#define TWI_SLAVE_INTLVL_gp 6 /* Interrupt Level group position. */ -#define TWI_SLAVE_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ -#define TWI_SLAVE_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ -#define TWI_SLAVE_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ -#define TWI_SLAVE_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ - -#define TWI_SLAVE_DIEN_bm 0x20 /* Data Interrupt Enable bit mask. */ -#define TWI_SLAVE_DIEN_bp 5 /* Data Interrupt Enable bit position. */ - -#define TWI_SLAVE_APIEN_bm 0x10 /* Address/Stop Interrupt Enable bit mask. */ -#define TWI_SLAVE_APIEN_bp 4 /* Address/Stop Interrupt Enable bit position. */ - -#define TWI_SLAVE_ENABLE_bm 0x08 /* Enable TWI Slave bit mask. */ -#define TWI_SLAVE_ENABLE_bp 3 /* Enable TWI Slave bit position. */ - -#define TWI_SLAVE_PIEN_bm 0x04 /* Stop Interrupt Enable bit mask. */ -#define TWI_SLAVE_PIEN_bp 2 /* Stop Interrupt Enable bit position. */ - -#define TWI_SLAVE_PMEN_bm 0x02 /* Promiscuous Mode Enable bit mask. */ -#define TWI_SLAVE_PMEN_bp 1 /* Promiscuous Mode Enable bit position. */ - -#define TWI_SLAVE_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ -#define TWI_SLAVE_SMEN_bp 0 /* Smart Mode Enable bit position. */ - -/* TWI_SLAVE.CTRLB bit masks and bit positions */ -#define TWI_SLAVE_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ -#define TWI_SLAVE_ACKACT_bp 2 /* Acknowledge Action bit position. */ - -#define TWI_SLAVE_CMD_gm 0x03 /* Command group mask. */ -#define TWI_SLAVE_CMD_gp 0 /* Command group position. */ -#define TWI_SLAVE_CMD0_bm (1<<0) /* Command bit 0 mask. */ -#define TWI_SLAVE_CMD0_bp 0 /* Command bit 0 position. */ -#define TWI_SLAVE_CMD1_bm (1<<1) /* Command bit 1 mask. */ -#define TWI_SLAVE_CMD1_bp 1 /* Command bit 1 position. */ - -/* TWI_SLAVE.STATUS bit masks and bit positions */ -#define TWI_SLAVE_DIF_bm 0x80 /* Data Interrupt Flag bit mask. */ -#define TWI_SLAVE_DIF_bp 7 /* Data Interrupt Flag bit position. */ - -#define TWI_SLAVE_APIF_bm 0x40 /* Address/Stop Interrupt Flag bit mask. */ -#define TWI_SLAVE_APIF_bp 6 /* Address/Stop Interrupt Flag bit position. */ - -#define TWI_SLAVE_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ -#define TWI_SLAVE_CLKHOLD_bp 5 /* Clock Hold bit position. */ - -#define TWI_SLAVE_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ -#define TWI_SLAVE_RXACK_bp 4 /* Received Acknowledge bit position. */ - -#define TWI_SLAVE_COLL_bm 0x08 /* Collision bit mask. */ -#define TWI_SLAVE_COLL_bp 3 /* Collision bit position. */ - -#define TWI_SLAVE_BUSERR_bm 0x04 /* Bus Error bit mask. */ -#define TWI_SLAVE_BUSERR_bp 2 /* Bus Error bit position. */ - -#define TWI_SLAVE_DIR_bm 0x02 /* Read/Write Direction bit mask. */ -#define TWI_SLAVE_DIR_bp 1 /* Read/Write Direction bit position. */ - -#define TWI_SLAVE_AP_bm 0x01 /* Slave Address or Stop bit mask. */ -#define TWI_SLAVE_AP_bp 0 /* Slave Address or Stop bit position. */ - -/* TWI_SLAVE.ADDRMASK bit masks and bit positions */ -#define TWI_SLAVE_ADDRMASK_gm 0xFE /* Address Mask group mask. */ -#define TWI_SLAVE_ADDRMASK_gp 1 /* Address Mask group position. */ -#define TWI_SLAVE_ADDRMASK0_bm (1<<1) /* Address Mask bit 0 mask. */ -#define TWI_SLAVE_ADDRMASK0_bp 1 /* Address Mask bit 0 position. */ -#define TWI_SLAVE_ADDRMASK1_bm (1<<2) /* Address Mask bit 1 mask. */ -#define TWI_SLAVE_ADDRMASK1_bp 2 /* Address Mask bit 1 position. */ -#define TWI_SLAVE_ADDRMASK2_bm (1<<3) /* Address Mask bit 2 mask. */ -#define TWI_SLAVE_ADDRMASK2_bp 3 /* Address Mask bit 2 position. */ -#define TWI_SLAVE_ADDRMASK3_bm (1<<4) /* Address Mask bit 3 mask. */ -#define TWI_SLAVE_ADDRMASK3_bp 4 /* Address Mask bit 3 position. */ -#define TWI_SLAVE_ADDRMASK4_bm (1<<5) /* Address Mask bit 4 mask. */ -#define TWI_SLAVE_ADDRMASK4_bp 5 /* Address Mask bit 4 position. */ -#define TWI_SLAVE_ADDRMASK5_bm (1<<6) /* Address Mask bit 5 mask. */ -#define TWI_SLAVE_ADDRMASK5_bp 6 /* Address Mask bit 5 position. */ -#define TWI_SLAVE_ADDRMASK6_bm (1<<7) /* Address Mask bit 6 mask. */ -#define TWI_SLAVE_ADDRMASK6_bp 7 /* Address Mask bit 6 position. */ - -#define TWI_SLAVE_ADDREN_bm 0x01 /* Address Enable bit mask. */ -#define TWI_SLAVE_ADDREN_bp 0 /* Address Enable bit position. */ - -/* TWI.CTRL bit masks and bit positions */ -#define TWI_SDAHOLD_gm 0x06 /* SDA Hold Time Enable group mask. */ -#define TWI_SDAHOLD_gp 1 /* SDA Hold Time Enable group position. */ -#define TWI_SDAHOLD0_bm (1<<1) /* SDA Hold Time Enable bit 0 mask. */ -#define TWI_SDAHOLD0_bp 1 /* SDA Hold Time Enable bit 0 position. */ -#define TWI_SDAHOLD1_bm (1<<2) /* SDA Hold Time Enable bit 1 mask. */ -#define TWI_SDAHOLD1_bp 2 /* SDA Hold Time Enable bit 1 position. */ - -#define TWI_EDIEN_bm 0x01 /* External Driver Interface Enable bit mask. */ -#define TWI_EDIEN_bp 0 /* External Driver Interface Enable bit position. */ - -/* PORT - I/O Port Configuration */ -/* PORT.INTCTRL bit masks and bit positions */ -#define PORT_INT1LVL_gm 0x0C /* Port Interrupt 1 Level group mask. */ -#define PORT_INT1LVL_gp 2 /* Port Interrupt 1 Level group position. */ -#define PORT_INT1LVL0_bm (1<<2) /* Port Interrupt 1 Level bit 0 mask. */ -#define PORT_INT1LVL0_bp 2 /* Port Interrupt 1 Level bit 0 position. */ -#define PORT_INT1LVL1_bm (1<<3) /* Port Interrupt 1 Level bit 1 mask. */ -#define PORT_INT1LVL1_bp 3 /* Port Interrupt 1 Level bit 1 position. */ - -#define PORT_INT0LVL_gm 0x03 /* Port Interrupt 0 Level group mask. */ -#define PORT_INT0LVL_gp 0 /* Port Interrupt 0 Level group position. */ -#define PORT_INT0LVL0_bm (1<<0) /* Port Interrupt 0 Level bit 0 mask. */ -#define PORT_INT0LVL0_bp 0 /* Port Interrupt 0 Level bit 0 position. */ -#define PORT_INT0LVL1_bm (1<<1) /* Port Interrupt 0 Level bit 1 mask. */ -#define PORT_INT0LVL1_bp 1 /* Port Interrupt 0 Level bit 1 position. */ - -/* PORT.INTFLAGS bit masks and bit positions */ -#define PORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ -#define PORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ - -#define PORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ -#define PORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ - -/* PORT.REMAP bit masks and bit positions */ -#define PORT_SPI_bm 0x20 /* SPI bit mask. */ -#define PORT_SPI_bp 5 /* SPI bit position. */ - -#define PORT_USART0_bm 0x10 /* USART0 bit mask. */ -#define PORT_USART0_bp 4 /* USART0 bit position. */ - -#define PORT_TC0D_bm 0x08 /* Timer/Counter 0 Output Compare D bit mask. */ -#define PORT_TC0D_bp 3 /* Timer/Counter 0 Output Compare D bit position. */ - -#define PORT_TC0C_bm 0x04 /* Timer/Counter 0 Output Compare C bit mask. */ -#define PORT_TC0C_bp 2 /* Timer/Counter 0 Output Compare C bit position. */ - -#define PORT_TC0B_bm 0x02 /* Timer/Counter 0 Output Compare B bit mask. */ -#define PORT_TC0B_bp 1 /* Timer/Counter 0 Output Compare B bit position. */ - -#define PORT_TC0A_bm 0x01 /* Timer/Counter 0 Output Compare A bit mask. */ -#define PORT_TC0A_bp 0 /* Timer/Counter 0 Output Compare A bit position. */ - -/* PORT.PIN0CTRL bit masks and bit positions */ -#define PORT_SRLEN_bm 0x80 /* Slew Rate Enable bit mask. */ -#define PORT_SRLEN_bp 7 /* Slew Rate Enable bit position. */ - -#define PORT_INVEN_bm 0x40 /* Inverted I/O Enable bit mask. */ -#define PORT_INVEN_bp 6 /* Inverted I/O Enable bit position. */ - -#define PORT_OPC_gm 0x38 /* Output/Pull Configuration group mask. */ -#define PORT_OPC_gp 3 /* Output/Pull Configuration group position. */ -#define PORT_OPC0_bm (1<<3) /* Output/Pull Configuration bit 0 mask. */ -#define PORT_OPC0_bp 3 /* Output/Pull Configuration bit 0 position. */ -#define PORT_OPC1_bm (1<<4) /* Output/Pull Configuration bit 1 mask. */ -#define PORT_OPC1_bp 4 /* Output/Pull Configuration bit 1 position. */ -#define PORT_OPC2_bm (1<<5) /* Output/Pull Configuration bit 2 mask. */ -#define PORT_OPC2_bp 5 /* Output/Pull Configuration bit 2 position. */ - -#define PORT_ISC_gm 0x07 /* Input/Sense Configuration group mask. */ -#define PORT_ISC_gp 0 /* Input/Sense Configuration group position. */ -#define PORT_ISC0_bm (1<<0) /* Input/Sense Configuration bit 0 mask. */ -#define PORT_ISC0_bp 0 /* Input/Sense Configuration bit 0 position. */ -#define PORT_ISC1_bm (1<<1) /* Input/Sense Configuration bit 1 mask. */ -#define PORT_ISC1_bp 1 /* Input/Sense Configuration bit 1 position. */ -#define PORT_ISC2_bm (1<<2) /* Input/Sense Configuration bit 2 mask. */ -#define PORT_ISC2_bp 2 /* Input/Sense Configuration bit 2 position. */ - -/* PORT.PIN1CTRL bit masks and bit positions */ -/* PORT_SRLEN Predefined. */ -/* PORT_SRLEN Predefined. */ - -/* PORT_INVEN Predefined. */ -/* PORT_INVEN Predefined. */ - -/* PORT_OPC Predefined. */ -/* PORT_OPC Predefined. */ - -/* PORT_ISC Predefined. */ -/* PORT_ISC Predefined. */ - -/* PORT.PIN2CTRL bit masks and bit positions */ -/* PORT_SRLEN Predefined. */ -/* PORT_SRLEN Predefined. */ - -/* PORT_INVEN Predefined. */ -/* PORT_INVEN Predefined. */ - -/* PORT_OPC Predefined. */ -/* PORT_OPC Predefined. */ - -/* PORT_ISC Predefined. */ -/* PORT_ISC Predefined. */ - -/* PORT.PIN3CTRL bit masks and bit positions */ -/* PORT_SRLEN Predefined. */ -/* PORT_SRLEN Predefined. */ - -/* PORT_INVEN Predefined. */ -/* PORT_INVEN Predefined. */ - -/* PORT_OPC Predefined. */ -/* PORT_OPC Predefined. */ - -/* PORT_ISC Predefined. */ -/* PORT_ISC Predefined. */ - -/* PORT.PIN4CTRL bit masks and bit positions */ -/* PORT_SRLEN Predefined. */ -/* PORT_SRLEN Predefined. */ - -/* PORT_INVEN Predefined. */ -/* PORT_INVEN Predefined. */ - -/* PORT_OPC Predefined. */ -/* PORT_OPC Predefined. */ - -/* PORT_ISC Predefined. */ -/* PORT_ISC Predefined. */ - -/* PORT.PIN5CTRL bit masks and bit positions */ -/* PORT_SRLEN Predefined. */ -/* PORT_SRLEN Predefined. */ - -/* PORT_INVEN Predefined. */ -/* PORT_INVEN Predefined. */ - -/* PORT_OPC Predefined. */ -/* PORT_OPC Predefined. */ - -/* PORT_ISC Predefined. */ -/* PORT_ISC Predefined. */ - -/* PORT.PIN6CTRL bit masks and bit positions */ -/* PORT_SRLEN Predefined. */ -/* PORT_SRLEN Predefined. */ - -/* PORT_INVEN Predefined. */ -/* PORT_INVEN Predefined. */ - -/* PORT_OPC Predefined. */ -/* PORT_OPC Predefined. */ - -/* PORT_ISC Predefined. */ -/* PORT_ISC Predefined. */ - -/* PORT.PIN7CTRL bit masks and bit positions */ -/* PORT_SRLEN Predefined. */ -/* PORT_SRLEN Predefined. */ - -/* PORT_INVEN Predefined. */ -/* PORT_INVEN Predefined. */ - -/* PORT_OPC Predefined. */ -/* PORT_OPC Predefined. */ - -/* PORT_ISC Predefined. */ -/* PORT_ISC Predefined. */ - -/* TC - 16-bit Timer/Counter With PWM */ -/* TC0.CTRLA bit masks and bit positions */ -#define TC0_CLKSEL_gm 0x0F /* Clock Selection group mask. */ -#define TC0_CLKSEL_gp 0 /* Clock Selection group position. */ -#define TC0_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ -#define TC0_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ -#define TC0_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ -#define TC0_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ -#define TC0_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ -#define TC0_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ -#define TC0_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ -#define TC0_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ - -/* TC0.CTRLB bit masks and bit positions */ -#define TC0_CCDEN_bm 0x80 /* Compare or Capture D Enable bit mask. */ -#define TC0_CCDEN_bp 7 /* Compare or Capture D Enable bit position. */ - -#define TC0_CCCEN_bm 0x40 /* Compare or Capture C Enable bit mask. */ -#define TC0_CCCEN_bp 6 /* Compare or Capture C Enable bit position. */ - -#define TC0_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ -#define TC0_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ - -#define TC0_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ -#define TC0_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ - -#define TC0_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ -#define TC0_WGMODE_gp 0 /* Waveform generation mode group position. */ -#define TC0_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ -#define TC0_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ -#define TC0_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ -#define TC0_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ -#define TC0_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ -#define TC0_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ - -/* TC0.CTRLC bit masks and bit positions */ -#define TC0_CMPD_bm 0x08 /* Compare D Output Value bit mask. */ -#define TC0_CMPD_bp 3 /* Compare D Output Value bit position. */ - -#define TC0_CMPC_bm 0x04 /* Compare C Output Value bit mask. */ -#define TC0_CMPC_bp 2 /* Compare C Output Value bit position. */ - -#define TC0_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ -#define TC0_CMPB_bp 1 /* Compare B Output Value bit position. */ - -#define TC0_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ -#define TC0_CMPA_bp 0 /* Compare A Output Value bit position. */ - -/* TC0.CTRLD bit masks and bit positions */ -#define TC0_EVACT_gm 0xE0 /* Event Action group mask. */ -#define TC0_EVACT_gp 5 /* Event Action group position. */ -#define TC0_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ -#define TC0_EVACT0_bp 5 /* Event Action bit 0 position. */ -#define TC0_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ -#define TC0_EVACT1_bp 6 /* Event Action bit 1 position. */ -#define TC0_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ -#define TC0_EVACT2_bp 7 /* Event Action bit 2 position. */ - -#define TC0_EVDLY_bm 0x10 /* Event Delay bit mask. */ -#define TC0_EVDLY_bp 4 /* Event Delay bit position. */ - -#define TC0_EVSEL_gm 0x0F /* Event Source Select group mask. */ -#define TC0_EVSEL_gp 0 /* Event Source Select group position. */ -#define TC0_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ -#define TC0_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ -#define TC0_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ -#define TC0_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ -#define TC0_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ -#define TC0_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ -#define TC0_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ -#define TC0_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ - -/* TC0.CTRLE bit masks and bit positions */ -#define TC0_BYTEM_gm 0x03 /* Byte Mode group mask. */ -#define TC0_BYTEM_gp 0 /* Byte Mode group position. */ -#define TC0_BYTEM0_bm (1<<0) /* Byte Mode bit 0 mask. */ -#define TC0_BYTEM0_bp 0 /* Byte Mode bit 0 position. */ -#define TC0_BYTEM1_bm (1<<1) /* Byte Mode bit 1 mask. */ -#define TC0_BYTEM1_bp 1 /* Byte Mode bit 1 position. */ - -/* TC0.INTCTRLA bit masks and bit positions */ -#define TC0_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ -#define TC0_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ -#define TC0_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ -#define TC0_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ -#define TC0_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ -#define TC0_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ - -#define TC0_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ -#define TC0_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ -#define TC0_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ -#define TC0_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ -#define TC0_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ -#define TC0_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ - -/* TC0.INTCTRLB bit masks and bit positions */ -#define TC0_CCDINTLVL_gm 0xC0 /* Compare or Capture D Interrupt Level group mask. */ -#define TC0_CCDINTLVL_gp 6 /* Compare or Capture D Interrupt Level group position. */ -#define TC0_CCDINTLVL0_bm (1<<6) /* Compare or Capture D Interrupt Level bit 0 mask. */ -#define TC0_CCDINTLVL0_bp 6 /* Compare or Capture D Interrupt Level bit 0 position. */ -#define TC0_CCDINTLVL1_bm (1<<7) /* Compare or Capture D Interrupt Level bit 1 mask. */ -#define TC0_CCDINTLVL1_bp 7 /* Compare or Capture D Interrupt Level bit 1 position. */ - -#define TC0_CCCINTLVL_gm 0x30 /* Compare or Capture C Interrupt Level group mask. */ -#define TC0_CCCINTLVL_gp 4 /* Compare or Capture C Interrupt Level group position. */ -#define TC0_CCCINTLVL0_bm (1<<4) /* Compare or Capture C Interrupt Level bit 0 mask. */ -#define TC0_CCCINTLVL0_bp 4 /* Compare or Capture C Interrupt Level bit 0 position. */ -#define TC0_CCCINTLVL1_bm (1<<5) /* Compare or Capture C Interrupt Level bit 1 mask. */ -#define TC0_CCCINTLVL1_bp 5 /* Compare or Capture C Interrupt Level bit 1 position. */ - -#define TC0_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ -#define TC0_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ -#define TC0_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ -#define TC0_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ -#define TC0_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ -#define TC0_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ - -#define TC0_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ -#define TC0_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ -#define TC0_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ -#define TC0_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ -#define TC0_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ -#define TC0_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ - -/* TC0.CTRLFCLR bit masks and bit positions */ -#define TC0_CMD_gm 0x0C /* Command group mask. */ -#define TC0_CMD_gp 2 /* Command group position. */ -#define TC0_CMD0_bm (1<<2) /* Command bit 0 mask. */ -#define TC0_CMD0_bp 2 /* Command bit 0 position. */ -#define TC0_CMD1_bm (1<<3) /* Command bit 1 mask. */ -#define TC0_CMD1_bp 3 /* Command bit 1 position. */ - -#define TC0_LUPD_bm 0x02 /* Lock Update bit mask. */ -#define TC0_LUPD_bp 1 /* Lock Update bit position. */ - -#define TC0_DIR_bm 0x01 /* Direction bit mask. */ -#define TC0_DIR_bp 0 /* Direction bit position. */ - -/* TC0.CTRLFSET bit masks and bit positions */ -/* TC0_CMD Predefined. */ -/* TC0_CMD Predefined. */ - -/* TC0_LUPD Predefined. */ -/* TC0_LUPD Predefined. */ - -/* TC0_DIR Predefined. */ -/* TC0_DIR Predefined. */ - -/* TC0.CTRLGCLR bit masks and bit positions */ -#define TC0_CCDBV_bm 0x10 /* Compare or Capture D Buffer Valid bit mask. */ -#define TC0_CCDBV_bp 4 /* Compare or Capture D Buffer Valid bit position. */ - -#define TC0_CCCBV_bm 0x08 /* Compare or Capture C Buffer Valid bit mask. */ -#define TC0_CCCBV_bp 3 /* Compare or Capture C Buffer Valid bit position. */ - -#define TC0_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ -#define TC0_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ - -#define TC0_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ -#define TC0_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ - -#define TC0_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ -#define TC0_PERBV_bp 0 /* Period Buffer Valid bit position. */ - -/* TC0.CTRLGSET bit masks and bit positions */ -/* TC0_CCDBV Predefined. */ -/* TC0_CCDBV Predefined. */ - -/* TC0_CCCBV Predefined. */ -/* TC0_CCCBV Predefined. */ - -/* TC0_CCBBV Predefined. */ -/* TC0_CCBBV Predefined. */ - -/* TC0_CCABV Predefined. */ -/* TC0_CCABV Predefined. */ - -/* TC0_PERBV Predefined. */ -/* TC0_PERBV Predefined. */ - -/* TC0.INTFLAGS bit masks and bit positions */ -#define TC0_CCDIF_bm 0x80 /* Compare or Capture D Interrupt Flag bit mask. */ -#define TC0_CCDIF_bp 7 /* Compare or Capture D Interrupt Flag bit position. */ - -#define TC0_CCCIF_bm 0x40 /* Compare or Capture C Interrupt Flag bit mask. */ -#define TC0_CCCIF_bp 6 /* Compare or Capture C Interrupt Flag bit position. */ - -#define TC0_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ -#define TC0_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ - -#define TC0_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ -#define TC0_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ - -#define TC0_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ -#define TC0_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ - -#define TC0_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ -#define TC0_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ - -/* TC1.CTRLA bit masks and bit positions */ -#define TC1_CLKSEL_gm 0x0F /* Clock Selection group mask. */ -#define TC1_CLKSEL_gp 0 /* Clock Selection group position. */ -#define TC1_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ -#define TC1_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ -#define TC1_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ -#define TC1_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ -#define TC1_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ -#define TC1_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ -#define TC1_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ -#define TC1_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ - -/* TC1.CTRLB bit masks and bit positions */ -#define TC1_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ -#define TC1_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ - -#define TC1_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ -#define TC1_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ - -#define TC1_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ -#define TC1_WGMODE_gp 0 /* Waveform generation mode group position. */ -#define TC1_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ -#define TC1_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ -#define TC1_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ -#define TC1_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ -#define TC1_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ -#define TC1_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ - -/* TC1.CTRLC bit masks and bit positions */ -#define TC1_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ -#define TC1_CMPB_bp 1 /* Compare B Output Value bit position. */ - -#define TC1_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ -#define TC1_CMPA_bp 0 /* Compare A Output Value bit position. */ - -/* TC1.CTRLD bit masks and bit positions */ -#define TC1_EVACT_gm 0xE0 /* Event Action group mask. */ -#define TC1_EVACT_gp 5 /* Event Action group position. */ -#define TC1_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ -#define TC1_EVACT0_bp 5 /* Event Action bit 0 position. */ -#define TC1_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ -#define TC1_EVACT1_bp 6 /* Event Action bit 1 position. */ -#define TC1_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ -#define TC1_EVACT2_bp 7 /* Event Action bit 2 position. */ - -#define TC1_EVDLY_bm 0x10 /* Event Delay bit mask. */ -#define TC1_EVDLY_bp 4 /* Event Delay bit position. */ - -#define TC1_EVSEL_gm 0x0F /* Event Source Select group mask. */ -#define TC1_EVSEL_gp 0 /* Event Source Select group position. */ -#define TC1_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ -#define TC1_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ -#define TC1_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ -#define TC1_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ -#define TC1_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ -#define TC1_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ -#define TC1_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ -#define TC1_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ - -/* TC1.CTRLE bit masks and bit positions */ -#define TC1_BYTEM_bm 0x01 /* Byte Mode bit mask. */ -#define TC1_BYTEM_bp 0 /* Byte Mode bit position. */ - -/* TC1.INTCTRLA bit masks and bit positions */ -#define TC1_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ -#define TC1_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ -#define TC1_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ -#define TC1_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ -#define TC1_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ -#define TC1_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ - -#define TC1_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ -#define TC1_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ -#define TC1_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ -#define TC1_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ -#define TC1_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ -#define TC1_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ - -/* TC1.INTCTRLB bit masks and bit positions */ -#define TC1_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ -#define TC1_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ -#define TC1_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ -#define TC1_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ -#define TC1_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ -#define TC1_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ - -#define TC1_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ -#define TC1_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ -#define TC1_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ -#define TC1_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ -#define TC1_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ -#define TC1_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ - -/* TC1.CTRLFCLR bit masks and bit positions */ -#define TC1_CMD_gm 0x0C /* Command group mask. */ -#define TC1_CMD_gp 2 /* Command group position. */ -#define TC1_CMD0_bm (1<<2) /* Command bit 0 mask. */ -#define TC1_CMD0_bp 2 /* Command bit 0 position. */ -#define TC1_CMD1_bm (1<<3) /* Command bit 1 mask. */ -#define TC1_CMD1_bp 3 /* Command bit 1 position. */ - -#define TC1_LUPD_bm 0x02 /* Lock Update bit mask. */ -#define TC1_LUPD_bp 1 /* Lock Update bit position. */ - -#define TC1_DIR_bm 0x01 /* Direction bit mask. */ -#define TC1_DIR_bp 0 /* Direction bit position. */ - -/* TC1.CTRLFSET bit masks and bit positions */ -/* TC1_CMD Predefined. */ -/* TC1_CMD Predefined. */ - -/* TC1_LUPD Predefined. */ -/* TC1_LUPD Predefined. */ - -/* TC1_DIR Predefined. */ -/* TC1_DIR Predefined. */ - -/* TC1.CTRLGCLR bit masks and bit positions */ -#define TC1_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ -#define TC1_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ - -#define TC1_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ -#define TC1_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ - -#define TC1_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ -#define TC1_PERBV_bp 0 /* Period Buffer Valid bit position. */ - -/* TC1.CTRLGSET bit masks and bit positions */ -/* TC1_CCBBV Predefined. */ -/* TC1_CCBBV Predefined. */ - -/* TC1_CCABV Predefined. */ -/* TC1_CCABV Predefined. */ - -/* TC1_PERBV Predefined. */ -/* TC1_PERBV Predefined. */ - -/* TC1.INTFLAGS bit masks and bit positions */ -#define TC1_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ -#define TC1_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ - -#define TC1_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ -#define TC1_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ - -#define TC1_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ -#define TC1_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ - -#define TC1_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ -#define TC1_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ - -/* TC2 - 16-bit Timer/Counter type 2 */ -/* TC2.CTRLA bit masks and bit positions */ -#define TC2_CLKSEL_gm 0x0F /* Clock Selection group mask. */ -#define TC2_CLKSEL_gp 0 /* Clock Selection group position. */ -#define TC2_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ -#define TC2_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ -#define TC2_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ -#define TC2_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ -#define TC2_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ -#define TC2_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ -#define TC2_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ -#define TC2_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ - -/* TC2.CTRLB bit masks and bit positions */ -#define TC2_HCMPDEN_bm 0x80 /* High Byte Compare D Enable bit mask. */ -#define TC2_HCMPDEN_bp 7 /* High Byte Compare D Enable bit position. */ - -#define TC2_HCMPCEN_bm 0x40 /* High Byte Compare C Enable bit mask. */ -#define TC2_HCMPCEN_bp 6 /* High Byte Compare C Enable bit position. */ - -#define TC2_HCMPBEN_bm 0x20 /* High Byte Compare B Enable bit mask. */ -#define TC2_HCMPBEN_bp 5 /* High Byte Compare B Enable bit position. */ - -#define TC2_HCMPAEN_bm 0x10 /* High Byte Compare A Enable bit mask. */ -#define TC2_HCMPAEN_bp 4 /* High Byte Compare A Enable bit position. */ - -#define TC2_LCMPDEN_bm 0x08 /* Low Byte Compare D Enable bit mask. */ -#define TC2_LCMPDEN_bp 3 /* Low Byte Compare D Enable bit position. */ - -#define TC2_LCMPCEN_bm 0x04 /* Low Byte Compare C Enable bit mask. */ -#define TC2_LCMPCEN_bp 2 /* Low Byte Compare C Enable bit position. */ - -#define TC2_LCMPBEN_bm 0x02 /* Low Byte Compare B Enable bit mask. */ -#define TC2_LCMPBEN_bp 1 /* Low Byte Compare B Enable bit position. */ - -#define TC2_LCMPAEN_bm 0x01 /* Low Byte Compare A Enable bit mask. */ -#define TC2_LCMPAEN_bp 0 /* Low Byte Compare A Enable bit position. */ - -/* TC2.CTRLC bit masks and bit positions */ -#define TC2_HCMPD_bm 0x80 /* High Byte Compare D Output Value bit mask. */ -#define TC2_HCMPD_bp 7 /* High Byte Compare D Output Value bit position. */ - -#define TC2_HCMPC_bm 0x40 /* High Byte Compare C Output Value bit mask. */ -#define TC2_HCMPC_bp 6 /* High Byte Compare C Output Value bit position. */ - -#define TC2_HCMPB_bm 0x20 /* High Byte Compare B Output Value bit mask. */ -#define TC2_HCMPB_bp 5 /* High Byte Compare B Output Value bit position. */ - -#define TC2_HCMPA_bm 0x10 /* High Byte Compare A Output Value bit mask. */ -#define TC2_HCMPA_bp 4 /* High Byte Compare A Output Value bit position. */ - -#define TC2_LCMPD_bm 0x08 /* Low Byte Compare D Output Value bit mask. */ -#define TC2_LCMPD_bp 3 /* Low Byte Compare D Output Value bit position. */ - -#define TC2_LCMPC_bm 0x04 /* Low Byte Compare C Output Value bit mask. */ -#define TC2_LCMPC_bp 2 /* Low Byte Compare C Output Value bit position. */ - -#define TC2_LCMPB_bm 0x02 /* Low Byte Compare B Output Value bit mask. */ -#define TC2_LCMPB_bp 1 /* Low Byte Compare B Output Value bit position. */ - -#define TC2_LCMPA_bm 0x01 /* Low Byte Compare A Output Value bit mask. */ -#define TC2_LCMPA_bp 0 /* Low Byte Compare A Output Value bit position. */ - -/* TC2.CTRLE bit masks and bit positions */ -#define TC2_BYTEM_gm 0x03 /* Byte Mode group mask. */ -#define TC2_BYTEM_gp 0 /* Byte Mode group position. */ -#define TC2_BYTEM0_bm (1<<0) /* Byte Mode bit 0 mask. */ -#define TC2_BYTEM0_bp 0 /* Byte Mode bit 0 position. */ -#define TC2_BYTEM1_bm (1<<1) /* Byte Mode bit 1 mask. */ -#define TC2_BYTEM1_bp 1 /* Byte Mode bit 1 position. */ - -/* TC2.INTCTRLA bit masks and bit positions */ -#define TC2_HUNFINTLVL_gm 0x0C /* High Byte Underflow Interrupt Level group mask. */ -#define TC2_HUNFINTLVL_gp 2 /* High Byte Underflow Interrupt Level group position. */ -#define TC2_HUNFINTLVL0_bm (1<<2) /* High Byte Underflow Interrupt Level bit 0 mask. */ -#define TC2_HUNFINTLVL0_bp 2 /* High Byte Underflow Interrupt Level bit 0 position. */ -#define TC2_HUNFINTLVL1_bm (1<<3) /* High Byte Underflow Interrupt Level bit 1 mask. */ -#define TC2_HUNFINTLVL1_bp 3 /* High Byte Underflow Interrupt Level bit 1 position. */ - -#define TC2_LUNFINTLVL_gm 0x03 /* Low Byte Underflow interrupt level group mask. */ -#define TC2_LUNFINTLVL_gp 0 /* Low Byte Underflow interrupt level group position. */ -#define TC2_LUNFINTLVL0_bm (1<<0) /* Low Byte Underflow interrupt level bit 0 mask. */ -#define TC2_LUNFINTLVL0_bp 0 /* Low Byte Underflow interrupt level bit 0 position. */ -#define TC2_LUNFINTLVL1_bm (1<<1) /* Low Byte Underflow interrupt level bit 1 mask. */ -#define TC2_LUNFINTLVL1_bp 1 /* Low Byte Underflow interrupt level bit 1 position. */ - -/* TC2.INTCTRLB bit masks and bit positions */ -#define TC2_LCMPDINTLVL_gm 0xC0 /* Low Byte Compare D Interrupt Level group mask. */ -#define TC2_LCMPDINTLVL_gp 6 /* Low Byte Compare D Interrupt Level group position. */ -#define TC2_LCMPDINTLVL0_bm (1<<6) /* Low Byte Compare D Interrupt Level bit 0 mask. */ -#define TC2_LCMPDINTLVL0_bp 6 /* Low Byte Compare D Interrupt Level bit 0 position. */ -#define TC2_LCMPDINTLVL1_bm (1<<7) /* Low Byte Compare D Interrupt Level bit 1 mask. */ -#define TC2_LCMPDINTLVL1_bp 7 /* Low Byte Compare D Interrupt Level bit 1 position. */ - -#define TC2_LCMPCINTLVL_gm 0x30 /* Low Byte Compare C Interrupt Level group mask. */ -#define TC2_LCMPCINTLVL_gp 4 /* Low Byte Compare C Interrupt Level group position. */ -#define TC2_LCMPCINTLVL0_bm (1<<4) /* Low Byte Compare C Interrupt Level bit 0 mask. */ -#define TC2_LCMPCINTLVL0_bp 4 /* Low Byte Compare C Interrupt Level bit 0 position. */ -#define TC2_LCMPCINTLVL1_bm (1<<5) /* Low Byte Compare C Interrupt Level bit 1 mask. */ -#define TC2_LCMPCINTLVL1_bp 5 /* Low Byte Compare C Interrupt Level bit 1 position. */ - -#define TC2_LCMPBINTLVL_gm 0x0C /* Low Byte Compare B Interrupt Level group mask. */ -#define TC2_LCMPBINTLVL_gp 2 /* Low Byte Compare B Interrupt Level group position. */ -#define TC2_LCMPBINTLVL0_bm (1<<2) /* Low Byte Compare B Interrupt Level bit 0 mask. */ -#define TC2_LCMPBINTLVL0_bp 2 /* Low Byte Compare B Interrupt Level bit 0 position. */ -#define TC2_LCMPBINTLVL1_bm (1<<3) /* Low Byte Compare B Interrupt Level bit 1 mask. */ -#define TC2_LCMPBINTLVL1_bp 3 /* Low Byte Compare B Interrupt Level bit 1 position. */ - -#define TC2_LCMPAINTLVL_gm 0x03 /* Low Byte Compare A Interrupt Level group mask. */ -#define TC2_LCMPAINTLVL_gp 0 /* Low Byte Compare A Interrupt Level group position. */ -#define TC2_LCMPAINTLVL0_bm (1<<0) /* Low Byte Compare A Interrupt Level bit 0 mask. */ -#define TC2_LCMPAINTLVL0_bp 0 /* Low Byte Compare A Interrupt Level bit 0 position. */ -#define TC2_LCMPAINTLVL1_bm (1<<1) /* Low Byte Compare A Interrupt Level bit 1 mask. */ -#define TC2_LCMPAINTLVL1_bp 1 /* Low Byte Compare A Interrupt Level bit 1 position. */ - -/* TC2.CTRLF bit masks and bit positions */ -#define TC2_CMD_gm 0x0C /* Command group mask. */ -#define TC2_CMD_gp 2 /* Command group position. */ -#define TC2_CMD0_bm (1<<2) /* Command bit 0 mask. */ -#define TC2_CMD0_bp 2 /* Command bit 0 position. */ -#define TC2_CMD1_bm (1<<3) /* Command bit 1 mask. */ -#define TC2_CMD1_bp 3 /* Command bit 1 position. */ - -#define TC2_CMDEN_gm 0x03 /* Command Enable group mask. */ -#define TC2_CMDEN_gp 0 /* Command Enable group position. */ -#define TC2_CMDEN0_bm (1<<0) /* Command Enable bit 0 mask. */ -#define TC2_CMDEN0_bp 0 /* Command Enable bit 0 position. */ -#define TC2_CMDEN1_bm (1<<1) /* Command Enable bit 1 mask. */ -#define TC2_CMDEN1_bp 1 /* Command Enable bit 1 position. */ - -/* TC2.INTFLAGS bit masks and bit positions */ -#define TC2_LCMPDIF_bm 0x80 /* Low Byte Compare D Interrupt Flag bit mask. */ -#define TC2_LCMPDIF_bp 7 /* Low Byte Compare D Interrupt Flag bit position. */ - -#define TC2_LCMPCIF_bm 0x40 /* Low Byte Compare C Interrupt Flag bit mask. */ -#define TC2_LCMPCIF_bp 6 /* Low Byte Compare C Interrupt Flag bit position. */ - -#define TC2_LCMPBIF_bm 0x20 /* Low Byte Compare B Interrupt Flag bit mask. */ -#define TC2_LCMPBIF_bp 5 /* Low Byte Compare B Interrupt Flag bit position. */ - -#define TC2_LCMPAIF_bm 0x10 /* Low Byte Compare A Interrupt Flag bit mask. */ -#define TC2_LCMPAIF_bp 4 /* Low Byte Compare A Interrupt Flag bit position. */ - -#define TC2_HUNFIF_bm 0x02 /* High Byte Underflow Interrupt Flag bit mask. */ -#define TC2_HUNFIF_bp 1 /* High Byte Underflow Interrupt Flag bit position. */ - -#define TC2_LUNFIF_bm 0x01 /* Low Byte Underflow Interrupt Flag bit mask. */ -#define TC2_LUNFIF_bp 0 /* Low Byte Underflow Interrupt Flag bit position. */ - -/* AWEX - Timer/Counter Advanced Waveform Extension */ -/* AWEX.CTRL bit masks and bit positions */ -#define AWEX_PGM_bm 0x20 /* Pattern Generation Mode bit mask. */ -#define AWEX_PGM_bp 5 /* Pattern Generation Mode bit position. */ - -#define AWEX_CWCM_bm 0x10 /* Common Waveform Channel Mode bit mask. */ -#define AWEX_CWCM_bp 4 /* Common Waveform Channel Mode bit position. */ - -#define AWEX_DTICCDEN_bm 0x08 /* Dead Time Insertion Compare Channel D Enable bit mask. */ -#define AWEX_DTICCDEN_bp 3 /* Dead Time Insertion Compare Channel D Enable bit position. */ - -#define AWEX_DTICCCEN_bm 0x04 /* Dead Time Insertion Compare Channel C Enable bit mask. */ -#define AWEX_DTICCCEN_bp 2 /* Dead Time Insertion Compare Channel C Enable bit position. */ - -#define AWEX_DTICCBEN_bm 0x02 /* Dead Time Insertion Compare Channel B Enable bit mask. */ -#define AWEX_DTICCBEN_bp 1 /* Dead Time Insertion Compare Channel B Enable bit position. */ - -#define AWEX_DTICCAEN_bm 0x01 /* Dead Time Insertion Compare Channel A Enable bit mask. */ -#define AWEX_DTICCAEN_bp 0 /* Dead Time Insertion Compare Channel A Enable bit position. */ - -/* AWEX.FDCTRL bit masks and bit positions */ -#define AWEX_FDDBD_bm 0x10 /* Fault Detect on Disable Break Disable bit mask. */ -#define AWEX_FDDBD_bp 4 /* Fault Detect on Disable Break Disable bit position. */ - -#define AWEX_FDMODE_bm 0x04 /* Fault Detect Mode bit mask. */ -#define AWEX_FDMODE_bp 2 /* Fault Detect Mode bit position. */ - -#define AWEX_FDACT_gm 0x03 /* Fault Detect Action group mask. */ -#define AWEX_FDACT_gp 0 /* Fault Detect Action group position. */ -#define AWEX_FDACT0_bm (1<<0) /* Fault Detect Action bit 0 mask. */ -#define AWEX_FDACT0_bp 0 /* Fault Detect Action bit 0 position. */ -#define AWEX_FDACT1_bm (1<<1) /* Fault Detect Action bit 1 mask. */ -#define AWEX_FDACT1_bp 1 /* Fault Detect Action bit 1 position. */ - -/* AWEX.STATUS bit masks and bit positions */ -#define AWEX_FDF_bm 0x04 /* Fault Detect Flag bit mask. */ -#define AWEX_FDF_bp 2 /* Fault Detect Flag bit position. */ - -#define AWEX_DTHSBUFV_bm 0x02 /* Dead Time High Side Buffer Valid bit mask. */ -#define AWEX_DTHSBUFV_bp 1 /* Dead Time High Side Buffer Valid bit position. */ - -#define AWEX_DTLSBUFV_bm 0x01 /* Dead Time Low Side Buffer Valid bit mask. */ -#define AWEX_DTLSBUFV_bp 0 /* Dead Time Low Side Buffer Valid bit position. */ - -/* AWEX.STATUSSET bit masks and bit positions */ -/* AWEX_FDF Predefined. */ -/* AWEX_FDF Predefined. */ - -/* AWEX_DTHSBUFV Predefined. */ -/* AWEX_DTHSBUFV Predefined. */ - -/* AWEX_DTLSBUFV Predefined. */ -/* AWEX_DTLSBUFV Predefined. */ - -/* HIRES - Timer/Counter High-Resolution Extension */ -/* HIRES.CTRLA bit masks and bit positions */ -#define HIRES_HREN_gm 0x03 /* High Resolution Enable group mask. */ -#define HIRES_HREN_gp 0 /* High Resolution Enable group position. */ -#define HIRES_HREN0_bm (1<<0) /* High Resolution Enable bit 0 mask. */ -#define HIRES_HREN0_bp 0 /* High Resolution Enable bit 0 position. */ -#define HIRES_HREN1_bm (1<<1) /* High Resolution Enable bit 1 mask. */ -#define HIRES_HREN1_bp 1 /* High Resolution Enable bit 1 position. */ - -/* USART - Universal Asynchronous Receiver-Transmitter */ -/* USART.STATUS bit masks and bit positions */ -#define USART_RXCIF_bm 0x80 /* Receive Interrupt Flag bit mask. */ -#define USART_RXCIF_bp 7 /* Receive Interrupt Flag bit position. */ - -#define USART_TXCIF_bm 0x40 /* Transmit Interrupt Flag bit mask. */ -#define USART_TXCIF_bp 6 /* Transmit Interrupt Flag bit position. */ - -#define USART_DREIF_bm 0x20 /* Data Register Empty Flag bit mask. */ -#define USART_DREIF_bp 5 /* Data Register Empty Flag bit position. */ - -#define USART_FERR_bm 0x10 /* Frame Error bit mask. */ -#define USART_FERR_bp 4 /* Frame Error bit position. */ - -#define USART_BUFOVF_bm 0x08 /* Buffer Overflow bit mask. */ -#define USART_BUFOVF_bp 3 /* Buffer Overflow bit position. */ - -#define USART_PERR_bm 0x04 /* Parity Error bit mask. */ -#define USART_PERR_bp 2 /* Parity Error bit position. */ - -#define USART_RXB8_bm 0x01 /* Receive Bit 8 bit mask. */ -#define USART_RXB8_bp 0 /* Receive Bit 8 bit position. */ - -/* USART.CTRLA bit masks and bit positions */ -#define USART_RXCINTLVL_gm 0x30 /* Receive Interrupt Level group mask. */ -#define USART_RXCINTLVL_gp 4 /* Receive Interrupt Level group position. */ -#define USART_RXCINTLVL0_bm (1<<4) /* Receive Interrupt Level bit 0 mask. */ -#define USART_RXCINTLVL0_bp 4 /* Receive Interrupt Level bit 0 position. */ -#define USART_RXCINTLVL1_bm (1<<5) /* Receive Interrupt Level bit 1 mask. */ -#define USART_RXCINTLVL1_bp 5 /* Receive Interrupt Level bit 1 position. */ - -#define USART_TXCINTLVL_gm 0x0C /* Transmit Interrupt Level group mask. */ -#define USART_TXCINTLVL_gp 2 /* Transmit Interrupt Level group position. */ -#define USART_TXCINTLVL0_bm (1<<2) /* Transmit Interrupt Level bit 0 mask. */ -#define USART_TXCINTLVL0_bp 2 /* Transmit Interrupt Level bit 0 position. */ -#define USART_TXCINTLVL1_bm (1<<3) /* Transmit Interrupt Level bit 1 mask. */ -#define USART_TXCINTLVL1_bp 3 /* Transmit Interrupt Level bit 1 position. */ - -#define USART_DREINTLVL_gm 0x03 /* Data Register Empty Interrupt Level group mask. */ -#define USART_DREINTLVL_gp 0 /* Data Register Empty Interrupt Level group position. */ -#define USART_DREINTLVL0_bm (1<<0) /* Data Register Empty Interrupt Level bit 0 mask. */ -#define USART_DREINTLVL0_bp 0 /* Data Register Empty Interrupt Level bit 0 position. */ -#define USART_DREINTLVL1_bm (1<<1) /* Data Register Empty Interrupt Level bit 1 mask. */ -#define USART_DREINTLVL1_bp 1 /* Data Register Empty Interrupt Level bit 1 position. */ - -/* USART.CTRLB bit masks and bit positions */ -#define USART_RXEN_bm 0x10 /* Receiver Enable bit mask. */ -#define USART_RXEN_bp 4 /* Receiver Enable bit position. */ - -#define USART_TXEN_bm 0x08 /* Transmitter Enable bit mask. */ -#define USART_TXEN_bp 3 /* Transmitter Enable bit position. */ - -#define USART_CLK2X_bm 0x04 /* Double transmission speed bit mask. */ -#define USART_CLK2X_bp 2 /* Double transmission speed bit position. */ - -#define USART_MPCM_bm 0x02 /* Multi-processor Communication Mode bit mask. */ -#define USART_MPCM_bp 1 /* Multi-processor Communication Mode bit position. */ - -#define USART_TXB8_bm 0x01 /* Transmit bit 8 bit mask. */ -#define USART_TXB8_bp 0 /* Transmit bit 8 bit position. */ - -/* USART.CTRLC bit masks and bit positions */ -#define USART_CMODE_gm 0xC0 /* Communication Mode group mask. */ -#define USART_CMODE_gp 6 /* Communication Mode group position. */ -#define USART_CMODE0_bm (1<<6) /* Communication Mode bit 0 mask. */ -#define USART_CMODE0_bp 6 /* Communication Mode bit 0 position. */ -#define USART_CMODE1_bm (1<<7) /* Communication Mode bit 1 mask. */ -#define USART_CMODE1_bp 7 /* Communication Mode bit 1 position. */ - -#define USART_PMODE_gm 0x30 /* Parity Mode group mask. */ -#define USART_PMODE_gp 4 /* Parity Mode group position. */ -#define USART_PMODE0_bm (1<<4) /* Parity Mode bit 0 mask. */ -#define USART_PMODE0_bp 4 /* Parity Mode bit 0 position. */ -#define USART_PMODE1_bm (1<<5) /* Parity Mode bit 1 mask. */ -#define USART_PMODE1_bp 5 /* Parity Mode bit 1 position. */ - -#define USART_SBMODE_bm 0x08 /* Stop Bit Mode bit mask. */ -#define USART_SBMODE_bp 3 /* Stop Bit Mode bit position. */ - -#define USART_CHSIZE_gm 0x07 /* Character Size group mask. */ -#define USART_CHSIZE_gp 0 /* Character Size group position. */ -#define USART_CHSIZE0_bm (1<<0) /* Character Size bit 0 mask. */ -#define USART_CHSIZE0_bp 0 /* Character Size bit 0 position. */ -#define USART_CHSIZE1_bm (1<<1) /* Character Size bit 1 mask. */ -#define USART_CHSIZE1_bp 1 /* Character Size bit 1 position. */ -#define USART_CHSIZE2_bm (1<<2) /* Character Size bit 2 mask. */ -#define USART_CHSIZE2_bp 2 /* Character Size bit 2 position. */ - -/* USART.BAUDCTRLA bit masks and bit positions */ -#define USART_BSEL_gm 0xFF /* Baud Rate Selection Bits [7:0] group mask. */ -#define USART_BSEL_gp 0 /* Baud Rate Selection Bits [7:0] group position. */ -#define USART_BSEL0_bm (1<<0) /* Baud Rate Selection Bits [7:0] bit 0 mask. */ -#define USART_BSEL0_bp 0 /* Baud Rate Selection Bits [7:0] bit 0 position. */ -#define USART_BSEL1_bm (1<<1) /* Baud Rate Selection Bits [7:0] bit 1 mask. */ -#define USART_BSEL1_bp 1 /* Baud Rate Selection Bits [7:0] bit 1 position. */ -#define USART_BSEL2_bm (1<<2) /* Baud Rate Selection Bits [7:0] bit 2 mask. */ -#define USART_BSEL2_bp 2 /* Baud Rate Selection Bits [7:0] bit 2 position. */ -#define USART_BSEL3_bm (1<<3) /* Baud Rate Selection Bits [7:0] bit 3 mask. */ -#define USART_BSEL3_bp 3 /* Baud Rate Selection Bits [7:0] bit 3 position. */ -#define USART_BSEL4_bm (1<<4) /* Baud Rate Selection Bits [7:0] bit 4 mask. */ -#define USART_BSEL4_bp 4 /* Baud Rate Selection Bits [7:0] bit 4 position. */ -#define USART_BSEL5_bm (1<<5) /* Baud Rate Selection Bits [7:0] bit 5 mask. */ -#define USART_BSEL5_bp 5 /* Baud Rate Selection Bits [7:0] bit 5 position. */ -#define USART_BSEL6_bm (1<<6) /* Baud Rate Selection Bits [7:0] bit 6 mask. */ -#define USART_BSEL6_bp 6 /* Baud Rate Selection Bits [7:0] bit 6 position. */ -#define USART_BSEL7_bm (1<<7) /* Baud Rate Selection Bits [7:0] bit 7 mask. */ -#define USART_BSEL7_bp 7 /* Baud Rate Selection Bits [7:0] bit 7 position. */ - -/* USART.BAUDCTRLB bit masks and bit positions */ -#define USART_BSCALE_gm 0xF0 /* Baud Rate Scale group mask. */ -#define USART_BSCALE_gp 4 /* Baud Rate Scale group position. */ -#define USART_BSCALE0_bm (1<<4) /* Baud Rate Scale bit 0 mask. */ -#define USART_BSCALE0_bp 4 /* Baud Rate Scale bit 0 position. */ -#define USART_BSCALE1_bm (1<<5) /* Baud Rate Scale bit 1 mask. */ -#define USART_BSCALE1_bp 5 /* Baud Rate Scale bit 1 position. */ -#define USART_BSCALE2_bm (1<<6) /* Baud Rate Scale bit 2 mask. */ -#define USART_BSCALE2_bp 6 /* Baud Rate Scale bit 2 position. */ -#define USART_BSCALE3_bm (1<<7) /* Baud Rate Scale bit 3 mask. */ -#define USART_BSCALE3_bp 7 /* Baud Rate Scale bit 3 position. */ - -/* USART_BSEL Predefined. */ -/* USART_BSEL Predefined. */ - -/* SPI - Serial Peripheral Interface */ -/* SPI.CTRL bit masks and bit positions */ -#define SPI_CLK2X_bm 0x80 /* Enable Double Speed bit mask. */ -#define SPI_CLK2X_bp 7 /* Enable Double Speed bit position. */ - -#define SPI_ENABLE_bm 0x40 /* Enable Module bit mask. */ -#define SPI_ENABLE_bp 6 /* Enable Module bit position. */ - -#define SPI_DORD_bm 0x20 /* Data Order Setting bit mask. */ -#define SPI_DORD_bp 5 /* Data Order Setting bit position. */ - -#define SPI_MASTER_bm 0x10 /* Master Operation Enable bit mask. */ -#define SPI_MASTER_bp 4 /* Master Operation Enable bit position. */ - -#define SPI_MODE_gm 0x0C /* SPI Mode group mask. */ -#define SPI_MODE_gp 2 /* SPI Mode group position. */ -#define SPI_MODE0_bm (1<<2) /* SPI Mode bit 0 mask. */ -#define SPI_MODE0_bp 2 /* SPI Mode bit 0 position. */ -#define SPI_MODE1_bm (1<<3) /* SPI Mode bit 1 mask. */ -#define SPI_MODE1_bp 3 /* SPI Mode bit 1 position. */ - -#define SPI_PRESCALER_gm 0x03 /* Prescaler group mask. */ -#define SPI_PRESCALER_gp 0 /* Prescaler group position. */ -#define SPI_PRESCALER0_bm (1<<0) /* Prescaler bit 0 mask. */ -#define SPI_PRESCALER0_bp 0 /* Prescaler bit 0 position. */ -#define SPI_PRESCALER1_bm (1<<1) /* Prescaler bit 1 mask. */ -#define SPI_PRESCALER1_bp 1 /* Prescaler bit 1 position. */ - -/* SPI.INTCTRL bit masks and bit positions */ -#define SPI_INTLVL_gm 0x03 /* Interrupt level group mask. */ -#define SPI_INTLVL_gp 0 /* Interrupt level group position. */ -#define SPI_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */ -#define SPI_INTLVL0_bp 0 /* Interrupt level bit 0 position. */ -#define SPI_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */ -#define SPI_INTLVL1_bp 1 /* Interrupt level bit 1 position. */ - -/* SPI.STATUS bit masks and bit positions */ -#define SPI_IF_bm 0x80 /* Interrupt Flag bit mask. */ -#define SPI_IF_bp 7 /* Interrupt Flag bit position. */ - -#define SPI_WRCOL_bm 0x40 /* Write Collision bit mask. */ -#define SPI_WRCOL_bp 6 /* Write Collision bit position. */ - -/* IRCOM - IR Communication Module */ -/* IRCOM.CTRL bit masks and bit positions */ -#define IRCOM_EVSEL_gm 0x0F /* Event Channel Select group mask. */ -#define IRCOM_EVSEL_gp 0 /* Event Channel Select group position. */ -#define IRCOM_EVSEL0_bm (1<<0) /* Event Channel Select bit 0 mask. */ -#define IRCOM_EVSEL0_bp 0 /* Event Channel Select bit 0 position. */ -#define IRCOM_EVSEL1_bm (1<<1) /* Event Channel Select bit 1 mask. */ -#define IRCOM_EVSEL1_bp 1 /* Event Channel Select bit 1 position. */ -#define IRCOM_EVSEL2_bm (1<<2) /* Event Channel Select bit 2 mask. */ -#define IRCOM_EVSEL2_bp 2 /* Event Channel Select bit 2 position. */ -#define IRCOM_EVSEL3_bm (1<<3) /* Event Channel Select bit 3 mask. */ -#define IRCOM_EVSEL3_bp 3 /* Event Channel Select bit 3 position. */ - -/* FUSE - Fuses and Lockbits */ -/* NVM_FUSES.FUSEBYTE1 bit masks and bit positions */ -#define NVM_FUSES_WDWP_gm 0xF0 /* Watchdog Window Timeout Period group mask. */ -#define NVM_FUSES_WDWP_gp 4 /* Watchdog Window Timeout Period group position. */ -#define NVM_FUSES_WDWP0_bm (1<<4) /* Watchdog Window Timeout Period bit 0 mask. */ -#define NVM_FUSES_WDWP0_bp 4 /* Watchdog Window Timeout Period bit 0 position. */ -#define NVM_FUSES_WDWP1_bm (1<<5) /* Watchdog Window Timeout Period bit 1 mask. */ -#define NVM_FUSES_WDWP1_bp 5 /* Watchdog Window Timeout Period bit 1 position. */ -#define NVM_FUSES_WDWP2_bm (1<<6) /* Watchdog Window Timeout Period bit 2 mask. */ -#define NVM_FUSES_WDWP2_bp 6 /* Watchdog Window Timeout Period bit 2 position. */ -#define NVM_FUSES_WDWP3_bm (1<<7) /* Watchdog Window Timeout Period bit 3 mask. */ -#define NVM_FUSES_WDWP3_bp 7 /* Watchdog Window Timeout Period bit 3 position. */ - -#define NVM_FUSES_WDP_gm 0x0F /* Watchdog Timeout Period group mask. */ -#define NVM_FUSES_WDP_gp 0 /* Watchdog Timeout Period group position. */ -#define NVM_FUSES_WDP0_bm (1<<0) /* Watchdog Timeout Period bit 0 mask. */ -#define NVM_FUSES_WDP0_bp 0 /* Watchdog Timeout Period bit 0 position. */ -#define NVM_FUSES_WDP1_bm (1<<1) /* Watchdog Timeout Period bit 1 mask. */ -#define NVM_FUSES_WDP1_bp 1 /* Watchdog Timeout Period bit 1 position. */ -#define NVM_FUSES_WDP2_bm (1<<2) /* Watchdog Timeout Period bit 2 mask. */ -#define NVM_FUSES_WDP2_bp 2 /* Watchdog Timeout Period bit 2 position. */ -#define NVM_FUSES_WDP3_bm (1<<3) /* Watchdog Timeout Period bit 3 mask. */ -#define NVM_FUSES_WDP3_bp 3 /* Watchdog Timeout Period bit 3 position. */ - -/* NVM_FUSES.FUSEBYTE2 bit masks and bit positions */ -#define NVM_FUSES_BOOTRST_bm 0x40 /* Boot Loader Section Reset Vector bit mask. */ -#define NVM_FUSES_BOOTRST_bp 6 /* Boot Loader Section Reset Vector bit position. */ - -#define NVM_FUSES_TOSCSEL_bm 0x20 /* Timer Oscillator pin location bit mask. */ -#define NVM_FUSES_TOSCSEL_bp 5 /* Timer Oscillator pin location bit position. */ - -#define NVM_FUSES_BODPD_gm 0x03 /* BOD Operation in Power-Down Mode group mask. */ -#define NVM_FUSES_BODPD_gp 0 /* BOD Operation in Power-Down Mode group position. */ -#define NVM_FUSES_BODPD0_bm (1<<0) /* BOD Operation in Power-Down Mode bit 0 mask. */ -#define NVM_FUSES_BODPD0_bp 0 /* BOD Operation in Power-Down Mode bit 0 position. */ -#define NVM_FUSES_BODPD1_bm (1<<1) /* BOD Operation in Power-Down Mode bit 1 mask. */ -#define NVM_FUSES_BODPD1_bp 1 /* BOD Operation in Power-Down Mode bit 1 position. */ - -/* NVM_FUSES.FUSEBYTE4 bit masks and bit positions */ -#define NVM_FUSES_RSTDISBL_bm 0x10 /* External Reset Disable bit mask. */ -#define NVM_FUSES_RSTDISBL_bp 4 /* External Reset Disable bit position. */ - -#define NVM_FUSES_SUT_gm 0x0C /* Start-up Time group mask. */ -#define NVM_FUSES_SUT_gp 2 /* Start-up Time group position. */ -#define NVM_FUSES_SUT0_bm (1<<2) /* Start-up Time bit 0 mask. */ -#define NVM_FUSES_SUT0_bp 2 /* Start-up Time bit 0 position. */ -#define NVM_FUSES_SUT1_bm (1<<3) /* Start-up Time bit 1 mask. */ -#define NVM_FUSES_SUT1_bp 3 /* Start-up Time bit 1 position. */ - -#define NVM_FUSES_WDLOCK_bm 0x02 /* Watchdog Timer Lock bit mask. */ -#define NVM_FUSES_WDLOCK_bp 1 /* Watchdog Timer Lock bit position. */ - -/* NVM_FUSES.FUSEBYTE5 bit masks and bit positions */ -#define NVM_FUSES_BODACT_gm 0x30 /* BOD Operation in Active Mode group mask. */ -#define NVM_FUSES_BODACT_gp 4 /* BOD Operation in Active Mode group position. */ -#define NVM_FUSES_BODACT0_bm (1<<4) /* BOD Operation in Active Mode bit 0 mask. */ -#define NVM_FUSES_BODACT0_bp 4 /* BOD Operation in Active Mode bit 0 position. */ -#define NVM_FUSES_BODACT1_bm (1<<5) /* BOD Operation in Active Mode bit 1 mask. */ -#define NVM_FUSES_BODACT1_bp 5 /* BOD Operation in Active Mode bit 1 position. */ - -#define NVM_FUSES_EESAVE_bm 0x08 /* Preserve EEPROM Through Chip Erase bit mask. */ -#define NVM_FUSES_EESAVE_bp 3 /* Preserve EEPROM Through Chip Erase bit position. */ - -#define NVM_FUSES_BODLVL_gm 0x07 /* Brownout Detection Voltage Level group mask. */ -#define NVM_FUSES_BODLVL_gp 0 /* Brownout Detection Voltage Level group position. */ -#define NVM_FUSES_BODLVL0_bm (1<<0) /* Brownout Detection Voltage Level bit 0 mask. */ -#define NVM_FUSES_BODLVL0_bp 0 /* Brownout Detection Voltage Level bit 0 position. */ -#define NVM_FUSES_BODLVL1_bm (1<<1) /* Brownout Detection Voltage Level bit 1 mask. */ -#define NVM_FUSES_BODLVL1_bp 1 /* Brownout Detection Voltage Level bit 1 position. */ -#define NVM_FUSES_BODLVL2_bm (1<<2) /* Brownout Detection Voltage Level bit 2 mask. */ -#define NVM_FUSES_BODLVL2_bp 2 /* Brownout Detection Voltage Level bit 2 position. */ - -/* LOCKBIT - Fuses and Lockbits */ -/* NVM_LOCKBITS.LOCKBITS bit masks and bit positions */ -#define NVM_LOCKBITS_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ -#define NVM_LOCKBITS_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ -#define NVM_LOCKBITS_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ -#define NVM_LOCKBITS_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ -#define NVM_LOCKBITS_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ -#define NVM_LOCKBITS_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ - -#define NVM_LOCKBITS_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ -#define NVM_LOCKBITS_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ -#define NVM_LOCKBITS_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ -#define NVM_LOCKBITS_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ -#define NVM_LOCKBITS_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ -#define NVM_LOCKBITS_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ - -#define NVM_LOCKBITS_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ -#define NVM_LOCKBITS_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ -#define NVM_LOCKBITS_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ -#define NVM_LOCKBITS_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ -#define NVM_LOCKBITS_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ -#define NVM_LOCKBITS_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ - -#define NVM_LOCKBITS_LB_gm 0x03 /* Lock Bits group mask. */ -#define NVM_LOCKBITS_LB_gp 0 /* Lock Bits group position. */ -#define NVM_LOCKBITS_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ -#define NVM_LOCKBITS_LB0_bp 0 /* Lock Bits bit 0 position. */ -#define NVM_LOCKBITS_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ -#define NVM_LOCKBITS_LB1_bp 1 /* Lock Bits bit 1 position. */ - - - -// Generic Port Pins - -#define PIN0_bm 0x01 -#define PIN0_bp 0 -#define PIN1_bm 0x02 -#define PIN1_bp 1 -#define PIN2_bm 0x04 -#define PIN2_bp 2 -#define PIN3_bm 0x08 -#define PIN3_bp 3 -#define PIN4_bm 0x10 -#define PIN4_bp 4 -#define PIN5_bm 0x20 -#define PIN5_bp 5 -#define PIN6_bm 0x40 -#define PIN6_bp 6 -#define PIN7_bm 0x80 -#define PIN7_bp 7 - -/* ========== Interrupt Vector Definitions ========== */ -/* Vector 0 is the reset vector */ - -/* OSC interrupt vectors */ -#define OSC_OSCF_vect_num 1 -#define OSC_OSCF_vect _VECTOR(1) /* Oscillator Failure Interrupt (NMI) */ - -/* PORTC interrupt vectors */ -#define PORTC_INT0_vect_num 2 -#define PORTC_INT0_vect _VECTOR(2) /* External Interrupt 0 */ -#define PORTC_INT1_vect_num 3 -#define PORTC_INT1_vect _VECTOR(3) /* External Interrupt 1 */ - -/* PORTR interrupt vectors */ -#define PORTR_INT0_vect_num 4 -#define PORTR_INT0_vect _VECTOR(4) /* External Interrupt 0 */ -#define PORTR_INT1_vect_num 5 -#define PORTR_INT1_vect _VECTOR(5) /* External Interrupt 1 */ - -/* RTC interrupt vectors */ -#define RTC_OVF_vect_num 10 -#define RTC_OVF_vect _VECTOR(10) /* Overflow Interrupt */ -#define RTC_COMP_vect_num 11 -#define RTC_COMP_vect _VECTOR(11) /* Compare Interrupt */ - -/* TWIC interrupt vectors */ -#define TWIC_TWIS_vect_num 12 -#define TWIC_TWIS_vect _VECTOR(12) /* TWI Slave Interrupt */ -#define TWIC_TWIM_vect_num 13 -#define TWIC_TWIM_vect _VECTOR(13) /* TWI Master Interrupt */ - -/* TCC0 interrupt vectors */ -#define TCC0_OVF_vect_num 14 -#define TCC0_OVF_vect _VECTOR(14) /* Overflow Interrupt */ - -/* TCC2 interrupt vectors */ -#define TCC2_LUNF_vect_num 14 -#define TCC2_LUNF_vect _VECTOR(14) /* Low Byte Underflow Interrupt */ - -/* TCC0 interrupt vectors */ -#define TCC0_ERR_vect_num 15 -#define TCC0_ERR_vect _VECTOR(15) /* Error Interrupt */ - -/* TCC2 interrupt vectors */ -#define TCC2_HUNF_vect_num 15 -#define TCC2_HUNF_vect _VECTOR(15) /* High Byte Underflow Interrupt */ - -/* TCC0 interrupt vectors */ -#define TCC0_CCA_vect_num 16 -#define TCC0_CCA_vect _VECTOR(16) /* Compare or Capture A Interrupt */ - -/* TCC2 interrupt vectors */ -#define TCC2_LCMPA_vect_num 16 -#define TCC2_LCMPA_vect _VECTOR(16) /* Low Byte Compare A Interrupt */ - -/* TCC0 interrupt vectors */ -#define TCC0_CCB_vect_num 17 -#define TCC0_CCB_vect _VECTOR(17) /* Compare or Capture B Interrupt */ - -/* TCC2 interrupt vectors */ -#define TCC2_LCMPB_vect_num 17 -#define TCC2_LCMPB_vect _VECTOR(17) /* Low Byte Compare B Interrupt */ - -/* TCC0 interrupt vectors */ -#define TCC0_CCC_vect_num 18 -#define TCC0_CCC_vect _VECTOR(18) /* Compare or Capture C Interrupt */ - -/* TCC2 interrupt vectors */ -#define TCC2_LCMPC_vect_num 18 -#define TCC2_LCMPC_vect _VECTOR(18) /* Low Byte Compare C Interrupt */ - -/* TCC0 interrupt vectors */ -#define TCC0_CCD_vect_num 19 -#define TCC0_CCD_vect _VECTOR(19) /* Compare or Capture D Interrupt */ - -/* TCC2 interrupt vectors */ -#define TCC2_LCMPD_vect_num 19 -#define TCC2_LCMPD_vect _VECTOR(19) /* Low Byte Compare D Interrupt */ - -/* TCC1 interrupt vectors */ -#define TCC1_OVF_vect_num 20 -#define TCC1_OVF_vect _VECTOR(20) /* Overflow Interrupt */ -#define TCC1_ERR_vect_num 21 -#define TCC1_ERR_vect _VECTOR(21) /* Error Interrupt */ -#define TCC1_CCA_vect_num 22 -#define TCC1_CCA_vect _VECTOR(22) /* Compare or Capture A Interrupt */ -#define TCC1_CCB_vect_num 23 -#define TCC1_CCB_vect _VECTOR(23) /* Compare or Capture B Interrupt */ - -/* SPIC interrupt vectors */ -#define SPIC_INT_vect_num 24 -#define SPIC_INT_vect _VECTOR(24) /* SPI Interrupt */ - -/* USARTC0 interrupt vectors */ -#define USARTC0_RXC_vect_num 25 -#define USARTC0_RXC_vect _VECTOR(25) /* Reception Complete Interrupt */ -#define USARTC0_DRE_vect_num 26 -#define USARTC0_DRE_vect _VECTOR(26) /* Data Register Empty Interrupt */ -#define USARTC0_TXC_vect_num 27 -#define USARTC0_TXC_vect _VECTOR(27) /* Transmission Complete Interrupt */ - -/* NVM interrupt vectors */ -#define NVM_EE_vect_num 32 -#define NVM_EE_vect _VECTOR(32) /* EE Interrupt */ -#define NVM_SPM_vect_num 33 -#define NVM_SPM_vect _VECTOR(33) /* SPM Interrupt */ - -/* PORTB interrupt vectors */ -#define PORTB_INT0_vect_num 34 -#define PORTB_INT0_vect _VECTOR(34) /* External Interrupt 0 */ -#define PORTB_INT1_vect_num 35 -#define PORTB_INT1_vect _VECTOR(35) /* External Interrupt 1 */ - -/* PORTE interrupt vectors */ -#define PORTE_INT0_vect_num 43 -#define PORTE_INT0_vect _VECTOR(43) /* External Interrupt 0 */ -#define PORTE_INT1_vect_num 44 -#define PORTE_INT1_vect _VECTOR(44) /* External Interrupt 1 */ - -/* TWIE interrupt vectors */ -#define TWIE_TWIS_vect_num 45 -#define TWIE_TWIS_vect _VECTOR(45) /* TWI Slave Interrupt */ -#define TWIE_TWIM_vect_num 46 -#define TWIE_TWIM_vect _VECTOR(46) /* TWI Master Interrupt */ - -/* TCE0 interrupt vectors */ -#define TCE0_OVF_vect_num 47 -#define TCE0_OVF_vect _VECTOR(47) /* Overflow Interrupt */ -#define TCE0_ERR_vect_num 48 -#define TCE0_ERR_vect _VECTOR(48) /* Error Interrupt */ -#define TCE0_CCA_vect_num 49 -#define TCE0_CCA_vect _VECTOR(49) /* Compare or Capture A Interrupt */ -#define TCE0_CCB_vect_num 50 -#define TCE0_CCB_vect _VECTOR(50) /* Compare or Capture B Interrupt */ -#define TCE0_CCC_vect_num 51 -#define TCE0_CCC_vect _VECTOR(51) /* Compare or Capture C Interrupt */ -#define TCE0_CCD_vect_num 52 -#define TCE0_CCD_vect _VECTOR(52) /* Compare or Capture D Interrupt */ - -/* USARTE0 interrupt vectors */ -#define USARTE0_RXC_vect_num 58 -#define USARTE0_RXC_vect _VECTOR(58) /* Reception Complete Interrupt */ -#define USARTE0_DRE_vect_num 59 -#define USARTE0_DRE_vect _VECTOR(59) /* Data Register Empty Interrupt */ -#define USARTE0_TXC_vect_num 60 -#define USARTE0_TXC_vect _VECTOR(60) /* Transmission Complete Interrupt */ - -/* PORTD interrupt vectors */ -#define PORTD_INT0_vect_num 64 -#define PORTD_INT0_vect _VECTOR(64) /* External Interrupt 0 */ -#define PORTD_INT1_vect_num 65 -#define PORTD_INT1_vect _VECTOR(65) /* External Interrupt 1 */ - -/* PORTA interrupt vectors */ -#define PORTA_INT0_vect_num 66 -#define PORTA_INT0_vect _VECTOR(66) /* External Interrupt 0 */ -#define PORTA_INT1_vect_num 67 -#define PORTA_INT1_vect _VECTOR(67) /* External Interrupt 1 */ - -/* ACA interrupt vectors */ -#define ACA_AC0_vect_num 68 -#define ACA_AC0_vect _VECTOR(68) /* AC0 Interrupt */ -#define ACA_AC1_vect_num 69 -#define ACA_AC1_vect _VECTOR(69) /* AC1 Interrupt */ -#define ACA_ACW_vect_num 70 -#define ACA_ACW_vect _VECTOR(70) /* ACW Window Mode Interrupt */ - -/* ADCA interrupt vectors */ -#define ADCA_CH0_vect_num 71 -#define ADCA_CH0_vect _VECTOR(71) /* Interrupt 0 */ - -/* TCD0 interrupt vectors */ -#define TCD0_OVF_vect_num 77 -#define TCD0_OVF_vect _VECTOR(77) /* Overflow Interrupt */ - -/* TCD2 interrupt vectors */ -#define TCD2_LUNF_vect_num 77 -#define TCD2_LUNF_vect _VECTOR(77) /* Low Byte Underflow Interrupt */ - -/* TCD0 interrupt vectors */ -#define TCD0_ERR_vect_num 78 -#define TCD0_ERR_vect _VECTOR(78) /* Error Interrupt */ - -/* TCD2 interrupt vectors */ -#define TCD2_HUNF_vect_num 78 -#define TCD2_HUNF_vect _VECTOR(78) /* High Byte Underflow Interrupt */ - -/* TCD0 interrupt vectors */ -#define TCD0_CCA_vect_num 79 -#define TCD0_CCA_vect _VECTOR(79) /* Compare or Capture A Interrupt */ - -/* TCD2 interrupt vectors */ -#define TCD2_LCMPA_vect_num 79 -#define TCD2_LCMPA_vect _VECTOR(79) /* Low Byte Compare A Interrupt */ - -/* TCD0 interrupt vectors */ -#define TCD0_CCB_vect_num 80 -#define TCD0_CCB_vect _VECTOR(80) /* Compare or Capture B Interrupt */ - -/* TCD2 interrupt vectors */ -#define TCD2_LCMPB_vect_num 80 -#define TCD2_LCMPB_vect _VECTOR(80) /* Low Byte Compare B Interrupt */ - -/* TCD0 interrupt vectors */ -#define TCD0_CCC_vect_num 81 -#define TCD0_CCC_vect _VECTOR(81) /* Compare or Capture C Interrupt */ - -/* TCD2 interrupt vectors */ -#define TCD2_LCMPC_vect_num 81 -#define TCD2_LCMPC_vect _VECTOR(81) /* Low Byte Compare C Interrupt */ - -/* TCD0 interrupt vectors */ -#define TCD0_CCD_vect_num 82 -#define TCD0_CCD_vect _VECTOR(82) /* Compare or Capture D Interrupt */ - -/* TCD2 interrupt vectors */ -#define TCD2_LCMPD_vect_num 82 -#define TCD2_LCMPD_vect _VECTOR(82) /* Low Byte Compare D Interrupt */ - -/* SPID interrupt vectors */ -#define SPID_INT_vect_num 87 -#define SPID_INT_vect _VECTOR(87) /* SPI Interrupt */ - -/* USARTD0 interrupt vectors */ -#define USARTD0_RXC_vect_num 88 -#define USARTD0_RXC_vect _VECTOR(88) /* Reception Complete Interrupt */ -#define USARTD0_DRE_vect_num 89 -#define USARTD0_DRE_vect _VECTOR(89) /* Data Register Empty Interrupt */ -#define USARTD0_TXC_vect_num 90 -#define USARTD0_TXC_vect _VECTOR(90) /* Transmission Complete Interrupt */ - -#define _VECTOR_SIZE 4 /* Size of individual vector. */ -#define _VECTORS_SIZE (91 * _VECTOR_SIZE) - - -/* ========== Constants ========== */ - -#define PROGMEM_START (0x0000) -#define PROGMEM_SIZE (69632) -#define PROGMEM_END (PROGMEM_START + PROGMEM_SIZE - 1) - -#define APP_SECTION_START (0x0000) -#define APP_SECTION_SIZE (65536) -#define APP_SECTION_PAGE_SIZE (256) -#define APP_SECTION_END (APP_SECTION_START + APP_SECTION_SIZE - 1) - -#define APPTABLE_SECTION_START (0xF000) -#define APPTABLE_SECTION_SIZE (4096) -#define APPTABLE_SECTION_PAGE_SIZE (256) -#define APPTABLE_SECTION_END (APPTABLE_SECTION_START + APPTABLE_SECTION_SIZE - 1) - -#define BOOT_SECTION_START (0x10000) -#define BOOT_SECTION_SIZE (4096) -#define BOOT_SECTION_PAGE_SIZE (256) -#define BOOT_SECTION_END (BOOT_SECTION_START + BOOT_SECTION_SIZE - 1) - -#define DATAMEM_START (0x0000) -#define DATAMEM_SIZE (12288) -#define DATAMEM_END (DATAMEM_START + DATAMEM_SIZE - 1) - -#define IO_START (0x0000) -#define IO_SIZE (4096) -#define IO_PAGE_SIZE (0) -#define IO_END (IO_START + IO_SIZE - 1) - -#define MAPPED_EEPROM_START (0x1000) -#define MAPPED_EEPROM_SIZE (2048) -#define MAPPED_EEPROM_PAGE_SIZE (0) -#define MAPPED_EEPROM_END (MAPPED_EEPROM_START + MAPPED_EEPROM_SIZE - 1) - -#define INTERNAL_SRAM_START (0x2000) -#define INTERNAL_SRAM_SIZE (4096) -#define INTERNAL_SRAM_PAGE_SIZE (0) -#define INTERNAL_SRAM_END (INTERNAL_SRAM_START + INTERNAL_SRAM_SIZE - 1) - -#define EEPROM_START (0x0000) -#define EEPROM_SIZE (2048) -#define EEPROM_PAGE_SIZE (32) -#define EEPROM_END (EEPROM_START + EEPROM_SIZE - 1) - -#define SIGNATURES_START (0x0000) -#define SIGNATURES_SIZE (3) -#define SIGNATURES_PAGE_SIZE (0) -#define SIGNATURES_END (SIGNATURES_START + SIGNATURES_SIZE - 1) - -#define FUSES_START (0x0000) -#define FUSES_SIZE (6) -#define FUSES_PAGE_SIZE (0) -#define FUSES_END (FUSES_START + FUSES_SIZE - 1) - -#define LOCKBITS_START (0x0000) -#define LOCKBITS_SIZE (1) -#define LOCKBITS_PAGE_SIZE (0) -#define LOCKBITS_END (LOCKBITS_START + LOCKBITS_SIZE - 1) - -#define USER_SIGNATURES_START (0x0000) -#define USER_SIGNATURES_SIZE (256) -#define USER_SIGNATURES_PAGE_SIZE (256) -#define USER_SIGNATURES_END (USER_SIGNATURES_START + USER_SIGNATURES_SIZE - 1) - -#define PROD_SIGNATURES_START (0x0000) -#define PROD_SIGNATURES_SIZE (64) -#define PROD_SIGNATURES_PAGE_SIZE (256) -#define PROD_SIGNATURES_END (PROD_SIGNATURES_START + PROD_SIGNATURES_SIZE - 1) - -#define FLASHSTART PROGMEM_START -#define FLASHEND PROGMEM_END -#define SPM_PAGESIZE 256 -#define RAMSTART INTERNAL_SRAM_START -#define RAMSIZE INTERNAL_SRAM_SIZE -#define RAMEND INTERNAL_SRAM_END -#define E2END EEPROM_END -#define E2PAGESIZE EEPROM_PAGE_SIZE - - -/* ========== Fuses ========== */ -#define FUSE_MEMORY_SIZE 6 - -/* Fuse Byte 0 Reserved */ - -/* Fuse Byte 1 */ -#define FUSE_WDP0 (unsigned char)~_BV(0) /* Watchdog Timeout Period Bit 0 */ -#define FUSE_WDP1 (unsigned char)~_BV(1) /* Watchdog Timeout Period Bit 1 */ -#define FUSE_WDP2 (unsigned char)~_BV(2) /* Watchdog Timeout Period Bit 2 */ -#define FUSE_WDP3 (unsigned char)~_BV(3) /* Watchdog Timeout Period Bit 3 */ -#define FUSE_WDWP0 (unsigned char)~_BV(4) /* Watchdog Window Timeout Period Bit 0 */ -#define FUSE_WDWP1 (unsigned char)~_BV(5) /* Watchdog Window Timeout Period Bit 1 */ -#define FUSE_WDWP2 (unsigned char)~_BV(6) /* Watchdog Window Timeout Period Bit 2 */ -#define FUSE_WDWP3 (unsigned char)~_BV(7) /* Watchdog Window Timeout Period Bit 3 */ -#define FUSE1_DEFAULT (0xFF) - -/* Fuse Byte 2 */ -#define FUSE_BODPD0 (unsigned char)~_BV(0) /* BOD Operation in Power-Down Mode Bit 0 */ -#define FUSE_BODPD1 (unsigned char)~_BV(1) /* BOD Operation in Power-Down Mode Bit 1 */ -#define FUSE_TOSCSEL (unsigned char)~_BV(5) /* Timer Oscillator pin location */ -#define FUSE_BOOTRST (unsigned char)~_BV(6) /* Boot Loader Section Reset Vector */ -#define FUSE2_DEFAULT (0xFF) - -/* Fuse Byte 3 Reserved */ - -/* Fuse Byte 4 */ -#define FUSE_WDLOCK (unsigned char)~_BV(1) /* Watchdog Timer Lock */ -#define FUSE_SUT0 (unsigned char)~_BV(2) /* Start-up Time Bit 0 */ -#define FUSE_SUT1 (unsigned char)~_BV(3) /* Start-up Time Bit 1 */ -#define FUSE_RSTDISBL (unsigned char)~_BV(4) /* External Reset Disable */ -#define FUSE4_DEFAULT (0xFF) - -/* Fuse Byte 5 */ -#define FUSE_BODLVL0 (unsigned char)~_BV(0) /* Brownout Detection Voltage Level Bit 0 */ -#define FUSE_BODLVL1 (unsigned char)~_BV(1) /* Brownout Detection Voltage Level Bit 1 */ -#define FUSE_BODLVL2 (unsigned char)~_BV(2) /* Brownout Detection Voltage Level Bit 2 */ -#define FUSE_EESAVE (unsigned char)~_BV(3) /* Preserve EEPROM Through Chip Erase */ -#define FUSE_BODACT0 (unsigned char)~_BV(4) /* BOD Operation in Active Mode Bit 0 */ -#define FUSE_BODACT1 (unsigned char)~_BV(5) /* BOD Operation in Active Mode Bit 1 */ -#define FUSE5_DEFAULT (0xFF) - -/* ========== Lock Bits ========== */ -#define __LOCK_BITS_EXIST -#define __BOOT_LOCK_APPLICATION_TABLE_BITS_EXIST -#define __BOOT_LOCK_APPLICATION_BITS_EXIST -#define __BOOT_LOCK_BOOT_BITS_EXIST - -/* ========== Signature ========== */ -#define SIGNATURE_0 0x1E -#define SIGNATURE_1 0x96 -#define SIGNATURE_2 0x47 - -/* ========== Power Reduction Condition Definitions ========== */ - -/* PR.PRGEN */ -#define __AVR_HAVE_PRGEN (PR_RTC_bm|PR_EVSYS_bm) -#define __AVR_HAVE_PRGEN_RTC -#define __AVR_HAVE_PRGEN_EVSYS - -/* PR.PRPA */ -#define __AVR_HAVE_PRPA (PR_ADC_bm|PR_AC_bm) -#define __AVR_HAVE_PRPA_ADC -#define __AVR_HAVE_PRPA_AC - -/* PR.PRPC */ -#define __AVR_HAVE_PRPC (PR_TWI_bm|PR_USART0_bm|PR_SPI_bm|PR_HIRES_bm|PR_TC1_bm|PR_TC0_bm) -#define __AVR_HAVE_PRPC_TWI -#define __AVR_HAVE_PRPC_USART0 -#define __AVR_HAVE_PRPC_SPI -#define __AVR_HAVE_PRPC_HIRES -#define __AVR_HAVE_PRPC_TC1 -#define __AVR_HAVE_PRPC_TC0 - -/* PR.PRPD */ -#define __AVR_HAVE_PRPD (PR_USART0_bm|PR_SPI_bm|PR_TC0_bm) -#define __AVR_HAVE_PRPD_USART0 -#define __AVR_HAVE_PRPD_SPI -#define __AVR_HAVE_PRPD_TC0 - -/* PR.PRPE */ -#define __AVR_HAVE_PRPE (PR_TWI_bm|PR_USART0_bm|PR_TC0_bm) -#define __AVR_HAVE_PRPE_TWI -#define __AVR_HAVE_PRPE_USART0 -#define __AVR_HAVE_PRPE_TC0 - -/* PR.PRPF */ -#define __AVR_HAVE_PRPF (PR_USART0_bm|PR_TC0_bm) -#define __AVR_HAVE_PRPF_USART0 -#define __AVR_HAVE_PRPF_TC0 - - -#endif /* #ifdef _AVR_ATXMEGA64D4_H_INCLUDED */ - diff --git a/arduino/hardware/tools/avr/avr/include/avr/iox8e5.h b/arduino/hardware/tools/avr/avr/include/avr/iox8e5.h deleted file mode 100644 index cfab85d..0000000 --- a/arduino/hardware/tools/avr/avr/include/avr/iox8e5.h +++ /dev/null @@ -1,7699 +0,0 @@ -/***************************************************************************** - * - * Copyright (C) 2015 Atmel Corporation - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * - * * Neither the name of the copyright holders nor the names of - * contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - ****************************************************************************/ - - -#ifndef _AVR_IO_H_ -# error "Include instead of this file." -#endif - -#ifndef _AVR_IOXXX_H_ -# define _AVR_IOXXX_H_ "iox8e5.h" -#else -# error "Attempt to include more than one file." -#endif - -#ifndef _AVR_ATXMEGA8E5_H_INCLUDED -#define _AVR_ATXMEGA8E5_H_INCLUDED - -/* Ungrouped common registers */ -#define GPIOR0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ -#define GPIOR1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ -#define GPIOR2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ -#define GPIOR3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ - -/* Deprecated */ -#define GPIO0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ -#define GPIO1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ -#define GPIO2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ -#define GPIO3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ - -#define CCP _SFR_MEM8(0x0034) /* Configuration Change Protection */ -#define RAMPD _SFR_MEM8(0x0038) /* Ramp D */ -#define RAMPX _SFR_MEM8(0x0039) /* Ramp X */ -#define RAMPY _SFR_MEM8(0x003A) /* Ramp Y */ -#define RAMPZ _SFR_MEM8(0x003B) /* Ramp Z */ -#define EIND _SFR_MEM8(0x003C) /* Extended Indirect Jump */ -#define SPL _SFR_MEM8(0x003D) /* Stack Pointer Low */ -#define SPH _SFR_MEM8(0x003E) /* Stack Pointer High */ -#define SREG _SFR_MEM8(0x003F) /* Status Register */ - -/* C Language Only */ -#if !defined (__ASSEMBLER__) - -#include - -typedef volatile uint8_t register8_t; -typedef volatile uint16_t register16_t; -typedef volatile uint32_t register32_t; - - -#ifdef _WORDREGISTER -#undef _WORDREGISTER -#endif -#define _WORDREGISTER(regname) \ - __extension__ union \ - { \ - register16_t regname; \ - struct \ - { \ - register8_t regname ## L; \ - register8_t regname ## H; \ - }; \ - } - -#ifdef _DWORDREGISTER -#undef _DWORDREGISTER -#endif -#define _DWORDREGISTER(regname) \ - __extension__ union \ - { \ - register32_t regname; \ - struct \ - { \ - register8_t regname ## 0; \ - register8_t regname ## 1; \ - register8_t regname ## 2; \ - register8_t regname ## 3; \ - }; \ - } - - -/* -========================================================================== -IO Module Structures -========================================================================== -*/ - - -/* --------------------------------------------------------------------------- -VPORT - Virtual Ports --------------------------------------------------------------------------- -*/ - -/* Virtual Port */ -typedef struct VPORT_struct -{ - register8_t DIR; /* I/O Port Data Direction */ - register8_t OUT; /* I/O Port Output */ - register8_t IN; /* I/O Port Input */ - register8_t INTFLAGS; /* Interrupt Flag Register */ -} VPORT_t; - - -/* --------------------------------------------------------------------------- -XOCD - On-Chip Debug System --------------------------------------------------------------------------- -*/ - -/* On-Chip Debug System */ -typedef struct OCD_struct -{ - register8_t OCDR0; /* OCD Register 0 */ - register8_t OCDR1; /* OCD Register 1 */ -} OCD_t; - - -/* --------------------------------------------------------------------------- -CPU - CPU --------------------------------------------------------------------------- -*/ - -/* CCP signatures */ -typedef enum CCP_enum -{ - CCP_SPM_gc = (0x9D<<0), /* SPM Instruction Protection */ - CCP_IOREG_gc = (0xD8<<0), /* IO Register Protection */ -} CCP_t; - - -/* --------------------------------------------------------------------------- -CLK - Clock System --------------------------------------------------------------------------- -*/ - -/* Clock System */ -typedef struct CLK_struct -{ - register8_t CTRL; /* Control Register */ - register8_t PSCTRL; /* Prescaler Control Register */ - register8_t LOCK; /* Lock register */ - register8_t RTCCTRL; /* RTC Control Register */ - register8_t reserved_0x04; -} CLK_t; - - -/* Power Reduction */ -typedef struct PR_struct -{ - register8_t PRGEN; /* General Power Reduction */ - register8_t PRPA; /* Power Reduction Port A */ - register8_t reserved_0x02; - register8_t PRPC; /* Power Reduction Port C */ - register8_t PRPD; /* Power Reduction Port D */ - register8_t reserved_0x05; - register8_t reserved_0x06; -} PR_t; - -/* System Clock Selection */ -typedef enum CLK_SCLKSEL_enum -{ - CLK_SCLKSEL_RC2M_gc = (0x00<<0), /* Internal 2 MHz RC Oscillator */ - CLK_SCLKSEL_RC32M_gc = (0x01<<0), /* Internal 32 MHz RC Oscillator */ - CLK_SCLKSEL_RC32K_gc = (0x02<<0), /* Internal 32.768 kHz RC Oscillator */ - CLK_SCLKSEL_XOSC_gc = (0x03<<0), /* External Crystal Oscillator or Clock */ - CLK_SCLKSEL_PLL_gc = (0x04<<0), /* Phase Locked Loop */ - CLK_SCLKSEL_RC8M_gc = (0x05<<0), /* Internal 8 MHz RC Oscillator */ -} CLK_SCLKSEL_t; - -/* Prescaler A Division Factor */ -typedef enum CLK_PSADIV_enum -{ - CLK_PSADIV_1_gc = (0x00<<2), /* Divide by 1 */ - CLK_PSADIV_2_gc = (0x01<<2), /* Divide by 2 */ - CLK_PSADIV_4_gc = (0x03<<2), /* Divide by 4 */ - CLK_PSADIV_8_gc = (0x05<<2), /* Divide by 8 */ - CLK_PSADIV_16_gc = (0x07<<2), /* Divide by 16 */ - CLK_PSADIV_32_gc = (0x09<<2), /* Divide by 32 */ - CLK_PSADIV_64_gc = (0x0B<<2), /* Divide by 64 */ - CLK_PSADIV_128_gc = (0x0D<<2), /* Divide by 128 */ - CLK_PSADIV_256_gc = (0x0F<<2), /* Divide by 256 */ - CLK_PSADIV_512_gc = (0x11<<2), /* Divide by 512 */ - CLK_PSADIV_6_gc = (0x13<<2), /* Divide by 6 */ - CLK_PSADIV_10_gc = (0x15<<2), /* Divide by 10 */ - CLK_PSADIV_12_gc = (0x17<<2), /* Divide by 12 */ - CLK_PSADIV_24_gc = (0x19<<2), /* Divide by 24 */ - CLK_PSADIV_48_gc = (0x1B<<2), /* Divide by 48 */ -} CLK_PSADIV_t; - -/* Prescaler B and C Division Factor */ -typedef enum CLK_PSBCDIV_enum -{ - CLK_PSBCDIV_1_1_gc = (0x00<<0), /* Divide B by 1 and C by 1 */ - CLK_PSBCDIV_1_2_gc = (0x01<<0), /* Divide B by 1 and C by 2 */ - CLK_PSBCDIV_4_1_gc = (0x02<<0), /* Divide B by 4 and C by 1 */ - CLK_PSBCDIV_2_2_gc = (0x03<<0), /* Divide B by 2 and C by 2 */ -} CLK_PSBCDIV_t; - -/* RTC Clock Source */ -typedef enum CLK_RTCSRC_enum -{ - CLK_RTCSRC_ULP_gc = (0x00<<1), /* 1.024 kHz from internal 32kHz ULP */ - CLK_RTCSRC_TOSC_gc = (0x01<<1), /* 1.024 kHz from 32.768 kHz crystal oscillator on TOSC */ - CLK_RTCSRC_RCOSC_gc = (0x02<<1), /* 1.024 kHz from internal 32.768 kHz RC oscillator */ - CLK_RTCSRC_TOSC32_gc = (0x05<<1), /* 32.768 kHz from 32.768 kHz crystal oscillator on TOSC */ - CLK_RTCSRC_RCOSC32_gc = (0x06<<1), /* 32.768 kHz from internal 32.768 kHz RC oscillator */ - CLK_RTCSRC_EXTCLK_gc = (0x07<<1), /* External Clock from TOSC1 */ -} CLK_RTCSRC_t; - - -/* --------------------------------------------------------------------------- -SLEEP - Sleep Controller --------------------------------------------------------------------------- -*/ - -/* Sleep Controller */ -typedef struct SLEEP_struct -{ - register8_t CTRL; /* Control Register */ -} SLEEP_t; - -/* Sleep Mode */ -typedef enum SLEEP_SMODE_enum -{ - SLEEP_SMODE_IDLE_gc = (0x00<<1), /* Idle mode */ - SLEEP_SMODE_PDOWN_gc = (0x02<<1), /* Power-down Mode */ - SLEEP_SMODE_PSAVE_gc = (0x03<<1), /* Power-save Mode */ - SLEEP_SMODE_STDBY_gc = (0x06<<1), /* Standby Mode */ - SLEEP_SMODE_ESTDBY_gc = (0x07<<1), /* Extended Standby Mode */ -} SLEEP_SMODE_t; - - - -#define SLEEP_MODE_IDLE (0x00<<1) -#define SLEEP_MODE_PWR_DOWN (0x02<<1) -#define SLEEP_MODE_PWR_SAVE (0x03<<1) -#define SLEEP_MODE_STANDBY (0x06<<1) -#define SLEEP_MODE_EXT_STANDBY (0x07<<1) -/* --------------------------------------------------------------------------- -OSC - Oscillator --------------------------------------------------------------------------- -*/ - -/* Oscillator */ -typedef struct OSC_struct -{ - register8_t CTRL; /* Control Register */ - register8_t STATUS; /* Status Register */ - register8_t XOSCCTRL; /* External Oscillator Control Register */ - register8_t XOSCFAIL; /* Oscillator Failure Detection Register */ - register8_t RC32KCAL; /* 32.768 kHz Internal Oscillator Calibration Register */ - register8_t PLLCTRL; /* PLL Control Register */ - register8_t DFLLCTRL; /* DFLL Control Register */ - register8_t RC8MCAL; /* Internal 8 MHz RC Oscillator Calibration Register */ -} OSC_t; - -/* Oscillator Frequency Range */ -typedef enum OSC_FRQRANGE_enum -{ - OSC_FRQRANGE_04TO2_gc = (0x00<<6), /* 0.4 - 2 MHz */ - OSC_FRQRANGE_2TO9_gc = (0x01<<6), /* 2 - 9 MHz */ - OSC_FRQRANGE_9TO12_gc = (0x02<<6), /* 9 - 12 MHz */ - OSC_FRQRANGE_12TO16_gc = (0x03<<6), /* 12 - 16 MHz */ -} OSC_FRQRANGE_t; - -/* External Oscillator Selection and Startup Time */ -typedef enum OSC_XOSCSEL_enum -{ - OSC_XOSCSEL_EXTCLK_gc = (0x00<<0), /* External Clock on port R1 - 6 CLK */ - OSC_XOSCSEL_32KHz_gc = (0x02<<0), /* 32.768 kHz TOSC - 32K CLK */ - OSC_XOSCSEL_XTAL_256CLK_gc = (0x03<<0), /* 0.4-16 MHz XTAL - 256 CLK */ - OSC_XOSCSEL_XTAL_1KCLK_gc = (0x07<<0), /* 0.4-16 MHz XTAL - 1K CLK */ - OSC_XOSCSEL_XTAL_16KCLK_gc = (0x0B<<0), /* 0.4-16 MHz XTAL - 16K CLK */ - OSC_XOSCSEL_EXTCLK_C4_gc = (0x14<<0), /* External Clock on port C4 - 6 CLK */ -} OSC_XOSCSEL_t; - -/* PLL Clock Source */ -typedef enum OSC_PLLSRC_enum -{ - OSC_PLLSRC_RC2M_gc = (0x00<<6), /* Internal 2 MHz RC Oscillator */ - OSC_PLLSRC_RC8M_gc = (0x01<<6), /* Internal 8 MHz RC Oscillator */ - OSC_PLLSRC_RC32M_gc = (0x02<<6), /* Internal 32 MHz RC Oscillator */ - OSC_PLLSRC_XOSC_gc = (0x03<<6), /* External Oscillator */ -} OSC_PLLSRC_t; - -/* 32 MHz DFLL Calibration Reference */ -typedef enum OSC_RC32MCREF_enum -{ - OSC_RC32MCREF_RC32K_gc = (0x00<<1), /* Internal 32.768 kHz RC Oscillator */ - OSC_RC32MCREF_XOSC32K_gc = (0x01<<1), /* External 32.768 kHz Crystal Oscillator */ -} OSC_RC32MCREF_t; - - -/* --------------------------------------------------------------------------- -DFLL - DFLL --------------------------------------------------------------------------- -*/ - -/* DFLL */ -typedef struct DFLL_struct -{ - register8_t CTRL; /* Control Register */ - register8_t reserved_0x01; - register8_t CALA; /* Calibration Register A */ - register8_t CALB; /* Calibration Register B */ - register8_t COMP0; /* Oscillator Compare Register 0 */ - register8_t COMP1; /* Oscillator Compare Register 1 */ - register8_t COMP2; /* Oscillator Compare Register 2 */ - register8_t reserved_0x07; -} DFLL_t; - - -/* --------------------------------------------------------------------------- -RST - Reset --------------------------------------------------------------------------- -*/ - -/* Reset */ -typedef struct RST_struct -{ - register8_t STATUS; /* Status Register */ - register8_t CTRL; /* Control Register */ -} RST_t; - - -/* --------------------------------------------------------------------------- -WDT - Watch-Dog Timer --------------------------------------------------------------------------- -*/ - -/* Watch-Dog Timer */ -typedef struct WDT_struct -{ - register8_t CTRL; /* Control */ - register8_t WINCTRL; /* Windowed Mode Control */ - register8_t STATUS; /* Status */ -} WDT_t; - -/* Period setting */ -typedef enum WDT_PER_enum -{ - WDT_PER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ - WDT_PER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ - WDT_PER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ - WDT_PER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ - WDT_PER_128CLK_gc = (0x04<<2), /* 128 cycles (0.128s @ 3.3V) */ - WDT_PER_256CLK_gc = (0x05<<2), /* 256 cycles (0.256s @ 3.3V) */ - WDT_PER_512CLK_gc = (0x06<<2), /* 512 cycles (0.512s @ 3.3V) */ - WDT_PER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ - WDT_PER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ - WDT_PER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ - WDT_PER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ -} WDT_PER_t; - -/* Closed window period */ -typedef enum WDT_WPER_enum -{ - WDT_WPER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ - WDT_WPER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ - WDT_WPER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ - WDT_WPER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ - WDT_WPER_128CLK_gc = (0x04<<2), /* 128 cycles (0.128s @ 3.3V) */ - WDT_WPER_256CLK_gc = (0x05<<2), /* 256 cycles (0.256s @ 3.3V) */ - WDT_WPER_512CLK_gc = (0x06<<2), /* 512 cycles (0.512s @ 3.3V) */ - WDT_WPER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ - WDT_WPER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ - WDT_WPER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ - WDT_WPER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ -} WDT_WPER_t; - - -/* --------------------------------------------------------------------------- -MCU - MCU Control --------------------------------------------------------------------------- -*/ - -/* MCU Control */ -typedef struct MCU_struct -{ - register8_t DEVID0; /* Device ID byte 0 */ - register8_t DEVID1; /* Device ID byte 1 */ - register8_t DEVID2; /* Device ID byte 2 */ - register8_t REVID; /* Revision ID */ - register8_t reserved_0x04; - register8_t reserved_0x05; - register8_t reserved_0x06; - register8_t ANAINIT; /* Analog Startup Delay */ - register8_t EVSYSLOCK; /* Event System Lock */ - register8_t WEXLOCK; /* WEX Lock */ - register8_t FAULTLOCK; /* FAULT Lock */ - register8_t reserved_0x0B; -} MCU_t; - - -/* --------------------------------------------------------------------------- -PMIC - Programmable Multi-level Interrupt Controller --------------------------------------------------------------------------- -*/ - -/* Programmable Multi-level Interrupt Controller */ -typedef struct PMIC_struct -{ - register8_t STATUS; /* Status Register */ - register8_t INTPRI; /* Interrupt Priority */ - register8_t CTRL; /* Control Register */ - register8_t reserved_0x03; - register8_t reserved_0x04; - register8_t reserved_0x05; - register8_t reserved_0x06; - register8_t reserved_0x07; - register8_t reserved_0x08; - register8_t reserved_0x09; - register8_t reserved_0x0A; - register8_t reserved_0x0B; - register8_t reserved_0x0C; - register8_t reserved_0x0D; - register8_t reserved_0x0E; - register8_t reserved_0x0F; -} PMIC_t; - - -/* --------------------------------------------------------------------------- -PORTCFG - Port Configuration --------------------------------------------------------------------------- -*/ - -/* I/O port Configuration */ -typedef struct PORTCFG_struct -{ - register8_t MPCMASK; /* Multi-pin Configuration Mask */ - register8_t reserved_0x01; - register8_t reserved_0x02; - register8_t reserved_0x03; - register8_t CLKOUT; /* Clock Out Register */ - register8_t reserved_0x05; - register8_t ACEVOUT; /* Analog Comparator and Event Out Register */ - register8_t SRLCTRL; /* Slew Rate Limit Control Register */ -} PORTCFG_t; - -/* Clock and Event Output Port */ -typedef enum PORTCFG_CLKEVPIN_enum -{ - PORTCFG_CLKEVPIN_PIN7_gc = (0x00<<7), /* Clock and Event Ouput on PIN 7 */ - PORTCFG_CLKEVPIN_PIN4_gc = (0x01<<7), /* Clock and Event Ouput on PIN 4 */ -} PORTCFG_CLKEVPIN_t; - -/* RTC Clock Output Port */ -typedef enum PORTCFG_RTCCLKOUT_enum -{ - PORTCFG_RTCCLKOUT_OFF_gc = (0x00<<5), /* System Clock Output Disabled */ - PORTCFG_RTCCLKOUT_PC6_gc = (0x01<<5), /* System Clock Output on Port C pin 6 */ - PORTCFG_RTCCLKOUT_PD6_gc = (0x02<<5), /* System Clock Output on Port D pin 6 */ - PORTCFG_RTCCLKOUT_PR0_gc = (0x03<<5), /* System Clock Output on Port R pin 0 */ -} PORTCFG_RTCCLKOUT_t; - -/* Peripheral Clock Output Select */ -typedef enum PORTCFG_CLKOUTSEL_enum -{ - PORTCFG_CLKOUTSEL_CLK1X_gc = (0x00<<2), /* 1x Peripheral Clock Output to pin */ - PORTCFG_CLKOUTSEL_CLK2X_gc = (0x01<<2), /* 2x Peripheral Clock Output to pin */ - PORTCFG_CLKOUTSEL_CLK4X_gc = (0x02<<2), /* 4x Peripheral Clock Output to pin */ -} PORTCFG_CLKOUTSEL_t; - -/* System Clock Output Port */ -typedef enum PORTCFG_CLKOUT_enum -{ - PORTCFG_CLKOUT_OFF_gc = (0x00<<0), /* System Clock Output Disabled */ - PORTCFG_CLKOUT_PC7_gc = (0x01<<0), /* System Clock Output on Port C pin 7 */ - PORTCFG_CLKOUT_PD7_gc = (0x02<<0), /* System Clock Output on Port D pin 7 */ - PORTCFG_CLKOUT_PR0_gc = (0x03<<0), /* System Clock Output on Port R pin 0 */ -} PORTCFG_CLKOUT_t; - -/* Analog Comparator Output Port */ -typedef enum PORTCFG_ACOUT_enum -{ - PORTCFG_ACOUT_PA_gc = (0x00<<6), /* Analog Comparator Outputs on Port A, Pin 6-7 */ - PORTCFG_ACOUT_PC_gc = (0x01<<6), /* Analog Comparator Outputs on Port C, Pin 6-7 */ - PORTCFG_ACOUT_PD_gc = (0x02<<6), /* Analog Comparator Outputs on Port D, Pin 6-7 */ - PORTCFG_ACOUT_PR_gc = (0x03<<6), /* Analog Comparator Outputs on Port R, Pin 0-1 */ -} PORTCFG_ACOUT_t; - -/* Event Output Port */ -typedef enum PORTCFG_EVOUT_enum -{ - PORTCFG_EVOUT_OFF_gc = (0x00<<4), /* Event Output Disabled */ - PORTCFG_EVOUT_PC7_gc = (0x01<<4), /* Event Channel n Output on Port C pin 7 */ - PORTCFG_EVOUT_PD7_gc = (0x02<<4), /* Event Channel n Output on Port D pin 7 */ - PORTCFG_EVOUT_PR0_gc = (0x03<<4), /* Event Channel n Output on Port R pin 0 */ -} PORTCFG_EVOUT_t; - -/* Event Output Select */ -typedef enum PORTCFG_EVOUTSEL_enum -{ - PORTCFG_EVOUTSEL_0_gc = (0x00<<0), /* Event Channel 0 output to pin */ - PORTCFG_EVOUTSEL_1_gc = (0x01<<0), /* Event Channel 1 output to pin */ - PORTCFG_EVOUTSEL_2_gc = (0x02<<0), /* Event Channel 2 output to pin */ - PORTCFG_EVOUTSEL_3_gc = (0x03<<0), /* Event Channel 3 output to pin */ - PORTCFG_EVOUTSEL_4_gc = (0x04<<0), /* Event Channel 4 output to pin */ - PORTCFG_EVOUTSEL_5_gc = (0x05<<0), /* Event Channel 5 output to pin */ - PORTCFG_EVOUTSEL_6_gc = (0x06<<0), /* Event Channel 6 output to pin */ - PORTCFG_EVOUTSEL_7_gc = (0x07<<0), /* Event Channel 7 output to pin */ -} PORTCFG_EVOUTSEL_t; - - -/* --------------------------------------------------------------------------- -CRC - Cyclic Redundancy Checker --------------------------------------------------------------------------- -*/ - -/* Cyclic Redundancy Checker */ -typedef struct CRC_struct -{ - register8_t CTRL; /* Control Register */ - register8_t STATUS; /* Status Register */ - register8_t reserved_0x02; - register8_t DATAIN; /* Data Input */ - register8_t CHECKSUM0; /* Checksum byte 0 */ - register8_t CHECKSUM1; /* Checksum byte 1 */ - register8_t CHECKSUM2; /* Checksum byte 2 */ - register8_t CHECKSUM3; /* Checksum byte 3 */ -} CRC_t; - -/* Reset */ -typedef enum CRC_RESET_enum -{ - CRC_RESET_NO_gc = (0x00<<6), /* No Reset */ - CRC_RESET_RESET0_gc = (0x02<<6), /* Reset CRC with CHECKSUM to all zeros */ - CRC_RESET_RESET1_gc = (0x03<<6), /* Reset CRC with CHECKSUM to all ones */ -} CRC_RESET_t; - -/* Input Source */ -typedef enum CRC_SOURCE_enum -{ - CRC_SOURCE_DISABLE_gc = (0x00<<0), /* Disabled */ - CRC_SOURCE_IO_gc = (0x01<<0), /* I/O Interface */ - CRC_SOURCE_FLASH_gc = (0x02<<0), /* Flash */ - CRC_SOURCE_DMAC0_gc = (0x04<<0), /* DMAC Channel 0 */ - CRC_SOURCE_DMAC1_gc = (0x05<<0), /* DMAC Channel 1 */ - CRC_SOURCE_DMAC2_gc = (0x06<<0), /* DMAC Channel 2 */ - CRC_SOURCE_DMAC3_gc = (0x07<<0), /* DMAC Channel 3 */ -} CRC_SOURCE_t; - - -/* --------------------------------------------------------------------------- -EDMA - Enhanced DMA Controller --------------------------------------------------------------------------- -*/ - -/* EDMA Channel */ -typedef struct EDMA_CH_struct -{ - register8_t CTRLA; /* Channel Control A */ - register8_t CTRLB; /* Channel Control */ - register8_t ADDRCTRL; /* Memory Address Control for Peripheral Ch., or Source Address Control for Standard Ch. */ - register8_t DESTADDRCTRL; /* Destination Address Control for Standard Channels Only. */ - register8_t TRIGSRC; /* Channel Trigger Source */ - register8_t reserved_0x05; - _WORDREGISTER(TRFCNT); /* Channel Block Transfer Count for Peripheral Ch., or Channel Block Transfer Count Low for Standard Ch. */ - _WORDREGISTER(ADDR); /* Channel Memory Address for Peripheral Ch., or Channel Source Address Low for Standard Ch. */ - register8_t reserved_0x0A; - register8_t reserved_0x0B; - _WORDREGISTER(DESTADDR); /* Channel Destination Address for Standard Channels Only. */ - register8_t reserved_0x0E; - register8_t reserved_0x0F; -} EDMA_CH_t; - - -/* Enhanced DMA Controller */ -typedef struct EDMA_struct -{ - register8_t CTRL; /* Control */ - register8_t reserved_0x01; - register8_t reserved_0x02; - register8_t INTFLAGS; /* Transfer Interrupt Status */ - register8_t STATUS; /* Status */ - register8_t reserved_0x05; - register8_t TEMP; /* Temporary Register For 16-bit Access */ - register8_t reserved_0x07; - register8_t reserved_0x08; - register8_t reserved_0x09; - register8_t reserved_0x0A; - register8_t reserved_0x0B; - register8_t reserved_0x0C; - register8_t reserved_0x0D; - register8_t reserved_0x0E; - register8_t reserved_0x0F; - EDMA_CH_t CH0; /* EDMA Channel 0 */ - EDMA_CH_t CH1; /* EDMA Channel 1 */ - EDMA_CH_t CH2; /* EDMA Channel 2 */ - EDMA_CH_t CH3; /* EDMA Channel 3 */ -} EDMA_t; - -/* Channel mode */ -typedef enum EDMA_CHMODE_enum -{ - EDMA_CHMODE_PER0123_gc = (0x00<<4), /* Channels 0, 1, 2 and 3 in peripheal conf. */ - EDMA_CHMODE_STD0_gc = (0x01<<4), /* Channel 0 in standard conf.; channels 2 and 3 in peripheral conf. */ - EDMA_CHMODE_STD2_gc = (0x02<<4), /* Channel 2 in standard conf.; channels 0 and 1 in peripheral conf. */ - EDMA_CHMODE_STD02_gc = (0x03<<4), /* Channels 0 and 2 in standard conf. */ -} EDMA_CHMODE_t; - -/* Double buffer mode */ -typedef enum EDMA_DBUFMODE_enum -{ - EDMA_DBUFMODE_DISABLE_gc = (0x00<<2), /* No double buffer enabled */ - EDMA_DBUFMODE_BUF01_gc = (0x01<<2), /* Double buffer enabled on peripheral channels 0/1 (if exist) */ - EDMA_DBUFMODE_BUF23_gc = (0x02<<2), /* Double buffer enabled on peripheral channels 2/3 (if exist) */ - EDMA_DBUFMODE_BUF0123_gc = (0x03<<2), /* Double buffer enabled on peripheral channels 0/1 and 2/3 or standard channels 0/2 */ -} EDMA_DBUFMODE_t; - -/* Priority mode */ -typedef enum EDMA_PRIMODE_enum -{ - EDMA_PRIMODE_RR0123_gc = (0x00<<0), /* Round robin on all channels */ - EDMA_PRIMODE_RR123_gc = (0x01<<0), /* Ch0 > round robin (Ch 1 ch2 Ch3) */ - EDMA_PRIMODE_RR23_gc = (0x02<<0), /* Ch0 > Ch 1 > round robin (Ch2 Ch3) */ - EDMA_PRIMODE_CH0123_gc = (0x03<<0), /* Ch0 > Ch1 > Ch2 > Ch3 */ -} EDMA_PRIMODE_t; - -/* Memory Address Reload for Peripheral Ch., or Source Address Reload for Standard Ch. */ -typedef enum EDMA_CH_RELOAD_enum -{ - EDMA_CH_RELOAD_NONE_gc = (0x00<<4), /* No reload */ - EDMA_CH_RELOAD_BLOCK_gc = (0x01<<4), /* Reload at end of each block transfer */ - EDMA_CH_RELOAD_BURST_gc = (0x02<<4), /* Reload at end of each burst transfer */ - EDMA_CH_RELOAD_TRANSACTION_gc = (0x03<<4), /* Reload at end of each transaction */ -} EDMA_CH_RELOAD_t; - -/* Memory Address Mode for Peripheral Ch., or Source Address Mode for Standard Ch. */ -typedef enum EDMA_CH_DIR_enum -{ - EDMA_CH_DIR_FIXED_gc = (0x00<<0), /* Fixed */ - EDMA_CH_DIR_INC_gc = (0x01<<0), /* Increment */ - EDMA_CH_DIR_MP1_gc = (0x04<<0), /* If Peripheral Ch. (Per ==> Mem), 1-byte 'mask-match' (data: ADDRL, mask: ADDRH), else reserved conf. */ - EDMA_CH_DIR_MP2_gc = (0x05<<0), /* If Peripheral Ch. (Per ==> Mem), 1-byte 'OR-match' (data-1: ADDRL OR data-2: ADDRH), else reserved conf. */ - EDMA_CH_DIR_MP3_gc = (0x06<<0), /* If Peripheral Ch. (Per ==> Mem), 2-byte 'match' (data-1: ADDRL followed by data-2: ADDRH), else reserved conf. */ -} EDMA_CH_DIR_t; - -/* Destination addressing mode */ -typedef enum EDMA_CH_DESTDIR_enum -{ - EDMA_CH_DESTDIR_FIXED_gc = (0x00<<0), /* Fixed */ - EDMA_CH_DESTDIR_INC_gc = (0x01<<0), /* Increment */ - EDMA_CH_DESTDIR_MP1_gc = (0x04<<0), /* 1-byte 'mask-match' (data: ADDRL, mask: ADDRH) */ - EDMA_CH_DESTDIR_MP2_gc = (0x05<<0), /* 1-byte 'OR-match' (data-1: ADDRL OR data-2: ADDRH) */ - EDMA_CH_DESTDIR_MP3_gc = (0x06<<0), /* 2-byte 'match' (data1: ADDRL followed by data2: ADDRH) */ -} EDMA_CH_DESTDIR_t; - -/* Transfer trigger source */ -typedef enum EDMA_CH_TRIGSRC_enum -{ - EDMA_CH_TRIGSRC_OFF_gc = (0x00<<0), /* Software triggers only */ - EDMA_CH_TRIGSRC_EVSYS_CH0_gc = (0x01<<0), /* Event CH0 as trigger (Standard Channels Only) */ - EDMA_CH_TRIGSRC_EVSYS_CH1_gc = (0x02<<0), /* Event CH1 as trigger (Standard Channels Only) */ - EDMA_CH_TRIGSRC_EVSYS_CH2_gc = (0x03<<0), /* Event CH2 as trigger (Standard Channels Only) */ - EDMA_CH_TRIGSRC_ADCA_CH0_gc = (0x10<<0), /* ADCA CH0 as trigger */ - EDMA_CH_TRIGSRC_DACA_CH0_gc = (0x15<<0), /* DACA CH0 as trigger */ - EDMA_CH_TRIGSRC_DACA_CH1_gc = (0x16<<0), /* DACA CH1 as trigger */ - EDMA_CH_TRIGSRC_TCC4_OVF_gc = (0x40<<0), /* TCC4 overflow/underflow as trigger (Standard Channels Only) */ - EDMA_CH_TRIGSRC_TCC4_ERR_gc = (0x41<<0), /* TCC4 error as trigger (Standard Channels Only) */ - EDMA_CH_TRIGSRC_TCC4_CCA_gc = (0x42<<0), /* TCC4 compare or capture channel A as trigger (Standard Channels Only) */ - EDMA_CH_TRIGSRC_TCC4_CCB_gc = (0x43<<0), /* TCC4 compare or capture channel B as trigger (Standard Channels Only) */ - EDMA_CH_TRIGSRC_TCC4_CCC_gc = (0x44<<0), /* TCC4 compare or capture channel C as trigger (Standard Channels Only) */ - EDMA_CH_TRIGSRC_TCC4_CCD_gc = (0x45<<0), /* TCC4 compare or capture channel D as trigger (Standard Channels Only) */ - EDMA_CH_TRIGSRC_TCC5_OVF_gc = (0x46<<0), /* TCC5 overflow/underflow as trigger (Standard Channels Only) */ - EDMA_CH_TRIGSRC_TCC5_ERR_gc = (0x47<<0), /* TCC5 error as trigger (Standard Channels Only) */ - EDMA_CH_TRIGSRC_TCC5_CCA_gc = (0x48<<0), /* TCC5 compare or capture channel A as trigger (Standard Channels Only) */ - EDMA_CH_TRIGSRC_TCC5_CCB_gc = (0x49<<0), /* TCC5 compare or capture channel B as trigger (Standard Channels Only) */ - EDMA_CH_TRIGSRC_SPIC_RXC_gc = (0x4A<<0), /* SPI C transfer complete (SPI Standard Mode) or SPI C receive complete as trigger (SPI Buffer Modes) */ - EDMA_CH_TRIGSRC_SPIC_DRE_gc = (0x4B<<0), /* SPI C transfer complete (SPI Standard Mode) or SPI C data register empty as trigger (SPI Buffer modes) */ - EDMA_CH_TRIGSRC_USARTC0_RXC_gc = (0x4C<<0), /* USART C0 receive complete as trigger */ - EDMA_CH_TRIGSRC_USARTC0_DRE_gc = (0x4D<<0), /* USART C0 data register empty as trigger */ - EDMA_CH_TRIGSRC_TCD5_OVF_gc = (0x66<<0), /* TCD5 overflow/underflow as trigger (Standard Channels Only) */ - EDMA_CH_TRIGSRC_TCD5_ERR_gc = (0x67<<0), /* TCD5 error as trigger (Standard Channels Only) */ - EDMA_CH_TRIGSRC_TCD5_CCA_gc = (0x68<<0), /* TCD5 compare or capture channel A as trigger (Standard Channels Only) */ - EDMA_CH_TRIGSRC_TCD5_CCB_gc = (0x69<<0), /* TCD5 compare or capture channel B as trigger (Standard Channels Only) */ - EDMA_CH_TRIGSRC_USARTD0_RXC_gc = (0x6C<<0), /* USART D0 receive complete as trigger */ - EDMA_CH_TRIGSRC_USARTD0_DRE_gc = (0x6D<<0), /* USART D0 data register empty as trigger */ -} EDMA_CH_TRIGSRC_t; - -/* Interrupt level */ -typedef enum EDMA_CH_INTLVL_enum -{ - EDMA_CH_INTLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ - EDMA_CH_INTLVL_LO_gc = (0x01<<2), /* Low level */ - EDMA_CH_INTLVL_MED_gc = (0x02<<2), /* Medium level */ - EDMA_CH_INTLVL_HI_gc = (0x03<<2), /* High level */ -} EDMA_CH_INTLVL_t; - - -/* --------------------------------------------------------------------------- -EVSYS - Event System --------------------------------------------------------------------------- -*/ - -/* Event System */ -typedef struct EVSYS_struct -{ - register8_t CH0MUX; /* Event Channel 0 Multiplexer */ - register8_t CH1MUX; /* Event Channel 1 Multiplexer */ - register8_t CH2MUX; /* Event Channel 2 Multiplexer */ - register8_t CH3MUX; /* Event Channel 3 Multiplexer */ - register8_t CH4MUX; /* Event Channel 4 Multiplexer */ - register8_t CH5MUX; /* Event Channel 5 Multiplexer */ - register8_t CH6MUX; /* Event Channel 6 Multiplexer */ - register8_t CH7MUX; /* Event Channel 7 Multiplexer */ - register8_t CH0CTRL; /* Channel 0 Control Register */ - register8_t CH1CTRL; /* Channel 1 Control Register */ - register8_t CH2CTRL; /* Channel 2 Control Register */ - register8_t CH3CTRL; /* Channel 3 Control Register */ - register8_t CH4CTRL; /* Channel 4 Control Register */ - register8_t CH5CTRL; /* Channel 5 Control Register */ - register8_t CH6CTRL; /* Channel 6 Control Register */ - register8_t CH7CTRL; /* Channel 7 Control Register */ - register8_t STROBE; /* Event Strobe */ - register8_t DATA; /* Event Data */ - register8_t DFCTRL; /* Digital Filter Control Register */ -} EVSYS_t; - -/* Event Channel multiplexer input selection */ -typedef enum EVSYS_CHMUX_enum -{ - EVSYS_CHMUX_OFF_gc = (0x00<<0), /* Off */ - EVSYS_CHMUX_RTC_OVF_gc = (0x08<<0), /* RTC Overflow */ - EVSYS_CHMUX_RTC_CMP_gc = (0x09<<0), /* RTC Compare Match */ - EVSYS_CHMUX_ACA_CH0_gc = (0x10<<0), /* Analog Comparator A Channel 0 */ - EVSYS_CHMUX_ACA_CH1_gc = (0x11<<0), /* Analog Comparator A Channel 1 */ - EVSYS_CHMUX_ACA_WIN_gc = (0x12<<0), /* Analog Comparator A Window */ - EVSYS_CHMUX_ADCA_CH0_gc = (0x20<<0), /* ADC A Channel 0 */ - EVSYS_CHMUX_PORTA_PIN0_gc = (0x50<<0), /* Port A, Pin0 */ - EVSYS_CHMUX_PORTA_PIN1_gc = (0x51<<0), /* Port A, Pin1 */ - EVSYS_CHMUX_PORTA_PIN2_gc = (0x52<<0), /* Port A, Pin2 */ - EVSYS_CHMUX_PORTA_PIN3_gc = (0x53<<0), /* Port A, Pin3 */ - EVSYS_CHMUX_PORTA_PIN4_gc = (0x54<<0), /* Port A, Pin4 */ - EVSYS_CHMUX_PORTA_PIN5_gc = (0x55<<0), /* Port A, Pin5 */ - EVSYS_CHMUX_PORTA_PIN6_gc = (0x56<<0), /* Port A, Pin6 */ - EVSYS_CHMUX_PORTA_PIN7_gc = (0x57<<0), /* Port A, Pin7 */ - EVSYS_CHMUX_PORTC_PIN0_gc = (0x60<<0), /* Port C, Pin0 */ - EVSYS_CHMUX_PORTC_PIN1_gc = (0x61<<0), /* Port C, Pin1 */ - EVSYS_CHMUX_PORTC_PIN2_gc = (0x62<<0), /* Port C, Pin2 */ - EVSYS_CHMUX_PORTC_PIN3_gc = (0x63<<0), /* Port C, Pin3 */ - EVSYS_CHMUX_PORTC_PIN4_gc = (0x64<<0), /* Port C, Pin4 */ - EVSYS_CHMUX_PORTC_PIN5_gc = (0x65<<0), /* Port C, Pin5 */ - EVSYS_CHMUX_PORTC_PIN6_gc = (0x66<<0), /* Port C, Pin6 */ - EVSYS_CHMUX_PORTC_PIN7_gc = (0x67<<0), /* Port C, Pin7 */ - EVSYS_CHMUX_PORTD_PIN0_gc = (0x68<<0), /* Port D, Pin0 */ - EVSYS_CHMUX_PORTD_PIN1_gc = (0x69<<0), /* Port D, Pin1 */ - EVSYS_CHMUX_PORTD_PIN2_gc = (0x6A<<0), /* Port D, Pin2 */ - EVSYS_CHMUX_PORTD_PIN3_gc = (0x6B<<0), /* Port D, Pin3 */ - EVSYS_CHMUX_PORTD_PIN4_gc = (0x6C<<0), /* Port D, Pin4 */ - EVSYS_CHMUX_PORTD_PIN5_gc = (0x6D<<0), /* Port D, Pin5 */ - EVSYS_CHMUX_PORTD_PIN6_gc = (0x6E<<0), /* Port D, Pin6 */ - EVSYS_CHMUX_PORTD_PIN7_gc = (0x6F<<0), /* Port D, Pin7 */ - EVSYS_CHMUX_PRESCALER_1_gc = (0x80<<0), /* Prescaler, divide by 1 */ - EVSYS_CHMUX_PRESCALER_2_gc = (0x81<<0), /* Prescaler, divide by 2 */ - EVSYS_CHMUX_PRESCALER_4_gc = (0x82<<0), /* Prescaler, divide by 4 */ - EVSYS_CHMUX_PRESCALER_8_gc = (0x83<<0), /* Prescaler, divide by 8 */ - EVSYS_CHMUX_PRESCALER_16_gc = (0x84<<0), /* Prescaler, divide by 16 */ - EVSYS_CHMUX_PRESCALER_32_gc = (0x85<<0), /* Prescaler, divide by 32 */ - EVSYS_CHMUX_PRESCALER_64_gc = (0x86<<0), /* Prescaler, divide by 64 */ - EVSYS_CHMUX_PRESCALER_128_gc = (0x87<<0), /* Prescaler, divide by 128 */ - EVSYS_CHMUX_PRESCALER_256_gc = (0x88<<0), /* Prescaler, divide by 256 */ - EVSYS_CHMUX_PRESCALER_512_gc = (0x89<<0), /* Prescaler, divide by 512 */ - EVSYS_CHMUX_PRESCALER_1024_gc = (0x8A<<0), /* Prescaler, divide by 1024 */ - EVSYS_CHMUX_PRESCALER_2048_gc = (0x8B<<0), /* Prescaler, divide by 2048 */ - EVSYS_CHMUX_PRESCALER_4096_gc = (0x8C<<0), /* Prescaler, divide by 4096 */ - EVSYS_CHMUX_PRESCALER_8192_gc = (0x8D<<0), /* Prescaler, divide by 8192 */ - EVSYS_CHMUX_PRESCALER_16384_gc = (0x8E<<0), /* Prescaler, divide by 16384 */ - EVSYS_CHMUX_PRESCALER_32768_gc = (0x8F<<0), /* Prescaler, divide by 32768 */ - EVSYS_CHMUX_XCL_UNF0_gc = (0xB0<<0), /* XCL BTC0 underflow */ - EVSYS_CHMUX_XCL_UNF1_gc = (0xB1<<0), /* XCL BTC1 underflow */ - EVSYS_CHMUX_XCL_CC0_gc = (0xB2<<0), /* XCL BTC0 capture or compare */ - EVSYS_CHMUX_XCL_CC1_gc = (0xB3<<0), /* XCL BTC0 capture or compare */ - EVSYS_CHMUX_XCL_PEC0_gc = (0xB4<<0), /* XCL PEC0 restart */ - EVSYS_CHMUX_XCL_PEC1_gc = (0xB5<<0), /* XCL PEC1 restart */ - EVSYS_CHMUX_XCL_LUT0_gc = (0xB6<<0), /* XCL LUT0 output */ - EVSYS_CHMUX_XCL_LUT1_gc = (0xB7<<0), /* XCL LUT1 output */ - EVSYS_CHMUX_TCC4_OVF_gc = (0xC0<<0), /* Timer/Counter C4 Overflow */ - EVSYS_CHMUX_TCC4_ERR_gc = (0xC1<<0), /* Timer/Counter C4 Error */ - EVSYS_CHMUX_TCC4_CCA_gc = (0xC4<<0), /* Timer/Counter C4 Compare or Capture A */ - EVSYS_CHMUX_TCC4_CCB_gc = (0xC5<<0), /* Timer/Counter C4 Compare or Capture B */ - EVSYS_CHMUX_TCC4_CCC_gc = (0xC6<<0), /* Timer/Counter C4 Compare or Capture C */ - EVSYS_CHMUX_TCC4_CCD_gc = (0xC7<<0), /* Timer/Counter C4 Compare or Capture D */ - EVSYS_CHMUX_TCC5_OVF_gc = (0xC8<<0), /* Timer/Counter C5 Overflow */ - EVSYS_CHMUX_TCC5_ERR_gc = (0xC9<<0), /* Timer/Counter C5 Error */ - EVSYS_CHMUX_TCC5_CCA_gc = (0xCC<<0), /* Timer/Counter C5 Compare or Capture A */ - EVSYS_CHMUX_TCC5_CCB_gc = (0xCD<<0), /* Timer/Counter C5 Compare or Capture B */ - EVSYS_CHMUX_TCD5_OVF_gc = (0xD8<<0), /* Timer/Counter D5 Overflow */ - EVSYS_CHMUX_TCD5_ERR_gc = (0xD9<<0), /* Timer/Counter D5 Error */ - EVSYS_CHMUX_TCD5_CCA_gc = (0xDC<<0), /* Timer/Counter D5 Compare or Capture A */ - EVSYS_CHMUX_TCD5_CCB_gc = (0xDD<<0), /* Timer/Counter D5 Compare or Capture B */ -} EVSYS_CHMUX_t; - -/* Quadrature Decoder Index Recognition Mode */ -typedef enum EVSYS_QDIRM_enum -{ - EVSYS_QDIRM_00_gc = (0x00<<5), /* QDPH0 = 0, QDPH90 = 0 */ - EVSYS_QDIRM_01_gc = (0x01<<5), /* QDPH0 = 0, QDPH90 = 1 */ - EVSYS_QDIRM_10_gc = (0x02<<5), /* QDPH0 = 1, QDPH90 = 0 */ - EVSYS_QDIRM_11_gc = (0x03<<5), /* QDPH0 = 1, QDPH90 = 1 */ -} EVSYS_QDIRM_t; - -/* Digital filter coefficient */ -typedef enum EVSYS_DIGFILT_enum -{ - EVSYS_DIGFILT_1SAMPLE_gc = (0x00<<0), /* 1 SAMPLE */ - EVSYS_DIGFILT_2SAMPLES_gc = (0x01<<0), /* 2 SAMPLES */ - EVSYS_DIGFILT_3SAMPLES_gc = (0x02<<0), /* 3 SAMPLES */ - EVSYS_DIGFILT_4SAMPLES_gc = (0x03<<0), /* 4 SAMPLES */ - EVSYS_DIGFILT_5SAMPLES_gc = (0x04<<0), /* 5 SAMPLES */ - EVSYS_DIGFILT_6SAMPLES_gc = (0x05<<0), /* 6 SAMPLES */ - EVSYS_DIGFILT_7SAMPLES_gc = (0x06<<0), /* 7 SAMPLES */ - EVSYS_DIGFILT_8SAMPLES_gc = (0x07<<0), /* 8 SAMPLES */ -} EVSYS_DIGFILT_t; - -/* Prescaler Filter */ -typedef enum EVSYS_PRESCFILT_enum -{ - EVSYS_PRESCFILT_CH04_gc = (0x01<<4), /* Enable prescaler filter for either channel 0 or 4 */ - EVSYS_PRESCFILT_CH15_gc = (0x02<<4), /* Enable prescaler filter for either channel 1 or 5 */ - EVSYS_PRESCFILT_CH26_gc = (0x04<<4), /* Enable prescaler filter for either channel 2 or 6 */ - EVSYS_PRESCFILT_CH37_gc = (0x08<<4), /* Enable prescaler filter for either channel 3 or 7 */ -} EVSYS_PRESCFILT_t; - -/* Prescaler */ -typedef enum EVSYS_PRESCALER_enum -{ - EVSYS_PRESCALER_CLKPER_8_gc = (0x00<<0), /* CLKPER, divide by 8 */ - EVSYS_PRESCALER_CLKPER_64_gc = (0x01<<0), /* CLKPER, divide by 64 */ - EVSYS_PRESCALER_CLKPER_512_gc = (0x02<<0), /* CLKPER, divide by 512 */ - EVSYS_PRESCALER_CLKPER_4096_gc = (0x03<<0), /* CLKPER, divide by 4096 */ - EVSYS_PRESCALER_CLKPER_32768_gc = (0x04<<0), /* CLKPER, divide by 32768 */ -} EVSYS_PRESCALER_t; - - -/* --------------------------------------------------------------------------- -NVM - Non Volatile Memory Controller --------------------------------------------------------------------------- -*/ - -/* Non-volatile Memory Controller */ -typedef struct NVM_struct -{ - register8_t ADDR0; /* Address Register 0 */ - register8_t ADDR1; /* Address Register 1 */ - register8_t ADDR2; /* Address Register 2 */ - register8_t reserved_0x03; - register8_t DATA0; /* Data Register 0 */ - register8_t DATA1; /* Data Register 1 */ - register8_t DATA2; /* Data Register 2 */ - register8_t reserved_0x07; - register8_t reserved_0x08; - register8_t reserved_0x09; - register8_t CMD; /* Command */ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t INTCTRL; /* Interrupt Control */ - register8_t reserved_0x0E; - register8_t STATUS; /* Status */ - register8_t LOCK_BITS; /* Lock Bits (Changed from LOCKBITS to avoid avr-libc collision) */ -} NVM_t; - -/* NVM Command */ -typedef enum NVM_CMD_enum -{ - NVM_CMD_NO_OPERATION_gc = (0x00<<0), /* Noop/Ordinary LPM */ - NVM_CMD_READ_USER_SIG_ROW_gc = (0x01<<0), /* Read user signature row */ - NVM_CMD_READ_CALIB_ROW_gc = (0x02<<0), /* Read calibration row */ - NVM_CMD_READ_FUSES_gc = (0x07<<0), /* Read fuse byte */ - NVM_CMD_WRITE_LOCK_BITS_gc = (0x08<<0), /* Write lock bits */ - NVM_CMD_ERASE_USER_SIG_ROW_gc = (0x18<<0), /* Erase user signature row */ - NVM_CMD_WRITE_USER_SIG_ROW_gc = (0x1A<<0), /* Write user signature row */ - NVM_CMD_ERASE_APP_gc = (0x20<<0), /* Erase Application Section */ - NVM_CMD_ERASE_APP_PAGE_gc = (0x22<<0), /* Erase Application Section page */ - NVM_CMD_LOAD_FLASH_BUFFER_gc = (0x23<<0), /* Load Flash page buffer */ - NVM_CMD_WRITE_APP_PAGE_gc = (0x24<<0), /* Write Application Section page */ - NVM_CMD_ERASE_WRITE_APP_PAGE_gc = (0x25<<0), /* Erase-and-write Application Section page */ - NVM_CMD_ERASE_FLASH_BUFFER_gc = (0x26<<0), /* Erase/flush Flash page buffer */ - NVM_CMD_ERASE_BOOT_PAGE_gc = (0x2A<<0), /* Erase Boot Section page */ - NVM_CMD_ERASE_FLASH_PAGE_gc = (0x2B<<0), /* Erase Flash Page */ - NVM_CMD_WRITE_BOOT_PAGE_gc = (0x2C<<0), /* Write Boot Section page */ - NVM_CMD_ERASE_WRITE_BOOT_PAGE_gc = (0x2D<<0), /* Erase-and-write Boot Section page */ - NVM_CMD_WRITE_FLASH_PAGE_gc = (0x2E<<0), /* Write Flash Page */ - NVM_CMD_ERASE_WRITE_FLASH_PAGE_gc = (0x2F<<0), /* Erase-and-write Flash Page */ - NVM_CMD_ERASE_EEPROM_gc = (0x30<<0), /* Erase EEPROM */ - NVM_CMD_ERASE_EEPROM_PAGE_gc = (0x32<<0), /* Erase EEPROM page */ - NVM_CMD_WRITE_EEPROM_PAGE_gc = (0x34<<0), /* Write EEPROM page */ - NVM_CMD_ERASE_WRITE_EEPROM_PAGE_gc = (0x35<<0), /* Erase-and-write EEPROM page */ - NVM_CMD_ERASE_EEPROM_BUFFER_gc = (0x36<<0), /* Erase/flush EEPROM page buffer */ - NVM_CMD_APP_CRC_gc = (0x38<<0), /* Application section CRC */ - NVM_CMD_BOOT_CRC_gc = (0x39<<0), /* Boot Section CRC */ - NVM_CMD_FLASH_RANGE_CRC_gc = (0x3A<<0), /* Flash Range CRC */ - NVM_CMD_CHIP_ERASE_gc = (0x40<<0), /* Erase Chip */ - NVM_CMD_READ_NVM_gc = (0x43<<0), /* Read NVM */ - NVM_CMD_WRITE_FUSE_gc = (0x4C<<0), /* Write Fuse byte */ - NVM_CMD_ERASE_BOOT_gc = (0x68<<0), /* Erase Boot Section */ - NVM_CMD_FLASH_CRC_gc = (0x78<<0), /* Flash CRC */ -} NVM_CMD_t; - -/* SPM ready interrupt level */ -typedef enum NVM_SPMLVL_enum -{ - NVM_SPMLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ - NVM_SPMLVL_LO_gc = (0x01<<2), /* Low level */ - NVM_SPMLVL_MED_gc = (0x02<<2), /* Medium level */ - NVM_SPMLVL_HI_gc = (0x03<<2), /* High level */ -} NVM_SPMLVL_t; - -/* EEPROM ready interrupt level */ -typedef enum NVM_EELVL_enum -{ - NVM_EELVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ - NVM_EELVL_LO_gc = (0x01<<0), /* Low level */ - NVM_EELVL_MED_gc = (0x02<<0), /* Medium level */ - NVM_EELVL_HI_gc = (0x03<<0), /* High level */ -} NVM_EELVL_t; - -/* Boot lock bits - boot setcion */ -typedef enum NVM_BLBB_enum -{ - NVM_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ - NVM_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ - NVM_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ - NVM_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ -} NVM_BLBB_t; - -/* Boot lock bits - application section */ -typedef enum NVM_BLBA_enum -{ - NVM_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ - NVM_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ - NVM_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ - NVM_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ -} NVM_BLBA_t; - -/* Boot lock bits - application table section */ -typedef enum NVM_BLBAT_enum -{ - NVM_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ - NVM_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ - NVM_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ - NVM_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ -} NVM_BLBAT_t; - -/* Lock bits */ -typedef enum NVM_LB_enum -{ - NVM_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ - NVM_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ - NVM_LB_NOLOCK_gc = (0x03<<0), /* No locks */ -} NVM_LB_t; - - -/* --------------------------------------------------------------------------- -ADC - Analog/Digital Converter --------------------------------------------------------------------------- -*/ - -/* ADC Channel */ -typedef struct ADC_CH_struct -{ - register8_t CTRL; /* Control Register */ - register8_t MUXCTRL; /* MUX Control */ - register8_t INTCTRL; /* Channel Interrupt Control Register */ - register8_t INTFLAGS; /* Interrupt Flags */ - _WORDREGISTER(RES); /* Channel Result */ - register8_t SCAN; /* Input Channel Scan */ - register8_t CORRCTRL; /* Correction Control Register */ - register8_t OFFSETCORR0; /* Offset Correction Register 0 */ - register8_t OFFSETCORR1; /* Offset Correction Register 1 */ - register8_t GAINCORR0; /* Gain Correction Register 0 */ - register8_t GAINCORR1; /* Gain Correction Register 1 */ - register8_t AVGCTRL; /* Average Control Register */ - register8_t reserved_0x0D; - register8_t reserved_0x0E; - register8_t reserved_0x0F; -} ADC_CH_t; - - -/* Analog-to-Digital Converter */ -typedef struct ADC_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t REFCTRL; /* Reference Control */ - register8_t EVCTRL; /* Event Control */ - register8_t PRESCALER; /* Clock Prescaler */ - register8_t reserved_0x05; - register8_t INTFLAGS; /* Interrupt Flags */ - register8_t TEMP; /* Temporary Register */ - register8_t SAMPCTRL; /* ADC Sampling Time Control Register */ - register8_t reserved_0x09; - register8_t reserved_0x0A; - register8_t reserved_0x0B; - _WORDREGISTER(CAL); /* Calibration Value */ - register8_t reserved_0x0E; - register8_t reserved_0x0F; - _WORDREGISTER(CH0RES); /* Channel 0 Result */ - register8_t reserved_0x12; - register8_t reserved_0x13; - register8_t reserved_0x14; - register8_t reserved_0x15; - register8_t reserved_0x16; - register8_t reserved_0x17; - _WORDREGISTER(CMP); /* Compare Value */ - register8_t reserved_0x1A; - register8_t reserved_0x1B; - register8_t reserved_0x1C; - register8_t reserved_0x1D; - register8_t reserved_0x1E; - register8_t reserved_0x1F; - ADC_CH_t CH0; /* ADC Channel 0 */ -} ADC_t; - -/* Current Limitation */ -typedef enum ADC_CURRLIMIT_enum -{ - ADC_CURRLIMIT_NO_gc = (0x00<<5), /* No current limit, 300ksps max sampling rate */ - ADC_CURRLIMIT_LOW_gc = (0x01<<5), /* Low current limit, 250ksps max sampling rate */ - ADC_CURRLIMIT_MED_gc = (0x02<<5), /* Medium current limit, 150ksps max sampling rate */ - ADC_CURRLIMIT_HIGH_gc = (0x03<<5), /* High current limit, 50ksps max sampling rate */ -} ADC_CURRLIMIT_t; - -/* Conversion result resolution */ -typedef enum ADC_RESOLUTION_enum -{ - ADC_RESOLUTION_12BIT_gc = (0x00<<1), /* 12-bit right-adjusted result */ - ADC_RESOLUTION_MT12BIT_gc = (0x01<<1), /* More than 12-bit (oversapling) right-adjusted result */ - ADC_RESOLUTION_8BIT_gc = (0x02<<1), /* 8-bit right-adjusted result */ - ADC_RESOLUTION_LEFT12BIT_gc = (0x03<<1), /* 12-bit left-adjusted result */ -} ADC_RESOLUTION_t; - -/* Voltage reference selection */ -typedef enum ADC_REFSEL_enum -{ - ADC_REFSEL_INT1V_gc = (0x00<<4), /* Internal 1V */ - ADC_REFSEL_INTVCC_gc = (0x01<<4), /* Internal VCC / 1.6 */ - ADC_REFSEL_AREFA_gc = (0x02<<4), /* External reference on PORT A */ - ADC_REFSEL_AREFD_gc = (0x03<<4), /* External reference on PORT D */ - ADC_REFSEL_INTVCC2_gc = (0x04<<4), /* Internal VCC / 2 */ -} ADC_REFSEL_t; - -/* Event channel input selection */ -typedef enum ADC_EVSEL_enum -{ - ADC_EVSEL_0_gc = (0x00<<3), /* Event Channel 0 */ - ADC_EVSEL_1_gc = (0x01<<3), /* Event Channel 1 */ - ADC_EVSEL_2_gc = (0x02<<3), /* Event Channel 2 */ - ADC_EVSEL_3_gc = (0x03<<3), /* Event Channel 3 */ - ADC_EVSEL_4_gc = (0x04<<3), /* Event Channel 4 */ - ADC_EVSEL_5_gc = (0x05<<3), /* Event Channel 5 */ - ADC_EVSEL_6_gc = (0x06<<3), /* Event Channel 6 */ - ADC_EVSEL_7_gc = (0x07<<3), /* Event Channel 7 */ -} ADC_EVSEL_t; - -/* Event action selection */ -typedef enum ADC_EVACT_enum -{ - ADC_EVACT_NONE_gc = (0x00<<0), /* No event action */ - ADC_EVACT_CH0_gc = (0x01<<0), /* First event triggers channel conversion */ - ADC_EVACT_SYNCSWEEP_gc = (0x06<<0), /* The ADC is flushed and restarted for accurate timing */ -} ADC_EVACT_t; - -/* Clock prescaler */ -typedef enum ADC_PRESCALER_enum -{ - ADC_PRESCALER_DIV4_gc = (0x00<<0), /* Divide clock by 4 */ - ADC_PRESCALER_DIV8_gc = (0x01<<0), /* Divide clock by 8 */ - ADC_PRESCALER_DIV16_gc = (0x02<<0), /* Divide clock by 16 */ - ADC_PRESCALER_DIV32_gc = (0x03<<0), /* Divide clock by 32 */ - ADC_PRESCALER_DIV64_gc = (0x04<<0), /* Divide clock by 64 */ - ADC_PRESCALER_DIV128_gc = (0x05<<0), /* Divide clock by 128 */ - ADC_PRESCALER_DIV256_gc = (0x06<<0), /* Divide clock by 256 */ - ADC_PRESCALER_DIV512_gc = (0x07<<0), /* Divide clock by 512 */ -} ADC_PRESCALER_t; - -/* Gain factor */ -typedef enum ADC_CH_GAIN_enum -{ - ADC_CH_GAIN_1X_gc = (0x00<<2), /* 1x gain */ - ADC_CH_GAIN_2X_gc = (0x01<<2), /* 2x gain */ - ADC_CH_GAIN_4X_gc = (0x02<<2), /* 4x gain */ - ADC_CH_GAIN_8X_gc = (0x03<<2), /* 8x gain */ - ADC_CH_GAIN_16X_gc = (0x04<<2), /* 16x gain */ - ADC_CH_GAIN_32X_gc = (0x05<<2), /* 32x gain */ - ADC_CH_GAIN_64X_gc = (0x06<<2), /* 64x gain */ - ADC_CH_GAIN_DIV2_gc = (0x07<<2), /* x/2 gain */ -} ADC_CH_GAIN_t; - -/* Input mode */ -typedef enum ADC_CH_INPUTMODE_enum -{ - ADC_CH_INPUTMODE_INTERNAL_gc = (0x00<<0), /* Internal inputs, no gain */ - ADC_CH_INPUTMODE_SINGLEENDED_gc = (0x01<<0), /* Single-ended input, no gain */ - ADC_CH_INPUTMODE_DIFFWGAINL_gc = (0x02<<0), /* Differential input, gain with 4 LSB pins selection */ - ADC_CH_INPUTMODE_DIFFWGAINH_gc = (0x03<<0), /* Differential input, gain with 4 MSB pins selection */ -} ADC_CH_INPUTMODE_t; - -/* Positive input multiplexer selection */ -typedef enum ADC_CH_MUXPOS_enum -{ - ADC_CH_MUXPOS_PIN0_gc = (0x00<<3), /* Input pin 0 */ - ADC_CH_MUXPOS_PIN1_gc = (0x01<<3), /* Input pin 1 */ - ADC_CH_MUXPOS_PIN2_gc = (0x02<<3), /* Input pin 2 */ - ADC_CH_MUXPOS_PIN3_gc = (0x03<<3), /* Input pin 3 */ - ADC_CH_MUXPOS_PIN4_gc = (0x04<<3), /* Input pin 4 */ - ADC_CH_MUXPOS_PIN5_gc = (0x05<<3), /* Input pin 5 */ - ADC_CH_MUXPOS_PIN6_gc = (0x06<<3), /* Input pin 6 */ - ADC_CH_MUXPOS_PIN7_gc = (0x07<<3), /* Input pin 7 */ - ADC_CH_MUXPOS_PIN8_gc = (0x08<<3), /* Input pin 8 */ - ADC_CH_MUXPOS_PIN9_gc = (0x09<<3), /* Input pin 9 */ - ADC_CH_MUXPOS_PIN10_gc = (0x0A<<3), /* Input pin 10 */ - ADC_CH_MUXPOS_PIN11_gc = (0x0B<<3), /* Input pin 11 */ - ADC_CH_MUXPOS_PIN12_gc = (0x0C<<3), /* Input pin 12 */ - ADC_CH_MUXPOS_PIN13_gc = (0x0D<<3), /* Input pin 13 */ - ADC_CH_MUXPOS_PIN14_gc = (0x0E<<3), /* Input pin 14 */ - ADC_CH_MUXPOS_PIN15_gc = (0x0F<<3), /* Input pin 15 */ -} ADC_CH_MUXPOS_t; - -/* Internal input multiplexer selections */ -typedef enum ADC_CH_MUXINT_enum -{ - ADC_CH_MUXINT_TEMP_gc = (0x00<<3), /* Temperature Reference */ - ADC_CH_MUXINT_BANDGAP_gc = (0x01<<3), /* Bandgap Reference */ - ADC_CH_MUXINT_SCALEDVCC_gc = (0x02<<3), /* 1/10 Scaled VCC */ - ADC_CH_MUXINT_DAC_gc = (0x03<<3), /* DAC Output */ -} ADC_CH_MUXINT_t; - -/* Negative input multiplexer selection when gain on 4 LSB pins */ -typedef enum ADC_CH_MUXNEGL_enum -{ - ADC_CH_MUXNEGL_PIN0_gc = (0x00<<0), /* Input pin 0 */ - ADC_CH_MUXNEGL_PIN1_gc = (0x01<<0), /* Input pin 1 */ - ADC_CH_MUXNEGL_PIN2_gc = (0x02<<0), /* Input pin 2 */ - ADC_CH_MUXNEGL_PIN3_gc = (0x03<<0), /* Input pin 3 */ - ADC_CH_MUXNEGL_GND_gc = (0x05<<0), /* PAD ground */ - ADC_CH_MUXNEGL_INTGND_gc = (0x07<<0), /* Internal ground */ -} ADC_CH_MUXNEGL_t; - -/* Negative input multiplexer selection when gain on 4 MSB pins */ -typedef enum ADC_CH_MUXNEGH_enum -{ - ADC_CH_MUXNEGH_PIN4_gc = (0x00<<0), /* Input pin 4 */ - ADC_CH_MUXNEGH_PIN5_gc = (0x01<<0), /* Input pin 5 */ - ADC_CH_MUXNEGH_PIN6_gc = (0x02<<0), /* Input pin 6 */ - ADC_CH_MUXNEGH_PIN7_gc = (0x03<<0), /* Input pin 7 */ - ADC_CH_MUXNEGH_GND_gc = (0x05<<0), /* PAD ground */ -} ADC_CH_MUXNEGH_t; - -/* Negative input multiplexer selection */ -typedef enum ADC_CH_MUXNEG_enum -{ - ADC_CH_MUXNEG_PIN0_gc = (0x00<<0), /* Input pin 0 */ -} ADC_CH_MUXNEG_t; - -/* Interupt mode */ -typedef enum ADC_CH_INTMODE_enum -{ - ADC_CH_INTMODE_COMPLETE_gc = (0x00<<2), /* Interrupt on conversion complete */ - ADC_CH_INTMODE_BELOW_gc = (0x01<<2), /* Interrupt on result below compare value */ - ADC_CH_INTMODE_ABOVE_gc = (0x03<<2), /* Interrupt on result above compare value */ -} ADC_CH_INTMODE_t; - -/* Interrupt level */ -typedef enum ADC_CH_INTLVL_enum -{ - ADC_CH_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ - ADC_CH_INTLVL_LO_gc = (0x01<<0), /* Low level */ - ADC_CH_INTLVL_MED_gc = (0x02<<0), /* Medium level */ - ADC_CH_INTLVL_HI_gc = (0x03<<0), /* High level */ -} ADC_CH_INTLVL_t; - -/* Averaged Number of Samples */ -typedef enum ADC_SAMPNUM_enum -{ - ADC_SAMPNUM_1X_gc = (0x00<<0), /* 1 Sample */ - ADC_SAMPNUM_2X_gc = (0x01<<0), /* 2 Samples */ - ADC_SAMPNUM_4X_gc = (0x02<<0), /* 4 Samples */ - ADC_SAMPNUM_8X_gc = (0x03<<0), /* 8 Samples */ - ADC_SAMPNUM_16X_gc = (0x04<<0), /* 16 Samples */ - ADC_SAMPNUM_32X_gc = (0x05<<0), /* 32 Samples */ - ADC_SAMPNUM_64X_gc = (0x06<<0), /* 64 Samples */ - ADC_SAMPNUM_128X_gc = (0x07<<0), /* 128 Samples */ - ADC_SAMPNUM_256X_gc = (0x08<<0), /* 256 Samples */ - ADC_SAMPNUM_512X_gc = (0x09<<0), /* 512 Samples */ - ADC_SAMPNUM_1024X_gc = (0x0A<<0), /* 1024 Samples */ -} ADC_SAMPNUM_t; - - -/* --------------------------------------------------------------------------- -DAC - Digital/Analog Converter --------------------------------------------------------------------------- -*/ - -/* Digital-to-Analog Converter */ -typedef struct DAC_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t CTRLC; /* Control Register C */ - register8_t EVCTRL; /* Event Input Control */ - register8_t reserved_0x04; - register8_t STATUS; /* Status */ - register8_t reserved_0x06; - register8_t reserved_0x07; - register8_t CH0GAINCAL; /* Gain Calibration */ - register8_t CH0OFFSETCAL; /* Offset Calibration */ - register8_t CH1GAINCAL; /* Gain Calibration */ - register8_t CH1OFFSETCAL; /* Offset Calibration */ - register8_t reserved_0x0C; - register8_t reserved_0x0D; - register8_t reserved_0x0E; - register8_t reserved_0x0F; - register8_t reserved_0x10; - register8_t reserved_0x11; - register8_t reserved_0x12; - register8_t reserved_0x13; - register8_t reserved_0x14; - register8_t reserved_0x15; - register8_t reserved_0x16; - register8_t reserved_0x17; - _WORDREGISTER(CH0DATA); /* Channel 0 Data */ - _WORDREGISTER(CH1DATA); /* Channel 1 Data */ -} DAC_t; - -/* Output channel selection */ -typedef enum DAC_CHSEL_enum -{ - DAC_CHSEL_SINGLE_gc = (0x00<<5), /* Single channel operation (Channel 0 only) */ - DAC_CHSEL_SINGLE1_gc = (0x01<<5), /* Single channel operation (Channel 1 only) */ - DAC_CHSEL_DUAL_gc = (0x02<<5), /* Dual channel operation (Channel 0 and channel 1) */ -} DAC_CHSEL_t; - -/* Reference voltage selection */ -typedef enum DAC_REFSEL_enum -{ - DAC_REFSEL_INT1V_gc = (0x00<<3), /* Internal 1V */ - DAC_REFSEL_AVCC_gc = (0x01<<3), /* Analog supply voltage */ - DAC_REFSEL_AREFA_gc = (0x02<<3), /* External reference on AREF on PORTA */ - DAC_REFSEL_AREFB_gc = (0x03<<3), /* External reference on AREF on PORTB */ -} DAC_REFSEL_t; - -/* Event channel selection */ -typedef enum DAC_EVSEL_enum -{ - DAC_EVSEL_0_gc = (0x00<<0), /* Event Channel 0 */ - DAC_EVSEL_1_gc = (0x01<<0), /* Event Channel 1 */ - DAC_EVSEL_2_gc = (0x02<<0), /* Event Channel 2 */ - DAC_EVSEL_3_gc = (0x03<<0), /* Event Channel 3 */ - DAC_EVSEL_4_gc = (0x04<<0), /* Event Channel 4 */ - DAC_EVSEL_5_gc = (0x05<<0), /* Event Channel 5 */ - DAC_EVSEL_6_gc = (0x06<<0), /* Event Channel 6 */ - DAC_EVSEL_7_gc = (0x07<<0), /* Event Channel 7 */ -} DAC_EVSEL_t; - - -/* --------------------------------------------------------------------------- -AC - Analog Comparator --------------------------------------------------------------------------- -*/ - -/* Analog Comparator */ -typedef struct AC_struct -{ - register8_t AC0CTRL; /* Analog Comparator 0 Control */ - register8_t AC1CTRL; /* Analog Comparator 1 Control */ - register8_t AC0MUXCTRL; /* Analog Comparator 0 MUX Control */ - register8_t AC1MUXCTRL; /* Analog Comparator 1 MUX Control */ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t WINCTRL; /* Window Mode Control */ - register8_t STATUS; /* Status */ - register8_t CURRCTRL; /* Current Source Control Register */ - register8_t CURRCALIB; /* Current Source Calibration Register */ -} AC_t; - -/* Interrupt mode */ -typedef enum AC_INTMODE_enum -{ - AC_INTMODE_BOTHEDGES_gc = (0x00<<6), /* Interrupt on both edges */ - AC_INTMODE_FALLING_gc = (0x02<<6), /* Interrupt on falling edge */ - AC_INTMODE_RISING_gc = (0x03<<6), /* Interrupt on rising edge */ -} AC_INTMODE_t; - -/* Interrupt level */ -typedef enum AC_INTLVL_enum -{ - AC_INTLVL_OFF_gc = (0x00<<4), /* Interrupt disabled */ - AC_INTLVL_LO_gc = (0x01<<4), /* Low level */ - AC_INTLVL_MED_gc = (0x02<<4), /* Medium level */ - AC_INTLVL_HI_gc = (0x03<<4), /* High level */ -} AC_INTLVL_t; - -/* Hysteresis mode selection */ -typedef enum AC_HYSMODE_enum -{ - AC_HYSMODE_NO_gc = (0x00<<1), /* No hysteresis */ - AC_HYSMODE_SMALL_gc = (0x01<<1), /* Small hysteresis */ - AC_HYSMODE_LARGE_gc = (0x02<<1), /* Large hysteresis */ -} AC_HYSMODE_t; - -/* Positive input multiplexer selection */ -typedef enum AC_MUXPOS_enum -{ - AC_MUXPOS_PIN0_gc = (0x00<<3), /* Pin 0 */ - AC_MUXPOS_PIN1_gc = (0x01<<3), /* Pin 1 */ - AC_MUXPOS_PIN2_gc = (0x02<<3), /* Pin 2 */ - AC_MUXPOS_PIN3_gc = (0x03<<3), /* Pin 3 */ - AC_MUXPOS_PIN4_gc = (0x04<<3), /* Pin 4 */ - AC_MUXPOS_PIN5_gc = (0x05<<3), /* Pin 5 */ - AC_MUXPOS_PIN6_gc = (0x06<<3), /* Pin 6 */ - AC_MUXPOS_DAC_gc = (0x07<<3), /* DAC output */ -} AC_MUXPOS_t; - -/* Negative input multiplexer selection */ -typedef enum AC_MUXNEG_enum -{ - AC_MUXNEG_PIN0_gc = (0x00<<0), /* Pin 0 */ - AC_MUXNEG_PIN1_gc = (0x01<<0), /* Pin 1 */ - AC_MUXNEG_PIN3_gc = (0x02<<0), /* Pin 3 */ - AC_MUXNEG_PIN5_gc = (0x03<<0), /* Pin 5 */ - AC_MUXNEG_PIN7_gc = (0x04<<0), /* Pin 7 */ - AC_MUXNEG_DAC_gc = (0x05<<0), /* DAC output */ - AC_MUXNEG_BANDGAP_gc = (0x06<<0), /* Bandgap Reference */ - AC_MUXNEG_SCALER_gc = (0x07<<0), /* Internal voltage scaler */ -} AC_MUXNEG_t; - -/* Windows interrupt mode */ -typedef enum AC_WINTMODE_enum -{ - AC_WINTMODE_ABOVE_gc = (0x00<<2), /* Interrupt on above window */ - AC_WINTMODE_INSIDE_gc = (0x01<<2), /* Interrupt on inside window */ - AC_WINTMODE_BELOW_gc = (0x02<<2), /* Interrupt on below window */ - AC_WINTMODE_OUTSIDE_gc = (0x03<<2), /* Interrupt on outside window */ -} AC_WINTMODE_t; - -/* Window interrupt level */ -typedef enum AC_WINTLVL_enum -{ - AC_WINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ - AC_WINTLVL_LO_gc = (0x01<<0), /* Low priority */ - AC_WINTLVL_MED_gc = (0x02<<0), /* Medium priority */ - AC_WINTLVL_HI_gc = (0x03<<0), /* High priority */ -} AC_WINTLVL_t; - -/* Window mode state */ -typedef enum AC_WSTATE_enum -{ - AC_WSTATE_ABOVE_gc = (0x00<<6), /* Signal above window */ - AC_WSTATE_INSIDE_gc = (0x01<<6), /* Signal inside window */ - AC_WSTATE_BELOW_gc = (0x02<<6), /* Signal below window */ -} AC_WSTATE_t; - - -/* --------------------------------------------------------------------------- -RTC - Real-Time Clounter --------------------------------------------------------------------------- -*/ - -/* Real-Time Counter */ -typedef struct RTC_struct -{ - register8_t CTRL; /* Control Register */ - register8_t STATUS; /* Status Register */ - register8_t INTCTRL; /* Interrupt Control Register */ - register8_t INTFLAGS; /* Interrupt Flags */ - register8_t TEMP; /* Temporary register */ - register8_t reserved_0x05; - register8_t CALIB; /* Calibration Register */ - register8_t reserved_0x07; - _WORDREGISTER(CNT); /* Count Register */ - _WORDREGISTER(PER); /* Period Register */ - _WORDREGISTER(COMP); /* Compare Register */ -} RTC_t; - -/* Prescaler Factor */ -typedef enum RTC_PRESCALER_enum -{ - RTC_PRESCALER_OFF_gc = (0x00<<0), /* RTC Off */ - RTC_PRESCALER_DIV1_gc = (0x01<<0), /* RTC Clock */ - RTC_PRESCALER_DIV2_gc = (0x02<<0), /* RTC Clock / 2 */ - RTC_PRESCALER_DIV8_gc = (0x03<<0), /* RTC Clock / 8 */ - RTC_PRESCALER_DIV16_gc = (0x04<<0), /* RTC Clock / 16 */ - RTC_PRESCALER_DIV64_gc = (0x05<<0), /* RTC Clock / 64 */ - RTC_PRESCALER_DIV256_gc = (0x06<<0), /* RTC Clock / 256 */ - RTC_PRESCALER_DIV1024_gc = (0x07<<0), /* RTC Clock / 1024 */ -} RTC_PRESCALER_t; - -/* Compare Interrupt level */ -typedef enum RTC_COMPINTLVL_enum -{ - RTC_COMPINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ - RTC_COMPINTLVL_LO_gc = (0x01<<2), /* Low Level */ - RTC_COMPINTLVL_MED_gc = (0x02<<2), /* Medium Level */ - RTC_COMPINTLVL_HI_gc = (0x03<<2), /* High Level */ -} RTC_COMPINTLVL_t; - -/* Overflow Interrupt level */ -typedef enum RTC_OVFINTLVL_enum -{ - RTC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - RTC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ - RTC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ - RTC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ -} RTC_OVFINTLVL_t; - - -/* --------------------------------------------------------------------------- -XCL - XMEGA Custom Logic --------------------------------------------------------------------------- -*/ - -/* XMEGA Custom Logic */ -typedef struct XCL_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t CTRLC; /* Control Register C */ - register8_t CTRLD; /* Control Register D */ - register8_t CTRLE; /* Control Register E */ - register8_t CTRLF; /* Control Register F */ - register8_t CTRLG; /* Control Register G */ - register8_t INTCTRL; /* Interrupt Control Register */ - register8_t INTFLAGS; /* Interrupt Flag Register */ - register8_t PLC; /* Peripheral Lenght Control Register */ - register8_t CNTL; /* Counter Register Low */ - register8_t CNTH; /* Counter Register High */ - register8_t CMPL; /* Compare Register Low */ - register8_t CMPH; /* Compare Register High */ - register8_t PERCAPTL; /* Period or Capture Register Low */ - register8_t PERCAPTH; /* Period or Capture Register High */ -} XCL_t; - -/* LUT0 Output Enable */ -typedef enum XCL_LUTOUTEN_enum -{ - XCL_LUTOUTEN_DISABLE_gc = (0x00<<6), /* LUT0 output disabled */ - XCL_LUTOUTEN_PIN0_gc = (0x01<<6), /* LUT0 Output to pin 0 */ - XCL_LUTOUTEN_PIN4_gc = (0x02<<6), /* LUT0 Output to pin 4 */ -} XCL_LUTOUTEN_t; - -/* Port Selection */ -typedef enum XCL_PORTSEL_enum -{ - XCL_PORTSEL_PC_gc = (0x00<<4), /* Port C for LUT or USARTC0 for PEC */ - XCL_PORTSEL_PD_gc = (0x01<<4), /* Port D for LUT or USARTD0 for PEC */ -} XCL_PORTSEL_t; - -/* LUT Configuration */ -typedef enum XCL_LUTCONF_enum -{ - XCL_LUTCONF_2LUT2IN_gc = (0x00<<0), /* 2-Input two LUT */ - XCL_LUTCONF_2LUT1IN_gc = (0x01<<0), /* Two LUT with duplicated input */ - XCL_LUTCONF_2LUT3IN_gc = (0x02<<0), /* Two LUT with one common input */ - XCL_LUTCONF_1LUT3IN_gc = (0x03<<0), /* 3-Input LUT */ - XCL_LUTCONF_MUX_gc = (0x04<<0), /* One LUT Mux */ - XCL_LUTCONF_DLATCH_gc = (0x05<<0), /* One D-Latch LUT */ - XCL_LUTCONF_RSLATCH_gc = (0x06<<0), /* One RS-Latch LUT */ - XCL_LUTCONF_DFF_gc = (0x07<<0), /* One DFF LUT */ -} XCL_LUTCONF_t; - -/* Input Selection */ -typedef enum XCL_INSEL_enum -{ - XCL_INSEL_EVSYS_gc = (0x00<<6), /* Event system selected as source */ - XCL_INSEL_XCL_gc = (0x01<<6), /* XCL selected as source */ - XCL_INSEL_PINL_gc = (0x02<<6), /* LSB port pin selected as source */ - XCL_INSEL_PINH_gc = (0x03<<6), /* MSB port pin selected as source */ -} XCL_INSEL_t; - -/* Delay Configuration on LUT */ -typedef enum XCL_DLYCONF_enum -{ - XCL_DLYCONF_DISABLE_gc = (0x00<<2), /* Delay element disabled */ - XCL_DLYCONF_IN_gc = (0x01<<2), /* Delay enabled on LUT input */ - XCL_DLYCONF_OUT_gc = (0x02<<2), /* Delay enabled on LUT output */ -} XCL_DLYCONF_t; - -/* Delay Selection */ -typedef enum XCL_DLYSEL_enum -{ - XCL_DLYSEL_DLY11_gc = (0x00<<4), /* One cycle delay for each LUT1 and LUT0 */ - XCL_DLYSEL_DLY12_gc = (0x01<<4), /* One cycle delay for LUT1 and two cycles for LUT0 */ - XCL_DLYSEL_DLY21_gc = (0x02<<4), /* Two cycles delay for LUT1 and one cycle for LUT0 */ - XCL_DLYSEL_DLY22_gc = (0x03<<4), /* Two cycle delays for each LUT1 and LUT0 */ -} XCL_DLYSEL_t; - -/* Clock Selection */ -typedef enum XCL_CLKSEL_enum -{ - XCL_CLKSEL_OFF_gc = (0x00<<0), /* OFF */ - XCL_CLKSEL_DIV1_gc = (0x01<<0), /* Prescaler clk */ - XCL_CLKSEL_DIV2_gc = (0x02<<0), /* Prescaler clk/2 */ - XCL_CLKSEL_DIV4_gc = (0x03<<0), /* Prescaler clk/4 */ - XCL_CLKSEL_DIV8_gc = (0x04<<0), /* Prescaler clk/8 */ - XCL_CLKSEL_DIV64_gc = (0x05<<0), /* Prescaler clk/64 */ - XCL_CLKSEL_DIV256_gc = (0x06<<0), /* Prescaler clk/256 */ - XCL_CLKSEL_DIV1024_gc = (0x07<<0), /* Prescaler clk/1024 */ - XCL_CLKSEL_EVCH0_gc = (0x08<<0), /* Event channel 0 */ - XCL_CLKSEL_EVCH1_gc = (0x09<<0), /* Event channel 1 */ - XCL_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event channel 2 */ - XCL_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event channel 3 */ - XCL_CLKSEL_EVCH4_gc = (0x0C<<0), /* Event channel 4 */ - XCL_CLKSEL_EVCH5_gc = (0x0D<<0), /* Event channel 5 */ - XCL_CLKSEL_EVCH6_gc = (0x0E<<0), /* Event channel 6 */ - XCL_CLKSEL_EVCH7_gc = (0x0F<<0), /* Event channel 7 */ -} XCL_CLKSEL_t; - -/* Timer/Counter Command Selection */ -typedef enum XCL_CMDSEL_enum -{ - XCL_CMDSEL_NONE_gc = (0x00<<7), /* None */ - XCL_CMDSEL_RESTART_gc = (0x01<<7), /* Force restart */ -} XCL_CMDSEL_t; - -/* Timer/Counter Selection */ -typedef enum XCL_TCSEL_enum -{ - XCL_TCSEL_TC16_gc = (0x00<<4), /* 16-bit timer/counter */ - XCL_TCSEL_BTC0_gc = (0x01<<4), /* One 8-bit timer/counter */ - XCL_TCSEL_BTC01_gc = (0x02<<4), /* Two 8-bit timer/counters */ - XCL_TCSEL_BTC0PEC1_gc = (0x03<<4), /* One 8-bit timer/counter and one 8-bit peripheral counter */ - XCL_TCSEL_PEC0BTC1_gc = (0x04<<4), /* One 8-bit timer/counter and one 8-bit peripheral counter */ - XCL_TCSEL_PEC01_gc = (0x05<<4), /* Two 8-bit peripheral counters */ - XCL_TCSEL_BTC0PEC2_gc = (0x06<<4), /* One 8-bit timer/counter and two 4-bit peripheral counters */ -} XCL_TCSEL_t; - -/* Timer/Counter Mode */ -typedef enum XCL_TCMODE_enum -{ - XCL_TCMODE_NORMAL_gc = (0x00<<0), /* Normal mode with compare/period */ - XCL_TCMODE_CAPT_gc = (0x01<<0), /* Capture mode */ - XCL_TCMODE_PWM_gc = (0x02<<0), /* Single Slope PWM */ -} XCL_TCMODE_t; - -/* Compare Output Value Timer */ -typedef enum XCL_CMPEN_enum -{ - XCL_CMPEN_CLEAR_gc = (0x00<<5), /* Clear WG Output */ - XCL_CMPEN_SET_gc = (0x01<<5), /* Set WG Output */ -} XCL_CMPEN_t; - -/* Command Enable */ -typedef enum XCL_CMDEN_enum -{ - XCL_CMDEN_DISABLE_gc = (0x00<<6), /* Command Ignored */ - XCL_CMDEN_CMD0_gc = (0x01<<6), /* Command valid for timer/counter 0 */ - XCL_CMDEN_CMD1_gc = (0x02<<6), /* Command valid for timer/counter 1 */ - XCL_CMDEN_CMD01_gc = (0x03<<6), /* Command valid for both timer/counter 0 and 1 */ -} XCL_CMDEN_t; - -/* Timer/Counter Event Source Selection */ -typedef enum XCL_EVSRC_enum -{ - XCL_EVSRC_EVCH0_gc = (0x00<<0), /* Event channel 0 */ - XCL_EVSRC_EVCH1_gc = (0x01<<0), /* Event channel 1 */ - XCL_EVSRC_EVCH2_gc = (0x02<<0), /* Event channel 2 */ - XCL_EVSRC_EVCH3_gc = (0x03<<0), /* Event channel 3 */ - XCL_EVSRC_EVCH4_gc = (0x04<<0), /* Event channel 4 */ - XCL_EVSRC_EVCH5_gc = (0x05<<0), /* Event channel 5 */ - XCL_EVSRC_EVCH6_gc = (0x06<<0), /* Event channel 6 */ - XCL_EVSRC_EVCH7_gc = (0x07<<0), /* Event channel 7 */ -} XCL_EVSRC_t; - -/* Timer/Counter Event Action Selection */ -typedef enum XCL_EVACT_enum -{ - XCL_EVACT_INPUT_gc = (0x00<<5), /* Input Capture */ - XCL_EVACT_FREQ_gc = (0x01<<5), /* Frequency Capture */ - XCL_EVACT_PW_gc = (0x02<<5), /* Pulse Width Capture */ - XCL_EVACT_RESTART_gc = (0x03<<5), /* Restart timer/counter */ -} XCL_EVACT_t; - -/* Underflow Interrupt level */ -typedef enum XCL_UNF_INTLVL_enum -{ - XCL_UNF_INTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ - XCL_UNF_INTLVL_LO_gc = (0x01<<2), /* Low Level */ - XCL_UNF_INTLVL_MED_gc = (0x02<<2), /* Medium Level */ - XCL_UNF_INTLVL_HI_gc = (0x03<<2), /* High Level */ -} XCL_UNF_INTLVL_t; - -/* Compare/Capture Interrupt level */ -typedef enum XCL_CC_INTLVL_enum -{ - XCL_CC_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - XCL_CC_INTLVL_LO_gc = (0x01<<0), /* Low Level */ - XCL_CC_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ - XCL_CC_INTLVL_HI_gc = (0x03<<0), /* High Level */ -} XCL_CC_INTLVL_t; - - -/* --------------------------------------------------------------------------- -TWI - Two-Wire Interface --------------------------------------------------------------------------- -*/ - -/* */ -typedef struct TWI_MASTER_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t CTRLC; /* Control Register C */ - register8_t STATUS; /* Status Register */ - register8_t BAUD; /* Baurd Rate Control Register */ - register8_t ADDR; /* Address Register */ - register8_t DATA; /* Data Register */ -} TWI_MASTER_t; - - -/* */ -typedef struct TWI_SLAVE_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t STATUS; /* Status Register */ - register8_t ADDR; /* Address Register */ - register8_t DATA; /* Data Register */ - register8_t ADDRMASK; /* Address Mask Register */ -} TWI_SLAVE_t; - - -/* */ -typedef struct TWI_TIMEOUT_struct -{ - register8_t TOS; /* Timeout Status Register */ - register8_t TOCONF; /* Timeout Configuration Register */ -} TWI_TIMEOUT_t; - - -/* Two-Wire Interface */ -typedef struct TWI_struct -{ - register8_t CTRL; /* TWI Common Control Register */ - TWI_MASTER_t MASTER; /* TWI master module */ - TWI_SLAVE_t SLAVE; /* TWI slave module */ - TWI_TIMEOUT_t TIMEOUT; /* TWI SMBUS timeout module */ -} TWI_t; - -/* SDA Hold Time */ -typedef enum TWI_SDAHOLD_enum -{ - TWI_SDAHOLD_OFF_gc = (0x00<<4), /* SDA Hold Time off */ - TWI_SDAHOLD_50NS_gc = (0x01<<4), /* SDA Hold Time 50 ns */ - TWI_SDAHOLD_300NS_gc = (0x02<<4), /* SDA Hold Time 300 ns */ - TWI_SDAHOLD_400NS_gc = (0x03<<4), /* SDA Hold Time 400 ns */ -} TWI_SDAHOLD_t; - -/* Master Interrupt Level */ -typedef enum TWI_MASTER_INTLVL_enum -{ - TWI_MASTER_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ - TWI_MASTER_INTLVL_LO_gc = (0x01<<6), /* Low Level */ - TWI_MASTER_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ - TWI_MASTER_INTLVL_HI_gc = (0x03<<6), /* High Level */ -} TWI_MASTER_INTLVL_t; - -/* Inactive Timeout */ -typedef enum TWI_MASTER_TIMEOUT_enum -{ - TWI_MASTER_TIMEOUT_DISABLED_gc = (0x00<<2), /* Bus Timeout Disabled */ - TWI_MASTER_TIMEOUT_50US_gc = (0x01<<2), /* 50 Microseconds */ - TWI_MASTER_TIMEOUT_100US_gc = (0x02<<2), /* 100 Microseconds */ - TWI_MASTER_TIMEOUT_200US_gc = (0x03<<2), /* 200 Microseconds */ -} TWI_MASTER_TIMEOUT_t; - -/* Master Command */ -typedef enum TWI_MASTER_CMD_enum -{ - TWI_MASTER_CMD_NOACT_gc = (0x00<<0), /* No Action */ - TWI_MASTER_CMD_REPSTART_gc = (0x01<<0), /* Issue Repeated Start Condition */ - TWI_MASTER_CMD_RECVTRANS_gc = (0x02<<0), /* Receive or Transmit Data */ - TWI_MASTER_CMD_STOP_gc = (0x03<<0), /* Issue Stop Condition */ -} TWI_MASTER_CMD_t; - -/* Master Bus State */ -typedef enum TWI_MASTER_BUSSTATE_enum -{ - TWI_MASTER_BUSSTATE_UNKNOWN_gc = (0x00<<0), /* Unknown Bus State */ - TWI_MASTER_BUSSTATE_IDLE_gc = (0x01<<0), /* Bus is Idle */ - TWI_MASTER_BUSSTATE_OWNER_gc = (0x02<<0), /* This Module Controls The Bus */ - TWI_MASTER_BUSSTATE_BUSY_gc = (0x03<<0), /* The Bus is Busy */ -} TWI_MASTER_BUSSTATE_t; - -/* Slave Interrupt Level */ -typedef enum TWI_SLAVE_INTLVL_enum -{ - TWI_SLAVE_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ - TWI_SLAVE_INTLVL_LO_gc = (0x01<<6), /* Low Level */ - TWI_SLAVE_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ - TWI_SLAVE_INTLVL_HI_gc = (0x03<<6), /* High Level */ -} TWI_SLAVE_INTLVL_t; - -/* Slave Command */ -typedef enum TWI_SLAVE_CMD_enum -{ - TWI_SLAVE_CMD_NOACT_gc = (0x00<<0), /* No Action */ - TWI_SLAVE_CMD_COMPTRANS_gc = (0x02<<0), /* Used To Complete a Transaction */ - TWI_SLAVE_CMD_RESPONSE_gc = (0x03<<0), /* Used in Response to Address/Data Interrupt */ -} TWI_SLAVE_CMD_t; - -/* Master Timeout */ -typedef enum TWI_MASTER_TTIMEOUT_enum -{ - TWI_MASTER_TTIMEOUT_25MS_gc = (0x00<<0), /* 25 Milliseconds */ - TWI_MASTER_TTIMEOUT_24MS_gc = (0x01<<0), /* 24 Milliseconds */ - TWI_MASTER_TTIMEOUT_23MS_gc = (0x02<<0), /* 23 Milliseconds */ - TWI_MASTER_TTIMEOUT_22MS_gc = (0x03<<0), /* 22 Milliseconds */ - TWI_MASTER_TTIMEOUT_26MS_gc = (0x04<<0), /* 26 Milliseconds */ - TWI_MASTER_TTIMEOUT_27MS_gc = (0x05<<0), /* 27 Milliseconds */ - TWI_MASTER_TTIMEOUT_28MS_gc = (0x06<<0), /* 28 Milliseconds */ - TWI_MASTER_TTIMEOUT_29MS_gc = (0x07<<0), /* 29 Milliseconds */ -} TWI_MASTER_TTIMEOUT_t; - -/* Slave Ttimeout */ -typedef enum TWI_SLAVE_TTIMEOUT_enum -{ - TWI_SLAVE_TTIMEOUT_25MS_gc = (0x00<<5), /* 25 Milliseconds */ - TWI_SLAVE_TTIMEOUT_24MS_gc = (0x01<<5), /* 24 Milliseconds */ - TWI_SLAVE_TTIMEOUT_23MS_gc = (0x02<<5), /* 23 Milliseconds */ - TWI_SLAVE_TTIMEOUT_22MS_gc = (0x03<<5), /* 22 Milliseconds */ - TWI_SLAVE_TTIMEOUT_26MS_gc = (0x04<<5), /* 26 Milliseconds */ - TWI_SLAVE_TTIMEOUT_27MS_gc = (0x05<<5), /* 27 Milliseconds */ - TWI_SLAVE_TTIMEOUT_28MS_gc = (0x06<<5), /* 28 Milliseconds */ - TWI_SLAVE_TTIMEOUT_29MS_gc = (0x07<<5), /* 29 Milliseconds */ -} TWI_SLAVE_TTIMEOUT_t; - -/* Master/Slave Extend Timeout */ -typedef enum TWI_MASTER_TMSEXT_enum -{ - TWI_MASTER_TMSEXT_10MS25MS_gc = (0x00<<3), /* Tmext 10ms Tsext 25ms */ - TWI_MASTER_TMSEXT_9MS24MS_gc = (0x01<<3), /* Tmext 9ms Tsext 24ms */ - TWI_MASTER_TMSEXT_11MS26MS_gc = (0x02<<3), /* Tmext 11ms Tsext 26ms */ - TWI_MASTER_TMSEXT_12MS27MS_gc = (0x03<<3), /* Tmext 12ms Tsext 27ms */ -} TWI_MASTER_TMSEXT_t; - - -/* --------------------------------------------------------------------------- -PORT - Port Configuration --------------------------------------------------------------------------- -*/ - -/* I/O Ports */ -typedef struct PORT_struct -{ - register8_t DIR; /* I/O Port Data Direction */ - register8_t DIRSET; /* I/O Port Data Direction Set */ - register8_t DIRCLR; /* I/O Port Data Direction Clear */ - register8_t DIRTGL; /* I/O Port Data Direction Toggle */ - register8_t OUT; /* I/O Port Output */ - register8_t OUTSET; /* I/O Port Output Set */ - register8_t OUTCLR; /* I/O Port Output Clear */ - register8_t OUTTGL; /* I/O Port Output Toggle */ - register8_t IN; /* I/O port Input */ - register8_t INTCTRL; /* Interrupt Control Register */ - register8_t INTMASK; /* Port Interrupt Mask */ - register8_t reserved_0x0B; - register8_t INTFLAGS; /* Interrupt Flag Register */ - register8_t reserved_0x0D; - register8_t REMAP; /* Pin Remap Register */ - register8_t reserved_0x0F; - register8_t PIN0CTRL; /* Pin 0 Control Register */ - register8_t PIN1CTRL; /* Pin 1 Control Register */ - register8_t PIN2CTRL; /* Pin 2 Control Register */ - register8_t PIN3CTRL; /* Pin 3 Control Register */ - register8_t PIN4CTRL; /* Pin 4 Control Register */ - register8_t PIN5CTRL; /* Pin 5 Control Register */ - register8_t PIN6CTRL; /* Pin 6 Control Register */ - register8_t PIN7CTRL; /* Pin 7 Control Register */ -} PORT_t; - -/* Port Interrupt Level */ -typedef enum PORT_INTLVL_enum -{ - PORT_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - PORT_INTLVL_LO_gc = (0x01<<0), /* Low Level */ - PORT_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ - PORT_INTLVL_HI_gc = (0x03<<0), /* High Level */ -} PORT_INTLVL_t; - -/* Output/Pull Configuration */ -typedef enum PORT_OPC_enum -{ - PORT_OPC_TOTEM_gc = (0x00<<3), /* Totempole */ - PORT_OPC_BUSKEEPER_gc = (0x01<<3), /* Totempole w/ Bus keeper on Input and Output */ - PORT_OPC_PULLDOWN_gc = (0x02<<3), /* Totempole w/ Pull-down on Input */ - PORT_OPC_PULLUP_gc = (0x03<<3), /* Totempole w/ Pull-up on Input */ - PORT_OPC_WIREDOR_gc = (0x04<<3), /* Wired OR */ - PORT_OPC_WIREDAND_gc = (0x05<<3), /* Wired AND */ - PORT_OPC_WIREDORPULL_gc = (0x06<<3), /* Wired OR w/ Pull-down */ - PORT_OPC_WIREDANDPULL_gc = (0x07<<3), /* Wired AND w/ Pull-up */ -} PORT_OPC_t; - -/* Input/Sense Configuration */ -typedef enum PORT_ISC_enum -{ - PORT_ISC_BOTHEDGES_gc = (0x00<<0), /* Sense Both Edges */ - PORT_ISC_RISING_gc = (0x01<<0), /* Sense Rising Edge */ - PORT_ISC_FALLING_gc = (0x02<<0), /* Sense Falling Edge */ - PORT_ISC_LEVEL_gc = (0x03<<0), /* Sense Level (Transparent For Events) */ - PORT_ISC_FORCE_ENABLE_gc = (0x06<<0), /* Digital Input Buffer Forced Enable */ - PORT_ISC_INPUT_DISABLE_gc = (0x07<<0), /* Disable Digital Input Buffer */ -} PORT_ISC_t; - - -/* --------------------------------------------------------------------------- -TC - 16-bit Timer/Counter With PWM --------------------------------------------------------------------------- -*/ - -/* 16-bit Timer/Counter 4 */ -typedef struct TC4_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t CTRLC; /* Control register C */ - register8_t CTRLD; /* Control Register D */ - register8_t CTRLE; /* Control Register E */ - register8_t CTRLF; /* Control Register F */ - register8_t INTCTRLA; /* Interrupt Control Register A */ - register8_t INTCTRLB; /* Interrupt Control Register B */ - register8_t CTRLGCLR; /* Control Register G Clear */ - register8_t CTRLGSET; /* Control Register G Set */ - register8_t CTRLHCLR; /* Control Register H Clear */ - register8_t CTRLHSET; /* Control Register H Set */ - register8_t INTFLAGS; /* Interrupt Flag Register */ - register8_t reserved_0x0D; - register8_t reserved_0x0E; - register8_t TEMP; /* Temporary Register For 16-bit Access */ - register8_t reserved_0x10; - register8_t reserved_0x11; - register8_t reserved_0x12; - register8_t reserved_0x13; - register8_t reserved_0x14; - register8_t reserved_0x15; - register8_t reserved_0x16; - register8_t reserved_0x17; - register8_t reserved_0x18; - register8_t reserved_0x19; - register8_t reserved_0x1A; - register8_t reserved_0x1B; - register8_t reserved_0x1C; - register8_t reserved_0x1D; - register8_t reserved_0x1E; - register8_t reserved_0x1F; - _WORDREGISTER(CNT); /* Count */ - register8_t reserved_0x22; - register8_t reserved_0x23; - register8_t reserved_0x24; - register8_t reserved_0x25; - _WORDREGISTER(PER); /* Period */ - _WORDREGISTER(CCA); /* Compare or Capture A */ - _WORDREGISTER(CCB); /* Compare or Capture B */ - _WORDREGISTER(CCC); /* Compare or Capture C */ - _WORDREGISTER(CCD); /* Compare or Capture D */ - register8_t reserved_0x30; - register8_t reserved_0x31; - register8_t reserved_0x32; - register8_t reserved_0x33; - register8_t reserved_0x34; - register8_t reserved_0x35; - _WORDREGISTER(PERBUF); /* Period Buffer */ - _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ - _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ - _WORDREGISTER(CCCBUF); /* Compare Or Capture C Buffer */ - _WORDREGISTER(CCDBUF); /* Compare Or Capture D Buffer */ -} TC4_t; - - -/* 16-bit Timer/Counter 5 */ -typedef struct TC5_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t CTRLC; /* Control register C */ - register8_t CTRLD; /* Control Register D */ - register8_t CTRLE; /* Control Register E */ - register8_t CTRLF; /* Control Register F */ - register8_t INTCTRLA; /* Interrupt Control Register A */ - register8_t INTCTRLB; /* Interrupt Control Register B */ - register8_t CTRLGCLR; /* Control Register G Clear */ - register8_t CTRLGSET; /* Control Register G Set */ - register8_t CTRLHCLR; /* Control Register H Clear */ - register8_t CTRLHSET; /* Control Register H Set */ - register8_t INTFLAGS; /* Interrupt Flag Register */ - register8_t reserved_0x0D; - register8_t reserved_0x0E; - register8_t TEMP; /* Temporary Register For 16-bit Access */ - register8_t reserved_0x10; - register8_t reserved_0x11; - register8_t reserved_0x12; - register8_t reserved_0x13; - register8_t reserved_0x14; - register8_t reserved_0x15; - register8_t reserved_0x16; - register8_t reserved_0x17; - register8_t reserved_0x18; - register8_t reserved_0x19; - register8_t reserved_0x1A; - register8_t reserved_0x1B; - register8_t reserved_0x1C; - register8_t reserved_0x1D; - register8_t reserved_0x1E; - register8_t reserved_0x1F; - _WORDREGISTER(CNT); /* Count */ - register8_t reserved_0x22; - register8_t reserved_0x23; - register8_t reserved_0x24; - register8_t reserved_0x25; - _WORDREGISTER(PER); /* Period */ - _WORDREGISTER(CCA); /* Compare or Capture A */ - _WORDREGISTER(CCB); /* Compare or Capture B */ - register8_t reserved_0x2C; - register8_t reserved_0x2D; - register8_t reserved_0x2E; - register8_t reserved_0x2F; - register8_t reserved_0x30; - register8_t reserved_0x31; - register8_t reserved_0x32; - register8_t reserved_0x33; - register8_t reserved_0x34; - register8_t reserved_0x35; - _WORDREGISTER(PERBUF); /* Period Buffer */ - _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ - _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ - register8_t reserved_0x3C; - register8_t reserved_0x3D; - register8_t reserved_0x3E; - register8_t reserved_0x3F; -} TC5_t; - -/* Clock Selection */ -typedef enum TC45_CLKSEL_enum -{ - TC45_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */ - TC45_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */ - TC45_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */ - TC45_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */ - TC45_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */ - TC45_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */ - TC45_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */ - TC45_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */ - TC45_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */ - TC45_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */ - TC45_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */ - TC45_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */ - TC45_CLKSEL_EVCH4_gc = (0x0C<<0), /* Event Channel 4 */ - TC45_CLKSEL_EVCH5_gc = (0x0D<<0), /* Event Channel 5 */ - TC45_CLKSEL_EVCH6_gc = (0x0E<<0), /* Event Channel 6 */ - TC45_CLKSEL_EVCH7_gc = (0x0F<<0), /* Event Channel 7 */ -} TC45_CLKSEL_t; - -/* Byte Mode */ -typedef enum TC45_BYTEM_enum -{ - TC45_BYTEM_NORMAL_gc = (0x00<<6), /* 16-bit mode */ - TC45_BYTEM_BYTEMODE_gc = (0x01<<6), /* Timer/Counter Operating in Byte Mode Only */ -} TC45_BYTEM_t; - -/* Circular Enable Mode */ -typedef enum TC45_CIRCEN_enum -{ - TC45_CIRCEN_DISABLE_gc = (0x00<<4), /* Circular Buffer Disabled */ - TC45_CIRCEN_PER_gc = (0x01<<4), /* Circular Buffer Enabled on PER/PERBUF */ - TC45_CIRCEN_CCA_gc = (0x02<<4), /* Circular Buffer Enabled on CCA/CCABUF */ - TC45_CIRCEN_BOTH_gc = (0x03<<4), /* Circular Buffer Enabled on All Buffered Registers */ -} TC45_CIRCEN_t; - -/* Waveform Generation Mode */ -typedef enum TC45_WGMODE_enum -{ - TC45_WGMODE_NORMAL_gc = (0x00<<0), /* Normal Mode */ - TC45_WGMODE_FRQ_gc = (0x01<<0), /* Frequency Generation Mode */ - TC45_WGMODE_SINGLESLOPE_gc = (0x03<<0), /* Single Slope */ - TC45_WGMODE_DSTOP_gc = (0x05<<0), /* Dual Slope, Update on TOP */ - TC45_WGMODE_DSBOTH_gc = (0x06<<0), /* Dual Slope, Both */ - TC45_WGMODE_DSBOTTOM_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */ -} TC45_WGMODE_t; - -/* Event Action */ -typedef enum TC45_EVACT_enum -{ - TC45_EVACT_OFF_gc = (0x00<<5), /* No Event Action */ - TC45_EVACT_FMODE1_gc = (0x01<<5), /* Fault Mode 1 capture */ - TC45_EVACT_FMODE2_gc = (0x02<<5), /* Fault Mode 2 capture */ - TC45_EVACT_UPDOWN_gc = (0x03<<5), /* Up/down count */ - TC45_EVACT_QDEC_gc = (0x04<<5), /* Quadrature decode */ - TC45_EVACT_RESTART_gc = (0x05<<5), /* Restart */ - TC45_EVACT_PWF_gc = (0x06<<5), /* Pulse-width Capture */ -} TC45_EVACT_t; - -/* Event Selection */ -typedef enum TC45_EVSEL_enum -{ - TC45_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ - TC45_EVSEL_CH0_gc = (0x08<<0), /* Event Channel 0 */ - TC45_EVSEL_CH1_gc = (0x09<<0), /* Event Channel 1 */ - TC45_EVSEL_CH2_gc = (0x0A<<0), /* Event Channel 2 */ - TC45_EVSEL_CH3_gc = (0x0B<<0), /* Event Channel 3 */ - TC45_EVSEL_CH4_gc = (0x0C<<0), /* Event Channel 4 */ - TC45_EVSEL_CH5_gc = (0x0D<<0), /* Event Channel 5 */ - TC45_EVSEL_CH6_gc = (0x0E<<0), /* Event Channel 6 */ - TC45_EVSEL_CH7_gc = (0x0F<<0), /* Event Channel 7 */ -} TC45_EVSEL_t; - -/* Compare or Capture Channel A Mode */ -typedef enum TC45_CCAMODE_enum -{ - TC45_CCAMODE_DISABLE_gc = (0x00<<0), /* Channel Disabled */ - TC45_CCAMODE_COMP_gc = (0x01<<0), /* Ouput Compare enabled */ - TC45_CCAMODE_CAPT_gc = (0x02<<0), /* Input Capture enabled */ - TC45_CCAMODE_BOTHCC_gc = (0x03<<0), /* Both Compare and Capture enabled */ -} TC45_CCAMODE_t; - -/* Compare or Capture Channel B Mode */ -typedef enum TC45_CCBMODE_enum -{ - TC45_CCBMODE_DISABLE_gc = (0x00<<2), /* Channel Disabled */ - TC45_CCBMODE_COMP_gc = (0x01<<2), /* Ouput Compare enabled */ - TC45_CCBMODE_CAPT_gc = (0x02<<2), /* Input Capture enabled */ - TC45_CCBMODE_BOTHCC_gc = (0x03<<2), /* Both Compare and Capture enabled */ -} TC45_CCBMODE_t; - -/* Compare or Capture Channel C Mode */ -typedef enum TC45_CCCMODE_enum -{ - TC45_CCCMODE_DISABLE_gc = (0x00<<4), /* Channel Disabled */ - TC45_CCCMODE_COMP_gc = (0x01<<4), /* Ouput Compare enabled */ - TC45_CCCMODE_CAPT_gc = (0x02<<4), /* Input Capture enabled */ - TC45_CCCMODE_BOTHCC_gc = (0x03<<4), /* Both Compare and Capture enabled */ -} TC45_CCCMODE_t; - -/* Compare or Capture Channel D Mode */ -typedef enum TC45_CCDMODE_enum -{ - TC45_CCDMODE_DISABLE_gc = (0x00<<6), /* Channel Disabled */ - TC45_CCDMODE_COMP_gc = (0x01<<6), /* Ouput Compare enabled */ - TC45_CCDMODE_CAPT_gc = (0x02<<6), /* Input Capture enabled */ - TC45_CCDMODE_BOTHCC_gc = (0x03<<6), /* Both Compare and Capture enabled */ -} TC45_CCDMODE_t; - -/* Compare or Capture Low Channel A Mode */ -typedef enum TC45_LCCAMODE_enum -{ - TC45_LCCAMODE_DISABLE_gc = (0x00<<0), /* Channel Disabled */ - TC45_LCCAMODE_COMP_gc = (0x01<<0), /* Ouput Compare enabled */ - TC45_LCCAMODE_CAPT_gc = (0x02<<0), /* Input Capture enabled */ - TC45_LCCAMODE_BOTHCC_gc = (0x03<<0), /* Both Compare and Capture enabled */ -} TC45_LCCAMODE_t; - -/* Compare or Capture Low Channel B Mode */ -typedef enum TC45_LCCBMODE_enum -{ - TC45_LCCBMODE_DISABLE_gc = (0x00<<2), /* Channel Disabled */ - TC45_LCCBMODE_COMP_gc = (0x01<<2), /* Ouput Compare enabled */ - TC45_LCCBMODE_CAPT_gc = (0x02<<2), /* Input Capture enabled */ - TC45_LCCBMODE_BOTHCC_gc = (0x03<<2), /* Both Compare and Capture enabled */ -} TC45_LCCBMODE_t; - -/* Compare or Capture Low Channel C Mode */ -typedef enum TC45_LCCCMODE_enum -{ - TC45_LCCCMODE_DISABLE_gc = (0x00<<4), /* Channel Disabled */ - TC45_LCCCMODE_COMP_gc = (0x01<<4), /* Ouput Compare enabled */ - TC45_LCCCMODE_CAPT_gc = (0x02<<4), /* Input Capture enabled */ - TC45_LCCCMODE_BOTHCC_gc = (0x03<<4), /* Both Compare and Capture enabled */ -} TC45_LCCCMODE_t; - -/* Compare or Capture Low Channel D Mode */ -typedef enum TC45_LCCDMODE_enum -{ - TC45_LCCDMODE_DISABLE_gc = (0x00<<6), /* Channel Disabled */ - TC45_LCCDMODE_COMP_gc = (0x01<<6), /* Ouput Compare enabled */ - TC45_LCCDMODE_CAPT_gc = (0x02<<6), /* Input Capture enabled */ - TC45_LCCDMODE_BOTHCC_gc = (0x03<<6), /* Both Compare and Capture enabled */ -} TC45_LCCDMODE_t; - -/* Compare or Capture High Channel A Mode */ -typedef enum TC45_HCCAMODE_enum -{ - TC45_HCCAMODE_DISABLE_gc = (0x00<<0), /* Channel Disabled */ - TC45_HCCAMODE_COMP_gc = (0x01<<0), /* Ouput Compare enabled */ - TC45_HCCAMODE_CAPT_gc = (0x02<<0), /* Input Capture enabled */ - TC45_HCCAMODE_BOTHCC_gc = (0x03<<0), /* Both Compare and Capture enabled */ -} TC45_HCCAMODE_t; - -/* Compare or Capture High Channel B Mode */ -typedef enum TC45_HCCBMODE_enum -{ - TC45_HCCBMODE_DISABLE_gc = (0x00<<2), /* Channel Disabled */ - TC45_HCCBMODE_COMP_gc = (0x01<<2), /* Ouput Compare enabled */ - TC45_HCCBMODE_CAPT_gc = (0x02<<2), /* Input Capture enabled */ - TC45_HCCBMODE_BOTHCC_gc = (0x03<<2), /* Both Compare and Capture enabled */ -} TC45_HCCBMODE_t; - -/* Compare or Capture High Channel C Mode */ -typedef enum TC45_HCCCMODE_enum -{ - TC45_HCCCMODE_DISABLE_gc = (0x00<<4), /* Channel Disabled */ - TC45_HCCCMODE_COMP_gc = (0x01<<4), /* Ouput Compare enabled */ - TC45_HCCCMODE_CAPT_gc = (0x02<<4), /* Input Capture enabled */ - TC45_HCCCMODE_BOTHCC_gc = (0x03<<4), /* Both Compare and Capture enabled */ -} TC45_HCCCMODE_t; - -/* Compare or Capture High Channel D Mode */ -typedef enum TC45_HCCDMODE_enum -{ - TC45_HCCDMODE_DISABLE_gc = (0x00<<6), /* Channel Disabled */ - TC45_HCCDMODE_COMP_gc = (0x01<<6), /* Ouput Compare enabled */ - TC45_HCCDMODE_CAPT_gc = (0x02<<6), /* Input Capture enabled */ - TC45_HCCDMODE_BOTHCC_gc = (0x03<<6), /* Both Compare and Capture enabled */ -} TC45_HCCDMODE_t; - -/* Timer Trigger Restart Interrupt Level */ -typedef enum TC45_TRGINTLVL_enum -{ - TC45_TRGINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ - TC45_TRGINTLVL_LO_gc = (0x01<<4), /* Low Level */ - TC45_TRGINTLVL_MED_gc = (0x02<<4), /* Medium Level */ - TC45_TRGINTLVL_HI_gc = (0x03<<4), /* High Level */ -} TC45_TRGINTLVL_t; - -/* Error Interrupt Level */ -typedef enum TC45_ERRINTLVL_enum -{ - TC45_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ - TC45_ERRINTLVL_LO_gc = (0x01<<2), /* Low Level */ - TC45_ERRINTLVL_MED_gc = (0x02<<2), /* Medium Level */ - TC45_ERRINTLVL_HI_gc = (0x03<<2), /* High Level */ -} TC45_ERRINTLVL_t; - -/* Overflow Interrupt Level */ -typedef enum TC45_OVFINTLVL_enum -{ - TC45_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - TC45_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ - TC45_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ - TC45_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ -} TC45_OVFINTLVL_t; - -/* Compare or Capture Channel A Interrupt Level */ -typedef enum TC45_CCAINTLVL_enum -{ - TC45_CCAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - TC45_CCAINTLVL_LO_gc = (0x01<<0), /* Low Level */ - TC45_CCAINTLVL_MED_gc = (0x02<<0), /* Medium Level */ - TC45_CCAINTLVL_HI_gc = (0x03<<0), /* High Level */ -} TC45_CCAINTLVL_t; - -/* Compare or Capture Channel B Interrupt Level */ -typedef enum TC45_CCBINTLVL_enum -{ - TC45_CCBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ - TC45_CCBINTLVL_LO_gc = (0x01<<2), /* Low Level */ - TC45_CCBINTLVL_MED_gc = (0x02<<2), /* Medium Level */ - TC45_CCBINTLVL_HI_gc = (0x03<<2), /* High Level */ -} TC45_CCBINTLVL_t; - -/* Compare or Capture Channel C Interrupt Level */ -typedef enum TC45_CCCINTLVL_enum -{ - TC45_CCCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ - TC45_CCCINTLVL_LO_gc = (0x01<<4), /* Low Level */ - TC45_CCCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ - TC45_CCCINTLVL_HI_gc = (0x03<<4), /* High Level */ -} TC45_CCCINTLVL_t; - -/* Compare or Capture Channel D Interrupt Level */ -typedef enum TC45_CCDINTLVL_enum -{ - TC45_CCDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ - TC45_CCDINTLVL_LO_gc = (0x01<<6), /* Low Level */ - TC45_CCDINTLVL_MED_gc = (0x02<<6), /* Medium Level */ - TC45_CCDINTLVL_HI_gc = (0x03<<6), /* High Level */ -} TC45_CCDINTLVL_t; - -/* Compare or Capture Low Channel A Interrupt Level */ -typedef enum TC45_LCCAINTLVL_enum -{ - TC45_LCCAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - TC45_LCCAINTLVL_LO_gc = (0x01<<0), /* Low Level */ - TC45_LCCAINTLVL_MED_gc = (0x02<<0), /* Medium Level */ - TC45_LCCAINTLVL_HI_gc = (0x03<<0), /* High Level */ -} TC45_LCCAINTLVL_t; - -/* Compare or Capture Low Channel B Interrupt Level */ -typedef enum TC45_LCCBINTLVL_enum -{ - TC45_LCCBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ - TC45_LCCBINTLVL_LO_gc = (0x01<<2), /* Low Level */ - TC45_LCCBINTLVL_MED_gc = (0x02<<2), /* Medium Level */ - TC45_LCCBINTLVL_HI_gc = (0x03<<2), /* High Level */ -} TC45_LCCBINTLVL_t; - -/* Compare or Capture Low Channel C Interrupt Level */ -typedef enum TC45_LCCCINTLVL_enum -{ - TC45_LCCCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ - TC45_LCCCINTLVL_LO_gc = (0x01<<4), /* Low Level */ - TC45_LCCCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ - TC45_LCCCINTLVL_HI_gc = (0x03<<4), /* High Level */ -} TC45_LCCCINTLVL_t; - -/* Compare or Capture Low Channel D Interrupt Level */ -typedef enum TC45_LCCDINTLVL_enum -{ - TC45_LCCDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ - TC45_LCCDINTLVL_LO_gc = (0x01<<6), /* Low Level */ - TC45_LCCDINTLVL_MED_gc = (0x02<<6), /* Medium Level */ - TC45_LCCDINTLVL_HI_gc = (0x03<<6), /* High Level */ -} TC45_LCCDINTLVL_t; - -/* Timer/Counter Command */ -typedef enum TC45_CMD_enum -{ - TC45_CMD_NONE_gc = (0x00<<2), /* No Command */ - TC45_CMD_UPDATE_gc = (0x01<<2), /* Force Update */ - TC45_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ - TC45_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ -} TC45_CMD_t; - - -/* --------------------------------------------------------------------------- -FAULT - Fault Extension --------------------------------------------------------------------------- -*/ - -/* Fault Extension */ -typedef struct FAULT_struct -{ - register8_t CTRLA; /* Control A Register */ - register8_t CTRLB; /* Control B Register */ - register8_t CTRLC; /* Control C Register */ - register8_t CTRLD; /* Control D Register */ - register8_t CTRLE; /* Control E Register */ - register8_t STATUS; /* Status Register */ - register8_t CTRLGCLR; /* Control Register G Clear */ - register8_t CTRLGSET; /* Control Register G set */ -} FAULT_t; - -/* Ramp Mode Selection */ -typedef enum FAULT_RAMP_enum -{ - FAULT_RAMP_RAMP1_gc = (0x00<<6), /* Normal Mode */ - FAULT_RAMP_RAMP2_gc = (0x02<<6), /* RAMP2 Mode */ -} FAULT_RAMP_t; - -/* Fault E Input Source Selection */ -typedef enum FAULT_SRCE_enum -{ - FAULT_SRCE_DISABLE_gc = (0x00<<0), /* Fault Protection Disabled */ - FAULT_SRCE_CHN_gc = (0x01<<0), /* Event Channel n */ - FAULT_SRCE_CHN1_gc = (0x02<<0), /* Event Channel n+1 */ - FAULT_SRCE_CHN2_gc = (0x03<<0), /* Event Channel n+2 */ -} FAULT_SRCE_t; - -/* Fault A Halt Action Selection */ -typedef enum FAULT_HALTA_enum -{ - FAULT_HALTA_DISABLE_gc = (0x00<<5), /* Halt Action Disabled */ - FAULT_HALTA_HW_gc = (0x01<<5), /* Hardware Halt Action */ - FAULT_HALTA_SW_gc = (0x02<<5), /* Software Halt Action */ -} FAULT_HALTA_t; - -/* Fault A Source Selection */ -typedef enum FAULT_SRCA_enum -{ - FAULT_SRCA_DISABLE_gc = (0x00<<0), /* Fault A Disabled */ - FAULT_SRCA_CHN_gc = (0x01<<0), /* Event Channel n */ - FAULT_SRCA_CHN1_gc = (0x02<<0), /* Event Channel n+1 */ - FAULT_SRCA_LINK_gc = (0x03<<0), /* Fault A linked to Fault B State from previous cycle */ -} FAULT_SRCA_t; - -/* Fault B Halt Action Selection */ -typedef enum FAULT_HALTB_enum -{ - FAULT_HALTB_DISABLE_gc = (0x00<<5), /* Halt Action Disabled */ - FAULT_HALTB_HW_gc = (0x01<<5), /* Hardware Halt Action */ - FAULT_HALTB_SW_gc = (0x02<<5), /* Software Halt Action */ -} FAULT_HALTB_t; - -/* Fault B Source Selection */ -typedef enum FAULT_SRCB_enum -{ - FAULT_SRCB_DISABLE_gc = (0x00<<0), /* Fault B disabled */ - FAULT_SRCB_CHN_gc = (0x01<<0), /* Event Channel n */ - FAULT_SRCB_CHN1_gc = (0x02<<0), /* Event Channel n+1 */ - FAULT_SRCB_LINK_gc = (0x03<<0), /* Fault B linked to Fault A State from previous cycle */ -} FAULT_SRCB_t; - -/* Channel index Command */ -typedef enum FAULT_IDXCMD_enum -{ - FAULT_IDXCMD_DISABLE_gc = (0x00<<3), /* Command Disabled */ - FAULT_IDXCMD_SET_gc = (0x01<<3), /* Force Cycle B in Next Cycle */ - FAULT_IDXCMD_CLEAR_gc = (0x02<<3), /* Force Cycle A in Next Cycle */ - FAULT_IDXCMD_HOLD_gc = (0x03<<3), /* Hold Current Cycle Index in Next Cycle */ -} FAULT_IDXCMD_t; - - -/* --------------------------------------------------------------------------- -WEX - Waveform Extension --------------------------------------------------------------------------- -*/ - -/* Waveform Extension */ -typedef struct WEX_struct -{ - register8_t CTRL; /* Control Register */ - register8_t DTBOTH; /* Dead-time Concurrent Write to Both Sides Register */ - register8_t DTLS; /* Dead-time Low Side Register */ - register8_t DTHS; /* Dead-time High Side Register */ - register8_t STATUSCLR; /* Status Clear Register */ - register8_t STATUSSET; /* Status Set Register */ - register8_t SWAP; /* Swap Register */ - register8_t PGO; /* Pattern Generation Override Register */ - register8_t PGV; /* Pattern Generation Value Register */ - register8_t reserved_0x09; - register8_t SWAPBUF; /* Dead Time Low Side Buffer */ - register8_t PGOBUF; /* Pattern Generation Overwrite Buffer Register */ - register8_t PGVBUF; /* Pattern Generation Value Buffer Register */ - register8_t reserved_0x0D; - register8_t reserved_0x0E; - register8_t OUTOVDIS; /* Output Override Disable Register */ -} WEX_t; - -/* Output Matrix Mode */ -typedef enum WEX_OTMX_enum -{ - WEX_OTMX_DEFAULT_gc = (0x00<<4), /* Default Ouput Matrix Mode */ - WEX_OTMX_FIRST_gc = (0x01<<4), /* First Output matrix Mode */ - WEX_OTMX_SECOND_gc = (0x02<<4), /* Second Output matrix Mode */ - WEX_OTMX_THIRD_gc = (0x03<<4), /* Third Output matrix Mode */ - WEX_OTMX_FOURTH_gc = (0x04<<4), /* Fourth Output matrix Mode */ -} WEX_OTMX_t; - - -/* --------------------------------------------------------------------------- -HIRES - High-Resolution Extension --------------------------------------------------------------------------- -*/ - -/* High-Resolution Extension */ -typedef struct HIRES_struct -{ - register8_t CTRLA; /* Control Register A */ -} HIRES_t; - -/* High Resolution Plus Mode */ -typedef enum HIRES_HRPLUS_enum -{ - HIRES_HRPLUS_NONE_gc = (0x00<<2), /* No Hi-Res Plus */ - HIRES_HRPLUS_HRP4_gc = (0x01<<2), /* Hi-Res Plus enabled on Timer 4 */ - HIRES_HRPLUS_HRP5_gc = (0x02<<2), /* Hi-Res Plus enabled on Timer 5 */ - HIRES_HRPLUS_BOTH_gc = (0x03<<2), /* Hi-Res Plus enabled on Timer 4 and 5 */ -} HIRES_HRPLUS_t; - -/* High Resolution Mode */ -typedef enum HIRES_HREN_enum -{ - HIRES_HREN_NONE_gc = (0x00<<0), /* No Hi-Res */ - HIRES_HREN_HRP4_gc = (0x01<<0), /* Hi-Res enabled on Timer 4 */ - HIRES_HREN_HRP5_gc = (0x02<<0), /* Hi-Res enabled on Timer 5 */ - HIRES_HREN_BOTH_gc = (0x03<<0), /* Hi-Res enabled on Timer 4 and 5 */ -} HIRES_HREN_t; - - -/* --------------------------------------------------------------------------- -USART - Universal Asynchronous Receiver-Transmitter --------------------------------------------------------------------------- -*/ - -/* Universal Synchronous/Asynchronous Receiver/Transmitter */ -typedef struct USART_struct -{ - register8_t DATA; /* Data Register */ - register8_t STATUS; /* Status Register */ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t CTRLC; /* Control Register C */ - register8_t CTRLD; /* Control Register D */ - register8_t BAUDCTRLA; /* Baud Rate Control Register A */ - register8_t BAUDCTRLB; /* Baud Rate Control Register B */ -} USART_t; - -/* Receive Start Interrupt level */ -typedef enum USART_RXSINTLVL_enum -{ - USART_RXSINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - USART_RXSINTLVL_LO_gc = (0x01<<0), /* Low Level */ - USART_RXSINTLVL_MED_gc = (0x02<<0), /* Medium Level */ - USART_RXSINTLVL_HI_gc = (0x03<<0), /* High Level */ -} USART_RXSINTLVL_t; - -/* Receive Complete Interrupt level */ -typedef enum USART_RXCINTLVL_enum -{ - USART_RXCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ - USART_RXCINTLVL_LO_gc = (0x01<<4), /* Low Level */ - USART_RXCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ - USART_RXCINTLVL_HI_gc = (0x03<<4), /* High Level */ -} USART_RXCINTLVL_t; - -/* Transmit Complete Interrupt level */ -typedef enum USART_TXCINTLVL_enum -{ - USART_TXCINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ - USART_TXCINTLVL_LO_gc = (0x01<<2), /* Low Level */ - USART_TXCINTLVL_MED_gc = (0x02<<2), /* Medium Level */ - USART_TXCINTLVL_HI_gc = (0x03<<2), /* High Level */ -} USART_TXCINTLVL_t; - -/* Data Register Empty Interrupt level */ -typedef enum USART_DREINTLVL_enum -{ - USART_DREINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - USART_DREINTLVL_LO_gc = (0x01<<0), /* Low Level */ - USART_DREINTLVL_MED_gc = (0x02<<0), /* Medium Level */ - USART_DREINTLVL_HI_gc = (0x03<<0), /* High Level */ -} USART_DREINTLVL_t; - -/* Character Size */ -typedef enum USART_CHSIZE_enum -{ - USART_CHSIZE_5BIT_gc = (0x00<<0), /* Character size: 5 bit */ - USART_CHSIZE_6BIT_gc = (0x01<<0), /* Character size: 6 bit */ - USART_CHSIZE_7BIT_gc = (0x02<<0), /* Character size: 7 bit */ - USART_CHSIZE_8BIT_gc = (0x03<<0), /* Character size: 8 bit */ - USART_CHSIZE_9BIT_gc = (0x07<<0), /* Character size: 9 bit */ -} USART_CHSIZE_t; - -/* Communication Mode */ -typedef enum USART_CMODE_enum -{ - USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6), /* Asynchronous Mode */ - USART_CMODE_SYNCHRONOUS_gc = (0x01<<6), /* Synchronous Mode */ - USART_CMODE_IRDA_gc = (0x02<<6), /* IrDA Mode */ - USART_CMODE_MSPI_gc = (0x03<<6), /* Master SPI Mode */ -} USART_CMODE_t; - -/* Parity Mode */ -typedef enum USART_PMODE_enum -{ - USART_PMODE_DISABLED_gc = (0x00<<4), /* No Parity */ - USART_PMODE_EVEN_gc = (0x02<<4), /* Even Parity */ - USART_PMODE_ODD_gc = (0x03<<4), /* Odd Parity */ -} USART_PMODE_t; - -/* Encoding and Decoding Type */ -typedef enum USART_DECTYPE_enum -{ - USART_DECTYPE_DATA_gc = (0x00<<4), /* DATA Field Encoding */ - USART_DECTYPE_SDATA_gc = (0x02<<4), /* Start and Data Fields Encoding */ - USART_DECTYPE_NOTSDATA_gc = (0x03<<4), /* Start and Data Fields Encoding, with invertion in START field */ -} USART_DECTYPE_t; - -/* XCL LUT Action */ -typedef enum USART_LUTACT_enum -{ - USART_LUTACT_OFF_gc = (0x00<<2), /* Standard Frame Configuration */ - USART_LUTACT_RX_gc = (0x01<<2), /* Receiver Decoding Enabled */ - USART_LUTACT_TX_gc = (0x02<<2), /* Transmitter Encoding Enabled */ - USART_LUTACT_BOTH_gc = (0x03<<2), /* Both Encoding and Decoding Enabled */ -} USART_LUTACT_t; - -/* XCL Peripheral Counter Action */ -typedef enum USART_PECACT_enum -{ - USART_PECACT_OFF_gc = (0x00<<0), /* Standard Mode */ - USART_PECACT_PEC0_gc = (0x01<<0), /* Variable Data Lenght in Reception */ - USART_PECACT_PEC1_gc = (0x02<<0), /* Variable Data Lenght in Transmission */ - USART_PECACT_PERC01_gc = (0x03<<0), /* Variable Data Lenght in both Reception and Transmission */ -} USART_PECACT_t; - - -/* --------------------------------------------------------------------------- -SPI - Serial Peripheral Interface --------------------------------------------------------------------------- -*/ - -/* Serial Peripheral Interface with Buffer Modes */ -typedef struct SPI_struct -{ - register8_t CTRL; /* Control Register */ - register8_t INTCTRL; /* Interrupt Control Register */ - register8_t STATUS; /* Status Register */ - register8_t DATA; /* Data Register */ - register8_t CTRLB; /* Control Register B */ -} SPI_t; - -/* SPI Mode */ -typedef enum SPI_MODE_enum -{ - SPI_MODE_0_gc = (0x00<<2), /* SPI Mode 0, base clock at "0", sampling on leading edge (rising) & set-up on trailling edge (falling). */ - SPI_MODE_1_gc = (0x01<<2), /* SPI Mode 1, base clock at "0", set-up on leading edge (rising) & sampling on trailling edge (falling). */ - SPI_MODE_2_gc = (0x02<<2), /* SPI Mode 2, base clock at "1", sampling on leading edge (falling) & set-up on trailling edge (rising). */ - SPI_MODE_3_gc = (0x03<<2), /* SPI Mode 3, base clock at "1", set-up on leading edge (falling) & sampling on trailling edge (rising). */ -} SPI_MODE_t; - -/* Prescaler setting */ -typedef enum SPI_PRESCALER_enum -{ - SPI_PRESCALER_DIV4_gc = (0x00<<0), /* If CLK2X=1 CLKper/2, else (CLK2X=0) CLKper/4. */ - SPI_PRESCALER_DIV16_gc = (0x01<<0), /* If CLK2X=1 CLKper/8, else (CLK2X=0) CLKper/16. */ - SPI_PRESCALER_DIV64_gc = (0x02<<0), /* If CLK2X=1 CLKper/32, else (CLK2X=0) CLKper/64. */ - SPI_PRESCALER_DIV128_gc = (0x03<<0), /* If CLK2X=1 CLKper/64, else (CLK2X=0) CLKper/128. */ -} SPI_PRESCALER_t; - -/* Interrupt level */ -typedef enum SPI_INTLVL_enum -{ - SPI_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - SPI_INTLVL_LO_gc = (0x01<<0), /* Low Level */ - SPI_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ - SPI_INTLVL_HI_gc = (0x03<<0), /* High Level */ -} SPI_INTLVL_t; - -/* Buffer Modes */ -typedef enum SPI_BUFMODE_enum -{ - SPI_BUFMODE_OFF_gc = (0x00<<6), /* SPI Unbuffered Mode */ - SPI_BUFMODE_BUFMODE1_gc = (0x02<<6), /* Buffer Mode 1 (with dummy byte) */ - SPI_BUFMODE_BUFMODE2_gc = (0x03<<6), /* Buffer Mode 2 (no dummy byte) */ -} SPI_BUFMODE_t; - - -/* --------------------------------------------------------------------------- -IRCOM - IR Communication Module --------------------------------------------------------------------------- -*/ - -/* IR Communication Module */ -typedef struct IRCOM_struct -{ - register8_t CTRL; /* Control Register */ - register8_t TXPLCTRL; /* IrDA Transmitter Pulse Length Control Register */ - register8_t RXPLCTRL; /* IrDA Receiver Pulse Length Control Register */ -} IRCOM_t; - -/* Event channel selection */ -typedef enum IRDA_EVSEL_enum -{ - IRDA_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ - IRDA_EVSEL_0_gc = (0x08<<0), /* Event Channel 0 */ - IRDA_EVSEL_1_gc = (0x09<<0), /* Event Channel 1 */ - IRDA_EVSEL_2_gc = (0x0A<<0), /* Event Channel 2 */ - IRDA_EVSEL_3_gc = (0x0B<<0), /* Event Channel 3 */ - IRDA_EVSEL_4_gc = (0x0C<<0), /* Event Channel 4 */ - IRDA_EVSEL_5_gc = (0x0D<<0), /* Event Channel 5 */ - IRDA_EVSEL_6_gc = (0x0E<<0), /* Event Channel 6 */ - IRDA_EVSEL_7_gc = (0x0F<<0), /* Event Channel 7 */ -} IRDA_EVSEL_t; - - -/* --------------------------------------------------------------------------- -FUSE - Fuses and Lockbits --------------------------------------------------------------------------- -*/ - -/* Lock Bits */ -typedef struct NVM_LOCKBITS_struct -{ - register8_t LOCK_BITS; /* Lock Bits (Changed from LOCKBITS to avoid avr-libc collision) */ -} NVM_LOCKBITS_t; - - -/* Fuses */ -typedef struct NVM_FUSES_struct -{ - register8_t reserved_0x00; - register8_t FUSEBYTE1; /* Watchdog Configuration */ - register8_t FUSEBYTE2; /* Reset Configuration */ - register8_t reserved_0x03; - register8_t FUSEBYTE4; /* Start-up Configuration */ - register8_t FUSEBYTE5; /* EESAVE and BOD Level */ - register8_t FUSEBYTE6; /* Fault State */ -} NVM_FUSES_t; - -/* Boot lock bits - boot setcion */ -typedef enum FUSE_BLBB_enum -{ - FUSE_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ - FUSE_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ - FUSE_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ - FUSE_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ -} FUSE_BLBB_t; - -/* Boot lock bits - application section */ -typedef enum FUSE_BLBA_enum -{ - FUSE_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ - FUSE_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ - FUSE_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ - FUSE_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ -} FUSE_BLBA_t; - -/* Boot lock bits - application table section */ -typedef enum FUSE_BLBAT_enum -{ - FUSE_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ - FUSE_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ - FUSE_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ - FUSE_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ -} FUSE_BLBAT_t; - -/* Lock bits */ -typedef enum FUSE_LB_enum -{ - FUSE_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ - FUSE_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ - FUSE_LB_NOLOCK_gc = (0x03<<0), /* No locks */ -} FUSE_LB_t; - -/* Boot Loader Section Reset Vector */ -typedef enum BOOTRST_enum -{ - BOOTRST_BOOTLDR_gc = (0x00<<6), /* Boot Loader Reset */ - BOOTRST_APPLICATION_gc = (0x01<<6), /* Application Reset */ -} BOOTRST_t; - -/* BOD operation */ -typedef enum BOD_enum -{ - BOD_SAMPLED_gc = (0x01<<4), /* BOD enabled in sampled mode */ - BOD_CONTINUOUS_gc = (0x02<<4), /* BOD enabled continuously */ - BOD_DISABLED_gc = (0x03<<4), /* BOD Disabled */ -} BOD_t; - -/* Watchdog (Window) Timeout Period */ -typedef enum WD_enum -{ - WD_8CLK_gc = (0x00<<4), /* 8 cycles (8ms @ 3.3V) */ - WD_16CLK_gc = (0x01<<4), /* 16 cycles (16ms @ 3.3V) */ - WD_32CLK_gc = (0x02<<4), /* 32 cycles (32ms @ 3.3V) */ - WD_64CLK_gc = (0x03<<4), /* 64 cycles (64ms @ 3.3V) */ - WD_128CLK_gc = (0x04<<4), /* 128 cycles (0.125s @ 3.3V) */ - WD_256CLK_gc = (0x05<<4), /* 256 cycles (0.25s @ 3.3V) */ - WD_512CLK_gc = (0x06<<4), /* 512 cycles (0.5s @ 3.3V) */ - WD_1KCLK_gc = (0x07<<4), /* 1K cycles (1s @ 3.3V) */ - WD_2KCLK_gc = (0x08<<4), /* 2K cycles (2s @ 3.3V) */ - WD_4KCLK_gc = (0x09<<4), /* 4K cycles (4s @ 3.3V) */ - WD_8KCLK_gc = (0x0A<<4), /* 8K cycles (8s @ 3.3V) */ -} WD_t; - -/* Start-up Time */ -typedef enum SUT_enum -{ - SUT_0MS_gc = (0x03<<2), /* 0 ms */ - SUT_4MS_gc = (0x01<<2), /* 4 ms */ - SUT_64MS_gc = (0x00<<2), /* 64 ms */ -} SUT_t; - -/* Brownout Detection Voltage Level */ -typedef enum BODLVL_enum -{ - BODLVL_1V6_gc = (0x07<<0), /* 1.6 V */ - BODLVL_1V8_gc = (0x06<<0), /* 1.8 V */ - BODLVL_2V0_gc = (0x05<<0), /* 2.0 V */ - BODLVL_2V2_gc = (0x04<<0), /* 2.2 V */ - BODLVL_2V4_gc = (0x03<<0), /* 2.4 V */ - BODLVL_2V6_gc = (0x02<<0), /* 2.6 V */ - BODLVL_2V8_gc = (0x01<<0), /* 2.8 V */ - BODLVL_3V0_gc = (0x00<<0), /* 3.0 V */ -} BODLVL_t; - - -/* --------------------------------------------------------------------------- -SIGROW - Signature Row --------------------------------------------------------------------------- -*/ - -/* Production Signatures */ -typedef struct NVM_PROD_SIGNATURES_struct -{ - register8_t RCOSC8M; /* RCOSC 8MHz Calibration Value */ - register8_t reserved_0x01; - register8_t RCOSC32K; /* RCOSC 32.768 kHz Calibration Value */ - register8_t RCOSC32M; /* RCOSC 32 MHz Calibration Value B */ - register8_t RCOSC32MA; /* RCOSC 32 MHz Calibration Value A */ - register8_t reserved_0x05; - register8_t reserved_0x06; - register8_t reserved_0x07; - register8_t LOTNUM0; /* Lot Number Byte 0, ASCII */ - register8_t LOTNUM1; /* Lot Number Byte 1, ASCII */ - register8_t LOTNUM2; /* Lot Number Byte 2, ASCII */ - register8_t LOTNUM3; /* Lot Number Byte 3, ASCII */ - register8_t LOTNUM4; /* Lot Number Byte 4, ASCII */ - register8_t LOTNUM5; /* Lot Number Byte 5, ASCII */ - register8_t reserved_0x0E; - register8_t reserved_0x0F; - register8_t WAFNUM; /* Wafer Number */ - register8_t reserved_0x11; - register8_t COORDX0; /* Wafer Coordinate X Byte 0 */ - register8_t COORDX1; /* Wafer Coordinate X Byte 1 */ - register8_t COORDY0; /* Wafer Coordinate Y Byte 0 */ - register8_t COORDY1; /* Wafer Coordinate Y Byte 1 */ - register8_t reserved_0x16; - register8_t reserved_0x17; - register8_t reserved_0x18; - register8_t reserved_0x19; - register8_t reserved_0x1A; - register8_t reserved_0x1B; - register8_t reserved_0x1C; - register8_t reserved_0x1D; - register8_t ROOMTEMP; /* Temperature corresponds to TEMPSENSE3/2 */ - register8_t HOTTEMP; /* Temperature corresponds to TEMPSENSE1/0 */ - register8_t ADCACAL0; /* ADCA Calibration Byte 0 */ - register8_t ADCACAL1; /* ADCA Calibration Byte 1 */ - register8_t reserved_0x22; - register8_t reserved_0x23; - register8_t reserved_0x24; - register8_t reserved_0x25; - register8_t reserved_0x26; - register8_t reserved_0x27; - register8_t ACACURRCAL; /* ACA Current Calibration Byte */ - register8_t reserved_0x29; - register8_t reserved_0x2A; - register8_t reserved_0x2B; - register8_t TEMPSENSE2; /* Temperature Sensor Calibration Byte 2 */ - register8_t TEMPSENSE3; /* Temperature Sensor Calibration Byte 3 */ - register8_t TEMPSENSE0; /* Temperature Sensor Calibration Byte 0 */ - register8_t TEMPSENSE1; /* Temperature Sensor Calibration Byte 1 */ - register8_t DACA0OFFCAL; /* DACA0 Calibration Byte 0 */ - register8_t DACA0GAINCAL; /* DACA0 Calibration Byte 1 */ - register8_t reserved_0x32; - register8_t reserved_0x33; - register8_t DACA1OFFCAL; /* DACA1 Calibration Byte 0 */ - register8_t DACA1GAINCAL; /* DACA1 Calibration Byte 1 */ - register8_t reserved_0x36; - register8_t reserved_0x37; - register8_t reserved_0x38; - register8_t reserved_0x39; - register8_t reserved_0x3A; - register8_t reserved_0x3B; - register8_t reserved_0x3C; - register8_t reserved_0x3D; - register8_t reserved_0x3E; - register8_t reserved_0x3F; -} NVM_PROD_SIGNATURES_t; - -/* -========================================================================== -IO Module Instances. Mapped to memory. -========================================================================== -*/ - -#define VPORT0 (*(VPORT_t *) 0x0010) /* Virtual Port */ -#define VPORT1 (*(VPORT_t *) 0x0014) /* Virtual Port */ -#define VPORT2 (*(VPORT_t *) 0x0018) /* Virtual Port */ -#define VPORT3 (*(VPORT_t *) 0x001C) /* Virtual Port */ -#define OCD (*(OCD_t *) 0x002E) /* On-Chip Debug System */ -#define CLK (*(CLK_t *) 0x0040) /* Clock System */ -#define SLEEP (*(SLEEP_t *) 0x0048) /* Sleep Controller */ -#define OSC (*(OSC_t *) 0x0050) /* Oscillator */ -#define DFLLRC32M (*(DFLL_t *) 0x0060) /* DFLL */ -#define PR (*(PR_t *) 0x0070) /* Power Reduction */ -#define RST (*(RST_t *) 0x0078) /* Reset */ -#define WDT (*(WDT_t *) 0x0080) /* Watch-Dog Timer */ -#define MCU (*(MCU_t *) 0x0090) /* MCU Control */ -#define PMIC (*(PMIC_t *) 0x00A0) /* Programmable Multi-level Interrupt Controller */ -#define PORTCFG (*(PORTCFG_t *) 0x00B0) /* I/O port Configuration */ -#define CRC (*(CRC_t *) 0x00D0) /* Cyclic Redundancy Checker */ -#define EDMA (*(EDMA_t *) 0x0100) /* Enhanced DMA Controller */ -#define EVSYS (*(EVSYS_t *) 0x0180) /* Event System */ -#define NVM (*(NVM_t *) 0x01C0) /* Non-volatile Memory Controller */ -#define ADCA (*(ADC_t *) 0x0200) /* Analog-to-Digital Converter */ -#define DACA (*(DAC_t *) 0x0300) /* Digital-to-Analog Converter */ -#define ACA (*(AC_t *) 0x0380) /* Analog Comparator */ -#define RTC (*(RTC_t *) 0x0400) /* Real-Time Counter */ -#define XCL (*(XCL_t *) 0x0460) /* XMEGA Custom Logic */ -#define TWIC (*(TWI_t *) 0x0480) /* Two-Wire Interface */ -#define PORTA (*(PORT_t *) 0x0600) /* I/O Ports */ -#define PORTC (*(PORT_t *) 0x0640) /* I/O Ports */ -#define PORTD (*(PORT_t *) 0x0660) /* I/O Ports */ -#define PORTR (*(PORT_t *) 0x07E0) /* I/O Ports */ -#define TCC4 (*(TC4_t *) 0x0800) /* 16-bit Timer/Counter 4 */ -#define TCC5 (*(TC5_t *) 0x0840) /* 16-bit Timer/Counter 5 */ -#define FAULTC4 (*(FAULT_t *) 0x0880) /* Fault Extension */ -#define FAULTC5 (*(FAULT_t *) 0x0890) /* Fault Extension */ -#define WEXC (*(WEX_t *) 0x08A0) /* Waveform Extension */ -#define HIRESC (*(HIRES_t *) 0x08B0) /* High-Resolution Extension */ -#define USARTC0 (*(USART_t *) 0x08C0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ -#define SPIC (*(SPI_t *) 0x08E0) /* Serial Peripheral Interface with Buffer Modes */ -#define IRCOM (*(IRCOM_t *) 0x08F8) /* IR Communication Module */ -#define TCD5 (*(TC5_t *) 0x0940) /* 16-bit Timer/Counter 5 */ -#define USARTD0 (*(USART_t *) 0x09C0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ - - -#endif /* !defined (__ASSEMBLER__) */ - - -/* ========== Flattened fully qualified IO register names ========== */ - -/* GPIO - General Purpose IO Registers */ -#define GPIO_GPIOR0 _SFR_MEM8(0x0000) -#define GPIO_GPIOR1 _SFR_MEM8(0x0001) -#define GPIO_GPIOR2 _SFR_MEM8(0x0002) -#define GPIO_GPIOR3 _SFR_MEM8(0x0003) - -/* Deprecated */ -#define GPIO_GPIO0 _SFR_MEM8(0x0000) -#define GPIO_GPIO1 _SFR_MEM8(0x0001) -#define GPIO_GPIO2 _SFR_MEM8(0x0002) -#define GPIO_GPIO3 _SFR_MEM8(0x0003) - -/* NVM_FUSES - Fuses */ -#define FUSE_FUSEBYTE1 _SFR_MEM8(0x0001) -#define FUSE_FUSEBYTE2 _SFR_MEM8(0x0002) -#define FUSE_FUSEBYTE4 _SFR_MEM8(0x0004) -#define FUSE_FUSEBYTE5 _SFR_MEM8(0x0005) -#define FUSE_FUSEBYTE6 _SFR_MEM8(0x0006) - -/* NVM_LOCKBITS - Lock Bits */ -#define LOCKBIT_LOCKBITS _SFR_MEM8(0x0000) - -/* NVM_PROD_SIGNATURES - Production Signatures */ -#define PRODSIGNATURES_RCOSC8M _SFR_MEM8(0x0000) -#define PRODSIGNATURES_RCOSC32K _SFR_MEM8(0x0002) -#define PRODSIGNATURES_RCOSC32M _SFR_MEM8(0x0003) -#define PRODSIGNATURES_RCOSC32MA _SFR_MEM8(0x0004) -#define PRODSIGNATURES_LOTNUM0 _SFR_MEM8(0x0008) -#define PRODSIGNATURES_LOTNUM1 _SFR_MEM8(0x0009) -#define PRODSIGNATURES_LOTNUM2 _SFR_MEM8(0x000A) -#define PRODSIGNATURES_LOTNUM3 _SFR_MEM8(0x000B) -#define PRODSIGNATURES_LOTNUM4 _SFR_MEM8(0x000C) -#define PRODSIGNATURES_LOTNUM5 _SFR_MEM8(0x000D) -#define PRODSIGNATURES_WAFNUM _SFR_MEM8(0x0010) -#define PRODSIGNATURES_COORDX0 _SFR_MEM8(0x0012) -#define PRODSIGNATURES_COORDX1 _SFR_MEM8(0x0013) -#define PRODSIGNATURES_COORDY0 _SFR_MEM8(0x0014) -#define PRODSIGNATURES_COORDY1 _SFR_MEM8(0x0015) -#define PRODSIGNATURES_ROOMTEMP _SFR_MEM8(0x001E) -#define PRODSIGNATURES_HOTTEMP _SFR_MEM8(0x001F) -#define PRODSIGNATURES_ADCACAL0 _SFR_MEM8(0x0020) -#define PRODSIGNATURES_ADCACAL1 _SFR_MEM8(0x0021) -#define PRODSIGNATURES_ACACURRCAL _SFR_MEM8(0x0028) -#define PRODSIGNATURES_TEMPSENSE2 _SFR_MEM8(0x002C) -#define PRODSIGNATURES_TEMPSENSE3 _SFR_MEM8(0x002D) -#define PRODSIGNATURES_TEMPSENSE0 _SFR_MEM8(0x002E) -#define PRODSIGNATURES_TEMPSENSE1 _SFR_MEM8(0x002F) -#define PRODSIGNATURES_DACA0OFFCAL _SFR_MEM8(0x0030) -#define PRODSIGNATURES_DACA0GAINCAL _SFR_MEM8(0x0031) -#define PRODSIGNATURES_DACA1OFFCAL _SFR_MEM8(0x0034) -#define PRODSIGNATURES_DACA1GAINCAL _SFR_MEM8(0x0035) - -/* VPORT - Virtual Port */ -#define VPORT0_DIR _SFR_MEM8(0x0010) -#define VPORT0_OUT _SFR_MEM8(0x0011) -#define VPORT0_IN _SFR_MEM8(0x0012) -#define VPORT0_INTFLAGS _SFR_MEM8(0x0013) - -/* VPORT - Virtual Port */ -#define VPORT1_DIR _SFR_MEM8(0x0014) -#define VPORT1_OUT _SFR_MEM8(0x0015) -#define VPORT1_IN _SFR_MEM8(0x0016) -#define VPORT1_INTFLAGS _SFR_MEM8(0x0017) - -/* VPORT - Virtual Port */ -#define VPORT2_DIR _SFR_MEM8(0x0018) -#define VPORT2_OUT _SFR_MEM8(0x0019) -#define VPORT2_IN _SFR_MEM8(0x001A) -#define VPORT2_INTFLAGS _SFR_MEM8(0x001B) - -/* VPORT - Virtual Port */ -#define VPORT3_DIR _SFR_MEM8(0x001C) -#define VPORT3_OUT _SFR_MEM8(0x001D) -#define VPORT3_IN _SFR_MEM8(0x001E) -#define VPORT3_INTFLAGS _SFR_MEM8(0x001F) - -/* OCD - On-Chip Debug System */ -#define OCD_OCDR0 _SFR_MEM8(0x002E) -#define OCD_OCDR1 _SFR_MEM8(0x002F) - -/* CPU - CPU registers */ -#define CPU_CCP _SFR_MEM8(0x0034) -#define CPU_RAMPD _SFR_MEM8(0x0038) -#define CPU_RAMPX _SFR_MEM8(0x0039) -#define CPU_RAMPY _SFR_MEM8(0x003A) -#define CPU_RAMPZ _SFR_MEM8(0x003B) -#define CPU_EIND _SFR_MEM8(0x003C) -#define CPU_SPL _SFR_MEM8(0x003D) -#define CPU_SPH _SFR_MEM8(0x003E) -#define CPU_SREG _SFR_MEM8(0x003F) - -/* CLK - Clock System */ -#define CLK_CTRL _SFR_MEM8(0x0040) -#define CLK_PSCTRL _SFR_MEM8(0x0041) -#define CLK_LOCK _SFR_MEM8(0x0042) -#define CLK_RTCCTRL _SFR_MEM8(0x0043) - -/* SLEEP - Sleep Controller */ -#define SLEEP_CTRL _SFR_MEM8(0x0048) - -/* OSC - Oscillator */ -#define OSC_CTRL _SFR_MEM8(0x0050) -#define OSC_STATUS _SFR_MEM8(0x0051) -#define OSC_XOSCCTRL _SFR_MEM8(0x0052) -#define OSC_XOSCFAIL _SFR_MEM8(0x0053) -#define OSC_RC32KCAL _SFR_MEM8(0x0054) -#define OSC_PLLCTRL _SFR_MEM8(0x0055) -#define OSC_DFLLCTRL _SFR_MEM8(0x0056) -#define OSC_RC8MCAL _SFR_MEM8(0x0057) - -/* DFLL - DFLL */ -#define DFLLRC32M_CTRL _SFR_MEM8(0x0060) -#define DFLLRC32M_CALA _SFR_MEM8(0x0062) -#define DFLLRC32M_CALB _SFR_MEM8(0x0063) -#define DFLLRC32M_COMP0 _SFR_MEM8(0x0064) -#define DFLLRC32M_COMP1 _SFR_MEM8(0x0065) -#define DFLLRC32M_COMP2 _SFR_MEM8(0x0066) - -/* PR - Power Reduction */ -#define PR_PRGEN _SFR_MEM8(0x0070) -#define PR_PRPA _SFR_MEM8(0x0071) -#define PR_PRPC _SFR_MEM8(0x0073) -#define PR_PRPD _SFR_MEM8(0x0074) - -/* RST - Reset */ -#define RST_STATUS _SFR_MEM8(0x0078) -#define RST_CTRL _SFR_MEM8(0x0079) - -/* WDT - Watch-Dog Timer */ -#define WDT_CTRL _SFR_MEM8(0x0080) -#define WDT_WINCTRL _SFR_MEM8(0x0081) -#define WDT_STATUS _SFR_MEM8(0x0082) - -/* MCU - MCU Control */ -#define MCU_DEVID0 _SFR_MEM8(0x0090) -#define MCU_DEVID1 _SFR_MEM8(0x0091) -#define MCU_DEVID2 _SFR_MEM8(0x0092) -#define MCU_REVID _SFR_MEM8(0x0093) -#define MCU_ANAINIT _SFR_MEM8(0x0097) -#define MCU_EVSYSLOCK _SFR_MEM8(0x0098) -#define MCU_WEXLOCK _SFR_MEM8(0x0099) -#define MCU_FAULTLOCK _SFR_MEM8(0x009A) - -/* PMIC - Programmable Multi-level Interrupt Controller */ -#define PMIC_STATUS _SFR_MEM8(0x00A0) -#define PMIC_INTPRI _SFR_MEM8(0x00A1) -#define PMIC_CTRL _SFR_MEM8(0x00A2) - -/* PORTCFG - I/O port Configuration */ -#define PORTCFG_MPCMASK _SFR_MEM8(0x00B0) -#define PORTCFG_CLKOUT _SFR_MEM8(0x00B4) -#define PORTCFG_ACEVOUT _SFR_MEM8(0x00B6) -#define PORTCFG_SRLCTRL _SFR_MEM8(0x00B7) - -/* CRC - Cyclic Redundancy Checker */ -#define CRC_CTRL _SFR_MEM8(0x00D0) -#define CRC_STATUS _SFR_MEM8(0x00D1) -#define CRC_DATAIN _SFR_MEM8(0x00D3) -#define CRC_CHECKSUM0 _SFR_MEM8(0x00D4) -#define CRC_CHECKSUM1 _SFR_MEM8(0x00D5) -#define CRC_CHECKSUM2 _SFR_MEM8(0x00D6) -#define CRC_CHECKSUM3 _SFR_MEM8(0x00D7) - -/* EDMA - Enhanced DMA Controller */ -#define EDMA_CTRL _SFR_MEM8(0x0100) -#define EDMA_INTFLAGS _SFR_MEM8(0x0103) -#define EDMA_STATUS _SFR_MEM8(0x0104) -#define EDMA_TEMP _SFR_MEM8(0x0106) -#define EDMA_CH0_CTRLA _SFR_MEM8(0x0110) -#define EDMA_CH0_CTRLB _SFR_MEM8(0x0111) -#define EDMA_CH0_ADDRCTRL _SFR_MEM8(0x0112) -#define EDMA_CH0_DESTADDRCTRL _SFR_MEM8(0x0113) -#define EDMA_CH0_TRIGSRC _SFR_MEM8(0x0114) -#define EDMA_CH0_TRFCNT _SFR_MEM16(0x0116) -#define EDMA_CH0_ADDR _SFR_MEM16(0x0118) -#define EDMA_CH0_DESTADDR _SFR_MEM16(0x011C) -#define EDMA_CH1_CTRLA _SFR_MEM8(0x0120) -#define EDMA_CH1_CTRLB _SFR_MEM8(0x0121) -#define EDMA_CH1_ADDRCTRL _SFR_MEM8(0x0122) -#define EDMA_CH1_DESTADDRCTRL _SFR_MEM8(0x0123) -#define EDMA_CH1_TRIGSRC _SFR_MEM8(0x0124) -#define EDMA_CH1_TRFCNT _SFR_MEM16(0x0126) -#define EDMA_CH1_ADDR _SFR_MEM16(0x0128) -#define EDMA_CH1_DESTADDR _SFR_MEM16(0x012C) -#define EDMA_CH2_CTRLA _SFR_MEM8(0x0130) -#define EDMA_CH2_CTRLB _SFR_MEM8(0x0131) -#define EDMA_CH2_ADDRCTRL _SFR_MEM8(0x0132) -#define EDMA_CH2_DESTADDRCTRL _SFR_MEM8(0x0133) -#define EDMA_CH2_TRIGSRC _SFR_MEM8(0x0134) -#define EDMA_CH2_TRFCNT _SFR_MEM16(0x0136) -#define EDMA_CH2_ADDR _SFR_MEM16(0x0138) -#define EDMA_CH2_DESTADDR _SFR_MEM16(0x013C) -#define EDMA_CH3_CTRLA _SFR_MEM8(0x0140) -#define EDMA_CH3_CTRLB _SFR_MEM8(0x0141) -#define EDMA_CH3_ADDRCTRL _SFR_MEM8(0x0142) -#define EDMA_CH3_DESTADDRCTRL _SFR_MEM8(0x0143) -#define EDMA_CH3_TRIGSRC _SFR_MEM8(0x0144) -#define EDMA_CH3_TRFCNT _SFR_MEM16(0x0146) -#define EDMA_CH3_ADDR _SFR_MEM16(0x0148) -#define EDMA_CH3_DESTADDR _SFR_MEM16(0x014C) - -/* EVSYS - Event System */ -#define EVSYS_CH0MUX _SFR_MEM8(0x0180) -#define EVSYS_CH1MUX _SFR_MEM8(0x0181) -#define EVSYS_CH2MUX _SFR_MEM8(0x0182) -#define EVSYS_CH3MUX _SFR_MEM8(0x0183) -#define EVSYS_CH4MUX _SFR_MEM8(0x0184) -#define EVSYS_CH5MUX _SFR_MEM8(0x0185) -#define EVSYS_CH6MUX _SFR_MEM8(0x0186) -#define EVSYS_CH7MUX _SFR_MEM8(0x0187) -#define EVSYS_CH0CTRL _SFR_MEM8(0x0188) -#define EVSYS_CH1CTRL _SFR_MEM8(0x0189) -#define EVSYS_CH2CTRL _SFR_MEM8(0x018A) -#define EVSYS_CH3CTRL _SFR_MEM8(0x018B) -#define EVSYS_CH4CTRL _SFR_MEM8(0x018C) -#define EVSYS_CH5CTRL _SFR_MEM8(0x018D) -#define EVSYS_CH6CTRL _SFR_MEM8(0x018E) -#define EVSYS_CH7CTRL _SFR_MEM8(0x018F) -#define EVSYS_STROBE _SFR_MEM8(0x0190) -#define EVSYS_DATA _SFR_MEM8(0x0191) -#define EVSYS_DFCTRL _SFR_MEM8(0x0192) - -/* NVM - Non-volatile Memory Controller */ -#define NVM_ADDR0 _SFR_MEM8(0x01C0) -#define NVM_ADDR1 _SFR_MEM8(0x01C1) -#define NVM_ADDR2 _SFR_MEM8(0x01C2) -#define NVM_DATA0 _SFR_MEM8(0x01C4) -#define NVM_DATA1 _SFR_MEM8(0x01C5) -#define NVM_DATA2 _SFR_MEM8(0x01C6) -#define NVM_CMD _SFR_MEM8(0x01CA) -#define NVM_CTRLA _SFR_MEM8(0x01CB) -#define NVM_CTRLB _SFR_MEM8(0x01CC) -#define NVM_INTCTRL _SFR_MEM8(0x01CD) -#define NVM_STATUS _SFR_MEM8(0x01CF) -#define NVM_LOCKBITS _SFR_MEM8(0x01D0) - -/* ADC - Analog-to-Digital Converter */ -#define ADCA_CTRLA _SFR_MEM8(0x0200) -#define ADCA_CTRLB _SFR_MEM8(0x0201) -#define ADCA_REFCTRL _SFR_MEM8(0x0202) -#define ADCA_EVCTRL _SFR_MEM8(0x0203) -#define ADCA_PRESCALER _SFR_MEM8(0x0204) -#define ADCA_INTFLAGS _SFR_MEM8(0x0206) -#define ADCA_TEMP _SFR_MEM8(0x0207) -#define ADCA_SAMPCTRL _SFR_MEM8(0x0208) -#define ADCA_CAL _SFR_MEM16(0x020C) -#define ADCA_CH0RES _SFR_MEM16(0x0210) -#define ADCA_CMP _SFR_MEM16(0x0218) -#define ADCA_CH0_CTRL _SFR_MEM8(0x0220) -#define ADCA_CH0_MUXCTRL _SFR_MEM8(0x0221) -#define ADCA_CH0_INTCTRL _SFR_MEM8(0x0222) -#define ADCA_CH0_INTFLAGS _SFR_MEM8(0x0223) -#define ADCA_CH0_RES _SFR_MEM16(0x0224) -#define ADCA_CH0_SCAN _SFR_MEM8(0x0226) -#define ADCA_CH0_CORRCTRL _SFR_MEM8(0x0227) -#define ADCA_CH0_OFFSETCORR0 _SFR_MEM8(0x0228) -#define ADCA_CH0_OFFSETCORR1 _SFR_MEM8(0x0229) -#define ADCA_CH0_GAINCORR0 _SFR_MEM8(0x022A) -#define ADCA_CH0_GAINCORR1 _SFR_MEM8(0x022B) -#define ADCA_CH0_AVGCTRL _SFR_MEM8(0x022C) - -/* DAC - Digital-to-Analog Converter */ -#define DACA_CTRLA _SFR_MEM8(0x0300) -#define DACA_CTRLB _SFR_MEM8(0x0301) -#define DACA_CTRLC _SFR_MEM8(0x0302) -#define DACA_EVCTRL _SFR_MEM8(0x0303) -#define DACA_STATUS _SFR_MEM8(0x0305) -#define DACA_CH0GAINCAL _SFR_MEM8(0x0308) -#define DACA_CH0OFFSETCAL _SFR_MEM8(0x0309) -#define DACA_CH1GAINCAL _SFR_MEM8(0x030A) -#define DACA_CH1OFFSETCAL _SFR_MEM8(0x030B) -#define DACA_CH0DATA _SFR_MEM16(0x0318) -#define DACA_CH1DATA _SFR_MEM16(0x031A) - -/* AC - Analog Comparator */ -#define ACA_AC0CTRL _SFR_MEM8(0x0380) -#define ACA_AC1CTRL _SFR_MEM8(0x0381) -#define ACA_AC0MUXCTRL _SFR_MEM8(0x0382) -#define ACA_AC1MUXCTRL _SFR_MEM8(0x0383) -#define ACA_CTRLA _SFR_MEM8(0x0384) -#define ACA_CTRLB _SFR_MEM8(0x0385) -#define ACA_WINCTRL _SFR_MEM8(0x0386) -#define ACA_STATUS _SFR_MEM8(0x0387) -#define ACA_CURRCTRL _SFR_MEM8(0x0388) -#define ACA_CURRCALIB _SFR_MEM8(0x0389) - -/* RTC - Real-Time Counter */ -#define RTC_CTRL _SFR_MEM8(0x0400) -#define RTC_STATUS _SFR_MEM8(0x0401) -#define RTC_INTCTRL _SFR_MEM8(0x0402) -#define RTC_INTFLAGS _SFR_MEM8(0x0403) -#define RTC_TEMP _SFR_MEM8(0x0404) -#define RTC_CALIB _SFR_MEM8(0x0406) -#define RTC_CNT _SFR_MEM16(0x0408) -#define RTC_PER _SFR_MEM16(0x040A) -#define RTC_COMP _SFR_MEM16(0x040C) - -/* XCL - XMEGA Custom Logic */ -#define XCL_CTRLA _SFR_MEM8(0x0460) -#define XCL_CTRLB _SFR_MEM8(0x0461) -#define XCL_CTRLC _SFR_MEM8(0x0462) -#define XCL_CTRLD _SFR_MEM8(0x0463) -#define XCL_CTRLE _SFR_MEM8(0x0464) -#define XCL_CTRLF _SFR_MEM8(0x0465) -#define XCL_CTRLG _SFR_MEM8(0x0466) -#define XCL_INTCTRL _SFR_MEM8(0x0467) -#define XCL_INTFLAGS _SFR_MEM8(0x0468) -#define XCL_PLC _SFR_MEM8(0x0469) -#define XCL_CNTL _SFR_MEM8(0x046A) -#define XCL_CNTH _SFR_MEM8(0x046B) -#define XCL_CMPL _SFR_MEM8(0x046C) -#define XCL_CMPH _SFR_MEM8(0x046D) -#define XCL_PERCAPTL _SFR_MEM8(0x046E) -#define XCL_PERCAPTH _SFR_MEM8(0x046F) - -/* TWI - Two-Wire Interface */ -#define TWIC_CTRL _SFR_MEM8(0x0480) -#define TWIC_MASTER_CTRLA _SFR_MEM8(0x0481) -#define TWIC_MASTER_CTRLB _SFR_MEM8(0x0482) -#define TWIC_MASTER_CTRLC _SFR_MEM8(0x0483) -#define TWIC_MASTER_STATUS _SFR_MEM8(0x0484) -#define TWIC_MASTER_BAUD _SFR_MEM8(0x0485) -#define TWIC_MASTER_ADDR _SFR_MEM8(0x0486) -#define TWIC_MASTER_DATA _SFR_MEM8(0x0487) -#define TWIC_SLAVE_CTRLA _SFR_MEM8(0x0488) -#define TWIC_SLAVE_CTRLB _SFR_MEM8(0x0489) -#define TWIC_SLAVE_STATUS _SFR_MEM8(0x048A) -#define TWIC_SLAVE_ADDR _SFR_MEM8(0x048B) -#define TWIC_SLAVE_DATA _SFR_MEM8(0x048C) -#define TWIC_SLAVE_ADDRMASK _SFR_MEM8(0x048D) -#define TWIC_TIMEOUT_TOS _SFR_MEM8(0x048E) -#define TWIC_TIMEOUT_TOCONF _SFR_MEM8(0x048F) - -/* PORT - I/O Ports */ -#define PORTA_DIR _SFR_MEM8(0x0600) -#define PORTA_DIRSET _SFR_MEM8(0x0601) -#define PORTA_DIRCLR _SFR_MEM8(0x0602) -#define PORTA_DIRTGL _SFR_MEM8(0x0603) -#define PORTA_OUT _SFR_MEM8(0x0604) -#define PORTA_OUTSET _SFR_MEM8(0x0605) -#define PORTA_OUTCLR _SFR_MEM8(0x0606) -#define PORTA_OUTTGL _SFR_MEM8(0x0607) -#define PORTA_IN _SFR_MEM8(0x0608) -#define PORTA_INTCTRL _SFR_MEM8(0x0609) -#define PORTA_INTMASK _SFR_MEM8(0x060A) -#define PORTA_INTFLAGS _SFR_MEM8(0x060C) -#define PORTA_REMAP _SFR_MEM8(0x060E) -#define PORTA_PIN0CTRL _SFR_MEM8(0x0610) -#define PORTA_PIN1CTRL _SFR_MEM8(0x0611) -#define PORTA_PIN2CTRL _SFR_MEM8(0x0612) -#define PORTA_PIN3CTRL _SFR_MEM8(0x0613) -#define PORTA_PIN4CTRL _SFR_MEM8(0x0614) -#define PORTA_PIN5CTRL _SFR_MEM8(0x0615) -#define PORTA_PIN6CTRL _SFR_MEM8(0x0616) -#define PORTA_PIN7CTRL _SFR_MEM8(0x0617) - -/* PORT - I/O Ports */ -#define PORTC_DIR _SFR_MEM8(0x0640) -#define PORTC_DIRSET _SFR_MEM8(0x0641) -#define PORTC_DIRCLR _SFR_MEM8(0x0642) -#define PORTC_DIRTGL _SFR_MEM8(0x0643) -#define PORTC_OUT _SFR_MEM8(0x0644) -#define PORTC_OUTSET _SFR_MEM8(0x0645) -#define PORTC_OUTCLR _SFR_MEM8(0x0646) -#define PORTC_OUTTGL _SFR_MEM8(0x0647) -#define PORTC_IN _SFR_MEM8(0x0648) -#define PORTC_INTCTRL _SFR_MEM8(0x0649) -#define PORTC_INTMASK _SFR_MEM8(0x064A) -#define PORTC_INTFLAGS _SFR_MEM8(0x064C) -#define PORTC_REMAP _SFR_MEM8(0x064E) -#define PORTC_PIN0CTRL _SFR_MEM8(0x0650) -#define PORTC_PIN1CTRL _SFR_MEM8(0x0651) -#define PORTC_PIN2CTRL _SFR_MEM8(0x0652) -#define PORTC_PIN3CTRL _SFR_MEM8(0x0653) -#define PORTC_PIN4CTRL _SFR_MEM8(0x0654) -#define PORTC_PIN5CTRL _SFR_MEM8(0x0655) -#define PORTC_PIN6CTRL _SFR_MEM8(0x0656) -#define PORTC_PIN7CTRL _SFR_MEM8(0x0657) - -/* PORT - I/O Ports */ -#define PORTD_DIR _SFR_MEM8(0x0660) -#define PORTD_DIRSET _SFR_MEM8(0x0661) -#define PORTD_DIRCLR _SFR_MEM8(0x0662) -#define PORTD_DIRTGL _SFR_MEM8(0x0663) -#define PORTD_OUT _SFR_MEM8(0x0664) -#define PORTD_OUTSET _SFR_MEM8(0x0665) -#define PORTD_OUTCLR _SFR_MEM8(0x0666) -#define PORTD_OUTTGL _SFR_MEM8(0x0667) -#define PORTD_IN _SFR_MEM8(0x0668) -#define PORTD_INTCTRL _SFR_MEM8(0x0669) -#define PORTD_INTMASK _SFR_MEM8(0x066A) -#define PORTD_INTFLAGS _SFR_MEM8(0x066C) -#define PORTD_REMAP _SFR_MEM8(0x066E) -#define PORTD_PIN0CTRL _SFR_MEM8(0x0670) -#define PORTD_PIN1CTRL _SFR_MEM8(0x0671) -#define PORTD_PIN2CTRL _SFR_MEM8(0x0672) -#define PORTD_PIN3CTRL _SFR_MEM8(0x0673) -#define PORTD_PIN4CTRL _SFR_MEM8(0x0674) -#define PORTD_PIN5CTRL _SFR_MEM8(0x0675) -#define PORTD_PIN6CTRL _SFR_MEM8(0x0676) -#define PORTD_PIN7CTRL _SFR_MEM8(0x0677) - -/* PORT - I/O Ports */ -#define PORTR_DIR _SFR_MEM8(0x07E0) -#define PORTR_DIRSET _SFR_MEM8(0x07E1) -#define PORTR_DIRCLR _SFR_MEM8(0x07E2) -#define PORTR_DIRTGL _SFR_MEM8(0x07E3) -#define PORTR_OUT _SFR_MEM8(0x07E4) -#define PORTR_OUTSET _SFR_MEM8(0x07E5) -#define PORTR_OUTCLR _SFR_MEM8(0x07E6) -#define PORTR_OUTTGL _SFR_MEM8(0x07E7) -#define PORTR_IN _SFR_MEM8(0x07E8) -#define PORTR_INTCTRL _SFR_MEM8(0x07E9) -#define PORTR_INTMASK _SFR_MEM8(0x07EA) -#define PORTR_INTFLAGS _SFR_MEM8(0x07EC) -#define PORTR_REMAP _SFR_MEM8(0x07EE) -#define PORTR_PIN0CTRL _SFR_MEM8(0x07F0) -#define PORTR_PIN1CTRL _SFR_MEM8(0x07F1) -#define PORTR_PIN2CTRL _SFR_MEM8(0x07F2) -#define PORTR_PIN3CTRL _SFR_MEM8(0x07F3) -#define PORTR_PIN4CTRL _SFR_MEM8(0x07F4) -#define PORTR_PIN5CTRL _SFR_MEM8(0x07F5) -#define PORTR_PIN6CTRL _SFR_MEM8(0x07F6) -#define PORTR_PIN7CTRL _SFR_MEM8(0x07F7) - -/* TC4 - 16-bit Timer/Counter 4 */ -#define TCC4_CTRLA _SFR_MEM8(0x0800) -#define TCC4_CTRLB _SFR_MEM8(0x0801) -#define TCC4_CTRLC _SFR_MEM8(0x0802) -#define TCC4_CTRLD _SFR_MEM8(0x0803) -#define TCC4_CTRLE _SFR_MEM8(0x0804) -#define TCC4_CTRLF _SFR_MEM8(0x0805) -#define TCC4_INTCTRLA _SFR_MEM8(0x0806) -#define TCC4_INTCTRLB _SFR_MEM8(0x0807) -#define TCC4_CTRLGCLR _SFR_MEM8(0x0808) -#define TCC4_CTRLGSET _SFR_MEM8(0x0809) -#define TCC4_CTRLHCLR _SFR_MEM8(0x080A) -#define TCC4_CTRLHSET _SFR_MEM8(0x080B) -#define TCC4_INTFLAGS _SFR_MEM8(0x080C) -#define TCC4_TEMP _SFR_MEM8(0x080F) -#define TCC4_CNT _SFR_MEM16(0x0820) -#define TCC4_PER _SFR_MEM16(0x0826) -#define TCC4_CCA _SFR_MEM16(0x0828) -#define TCC4_CCB _SFR_MEM16(0x082A) -#define TCC4_CCC _SFR_MEM16(0x082C) -#define TCC4_CCD _SFR_MEM16(0x082E) -#define TCC4_PERBUF _SFR_MEM16(0x0836) -#define TCC4_CCABUF _SFR_MEM16(0x0838) -#define TCC4_CCBBUF _SFR_MEM16(0x083A) -#define TCC4_CCCBUF _SFR_MEM16(0x083C) -#define TCC4_CCDBUF _SFR_MEM16(0x083E) - -/* TC5 - 16-bit Timer/Counter 5 */ -#define TCC5_CTRLA _SFR_MEM8(0x0840) -#define TCC5_CTRLB _SFR_MEM8(0x0841) -#define TCC5_CTRLC _SFR_MEM8(0x0842) -#define TCC5_CTRLD _SFR_MEM8(0x0843) -#define TCC5_CTRLE _SFR_MEM8(0x0844) -#define TCC5_CTRLF _SFR_MEM8(0x0845) -#define TCC5_INTCTRLA _SFR_MEM8(0x0846) -#define TCC5_INTCTRLB _SFR_MEM8(0x0847) -#define TCC5_CTRLGCLR _SFR_MEM8(0x0848) -#define TCC5_CTRLGSET _SFR_MEM8(0x0849) -#define TCC5_CTRLHCLR _SFR_MEM8(0x084A) -#define TCC5_CTRLHSET _SFR_MEM8(0x084B) -#define TCC5_INTFLAGS _SFR_MEM8(0x084C) -#define TCC5_TEMP _SFR_MEM8(0x084F) -#define TCC5_CNT _SFR_MEM16(0x0860) -#define TCC5_PER _SFR_MEM16(0x0866) -#define TCC5_CCA _SFR_MEM16(0x0868) -#define TCC5_CCB _SFR_MEM16(0x086A) -#define TCC5_PERBUF _SFR_MEM16(0x0876) -#define TCC5_CCABUF _SFR_MEM16(0x0878) -#define TCC5_CCBBUF _SFR_MEM16(0x087A) - -/* FAULT - Fault Extension */ -#define FAULTC4_CTRLA _SFR_MEM8(0x0880) -#define FAULTC4_CTRLB _SFR_MEM8(0x0881) -#define FAULTC4_CTRLC _SFR_MEM8(0x0882) -#define FAULTC4_CTRLD _SFR_MEM8(0x0883) -#define FAULTC4_CTRLE _SFR_MEM8(0x0884) -#define FAULTC4_STATUS _SFR_MEM8(0x0885) -#define FAULTC4_CTRLGCLR _SFR_MEM8(0x0886) -#define FAULTC4_CTRLGSET _SFR_MEM8(0x0887) - -/* FAULT - Fault Extension */ -#define FAULTC5_CTRLA _SFR_MEM8(0x0890) -#define FAULTC5_CTRLB _SFR_MEM8(0x0891) -#define FAULTC5_CTRLC _SFR_MEM8(0x0892) -#define FAULTC5_CTRLD _SFR_MEM8(0x0893) -#define FAULTC5_CTRLE _SFR_MEM8(0x0894) -#define FAULTC5_STATUS _SFR_MEM8(0x0895) -#define FAULTC5_CTRLGCLR _SFR_MEM8(0x0896) -#define FAULTC5_CTRLGSET _SFR_MEM8(0x0897) - -/* WEX - Waveform Extension */ -#define WEXC_CTRL _SFR_MEM8(0x08A0) -#define WEXC_DTBOTH _SFR_MEM8(0x08A1) -#define WEXC_DTLS _SFR_MEM8(0x08A2) -#define WEXC_DTHS _SFR_MEM8(0x08A3) -#define WEXC_STATUSCLR _SFR_MEM8(0x08A4) -#define WEXC_STATUSSET _SFR_MEM8(0x08A5) -#define WEXC_SWAP _SFR_MEM8(0x08A6) -#define WEXC_PGO _SFR_MEM8(0x08A7) -#define WEXC_PGV _SFR_MEM8(0x08A8) -#define WEXC_SWAPBUF _SFR_MEM8(0x08AA) -#define WEXC_PGOBUF _SFR_MEM8(0x08AB) -#define WEXC_PGVBUF _SFR_MEM8(0x08AC) -#define WEXC_OUTOVDIS _SFR_MEM8(0x08AF) - -/* HIRES - High-Resolution Extension */ -#define HIRESC_CTRLA _SFR_MEM8(0x08B0) - -/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ -#define USARTC0_DATA _SFR_MEM8(0x08C0) -#define USARTC0_STATUS _SFR_MEM8(0x08C1) -#define USARTC0_CTRLA _SFR_MEM8(0x08C2) -#define USARTC0_CTRLB _SFR_MEM8(0x08C3) -#define USARTC0_CTRLC _SFR_MEM8(0x08C4) -#define USARTC0_CTRLD _SFR_MEM8(0x08C5) -#define USARTC0_BAUDCTRLA _SFR_MEM8(0x08C6) -#define USARTC0_BAUDCTRLB _SFR_MEM8(0x08C7) - -/* SPI - Serial Peripheral Interface with Buffer Modes */ -#define SPIC_CTRL _SFR_MEM8(0x08E0) -#define SPIC_INTCTRL _SFR_MEM8(0x08E1) -#define SPIC_STATUS _SFR_MEM8(0x08E2) -#define SPIC_DATA _SFR_MEM8(0x08E3) -#define SPIC_CTRLB _SFR_MEM8(0x08E4) - -/* IRCOM - IR Communication Module */ -#define IRCOM_CTRL _SFR_MEM8(0x08F8) -#define IRCOM_TXPLCTRL _SFR_MEM8(0x08F9) -#define IRCOM_RXPLCTRL _SFR_MEM8(0x08FA) - -/* TC5 - 16-bit Timer/Counter 5 */ -#define TCD5_CTRLA _SFR_MEM8(0x0940) -#define TCD5_CTRLB _SFR_MEM8(0x0941) -#define TCD5_CTRLC _SFR_MEM8(0x0942) -#define TCD5_CTRLD _SFR_MEM8(0x0943) -#define TCD5_CTRLE _SFR_MEM8(0x0944) -#define TCD5_CTRLF _SFR_MEM8(0x0945) -#define TCD5_INTCTRLA _SFR_MEM8(0x0946) -#define TCD5_INTCTRLB _SFR_MEM8(0x0947) -#define TCD5_CTRLGCLR _SFR_MEM8(0x0948) -#define TCD5_CTRLGSET _SFR_MEM8(0x0949) -#define TCD5_CTRLHCLR _SFR_MEM8(0x094A) -#define TCD5_CTRLHSET _SFR_MEM8(0x094B) -#define TCD5_INTFLAGS _SFR_MEM8(0x094C) -#define TCD5_TEMP _SFR_MEM8(0x094F) -#define TCD5_CNT _SFR_MEM16(0x0960) -#define TCD5_PER _SFR_MEM16(0x0966) -#define TCD5_CCA _SFR_MEM16(0x0968) -#define TCD5_CCB _SFR_MEM16(0x096A) -#define TCD5_PERBUF _SFR_MEM16(0x0976) -#define TCD5_CCABUF _SFR_MEM16(0x0978) -#define TCD5_CCBBUF _SFR_MEM16(0x097A) - -/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ -#define USARTD0_DATA _SFR_MEM8(0x09C0) -#define USARTD0_STATUS _SFR_MEM8(0x09C1) -#define USARTD0_CTRLA _SFR_MEM8(0x09C2) -#define USARTD0_CTRLB _SFR_MEM8(0x09C3) -#define USARTD0_CTRLC _SFR_MEM8(0x09C4) -#define USARTD0_CTRLD _SFR_MEM8(0x09C5) -#define USARTD0_BAUDCTRLA _SFR_MEM8(0x09C6) -#define USARTD0_BAUDCTRLB _SFR_MEM8(0x09C7) - - - -/*================== Bitfield Definitions ================== */ - -/* VPORT - Virtual Ports */ -/* VPORT.INTFLAGS bit masks and bit positions */ -#define VPORT_INT7IF_bm 0x80 /* Interrupt Pin 7 Flag bit mask. */ -#define VPORT_INT7IF_bp 7 /* Interrupt Pin 7 Flag bit position. */ - -#define VPORT_INT6IF_bm 0x40 /* Interrupt Pin 6 Flag bit mask. */ -#define VPORT_INT6IF_bp 6 /* Interrupt Pin 6 Flag bit position. */ - -#define VPORT_INT5IF_bm 0x20 /* Interrupt Pin 5 Flag bit mask. */ -#define VPORT_INT5IF_bp 5 /* Interrupt Pin 5 Flag bit position. */ - -#define VPORT_INT4IF_bm 0x10 /* Interrupt Pin 4 Flag bit mask. */ -#define VPORT_INT4IF_bp 4 /* Interrupt Pin 4 Flag bit position. */ - -#define VPORT_INT3IF_bm 0x08 /* Interrupt Pin 3 Flag bit mask. */ -#define VPORT_INT3IF_bp 3 /* Interrupt Pin 3 Flag bit position. */ - -#define VPORT_INT2IF_bm 0x04 /* Interrupt Pin 2 Flag bit mask. */ -#define VPORT_INT2IF_bp 2 /* Interrupt Pin 2 Flag bit position. */ - -#define VPORT_INT1IF_bm 0x02 /* Interrupt Pin 1 Flag bit mask. */ -#define VPORT_INT1IF_bp 1 /* Interrupt Pin 1 Flag bit position. */ - -#define VPORT_INT0IF_bm 0x01 /* Interrupt Pin 0 Flag bit mask. */ -#define VPORT_INT0IF_bp 0 /* Interrupt Pin 0 Flag bit position. */ - -/* XOCD - On-Chip Debug System */ -/* OCD.OCDR0 bit masks and bit positions */ -#define OCD_OCDRD_gm 0xFF /* OCDR Dirty group mask. */ -#define OCD_OCDRD_gp 0 /* OCDR Dirty group position. */ -#define OCD_OCDRD0_bm (1<<0) /* OCDR Dirty bit 0 mask. */ -#define OCD_OCDRD0_bp 0 /* OCDR Dirty bit 0 position. */ -#define OCD_OCDRD1_bm (1<<1) /* OCDR Dirty bit 1 mask. */ -#define OCD_OCDRD1_bp 1 /* OCDR Dirty bit 1 position. */ -#define OCD_OCDRD2_bm (1<<2) /* OCDR Dirty bit 2 mask. */ -#define OCD_OCDRD2_bp 2 /* OCDR Dirty bit 2 position. */ -#define OCD_OCDRD3_bm (1<<3) /* OCDR Dirty bit 3 mask. */ -#define OCD_OCDRD3_bp 3 /* OCDR Dirty bit 3 position. */ -#define OCD_OCDRD4_bm (1<<4) /* OCDR Dirty bit 4 mask. */ -#define OCD_OCDRD4_bp 4 /* OCDR Dirty bit 4 position. */ -#define OCD_OCDRD5_bm (1<<5) /* OCDR Dirty bit 5 mask. */ -#define OCD_OCDRD5_bp 5 /* OCDR Dirty bit 5 position. */ -#define OCD_OCDRD6_bm (1<<6) /* OCDR Dirty bit 6 mask. */ -#define OCD_OCDRD6_bp 6 /* OCDR Dirty bit 6 position. */ -#define OCD_OCDRD7_bm (1<<7) /* OCDR Dirty bit 7 mask. */ -#define OCD_OCDRD7_bp 7 /* OCDR Dirty bit 7 position. */ - -/* OCD.OCDR1 bit masks and bit positions */ -/* OCD_OCDRD Predefined. */ -/* OCD_OCDRD Predefined. */ - -/* CPU - CPU */ -/* CPU.CCP bit masks and bit positions */ -#define CPU_CCP_gm 0xFF /* CCP signature group mask. */ -#define CPU_CCP_gp 0 /* CCP signature group position. */ -#define CPU_CCP0_bm (1<<0) /* CCP signature bit 0 mask. */ -#define CPU_CCP0_bp 0 /* CCP signature bit 0 position. */ -#define CPU_CCP1_bm (1<<1) /* CCP signature bit 1 mask. */ -#define CPU_CCP1_bp 1 /* CCP signature bit 1 position. */ -#define CPU_CCP2_bm (1<<2) /* CCP signature bit 2 mask. */ -#define CPU_CCP2_bp 2 /* CCP signature bit 2 position. */ -#define CPU_CCP3_bm (1<<3) /* CCP signature bit 3 mask. */ -#define CPU_CCP3_bp 3 /* CCP signature bit 3 position. */ -#define CPU_CCP4_bm (1<<4) /* CCP signature bit 4 mask. */ -#define CPU_CCP4_bp 4 /* CCP signature bit 4 position. */ -#define CPU_CCP5_bm (1<<5) /* CCP signature bit 5 mask. */ -#define CPU_CCP5_bp 5 /* CCP signature bit 5 position. */ -#define CPU_CCP6_bm (1<<6) /* CCP signature bit 6 mask. */ -#define CPU_CCP6_bp 6 /* CCP signature bit 6 position. */ -#define CPU_CCP7_bm (1<<7) /* CCP signature bit 7 mask. */ -#define CPU_CCP7_bp 7 /* CCP signature bit 7 position. */ - -/* CPU.SREG bit masks and bit positions */ -#define CPU_I_bm 0x80 /* Global Interrupt Enable Flag bit mask. */ -#define CPU_I_bp 7 /* Global Interrupt Enable Flag bit position. */ - -#define CPU_T_bm 0x40 /* Transfer Bit bit mask. */ -#define CPU_T_bp 6 /* Transfer Bit bit position. */ - -#define CPU_H_bm 0x20 /* Half Carry Flag bit mask. */ -#define CPU_H_bp 5 /* Half Carry Flag bit position. */ - -#define CPU_S_bm 0x10 /* N Exclusive Or V Flag bit mask. */ -#define CPU_S_bp 4 /* N Exclusive Or V Flag bit position. */ - -#define CPU_V_bm 0x08 /* Two's Complement Overflow Flag bit mask. */ -#define CPU_V_bp 3 /* Two's Complement Overflow Flag bit position. */ - -#define CPU_N_bm 0x04 /* Negative Flag bit mask. */ -#define CPU_N_bp 2 /* Negative Flag bit position. */ - -#define CPU_Z_bm 0x02 /* Zero Flag bit mask. */ -#define CPU_Z_bp 1 /* Zero Flag bit position. */ - -#define CPU_C_bm 0x01 /* Carry Flag bit mask. */ -#define CPU_C_bp 0 /* Carry Flag bit position. */ - -/* CLK - Clock System */ -/* CLK.CTRL bit masks and bit positions */ -#define CLK_SCLKSEL_gm 0x07 /* System Clock Selection group mask. */ -#define CLK_SCLKSEL_gp 0 /* System Clock Selection group position. */ -#define CLK_SCLKSEL0_bm (1<<0) /* System Clock Selection bit 0 mask. */ -#define CLK_SCLKSEL0_bp 0 /* System Clock Selection bit 0 position. */ -#define CLK_SCLKSEL1_bm (1<<1) /* System Clock Selection bit 1 mask. */ -#define CLK_SCLKSEL1_bp 1 /* System Clock Selection bit 1 position. */ -#define CLK_SCLKSEL2_bm (1<<2) /* System Clock Selection bit 2 mask. */ -#define CLK_SCLKSEL2_bp 2 /* System Clock Selection bit 2 position. */ - -/* CLK.PSCTRL bit masks and bit positions */ -#define CLK_PSADIV_gm 0x7C /* Prescaler A Division Factor group mask. */ -#define CLK_PSADIV_gp 2 /* Prescaler A Division Factor group position. */ -#define CLK_PSADIV0_bm (1<<2) /* Prescaler A Division Factor bit 0 mask. */ -#define CLK_PSADIV0_bp 2 /* Prescaler A Division Factor bit 0 position. */ -#define CLK_PSADIV1_bm (1<<3) /* Prescaler A Division Factor bit 1 mask. */ -#define CLK_PSADIV1_bp 3 /* Prescaler A Division Factor bit 1 position. */ -#define CLK_PSADIV2_bm (1<<4) /* Prescaler A Division Factor bit 2 mask. */ -#define CLK_PSADIV2_bp 4 /* Prescaler A Division Factor bit 2 position. */ -#define CLK_PSADIV3_bm (1<<5) /* Prescaler A Division Factor bit 3 mask. */ -#define CLK_PSADIV3_bp 5 /* Prescaler A Division Factor bit 3 position. */ -#define CLK_PSADIV4_bm (1<<6) /* Prescaler A Division Factor bit 4 mask. */ -#define CLK_PSADIV4_bp 6 /* Prescaler A Division Factor bit 4 position. */ - -#define CLK_PSBCDIV_gm 0x03 /* Prescaler B and C Division factor group mask. */ -#define CLK_PSBCDIV_gp 0 /* Prescaler B and C Division factor group position. */ -#define CLK_PSBCDIV0_bm (1<<0) /* Prescaler B and C Division factor bit 0 mask. */ -#define CLK_PSBCDIV0_bp 0 /* Prescaler B and C Division factor bit 0 position. */ -#define CLK_PSBCDIV1_bm (1<<1) /* Prescaler B and C Division factor bit 1 mask. */ -#define CLK_PSBCDIV1_bp 1 /* Prescaler B and C Division factor bit 1 position. */ - -/* CLK.LOCK bit masks and bit positions */ -#define CLK_LOCK_bm 0x01 /* Clock System Lock bit mask. */ -#define CLK_LOCK_bp 0 /* Clock System Lock bit position. */ - -/* CLK.RTCCTRL bit masks and bit positions */ -#define CLK_RTCSRC_gm 0x0E /* Clock Source group mask. */ -#define CLK_RTCSRC_gp 1 /* Clock Source group position. */ -#define CLK_RTCSRC0_bm (1<<1) /* Clock Source bit 0 mask. */ -#define CLK_RTCSRC0_bp 1 /* Clock Source bit 0 position. */ -#define CLK_RTCSRC1_bm (1<<2) /* Clock Source bit 1 mask. */ -#define CLK_RTCSRC1_bp 2 /* Clock Source bit 1 position. */ -#define CLK_RTCSRC2_bm (1<<3) /* Clock Source bit 2 mask. */ -#define CLK_RTCSRC2_bp 3 /* Clock Source bit 2 position. */ - -#define CLK_RTCEN_bm 0x01 /* Clock Source Enable bit mask. */ -#define CLK_RTCEN_bp 0 /* Clock Source Enable bit position. */ - -/* PR.PRGEN bit masks and bit positions */ -#define PR_XCL_bm 0x80 /* XMEGA Custom Logic bit mask. */ -#define PR_XCL_bp 7 /* XMEGA Custom Logic bit position. */ - -#define PR_RTC_bm 0x04 /* Real-time Counter bit mask. */ -#define PR_RTC_bp 2 /* Real-time Counter bit position. */ - -#define PR_EVSYS_bm 0x02 /* Event System bit mask. */ -#define PR_EVSYS_bp 1 /* Event System bit position. */ - -#define PR_EDMA_bm 0x01 /* Enhanced DMA-Controller bit mask. */ -#define PR_EDMA_bp 0 /* Enhanced DMA-Controller bit position. */ - -/* PR.PRPA bit masks and bit positions */ -#define PR_DAC_bm 0x04 /* Port A DAC bit mask. */ -#define PR_DAC_bp 2 /* Port A DAC bit position. */ - -#define PR_ADC_bm 0x02 /* Port A ADC bit mask. */ -#define PR_ADC_bp 1 /* Port A ADC bit position. */ - -#define PR_AC_bm 0x01 /* Port A Analog Comparator bit mask. */ -#define PR_AC_bp 0 /* Port A Analog Comparator bit position. */ - -/* PR.PRPC bit masks and bit positions */ -#define PR_TWI_bm 0x40 /* Port C Two-wire Interface bit mask. */ -#define PR_TWI_bp 6 /* Port C Two-wire Interface bit position. */ - -#define PR_USART0_bm 0x10 /* Port C USART0 bit mask. */ -#define PR_USART0_bp 4 /* Port C USART0 bit position. */ - -#define PR_SPI_bm 0x08 /* Port C SPI bit mask. */ -#define PR_SPI_bp 3 /* Port C SPI bit position. */ - -#define PR_HIRES_bm 0x04 /* Port C WEX bit mask. */ -#define PR_HIRES_bp 2 /* Port C WEX bit position. */ - -#define PR_TC5_bm 0x02 /* Port C Timer/Counter5 bit mask. */ -#define PR_TC5_bp 1 /* Port C Timer/Counter5 bit position. */ - -#define PR_TC4_bm 0x01 /* Port C Timer/Counter4 bit mask. */ -#define PR_TC4_bp 0 /* Port C Timer/Counter4 bit position. */ - -/* PR.PRPD bit masks and bit positions */ -/* PR_USART0 Predefined. */ -/* PR_USART0 Predefined. */ - -/* PR_TC5 Predefined. */ -/* PR_TC5 Predefined. */ - -/* SLEEP - Sleep Controller */ -/* SLEEP.CTRL bit masks and bit positions */ -#define SLEEP_SMODE_gm 0x0E /* Sleep Mode group mask. */ -#define SLEEP_SMODE_gp 1 /* Sleep Mode group position. */ -#define SLEEP_SMODE0_bm (1<<1) /* Sleep Mode bit 0 mask. */ -#define SLEEP_SMODE0_bp 1 /* Sleep Mode bit 0 position. */ -#define SLEEP_SMODE1_bm (1<<2) /* Sleep Mode bit 1 mask. */ -#define SLEEP_SMODE1_bp 2 /* Sleep Mode bit 1 position. */ -#define SLEEP_SMODE2_bm (1<<3) /* Sleep Mode bit 2 mask. */ -#define SLEEP_SMODE2_bp 3 /* Sleep Mode bit 2 position. */ - -#define SLEEP_SEN_bm 0x01 /* Sleep Enable bit mask. */ -#define SLEEP_SEN_bp 0 /* Sleep Enable bit position. */ - -/* OSC - Oscillator */ -/* OSC.CTRL bit masks and bit positions */ -#define OSC_RC8MLPM_bm 0x40 /* Internal 8 MHz RC Low Power Mode Enable bit mask. */ -#define OSC_RC8MLPM_bp 6 /* Internal 8 MHz RC Low Power Mode Enable bit position. */ - -#define OSC_RC8MEN_bm 0x20 /* Internal 8 MHz RC Oscillator Enable bit mask. */ -#define OSC_RC8MEN_bp 5 /* Internal 8 MHz RC Oscillator Enable bit position. */ - -#define OSC_PLLEN_bm 0x10 /* PLL Enable bit mask. */ -#define OSC_PLLEN_bp 4 /* PLL Enable bit position. */ - -#define OSC_XOSCEN_bm 0x08 /* External Oscillator Enable bit mask. */ -#define OSC_XOSCEN_bp 3 /* External Oscillator Enable bit position. */ - -#define OSC_RC32KEN_bm 0x04 /* Internal 32.768 kHz RC Oscillator Enable bit mask. */ -#define OSC_RC32KEN_bp 2 /* Internal 32.768 kHz RC Oscillator Enable bit position. */ - -#define OSC_RC32MEN_bm 0x02 /* Internal 32 MHz RC Oscillator Enable bit mask. */ -#define OSC_RC32MEN_bp 1 /* Internal 32 MHz RC Oscillator Enable bit position. */ - -#define OSC_RC2MEN_bm 0x01 /* Internal 2 MHz RC Oscillator Enable bit mask. */ -#define OSC_RC2MEN_bp 0 /* Internal 2 MHz RC Oscillator Enable bit position. */ - -/* OSC.STATUS bit masks and bit positions */ -#define OSC_RC8MRDY_bm 0x20 /* Internal 8 MHz RC Oscillator Ready bit mask. */ -#define OSC_RC8MRDY_bp 5 /* Internal 8 MHz RC Oscillator Ready bit position. */ - -#define OSC_PLLRDY_bm 0x10 /* PLL Ready bit mask. */ -#define OSC_PLLRDY_bp 4 /* PLL Ready bit position. */ - -#define OSC_XOSCRDY_bm 0x08 /* External Oscillator Ready bit mask. */ -#define OSC_XOSCRDY_bp 3 /* External Oscillator Ready bit position. */ - -#define OSC_RC32KRDY_bm 0x04 /* Internal 32.768 kHz RC Oscillator Ready bit mask. */ -#define OSC_RC32KRDY_bp 2 /* Internal 32.768 kHz RC Oscillator Ready bit position. */ - -#define OSC_RC32MRDY_bm 0x02 /* Internal 32 MHz RC Oscillator Ready bit mask. */ -#define OSC_RC32MRDY_bp 1 /* Internal 32 MHz RC Oscillator Ready bit position. */ - -#define OSC_RC2MRDY_bm 0x01 /* Internal 2 MHz RC Oscillator Ready bit mask. */ -#define OSC_RC2MRDY_bp 0 /* Internal 2 MHz RC Oscillator Ready bit position. */ - -/* OSC.XOSCCTRL bit masks and bit positions */ -#define OSC_FRQRANGE_gm 0xC0 /* Frequency Range group mask. */ -#define OSC_FRQRANGE_gp 6 /* Frequency Range group position. */ -#define OSC_FRQRANGE0_bm (1<<6) /* Frequency Range bit 0 mask. */ -#define OSC_FRQRANGE0_bp 6 /* Frequency Range bit 0 position. */ -#define OSC_FRQRANGE1_bm (1<<7) /* Frequency Range bit 1 mask. */ -#define OSC_FRQRANGE1_bp 7 /* Frequency Range bit 1 position. */ - -#define OSC_X32KLPM_bm 0x20 /* 32.768 kHz XTAL OSC Low-power Mode bit mask. */ -#define OSC_X32KLPM_bp 5 /* 32.768 kHz XTAL OSC Low-power Mode bit position. */ - -#define OSC_XOSCPWR_bm 0x10 /* 16 MHz Crystal Oscillator High Power mode bit mask. */ -#define OSC_XOSCPWR_bp 4 /* 16 MHz Crystal Oscillator High Power mode bit position. */ - -#define OSC_XOSCSEL_gm 0x1F /* External Oscillator Selection and Startup Time group mask. */ -#define OSC_XOSCSEL_gp 0 /* External Oscillator Selection and Startup Time group position. */ -#define OSC_XOSCSEL0_bm (1<<0) /* External Oscillator Selection and Startup Time bit 0 mask. */ -#define OSC_XOSCSEL0_bp 0 /* External Oscillator Selection and Startup Time bit 0 position. */ -#define OSC_XOSCSEL1_bm (1<<1) /* External Oscillator Selection and Startup Time bit 1 mask. */ -#define OSC_XOSCSEL1_bp 1 /* External Oscillator Selection and Startup Time bit 1 position. */ -#define OSC_XOSCSEL2_bm (1<<2) /* External Oscillator Selection and Startup Time bit 2 mask. */ -#define OSC_XOSCSEL2_bp 2 /* External Oscillator Selection and Startup Time bit 2 position. */ -#define OSC_XOSCSEL3_bm (1<<3) /* External Oscillator Selection and Startup Time bit 3 mask. */ -#define OSC_XOSCSEL3_bp 3 /* External Oscillator Selection and Startup Time bit 3 position. */ -#define OSC_XOSCSEL4_bm (1<<4) /* External Oscillator Selection and Startup Time bit 4 mask. */ -#define OSC_XOSCSEL4_bp 4 /* External Oscillator Selection and Startup Time bit 4 position. */ - -/* OSC.XOSCFAIL bit masks and bit positions */ -#define OSC_PLLFDIF_bm 0x08 /* PLL Failure Detection Interrupt Flag bit mask. */ -#define OSC_PLLFDIF_bp 3 /* PLL Failure Detection Interrupt Flag bit position. */ - -#define OSC_PLLFDEN_bm 0x04 /* PLL Failure Detection Enable bit mask. */ -#define OSC_PLLFDEN_bp 2 /* PLL Failure Detection Enable bit position. */ - -#define OSC_XOSCFDIF_bm 0x02 /* XOSC Failure Detection Interrupt Flag bit mask. */ -#define OSC_XOSCFDIF_bp 1 /* XOSC Failure Detection Interrupt Flag bit position. */ - -#define OSC_XOSCFDEN_bm 0x01 /* XOSC Failure Detection Enable bit mask. */ -#define OSC_XOSCFDEN_bp 0 /* XOSC Failure Detection Enable bit position. */ - -/* OSC.PLLCTRL bit masks and bit positions */ -#define OSC_PLLSRC_gm 0xC0 /* Clock Source group mask. */ -#define OSC_PLLSRC_gp 6 /* Clock Source group position. */ -#define OSC_PLLSRC0_bm (1<<6) /* Clock Source bit 0 mask. */ -#define OSC_PLLSRC0_bp 6 /* Clock Source bit 0 position. */ -#define OSC_PLLSRC1_bm (1<<7) /* Clock Source bit 1 mask. */ -#define OSC_PLLSRC1_bp 7 /* Clock Source bit 1 position. */ - -#define OSC_PLLDIV_bm 0x20 /* Divide by 2 bit mask. */ -#define OSC_PLLDIV_bp 5 /* Divide by 2 bit position. */ - -#define OSC_PLLFAC_gm 0x1F /* Multiplication Factor group mask. */ -#define OSC_PLLFAC_gp 0 /* Multiplication Factor group position. */ -#define OSC_PLLFAC0_bm (1<<0) /* Multiplication Factor bit 0 mask. */ -#define OSC_PLLFAC0_bp 0 /* Multiplication Factor bit 0 position. */ -#define OSC_PLLFAC1_bm (1<<1) /* Multiplication Factor bit 1 mask. */ -#define OSC_PLLFAC1_bp 1 /* Multiplication Factor bit 1 position. */ -#define OSC_PLLFAC2_bm (1<<2) /* Multiplication Factor bit 2 mask. */ -#define OSC_PLLFAC2_bp 2 /* Multiplication Factor bit 2 position. */ -#define OSC_PLLFAC3_bm (1<<3) /* Multiplication Factor bit 3 mask. */ -#define OSC_PLLFAC3_bp 3 /* Multiplication Factor bit 3 position. */ -#define OSC_PLLFAC4_bm (1<<4) /* Multiplication Factor bit 4 mask. */ -#define OSC_PLLFAC4_bp 4 /* Multiplication Factor bit 4 position. */ - -/* OSC.DFLLCTRL bit masks and bit positions */ -#define OSC_RC32MCREF_gm 0x06 /* 32 MHz DFLL Calibration Reference group mask. */ -#define OSC_RC32MCREF_gp 1 /* 32 MHz DFLL Calibration Reference group position. */ -#define OSC_RC32MCREF0_bm (1<<1) /* 32 MHz DFLL Calibration Reference bit 0 mask. */ -#define OSC_RC32MCREF0_bp 1 /* 32 MHz DFLL Calibration Reference bit 0 position. */ -#define OSC_RC32MCREF1_bm (1<<2) /* 32 MHz DFLL Calibration Reference bit 1 mask. */ -#define OSC_RC32MCREF1_bp 2 /* 32 MHz DFLL Calibration Reference bit 1 position. */ - -/* OSC.RC8MCAL bit masks and bit positions */ -#define OSC_RC8MCAL_gm 0xFF /* Calibration Bits group mask. */ -#define OSC_RC8MCAL_gp 0 /* Calibration Bits group position. */ -#define OSC_RC8MCAL0_bm (1<<0) /* Calibration Bits bit 0 mask. */ -#define OSC_RC8MCAL0_bp 0 /* Calibration Bits bit 0 position. */ -#define OSC_RC8MCAL1_bm (1<<1) /* Calibration Bits bit 1 mask. */ -#define OSC_RC8MCAL1_bp 1 /* Calibration Bits bit 1 position. */ -#define OSC_RC8MCAL2_bm (1<<2) /* Calibration Bits bit 2 mask. */ -#define OSC_RC8MCAL2_bp 2 /* Calibration Bits bit 2 position. */ -#define OSC_RC8MCAL3_bm (1<<3) /* Calibration Bits bit 3 mask. */ -#define OSC_RC8MCAL3_bp 3 /* Calibration Bits bit 3 position. */ -#define OSC_RC8MCAL4_bm (1<<4) /* Calibration Bits bit 4 mask. */ -#define OSC_RC8MCAL4_bp 4 /* Calibration Bits bit 4 position. */ -#define OSC_RC8MCAL5_bm (1<<5) /* Calibration Bits bit 5 mask. */ -#define OSC_RC8MCAL5_bp 5 /* Calibration Bits bit 5 position. */ -#define OSC_RC8MCAL6_bm (1<<6) /* Calibration Bits bit 6 mask. */ -#define OSC_RC8MCAL6_bp 6 /* Calibration Bits bit 6 position. */ -#define OSC_RC8MCAL7_bm (1<<7) /* Calibration Bits bit 7 mask. */ -#define OSC_RC8MCAL7_bp 7 /* Calibration Bits bit 7 position. */ - -/* DFLL - DFLL */ -/* DFLL.CTRL bit masks and bit positions */ -#define DFLL_ENABLE_bm 0x01 /* DFLL Enable bit mask. */ -#define DFLL_ENABLE_bp 0 /* DFLL Enable bit position. */ - -/* DFLL.CALA bit masks and bit positions */ -#define DFLL_CALL_gm 0x7F /* DFLL Calibration Value A group mask. */ -#define DFLL_CALL_gp 0 /* DFLL Calibration Value A group position. */ -#define DFLL_CALL0_bm (1<<0) /* DFLL Calibration Value A bit 0 mask. */ -#define DFLL_CALL0_bp 0 /* DFLL Calibration Value A bit 0 position. */ -#define DFLL_CALL1_bm (1<<1) /* DFLL Calibration Value A bit 1 mask. */ -#define DFLL_CALL1_bp 1 /* DFLL Calibration Value A bit 1 position. */ -#define DFLL_CALL2_bm (1<<2) /* DFLL Calibration Value A bit 2 mask. */ -#define DFLL_CALL2_bp 2 /* DFLL Calibration Value A bit 2 position. */ -#define DFLL_CALL3_bm (1<<3) /* DFLL Calibration Value A bit 3 mask. */ -#define DFLL_CALL3_bp 3 /* DFLL Calibration Value A bit 3 position. */ -#define DFLL_CALL4_bm (1<<4) /* DFLL Calibration Value A bit 4 mask. */ -#define DFLL_CALL4_bp 4 /* DFLL Calibration Value A bit 4 position. */ -#define DFLL_CALL5_bm (1<<5) /* DFLL Calibration Value A bit 5 mask. */ -#define DFLL_CALL5_bp 5 /* DFLL Calibration Value A bit 5 position. */ -#define DFLL_CALL6_bm (1<<6) /* DFLL Calibration Value A bit 6 mask. */ -#define DFLL_CALL6_bp 6 /* DFLL Calibration Value A bit 6 position. */ - -/* DFLL.CALB bit masks and bit positions */ -#define DFLL_CALH_gm 0x3F /* DFLL Calibration Value B group mask. */ -#define DFLL_CALH_gp 0 /* DFLL Calibration Value B group position. */ -#define DFLL_CALH0_bm (1<<0) /* DFLL Calibration Value B bit 0 mask. */ -#define DFLL_CALH0_bp 0 /* DFLL Calibration Value B bit 0 position. */ -#define DFLL_CALH1_bm (1<<1) /* DFLL Calibration Value B bit 1 mask. */ -#define DFLL_CALH1_bp 1 /* DFLL Calibration Value B bit 1 position. */ -#define DFLL_CALH2_bm (1<<2) /* DFLL Calibration Value B bit 2 mask. */ -#define DFLL_CALH2_bp 2 /* DFLL Calibration Value B bit 2 position. */ -#define DFLL_CALH3_bm (1<<3) /* DFLL Calibration Value B bit 3 mask. */ -#define DFLL_CALH3_bp 3 /* DFLL Calibration Value B bit 3 position. */ -#define DFLL_CALH4_bm (1<<4) /* DFLL Calibration Value B bit 4 mask. */ -#define DFLL_CALH4_bp 4 /* DFLL Calibration Value B bit 4 position. */ -#define DFLL_CALH5_bm (1<<5) /* DFLL Calibration Value B bit 5 mask. */ -#define DFLL_CALH5_bp 5 /* DFLL Calibration Value B bit 5 position. */ - -/* RST - Reset */ -/* RST.STATUS bit masks and bit positions */ -#define RST_SDRF_bm 0x40 /* Spike Detection Reset Flag bit mask. */ -#define RST_SDRF_bp 6 /* Spike Detection Reset Flag bit position. */ - -#define RST_SRF_bm 0x20 /* Software Reset Flag bit mask. */ -#define RST_SRF_bp 5 /* Software Reset Flag bit position. */ - -#define RST_PDIRF_bm 0x10 /* Programming and Debug Interface Interface Reset Flag bit mask. */ -#define RST_PDIRF_bp 4 /* Programming and Debug Interface Interface Reset Flag bit position. */ - -#define RST_WDRF_bm 0x08 /* Watchdog Reset Flag bit mask. */ -#define RST_WDRF_bp 3 /* Watchdog Reset Flag bit position. */ - -#define RST_BORF_bm 0x04 /* Brown-out Reset Flag bit mask. */ -#define RST_BORF_bp 2 /* Brown-out Reset Flag bit position. */ - -#define RST_EXTRF_bm 0x02 /* External Reset Flag bit mask. */ -#define RST_EXTRF_bp 1 /* External Reset Flag bit position. */ - -#define RST_PORF_bm 0x01 /* Power-on Reset Flag bit mask. */ -#define RST_PORF_bp 0 /* Power-on Reset Flag bit position. */ - -/* RST.CTRL bit masks and bit positions */ -#define RST_SWRST_bm 0x01 /* Software Reset bit mask. */ -#define RST_SWRST_bp 0 /* Software Reset bit position. */ - -/* WDT - Watch-Dog Timer */ -/* WDT.CTRL bit masks and bit positions */ -#define WDT_PER_gm 0x3C /* Period group mask. */ -#define WDT_PER_gp 2 /* Period group position. */ -#define WDT_PER0_bm (1<<2) /* Period bit 0 mask. */ -#define WDT_PER0_bp 2 /* Period bit 0 position. */ -#define WDT_PER1_bm (1<<3) /* Period bit 1 mask. */ -#define WDT_PER1_bp 3 /* Period bit 1 position. */ -#define WDT_PER2_bm (1<<4) /* Period bit 2 mask. */ -#define WDT_PER2_bp 4 /* Period bit 2 position. */ -#define WDT_PER3_bm (1<<5) /* Period bit 3 mask. */ -#define WDT_PER3_bp 5 /* Period bit 3 position. */ - -#define WDT_ENABLE_bm 0x02 /* Enable bit mask. */ -#define WDT_ENABLE_bp 1 /* Enable bit position. */ - -#define WDT_CEN_bm 0x01 /* Change Enable bit mask. */ -#define WDT_CEN_bp 0 /* Change Enable bit position. */ - -/* WDT.WINCTRL bit masks and bit positions */ -#define WDT_WPER_gm 0x3C /* Windowed Mode Period group mask. */ -#define WDT_WPER_gp 2 /* Windowed Mode Period group position. */ -#define WDT_WPER0_bm (1<<2) /* Windowed Mode Period bit 0 mask. */ -#define WDT_WPER0_bp 2 /* Windowed Mode Period bit 0 position. */ -#define WDT_WPER1_bm (1<<3) /* Windowed Mode Period bit 1 mask. */ -#define WDT_WPER1_bp 3 /* Windowed Mode Period bit 1 position. */ -#define WDT_WPER2_bm (1<<4) /* Windowed Mode Period bit 2 mask. */ -#define WDT_WPER2_bp 4 /* Windowed Mode Period bit 2 position. */ -#define WDT_WPER3_bm (1<<5) /* Windowed Mode Period bit 3 mask. */ -#define WDT_WPER3_bp 5 /* Windowed Mode Period bit 3 position. */ - -#define WDT_WEN_bm 0x02 /* Windowed Mode Enable bit mask. */ -#define WDT_WEN_bp 1 /* Windowed Mode Enable bit position. */ - -#define WDT_WCEN_bm 0x01 /* Windowed Mode Change Enable bit mask. */ -#define WDT_WCEN_bp 0 /* Windowed Mode Change Enable bit position. */ - -/* WDT.STATUS bit masks and bit positions */ -#define WDT_SYNCBUSY_bm 0x01 /* Syncronization busy bit mask. */ -#define WDT_SYNCBUSY_bp 0 /* Syncronization busy bit position. */ - -/* MCU - MCU Control */ -/* MCU.ANAINIT bit masks and bit positions */ -#define MCU_STARTUPDLYA_gm 0x03 /* Analog startup delay Port A group mask. */ -#define MCU_STARTUPDLYA_gp 0 /* Analog startup delay Port A group position. */ -#define MCU_STARTUPDLYA0_bm (1<<0) /* Analog startup delay Port A bit 0 mask. */ -#define MCU_STARTUPDLYA0_bp 0 /* Analog startup delay Port A bit 0 position. */ -#define MCU_STARTUPDLYA1_bm (1<<1) /* Analog startup delay Port A bit 1 mask. */ -#define MCU_STARTUPDLYA1_bp 1 /* Analog startup delay Port A bit 1 position. */ - -/* MCU.EVSYSLOCK bit masks and bit positions */ -#define MCU_EVSYS1LOCK_bm 0x10 /* Event Channel 4-7 Lock bit mask. */ -#define MCU_EVSYS1LOCK_bp 4 /* Event Channel 4-7 Lock bit position. */ - -#define MCU_EVSYS0LOCK_bm 0x01 /* Event Channel 0-3 Lock bit mask. */ -#define MCU_EVSYS0LOCK_bp 0 /* Event Channel 0-3 Lock bit position. */ - -/* MCU.WEXLOCK bit masks and bit positions */ -#define MCU_WEXCLOCK_bm 0x01 /* WeX on T/C C4 Lock bit mask. */ -#define MCU_WEXCLOCK_bp 0 /* WeX on T/C C4 Lock bit position. */ - -/* MCU.FAULTLOCK bit masks and bit positions */ -#define MCU_FAULTC5LOCK_bm 0x02 /* Fault on T/C C5 Lock bit mask. */ -#define MCU_FAULTC5LOCK_bp 1 /* Fault on T/C C5 Lock bit position. */ - -#define MCU_FAULTC4LOCK_bm 0x01 /* Fault on T/C C4 Lock bit mask. */ -#define MCU_FAULTC4LOCK_bp 0 /* Fault on T/C C4 Lock bit position. */ - -/* PMIC - Programmable Multi-level Interrupt Controller */ -/* PMIC.STATUS bit masks and bit positions */ -#define PMIC_NMIEX_bm 0x80 /* Non-maskable Interrupt Executing bit mask. */ -#define PMIC_NMIEX_bp 7 /* Non-maskable Interrupt Executing bit position. */ - -#define PMIC_HILVLEX_bm 0x04 /* High Level Interrupt Executing bit mask. */ -#define PMIC_HILVLEX_bp 2 /* High Level Interrupt Executing bit position. */ - -#define PMIC_MEDLVLEX_bm 0x02 /* Medium Level Interrupt Executing bit mask. */ -#define PMIC_MEDLVLEX_bp 1 /* Medium Level Interrupt Executing bit position. */ - -#define PMIC_LOLVLEX_bm 0x01 /* Low Level Interrupt Executing bit mask. */ -#define PMIC_LOLVLEX_bp 0 /* Low Level Interrupt Executing bit position. */ - -/* PMIC.INTPRI bit masks and bit positions */ -#define PMIC_INTPRI_gm 0xFF /* Interrupt Priority group mask. */ -#define PMIC_INTPRI_gp 0 /* Interrupt Priority group position. */ -#define PMIC_INTPRI0_bm (1<<0) /* Interrupt Priority bit 0 mask. */ -#define PMIC_INTPRI0_bp 0 /* Interrupt Priority bit 0 position. */ -#define PMIC_INTPRI1_bm (1<<1) /* Interrupt Priority bit 1 mask. */ -#define PMIC_INTPRI1_bp 1 /* Interrupt Priority bit 1 position. */ -#define PMIC_INTPRI2_bm (1<<2) /* Interrupt Priority bit 2 mask. */ -#define PMIC_INTPRI2_bp 2 /* Interrupt Priority bit 2 position. */ -#define PMIC_INTPRI3_bm (1<<3) /* Interrupt Priority bit 3 mask. */ -#define PMIC_INTPRI3_bp 3 /* Interrupt Priority bit 3 position. */ -#define PMIC_INTPRI4_bm (1<<4) /* Interrupt Priority bit 4 mask. */ -#define PMIC_INTPRI4_bp 4 /* Interrupt Priority bit 4 position. */ -#define PMIC_INTPRI5_bm (1<<5) /* Interrupt Priority bit 5 mask. */ -#define PMIC_INTPRI5_bp 5 /* Interrupt Priority bit 5 position. */ -#define PMIC_INTPRI6_bm (1<<6) /* Interrupt Priority bit 6 mask. */ -#define PMIC_INTPRI6_bp 6 /* Interrupt Priority bit 6 position. */ -#define PMIC_INTPRI7_bm (1<<7) /* Interrupt Priority bit 7 mask. */ -#define PMIC_INTPRI7_bp 7 /* Interrupt Priority bit 7 position. */ - -/* PMIC.CTRL bit masks and bit positions */ -#define PMIC_RREN_bm 0x80 /* Round-Robin Priority Enable bit mask. */ -#define PMIC_RREN_bp 7 /* Round-Robin Priority Enable bit position. */ - -#define PMIC_IVSEL_bm 0x40 /* Interrupt Vector Select bit mask. */ -#define PMIC_IVSEL_bp 6 /* Interrupt Vector Select bit position. */ - -#define PMIC_HILVLEN_bm 0x04 /* High Level Enable bit mask. */ -#define PMIC_HILVLEN_bp 2 /* High Level Enable bit position. */ - -#define PMIC_MEDLVLEN_bm 0x02 /* Medium Level Enable bit mask. */ -#define PMIC_MEDLVLEN_bp 1 /* Medium Level Enable bit position. */ - -#define PMIC_LOLVLEN_bm 0x01 /* Low Level Enable bit mask. */ -#define PMIC_LOLVLEN_bp 0 /* Low Level Enable bit position. */ - -/* PORTCFG - Port Configuration */ -/* PORTCFG.CLKOUT bit masks and bit positions */ -#define PORTCFG_CLKEVPIN_bm 0x80 /* Clock and Event Output Pin Select bit mask. */ -#define PORTCFG_CLKEVPIN_bp 7 /* Clock and Event Output Pin Select bit position. */ - -#define PORTCFG_RTCOUT_gm 0x60 /* RTC Clock Output Enable group mask. */ -#define PORTCFG_RTCOUT_gp 5 /* RTC Clock Output Enable group position. */ -#define PORTCFG_RTCOUT0_bm (1<<5) /* RTC Clock Output Enable bit 0 mask. */ -#define PORTCFG_RTCOUT0_bp 5 /* RTC Clock Output Enable bit 0 position. */ -#define PORTCFG_RTCOUT1_bm (1<<6) /* RTC Clock Output Enable bit 1 mask. */ -#define PORTCFG_RTCOUT1_bp 6 /* RTC Clock Output Enable bit 1 position. */ - -#define PORTCFG_CLKOUTSEL_gm 0x0C /* Clock Output Select group mask. */ -#define PORTCFG_CLKOUTSEL_gp 2 /* Clock Output Select group position. */ -#define PORTCFG_CLKOUTSEL0_bm (1<<2) /* Clock Output Select bit 0 mask. */ -#define PORTCFG_CLKOUTSEL0_bp 2 /* Clock Output Select bit 0 position. */ -#define PORTCFG_CLKOUTSEL1_bm (1<<3) /* Clock Output Select bit 1 mask. */ -#define PORTCFG_CLKOUTSEL1_bp 3 /* Clock Output Select bit 1 position. */ - -#define PORTCFG_CLKOUT_gm 0x03 /* Clock Output Port group mask. */ -#define PORTCFG_CLKOUT_gp 0 /* Clock Output Port group position. */ -#define PORTCFG_CLKOUT0_bm (1<<0) /* Clock Output Port bit 0 mask. */ -#define PORTCFG_CLKOUT0_bp 0 /* Clock Output Port bit 0 position. */ -#define PORTCFG_CLKOUT1_bm (1<<1) /* Clock Output Port bit 1 mask. */ -#define PORTCFG_CLKOUT1_bp 1 /* Clock Output Port bit 1 position. */ - -/* PORTCFG.ACEVOUT bit masks and bit positions */ -#define PORTCFG_ACOUT_gm 0xC0 /* Analog Comparator Output Port group mask. */ -#define PORTCFG_ACOUT_gp 6 /* Analog Comparator Output Port group position. */ -#define PORTCFG_ACOUT0_bm (1<<6) /* Analog Comparator Output Port bit 0 mask. */ -#define PORTCFG_ACOUT0_bp 6 /* Analog Comparator Output Port bit 0 position. */ -#define PORTCFG_ACOUT1_bm (1<<7) /* Analog Comparator Output Port bit 1 mask. */ -#define PORTCFG_ACOUT1_bp 7 /* Analog Comparator Output Port bit 1 position. */ - -#define PORTCFG_EVOUT_gm 0x30 /* Event Channel Output Port group mask. */ -#define PORTCFG_EVOUT_gp 4 /* Event Channel Output Port group position. */ -#define PORTCFG_EVOUT0_bm (1<<4) /* Event Channel Output Port bit 0 mask. */ -#define PORTCFG_EVOUT0_bp 4 /* Event Channel Output Port bit 0 position. */ -#define PORTCFG_EVOUT1_bm (1<<5) /* Event Channel Output Port bit 1 mask. */ -#define PORTCFG_EVOUT1_bp 5 /* Event Channel Output Port bit 1 position. */ - -#define PORTCFG_EVASYEN_bm 0x08 /* Asynchronous Event Enabled bit mask. */ -#define PORTCFG_EVASYEN_bp 3 /* Asynchronous Event Enabled bit position. */ - -#define PORTCFG_EVOUTSEL_gm 0x07 /* Event Channel Output Selection group mask. */ -#define PORTCFG_EVOUTSEL_gp 0 /* Event Channel Output Selection group position. */ -#define PORTCFG_EVOUTSEL0_bm (1<<0) /* Event Channel Output Selection bit 0 mask. */ -#define PORTCFG_EVOUTSEL0_bp 0 /* Event Channel Output Selection bit 0 position. */ -#define PORTCFG_EVOUTSEL1_bm (1<<1) /* Event Channel Output Selection bit 1 mask. */ -#define PORTCFG_EVOUTSEL1_bp 1 /* Event Channel Output Selection bit 1 position. */ -#define PORTCFG_EVOUTSEL2_bm (1<<2) /* Event Channel Output Selection bit 2 mask. */ -#define PORTCFG_EVOUTSEL2_bp 2 /* Event Channel Output Selection bit 2 position. */ - -/* PORTCFG.SRLCTRL bit masks and bit positions */ -#define PORTCFG_SRLENRA_bm 0x01 /* Slew Rate Limit Enable on PORTA bit mask. */ -#define PORTCFG_SRLENRA_bp 0 /* Slew Rate Limit Enable on PORTA bit position. */ - -#define PORTCFG_SRLENRC_bm 0x04 /* Slew Rate Limit Enable on PORTC bit mask. */ -#define PORTCFG_SRLENRC_bp 2 /* Slew Rate Limit Enable on PORTC bit position. */ - -#define PORTCFG_SRLENRD_bm 0x08 /* Slew Rate Limit Enable on PORTD bit mask. */ -#define PORTCFG_SRLENRD_bp 3 /* Slew Rate Limit Enable on PORTD bit position. */ - -#define PORTCFG_SRLENRR_bm 0x80 /* Slew Rate Limit Enable on PORTR bit mask. */ -#define PORTCFG_SRLENRR_bp 7 /* Slew Rate Limit Enable on PORTR bit position. */ - -/* CRC - Cyclic Redundancy Checker */ -/* CRC.CTRL bit masks and bit positions */ -#define CRC_RESET_gm 0xC0 /* Reset group mask. */ -#define CRC_RESET_gp 6 /* Reset group position. */ -#define CRC_RESET0_bm (1<<6) /* Reset bit 0 mask. */ -#define CRC_RESET0_bp 6 /* Reset bit 0 position. */ -#define CRC_RESET1_bm (1<<7) /* Reset bit 1 mask. */ -#define CRC_RESET1_bp 7 /* Reset bit 1 position. */ - -#define CRC_CRC32_bm 0x20 /* CRC Mode bit mask. */ -#define CRC_CRC32_bp 5 /* CRC Mode bit position. */ - -#define CRC_SOURCE_gm 0x0F /* Input Source group mask. */ -#define CRC_SOURCE_gp 0 /* Input Source group position. */ -#define CRC_SOURCE0_bm (1<<0) /* Input Source bit 0 mask. */ -#define CRC_SOURCE0_bp 0 /* Input Source bit 0 position. */ -#define CRC_SOURCE1_bm (1<<1) /* Input Source bit 1 mask. */ -#define CRC_SOURCE1_bp 1 /* Input Source bit 1 position. */ -#define CRC_SOURCE2_bm (1<<2) /* Input Source bit 2 mask. */ -#define CRC_SOURCE2_bp 2 /* Input Source bit 2 position. */ -#define CRC_SOURCE3_bm (1<<3) /* Input Source bit 3 mask. */ -#define CRC_SOURCE3_bp 3 /* Input Source bit 3 position. */ - -/* CRC.STATUS bit masks and bit positions */ -#define CRC_ZERO_bm 0x02 /* Zero detection bit mask. */ -#define CRC_ZERO_bp 1 /* Zero detection bit position. */ - -#define CRC_BUSY_bm 0x01 /* Busy bit mask. */ -#define CRC_BUSY_bp 0 /* Busy bit position. */ - -/* EDMA - Enhanced DMA Controller */ -/* EDMA.CTRL bit masks and bit positions */ -#define EDMA_ENABLE_bm 0x80 /* Enable bit mask. */ -#define EDMA_ENABLE_bp 7 /* Enable bit position. */ - -#define EDMA_RESET_bm 0x40 /* Software Reset bit mask. */ -#define EDMA_RESET_bp 6 /* Software Reset bit position. */ - -#define EDMA_CHMODE_gm 0x30 /* Channel Mode group mask. */ -#define EDMA_CHMODE_gp 4 /* Channel Mode group position. */ -#define EDMA_CHMODE0_bm (1<<4) /* Channel Mode bit 0 mask. */ -#define EDMA_CHMODE0_bp 4 /* Channel Mode bit 0 position. */ -#define EDMA_CHMODE1_bm (1<<5) /* Channel Mode bit 1 mask. */ -#define EDMA_CHMODE1_bp 5 /* Channel Mode bit 1 position. */ - -#define EDMA_DBUFMODE_gm 0x0C /* Double Buffer Mode group mask. */ -#define EDMA_DBUFMODE_gp 2 /* Double Buffer Mode group position. */ -#define EDMA_DBUFMODE0_bm (1<<2) /* Double Buffer Mode bit 0 mask. */ -#define EDMA_DBUFMODE0_bp 2 /* Double Buffer Mode bit 0 position. */ -#define EDMA_DBUFMODE1_bm (1<<3) /* Double Buffer Mode bit 1 mask. */ -#define EDMA_DBUFMODE1_bp 3 /* Double Buffer Mode bit 1 position. */ - -#define EDMA_PRIMODE_gm 0x03 /* Priority Mode group mask. */ -#define EDMA_PRIMODE_gp 0 /* Priority Mode group position. */ -#define EDMA_PRIMODE0_bm (1<<0) /* Priority Mode bit 0 mask. */ -#define EDMA_PRIMODE0_bp 0 /* Priority Mode bit 0 position. */ -#define EDMA_PRIMODE1_bm (1<<1) /* Priority Mode bit 1 mask. */ -#define EDMA_PRIMODE1_bp 1 /* Priority Mode bit 1 position. */ - -/* EDMA.INTFLAGS bit masks and bit positions */ -#define EDMA_CH3ERRIF_bm 0x80 /* Channel 3 Transaction Error Interrupt Flag bit mask. */ -#define EDMA_CH3ERRIF_bp 7 /* Channel 3 Transaction Error Interrupt Flag bit position. */ - -#define EDMA_CH2ERRIF_bm 0x40 /* Channel 2 Transaction Error Interrupt Flag bit mask. */ -#define EDMA_CH2ERRIF_bp 6 /* Channel 2 Transaction Error Interrupt Flag bit position. */ - -#define EDMA_CH1ERRIF_bm 0x20 /* Channel 1 Transaction Error Interrupt Flag bit mask. */ -#define EDMA_CH1ERRIF_bp 5 /* Channel 1 Transaction Error Interrupt Flag bit position. */ - -#define EDMA_CH0ERRIF_bm 0x10 /* Channel 0 Transaction Error Interrupt Flag bit mask. */ -#define EDMA_CH0ERRIF_bp 4 /* Channel 0 Transaction Error Interrupt Flag bit position. */ - -#define EDMA_CH3TRNFIF_bm 0x08 /* Channel 3 Transaction Complete Interrupt Flag bit mask. */ -#define EDMA_CH3TRNFIF_bp 3 /* Channel 3 Transaction Complete Interrupt Flag bit position. */ - -#define EDMA_CH2TRNFIF_bm 0x04 /* Channel 2 Transaction Complete Interrupt Flag bit mask. */ -#define EDMA_CH2TRNFIF_bp 2 /* Channel 2 Transaction Complete Interrupt Flag bit position. */ - -#define EDMA_CH1TRNFIF_bm 0x02 /* Channel 1 Transaction Complete Interrupt Flag bit mask. */ -#define EDMA_CH1TRNFIF_bp 1 /* Channel 1 Transaction Complete Interrupt Flag bit position. */ - -#define EDMA_CH0TRNFIF_bm 0x01 /* Channel 0 Transaction Complete Interrupt Flag bit mask. */ -#define EDMA_CH0TRNFIF_bp 0 /* Channel 0 Transaction Complete Interrupt Flag bit position. */ - -/* EDMA.STATUS bit masks and bit positions */ -#define EDMA_CH3BUSY_bm 0x80 /* Channel 3 Busy Flag bit mask. */ -#define EDMA_CH3BUSY_bp 7 /* Channel 3 Busy Flag bit position. */ - -#define EDMA_CH2BUSY_bm 0x40 /* Channel 2 Busy Flag bit mask. */ -#define EDMA_CH2BUSY_bp 6 /* Channel 2 Busy Flag bit position. */ - -#define EDMA_CH1BUSY_bm 0x20 /* Channel 1 Busy Flag bit mask. */ -#define EDMA_CH1BUSY_bp 5 /* Channel 1 Busy Flag bit position. */ - -#define EDMA_CH0BUSY_bm 0x10 /* Channel 0 Busy Flag bit mask. */ -#define EDMA_CH0BUSY_bp 4 /* Channel 0 Busy Flag bit position. */ - -#define EDMA_CH3PEND_bm 0x08 /* Channel 3 Pending Flag bit mask. */ -#define EDMA_CH3PEND_bp 3 /* Channel 3 Pending Flag bit position. */ - -#define EDMA_CH2PEND_bm 0x04 /* Channel 2 Pending Flag bit mask. */ -#define EDMA_CH2PEND_bp 2 /* Channel 2 Pending Flag bit position. */ - -#define EDMA_CH1PEND_bm 0x02 /* Channel 1 Pending Flag bit mask. */ -#define EDMA_CH1PEND_bp 1 /* Channel 1 Pending Flag bit position. */ - -#define EDMA_CH0PEND_bm 0x01 /* Channel 0 Pending Flag bit mask. */ -#define EDMA_CH0PEND_bp 0 /* Channel 0 Pending Flag bit position. */ - -/* EDMA_CH.CTRLA bit masks and bit positions */ -#define EDMA_CH_ENABLE_bm 0x80 /* Channel Enable bit mask. */ -#define EDMA_CH_ENABLE_bp 7 /* Channel Enable bit position. */ - -#define EDMA_CH_RESET_bm 0x40 /* Channel Software Reset bit mask. */ -#define EDMA_CH_RESET_bp 6 /* Channel Software Reset bit position. */ - -#define EDMA_CH_REPEAT_bm 0x20 /* Channel Repeat Mode bit mask. */ -#define EDMA_CH_REPEAT_bp 5 /* Channel Repeat Mode bit position. */ - -#define EDMA_CH_TRFREQ_bm 0x10 /* Channel Transfer Request bit mask. */ -#define EDMA_CH_TRFREQ_bp 4 /* Channel Transfer Request bit position. */ - -#define EDMA_CH_SINGLE_bm 0x04 /* Channel Single Shot Data Transfer bit mask. */ -#define EDMA_CH_SINGLE_bp 2 /* Channel Single Shot Data Transfer bit position. */ - -#define EDMA_CH_BURSTLEN_bm 0x01 /* Channel 2-bytes Burst Length bit mask. */ -#define EDMA_CH_BURSTLEN_bp 0 /* Channel 2-bytes Burst Length bit position. */ - -/* EDMA_CH.CTRLB bit masks and bit positions */ -#define EDMA_CH_CHBUSY_bm 0x80 /* Channel Block Transfer Busy bit mask. */ -#define EDMA_CH_CHBUSY_bp 7 /* Channel Block Transfer Busy bit position. */ - -#define EDMA_CH_CHPEND_bm 0x40 /* Channel Block Transfer Pending bit mask. */ -#define EDMA_CH_CHPEND_bp 6 /* Channel Block Transfer Pending bit position. */ - -#define EDMA_CH_ERRIF_bm 0x20 /* Channel Transaction Error Interrupt Flag bit mask. */ -#define EDMA_CH_ERRIF_bp 5 /* Channel Transaction Error Interrupt Flag bit position. */ - -#define EDMA_CH_TRNIF_bm 0x10 /* Channel Transaction Complete Interrup Flag bit mask. */ -#define EDMA_CH_TRNIF_bp 4 /* Channel Transaction Complete Interrup Flag bit position. */ - -#define EDMA_CH_ERRINTLVL_gm 0x0C /* Channel Transaction Error Interrupt Level group mask. */ -#define EDMA_CH_ERRINTLVL_gp 2 /* Channel Transaction Error Interrupt Level group position. */ -#define EDMA_CH_ERRINTLVL0_bm (1<<2) /* Channel Transaction Error Interrupt Level bit 0 mask. */ -#define EDMA_CH_ERRINTLVL0_bp 2 /* Channel Transaction Error Interrupt Level bit 0 position. */ -#define EDMA_CH_ERRINTLVL1_bm (1<<3) /* Channel Transaction Error Interrupt Level bit 1 mask. */ -#define EDMA_CH_ERRINTLVL1_bp 3 /* Channel Transaction Error Interrupt Level bit 1 position. */ - -#define EDMA_CH_TRNINTLVL_gm 0x03 /* Channel Transaction Complete Interrupt Level group mask. */ -#define EDMA_CH_TRNINTLVL_gp 0 /* Channel Transaction Complete Interrupt Level group position. */ -#define EDMA_CH_TRNINTLVL0_bm (1<<0) /* Channel Transaction Complete Interrupt Level bit 0 mask. */ -#define EDMA_CH_TRNINTLVL0_bp 0 /* Channel Transaction Complete Interrupt Level bit 0 position. */ -#define EDMA_CH_TRNINTLVL1_bm (1<<1) /* Channel Transaction Complete Interrupt Level bit 1 mask. */ -#define EDMA_CH_TRNINTLVL1_bp 1 /* Channel Transaction Complete Interrupt Level bit 1 position. */ - -/* EDMA_CH.ADDRCTRL bit masks and bit positions */ -#define EDMA_CH_RELOAD_gm 0x30 /* Memory Address Reload for Peripheral Ch., or Source Address Reload for Standard Ch. group mask. */ -#define EDMA_CH_RELOAD_gp 4 /* Memory Address Reload for Peripheral Ch., or Source Address Reload for Standard Ch. group position. */ -#define EDMA_CH_RELOAD0_bm (1<<4) /* Memory Address Reload for Peripheral Ch., or Source Address Reload for Standard Ch. bit 0 mask. */ -#define EDMA_CH_RELOAD0_bp 4 /* Memory Address Reload for Peripheral Ch., or Source Address Reload for Standard Ch. bit 0 position. */ -#define EDMA_CH_RELOAD1_bm (1<<5) /* Memory Address Reload for Peripheral Ch., or Source Address Reload for Standard Ch. bit 1 mask. */ -#define EDMA_CH_RELOAD1_bp 5 /* Memory Address Reload for Peripheral Ch., or Source Address Reload for Standard Ch. bit 1 position. */ - -#define EDMA_CH_DIR_gm 0x07 /* Memory Address Mode for Peripheral Ch., or Source Address Mode for Standard Ch. group mask. */ -#define EDMA_CH_DIR_gp 0 /* Memory Address Mode for Peripheral Ch., or Source Address Mode for Standard Ch. group position. */ -#define EDMA_CH_DIR0_bm (1<<0) /* Memory Address Mode for Peripheral Ch., or Source Address Mode for Standard Ch. bit 0 mask. */ -#define EDMA_CH_DIR0_bp 0 /* Memory Address Mode for Peripheral Ch., or Source Address Mode for Standard Ch. bit 0 position. */ -#define EDMA_CH_DIR1_bm (1<<1) /* Memory Address Mode for Peripheral Ch., or Source Address Mode for Standard Ch. bit 1 mask. */ -#define EDMA_CH_DIR1_bp 1 /* Memory Address Mode for Peripheral Ch., or Source Address Mode for Standard Ch. bit 1 position. */ -#define EDMA_CH_DIR2_bm (1<<2) /* Memory Address Mode for Peripheral Ch., or Source Address Mode for Standard Ch. bit 2 mask. */ -#define EDMA_CH_DIR2_bp 2 /* Memory Address Mode for Peripheral Ch., or Source Address Mode for Standard Ch. bit 2 position. */ - -/* EDMA_CH.DESTADDRCTRL bit masks and bit positions */ -#define EDMA_CH_DESTRELOAD_gm 0x30 /* Destination Address Reload for Standard Channels Only. group mask. */ -#define EDMA_CH_DESTRELOAD_gp 4 /* Destination Address Reload for Standard Channels Only. group position. */ -#define EDMA_CH_DESTRELOAD0_bm (1<<4) /* Destination Address Reload for Standard Channels Only. bit 0 mask. */ -#define EDMA_CH_DESTRELOAD0_bp 4 /* Destination Address Reload for Standard Channels Only. bit 0 position. */ -#define EDMA_CH_DESTRELOAD1_bm (1<<5) /* Destination Address Reload for Standard Channels Only. bit 1 mask. */ -#define EDMA_CH_DESTRELOAD1_bp 5 /* Destination Address Reload for Standard Channels Only. bit 1 position. */ - -#define EDMA_CH_DESTDIR_gm 0x07 /* Destination Address Mode for Standard Channels Only. group mask. */ -#define EDMA_CH_DESTDIR_gp 0 /* Destination Address Mode for Standard Channels Only. group position. */ -#define EDMA_CH_DESTDIR0_bm (1<<0) /* Destination Address Mode for Standard Channels Only. bit 0 mask. */ -#define EDMA_CH_DESTDIR0_bp 0 /* Destination Address Mode for Standard Channels Only. bit 0 position. */ -#define EDMA_CH_DESTDIR1_bm (1<<1) /* Destination Address Mode for Standard Channels Only. bit 1 mask. */ -#define EDMA_CH_DESTDIR1_bp 1 /* Destination Address Mode for Standard Channels Only. bit 1 position. */ -#define EDMA_CH_DESTDIR2_bm (1<<2) /* Destination Address Mode for Standard Channels Only. bit 2 mask. */ -#define EDMA_CH_DESTDIR2_bp 2 /* Destination Address Mode for Standard Channels Only. bit 2 position. */ - -/* EDMA_CH.TRIGSRC bit masks and bit positions */ -#define EDMA_CH_TRIGSRC_gm 0xFF /* Channel Trigger Source group mask. */ -#define EDMA_CH_TRIGSRC_gp 0 /* Channel Trigger Source group position. */ -#define EDMA_CH_TRIGSRC0_bm (1<<0) /* Channel Trigger Source bit 0 mask. */ -#define EDMA_CH_TRIGSRC0_bp 0 /* Channel Trigger Source bit 0 position. */ -#define EDMA_CH_TRIGSRC1_bm (1<<1) /* Channel Trigger Source bit 1 mask. */ -#define EDMA_CH_TRIGSRC1_bp 1 /* Channel Trigger Source bit 1 position. */ -#define EDMA_CH_TRIGSRC2_bm (1<<2) /* Channel Trigger Source bit 2 mask. */ -#define EDMA_CH_TRIGSRC2_bp 2 /* Channel Trigger Source bit 2 position. */ -#define EDMA_CH_TRIGSRC3_bm (1<<3) /* Channel Trigger Source bit 3 mask. */ -#define EDMA_CH_TRIGSRC3_bp 3 /* Channel Trigger Source bit 3 position. */ -#define EDMA_CH_TRIGSRC4_bm (1<<4) /* Channel Trigger Source bit 4 mask. */ -#define EDMA_CH_TRIGSRC4_bp 4 /* Channel Trigger Source bit 4 position. */ -#define EDMA_CH_TRIGSRC5_bm (1<<5) /* Channel Trigger Source bit 5 mask. */ -#define EDMA_CH_TRIGSRC5_bp 5 /* Channel Trigger Source bit 5 position. */ -#define EDMA_CH_TRIGSRC6_bm (1<<6) /* Channel Trigger Source bit 6 mask. */ -#define EDMA_CH_TRIGSRC6_bp 6 /* Channel Trigger Source bit 6 position. */ -#define EDMA_CH_TRIGSRC7_bm (1<<7) /* Channel Trigger Source bit 7 mask. */ -#define EDMA_CH_TRIGSRC7_bp 7 /* Channel Trigger Source bit 7 position. */ - -/* EVSYS - Event System */ -/* EVSYS.CH0MUX bit masks and bit positions */ -#define EVSYS_CHMUX_gm 0xFF /* Event Channel 0 Multiplexer group mask. */ -#define EVSYS_CHMUX_gp 0 /* Event Channel 0 Multiplexer group position. */ -#define EVSYS_CHMUX0_bm (1<<0) /* Event Channel 0 Multiplexer bit 0 mask. */ -#define EVSYS_CHMUX0_bp 0 /* Event Channel 0 Multiplexer bit 0 position. */ -#define EVSYS_CHMUX1_bm (1<<1) /* Event Channel 0 Multiplexer bit 1 mask. */ -#define EVSYS_CHMUX1_bp 1 /* Event Channel 0 Multiplexer bit 1 position. */ -#define EVSYS_CHMUX2_bm (1<<2) /* Event Channel 0 Multiplexer bit 2 mask. */ -#define EVSYS_CHMUX2_bp 2 /* Event Channel 0 Multiplexer bit 2 position. */ -#define EVSYS_CHMUX3_bm (1<<3) /* Event Channel 0 Multiplexer bit 3 mask. */ -#define EVSYS_CHMUX3_bp 3 /* Event Channel 0 Multiplexer bit 3 position. */ -#define EVSYS_CHMUX4_bm (1<<4) /* Event Channel 0 Multiplexer bit 4 mask. */ -#define EVSYS_CHMUX4_bp 4 /* Event Channel 0 Multiplexer bit 4 position. */ -#define EVSYS_CHMUX5_bm (1<<5) /* Event Channel 0 Multiplexer bit 5 mask. */ -#define EVSYS_CHMUX5_bp 5 /* Event Channel 0 Multiplexer bit 5 position. */ -#define EVSYS_CHMUX6_bm (1<<6) /* Event Channel 0 Multiplexer bit 6 mask. */ -#define EVSYS_CHMUX6_bp 6 /* Event Channel 0 Multiplexer bit 6 position. */ -#define EVSYS_CHMUX7_bm (1<<7) /* Event Channel 0 Multiplexer bit 7 mask. */ -#define EVSYS_CHMUX7_bp 7 /* Event Channel 0 Multiplexer bit 7 position. */ - -/* EVSYS.CH1MUX bit masks and bit positions */ -/* EVSYS_CHMUX Predefined. */ -/* EVSYS_CHMUX Predefined. */ - -/* EVSYS.CH2MUX bit masks and bit positions */ -/* EVSYS_CHMUX Predefined. */ -/* EVSYS_CHMUX Predefined. */ - -/* EVSYS.CH3MUX bit masks and bit positions */ -/* EVSYS_CHMUX Predefined. */ -/* EVSYS_CHMUX Predefined. */ - -/* EVSYS.CH4MUX bit masks and bit positions */ -/* EVSYS_CHMUX Predefined. */ -/* EVSYS_CHMUX Predefined. */ - -/* EVSYS.CH5MUX bit masks and bit positions */ -/* EVSYS_CHMUX Predefined. */ -/* EVSYS_CHMUX Predefined. */ - -/* EVSYS.CH6MUX bit masks and bit positions */ -/* EVSYS_CHMUX Predefined. */ -/* EVSYS_CHMUX Predefined. */ - -/* EVSYS.CH7MUX bit masks and bit positions */ -/* EVSYS_CHMUX Predefined. */ -/* EVSYS_CHMUX Predefined. */ - -/* EVSYS.CH0CTRL bit masks and bit positions */ -#define EVSYS_ROTARY_bm 0x80 /* Rotary Decoder Enable bit mask. */ -#define EVSYS_ROTARY_bp 7 /* Rotary Decoder Enable bit position. */ - -#define EVSYS_QDIRM_gm 0x60 /* Quadrature Decoder Index Recognition Mode group mask. */ -#define EVSYS_QDIRM_gp 5 /* Quadrature Decoder Index Recognition Mode group position. */ -#define EVSYS_QDIRM0_bm (1<<5) /* Quadrature Decoder Index Recognition Mode bit 0 mask. */ -#define EVSYS_QDIRM0_bp 5 /* Quadrature Decoder Index Recognition Mode bit 0 position. */ -#define EVSYS_QDIRM1_bm (1<<6) /* Quadrature Decoder Index Recognition Mode bit 1 mask. */ -#define EVSYS_QDIRM1_bp 6 /* Quadrature Decoder Index Recognition Mode bit 1 position. */ - -#define EVSYS_QDIEN_bm 0x10 /* Quadrature Decoder Index Enable bit mask. */ -#define EVSYS_QDIEN_bp 4 /* Quadrature Decoder Index Enable bit position. */ - -#define EVSYS_QDEN_bm 0x08 /* Quadrature Decoder Enable bit mask. */ -#define EVSYS_QDEN_bp 3 /* Quadrature Decoder Enable bit position. */ - -#define EVSYS_DIGFILT_gm 0x07 /* Digital Filter group mask. */ -#define EVSYS_DIGFILT_gp 0 /* Digital Filter group position. */ -#define EVSYS_DIGFILT0_bm (1<<0) /* Digital Filter bit 0 mask. */ -#define EVSYS_DIGFILT0_bp 0 /* Digital Filter bit 0 position. */ -#define EVSYS_DIGFILT1_bm (1<<1) /* Digital Filter bit 1 mask. */ -#define EVSYS_DIGFILT1_bp 1 /* Digital Filter bit 1 position. */ -#define EVSYS_DIGFILT2_bm (1<<2) /* Digital Filter bit 2 mask. */ -#define EVSYS_DIGFILT2_bp 2 /* Digital Filter bit 2 position. */ - -/* EVSYS.CH1CTRL bit masks and bit positions */ -/* EVSYS_DIGFILT Predefined. */ -/* EVSYS_DIGFILT Predefined. */ - -/* EVSYS.CH2CTRL bit masks and bit positions */ -/* EVSYS_DIGFILT Predefined. */ -/* EVSYS_DIGFILT Predefined. */ - -/* EVSYS.CH3CTRL bit masks and bit positions */ -/* EVSYS_DIGFILT Predefined. */ -/* EVSYS_DIGFILT Predefined. */ - -/* EVSYS.CH4CTRL bit masks and bit positions */ -/* EVSYS_DIGFILT Predefined. */ -/* EVSYS_DIGFILT Predefined. */ - -/* EVSYS.CH5CTRL bit masks and bit positions */ -/* EVSYS_DIGFILT Predefined. */ -/* EVSYS_DIGFILT Predefined. */ - -/* EVSYS.CH6CTRL bit masks and bit positions */ -/* EVSYS_DIGFILT Predefined. */ -/* EVSYS_DIGFILT Predefined. */ - -/* EVSYS.CH7CTRL bit masks and bit positions */ -/* EVSYS_DIGFILT Predefined. */ -/* EVSYS_DIGFILT Predefined. */ - -/* EVSYS.DFCTRL bit masks and bit positions */ -#define EVSYS_PRESCFILT_gm 0xF0 /* Prescaler Filter group mask. */ -#define EVSYS_PRESCFILT_gp 4 /* Prescaler Filter group position. */ -#define EVSYS_PRESCFILT0_bm (1<<4) /* Prescaler Filter bit 0 mask. */ -#define EVSYS_PRESCFILT0_bp 4 /* Prescaler Filter bit 0 position. */ -#define EVSYS_PRESCFILT1_bm (1<<5) /* Prescaler Filter bit 1 mask. */ -#define EVSYS_PRESCFILT1_bp 5 /* Prescaler Filter bit 1 position. */ -#define EVSYS_PRESCFILT2_bm (1<<6) /* Prescaler Filter bit 2 mask. */ -#define EVSYS_PRESCFILT2_bp 6 /* Prescaler Filter bit 2 position. */ -#define EVSYS_PRESCFILT3_bm (1<<7) /* Prescaler Filter bit 3 mask. */ -#define EVSYS_PRESCFILT3_bp 7 /* Prescaler Filter bit 3 position. */ - -#define EVSYS_FILTSEL_bm 0x08 /* Prescaler Filter Select bit mask. */ -#define EVSYS_FILTSEL_bp 3 /* Prescaler Filter Select bit position. */ - -#define EVSYS_PRESC_gm 0x07 /* Prescaler group mask. */ -#define EVSYS_PRESC_gp 0 /* Prescaler group position. */ -#define EVSYS_PRESC0_bm (1<<0) /* Prescaler bit 0 mask. */ -#define EVSYS_PRESC0_bp 0 /* Prescaler bit 0 position. */ -#define EVSYS_PRESC1_bm (1<<1) /* Prescaler bit 1 mask. */ -#define EVSYS_PRESC1_bp 1 /* Prescaler bit 1 position. */ -#define EVSYS_PRESC2_bm (1<<2) /* Prescaler bit 2 mask. */ -#define EVSYS_PRESC2_bp 2 /* Prescaler bit 2 position. */ - -/* NVM - Non Volatile Memory Controller */ -/* NVM.CMD bit masks and bit positions */ -#define NVM_CMD_gm 0x7F /* Command group mask. */ -#define NVM_CMD_gp 0 /* Command group position. */ -#define NVM_CMD0_bm (1<<0) /* Command bit 0 mask. */ -#define NVM_CMD0_bp 0 /* Command bit 0 position. */ -#define NVM_CMD1_bm (1<<1) /* Command bit 1 mask. */ -#define NVM_CMD1_bp 1 /* Command bit 1 position. */ -#define NVM_CMD2_bm (1<<2) /* Command bit 2 mask. */ -#define NVM_CMD2_bp 2 /* Command bit 2 position. */ -#define NVM_CMD3_bm (1<<3) /* Command bit 3 mask. */ -#define NVM_CMD3_bp 3 /* Command bit 3 position. */ -#define NVM_CMD4_bm (1<<4) /* Command bit 4 mask. */ -#define NVM_CMD4_bp 4 /* Command bit 4 position. */ -#define NVM_CMD5_bm (1<<5) /* Command bit 5 mask. */ -#define NVM_CMD5_bp 5 /* Command bit 5 position. */ -#define NVM_CMD6_bm (1<<6) /* Command bit 6 mask. */ -#define NVM_CMD6_bp 6 /* Command bit 6 position. */ - -/* NVM.CTRLA bit masks and bit positions */ -#define NVM_CMDEX_bm 0x01 /* Command Execute bit mask. */ -#define NVM_CMDEX_bp 0 /* Command Execute bit position. */ - -/* NVM.CTRLB bit masks and bit positions */ -#define NVM_EPRM_bm 0x02 /* EEPROM Power Reduction Enable bit mask. */ -#define NVM_EPRM_bp 1 /* EEPROM Power Reduction Enable bit position. */ - -#define NVM_SPMLOCK_bm 0x01 /* SPM Lock bit mask. */ -#define NVM_SPMLOCK_bp 0 /* SPM Lock bit position. */ - -/* NVM.INTCTRL bit masks and bit positions */ -#define NVM_SPMLVL_gm 0x0C /* SPM Interrupt Level group mask. */ -#define NVM_SPMLVL_gp 2 /* SPM Interrupt Level group position. */ -#define NVM_SPMLVL0_bm (1<<2) /* SPM Interrupt Level bit 0 mask. */ -#define NVM_SPMLVL0_bp 2 /* SPM Interrupt Level bit 0 position. */ -#define NVM_SPMLVL1_bm (1<<3) /* SPM Interrupt Level bit 1 mask. */ -#define NVM_SPMLVL1_bp 3 /* SPM Interrupt Level bit 1 position. */ - -#define NVM_EELVL_gm 0x03 /* EEPROM Interrupt Level group mask. */ -#define NVM_EELVL_gp 0 /* EEPROM Interrupt Level group position. */ -#define NVM_EELVL0_bm (1<<0) /* EEPROM Interrupt Level bit 0 mask. */ -#define NVM_EELVL0_bp 0 /* EEPROM Interrupt Level bit 0 position. */ -#define NVM_EELVL1_bm (1<<1) /* EEPROM Interrupt Level bit 1 mask. */ -#define NVM_EELVL1_bp 1 /* EEPROM Interrupt Level bit 1 position. */ - -/* NVM.STATUS bit masks and bit positions */ -#define NVM_NVMBUSY_bm 0x80 /* Non-volatile Memory Busy bit mask. */ -#define NVM_NVMBUSY_bp 7 /* Non-volatile Memory Busy bit position. */ - -#define NVM_FBUSY_bm 0x40 /* Flash Memory Busy bit mask. */ -#define NVM_FBUSY_bp 6 /* Flash Memory Busy bit position. */ - -#define NVM_EELOAD_bm 0x02 /* EEPROM Page Buffer Active Loading bit mask. */ -#define NVM_EELOAD_bp 1 /* EEPROM Page Buffer Active Loading bit position. */ - -#define NVM_FLOAD_bm 0x01 /* Flash Page Buffer Active Loading bit mask. */ -#define NVM_FLOAD_bp 0 /* Flash Page Buffer Active Loading bit position. */ - -/* NVM.LOCKBITS bit masks and bit positions */ -#define NVM_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ -#define NVM_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ -#define NVM_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ -#define NVM_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ -#define NVM_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ -#define NVM_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ - -#define NVM_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ -#define NVM_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ -#define NVM_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ -#define NVM_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ -#define NVM_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ -#define NVM_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ - -#define NVM_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ -#define NVM_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ -#define NVM_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ -#define NVM_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ -#define NVM_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ -#define NVM_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ - -#define NVM_LB_gm 0x03 /* Lock Bits group mask. */ -#define NVM_LB_gp 0 /* Lock Bits group position. */ -#define NVM_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ -#define NVM_LB0_bp 0 /* Lock Bits bit 0 position. */ -#define NVM_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ -#define NVM_LB1_bp 1 /* Lock Bits bit 1 position. */ - -/* ADC - Analog/Digital Converter */ -/* ADC_CH.CTRL bit masks and bit positions */ -#define ADC_CH_START_bm 0x80 /* Channel Start Conversion bit mask. */ -#define ADC_CH_START_bp 7 /* Channel Start Conversion bit position. */ - -#define ADC_CH_GAIN_gm 0x1C /* Gain Factor group mask. */ -#define ADC_CH_GAIN_gp 2 /* Gain Factor group position. */ -#define ADC_CH_GAIN0_bm (1<<2) /* Gain Factor bit 0 mask. */ -#define ADC_CH_GAIN0_bp 2 /* Gain Factor bit 0 position. */ -#define ADC_CH_GAIN1_bm (1<<3) /* Gain Factor bit 1 mask. */ -#define ADC_CH_GAIN1_bp 3 /* Gain Factor bit 1 position. */ -#define ADC_CH_GAIN2_bm (1<<4) /* Gain Factor bit 2 mask. */ -#define ADC_CH_GAIN2_bp 4 /* Gain Factor bit 2 position. */ - -#define ADC_CH_INPUTMODE_gm 0x03 /* Input Mode Select group mask. */ -#define ADC_CH_INPUTMODE_gp 0 /* Input Mode Select group position. */ -#define ADC_CH_INPUTMODE0_bm (1<<0) /* Input Mode Select bit 0 mask. */ -#define ADC_CH_INPUTMODE0_bp 0 /* Input Mode Select bit 0 position. */ -#define ADC_CH_INPUTMODE1_bm (1<<1) /* Input Mode Select bit 1 mask. */ -#define ADC_CH_INPUTMODE1_bp 1 /* Input Mode Select bit 1 position. */ - -/* ADC_CH.MUXCTRL bit masks and bit positions */ -#define ADC_CH_MUXPOS_gm 0x78 /* MUX selection on Positive ADC Input group mask. */ -#define ADC_CH_MUXPOS_gp 3 /* MUX selection on Positive ADC Input group position. */ -#define ADC_CH_MUXPOS0_bm (1<<3) /* MUX selection on Positive ADC Input bit 0 mask. */ -#define ADC_CH_MUXPOS0_bp 3 /* MUX selection on Positive ADC Input bit 0 position. */ -#define ADC_CH_MUXPOS1_bm (1<<4) /* MUX selection on Positive ADC Input bit 1 mask. */ -#define ADC_CH_MUXPOS1_bp 4 /* MUX selection on Positive ADC Input bit 1 position. */ -#define ADC_CH_MUXPOS2_bm (1<<5) /* MUX selection on Positive ADC Input bit 2 mask. */ -#define ADC_CH_MUXPOS2_bp 5 /* MUX selection on Positive ADC Input bit 2 position. */ -#define ADC_CH_MUXPOS3_bm (1<<6) /* MUX selection on Positive ADC Input bit 3 mask. */ -#define ADC_CH_MUXPOS3_bp 6 /* MUX selection on Positive ADC Input bit 3 position. */ - -#define ADC_CH_MUXINT_gm 0x78 /* MUX selection on Internal ADC Input group mask. */ -#define ADC_CH_MUXINT_gp 3 /* MUX selection on Internal ADC Input group position. */ -#define ADC_CH_MUXINT0_bm (1<<3) /* MUX selection on Internal ADC Input bit 0 mask. */ -#define ADC_CH_MUXINT0_bp 3 /* MUX selection on Internal ADC Input bit 0 position. */ -#define ADC_CH_MUXINT1_bm (1<<4) /* MUX selection on Internal ADC Input bit 1 mask. */ -#define ADC_CH_MUXINT1_bp 4 /* MUX selection on Internal ADC Input bit 1 position. */ -#define ADC_CH_MUXINT2_bm (1<<5) /* MUX selection on Internal ADC Input bit 2 mask. */ -#define ADC_CH_MUXINT2_bp 5 /* MUX selection on Internal ADC Input bit 2 position. */ -#define ADC_CH_MUXINT3_bm (1<<6) /* MUX selection on Internal ADC Input bit 3 mask. */ -#define ADC_CH_MUXINT3_bp 6 /* MUX selection on Internal ADC Input bit 3 position. */ - -#define ADC_CH_MUXNEG_gm 0x03 /* MUX selection on Negative ADC Input group mask. */ -#define ADC_CH_MUXNEG_gp 0 /* MUX selection on Negative ADC Input group position. */ -#define ADC_CH_MUXNEG0_bm (1<<0) /* MUX selection on Negative ADC Input bit 0 mask. */ -#define ADC_CH_MUXNEG0_bp 0 /* MUX selection on Negative ADC Input bit 0 position. */ -#define ADC_CH_MUXNEG1_bm (1<<1) /* MUX selection on Negative ADC Input bit 1 mask. */ -#define ADC_CH_MUXNEG1_bp 1 /* MUX selection on Negative ADC Input bit 1 position. */ - -#define ADC_CH_MUXNEGL_gm 0x03 /* MUX selection on Negative ADC Input Gain on 4 LSB pins group mask. */ -#define ADC_CH_MUXNEGL_gp 0 /* MUX selection on Negative ADC Input Gain on 4 LSB pins group position. */ -#define ADC_CH_MUXNEGL0_bm (1<<0) /* MUX selection on Negative ADC Input Gain on 4 LSB pins bit 0 mask. */ -#define ADC_CH_MUXNEGL0_bp 0 /* MUX selection on Negative ADC Input Gain on 4 LSB pins bit 0 position. */ -#define ADC_CH_MUXNEGL1_bm (1<<1) /* MUX selection on Negative ADC Input Gain on 4 LSB pins bit 1 mask. */ -#define ADC_CH_MUXNEGL1_bp 1 /* MUX selection on Negative ADC Input Gain on 4 LSB pins bit 1 position. */ - -#define ADC_CH_MUXNEGH_gm 0x03 /* MUX selection on Negative ADC Input Gain on 4 MSB pins group mask. */ -#define ADC_CH_MUXNEGH_gp 0 /* MUX selection on Negative ADC Input Gain on 4 MSB pins group position. */ -#define ADC_CH_MUXNEGH0_bm (1<<0) /* MUX selection on Negative ADC Input Gain on 4 MSB pins bit 0 mask. */ -#define ADC_CH_MUXNEGH0_bp 0 /* MUX selection on Negative ADC Input Gain on 4 MSB pins bit 0 position. */ -#define ADC_CH_MUXNEGH1_bm (1<<1) /* MUX selection on Negative ADC Input Gain on 4 MSB pins bit 1 mask. */ -#define ADC_CH_MUXNEGH1_bp 1 /* MUX selection on Negative ADC Input Gain on 4 MSB pins bit 1 position. */ - -/* ADC_CH.INTCTRL bit masks and bit positions */ -#define ADC_CH_INTMODE_gm 0x0C /* Interrupt Mode group mask. */ -#define ADC_CH_INTMODE_gp 2 /* Interrupt Mode group position. */ -#define ADC_CH_INTMODE0_bm (1<<2) /* Interrupt Mode bit 0 mask. */ -#define ADC_CH_INTMODE0_bp 2 /* Interrupt Mode bit 0 position. */ -#define ADC_CH_INTMODE1_bm (1<<3) /* Interrupt Mode bit 1 mask. */ -#define ADC_CH_INTMODE1_bp 3 /* Interrupt Mode bit 1 position. */ - -#define ADC_CH_INTLVL_gm 0x03 /* Interrupt Level group mask. */ -#define ADC_CH_INTLVL_gp 0 /* Interrupt Level group position. */ -#define ADC_CH_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */ -#define ADC_CH_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */ -#define ADC_CH_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ -#define ADC_CH_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */ - -/* ADC_CH.INTFLAGS bit masks and bit positions */ -#define ADC_CH_IF_bm 0x01 /* Channel Interrupt Flag bit mask. */ -#define ADC_CH_IF_bp 0 /* Channel Interrupt Flag bit position. */ - -/* ADC_CH.SCAN bit masks and bit positions */ -#define ADC_CH_INPUTOFFSET_gm 0xF0 /* Positive MUX Setting Offset group mask. */ -#define ADC_CH_INPUTOFFSET_gp 4 /* Positive MUX Setting Offset group position. */ -#define ADC_CH_INPUTOFFSET0_bm (1<<4) /* Positive MUX Setting Offset bit 0 mask. */ -#define ADC_CH_INPUTOFFSET0_bp 4 /* Positive MUX Setting Offset bit 0 position. */ -#define ADC_CH_INPUTOFFSET1_bm (1<<5) /* Positive MUX Setting Offset bit 1 mask. */ -#define ADC_CH_INPUTOFFSET1_bp 5 /* Positive MUX Setting Offset bit 1 position. */ -#define ADC_CH_INPUTOFFSET2_bm (1<<6) /* Positive MUX Setting Offset bit 2 mask. */ -#define ADC_CH_INPUTOFFSET2_bp 6 /* Positive MUX Setting Offset bit 2 position. */ -#define ADC_CH_INPUTOFFSET3_bm (1<<7) /* Positive MUX Setting Offset bit 3 mask. */ -#define ADC_CH_INPUTOFFSET3_bp 7 /* Positive MUX Setting Offset bit 3 position. */ - -#define ADC_CH_INPUTSCAN_gm 0x0F /* Number of Channels Included in Scan group mask. */ -#define ADC_CH_INPUTSCAN_gp 0 /* Number of Channels Included in Scan group position. */ -#define ADC_CH_INPUTSCAN0_bm (1<<0) /* Number of Channels Included in Scan bit 0 mask. */ -#define ADC_CH_INPUTSCAN0_bp 0 /* Number of Channels Included in Scan bit 0 position. */ -#define ADC_CH_INPUTSCAN1_bm (1<<1) /* Number of Channels Included in Scan bit 1 mask. */ -#define ADC_CH_INPUTSCAN1_bp 1 /* Number of Channels Included in Scan bit 1 position. */ -#define ADC_CH_INPUTSCAN2_bm (1<<2) /* Number of Channels Included in Scan bit 2 mask. */ -#define ADC_CH_INPUTSCAN2_bp 2 /* Number of Channels Included in Scan bit 2 position. */ -#define ADC_CH_INPUTSCAN3_bm (1<<3) /* Number of Channels Included in Scan bit 3 mask. */ -#define ADC_CH_INPUTSCAN3_bp 3 /* Number of Channels Included in Scan bit 3 position. */ - -/* ADC_CH.CORRCTRL bit masks and bit positions */ -#define ADC_CH_CORREN_bm 0x01 /* Correction Enable bit mask. */ -#define ADC_CH_CORREN_bp 0 /* Correction Enable bit position. */ - -/* ADC_CH.OFFSETCORR1 bit masks and bit positions */ -#define ADC_CH_OFFSETCORR_gm 0x0F /* Offset Correction Byte 1 group mask. */ -#define ADC_CH_OFFSETCORR_gp 0 /* Offset Correction Byte 1 group position. */ -#define ADC_CH_OFFSETCORR0_bm (1<<0) /* Offset Correction Byte 1 bit 0 mask. */ -#define ADC_CH_OFFSETCORR0_bp 0 /* Offset Correction Byte 1 bit 0 position. */ -#define ADC_CH_OFFSETCORR1_bm (1<<1) /* Offset Correction Byte 1 bit 1 mask. */ -#define ADC_CH_OFFSETCORR1_bp 1 /* Offset Correction Byte 1 bit 1 position. */ -#define ADC_CH_OFFSETCORR2_bm (1<<2) /* Offset Correction Byte 1 bit 2 mask. */ -#define ADC_CH_OFFSETCORR2_bp 2 /* Offset Correction Byte 1 bit 2 position. */ -#define ADC_CH_OFFSETCORR3_bm (1<<3) /* Offset Correction Byte 1 bit 3 mask. */ -#define ADC_CH_OFFSETCORR3_bp 3 /* Offset Correction Byte 1 bit 3 position. */ - -/* ADC_CH.GAINCORR1 bit masks and bit positions */ -#define ADC_CH_GAINCORR_gm 0x0F /* Gain Correction Byte 1 group mask. */ -#define ADC_CH_GAINCORR_gp 0 /* Gain Correction Byte 1 group position. */ -#define ADC_CH_GAINCORR0_bm (1<<0) /* Gain Correction Byte 1 bit 0 mask. */ -#define ADC_CH_GAINCORR0_bp 0 /* Gain Correction Byte 1 bit 0 position. */ -#define ADC_CH_GAINCORR1_bm (1<<1) /* Gain Correction Byte 1 bit 1 mask. */ -#define ADC_CH_GAINCORR1_bp 1 /* Gain Correction Byte 1 bit 1 position. */ -#define ADC_CH_GAINCORR2_bm (1<<2) /* Gain Correction Byte 1 bit 2 mask. */ -#define ADC_CH_GAINCORR2_bp 2 /* Gain Correction Byte 1 bit 2 position. */ -#define ADC_CH_GAINCORR3_bm (1<<3) /* Gain Correction Byte 1 bit 3 mask. */ -#define ADC_CH_GAINCORR3_bp 3 /* Gain Correction Byte 1 bit 3 position. */ - -/* ADC_CH.AVGCTRL bit masks and bit positions */ -#define ADC_CH_RIGHTSHIFT_gm 0x70 /* Right Shift group mask. */ -#define ADC_CH_RIGHTSHIFT_gp 4 /* Right Shift group position. */ -#define ADC_CH_RIGHTSHIFT0_bm (1<<4) /* Right Shift bit 0 mask. */ -#define ADC_CH_RIGHTSHIFT0_bp 4 /* Right Shift bit 0 position. */ -#define ADC_CH_RIGHTSHIFT1_bm (1<<5) /* Right Shift bit 1 mask. */ -#define ADC_CH_RIGHTSHIFT1_bp 5 /* Right Shift bit 1 position. */ -#define ADC_CH_RIGHTSHIFT2_bm (1<<6) /* Right Shift bit 2 mask. */ -#define ADC_CH_RIGHTSHIFT2_bp 6 /* Right Shift bit 2 position. */ - -#define ADC_CH_SAMPNUM_gm 0x0F /* Averaged Number of Samples group mask. */ -#define ADC_CH_SAMPNUM_gp 0 /* Averaged Number of Samples group position. */ -#define ADC_CH_SAMPNUM0_bm (1<<0) /* Averaged Number of Samples bit 0 mask. */ -#define ADC_CH_SAMPNUM0_bp 0 /* Averaged Number of Samples bit 0 position. */ -#define ADC_CH_SAMPNUM1_bm (1<<1) /* Averaged Number of Samples bit 1 mask. */ -#define ADC_CH_SAMPNUM1_bp 1 /* Averaged Number of Samples bit 1 position. */ -#define ADC_CH_SAMPNUM2_bm (1<<2) /* Averaged Number of Samples bit 2 mask. */ -#define ADC_CH_SAMPNUM2_bp 2 /* Averaged Number of Samples bit 2 position. */ -#define ADC_CH_SAMPNUM3_bm (1<<3) /* Averaged Number of Samples bit 3 mask. */ -#define ADC_CH_SAMPNUM3_bp 3 /* Averaged Number of Samples bit 3 position. */ - -/* ADC.CTRLA bit masks and bit positions */ -#define ADC_START_bm 0x04 /* Start Conversion bit mask. */ -#define ADC_START_bp 2 /* Start Conversion bit position. */ - -#define ADC_FLUSH_bm 0x02 /* ADC Flush bit mask. */ -#define ADC_FLUSH_bp 1 /* ADC Flush bit position. */ - -#define ADC_ENABLE_bm 0x01 /* Enable ADC bit mask. */ -#define ADC_ENABLE_bp 0 /* Enable ADC bit position. */ - -/* ADC.CTRLB bit masks and bit positions */ -#define ADC_CURRLIMIT_gm 0x60 /* Current Limitation group mask. */ -#define ADC_CURRLIMIT_gp 5 /* Current Limitation group position. */ -#define ADC_CURRLIMIT0_bm (1<<5) /* Current Limitation bit 0 mask. */ -#define ADC_CURRLIMIT0_bp 5 /* Current Limitation bit 0 position. */ -#define ADC_CURRLIMIT1_bm (1<<6) /* Current Limitation bit 1 mask. */ -#define ADC_CURRLIMIT1_bp 6 /* Current Limitation bit 1 position. */ - -#define ADC_CONMODE_bm 0x10 /* Conversion Mode bit mask. */ -#define ADC_CONMODE_bp 4 /* Conversion Mode bit position. */ - -#define ADC_FREERUN_bm 0x08 /* Free Running Mode Enable bit mask. */ -#define ADC_FREERUN_bp 3 /* Free Running Mode Enable bit position. */ - -#define ADC_RESOLUTION_gm 0x06 /* Result Resolution group mask. */ -#define ADC_RESOLUTION_gp 1 /* Result Resolution group position. */ -#define ADC_RESOLUTION0_bm (1<<1) /* Result Resolution bit 0 mask. */ -#define ADC_RESOLUTION0_bp 1 /* Result Resolution bit 0 position. */ -#define ADC_RESOLUTION1_bm (1<<2) /* Result Resolution bit 1 mask. */ -#define ADC_RESOLUTION1_bp 2 /* Result Resolution bit 1 position. */ - -/* ADC.REFCTRL bit masks and bit positions */ -#define ADC_REFSEL_gm 0x70 /* Reference Selection group mask. */ -#define ADC_REFSEL_gp 4 /* Reference Selection group position. */ -#define ADC_REFSEL0_bm (1<<4) /* Reference Selection bit 0 mask. */ -#define ADC_REFSEL0_bp 4 /* Reference Selection bit 0 position. */ -#define ADC_REFSEL1_bm (1<<5) /* Reference Selection bit 1 mask. */ -#define ADC_REFSEL1_bp 5 /* Reference Selection bit 1 position. */ -#define ADC_REFSEL2_bm (1<<6) /* Reference Selection bit 2 mask. */ -#define ADC_REFSEL2_bp 6 /* Reference Selection bit 2 position. */ - -#define ADC_BANDGAP_bm 0x02 /* Bandgap enable bit mask. */ -#define ADC_BANDGAP_bp 1 /* Bandgap enable bit position. */ - -#define ADC_TEMPREF_bm 0x01 /* Temperature Reference Enable bit mask. */ -#define ADC_TEMPREF_bp 0 /* Temperature Reference Enable bit position. */ - -/* ADC.EVCTRL bit masks and bit positions */ -#define ADC_EVSEL_gm 0x38 /* Event Input Select group mask. */ -#define ADC_EVSEL_gp 3 /* Event Input Select group position. */ -#define ADC_EVSEL0_bm (1<<3) /* Event Input Select bit 0 mask. */ -#define ADC_EVSEL0_bp 3 /* Event Input Select bit 0 position. */ -#define ADC_EVSEL1_bm (1<<4) /* Event Input Select bit 1 mask. */ -#define ADC_EVSEL1_bp 4 /* Event Input Select bit 1 position. */ -#define ADC_EVSEL2_bm (1<<5) /* Event Input Select bit 2 mask. */ -#define ADC_EVSEL2_bp 5 /* Event Input Select bit 2 position. */ - -#define ADC_EVACT_gm 0x07 /* Event Action Select group mask. */ -#define ADC_EVACT_gp 0 /* Event Action Select group position. */ -#define ADC_EVACT0_bm (1<<0) /* Event Action Select bit 0 mask. */ -#define ADC_EVACT0_bp 0 /* Event Action Select bit 0 position. */ -#define ADC_EVACT1_bm (1<<1) /* Event Action Select bit 1 mask. */ -#define ADC_EVACT1_bp 1 /* Event Action Select bit 1 position. */ -#define ADC_EVACT2_bm (1<<2) /* Event Action Select bit 2 mask. */ -#define ADC_EVACT2_bp 2 /* Event Action Select bit 2 position. */ - -/* ADC.PRESCALER bit masks and bit positions */ -#define ADC_PRESCALER_gm 0x07 /* Clock Prescaler Selection group mask. */ -#define ADC_PRESCALER_gp 0 /* Clock Prescaler Selection group position. */ -#define ADC_PRESCALER0_bm (1<<0) /* Clock Prescaler Selection bit 0 mask. */ -#define ADC_PRESCALER0_bp 0 /* Clock Prescaler Selection bit 0 position. */ -#define ADC_PRESCALER1_bm (1<<1) /* Clock Prescaler Selection bit 1 mask. */ -#define ADC_PRESCALER1_bp 1 /* Clock Prescaler Selection bit 1 position. */ -#define ADC_PRESCALER2_bm (1<<2) /* Clock Prescaler Selection bit 2 mask. */ -#define ADC_PRESCALER2_bp 2 /* Clock Prescaler Selection bit 2 position. */ - -/* ADC.INTFLAGS bit masks and bit positions */ -#define ADC_CH0IF_bm 0x01 /* Channel 0 Interrupt Flag bit mask. */ -#define ADC_CH0IF_bp 0 /* Channel 0 Interrupt Flag bit position. */ - -/* ADC.SAMPCTRL bit masks and bit positions */ -#define ADC_SAMPVAL_gm 0x3F /* Sampling time control register group mask. */ -#define ADC_SAMPVAL_gp 0 /* Sampling time control register group position. */ -#define ADC_SAMPVAL0_bm (1<<0) /* Sampling time control register bit 0 mask. */ -#define ADC_SAMPVAL0_bp 0 /* Sampling time control register bit 0 position. */ -#define ADC_SAMPVAL1_bm (1<<1) /* Sampling time control register bit 1 mask. */ -#define ADC_SAMPVAL1_bp 1 /* Sampling time control register bit 1 position. */ -#define ADC_SAMPVAL2_bm (1<<2) /* Sampling time control register bit 2 mask. */ -#define ADC_SAMPVAL2_bp 2 /* Sampling time control register bit 2 position. */ -#define ADC_SAMPVAL3_bm (1<<3) /* Sampling time control register bit 3 mask. */ -#define ADC_SAMPVAL3_bp 3 /* Sampling time control register bit 3 position. */ -#define ADC_SAMPVAL4_bm (1<<4) /* Sampling time control register bit 4 mask. */ -#define ADC_SAMPVAL4_bp 4 /* Sampling time control register bit 4 position. */ -#define ADC_SAMPVAL5_bm (1<<5) /* Sampling time control register bit 5 mask. */ -#define ADC_SAMPVAL5_bp 5 /* Sampling time control register bit 5 position. */ - -/* DAC - Digital/Analog Converter */ -/* DAC.CTRLA bit masks and bit positions */ -#define DAC_IDOEN_bm 0x10 /* Internal Output Enable bit mask. */ -#define DAC_IDOEN_bp 4 /* Internal Output Enable bit position. */ - -#define DAC_CH1EN_bm 0x08 /* Channel 1 Output Enable bit mask. */ -#define DAC_CH1EN_bp 3 /* Channel 1 Output Enable bit position. */ - -#define DAC_CH0EN_bm 0x04 /* Channel 0 Output Enable bit mask. */ -#define DAC_CH0EN_bp 2 /* Channel 0 Output Enable bit position. */ - -#define DAC_LPMODE_bm 0x02 /* Low Power Mode bit mask. */ -#define DAC_LPMODE_bp 1 /* Low Power Mode bit position. */ - -#define DAC_ENABLE_bm 0x01 /* Enable bit mask. */ -#define DAC_ENABLE_bp 0 /* Enable bit position. */ - -/* DAC.CTRLB bit masks and bit positions */ -#define DAC_CHSEL_gm 0x60 /* Channel Select group mask. */ -#define DAC_CHSEL_gp 5 /* Channel Select group position. */ -#define DAC_CHSEL0_bm (1<<5) /* Channel Select bit 0 mask. */ -#define DAC_CHSEL0_bp 5 /* Channel Select bit 0 position. */ -#define DAC_CHSEL1_bm (1<<6) /* Channel Select bit 1 mask. */ -#define DAC_CHSEL1_bp 6 /* Channel Select bit 1 position. */ - -#define DAC_CH1TRIG_bm 0x02 /* Channel 1 Event Trig Enable bit mask. */ -#define DAC_CH1TRIG_bp 1 /* Channel 1 Event Trig Enable bit position. */ - -#define DAC_CH0TRIG_bm 0x01 /* Channel 0 Event Trig Enable bit mask. */ -#define DAC_CH0TRIG_bp 0 /* Channel 0 Event Trig Enable bit position. */ - -/* DAC.CTRLC bit masks and bit positions */ -#define DAC_REFSEL_gm 0x18 /* Reference Select group mask. */ -#define DAC_REFSEL_gp 3 /* Reference Select group position. */ -#define DAC_REFSEL0_bm (1<<3) /* Reference Select bit 0 mask. */ -#define DAC_REFSEL0_bp 3 /* Reference Select bit 0 position. */ -#define DAC_REFSEL1_bm (1<<4) /* Reference Select bit 1 mask. */ -#define DAC_REFSEL1_bp 4 /* Reference Select bit 1 position. */ - -#define DAC_LEFTADJ_bm 0x01 /* Left-adjust Result bit mask. */ -#define DAC_LEFTADJ_bp 0 /* Left-adjust Result bit position. */ - -/* DAC.EVCTRL bit masks and bit positions */ -#define DAC_EVSPLIT_bm 0x08 /* Separate Event Channel Input for Channel 1 bit mask. */ -#define DAC_EVSPLIT_bp 3 /* Separate Event Channel Input for Channel 1 bit position. */ - -#define DAC_EVSEL_gm 0x07 /* Event Input Selection group mask. */ -#define DAC_EVSEL_gp 0 /* Event Input Selection group position. */ -#define DAC_EVSEL0_bm (1<<0) /* Event Input Selection bit 0 mask. */ -#define DAC_EVSEL0_bp 0 /* Event Input Selection bit 0 position. */ -#define DAC_EVSEL1_bm (1<<1) /* Event Input Selection bit 1 mask. */ -#define DAC_EVSEL1_bp 1 /* Event Input Selection bit 1 position. */ -#define DAC_EVSEL2_bm (1<<2) /* Event Input Selection bit 2 mask. */ -#define DAC_EVSEL2_bp 2 /* Event Input Selection bit 2 position. */ - -/* DAC.STATUS bit masks and bit positions */ -#define DAC_CH1DRE_bm 0x02 /* Channel 1 Data Register Empty bit mask. */ -#define DAC_CH1DRE_bp 1 /* Channel 1 Data Register Empty bit position. */ - -#define DAC_CH0DRE_bm 0x01 /* Channel 0 Data Register Empty bit mask. */ -#define DAC_CH0DRE_bp 0 /* Channel 0 Data Register Empty bit position. */ - -/* DAC.CH0GAINCAL bit masks and bit positions */ -#define DAC_CH0GAINCAL_gm 0x7F /* Gain Calibration group mask. */ -#define DAC_CH0GAINCAL_gp 0 /* Gain Calibration group position. */ -#define DAC_CH0GAINCAL0_bm (1<<0) /* Gain Calibration bit 0 mask. */ -#define DAC_CH0GAINCAL0_bp 0 /* Gain Calibration bit 0 position. */ -#define DAC_CH0GAINCAL1_bm (1<<1) /* Gain Calibration bit 1 mask. */ -#define DAC_CH0GAINCAL1_bp 1 /* Gain Calibration bit 1 position. */ -#define DAC_CH0GAINCAL2_bm (1<<2) /* Gain Calibration bit 2 mask. */ -#define DAC_CH0GAINCAL2_bp 2 /* Gain Calibration bit 2 position. */ -#define DAC_CH0GAINCAL3_bm (1<<3) /* Gain Calibration bit 3 mask. */ -#define DAC_CH0GAINCAL3_bp 3 /* Gain Calibration bit 3 position. */ -#define DAC_CH0GAINCAL4_bm (1<<4) /* Gain Calibration bit 4 mask. */ -#define DAC_CH0GAINCAL4_bp 4 /* Gain Calibration bit 4 position. */ -#define DAC_CH0GAINCAL5_bm (1<<5) /* Gain Calibration bit 5 mask. */ -#define DAC_CH0GAINCAL5_bp 5 /* Gain Calibration bit 5 position. */ -#define DAC_CH0GAINCAL6_bm (1<<6) /* Gain Calibration bit 6 mask. */ -#define DAC_CH0GAINCAL6_bp 6 /* Gain Calibration bit 6 position. */ - -/* DAC.CH0OFFSETCAL bit masks and bit positions */ -#define DAC_CH0OFFSETCAL_gm 0x7F /* Offset Calibration group mask. */ -#define DAC_CH0OFFSETCAL_gp 0 /* Offset Calibration group position. */ -#define DAC_CH0OFFSETCAL0_bm (1<<0) /* Offset Calibration bit 0 mask. */ -#define DAC_CH0OFFSETCAL0_bp 0 /* Offset Calibration bit 0 position. */ -#define DAC_CH0OFFSETCAL1_bm (1<<1) /* Offset Calibration bit 1 mask. */ -#define DAC_CH0OFFSETCAL1_bp 1 /* Offset Calibration bit 1 position. */ -#define DAC_CH0OFFSETCAL2_bm (1<<2) /* Offset Calibration bit 2 mask. */ -#define DAC_CH0OFFSETCAL2_bp 2 /* Offset Calibration bit 2 position. */ -#define DAC_CH0OFFSETCAL3_bm (1<<3) /* Offset Calibration bit 3 mask. */ -#define DAC_CH0OFFSETCAL3_bp 3 /* Offset Calibration bit 3 position. */ -#define DAC_CH0OFFSETCAL4_bm (1<<4) /* Offset Calibration bit 4 mask. */ -#define DAC_CH0OFFSETCAL4_bp 4 /* Offset Calibration bit 4 position. */ -#define DAC_CH0OFFSETCAL5_bm (1<<5) /* Offset Calibration bit 5 mask. */ -#define DAC_CH0OFFSETCAL5_bp 5 /* Offset Calibration bit 5 position. */ -#define DAC_CH0OFFSETCAL6_bm (1<<6) /* Offset Calibration bit 6 mask. */ -#define DAC_CH0OFFSETCAL6_bp 6 /* Offset Calibration bit 6 position. */ - -/* DAC.CH1GAINCAL bit masks and bit positions */ -#define DAC_CH1GAINCAL_gm 0x7F /* Gain Calibration group mask. */ -#define DAC_CH1GAINCAL_gp 0 /* Gain Calibration group position. */ -#define DAC_CH1GAINCAL0_bm (1<<0) /* Gain Calibration bit 0 mask. */ -#define DAC_CH1GAINCAL0_bp 0 /* Gain Calibration bit 0 position. */ -#define DAC_CH1GAINCAL1_bm (1<<1) /* Gain Calibration bit 1 mask. */ -#define DAC_CH1GAINCAL1_bp 1 /* Gain Calibration bit 1 position. */ -#define DAC_CH1GAINCAL2_bm (1<<2) /* Gain Calibration bit 2 mask. */ -#define DAC_CH1GAINCAL2_bp 2 /* Gain Calibration bit 2 position. */ -#define DAC_CH1GAINCAL3_bm (1<<3) /* Gain Calibration bit 3 mask. */ -#define DAC_CH1GAINCAL3_bp 3 /* Gain Calibration bit 3 position. */ -#define DAC_CH1GAINCAL4_bm (1<<4) /* Gain Calibration bit 4 mask. */ -#define DAC_CH1GAINCAL4_bp 4 /* Gain Calibration bit 4 position. */ -#define DAC_CH1GAINCAL5_bm (1<<5) /* Gain Calibration bit 5 mask. */ -#define DAC_CH1GAINCAL5_bp 5 /* Gain Calibration bit 5 position. */ -#define DAC_CH1GAINCAL6_bm (1<<6) /* Gain Calibration bit 6 mask. */ -#define DAC_CH1GAINCAL6_bp 6 /* Gain Calibration bit 6 position. */ - -/* DAC.CH1OFFSETCAL bit masks and bit positions */ -#define DAC_CH1OFFSETCAL_gm 0x7F /* Offset Calibration group mask. */ -#define DAC_CH1OFFSETCAL_gp 0 /* Offset Calibration group position. */ -#define DAC_CH1OFFSETCAL0_bm (1<<0) /* Offset Calibration bit 0 mask. */ -#define DAC_CH1OFFSETCAL0_bp 0 /* Offset Calibration bit 0 position. */ -#define DAC_CH1OFFSETCAL1_bm (1<<1) /* Offset Calibration bit 1 mask. */ -#define DAC_CH1OFFSETCAL1_bp 1 /* Offset Calibration bit 1 position. */ -#define DAC_CH1OFFSETCAL2_bm (1<<2) /* Offset Calibration bit 2 mask. */ -#define DAC_CH1OFFSETCAL2_bp 2 /* Offset Calibration bit 2 position. */ -#define DAC_CH1OFFSETCAL3_bm (1<<3) /* Offset Calibration bit 3 mask. */ -#define DAC_CH1OFFSETCAL3_bp 3 /* Offset Calibration bit 3 position. */ -#define DAC_CH1OFFSETCAL4_bm (1<<4) /* Offset Calibration bit 4 mask. */ -#define DAC_CH1OFFSETCAL4_bp 4 /* Offset Calibration bit 4 position. */ -#define DAC_CH1OFFSETCAL5_bm (1<<5) /* Offset Calibration bit 5 mask. */ -#define DAC_CH1OFFSETCAL5_bp 5 /* Offset Calibration bit 5 position. */ -#define DAC_CH1OFFSETCAL6_bm (1<<6) /* Offset Calibration bit 6 mask. */ -#define DAC_CH1OFFSETCAL6_bp 6 /* Offset Calibration bit 6 position. */ - -/* AC - Analog Comparator */ -/* AC.AC0CTRL bit masks and bit positions */ -#define AC_INTMODE_gm 0xC0 /* Interrupt Mode group mask. */ -#define AC_INTMODE_gp 6 /* Interrupt Mode group position. */ -#define AC_INTMODE0_bm (1<<6) /* Interrupt Mode bit 0 mask. */ -#define AC_INTMODE0_bp 6 /* Interrupt Mode bit 0 position. */ -#define AC_INTMODE1_bm (1<<7) /* Interrupt Mode bit 1 mask. */ -#define AC_INTMODE1_bp 7 /* Interrupt Mode bit 1 position. */ - -#define AC_INTLVL_gm 0x30 /* Interrupt Level group mask. */ -#define AC_INTLVL_gp 4 /* Interrupt Level group position. */ -#define AC_INTLVL0_bm (1<<4) /* Interrupt Level bit 0 mask. */ -#define AC_INTLVL0_bp 4 /* Interrupt Level bit 0 position. */ -#define AC_INTLVL1_bm (1<<5) /* Interrupt Level bit 1 mask. */ -#define AC_INTLVL1_bp 5 /* Interrupt Level bit 1 position. */ - -#define AC_HYSMODE_gm 0x06 /* Hysteresis Mode group mask. */ -#define AC_HYSMODE_gp 1 /* Hysteresis Mode group position. */ -#define AC_HYSMODE0_bm (1<<1) /* Hysteresis Mode bit 0 mask. */ -#define AC_HYSMODE0_bp 1 /* Hysteresis Mode bit 0 position. */ -#define AC_HYSMODE1_bm (1<<2) /* Hysteresis Mode bit 1 mask. */ -#define AC_HYSMODE1_bp 2 /* Hysteresis Mode bit 1 position. */ - -#define AC_ENABLE_bm 0x01 /* Enable bit mask. */ -#define AC_ENABLE_bp 0 /* Enable bit position. */ - -/* AC.AC1CTRL bit masks and bit positions */ -/* AC_INTMODE Predefined. */ -/* AC_INTMODE Predefined. */ - -/* AC_INTLVL Predefined. */ -/* AC_INTLVL Predefined. */ - -/* AC_HYSMODE Predefined. */ -/* AC_HYSMODE Predefined. */ - -/* AC_ENABLE Predefined. */ -/* AC_ENABLE Predefined. */ - -/* AC.AC0MUXCTRL bit masks and bit positions */ -#define AC_MUXPOS_gm 0x38 /* MUX Positive Input group mask. */ -#define AC_MUXPOS_gp 3 /* MUX Positive Input group position. */ -#define AC_MUXPOS0_bm (1<<3) /* MUX Positive Input bit 0 mask. */ -#define AC_MUXPOS0_bp 3 /* MUX Positive Input bit 0 position. */ -#define AC_MUXPOS1_bm (1<<4) /* MUX Positive Input bit 1 mask. */ -#define AC_MUXPOS1_bp 4 /* MUX Positive Input bit 1 position. */ -#define AC_MUXPOS2_bm (1<<5) /* MUX Positive Input bit 2 mask. */ -#define AC_MUXPOS2_bp 5 /* MUX Positive Input bit 2 position. */ - -#define AC_MUXNEG_gm 0x07 /* MUX Negative Input group mask. */ -#define AC_MUXNEG_gp 0 /* MUX Negative Input group position. */ -#define AC_MUXNEG0_bm (1<<0) /* MUX Negative Input bit 0 mask. */ -#define AC_MUXNEG0_bp 0 /* MUX Negative Input bit 0 position. */ -#define AC_MUXNEG1_bm (1<<1) /* MUX Negative Input bit 1 mask. */ -#define AC_MUXNEG1_bp 1 /* MUX Negative Input bit 1 position. */ -#define AC_MUXNEG2_bm (1<<2) /* MUX Negative Input bit 2 mask. */ -#define AC_MUXNEG2_bp 2 /* MUX Negative Input bit 2 position. */ - -/* AC.AC1MUXCTRL bit masks and bit positions */ -/* AC_MUXPOS Predefined. */ -/* AC_MUXPOS Predefined. */ - -/* AC_MUXNEG Predefined. */ -/* AC_MUXNEG Predefined. */ - -/* AC.CTRLA bit masks and bit positions */ -#define AC_AC1INVEN_bm 0x08 /* Analog Comparator 1 Output Invert Enable bit mask. */ -#define AC_AC1INVEN_bp 3 /* Analog Comparator 1 Output Invert Enable bit position. */ - -#define AC_AC0INVEN_bm 0x04 /* Analog Comparator 0 Output Invert Enable bit mask. */ -#define AC_AC0INVEN_bp 2 /* Analog Comparator 0 Output Invert Enable bit position. */ - -#define AC_AC1OUT_bm 0x02 /* Analog Comparator 1 Output Enable bit mask. */ -#define AC_AC1OUT_bp 1 /* Analog Comparator 1 Output Enable bit position. */ - -#define AC_AC0OUT_bm 0x01 /* Analog Comparator 0 Output Enable bit mask. */ -#define AC_AC0OUT_bp 0 /* Analog Comparator 0 Output Enable bit position. */ - -/* AC.CTRLB bit masks and bit positions */ -#define AC_SCALEFAC_gm 0x3F /* VCC Voltage Scaler Factor group mask. */ -#define AC_SCALEFAC_gp 0 /* VCC Voltage Scaler Factor group position. */ -#define AC_SCALEFAC0_bm (1<<0) /* VCC Voltage Scaler Factor bit 0 mask. */ -#define AC_SCALEFAC0_bp 0 /* VCC Voltage Scaler Factor bit 0 position. */ -#define AC_SCALEFAC1_bm (1<<1) /* VCC Voltage Scaler Factor bit 1 mask. */ -#define AC_SCALEFAC1_bp 1 /* VCC Voltage Scaler Factor bit 1 position. */ -#define AC_SCALEFAC2_bm (1<<2) /* VCC Voltage Scaler Factor bit 2 mask. */ -#define AC_SCALEFAC2_bp 2 /* VCC Voltage Scaler Factor bit 2 position. */ -#define AC_SCALEFAC3_bm (1<<3) /* VCC Voltage Scaler Factor bit 3 mask. */ -#define AC_SCALEFAC3_bp 3 /* VCC Voltage Scaler Factor bit 3 position. */ -#define AC_SCALEFAC4_bm (1<<4) /* VCC Voltage Scaler Factor bit 4 mask. */ -#define AC_SCALEFAC4_bp 4 /* VCC Voltage Scaler Factor bit 4 position. */ -#define AC_SCALEFAC5_bm (1<<5) /* VCC Voltage Scaler Factor bit 5 mask. */ -#define AC_SCALEFAC5_bp 5 /* VCC Voltage Scaler Factor bit 5 position. */ - -/* AC.WINCTRL bit masks and bit positions */ -#define AC_WEN_bm 0x10 /* Window Mode Enable bit mask. */ -#define AC_WEN_bp 4 /* Window Mode Enable bit position. */ - -#define AC_WINTMODE_gm 0x0C /* Window Interrupt Mode group mask. */ -#define AC_WINTMODE_gp 2 /* Window Interrupt Mode group position. */ -#define AC_WINTMODE0_bm (1<<2) /* Window Interrupt Mode bit 0 mask. */ -#define AC_WINTMODE0_bp 2 /* Window Interrupt Mode bit 0 position. */ -#define AC_WINTMODE1_bm (1<<3) /* Window Interrupt Mode bit 1 mask. */ -#define AC_WINTMODE1_bp 3 /* Window Interrupt Mode bit 1 position. */ - -#define AC_WINTLVL_gm 0x03 /* Window Interrupt Level group mask. */ -#define AC_WINTLVL_gp 0 /* Window Interrupt Level group position. */ -#define AC_WINTLVL0_bm (1<<0) /* Window Interrupt Level bit 0 mask. */ -#define AC_WINTLVL0_bp 0 /* Window Interrupt Level bit 0 position. */ -#define AC_WINTLVL1_bm (1<<1) /* Window Interrupt Level bit 1 mask. */ -#define AC_WINTLVL1_bp 1 /* Window Interrupt Level bit 1 position. */ - -/* AC.STATUS bit masks and bit positions */ -#define AC_WSTATE_gm 0xC0 /* Window Mode State group mask. */ -#define AC_WSTATE_gp 6 /* Window Mode State group position. */ -#define AC_WSTATE0_bm (1<<6) /* Window Mode State bit 0 mask. */ -#define AC_WSTATE0_bp 6 /* Window Mode State bit 0 position. */ -#define AC_WSTATE1_bm (1<<7) /* Window Mode State bit 1 mask. */ -#define AC_WSTATE1_bp 7 /* Window Mode State bit 1 position. */ - -#define AC_AC1STATE_bm 0x20 /* Analog Comparator 1 State bit mask. */ -#define AC_AC1STATE_bp 5 /* Analog Comparator 1 State bit position. */ - -#define AC_AC0STATE_bm 0x10 /* Analog Comparator 0 State bit mask. */ -#define AC_AC0STATE_bp 4 /* Analog Comparator 0 State bit position. */ - -#define AC_WIF_bm 0x04 /* Window Mode Interrupt Flag bit mask. */ -#define AC_WIF_bp 2 /* Window Mode Interrupt Flag bit position. */ - -#define AC_AC1IF_bm 0x02 /* Analog Comparator 1 Interrupt Flag bit mask. */ -#define AC_AC1IF_bp 1 /* Analog Comparator 1 Interrupt Flag bit position. */ - -#define AC_AC0IF_bm 0x01 /* Analog Comparator 0 Interrupt Flag bit mask. */ -#define AC_AC0IF_bp 0 /* Analog Comparator 0 Interrupt Flag bit position. */ - -/* AC.CURRCTRL bit masks and bit positions */ -#define AC_CURREN_bm 0x80 /* Current Source Enable bit mask. */ -#define AC_CURREN_bp 7 /* Current Source Enable bit position. */ - -#define AC_CURRMODE_bm 0x40 /* Current Mode bit mask. */ -#define AC_CURRMODE_bp 6 /* Current Mode bit position. */ - -#define AC_AC1CURR_bm 0x02 /* Analog Comparator 1 current source output bit mask. */ -#define AC_AC1CURR_bp 1 /* Analog Comparator 1 current source output bit position. */ - -#define AC_AC0CURR_bm 0x01 /* Analog Comparator 0 current source output bit mask. */ -#define AC_AC0CURR_bp 0 /* Analog Comparator 0 current source output bit position. */ - -/* AC.CURRCALIB bit masks and bit positions */ -#define AC_CALIB_gm 0x0F /* Current Source Calibration group mask. */ -#define AC_CALIB_gp 0 /* Current Source Calibration group position. */ -#define AC_CALIB0_bm (1<<0) /* Current Source Calibration bit 0 mask. */ -#define AC_CALIB0_bp 0 /* Current Source Calibration bit 0 position. */ -#define AC_CALIB1_bm (1<<1) /* Current Source Calibration bit 1 mask. */ -#define AC_CALIB1_bp 1 /* Current Source Calibration bit 1 position. */ -#define AC_CALIB2_bm (1<<2) /* Current Source Calibration bit 2 mask. */ -#define AC_CALIB2_bp 2 /* Current Source Calibration bit 2 position. */ -#define AC_CALIB3_bm (1<<3) /* Current Source Calibration bit 3 mask. */ -#define AC_CALIB3_bp 3 /* Current Source Calibration bit 3 position. */ - -/* RTC - Real-Time Clounter */ -/* RTC.CTRL bit masks and bit positions */ -#define RTC_CORREN_bm 0x08 /* Correction Enable bit mask. */ -#define RTC_CORREN_bp 3 /* Correction Enable bit position. */ - -#define RTC_PRESCALER_gm 0x07 /* Prescaling Factor group mask. */ -#define RTC_PRESCALER_gp 0 /* Prescaling Factor group position. */ -#define RTC_PRESCALER0_bm (1<<0) /* Prescaling Factor bit 0 mask. */ -#define RTC_PRESCALER0_bp 0 /* Prescaling Factor bit 0 position. */ -#define RTC_PRESCALER1_bm (1<<1) /* Prescaling Factor bit 1 mask. */ -#define RTC_PRESCALER1_bp 1 /* Prescaling Factor bit 1 position. */ -#define RTC_PRESCALER2_bm (1<<2) /* Prescaling Factor bit 2 mask. */ -#define RTC_PRESCALER2_bp 2 /* Prescaling Factor bit 2 position. */ - -/* RTC.STATUS bit masks and bit positions */ -#define RTC_SYNCBUSY_bm 0x01 /* Synchronization Busy Flag bit mask. */ -#define RTC_SYNCBUSY_bp 0 /* Synchronization Busy Flag bit position. */ - -/* RTC.INTCTRL bit masks and bit positions */ -#define RTC_COMPINTLVL_gm 0x0C /* Compare Match Interrupt Level group mask. */ -#define RTC_COMPINTLVL_gp 2 /* Compare Match Interrupt Level group position. */ -#define RTC_COMPINTLVL0_bm (1<<2) /* Compare Match Interrupt Level bit 0 mask. */ -#define RTC_COMPINTLVL0_bp 2 /* Compare Match Interrupt Level bit 0 position. */ -#define RTC_COMPINTLVL1_bm (1<<3) /* Compare Match Interrupt Level bit 1 mask. */ -#define RTC_COMPINTLVL1_bp 3 /* Compare Match Interrupt Level bit 1 position. */ - -#define RTC_OVFINTLVL_gm 0x03 /* Overflow Interrupt Level group mask. */ -#define RTC_OVFINTLVL_gp 0 /* Overflow Interrupt Level group position. */ -#define RTC_OVFINTLVL0_bm (1<<0) /* Overflow Interrupt Level bit 0 mask. */ -#define RTC_OVFINTLVL0_bp 0 /* Overflow Interrupt Level bit 0 position. */ -#define RTC_OVFINTLVL1_bm (1<<1) /* Overflow Interrupt Level bit 1 mask. */ -#define RTC_OVFINTLVL1_bp 1 /* Overflow Interrupt Level bit 1 position. */ - -/* RTC.INTFLAGS bit masks and bit positions */ -#define RTC_COMPIF_bm 0x02 /* Compare Match Interrupt Flag bit mask. */ -#define RTC_COMPIF_bp 1 /* Compare Match Interrupt Flag bit position. */ - -#define RTC_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ -#define RTC_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ - -/* RTC.CALIB bit masks and bit positions */ -#define RTC_SIGN_bm 0x80 /* Correction Sign bit mask. */ -#define RTC_SIGN_bp 7 /* Correction Sign bit position. */ - -#define RTC_ERROR_gm 0x7F /* Error Value group mask. */ -#define RTC_ERROR_gp 0 /* Error Value group position. */ -#define RTC_ERROR0_bm (1<<0) /* Error Value bit 0 mask. */ -#define RTC_ERROR0_bp 0 /* Error Value bit 0 position. */ -#define RTC_ERROR1_bm (1<<1) /* Error Value bit 1 mask. */ -#define RTC_ERROR1_bp 1 /* Error Value bit 1 position. */ -#define RTC_ERROR2_bm (1<<2) /* Error Value bit 2 mask. */ -#define RTC_ERROR2_bp 2 /* Error Value bit 2 position. */ -#define RTC_ERROR3_bm (1<<3) /* Error Value bit 3 mask. */ -#define RTC_ERROR3_bp 3 /* Error Value bit 3 position. */ -#define RTC_ERROR4_bm (1<<4) /* Error Value bit 4 mask. */ -#define RTC_ERROR4_bp 4 /* Error Value bit 4 position. */ -#define RTC_ERROR5_bm (1<<5) /* Error Value bit 5 mask. */ -#define RTC_ERROR5_bp 5 /* Error Value bit 5 position. */ -#define RTC_ERROR6_bm (1<<6) /* Error Value bit 6 mask. */ -#define RTC_ERROR6_bp 6 /* Error Value bit 6 position. */ - -/* XCL - XMEGA Custom Logic */ -/* XCL.CTRLA bit masks and bit positions */ -#define XCL_LUT0OUTEN_gm 0xC0 /* LUT0 Output Enable group mask. */ -#define XCL_LUT0OUTEN_gp 6 /* LUT0 Output Enable group position. */ -#define XCL_LUT0OUTEN0_bm (1<<6) /* LUT0 Output Enable bit 0 mask. */ -#define XCL_LUT0OUTEN0_bp 6 /* LUT0 Output Enable bit 0 position. */ -#define XCL_LUT0OUTEN1_bm (1<<7) /* LUT0 Output Enable bit 1 mask. */ -#define XCL_LUT0OUTEN1_bp 7 /* LUT0 Output Enable bit 1 position. */ - -#define XCL_PORTSEL_gm 0x30 /* Port Selection group mask. */ -#define XCL_PORTSEL_gp 4 /* Port Selection group position. */ -#define XCL_PORTSEL0_bm (1<<4) /* Port Selection bit 0 mask. */ -#define XCL_PORTSEL0_bp 4 /* Port Selection bit 0 position. */ -#define XCL_PORTSEL1_bm (1<<5) /* Port Selection bit 1 mask. */ -#define XCL_PORTSEL1_bp 5 /* Port Selection bit 1 position. */ - -#define XCL_LUTCONF_gm 0x07 /* LUT Configuration group mask. */ -#define XCL_LUTCONF_gp 0 /* LUT Configuration group position. */ -#define XCL_LUTCONF0_bm (1<<0) /* LUT Configuration bit 0 mask. */ -#define XCL_LUTCONF0_bp 0 /* LUT Configuration bit 0 position. */ -#define XCL_LUTCONF1_bm (1<<1) /* LUT Configuration bit 1 mask. */ -#define XCL_LUTCONF1_bp 1 /* LUT Configuration bit 1 position. */ -#define XCL_LUTCONF2_bm (1<<2) /* LUT Configuration bit 2 mask. */ -#define XCL_LUTCONF2_bp 2 /* LUT Configuration bit 2 position. */ - -/* XCL.CTRLB bit masks and bit positions */ -#define XCL_IN3SEL_gm 0xC0 /* Input Selection 3 group mask. */ -#define XCL_IN3SEL_gp 6 /* Input Selection 3 group position. */ -#define XCL_IN3SEL0_bm (1<<6) /* Input Selection 3 bit 0 mask. */ -#define XCL_IN3SEL0_bp 6 /* Input Selection 3 bit 0 position. */ -#define XCL_IN3SEL1_bm (1<<7) /* Input Selection 3 bit 1 mask. */ -#define XCL_IN3SEL1_bp 7 /* Input Selection 3 bit 1 position. */ - -#define XCL_IN2SEL_gm 0x30 /* Input Selection 2 group mask. */ -#define XCL_IN2SEL_gp 4 /* Input Selection 2 group position. */ -#define XCL_IN2SEL0_bm (1<<4) /* Input Selection 2 bit 0 mask. */ -#define XCL_IN2SEL0_bp 4 /* Input Selection 2 bit 0 position. */ -#define XCL_IN2SEL1_bm (1<<5) /* Input Selection 2 bit 1 mask. */ -#define XCL_IN2SEL1_bp 5 /* Input Selection 2 bit 1 position. */ - -#define XCL_IN1SEL_gm 0x0C /* Input Selection 1 group mask. */ -#define XCL_IN1SEL_gp 2 /* Input Selection 1 group position. */ -#define XCL_IN1SEL0_bm (1<<2) /* Input Selection 1 bit 0 mask. */ -#define XCL_IN1SEL0_bp 2 /* Input Selection 1 bit 0 position. */ -#define XCL_IN1SEL1_bm (1<<3) /* Input Selection 1 bit 1 mask. */ -#define XCL_IN1SEL1_bp 3 /* Input Selection 1 bit 1 position. */ - -#define XCL_IN0SEL_gm 0x03 /* Input Selection 0 group mask. */ -#define XCL_IN0SEL_gp 0 /* Input Selection 0 group position. */ -#define XCL_IN0SEL0_bm (1<<0) /* Input Selection 0 bit 0 mask. */ -#define XCL_IN0SEL0_bp 0 /* Input Selection 0 bit 0 position. */ -#define XCL_IN0SEL1_bm (1<<1) /* Input Selection 0 bit 1 mask. */ -#define XCL_IN0SEL1_bp 1 /* Input Selection 0 bit 1 position. */ - -/* XCL.CTRLC bit masks and bit positions */ -#define XCL_EVASYSEL1_bm 0x80 /* Asynchronous Event Line Selection for LUT1 bit mask. */ -#define XCL_EVASYSEL1_bp 7 /* Asynchronous Event Line Selection for LUT1 bit position. */ - -#define XCL_EVASYSEL0_bm 0x40 /* Asynchronous Event Line Selection for LUT0 bit mask. */ -#define XCL_EVASYSEL0_bp 6 /* Asynchronous Event Line Selection for LUT0 bit position. */ - -#define XCL_DLYSEL_gm 0x30 /* Delay Selection group mask. */ -#define XCL_DLYSEL_gp 4 /* Delay Selection group position. */ -#define XCL_DLYSEL0_bm (1<<4) /* Delay Selection bit 0 mask. */ -#define XCL_DLYSEL0_bp 4 /* Delay Selection bit 0 position. */ -#define XCL_DLYSEL1_bm (1<<5) /* Delay Selection bit 1 mask. */ -#define XCL_DLYSEL1_bp 5 /* Delay Selection bit 1 position. */ - -#define XCL_DLY1CONF_gm 0x0C /* Delay Configuration on LUT1 group mask. */ -#define XCL_DLY1CONF_gp 2 /* Delay Configuration on LUT1 group position. */ -#define XCL_DLY1CONF0_bm (1<<2) /* Delay Configuration on LUT1 bit 0 mask. */ -#define XCL_DLY1CONF0_bp 2 /* Delay Configuration on LUT1 bit 0 position. */ -#define XCL_DLY1CONF1_bm (1<<3) /* Delay Configuration on LUT1 bit 1 mask. */ -#define XCL_DLY1CONF1_bp 3 /* Delay Configuration on LUT1 bit 1 position. */ - -#define XCL_DLY0CONF_gm 0x03 /* Delay Configuration on LUT0 group mask. */ -#define XCL_DLY0CONF_gp 0 /* Delay Configuration on LUT0 group position. */ -#define XCL_DLY0CONF0_bm (1<<0) /* Delay Configuration on LUT0 bit 0 mask. */ -#define XCL_DLY0CONF0_bp 0 /* Delay Configuration on LUT0 bit 0 position. */ -#define XCL_DLY0CONF1_bm (1<<1) /* Delay Configuration on LUT0 bit 1 mask. */ -#define XCL_DLY0CONF1_bp 1 /* Delay Configuration on LUT0 bit 1 position. */ - -/* XCL.CTRLD bit masks and bit positions */ -#define XCL_TRUTH1_gm 0xF0 /* Truth Table of LUT1 group mask. */ -#define XCL_TRUTH1_gp 4 /* Truth Table of LUT1 group position. */ -#define XCL_TRUTH10_bm (1<<4) /* Truth Table of LUT1 bit 0 mask. */ -#define XCL_TRUTH10_bp 4 /* Truth Table of LUT1 bit 0 position. */ -#define XCL_TRUTH11_bm (1<<5) /* Truth Table of LUT1 bit 1 mask. */ -#define XCL_TRUTH11_bp 5 /* Truth Table of LUT1 bit 1 position. */ -#define XCL_TRUTH12_bm (1<<6) /* Truth Table of LUT1 bit 2 mask. */ -#define XCL_TRUTH12_bp 6 /* Truth Table of LUT1 bit 2 position. */ -#define XCL_TRUTH13_bm (1<<7) /* Truth Table of LUT1 bit 3 mask. */ -#define XCL_TRUTH13_bp 7 /* Truth Table of LUT1 bit 3 position. */ - -#define XCL_TRUTH0_gm 0x0F /* Truth Table of LUT0 group mask. */ -#define XCL_TRUTH0_gp 0 /* Truth Table of LUT0 group position. */ -#define XCL_TRUTH00_bm (1<<0) /* Truth Table of LUT0 bit 0 mask. */ -#define XCL_TRUTH00_bp 0 /* Truth Table of LUT0 bit 0 position. */ -#define XCL_TRUTH01_bm (1<<1) /* Truth Table of LUT0 bit 1 mask. */ -#define XCL_TRUTH01_bp 1 /* Truth Table of LUT0 bit 1 position. */ -#define XCL_TRUTH02_bm (1<<2) /* Truth Table of LUT0 bit 2 mask. */ -#define XCL_TRUTH02_bp 2 /* Truth Table of LUT0 bit 2 position. */ -#define XCL_TRUTH03_bm (1<<3) /* Truth Table of LUT0 bit 3 mask. */ -#define XCL_TRUTH03_bp 3 /* Truth Table of LUT0 bit 3 position. */ - -/* XCL.CTRLE bit masks and bit positions */ -#define XCL_CMDSEL_bm 0x80 /* Timer/Counter Command Selection bit mask. */ -#define XCL_CMDSEL_bp 7 /* Timer/Counter Command Selection bit position. */ - -#define XCL_TCSEL_gm 0x70 /* Timer/Counter Selection group mask. */ -#define XCL_TCSEL_gp 4 /* Timer/Counter Selection group position. */ -#define XCL_TCSEL0_bm (1<<4) /* Timer/Counter Selection bit 0 mask. */ -#define XCL_TCSEL0_bp 4 /* Timer/Counter Selection bit 0 position. */ -#define XCL_TCSEL1_bm (1<<5) /* Timer/Counter Selection bit 1 mask. */ -#define XCL_TCSEL1_bp 5 /* Timer/Counter Selection bit 1 position. */ -#define XCL_TCSEL2_bm (1<<6) /* Timer/Counter Selection bit 2 mask. */ -#define XCL_TCSEL2_bp 6 /* Timer/Counter Selection bit 2 position. */ - -#define XCL_CLKSEL_gm 0x0F /* Clock Selection group mask. */ -#define XCL_CLKSEL_gp 0 /* Clock Selection group position. */ -#define XCL_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ -#define XCL_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ -#define XCL_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ -#define XCL_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ -#define XCL_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ -#define XCL_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ -#define XCL_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ -#define XCL_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ - -/* XCL.CTRLF bit masks and bit positions */ -#define XCL_CMDEN_gm 0xC0 /* Command Enable group mask. */ -#define XCL_CMDEN_gp 6 /* Command Enable group position. */ -#define XCL_CMDEN0_bm (1<<6) /* Command Enable bit 0 mask. */ -#define XCL_CMDEN0_bp 6 /* Command Enable bit 0 position. */ -#define XCL_CMDEN1_bm (1<<7) /* Command Enable bit 1 mask. */ -#define XCL_CMDEN1_bp 7 /* Command Enable bit 1 position. */ - -#define XCL_CMP1_bm 0x20 /* Compare Channel 1 Output Value bit mask. */ -#define XCL_CMP1_bp 5 /* Compare Channel 1 Output Value bit position. */ - -#define XCL_CMP0_bm 0x10 /* Compare Channel 0 Output Value bit mask. */ -#define XCL_CMP0_bp 4 /* Compare Channel 0 Output Value bit position. */ - -#define XCL_CCEN1_bm 0x08 /* Compare or Capture Channel 1 Enable bit mask. */ -#define XCL_CCEN1_bp 3 /* Compare or Capture Channel 1 Enable bit position. */ - -#define XCL_CCEN0_bm 0x04 /* Compare or Capture Channel 0 Enable bit mask. */ -#define XCL_CCEN0_bp 2 /* Compare or Capture Channel 0 Enable bit position. */ - -#define XCL_MODE_gm 0x03 /* Timer/Counter Mode group mask. */ -#define XCL_MODE_gp 0 /* Timer/Counter Mode group position. */ -#define XCL_MODE0_bm (1<<0) /* Timer/Counter Mode bit 0 mask. */ -#define XCL_MODE0_bp 0 /* Timer/Counter Mode bit 0 position. */ -#define XCL_MODE1_bm (1<<1) /* Timer/Counter Mode bit 1 mask. */ -#define XCL_MODE1_bp 1 /* Timer/Counter Mode bit 1 position. */ - -/* XCL.CTRLG bit masks and bit positions */ -#define XCL_EVACTEN_bm 0x80 /* Event Action Enable bit mask. */ -#define XCL_EVACTEN_bp 7 /* Event Action Enable bit position. */ - -#define XCL_EVACT1_gm 0x60 /* Event Action Selection on Timer/Counter 1 group mask. */ -#define XCL_EVACT1_gp 5 /* Event Action Selection on Timer/Counter 1 group position. */ -#define XCL_EVACT10_bm (1<<5) /* Event Action Selection on Timer/Counter 1 bit 0 mask. */ -#define XCL_EVACT10_bp 5 /* Event Action Selection on Timer/Counter 1 bit 0 position. */ -#define XCL_EVACT11_bm (1<<6) /* Event Action Selection on Timer/Counter 1 bit 1 mask. */ -#define XCL_EVACT11_bp 6 /* Event Action Selection on Timer/Counter 1 bit 1 position. */ - -#define XCL_EVACT0_gm 0x18 /* Event Action Selection on Timer/Counter 0 group mask. */ -#define XCL_EVACT0_gp 3 /* Event Action Selection on Timer/Counter 0 group position. */ -#define XCL_EVACT00_bm (1<<3) /* Event Action Selection on Timer/Counter 0 bit 0 mask. */ -#define XCL_EVACT00_bp 3 /* Event Action Selection on Timer/Counter 0 bit 0 position. */ -#define XCL_EVACT01_bm (1<<4) /* Event Action Selection on Timer/Counter 0 bit 1 mask. */ -#define XCL_EVACT01_bp 4 /* Event Action Selection on Timer/Counter 0 bit 1 position. */ - -#define XCL_EVSRC_gm 0x07 /* Event Source Selection group mask. */ -#define XCL_EVSRC_gp 0 /* Event Source Selection group position. */ -#define XCL_EVSRC0_bm (1<<0) /* Event Source Selection bit 0 mask. */ -#define XCL_EVSRC0_bp 0 /* Event Source Selection bit 0 position. */ -#define XCL_EVSRC1_bm (1<<1) /* Event Source Selection bit 1 mask. */ -#define XCL_EVSRC1_bp 1 /* Event Source Selection bit 1 position. */ -#define XCL_EVSRC2_bm (1<<2) /* Event Source Selection bit 2 mask. */ -#define XCL_EVSRC2_bp 2 /* Event Source Selection bit 2 position. */ - -/* XCL.INTCTRL bit masks and bit positions */ -#define XCL_UNF1IE_bm 0x80 /* Underflow 1 Interrupt Enable bit mask. */ -#define XCL_UNF1IE_bp 7 /* Underflow 1 Interrupt Enable bit position. */ - -#define XCL_PEC1IE_bm 0x80 /* Peripheral Counter 1 Interrupt Enable bit mask. */ -#define XCL_PEC1IE_bp 7 /* Peripheral Counter 1 Interrupt Enable bit position. */ - -#define XCL_PEC21IE_bm 0x80 /* Peripheral High Counter 2 Interrupt Enable bit mask. */ -#define XCL_PEC21IE_bp 7 /* Peripheral High Counter 2 Interrupt Enable bit position. */ - -#define XCL_UNF0IE_bm 0x40 /* Underflow 0 Interrupt Enable bit mask. */ -#define XCL_UNF0IE_bp 6 /* Underflow 0 Interrupt Enable bit position. */ - -#define XCL_PEC0IE_bm 0x40 /* Peripheral Counter 0 Interrupt Enable bit mask. */ -#define XCL_PEC0IE_bp 6 /* Peripheral Counter 0 Interrupt Enable bit position. */ - -#define XCL_CC1IE_bm 0x20 /* Compare Or Capture 1 Interrupt Enable bit mask. */ -#define XCL_CC1IE_bp 5 /* Compare Or Capture 1 Interrupt Enable bit position. */ - -#define XCL_PEC20IE_bm 0x20 /* Peripheral Low Counter 2 Interrupt Enable bit mask. */ -#define XCL_PEC20IE_bp 5 /* Peripheral Low Counter 2 Interrupt Enable bit position. */ - -#define XCL_CC0IE_bm 0x10 /* Compare Or Capture 0 Interrupt Enable bit mask. */ -#define XCL_CC0IE_bp 4 /* Compare Or Capture 0 Interrupt Enable bit position. */ - -#define XCL_UNFINTLVL_gm 0x0C /* Timer Underflow Interrupt Level group mask. */ -#define XCL_UNFINTLVL_gp 2 /* Timer Underflow Interrupt Level group position. */ -#define XCL_UNFINTLVL0_bm (1<<2) /* Timer Underflow Interrupt Level bit 0 mask. */ -#define XCL_UNFINTLVL0_bp 2 /* Timer Underflow Interrupt Level bit 0 position. */ -#define XCL_UNFINTLVL1_bm (1<<3) /* Timer Underflow Interrupt Level bit 1 mask. */ -#define XCL_UNFINTLVL1_bp 3 /* Timer Underflow Interrupt Level bit 1 position. */ - -#define XCL_CCINTLVL_gm 0x03 /* Timer Compare or Capture Interrupt Level group mask. */ -#define XCL_CCINTLVL_gp 0 /* Timer Compare or Capture Interrupt Level group position. */ -#define XCL_CCINTLVL0_bm (1<<0) /* Timer Compare or Capture Interrupt Level bit 0 mask. */ -#define XCL_CCINTLVL0_bp 0 /* Timer Compare or Capture Interrupt Level bit 0 position. */ -#define XCL_CCINTLVL1_bm (1<<1) /* Timer Compare or Capture Interrupt Level bit 1 mask. */ -#define XCL_CCINTLVL1_bp 1 /* Timer Compare or Capture Interrupt Level bit 1 position. */ - -/* XCL.INTFLAGS bit masks and bit positions */ -#define XCL_UNF1IF_bm 0x80 /* Timer/Counter 1 Underflow Interrupt Flag bit mask. */ -#define XCL_UNF1IF_bp 7 /* Timer/Counter 1 Underflow Interrupt Flag bit position. */ - -#define XCL_PEC1IF_bm 0x80 /* Peripheral Counter 1 Interrupt Flag bit mask. */ -#define XCL_PEC1IF_bp 7 /* Peripheral Counter 1 Interrupt Flag bit position. */ - -#define XCL_PEC21IF_bm 0x80 /* Peripheral High Counter 2 Interrupt Flag bit mask. */ -#define XCL_PEC21IF_bp 7 /* Peripheral High Counter 2 Interrupt Flag bit position. */ - -#define XCL_UNF0IF_bm 0x40 /* Timer/Counter 0 Underflow Interrupt Flag bit mask. */ -#define XCL_UNF0IF_bp 6 /* Timer/Counter 0 Underflow Interrupt Flag bit position. */ - -#define XCL_PEC0IF_bm 0x40 /* Peripheral Counter 0 Interrupt Flag bit mask. */ -#define XCL_PEC0IF_bp 6 /* Peripheral Counter 0 Interrupt Flag bit position. */ - -#define XCL_CC1IF_bm 0x20 /* Compare or Capture Channel 1 Interrupt Flag bit mask. */ -#define XCL_CC1IF_bp 5 /* Compare or Capture Channel 1 Interrupt Flag bit position. */ - -#define XCL_PEC20IF_bm 0x20 /* Peripheral Low Counter 2 Interrupt Flag bit mask. */ -#define XCL_PEC20IF_bp 5 /* Peripheral Low Counter 2 Interrupt Flag bit position. */ - -#define XCL_CC0IF_bm 0x10 /* Compare or Capture Channel 0 Interrupt Flag bit mask. */ -#define XCL_CC0IF_bp 4 /* Compare or Capture Channel 0 Interrupt Flag bit position. */ - -/* XCL.PLC bit masks and bit positions */ -#define XCL_PLC_gm 0xFF /* Peripheral Lenght Control Bits group mask. */ -#define XCL_PLC_gp 0 /* Peripheral Lenght Control Bits group position. */ -#define XCL_PLC0_bm (1<<0) /* Peripheral Lenght Control Bits bit 0 mask. */ -#define XCL_PLC0_bp 0 /* Peripheral Lenght Control Bits bit 0 position. */ -#define XCL_PLC1_bm (1<<1) /* Peripheral Lenght Control Bits bit 1 mask. */ -#define XCL_PLC1_bp 1 /* Peripheral Lenght Control Bits bit 1 position. */ -#define XCL_PLC2_bm (1<<2) /* Peripheral Lenght Control Bits bit 2 mask. */ -#define XCL_PLC2_bp 2 /* Peripheral Lenght Control Bits bit 2 position. */ -#define XCL_PLC3_bm (1<<3) /* Peripheral Lenght Control Bits bit 3 mask. */ -#define XCL_PLC3_bp 3 /* Peripheral Lenght Control Bits bit 3 position. */ -#define XCL_PLC4_bm (1<<4) /* Peripheral Lenght Control Bits bit 4 mask. */ -#define XCL_PLC4_bp 4 /* Peripheral Lenght Control Bits bit 4 position. */ -#define XCL_PLC5_bm (1<<5) /* Peripheral Lenght Control Bits bit 5 mask. */ -#define XCL_PLC5_bp 5 /* Peripheral Lenght Control Bits bit 5 position. */ -#define XCL_PLC6_bm (1<<6) /* Peripheral Lenght Control Bits bit 6 mask. */ -#define XCL_PLC6_bp 6 /* Peripheral Lenght Control Bits bit 6 position. */ -#define XCL_PLC7_bm (1<<7) /* Peripheral Lenght Control Bits bit 7 mask. */ -#define XCL_PLC7_bp 7 /* Peripheral Lenght Control Bits bit 7 position. */ - -/* XCL.CNTL bit masks and bit positions */ -#define XCL_BCNTO_gm 0xFF /* BTC0 Counter Byte group mask. */ -#define XCL_BCNTO_gp 0 /* BTC0 Counter Byte group position. */ -#define XCL_BCNTO0_bm (1<<0) /* BTC0 Counter Byte bit 0 mask. */ -#define XCL_BCNTO0_bp 0 /* BTC0 Counter Byte bit 0 position. */ -#define XCL_BCNTO1_bm (1<<1) /* BTC0 Counter Byte bit 1 mask. */ -#define XCL_BCNTO1_bp 1 /* BTC0 Counter Byte bit 1 position. */ -#define XCL_BCNTO2_bm (1<<2) /* BTC0 Counter Byte bit 2 mask. */ -#define XCL_BCNTO2_bp 2 /* BTC0 Counter Byte bit 2 position. */ -#define XCL_BCNTO3_bm (1<<3) /* BTC0 Counter Byte bit 3 mask. */ -#define XCL_BCNTO3_bp 3 /* BTC0 Counter Byte bit 3 position. */ -#define XCL_BCNTO4_bm (1<<4) /* BTC0 Counter Byte bit 4 mask. */ -#define XCL_BCNTO4_bp 4 /* BTC0 Counter Byte bit 4 position. */ -#define XCL_BCNTO5_bm (1<<5) /* BTC0 Counter Byte bit 5 mask. */ -#define XCL_BCNTO5_bp 5 /* BTC0 Counter Byte bit 5 position. */ -#define XCL_BCNTO6_bm (1<<6) /* BTC0 Counter Byte bit 6 mask. */ -#define XCL_BCNTO6_bp 6 /* BTC0 Counter Byte bit 6 position. */ -#define XCL_BCNTO7_bm (1<<7) /* BTC0 Counter Byte bit 7 mask. */ -#define XCL_BCNTO7_bp 7 /* BTC0 Counter Byte bit 7 position. */ - -#define XCL_CNTL_gm 0xFF /* TC16 Counter Low Byte group mask. */ -#define XCL_CNTL_gp 0 /* TC16 Counter Low Byte group position. */ -#define XCL_CNTL0_bm (1<<0) /* TC16 Counter Low Byte bit 0 mask. */ -#define XCL_CNTL0_bp 0 /* TC16 Counter Low Byte bit 0 position. */ -#define XCL_CNTL1_bm (1<<1) /* TC16 Counter Low Byte bit 1 mask. */ -#define XCL_CNTL1_bp 1 /* TC16 Counter Low Byte bit 1 position. */ -#define XCL_CNTL2_bm (1<<2) /* TC16 Counter Low Byte bit 2 mask. */ -#define XCL_CNTL2_bp 2 /* TC16 Counter Low Byte bit 2 position. */ -#define XCL_CNTL3_bm (1<<3) /* TC16 Counter Low Byte bit 3 mask. */ -#define XCL_CNTL3_bp 3 /* TC16 Counter Low Byte bit 3 position. */ -#define XCL_CNTL4_bm (1<<4) /* TC16 Counter Low Byte bit 4 mask. */ -#define XCL_CNTL4_bp 4 /* TC16 Counter Low Byte bit 4 position. */ -#define XCL_CNTL5_bm (1<<5) /* TC16 Counter Low Byte bit 5 mask. */ -#define XCL_CNTL5_bp 5 /* TC16 Counter Low Byte bit 5 position. */ -#define XCL_CNTL6_bm (1<<6) /* TC16 Counter Low Byte bit 6 mask. */ -#define XCL_CNTL6_bp 6 /* TC16 Counter Low Byte bit 6 position. */ -#define XCL_CNTL7_bm (1<<7) /* TC16 Counter Low Byte bit 7 mask. */ -#define XCL_CNTL7_bp 7 /* TC16 Counter Low Byte bit 7 position. */ - -#define XCL_PCNTO_gm 0xFF /* Peripheral Counter 0 Byte group mask. */ -#define XCL_PCNTO_gp 0 /* Peripheral Counter 0 Byte group position. */ -#define XCL_PCNTO0_bm (1<<0) /* Peripheral Counter 0 Byte bit 0 mask. */ -#define XCL_PCNTO0_bp 0 /* Peripheral Counter 0 Byte bit 0 position. */ -#define XCL_PCNTO1_bm (1<<1) /* Peripheral Counter 0 Byte bit 1 mask. */ -#define XCL_PCNTO1_bp 1 /* Peripheral Counter 0 Byte bit 1 position. */ -#define XCL_PCNTO2_bm (1<<2) /* Peripheral Counter 0 Byte bit 2 mask. */ -#define XCL_PCNTO2_bp 2 /* Peripheral Counter 0 Byte bit 2 position. */ -#define XCL_PCNTO3_bm (1<<3) /* Peripheral Counter 0 Byte bit 3 mask. */ -#define XCL_PCNTO3_bp 3 /* Peripheral Counter 0 Byte bit 3 position. */ -#define XCL_PCNTO4_bm (1<<4) /* Peripheral Counter 0 Byte bit 4 mask. */ -#define XCL_PCNTO4_bp 4 /* Peripheral Counter 0 Byte bit 4 position. */ -#define XCL_PCNTO5_bm (1<<5) /* Peripheral Counter 0 Byte bit 5 mask. */ -#define XCL_PCNTO5_bp 5 /* Peripheral Counter 0 Byte bit 5 position. */ -#define XCL_PCNTO6_bm (1<<6) /* Peripheral Counter 0 Byte bit 6 mask. */ -#define XCL_PCNTO6_bp 6 /* Peripheral Counter 0 Byte bit 6 position. */ -#define XCL_PCNTO7_bm (1<<7) /* Peripheral Counter 0 Byte bit 7 mask. */ -#define XCL_PCNTO7_bp 7 /* Peripheral Counter 0 Byte bit 7 position. */ - -/* XCL.CNTH bit masks and bit positions */ -#define XCL_BCNT1_gm 0xFF /* BTC1 Counter Byte group mask. */ -#define XCL_BCNT1_gp 0 /* BTC1 Counter Byte group position. */ -#define XCL_BCNT10_bm (1<<0) /* BTC1 Counter Byte bit 0 mask. */ -#define XCL_BCNT10_bp 0 /* BTC1 Counter Byte bit 0 position. */ -#define XCL_BCNT11_bm (1<<1) /* BTC1 Counter Byte bit 1 mask. */ -#define XCL_BCNT11_bp 1 /* BTC1 Counter Byte bit 1 position. */ -#define XCL_BCNT12_bm (1<<2) /* BTC1 Counter Byte bit 2 mask. */ -#define XCL_BCNT12_bp 2 /* BTC1 Counter Byte bit 2 position. */ -#define XCL_BCNT13_bm (1<<3) /* BTC1 Counter Byte bit 3 mask. */ -#define XCL_BCNT13_bp 3 /* BTC1 Counter Byte bit 3 position. */ -#define XCL_BCNT14_bm (1<<4) /* BTC1 Counter Byte bit 4 mask. */ -#define XCL_BCNT14_bp 4 /* BTC1 Counter Byte bit 4 position. */ -#define XCL_BCNT15_bm (1<<5) /* BTC1 Counter Byte bit 5 mask. */ -#define XCL_BCNT15_bp 5 /* BTC1 Counter Byte bit 5 position. */ -#define XCL_BCNT16_bm (1<<6) /* BTC1 Counter Byte bit 6 mask. */ -#define XCL_BCNT16_bp 6 /* BTC1 Counter Byte bit 6 position. */ -#define XCL_BCNT17_bm (1<<7) /* BTC1 Counter Byte bit 7 mask. */ -#define XCL_BCNT17_bp 7 /* BTC1 Counter Byte bit 7 position. */ - -#define XCL_CNTH_gm 0xFF /* TC16 Counter High Byte group mask. */ -#define XCL_CNTH_gp 0 /* TC16 Counter High Byte group position. */ -#define XCL_CNTH0_bm (1<<0) /* TC16 Counter High Byte bit 0 mask. */ -#define XCL_CNTH0_bp 0 /* TC16 Counter High Byte bit 0 position. */ -#define XCL_CNTH1_bm (1<<1) /* TC16 Counter High Byte bit 1 mask. */ -#define XCL_CNTH1_bp 1 /* TC16 Counter High Byte bit 1 position. */ -#define XCL_CNTH2_bm (1<<2) /* TC16 Counter High Byte bit 2 mask. */ -#define XCL_CNTH2_bp 2 /* TC16 Counter High Byte bit 2 position. */ -#define XCL_CNTH3_bm (1<<3) /* TC16 Counter High Byte bit 3 mask. */ -#define XCL_CNTH3_bp 3 /* TC16 Counter High Byte bit 3 position. */ -#define XCL_CNTH4_bm (1<<4) /* TC16 Counter High Byte bit 4 mask. */ -#define XCL_CNTH4_bp 4 /* TC16 Counter High Byte bit 4 position. */ -#define XCL_CNTH5_bm (1<<5) /* TC16 Counter High Byte bit 5 mask. */ -#define XCL_CNTH5_bp 5 /* TC16 Counter High Byte bit 5 position. */ -#define XCL_CNTH6_bm (1<<6) /* TC16 Counter High Byte bit 6 mask. */ -#define XCL_CNTH6_bp 6 /* TC16 Counter High Byte bit 6 position. */ -#define XCL_CNTH7_bm (1<<7) /* TC16 Counter High Byte bit 7 mask. */ -#define XCL_CNTH7_bp 7 /* TC16 Counter High Byte bit 7 position. */ - -#define XCL_PCNT1_gm 0xFF /* Peripheral Counter 1 Byte group mask. */ -#define XCL_PCNT1_gp 0 /* Peripheral Counter 1 Byte group position. */ -#define XCL_PCNT10_bm (1<<0) /* Peripheral Counter 1 Byte bit 0 mask. */ -#define XCL_PCNT10_bp 0 /* Peripheral Counter 1 Byte bit 0 position. */ -#define XCL_PCNT11_bm (1<<1) /* Peripheral Counter 1 Byte bit 1 mask. */ -#define XCL_PCNT11_bp 1 /* Peripheral Counter 1 Byte bit 1 position. */ -#define XCL_PCNT12_bm (1<<2) /* Peripheral Counter 1 Byte bit 2 mask. */ -#define XCL_PCNT12_bp 2 /* Peripheral Counter 1 Byte bit 2 position. */ -#define XCL_PCNT13_bm (1<<3) /* Peripheral Counter 1 Byte bit 3 mask. */ -#define XCL_PCNT13_bp 3 /* Peripheral Counter 1 Byte bit 3 position. */ -#define XCL_PCNT14_bm (1<<4) /* Peripheral Counter 1 Byte bit 4 mask. */ -#define XCL_PCNT14_bp 4 /* Peripheral Counter 1 Byte bit 4 position. */ -#define XCL_PCNT15_bm (1<<5) /* Peripheral Counter 1 Byte bit 5 mask. */ -#define XCL_PCNT15_bp 5 /* Peripheral Counter 1 Byte bit 5 position. */ -#define XCL_PCNT16_bm (1<<6) /* Peripheral Counter 1 Byte bit 6 mask. */ -#define XCL_PCNT16_bp 6 /* Peripheral Counter 1 Byte bit 6 position. */ -#define XCL_PCNT17_bm (1<<7) /* Peripheral Counter 1 Byte bit 7 mask. */ -#define XCL_PCNT17_bp 7 /* Peripheral Counter 1 Byte bit 7 position. */ - -#define XCL_PCNT21_gm 0xF0 /* Peripheral High Counter 2 Bits group mask. */ -#define XCL_PCNT21_gp 4 /* Peripheral High Counter 2 Bits group position. */ -#define XCL_PCNT210_bm (1<<4) /* Peripheral High Counter 2 Bits bit 0 mask. */ -#define XCL_PCNT210_bp 4 /* Peripheral High Counter 2 Bits bit 0 position. */ -#define XCL_PCNT211_bm (1<<5) /* Peripheral High Counter 2 Bits bit 1 mask. */ -#define XCL_PCNT211_bp 5 /* Peripheral High Counter 2 Bits bit 1 position. */ -#define XCL_PCNT212_bm (1<<6) /* Peripheral High Counter 2 Bits bit 2 mask. */ -#define XCL_PCNT212_bp 6 /* Peripheral High Counter 2 Bits bit 2 position. */ -#define XCL_PCNT213_bm (1<<7) /* Peripheral High Counter 2 Bits bit 3 mask. */ -#define XCL_PCNT213_bp 7 /* Peripheral High Counter 2 Bits bit 3 position. */ - -#define XCL_PCNT20_gm 0x0F /* Peripheral Low Counter 2 Bits group mask. */ -#define XCL_PCNT20_gp 0 /* Peripheral Low Counter 2 Bits group position. */ -#define XCL_PCNT200_bm (1<<0) /* Peripheral Low Counter 2 Bits bit 0 mask. */ -#define XCL_PCNT200_bp 0 /* Peripheral Low Counter 2 Bits bit 0 position. */ -#define XCL_PCNT201_bm (1<<1) /* Peripheral Low Counter 2 Bits bit 1 mask. */ -#define XCL_PCNT201_bp 1 /* Peripheral Low Counter 2 Bits bit 1 position. */ -#define XCL_PCNT202_bm (1<<2) /* Peripheral Low Counter 2 Bits bit 2 mask. */ -#define XCL_PCNT202_bp 2 /* Peripheral Low Counter 2 Bits bit 2 position. */ -#define XCL_PCNT203_bm (1<<3) /* Peripheral Low Counter 2 Bits bit 3 mask. */ -#define XCL_PCNT203_bp 3 /* Peripheral Low Counter 2 Bits bit 3 position. */ - -/* XCL.CMPL bit masks and bit positions */ -#define XCL_CMPL_gm 0xFF /* TC16 Compare Low Byte group mask. */ -#define XCL_CMPL_gp 0 /* TC16 Compare Low Byte group position. */ -#define XCL_CMPL0_bm (1<<0) /* TC16 Compare Low Byte bit 0 mask. */ -#define XCL_CMPL0_bp 0 /* TC16 Compare Low Byte bit 0 position. */ -#define XCL_CMPL1_bm (1<<1) /* TC16 Compare Low Byte bit 1 mask. */ -#define XCL_CMPL1_bp 1 /* TC16 Compare Low Byte bit 1 position. */ -#define XCL_CMPL2_bm (1<<2) /* TC16 Compare Low Byte bit 2 mask. */ -#define XCL_CMPL2_bp 2 /* TC16 Compare Low Byte bit 2 position. */ -#define XCL_CMPL3_bm (1<<3) /* TC16 Compare Low Byte bit 3 mask. */ -#define XCL_CMPL3_bp 3 /* TC16 Compare Low Byte bit 3 position. */ -#define XCL_CMPL4_bm (1<<4) /* TC16 Compare Low Byte bit 4 mask. */ -#define XCL_CMPL4_bp 4 /* TC16 Compare Low Byte bit 4 position. */ -#define XCL_CMPL5_bm (1<<5) /* TC16 Compare Low Byte bit 5 mask. */ -#define XCL_CMPL5_bp 5 /* TC16 Compare Low Byte bit 5 position. */ -#define XCL_CMPL6_bm (1<<6) /* TC16 Compare Low Byte bit 6 mask. */ -#define XCL_CMPL6_bp 6 /* TC16 Compare Low Byte bit 6 position. */ -#define XCL_CMPL7_bm (1<<7) /* TC16 Compare Low Byte bit 7 mask. */ -#define XCL_CMPL7_bp 7 /* TC16 Compare Low Byte bit 7 position. */ - -#define XCL_BCMP0_gm 0xFF /* BTC0 Compare Byte group mask. */ -#define XCL_BCMP0_gp 0 /* BTC0 Compare Byte group position. */ -#define XCL_BCMP00_bm (1<<0) /* BTC0 Compare Byte bit 0 mask. */ -#define XCL_BCMP00_bp 0 /* BTC0 Compare Byte bit 0 position. */ -#define XCL_BCMP01_bm (1<<1) /* BTC0 Compare Byte bit 1 mask. */ -#define XCL_BCMP01_bp 1 /* BTC0 Compare Byte bit 1 position. */ -#define XCL_BCMP02_bm (1<<2) /* BTC0 Compare Byte bit 2 mask. */ -#define XCL_BCMP02_bp 2 /* BTC0 Compare Byte bit 2 position. */ -#define XCL_BCMP03_bm (1<<3) /* BTC0 Compare Byte bit 3 mask. */ -#define XCL_BCMP03_bp 3 /* BTC0 Compare Byte bit 3 position. */ -#define XCL_BCMP04_bm (1<<4) /* BTC0 Compare Byte bit 4 mask. */ -#define XCL_BCMP04_bp 4 /* BTC0 Compare Byte bit 4 position. */ -#define XCL_BCMP05_bm (1<<5) /* BTC0 Compare Byte bit 5 mask. */ -#define XCL_BCMP05_bp 5 /* BTC0 Compare Byte bit 5 position. */ -#define XCL_BCMP06_bm (1<<6) /* BTC0 Compare Byte bit 6 mask. */ -#define XCL_BCMP06_bp 6 /* BTC0 Compare Byte bit 6 position. */ -#define XCL_BCMP07_bm (1<<7) /* BTC0 Compare Byte bit 7 mask. */ -#define XCL_BCMP07_bp 7 /* BTC0 Compare Byte bit 7 position. */ - -/* XCL.CMPH bit masks and bit positions */ -#define XCL_CMPH_gm 0xFF /* TC16 Compare High Byte group mask. */ -#define XCL_CMPH_gp 0 /* TC16 Compare High Byte group position. */ -#define XCL_CMPH0_bm (1<<0) /* TC16 Compare High Byte bit 0 mask. */ -#define XCL_CMPH0_bp 0 /* TC16 Compare High Byte bit 0 position. */ -#define XCL_CMPH1_bm (1<<1) /* TC16 Compare High Byte bit 1 mask. */ -#define XCL_CMPH1_bp 1 /* TC16 Compare High Byte bit 1 position. */ -#define XCL_CMPH2_bm (1<<2) /* TC16 Compare High Byte bit 2 mask. */ -#define XCL_CMPH2_bp 2 /* TC16 Compare High Byte bit 2 position. */ -#define XCL_CMPH3_bm (1<<3) /* TC16 Compare High Byte bit 3 mask. */ -#define XCL_CMPH3_bp 3 /* TC16 Compare High Byte bit 3 position. */ -#define XCL_CMPH4_bm (1<<4) /* TC16 Compare High Byte bit 4 mask. */ -#define XCL_CMPH4_bp 4 /* TC16 Compare High Byte bit 4 position. */ -#define XCL_CMPH5_bm (1<<5) /* TC16 Compare High Byte bit 5 mask. */ -#define XCL_CMPH5_bp 5 /* TC16 Compare High Byte bit 5 position. */ -#define XCL_CMPH6_bm (1<<6) /* TC16 Compare High Byte bit 6 mask. */ -#define XCL_CMPH6_bp 6 /* TC16 Compare High Byte bit 6 position. */ -#define XCL_CMPH7_bm (1<<7) /* TC16 Compare High Byte bit 7 mask. */ -#define XCL_CMPH7_bp 7 /* TC16 Compare High Byte bit 7 position. */ - -#define XCL_BCMP1_gm 0xFF /* BTC1 Compare Byte group mask. */ -#define XCL_BCMP1_gp 0 /* BTC1 Compare Byte group position. */ -#define XCL_BCMP10_bm (1<<0) /* BTC1 Compare Byte bit 0 mask. */ -#define XCL_BCMP10_bp 0 /* BTC1 Compare Byte bit 0 position. */ -#define XCL_BCMP11_bm (1<<1) /* BTC1 Compare Byte bit 1 mask. */ -#define XCL_BCMP11_bp 1 /* BTC1 Compare Byte bit 1 position. */ -#define XCL_BCMP12_bm (1<<2) /* BTC1 Compare Byte bit 2 mask. */ -#define XCL_BCMP12_bp 2 /* BTC1 Compare Byte bit 2 position. */ -#define XCL_BCMP13_bm (1<<3) /* BTC1 Compare Byte bit 3 mask. */ -#define XCL_BCMP13_bp 3 /* BTC1 Compare Byte bit 3 position. */ -#define XCL_BCMP14_bm (1<<4) /* BTC1 Compare Byte bit 4 mask. */ -#define XCL_BCMP14_bp 4 /* BTC1 Compare Byte bit 4 position. */ -#define XCL_BCMP15_bm (1<<5) /* BTC1 Compare Byte bit 5 mask. */ -#define XCL_BCMP15_bp 5 /* BTC1 Compare Byte bit 5 position. */ -#define XCL_BCMP16_bm (1<<6) /* BTC1 Compare Byte bit 6 mask. */ -#define XCL_BCMP16_bp 6 /* BTC1 Compare Byte bit 6 position. */ -#define XCL_BCMP17_bm (1<<7) /* BTC1 Compare Byte bit 7 mask. */ -#define XCL_BCMP17_bp 7 /* BTC1 Compare Byte bit 7 position. */ - -/* XCL.PERCAPTL bit masks and bit positions */ -#define XCL_PERL_gm 0xFF /* TC16 Low Byte Period group mask. */ -#define XCL_PERL_gp 0 /* TC16 Low Byte Period group position. */ -#define XCL_PERL0_bm (1<<0) /* TC16 Low Byte Period bit 0 mask. */ -#define XCL_PERL0_bp 0 /* TC16 Low Byte Period bit 0 position. */ -#define XCL_PERL1_bm (1<<1) /* TC16 Low Byte Period bit 1 mask. */ -#define XCL_PERL1_bp 1 /* TC16 Low Byte Period bit 1 position. */ -#define XCL_PERL2_bm (1<<2) /* TC16 Low Byte Period bit 2 mask. */ -#define XCL_PERL2_bp 2 /* TC16 Low Byte Period bit 2 position. */ -#define XCL_PERL3_bm (1<<3) /* TC16 Low Byte Period bit 3 mask. */ -#define XCL_PERL3_bp 3 /* TC16 Low Byte Period bit 3 position. */ -#define XCL_PERL4_bm (1<<4) /* TC16 Low Byte Period bit 4 mask. */ -#define XCL_PERL4_bp 4 /* TC16 Low Byte Period bit 4 position. */ -#define XCL_PERL5_bm (1<<5) /* TC16 Low Byte Period bit 5 mask. */ -#define XCL_PERL5_bp 5 /* TC16 Low Byte Period bit 5 position. */ -#define XCL_PERL6_bm (1<<6) /* TC16 Low Byte Period bit 6 mask. */ -#define XCL_PERL6_bp 6 /* TC16 Low Byte Period bit 6 position. */ -#define XCL_PERL7_bm (1<<7) /* TC16 Low Byte Period bit 7 mask. */ -#define XCL_PERL7_bp 7 /* TC16 Low Byte Period bit 7 position. */ - -#define XCL_CAPTL_gm 0xFF /* TC16 Capture Value Low Byte group mask. */ -#define XCL_CAPTL_gp 0 /* TC16 Capture Value Low Byte group position. */ -#define XCL_CAPTL0_bm (1<<0) /* TC16 Capture Value Low Byte bit 0 mask. */ -#define XCL_CAPTL0_bp 0 /* TC16 Capture Value Low Byte bit 0 position. */ -#define XCL_CAPTL1_bm (1<<1) /* TC16 Capture Value Low Byte bit 1 mask. */ -#define XCL_CAPTL1_bp 1 /* TC16 Capture Value Low Byte bit 1 position. */ -#define XCL_CAPTL2_bm (1<<2) /* TC16 Capture Value Low Byte bit 2 mask. */ -#define XCL_CAPTL2_bp 2 /* TC16 Capture Value Low Byte bit 2 position. */ -#define XCL_CAPTL3_bm (1<<3) /* TC16 Capture Value Low Byte bit 3 mask. */ -#define XCL_CAPTL3_bp 3 /* TC16 Capture Value Low Byte bit 3 position. */ -#define XCL_CAPTL4_bm (1<<4) /* TC16 Capture Value Low Byte bit 4 mask. */ -#define XCL_CAPTL4_bp 4 /* TC16 Capture Value Low Byte bit 4 position. */ -#define XCL_CAPTL5_bm (1<<5) /* TC16 Capture Value Low Byte bit 5 mask. */ -#define XCL_CAPTL5_bp 5 /* TC16 Capture Value Low Byte bit 5 position. */ -#define XCL_CAPTL6_bm (1<<6) /* TC16 Capture Value Low Byte bit 6 mask. */ -#define XCL_CAPTL6_bp 6 /* TC16 Capture Value Low Byte bit 6 position. */ -#define XCL_CAPTL7_bm (1<<7) /* TC16 Capture Value Low Byte bit 7 mask. */ -#define XCL_CAPTL7_bp 7 /* TC16 Capture Value Low Byte bit 7 position. */ - -#define XCL_BPER0_gm 0xFF /* BTC0 Period group mask. */ -#define XCL_BPER0_gp 0 /* BTC0 Period group position. */ -#define XCL_BPER00_bm (1<<0) /* BTC0 Period bit 0 mask. */ -#define XCL_BPER00_bp 0 /* BTC0 Period bit 0 position. */ -#define XCL_BPER01_bm (1<<1) /* BTC0 Period bit 1 mask. */ -#define XCL_BPER01_bp 1 /* BTC0 Period bit 1 position. */ -#define XCL_BPER02_bm (1<<2) /* BTC0 Period bit 2 mask. */ -#define XCL_BPER02_bp 2 /* BTC0 Period bit 2 position. */ -#define XCL_BPER03_bm (1<<3) /* BTC0 Period bit 3 mask. */ -#define XCL_BPER03_bp 3 /* BTC0 Period bit 3 position. */ -#define XCL_BPER04_bm (1<<4) /* BTC0 Period bit 4 mask. */ -#define XCL_BPER04_bp 4 /* BTC0 Period bit 4 position. */ -#define XCL_BPER05_bm (1<<5) /* BTC0 Period bit 5 mask. */ -#define XCL_BPER05_bp 5 /* BTC0 Period bit 5 position. */ -#define XCL_BPER06_bm (1<<6) /* BTC0 Period bit 6 mask. */ -#define XCL_BPER06_bp 6 /* BTC0 Period bit 6 position. */ -#define XCL_BPER07_bm (1<<7) /* BTC0 Period bit 7 mask. */ -#define XCL_BPER07_bp 7 /* BTC0 Period bit 7 position. */ - -#define XCL_BCAPT0_gm 0xFF /* BTC0 Capture Value Byte group mask. */ -#define XCL_BCAPT0_gp 0 /* BTC0 Capture Value Byte group position. */ -#define XCL_BCAPT00_bm (1<<0) /* BTC0 Capture Value Byte bit 0 mask. */ -#define XCL_BCAPT00_bp 0 /* BTC0 Capture Value Byte bit 0 position. */ -#define XCL_BCAPT01_bm (1<<1) /* BTC0 Capture Value Byte bit 1 mask. */ -#define XCL_BCAPT01_bp 1 /* BTC0 Capture Value Byte bit 1 position. */ -#define XCL_BCAPT02_bm (1<<2) /* BTC0 Capture Value Byte bit 2 mask. */ -#define XCL_BCAPT02_bp 2 /* BTC0 Capture Value Byte bit 2 position. */ -#define XCL_BCAPT03_bm (1<<3) /* BTC0 Capture Value Byte bit 3 mask. */ -#define XCL_BCAPT03_bp 3 /* BTC0 Capture Value Byte bit 3 position. */ -#define XCL_BCAPT04_bm (1<<4) /* BTC0 Capture Value Byte bit 4 mask. */ -#define XCL_BCAPT04_bp 4 /* BTC0 Capture Value Byte bit 4 position. */ -#define XCL_BCAPT05_bm (1<<5) /* BTC0 Capture Value Byte bit 5 mask. */ -#define XCL_BCAPT05_bp 5 /* BTC0 Capture Value Byte bit 5 position. */ -#define XCL_BCAPT06_bm (1<<6) /* BTC0 Capture Value Byte bit 6 mask. */ -#define XCL_BCAPT06_bp 6 /* BTC0 Capture Value Byte bit 6 position. */ -#define XCL_BCAPT07_bm (1<<7) /* BTC0 Capture Value Byte bit 7 mask. */ -#define XCL_BCAPT07_bp 7 /* BTC0 Capture Value Byte bit 7 position. */ - -/* XCL.PERCAPTH bit masks and bit positions */ -#define XCL_PERH_gm 0xFF /* TC16 High Byte Period group mask. */ -#define XCL_PERH_gp 0 /* TC16 High Byte Period group position. */ -#define XCL_PERH0_bm (1<<0) /* TC16 High Byte Period bit 0 mask. */ -#define XCL_PERH0_bp 0 /* TC16 High Byte Period bit 0 position. */ -#define XCL_PERH1_bm (1<<1) /* TC16 High Byte Period bit 1 mask. */ -#define XCL_PERH1_bp 1 /* TC16 High Byte Period bit 1 position. */ -#define XCL_PERH2_bm (1<<2) /* TC16 High Byte Period bit 2 mask. */ -#define XCL_PERH2_bp 2 /* TC16 High Byte Period bit 2 position. */ -#define XCL_PERH3_bm (1<<3) /* TC16 High Byte Period bit 3 mask. */ -#define XCL_PERH3_bp 3 /* TC16 High Byte Period bit 3 position. */ -#define XCL_PERH4_bm (1<<4) /* TC16 High Byte Period bit 4 mask. */ -#define XCL_PERH4_bp 4 /* TC16 High Byte Period bit 4 position. */ -#define XCL_PERH5_bm (1<<5) /* TC16 High Byte Period bit 5 mask. */ -#define XCL_PERH5_bp 5 /* TC16 High Byte Period bit 5 position. */ -#define XCL_PERH6_bm (1<<6) /* TC16 High Byte Period bit 6 mask. */ -#define XCL_PERH6_bp 6 /* TC16 High Byte Period bit 6 position. */ -#define XCL_PERH7_bm (1<<7) /* TC16 High Byte Period bit 7 mask. */ -#define XCL_PERH7_bp 7 /* TC16 High Byte Period bit 7 position. */ - -#define XCL_CAPTH_gm 0xFF /* TC16 Capture Value High Byte group mask. */ -#define XCL_CAPTH_gp 0 /* TC16 Capture Value High Byte group position. */ -#define XCL_CAPTH0_bm (1<<0) /* TC16 Capture Value High Byte bit 0 mask. */ -#define XCL_CAPTH0_bp 0 /* TC16 Capture Value High Byte bit 0 position. */ -#define XCL_CAPTH1_bm (1<<1) /* TC16 Capture Value High Byte bit 1 mask. */ -#define XCL_CAPTH1_bp 1 /* TC16 Capture Value High Byte bit 1 position. */ -#define XCL_CAPTH2_bm (1<<2) /* TC16 Capture Value High Byte bit 2 mask. */ -#define XCL_CAPTH2_bp 2 /* TC16 Capture Value High Byte bit 2 position. */ -#define XCL_CAPTH3_bm (1<<3) /* TC16 Capture Value High Byte bit 3 mask. */ -#define XCL_CAPTH3_bp 3 /* TC16 Capture Value High Byte bit 3 position. */ -#define XCL_CAPTH4_bm (1<<4) /* TC16 Capture Value High Byte bit 4 mask. */ -#define XCL_CAPTH4_bp 4 /* TC16 Capture Value High Byte bit 4 position. */ -#define XCL_CAPTH5_bm (1<<5) /* TC16 Capture Value High Byte bit 5 mask. */ -#define XCL_CAPTH5_bp 5 /* TC16 Capture Value High Byte bit 5 position. */ -#define XCL_CAPTH6_bm (1<<6) /* TC16 Capture Value High Byte bit 6 mask. */ -#define XCL_CAPTH6_bp 6 /* TC16 Capture Value High Byte bit 6 position. */ -#define XCL_CAPTH7_bm (1<<7) /* TC16 Capture Value High Byte bit 7 mask. */ -#define XCL_CAPTH7_bp 7 /* TC16 Capture Value High Byte bit 7 position. */ - -#define XCL_BPER1_gm 0xFF /* BTC1 Period group mask. */ -#define XCL_BPER1_gp 0 /* BTC1 Period group position. */ -#define XCL_BPER10_bm (1<<0) /* BTC1 Period bit 0 mask. */ -#define XCL_BPER10_bp 0 /* BTC1 Period bit 0 position. */ -#define XCL_BPER11_bm (1<<1) /* BTC1 Period bit 1 mask. */ -#define XCL_BPER11_bp 1 /* BTC1 Period bit 1 position. */ -#define XCL_BPER12_bm (1<<2) /* BTC1 Period bit 2 mask. */ -#define XCL_BPER12_bp 2 /* BTC1 Period bit 2 position. */ -#define XCL_BPER13_bm (1<<3) /* BTC1 Period bit 3 mask. */ -#define XCL_BPER13_bp 3 /* BTC1 Period bit 3 position. */ -#define XCL_BPER14_bm (1<<4) /* BTC1 Period bit 4 mask. */ -#define XCL_BPER14_bp 4 /* BTC1 Period bit 4 position. */ -#define XCL_BPER15_bm (1<<5) /* BTC1 Period bit 5 mask. */ -#define XCL_BPER15_bp 5 /* BTC1 Period bit 5 position. */ -#define XCL_BPER16_bm (1<<6) /* BTC1 Period bit 6 mask. */ -#define XCL_BPER16_bp 6 /* BTC1 Period bit 6 position. */ -#define XCL_BPER17_bm (1<<7) /* BTC1 Period bit 7 mask. */ -#define XCL_BPER17_bp 7 /* BTC1 Period bit 7 position. */ - -#define XCL_BCAPT1_gm 0xFF /* BTC1 Capture Value Byte group mask. */ -#define XCL_BCAPT1_gp 0 /* BTC1 Capture Value Byte group position. */ -#define XCL_BCAPT10_bm (1<<0) /* BTC1 Capture Value Byte bit 0 mask. */ -#define XCL_BCAPT10_bp 0 /* BTC1 Capture Value Byte bit 0 position. */ -#define XCL_BCAPT11_bm (1<<1) /* BTC1 Capture Value Byte bit 1 mask. */ -#define XCL_BCAPT11_bp 1 /* BTC1 Capture Value Byte bit 1 position. */ -#define XCL_BCAPT12_bm (1<<2) /* BTC1 Capture Value Byte bit 2 mask. */ -#define XCL_BCAPT12_bp 2 /* BTC1 Capture Value Byte bit 2 position. */ -#define XCL_BCAPT13_bm (1<<3) /* BTC1 Capture Value Byte bit 3 mask. */ -#define XCL_BCAPT13_bp 3 /* BTC1 Capture Value Byte bit 3 position. */ -#define XCL_BCAPT14_bm (1<<4) /* BTC1 Capture Value Byte bit 4 mask. */ -#define XCL_BCAPT14_bp 4 /* BTC1 Capture Value Byte bit 4 position. */ -#define XCL_BCAPT15_bm (1<<5) /* BTC1 Capture Value Byte bit 5 mask. */ -#define XCL_BCAPT15_bp 5 /* BTC1 Capture Value Byte bit 5 position. */ -#define XCL_BCAPT16_bm (1<<6) /* BTC1 Capture Value Byte bit 6 mask. */ -#define XCL_BCAPT16_bp 6 /* BTC1 Capture Value Byte bit 6 position. */ -#define XCL_BCAPT17_bm (1<<7) /* BTC1 Capture Value Byte bit 7 mask. */ -#define XCL_BCAPT17_bp 7 /* BTC1 Capture Value Byte bit 7 position. */ - -/* TWI - Two-Wire Interface */ -/* TWI.CTRL bit masks and bit positions */ -#define TWI_BRIDGEEN_bm 0x80 /* Bridge Enable bit mask. */ -#define TWI_BRIDGEEN_bp 7 /* Bridge Enable bit position. */ - -#define TWI_SFMPEN_bm 0x40 /* Slave Fast Mode Plus Enable bit mask. */ -#define TWI_SFMPEN_bp 6 /* Slave Fast Mode Plus Enable bit position. */ - -#define TWI_SSDAHOLD_gm 0x30 /* Slave SDA Hold Time Enable group mask. */ -#define TWI_SSDAHOLD_gp 4 /* Slave SDA Hold Time Enable group position. */ -#define TWI_SSDAHOLD0_bm (1<<4) /* Slave SDA Hold Time Enable bit 0 mask. */ -#define TWI_SSDAHOLD0_bp 4 /* Slave SDA Hold Time Enable bit 0 position. */ -#define TWI_SSDAHOLD1_bm (1<<5) /* Slave SDA Hold Time Enable bit 1 mask. */ -#define TWI_SSDAHOLD1_bp 5 /* Slave SDA Hold Time Enable bit 1 position. */ - -#define TWI_FMPEN_bm 0x08 /* FMPLUS Enable bit mask. */ -#define TWI_FMPEN_bp 3 /* FMPLUS Enable bit position. */ - -#define TWI_SDAHOLD_gm 0x06 /* SDA Hold Time Enable group mask. */ -#define TWI_SDAHOLD_gp 1 /* SDA Hold Time Enable group position. */ -#define TWI_SDAHOLD0_bm (1<<1) /* SDA Hold Time Enable bit 0 mask. */ -#define TWI_SDAHOLD0_bp 1 /* SDA Hold Time Enable bit 0 position. */ -#define TWI_SDAHOLD1_bm (1<<2) /* SDA Hold Time Enable bit 1 mask. */ -#define TWI_SDAHOLD1_bp 2 /* SDA Hold Time Enable bit 1 position. */ - -#define TWI_EDIEN_bm 0x01 /* External Driver Interface Enable bit mask. */ -#define TWI_EDIEN_bp 0 /* External Driver Interface Enable bit position. */ - -/* TWI_MASTER.CTRLA bit masks and bit positions */ -#define TWI_MASTER_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ -#define TWI_MASTER_INTLVL_gp 6 /* Interrupt Level group position. */ -#define TWI_MASTER_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ -#define TWI_MASTER_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ -#define TWI_MASTER_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ -#define TWI_MASTER_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ - -#define TWI_MASTER_RIEN_bm 0x20 /* Read Interrupt Enable bit mask. */ -#define TWI_MASTER_RIEN_bp 5 /* Read Interrupt Enable bit position. */ - -#define TWI_MASTER_WIEN_bm 0x10 /* Write Interrupt Enable bit mask. */ -#define TWI_MASTER_WIEN_bp 4 /* Write Interrupt Enable bit position. */ - -#define TWI_MASTER_ENABLE_bm 0x08 /* Enable TWI Master bit mask. */ -#define TWI_MASTER_ENABLE_bp 3 /* Enable TWI Master bit position. */ - -/* TWI_MASTER.CTRLB bit masks and bit positions */ -#define TWI_MASTER_TIMEOUT_gm 0x0C /* Inactive Bus Timeout group mask. */ -#define TWI_MASTER_TIMEOUT_gp 2 /* Inactive Bus Timeout group position. */ -#define TWI_MASTER_TIMEOUT0_bm (1<<2) /* Inactive Bus Timeout bit 0 mask. */ -#define TWI_MASTER_TIMEOUT0_bp 2 /* Inactive Bus Timeout bit 0 position. */ -#define TWI_MASTER_TIMEOUT1_bm (1<<3) /* Inactive Bus Timeout bit 1 mask. */ -#define TWI_MASTER_TIMEOUT1_bp 3 /* Inactive Bus Timeout bit 1 position. */ - -#define TWI_MASTER_QCEN_bm 0x02 /* Quick Command Enable bit mask. */ -#define TWI_MASTER_QCEN_bp 1 /* Quick Command Enable bit position. */ - -#define TWI_MASTER_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ -#define TWI_MASTER_SMEN_bp 0 /* Smart Mode Enable bit position. */ - -#define TWI_MASTER_TTOUTEN_bm 0x10 /* Ttimeout Enable bit mask. */ -#define TWI_MASTER_TTOUTEN_bp 4 /* Ttimeout Enable bit position. */ - -#define TWI_MASTER_TSEXTEN_bm 0x20 /* Slave Extend Timeout Enable bit mask. */ -#define TWI_MASTER_TSEXTEN_bp 5 /* Slave Extend Timeout Enable bit position. */ - -#define TWI_MASTER_TMEXTEN_bm 0x40 /* Master Extend Timeout Enable bit mask. */ -#define TWI_MASTER_TMEXTEN_bp 6 /* Master Extend Timeout Enable bit position. */ - -#define TWI_MASTER_TOIE_bm 0x80 /* Timeout Interrupt Enable bit mask. */ -#define TWI_MASTER_TOIE_bp 7 /* Timeout Interrupt Enable bit position. */ - -/* TWI_MASTER.CTRLC bit masks and bit positions */ -#define TWI_MASTER_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ -#define TWI_MASTER_ACKACT_bp 2 /* Acknowledge Action bit position. */ - -#define TWI_MASTER_CMD_gm 0x03 /* Command group mask. */ -#define TWI_MASTER_CMD_gp 0 /* Command group position. */ -#define TWI_MASTER_CMD0_bm (1<<0) /* Command bit 0 mask. */ -#define TWI_MASTER_CMD0_bp 0 /* Command bit 0 position. */ -#define TWI_MASTER_CMD1_bm (1<<1) /* Command bit 1 mask. */ -#define TWI_MASTER_CMD1_bp 1 /* Command bit 1 position. */ - -/* TWI_MASTER.STATUS bit masks and bit positions */ -#define TWI_MASTER_RIF_bm 0x80 /* Read Interrupt Flag bit mask. */ -#define TWI_MASTER_RIF_bp 7 /* Read Interrupt Flag bit position. */ - -#define TWI_MASTER_WIF_bm 0x40 /* Write Interrupt Flag bit mask. */ -#define TWI_MASTER_WIF_bp 6 /* Write Interrupt Flag bit position. */ - -#define TWI_MASTER_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ -#define TWI_MASTER_CLKHOLD_bp 5 /* Clock Hold bit position. */ - -#define TWI_MASTER_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ -#define TWI_MASTER_RXACK_bp 4 /* Received Acknowledge bit position. */ - -#define TWI_MASTER_ARBLOST_bm 0x08 /* Arbitration Lost bit mask. */ -#define TWI_MASTER_ARBLOST_bp 3 /* Arbitration Lost bit position. */ - -#define TWI_MASTER_BUSERR_bm 0x04 /* Bus Error bit mask. */ -#define TWI_MASTER_BUSERR_bp 2 /* Bus Error bit position. */ - -#define TWI_MASTER_BUSSTATE_gm 0x03 /* Bus State group mask. */ -#define TWI_MASTER_BUSSTATE_gp 0 /* Bus State group position. */ -#define TWI_MASTER_BUSSTATE0_bm (1<<0) /* Bus State bit 0 mask. */ -#define TWI_MASTER_BUSSTATE0_bp 0 /* Bus State bit 0 position. */ -#define TWI_MASTER_BUSSTATE1_bm (1<<1) /* Bus State bit 1 mask. */ -#define TWI_MASTER_BUSSTATE1_bp 1 /* Bus State bit 1 position. */ - -/* TWI_SLAVE.CTRLA bit masks and bit positions */ -#define TWI_SLAVE_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ -#define TWI_SLAVE_INTLVL_gp 6 /* Interrupt Level group position. */ -#define TWI_SLAVE_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ -#define TWI_SLAVE_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ -#define TWI_SLAVE_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ -#define TWI_SLAVE_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ - -#define TWI_SLAVE_DIEN_bm 0x20 /* Data Interrupt Enable bit mask. */ -#define TWI_SLAVE_DIEN_bp 5 /* Data Interrupt Enable bit position. */ - -#define TWI_SLAVE_APIEN_bm 0x10 /* Address/Stop Interrupt Enable bit mask. */ -#define TWI_SLAVE_APIEN_bp 4 /* Address/Stop Interrupt Enable bit position. */ - -#define TWI_SLAVE_ENABLE_bm 0x08 /* Enable TWI Slave bit mask. */ -#define TWI_SLAVE_ENABLE_bp 3 /* Enable TWI Slave bit position. */ - -#define TWI_SLAVE_PIEN_bm 0x04 /* Stop Interrupt Enable bit mask. */ -#define TWI_SLAVE_PIEN_bp 2 /* Stop Interrupt Enable bit position. */ - -#define TWI_SLAVE_PMEN_bm 0x02 /* Promiscuous Mode Enable bit mask. */ -#define TWI_SLAVE_PMEN_bp 1 /* Promiscuous Mode Enable bit position. */ - -#define TWI_SLAVE_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ -#define TWI_SLAVE_SMEN_bp 0 /* Smart Mode Enable bit position. */ - -/* TWI_SLAVE.CTRLB bit masks and bit positions */ -#define TWI_SLAVE_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ -#define TWI_SLAVE_ACKACT_bp 2 /* Acknowledge Action bit position. */ - -#define TWI_SLAVE_CMD_gm 0x03 /* Command group mask. */ -#define TWI_SLAVE_CMD_gp 0 /* Command group position. */ -#define TWI_SLAVE_CMD0_bm (1<<0) /* Command bit 0 mask. */ -#define TWI_SLAVE_CMD0_bp 0 /* Command bit 0 position. */ -#define TWI_SLAVE_CMD1_bm (1<<1) /* Command bit 1 mask. */ -#define TWI_SLAVE_CMD1_bp 1 /* Command bit 1 position. */ - -#define TWI_SLAVE_TTOUTEN_bm 0x10 /* Ttimeout Enable bit mask. */ -#define TWI_SLAVE_TTOUTEN_bp 4 /* Ttimeout Enable bit position. */ - -#define TWI_SLAVE_TOIE_bm 0x80 /* Timeout Interrupt Enable bit mask. */ -#define TWI_SLAVE_TOIE_bp 7 /* Timeout Interrupt Enable bit position. */ - -/* TWI_SLAVE.STATUS bit masks and bit positions */ -#define TWI_SLAVE_DIF_bm 0x80 /* Data Interrupt Flag bit mask. */ -#define TWI_SLAVE_DIF_bp 7 /* Data Interrupt Flag bit position. */ - -#define TWI_SLAVE_APIF_bm 0x40 /* Address/Stop Interrupt Flag bit mask. */ -#define TWI_SLAVE_APIF_bp 6 /* Address/Stop Interrupt Flag bit position. */ - -#define TWI_SLAVE_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ -#define TWI_SLAVE_CLKHOLD_bp 5 /* Clock Hold bit position. */ - -#define TWI_SLAVE_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ -#define TWI_SLAVE_RXACK_bp 4 /* Received Acknowledge bit position. */ - -#define TWI_SLAVE_COLL_bm 0x08 /* Collision bit mask. */ -#define TWI_SLAVE_COLL_bp 3 /* Collision bit position. */ - -#define TWI_SLAVE_BUSERR_bm 0x04 /* Bus Error bit mask. */ -#define TWI_SLAVE_BUSERR_bp 2 /* Bus Error bit position. */ - -#define TWI_SLAVE_DIR_bm 0x02 /* Read/Write Direction bit mask. */ -#define TWI_SLAVE_DIR_bp 1 /* Read/Write Direction bit position. */ - -#define TWI_SLAVE_AP_bm 0x01 /* Slave Address or Stop bit mask. */ -#define TWI_SLAVE_AP_bp 0 /* Slave Address or Stop bit position. */ - -/* TWI_SLAVE.ADDRMASK bit masks and bit positions */ -#define TWI_SLAVE_ADDRMASK_gm 0xFE /* Address Mask group mask. */ -#define TWI_SLAVE_ADDRMASK_gp 1 /* Address Mask group position. */ -#define TWI_SLAVE_ADDRMASK0_bm (1<<1) /* Address Mask bit 0 mask. */ -#define TWI_SLAVE_ADDRMASK0_bp 1 /* Address Mask bit 0 position. */ -#define TWI_SLAVE_ADDRMASK1_bm (1<<2) /* Address Mask bit 1 mask. */ -#define TWI_SLAVE_ADDRMASK1_bp 2 /* Address Mask bit 1 position. */ -#define TWI_SLAVE_ADDRMASK2_bm (1<<3) /* Address Mask bit 2 mask. */ -#define TWI_SLAVE_ADDRMASK2_bp 3 /* Address Mask bit 2 position. */ -#define TWI_SLAVE_ADDRMASK3_bm (1<<4) /* Address Mask bit 3 mask. */ -#define TWI_SLAVE_ADDRMASK3_bp 4 /* Address Mask bit 3 position. */ -#define TWI_SLAVE_ADDRMASK4_bm (1<<5) /* Address Mask bit 4 mask. */ -#define TWI_SLAVE_ADDRMASK4_bp 5 /* Address Mask bit 4 position. */ -#define TWI_SLAVE_ADDRMASK5_bm (1<<6) /* Address Mask bit 5 mask. */ -#define TWI_SLAVE_ADDRMASK5_bp 6 /* Address Mask bit 5 position. */ -#define TWI_SLAVE_ADDRMASK6_bm (1<<7) /* Address Mask bit 6 mask. */ -#define TWI_SLAVE_ADDRMASK6_bp 7 /* Address Mask bit 6 position. */ - -#define TWI_SLAVE_ADDREN_bm 0x01 /* Address Enable bit mask. */ -#define TWI_SLAVE_ADDREN_bp 0 /* Address Enable bit position. */ - -/* TWI_TIMEOUT.TOS bit masks and bit positions */ -#define TWI_TIMEOUT_TTOUTMIF_bm 0x01 /* Master Ttimeout Interrupt Flag bit mask. */ -#define TWI_TIMEOUT_TTOUTMIF_bp 0 /* Master Ttimeout Interrupt Flag bit position. */ - -#define TWI_TIMEOUT_TSEXTIF_bm 0x02 /* Slave Extend Interrupt Flag bit mask. */ -#define TWI_TIMEOUT_TSEXTIF_bp 1 /* Slave Extend Interrupt Flag bit position. */ - -#define TWI_TIMEOUT_TMEXTIF_bm 0x04 /* Master Extend Interrupt Flag bit mask. */ -#define TWI_TIMEOUT_TMEXTIF_bp 2 /* Master Extend Interrupt Flag bit position. */ - -#define TWI_TIMEOUT_TTOUTSIF_bm 0x10 /* Slave Ttimeout Interrupt Flag bit mask. */ -#define TWI_TIMEOUT_TTOUTSIF_bp 4 /* Slave Ttimeout Interrupt Flag bit position. */ - -/* TWI_TIMEOUT.TOCONF bit masks and bit positions */ -#define TWI_TIMEOUT_TTOUTMSEL_gm 0x07 /* Master Ttimeout Select group mask. */ -#define TWI_TIMEOUT_TTOUTMSEL_gp 0 /* Master Ttimeout Select group position. */ -#define TWI_TIMEOUT_TTOUTMSEL0_bm (1<<0) /* Master Ttimeout Select bit 0 mask. */ -#define TWI_TIMEOUT_TTOUTMSEL0_bp 0 /* Master Ttimeout Select bit 0 position. */ -#define TWI_TIMEOUT_TTOUTMSEL1_bm (1<<1) /* Master Ttimeout Select bit 1 mask. */ -#define TWI_TIMEOUT_TTOUTMSEL1_bp 1 /* Master Ttimeout Select bit 1 position. */ -#define TWI_TIMEOUT_TTOUTMSEL2_bm (1<<2) /* Master Ttimeout Select bit 2 mask. */ -#define TWI_TIMEOUT_TTOUTMSEL2_bp 2 /* Master Ttimeout Select bit 2 position. */ - -#define TWI_TIMEOUT_TMSEXTSEL_gm 0x18 /* Master/Slave Timeout Select group mask. */ -#define TWI_TIMEOUT_TMSEXTSEL_gp 3 /* Master/Slave Timeout Select group position. */ -#define TWI_TIMEOUT_TMSEXTSEL0_bm (1<<3) /* Master/Slave Timeout Select bit 0 mask. */ -#define TWI_TIMEOUT_TMSEXTSEL0_bp 3 /* Master/Slave Timeout Select bit 0 position. */ -#define TWI_TIMEOUT_TMSEXTSEL1_bm (1<<4) /* Master/Slave Timeout Select bit 1 mask. */ -#define TWI_TIMEOUT_TMSEXTSEL1_bp 4 /* Master/Slave Timeout Select bit 1 position. */ - -#define TWI_TIMEOUT_TTOUTSSEL_gm 0xE0 /* Slave Ttimeout Select group mask. */ -#define TWI_TIMEOUT_TTOUTSSEL_gp 5 /* Slave Ttimeout Select group position. */ -#define TWI_TIMEOUT_TTOUTSSEL0_bm (1<<5) /* Slave Ttimeout Select bit 0 mask. */ -#define TWI_TIMEOUT_TTOUTSSEL0_bp 5 /* Slave Ttimeout Select bit 0 position. */ -#define TWI_TIMEOUT_TTOUTSSEL1_bm (1<<6) /* Slave Ttimeout Select bit 1 mask. */ -#define TWI_TIMEOUT_TTOUTSSEL1_bp 6 /* Slave Ttimeout Select bit 1 position. */ -#define TWI_TIMEOUT_TTOUTSSEL2_bm (1<<7) /* Slave Ttimeout Select bit 2 mask. */ -#define TWI_TIMEOUT_TTOUTSSEL2_bp 7 /* Slave Ttimeout Select bit 2 position. */ - -/* PORT - Port Configuration */ -/* PORT.INTCTRL bit masks and bit positions */ -#define PORT_INTLVL_gm 0x03 /* Port Interrupt Level group mask. */ -#define PORT_INTLVL_gp 0 /* Port Interrupt Level group position. */ -#define PORT_INTLVL0_bm (1<<0) /* Port Interrupt Level bit 0 mask. */ -#define PORT_INTLVL0_bp 0 /* Port Interrupt Level bit 0 position. */ -#define PORT_INTLVL1_bm (1<<1) /* Port Interrupt Level bit 1 mask. */ -#define PORT_INTLVL1_bp 1 /* Port Interrupt Level bit 1 position. */ - -/* PORT.INTFLAGS bit masks and bit positions */ -#define PORT_INT7IF_bm 0x80 /* Pin 7 Interrupt Flag bit mask. */ -#define PORT_INT7IF_bp 7 /* Pin 7 Interrupt Flag bit position. */ - -#define PORT_INT6IF_bm 0x40 /* Pin 6 Interrupt Flag bit mask. */ -#define PORT_INT6IF_bp 6 /* Pin 6 Interrupt Flag bit position. */ - -#define PORT_INT5IF_bm 0x20 /* Pin 5 Interrupt Flag bit mask. */ -#define PORT_INT5IF_bp 5 /* Pin 5 Interrupt Flag bit position. */ - -#define PORT_INT4IF_bm 0x10 /* Pin 4 Interrupt Flag bit mask. */ -#define PORT_INT4IF_bp 4 /* Pin 4 Interrupt Flag bit position. */ - -#define PORT_INT3IF_bm 0x08 /* Pin 3 Interrupt Flag bit mask. */ -#define PORT_INT3IF_bp 3 /* Pin 3 Interrupt Flag bit position. */ - -#define PORT_INT2IF_bm 0x04 /* Pin 2 Interrupt Flag bit mask. */ -#define PORT_INT2IF_bp 2 /* Pin 2 Interrupt Flag bit position. */ - -#define PORT_INT1IF_bm 0x02 /* Pin 1 Interrupt Flag bit mask. */ -#define PORT_INT1IF_bp 1 /* Pin 1 Interrupt Flag bit position. */ - -#define PORT_INT0IF_bm 0x01 /* Pin 0 Interrupt Flag bit mask. */ -#define PORT_INT0IF_bp 0 /* Pin 0 Interrupt Flag bit position. */ - -/* PORT.REMAP bit masks and bit positions */ -#define PORT_USART0_bm 0x10 /* Usart0 bit mask. */ -#define PORT_USART0_bp 4 /* Usart0 bit position. */ - -#define PORT_TC4D_bm 0x08 /* Timer/Counter 4 Output Compare D bit mask. */ -#define PORT_TC4D_bp 3 /* Timer/Counter 4 Output Compare D bit position. */ - -#define PORT_TC4C_bm 0x04 /* Timer/Counter 4 Output Compare C bit mask. */ -#define PORT_TC4C_bp 2 /* Timer/Counter 4 Output Compare C bit position. */ - -#define PORT_TC4B_bm 0x02 /* Timer/Counter 4 Output Compare B bit mask. */ -#define PORT_TC4B_bp 1 /* Timer/Counter 4 Output Compare B bit position. */ - -#define PORT_TC4A_bm 0x01 /* Timer/Counter 4 Output Compare A bit mask. */ -#define PORT_TC4A_bp 0 /* Timer/Counter 4 Output Compare A bit position. */ - -/* PORT.PIN0CTRL bit masks and bit positions */ -#define PORT_INVEN_bm 0x40 /* Inverted I/O Enable bit mask. */ -#define PORT_INVEN_bp 6 /* Inverted I/O Enable bit position. */ - -#define PORT_OPC_gm 0x38 /* Output/Pull Configuration group mask. */ -#define PORT_OPC_gp 3 /* Output/Pull Configuration group position. */ -#define PORT_OPC0_bm (1<<3) /* Output/Pull Configuration bit 0 mask. */ -#define PORT_OPC0_bp 3 /* Output/Pull Configuration bit 0 position. */ -#define PORT_OPC1_bm (1<<4) /* Output/Pull Configuration bit 1 mask. */ -#define PORT_OPC1_bp 4 /* Output/Pull Configuration bit 1 position. */ -#define PORT_OPC2_bm (1<<5) /* Output/Pull Configuration bit 2 mask. */ -#define PORT_OPC2_bp 5 /* Output/Pull Configuration bit 2 position. */ - -#define PORT_ISC_gm 0x07 /* Input/Sense Configuration group mask. */ -#define PORT_ISC_gp 0 /* Input/Sense Configuration group position. */ -#define PORT_ISC0_bm (1<<0) /* Input/Sense Configuration bit 0 mask. */ -#define PORT_ISC0_bp 0 /* Input/Sense Configuration bit 0 position. */ -#define PORT_ISC1_bm (1<<1) /* Input/Sense Configuration bit 1 mask. */ -#define PORT_ISC1_bp 1 /* Input/Sense Configuration bit 1 position. */ -#define PORT_ISC2_bm (1<<2) /* Input/Sense Configuration bit 2 mask. */ -#define PORT_ISC2_bp 2 /* Input/Sense Configuration bit 2 position. */ - -/* PORT.PIN1CTRL bit masks and bit positions */ -/* PORT_INVEN Predefined. */ -/* PORT_INVEN Predefined. */ - -/* PORT_OPC Predefined. */ -/* PORT_OPC Predefined. */ - -/* PORT_ISC Predefined. */ -/* PORT_ISC Predefined. */ - -/* PORT.PIN2CTRL bit masks and bit positions */ -/* PORT_INVEN Predefined. */ -/* PORT_INVEN Predefined. */ - -/* PORT_OPC Predefined. */ -/* PORT_OPC Predefined. */ - -/* PORT_ISC Predefined. */ -/* PORT_ISC Predefined. */ - -/* PORT.PIN3CTRL bit masks and bit positions */ -/* PORT_INVEN Predefined. */ -/* PORT_INVEN Predefined. */ - -/* PORT_OPC Predefined. */ -/* PORT_OPC Predefined. */ - -/* PORT_ISC Predefined. */ -/* PORT_ISC Predefined. */ - -/* PORT.PIN4CTRL bit masks and bit positions */ -/* PORT_INVEN Predefined. */ -/* PORT_INVEN Predefined. */ - -/* PORT_OPC Predefined. */ -/* PORT_OPC Predefined. */ - -/* PORT_ISC Predefined. */ -/* PORT_ISC Predefined. */ - -/* PORT.PIN5CTRL bit masks and bit positions */ -/* PORT_INVEN Predefined. */ -/* PORT_INVEN Predefined. */ - -/* PORT_OPC Predefined. */ -/* PORT_OPC Predefined. */ - -/* PORT_ISC Predefined. */ -/* PORT_ISC Predefined. */ - -/* PORT.PIN6CTRL bit masks and bit positions */ -/* PORT_INVEN Predefined. */ -/* PORT_INVEN Predefined. */ - -/* PORT_OPC Predefined. */ -/* PORT_OPC Predefined. */ - -/* PORT_ISC Predefined. */ -/* PORT_ISC Predefined. */ - -/* PORT.PIN7CTRL bit masks and bit positions */ -/* PORT_INVEN Predefined. */ -/* PORT_INVEN Predefined. */ - -/* PORT_OPC Predefined. */ -/* PORT_OPC Predefined. */ - -/* PORT_ISC Predefined. */ -/* PORT_ISC Predefined. */ - -/* TC - 16-bit Timer/Counter With PWM */ -/* TC4.CTRLA bit masks and bit positions */ -#define TC4_SYNCHEN_bm 0x40 /* Synchronization Enabled bit mask. */ -#define TC4_SYNCHEN_bp 6 /* Synchronization Enabled bit position. */ - -#define TC4_EVSTART_bm 0x20 /* Start on Next Event bit mask. */ -#define TC4_EVSTART_bp 5 /* Start on Next Event bit position. */ - -#define TC4_UPSTOP_bm 0x10 /* Stop on Next Update bit mask. */ -#define TC4_UPSTOP_bp 4 /* Stop on Next Update bit position. */ - -#define TC4_CLKSEL_gm 0x0F /* Clock Select group mask. */ -#define TC4_CLKSEL_gp 0 /* Clock Select group position. */ -#define TC4_CLKSEL0_bm (1<<0) /* Clock Select bit 0 mask. */ -#define TC4_CLKSEL0_bp 0 /* Clock Select bit 0 position. */ -#define TC4_CLKSEL1_bm (1<<1) /* Clock Select bit 1 mask. */ -#define TC4_CLKSEL1_bp 1 /* Clock Select bit 1 position. */ -#define TC4_CLKSEL2_bm (1<<2) /* Clock Select bit 2 mask. */ -#define TC4_CLKSEL2_bp 2 /* Clock Select bit 2 position. */ -#define TC4_CLKSEL3_bm (1<<3) /* Clock Select bit 3 mask. */ -#define TC4_CLKSEL3_bp 3 /* Clock Select bit 3 position. */ - -/* TC4.CTRLB bit masks and bit positions */ -#define TC4_BYTEM_gm 0xC0 /* Byte Mode group mask. */ -#define TC4_BYTEM_gp 6 /* Byte Mode group position. */ -#define TC4_BYTEM0_bm (1<<6) /* Byte Mode bit 0 mask. */ -#define TC4_BYTEM0_bp 6 /* Byte Mode bit 0 position. */ -#define TC4_BYTEM1_bm (1<<7) /* Byte Mode bit 1 mask. */ -#define TC4_BYTEM1_bp 7 /* Byte Mode bit 1 position. */ - -#define TC4_CIRCEN_gm 0x30 /* Circular Buffer Enable group mask. */ -#define TC4_CIRCEN_gp 4 /* Circular Buffer Enable group position. */ -#define TC4_CIRCEN0_bm (1<<4) /* Circular Buffer Enable bit 0 mask. */ -#define TC4_CIRCEN0_bp 4 /* Circular Buffer Enable bit 0 position. */ -#define TC4_CIRCEN1_bm (1<<5) /* Circular Buffer Enable bit 1 mask. */ -#define TC4_CIRCEN1_bp 5 /* Circular Buffer Enable bit 1 position. */ - -#define TC4_WGMODE_gm 0x07 /* Waveform Generation Mode group mask. */ -#define TC4_WGMODE_gp 0 /* Waveform Generation Mode group position. */ -#define TC4_WGMODE0_bm (1<<0) /* Waveform Generation Mode bit 0 mask. */ -#define TC4_WGMODE0_bp 0 /* Waveform Generation Mode bit 0 position. */ -#define TC4_WGMODE1_bm (1<<1) /* Waveform Generation Mode bit 1 mask. */ -#define TC4_WGMODE1_bp 1 /* Waveform Generation Mode bit 1 position. */ -#define TC4_WGMODE2_bm (1<<2) /* Waveform Generation Mode bit 2 mask. */ -#define TC4_WGMODE2_bp 2 /* Waveform Generation Mode bit 2 position. */ - -/* TC4.CTRLC bit masks and bit positions */ -#define TC4_POLD_bm 0x80 /* Channel D Output Polarity bit mask. */ -#define TC4_POLD_bp 7 /* Channel D Output Polarity bit position. */ - -#define TC4_POLC_bm 0x40 /* Channel C Output Polarity bit mask. */ -#define TC4_POLC_bp 6 /* Channel C Output Polarity bit position. */ - -#define TC4_POLB_bm 0x20 /* Channel B Output Polarity bit mask. */ -#define TC4_POLB_bp 5 /* Channel B Output Polarity bit position. */ - -#define TC4_POLA_bm 0x10 /* Channel A Output Polarity bit mask. */ -#define TC4_POLA_bp 4 /* Channel A Output Polarity bit position. */ - -#define TC4_CMPD_bm 0x08 /* Channel D Compare Output Value bit mask. */ -#define TC4_CMPD_bp 3 /* Channel D Compare Output Value bit position. */ - -#define TC4_CMPC_bm 0x04 /* Channel C Compare Output Value bit mask. */ -#define TC4_CMPC_bp 2 /* Channel C Compare Output Value bit position. */ - -#define TC4_CMPB_bm 0x02 /* Channel B Compare Output Value bit mask. */ -#define TC4_CMPB_bp 1 /* Channel B Compare Output Value bit position. */ - -#define TC4_CMPA_bm 0x01 /* Channel A Compare Output Value bit mask. */ -#define TC4_CMPA_bp 0 /* Channel A Compare Output Value bit position. */ - -#define TC4_HCMPD_bm 0x80 /* High Channel D Compare Output Value bit mask. */ -#define TC4_HCMPD_bp 7 /* High Channel D Compare Output Value bit position. */ - -#define TC4_HCMPC_bm 0x40 /* High Channel C Compare Output Value bit mask. */ -#define TC4_HCMPC_bp 6 /* High Channel C Compare Output Value bit position. */ - -#define TC4_HCMPB_bm 0x20 /* High Channel B Compare Output Value bit mask. */ -#define TC4_HCMPB_bp 5 /* High Channel B Compare Output Value bit position. */ - -#define TC4_HCMPA_bm 0x10 /* High Channel A Compare Output Value bit mask. */ -#define TC4_HCMPA_bp 4 /* High Channel A Compare Output Value bit position. */ - -#define TC4_LCMPD_bm 0x08 /* Low Channel D Compare Output Value bit mask. */ -#define TC4_LCMPD_bp 3 /* Low Channel D Compare Output Value bit position. */ - -#define TC4_LCMPC_bm 0x04 /* Low Channel C Compare Output Value bit mask. */ -#define TC4_LCMPC_bp 2 /* Low Channel C Compare Output Value bit position. */ - -#define TC4_LCMPB_bm 0x02 /* Low Channel B Compare Output Value bit mask. */ -#define TC4_LCMPB_bp 1 /* Low Channel B Compare Output Value bit position. */ - -#define TC4_LCMPA_bm 0x01 /* Low Channel A Compare Output Value bit mask. */ -#define TC4_LCMPA_bp 0 /* Low Channel A Compare Output Value bit position. */ - -/* TC4.CTRLD bit masks and bit positions */ -#define TC4_EVACT_gm 0xE0 /* Event Action group mask. */ -#define TC4_EVACT_gp 5 /* Event Action group position. */ -#define TC4_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ -#define TC4_EVACT0_bp 5 /* Event Action bit 0 position. */ -#define TC4_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ -#define TC4_EVACT1_bp 6 /* Event Action bit 1 position. */ -#define TC4_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ -#define TC4_EVACT2_bp 7 /* Event Action bit 2 position. */ - -#define TC4_EVDLY_bm 0x10 /* Event Delay bit mask. */ -#define TC4_EVDLY_bp 4 /* Event Delay bit position. */ - -#define TC4_EVSEL_gm 0x0F /* Event Source Select group mask. */ -#define TC4_EVSEL_gp 0 /* Event Source Select group position. */ -#define TC4_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ -#define TC4_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ -#define TC4_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ -#define TC4_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ -#define TC4_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ -#define TC4_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ -#define TC4_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ -#define TC4_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ - -/* TC4.CTRLE bit masks and bit positions */ -#define TC4_CCDMODE_gm 0xC0 /* Channel D Compare or Capture Mode group mask. */ -#define TC4_CCDMODE_gp 6 /* Channel D Compare or Capture Mode group position. */ -#define TC4_CCDMODE0_bm (1<<6) /* Channel D Compare or Capture Mode bit 0 mask. */ -#define TC4_CCDMODE0_bp 6 /* Channel D Compare or Capture Mode bit 0 position. */ -#define TC4_CCDMODE1_bm (1<<7) /* Channel D Compare or Capture Mode bit 1 mask. */ -#define TC4_CCDMODE1_bp 7 /* Channel D Compare or Capture Mode bit 1 position. */ - -#define TC4_CCCMODE_gm 0x30 /* Channel C Compare or Capture Mode group mask. */ -#define TC4_CCCMODE_gp 4 /* Channel C Compare or Capture Mode group position. */ -#define TC4_CCCMODE0_bm (1<<4) /* Channel C Compare or Capture Mode bit 0 mask. */ -#define TC4_CCCMODE0_bp 4 /* Channel C Compare or Capture Mode bit 0 position. */ -#define TC4_CCCMODE1_bm (1<<5) /* Channel C Compare or Capture Mode bit 1 mask. */ -#define TC4_CCCMODE1_bp 5 /* Channel C Compare or Capture Mode bit 1 position. */ - -#define TC4_CCBMODE_gm 0x0C /* Channel B Compare or Capture Mode group mask. */ -#define TC4_CCBMODE_gp 2 /* Channel B Compare or Capture Mode group position. */ -#define TC4_CCBMODE0_bm (1<<2) /* Channel B Compare or Capture Mode bit 0 mask. */ -#define TC4_CCBMODE0_bp 2 /* Channel B Compare or Capture Mode bit 0 position. */ -#define TC4_CCBMODE1_bm (1<<3) /* Channel B Compare or Capture Mode bit 1 mask. */ -#define TC4_CCBMODE1_bp 3 /* Channel B Compare or Capture Mode bit 1 position. */ - -#define TC4_CCAMODE_gm 0x03 /* Channel A Compare or Capture Mode group mask. */ -#define TC4_CCAMODE_gp 0 /* Channel A Compare or Capture Mode group position. */ -#define TC4_CCAMODE0_bm (1<<0) /* Channel A Compare or Capture Mode bit 0 mask. */ -#define TC4_CCAMODE0_bp 0 /* Channel A Compare or Capture Mode bit 0 position. */ -#define TC4_CCAMODE1_bm (1<<1) /* Channel A Compare or Capture Mode bit 1 mask. */ -#define TC4_CCAMODE1_bp 1 /* Channel A Compare or Capture Mode bit 1 position. */ - -#define TC4_LCCDMODE_gm 0xC0 /* Channel Low D Compare or Capture Mode group mask. */ -#define TC4_LCCDMODE_gp 6 /* Channel Low D Compare or Capture Mode group position. */ -#define TC4_LCCDMODE0_bm (1<<6) /* Channel Low D Compare or Capture Mode bit 0 mask. */ -#define TC4_LCCDMODE0_bp 6 /* Channel Low D Compare or Capture Mode bit 0 position. */ -#define TC4_LCCDMODE1_bm (1<<7) /* Channel Low D Compare or Capture Mode bit 1 mask. */ -#define TC4_LCCDMODE1_bp 7 /* Channel Low D Compare or Capture Mode bit 1 position. */ - -#define TC4_LCCCMODE_gm 0x30 /* Channel Low C Compare or Capture Mode group mask. */ -#define TC4_LCCCMODE_gp 4 /* Channel Low C Compare or Capture Mode group position. */ -#define TC4_LCCCMODE0_bm (1<<4) /* Channel Low C Compare or Capture Mode bit 0 mask. */ -#define TC4_LCCCMODE0_bp 4 /* Channel Low C Compare or Capture Mode bit 0 position. */ -#define TC4_LCCCMODE1_bm (1<<5) /* Channel Low C Compare or Capture Mode bit 1 mask. */ -#define TC4_LCCCMODE1_bp 5 /* Channel Low C Compare or Capture Mode bit 1 position. */ - -#define TC4_LCCBMODE_gm 0x0C /* Channel Low B Compare or Capture Mode group mask. */ -#define TC4_LCCBMODE_gp 2 /* Channel Low B Compare or Capture Mode group position. */ -#define TC4_LCCBMODE0_bm (1<<2) /* Channel Low B Compare or Capture Mode bit 0 mask. */ -#define TC4_LCCBMODE0_bp 2 /* Channel Low B Compare or Capture Mode bit 0 position. */ -#define TC4_LCCBMODE1_bm (1<<3) /* Channel Low B Compare or Capture Mode bit 1 mask. */ -#define TC4_LCCBMODE1_bp 3 /* Channel Low B Compare or Capture Mode bit 1 position. */ - -#define TC4_LCCAMODE_gm 0x03 /* Channel Low A Compare or Capture Mode group mask. */ -#define TC4_LCCAMODE_gp 0 /* Channel Low A Compare or Capture Mode group position. */ -#define TC4_LCCAMODE0_bm (1<<0) /* Channel Low A Compare or Capture Mode bit 0 mask. */ -#define TC4_LCCAMODE0_bp 0 /* Channel Low A Compare or Capture Mode bit 0 position. */ -#define TC4_LCCAMODE1_bm (1<<1) /* Channel Low A Compare or Capture Mode bit 1 mask. */ -#define TC4_LCCAMODE1_bp 1 /* Channel Low A Compare or Capture Mode bit 1 position. */ - -/* TC4.CTRLF bit masks and bit positions */ -#define TC4_HCCDMODE_gm 0xC0 /* Channel High D Compare or Capture Mode group mask. */ -#define TC4_HCCDMODE_gp 6 /* Channel High D Compare or Capture Mode group position. */ -#define TC4_HCCDMODE0_bm (1<<6) /* Channel High D Compare or Capture Mode bit 0 mask. */ -#define TC4_HCCDMODE0_bp 6 /* Channel High D Compare or Capture Mode bit 0 position. */ -#define TC4_HCCDMODE1_bm (1<<7) /* Channel High D Compare or Capture Mode bit 1 mask. */ -#define TC4_HCCDMODE1_bp 7 /* Channel High D Compare or Capture Mode bit 1 position. */ - -#define TC4_HCCCMODE_gm 0x30 /* Channel High C Compare or Capture Mode group mask. */ -#define TC4_HCCCMODE_gp 4 /* Channel High C Compare or Capture Mode group position. */ -#define TC4_HCCCMODE0_bm (1<<4) /* Channel High C Compare or Capture Mode bit 0 mask. */ -#define TC4_HCCCMODE0_bp 4 /* Channel High C Compare or Capture Mode bit 0 position. */ -#define TC4_HCCCMODE1_bm (1<<5) /* Channel High C Compare or Capture Mode bit 1 mask. */ -#define TC4_HCCCMODE1_bp 5 /* Channel High C Compare or Capture Mode bit 1 position. */ - -#define TC4_HCCBMODE_gm 0x0C /* Channel High B Compare or Capture Mode group mask. */ -#define TC4_HCCBMODE_gp 2 /* Channel High B Compare or Capture Mode group position. */ -#define TC4_HCCBMODE0_bm (1<<2) /* Channel High B Compare or Capture Mode bit 0 mask. */ -#define TC4_HCCBMODE0_bp 2 /* Channel High B Compare or Capture Mode bit 0 position. */ -#define TC4_HCCBMODE1_bm (1<<3) /* Channel High B Compare or Capture Mode bit 1 mask. */ -#define TC4_HCCBMODE1_bp 3 /* Channel High B Compare or Capture Mode bit 1 position. */ - -#define TC4_HCCAMODE_gm 0x03 /* Channel High A Compare or Capture Mode group mask. */ -#define TC4_HCCAMODE_gp 0 /* Channel High A Compare or Capture Mode group position. */ -#define TC4_HCCAMODE0_bm (1<<0) /* Channel High A Compare or Capture Mode bit 0 mask. */ -#define TC4_HCCAMODE0_bp 0 /* Channel High A Compare or Capture Mode bit 0 position. */ -#define TC4_HCCAMODE1_bm (1<<1) /* Channel High A Compare or Capture Mode bit 1 mask. */ -#define TC4_HCCAMODE1_bp 1 /* Channel High A Compare or Capture Mode bit 1 position. */ - -/* TC4.INTCTRLA bit masks and bit positions */ -#define TC4_TRGINTLVL_gm 0x30 /* Timer Trigger Restart Interrupt Level group mask. */ -#define TC4_TRGINTLVL_gp 4 /* Timer Trigger Restart Interrupt Level group position. */ -#define TC4_TRGINTLVL0_bm (1<<4) /* Timer Trigger Restart Interrupt Level bit 0 mask. */ -#define TC4_TRGINTLVL0_bp 4 /* Timer Trigger Restart Interrupt Level bit 0 position. */ -#define TC4_TRGINTLVL1_bm (1<<5) /* Timer Trigger Restart Interrupt Level bit 1 mask. */ -#define TC4_TRGINTLVL1_bp 5 /* Timer Trigger Restart Interrupt Level bit 1 position. */ - -#define TC4_ERRINTLVL_gm 0x0C /* Timer Error Interrupt Level group mask. */ -#define TC4_ERRINTLVL_gp 2 /* Timer Error Interrupt Level group position. */ -#define TC4_ERRINTLVL0_bm (1<<2) /* Timer Error Interrupt Level bit 0 mask. */ -#define TC4_ERRINTLVL0_bp 2 /* Timer Error Interrupt Level bit 0 position. */ -#define TC4_ERRINTLVL1_bm (1<<3) /* Timer Error Interrupt Level bit 1 mask. */ -#define TC4_ERRINTLVL1_bp 3 /* Timer Error Interrupt Level bit 1 position. */ - -#define TC4_OVFINTLVL_gm 0x03 /* Timer Overflow/Underflow Interrupt Level group mask. */ -#define TC4_OVFINTLVL_gp 0 /* Timer Overflow/Underflow Interrupt Level group position. */ -#define TC4_OVFINTLVL0_bm (1<<0) /* Timer Overflow/Underflow Interrupt Level bit 0 mask. */ -#define TC4_OVFINTLVL0_bp 0 /* Timer Overflow/Underflow Interrupt Level bit 0 position. */ -#define TC4_OVFINTLVL1_bm (1<<1) /* Timer Overflow/Underflow Interrupt Level bit 1 mask. */ -#define TC4_OVFINTLVL1_bp 1 /* Timer Overflow/Underflow Interrupt Level bit 1 position. */ - -/* TC4.INTCTRLB bit masks and bit positions */ -#define TC4_CCDINTLVL_gm 0xC0 /* Channel D Compare or Capture Interrupt Level group mask. */ -#define TC4_CCDINTLVL_gp 6 /* Channel D Compare or Capture Interrupt Level group position. */ -#define TC4_CCDINTLVL0_bm (1<<6) /* Channel D Compare or Capture Interrupt Level bit 0 mask. */ -#define TC4_CCDINTLVL0_bp 6 /* Channel D Compare or Capture Interrupt Level bit 0 position. */ -#define TC4_CCDINTLVL1_bm (1<<7) /* Channel D Compare or Capture Interrupt Level bit 1 mask. */ -#define TC4_CCDINTLVL1_bp 7 /* Channel D Compare or Capture Interrupt Level bit 1 position. */ - -#define TC4_CCCINTLVL_gm 0x30 /* Channel C Compare or Capture Interrupt Level group mask. */ -#define TC4_CCCINTLVL_gp 4 /* Channel C Compare or Capture Interrupt Level group position. */ -#define TC4_CCCINTLVL0_bm (1<<4) /* Channel C Compare or Capture Interrupt Level bit 0 mask. */ -#define TC4_CCCINTLVL0_bp 4 /* Channel C Compare or Capture Interrupt Level bit 0 position. */ -#define TC4_CCCINTLVL1_bm (1<<5) /* Channel C Compare or Capture Interrupt Level bit 1 mask. */ -#define TC4_CCCINTLVL1_bp 5 /* Channel C Compare or Capture Interrupt Level bit 1 position. */ - -#define TC4_CCBINTLVL_gm 0x0C /* Channel B Compare or Capture Interrupt Level group mask. */ -#define TC4_CCBINTLVL_gp 2 /* Channel B Compare or Capture Interrupt Level group position. */ -#define TC4_CCBINTLVL0_bm (1<<2) /* Channel B Compare or Capture Interrupt Level bit 0 mask. */ -#define TC4_CCBINTLVL0_bp 2 /* Channel B Compare or Capture Interrupt Level bit 0 position. */ -#define TC4_CCBINTLVL1_bm (1<<3) /* Channel B Compare or Capture Interrupt Level bit 1 mask. */ -#define TC4_CCBINTLVL1_bp 3 /* Channel B Compare or Capture Interrupt Level bit 1 position. */ - -#define TC4_CCAINTLVL_gm 0x03 /* Channel A Compare or Capture Interrupt Level group mask. */ -#define TC4_CCAINTLVL_gp 0 /* Channel A Compare or Capture Interrupt Level group position. */ -#define TC4_CCAINTLVL0_bm (1<<0) /* Channel A Compare or Capture Interrupt Level bit 0 mask. */ -#define TC4_CCAINTLVL0_bp 0 /* Channel A Compare or Capture Interrupt Level bit 0 position. */ -#define TC4_CCAINTLVL1_bm (1<<1) /* Channel A Compare or Capture Interrupt Level bit 1 mask. */ -#define TC4_CCAINTLVL1_bp 1 /* Channel A Compare or Capture Interrupt Level bit 1 position. */ - -#define TC4_LCCDINTLVL_gm 0xC0 /* Channel Low D Compare or Capture Interrupt Level group mask. */ -#define TC4_LCCDINTLVL_gp 6 /* Channel Low D Compare or Capture Interrupt Level group position. */ -#define TC4_LCCDINTLVL0_bm (1<<6) /* Channel Low D Compare or Capture Interrupt Level bit 0 mask. */ -#define TC4_LCCDINTLVL0_bp 6 /* Channel Low D Compare or Capture Interrupt Level bit 0 position. */ -#define TC4_LCCDINTLVL1_bm (1<<7) /* Channel Low D Compare or Capture Interrupt Level bit 1 mask. */ -#define TC4_LCCDINTLVL1_bp 7 /* Channel Low D Compare or Capture Interrupt Level bit 1 position. */ - -#define TC4_LCCCINTLVL_gm 0x30 /* Channel Low C Compare or Capture Interrupt Level group mask. */ -#define TC4_LCCCINTLVL_gp 4 /* Channel Low C Compare or Capture Interrupt Level group position. */ -#define TC4_LCCCINTLVL0_bm (1<<4) /* Channel Low C Compare or Capture Interrupt Level bit 0 mask. */ -#define TC4_LCCCINTLVL0_bp 4 /* Channel Low C Compare or Capture Interrupt Level bit 0 position. */ -#define TC4_LCCCINTLVL1_bm (1<<5) /* Channel Low C Compare or Capture Interrupt Level bit 1 mask. */ -#define TC4_LCCCINTLVL1_bp 5 /* Channel Low C Compare or Capture Interrupt Level bit 1 position. */ - -#define TC4_LCCBINTLVL_gm 0x0C /* Channel Low B Compare or Capture Interrupt Level group mask. */ -#define TC4_LCCBINTLVL_gp 2 /* Channel Low B Compare or Capture Interrupt Level group position. */ -#define TC4_LCCBINTLVL0_bm (1<<2) /* Channel Low B Compare or Capture Interrupt Level bit 0 mask. */ -#define TC4_LCCBINTLVL0_bp 2 /* Channel Low B Compare or Capture Interrupt Level bit 0 position. */ -#define TC4_LCCBINTLVL1_bm (1<<3) /* Channel Low B Compare or Capture Interrupt Level bit 1 mask. */ -#define TC4_LCCBINTLVL1_bp 3 /* Channel Low B Compare or Capture Interrupt Level bit 1 position. */ - -#define TC4_LCCAINTLVL_gm 0x03 /* Channel Low A Compare or Capture Interrupt Level group mask. */ -#define TC4_LCCAINTLVL_gp 0 /* Channel Low A Compare or Capture Interrupt Level group position. */ -#define TC4_LCCAINTLVL0_bm (1<<0) /* Channel Low A Compare or Capture Interrupt Level bit 0 mask. */ -#define TC4_LCCAINTLVL0_bp 0 /* Channel Low A Compare or Capture Interrupt Level bit 0 position. */ -#define TC4_LCCAINTLVL1_bm (1<<1) /* Channel Low A Compare or Capture Interrupt Level bit 1 mask. */ -#define TC4_LCCAINTLVL1_bp 1 /* Channel Low A Compare or Capture Interrupt Level bit 1 position. */ - -/* TC4.CTRLGCLR bit masks and bit positions */ -#define TC4_STOP_bm 0x20 /* Timer/Counter Stop bit mask. */ -#define TC4_STOP_bp 5 /* Timer/Counter Stop bit position. */ - -#define TC4_CMD_gm 0x0C /* Command group mask. */ -#define TC4_CMD_gp 2 /* Command group position. */ -#define TC4_CMD0_bm (1<<2) /* Command bit 0 mask. */ -#define TC4_CMD0_bp 2 /* Command bit 0 position. */ -#define TC4_CMD1_bm (1<<3) /* Command bit 1 mask. */ -#define TC4_CMD1_bp 3 /* Command bit 1 position. */ - -#define TC4_LUPD_bm 0x02 /* Lock Update bit mask. */ -#define TC4_LUPD_bp 1 /* Lock Update bit position. */ - -#define TC4_DIR_bm 0x01 /* Counter Direction bit mask. */ -#define TC4_DIR_bp 0 /* Counter Direction bit position. */ - -/* TC4.CTRLGSET bit masks and bit positions */ -/* TC4_STOP Predefined. */ -/* TC4_STOP Predefined. */ - -/* TC4_CMD Predefined. */ -/* TC4_CMD Predefined. */ - -/* TC4_LUPD Predefined. */ -/* TC4_LUPD Predefined. */ - -/* TC4_DIR Predefined. */ -/* TC4_DIR Predefined. */ - -/* TC4.CTRLHCLR bit masks and bit positions */ -#define TC4_CCDBV_bm 0x10 /* Channel D Compare or Capture Buffer Valid bit mask. */ -#define TC4_CCDBV_bp 4 /* Channel D Compare or Capture Buffer Valid bit position. */ - -#define TC4_CCCBV_bm 0x08 /* Channel C Compare or Capture Buffer Valid bit mask. */ -#define TC4_CCCBV_bp 3 /* Channel C Compare or Capture Buffer Valid bit position. */ - -#define TC4_CCBBV_bm 0x04 /* Channel B Compare or Capture Buffer Valid bit mask. */ -#define TC4_CCBBV_bp 2 /* Channel B Compare or Capture Buffer Valid bit position. */ - -#define TC4_CCABV_bm 0x02 /* Channel A Compare or Capture Buffer Valid bit mask. */ -#define TC4_CCABV_bp 1 /* Channel A Compare or Capture Buffer Valid bit position. */ - -#define TC4_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ -#define TC4_PERBV_bp 0 /* Period Buffer Valid bit position. */ - -#define TC4_LCCDBV_bm 0x10 /* Channel Low D Compare or Capture Buffer Valid bit mask. */ -#define TC4_LCCDBV_bp 4 /* Channel Low D Compare or Capture Buffer Valid bit position. */ - -#define TC4_LCCCBV_bm 0x08 /* Channel Low C Compare or Capture Buffer Valid bit mask. */ -#define TC4_LCCCBV_bp 3 /* Channel Low C Compare or Capture Buffer Valid bit position. */ - -#define TC4_LCCBBV_bm 0x04 /* Channel Low B Compare or Capture Buffer Valid bit mask. */ -#define TC4_LCCBBV_bp 2 /* Channel Low B Compare or Capture Buffer Valid bit position. */ - -#define TC4_LCCABV_bm 0x02 /* Channel Low A Compare or Capture Buffer Valid bit mask. */ -#define TC4_LCCABV_bp 1 /* Channel Low A Compare or Capture Buffer Valid bit position. */ - -#define TC4_LPERBV_bm 0x01 /* Period Low Buffer Valid bit mask. */ -#define TC4_LPERBV_bp 0 /* Period Low Buffer Valid bit position. */ - -/* TC4.CTRLHSET bit masks and bit positions */ -/* TC4_CCDBV Predefined. */ -/* TC4_CCDBV Predefined. */ - -/* TC4_CCCBV Predefined. */ -/* TC4_CCCBV Predefined. */ - -/* TC4_CCBBV Predefined. */ -/* TC4_CCBBV Predefined. */ - -/* TC4_CCABV Predefined. */ -/* TC4_CCABV Predefined. */ - -/* TC4_PERBV Predefined. */ -/* TC4_PERBV Predefined. */ - -/* TC4_LCCDBV Predefined. */ -/* TC4_LCCDBV Predefined. */ - -/* TC4_LCCCBV Predefined. */ -/* TC4_LCCCBV Predefined. */ - -/* TC4_LCCBBV Predefined. */ -/* TC4_LCCBBV Predefined. */ - -/* TC4_LCCABV Predefined. */ -/* TC4_LCCABV Predefined. */ - -/* TC4_LPERBV Predefined. */ -/* TC4_LPERBV Predefined. */ - -/* TC4.INTFLAGS bit masks and bit positions */ -#define TC4_CCDIF_bm 0x80 /* Channel D Compare or Capture Interrupt Flag bit mask. */ -#define TC4_CCDIF_bp 7 /* Channel D Compare or Capture Interrupt Flag bit position. */ - -#define TC4_CCCIF_bm 0x40 /* Channel C Compare or Capture Interrupt Flag bit mask. */ -#define TC4_CCCIF_bp 6 /* Channel C Compare or Capture Interrupt Flag bit position. */ - -#define TC4_CCBIF_bm 0x20 /* Channel B Compare or Capture Interrupt Flag bit mask. */ -#define TC4_CCBIF_bp 5 /* Channel B Compare or Capture Interrupt Flag bit position. */ - -#define TC4_CCAIF_bm 0x10 /* Channel A Compare or Capture Interrupt Flag bit mask. */ -#define TC4_CCAIF_bp 4 /* Channel A Compare or Capture Interrupt Flag bit position. */ - -#define TC4_TRGIF_bm 0x04 /* Trigger Restart Interrupt Flag bit mask. */ -#define TC4_TRGIF_bp 2 /* Trigger Restart Interrupt Flag bit position. */ - -#define TC4_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ -#define TC4_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ - -#define TC4_OVFIF_bm 0x01 /* Overflow/Underflow Interrupt Flag bit mask. */ -#define TC4_OVFIF_bp 0 /* Overflow/Underflow Interrupt Flag bit position. */ - -#define TC4_LCCDIF_bm 0x80 /* Channel Low D Compare or Capture Interrupt Flag bit mask. */ -#define TC4_LCCDIF_bp 7 /* Channel Low D Compare or Capture Interrupt Flag bit position. */ - -#define TC4_LCCCIF_bm 0x40 /* Channel Low C Compare or Capture Interrupt Flag bit mask. */ -#define TC4_LCCCIF_bp 6 /* Channel Low C Compare or Capture Interrupt Flag bit position. */ - -#define TC4_LCCBIF_bm 0x20 /* Channel Low B Compare or Capture Interrupt Flag bit mask. */ -#define TC4_LCCBIF_bp 5 /* Channel Low B Compare or Capture Interrupt Flag bit position. */ - -#define TC4_LCCAIF_bm 0x10 /* Channel Low A Compare or Capture Interrupt Flag bit mask. */ -#define TC4_LCCAIF_bp 4 /* Channel Low A Compare or Capture Interrupt Flag bit position. */ - -/* TC5.CTRLA bit masks and bit positions */ -#define TC5_SYNCHEN_bm 0x40 /* Synchronization Enabled bit mask. */ -#define TC5_SYNCHEN_bp 6 /* Synchronization Enabled bit position. */ - -#define TC5_EVSTART_bm 0x20 /* Start on Next Event bit mask. */ -#define TC5_EVSTART_bp 5 /* Start on Next Event bit position. */ - -#define TC5_UPSTOP_bm 0x10 /* Stop on Next Update bit mask. */ -#define TC5_UPSTOP_bp 4 /* Stop on Next Update bit position. */ - -#define TC5_CLKSEL_gm 0x0F /* Clock Select group mask. */ -#define TC5_CLKSEL_gp 0 /* Clock Select group position. */ -#define TC5_CLKSEL0_bm (1<<0) /* Clock Select bit 0 mask. */ -#define TC5_CLKSEL0_bp 0 /* Clock Select bit 0 position. */ -#define TC5_CLKSEL1_bm (1<<1) /* Clock Select bit 1 mask. */ -#define TC5_CLKSEL1_bp 1 /* Clock Select bit 1 position. */ -#define TC5_CLKSEL2_bm (1<<2) /* Clock Select bit 2 mask. */ -#define TC5_CLKSEL2_bp 2 /* Clock Select bit 2 position. */ -#define TC5_CLKSEL3_bm (1<<3) /* Clock Select bit 3 mask. */ -#define TC5_CLKSEL3_bp 3 /* Clock Select bit 3 position. */ - -/* TC5.CTRLB bit masks and bit positions */ -#define TC5_BYTEM_gm 0xC0 /* Byte Mode group mask. */ -#define TC5_BYTEM_gp 6 /* Byte Mode group position. */ -#define TC5_BYTEM0_bm (1<<6) /* Byte Mode bit 0 mask. */ -#define TC5_BYTEM0_bp 6 /* Byte Mode bit 0 position. */ -#define TC5_BYTEM1_bm (1<<7) /* Byte Mode bit 1 mask. */ -#define TC5_BYTEM1_bp 7 /* Byte Mode bit 1 position. */ - -#define TC5_CIRCEN_gm 0x30 /* Circular Buffer Enable group mask. */ -#define TC5_CIRCEN_gp 4 /* Circular Buffer Enable group position. */ -#define TC5_CIRCEN0_bm (1<<4) /* Circular Buffer Enable bit 0 mask. */ -#define TC5_CIRCEN0_bp 4 /* Circular Buffer Enable bit 0 position. */ -#define TC5_CIRCEN1_bm (1<<5) /* Circular Buffer Enable bit 1 mask. */ -#define TC5_CIRCEN1_bp 5 /* Circular Buffer Enable bit 1 position. */ - -#define TC5_WGMODE_gm 0x07 /* Waveform Generation Mode group mask. */ -#define TC5_WGMODE_gp 0 /* Waveform Generation Mode group position. */ -#define TC5_WGMODE0_bm (1<<0) /* Waveform Generation Mode bit 0 mask. */ -#define TC5_WGMODE0_bp 0 /* Waveform Generation Mode bit 0 position. */ -#define TC5_WGMODE1_bm (1<<1) /* Waveform Generation Mode bit 1 mask. */ -#define TC5_WGMODE1_bp 1 /* Waveform Generation Mode bit 1 position. */ -#define TC5_WGMODE2_bm (1<<2) /* Waveform Generation Mode bit 2 mask. */ -#define TC5_WGMODE2_bp 2 /* Waveform Generation Mode bit 2 position. */ - -/* TC5.CTRLC bit masks and bit positions */ -#define TC5_POLB_bm 0x20 /* Channel B Output Polarity bit mask. */ -#define TC5_POLB_bp 5 /* Channel B Output Polarity bit position. */ - -#define TC5_POLA_bm 0x10 /* Channel A Output Polarity bit mask. */ -#define TC5_POLA_bp 4 /* Channel A Output Polarity bit position. */ - -#define TC5_CMPB_bm 0x02 /* Channel B Compare Output Value bit mask. */ -#define TC5_CMPB_bp 1 /* Channel B Compare Output Value bit position. */ - -#define TC5_CMPA_bm 0x01 /* Channel A Compare Output Value bit mask. */ -#define TC5_CMPA_bp 0 /* Channel A Compare Output Value bit position. */ - -#define TC5_HCMPB_bm 0x20 /* High Channel B Compare Output Value bit mask. */ -#define TC5_HCMPB_bp 5 /* High Channel B Compare Output Value bit position. */ - -#define TC5_HCMPA_bm 0x10 /* High Channel A Compare Output Value bit mask. */ -#define TC5_HCMPA_bp 4 /* High Channel A Compare Output Value bit position. */ - -#define TC5_LCMPB_bm 0x02 /* Low Channel B Compare Output Value bit mask. */ -#define TC5_LCMPB_bp 1 /* Low Channel B Compare Output Value bit position. */ - -#define TC5_LCMPA_bm 0x01 /* Low Channel A Compare Output Value bit mask. */ -#define TC5_LCMPA_bp 0 /* Low Channel A Compare Output Value bit position. */ - -/* TC5.CTRLD bit masks and bit positions */ -#define TC5_EVACT_gm 0xE0 /* Event Action group mask. */ -#define TC5_EVACT_gp 5 /* Event Action group position. */ -#define TC5_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ -#define TC5_EVACT0_bp 5 /* Event Action bit 0 position. */ -#define TC5_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ -#define TC5_EVACT1_bp 6 /* Event Action bit 1 position. */ -#define TC5_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ -#define TC5_EVACT2_bp 7 /* Event Action bit 2 position. */ - -#define TC5_EVDLY_bm 0x10 /* Event Delay bit mask. */ -#define TC5_EVDLY_bp 4 /* Event Delay bit position. */ - -#define TC5_EVSEL_gm 0x0F /* Event Source Select group mask. */ -#define TC5_EVSEL_gp 0 /* Event Source Select group position. */ -#define TC5_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ -#define TC5_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ -#define TC5_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ -#define TC5_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ -#define TC5_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ -#define TC5_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ -#define TC5_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ -#define TC5_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ - -/* TC5.CTRLE bit masks and bit positions */ -#define TC5_CCBMODE_gm 0x0C /* Channel B Compare or Capture Mode group mask. */ -#define TC5_CCBMODE_gp 2 /* Channel B Compare or Capture Mode group position. */ -#define TC5_CCBMODE0_bm (1<<2) /* Channel B Compare or Capture Mode bit 0 mask. */ -#define TC5_CCBMODE0_bp 2 /* Channel B Compare or Capture Mode bit 0 position. */ -#define TC5_CCBMODE1_bm (1<<3) /* Channel B Compare or Capture Mode bit 1 mask. */ -#define TC5_CCBMODE1_bp 3 /* Channel B Compare or Capture Mode bit 1 position. */ - -#define TC5_CCAMODE_gm 0x03 /* Channel A Compare or Capture Mode group mask. */ -#define TC5_CCAMODE_gp 0 /* Channel A Compare or Capture Mode group position. */ -#define TC5_CCAMODE0_bm (1<<0) /* Channel A Compare or Capture Mode bit 0 mask. */ -#define TC5_CCAMODE0_bp 0 /* Channel A Compare or Capture Mode bit 0 position. */ -#define TC5_CCAMODE1_bm (1<<1) /* Channel A Compare or Capture Mode bit 1 mask. */ -#define TC5_CCAMODE1_bp 1 /* Channel A Compare or Capture Mode bit 1 position. */ - -#define TC5_LCCBMODE_gm 0x0C /* Channel Low B Compare or Capture Mode group mask. */ -#define TC5_LCCBMODE_gp 2 /* Channel Low B Compare or Capture Mode group position. */ -#define TC5_LCCBMODE0_bm (1<<2) /* Channel Low B Compare or Capture Mode bit 0 mask. */ -#define TC5_LCCBMODE0_bp 2 /* Channel Low B Compare or Capture Mode bit 0 position. */ -#define TC5_LCCBMODE1_bm (1<<3) /* Channel Low B Compare or Capture Mode bit 1 mask. */ -#define TC5_LCCBMODE1_bp 3 /* Channel Low B Compare or Capture Mode bit 1 position. */ - -#define TC5_LCCAMODE_gm 0x03 /* Channel Low A Compare or Capture Mode group mask. */ -#define TC5_LCCAMODE_gp 0 /* Channel Low A Compare or Capture Mode group position. */ -#define TC5_LCCAMODE0_bm (1<<0) /* Channel Low A Compare or Capture Mode bit 0 mask. */ -#define TC5_LCCAMODE0_bp 0 /* Channel Low A Compare or Capture Mode bit 0 position. */ -#define TC5_LCCAMODE1_bm (1<<1) /* Channel Low A Compare or Capture Mode bit 1 mask. */ -#define TC5_LCCAMODE1_bp 1 /* Channel Low A Compare or Capture Mode bit 1 position. */ - -/* TC5.CTRLF bit masks and bit positions */ -#define TC5_HCCBMODE_gm 0x0C /* Channel High B Compare or Capture Mode group mask. */ -#define TC5_HCCBMODE_gp 2 /* Channel High B Compare or Capture Mode group position. */ -#define TC5_HCCBMODE0_bm (1<<2) /* Channel High B Compare or Capture Mode bit 0 mask. */ -#define TC5_HCCBMODE0_bp 2 /* Channel High B Compare or Capture Mode bit 0 position. */ -#define TC5_HCCBMODE1_bm (1<<3) /* Channel High B Compare or Capture Mode bit 1 mask. */ -#define TC5_HCCBMODE1_bp 3 /* Channel High B Compare or Capture Mode bit 1 position. */ - -#define TC5_HCCAMODE_gm 0x03 /* Channel High A Compare or Capture Mode group mask. */ -#define TC5_HCCAMODE_gp 0 /* Channel High A Compare or Capture Mode group position. */ -#define TC5_HCCAMODE0_bm (1<<0) /* Channel High A Compare or Capture Mode bit 0 mask. */ -#define TC5_HCCAMODE0_bp 0 /* Channel High A Compare or Capture Mode bit 0 position. */ -#define TC5_HCCAMODE1_bm (1<<1) /* Channel High A Compare or Capture Mode bit 1 mask. */ -#define TC5_HCCAMODE1_bp 1 /* Channel High A Compare or Capture Mode bit 1 position. */ - -/* TC5.INTCTRLA bit masks and bit positions */ -#define TC5_TRGINTLVL_gm 0x30 /* Timer Trigger Restart Interrupt Level group mask. */ -#define TC5_TRGINTLVL_gp 4 /* Timer Trigger Restart Interrupt Level group position. */ -#define TC5_TRGINTLVL0_bm (1<<4) /* Timer Trigger Restart Interrupt Level bit 0 mask. */ -#define TC5_TRGINTLVL0_bp 4 /* Timer Trigger Restart Interrupt Level bit 0 position. */ -#define TC5_TRGINTLVL1_bm (1<<5) /* Timer Trigger Restart Interrupt Level bit 1 mask. */ -#define TC5_TRGINTLVL1_bp 5 /* Timer Trigger Restart Interrupt Level bit 1 position. */ - -#define TC5_ERRINTLVL_gm 0x0C /* Timer Error Interrupt Level group mask. */ -#define TC5_ERRINTLVL_gp 2 /* Timer Error Interrupt Level group position. */ -#define TC5_ERRINTLVL0_bm (1<<2) /* Timer Error Interrupt Level bit 0 mask. */ -#define TC5_ERRINTLVL0_bp 2 /* Timer Error Interrupt Level bit 0 position. */ -#define TC5_ERRINTLVL1_bm (1<<3) /* Timer Error Interrupt Level bit 1 mask. */ -#define TC5_ERRINTLVL1_bp 3 /* Timer Error Interrupt Level bit 1 position. */ - -#define TC5_OVFINTLVL_gm 0x03 /* Timer Overflow/Underflow Interrupt Level group mask. */ -#define TC5_OVFINTLVL_gp 0 /* Timer Overflow/Underflow Interrupt Level group position. */ -#define TC5_OVFINTLVL0_bm (1<<0) /* Timer Overflow/Underflow Interrupt Level bit 0 mask. */ -#define TC5_OVFINTLVL0_bp 0 /* Timer Overflow/Underflow Interrupt Level bit 0 position. */ -#define TC5_OVFINTLVL1_bm (1<<1) /* Timer Overflow/Underflow Interrupt Level bit 1 mask. */ -#define TC5_OVFINTLVL1_bp 1 /* Timer Overflow/Underflow Interrupt Level bit 1 position. */ - -/* TC5.INTCTRLB bit masks and bit positions */ -#define TC5_CCBINTLVL_gm 0x0C /* Channel B Compare or Capture Interrupt Level group mask. */ -#define TC5_CCBINTLVL_gp 2 /* Channel B Compare or Capture Interrupt Level group position. */ -#define TC5_CCBINTLVL0_bm (1<<2) /* Channel B Compare or Capture Interrupt Level bit 0 mask. */ -#define TC5_CCBINTLVL0_bp 2 /* Channel B Compare or Capture Interrupt Level bit 0 position. */ -#define TC5_CCBINTLVL1_bm (1<<3) /* Channel B Compare or Capture Interrupt Level bit 1 mask. */ -#define TC5_CCBINTLVL1_bp 3 /* Channel B Compare or Capture Interrupt Level bit 1 position. */ - -#define TC5_CCAINTLVL_gm 0x03 /* Channel A Compare or Capture Interrupt Level group mask. */ -#define TC5_CCAINTLVL_gp 0 /* Channel A Compare or Capture Interrupt Level group position. */ -#define TC5_CCAINTLVL0_bm (1<<0) /* Channel A Compare or Capture Interrupt Level bit 0 mask. */ -#define TC5_CCAINTLVL0_bp 0 /* Channel A Compare or Capture Interrupt Level bit 0 position. */ -#define TC5_CCAINTLVL1_bm (1<<1) /* Channel A Compare or Capture Interrupt Level bit 1 mask. */ -#define TC5_CCAINTLVL1_bp 1 /* Channel A Compare or Capture Interrupt Level bit 1 position. */ - -#define TC5_LCCBINTLVL_gm 0x0C /* Channel Low B Compare or Capture Interrupt Level group mask. */ -#define TC5_LCCBINTLVL_gp 2 /* Channel Low B Compare or Capture Interrupt Level group position. */ -#define TC5_LCCBINTLVL0_bm (1<<2) /* Channel Low B Compare or Capture Interrupt Level bit 0 mask. */ -#define TC5_LCCBINTLVL0_bp 2 /* Channel Low B Compare or Capture Interrupt Level bit 0 position. */ -#define TC5_LCCBINTLVL1_bm (1<<3) /* Channel Low B Compare or Capture Interrupt Level bit 1 mask. */ -#define TC5_LCCBINTLVL1_bp 3 /* Channel Low B Compare or Capture Interrupt Level bit 1 position. */ - -#define TC5_LCCAINTLVL_gm 0x03 /* Channel Low A Compare or Capture Interrupt Level group mask. */ -#define TC5_LCCAINTLVL_gp 0 /* Channel Low A Compare or Capture Interrupt Level group position. */ -#define TC5_LCCAINTLVL0_bm (1<<0) /* Channel Low A Compare or Capture Interrupt Level bit 0 mask. */ -#define TC5_LCCAINTLVL0_bp 0 /* Channel Low A Compare or Capture Interrupt Level bit 0 position. */ -#define TC5_LCCAINTLVL1_bm (1<<1) /* Channel Low A Compare or Capture Interrupt Level bit 1 mask. */ -#define TC5_LCCAINTLVL1_bp 1 /* Channel Low A Compare or Capture Interrupt Level bit 1 position. */ - -/* TC5.CTRLGCLR bit masks and bit positions */ -#define TC5_STOP_bm 0x20 /* Timer/Counter Stop bit mask. */ -#define TC5_STOP_bp 5 /* Timer/Counter Stop bit position. */ - -#define TC5_CMD_gm 0x0C /* Command group mask. */ -#define TC5_CMD_gp 2 /* Command group position. */ -#define TC5_CMD0_bm (1<<2) /* Command bit 0 mask. */ -#define TC5_CMD0_bp 2 /* Command bit 0 position. */ -#define TC5_CMD1_bm (1<<3) /* Command bit 1 mask. */ -#define TC5_CMD1_bp 3 /* Command bit 1 position. */ - -#define TC5_LUPD_bm 0x02 /* Lock Update bit mask. */ -#define TC5_LUPD_bp 1 /* Lock Update bit position. */ - -#define TC5_DIR_bm 0x01 /* Counter Direction bit mask. */ -#define TC5_DIR_bp 0 /* Counter Direction bit position. */ - -/* TC5.CTRLGSET bit masks and bit positions */ -/* TC5_STOP Predefined. */ -/* TC5_STOP Predefined. */ - -/* TC5_CMD Predefined. */ -/* TC5_CMD Predefined. */ - -/* TC5_LUPD Predefined. */ -/* TC5_LUPD Predefined. */ - -/* TC5_DIR Predefined. */ -/* TC5_DIR Predefined. */ - -/* TC5.CTRLHCLR bit masks and bit positions */ -#define TC5_CCBBV_bm 0x04 /* Channel B Compare or Capture Buffer Valid bit mask. */ -#define TC5_CCBBV_bp 2 /* Channel B Compare or Capture Buffer Valid bit position. */ - -#define TC5_CCABV_bm 0x02 /* Channel A Compare or Capture Buffer Valid bit mask. */ -#define TC5_CCABV_bp 1 /* Channel A Compare or Capture Buffer Valid bit position. */ - -#define TC5_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ -#define TC5_PERBV_bp 0 /* Period Buffer Valid bit position. */ - -#define TC5_LCCBBV_bm 0x04 /* Channel Low B Compare or Capture Buffer Valid bit mask. */ -#define TC5_LCCBBV_bp 2 /* Channel Low B Compare or Capture Buffer Valid bit position. */ - -#define TC5_LCCABV_bm 0x02 /* Channel Low A Compare or Capture Buffer Valid bit mask. */ -#define TC5_LCCABV_bp 1 /* Channel Low A Compare or Capture Buffer Valid bit position. */ - -#define TC5_LPERBV_bm 0x01 /* Period Low Buffer Valid bit mask. */ -#define TC5_LPERBV_bp 0 /* Period Low Buffer Valid bit position. */ - -/* TC5.CTRLHSET bit masks and bit positions */ -/* TC5_CCBBV Predefined. */ -/* TC5_CCBBV Predefined. */ - -/* TC5_CCABV Predefined. */ -/* TC5_CCABV Predefined. */ - -/* TC5_PERBV Predefined. */ -/* TC5_PERBV Predefined. */ - -/* TC5_LCCBBV Predefined. */ -/* TC5_LCCBBV Predefined. */ - -/* TC5_LCCABV Predefined. */ -/* TC5_LCCABV Predefined. */ - -/* TC5_LPERBV Predefined. */ -/* TC5_LPERBV Predefined. */ - -/* TC5.INTFLAGS bit masks and bit positions */ -#define TC5_CCBIF_bm 0x20 /* Channel B Compare or Capture Interrupt Flag bit mask. */ -#define TC5_CCBIF_bp 5 /* Channel B Compare or Capture Interrupt Flag bit position. */ - -#define TC5_CCAIF_bm 0x10 /* Channel A Compare or Capture Interrupt Flag bit mask. */ -#define TC5_CCAIF_bp 4 /* Channel A Compare or Capture Interrupt Flag bit position. */ - -#define TC5_TRGIF_bm 0x04 /* Trigger Restart Interrupt Flag bit mask. */ -#define TC5_TRGIF_bp 2 /* Trigger Restart Interrupt Flag bit position. */ - -#define TC5_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ -#define TC5_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ - -#define TC5_OVFIF_bm 0x01 /* Overflow/Underflow Interrupt Flag bit mask. */ -#define TC5_OVFIF_bp 0 /* Overflow/Underflow Interrupt Flag bit position. */ - -#define TC5_LCCBIF_bm 0x20 /* Channel Low B Compare or Capture Interrupt Flag bit mask. */ -#define TC5_LCCBIF_bp 5 /* Channel Low B Compare or Capture Interrupt Flag bit position. */ - -#define TC5_LCCAIF_bm 0x10 /* Channel Low A Compare or Capture Interrupt Flag bit mask. */ -#define TC5_LCCAIF_bp 4 /* Channel Low A Compare or Capture Interrupt Flag bit position. */ - -/* FAULT - Fault Extension */ -/* FAULT.CTRLA bit masks and bit positions */ -#define FAULT_RAMP_gm 0xC0 /* Ramp Mode Selection group mask. */ -#define FAULT_RAMP_gp 6 /* Ramp Mode Selection group position. */ -#define FAULT_RAMP0_bm (1<<6) /* Ramp Mode Selection bit 0 mask. */ -#define FAULT_RAMP0_bp 6 /* Ramp Mode Selection bit 0 position. */ -#define FAULT_RAMP1_bm (1<<7) /* Ramp Mode Selection bit 1 mask. */ -#define FAULT_RAMP1_bp 7 /* Ramp Mode Selection bit 1 position. */ - -#define FAULT_FDDBD_bm 0x20 /* Fault on Debug Break Detection bit mask. */ -#define FAULT_FDDBD_bp 5 /* Fault on Debug Break Detection bit position. */ - -#define FAULT_PORTCTRL_bm 0x10 /* Port Control Mode bit mask. */ -#define FAULT_PORTCTRL_bp 4 /* Port Control Mode bit position. */ - -#define FAULT_FUSE_bm 0x08 /* Fuse State bit mask. */ -#define FAULT_FUSE_bp 3 /* Fuse State bit position. */ - -#define FAULT_FILTERE_bm 0x04 /* Fault E Digital Filter Selection bit mask. */ -#define FAULT_FILTERE_bp 2 /* Fault E Digital Filter Selection bit position. */ - -#define FAULT_SRCE_gm 0x03 /* Fault E Input selection group mask. */ -#define FAULT_SRCE_gp 0 /* Fault E Input selection group position. */ -#define FAULT_SRCE0_bm (1<<0) /* Fault E Input selection bit 0 mask. */ -#define FAULT_SRCE0_bp 0 /* Fault E Input selection bit 0 position. */ -#define FAULT_SRCE1_bm (1<<1) /* Fault E Input selection bit 1 mask. */ -#define FAULT_SRCE1_bp 1 /* Fault E Input selection bit 1 position. */ - -/* FAULT.CTRLB bit masks and bit positions */ -#define FAULT_SOFTA_bm 0x80 /* Fault A Software Mode bit mask. */ -#define FAULT_SOFTA_bp 7 /* Fault A Software Mode bit position. */ - -#define FAULT_HALTA_gm 0x60 /* Fault A Halt Action group mask. */ -#define FAULT_HALTA_gp 5 /* Fault A Halt Action group position. */ -#define FAULT_HALTA0_bm (1<<5) /* Fault A Halt Action bit 0 mask. */ -#define FAULT_HALTA0_bp 5 /* Fault A Halt Action bit 0 position. */ -#define FAULT_HALTA1_bm (1<<6) /* Fault A Halt Action bit 1 mask. */ -#define FAULT_HALTA1_bp 6 /* Fault A Halt Action bit 1 position. */ - -#define FAULT_RESTARTA_bm 0x10 /* Fault A Restart Action bit mask. */ -#define FAULT_RESTARTA_bp 4 /* Fault A Restart Action bit position. */ - -#define FAULT_KEEPA_bm 0x08 /* Fault A Keep Action bit mask. */ -#define FAULT_KEEPA_bp 3 /* Fault A Keep Action bit position. */ - -#define FAULT_SRCA_gm 0x03 /* Fault A Source Selection group mask. */ -#define FAULT_SRCA_gp 0 /* Fault A Source Selection group position. */ -#define FAULT_SRCA0_bm (1<<0) /* Fault A Source Selection bit 0 mask. */ -#define FAULT_SRCA0_bp 0 /* Fault A Source Selection bit 0 position. */ -#define FAULT_SRCA1_bm (1<<1) /* Fault A Source Selection bit 1 mask. */ -#define FAULT_SRCA1_bp 1 /* Fault A Source Selection bit 1 position. */ - -/* FAULT.CTRLC bit masks and bit positions */ -#define FAULT_CAPTA_bm 0x20 /* Fault A Capture bit mask. */ -#define FAULT_CAPTA_bp 5 /* Fault A Capture bit position. */ - -#define FAULT_FILTERA_bm 0x04 /* Fault A Digital Filter Selection bit mask. */ -#define FAULT_FILTERA_bp 2 /* Fault A Digital Filter Selection bit position. */ - -#define FAULT_BLANKA_bm 0x02 /* Fault A Blanking bit mask. */ -#define FAULT_BLANKA_bp 1 /* Fault A Blanking bit position. */ - -#define FAULT_QUALA_bm 0x01 /* Fault A Qualification bit mask. */ -#define FAULT_QUALA_bp 0 /* Fault A Qualification bit position. */ - -/* FAULT.CTRLD bit masks and bit positions */ -#define FAULT_SOFTB_bm 0x80 /* Fault B Software Mode bit mask. */ -#define FAULT_SOFTB_bp 7 /* Fault B Software Mode bit position. */ - -#define FAULT_HALTB_gm 0x60 /* Fault B Halt Action group mask. */ -#define FAULT_HALTB_gp 5 /* Fault B Halt Action group position. */ -#define FAULT_HALTB0_bm (1<<5) /* Fault B Halt Action bit 0 mask. */ -#define FAULT_HALTB0_bp 5 /* Fault B Halt Action bit 0 position. */ -#define FAULT_HALTB1_bm (1<<6) /* Fault B Halt Action bit 1 mask. */ -#define FAULT_HALTB1_bp 6 /* Fault B Halt Action bit 1 position. */ - -#define FAULT_RESTARTB_bm 0x10 /* Fault B Restart Action bit mask. */ -#define FAULT_RESTARTB_bp 4 /* Fault B Restart Action bit position. */ - -#define FAULT_KEEPB_bm 0x08 /* Fault B Keep Action bit mask. */ -#define FAULT_KEEPB_bp 3 /* Fault B Keep Action bit position. */ - -#define FAULT_SRCB_gm 0x03 /* Fault B Source Selection group mask. */ -#define FAULT_SRCB_gp 0 /* Fault B Source Selection group position. */ -#define FAULT_SRCB0_bm (1<<0) /* Fault B Source Selection bit 0 mask. */ -#define FAULT_SRCB0_bp 0 /* Fault B Source Selection bit 0 position. */ -#define FAULT_SRCB1_bm (1<<1) /* Fault B Source Selection bit 1 mask. */ -#define FAULT_SRCB1_bp 1 /* Fault B Source Selection bit 1 position. */ - -/* FAULT.CTRLE bit masks and bit positions */ -#define FAULT_CAPTB_bm 0x20 /* Fault B Capture bit mask. */ -#define FAULT_CAPTB_bp 5 /* Fault B Capture bit position. */ - -#define FAULT_FILTERB_bm 0x04 /* Fault B Digital Filter Selection bit mask. */ -#define FAULT_FILTERB_bp 2 /* Fault B Digital Filter Selection bit position. */ - -#define FAULT_BLANKB_bm 0x02 /* Fault B Blanking bit mask. */ -#define FAULT_BLANKB_bp 1 /* Fault B Blanking bit position. */ - -#define FAULT_QUALB_bm 0x01 /* Fault B Qualification bit mask. */ -#define FAULT_QUALB_bp 0 /* Fault B Qualification bit position. */ - -/* FAULT.STATUS bit masks and bit positions */ -#define FAULT_STATEB_bm 0x80 /* Fault B State bit mask. */ -#define FAULT_STATEB_bp 7 /* Fault B State bit position. */ - -#define FAULT_STATEA_bm 0x40 /* Fault A State bit mask. */ -#define FAULT_STATEA_bp 6 /* Fault A State bit position. */ - -#define FAULT_STATEE_bm 0x20 /* Fault E State bit mask. */ -#define FAULT_STATEE_bp 5 /* Fault E State bit position. */ - -#define FAULT_IDX_bm 0x08 /* Channel Index Flag bit mask. */ -#define FAULT_IDX_bp 3 /* Channel Index Flag bit position. */ - -#define FAULT_FAULTBIN_bm 0x04 /* Fault B Flag bit mask. */ -#define FAULT_FAULTBIN_bp 2 /* Fault B Flag bit position. */ - -#define FAULT_FAULTAIN_bm 0x02 /* Fault A Flag bit mask. */ -#define FAULT_FAULTAIN_bp 1 /* Fault A Flag bit position. */ - -#define FAULT_FAULTEIN_bm 0x01 /* Fault E Flag bit mask. */ -#define FAULT_FAULTEIN_bp 0 /* Fault E Flag bit position. */ - -/* FAULT.CTRLGCLR bit masks and bit positions */ -#define FAULT_HALTBCLR_bm 0x80 /* State B Clear bit mask. */ -#define FAULT_HALTBCLR_bp 7 /* State B Clear bit position. */ - -#define FAULT_HALTACLR_bm 0x40 /* State A Clear bit mask. */ -#define FAULT_HALTACLR_bp 6 /* State A Clear bit position. */ - -#define FAULT_STATEECLR_bm 0x20 /* State E Clear bit mask. */ -#define FAULT_STATEECLR_bp 5 /* State E Clear bit position. */ - -#define FAULT_FAULTB_bm 0x04 /* Fault B Flag bit mask. */ -#define FAULT_FAULTB_bp 2 /* Fault B Flag bit position. */ - -#define FAULT_FAULTA_bm 0x02 /* Fault A Flag bit mask. */ -#define FAULT_FAULTA_bp 1 /* Fault A Flag bit position. */ - -#define FAULT_FAULTE_bm 0x01 /* Fault E Flag bit mask. */ -#define FAULT_FAULTE_bp 0 /* Fault E Flag bit position. */ - -/* FAULT.CTRLGSET bit masks and bit positions */ -#define FAULT_FAULTBSW_bm 0x80 /* Software Fault B bit mask. */ -#define FAULT_FAULTBSW_bp 7 /* Software Fault B bit position. */ - -#define FAULT_FAULTASW_bm 0x40 /* Software Fault A bit mask. */ -#define FAULT_FAULTASW_bp 6 /* Software Fault A bit position. */ - -#define FAULT_FAULTESW_bm 0x20 /* Software Fault E bit mask. */ -#define FAULT_FAULTESW_bp 5 /* Software Fault E bit position. */ - -#define FAULT_IDXCMD_gm 0x18 /* Channel index Command group mask. */ -#define FAULT_IDXCMD_gp 3 /* Channel index Command group position. */ -#define FAULT_IDXCMD0_bm (1<<3) /* Channel index Command bit 0 mask. */ -#define FAULT_IDXCMD0_bp 3 /* Channel index Command bit 0 position. */ -#define FAULT_IDXCMD1_bm (1<<4) /* Channel index Command bit 1 mask. */ -#define FAULT_IDXCMD1_bp 4 /* Channel index Command bit 1 position. */ - -/* WEX - Waveform Extension */ -/* WEX.CTRL bit masks and bit positions */ -#define WEX_UPSEL_bm 0x80 /* Update Source Selection bit mask. */ -#define WEX_UPSEL_bp 7 /* Update Source Selection bit position. */ - -#define WEX_OTMX_gm 0x70 /* Output Matrix group mask. */ -#define WEX_OTMX_gp 4 /* Output Matrix group position. */ -#define WEX_OTMX0_bm (1<<4) /* Output Matrix bit 0 mask. */ -#define WEX_OTMX0_bp 4 /* Output Matrix bit 0 position. */ -#define WEX_OTMX1_bm (1<<5) /* Output Matrix bit 1 mask. */ -#define WEX_OTMX1_bp 5 /* Output Matrix bit 1 position. */ -#define WEX_OTMX2_bm (1<<6) /* Output Matrix bit 2 mask. */ -#define WEX_OTMX2_bp 6 /* Output Matrix bit 2 position. */ - -#define WEX_DTI3EN_bm 0x08 /* Dead-Time Insertion Generator 3 Enable bit mask. */ -#define WEX_DTI3EN_bp 3 /* Dead-Time Insertion Generator 3 Enable bit position. */ - -#define WEX_DTI2EN_bm 0x04 /* Dead-Time Insertion Generator 2 Enable bit mask. */ -#define WEX_DTI2EN_bp 2 /* Dead-Time Insertion Generator 2 Enable bit position. */ - -#define WEX_DTI1EN_bm 0x02 /* Dead-Time Insertion Generator 1 Enable bit mask. */ -#define WEX_DTI1EN_bp 1 /* Dead-Time Insertion Generator 1 Enable bit position. */ - -#define WEX_DTI0EN_bm 0x01 /* Dead-Time Insertion Generator 0 Enable bit mask. */ -#define WEX_DTI0EN_bp 0 /* Dead-Time Insertion Generator 0 Enable bit position. */ - -/* WEX.STATUSCLR bit masks and bit positions */ -#define WEX_SWAPBUF_bm 0x04 /* Swap Buffer Valid bit mask. */ -#define WEX_SWAPBUF_bp 2 /* Swap Buffer Valid bit position. */ - -#define WEX_PGVBUFV_bm 0x02 /* Pattern Generator Value Buffer Valid bit mask. */ -#define WEX_PGVBUFV_bp 1 /* Pattern Generator Value Buffer Valid bit position. */ - -#define WEX_PGOBUFV_bm 0x01 /* Pattern Generator Overwrite Buffer Valid bit mask. */ -#define WEX_PGOBUFV_bp 0 /* Pattern Generator Overwrite Buffer Valid bit position. */ - -/* WEX.STATUSSET bit masks and bit positions */ -/* WEX_SWAPBUF Predefined. */ -/* WEX_SWAPBUF Predefined. */ - -/* WEX_PGVBUFV Predefined. */ -/* WEX_PGVBUFV Predefined. */ - -/* WEX_PGOBUFV Predefined. */ -/* WEX_PGOBUFV Predefined. */ - -/* WEX.SWAP bit masks and bit positions */ -#define WEX_SWAP3_bm 0x08 /* Swap DTI output pair 3 bit mask. */ -#define WEX_SWAP3_bp 3 /* Swap DTI output pair 3 bit position. */ - -#define WEX_SWAP2_bm 0x04 /* Swap DTI output pair 2 bit mask. */ -#define WEX_SWAP2_bp 2 /* Swap DTI output pair 2 bit position. */ - -#define WEX_SWAP1_bm 0x02 /* Swap DTI output pair 1 bit mask. */ -#define WEX_SWAP1_bp 1 /* Swap DTI output pair 1 bit position. */ - -#define WEX_SWAP0_bm 0x01 /* Swap DTI output pair 0 bit mask. */ -#define WEX_SWAP0_bp 0 /* Swap DTI output pair 0 bit position. */ - -/* WEX.SWAPBUF bit masks and bit positions */ -#define WEX_SWAP3BUF_bm 0x08 /* Swap DTI output pair 3 bit mask. */ -#define WEX_SWAP3BUF_bp 3 /* Swap DTI output pair 3 bit position. */ - -#define WEX_SWAP2BUF_bm 0x04 /* Swap DTI output pair 2 bit mask. */ -#define WEX_SWAP2BUF_bp 2 /* Swap DTI output pair 2 bit position. */ - -#define WEX_SWAP1BUF_bm 0x02 /* Swap DTI output pair 1 bit mask. */ -#define WEX_SWAP1BUF_bp 1 /* Swap DTI output pair 1 bit position. */ - -#define WEX_SWAP0BUF_bm 0x01 /* Swap DTI output pair 0 bit mask. */ -#define WEX_SWAP0BUF_bp 0 /* Swap DTI output pair 0 bit position. */ - -/* HIRES - High-Resolution Extension */ -/* HIRES.CTRLA bit masks and bit positions */ -#define HIRES_HRPLUS_gm 0x0C /* High Resolution Plus group mask. */ -#define HIRES_HRPLUS_gp 2 /* High Resolution Plus group position. */ -#define HIRES_HRPLUS0_bm (1<<2) /* High Resolution Plus bit 0 mask. */ -#define HIRES_HRPLUS0_bp 2 /* High Resolution Plus bit 0 position. */ -#define HIRES_HRPLUS1_bm (1<<3) /* High Resolution Plus bit 1 mask. */ -#define HIRES_HRPLUS1_bp 3 /* High Resolution Plus bit 1 position. */ - -#define HIRES_HREN_gm 0x03 /* High Resolution Mode group mask. */ -#define HIRES_HREN_gp 0 /* High Resolution Mode group position. */ -#define HIRES_HREN0_bm (1<<0) /* High Resolution Mode bit 0 mask. */ -#define HIRES_HREN0_bp 0 /* High Resolution Mode bit 0 position. */ -#define HIRES_HREN1_bm (1<<1) /* High Resolution Mode bit 1 mask. */ -#define HIRES_HREN1_bp 1 /* High Resolution Mode bit 1 position. */ - -/* USART - Universal Asynchronous Receiver-Transmitter */ -/* USART.STATUS bit masks and bit positions */ -#define USART_RXCIF_bm 0x80 /* Receive Interrupt Flag bit mask. */ -#define USART_RXCIF_bp 7 /* Receive Interrupt Flag bit position. */ - -#define USART_TXCIF_bm 0x40 /* Transmit Interrupt Flag bit mask. */ -#define USART_TXCIF_bp 6 /* Transmit Interrupt Flag bit position. */ - -#define USART_DREIF_bm 0x20 /* Data Register Empty Flag bit mask. */ -#define USART_DREIF_bp 5 /* Data Register Empty Flag bit position. */ - -#define USART_FERR_bm 0x10 /* Frame Error bit mask. */ -#define USART_FERR_bp 4 /* Frame Error bit position. */ - -#define USART_BUFOVF_bm 0x08 /* Buffer Overflow bit mask. */ -#define USART_BUFOVF_bp 3 /* Buffer Overflow bit position. */ - -#define USART_PERR_bm 0x04 /* Parity Error bit mask. */ -#define USART_PERR_bp 2 /* Parity Error bit position. */ - -#define USART_RXSIF_bm 0x02 /* Receive Start Bit Interrupt Flag bit mask. */ -#define USART_RXSIF_bp 1 /* Receive Start Bit Interrupt Flag bit position. */ - -#define USART_RXB8_bm 0x01 /* Receive Bit 8 bit mask. */ -#define USART_RXB8_bp 0 /* Receive Bit 8 bit position. */ - -#define USART_DRIF_bm 0x01 /* Data Reception Flag bit mask. */ -#define USART_DRIF_bp 0 /* Data Reception Flag bit position. */ - -/* USART.CTRLA bit masks and bit positions */ -#define USART_RXSIE_bm 0x80 /* Receive Start Interrupt Enable bit mask. */ -#define USART_RXSIE_bp 7 /* Receive Start Interrupt Enable bit position. */ - -#define USART_DRIE_bm 0x40 /* Data Reception Interrupt Enable bit mask. */ -#define USART_DRIE_bp 6 /* Data Reception Interrupt Enable bit position. */ - -#define USART_RXCINTLVL_gm 0x30 /* Receive Interrupt Level group mask. */ -#define USART_RXCINTLVL_gp 4 /* Receive Interrupt Level group position. */ -#define USART_RXCINTLVL0_bm (1<<4) /* Receive Interrupt Level bit 0 mask. */ -#define USART_RXCINTLVL0_bp 4 /* Receive Interrupt Level bit 0 position. */ -#define USART_RXCINTLVL1_bm (1<<5) /* Receive Interrupt Level bit 1 mask. */ -#define USART_RXCINTLVL1_bp 5 /* Receive Interrupt Level bit 1 position. */ - -#define USART_TXCINTLVL_gm 0x0C /* Transmit Interrupt Level group mask. */ -#define USART_TXCINTLVL_gp 2 /* Transmit Interrupt Level group position. */ -#define USART_TXCINTLVL0_bm (1<<2) /* Transmit Interrupt Level bit 0 mask. */ -#define USART_TXCINTLVL0_bp 2 /* Transmit Interrupt Level bit 0 position. */ -#define USART_TXCINTLVL1_bm (1<<3) /* Transmit Interrupt Level bit 1 mask. */ -#define USART_TXCINTLVL1_bp 3 /* Transmit Interrupt Level bit 1 position. */ - -#define USART_DREINTLVL_gm 0x03 /* Data Register Empty Interrupt Level group mask. */ -#define USART_DREINTLVL_gp 0 /* Data Register Empty Interrupt Level group position. */ -#define USART_DREINTLVL0_bm (1<<0) /* Data Register Empty Interrupt Level bit 0 mask. */ -#define USART_DREINTLVL0_bp 0 /* Data Register Empty Interrupt Level bit 0 position. */ -#define USART_DREINTLVL1_bm (1<<1) /* Data Register Empty Interrupt Level bit 1 mask. */ -#define USART_DREINTLVL1_bp 1 /* Data Register Empty Interrupt Level bit 1 position. */ - -/* USART.CTRLB bit masks and bit positions */ -#define USART_ONEWIRE_bm 0x80 /* One Wire Mode bit mask. */ -#define USART_ONEWIRE_bp 7 /* One Wire Mode bit position. */ - -#define USART_SFDEN_bm 0x40 /* Start Frame Detection Enable bit mask. */ -#define USART_SFDEN_bp 6 /* Start Frame Detection Enable bit position. */ - -#define USART_RXEN_bm 0x10 /* Receiver Enable bit mask. */ -#define USART_RXEN_bp 4 /* Receiver Enable bit position. */ - -#define USART_TXEN_bm 0x08 /* Transmitter Enable bit mask. */ -#define USART_TXEN_bp 3 /* Transmitter Enable bit position. */ - -#define USART_CLK2X_bm 0x04 /* Double transmission speed bit mask. */ -#define USART_CLK2X_bp 2 /* Double transmission speed bit position. */ - -#define USART_MPCM_bm 0x02 /* Multi-processor Communication Mode bit mask. */ -#define USART_MPCM_bp 1 /* Multi-processor Communication Mode bit position. */ - -#define USART_TXB8_bm 0x01 /* Transmit bit 8 bit mask. */ -#define USART_TXB8_bp 0 /* Transmit bit 8 bit position. */ - -/* USART.CTRLC bit masks and bit positions */ -#define USART_CMODE_gm 0xC0 /* Communication Mode group mask. */ -#define USART_CMODE_gp 6 /* Communication Mode group position. */ -#define USART_CMODE0_bm (1<<6) /* Communication Mode bit 0 mask. */ -#define USART_CMODE0_bp 6 /* Communication Mode bit 0 position. */ -#define USART_CMODE1_bm (1<<7) /* Communication Mode bit 1 mask. */ -#define USART_CMODE1_bp 7 /* Communication Mode bit 1 position. */ - -#define USART_PMODE_gm 0x30 /* Parity Mode group mask. */ -#define USART_PMODE_gp 4 /* Parity Mode group position. */ -#define USART_PMODE0_bm (1<<4) /* Parity Mode bit 0 mask. */ -#define USART_PMODE0_bp 4 /* Parity Mode bit 0 position. */ -#define USART_PMODE1_bm (1<<5) /* Parity Mode bit 1 mask. */ -#define USART_PMODE1_bp 5 /* Parity Mode bit 1 position. */ - -#define USART_SBMODE_bm 0x08 /* Stop Bit Mode bit mask. */ -#define USART_SBMODE_bp 3 /* Stop Bit Mode bit position. */ - -#define USART_CHSIZE_gm 0x07 /* Character Size group mask. */ -#define USART_CHSIZE_gp 0 /* Character Size group position. */ -#define USART_CHSIZE0_bm (1<<0) /* Character Size bit 0 mask. */ -#define USART_CHSIZE0_bp 0 /* Character Size bit 0 position. */ -#define USART_CHSIZE1_bm (1<<1) /* Character Size bit 1 mask. */ -#define USART_CHSIZE1_bp 1 /* Character Size bit 1 position. */ -#define USART_CHSIZE2_bm (1<<2) /* Character Size bit 2 mask. */ -#define USART_CHSIZE2_bp 2 /* Character Size bit 2 position. */ - -/* USART.CTRLD bit masks and bit positions */ -#define USART_DECTYPE_gm 0x30 /* Receive Interrupt Level group mask. */ -#define USART_DECTYPE_gp 4 /* Receive Interrupt Level group position. */ -#define USART_DECTYPE0_bm (1<<4) /* Receive Interrupt Level bit 0 mask. */ -#define USART_DECTYPE0_bp 4 /* Receive Interrupt Level bit 0 position. */ -#define USART_DECTYPE1_bm (1<<5) /* Receive Interrupt Level bit 1 mask. */ -#define USART_DECTYPE1_bp 5 /* Receive Interrupt Level bit 1 position. */ - -#define USART_LUTACT_gm 0x0C /* Transmit Interrupt Level group mask. */ -#define USART_LUTACT_gp 2 /* Transmit Interrupt Level group position. */ -#define USART_LUTACT0_bm (1<<2) /* Transmit Interrupt Level bit 0 mask. */ -#define USART_LUTACT0_bp 2 /* Transmit Interrupt Level bit 0 position. */ -#define USART_LUTACT1_bm (1<<3) /* Transmit Interrupt Level bit 1 mask. */ -#define USART_LUTACT1_bp 3 /* Transmit Interrupt Level bit 1 position. */ - -#define USART_PECACT_gm 0x03 /* Data Register Empty Interrupt Level group mask. */ -#define USART_PECACT_gp 0 /* Data Register Empty Interrupt Level group position. */ -#define USART_PECACT0_bm (1<<0) /* Data Register Empty Interrupt Level bit 0 mask. */ -#define USART_PECACT0_bp 0 /* Data Register Empty Interrupt Level bit 0 position. */ -#define USART_PECACT1_bm (1<<1) /* Data Register Empty Interrupt Level bit 1 mask. */ -#define USART_PECACT1_bp 1 /* Data Register Empty Interrupt Level bit 1 position. */ - -/* USART.BAUDCTRLA bit masks and bit positions */ -#define USART_BSEL_gm 0xFF /* Baud Rate Selection Bits [7:0] group mask. */ -#define USART_BSEL_gp 0 /* Baud Rate Selection Bits [7:0] group position. */ -#define USART_BSEL0_bm (1<<0) /* Baud Rate Selection Bits [7:0] bit 0 mask. */ -#define USART_BSEL0_bp 0 /* Baud Rate Selection Bits [7:0] bit 0 position. */ -#define USART_BSEL1_bm (1<<1) /* Baud Rate Selection Bits [7:0] bit 1 mask. */ -#define USART_BSEL1_bp 1 /* Baud Rate Selection Bits [7:0] bit 1 position. */ -#define USART_BSEL2_bm (1<<2) /* Baud Rate Selection Bits [7:0] bit 2 mask. */ -#define USART_BSEL2_bp 2 /* Baud Rate Selection Bits [7:0] bit 2 position. */ -#define USART_BSEL3_bm (1<<3) /* Baud Rate Selection Bits [7:0] bit 3 mask. */ -#define USART_BSEL3_bp 3 /* Baud Rate Selection Bits [7:0] bit 3 position. */ -#define USART_BSEL4_bm (1<<4) /* Baud Rate Selection Bits [7:0] bit 4 mask. */ -#define USART_BSEL4_bp 4 /* Baud Rate Selection Bits [7:0] bit 4 position. */ -#define USART_BSEL5_bm (1<<5) /* Baud Rate Selection Bits [7:0] bit 5 mask. */ -#define USART_BSEL5_bp 5 /* Baud Rate Selection Bits [7:0] bit 5 position. */ -#define USART_BSEL6_bm (1<<6) /* Baud Rate Selection Bits [7:0] bit 6 mask. */ -#define USART_BSEL6_bp 6 /* Baud Rate Selection Bits [7:0] bit 6 position. */ -#define USART_BSEL7_bm (1<<7) /* Baud Rate Selection Bits [7:0] bit 7 mask. */ -#define USART_BSEL7_bp 7 /* Baud Rate Selection Bits [7:0] bit 7 position. */ - -/* USART.BAUDCTRLB bit masks and bit positions */ -#define USART_BSCALE_gm 0xF0 /* Baud Rate Scale group mask. */ -#define USART_BSCALE_gp 4 /* Baud Rate Scale group position. */ -#define USART_BSCALE0_bm (1<<4) /* Baud Rate Scale bit 0 mask. */ -#define USART_BSCALE0_bp 4 /* Baud Rate Scale bit 0 position. */ -#define USART_BSCALE1_bm (1<<5) /* Baud Rate Scale bit 1 mask. */ -#define USART_BSCALE1_bp 5 /* Baud Rate Scale bit 1 position. */ -#define USART_BSCALE2_bm (1<<6) /* Baud Rate Scale bit 2 mask. */ -#define USART_BSCALE2_bp 6 /* Baud Rate Scale bit 2 position. */ -#define USART_BSCALE3_bm (1<<7) /* Baud Rate Scale bit 3 mask. */ -#define USART_BSCALE3_bp 7 /* Baud Rate Scale bit 3 position. */ - -/* USART_BSEL Predefined. */ -/* USART_BSEL Predefined. */ - -/* SPI - Serial Peripheral Interface */ -/* SPI.CTRL bit masks and bit positions */ -#define SPI_CLK2X_bm 0x80 /* Enable Double Speed bit mask. */ -#define SPI_CLK2X_bp 7 /* Enable Double Speed bit position. */ - -#define SPI_ENABLE_bm 0x40 /* Enable SPI Module bit mask. */ -#define SPI_ENABLE_bp 6 /* Enable SPI Module bit position. */ - -#define SPI_DORD_bm 0x20 /* Data Order Setting bit mask. */ -#define SPI_DORD_bp 5 /* Data Order Setting bit position. */ - -#define SPI_MASTER_bm 0x10 /* Master Operation Enable bit mask. */ -#define SPI_MASTER_bp 4 /* Master Operation Enable bit position. */ - -#define SPI_MODE_gm 0x0C /* SPI Mode group mask. */ -#define SPI_MODE_gp 2 /* SPI Mode group position. */ -#define SPI_MODE0_bm (1<<2) /* SPI Mode bit 0 mask. */ -#define SPI_MODE0_bp 2 /* SPI Mode bit 0 position. */ -#define SPI_MODE1_bm (1<<3) /* SPI Mode bit 1 mask. */ -#define SPI_MODE1_bp 3 /* SPI Mode bit 1 position. */ - -#define SPI_PRESCALER_gm 0x03 /* Prescaler group mask. */ -#define SPI_PRESCALER_gp 0 /* Prescaler group position. */ -#define SPI_PRESCALER0_bm (1<<0) /* Prescaler bit 0 mask. */ -#define SPI_PRESCALER0_bp 0 /* Prescaler bit 0 position. */ -#define SPI_PRESCALER1_bm (1<<1) /* Prescaler bit 1 mask. */ -#define SPI_PRESCALER1_bp 1 /* Prescaler bit 1 position. */ - -/* SPI.INTCTRL bit masks and bit positions */ -#define SPI_RXCIE_bm 0x80 /* Receive Complete Interrupt Enable (In Buffer Modes Only). bit mask. */ -#define SPI_RXCIE_bp 7 /* Receive Complete Interrupt Enable (In Buffer Modes Only). bit position. */ - -#define SPI_TXCIE_bm 0x40 /* Transmit Complete Interrupt Enable (In Buffer Modes Only). bit mask. */ -#define SPI_TXCIE_bp 6 /* Transmit Complete Interrupt Enable (In Buffer Modes Only). bit position. */ - -#define SPI_DREIE_bm 0x20 /* Data Register Empty Interrupt Enable (In Buffer Modes Only). bit mask. */ -#define SPI_DREIE_bp 5 /* Data Register Empty Interrupt Enable (In Buffer Modes Only). bit position. */ - -#define SPI_SSIE_bm 0x10 /* Slave Select Trigger Interrupt Enable (In Buffer Modes Only). bit mask. */ -#define SPI_SSIE_bp 4 /* Slave Select Trigger Interrupt Enable (In Buffer Modes Only). bit position. */ - -#define SPI_INTLVL_gm 0x03 /* Interrupt level group mask. */ -#define SPI_INTLVL_gp 0 /* Interrupt level group position. */ -#define SPI_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */ -#define SPI_INTLVL0_bp 0 /* Interrupt level bit 0 position. */ -#define SPI_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */ -#define SPI_INTLVL1_bp 1 /* Interrupt level bit 1 position. */ - -/* SPI.STATUS bit masks and bit positions */ -#define SPI_IF_bm 0x80 /* Interrupt Flag (In Standard Mode Only). bit mask. */ -#define SPI_IF_bp 7 /* Interrupt Flag (In Standard Mode Only). bit position. */ - -#define SPI_RXCIF_bm 0x80 /* Receive Complete Interrupt Flag (In Buffer Modes Only). bit mask. */ -#define SPI_RXCIF_bp 7 /* Receive Complete Interrupt Flag (In Buffer Modes Only). bit position. */ - -#define SPI_WRCOL_bm 0x40 /* Write Collision Flag (In Standard Mode Only). bit mask. */ -#define SPI_WRCOL_bp 6 /* Write Collision Flag (In Standard Mode Only). bit position. */ - -#define SPI_TXCIF_bm 0x40 /* Transmit Complete Interrupt Flag (In Buffer Modes Only). bit mask. */ -#define SPI_TXCIF_bp 6 /* Transmit Complete Interrupt Flag (In Buffer Modes Only). bit position. */ - -#define SPI_DREIF_bm 0x20 /* Data Register Empty Interrupt Flag (In Buffer Modes Only). bit mask. */ -#define SPI_DREIF_bp 5 /* Data Register Empty Interrupt Flag (In Buffer Modes Only). bit position. */ - -#define SPI_SSIF_bm 0x10 /* Slave Select Trigger Interrupt Flag (In Buffer Modes Only). bit mask. */ -#define SPI_SSIF_bp 4 /* Slave Select Trigger Interrupt Flag (In Buffer Modes Only). bit position. */ - -#define SPI_BUFOVF_bm 0x01 /* Buffer Overflow (In Buffer Modes Only). bit mask. */ -#define SPI_BUFOVF_bp 0 /* Buffer Overflow (In Buffer Modes Only). bit position. */ - -/* SPI.CTRLB bit masks and bit positions */ -#define SPI_BUFMODE_gm 0xC0 /* Buffer Modes group mask. */ -#define SPI_BUFMODE_gp 6 /* Buffer Modes group position. */ -#define SPI_BUFMODE0_bm (1<<6) /* Buffer Modes bit 0 mask. */ -#define SPI_BUFMODE0_bp 6 /* Buffer Modes bit 0 position. */ -#define SPI_BUFMODE1_bm (1<<7) /* Buffer Modes bit 1 mask. */ -#define SPI_BUFMODE1_bp 7 /* Buffer Modes bit 1 position. */ - -#define SPI_SSD_bm 0x04 /* Slave Select Disable bit mask. */ -#define SPI_SSD_bp 2 /* Slave Select Disable bit position. */ - -/* IRCOM - IR Communication Module */ -/* IRCOM.CTRL bit masks and bit positions */ -#define IRCOM_EVSEL_gm 0x0F /* Event Channel Select group mask. */ -#define IRCOM_EVSEL_gp 0 /* Event Channel Select group position. */ -#define IRCOM_EVSEL0_bm (1<<0) /* Event Channel Select bit 0 mask. */ -#define IRCOM_EVSEL0_bp 0 /* Event Channel Select bit 0 position. */ -#define IRCOM_EVSEL1_bm (1<<1) /* Event Channel Select bit 1 mask. */ -#define IRCOM_EVSEL1_bp 1 /* Event Channel Select bit 1 position. */ -#define IRCOM_EVSEL2_bm (1<<2) /* Event Channel Select bit 2 mask. */ -#define IRCOM_EVSEL2_bp 2 /* Event Channel Select bit 2 position. */ -#define IRCOM_EVSEL3_bm (1<<3) /* Event Channel Select bit 3 mask. */ -#define IRCOM_EVSEL3_bp 3 /* Event Channel Select bit 3 position. */ - -/* FUSE - Fuses and Lockbits */ -/* NVM_LOCKBITS.LOCKBITS bit masks and bit positions */ -#define NVM_LOCKBITS_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ -#define NVM_LOCKBITS_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ -#define NVM_LOCKBITS_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ -#define NVM_LOCKBITS_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ -#define NVM_LOCKBITS_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ -#define NVM_LOCKBITS_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ - -#define NVM_LOCKBITS_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ -#define NVM_LOCKBITS_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ -#define NVM_LOCKBITS_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ -#define NVM_LOCKBITS_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ -#define NVM_LOCKBITS_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ -#define NVM_LOCKBITS_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ - -#define NVM_LOCKBITS_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ -#define NVM_LOCKBITS_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ -#define NVM_LOCKBITS_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ -#define NVM_LOCKBITS_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ -#define NVM_LOCKBITS_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ -#define NVM_LOCKBITS_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ - -#define NVM_LOCKBITS_LB_gm 0x03 /* Lock Bits group mask. */ -#define NVM_LOCKBITS_LB_gp 0 /* Lock Bits group position. */ -#define NVM_LOCKBITS_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ -#define NVM_LOCKBITS_LB0_bp 0 /* Lock Bits bit 0 position. */ -#define NVM_LOCKBITS_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ -#define NVM_LOCKBITS_LB1_bp 1 /* Lock Bits bit 1 position. */ - -/* NVM_FUSES.FUSEBYTE1 bit masks and bit positions */ -#define NVM_FUSES_WDWP_gm 0xF0 /* Watchdog Window Timeout Period group mask. */ -#define NVM_FUSES_WDWP_gp 4 /* Watchdog Window Timeout Period group position. */ -#define NVM_FUSES_WDWP0_bm (1<<4) /* Watchdog Window Timeout Period bit 0 mask. */ -#define NVM_FUSES_WDWP0_bp 4 /* Watchdog Window Timeout Period bit 0 position. */ -#define NVM_FUSES_WDWP1_bm (1<<5) /* Watchdog Window Timeout Period bit 1 mask. */ -#define NVM_FUSES_WDWP1_bp 5 /* Watchdog Window Timeout Period bit 1 position. */ -#define NVM_FUSES_WDWP2_bm (1<<6) /* Watchdog Window Timeout Period bit 2 mask. */ -#define NVM_FUSES_WDWP2_bp 6 /* Watchdog Window Timeout Period bit 2 position. */ -#define NVM_FUSES_WDWP3_bm (1<<7) /* Watchdog Window Timeout Period bit 3 mask. */ -#define NVM_FUSES_WDWP3_bp 7 /* Watchdog Window Timeout Period bit 3 position. */ - -#define NVM_FUSES_WDP_gm 0x0F /* Watchdog Timeout Period group mask. */ -#define NVM_FUSES_WDP_gp 0 /* Watchdog Timeout Period group position. */ -#define NVM_FUSES_WDP0_bm (1<<0) /* Watchdog Timeout Period bit 0 mask. */ -#define NVM_FUSES_WDP0_bp 0 /* Watchdog Timeout Period bit 0 position. */ -#define NVM_FUSES_WDP1_bm (1<<1) /* Watchdog Timeout Period bit 1 mask. */ -#define NVM_FUSES_WDP1_bp 1 /* Watchdog Timeout Period bit 1 position. */ -#define NVM_FUSES_WDP2_bm (1<<2) /* Watchdog Timeout Period bit 2 mask. */ -#define NVM_FUSES_WDP2_bp 2 /* Watchdog Timeout Period bit 2 position. */ -#define NVM_FUSES_WDP3_bm (1<<3) /* Watchdog Timeout Period bit 3 mask. */ -#define NVM_FUSES_WDP3_bp 3 /* Watchdog Timeout Period bit 3 position. */ - -/* NVM_FUSES.FUSEBYTE2 bit masks and bit positions */ -#define NVM_FUSES_BOOTRST_bm 0x40 /* Boot Loader Section Reset Vector bit mask. */ -#define NVM_FUSES_BOOTRST_bp 6 /* Boot Loader Section Reset Vector bit position. */ - -#define NVM_FUSES_BODPD_gm 0x03 /* BOD Operation in Power-Down Mode group mask. */ -#define NVM_FUSES_BODPD_gp 0 /* BOD Operation in Power-Down Mode group position. */ -#define NVM_FUSES_BODPD0_bm (1<<0) /* BOD Operation in Power-Down Mode bit 0 mask. */ -#define NVM_FUSES_BODPD0_bp 0 /* BOD Operation in Power-Down Mode bit 0 position. */ -#define NVM_FUSES_BODPD1_bm (1<<1) /* BOD Operation in Power-Down Mode bit 1 mask. */ -#define NVM_FUSES_BODPD1_bp 1 /* BOD Operation in Power-Down Mode bit 1 position. */ - -/* NVM_FUSES.FUSEBYTE4 bit masks and bit positions */ -#define NVM_FUSES_RSTDISBL_bm 0x10 /* External Reset Disable bit mask. */ -#define NVM_FUSES_RSTDISBL_bp 4 /* External Reset Disable bit position. */ - -#define NVM_FUSES_SUT_gm 0x0C /* Start-up Time group mask. */ -#define NVM_FUSES_SUT_gp 2 /* Start-up Time group position. */ -#define NVM_FUSES_SUT0_bm (1<<2) /* Start-up Time bit 0 mask. */ -#define NVM_FUSES_SUT0_bp 2 /* Start-up Time bit 0 position. */ -#define NVM_FUSES_SUT1_bm (1<<3) /* Start-up Time bit 1 mask. */ -#define NVM_FUSES_SUT1_bp 3 /* Start-up Time bit 1 position. */ - -#define NVM_FUSES_WDLOCK_bm 0x02 /* Watchdog Timer Lock bit mask. */ -#define NVM_FUSES_WDLOCK_bp 1 /* Watchdog Timer Lock bit position. */ - -/* NVM_FUSES.FUSEBYTE5 bit masks and bit positions */ -#define NVM_FUSES_BODACT_gm 0x30 /* BOD Operation in Active Mode group mask. */ -#define NVM_FUSES_BODACT_gp 4 /* BOD Operation in Active Mode group position. */ -#define NVM_FUSES_BODACT0_bm (1<<4) /* BOD Operation in Active Mode bit 0 mask. */ -#define NVM_FUSES_BODACT0_bp 4 /* BOD Operation in Active Mode bit 0 position. */ -#define NVM_FUSES_BODACT1_bm (1<<5) /* BOD Operation in Active Mode bit 1 mask. */ -#define NVM_FUSES_BODACT1_bp 5 /* BOD Operation in Active Mode bit 1 position. */ - -#define NVM_FUSES_EESAVE_bm 0x08 /* Preserve EEPROM Through Chip Erase bit mask. */ -#define NVM_FUSES_EESAVE_bp 3 /* Preserve EEPROM Through Chip Erase bit position. */ - -#define NVM_FUSES_BODLVL_gm 0x07 /* Brownout Detection Voltage Level group mask. */ -#define NVM_FUSES_BODLVL_gp 0 /* Brownout Detection Voltage Level group position. */ -#define NVM_FUSES_BODLVL0_bm (1<<0) /* Brownout Detection Voltage Level bit 0 mask. */ -#define NVM_FUSES_BODLVL0_bp 0 /* Brownout Detection Voltage Level bit 0 position. */ -#define NVM_FUSES_BODLVL1_bm (1<<1) /* Brownout Detection Voltage Level bit 1 mask. */ -#define NVM_FUSES_BODLVL1_bp 1 /* Brownout Detection Voltage Level bit 1 position. */ -#define NVM_FUSES_BODLVL2_bm (1<<2) /* Brownout Detection Voltage Level bit 2 mask. */ -#define NVM_FUSES_BODLVL2_bp 2 /* Brownout Detection Voltage Level bit 2 position. */ - -/* NVM_FUSES.FUSEBYTE6 bit masks and bit positions */ -#define NVM_FUSES_FDACT5_bm 0x80 /* Fault Dectection Action on TC5 bit mask. */ -#define NVM_FUSES_FDACT5_bp 7 /* Fault Dectection Action on TC5 bit position. */ - -#define NVM_FUSES_FDACT4_bm 0x40 /* Fault Dectection Action on TC4 bit mask. */ -#define NVM_FUSES_FDACT4_bp 6 /* Fault Dectection Action on TC4 bit position. */ - -#define NVM_FUSES_VALUE_gm 0x3F /* Port Pin Value group mask. */ -#define NVM_FUSES_VALUE_gp 0 /* Port Pin Value group position. */ -#define NVM_FUSES_VALUE0_bm (1<<0) /* Port Pin Value bit 0 mask. */ -#define NVM_FUSES_VALUE0_bp 0 /* Port Pin Value bit 0 position. */ -#define NVM_FUSES_VALUE1_bm (1<<1) /* Port Pin Value bit 1 mask. */ -#define NVM_FUSES_VALUE1_bp 1 /* Port Pin Value bit 1 position. */ -#define NVM_FUSES_VALUE2_bm (1<<2) /* Port Pin Value bit 2 mask. */ -#define NVM_FUSES_VALUE2_bp 2 /* Port Pin Value bit 2 position. */ -#define NVM_FUSES_VALUE3_bm (1<<3) /* Port Pin Value bit 3 mask. */ -#define NVM_FUSES_VALUE3_bp 3 /* Port Pin Value bit 3 position. */ -#define NVM_FUSES_VALUE4_bm (1<<4) /* Port Pin Value bit 4 mask. */ -#define NVM_FUSES_VALUE4_bp 4 /* Port Pin Value bit 4 position. */ -#define NVM_FUSES_VALUE5_bm (1<<5) /* Port Pin Value bit 5 mask. */ -#define NVM_FUSES_VALUE5_bp 5 /* Port Pin Value bit 5 position. */ - - - -// Generic Port Pins - -#define PIN0_bm 0x01 -#define PIN0_bp 0 -#define PIN1_bm 0x02 -#define PIN1_bp 1 -#define PIN2_bm 0x04 -#define PIN2_bp 2 -#define PIN3_bm 0x08 -#define PIN3_bp 3 -#define PIN4_bm 0x10 -#define PIN4_bp 4 -#define PIN5_bm 0x20 -#define PIN5_bp 5 -#define PIN6_bm 0x40 -#define PIN6_bp 6 -#define PIN7_bm 0x80 -#define PIN7_bp 7 - -/* ========== Interrupt Vector Definitions ========== */ -/* Vector 0 is the reset vector */ - -/* OSC interrupt vectors */ -#define OSC_OSCF_vect_num 1 -#define OSC_OSCF_vect _VECTOR(1) /* Oscillator Failure Interrupt (NMI) */ - -/* PORTR interrupt vectors */ -#define PORTR_INT_vect_num 2 -#define PORTR_INT_vect _VECTOR(2) /* External Interrupt */ - -/* EDMA interrupt vectors */ -#define EDMA_CH0_vect_num 3 -#define EDMA_CH0_vect _VECTOR(3) /* EDMA Channel 0 Interrupt */ -#define EDMA_CH1_vect_num 4 -#define EDMA_CH1_vect _VECTOR(4) /* EDMA Channel 1 Interrupt */ -#define EDMA_CH2_vect_num 5 -#define EDMA_CH2_vect _VECTOR(5) /* EDMA Channel 2 Interrupt */ -#define EDMA_CH3_vect_num 6 -#define EDMA_CH3_vect _VECTOR(6) /* EDMA Channel 3 Interrupt */ - -/* RTC interrupt vectors */ -#define RTC_OVF_vect_num 7 -#define RTC_OVF_vect _VECTOR(7) /* Overflow Interrupt */ -#define RTC_COMP_vect_num 8 -#define RTC_COMP_vect _VECTOR(8) /* Compare Interrupt */ - -/* PORTC interrupt vectors */ -#define PORTC_INT_vect_num 9 -#define PORTC_INT_vect _VECTOR(9) /* External Interrupt */ - -/* TWIC interrupt vectors */ -#define TWIC_TWIS_vect_num 10 -#define TWIC_TWIS_vect _VECTOR(10) /* TWI Slave Interrupt */ -#define TWIC_TWIM_vect_num 11 -#define TWIC_TWIM_vect _VECTOR(11) /* TWI Master Interrupt */ - -/* TCC4 interrupt vectors */ -#define TCC4_OVF_vect_num 12 -#define TCC4_OVF_vect _VECTOR(12) /* Overflow Interrupt */ -#define TCC4_ERR_vect_num 13 -#define TCC4_ERR_vect _VECTOR(13) /* Error Interrupt */ -#define TCC4_CCA_vect_num 14 -#define TCC4_CCA_vect _VECTOR(14) /* Channel A Compare or Capture Interrupt */ -#define TCC4_CCB_vect_num 15 -#define TCC4_CCB_vect _VECTOR(15) /* Channel B Compare or Capture Interrupt */ -#define TCC4_CCC_vect_num 16 -#define TCC4_CCC_vect _VECTOR(16) /* Channel C Compare or Capture Interrupt */ -#define TCC4_CCD_vect_num 17 -#define TCC4_CCD_vect _VECTOR(17) /* Channel D Compare or Capture Interrupt */ - -/* TCC5 interrupt vectors */ -#define TCC5_OVF_vect_num 18 -#define TCC5_OVF_vect _VECTOR(18) /* Overflow Interrupt */ -#define TCC5_ERR_vect_num 19 -#define TCC5_ERR_vect _VECTOR(19) /* Error Interrupt */ -#define TCC5_CCA_vect_num 20 -#define TCC5_CCA_vect _VECTOR(20) /* Channel A Compare or Capture Interrupt */ -#define TCC5_CCB_vect_num 21 -#define TCC5_CCB_vect _VECTOR(21) /* Channel B Compare or Capture Interrupt */ - -/* SPIC interrupt vectors */ -#define SPIC_INT_vect_num 22 -#define SPIC_INT_vect _VECTOR(22) /* SPI Interrupt */ - -/* USARTC0 interrupt vectors */ -#define USARTC0_RXC_vect_num 23 -#define USARTC0_RXC_vect _VECTOR(23) /* Reception Complete Interrupt */ -#define USARTC0_DRE_vect_num 24 -#define USARTC0_DRE_vect _VECTOR(24) /* Data Register Empty Interrupt */ -#define USARTC0_TXC_vect_num 25 -#define USARTC0_TXC_vect _VECTOR(25) /* Transmission Complete Interrupt */ - -/* NVM interrupt vectors */ -#define NVM_EE_vect_num 26 -#define NVM_EE_vect _VECTOR(26) /* EE Interrupt */ -#define NVM_SPM_vect_num 27 -#define NVM_SPM_vect _VECTOR(27) /* SPM Interrupt */ - -/* XCL interrupt vectors */ -#define XCL_UNF_vect_num 28 -#define XCL_UNF_vect _VECTOR(28) /* Timer/Counter Underflow Interrupt */ -#define XCL_CC_vect_num 29 -#define XCL_CC_vect _VECTOR(29) /* Timer/Counter Compare or Capture Interrupt */ - -/* PORTA interrupt vectors */ -#define PORTA_INT_vect_num 30 -#define PORTA_INT_vect _VECTOR(30) /* External Interrupt */ - -/* ACA interrupt vectors */ -#define ACA_AC0_vect_num 31 -#define ACA_AC0_vect _VECTOR(31) /* AC0 Interrupt */ -#define ACA_AC1_vect_num 32 -#define ACA_AC1_vect _VECTOR(32) /* AC1 Interrupt */ -#define ACA_ACW_vect_num 33 -#define ACA_ACW_vect _VECTOR(33) /* ACW Window Mode Interrupt */ - -/* ADCA interrupt vectors */ -#define ADCA_CH0_vect_num 34 -#define ADCA_CH0_vect _VECTOR(34) /* ADC Channel Interrupt */ - -/* PORTD interrupt vectors */ -#define PORTD_INT_vect_num 35 -#define PORTD_INT_vect _VECTOR(35) /* External Interrupt */ - -/* TCD5 interrupt vectors */ -#define TCD5_OVF_vect_num 36 -#define TCD5_OVF_vect _VECTOR(36) /* Overflow Interrupt */ -#define TCD5_ERR_vect_num 37 -#define TCD5_ERR_vect _VECTOR(37) /* Error Interrupt */ -#define TCD5_CCA_vect_num 38 -#define TCD5_CCA_vect _VECTOR(38) /* Channel A Compare or Capture Interrupt */ -#define TCD5_CCB_vect_num 39 -#define TCD5_CCB_vect _VECTOR(39) /* Channel B Compare or Capture Interrupt */ - -/* USARTD0 interrupt vectors */ -#define USARTD0_RXC_vect_num 40 -#define USARTD0_RXC_vect _VECTOR(40) /* Reception Complete Interrupt */ -#define USARTD0_DRE_vect_num 41 -#define USARTD0_DRE_vect _VECTOR(41) /* Data Register Empty Interrupt */ -#define USARTD0_TXC_vect_num 42 -#define USARTD0_TXC_vect _VECTOR(42) /* Transmission Complete Interrupt */ - -#define _VECTOR_SIZE 4 /* Size of individual vector. */ -#define _VECTORS_SIZE (43 * _VECTOR_SIZE) - - -/* ========== Constants ========== */ - -#define PROGMEM_START (0x0000) -#define PROGMEM_SIZE (10240) -#define PROGMEM_END (PROGMEM_START + PROGMEM_SIZE - 1) - -#define APP_SECTION_START (0x0000) -#define APP_SECTION_SIZE (8192) -#define APP_SECTION_PAGE_SIZE (128) -#define APP_SECTION_END (APP_SECTION_START + APP_SECTION_SIZE - 1) - -#define APPTABLE_SECTION_START (0x1800) -#define APPTABLE_SECTION_SIZE (2048) -#define APPTABLE_SECTION_PAGE_SIZE (128) -#define APPTABLE_SECTION_END (APPTABLE_SECTION_START + APPTABLE_SECTION_SIZE - 1) - -#define BOOT_SECTION_START (0x2000) -#define BOOT_SECTION_SIZE (2048) -#define BOOT_SECTION_PAGE_SIZE (128) -#define BOOT_SECTION_END (BOOT_SECTION_START + BOOT_SECTION_SIZE - 1) - -#define DATAMEM_START (0x0000) -#define DATAMEM_SIZE (9216) -#define DATAMEM_END (DATAMEM_START + DATAMEM_SIZE - 1) - -#define IO_START (0x0000) -#define IO_SIZE (4096) -#define IO_PAGE_SIZE (0) -#define IO_END (IO_START + IO_SIZE - 1) - -#define MAPPED_EEPROM_START (0x1000) -#define MAPPED_EEPROM_SIZE (512) -#define MAPPED_EEPROM_PAGE_SIZE (0) -#define MAPPED_EEPROM_END (MAPPED_EEPROM_START + MAPPED_EEPROM_SIZE - 1) - -#define INTERNAL_SRAM_START (0x2000) -#define INTERNAL_SRAM_SIZE (1024) -#define INTERNAL_SRAM_PAGE_SIZE (0) -#define INTERNAL_SRAM_END (INTERNAL_SRAM_START + INTERNAL_SRAM_SIZE - 1) - -#define EEPROM_START (0x0000) -#define EEPROM_SIZE (512) -#define EEPROM_PAGE_SIZE (32) -#define EEPROM_END (EEPROM_START + EEPROM_SIZE - 1) - -#define SIGNATURES_START (0x0000) -#define SIGNATURES_SIZE (3) -#define SIGNATURES_PAGE_SIZE (0) -#define SIGNATURES_END (SIGNATURES_START + SIGNATURES_SIZE - 1) - -#define FUSES_START (0x0000) -#define FUSES_SIZE (7) -#define FUSES_PAGE_SIZE (0) -#define FUSES_END (FUSES_START + FUSES_SIZE - 1) - -#define LOCKBITS_START (0x0000) -#define LOCKBITS_SIZE (1) -#define LOCKBITS_PAGE_SIZE (0) -#define LOCKBITS_END (LOCKBITS_START + LOCKBITS_SIZE - 1) - -#define USER_SIGNATURES_START (0x0000) -#define USER_SIGNATURES_SIZE (128) -#define USER_SIGNATURES_PAGE_SIZE (128) -#define USER_SIGNATURES_END (USER_SIGNATURES_START + USER_SIGNATURES_SIZE - 1) - -#define PROD_SIGNATURES_START (0x0000) -#define PROD_SIGNATURES_SIZE (54) -#define PROD_SIGNATURES_PAGE_SIZE (128) -#define PROD_SIGNATURES_END (PROD_SIGNATURES_START + PROD_SIGNATURES_SIZE - 1) - -#define FLASHSTART PROGMEM_START -#define FLASHEND PROGMEM_END -#define SPM_PAGESIZE 128 -#define RAMSTART INTERNAL_SRAM_START -#define RAMSIZE INTERNAL_SRAM_SIZE -#define RAMEND INTERNAL_SRAM_END -#define E2END EEPROM_END -#define E2PAGESIZE EEPROM_PAGE_SIZE - - -/* ========== Fuses ========== */ -#define FUSE_MEMORY_SIZE 7 - -/* Fuse Byte 0 Reserved */ - -/* Fuse Byte 1 */ -#define FUSE_WDP0 (unsigned char)~_BV(0) /* Watchdog Timeout Period Bit 0 */ -#define FUSE_WDP1 (unsigned char)~_BV(1) /* Watchdog Timeout Period Bit 1 */ -#define FUSE_WDP2 (unsigned char)~_BV(2) /* Watchdog Timeout Period Bit 2 */ -#define FUSE_WDP3 (unsigned char)~_BV(3) /* Watchdog Timeout Period Bit 3 */ -#define FUSE_WDWP0 (unsigned char)~_BV(4) /* Watchdog Window Timeout Period Bit 0 */ -#define FUSE_WDWP1 (unsigned char)~_BV(5) /* Watchdog Window Timeout Period Bit 1 */ -#define FUSE_WDWP2 (unsigned char)~_BV(6) /* Watchdog Window Timeout Period Bit 2 */ -#define FUSE_WDWP3 (unsigned char)~_BV(7) /* Watchdog Window Timeout Period Bit 3 */ -#define FUSE1_DEFAULT (0xFF) - -/* Fuse Byte 2 */ -#define FUSE_BODPD0 (unsigned char)~_BV(0) /* BOD Operation in Power-Down Mode Bit 0 */ -#define FUSE_BODPD1 (unsigned char)~_BV(1) /* BOD Operation in Power-Down Mode Bit 1 */ -#define FUSE_BOOTRST (unsigned char)~_BV(6) /* Boot Loader Section Reset Vector */ -#define FUSE2_DEFAULT (0xFF) - -/* Fuse Byte 3 Reserved */ - -/* Fuse Byte 4 */ -#define FUSE_WDLOCK (unsigned char)~_BV(1) /* Watchdog Timer Lock */ -#define FUSE_SUT0 (unsigned char)~_BV(2) /* Start-up Time Bit 0 */ -#define FUSE_SUT1 (unsigned char)~_BV(3) /* Start-up Time Bit 1 */ -#define FUSE_RSTDISBL (unsigned char)~_BV(4) /* External Reset Disable */ -#define FUSE4_DEFAULT (0xFF) - -/* Fuse Byte 5 */ -#define FUSE_BODLVL0 (unsigned char)~_BV(0) /* Brownout Detection Voltage Level Bit 0 */ -#define FUSE_BODLVL1 (unsigned char)~_BV(1) /* Brownout Detection Voltage Level Bit 1 */ -#define FUSE_BODLVL2 (unsigned char)~_BV(2) /* Brownout Detection Voltage Level Bit 2 */ -#define FUSE_EESAVE (unsigned char)~_BV(3) /* Preserve EEPROM Through Chip Erase */ -#define FUSE_BODACT0 (unsigned char)~_BV(4) /* BOD Operation in Active Mode Bit 0 */ -#define FUSE_BODACT1 (unsigned char)~_BV(5) /* BOD Operation in Active Mode Bit 1 */ -#define FUSE5_DEFAULT (0xFF) - -/* Fuse Byte 6 */ -#define FUSE_VALUE0 (unsigned char)~_BV(0) /* Port Pin Value Bit 0 */ -#define FUSE_VALUE1 (unsigned char)~_BV(1) /* Port Pin Value Bit 1 */ -#define FUSE_VALUE2 (unsigned char)~_BV(2) /* Port Pin Value Bit 2 */ -#define FUSE_VALUE3 (unsigned char)~_BV(3) /* Port Pin Value Bit 3 */ -#define FUSE_VALUE4 (unsigned char)~_BV(4) /* Port Pin Value Bit 4 */ -#define FUSE_VALUE5 (unsigned char)~_BV(5) /* Port Pin Value Bit 5 */ -#define FUSE_FDACT4 (unsigned char)~_BV(6) /* Fault Dectection Action on TC4 */ -#define FUSE_FDACT5 (unsigned char)~_BV(7) /* Fault Dectection Action on TC5 */ -#define FUSE6_DEFAULT (0xFF) - -/* ========== Lock Bits ========== */ -#define __LOCK_BITS_EXIST -#define __BOOT_LOCK_APPLICATION_TABLE_BITS_EXIST -#define __BOOT_LOCK_APPLICATION_BITS_EXIST -#define __BOOT_LOCK_BOOT_BITS_EXIST - -/* ========== Signature ========== */ -#define SIGNATURE_0 0x1E -#define SIGNATURE_1 0x93 -#define SIGNATURE_2 0x41 - -/* ========== Power Reduction Condition Definitions ========== */ - -/* PR.PRGEN */ -#define __AVR_HAVE_PRGEN (PR_XCL_bm|PR_RTC_bm|PR_EVSYS_bm|PR_EDMA_bm) -#define __AVR_HAVE_PRGEN_XCL -#define __AVR_HAVE_PRGEN_RTC -#define __AVR_HAVE_PRGEN_EVSYS -#define __AVR_HAVE_PRGEN_EDMA - -/* PR.PRPA */ -#define __AVR_HAVE_PRPA (PR_DAC_bm|PR_ADC_bm|PR_AC_bm) -#define __AVR_HAVE_PRPA_DAC -#define __AVR_HAVE_PRPA_ADC -#define __AVR_HAVE_PRPA_AC - -/* PR.PRPC */ -#define __AVR_HAVE_PRPC (PR_TWI_bm|PR_USART0_bm|PR_SPI_bm|PR_HIRES_bm|PR_TC5_bm|PR_TC4_bm) -#define __AVR_HAVE_PRPC_TWI -#define __AVR_HAVE_PRPC_USART0 -#define __AVR_HAVE_PRPC_SPI -#define __AVR_HAVE_PRPC_HIRES -#define __AVR_HAVE_PRPC_TC5 -#define __AVR_HAVE_PRPC_TC4 - -/* PR.PRPD */ -#define __AVR_HAVE_PRPD (PR_USART0_bm|PR_TC5_bm) -#define __AVR_HAVE_PRPD_USART0 -#define __AVR_HAVE_PRPD_TC5 - - -#endif /* #ifdef _AVR_ATXMEGA8E5_H_INCLUDED */ - diff --git a/arduino/hardware/tools/avr/avr/include/avr/lock.h b/arduino/hardware/tools/avr/avr/include/avr/lock.h deleted file mode 100644 index fa87655..0000000 --- a/arduino/hardware/tools/avr/avr/include/avr/lock.h +++ /dev/null @@ -1,239 +0,0 @@ -/* Copyright (c) 2007, Atmel Corporation - All rights reserved. - - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - * Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - * Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in - the documentation and/or other materials provided with the - distribution. - - * Neither the name of the copyright holders nor the names of - contributors may be used to endorse or promote products derived - from this software without specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. */ - -/* $Id$ */ - -/* avr/lock.h - Lock Bits API */ - -#ifndef _AVR_LOCK_H_ -#define _AVR_LOCK_H_ 1 - - -/** \file */ -/** \defgroup avr_lock : Lockbit Support - - \par Introduction - - The Lockbit API allows a user to specify the lockbit settings for the - specific AVR device they are compiling for. These lockbit settings will be - placed in a special section in the ELF output file, after linking. - - Programming tools can take advantage of the lockbit information embedded in - the ELF file, by extracting this information and determining if the lockbits - need to be programmed after programming the Flash and EEPROM memories. - This also allows a single ELF file to contain all the - information needed to program an AVR. - - To use the Lockbit API, include the header file, which in turn - automatically includes the individual I/O header file and the - file. These other two files provides everything necessary to set the AVR - lockbits. - - \par Lockbit API - - Each I/O header file may define up to 3 macros that controls what kinds - of lockbits are available to the user. - - If __LOCK_BITS_EXIST is defined, then two lock bits are available to the - user and 3 mode settings are defined for these two bits. - - If __BOOT_LOCK_BITS_0_EXIST is defined, then the two BLB0 lock bits are - available to the user and 4 mode settings are defined for these two bits. - - If __BOOT_LOCK_BITS_1_EXIST is defined, then the two BLB1 lock bits are - available to the user and 4 mode settings are defined for these two bits. - - If __BOOT_LOCK_APPLICATION_TABLE_BITS_EXIST is defined then two lock bits - are available to set the locking mode for the Application Table Section - (which is used in the XMEGA family). - - If __BOOT_LOCK_APPLICATION_BITS_EXIST is defined then two lock bits are - available to set the locking mode for the Application Section (which is used - in the XMEGA family). - - If __BOOT_LOCK_BOOT_BITS_EXIST is defined then two lock bits are available - to set the locking mode for the Boot Loader Section (which is used in the - XMEGA family). - - The AVR lockbit modes have inverted values, logical 1 for an unprogrammed - (disabled) bit and logical 0 for a programmed (enabled) bit. The defined - macros for each individual lock bit represent this in their definition by a - bit-wise inversion of a mask. For example, the LB_MODE_3 macro is defined - as: - \code - #define LB_MODE_3 (0xFC) -` \endcode - - To combine the lockbit mode macros together to represent a whole byte, - use the bitwise AND operator, like so: - \code - (LB_MODE_3 & BLB0_MODE_2) - \endcode - - also defines a macro that provides a default lockbit value: - LOCKBITS_DEFAULT which is defined to be 0xFF. - - See the AVR device specific datasheet for more details about these - lock bits and the available mode settings. - - A convenience macro, LOCKMEM, is defined as a GCC attribute for a - custom-named section of ".lock". - - A convenience macro, LOCKBITS, is defined that declares a variable, __lock, - of type unsigned char with the attribute defined by LOCKMEM. This variable - allows the end user to easily set the lockbit data. - - \note If a device-specific I/O header file has previously defined LOCKMEM, - then LOCKMEM is not redefined. If a device-specific I/O header file has - previously defined LOCKBITS, then LOCKBITS is not redefined. LOCKBITS is - currently known to be defined in the I/O header files for the XMEGA devices. - - \par API Usage Example - - Putting all of this together is easy: - - \code - #include - - LOCKBITS = (LB_MODE_1 & BLB0_MODE_3 & BLB1_MODE_4); - - int main(void) - { - return 0; - } - \endcode - - Or: - - \code - #include - - unsigned char __lock __attribute__((section (".lock"))) = - (LB_MODE_1 & BLB0_MODE_3 & BLB1_MODE_4); - - int main(void) - { - return 0; - } - \endcode - - - - However there are a number of caveats that you need to be aware of to - use this API properly. - - Be sure to include to get all of the definitions for the API. - The LOCKBITS macro defines a global variable to store the lockbit data. This - variable is assigned to its own linker section. Assign the desired lockbit - values immediately in the variable initialization. - - The .lock section in the ELF file will get its values from the initial - variable assignment ONLY. This means that you can NOT assign values to - this variable in functions and the new values will not be put into the - ELF .lock section. - - The global variable is declared in the LOCKBITS macro has two leading - underscores, which means that it is reserved for the "implementation", - meaning the library, so it will not conflict with a user-named variable. - - You must initialize the lockbit variable to some meaningful value, even - if it is the default value. This is because the lockbits default to a - logical 1, meaning unprogrammed. Normal uninitialized data defaults to all - locgial zeros. So it is vital that all lockbits are initialized, even with - default data. If they are not, then the lockbits may not programmed to the - desired settings and can possibly put your device into an unrecoverable - state. - - Be sure to have the -mmcu=device flag in your compile command line and - your linker command line to have the correct device selected and to have - the correct I/O header file included when you include . - - You can print out the contents of the .lock section in the ELF file by - using this command line: - \code - avr-objdump -s -j .lock - \endcode - -*/ - - -#if !(defined(__ASSEMBLER__) || defined(__DOXYGEN__)) - -#ifndef LOCKMEM -#define LOCKMEM __attribute__((__used__, __section__ (".lock"))) -#endif - -#ifndef LOCKBITS -#define LOCKBITS unsigned char __lock LOCKMEM -#endif - -/* Lock Bit Modes */ -#if defined(__LOCK_BITS_EXIST) -#define LB_MODE_1 (0xFF) -#define LB_MODE_2 (0xFE) -#define LB_MODE_3 (0xFC) -#endif - -#if defined(__BOOT_LOCK_BITS_0_EXIST) -#define BLB0_MODE_1 (0xFF) -#define BLB0_MODE_2 (0xFB) -#define BLB0_MODE_3 (0xF3) -#define BLB0_MODE_4 (0xF7) -#endif - -#if defined(__BOOT_LOCK_BITS_1_EXIST) -#define BLB1_MODE_1 (0xFF) -#define BLB1_MODE_2 (0xEF) -#define BLB1_MODE_3 (0xCF) -#define BLB1_MODE_4 (0xDF) -#endif - -#if defined(__BOOT_LOCK_APPLICATION_TABLE_BITS_EXIST) -#define BLBAT0 ~_BV(2) -#define BLBAT1 ~_BV(3) -#endif - -#if defined(__BOOT_LOCK_APPLICATION_BITS_EXIST) -#define BLBA0 ~_BV(4) -#define BLBA1 ~_BV(5) -#endif - -#if defined(__BOOT_LOCK_BOOT_BITS_EXIST) -#define BLBB0 ~_BV(6) -#define BLBB1 ~_BV(7) -#endif - - -#define LOCKBITS_DEFAULT (0xFF) - -#endif /* !(__ASSEMBLER || __DOXYGEN__) */ - - -#endif /* _AVR_LOCK_H_ */ diff --git a/arduino/hardware/tools/avr/avr/include/avr/parity.h b/arduino/hardware/tools/avr/avr/include/avr/parity.h deleted file mode 100644 index d7afd34..0000000 --- a/arduino/hardware/tools/avr/avr/include/avr/parity.h +++ /dev/null @@ -1,39 +0,0 @@ -/* Copyright (c) 2005 Joerg Wunsch - All rights reserved. - - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - * Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - * Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in - the documentation and/or other materials provided with the - distribution. - - * Neither the name of the copyright holders nor the names of - contributors may be used to endorse or promote products derived - from this software without specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. */ - -/* $Id$ */ - -#ifndef _AVR_PARITY_H_ -#define _AVR_PARITY_H_ - -#warning "This file has been moved to ." -#include - -#endif /* _AVR_PARITY_H_ */ diff --git a/arduino/hardware/tools/avr/avr/include/avr/pgmspace.h b/arduino/hardware/tools/avr/avr/include/avr/pgmspace.h deleted file mode 100644 index 5740740..0000000 --- a/arduino/hardware/tools/avr/avr/include/avr/pgmspace.h +++ /dev/null @@ -1,1791 +0,0 @@ -/* Copyright (c) 2002-2007 Marek Michalkiewicz - Copyright (c) 2006, Carlos Lamas - Copyright (c) 2009-2010, Jan Waclawek - All rights reserved. - - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - * Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - * Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in - the documentation and/or other materials provided with the - distribution. - * Neither the name of the copyright holders nor the names of - contributors may be used to endorse or promote products derived - from this software without specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. */ - -/* $Id$ */ - -/* - pgmspace.h - - Contributors: - Created by Marek Michalkiewicz - Eric B. Weddington - Wolfgang Haidinger (pgm_read_dword()) - Ivanov Anton (pgm_read_float()) - */ - -/** \file */ -/** \defgroup avr_pgmspace : Program Space Utilities - \code - #include - #include - \endcode - - The functions in this module provide interfaces for a program to access - data stored in program space (flash memory) of the device. In order to - use these functions, the target device must support either the \c LPM or - \c ELPM instructions. - - \note These functions are an attempt to provide some compatibility with - header files that come with IAR C, to make porting applications between - different compilers easier. This is not 100% compatibility though (GCC - does not have full support for multiple address spaces yet). - - \note If you are working with strings which are completely based in ram, - use the standard string functions described in \ref avr_string. - - \note If possible, put your constant tables in the lower 64 KB and use - pgm_read_byte_near() or pgm_read_word_near() instead of - pgm_read_byte_far() or pgm_read_word_far() since it is more efficient that - way, and you can still use the upper 64K for executable code. - All functions that are suffixed with a \c _P \e require their - arguments to be in the lower 64 KB of the flash ROM, as they do - not use ELPM instructions. This is normally not a big concern as - the linker setup arranges any program space constants declared - using the macros from this header file so they are placed right after - the interrupt vectors, and in front of any executable code. However, - it can become a problem if there are too many of these constants, or - for bootloaders on devices with more than 64 KB of ROM. - All these functions will not work in that situation. - - \note For Xmega devices, make sure the NVM controller - command register (\c NVM.CMD or \c NVM_CMD) is set to 0x00 (NOP) - before using any of these functions. -*/ - -#ifndef __PGMSPACE_H_ -#define __PGMSPACE_H_ 1 - -#ifndef __DOXYGEN__ -#define __need_size_t -#endif -#include -#include -#include - -#ifndef __DOXYGEN__ -#ifndef __ATTR_CONST__ -#define __ATTR_CONST__ __attribute__((__const__)) -#endif - -#ifndef __ATTR_PROGMEM__ -#define __ATTR_PROGMEM__ __attribute__((__progmem__)) -#endif - -#ifndef __ATTR_PURE__ -#define __ATTR_PURE__ __attribute__((__pure__)) -#endif -#endif /* !__DOXYGEN__ */ - -/** - \ingroup avr_pgmspace - \def PROGMEM - - Attribute to use in order to declare an object being located in - flash ROM. - */ -#define PROGMEM __ATTR_PROGMEM__ - -#ifdef __cplusplus -extern "C" { -#endif - -#if defined(__DOXYGEN__) -/* - * Doxygen doesn't grok the appended attribute syntax of - * GCC, and confuses the typedefs with function decls, so - * supply a doxygen-friendly view. - */ - -/** - \ingroup avr_pgmspace - \typedef prog_void - \note DEPRECATED - - This typedef is now deprecated because the usage of the __progmem__ - attribute on a type is not supported in GCC. However, the use of the - __progmem__ attribute on a variable declaration is supported, and this is - now the recommended usage. - - The typedef is only visible if the macro __PROG_TYPES_COMPAT__ - has been defined before including (either by a - \c \#define directive, or by a -D compiler option.) - - Type of a "void" object located in flash ROM. Does not make much - sense by itself, but can be used to declare a "void *" object in - flash ROM. -*/ -typedef void PROGMEM prog_void; - -/** - \ingroup avr_pgmspace - \typedef prog_char - \note DEPRECATED - - This typedef is now deprecated because the usage of the __progmem__ - attribute on a type is not supported in GCC. However, the use of the - __progmem__ attribute on a variable declaration is supported, and this is - now the recommended usage. - - The typedef is only visible if the macro __PROG_TYPES_COMPAT__ - has been defined before including (either by a - \c \#define directive, or by a -D compiler option.) - - Type of a "char" object located in flash ROM. -*/ -typedef char PROGMEM prog_char; - -/** - \ingroup avr_pgmspace - \typedef prog_uchar - \note DEPRECATED - - This typedef is now deprecated because the usage of the __progmem__ - attribute on a type is not supported in GCC. However, the use of the - __progmem__ attribute on a variable declaration is supported, and this is - now the recommended usage. - - The typedef is only visible if the macro __PROG_TYPES_COMPAT__ - has been defined before including (either by a - \c \#define directive, or by a -D compiler option.) - - Type of an "unsigned char" object located in flash ROM. -*/ -typedef unsigned char PROGMEM prog_uchar; - -/** - \ingroup avr_pgmspace - \typedef prog_int8_t - \note DEPRECATED - - This typedef is now deprecated because the usage of the __progmem__ - attribute on a type is not supported in GCC. However, the use of the - __progmem__ attribute on a variable declaration is supported, and this is - now the recommended usage. - - The typedef is only visible if the macro __PROG_TYPES_COMPAT__ - has been defined before including (either by a - \c \#define directive, or by a -D compiler option.) - - Type of an "int8_t" object located in flash ROM. -*/ -typedef int8_t PROGMEM prog_int8_t; - -/** - \ingroup avr_pgmspace - \typedef prog_uint8_t - \note DEPRECATED - - This typedef is now deprecated because the usage of the __progmem__ - attribute on a type is not supported in GCC. However, the use of the - __progmem__ attribute on a variable declaration is supported, and this is - now the recommended usage. - - The typedef is only visible if the macro __PROG_TYPES_COMPAT__ - has been defined before including (either by a - \c \#define directive, or by a -D compiler option.) - - Type of an "uint8_t" object located in flash ROM. -*/ -typedef uint8_t PROGMEM prog_uint8_t; - -/** - \ingroup avr_pgmspace - \typedef prog_int16_t - \note DEPRECATED - - This typedef is now deprecated because the usage of the __progmem__ - attribute on a type is not supported in GCC. However, the use of the - __progmem__ attribute on a variable declaration is supported, and this is - now the recommended usage. - - The typedef is only visible if the macro __PROG_TYPES_COMPAT__ - has been defined before including (either by a - \c \#define directive, or by a -D compiler option.) - - Type of an "int16_t" object located in flash ROM. -*/ -typedef int16_t PROGMEM prog_int16_t; - -/** - \ingroup avr_pgmspace - \typedef prog_uint16_t - \note DEPRECATED - - This typedef is now deprecated because the usage of the __progmem__ - attribute on a type is not supported in GCC. However, the use of the - __progmem__ attribute on a variable declaration is supported, and this is - now the recommended usage. - - The typedef is only visible if the macro __PROG_TYPES_COMPAT__ - has been defined before including (either by a - \c \#define directive, or by a -D compiler option.) - - Type of an "uint16_t" object located in flash ROM. -*/ -typedef uint16_t PROGMEM prog_uint16_t; - -/** - \ingroup avr_pgmspace - \typedef prog_int32_t - \note DEPRECATED - - This typedef is now deprecated because the usage of the __progmem__ - attribute on a type is not supported in GCC. However, the use of the - __progmem__ attribute on a variable declaration is supported, and this is - now the recommended usage. - - The typedef is only visible if the macro __PROG_TYPES_COMPAT__ - has been defined before including (either by a - \c \#define directive, or by a -D compiler option.) - - Type of an "int32_t" object located in flash ROM. -*/ -typedef int32_t PROGMEM prog_int32_t; - -/** - \ingroup avr_pgmspace - \typedef prog_uint32_t - \note DEPRECATED - - This typedef is now deprecated because the usage of the __progmem__ - attribute on a type is not supported in GCC. However, the use of the - __progmem__ attribute on a variable declaration is supported, and this is - now the recommended usage. - - The typedef is only visible if the macro __PROG_TYPES_COMPAT__ - has been defined before including (either by a - \c \#define directive, or by a -D compiler option.) - - Type of an "uint32_t" object located in flash ROM. -*/ -typedef uint32_t PROGMEM prog_uint32_t; - -/** - \ingroup avr_pgmspace - \typedef prog_int64_t - \note DEPRECATED - - This typedef is now deprecated because the usage of the __progmem__ - attribute on a type is not supported in GCC. However, the use of the - __progmem__ attribute on a variable declaration is supported, and this is - now the recommended usage. - - The typedef is only visible if the macro __PROG_TYPES_COMPAT__ - has been defined before including (either by a - \c \#define directive, or by a -D compiler option.) - - Type of an "int64_t" object located in flash ROM. - - \note This type is not available when the compiler - option -mint8 is in effect. -*/ -typedef int64_t PROGMEM prog_int64_t; - -/** - \ingroup avr_pgmspace - \typedef prog_uint64_t - \note DEPRECATED - - This typedef is now deprecated because the usage of the __progmem__ - attribute on a type is not supported in GCC. However, the use of the - __progmem__ attribute on a variable declaration is supported, and this is - now the recommended usage. - - The typedef is only visible if the macro __PROG_TYPES_COMPAT__ - has been defined before including (either by a - \c \#define directive, or by a -D compiler option.) - - Type of an "uint64_t" object located in flash ROM. - - \note This type is not available when the compiler - option -mint8 is in effect. -*/ -typedef uint64_t PROGMEM prog_uint64_t; - -/** \ingroup avr_pgmspace - \def PGM_P - - Used to declare a variable that is a pointer to a string in program - space. */ - -#ifndef PGM_P -#define PGM_P const char * -#endif - -/** \ingroup avr_pgmspace - \def PGM_VOID_P - - Used to declare a generic pointer to an object in program space. */ - -#ifndef PGM_VOID_P -#define PGM_VOID_P const void * -#endif - -#elif defined(__PROG_TYPES_COMPAT__) /* !DOXYGEN */ - -typedef void prog_void __attribute__((__progmem__,deprecated("prog_void type is deprecated."))); -typedef char prog_char __attribute__((__progmem__,deprecated("prog_char type is deprecated."))); -typedef unsigned char prog_uchar __attribute__((__progmem__,deprecated("prog_uchar type is deprecated."))); -typedef int8_t prog_int8_t __attribute__((__progmem__,deprecated("prog_int8_t type is deprecated."))); -typedef uint8_t prog_uint8_t __attribute__((__progmem__,deprecated("prog_uint8_t type is deprecated."))); -typedef int16_t prog_int16_t __attribute__((__progmem__,deprecated("prog_int16_t type is deprecated."))); -typedef uint16_t prog_uint16_t __attribute__((__progmem__,deprecated("prog_uint16_t type is deprecated."))); -typedef int32_t prog_int32_t __attribute__((__progmem__,deprecated("prog_int32_t type is deprecated."))); -typedef uint32_t prog_uint32_t __attribute__((__progmem__,deprecated("prog_uint32_t type is deprecated."))); -#if !__USING_MINT8 -typedef int64_t prog_int64_t __attribute__((__progmem__,deprecated("prog_int64_t type is deprecated."))); -typedef uint64_t prog_uint64_t __attribute__((__progmem__,deprecated("prog_uint64_t type is deprecated."))); -#endif - -#ifndef PGM_P -#define PGM_P const prog_char * -#endif - -#ifndef PGM_VOID_P -#define PGM_VOID_P const prog_void * -#endif - -#else /* !defined(__DOXYGEN__), !defined(__PROG_TYPES_COMPAT__) */ - -#ifndef PGM_P -#define PGM_P const char * -#endif - -#ifndef PGM_VOID_P -#define PGM_VOID_P const void * -#endif -#endif /* defined(__DOXYGEN__), defined(__PROG_TYPES_COMPAT__) */ - -/* Although in C, we can get away with just using __c, it does not work in - C++. We need to use &__c[0] to avoid the compiler puking. Dave Hylands - explaned it thusly, - - Let's suppose that we use PSTR("Test"). In this case, the type returned - by __c is a prog_char[5] and not a prog_char *. While these are - compatible, they aren't the same thing (especially in C++). The type - returned by &__c[0] is a prog_char *, which explains why it works - fine. */ - -#if defined(__DOXYGEN__) -/* - * The #define below is just a dummy that serves documentation - * purposes only. - */ -/** \ingroup avr_pgmspace - \def PSTR(s) - - Used to declare a static pointer to a string in program space. */ -# define PSTR(s) ((const PROGMEM char *)(s)) -#else /* !DOXYGEN */ -/* The real thing. */ -# define PSTR(s) (__extension__({static const char __c[] PROGMEM = (s); &__c[0];})) -#endif /* DOXYGEN */ - -#ifndef __DOXYGEN__ /* Internal macros, not documented. */ -#define __LPM_classic__(addr) \ -(__extension__({ \ - uint16_t __addr16 = (uint16_t)(addr); \ - uint8_t __result; \ - __asm__ __volatile__ \ - ( \ - "lpm" "\n\t" \ - "mov %0, r0" "\n\t" \ - : "=r" (__result) \ - : "z" (__addr16) \ - : "r0" \ - ); \ - __result; \ -})) - -#define __LPM_tiny__(addr) \ -(__extension__({ \ - uint16_t __addr16 = (uint16_t)(addr) + __AVR_TINY_PM_BASE_ADDRESS__; \ - uint8_t __result; \ - __asm__ \ - ( \ - "ld %0, z" "\n\t" \ - : "=r" (__result) \ - : "z" (__addr16) \ - ); \ - __result; \ -})) - -#define __LPM_enhanced__(addr) \ -(__extension__({ \ - uint16_t __addr16 = (uint16_t)(addr); \ - uint8_t __result; \ - __asm__ __volatile__ \ - ( \ - "lpm %0, Z" "\n\t" \ - : "=r" (__result) \ - : "z" (__addr16) \ - ); \ - __result; \ -})) - -#define __LPM_word_classic__(addr) \ -(__extension__({ \ - uint16_t __addr16 = (uint16_t)(addr); \ - uint16_t __result; \ - __asm__ __volatile__ \ - ( \ - "lpm" "\n\t" \ - "mov %A0, r0" "\n\t" \ - "adiw r30, 1" "\n\t" \ - "lpm" "\n\t" \ - "mov %B0, r0" "\n\t" \ - : "=r" (__result), "=z" (__addr16) \ - : "1" (__addr16) \ - : "r0" \ - ); \ - __result; \ -})) - -#define __LPM_word_tiny__(addr) \ -(__extension__({ \ - uint16_t __addr16 = (uint16_t)(addr) + __AVR_TINY_PM_BASE_ADDRESS__; \ - uint16_t __result; \ - __asm__ \ - ( \ - "ld %A0, z+" "\n\t" \ - "ld %B0, z" "\n\t" \ - : "=r" (__result), "=z" (__addr16) \ - : "1" (__addr16) \ - ); \ - __result; \ -})) - -#define __LPM_word_enhanced__(addr) \ -(__extension__({ \ - uint16_t __addr16 = (uint16_t)(addr); \ - uint16_t __result; \ - __asm__ __volatile__ \ - ( \ - "lpm %A0, Z+" "\n\t" \ - "lpm %B0, Z" "\n\t" \ - : "=r" (__result), "=z" (__addr16) \ - : "1" (__addr16) \ - ); \ - __result; \ -})) - -#define __LPM_dword_classic__(addr) \ -(__extension__({ \ - uint16_t __addr16 = (uint16_t)(addr); \ - uint32_t __result; \ - __asm__ __volatile__ \ - ( \ - "lpm" "\n\t" \ - "mov %A0, r0" "\n\t" \ - "adiw r30, 1" "\n\t" \ - "lpm" "\n\t" \ - "mov %B0, r0" "\n\t" \ - "adiw r30, 1" "\n\t" \ - "lpm" "\n\t" \ - "mov %C0, r0" "\n\t" \ - "adiw r30, 1" "\n\t" \ - "lpm" "\n\t" \ - "mov %D0, r0" "\n\t" \ - : "=r" (__result), "=z" (__addr16) \ - : "1" (__addr16) \ - : "r0" \ - ); \ - __result; \ -})) - -#define __LPM_dword_tiny__(addr) \ -(__extension__({ \ - uint16_t __addr16 = (uint16_t)(addr) + __AVR_TINY_PM_BASE_ADDRESS__; \ - uint32_t __result; \ - __asm__ \ - ( \ - "ld %A0, z+" "\n\t" \ - "ld %B0, z+" "\n\t" \ - "ld %C0, z+" "\n\t" \ - "ld %D0, z" "\n\t" \ - : "=r" (__result), "=z" (__addr16) \ - : "1" (__addr16) \ - ); \ - __result; \ -})) - -#define __LPM_dword_enhanced__(addr) \ -(__extension__({ \ - uint16_t __addr16 = (uint16_t)(addr); \ - uint32_t __result; \ - __asm__ __volatile__ \ - ( \ - "lpm %A0, Z+" "\n\t" \ - "lpm %B0, Z+" "\n\t" \ - "lpm %C0, Z+" "\n\t" \ - "lpm %D0, Z" "\n\t" \ - : "=r" (__result), "=z" (__addr16) \ - : "1" (__addr16) \ - ); \ - __result; \ -})) - -#define __LPM_float_classic__(addr) \ -(__extension__({ \ - uint16_t __addr16 = (uint16_t)(addr); \ - float __result; \ - __asm__ __volatile__ \ - ( \ - "lpm" "\n\t" \ - "mov %A0, r0" "\n\t" \ - "adiw r30, 1" "\n\t" \ - "lpm" "\n\t" \ - "mov %B0, r0" "\n\t" \ - "adiw r30, 1" "\n\t" \ - "lpm" "\n\t" \ - "mov %C0, r0" "\n\t" \ - "adiw r30, 1" "\n\t" \ - "lpm" "\n\t" \ - "mov %D0, r0" "\n\t" \ - : "=r" (__result), "=z" (__addr16) \ - : "1" (__addr16) \ - : "r0" \ - ); \ - __result; \ -})) - -#define __LPM_float_tiny__(addr) \ -(__extension__({ \ - uint16_t __addr16 = (uint16_t)(addr) + __AVR_TINY_PM_BASE_ADDRESS__; \ - float __result; \ - __asm__ \ - ( \ - "ld %A0, z+" "\n\t" \ - "ld %B0, z+" "\n\t" \ - "ld %C0, z+" "\n\t" \ - "ld %D0, z" "\n\t" \ - : "=r" (__result), "=z" (__addr16) \ - : "1" (__addr16) \ - ); \ - __result; \ -})) - -#define __LPM_float_enhanced__(addr) \ -(__extension__({ \ - uint16_t __addr16 = (uint16_t)(addr); \ - float __result; \ - __asm__ __volatile__ \ - ( \ - "lpm %A0, Z+" "\n\t" \ - "lpm %B0, Z+" "\n\t" \ - "lpm %C0, Z+" "\n\t" \ - "lpm %D0, Z" "\n\t" \ - : "=r" (__result), "=z" (__addr16) \ - : "1" (__addr16) \ - ); \ - __result; \ -})) - -#if defined (__AVR_HAVE_LPMX__) -#define __LPM(addr) __LPM_enhanced__(addr) -#define __LPM_word(addr) __LPM_word_enhanced__(addr) -#define __LPM_dword(addr) __LPM_dword_enhanced__(addr) -#define __LPM_float(addr) __LPM_float_enhanced__(addr) -/* -Macro to read data from program memory for avr tiny parts(tiny 4/5/9/10/20/40). -why: -- LPM instruction is not available in AVR_TINY instruction set. -- Programs are executed starting from address 0x0000 in program memory. -But it must be addressed starting from 0x4000 when accessed via data memory. -Reference: TINY device (ATTiny 4,5,9,10,20 and 40) datasheets -Bug: avrtc-536 -*/ -#elif defined (__AVR_TINY__) -#define __LPM(addr) __LPM_tiny__(addr) -#define __LPM_word(addr) __LPM_word_tiny__(addr) -#define __LPM_dword(addr) __LPM_dword_tiny__(addr) -#define __LPM_float(addr) __LPM_float_tiny__(addr) -#else -#define __LPM(addr) __LPM_classic__(addr) -#define __LPM_word(addr) __LPM_word_classic__(addr) -#define __LPM_dword(addr) __LPM_dword_classic__(addr) -#define __LPM_float(addr) __LPM_float_classic__(addr) -#endif - -#endif /* !__DOXYGEN__ */ - -/** \ingroup avr_pgmspace - \def pgm_read_byte_near(address_short) - Read a byte from the program space with a 16-bit (near) address. - \note The address is a byte address. - The address is in the program space. */ - -#define pgm_read_byte_near(address_short) __LPM((uint16_t)(address_short)) - -/** \ingroup avr_pgmspace - \def pgm_read_word_near(address_short) - Read a word from the program space with a 16-bit (near) address. - \note The address is a byte address. - The address is in the program space. */ - -#define pgm_read_word_near(address_short) __LPM_word((uint16_t)(address_short)) - -/** \ingroup avr_pgmspace - \def pgm_read_dword_near(address_short) - Read a double word from the program space with a 16-bit (near) address. - \note The address is a byte address. - The address is in the program space. */ - -#define pgm_read_dword_near(address_short) \ - __LPM_dword((uint16_t)(address_short)) - -/** \ingroup avr_pgmspace - \def pgm_read_float_near(address_short) - Read a float from the program space with a 16-bit (near) address. - \note The address is a byte address. - The address is in the program space. */ - -#define pgm_read_float_near(address_short) \ - __LPM_float((uint16_t)(address_short)) - -/** \ingroup avr_pgmspace - \def pgm_read_ptr_near(address_short) - Read a pointer from the program space with a 16-bit (near) address. - \note The address is a byte address. - The address is in the program space. */ - -#define pgm_read_ptr_near(address_short) \ - (void*)__LPM_word((uint16_t)(address_short)) - -#if defined(RAMPZ) || defined(__DOXYGEN__) - -/* Only for devices with more than 64K of program memory. - RAMPZ must be defined (see iom103.h, iom128.h). -*/ - -/* The classic functions are needed for ATmega103. */ -#ifndef __DOXYGEN__ /* These are internal macros, avoid "is - not documented" warnings. */ -#define __ELPM_classic__(addr) \ -(__extension__({ \ - uint32_t __addr32 = (uint32_t)(addr); \ - uint8_t __result; \ - __asm__ __volatile__ \ - ( \ - "out %2, %C1" "\n\t" \ - "mov r31, %B1" "\n\t" \ - "mov r30, %A1" "\n\t" \ - "elpm" "\n\t" \ - "mov %0, r0" "\n\t" \ - : "=r" (__result) \ - : "r" (__addr32), \ - "I" (_SFR_IO_ADDR(RAMPZ)) \ - : "r0", "r30", "r31" \ - ); \ - __result; \ -})) - -#define __ELPM_enhanced__(addr) \ -(__extension__({ \ - uint32_t __addr32 = (uint32_t)(addr); \ - uint8_t __result; \ - __asm__ __volatile__ \ - ( \ - "out %2, %C1" "\n\t" \ - "movw r30, %1" "\n\t" \ - "elpm %0, Z+" "\n\t" \ - : "=r" (__result) \ - : "r" (__addr32), \ - "I" (_SFR_IO_ADDR(RAMPZ)) \ - : "r30", "r31" \ - ); \ - __result; \ -})) - -#define __ELPM_xmega__(addr) \ -(__extension__({ \ - uint32_t __addr32 = (uint32_t)(addr); \ - uint8_t __result; \ - __asm__ __volatile__ \ - ( \ - "in __tmp_reg__, %2" "\n\t" \ - "out %2, %C1" "\n\t" \ - "movw r30, %1" "\n\t" \ - "elpm %0, Z+" "\n\t" \ - "out %2, __tmp_reg__" \ - : "=r" (__result) \ - : "r" (__addr32), \ - "I" (_SFR_IO_ADDR(RAMPZ)) \ - : "r30", "r31" \ - ); \ - __result; \ -})) - -#define __ELPM_word_classic__(addr) \ -(__extension__({ \ - uint32_t __addr32 = (uint32_t)(addr); \ - uint16_t __result; \ - __asm__ __volatile__ \ - ( \ - "out %2, %C1" "\n\t" \ - "mov r31, %B1" "\n\t" \ - "mov r30, %A1" "\n\t" \ - "elpm" "\n\t" \ - "mov %A0, r0" "\n\t" \ - "in r0, %2" "\n\t" \ - "adiw r30, 1" "\n\t" \ - "adc r0, __zero_reg__" "\n\t" \ - "out %2, r0" "\n\t" \ - "elpm" "\n\t" \ - "mov %B0, r0" "\n\t" \ - : "=r" (__result) \ - : "r" (__addr32), \ - "I" (_SFR_IO_ADDR(RAMPZ)) \ - : "r0", "r30", "r31" \ - ); \ - __result; \ -})) - -#define __ELPM_word_enhanced__(addr) \ -(__extension__({ \ - uint32_t __addr32 = (uint32_t)(addr); \ - uint16_t __result; \ - __asm__ __volatile__ \ - ( \ - "out %2, %C1" "\n\t" \ - "movw r30, %1" "\n\t" \ - "elpm %A0, Z+" "\n\t" \ - "elpm %B0, Z" "\n\t" \ - : "=r" (__result) \ - : "r" (__addr32), \ - "I" (_SFR_IO_ADDR(RAMPZ)) \ - : "r30", "r31" \ - ); \ - __result; \ -})) - -#define __ELPM_word_xmega__(addr) \ -(__extension__({ \ - uint32_t __addr32 = (uint32_t)(addr); \ - uint16_t __result; \ - __asm__ __volatile__ \ - ( \ - "in __tmp_reg__, %2" "\n\t" \ - "out %2, %C1" "\n\t" \ - "movw r30, %1" "\n\t" \ - "elpm %A0, Z+" "\n\t" \ - "elpm %B0, Z" "\n\t" \ - "out %2, __tmp_reg__" \ - : "=r" (__result) \ - : "r" (__addr32), \ - "I" (_SFR_IO_ADDR(RAMPZ)) \ - : "r30", "r31" \ - ); \ - __result; \ -})) - -#define __ELPM_dword_classic__(addr) \ -(__extension__({ \ - uint32_t __addr32 = (uint32_t)(addr); \ - uint32_t __result; \ - __asm__ __volatile__ \ - ( \ - "out %2, %C1" "\n\t" \ - "mov r31, %B1" "\n\t" \ - "mov r30, %A1" "\n\t" \ - "elpm" "\n\t" \ - "mov %A0, r0" "\n\t" \ - "in r0, %2" "\n\t" \ - "adiw r30, 1" "\n\t" \ - "adc r0, __zero_reg__" "\n\t" \ - "out %2, r0" "\n\t" \ - "elpm" "\n\t" \ - "mov %B0, r0" "\n\t" \ - "in r0, %2" "\n\t" \ - "adiw r30, 1" "\n\t" \ - "adc r0, __zero_reg__" "\n\t" \ - "out %2, r0" "\n\t" \ - "elpm" "\n\t" \ - "mov %C0, r0" "\n\t" \ - "in r0, %2" "\n\t" \ - "adiw r30, 1" "\n\t" \ - "adc r0, __zero_reg__" "\n\t" \ - "out %2, r0" "\n\t" \ - "elpm" "\n\t" \ - "mov %D0, r0" "\n\t" \ - : "=r" (__result) \ - : "r" (__addr32), \ - "I" (_SFR_IO_ADDR(RAMPZ)) \ - : "r0", "r30", "r31" \ - ); \ - __result; \ -})) - -#define __ELPM_dword_enhanced__(addr) \ -(__extension__({ \ - uint32_t __addr32 = (uint32_t)(addr); \ - uint32_t __result; \ - __asm__ __volatile__ \ - ( \ - "out %2, %C1" "\n\t" \ - "movw r30, %1" "\n\t" \ - "elpm %A0, Z+" "\n\t" \ - "elpm %B0, Z+" "\n\t" \ - "elpm %C0, Z+" "\n\t" \ - "elpm %D0, Z" "\n\t" \ - : "=r" (__result) \ - : "r" (__addr32), \ - "I" (_SFR_IO_ADDR(RAMPZ)) \ - : "r30", "r31" \ - ); \ - __result; \ -})) - -#define __ELPM_dword_xmega__(addr) \ -(__extension__({ \ - uint32_t __addr32 = (uint32_t)(addr); \ - uint32_t __result; \ - __asm__ __volatile__ \ - ( \ - "in __tmp_reg__, %2" "\n\t" \ - "out %2, %C1" "\n\t" \ - "movw r30, %1" "\n\t" \ - "elpm %A0, Z+" "\n\t" \ - "elpm %B0, Z+" "\n\t" \ - "elpm %C0, Z+" "\n\t" \ - "elpm %D0, Z" "\n\t" \ - "out %2, __tmp_reg__" \ - : "=r" (__result) \ - : "r" (__addr32), \ - "I" (_SFR_IO_ADDR(RAMPZ)) \ - : "r30", "r31" \ - ); \ - __result; \ -})) - -#define __ELPM_float_classic__(addr) \ -(__extension__({ \ - uint32_t __addr32 = (uint32_t)(addr); \ - float __result; \ - __asm__ __volatile__ \ - ( \ - "out %2, %C1" "\n\t" \ - "mov r31, %B1" "\n\t" \ - "mov r30, %A1" "\n\t" \ - "elpm" "\n\t" \ - "mov %A0, r0" "\n\t" \ - "in r0, %2" "\n\t" \ - "adiw r30, 1" "\n\t" \ - "adc r0, __zero_reg__" "\n\t" \ - "out %2, r0" "\n\t" \ - "elpm" "\n\t" \ - "mov %B0, r0" "\n\t" \ - "in r0, %2" "\n\t" \ - "adiw r30, 1" "\n\t" \ - "adc r0, __zero_reg__" "\n\t" \ - "out %2, r0" "\n\t" \ - "elpm" "\n\t" \ - "mov %C0, r0" "\n\t" \ - "in r0, %2" "\n\t" \ - "adiw r30, 1" "\n\t" \ - "adc r0, __zero_reg__" "\n\t" \ - "out %2, r0" "\n\t" \ - "elpm" "\n\t" \ - "mov %D0, r0" "\n\t" \ - : "=r" (__result) \ - : "r" (__addr32), \ - "I" (_SFR_IO_ADDR(RAMPZ)) \ - : "r0", "r30", "r31" \ - ); \ - __result; \ -})) - -#define __ELPM_float_enhanced__(addr) \ -(__extension__({ \ - uint32_t __addr32 = (uint32_t)(addr); \ - float __result; \ - __asm__ __volatile__ \ - ( \ - "out %2, %C1" "\n\t" \ - "movw r30, %1" "\n\t" \ - "elpm %A0, Z+" "\n\t" \ - "elpm %B0, Z+" "\n\t" \ - "elpm %C0, Z+" "\n\t" \ - "elpm %D0, Z" "\n\t" \ - : "=r" (__result) \ - : "r" (__addr32), \ - "I" (_SFR_IO_ADDR(RAMPZ)) \ - : "r30", "r31" \ - ); \ - __result; \ -})) - -#define __ELPM_float_xmega__(addr) \ -(__extension__({ \ - uint32_t __addr32 = (uint32_t)(addr); \ - float __result; \ - __asm__ __volatile__ \ - ( \ - "in __tmp_reg__, %2" "\n\t" \ - "out %2, %C1" "\n\t" \ - "movw r30, %1" "\n\t" \ - "elpm %A0, Z+" "\n\t" \ - "elpm %B0, Z+" "\n\t" \ - "elpm %C0, Z+" "\n\t" \ - "elpm %D0, Z" "\n\t" \ - "out %2, __tmp_reg__" \ - : "=r" (__result) \ - : "r" (__addr32), \ - "I" (_SFR_IO_ADDR(RAMPZ)) \ - : "r30", "r31" \ - ); \ - __result; \ -})) - -/* -Check for architectures that implement RAMPD (avrxmega5, avrxmega7) -as they need to save/restore RAMPZ for ELPM macros so it does -not interfere with data accesses. -*/ -#if defined (__AVR_HAVE_RAMPD__) - -#define __ELPM(addr) __ELPM_xmega__(addr) -#define __ELPM_word(addr) __ELPM_word_xmega__(addr) -#define __ELPM_dword(addr) __ELPM_dword_xmega__(addr) -#define __ELPM_float(addr) __ELPM_float_xmega__(addr) - -#else - -#if defined (__AVR_HAVE_LPMX__) - -#define __ELPM(addr) __ELPM_enhanced__(addr) -#define __ELPM_word(addr) __ELPM_word_enhanced__(addr) -#define __ELPM_dword(addr) __ELPM_dword_enhanced__(addr) -#define __ELPM_float(addr) __ELPM_float_enhanced__(addr) - -#else - -#define __ELPM(addr) __ELPM_classic__(addr) -#define __ELPM_word(addr) __ELPM_word_classic__(addr) -#define __ELPM_dword(addr) __ELPM_dword_classic__(addr) -#define __ELPM_float(addr) __ELPM_float_classic__(addr) - -#endif /* __AVR_HAVE_LPMX__ */ - -#endif /* __AVR_HAVE_RAMPD__ */ - -#endif /* !__DOXYGEN__ */ - -/** \ingroup avr_pgmspace - \def pgm_read_byte_far(address_long) - Read a byte from the program space with a 32-bit (far) address. - - \note The address is a byte address. - The address is in the program space. */ - -#define pgm_read_byte_far(address_long) __ELPM((uint32_t)(address_long)) - -/** \ingroup avr_pgmspace - \def pgm_read_word_far(address_long) - Read a word from the program space with a 32-bit (far) address. - - \note The address is a byte address. - The address is in the program space. */ - -#define pgm_read_word_far(address_long) __ELPM_word((uint32_t)(address_long)) - -/** \ingroup avr_pgmspace - \def pgm_read_dword_far(address_long) - Read a double word from the program space with a 32-bit (far) address. - - \note The address is a byte address. - The address is in the program space. */ - -#define pgm_read_dword_far(address_long) __ELPM_dword((uint32_t)(address_long)) - -/** \ingroup avr_pgmspace - \def pgm_read_float_far(address_long) - Read a float from the program space with a 32-bit (far) address. - - \note The address is a byte address. - The address is in the program space. */ - -#define pgm_read_float_far(address_long) __ELPM_float((uint32_t)(address_long)) - -/** \ingroup avr_pgmspace - \def pgm_read_ptr_far(address_long) - Read a pointer from the program space with a 32-bit (far) address. - - \note The address is a byte address. - The address is in the program space. */ - -#define pgm_read_ptr_far(address_long) (void*)__ELPM_word((uint32_t)(address_long)) - -#endif /* RAMPZ or __DOXYGEN__ */ - -/** \ingroup avr_pgmspace - \def pgm_read_byte(address_short) - Read a byte from the program space with a 16-bit (near) address. - - \note The address is a byte address. - The address is in the program space. */ - -#define pgm_read_byte(address_short) pgm_read_byte_near(address_short) - -/** \ingroup avr_pgmspace - \def pgm_read_word(address_short) - Read a word from the program space with a 16-bit (near) address. - - \note The address is a byte address. - The address is in the program space. */ - -#define pgm_read_word(address_short) pgm_read_word_near(address_short) - -/** \ingroup avr_pgmspace - \def pgm_read_dword(address_short) - Read a double word from the program space with a 16-bit (near) address. - - \note The address is a byte address. - The address is in the program space. */ - -#define pgm_read_dword(address_short) pgm_read_dword_near(address_short) - -/** \ingroup avr_pgmspace - \def pgm_read_float(address_short) - Read a float from the program space with a 16-bit (near) address. - - \note The address is a byte address. - The address is in the program space. */ - -#define pgm_read_float(address_short) pgm_read_float_near(address_short) - -/** \ingroup avr_pgmspace - \def pgm_read_ptr(address_short) - Read a pointer from the program space with a 16-bit (near) address. - - \note The address is a byte address. - The address is in the program space. */ - -#define pgm_read_ptr(address_short) pgm_read_ptr_near(address_short) - -/** \ingroup avr_pgmspace - \def pgm_get_far_address(var) - - This macro facilitates the obtention of a 32 bit "far" pointer (only 24 bits - used) to data even passed the 64KB limit for the 16 bit ordinary pointer. It - is similar to the '&' operator, with some limitations. - - Comments: - - - The overhead is minimal and it's mainly due to the 32 bit size operation. - - - 24 bit sizes guarantees the code compatibility for use in future devices. - - - hh8() is an undocumented feature but seems to give the third significant byte - of a 32 bit data and accepts symbols, complementing the functionality of hi8() - and lo8(). There is not an equivalent assembler function to get the high - significant byte. - - - 'var' has to be resolved at linking time as an existing symbol, i.e, a simple - type variable name, an array name (not an indexed element of the array, if the - index is a constant the compiler does not complain but fails to get the address - if optimization is enabled), a struct name or a struct field name, a function - identifier, a linker defined identifier,... - - - The returned value is the identifier's VMA (virtual memory address) determined - by the linker and falls in the corresponding memory region. The AVR Harvard - architecture requires non overlapping VMA areas for the multiple address spaces - in the processor: Flash ROM, RAM, and EEPROM. Typical offset for this are - 0x00000000, 0x00800xx0, and 0x00810000 respectively, derived from the linker - script used and linker options. The value returned can be seen then as a - universal pointer. -*/ - -#define pgm_get_far_address(var) \ -({ \ - uint_farptr_t tmp; \ - \ - __asm__ __volatile__( \ - \ - "ldi %A0, lo8(%1)" "\n\t" \ - "ldi %B0, hi8(%1)" "\n\t" \ - "ldi %C0, hh8(%1)" "\n\t" \ - "clr %D0" "\n\t" \ - : \ - "=d" (tmp) \ - : \ - "p" (&(var)) \ - ); \ - tmp; \ -}) - - - -/** \ingroup avr_pgmspace - \fn const void * memchr_P(const void *s, int val, size_t len) - \brief Scan flash memory for a character. - - The memchr_P() function scans the first \p len bytes of the flash - memory area pointed to by \p s for the character \p val. The first - byte to match \p val (interpreted as an unsigned character) stops - the operation. - - \return The memchr_P() function returns a pointer to the matching - byte or \c NULL if the character does not occur in the given memory - area. */ -extern const void * memchr_P(const void *, int __val, size_t __len) __ATTR_CONST__; - -/** \ingroup avr_pgmspace - \fn int memcmp_P(const void *s1, const void *s2, size_t len) - \brief Compare memory areas - - The memcmp_P() function compares the first \p len bytes of the memory - areas \p s1 and flash \p s2. The comparision is performed using unsigned - char operations. - - \returns The memcmp_P() function returns an integer less than, equal - to, or greater than zero if the first \p len bytes of \p s1 is found, - respectively, to be less than, to match, or be greater than the first - \p len bytes of \p s2. */ -extern int memcmp_P(const void *, const void *, size_t) __ATTR_PURE__; - -/** \ingroup avr_pgmspace - \fn void *memccpy_P (void *dest, const void *src, int val, size_t len) - - This function is similar to memccpy() except that \p src is pointer - to a string in program space. */ -extern void *memccpy_P(void *, const void *, int __val, size_t); - -/** \ingroup avr_pgmspace - \fn void *memcpy_P(void *dest, const void *src, size_t n) - - The memcpy_P() function is similar to memcpy(), except the src string - resides in program space. - - \returns The memcpy_P() function returns a pointer to dest. */ -extern void *memcpy_P(void *, const void *, size_t); - -/** \ingroup avr_pgmspace - \fn void *memmem_P(const void *s1, size_t len1, const void *s2, size_t len2) - - The memmem_P() function is similar to memmem() except that \p s2 is - pointer to a string in program space. */ -extern void *memmem_P(const void *, size_t, const void *, size_t) __ATTR_PURE__; - -/** \ingroup avr_pgmspace - \fn const void +memrchr_P(const void *src, int val, size_t len) - - The memrchr_P() function is like the memchr_P() function, except - that it searches backwards from the end of the \p len bytes pointed - to by \p src instead of forwards from the front. (Glibc, GNU extension.) - - \return The memrchr_P() function returns a pointer to the matching - byte or \c NULL if the character does not occur in the given memory - area. */ -extern const void * memrchr_P(const void *, int __val, size_t __len) __ATTR_CONST__; - -/** \ingroup avr_pgmspace - \fn char *strcat_P(char *dest, const char *src) - - The strcat_P() function is similar to strcat() except that the \e src - string must be located in program space (flash). - - \returns The strcat() function returns a pointer to the resulting string - \e dest. */ -extern char *strcat_P(char *, const char *); - -/** \ingroup avr_pgmspace - \fn const char *strchr_P(const char *s, int val) - \brief Locate character in program space string. - - The strchr_P() function locates the first occurrence of \p val - (converted to a char) in the string pointed to by \p s in program - space. The terminating null character is considered to be part of - the string. - - The strchr_P() function is similar to strchr() except that \p s is - pointer to a string in program space. - - \returns The strchr_P() function returns a pointer to the matched - character or \c NULL if the character is not found. */ -extern const char * strchr_P(const char *, int __val) __ATTR_CONST__; - -/** \ingroup avr_pgmspace - \fn const char *strchrnul_P(const char *s, int c) - - The strchrnul_P() function is like strchr_P() except that if \p c is - not found in \p s, then it returns a pointer to the null byte at the - end of \p s, rather than \c NULL. (Glibc, GNU extension.) - - \return The strchrnul_P() function returns a pointer to the matched - character, or a pointer to the null byte at the end of \p s (i.e., - \c s+strlen(s)) if the character is not found. */ -extern const char * strchrnul_P(const char *, int __val) __ATTR_CONST__; - -/** \ingroup avr_pgmspace - \fn int strcmp_P(const char *s1, const char *s2) - - The strcmp_P() function is similar to strcmp() except that \p s2 is - pointer to a string in program space. - - \returns The strcmp_P() function returns an integer less than, equal - to, or greater than zero if \p s1 is found, respectively, to be less - than, to match, or be greater than \p s2. A consequence of the - ordering used by strcmp_P() is that if \p s1 is an initial substring - of \p s2, then \p s1 is considered to be "less than" \p s2. */ -extern int strcmp_P(const char *, const char *) __ATTR_PURE__; - -/** \ingroup avr_pgmspace - \fn char *strcpy_P(char *dest, const char *src) - - The strcpy_P() function is similar to strcpy() except that src is a - pointer to a string in program space. - - \returns The strcpy_P() function returns a pointer to the destination - string dest. */ -extern char *strcpy_P(char *, const char *); - -/** \ingroup avr_pgmspace - \fn int strcasecmp_P(const char *s1, const char *s2) - \brief Compare two strings ignoring case. - - The strcasecmp_P() function compares the two strings \p s1 and \p s2, - ignoring the case of the characters. - - \param s1 A pointer to a string in the devices SRAM. - \param s2 A pointer to a string in the devices Flash. - - \returns The strcasecmp_P() function returns an integer less than, - equal to, or greater than zero if \p s1 is found, respectively, to - be less than, to match, or be greater than \p s2. A consequence of - the ordering used by strcasecmp_P() is that if \p s1 is an initial - substring of \p s2, then \p s1 is considered to be "less than" \p s2. */ -extern int strcasecmp_P(const char *, const char *) __ATTR_PURE__; - -/** \ingroup avr_pgmspace - \fn char *strcasestr_P(const char *s1, const char *s2) - - This funtion is similar to strcasestr() except that \p s2 is pointer - to a string in program space. */ -extern char *strcasestr_P(const char *, const char *) __ATTR_PURE__; - -/** \ingroup avr_pgmspace - \fn size_t strcspn_P(const char *s, const char *reject) - - The strcspn_P() function calculates the length of the initial segment - of \p s which consists entirely of characters not in \p reject. This - function is similar to strcspn() except that \p reject is a pointer - to a string in program space. - - \return The strcspn_P() function returns the number of characters in - the initial segment of \p s which are not in the string \p reject. - The terminating zero is not considered as a part of string. */ -extern size_t strcspn_P(const char *__s, const char * __reject) __ATTR_PURE__; - -/** \ingroup avr_pgmspace - \fn size_t strlcat_P(char *dst, const char *src, size_t siz) - \brief Concatenate two strings. - - The strlcat_P() function is similar to strlcat(), except that the \p src - string must be located in program space (flash). - - Appends \p src to string \p dst of size \p siz (unlike strncat(), - \p siz is the full size of \p dst, not space left). At most \p siz-1 - characters will be copied. Always NULL terminates (unless \p siz <= - \p strlen(dst)). - - \returns The strlcat_P() function returns strlen(src) + MIN(siz, - strlen(initial dst)). If retval >= siz, truncation occurred. */ -extern size_t strlcat_P (char *, const char *, size_t ); - -/** \ingroup avr_pgmspace - \fn size_t strlcpy_P(char *dst, const char *src, size_t siz) - \brief Copy a string from progmem to RAM. - - Copy \p src to string \p dst of size \p siz. At most \p siz-1 - characters will be copied. Always NULL terminates (unless \p siz == 0). - The strlcpy_P() function is similar to strlcpy() except that the - \p src is pointer to a string in memory space. - - \returns The strlcpy_P() function returns strlen(src). If - retval >= siz, truncation occurred. */ -extern size_t strlcpy_P (char *, const char *, size_t ); - -/** \ingroup avr_pgmspace - \fn size_t strnlen_P(const char *src, size_t len) - \brief Determine the length of a fixed-size string. - - The strnlen_P() function is similar to strnlen(), except that \c src is a - pointer to a string in program space. - - \returns The strnlen_P function returns strlen_P(src), if that is less than - \c len, or \c len if there is no '\\0' character among the first \c len - characters pointed to by \c src. */ -extern size_t strnlen_P(const char *, size_t) __ATTR_CONST__; /* program memory can't change */ - -/** \ingroup avr_pgmspace - \fn int strncmp_P(const char *s1, const char *s2, size_t n) - - The strncmp_P() function is similar to strcmp_P() except it only compares - the first (at most) n characters of s1 and s2. - - \returns The strncmp_P() function returns an integer less than, equal to, - or greater than zero if s1 (or the first n bytes thereof) is found, - respectively, to be less than, to match, or be greater than s2. */ -extern int strncmp_P(const char *, const char *, size_t) __ATTR_PURE__; - -/** \ingroup avr_pgmspace - \fn int strncasecmp_P(const char *s1, const char *s2, size_t n) - \brief Compare two strings ignoring case. - - The strncasecmp_P() function is similar to strcasecmp_P(), except it - only compares the first \p n characters of \p s1. - - \param s1 A pointer to a string in the devices SRAM. - \param s2 A pointer to a string in the devices Flash. - \param n The maximum number of bytes to compare. - - \returns The strncasecmp_P() function returns an integer less than, - equal to, or greater than zero if \p s1 (or the first \p n bytes - thereof) is found, respectively, to be less than, to match, or be - greater than \p s2. A consequence of the ordering used by - strncasecmp_P() is that if \p s1 is an initial substring of \p s2, - then \p s1 is considered to be "less than" \p s2. */ -extern int strncasecmp_P(const char *, const char *, size_t) __ATTR_PURE__; - -/** \ingroup avr_pgmspace - \fn char *strncat_P(char *dest, const char *src, size_t len) - \brief Concatenate two strings. - - The strncat_P() function is similar to strncat(), except that the \e src - string must be located in program space (flash). - - \returns The strncat_P() function returns a pointer to the resulting string - dest. */ -extern char *strncat_P(char *, const char *, size_t); - -/** \ingroup avr_pgmspace - \fn char *strncpy_P(char *dest, const char *src, size_t n) - - The strncpy_P() function is similar to strcpy_P() except that not more - than n bytes of src are copied. Thus, if there is no null byte among the - first n bytes of src, the result will not be null-terminated. - - In the case where the length of src is less than that of n, the remainder - of dest will be padded with nulls. - - \returns The strncpy_P() function returns a pointer to the destination - string dest. */ -extern char *strncpy_P(char *, const char *, size_t); - -/** \ingroup avr_pgmspace - \fn char *strpbrk_P(const char *s, const char *accept) - - The strpbrk_P() function locates the first occurrence in the string - \p s of any of the characters in the flash string \p accept. This - function is similar to strpbrk() except that \p accept is a pointer - to a string in program space. - - \return The strpbrk_P() function returns a pointer to the character - in \p s that matches one of the characters in \p accept, or \c NULL - if no such character is found. The terminating zero is not considered - as a part of string: if one or both args are empty, the result will - \c NULL. */ -extern char *strpbrk_P(const char *__s, const char * __accept) __ATTR_PURE__; - -/** \ingroup avr_pgmspace - \fn const char *strrchr_P(const char *s, int val) - \brief Locate character in string. - - The strrchr_P() function returns a pointer to the last occurrence of - the character \p val in the flash string \p s. - - \return The strrchr_P() function returns a pointer to the matched - character or \c NULL if the character is not found. */ -extern const char * strrchr_P(const char *, int __val) __ATTR_CONST__; - -/** \ingroup avr_pgmspace - \fn char *strsep_P(char **sp, const char *delim) - \brief Parse a string into tokens. - - The strsep_P() function locates, in the string referenced by \p *sp, - the first occurrence of any character in the string \p delim (or the - terminating '\\0' character) and replaces it with a '\\0'. The - location of the next character after the delimiter character (or \c - NULL, if the end of the string was reached) is stored in \p *sp. An - ``empty'' field, i.e. one caused by two adjacent delimiter - characters, can be detected by comparing the location referenced by - the pointer returned in \p *sp to '\\0'. This function is similar to - strsep() except that \p delim is a pointer to a string in program - space. - - \return The strsep_P() function returns a pointer to the original - value of \p *sp. If \p *sp is initially \c NULL, strsep_P() returns - \c NULL. */ -extern char *strsep_P(char **__sp, const char * __delim); - -/** \ingroup avr_pgmspace - \fn size_t strspn_P(const char *s, const char *accept) - - The strspn_P() function calculates the length of the initial segment - of \p s which consists entirely of characters in \p accept. This - function is similar to strspn() except that \p accept is a pointer - to a string in program space. - - \return The strspn_P() function returns the number of characters in - the initial segment of \p s which consist only of characters from \p - accept. The terminating zero is not considered as a part of string. */ -extern size_t strspn_P(const char *__s, const char * __accept) __ATTR_PURE__; - -/** \ingroup avr_pgmspace - \fn char *strstr_P(const char *s1, const char *s2) - \brief Locate a substring. - - The strstr_P() function finds the first occurrence of the substring - \p s2 in the string \p s1. The terminating '\\0' characters are not - compared. The strstr_P() function is similar to strstr() except that - \p s2 is pointer to a string in program space. - - \returns The strstr_P() function returns a pointer to the beginning - of the substring, or NULL if the substring is not found. If \p s2 - points to a string of zero length, the function returns \p s1. */ -extern char *strstr_P(const char *, const char *) __ATTR_PURE__; - -/** \ingroup avr_pgmspace - \fn char *strtok_P(char *s, const char * delim) - \brief Parses the string into tokens. - - strtok_P() parses the string \p s into tokens. The first call to - strtok_P() should have \p s as its first argument. Subsequent calls - should have the first argument set to NULL. If a token ends with a - delimiter, this delimiting character is overwritten with a '\\0' and a - pointer to the next character is saved for the next call to strtok_P(). - The delimiter string \p delim may be different for each call. - - The strtok_P() function is similar to strtok() except that \p delim - is pointer to a string in program space. - - \returns The strtok_P() function returns a pointer to the next token or - NULL when no more tokens are found. - - \note strtok_P() is NOT reentrant. For a reentrant version of this - function see strtok_rP(). - */ -extern char *strtok_P(char *__s, const char * __delim); - -/** \ingroup avr_pgmspace - \fn char *strtok_rP (char *string, const char *delim, char **last) - \brief Parses string into tokens. - - The strtok_rP() function parses \p string into tokens. The first call to - strtok_rP() should have string as its first argument. Subsequent calls - should have the first argument set to NULL. If a token ends with a - delimiter, this delimiting character is overwritten with a '\\0' and a - pointer to the next character is saved for the next call to strtok_rP(). - The delimiter string \p delim may be different for each call. \p last is - a user allocated char* pointer. It must be the same while parsing the - same string. strtok_rP() is a reentrant version of strtok_P(). - - The strtok_rP() function is similar to strtok_r() except that \p delim - is pointer to a string in program space. - - \returns The strtok_rP() function returns a pointer to the next token or - NULL when no more tokens are found. */ -extern char *strtok_rP(char *__s, const char * __delim, char **__last); - -/** \ingroup avr_pgmspace - \fn size_t strlen_PF(uint_farptr_t s) - \brief Obtain the length of a string - - The strlen_PF() function is similar to strlen(), except that \e s is a - far pointer to a string in program space. - - \param s A far pointer to the string in flash - - \returns The strlen_PF() function returns the number of characters in - \e s. The contents of RAMPZ SFR are undefined when the function returns. */ -extern size_t strlen_PF(uint_farptr_t src) __ATTR_CONST__; /* program memory can't change */ - -/** \ingroup avr_pgmspace - \fn size_t strnlen_PF(uint_farptr_t s, size_t len) - \brief Determine the length of a fixed-size string - - The strnlen_PF() function is similar to strnlen(), except that \e s is a - far pointer to a string in program space. - - \param s A far pointer to the string in Flash - \param len The maximum number of length to return - - \returns The strnlen_PF function returns strlen_P(\e s), if that is less - than \e len, or \e len if there is no '\\0' character among the first \e - len characters pointed to by \e s. The contents of RAMPZ SFR are - undefined when the function returns. */ -extern size_t strnlen_PF(uint_farptr_t src, size_t len) __ATTR_CONST__; /* program memory can't change */ - -/** \ingroup avr_pgmspace - \fn void *memcpy_PF(void *dest, uint_farptr_t src, size_t n) - \brief Copy a memory block from flash to SRAM - - The memcpy_PF() function is similar to memcpy(), except the data - is copied from the program space and is addressed using a far pointer. - - \param dest A pointer to the destination buffer - \param src A far pointer to the origin of data in flash memory - \param n The number of bytes to be copied - - \returns The memcpy_PF() function returns a pointer to \e dst. The contents - of RAMPZ SFR are undefined when the function returns. */ -extern void *memcpy_PF(void *dest, uint_farptr_t src, size_t len); - -/** \ingroup avr_pgmspace - \fn char *strcpy_PF(char *dst, uint_farptr_t src) - \brief Duplicate a string - - The strcpy_PF() function is similar to strcpy() except that \e src is a far - pointer to a string in program space. - - \param dst A pointer to the destination string in SRAM - \param src A far pointer to the source string in Flash - - \returns The strcpy_PF() function returns a pointer to the destination - string \e dst. The contents of RAMPZ SFR are undefined when the funcion - returns. */ -extern char *strcpy_PF(char *dest, uint_farptr_t src); - -/** \ingroup avr_pgmspace - \fn char *strncpy_PF(char *dst, uint_farptr_t src, size_t n) - \brief Duplicate a string until a limited length - - The strncpy_PF() function is similar to strcpy_PF() except that not more - than \e n bytes of \e src are copied. Thus, if there is no null byte among - the first \e n bytes of \e src, the result will not be null-terminated. - - In the case where the length of \e src is less than that of \e n, the - remainder of \e dst will be padded with nulls. - - \param dst A pointer to the destination string in SRAM - \param src A far pointer to the source string in Flash - \param n The maximum number of bytes to copy - - \returns The strncpy_PF() function returns a pointer to the destination - string \e dst. The contents of RAMPZ SFR are undefined when the function - returns. */ -extern char *strncpy_PF(char *dest, uint_farptr_t src, size_t len); - -/** \ingroup avr_pgmspace - \fn char *strcat_PF(char *dst, uint_farptr_t src) - \brief Concatenates two strings - - The strcat_PF() function is similar to strcat() except that the \e src - string must be located in program space (flash) and is addressed using - a far pointer - - \param dst A pointer to the destination string in SRAM - \param src A far pointer to the string to be appended in Flash - - \returns The strcat_PF() function returns a pointer to the resulting - string \e dst. The contents of RAMPZ SFR are undefined when the function - returns */ -extern char *strcat_PF(char *dest, uint_farptr_t src); - -/** \ingroup avr_pgmspace - \fn size_t strlcat_PF(char *dst, uint_farptr_t src, size_t n) - \brief Concatenate two strings - - The strlcat_PF() function is similar to strlcat(), except that the \e src - string must be located in program space (flash) and is addressed using - a far pointer. - - Appends src to string dst of size \e n (unlike strncat(), \e n is the - full size of \e dst, not space left). At most \e n-1 characters - will be copied. Always NULL terminates (unless \e n <= strlen(\e dst)). - - \param dst A pointer to the destination string in SRAM - \param src A far pointer to the source string in Flash - \param n The total number of bytes allocated to the destination string - - \returns The strlcat_PF() function returns strlen(\e src) + MIN(\e n, - strlen(initial \e dst)). If retval >= \e n, truncation occurred. The - contents of RAMPZ SFR are undefined when the funcion returns. */ -extern size_t strlcat_PF(char *dst, uint_farptr_t src, size_t siz); - -/** \ingroup avr_pgmspace - \fn char *strncat_PF(char *dst, uint_farptr_t src, size_t n) - \brief Concatenate two strings - - The strncat_PF() function is similar to strncat(), except that the \e src - string must be located in program space (flash) and is addressed using a - far pointer. - - \param dst A pointer to the destination string in SRAM - \param src A far pointer to the source string in Flash - \param n The maximum number of bytes to append - - \returns The strncat_PF() function returns a pointer to the resulting - string \e dst. The contents of RAMPZ SFR are undefined when the function - returns. */ -extern char *strncat_PF(char *dest, uint_farptr_t src, size_t len); - -/** \ingroup avr_pgmspace - \fn int strcmp_PF(const char *s1, uint_farptr_t s2) - \brief Compares two strings - - The strcmp_PF() function is similar to strcmp() except that \e s2 is a far - pointer to a string in program space. - - \param s1 A pointer to the first string in SRAM - \param s2 A far pointer to the second string in Flash - - \returns The strcmp_PF() function returns an integer less than, equal to, - or greater than zero if \e s1 is found, respectively, to be less than, to - match, or be greater than \e s2. The contents of RAMPZ SFR are undefined - when the function returns. */ -extern int strcmp_PF(const char *s1, uint_farptr_t s2) __ATTR_PURE__; - -/** \ingroup avr_pgmspace - \fn int strncmp_PF(const char *s1, uint_farptr_t s2, size_t n) - \brief Compare two strings with limited length - - The strncmp_PF() function is similar to strcmp_PF() except it only - compares the first (at most) \e n characters of \e s1 and \e s2. - - \param s1 A pointer to the first string in SRAM - \param s2 A far pointer to the second string in Flash - \param n The maximum number of bytes to compare - - \returns The strncmp_PF() function returns an integer less than, equal - to, or greater than zero if \e s1 (or the first \e n bytes thereof) is found, - respectively, to be less than, to match, or be greater than \e s2. The - contents of RAMPZ SFR are undefined when the function returns. */ -extern int strncmp_PF(const char *s1, uint_farptr_t s2, size_t n) __ATTR_PURE__; - -/** \ingroup avr_pgmspace - \fn int strcasecmp_PF(const char *s1, uint_farptr_t s2) - \brief Compare two strings ignoring case - - The strcasecmp_PF() function compares the two strings \e s1 and \e s2, ignoring - the case of the characters. - - \param s1 A pointer to the first string in SRAM - \param s2 A far pointer to the second string in Flash - - \returns The strcasecmp_PF() function returns an integer less than, equal - to, or greater than zero if \e s1 is found, respectively, to be less than, to - match, or be greater than \e s2. The contents of RAMPZ SFR are undefined - when the function returns. */ -extern int strcasecmp_PF(const char *s1, uint_farptr_t s2) __ATTR_PURE__; - -/** \ingroup avr_pgmspace - \fn int strncasecmp_PF(const char *s1, uint_farptr_t s2, size_t n) - \brief Compare two strings ignoring case - - The strncasecmp_PF() function is similar to strcasecmp_PF(), except it - only compares the first \e n characters of \e s1 and the string in flash is - addressed using a far pointer. - - \param s1 A pointer to a string in SRAM - \param s2 A far pointer to a string in Flash - \param n The maximum number of bytes to compare - - \returns The strncasecmp_PF() function returns an integer less than, equal - to, or greater than zero if \e s1 (or the first \e n bytes thereof) is found, - respectively, to be less than, to match, or be greater than \e s2. The - contents of RAMPZ SFR are undefined when the function returns. */ -extern int strncasecmp_PF(const char *s1, uint_farptr_t s2, size_t n) __ATTR_PURE__; - -/** \ingroup avr_pgmspace - \fn char *strstr_PF(const char *s1, uint_farptr_t s2) - \brief Locate a substring. - - The strstr_PF() function finds the first occurrence of the substring \c s2 - in the string \c s1. The terminating '\\0' characters are not - compared. - The strstr_PF() function is similar to strstr() except that \c s2 is a - far pointer to a string in program space. - - \returns The strstr_PF() function returns a pointer to the beginning of the - substring, or NULL if the substring is not found. - If \c s2 points to a string of zero length, the function returns \c s1. The - contents of RAMPZ SFR are undefined when the function returns. */ -extern char *strstr_PF(const char *s1, uint_farptr_t s2); - -/** \ingroup avr_pgmspace - \fn size_t strlcpy_PF(char *dst, uint_farptr_t src, size_t siz) - \brief Copy a string from progmem to RAM. - - Copy src to string dst of size siz. At most siz-1 characters will be - copied. Always NULL terminates (unless siz == 0). - - \returns The strlcpy_PF() function returns strlen(src). If retval >= siz, - truncation occurred. The contents of RAMPZ SFR are undefined when the - function returns. */ -extern size_t strlcpy_PF(char *dst, uint_farptr_t src, size_t siz); - -/** \ingroup avr_pgmspace - \fn int memcmp_PF(const void *s1, uint_farptr_t s2, size_t len) - \brief Compare memory areas - - The memcmp_PF() function compares the first \p len bytes of the memory - areas \p s1 and flash \p s2. The comparision is performed using unsigned - char operations. It is an equivalent of memcmp_P() function, except - that it is capable working on all FLASH including the exteded area - above 64kB. - - \returns The memcmp_PF() function returns an integer less than, equal - to, or greater than zero if the first \p len bytes of \p s1 is found, - respectively, to be less than, to match, or be greater than the first - \p len bytes of \p s2. */ -extern int memcmp_PF(const void *, uint_farptr_t, size_t) __ATTR_PURE__; - -#ifdef __DOXYGEN__ -/** \ingroup avr_pgmspace - \fn size_t strlen_P(const char *src) - - The strlen_P() function is similar to strlen(), except that src is a - pointer to a string in program space. - - \returns The strlen_P() function returns the number of characters in src. - - \note strlen_P() is implemented as an inline function in the avr/pgmspace.h - header file, which will check if the length of the string is a constant - and known at compile time. If it is not known at compile time, the macro - will issue a call to __strlen_P() which will then calculate the length - of the string as normal. -*/ -static inline size_t strlen_P(const char * s); -#else -extern size_t __strlen_P(const char *) __ATTR_CONST__; /* internal helper function */ -__attribute__((__always_inline__)) static __inline__ size_t strlen_P(const char * s); -static __inline__ size_t strlen_P(const char *s) { - return __builtin_constant_p(__builtin_strlen(s)) - ? __builtin_strlen(s) : __strlen_P(s); -} -#endif - -#ifdef __cplusplus -} -#endif - -#endif /* __PGMSPACE_H_ */ diff --git a/arduino/hardware/tools/avr/avr/include/avr/portpins.h b/arduino/hardware/tools/avr/avr/include/avr/portpins.h deleted file mode 100644 index c179edf..0000000 --- a/arduino/hardware/tools/avr/avr/include/avr/portpins.h +++ /dev/null @@ -1,549 +0,0 @@ -/* Copyright (c) 2003 Theodore A. Roth - All rights reserved. - - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - * Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - * Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in - the documentation and/or other materials provided with the - distribution. - - * Neither the name of the copyright holders nor the names of - contributors may be used to endorse or promote products derived - from this software without specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. */ - -/* $Id$ */ - -#ifndef _AVR_PORTPINS_H_ -#define _AVR_PORTPINS_H_ 1 - -/* This file should only be included from , never directly. */ - -#ifndef _AVR_IO_H_ -# error "Include instead of this file." -#endif - -/* Define Generic PORTn, DDn, and PINn values. */ - -/* Port Data Register (generic) */ -#define PORT7 7 -#define PORT6 6 -#define PORT5 5 -#define PORT4 4 -#define PORT3 3 -#define PORT2 2 -#define PORT1 1 -#define PORT0 0 - -/* Port Data Direction Register (generic) */ -#define DD7 7 -#define DD6 6 -#define DD5 5 -#define DD4 4 -#define DD3 3 -#define DD2 2 -#define DD1 1 -#define DD0 0 - -/* Port Input Pins (generic) */ -#define PIN7 7 -#define PIN6 6 -#define PIN5 5 -#define PIN4 4 -#define PIN3 3 -#define PIN2 2 -#define PIN1 1 -#define PIN0 0 - -/* Define PORTxn an Pxn values for all possible port pins if not defined already by io.h. */ - -/* PORT A */ - -#if defined(PA0) && !defined(PORTA0) -# define PORTA0 PA0 -#elif defined(PORTA0) && !defined(PA0) -# define PA0 PORTA0 -#endif -#if defined(PA1) && !defined(PORTA1) -# define PORTA1 PA1 -#elif defined(PORTA1) && !defined(PA1) -# define PA1 PORTA1 -#endif -#if defined(PA2) && !defined(PORTA2) -# define PORTA2 PA2 -#elif defined(PORTA2) && !defined(PA2) -# define PA2 PORTA2 -#endif -#if defined(PA3) && !defined(PORTA3) -# define PORTA3 PA3 -#elif defined(PORTA3) && !defined(PA3) -# define PA3 PORTA3 -#endif -#if defined(PA4) && !defined(PORTA4) -# define PORTA4 PA4 -#elif defined(PORTA4) && !defined(PA4) -# define PA4 PORTA4 -#endif -#if defined(PA5) && !defined(PORTA5) -# define PORTA5 PA5 -#elif defined(PORTA5) && !defined(PA5) -# define PA5 PORTA5 -#endif -#if defined(PA6) && !defined(PORTA6) -# define PORTA6 PA6 -#elif defined(PORTA6) && !defined(PA6) -# define PA6 PORTA6 -#endif -#if defined(PA7) && !defined(PORTA7) -# define PORTA7 PA7 -#elif defined(PORTA7) && !defined(PA7) -# define PA7 PORTA7 -#endif - -/* PORT B */ - -#if defined(PB0) && !defined(PORTB0) -# define PORTB0 PB0 -#elif defined(PORTB0) && !defined(PB0) -# define PB0 PORTB0 -#endif -#if defined(PB1) && !defined(PORTB1) -# define PORTB1 PB1 -#elif defined(PORTB1) && !defined(PB1) -# define PB1 PORTB1 -#endif -#if defined(PB2) && !defined(PORTB2) -# define PORTB2 PB2 -#elif defined(PORTB2) && !defined(PB2) -# define PB2 PORTB2 -#endif -#if defined(PB3) && !defined(PORTB3) -# define PORTB3 PB3 -#elif defined(PORTB3) && !defined(PB3) -# define PB3 PORTB3 -#endif -#if defined(PB4) && !defined(PORTB4) -# define PORTB4 PB4 -#elif defined(PORTB4) && !defined(PB4) -# define PB4 PORTB4 -#endif -#if defined(PB5) && !defined(PORTB5) -# define PORTB5 PB5 -#elif defined(PORTB5) && !defined(PB5) -# define PB5 PORTB5 -#endif -#if defined(PB6) && !defined(PORTB6) -# define PORTB6 PB6 -#elif defined(PORTB6) && !defined(PB6) -# define PB6 PORTB6 -#endif -#if defined(PB7) && !defined(PORTB7) -# define PORTB7 PB7 -#elif defined(PORTB7) && !defined(PB7) -# define PB7 PORTB7 -#endif - -/* PORT C */ - -#if defined(PC0) && !defined(PORTC0) -# define PORTC0 PC0 -#elif defined(PORTC0) && !defined(PC0) -# define PC0 PORTC0 -#endif -#if defined(PC1) && !defined(PORTC1) -# define PORTC1 PC1 -#elif defined(PORTC1) && !defined(PC1) -# define PC1 PORTC1 -#endif -#if defined(PC2) && !defined(PORTC2) -# define PORTC2 PC2 -#elif defined(PORTC2) && !defined(PC2) -# define PC2 PORTC2 -#endif -#if defined(PC3) && !defined(PORTC3) -# define PORTC3 PC3 -#elif defined(PORTC3) && !defined(PC3) -# define PC3 PORTC3 -#endif -#if defined(PC4) && !defined(PORTC4) -# define PORTC4 PC4 -#elif defined(PORTC4) && !defined(PC4) -# define PC4 PORTC4 -#endif -#if defined(PC5) && !defined(PORTC5) -# define PORTC5 PC5 -#elif defined(PORTC5) && !defined(PC5) -# define PC5 PORTC5 -#endif -#if defined(PC6) && !defined(PORTC6) -# define PORTC6 PC6 -#elif defined(PORTC6) && !defined(PC6) -# define PC6 PORTC6 -#endif -#if defined(PC7) && !defined(PORTC7) -# define PORTC7 PC7 -#elif defined(PORTC7) && !defined(PC7) -# define PC7 PORTC7 -#endif - -/* PORT D */ - -#if defined(PD0) && !defined(PORTD0) -# define PORTD0 PD0 -#elif defined(PORTD0) && !defined(PD0) -# define PD0 PORTD0 -#endif -#if defined(PD1) && !defined(PORTD1) -# define PORTD1 PD1 -#elif defined(PORTD1) && !defined(PD1) -# define PD1 PORTD1 -#endif -#if defined(PD2) && !defined(PORTD2) -# define PORTD2 PD2 -#elif defined(PORTD2) && !defined(PD2) -# define PD2 PORTD2 -#endif -#if defined(PD3) && !defined(PORTD3) -# define PORTD3 PD3 -#elif defined(PORTD3) && !defined(PD3) -# define PD3 PORTD3 -#endif -#if defined(PD4) && !defined(PORTD4) -# define PORTD4 PD4 -#elif defined(PORTD4) && !defined(PD4) -# define PD4 PORTD4 -#endif -#if defined(PD5) && !defined(PORTD5) -# define PORTD5 PD5 -#elif defined(PORTD5) && !defined(PD5) -# define PD5 PORTD5 -#endif -#if defined(PD6) && !defined(PORTD6) -# define PORTD6 PD6 -#elif defined(PORTD6) && !defined(PD6) -# define PD6 PORTD6 -#endif -#if defined(PD7) && !defined(PORTD7) -# define PORTD7 PD7 -#elif defined(PORTD7) && !defined(PD7) -# define PD7 PORTD7 -#endif - -/* PORT E */ - -#if defined(PE0) && !defined(PORTE0) -# define PORTE0 PE0 -#elif defined(PORTE0) && !defined(PE0) -# define PE0 PORTE0 -#endif -#if defined(PE1) && !defined(PORTE1) -# define PORTE1 PE1 -#elif defined(PORTE1) && !defined(PE1) -# define PE1 PORTE1 -#endif -#if defined(PE2) && !defined(PORTE2) -# define PORTE2 PE2 -#elif defined(PORTE2) && !defined(PE2) -# define PE2 PORTE2 -#endif -#if defined(PE3) && !defined(PORTE3) -# define PORTE3 PE3 -#elif defined(PORTE3) && !defined(PE3) -# define PE3 PORTE3 -#endif -#if defined(PE4) && !defined(PORTE4) -# define PORTE4 PE4 -#elif defined(PORTE4) && !defined(PE4) -# define PE4 PORTE4 -#endif -#if defined(PE5) && !defined(PORTE5) -# define PORTE5 PE5 -#elif defined(PORTE5) && !defined(PE5) -# define PE5 PORTE5 -#endif -#if defined(PE6) && !defined(PORTE6) -# define PORTE6 PE6 -#elif defined(PORTE6) && !defined(PE6) -# define PE6 PORTE6 -#endif -#if defined(PE7) && !defined(PORTE7) -# define PORTE7 PE7 -#elif defined(PORTE7) && !defined(PE7) -# define PE7 PORTE7 -#endif - -/* PORT F */ - -#if defined(PF0) && !defined(PORTF0) -# define PORTF0 PF0 -#elif defined(PORTF0) && !defined(PF0) -# define PF0 PORTF0 -#endif -#if defined(PF1) && !defined(PORTF1) -# define PORTF1 PF1 -#elif defined(PORTF1) && !defined(PF1) -# define PF1 PORTF1 -#endif -#if defined(PF2) && !defined(PORTF2) -# define PORTF2 PF2 -#elif defined(PORTF2) && !defined(PF2) -# define PF2 PORTF2 -#endif -#if defined(PF3) && !defined(PORTF3) -# define PORTF3 PF3 -#elif defined(PORTF3) && !defined(PF3) -# define PF3 PORTF3 -#endif -#if defined(PF4) && !defined(PORTF4) -# define PORTF4 PF4 -#elif defined(PORTF4) && !defined(PF4) -# define PF4 PORTF4 -#endif -#if defined(PF5) && !defined(PORTF5) -# define PORTF5 PF5 -#elif defined(PORTF5) && !defined(PF5) -# define PF5 PORTF5 -#endif -#if defined(PF6) && !defined(PORTF6) -# define PORTF6 PF6 -#elif defined(PORTF6) && !defined(PF6) -# define PF6 PORTF6 -#endif -#if defined(PF7) && !defined(PORTF7) -# define PORTF7 PF7 -#elif defined(PORTF7) && !defined(PF7) -# define PF7 PORTF7 -#endif - -/* PORT G */ - -#if defined(PG0) && !defined(PORTG0) -# define PORTG0 PG0 -#elif defined(PORTG0) && !defined(PG0) -# define PG0 PORTG0 -#endif -#if defined(PG1) && !defined(PORTG1) -# define PORTG1 PG1 -#elif defined(PORTG1) && !defined(PG1) -# define PG1 PORTG1 -#endif -#if defined(PG2) && !defined(PORTG2) -# define PORTG2 PG2 -#elif defined(PORTG2) && !defined(PG2) -# define PG2 PORTG2 -#endif -#if defined(PG3) && !defined(PORTG3) -# define PORTG3 PG3 -#elif defined(PORTG3) && !defined(PG3) -# define PG3 PORTG3 -#endif -#if defined(PG4) && !defined(PORTG4) -# define PORTG4 PG4 -#elif defined(PORTG4) && !defined(PG4) -# define PG4 PORTG4 -#endif -#if defined(PG5) && !defined(PORTG5) -# define PORTG5 PG5 -#elif defined(PORTG5) && !defined(PG5) -# define PG5 PORTG5 -#endif -#if defined(PG6) && !defined(PORTG6) -# define PORTG6 PG6 -#elif defined(PORTG6) && !defined(PG6) -# define PG6 PORTG6 -#endif -#if defined(PG7) && !defined(PORTG7) -# define PORTG7 PG7 -#elif defined(PORTG7) && !defined(PG7) -# define PG7 PORTG7 -#endif - -/* PORT H */ - -#if defined(PH0) && !defined(PORTH0) -# define PORTH0 PH0 -#elif defined(PORTH0) && !defined(PH0) -# define PH0 PORTH0 -#endif -#if defined(PH1) && !defined(PORTH1) -# define PORTH1 PH1 -#elif defined(PORTH1) && !defined(PH1) -# define PH1 PORTH1 -#endif -#if defined(PH2) && !defined(PORTH2) -# define PORTH2 PH2 -#elif defined(PORTH2) && !defined(PH2) -# define PH2 PORTH2 -#endif -#if defined(PH3) && !defined(PORTH3) -# define PORTH3 PH3 -#elif defined(PORTH3) && !defined(PH3) -# define PH3 PORTH3 -#endif -#if defined(PH4) && !defined(PORTH4) -# define PORTH4 PH4 -#elif defined(PORTH4) && !defined(PH4) -# define PH4 PORTH4 -#endif -#if defined(PH5) && !defined(PORTH5) -# define PORTH5 PH5 -#elif defined(PORTH5) && !defined(PH5) -# define PH5 PORTH5 -#endif -#if defined(PH6) && !defined(PORTH6) -# define PORTH6 PH6 -#elif defined(PORTH6) && !defined(PH6) -# define PH6 PORTH6 -#endif -#if defined(PH7) && !defined(PORTH7) -# define PORTH7 PH7 -#elif defined(PORTH7) && !defined(PH7) -# define PH7 PORTH7 -#endif - -/* PORT J */ - -#if defined(PJ0) && !defined(PORTJ0) -# define PORTJ0 PJ0 -#elif defined(PORTJ0) && !defined(PJ0) -# define PJ0 PORTJ0 -#endif -#if defined(PJ1) && !defined(PORTJ1) -# define PORTJ1 PJ1 -#elif defined(PORTJ1) && !defined(PJ1) -# define PJ1 PORTJ1 -#endif -#if defined(PJ2) && !defined(PORTJ2) -# define PORTJ2 PJ2 -#elif defined(PORTJ2) && !defined(PJ2) -# define PJ2 PORTJ2 -#endif -#if defined(PJ3) && !defined(PORTJ3) -# define PORTJ3 PJ3 -#elif defined(PORTJ3) && !defined(PJ3) -# define PJ3 PORTJ3 -#endif -#if defined(PJ4) && !defined(PORTJ4) -# define PORTJ4 PJ4 -#elif defined(PORTJ4) && !defined(PJ4) -# define PJ4 PORTJ4 -#endif -#if defined(PJ5) && !defined(PORTJ5) -# define PORTJ5 PJ5 -#elif defined(PORTJ5) && !defined(PJ5) -# define PJ5 PORTJ5 -#endif -#if defined(PJ6) && !defined(PORTJ6) -# define PORTJ6 PJ6 -#elif defined(PORTJ6) && !defined(PJ6) -# define PJ6 PORTJ6 -#endif -#if defined(PJ7) && !defined(PORTJ7) -# define PORTJ7 PJ7 -#elif defined(PORTJ7) && !defined(PJ7) -# define PJ7 PORTJ7 -#endif - -/* PORT K */ - -#if defined(PK0) && !defined(PORTK0) -# define PORTK0 PK0 -#elif defined(PORTK0) && !defined(PK0) -# define PK0 PORTK0 -#endif -#if defined(PK1) && !defined(PORTK1) -# define PORTK1 PK1 -#elif defined(PORTK1) && !defined(PK1) -# define PK1 PORTK1 -#endif -#if defined(PK2) && !defined(PORTK2) -# define PORTK2 PK2 -#elif defined(PORTK2) && !defined(PK2) -# define PK2 PORTK2 -#endif -#if defined(PK3) && !defined(PORTK3) -# define PORTK3 PK3 -#elif defined(PORTK3) && !defined(PK3) -# define PK3 PORTK3 -#endif -#if defined(PK4) && !defined(PORTK4) -# define PORTK4 PK4 -#elif defined(PORTK4) && !defined(PK4) -# define PK4 PORTK4 -#endif -#if defined(PK5) && !defined(PORTK5) -# define PORTK5 PK5 -#elif defined(PORTK5) && !defined(PK5) -# define PK5 PORTK5 -#endif -#if defined(PK6) && !defined(PORTK6) -# define PORTK6 PK6 -#elif defined(PORTK6) && !defined(PK6) -# define PK6 PORTK6 -#endif -#if defined(PK7) && !defined(PORTK7) -# define PORTK7 PK7 -#elif defined(PORTK7) && !defined(PK7) -# define PK7 PORTK7 -#endif - -/* PORT L */ - -#if defined(PL0) && !defined(PORTL0) -# define PORTL0 PL0 -#elif defined(PORTL0) && !defined(PL0) -# define PL0 PORTL0 -#endif -#if defined(PL1) && !defined(PORTL1) -# define PORTL1 PL1 -#elif defined(PORTL1) && !defined(PL1) -# define PL1 PORTL1 -#endif -#if defined(PL2) && !defined(PORTL2) -# define PORTL2 PL2 -#elif defined(PORTL2) && !defined(PL2) -# define PL2 PORTL2 -#endif -#if defined(PL3) && !defined(PORTL3) -# define PORTL3 PL3 -#elif defined(PORTL3) && !defined(PL3) -# define PL3 PORTL3 -#endif -#if defined(PL4) && !defined(PORTL4) -# define PORTL4 PL4 -#elif defined(PORTL4) && !defined(PL4) -# define PL4 PORTL4 -#endif -#if defined(PL5) && !defined(PORTL5) -# define PORTL5 PL5 -#elif defined(PORTL5) && !defined(PL5) -# define PL5 PORTL5 -#endif -#if defined(PL6) && !defined(PORTL6) -# define PORTL6 PL6 -#elif defined(PORTL6) && !defined(PL6) -# define PL6 PORTL6 -#endif -#if defined(PL7) && !defined(PORTL7) -# define PORTL7 PL7 -#elif defined(PORTL7) && !defined(PL7) -# define PL7 PORTL7 -#endif - -#endif /* _AVR_PORTPINS_H_ */ diff --git a/arduino/hardware/tools/avr/avr/include/avr/power.h b/arduino/hardware/tools/avr/avr/include/avr/power.h deleted file mode 100644 index f74e6cb..0000000 --- a/arduino/hardware/tools/avr/avr/include/avr/power.h +++ /dev/null @@ -1,1909 +0,0 @@ -/* Copyright (c) 2006, 2007, 2008 Eric B. Weddington - Copyright (c) 2011 Frédéric Nadeau - All rights reserved. - - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - * Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - * Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in - the documentation and/or other materials provided with the - distribution. - * Neither the name of the copyright holders nor the names of - contributors may be used to endorse or promote products derived - from this software without specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. */ - -/* $Id$ */ - -#ifndef _AVR_POWER_H_ -#define _AVR_POWER_H_ 1 - -#include -#include - - -/** \file */ -/** \defgroup avr_power : Power Reduction Management - -\code #include \endcode - -Many AVRs contain a Power Reduction Register (PRR) or Registers (PRRx) that -allow you to reduce power consumption by disabling or enabling various on-board -peripherals as needed. Some devices have the XTAL Divide Control Register -(XDIV) which offer similar functionality as System Clock Prescale -Register (CLKPR). - -There are many macros in this header file that provide an easy interface -to enable or disable on-board peripherals to reduce power. See the table below. - -\note Not all AVR devices have a Power Reduction Register (for example -the ATmega8). On those devices without a Power Reduction Register, the -power reduction macros are not available.. - -\note Not all AVR devices contain the same peripherals (for example, the LCD -interface), or they will be named differently (for example, USART and -USART0). Please consult your device's datasheet, or the header file, to -find out which macros are applicable to your device. - -\note For device using the XTAL Divide Control Register (XDIV), when prescaler -is used, Timer/Counter0 can only be used in asynchronous mode. Keep in mind -that Timer/Counter0 source shall be less than ¼th of peripheral clock. -Therefore, when using a typical 32.768 kHz crystal, one shall not scale -the clock below 131.072 kHz. - -*/ - - -/** \addtogroup avr_power - -\anchor avr_powermacros - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Power MacroDescription
power_aca_disable()Disable the Analog Comparator on PortA.
power_aca_enable()Enable the Analog Comparator on PortA.
power_adc_enable()Enable the Analog to Digital Converter module.
power_adc_disable()Disable the Analog to Digital Converter module.
power_adca_disable()Disable the Analog to Digital Converter module on PortA
power_adca_enable()Enable the Analog to Digital Converter module on PortA
power_evsys_disable()Disable the EVSYS module
power_evsys_enable()Enable the EVSYS module
power_hiresc_disable()Disable the HIRES module on PortC
power_hiresc_enable()Enable the HIRES module on PortC
power_lcd_enable()Enable the LCD module.
power_lcd_disable().Disable the LCD module.
power_pga_enable()Enable the Programmable Gain Amplifier module.
power_pga_disable()Disable the Programmable Gain Amplifier module.
power_pscr_enable()Enable the Reduced Power Stage Controller module.
power_pscr_disable()Disable the Reduced Power Stage Controller module.
power_psc0_enable()Enable the Power Stage Controller 0 module.
power_psc0_disable()Disable the Power Stage Controller 0 module.
power_psc1_enable()Enable the Power Stage Controller 1 module.
power_psc1_disable()Disable the Power Stage Controller 1 module.
power_psc2_enable()Enable the Power Stage Controller 2 module.
power_psc2_disable()Disable the Power Stage Controller 2 module.
power_ram0_enable()Enable the SRAM block 0 .
power_ram0_disable()Disable the SRAM block 0.
power_ram1_enable()Enable the SRAM block 1 .
power_ram1_disable()Disable the SRAM block 1.
power_ram2_enable()Enable the SRAM block 2 .
power_ram2_disable()Disable the SRAM block 2.
power_ram3_enable()Enable the SRAM block 3 .
power_ram3_disable()Disable the SRAM block 3.
power_rtc_disable()Disable the RTC module
power_rtc_enable()Enable the RTC module
power_spi_enable()Enable the Serial Peripheral Interface module.
power_spi_disable()Disable the Serial Peripheral Interface module.
power_spic_disable()Disable the SPI module on PortC
power_spic_enable()Enable the SPI module on PortC
power_spid_disable()Disable the SPI module on PortD
power_spid_enable()Enable the SPI module on PortD
power_tc0c_disable()Disable the TC0 module on PortC
power_tc0c_enable()Enable the TC0 module on PortC
power_tc0d_disable()Disable the TC0 module on PortD
power_tc0d_enable()Enable the TC0 module on PortD
power_tc0e_disable()Disable the TC0 module on PortE
power_tc0e_enable()Enable the TC0 module on PortE
power_tc0f_disable()Disable the TC0 module on PortF
power_tc0f_enable()Enable the TC0 module on PortF
power_tc1c_disable()Disable the TC1 module on PortC
power_tc1c_enable()Enable the TC1 module on PortC
power_twic_disable()Disable the Two Wire Interface module on PortC
power_twic_enable()Enable the Two Wire Interface module on PortC
power_twie_disable()Disable the Two Wire Interface module on PortE
power_twie_enable()Enable the Two Wire Interface module on PortE
power_timer0_enable()Enable the Timer 0 module.
power_timer0_disable()Disable the Timer 0 module.
power_timer1_enable()Enable the Timer 1 module.
power_timer1_disable()Disable the Timer 1 module.
power_timer2_enable()Enable the Timer 2 module.
power_timer2_disable()Disable the Timer 2 module.
power_timer3_enable()Enable the Timer 3 module.
power_timer3_disable()Disable the Timer 3 module.
power_timer4_enable()Enable the Timer 4 module.
power_timer4_disable()Disable the Timer 4 module.
power_timer5_enable()Enable the Timer 5 module.
power_timer5_disable()Disable the Timer 5 module.
power_twi_enable()Enable the Two Wire Interface module.
power_twi_disable()Disable the Two Wire Interface module.
power_usart_enable()Enable the USART module.
power_usart_disable()Disable the USART module.
power_usart0_enable()Enable the USART 0 module.
power_usart0_disable()Disable the USART 0 module.
power_usart1_enable()Enable the USART 1 module.
power_usart1_disable()Disable the USART 1 module.
power_usart2_enable()Enable the USART 2 module.
power_usart2_disable()Disable the USART 2 module.
power_usart3_enable()Enable the USART 3 module.
power_usart3_disable()Disable the USART 3 module.
power_usartc0_disable() Disable the USART0 module on PortC
power_usartc0_enable() Enable the USART0 module on PortC
power_usartd0_disable() Disable the USART0 module on PortD
power_usartd0_enable() Enable the USART0 module on PortD
power_usarte0_disable() Disable the USART0 module on PortE
power_usarte0_enable() Enable the USART0 module on PortE
power_usartf0_disable() Disable the USART0 module on PortF
power_usartf0_enable() Enable the USART0 module on PortF
power_usb_enable()Enable the USB module.
power_usb_disable()Disable the USB module.
power_usi_enable()Enable the Universal Serial Interface module.
power_usi_disable()Disable the Universal Serial Interface module.
power_vadc_enable()Enable the Voltage ADC module.
power_vadc_disable()Disable the Voltage ADC module.
power_all_enable()Enable all modules.
power_all_disable()Disable all modules.
-
- - -@} */ - -#if defined(__AVR_HAVE_PRR_PRADC) -#define power_adc_enable() (PRR &= (uint8_t)~(1 << PRADC)) -#define power_adc_disable() (PRR |= (uint8_t)(1 << PRADC)) -#endif - -#if defined(__AVR_HAVE_PRR_PRCAN) -#define power_can_enable() (PRR &= (uint8_t)~(1 << PRCAN)) -#define power_can_disable() (PRR |= (uint8_t)(1 << PRCAN)) -#endif - -#if defined(__AVR_HAVE_PRR_PRLCD) -#define power_lcd_enable() (PRR &= (uint8_t)~(1 << PRLCD)) -#define power_lcd_disable() (PRR |= (uint8_t)(1 << PRLCD)) -#endif - -#if defined(__AVR_HAVE_PRR_PRLIN) -#define power_lin_enable() (PRR &= (uint8_t)~(1 << PRLIN)) -#define power_lin_disable() (PRR |= (uint8_t)(1 << PRLIN)) -#endif - -#if defined(__AVR_HAVE_PRR_PRPSC) -#define power_psc_enable() (PRR &= (uint8_t)~(1 << PRPSC)) -#define power_psc_disable() (PRR |= (uint8_t)(1 << PRPSC)) -#endif - -#if defined(__AVR_HAVE_PRR_PRPSC0) -#define power_psc0_enable() (PRR &= (uint8_t)~(1 << PRPSC0)) -#define power_psc0_disable() (PRR |= (uint8_t)(1 << PRPSC0)) -#endif - -#if defined(__AVR_HAVE_PRR_PRPSC1) -#define power_psc1_enable() (PRR &= (uint8_t)~(1 << PRPSC1)) -#define power_psc1_disable() (PRR |= (uint8_t)(1 << PRPSC1)) -#endif - -#if defined(__AVR_HAVE_PRR_PRPSC2) -#define power_psc2_enable() (PRR &= (uint8_t)~(1 << PRPSC2)) -#define power_psc2_disable() (PRR |= (uint8_t)(1 << PRPSC2)) -#endif - -#if defined(__AVR_HAVE_PRR_PRPSCR) -#define power_pscr_enable() (PRR &= (uint8_t)~(1 << PRPSCR)) -#define power_pscr_disable() (PRR |= (uint8_t)(1 << PRPSCR)) -#endif - -#if defined(__AVR_HAVE_PRR_PRSPI) -#define power_spi_enable() (PRR &= (uint8_t)~(1 << PRSPI)) -#define power_spi_disable() (PRR |= (uint8_t)(1 << PRSPI)) -#endif - -#if defined(__AVR_HAVE_PRR_PRTIM0) -#define power_timer0_enable() (PRR &= (uint8_t)~(1 << PRTIM0)) -#define power_timer0_disable() (PRR |= (uint8_t)(1 << PRTIM0)) -#endif - -#if defined(__AVR_HAVE_PRR_PRTIM1) -#define power_timer1_enable() (PRR &= (uint8_t)~(1 << PRTIM1)) -#define power_timer1_disable() (PRR |= (uint8_t)(1 << PRTIM1)) -#endif - -#if defined(__AVR_HAVE_PRR_PRTIM2) -#define power_timer2_enable() (PRR &= (uint8_t)~(1 << PRTIM2)) -#define power_timer2_disable() (PRR |= (uint8_t)(1 << PRTIM2)) -#endif - -#if defined(__AVR_HAVE_PRR_PRTWI) -#define power_twi_enable() (PRR &= (uint8_t)~(1 << PRTWI)) -#define power_twi_disable() (PRR |= (uint8_t)(1 << PRTWI)) -#endif - -#if defined(__AVR_HAVE_PRR_PRUSART) -#define power_usart_enable() (PRR &= (uint8_t)~(1 << PRUSART)) -#define power_usart_disable() (PRR |= (uint8_t)(1 << PRUSART)) -#endif - -#if defined(__AVR_HAVE_PRR_PRUSART0) -#define power_usart0_enable() (PRR &= (uint8_t)~(1 << PRUSART0)) -#define power_usart0_disable() (PRR |= (uint8_t)(1 << PRUSART0)) -#endif - -#if defined(__AVR_HAVE_PRR_PRUSART1) -#define power_usart1_enable() (PRR &= (uint8_t)~(1 << PRUSART1)) -#define power_usart1_disable() (PRR |= (uint8_t)(1 << PRUSART1)) -#endif - -#if defined(__AVR_HAVE_PRR_PRUSI) -#define power_usi_enable() (PRR &= (uint8_t)~(1 << PRUSI)) -#define power_usi_disable() (PRR |= (uint8_t)(1 << PRUSI)) -#endif - -#if defined(__AVR_HAVE_PRR0_PRADC) -#define power_adc_enable() (PRR0 &= (uint8_t)~(1 << PRADC)) -#define power_adc_disable() (PRR0 |= (uint8_t)(1 << PRADC)) -#endif - -#if defined(__AVR_HAVE_PRR0_PRCO) -#define power_clock_output_enable() (PRR0 &= (uint8_t)~(1 << PRCO)) -#define power_clock_output_disable() (PRR0 |= (uint8_t)(1 << PRCO)) -#endif - -#if defined(__AVR_HAVE_PRR0_PRCRC) -#define power_crc_enable() (PRR0 &= (uint8_t)~(1 << PRCRC)) -#define power_crc_disable() (PRR0 |= (uint8_t)(1 << PRCRC)) -#endif - -#if defined(__AVR_HAVE_PRR0_PRCU) -#define power_crypto_enable() (PRR0 &= (uint8_t)~(1 << PRCU)) -#define power_crypto_disable() (PRR0 |= (uint8_t)(1 << PRCU)) -#endif - -#if defined(__AVR_HAVE_PRR0_PRDS) -#define power_irdriver_enable() (PRR0 &= (uint8_t)~(1 << PRDS)) -#define power_irdriver_disable() (PRR0 |= (uint8_t)(1 << PRDS)) -#endif - -#if defined(__AVR_HAVE_PRR0_PRLFR) -#define power_lfreceiver_enable() (PRR0 &= (uint8_t)~(1 << PRLFR)) -#define power_lfreceiver_disable() (PRR0 |= (uint8_t)(1 << PRLFR)) -#endif - -#if defined(__AVR_HAVE_PRR0_PRLFRS) -#define power_lfrs_enable() (PRR0 &= (uint8_t)~(1 << PRLFRS)) -#define power_lfrs_disable() (PRR0 |= (uint8_t)(1 << PRLFRS)) -#endif - -#if defined(__AVR_HAVE_PRR0_PRLIN) -#define power_lin_enable() (PRR0 &= (uint8_t)~(1 << PRLIN)) -#define power_lin_disable() (PRR0 |= (uint8_t)(1 << PRLIN)) -#endif - -#if defined(__AVR_HAVE_PRR0_PRPGA) -#define power_pga_enable() (PRR0 &= (uint8_t)~(1 << PRPGA)) -#define power_pga_disable() (PRR0 |= (uint8_t)(1 << PRPGA)) -#endif - -#if defined(__AVR_HAVE_PRR0_PRRXDC) -#define power_receive_dsp_control_enable() (PRR0 &= (uint8_t)~(1 << PRRXDC)) -#define power_receive_dsp_control_disable() (PRR0 |= (uint8_t)(1 << PRRXDC)) -#endif - -#if defined(__AVR_HAVE_PRR0_PRSPI) -#define power_spi_enable() (PRR0 &= (uint8_t)~(1 << PRSPI)) -#define power_spi_disable() (PRR0 |= (uint8_t)(1 << PRSPI)) -#endif - -#if defined(__AVR_HAVE_PRR0_PRT0) -#define power_timer0_enable() (PRR0 &= (uint8_t)~(1 << PRT0)) -#define power_timer0_disable() (PRR0 |= (uint8_t)(1 << PRT0)) -#endif - -#if defined(__AVR_HAVE_PRR0_PRTIM0) -#define power_timer0_enable() (PRR0 &= (uint8_t)~(1 << PRTIM0)) -#define power_timer0_disable() (PRR0 |= (uint8_t)(1 << PRTIM0)) -#endif - -#if defined(__AVR_HAVE_PRR0_PRT1) -#define power_timer1_enable() (PRR0 &= (uint8_t)~(1 << PRT1)) -#define power_timer1_disable() (PRR0 |= (uint8_t)(1 << PRT1)) -#endif - -#if defined(__AVR_HAVE_PRR0_PRTIM1) -#define power_timer1_enable() (PRR0 &= (uint8_t)~(1 << PRTIM1)) -#define power_timer1_disable() (PRR0 |= (uint8_t)(1 << PRTIM1)) -#endif - -#if defined(__AVR_HAVE_PRR0_PRT2) -#define power_timer2_enable() (PRR0 &= (uint8_t)~(1 << PRT2)) -#define power_timer2_disable() (PRR0 |= (uint8_t)(1 << PRT2)) -#endif - -#if defined(__AVR_HAVE_PRR0_PRTIM2) -#define power_timer2_enable() (PRR0 &= (uint8_t)~(1 << PRTIM2)) -#define power_timer2_disable() (PRR0 |= (uint8_t)(1 << PRTIM2)) -#endif - -#if defined(__AVR_HAVE_PRR0_PRT3) -#define power_timer3_enable() (PRR0 &= (uint8_t)~(1 << PRT3)) -#define power_timer3_disable() (PRR0 |= (uint8_t)(1 << PRT3)) -#endif - -#if defined(__AVR_HAVE_PRR0_PRTM) -#define power_timermodulator_enable() (PRR0 &= (uint8_t)~(1 << PRTM)) -#define power_timermodulator_disable() (PRR0 |= (uint8_t)(1 << PRTM)) -#endif - -#if defined(__AVR_HAVE_PRR0_PRTWI) -#define power_twi_enable() (PRR0 &= (uint8_t)~(1 << PRTWI)) -#define power_twi_disable() (PRR0 |= (uint8_t)(1 << PRTWI)) -#endif - -#if defined(__AVR_HAVE_PRR0_PRTWI1) -#define power_twi1_enable() (PRR0 &= (uint8_t)~(1 << PRTWI1)) -#define power_twi1_disable() (PRR0 |= (uint8_t)(1 << PRTWI1)) -#endif - -#if defined(__AVR_HAVE_PRR0_PRTXDC) -#define power_transmit_dsp_control_enable() (PRR0 &= (uint8_t)~(1 << PRTXDC)) -#define power_transmit_dsp_control_disable() (PRR0 |= (uint8_t)(1 << PRTXDC)) -#endif - -#if defined(__AVR_HAVE_PRR0_PRUSART0) -#define power_usart0_enable() (PRR0 &= (uint8_t)~(1 << PRUSART0)) -#define power_usart0_disable() (PRR0 |= (uint8_t)(1 << PRUSART0)) -#endif - -#if defined(__AVR_HAVE_PRR0_PRUSART1) -#define power_usart1_enable() (PRR0 &= (uint8_t)~(1 << PRUSART1)) -#define power_usart1_disable() (PRR0 |= (uint8_t)(1 << PRUSART1)) -#endif - -#if defined(__AVR_HAVE_PRR0_PRVADC) -#define power_vadc_enable() (PRR0 &= (uint8_t)~(1 << PRVADC)) -#define power_vadc_disable() (PRR0 |= (uint8_t)(1 << PRVADC)) -#endif - -#if defined(__AVR_HAVE_PRR0_PRVM) -#define power_voltage_monitor_enable() (PRR0 &= (uint8_t)~(1 << PRVM)) -#define power_voltage_monitor_disable() (PRR0 |= (uint8_t)(1 << PRVM)) -#endif - -#if defined(__AVR_HAVE_PRR0_PRVRM) -#define power_vrm_enable() (PRR0 &= (uint8_t)~(1 << PRVRM)) -#define power_vrm_disable() (PRR0 |= (uint8_t)(1 << PRVRM)) -#endif - -#if defined(__AVR_HAVE_PRR1_PRAES) -#define power_aes_enable() (PRR1 &= (uint8_t)~(1 << PRAES)) -#define power_aes_disable() (PRR1 |= (uint8_t)(1 << PRAES)) -#endif - -#if defined(__AVR_HAVE_PRR1_PRCI) -#define power_cinterface_enable() (PRR1 &= (uint8_t)~(1 << PRCI)) -#define power_cinterface_disable() (PRR1 |= (uint8_t)(1 << PRCI)) -#endif - -#if defined(__AVR_HAVE_PRR1_PRHSSPI) -#define power_hsspi_enable() (PRR1 &= (uint8_t)~(1 << PRHSSPI)) -#define power_hsspi_disable() (PRR1 |= (uint8_t)(1 << PRHSSPI)) -#endif - -#if defined(__AVR_HAVE_PRR1_PRKB) -#define power_kb_enable() (PRR1 &= (uint8_t)~(1 << PRKB)) -#define power_kb_disable() (PRR1 |= (uint8_t)(1 << PRKB)) -#endif - -#if defined(__AVR_HAVE_PRR1_PRLFPH) -#define power_lfph_enable() (PRR1 &= (uint8_t)~(1 << PRLFPH)) -#define power_lfph_disable() (PRR1 |= (uint8_t)(1 << PRLFPH)) -#endif - -#if defined(__AVR_HAVE_PRR1_PRLFR) -#define power_lfreceiver_enable() (PRR1 &= (uint8_t)~(1 << PRLFR)) -#define power_lfreceiver_disable() (PRR1 |= (uint8_t)(1 << PRLFR)) -#endif - -#if defined(__AVR_HAVE_PRR1_PRLFTP) -#define power_lftp_enable() (PRR1 &= (uint8_t)~(1 << PRLFTP)) -#define power_lftp_disable() (PRR1 |= (uint8_t)(1 << PRLFTP)) -#endif - -#if defined(__AVR_HAVE_PRR1_PRSCI) -#define power_sci_enable() (PRR1 &= (uint8_t)~(1 << PRSCI)) -#define power_sci_disable() (PRR1 |= (uint8_t)(1 << PRSCI)) -#endif - -#if defined(__AVR_HAVE_PRR1_PRSPI) -#define power_spi_enable() (PRR1 &= (uint8_t)~(1 << PRSPI)) -#define power_spi_disable() (PRR1 |= (uint8_t)(1 << PRSPI)) -#endif - -#if defined(__AVR_HAVE_PRR1_PRT1) -#define power_timer1_enable() (PRR1 &= (uint8_t)~(1 << PRT1)) -#define power_timer1_disable() (PRR1 |= (uint8_t)(1 << PRT1)) -#endif - -#if defined(__AVR_HAVE_PRR1_PRT2) -#define power_timer2_enable() (PRR1 &= (uint8_t)~(1 << PRT2)) -#define power_timer2_disable() (PRR1 |= (uint8_t)(1 << PRT2)) -#endif - -#if defined(__AVR_HAVE_PRR1_PRT3) -#define power_timer3_enable() (PRR1 &= (uint8_t)~(1 << PRT3)) -#define power_timer3_disable() (PRR1 |= (uint8_t)(1 << PRT3)) -#endif - -#if defined(__AVR_HAVE_PRR1_PRT4) -#define power_timer4_enable() (PRR1 &= (uint8_t)~(1 << PRT4)) -#define power_timer4_disable() (PRR1 |= (uint8_t)(1 << PRT4)) -#endif - -#if defined(__AVR_HAVE_PRR1_PRT5) -#define power_timer5_enable() (PRR1 &= (uint8_t)~(1 << PRT5)) -#define power_timer5_disable() (PRR1 |= (uint8_t)(1 << PRT5)) -#endif - -#if defined(__AVR_HAVE_PRR1_PRTIM3) -#define power_timer3_enable() (PRR1 &= (uint8_t)~(1 << PRTIM3)) -#define power_timer3_disable() (PRR1 |= (uint8_t)(1 << PRTIM3)) -#endif - -#if defined(__AVR_HAVE_PRR1_PRTIM4) -#define power_timer4_enable() (PRR1 &= (uint8_t)~(1 << PRTIM4)) -#define power_timer4_disable() (PRR1 |= (uint8_t)(1 << PRTIM4)) -#endif - -#if defined(__AVR_HAVE_PRR1_PRTIM5) -#define power_timer5_enable() (PRR1 &= (uint8_t)~(1 << PRTIM5)) -#define power_timer5_disable() (PRR1 |= (uint8_t)(1 << PRTIM5)) -#endif - -#if defined(__AVR_HAVE_PRR1_PRTRX24) -#define power_transceiver_enable() (PRR1 &= (uint8_t)~(1 << PRTRX24)) -#define power_transceiver_disable() (PRR1 |= (uint8_t)(1 << PRTRX24)) -#endif - -#if defined(__AVR_HAVE_PRR1_PRUSART1) -#define power_usart1_enable() (PRR1 &= (uint8_t)~(1 << PRUSART1)) -#define power_usart1_disable() (PRR1 |= (uint8_t)(1 << PRUSART1)) -#endif - -#if defined(__AVR_HAVE_PRR1_PRUSART2) -#define power_usart2_enable() (PRR1 &= (uint8_t)~(1 << PRUSART2)) -#define power_usart2_disable() (PRR1 |= (uint8_t)(1 << PRUSART2)) -#endif - -#if defined(__AVR_HAVE_PRR1_PRUSART3) -#define power_usart3_enable() (PRR1 &= (uint8_t)~(1 << PRUSART3)) -#define power_usart3_disable() (PRR1 |= (uint8_t)(1 << PRUSART3)) -#endif - -#if defined(__AVR_HAVE_PRR1_PRUSB) -#define power_usb_enable() (PRR1 &= (uint8_t)~(1 << PRUSB)) -#define power_usb_disable() (PRR1 |= (uint8_t)(1 << PRUSB)) -#endif - -#if defined(__AVR_HAVE_PRR1_PRUSBH) -#define power_usbh_enable() (PRR1 &= (uint8_t)~(1 << PRUSBH)) -#define power_usbh_disable() (PRR1 |= (uint8_t)(1 << PRUSBH)) -#endif - -#if defined(__AVR_HAVE_PRR2_PRDF) -#define power_data_fifo_enable() (PRR2 &= (uint8_t)~(1 << PRDF)) -#define power_data_fifo_disable() (PRR2 |= (uint8_t)(1 << PRDF)) -#endif - -#if defined(__AVR_HAVE_PRR2_PRIDS) -#define power_id_scan_enable() (PRR2 &= (uint8_t)~(1 << PRIDS)) -#define power_id_scan_disable() (PRR2 |= (uint8_t)(1 << PRIDS)) -#endif - -#if defined(__AVR_HAVE_PRR2_PRRAM0) -#define power_ram0_enable() (PRR2 &= (uint8_t)~(1 << PRRAM0)) -#define power_ram0_disable() (PRR2 |= (uint8_t)(1 << PRRAM0)) -#endif - -#if defined(__AVR_HAVE_PRR2_PRRAM1) -#define power_ram1_enable() (PRR2 &= (uint8_t)~(1 << PRRAM1)) -#define power_ram1_disable() (PRR2 |= (uint8_t)(1 << PRRAM1)) -#endif - -#if defined(__AVR_HAVE_PRR2_PRRAM2) -#define power_ram2_enable() (PRR2 &= (uint8_t)~(1 << PRRAM2)) -#define power_ram2_disable() (PRR2 |= (uint8_t)(1 << PRRAM2)) -#endif - -#if defined(__AVR_HAVE_PRR2_PRRAM3) -#define power_ram3_enable() (PRR2 &= (uint8_t)~(1 << PRRAM3)) -#define power_ram3_disable() (PRR2 |= (uint8_t)(1 << PRRAM3)) -#endif - -#if defined(__AVR_HAVE_PRR2_PRRS) -#define power_rssi_buffer_enable() (PRR2 &= (uint8_t)~(1 << PRRS)) -#define power_rssi_buffer_disable() (PRR2 |= (uint8_t)(1 << PRRS)) -#endif - -#if defined(__AVR_HAVE_PRR2_PRSF) -#define power_preamble_rssi_fifo_enable() (PRR2 &= (uint8_t)~(1 << PRSF)) -#define power_preamble_rssi_fifo_disable() (PRR2 |= (uint8_t)(1 << PRSF)) -#endif - -#if defined(__AVR_HAVE_PRR2_PRSPI2) -#define power_spi2_enable() (PRR2 &= (uint8_t)~(1 << PRSPI2)) -#define power_spi2_disable() (PRR2 |= (uint8_t)(1 << PRSPI2)) -#endif - -#if defined(__AVR_HAVE_PRR2_PRSSM) -#define power_sequencer_state_machine_enable() (PRR2 &= (uint8_t)~(1 << PRSSM)) -#define power_sequencer_state_machine_disable() (PRR2 |= (uint8_t)(1 << PRSSM)) -#endif - -#if defined(__AVR_HAVE_PRR2_PRTM) -#define power_tx_modulator_enable() (PRR2 &= (uint8_t)~(1 << PRTM)) -#define power_tx_modulator_disable() (PRR2 |= (uint8_t)(1 << PRTM)) -#endif - -#if defined(__AVR_HAVE_PRR2_PRTWI2) -#define power_twi2_enable() (PRR2 &= (uint8_t)~(1 << PRTWI2)) -#define power_twi2_disable() (PRR2 |= (uint8_t)(1 << PRTWI2)) -#endif - -#if defined(__AVR_HAVE_PRR2_PRXA) -#define power_rx_buffer_A_enable() (PRR2 &= (uint8_t)~(1 << PRXA)) -#define power_rx_buffer_A_disable() (PRR2 |= (uint8_t)(1 << PRXA)) -#endif - -#if defined(__AVR_HAVE_PRR2_PRXB) -#define power_rx_buffer_B_enable() (PRR2 &= (uint8_t)~(1 << PRXB)) -#define power_rx_buffer_B_disable() (PRR2 |= (uint8_t)(1 << PRXB)) -#endif - -#if defined(__AVR_HAVE_PRGEN_AES) -#define power_aes_enable() (PR_PRGEN &= (uint8_t)~(PR_AES_bm)) -#define power_aes_disable() (PR_PRGEN |= (uint8_t)PR_AES_bm) -#endif - -#if defined(__AVR_HAVE_PRGEN_DMA) -#define power_dma_enable() (PR_PRGEN &= (uint8_t)~(PR_DMA_bm)) -#define power_dma_disable() (PR_PRGEN |= (uint8_t)PR_DMA_bm) -#endif - -#if defined(__AVR_HAVE_PRGEN_EBI) -#define power_ebi_enable() (PR_PRGEN &= (uint8_t)~(PR_EBI_bm)) -#define power_ebi_disable() (PR_PRGEN |= (uint8_t)PR_EBI_bm) -#endif - -#if defined(__AVR_HAVE_PRGEN_EDMA) -#define power_edma_enable() (PR_PRGEN &= (uint8_t)~(PR_EDMA_bm)) -#define power_edma_disable() (PR_PRGEN |= (uint8_t)PR_EDMA_bm) -#endif - -#if defined(__AVR_HAVE_PRGEN_EVSYS) -#define power_evsys_enable() (PR_PRGEN &= (uint8_t)~(PR_EVSYS_bm)) -#define power_evsys_disable() (PR_PRGEN |= (uint8_t)PR_EVSYS_bm) -#endif - -#if defined(__AVR_HAVE_PRGEN_LCD) -#define power_lcd_enable() (PR_PRGEN &= (uint8_t)~(PR_LCD_bm)) -#define power_lcd_disable() (PR_PRGEN |= (uint8_t)PR_LCD_bm) -#endif - -#if defined(__AVR_HAVE_PRGEN_RTC) -#define power_rtc_enable() (PR_PRGEN &= (uint8_t)~(PR_RTC_bm)) -#define power_rtc_disable() (PR_PRGEN |= (uint8_t)PR_RTC_bm) -#endif - -#if defined(__AVR_HAVE_PRGEN_USB) -#define power_usb_enable() (PR_PRGEN &= (uint8_t)~(PR_USB_bm)) -#define power_usb_disable() (PR_PRGEN &= (uint8_t)(PR_USB_bm)) -#endif - -#if defined(__AVR_HAVE_PRGEN_XCL) -#define power_xcl_enable() (PR_PRGEN &= (uint8_t)~(PR_XCL_bm)) -#define power_xcl_disable() (PR_PRGEN |= (uint8_t)PR_XCL_bm) -#endif - -#if defined(__AVR_HAVE_PRPA_AC) -#define power_aca_enable() (PR_PRPA &= (uint8_t)~(PR_AC_bm)) -#define power_aca_disable() (PR_PRPA |= (uint8_t)PR_AC_bm) -#endif - -#if defined(__AVR_HAVE_PRPA_ADC) -#define power_adca_enable() (PR_PRPA &= (uint8_t)~(PR_ADC_bm)) -#define power_adca_disable() (PR_PRPA |= (uint8_t)PR_ADC_bm) -#endif - -#if defined(__AVR_HAVE_PRPA_DAC) -#define power_daca_enable() (PR_PRPA &= (uint8_t)~(PR_DAC_bm)) -#define power_daca_disable() (PR_PRPA |= (uint8_t)PR_DAC_bm) -#endif - -#if defined(__AVR_HAVE_PRPB_AC) -#define power_acb_enable() (PR_PRPB &= (uint8_t)~(PR_AC_bm)) -#define power_acb_disable() (PR_PRPB |= (uint8_t)PR_AC_bm) -#endif - -#if defined(__AVR_HAVE_PRPB_ADC) -#define power_adcb_enable() (PR_PRPB &= (uint8_t)~(PR_ADC_bm)) -#define power_adcb_disable() (PR_PRPB |= (uint8_t)PR_ADC_bm) -#endif - -#if defined(__AVR_HAVE_PRPB_DAC) -#define power_dacb_enable() (PR_PRPB &= (uint8_t)~(PR_DAC_bm)) -#define power_dacb_disable() (PR_PRPB |= (uint8_t)PR_DAC_bm) -#endif - -#if defined(__AVR_HAVE_PRPC_HIRES) -#define power_hiresc_enable() (PR_PRPC &= (uint8_t)~(PR_HIRES_bm)) -#define power_hiresc_disable() (PR_PRPC |= (uint8_t)PR_HIRES_bm) -#endif - -#if defined(__AVR_HAVE_PRPC_SPI) -#define power_spic_enable() (PR_PRPC &= (uint8_t)~(PR_SPI_bm)) -#define power_spic_disable() (PR_PRPC |= (uint8_t)PR_SPI_bm) -#endif - -#if defined(__AVR_HAVE_PRPC_TC0) -#define power_tc0c_enable() (PR_PRPC &= (uint8_t)~(PR_TC0_bm)) -#define power_tc0c_disable() (PR_PRPC |= (uint8_t)PR_TC0_bm) -#endif - -#if defined(__AVR_HAVE_PRPC_TC1) -#define power_tc1c_enable() (PR_PRPC &= (uint8_t)~(PR_TC1_bm)) -#define power_tc1c_disable() (PR_PRPC |= (uint8_t)PR_TC1_bm) -#endif - -#if defined(__AVR_HAVE_PRPC_TC4) -#define power_tc4c_enable() (PR_PRPC &= (uint8_t)~(PR_TC4_bm)) -#define power_tc4c_disable() (PR_PRPC |= (uint8_t)PR_TC4_bm) -#endif - -#if defined(__AVR_HAVE_PRPC_TC5) -#define power_tc5c_enable() (PR_PRPC &= (uint8_t)~(PR_TC5_bm)) -#define power_tc5c_disable() (PR_PRPC |= (uint8_t)PR_TC5_bm) -#endif - -#if defined(__AVR_HAVE_PRPC_TWI) -#define power_twic_enable() (PR_PRPC &= (uint8_t)~(PR_TWI_bm)) -#define power_twic_disable() (PR_PRPC |= (uint8_t)PR_TWI_bm) -#endif - -#if defined(__AVR_HAVE_PRPC_USART0) -#define power_usartc0_enable() (PR_PRPC &= (uint8_t)~(PR_USART0_bm)) -#define power_usartc0_disable() (PR_PRPC |= (uint8_t)PR_USART0_bm) -#endif - -#if defined(__AVR_HAVE_PRPC_USART1) -#define power_usartc1_enable() (PR_PRPC &= (uint8_t)~(PR_USART1_bm)) -#define power_usartc1_disable() (PR_PRPC |= (uint8_t)PR_USART1_bm) -#endif - -#if defined(__AVR_HAVE_PRPD_HIRES) -#define power_hiresd_enable() (PR_PRPD &= (uint8_t)~(PR_HIRES_bm)) -#define power_hiresd_disable() (PR_PRPD |= (uint8_t)PR_HIRES_bm) -#endif - -#if defined(__AVR_HAVE_PRPD_SPI) -#define power_spid_enable() (PR_PRPD &= (uint8_t)~(PR_SPI_bm)) -#define power_spid_disable() (PR_PRPD |= (uint8_t)PR_SPI_bm) -#endif - -#if defined(__AVR_HAVE_PRPD_TC0) -#define power_tc0d_enable() (PR_PRPD &= (uint8_t)~(PR_TC0_bm)) -#define power_tc0d_disable() (PR_PRPD |= (uint8_t)PR_TC0_bm) -#endif - -#if defined(__AVR_HAVE_PRPD_TC1) -#define power_tc1d_enable() (PR_PRPD &= (uint8_t)~(PR_TC1_bm)) -#define power_tc1d_disable() (PR_PRPD |= (uint8_t)PR_TC1_bm) -#endif - -#if defined(__AVR_HAVE_PRPD_TC5) -#define power_tc5d_enable() (PR_PRPD &= (uint8_t)~(PR_TC5_bm)) -#define power_tc5d_disable() (PR_PRPD |= (uint8_t)PR_TC5_bm) -#endif - -#if defined(__AVR_HAVE_PRPD_TWI) -#define power_twid_enable() (PR_PRPD &= (uint8_t)~(PR_TWI_bm)) -#define power_twid_disable() (PR_PRPD |= (uint8_t)PR_TWI_bm) -#endif - -#if defined(__AVR_HAVE_PRPD_USART0) -#define power_usartd0_enable() (PR_PRPD &= (uint8_t)~(PR_USART0_bm)) -#define power_usartd0_disable() (PR_PRPD |= (uint8_t)PR_USART0_bm) -#endif - -#if defined(__AVR_HAVE_PRPD_USART1) -#define power_usartd1_enable() (PR_PRPD &= (uint8_t)~(PR_USART1_bm)) -#define power_usartd1_disable() (PR_PRPD |= (uint8_t)PR_USART1_bm) -#endif - -#if defined(__AVR_HAVE_PRPE_HIRES) -#define power_hirese_enable() (PR_PRPE &= (uint8_t)~(PR_HIRES_bm)) -#define power_hirese_disable() (PR_PRPE |= (uint8_t)PR_HIRES_bm) -#endif - -#if defined(__AVR_HAVE_PRPE_SPI) -#define power_spie_enable() (PR_PRPE &= (uint8_t)~(PR_SPI_bm)) -#define power_spie_disable() (PR_PRPE |= (uint8_t)PR_SPI_bm) -#endif - -#if defined(__AVR_HAVE_PRPE_TC0) -#define power_tc0e_enable() (PR_PRPE &= (uint8_t)~(PR_TC0_bm)) -#define power_tc0e_disable() (PR_PRPE |= (uint8_t)PR_TC0_bm) -#endif - -#if defined(__AVR_HAVE_PRPE_TC1) -#define power_tc1e_enable() (PR_PRPE &= (uint8_t)~(PR_TC1_bm)) -#define power_tc1e_disable() (PR_PRPE |= (uint8_t)PR_TC1_bm) -#endif - -#if defined(__AVR_HAVE_PRPE_TWI) -#define power_twie_enable() (PR_PRPE &= (uint8_t)~(PR_TWI_bm)) -#define power_twie_disable() (PR_PRPE |= (uint8_t)PR_TWI_bm) -#endif - -#if defined(__AVR_HAVE_PRPE_USART0) -#define power_usarte0_enable() (PR_PRPE &= (uint8_t)~(PR_USART0_bm)) -#define power_usarte0_disable() (PR_PRPE |= (uint8_t)PR_USART0_bm) -#endif - -#if defined(__AVR_HAVE_PRPE_USART1) -#define power_usarte1_enable() (PR_PRPE &= (uint8_t)~(PR_USART1_bm)) -#define power_usarte1_disable() (PR_PRPE |= (uint8_t)PR_USART1_bm) -#endif - -#if defined(__AVR_HAVE_PRPF_HIRES) -#define power_hiresf_enable() (PR_PRPF &= (uint8_t)~(PR_HIRES_bm)) -#define power_hiresf_disable() (PR_PRPF |= (uint8_t)PR_HIRES_bm) -#endif - -#if defined(__AVR_HAVE_PRPF_SPI) -#define power_spif_enable() (PR_PRPF &= (uint8_t)~(PR_SPI_bm)) -#define power_spif_disable() (PR_PRPF |= (uint8_t)PR_SPI_bm) -#endif - -#if defined(__AVR_HAVE_PRPF_TC0) -#define power_tc0f_enable() (PR_PRPF &= (uint8_t)~(PR_TC0_bm)) -#define power_tc0f_disable() (PR_PRPF |= (uint8_t)PR_TC0_bm) -#endif - -#if defined(__AVR_HAVE_PRPF_TC1) -#define power_tc1f_enable() (PR_PRPF &= (uint8_t)~(PR_TC1_bm)) -#define power_tc1f_disable() (PR_PRPF |= (uint8_t)PR_TC1_bm) -#endif - -#if defined(__AVR_HAVE_PRPF_TWI) -#define power_twif_enable() (PR_PRPF &= (uint8_t)~(PR_TWI_bm)) -#define power_twif_disable() (PR_PRPF |= (uint8_t)PR_TWI_bm) -#endif - -#if defined(__AVR_HAVE_PRPF_USART0) -#define power_usartf0_enable() (PR_PRPF &= (uint8_t)~(PR_USART0_bm)) -#define power_usartf0_disable() (PR_PRPF |= (uint8_t)PR_USART0_bm) -#endif - -#if defined(__AVR_HAVE_PRPF_USART1) -#define power_usartf1_enable() (PR_PRPF &= (uint8_t)~(PR_USART1_bm)) -#define power_usartf1_disable() (PR_PRPF |= (uint8_t)PR_USART1_bm) -#endif - -static __inline void -__attribute__ ((__always_inline__)) -__power_all_enable() -{ -#ifdef __AVR_HAVE_PRR - PRR &= (uint8_t)~(__AVR_HAVE_PRR); -#endif - -#ifdef __AVR_HAVE_PRR0 - PRR0 &= (uint8_t)~(__AVR_HAVE_PRR0); -#endif - -#ifdef __AVR_HAVE_PRR1 - PRR1 &= (uint8_t)~(__AVR_HAVE_PRR1); -#endif - -#ifdef __AVR_HAVE_PRR2 - PRR2 &= (uint8_t)~(__AVR_HAVE_PRR2); -#endif - -#ifdef __AVR_HAVE_PRGEN - PR_PRGEN &= (uint8_t)~(__AVR_HAVE_PRGEN); -#endif - -#ifdef __AVR_HAVE_PRPA - PR_PRPA &= (uint8_t)~(__AVR_HAVE_PRPA); -#endif - -#ifdef __AVR_HAVE_PRPB - PR_PRPB &= (uint8_t)~(__AVR_HAVE_PRPB); -#endif - -#ifdef __AVR_HAVE_PRPC - PR_PRPC &= (uint8_t)~(__AVR_HAVE_PRPC); -#endif - -#ifdef __AVR_HAVE_PRPD - PR_PRPD &= (uint8_t)~(__AVR_HAVE_PRPD); -#endif - -#ifdef __AVR_HAVE_PRPE - PR_PRPE &= (uint8_t)~(__AVR_HAVE_PRPE); -#endif - -#ifdef __AVR_HAVE_PRPF - PR_PRPF &= (uint8_t)~(__AVR_HAVE_PRPF); -#endif -} - -static __inline void -__attribute__ ((__always_inline__)) -__power_all_disable() -{ -#ifdef __AVR_HAVE_PRR - PRR |= (uint8_t)(__AVR_HAVE_PRR); -#endif - -#ifdef __AVR_HAVE_PRR0 - PRR0 |= (uint8_t)(__AVR_HAVE_PRR0); -#endif - -#ifdef __AVR_HAVE_PRR1 - PRR1 |= (uint8_t)(__AVR_HAVE_PRR1); -#endif - -#ifdef __AVR_HAVE_PRR2 - PRR2 |= (uint8_t)(__AVR_HAVE_PRR2); -#endif - -#ifdef __AVR_HAVE_PRGEN - PR_PRGEN |= (uint8_t)(__AVR_HAVE_PRGEN); -#endif - -#ifdef __AVR_HAVE_PRPA - PR_PRPA |= (uint8_t)(__AVR_HAVE_PRPA); -#endif - -#ifdef __AVR_HAVE_PRPB - PR_PRPB |= (uint8_t)(__AVR_HAVE_PRPB); -#endif - -#ifdef __AVR_HAVE_PRPC - PR_PRPC |= (uint8_t)(__AVR_HAVE_PRPC); -#endif - -#ifdef __AVR_HAVE_PRPD - PR_PRPD |= (uint8_t)(__AVR_HAVE_PRPD); -#endif - -#ifdef __AVR_HAVE_PRPE - PR_PRPE |= (uint8_t)(__AVR_HAVE_PRPE); -#endif - -#ifdef __AVR_HAVE_PRPF - PR_PRPF |= (uint8_t)(__AVR_HAVE_PRPF); -#endif -} - -#ifndef __DOXYGEN__ -#ifndef power_all_enable -#define power_all_enable() __power_all_enable() -#endif - -#ifndef power_all_disable -#define power_all_disable() __power_all_disable() -#endif -#endif /* !__DOXYGEN__ */ - - -#if defined(__AVR_AT90CAN32__) \ -|| defined(__AVR_AT90CAN64__) \ -|| defined(__AVR_AT90CAN128__) \ -|| defined(__AVR_AT90PWM1__) \ -|| defined(__AVR_AT90PWM2__) \ -|| defined(__AVR_AT90PWM2B__) \ -|| defined(__AVR_AT90PWM3__) \ -|| defined(__AVR_AT90PWM3B__) \ -|| defined(__AVR_AT90PWM81__) \ -|| defined(__AVR_AT90PWM161__) \ -|| defined(__AVR_AT90PWM216__) \ -|| defined(__AVR_AT90PWM316__) \ -|| defined(__AVR_AT90SCR100__) \ -|| defined(__AVR_AT90USB646__) \ -|| defined(__AVR_AT90USB647__) \ -|| defined(__AVR_AT90USB82__) \ -|| defined(__AVR_AT90USB1286__) \ -|| defined(__AVR_AT90USB1287__) \ -|| defined(__AVR_AT90USB162__) \ -|| defined(__AVR_ATA5505__) \ -|| defined(__AVR_ATA5272__) \ -|| defined(__AVR_ATA6617C__) \ -|| defined(__AVR_ATA664251__) \ -|| defined(__AVR_ATmega1280__) \ -|| defined(__AVR_ATmega1281__) \ -|| defined(__AVR_ATmega1284__) \ -|| defined(__AVR_ATmega128RFA1__) \ -|| defined(__AVR_ATmega1284RFR2__) \ -|| defined(__AVR_ATmega128RFR2__) \ -|| defined(__AVR_ATmega1284P__) \ -|| defined(__AVR_ATmega162__) \ -|| defined(__AVR_ATmega164A__) \ -|| defined(__AVR_ATmega164P__) \ -|| defined(__AVR_ATmega164PA__) \ -|| defined(__AVR_ATmega165__) \ -|| defined(__AVR_ATmega165A__) \ -|| defined(__AVR_ATmega165P__) \ -|| defined(__AVR_ATmega165PA__) \ -|| defined(__AVR_ATmega168__) \ -|| defined(__AVR_ATmega168A__) \ -|| defined(__AVR_ATmega168P__) \ -|| defined(__AVR_ATmega168PA__) \ -|| defined(__AVR_ATmega168PB__) \ -|| defined(__AVR_ATmega169__) \ -|| defined(__AVR_ATmega169A__) \ -|| defined(__AVR_ATmega169P__) \ -|| defined(__AVR_ATmega169PA__) \ -|| defined(__AVR_ATmega16M1__) \ -|| defined(__AVR_ATmega16U2__) \ -|| defined(__AVR_ATmega16U4__) \ -|| defined(__AVR_ATmega2560__) \ -|| defined(__AVR_ATmega2561__) \ -|| defined(__AVR_ATmega2564RFR2__) \ -|| defined(__AVR_ATmega256RFR2__) \ -|| defined(__AVR_ATmega324A__) \ -|| defined(__AVR_ATmega324P__) \ -|| defined(__AVR_ATmega324PA__) \ -|| defined(__AVR_ATmega325__) \ -|| defined(__AVR_ATmega325A__) \ -|| defined(__AVR_ATmega325P__) \ -|| defined(__AVR_ATmega325PA__) \ -|| defined(__AVR_ATmega3250__) \ -|| defined(__AVR_ATmega3250A__) \ -|| defined(__AVR_ATmega3250P__) \ -|| defined(__AVR_ATmega3250PA__) \ -|| defined(__AVR_ATmega328__) \ -|| defined(__AVR_ATmega328P__) \ -|| defined(__AVR_ATmega329__) \ -|| defined(__AVR_ATmega329A__) \ -|| defined(__AVR_ATmega329P__) \ -|| defined(__AVR_ATmega329PA__) \ -|| defined(__AVR_ATmega3290__) \ -|| defined(__AVR_ATmega3290A__) \ -|| defined(__AVR_ATmega3290P__) \ -|| defined(__AVR_ATmega3290PA__) \ -|| defined(__AVR_ATmega32C1__) \ -|| defined(__AVR_ATmega32M1__) \ -|| defined(__AVR_ATmega32U2__) \ -|| defined(__AVR_ATmega32U4__) \ -|| defined(__AVR_ATmega32U6__) \ -|| defined(__AVR_ATmega48__) \ -|| defined(__AVR_ATmega48A__) \ -|| defined(__AVR_ATmega48PA__) \ -|| defined(__AVR_ATmega48PB__) \ -|| defined(__AVR_ATmega48P__) \ -|| defined(__AVR_ATmega640__) \ -|| defined(__AVR_ATmega649P__) \ -|| defined(__AVR_ATmega644__) \ -|| defined(__AVR_ATmega644A__) \ -|| defined(__AVR_ATmega644P__) \ -|| defined(__AVR_ATmega644PA__) \ -|| defined(__AVR_ATmega645__) \ -|| defined(__AVR_ATmega645A__) \ -|| defined(__AVR_ATmega645P__) \ -|| defined(__AVR_ATmega6450__) \ -|| defined(__AVR_ATmega6450A__) \ -|| defined(__AVR_ATmega6450P__) \ -|| defined(__AVR_ATmega649__) \ -|| defined(__AVR_ATmega649A__) \ -|| defined(__AVR_ATmega64M1__) \ -|| defined(__AVR_ATmega64C1__) \ -|| defined(__AVR_ATmega88A__) \ -|| defined(__AVR_ATmega88PA__) \ -|| defined(__AVR_ATmega88PB__) \ -|| defined(__AVR_ATmega6490__) \ -|| defined(__AVR_ATmega6490A__) \ -|| defined(__AVR_ATmega6490P__) \ -|| defined(__AVR_ATmega644RFR2__) \ -|| defined(__AVR_ATmega64RFR2__) \ -|| defined(__AVR_ATmega88__) \ -|| defined(__AVR_ATmega88P__) \ -|| defined(__AVR_ATmega8U2__) \ -|| defined(__AVR_ATmega16U2__) \ -|| defined(__AVR_ATmega32U2__) \ -|| defined(__AVR_ATtiny48__) \ -|| defined(__AVR_ATtiny88__) \ -|| defined(__AVR_ATtiny87__) \ -|| defined(__AVR_ATtiny167__) \ -|| defined(__DOXYGEN__) - - -/** \addtogroup avr_power - -Some of the newer AVRs contain a System Clock Prescale Register (CLKPR) that -allows you to decrease the system clock frequency and the power consumption -when the need for processing power is low. -On some earlier AVRs (ATmega103, ATmega64, ATmega128), similar -functionality can be achieved through the XTAL Divide Control Register. -Below are two macros and an enumerated type that can be used to -interface to the Clock Prescale Register or -XTAL Divide Control Register. - -\note Not all AVR devices have a clock prescaler. On those devices -without a Clock Prescale Register or XTAL Divide Control Register, these -macros are not available. -*/ - - -/** \addtogroup avr_power -\code -typedef enum -{ - clock_div_1 = 0, - clock_div_2 = 1, - clock_div_4 = 2, - clock_div_8 = 3, - clock_div_16 = 4, - clock_div_32 = 5, - clock_div_64 = 6, - clock_div_128 = 7, - clock_div_256 = 8, - clock_div_1_rc = 15, // ATmega128RFA1 only -} clock_div_t; -\endcode -Clock prescaler setting enumerations for device using -System Clock Prescale Register. - -\code -typedef enum -{ - clock_div_1 = 1, - clock_div_2 = 2, - clock_div_4 = 4, - clock_div_8 = 8, - clock_div_16 = 16, - clock_div_32 = 32, - clock_div_64 = 64, - clock_div_128 = 128 -} clock_div_t; -\endcode -Clock prescaler setting enumerations for device using -XTAL Divide Control Register. - -*/ -#ifndef __DOXYGEN__ -typedef enum -{ - clock_div_1 = 0, - clock_div_2 = 1, - clock_div_4 = 2, - clock_div_8 = 3, - clock_div_16 = 4, - clock_div_32 = 5, - clock_div_64 = 6, - clock_div_128 = 7, - clock_div_256 = 8 -#if defined(__AVR_ATmega128RFA1__) \ -|| defined(__AVR_ATmega2564RFR2__) \ -|| defined(__AVR_ATmega1284RFR2__) \ -|| defined(__AVR_ATmega644RFR2__) \ -|| defined(__AVR_ATmega256RFR2__) \ -|| defined(__AVR_ATmega128RFR2__) \ -|| defined(__AVR_ATmega64RFR2__) - , clock_div_1_rc = 15 -#endif -} clock_div_t; - -static __inline__ void clock_prescale_set(clock_div_t) __attribute__((__always_inline__)); -#endif /* !__DOXYGEN__ */ - -/** - \ingroup avr_power - \fn clock_prescale_set(clock_div_t x) - -Set the clock prescaler register select bits, selecting a system clock -division setting. This function is inlined, even if compiler -optimizations are disabled. - -The type of \c x is \c clock_div_t. - -\note For device with XTAL Divide Control Register (XDIV), \c x can actually range -from 1 to 129. Thus, one does not need to use \c clock_div_t type as argument. -*/ -void clock_prescale_set(clock_div_t __x) -{ - uint8_t __tmp = _BV(CLKPCE); - __asm__ __volatile__ ( - "in __tmp_reg__,__SREG__" "\n\t" - "cli" "\n\t" - "sts %1, %0" "\n\t" - "sts %1, %2" "\n\t" - "out __SREG__, __tmp_reg__" - : /* no outputs */ - : "d" (__tmp), - "M" (_SFR_MEM_ADDR(CLKPR)), - "d" (__x) - : "r0"); -} - -/** \addtogroup avr_power -\def clock_prescale_get() -Gets and returns the clock prescaler register setting. The return type is \c clock_div_t. - -\note For device with XTAL Divide Control Register (XDIV), return can actually -range from 1 to 129. Care should be taken has the return value could differ from the -typedef enum clock_div_t. This should only happen if clock_prescale_set was previously -called with a value other than those defined by \c clock_div_t. -*/ -#define clock_prescale_get() (clock_div_t)(CLKPR & (uint8_t)((1< 129)) - { - return;//Invalid value. - } - else - { - uint8_t __tmp = 0; - //Algo explained: - //1 - Clear XDIV in order for it to accept a new value (actually only - // XDIVEN need to be cleared, but clearing XDIV is faster than - // read-modify-write since we will rewrite XDIV later anyway) - //2 - wait 8 clock cycle for stability, see datasheet erreta - //3 - Exist if requested prescaller is 1 - //4 - Calculate XDIV6..0 value = 129 - __x - //5 - Set XDIVEN bit in calculated value - //6 - write XDIV with calculated value - //7 - wait 8 clock cycle for stability, see datasheet erreta - __asm__ __volatile__ ( - "in __tmp_reg__,__SREG__" "\n\t" - "cli" "\n\t" - "out %1, __zero_reg__" "\n\t" - "nop" "\n\t" - "nop" "\n\t" - "nop" "\n\t" - "nop" "\n\t" - "nop" "\n\t" - "nop" "\n\t" - "nop" "\n\t" - "nop" "\n\t" - "cpi %0, 0x01" "\n\t" - "breq L_%=" "\n\t" - "ldi %2, 0x81" "\n\t" //129 - "sub %2, %0" "\n\t" - "ori %2, 0x80" "\n\t" //128 - "out %1, %2" "\n\t" - "nop" "\n\t" - "nop" "\n\t" - "nop" "\n\t" - "nop" "\n\t" - "nop" "\n\t" - "nop" "\n\t" - "nop" "\n\t" - "nop" "\n\t" - "L_%=: " "out __SREG__, __tmp_reg__" - : /* no outputs */ - :"d" (__x), - "I" (_SFR_IO_ADDR(XDIV)), - "d" (__tmp) - : "r0"); - } -} - -static __inline__ clock_div_t clock_prescale_get(void) __attribute__((__always_inline__)); - -clock_div_t clock_prescale_get(void) -{ - if(bit_is_clear(XDIV, XDIVEN)) - { - return 1; - } - else - { - return (clock_div_t)(129 - (XDIV & 0x7F)); - } -} - -#elif defined(__AVR_ATtiny4__) \ -|| defined(__AVR_ATtiny5__) \ -|| defined(__AVR_ATtiny9__) \ -|| defined(__AVR_ATtiny10__) \ -|| defined(__AVR_ATtiny20__) \ -|| defined(__AVR_ATtiny40__) \ - -typedef enum -{ - clock_div_1 = 0, - clock_div_2 = 1, - clock_div_4 = 2, - clock_div_8 = 3, - clock_div_16 = 4, - clock_div_32 = 5, - clock_div_64 = 6, - clock_div_128 = 7, - clock_div_256 = 8 -} clock_div_t; - -static __inline__ void clock_prescale_set(clock_div_t) __attribute__((__always_inline__)); - -void clock_prescale_set(clock_div_t __x) -{ - uint8_t __tmp = 0xD8; - __asm__ __volatile__ ( - "in __tmp_reg__,__SREG__" "\n\t" - "cli" "\n\t" - "out %1, %0" "\n\t" - "out %2, %3" "\n\t" - "out __SREG__, __tmp_reg__" - : /* no outputs */ - : "d" (__tmp), - "I" (_SFR_IO_ADDR(CCP)), - "I" (_SFR_IO_ADDR(CLKPSR)), - "d" (__x) - : "r16"); -} - -#define clock_prescale_get() (clock_div_t)(CLKPSR & (uint8_t)((1< - All rights reserved. - - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - * Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - * Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in - the documentation and/or other materials provided with the - distribution. - - * Neither the name of the copyright holders nor the names of - contributors may be used to endorse or promote products derived - from this software without specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. */ - -/* avr/sfr_defs.h - macros for accessing AVR special function registers */ - -/* $Id$ */ - -#ifndef _AVR_SFR_DEFS_H_ -#define _AVR_SFR_DEFS_H_ 1 - -/** \defgroup avr_sfr_notes Additional notes from - \ingroup avr_sfr - - The \c file is included by all of the \c - files, which use macros defined here to make the special function register - definitions look like C variables or simple constants, depending on the - _SFR_ASM_COMPAT define. Some examples from \c to - show how to define such macros: - -\code -#define PORTA _SFR_IO8(0x02) -#define EEAR _SFR_IO16(0x21) -#define UDR0 _SFR_MEM8(0xC6) -#define TCNT3 _SFR_MEM16(0x94) -#define CANIDT _SFR_MEM32(0xF0) -\endcode - - If \c _SFR_ASM_COMPAT is not defined, C programs can use names like - PORTA directly in C expressions (also on the left side of - assignment operators) and GCC will do the right thing (use short I/O - instructions if possible). The \c __SFR_OFFSET definition is not used in - any way in this case. - - Define \c _SFR_ASM_COMPAT as 1 to make these names work as simple constants - (addresses of the I/O registers). This is necessary when included in - preprocessed assembler (*.S) source files, so it is done automatically if - \c __ASSEMBLER__ is defined. By default, all addresses are defined as if - they were memory addresses (used in \c lds/sts instructions). To use these - addresses in \c in/out instructions, you must subtract 0x20 from them. - - For more backwards compatibility, insert the following at the start of your - old assembler source file: - -\code -#define __SFR_OFFSET 0 -\endcode - - This automatically subtracts 0x20 from I/O space addresses, but it's a - hack, so it is recommended to change your source: wrap such addresses in - macros defined here, as shown below. After this is done, the - __SFR_OFFSET definition is no longer necessary and can be removed. - - Real example - this code could be used in a boot loader that is portable - between devices with \c SPMCR at different addresses. - -\verbatim -: #define SPMCR _SFR_IO8(0x37) -: #define SPMCR _SFR_MEM8(0x68) -\endverbatim - -\code -#if _SFR_IO_REG_P(SPMCR) - out _SFR_IO_ADDR(SPMCR), r24 -#else - sts _SFR_MEM_ADDR(SPMCR), r24 -#endif -\endcode - - You can use the \c in/out/cbi/sbi/sbic/sbis instructions, without the - _SFR_IO_REG_P test, if you know that the register is in the I/O - space (as with \c SREG, for example). If it isn't, the assembler will - complain (I/O address out of range 0...0x3f), so this should be fairly - safe. - - If you do not define \c __SFR_OFFSET (so it will be 0x20 by default), all - special register addresses are defined as memory addresses (so \c SREG is - 0x5f), and (if code size and speed are not important, and you don't like - the ugly \#if above) you can always use lds/sts to access them. But, this - will not work if __SFR_OFFSET != 0x20, so use a different macro - (defined only if __SFR_OFFSET == 0x20) for safety: - -\code - sts _SFR_ADDR(SPMCR), r24 -\endcode - - In C programs, all 3 combinations of \c _SFR_ASM_COMPAT and - __SFR_OFFSET are supported - the \c _SFR_ADDR(SPMCR) macro can be - used to get the address of the \c SPMCR register (0x57 or 0x68 depending on - device). */ - -#ifdef __ASSEMBLER__ -#define _SFR_ASM_COMPAT 1 -#elif !defined(_SFR_ASM_COMPAT) -#define _SFR_ASM_COMPAT 0 -#endif - -#ifndef __ASSEMBLER__ -/* These only work in C programs. */ -#include - -#define _MMIO_BYTE(mem_addr) (*(volatile uint8_t *)(mem_addr)) -#define _MMIO_WORD(mem_addr) (*(volatile uint16_t *)(mem_addr)) -#define _MMIO_DWORD(mem_addr) (*(volatile uint32_t *)(mem_addr)) -#endif - -#if _SFR_ASM_COMPAT - -#ifndef __SFR_OFFSET -/* Define as 0 before including this file for compatibility with old asm - sources that don't subtract __SFR_OFFSET from symbolic I/O addresses. */ -# if __AVR_ARCH__ >= 100 -# define __SFR_OFFSET 0x00 -# else -# define __SFR_OFFSET 0x20 -# endif -#endif - -#if (__SFR_OFFSET != 0) && (__SFR_OFFSET != 0x20) -#error "__SFR_OFFSET must be 0 or 0x20" -#endif - -#define _SFR_MEM8(mem_addr) (mem_addr) -#define _SFR_MEM16(mem_addr) (mem_addr) -#define _SFR_MEM32(mem_addr) (mem_addr) -#define _SFR_IO8(io_addr) ((io_addr) + __SFR_OFFSET) -#define _SFR_IO16(io_addr) ((io_addr) + __SFR_OFFSET) - -#define _SFR_IO_ADDR(sfr) ((sfr) - __SFR_OFFSET) -#define _SFR_MEM_ADDR(sfr) (sfr) -#define _SFR_IO_REG_P(sfr) ((sfr) < 0x40 + __SFR_OFFSET) - -#if (__SFR_OFFSET == 0x20) -/* No need to use ?: operator, so works in assembler too. */ -#define _SFR_ADDR(sfr) _SFR_MEM_ADDR(sfr) -#elif !defined(__ASSEMBLER__) -#define _SFR_ADDR(sfr) (_SFR_IO_REG_P(sfr) ? (_SFR_IO_ADDR(sfr) + 0x20) : _SFR_MEM_ADDR(sfr)) -#endif - -#else /* !_SFR_ASM_COMPAT */ - -#ifndef __SFR_OFFSET -# if __AVR_ARCH__ >= 100 -# define __SFR_OFFSET 0x00 -# else -# define __SFR_OFFSET 0x20 -# endif -#endif - -#define _SFR_MEM8(mem_addr) _MMIO_BYTE(mem_addr) -#define _SFR_MEM16(mem_addr) _MMIO_WORD(mem_addr) -#define _SFR_MEM32(mem_addr) _MMIO_DWORD(mem_addr) -#define _SFR_IO8(io_addr) _MMIO_BYTE((io_addr) + __SFR_OFFSET) -#define _SFR_IO16(io_addr) _MMIO_WORD((io_addr) + __SFR_OFFSET) - -#define _SFR_MEM_ADDR(sfr) ((uint16_t) &(sfr)) -#define _SFR_IO_ADDR(sfr) (_SFR_MEM_ADDR(sfr) - __SFR_OFFSET) -#define _SFR_IO_REG_P(sfr) (_SFR_MEM_ADDR(sfr) < 0x40 + __SFR_OFFSET) - -#define _SFR_ADDR(sfr) _SFR_MEM_ADDR(sfr) - -#endif /* !_SFR_ASM_COMPAT */ - -#define _SFR_BYTE(sfr) _MMIO_BYTE(_SFR_ADDR(sfr)) -#define _SFR_WORD(sfr) _MMIO_WORD(_SFR_ADDR(sfr)) -#define _SFR_DWORD(sfr) _MMIO_DWORD(_SFR_ADDR(sfr)) - -/** \name Bit manipulation */ - -/*@{*/ -/** \def _BV - \ingroup avr_sfr - - \code #include \endcode - - Converts a bit number into a byte value. - - \note The bit shift is performed by the compiler which then inserts the - result into the code. Thus, there is no run-time overhead when using - _BV(). */ - -#define _BV(bit) (1 << (bit)) - -/*@}*/ - -#ifndef _VECTOR -#define _VECTOR(N) __vector_ ## N -#endif - -#ifndef __ASSEMBLER__ - - -/** \name IO register bit manipulation */ - -/*@{*/ - - - -/** \def bit_is_set - \ingroup avr_sfr - - \code #include \endcode - - Test whether bit \c bit in IO register \c sfr is set. - This will return a 0 if the bit is clear, and non-zero - if the bit is set. */ - -#define bit_is_set(sfr, bit) (_SFR_BYTE(sfr) & _BV(bit)) - -/** \def bit_is_clear - \ingroup avr_sfr - - \code #include \endcode - - Test whether bit \c bit in IO register \c sfr is clear. - This will return non-zero if the bit is clear, and a 0 - if the bit is set. */ - -#define bit_is_clear(sfr, bit) (!(_SFR_BYTE(sfr) & _BV(bit))) - -/** \def loop_until_bit_is_set - \ingroup avr_sfr - - \code #include \endcode - - Wait until bit \c bit in IO register \c sfr is set. */ - -#define loop_until_bit_is_set(sfr, bit) do { } while (bit_is_clear(sfr, bit)) - -/** \def loop_until_bit_is_clear - \ingroup avr_sfr - - \code #include \endcode - - Wait until bit \c bit in IO register \c sfr is clear. */ - -#define loop_until_bit_is_clear(sfr, bit) do { } while (bit_is_set(sfr, bit)) - -/*@}*/ - -#endif /* !__ASSEMBLER__ */ - -#endif /* _SFR_DEFS_H_ */ diff --git a/arduino/hardware/tools/avr/avr/include/avr/signal.h b/arduino/hardware/tools/avr/avr/include/avr/signal.h deleted file mode 100644 index 8f83399..0000000 --- a/arduino/hardware/tools/avr/avr/include/avr/signal.h +++ /dev/null @@ -1,39 +0,0 @@ -/* Copyright (c) 2002,2005,2006 Marek Michalkiewicz - All rights reserved. - - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - * Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - * Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in - the documentation and/or other materials provided with the - distribution. - - * Neither the name of the copyright holders nor the names of - contributors may be used to endorse or promote products derived - from this software without specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. */ - -/* $Id$ */ - -#ifndef _AVR_SIGNAL_H_ -#define _AVR_SIGNAL_H_ - -#warning "This header file is obsolete. Use ." -#include - -#endif /* _AVR_SIGNAL_H_ */ diff --git a/arduino/hardware/tools/avr/avr/include/avr/signature.h b/arduino/hardware/tools/avr/avr/include/avr/signature.h deleted file mode 100644 index 40fea7b..0000000 --- a/arduino/hardware/tools/avr/avr/include/avr/signature.h +++ /dev/null @@ -1,85 +0,0 @@ -/* Copyright (c) 2009, Atmel Corporation - All rights reserved. - - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - * Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - * Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in - the documentation and/or other materials provided with the - distribution. - - * Neither the name of the copyright holders nor the names of - contributors may be used to endorse or promote products derived - from this software without specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. */ - -/* $Id$ */ - -/* avr/signature.h - Signature API */ - -#ifndef _AVR_SIGNATURE_H_ -#define _AVR_SIGNATURE_H_ 1 - -/** \file */ -/** \defgroup avr_signature : Signature Support - - \par Introduction - - The header file allows the user to automatically - and easily include the device's signature data in a special section of - the final linked ELF file. - - This value can then be used by programming software to compare the on-device - signature with the signature recorded in the ELF file to look for a match - before programming the device. - - \par API Usage Example - - Usage is very simple; just include the header file: - - \code - #include - \endcode - - This will declare a constant unsigned char array and it is initialized with - the three signature bytes, MSB first, that are defined in the device I/O - header file. This array is then placed in the .signature section in the - resulting linked ELF file. - - The three signature bytes that are used to initialize the array are - these defined macros in the device I/O header file, from MSB to LSB: - SIGNATURE_2, SIGNATURE_1, SIGNATURE_0. - - This header file should only be included once in an application. -*/ - -#ifndef __ASSEMBLER__ - -#include - -#if defined(SIGNATURE_0) && defined(SIGNATURE_1) && defined(SIGNATURE_2) - -const unsigned char __signature[3] -__attribute__((__used__, __section__(".signature"))) = - { SIGNATURE_2, SIGNATURE_1, SIGNATURE_0 }; - -#endif /* defined(SIGNATURE_0) && defined(SIGNATURE_1) && defined(SIGNATURE_2) */ - -#endif /* __ASSEMBLER__ */ - -#endif /* _AVR_SIGNATURE_H_ */ diff --git a/arduino/hardware/tools/avr/avr/include/avr/sleep.h b/arduino/hardware/tools/avr/avr/include/avr/sleep.h deleted file mode 100644 index fa0d8f0..0000000 --- a/arduino/hardware/tools/avr/avr/include/avr/sleep.h +++ /dev/null @@ -1,357 +0,0 @@ -/* Copyright (c) 2002, 2004 Theodore A. Roth - Copyright (c) 2004, 2007, 2008 Eric B. Weddington - Copyright (c) 2005, 2006, 2007 Joerg Wunsch - All rights reserved. - - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - * Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - * Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in - the documentation and/or other materials provided with the - distribution. - - * Neither the name of the copyright holders nor the names of - contributors may be used to endorse or promote products derived - from this software without specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. */ - -/* $Id$ */ - -#ifndef _AVR_SLEEP_H_ -#define _AVR_SLEEP_H_ 1 - -#include -#include - - -/** \file */ - -/** \defgroup avr_sleep : Power Management and Sleep Modes - - \code #include \endcode - - Use of the \c SLEEP instruction can allow an application to reduce its - power comsumption considerably. AVR devices can be put into different - sleep modes. Refer to the datasheet for the details relating to the device - you are using. - - There are several macros provided in this header file to actually - put the device into sleep mode. The simplest way is to optionally - set the desired sleep mode using \c set_sleep_mode() (it usually - defaults to idle mode where the CPU is put on sleep but all - peripheral clocks are still running), and then call - \c sleep_mode(). This macro automatically sets the sleep enable bit, goes - to sleep, and clears the sleep enable bit. - - Example: - \code - #include - - ... - set_sleep_mode(); - sleep_mode(); - \endcode - - Note that unless your purpose is to completely lock the CPU (until a - hardware reset), interrupts need to be enabled before going to sleep. - - As the \c sleep_mode() macro might cause race conditions in some - situations, the individual steps of manipulating the sleep enable - (SE) bit, and actually issuing the \c SLEEP instruction, are provided - in the macros \c sleep_enable(), \c sleep_disable(), and - \c sleep_cpu(). This also allows for test-and-sleep scenarios that - take care of not missing the interrupt that will awake the device - from sleep. - - Example: - \code - #include - #include - - ... - set_sleep_mode(); - cli(); - if (some_condition) - { - sleep_enable(); - sei(); - sleep_cpu(); - sleep_disable(); - } - sei(); - \endcode - - This sequence ensures an atomic test of \c some_condition with - interrupts being disabled. If the condition is met, sleep mode - will be prepared, and the \c SLEEP instruction will be scheduled - immediately after an \c SEI instruction. As the intruction right - after the \c SEI is guaranteed to be executed before an interrupt - could trigger, it is sure the device will really be put to sleep. - - Some devices have the ability to disable the Brown Out Detector (BOD) before - going to sleep. This will also reduce power while sleeping. If the - specific AVR device has this ability then an additional macro is defined: - \c sleep_bod_disable(). This macro generates inlined assembly code - that will correctly implement the timed sequence for disabling the BOD - before sleeping. However, there is a limited number of cycles after the - BOD has been disabled that the device can be put into sleep mode, otherwise - the BOD will not truly be disabled. Recommended practice is to disable - the BOD (\c sleep_bod_disable()), set the interrupts (\c sei()), and then - put the device to sleep (\c sleep_cpu()), like so: - - \code - #include - #include - - ... - set_sleep_mode(); - cli(); - if (some_condition) - { - sleep_enable(); - sleep_bod_disable(); - sei(); - sleep_cpu(); - sleep_disable(); - } - sei(); - \endcode -*/ - - -/* Define an internal sleep control register and an internal sleep enable bit mask. */ -#if defined(SLEEP_CTRL) - - /* XMEGA devices */ - #define _SLEEP_CONTROL_REG SLEEP_CTRL - #define _SLEEP_ENABLE_MASK SLEEP_SEN_bm - #define _SLEEP_SMODE_GROUP_MASK SLEEP_SMODE_gm - -#elif defined(SLPCTRL) - - /* New xmega devices */ - #define _SLEEP_CONTROL_REG SLPCTRL_CTRLA - #define _SLEEP_ENABLE_MASK SLPCTRL_SEN_bm - #define _SLEEP_SMODE_GROUP_MASK SLPCTRL_SMODE_gm - -#elif defined(SMCR) - - #define _SLEEP_CONTROL_REG SMCR - #define _SLEEP_ENABLE_MASK _BV(SE) - -#elif defined(__AVR_AT94K__) - - #define _SLEEP_CONTROL_REG MCUR - #define _SLEEP_ENABLE_MASK _BV(SE) - -#elif !defined(__DOXYGEN__) - - #define _SLEEP_CONTROL_REG MCUCR - #define _SLEEP_ENABLE_MASK _BV(SE) - -#endif - - -/* Special casing these three devices - they are the - only ones that need to write to more than one register. */ -#if defined(__AVR_ATmega161__) - - #define set_sleep_mode(mode) \ - do { \ - MCUCR = ((MCUCR & ~_BV(SM1)) | ((mode) == SLEEP_MODE_PWR_DOWN || (mode) == SLEEP_MODE_PWR_SAVE ? _BV(SM1) : 0)); \ - EMCUCR = ((EMCUCR & ~_BV(SM0)) | ((mode) == SLEEP_MODE_PWR_SAVE ? _BV(SM0) : 0)); \ - } while(0) - - -#elif defined(__AVR_ATmega162__) \ -|| defined(__AVR_ATmega8515__) - - #define set_sleep_mode(mode) \ - do { \ - MCUCR = ((MCUCR & ~_BV(SM1)) | ((mode) == SLEEP_MODE_IDLE ? 0 : _BV(SM1))); \ - MCUCSR = ((MCUCSR & ~_BV(SM2)) | ((mode) == SLEEP_MODE_STANDBY || (mode) == SLEEP_MODE_EXT_STANDBY ? _BV(SM2) : 0)); \ - EMCUCR = ((EMCUCR & ~_BV(SM0)) | ((mode) == SLEEP_MODE_PWR_SAVE || (mode) == SLEEP_MODE_EXT_STANDBY ? _BV(SM0) : 0)); \ - } while(0) - -/* For xmegas, check presence of SLEEP_SMODE_bm and define set_sleep_mode accordingly. */ -#elif defined(__AVR_XMEGA__) - -#define set_sleep_mode(mode) \ - do { \ - _SLEEP_CONTROL_REG = ((_SLEEP_CONTROL_REG & ~(_SLEEP_SMODE_GROUP_MASK)) | (mode)); \ - } while(0) - -/* For everything else, check for presence of SM and define set_sleep_mode accordingly. */ -#else -#if defined(SM2) - - #define set_sleep_mode(mode) \ - do { \ - _SLEEP_CONTROL_REG = ((_SLEEP_CONTROL_REG & ~(_BV(SM0) | _BV(SM1) | _BV(SM2))) | (mode)); \ - } while(0) - -#elif defined(SM1) - - #define set_sleep_mode(mode) \ - do { \ - _SLEEP_CONTROL_REG = ((_SLEEP_CONTROL_REG & ~(_BV(SM0) | _BV(SM1))) | (mode)); \ - } while(0) - -#elif defined(SM) - - #define set_sleep_mode(mode) \ - do { \ - _SLEEP_CONTROL_REG = ((_SLEEP_CONTROL_REG & ~_BV(SM)) | (mode)); \ - } while(0) - -#else - - #error "No SLEEP mode defined for this device." - -#endif /* if defined(SM2) */ -#endif /* #if defined(__AVR_ATmega161__) */ - - - -/** \ingroup avr_sleep - - Put the device in sleep mode. How the device is brought out of sleep mode - depends on the specific mode selected with the set_sleep_mode() function. - See the data sheet for your device for more details. */ - - -#if defined(__DOXYGEN__) - -/** \ingroup avr_sleep - - Set the SE (sleep enable) bit. -*/ -extern void sleep_enable (void); - -#else - -#define sleep_enable() \ -do { \ - _SLEEP_CONTROL_REG |= (uint8_t)_SLEEP_ENABLE_MASK; \ -} while(0) - -#endif - - -#if defined(__DOXYGEN__) - -/** \ingroup avr_sleep - - Clear the SE (sleep enable) bit. -*/ -extern void sleep_disable (void); - -#else - -#define sleep_disable() \ -do { \ - _SLEEP_CONTROL_REG &= (uint8_t)(~_SLEEP_ENABLE_MASK); \ -} while(0) - -#endif - - -/** \ingroup avr_sleep - - Put the device into sleep mode. The SE bit must be set - beforehand, and it is recommended to clear it afterwards. -*/ -#if defined(__DOXYGEN__) - -extern void sleep_cpu (void); - -#else - -#define sleep_cpu() \ -do { \ - __asm__ __volatile__ ( "sleep" "\n\t" :: ); \ -} while(0) - -#endif - - -#if defined(__DOXYGEN__) - -/** \ingroup avr_sleep - - Put the device into sleep mode, taking care of setting - the SE bit before, and clearing it afterwards. */ -extern void sleep_mode (void); - -#else - -#define sleep_mode() \ -do { \ - sleep_enable(); \ - sleep_cpu(); \ - sleep_disable(); \ -} while (0) - -#endif - - -#if defined(__DOXYGEN__) - -/** \ingroup avr_sleep - - Disable BOD before going to sleep. - Not available on all devices. -*/ -extern void sleep_bod_disable (void); - -#else - -#if defined(BODS) && defined(BODSE) - -#ifdef BODCR - -#define BOD_CONTROL_REG BODCR - -#else - -#define BOD_CONTROL_REG MCUCR - -#endif - -#define sleep_bod_disable() \ -do { \ - uint8_t tempreg; \ - __asm__ __volatile__("in %[tempreg], %[mcucr]" "\n\t" \ - "ori %[tempreg], %[bods_bodse]" "\n\t" \ - "out %[mcucr], %[tempreg]" "\n\t" \ - "andi %[tempreg], %[not_bodse]" "\n\t" \ - "out %[mcucr], %[tempreg]" \ - : [tempreg] "=&d" (tempreg) \ - : [mcucr] "I" _SFR_IO_ADDR(BOD_CONTROL_REG), \ - [bods_bodse] "i" (_BV(BODS) | _BV(BODSE)), \ - [not_bodse] "i" (~_BV(BODSE))); \ -} while (0) - -#endif - -#endif - - -/*@}*/ - -#endif /* _AVR_SLEEP_H_ */ diff --git a/arduino/hardware/tools/avr/avr/include/avr/version.h b/arduino/hardware/tools/avr/avr/include/avr/version.h deleted file mode 100644 index 2deaf86..0000000 --- a/arduino/hardware/tools/avr/avr/include/avr/version.h +++ /dev/null @@ -1,90 +0,0 @@ -/* Copyright (c) 2005, Joerg Wunsch -*- c -*- - All rights reserved. - - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - * Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - * Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in - the documentation and/or other materials provided with the - distribution. - - * Neither the name of the copyright holders nor the names of - contributors may be used to endorse or promote products derived - from this software without specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. */ - -/* $Id$ */ - -/** \defgroup avr_version : avr-libc version macros - \code #include \endcode - - This header file defines macros that contain version numbers and - strings describing the current version of avr-libc. - - The version number itself basically consists of three pieces that - are separated by a dot: the major number, the minor number, and - the revision number. For development versions (which use an odd - minor number), the string representation additionally gets the - date code (YYYYMMDD) appended. - - This file will also be included by \c . That way, - portable tests can be implemented using \c that can be - used in code that wants to remain backwards-compatible to library - versions prior to the date when the library version API had been - added, as referenced but undefined C preprocessor macros - automatically evaluate to 0. -*/ - -#ifndef _AVR_VERSION_H_ -#define _AVR_VERSION_H_ - -/** \ingroup avr_version - String literal representation of the current library version. */ -#define __AVR_LIBC_VERSION_STRING__ "2.0.0" - -/** \ingroup avr_version - Numerical representation of the current library version. - - In the numerical representation, the major number is multiplied by - 10000, the minor number by 100, and all three parts are then - added. It is intented to provide a monotonically increasing - numerical value that can easily be used in numerical checks. - */ -#define __AVR_LIBC_VERSION__ 20000UL - -/** \ingroup avr_version - String literal representation of the release date. */ -#define __AVR_LIBC_DATE_STRING__ "20150208" - -/** \ingroup avr_version - Numerical representation of the release date. */ -#define __AVR_LIBC_DATE_ 20150208UL - -/** \ingroup avr_version - Library major version number. */ -#define __AVR_LIBC_MAJOR__ 2 - -/** \ingroup avr_version - Library minor version number. */ -#define __AVR_LIBC_MINOR__ 0 - -/** \ingroup avr_version - Library revision number. */ -#define __AVR_LIBC_REVISION__ 0 - -#endif /* _AVR_VERSION_H_ */ diff --git a/arduino/hardware/tools/avr/avr/include/avr/wdt.h b/arduino/hardware/tools/avr/avr/include/avr/wdt.h deleted file mode 100644 index 2b4a02e..0000000 --- a/arduino/hardware/tools/avr/avr/include/avr/wdt.h +++ /dev/null @@ -1,645 +0,0 @@ -/* Copyright (c) 2002, 2004 Marek Michalkiewicz - Copyright (c) 2005, 2006, 2007 Eric B. Weddington - All rights reserved. - - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - * Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - * Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in - the documentation and/or other materials provided with the - distribution. - - * Neither the name of the copyright holders nor the names of - contributors may be used to endorse or promote products derived - from this software without specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. */ - -/* $Id$ */ - -/* - avr/wdt.h - macros for AVR watchdog timer - */ - -#ifndef _AVR_WDT_H_ -#define _AVR_WDT_H_ - -#include -#include - -/** \file */ -/** \defgroup avr_watchdog : Watchdog timer handling - \code #include \endcode - - This header file declares the interface to some inline macros - handling the watchdog timer present in many AVR devices. In order - to prevent the watchdog timer configuration from being - accidentally altered by a crashing application, a special timed - sequence is required in order to change it. The macros within - this header file handle the required sequence automatically - before changing any value. Interrupts will be disabled during - the manipulation. - - \note Depending on the fuse configuration of the particular - device, further restrictions might apply, in particular it might - be disallowed to turn off the watchdog timer. - - Note that for newer devices (ATmega88 and newer, effectively any - AVR that has the option to also generate interrupts), the watchdog - timer remains active even after a system reset (except a power-on - condition), using the fastest prescaler value (approximately 15 - ms). It is therefore required to turn off the watchdog early - during program startup, the datasheet recommends a sequence like - the following: - - \code - #include - #include - - uint8_t mcusr_mirror __attribute__ ((section (".noinit"))); - - void get_mcusr(void) \ - __attribute__((naked)) \ - __attribute__((section(".init3"))); - void get_mcusr(void) - { - mcusr_mirror = MCUSR; - MCUSR = 0; - wdt_disable(); - } - \endcode - - Saving the value of MCUSR in \c mcusr_mirror is only needed if the - application later wants to examine the reset source, but in particular, - clearing the watchdog reset flag before disabling the - watchdog is required, according to the datasheet. -*/ - -/** - \ingroup avr_watchdog - Reset the watchdog timer. When the watchdog timer is enabled, - a call to this instruction is required before the timer expires, - otherwise a watchdog-initiated device reset will occur. -*/ - -#define wdt_reset() __asm__ __volatile__ ("wdr") - -#ifndef __DOXYGEN__ - -#if defined(WDP3) -# define _WD_PS3_MASK _BV(WDP3) -#else -# define _WD_PS3_MASK 0x00 -#endif - -#if defined(WDTCSR) -# define _WD_CONTROL_REG WDTCSR -#elif defined(WDTCR) -# define _WD_CONTROL_REG WDTCR -#else -# define _WD_CONTROL_REG WDT -#endif - -#if defined(WDTOE) -#define _WD_CHANGE_BIT WDTOE -#else -#define _WD_CHANGE_BIT WDCE -#endif - -#endif /* !__DOXYGEN__ */ - - -/** - \ingroup avr_watchdog - Enable the watchdog timer, configuring it for expiry after - \c timeout (which is a combination of the \c WDP0 through - \c WDP2 bits to write into the \c WDTCR register; For those devices - that have a \c WDTCSR register, it uses the combination of the \c WDP0 - through \c WDP3 bits). - - See also the symbolic constants \c WDTO_15MS et al. -*/ - - -#if defined(__AVR_XMEGA__) - -#if defined (WDT_CTRLA) && !defined(RAMPD) - -#define wdt_enable(timeout) \ -do { \ -uint8_t temp; \ -__asm__ __volatile__ ( \ - "wdr" "\n\t" \ - "out %[ccp_reg], %[ioreg_cen_mask]" "\n\t" \ - "lds %[tmp], %[wdt_reg]" "\n\t" \ - "sbr %[tmp], %[wdt_enable_timeout]" "\n\t" \ - "sts %[wdt_reg], %[tmp]" "\n\t" \ - "1:lds %[tmp], %[wdt_status_reg]" "\n\t" \ - "sbrc %[tmp], %[wdt_syncbusy_bit]" "\n\t" \ - "rjmp 1b" "\n\t" \ - : [tmp] "=r" (temp) \ - : [ccp_reg] "I" (_SFR_IO_ADDR(CCP)), \ - [ioreg_cen_mask] "r" ((uint8_t)CCP_IOREG_gc), \ - [wdt_reg] "n" (_SFR_MEM_ADDR(WDT_CTRLA)), \ - [wdt_enable_timeout] "M" (timeout), \ - [wdt_status_reg] "n" (_SFR_MEM_ADDR(WDT_STATUS)), \ - [wdt_syncbusy_bit] "I" (WDT_SYNCBUSY_bm) \ -); \ -} while(0) - -#define wdt_disable() \ -do { \ -uint8_t temp; \ -__asm__ __volatile__ ( \ - "wdr" "\n\t" \ - "out %[ccp_reg], %[ioreg_cen_mask]" "\n\t" \ - "lds %[tmp], %[wdt_reg]" "\n\t" \ - "cbr %[tmp], %[timeout_mask]" "\n\t" \ - "sts %[wdt_reg], %[tmp]" "\n\t" \ - : [tmp] "=r" (temp) \ - : [ccp_reg] "I" (_SFR_IO_ADDR(CCP)), \ - [ioreg_cen_mask] "r" ((uint8_t)CCP_IOREG_gc), \ - [wdt_reg] "n" (_SFR_MEM_ADDR(WDT_CTRLA)),\ - [timeout_mask] "I" (WDT_PERIOD_gm) \ -); \ -} while(0) - -#else // defined (WDT_CTRLA) && !defined(RAMPD) - -/* - wdt_enable(timeout) for xmega devices -** write signature (CCP_IOREG_gc) that enables change of protected I/O - registers to the CCP register -** At the same time, - 1) set WDT change enable (WDT_CEN_bm) - 2) enable WDT (WDT_ENABLE_bm) - 3) set timeout (timeout) -** Synchronization starts when ENABLE bit of WDT is set. So, wait till it - finishes (SYNCBUSY of STATUS register is automatically cleared after the - sync is finished). -*/ -#define wdt_enable(timeout) \ -do { \ -uint8_t temp; \ -__asm__ __volatile__ ( \ - "in __tmp_reg__, %[rampd]" "\n\t" \ - "out %[rampd], __zero_reg__" "\n\t" \ - "out %[ccp_reg], %[ioreg_cen_mask]" "\n\t" \ - "sts %[wdt_reg], %[wdt_enable_timeout]" "\n\t" \ - "1:lds %[tmp], %[wdt_status_reg]" "\n\t" \ - "sbrc %[tmp], %[wdt_syncbusy_bit]" "\n\t" \ - "rjmp 1b" "\n\t" \ - "out %[rampd], __tmp_reg__" "\n\t" \ - : [tmp] "=r" (temp) \ - : [rampd] "I" (_SFR_IO_ADDR(RAMPD)), \ - [ccp_reg] "I" (_SFR_IO_ADDR(CCP)), \ - [ioreg_cen_mask] "r" ((uint8_t)CCP_IOREG_gc), \ - [wdt_reg] "n" (_SFR_MEM_ADDR(WDT_CTRL)), \ - [wdt_enable_timeout] "r" ((uint8_t)(WDT_CEN_bm | WDT_ENABLE_bm | timeout)), \ - [wdt_status_reg] "n" (_SFR_MEM_ADDR(WDT_STATUS)), \ - [wdt_syncbusy_bit] "I" (WDT_SYNCBUSY_bm) \ - : "r0" \ -); \ -} while(0) - -#define wdt_disable() \ -__asm__ __volatile__ ( \ - "in __tmp_reg__, %[rampd]" "\n\t" \ - "out %[rampd], __zero_reg__" "\n\t" \ - "out %[ccp_reg], %[ioreg_cen_mask]" "\n\t" \ - "sts %[wdt_reg], %[disable_mask]" "\n\t" \ - "out %[rampd], __tmp_reg__" "\n\t" \ - : \ - : [rampd] "I" (_SFR_IO_ADDR(RAMPD)), \ - [ccp_reg] "I" (_SFR_IO_ADDR(CCP)), \ - [ioreg_cen_mask] "r" ((uint8_t)CCP_IOREG_gc), \ - [wdt_reg] "n" (_SFR_MEM_ADDR(WDT_CTRL)), \ - [disable_mask] "r" ((uint8_t)((~WDT_ENABLE_bm) | WDT_CEN_bm)) \ - : "r0" \ -); - -#endif // defined (WDT_CTRLA) && !defined(RAMPD) - -#elif defined(__AVR_TINY__) - -#define wdt_enable(value) \ -__asm__ __volatile__ ( \ - "in __tmp_reg__,__SREG__" "\n\t" \ - "cli" "\n\t" \ - "wdr" "\n\t" \ - "out %[CCPADDRESS],%[SIGNATURE]" "\n\t" \ - "out %[WDTREG],%[WDVALUE]" "\n\t" \ - "out __SREG__,__tmp_reg__" "\n\t" \ - : /* no outputs */ \ - : [CCPADDRESS] "I" (_SFR_IO_ADDR(CCP)), \ - [SIGNATURE] "r" ((uint8_t)0xD8), \ - [WDTREG] "I" (_SFR_IO_ADDR(_WD_CONTROL_REG)), \ - [WDVALUE] "r" ((uint8_t)((value & 0x08 ? _WD_PS3_MASK : 0x00) \ - | _BV(WDE) | (value & 0x07) )) \ - : "r16" \ -) - -#define wdt_disable() \ -do { \ -uint8_t temp_wd; \ -__asm__ __volatile__ ( \ - "in __tmp_reg__,__SREG__" "\n\t" \ - "cli" "\n\t" \ - "wdr" "\n\t" \ - "out %[CCPADDRESS],%[SIGNATURE]" "\n\t" \ - "in %[TEMP_WD],%[WDTREG]" "\n\t" \ - "cbr %[TEMP_WD],%[WDVALUE]" "\n\t" \ - "out %[WDTREG],%[TEMP_WD]" "\n\t" \ - "out __SREG__,__tmp_reg__" "\n\t" \ - : /*no output */ \ - : [CCPADDRESS] "I" (_SFR_IO_ADDR(CCP)), \ - [SIGNATURE] "r" ((uint8_t)0xD8), \ - [WDTREG] "I" (_SFR_IO_ADDR(_WD_CONTROL_REG)), \ - [TEMP_WD] "d" (temp_wd), \ - [WDVALUE] "n" (1 << WDE) \ - : "r16" \ -); \ -}while(0) - -#elif defined(CCP) - -static __inline__ -__attribute__ ((__always_inline__)) -void wdt_enable (const uint8_t value) -{ - if (!_SFR_IO_REG_P (CCP) && !_SFR_IO_REG_P (_WD_CONTROL_REG)) - { - __asm__ __volatile__ ( - "in __tmp_reg__,__SREG__" "\n\t" - "cli" "\n\t" - "wdr" "\n\t" - "sts %[CCPADDRESS],%[SIGNATURE]" "\n\t" - "sts %[WDTREG],%[WDVALUE]" "\n\t" - "out __SREG__,__tmp_reg__" "\n\t" - : /* no outputs */ - : [CCPADDRESS] "n" (_SFR_MEM_ADDR(CCP)), - [SIGNATURE] "r" ((uint8_t)0xD8), - [WDTREG] "n" (_SFR_MEM_ADDR(_WD_CONTROL_REG)), - [WDVALUE] "r" ((uint8_t)((value & 0x08 ? _WD_PS3_MASK : 0x00) - | _BV(WDE) | (value & 0x07) )) - : "r0" - ); - } - else if (!_SFR_IO_REG_P (CCP) && _SFR_IO_REG_P (_WD_CONTROL_REG)) - { - __asm__ __volatile__ ( - "in __tmp_reg__,__SREG__" "\n\t" - "cli" "\n\t" - "wdr" "\n\t" - "sts %[CCPADDRESS],%[SIGNATURE]" "\n\t" - "out %[WDTREG],%[WDVALUE]" "\n\t" - "out __SREG__,__tmp_reg__" "\n\t" - : /* no outputs */ - : [CCPADDRESS] "n" (_SFR_MEM_ADDR(CCP)), - [SIGNATURE] "r" ((uint8_t)0xD8), - [WDTREG] "I" (_SFR_IO_ADDR(_WD_CONTROL_REG)), - [WDVALUE] "r" ((uint8_t)((value & 0x08 ? _WD_PS3_MASK : 0x00) - | _BV(WDE) | (value & 0x07) )) - : "r0" - ); - } - else if (_SFR_IO_REG_P (CCP) && !_SFR_IO_REG_P (_WD_CONTROL_REG)) - { - __asm__ __volatile__ ( - "in __tmp_reg__,__SREG__" "\n\t" - "cli" "\n\t" - "wdr" "\n\t" - "out %[CCPADDRESS],%[SIGNATURE]" "\n\t" - "sts %[WDTREG],%[WDVALUE]" "\n\t" - "out __SREG__,__tmp_reg__" "\n\t" - : /* no outputs */ - : [CCPADDRESS] "I" (_SFR_IO_ADDR(CCP)), - [SIGNATURE] "r" ((uint8_t)0xD8), - [WDTREG] "n" (_SFR_MEM_ADDR(_WD_CONTROL_REG)), - [WDVALUE] "r" ((uint8_t)((value & 0x08 ? _WD_PS3_MASK : 0x00) - | _BV(WDE) | (value & 0x07) )) - : "r0" - ); - } - else - { - __asm__ __volatile__ ( - "in __tmp_reg__,__SREG__" "\n\t" - "cli" "\n\t" - "wdr" "\n\t" - "out %[CCPADDRESS],%[SIGNATURE]" "\n\t" - "out %[WDTREG],%[WDVALUE]" "\n\t" - "out __SREG__,__tmp_reg__" "\n\t" - : /* no outputs */ - : [CCPADDRESS] "I" (_SFR_IO_ADDR(CCP)), - [SIGNATURE] "r" ((uint8_t)0xD8), - [WDTREG] "I" (_SFR_IO_ADDR(_WD_CONTROL_REG)), - [WDVALUE] "r" ((uint8_t)((value & 0x08 ? _WD_PS3_MASK : 0x00) - | _BV(WDE) | (value & 0x07) )) - : "r0" - ); - } -} - -static __inline__ -__attribute__ ((__always_inline__)) -void wdt_disable (void) -{ - if (!_SFR_IO_REG_P (CCP) && !_SFR_IO_REG_P(_WD_CONTROL_REG)) - { - uint8_t temp_wd; - __asm__ __volatile__ ( - "in __tmp_reg__,__SREG__" "\n\t" - "cli" "\n\t" - "wdr" "\n\t" - "sts %[CCPADDRESS],%[SIGNATURE]" "\n\t" - "lds %[TEMP_WD],%[WDTREG]" "\n\t" - "cbr %[TEMP_WD],%[WDVALUE]" "\n\t" - "sts %[WDTREG],%[TEMP_WD]" "\n\t" - "out __SREG__,__tmp_reg__" "\n\t" - : /*no output */ - : [CCPADDRESS] "n" (_SFR_MEM_ADDR(CCP)), - [SIGNATURE] "r" ((uint8_t)0xD8), - [WDTREG] "n" (_SFR_MEM_ADDR(_WD_CONTROL_REG)), - [TEMP_WD] "d" (temp_wd), - [WDVALUE] "n" (1 << WDE) - : "r0" - ); - } - else if (!_SFR_IO_REG_P (CCP) && _SFR_IO_REG_P(_WD_CONTROL_REG)) - { - uint8_t temp_wd; - __asm__ __volatile__ ( - "in __tmp_reg__,__SREG__" "\n\t" - "cli" "\n\t" - "wdr" "\n\t" - "sts %[CCPADDRESS],%[SIGNATURE]" "\n\t" - "in %[TEMP_WD],%[WDTREG]" "\n\t" - "cbr %[TEMP_WD],%[WDVALUE]" "\n\t" - "out %[WDTREG],%[TEMP_WD]" "\n\t" - "out __SREG__,__tmp_reg__" "\n\t" - : /*no output */ - : [CCPADDRESS] "n" (_SFR_MEM_ADDR(CCP)), - [SIGNATURE] "r" ((uint8_t)0xD8), - [WDTREG] "I" (_SFR_IO_ADDR(_WD_CONTROL_REG)), - [TEMP_WD] "d" (temp_wd), - [WDVALUE] "n" (1 << WDE) - : "r0" - ); - } - else if (_SFR_IO_REG_P (CCP) && !_SFR_IO_REG_P(_WD_CONTROL_REG)) - { - uint8_t temp_wd; - __asm__ __volatile__ ( - "in __tmp_reg__,__SREG__" "\n\t" - "cli" "\n\t" - "wdr" "\n\t" - "out %[CCPADDRESS],%[SIGNATURE]" "\n\t" - "lds %[TEMP_WD],%[WDTREG]" "\n\t" - "cbr %[TEMP_WD],%[WDVALUE]" "\n\t" - "sts %[WDTREG],%[TEMP_WD]" "\n\t" - "out __SREG__,__tmp_reg__" "\n\t" - : /*no output */ - : [CCPADDRESS] "I" (_SFR_IO_ADDR(CCP)), - [SIGNATURE] "r" ((uint8_t)0xD8), - [WDTREG] "n" (_SFR_MEM_ADDR(_WD_CONTROL_REG)), - [TEMP_WD] "d" (temp_wd), - [WDVALUE] "n" (1 << WDE) - : "r0" - ); - } - else - { - uint8_t temp_wd; - __asm__ __volatile__ ( - "in __tmp_reg__,__SREG__" "\n\t" - "cli" "\n\t" - "wdr" "\n\t" - "out %[CCPADDRESS],%[SIGNATURE]" "\n\t" - "in %[TEMP_WD],%[WDTREG]" "\n\t" - "cbr %[TEMP_WD],%[WDVALUE]" "\n\t" - "out %[WDTREG],%[TEMP_WD]" "\n\t" - "out __SREG__,__tmp_reg__" "\n\t" - : /*no output */ - : [CCPADDRESS] "I" (_SFR_IO_ADDR(CCP)), - [SIGNATURE] "r" ((uint8_t)0xD8), - [WDTREG] "I" (_SFR_IO_ADDR(_WD_CONTROL_REG)), - [TEMP_WD] "d" (temp_wd), - [WDVALUE] "n" (1 << WDE) - : "r0" - ); - } -} - -#else - -static __inline__ -__attribute__ ((__always_inline__)) -void wdt_enable (const uint8_t value) -{ - if (_SFR_IO_REG_P (_WD_CONTROL_REG)) - { - __asm__ __volatile__ ( - "in __tmp_reg__,__SREG__" "\n\t" - "cli" "\n\t" - "wdr" "\n\t" - "out %0, %1" "\n\t" - "out __SREG__,__tmp_reg__" "\n\t" - "out %0, %2" "\n \t" - : /* no outputs */ - : "I" (_SFR_IO_ADDR(_WD_CONTROL_REG)), - "r" ((uint8_t)(_BV(_WD_CHANGE_BIT) | _BV(WDE))), - "r" ((uint8_t) ((value & 0x08 ? _WD_PS3_MASK : 0x00) | - _BV(WDE) | (value & 0x07)) ) - : "r0" - ); - } - else - { - __asm__ __volatile__ ( - "in __tmp_reg__,__SREG__" "\n\t" - "cli" "\n\t" - "wdr" "\n\t" - "sts %0, %1" "\n\t" - "out __SREG__,__tmp_reg__" "\n\t" - "sts %0, %2" "\n \t" - : /* no outputs */ - : "n" (_SFR_MEM_ADDR(_WD_CONTROL_REG)), - "r" ((uint8_t)(_BV(_WD_CHANGE_BIT) | _BV(WDE))), - "r" ((uint8_t) ((value & 0x08 ? _WD_PS3_MASK : 0x00) | - _BV(WDE) | (value & 0x07)) ) - : "r0" - ); - } -} - -static __inline__ -__attribute__ ((__always_inline__)) -void wdt_disable (void) -{ - if (_SFR_IO_REG_P (_WD_CONTROL_REG)) - { - uint8_t register temp_reg; - __asm__ __volatile__ ( - "in __tmp_reg__,__SREG__" "\n\t" - "cli" "\n\t" - "wdr" "\n\t" - "in %[TEMPREG],%[WDTREG]" "\n\t" - "ori %[TEMPREG],%[WDCE_WDE]" "\n\t" - "out %[WDTREG],%[TEMPREG]" "\n\t" - "out %[WDTREG],__zero_reg__" "\n\t" - "out __SREG__,__tmp_reg__" "\n\t" - : [TEMPREG] "=d" (temp_reg) - : [WDTREG] "I" (_SFR_IO_ADDR(_WD_CONTROL_REG)), - [WDCE_WDE] "n" ((uint8_t)(_BV(_WD_CHANGE_BIT) | _BV(WDE))) - : "r0" - ); - } - else - { - uint8_t register temp_reg; - __asm__ __volatile__ ( - "in __tmp_reg__,__SREG__" "\n\t" - "cli" "\n\t" - "wdr" "\n\t" - "lds %[TEMPREG],%[WDTREG]" "\n\t" - "ori %[TEMPREG],%[WDCE_WDE]" "\n\t" - "sts %[WDTREG],%[TEMPREG]" "\n\t" - "sts %[WDTREG],__zero_reg__" "\n\t" - "out __SREG__,__tmp_reg__" "\n\t" - : [TEMPREG] "=d" (temp_reg) - : [WDTREG] "n" (_SFR_MEM_ADDR(_WD_CONTROL_REG)), - [WDCE_WDE] "n" ((uint8_t)(_BV(_WD_CHANGE_BIT) | _BV(WDE))) - : "r0" - ); - } -} - -#endif - - -/** - \ingroup avr_watchdog - Symbolic constants for the watchdog timeout. Since the watchdog - timer is based on a free-running RC oscillator, the times are - approximate only and apply to a supply voltage of 5 V. At lower - supply voltages, the times will increase. For older devices, the - times will be as large as three times when operating at Vcc = 3 V, - while the newer devices (e. g. ATmega128, ATmega8) only experience - a negligible change. - - Possible timeout values are: 15 ms, 30 ms, 60 ms, 120 ms, 250 ms, - 500 ms, 1 s, 2 s. (Some devices also allow for 4 s and 8 s.) - Symbolic constants are formed by the prefix - \c WDTO_, followed by the time. - - Example that would select a watchdog timer expiry of approximately - 500 ms: - \code - wdt_enable(WDTO_500MS); - \endcode -*/ -#define WDTO_15MS 0 - -/** \ingroup avr_watchdog - See \c WDTO_15MS */ -#define WDTO_30MS 1 - -/** \ingroup avr_watchdog - See \c WDTO_15MS */ -#define WDTO_60MS 2 - -/** \ingroup avr_watchdog - See \c WDTO_15MS */ -#define WDTO_120MS 3 - -/** \ingroup avr_watchdog - See \c WDTO_15MS */ -#define WDTO_250MS 4 - -/** \ingroup avr_watchdog - See \c WDTO_15MS */ -#define WDTO_500MS 5 - -/** \ingroup avr_watchdog - See \c WDTO_15MS */ -#define WDTO_1S 6 - -/** \ingroup avr_watchdog - See \c WDTO_15MS */ -#define WDTO_2S 7 - -#if defined(__DOXYGEN__) || defined(WDP3) - -/** \ingroup avr_watchdog - See \c WDTO_15MS - Note: This is only available on the - ATtiny2313, - ATtiny24, ATtiny44, ATtiny84, ATtiny84A, - ATtiny25, ATtiny45, ATtiny85, - ATtiny261, ATtiny461, ATtiny861, - ATmega48, ATmega88, ATmega168, - ATmega48P, ATmega88P, ATmega168P, ATmega328P, - ATmega164P, ATmega324P, ATmega644P, ATmega644, - ATmega640, ATmega1280, ATmega1281, ATmega2560, ATmega2561, - ATmega8HVA, ATmega16HVA, ATmega32HVB, - ATmega406, ATmega1284P, - AT90PWM1, AT90PWM2, AT90PWM2B, AT90PWM3, AT90PWM3B, AT90PWM216, AT90PWM316, - AT90PWM81, AT90PWM161, - AT90USB82, AT90USB162, - AT90USB646, AT90USB647, AT90USB1286, AT90USB1287, - ATtiny48, ATtiny88. - - Note: This value does not match the bit pattern of the - respective control register. It is solely meant to be used together - with wdt_enable(). - */ -#define WDTO_4S 8 - -/** \ingroup avr_watchdog - See \c WDTO_15MS - Note: This is only available on the - ATtiny2313, - ATtiny24, ATtiny44, ATtiny84, ATtiny84A, - ATtiny25, ATtiny45, ATtiny85, - ATtiny261, ATtiny461, ATtiny861, - ATmega48, ATmega48A, ATmega48PA, ATmega88, ATmega168, - ATmega48P, ATmega88P, ATmega168P, ATmega328P, - ATmega164P, ATmega324P, ATmega644P, ATmega644, - ATmega640, ATmega1280, ATmega1281, ATmega2560, ATmega2561, - ATmega8HVA, ATmega16HVA, ATmega32HVB, - ATmega406, ATmega1284P, - ATmega2564RFR2, ATmega256RFR2, ATmega1284RFR2, ATmega128RFR2, ATmega644RFR2, ATmega64RFR2 - AT90PWM1, AT90PWM2, AT90PWM2B, AT90PWM3, AT90PWM3B, AT90PWM216, AT90PWM316, - AT90PWM81, AT90PWM161, - AT90USB82, AT90USB162, - AT90USB646, AT90USB647, AT90USB1286, AT90USB1287, - ATtiny48, ATtiny88, - ATxmega16a4u, ATxmega32a4u, - ATxmega16c4, ATxmega32c4, - ATxmega128c3, ATxmega192c3, ATxmega256c3. - - Note: This value does not match the bit pattern of the - respective control register. It is solely meant to be used together - with wdt_enable(). - */ -#define WDTO_8S 9 - -#endif /* defined(__DOXYGEN__) || defined(WDP3) */ - - -#endif /* _AVR_WDT_H_ */ diff --git a/arduino/hardware/tools/avr/avr/include/avr/xmega.h b/arduino/hardware/tools/avr/avr/include/avr/xmega.h deleted file mode 100644 index 54375ab..0000000 --- a/arduino/hardware/tools/avr/avr/include/avr/xmega.h +++ /dev/null @@ -1,100 +0,0 @@ -/* Copyright (c) 2012 Joerg Wunsch - All rights reserved. - - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - * Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - * Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in - the documentation and/or other materials provided with the - distribution. - - * Neither the name of the copyright holders nor the names of - contributors may be used to endorse or promote products derived - from this software without specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. */ - -/* $Id$ */ - -/* - * This file is included by whenever compiling for an Xmega - * device. It abstracts certain features common to the Xmega device - * families. - */ - -#ifndef _AVR_XMEGA_H -#define _AVR_XMEGA_H - -#ifdef __DOXYGEN__ -/** - \def _PROTECTED_WRITE - \ingroup avr_io - - Write value \c value to IO register \c reg that is protected through - the Xmega configuration change protection (CCP) mechanism. This - implements the timed sequence that is required for CCP. - - Example to modify the CPU clock: - \code - #include - - _PROTECTED_WRITE(CLK_PSCTRL, CLK_PSADIV0_bm); - _PROTECTED_WRITE(CLK_CTRL, CLK_SCLKSEL0_bm); - \endcode - */ -#define _PROTECTED_WRITE(reg, value) - -/** - \def _PROTECTED_WRITE_SPM - \ingroup avr_io - - Write value \c value to register \c reg that is protected through - the Xmega configuration change protection (CCP) key for self - programming (SPM). This implements the timed sequence that is - required for CCP. - - Example to modify the CPU clock: - \code - #include - - _PROTECTED_WRITE_SPM(NVMCTRL_CTRLA, NVMCTRL_CMD_PAGEERASEWRITE_gc); - \endcode - */ -#define _PROTECTED_WRITE_SPM(reg, value) - -#else /* !__DOXYGEN__ */ - -#define _PROTECTED_WRITE(reg, value) \ - __asm__ __volatile__("out %[ccp], %[ccp_ioreg]" "\n\t" \ - "sts %[ioreg], %[val]" \ - : \ - : [ccp] "I" (_SFR_IO_ADDR(CCP)), \ - [ccp_ioreg] "d" ((uint8_t)CCP_IOREG_gc), \ - [ioreg] "n" (_SFR_MEM_ADDR(reg)), \ - [val] "r" ((uint8_t)value)) - -#define _PROTECTED_WRITE_SPM(reg, value) \ - __asm__ __volatile__("out %[ccp], %[ccp_spm_mask]" "\n\t" \ - "sts %[ioreg], %[val]" \ - : \ - : [ccp] "I" (_SFR_IO_ADDR(CCP)), \ - [ccp_spm_mask] "d" ((uint8_t)CCP_SPM_gc), \ - [ioreg] "n" (_SFR_MEM_ADDR(reg)), \ - [val] "r" ((uint8_t)value)) -#endif /* DOXYGEN */ - -#endif /* _AVR_XMEGA_H */ diff --git a/arduino/hardware/tools/avr/avr/include/compat/deprecated.h b/arduino/hardware/tools/avr/avr/include/compat/deprecated.h deleted file mode 100644 index a43fe06..0000000 --- a/arduino/hardware/tools/avr/avr/include/compat/deprecated.h +++ /dev/null @@ -1,226 +0,0 @@ -/* Copyright (c) 2005,2006 Joerg Wunsch - All rights reserved. - - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - * Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - * Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in - the documentation and/or other materials provided with the - distribution. - - * Neither the name of the copyright holders nor the names of - contributors may be used to endorse or promote products derived - from this software without specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. */ - -/* $Id$ */ - -#ifndef _COMPAT_DEPRECATED_H_ -#define _COMPAT_DEPRECATED_H_ - -/** \defgroup deprecated_items : Deprecated items - - This header file contains several items that used to be available - in previous versions of this library, but have eventually been - deprecated over time. - - \code #include \endcode - - These items are supplied within that header file for backward - compatibility reasons only, so old source code that has been - written for previous library versions could easily be maintained - until its end-of-life. Use of any of these items in new code is - strongly discouraged. - */ - -/** \name Allowing specific system-wide interrupts - - In addition to globally enabling interrupts, each device's particular - interrupt needs to be enabled separately if interrupts for this device are - desired. While some devices maintain their interrupt enable bit inside - the device's register set, external and timer interrupts have system-wide - configuration registers. - - Example: - - \code - // Enable timer 1 overflow interrupts. - timer_enable_int(_BV(TOIE1)); - - // Do some work... - - // Disable all timer interrupts. - timer_enable_int(0); - \endcode - - \note Be careful when you use these functions. If you already have a - different interrupt enabled, you could inadvertantly disable it by - enabling another intterupt. */ - -/*@{*/ - -/** \ingroup deprecated_items - \def enable_external_int(mask) - \deprecated - - This macro gives access to the \c GIMSK register (or \c EIMSK register - if using an AVR Mega device or \c GICR register for others). Although this - macro is essentially the same as assigning to the register, it does - adapt slightly to the type of device being used. This macro is - unavailable if none of the registers listed above are defined. */ - -/* Define common register definition if available. */ -#if defined(EIMSK) -# define __EICR EIMSK -#elif defined(GIMSK) -# define __EICR GIMSK -#elif defined(GICR) -# define __EICR GICR -#endif - -/* If common register defined, define macro. */ -#if defined(__EICR) || defined(__DOXYGEN__) -#define enable_external_int(mask) (__EICR = mask) -#endif - -/** \ingroup deprecated_items - \deprecated - - This function modifies the \c timsk register. - The value you pass via \c ints is device specific. */ - -static __inline__ void timer_enable_int (unsigned char ints) -{ -#ifdef TIMSK - TIMSK = ints; -#endif -} - -/** \def INTERRUPT(signame) - \ingroup deprecated_items - \deprecated - - Introduces an interrupt handler function that runs with global interrupts - initially enabled. This allows interrupt handlers to be interrupted. - - As this macro has been used by too many unsuspecting people in the - past, it has been deprecated, and will be removed in a future - version of the library. Users who want to legitimately re-enable - interrupts in their interrupt handlers as quickly as possible are - encouraged to explicitly declare their handlers as described - \ref attr_interrupt "above". -*/ - -#if (__GNUC__ == 4 && __GNUC_MINOR__ >= 1) || (__GNUC__ > 4) -# define __INTR_ATTRS used, externally_visible -#else /* GCC < 4.1 */ -# define __INTR_ATTRS used -#endif - -#ifdef __cplusplus -#define INTERRUPT(signame) \ -extern "C" void signame(void); \ -void signame (void) __attribute__ ((interrupt,__INTR_ATTRS)); \ -void signame (void) -#else -#define INTERRUPT(signame) \ -void signame (void) __attribute__ ((interrupt,__INTR_ATTRS)); \ -void signame (void) -#endif - -/*@}*/ - -/** - \name Obsolete IO macros - - Back in a time when AVR-GCC and avr-libc could not handle IO port - access in the direct assignment form as they are handled now, all - IO port access had to be done through specific macros that - eventually resulted in inline assembly instructions performing the - desired action. - - These macros became obsolete, as reading and writing IO ports can - be done by simply using the IO port name in an expression, and all - bit manipulation (including those on IO ports) can be done using - generic C bit manipulation operators. - - The macros in this group simulate the historical behaviour. While - they are supposed to be applied to IO ports, the emulation actually - uses standard C methods, so they could be applied to arbitrary - memory locations as well. -*/ - -/*@{*/ - -/** - \ingroup deprecated_items - \def inp(port) - \deprecated - - Read a value from an IO port \c port. -*/ -#define inp(port) (port) - -/** - \ingroup deprecated_items - \def outp(val, port) - \deprecated - - Write \c val to IO port \c port. -*/ -#define outp(val, port) (port) = (val) - -/** - \ingroup deprecated_items - \def inb(port) - \deprecated - - Read a value from an IO port \c port. -*/ -#define inb(port) (port) - -/** - \ingroup deprecated_items - \def outb(port, val) - \deprecated - - Write \c val to IO port \c port. -*/ -#define outb(port, val) (port) = (val) - -/** - \ingroup deprecated_items - \def sbi(port, bit) - \deprecated - - Set \c bit in IO port \c port. -*/ -#define sbi(port, bit) (port) |= (1 << (bit)) - -/** - \ingroup deprecated_items - \def cbi(port, bit) - \deprecated - - Clear \c bit in IO port \c port. -*/ -#define cbi(port, bit) (port) &= ~(1 << (bit)) - -/*@}*/ - -#endif /* _COMPAT_DEPRECATED_H_ */ diff --git a/arduino/hardware/tools/avr/avr/include/compat/ina90.h b/arduino/hardware/tools/avr/avr/include/compat/ina90.h deleted file mode 100644 index 076593a..0000000 --- a/arduino/hardware/tools/avr/avr/include/compat/ina90.h +++ /dev/null @@ -1,99 +0,0 @@ -/* Copyright (c) 2002,2004 Marek Michalkiewicz - All rights reserved. - - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - * Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - * Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in - the documentation and/or other materials provided with the - distribution. - - * Neither the name of the copyright holders nor the names of - contributors may be used to endorse or promote products derived - from this software without specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. */ - -/* $Id$ */ -/* copied from: Id: avr/ina90.h,v 1.8 2004/11/09 19:16:09 arcanum Exp */ - -/* - ina90.h - - Contributors: - Created by Marek Michalkiewicz - */ - -/** - \defgroup compat_ina90 : Compatibility with IAR EWB 3.x - - \code #include \endcode - - This is an attempt to provide some compatibility with - header files that come with IAR C, to make porting applications - between different compilers easier. No 100% compatibility though. - - \note For actual documentation, please see the IAR manual. - */ - -#ifndef _INA90_H_ -#define _INA90_H_ 1 - -#define _CLI() do { __asm__ __volatile__ ("cli"); } while (0) -#define _SEI() do { __asm__ __volatile__ ("sei"); } while (0) -#define _NOP() do { __asm__ __volatile__ ("nop"); } while (0) -#define _WDR() do { __asm__ __volatile__ ("wdr"); } while (0) -#define _SLEEP() do { __asm__ __volatile__ ("sleep"); } while (0) -#define _OPC(op) do { __asm__ __volatile__ (".word %0" : : "n" (op)); } while (0) - -/* _LPM, _ELPM */ -#include -#define _LPM(x) do { __LPM(x); } while (0) -#define _ELPM(x) do { __ELPM(x); } while (0) - -/* _EEGET, _EEPUT */ -#include - -#define input(port) (port) -#define output(port, val) do { (port) = (val); } while (0) - -#define __inp_blk__(port, addr, cnt, op) do { \ - unsigned char __i = (cnt); \ - unsigned char *__addr = (addr); \ - while (__i) { \ - *(__addr op) = input(port); \ - __i--; \ - } \ - } while (0) - -#define input_block_inc(port, addr, cnt) __inp_blk__(port, addr, cnt, ++) -#define input_block_dec(port, addr, cnt) __inp_blk__(port, addr, cnt, --) - -#define __out_blk__(port, addr, cnt, op) do { \ - unsigned char __i = (cnt); \ - const unsigned char *__addr = (addr); \ - while (__i) { \ - output(port, *(__addr op)); \ - __i--; \ - } \ - } while (0) - -#define output_block_inc(port, addr, cnt) __out_blk__(port, addr, cnt, ++) -#define output_block_dec(port, addr, cnt) __out_blk__(port, addr, cnt, --) - -#endif - diff --git a/arduino/hardware/tools/avr/avr/include/compat/twi.h b/arduino/hardware/tools/avr/avr/include/compat/twi.h deleted file mode 100644 index 082852f..0000000 --- a/arduino/hardware/tools/avr/avr/include/compat/twi.h +++ /dev/null @@ -1,38 +0,0 @@ -/* Copyright (c) 2005 Joerg Wunsch - All rights reserved. - - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - * Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - * Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in - the documentation and/or other materials provided with the - distribution. - - * Neither the name of the copyright holders nor the names of - contributors may be used to endorse or promote products derived - from this software without specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. */ - -/* $Id$ */ - -#ifndef _COMPAT_TWI_H_ -#define _COMPAT_TWI_H_ - -#include - -#endif /* _COMPAT_TWI_H_ */ diff --git a/arduino/hardware/tools/avr/avr/include/ctype.h b/arduino/hardware/tools/avr/avr/include/ctype.h deleted file mode 100644 index 82bce45..0000000 --- a/arduino/hardware/tools/avr/avr/include/ctype.h +++ /dev/null @@ -1,193 +0,0 @@ -/* Copyright (c) 2002,2007 Michael Stumpf - All rights reserved. - - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - * Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - * Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in - the documentation and/or other materials provided with the - distribution. - - * Neither the name of the copyright holders nor the names of - contributors may be used to endorse or promote products derived - from this software without specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. */ - -/* $Id$ */ - -/* - ctype.h - character conversion macros and ctype macros - - Author : Michael Stumpf - Michael.Stumpf@t-online.de -*/ - -#ifndef __CTYPE_H_ -#define __CTYPE_H_ 1 - -#ifndef __ATTR_CONST__ -#define __ATTR_CONST__ __attribute__((__const__)) -#endif - -#ifdef __cplusplus -extern "C" { -#endif - -/** \file */ -/** \defgroup ctype : Character Operations - These functions perform various operations on characters. - - \code #include \endcode - -*/ - -/** \name Character classification routines - - These functions perform character classification. They return true or - false status depending whether the character passed to the function falls - into the function's classification (i.e. isdigit() returns true if its - argument is any value '0' though '9', inclusive). If the input is not - an unsigned char value, all of this function return false. */ - - /* @{ */ - -/** \ingroup ctype - - Checks for an alphanumeric character. It is equivalent to (isalpha(c) - || isdigit(c)). */ - -extern int isalnum(int __c) __ATTR_CONST__; - -/** \ingroup ctype - - Checks for an alphabetic character. It is equivalent to (isupper(c) || - islower(c)). */ - -extern int isalpha(int __c) __ATTR_CONST__; - -/** \ingroup ctype - - Checks whether \c c is a 7-bit unsigned char value that fits into the - ASCII character set. */ - -extern int isascii(int __c) __ATTR_CONST__; - -/** \ingroup ctype - - Checks for a blank character, that is, a space or a tab. */ - -extern int isblank(int __c) __ATTR_CONST__; - -/** \ingroup ctype - - Checks for a control character. */ - -extern int iscntrl(int __c) __ATTR_CONST__; - -/** \ingroup ctype - - Checks for a digit (0 through 9). */ - -extern int isdigit(int __c) __ATTR_CONST__; - -/** \ingroup ctype - - Checks for any printable character except space. */ - -extern int isgraph(int __c) __ATTR_CONST__; - -/** \ingroup ctype - - Checks for a lower-case character. */ - -extern int islower(int __c) __ATTR_CONST__; - -/** \ingroup ctype - - Checks for any printable character including space. */ - -extern int isprint(int __c) __ATTR_CONST__; - -/** \ingroup ctype - - Checks for any printable character which is not a space or an alphanumeric - character. */ - -extern int ispunct(int __c) __ATTR_CONST__; - -/** \ingroup ctype - - Checks for white-space characters. For the avr-libc library, these are: - space, form-feed ('\\f'), newline ('\\n'), carriage return ('\\r'), - horizontal tab ('\\t'), and vertical tab ('\\v'). */ - -extern int isspace(int __c) __ATTR_CONST__; - -/** \ingroup ctype - - Checks for an uppercase letter. */ - -extern int isupper(int __c) __ATTR_CONST__; - -/** \ingroup ctype - - Checks for a hexadecimal digits, i.e. one of 0 1 2 3 4 5 6 7 8 9 a b c d e - f A B C D E F. */ - -extern int isxdigit(int __c) __ATTR_CONST__; - -/* @} */ - -/** \name Character convertion routines - - This realization permits all possible values of integer argument. - The toascii() function clears all highest bits. The tolower() and - toupper() functions return an input argument as is, if it is not an - unsigned char value. */ - -/* @{ */ - -/** \ingroup ctype - - Converts \c c to a 7-bit unsigned char value that fits into the ASCII - character set, by clearing the high-order bits. - - \warning Many people will be unhappy if you use this function. This - function will convert accented letters into random characters. */ - -extern int toascii(int __c) __ATTR_CONST__; - -/** \ingroup ctype - - Converts the letter \c c to lower case, if possible. */ - -extern int tolower(int __c) __ATTR_CONST__; - -/** \ingroup ctype - - Converts the letter \c c to upper case, if possible. */ - -extern int toupper(int __c) __ATTR_CONST__; - -/* @} */ - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/arduino/hardware/tools/avr/avr/include/errno.h b/arduino/hardware/tools/avr/avr/include/errno.h deleted file mode 100644 index f7c8cc8..0000000 --- a/arduino/hardware/tools/avr/avr/include/errno.h +++ /dev/null @@ -1,154 +0,0 @@ -/* Copyright (c) 2002,2007 Marek Michalkiewicz - All rights reserved. - - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - * Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - * Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in - the documentation and/or other materials provided with the - distribution. - - * Neither the name of the copyright holders nor the names of - contributors may be used to endorse or promote products derived - from this software without specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. */ - -/* $Id$ */ - -#ifndef __ERRNO_H_ -#define __ERRNO_H_ 1 - -/** \file */ -/** \defgroup avr_errno : System Errors - - \code #include \endcode - - Some functions in the library set the global variable \c errno when an - error occurs. The file, \c , provides symbolic names for various - error codes. - */ - -#ifdef __cplusplus -extern "C" { -#endif - -/** \ingroup avr_errno - \brief Error code for last error encountered by library - - The variable \c errno holds the last error code encountered by - a library function. This variable must be cleared by the - user prior to calling a library function. - - \warning The \c errno global variable is not safe to use in a threaded or - multi-task system. A race condition can occur if a task is interrupted - between the call which sets \c error and when the task examines \c - errno. If another task changes \c errno during this time, the result will - be incorrect for the interrupted task. */ -extern int errno; - -#ifdef __cplusplus -} -#endif - -/** \ingroup avr_errno - \def EDOM - - Domain error. */ -#define EDOM 33 - -/** \ingroup avr_errno - \def ERANGE - - Range error. */ -#define ERANGE 34 - -#ifndef __DOXYGEN__ - -/* ((((('E'-64)*26+('N'-64))*26+('O'-64))*26+('S'-64))*26+('Y'-64))*26+'S'-64 */ -#define ENOSYS ((int)(66081697 & 0x7fff)) - -/* (((('E'-64)*26+('I'-64))*26+('N'-64))*26+('T'-64))*26+('R'-64) */ -#define EINTR ((int)(2453066 & 0x7fff)) - -#define E2BIG ENOERR -#define EACCES ENOERR -#define EADDRINUSE ENOERR -#define EADDRNOTAVAIL ENOERR -#define EAFNOSUPPORT ENOERR -#define EAGAIN ENOERR -#define EALREADY ENOERR -#define EBADF ENOERR -#define EBUSY ENOERR -#define ECHILD ENOERR -#define ECONNABORTED ENOERR -#define ECONNREFUSED ENOERR -#define ECONNRESET ENOERR -#define EDEADLK ENOERR -#define EDESTADDRREQ ENOERR -#define EEXIST ENOERR -#define EFAULT ENOERR -#define EFBIG ENOERR -#define EHOSTUNREACH ENOERR -#define EILSEQ ENOERR -#define EINPROGRESS ENOERR -#define EINVAL ENOERR -#define EIO ENOERR -#define EISCONN ENOERR -#define EISDIR ENOERR -#define ELOOP ENOERR -#define EMFILE ENOERR -#define EMLINK ENOERR -#define EMSGSIZE ENOERR -#define ENAMETOOLONG ENOERR -#define ENETDOWN ENOERR -#define ENETRESET ENOERR -#define ENETUNREACH ENOERR -#define ENFILE ENOERR -#define ENOBUFS ENOERR -#define ENODEV ENOERR -#define ENOENT ENOERR -#define ENOEXEC ENOERR -#define ENOLCK ENOERR -#define ENOMEM ENOERR -#define ENOMSG ENOERR -#define ENOPROTOOPT ENOERR -#define ENOSPC ENOERR -#define ENOTCONN ENOERR -#define ENOTDIR ENOERR -#define ENOTEMPTY ENOERR -#define ENOTSOCK ENOERR -#define ENOTTY ENOERR -#define ENXIO ENOERR -#define EOPNOTSUPP ENOERR -#define EPERM ENOERR -#define EPIPE ENOERR -#define EPROTONOSUPPORT ENOERR -#define EPROTOTYPE ENOERR -#define EROFS ENOERR -#define ESPIPE ENOERR -#define ESRCH ENOERR -#define ETIMEDOUT ENOERR -#define EWOULDBLOCK ENOERR -#define EXDEV ENOERR - -/* ((((('E'-64)*26+('N'-64))*26+('O'-64))*26+('E'-64))*26+('R'-64))*26+'R'-64 */ -#define ENOERR ((int)(66072050 & 0xffff)) - -#endif /* !__DOXYGEN__ */ - -#endif diff --git a/arduino/hardware/tools/avr/avr/include/fcntl.h b/arduino/hardware/tools/avr/avr/include/fcntl.h deleted file mode 100644 index a12c43b..0000000 --- a/arduino/hardware/tools/avr/avr/include/fcntl.h +++ /dev/null @@ -1 +0,0 @@ -#include diff --git a/arduino/hardware/tools/avr/avr/include/inttypes.h b/arduino/hardware/tools/avr/avr/include/inttypes.h deleted file mode 100644 index 6e69d74..0000000 --- a/arduino/hardware/tools/avr/avr/include/inttypes.h +++ /dev/null @@ -1,555 +0,0 @@ -/* Copyright (c) 2004,2005,2007,2012 Joerg Wunsch - Copyright (c) 2005, Carlos Lamas - All rights reserved. - - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - * Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - * Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in - the documentation and/or other materials provided with the - distribution. - - * Neither the name of the copyright holders nor the names of - contributors may be used to endorse or promote products derived - from this software without specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. */ - -/* $Id$ */ - -#ifndef __INTTYPES_H_ -#define __INTTYPES_H_ - -#include - -/** \file */ -/** \defgroup avr_inttypes : Integer Type conversions - \code #include \endcode - - This header file includes the exact-width integer definitions from - , and extends them with additional facilities - provided by the implementation. - - Currently, the extensions include two additional integer types - that could hold a "far" pointer (i.e. a code pointer that can - address more than 64 KB), as well as standard names for all printf - and scanf formatting options that are supported by the \ref avr_stdio. - As the library does not support the full range of conversion - specifiers from ISO 9899:1999, only those conversions that are - actually implemented will be listed here. - - The idea behind these conversion macros is that, for each of the - types defined by , a macro will be supplied that portably - allows formatting an object of that type in printf() or scanf() - operations. Example: - - \code - #include - - uint8_t smallval; - int32_t longval; - ... - printf("The hexadecimal value of smallval is %" PRIx8 - ", the decimal value of longval is %" PRId32 ".\n", - smallval, longval); - \endcode -*/ - -/** \name Far pointers for memory access >64K */ - -/*@{*/ -/** \ingroup avr_inttypes - signed integer type that can hold a pointer > 64 KB */ -typedef int32_t int_farptr_t; - -/** \ingroup avr_inttypes - unsigned integer type that can hold a pointer > 64 KB */ -typedef uint32_t uint_farptr_t; -/*@}*/ - -#if !defined(__cplusplus) || defined(__STDC_LIMIT_MACROS) - - -/** \name macros for printf and scanf format specifiers - - For C++, these are only included if __STDC_LIMIT_MACROS - is defined before including . - */ - -/*@{*/ -/** \ingroup avr_inttypes - decimal printf format for int8_t */ -#define PRId8 "d" -/** \ingroup avr_inttypes - decimal printf format for int_least8_t */ -#define PRIdLEAST8 "d" -/** \ingroup avr_inttypes - decimal printf format for int_fast8_t */ -#define PRIdFAST8 "d" - -/** \ingroup avr_inttypes - integer printf format for int8_t */ -#define PRIi8 "i" -/** \ingroup avr_inttypes - integer printf format for int_least8_t */ -#define PRIiLEAST8 "i" -/** \ingroup avr_inttypes - integer printf format for int_fast8_t */ -#define PRIiFAST8 "i" - - -/** \ingroup avr_inttypes - decimal printf format for int16_t */ -#define PRId16 "d" -/** \ingroup avr_inttypes - decimal printf format for int_least16_t */ -#define PRIdLEAST16 "d" -/** \ingroup avr_inttypes - decimal printf format for int_fast16_t */ -#define PRIdFAST16 "d" - -/** \ingroup avr_inttypes - integer printf format for int16_t */ -#define PRIi16 "i" -/** \ingroup avr_inttypes - integer printf format for int_least16_t */ -#define PRIiLEAST16 "i" -/** \ingroup avr_inttypes - integer printf format for int_fast16_t */ -#define PRIiFAST16 "i" - - -/** \ingroup avr_inttypes - decimal printf format for int32_t */ -#define PRId32 "ld" -/** \ingroup avr_inttypes - decimal printf format for int_least32_t */ -#define PRIdLEAST32 "ld" -/** \ingroup avr_inttypes - decimal printf format for int_fast32_t */ -#define PRIdFAST32 "ld" - -/** \ingroup avr_inttypes - integer printf format for int32_t */ -#define PRIi32 "li" -/** \ingroup avr_inttypes - integer printf format for int_least32_t */ -#define PRIiLEAST32 "li" -/** \ingroup avr_inttypes - integer printf format for int_fast32_t */ -#define PRIiFAST32 "li" - - -#ifdef __avr_libc_does_not_implement_long_long_in_printf_or_scanf - -#define PRId64 "lld" -#define PRIdLEAST64 "lld" -#define PRIdFAST64 "lld" - -#define PRIi64 "lli" -#define PRIiLEAST64 "lli" -#define PRIiFAST64 "lli" - - -#define PRIdMAX "lld" -#define PRIiMAX "lli" - -#endif - -/** \ingroup avr_inttypes - decimal printf format for intptr_t */ -#define PRIdPTR PRId16 -/** \ingroup avr_inttypes - integer printf format for intptr_t */ -#define PRIiPTR PRIi16 - -/** \ingroup avr_inttypes - octal printf format for uint8_t */ -#define PRIo8 "o" -/** \ingroup avr_inttypes - octal printf format for uint_least8_t */ -#define PRIoLEAST8 "o" -/** \ingroup avr_inttypes - octal printf format for uint_fast8_t */ -#define PRIoFAST8 "o" - -/** \ingroup avr_inttypes - decimal printf format for uint8_t */ -#define PRIu8 "u" -/** \ingroup avr_inttypes - decimal printf format for uint_least8_t */ -#define PRIuLEAST8 "u" -/** \ingroup avr_inttypes - decimal printf format for uint_fast8_t */ -#define PRIuFAST8 "u" - -/** \ingroup avr_inttypes - hexadecimal printf format for uint8_t */ -#define PRIx8 "x" -/** \ingroup avr_inttypes - hexadecimal printf format for uint_least8_t */ -#define PRIxLEAST8 "x" -/** \ingroup avr_inttypes - hexadecimal printf format for uint_fast8_t */ -#define PRIxFAST8 "x" - -/** \ingroup avr_inttypes - uppercase hexadecimal printf format for uint8_t */ -#define PRIX8 "X" -/** \ingroup avr_inttypes - uppercase hexadecimal printf format for uint_least8_t */ -#define PRIXLEAST8 "X" -/** \ingroup avr_inttypes - uppercase hexadecimal printf format for uint_fast8_t */ -#define PRIXFAST8 "X" - - -/** \ingroup avr_inttypes - octal printf format for uint16_t */ -#define PRIo16 "o" -/** \ingroup avr_inttypes - octal printf format for uint_least16_t */ -#define PRIoLEAST16 "o" -/** \ingroup avr_inttypes - octal printf format for uint_fast16_t */ -#define PRIoFAST16 "o" - -/** \ingroup avr_inttypes - decimal printf format for uint16_t */ -#define PRIu16 "u" -/** \ingroup avr_inttypes - decimal printf format for uint_least16_t */ -#define PRIuLEAST16 "u" -/** \ingroup avr_inttypes - decimal printf format for uint_fast16_t */ -#define PRIuFAST16 "u" - -/** \ingroup avr_inttypes - hexadecimal printf format for uint16_t */ -#define PRIx16 "x" -/** \ingroup avr_inttypes - hexadecimal printf format for uint_least16_t */ -#define PRIxLEAST16 "x" -/** \ingroup avr_inttypes - hexadecimal printf format for uint_fast16_t */ -#define PRIxFAST16 "x" - -/** \ingroup avr_inttypes - uppercase hexadecimal printf format for uint16_t */ -#define PRIX16 "X" -/** \ingroup avr_inttypes - uppercase hexadecimal printf format for uint_least16_t */ -#define PRIXLEAST16 "X" -/** \ingroup avr_inttypes - uppercase hexadecimal printf format for uint_fast16_t */ -#define PRIXFAST16 "X" - - -/** \ingroup avr_inttypes - octal printf format for uint32_t */ -#define PRIo32 "lo" -/** \ingroup avr_inttypes - octal printf format for uint_least32_t */ -#define PRIoLEAST32 "lo" -/** \ingroup avr_inttypes - octal printf format for uint_fast32_t */ -#define PRIoFAST32 "lo" - -/** \ingroup avr_inttypes - decimal printf format for uint32_t */ -#define PRIu32 "lu" -/** \ingroup avr_inttypes - decimal printf format for uint_least32_t */ -#define PRIuLEAST32 "lu" -/** \ingroup avr_inttypes - decimal printf format for uint_fast32_t */ -#define PRIuFAST32 "lu" - -/** \ingroup avr_inttypes - hexadecimal printf format for uint32_t */ -#define PRIx32 "lx" -/** \ingroup avr_inttypes - hexadecimal printf format for uint_least32_t */ -#define PRIxLEAST32 "lx" -/** \ingroup avr_inttypes - hexadecimal printf format for uint_fast32_t */ -#define PRIxFAST32 "lx" - -/** \ingroup avr_inttypes - uppercase hexadecimal printf format for uint32_t */ -#define PRIX32 "lX" -/** \ingroup avr_inttypes - uppercase hexadecimal printf format for uint_least32_t */ -#define PRIXLEAST32 "lX" -/** \ingroup avr_inttypes - uppercase hexadecimal printf format for uint_fast32_t */ -#define PRIXFAST32 "lX" - - -#ifdef __avr_libc_does_not_implement_long_long_in_printf_or_scanf - -#define PRIo64 "llo" -#define PRIoLEAST64 "llo" -#define PRIoFAST64 "llo" - -#define PRIu64 "llu" -#define PRIuLEAST64 "llu" -#define PRIuFAST64 "llu" - -#define PRIx64 "llx" -#define PRIxLEAST64 "llx" -#define PRIxFAST64 "llx" - -#define PRIX64 "llX" -#define PRIXLEAST64 "llX" -#define PRIXFAST64 "llX" - -#define PRIoMAX "llo" -#define PRIuMAX "llu" -#define PRIxMAX "llx" -#define PRIXMAX "llX" - -#endif - -/** \ingroup avr_inttypes - octal printf format for uintptr_t */ -#define PRIoPTR PRIo16 -/** \ingroup avr_inttypes - decimal printf format for uintptr_t */ -#define PRIuPTR PRIu16 -/** \ingroup avr_inttypes - hexadecimal printf format for uintptr_t */ -#define PRIxPTR PRIx16 -/** \ingroup avr_inttypes - uppercase hexadecimal printf format for uintptr_t */ -#define PRIXPTR PRIX16 - - -/** \ingroup avr_inttypes - decimal scanf format for int8_t */ -#define SCNd8 "hhd" -/** \ingroup avr_inttypes - decimal scanf format for int_least8_t */ -#define SCNdLEAST8 "hhd" -/** \ingroup avr_inttypes - decimal scanf format for int_fast8_t */ -#define SCNdFAST8 "hhd" - -/** \ingroup avr_inttypes - generic-integer scanf format for int8_t */ -#define SCNi8 "hhi" -/** \ingroup avr_inttypes - generic-integer scanf format for int_least8_t */ -#define SCNiLEAST8 "hhi" -/** \ingroup avr_inttypes - generic-integer scanf format for int_fast8_t */ -#define SCNiFAST8 "hhi" - - -/** \ingroup avr_inttypes - decimal scanf format for int16_t */ -#define SCNd16 "d" -/** \ingroup avr_inttypes - decimal scanf format for int_least16_t */ -#define SCNdLEAST16 "d" -/** \ingroup avr_inttypes - decimal scanf format for int_fast16_t */ -#define SCNdFAST16 "d" - -/** \ingroup avr_inttypes - generic-integer scanf format for int16_t */ -#define SCNi16 "i" -/** \ingroup avr_inttypes - generic-integer scanf format for int_least16_t */ -#define SCNiLEAST16 "i" -/** \ingroup avr_inttypes - generic-integer scanf format for int_fast16_t */ -#define SCNiFAST16 "i" - - -/** \ingroup avr_inttypes - decimal scanf format for int32_t */ -#define SCNd32 "ld" -/** \ingroup avr_inttypes - decimal scanf format for int_least32_t */ -#define SCNdLEAST32 "ld" -/** \ingroup avr_inttypes - decimal scanf format for int_fast32_t */ -#define SCNdFAST32 "ld" - -/** \ingroup avr_inttypes - generic-integer scanf format for int32_t */ -#define SCNi32 "li" -/** \ingroup avr_inttypes - generic-integer scanf format for int_least32_t */ -#define SCNiLEAST32 "li" -/** \ingroup avr_inttypes - generic-integer scanf format for int_fast32_t */ -#define SCNiFAST32 "li" - - -#ifdef __avr_libc_does_not_implement_long_long_in_printf_or_scanf - -#define SCNd64 "lld" -#define SCNdLEAST64 "lld" -#define SCNdFAST64 "lld" - -#define SCNi64 "lli" -#define SCNiLEAST64 "lli" -#define SCNiFAST64 "lli" - -#define SCNdMAX "lld" -#define SCNiMAX "lli" - -#endif - -/** \ingroup avr_inttypes - decimal scanf format for intptr_t */ -#define SCNdPTR SCNd16 -/** \ingroup avr_inttypes - generic-integer scanf format for intptr_t */ -#define SCNiPTR SCNi16 - -/** \ingroup avr_inttypes - octal scanf format for uint8_t */ -#define SCNo8 "hho" -/** \ingroup avr_inttypes - octal scanf format for uint_least8_t */ -#define SCNoLEAST8 "hho" -/** \ingroup avr_inttypes - octal scanf format for uint_fast8_t */ -#define SCNoFAST8 "hho" - -/** \ingroup avr_inttypes - decimal scanf format for uint8_t */ -#define SCNu8 "hhu" -/** \ingroup avr_inttypes - decimal scanf format for uint_least8_t */ -#define SCNuLEAST8 "hhu" -/** \ingroup avr_inttypes - decimal scanf format for uint_fast8_t */ -#define SCNuFAST8 "hhu" - -/** \ingroup avr_inttypes - hexadecimal scanf format for uint8_t */ -#define SCNx8 "hhx" -/** \ingroup avr_inttypes - hexadecimal scanf format for uint_least8_t */ -#define SCNxLEAST8 "hhx" -/** \ingroup avr_inttypes - hexadecimal scanf format for uint_fast8_t */ -#define SCNxFAST8 "hhx" - -/** \ingroup avr_inttypes - octal scanf format for uint16_t */ -#define SCNo16 "o" -/** \ingroup avr_inttypes - octal scanf format for uint_least16_t */ -#define SCNoLEAST16 "o" -/** \ingroup avr_inttypes - octal scanf format for uint_fast16_t */ -#define SCNoFAST16 "o" - -/** \ingroup avr_inttypes - decimal scanf format for uint16_t */ -#define SCNu16 "u" -/** \ingroup avr_inttypes - decimal scanf format for uint_least16_t */ -#define SCNuLEAST16 "u" -/** \ingroup avr_inttypes - decimal scanf format for uint_fast16_t */ -#define SCNuFAST16 "u" - -/** \ingroup avr_inttypes - hexadecimal scanf format for uint16_t */ -#define SCNx16 "x" -/** \ingroup avr_inttypes - hexadecimal scanf format for uint_least16_t */ -#define SCNxLEAST16 "x" -/** \ingroup avr_inttypes - hexadecimal scanf format for uint_fast16_t */ -#define SCNxFAST16 "x" - - -/** \ingroup avr_inttypes - octal scanf format for uint32_t */ -#define SCNo32 "lo" -/** \ingroup avr_inttypes - octal scanf format for uint_least32_t */ -#define SCNoLEAST32 "lo" -/** \ingroup avr_inttypes - octal scanf format for uint_fast32_t */ -#define SCNoFAST32 "lo" - -/** \ingroup avr_inttypes - decimal scanf format for uint32_t */ -#define SCNu32 "lu" -/** \ingroup avr_inttypes - decimal scanf format for uint_least32_t */ -#define SCNuLEAST32 "lu" -/** \ingroup avr_inttypes - decimal scanf format for uint_fast32_t */ -#define SCNuFAST32 "lu" - -/** \ingroup avr_inttypes - hexadecimal scanf format for uint32_t */ -#define SCNx32 "lx" -/** \ingroup avr_inttypes - hexadecimal scanf format for uint_least32_t */ -#define SCNxLEAST32 "lx" -/** \ingroup avr_inttypes - hexadecimal scanf format for uint_fast32_t */ -#define SCNxFAST32 "lx" - - -#ifdef __avr_libc_does_not_implement_long_long_in_printf_or_scanf - -#define SCNo64 "llo" -#define SCNoLEAST64 "llo" -#define SCNoFAST64 "llo" - -#define SCNu64 "llu" -#define SCNuLEAST64 "llu" -#define SCNuFAST64 "llu" - -#define SCNx64 "llx" -#define SCNxLEAST64 "llx" -#define SCNxFAST64 "llx" - -#define SCNoMAX "llo" -#define SCNuMAX "llu" -#define SCNxMAX "llx" - -#endif - -/** \ingroup avr_inttypes - octal scanf format for uintptr_t */ -#define SCNoPTR SCNo16 -/** \ingroup avr_inttypes - decimal scanf format for uintptr_t */ -#define SCNuPTR SCNu16 -/** \ingroup avr_inttypes - hexadecimal scanf format for uintptr_t */ -#define SCNxPTR SCNx16 - -/*@}*/ - - -#endif /* !defined(__cplusplus) || defined(__STDC_LIMIT_MACROS) */ - - -#endif /* __INTTYPES_H_ */ diff --git a/arduino/hardware/tools/avr/avr/include/locale.h b/arduino/hardware/tools/avr/avr/include/locale.h deleted file mode 100644 index 91ae7bc..0000000 --- a/arduino/hardware/tools/avr/avr/include/locale.h +++ /dev/null @@ -1,17 +0,0 @@ -#ifndef _LOCALE_H -#define _LOCALE_H - -#if 1 /* ??? unimplemented */ -#define LC_ALL 0 -#define LC_COLLATE 1 -#define LC_CTYPE 2 -#define LC_MESSAGES 3 -#define LC_MONETARY 4 -#define LC_NUMERIC 5 -#define LC_TIME 6 -struct lconv; -extern char *setlocale(int category, const char *locale); -extern struct lconv *localeconv(void); -#endif - -#endif /* L_OCALE_H */ diff --git a/arduino/hardware/tools/avr/avr/include/math.h b/arduino/hardware/tools/avr/avr/include/math.h deleted file mode 100644 index 92e2b12..0000000 --- a/arduino/hardware/tools/avr/avr/include/math.h +++ /dev/null @@ -1,462 +0,0 @@ -/* Copyright (c) 2002,2007-2009 Michael Stumpf - - Portions of documentation Copyright (c) 1990 - 1994 - The Regents of the University of California. - - All rights reserved. - - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - * Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - * Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in - the documentation and/or other materials provided with the - distribution. - - * Neither the name of the copyright holders nor the names of - contributors may be used to endorse or promote products derived - from this software without specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. */ - -/* $Id$ */ - -/* - math.h - mathematical functions - - Author : Michael Stumpf - Michael.Stumpf@t-online.de - - __ATTR_CONST__ added by marekm@linux.org.pl for functions - that "do not examine any values except their arguments, and have - no effects except the return value", for better optimization by gcc. - */ - -#ifndef __MATH_H -#define __MATH_H - -/** \file */ -/** \defgroup avr_math : Mathematics - \code #include \endcode - - This header file declares basic mathematics constants and - functions. - - \par Notes: - - In order to access the functions declared herein, it is usually - also required to additionally link against the library \c libm.a. - See also the related \ref faq_libm "FAQ entry". - - Math functions do not raise exceptions and do not change the - \c errno variable. Therefore the majority of them are declared - with const attribute, for better optimization by GCC. */ - - -/** \ingroup avr_math */ -/*@{*/ - -/** The constant \a e. */ -#define M_E 2.7182818284590452354 - -/** The logarithm of the \a e to base 2. */ -#define M_LOG2E 1.4426950408889634074 /* log_2 e */ - -/** The logarithm of the \a e to base 10. */ -#define M_LOG10E 0.43429448190325182765 /* log_10 e */ - -/** The natural logarithm of the 2. */ -#define M_LN2 0.69314718055994530942 /* log_e 2 */ - -/** The natural logarithm of the 10. */ -#define M_LN10 2.30258509299404568402 /* log_e 10 */ - -/** The constant \a pi. */ -#define M_PI 3.14159265358979323846 /* pi */ - -/** The constant \a pi/2. */ -#define M_PI_2 1.57079632679489661923 /* pi/2 */ - -/** The constant \a pi/4. */ -#define M_PI_4 0.78539816339744830962 /* pi/4 */ - -/** The constant \a 1/pi. */ -#define M_1_PI 0.31830988618379067154 /* 1/pi */ - -/** The constant \a 2/pi. */ -#define M_2_PI 0.63661977236758134308 /* 2/pi */ - -/** The constant \a 2/sqrt(pi). */ -#define M_2_SQRTPI 1.12837916709551257390 /* 2/sqrt(pi) */ - -/** The square root of 2. */ -#define M_SQRT2 1.41421356237309504880 /* sqrt(2) */ - -/** The constant \a 1/sqrt(2). */ -#define M_SQRT1_2 0.70710678118654752440 /* 1/sqrt(2) */ - -/** NAN constant. */ -#define NAN __builtin_nan("") - -/** INFINITY constant. */ -#define INFINITY __builtin_inf() - - -#ifndef __ATTR_CONST__ -# define __ATTR_CONST__ __attribute__((__const__)) -#endif - -#ifdef __cplusplus -extern "C" { -#endif - -/** - The cos() function returns the cosine of \a __x, measured in radians. - */ -extern double cos(double __x) __ATTR_CONST__; -#define cosf cos /**< The alias for cos(). */ - -/** - The sin() function returns the sine of \a __x, measured in radians. - */ -extern double sin(double __x) __ATTR_CONST__; -#define sinf sin /**< The alias for sin(). */ - -/** - The tan() function returns the tangent of \a __x, measured in radians. - */ -extern double tan(double __x) __ATTR_CONST__; -#define tanf tan /**< The alias for tan(). */ - -/** - The fabs() function computes the absolute value of a floating-point - number \a __x. - */ -extern double fabs(double __x) __ATTR_CONST__; -#define fabsf fabs /**< The alias for fabs(). */ - -/** - The function fmod() returns the floating-point remainder of __x / - __y. - */ -extern double fmod(double __x, double __y) __ATTR_CONST__; -#define fmodf fmod /**< The alias for fmod(). */ - -/** - The modf() function breaks the argument \a __x into integral and - fractional parts, each of which has the same sign as the argument. - It stores the integral part as a double in the object pointed to by - \a __iptr. - - The modf() function returns the signed fractional part of \a __x. - - \note This implementation skips writing by zero pointer. However, - the GCC 4.3 can replace this function with inline code that does not - permit to use NULL address for the avoiding of storing. - */ -extern double modf(double __x, double *__iptr); - -/** An alias for modf(). */ -extern float modff (float __x, float *__iptr); - -/** - The sqrt() function returns the non-negative square root of \a __x. - */ -extern double sqrt(double __x) __ATTR_CONST__; - -/** An alias for sqrt(). */ -extern float sqrtf (float) __ATTR_CONST__; - -/** - The cbrt() function returns the cube root of \a __x. - */ -extern double cbrt(double __x) __ATTR_CONST__; -#define cbrtf cbrt /**< The alias for cbrt(). */ - -/** - The hypot() function returns sqrt(__x*__x + __y*__y). This - is the length of the hypotenuse of a right triangle with sides of - length \a __x and \a __y, or the distance of the point (\a __x, \a - __y) from the origin. Using this function instead of the direct - formula is wise, since the error is much smaller. No underflow with - small \a __x and \a __y. No overflow if result is in range. - */ -extern double hypot (double __x, double __y) __ATTR_CONST__; -#define hypotf hypot /**< The alias for hypot(). */ - -/** - The function square() returns __x * __x. - - \note This function does not belong to the C standard definition. - */ -extern double square(double __x) __ATTR_CONST__; -#define squaref square /**< The alias for square(). */ - -/** - The floor() function returns the largest integral value less than or - equal to \a __x, expressed as a floating-point number. - */ -extern double floor(double __x) __ATTR_CONST__; -#define floorf floor /**< The alias for floor(). */ - -/** - The ceil() function returns the smallest integral value greater than - or equal to \a __x, expressed as a floating-point number. - */ -extern double ceil(double __x) __ATTR_CONST__; -#define ceilf ceil /**< The alias for ceil(). */ - -/** - The frexp() function breaks a floating-point number into a normalized - fraction and an integral power of 2. It stores the integer in the \c - int object pointed to by \a __pexp. - - If \a __x is a normal float point number, the frexp() function - returns the value \c v, such that \c v has a magnitude in the - interval [1/2, 1) or zero, and \a __x equals \c v times 2 raised to - the power \a __pexp. If \a __x is zero, both parts of the result are - zero. If \a __x is not a finite number, the frexp() returns \a __x as - is and stores 0 by \a __pexp. - - \note This implementation permits a zero pointer as a directive to - skip a storing the exponent. - */ -extern double frexp(double __x, int *__pexp); -#define frexpf frexp /**< The alias for frexp(). */ - -/** - The ldexp() function multiplies a floating-point number by an integral - power of 2. It returns the value of \a __x times 2 raised to the power - \a __exp. - */ -extern double ldexp(double __x, int __exp) __ATTR_CONST__; -#define ldexpf ldexp /**< The alias for ldexp(). */ - -/** - The exp() function returns the exponential value of \a __x. - */ -extern double exp(double __x) __ATTR_CONST__; -#define expf exp /**< The alias for exp(). */ - -/** - The cosh() function returns the hyperbolic cosine of \a __x. - */ -extern double cosh(double __x) __ATTR_CONST__; -#define coshf cosh /**< The alias for cosh(). */ - -/** - The sinh() function returns the hyperbolic sine of \a __x. - */ -extern double sinh(double __x) __ATTR_CONST__; -#define sinhf sinh /**< The alias for sinh(). */ - -/** - The tanh() function returns the hyperbolic tangent of \a __x. - */ -extern double tanh(double __x) __ATTR_CONST__; -#define tanhf tanh /**< The alias for tanh(). */ - -/** - The acos() function computes the principal value of the arc cosine of - \a __x. The returned value is in the range [0, pi] radians. A domain - error occurs for arguments not in the range [-1, +1]. - */ -extern double acos(double __x) __ATTR_CONST__; -#define acosf acos /**< The alias for acos(). */ - -/** - The asin() function computes the principal value of the arc sine of - \a __x. The returned value is in the range [-pi/2, pi/2] radians. A - domain error occurs for arguments not in the range [-1, +1]. - */ -extern double asin(double __x) __ATTR_CONST__; -#define asinf asin /**< The alias for asin(). */ - -/** - The atan() function computes the principal value of the arc tangent - of \a __x. The returned value is in the range [-pi/2, pi/2] radians. - */ -extern double atan(double __x) __ATTR_CONST__; -#define atanf atan /**< The alias for atan(). */ - -/** - The atan2() function computes the principal value of the arc tangent - of __y / __x, using the signs of both arguments to determine - the quadrant of the return value. The returned value is in the range - [-pi, +pi] radians. - */ -extern double atan2(double __y, double __x) __ATTR_CONST__; -#define atan2f atan2 /**< The alias for atan2(). */ - -/** - The log() function returns the natural logarithm of argument \a __x. - */ -extern double log(double __x) __ATTR_CONST__; -#define logf log /**< The alias for log(). */ - -/** - The log10() function returns the logarithm of argument \a __x to base 10. - */ -extern double log10(double __x) __ATTR_CONST__; -#define log10f log10 /**< The alias for log10(). */ - -/** - The function pow() returns the value of \a __x to the exponent \a __y. - */ -extern double pow(double __x, double __y) __ATTR_CONST__; -#define powf pow /**< The alias for pow(). */ - -/** - The function isnan() returns 1 if the argument \a __x represents a - "not-a-number" (NaN) object, otherwise 0. - */ -extern int isnan(double __x) __ATTR_CONST__; -#define isnanf isnan /**< The alias for isnan(). */ - -/** - The function isinf() returns 1 if the argument \a __x is positive - infinity, -1 if \a __x is negative infinity, and 0 otherwise. - - \note The GCC 4.3 can replace this function with inline code that - returns the 1 value for both infinities (gcc bug #35509). - */ -extern int isinf(double __x) __ATTR_CONST__; -#define isinff isinf /**< The alias for isinf(). */ - -/** - The isfinite() function returns a nonzero value if \a __x is finite: - not plus or minus infinity, and not NaN. - */ -__ATTR_CONST__ static inline int isfinite (double __x) -{ - unsigned char __exp; - __asm__ ( - "mov %0, %C1 \n\t" - "lsl %0 \n\t" - "mov %0, %D1 \n\t" - "rol %0 " - : "=r" (__exp) - : "r" (__x) ); - return __exp != 0xff; -} -#define isfinitef isfinite /**< The alias for isfinite(). */ - -/** - The copysign() function returns \a __x but with the sign of \a __y. - They work even if \a __x or \a __y are NaN or zero. -*/ -__ATTR_CONST__ static inline double copysign (double __x, double __y) -{ - __asm__ ( - "bst %D2, 7 \n\t" - "bld %D0, 7 " - : "=r" (__x) - : "0" (__x), "r" (__y) ); - return __x; -} -#define copysignf copysign /**< The alias for copysign(). */ - -/** - The signbit() function returns a nonzero value if the value of \a __x - has its sign bit set. This is not the same as `\a __x < 0.0', - because IEEE 754 floating point allows zero to be signed. The - comparison `-0.0 < 0.0' is false, but `signbit (-0.0)' will return a - nonzero value. - */ -extern int signbit (double __x) __ATTR_CONST__; -#define signbitf signbit /**< The alias for signbit(). */ - -/** - The fdim() function returns max(__x - __y, 0). If \a __x or - \a __y or both are NaN, NaN is returned. - */ -extern double fdim (double __x, double __y) __ATTR_CONST__; -#define fdimf fdim /**< The alias for fdim(). */ - -/** - The fma() function performs floating-point multiply-add. This is the - operation (__x * __y) + __z, but the intermediate result is - not rounded to the destination type. This can sometimes improve the - precision of a calculation. - */ -extern double fma (double __x, double __y, double __z) __ATTR_CONST__; -#define fmaf fma /**< The alias for fma(). */ - -/** - The fmax() function returns the greater of the two values \a __x and - \a __y. If an argument is NaN, the other argument is returned. If - both arguments are NaN, NaN is returned. - */ -extern double fmax (double __x, double __y) __ATTR_CONST__; -#define fmaxf fmax /**< The alias for fmax(). */ - -/** - The fmin() function returns the lesser of the two values \a __x and - \a __y. If an argument is NaN, the other argument is returned. If - both arguments are NaN, NaN is returned. - */ -extern double fmin (double __x, double __y) __ATTR_CONST__; -#define fminf fmin /**< The alias for fmin(). */ - -/** - The trunc() function rounds \a __x to the nearest integer not larger - in absolute value. - */ -extern double trunc (double __x) __ATTR_CONST__; -#define truncf trunc /**< The alias for trunc(). */ - -/** - The round() function rounds \a __x to the nearest integer, but rounds - halfway cases away from zero (instead of to the nearest even integer). - Overflow is impossible. - - \return The rounded value. If \a __x is an integral or infinite, \a - __x itself is returned. If \a __x is \c NaN, then \c NaN is returned. - */ -extern double round (double __x) __ATTR_CONST__; -#define roundf round /**< The alias for round(). */ - -/** - The lround() function rounds \a __x to the nearest integer, but rounds - halfway cases away from zero (instead of to the nearest even integer). - This function is similar to round() function, but it differs in type of - return value and in that an overflow is possible. - - \return The rounded long integer value. If \a __x is not a finite number - or an overflow was, this realization returns the \c LONG_MIN value - (0x80000000). - */ -extern long lround (double __x) __ATTR_CONST__; -#define lroundf lround /**< The alias for lround(). */ - -/** - The lrint() function rounds \a __x to the nearest integer, rounding the - halfway cases to the even integer direction. (That is both 1.5 and 2.5 - values are rounded to 2). This function is similar to rint() function, - but it differs in type of return value and in that an overflow is - possible. - - \return The rounded long integer value. If \a __x is not a finite - number or an overflow was, this realization returns the \c LONG_MIN - value (0x80000000). - */ -extern long lrint (double __x) __ATTR_CONST__; -#define lrintf lrint /**< The alias for lrint(). */ - -#ifdef __cplusplus -} -#endif - -/*@}*/ -#endif /* !__MATH_H */ diff --git a/arduino/hardware/tools/avr/avr/include/setjmp.h b/arduino/hardware/tools/avr/avr/include/setjmp.h deleted file mode 100644 index 1038a1e..0000000 --- a/arduino/hardware/tools/avr/avr/include/setjmp.h +++ /dev/null @@ -1,163 +0,0 @@ -/* Copyright (c) 2002,2007 Marek Michalkiewicz - All rights reserved. - - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - * Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - * Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in - the documentation and/or other materials provided with the - distribution. - - * Neither the name of the copyright holders nor the names of - contributors may be used to endorse or promote products derived - from this software without specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. */ - -/* $Id$ */ - -#ifndef __SETJMP_H_ -#define __SETJMP_H_ 1 - -#ifdef __cplusplus -extern "C" { -#endif - -/* - jmp_buf: - offset size description - 0 16/2 call-saved registers (r2-r17) - (AVR_TINY arch has only 2 call saved registers (r18,r19)) - 16/2 2 frame pointer (r29:r28) - 18/4 2 stack pointer (SPH:SPL) - 20/6 1 status register (SREG) - 21/7 2/3 return address (PC) (2 bytes used for <=128Kw flash) - 23/24/9 = total size (AVR_TINY arch always has 2 bytes PC) - */ - -#if !defined(__DOXYGEN__) - -#if defined(__AVR_TINY__) -# define _JBLEN 9 -#elif defined(__AVR_3_BYTE_PC__) && __AVR_3_BYTE_PC__ -# define _JBLEN 24 -#else -# define _JBLEN 23 -#endif -typedef struct _jmp_buf { unsigned char _jb[_JBLEN]; } jmp_buf[1]; - -#endif /* not __DOXYGEN__ */ - -/** \file */ -/** \defgroup setjmp : Non-local goto - - While the C language has the dreaded \c goto statement, it can only be - used to jump to a label in the same (local) function. In order to jump - directly to another (non-local) function, the C library provides the - setjmp() and longjmp() functions. setjmp() and longjmp() are useful for - dealing with errors and interrupts encountered in a low-level subroutine - of a program. - - \note setjmp() and longjmp() make programs hard to understand and maintain. - If possible, an alternative should be used. - - \note longjmp() can destroy changes made to global register - variables (see \ref faq_regbind). - - For a very detailed discussion of setjmp()/longjmp(), see Chapter 7 of - Advanced Programming in the UNIX Environment, by W. Richard - Stevens. - - Example: - - \code - #include - - jmp_buf env; - - int main (void) - { - if (setjmp (env)) - { - ... handle error ... - } - - while (1) - { - ... main processing loop which calls foo() some where ... - } - } - - ... - - void foo (void) - { - ... blah, blah, blah ... - - if (err) - { - longjmp (env, 1); - } - } - \endcode */ - -#if !(defined(__ATTR_NORETURN__) || defined(__DOXYGEN__)) -#define __ATTR_NORETURN__ __attribute__((__noreturn__)) -#endif - -/** \ingroup setjmp - \brief Save stack context for non-local goto. - - \code #include \endcode - - setjmp() saves the stack context/environment in \e __jmpb for later use by - longjmp(). The stack context will be invalidated if the function which - called setjmp() returns. - - \param __jmpb Variable of type \c jmp_buf which holds the stack - information such that the environment can be restored. - - \returns setjmp() returns 0 if returning directly, and - non-zero when returning from longjmp() using the saved context. */ - -extern int setjmp(jmp_buf __jmpb); - -/** \ingroup setjmp - \brief Non-local jump to a saved stack context. - - \code #include \endcode - - longjmp() restores the environment saved by the last call of setjmp() with - the corresponding \e __jmpb argument. After longjmp() is completed, - program execution continues as if the corresponding call of setjmp() had - just returned the value \e __ret. - - \note longjmp() cannot cause 0 to be returned. If longjmp() is invoked - with a second argument of 0, 1 will be returned instead. - - \param __jmpb Information saved by a previous call to setjmp(). - \param __ret Value to return to the caller of setjmp(). - - \returns This function never returns. */ - -extern void longjmp(jmp_buf __jmpb, int __ret) __ATTR_NORETURN__; - -#ifdef __cplusplus -} -#endif - -#endif /* !__SETJMP_H_ */ diff --git a/arduino/hardware/tools/avr/avr/include/signal.h b/arduino/hardware/tools/avr/avr/include/signal.h deleted file mode 100644 index 5274fcd..0000000 --- a/arduino/hardware/tools/avr/avr/include/signal.h +++ /dev/null @@ -1,20 +0,0 @@ -#ifndef _SIGNAL_H -#define _SIGNAL_H - -/* A minimal header to allow libstdc++-v3 pre-compiled headers to build. - We just pretend that there are signal / raise functions, even though - they are not implemented. */ -typedef void (*sighandler_t)(int); -extern sighandler_t signal(int signum, sighandler_t handler); - -#define SIG_DFL ((sighandler_t)0) -#define SIG_ERR ((sighandler_t)((void*)signal+1)) -#define SIG_HOLD ((sighandler_t)((void*)signal+2)) -#define SIG_IGN ((sighandler_t)((void*)signal+3)) - -volatile signed char sig_atomic_t; -typedef int sigset_t; - -extern int raise(int sig); - -#endif /* _SIGNAL_H */ diff --git a/arduino/hardware/tools/avr/avr/include/stdfix-avrlibc.h b/arduino/hardware/tools/avr/avr/include/stdfix-avrlibc.h deleted file mode 100644 index d133999..0000000 --- a/arduino/hardware/tools/avr/avr/include/stdfix-avrlibc.h +++ /dev/null @@ -1,49 +0,0 @@ -/* Copyright (c) 2013 Joerg Wunsch - All rights reserved. - - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - * Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - * Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in - the documentation and/or other materials provided with the - distribution. - - * Neither the name of the copyright holders nor the names of - contributors may be used to endorse or promote products derived - from this software without specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. */ - -/* $Id$ */ - -#ifndef _STDFIX_AVRLIBC_H -#define _STDFIX_AVRLIBC_H - -/* - * avr-libc addendum file for Embedded C Fixed-Point support - * - * See: ISO/IEC TR 18037 - * http://www.open-std.org/jtc1/sc22/wg14/www/docs/n1169.pdf - */ - -#ifndef _AVRGCC_STDFIX_H /* Defined in stdfix.h from avr-gcc */ -#warning please include directly rather than -#endif /* _AVRGCC_STDFIX_H */ - -/* Room for avr-libc specific extensions */ - -#endif /* _STDFIX_AVRLIBC_H */ diff --git a/arduino/hardware/tools/avr/avr/include/stdint.h b/arduino/hardware/tools/avr/avr/include/stdint.h deleted file mode 100644 index a882e30..0000000 --- a/arduino/hardware/tools/avr/avr/include/stdint.h +++ /dev/null @@ -1,706 +0,0 @@ -/* Copyright (c) 2002,2004,2005 Marek Michalkiewicz - Copyright (c) 2005, Carlos Lamas - Copyright (c) 2005,2007 Joerg Wunsch - Copyright (c) 2013 Embecosm - All rights reserved. - - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - * Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - * Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in - the documentation and/or other materials provided with the - distribution. - - * Neither the name of the copyright holders nor the names of - contributors may be used to endorse or promote products derived - from this software without specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. */ - -/* $Id$ */ - -/* - * ISO/IEC 9899:1999 7.18 Integer types - */ - -#ifndef __STDINT_H_ -#define __STDINT_H_ - -/** \file */ -/** \defgroup avr_stdint : Standard Integer Types - \code #include \endcode - - Use [u]intN_t if you need exactly N bits. - - Since these typedefs are mandated by the C99 standard, they are preferred - over rolling your own typedefs. */ - -#ifndef __DOXYGEN__ -/* - * __USING_MINT8 is defined to 1 if the -mint8 option is in effect. - */ -#if __INT_MAX__ == 127 -# define __USING_MINT8 1 -#else -# define __USING_MINT8 0 -#endif - -#endif /* !__DOXYGEN__ */ - -/* Integer types */ - -#if defined(__DOXYGEN__) - -/* doxygen gets confused by the __attribute__ stuff */ - -/** \name Exact-width integer types - Integer types having exactly the specified width */ - -/*@{*/ - -/** \ingroup avr_stdint - 8-bit signed type. */ - -typedef signed char int8_t; - -/** \ingroup avr_stdint - 8-bit unsigned type. */ - -typedef unsigned char uint8_t; - -/** \ingroup avr_stdint - 16-bit signed type. */ - -typedef signed int int16_t; - -/** \ingroup avr_stdint - 16-bit unsigned type. */ - -typedef unsigned int uint16_t; - -/** \ingroup avr_stdint - 32-bit signed type. */ - -typedef signed long int int32_t; - -/** \ingroup avr_stdint - 32-bit unsigned type. */ - -typedef unsigned long int uint32_t; - -/** \ingroup avr_stdint - 64-bit signed type. - \note This type is not available when the compiler - option -mint8 is in effect. */ - -typedef signed long long int int64_t; - -/** \ingroup avr_stdint - 64-bit unsigned type. - \note This type is not available when the compiler - option -mint8 is in effect. */ - -typedef unsigned long long int uint64_t; - -/*@}*/ - -#else /* !defined(__DOXYGEN__) */ - -/* actual implementation goes here */ - -typedef signed int int8_t __attribute__((__mode__(__QI__))); -typedef unsigned int uint8_t __attribute__((__mode__(__QI__))); -typedef signed int int16_t __attribute__ ((__mode__ (__HI__))); -typedef unsigned int uint16_t __attribute__ ((__mode__ (__HI__))); -typedef signed int int32_t __attribute__ ((__mode__ (__SI__))); -typedef unsigned int uint32_t __attribute__ ((__mode__ (__SI__))); -#if !__USING_MINT8 -typedef signed int int64_t __attribute__((__mode__(__DI__))); -typedef unsigned int uint64_t __attribute__((__mode__(__DI__))); -#endif - -#endif /* defined(__DOXYGEN__) */ - -/** \name Integer types capable of holding object pointers - These allow you to declare variables of the same size as a pointer. */ - -/*@{*/ - -/** \ingroup avr_stdint - Signed pointer compatible type. */ - -typedef int16_t intptr_t; - -/** \ingroup avr_stdint - Unsigned pointer compatible type. */ - -typedef uint16_t uintptr_t; - -/*@}*/ - -/** \name Minimum-width integer types - Integer types having at least the specified width */ - -/*@{*/ - -/** \ingroup avr_stdint - signed int with at least 8 bits. */ - -typedef int8_t int_least8_t; - -/** \ingroup avr_stdint - unsigned int with at least 8 bits. */ - -typedef uint8_t uint_least8_t; - -/** \ingroup avr_stdint - signed int with at least 16 bits. */ - -typedef int16_t int_least16_t; - -/** \ingroup avr_stdint - unsigned int with at least 16 bits. */ - -typedef uint16_t uint_least16_t; - -/** \ingroup avr_stdint - signed int with at least 32 bits. */ - -typedef int32_t int_least32_t; - -/** \ingroup avr_stdint - unsigned int with at least 32 bits. */ - -typedef uint32_t uint_least32_t; - -#if !__USING_MINT8 || defined(__DOXYGEN__) -/** \ingroup avr_stdint - signed int with at least 64 bits. - \note This type is not available when the compiler - option -mint8 is in effect. */ - -typedef int64_t int_least64_t; - -/** \ingroup avr_stdint - unsigned int with at least 64 bits. - \note This type is not available when the compiler - option -mint8 is in effect. */ - -typedef uint64_t uint_least64_t; -#endif - -/*@}*/ - - -/** \name Fastest minimum-width integer types - Integer types being usually fastest having at least the specified width */ - -/*@{*/ - -/** \ingroup avr_stdint - fastest signed int with at least 8 bits. */ - -typedef int8_t int_fast8_t; - -/** \ingroup avr_stdint - fastest unsigned int with at least 8 bits. */ - -typedef uint8_t uint_fast8_t; - -/** \ingroup avr_stdint - fastest signed int with at least 16 bits. */ - -typedef int16_t int_fast16_t; - -/** \ingroup avr_stdint - fastest unsigned int with at least 16 bits. */ - -typedef uint16_t uint_fast16_t; - -/** \ingroup avr_stdint - fastest signed int with at least 32 bits. */ - -typedef int32_t int_fast32_t; - -/** \ingroup avr_stdint - fastest unsigned int with at least 32 bits. */ - -typedef uint32_t uint_fast32_t; - -#if !__USING_MINT8 || defined(__DOXYGEN__) -/** \ingroup avr_stdint - fastest signed int with at least 64 bits. - \note This type is not available when the compiler - option -mint8 is in effect. */ - -typedef int64_t int_fast64_t; - -/** \ingroup avr_stdint - fastest unsigned int with at least 64 bits. - \note This type is not available when the compiler - option -mint8 is in effect. */ - -typedef uint64_t uint_fast64_t; -#endif - -/*@}*/ - - -/** \name Greatest-width integer types - Types designating integer data capable of representing any value of - any integer type in the corresponding signed or unsigned category */ - -/*@{*/ - -#if __USING_MINT8 -typedef int32_t intmax_t; - -typedef uint32_t uintmax_t; -#else /* !__USING_MINT8 */ -/** \ingroup avr_stdint - largest signed int available. */ - -typedef int64_t intmax_t; - -/** \ingroup avr_stdint - largest unsigned int available. */ - -typedef uint64_t uintmax_t; -#endif /* __USING_MINT8 */ - -/*@}*/ - -#ifndef __DOXYGEN__ -/* Helping macro */ -#ifndef __CONCAT -#define __CONCATenate(left, right) left ## right -#define __CONCAT(left, right) __CONCATenate(left, right) -#endif - -#endif /* !__DOXYGEN__ */ - -#if !defined(__cplusplus) || defined(__STDC_LIMIT_MACROS) - -/** \name Limits of specified-width integer types - C++ implementations should define these macros only when - __STDC_LIMIT_MACROS is defined before is included */ - -/*@{*/ - -/** \ingroup avr_stdint - largest positive value an int8_t can hold. */ - -#define INT8_MAX 0x7f - -/** \ingroup avr_stdint - smallest negative value an int8_t can hold. */ - -#define INT8_MIN (-INT8_MAX - 1) - -#if __USING_MINT8 - -#define UINT8_MAX (__CONCAT(INT8_MAX, U) * 2U + 1U) - -#define INT16_MAX 0x7fffL -#define INT16_MIN (-INT16_MAX - 1L) -#define UINT16_MAX (__CONCAT(INT16_MAX, U) * 2UL + 1UL) - -#define INT32_MAX 0x7fffffffLL -#define INT32_MIN (-INT32_MAX - 1LL) -#define UINT32_MAX (__CONCAT(INT32_MAX, U) * 2ULL + 1ULL) - -#else /* !__USING_MINT8 */ - -/** \ingroup avr_stdint - largest value an uint8_t can hold. */ - -#define UINT8_MAX (INT8_MAX * 2 + 1) - -/** \ingroup avr_stdint - largest positive value an int16_t can hold. */ - -#define INT16_MAX 0x7fff - -/** \ingroup avr_stdint - smallest negative value an int16_t can hold. */ - -#define INT16_MIN (-INT16_MAX - 1) - -/** \ingroup avr_stdint - largest value an uint16_t can hold. */ - -#define UINT16_MAX (__CONCAT(INT16_MAX, U) * 2U + 1U) - -/** \ingroup avr_stdint - largest positive value an int32_t can hold. */ - -#define INT32_MAX 0x7fffffffL - -/** \ingroup avr_stdint - smallest negative value an int32_t can hold. */ - -#define INT32_MIN (-INT32_MAX - 1L) - -/** \ingroup avr_stdint - largest value an uint32_t can hold. */ - -#define UINT32_MAX (__CONCAT(INT32_MAX, U) * 2UL + 1UL) - -#endif /* __USING_MINT8 */ - -/** \ingroup avr_stdint - largest positive value an int64_t can hold. */ - -#define INT64_MAX 0x7fffffffffffffffLL - -/** \ingroup avr_stdint - smallest negative value an int64_t can hold. */ - -#define INT64_MIN (-INT64_MAX - 1LL) - -/** \ingroup avr_stdint - largest value an uint64_t can hold. */ - -#define UINT64_MAX (__CONCAT(INT64_MAX, U) * 2ULL + 1ULL) - -/*@}*/ - -/** \name Limits of minimum-width integer types */ -/*@{*/ - -/** \ingroup avr_stdint - largest positive value an int_least8_t can hold. */ - -#define INT_LEAST8_MAX INT8_MAX - -/** \ingroup avr_stdint - smallest negative value an int_least8_t can hold. */ - -#define INT_LEAST8_MIN INT8_MIN - -/** \ingroup avr_stdint - largest value an uint_least8_t can hold. */ - -#define UINT_LEAST8_MAX UINT8_MAX - -/** \ingroup avr_stdint - largest positive value an int_least16_t can hold. */ - -#define INT_LEAST16_MAX INT16_MAX - -/** \ingroup avr_stdint - smallest negative value an int_least16_t can hold. */ - -#define INT_LEAST16_MIN INT16_MIN - -/** \ingroup avr_stdint - largest value an uint_least16_t can hold. */ - -#define UINT_LEAST16_MAX UINT16_MAX - -/** \ingroup avr_stdint - largest positive value an int_least32_t can hold. */ - -#define INT_LEAST32_MAX INT32_MAX - -/** \ingroup avr_stdint - smallest negative value an int_least32_t can hold. */ - -#define INT_LEAST32_MIN INT32_MIN - -/** \ingroup avr_stdint - largest value an uint_least32_t can hold. */ - -#define UINT_LEAST32_MAX UINT32_MAX - -/** \ingroup avr_stdint - largest positive value an int_least64_t can hold. */ - -#define INT_LEAST64_MAX INT64_MAX - -/** \ingroup avr_stdint - smallest negative value an int_least64_t can hold. */ - -#define INT_LEAST64_MIN INT64_MIN - -/** \ingroup avr_stdint - largest value an uint_least64_t can hold. */ - -#define UINT_LEAST64_MAX UINT64_MAX - -/*@}*/ - -/** \name Limits of fastest minimum-width integer types */ - -/*@{*/ - -/** \ingroup avr_stdint - largest positive value an int_fast8_t can hold. */ - -#define INT_FAST8_MAX INT8_MAX - -/** \ingroup avr_stdint - smallest negative value an int_fast8_t can hold. */ - -#define INT_FAST8_MIN INT8_MIN - -/** \ingroup avr_stdint - largest value an uint_fast8_t can hold. */ - -#define UINT_FAST8_MAX UINT8_MAX - -/** \ingroup avr_stdint - largest positive value an int_fast16_t can hold. */ - -#define INT_FAST16_MAX INT16_MAX - -/** \ingroup avr_stdint - smallest negative value an int_fast16_t can hold. */ - -#define INT_FAST16_MIN INT16_MIN - -/** \ingroup avr_stdint - largest value an uint_fast16_t can hold. */ - -#define UINT_FAST16_MAX UINT16_MAX - -/** \ingroup avr_stdint - largest positive value an int_fast32_t can hold. */ - -#define INT_FAST32_MAX INT32_MAX - -/** \ingroup avr_stdint - smallest negative value an int_fast32_t can hold. */ - -#define INT_FAST32_MIN INT32_MIN - -/** \ingroup avr_stdint - largest value an uint_fast32_t can hold. */ - -#define UINT_FAST32_MAX UINT32_MAX - -/** \ingroup avr_stdint - largest positive value an int_fast64_t can hold. */ - -#define INT_FAST64_MAX INT64_MAX - -/** \ingroup avr_stdint - smallest negative value an int_fast64_t can hold. */ - -#define INT_FAST64_MIN INT64_MIN - -/** \ingroup avr_stdint - largest value an uint_fast64_t can hold. */ - -#define UINT_FAST64_MAX UINT64_MAX - -/*@}*/ - -/** \name Limits of integer types capable of holding object pointers */ - -/*@{*/ - -/** \ingroup avr_stdint - largest positive value an intptr_t can hold. */ - -#define INTPTR_MAX INT16_MAX - -/** \ingroup avr_stdint - smallest negative value an intptr_t can hold. */ - -#define INTPTR_MIN INT16_MIN - -/** \ingroup avr_stdint - largest value an uintptr_t can hold. */ - -#define UINTPTR_MAX UINT16_MAX - -/*@}*/ - -/** \name Limits of greatest-width integer types */ - -/*@{*/ - -/** \ingroup avr_stdint - largest positive value an intmax_t can hold. */ - -#define INTMAX_MAX INT64_MAX - -/** \ingroup avr_stdint - smallest negative value an intmax_t can hold. */ - -#define INTMAX_MIN INT64_MIN - -/** \ingroup avr_stdint - largest value an uintmax_t can hold. */ - -#define UINTMAX_MAX UINT64_MAX - -/*@}*/ - -/** \name Limits of other integer types - C++ implementations should define these macros only when - __STDC_LIMIT_MACROS is defined before is included */ - -/*@{*/ - -/** \ingroup avr_stdint - largest positive value a ptrdiff_t can hold. */ - -#define PTRDIFF_MAX INT16_MAX - -/** \ingroup avr_stdint - smallest negative value a ptrdiff_t can hold. */ - -#define PTRDIFF_MIN INT16_MIN - - -/* Limits of sig_atomic_t */ -/* signal.h is currently not implemented (not avr/signal.h) */ - -/** \ingroup avr_stdint - largest positive value a sig_atomic_t can hold. */ - -#define SIG_ATOMIC_MAX INT8_MAX - -/** \ingroup avr_stdint - smallest negative value a sig_atomic_t can hold. */ - -#define SIG_ATOMIC_MIN INT8_MIN - - -/** \ingroup avr_stdint - largest value a size_t can hold. */ - -#define SIZE_MAX UINT16_MAX - - -/* Limits of wchar_t */ -/* wchar.h is currently not implemented */ -/* #define WCHAR_MAX */ -/* #define WCHAR_MIN */ - - -/* Limits of wint_t */ -/* wchar.h is currently not implemented */ -#ifndef WCHAR_MAX -#define WCHAR_MAX __WCHAR_MAX__ -#define WCHAR_MIN __WCHAR_MIN__ -#endif -#ifndef WINT_MAX -#define WINT_MAX __WINT_MAX__ -#define WINT_MIN __WINT_MIN__ -#endif - - -#endif /* !defined(__cplusplus) || defined(__STDC_LIMIT_MACROS) */ - -#if (!defined __cplusplus || __cplusplus >= 201103L \ - || defined __STDC_CONSTANT_MACROS) - -/** \name Macros for integer constants - C++ implementations should define these macros only when - __STDC_CONSTANT_MACROS is defined before is included. - - These definitions are valid for integer constants without suffix and - for macros defined as integer constant without suffix */ - -/* The GNU C preprocessor defines special macros in the implementation - namespace to allow a definition that works in #if expressions. */ -#ifdef __INT8_C -#define INT8_C(c) __INT8_C(c) -#define INT16_C(c) __INT16_C(c) -#define INT32_C(c) __INT32_C(c) -#define INT64_C(c) __INT64_C(c) -#define UINT8_C(c) __UINT8_C(c) -#define UINT16_C(c) __UINT16_C(c) -#define UINT32_C(c) __UINT32_C(c) -#define UINT64_C(c) __UINT64_C(c) -#define INTMAX_C(c) __INTMAX_C(c) -#define UINTMAX_C(c) __UINTMAX_C(c) -#else -/** \ingroup avr_stdint - define a constant of type int8_t */ - -#define INT8_C(value) ((int8_t) value) - -/** \ingroup avr_stdint - define a constant of type uint8_t */ - -#define UINT8_C(value) ((uint8_t) __CONCAT(value, U)) - -#if __USING_MINT8 - -#define INT16_C(value) __CONCAT(value, L) -#define UINT16_C(value) __CONCAT(value, UL) - -#define INT32_C(value) ((int32_t) __CONCAT(value, LL)) -#define UINT32_C(value) ((uint32_t) __CONCAT(value, ULL)) - -#else /* !__USING_MINT8 */ - -/** \ingroup avr_stdint - define a constant of type int16_t */ - -#define INT16_C(value) value - -/** \ingroup avr_stdint - define a constant of type uint16_t */ - -#define UINT16_C(value) __CONCAT(value, U) - -/** \ingroup avr_stdint - define a constant of type int32_t */ - -#define INT32_C(value) __CONCAT(value, L) - -/** \ingroup avr_stdint - define a constant of type uint32_t */ - -#define UINT32_C(value) __CONCAT(value, UL) - -#endif /* __USING_MINT8 */ - -/** \ingroup avr_stdint - define a constant of type int64_t */ - -#define INT64_C(value) __CONCAT(value, LL) - -/** \ingroup avr_stdint - define a constant of type uint64_t */ - -#define UINT64_C(value) __CONCAT(value, ULL) - -/** \ingroup avr_stdint - define a constant of type intmax_t */ - -#define INTMAX_C(value) __CONCAT(value, LL) - -/** \ingroup avr_stdint - define a constant of type uintmax_t */ - -#define UINTMAX_C(value) __CONCAT(value, ULL) - -#endif /* !__INT8_C */ - -/*@}*/ - -#endif /* (!defined __cplusplus || __cplusplus >= 201103L \ - || defined __STDC_CONSTANT_MACROS) */ - - -#endif /* _STDINT_H_ */ diff --git a/arduino/hardware/tools/avr/avr/include/stdio.h b/arduino/hardware/tools/avr/avr/include/stdio.h deleted file mode 100644 index 9c2c2f6..0000000 --- a/arduino/hardware/tools/avr/avr/include/stdio.h +++ /dev/null @@ -1,989 +0,0 @@ -/* Copyright (c) 2002, 2005, 2007 Joerg Wunsch - All rights reserved. - - Portions of documentation Copyright (c) 1990, 1991, 1993 - The Regents of the University of California. - - All rights reserved. - - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - * Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - * Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in - the documentation and/or other materials provided with the - distribution. - - * Neither the name of the copyright holders nor the names of - contributors may be used to endorse or promote products derived - from this software without specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - - $Id$ -*/ - -#ifndef _STDIO_H_ -#define _STDIO_H_ 1 - -#ifndef __ASSEMBLER__ - -#include -#include - -#ifndef __DOXYGEN__ -#define __need_NULL -#define __need_size_t -#include -#endif /* !__DOXYGEN__ */ - -/** \file */ -/** \defgroup avr_stdio : Standard IO facilities - \code #include \endcode - -

Introduction to the Standard IO facilities

- - This file declares the standard IO facilities that are implemented - in \c avr-libc. Due to the nature of the underlying hardware, - only a limited subset of standard IO is implemented. There is no - actual file implementation available, so only device IO can be - performed. Since there's no operating system, the application - needs to provide enough details about their devices in order to - make them usable by the standard IO facilities. - - Due to space constraints, some functionality has not been - implemented at all (like some of the \c printf conversions that - have been left out). Nevertheless, potential users of this - implementation should be warned: the \c printf and \c scanf families of functions, although - usually associated with presumably simple things like the - famous "Hello, world!" program, are actually fairly complex - which causes their inclusion to eat up a fair amount of code space. - Also, they are not fast due to the nature of interpreting the - format string at run-time. Whenever possible, resorting to the - (sometimes non-standard) predetermined conversion facilities that are - offered by avr-libc will usually cost much less in terms of speed - and code size. - -

Tunable options for code size vs. feature set

- - In order to allow programmers a code size vs. functionality tradeoff, - the function vfprintf() which is the heart of the printf family can be - selected in different flavours using linker options. See the - documentation of vfprintf() for a detailed description. The same - applies to vfscanf() and the \c scanf family of functions. - -

Outline of the chosen API

- - The standard streams \c stdin, \c stdout, and \c stderr are - provided, but contrary to the C standard, since avr-libc has no - knowledge about applicable devices, these streams are not already - pre-initialized at application startup. Also, since there is no - notion of "file" whatsoever to avr-libc, there is no function - \c fopen() that could be used to associate a stream to some device. - (See \ref stdio_note1 "note 1".) Instead, the function \c fdevopen() - is provided to associate a stream to a device, where the device - needs to provide a function to send a character, to receive a - character, or both. There is no differentiation between "text" and - "binary" streams inside avr-libc. Character \c \\n is sent - literally down to the device's \c put() function. If the device - requires a carriage return (\c \\r) character to be sent before - the linefeed, its \c put() routine must implement this (see - \ref stdio_note2 "note 2"). - - As an alternative method to fdevopen(), the macro - fdev_setup_stream() might be used to setup a user-supplied FILE - structure. - - It should be noted that the automatic conversion of a newline - character into a carriage return - newline sequence breaks binary - transfers. If binary transfers are desired, no automatic - conversion should be performed, but instead any string that aims - to issue a CR-LF sequence must use "\r\n" explicitly. - - For convenience, the first call to \c fdevopen() that opens a - stream for reading will cause the resulting stream to be aliased - to \c stdin. Likewise, the first call to \c fdevopen() that opens - a stream for writing will cause the resulting stream to be aliased - to both, \c stdout, and \c stderr. Thus, if the open was done - with both, read and write intent, all three standard streams will - be identical. Note that these aliases are indistinguishable from - each other, thus calling \c fclose() on such a stream will also - effectively close all of its aliases (\ref stdio_note3 "note 3"). - - It is possible to tie additional user data to a stream, using - fdev_set_udata(). The backend put and get functions can then - extract this user data using fdev_get_udata(), and act - appropriately. For example, a single put function could be used - to talk to two different UARTs that way, or the put and get - functions could keep internal state between calls there. - -

Format strings in flash ROM

- - All the \c printf and \c scanf family functions come in two flavours: the - standard name, where the format string is expected to be in - SRAM, as well as a version with the suffix "_P" where the format - string is expected to reside in the flash ROM. The macro - \c PSTR (explained in \ref avr_pgmspace) becomes very handy - for declaring these format strings. - - \anchor stdio_without_malloc -

Running stdio without malloc()

- - By default, fdevopen() requires malloc(). As this is often - not desired in the limited environment of a microcontroller, an - alternative option is provided to run completely without malloc(). - - The macro fdev_setup_stream() is provided to prepare a - user-supplied FILE buffer for operation with stdio. - -

Example

- - \code - #include - - static int uart_putchar(char c, FILE *stream); - - static FILE mystdout = FDEV_SETUP_STREAM(uart_putchar, NULL, - _FDEV_SETUP_WRITE); - - static int - uart_putchar(char c, FILE *stream) - { - - if (c == '\n') - uart_putchar('\r', stream); - loop_until_bit_is_set(UCSRA, UDRE); - UDR = c; - return 0; - } - - int - main(void) - { - init_uart(); - stdout = &mystdout; - printf("Hello, world!\n"); - - return 0; - } - \endcode - - This example uses the initializer form FDEV_SETUP_STREAM() rather - than the function-like fdev_setup_stream(), so all data - initialization happens during C start-up. - - If streams initialized that way are no longer needed, they can be - destroyed by first calling the macro fdev_close(), and then - destroying the object itself. No call to fclose() should be - issued for these streams. While calling fclose() itself is - harmless, it will cause an undefined reference to free() and thus - cause the linker to link the malloc module into the application. - -

Notes

- - \anchor stdio_note1 \par Note 1: - It might have been possible to implement a device abstraction that - is compatible with \c fopen() but since this would have required - to parse a string, and to take all the information needed either - out of this string, or out of an additional table that would need to be - provided by the application, this approach was not taken. - - \anchor stdio_note2 \par Note 2: - This basically follows the Unix approach: if a device such as a - terminal needs special handling, it is in the domain of the - terminal device driver to provide this functionality. Thus, a - simple function suitable as \c put() for \c fdevopen() that talks - to a UART interface might look like this: - - \code - int - uart_putchar(char c, FILE *stream) - { - - if (c == '\n') - uart_putchar('\r'); - loop_until_bit_is_set(UCSRA, UDRE); - UDR = c; - return 0; - } - \endcode - - \anchor stdio_note3 \par Note 3: - This implementation has been chosen because the cost of maintaining - an alias is considerably smaller than the cost of maintaining full - copies of each stream. Yet, providing an implementation that offers - the complete set of standard streams was deemed to be useful. Not - only that writing \c printf() instead of fprintf(mystream, ...) - saves typing work, but since avr-gcc needs to resort to pass all - arguments of variadic functions on the stack (as opposed to passing - them in registers for functions that take a fixed number of - parameters), the ability to pass one parameter less by implying - \c stdin or stdout will also save some execution time. -*/ - -#if !defined(__DOXYGEN__) - -/* - * This is an internal structure of the library that is subject to be - * changed without warnings at any time. Please do *never* reference - * elements of it beyond by using the official interfaces provided. - */ -struct __file { - char *buf; /* buffer pointer */ - unsigned char unget; /* ungetc() buffer */ - uint8_t flags; /* flags, see below */ -#define __SRD 0x0001 /* OK to read */ -#define __SWR 0x0002 /* OK to write */ -#define __SSTR 0x0004 /* this is an sprintf/snprintf string */ -#define __SPGM 0x0008 /* fmt string is in progmem */ -#define __SERR 0x0010 /* found error */ -#define __SEOF 0x0020 /* found EOF */ -#define __SUNGET 0x040 /* ungetc() happened */ -#define __SMALLOC 0x80 /* handle is malloc()ed */ -#if 0 -/* possible future extensions, will require uint16_t flags */ -#define __SRW 0x0100 /* open for reading & writing */ -#define __SLBF 0x0200 /* line buffered */ -#define __SNBF 0x0400 /* unbuffered */ -#define __SMBF 0x0800 /* buf is from malloc */ -#endif - int size; /* size of buffer */ - int len; /* characters read or written so far */ - int (*put)(char, struct __file *); /* function to write one char to device */ - int (*get)(struct __file *); /* function to read one char from device */ - void *udata; /* User defined and accessible data. */ -}; - -#endif /* not __DOXYGEN__ */ - -/*@{*/ -/** - \c FILE is the opaque structure that is passed around between the - various standard IO functions. -*/ -typedef struct __file FILE; - -/** - Stream that will be used as an input stream by the simplified - functions that don't take a \c stream argument. - - The first stream opened with read intent using \c fdevopen() - will be assigned to \c stdin. -*/ -#define stdin (__iob[0]) - -/** - Stream that will be used as an output stream by the simplified - functions that don't take a \c stream argument. - - The first stream opened with write intent using \c fdevopen() - will be assigned to both, \c stdin, and \c stderr. -*/ -#define stdout (__iob[1]) - -/** - Stream destined for error output. Unless specifically assigned, - identical to \c stdout. - - If \c stderr should point to another stream, the result of - another \c fdevopen() must be explicitly assigned to it without - closing the previous \c stderr (since this would also close - \c stdout). -*/ -#define stderr (__iob[2]) - -/** - \c EOF declares the value that is returned by various standard IO - functions in case of an error. Since the AVR platform (currently) - doesn't contain an abstraction for actual files, its origin as - "end of file" is somewhat meaningless here. -*/ -#define EOF (-1) - -/** This macro inserts a pointer to user defined data into a FILE - stream object. - - The user data can be useful for tracking state in the put and get - functions supplied to the fdevopen() function. */ -#define fdev_set_udata(stream, u) do { (stream)->udata = u; } while(0) - -/** This macro retrieves a pointer to user defined data from a FILE - stream object. */ -#define fdev_get_udata(stream) ((stream)->udata) - -#if defined(__DOXYGEN__) -/** - \brief Setup a user-supplied buffer as an stdio stream - - This macro takes a user-supplied buffer \c stream, and sets it up - as a stream that is valid for stdio operations, similar to one that - has been obtained dynamically from fdevopen(). The buffer to setup - must be of type FILE. - - The arguments \c put and \c get are identical to those that need to - be passed to fdevopen(). - - The \c rwflag argument can take one of the values _FDEV_SETUP_READ, - _FDEV_SETUP_WRITE, or _FDEV_SETUP_RW, for read, write, or read/write - intent, respectively. - - \note No assignments to the standard streams will be performed by - fdev_setup_stream(). If standard streams are to be used, these - need to be assigned by the user. See also under - \ref stdio_without_malloc "Running stdio without malloc()". - */ -#define fdev_setup_stream(stream, put, get, rwflag) -#else /* !DOXYGEN */ -#define fdev_setup_stream(stream, p, g, f) \ - do { \ - (stream)->put = p; \ - (stream)->get = g; \ - (stream)->flags = f; \ - (stream)->udata = 0; \ - } while(0) -#endif /* DOXYGEN */ - -#define _FDEV_SETUP_READ __SRD /**< fdev_setup_stream() with read intent */ -#define _FDEV_SETUP_WRITE __SWR /**< fdev_setup_stream() with write intent */ -#define _FDEV_SETUP_RW (__SRD|__SWR) /**< fdev_setup_stream() with read/write intent */ - -/** - * Return code for an error condition during device read. - * - * To be used in the get function of fdevopen(). - */ -#define _FDEV_ERR (-1) - -/** - * Return code for an end-of-file condition during device read. - * - * To be used in the get function of fdevopen(). - */ -#define _FDEV_EOF (-2) - -#if defined(__DOXYGEN__) -/** - \brief Initializer for a user-supplied stdio stream - - This macro acts similar to fdev_setup_stream(), but it is to be - used as the initializer of a variable of type FILE. - - The remaining arguments are to be used as explained in - fdev_setup_stream(). - */ -#define FDEV_SETUP_STREAM(put, get, rwflag) -#else /* !DOXYGEN */ -#define FDEV_SETUP_STREAM(p, g, f) \ - { \ - .put = p, \ - .get = g, \ - .flags = f, \ - .udata = 0, \ - } -#endif /* DOXYGEN */ - -#ifdef __cplusplus -extern "C" { -#endif - -#if !defined(__DOXYGEN__) -/* - * Doxygen documentation can be found in fdevopen.c. - */ - -extern struct __file *__iob[]; - -#if defined(__STDIO_FDEVOPEN_COMPAT_12) -/* - * Declare prototype for the discontinued version of fdevopen() that - * has been in use up to avr-libc 1.2.x. The new implementation has - * some backwards compatibility with the old version. - */ -extern FILE *fdevopen(int (*__put)(char), int (*__get)(void), - int __opts __attribute__((unused))); -#else /* !defined(__STDIO_FDEVOPEN_COMPAT_12) */ -/* New prototype for avr-libc 1.4 and above. */ -extern FILE *fdevopen(int (*__put)(char, FILE*), int (*__get)(FILE*)); -#endif /* defined(__STDIO_FDEVOPEN_COMPAT_12) */ - -#endif /* not __DOXYGEN__ */ - -/** - This function closes \c stream, and disallows and further - IO to and from it. - - When using fdevopen() to setup the stream, a call to fclose() is - needed in order to free the internal resources allocated. - - If the stream has been set up using fdev_setup_stream() or - FDEV_SETUP_STREAM(), use fdev_close() instead. - - It currently always returns 0 (for success). -*/ -extern int fclose(FILE *__stream); - -/** - This macro frees up any library resources that might be associated - with \c stream. It should be called if \c stream is no longer - needed, right before the application is going to destroy the - \c stream object itself. - - (Currently, this macro evaluates to nothing, but this might change - in future versions of the library.) -*/ -#if defined(__DOXYGEN__) -# define fdev_close() -#else -# define fdev_close() ((void)0) -#endif - -/** - \c vfprintf is the central facility of the \c printf family of - functions. It outputs values to \c stream under control of a - format string passed in \c fmt. The actual values to print are - passed as a variable argument list \c ap. - - \c vfprintf returns the number of characters written to \c stream, - or \c EOF in case of an error. Currently, this will only happen - if \c stream has not been opened with write intent. - - The format string is composed of zero or more directives: ordinary - characters (not \c %), which are copied unchanged to the output - stream; and conversion specifications, each of which results in - fetching zero or more subsequent arguments. Each conversion - specification is introduced by the \c % character. The arguments must - properly correspond (after type promotion) with the conversion - specifier. After the \c %, the following appear in sequence: - - - Zero or more of the following flags: -
    -
  • \c # The value should be converted to an "alternate form". For - c, d, i, s, and u conversions, this option has no effect. - For o conversions, the precision of the number is - increased to force the first character of the output - string to a zero (except if a zero value is printed with - an explicit precision of zero). For x and X conversions, - a non-zero result has the string `0x' (or `0X' for X - conversions) prepended to it.
    • -
  • \c 0 (zero) Zero padding. For all conversions, the converted - value is padded on the left with zeros rather than blanks. - If a precision is given with a numeric conversion (d, i, - o, u, i, x, and X), the 0 flag is ignored.
    • -
  • \c - A negative field width flag; the converted value is to be - left adjusted on the field boundary. The converted value - is padded on the right with blanks, rather than on the - left with blanks or zeros. A - overrides a 0 if both are - given.
    • -
  • ' ' (space) A blank should be left before a positive number - produced by a signed conversion (d, or i).
    • -
  • \c + A sign must always be placed before a number produced by a - signed conversion. A + overrides a space if both are - used.
    • -
- - - An optional decimal digit string specifying a minimum field width. - If the converted value has fewer characters than the field width, it - will be padded with spaces on the left (or right, if the left-adjustment - flag has been given) to fill out the field width. - - An optional precision, in the form of a period . followed by an - optional digit string. If the digit string is omitted, the - precision is taken as zero. This gives the minimum number of - digits to appear for d, i, o, u, x, and X conversions, or the - maximum number of characters to be printed from a string for \c s - conversions. - - An optional \c l or \c h length modifier, that specifies that the - argument for the d, i, o, u, x, or X conversion is a \c "long int" - rather than \c int. The \c h is ignored, as \c "short int" is - equivalent to \c int. - - A character that specifies the type of conversion to be applied. - - The conversion specifiers and their meanings are: - - - \c diouxX The int (or appropriate variant) argument is converted - to signed decimal (d and i), unsigned octal (o), unsigned - decimal (u), or unsigned hexadecimal (x and X) notation. - The letters "abcdef" are used for x conversions; the - letters "ABCDEF" are used for X conversions. The - precision, if any, gives the minimum number of digits that - must appear; if the converted value requires fewer digits, - it is padded on the left with zeros. - - \c p The void * argument is taken as an unsigned integer, - and converted similarly as a %\#x command would do. - - \c c The \c int argument is converted to an \c "unsigned char", and the - resulting character is written. - - \c s The \c "char *" argument is expected to be a pointer to an array - of character type (pointer to a string). Characters from - the array are written up to (but not including) a - terminating NUL character; if a precision is specified, no - more than the number specified are written. If a precision - is given, no null character need be present; if the - precision is not specified, or is greater than the size of - the array, the array must contain a terminating NUL - character. - - \c % A \c % is written. No argument is converted. The complete - conversion specification is "%%". - - \c eE The double argument is rounded and converted in the format - \c "[-]d.ddde±dd" where there is one digit before the - decimal-point character and the number of digits after it - is equal to the precision; if the precision is missing, it - is taken as 6; if the precision is zero, no decimal-point - character appears. An \e E conversion uses the letter \c 'E' - (rather than \c 'e') to introduce the exponent. The exponent - always contains two digits; if the value is zero, - the exponent is 00. - - \c fF The double argument is rounded and converted to decimal notation - in the format \c "[-]ddd.ddd", where the number of digits after the - decimal-point character is equal to the precision specification. - If the precision is missing, it is taken as 6; if the precision - is explicitly zero, no decimal-point character appears. If a - decimal point appears, at least one digit appears before it. - - \c gG The double argument is converted in style \c f or \c e (or - \c F or \c E for \c G conversions). The precision - specifies the number of significant digits. If the - precision is missing, 6 digits are given; if the precision - is zero, it is treated as 1. Style \c e is used if the - exponent from its conversion is less than -4 or greater - than or equal to the precision. Trailing zeros are removed - from the fractional part of the result; a decimal point - appears only if it is followed by at least one digit. - - \c S Similar to the \c s format, except the pointer is expected to - point to a program-memory (ROM) string instead of a RAM string. - - In no case does a non-existent or small field width cause truncation of a - numeric field; if the result of a conversion is wider than the field - width, the field is expanded to contain the conversion result. - - Since the full implementation of all the mentioned features becomes - fairly large, three different flavours of vfprintf() can be - selected using linker options. The default vfprintf() implements - all the mentioned functionality except floating point conversions. - A minimized version of vfprintf() is available that only implements - the very basic integer and string conversion facilities, but only - the \c # additional option can be specified using conversion - flags (these flags are parsed correctly from the format - specification, but then simply ignored). This version can be - requested using the following \ref gcc_minusW "compiler options": - - \code - -Wl,-u,vfprintf -lprintf_min - \endcode - - If the full functionality including the floating point conversions - is required, the following options should be used: - - \code - -Wl,-u,vfprintf -lprintf_flt -lm - \endcode - - \par Limitations: - - The specified width and precision can be at most 255. - - \par Notes: - - For floating-point conversions, if you link default or minimized - version of vfprintf(), the symbol \c ? will be output and double - argument will be skiped. So you output below will not be crashed. - For default version the width field and the "pad to left" ( symbol - minus ) option will work in this case. - - The \c hh length modifier is ignored (\c char argument is - promouted to \c int). More exactly, this realization does not check - the number of \c h symbols. - - But the \c ll length modifier will to abort the output, as this - realization does not operate \c long \c long arguments. - - The variable width or precision field (an asterisk \c * symbol) - is not realized and will to abort the output. - - */ - -extern int vfprintf(FILE *__stream, const char *__fmt, va_list __ap); - -/** - Variant of \c vfprintf() that uses a \c fmt string that resides - in program memory. -*/ -extern int vfprintf_P(FILE *__stream, const char *__fmt, va_list __ap); - -/** - The function \c fputc sends the character \c c (though given as type - \c int) to \c stream. It returns the character, or \c EOF in case - an error occurred. -*/ -extern int fputc(int __c, FILE *__stream); - -#if !defined(__DOXYGEN__) - -/* putc() function implementation, required by standard */ -extern int putc(int __c, FILE *__stream); - -/* putchar() function implementation, required by standard */ -extern int putchar(int __c); - -#endif /* not __DOXYGEN__ */ - -/** - The macro \c putc used to be a "fast" macro implementation with a - functionality identical to fputc(). For space constraints, in - \c avr-libc, it is just an alias for \c fputc. -*/ -#define putc(__c, __stream) fputc(__c, __stream) - -/** - The macro \c putchar sends character \c c to \c stdout. -*/ -#define putchar(__c) fputc(__c, stdout) - -/** - The function \c printf performs formatted output to stream - \c stdout. See \c vfprintf() for details. -*/ -extern int printf(const char *__fmt, ...); - -/** - Variant of \c printf() that uses a \c fmt string that resides - in program memory. -*/ -extern int printf_P(const char *__fmt, ...); - -/** - The function \c vprintf performs formatted output to stream - \c stdout, taking a variable argument list as in vfprintf(). - - See vfprintf() for details. -*/ -extern int vprintf(const char *__fmt, va_list __ap); - -/** - Variant of \c printf() that sends the formatted characters - to string \c s. -*/ -extern int sprintf(char *__s, const char *__fmt, ...); - -/** - Variant of \c sprintf() that uses a \c fmt string that resides - in program memory. -*/ -extern int sprintf_P(char *__s, const char *__fmt, ...); - -/** - Like \c sprintf(), but instead of assuming \c s to be of infinite - size, no more than \c n characters (including the trailing NUL - character) will be converted to \c s. - - Returns the number of characters that would have been written to - \c s if there were enough space. -*/ -extern int snprintf(char *__s, size_t __n, const char *__fmt, ...); - -/** - Variant of \c snprintf() that uses a \c fmt string that resides - in program memory. -*/ -extern int snprintf_P(char *__s, size_t __n, const char *__fmt, ...); - -/** - Like \c sprintf() but takes a variable argument list for the - arguments. -*/ -extern int vsprintf(char *__s, const char *__fmt, va_list ap); - -/** - Variant of \c vsprintf() that uses a \c fmt string that resides - in program memory. -*/ -extern int vsprintf_P(char *__s, const char *__fmt, va_list ap); - -/** - Like \c vsprintf(), but instead of assuming \c s to be of infinite - size, no more than \c n characters (including the trailing NUL - character) will be converted to \c s. - - Returns the number of characters that would have been written to - \c s if there were enough space. -*/ -extern int vsnprintf(char *__s, size_t __n, const char *__fmt, va_list ap); - -/** - Variant of \c vsnprintf() that uses a \c fmt string that resides - in program memory. -*/ -extern int vsnprintf_P(char *__s, size_t __n, const char *__fmt, va_list ap); -/** - The function \c fprintf performs formatted output to \c stream. - See \c vfprintf() for details. -*/ -extern int fprintf(FILE *__stream, const char *__fmt, ...); - -/** - Variant of \c fprintf() that uses a \c fmt string that resides - in program memory. -*/ -extern int fprintf_P(FILE *__stream, const char *__fmt, ...); - -/** - Write the string pointed to by \c str to stream \c stream. - - Returns 0 on success and EOF on error. -*/ -extern int fputs(const char *__str, FILE *__stream); - -/** - Variant of fputs() where \c str resides in program memory. -*/ -extern int fputs_P(const char *__str, FILE *__stream); - -/** - Write the string pointed to by \c str, and a trailing newline - character, to \c stdout. -*/ -extern int puts(const char *__str); - -/** - Variant of puts() where \c str resides in program memory. -*/ -extern int puts_P(const char *__str); - -/** - Write \c nmemb objects, \c size bytes each, to \c stream. - The first byte of the first object is referenced by \c ptr. - - Returns the number of objects successfully written, i. e. - \c nmemb unless an output error occured. - */ -extern size_t fwrite(const void *__ptr, size_t __size, size_t __nmemb, - FILE *__stream); - -/** - The function \c fgetc reads a character from \c stream. It returns - the character, or \c EOF in case end-of-file was encountered or an - error occurred. The routines feof() or ferror() must be used to - distinguish between both situations. -*/ -extern int fgetc(FILE *__stream); - -#if !defined(__DOXYGEN__) - -/* getc() function implementation, required by standard */ -extern int getc(FILE *__stream); - -/* getchar() function implementation, required by standard */ -extern int getchar(void); - -#endif /* not __DOXYGEN__ */ - -/** - The macro \c getc used to be a "fast" macro implementation with a - functionality identical to fgetc(). For space constraints, in - \c avr-libc, it is just an alias for \c fgetc. -*/ -#define getc(__stream) fgetc(__stream) - -/** - The macro \c getchar reads a character from \c stdin. Return - values and error handling is identical to fgetc(). -*/ -#define getchar() fgetc(stdin) - -/** - The ungetc() function pushes the character \c c (converted to an - unsigned char) back onto the input stream pointed to by \c stream. - The pushed-back character will be returned by a subsequent read on - the stream. - - Currently, only a single character can be pushed back onto the - stream. - - The ungetc() function returns the character pushed back after the - conversion, or \c EOF if the operation fails. If the value of the - argument \c c character equals \c EOF, the operation will fail and - the stream will remain unchanged. -*/ -extern int ungetc(int __c, FILE *__stream); - -/** - Read at most size - 1 bytes from \c stream, until a - newline character was encountered, and store the characters in the - buffer pointed to by \c str. Unless an error was encountered while - reading, the string will then be terminated with a \c NUL - character. - - If an error was encountered, the function returns NULL and sets the - error flag of \c stream, which can be tested using ferror(). - Otherwise, a pointer to the string will be returned. */ -extern char *fgets(char *__str, int __size, FILE *__stream); - -/** - Similar to fgets() except that it will operate on stream \c stdin, - and the trailing newline (if any) will not be stored in the string. - It is the caller's responsibility to provide enough storage to hold - the characters read. */ -extern char *gets(char *__str); - -/** - Read \c nmemb objects, \c size bytes each, from \c stream, - to the buffer pointed to by \c ptr. - - Returns the number of objects successfully read, i. e. - \c nmemb unless an input error occured or end-of-file was - encountered. feof() and ferror() must be used to distinguish - between these two conditions. - */ -extern size_t fread(void *__ptr, size_t __size, size_t __nmemb, - FILE *__stream); - -/** - Clear the error and end-of-file flags of \c stream. - */ -extern void clearerr(FILE *__stream); - -#if !defined(__DOXYGEN__) -/* fast inlined version of clearerr() */ -#define clearerror(s) do { (s)->flags &= ~(__SERR | __SEOF); } while(0) -#endif /* !defined(__DOXYGEN__) */ - -/** - Test the end-of-file flag of \c stream. This flag can only be cleared - by a call to clearerr(). - */ -extern int feof(FILE *__stream); - -#if !defined(__DOXYGEN__) -/* fast inlined version of feof() */ -#define feof(s) ((s)->flags & __SEOF) -#endif /* !defined(__DOXYGEN__) */ - -/** - Test the error flag of \c stream. This flag can only be cleared - by a call to clearerr(). - */ -extern int ferror(FILE *__stream); - -#if !defined(__DOXYGEN__) -/* fast inlined version of ferror() */ -#define ferror(s) ((s)->flags & __SERR) -#endif /* !defined(__DOXYGEN__) */ - -extern int vfscanf(FILE *__stream, const char *__fmt, va_list __ap); - -/** - Variant of vfscanf() using a \c fmt string in program memory. - */ -extern int vfscanf_P(FILE *__stream, const char *__fmt, va_list __ap); - -/** - The function \c fscanf performs formatted input, reading the - input data from \c stream. - - See vfscanf() for details. - */ -extern int fscanf(FILE *__stream, const char *__fmt, ...); - -/** - Variant of fscanf() using a \c fmt string in program memory. - */ -extern int fscanf_P(FILE *__stream, const char *__fmt, ...); - -/** - The function \c scanf performs formatted input from stream \c stdin. - - See vfscanf() for details. - */ -extern int scanf(const char *__fmt, ...); - -/** - Variant of scanf() where \c fmt resides in program memory. - */ -extern int scanf_P(const char *__fmt, ...); - -/** - The function \c vscanf performs formatted input from stream - \c stdin, taking a variable argument list as in vfscanf(). - - See vfscanf() for details. -*/ -extern int vscanf(const char *__fmt, va_list __ap); - -/** - The function \c sscanf performs formatted input, reading the - input data from the buffer pointed to by \c buf. - - See vfscanf() for details. - */ -extern int sscanf(const char *__buf, const char *__fmt, ...); - -/** - Variant of sscanf() using a \c fmt string in program memory. - */ -extern int sscanf_P(const char *__buf, const char *__fmt, ...); - -#if defined(__DOXYGEN__) -/** - Flush \c stream. - - This is a null operation provided for source-code compatibility - only, as the standard IO implementation currently does not perform - any buffering. - */ -extern int fflush(FILE *stream); -#else -static __inline__ int fflush(FILE *stream __attribute__((unused))) -{ - return 0; -} -#endif - -#ifndef __DOXYGEN__ -/* only mentioned for libstdc++ support, not implemented in library */ -#define BUFSIZ 1024 -#define _IONBF 0 -__extension__ typedef long long fpos_t; -extern int fgetpos(FILE *stream, fpos_t *pos); -extern FILE *fopen(const char *path, const char *mode); -extern FILE *freopen(const char *path, const char *mode, FILE *stream); -extern FILE *fdopen(int, const char *); -extern int fseek(FILE *stream, long offset, int whence); -extern int fsetpos(FILE *stream, fpos_t *pos); -extern long ftell(FILE *stream); -extern int fileno(FILE *); -extern void perror(const char *s); -extern int remove(const char *pathname); -extern int rename(const char *oldpath, const char *newpath); -extern void rewind(FILE *stream); -extern void setbuf(FILE *stream, char *buf); -extern int setvbuf(FILE *stream, char *buf, int mode, size_t size); -extern FILE *tmpfile(void); -extern char *tmpnam (char *s); -#endif /* !__DOXYGEN__ */ - -#ifdef __cplusplus -} -#endif - -/*@}*/ - -#ifndef __DOXYGEN__ -/* - * The following constants are currently not used by avr-libc's - * stdio subsystem. They are defined here since the gcc build - * environment expects them to be here. - */ -#define SEEK_SET 0 -#define SEEK_CUR 1 -#define SEEK_END 2 - -#endif - -#endif /* __ASSEMBLER */ - -#endif /* _STDLIB_H_ */ diff --git a/arduino/hardware/tools/avr/avr/include/stdlib.h b/arduino/hardware/tools/avr/avr/include/stdlib.h deleted file mode 100644 index a77f7b3..0000000 --- a/arduino/hardware/tools/avr/avr/include/stdlib.h +++ /dev/null @@ -1,696 +0,0 @@ -/* Copyright (c) 2002, Marek Michalkiewicz - Copyright (c) 2004,2007 Joerg Wunsch - - Portions of documentation Copyright (c) 1990, 1991, 1993, 1994 - The Regents of the University of California. - - All rights reserved. - - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - * Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - * Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in - the documentation and/or other materials provided with the - distribution. - - * Neither the name of the copyright holders nor the names of - contributors may be used to endorse or promote products derived - from this software without specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - - $Id$ -*/ - -#ifndef _STDLIB_H_ -#define _STDLIB_H_ 1 - -#ifndef __ASSEMBLER__ - -#ifndef __DOXYGEN__ -#define __need_NULL -#define __need_size_t -#define __need_wchar_t -#include - -#ifndef __ptr_t -#define __ptr_t void * -#endif -#endif /* !__DOXYGEN__ */ - -#ifdef __cplusplus -extern "C" { -#endif - -/** \file */ - -/** \defgroup avr_stdlib : General utilities - \code #include \endcode - - This file declares some basic C macros and functions as - defined by the ISO standard, plus some AVR-specific extensions. -*/ - -/*@{*/ -/** Result type for function div(). */ -typedef struct { - int quot; /**< The Quotient. */ - int rem; /**< The Remainder. */ -} div_t; - -/** Result type for function ldiv(). */ -typedef struct { - long quot; /**< The Quotient. */ - long rem; /**< The Remainder. */ -} ldiv_t; - -/** Comparision function type for qsort(), just for convenience. */ -typedef int (*__compar_fn_t)(const void *, const void *); - -#ifndef __DOXYGEN__ - -#ifndef __ATTR_CONST__ -# define __ATTR_CONST__ __attribute__((__const__)) -#endif - -#ifndef __ATTR_MALLOC__ -# define __ATTR_MALLOC__ __attribute__((__malloc__)) -#endif - -#ifndef __ATTR_NORETURN__ -# define __ATTR_NORETURN__ __attribute__((__noreturn__)) -#endif - -#ifndef __ATTR_PURE__ -# define __ATTR_PURE__ __attribute__((__pure__)) -#endif - -#ifndef __ATTR_GNU_INLINE__ -# ifdef __GNUC_STDC_INLINE__ -# define __ATTR_GNU_INLINE__ __attribute__((__gnu_inline__)) -# else -# define __ATTR_GNU_INLINE__ -# endif -#endif - -#endif - -/** The abort() function causes abnormal program termination to occur. - This realization disables interrupts and jumps to _exit() function - with argument equal to 1. In the limited AVR environment, execution is - effectively halted by entering an infinite loop. */ -extern void abort(void) __ATTR_NORETURN__; - -/** The abs() function computes the absolute value of the integer \c i. - \note The abs() and labs() functions are builtins of gcc. -*/ -extern int abs(int __i) __ATTR_CONST__; -#ifndef __DOXYGEN__ -#define abs(__i) __builtin_abs(__i) -#endif - -/** The labs() function computes the absolute value of the long integer - \c i. - \note The abs() and labs() functions are builtins of gcc. -*/ -extern long labs(long __i) __ATTR_CONST__; -#ifndef __DOXYGEN__ -#define labs(__i) __builtin_labs(__i) -#endif - -/** - The bsearch() function searches an array of \c nmemb objects, the - initial member of which is pointed to by \c base, for a member - that matches the object pointed to by \c key. The size of each - member of the array is specified by \c size. - - The contents of the array should be in ascending sorted order - according to the comparison function referenced by \c compar. - The \c compar routine is expected to have two arguments which - point to the key object and to an array member, in that order, - and should return an integer less than, equal to, or greater than - zero if the key object is found, respectively, to be less than, - to match, or be greater than the array member. - - The bsearch() function returns a pointer to a matching member of - the array, or a null pointer if no match is found. If two - members compare as equal, which member is matched is unspecified. -*/ -extern void *bsearch(const void *__key, const void *__base, size_t __nmemb, - size_t __size, int (*__compar)(const void *, const void *)); - -/* __divmodhi4 and __divmodsi4 from libgcc.a */ -/** - The div() function computes the value \c num/denom and returns - the quotient and remainder in a structure named \c div_t that - contains two int members named \c quot and \c rem. -*/ -extern div_t div(int __num, int __denom) __asm__("__divmodhi4") __ATTR_CONST__; -/** - The ldiv() function computes the value \c num/denom and returns - the quotient and remainder in a structure named \c ldiv_t that - contains two long integer members named \c quot and \c rem. -*/ -extern ldiv_t ldiv(long __num, long __denom) __asm__("__divmodsi4") __ATTR_CONST__; - -/** - The qsort() function is a modified partition-exchange sort, or - quicksort. - - The qsort() function sorts an array of \c nmemb objects, the - initial member of which is pointed to by \c base. The size of - each object is specified by \c size. The contents of the array - base are sorted in ascending order according to a comparison - function pointed to by \c compar, which requires two arguments - pointing to the objects being compared. - - The comparison function must return an integer less than, equal - to, or greater than zero if the first argument is considered to - be respectively less than, equal to, or greater than the second. -*/ -extern void qsort(void *__base, size_t __nmemb, size_t __size, - __compar_fn_t __compar); - -/** - The strtol() function converts the string in \c nptr to a long - value. The conversion is done according to the given base, which - must be between 2 and 36 inclusive, or be the special value 0. - - The string may begin with an arbitrary amount of white space (as - determined by isspace()) followed by a single optional \c '+' or \c '-' - sign. If \c base is zero or 16, the string may then include a - \c "0x" prefix, and the number will be read in base 16; otherwise, - a zero base is taken as 10 (decimal) unless the next character is - \c '0', in which case it is taken as 8 (octal). - - The remainder of the string is converted to a long value in the - obvious manner, stopping at the first character which is not a - valid digit in the given base. (In bases above 10, the letter \c 'A' - in either upper or lower case represents 10, \c 'B' represents 11, - and so forth, with \c 'Z' representing 35.) - - If \c endptr is not NULL, strtol() stores the address of the first - invalid character in \c *endptr. If there were no digits at all, - however, strtol() stores the original value of \c nptr in \c - *endptr. (Thus, if \c *nptr is not \c '\\0' but \c **endptr is \c '\\0' - on return, the entire string was valid.) - - The strtol() function returns the result of the conversion, unless - the value would underflow or overflow. If no conversion could be - performed, 0 is returned. If an overflow or underflow occurs, \c - errno is set to \ref avr_errno "ERANGE" and the function return value - is clamped to \c LONG_MIN or \c LONG_MAX, respectively. -*/ -extern long strtol(const char *__nptr, char **__endptr, int __base); - -/** - The strtoul() function converts the string in \c nptr to an - unsigned long value. The conversion is done according to the - given base, which must be between 2 and 36 inclusive, or be the - special value 0. - - The string may begin with an arbitrary amount of white space (as - determined by isspace()) followed by a single optional \c '+' or \c '-' - sign. If \c base is zero or 16, the string may then include a - \c "0x" prefix, and the number will be read in base 16; otherwise, - a zero base is taken as 10 (decimal) unless the next character is - \c '0', in which case it is taken as 8 (octal). - - The remainder of the string is converted to an unsigned long value - in the obvious manner, stopping at the first character which is - not a valid digit in the given base. (In bases above 10, the - letter \c 'A' in either upper or lower case represents 10, \c 'B' - represents 11, and so forth, with \c 'Z' representing 35.) - - If \c endptr is not NULL, strtoul() stores the address of the first - invalid character in \c *endptr. If there were no digits at all, - however, strtoul() stores the original value of \c nptr in \c - *endptr. (Thus, if \c *nptr is not \c '\\0' but \c **endptr is \c '\\0' - on return, the entire string was valid.) - - The strtoul() function return either the result of the conversion - or, if there was a leading minus sign, the negation of the result - of the conversion, unless the original (non-negated) value would - overflow; in the latter case, strtoul() returns ULONG_MAX, and \c - errno is set to \ref avr_errno "ERANGE". If no conversion could - be performed, 0 is returned. -*/ -extern unsigned long strtoul(const char *__nptr, char **__endptr, int __base); - -/** - The atol() function converts the initial portion of the string - pointed to by \p s to long integer representation. In contrast to - - \code strtol(s, (char **)NULL, 10); \endcode - - this function does not detect overflow (\c errno is not changed and - the result value is not predictable), uses smaller memory (flash and - stack) and works more quickly. -*/ -extern long atol(const char *__s) __ATTR_PURE__; - -/** - The atoi() function converts the initial portion of the string - pointed to by \p s to integer representation. In contrast to - - \code (int)strtol(s, (char **)NULL, 10); \endcode - - this function does not detect overflow (\c errno is not changed and - the result value is not predictable), uses smaller memory (flash and - stack) and works more quickly. -*/ -extern int atoi(const char *__s) __ATTR_PURE__; - -/** - The exit() function terminates the application. Since there is no - environment to return to, \c status is ignored, and code execution - will eventually reach an infinite loop, thereby effectively halting - all code processing. Before entering the infinite loop, interrupts - are globally disabled. - - In a C++ context, global destructors will be called before halting - execution. -*/ -extern void exit(int __status) __ATTR_NORETURN__; - -/** - The malloc() function allocates \c size bytes of memory. - If malloc() fails, a NULL pointer is returned. - - Note that malloc() does \e not initialize the returned memory to - zero bytes. - - See the chapter about \ref malloc "malloc() usage" for implementation - details. -*/ -extern void *malloc(size_t __size) __ATTR_MALLOC__; - -/** - The free() function causes the allocated memory referenced by \c - ptr to be made available for future allocations. If \c ptr is - NULL, no action occurs. -*/ -extern void free(void *__ptr); - -/** - \c malloc() \ref malloc_tunables "tunable". -*/ -extern size_t __malloc_margin; - -/** - \c malloc() \ref malloc_tunables "tunable". -*/ -extern char *__malloc_heap_start; - -/** - \c malloc() \ref malloc_tunables "tunable". -*/ -extern char *__malloc_heap_end; - -/** - Allocate \c nele elements of \c size each. Identical to calling - \c malloc() using nele * size as argument, except the - allocated memory will be cleared to zero. -*/ -extern void *calloc(size_t __nele, size_t __size) __ATTR_MALLOC__; - -/** - The realloc() function tries to change the size of the region - allocated at \c ptr to the new \c size value. It returns a - pointer to the new region. The returned pointer might be the - same as the old pointer, or a pointer to a completely different - region. - - The contents of the returned region up to either the old or the new - size value (whatever is less) will be identical to the contents of - the old region, even in case a new region had to be allocated. - - It is acceptable to pass \c ptr as NULL, in which case realloc() - will behave identical to malloc(). - - If the new memory cannot be allocated, realloc() returns NULL, and - the region at \c ptr will not be changed. -*/ -extern void *realloc(void *__ptr, size_t __size) __ATTR_MALLOC__; - -extern double strtod(const char *__nptr, char **__endptr); - -/** \ingroup avr_stdlib - \fn double atof (const char *nptr) - - The atof() function converts the initial portion of the string pointed - to by \a nptr to double representation. - - It is equivalent to calling - \code strtod(nptr, (char **)0); \endcode - */ -extern double atof(const char *__nptr); - -/** Highest number that can be generated by rand(). */ -#define RAND_MAX 0x7FFF - -/** - The rand() function computes a sequence of pseudo-random integers in the - range of 0 to \c RAND_MAX (as defined by the header file ). - - The srand() function sets its argument \c seed as the seed for a new - sequence of pseudo-random numbers to be returned by rand(). These - sequences are repeatable by calling srand() with the same seed value. - - If no seed value is provided, the functions are automatically seeded with - a value of 1. - - In compliance with the C standard, these functions operate on - \c int arguments. Since the underlying algorithm already uses - 32-bit calculations, this causes a loss of precision. See - \c random() for an alternate set of functions that retains full - 32-bit precision. -*/ -extern int rand(void); -/** - Pseudo-random number generator seeding; see rand(). -*/ -extern void srand(unsigned int __seed); - -/** - Variant of rand() that stores the context in the user-supplied - variable located at \c ctx instead of a static library variable - so the function becomes re-entrant. -*/ -extern int rand_r(unsigned long *__ctx); -/*@}*/ - -/*@{*/ -/** \name Non-standard (i.e. non-ISO C) functions. - \ingroup avr_stdlib -*/ -/** - \brief Convert an integer to a string. - - The function itoa() converts the integer value from \c val into an - ASCII representation that will be stored under \c s. The caller - is responsible for providing sufficient storage in \c s. - - \note The minimal size of the buffer \c s depends on the choice of - radix. For example, if the radix is 2 (binary), you need to supply a buffer - with a minimal length of 8 * sizeof (int) + 1 characters, i.e. one - character for each bit plus one for the string terminator. Using a larger - radix will require a smaller minimal buffer size. - - \warning If the buffer is too small, you risk a buffer overflow. - - Conversion is done using the \c radix as base, which may be a - number between 2 (binary conversion) and up to 36. If \c radix - is greater than 10, the next digit after \c '9' will be the letter - \c 'a'. - - If radix is 10 and val is negative, a minus sign will be prepended. - - The itoa() function returns the pointer passed as \c s. -*/ -#ifdef __DOXYGEN__ -extern char *itoa(int val, char *s, int radix); -#else -extern __inline__ __ATTR_GNU_INLINE__ -char *itoa (int __val, char *__s, int __radix) -{ - if (!__builtin_constant_p (__radix)) { - extern char *__itoa (int, char *, int); - return __itoa (__val, __s, __radix); - } else if (__radix < 2 || __radix > 36) { - *__s = 0; - return __s; - } else { - extern char *__itoa_ncheck (int, char *, unsigned char); - return __itoa_ncheck (__val, __s, __radix); - } -} -#endif - -/** - \ingroup avr_stdlib - - \brief Convert a long integer to a string. - - The function ltoa() converts the long integer value from \c val into an - ASCII representation that will be stored under \c s. The caller - is responsible for providing sufficient storage in \c s. - - \note The minimal size of the buffer \c s depends on the choice of - radix. For example, if the radix is 2 (binary), you need to supply a buffer - with a minimal length of 8 * sizeof (long int) + 1 characters, i.e. one - character for each bit plus one for the string terminator. Using a larger - radix will require a smaller minimal buffer size. - - \warning If the buffer is too small, you risk a buffer overflow. - - Conversion is done using the \c radix as base, which may be a - number between 2 (binary conversion) and up to 36. If \c radix - is greater than 10, the next digit after \c '9' will be the letter - \c 'a'. - - If radix is 10 and val is negative, a minus sign will be prepended. - - The ltoa() function returns the pointer passed as \c s. -*/ -#ifdef __DOXYGEN__ -extern char *ltoa(long val, char *s, int radix); -#else -extern __inline__ __ATTR_GNU_INLINE__ -char *ltoa (long __val, char *__s, int __radix) -{ - if (!__builtin_constant_p (__radix)) { - extern char *__ltoa (long, char *, int); - return __ltoa (__val, __s, __radix); - } else if (__radix < 2 || __radix > 36) { - *__s = 0; - return __s; - } else { - extern char *__ltoa_ncheck (long, char *, unsigned char); - return __ltoa_ncheck (__val, __s, __radix); - } -} -#endif - -/** - \ingroup avr_stdlib - - \brief Convert an unsigned integer to a string. - - The function utoa() converts the unsigned integer value from \c val into an - ASCII representation that will be stored under \c s. The caller - is responsible for providing sufficient storage in \c s. - - \note The minimal size of the buffer \c s depends on the choice of - radix. For example, if the radix is 2 (binary), you need to supply a buffer - with a minimal length of 8 * sizeof (unsigned int) + 1 characters, i.e. one - character for each bit plus one for the string terminator. Using a larger - radix will require a smaller minimal buffer size. - - \warning If the buffer is too small, you risk a buffer overflow. - - Conversion is done using the \c radix as base, which may be a - number between 2 (binary conversion) and up to 36. If \c radix - is greater than 10, the next digit after \c '9' will be the letter - \c 'a'. - - The utoa() function returns the pointer passed as \c s. -*/ -#ifdef __DOXYGEN__ -extern char *utoa(unsigned int val, char *s, int radix); -#else -extern __inline__ __ATTR_GNU_INLINE__ -char *utoa (unsigned int __val, char *__s, int __radix) -{ - if (!__builtin_constant_p (__radix)) { - extern char *__utoa (unsigned int, char *, int); - return __utoa (__val, __s, __radix); - } else if (__radix < 2 || __radix > 36) { - *__s = 0; - return __s; - } else { - extern char *__utoa_ncheck (unsigned int, char *, unsigned char); - return __utoa_ncheck (__val, __s, __radix); - } -} -#endif - -/** - \ingroup avr_stdlib - \brief Convert an unsigned long integer to a string. - - The function ultoa() converts the unsigned long integer value from - \c val into an ASCII representation that will be stored under \c s. - The caller is responsible for providing sufficient storage in \c s. - - \note The minimal size of the buffer \c s depends on the choice of - radix. For example, if the radix is 2 (binary), you need to supply a buffer - with a minimal length of 8 * sizeof (unsigned long int) + 1 characters, - i.e. one character for each bit plus one for the string terminator. Using a - larger radix will require a smaller minimal buffer size. - - \warning If the buffer is too small, you risk a buffer overflow. - - Conversion is done using the \c radix as base, which may be a - number between 2 (binary conversion) and up to 36. If \c radix - is greater than 10, the next digit after \c '9' will be the letter - \c 'a'. - - The ultoa() function returns the pointer passed as \c s. -*/ -#ifdef __DOXYGEN__ -extern char *ultoa(unsigned long val, char *s, int radix); -#else -extern __inline__ __ATTR_GNU_INLINE__ -char *ultoa (unsigned long __val, char *__s, int __radix) -{ - if (!__builtin_constant_p (__radix)) { - extern char *__ultoa (unsigned long, char *, int); - return __ultoa (__val, __s, __radix); - } else if (__radix < 2 || __radix > 36) { - *__s = 0; - return __s; - } else { - extern char *__ultoa_ncheck (unsigned long, char *, unsigned char); - return __ultoa_ncheck (__val, __s, __radix); - } -} -#endif - -/** \ingroup avr_stdlib -Highest number that can be generated by random(). */ -#define RANDOM_MAX 0x7FFFFFFF - -/** - \ingroup avr_stdlib - The random() function computes a sequence of pseudo-random integers in the - range of 0 to \c RANDOM_MAX (as defined by the header file ). - - The srandom() function sets its argument \c seed as the seed for a new - sequence of pseudo-random numbers to be returned by rand(). These - sequences are repeatable by calling srandom() with the same seed value. - - If no seed value is provided, the functions are automatically seeded with - a value of 1. -*/ -extern long random(void); -/** - \ingroup avr_stdlib - Pseudo-random number generator seeding; see random(). -*/ -extern void srandom(unsigned long __seed); - -/** - \ingroup avr_stdlib - Variant of random() that stores the context in the user-supplied - variable located at \c ctx instead of a static library variable - so the function becomes re-entrant. -*/ -extern long random_r(unsigned long *__ctx); -#endif /* __ASSEMBLER */ -/*@}*/ - -/*@{*/ -/** \name Conversion functions for double arguments. - \ingroup avr_stdlib - Note that these functions are not located in the default library, - libc.a, but in the mathematical library, libm.a. - So when linking the application, the \c -lm option needs to be - specified. -*/ -/** \ingroup avr_stdlib - Bit value that can be passed in \c flags to dtostre(). */ -#define DTOSTR_ALWAYS_SIGN 0x01 /* put '+' or ' ' for positives */ -/** \ingroup avr_stdlib - Bit value that can be passed in \c flags to dtostre(). */ -#define DTOSTR_PLUS_SIGN 0x02 /* put '+' rather than ' ' */ -/** \ingroup avr_stdlib - Bit value that can be passed in \c flags to dtostre(). */ -#define DTOSTR_UPPERCASE 0x04 /* put 'E' rather 'e' */ - -#ifndef __ASSEMBLER__ - -/** - \ingroup avr_stdlib - The dtostre() function converts the double value passed in \c val into - an ASCII representation that will be stored under \c s. The caller - is responsible for providing sufficient storage in \c s. - - Conversion is done in the format \c "[-]d.ddde±dd" where there is - one digit before the decimal-point character and the number of - digits after it is equal to the precision \c prec; if the precision - is zero, no decimal-point character appears. If \c flags has the - DTOSTR_UPPERCASE bit set, the letter \c 'E' (rather than \c 'e' ) will be - used to introduce the exponent. The exponent always contains two - digits; if the value is zero, the exponent is \c "00". - - If \c flags has the DTOSTR_ALWAYS_SIGN bit set, a space character - will be placed into the leading position for positive numbers. - - If \c flags has the DTOSTR_PLUS_SIGN bit set, a plus sign will be - used instead of a space character in this case. - - The dtostre() function returns the pointer to the converted string \c s. -*/ -extern char *dtostre(double __val, char *__s, unsigned char __prec, - unsigned char __flags); - -/** - \ingroup avr_stdlib - The dtostrf() function converts the double value passed in \c val into - an ASCII representationthat will be stored under \c s. The caller - is responsible for providing sufficient storage in \c s. - - Conversion is done in the format \c "[-]d.ddd". The minimum field - width of the output string (including the possible \c '.' and the possible - sign for negative values) is given in \c width, and \c prec determines - the number of digits after the decimal sign. \c width is signed value, - negative for left adjustment. - - The dtostrf() function returns the pointer to the converted string \c s. -*/ -extern char *dtostrf(double __val, signed char __width, - unsigned char __prec, char *__s); - -/** - \ingroup avr_stdlib - Successful termination for exit(); evaluates to 0. -*/ -#define EXIT_SUCCESS 0 - -/** - \ingroup avr_stdlib - Unsuccessful termination for exit(); evaluates to a non-zero value. -*/ -#define EXIT_FAILURE 1 - -/*@}*/ - -#ifndef __DOXYGEN__ -/* dummy declarations for libstdc++ compatibility */ -extern int atexit(void (*)(void)); -extern int system (const char *); -extern char *getenv (const char *); -#endif /* __DOXYGEN__ */ - -#ifdef __cplusplus -} -#endif - -#endif /* __ASSEMBLER */ - -#endif /* _STDLIB_H_ */ diff --git a/arduino/hardware/tools/avr/avr/include/string.h b/arduino/hardware/tools/avr/avr/include/string.h deleted file mode 100644 index 35d895b..0000000 --- a/arduino/hardware/tools/avr/avr/include/string.h +++ /dev/null @@ -1,620 +0,0 @@ -/* Copyright (c) 2002,2007 Marek Michalkiewicz - All rights reserved. - - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - * Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - * Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in - the documentation and/or other materials provided with the - distribution. - - * Neither the name of the copyright holders nor the names of - contributors may be used to endorse or promote products derived - from this software without specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. */ - -/* $Id$ */ - -/* - string.h - - Contributors: - Created by Marek Michalkiewicz - */ - -#ifndef _STRING_H_ -#define _STRING_H_ 1 - -#ifndef __DOXYGEN__ -#define __need_NULL -#define __need_size_t -#include - -#ifndef __ATTR_PURE__ -#define __ATTR_PURE__ __attribute__((__pure__)) -#endif - -#ifndef __ATTR_CONST__ -# define __ATTR_CONST__ __attribute__((__const__)) -#endif -#endif /* !__DOXYGEN__ */ - -#ifdef __cplusplus -extern "C" { -#endif - -/** \file */ -/** \defgroup avr_string : Strings - \code #include \endcode - - The string functions perform string operations on NULL terminated - strings. - - \note If the strings you are working on resident in program space (flash), - you will need to use the string functions described in \ref avr_pgmspace. */ - - -/** \ingroup avr_string - - This macro finds the first (least significant) bit set in the - input value. - - This macro is very similar to the function ffs() except that - it evaluates its argument at compile-time, so it should only - be applied to compile-time constant expressions where it will - reduce to a constant itself. - Application of this macro to expressions that are not constant - at compile-time is not recommended, and might result in a huge - amount of code generated. - - \returns The _FFS() macro returns the position of the first - (least significant) bit set in the word val, or 0 if no bits are set. - The least significant bit is position 1. Only 16 bits of argument - are evaluted. -*/ -#if defined(__DOXYGEN__) -#define _FFS(x) -#else /* !DOXYGEN */ -#define _FFS(x) \ - (1 \ - + (((x) & 1) == 0) \ - + (((x) & 3) == 0) \ - + (((x) & 7) == 0) \ - + (((x) & 017) == 0) \ - + (((x) & 037) == 0) \ - + (((x) & 077) == 0) \ - + (((x) & 0177) == 0) \ - + (((x) & 0377) == 0) \ - + (((x) & 0777) == 0) \ - + (((x) & 01777) == 0) \ - + (((x) & 03777) == 0) \ - + (((x) & 07777) == 0) \ - + (((x) & 017777) == 0) \ - + (((x) & 037777) == 0) \ - + (((x) & 077777) == 0) \ - - (((x) & 0177777) == 0) * 16) -#endif /* DOXYGEN */ - -/** \ingroup avr_string - \fn int ffs(int val); - - \brief This function finds the first (least significant) bit set in the input value. - - \returns The ffs() function returns the position of the first - (least significant) bit set in the word val, or 0 if no bits are set. - The least significant bit is position 1. - - \note For expressions that are constant at compile time, consider - using the \ref _FFS macro instead. -*/ -extern int ffs(int __val) __ATTR_CONST__; - -/** \ingroup avr_string - \fn int ffsl(long val); - - \brief Same as ffs(), for an argument of type long. */ -extern int ffsl(long __val) __ATTR_CONST__; - -/** \ingroup avr_string - \fn int ffsll(long long val); - - \brief Same as ffs(), for an argument of type long long. */ -__extension__ extern int ffsll(long long __val) __ATTR_CONST__; - -/** \ingroup avr_string - \fn void *memccpy(void *dest, const void *src, int val, size_t len) - \brief Copy memory area. - - The memccpy() function copies no more than \p len bytes from memory - area \p src to memory area \p dest, stopping when the character \p val - is found. - - \returns The memccpy() function returns a pointer to the next character - in \p dest after \p val, or NULL if \p val was not found in the first - \p len characters of \p src. */ -extern void *memccpy(void *, const void *, int, size_t); - -/** \ingroup avr_string - \fn void *memchr(const void *src, int val, size_t len) - \brief Scan memory for a character. - - The memchr() function scans the first len bytes of the memory area pointed - to by src for the character val. The first byte to match val (interpreted - as an unsigned character) stops the operation. - - \returns The memchr() function returns a pointer to the matching byte or - NULL if the character does not occur in the given memory area. */ -extern void *memchr(const void *, int, size_t) __ATTR_PURE__; - -/** \ingroup avr_string - \fn int memcmp(const void *s1, const void *s2, size_t len) - \brief Compare memory areas - - The memcmp() function compares the first len bytes of the memory areas s1 - and s2. The comparision is performed using unsigned char operations. - - \returns The memcmp() function returns an integer less than, equal to, or - greater than zero if the first len bytes of s1 is found, respectively, to be - less than, to match, or be greater than the first len bytes of s2. - - \note Be sure to store the result in a 16 bit variable since you may get - incorrect results if you use an unsigned char or char due to truncation. - - \warning This function is not -mint8 compatible, although if you only care - about testing for equality, this function should be safe to use. */ -extern int memcmp(const void *, const void *, size_t) __ATTR_PURE__; - -/** \ingroup avr_string - \fn void *memcpy(void *dest, const void *src, size_t len) - \brief Copy a memory area. - - The memcpy() function copies len bytes from memory area src to memory area - dest. The memory areas may not overlap. Use memmove() if the memory - areas do overlap. - - \returns The memcpy() function returns a pointer to dest. */ -extern void *memcpy(void *, const void *, size_t); - -/** \ingroup avr_string - \fn void *memmem(const void *s1, size_t len1, const void *s2, size_t len2) - - The memmem() function finds the start of the first occurrence of the - substring \p s2 of length \p len2 in the memory area \p s1 of length - \p len1. - - \return The memmem() function returns a pointer to the beginning of - the substring, or \c NULL if the substring is not found. If \p len2 - is zero, the function returns \p s1. */ -extern void *memmem(const void *, size_t, const void *, size_t) __ATTR_PURE__; - -/** \ingroup avr_string - \fn void *memmove(void *dest, const void *src, size_t len) - \brief Copy memory area. - - The memmove() function copies len bytes from memory area src to memory area - dest. The memory areas may overlap. - - \returns The memmove() function returns a pointer to dest. */ -extern void *memmove(void *, const void *, size_t); - -/** \ingroup avr_string - \fn void *memrchr(const void *src, int val, size_t len) - - The memrchr() function is like the memchr() function, except that it - searches backwards from the end of the \p len bytes pointed to by \p - src instead of forwards from the front. (Glibc, GNU extension.) - - \return The memrchr() function returns a pointer to the matching - byte or \c NULL if the character does not occur in the given memory - area. */ -extern void *memrchr(const void *, int, size_t) __ATTR_PURE__; - -/** \ingroup avr_string - \fn void *memset(void *dest, int val, size_t len) - \brief Fill memory with a constant byte. - - The memset() function fills the first len bytes of the memory area pointed - to by dest with the constant byte val. - - \returns The memset() function returns a pointer to the memory area dest. */ -extern void *memset(void *, int, size_t); - -/** \ingroup avr_string - \fn char *strcat(char *dest, const char *src) - \brief Concatenate two strings. - - The strcat() function appends the src string to the dest string - overwriting the '\\0' character at the end of dest, and then adds a - terminating '\\0' character. The strings may not overlap, and the dest - string must have enough space for the result. - - \returns The strcat() function returns a pointer to the resulting string - dest. */ -extern char *strcat(char *, const char *); - -/** \ingroup avr_string - \fn char *strchr(const char *src, int val) - \brief Locate character in string. - - The strchr() function returns a pointer to the first occurrence of - the character \p val in the string \p src. - - Here "character" means "byte" - these functions do not work with - wide or multi-byte characters. - - \returns The strchr() function returns a pointer to the matched - character or \c NULL if the character is not found. */ -extern char *strchr(const char *, int) __ATTR_PURE__; - -/** \ingroup avr_string - \fn char *strchrnul(const char *s, int c) - - The strchrnul() function is like strchr() except that if \p c is not - found in \p s, then it returns a pointer to the null byte at the end - of \p s, rather than \c NULL. (Glibc, GNU extension.) - - \return The strchrnul() function returns a pointer to the matched - character, or a pointer to the null byte at the end of \p s (i.e., - \c s+strlen(s)) if the character is not found. */ -extern char *strchrnul(const char *, int) __ATTR_PURE__; - -/** \ingroup avr_string - \fn int strcmp(const char *s1, const char *s2) - \brief Compare two strings. - - The strcmp() function compares the two strings \p s1 and \p s2. - - \returns The strcmp() function returns an integer less than, equal - to, or greater than zero if \p s1 is found, respectively, to be less - than, to match, or be greater than \p s2. A consequence of the - ordering used by strcmp() is that if \p s1 is an initial substring - of \p s2, then \p s1 is considered to be "less than" \p s2. */ -extern int strcmp(const char *, const char *) __ATTR_PURE__; - -/** \ingroup avr_string - \fn char *strcpy(char *dest, const char *src) - \brief Copy a string. - - The strcpy() function copies the string pointed to by src (including the - terminating '\\0' character) to the array pointed to by dest. The strings - may not overlap, and the destination string dest must be large enough to - receive the copy. - - \returns The strcpy() function returns a pointer to the destination - string dest. - - \note If the destination string of a strcpy() is not large enough (that - is, if the programmer was stupid/lazy, and failed to check the size before - copying) then anything might happen. Overflowing fixed length strings is - a favourite cracker technique. */ -extern char *strcpy(char *, const char *); - -/** \ingroup avr_string - \fn int strcasecmp(const char *s1, const char *s2) - \brief Compare two strings ignoring case. - - The strcasecmp() function compares the two strings \p s1 and \p s2, - ignoring the case of the characters. - - \returns The strcasecmp() function returns an integer less than, - equal to, or greater than zero if \p s1 is found, respectively, to - be less than, to match, or be greater than \p s2. A consequence of - the ordering used by strcasecmp() is that if \p s1 is an initial - substring of \p s2, then \p s1 is considered to be "less than" - \p s2. */ -extern int strcasecmp(const char *, const char *) __ATTR_PURE__; - -/** \ingroup avr_string - \fn char *strcasestr(const char *s1, const char *s2) - - The strcasestr() function finds the first occurrence of the - substring \p s2 in the string \p s1. This is like strstr(), except - that it ignores case of alphabetic symbols in searching for the - substring. (Glibc, GNU extension.) - - \return The strcasestr() function returns a pointer to the beginning - of the substring, or \c NULL if the substring is not found. If \p s2 - points to a string of zero length, the function returns \p s1. */ -extern char *strcasestr(const char *, const char *) __ATTR_PURE__; - -/** \ingroup avr_string - \fn size_t strcspn(const char *s, const char *reject) - - The strcspn() function calculates the length of the initial segment - of \p s which consists entirely of characters not in \p reject. - - \return The strcspn() function returns the number of characters in - the initial segment of \p s which are not in the string \p reject. - The terminating zero is not considered as a part of string. */ -extern size_t strcspn(const char *__s, const char *__reject) __ATTR_PURE__; - -/** \ingroup avr_string - \fn char *strdup(const char *s1) - \brief Duplicate a string. - - The strdup() function allocates memory and copies into it the string - addressed by s1, including the terminating null character. - - \warning The strdup() function calls malloc() to allocate the memory - for the duplicated string! The user is responsible for freeing the - memory by calling free(). - - \returns The strdup() function returns a pointer to the resulting string - dest. If malloc() cannot allocate enough storage for the string, strdup() - will return NULL. - - \warning Be sure to check the return value of the strdup() function to - make sure that the function has succeeded in allocating the memory! -*/ -extern char *strdup(const char *s1); - -/** \ingroup avr_string - \fn size_t strlcat(char *dst, const char *src, size_t siz) - \brief Concatenate two strings. - - Appends \p src to string \p dst of size \p siz (unlike strncat(), - \p siz is the full size of \p dst, not space left). At most \p siz-1 - characters will be copied. Always NULL terminates (unless \p siz <= - \p strlen(dst)). - - \returns The strlcat() function returns strlen(src) + MIN(siz, - strlen(initial dst)). If retval >= siz, truncation occurred. */ -extern size_t strlcat(char *, const char *, size_t); - -/** \ingroup avr_string - \fn size_t strlcpy(char *dst, const char *src, size_t siz) - \brief Copy a string. - - Copy \p src to string \p dst of size \p siz. At most \p siz-1 - characters will be copied. Always NULL terminates (unless \p siz == 0). - - \returns The strlcpy() function returns strlen(src). If retval >= siz, - truncation occurred. */ -extern size_t strlcpy(char *, const char *, size_t); - -/** \ingroup avr_string - \fn size_t strlen(const char *src) - \brief Calculate the length of a string. - - The strlen() function calculates the length of the string src, not - including the terminating '\\0' character. - - \returns The strlen() function returns the number of characters in - src. */ -extern size_t strlen(const char *) __ATTR_PURE__; - -/** \ingroup avr_string - \fn char *strlwr(char *s) - \brief Convert a string to lower case. - - The strlwr() function will convert a string to lower case. Only the upper - case alphabetic characters [A .. Z] are converted. Non-alphabetic - characters will not be changed. - - \returns The strlwr() function returns a pointer to the converted - string. */ -extern char *strlwr(char *); - -/** \ingroup avr_string - \fn char *strncat(char *dest, const char *src, size_t len) - \brief Concatenate two strings. - - The strncat() function is similar to strcat(), except that only the first - n characters of src are appended to dest. - - \returns The strncat() function returns a pointer to the resulting string - dest. */ -extern char *strncat(char *, const char *, size_t); - -/** \ingroup avr_string - \fn int strncmp(const char *s1, const char *s2, size_t len) - \brief Compare two strings. - - The strncmp() function is similar to strcmp(), except it only compares the - first (at most) n characters of s1 and s2. - - \returns The strncmp() function returns an integer less than, equal to, or - greater than zero if s1 (or the first n bytes thereof) is found, - respectively, to be less than, to match, or be greater than s2. */ -extern int strncmp(const char *, const char *, size_t) __ATTR_PURE__; - -/** \ingroup avr_string - \fn char *strncpy(char *dest, const char *src, size_t len) - \brief Copy a string. - - The strncpy() function is similar to strcpy(), except that not more than n - bytes of src are copied. Thus, if there is no null byte among the first n - bytes of src, the result will not be null-terminated. - - In the case where the length of src is less than that of n, the remainder - of dest will be padded with nulls. - - \returns The strncpy() function returns a pointer to the destination - string dest. */ -extern char *strncpy(char *, const char *, size_t); - -/** \ingroup avr_string - \fn int strncasecmp(const char *s1, const char *s2, size_t len) - \brief Compare two strings ignoring case. - - The strncasecmp() function is similar to strcasecmp(), except it - only compares the first \p len characters of \p s1. - - \returns The strncasecmp() function returns an integer less than, - equal to, or greater than zero if \p s1 (or the first \p len bytes - thereof) is found, respectively, to be less than, to match, or be - greater than \p s2. A consequence of the ordering used by - strncasecmp() is that if \p s1 is an initial substring of \p s2, - then \p s1 is considered to be "less than" \p s2. */ -extern int strncasecmp(const char *, const char *, size_t) __ATTR_PURE__; - -/** \ingroup avr_string - \fn size_t strnlen(const char *src, size_t len) - \brief Determine the length of a fixed-size string. - - The strnlen function returns the number of characters in the string - pointed to by src, not including the terminating '\\0' character, but at - most len. In doing this, strnlen looks only at the first len characters at - src and never beyond src+len. - - \returns The strnlen function returns strlen(src), if that is less than - len, or len if there is no '\\0' character among the first len - characters pointed to by src. */ -extern size_t strnlen(const char *, size_t) __ATTR_PURE__; - -/** \ingroup avr_string - \fn char *strpbrk(const char *s, const char *accept) - - The strpbrk() function locates the first occurrence in the string - \p s of any of the characters in the string \p accept. - - \return The strpbrk() function returns a pointer to the character - in \p s that matches one of the characters in \p accept, or \c NULL - if no such character is found. The terminating zero is not - considered as a part of string: if one or both args are empty, the - result will be \c NULL. */ -extern char *strpbrk(const char *__s, const char *__accept) __ATTR_PURE__; - -/** \ingroup avr_string - \fn char *strrchr(const char *src, int val) - \brief Locate character in string. - - The strrchr() function returns a pointer to the last occurrence of the - character val in the string src. - - Here "character" means "byte" - these functions do not work with wide or - multi-byte characters. - - \returns The strrchr() function returns a pointer to the matched character - or NULL if the character is not found. */ -extern char *strrchr(const char *, int) __ATTR_PURE__; - -/** \ingroup avr_string - \fn char *strrev(char *s) - \brief Reverse a string. - - The strrev() function reverses the order of the string. - - \returns The strrev() function returns a pointer to the beginning of the - reversed string. */ -extern char *strrev(char *); - -/** \ingroup avr_string - \fn char *strsep(char **sp, const char *delim) - \brief Parse a string into tokens. - - The strsep() function locates, in the string referenced by \p *sp, - the first occurrence of any character in the string \p delim (or the - terminating '\\0' character) and replaces it with a '\\0'. The - location of the next character after the delimiter character (or \c - NULL, if the end of the string was reached) is stored in \p *sp. An - ``empty'' field, i.e. one caused by two adjacent delimiter - characters, can be detected by comparing the location referenced by - the pointer returned in \p *sp to '\\0'. - - \return The strsep() function returns a pointer to the original - value of \p *sp. If \p *sp is initially \c NULL, strsep() returns - \c NULL. */ -extern char *strsep(char **, const char *); - -/** \ingroup avr_string - \fn size_t strspn(const char *s, const char *accept) - - The strspn() function calculates the length of the initial segment - of \p s which consists entirely of characters in \p accept. - - \return The strspn() function returns the number of characters in - the initial segment of \p s which consist only of characters from \p - accept. The terminating zero is not considered as a part of string. */ -extern size_t strspn(const char *__s, const char *__accept) __ATTR_PURE__; - -/** \ingroup avr_string - \fn char *strstr(const char *s1, const char *s2) - \brief Locate a substring. - - The strstr() function finds the first occurrence of the substring \p - s2 in the string \p s1. The terminating '\\0' characters are not - compared. - - \returns The strstr() function returns a pointer to the beginning of - the substring, or \c NULL if the substring is not found. If \p s2 - points to a string of zero length, the function returns \p s1. */ -extern char *strstr(const char *, const char *) __ATTR_PURE__; - -/** \ingroup avr_string - \fn char *strtok(char *s, const char *delim) - \brief Parses the string s into tokens. - - strtok parses the string s into tokens. The first call to strtok - should have s as its first argument. Subsequent calls should have - the first argument set to NULL. If a token ends with a delimiter, this - delimiting character is overwritten with a '\\0' and a pointer to the next - character is saved for the next call to strtok. The delimiter string - delim may be different for each call. - - \returns The strtok() function returns a pointer to the next token or - NULL when no more tokens are found. - - \note strtok() is NOT reentrant. For a reentrant version of this function - see \c strtok_r(). -*/ -extern char *strtok(char *, const char *); - -/** \ingroup avr_string - \fn char *strtok_r(char *string, const char *delim, char **last) - \brief Parses string into tokens. - - strtok_r parses string into tokens. The first call to strtok_r - should have string as its first argument. Subsequent calls should have - the first argument set to NULL. If a token ends with a delimiter, this - delimiting character is overwritten with a '\\0' and a pointer to the next - character is saved for the next call to strtok_r. The delimiter string - \p delim may be different for each call. \p last is a user allocated char* - pointer. It must be the same while parsing the same string. strtok_r is - a reentrant version of strtok(). - - \returns The strtok_r() function returns a pointer to the next token or - NULL when no more tokens are found. */ -extern char *strtok_r(char *, const char *, char **); - -/** \ingroup avr_string - \fn char *strupr(char *s) - \brief Convert a string to upper case. - - The strupr() function will convert a string to upper case. Only the lower - case alphabetic characters [a .. z] are converted. Non-alphabetic - characters will not be changed. - - \returns The strupr() function returns a pointer to the converted - string. The pointer is the same as that passed in since the operation is - perform in place. */ -extern char *strupr(char *); - -#ifndef __DOXYGEN__ -/* libstdc++ compatibility, dummy declarations */ -extern int strcoll(const char *s1, const char *s2); -extern char *strerror(int errnum); -extern size_t strxfrm(char *dest, const char *src, size_t n); -#endif /* !__DOXYGEN__ */ - -#ifdef __cplusplus -} -#endif - -#endif /* _STRING_H_ */ - diff --git a/arduino/hardware/tools/avr/avr/include/sys/types.h b/arduino/hardware/tools/avr/avr/include/sys/types.h deleted file mode 100644 index e5df837..0000000 --- a/arduino/hardware/tools/avr/avr/include/sys/types.h +++ /dev/null @@ -1,6 +0,0 @@ -#ifndef _SYS_TYPES_H_ -#define _SYS_TYPES_H_ 1 - -typedef long off_t; - -#endif diff --git a/arduino/hardware/tools/avr/avr/include/time.h b/arduino/hardware/tools/avr/avr/include/time.h deleted file mode 100644 index ffffaac..0000000 --- a/arduino/hardware/tools/avr/avr/include/time.h +++ /dev/null @@ -1,509 +0,0 @@ -/* - * (C)2012 Michael Duane Rice All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: - * - * Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. Redistributions in binary - * form must reproduce the above copyright notice, this list of conditions - * and the following disclaimer in the documentation and/or other materials - * provided with the distribution. Neither the name of the copyright holders - * nor the names of contributors may be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ - -/* $Id$ */ - -/** \file */ - -/** \defgroup avr_time : Time - \code #include \endcode -

Introduction to the Time functions

- This file declares the time functions implemented in \c avr-libc. - - The implementation aspires to conform with ISO/IEC 9899 (C90). However, due to limitations of the - target processor and the nature of its development environment, a practical implementation must - of necessity deviate from the standard. - - - - Section 7.23.2.1 clock() - The type clock_t, the macro CLOCKS_PER_SEC, and the function clock() are not implemented. We - consider these items belong to operating system code, or to application code when no operating - system is present. - - Section 7.23.2.3 mktime() - The standard specifies that mktime() should return (time_t) -1, if the time cannot be represented. - This implementation always returns a 'best effort' representation. - - Section 7.23.2.4 time() - The standard specifies that time() should return (time_t) -1, if the time is not available. - Since the application must initialize the time system, this functionality is not implemented. - - Section 7.23.2.2, difftime() - Due to the lack of a 64 bit double, the function difftime() returns a long integer. In most cases - this change will be invisible to the user, handled automatically by the compiler. - - Section 7.23.1.4 struct tm - Per the standard, struct tm->tm_isdst is greater than zero when Daylight Saving time is in effect. - This implementation further specifies that, when positive, the value of tm_isdst represents - the amount time is advanced during Daylight Saving time. - - Section 7.23.3.5 strftime() - Only the 'C' locale is supported, therefore the modifiers 'E' and 'O' are ignored. - The 'Z' conversion is also ignored, due to the lack of time zone name. - - In addition to the above departures from the standard, there are some behaviors which are different - from what is often expected, though allowed under the standard. - - There is no 'platform standard' method to obtain the current time, time zone, or - daylight savings 'rules' in the AVR environment. Therefore the application must initialize - the time system with this information. The functions set_zone(), set_dst(), and - set_system_time() are provided for initialization. Once initialized, system time is maintained by - calling the function system_tick() at one second intervals. - - Though not specified in the standard, it is often expected that time_t is a signed integer - representing an offset in seconds from Midnight Jan 1 1970... i.e. 'Unix time'. This implementation - uses an unsigned 32 bit integer offset from Midnight Jan 1 2000. The use of this 'epoch' helps to - simplify the conversion functions, while the 32 bit value allows time to be properly represented - until Tue Feb 7 06:28:15 2136 UTC. The macros UNIX_OFFSET and NTP_OFFSET are defined to assist in - converting to and from Unix and NTP time stamps. - - Unlike desktop counterparts, it is impractical to implement or maintain the 'zoneinfo' database. - Therefore no attempt is made to account for time zone, daylight saving, or leap seconds in past dates. - All calculations are made according to the currently configured time zone and daylight saving 'rule'. - - In addition to C standard functions, re-entrant versions of ctime(), asctime(), gmtime() and - localtime() are provided which, in addition to being re-entrant, have the property of claiming - less permanent storage in RAM. An additional time conversion, isotime() and its re-entrant version, - uses far less storage than either ctime() or asctime(). - - Along with the usual smattering of utility functions, such as is_leap_year(), this library includes - a set of functions related the sun and moon, as well as sidereal time functions. -*/ - -#ifndef TIME_H -#define TIME_H - -#ifdef __cplusplus -extern "C" { -#endif - -#include -#include - - /** \ingroup avr_time */ - /* @{ */ - - /** - time_t represents seconds elapsed from Midnight, Jan 1 2000 UTC (the Y2K 'epoch'). - Its range allows this implementation to represent time up to Tue Feb 7 06:28:15 2136 UTC. - */ - typedef uint32_t time_t; - - /** - The time function returns the systems current time stamp. - If timer is not a null pointer, the return value is also assigned to the object it points to. - */ - time_t time(time_t *timer); - - /** - The difftime function returns the difference between two binary time stamps, - time1 - time0. - */ - int32_t difftime(time_t time1, time_t time0); - - - /** - The tm structure contains a representation of time 'broken down' into components of the - Gregorian calendar. - - The value of tm_isdst is zero if Daylight Saving Time is not in effect, and is negative if - the information is not available. - - When Daylight Saving Time is in effect, the value represents the number of - seconds the clock is advanced. - - See the set_dst() function for more information about Daylight Saving. - - */ - struct tm { - int8_t tm_sec; /**< seconds after the minute - [ 0 to 59 ] */ - int8_t tm_min; /**< minutes after the hour - [ 0 to 59 ] */ - int8_t tm_hour; /**< hours since midnight - [ 0 to 23 ] */ - int8_t tm_mday; /**< day of the month - [ 1 to 31 ] */ - int8_t tm_wday; /**< days since Sunday - [ 0 to 6 ] */ - int8_t tm_mon; /**< months since January - [ 0 to 11 ] */ - int16_t tm_year; /**< years since 1900 */ - int16_t tm_yday; /**< days since January 1 - [ 0 to 365 ] */ - int16_t tm_isdst; /**< Daylight Saving Time flag */ - }; - -#ifndef __DOXYGEN__ - /* We have to provide clock_t / CLOCKS_PER_SEC so that libstdc++-v3 can - be built. We define CLOCKS_PER_SEC via a symbol _CLOCKS_PER_SEC_ - so that the user can provide the value on the link line, which should - result in little or no run-time overhead compared with a constant. */ - typedef unsigned long clock_t; - extern char *_CLOCKS_PER_SEC_; -#define CLOCKS_PER_SEC ((clock_t) _CLOCKS_PER_SEC_) - extern clock_t clock(void); -#endif /* !__DOXYGEN__ */ - - /** - This function 'compiles' the elements of a broken-down time structure, returning a binary time stamp. - The elements of timeptr are interpreted as representing Local Time. - - The original values of the tm_wday and tm_yday elements of the structure are ignored, - and the original values of the other elements are not restricted to the ranges stated for struct tm. - - On successful completion, the values of all elements of timeptr are set to the appropriate range. - */ - time_t mktime(struct tm * timeptr); - - /** - This function 'compiles' the elements of a broken-down time structure, returning a binary time stamp. - The elements of timeptr are interpreted as representing UTC. - - The original values of the tm_wday and tm_yday elements of the structure are ignored, - and the original values of the other elements are not restricted to the ranges stated for struct tm. - - Unlike mktime(), this function DOES NOT modify the elements of timeptr. - */ - time_t mk_gmtime(const struct tm * timeptr); - - /** - The gmtime function converts the time stamp pointed to by timer into broken-down time, - expressed as UTC. - */ - struct tm *gmtime(const time_t * timer); - - /** - Re entrant version of gmtime(). - */ - void gmtime_r(const time_t * timer, struct tm * timeptr); - - /** - The localtime function converts the time stamp pointed to by timer into broken-down time, - expressed as Local time. - */ - struct tm *localtime(const time_t * timer); - - /** - Re entrant version of localtime(). - */ - void localtime_r(const time_t * timer, struct tm * timeptr); - - /** - The asctime function converts the broken-down time of timeptr, into an ascii string in the form - - Sun Mar 23 01:03:52 2013 - */ - char *asctime(const struct tm * timeptr); - - /** - Re entrant version of asctime(). - */ - void asctime_r(const struct tm * timeptr, char *buf); - - /** - The ctime function is equivalent to asctime(localtime(timer)) - */ - char *ctime(const time_t * timer); - - /** - Re entrant version of ctime(). - */ - void ctime_r(const time_t * timer, char *buf); - - /** - The isotime function constructs an ascii string in the form - \code2013-03-23 01:03:52\endcode - */ - char *isotime(const struct tm * tmptr); - - /** - Re entrant version of isotime() - */ - void isotime_r(const struct tm *, char *); - - /** - A complete description of strftime() is beyond the pale of this document. - Refer to ISO/IEC document 9899 for details. - - All conversions are made using the 'C Locale', ignoring the E or O modifiers. Due to the lack of - a time zone 'name', the 'Z' conversion is also ignored. - */ - size_t strftime(char *s, size_t maxsize, const char *format, const struct tm * timeptr); - - /** - Specify the Daylight Saving function. - - The Daylight Saving function should examine its parameters to determine whether - Daylight Saving is in effect, and return a value appropriate for tm_isdst. - - Working examples for the USA and the EU are available.. - - \code #include \endcode - for the European Union, and - \code #include \endcode - for the United States - - If a Daylight Saving function is not specified, the system will ignore Daylight Saving. - */ - void set_dst(int (*) (const time_t *, int32_t *)); - - /** - Set the 'time zone'. The parameter is given in seconds East of the Prime Meridian. - Example for New York City: - \code set_zone(-5 * ONE_HOUR);\endcode - - If the time zone is not set, the time system will operate in UTC only. - */ - void set_zone(int32_t); - - /** - Initialize the system time. Examples are... - - From a Clock / Calendar type RTC: - \code - struct tm rtc_time; - - read_rtc(&rtc_time); - rtc_time.tm_isdst = 0; - set_system_time( mktime(&rtc_time) ); - \endcode - - From a Network Time Protocol time stamp: - \code - set_system_time(ntp_timestamp - NTP_OFFSET); - \endcode - - From a UNIX time stamp: - \code - set_system_time(unix_timestamp - UNIX_OFFSET); - \endcode - - */ - void set_system_time(time_t timestamp); - - /** - Maintain the system time by calling this function at a rate of 1 Hertz. - - It is anticipated that this function will typically be called from within an - Interrupt Service Routine, (though that is not required). It therefore includes code which - makes it simple to use from within a 'Naked' ISR, avoiding the cost of saving and restoring - all the cpu registers. - - Such an ISR may resemble the following example... - \code - ISR(RTC_OVF_vect, ISR_NAKED) - { - system_tick(); - reti(); - } - \endcode - */ - void system_tick(void); - - /** - Enumerated labels for the days of the week. - */ - enum _WEEK_DAYS_ { - SUNDAY, - MONDAY, - TUESDAY, - WEDNESDAY, - THURSDAY, - FRIDAY, - SATURDAY - }; - - /** - Enumerated labels for the months. - */ - enum _MONTHS_ { - JANUARY, - FEBRUARY, - MARCH, - APRIL, - MAY, - JUNE, - JULY, - AUGUST, - SEPTEMBER, - OCTOBER, - NOVEMBER, - DECEMBER - }; - - /** - Return 1 if year is a leap year, zero if it is not. - */ - uint8_t is_leap_year(int16_t year); - - /** - Return the length of month, given the year and month, where month is in the range 1 to 12. - */ - uint8_t month_length(int16_t year, uint8_t month); - - /** - Return the calendar week of year, where week 1 is considered to begin on the - day of week specified by 'start'. The returned value may range from zero to 52. - */ - uint8_t week_of_year(const struct tm * timeptr, uint8_t start); - - /** - Return the calendar week of month, where the first week is considered to begin on the - day of week specified by 'start'. The returned value may range from zero to 5. - */ - uint8_t week_of_month(const struct tm * timeptr, uint8_t start); - - /** - Structure which represents a date as a year, week number of that year, and day of week. - See http://en.wikipedia.org/wiki/ISO_week_date for more information. - */ - struct week_date { - int year; /**< year number (Gregorian calendar) */ - int week; /**< week number (#1 is where first Thursday is in) */ - int day; /**< day within week */ - }; - - /** - Return a week_date structure with the ISO_8601 week based date corresponding to the given - year and day of year. See http://en.wikipedia.org/wiki/ISO_week_date for more - information. - */ - struct week_date * iso_week_date( int year, int yday); - - /** - Re-entrant version of iso-week_date. - */ - void iso_week_date_r( int year, int yday, struct week_date *); - - /** - Convert a Y2K time stamp into a FAT file system time stamp. - */ - uint32_t fatfs_time(const struct tm * timeptr); - - /** One hour, expressed in seconds */ -#define ONE_HOUR 3600 - - /** Angular degree, expressed in arc seconds */ -#define ONE_DEGREE 3600 - - /** One day, expressed in seconds */ -#define ONE_DAY 86400 - - /** Difference between the Y2K and the UNIX epochs, in seconds. To convert a Y2K - timestamp to UNIX... - \code - long unix; - time_t y2k; - - y2k = time(NULL); - unix = y2k + UNIX_OFFSET; - \endcode - */ -#define UNIX_OFFSET 946684800 - - /** Difference between the Y2K and the NTP epochs, in seconds. To convert a Y2K - timestamp to NTP... - \code - unsigned long ntp; - time_t y2k; - - y2k = time(NULL); - ntp = y2k + NTP_OFFSET; - \endcode - */ -#define NTP_OFFSET 3155673600 - - /* - * =================================================================== - * Ephemera - */ - - /** - Set the geographic coordinates of the 'observer', for use with several of the - following functions. Parameters are passed as seconds of North Latitude, and seconds - of East Longitude. - - For New York City... - \code set_position( 40.7142 * ONE_DEGREE, -74.0064 * ONE_DEGREE); \endcode - */ - void set_position(int32_t latitude, int32_t longitude); - - /** - Computes the difference between apparent solar time and mean solar time. - The returned value is in seconds. - */ - int16_t equation_of_time(const time_t * timer); - - /** - Computes the amount of time the sun is above the horizon, at the location of the observer. - - NOTE: At observer locations inside a polar circle, this value can be zero during the winter, - and can exceed ONE_DAY during the summer. - - The returned value is in seconds. - */ - int32_t daylight_seconds(const time_t * timer); - - /** - Computes the time of solar noon, at the location of the observer. - */ - time_t solar_noon(const time_t * timer); - - /** - Return the time of sunrise, at the location of the observer. See the note about daylight_seconds(). - */ - time_t sun_rise(const time_t * timer); - - /** - Return the time of sunset, at the location of the observer. See the note about daylight_seconds(). - */ - time_t sun_set(const time_t * timer); - - /** Returns the declination of the sun in radians. */ - double solar_declination(const time_t * timer); - - /** - Returns an approximation to the phase of the moon. - The sign of the returned value indicates a waning or waxing phase. - The magnitude of the returned value indicates the percentage illumination. - */ - int8_t moon_phase(const time_t * timer); - - /** - Returns Greenwich Mean Sidereal Time, as seconds into the sidereal day. - The returned value will range from 0 through 86399 seconds. - */ - unsigned long gm_sidereal(const time_t * timer); - - /** - Returns Local Mean Sidereal Time, as seconds into the sidereal day. - The returned value will range from 0 through 86399 seconds. - */ - unsigned long lm_sidereal(const time_t * timer); - - /* @} */ -#ifdef __cplusplus -} -#endif - -#endif /* TIME_H */ diff --git a/arduino/hardware/tools/avr/avr/include/unistd.h b/arduino/hardware/tools/avr/avr/include/unistd.h deleted file mode 100644 index c904e62..0000000 --- a/arduino/hardware/tools/avr/avr/include/unistd.h +++ /dev/null @@ -1,8 +0,0 @@ -#define __need_size_t -#include - -#include - -extern int write (int, const void *, size_t); -extern int read (int, void *, size_t); -off_t lseek (int, off_t, int); diff --git a/arduino/hardware/tools/avr/avr/include/util/atomic.h b/arduino/hardware/tools/avr/avr/include/util/atomic.h deleted file mode 100644 index fd76e86..0000000 --- a/arduino/hardware/tools/avr/avr/include/util/atomic.h +++ /dev/null @@ -1,308 +0,0 @@ -/* Copyright (c) 2007 Dean Camera - All rights reserved. - - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - * Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - * Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in - the documentation and/or other materials provided with the - distribution. - - * Neither the name of the copyright holders nor the names of - contributors may be used to endorse or promote products derived - from this software without specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. -*/ - -/* $Id$ */ - -#ifndef _UTIL_ATOMIC_H_ -#define _UTIL_ATOMIC_H_ 1 - -#include -#include - -#if !defined(__DOXYGEN__) -/* Internal helper functions. */ -static __inline__ uint8_t __iSeiRetVal(void) -{ - sei(); - return 1; -} - -static __inline__ uint8_t __iCliRetVal(void) -{ - cli(); - return 1; -} - -static __inline__ void __iSeiParam(const uint8_t *__s) -{ - sei(); - __asm__ volatile ("" ::: "memory"); - (void)__s; -} - -static __inline__ void __iCliParam(const uint8_t *__s) -{ - cli(); - __asm__ volatile ("" ::: "memory"); - (void)__s; -} - -static __inline__ void __iRestore(const uint8_t *__s) -{ - SREG = *__s; - __asm__ volatile ("" ::: "memory"); -} -#endif /* !__DOXYGEN__ */ - -/** \file */ -/** \defgroup util_atomic Atomically and Non-Atomically Executed Code Blocks - - \code - #include - \endcode - - \note The macros in this header file require the ISO/IEC 9899:1999 - ("ISO C99") feature of for loop variables that are declared inside - the for loop itself. For that reason, this header file can only - be used if the standard level of the compiler (option --std=) is - set to either \c c99 or \c gnu99. - - The macros in this header file deal with code blocks that are - guaranteed to be excuted Atomically or Non-Atmomically. The term - "Atomic" in this context refers to the unability of the respective - code to be interrupted. - - These macros operate via automatic manipulation of the Global - Interrupt Status (I) bit of the SREG register. Exit paths from - both block types are all managed automatically without the need - for special considerations, i. e. the interrupt status will be - restored to the same value it has been when entering the - respective block. - - A typical example that requires atomic access is a 16 (or more) - bit variable that is shared between the main execution path and an - ISR. While declaring such a variable as volatile ensures that the - compiler will not optimize accesses to it away, it does not - guarantee atomic access to it. Assuming the following example: - - \code -#include -#include -#include - -volatile uint16_t ctr; - -ISR(TIMER1_OVF_vect) -{ - ctr--; -} - -... -int -main(void) -{ - ... - ctr = 0x200; - start_timer(); - while (ctr != 0) - // wait - ; - ... -} - \endcode - - There is a chance where the main context will exit its wait loop - when the variable \c ctr just reached the value 0xFF. This happens - because the compiler cannot natively access a 16-bit variable - atomically in an 8-bit CPU. So the variable is for example at - 0x100, the compiler then tests the low byte for 0, which succeeds. - It then proceeds to test the high byte, but that moment the ISR - triggers, and the main context is interrupted. The ISR will - decrement the variable from 0x100 to 0xFF, and the main context - proceeds. It now tests the high byte of the variable which is - (now) also 0, so it concludes the variable has reached 0, and - terminates the loop. - - Using the macros from this header file, the above code can be - rewritten like: - - \code -#include -#include -#include -#include - -volatile uint16_t ctr; - -ISR(TIMER1_OVF_vect) -{ - ctr--; -} - -... -int -main(void) -{ - ... - ctr = 0x200; - start_timer(); - sei(); - uint16_t ctr_copy; - do - { - ATOMIC_BLOCK(ATOMIC_FORCEON) - { - ctr_copy = ctr; - } - } - while (ctr_copy != 0); - ... -} - \endcode - - This will install the appropriate interrupt protection before - accessing variable \c ctr, so it is guaranteed to be consistently - tested. If the global interrupt state were uncertain before - entering the ATOMIC_BLOCK, it should be executed with the - parameter ATOMIC_RESTORESTATE rather than ATOMIC_FORCEON. - - See \ref optim_code_reorder for things to be taken into account - with respect to compiler optimizations. -*/ - -/** \def ATOMIC_BLOCK(type) - \ingroup util_atomic - - Creates a block of code that is guaranteed to be executed - atomically. Upon entering the block the Global Interrupt Status - flag in SREG is disabled, and re-enabled upon exiting the block - from any exit path. - - Two possible macro parameters are permitted, ATOMIC_RESTORESTATE - and ATOMIC_FORCEON. -*/ -#if defined(__DOXYGEN__) -#define ATOMIC_BLOCK(type) -#else -#define ATOMIC_BLOCK(type) for ( type, __ToDo = __iCliRetVal(); \ - __ToDo ; __ToDo = 0 ) -#endif /* __DOXYGEN__ */ - -/** \def NONATOMIC_BLOCK(type) - \ingroup util_atomic - - Creates a block of code that is executed non-atomically. Upon - entering the block the Global Interrupt Status flag in SREG is - enabled, and disabled upon exiting the block from any exit - path. This is useful when nested inside ATOMIC_BLOCK sections, - allowing for non-atomic execution of small blocks of code while - maintaining the atomic access of the other sections of the parent - ATOMIC_BLOCK. - - Two possible macro parameters are permitted, - NONATOMIC_RESTORESTATE and NONATOMIC_FORCEOFF. -*/ -#if defined(__DOXYGEN__) -#define NONATOMIC_BLOCK(type) -#else -#define NONATOMIC_BLOCK(type) for ( type, __ToDo = __iSeiRetVal(); \ - __ToDo ; __ToDo = 0 ) -#endif /* __DOXYGEN__ */ - -/** \def ATOMIC_RESTORESTATE - \ingroup util_atomic - - This is a possible parameter for ATOMIC_BLOCK. When used, it will - cause the ATOMIC_BLOCK to restore the previous state of the SREG - register, saved before the Global Interrupt Status flag bit was - disabled. The net effect of this is to make the ATOMIC_BLOCK's - contents guaranteed atomic, without changing the state of the - Global Interrupt Status flag when execution of the block - completes. -*/ -#if defined(__DOXYGEN__) -#define ATOMIC_RESTORESTATE -#else -#define ATOMIC_RESTORESTATE uint8_t sreg_save \ - __attribute__((__cleanup__(__iRestore))) = SREG -#endif /* __DOXYGEN__ */ - -/** \def ATOMIC_FORCEON - \ingroup util_atomic - - This is a possible parameter for ATOMIC_BLOCK. When used, it will - cause the ATOMIC_BLOCK to force the state of the SREG register on - exit, enabling the Global Interrupt Status flag bit. This saves on - flash space as the previous value of the SREG register does not - need to be saved at the start of the block. - - Care should be taken that ATOMIC_FORCEON is only used when it is - known that interrupts are enabled before the block's execution or - when the side effects of enabling global interrupts at the block's - completion are known and understood. -*/ -#if defined(__DOXYGEN__) -#define ATOMIC_FORCEON -#else -#define ATOMIC_FORCEON uint8_t sreg_save \ - __attribute__((__cleanup__(__iSeiParam))) = 0 -#endif /* __DOXYGEN__ */ - -/** \def NONATOMIC_RESTORESTATE - \ingroup util_atomic - - This is a possible parameter for NONATOMIC_BLOCK. When used, it - will cause the NONATOMIC_BLOCK to restore the previous state of - the SREG register, saved before the Global Interrupt Status flag - bit was enabled. The net effect of this is to make the - NONATOMIC_BLOCK's contents guaranteed non-atomic, without changing - the state of the Global Interrupt Status flag when execution of - the block completes. -*/ -#if defined(__DOXYGEN__) -#define NONATOMIC_RESTORESTATE -#else -#define NONATOMIC_RESTORESTATE uint8_t sreg_save \ - __attribute__((__cleanup__(__iRestore))) = SREG -#endif /* __DOXYGEN__ */ - -/** \def NONATOMIC_FORCEOFF - \ingroup util_atomic - - This is a possible parameter for NONATOMIC_BLOCK. When used, it - will cause the NONATOMIC_BLOCK to force the state of the SREG - register on exit, disabling the Global Interrupt Status flag - bit. This saves on flash space as the previous value of the SREG - register does not need to be saved at the start of the block. - - Care should be taken that NONATOMIC_FORCEOFF is only used when it - is known that interrupts are disabled before the block's execution - or when the side effects of disabling global interrupts at the - block's completion are known and understood. -*/ -#if defined(__DOXYGEN__) -#define NONATOMIC_FORCEOFF -#else -#define NONATOMIC_FORCEOFF uint8_t sreg_save \ - __attribute__((__cleanup__(__iCliParam))) = 0 -#endif /* __DOXYGEN__ */ - -#endif diff --git a/arduino/hardware/tools/avr/avr/include/util/crc16.h b/arduino/hardware/tools/avr/avr/include/util/crc16.h deleted file mode 100644 index 630b6fc..0000000 --- a/arduino/hardware/tools/avr/avr/include/util/crc16.h +++ /dev/null @@ -1,403 +0,0 @@ -/* Copyright (c) 2002, 2003, 2004 Marek Michalkiewicz - Copyright (c) 2005, 2007 Joerg Wunsch - Copyright (c) 2013 Dave Hylands - Copyright (c) 2013 Frederic Nadeau - All rights reserved. - - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - * Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - * Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in - the documentation and/or other materials provided with the - distribution. - - * Neither the name of the copyright holders nor the names of - contributors may be used to endorse or promote products derived - from this software without specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. */ - -/* $Id$ */ - -#ifndef _UTIL_CRC16_H_ -#define _UTIL_CRC16_H_ - -#include - -/** \file */ -/** \defgroup util_crc : CRC Computations - \code#include \endcode - - This header file provides a optimized inline functions for calculating - cyclic redundancy checks (CRC) using common polynomials. - - \par References: - - \par - - See the Dallas Semiconductor app note 27 for 8051 assembler example and - general CRC optimization suggestions. The table on the last page of the - app note is the key to understanding these implementations. - - \par - - Jack Crenshaw's "Implementing CRCs" article in the January 1992 isue of \e - Embedded \e Systems \e Programming. This may be difficult to find, but it - explains CRC's in very clear and concise terms. Well worth the effort to - obtain a copy. - - A typical application would look like: - - \code - // Dallas iButton test vector. - uint8_t serno[] = { 0x02, 0x1c, 0xb8, 0x01, 0, 0, 0, 0xa2 }; - - int - checkcrc(void) - { - uint8_t crc = 0, i; - - for (i = 0; i < sizeof serno / sizeof serno[0]; i++) - crc = _crc_ibutton_update(crc, serno[i]); - - return crc; // must be 0 - } - \endcode -*/ - -/** \ingroup util_crc - Optimized CRC-16 calculation. - - Polynomial: x^16 + x^15 + x^2 + 1 (0xa001)
- Initial value: 0xffff - - This CRC is normally used in disk-drive controllers. - - The following is the equivalent functionality written in C. - - \code - uint16_t - crc16_update(uint16_t crc, uint8_t a) - { - int i; - - crc ^= a; - for (i = 0; i < 8; ++i) - { - if (crc & 1) - crc = (crc >> 1) ^ 0xA001; - else - crc = (crc >> 1); - } - - return crc; - } - - \endcode */ - -static __inline__ uint16_t -_crc16_update(uint16_t __crc, uint8_t __data) -{ - uint8_t __tmp; - uint16_t __ret; - - __asm__ __volatile__ ( - "eor %A0,%2" "\n\t" - "mov %1,%A0" "\n\t" - "swap %1" "\n\t" - "eor %1,%A0" "\n\t" - "mov __tmp_reg__,%1" "\n\t" - "lsr %1" "\n\t" - "lsr %1" "\n\t" - "eor %1,__tmp_reg__" "\n\t" - "mov __tmp_reg__,%1" "\n\t" - "lsr %1" "\n\t" - "eor %1,__tmp_reg__" "\n\t" - "andi %1,0x07" "\n\t" - "mov __tmp_reg__,%A0" "\n\t" - "mov %A0,%B0" "\n\t" - "lsr %1" "\n\t" - "ror __tmp_reg__" "\n\t" - "ror %1" "\n\t" - "mov %B0,__tmp_reg__" "\n\t" - "eor %A0,%1" "\n\t" - "lsr __tmp_reg__" "\n\t" - "ror %1" "\n\t" - "eor %B0,__tmp_reg__" "\n\t" - "eor %A0,%1" - : "=r" (__ret), "=d" (__tmp) - : "r" (__data), "0" (__crc) - : "r0" - ); - return __ret; -} - -/** \ingroup util_crc - Optimized CRC-XMODEM calculation. - - Polynomial: x^16 + x^12 + x^5 + 1 (0x1021)
- Initial value: 0x0 - - This is the CRC used by the Xmodem-CRC protocol. - - The following is the equivalent functionality written in C. - - \code - uint16_t - crc_xmodem_update (uint16_t crc, uint8_t data) - { - int i; - - crc = crc ^ ((uint16_t)data << 8); - for (i=0; i<8; i++) - { - if (crc & 0x8000) - crc = (crc << 1) ^ 0x1021; - else - crc <<= 1; - } - - return crc; - } - \endcode */ - -static __inline__ uint16_t -_crc_xmodem_update(uint16_t __crc, uint8_t __data) -{ - uint16_t __ret; /* %B0:%A0 (alias for __crc) */ - uint8_t __tmp1; /* %1 */ - uint8_t __tmp2; /* %2 */ - /* %3 __data */ - - __asm__ __volatile__ ( - "eor %B0,%3" "\n\t" /* crc.hi ^ data */ - "mov __tmp_reg__,%B0" "\n\t" - "swap __tmp_reg__" "\n\t" /* swap(crc.hi ^ data) */ - - /* Calculate the ret.lo of the CRC. */ - "mov %1,__tmp_reg__" "\n\t" - "andi %1,0x0f" "\n\t" - "eor %1,%B0" "\n\t" - "mov %2,%B0" "\n\t" - "eor %2,__tmp_reg__" "\n\t" - "lsl %2" "\n\t" - "andi %2,0xe0" "\n\t" - "eor %1,%2" "\n\t" /* __tmp1 is now ret.lo. */ - - /* Calculate the ret.hi of the CRC. */ - "mov %2,__tmp_reg__" "\n\t" - "eor %2,%B0" "\n\t" - "andi %2,0xf0" "\n\t" - "lsr %2" "\n\t" - "mov __tmp_reg__,%B0" "\n\t" - "lsl __tmp_reg__" "\n\t" - "rol %2" "\n\t" - "lsr %B0" "\n\t" - "lsr %B0" "\n\t" - "lsr %B0" "\n\t" - "andi %B0,0x1f" "\n\t" - "eor %B0,%2" "\n\t" - "eor %B0,%A0" "\n\t" /* ret.hi is now ready. */ - "mov %A0,%1" "\n\t" /* ret.lo is now ready. */ - : "=d" (__ret), "=d" (__tmp1), "=d" (__tmp2) - : "r" (__data), "0" (__crc) - : "r0" - ); - return __ret; -} - -/** \ingroup util_crc - Optimized CRC-CCITT calculation. - - Polynomial: x^16 + x^12 + x^5 + 1 (0x8408)
- Initial value: 0xffff - - This is the CRC used by PPP and IrDA. - - See RFC1171 (PPP protocol) and IrDA IrLAP 1.1 - - \note Although the CCITT polynomial is the same as that used by the Xmodem - protocol, they are quite different. The difference is in how the bits are - shifted through the alorgithm. Xmodem shifts the MSB of the CRC and the - input first, while CCITT shifts the LSB of the CRC and the input first. - - The following is the equivalent functionality written in C. - - \code - uint16_t - crc_ccitt_update (uint16_t crc, uint8_t data) - { - data ^= lo8 (crc); - data ^= data << 4; - - return ((((uint16_t)data << 8) | hi8 (crc)) ^ (uint8_t)(data >> 4) - ^ ((uint16_t)data << 3)); - } - \endcode */ - -static __inline__ uint16_t -_crc_ccitt_update (uint16_t __crc, uint8_t __data) -{ - uint16_t __ret; - - __asm__ __volatile__ ( - "eor %A0,%1" "\n\t" - - "mov __tmp_reg__,%A0" "\n\t" - "swap %A0" "\n\t" - "andi %A0,0xf0" "\n\t" - "eor %A0,__tmp_reg__" "\n\t" - - "mov __tmp_reg__,%B0" "\n\t" - - "mov %B0,%A0" "\n\t" - - "swap %A0" "\n\t" - "andi %A0,0x0f" "\n\t" - "eor __tmp_reg__,%A0" "\n\t" - - "lsr %A0" "\n\t" - "eor %B0,%A0" "\n\t" - - "eor %A0,%B0" "\n\t" - "lsl %A0" "\n\t" - "lsl %A0" "\n\t" - "lsl %A0" "\n\t" - "eor %A0,__tmp_reg__" - - : "=d" (__ret) - : "r" (__data), "0" (__crc) - : "r0" - ); - return __ret; -} - -/** \ingroup util_crc - Optimized Dallas (now Maxim) iButton 8-bit CRC calculation. - - Polynomial: x^8 + x^5 + x^4 + 1 (0x8C)
- Initial value: 0x0 - - See http://www.maxim-ic.com/appnotes.cfm/appnote_number/27 - - The following is the equivalent functionality written in C. - - \code - uint8_t - _crc_ibutton_update(uint8_t crc, uint8_t data) - { - uint8_t i; - - crc = crc ^ data; - for (i = 0; i < 8; i++) - { - if (crc & 0x01) - crc = (crc >> 1) ^ 0x8C; - else - crc >>= 1; - } - - return crc; - } - \endcode -*/ - -static __inline__ uint8_t -_crc_ibutton_update(uint8_t __crc, uint8_t __data) -{ - uint8_t __i, __pattern; - __asm__ __volatile__ ( - " eor %0, %4" "\n\t" - " ldi %1, 8" "\n\t" - " ldi %2, 0x8C" "\n\t" - "1: lsr %0" "\n\t" - " brcc 2f" "\n\t" - " eor %0, %2" "\n\t" - "2: dec %1" "\n\t" - " brne 1b" "\n\t" - : "=r" (__crc), "=d" (__i), "=d" (__pattern) - : "0" (__crc), "r" (__data)); - return __crc; -} - -/** \ingroup util_crc - Optimized CRC-8-CCITT calculation. - - Polynomial: x^8 + x^2 + x + 1 (0xE0)
- - For use with simple CRC-8
- Initial value: 0x0 - - For use with CRC-8-ROHC
- Initial value: 0xff
- Reference: http://tools.ietf.org/html/rfc3095#section-5.9.1 - - For use with CRC-8-ATM/ITU
- Initial value: 0xff
- Final XOR value: 0x55
- Reference: http://www.itu.int/rec/T-REC-I.432.1-199902-I/en - - The C equivalent has been originally written by Dave Hylands. - Assembly code is based on _crc_ibutton_update optimization. - - The following is the equivalent functionality written in C. - - \code - uint8_t - _crc8_ccitt_update (uint8_t inCrc, uint8_t inData) - { - uint8_t i; - uint8_t data; - - data = inCrc ^ inData; - - for ( i = 0; i < 8; i++ ) - { - if (( data & 0x80 ) != 0 ) - { - data <<= 1; - data ^= 0x07; - } - else - { - data <<= 1; - } - } - return data; - } - \endcode -*/ - -static __inline__ uint8_t -_crc8_ccitt_update(uint8_t __crc, uint8_t __data) -{ - uint8_t __i, __pattern; - __asm__ __volatile__ ( - " eor %0, %4" "\n\t" - " ldi %1, 8" "\n\t" - " ldi %2, 0x07" "\n\t" - "1: lsl %0" "\n\t" - " brcc 2f" "\n\t" - " eor %0, %2" "\n\t" - "2: dec %1" "\n\t" - " brne 1b" "\n\t" - : "=r" (__crc), "=d" (__i), "=d" (__pattern) - : "0" (__crc), "r" (__data)); - return __crc; -} - -#endif /* _UTIL_CRC16_H_ */ diff --git a/arduino/hardware/tools/avr/avr/include/util/delay.h b/arduino/hardware/tools/avr/avr/include/util/delay.h deleted file mode 100644 index 6313536..0000000 --- a/arduino/hardware/tools/avr/avr/include/util/delay.h +++ /dev/null @@ -1,302 +0,0 @@ -/* Copyright (c) 2002, Marek Michalkiewicz - Copyright (c) 2004,2005,2007 Joerg Wunsch - Copyright (c) 2007 Florin-Viorel Petrov - All rights reserved. - - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - * Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - * Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in - the documentation and/or other materials provided with the - distribution. - - * Neither the name of the copyright holders nor the names of - contributors may be used to endorse or promote products derived - from this software without specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. */ - -/* $Id$ */ - -#ifndef _UTIL_DELAY_H_ -#define _UTIL_DELAY_H_ 1 - -#ifndef __DOXYGEN__ -# ifndef __HAS_DELAY_CYCLES -# define __HAS_DELAY_CYCLES 1 -# endif -#endif /* __DOXYGEN__ */ - -#include -#include -#include - -/** \file */ -/** \defgroup util_delay : Convenience functions for busy-wait delay loops - \code - #define F_CPU 1000000UL // 1 MHz - //#define F_CPU 14.7456E6 - #include - \endcode - - \note As an alternative method, it is possible to pass the - F_CPU macro down to the compiler from the Makefile. - Obviously, in that case, no \c \#define statement should be - used. - - The functions in this header file are wrappers around the basic - busy-wait functions from . They are meant as - convenience functions where actual time values can be specified - rather than a number of cycles to wait for. The idea behind is - that compile-time constant expressions will be eliminated by - compiler optimization so floating-point expressions can be used - to calculate the number of delay cycles needed based on the CPU - frequency passed by the macro F_CPU. - - \note In order for these functions to work as intended, compiler - optimizations must be enabled, and the delay time - must be an expression that is a known constant at - compile-time. If these requirements are not met, the resulting - delay will be much longer (and basically unpredictable), and - applications that otherwise do not use floating-point calculations - will experience severe code bloat by the floating-point library - routines linked into the application. - - The functions available allow the specification of microsecond, and - millisecond delays directly, using the application-supplied macro - F_CPU as the CPU clock frequency (in Hertz). - -*/ - -#if !defined(__DOXYGEN__) -static __inline__ void _delay_us(double __us) __attribute__((__always_inline__)); -static __inline__ void _delay_ms(double __ms) __attribute__((__always_inline__)); -#endif - -#ifndef F_CPU -/* prevent compiler error by supplying a default */ -# warning "F_CPU not defined for " -/** \ingroup util_delay - \def F_CPU - \brief CPU frequency in Hz - - The macro F_CPU specifies the CPU frequency to be considered by - the delay macros. This macro is normally supplied by the - environment (e.g. from within a project header, or the project's - Makefile). The value 1 MHz here is only provided as a "vanilla" - fallback if no such user-provided definition could be found. - - In terms of the delay functions, the CPU frequency can be given as - a floating-point constant (e.g. 3.6864E6 for 3.6864 MHz). - However, the macros in require it to be an - integer value. - */ -# define F_CPU 1000000UL -#endif - -#ifndef __OPTIMIZE__ -# warning "Compiler optimizations disabled; functions from won't work as designed" -#endif - -#if __HAS_DELAY_CYCLES && defined(__OPTIMIZE__) && \ - !defined(__DELAY_BACKWARD_COMPATIBLE__) && \ - __STDC_HOSTED__ -# include -#endif - -/** - \ingroup util_delay - - Perform a delay of \c __ms milliseconds, using _delay_loop_2(). - - The macro F_CPU is supposed to be defined to a - constant defining the CPU clock frequency (in Hertz). - - The maximal possible delay is 262.14 ms / F_CPU in MHz. - - When the user request delay which exceed the maximum possible one, - _delay_ms() provides a decreased resolution functionality. In this - mode _delay_ms() will work with a resolution of 1/10 ms, providing - delays up to 6.5535 seconds (independent from CPU frequency). The - user will not be informed about decreased resolution. - - If the avr-gcc toolchain has __builtin_avr_delay_cycles() - support, maximal possible delay is 4294967.295 ms/ F_CPU in MHz. For - values greater than the maximal possible delay, overflows results in - no delay i.e., 0ms. - - Conversion of \c __ms into clock cycles may not always result in - integer. By default, the clock cycles rounded up to next - integer. This ensures that the user gets at least \c __ms - microseconds of delay. - - Alternatively, by defining the macro \c __DELAY_ROUND_DOWN__, or - \c __DELAY_ROUND_CLOSEST__, before including this header file, the - algorithm can be made to round down, or round to closest integer, - respectively. - - \note - - The implementation of _delay_ms() based on - __builtin_avr_delay_cycles() is not backward compatible with older - implementations. In order to get functionality backward compatible - with previous versions, the macro \c "__DELAY_BACKWARD_COMPATIBLE__" - must be defined before including this header file. Also, the - backward compatible algorithm will be chosen if the code is - compiled in a freestanding environment (GCC option - \c -ffreestanding), as the math functions required for rounding are - not available to the compiler then. - - */ -void -_delay_ms(double __ms) -{ - double __tmp ; -#if __HAS_DELAY_CYCLES && defined(__OPTIMIZE__) && \ - !defined(__DELAY_BACKWARD_COMPATIBLE__) && \ - __STDC_HOSTED__ - uint32_t __ticks_dc; - extern void __builtin_avr_delay_cycles(unsigned long); - __tmp = ((F_CPU) / 1e3) * __ms; - - #if defined(__DELAY_ROUND_DOWN__) - __ticks_dc = (uint32_t)fabs(__tmp); - - #elif defined(__DELAY_ROUND_CLOSEST__) - __ticks_dc = (uint32_t)(fabs(__tmp)+0.5); - - #else - //round up by default - __ticks_dc = (uint32_t)(ceil(fabs(__tmp))); - #endif - - __builtin_avr_delay_cycles(__ticks_dc); - -#else - uint16_t __ticks; - __tmp = ((F_CPU) / 4e3) * __ms; - if (__tmp < 1.0) - __ticks = 1; - else if (__tmp > 65535) - { - // __ticks = requested delay in 1/10 ms - __ticks = (uint16_t) (__ms * 10.0); - while(__ticks) - { - // wait 1/10 ms - _delay_loop_2(((F_CPU) / 4e3) / 10); - __ticks --; - } - return; - } - else - __ticks = (uint16_t)__tmp; - _delay_loop_2(__ticks); -#endif -} - -/** - \ingroup util_delay - - Perform a delay of \c __us microseconds, using _delay_loop_1(). - - The macro F_CPU is supposed to be defined to a - constant defining the CPU clock frequency (in Hertz). - - The maximal possible delay is 768 us / F_CPU in MHz. - - If the user requests a delay greater than the maximal possible one, - _delay_us() will automatically call _delay_ms() instead. The user - will not be informed about this case. - - If the avr-gcc toolchain has __builtin_avr_delay_cycles() - support, maximal possible delay is 4294967.295 us/ F_CPU in MHz. For - values greater than the maximal possible delay, overflow results in - no delay i.e., 0us. - - Conversion of \c __us into clock cycles may not always result in - integer. By default, the clock cycles rounded up to next - integer. This ensures that the user gets at least \c __us - microseconds of delay. - - Alternatively, by defining the macro \c __DELAY_ROUND_DOWN__, or - \c __DELAY_ROUND_CLOSEST__, before including this header file, the - algorithm can be made to round down, or round to closest integer, - respectively. - - \note - - The implementation of _delay_ms() based on - __builtin_avr_delay_cycles() is not backward compatible with older - implementations. In order to get functionality backward compatible - with previous versions, the macro \c __DELAY_BACKWARD_COMPATIBLE__ - must be defined before including this header file. Also, the - backward compatible algorithm will be chosen if the code is - compiled in a freestanding environment (GCC option - \c -ffreestanding), as the math functions required for rounding are - not available to the compiler then. - - */ -void -_delay_us(double __us) -{ - double __tmp ; -#if __HAS_DELAY_CYCLES && defined(__OPTIMIZE__) && \ - !defined(__DELAY_BACKWARD_COMPATIBLE__) && \ - __STDC_HOSTED__ - uint32_t __ticks_dc; - extern void __builtin_avr_delay_cycles(unsigned long); - __tmp = ((F_CPU) / 1e6) * __us; - - #if defined(__DELAY_ROUND_DOWN__) - __ticks_dc = (uint32_t)fabs(__tmp); - - #elif defined(__DELAY_ROUND_CLOSEST__) - __ticks_dc = (uint32_t)(fabs(__tmp)+0.5); - - #else - //round up by default - __ticks_dc = (uint32_t)(ceil(fabs(__tmp))); - #endif - - __builtin_avr_delay_cycles(__ticks_dc); - -#else - uint8_t __ticks; - double __tmp2 ; - __tmp = ((F_CPU) / 3e6) * __us; - __tmp2 = ((F_CPU) / 4e6) * __us; - if (__tmp < 1.0) - __ticks = 1; - else if (__tmp2 > 65535) - { - _delay_ms(__us / 1000.0); - } - else if (__tmp > 255) - { - uint16_t __ticks=(uint16_t)__tmp2; - _delay_loop_2(__ticks); - return; - } - else - __ticks = (uint8_t)__tmp; - _delay_loop_1(__ticks); -#endif -} - - -#endif /* _UTIL_DELAY_H_ */ diff --git a/arduino/hardware/tools/avr/avr/include/util/delay_basic.h b/arduino/hardware/tools/avr/avr/include/util/delay_basic.h deleted file mode 100644 index 9bf1e45..0000000 --- a/arduino/hardware/tools/avr/avr/include/util/delay_basic.h +++ /dev/null @@ -1,113 +0,0 @@ -/* Copyright (c) 2002, Marek Michalkiewicz - Copyright (c) 2007 Joerg Wunsch - All rights reserved. - - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - * Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - * Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in - the documentation and/or other materials provided with the - distribution. - - * Neither the name of the copyright holders nor the names of - contributors may be used to endorse or promote products derived - from this software without specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. */ - -/* $Id$ */ - -#ifndef _UTIL_DELAY_BASIC_H_ -#define _UTIL_DELAY_BASIC_H_ 1 - -#include - -#if !defined(__DOXYGEN__) -static __inline__ void _delay_loop_1(uint8_t __count) __attribute__((__always_inline__)); -static __inline__ void _delay_loop_2(uint16_t __count) __attribute__((__always_inline__)); -#endif - -/** \file */ -/** \defgroup util_delay_basic : Basic busy-wait delay loops - \code - #include - \endcode - - The functions in this header file implement simple delay loops - that perform a busy-waiting. They are typically used to - facilitate short delays in the program execution. They are - implemented as count-down loops with a well-known CPU cycle - count per loop iteration. As such, no other processing can - occur simultaneously. It should be kept in mind that the - functions described here do not disable interrupts. - - In general, for long delays, the use of hardware timers is - much preferrable, as they free the CPU, and allow for - concurrent processing of other events while the timer is - running. However, in particular for very short delays, the - overhead of setting up a hardware timer is too much compared - to the overall delay time. - - Two inline functions are provided for the actual delay algorithms. - -*/ - -/** \ingroup util_delay_basic - - Delay loop using an 8-bit counter \c __count, so up to 256 - iterations are possible. (The value 256 would have to be passed - as 0.) The loop executes three CPU cycles per iteration, not - including the overhead the compiler needs to setup the counter - register. - - Thus, at a CPU speed of 1 MHz, delays of up to 768 microseconds - can be achieved. -*/ -void -_delay_loop_1(uint8_t __count) -{ - __asm__ volatile ( - "1: dec %0" "\n\t" - "brne 1b" - : "=r" (__count) - : "0" (__count) - ); -} - -/** \ingroup util_delay_basic - - Delay loop using a 16-bit counter \c __count, so up to 65536 - iterations are possible. (The value 65536 would have to be - passed as 0.) The loop executes four CPU cycles per iteration, - not including the overhead the compiler requires to setup the - counter register pair. - - Thus, at a CPU speed of 1 MHz, delays of up to about 262.1 - milliseconds can be achieved. - */ -void -_delay_loop_2(uint16_t __count) -{ - __asm__ volatile ( - "1: sbiw %0,1" "\n\t" - "brne 1b" - : "=w" (__count) - : "0" (__count) - ); -} - -#endif /* _UTIL_DELAY_BASIC_H_ */ diff --git a/arduino/hardware/tools/avr/avr/include/util/eu_dst.h b/arduino/hardware/tools/avr/avr/include/util/eu_dst.h deleted file mode 100644 index eee7f61..0000000 --- a/arduino/hardware/tools/avr/avr/include/util/eu_dst.h +++ /dev/null @@ -1,116 +0,0 @@ -/* - * (c)2012 Michael Duane Rice All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: - * - * Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. Redistributions in binary - * form must reproduce the above copyright notice, this list of conditions - * and the following disclaimer in the documentation and/or other materials - * provided with the distribution. Neither the name of the copyright holders - * nor the names of contributors may be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ - -/* $Id$ */ - -/** - Daylight Saving function for the European Union. To utilize this function, you must - \code #include \endcode - and - \code set_dst(eu_dst); \endcode - - Given the time stamp and time zone parameters provided, the Daylight Saving function must - return a value appropriate for the tm structures' tm_isdst element. That is... - - 0 : If Daylight Saving is not in effect. - - -1 : If it cannot be determined if Daylight Saving is in effect. - - A positive integer : Represents the number of seconds a clock is advanced for Daylight Saving. - This will typically be ONE_HOUR. - - Daylight Saving 'rules' are subject to frequent change. For production applications it is - recommended to write your own DST function, which uses 'rules' obtained from, and modifiable by, - the end user ( perhaps stored in EEPROM ). -*/ - -#ifndef EU_DST_H -#define EU_DST_H - -#ifdef __cplusplus -extern "C" { -#endif - -#include -#include - - int eu_dst(const time_t * timer, int32_t * z) { - struct tm tmptr; - uint8_t month, mday, hour, day_of_week, d; - int n; - - /* obtain the variables */ - gmtime_r(timer, &tmptr); - month = tmptr.tm_mon; - day_of_week = tmptr.tm_wday; - mday = tmptr.tm_mday - 1; - hour = tmptr.tm_hour; - - if ((month > MARCH) && (month < OCTOBER)) - return ONE_HOUR; - - if (month < MARCH) - return 0; - if (month > OCTOBER) - return 0; - - /* determine mday of last Sunday */ - n = tmptr.tm_mday - 1; - n -= day_of_week; - n += 7; - d = n % 7; /* date of first Sunday */ - - n = 31 - d; - n /= 7; /* number of Sundays left in the month */ - - d = d + 7 * n; /* mday of final Sunday */ - - if (month == MARCH) { - if (d < mday) - return 0; - if (d > mday) - return ONE_HOUR; - if (hour < 2) - return 0; - return ONE_HOUR; - } - if (d < mday) - return ONE_HOUR; - if (d > mday) - return 0; - if (hour < 2) - return ONE_HOUR; - return 0; - - } - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/arduino/hardware/tools/avr/avr/include/util/parity.h b/arduino/hardware/tools/avr/avr/include/util/parity.h deleted file mode 100644 index b28813e..0000000 --- a/arduino/hardware/tools/avr/avr/include/util/parity.h +++ /dev/null @@ -1,65 +0,0 @@ -/* Copyright (c) 2002, Marek Michalkiewicz - Copyright (c) 2004,2005,2007 Joerg Wunsch - All rights reserved. - - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - * Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - * Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in - the documentation and/or other materials provided with the - distribution. - - * Neither the name of the copyright holders nor the names of - contributors may be used to endorse or promote products derived - from this software without specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. */ - -/* $Id$ */ - -#ifndef _UTIL_PARITY_H_ -#define _UTIL_PARITY_H_ - -/** \file */ -/** \defgroup util_parity : Parity bit generation - \code #include \endcode - - This header file contains optimized assembler code to calculate - the parity bit for a byte. -*/ -/** \def parity_even_bit - \ingroup util_parity - \returns 1 if \c val has an odd number of bits set. */ -#define parity_even_bit(val) \ -(__extension__({ \ - unsigned char __t; \ - __asm__ ( \ - "mov __tmp_reg__,%0" "\n\t" \ - "swap %0" "\n\t" \ - "eor %0,__tmp_reg__" "\n\t" \ - "mov __tmp_reg__,%0" "\n\t" \ - "lsr %0" "\n\t" \ - "lsr %0" "\n\t" \ - "eor %0,__tmp_reg__" \ - : "=r" (__t) \ - : "0" ((unsigned char)(val)) \ - : "r0" \ - ); \ - (((__t + 1) >> 1) & 1); \ - })) - -#endif /* _UTIL_PARITY_H_ */ diff --git a/arduino/hardware/tools/avr/avr/include/util/setbaud.h b/arduino/hardware/tools/avr/avr/include/util/setbaud.h deleted file mode 100644 index c774638..0000000 --- a/arduino/hardware/tools/avr/avr/include/util/setbaud.h +++ /dev/null @@ -1,243 +0,0 @@ -/* Copyright (c) 2007 Cliff Lawson - Copyright (c) 2007 Carlos Lamas - All rights reserved. - - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - * Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - * Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in - the documentation and/or other materials provided with the - distribution. - - * Neither the name of the copyright holders nor the names of - contributors may be used to endorse or promote products derived - from this software without specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. */ - -/* $Id$ */ - -/** - \file -*/ - -/** - \defgroup util_setbaud : Helper macros for baud rate calculations - \code - #define F_CPU 11059200 - #define BAUD 38400 - #include - \endcode - - This header file requires that on entry values are already defined - for F_CPU and BAUD. In addition, the macro BAUD_TOL will define - the baud rate tolerance (in percent) that is acceptable during - the calculations. The value of BAUD_TOL will default to 2 %. - - This header file defines macros suitable to setup the UART baud - rate prescaler registers of an AVR. All calculations are done - using the C preprocessor. Including this header file causes no - other side effects so it is possible to include this file more than - once (supposedly, with different values for the BAUD parameter), - possibly even within the same function. - - Assuming that the requested BAUD is valid for the given F_CPU then - the macro UBRR_VALUE is set to the required prescaler value. Two - additional macros are provided for the low and high bytes of the - prescaler, respectively: UBRRL_VALUE is set to the lower byte of - the UBRR_VALUE and UBRRH_VALUE is set to the upper byte. An - additional macro USE_2X will be defined. Its value is set to 1 if - the desired BAUD rate within the given tolerance could only be - achieved by setting the U2X bit in the UART configuration. It will - be defined to 0 if U2X is not needed. - - Example usage: - - \code - #include - - #define F_CPU 4000000 - - static void - uart_9600(void) - { - #define BAUD 9600 - #include - UBRRH = UBRRH_VALUE; - UBRRL = UBRRL_VALUE; - #if USE_2X - UCSRA |= (1 << U2X); - #else - UCSRA &= ~(1 << U2X); - #endif - } - - static void - uart_38400(void) - { - #undef BAUD // avoid compiler warning - #define BAUD 38400 - #include - UBRRH = UBRRH_VALUE; - UBRRL = UBRRL_VALUE; - #if USE_2X - UCSRA |= (1 << U2X); - #else - UCSRA &= ~(1 << U2X); - #endif - } - \endcode - - In this example, two functions are defined to setup the UART - to run at 9600 Bd, and 38400 Bd, respectively. Using a CPU - clock of 4 MHz, 9600 Bd can be achieved with an acceptable - tolerance without setting U2X (prescaler 25), while 38400 Bd - require U2X to be set (prescaler 12). -*/ - -#ifndef F_CPU -# error "setbaud.h requires F_CPU to be defined" -#endif - -#ifndef BAUD -# error "setbaud.h requires BAUD to be defined" -#endif - -#if !(F_CPU) -# error "F_CPU must be a constant value" -#endif - -#if !(BAUD) -# error "BAUD must be a constant value" -#endif - -#if defined(__DOXYGEN__) -/** - \def BAUD_TOL - \ingroup util_setbaud - - Input and output macro for - - Define the acceptable baud rate tolerance in percent. If not set - on entry, it will be set to its default value of 2. -*/ -#define BAUD_TOL 2 - -/** - \def UBRR_VALUE - \ingroup util_setbaud - - Output macro from - - Contains the calculated baud rate prescaler value for the UBRR - register. -*/ -#define UBRR_VALUE - -/** - \def UBRRL_VALUE - \ingroup util_setbaud - - Output macro from - - Contains the lower byte of the calculated prescaler value - (UBRR_VALUE). -*/ -#define UBRRL_VALUE - -/** - \def UBRRH_VALUE - \ingroup util_setbaud - - Output macro from - - Contains the upper byte of the calculated prescaler value - (UBRR_VALUE). -*/ -#define UBRRH_VALUE - -/** - \def USE_2X - \ingroup util_setbaud - - Output macro from - - Contains the value 1 if the desired baud rate tolerance could only - be achieved by setting the U2X bit in the UART configuration. - Contains 0 otherwise. -*/ -#define USE_2X 0 - -#else /* !__DOXYGEN__ */ - -#undef USE_2X - -/* Baud rate tolerance is 2 % unless previously defined */ -#ifndef BAUD_TOL -# define BAUD_TOL 2 -#endif - -#ifdef __ASSEMBLER__ -#define UBRR_VALUE (((F_CPU) + 8 * (BAUD)) / (16 * (BAUD)) -1) -#else -#define UBRR_VALUE (((F_CPU) + 8UL * (BAUD)) / (16UL * (BAUD)) -1UL) -#endif - -#if 100 * (F_CPU) > \ - (16 * ((UBRR_VALUE) + 1)) * (100 * (BAUD) + (BAUD) * (BAUD_TOL)) -# define USE_2X 1 -#elif 100 * (F_CPU) < \ - (16 * ((UBRR_VALUE) + 1)) * (100 * (BAUD) - (BAUD) * (BAUD_TOL)) -# define USE_2X 1 -#else -# define USE_2X 0 -#endif - -#if USE_2X -/* U2X required, recalculate */ -#undef UBRR_VALUE - -#ifdef __ASSEMBLER__ -#define UBRR_VALUE (((F_CPU) + 4 * (BAUD)) / (8 * (BAUD)) -1) -#else -#define UBRR_VALUE (((F_CPU) + 4UL * (BAUD)) / (8UL * (BAUD)) -1UL) -#endif - -#if 100 * (F_CPU) > \ - (8 * ((UBRR_VALUE) + 1)) * (100 * (BAUD) + (BAUD) * (BAUD_TOL)) -# warning "Baud rate achieved is higher than allowed" -#endif - -#if 100 * (F_CPU) < \ - (8 * ((UBRR_VALUE) + 1)) * (100 * (BAUD) - (BAUD) * (BAUD_TOL)) -# warning "Baud rate achieved is lower than allowed" -#endif - -#endif /* USE_U2X */ - -#ifdef UBRR_VALUE - /* Check for overflow */ -# if UBRR_VALUE >= (1 << 12) -# warning "UBRR value overflow" -# endif - -# define UBRRL_VALUE (UBRR_VALUE & 0xff) -# define UBRRH_VALUE (UBRR_VALUE >> 8) -#endif - -#endif /* __DOXYGEN__ */ -/* end of util/setbaud.h */ diff --git a/arduino/hardware/tools/avr/avr/include/util/twi.h b/arduino/hardware/tools/avr/avr/include/util/twi.h deleted file mode 100644 index 14bc830..0000000 --- a/arduino/hardware/tools/avr/avr/include/util/twi.h +++ /dev/null @@ -1,237 +0,0 @@ -/* Copyright (c) 2002, Marek Michalkiewicz - Copyright (c) 2005, 2007 Joerg Wunsch - All rights reserved. - - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - * Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - * Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in - the documentation and/or other materials provided with the - distribution. - - * Neither the name of the copyright holders nor the names of - contributors may be used to endorse or promote products derived - from this software without specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. */ - -/* $Id$ */ -/* copied from: Id: avr/twi.h,v 1.4 2004/11/01 21:19:54 arcanum Exp */ - -#ifndef _UTIL_TWI_H_ -#define _UTIL_TWI_H_ 1 - -#include - -/** \file */ -/** \defgroup util_twi : TWI bit mask definitions - \code #include \endcode - - This header file contains bit mask definitions for use with - the AVR TWI interface. -*/ -/** \name TWSR values - - Mnemonics: -
TW_MT_xxx - master transmitter -
TW_MR_xxx - master receiver -
TW_ST_xxx - slave transmitter -
TW_SR_xxx - slave receiver - */ - -/*@{*/ -/* Master */ -/** \ingroup util_twi - \def TW_START - start condition transmitted */ -#define TW_START 0x08 - -/** \ingroup util_twi - \def TW_REP_START - repeated start condition transmitted */ -#define TW_REP_START 0x10 - -/* Master Transmitter */ -/** \ingroup util_twi - \def TW_MT_SLA_ACK - SLA+W transmitted, ACK received */ -#define TW_MT_SLA_ACK 0x18 - -/** \ingroup util_twi - \def TW_MT_SLA_NACK - SLA+W transmitted, NACK received */ -#define TW_MT_SLA_NACK 0x20 - -/** \ingroup util_twi - \def TW_MT_DATA_ACK - data transmitted, ACK received */ -#define TW_MT_DATA_ACK 0x28 - -/** \ingroup util_twi - \def TW_MT_DATA_NACK - data transmitted, NACK received */ -#define TW_MT_DATA_NACK 0x30 - -/** \ingroup util_twi - \def TW_MT_ARB_LOST - arbitration lost in SLA+W or data */ -#define TW_MT_ARB_LOST 0x38 - -/* Master Receiver */ -/** \ingroup util_twi - \def TW_MR_ARB_LOST - arbitration lost in SLA+R or NACK */ -#define TW_MR_ARB_LOST 0x38 - -/** \ingroup util_twi - \def TW_MR_SLA_ACK - SLA+R transmitted, ACK received */ -#define TW_MR_SLA_ACK 0x40 - -/** \ingroup util_twi - \def TW_MR_SLA_NACK - SLA+R transmitted, NACK received */ -#define TW_MR_SLA_NACK 0x48 - -/** \ingroup util_twi - \def TW_MR_DATA_ACK - data received, ACK returned */ -#define TW_MR_DATA_ACK 0x50 - -/** \ingroup util_twi - \def TW_MR_DATA_NACK - data received, NACK returned */ -#define TW_MR_DATA_NACK 0x58 - -/* Slave Transmitter */ -/** \ingroup util_twi - \def TW_ST_SLA_ACK - SLA+R received, ACK returned */ -#define TW_ST_SLA_ACK 0xA8 - -/** \ingroup util_twi - \def TW_ST_ARB_LOST_SLA_ACK - arbitration lost in SLA+RW, SLA+R received, ACK returned */ -#define TW_ST_ARB_LOST_SLA_ACK 0xB0 - -/** \ingroup util_twi - \def TW_ST_DATA_ACK - data transmitted, ACK received */ -#define TW_ST_DATA_ACK 0xB8 - -/** \ingroup util_twi - \def TW_ST_DATA_NACK - data transmitted, NACK received */ -#define TW_ST_DATA_NACK 0xC0 - -/** \ingroup util_twi - \def TW_ST_LAST_DATA - last data byte transmitted, ACK received */ -#define TW_ST_LAST_DATA 0xC8 - -/* Slave Receiver */ -/** \ingroup util_twi - \def TW_SR_SLA_ACK - SLA+W received, ACK returned */ -#define TW_SR_SLA_ACK 0x60 - -/** \ingroup util_twi - \def TW_SR_ARB_LOST_SLA_ACK - arbitration lost in SLA+RW, SLA+W received, ACK returned */ -#define TW_SR_ARB_LOST_SLA_ACK 0x68 - -/** \ingroup util_twi - \def TW_SR_GCALL_ACK - general call received, ACK returned */ -#define TW_SR_GCALL_ACK 0x70 - -/** \ingroup util_twi - \def TW_SR_ARB_LOST_GCALL_ACK - arbitration lost in SLA+RW, general call received, ACK returned */ -#define TW_SR_ARB_LOST_GCALL_ACK 0x78 - -/** \ingroup util_twi - \def TW_SR_DATA_ACK - data received, ACK returned */ -#define TW_SR_DATA_ACK 0x80 - -/** \ingroup util_twi - \def TW_SR_DATA_NACK - data received, NACK returned */ -#define TW_SR_DATA_NACK 0x88 - -/** \ingroup util_twi - \def TW_SR_GCALL_DATA_ACK - general call data received, ACK returned */ -#define TW_SR_GCALL_DATA_ACK 0x90 - -/** \ingroup util_twi - \def TW_SR_GCALL_DATA_NACK - general call data received, NACK returned */ -#define TW_SR_GCALL_DATA_NACK 0x98 - -/** \ingroup util_twi - \def TW_SR_STOP - stop or repeated start condition received while selected */ -#define TW_SR_STOP 0xA0 - -/* Misc */ -/** \ingroup util_twi - \def TW_NO_INFO - no state information available */ -#define TW_NO_INFO 0xF8 - -/** \ingroup util_twi - \def TW_BUS_ERROR - illegal start or stop condition */ -#define TW_BUS_ERROR 0x00 - - -/** - * \ingroup util_twi - * \def TW_STATUS_MASK - * The lower 3 bits of TWSR are reserved on the ATmega163. - * The 2 LSB carry the prescaler bits on the newer ATmegas. - */ -#define TW_STATUS_MASK (_BV(TWS7)|_BV(TWS6)|_BV(TWS5)|_BV(TWS4)|\ - _BV(TWS3)) -/** - * \ingroup util_twi - * \def TW_STATUS - * - * TWSR, masked by TW_STATUS_MASK - */ -#define TW_STATUS (TWSR & TW_STATUS_MASK) -/*@}*/ - -/** - * \name R/~W bit in SLA+R/W address field. - */ - -/*@{*/ -/** \ingroup util_twi - \def TW_READ - SLA+R address */ -#define TW_READ 1 - -/** \ingroup util_twi - \def TW_WRITE - SLA+W address */ -#define TW_WRITE 0 -/*@}*/ - -#endif /* _UTIL_TWI_H_ */ diff --git a/arduino/hardware/tools/avr/avr/include/util/usa_dst.h b/arduino/hardware/tools/avr/avr/include/util/usa_dst.h deleted file mode 100644 index bf21656..0000000 --- a/arduino/hardware/tools/avr/avr/include/util/usa_dst.h +++ /dev/null @@ -1,130 +0,0 @@ -/* - * (c)2012 Michael Duane Rice All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: - * - * Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. Redistributions in binary - * form must reproduce the above copyright notice, this list of conditions - * and the following disclaimer in the documentation and/or other materials - * provided with the distribution. Neither the name of the copyright holders - * nor the names of contributors may be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ - -/* $Id$ */ - -/** - Daylight Saving function for the USA. To utilize this function, you must - \code #include \endcode - and - \code set_dst(usa_dst); \endcode - - Given the time stamp and time zone parameters provided, the Daylight Saving function must - return a value appropriate for the tm structures' tm_isdst element. That is... - - 0 : If Daylight Saving is not in effect. - - -1 : If it cannot be determined if Daylight Saving is in effect. - - A positive integer : Represents the number of seconds a clock is advanced for Daylight Saving. - This will typically be ONE_HOUR. - - Daylight Saving 'rules' are subject to frequent change. For production applications it is - recommended to write your own DST function, which uses 'rules' obtained from, and modifiable by, - the end user ( perhaps stored in EEPROM ). - -*/ - -#ifndef USA_DST_H -#define USA_DST_H - -#ifdef __cplusplus -extern "C" { -#endif - -#include -#include - -#ifndef DST_START_MONTH -#define DST_START_MONTH MARCH -#endif - -#ifndef DST_END_MONTH -#define DST_END_MONTH NOVEMBER -#endif - -#ifndef DST_START_WEEK -#define DST_START_WEEK 2 -#endif - -#ifndef DST_END_WEEK -#define DST_END_WEEK 1 -#endif - - int usa_dst(const time_t * timer, int32_t * z) { - time_t t; - struct tm tmptr; - uint8_t month, week, hour, day_of_week, d; - int n; - - /* obtain the variables */ - t = *timer + *z; - gmtime_r(&t, &tmptr); - month = tmptr.tm_mon; - day_of_week = tmptr.tm_wday; - week = week_of_month(&tmptr, 0); - hour = tmptr.tm_hour; - - if ((month > DST_START_MONTH) && (month < DST_END_MONTH)) - return ONE_HOUR; - - if (month < DST_START_MONTH) - return 0; - if (month > DST_END_MONTH) - return 0; - - if (month == DST_START_MONTH) { - - if (week < DST_START_WEEK) - return 0; - if (week > DST_START_WEEK) - return ONE_HOUR; - - if (day_of_week > SUNDAY) - return ONE_HOUR; - if (hour >= 2) - return ONE_HOUR; - return 0; - } - if (week > DST_END_WEEK) - return 0; - if (week < DST_END_WEEK) - return ONE_HOUR; - if (day_of_week > SUNDAY) - return 0; - if (hour >= 1) - return 0; - return ONE_HOUR; - - } - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/arduino/hardware/tools/avr/avr/lib/avr25/crtat86rf401.o b/arduino/hardware/tools/avr/avr/lib/avr25/crtat86rf401.o deleted file mode 100644 index 31a9f51..0000000 Binary files a/arduino/hardware/tools/avr/avr/lib/avr25/crtat86rf401.o and /dev/null differ diff --git a/arduino/hardware/tools/avr/avr/lib/avr25/crtata5272.o b/arduino/hardware/tools/avr/avr/lib/avr25/crtata5272.o deleted file mode 100644 index c42926c..0000000 Binary files a/arduino/hardware/tools/avr/avr/lib/avr25/crtata5272.o and /dev/null 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in -# the documentation and/or other materials provided with the -# distribution. -# * Neither the name of the copyright holders nor the names of -# contributors may be used to endorse or promote products derived -# from this software without specific prior written permission. -# -# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE -# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -# POSSIBILITY OF SUCH DAMAGE. - -## man(1) replacement to access the avr-libc manual pages - -: ${DESTDIR:-} -prefix=/home/jenkins/workspace/avr-gcc-staging/label/debian7-x86_64/objdir -datadir=/home/jenkins/workspace/avr-gcc-staging/label/debian7-x86_64/objdir/share - -exec man -M /home/jenkins/workspace/avr-gcc-staging/label/debian7-x86_64/objdir/share/doc/avr-libc-2.0.0/man "$@" diff --git a/arduino/hardware/tools/avr/bin/avr-nm b/arduino/hardware/tools/avr/bin/avr-nm deleted file mode 100755 index 3b428f3..0000000 Binary files a/arduino/hardware/tools/avr/bin/avr-nm and /dev/null differ diff --git a/arduino/hardware/tools/avr/bin/avr-objcopy b/arduino/hardware/tools/avr/bin/avr-objcopy deleted file mode 100755 index 214835b..0000000 Binary files a/arduino/hardware/tools/avr/bin/avr-objcopy and /dev/null differ diff --git a/arduino/hardware/tools/avr/bin/avr-objdump b/arduino/hardware/tools/avr/bin/avr-objdump deleted file mode 100755 index 421786b..0000000 Binary files a/arduino/hardware/tools/avr/bin/avr-objdump and /dev/null differ diff --git a/arduino/hardware/tools/avr/bin/avr-ranlib b/arduino/hardware/tools/avr/bin/avr-ranlib deleted file mode 100755 index ac629f3..0000000 Binary files a/arduino/hardware/tools/avr/bin/avr-ranlib and /dev/null differ diff --git a/arduino/hardware/tools/avr/bin/avr-readelf b/arduino/hardware/tools/avr/bin/avr-readelf deleted file mode 100755 index af419b1..0000000 Binary files a/arduino/hardware/tools/avr/bin/avr-readelf and /dev/null differ diff --git a/arduino/hardware/tools/avr/bin/avr-size b/arduino/hardware/tools/avr/bin/avr-size deleted file mode 100755 index 751d0d7..0000000 Binary files a/arduino/hardware/tools/avr/bin/avr-size and /dev/null differ diff --git a/arduino/hardware/tools/avr/bin/avr-strings b/arduino/hardware/tools/avr/bin/avr-strings deleted file mode 100755 index e9add2d..0000000 Binary files a/arduino/hardware/tools/avr/bin/avr-strings and /dev/null differ diff --git a/arduino/hardware/tools/avr/bin/avr-strip b/arduino/hardware/tools/avr/bin/avr-strip deleted file mode 100755 index e40c50f..0000000 Binary files a/arduino/hardware/tools/avr/bin/avr-strip and /dev/null differ diff --git a/arduino/hardware/tools/avr/bin/avrdude b/arduino/hardware/tools/avr/bin/avrdude deleted file mode 100755 index 7644fce..0000000 Binary files a/arduino/hardware/tools/avr/bin/avrdude and /dev/null differ diff --git a/arduino/hardware/tools/avr/builtin_tools_versions.txt b/arduino/hardware/tools/avr/builtin_tools_versions.txt deleted file mode 100644 index 776eae6..0000000 --- a/arduino/hardware/tools/avr/builtin_tools_versions.txt +++ /dev/null @@ -1,3 +0,0 @@ -arduino.avrdude=6.3.0-arduino14 -arduino.arduinoOTA=1.2.1 -arduino.avr-gcc=5.4.0-atmel3.6.1-arduino2 diff --git a/arduino/hardware/tools/avr/etc/avrdude.conf b/arduino/hardware/tools/avr/etc/avrdude.conf deleted file mode 100644 index d3994bd..0000000 --- a/arduino/hardware/tools/avr/etc/avrdude.conf +++ /dev/null @@ -1,16077 +0,0 @@ -# $Id$ -*- text -*- -# -# AVRDUDE Configuration File -# -# This file contains configuration data used by AVRDUDE which describes -# the programming hardware pinouts and also provides part definitions. -# AVRDUDE's "-C" command line option specifies the location of the -# configuration file. The "-c" option names the programmer configuration -# which must match one of the entry's "id" parameter. The "-p" option -# identifies which part AVRDUDE is going to be programming and must match -# one of the parts' "id" parameter. -# -# DO NOT MODIFY THIS FILE. Modifications will be overwritten the next -# time a "make install" is run. For user-specific additions, use the -# "-C +filename" commandline option. -# -# Possible entry formats are: -# -# programmer -# parent # optional parent -# id = [, [, ] ...] ; # are quoted strings -# desc = ; # quoted string -# type = ; # programmer type, quoted string -# # supported programmer types can be listed by "-c ?type" -# connection_type = parallel | serial | usb -# baudrate = ; # baudrate for avr910-programmer -# vcc = [, ... ] ; # pin number(s) -# buff = [, ... ] ; # pin number(s) -# reset = ; # pin number -# sck = ; # pin number -# mosi = ; # pin number -# miso = ; # pin number -# errled = ; # pin number -# rdyled = ; # pin number -# pgmled = ; # pin number -# vfyled = ; # pin number -# usbvid = ; # USB VID (Vendor ID) -# usbpid = [, ...] # USB PID (Product ID) (1) -# usbdev = ; # USB interface or other device info -# usbvendor = ; # USB Vendor Name -# usbproduct = ; # USB Product Name -# usbsn = ; # USB Serial Number -# -# To invert a bit, use = ~ , the spaces are important. -# For a pin list all pins must be inverted. -# A single pin can be specified as usual = ~ , for lists -# specify it as follows = ~ ( [, ... ] ) . -# -# (1) Not all programmer types can process a list of PIDs. -# ; -# -# part -# id = ; # quoted string -# desc = ; # quoted string -# has_jtag = ; # part has JTAG i/f -# has_debugwire = ; # part has debugWire i/f -# has_pdi = ; # part has PDI i/f -# has_updi = ; # part has UPDI i/f -# has_tpi = ; # part has TPI i/f -# devicecode = ; # deprecated, use stk500_devcode -# stk500_devcode = ; # numeric -# avr910_devcode = ; # numeric -# signature = ; # signature bytes -# usbpid = ; # DFU USB PID -# chip_erase_delay = ; # micro-seconds -# reset = dedicated | io; -# retry_pulse = reset | sck; -# pgm_enable = ; -# chip_erase = ; -# chip_erase_delay = ; # chip erase delay (us) -# # STK500 parameters (parallel programming IO lines) -# pagel = ; # pin name in hex, i.e., 0xD7 -# bs2 = ; # pin name in hex, i.e., 0xA0 -# serial = ; # can use serial downloading -# parallel = ; # can use par. programming -# # STK500v2 parameters, to be taken from Atmel's XML files -# timeout = ; -# stabdelay = ; -# cmdexedelay = ; -# synchloops = ; -# bytedelay = ; -# pollvalue = ; -# pollindex = ; -# predelay = ; -# postdelay = ; -# pollmethod = ; -# mode = ; -# delay = ; -# blocksize = ; -# readsize = ; -# hvspcmdexedelay = ; -# # STK500v2 HV programming parameters, from XML -# pp_controlstack = , , ...; # PP only -# hvsp_controlstack = , , ...; # HVSP only -# hventerstabdelay = ; -# progmodedelay = ; # PP only -# latchcycles = ; -# togglevtg = ; -# poweroffdelay = ; -# resetdelayms = ; -# resetdelayus = ; -# hvleavestabdelay = ; -# resetdelay = ; -# synchcycles = ; # HVSP only -# chiperasepulsewidth = ; # PP only -# chiperasepolltimeout = ; -# chiperasetime = ; # HVSP only -# programfusepulsewidth = ; # PP only -# programfusepolltimeout = ; -# programlockpulsewidth = ; # PP only -# programlockpolltimeout = ; -# # JTAG ICE mkII parameters, also from XML files -# allowfullpagebitstream = ; -# enablepageprogramming = ; -# idr = ; # IO addr of IDR (OCD) reg. -# rampz = ; # IO addr of RAMPZ reg. -# spmcr = ; # mem addr of SPMC[S]R reg. -# eecr = ; # mem addr of EECR reg. -# # (only when != 0x3c) -# is_at90s1200 = ; # AT90S1200 part -# is_avr32 = ; # AVR32 part -# -# memory -# paged = ; # yes / no -# size = ; # bytes -# page_size = ; # bytes -# num_pages = ; # numeric -# min_write_delay = ; # micro-seconds -# max_write_delay = ; # micro-seconds -# readback_p1 = ; # byte value -# readback_p2 = ; # byte value -# pwroff_after_write = ; # yes / no -# read = ; -# write = ; -# read_lo = ; -# read_hi = ; -# write_lo = ; -# write_hi = ; -# loadpage_lo = ; -# loadpage_hi = ; -# writepage = ; -# ; -# ; -# -# If any of the above parameters are not specified, the default value -# of 0 is used for numerics or the empty string ("") for string -# values. If a required parameter is left empty, AVRDUDE will -# complain. -# -# Parts can also inherit parameters from previously defined parts -# using the following syntax. In this case specified integer and -# string values override parameter values from the parent part. New -# memory definitions are added to the definitions inherited from the -# parent. -# -# part parent # quoted string -# id = ; # quoted string -# -# ; -# -# NOTES: -# * 'devicecode' is the device code used by the STK500 (see codes -# listed below) -# * Not all memory types will implement all instructions. -# * AVR Fuse bits and Lock bits are implemented as a type of memory. -# * Example memory types are: -# "flash", "eeprom", "fuse", "lfuse" (low fuse), "hfuse" (high -# fuse), "signature", "calibration", "lock" -# * The memory type specified on the avrdude command line must match -# one of the memory types defined for the specified chip. -# * The pwroff_after_write flag causes avrdude to attempt to -# power the device off and back on after an unsuccessful write to -# the affected memory area if VCC programmer pins are defined. If -# VCC pins are not defined for the programmer, a message -# indicating that the device needs a power-cycle is printed out. -# This flag was added to work around a problem with the -# at90s4433/2333's; see the at90s4433 errata at: -# -# http://www.atmel.com/dyn/resources/prod_documents/doc1280.pdf -# -# INSTRUCTION FORMATS -# -# Instruction formats are specified as a comma seperated list of -# string values containing information (bit specifiers) about each -# of the 32 bits of the instruction. Bit specifiers may be one of -# the following formats: -# -# '1' = the bit is always set on input as well as output -# -# '0' = the bit is always clear on input as well as output -# -# 'x' = the bit is ignored on input and output -# -# 'a' = the bit is an address bit, the bit-number matches this bit -# specifier's position within the current instruction byte -# -# 'aN' = the bit is the Nth address bit, bit-number = N, i.e., a12 -# is address bit 12 on input, a0 is address bit 0. -# -# 'i' = the bit is an input data bit -# -# 'o' = the bit is an output data bit -# -# Each instruction must be composed of 32 bit specifiers. The -# instruction specification closely follows the instruction data -# provided in Atmel's data sheets for their parts. -# -# See below for some examples. -# -# -# The following are STK500 part device codes to use for the -# "devicecode" field of the part. These came from Atmel's software -# section avr061.zip which accompanies the application note -# AVR061 available from: -# -# http://www.atmel.com/dyn/resources/prod_documents/doc2525.pdf -# - -#define ATTINY10 0x10 /* the _old_ one that never existed! */ -#define ATTINY11 0x11 -#define ATTINY12 0x12 -#define ATTINY15 0x13 -#define ATTINY13 0x14 - -#define ATTINY22 0x20 -#define ATTINY26 0x21 -#define ATTINY28 0x22 -#define ATTINY2313 0x23 - -#define AT90S1200 0x33 - -#define AT90S2313 0x40 -#define AT90S2323 0x41 -#define AT90S2333 0x42 -#define AT90S2343 0x43 - -#define AT90S4414 0x50 -#define AT90S4433 0x51 -#define AT90S4434 0x52 -#define ATMEGA48 0x59 - -#define AT90S8515 0x60 -#define AT90S8535 0x61 -#define AT90C8534 0x62 -#define ATMEGA8515 0x63 -#define ATMEGA8535 0x64 - -#define ATMEGA8 0x70 -#define ATMEGA88 0x73 -#define ATMEGA168 0x86 - -#define ATMEGA161 0x80 -#define ATMEGA163 0x81 -#define ATMEGA16 0x82 -#define ATMEGA162 0x83 -#define ATMEGA169 0x84 - -#define ATMEGA323 0x90 -#define ATMEGA32 0x91 - -#define ATMEGA64 0xA0 - -#define ATMEGA103 0xB1 -#define ATMEGA128 0xB2 -#define AT90CAN128 0xB3 -#define AT90CAN64 0xB3 -#define AT90CAN32 0xB3 - -#define AT86RF401 0xD0 - -#define AT89START 0xE0 -#define AT89S51 0xE0 -#define AT89S52 0xE1 - -# The following table lists the devices in the original AVR910 -# appnote: -# |Device |Signature | Code | -# +-------+----------+------+ -# |tiny12 | 1E 90 05 | 0x55 | -# |tiny15 | 1E 90 06 | 0x56 | -# | | | | -# | S1200 | 1E 90 01 | 0x13 | -# | | | | -# | S2313 | 1E 91 01 | 0x20 | -# | S2323 | 1E 91 02 | 0x48 | -# | S2333 | 1E 91 05 | 0x34 | -# | S2343 | 1E 91 03 | 0x4C | -# | | | | -# | S4414 | 1E 92 01 | 0x28 | -# | S4433 | 1E 92 03 | 0x30 | -# | S4434 | 1E 92 02 | 0x6C | -# | | | | -# | S8515 | 1E 93 01 | 0x38 | -# | S8535 | 1E 93 03 | 0x68 | -# | | | | -# |mega32 | 1E 95 01 | 0x72 | -# |mega83 | 1E 93 05 | 0x65 | -# |mega103| 1E 97 01 | 0x41 | -# |mega161| 1E 94 01 | 0x60 | -# |mega163| 1E 94 02 | 0x64 | - -# Appnote AVR109 also has a table of AVR910 device codes, which -# lists: -# dev avr910 signature -# ATmega8 0x77 0x1E 0x93 0x07 -# ATmega8515 0x3B 0x1E 0x93 0x06 -# ATmega8535 0x6A 0x1E 0x93 0x08 -# ATmega16 0x75 0x1E 0x94 0x03 -# ATmega162 0x63 0x1E 0x94 0x04 -# ATmega163 0x66 0x1E 0x94 0x02 -# ATmega169 0x79 0x1E 0x94 0x05 -# ATmega32 0x7F 0x1E 0x95 0x02 -# ATmega323 0x73 0x1E 0x95 0x01 -# ATmega64 0x46 0x1E 0x96 0x02 -# ATmega128 0x44 0x1E 0x97 0x02 -# -# These codes refer to "BOOT" device codes which are apparently -# different than standard device codes, for whatever reasons -# (often one above the standard code). - -# There are several extended versions of AVR910 implementations around -# in the Internet. These add the following codes (only devices that -# actually exist are listed): - -# ATmega8515 0x3A -# ATmega128 0x43 -# ATmega64 0x45 -# ATtiny26 0x5E -# ATmega8535 0x69 -# ATmega32 0x72 -# ATmega16 0x74 -# ATmega8 0x76 -# ATmega169 0x78 - -# -# Overall avrdude defaults; suitable for ~/.avrduderc -# -default_parallel = "/dev/parport0"; -default_serial = "/dev/ttyS0"; -# default_bitclock = 2.5; - -# Turn off safemode by default -#default_safemode = no; - - -# -# PROGRAMMER DEFINITIONS -# - -# http://wiring.org.co/ -# Basically STK500v2 protocol, with some glue to trigger the -# bootloader. -programmer - id = "wiring"; - desc = "Wiring"; - type = "wiring"; - connection_type = serial; -; - -programmer - id = "arduino"; - desc = "Arduino"; - type = "arduino"; - connection_type = serial; -; -# this will interface with the chips on these programmers: -# -# http://real.kiev.ua/old/avreal/en/adapters -# http://www.amontec.com/jtagkey.shtml, jtagkey-tiny.shtml -# http://www.olimex.com/dev/arm-usb-ocd.html, arm-usb-tiny.html -# http://www.ethernut.de/en/hardware/turtelizer/index.html -# http://elk.informatik.fh-augsburg.de/hhweb/doc/openocd/usbjtag/usbjtag.html -# http://dangerousprototypes.com/docs/FT2232_breakout_board -# http://www.ftdichip.com/Products/Modules/DLPModules.htm,DLP-2232*,DLP-USB1232H -# http://flashrom.org/FT2232SPI_Programmer -# -# The drivers will look for a specific device and use the first one found. -# If you have mulitple devices, then look for unique information (like SN) -# And fill that in here. -# -# Note that the pin numbers for the main ISP signals (reset, sck, -# mosi, miso) are fixed and cannot be changed, since they must match -# the way the Multi-Protocol Synchronous Serial Engine (MPSSE) of -# these FTDI ICs has been designed. - -programmer - id = "avrftdi"; - desc = "FT2232D based generic programmer"; - type = "avrftdi"; - connection_type = usb; - usbvid = 0x0403; - usbpid = 0x6010; - usbvendor = ""; - usbproduct = ""; - usbdev = "A"; - usbsn = ""; -#ISP-signals - lower ADBUS-Nibble (default) - reset = 3; - sck = 0; - mosi = 1; - miso = 2; -#LED SIGNALs - higher ADBUS-Nibble -# errled = 4; -# rdyled = 5; -# pgmled = 6; -# vfyled = 7; -#Buffer Signal - ACBUS - Nibble -# buff = 8; -; -# This is an implementation of the above with a buffer IC (74AC244) and -# 4 LEDs directly attached, all active low. -programmer - id = "2232HIO"; - desc = "FT2232H based generic programmer"; - type = "avrftdi"; - connection_type = usb; - usbvid = 0x0403; -# Note: This PID is reserved for generic H devices and -# should be programmed into the EEPROM -# usbpid = 0x8A48; - usbpid = 0x6010; - usbdev = "A"; - usbvendor = ""; - usbproduct = ""; - usbsn = ""; -#ISP-signals - reset = 3; - sck = 0; - mosi = 1; - miso = 2; - buff = ~4; -#LED SIGNALs - errled = ~ 11; - rdyled = ~ 14; - pgmled = ~ 13; - vfyled = ~ 12; -; - -#The FT4232H can be treated as FT2232H, but it has a different USB -#device ID of 0x6011. -programmer parent "avrftdi" - id = "4232h"; - desc = "FT4232H based generic programmer"; - usbpid = 0x6011; -; - -programmer - id = "jtagkey"; - desc = "Amontec JTAGKey, JTAGKey-Tiny and JTAGKey2"; - type = "avrftdi"; - connection_type = usb; - usbvid = 0x0403; -# Note: This PID is used in all JTAGKey variants - usbpid = 0xCFF8; - usbdev = "A"; - usbvendor = ""; - usbproduct = ""; - usbsn = ""; -#ISP-signals => 20 - Pin connector on JTAGKey - reset = 3; # TMS 7 violet - sck = 0; # TCK 9 white - mosi = 1; # TDI 5 green - miso = 2; # TDO 13 orange - buff = ~4; -# VTG VREF 1 brown with red tip -# GND GND 20 black -# The colors are on the 20 pin breakout cable -# from Amontec -; - -# UM232H module from FTDI and Glyn.com.au. -# See helix.air.net.au for detailed usage information. -# J1: Connect pin 2 and 3 for USB power. -# J2: Connect pin 2 and 3 for USB power. -# J2: Pin 7 is SCK -# : Pin 8 is MOSI -# : Pin 9 is MISO -# : Pin 11 is RST -# : Pin 6 is ground -# Use the -b flag to set the SPI clock rate eg -b 3750000 is the fastest I could get -# a 16MHz Atmega1280 to program reliably. The 232H is conveniently 5V tolerant. -programmer - id = "UM232H"; - desc = "FT232H based module from FTDI and Glyn.com.au"; - type = "avrftdi"; - usbvid = 0x0403; -# Note: This PID is reserved for generic 232H devices and -# should be programmed into the EEPROM - usbpid = 0x6014; - usbdev = "A"; - usbvendor = ""; - usbproduct = ""; - usbsn = ""; -#ISP-signals - sck = 0; - mosi = 1; - miso = 2; - reset = 3; -; - -# C232HM module from FTDI and Glyn.com.au. -# : Orange is SCK -# : Yellow is MOSI -# : Green is MISO -# : Brown is RST -# : Black is ground -# Use the -b flag to set the SPI clock rate eg -b 3750000 is the fastest I could get -# a 16MHz Atmega1280 to program reliably. The 232H is conveniently 5V tolerant. -programmer - id = "C232HM"; - desc = "FT232H based module from FTDI and Glyn.com.au"; - type = "avrftdi"; - usbvid = 0x0403; -# Note: This PID is reserved for generic 232H devices and -# should be programmed into the EEPROM - usbpid = 0x6014; - usbdev = "A"; - usbvendor = ""; - usbproduct = ""; - usbsn = ""; -#ISP-signals - sck = 0; - mosi = 1; - miso = 2; - reset = 3; -; - - -# On the adapter you can read "O-Link". On the PCB is printed "OpenJTAG v3.1" -# You can find it as "OpenJTAG ARM JTAG USB" in the internet. -# (But there are also several projects called Open JTAG, eg. -# http://www.openjtag.org, which are completely different.) -# http://www.100ask.net/shop/english.html (website seems to be outdated) -# http://item.taobao.com/item.htm?id=1559277013 -# http://www.micro4you.com/store/openjtag-arm-jtag-usb.html (schematics!) -# some other sources which call it O-Link -# http://www.andahammer.com/olink/ -# http://www.developmentboard.net/31-o-link-debugger.html -# http://armwerks.com/catalog/o-link-debugger-copy/ -# or just have a look at ebay ... -# It is basically the same entry as jtagkey with different usb ids. -programmer parent "jtagkey" - id = "o-link"; - desc = "O-Link, OpenJTAG from www.100ask.net"; - usbvid = 0x1457; - usbpid = 0x5118; - usbvendor = "www.100ask.net"; - usbproduct = "USB<=>JTAG&RS232"; -; - -# http://wiki.openmoko.org/wiki/Debug_Board_v3 -programmer - id = "openmoko"; - desc = "Openmoko debug board (v3)"; - type = "avrftdi"; - usbvid = 0x1457; - usbpid = 0x5118; - usbdev = "A"; - usbvendor = ""; - usbproduct = ""; - usbsn = ""; - reset = 3; # TMS 7 - sck = 0; # TCK 9 - mosi = 1; # TDI 5 - miso = 2; # TDO 13 -; - -# Only Rev. A boards. -# Schematic and user manual: http://www.cs.put.poznan.pl/wswitala/download/pdf/811EVBK.pdf -programmer - id = "lm3s811"; - desc = "Luminary Micro LM3S811 Eval Board (Rev. A)"; - type = "avrftdi"; - connection_type = usb; - usbvid = 0x0403; - usbpid = 0xbcd9; - usbvendor = "LMI"; - usbproduct = "LM3S811 Evaluation Board"; - usbdev = "A"; - usbsn = ""; -#ISP-signals - lower ACBUS-Nibble (default) - reset = 3; - sck = 0; - mosi = 1; - miso = 2; -# Enable correct buffers - buff = 7; -; - -# submitted as bug #46020 -programmer - id = "tumpa"; - desc = "TIAO USB Multi-Protocol Adapter"; - type = "avrftdi"; - connection_type = usb; - usbvid = 0x0403; - usbpid = 0x8A98; - usbdev = "A"; - usbvendor = "TIAO"; - usbproduct = ""; - usbsn = ""; - sck = 0; # TCK 9 - mosi = 1; # TDI 5 - miso = 2; # TDO 13 - reset = 3; # TMS 7 -; - -programmer - id = "avrisp"; - desc = "Atmel AVR ISP"; - type = "stk500"; - connection_type = serial; -; - -programmer - id = "avrispv2"; - desc = "Atmel AVR ISP V2"; - type = "stk500v2"; - connection_type = serial; -; - -programmer - id = "avrispmkII"; - desc = "Atmel AVR ISP mkII"; - type = "stk500v2"; - connection_type = usb; -; - -programmer parent "avrispmkII" - id = "avrisp2"; -; - -programmer - id = "buspirate"; - desc = "The Bus Pirate"; - type = "buspirate"; - connection_type = serial; -; - -programmer - id = "buspirate_bb"; - desc = "The Bus Pirate (bitbang interface, supports TPI)"; - type = "buspirate_bb"; - connection_type = serial; - # pins are bits in bitbang byte (numbers are 87654321) - # 1|POWER|PULLUP|AUX|MOSI|CLK|MISO|CS - reset = 1; - sck = 3; - mosi = 4; - miso = 2; - #vcc = 7; This is internally set independent of this setting. -; - -# This is supposed to be the "default" STK500 entry. -# Attempts to select the correct firmware version -# by probing for it. Better use one of the entries -# below instead. -programmer - id = "stk500"; - desc = "Atmel STK500"; - type = "stk500generic"; - connection_type = serial; -; - -programmer - id = "stk500v1"; - desc = "Atmel STK500 Version 1.x firmware"; - type = "stk500"; - connection_type = serial; -; - -programmer - id = "mib510"; - desc = "Crossbow MIB510 programming board"; - type = "stk500"; - connection_type = serial; -; - -programmer - id = "stk500v2"; - desc = "Atmel STK500 Version 2.x firmware"; - type = "stk500v2"; - connection_type = serial; -; - -programmer - id = "stk500pp"; - desc = "Atmel STK500 V2 in parallel programming mode"; - type = "stk500pp"; - connection_type = serial; -; - -programmer - id = "stk500hvsp"; - desc = "Atmel STK500 V2 in high-voltage serial programming mode"; - type = "stk500hvsp"; - connection_type = serial; -; - -programmer - id = "stk600"; - desc = "Atmel STK600"; - type = "stk600"; - connection_type = usb; -; - -programmer - id = "stk600pp"; - desc = "Atmel STK600 in parallel programming mode"; - type = "stk600pp"; - connection_type = usb; -; - -programmer - id = "stk600hvsp"; - desc = "Atmel STK600 in high-voltage serial programming mode"; - type = "stk600hvsp"; - connection_type = usb; -; - -programmer - id = "avr910"; - desc = "Atmel Low Cost Serial Programmer"; - type = "avr910"; - connection_type = serial; -; - -programmer - id = "ft245r"; - desc = "FT245R Synchronous BitBang"; - type = "ftdi_syncbb"; - connection_type = usb; - miso = 1; # D1 - sck = 0; # D0 - mosi = 2; # D2 - reset = 4; # D4 -; - -programmer - id = "ft232r"; - desc = "FT232R Synchronous BitBang"; - type = "ftdi_syncbb"; - connection_type = usb; - miso = 1; # RxD - sck = 0; # TxD - mosi = 2; # RTS - reset = 4; # DTR -; - -# see http://www.bitwizard.nl/wiki/index.php/FTDI_ATmega -programmer - id = "bwmega"; - desc = "BitWizard ftdi_atmega builtin programmer"; - type = "ftdi_syncbb"; - connection_type = usb; - miso = 5; # DSR - sck = 6; # DCD - mosi = 3; # CTS - reset = 7; # RI -; - -# see http://www.geocities.jp/arduino_diecimila/bootloader/index_en.html -# Note: pins are numbered from 1! -programmer - id = "arduino-ft232r"; - desc = "Arduino: FT232R connected to ISP"; - type = "ftdi_syncbb"; - connection_type = usb; - miso = 3; # CTS X3(1) - sck = 5; # DSR X3(2) - mosi = 6; # DCD X3(3) - reset = 7; # RI X3(4) -; - -# website mentioned above uses this id -programmer parent "arduino-ft232r" - id = "diecimila"; - desc = "alias for arduino-ft232r"; -; - -# There is a ATmega328P kit PCB called "uncompatino". -# This board allows ISP via its on-board FT232R. -# This is designed like Arduino Duemilanove but has no standard ICPS header. -# Its 4 pairs of pins are shorted to enable ftdi_syncbb. -# http://akizukidenshi.com/catalog/g/gP-07487/ -# http://akizukidenshi.com/download/ds/akizuki/k6096_manual_20130816.pdf -programmer - id = "uncompatino"; - desc = "uncompatino with all pairs of pins shorted"; - type = "ftdi_syncbb"; - connection_type = usb; - miso = 3; # cts - sck = 5; # dsr - mosi = 6; # dcd - reset = 7; # ri -; - -# FTDI USB to serial cable TTL-232R-5V with a custom adapter for ICSP -# http://www.ftdichip.com/Products/Cables/USBTTLSerial.htm -# http://www.ftdichip.com/Support/Documents/DataSheets/Cables/DS_TTL-232R_CABLES.pdf -# For ICSP pinout see for example http://www.atmel.com/images/doc2562.pdf -# (Figure 1. ISP6PIN header pinout and Table 1. Connections required for ISP ...) -# TTL-232R GND 1 Black -> ICPS GND (pin 6) -# TTL-232R CTS 2 Brown -> ICPS MOSI (pin 4) -# TTL-232R VCC 3 Red -> ICPS VCC (pin 2) -# TTL-232R TXD 4 Orange -> ICPS RESET (pin 5) -# TTL-232R RXD 5 Yellow -> ICPS SCK (pin 3) -# TTL-232R RTS 6 Green -> ICPS MISO (pin 1) -# Except for VCC and GND, you can connect arbitual pairs as long as -# the following table is adjusted. -programmer - id = "ttl232r"; - desc = "FTDI TTL232R-5V with ICSP adapter"; - type = "ftdi_syncbb"; - connection_type = usb; - miso = 2; # rts - sck = 1; # rxd - mosi = 3; # cts - reset = 0; # txd -; - -programmer - id = "usbasp"; - desc = "USBasp, http://www.fischl.de/usbasp/"; - type = "usbasp"; - connection_type = usb; - usbvid = 0x16C0; # VOTI - usbpid = 0x05DC; # Obdev's free shared PID - usbvendor = "www.fischl.de"; - usbproduct = "USBasp"; - - # following variants are autodetected for id "usbasp" - - # original usbasp from fischl.de - # see above "usbasp" - - # old usbasp from fischl.de - #usbvid = 0x03EB; # ATMEL - #usbpid = 0xC7B4; # (unoffical) USBasp - #usbvendor = "www.fischl.de"; - #usbproduct = "USBasp"; - - # NIBObee (only if -P nibobee is given on command line) - # see below "nibobee" -; - -programmer - id = "nibobee"; - desc = "NIBObee"; - type = "usbasp"; - connection_type = usb; - usbvid = 0x16C0; # VOTI - usbpid = 0x092F; # NIBObee PID - usbvendor = "www.nicai-systems.com"; - usbproduct = "NIBObee"; -; - -programmer - id = "usbasp-clone"; - desc = "Any usbasp clone with correct VID/PID"; - type = "usbasp"; - connection_type = usb; - usbvid = 0x16C0; # VOTI - usbpid = 0x05DC; # Obdev's free shared PID - #usbvendor = ""; - #usbproduct = ""; -; - -# USBtiny can also be used for TPI programming. -# In that case, a resistor of 1 kOhm is needed between MISO and MOSI -# pins of the connector, and MISO (pin 1 of the 6-pin connector) -# connects to TPIDATA. -programmer - id = "usbtiny"; - desc = "USBtiny simple USB programmer, https://learn.adafruit.com/usbtinyisp"; - type = "usbtiny"; - connection_type = usb; - usbvid = 0x1781; - usbpid = 0x0c9f; -; - -# commercial version of USBtiny, using a separate VID/PID -programmer - id = "ehajo-isp"; - desc = "avr-isp-programmer from eHaJo, http://www.eHaJo.de"; - type = "usbtiny"; - connection_type = usb; - usbvid = 0x16D0; - usbpid = 0x0BA5; -; - -programmer - id = "arduinoisp"; - desc = "Arduino ISP Programmer"; - type = "usbtiny"; - connection_type = usb; - usbvid = 0x2341; - usbpid = 0x0049; -; - -programmer - id = "arduinoisporg"; - desc = "Arduino ISP Programmer"; - type = "usbtiny"; - connection_type = usb; - usbvid = 0x2A03; - usbpid = 0x0049; -; - -programmer - id = "butterfly"; - desc = "Atmel Butterfly Development Board"; - type = "butterfly"; - connection_type = serial; -; - -programmer - id = "avr109"; - desc = "Atmel AppNote AVR109 Boot Loader"; - type = "butterfly"; - connection_type = serial; -; - -programmer - id = "avr911"; - desc = "Atmel AppNote AVR911 AVROSP"; - type = "butterfly"; - connection_type = serial; -; - -# suggested in http://forum.mikrokopter.de/topic-post48317.html -programmer - id = "mkbutterfly"; - desc = "Mikrokopter.de Butterfly"; - type = "butterfly_mk"; - connection_type = serial; -; - -programmer parent "mkbutterfly" - id = "butterfly_mk"; -; - -programmer - id = "jtagmkI"; - desc = "Atmel JTAG ICE (mkI)"; - baudrate = 115200; # default is 115200 - type = "jtagmki"; - connection_type = serial; -; - -# easier to type -programmer parent "jtagmkI" - id = "jtag1"; -; - -# easier to type -programmer parent "jtag1" - id = "jtag1slow"; - baudrate = 19200; -; - -# The JTAG ICE mkII has both, serial and USB connectivity. As it is -# mostly used through USB these days (AVR Studio 5 only supporting it -# that way), we make connection_type = usb the default. Users are -# still free to use a serial port with the -P option. - -programmer - id = "jtagmkII"; - desc = "Atmel JTAG ICE mkII"; - baudrate = 19200; # default is 19200 - type = "jtagmkii"; - connection_type = usb; -; - -# easier to type -programmer parent "jtagmkII" - id = "jtag2slow"; -; - -# JTAG ICE mkII @ 115200 Bd -programmer parent "jtag2slow" - id = "jtag2fast"; - baudrate = 115200; -; - -# make the fast one the default, people will love that -programmer parent "jtag2fast" - id = "jtag2"; -; - -# JTAG ICE mkII in ISP mode -programmer - id = "jtag2isp"; - desc = "Atmel JTAG ICE mkII in ISP mode"; - baudrate = 115200; - type = "jtagmkii_isp"; - connection_type = usb; -; - -# JTAG ICE mkII in debugWire mode -programmer - id = "jtag2dw"; - desc = "Atmel JTAG ICE mkII in debugWire mode"; - baudrate = 115200; - type = "jtagmkii_dw"; - connection_type = usb; -; - -# JTAG ICE mkII in AVR32 mode -programmer - id = "jtagmkII_avr32"; - desc = "Atmel JTAG ICE mkII im AVR32 mode"; - baudrate = 115200; - type = "jtagmkii_avr32"; - connection_type = usb; -; - -# JTAG ICE mkII in AVR32 mode -programmer - id = "jtag2avr32"; - desc = "Atmel JTAG ICE mkII im AVR32 mode"; - baudrate = 115200; - type = "jtagmkii_avr32"; - connection_type = usb; -; - -# JTAG ICE mkII in PDI mode -programmer - id = "jtag2pdi"; - desc = "Atmel JTAG ICE mkII PDI mode"; - baudrate = 115200; - type = "jtagmkii_pdi"; - connection_type = usb; -; - -# AVR Dragon in JTAG mode -programmer - id = "dragon_jtag"; - desc = "Atmel AVR Dragon in JTAG mode"; - baudrate = 115200; - type = "dragon_jtag"; - connection_type = usb; -; - -# AVR Dragon in ISP mode -programmer - id = "dragon_isp"; - desc = "Atmel AVR Dragon in ISP mode"; - baudrate = 115200; - type = "dragon_isp"; - connection_type = usb; -; - -# AVR Dragon in PP mode -programmer - id = "dragon_pp"; - desc = "Atmel AVR Dragon in PP mode"; - baudrate = 115200; - type = "dragon_pp"; - connection_type = usb; -; - -# AVR Dragon in HVSP mode -programmer - id = "dragon_hvsp"; - desc = "Atmel AVR Dragon in HVSP mode"; - baudrate = 115200; - type = "dragon_hvsp"; - connection_type = usb; -; - -# AVR Dragon in debugWire mode -programmer - id = "dragon_dw"; - desc = "Atmel AVR Dragon in debugWire mode"; - baudrate = 115200; - type = "dragon_dw"; - connection_type = usb; -; - -# AVR Dragon in PDI mode -programmer - id = "dragon_pdi"; - desc = "Atmel AVR Dragon in PDI mode"; - baudrate = 115200; - type = "dragon_pdi"; - connection_type = usb; -; - -programmer - id = "jtag3"; - desc = "Atmel AVR JTAGICE3 in JTAG mode"; - type = "jtagice3"; - connection_type = usb; - usbpid = 0x2110, 0x2140; -; - -programmer - id = "jtag3pdi"; - desc = "Atmel AVR JTAGICE3 in PDI mode"; - type = "jtagice3_pdi"; - connection_type = usb; - usbpid = 0x2110, 0x2140; -; - -programmer - id = "jtag3dw"; - desc = "Atmel AVR JTAGICE3 in debugWIRE mode"; - type = "jtagice3_dw"; - connection_type = usb; - usbpid = 0x2110, 0x2140; -; - -programmer - id = "jtag3isp"; - desc = "Atmel AVR JTAGICE3 in ISP mode"; - type = "jtagice3_isp"; - connection_type = usb; - usbpid = 0x2110, 0x2140; -; - -programmer - id = "xplainedpro"; - desc = "Atmel AVR XplainedPro in JTAG mode"; - type = "jtagice3"; - connection_type = usb; - usbpid = 0x2111; -; - -programmer - id = "xplainedpro_updi"; - desc = "Atmel AVR XplainedPro in UPDI mode"; - type = "jtagice3_updi"; - connection_type = usb; - usbpid = 0x2111; -; - -programmer - id = "xplainedmini"; - desc = "Atmel AVR XplainedMini in ISP mode"; - type = "jtagice3_isp"; - connection_type = usb; - usbpid = 0x2145; -; - -programmer - id = "xplainedmini_dw"; - desc = "Atmel AVR XplainedMini in debugWIRE mode"; - type = "jtagice3_dw"; - connection_type = usb; - usbpid = 0x2145; -; - -programmer - id = "xplainedmini_updi"; - desc = "Atmel AVR XplainedMini in UPDI mode"; - type = "jtagice3_updi"; - connection_type = usb; - usbpid = 0x2145; -; - -programmer - id = "atmelice"; - desc = "Atmel-ICE (ARM/AVR) in JTAG mode"; - type = "jtagice3"; - connection_type = usb; - usbpid = 0x2141; -; - -programmer - id = "atmelice_pdi"; - desc = "Atmel-ICE (ARM/AVR) in PDI mode"; - type = "jtagice3_pdi"; - connection_type = usb; - usbpid = 0x2141; -; - -programmer - id = "atmelice_updi"; - desc = "Atmel-ICE (ARM/AVR) in UPDI mode"; - type = "jtagice3_updi"; - connection_type = usb; - usbpid = 0x2141; -; - -programmer - id = "atmelice_dw"; - desc = "Atmel-ICE (ARM/AVR) in debugWIRE mode"; - type = "jtagice3_dw"; - connection_type = usb; - usbpid = 0x2141; -; - -programmer - id = "atmelice_isp"; - desc = "Atmel-ICE (ARM/AVR) in ISP mode"; - type = "jtagice3_isp"; - connection_type = usb; - usbpid = 0x2141; -; - -programmer - id = "powerdebugger"; - desc = "Atmel PowerDebugger (ARM/AVR) in JTAG mode"; - type = "jtagice3"; - connection_type = usb; - usbpid = 0x2144; -; - -programmer - id = "powerdebugger_pdi"; - desc = "Atmel PowerDebugger (ARM/AVR) in PDI mode"; - type = "jtagice3_pdi"; - connection_type = usb; - usbpid = 0x2144; -; - -programmer - id = "powerdebugger_updi"; - desc = "Atmel PowerDebugger (ARM/AVR) in UPDI mode"; - type = "jtagice3_updi"; - connection_type = usb; - usbpid = 0x2144; -; - -programmer - id = "powerdebugger_dw"; - desc = "Atmel PowerDebugger (ARM/AVR) in debugWire mode"; - type = "jtagice3_dw"; - connection_type = usb; - usbpid = 0x2144; -; - -programmer - id = "powerdebugger_isp"; - desc = "Atmel PowerDebugger (ARM/AVR) in ISP mode"; - type = "jtagice3_isp"; - connection_type = usb; - usbpid = 0x2144; -; - -programmer - id = "pavr"; - desc = "Jason Kyle's pAVR Serial Programmer"; - type = "avr910"; - connection_type = serial; -; - -programmer - id = "pickit2"; - desc = "MicroChip's PICkit2 Programmer"; - type = "pickit2"; - connection_type = usb; -; - -programmer - id = "flip1"; - desc = "FLIP USB DFU protocol version 1 (doc7618)"; - type = "flip1"; - connection_type = usb; -; - -programmer - id = "flip2"; - desc = "FLIP USB DFU protocol version 2 (AVR4023)"; - type = "flip2"; - connection_type = usb; -; - -# Parallel port programmers. - -programmer - id = "bsd"; - desc = "Brian Dean's Programmer, http://www.bsdhome.com/avrdude/"; - type = "par"; - connection_type = parallel; - vcc = 2, 3, 4, 5; - reset = 7; - sck = 8; - mosi = 9; - miso = 10; -; - -programmer - id = "stk200"; - desc = "STK200"; - type = "par"; - connection_type = parallel; - buff = 4, 5; - sck = 6; - mosi = 7; - reset = 9; - miso = 10; -; - -# The programming dongle used by the popular Ponyprog -# utility. It is almost similar to the STK200 one, -# except that there is a LED indicating that the -# programming is currently in progress. - -programmer parent "stk200" - id = "pony-stk200"; - desc = "Pony Prog STK200"; - pgmled = 8; -; - -programmer - id = "dt006"; - desc = "Dontronics DT006"; - type = "par"; - connection_type = parallel; - reset = 4; - sck = 5; - mosi = 2; - miso = 11; -; - -programmer parent "dt006" - id = "bascom"; - desc = "Bascom SAMPLE programming cable"; -; - -programmer - id = "alf"; - desc = "Nightshade ALF-PgmAVR, http://nightshade.homeip.net/"; - type = "par"; - connection_type = parallel; - vcc = 2, 3, 4, 5; - buff = 6; - reset = 7; - sck = 8; - mosi = 9; - miso = 10; - errled = 1; - rdyled = 14; - pgmled = 16; - vfyled = 17; -; - -programmer - id = "sp12"; - desc = "Steve Bolt's Programmer"; - type = "par"; - connection_type = parallel; - vcc = 4,5,6,7,8; - reset = 3; - sck = 2; - mosi = 9; - miso = 11; -; - -programmer - id = "picoweb"; - desc = "Picoweb Programming Cable, http://www.picoweb.net/"; - type = "par"; - connection_type = parallel; - reset = 2; - sck = 3; - mosi = 4; - miso = 13; -; - -programmer - id = "abcmini"; - desc = "ABCmini Board, aka Dick Smith HOTCHIP"; - type = "par"; - connection_type = parallel; - reset = 4; - sck = 3; - mosi = 2; - miso = 10; -; - -programmer - id = "futurlec"; - desc = "Futurlec.com programming cable."; - type = "par"; - connection_type = parallel; - reset = 3; - sck = 2; - mosi = 1; - miso = 10; -; - - -# From the contributor of the "xil" jtag cable: -# The "vcc" definition isn't really vcc (the cable gets its power from -# the programming circuit) but is necessary to switch one of the -# buffer lines (trying to add it to the "buff" lines doesn't work in -# avrdude versions before 5.5j). -# With this, TMS connects to RESET, TDI to MOSI, TDO to MISO and TCK -# to SCK (plus vcc/gnd of course) -programmer - id = "xil"; - desc = "Xilinx JTAG cable"; - type = "par"; - connection_type = parallel; - mosi = 2; - sck = 3; - reset = 4; - buff = 5; - miso = 13; - vcc = 6; -; - - -programmer - id = "dapa"; - desc = "Direct AVR Parallel Access cable"; - type = "par"; - connection_type = parallel; - vcc = 3; - reset = 16; - sck = 1; - mosi = 2; - miso = 11; -; - -programmer - id = "atisp"; - desc = "AT-ISP V1.1 programming cable for AVR-SDK1 from micro-research.co.th"; - type = "par"; - connection_type = parallel; - reset = ~6; - sck = ~8; - mosi = ~7; - miso = ~10; -; - -programmer - id = "ere-isp-avr"; - desc = "ERE ISP-AVR "; - type = "par"; - connection_type = parallel; - reset = ~4; - sck = 3; - mosi = 2; - miso = 10; -; - -programmer - id = "blaster"; - desc = "Altera ByteBlaster"; - type = "par"; - connection_type = parallel; - sck = 2; - miso = 11; - reset = 3; - mosi = 8; - buff = 14; -; - -# It is almost same as pony-stk200, except vcc on pin 5 to auto -# disconnect port (download on http://electropol.free.fr/spip/spip.php?article27) -programmer parent "pony-stk200" - id = "frank-stk200"; - desc = "Frank STK200"; - buff = ; # delete buff pin assignment - vcc = 5; -; - -# The AT98ISP Cable is a simple parallel dongle for AT89 family. -# http://www.atmel.com/dyn/products/tools_card.asp?tool_id=2877 -programmer - id = "89isp"; - desc = "Atmel at89isp cable"; - type = "par"; - connection_type = parallel; - reset = 17; - sck = 1; - mosi = 2; - miso = 10; -; - - -#This programmer bitbangs GPIO lines using the Linux sysfs GPIO interface -# -#To enable it set the configuration below to match the GPIO lines connected to the -#relevant ISP header pins and uncomment the entry definition. In case you don't -#have the required permissions to edit this system wide config file put the -#entry in a separate .conf file and use it with -C+.conf -#on the command line. -# -#To check if your avrdude build has support for the linuxgpio programmer compiled in, -#use -c?type on the command line and look for linuxgpio in the list. If it's not available -#you need pass the --enable-linuxgpio=yes option to configure and recompile avrdude. -# -#programmer -# id = "linuxgpio"; -# desc = "Use the Linux sysfs interface to bitbang GPIO lines"; -# type = "linuxgpio"; -# reset = ?; -# sck = ?; -# mosi = ?; -# miso = ?; -#; - - -#This programmer uses the built in linux SPI bus devices to program an -#attached AVR. A GPIO accessed through the sysfs GPIO interface needs to -#be specified for a reset pin since the linux SPI userspace functions do -#not allow for control over the slave select/chip select signal. -# -programmer - id = "linuxspi"; - desc = "Use Linux SPI device in /dev/spidev*"; - type = "linuxspi"; - reset = 25; -; - -# some ultra cheap programmers use bitbanging on the -# serialport. -# -# PC - DB9 - Pins for RS232: -# -# GND 5 -- |O -# | O| <- 9 RI -# DTR 4 <- |O | -# | O| <- 8 CTS -# TXD 3 <- |O | -# | O| -> 7 RTS -# RXD 2 -> |O | -# | O| <- 6 DSR -# DCD 1 -> |O -# -# Using RXD is currently not supported. -# Using RI is not supported under Win32 but is supported under Posix. - -# serial ponyprog design (dasa2 in uisp) -# reset=!txd sck=rts mosi=dtr miso=cts - -programmer - id = "ponyser"; - desc = "design ponyprog serial, reset=!txd sck=rts mosi=dtr miso=cts"; - type = "serbb"; - connection_type = serial; - reset = ~3; - sck = 7; - mosi = 4; - miso = 8; -; - -# Same as above, different name -# reset=!txd sck=rts mosi=dtr miso=cts - -programmer parent "ponyser" - id = "siprog"; - desc = "Lancos SI-Prog "; -; - -# unknown (dasa in uisp) -# reset=rts sck=dtr mosi=txd miso=cts - -programmer - id = "dasa"; - desc = "serial port banging, reset=rts sck=dtr mosi=txd miso=cts"; - type = "serbb"; - connection_type = serial; - reset = 7; - sck = 4; - mosi = 3; - miso = 8; -; - -# unknown (dasa3 in uisp) -# reset=!dtr sck=rts mosi=txd miso=cts - -programmer - id = "dasa3"; - desc = "serial port banging, reset=!dtr sck=rts mosi=txd miso=cts"; - type = "serbb"; - connection_type = serial; - reset = ~4; - sck = 7; - mosi = 3; - miso = 8; -; - -# C2N232i (jumper configuration "auto") -# reset=dtr sck=!rts mosi=!txd miso=!cts - -programmer - id = "c2n232i"; - desc = "serial port banging, reset=dtr sck=!rts mosi=!txd miso=!cts"; - type = "serbb"; - connection_type = serial; - reset = 4; - sck = ~7; - mosi = ~3; - miso = ~8; -; - -# -# PART DEFINITIONS -# - -#------------------------------------------------------------ -# ATtiny11 -#------------------------------------------------------------ - -# This is an HVSP-only device. - -part - id = "t11"; - desc = "ATtiny11"; - stk500_devcode = 0x11; - signature = 0x1e 0x90 0x04; - chip_erase_delay = 20000; - - timeout = 200; - hvsp_controlstack = - 0x4C, 0x0C, 0x1C, 0x2C, 0x3C, 0x64, 0x74, 0x00, - 0x68, 0x78, 0x68, 0x68, 0x00, 0x00, 0x68, 0x78, - 0x78, 0x00, 0x6D, 0x0C, 0x80, 0x40, 0x20, 0x10, - 0x11, 0x08, 0x04, 0x02, 0x03, 0x08, 0x04, 0x00; - hventerstabdelay = 100; - progmodedelay = 0; - hvspcmdexedelay = 0; - synchcycles = 6; - latchcycles = 1; - togglevtg = 1; - poweroffdelay = 25; - resetdelayms = 0; - resetdelayus = 50; - hvleavestabdelay = 100; - resetdelay = 25; - chiperasepolltimeout = 40; - chiperasetime = 0; - programfusepolltimeout = 25; - programlockpolltimeout = 25; - - memory "eeprom" - size = 64; - blocksize = 64; - readsize = 256; - delay = 5; - ; - - memory "flash" - size = 1024; - blocksize = 128; - readsize = 256; - delay = 3; - ; - - memory "signature" - size = 3; - ; - - memory "lock" - size = 1; - ; - - memory "calibration" - size = 1; - ; - - memory "fuse" - size = 1; - ; -; - -#------------------------------------------------------------ -# ATtiny12 -#------------------------------------------------------------ - -part - id = "t12"; - desc = "ATtiny12"; - stk500_devcode = 0x12; - avr910_devcode = 0x55; - signature = 0x1e 0x90 0x05; - chip_erase_delay = 20000; - pgm_enable = "1 0 1 0 1 1 0 0 0 1 0 1 0 0 1 1", - "x x x x x x x x x x x x x x x x"; - - chip_erase = "1 0 1 0 1 1 0 0 1 0 0 x x x x x", - "x x x x x x x x x x x x x x x x"; - - timeout = 200; - stabdelay = 100; - cmdexedelay = 25; - synchloops = 32; - bytedelay = 0; - pollindex = 3; - pollvalue = 0x53; - predelay = 1; - postdelay = 1; - pollmethod = 0; - - hvsp_controlstack = - 0x4C, 0x0C, 0x1C, 0x2C, 0x3C, 0x64, 0x74, 0x00, - 0x68, 0x78, 0x68, 0x68, 0x00, 0x00, 0x68, 0x78, - 0x78, 0x00, 0x6D, 0x0C, 0x80, 0x40, 0x20, 0x10, - 0x11, 0x08, 0x04, 0x02, 0x03, 0x08, 0x04, 0x00; - hventerstabdelay = 100; - hvspcmdexedelay = 0; - synchcycles = 6; - latchcycles = 1; - togglevtg = 1; - poweroffdelay = 25; - resetdelayms = 0; - resetdelayus = 50; - hvleavestabdelay = 100; - resetdelay = 25; - chiperasepolltimeout = 40; - chiperasetime = 0; - programfusepolltimeout = 25; - programlockpolltimeout = 25; - - memory "eeprom" - size = 64; - min_write_delay = 9000; - max_write_delay = 20000; - readback_p1 = 0xff; - readback_p2 = 0xff; - read = "1 0 1 0 0 0 0 0 x x x x x x x x", - "x x a5 a4 a3 a2 a1 a0 o o o o o o o o"; - - write = "1 1 0 0 0 0 0 0 x x x x x x x x", - "x x a5 a4 a3 a2 a1 a0 i i i i i i i i"; - - mode = 0x04; - delay = 8; - blocksize = 64; - readsize = 256; - ; - - memory "flash" - size = 1024; - min_write_delay = 4500; - max_write_delay = 20000; - readback_p1 = 0xff; - readback_p2 = 0xff; - read_lo = " 0 0 1 0 0 0 0 0", - " x x x x x x x a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " o o o o o o o o"; - - read_hi = " 0 0 1 0 1 0 0 0", - " x x x x x x x a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " o o o o o o o o"; - - write_lo = " 0 1 0 0 0 0 0 0", - " x x x x x x x a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " i i i i i i i i"; - - write_hi = " 0 1 0 0 1 0 0 0", - " x x x x x x x a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " i i i i i i i i"; - - mode = 0x04; - delay = 5; - blocksize = 128; - readsize = 256; - ; - - memory "signature" - size = 3; - read = "0 0 1 1 0 0 0 0 x x x x x x x x", - "0 0 0 0 0 0 a1 a0 o o o o o o o o"; - ; - - memory "lock" - size = 1; - read = "0 1 0 1 1 0 0 0 x x x x x x x x", - "x x x x x x x x x x x x x o o x"; - - write = "1 0 1 0 1 1 0 0 1 1 1 1 1 i i 1", - "x x x x x x x x x x x x x x x x"; - min_write_delay = 9000; - max_write_delay = 9000; - ; - - memory "calibration" - size = 1; - read = "0 0 1 1 1 0 0 0 x x x x x x x x", - "0 0 0 0 0 0 0 0 o o o o o o o o"; - ; - - memory "fuse" - size = 1; - read = "0 1 0 1 0 0 0 0 x x x x x x x x", - "x x x x x x x x o o o o o o o o"; - - write = "1 0 1 0 1 1 0 0 1 0 1 x x x x x", - "x x x x x x x x i i i i i i i i"; - min_write_delay = 9000; - max_write_delay = 9000; - ; -; - -#------------------------------------------------------------ -# ATtiny13 -#------------------------------------------------------------ - -part - id = "t13"; - desc = "ATtiny13"; - has_debugwire = yes; - flash_instr = 0xB4, 0x0E, 0x1E; - eeprom_instr = 0xBB, 0xFE, 0xBB, 0xEE, 0xBB, 0xCC, 0xB2, 0x0D, - 0xBC, 0x0E, 0xB4, 0x0E, 0xBA, 0x0D, 0xBB, 0xBC, - 0x99, 0xE1, 0xBB, 0xAC; - stk500_devcode = 0x14; - signature = 0x1e 0x90 0x07; - chip_erase_delay = 4000; - pgm_enable = "1 0 1 0 1 1 0 0 0 1 0 1 0 0 1 1", - "x x x x x x x x x x x x x x x x"; - - chip_erase = "1 0 1 0 1 1 0 0 1 0 0 x x x x x", - "x x x x x x x x x x x x x x x x"; - - timeout = 200; - stabdelay = 100; - cmdexedelay = 25; - synchloops = 32; - bytedelay = 0; - pollindex = 3; - pollvalue = 0x53; - predelay = 1; - postdelay = 1; - pollmethod = 1; - - hvsp_controlstack = - 0x4C, 0x0C, 0x1C, 0x2C, 0x3C, 0x64, 0x74, 0x66, - 0x68, 0x78, 0x68, 0x68, 0x7A, 0x6A, 0x68, 0x78, - 0x78, 0x7D, 0x6D, 0x0C, 0x80, 0x40, 0x20, 0x10, - 0x11, 0x08, 0x04, 0x02, 0x03, 0x08, 0x04, 0x00; - hventerstabdelay = 100; - progmodedelay = 0; - hvspcmdexedelay = 0; - synchcycles = 6; - latchcycles = 1; - togglevtg = 1; - poweroffdelay = 25; - resetdelayms = 0; - resetdelayus = 90; - hvleavestabdelay = 100; - resetdelay = 25; - chiperasepolltimeout = 40; - chiperasetime = 0; - programfusepolltimeout = 25; - programlockpolltimeout = 25; - - ocdrev = 0; - - memory "eeprom" - size = 64; - page_size = 4; - min_write_delay = 4000; - max_write_delay = 4000; - readback_p1 = 0xff; - readback_p2 = 0xff; - read = "1 0 1 0 0 0 0 0 0 0 0 x x x x x", - "x x a5 a4 a3 a2 a1 a0 o o o o o o o o"; - - write = "1 1 0 0 0 0 0 0 0 0 0 x x x x x", - "x x a5 a4 a3 a2 a1 a0 i i i i i i i i"; - - loadpage_lo = " 1 1 0 0 0 0 0 1", - " 0 0 0 0 0 0 0 0", - " 0 0 0 0 0 0 a1 a0", - " i i i i i i i i"; - - writepage = " 1 1 0 0 0 0 1 0", - " 0 0 x x x x x x", - " x x a5 a4 a3 a2 0 0", - " x x x x x x x x"; - - mode = 0x41; - delay = 5; - blocksize = 4; - readsize = 256; - ; - - memory "flash" - paged = yes; - size = 1024; - page_size = 32; - num_pages = 32; - min_write_delay = 4500; - max_write_delay = 4500; - readback_p1 = 0xff; - readback_p2 = 0xff; - read_lo = " 0 0 1 0 0 0 0 0", - " 0 0 0 0 0 0 0 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " o o o o o o o o"; - - read_hi = " 0 0 1 0 1 0 0 0", - " 0 0 0 0 0 0 0 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " o o o o o o o o"; - - loadpage_lo = " 0 1 0 0 0 0 0 0", - " 0 0 0 x x x x x", - " x x x x a3 a2 a1 a0", - " i i i i i i i i"; - - loadpage_hi = " 0 1 0 0 1 0 0 0", - " 0 0 0 x x x x x", - " x x x x a3 a2 a1 a0", - " i i i i i i i i"; - - writepage = " 0 1 0 0 1 1 0 0", - " 0 0 0 0 0 0 0 a8", - " a7 a6 a5 a4 x x x x", - " x x x x x x x x"; - - mode = 0x41; - delay = 6; - blocksize = 32; - readsize = 256; - ; - - memory "signature" - size = 3; - read = "0 0 1 1 0 0 0 0 0 0 0 x x x x x", - "x x x x x x a1 a0 o o o o o o o o"; - ; - - memory "lock" - size = 1; - min_write_delay = 4500; - max_write_delay = 4500; - - read = "0 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0", - "x x x x x x x x x x o o o o o o"; - - write = "1 0 1 0 1 1 0 0 1 1 1 x x x x x", - "x x x x x x x x 1 1 i i i i i i"; - ; - - memory "calibration" - size = 2; - read = "0 0 1 1 1 0 0 0 0 0 0 x x x x x", - "0 0 0 0 0 0 0 a0 o o o o o o o o"; - ; - - memory "lfuse" - size = 1; - min_write_delay = 4500; - max_write_delay = 4500; - - write = "1 0 1 0 1 1 0 0 1 0 1 0 0 0 0 0", - "x x x x x x x x i i i i i i i i"; - - read = "0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0", - "x x x x x x x x o o o o o o o o"; - ; - - memory "hfuse" - size = 1; - min_write_delay = 4500; - max_write_delay = 4500; - - write = "1 0 1 0 1 1 0 0 1 0 1 0 1 0 0 0", - "x x x x x x x x i i i i i i i i"; - - read = "0 1 0 1 1 0 0 0 0 0 0 0 1 0 0 0", - "x x x x x x x x o o o o o o o o"; - ; - -; - - -#------------------------------------------------------------ -# ATtiny15 -#------------------------------------------------------------ - -part - id = "t15"; - desc = "ATtiny15"; - stk500_devcode = 0x13; - avr910_devcode = 0x56; - signature = 0x1e 0x90 0x06; - chip_erase_delay = 8200; - pgm_enable = "1 0 1 0 1 1 0 0 0 1 0 1 0 0 1 1", - "x x x x x x x x x x x x x x x x"; - - chip_erase = "1 0 1 0 1 1 0 0 1 0 0 x x x x x", - "x x x x x x x x x x x x x x x x"; - - timeout = 200; - stabdelay = 100; - cmdexedelay = 25; - synchloops = 32; - bytedelay = 0; - pollindex = 3; - pollvalue = 0x53; - predelay = 1; - postdelay = 1; - pollmethod = 0; - - hvsp_controlstack = - 0x4C, 0x0C, 0x1C, 0x2C, 0x3C, 0x64, 0x74, 0x00, - 0x68, 0x78, 0x68, 0x68, 0x00, 0x00, 0x68, 0x78, - 0x78, 0x00, 0x6D, 0x0C, 0x80, 0x40, 0x20, 0x10, - 0x11, 0x08, 0x04, 0x02, 0x03, 0x08, 0x04, 0x00; - hventerstabdelay = 100; - hvspcmdexedelay = 5; - synchcycles = 6; - latchcycles = 16; - togglevtg = 1; - poweroffdelay = 25; - resetdelayms = 0; - resetdelayus = 50; - hvleavestabdelay = 100; - resetdelay = 25; - chiperasepolltimeout = 40; - chiperasetime = 0; - programfusepolltimeout = 25; - programlockpolltimeout = 25; - - memory "eeprom" - size = 64; - min_write_delay = 8200; - max_write_delay = 8200; - readback_p1 = 0xff; - readback_p2 = 0xff; - read = "1 0 1 0 0 0 0 0 x x x x x x x x", - "x x a5 a4 a3 a2 a1 a0 o o o o o o o o"; - - write = "1 1 0 0 0 0 0 0 x x x x x x x x", - "x x a5 a4 a3 a2 a1 a0 i i i i i i i i"; - - mode = 0x04; - delay = 10; - blocksize = 64; - readsize = 256; - ; - - memory "flash" - size = 1024; - min_write_delay = 4100; - max_write_delay = 4100; - readback_p1 = 0xff; - readback_p2 = 0xff; - read_lo = " 0 0 1 0 0 0 0 0", - " x x x x x x x a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " o o o o o o o o"; - - read_hi = " 0 0 1 0 1 0 0 0", - " x x x x x x x a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " o o o o o o o o"; - - write_lo = " 0 1 0 0 0 0 0 0", - " x x x x x x x a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " i i i i i i i i"; - - write_hi = " 0 1 0 0 1 0 0 0", - " x x x x x x x a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " i i i i i i i i"; - - mode = 0x04; - delay = 5; - blocksize = 128; - readsize = 256; - ; - - memory "signature" - size = 3; - read = "0 0 1 1 0 0 0 0 x x x x x x x x", - "0 0 0 0 0 0 a1 a0 o o o o o o o o"; - ; - - memory "lock" - size = 1; - read = "0 1 0 1 1 0 0 0 x x x x x x x x", - "x x x x x x x x x x x x x o o x"; - - write = "1 0 1 0 1 1 0 0 1 1 1 1 1 i i 1", - "x x x x x x x x x x x x x x x x"; - min_write_delay = 9000; - max_write_delay = 9000; - ; - - memory "calibration" - size = 1; - read = "0 0 1 1 1 0 0 0 x x x x x x x x", - "0 0 0 0 0 0 0 0 o o o o o o o o"; - ; - - memory "fuse" - size = 1; - read = "0 1 0 1 0 0 0 0 x x x x x x x x", - "x x x x x x x x o o o o x x o o"; - - write = "1 0 1 0 1 1 0 0 1 0 1 x x x x x", - "x x x x x x x x i i i i 1 1 i i"; - min_write_delay = 9000; - max_write_delay = 9000; - ; -; - -#------------------------------------------------------------ -# AT90s1200 -#------------------------------------------------------------ - -part - id = "1200"; - desc = "AT90S1200"; - is_at90s1200 = yes; - stk500_devcode = 0x33; - avr910_devcode = 0x13; - signature = 0x1e 0x90 0x01; - pagel = 0xd7; - bs2 = 0xa0; - chip_erase_delay = 20000; - pgm_enable = "1 0 1 0 1 1 0 0 0 1 0 1 0 0 1 1", - "x x x x x x x x x x x x x x x x"; - - chip_erase = "1 0 1 0 1 1 0 0 1 0 0 0 0 0 0 0", - "x x x x x x x x x x x x x x x x"; - - timeout = 200; - stabdelay = 100; - cmdexedelay = 25; - synchloops = 1; - bytedelay = 0; - pollindex = 0; - pollvalue = 0xFF; - predelay = 1; - postdelay = 1; - pollmethod = 0; - - pp_controlstack = - 0x0E, 0x1E, 0x0F, 0x1F, 0x2E, 0x3E, 0x2F, 0x3F, - 0x4E, 0x5E, 0x4F, 0x5F, 0x6E, 0x7E, 0x6F, 0x7F, - 0x66, 0x76, 0x67, 0x77, 0x6A, 0x7A, 0x6B, 0x7B, - 0xBE, 0xFD, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00; - hventerstabdelay = 100; - progmodedelay = 0; - latchcycles = 0; - togglevtg = 0; - poweroffdelay = 0; - resetdelayms = 0; - resetdelayus = 0; - hvleavestabdelay = 15; - chiperasepulsewidth = 15; - chiperasepolltimeout = 0; - programfusepulsewidth = 2; - programfusepolltimeout = 0; - programlockpulsewidth = 0; - programlockpolltimeout = 1; - - memory "eeprom" - size = 64; - min_write_delay = 4000; - max_write_delay = 9000; - readback_p1 = 0x00; - readback_p2 = 0xff; - read = "1 0 1 0 0 0 0 0 x x x x x x x x", - "x x a5 a4 a3 a2 a1 a0 o o o o o o o o"; - - write = "1 1 0 0 0 0 0 0 x x x x x x x x", - "x x a5 a4 a3 a2 a1 a0 i i i i i i i i"; - - mode = 0x04; - delay = 20; - blocksize = 32; - readsize = 256; - ; - memory "flash" - size = 1024; - min_write_delay = 4000; - max_write_delay = 9000; - readback_p1 = 0xff; - readback_p2 = 0xff; - read_lo = " 0 0 1 0 0 0 0 0", - " x x x x x x x a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " o o o o o o o o"; - - read_hi = " 0 0 1 0 1 0 0 0", - " x x x x x x x a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " o o o o o o o o"; - - write_lo = " 0 1 0 0 0 0 0 0", - " x x x x x x x a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " i i i i i i i i"; - - write_hi = " 0 1 0 0 1 0 0 0", - " x x x x x x x a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " i i i i i i i i"; - - mode = 0x02; - delay = 15; - blocksize = 128; - readsize = 256; - ; - memory "signature" - size = 3; - read = "0 0 1 1 0 0 0 0 x x x x x x x x", - "x x x x x x a1 a0 o o o o o o o o"; - ; - memory "fuse" - size = 1; - ; - memory "lock" - size = 1; - min_write_delay = 9000; - max_write_delay = 20000; - write = "1 0 1 0 1 1 0 0 1 1 1 1 1 i i 1", - "x x x x x x x x x x x x x x x x"; - ; - ; - -#------------------------------------------------------------ -# AT90s4414 -#------------------------------------------------------------ - -part - id = "4414"; - desc = "AT90S4414"; - stk500_devcode = 0x50; - avr910_devcode = 0x28; - signature = 0x1e 0x92 0x01; - chip_erase_delay = 20000; - pgm_enable = "1 0 1 0 1 1 0 0 0 1 0 1 0 0 1 1", - "x x x x x x x x x x x x x x x x"; - - chip_erase = "1 0 1 0 1 1 0 0 1 0 0 0 0 0 0 0", - "x x x x x x x x x x x x x x x x"; - - timeout = 200; - stabdelay = 100; - cmdexedelay = 25; - synchloops = 32; - bytedelay = 0; - pollindex = 3; - pollvalue = 0x53; - predelay = 1; - postdelay = 1; - pollmethod = 0; - - pp_controlstack = - 0x0E, 0x1E, 0x0F, 0x1F, 0x2E, 0x3E, 0x2F, 0x3F, - 0x4E, 0x5E, 0x4F, 0x5F, 0x6E, 0x7E, 0x6F, 0x7F, - 0x66, 0x76, 0x67, 0x77, 0x6A, 0x7A, 0x6B, 0x7B, - 0xBE, 0xFD, 0x00, 0x01, 0x00, 0x00, 0x00, 0x01; - hventerstabdelay = 100; - progmodedelay = 0; - latchcycles = 0; - togglevtg = 0; - poweroffdelay = 0; - resetdelayms = 0; - resetdelayus = 0; - hvleavestabdelay = 15; - chiperasepulsewidth = 15; - chiperasepolltimeout = 0; - programfusepulsewidth = 2; - programfusepolltimeout = 0; - programlockpulsewidth = 0; - programlockpolltimeout = 1; - - memory "eeprom" - size = 256; - min_write_delay = 9000; - max_write_delay = 20000; - readback_p1 = 0x80; - readback_p2 = 0x7f; - read = " 1 0 1 0 0 0 0 0 x x x x x x x a8", - "a7 a6 a5 a4 a3 a2 a1 a0 o o o o o o o o"; - - write = " 1 1 0 0 0 0 0 0 x x x x x x x a8", - "a7 a6 a5 a4 a3 a2 a1 a0 i i i i i i i i"; - - mode = 0x04; - delay = 12; - blocksize = 64; - readsize = 256; - ; - memory "flash" - size = 4096; - min_write_delay = 9000; - max_write_delay = 20000; - readback_p1 = 0x7f; - readback_p2 = 0x7f; - read_lo = " 0 0 1 0 0 0 0 0", - " x x x x a11 a10 a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " o o o o o o o o"; - - read_hi = " 0 0 1 0 1 0 0 0", - " x x x x a11 a10 a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " o o o o o o o o"; - - write_lo = " 0 1 0 0 0 0 0 0", - " x x x x a11 a10 a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " i i i i i i i i"; - - write_hi = " 0 1 0 0 1 0 0 0", - " x x x x a11 a10 a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " i i i i i i i i"; - - mode = 0x04; - delay = 12; - blocksize = 64; - readsize = 256; - ; - memory "signature" - size = 3; - read = "0 0 1 1 0 0 0 0 x x x x x x x x", - "x x x x x x a1 a0 o o o o o o o o"; - ; - memory "fuse" - size = 1; - ; - memory "lock" - size = 1; - write = "1 0 1 0 1 1 0 0 1 1 1 1 1 i i 1", - "x x x x x x x x x x x x x x x x"; - min_write_delay = 9000; - max_write_delay = 9000; - ; - ; - -#------------------------------------------------------------ -# AT90s2313 -#------------------------------------------------------------ - -part - id = "2313"; - desc = "AT90S2313"; - stk500_devcode = 0x40; - avr910_devcode = 0x20; - signature = 0x1e 0x91 0x01; - chip_erase_delay = 20000; - pgm_enable = "1 0 1 0 1 1 0 0 0 1 0 1 0 0 1 1", - "x x x x x x x x x x x x x x x x"; - - chip_erase = "1 0 1 0 1 1 0 0 1 0 0 0 0 0 0 0", - "x x x x x x x x x x x x x x x x"; - - timeout = 200; - stabdelay = 100; - cmdexedelay = 25; - synchloops = 32; - bytedelay = 0; - pollindex = 3; - pollvalue = 0x53; - predelay = 1; - postdelay = 1; - pollmethod = 0; - - pp_controlstack = - 0x0E, 0x1E, 0x0F, 0x1F, 0x2E, 0x3E, 0x2F, 0x3F, - 0x4E, 0x5E, 0x4F, 0x5F, 0x6E, 0x7E, 0x6F, 0x7F, - 0x66, 0x76, 0x67, 0x77, 0x6A, 0x7A, 0x6B, 0x7B, - 0xBE, 0xFD, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00; - hventerstabdelay = 100; - progmodedelay = 0; - latchcycles = 0; - togglevtg = 0; - poweroffdelay = 0; - resetdelayms = 0; - resetdelayus = 0; - hvleavestabdelay = 15; - chiperasepulsewidth = 15; - chiperasepolltimeout = 0; - programfusepulsewidth = 2; - programfusepolltimeout = 0; - programlockpulsewidth = 0; - programlockpolltimeout = 1; - - memory "eeprom" - size = 128; - min_write_delay = 4000; - max_write_delay = 9000; - readback_p1 = 0x80; - readback_p2 = 0x7f; - read = "1 0 1 0 0 0 0 0 x x x x x x x x", - "x a6 a5 a4 a3 a2 a1 a0 o o o o o o o o"; - - write = "1 1 0 0 0 0 0 0 x x x x x x x x", - "x a6 a5 a4 a3 a2 a1 a0 i i i i i i i i"; - - mode = 0x04; - delay = 12; - blocksize = 64; - readsize = 256; - ; - memory "flash" - size = 2048; - min_write_delay = 4000; - max_write_delay = 9000; - readback_p1 = 0x7f; - readback_p2 = 0x7f; - read_lo = " 0 0 1 0 0 0 0 0", - " x x x x x x a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " o o o o o o o o"; - - read_hi = " 0 0 1 0 1 0 0 0", - " x x x x x x a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " o o o o o o o o"; - - write_lo = " 0 1 0 0 0 0 0 0", - " x x x x x x a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " i i i i i i i i"; - - write_hi = " 0 1 0 0 1 0 0 0", - " x x x x x x a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " i i i i i i i i"; - - mode = 0x04; - delay = 12; - blocksize = 128; - readsize = 256; - ; - memory "signature" - size = 3; - read = "0 0 1 1 0 0 0 0 x x x x x x x x", - "x x x x x x a1 a0 o o o o o o o o"; - ; - memory "fuse" - size = 1; - ; - memory "lock" - size = 1; - write = "1 0 1 0 1 1 0 0 1 1 1 x x i i x", - "x x x x x x x x x x x x x x x x"; - min_write_delay = 9000; - max_write_delay = 9000; - ; - ; - -#------------------------------------------------------------ -# AT90s2333 -#------------------------------------------------------------ - -part - id = "2333"; -##### WARNING: No XML file for device 'AT90S2333'! ##### - desc = "AT90S2333"; - stk500_devcode = 0x42; - avr910_devcode = 0x34; - signature = 0x1e 0x91 0x05; - chip_erase_delay = 20000; - pgm_enable = "1 0 1 0 1 1 0 0 0 1 0 1 0 0 1 1", - "x x x x x x x x x x x x x x x x"; - - chip_erase = "1 0 1 0 1 1 0 0 1 0 0 0 0 0 0 0", - "x x x x x x x x x x x x x x x x"; - - timeout = 200; - stabdelay = 100; - cmdexedelay = 25; - synchloops = 32; - bytedelay = 0; - pollindex = 3; - pollvalue = 0x53; - predelay = 1; - postdelay = 1; - pollmethod = 0; - - pp_controlstack = - 0x0E, 0x1E, 0x0F, 0x1F, 0x2E, 0x3E, 0x2F, 0x3F, - 0x4E, 0x5E, 0x4F, 0x5F, 0x6E, 0x7E, 0x6F, 0x7F, - 0x66, 0x76, 0x67, 0x77, 0x6A, 0x7A, 0x6B, 0x7B, - 0xBE, 0xFD, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00; - hventerstabdelay = 100; - progmodedelay = 0; - latchcycles = 0; - togglevtg = 0; - poweroffdelay = 0; - resetdelayms = 0; - resetdelayus = 0; - hvleavestabdelay = 15; - chiperasepulsewidth = 15; - chiperasepolltimeout = 0; - programfusepulsewidth = 2; - programfusepolltimeout = 0; - programlockpulsewidth = 0; - programlockpolltimeout = 1; - - memory "eeprom" - size = 128; - min_write_delay = 9000; - max_write_delay = 20000; - readback_p1 = 0x00; - readback_p2 = 0xff; - read = "1 0 1 0 0 0 0 0 x x x x x x x x", - "x a6 a5 a4 a3 a2 a1 a0 o o o o o o o o"; - - write = "1 1 0 0 0 0 0 0 x x x x x x x x", - "x a6 a5 a4 a3 a2 a1 a0 i i i i i i i i"; - - mode = 0x04; - delay = 12; - blocksize = 128; - readsize = 256; - ; - - memory "flash" - size = 2048; - min_write_delay = 9000; - max_write_delay = 20000; - readback_p1 = 0xff; - readback_p2 = 0xff; - read_lo = " 0 0 1 0 0 0 0 0", - " x x x x x x a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " o o o o o o o o"; - - read_hi = " 0 0 1 0 1 0 0 0", - " x x x x x x a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " o o o o o o o o"; - - write_lo = " 0 1 0 0 0 0 0 0", - " x x x x x x a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " i i i i i i i i"; - - write_hi = " 0 1 0 0 1 0 0 0", - " x x x x x x a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " i i i i i i i i"; - - mode = 0x04; - delay = 12; - blocksize = 128; - readsize = 256; - ; - - memory "signature" - size = 3; - read = "0 0 1 1 0 0 0 0 x x x x x x x x", - "x x x x x x a1 a0 o o o o o o o o"; - ; - memory "fuse" - size = 1; - min_write_delay = 9000; - max_write_delay = 20000; - pwroff_after_write = yes; - read = "0 1 0 1 0 0 0 0 x x x x x x x x", - "x x x x x x x x x x o o o o o o"; - - write = "1 0 1 0 1 1 0 0 1 0 1 i i i i i", - "x x x x x x x x x x x x x x x x"; - ; - memory "lock" - size = 1; - min_write_delay = 9000; - max_write_delay = 20000; - read = "0 1 0 1 1 0 0 0 x x x x x x x x", - "x x x x x x x x x x x x x o o x"; - - write = "1 0 1 0 1 1 0 0 1 1 1 1 1 i i 1", - "x x x x x x x x x x x x x x x x"; - ; - ; - - -#------------------------------------------------------------ -# AT90s2343 (also AT90s2323 and ATtiny22) -#------------------------------------------------------------ - -part - id = "2343"; - desc = "AT90S2343"; - stk500_devcode = 0x43; - avr910_devcode = 0x4c; - signature = 0x1e 0x91 0x03; - chip_erase_delay = 18000; - pgm_enable = "1 0 1 0 1 1 0 0 0 1 0 1 0 0 1 1", - "x x x x x x x x x x x x x x x x"; - - chip_erase = "1 0 1 0 1 1 0 0 1 0 0 x x x x x", - "x x x x x x x x x x x x x x x x"; - - timeout = 200; - stabdelay = 100; - cmdexedelay = 25; - synchloops = 32; - bytedelay = 0; - pollindex = 3; - pollvalue = 0x53; - predelay = 1; - postdelay = 1; - pollmethod = 0; - - hvsp_controlstack = - 0x4C, 0x0C, 0x1C, 0x2C, 0x3C, 0x64, 0x74, 0x00, - 0x68, 0x78, 0x68, 0x68, 0x00, 0x00, 0x68, 0x78, - 0x78, 0x00, 0x6D, 0x0C, 0x80, 0x40, 0x20, 0x10, - 0x11, 0x08, 0x04, 0x02, 0x03, 0x08, 0x04, 0x00; - hventerstabdelay = 100; - hvspcmdexedelay = 0; - synchcycles = 6; - latchcycles = 1; - togglevtg = 0; - poweroffdelay = 25; - resetdelayms = 0; - resetdelayus = 50; - hvleavestabdelay = 100; - resetdelay = 25; - chiperasepolltimeout = 40; - chiperasetime = 0; - programfusepolltimeout = 25; - programlockpolltimeout = 25; - - memory "eeprom" - size = 128; - min_write_delay = 9000; - max_write_delay = 20000; - readback_p1 = 0x00; - readback_p2 = 0xff; - read = "1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0", - "x a6 a5 a4 a3 a2 a1 a0 o o o o o o o o"; - - write = "1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0", - "x a6 a5 a4 a3 a2 a1 a0 i i i i i i i i"; - - mode = 0x04; - delay = 12; - blocksize = 64; - readsize = 256; - ; - memory "flash" - size = 2048; - min_write_delay = 9000; - max_write_delay = 20000; - readback_p1 = 0xff; - readback_p2 = 0xff; - read_lo = " 0 0 1 0 0 0 0 0", - " x x x x x x a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " o o o o o o o o"; - - read_hi = " 0 0 1 0 1 0 0 0", - " x x x x x x a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " o o o o o o o o"; - - write_lo = " 0 1 0 0 0 0 0 0", - " x x x x x x a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " i i i i i i i i"; - - write_hi = " 0 1 0 0 1 0 0 0", - " x x x x x x a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " i i i i i i i i"; - - mode = 0x04; - delay = 12; - blocksize = 128; - readsize = 128; - ; - memory "signature" - size = 3; - read = "0 0 1 1 0 0 0 0 x x x x x x x x", - "x x x x x x a1 a0 o o o o o o o o"; - ; - memory "fuse" - size = 1; - min_write_delay = 9000; - max_write_delay = 20000; - read = "0 1 0 1 1 0 0 0 x x x x x x x x", - "x x x x x x x x o o o x x x x o"; - - write = "1 0 1 0 1 1 0 0 1 0 1 1 1 1 1 i", - "x x x x x x x x x x x x x x x x"; - ; - memory "lock" - size = 1; - min_write_delay = 9000; - max_write_delay = 20000; - read = "0 1 0 1 1 0 0 0 x x x x x x x x", - "x x x x x x x x o o o x x x x o"; - - write = "1 0 1 0 1 1 0 0 1 1 1 1 1 i i 1", - "x x x x x x x x x x x x x x x x"; - ; - ; - - -#------------------------------------------------------------ -# AT90s4433 -#------------------------------------------------------------ - -part - id = "4433"; - desc = "AT90S4433"; - stk500_devcode = 0x51; - avr910_devcode = 0x30; - signature = 0x1e 0x92 0x03; - chip_erase_delay = 20000; - pgm_enable = "1 0 1 0 1 1 0 0 0 1 0 1 0 0 1 1", - "x x x x x x x x x x x x x x x x"; - - chip_erase = "1 0 1 0 1 1 0 0 1 0 0 0 0 0 0 0", - "x x x x x x x x x x x x x x x x"; - - timeout = 200; - stabdelay = 100; - cmdexedelay = 25; - synchloops = 32; - bytedelay = 0; - pollindex = 3; - pollvalue = 0x53; - predelay = 1; - postdelay = 1; - pollmethod = 0; - - pp_controlstack = - 0x0E, 0x1E, 0x0F, 0x1F, 0x2E, 0x3E, 0x2F, 0x3F, - 0x4E, 0x5E, 0x4F, 0x5F, 0x6E, 0x7E, 0x6F, 0x7F, - 0x66, 0x76, 0x67, 0x77, 0x6A, 0x7A, 0x6B, 0x7B, - 0xBE, 0xFD, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00; - hventerstabdelay = 100; - progmodedelay = 0; - latchcycles = 0; - togglevtg = 0; - poweroffdelay = 0; - resetdelayms = 0; - resetdelayus = 0; - hvleavestabdelay = 15; - chiperasepulsewidth = 15; - chiperasepolltimeout = 0; - programfusepulsewidth = 2; - programfusepolltimeout = 0; - programlockpulsewidth = 0; - programlockpolltimeout = 1; - - memory "eeprom" - size = 256; - min_write_delay = 9000; - max_write_delay = 20000; - readback_p1 = 0x00; - readback_p2 = 0xff; - read = " 1 0 1 0 0 0 0 0 x x x x x x x x", - "a7 a6 a5 a4 a3 a2 a1 a0 o o o o o o o o"; - - write = " 1 1 0 0 0 0 0 0 x x x x x x x x", - "a7 a6 a5 a4 a3 a2 a1 a0 i i i i i i i i"; - - mode = 0x04; - delay = 12; - blocksize = 128; - readsize = 256; - ; - memory "flash" - size = 4096; - min_write_delay = 9000; - max_write_delay = 20000; - readback_p1 = 0xff; - readback_p2 = 0xff; - read_lo = " 0 0 1 0 0 0 0 0", - " x x x x x a10 a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " o o o o o o o o"; - - read_hi = " 0 0 1 0 1 0 0 0", - " x x x x x a10 a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " o o o o o o o o"; - - write_lo = " 0 1 0 0 0 0 0 0", - " x x x x x a10 a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " i i i i i i i i"; - - write_hi = " 0 1 0 0 1 0 0 0", - " x x x x x a10 a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " i i i i i i i i"; - - mode = 0x04; - delay = 12; - blocksize = 128; - readsize = 256; - ; - memory "signature" - size = 3; - read = "0 0 1 1 0 0 0 0 x x x x x x x x", - "x x x x x x a1 a0 o o o o o o o o"; - ; - memory "fuse" - size = 1; - min_write_delay = 9000; - max_write_delay = 20000; - pwroff_after_write = yes; - read = "0 1 0 1 0 0 0 0 x x x x x x x x", - "x x x x x x x x x x o o o o o o"; - - write = "1 0 1 0 1 1 0 0 1 0 1 i i i i i", - "x x x x x x x x x x x x x x x x"; - ; - memory "lock" - size = 1; - min_write_delay = 9000; - max_write_delay = 20000; - read = "0 1 0 1 1 0 0 0 x x x x x x x x", - "x x x x x x x x x x x x x o o x"; - - write = "1 0 1 0 1 1 0 0 1 1 1 1 1 i i 1", - "x x x x x x x x x x x x x x x x"; - ; - ; - -#------------------------------------------------------------ -# AT90s4434 -#------------------------------------------------------------ - -part - id = "4434"; -##### WARNING: No XML file for device 'AT90S4434'! ##### - desc = "AT90S4434"; - stk500_devcode = 0x52; - avr910_devcode = 0x6c; - signature = 0x1e 0x92 0x02; - chip_erase_delay = 20000; - pgm_enable = "1 0 1 0 1 1 0 0 0 1 0 1 0 0 1 1", - "x x x x x x x x x x x x x x x x"; - - chip_erase = "1 0 1 0 1 1 0 0 1 0 0 0 0 0 0 0", - "x x x x x x x x x x x x x x x x"; - - memory "eeprom" - size = 256; - min_write_delay = 9000; - max_write_delay = 20000; - readback_p1 = 0x00; - readback_p2 = 0xff; - read = " 1 0 1 0 0 0 0 0 x x x x x x x x", - "a7 a6 a5 a4 a3 a2 a1 a0 o o o o o o o o"; - - write = " 1 1 0 0 0 0 0 0 x x x x x x x x", - "a7 a6 a5 a4 a3 a2 a1 a0 i i i i i i i i"; - ; - memory "flash" - size = 4096; - min_write_delay = 9000; - max_write_delay = 20000; - readback_p1 = 0xff; - readback_p2 = 0xff; - read_lo = " 0 0 1 0 0 0 0 0", - " x x x x x a10 a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " o o o o o o o o"; - - read_hi = " 0 0 1 0 1 0 0 0", - " x x x x x a10 a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " o o o o o o o o"; - - write_lo = " 0 1 0 0 0 0 0 0", - " x x x x x a10 a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " i i i i i i i i"; - - write_hi = " 0 1 0 0 1 0 0 0", - " x x x x x a10 a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " i i i i i i i i"; - ; - memory "signature" - size = 3; - read = "0 0 1 1 0 0 0 0 x x x x x x x x", - "x x x x x x a1 a0 o o o o o o o o"; - ; - memory "fuse" - size = 1; - min_write_delay = 9000; - max_write_delay = 20000; - read = "0 1 0 1 0 0 0 0 x x x x x x x x", - "x x x x x x x x x x o o o o o o"; - - write = "1 0 1 0 1 1 0 0 1 0 1 i i i i i", - "x x x x x x x x x x x x x x x x"; - ; - memory "lock" - size = 1; - min_write_delay = 9000; - max_write_delay = 20000; - read = "0 1 0 1 1 0 0 0 x x x x x x x x", - "x x x x x x x x x x x x x o o x"; - - write = "1 0 1 0 1 1 0 0 1 1 1 1 1 i i 1", - "x x x x x x x x x x x x x x x x"; - ; - ; - -#------------------------------------------------------------ -# AT90s8515 -#------------------------------------------------------------ - -part - id = "8515"; - desc = "AT90S8515"; - stk500_devcode = 0x60; - avr910_devcode = 0x38; - signature = 0x1e 0x93 0x01; - chip_erase_delay = 20000; - pgm_enable = "1 0 1 0 1 1 0 0 0 1 0 1 0 0 1 1", - "x x x x x x x x x x x x x x x x"; - - chip_erase = "1 0 1 0 1 1 0 0 1 0 0 x x x x x", - "x x x x x x x x x x x x x x x x"; - - timeout = 200; - stabdelay = 100; - cmdexedelay = 25; - synchloops = 32; - bytedelay = 0; - pollindex = 3; - pollvalue = 0x53; - predelay = 1; - postdelay = 1; - pollmethod = 0; - - pp_controlstack = - 0x0E, 0x1E, 0x0F, 0x1F, 0x2E, 0x3E, 0x2F, 0x3F, - 0x4E, 0x5E, 0x4F, 0x5F, 0x6E, 0x7E, 0x6F, 0x7F, - 0x66, 0x76, 0x67, 0x77, 0x6A, 0x7A, 0x6B, 0x7B, - 0xBE, 0xFD, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00; - hventerstabdelay = 100; - progmodedelay = 0; - latchcycles = 0; - togglevtg = 0; - poweroffdelay = 0; - resetdelayms = 0; - resetdelayus = 0; - hvleavestabdelay = 15; - resetdelay = 15; - chiperasepulsewidth = 15; - chiperasepolltimeout = 0; - programfusepulsewidth = 2; - programfusepolltimeout = 0; - programlockpulsewidth = 0; - programlockpolltimeout = 1; - - memory "eeprom" - size = 512; - min_write_delay = 4000; - max_write_delay = 9000; - readback_p1 = 0x80; - readback_p2 = 0x7f; - read = " 1 0 1 0 0 0 0 0 x x x x x x x a8", - "a7 a6 a5 a4 a3 a2 a1 a0 o o o o o o o o"; - - write = " 1 1 0 0 0 0 0 0 x x x x x x x a8", - "a7 a6 a5 a4 a3 a2 a1 a0 i i i i i i i i"; - - mode = 0x04; - delay = 12; - blocksize = 128; - readsize = 256; - ; - memory "flash" - size = 8192; - min_write_delay = 4000; - max_write_delay = 9000; - readback_p1 = 0x7f; - readback_p2 = 0x7f; - read_lo = " 0 0 1 0 0 0 0 0", - " x x x x a11 a10 a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " o o o o o o o o"; - - read_hi = " 0 0 1 0 1 0 0 0", - " x x x x a11 a10 a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " o o o o o o o o"; - - write_lo = " 0 1 0 0 0 0 0 0", - " x x x x a11 a10 a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " i i i i i i i i"; - - write_hi = " 0 1 0 0 1 0 0 0", - " x x x x a11 a10 a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " i i i i i i i i"; - - mode = 0x04; - delay = 12; - blocksize = 128; - readsize = 256; - ; - memory "signature" - size = 3; - read = "0 0 1 1 0 0 0 0 x x x x x x x x", - "x x x x x x a1 a0 o o o o o o o o"; - ; - memory "fuse" - size = 1; - ; - memory "lock" - size = 1; - write = "1 0 1 0 1 1 0 0 1 1 1 1 1 i i 1", - "x x x x x x x x x x x x x x x x"; - min_write_delay = 9000; - max_write_delay = 9000; - ; - ; - -#------------------------------------------------------------ -# AT90s8535 -#------------------------------------------------------------ - -part - id = "8535"; - desc = "AT90S8535"; - stk500_devcode = 0x61; - avr910_devcode = 0x68; - signature = 0x1e 0x93 0x03; - chip_erase_delay = 20000; - pgm_enable = "1 0 1 0 1 1 0 0 0 1 0 1 0 0 1 1", - "x x x x x x x x x x x x x x x x"; - - chip_erase = "1 0 1 0 1 1 0 0 1 0 0 0 0 0 0 0", - "x x x x x x x x x x x x x x x x"; - - timeout = 200; - stabdelay = 100; - cmdexedelay = 25; - synchloops = 32; - bytedelay = 0; - pollindex = 3; - pollvalue = 0x53; - predelay = 1; - postdelay = 1; - pollmethod = 0; - - pp_controlstack = - 0x0E, 0x1E, 0x0F, 0x1F, 0x2E, 0x3E, 0x2F, 0x3F, - 0x4E, 0x5E, 0x4F, 0x5F, 0x6E, 0x7E, 0x6F, 0x7F, - 0x66, 0x76, 0x67, 0x77, 0x6A, 0x7A, 0x6B, 0x7B, - 0xBE, 0xFD, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00; - hventerstabdelay = 100; - progmodedelay = 0; - latchcycles = 0; - togglevtg = 0; - poweroffdelay = 0; - resetdelayms = 0; - resetdelayus = 0; - hvleavestabdelay = 15; - chiperasepulsewidth = 15; - chiperasepolltimeout = 0; - programfusepulsewidth = 2; - programfusepolltimeout = 0; - programlockpulsewidth = 0; - programlockpolltimeout = 1; - - memory "eeprom" - size = 512; - min_write_delay = 9000; - max_write_delay = 20000; - readback_p1 = 0x00; - readback_p2 = 0xff; - read = " 1 0 1 0 0 0 0 0 x x x x x x x a8", - "a7 a6 a5 a4 a3 a2 a1 a0 o o o o o o o o"; - - write = " 1 1 0 0 0 0 0 0 x x x x x x x a8", - "a7 a6 a5 a4 a3 a2 a1 a0 i i i i i i i i"; - - mode = 0x04; - delay = 12; - blocksize = 128; - readsize = 256; - ; - memory "flash" - size = 8192; - min_write_delay = 9000; - max_write_delay = 20000; - readback_p1 = 0xff; - readback_p2 = 0xff; - read_lo = " 0 0 1 0 0 0 0 0", - " x x x x a11 a10 a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " o o o o o o o o"; - - read_hi = " 0 0 1 0 1 0 0 0", - " x x x x a11 a10 a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " o o o o o o o o"; - - write_lo = " 0 1 0 0 0 0 0 0", - " x x x x a11 a10 a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " i i i i i i i i"; - - write_hi = " 0 1 0 0 1 0 0 0", - " x x x x a11 a10 a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " i i i i i i i i"; - - mode = 0x04; - delay = 12; - blocksize = 128; - readsize = 256; - ; - memory "signature" - size = 3; - read = "0 0 1 1 0 0 0 0 x x x x x x x x", - "x x x x x x a1 a0 o o o o o o o o"; - ; - memory "fuse" - size = 1; - read = "0 1 0 1 1 0 0 0 x x x x x x x x", - "x x x x x x x x x x x x x x x o"; - write = "1 0 1 0 1 1 0 0 1 0 1 1 1 1 1 i", - "x x x x x x x x x x x x x x x x"; - min_write_delay = 9000; - max_write_delay = 9000; - ; - memory "lock" - size = 1; - read = "0 1 0 1 1 0 0 0 x x x x x x x x", - "x x x x x x x x o o x x x x x x"; - write = "1 0 1 0 1 1 0 0 1 1 1 1 1 i i 1", - "x x x x x x x x x x x x x x x x"; - min_write_delay = 9000; - max_write_delay = 9000; - ; - ; - -#------------------------------------------------------------ -# ATmega103 -#------------------------------------------------------------ - -part - id = "m103"; - desc = "ATmega103"; - stk500_devcode = 0xB1; - avr910_devcode = 0x41; - signature = 0x1e 0x97 0x01; - chip_erase_delay = 112000; - pgm_enable = "1 0 1 0 1 1 0 0 0 1 0 1 0 0 1 1", - "x x x x x x x x x x x x x x x x"; - - chip_erase = "1 0 1 0 1 1 0 0 1 0 0 0 0 0 0 0", - "x x x x x x x x x x x x x x x x"; - - timeout = 200; - stabdelay = 100; - cmdexedelay = 25; - synchloops = 32; - bytedelay = 0; - pollindex = 3; - pollvalue = 0x53; - predelay = 1; - postdelay = 1; - pollmethod = 0; - - pp_controlstack = - 0x0E, 0x1E, 0x8E, 0x9E, 0x2E, 0x3E, 0xAE, 0xBE, - 0x4E, 0x5E, 0xCE, 0xDE, 0x6E, 0x7E, 0xEE, 0xDE, - 0x66, 0x76, 0xE6, 0xF6, 0x6A, 0x7A, 0xEA, 0x7A, - 0x7F, 0xFD, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00; - hventerstabdelay = 100; - progmodedelay = 0; - latchcycles = 0; - togglevtg = 0; - poweroffdelay = 0; - resetdelayms = 0; - resetdelayus = 0; - hvleavestabdelay = 15; - chiperasepulsewidth = 15; - chiperasepolltimeout = 0; - programfusepulsewidth = 2; - programfusepolltimeout = 0; - programlockpulsewidth = 0; - programlockpolltimeout = 10; - - memory "eeprom" - size = 4096; - min_write_delay = 4000; - max_write_delay = 9000; - readback_p1 = 0x80; - readback_p2 = 0x7f; - read = " 1 0 1 0 0 0 0 0", - " x x x x a11 a10 a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " o o o o o o o o"; - - write = " 1 1 0 0 0 0 0 0", - " x x x x a11 a10 a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " i i i i i i i i"; - - mode = 0x04; - delay = 12; - blocksize = 64; - readsize = 256; - ; - - memory "flash" - paged = yes; - size = 131072; - page_size = 256; - num_pages = 512; - min_write_delay = 22000; - max_write_delay = 56000; - readback_p1 = 0xff; - readback_p2 = 0xff; - read_lo = " 0 0 1 0 0 0 0 0", - "a15 a14 a13 a12 a11 a10 a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " o o o o o o o o"; - - read_hi = " 0 0 1 0 1 0 0 0", - "a15 a14 a13 a12 a11 a10 a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " o o o o o o o o"; - - loadpage_lo = " 0 1 0 0 0 0 0 0", - " x x x x x x x x", - " x a6 a5 a4 a3 a2 a1 a0", - " i i i i i i i i"; - - loadpage_hi = " 0 1 0 0 1 0 0 0", - " x x x x x x x x", - " x a6 a5 a4 a3 a2 a1 a0", - " i i i i i i i i"; - - writepage = " 0 1 0 0 1 1 0 0", - "a15 a14 a13 a12 a11 a10 a9 a8", - " a7 x x x x x x x", - " x x x x x x x x"; - - mode = 0x11; - delay = 70; - blocksize = 256; - readsize = 256; - ; - - memory "fuse" - size = 1; - read = "0 1 0 1 0 0 0 0 x x x x x x x x", - "x x x x x x x x x x o x o 1 o o"; - - write = "1 0 1 0 1 1 0 0 1 0 1 1 i 1 i i", - "x x x x x x x x x x x x x x x x"; - min_write_delay = 9000; - max_write_delay = 9000; - ; - - memory "lock" - size = 1; - read = "0 1 0 1 1 0 0 0 x x x x x x x x", - "x x x x x x x x x x x x x o o x"; - - write = "1 0 1 0 1 1 0 0 1 1 1 1 1 i i 1", - "x x x x x x x x x x x x x x x x"; - min_write_delay = 9000; - max_write_delay = 9000; - ; - - memory "signature" - size = 3; - read = "0 0 1 1 0 0 0 0 x x x x x x x x", - "x x x x x x a1 a0 o o o o o o o o"; - ; - ; - - -#------------------------------------------------------------ -# ATmega64 -#------------------------------------------------------------ - -part - id = "m64"; - desc = "ATmega64"; - has_jtag = yes; - stk500_devcode = 0xA0; - avr910_devcode = 0x45; - signature = 0x1e 0x96 0x02; - chip_erase_delay = 9000; - pagel = 0xD7; - bs2 = 0xA0; - reset = dedicated; - pgm_enable = "1 0 1 0 1 1 0 0 0 1 0 1 0 0 1 1", - "x x x x x x x x x x x x x x x x"; - - chip_erase = "1 0 1 0 1 1 0 0 1 0 0 0 0 0 0 0", - "x x x x x x x x x x x x x x x x"; - - timeout = 200; - stabdelay = 100; - cmdexedelay = 25; - synchloops = 32; - bytedelay = 0; - pollindex = 3; - pollvalue = 0x53; - predelay = 1; - postdelay = 1; - pollmethod = 0; - - pp_controlstack = - 0x0E, 0x1E, 0x0F, 0x1F, 0x2E, 0x3E, 0x2F, 0x3F, - 0x4E, 0x5E, 0x4F, 0x5F, 0x6E, 0x7E, 0x6F, 0x7F, - 0x66, 0x76, 0x67, 0x77, 0x6A, 0x7A, 0x6B, 0x7B, - 0xBE, 0xFD, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00; - hventerstabdelay = 100; - progmodedelay = 0; - latchcycles = 6; - togglevtg = 0; - poweroffdelay = 0; - resetdelayms = 0; - resetdelayus = 0; - hvleavestabdelay = 15; - chiperasepulsewidth = 0; - chiperasepolltimeout = 10; - programfusepulsewidth = 0; - programfusepolltimeout = 5; - programlockpulsewidth = 0; - programlockpolltimeout = 5; - - idr = 0x22; - spmcr = 0x68; - allowfullpagebitstream = yes; - - ocdrev = 2; - - memory "eeprom" - paged = no; /* leave this "no" */ - page_size = 8; /* for parallel programming */ - size = 2048; - min_write_delay = 9000; - max_write_delay = 9000; - readback_p1 = 0xff; - readback_p2 = 0xff; - read = " 1 0 1 0 0 0 0 0", - " x x x x a11 a10 a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " o o o o o o o o"; - - write = " 1 1 0 0 0 0 0 0", - " x x x x a11 a10 a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " i i i i i i i i"; - - mode = 0x04; - delay = 20; - blocksize = 64; - readsize = 256; - ; - - memory "flash" - paged = yes; - size = 65536; - page_size = 256; - num_pages = 256; - min_write_delay = 4500; - max_write_delay = 4500; - readback_p1 = 0xff; - readback_p2 = 0xff; - read_lo = " 0 0 1 0 0 0 0 0", - " x a14 a13 a12 a11 a10 a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " o o o o o o o o"; - - read_hi = " 0 0 1 0 1 0 0 0", - " x a14 a13 a12 a11 a10 a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " o o o o o o o o"; - - - loadpage_lo = " 0 1 0 0 0 0 0 0", - " x x x x x x x x", - " x a6 a5 a4 a3 a2 a1 a0", - " i i i i i i i i"; - - loadpage_hi = " 0 1 0 0 1 0 0 0", - " x x x x x x x x", - " x a6 a5 a4 a3 a2 a1 a0", - " i i i i i i i i"; - - writepage = " 0 1 0 0 1 1 0 0", - " x a14 a13 a12 a11 a10 a9 a8", - " a7 x x x x x x x", - " x x x x x x x x"; - - mode = 0x21; - delay = 6; - blocksize = 128; - readsize = 256; - ; - - memory "lfuse" - size = 1; - write = "1 0 1 0 1 1 0 0 1 0 1 0 0 0 0 0", - "x x x x x x x x i i i i i i i i"; - - read = "0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0", - "x x x x x x x x o o o o o o o o"; - min_write_delay = 9000; - max_write_delay = 9000; - ; - - memory "hfuse" - size = 1; - write = "1 0 1 0 1 1 0 0 1 0 1 0 1 0 0 0", - "x x x x x x x x i i i i i i i i"; - - read = "0 1 0 1 1 0 0 0 0 0 0 0 1 0 0 0", - "x x x x x x x x o o o o o o o o"; - min_write_delay = 9000; - max_write_delay = 9000; - ; - - memory "efuse" - size = 1; - write = "1 0 1 0 1 1 0 0 1 0 1 0 0 1 0 0", - "x x x x x x x x x x x x x x i i"; - - read = "0 1 0 1 0 0 0 0 0 0 0 0 1 0 0 0", - "x x x x x x x x o o o o o o o o"; - min_write_delay = 9000; - max_write_delay = 9000; - ; - - memory "lock" - size = 1; - read = "0 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0", - "x x x x x x x x x x o o o o o o"; - - write = "1 0 1 0 1 1 0 0 1 1 1 x x x x x", - "x x x x x x x x 1 1 i i i i i i"; - min_write_delay = 9000; - max_write_delay = 9000; - ; - - memory "calibration" - size = 4; - read = "0 0 1 1 1 0 0 0 x x x x x x x x", - "0 0 0 0 0 0 a1 a0 o o o o o o o o"; - ; - - memory "signature" - size = 3; - read = "0 0 1 1 0 0 0 0 x x x x x x x x", - "x x x x x x a1 a0 o o o o o o o o"; - ; - ; - - - - -#------------------------------------------------------------ -# ATmega128 -#------------------------------------------------------------ - -part - id = "m128"; - desc = "ATmega128"; - has_jtag = yes; - stk500_devcode = 0xB2; - avr910_devcode = 0x43; - signature = 0x1e 0x97 0x02; - chip_erase_delay = 9000; - pagel = 0xD7; - bs2 = 0xA0; - reset = dedicated; - pgm_enable = "1 0 1 0 1 1 0 0 0 1 0 1 0 0 1 1", - "x x x x x x x x x x x x x x x x"; - - chip_erase = "1 0 1 0 1 1 0 0 1 0 0 0 0 0 0 0", - "x x x x x x x x x x x x x x x x"; - - timeout = 200; - stabdelay = 100; - cmdexedelay = 25; - synchloops = 32; - bytedelay = 0; - pollindex = 3; - pollvalue = 0x53; - predelay = 1; - postdelay = 1; - pollmethod = 0; - - pp_controlstack = - 0x0E, 0x1E, 0x0F, 0x1F, 0x2E, 0x3E, 0x2F, 0x3F, - 0x4E, 0x5E, 0x4F, 0x5F, 0x6E, 0x7E, 0x6F, 0x7F, - 0x66, 0x76, 0x67, 0x77, 0x6A, 0x7A, 0x6B, 0x7B, - 0xBE, 0xFD, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00; - hventerstabdelay = 100; - progmodedelay = 0; - latchcycles = 6; - togglevtg = 0; - poweroffdelay = 0; - resetdelayms = 0; - resetdelayus = 0; - hvleavestabdelay = 15; - chiperasepulsewidth = 0; - chiperasepolltimeout = 10; - programfusepulsewidth = 0; - programfusepolltimeout = 5; - programlockpulsewidth = 0; - programlockpolltimeout = 5; - - idr = 0x22; - spmcr = 0x68; - rampz = 0x3b; - allowfullpagebitstream = yes; - - ocdrev = 1; - - memory "eeprom" - paged = no; /* leave this "no" */ - page_size = 8; /* for parallel programming */ - size = 4096; - min_write_delay = 9000; - max_write_delay = 9000; - readback_p1 = 0xff; - readback_p2 = 0xff; - read = " 1 0 1 0 0 0 0 0", - " x x x x a11 a10 a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " o o o o o o o o"; - - write = " 1 1 0 0 0 0 0 0", - " x x x x a11 a10 a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " i i i i i i i i"; - - mode = 0x04; - delay = 12; - blocksize = 64; - readsize = 256; - ; - - memory "flash" - paged = yes; - size = 131072; - page_size = 256; - num_pages = 512; - min_write_delay = 4500; - max_write_delay = 4500; - readback_p1 = 0xff; - readback_p2 = 0xff; - read_lo = " 0 0 1 0 0 0 0 0", - "a15 a14 a13 a12 a11 a10 a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " o o o o o o o o"; - - read_hi = " 0 0 1 0 1 0 0 0", - "a15 a14 a13 a12 a11 a10 a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " o o o o o o o o"; - - loadpage_lo = " 0 1 0 0 0 0 0 0", - " x x x x x x x x", - " x a6 a5 a4 a3 a2 a1 a0", - " i i i i i i i i"; - - loadpage_hi = " 0 1 0 0 1 0 0 0", - " x x x x x x x x", - " x a6 a5 a4 a3 a2 a1 a0", - " i i i i i i i i"; - - writepage = " 0 1 0 0 1 1 0 0", - "a15 a14 a13 a12 a11 a10 a9 a8", - " a7 x x x x x x x", - " x x x x x x x x"; - - mode = 0x21; - delay = 6; - blocksize = 128; - readsize = 256; - ; - - memory "lfuse" - size = 1; - write = "1 0 1 0 1 1 0 0 1 0 1 0 0 0 0 0", - "x x x x x x x x i i i i i i i i"; - - read = "0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0", - "x x x x x x x x o o o o o o o o"; - min_write_delay = 9000; - max_write_delay = 9000; - ; - - memory "hfuse" - size = 1; - write = "1 0 1 0 1 1 0 0 1 0 1 0 1 0 0 0", - "x x x x x x x x i i i i i i i i"; - - read = "0 1 0 1 1 0 0 0 0 0 0 0 1 0 0 0", - "x x x x x x x x o o o o o o o o"; - min_write_delay = 9000; - max_write_delay = 9000; - ; - - memory "efuse" - size = 1; - write = "1 0 1 0 1 1 0 0 1 0 1 0 0 1 0 0", - "x x x x x x x x x x x x x x i i"; - - read = "0 1 0 1 0 0 0 0 0 0 0 0 1 0 0 0", - "x x x x x x x x o o o o o o o o"; - min_write_delay = 9000; - max_write_delay = 9000; - ; - - memory "lock" - size = 1; - read = "0 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0", - "x x x x x x x x x x o o o o o o"; - - write = "1 0 1 0 1 1 0 0 1 1 1 x x x x x", - "x x x x x x x x 1 1 i i i i i i"; - min_write_delay = 9000; - max_write_delay = 9000; - ; - - memory "calibration" - size = 4; - read = "0 0 1 1 1 0 0 0 x x x x x x x x", - "0 0 0 0 0 0 a1 a0 o o o o o o o o"; - ; - - memory "signature" - size = 3; - read = "0 0 1 1 0 0 0 0 x x x x x x x x", - "x x x x x x a1 a0 o o o o o o o o"; - ; - ; - -#------------------------------------------------------------ -# AT90CAN128 -#------------------------------------------------------------ - -part - id = "c128"; - desc = "AT90CAN128"; - has_jtag = yes; - stk500_devcode = 0xB3; -# avr910_devcode = 0x43; - signature = 0x1e 0x97 0x81; - chip_erase_delay = 9000; - pagel = 0xD7; - bs2 = 0xA0; - reset = dedicated; - pgm_enable = "1 0 1 0 1 1 0 0 0 1 0 1 0 0 1 1", - "x x x x x x x x x x x x x x x x"; - - chip_erase = "1 0 1 0 1 1 0 0 1 0 0 x x x x x", - "x x x x x x x x x x x x x x x x"; - - timeout = 200; - stabdelay = 100; - cmdexedelay = 25; - synchloops = 32; - bytedelay = 0; - pollindex = 3; - pollvalue = 0x53; - predelay = 1; - postdelay = 1; - pollmethod = 1; - - pp_controlstack = - 0x0E, 0x1E, 0x0F, 0x1F, 0x2E, 0x3E, 0x2F, 0x3F, - 0x4E, 0x5E, 0x4F, 0x5F, 0x6E, 0x7E, 0x6F, 0x7F, - 0x66, 0x76, 0x67, 0x77, 0x6A, 0x7A, 0x6B, 0x7B, - 0xBE, 0xFD, 0x00, 0x01, 0x00, 0x00, 0x00, 0x01; - hventerstabdelay = 100; - progmodedelay = 0; - latchcycles = 6; - togglevtg = 0; - poweroffdelay = 0; - resetdelayms = 0; - resetdelayus = 0; - hvleavestabdelay = 15; - chiperasepulsewidth = 0; - chiperasepolltimeout = 10; - programfusepulsewidth = 0; - programfusepolltimeout = 5; - programlockpulsewidth = 0; - programlockpolltimeout = 5; - - idr = 0x31; - spmcr = 0x57; - rampz = 0x3b; - eecr = 0x3f; - allowfullpagebitstream = no; - - ocdrev = 3; - - memory "eeprom" - paged = no; /* leave this "no" */ - page_size = 8; /* for parallel programming */ - size = 4096; - min_write_delay = 9000; - max_write_delay = 9000; - readback_p1 = 0xff; - readback_p2 = 0xff; - read = " 1 0 1 0 0 0 0 0", - " 0 0 0 x a11 a10 a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " o o o o o o o o"; - - write = " 1 1 0 0 0 0 0 0", - " 0 0 0 x a11 a10 a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " i i i i i i i i"; - - loadpage_lo = " 1 1 0 0 0 0 0 1", - " 0 0 0 0 0 0 0 0", - " 0 0 0 0 0 a2 a1 a0", - " i i i i i i i i"; - - writepage = " 1 1 0 0 0 0 1 0", - " 0 0 x x a11 a10 a9 a8", - " a7 a6 a5 a4 a3 0 0 0", - " x x x x x x x x"; - - - mode = 0x41; - delay = 20; - blocksize = 8; - readsize = 256; - ; - - memory "flash" - paged = yes; - size = 131072; - page_size = 256; - num_pages = 512; - min_write_delay = 4500; - max_write_delay = 4500; - readback_p1 = 0xff; - readback_p2 = 0xff; - read_lo = " 0 0 1 0 0 0 0 0", - "a15 a14 a13 a12 a11 a10 a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " o o o o o o o o"; - - read_hi = " 0 0 1 0 1 0 0 0", - "a15 a14 a13 a12 a11 a10 a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " o o o o o o o o"; - - loadpage_lo = " 0 1 0 0 0 0 0 0", - " 0 0 0 x x x x x", - " x a6 a5 a4 a3 a2 a1 a0", - " i i i i i i i i"; - - loadpage_hi = " 0 1 0 0 1 0 0 0", - " 0 0 0 x x x x x", - " x a6 a5 a4 a3 a2 a1 a0", - " i i i i i i i i"; - - writepage = " 0 1 0 0 1 1 0 0", - "a15 a14 a13 a12 a11 a10 a9 a8", - " a7 x x x x x x x", - " x x x x x x x x"; - - mode = 0x41; - delay = 6; - blocksize = 256; - readsize = 256; - ; - - memory "lfuse" - size = 1; - write = "1 0 1 0 1 1 0 0 1 0 1 0 0 0 0 0", - "x x x x x x x x i i i i i i i i"; - - read = "0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0", - "x x x x x x x x o o o o o o o o"; - min_write_delay = 9000; - max_write_delay = 9000; - ; - - memory "hfuse" - size = 1; - write = "1 0 1 0 1 1 0 0 1 0 1 0 1 0 0 0", - "x x x x x x x x i i i i i i i i"; - - read = "0 1 0 1 1 0 0 0 0 0 0 0 1 0 0 0", - "x x x x x x x x o o o o o o o o"; - min_write_delay = 9000; - max_write_delay = 9000; - ; - - memory "efuse" - size = 1; - write = "1 0 1 0 1 1 0 0 1 0 1 0 0 1 0 0", - "x x x x x x x x x x x x i i i i"; - - read = "0 1 0 1 0 0 0 0 0 0 0 0 1 0 0 0", - "x x x x x x x x o o o o o o o o"; - min_write_delay = 9000; - max_write_delay = 9000; - ; - - memory "lock" - size = 1; - read = "0 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0", - "x x x x x x x x x x o o o o o o"; - - write = "1 0 1 0 1 1 0 0 1 1 1 x x x x x", - "x x x x x x x x 1 1 i i i i i i"; - min_write_delay = 9000; - max_write_delay = 9000; - ; - - memory "calibration" - size = 1; - read = "0 0 1 1 1 0 0 0 0 0 0 x x x x x", - "0 0 0 0 0 0 0 0 o o o o o o o o"; - ; - - memory "signature" - size = 3; - read = "0 0 1 1 0 0 0 0 x x x x x x x x", - "x x x x x x a1 a0 o o o o o o o o"; - ; - ; - -#------------------------------------------------------------ -# AT90CAN64 -#------------------------------------------------------------ - -part - id = "c64"; - desc = "AT90CAN64"; - has_jtag = yes; - stk500_devcode = 0xB3; -# avr910_devcode = 0x43; - signature = 0x1e 0x96 0x81; - chip_erase_delay = 9000; - pagel = 0xD7; - bs2 = 0xA0; - reset = dedicated; - pgm_enable = "1 0 1 0 1 1 0 0 0 1 0 1 0 0 1 1", - "x x x x x x x x x x x x x x x x"; - - chip_erase = "1 0 1 0 1 1 0 0 1 0 0 x x x x x", - "x x x x x x x x x x x x x x x x"; - - timeout = 200; - stabdelay = 100; - cmdexedelay = 25; - synchloops = 32; - bytedelay = 0; - pollindex = 3; - pollvalue = 0x53; - predelay = 1; - postdelay = 1; - pollmethod = 1; - - pp_controlstack = - 0x0E, 0x1E, 0x0F, 0x1F, 0x2E, 0x3E, 0x2F, 0x3F, - 0x4E, 0x5E, 0x4F, 0x5F, 0x6E, 0x7E, 0x6F, 0x7F, - 0x66, 0x76, 0x67, 0x77, 0x6A, 0x7A, 0x6B, 0x7B, - 0xBE, 0xFD, 0x00, 0x01, 0x00, 0x00, 0x00, 0x01; - hventerstabdelay = 100; - progmodedelay = 0; - latchcycles = 6; - togglevtg = 0; - poweroffdelay = 0; - resetdelayms = 0; - resetdelayus = 0; - hvleavestabdelay = 15; - chiperasepulsewidth = 0; - chiperasepolltimeout = 10; - programfusepulsewidth = 0; - programfusepolltimeout = 5; - programlockpulsewidth = 0; - programlockpolltimeout = 5; - - idr = 0x31; - spmcr = 0x57; - rampz = 0x3b; - eecr = 0x3f; - allowfullpagebitstream = no; - - ocdrev = 3; - - memory "eeprom" - paged = no; /* leave this "no" */ - page_size = 8; /* for parallel programming */ - size = 2048; - min_write_delay = 9000; - max_write_delay = 9000; - readback_p1 = 0xff; - readback_p2 = 0xff; - read = " 1 0 1 0 0 0 0 0", - " 0 0 0 x x a10 a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " o o o o o o o o"; - - write = " 1 1 0 0 0 0 0 0", - " 0 0 0 x x a10 a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " i i i i i i i i"; - - loadpage_lo = " 1 1 0 0 0 0 0 1", - " 0 0 0 0 0 0 0 0", - " 0 0 0 0 0 a2 a1 a0", - " i i i i i i i i"; - - writepage = " 1 1 0 0 0 0 1 0", - " 0 0 x x x a10 a9 a8", - " a7 a6 a5 a4 a3 0 0 0", - " x x x x x x x x"; - - - mode = 0x41; - delay = 20; - blocksize = 8; - readsize = 256; - ; - - memory "flash" - paged = yes; - size = 65536; - page_size = 256; - num_pages = 256; - min_write_delay = 4500; - max_write_delay = 4500; - readback_p1 = 0xff; - readback_p2 = 0xff; - read_lo = " 0 0 1 0 0 0 0 0", - "a15 a14 a13 a12 a11 a10 a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " o o o o o o o o"; - - read_hi = " 0 0 1 0 1 0 0 0", - "a15 a14 a13 a12 a11 a10 a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " o o o o o o o o"; - - loadpage_lo = " 0 1 0 0 0 0 0 0", - " 0 0 0 x x x x x", - " x a6 a5 a4 a3 a2 a1 a0", - " i i i i i i i i"; - - loadpage_hi = " 0 1 0 0 1 0 0 0", - " 0 0 0 x x x x x", - " x a6 a5 a4 a3 a2 a1 a0", - " i i i i i i i i"; - - writepage = " 0 1 0 0 1 1 0 0", - "a15 a14 a13 a12 a11 a10 a9 a8", - " a7 x x x x x x x", - " x x x x x x x x"; - - mode = 0x41; - delay = 6; - blocksize = 256; - readsize = 256; - ; - - memory "lfuse" - size = 1; - write = "1 0 1 0 1 1 0 0 1 0 1 0 0 0 0 0", - "x x x x x x x x i i i i i i i i"; - - read = "0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0", - "x x x x x x x x o o o o o o o o"; - min_write_delay = 9000; - max_write_delay = 9000; - ; - - memory "hfuse" - size = 1; - write = "1 0 1 0 1 1 0 0 1 0 1 0 1 0 0 0", - "x x x x x x x x i i i i i i i i"; - - read = "0 1 0 1 1 0 0 0 0 0 0 0 1 0 0 0", - "x x x x x x x x o o o o o o o o"; - min_write_delay = 9000; - max_write_delay = 9000; - ; - - memory "efuse" - size = 1; - write = "1 0 1 0 1 1 0 0 1 0 1 0 0 1 0 0", - "x x x x x x x x x x x x i i i i"; - - read = "0 1 0 1 0 0 0 0 0 0 0 0 1 0 0 0", - "x x x x x x x x o o o o o o o o"; - min_write_delay = 9000; - max_write_delay = 9000; - ; - - memory "lock" - size = 1; - read = "0 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0", - "x x x x x x x x x x o o o o o o"; - - write = "1 0 1 0 1 1 0 0 1 1 1 x x x x x", - "x x x x x x x x 1 1 i i i i i i"; - min_write_delay = 9000; - max_write_delay = 9000; - ; - - memory "calibration" - size = 1; - read = "0 0 1 1 1 0 0 0 0 0 0 x x x x x", - "0 0 0 0 0 0 0 0 o o o o o o o o"; - ; - - memory "signature" - size = 3; - read = "0 0 1 1 0 0 0 0 x x x x x x x x", - "x x x x x x a1 a0 o o o o o o o o"; - ; - ; - -#------------------------------------------------------------ -# AT90CAN32 -#------------------------------------------------------------ - -part - id = "c32"; - desc = "AT90CAN32"; - has_jtag = yes; - stk500_devcode = 0xB3; -# avr910_devcode = 0x43; - signature = 0x1e 0x95 0x81; - chip_erase_delay = 9000; - pagel = 0xD7; - bs2 = 0xA0; - reset = dedicated; - pgm_enable = "1 0 1 0 1 1 0 0 0 1 0 1 0 0 1 1", - "x x x x x x x x x x x x x x x x"; - - chip_erase = "1 0 1 0 1 1 0 0 1 0 0 x x x x x", - "x x x x x x x x x x x x x x x x"; - - timeout = 200; - stabdelay = 100; - cmdexedelay = 25; - synchloops = 32; - bytedelay = 0; - pollindex = 3; - pollvalue = 0x53; - predelay = 1; - postdelay = 1; - pollmethod = 1; - - pp_controlstack = - 0x0E, 0x1E, 0x0F, 0x1F, 0x2E, 0x3E, 0x2F, 0x3F, - 0x4E, 0x5E, 0x4F, 0x5F, 0x6E, 0x7E, 0x6F, 0x7F, - 0x66, 0x76, 0x67, 0x77, 0x6A, 0x7A, 0x6B, 0x7B, - 0xBE, 0xFD, 0x00, 0x01, 0x00, 0x00, 0x00, 0x01; - hventerstabdelay = 100; - progmodedelay = 0; - latchcycles = 6; - togglevtg = 0; - poweroffdelay = 0; - resetdelayms = 0; - resetdelayus = 0; - hvleavestabdelay = 15; - chiperasepulsewidth = 0; - chiperasepolltimeout = 10; - programfusepulsewidth = 0; - programfusepolltimeout = 5; - programlockpulsewidth = 0; - programlockpolltimeout = 5; - - idr = 0x31; - spmcr = 0x57; - rampz = 0x3b; - eecr = 0x3f; - allowfullpagebitstream = no; - - ocdrev = 3; - - memory "eeprom" - paged = no; /* leave this "no" */ - page_size = 8; /* for parallel programming */ - size = 1024; - min_write_delay = 9000; - max_write_delay = 9000; - readback_p1 = 0xff; - readback_p2 = 0xff; - read = " 1 0 1 0 0 0 0 0", - " 0 0 0 x x x a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " o o o o o o o o"; - - write = " 1 1 0 0 0 0 0 0", - " 0 0 0 x x x a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " i i i i i i i i"; - - loadpage_lo = " 1 1 0 0 0 0 0 1", - " 0 0 0 0 0 0 0 0", - " 0 0 0 0 0 a2 a1 a0", - " i i i i i i i i"; - - writepage = " 1 1 0 0 0 0 1 0", - " 0 0 x x x x a9 a8", - " a7 a6 a5 a4 a3 0 0 0", - " x x x x x x x x"; - - - mode = 0x41; - delay = 20; - blocksize = 8; - readsize = 256; - ; - - memory "flash" - paged = yes; - size = 32768; - page_size = 256; - num_pages = 128; - min_write_delay = 4500; - max_write_delay = 4500; - readback_p1 = 0xff; - readback_p2 = 0xff; - read_lo = " 0 0 1 0 0 0 0 0", - "a15 a14 a13 a12 a11 a10 a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " o o o o o o o o"; - - read_hi = " 0 0 1 0 1 0 0 0", - "a15 a14 a13 a12 a11 a10 a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " o o o o o o o o"; - - loadpage_lo = " 0 1 0 0 0 0 0 0", - " 0 0 0 x x x x x", - " x a6 a5 a4 a3 a2 a1 a0", - " i i i i i i i i"; - - loadpage_hi = " 0 1 0 0 1 0 0 0", - " 0 0 0 x x x x x", - " x a6 a5 a4 a3 a2 a1 a0", - " i i i i i i i i"; - - writepage = " 0 1 0 0 1 1 0 0", - "a15 a14 a13 a12 a11 a10 a9 a8", - " a7 x x x x x x x", - " x x x x x x x x"; - - mode = 0x41; - delay = 6; - blocksize = 256; - readsize = 256; - ; - - memory "lfuse" - size = 1; - write = "1 0 1 0 1 1 0 0 1 0 1 0 0 0 0 0", - "x x x x x x x x i i i i i i i i"; - - read = "0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0", - "x x x x x x x x o o o o o o o o"; - min_write_delay = 9000; - max_write_delay = 9000; - ; - - memory "hfuse" - size = 1; - write = "1 0 1 0 1 1 0 0 1 0 1 0 1 0 0 0", - "x x x x x x x x i i i i i i i i"; - - read = "0 1 0 1 1 0 0 0 0 0 0 0 1 0 0 0", - "x x x x x x x x o o o o o o o o"; - min_write_delay = 9000; - max_write_delay = 9000; - ; - - memory "efuse" - size = 1; - write = "1 0 1 0 1 1 0 0 1 0 1 0 0 1 0 0", - "x x x x x x x x x x x x i i i i"; - - read = "0 1 0 1 0 0 0 0 0 0 0 0 1 0 0 0", - "x x x x x x x x o o o o o o o o"; - min_write_delay = 9000; - max_write_delay = 9000; - ; - - memory "lock" - size = 1; - read = "0 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0", - "x x x x x x x x x x o o o o o o"; - - write = "1 0 1 0 1 1 0 0 1 1 1 x x x x x", - "x x x x x x x x 1 1 i i i i i i"; - min_write_delay = 9000; - max_write_delay = 9000; - ; - - memory "calibration" - size = 1; - read = "0 0 1 1 1 0 0 0 0 0 0 x x x x x", - "0 0 0 0 0 0 0 0 o o o o o o o o"; - ; - - memory "signature" - size = 3; - read = "0 0 1 1 0 0 0 0 x x x x x x x x", - "x x x x x x a1 a0 o o o o o o o o"; - ; - ; - - -#------------------------------------------------------------ -# ATmega16 -#------------------------------------------------------------ - -part - id = "m16"; - desc = "ATmega16"; - has_jtag = yes; - stk500_devcode = 0x82; - avr910_devcode = 0x74; - signature = 0x1e 0x94 0x03; - pagel = 0xd7; - bs2 = 0xa0; - chip_erase_delay = 9000; - pgm_enable = "1 0 1 0 1 1 0 0 0 1 0 1 0 0 1 1", - "x x x x x x x x x x x x x x x x"; - - chip_erase = "1 0 1 0 1 1 0 0 1 0 0 x x x x x", - "x x x x x x x x x x x x x x x x"; - - timeout = 200; - stabdelay = 100; - cmdexedelay = 25; - synchloops = 32; - bytedelay = 0; - pollindex = 3; - pollvalue = 0x53; - predelay = 1; - postdelay = 1; - pollmethod = 0; - - pp_controlstack = - 0x0E, 0x1E, 0x0F, 0x1F, 0x2E, 0x3E, 0x2F, 0x3F, - 0x4E, 0x5E, 0x4F, 0x5F, 0x6E, 0x7E, 0x6F, 0x7F, - 0x66, 0x76, 0x67, 0x77, 0x6A, 0x7A, 0x6B, 0x7B, - 0xBE, 0xFD, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00; - hventerstabdelay = 100; - progmodedelay = 100; - latchcycles = 6; - togglevtg = 0; - poweroffdelay = 0; - resetdelayms = 0; - resetdelayus = 0; - hvleavestabdelay = 15; - resetdelay = 15; - chiperasepulsewidth = 0; - chiperasepolltimeout = 10; - programfusepulsewidth = 0; - programfusepolltimeout = 5; - programlockpulsewidth = 0; - programlockpolltimeout = 5; - - idr = 0x31; - spmcr = 0x57; - allowfullpagebitstream = yes; - - ocdrev = 2; - - memory "eeprom" - paged = no; /* leave this "no" */ - page_size = 4; /* for parallel programming */ - size = 512; - min_write_delay = 9000; - max_write_delay = 9000; - readback_p1 = 0xff; - readback_p2 = 0xff; - read = " 1 0 1 0 0 0 0 0", - " 0 0 x x x x a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " o o o o o o o o"; - - write = " 1 1 0 0 0 0 0 0", - " 0 0 x x x x a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " i i i i i i i i"; - - loadpage_lo = " 1 1 0 0 0 0 0 1", - " 0 0 0 0 0 0 0 0", - " 0 0 0 0 0 0 a1 a0", - " i i i i i i i i"; - - writepage = " 1 1 0 0 0 0 1 0", - " 0 0 x x x x a9 a8", - " a7 a6 a5 a4 a3 a2 0 0", - " x x x x x x x x"; - - mode = 0x04; - delay = 10; - blocksize = 128; - readsize = 256; - ; - - memory "flash" - paged = yes; - size = 16384; - page_size = 128; - num_pages = 128; - min_write_delay = 4500; - max_write_delay = 4500; - readback_p1 = 0xff; - readback_p2 = 0xff; - read_lo = " 0 0 1 0 0 0 0 0", - " 0 0 a13 a12 a11 a10 a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " o o o o o o o o"; - - read_hi = " 0 0 1 0 1 0 0 0", - " 0 0 a13 a12 a11 a10 a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " o o o o o o o o"; - - loadpage_lo = " 0 1 0 0 0 0 0 0", - " 0 0 x x x x x x", - " x x a5 a4 a3 a2 a1 a0", - " i i i i i i i i"; - - loadpage_hi = " 0 1 0 0 1 0 0 0", - " 0 0 x x x x x x", - " x x a5 a4 a3 a2 a1 a0", - " i i i i i i i i"; - - writepage = " 0 1 0 0 1 1 0 0", - " 0 0 a13 a12 a11 a10 a9 a8", - " a7 a6 x x x x x x", - " x x x x x x x x"; - - mode = 0x21; - delay = 6; - blocksize = 128; - readsize = 256; - ; - - memory "lock" - size = 1; - read = "0 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0", - "x x x x x x x x x x o o o o o o"; - - write = "1 0 1 0 1 1 0 0 1 1 1 x x x x x", - "x x x x x x x x 1 1 i i i i i i"; - min_write_delay = 9000; - max_write_delay = 9000; - ; - - memory "lfuse" - size = 1; - read = "0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0", - "x x x x x x x x o o o o o o o o"; - - write = "1 0 1 0 1 1 0 0 1 0 1 0 0 0 0 0", - "x x x x x x x x i i i i i i i i"; - min_write_delay = 9000; - max_write_delay = 9000; - ; - - memory "hfuse" - size = 1; - read = "0 1 0 1 1 0 0 0 0 0 0 0 1 0 0 0", - "x x x x x x x x o o o o o o o o"; - - write = "1 0 1 0 1 1 0 0 1 0 1 0 1 0 0 0", - "x x x x x x x x i i i i i i i i"; - min_write_delay = 9000; - max_write_delay = 9000; - ; - memory "signature" - size = 3; - read = "0 0 1 1 0 0 0 0 x x x x x x x x", - "x x x x x x a1 a0 o o o o o o o o"; - ; - memory "calibration" - size = 4; - - read = "0 0 1 1 1 0 0 0 0 0 0 x x x x x", - "0 0 0 0 0 0 a1 a0 o o o o o o o o"; - ; - ; - - -#------------------------------------------------------------ -# ATmega164P -#------------------------------------------------------------ - -# close to ATmega16 - -part parent "m16" - id = "m164p"; - desc = "ATmega164P"; - signature = 0x1e 0x94 0x0a; - - progmodedelay = 0; - latchcycles = 5; - togglevtg = 1; - poweroffdelay = 15; - resetdelayms = 1; - allowfullpagebitstream = no; - chip_erase_delay = 55000; - - ocdrev = 3; - ; - - -#------------------------------------------------------------ -# ATmega324P -#------------------------------------------------------------ - -# similar to ATmega164P - -part - id = "m324p"; - desc = "ATmega324P"; - has_jtag = yes; - stk500_devcode = 0x82; # no STK500v1 support, use the ATmega16 one - avr910_devcode = 0x74; - signature = 0x1e 0x95 0x08; - pagel = 0xd7; - bs2 = 0xa0; - chip_erase_delay = 55000; - pgm_enable = "1 0 1 0 1 1 0 0 0 1 0 1 0 0 1 1", - "x x x x x x x x x x x x x x x x"; - - chip_erase = "1 0 1 0 1 1 0 0 1 0 0 x x x x x", - "x x x x x x x x x x x x x x x x"; - - timeout = 200; - stabdelay = 100; - cmdexedelay = 25; - synchloops = 32; - bytedelay = 0; - pollindex = 3; - pollvalue = 0x53; - predelay = 1; - postdelay = 1; - pollmethod = 0; - - pp_controlstack = - 0x0E, 0x1E, 0x0F, 0x1F, 0x2E, 0x3E, 0x2F, 0x3F, - 0x4E, 0x5E, 0x4F, 0x5F, 0x6E, 0x7E, 0x6F, 0x7F, - 0x66, 0x76, 0x67, 0x77, 0x6A, 0x7A, 0x6B, 0x7B, - 0xBE, 0xFD, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00; - hventerstabdelay = 100; - progmodedelay = 0; - latchcycles = 5; - togglevtg = 1; - poweroffdelay = 15; - resetdelayms = 1; - resetdelayus = 0; - hvleavestabdelay = 15; - chiperasepulsewidth = 0; - chiperasepolltimeout = 10; - programfusepulsewidth = 0; - programfusepolltimeout = 5; - programlockpulsewidth = 0; - programlockpolltimeout = 5; - - idr = 0x31; - spmcr = 0x57; - allowfullpagebitstream = no; - - ocdrev = 3; - - memory "eeprom" - paged = no; /* leave this "no" */ - page_size = 4; /* for parallel programming */ - size = 1024; - min_write_delay = 9000; - max_write_delay = 9000; - readback_p1 = 0xff; - readback_p2 = 0xff; - read = " 1 0 1 0 0 0 0 0", - " 0 0 x x x a10 a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " o o o o o o o o"; - - write = " 1 1 0 0 0 0 0 0", - " 0 0 x x x a10 a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " i i i i i i i i"; - - loadpage_lo = " 1 1 0 0 0 0 0 1", - " 0 0 0 0 0 0 0 0", - " 0 0 0 0 0 0 a1 a0", - " i i i i i i i i"; - - writepage = " 1 1 0 0 0 0 1 0", - " 0 0 x x x a10 a9 a8", - " a7 a6 a5 a4 a3 a2 0 0", - " x x x x x x x x"; - - mode = 0x41; - delay = 10; - blocksize = 128; - readsize = 256; - ; - - memory "flash" - paged = yes; - size = 32768; - page_size = 128; - num_pages = 256; - min_write_delay = 4500; - max_write_delay = 4500; - readback_p1 = 0xff; - readback_p2 = 0xff; - read_lo = " 0 0 1 0 0 0 0 0", - " 0 a14 a13 a12 a11 a10 a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " o o o o o o o o"; - - read_hi = " 0 0 1 0 1 0 0 0", - " 0 a14 a13 a12 a11 a10 a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " o o o o o o o o"; - - loadpage_lo = " 0 1 0 0 0 0 0 0", - " 0 0 x x x x x x", - " x x a5 a4 a3 a2 a1 a0", - " i i i i i i i i"; - - loadpage_hi = " 0 1 0 0 1 0 0 0", - " 0 0 x x x x x x", - " x x a5 a4 a3 a2 a1 a0", - " i i i i i i i i"; - - writepage = " 0 1 0 0 1 1 0 0", - " 0 a14 a13 a12 a11 a10 a9 a8", - " a7 a6 x x x x x x", - " x x x x x x x x"; - - mode = 0x21; - delay = 6; - blocksize = 256; - readsize = 256; - ; - - memory "lock" - size = 1; - read = "0 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0", - "x x x x x x x x x x o o o o o o"; - - write = "1 0 1 0 1 1 0 0 1 1 1 x x x x x", - "x x x x x x x x 1 1 i i i i i i"; - min_write_delay = 9000; - max_write_delay = 9000; - ; - - memory "lfuse" - size = 1; - read = "0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0", - "x x x x x x x x o o o o o o o o"; - - write = "1 0 1 0 1 1 0 0 1 0 1 0 0 0 0 0", - "x x x x x x x x i i i i i i i i"; - min_write_delay = 9000; - max_write_delay = 9000; - ; - - memory "hfuse" - size = 1; - read = "0 1 0 1 1 0 0 0 0 0 0 0 1 0 0 0", - "x x x x x x x x o o o o o o o o"; - - write = "1 0 1 0 1 1 0 0 1 0 1 0 1 0 0 0", - "x x x x x x x x i i i i i i i i"; - min_write_delay = 9000; - max_write_delay = 9000; - ; - - memory "efuse" - size = 1; - - read = "0 1 0 1 0 0 0 0 0 0 0 0 1 0 0 0", - "x x x x x x x x o o o o o o o o"; - - write = "1 0 1 0 1 1 0 0 1 0 1 0 0 1 0 0", - "x x x x x x x x 1 1 1 1 1 i i i"; - min_write_delay = 9000; - max_write_delay = 9000; - ; - - memory "signature" - size = 3; - read = "0 0 1 1 0 0 0 0 x x x x x x x x", - "x x x x x x a1 a0 o o o o o o o o"; - ; - - memory "calibration" - size = 1; - - read = "0 0 1 1 1 0 0 0 0 0 0 x x x x x", - "0 0 0 0 0 0 0 0 o o o o o o o o"; - ; - ; - - -#------------------------------------------------------------ -# ATmega324PA -#------------------------------------------------------------ - -# similar to ATmega324P - -part parent "m324p" - id = "m324pa"; - desc = "ATmega324PA"; - signature = 0x1e 0x95 0x11; - - ocdrev = 3; - ; - - -#------------------------------------------------------------ -# ATmega644 -#------------------------------------------------------------ - -# similar to ATmega164 - -part - id = "m644"; - desc = "ATmega644"; - has_jtag = yes; - stk500_devcode = 0x82; # no STK500v1 support, use the ATmega16 one - avr910_devcode = 0x74; - signature = 0x1e 0x96 0x09; - pagel = 0xd7; - bs2 = 0xa0; - chip_erase_delay = 55000; - pgm_enable = "1 0 1 0 1 1 0 0 0 1 0 1 0 0 1 1", - "x x x x x x x x x x x x x x x x"; - - chip_erase = "1 0 1 0 1 1 0 0 1 0 0 x x x x x", - "x x x x x x x x x x x x x x x x"; - - timeout = 200; - stabdelay = 100; - cmdexedelay = 25; - synchloops = 32; - bytedelay = 0; - pollindex = 3; - pollvalue = 0x53; - predelay = 1; - postdelay = 1; - pollmethod = 0; - - pp_controlstack = - 0x0E, 0x1E, 0x0F, 0x1F, 0x2E, 0x3E, 0x2F, 0x3F, - 0x4E, 0x5E, 0x4F, 0x5F, 0x6E, 0x7E, 0x6F, 0x7F, - 0x66, 0x76, 0x67, 0x77, 0x6A, 0x7A, 0x6B, 0x7B, - 0xBE, 0xFD, 0x00, 0x01, 0x00, 0x00, 0x00, 0x02; - hventerstabdelay = 100; - progmodedelay = 0; - latchcycles = 6; - togglevtg = 0; - poweroffdelay = 0; - resetdelayms = 0; - resetdelayus = 0; - hvleavestabdelay = 15; - chiperasepulsewidth = 0; - chiperasepolltimeout = 10; - programfusepulsewidth = 0; - programfusepolltimeout = 5; - programlockpulsewidth = 0; - programlockpolltimeout = 5; - - idr = 0x31; - spmcr = 0x57; - allowfullpagebitstream = no; - - ocdrev = 3; - - memory "eeprom" - paged = no; /* leave this "no" */ - page_size = 8; /* for parallel programming */ - size = 2048; - min_write_delay = 9000; - max_write_delay = 9000; - readback_p1 = 0xff; - readback_p2 = 0xff; - read = " 1 0 1 0 0 0 0 0", - " 0 0 x x a11 a10 a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " o o o o o o o o"; - - write = " 1 1 0 0 0 0 0 0", - " 0 0 x x a11 a10 a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " i i i i i i i i"; - - loadpage_lo = " 1 1 0 0 0 0 0 1", - " 0 0 0 0 0 0 0 0", - " 0 0 0 0 0 a2 a1 a0", - " i i i i i i i i"; - - writepage = " 1 1 0 0 0 0 1 0", - " 0 0 x x a11 a10 a9 a8", - " a7 a6 a5 a4 a3 0 0 0", - " x x x x x x x x"; - - mode = 0x41; - delay = 10; - blocksize = 128; - readsize = 256; - ; - - memory "flash" - paged = yes; - size = 65536; - page_size = 256; - num_pages = 256; - min_write_delay = 4500; - max_write_delay = 4500; - readback_p1 = 0xff; - readback_p2 = 0xff; - read_lo = " 0 0 1 0 0 0 0 0", - "a15 a14 a13 a12 a11 a10 a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " o o o o o o o o"; - - read_hi = " 0 0 1 0 1 0 0 0", - "a15 a14 a13 a12 a11 a10 a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " o o o o o o o o"; - - loadpage_lo = " 0 1 0 0 0 0 0 0", - " 0 0 x x x x x x", - " x a6 a5 a4 a3 a2 a1 a0", - " i i i i i i i i"; - - loadpage_hi = " 0 1 0 0 1 0 0 0", - " 0 0 x x x x x x", - " x a6 a5 a4 a3 a2 a1 a0", - " i i i i i i i i"; - - writepage = " 0 1 0 0 1 1 0 0", - "a15 a14 a13 a12 a11 a10 a9 a8", - " a7 x x x x x x x", - " x x x x x x x x"; - - mode = 0x21; - delay = 6; - blocksize = 256; - readsize = 256; - ; - - memory "lock" - size = 1; - read = "0 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0", - "x x x x x x x x x x o o o o o o"; - - write = "1 0 1 0 1 1 0 0 1 1 1 x x x x x", - "x x x x x x x x 1 1 i i i i i i"; - min_write_delay = 9000; - max_write_delay = 9000; - ; - - memory "lfuse" - size = 1; - read = "0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0", - "x x x x x x x x o o o o o o o o"; - - write = "1 0 1 0 1 1 0 0 1 0 1 0 0 0 0 0", - "x x x x x x x x i i i i i i i i"; - min_write_delay = 9000; - max_write_delay = 9000; - ; - - memory "hfuse" - size = 1; - read = "0 1 0 1 1 0 0 0 0 0 0 0 1 0 0 0", - "x x x x x x x x o o o o o o o o"; - - write = "1 0 1 0 1 1 0 0 1 0 1 0 1 0 0 0", - "x x x x x x x x i i i i i i i i"; - min_write_delay = 9000; - max_write_delay = 9000; - ; - - memory "efuse" - size = 1; - - read = "0 1 0 1 0 0 0 0 0 0 0 0 1 0 0 0", - "x x x x x x x x o o o o o o o o"; - - write = "1 0 1 0 1 1 0 0 1 0 1 0 0 1 0 0", - "x x x x x x x x 1 1 1 1 1 i i i"; - min_write_delay = 9000; - max_write_delay = 9000; - ; - - memory "signature" - size = 3; - read = "0 0 1 1 0 0 0 0 x x x x x x x x", - "x x x x x x a1 a0 o o o o o o o o"; - ; - - memory "calibration" - size = 1; - - read = "0 0 1 1 1 0 0 0 0 0 0 x x x x x", - "0 0 0 0 0 0 0 0 o o o o o o o o"; - ; - ; - -#------------------------------------------------------------ -# ATmega644P -#------------------------------------------------------------ - -# similar to ATmega164p - -part parent "m644" - id = "m644p"; - desc = "ATmega644P"; - signature = 0x1e 0x96 0x0a; - - ocdrev = 3; - ; - - - -#------------------------------------------------------------ -# ATmega1284 -#------------------------------------------------------------ - -# similar to ATmega164 - -part - id = "m1284"; - desc = "ATmega1284"; - has_jtag = yes; - stk500_devcode = 0x82; # no STK500v1 support, use the ATmega16 one - avr910_devcode = 0x74; - signature = 0x1e 0x97 0x06; - pagel = 0xd7; - bs2 = 0xa0; - chip_erase_delay = 55000; - pgm_enable = "1 0 1 0 1 1 0 0 0 1 0 1 0 0 1 1", - "x x x x x x x x x x x x x x x x"; - - chip_erase = "1 0 1 0 1 1 0 0 1 0 0 x x x x x", - "x x x x x x x x x x x x x x x x"; - - timeout = 200; - stabdelay = 100; - cmdexedelay = 25; - synchloops = 32; - bytedelay = 0; - pollindex = 3; - pollvalue = 0x53; - predelay = 1; - postdelay = 1; - pollmethod = 1; - - pp_controlstack = - 0x0E, 0x1E, 0x0F, 0x1F, 0x2E, 0x3E, 0x2F, 0x3F, - 0x4E, 0x5E, 0x4F, 0x5F, 0x6E, 0x7E, 0x6F, 0x7F, - 0x66, 0x76, 0x67, 0x77, 0x6A, 0x7A, 0x6B, 0x7B, - 0xBE, 0xFD, 0x00, 0x01, 0x00, 0x00, 0x00, 0x02; - hventerstabdelay = 100; - progmodedelay = 0; - latchcycles = 6; - togglevtg = 1; - poweroffdelay = 15; - resetdelayms = 1; - resetdelayus = 0; - hvleavestabdelay = 15; - chiperasepulsewidth = 0; - chiperasepolltimeout = 10; - programfusepulsewidth = 0; - programfusepolltimeout = 5; - programlockpulsewidth = 0; - programlockpolltimeout = 5; - - idr = 0x31; - spmcr = 0x57; - allowfullpagebitstream = no; - - ocdrev = 3; - - memory "eeprom" - paged = no; /* leave this "no" */ - page_size = 8; /* for parallel programming */ - size = 4096; - min_write_delay = 9000; - max_write_delay = 9000; - readback_p1 = 0xff; - readback_p2 = 0xff; - read = " 1 0 1 0 0 0 0 0", - " 0 0 x x a11 a10 a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " o o o o o o o o"; - - write = " 1 1 0 0 0 0 0 0", - " 0 0 x x a11 a10 a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " i i i i i i i i"; - - loadpage_lo = " 1 1 0 0 0 0 0 1", - " 0 0 0 0 0 0 0 0", - " 0 0 0 0 0 a2 a1 a0", - " i i i i i i i i"; - - writepage = " 1 1 0 0 0 0 1 0", - " 0 0 x x a11 a10 a9 a8", - " a7 a6 a5 a4 a3 0 0 0", - " x x x x x x x x"; - - mode = 0x41; - delay = 10; - blocksize = 128; - readsize = 256; - ; - - memory "flash" - paged = yes; - size = 131072; - page_size = 256; - num_pages = 512; - min_write_delay = 4500; - max_write_delay = 4500; - readback_p1 = 0xff; - readback_p2 = 0xff; - read_lo = " 0 0 1 0 0 0 0 0", - "a15 a14 a13 a12 a11 a10 a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " o o o o o o o o"; - - read_hi = " 0 0 1 0 1 0 0 0", - "a15 a14 a13 a12 a11 a10 a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " o o o o o o o o"; - - loadpage_lo = " 0 1 0 0 0 0 0 0", - " 0 0 x x x x x x", - " x a6 a5 a4 a3 a2 a1 a0", - " i i i i i i i i"; - - loadpage_hi = " 0 1 0 0 1 0 0 0", - " 0 0 x x x x x x", - " x a6 a5 a4 a3 a2 a1 a0", - " i i i i i i i i"; - - writepage = " 0 1 0 0 1 1 0 0", - "a15 a14 a13 a12 a11 a10 a9 a8", - " a7 x x x x x x x", - " x x x x x x x x"; - - mode = 0x41; - delay = 10; - blocksize = 256; - readsize = 256; - ; - - memory "lock" - size = 1; - read = "0 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0", - "x x x x x x x x x x o o o o o o"; - - write = "1 0 1 0 1 1 0 0 1 1 1 x x x x x", - "x x x x x x x x 1 1 i i i i i i"; - min_write_delay = 9000; - max_write_delay = 9000; - ; - - memory "lfuse" - size = 1; - read = "0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0", - "x x x x x x x x o o o o o o o o"; - - write = "1 0 1 0 1 1 0 0 1 0 1 0 0 0 0 0", - "x x x x x x x x i i i i i i i i"; - min_write_delay = 9000; - max_write_delay = 9000; - ; - - memory "hfuse" - size = 1; - read = "0 1 0 1 1 0 0 0 0 0 0 0 1 0 0 0", - "x x x x x x x x o o o o o o o o"; - - write = "1 0 1 0 1 1 0 0 1 0 1 0 1 0 0 0", - "x x x x x x x x i i i i i i i i"; - min_write_delay = 9000; - max_write_delay = 9000; - ; - - memory "efuse" - size = 1; - - read = "0 1 0 1 0 0 0 0 0 0 0 0 1 0 0 0", - "x x x x x x x x o o o o o o o o"; - - write = "1 0 1 0 1 1 0 0 1 0 1 0 0 1 0 0", - "x x x x x x x x 1 1 1 1 1 i i i"; - min_write_delay = 9000; - max_write_delay = 9000; - ; - - memory "signature" - size = 3; - read = "0 0 1 1 0 0 0 0 x x x x x x x x", - "x x x x x x a1 a0 o o o o o o o o"; - ; - - memory "calibration" - size = 1; - - read = "0 0 1 1 1 0 0 0 0 0 0 x x x x x", - "0 0 0 0 0 0 0 0 o o o o o o o o"; - ; - ; - - - -#------------------------------------------------------------ -# ATmega1284P -#------------------------------------------------------------ - -# similar to ATmega164p - -part - id = "m1284p"; - desc = "ATmega1284P"; - has_jtag = yes; - stk500_devcode = 0x82; # no STK500v1 support, use the ATmega16 one - avr910_devcode = 0x74; - signature = 0x1e 0x97 0x05; - pagel = 0xd7; - bs2 = 0xa0; - chip_erase_delay = 55000; - pgm_enable = "1 0 1 0 1 1 0 0 0 1 0 1 0 0 1 1", - "x x x x x x x x x x x x x x x x"; - - chip_erase = "1 0 1 0 1 1 0 0 1 0 0 x x x x x", - "x x x x x x x x x x x x x x x x"; - - timeout = 200; - stabdelay = 100; - cmdexedelay = 25; - synchloops = 32; - bytedelay = 0; - pollindex = 3; - pollvalue = 0x53; - predelay = 1; - postdelay = 1; - pollmethod = 1; - - pp_controlstack = - 0x0E, 0x1E, 0x0F, 0x1F, 0x2E, 0x3E, 0x2F, 0x3F, - 0x4E, 0x5E, 0x4F, 0x5F, 0x6E, 0x7E, 0x6F, 0x7F, - 0x66, 0x76, 0x67, 0x77, 0x6A, 0x7A, 0x6B, 0x7B, - 0xBE, 0xFD, 0x00, 0x01, 0x00, 0x00, 0x00, 0x02; - hventerstabdelay = 100; - progmodedelay = 0; - latchcycles = 6; - togglevtg = 1; - poweroffdelay = 15; - resetdelayms = 1; - resetdelayus = 0; - hvleavestabdelay = 15; - chiperasepulsewidth = 0; - chiperasepolltimeout = 10; - programfusepulsewidth = 0; - programfusepolltimeout = 5; - programlockpulsewidth = 0; - programlockpolltimeout = 5; - - idr = 0x31; - spmcr = 0x57; - allowfullpagebitstream = no; - - ocdrev = 3; - - memory "eeprom" - paged = no; /* leave this "no" */ - page_size = 8; /* for parallel programming */ - size = 4096; - min_write_delay = 9000; - max_write_delay = 9000; - readback_p1 = 0xff; - readback_p2 = 0xff; - read = " 1 0 1 0 0 0 0 0", - " 0 0 x x a11 a10 a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " o o o o o o o o"; - - write = " 1 1 0 0 0 0 0 0", - " 0 0 x x a11 a10 a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " i i i i i i i i"; - - loadpage_lo = " 1 1 0 0 0 0 0 1", - " 0 0 0 0 0 0 0 0", - " 0 0 0 0 0 a2 a1 a0", - " i i i i i i i i"; - - writepage = " 1 1 0 0 0 0 1 0", - " 0 0 x x a11 a10 a9 a8", - " a7 a6 a5 a4 a3 0 0 0", - " x x x x x x x x"; - - mode = 0x41; - delay = 10; - blocksize = 128; - readsize = 256; - ; - - memory "flash" - paged = yes; - size = 131072; - page_size = 256; - num_pages = 512; - min_write_delay = 4500; - max_write_delay = 4500; - readback_p1 = 0xff; - readback_p2 = 0xff; - read_lo = " 0 0 1 0 0 0 0 0", - "a15 a14 a13 a12 a11 a10 a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " o o o o o o o o"; - - read_hi = " 0 0 1 0 1 0 0 0", - "a15 a14 a13 a12 a11 a10 a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " o o o o o o o o"; - - loadpage_lo = " 0 1 0 0 0 0 0 0", - " 0 0 x x x x x x", - " x a6 a5 a4 a3 a2 a1 a0", - " i i i i i i i i"; - - loadpage_hi = " 0 1 0 0 1 0 0 0", - " 0 0 x x x x x x", - " x a6 a5 a4 a3 a2 a1 a0", - " i i i i i i i i"; - - writepage = " 0 1 0 0 1 1 0 0", - "a15 a14 a13 a12 a11 a10 a9 a8", - " a7 x x x x x x x", - " x x x x x x x x"; - - mode = 0x41; - delay = 10; - blocksize = 256; - readsize = 256; - ; - - memory "lock" - size = 1; - read = "0 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0", - "x x x x x x x x x x o o o o o o"; - - write = "1 0 1 0 1 1 0 0 1 1 1 x x x x x", - "x x x x x x x x 1 1 i i i i i i"; - min_write_delay = 9000; - max_write_delay = 9000; - ; - - memory "lfuse" - size = 1; - read = "0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0", - "x x x x x x x x o o o o o o o o"; - - write = "1 0 1 0 1 1 0 0 1 0 1 0 0 0 0 0", - "x x x x x x x x i i i i i i i i"; - min_write_delay = 9000; - max_write_delay = 9000; - ; - - memory "hfuse" - size = 1; - read = "0 1 0 1 1 0 0 0 0 0 0 0 1 0 0 0", - "x x x x x x x x o o o o o o o o"; - - write = "1 0 1 0 1 1 0 0 1 0 1 0 1 0 0 0", - "x x x x x x x x i i i i i i i i"; - min_write_delay = 9000; - max_write_delay = 9000; - ; - - memory "efuse" - size = 1; - - read = "0 1 0 1 0 0 0 0 0 0 0 0 1 0 0 0", - "x x x x x x x x o o o o o o o o"; - - write = "1 0 1 0 1 1 0 0 1 0 1 0 0 1 0 0", - "x x x x x x x x 1 1 1 1 1 i i i"; - min_write_delay = 9000; - max_write_delay = 9000; - ; - - memory "signature" - size = 3; - read = "0 0 1 1 0 0 0 0 x x x x x x x x", - "x x x x x x a1 a0 o o o o o o o o"; - ; - - memory "calibration" - size = 1; - - read = "0 0 1 1 1 0 0 0 0 0 0 x x x x x", - "0 0 0 0 0 0 0 0 o o o o o o o o"; - ; - ; - - - -#------------------------------------------------------------ -# ATmega162 -#------------------------------------------------------------ - -part - id = "m162"; - desc = "ATmega162"; - has_jtag = yes; - stk500_devcode = 0x83; - avr910_devcode = 0x63; - signature = 0x1e 0x94 0x04; - chip_erase_delay = 9000; - pagel = 0xd7; - bs2 = 0xa0; - - idr = 0x04; - spmcr = 0x57; - allowfullpagebitstream = yes; - - pgm_enable = "1 0 1 0 1 1 0 0 0 1 0 1 0 0 1 1", - "x x x x x x x x x x x x x x x x"; - - chip_erase = "1 0 1 0 1 1 0 0 1 0 0 x x x x x", - "x x x x x x x x x x x x x x x x"; - - ocdrev = 2; - - memory "flash" - paged = yes; - size = 16384; - page_size = 128; - num_pages = 128; - min_write_delay = 4500; - max_write_delay = 4500; - readback_p1 = 0xff; - readback_p2 = 0xff; - - read_lo = " 0 0 1 0 0 0 0 0", - " 0 0 a13 a12 a11 a10 a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " o o o o o o o o"; - - read_hi = " 0 0 1 0 1 0 0 0", - " 0 0 a13 a12 a11 a10 a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " o o o o o o o o"; - - loadpage_lo = " 0 1 0 0 0 0 0 0", - " 0 0 x x x x x x", - " x x a5 a4 a3 a2 a1 a0", - " i i i i i i i i"; - - loadpage_hi = " 0 1 0 0 1 0 0 0", - " 0 0 x x x x x x", - " x x a5 a4 a3 a2 a1 a0", - " i i i i i i i i"; - - writepage = " 0 1 0 0 1 1 0 0", - " 0 0 a13 a12 a11 a10 a9 a8", - " a7 a6 x x x x x x", - " x x x x x x x x"; - mode = 0x41; - delay = 10; - blocksize = 128; - readsize = 256; - - ; - - timeout = 200; - stabdelay = 100; - cmdexedelay = 25; - synchloops = 32; - bytedelay = 0; - pollindex = 3; - pollvalue = 0x53; - predelay = 1; - postdelay = 1; - pollmethod = 0; - - pp_controlstack = - 0x0E, 0x1E, 0x0F, 0x1F, 0x2E, 0x3E, 0x2F, 0x3F, - 0x4E, 0x5E, 0x4F, 0x5F, 0x6E, 0x7E, 0x6F, 0x7F, - 0x66, 0x76, 0x67, 0x77, 0x6A, 0x7A, 0x6B, 0x7B, - 0xBE, 0xFD, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00; - hventerstabdelay = 100; - progmodedelay = 0; - latchcycles = 6; - togglevtg = 0; - poweroffdelay = 0; - resetdelayms = 0; - resetdelayus = 0; - hvleavestabdelay = 15; - chiperasepulsewidth = 0; - chiperasepolltimeout = 10; - programfusepulsewidth = 0; - programfusepolltimeout = 5; - programlockpulsewidth = 0; - programlockpolltimeout = 5; - - memory "eeprom" - paged = no; /* leave this "no" */ - page_size = 4; /* for parallel programming */ - size = 512; - min_write_delay = 9000; - max_write_delay = 9000; - readback_p1 = 0xff; - readback_p2 = 0xff; - - read = " 1 0 1 0 0 0 0 0", - " 0 0 x x x x a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " o o o o o o o o"; - - write = " 1 1 0 0 0 0 0 0", - " 0 0 x x x x a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " i i i i i i i i"; - - loadpage_lo = " 1 1 0 0 0 0 0 1", - " 0 0 0 0 0 0 0 0", - " 0 0 0 0 0 0 a1 a0", - " i i i i i i i i"; - - writepage = " 1 1 0 0 0 0 1 0", - " 0 0 x x x x a9 a8", - " a7 a6 a5 a4 a3 a2 0 0", - " x x x x x x x x"; - - mode = 0x41; - delay = 20; - blocksize = 4; - readsize = 256; - ; - - memory "lfuse" - size = 1; - min_write_delay = 16000; - max_write_delay = 16000; - read = "0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0", - "x x x x x x x x o o o o o o o o"; - - write = "1 0 1 0 1 1 0 0 1 0 1 0 0 0 0 0", - "x x x x x x x x i i i i i i i i"; - ; - - memory "hfuse" - size = 1; - min_write_delay = 16000; - max_write_delay = 16000; - - read = "0 1 0 1 1 0 0 0 0 0 0 0 1 0 0 0", - "x x x x x x x x o o o o o o o o"; - - write = "1 0 1 0 1 1 0 0 1 0 1 0 1 0 0 0", - "x x x x x x x x i i i i i i i i"; - ; - - memory "efuse" - size = 1; - min_write_delay = 16000; - max_write_delay = 16000; - - read = "0 1 0 1 0 0 0 0 0 0 0 0 1 0 0 0", - "x x x x x x x x o o o o o o o o"; - - write = "1 0 1 0 1 1 0 0 1 0 1 0 0 1 0 0", - "x x x x x x x x 1 1 1 1 1 i i i"; - ; - - memory "lock" - size = 1; - min_write_delay = 16000; - max_write_delay = 16000; - - read = "0 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0", - "x x x x x x x x x x o o o o o o"; - - write = "1 0 1 0 1 1 0 0 1 1 1 x x x x x", - "x x x x x x x x 1 1 i i i i i i"; - ; - - memory "signature" - size = 3; - - read = "0 0 1 1 0 0 0 0 0 0 x x x x x x", - "x x x x x x a1 a0 o o o o o o o o"; - ; - - memory "calibration" - size = 1; - - read = "0 0 1 1 1 0 0 0 0 0 x x x x x x", - "0 0 0 0 0 0 0 0 o o o o o o o o"; - ; -; - - - -#------------------------------------------------------------ -# ATmega163 -#------------------------------------------------------------ - -part - id = "m163"; - desc = "ATmega163"; - stk500_devcode = 0x81; - avr910_devcode = 0x64; - signature = 0x1e 0x94 0x02; - chip_erase_delay = 32000; - pagel = 0xd7; - bs2 = 0xa0; - pgm_enable = "1 0 1 0 1 1 0 0 0 1 0 1 0 0 1 1", - "x x x x x x x x x x x x x x x x"; - - chip_erase = "1 0 1 0 1 1 0 0 1 0 0 0 0 0 0 0", - "x x x x x x x x x x x x x x x x"; - - timeout = 200; - stabdelay = 100; - cmdexedelay = 25; - synchloops = 32; - bytedelay = 0; - pollindex = 3; - pollvalue = 0x53; - predelay = 1; - postdelay = 1; - pollmethod = 0; - - pp_controlstack = - 0x0E, 0x1E, 0x0F, 0x1F, 0x2E, 0x3E, 0x2F, 0x3F, - 0x4E, 0x5E, 0x4F, 0x5F, 0x6E, 0x7E, 0x6F, 0x7F, - 0x66, 0x76, 0x67, 0x77, 0x6A, 0x7A, 0x6B, 0x7B, - 0xBE, 0xFD, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00; - hventerstabdelay = 100; - progmodedelay = 0; - latchcycles = 0; - togglevtg = 0; - poweroffdelay = 0; - resetdelayms = 0; - resetdelayus = 0; - hvleavestabdelay = 15; - chiperasepulsewidth = 0; - chiperasepolltimeout = 30; - programfusepulsewidth = 0; - programfusepolltimeout = 2; - programlockpulsewidth = 0; - programlockpolltimeout = 2; - - - memory "eeprom" - size = 512; - min_write_delay = 4000; - max_write_delay = 4000; - readback_p1 = 0xff; - readback_p2 = 0xff; - read = " 1 0 1 0 0 0 0 0", - " x x x x x x x a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " o o o o o o o o"; - - write = " 1 1 0 0 0 0 0 0", - " x x x x x x x a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " i i i i i i i i"; - mode = 0x41; - delay = 20; - blocksize = 4; - readsize = 256; - ; - - memory "flash" - paged = yes; - size = 16384; - page_size = 128; - num_pages = 128; - min_write_delay = 16000; - max_write_delay = 16000; - readback_p1 = 0xff; - readback_p2 = 0xff; - read_lo = " 0 0 1 0 0 0 0 0", - " x x x a12 a11 a10 a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " o o o o o o o o"; - - read_hi = " 0 0 1 0 1 0 0 0", - " x x x a12 a11 a10 a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " o o o o o o o o"; - - loadpage_lo = " 0 1 0 0 0 0 0 0", - " x x x x x x x x", - " x x a5 a4 a3 a2 a1 a0", - " i i i i i i i i"; - - loadpage_hi = " 0 1 0 0 1 0 0 0", - " x x x x x x x x", - " x x a5 a4 a3 a2 a1 a0", - " i i i i i i i i"; - - writepage = " 0 1 0 0 1 1 0 0", - " x x x a12 a11 a10 a9 a8", - " a7 a6 x x x x x x", - " x x x x x x x x"; - - mode = 0x11; - delay = 20; - blocksize = 128; - readsize = 256; - ; - - memory "lfuse" - size = 1; - min_write_delay = 2000; - max_write_delay = 2000; - read = "0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0", - "x x x x x x x x o o x x o o o o"; - - write = "1 0 1 0 1 1 0 0 1 0 1 0 0 0 0 0", - "x x x x x x x x i i 1 1 i i i i"; - ; - - memory "hfuse" - size = 1; - min_write_delay = 2000; - max_write_delay = 2000; - read = "0 1 0 1 1 0 0 0 0 0 0 0 1 0 0 0", - "x x x x x x x x x x x x 1 o o o"; - - write = "1 0 1 0 1 1 0 0 1 0 1 0 1 0 0 0", - "x x x x x x x x 1 1 1 1 1 i i i"; - ; - - memory "lock" - size = 1; - min_write_delay = 2000; - max_write_delay = 2000; - read = "0 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0", - "x x x x 0 x x x x x o o o o o o"; - - write = "1 0 1 0 1 1 0 0 1 1 1 x x x x x", - "x x x x x x x x 1 1 i i i i i i"; - ; - - memory "signature" - size = 3; - read = "0 0 1 1 0 0 0 0 x x x x x x x x", - "x x x x x x a1 a0 o o o o o o o o"; - ; - - memory "calibration" - size = 1; - read = "0 0 1 1 1 0 0 0 x x x x x x x x", - "0 0 0 0 0 0 0 0 o o o o o o o o"; - ; - ; - -#------------------------------------------------------------ -# ATmega169 -#------------------------------------------------------------ - -part - id = "m169"; - desc = "ATmega169"; - has_jtag = yes; - stk500_devcode = 0x85; - avr910_devcode = 0x78; - signature = 0x1e 0x94 0x05; - chip_erase_delay = 9000; - pgm_enable = "1 0 1 0 1 1 0 0 0 1 0 1 0 0 1 1", - "x x x x x x x x x x x x x x x x"; - - chip_erase = "1 0 1 0 1 1 0 0 1 0 0 0 0 0 0 0", - "x x x x x x x x x x x x x x x x"; - timeout = 200; - stabdelay = 100; - cmdexedelay = 25; - synchloops = 32; - bytedelay = 0; - pollindex = 3; - pollvalue = 0x53; - predelay = 1; - postdelay = 1; - pollmethod = 1; - - pp_controlstack = - 0x0E, 0x1E, 0x0F, 0x1F, 0x2E, 0x3E, 0x2F, 0x3F, - 0x4E, 0x5E, 0x4F, 0x5F, 0x6E, 0x7E, 0x6F, 0x7F, - 0x66, 0x76, 0x67, 0x77, 0x6A, 0x7A, 0x6B, 0x7B, - 0xBE, 0xFD, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00; - hventerstabdelay = 100; - progmodedelay = 0; - latchcycles = 5; - togglevtg = 1; - poweroffdelay = 15; - resetdelayms = 1; - resetdelayus = 0; - hvleavestabdelay = 15; - chiperasepulsewidth = 0; - chiperasepolltimeout = 10; - programfusepulsewidth = 0; - programfusepolltimeout = 5; - programlockpulsewidth = 0; - programlockpolltimeout = 5; - - idr = 0x31; - spmcr = 0x57; - - ocdrev = 2; - - memory "eeprom" - paged = no; /* leave this "no" */ - page_size = 4; /* for parallel programming */ - size = 512; - min_write_delay = 9000; - max_write_delay = 9000; - readback_p1 = 0xff; - readback_p2 = 0xff; - read = " 1 0 1 0 0 0 0 0", - " x x x x x x x a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " o o o o o o o o"; - - write = " 1 1 0 0 0 0 0 0", - " x x x x x x x a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " i i i i i i i i"; - - loadpage_lo = " 1 1 0 0 0 0 0 1", - " 0 0 0 0 0 0 0 0", - " 0 0 0 0 0 0 a1 a0", - " i i i i i i i i"; - - writepage = " 1 1 0 0 0 0 1 0", - " 0 0 x x x x x a8", - " a7 a6 a5 a4 a3 a2 0 0", - " x x x x x x x x"; - - mode = 0x41; - delay = 20; - blocksize = 4; - readsize = 256; - ; - - memory "flash" - paged = yes; - size = 16384; - page_size = 128; - num_pages = 128; - min_write_delay = 4500; - max_write_delay = 4500; - readback_p1 = 0xff; - readback_p2 = 0xff; - read_lo = " 0 0 1 0 0 0 0 0", - " x x x a12 a11 a10 a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " o o o o o o o o"; - - read_hi = " 0 0 1 0 1 0 0 0", - " x x x a12 a11 a10 a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " o o o o o o o o"; - - loadpage_lo = " 0 1 0 0 0 0 0 0", - " x x x x x x x x", - " x x a5 a4 a3 a2 a1 a0", - " i i i i i i i i"; - - loadpage_hi = " 0 1 0 0 1 0 0 0", - " x x x x x x x x", - " x x a5 a4 a3 a2 a1 a0", - " i i i i i i i i"; - - writepage = " 0 1 0 0 1 1 0 0", - " x x x a12 a11 a10 a9 a8", - " a7 a6 x x x x x x", - " x x x x x x x x"; - - mode = 0x41; - delay = 6; - blocksize = 128; - readsize = 256; - ; - - memory "lfuse" - size = 1; - min_write_delay = 2000; - max_write_delay = 2000; - read = "0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0", - "x x x x x x x x o o o o o o o o"; - - write = "1 0 1 0 1 1 0 0 1 0 1 0 0 0 0 0", - "x x x x x x x x i i i i i i i i"; - ; - - memory "hfuse" - size = 1; - min_write_delay = 2000; - max_write_delay = 2000; - read = "0 1 0 1 1 0 0 0 0 0 0 0 1 0 0 0", - "x x x x x x x x o o o o o o o o"; - - write = "1 0 1 0 1 1 0 0 1 0 1 0 1 0 0 0", - "x x x x x x x x i i i i i i i i"; - ; - - memory "efuse" - size = 1; - write = "1 0 1 0 1 1 0 0 1 0 1 0 0 1 0 0", - "x x x x x x x x x x x x i i i i"; - - read = "0 1 0 1 0 0 0 0 0 0 0 0 1 0 0 0", - "x x x x x x x x o o o o o o o o"; - ; - - memory "lock" - size = 1; - min_write_delay = 2000; - max_write_delay = 2000; - read = "0 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0", - "x x x x x x x x x x o o o o o o"; - - write = "1 0 1 0 1 1 0 0 1 1 1 x x x x x", - "x x x x x x x x 1 1 i i i i i i"; - ; - - memory "signature" - size = 3; - read = "0 0 1 1 0 0 0 0 0 0 0 x x x x x", - "x x x x x x a1 a0 o o o o o o o o"; - ; - - memory "calibration" - size = 1; - read = "0 0 1 1 1 0 0 0 0 0 0 x x x x x", - "0 0 0 0 0 0 0 0 o o o o o o o o"; - ; - ; - -#------------------------------------------------------------ -# ATmega329 -#------------------------------------------------------------ - -part - id = "m329"; - desc = "ATmega329"; - has_jtag = yes; -# stk500_devcode = 0x85; # no STK500 support, only STK500v2 -# avr910_devcode = 0x?; # try the ATmega169 one: - avr910_devcode = 0x75; - signature = 0x1e 0x95 0x03; - chip_erase_delay = 9000; - pgm_enable = "1 0 1 0 1 1 0 0 0 1 0 1 0 0 1 1", - "x x x x x x x x x x x x x x x x"; - - chip_erase = "1 0 1 0 1 1 0 0 1 0 0 0 0 0 0 0", - "x x x x x x x x x x x x x x x x"; - timeout = 200; - stabdelay = 100; - cmdexedelay = 25; - synchloops = 32; - bytedelay = 0; - pollindex = 3; - pollvalue = 0x53; - predelay = 1; - postdelay = 1; - pollmethod = 1; - - pp_controlstack = - 0x0E, 0x1E, 0x0F, 0x1F, 0x2E, 0x3E, 0x2F, 0x3F, - 0x4E, 0x5E, 0x4F, 0x5F, 0x6E, 0x7E, 0x6F, 0x7F, - 0x66, 0x76, 0x67, 0x77, 0x6A, 0x7A, 0x6B, 0x7B, - 0xBE, 0xFD, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00; - hventerstabdelay = 100; - progmodedelay = 0; - latchcycles = 5; - togglevtg = 1; - poweroffdelay = 15; - resetdelayms = 1; - resetdelayus = 0; - hvleavestabdelay = 15; - chiperasepulsewidth = 0; - chiperasepolltimeout = 10; - programfusepulsewidth = 0; - programfusepolltimeout = 5; - programlockpulsewidth = 0; - programlockpolltimeout = 5; - - idr = 0x31; - spmcr = 0x57; - - ocdrev = 3; - - memory "eeprom" - paged = no; /* leave this "no" */ - page_size = 4; /* for parallel programming */ - size = 1024; - min_write_delay = 9000; - max_write_delay = 9000; - readback_p1 = 0xff; - readback_p2 = 0xff; - read = " 1 0 1 0 0 0 0 0", - " x x x x x x a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " o o o o o o o o"; - - write = " 1 1 0 0 0 0 0 0", - " x x x x x x a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " i i i i i i i i"; - - loadpage_lo = " 1 1 0 0 0 0 0 1", - " 0 0 0 0 0 0 0 0", - " 0 0 0 0 0 0 a1 a0", - " i i i i i i i i"; - - writepage = " 1 1 0 0 0 0 1 0", - " 0 0 x x x x a9 a8", - " a7 a6 a5 a4 a3 a2 0 0", - " x x x x x x x x"; - - mode = 0x41; - delay = 20; - blocksize = 8; - readsize = 256; - ; - - memory "flash" - paged = yes; - size = 32768; - page_size = 128; - num_pages = 256; - min_write_delay = 4500; - max_write_delay = 4500; - readback_p1 = 0xff; - readback_p2 = 0xff; - read_lo = " 0 0 1 0 0 0 0 0", - " x a14 a13 a12 a11 a10 a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " o o o o o o o o"; - - read_hi = " 0 0 1 0 1 0 0 0", - " x a14 a13 a12 a11 a10 a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " o o o o o o o o"; - - loadpage_lo = " 0 1 0 0 0 0 0 0", - " x x x x x x x x", - " x x a5 a4 a3 a2 a1 a0", - " i i i i i i i i"; - - loadpage_hi = " 0 1 0 0 1 0 0 0", - " x x x x x x x x", - " x x a5 a4 a3 a2 a1 a0", - " i i i i i i i i"; - - writepage = " 0 1 0 0 1 1 0 0", - " x x x a12 a11 a10 a9 a8", - " a7 a6 x x x x x x", - " x x x x x x x x"; - - mode = 0x41; - delay = 6; - blocksize = 256; - readsize = 256; - ; - - memory "lfuse" - size = 1; - min_write_delay = 4500; - max_write_delay = 4500; - read = "0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0", - "x x x x x x x x o o o o o o o o"; - - write = "1 0 1 0 1 1 0 0 1 0 1 0 0 0 0 0", - "x x x x x x x x i i i i i i i i"; - ; - - memory "hfuse" - size = 1; - min_write_delay = 4500; - max_write_delay = 4500; - read = "0 1 0 1 1 0 0 0 0 0 0 0 1 0 0 0", - "x x x x x x x x o o o o o o o o"; - - write = "1 0 1 0 1 1 0 0 1 0 1 0 1 0 0 0", - "x x x x x x x x i i i i i i i i"; - ; - - memory "efuse" - size = 1; - min_write_delay = 4500; - max_write_delay = 4500; - read = "0 1 0 1 0 0 0 0 0 0 0 0 1 0 0 0", - "x x x x x x x x o o o o o o o o"; - - write = "1 0 1 0 1 1 0 0 1 0 1 0 0 1 0 0", - "x x x x x x x x x x x x x i i i"; - ; - - memory "lock" - size = 1; - min_write_delay = 4500; - max_write_delay = 4500; - read = "0 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0", - "x x x x x x x x x x o o o o o o"; - - write = "1 0 1 0 1 1 0 0 1 1 1 x x x x x", - "x x x x x x x x 1 1 i i i i i i"; - ; - - memory "signature" - size = 3; - read = "0 0 1 1 0 0 0 0 0 0 0 x x x x x", - "x x x x x x a1 a0 o o o o o o o o"; - ; - - memory "calibration" - size = 1; - read = "0 0 1 1 1 0 0 0 0 0 0 x x x x x", - "0 0 0 0 0 0 0 0 o o o o o o o o"; - ; - ; - -#------------------------------------------------------------ -# ATmega329P -#------------------------------------------------------------ -# Identical to ATmega329 except of the signature - -part parent "m329" - id = "m329p"; - desc = "ATmega329P"; - signature = 0x1e 0x95 0x0b; - - ocdrev = 3; - ; - -#------------------------------------------------------------ -# ATmega3290 -#------------------------------------------------------------ - -# identical to ATmega329 - -part parent "m329" - id = "m3290"; - desc = "ATmega3290"; - signature = 0x1e 0x95 0x04; - - ocdrev = 3; - ; - -#------------------------------------------------------------ -# ATmega3290P -#------------------------------------------------------------ - -# identical to ATmega3290 except of the signature - -part parent "m3290" - id = "m3290p"; - desc = "ATmega3290P"; - signature = 0x1e 0x95 0x0c; - - ocdrev = 3; - ; - -#------------------------------------------------------------ -# ATmega649 -#------------------------------------------------------------ - -part - id = "m649"; - desc = "ATmega649"; - has_jtag = yes; -# stk500_devcode = 0x85; # no STK500 support, only STK500v2 -# avr910_devcode = 0x?; # try the ATmega169 one: - avr910_devcode = 0x75; - signature = 0x1e 0x96 0x03; - chip_erase_delay = 9000; - pgm_enable = "1 0 1 0 1 1 0 0 0 1 0 1 0 0 1 1", - "x x x x x x x x x x x x x x x x"; - - chip_erase = "1 0 1 0 1 1 0 0 1 0 0 0 0 0 0 0", - "x x x x x x x x x x x x x x x x"; - timeout = 200; - stabdelay = 100; - cmdexedelay = 25; - synchloops = 32; - bytedelay = 0; - pollindex = 3; - pollvalue = 0x53; - predelay = 1; - postdelay = 1; - pollmethod = 1; - - pp_controlstack = - 0x0E, 0x1E, 0x0F, 0x1F, 0x2E, 0x3E, 0x2F, 0x3F, - 0x4E, 0x5E, 0x4F, 0x5F, 0x6E, 0x7E, 0x6F, 0x7F, - 0x66, 0x76, 0x67, 0x77, 0x6A, 0x7A, 0x6B, 0x7B, - 0xBE, 0xFD, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00; - hventerstabdelay = 100; - progmodedelay = 0; - latchcycles = 5; - togglevtg = 1; - poweroffdelay = 15; - resetdelayms = 1; - resetdelayus = 0; - hvleavestabdelay = 15; - chiperasepulsewidth = 0; - chiperasepolltimeout = 10; - programfusepulsewidth = 0; - programfusepolltimeout = 5; - programlockpulsewidth = 0; - programlockpolltimeout = 5; - - idr = 0x31; - spmcr = 0x57; - - ocdrev = 3; - - memory "eeprom" - paged = no; /* leave this "no" */ - page_size = 8; /* for parallel programming */ - size = 2048; - min_write_delay = 9000; - max_write_delay = 9000; - readback_p1 = 0xff; - readback_p2 = 0xff; - read = " 1 0 1 0 0 0 0 0", - " x x x x x a10 a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " o o o o o o o o"; - - write = " 1 1 0 0 0 0 0 0", - " x x x x x a10 a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " i i i i i i i i"; - - loadpage_lo = " 1 1 0 0 0 0 0 1", - " 0 0 0 0 0 0 0 0", - " 0 0 0 0 0 a2 a1 a0", - " i i i i i i i i"; - - writepage = " 1 1 0 0 0 0 1 0", - " 0 0 x x x a10 a9 a8", - " a7 a6 a5 a4 a3 0 0 0", - " x x x x x x x x"; - - mode = 0x41; - delay = 20; - blocksize = 8; - readsize = 256; - ; - - memory "flash" - paged = yes; - size = 65536; - page_size = 256; - num_pages = 256; - min_write_delay = 4500; - max_write_delay = 4500; - readback_p1 = 0xff; - readback_p2 = 0xff; - read_lo = " 0 0 1 0 0 0 0 0", - "a15 a14 a13 a12 a11 a10 a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " o o o o o o o o"; - - read_hi = " 0 0 1 0 1 0 0 0", - "a15 a14 a13 a12 a11 a10 a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " o o o o o o o o"; - - loadpage_lo = " 0 1 0 0 0 0 0 0", - " x x x x x x x x", - " x a6 a5 a4 a3 a2 a1 a0", - " i i i i i i i i"; - - loadpage_hi = " 0 1 0 0 1 0 0 0", - " x x x x x x x x", - " x a6 a5 a4 a3 a2 a1 a0", - " i i i i i i i i"; - - writepage = " 0 1 0 0 1 1 0 0", - " x x x a12 a11 a10 a9 a8", - " a7 x x x x x x x", - " x x x x x x x x"; - - mode = 0x41; - delay = 6; - blocksize = 256; - readsize = 256; - ; - - memory "lfuse" - size = 1; - min_write_delay = 4500; - max_write_delay = 4500; - read = "0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0", - "x x x x x x x x o o o o o o o o"; - - write = "1 0 1 0 1 1 0 0 1 0 1 0 0 0 0 0", - "x x x x x x x x i i i i i i i i"; - ; - - memory "hfuse" - size = 1; - min_write_delay = 4500; - max_write_delay = 4500; - read = "0 1 0 1 1 0 0 0 0 0 0 0 1 0 0 0", - "x x x x x x x x o o o o o o o o"; - - write = "1 0 1 0 1 1 0 0 1 0 1 0 1 0 0 0", - "x x x x x x x x i i i i i i i i"; - ; - - memory "efuse" - size = 1; - min_write_delay = 4500; - max_write_delay = 4500; - read = "0 1 0 1 0 0 0 0 0 0 0 0 1 0 0 0", - "x x x x x x x x o o o o o o o o"; - - write = "1 0 1 0 1 1 0 0 1 0 1 0 0 1 0 0", - "x x x x x x x x x x x x x i i i"; - ; - - memory "lock" - size = 1; - min_write_delay = 4500; - max_write_delay = 4500; - read = "0 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0", - "x x x x x x x x x x o o o o o o"; - - write = "1 0 1 0 1 1 0 0 1 1 1 x x x x x", - "x x x x x x x x 1 1 i i i i i i"; - ; - - memory "signature" - size = 3; - read = "0 0 1 1 0 0 0 0 0 0 0 x x x x x", - "x x x x x x a1 a0 o o o o o o o o"; - ; - - memory "calibration" - size = 1; - read = "0 0 1 1 1 0 0 0 0 0 0 x x x x x", - "0 0 0 0 0 0 0 0 o o o o o o o o"; - ; - ; - -#------------------------------------------------------------ -# ATmega6490 -#------------------------------------------------------------ - -# identical to ATmega649 - -part parent "m649" - id = "m6490"; - desc = "ATmega6490"; - signature = 0x1e 0x96 0x04; - - ocdrev = 3; - ; - -#------------------------------------------------------------ -# ATmega32 -#------------------------------------------------------------ - -part - id = "m32"; - desc = "ATmega32"; - has_jtag = yes; - stk500_devcode = 0x91; - avr910_devcode = 0x72; - signature = 0x1e 0x95 0x02; - chip_erase_delay = 9000; - pagel = 0xd7; - bs2 = 0xa0; - reset = dedicated; - pgm_enable = "1 0 1 0 1 1 0 0 0 1 0 1 0 0 1 1", - "x x x x x x x x x x x x x x x x"; - - chip_erase = "1 0 1 0 1 1 0 0 1 0 0 0 0 0 0 0", - "x x x x x x x x x x x x x x x x"; - timeout = 200; - stabdelay = 100; - cmdexedelay = 25; - synchloops = 32; - bytedelay = 0; - pollindex = 3; - pollvalue = 0x53; - predelay = 1; - postdelay = 1; - pollmethod = 0; - - pp_controlstack = - 0x0E, 0x1E, 0x0F, 0x1F, 0x2E, 0x3E, 0x2F, 0x3F, - 0x4E, 0x5E, 0x4F, 0x5F, 0x6E, 0x7E, 0x6F, 0x7F, - 0x66, 0x76, 0x67, 0x77, 0x6A, 0x7A, 0x6B, 0x7B, - 0xBE, 0xFD, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00; - hventerstabdelay = 100; - progmodedelay = 0; - latchcycles = 6; - togglevtg = 0; - poweroffdelay = 0; - resetdelayms = 0; - resetdelayus = 0; - hvleavestabdelay = 15; - chiperasepulsewidth = 0; - chiperasepolltimeout = 10; - programfusepulsewidth = 0; - programfusepolltimeout = 5; - programlockpulsewidth = 0; - programlockpolltimeout = 5; - - idr = 0x31; - spmcr = 0x57; - allowfullpagebitstream = yes; - - ocdrev = 2; - - memory "eeprom" - paged = no; /* leave this "no" */ - page_size = 4; /* for parallel programming */ - size = 1024; - min_write_delay = 9000; - max_write_delay = 9000; - readback_p1 = 0xff; - readback_p2 = 0xff; - read = " 1 0 1 0 0 0 0 0", - " 0 0 x x x x a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " o o o o o o o o"; - - write = " 1 1 0 0 0 0 0 0", - " 0 0 x x x x a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " i i i i i i i i"; - - loadpage_lo = " 1 1 0 0 0 0 0 1", - " 0 0 0 0 0 0 0 0", - " 0 0 0 0 0 0 a1 a0", - " i i i i i i i i"; - - writepage = " 1 1 0 0 0 0 1 0", - " 0 0 x x x x a9 a8", - " a7 a6 a5 a4 a3 a2 0 0", - " x x x x x x x x"; - - mode = 0x04; - delay = 10; - blocksize = 64; - readsize = 256; - ; - - memory "flash" - paged = yes; - size = 32768; - page_size = 128; - num_pages = 256; - min_write_delay = 4500; - max_write_delay = 4500; - readback_p1 = 0xff; - readback_p2 = 0xff; - read_lo = " 0 0 1 0 0 0 0 0", - " 0 0 a13 a12 a11 a10 a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " o o o o o o o o"; - - read_hi = " 0 0 1 0 1 0 0 0", - " 0 0 a13 a12 a11 a10 a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " o o o o o o o o"; - - loadpage_lo = " 0 1 0 0 0 0 0 0", - " 0 0 x x x x x x", - " x x a5 a4 a3 a2 a1 a0", - " i i i i i i i i"; - - loadpage_hi = " 0 1 0 0 1 0 0 0", - " 0 0 x x x x x x", - " x x a5 a4 a3 a2 a1 a0", - " i i i i i i i i"; - - writepage = " 0 1 0 0 1 1 0 0", - " 0 0 a13 a12 a11 a10 a9 a8", - " a7 a6 x x x x x x", - " x x x x x x x x"; - - mode = 0x21; - delay = 6; - blocksize = 64; - readsize = 256; - ; - - memory "lfuse" - size = 1; - min_write_delay = 2000; - max_write_delay = 2000; - read = "0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0", - "x x x x x x x x o o o o o o o o"; - - write = "1 0 1 0 1 1 0 0 1 0 1 0 0 0 0 0", - "x x x x x x x x i i i i i i i i"; - ; - - memory "hfuse" - size = 1; - min_write_delay = 2000; - max_write_delay = 2000; - read = "0 1 0 1 1 0 0 0 0 0 0 0 1 0 0 0", - "x x x x x x x x o o o o o o o o"; - - write = "1 0 1 0 1 1 0 0 1 0 1 0 1 0 0 0", - "x x x x x x x x i i i i i i i i"; - ; - - memory "lock" - size = 1; - min_write_delay = 2000; - max_write_delay = 2000; - read = "0 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0", - "x x x x x x x x x x o o o o o o"; - - write = "1 0 1 0 1 1 0 0 1 1 1 x x x x x", - "x x x x x x x x 1 1 i i i i i i"; - ; - - memory "signature" - size = 3; - read = "0 0 1 1 0 0 0 0 x x x x x x x x", - "x x x x x x a1 a0 o o o o o o o o"; - ; - - memory "calibration" - size = 4; - read = "0 0 1 1 1 0 0 0 0 0 x x x x x x", - "0 0 0 0 0 0 a1 a0 o o o o o o o o"; - ; - ; - -#------------------------------------------------------------ -# ATmega161 -#------------------------------------------------------------ - -part - id = "m161"; - desc = "ATmega161"; - stk500_devcode = 0x80; - avr910_devcode = 0x60; - signature = 0x1e 0x94 0x01; - chip_erase_delay = 28000; - pagel = 0xd7; - bs2 = 0xa0; - pgm_enable = "1 0 1 0 1 1 0 0 0 1 0 1 0 0 1 1", - "x x x x x x x x x x x x x x x x"; - - chip_erase = "1 0 1 0 1 1 0 0 1 0 0 0 0 0 0 0", - "x x x x x x x x x x x x x x x x"; - timeout = 200; - stabdelay = 100; - cmdexedelay = 25; - synchloops = 32; - bytedelay = 0; - pollindex = 3; - pollvalue = 0x53; - predelay = 1; - postdelay = 1; - pollmethod = 0; - - pp_controlstack = - 0x0E, 0x1E, 0x0F, 0x1F, 0x2E, 0x3E, 0x2F, 0x3F, - 0x4E, 0x5E, 0x4F, 0x5F, 0x6E, 0x7E, 0x6F, 0x7F, - 0x66, 0x76, 0x67, 0x77, 0x6A, 0x7A, 0x6B, 0x7B, - 0xBE, 0xFD, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00; - hventerstabdelay = 100; - progmodedelay = 0; - latchcycles = 0; - togglevtg = 0; - poweroffdelay = 0; - resetdelayms = 0; - resetdelayus = 0; - hvleavestabdelay = 15; - chiperasepulsewidth = 0; - chiperasepolltimeout = 30; - programfusepulsewidth = 0; - programfusepolltimeout = 2; - programlockpulsewidth = 0; - programlockpolltimeout = 2; - - memory "eeprom" - size = 512; - min_write_delay = 3400; - max_write_delay = 3400; - readback_p1 = 0xff; - readback_p2 = 0xff; - read = " 1 0 1 0 0 0 0 0", - " x x x x x x x a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " o o o o o o o o"; - - write = " 1 1 0 0 0 0 0 0", - " x x x x x x x a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " i i i i i i i i"; - - mode = 0x04; - delay = 5; - blocksize = 128; - readsize = 256; - ; - - memory "flash" - paged = yes; - size = 16384; - page_size = 128; - num_pages = 128; - min_write_delay = 14000; - max_write_delay = 14000; - readback_p1 = 0xff; - readback_p2 = 0xff; - read_lo = " 0 0 1 0 0 0 0 0", - " x x x a12 a11 a10 a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " o o o o o o o o"; - - read_hi = " 0 0 1 0 1 0 0 0", - " x x x a12 a11 a10 a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " o o o o o o o o"; - - loadpage_lo = " 0 1 0 0 0 0 0 0", - " x x x x x x x x", - " x x a5 a4 a3 a2 a1 a0", - " i i i i i i i i"; - - loadpage_hi = " 0 1 0 0 1 0 0 0", - " x x x x x x x x", - " x x a5 a4 a3 a2 a1 a0", - " i i i i i i i i"; - - writepage = " 0 1 0 0 1 1 0 0", - " x x x a12 a11 a10 a9 a8", - " a7 a6 x x x x x x", - " x x x x x x x x"; - - mode = 0x21; - delay = 16; - blocksize = 128; - readsize = 256; - ; - - memory "fuse" - size = 1; - min_write_delay = 2000; - max_write_delay = 2000; - read = "0 1 0 1 0 0 0 0 x x x x x x x x", - "x x x x x x x x x o x o o o o o"; - - write = "1 0 1 0 1 1 0 0 1 0 1 x x x x x", - "x x x x x x x x 1 i 1 i i i i i"; - ; - - memory "lock" - size = 1; - min_write_delay = 2000; - max_write_delay = 2000; - read = "0 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0", - "x x x x x x x x x x o o o o o o"; - - write = "1 0 1 0 1 1 0 0 1 1 1 x x x x x", - "x x x x x x x x 1 1 i i i i i i"; - ; - memory "signature" - size = 3; - read = "0 0 1 1 0 0 0 0 x x x x x x x x", - "x x x x x x a1 a0 o o o o o o o o"; - ; - ; - - -#------------------------------------------------------------ -# ATmega8 -#------------------------------------------------------------ - -part - id = "m8"; - desc = "ATmega8"; - stk500_devcode = 0x70; - avr910_devcode = 0x76; - signature = 0x1e 0x93 0x07; - pagel = 0xd7; - bs2 = 0xc2; - chip_erase_delay = 10000; - pgm_enable = "1 0 1 0 1 1 0 0 0 1 0 1 0 0 1 1", - "x x x x x x x x x x x x x x x x"; - - chip_erase = "1 0 1 0 1 1 0 0 1 0 0 x x x x x", - "x x x x x x x x x x x x x x x x"; - - timeout = 200; - stabdelay = 100; - cmdexedelay = 25; - synchloops = 32; - bytedelay = 0; - pollindex = 3; - pollvalue = 0x53; - predelay = 1; - postdelay = 1; - pollmethod = 0; - - pp_controlstack = - 0x0E, 0x1E, 0x0F, 0x1F, 0x2E, 0x3E, 0x2F, 0x3F, - 0x4E, 0x5E, 0x4F, 0x5F, 0x6E, 0x7E, 0x6F, 0x7F, - 0x66, 0x76, 0x67, 0x77, 0x6A, 0x7A, 0x6B, 0x7B, - 0xBE, 0xFD, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00; - hventerstabdelay = 100; - progmodedelay = 0; - latchcycles = 5; - togglevtg = 1; - poweroffdelay = 15; - resetdelayms = 2; - resetdelayus = 0; - hvleavestabdelay = 15; - resetdelay = 15; - chiperasepulsewidth = 0; - chiperasepolltimeout = 10; - programfusepulsewidth = 0; - programfusepolltimeout = 5; - programlockpulsewidth = 0; - programlockpolltimeout = 5; - - memory "eeprom" - size = 512; - page_size = 4; - min_write_delay = 9000; - max_write_delay = 9000; - readback_p1 = 0xff; - readback_p2 = 0xff; - read = " 1 0 1 0 0 0 0 0", - " 0 0 x x x x x a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " o o o o o o o o"; - - write = " 1 1 0 0 0 0 0 0", - " 0 0 x x x x x a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " i i i i i i i i"; - - mode = 0x04; - delay = 20; - blocksize = 128; - readsize = 256; - ; - memory "flash" - paged = yes; - size = 8192; - page_size = 64; - num_pages = 128; - min_write_delay = 4500; - max_write_delay = 4500; - readback_p1 = 0xff; - readback_p2 = 0x00; - read_lo = " 0 0 1 0 0 0 0 0", - " 0 0 0 0 a11 a10 a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " o o o o o o o o"; - - read_hi = " 0 0 1 0 1 0 0 0", - " 0 0 0 0 a11 a10 a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " o o o o o o o o"; - - loadpage_lo = " 0 1 0 0 0 0 0 0", - " 0 0 0 0 x x x x", - " x x x a4 a3 a2 a1 a0", - " i i i i i i i i"; - - loadpage_hi = " 0 1 0 0 1 0 0 0", - " 0 0 0 0 x x x x", - " x x x a4 a3 a2 a1 a0", - " i i i i i i i i"; - - writepage = " 0 1 0 0 1 1 0 0", - " 0 0 0 0 a11 a10 a9 a8", - " a7 a6 a5 x x x x x", - " x x x x x x x x"; - - mode = 0x21; - delay = 10; - blocksize = 64; - readsize = 256; - ; - - memory "lfuse" - size = 1; - min_write_delay = 2000; - max_write_delay = 2000; - read = "0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0", - "x x x x x x x x o o o o o o o o"; - - write = "1 0 1 0 1 1 0 0 1 0 1 0 0 0 0 0", - "x x x x x x x x i i i i i i i i"; - ; - - memory "hfuse" - size = 1; - min_write_delay = 2000; - max_write_delay = 2000; - read = "0 1 0 1 1 0 0 0 0 0 0 0 1 0 0 0", - "x x x x x x x x o o o o o o o o"; - - write = "1 0 1 0 1 1 0 0 1 0 1 0 1 0 0 0", - "x x x x x x x x i i i i i i i i"; - ; - - # Required for Arduino IDE - # see: https://github.com/arduino/Arduino/issues/2075 - # https://github.com/arduino/Arduino/issues/2075#issuecomment-238031689 - memory "efuse" - size = 0; - ; - - memory "lock" - size = 1; - min_write_delay = 2000; - max_write_delay = 2000; - read = "0 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0", - "x x x x x x x x x x o o o o o o"; - - write = "1 0 1 0 1 1 0 0 1 1 1 x x x x x", - "x x x x x x x x 1 1 i i i i i i"; - ; - - memory "calibration" - size = 4; - read = "0 0 1 1 1 0 0 0 0 0 x x x x x x", - "0 0 0 0 0 0 a1 a0 o o o o o o o o"; - ; - - memory "signature" - size = 3; - read = "0 0 1 1 0 0 0 0 x x x x x x x x", - "x x x x x x a1 a0 o o o o o o o o"; - ; - ; - - - -#------------------------------------------------------------ -# ATmega8515 -#------------------------------------------------------------ - -part - id = "m8515"; - desc = "ATmega8515"; - stk500_devcode = 0x63; - avr910_devcode = 0x3A; - signature = 0x1e 0x93 0x06; - chip_erase_delay = 9000; - pgm_enable = "1 0 1 0 1 1 0 0 0 1 0 1 0 0 1 1", - "x x x x x x x x x x x x x x x x"; - - chip_erase = "1 0 1 0 1 1 0 0 1 0 0 x x x x x", - "x x x x x x x x x x x x x x x x"; - - timeout = 200; - stabdelay = 100; - cmdexedelay = 25; - synchloops = 32; - bytedelay = 0; - pollindex = 3; - pollvalue = 0x53; - predelay = 1; - postdelay = 1; - pollmethod = 0; - - pp_controlstack = - 0x0E, 0x1E, 0x0F, 0x1F, 0x2E, 0x3E, 0x2F, 0x3F, - 0x4E, 0x5E, 0x4F, 0x5F, 0x6E, 0x7E, 0x6F, 0x7F, - 0x66, 0x76, 0x67, 0x77, 0x6A, 0x7A, 0x6B, 0x7B, - 0xBE, 0xFD, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00; - hventerstabdelay = 100; - progmodedelay = 0; - latchcycles = 6; - togglevtg = 0; - poweroffdelay = 0; - resetdelayms = 0; - resetdelayus = 0; - hvleavestabdelay = 15; - chiperasepulsewidth = 0; - chiperasepolltimeout = 10; - programfusepulsewidth = 0; - programfusepolltimeout = 5; - programlockpulsewidth = 0; - programlockpolltimeout = 5; - - memory "eeprom" - size = 512; - min_write_delay = 9000; - max_write_delay = 9000; - readback_p1 = 0xff; - readback_p2 = 0xff; - read = " 1 0 1 0 0 0 0 0", - " 0 0 x x x x x a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " o o o o o o o o"; - - write = " 1 1 0 0 0 0 0 0", - " 0 0 x x x x x a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " i i i i i i i i"; - - mode = 0x04; - delay = 20; - blocksize = 128; - readsize = 256; - ; - memory "flash" - paged = yes; - size = 8192; - page_size = 64; - num_pages = 128; - min_write_delay = 4500; - max_write_delay = 4500; - readback_p1 = 0xff; - readback_p2 = 0xff; - read_lo = " 0 0 1 0 0 0 0 0", - " 0 0 0 0 a11 a10 a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " o o o o o o o o"; - - read_hi = " 0 0 1 0 1 0 0 0", - " 0 0 0 0 a11 a10 a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " o o o o o o o o"; - - loadpage_lo = " 0 1 0 0 0 0 0 0", - " 0 0 0 0 x x x x", - " x x x a4 a3 a2 a1 a0", - " i i i i i i i i"; - - loadpage_hi = " 0 1 0 0 1 0 0 0", - " 0 0 0 0 x x x x", - " x x x a4 a3 a2 a1 a0", - " i i i i i i i i"; - - writepage = " 0 1 0 0 1 1 0 0", - " 0 0 0 0 a11 a10 a9 a8", - " a7 a6 a5 x x x x x", - " x x x x x x x x"; - - mode = 0x21; - delay = 6; - blocksize = 64; - readsize = 256; - ; - - memory "lfuse" - size = 1; - min_write_delay = 4500; - max_write_delay = 4500; - read = "0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0", - "x x x x x x x x o o o o o o o o"; - - write = "1 0 1 0 1 1 0 0 1 0 1 0 0 0 0 0", - "x x x x x x x x i i i i i i i i"; - ; - - memory "hfuse" - size = 1; - min_write_delay = 4500; - max_write_delay = 4500; - read = "0 1 0 1 1 0 0 0 0 0 0 0 1 0 0 0", - "x x x x x x x x o o o o o o o o"; - - write = "1 0 1 0 1 1 0 0 1 0 1 0 1 0 0 0", - "x x x x x x x x i i i i i i i i"; - ; - - memory "lock" - size = 1; - min_write_delay = 4500; - max_write_delay = 4500; - read = "0 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0", - "x x x x x x x x x x o o o o o o"; - - write = "1 0 1 0 1 1 0 0 1 1 1 x x x x x", - "x x x x x x x x 1 1 i i i i i i"; - ; - - memory "calibration" - size = 4; - read = "0 0 1 1 1 0 0 0 0 0 x x x x x x", - "0 0 0 0 0 0 a1 a0 o o o o o o o o"; - ; - - memory "signature" - size = 3; - read = "0 0 1 1 0 0 0 0 x x x x x x x x", - "x x x x x x a1 a0 o o o o o o o o"; - ; - ; - - - - -#------------------------------------------------------------ -# ATmega8535 -#------------------------------------------------------------ - -part - id = "m8535"; - desc = "ATmega8535"; - stk500_devcode = 0x64; - avr910_devcode = 0x69; - signature = 0x1e 0x93 0x08; - pagel = 0xd7; - bs2 = 0xa0; - chip_erase_delay = 9000; - pgm_enable = "1 0 1 0 1 1 0 0 0 1 0 1 0 0 1 1", - "x x x x x x x x x x x x x x x x"; - - chip_erase = "1 0 1 0 1 1 0 0 1 0 0 x x x x x", - "x x x x x x x x x x x x x x x x"; - - timeout = 200; - stabdelay = 100; - cmdexedelay = 25; - synchloops = 32; - bytedelay = 0; - pollindex = 3; - pollvalue = 0x53; - predelay = 1; - postdelay = 1; - pollmethod = 0; - - pp_controlstack = - 0x0E, 0x1E, 0x0F, 0x1F, 0x2E, 0x3E, 0x2F, 0x3F, - 0x4E, 0x5E, 0x4F, 0x5F, 0x6E, 0x7E, 0x6F, 0x7F, - 0x66, 0x76, 0x67, 0x77, 0x6A, 0x7A, 0x6B, 0x7B, - 0xBE, 0xFD, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00; - hventerstabdelay = 100; - progmodedelay = 0; - latchcycles = 6; - togglevtg = 0; - poweroffdelay = 0; - resetdelayms = 0; - resetdelayus = 0; - hvleavestabdelay = 15; - chiperasepulsewidth = 0; - chiperasepolltimeout = 10; - programfusepulsewidth = 0; - programfusepolltimeout = 5; - programlockpulsewidth = 0; - programlockpolltimeout = 5; - - memory "eeprom" - size = 512; - min_write_delay = 9000; - max_write_delay = 9000; - readback_p1 = 0xff; - readback_p2 = 0xff; - read = " 1 0 1 0 0 0 0 0", - " 0 0 x x x x x a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " o o o o o o o o"; - - write = " 1 1 0 0 0 0 0 0", - " 0 0 x x x x x a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " i i i i i i i i"; - - mode = 0x04; - delay = 20; - blocksize = 128; - readsize = 256; - ; - memory "flash" - paged = yes; - size = 8192; - page_size = 64; - num_pages = 128; - min_write_delay = 4500; - max_write_delay = 4500; - readback_p1 = 0xff; - readback_p2 = 0xff; - read_lo = " 0 0 1 0 0 0 0 0", - " 0 0 0 0 a11 a10 a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " o o o o o o o o"; - - read_hi = " 0 0 1 0 1 0 0 0", - " 0 0 0 0 a11 a10 a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " o o o o o o o o"; - - loadpage_lo = " 0 1 0 0 0 0 0 0", - " 0 0 0 0 x x x x", - " x x x a4 a3 a2 a1 a0", - " i i i i i i i i"; - - loadpage_hi = " 0 1 0 0 1 0 0 0", - " 0 0 0 0 x x x x", - " x x x a4 a3 a2 a1 a0", - " i i i i i i i i"; - - writepage = " 0 1 0 0 1 1 0 0", - " 0 0 0 0 a11 a10 a9 a8", - " a7 a6 a5 x x x x x", - " x x x x x x x x"; - - mode = 0x21; - delay = 6; - blocksize = 64; - readsize = 256; - ; - - memory "lfuse" - size = 1; - min_write_delay = 2000; - max_write_delay = 2000; - read = "0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0", - "x x x x x x x x o o o o o o o o"; - - write = "1 0 1 0 1 1 0 0 1 0 1 0 0 0 0 0", - "x x x x x x x x i i i i i i i i"; - ; - - memory "hfuse" - size = 1; - min_write_delay = 2000; - max_write_delay = 2000; - read = "0 1 0 1 1 0 0 0 0 0 0 0 1 0 0 0", - "x x x x x x x x o o o o o o o o"; - - write = "1 0 1 0 1 1 0 0 1 0 1 0 1 0 0 0", - "x x x x x x x x i i i i i i i i"; - ; - - memory "lock" - size = 1; - min_write_delay = 2000; - max_write_delay = 2000; - read = "0 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0", - "x x x x x x x x x x o o o o o o"; - - write = "1 0 1 0 1 1 0 0 1 1 1 x x x x x", - "x x x x x x x x 1 1 i i i i i i"; - ; - - memory "calibration" - size = 4; - read = "0 0 1 1 1 0 0 0 0 0 x x x x x x", - "0 0 0 0 0 0 a1 a0 o o o o o o o o"; - ; - - memory "signature" - size = 3; - read = "0 0 1 1 0 0 0 0 x x x x x x x x", - "x x x x x x a1 a0 o o o o o o o o"; - ; - ; - - -#------------------------------------------------------------ -# ATtiny26 -#------------------------------------------------------------ - -part - id = "t26"; - desc = "ATtiny26"; - stk500_devcode = 0x21; - avr910_devcode = 0x5e; - signature = 0x1e 0x91 0x09; - pagel = 0xb3; - bs2 = 0xb2; - chip_erase_delay = 9000; - pgm_enable = "1 0 1 0 1 1 0 0 0 1 0 1 0 0 1 1", - "x x x x x x x x x x x x x x x x"; - - chip_erase = "1 0 1 0 1 1 0 0 1 0 0 x x x x x", - "x x x x x x x x x x x x x x x x"; - - timeout = 200; - stabdelay = 100; - cmdexedelay = 25; - synchloops = 32; - bytedelay = 0; - pollindex = 3; - pollvalue = 0x53; - predelay = 1; - postdelay = 1; - pollmethod = 0; - - pp_controlstack = - 0xC4, 0xE4, 0xC4, 0xE4, 0xCC, 0xEC, 0xCC, 0xEC, - 0xD4, 0xF4, 0xD4, 0xF4, 0xDC, 0xFC, 0xDC, 0xFC, - 0xC8, 0xE8, 0xD8, 0xF8, 0x4C, 0x6C, 0x5C, 0x7C, - 0xEC, 0xBC, 0x00, 0x06, 0x00, 0x00, 0x00, 0x00; - hventerstabdelay = 100; - progmodedelay = 0; - latchcycles = 5; - togglevtg = 1; - poweroffdelay = 15; - resetdelayms = 2; - resetdelayus = 0; - hvleavestabdelay = 15; - chiperasepulsewidth = 0; - chiperasepolltimeout = 10; - programfusepulsewidth = 0; - programfusepolltimeout = 5; - programlockpulsewidth = 0; - programlockpolltimeout = 5; - - memory "eeprom" - size = 128; - min_write_delay = 9000; - max_write_delay = 9000; - readback_p1 = 0xff; - readback_p2 = 0xff; - read = "1 0 1 0 0 0 0 0 x x x x x x x x", - "x a6 a5 a4 a3 a2 a1 a0 o o o o o o o o"; - - write = "1 1 0 0 0 0 0 0 x x x x x x x x", - "x a6 a5 a4 a3 a2 a1 a0 i i i i i i i i"; - - mode = 0x04; - delay = 10; - blocksize = 64; - readsize = 256; - ; - - memory "flash" - paged = yes; - size = 2048; - page_size = 32; - num_pages = 64; - min_write_delay = 4500; - max_write_delay = 4500; - readback_p1 = 0xff; - readback_p2 = 0xff; - read_lo = " 0 0 1 0 0 0 0 0", - " x x x x x x a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " o o o o o o o o"; - - read_hi = " 0 0 1 0 1 0 0 0", - " x x x x x x a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " o o o o o o o o"; - - loadpage_lo = " 0 1 0 0 0 0 0 0", - " x x x x x x x x", - " x x x x a3 a2 a1 a0", - " i i i i i i i i"; - - loadpage_hi = " 0 1 0 0 1 0 0 0", - " x x x x x x x x", - " x x x x a3 a2 a1 a0", - " i i i i i i i i"; - - writepage = " 0 1 0 0 1 1 0 0", - " x x x x x x a9 a8", - " a7 a6 a5 a4 x x x x", - " x x x x x x x x"; - - mode = 0x21; - delay = 6; - blocksize = 16; - readsize = 256; - ; - - memory "signature" - size = 3; - read = "0 0 1 1 0 0 0 0 x x x x x x x x", - "0 0 0 0 0 0 a1 a0 o o o o o o o o"; - ; - - memory "lock" - size = 1; - read = "0 1 0 1 1 0 0 0 x x x x x x x x", - "x x x x x x x x x x x x x x o o"; - - write = "1 0 1 0 1 1 0 0 1 1 1 1 1 1 i i", - "x x x x x x x x x x x x x x x x"; - min_write_delay = 9000; - max_write_delay = 9000; - ; - - memory "lfuse" - size = 1; - write = "1 0 1 0 1 1 0 0 1 0 1 0 0 0 0 0", - "x x x x x x x x i i i i i i i i"; - - read = "0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0", - "x x x x x x x x o o o o o o o o"; - min_write_delay = 9000; - max_write_delay = 9000; - ; - - memory "hfuse" - size = 1; - write = "1 0 1 0 1 1 0 0 1 0 1 0 1 0 0 0", - "x x x x x x x x x x x i i i i i"; - - read = "0 1 0 1 1 0 0 0 0 0 0 0 1 0 0 0", - "x x x x x x x x o o o o o o o o"; - min_write_delay = 9000; - max_write_delay = 9000; - ; - - memory "calibration" - size = 4; - read = "0 0 1 1 1 0 0 0 x x x x x x x x", - "0 0 0 0 0 0 a1 a0 o o o o o o o o"; - ; - -; - - -#------------------------------------------------------------ -# ATtiny261 -#------------------------------------------------------------ -# Close to ATtiny26 - -part - id = "t261"; - desc = "ATtiny261"; - has_debugwire = yes; - flash_instr = 0xB4, 0x00, 0x10; - eeprom_instr = 0xBB, 0xFF, 0xBB, 0xEE, 0xBB, 0xCC, 0xB2, 0x0D, - 0xBC, 0x00, 0xB4, 0x00, 0xBA, 0x0D, 0xBB, 0xBC, - 0x99, 0xE1, 0xBB, 0xAC; -# stk500_devcode = 0x21; -# avr910_devcode = 0x5e; - signature = 0x1e 0x91 0x0c; - pagel = 0xb3; - bs2 = 0xb2; - chip_erase_delay = 4000; - - pgm_enable = "1 0 1 0 1 1 0 0 0 1 0 1 0 0 1 1", - "x x x x x x x x x x x x x x x x"; - - chip_erase = "1 0 1 0 1 1 0 0 1 0 0 x x x x x", - "x x x x x x x x x x x x x x x x"; - - timeout = 200; - stabdelay = 100; - cmdexedelay = 25; - synchloops = 32; - bytedelay = 0; - pollindex = 3; - pollvalue = 0x53; - predelay = 1; - postdelay = 1; - pollmethod = 0; - - pp_controlstack = - 0xC4, 0xE4, 0xC4, 0xE4, 0xCC, 0xEC, 0xCC, 0xEC, - 0xD4, 0xF4, 0xD4, 0xF4, 0xDC, 0xFC, 0xDC, 0xFC, - 0xC8, 0xE8, 0xD8, 0xF8, 0x4C, 0x6C, 0x5C, 0x7C, - 0xEC, 0xBC, 0x00, 0x06, 0x00, 0x00, 0x00, 0x00; - hventerstabdelay = 100; - progmodedelay = 0; - latchcycles = 5; - togglevtg = 1; - poweroffdelay = 15; - resetdelayms = 2; - resetdelayus = 0; - hvleavestabdelay = 15; - chiperasepulsewidth = 0; - chiperasepolltimeout = 10; - programfusepulsewidth = 0; - programfusepolltimeout = 5; - programlockpulsewidth = 0; - programlockpolltimeout = 5; - - ocdrev = 1; - - memory "eeprom" - paged = no; - size = 128; - page_size = 4; - num_pages = 32; - min_write_delay = 4000; - max_write_delay = 4000; - readback_p1 = 0xff; - readback_p2 = 0xff; - - read = "1 0 1 0 0 0 0 0 x x x x x x x x", - "x a6 a5 a4 a3 a2 a1 a0 o o o o o o o o"; - - write = "1 1 0 0 0 0 0 0 x x x x x x x x", - "x a6 a5 a4 a3 a2 a1 a0 i i i i i i i i"; - - loadpage_lo = " 1 1 0 0 0 0 0 1", - " 0 0 0 0 0 0 0 0", - " 0 0 0 0 0 0 a1 a0", - " i i i i i i i i"; - - writepage = " 1 1 0 0 0 0 1 0", - " 0 0 x x x x x x", - " x a6 a5 a4 a3 a2 0 0", - " x x x x x x x x"; - - mode = 0x41; - delay = 10; - blocksize = 4; - readsize = 256; - ; - - memory "flash" - paged = yes; - size = 2048; - page_size = 32; - num_pages = 64; - min_write_delay = 4500; - max_write_delay = 4500; - readback_p1 = 0xff; - readback_p2 = 0xff; - - read_lo = " 0 0 1 0 0 0 0 0", - " x x x x x x a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " o o o o o o o o"; - - read_hi = " 0 0 1 0 1 0 0 0", - " x x x x x x a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " o o o o o o o o"; - - loadpage_lo = " 0 1 0 0 0 0 0 0", - " x x x x x x x x", - " x x x x a3 a2 a1 a0", - " i i i i i i i i"; - - loadpage_hi = " 0 1 0 0 1 0 0 0", - " x x x x x x x x", - " x x x x a3 a2 a1 a0", - " i i i i i i i i"; - - writepage = " 0 1 0 0 1 1 0 0", - " x x x x x x a9 a8", - " a7 a6 a5 a4 x x x x", - " x x x x x x x x"; - - mode = 0x41; - delay = 6; - blocksize = 32; - readsize = 256; - ; - - memory "signature" - size = 3; - read = "0 0 1 1 0 0 0 0 x x x x x x x x", - "0 0 0 0 0 0 a1 a0 o o o o o o o o"; - ; - - memory "lock" - size = 1; - read = "0 1 0 1 1 0 0 0 x x x x x x x x", - "x x x x x x x x x x x x x x o o"; - - write = "1 0 1 0 1 1 0 0 1 1 1 1 1 1 i i", - "x x x x x x x x x x x x x x x x"; - min_write_delay = 4500; - max_write_delay = 4500; - ; - - memory "lfuse" - size = 1; - write = "1 0 1 0 1 1 0 0 1 0 1 0 0 0 0 0", - "x x x x x x x x i i i i i i i i"; - - read = "0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0", - "x x x x x x x x o o o o o o o o"; - min_write_delay = 4500; - max_write_delay = 4500; - ; - - memory "hfuse" - size = 1; - write = "1 0 1 0 1 1 0 0 1 0 1 0 1 0 0 0", - "x x x x x x x x i i i i i i i i"; - - read = "0 1 0 1 1 0 0 0 0 0 0 0 1 0 0 0", - "x x x x x x x x o o o o o o o o"; - min_write_delay = 4500; - max_write_delay = 4500; - ; - - memory "efuse" - size = 1; - write = "1 0 1 0 1 1 0 0 1 0 1 0 0 1 0 0", - "x x x x x x x x x x x x x x x i"; - - read = "0 1 0 1 0 0 0 0 0 0 0 0 1 0 0 0", - "x x x x x x x x o o o o o o o o"; - min_write_delay = 4500; - max_write_delay = 4500; - ; - - memory "calibration" - size = 1; - read = "0 0 1 1 1 0 0 0 x x x x x x x x", - "0 0 0 0 0 0 0 0 o o o o o o o o"; - ; - -; - - -#------------------------------------------------------------ -# ATtiny461 -#------------------------------------------------------------ -# Close to ATtiny261 - -part - id = "t461"; - desc = "ATtiny461"; - has_debugwire = yes; - flash_instr = 0xB4, 0x00, 0x10; - eeprom_instr = 0xBB, 0xFF, 0xBB, 0xEE, 0xBB, 0xCC, 0xB2, 0x0D, - 0xBC, 0x00, 0xB4, 0x00, 0xBA, 0x0D, 0xBB, 0xBC, - 0x99, 0xE1, 0xBB, 0xAC; -# stk500_devcode = 0x21; -# avr910_devcode = 0x5e; - signature = 0x1e 0x92 0x08; - pagel = 0xb3; - bs2 = 0xb2; - chip_erase_delay = 4000; - - pgm_enable = "1 0 1 0 1 1 0 0 0 1 0 1 0 0 1 1", - "x x x x x x x x x x x x x x x x"; - - chip_erase = "1 0 1 0 1 1 0 0 1 0 0 x x x x x", - "x x x x x x x x x x x x x x x x"; - - timeout = 200; - stabdelay = 100; - cmdexedelay = 25; - synchloops = 32; - bytedelay = 0; - pollindex = 3; - pollvalue = 0x53; - predelay = 1; - postdelay = 1; - pollmethod = 0; - - pp_controlstack = - 0xC4, 0xE4, 0xC4, 0xE4, 0xCC, 0xEC, 0xCC, 0xEC, - 0xD4, 0xF4, 0xD4, 0xF4, 0xDC, 0xFC, 0xDC, 0xFC, - 0xC8, 0xE8, 0xD8, 0xF8, 0x4C, 0x6C, 0x5C, 0x7C, - 0xEC, 0xBC, 0x00, 0x06, 0x00, 0x00, 0x00, 0x00; - hventerstabdelay = 100; - progmodedelay = 0; - latchcycles = 5; - togglevtg = 1; - poweroffdelay = 15; - resetdelayms = 2; - resetdelayus = 0; - hvleavestabdelay = 15; - chiperasepulsewidth = 0; - chiperasepolltimeout = 10; - programfusepulsewidth = 0; - programfusepolltimeout = 5; - programlockpulsewidth = 0; - programlockpolltimeout = 5; - - ocdrev = 1; - - memory "eeprom" - paged = no; - size = 256; - page_size = 4; - num_pages = 64; - min_write_delay = 4000; - max_write_delay = 4000; - readback_p1 = 0xff; - readback_p2 = 0xff; - - read = " 1 0 1 0 0 0 0 0 x x x x x x x x", - "a7 a6 a5 a4 a3 a2 a1 a0 o o o o o o o o"; - - write = " 1 1 0 0 0 0 0 0 x x x x x x x x", - "a7 a6 a5 a4 a3 a2 a1 a0 i i i i i i i i"; - - loadpage_lo = " 1 1 0 0 0 0 0 1", - " 0 0 0 0 0 0 0 0", - " 0 0 0 0 0 0 a1 a0", - " i i i i i i i i"; - - writepage = " 1 1 0 0 0 0 1 0", - " 0 0 x x x x x x", - " a7 a6 a5 a4 a3 a2 0 0", - " x x x x x x x x"; - - mode = 0x41; - delay = 10; - blocksize = 4; - readsize = 256; - ; - - memory "flash" - paged = yes; - size = 4096; - page_size = 64; - num_pages = 64; - min_write_delay = 4500; - max_write_delay = 4500; - readback_p1 = 0xff; - readback_p2 = 0xff; - - read_lo = " 0 0 1 0 0 0 0 0", - " x x x x x a10 a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " o o o o o o o o"; - - read_hi = " 0 0 1 0 1 0 0 0", - " x x x x x a10 a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " o o o o o o o o"; - - loadpage_lo = " 0 1 0 0 0 0 0 0", - " x x x x x x x x", - " x x x a4 a3 a2 a1 a0", - " i i i i i i i i"; - - loadpage_hi = " 0 1 0 0 1 0 0 0", - " x x x x x x x x", - " x x x a4 a3 a2 a1 a0", - " i i i i i i i i"; - - writepage = " 0 1 0 0 1 1 0 0", - " x x x x x a10 a9 a8", - " a7 a6 a5 x x x x x", - " x x x x x x x x"; - - mode = 0x41; - delay = 6; - blocksize = 64; - readsize = 256; - ; - - memory "signature" - size = 3; - read = "0 0 1 1 0 0 0 0 x x x x x x x x", - "0 0 0 0 0 0 a1 a0 o o o o o o o o"; - ; - - memory "lock" - size = 1; - read = "0 1 0 1 1 0 0 0 x x x x x x x x", - "x x x x x x x x x x x x x x o o"; - - write = "1 0 1 0 1 1 0 0 1 1 1 1 1 1 i i", - "x x x x x x x x x x x x x x x x"; - min_write_delay = 4500; - max_write_delay = 4500; - ; - - memory "lfuse" - size = 1; - write = "1 0 1 0 1 1 0 0 1 0 1 0 0 0 0 0", - "x x x x x x x x i i i i i i i i"; - - read = "0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0", - "x x x x x x x x o o o o o o o o"; - min_write_delay = 4500; - max_write_delay = 4500; - ; - - memory "hfuse" - size = 1; - write = "1 0 1 0 1 1 0 0 1 0 1 0 1 0 0 0", - "x x x x x x x x i i i i i i i i"; - - read = "0 1 0 1 1 0 0 0 0 0 0 0 1 0 0 0", - "x x x x x x x x o o o o o o o o"; - min_write_delay = 4500; - max_write_delay = 4500; - ; - - memory "efuse" - size = 1; - write = "1 0 1 0 1 1 0 0 1 0 1 0 0 1 0 0", - "x x x x x x x x x x x x x x x i"; - - read = "0 1 0 1 0 0 0 0 0 0 0 0 1 0 0 0", - "x x x x x x x x o o o o o o o o"; - min_write_delay = 4500; - max_write_delay = 4500; - ; - - memory "calibration" - size = 1; - read = "0 0 1 1 1 0 0 0 x x x x x x x x", - "0 0 0 0 0 0 0 0 o o o o o o o o"; - ; - -; - - -#------------------------------------------------------------ -# ATtiny861 -#------------------------------------------------------------ -# Close to ATtiny461 - -part - id = "t861"; - desc = "ATtiny861"; - has_debugwire = yes; - flash_instr = 0xB4, 0x00, 0x10; - eeprom_instr = 0xBB, 0xFF, 0xBB, 0xEE, 0xBB, 0xCC, 0xB2, 0x0D, - 0xBC, 0x00, 0xB4, 0x00, 0xBA, 0x0D, 0xBB, 0xBC, - 0x99, 0xE1, 0xBB, 0xAC; -# stk500_devcode = 0x21; -# avr910_devcode = 0x5e; - signature = 0x1e 0x93 0x0d; - pagel = 0xb3; - bs2 = 0xb2; - chip_erase_delay = 4000; - - pgm_enable = "1 0 1 0 1 1 0 0 0 1 0 1 0 0 1 1", - "x x x x x x x x x x x x x x x x"; - - chip_erase = "1 0 1 0 1 1 0 0 1 0 0 x x x x x", - "x x x x x x x x x x x x x x x x"; - - timeout = 200; - stabdelay = 100; - cmdexedelay = 25; - synchloops = 32; - bytedelay = 0; - pollindex = 3; - pollvalue = 0x53; - predelay = 1; - postdelay = 1; - pollmethod = 0; - - pp_controlstack = - 0xC4, 0xE4, 0xC4, 0xE4, 0xCC, 0xEC, 0xCC, 0xEC, - 0xD4, 0xF4, 0xD4, 0xF4, 0xDC, 0xFC, 0xDC, 0xFC, - 0xC8, 0xE8, 0xD8, 0xF8, 0x4C, 0x6C, 0x5C, 0x7C, - 0xEC, 0xBC, 0x00, 0x06, 0x00, 0x00, 0x00, 0x00; - hventerstabdelay = 100; - progmodedelay = 0; - latchcycles = 5; - togglevtg = 1; - poweroffdelay = 15; - resetdelayms = 2; - resetdelayus = 0; - hvleavestabdelay = 15; - chiperasepulsewidth = 0; - chiperasepolltimeout = 10; - programfusepulsewidth = 0; - programfusepolltimeout = 5; - programlockpulsewidth = 0; - programlockpolltimeout = 5; - - ocdrev = 1; - - memory "eeprom" - paged = no; - size = 512; - num_pages = 128; - page_size = 4; - min_write_delay = 4000; - max_write_delay = 4000; - readback_p1 = 0xff; - readback_p2 = 0xff; - - read = " 1 0 1 0 0 0 0 0 x x x x x x x a8", - "a7 a6 a5 a4 a3 a2 a1 a0 o o o o o o o o"; - - write = " 1 1 0 0 0 0 0 0 x x x x x x x a8", - "a7 a6 a5 a4 a3 a2 a1 a0 i i i i i i i i"; - - loadpage_lo = " 1 1 0 0 0 0 0 1", - " 0 0 0 0 0 0 0 0", - " 0 0 0 0 0 0 a1 a0", - " i i i i i i i i"; - - writepage = " 1 1 0 0 0 0 1 0", - " 0 0 x x x x x a8", - " a7 a6 a5 a4 a3 a2 0 0", - " x x x x x x x x"; - - mode = 0x41; - delay = 10; - blocksize = 4; - readsize = 256; - ; - - memory "flash" - paged = yes; - size = 8192; - page_size = 64; - num_pages = 128; - min_write_delay = 4500; - max_write_delay = 4500; - readback_p1 = 0xff; - readback_p2 = 0xff; - - read_lo = " 0 0 1 0 0 0 0 0", - " x x x x a11 a10 a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " o o o o o o o o"; - - read_hi = " 0 0 1 0 1 0 0 0", - " x x x x a11 a10 a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " o o o o o o o o"; - - loadpage_lo = " 0 1 0 0 0 0 0 0", - " x x x x x x x x", - " x x x a4 a3 a2 a1 a0", - " i i i i i i i i"; - - loadpage_hi = " 0 1 0 0 1 0 0 0", - " x x x x x x x x", - " x x x a4 a3 a2 a1 a0", - " i i i i i i i i"; - - writepage = " 0 1 0 0 1 1 0 0", - " x x x x a11 a10 a9 a8", - " a7 a6 a5 x x x x x", - " x x x x x x x x"; - - mode = 0x41; - delay = 6; - blocksize = 64; - readsize = 256; - ; - - memory "signature" - size = 3; - read = "0 0 1 1 0 0 0 0 x x x x x x x x", - "0 0 0 0 0 0 a1 a0 o o o o o o o o"; - ; - - memory "lock" - size = 1; - read = "0 1 0 1 1 0 0 0 x x x x x x x x", - "x x x x x x x x x x x x x x o o"; - - write = "1 0 1 0 1 1 0 0 1 1 1 1 1 1 i i", - "x x x x x x x x x x x x x x x x"; - min_write_delay = 4500; - max_write_delay = 4500; - ; - - memory "lfuse" - size = 1; - write = "1 0 1 0 1 1 0 0 1 0 1 0 0 0 0 0", - "x x x x x x x x i i i i i i i i"; - - read = "0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0", - "x x x x x x x x o o o o o o o o"; - min_write_delay = 4500; - max_write_delay = 4500; - ; - - memory "hfuse" - size = 1; - write = "1 0 1 0 1 1 0 0 1 0 1 0 1 0 0 0", - "x x x x x x x x i i i i i i i i"; - - read = "0 1 0 1 1 0 0 0 0 0 0 0 1 0 0 0", - "x x x x x x x x o o o o o o o o"; - min_write_delay = 4500; - max_write_delay = 4500; - ; - - memory "efuse" - size = 1; - write = "1 0 1 0 1 1 0 0 1 0 1 0 0 1 0 0", - "x x x x x x x x x x x x x x x i"; - - read = "0 1 0 1 0 0 0 0 0 0 0 0 1 0 0 0", - "x x x x x x x x o o o o o o o o"; - min_write_delay = 4500; - max_write_delay = 4500; - ; - - memory "calibration" - size = 1; - read = "0 0 1 1 1 0 0 0 x x x x x x x x", - "0 0 0 0 0 0 0 0 o o o o o o o o"; - ; - -; - - -#------------------------------------------------------------ -# ATtiny28 -#------------------------------------------------------------ - -# This is an HVPP-only device. - -part - id = "t28"; - desc = "ATtiny28"; - stk500_devcode = 0x22; - avr910_devcode = 0x5c; - signature = 0x1e 0x91 0x07; - - pp_controlstack = - 0x0E, 0x1E, 0x0F, 0x1F, 0x2E, 0x3E, 0x2F, 0x3F, - 0x4E, 0x5E, 0x4F, 0x5F, 0x6E, 0x7E, 0x6F, 0x7F, - 0x66, 0x76, 0x67, 0x77, 0x6A, 0x7A, 0x6B, 0x7B, - 0xBE, 0xFD, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00; - hventerstabdelay = 100; - progmodedelay = 0; - latchcycles = 0; - togglevtg = 0; - poweroffdelay = 0; - resetdelayms = 0; - resetdelayus = 0; - hvleavestabdelay = 15; - resetdelay = 15; - chiperasepulsewidth = 0; - chiperasepolltimeout = 10; - programfusepulsewidth = 0; - programfusepolltimeout = 5; - programlockpulsewidth = 0; - programlockpolltimeout = 5; - - memory "flash" - size = 2048; - page_size = 2; - readsize = 256; - delay = 5; - ; - - memory "signature" - size = 3; - ; - - memory "lock" - size = 1; - ; - - memory "calibration" - size = 1; - ; - - memory "fuse" - size = 1; - ; -; - - - -#------------------------------------------------------------ -# ATmega48 -#------------------------------------------------------------ - -part - id = "m48"; - desc = "ATmega48"; - has_debugwire = yes; - flash_instr = 0xB6, 0x01, 0x11; - eeprom_instr = 0xBD, 0xF2, 0xBD, 0xE1, 0xBB, 0xCF, 0xB4, 0x00, - 0xBE, 0x01, 0xB6, 0x01, 0xBC, 0x00, 0xBB, 0xBF, - 0x99, 0xF9, 0xBB, 0xAF; - stk500_devcode = 0x59; -# avr910_devcode = 0x; - signature = 0x1e 0x92 0x05; - pagel = 0xd7; - bs2 = 0xc2; - chip_erase_delay = 45000; - pgm_enable = "1 0 1 0 1 1 0 0 0 1 0 1 0 0 1 1", - "x x x x x x x x x x x x x x x x"; - - chip_erase = "1 0 1 0 1 1 0 0 1 0 0 x x x x x", - "x x x x x x x x x x x x x x x x"; - - timeout = 200; - stabdelay = 100; - cmdexedelay = 25; - synchloops = 32; - bytedelay = 0; - pollindex = 3; - pollvalue = 0x53; - predelay = 1; - postdelay = 1; - pollmethod = 1; - - pp_controlstack = - 0x0E, 0x1E, 0x0F, 0x1F, 0x2E, 0x3E, 0x2F, 0x3F, - 0x4E, 0x5E, 0x4F, 0x5F, 0x6E, 0x7E, 0x6F, 0x7F, - 0x66, 0x76, 0x67, 0x77, 0x6A, 0x7A, 0x6B, 0x7B, - 0xBE, 0xFD, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00; - hventerstabdelay = 100; - progmodedelay = 0; - latchcycles = 5; - togglevtg = 1; - poweroffdelay = 15; - resetdelayms = 1; - resetdelayus = 0; - hvleavestabdelay = 15; - resetdelay = 15; - chiperasepulsewidth = 0; - chiperasepolltimeout = 10; - programfusepulsewidth = 0; - programfusepolltimeout = 5; - programlockpulsewidth = 0; - programlockpolltimeout = 5; - - ocdrev = 1; - - memory "eeprom" - paged = no; - page_size = 4; - size = 256; - min_write_delay = 3600; - max_write_delay = 3600; - readback_p1 = 0xff; - readback_p2 = 0xff; - read = " 1 0 1 0 0 0 0 0", - " 0 0 0 x x x x x", - " a7 a6 a5 a4 a3 a2 a1 a0", - " o o o o o o o o"; - - write = " 1 1 0 0 0 0 0 0", - " 0 0 0 x x x x x", - " a7 a6 a5 a4 a3 a2 a1 a0", - " i i i i i i i i"; - - loadpage_lo = " 1 1 0 0 0 0 0 1", - " 0 0 0 0 0 0 0 0", - " 0 0 0 0 0 0 a1 a0", - " i i i i i i i i"; - - writepage = " 1 1 0 0 0 0 1 0", - " 0 0 x x x x x x", - " a7 a6 a5 a4 a3 a2 0 0", - " x x x x x x x x"; - - mode = 0x41; - delay = 20; - blocksize = 4; - readsize = 256; - ; - memory "flash" - paged = yes; - size = 4096; - page_size = 64; - num_pages = 64; - min_write_delay = 4500; - max_write_delay = 4500; - readback_p1 = 0x00; - readback_p2 = 0x00; - read_lo = " 0 0 1 0 0 0 0 0", - " 0 0 0 0 0 a10 a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " o o o o o o o o"; - - read_hi = " 0 0 1 0 1 0 0 0", - " 0 0 0 0 0 a10 a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " o o o o o o o o"; - - loadpage_lo = " 0 1 0 0 0 0 0 0", - " 0 0 0 x x x x x", - " x x x a4 a3 a2 a1 a0", - " i i i i i i i i"; - - loadpage_hi = " 0 1 0 0 1 0 0 0", - " 0 0 0 x x x x x", - " x x x a4 a3 a2 a1 a0", - " i i i i i i i i"; - - writepage = " 0 1 0 0 1 1 0 0", - " 0 0 0 0 0 a10 a9 a8", - " a7 a6 a5 x x x x x", - " x x x x x x x x"; - - mode = 0x41; - delay = 6; - blocksize = 64; - readsize = 256; - ; - - memory "lfuse" - size = 1; - min_write_delay = 4500; - max_write_delay = 4500; - read = "0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0", - "x x x x x x x x o o o o o o o o"; - - write = "1 0 1 0 1 1 0 0 1 0 1 0 0 0 0 0", - "x x x x x x x x i i i i i i i i"; - ; - - memory "hfuse" - size = 1; - min_write_delay = 4500; - max_write_delay = 4500; - read = "0 1 0 1 1 0 0 0 0 0 0 0 1 0 0 0", - "x x x x x x x x o o o o o o o o"; - - write = "1 0 1 0 1 1 0 0 1 0 1 0 1 0 0 0", - "x x x x x x x x i i i i i i i i"; - ; - - memory "efuse" - size = 1; - min_write_delay = 4500; - max_write_delay = 4500; - read = "0 1 0 1 0 0 0 0 0 0 0 0 1 0 0 0", - "x x x x x x x x o o o o o o o o"; - - write = "1 0 1 0 1 1 0 0 1 0 1 0 0 1 0 0", - "x x x x x x x x x x x x x x x i"; - ; - - memory "lock" - size = 1; - min_write_delay = 4500; - max_write_delay = 4500; - read = "0 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0", - "x x x x x x x x x x o o o o o o"; - - write = "1 0 1 0 1 1 0 0 1 1 1 x x x x x", - "x x x x x x x x 1 1 i i i i i i"; - ; - - memory "calibration" - size = 1; - read = "0 0 1 1 1 0 0 0 0 0 0 x x x x x", - "0 0 0 0 0 0 0 0 o o o o o o o o"; - ; - - memory "signature" - size = 3; - read = "0 0 1 1 0 0 0 0 0 0 0 x x x x x", - "x x x x x x a1 a0 o o o o o o o o"; - ; - ; - -#------------------------------------------------------------ -# ATmega48P -#------------------------------------------------------------ - -part parent "m48" - id = "m48p"; - desc = "ATmega48P"; - signature = 0x1e 0x92 0x0a; - - ocdrev = 1; - ; - -#------------------------------------------------------------ -# ATmega48PB -#------------------------------------------------------------ - -part parent "m48" - id = "m48pb"; - desc = "ATmega48PB"; - signature = 0x1e 0x92 0x10; - - ocdrev = 1; - ; - -#------------------------------------------------------------ -# ATmega88 -#------------------------------------------------------------ - -part - id = "m88"; - desc = "ATmega88"; - has_debugwire = yes; - flash_instr = 0xB6, 0x01, 0x11; - eeprom_instr = 0xBD, 0xF2, 0xBD, 0xE1, 0xBB, 0xCF, 0xB4, 0x00, - 0xBE, 0x01, 0xB6, 0x01, 0xBC, 0x00, 0xBB, 0xBF, - 0x99, 0xF9, 0xBB, 0xAF; - stk500_devcode = 0x73; -# avr910_devcode = 0x; - signature = 0x1e 0x93 0x0a; - pagel = 0xd7; - bs2 = 0xc2; - chip_erase_delay = 9000; - pgm_enable = "1 0 1 0 1 1 0 0 0 1 0 1 0 0 1 1", - "x x x x x x x x x x x x x x x x"; - - chip_erase = "1 0 1 0 1 1 0 0 1 0 0 x x x x x", - "x x x x x x x x x x x x x x x x"; - - timeout = 200; - stabdelay = 100; - cmdexedelay = 25; - synchloops = 32; - bytedelay = 0; - pollindex = 3; - pollvalue = 0x53; - predelay = 1; - postdelay = 1; - pollmethod = 1; - - pp_controlstack = - 0x0E, 0x1E, 0x0F, 0x1F, 0x2E, 0x3E, 0x2F, 0x3F, - 0x4E, 0x5E, 0x4F, 0x5F, 0x6E, 0x7E, 0x6F, 0x7F, - 0x66, 0x76, 0x67, 0x77, 0x6A, 0x7A, 0x6B, 0x7B, - 0xBE, 0xFD, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00; - hventerstabdelay = 100; - progmodedelay = 0; - latchcycles = 5; - togglevtg = 1; - poweroffdelay = 15; - resetdelayms = 1; - resetdelayus = 0; - hvleavestabdelay = 15; - resetdelay = 15; - chiperasepulsewidth = 0; - chiperasepolltimeout = 10; - programfusepulsewidth = 0; - programfusepolltimeout = 5; - programlockpulsewidth = 0; - programlockpolltimeout = 5; - - ocdrev = 1; - - memory "eeprom" - paged = no; - page_size = 4; - size = 512; - min_write_delay = 3600; - max_write_delay = 3600; - readback_p1 = 0xff; - readback_p2 = 0xff; - read = " 1 0 1 0 0 0 0 0", - " 0 0 0 x x x x a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " o o o o o o o o"; - - write = " 1 1 0 0 0 0 0 0", - " 0 0 0 x x x x a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " i i i i i i i i"; - - loadpage_lo = " 1 1 0 0 0 0 0 1", - " 0 0 0 0 0 0 0 0", - " 0 0 0 0 0 0 a1 a0", - " i i i i i i i i"; - - writepage = " 1 1 0 0 0 0 1 0", - " 0 0 x x x x x a8", - " a7 a6 a5 a4 a3 a2 0 0", - " x x x x x x x x"; - - mode = 0x41; - delay = 20; - blocksize = 4; - readsize = 256; - ; - memory "flash" - paged = yes; - size = 8192; - page_size = 64; - num_pages = 128; - min_write_delay = 4500; - max_write_delay = 4500; - readback_p1 = 0xff; - readback_p2 = 0xff; - read_lo = " 0 0 1 0 0 0 0 0", - " 0 0 0 0 a11 a10 a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " o o o o o o o o"; - - read_hi = " 0 0 1 0 1 0 0 0", - " 0 0 0 0 a11 a10 a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " o o o o o o o o"; - - loadpage_lo = " 0 1 0 0 0 0 0 0", - " 0 0 0 x x x x x", - " x x x a4 a3 a2 a1 a0", - " i i i i i i i i"; - - loadpage_hi = " 0 1 0 0 1 0 0 0", - " 0 0 0 x x x x x", - " x x x a4 a3 a2 a1 a0", - " i i i i i i i i"; - - writepage = " 0 1 0 0 1 1 0 0", - " 0 0 0 0 a11 a10 a9 a8", - " a7 a6 a5 x x x x x", - " x x x x x x x x"; - - mode = 0x41; - delay = 6; - blocksize = 64; - readsize = 256; - ; - - memory "lfuse" - size = 1; - min_write_delay = 4500; - max_write_delay = 4500; - read = "0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0", - "x x x x x x x x o o o o o o o o"; - - write = "1 0 1 0 1 1 0 0 1 0 1 0 0 0 0 0", - "x x x x x x x x i i i i i i i i"; - ; - - memory "hfuse" - size = 1; - min_write_delay = 4500; - max_write_delay = 4500; - read = "0 1 0 1 1 0 0 0 0 0 0 0 1 0 0 0", - "x x x x x x x x o o o o o o o o"; - - write = "1 0 1 0 1 1 0 0 1 0 1 0 1 0 0 0", - "x x x x x x x x i i i i i i i i"; - ; - - memory "efuse" - size = 1; - min_write_delay = 4500; - max_write_delay = 4500; - read = "0 1 0 1 0 0 0 0 0 0 0 0 1 0 0 0", - "x x x x x x x x o o o o o o o o"; - - write = "1 0 1 0 1 1 0 0 1 0 1 0 0 1 0 0", - "x x x x x x x x x x x x x i i i"; - ; - - memory "lock" - size = 1; - min_write_delay = 4500; - max_write_delay = 4500; - read = "0 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0", - "x x x x x x x x x x o o o o o o"; - - write = "1 0 1 0 1 1 0 0 1 1 1 x x x x x", - "x x x x x x x x 1 1 i i i i i i"; - ; - - memory "calibration" - size = 1; - read = "0 0 1 1 1 0 0 0 0 0 0 x x x x x", - "0 0 0 0 0 0 0 0 o o o o o o o o"; - ; - - memory "signature" - size = 3; - read = "0 0 1 1 0 0 0 0 0 0 0 x x x x x", - "x x x x x x a1 a0 o o o o o o o o"; - ; - ; - -#------------------------------------------------------------ -# ATmega88P -#------------------------------------------------------------ - -part parent "m88" - id = "m88p"; - desc = "ATmega88P"; - signature = 0x1e 0x93 0x0f; - - ocdrev = 1; - ; - -#------------------------------------------------------------ -# ATmega88PB -#------------------------------------------------------------ - -part parent "m88" - id = "m88pb"; - desc = "ATmega88PB"; - signature = 0x1e 0x93 0x16; - - ocdrev = 1; - ; - -#------------------------------------------------------------ -# ATmega168 -#------------------------------------------------------------ - -part - id = "m168"; - desc = "ATmega168"; - has_debugwire = yes; - flash_instr = 0xB6, 0x01, 0x11; - eeprom_instr = 0xBD, 0xF2, 0xBD, 0xE1, 0xBB, 0xCF, 0xB4, 0x00, - 0xBE, 0x01, 0xB6, 0x01, 0xBC, 0x00, 0xBB, 0xBF, - 0x99, 0xF9, 0xBB, 0xAF; - stk500_devcode = 0x86; - # avr910_devcode = 0x; - signature = 0x1e 0x94 0x06; - pagel = 0xd7; - bs2 = 0xc2; - chip_erase_delay = 9000; - pgm_enable = "1 0 1 0 1 1 0 0 0 1 0 1 0 0 1 1", - "x x x x x x x x x x x x x x x x"; - - chip_erase = "1 0 1 0 1 1 0 0 1 0 0 x x x x x", - "x x x x x x x x x x x x x x x x"; - - timeout = 200; - stabdelay = 100; - cmdexedelay = 25; - synchloops = 32; - bytedelay = 0; - pollindex = 3; - pollvalue = 0x53; - predelay = 1; - postdelay = 1; - pollmethod = 1; - - pp_controlstack = - 0x0E, 0x1E, 0x0F, 0x1F, 0x2E, 0x3E, 0x2F, 0x3F, - 0x4E, 0x5E, 0x4F, 0x5F, 0x6E, 0x7E, 0x6F, 0x7F, - 0x66, 0x76, 0x67, 0x77, 0x6A, 0x7A, 0x6B, 0x7B, - 0xBE, 0xFD, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00; - hventerstabdelay = 100; - progmodedelay = 0; - latchcycles = 5; - togglevtg = 1; - poweroffdelay = 15; - resetdelayms = 1; - resetdelayus = 0; - hvleavestabdelay = 15; - resetdelay = 15; - chiperasepulsewidth = 0; - chiperasepolltimeout = 10; - programfusepulsewidth = 0; - programfusepolltimeout = 5; - programlockpulsewidth = 0; - programlockpolltimeout = 5; - - ocdrev = 1; - - memory "eeprom" - paged = no; - page_size = 4; - size = 512; - min_write_delay = 3600; - max_write_delay = 3600; - readback_p1 = 0xff; - readback_p2 = 0xff; - read = " 1 0 1 0 0 0 0 0", - " 0 0 0 x x x x a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " o o o o o o o o"; - - write = " 1 1 0 0 0 0 0 0", - " 0 0 0 x x x x a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " i i i i i i i i"; - - loadpage_lo = " 1 1 0 0 0 0 0 1", - " 0 0 0 0 0 0 0 0", - " 0 0 0 0 0 0 a1 a0", - " i i i i i i i i"; - - writepage = " 1 1 0 0 0 0 1 0", - " 0 0 x x x x x a8", - " a7 a6 a5 a4 a3 a2 0 0", - " x x x x x x x x"; - - mode = 0x41; - delay = 20; - blocksize = 4; - readsize = 256; - ; - - memory "flash" - paged = yes; - size = 16384; - page_size = 128; - num_pages = 128; - min_write_delay = 4500; - max_write_delay = 4500; - readback_p1 = 0xff; - readback_p2 = 0xff; - read_lo = " 0 0 1 0 0 0 0 0", - " 0 0 0 a12 a11 a10 a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " o o o o o o o o"; - - read_hi = " 0 0 1 0 1 0 0 0", - " 0 0 0 a12 a11 a10 a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " o o o o o o o o"; - - loadpage_lo = " 0 1 0 0 0 0 0 0", - " 0 0 0 x x x x x", - " x x a5 a4 a3 a2 a1 a0", - " i i i i i i i i"; - - loadpage_hi = " 0 1 0 0 1 0 0 0", - " 0 0 0 x x x x x", - " x x a5 a4 a3 a2 a1 a0", - " i i i i i i i i"; - - writepage = " 0 1 0 0 1 1 0 0", - " 0 0 0 a12 a11 a10 a9 a8", - " a7 a6 x x x x x x", - " x x x x x x x x"; - - mode = 0x41; - delay = 6; - blocksize = 128; - readsize = 256; - - ; - - memory "lfuse" - size = 1; - min_write_delay = 4500; - max_write_delay = 4500; - read = "0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0", - "x x x x x x x x o o o o o o o o"; - - write = "1 0 1 0 1 1 0 0 1 0 1 0 0 0 0 0", - "x x x x x x x x i i i i i i i i"; - ; - - memory "hfuse" - size = 1; - min_write_delay = 4500; - max_write_delay = 4500; - read = "0 1 0 1 1 0 0 0 0 0 0 0 1 0 0 0", - "x x x x x x x x o o o o o o o o"; - - write = "1 0 1 0 1 1 0 0 1 0 1 0 1 0 0 0", - "x x x x x x x x i i i i i i i i"; - ; - - memory "efuse" - size = 1; - min_write_delay = 4500; - max_write_delay = 4500; - read = "0 1 0 1 0 0 0 0 0 0 0 0 1 0 0 0", - "x x x x x x x x o o o o o o o o"; - - write = "1 0 1 0 1 1 0 0 1 0 1 0 0 1 0 0", - "x x x x x x x x x x x x x i i i"; - ; - - memory "lock" - size = 1; - min_write_delay = 4500; - max_write_delay = 4500; - read = "0 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0", - "x x x x x x x x x x o o o o o o"; - - write = "1 0 1 0 1 1 0 0 1 1 1 x x x x x", - "x x x x x x x x 1 1 i i i i i i"; - ; - - memory "calibration" - size = 1; - read = "0 0 1 1 1 0 0 0 0 0 0 x x x x x", - "0 0 0 0 0 0 0 0 o o o o o o o o"; - ; - - memory "signature" - size = 3; - read = "0 0 1 1 0 0 0 0 0 0 0 x x x x x", - "x x x x x x a1 a0 o o o o o o o o"; - ; -; - -#------------------------------------------------------------ -# ATmega168P -#------------------------------------------------------------ - -part parent "m168" - id = "m168p"; - desc = "ATmega168P"; - signature = 0x1e 0x94 0x0b; - - ocdrev = 1; -; - -#------------------------------------------------------------ -# ATmega168PB -#------------------------------------------------------------ - -part parent "m168" - id = "m168pb"; - desc = "ATmega168PB"; - signature = 0x1e 0x94 0x15; - - ocdrev = 1; -; - -#------------------------------------------------------------ -# ATtiny88 -#------------------------------------------------------------ - -part - id = "t88"; - desc = "ATtiny88"; - has_debugwire = yes; - flash_instr = 0xB6, 0x01, 0x11; - eeprom_instr = 0xBD, 0xF2, 0xBD, 0xE1, 0xBB, 0xCF, 0xB4, 0x00, - 0xBE, 0x01, 0xB6, 0x01, 0xBC, 0x00, 0xBB, 0xBF, - 0x99, 0xF9, 0xBB, 0xAF; - stk500_devcode = 0x73; -# avr910_devcode = 0x; - signature = 0x1e 0x93 0x11; - pagel = 0xd7; - bs2 = 0xc2; - chip_erase_delay = 9000; - pgm_enable = "1 0 1 0 1 1 0 0 0 1 0 1 0 0 1 1", - "x x x x x x x x x x x x x x x x"; - - chip_erase = "1 0 1 0 1 1 0 0 1 0 0 x x x x x", - "x x x x x x x x x x x x x x x x"; - - timeout = 200; - stabdelay = 100; - cmdexedelay = 25; - synchloops = 32; - bytedelay = 0; - pollindex = 3; - pollvalue = 0x53; - predelay = 1; - postdelay = 1; - pollmethod = 1; - - pp_controlstack = - 0x0E, 0x1E, 0x0F, 0x1F, 0x2E, 0x3E, 0x2F, 0x3F, - 0x4E, 0x5E, 0x4F, 0x5F, 0x6E, 0x7E, 0x6F, 0x7F, - 0x66, 0x76, 0x67, 0x77, 0x6A, 0x7A, 0x6B, 0x7B, - 0xBE, 0xFD, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00; - hventerstabdelay = 100; - progmodedelay = 0; - latchcycles = 5; - togglevtg = 1; - poweroffdelay = 15; - resetdelayms = 1; - resetdelayus = 0; - hvleavestabdelay = 15; - resetdelay = 15; - chiperasepulsewidth = 0; - chiperasepolltimeout = 10; - programfusepulsewidth = 0; - programfusepolltimeout = 5; - programlockpulsewidth = 0; - programlockpolltimeout = 5; - - ocdrev = 1; - - memory "eeprom" - paged = no; - page_size = 4; - size = 64; - min_write_delay = 3600; - max_write_delay = 3600; - readback_p1 = 0xff; - readback_p2 = 0xff; - read = " 1 0 1 0 0 0 0 0", - " 0 0 0 x x x x x", - " x a6 a5 a4 a3 a2 a1 a0", - " o o o o o o o o"; - - write = " 1 1 0 0 0 0 0 0", - " 0 0 0 x x x x x", - " x a6 a5 a4 a3 a2 a1 a0", - " i i i i i i i i"; - - loadpage_lo = " 1 1 0 0 0 0 0 1", - " 0 0 0 0 0 0 0 0", - " 0 0 0 0 0 0 a1 a0", - " i i i i i i i i"; - - writepage = " 1 1 0 0 0 0 1 0", - " 0 0 x x x x x x", - " x a6 a5 a4 a3 a2 0 0", - " x x x x x x x x"; - - mode = 0x41; - delay = 20; - blocksize = 4; - readsize = 64; - ; - memory "flash" - paged = yes; - size = 8192; - page_size = 64; - num_pages = 128; - min_write_delay = 4500; - max_write_delay = 4500; - readback_p1 = 0xff; - readback_p2 = 0xff; - read_lo = " 0 0 1 0 0 0 0 0", - " 0 0 0 0 a11 a10 a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " o o o o o o o o"; - - read_hi = " 0 0 1 0 1 0 0 0", - " 0 0 0 0 a11 a10 a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " o o o o o o o o"; - - loadpage_lo = " 0 1 0 0 0 0 0 0", - " 0 0 0 x x x x x", - " x x x a4 a3 a2 a1 a0", - " i i i i i i i i"; - - loadpage_hi = " 0 1 0 0 1 0 0 0", - " 0 0 0 x x x x x", - " x x x a4 a3 a2 a1 a0", - " i i i i i i i i"; - - writepage = " 0 1 0 0 1 1 0 0", - " 0 0 0 0 a11 a10 a9 a8", - " a7 a6 a5 x x x x x", - " x x x x x x x x"; - - mode = 0x41; - delay = 6; - blocksize = 64; - readsize = 256; - ; - - memory "lfuse" - size = 1; - min_write_delay = 4500; - max_write_delay = 4500; - read = "0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0", - "x x x x x x x x o o o o o o o o"; - - write = "1 0 1 0 1 1 0 0 1 0 1 0 0 0 0 0", - "x x x x x x x x i i i i i i i i"; - ; - - memory "hfuse" - size = 1; - min_write_delay = 4500; - max_write_delay = 4500; - read = "0 1 0 1 1 0 0 0 0 0 0 0 1 0 0 0", - "x x x x x x x x o o o o o o o o"; - - write = "1 0 1 0 1 1 0 0 1 0 1 0 1 0 0 0", - "x x x x x x x x i i i i i i i i"; - ; - - memory "efuse" - size = 1; - min_write_delay = 4500; - max_write_delay = 4500; - read = "0 1 0 1 0 0 0 0 0 0 0 0 1 0 0 0", - "x x x x x x x x o o o o o o o o"; - - write = "1 0 1 0 1 1 0 0 1 0 1 0 0 1 0 0", - "x x x x x x x x x x x x x x x i"; - ; - - memory "lock" - size = 1; - min_write_delay = 4500; - max_write_delay = 4500; - read = "0 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0", - "x x x x x x x x x x o o o o o o"; - - write = "1 0 1 0 1 1 0 0 1 1 1 x x x x x", - "x x x x x x x x 1 1 i i i i i i"; - ; - - memory "calibration" - size = 1; - read = "0 0 1 1 1 0 0 0 0 0 0 x x x x x", - "0 0 0 0 0 0 0 0 o o o o o o o o"; - ; - - memory "signature" - size = 3; - read = "0 0 1 1 0 0 0 0 0 0 0 x x x x x", - "x x x x x x a1 a0 o o o o o o o o"; - ; - ; - -#------------------------------------------------------------ -# ATmega328 -#------------------------------------------------------------ - -part - id = "m328"; - desc = "ATmega328"; - has_debugwire = yes; - flash_instr = 0xB6, 0x01, 0x11; - eeprom_instr = 0xBD, 0xF2, 0xBD, 0xE1, 0xBB, 0xCF, 0xB4, 0x00, - 0xBE, 0x01, 0xB6, 0x01, 0xBC, 0x00, 0xBB, 0xBF, - 0x99, 0xF9, 0xBB, 0xAF; - stk500_devcode = 0x86; - # avr910_devcode = 0x; - signature = 0x1e 0x95 0x14; - pagel = 0xd7; - bs2 = 0xc2; - chip_erase_delay = 9000; - pgm_enable = "1 0 1 0 1 1 0 0 0 1 0 1 0 0 1 1", - "x x x x x x x x x x x x x x x x"; - - chip_erase = "1 0 1 0 1 1 0 0 1 0 0 x x x x x", - "x x x x x x x x x x x x x x x x"; - - timeout = 200; - stabdelay = 100; - cmdexedelay = 25; - synchloops = 32; - bytedelay = 0; - pollindex = 3; - pollvalue = 0x53; - predelay = 1; - postdelay = 1; - pollmethod = 1; - - pp_controlstack = - 0x0E, 0x1E, 0x0F, 0x1F, 0x2E, 0x3E, 0x2F, 0x3F, - 0x4E, 0x5E, 0x4F, 0x5F, 0x6E, 0x7E, 0x6F, 0x7F, - 0x66, 0x76, 0x67, 0x77, 0x6A, 0x7A, 0x6B, 0x7B, - 0xBE, 0xFD, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00; - hventerstabdelay = 100; - progmodedelay = 0; - latchcycles = 5; - togglevtg = 1; - poweroffdelay = 15; - resetdelayms = 1; - resetdelayus = 0; - hvleavestabdelay = 15; - resetdelay = 15; - chiperasepulsewidth = 0; - chiperasepolltimeout = 10; - programfusepulsewidth = 0; - programfusepolltimeout = 5; - programlockpulsewidth = 0; - programlockpolltimeout = 5; - - ocdrev = 1; - - memory "eeprom" - paged = no; - page_size = 4; - size = 1024; - min_write_delay = 3600; - max_write_delay = 3600; - readback_p1 = 0xff; - readback_p2 = 0xff; - read = " 1 0 1 0 0 0 0 0", - " 0 0 0 x x x a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " o o o o o o o o"; - - write = " 1 1 0 0 0 0 0 0", - " 0 0 0 x x x a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " i i i i i i i i"; - - loadpage_lo = " 1 1 0 0 0 0 0 1", - " 0 0 0 0 0 0 0 0", - " 0 0 0 0 0 0 a1 a0", - " i i i i i i i i"; - - writepage = " 1 1 0 0 0 0 1 0", - " 0 0 x x x x a9 a8", - " a7 a6 a5 a4 a3 a2 0 0", - " x x x x x x x x"; - - mode = 0x41; - delay = 20; - blocksize = 4; - readsize = 256; - ; - - memory "flash" - paged = yes; - size = 32768; - page_size = 128; - num_pages = 256; - min_write_delay = 4500; - max_write_delay = 4500; - readback_p1 = 0xff; - readback_p2 = 0xff; - read_lo = " 0 0 1 0 0 0 0 0", - " 0 0 a13 a12 a11 a10 a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " o o o o o o o o"; - - read_hi = " 0 0 1 0 1 0 0 0", - " 0 0 a13 a12 a11 a10 a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " o o o o o o o o"; - - loadpage_lo = " 0 1 0 0 0 0 0 0", - " 0 0 0 x x x x x", - " x x a5 a4 a3 a2 a1 a0", - " i i i i i i i i"; - - loadpage_hi = " 0 1 0 0 1 0 0 0", - " 0 0 0 x x x x x", - " x x a5 a4 a3 a2 a1 a0", - " i i i i i i i i"; - - writepage = " 0 1 0 0 1 1 0 0", - " 0 0 a13 a12 a11 a10 a9 a8", - " a7 a6 x x x x x x", - " x x x x x x x x"; - - mode = 0x41; - delay = 6; - blocksize = 128; - readsize = 256; - - ; - - memory "lfuse" - size = 1; - min_write_delay = 4500; - max_write_delay = 4500; - read = "0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0", - "x x x x x x x x o o o o o o o o"; - - write = "1 0 1 0 1 1 0 0 1 0 1 0 0 0 0 0", - "x x x x x x x x i i i i i i i i"; - ; - - memory "hfuse" - size = 1; - min_write_delay = 4500; - max_write_delay = 4500; - read = "0 1 0 1 1 0 0 0 0 0 0 0 1 0 0 0", - "x x x x x x x x o o o o o o o o"; - - write = "1 0 1 0 1 1 0 0 1 0 1 0 1 0 0 0", - "x x x x x x x x i i i i i i i i"; - ; - - memory "efuse" - size = 1; - min_write_delay = 4500; - max_write_delay = 4500; - read = "0 1 0 1 0 0 0 0 0 0 0 0 1 0 0 0", - "x x x x x x x x o o o o o o o o"; - - write = "1 0 1 0 1 1 0 0 1 0 1 0 0 1 0 0", - "x x x x x x x x x x x x x i i i"; - ; - - memory "lock" - size = 1; - min_write_delay = 4500; - max_write_delay = 4500; - read = "0 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0", - "x x x x x x x x x x o o o o o o"; - - write = "1 0 1 0 1 1 0 0 1 1 1 x x x x x", - "x x x x x x x x 1 1 i i i i i i"; - ; - - memory "calibration" - size = 1; - read = "0 0 1 1 1 0 0 0 0 0 0 x x x x x", - "0 0 0 0 0 0 0 0 o o o o o o o o"; - ; - - memory "signature" - size = 3; - read = "0 0 1 1 0 0 0 0 0 0 0 x x x x x", - "x x x x x x a1 a0 o o o o o o o o"; - ; -; - -part parent "m328" - id = "m328p"; - desc = "ATmega328P"; - signature = 0x1e 0x95 0x0F; - - ocdrev = 1; -; - -part parent "m328" - id = "m328pb"; - desc = "ATmega328PB"; - signature = 0x1e 0x95 0x16; - - ocdrev = 1; -; - -#------------------------------------------------------------ -# ATmega32m1 -#------------------------------------------------------------ - -part parent "m328" - id = "m32m1"; - desc = "ATmega32M1"; - # stk500_devcode = 0x; - # avr910_devcode = 0x; - signature = 0x1e 0x95 0x84; - bs2 = 0xe2; - - memory "efuse" - read = "0 1 0 1 0 0 0 0 0 0 0 0 1 0 0 0", - "x x x x x x x x o o o o o o o o"; - write = "1 0 1 0 1 1 0 0 1 0 1 0 0 1 0 0", - "x x x x x x x x x x i i i i i i"; - ; -; - -#------------------------------------------------------------ -# ATmega64m1 -#------------------------------------------------------------ - -part parent "m328" - id = "m64m1"; - desc = "ATmega64M1"; - # stk500_devcode = 0x; - # avr910_devcode = 0x; - signature = 0x1e 0x96 0x84; - bs2 = 0xe2; - - memory "efuse" - size = 1; - min_write_delay = 4500; - max_write_delay = 4500; - read = "0 1 0 1 0 0 0 0 0 0 0 0 1 0 0 0", - "x x x x x x x x o o o o o o o o"; - - write = "1 0 1 0 1 1 0 0 1 0 1 0 0 1 0 0", - "x x x x x x x x x x i i i i i i"; - ; -; - -#------------------------------------------------------------ -# ATtiny2313 -#------------------------------------------------------------ - -part - id = "t2313"; - desc = "ATtiny2313"; - has_debugwire = yes; - flash_instr = 0xB2, 0x0F, 0x1F; - eeprom_instr = 0xBB, 0xFE, 0xBB, 0xEE, 0xBB, 0xCC, 0xB2, 0x0D, - 0xBA, 0x0F, 0xB2, 0x0F, 0xBA, 0x0D, 0xBB, 0xBC, - 0x99, 0xE1, 0xBB, 0xAC; - stk500_devcode = 0x23; -## Use the ATtiny26 devcode: - avr910_devcode = 0x5e; - signature = 0x1e 0x91 0x0a; - pagel = 0xD4; - bs2 = 0xD6; - reset = io; - chip_erase_delay = 9000; - - pgm_enable = "1 0 1 0 1 1 0 0 0 1 0 1 0 0 1 1", - "x x x x x x x x x x x x x x x x"; - - chip_erase = "1 0 1 0 1 1 0 0 1 0 0 x x x x x", - "x x x x x x x x x x x x x x x x"; - - timeout = 200; - stabdelay = 100; - cmdexedelay = 25; - synchloops = 32; - bytedelay = 0; - pollindex = 3; - pollvalue = 0x53; - predelay = 1; - postdelay = 1; - pollmethod = 1; - - pp_controlstack = - 0x0E, 0x1E, 0x0E, 0x1E, 0x2E, 0x3E, 0x2E, 0x3E, - 0x4E, 0x5E, 0x4E, 0x5E, 0x6E, 0x7E, 0x6E, 0x7E, - 0x26, 0x36, 0x66, 0x76, 0x2A, 0x3A, 0x6A, 0x7A, - 0x2E, 0xFD, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00; - hventerstabdelay = 100; - progmodedelay = 0; - latchcycles = 5; - togglevtg = 1; - poweroffdelay = 15; - resetdelayms = 1; - resetdelayus = 0; - hvleavestabdelay = 15; - chiperasepulsewidth = 0; - chiperasepolltimeout = 10; - programfusepulsewidth = 0; - programfusepolltimeout = 5; - programlockpulsewidth = 0; - programlockpolltimeout = 5; - - ocdrev = 0; - - memory "eeprom" - size = 128; - paged = no; - page_size = 4; - min_write_delay = 4000; - max_write_delay = 4500; - readback_p1 = 0xff; - readback_p2 = 0xff; - read = "1 0 1 0 0 0 0 0 0 0 0 x x x x x", - "x a6 a5 a4 a3 a2 a1 a0 o o o o o o o o"; - - write = "1 1 0 0 0 0 0 0 0 0 0 x x x x x", - "x a6 a5 a4 a3 a2 a1 a0 i i i i i i i i"; - - loadpage_lo = " 1 1 0 0 0 0 0 1", - " 0 0 0 0 0 0 0 0", - " 0 0 0 0 0 0 a1 a0", - " i i i i i i i i"; - - writepage = " 1 1 0 0 0 0 1 0", - " 0 0 x x x x x x", - " x a6 a5 a4 a3 a2 0 0", - " x x x x x x x x"; - - mode = 0x41; - delay = 6; - blocksize = 4; - readsize = 256; - ; - memory "flash" - paged = yes; - size = 2048; - page_size = 32; - num_pages = 64; - min_write_delay = 4500; - max_write_delay = 4500; - readback_p1 = 0xff; - readback_p2 = 0xff; - read_lo = " 0 0 1 0 0 0 0 0", - " 0 0 0 0 0 0 a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " o o o o o o o o"; - - read_hi = " 0 0 1 0 1 0 0 0", - " 0 0 0 0 0 0 a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " o o o o o o o o"; - -# The information in the data sheet of April/2004 is wrong, this works: - loadpage_lo = " 0 1 0 0 0 0 0 0", - " 0 0 0 x x x x x", - " x x x x a3 a2 a1 a0", - " i i i i i i i i"; - -# The information in the data sheet of April/2004 is wrong, this works: - loadpage_hi = " 0 1 0 0 1 0 0 0", - " 0 0 0 x x x x x", - " x x x x a3 a2 a1 a0", - " i i i i i i i i"; - -# The information in the data sheet of April/2004 is wrong, this works: - writepage = " 0 1 0 0 1 1 0 0", - " 0 0 0 0 0 0 a9 a8", - " a7 a6 a5 a4 x x x x", - " x x x x x x x x"; - - mode = 0x41; - delay = 6; - blocksize = 32; - readsize = 256; - ; -# ATtiny2313 has Signature Bytes: 0x1E 0x91 0x0A. - memory "signature" - size = 3; - read = "0 0 1 1 0 0 0 0 0 0 0 x x x x x", - "x x x x x x a1 a0 o o o o o o o o"; - ; - memory "lock" - size = 1; - write = "1 0 1 0 1 1 0 0 1 1 1 x x x x x", - "x x x x x x x x 1 1 i i i i i i"; - read = "0 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0", - "x x x x x x x x x x o o o o o o"; - min_write_delay = 9000; - max_write_delay = 9000; - ; - - memory "lfuse" - size = 1; - write = "1 0 1 0 1 1 0 0 1 0 1 0 0 0 0 0", - "x x x x x x x x i i i i i i i i"; - - read = "0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0", - "x x x x x x x x o o o o o o o o"; - min_write_delay = 9000; - max_write_delay = 9000; - ; - - memory "hfuse" - size = 1; - write = "1 0 1 0 1 1 0 0 1 0 1 0 1 0 0 0", - "x x x x x x x x i i i i i i i i"; - - read = "0 1 0 1 1 0 0 0 0 0 0 0 1 0 0 0", - "x x x x x x x x o o o o o o o o"; - min_write_delay = 9000; - max_write_delay = 9000; - ; - - memory "efuse" - size = 1; - write = "1 0 1 0 1 1 0 0 1 0 1 0 0 1 0 0", - "x x x x x x x x x x x x x x x i"; - - read = "0 1 0 1 0 0 0 0 0 0 0 0 1 0 0 0", - "x x x x x x x x o o o o o o o o"; - min_write_delay = 9000; - max_write_delay = 9000; - ; -# The Tiny2313 has calibration data for both 4 MHz and 8 MHz. -# The information in the data sheet of April/2004 is wrong, this works: - - memory "calibration" - size = 2; - read = "0 0 1 1 1 0 0 0 0 0 0 x x x x x", - "0 0 0 0 0 0 0 a0 o o o o o o o o"; - ; - ; - -#------------------------------------------------------------ -# ATtiny4313 -#------------------------------------------------------------ - -part - id = "t4313"; - desc = "ATtiny4313"; - has_debugwire = yes; - flash_instr = 0xB2, 0x0F, 0x1F; - eeprom_instr = 0xBB, 0xFE, 0xBB, 0xEE, 0xBB, 0xCC, 0xB2, 0x0D, - 0xBA, 0x0F, 0xB2, 0x0F, 0xBA, 0x0D, 0xBB, 0xBC, - 0x99, 0xE1, 0xBB, 0xAC; - stk500_devcode = 0x23; -## Use the ATtiny26 devcode: - avr910_devcode = 0x5e; - signature = 0x1e 0x92 0x0d; - pagel = 0xD4; - bs2 = 0xD6; - reset = io; - chip_erase_delay = 9000; - - pgm_enable = "1 0 1 0 1 1 0 0 0 1 0 1 0 0 1 1", - "x x x x x x x x x x x x x x x x"; - - chip_erase = "1 0 1 0 1 1 0 0 1 0 0 x x x x x", - "x x x x x x x x x x x x x x x x"; - - timeout = 200; - stabdelay = 100; - cmdexedelay = 25; - synchloops = 32; - bytedelay = 0; - pollindex = 3; - pollvalue = 0x53; - predelay = 1; - postdelay = 1; - pollmethod = 1; - - pp_controlstack = - 0x0E, 0x1E, 0x0E, 0x1E, 0x2E, 0x3E, 0x2E, 0x3E, - 0x4E, 0x5E, 0x4E, 0x5E, 0x6E, 0x7E, 0x6E, 0x7E, - 0x26, 0x36, 0x66, 0x76, 0x2A, 0x3A, 0x6A, 0x7A, - 0x2E, 0xFD, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00; - hventerstabdelay = 100; - progmodedelay = 0; - latchcycles = 5; - togglevtg = 1; - poweroffdelay = 15; - resetdelayms = 1; - resetdelayus = 0; - hvleavestabdelay = 15; - chiperasepulsewidth = 0; - chiperasepolltimeout = 10; - programfusepulsewidth = 0; - programfusepolltimeout = 5; - programlockpulsewidth = 0; - programlockpolltimeout = 5; - - ocdrev = 0; - - memory "eeprom" - size = 256; - paged = no; - page_size = 4; - min_write_delay = 4000; - max_write_delay = 4500; - readback_p1 = 0xff; - readback_p2 = 0xff; - read = "1 0 1 0 0 0 0 0 0 0 0 x x x x x", - "a7 a6 a5 a4 a3 a2 a1 a0 o o o o o o o o"; - - write = "1 1 0 0 0 0 0 0 0 0 0 x x x x x", - "a7 a6 a5 a4 a3 a2 a1 a0 i i i i i i i i"; - - loadpage_lo = " 1 1 0 0 0 0 0 1", - " 0 0 0 0 0 0 0 0", - " 0 0 0 0 0 0 a1 a0", - " i i i i i i i i"; - - writepage = " 1 1 0 0 0 0 1 0", - " 0 0 x x x x x x", - " a7 a6 a5 a4 a3 a2 0 0", - " x x x x x x x x"; - - mode = 0x41; - delay = 6; - blocksize = 4; - readsize = 256; - ; - memory "flash" - paged = yes; - size = 4096; - page_size = 64; - num_pages = 64; - min_write_delay = 4500; - max_write_delay = 4500; - readback_p1 = 0xff; - readback_p2 = 0xff; - read_lo = " 0 0 1 0 0 0 0 0", - " 0 0 0 0 0 a10 a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " o o o o o o o o"; - - read_hi = " 0 0 1 0 1 0 0 0", - " 0 0 0 0 0 a10 a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " o o o o o o o o"; - - loadpage_lo = " 0 1 0 0 0 0 0 0", - " 0 0 0 x x x x x", - " x x x a4 a3 a2 a1 a0", - " i i i i i i i i"; - - loadpage_hi = " 0 1 0 0 1 0 0 0", - " 0 0 0 x x x x x", - " x x x a4 a3 a2 a1 a0", - " i i i i i i i i"; - - writepage = " 0 1 0 0 1 1 0 0", - " 0 0 0 0 0 a10 a9 a8", - " a7 a6 a5 x x x x x", - " x x x x x x x x"; - - mode = 0x41; - delay = 6; - blocksize = 32; - readsize = 256; - ; -# ATtiny4313 has Signature Bytes: 0x1E 0x92 0x0D. - memory "signature" - size = 3; - read = "0 0 1 1 0 0 0 0 0 0 0 x x x x x", - "x x x x x x a1 a0 o o o o o o o o"; - ; - memory "lock" - size = 1; - write = "1 0 1 0 1 1 0 0 1 1 1 x x x x x", - "x x x x x x x x 1 1 i i i i i i"; - read = "0 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0", - "x x x x x x x x x x o o o o o o"; - min_write_delay = 9000; - max_write_delay = 9000; - ; - - memory "lfuse" - size = 1; - write = "1 0 1 0 1 1 0 0 1 0 1 0 0 0 0 0", - "x x x x x x x x i i i i i i i i"; - - read = "0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0", - "x x x x x x x x o o o o o o o o"; - min_write_delay = 9000; - max_write_delay = 9000; - ; - - memory "hfuse" - size = 1; - write = "1 0 1 0 1 1 0 0 1 0 1 0 1 0 0 0", - "x x x x x x x x i i i i i i i i"; - - read = "0 1 0 1 1 0 0 0 0 0 0 0 1 0 0 0", - "x x x x x x x x o o o o o o o o"; - min_write_delay = 9000; - max_write_delay = 9000; - ; - - memory "efuse" - size = 1; - write = "1 0 1 0 1 1 0 0 1 0 1 0 0 1 0 0", - "x x x x x x x x x x x x x x x i"; - - read = "0 1 0 1 0 0 0 0 0 0 0 0 1 0 0 0", - "x x x x x x x x o o o o o o o o"; - min_write_delay = 9000; - max_write_delay = 9000; - ; - - memory "calibration" - size = 2; - read = "0 0 1 1 1 0 0 0 0 0 0 x x x x x", - "0 0 0 0 0 0 0 a0 o o o o o o o o"; - ; - ; - -#------------------------------------------------------------ -# AT90PWM2 -#------------------------------------------------------------ - -part - id = "pwm2"; - desc = "AT90PWM2"; - has_debugwire = yes; - flash_instr = 0xB6, 0x01, 0x11; - eeprom_instr = 0xBD, 0xF2, 0xBD, 0xE1, 0xBB, 0xCF, 0xB4, 0x00, - 0xBE, 0x01, 0xB6, 0x01, 0xBC, 0x00, 0xBB, 0xBF, - 0x99, 0xF9, 0xBB, 0xAF; - stk500_devcode = 0x65; -## avr910_devcode = ?; - signature = 0x1e 0x93 0x81; - pagel = 0xD8; - bs2 = 0xE2; - reset = io; - chip_erase_delay = 9000; - - pgm_enable = "1 0 1 0 1 1 0 0 0 1 0 1 0 0 1 1", - "x x x x x x x x x x x x x x x x"; - - chip_erase = "1 0 1 0 1 1 0 0 1 0 0 x x x x x", - "x x x x x x x x x x x x x x x x"; - - timeout = 200; - stabdelay = 100; - cmdexedelay = 25; - synchloops = 32; - bytedelay = 0; - pollindex = 3; - pollvalue = 0x53; - predelay = 1; - postdelay = 1; - pollmethod = 1; - - pp_controlstack = - 0x0E, 0x1E, 0x0F, 0x1F, 0x2E, 0x3E, 0x2F, 0x3F, - 0x4E, 0x5E, 0x4F, 0x5F, 0x6E, 0x7E, 0x6F, 0x7F, - 0x66, 0x76, 0x67, 0x77, 0x6A, 0x7A, 0x6B, 0x7B, - 0xBE, 0xFD, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00; - hventerstabdelay = 100; - progmodedelay = 0; - latchcycles = 5; - togglevtg = 1; - poweroffdelay = 15; - resetdelayms = 1; - resetdelayus = 0; - hvleavestabdelay = 15; - chiperasepulsewidth = 0; - chiperasepolltimeout = 10; - programfusepulsewidth = 0; - programfusepolltimeout = 5; - programlockpulsewidth = 0; - programlockpolltimeout = 5; - - memory "eeprom" - size = 512; - paged = no; - page_size = 4; - min_write_delay = 4000; - max_write_delay = 4500; - readback_p1 = 0xff; - readback_p2 = 0xff; - read = "1 0 1 0 0 0 0 0 0 0 0 x x x x a8", - "a7 a6 a5 a4 a3 a2 a1 a0 o o o o o o o o"; - - write = "1 1 0 0 0 0 0 0 0 0 0 x x x x a8", - "a7 a6 a5 a4 a3 a2 a1 a0 i i i i i i i i"; - - loadpage_lo = " 1 1 0 0 0 0 0 1", - " 0 0 0 0 0 0 0 0", - " 0 0 0 0 0 0 a1 a0", - " i i i i i i i i"; - - writepage = " 1 1 0 0 0 0 1 0", - " 0 0 x x x x x x", - " a7 a6 a5 a4 a3 a2 0 0", - " x x x x x x x x"; - - mode = 0x41; - delay = 6; - blocksize = 4; - readsize = 256; - ; - memory "flash" - paged = yes; - size = 8192; - page_size = 64; - num_pages = 128; - min_write_delay = 4500; - max_write_delay = 4500; - readback_p1 = 0xff; - readback_p2 = 0xff; - read_lo = " 0 0 1 0 0 0 0 0", - " 0 0 0 0 a11 a10 a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " o o o o o o o o"; - - read_hi = " 0 0 1 0 1 0 0 0", - " 0 0 0 0 a11 a10 a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " o o o o o o o o"; - - loadpage_lo = " 0 1 0 0 0 0 0 0", - " 0 0 0 x x x x x", - " x x x a4 a3 a2 a1 a0", - " i i i i i i i i"; - - loadpage_hi = " 0 1 0 0 1 0 0 0", - " 0 0 0 x x x x x", - " x x x a4 a3 a2 a1 a0", - " i i i i i i i i"; - - writepage = " 0 1 0 0 1 1 0 0", - " 0 0 0 0 a11 a10 a9 a8", - " a7 a6 a5 x x x x x", - " x x x x x x x x"; - - mode = 0x41; - delay = 6; - blocksize = 64; - readsize = 256; - ; -# AT90PWM2 has Signature Bytes: 0x1E 0x93 0x81. - memory "signature" - size = 3; - read = "0 0 1 1 0 0 0 0 0 0 x x x x x x", - "x x x x x x a1 a0 o o o o o o o o"; - ; - memory "lock" - size = 1; - write = "1 0 1 0 1 1 0 0 1 1 1 x x x x x", - "x x x x x x x x 1 1 i i i i i i"; - - read = "0 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0", - "x x x x x x x x x x o o o o o o"; - min_write_delay = 9000; - max_write_delay = 9000; - ; - - memory "lfuse" - size = 1; - write = "1 0 1 0 1 1 0 0 1 0 1 0 0 0 0 0", - "x x x x x x x x i i i i i i i i"; - - read = "0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0", - "x x x x x x x x o o o o o o o o"; - min_write_delay = 9000; - max_write_delay = 9000; - ; - - memory "hfuse" - size = 1; - write = "1 0 1 0 1 1 0 0 1 0 1 0 1 0 0 0", - "x x x x x x x x i i i i i i i i"; - - read = "0 1 0 1 1 0 0 0 0 0 0 0 1 0 0 0", - "x x x x x x x x o o o o o o o o"; - min_write_delay = 9000; - max_write_delay = 9000; - ; - - memory "efuse" - size = 1; - write = "1 0 1 0 1 1 0 0 1 0 1 0 0 1 0 0", - "x x x x x x x x i i i i i i i i"; - - read = "0 1 0 1 0 0 0 0 0 0 0 0 1 0 0 0", - "x x x x x x x x o o o o o o o o"; - min_write_delay = 9000; - max_write_delay = 9000; - ; - - memory "calibration" - size = 1; - read = "0 0 1 1 1 0 0 0 0 0 0 x x x x x", - "0 0 0 0 0 0 0 0 o o o o o o o o"; - ; - ; - -#------------------------------------------------------------ -# AT90PWM3 -#------------------------------------------------------------ - -# Completely identical to AT90PWM2 (including the signature!) - -part parent "pwm2" - id = "pwm3"; - desc = "AT90PWM3"; - ; - -#------------------------------------------------------------ -# AT90PWM2B -#------------------------------------------------------------ -# Same as AT90PWM2 but different signature. - -part parent "pwm2" - id = "pwm2b"; - desc = "AT90PWM2B"; - signature = 0x1e 0x93 0x83; - - ocdrev = 1; - ; - -#------------------------------------------------------------ -# AT90PWM3B -#------------------------------------------------------------ - -# Completely identical to AT90PWM2B (including the signature!) - -part parent "pwm2b" - id = "pwm3b"; - desc = "AT90PWM3B"; - - ocdrev = 1; - ; - -#------------------------------------------------------------ -# AT90PWM316 -#------------------------------------------------------------ - -# Similar to AT90PWM3B, but with 16 kiB flash, 512 B EEPROM, and 1024 B SRAM. - -part parent "pwm3b" - id = "pwm316"; - desc = "AT90PWM316"; - signature = 0x1e 0x94 0x83; - - ocdrev = 1; - - memory "flash" - paged = yes; - size = 16384; - page_size = 128; - num_pages = 128; - min_write_delay = 4500; - max_write_delay = 4500; - readback_p1 = 0xff; - readback_p2 = 0xff; - read_lo = " 0 0 1 0 0 0 0 0", - " 0 0 a13 a12 a11 a10 a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " o o o o o o o o"; - - read_hi = " 0 0 1 0 1 0 0 0", - " 0 0 a13 a12 a11 a10 a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " o o o o o o o o"; - - loadpage_lo = " 0 1 0 0 0 0 0 0", - " 0 0 x x x x x x", - " x x a5 a4 a3 a2 a1 a0", - " i i i i i i i i"; - - loadpage_hi = " 0 1 0 0 1 0 0 0", - " 0 0 x x x x x x", - " x x a5 a4 a3 a2 a1 a0", - " i i i i i i i i"; - - writepage = " 0 1 0 0 1 1 0 0", - " 0 0 a13 a12 a11 a10 a9 a8", - " a7 a6 x x x x x x", - " x x x x x x x x"; - - mode = 0x21; - delay = 6; - blocksize = 128; - readsize = 256; - ; - ; - -#------------------------------------------------------------ -# AT90PWM216 -#------------------------------------------------------------ -# Completely identical to AT90PWM316 (including the signature!) - -part parent "pwm316" - id = "pwm216"; - desc = "AT90PWM216"; - ; - -#------------------------------------------------------------ -# ATtiny25 -#------------------------------------------------------------ - -part - id = "t25"; - desc = "ATtiny25"; - has_debugwire = yes; - flash_instr = 0xB4, 0x02, 0x12; - eeprom_instr = 0xBB, 0xFF, 0xBB, 0xEE, 0xBB, 0xCC, 0xB2, 0x0D, - 0xBC, 0x02, 0xB4, 0x02, 0xBA, 0x0D, 0xBB, 0xBC, - 0x99, 0xE1, 0xBB, 0xAC; -## no STK500 devcode in XML file, use the ATtiny45 one - stk500_devcode = 0x14; -## avr910_devcode = ?; -## Try the AT90S2313 devcode: - avr910_devcode = 0x20; - signature = 0x1e 0x91 0x08; - reset = io; - chip_erase_delay = 4500; - - pgm_enable = "1 0 1 0 1 1 0 0 0 1 0 1 0 0 1 1", - "x x x x x x x x x x x x x x x x"; - - chip_erase = "1 0 1 0 1 1 0 0 1 0 0 x x x x x", - "x x x x x x x x x x x x x x x x"; - - timeout = 200; - stabdelay = 100; - cmdexedelay = 25; - synchloops = 32; - bytedelay = 0; - pollindex = 3; - pollvalue = 0x53; - predelay = 1; - postdelay = 1; - pollmethod = 1; - - hvsp_controlstack = - 0x4C, 0x0C, 0x1C, 0x2C, 0x3C, 0x64, 0x74, 0x66, - 0x68, 0x78, 0x68, 0x68, 0x7A, 0x6A, 0x68, 0x78, - 0x78, 0x7D, 0x6D, 0x0C, 0x80, 0x40, 0x20, 0x10, - 0x11, 0x08, 0x04, 0x02, 0x03, 0x08, 0x04, 0x00; - hventerstabdelay = 100; - hvspcmdexedelay = 0; - synchcycles = 6; - latchcycles = 1; - togglevtg = 1; - poweroffdelay = 25; - resetdelayms = 1; - resetdelayus = 0; - hvleavestabdelay = 100; - resetdelay = 25; - chiperasepolltimeout = 40; - chiperasetime = 0; - programfusepolltimeout = 25; - programlockpolltimeout = 25; - - ocdrev = 1; - - memory "eeprom" - size = 128; - paged = no; - page_size = 4; - min_write_delay = 4000; - max_write_delay = 4500; - readback_p1 = 0xff; - readback_p2 = 0xff; - read = "1 0 1 0 0 0 0 0 0 0 0 x x x x x", - "x a6 a5 a4 a3 a2 a1 a0 o o o o o o o o"; - - write = "1 1 0 0 0 0 0 0 0 0 0 x x x x x", - "x a6 a5 a4 a3 a2 a1 a0 i i i i i i i i"; - - loadpage_lo = " 1 1 0 0 0 0 0 1", - " 0 0 0 0 0 0 0 0", - " 0 0 0 0 0 0 a1 a0", - " i i i i i i i i"; - - writepage = " 1 1 0 0 0 0 1 0", - " 0 0 x x x x x x", - " x a6 a5 a4 a3 a2 0 0", - " x x x x x x x x"; - - mode = 0x41; - delay = 6; - blocksize = 4; - readsize = 256; - ; - memory "flash" - paged = yes; - size = 2048; - page_size = 32; - num_pages = 64; - min_write_delay = 4500; - max_write_delay = 4500; - readback_p1 = 0xff; - readback_p2 = 0xff; - read_lo = " 0 0 1 0 0 0 0 0", - " 0 0 0 0 0 0 a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " o o o o o o o o"; - - read_hi = " 0 0 1 0 1 0 0 0", - " 0 0 0 0 0 0 a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " o o o o o o o o"; - - loadpage_lo = " 0 1 0 0 0 0 0 0", - " 0 0 0 x x x x x", - " x x x x a3 a2 a1 a0", - " i i i i i i i i"; - - loadpage_hi = " 0 1 0 0 1 0 0 0", - " 0 0 0 x x x x x", - " x x x x a3 a2 a1 a0", - " i i i i i i i i"; - - writepage = " 0 1 0 0 1 1 0 0", - " 0 0 0 0 0 0 a9 a8", - " a7 a6 a5 a4 x x x x", - " x x x x x x x x"; - - mode = 0x41; - delay = 6; - blocksize = 32; - readsize = 256; - ; -# ATtiny25 has Signature Bytes: 0x1E 0x91 0x08. - memory "signature" - size = 3; - read = "0 0 1 1 0 0 0 0 0 0 0 x x x x x", - "x x x x x x a1 a0 o o o o o o o o"; - ; - memory "lock" - size = 1; - write = "1 0 1 0 1 1 0 0 1 1 1 x x x x x", - "x x x x x x x x 1 1 i i i i i i"; - read = "0 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0", - "0 0 0 0 0 0 0 0 o o o o o o o o"; - min_write_delay = 9000; - max_write_delay = 9000; - ; - - memory "lfuse" - size = 1; - write = "1 0 1 0 1 1 0 0 1 0 1 0 0 0 0 0", - "x x x x x x x x i i i i i i i i"; - - read = "0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0", - "x x x x x x x x o o o o o o o o"; - min_write_delay = 9000; - max_write_delay = 9000; - ; - - memory "hfuse" - size = 1; - write = "1 0 1 0 1 1 0 0 1 0 1 0 1 0 0 0", - "x x x x x x x x i i i i i i i i"; - - read = "0 1 0 1 1 0 0 0 0 0 0 0 1 0 0 0", - "x x x x x x x x o o o o o o o o"; - min_write_delay = 9000; - max_write_delay = 9000; - ; - - memory "efuse" - size = 1; - write = "1 0 1 0 1 1 0 0 1 0 1 0 0 1 0 0", - "x x x x x x x x x x x x x x x i"; - - read = "0 1 0 1 0 0 0 0 0 0 0 0 1 0 0 0", - "x x x x x x x x o o o o o o o o"; - min_write_delay = 9000; - max_write_delay = 9000; - ; - - memory "calibration" - size = 1; - read = "0 0 1 1 1 0 0 0 0 0 0 x x x x x", - "0 0 0 0 0 0 0 a0 o o o o o o o o"; - ; - ; - -#------------------------------------------------------------ -# ATtiny45 -#------------------------------------------------------------ - -part - id = "t45"; - desc = "ATtiny45"; - has_debugwire = yes; - flash_instr = 0xB4, 0x02, 0x12; - eeprom_instr = 0xBB, 0xFF, 0xBB, 0xEE, 0xBB, 0xCC, 0xB2, 0x0D, - 0xBC, 0x02, 0xB4, 0x02, 0xBA, 0x0D, 0xBB, 0xBC, - 0x99, 0xE1, 0xBB, 0xAC; - stk500_devcode = 0x14; -## avr910_devcode = ?; -## Try the AT90S2313 devcode: - avr910_devcode = 0x20; - signature = 0x1e 0x92 0x06; - reset = io; - chip_erase_delay = 4500; - - pgm_enable = "1 0 1 0 1 1 0 0 0 1 0 1 0 0 1 1", - "x x x x x x x x x x x x x x x x"; - - chip_erase = "1 0 1 0 1 1 0 0 1 0 0 x x x x x", - "x x x x x x x x x x x x x x x x"; - - timeout = 200; - stabdelay = 100; - cmdexedelay = 25; - synchloops = 32; - bytedelay = 0; - pollindex = 3; - pollvalue = 0x53; - predelay = 1; - postdelay = 1; - pollmethod = 1; - - hvsp_controlstack = - 0x4C, 0x0C, 0x1C, 0x2C, 0x3C, 0x64, 0x74, 0x66, - 0x68, 0x78, 0x68, 0x68, 0x7A, 0x6A, 0x68, 0x78, - 0x78, 0x7D, 0x6D, 0x0C, 0x80, 0x40, 0x20, 0x10, - 0x11, 0x08, 0x04, 0x02, 0x03, 0x08, 0x04, 0x00; - hventerstabdelay = 100; - progmodedelay = 0; - hvspcmdexedelay = 0; - synchcycles = 6; - latchcycles = 1; - togglevtg = 1; - poweroffdelay = 25; - resetdelayms = 1; - resetdelayus = 0; - hvleavestabdelay = 100; - resetdelay = 25; - chiperasepolltimeout = 40; - chiperasetime = 0; - programfusepolltimeout = 25; - programlockpolltimeout = 25; - - ocdrev = 1; - - memory "eeprom" - size = 256; - page_size = 4; - min_write_delay = 4000; - max_write_delay = 4500; - readback_p1 = 0xff; - readback_p2 = 0xff; - read = "1 0 1 0 0 0 0 0 0 0 0 x x x x x", - "a7 a6 a5 a4 a3 a2 a1 a0 o o o o o o o o"; - - write = "1 1 0 0 0 0 0 0 0 0 0 x x x x x", - "a7 a6 a5 a4 a3 a2 a1 a0 i i i i i i i i"; - - loadpage_lo = " 1 1 0 0 0 0 0 1", - " 0 0 0 0 0 0 0 0", - " 0 0 0 0 0 0 a1 a0", - " i i i i i i i i"; - - writepage = " 1 1 0 0 0 0 1 0", - " 0 0 x x x x x x", - " a7 a6 a5 a4 a3 a2 0 0", - " x x x x x x x x"; - - mode = 0x41; - delay = 6; - blocksize = 4; - readsize = 256; - ; - memory "flash" - paged = yes; - size = 4096; - page_size = 64; - num_pages = 64; - min_write_delay = 4500; - max_write_delay = 4500; - readback_p1 = 0xff; - readback_p2 = 0xff; - read_lo = " 0 0 1 0 0 0 0 0", - " 0 0 0 0 0 a10 a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " o o o o o o o o"; - - read_hi = " 0 0 1 0 1 0 0 0", - " 0 0 0 0 0 a10 a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " o o o o o o o o"; - - loadpage_lo = " 0 1 0 0 0 0 0 0", - " 0 0 0 x x x x x", - " x x x a4 a3 a2 a1 a0", - " i i i i i i i i"; - - loadpage_hi = " 0 1 0 0 1 0 0 0", - " 0 0 0 x x x x x", - " x x x a4 a3 a2 a1 a0", - " i i i i i i i i"; - - writepage = " 0 1 0 0 1 1 0 0", - " 0 0 0 0 0 a10 a9 a8", - " a7 a6 a5 x x x x x", - " x x x x x x x x"; - - mode = 0x41; - delay = 6; - blocksize = 32; - readsize = 256; - ; -# ATtiny45 has Signature Bytes: 0x1E 0x92 0x08. (Data sheet 2586C-AVR-06/05 (doc2586.pdf) indicates otherwise!) - memory "signature" - size = 3; - read = "0 0 1 1 0 0 0 0 0 0 0 x x x x x", - "x x x x x x a1 a0 o o o o o o o o"; - ; - memory "lock" - size = 1; - write = "1 0 1 0 1 1 0 0 1 1 1 x x x x x", - "x x x x x x x x 1 1 i i i i i i"; - read = "0 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0", - "0 0 0 0 0 0 0 0 o o o o o o o o"; - min_write_delay = 9000; - max_write_delay = 9000; - ; - - memory "lfuse" - size = 1; - write = "1 0 1 0 1 1 0 0 1 0 1 0 0 0 0 0", - "x x x x x x x x i i i i i i i i"; - - read = "0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0", - "x x x x x x x x o o o o o o o o"; - min_write_delay = 9000; - max_write_delay = 9000; - ; - - memory "hfuse" - size = 1; - write = "1 0 1 0 1 1 0 0 1 0 1 0 1 0 0 0", - "x x x x x x x x i i i i i i i i"; - - read = "0 1 0 1 1 0 0 0 0 0 0 0 1 0 0 0", - "x x x x x x x x o o o o o o o o"; - min_write_delay = 9000; - max_write_delay = 9000; - ; - - memory "efuse" - size = 1; - write = "1 0 1 0 1 1 0 0 1 0 1 0 0 1 0 0", - "x x x x x x x x x x x x x x x i"; - - read = "0 1 0 1 0 0 0 0 0 0 0 0 1 0 0 0", - "x x x x x x x x o o o o o o o o"; - min_write_delay = 9000; - max_write_delay = 9000; - ; - - memory "calibration" - size = 1; - read = "0 0 1 1 1 0 0 0 0 0 0 x x x x x", - "0 0 0 0 0 0 0 a0 o o o o o o o o"; - ; - ; - -#------------------------------------------------------------ -# ATtiny85 -#------------------------------------------------------------ - -part - id = "t85"; - desc = "ATtiny85"; - has_debugwire = yes; - flash_instr = 0xB4, 0x02, 0x12; - eeprom_instr = 0xBB, 0xFF, 0xBB, 0xEE, 0xBB, 0xCC, 0xB2, 0x0D, - 0xBC, 0x02, 0xB4, 0x02, 0xBA, 0x0D, 0xBB, 0xBC, - 0x99, 0xE1, 0xBB, 0xAC; -## no STK500 devcode in XML file, use the ATtiny45 one - stk500_devcode = 0x14; -## avr910_devcode = ?; -## Try the AT90S2313 devcode: - avr910_devcode = 0x20; - signature = 0x1e 0x93 0x0b; - reset = io; - chip_erase_delay = 400000; - - pgm_enable = "1 0 1 0 1 1 0 0 0 1 0 1 0 0 1 1", - "x x x x x x x x x x x x x x x x"; - - chip_erase = "1 0 1 0 1 1 0 0 1 0 0 x x x x x", - "x x x x x x x x x x x x x x x x"; - - timeout = 200; - stabdelay = 100; - cmdexedelay = 25; - synchloops = 32; - bytedelay = 0; - pollindex = 3; - pollvalue = 0x53; - predelay = 1; - postdelay = 1; - pollmethod = 1; - - hvsp_controlstack = - 0x4C, 0x0C, 0x1C, 0x2C, 0x3C, 0x64, 0x74, 0x66, - 0x68, 0x78, 0x68, 0x68, 0x7A, 0x6A, 0x68, 0x78, - 0x78, 0x7D, 0x6D, 0x0C, 0x80, 0x40, 0x20, 0x10, - 0x11, 0x08, 0x04, 0x02, 0x03, 0x08, 0x04, 0x00; - hventerstabdelay = 100; - hvspcmdexedelay = 0; - synchcycles = 6; - latchcycles = 1; - togglevtg = 1; - poweroffdelay = 25; - resetdelayms = 1; - resetdelayus = 0; - hvleavestabdelay = 100; - resetdelay = 25; - chiperasepolltimeout = 40; - chiperasetime = 0; - programfusepolltimeout = 25; - programlockpolltimeout = 25; - - ocdrev = 1; - - memory "eeprom" - size = 512; - paged = no; - page_size = 4; - min_write_delay = 4000; - max_write_delay = 4500; - readback_p1 = 0xff; - readback_p2 = 0xff; - read = "1 0 1 0 0 0 0 0 0 0 0 x x x x a8", - "a7 a6 a5 a4 a3 a2 a1 a0 o o o o o o o o"; - - write = "1 1 0 0 0 0 0 0 0 0 0 x x x x a8", - "a7 a6 a5 a4 a3 a2 a1 a0 i i i i i i i i"; - - loadpage_lo = " 1 1 0 0 0 0 0 1", - " 0 0 0 0 0 0 0 0", - " 0 0 0 0 0 0 a1 a0", - " i i i i i i i i"; - - writepage = " 1 1 0 0 0 0 1 0", - " 0 0 x x x x x a8", - " a7 a6 a5 a4 a3 a2 0 0", - " x x x x x x x x"; - - mode = 0x41; - delay = 12; - blocksize = 4; - readsize = 256; - ; - memory "flash" - paged = yes; - size = 8192; - page_size = 64; - num_pages = 128; - min_write_delay = 30000; - max_write_delay = 30000; - readback_p1 = 0xff; - readback_p2 = 0xff; - read_lo = " 0 0 1 0 0 0 0 0", - " 0 0 0 0 a11 a10 a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " o o o o o o o o"; - - read_hi = " 0 0 1 0 1 0 0 0", - " 0 0 0 0 a11 a10 a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " o o o o o o o o"; - - loadpage_lo = " 0 1 0 0 0 0 0 0", - " 0 0 0 x x x x x", - " x x x a4 a3 a2 a1 a0", - " i i i i i i i i"; - - loadpage_hi = " 0 1 0 0 1 0 0 0", - " 0 0 0 x x x x x", - " x x x a4 a3 a2 a1 a0", - " i i i i i i i i"; - - writepage = " 0 1 0 0 1 1 0 0", - " 0 0 0 0 a11 a10 a9 a8", - " a7 a6 a5 x x x x x", - " x x x x x x x x"; - - mode = 0x41; - delay = 6; - blocksize = 32; - readsize = 256; - ; -# ATtiny85 has Signature Bytes: 0x1E 0x93 0x08. - memory "signature" - size = 3; - read = "0 0 1 1 0 0 0 0 0 0 0 x x x x x", - "x x x x x x a1 a0 o o o o o o o o"; - ; - memory "lock" - size = 1; - write = "1 0 1 0 1 1 0 0 1 1 1 x x x x x", - "x x x x x x x x 1 1 i i i i i i"; - read = "0 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0", - "0 0 0 0 0 0 0 0 o o o o o o o o"; - min_write_delay = 9000; - max_write_delay = 9000; - ; - - memory "lfuse" - size = 1; - write = "1 0 1 0 1 1 0 0 1 0 1 0 0 0 0 0", - "x x x x x x x x i i i i i i i i"; - - read = "0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0", - "x x x x x x x x o o o o o o o o"; - min_write_delay = 9000; - max_write_delay = 9000; - ; - - memory "hfuse" - size = 1; - write = "1 0 1 0 1 1 0 0 1 0 1 0 1 0 0 0", - "x x x x x x x x i i i i i i i i"; - - read = "0 1 0 1 1 0 0 0 0 0 0 0 1 0 0 0", - "x x x x x x x x o o o o o o o o"; - min_write_delay = 9000; - max_write_delay = 9000; - ; - - memory "efuse" - size = 1; - write = "1 0 1 0 1 1 0 0 1 0 1 0 0 1 0 0", - "x x x x x x x x x x x x x x x i"; - - read = "0 1 0 1 0 0 0 0 0 0 0 0 1 0 0 0", - "x x x x x x x x o o o o o o o o"; - min_write_delay = 9000; - max_write_delay = 9000; - ; - - memory "calibration" - size = 1; - read = "0 0 1 1 1 0 0 0 0 0 0 x x x x x", - "0 0 0 0 0 0 0 a0 o o o o o o o o"; - ; - ; - -#------------------------------------------------------------ -# ATmega640 -#------------------------------------------------------------ -# Almost same as ATmega1280, except for different memory sizes - -part - id = "m640"; - desc = "ATmega640"; - signature = 0x1e 0x96 0x08; - has_jtag = yes; -# stk500_devcode = 0xB2; -# avr910_devcode = 0x43; - chip_erase_delay = 9000; - pagel = 0xD7; - bs2 = 0xA0; - reset = dedicated; - pgm_enable = "1 0 1 0 1 1 0 0 0 1 0 1 0 0 1 1", - "x x x x x x x x x x x x x x x x"; - - chip_erase = "1 0 1 0 1 1 0 0 1 0 0 0 0 0 0 0", - "x x x x x x x x x x x x x x x x"; - - timeout = 200; - stabdelay = 100; - cmdexedelay = 25; - synchloops = 32; - bytedelay = 0; - pollindex = 3; - pollvalue = 0x53; - predelay = 1; - postdelay = 1; - pollmethod = 1; - - pp_controlstack = - 0x0E, 0x1E, 0x0F, 0x1F, 0x2E, 0x3E, 0x2F, 0x3F, - 0x4E, 0x5E, 0x4F, 0x5F, 0x6E, 0x7E, 0x6F, 0x7F, - 0x66, 0x76, 0x67, 0x77, 0x6A, 0x7A, 0x6B, 0x7B, - 0xBE, 0xFD, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00; - hventerstabdelay = 100; - progmodedelay = 0; - latchcycles = 5; - togglevtg = 1; - poweroffdelay = 15; - resetdelayms = 1; - resetdelayus = 0; - hvleavestabdelay = 15; - chiperasepulsewidth = 0; - chiperasepolltimeout = 10; - programfusepulsewidth = 0; - programfusepolltimeout = 5; - programlockpulsewidth = 0; - programlockpolltimeout = 5; - - idr = 0x31; - spmcr = 0x57; - rampz = 0x3b; - allowfullpagebitstream = no; - - ocdrev = 3; - - memory "eeprom" - paged = no; /* leave this "no" */ - page_size = 8; /* for parallel programming */ - size = 4096; - min_write_delay = 9000; - max_write_delay = 9000; - readback_p1 = 0x00; - readback_p2 = 0x00; - read = " 1 0 1 0 0 0 0 0", - " x x x x a11 a10 a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " o o o o o o o o"; - - write = " 1 1 0 0 0 0 0 0", - " x x x x a11 a10 a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " i i i i i i i i"; - - loadpage_lo = " 1 1 0 0 0 0 0 1", - " 0 0 0 0 0 0 0 0", - " 0 0 0 0 0 a2 a1 a0", - " i i i i i i i i"; - - writepage = " 1 1 0 0 0 0 1 0", - " 0 0 x x a11 a10 a9 a8", - " a7 a6 a5 a4 a3 0 0 0", - " x x x x x x x x"; - - mode = 0x41; - delay = 10; - blocksize = 8; - readsize = 256; - ; - - memory "flash" - paged = yes; - size = 65536; - page_size = 256; - num_pages = 256; - min_write_delay = 4500; - max_write_delay = 4500; - readback_p1 = 0x00; - readback_p2 = 0x00; - read_lo = " 0 0 1 0 0 0 0 0", - " 0 a14 a13 a12 a11 a10 a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " o o o o o o o o"; - - read_hi = " 0 0 1 0 1 0 0 0", - " 0 a14 a13 a12 a11 a10 a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " o o o o o o o o"; - - loadpage_lo = " 0 1 0 0 0 0 0 0", - " x x x x x x x x", - " x a6 a5 a4 a3 a2 a1 a0", - " i i i i i i i i"; - - loadpage_hi = " 0 1 0 0 1 0 0 0", - " x x x x x x x x", - " x a6 a5 a4 a3 a2 a1 a0", - " i i i i i i i i"; - - writepage = " 0 1 0 0 1 1 0 0", - " 0 a14 a13 a12 a11 a10 a9 a8", - " a7 x x x x x x x", - " x x x x x x x x"; - - mode = 0x41; - delay = 10; - blocksize = 256; - readsize = 256; - ; - - memory "lfuse" - size = 1; - write = "1 0 1 0 1 1 0 0 1 0 1 0 0 0 0 0", - "x x x x x x x x i i i i i i i i"; - - read = "0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0", - "x x x x x x x x o o o o o o o o"; - min_write_delay = 9000; - max_write_delay = 9000; - ; - - memory "hfuse" - size = 1; - write = "1 0 1 0 1 1 0 0 1 0 1 0 1 0 0 0", - "x x x x x x x x i i i i i i i i"; - - read = "0 1 0 1 1 0 0 0 0 0 0 0 1 0 0 0", - "x x x x x x x x o o o o o o o o"; - min_write_delay = 9000; - max_write_delay = 9000; - ; - - memory "efuse" - size = 1; - write = "1 0 1 0 1 1 0 0 1 0 1 0 0 1 0 0", - "x x x x x x x x x x x x x i i i"; - - read = "0 1 0 1 0 0 0 0 0 0 0 0 1 0 0 0", - "x x x x x x x x o o o o o o o o"; - min_write_delay = 9000; - max_write_delay = 9000; - ; - - memory "lock" - size = 1; - read = "0 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0", - "x x x x x x x x x x o o o o o o"; - - write = "1 0 1 0 1 1 0 0 1 1 1 x x x x x", - "x x x x x x x x 1 1 i i i i i i"; - min_write_delay = 9000; - max_write_delay = 9000; - ; - - memory "calibration" - size = 1; - read = "0 0 1 1 1 0 0 0 x x x x x x x x", - "0 0 0 0 0 0 0 0 o o o o o o o o"; - ; - - memory "signature" - size = 3; - read = "0 0 1 1 0 0 0 0 x x x x x x x x", - "x x x x x x a1 a0 o o o o o o o o"; - ; - ; - -#------------------------------------------------------------ -# ATmega1280 -#------------------------------------------------------------ - -part - id = "m1280"; - desc = "ATmega1280"; - signature = 0x1e 0x97 0x03; - has_jtag = yes; -# stk500_devcode = 0xB2; -# avr910_devcode = 0x43; - chip_erase_delay = 9000; - pagel = 0xD7; - bs2 = 0xA0; - reset = dedicated; - pgm_enable = "1 0 1 0 1 1 0 0 0 1 0 1 0 0 1 1", - "x x x x x x x x x x x x x x x x"; - - chip_erase = "1 0 1 0 1 1 0 0 1 0 0 0 0 0 0 0", - "x x x x x x x x x x x x x x x x"; - - timeout = 200; - stabdelay = 100; - cmdexedelay = 25; - synchloops = 32; - bytedelay = 0; - pollindex = 3; - pollvalue = 0x53; - predelay = 1; - postdelay = 1; - pollmethod = 1; - - pp_controlstack = - 0x0E, 0x1E, 0x0F, 0x1F, 0x2E, 0x3E, 0x2F, 0x3F, - 0x4E, 0x5E, 0x4F, 0x5F, 0x6E, 0x7E, 0x6F, 0x7F, - 0x66, 0x76, 0x67, 0x77, 0x6A, 0x7A, 0x6B, 0x7B, - 0xBE, 0xFD, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00; - hventerstabdelay = 100; - progmodedelay = 0; - latchcycles = 5; - togglevtg = 1; - poweroffdelay = 15; - resetdelayms = 1; - resetdelayus = 0; - hvleavestabdelay = 15; - chiperasepulsewidth = 0; - chiperasepolltimeout = 10; - programfusepulsewidth = 0; - programfusepolltimeout = 5; - programlockpulsewidth = 0; - programlockpolltimeout = 5; - - idr = 0x31; - spmcr = 0x57; - rampz = 0x3b; - allowfullpagebitstream = no; - - ocdrev = 3; - - memory "eeprom" - paged = no; /* leave this "no" */ - page_size = 8; /* for parallel programming */ - size = 4096; - min_write_delay = 9000; - max_write_delay = 9000; - readback_p1 = 0x00; - readback_p2 = 0x00; - read = " 1 0 1 0 0 0 0 0", - " x x x x a11 a10 a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " o o o o o o o o"; - - write = " 1 1 0 0 0 0 0 0", - " x x x x a11 a10 a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " i i i i i i i i"; - - loadpage_lo = " 1 1 0 0 0 0 0 1", - " 0 0 0 0 0 0 0 0", - " 0 0 0 0 0 a2 a1 a0", - " i i i i i i i i"; - - writepage = " 1 1 0 0 0 0 1 0", - " 0 0 x x a11 a10 a9 a8", - " a7 a6 a5 a4 a3 0 0 0", - " x x x x x x x x"; - - mode = 0x41; - delay = 10; - blocksize = 8; - readsize = 256; - ; - - memory "flash" - paged = yes; - size = 131072; - page_size = 256; - num_pages = 512; - min_write_delay = 4500; - max_write_delay = 4500; - readback_p1 = 0x00; - readback_p2 = 0x00; - read_lo = " 0 0 1 0 0 0 0 0", - "a15 a14 a13 a12 a11 a10 a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " o o o o o o o o"; - - read_hi = " 0 0 1 0 1 0 0 0", - "a15 a14 a13 a12 a11 a10 a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " o o o o o o o o"; - - loadpage_lo = " 0 1 0 0 0 0 0 0", - " x x x x x x x x", - " x a6 a5 a4 a3 a2 a1 a0", - " i i i i i i i i"; - - loadpage_hi = " 0 1 0 0 1 0 0 0", - " x x x x x x x x", - " x a6 a5 a4 a3 a2 a1 a0", - " i i i i i i i i"; - - writepage = " 0 1 0 0 1 1 0 0", - "a15 a14 a13 a12 a11 a10 a9 a8", - " a7 x x x x x x x", - " x x x x x x x x"; - - mode = 0x41; - delay = 10; - blocksize = 256; - readsize = 256; - ; - - memory "lfuse" - size = 1; - write = "1 0 1 0 1 1 0 0 1 0 1 0 0 0 0 0", - "x x x x x x x x i i i i i i i i"; - - read = "0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0", - "x x x x x x x x o o o o o o o o"; - min_write_delay = 9000; - max_write_delay = 9000; - ; - - memory "hfuse" - size = 1; - write = "1 0 1 0 1 1 0 0 1 0 1 0 1 0 0 0", - "x x x x x x x x i i i i i i i i"; - - read = "0 1 0 1 1 0 0 0 0 0 0 0 1 0 0 0", - "x x x x x x x x o o o o o o o o"; - min_write_delay = 9000; - max_write_delay = 9000; - ; - - memory "efuse" - size = 1; - write = "1 0 1 0 1 1 0 0 1 0 1 0 0 1 0 0", - "x x x x x x x x x x x x x i i i"; - - read = "0 1 0 1 0 0 0 0 0 0 0 0 1 0 0 0", - "x x x x x x x x o o o o o o o o"; - min_write_delay = 9000; - max_write_delay = 9000; - ; - - memory "lock" - size = 1; - read = "0 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0", - "x x x x x x x x x x o o o o o o"; - - write = "1 0 1 0 1 1 0 0 1 1 1 x x x x x", - "x x x x x x x x 1 1 i i i i i i"; - min_write_delay = 9000; - max_write_delay = 9000; - ; - - memory "calibration" - size = 1; - read = "0 0 1 1 1 0 0 0 x x x x x x x x", - "0 0 0 0 0 0 0 0 o o o o o o o o"; - ; - - memory "signature" - size = 3; - read = "0 0 1 1 0 0 0 0 x x x x x x x x", - "x x x x x x a1 a0 o o o o o o o o"; - ; - ; - -#------------------------------------------------------------ -# ATmega1281 -#------------------------------------------------------------ -# Identical to ATmega1280 - -part parent "m1280" - id = "m1281"; - desc = "ATmega1281"; - signature = 0x1e 0x97 0x04; - - ocdrev = 3; - ; - -#------------------------------------------------------------ -# ATmega2560 -#------------------------------------------------------------ - -part - id = "m2560"; - desc = "ATmega2560"; - signature = 0x1e 0x98 0x01; - has_jtag = yes; - stk500_devcode = 0xB2; -# avr910_devcode = 0x43; - chip_erase_delay = 9000; - pagel = 0xD7; - bs2 = 0xA0; - reset = dedicated; - pgm_enable = "1 0 1 0 1 1 0 0 0 1 0 1 0 0 1 1", - "x x x x x x x x x x x x x x x x"; - - chip_erase = "1 0 1 0 1 1 0 0 1 0 0 0 0 0 0 0", - "x x x x x x x x x x x x x x x x"; - - timeout = 200; - stabdelay = 100; - cmdexedelay = 25; - synchloops = 32; - bytedelay = 0; - pollindex = 3; - pollvalue = 0x53; - predelay = 1; - postdelay = 1; - pollmethod = 1; - - pp_controlstack = - 0x0E, 0x1E, 0x0F, 0x1F, 0x2E, 0x3E, 0x2F, 0x3F, - 0x4E, 0x5E, 0x4F, 0x5F, 0x6E, 0x7E, 0x6F, 0x7F, - 0x66, 0x76, 0x67, 0x77, 0x6A, 0x7A, 0x6B, 0x7B, - 0xBE, 0xFD, 0x00, 0x01, 0x00, 0x00, 0x00, 0x02; - hventerstabdelay = 100; - progmodedelay = 0; - latchcycles = 5; - togglevtg = 1; - poweroffdelay = 15; - resetdelayms = 1; - resetdelayus = 0; - hvleavestabdelay = 15; - chiperasepulsewidth = 0; - chiperasepolltimeout = 10; - programfusepulsewidth = 0; - programfusepolltimeout = 5; - programlockpulsewidth = 0; - programlockpolltimeout = 5; - - idr = 0x31; - spmcr = 0x57; - rampz = 0x3b; - allowfullpagebitstream = no; - - ocdrev = 4; - - memory "eeprom" - paged = no; /* leave this "no" */ - page_size = 8; /* for parallel programming */ - size = 4096; - min_write_delay = 9000; - max_write_delay = 9000; - readback_p1 = 0x00; - readback_p2 = 0x00; - read = " 1 0 1 0 0 0 0 0", - " x x x x a11 a10 a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " o o o o o o o o"; - - write = " 1 1 0 0 0 0 0 0", - " x x x x a11 a10 a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " i i i i i i i i"; - - loadpage_lo = " 1 1 0 0 0 0 0 1", - " 0 0 0 0 0 0 0 0", - " 0 0 0 0 0 a2 a1 a0", - " i i i i i i i i"; - - writepage = " 1 1 0 0 0 0 1 0", - " 0 0 x x a11 a10 a9 a8", - " a7 a6 a5 a4 a3 0 0 0", - " x x x x x x x x"; - - mode = 0x41; - delay = 10; - blocksize = 8; - readsize = 256; - ; - - memory "flash" - paged = yes; - size = 262144; - page_size = 256; - num_pages = 1024; - min_write_delay = 4500; - max_write_delay = 4500; - readback_p1 = 0x00; - readback_p2 = 0x00; - read_lo = " 0 0 1 0 0 0 0 0", - "a15 a14 a13 a12 a11 a10 a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " o o o o o o o o"; - - read_hi = " 0 0 1 0 1 0 0 0", - "a15 a14 a13 a12 a11 a10 a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " o o o o o o o o"; - - loadpage_lo = " 0 1 0 0 0 0 0 0", - " x x x x x x x x", - " x a6 a5 a4 a3 a2 a1 a0", - " i i i i i i i i"; - - loadpage_hi = " 0 1 0 0 1 0 0 0", - " x x x x x x x x", - " x a6 a5 a4 a3 a2 a1 a0", - " i i i i i i i i"; - - writepage = " 0 1 0 0 1 1 0 0", - "a15 a14 a13 a12 a11 a10 a9 a8", - " a7 x x x x x x x", - " x x x x x x x x"; - - load_ext_addr = " 0 1 0 0 1 1 0 1", - " 0 0 0 0 0 0 0 0", - " 0 0 0 0 0 0 0 a16", - " 0 0 0 0 0 0 0 0"; - - mode = 0x41; - delay = 10; - blocksize = 256; - readsize = 256; - ; - - memory "lfuse" - size = 1; - write = "1 0 1 0 1 1 0 0 1 0 1 0 0 0 0 0", - "x x x x x x x x i i i i i i i i"; - - read = "0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0", - "x x x x x x x x o o o o o o o o"; - min_write_delay = 9000; - max_write_delay = 9000; - ; - - memory "hfuse" - size = 1; - write = "1 0 1 0 1 1 0 0 1 0 1 0 1 0 0 0", - "x x x x x x x x i i i i i i i i"; - - read = "0 1 0 1 1 0 0 0 0 0 0 0 1 0 0 0", - "x x x x x x x x o o o o o o o o"; - min_write_delay = 9000; - max_write_delay = 9000; - ; - - memory "efuse" - size = 1; - write = "1 0 1 0 1 1 0 0 1 0 1 0 0 1 0 0", - "x x x x x x x x x x x x x i i i"; - - read = "0 1 0 1 0 0 0 0 0 0 0 0 1 0 0 0", - "x x x x x x x x o o o o o o o o"; - min_write_delay = 9000; - max_write_delay = 9000; - ; - - memory "lock" - size = 1; - read = "0 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0", - "x x x x x x x x x x o o o o o o"; - - write = "1 0 1 0 1 1 0 0 1 1 1 x x x x x", - "x x x x x x x x 1 1 i i i i i i"; - min_write_delay = 9000; - max_write_delay = 9000; - ; - - memory "calibration" - size = 1; - read = "0 0 1 1 1 0 0 0 x x x x x x x x", - "0 0 0 0 0 0 0 0 o o o o o o o o"; - ; - - memory "signature" - size = 3; - read = "0 0 1 1 0 0 0 0 x x x x x x x x", - "x x x x x x a1 a0 o o o o o o o o"; - ; - ; - -#------------------------------------------------------------ -# ATmega2561 -#------------------------------------------------------------ - -part parent "m2560" - id = "m2561"; - desc = "ATmega2561"; - signature = 0x1e 0x98 0x02; - - ocdrev = 4; - ; - -#------------------------------------------------------------ -# ATmega128RFA1 -#------------------------------------------------------------ -# Identical to ATmega2561 but half the ROM - -part parent "m2561" - id = "m128rfa1"; - desc = "ATmega128RFA1"; - signature = 0x1e 0xa7 0x01; - chip_erase_delay = 55000; - bs2 = 0xE2; - - ocdrev = 3; - - memory "flash" - paged = yes; - size = 131072; - page_size = 256; - num_pages = 512; - min_write_delay = 50000; - max_write_delay = 50000; - readback_p1 = 0x00; - readback_p2 = 0x00; - read_lo = " 0 0 1 0 0 0 0 0", - "a15 a14 a13 a12 a11 a10 a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " o o o o o o o o"; - - read_hi = " 0 0 1 0 1 0 0 0", - "a15 a14 a13 a12 a11 a10 a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " o o o o o o o o"; - - loadpage_lo = " 0 1 0 0 0 0 0 0", - " x x x x x x x x", - " x a6 a5 a4 a3 a2 a1 a0", - " i i i i i i i i"; - - loadpage_hi = " 0 1 0 0 1 0 0 0", - " x x x x x x x x", - " x a6 a5 a4 a3 a2 a1 a0", - " i i i i i i i i"; - - writepage = " 0 1 0 0 1 1 0 0", - "a15 a14 a13 a12 a11 a10 a9 a8", - " a7 x x x x x x x", - " x x x x x x x x"; - - mode = 0x41; - delay = 20; - blocksize = 256; - readsize = 256; - ; - ; - -#------------------------------------------------------------ -# ATmega256RFR2 -#------------------------------------------------------------ - -part parent "m2561" - id = "m256rfr2"; - desc = "ATmega256RFR2"; - signature = 0x1e 0xa8 0x02; - chip_erase_delay = 18500; - bs2 = 0xE2; - - memory "eeprom" - paged = no; /* leave this "no" */ - page_size = 8; /* for parallel programming */ - size = 8192; - min_write_delay = 13000; - max_write_delay = 13000; - readback_p1 = 0x00; - readback_p2 = 0x00; - read = " 1 0 1 0 0 0 0 0", - " x x x a12 a11 a10 a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " o o o o o o o o"; - - write = " 1 1 0 0 0 0 0 0", - " x x x a12 a11 a10 a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " i i i i i i i i"; - - loadpage_lo = " 1 1 0 0 0 0 0 1", - " 0 0 0 0 0 0 0 0", - " 0 0 0 0 0 a2 a1 a0", - " i i i i i i i i"; - - writepage = " 1 1 0 0 0 0 1 0", - " 0 0 x a12 a11 a10 a9 a8", - " a7 a6 a5 a4 a3 0 0 0", - " x x x x x x x x"; - - mode = 0x41; - delay = 10; - blocksize = 8; - readsize = 256; - ; - - - ocdrev = 4; - ; - -#------------------------------------------------------------ -# ATmega128RFR2 -#------------------------------------------------------------ - -part parent "m128rfa1" - id = "m128rfr2"; - desc = "ATmega128RFR2"; - signature = 0x1e 0xa7 0x02; - - - ocdrev = 3; - ; - -#------------------------------------------------------------ -# ATmega64RFR2 -#------------------------------------------------------------ - -part parent "m128rfa1" - id = "m64rfr2"; - desc = "ATmega64RFR2"; - signature = 0x1e 0xa6 0x02; - - - ocdrev = 3; - - memory "flash" - paged = yes; - size = 65536; - page_size = 256; - num_pages = 256; - min_write_delay = 50000; - max_write_delay = 50000; - readback_p1 = 0x00; - readback_p2 = 0x00; - read_lo = " 0 0 1 0 0 0 0 0", - " 0 a14 a13 a12 a11 a10 a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " o o o o o o o o"; - - read_hi = " 0 0 1 0 1 0 0 0", - " 0 a14 a13 a12 a11 a10 a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " o o o o o o o o"; - - loadpage_lo = " 0 1 0 0 0 0 0 0", - " x x x x x x x x", - " x a6 a5 a4 a3 a2 a1 a0", - " i i i i i i i i"; - - loadpage_hi = " 0 1 0 0 1 0 0 0", - " x x x x x x x x", - " x a6 a5 a4 a3 a2 a1 a0", - " i i i i i i i i"; - - writepage = " 0 1 0 0 1 1 0 0", - " 0 a14 a13 a12 a11 a10 a9 a8", - " a7 x x x x x x x", - " x x x x x x x x"; - - mode = 0x41; - delay = 20; - blocksize = 256; - readsize = 256; - ; - - memory "eeprom" - paged = no; /* leave this "no" */ - page_size = 8; /* for parallel programming */ - size = 2048; - min_write_delay = 13000; - max_write_delay = 13000; - readback_p1 = 0x00; - readback_p2 = 0x00; - read = " 1 0 1 0 0 0 0 0", - " x x x x x a10 a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " o o o o o o o o"; - - write = " 1 1 0 0 0 0 0 0", - " x x x x x a10 a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " i i i i i i i i"; - - loadpage_lo = " 1 1 0 0 0 0 0 1", - " 0 0 0 0 0 0 0 0", - " 0 0 0 0 0 a2 a1 a0", - " i i i i i i i i"; - - writepage = " 1 1 0 0 0 0 1 0", - " 0 0 x x x a10 a9 a8", - " a7 a6 a5 a4 a3 0 0 0", - " x x x x x x x x"; - - mode = 0x41; - delay = 10; - blocksize = 8; - readsize = 256; - ; - - - ; - -#------------------------------------------------------------ -# ATmega2564RFR2 -#------------------------------------------------------------ - -part parent "m256rfr2" - id = "m2564rfr2"; - desc = "ATmega2564RFR2"; - signature = 0x1e 0xa8 0x03; - ; - -#------------------------------------------------------------ -# ATmega1284RFR2 -#------------------------------------------------------------ - -part parent "m128rfr2" - id = "m1284rfr2"; - desc = "ATmega1284RFR2"; - signature = 0x1e 0xa7 0x03; - ; - -#------------------------------------------------------------ -# ATmega644RFR2 -#------------------------------------------------------------ - -part parent "m64rfr2" - id = "m644rfr2"; - desc = "ATmega644RFR2"; - signature = 0x1e 0xa6 0x03; - ; - -#------------------------------------------------------------ -# ATtiny24 -#------------------------------------------------------------ - -part - id = "t24"; - desc = "ATtiny24"; - has_debugwire = yes; - flash_instr = 0xB4, 0x07, 0x17; - eeprom_instr = 0xBB, 0xFF, 0xBB, 0xEE, 0xBB, 0xCC, 0xB2, 0x0D, - 0xBC, 0x07, 0xB4, 0x07, 0xBA, 0x0D, 0xBB, 0xBC, - 0x99, 0xE1, 0xBB, 0xAC; -## no STK500 devcode in XML file, use the ATtiny45 one - stk500_devcode = 0x14; -## avr910_devcode = ?; -## Try the AT90S2313 devcode: - avr910_devcode = 0x20; - signature = 0x1e 0x91 0x0b; - reset = io; - chip_erase_delay = 4500; - - pgm_enable = "1 0 1 0 1 1 0 0 0 1 0 1 0 0 1 1", - "x x x x x x x x x x x x x x x x"; - - chip_erase = "1 0 1 0 1 1 0 0 1 0 0 x x x x x", - "x x x x x x x x x x x x x x x x"; - - timeout = 200; - stabdelay = 100; - cmdexedelay = 25; - synchloops = 32; - bytedelay = 0; - pollindex = 3; - pollvalue = 0x53; - predelay = 1; - postdelay = 1; - pollmethod = 1; - - hvsp_controlstack = - 0x4C, 0x0C, 0x1C, 0x2C, 0x3C, 0x64, 0x74, 0x66, - 0x68, 0x78, 0x68, 0x68, 0x7A, 0x6A, 0x68, 0x78, - 0x78, 0x7D, 0x6D, 0x0C, 0x80, 0x40, 0x20, 0x10, - 0x11, 0x08, 0x04, 0x02, 0x03, 0x08, 0x04, 0x0F; - hventerstabdelay = 100; - hvspcmdexedelay = 0; - synchcycles = 6; - latchcycles = 1; - togglevtg = 1; - poweroffdelay = 25; - resetdelayms = 0; - resetdelayus = 70; - hvleavestabdelay = 100; - resetdelay = 25; - chiperasepolltimeout = 40; - chiperasetime = 0; - programfusepolltimeout = 25; - programlockpolltimeout = 25; - - ocdrev = 1; - - memory "eeprom" - size = 128; - paged = no; - page_size = 4; - min_write_delay = 4000; - max_write_delay = 4500; - readback_p1 = 0xff; - readback_p2 = 0xff; - read = "1 0 1 0 0 0 0 0 0 0 0 x x x x x", - "x a6 a5 a4 a3 a2 a1 a0 o o o o o o o o"; - - write = "1 1 0 0 0 0 0 0 0 0 0 x x x x x", - "x a6 a5 a4 a3 a2 a1 a0 i i i i i i i i"; - - loadpage_lo = " 1 1 0 0 0 0 0 1", - " 0 0 0 0 0 0 0 0", - " 0 0 0 0 0 0 a1 a0", - " i i i i i i i i"; - - writepage = " 1 1 0 0 0 0 1 0", - " 0 0 x x x x x x", - " x a6 a5 a4 a3 a2 0 0", - " x x x x x x x x"; - - mode = 0x41; - delay = 6; - blocksize = 4; - readsize = 256; - ; - memory "flash" - paged = yes; - size = 2048; - page_size = 32; - num_pages = 64; - min_write_delay = 4500; - max_write_delay = 4500; - readback_p1 = 0xff; - readback_p2 = 0xff; - read_lo = " 0 0 1 0 0 0 0 0", - " 0 0 0 0 0 0 a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " o o o o o o o o"; - - read_hi = " 0 0 1 0 1 0 0 0", - " 0 0 0 0 0 0 a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " o o o o o o o o"; - - loadpage_lo = " 0 1 0 0 0 0 0 0", - " 0 0 0 x x x x x", - " x x x x a3 a2 a1 a0", - " i i i i i i i i"; - - loadpage_hi = " 0 1 0 0 1 0 0 0", - " 0 0 0 x x x x x", - " x x x x a3 a2 a1 a0", - " i i i i i i i i"; - - writepage = " 0 1 0 0 1 1 0 0", - " 0 0 0 0 0 0 a9 a8", - " a7 a6 a5 a4 x x x x", - " x x x x x x x x"; - - mode = 0x41; - delay = 6; - blocksize = 32; - readsize = 256; - ; -# ATtiny24 has Signature Bytes: 0x1E 0x91 0x0B. - memory "signature" - size = 3; - read = "0 0 1 1 0 0 0 0 0 0 0 x x x x x", - "x x x x x x a1 a0 o o o o o o o o"; - ; - memory "lock" - size = 1; - write = "1 0 1 0 1 1 0 0 1 1 1 x x x x x", - "x x x x x x x x x x x x x x i i"; - read = "0 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0", - "0 0 0 0 0 0 0 0 o o o o o o o o"; - min_write_delay = 9000; - max_write_delay = 9000; - ; - - memory "lfuse" - size = 1; - write = "1 0 1 0 1 1 0 0 1 0 1 0 0 0 0 0", - "x x x x x x x x i i i i i i i i"; - - read = "0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0", - "x x x x x x x x o o o o o o o o"; - min_write_delay = 9000; - max_write_delay = 9000; - ; - - memory "hfuse" - size = 1; - write = "1 0 1 0 1 1 0 0 1 0 1 0 1 0 0 0", - "x x x x x x x x i i i i i i i i"; - - read = "0 1 0 1 1 0 0 0 0 0 0 0 1 0 0 0", - "x x x x x x x x o o o o o o o o"; - min_write_delay = 9000; - max_write_delay = 9000; - ; - - memory "efuse" - size = 1; - write = "1 0 1 0 1 1 0 0 1 0 1 0 0 1 0 0", - "x x x x x x x x x x x x x x x i"; - - read = "0 1 0 1 0 0 0 0 0 0 0 0 1 0 0 0", - "x x x x x x x x o o o o o o o o"; - min_write_delay = 9000; - max_write_delay = 9000; - ; - - memory "calibration" - size = 1; - read = "0 0 1 1 1 0 0 0 0 0 0 x x x x x", - "0 0 0 0 0 0 0 a0 o o o o o o o o"; - ; - ; - -#------------------------------------------------------------ -# ATtiny44 -#------------------------------------------------------------ - -part - id = "t44"; - desc = "ATtiny44"; - has_debugwire = yes; - flash_instr = 0xB4, 0x07, 0x17; - eeprom_instr = 0xBB, 0xFF, 0xBB, 0xEE, 0xBB, 0xCC, 0xB2, 0x0D, - 0xBC, 0x07, 0xB4, 0x07, 0xBA, 0x0D, 0xBB, 0xBC, - 0x99, 0xE1, 0xBB, 0xAC; -## no STK500 devcode in XML file, use the ATtiny45 one - stk500_devcode = 0x14; -## avr910_devcode = ?; -## Try the AT90S2313 devcode: - avr910_devcode = 0x20; - signature = 0x1e 0x92 0x07; - reset = io; - chip_erase_delay = 4500; - - pgm_enable = "1 0 1 0 1 1 0 0 0 1 0 1 0 0 1 1", - "x x x x x x x x x x x x x x x x"; - - chip_erase = "1 0 1 0 1 1 0 0 1 0 0 x x x x x", - "x x x x x x x x x x x x x x x x"; - - timeout = 200; - stabdelay = 100; - cmdexedelay = 25; - synchloops = 32; - bytedelay = 0; - pollindex = 3; - pollvalue = 0x53; - predelay = 1; - postdelay = 1; - pollmethod = 1; - - hvsp_controlstack = - 0x4C, 0x0C, 0x1C, 0x2C, 0x3C, 0x64, 0x74, 0x66, - 0x68, 0x78, 0x68, 0x68, 0x7A, 0x6A, 0x68, 0x78, - 0x78, 0x7D, 0x6D, 0x0C, 0x80, 0x40, 0x20, 0x10, - 0x11, 0x08, 0x04, 0x02, 0x03, 0x08, 0x04, 0x0F; - hventerstabdelay = 100; - hvspcmdexedelay = 0; - synchcycles = 6; - latchcycles = 1; - togglevtg = 1; - poweroffdelay = 25; - resetdelayms = 0; - resetdelayus = 70; - hvleavestabdelay = 100; - resetdelay = 25; - chiperasepolltimeout = 40; - chiperasetime = 0; - programfusepolltimeout = 25; - programlockpolltimeout = 25; - - ocdrev = 1; - - memory "eeprom" - size = 256; - paged = no; - page_size = 4; - min_write_delay = 4000; - max_write_delay = 4500; - readback_p1 = 0xff; - readback_p2 = 0xff; - read = "1 0 1 0 0 0 0 0 0 0 0 x x x x x", - "a7 a6 a5 a4 a3 a2 a1 a0 o o o o o o o o"; - - write = "1 1 0 0 0 0 0 0 0 0 0 x x x x x", - "a7 a6 a5 a4 a3 a2 a1 a0 i i i i i i i i"; - - loadpage_lo = " 1 1 0 0 0 0 0 1", - " 0 0 0 0 0 0 0 0", - " 0 0 0 0 0 0 a1 a0", - " i i i i i i i i"; - - writepage = " 1 1 0 0 0 0 1 0", - " 0 0 x x x x x x", - " x a6 a5 a4 a3 a2 0 0", - " x x x x x x x x"; - - mode = 0x41; - delay = 6; - blocksize = 4; - readsize = 256; - ; - memory "flash" - paged = yes; - size = 4096; - page_size = 64; - num_pages = 64; - min_write_delay = 4500; - max_write_delay = 4500; - readback_p1 = 0xff; - readback_p2 = 0xff; - read_lo = " 0 0 1 0 0 0 0 0", - " 0 0 0 0 0 a10 a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " o o o o o o o o"; - - read_hi = " 0 0 1 0 1 0 0 0", - " 0 0 0 0 0 a10 a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " o o o o o o o o"; - - loadpage_lo = " 0 1 0 0 0 0 0 0", - " 0 0 0 x x x x x", - " x x x a4 a3 a2 a1 a0", - " i i i i i i i i"; - - loadpage_hi = " 0 1 0 0 1 0 0 0", - " 0 0 0 x x x x x", - " x x x a4 a3 a2 a1 a0", - " i i i i i i i i"; - - writepage = " 0 1 0 0 1 1 0 0", - " 0 0 0 0 0 a10 a9 a8", - " a7 a6 a5 x x x x x", - " x x x x x x x x"; - - mode = 0x41; - delay = 6; - blocksize = 32; - readsize = 256; - ; -# ATtiny44 has Signature Bytes: 0x1E 0x92 0x07. - memory "signature" - size = 3; - read = "0 0 1 1 0 0 0 0 0 0 0 x x x x x", - "x x x x x x a1 a0 o o o o o o o o"; - ; - memory "lock" - size = 1; - write = "1 0 1 0 1 1 0 0 1 1 1 x x x x x", - "x x x x x x x x x x x x x x i i"; - read = "0 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0", - "0 0 0 0 0 0 0 0 o o o o o o o o"; - min_write_delay = 9000; - max_write_delay = 9000; - ; - - memory "lfuse" - size = 1; - write = "1 0 1 0 1 1 0 0 1 0 1 0 0 0 0 0", - "x x x x x x x x i i i i i i i i"; - - read = "0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0", - "x x x x x x x x o o o o o o o o"; - min_write_delay = 9000; - max_write_delay = 9000; - ; - - memory "hfuse" - size = 1; - write = "1 0 1 0 1 1 0 0 1 0 1 0 1 0 0 0", - "x x x x x x x x i i i i i i i i"; - - read = "0 1 0 1 1 0 0 0 0 0 0 0 1 0 0 0", - "x x x x x x x x o o o o o o o o"; - min_write_delay = 9000; - max_write_delay = 9000; - ; - - memory "efuse" - size = 1; - write = "1 0 1 0 1 1 0 0 1 0 1 0 0 1 0 0", - "x x x x x x x x x x x x x x x i"; - - read = "0 1 0 1 0 0 0 0 0 0 0 0 1 0 0 0", - "x x x x x x x x o o o o o o o o"; - min_write_delay = 9000; - max_write_delay = 9000; - ; - - memory "calibration" - size = 1; - read = "0 0 1 1 1 0 0 0 0 0 0 x x x x x", - "0 0 0 0 0 0 0 a0 o o o o o o o o"; - ; - ; - -#------------------------------------------------------------ -# ATtiny84 -#------------------------------------------------------------ - -part - id = "t84"; - desc = "ATtiny84"; - has_debugwire = yes; - flash_instr = 0xB4, 0x07, 0x17; - eeprom_instr = 0xBB, 0xFF, 0xBB, 0xEE, 0xBB, 0xCC, 0xB2, 0x0D, - 0xBC, 0x07, 0xB4, 0x07, 0xBA, 0x0D, 0xBB, 0xBC, - 0x99, 0xE1, 0xBB, 0xAC; -## no STK500 devcode in XML file, use the ATtiny45 one - stk500_devcode = 0x14; -## avr910_devcode = ?; -## Try the AT90S2313 devcode: - avr910_devcode = 0x20; - signature = 0x1e 0x93 0x0c; - reset = io; - chip_erase_delay = 4500; - - pgm_enable = "1 0 1 0 1 1 0 0 0 1 0 1 0 0 1 1", - "x x x x x x x x x x x x x x x x"; - - chip_erase = "1 0 1 0 1 1 0 0 1 0 0 x x x x x", - "x x x x x x x x x x x x x x x x"; - - timeout = 200; - stabdelay = 100; - cmdexedelay = 25; - synchloops = 32; - bytedelay = 0; - pollindex = 3; - pollvalue = 0x53; - predelay = 1; - postdelay = 1; - pollmethod = 1; - - hvsp_controlstack = - 0x4C, 0x0C, 0x1C, 0x2C, 0x3C, 0x64, 0x74, 0x66, - 0x68, 0x78, 0x68, 0x68, 0x7A, 0x6A, 0x68, 0x78, - 0x78, 0x7D, 0x6D, 0x0C, 0x80, 0x40, 0x20, 0x10, - 0x11, 0x08, 0x04, 0x02, 0x03, 0x08, 0x04, 0x0F; - hventerstabdelay = 100; - hvspcmdexedelay = 0; - synchcycles = 6; - latchcycles = 1; - togglevtg = 1; - poweroffdelay = 25; - resetdelayms = 0; - resetdelayus = 70; - hvleavestabdelay = 100; - resetdelay = 25; - chiperasepolltimeout = 40; - chiperasetime = 0; - programfusepolltimeout = 25; - programlockpolltimeout = 25; - - ocdrev = 1; - - memory "eeprom" - size = 512; - paged = no; - page_size = 4; - min_write_delay = 4000; - max_write_delay = 4500; - readback_p1 = 0xff; - readback_p2 = 0xff; - read = "1 0 1 0 0 0 0 0 0 0 0 x x x x a8", - "a7 a6 a5 a4 a3 a2 a1 a0 o o o o o o o o"; - - write = "1 1 0 0 0 0 0 0 0 0 0 x x x x a8", - "a7 a6 a5 a4 a3 a2 a1 a0 i i i i i i i i"; - - loadpage_lo = " 1 1 0 0 0 0 0 1", - " 0 0 0 0 0 0 0 0", - " 0 0 0 0 0 0 a1 a0", - " i i i i i i i i"; - - writepage = " 1 1 0 0 0 0 1 0", - " 0 0 x x x x x x", - " x a6 a5 a4 a3 a2 0 0", - " x x x x x x x x"; - - mode = 0x41; - delay = 6; - blocksize = 4; - readsize = 256; - ; - memory "flash" - paged = yes; - size = 8192; - page_size = 64; - num_pages = 128; - min_write_delay = 4500; - max_write_delay = 4500; - readback_p1 = 0xff; - readback_p2 = 0xff; - read_lo = " 0 0 1 0 0 0 0 0", - " 0 0 0 0 a11 a10 a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " o o o o o o o o"; - - read_hi = " 0 0 1 0 1 0 0 0", - " 0 0 0 0 a11 a10 a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " o o o o o o o o"; - - loadpage_lo = " 0 1 0 0 0 0 0 0", - " 0 0 0 x x x x x", - " x x x a4 a3 a2 a1 a0", - " i i i i i i i i"; - - loadpage_hi = " 0 1 0 0 1 0 0 0", - " 0 0 0 x x x x x", - " x x x a4 a3 a2 a1 a0", - " i i i i i i i i"; - - writepage = " 0 1 0 0 1 1 0 0", - " 0 0 0 0 a11 a10 a9 a8", - " a7 a6 a5 x x x x x", - " x x x x x x x x"; - - mode = 0x41; - delay = 6; - blocksize = 32; - readsize = 256; - ; -# ATtiny84 has Signature Bytes: 0x1E 0x93 0x0C. - memory "signature" - size = 3; - read = "0 0 1 1 0 0 0 0 0 0 0 x x x x x", - "x x x x x x a1 a0 o o o o o o o o"; - ; - - memory "lock" - size = 1; - write = "1 0 1 0 1 1 0 0 1 1 1 x x x x x", - "x x x x x x x x x x x x x x i i"; - read = "0 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0", - "0 0 0 0 0 0 0 0 o o o o o o o o"; - min_write_delay = 9000; - max_write_delay = 9000; - ; - - memory "lfuse" - size = 1; - write = "1 0 1 0 1 1 0 0 1 0 1 0 0 0 0 0", - "x x x x x x x x i i i i i i i i"; - - read = "0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0", - "x x x x x x x x o o o o o o o o"; - min_write_delay = 9000; - max_write_delay = 9000; - ; - - memory "hfuse" - size = 1; - write = "1 0 1 0 1 1 0 0 1 0 1 0 1 0 0 0", - "x x x x x x x x i i i i i i i i"; - - read = "0 1 0 1 1 0 0 0 0 0 0 0 1 0 0 0", - "x x x x x x x x o o o o o o o o"; - min_write_delay = 9000; - max_write_delay = 9000; - ; - - memory "efuse" - size = 1; - write = "1 0 1 0 1 1 0 0 1 0 1 0 0 1 0 0", - "x x x x x x x x x x x x x x x i"; - - read = "0 1 0 1 0 0 0 0 0 0 0 0 1 0 0 0", - "x x x x x x x x o o o o o o o o"; - min_write_delay = 9000; - max_write_delay = 9000; - ; - - memory "calibration" - size = 1; - read = "0 0 1 1 1 0 0 0 0 0 0 x x x x x", - "0 0 0 0 0 0 0 a0 o o o o o o o o"; - ; - ; - -#------------------------------------------------------------ -# ATtiny441 -#------------------------------------------------------------ - -part parent "t44" - id = "t441"; - desc = "ATtiny441"; - signature = 0x1e 0x92 0x15; - - memory "flash" - paged = yes; - size = 4096; - page_size = 16; - num_pages = 256; - min_write_delay = 4500; - max_write_delay = 4500; - readback_p1 = 0xff; - readback_p2 = 0xff; - read_lo = " 0 0 1 0 0 0 0 0", - " 0 0 0 0 0 a10 a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " o o o o o o o o"; - - read_hi = " 0 0 1 0 1 0 0 0", - " 0 0 0 0 0 a10 a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " o o o o o o o o"; - - loadpage_lo = " 0 1 0 0 0 0 0 0", - " 0 0 0 x x x x x", - " x x x x x a2 a1 a0", - " i i i i i i i i"; - - loadpage_hi = " 0 1 0 0 1 0 0 0", - " 0 0 0 x x x x x", - " x x x x x a2 a1 a0", - " i i i i i i i i"; - - writepage = " 0 1 0 0 1 1 0 0", - " 0 0 0 0 0 a10 a9 a8", - " a7 a6 a5 a4 a3 x x x", - " x x x x x x x x"; - - mode = 0x41; - delay = 6; - blocksize = 16; - readsize = 256; - ; - - memory "efuse" - size = 1; - write = "1 0 1 0 1 1 0 0 1 0 1 0 0 1 0 0", - "x x x x x x x x i i i i i i i i"; - - read = "0 1 0 1 0 0 0 0 0 0 0 0 1 0 0 0", - "x x x x x x x x o o o o o o o o"; - min_write_delay = 9000; - max_write_delay = 9000; - ; -; - -#------------------------------------------------------------ -# ATtiny841 -#------------------------------------------------------------ - -part parent "t84" - id = "t841"; - desc = "ATtiny841"; - signature = 0x1e 0x93 0x15; - - memory "flash" - paged = yes; - size = 8192; - page_size = 16; - num_pages = 512; - min_write_delay = 4500; - max_write_delay = 4500; - readback_p1 = 0xff; - readback_p2 = 0xff; - read_lo = " 0 0 1 0 0 0 0 0", - " 0 0 0 0 a11 a10 a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " o o o o o o o o"; - - read_hi = " 0 0 1 0 1 0 0 0", - " 0 0 0 0 a11 a10 a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " o o o o o o o o"; - - loadpage_lo = " 0 1 0 0 0 0 0 0", - " 0 0 0 x x x x x", - " x x x x x a2 a1 a0", - " i i i i i i i i"; - - loadpage_hi = " 0 1 0 0 1 0 0 0", - " 0 0 0 x x x x x", - " x x x x x a2 a1 a0", - " i i i i i i i i"; - - writepage = " 0 1 0 0 1 1 0 0", - " 0 0 0 0 a11 a10 a9 a8", - " a7 a6 a5 a4 a3 x x x", - " x x x x x x x x"; - - mode = 0x41; - delay = 6; - blocksize = 16; - readsize = 256; - ; - - memory "efuse" - size = 1; - write = "1 0 1 0 1 1 0 0 1 0 1 0 0 1 0 0", - "x x x x x x x x i i i i i i i i"; - - read = "0 1 0 1 0 0 0 0 0 0 0 0 1 0 0 0", - "x x x x x x x x o o o o o o o o"; - min_write_delay = 9000; - max_write_delay = 9000; - ; -; - -#------------------------------------------------------------ -# ATtiny43U -#------------------------------------------------------------ - -part - id = "t43u"; - desc = "ATtiny43u"; - has_debugwire = yes; - flash_instr = 0xB4, 0x07, 0x17; - eeprom_instr = 0xBB, 0xFF, 0xBB, 0xEE, 0xBB, 0xCC, 0xB2, 0x0D, - 0xBC, 0x07, 0xB4, 0x07, 0xBA, 0x0D, 0xBB, 0xBC, - 0x99, 0xE1, 0xBB, 0xAC; - stk500_devcode = 0x14; -## avr910_devcode = ?; -## Try the AT90S2313 devcode: - avr910_devcode = 0x20; - signature = 0x1e 0x92 0x0C; - reset = io; - chip_erase_delay = 1000; - - pgm_enable = "1 0 1 0 1 1 0 0 0 1 0 1 0 0 1 1", - "x x x x x x x x x x x x x x x x"; - - chip_erase = "1 0 1 0 1 1 0 0 1 0 0 x x x x x", - "x x x x x x x x x x x x x x x x"; - - timeout = 200; - stabdelay = 100; - cmdexedelay = 25; - synchloops = 32; - bytedelay = 0; - pollindex = 3; - pollvalue = 0x53; - predelay = 1; - postdelay = 1; - pollmethod = 1; - pp_controlstack = 0x0E, 0x1E, 0x0E, 0x1E, 0x2E, 0x3E, 0x2E, 0x3E, 0x4E, 0x5E, - 0x4E, 0x5E, 0x6E, 0x7E, 0x6E, 0x7E, 0x06, 0x16, 0x46, 0x56, - 0x0A, 0x1A, 0x4A, 0x5A, 0x1E, 0x7C, 0x00, 0x01, 0x00, 0x00, - 0x00, 0x00; - hventerstabdelay = 100; - progmodedelay = 0; - hvspcmdexedelay = 0; - latchcycles = 5; - togglevtg = 1; - poweroffdelay = 20; - resetdelayms = 1; - resetdelayus = 0; - hvleavestabdelay = 15; - resetdelay = 15; - chiperasepulsewidth = 0; - chiperasepolltimeout = 10; - programfusepulsewidth = 0; - programfusepolltimeout = 5; - programlockpulsewidth = 0; - programlockpolltimeout = 5; - memory "eeprom" - size = 64; - paged = yes; - page_size = 4; - num_pages = 16; - min_write_delay = 4000; - max_write_delay = 4500; - readback_p1 = 0xff; - readback_p2 = 0xff; - read = "1 0 1 0 0 0 0 0 0 0 0 x x x x x", - "0 0 a4 a3 a2 a1 a0 o o o o o o o o"; - - write = "1 1 0 0 0 0 0 0 0 0 0 x x x x x", - "0 0 a5 a4 a3 a2 a1 a0 i i i i i i i i"; - - loadpage_lo = " 1 1 0 0 0 0 0 1", - " 0 0 0 0 0 0 0 0", - " 0 0 0 0 0 0 a1 a0", - " i i i i i i i i"; - - writepage = " 1 1 0 0 0 0 1 0", - " 0 0 x x x x x x", - " 0 0 a5 a4 a3 a2 0 0", - " x x x x x x x x"; - - mode = 0x41; - delay = 5; - blocksize = 4; - readsize = 256; - ; - memory "flash" - paged = yes; - size = 4096; - page_size = 64; - num_pages = 64; - min_write_delay = 4500; - max_write_delay = 4500; - readback_p1 = 0xff; - readback_p2 = 0xff; - - read_lo = " 0 0 1 0 0 0 0 0", - " 0 0 0 0 0 a10 a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " o o o o o o o o"; - - read_hi = " 0 0 1 0 1 0 0 0", - " 0 0 0 0 0 a10 a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " o o o o o o o o"; - - loadpage_lo = " 0 1 0 0 0 0 0 0", - " 0 0 0 x x x x x", - " x x x a4 a3 a2 a1 a0", - " i i i i i i i i"; - - loadpage_hi = " 0 1 0 0 1 0 0 0", - " 0 0 0 x x x x x", - " x x x a4 a3 a2 a1 a0", - " i i i i i i i i"; - - writepage = " 0 1 0 0 1 1 0 0", - " 0 0 0 0 0 a10 a9 a8", - " a7 a6 a5 x x x x x", - " x x x x x x x x"; - - mode = 0x41; - delay = 10; - blocksize = 64; - readsize = 256; - ; - memory "signature" - size = 3; - read = "0 0 1 1 0 0 0 0 0 0 0 x x x x x", - "x x x x x x a1 a0 o o o o o o o o"; - ; - memory "lock" - size = 1; - write = "1 0 1 0 1 1 0 0 1 1 1 x x x x x", - "x x x x x x x x 1 1 i i i i i i"; - min_write_delay = 4500; - max_write_delay = 4500; - ; - - memory "lfuse" - size = 1; - write = "1 0 1 0 1 1 0 0 1 0 1 0 0 0 0 0", - "x x x x x x x x i i i i i i i i"; - - read = "0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0", - "x x x x x x x x o o o o o o o o"; - min_write_delay = 4500; - max_write_delay = 4500; - ; - - memory "hfuse" - size = 1; - write = "1 0 1 0 1 1 0 0 1 0 1 0 1 0 0 0", - "x x x x x x x x i i i i i i i i"; - - read = "0 1 0 1 1 0 0 0 0 0 0 0 1 0 0 0", - "x x x x x x x x o o o o o o o o"; - min_write_delay = 4500; - max_write_delay = 4500; - ; - - memory "efuse" - size = 1; - write = "1 0 1 0 1 1 0 0 1 0 1 0 0 1 0 0", - "x x x x x x x x x x x x x x x i"; - - read = "0 1 0 1 0 0 0 0 0 0 0 0 1 0 0 0", - "x x x x x x x x o o o o o o o o"; - min_write_delay = 4500; - max_write_delay = 4500; - ; - - memory "calibration" - size = 2; - read = "0 0 1 1 1 0 0 0 0 0 0 x x x x x", - "0 0 0 0 0 0 0 a0 o o o o o o o o"; - ; -; - -#------------------------------------------------------------ -# ATmega32u4 -#------------------------------------------------------------ - -part - id = "m32u4"; - desc = "ATmega32U4"; - signature = 0x1e 0x95 0x87; - usbpid = 0x2ff4; - has_jtag = yes; -# stk500_devcode = 0xB2; -# avr910_devcode = 0x43; - chip_erase_delay = 9000; - pagel = 0xD7; - bs2 = 0xA0; - reset = dedicated; - pgm_enable = "1 0 1 0 1 1 0 0 0 1 0 1 0 0 1 1", - "x x x x x x x x x x x x x x x x"; - - chip_erase = "1 0 1 0 1 1 0 0 1 0 0 0 0 0 0 0", - "x x x x x x x x x x x x x x x x"; - - timeout = 200; - stabdelay = 100; - cmdexedelay = 25; - synchloops = 32; - bytedelay = 0; - pollindex = 3; - pollvalue = 0x53; - predelay = 1; - postdelay = 1; - pollmethod = 1; - - pp_controlstack = - 0x0E, 0x1E, 0x0F, 0x1F, 0x2E, 0x3E, 0x2F, 0x3F, - 0x4E, 0x5E, 0x4F, 0x5F, 0x6E, 0x7E, 0x6F, 0x7F, - 0x66, 0x76, 0x67, 0x77, 0x6A, 0x7A, 0x6B, 0x7B, - 0xBE, 0xFD, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00; - hventerstabdelay = 100; - progmodedelay = 0; - latchcycles = 5; - togglevtg = 1; - poweroffdelay = 15; - resetdelayms = 1; - resetdelayus = 0; - hvleavestabdelay = 15; - chiperasepulsewidth = 0; - chiperasepolltimeout = 10; - programfusepulsewidth = 0; - programfusepolltimeout = 5; - programlockpulsewidth = 0; - programlockpolltimeout = 5; - - idr = 0x31; - spmcr = 0x57; - rampz = 0x3b; - allowfullpagebitstream = no; - - ocdrev = 3; - - memory "eeprom" - paged = no; /* leave this "no" */ - page_size = 4; /* for parallel programming */ - size = 1024; - min_write_delay = 9000; - max_write_delay = 9000; - readback_p1 = 0x00; - readback_p2 = 0x00; - read = " 1 0 1 0 0 0 0 0", - " x x x x x a10 a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " o o o o o o o o"; - - write = " 1 1 0 0 0 0 0 0", - " x x x x x a10 a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " i i i i i i i i"; - - loadpage_lo = " 1 1 0 0 0 0 0 1", - " 0 0 0 0 0 0 0 0", - " 0 0 0 0 0 a2 a1 a0", - " i i i i i i i i"; - - writepage = " 1 1 0 0 0 0 1 0", - " 0 0 x x x a10 a9 a8", - " a7 a6 a5 a4 a3 0 0 0", - " x x x x x x x x"; - - mode = 0x41; - delay = 20; - blocksize = 4; - readsize = 256; - ; - - memory "flash" - paged = yes; - size = 32768; - page_size = 128; - num_pages = 256; - min_write_delay = 4500; - max_write_delay = 4500; - readback_p1 = 0x00; - readback_p2 = 0x00; - read_lo = " 0 0 1 0 0 0 0 0", - " 0 a14 a13 a12 a11 a10 a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " o o o o o o o o"; - - read_hi = " 0 0 1 0 1 0 0 0", - " 0 a14 a13 a12 a11 a10 a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " o o o o o o o o"; - - loadpage_lo = " 0 1 0 0 0 0 0 0", - " x x x x x x x x", - " x x a5 a4 a3 a2 a1 a0", - " i i i i i i i i"; - - loadpage_hi = " 0 1 0 0 1 0 0 0", - " x x x x x x x x", - " x x a5 a4 a3 a2 a1 a0", - " i i i i i i i i"; - - writepage = " 0 1 0 0 1 1 0 0", - " a15 a14 a13 a12 a11 a10 a9 a8", - " a7 a6 x x x x x x", - " x x x x x x x x"; - - mode = 0x41; - delay = 6; - blocksize = 128; - readsize = 256; - ; - - memory "lfuse" - size = 1; - write = "1 0 1 0 1 1 0 0 1 0 1 0 0 0 0 0", - "x x x x x x x x i i i i i i i i"; - - read = "0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0", - "x x x x x x x x o o o o o o o o"; - min_write_delay = 9000; - max_write_delay = 9000; - ; - - memory "hfuse" - size = 1; - write = "1 0 1 0 1 1 0 0 1 0 1 0 1 0 0 0", - "x x x x x x x x i i i i i i i i"; - - read = "0 1 0 1 1 0 0 0 0 0 0 0 1 0 0 0", - "x x x x x x x x o o o o o o o o"; - min_write_delay = 9000; - max_write_delay = 9000; - ; - - memory "efuse" - size = 1; - write = "1 0 1 0 1 1 0 0 1 0 1 0 0 1 0 0", - "x x x x x x x x x x x x i i i i"; - - read = "0 1 0 1 0 0 0 0 0 0 0 0 1 0 0 0", - "x x x x x x x x o o o o o o o o"; - min_write_delay = 9000; - max_write_delay = 9000; - ; - - memory "lock" - size = 1; - read = "0 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0", - "x x x x x x x x x x o o o o o o"; - - write = "1 0 1 0 1 1 0 0 1 1 1 x x x x x", - "x x x x x x x x 1 1 i i i i i i"; - min_write_delay = 9000; - max_write_delay = 9000; - ; - - memory "calibration" - size = 1; - read = "0 0 1 1 1 0 0 0 x x x x x x x x", - "0 0 0 0 0 0 0 0 o o o o o o o o"; - ; - - memory "signature" - size = 3; - read = "0 0 1 1 0 0 0 0 x x x x x x x x", - "x x x x x x a1 a0 o o o o o o o o"; - ; - ; - -#------------------------------------------------------------ -# AT90USB646 -#------------------------------------------------------------ - -part - id = "usb646"; - desc = "AT90USB646"; - signature = 0x1e 0x96 0x82; - usbpid = 0x2ff9; - has_jtag = yes; -# stk500_devcode = 0xB2; -# avr910_devcode = 0x43; - chip_erase_delay = 9000; - pagel = 0xD7; - bs2 = 0xA0; - reset = dedicated; - pgm_enable = "1 0 1 0 1 1 0 0 0 1 0 1 0 0 1 1", - "x x x x x x x x x x x x x x x x"; - - chip_erase = "1 0 1 0 1 1 0 0 1 0 0 0 0 0 0 0", - "x x x x x x x x x x x x x x x x"; - - timeout = 200; - stabdelay = 100; - cmdexedelay = 25; - synchloops = 32; - bytedelay = 0; - pollindex = 3; - pollvalue = 0x53; - predelay = 1; - postdelay = 1; - pollmethod = 1; - - pp_controlstack = - 0x0E, 0x1E, 0x0F, 0x1F, 0x2E, 0x3E, 0x2F, 0x3F, - 0x4E, 0x5E, 0x4F, 0x5F, 0x6E, 0x7E, 0x6F, 0x7F, - 0x66, 0x76, 0x67, 0x77, 0x6A, 0x7A, 0x6B, 0x7B, - 0xBE, 0xFD, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00; - hventerstabdelay = 100; - progmodedelay = 0; - latchcycles = 5; - togglevtg = 1; - poweroffdelay = 15; - resetdelayms = 1; - resetdelayus = 0; - hvleavestabdelay = 15; - chiperasepulsewidth = 0; - chiperasepolltimeout = 10; - programfusepulsewidth = 0; - programfusepolltimeout = 5; - programlockpulsewidth = 0; - programlockpolltimeout = 5; - - idr = 0x31; - spmcr = 0x57; - rampz = 0x3b; - allowfullpagebitstream = no; - - ocdrev = 3; - - memory "eeprom" - paged = no; /* leave this "no" */ - page_size = 8; /* for parallel programming */ - size = 2048; - min_write_delay = 9000; - max_write_delay = 9000; - readback_p1 = 0x00; - readback_p2 = 0x00; - read = " 1 0 1 0 0 0 0 0", - " x x x x x a10 a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " o o o o o o o o"; - - write = " 1 1 0 0 0 0 0 0", - " x x x x x a10 a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " i i i i i i i i"; - - loadpage_lo = " 1 1 0 0 0 0 0 1", - " 0 0 0 0 0 0 0 0", - " 0 0 0 0 0 a2 a1 a0", - " i i i i i i i i"; - - writepage = " 1 1 0 0 0 0 1 0", - " 0 0 x x x a10 a9 a8", - " a7 a6 a5 a4 a3 0 0 0", - " x x x x x x x x"; - - mode = 0x41; - delay = 10; - blocksize = 8; - readsize = 256; - ; - - memory "flash" - paged = yes; - size = 65536; - page_size = 256; - num_pages = 256; - min_write_delay = 4500; - max_write_delay = 4500; - readback_p1 = 0x00; - readback_p2 = 0x00; - read_lo = " 0 0 1 0 0 0 0 0", - " 0 a14 a13 a12 a11 a10 a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " o o o o o o o o"; - - read_hi = " 0 0 1 0 1 0 0 0", - " 0 a14 a13 a12 a11 a10 a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " o o o o o o o o"; - - loadpage_lo = " 0 1 0 0 0 0 0 0", - " x x x x x x x x", - " x a6 a5 a4 a3 a2 a1 a0", - " i i i i i i i i"; - - loadpage_hi = " 0 1 0 0 1 0 0 0", - " x x x x x x x x", - " x a6 a5 a4 a3 a2 a1 a0", - " i i i i i i i i"; - - writepage = " 0 1 0 0 1 1 0 0", - " 0 a14 a13 a12 a11 a10 a9 a8", - " a7 x x x x x x x", - " x x x x x x x x"; - - mode = 0x41; - delay = 6; - blocksize = 256; - readsize = 256; - ; - - memory "lfuse" - size = 1; - write = "1 0 1 0 1 1 0 0 1 0 1 0 0 0 0 0", - "x x x x x x x x i i i i i i i i"; - - read = "0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0", - "x x x x x x x x o o o o o o o o"; - min_write_delay = 9000; - max_write_delay = 9000; - ; - - memory "hfuse" - size = 1; - write = "1 0 1 0 1 1 0 0 1 0 1 0 1 0 0 0", - "x x x x x x x x i i i i i i i i"; - - read = "0 1 0 1 1 0 0 0 0 0 0 0 1 0 0 0", - "x x x x x x x x o o o o o o o o"; - min_write_delay = 9000; - max_write_delay = 9000; - ; - - memory "efuse" - size = 1; - write = "1 0 1 0 1 1 0 0 1 0 1 0 0 1 0 0", - "x x x x x x x x x x x x i i i i"; - - read = "0 1 0 1 0 0 0 0 0 0 0 0 1 0 0 0", - "x x x x x x x x o o o o o o o o"; - min_write_delay = 9000; - max_write_delay = 9000; - ; - - memory "lock" - size = 1; - read = "0 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0", - "x x x x x x x x x x o o o o o o"; - - write = "1 0 1 0 1 1 0 0 1 1 1 x x x x x", - "x x x x x x x x 1 1 i i i i i i"; - min_write_delay = 9000; - max_write_delay = 9000; - ; - - memory "calibration" - size = 1; - read = "0 0 1 1 1 0 0 0 x x x x x x x x", - "0 0 0 0 0 0 0 0 o o o o o o o o"; - ; - - memory "signature" - size = 3; - read = "0 0 1 1 0 0 0 0 x x x x x x x x", - "x x x x x x a1 a0 o o o o o o o o"; - ; - ; - -#------------------------------------------------------------ -# AT90USB647 -#------------------------------------------------------------ -# identical to AT90USB646 - -part parent "usb646" - id = "usb647"; - desc = "AT90USB647"; - signature = 0x1e 0x96 0x82; - - ocdrev = 3; - ; - -#------------------------------------------------------------ -# AT90USB1286 -#------------------------------------------------------------ - -part - id = "usb1286"; - desc = "AT90USB1286"; - signature = 0x1e 0x97 0x82; - usbpid = 0x2ffb; - has_jtag = yes; -# stk500_devcode = 0xB2; -# avr910_devcode = 0x43; - chip_erase_delay = 9000; - pagel = 0xD7; - bs2 = 0xA0; - reset = dedicated; - pgm_enable = "1 0 1 0 1 1 0 0 0 1 0 1 0 0 1 1", - "x x x x x x x x x x x x x x x x"; - - chip_erase = "1 0 1 0 1 1 0 0 1 0 0 0 0 0 0 0", - "x x x x x x x x x x x x x x x x"; - - timeout = 200; - stabdelay = 100; - cmdexedelay = 25; - synchloops = 32; - bytedelay = 0; - pollindex = 3; - pollvalue = 0x53; - predelay = 1; - postdelay = 1; - pollmethod = 1; - - pp_controlstack = - 0x0E, 0x1E, 0x0F, 0x1F, 0x2E, 0x3E, 0x2F, 0x3F, - 0x4E, 0x5E, 0x4F, 0x5F, 0x6E, 0x7E, 0x6F, 0x7F, - 0x66, 0x76, 0x67, 0x77, 0x6A, 0x7A, 0x6B, 0x7B, - 0xBE, 0xFD, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00; - hventerstabdelay = 100; - progmodedelay = 0; - latchcycles = 5; - togglevtg = 1; - poweroffdelay = 15; - resetdelayms = 1; - resetdelayus = 0; - hvleavestabdelay = 15; - chiperasepulsewidth = 0; - chiperasepolltimeout = 10; - programfusepulsewidth = 0; - programfusepolltimeout = 5; - programlockpulsewidth = 0; - programlockpolltimeout = 5; - - idr = 0x31; - spmcr = 0x57; - rampz = 0x3b; - allowfullpagebitstream = no; - - ocdrev = 3; - - memory "eeprom" - paged = no; /* leave this "no" */ - page_size = 8; /* for parallel programming */ - size = 4096; - min_write_delay = 9000; - max_write_delay = 9000; - readback_p1 = 0x00; - readback_p2 = 0x00; - read = " 1 0 1 0 0 0 0 0", - " x x x x a11 a10 a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " o o o o o o o o"; - - write = " 1 1 0 0 0 0 0 0", - " x x x x a11 a10 a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " i i i i i i i i"; - - loadpage_lo = " 1 1 0 0 0 0 0 1", - " 0 0 0 0 0 0 0 0", - " 0 0 0 0 0 a2 a1 a0", - " i i i i i i i i"; - - writepage = " 1 1 0 0 0 0 1 0", - " 0 0 x x x a10 a9 a8", - " a7 a6 a5 a4 a3 0 0 0", - " x x x x x x x x"; - - mode = 0x41; - delay = 10; - blocksize = 8; - readsize = 256; - ; - - memory "flash" - paged = yes; - size = 131072; - page_size = 256; - num_pages = 512; - min_write_delay = 4500; - max_write_delay = 4500; - readback_p1 = 0x00; - readback_p2 = 0x00; - read_lo = " 0 0 1 0 0 0 0 0", - "a15 a14 a13 a12 a11 a10 a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " o o o o o o o o"; - - read_hi = " 0 0 1 0 1 0 0 0", - "a15 a14 a13 a12 a11 a10 a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " o o o o o o o o"; - - loadpage_lo = " 0 1 0 0 0 0 0 0", - " x x x x x x x x", - " x a6 a5 a4 a3 a2 a1 a0", - " i i i i i i i i"; - - loadpage_hi = " 0 1 0 0 1 0 0 0", - " x x x x x x x x", - " x a6 a5 a4 a3 a2 a1 a0", - " i i i i i i i i"; - - writepage = " 0 1 0 0 1 1 0 0", - "a15 a14 a13 a12 a11 a10 a9 a8", - " a7 x x x x x x x", - " x x x x x x x x"; - - mode = 0x41; - delay = 6; - blocksize = 256; - readsize = 256; - ; - - memory "lfuse" - size = 1; - write = "1 0 1 0 1 1 0 0 1 0 1 0 0 0 0 0", - "x x x x x x x x i i i i i i i i"; - - read = "0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0", - "x x x x x x x x o o o o o o o o"; - min_write_delay = 9000; - max_write_delay = 9000; - ; - - memory "hfuse" - size = 1; - write = "1 0 1 0 1 1 0 0 1 0 1 0 1 0 0 0", - "x x x x x x x x i i i i i i i i"; - - read = "0 1 0 1 1 0 0 0 0 0 0 0 1 0 0 0", - "x x x x x x x x o o o o o o o o"; - min_write_delay = 9000; - max_write_delay = 9000; - ; - - memory "efuse" - size = 1; - write = "1 0 1 0 1 1 0 0 1 0 1 0 0 1 0 0", - "x x x x x x x x x x x x i i i i"; - - read = "0 1 0 1 0 0 0 0 0 0 0 0 1 0 0 0", - "x x x x x x x x o o o o o o o o"; - min_write_delay = 9000; - max_write_delay = 9000; - ; - - memory "lock" - size = 1; - read = "0 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0", - "x x x x x x x x x x o o o o o o"; - - write = "1 0 1 0 1 1 0 0 1 1 1 x x x x x", - "x x x x x x x x 1 1 i i i i i i"; - min_write_delay = 9000; - max_write_delay = 9000; - ; - - memory "calibration" - size = 1; - read = "0 0 1 1 1 0 0 0 x x x x x x x x", - "0 0 0 0 0 0 0 0 o o o o o o o o"; - ; - - memory "signature" - size = 3; - read = "0 0 1 1 0 0 0 0 x x x x x x x x", - "x x x x x x a1 a0 o o o o o o o o"; - ; - ; - -#------------------------------------------------------------ -# AT90USB1287 -#------------------------------------------------------------ -# identical to AT90USB1286 - -part parent "usb1286" - id = "usb1287"; - desc = "AT90USB1287"; - signature = 0x1e 0x97 0x82; - - ocdrev = 3; - ; - -#------------------------------------------------------------ -# AT90USB162 -#------------------------------------------------------------ - -part - id = "usb162"; - desc = "AT90USB162"; - has_jtag = no; - has_debugwire = yes; - signature = 0x1e 0x94 0x82; - usbpid = 0x2ffa; - chip_erase_delay = 9000; - reset = io; - pgm_enable = "1 0 1 0 1 1 0 0 0 1 0 1 0 0 1 1", - "x x x x x x x x x x x x x x x x"; - chip_erase = "1 0 1 0 1 1 0 0 1 0 0 x x x x x", - "x x x x x x x x x x x x x x x x"; - pagel = 0xD7; - bs2 = 0xC6; - - timeout = 200; - stabdelay = 100; - cmdexedelay = 25; - synchloops = 32; - bytedelay = 0; - pollindex = 3; - pollvalue = 0x53; - predelay = 1; - postdelay = 1; - pollmethod = 1; - pp_controlstack = - 0x0E, 0x1E, 0x0F, 0x1F, 0x2E, 0x3E, 0x2F, 0x3F, - 0x4E, 0x5E, 0x4F, 0x5F, 0x6E, 0x7E, 0x6F, 0x7F, - 0x66, 0x76, 0x67, 0x77, 0x6A, 0x7A, 0x6B, 0x7B, - 0xBE, 0xFD, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00; - hventerstabdelay = 100; - progmodedelay = 0; - latchcycles = 5; - togglevtg = 1; - poweroffdelay = 15; - resetdelayms = 1; - resetdelayus = 0; - hvleavestabdelay = 15; - chiperasepulsewidth = 0; - chiperasepolltimeout = 10; - programfusepulsewidth = 0; - programfusepolltimeout = 5; - programlockpulsewidth = 0; - programlockpolltimeout = 5; - - ocdrev = 1; - - memory "eeprom" - paged = no; /* leave this "no" */ - page_size = 4; /* for parallel programming */ - size = 512; - num_pages = 128; - min_write_delay = 9000; - max_write_delay = 9000; - readback_p1 = 0x00; - readback_p2 = 0x00; - read = " 1 0 1 0 0 0 0 0", - " 0 0 0 0 a11 a10 a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " o o o o o o o o"; - - write = " 1 1 0 0 0 0 0 0", - " 0 0 0 0 a11 a10 a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " i i i i i i i i"; - - loadpage_lo = " 1 1 0 0 0 0 0 1", - " 0 0 0 0 0 0 0 0", - " 0 0 0 0 0 0 a1 a0", - " i i i i i i i i"; - - writepage = " 1 1 0 0 0 0 1 0", - " 0 0 0 0 a11 a10 a9 a8", - " a7 a6 a5 a4 a3 a2 0 0", - " x x x x x x x x"; - - mode = 0x41; - delay = 20; - blocksize = 4; - readsize = 256; - ; - - memory "flash" - paged = yes; - size = 16384; - page_size = 128; - num_pages = 128; - min_write_delay = 4500; - max_write_delay = 4500; - readback_p1 = 0x00; - readback_p2 = 0x00; - read_lo = " 0 0 1 0 0 0 0 0", - "a15 a14 a13 a12 a11 a10 a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " o o o o o o o o"; - - read_hi = " 0 0 1 0 1 0 0 0", - "a15 a14 a13 a12 a11 a10 a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " o o o o o o o o"; - - loadpage_lo = " 0 1 0 0 0 0 0 0", - " x x x x x x x x", - " x x a5 a4 a3 a2 a1 a0", - " i i i i i i i i"; - - loadpage_hi = " 0 1 0 0 1 0 0 0", - " x x x x x x x x", - " x x a5 a4 a3 a2 a1 a0", - " i i i i i i i i"; - - writepage = " 0 1 0 0 1 1 0 0", - "a15 a14 a13 a12 a11 a10 a9 a8", - " a7 a6 x x x x x x", - " x x x x x x x x"; - - mode = 0x41; - delay = 6; - blocksize = 128; - readsize = 256; - ; - - memory "lfuse" - size = 1; - write = "1 0 1 0 1 1 0 0 1 0 1 0 0 0 0 0", - "x x x x x x x x i i i i i i i i"; - - read = "0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0", - "x x x x x x x x o o o o o o o o"; - min_write_delay = 9000; - max_write_delay = 9000; - ; - - memory "hfuse" - size = 1; - write = "1 0 1 0 1 1 0 0 1 0 1 0 1 0 0 0", - "x x x x x x x x i i i i i i i i"; - - read = "0 1 0 1 1 0 0 0 0 0 0 0 1 0 0 0", - "x x x x x x x x o o o o o o o o"; - min_write_delay = 9000; - max_write_delay = 9000; - ; - - memory "efuse" - size = 1; - write = "1 0 1 0 1 1 0 0 1 0 1 0 0 1 0 0", - "x x x x x x x x i i i i i i i i"; - - read = "0 1 0 1 0 0 0 0 0 0 0 0 1 0 0 0", - "x x x x x x x x o o o o o o o o"; - min_write_delay = 9000; - max_write_delay = 9000; - ; - - memory "lock" - size = 1; - read = "0 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0", - "x x x x x x x x x x o o o o o o"; - - write = "1 0 1 0 1 1 0 0 1 1 1 x x x x x", - "x x x x x x x x 1 1 i i i i i i"; - min_write_delay = 9000; - max_write_delay = 9000; - ; - - memory "calibration" - size = 1; - read = "0 0 1 1 1 0 0 0 0 0 0 x x x x x", - "0 0 0 0 0 0 0 0 o o o o o o o o"; - ; - memory "signature" - size = 3; - read = "0 0 1 1 0 0 0 0 0 0 0 x x x x x", - "x x x x x x a1 a0 o o o o o o o o"; - ; - ; - -#------------------------------------------------------------ -# AT90USB82 -#------------------------------------------------------------ -# Changes against AT90USB162 (beside IDs) -# memory "flash" -# size = 8192; -# num_pages = 64; - -part - id = "usb82"; - desc = "AT90USB82"; - has_jtag = no; - has_debugwire = yes; - signature = 0x1e 0x93 0x82; - usbpid = 0x2ff7; - chip_erase_delay = 9000; - reset = io; - pgm_enable = "1 0 1 0 1 1 0 0 0 1 0 1 0 0 1 1", - "x x x x x x x x x x x x x x x x"; - chip_erase = "1 0 1 0 1 1 0 0 1 0 0 x x x x x", - "x x x x x x x x x x x x x x x x"; - pagel = 0xD7; - bs2 = 0xC6; - - timeout = 200; - stabdelay = 100; - cmdexedelay = 25; - synchloops = 32; - bytedelay = 0; - pollindex = 3; - pollvalue = 0x53; - predelay = 1; - postdelay = 1; - pollmethod = 1; - pp_controlstack = - 0x0E, 0x1E, 0x0F, 0x1F, 0x2E, 0x3E, 0x2F, 0x3F, - 0x4E, 0x5E, 0x4F, 0x5F, 0x6E, 0x7E, 0x6F, 0x7F, - 0x66, 0x76, 0x67, 0x77, 0x6A, 0x7A, 0x6B, 0x7B, - 0xBE, 0xFD, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00; - hventerstabdelay = 100; - progmodedelay = 0; - latchcycles = 5; - togglevtg = 1; - poweroffdelay = 15; - resetdelayms = 1; - resetdelayus = 0; - hvleavestabdelay = 15; - chiperasepulsewidth = 0; - chiperasepolltimeout = 10; - programfusepulsewidth = 0; - programfusepolltimeout = 5; - programlockpulsewidth = 0; - programlockpolltimeout = 5; - - ocdrev = 1; - - memory "eeprom" - paged = no; /* leave this "no" */ - page_size = 4; /* for parallel programming */ - size = 512; - num_pages = 128; - min_write_delay = 9000; - max_write_delay = 9000; - readback_p1 = 0x00; - readback_p2 = 0x00; - read = " 1 0 1 0 0 0 0 0", - " 0 0 0 0 a11 a10 a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " o o o o o o o o"; - - write = " 1 1 0 0 0 0 0 0", - " 0 0 0 0 a11 a10 a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " i i i i i i i i"; - - loadpage_lo = " 1 1 0 0 0 0 0 1", - " 0 0 0 0 0 0 0 0", - " 0 0 0 0 0 0 a1 a0", - " i i i i i i i i"; - - writepage = " 1 1 0 0 0 0 1 0", - " 0 0 0 0 a11 a10 a9 a8", - " a7 a6 a5 a4 a3 a2 0 0", - " x x x x x x x x"; - - mode = 0x41; - delay = 20; - blocksize = 4; - readsize = 256; - ; - - memory "flash" - paged = yes; - size = 8192; - page_size = 128; - num_pages = 64; - min_write_delay = 4500; - max_write_delay = 4500; - readback_p1 = 0x00; - readback_p2 = 0x00; - read_lo = " 0 0 1 0 0 0 0 0", - "a15 a14 a13 a12 a11 a10 a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " o o o o o o o o"; - - read_hi = " 0 0 1 0 1 0 0 0", - "a15 a14 a13 a12 a11 a10 a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " o o o o o o o o"; - - loadpage_lo = " 0 1 0 0 0 0 0 0", - " x x x x x x x x", - " x x a5 a4 a3 a2 a1 a0", - " i i i i i i i i"; - - loadpage_hi = " 0 1 0 0 1 0 0 0", - " x x x x x x x x", - " x x a5 a4 a3 a2 a1 a0", - " i i i i i i i i"; - - writepage = " 0 1 0 0 1 1 0 0", - "a15 a14 a13 a12 a11 a10 a9 a8", - " a7 a6 x x x x x x", - " x x x x x x x x"; - - mode = 0x41; - delay = 6; - blocksize = 128; - readsize = 256; - ; - - memory "lfuse" - size = 1; - write = "1 0 1 0 1 1 0 0 1 0 1 0 0 0 0 0", - "x x x x x x x x i i i i i i i i"; - - read = "0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0", - "x x x x x x x x o o o o o o o o"; - min_write_delay = 9000; - max_write_delay = 9000; - ; - - memory "hfuse" - size = 1; - write = "1 0 1 0 1 1 0 0 1 0 1 0 1 0 0 0", - "x x x x x x x x i i i i i i i i"; - - read = "0 1 0 1 1 0 0 0 0 0 0 0 1 0 0 0", - "x x x x x x x x o o o o o o o o"; - min_write_delay = 9000; - max_write_delay = 9000; - ; - - memory "efuse" - size = 1; - write = "1 0 1 0 1 1 0 0 1 0 1 0 0 1 0 0", - "x x x x x x x x i i i i i i i i"; - - read = "0 1 0 1 0 0 0 0 0 0 0 0 1 0 0 0", - "x x x x x x x x o o o o o o o o"; - min_write_delay = 9000; - max_write_delay = 9000; - ; - - memory "lock" - size = 1; - read = "0 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0", - "x x x x x x x x x x o o o o o o"; - - write = "1 0 1 0 1 1 0 0 1 1 1 x x x x x", - "x x x x x x x x 1 1 i i i i i i"; - min_write_delay = 9000; - max_write_delay = 9000; - ; - - memory "calibration" - size = 1; - read = "0 0 1 1 1 0 0 0 0 0 0 x x x x x", - "0 0 0 0 0 0 0 0 o o o o o o o o"; - ; - memory "signature" - size = 3; - read = "0 0 1 1 0 0 0 0 0 0 0 x x x x x", - "x x x x x x a1 a0 o o o o o o o o"; - ; - ; - -#------------------------------------------------------------ -# ATmega32U2 -#------------------------------------------------------------ -# Changes against AT90USB162 (beside IDs) -# memory "flash" -# size = 32768; -# num_pages = 256; -# memory "eeprom" -# size = 1024; -# num_pages = 256; -part - id = "m32u2"; - desc = "ATmega32U2"; - has_jtag = no; - has_debugwire = yes; - signature = 0x1e 0x95 0x8a; - usbpid = 0x2ff0; - chip_erase_delay = 9000; - reset = io; - pgm_enable = "1 0 1 0 1 1 0 0 0 1 0 1 0 0 1 1", - "x x x x x x x x x x x x x x x x"; - chip_erase = "1 0 1 0 1 1 0 0 1 0 0 x x x x x", - "x x x x x x x x x x x x x x x x"; - pagel = 0xD7; - bs2 = 0xC6; - - timeout = 200; - stabdelay = 100; - cmdexedelay = 25; - synchloops = 32; - bytedelay = 0; - pollindex = 3; - pollvalue = 0x53; - predelay = 1; - postdelay = 1; - pollmethod = 1; - pp_controlstack = - 0x0E, 0x1E, 0x0F, 0x1F, 0x2E, 0x3E, 0x2F, 0x3F, - 0x4E, 0x5E, 0x4F, 0x5F, 0x6E, 0x7E, 0x6F, 0x7F, - 0x66, 0x76, 0x67, 0x77, 0x6A, 0x7A, 0x6B, 0x7B, - 0xBE, 0xFD, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00; - hventerstabdelay = 100; - progmodedelay = 0; - latchcycles = 5; - togglevtg = 1; - poweroffdelay = 15; - resetdelayms = 1; - resetdelayus = 0; - hvleavestabdelay = 15; - chiperasepulsewidth = 0; - chiperasepolltimeout = 10; - programfusepulsewidth = 0; - programfusepolltimeout = 5; - programlockpulsewidth = 0; - programlockpolltimeout = 5; - - ocdrev = 1; - - memory "eeprom" - paged = no; /* leave this "no" */ - page_size = 4; /* for parallel programming */ - size = 1024; - num_pages = 256; - min_write_delay = 9000; - max_write_delay = 9000; - readback_p1 = 0x00; - readback_p2 = 0x00; - read = " 1 0 1 0 0 0 0 0", - " 0 0 0 0 a11 a10 a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " o o o o o o o o"; - - write = " 1 1 0 0 0 0 0 0", - " 0 0 0 0 a11 a10 a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " i i i i i i i i"; - - loadpage_lo = " 1 1 0 0 0 0 0 1", - " 0 0 0 0 0 0 0 0", - " 0 0 0 0 0 0 a1 a0", - " i i i i i i i i"; - - writepage = " 1 1 0 0 0 0 1 0", - " 0 0 0 0 a11 a10 a9 a8", - " a7 a6 a5 a4 a3 a2 0 0", - " x x x x x x x x"; - - mode = 0x41; - delay = 20; - blocksize = 4; - readsize = 256; - ; - - memory "flash" - paged = yes; - size = 32768; - page_size = 128; - num_pages = 256; - min_write_delay = 4500; - max_write_delay = 4500; - readback_p1 = 0x00; - readback_p2 = 0x00; - read_lo = " 0 0 1 0 0 0 0 0", - "a15 a14 a13 a12 a11 a10 a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " o o o o o o o o"; - - read_hi = " 0 0 1 0 1 0 0 0", - "a15 a14 a13 a12 a11 a10 a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " o o o o o o o o"; - - loadpage_lo = " 0 1 0 0 0 0 0 0", - " x x x x x x x x", - " x x a5 a4 a3 a2 a1 a0", - " i i i i i i i i"; - - loadpage_hi = " 0 1 0 0 1 0 0 0", - " x x x x x x x x", - " x x a5 a4 a3 a2 a1 a0", - " i i i i i i i i"; - - writepage = " 0 1 0 0 1 1 0 0", - "a15 a14 a13 a12 a11 a10 a9 a8", - " a7 a6 x x x x x x", - " x x x x x x x x"; - - mode = 0x41; - delay = 6; - blocksize = 128; - readsize = 256; - ; - - memory "lfuse" - size = 1; - write = "1 0 1 0 1 1 0 0 1 0 1 0 0 0 0 0", - "x x x x x x x x i i i i i i i i"; - - read = "0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0", - "x x x x x x x x o o o o o o o o"; - min_write_delay = 9000; - max_write_delay = 9000; - ; - - memory "hfuse" - size = 1; - write = "1 0 1 0 1 1 0 0 1 0 1 0 1 0 0 0", - "x x x x x x x x i i i i i i i i"; - - read = "0 1 0 1 1 0 0 0 0 0 0 0 1 0 0 0", - "x x x x x x x x o o o o o o o o"; - min_write_delay = 9000; - max_write_delay = 9000; - ; - - memory "efuse" - size = 1; - write = "1 0 1 0 1 1 0 0 1 0 1 0 0 1 0 0", - "x x x x x x x x i i i i i i i i"; - - read = "0 1 0 1 0 0 0 0 0 0 0 0 1 0 0 0", - "x x x x x x x x o o o o o o o o"; - min_write_delay = 9000; - max_write_delay = 9000; - ; - - memory "lock" - size = 1; - read = "0 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0", - "x x x x x x x x x x o o o o o o"; - - write = "1 0 1 0 1 1 0 0 1 1 1 x x x x x", - "x x x x x x x x 1 1 i i i i i i"; - min_write_delay = 9000; - max_write_delay = 9000; - ; - - memory "calibration" - size = 1; - read = "0 0 1 1 1 0 0 0 0 0 0 x x x x x", - "0 0 0 0 0 0 0 0 o o o o o o o o"; - ; - memory "signature" - size = 3; - read = "0 0 1 1 0 0 0 0 0 0 0 x x x x x", - "x x x x x x a1 a0 o o o o o o o o"; - ; - ; -#------------------------------------------------------------ -# ATmega16U2 -#------------------------------------------------------------ -# Changes against ATmega32U2 (beside IDs) -# memory "flash" -# size = 16384; -# num_pages = 128; -# memory "eeprom" -# size = 512; -# num_pages = 128; -part - id = "m16u2"; - desc = "ATmega16U2"; - has_jtag = no; - has_debugwire = yes; - signature = 0x1e 0x94 0x89; - usbpid = 0x2fef; - chip_erase_delay = 9000; - reset = io; - pgm_enable = "1 0 1 0 1 1 0 0 0 1 0 1 0 0 1 1", - "x x x x x x x x x x x x x x x x"; - chip_erase = "1 0 1 0 1 1 0 0 1 0 0 x x x x x", - "x x x x x x x x x x x x x x x x"; - pagel = 0xD7; - bs2 = 0xC6; - - timeout = 200; - stabdelay = 100; - cmdexedelay = 25; - synchloops = 32; - bytedelay = 0; - pollindex = 3; - pollvalue = 0x53; - predelay = 1; - postdelay = 1; - pollmethod = 1; - pp_controlstack = - 0x0E, 0x1E, 0x0F, 0x1F, 0x2E, 0x3E, 0x2F, 0x3F, - 0x4E, 0x5E, 0x4F, 0x5F, 0x6E, 0x7E, 0x6F, 0x7F, - 0x66, 0x76, 0x67, 0x77, 0x6A, 0x7A, 0x6B, 0x7B, - 0xBE, 0xFD, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00; - hventerstabdelay = 100; - progmodedelay = 0; - latchcycles = 5; - togglevtg = 1; - poweroffdelay = 15; - resetdelayms = 1; - resetdelayus = 0; - hvleavestabdelay = 15; - chiperasepulsewidth = 0; - chiperasepolltimeout = 10; - programfusepulsewidth = 0; - programfusepolltimeout = 5; - programlockpulsewidth = 0; - programlockpolltimeout = 5; - - ocdrev = 1; - - memory "eeprom" - paged = no; /* leave this "no" */ - page_size = 4; /* for parallel programming */ - size = 512; - num_pages = 128; - min_write_delay = 9000; - max_write_delay = 9000; - readback_p1 = 0x00; - readback_p2 = 0x00; - read = " 1 0 1 0 0 0 0 0", - " 0 0 0 0 a11 a10 a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " o o o o o o o o"; - - write = " 1 1 0 0 0 0 0 0", - " 0 0 0 0 a11 a10 a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " i i i i i i i i"; - - loadpage_lo = " 1 1 0 0 0 0 0 1", - " 0 0 0 0 0 0 0 0", - " 0 0 0 0 0 0 a1 a0", - " i i i i i i i i"; - - writepage = " 1 1 0 0 0 0 1 0", - " 0 0 0 0 a11 a10 a9 a8", - " a7 a6 a5 a4 a3 a2 0 0", - " x x x x x x x x"; - - mode = 0x41; - delay = 20; - blocksize = 4; - readsize = 256; - ; - - memory "flash" - paged = yes; - size = 16384; - page_size = 128; - num_pages = 128; - min_write_delay = 4500; - max_write_delay = 4500; - readback_p1 = 0x00; - readback_p2 = 0x00; - read_lo = " 0 0 1 0 0 0 0 0", - "a15 a14 a13 a12 a11 a10 a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " o o o o o o o o"; - - read_hi = " 0 0 1 0 1 0 0 0", - "a15 a14 a13 a12 a11 a10 a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " o o o o o o o o"; - - loadpage_lo = " 0 1 0 0 0 0 0 0", - " x x x x x x x x", - " x x a5 a4 a3 a2 a1 a0", - " i i i i i i i i"; - - loadpage_hi = " 0 1 0 0 1 0 0 0", - " x x x x x x x x", - " x x a5 a4 a3 a2 a1 a0", - " i i i i i i i i"; - - writepage = " 0 1 0 0 1 1 0 0", - "a15 a14 a13 a12 a11 a10 a9 a8", - " a7 a6 x x x x x x", - " x x x x x x x x"; - - mode = 0x41; - delay = 6; - blocksize = 128; - readsize = 256; - ; - - memory "lfuse" - size = 1; - write = "1 0 1 0 1 1 0 0 1 0 1 0 0 0 0 0", - "x x x x x x x x i i i i i i i i"; - - read = "0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0", - "x x x x x x x x o o o o o o o o"; - min_write_delay = 9000; - max_write_delay = 9000; - ; - - memory "hfuse" - size = 1; - write = "1 0 1 0 1 1 0 0 1 0 1 0 1 0 0 0", - "x x x x x x x x i i i i i i i i"; - - read = "0 1 0 1 1 0 0 0 0 0 0 0 1 0 0 0", - "x x x x x x x x o o o o o o o o"; - min_write_delay = 9000; - max_write_delay = 9000; - ; - - memory "efuse" - size = 1; - write = "1 0 1 0 1 1 0 0 1 0 1 0 0 1 0 0", - "x x x x x x x x i i i i i i i i"; - - read = "0 1 0 1 0 0 0 0 0 0 0 0 1 0 0 0", - "x x x x x x x x o o o o o o o o"; - min_write_delay = 9000; - max_write_delay = 9000; - ; - - memory "lock" - size = 1; - read = "0 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0", - "x x x x x x x x x x o o o o o o"; - - write = "1 0 1 0 1 1 0 0 1 1 1 x x x x x", - "x x x x x x x x 1 1 i i i i i i"; - min_write_delay = 9000; - max_write_delay = 9000; - ; - - memory "calibration" - size = 1; - read = "0 0 1 1 1 0 0 0 0 0 0 x x x x x", - "0 0 0 0 0 0 0 0 o o o o o o o o"; - ; - memory "signature" - size = 3; - read = "0 0 1 1 0 0 0 0 0 0 0 x x x x x", - "x x x x x x a1 a0 o o o o o o o o"; - ; - ; - -#------------------------------------------------------------ -# ATmega8U2 -#------------------------------------------------------------ -# Changes against ATmega16U2 (beside IDs) -# memory "flash" -# size = 8192; -# page_size = 64; -# blocksize = 64; - -part - id = "m8u2"; - desc = "ATmega8U2"; - has_jtag = no; - has_debugwire = yes; - signature = 0x1e 0x93 0x89; - usbpid = 0x2fee; - chip_erase_delay = 9000; - reset = io; - pgm_enable = "1 0 1 0 1 1 0 0 0 1 0 1 0 0 1 1", - "x x x x x x x x x x x x x x x x"; - chip_erase = "1 0 1 0 1 1 0 0 1 0 0 x x x x x", - "x x x x x x x x x x x x x x x x"; - pagel = 0xD7; - bs2 = 0xC6; - - timeout = 200; - stabdelay = 100; - cmdexedelay = 25; - synchloops = 32; - bytedelay = 0; - pollindex = 3; - pollvalue = 0x53; - predelay = 1; - postdelay = 1; - pollmethod = 1; - pp_controlstack = - 0x0E, 0x1E, 0x0F, 0x1F, 0x2E, 0x3E, 0x2F, 0x3F, - 0x4E, 0x5E, 0x4F, 0x5F, 0x6E, 0x7E, 0x6F, 0x7F, - 0x66, 0x76, 0x67, 0x77, 0x6A, 0x7A, 0x6B, 0x7B, - 0xBE, 0xFD, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00; - hventerstabdelay = 100; - progmodedelay = 0; - latchcycles = 5; - togglevtg = 1; - poweroffdelay = 15; - resetdelayms = 1; - resetdelayus = 0; - hvleavestabdelay = 15; - chiperasepulsewidth = 0; - chiperasepolltimeout = 10; - programfusepulsewidth = 0; - programfusepolltimeout = 5; - programlockpulsewidth = 0; - programlockpolltimeout = 5; - - ocdrev = 1; - - memory "eeprom" - paged = no; /* leave this "no" */ - page_size = 4; /* for parallel programming */ - size = 512; - num_pages = 128; - min_write_delay = 9000; - max_write_delay = 9000; - readback_p1 = 0x00; - readback_p2 = 0x00; - read = " 1 0 1 0 0 0 0 0", - " 0 0 0 0 a11 a10 a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " o o o o o o o o"; - - write = " 1 1 0 0 0 0 0 0", - " 0 0 0 0 a11 a10 a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " i i i i i i i i"; - - loadpage_lo = " 1 1 0 0 0 0 0 1", - " 0 0 0 0 0 0 0 0", - " 0 0 0 0 0 0 a1 a0", - " i i i i i i i i"; - - writepage = " 1 1 0 0 0 0 1 0", - " 0 0 0 0 a11 a10 a9 a8", - " a7 a6 a5 a4 a3 a2 0 0", - " x x x x x x x x"; - - mode = 0x41; - delay = 20; - blocksize = 4; - readsize = 256; - ; - - memory "flash" - paged = yes; - size = 8192; - page_size = 128; - num_pages = 64; - min_write_delay = 4500; - max_write_delay = 4500; - readback_p1 = 0x00; - readback_p2 = 0x00; - read_lo = " 0 0 1 0 0 0 0 0", - "a15 a14 a13 a12 a11 a10 a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " o o o o o o o o"; - - read_hi = " 0 0 1 0 1 0 0 0", - "a15 a14 a13 a12 a11 a10 a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " o o o o o o o o"; - - loadpage_lo = " 0 1 0 0 0 0 0 0", - " x x x x x x x x", - " x x a5 a4 a3 a2 a1 a0", - " i i i i i i i i"; - - loadpage_hi = " 0 1 0 0 1 0 0 0", - " x x x x x x x x", - " x x a5 a4 a3 a2 a1 a0", - " i i i i i i i i"; - - writepage = " 0 1 0 0 1 1 0 0", - "a15 a14 a13 a12 a11 a10 a9 a8", - " a7 a6 x x x x x x", - " x x x x x x x x"; - - mode = 0x41; - delay = 6; - blocksize = 128; - readsize = 256; - ; - - memory "lfuse" - size = 1; - write = "1 0 1 0 1 1 0 0 1 0 1 0 0 0 0 0", - "x x x x x x x x i i i i i i i i"; - - read = "0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0", - "x x x x x x x x o o o o o o o o"; - min_write_delay = 9000; - max_write_delay = 9000; - ; - - memory "hfuse" - size = 1; - write = "1 0 1 0 1 1 0 0 1 0 1 0 1 0 0 0", - "x x x x x x x x i i i i i i i i"; - - read = "0 1 0 1 1 0 0 0 0 0 0 0 1 0 0 0", - "x x x x x x x x o o o o o o o o"; - min_write_delay = 9000; - max_write_delay = 9000; - ; - - memory "efuse" - size = 1; - write = "1 0 1 0 1 1 0 0 1 0 1 0 0 1 0 0", - "x x x x x x x x i i i i i i i i"; - - read = "0 1 0 1 0 0 0 0 0 0 0 0 1 0 0 0", - "x x x x x x x x o o o o o o o o"; - min_write_delay = 9000; - max_write_delay = 9000; - ; - - memory "lock" - size = 1; - read = "0 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0", - "x x x x x x x x x x o o o o o o"; - - write = "1 0 1 0 1 1 0 0 1 1 1 x x x x x", - "x x x x x x x x 1 1 i i i i i i"; - min_write_delay = 9000; - max_write_delay = 9000; - ; - - memory "calibration" - size = 1; - read = "0 0 1 1 1 0 0 0 0 0 0 x x x x x", - "0 0 0 0 0 0 0 0 o o o o o o o o"; - ; - memory "signature" - size = 3; - read = "0 0 1 1 0 0 0 0 0 0 0 x x x x x", - "x x x x x x a1 a0 o o o o o o o o"; - ; - ; -#------------------------------------------------------------ -# ATmega325 -#------------------------------------------------------------ - -part - id = "m325"; - desc = "ATmega325"; - signature = 0x1e 0x95 0x05; - has_jtag = yes; -# stk500_devcode = 0x??; # No STK500v1 support? -# avr910_devcode = 0x??; # Try the ATmega16 one - avr910_devcode = 0x74; - pagel = 0xd7; - bs2 = 0xa0; - chip_erase_delay = 9000; - pgm_enable = "1 0 1 0 1 1 0 0 0 1 0 1 0 0 1 1", - "0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0"; - - chip_erase = "1 0 1 0 1 1 0 0 1 0 0 0 0 0 0 0", - "0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0"; - - timeout = 200; - stabdelay = 100; - cmdexedelay = 25; - synchloops = 32; - bytedelay = 0; - pollindex = 3; - pollvalue = 0x53; - predelay = 1; - postdelay = 1; - pollmethod = 1; - - pp_controlstack = - 0x0E, 0x1E, 0x0F, 0x1F, 0x2E, 0x3E, 0x2F, 0x3F, - 0x4E, 0x5E, 0x4F, 0x5F, 0x6E, 0x7E, 0x6F, 0x7F, - 0x66, 0x76, 0x67, 0x77, 0x6A, 0x7A, 0x6B, 0x7B, - 0xBE, 0xFD, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00; - hventerstabdelay = 100; - progmodedelay = 0; - latchcycles = 5; - togglevtg = 1; - poweroffdelay = 15; - resetdelayms = 1; - resetdelayus = 0; - hvleavestabdelay = 15; - chiperasepulsewidth = 0; - chiperasepolltimeout = 10; - programfusepulsewidth = 0; - programfusepolltimeout = 5; - programlockpulsewidth = 0; - programlockpolltimeout = 5; - - idr = 0x31; - spmcr = 0x57; - allowfullpagebitstream = no; - - ocdrev = 3; - - memory "eeprom" - paged = no; /* leave this "no" */ - page_size = 4; /* for parallel programming */ - size = 1024; - min_write_delay = 9000; - max_write_delay = 9000; - readback_p1 = 0xff; - readback_p2 = 0xff; - read = " 1 0 1 0 0 0 0 0", - " 0 0 0 0 0 0 a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " o o o o o o o o"; - - write = " 1 1 0 0 0 0 0 0", - " 0 0 0 0 0 0 a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " i i i i i i i i"; - - loadpage_lo = " 1 1 0 0 0 0 0 1", - " 0 0 0 0 0 0 0 0", - " 0 0 0 0 0 0 a1 a0", - " i i i i i i i i"; - - writepage = " 1 1 0 0 0 0 1 0", - " 0 0 0 0 0 0 a9 a8", - " a7 a6 a5 a4 a3 a2 0 0", - " x x x x x x x x"; - - mode = 0x41; - delay = 10; - blocksize = 4; - readsize = 256; - ; - - memory "flash" - paged = yes; - size = 32768; - page_size = 128; - num_pages = 256; - min_write_delay = 4500; - max_write_delay = 4500; - readback_p1 = 0xff; - readback_p2 = 0xff; - read_lo = " 0 0 1 0 0 0 0 0", - " 0 a14 a13 a12 a11 a10 a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " o o o o o o o o"; - - read_hi = " 0 0 1 0 1 0 0 0", - " 0 a14 a13 a12 a11 a10 a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " o o o o o o o o"; - - loadpage_lo = " 0 1 0 0 0 0 0 0", - " 0 0 0 0 0 0 0 0", - " a7 a6 a5 a4 a3 a2 a1 a0", - " i i i i i i i i"; - - loadpage_hi = " 0 1 0 0 1 0 0 0", - " 0 0 0 0 0 0 0 0", - " a7 a6 a5 a4 a3 a2 a1 a0", - " i i i i i i i i"; - - writepage = " 0 1 0 0 1 1 0 0", - " 0 a14 a13 a12 a11 a10 a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " x x x x x x x x"; - - mode = 0x41; - delay = 10; - blocksize = 128; - readsize = 256; - ; - - memory "lock" - size = 1; - read = "0 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0", - "x x x x x x x x x x o o o o o o"; - - write = "1 0 1 0 1 1 0 0 1 1 1 0 0 0 0 0", - "0 0 0 0 0 0 0 0 1 1 i i i i i i"; - min_write_delay = 9000; - max_write_delay = 9000; - ; - - memory "lfuse" - size = 1; - read = "0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0", - "0 0 0 0 0 0 0 0 o o o o o o o o"; - - write = "1 0 1 0 1 1 0 0 1 0 1 0 0 0 0 0", - "0 0 0 0 0 0 0 0 i i i i i i i i"; - min_write_delay = 9000; - max_write_delay = 9000; - ; - - memory "hfuse" - size = 1; - read = "0 1 0 1 1 0 0 0 0 0 0 0 1 0 0 0", - "0 0 0 0 0 0 0 0 o o o o o o o o"; - - write = "1 0 1 0 1 1 0 0 1 0 1 0 1 0 0 0", - "0 0 0 0 0 0 0 0 i i i i i i i i"; - min_write_delay = 9000; - max_write_delay = 9000; - ; - - memory "efuse" - size = 1; - - read = "0 1 0 1 0 0 0 0 0 0 0 0 1 0 0 0", - "0 0 0 0 0 0 0 0 o o o o o o o o"; - - write = "1 0 1 0 1 1 0 0 1 0 1 0 0 1 0 0", - "0 0 0 0 0 0 0 0 1 1 1 1 1 i i i"; - min_write_delay = 9000; - max_write_delay = 9000; - ; - - memory "signature" - size = 3; - read = "0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0", - "0 0 0 0 0 0 a1 a0 o o o o o o o o"; - ; - - memory "calibration" - size = 1; - - read = "0 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0", - "0 0 0 0 0 0 0 0 o o o o o o o o"; - ; - ; - -#------------------------------------------------------------ -# ATmega645 -#------------------------------------------------------------ - -part - id = "m645"; - desc = "ATmega645"; - signature = 0x1E 0x96 0x05; - has_jtag = yes; -# stk500_devcode = 0x??; # No STK500v1 support? -# avr910_devcode = 0x??; # Try the ATmega16 one - avr910_devcode = 0x74; - pagel = 0xd7; - bs2 = 0xa0; - chip_erase_delay = 9000; - pgm_enable = "1 0 1 0 1 1 0 0 0 1 0 1 0 0 1 1", - "0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0"; - - chip_erase = "1 0 1 0 1 1 0 0 1 0 0 0 0 0 0 0", - "0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0"; - - timeout = 200; - stabdelay = 100; - cmdexedelay = 25; - synchloops = 32; - bytedelay = 0; - pollindex = 3; - pollvalue = 0x53; - predelay = 1; - postdelay = 1; - pollmethod = 1; - - pp_controlstack = - 0x0E, 0x1E, 0x0F, 0x1F, 0x2E, 0x3E, 0x2F, 0x3F, - 0x4E, 0x5E, 0x4F, 0x5F, 0x6E, 0x7E, 0x6F, 0x7F, - 0x66, 0x76, 0x67, 0x77, 0x6A, 0x7A, 0x6B, 0x7B, - 0xBE, 0xFD, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00; - hventerstabdelay = 100; - progmodedelay = 0; - latchcycles = 5; - togglevtg = 1; - poweroffdelay = 15; - resetdelayms = 1; - resetdelayus = 0; - hvleavestabdelay = 15; - chiperasepulsewidth = 0; - chiperasepolltimeout = 10; - programfusepulsewidth = 0; - programfusepolltimeout = 5; - programlockpulsewidth = 0; - programlockpolltimeout = 5; - - idr = 0x31; - spmcr = 0x57; - allowfullpagebitstream = no; - - ocdrev = 3; - - memory "eeprom" - paged = no; /* leave this "no" */ - page_size = 8; /* for parallel programming */ - size = 2048; - min_write_delay = 9000; - max_write_delay = 9000; - readback_p1 = 0xff; - readback_p2 = 0xff; - read = " 1 0 1 0 0 0 0 0", - " 0 0 0 0 0 a10 a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " o o o o o o o o"; - - write = " 1 1 0 0 0 0 0 0", - " 0 0 0 0 0 a10 a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " i i i i i i i i"; - - loadpage_lo = " 1 1 0 0 0 0 0 1", - " 0 0 0 0 0 0 0 0", - " 0 0 0 0 0 a2 a1 a0", - " i i i i i i i i"; - - writepage = " 1 1 0 0 0 0 1 0", - " 0 0 0 0 0 a10 a9 a8", - " a7 a6 a5 a4 a3 0 0 0", - " x x x x x x x x"; - - mode = 0x41; - delay = 10; - blocksize = 8; - readsize = 256; - ; - - memory "flash" - paged = yes; - size = 65536; - page_size = 256; - num_pages = 256; - min_write_delay = 4500; - max_write_delay = 4500; - readback_p1 = 0xff; - readback_p2 = 0xff; - read_lo = " 0 0 1 0 0 0 0 0", - " a15 a14 a13 a12 a11 a10 a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " o o o o o o o o"; - - read_hi = " 0 0 1 0 1 0 0 0", - " a15 a14 a13 a12 a11 a10 a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " o o o o o o o o"; - - loadpage_lo = " 0 1 0 0 0 0 0 0", - " 0 0 0 0 0 0 0 0", - " a7 a6 a5 a4 a3 a2 a1 a0", - " i i i i i i i i"; - - loadpage_hi = " 0 1 0 0 1 0 0 0", - " 0 0 0 0 0 0 0 0", - " a7 a6 a5 a4 a3 a2 a1 a0", - " i i i i i i i i"; - - writepage = " 0 1 0 0 1 1 0 0", - " a15 a14 a13 a12 a11 a10 a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " 0 0 0 0 0 0 0 0"; - - mode = 0x41; - delay = 10; - blocksize = 128; - readsize = 256; - ; - - memory "lock" - size = 1; - read = "0 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0", - "x x x x x x x x x x o o o o o o"; - - write = "1 0 1 0 1 1 0 0 1 1 1 0 0 0 0 0", - "0 0 0 0 0 0 0 0 1 1 i i i i i i"; - min_write_delay = 9000; - max_write_delay = 9000; - ; - - memory "lfuse" - size = 1; - read = "0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0", - "0 0 0 0 0 0 0 0 o o o o o o o o"; - - write = "1 0 1 0 1 1 0 0 1 0 1 0 0 0 0 0", - "0 0 0 0 0 0 0 0 i i i i i i i i"; - min_write_delay = 9000; - max_write_delay = 9000; - ; - - memory "hfuse" - size = 1; - read = "0 1 0 1 1 0 0 0 0 0 0 0 1 0 0 0", - "0 0 0 0 0 0 0 0 o o o o o o o o"; - - write = "1 0 1 0 1 1 0 0 1 0 1 0 1 0 0 0", - "0 0 0 0 0 0 0 0 i i i i i i i i"; - min_write_delay = 9000; - max_write_delay = 9000; - ; - - memory "efuse" - size = 1; - - read = "0 1 0 1 0 0 0 0 0 0 0 0 1 0 0 0", - "0 0 0 0 0 0 0 0 o o o o o o o o"; - - write = "1 0 1 0 1 1 0 0 1 0 1 0 0 1 0 0", - "0 0 0 0 0 0 0 0 1 1 1 1 1 i i i"; - min_write_delay = 9000; - max_write_delay = 9000; - ; - - memory "signature" - size = 3; - read = "0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0", - "0 0 0 0 0 0 a1 a0 o o o o o o o o"; - ; - - memory "calibration" - size = 1; - - read = "0 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0", - "0 0 0 0 0 0 0 0 o o o o o o o o"; - ; - ; - -#------------------------------------------------------------ -# ATmega3250 -#------------------------------------------------------------ - -part parent "m325" - id = "m3250"; - desc = "ATmega3250"; - signature = 0x1E 0x95 0x06; - - ocdrev = 3; - ; - -#------------------------------------------------------------ -# ATmega6450 -#------------------------------------------------------------ - -part parent "m645" - id = "m6450"; - desc = "ATmega6450"; - signature = 0x1E 0x96 0x06; - - ocdrev = 3; - ; - -#------------------------------------------------------------ -# AVR XMEGA family common values -#------------------------------------------------------------ - -part - id = ".xmega"; - desc = "AVR XMEGA family common values"; - has_pdi = yes; - nvm_base = 0x01c0; - mcu_base = 0x0090; - - memory "signature" - size = 3; - offset = 0x1000090; - ; - - memory "prodsig" - size = 0x32; - offset = 0x8e0200; - page_size = 0x32; - readsize = 0x32; - ; - - memory "fuse1" - size = 1; - offset = 0x8f0021; - ; - - memory "fuse2" - size = 1; - offset = 0x8f0022; - ; - - memory "fuse4" - size = 1; - offset = 0x8f0024; - ; - - memory "fuse5" - size = 1; - offset = 0x8f0025; - ; - - memory "lock" - size = 1; - offset = 0x8f0027; - ; - - memory "data" - # SRAM, only used to supply the offset - offset = 0x1000000; - ; -; - -#------------------------------------------------------------ -# ATxmega16A4U -#------------------------------------------------------------ - -part parent ".xmega" - id = "x16a4u"; - desc = "ATxmega16A4U"; - signature = 0x1e 0x94 0x41; - usbpid = 0x2fe3; - - memory "eeprom" - size = 0x400; - offset = 0x8c0000; - page_size = 0x20; - readsize = 0x100; - ; - - memory "application" - size = 0x4000; - offset = 0x800000; - page_size = 0x100; - readsize = 0x100; - ; - - memory "apptable" - size = 0x1000; - offset = 0x803000; - page_size = 0x100; - readsize = 0x100; - ; - - memory "boot" - size = 0x1000; - offset = 0x804000; - page_size = 0x100; - readsize = 0x100; - ; - - memory "flash" - size = 0x5000; - offset = 0x800000; - page_size = 0x100; - readsize = 0x100; - ; - - memory "usersig" - size = 0x100; - offset = 0x8e0400; - page_size = 0x100; - readsize = 0x100; - ; -; - -#------------------------------------------------------------ -# ATxmega16C4 -#------------------------------------------------------------ - -part parent "x16a4u" - id = "x16c4"; - desc = "ATxmega16C4"; - signature = 0x1e 0x94 0x43; -; - -#------------------------------------------------------------ -# ATxmega16D4 -#------------------------------------------------------------ - -part parent "x16a4u" - id = "x16d4"; - desc = "ATxmega16D4"; - signature = 0x1e 0x94 0x42; -; - -#------------------------------------------------------------ -# ATxmega16A4 -#------------------------------------------------------------ - -part parent "x16a4u" - id = "x16a4"; - desc = "ATxmega16A4"; - signature = 0x1e 0x94 0x41; - has_jtag = yes; - - memory "fuse0" - size = 1; - offset = 0x8f0020; - ; -; - -#------------------------------------------------------------ -# ATxmega32A4U -#------------------------------------------------------------ - -part parent ".xmega" - id = "x32a4u"; - desc = "ATxmega32A4U"; - signature = 0x1e 0x95 0x41; - usbpid = 0x2fe4; - - memory "eeprom" - size = 0x400; - offset = 0x8c0000; - page_size = 0x20; - readsize = 0x100; - ; - - memory "application" - size = 0x8000; - offset = 0x800000; - page_size = 0x100; - readsize = 0x100; - ; - - memory "apptable" - size = 0x1000; - offset = 0x807000; - page_size = 0x100; - readsize = 0x100; - ; - - memory "boot" - size = 0x1000; - offset = 0x808000; - page_size = 0x100; - readsize = 0x100; - ; - - memory "flash" - size = 0x9000; - offset = 0x800000; - page_size = 0x100; - readsize = 0x100; - ; - - memory "usersig" - size = 0x100; - offset = 0x8e0400; - page_size = 0x100; - readsize = 0x100; - ; -; - -#------------------------------------------------------------ -# ATxmega32C4 -#------------------------------------------------------------ - -part parent "x32a4u" - id = "x32c4"; - desc = "ATxmega32C4"; - signature = 0x1e 0x95 0x44; -; - -#------------------------------------------------------------ -# ATxmega32D4 -#------------------------------------------------------------ - -part parent "x32a4u" - id = "x32d4"; - desc = "ATxmega32D4"; - signature = 0x1e 0x95 0x42; -; - -#------------------------------------------------------------ -# ATxmega32A4 -#------------------------------------------------------------ - -part parent "x32a4u" - id = "x32a4"; - desc = "ATxmega32A4"; - signature = 0x1e 0x95 0x41; - has_jtag = yes; - - memory "fuse0" - size = 1; - offset = 0x8f0020; - ; -; - -#------------------------------------------------------------ -# ATxmega64A4U -#------------------------------------------------------------ - -part parent ".xmega" - id = "x64a4u"; - desc = "ATxmega64A4U"; - signature = 0x1e 0x96 0x46; - usbpid = 0x2fe5; - - memory "eeprom" - size = 0x800; - offset = 0x8c0000; - page_size = 0x20; - readsize = 0x100; - ; - - memory "application" - size = 0x10000; - offset = 0x800000; - page_size = 0x100; - readsize = 0x100; - ; - - memory "apptable" - size = 0x1000; - offset = 0x80f000; - page_size = 0x100; - readsize = 0x100; - ; - - memory "boot" - size = 0x1000; - offset = 0x810000; - page_size = 0x100; - readsize = 0x100; - ; - - memory "flash" - size = 0x11000; - offset = 0x800000; - page_size = 0x100; - readsize = 0x100; - ; - - memory "usersig" - size = 0x100; - offset = 0x8e0400; - page_size = 0x100; - readsize = 0x100; - ; -; - -#------------------------------------------------------------ -# ATxmega64C3 -#------------------------------------------------------------ - -part parent "x64a4u" - id = "x64c3"; - desc = "ATxmega64C3"; - signature = 0x1e 0x96 0x49; - usbpid = 0x2fd6; -; - -#------------------------------------------------------------ -# ATxmega64D3 -#------------------------------------------------------------ - -part parent "x64a4u" - id = "x64d3"; - desc = "ATxmega64D3"; - signature = 0x1e 0x96 0x4a; -; - -#------------------------------------------------------------ -# ATxmega64D4 -#------------------------------------------------------------ - -part parent "x64a4u" - id = "x64d4"; - desc = "ATxmega64D4"; - signature = 0x1e 0x96 0x47; -; - -#------------------------------------------------------------ -# ATxmega64A1 -#------------------------------------------------------------ - -part parent "x64a4u" - id = "x64a1"; - desc = "ATxmega64A1"; - signature = 0x1e 0x96 0x4e; - has_jtag = yes; - - memory "fuse0" - size = 1; - offset = 0x8f0020; - ; -; - -#------------------------------------------------------------ -# ATxmega64A1U -#------------------------------------------------------------ - -part parent "x64a1" - id = "x64a1u"; - desc = "ATxmega64A1U"; - signature = 0x1e 0x96 0x4e; - usbpid = 0x2fe8; -; - -#------------------------------------------------------------ -# ATxmega64A3 -#------------------------------------------------------------ - -part parent "x64a1" - id = "x64a3"; - desc = "ATxmega64A3"; - signature = 0x1e 0x96 0x42; -; - -#------------------------------------------------------------ -# ATxmega64A3U -#------------------------------------------------------------ - -part parent "x64a1" - id = "x64a3u"; - desc = "ATxmega64A3U"; - signature = 0x1e 0x96 0x42; - usbpid = 0x2fe5; -; - -#------------------------------------------------------------ -# ATxmega64A4 -#------------------------------------------------------------ - -part parent "x64a1" - id = "x64a4"; - desc = "ATxmega64A4"; - signature = 0x1e 0x96 0x46; -; - -#------------------------------------------------------------ -# ATxmega64B1 -#------------------------------------------------------------ - -part parent "x64a1" - id = "x64b1"; - desc = "ATxmega64B1"; - signature = 0x1e 0x96 0x52; - usbpid = 0x2fe1; -; - -#------------------------------------------------------------ -# ATxmega64B3 -#------------------------------------------------------------ - -part parent "x64a1" - id = "x64b3"; - desc = "ATxmega64B3"; - signature = 0x1e 0x96 0x51; - usbpid = 0x2fdf; -; - -#------------------------------------------------------------ -# ATxmega128C3 -#------------------------------------------------------------ - -part parent ".xmega" - id = "x128c3"; - desc = "ATxmega128C3"; - signature = 0x1e 0x97 0x52; - usbpid = 0x2fd7; - - memory "eeprom" - size = 0x800; - offset = 0x8c0000; - page_size = 0x20; - readsize = 0x100; - ; - - memory "application" - size = 0x20000; - offset = 0x800000; - page_size = 0x200; - readsize = 0x100; - ; - - memory "apptable" - size = 0x2000; - offset = 0x81e000; - page_size = 0x200; - readsize = 0x100; - ; - - memory "boot" - size = 0x2000; - offset = 0x820000; - page_size = 0x200; - readsize = 0x100; - ; - - memory "flash" - size = 0x22000; - offset = 0x800000; - page_size = 0x200; - readsize = 0x100; - ; - - memory "usersig" - size = 0x200; - offset = 0x8e0400; - page_size = 0x200; - readsize = 0x100; - ; -; - -#------------------------------------------------------------ -# ATxmega128D3 -#------------------------------------------------------------ - -part parent "x128c3" - id = "x128d3"; - desc = "ATxmega128D3"; - signature = 0x1e 0x97 0x48; -; - -#------------------------------------------------------------ -# ATxmega128D4 -#------------------------------------------------------------ - -part parent "x128c3" - id = "x128d4"; - desc = "ATxmega128D4"; - signature = 0x1e 0x97 0x47; -; - -#------------------------------------------------------------ -# ATxmega128A1 -#------------------------------------------------------------ - -part parent "x128c3" - id = "x128a1"; - desc = "ATxmega128A1"; - signature = 0x1e 0x97 0x4c; - has_jtag = yes; - - memory "fuse0" - size = 1; - offset = 0x8f0020; - ; -; - -#------------------------------------------------------------ -# ATxmega128A1 revision D -#------------------------------------------------------------ - -part parent "x128a1" - id = "x128a1d"; - desc = "ATxmega128A1revD"; - signature = 0x1e 0x97 0x41; -; - -#------------------------------------------------------------ -# ATxmega128A1U -#------------------------------------------------------------ - -part parent "x128a1" - id = "x128a1u"; - desc = "ATxmega128A1U"; - signature = 0x1e 0x97 0x4c; - usbpid = 0x2fed; -; - -#------------------------------------------------------------ -# ATxmega128A3 -#------------------------------------------------------------ - -part parent "x128a1" - id = "x128a3"; - desc = "ATxmega128A3"; - signature = 0x1e 0x97 0x42; -; - -#------------------------------------------------------------ -# ATxmega128A3U -#------------------------------------------------------------ - -part parent "x128a1" - id = "x128a3u"; - desc = "ATxmega128A3U"; - signature = 0x1e 0x97 0x42; - usbpid = 0x2fe6; -; - -#------------------------------------------------------------ -# ATxmega128A4 -#------------------------------------------------------------ - -part parent ".xmega" - id = "x128a4"; - desc = "ATxmega128A4"; - signature = 0x1e 0x97 0x46; - has_jtag = yes; - - memory "eeprom" - size = 0x800; - offset = 0x8c0000; - page_size = 0x20; - readsize = 0x100; - ; - - memory "application" - size = 0x20000; - offset = 0x800000; - page_size = 0x200; - readsize = 0x100; - ; - - memory "apptable" - size = 0x1000; - offset = 0x81f000; - page_size = 0x200; - readsize = 0x100; - ; - - memory "boot" - size = 0x2000; - offset = 0x820000; - page_size = 0x200; - readsize = 0x100; - ; - - memory "flash" - size = 0x22000; - offset = 0x800000; - page_size = 0x200; - readsize = 0x100; - ; - - memory "usersig" - size = 0x200; - offset = 0x8e0400; - page_size = 0x200; - readsize = 0x100; - ; - - memory "fuse0" - size = 1; - offset = 0x8f0020; - ; -; - -#------------------------------------------------------------ -# ATxmega128A4U -#------------------------------------------------------------ - -part parent ".xmega" - id = "x128a4u"; - desc = "ATxmega128A4U"; - signature = 0x1e 0x97 0x46; - usbpid = 0x2fde; - - memory "eeprom" - size = 0x800; - offset = 0x8c0000; - page_size = 0x20; - readsize = 0x100; - ; - - memory "application" - size = 0x20000; - offset = 0x800000; - page_size = 0x100; - readsize = 0x100; - ; - - memory "apptable" - size = 0x1000; - offset = 0x81f000; - page_size = 0x100; - readsize = 0x100; - ; - - memory "boot" - size = 0x2000; - offset = 0x820000; - page_size = 0x100; - readsize = 0x100; - ; - - memory "flash" - size = 0x22000; - offset = 0x800000; - page_size = 0x100; - readsize = 0x100; - ; - - memory "usersig" - size = 0x100; - offset = 0x8e0400; - page_size = 0x100; - readsize = 0x100; - ; -; - -#------------------------------------------------------------ -# ATxmega128B1 -#------------------------------------------------------------ - -part parent ".xmega" - id = "x128b1"; - desc = "ATxmega128B1"; - signature = 0x1e 0x97 0x4d; - usbpid = 0x2fea; - has_jtag = yes; - - memory "eeprom" - size = 0x800; - offset = 0x8c0000; - page_size = 0x20; - readsize = 0x100; - ; - - memory "application" - size = 0x20000; - offset = 0x800000; - page_size = 0x100; - readsize = 0x100; - ; - - memory "apptable" - size = 0x2000; - offset = 0x81e000; - page_size = 0x100; - readsize = 0x100; - ; - - memory "boot" - size = 0x2000; - offset = 0x820000; - page_size = 0x100; - readsize = 0x100; - ; - - memory "flash" - size = 0x22000; - offset = 0x800000; - page_size = 0x100; - readsize = 0x100; - ; - - memory "usersig" - size = 0x100; - offset = 0x8e0400; - page_size = 0x100; - readsize = 0x100; - ; - - memory "fuse0" - size = 1; - offset = 0x8f0020; - ; -; - -#------------------------------------------------------------ -# ATxmega128B3 -#------------------------------------------------------------ - -part parent "x128b1" - id = "x128b3"; - desc = "ATxmega128B3"; - signature = 0x1e 0x97 0x4b; - usbpid = 0x2fe0; -; - -#------------------------------------------------------------ -# ATxmega192C3 -#------------------------------------------------------------ - -part parent ".xmega" - id = "x192c3"; - desc = "ATxmega192C3"; - signature = 0x1e 0x97 0x51; - # usbpid = 0x2f??; - - memory "eeprom" - size = 0x800; - offset = 0x8c0000; - page_size = 0x20; - readsize = 0x100; - ; - - memory "application" - size = 0x30000; - offset = 0x800000; - page_size = 0x200; - readsize = 0x100; - ; - - memory "apptable" - size = 0x2000; - offset = 0x82e000; - page_size = 0x200; - readsize = 0x100; - ; - - memory "boot" - size = 0x2000; - offset = 0x830000; - page_size = 0x200; - readsize = 0x100; - ; - - memory "flash" - size = 0x32000; - offset = 0x800000; - page_size = 0x200; - readsize = 0x100; - ; - - memory "usersig" - size = 0x200; - offset = 0x8e0400; - page_size = 0x200; - readsize = 0x100; - ; -; - -#------------------------------------------------------------ -# ATxmega192D3 -#------------------------------------------------------------ - -part parent "x192c3" - id = "x192d3"; - desc = "ATxmega192D3"; - signature = 0x1e 0x97 0x49; -; - -#------------------------------------------------------------ -# ATxmega192A1 -#------------------------------------------------------------ - -part parent "x192c3" - id = "x192a1"; - desc = "ATxmega192A1"; - signature = 0x1e 0x97 0x4e; - has_jtag = yes; - - memory "fuse0" - size = 1; - offset = 0x8f0020; - ; -; - -#------------------------------------------------------------ -# ATxmega192A3 -#------------------------------------------------------------ - -part parent "x192a1" - id = "x192a3"; - desc = "ATxmega192A3"; - signature = 0x1e 0x97 0x44; -; - -#------------------------------------------------------------ -# ATxmega192A3U -#------------------------------------------------------------ - -part parent "x192a1" - id = "x192a3u"; - desc = "ATxmega192A3U"; - signature = 0x1e 0x97 0x44; - usbpid = 0x2fe7; -; - -#------------------------------------------------------------ -# ATxmega256C3 -#------------------------------------------------------------ - -part parent ".xmega" - id = "x256c3"; - desc = "ATxmega256C3"; - signature = 0x1e 0x98 0x46; - usbpid = 0x2fda; - - memory "eeprom" - size = 0x1000; - offset = 0x8c0000; - page_size = 0x20; - readsize = 0x100; - ; - - memory "application" - size = 0x40000; - offset = 0x800000; - page_size = 0x200; - readsize = 0x100; - ; - - memory "apptable" - size = 0x2000; - offset = 0x83e000; - page_size = 0x200; - readsize = 0x100; - ; - - memory "boot" - size = 0x2000; - offset = 0x840000; - page_size = 0x200; - readsize = 0x100; - ; - - memory "flash" - size = 0x42000; - offset = 0x800000; - page_size = 0x200; - readsize = 0x100; - ; - - memory "usersig" - size = 0x200; - offset = 0x8e0400; - page_size = 0x200; - readsize = 0x100; - ; -; - -#------------------------------------------------------------ -# ATxmega256D3 -#------------------------------------------------------------ - -part parent "x256c3" - id = "x256d3"; - desc = "ATxmega256D3"; - signature = 0x1e 0x98 0x44; -; - -#------------------------------------------------------------ -# ATxmega256A1 -#------------------------------------------------------------ - -part parent "x256c3" - id = "x256a1"; - desc = "ATxmega256A1"; - signature = 0x1e 0x98 0x46; - has_jtag = yes; - - memory "fuse0" - size = 1; - offset = 0x8f0020; - ; -; - -#------------------------------------------------------------ -# ATxmega256A3 -#------------------------------------------------------------ - -part parent "x256a1" - id = "x256a3"; - desc = "ATxmega256A3"; - signature = 0x1e 0x98 0x42; -; - -#------------------------------------------------------------ -# ATxmega256A3U -#------------------------------------------------------------ - -part parent "x256a1" - id = "x256a3u"; - desc = "ATxmega256A3U"; - signature = 0x1e 0x98 0x42; - usbpid = 0x2fec; -; - -#------------------------------------------------------------ -# ATxmega256A3B -#------------------------------------------------------------ - -part parent "x256a1" - id = "x256a3b"; - desc = "ATxmega256A3B"; - signature = 0x1e 0x98 0x43; -; - -#------------------------------------------------------------ -# ATxmega256A3BU -#------------------------------------------------------------ - -part parent "x256a1" - id = "x256a3bu"; - desc = "ATxmega256A3BU"; - signature = 0x1e 0x98 0x43; - usbpid = 0x2fe2; -; - -#------------------------------------------------------------ -# ATxmega384C3 -#------------------------------------------------------------ - -part parent ".xmega" - id = "x384c3"; - desc = "ATxmega384C3"; - signature = 0x1e 0x98 0x45; - usbpid = 0x2fdb; - - memory "eeprom" - size = 0x1000; - offset = 0x8c0000; - page_size = 0x20; - readsize = 0x100; - ; - - memory "application" - size = 0x60000; - offset = 0x800000; - page_size = 0x200; - readsize = 0x100; - ; - - memory "apptable" - size = 0x2000; - offset = 0x85e000; - page_size = 0x200; - readsize = 0x100; - ; - - memory "boot" - size = 0x2000; - offset = 0x860000; - page_size = 0x200; - readsize = 0x100; - ; - - memory "flash" - size = 0x62000; - offset = 0x800000; - page_size = 0x200; - readsize = 0x100; - ; - - memory "usersig" - size = 0x200; - offset = 0x8e0400; - page_size = 0x200; - readsize = 0x100; - ; -; - -#------------------------------------------------------------ -# ATxmega384D3 -#------------------------------------------------------------ - -part parent "x384c3" - id = "x384d3"; - desc = "ATxmega384D3"; - signature = 0x1e 0x98 0x47; -; - -#------------------------------------------------------------ -# ATxmega8E5 -#------------------------------------------------------------ - -part parent ".xmega" - id = "x8e5"; - desc = "ATxmega8E5"; - signature = 0x1e 0x93 0x41; - - memory "eeprom" - size = 0x0200; - offset = 0x08c0000; - page_size = 0x20; - readsize = 0x100; - ; - - memory "application" - size = 0x2000; - offset = 0x0800000; - page_size = 0x80; - readsize = 0x100; - ; - - memory "apptable" - size = 0x800; - offset = 0x00801800; - page_size = 0x80; - readsize = 0x100; - ; - - memory "boot" - size = 0x800; - offset = 0x00802000; - page_size = 0x80; - readsize = 0x100; - ; - - memory "flash" - size = 0x2800; - offset = 0x0800000; - page_size = 0x80; - readsize = 0x100; - ; - - memory "usersig" - size = 0x80; - offset = 0x8e0400; - page_size = 0x80; - readsize = 0x100; - ; -; - -#------------------------------------------------------------ -# ATxmega16E5 -#------------------------------------------------------------ - -part parent ".xmega" - id = "x16e5"; - desc = "ATxmega16E5"; - signature = 0x1e 0x94 0x45; - - memory "eeprom" - size = 0x0200; - offset = 0x08c0000; - page_size = 0x20; - readsize = 0x100; - ; - - memory "application" - size = 0x4000; - offset = 0x0800000; - page_size = 0x80; - readsize = 0x100; - ; - - memory "apptable" - size = 0x1000; - offset = 0x00803000; - page_size = 0x80; - readsize = 0x100; - ; - - memory "boot" - size = 0x1000; - offset = 0x00804000; - page_size = 0x80; - readsize = 0x100; - ; - - memory "flash" - size = 0x5000; - offset = 0x0800000; - page_size = 0x80; - readsize = 0x100; - ; - - memory "usersig" - size = 0x80; - offset = 0x8e0400; - page_size = 0x80; - readsize = 0x100; - ; -; - -#------------------------------------------------------------ -# ATxmega32E5 -#------------------------------------------------------------ - -part parent ".xmega" - id = "x32e5"; - desc = "ATxmega32E5"; - signature = 0x1e 0x95 0x4c; - - memory "eeprom" - size = 0x0400; - offset = 0x08c0000; - page_size = 0x20; - readsize = 0x100; - ; - - memory "application" - size = 0x8000; - offset = 0x0800000; - page_size = 0x80; - readsize = 0x100; - ; - - memory "apptable" - size = 0x1000; - offset = 0x00807000; - page_size = 0x80; - readsize = 0x100; - ; - - memory "boot" - size = 0x1000; - offset = 0x00808000; - page_size = 0x80; - readsize = 0x100; - ; - - memory "flash" - size = 0x9000; - offset = 0x0800000; - page_size = 0x80; - readsize = 0x100; - ; - - memory "usersig" - size = 0x80; - offset = 0x8e0400; - page_size = 0x80; - readsize = 0x100; - ; -; - -#------------------------------------------------------------ -# AVR32UC3A0512 -#------------------------------------------------------------ - -part - id = "uc3a0512"; - desc = "AT32UC3A0512"; - signature = 0xED 0xC0 0x3F; - has_jtag = yes; - is_avr32 = yes; - - memory "flash" - paged = yes; - page_size = 512; # bytes - readsize = 512; # bytes - num_pages = 1024; # could be set dynamicly - size = 0x00080000; # could be set dynamicly - offset = 0x80000000; - ; -; - -part parent "uc3a0512" - id = "ucr2"; - desc = "deprecated, use 'uc3a0512'"; -; - -#------------------------------------------------------------ -# ATtiny1634. -#------------------------------------------------------------ - -part - id = "t1634"; - desc = "ATtiny1634"; - has_debugwire = yes; - flash_instr = 0xB6, 0x01, 0x11; - eeprom_instr = 0xBD, 0xF2, 0xBD, 0xE1, 0xBB, 0xCF, 0xB4, 0x00, - 0xBE, 0x01, 0xB6, 0x01, 0xBC, 0x00, 0xBB, 0xBF, - 0x99, 0xF9, 0xBB, 0xAF; - stk500_devcode = 0x86; - # avr910_devcode = 0x; - signature = 0x1e 0x94 0x12; - pagel = 0xB3; - bs2 = 0xB1; - reset = io; - chip_erase_delay = 9000; - pgm_enable = "1 0 1 0 1 1 0 0 0 1 0 1 0 0 1 1", - "x x x x x x x x x x x x x x x x"; - - chip_erase = "1 0 1 0 1 1 0 0 1 0 0 x x x x x", - "x x x x x x x x x x x x x x x x"; - - timeout = 200; - stabdelay = 100; - cmdexedelay = 25; - synchloops = 32; - bytedelay = 0; - pollindex = 3; - pollvalue = 0x53; - predelay = 1; - postdelay = 1; - pollmethod = 1; - - pp_controlstack = - 0x0E, 0x1E, 0x0E, 0x1E, 0x2E, 0x3E, 0x2E, 0x3E, - 0x4E, 0x5E, 0x4E, 0x5E, 0x6E, 0x7E, 0x6E, 0x7E, - 0x26, 0x36, 0x66, 0x76, 0x2A, 0x3A, 0x6A, 0x7A, - 0x2E, 0xFD, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00; - hventerstabdelay = 100; - progmodedelay = 0; - latchcycles = 0; - togglevtg = 1; - poweroffdelay = 15; - resetdelayms = 1; - resetdelayus = 0; - hvleavestabdelay = 15; - resetdelay = 15; - chiperasepulsewidth = 0; - chiperasepolltimeout = 10; - programfusepulsewidth = 0; - programfusepolltimeout = 5; - programlockpulsewidth = 0; - programlockpolltimeout = 5; - - memory "eeprom" - paged = no; - page_size = 4; - size = 256; - min_write_delay = 3600; - max_write_delay = 3600; - readback_p1 = 0xff; - readback_p2 = 0xff; - read = " 1 0 1 0 0 0 0 0", - " 0 0 0 x x x x a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " o o o o o o o o"; - - write = " 1 1 0 0 0 0 0 0", - " 0 0 0 x x x x a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " i i i i i i i i"; - - loadpage_lo = " 1 1 0 0 0 0 0 1", - " 0 0 0 0 0 0 0 0", - " 0 0 0 0 0 0 a1 a0", - " i i i i i i i i"; - - writepage = " 1 1 0 0 0 0 1 0", - " 0 0 x x x x x a8", - " a7 a6 a5 a4 a3 a2 0 0", - " x x x x x x x x"; - - mode = 0x41; - delay = 5; - blocksize = 4; - readsize = 256; - ; - - memory "flash" - paged = yes; - size = 16384; - page_size = 32; - num_pages = 512; - min_write_delay = 4500; - max_write_delay = 4500; - readback_p1 = 0xff; - readback_p2 = 0xff; - read_lo = " 0 0 1 0 0 0 0 0", - " 0 0 0 a12 a11 a10 a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " o o o o o o o o"; - - read_hi = " 0 0 1 0 1 0 0 0", - " 0 0 0 a12 a11 a10 a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " o o o o o o o o"; - - loadpage_lo = " 0 1 0 0 0 0 0 0", - " 0 0 0 x x x x x", - " x x a5 a4 a3 a2 a1 a0", - " i i i i i i i i"; - - loadpage_hi = " 0 1 0 0 1 0 0 0", - " 0 0 0 x x x x x", - " x x a5 a4 a3 a2 a1 a0", - " i i i i i i i i"; - - writepage = " 0 1 0 0 1 1 0 0", - " 0 0 0 a12 a11 a10 a9 a8", - " a7 a6 x x x x x x", - " x x x x x x x x"; - - mode = 0x41; - delay = 6; - blocksize = 128; - readsize = 256; - - ; - - memory "lfuse" - size = 1; - min_write_delay = 4500; - max_write_delay = 4500; - read = "0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0", - "x x x x x x x x o o o o o o o o"; - - write = "1 0 1 0 1 1 0 0 1 0 1 0 0 0 0 0", - "x x x x x x x x i i i i i i i i"; - ; - - memory "hfuse" - size = 1; - min_write_delay = 4500; - max_write_delay = 4500; - read = "0 1 0 1 1 0 0 0 0 0 0 0 1 0 0 0", - "x x x x x x x x o o o o o o o o"; - - write = "1 0 1 0 1 1 0 0 1 0 1 0 1 0 0 0", - "x x x x x x x x i i i i i i i i"; - ; - - memory "efuse" - size = 1; - min_write_delay = 4500; - max_write_delay = 4500; - read = "0 1 0 1 0 0 0 0 0 0 0 0 1 0 0 0", - "x x x x x x x x o o o o o o o o"; - - write = "1 0 1 0 1 1 0 0 1 0 1 0 0 1 0 0", - "x x x x x x x x x x x i i i i i"; - ; - - memory "lock" - size = 1; - min_write_delay = 4500; - max_write_delay = 4500; - read = "0 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0", - "x x x x x x x x x x x x x x o o"; - - write = "1 0 1 0 1 1 0 0 1 1 1 x x x x x", - "x x x x x x x x 1 1 1 1 1 1 i i"; - ; - - memory "calibration" - size = 1; - read = "0 0 1 1 1 0 0 0 0 0 0 x x x x x", - "0 0 0 0 0 0 0 0 o o o o o o o o"; - ; - - memory "signature" - size = 3; - read = "0 0 1 1 0 0 0 0 0 0 0 x x x x x", - "x x x x x x a1 a0 o o o o o o o o"; - ; -; - -#------------------------------------------------------------ -# Common values for reduced core tinys (4/5/9/10/20/40) -#------------------------------------------------------------ - -part - id = ".reduced_core_tiny"; - desc = "Common values for reduced core tinys"; - has_tpi = yes; - - memory "signature" - size = 3; - offset = 0x3fc0; - page_size = 16; - ; - - memory "fuse" - size = 1; - offset = 0x3f40; - page_size = 16; - blocksize = 4; - ; - - memory "calibration" - size = 1; - offset = 0x3f80; - page_size = 16; - ; - - memory "lockbits" - size = 1; - offset = 0x3f00; - page_size = 16; - ; -; - -#------------------------------------------------------------ -# ATtiny4 -#------------------------------------------------------------ - -part parent ".reduced_core_tiny" - id = "t4"; - desc = "ATtiny4"; - signature = 0x1e 0x8f 0x0a; - - memory "flash" - size = 512; - offset = 0x4000; - page_size = 16; - blocksize = 128; - ; -; - -#------------------------------------------------------------ -# ATtiny5 -#------------------------------------------------------------ - -part parent "t4" - id = "t5"; - desc = "ATtiny5"; - signature = 0x1e 0x8f 0x09; -; - -#------------------------------------------------------------ -# ATtiny9 -#------------------------------------------------------------ - -part parent ".reduced_core_tiny" - id = "t9"; - desc = "ATtiny9"; - signature = 0x1e 0x90 0x08; - - memory "flash" - size = 1024; - offset = 0x4000; - page_size = 16; - blocksize = 128; - ; -; - -#------------------------------------------------------------ -# ATtiny10 -#------------------------------------------------------------ - -part parent "t9" - id = "t10"; - desc = "ATtiny10"; - signature = 0x1e 0x90 0x03; -; - -#------------------------------------------------------------ -# ATtiny20 -#------------------------------------------------------------ - -part parent ".reduced_core_tiny" - id = "t20"; - desc = "ATtiny20"; - signature = 0x1e 0x91 0x0F; - - memory "flash" - size = 2048; - offset = 0x4000; - page_size = 16; - blocksize = 128; - ; -; - -#------------------------------------------------------------ -# ATtiny40 -#------------------------------------------------------------ - -part parent ".reduced_core_tiny" - id = "t40"; - desc = "ATtiny40"; - signature = 0x1e 0x92 0x0E; - - memory "flash" - size = 4096; - offset = 0x4000; - page_size = 64; - blocksize = 128; - ; -; - -#------------------------------------------------------------ -# ATmega406 -#------------------------------------------------------------ - -part - id = "m406"; - desc = "ATMEGA406"; - has_jtag = yes; - signature = 0x1e 0x95 0x07; - - # STK500 parameters (parallel programming IO lines) - pagel = 0xa7; - bs2 = 0xa0; - serial = no; - parallel = yes; - - # STK500v2 HV programming parameters, from XML - pp_controlstack = 0x0e, 0x1e, 0x0f, 0x1f, 0x2e, 0x3e, 0x2f, 0x3f, - 0x4e, 0x5e, 0x4f, 0x5f, 0x6e, 0x7e, 0x6f, 0x7f, - 0x66, 0x76, 0x67, 0x77, 0x6a, 0x7a, 0x6b, 0x7b, - 0xbe, 0xfd, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00; - - # JTAG ICE mkII parameters, also from XML files - allowfullpagebitstream = no; - enablepageprogramming = yes; - idr = 0x51; - rampz = 0x00; - spmcr = 0x57; - eecr = 0x3f; - - memory "eeprom" - paged = no; - size = 512; - page_size = 4; - blocksize = 4; - readsize = 4; - num_pages = 128; - ; - - memory "flash" - paged = yes; - size = 40960; - page_size = 128; - blocksize = 128; - readsize = 128; - num_pages = 320; - ; - - memory "hfuse" - size = 1; - ; - - memory "lfuse" - size = 1; - ; - - memory "lockbits" - size = 1; - ; - - memory "signature" - size = 3; - ; -; - -#------------------------------------------------------------ -# AVR8X family common values -#------------------------------------------------------------ - -part - id = ".avr8x"; - desc = "AVR8X family common values"; - has_updi = yes; - nvm_base = 0x1000; - ocd_base = 0x0F80; - - memory "signature" - size = 3; - offset = 0x1100; - ; - - memory "prodsig" - size = 0x3D; - offset = 0x1103; - page_size = 0x3D; - readsize = 0x3D; - ; - - memory "fuses" - size = 9; - offset = 0x1280; - ; - - memory "fuse0" - size = 1; - offset = 0x1280; - ; - - memory "fuse1" - size = 1; - offset = 0x1281; - ; - - memory "fuse2" - size = 1; - offset = 0x1282; - ; - - memory "fuse4" - size = 1; - offset = 0x1284; - ; - - memory "fuse5" - size = 1; - offset = 0x1285; - ; - - memory "fuse6" - size = 1; - offset = 0x1286; - ; - - memory "fuse7" - size = 1; - offset = 0x1287; - ; - - memory "fuse8" - size = 1; - offset = 0x1288; - ; - - memory "lock" - size = 1; - offset = 0x128a; - ; - - memory "data" - # SRAM, only used to supply the offset - offset = 0x1000000; - ; -; - -#------------------------------------------------------------ -# AVR8X tiny family common values -#------------------------------------------------------------ - -part parent ".avr8x" - id = ".avr8x_tiny"; - desc = "AVR8X tiny family common values"; - family_id = "tinyAVR"; - - memory "usersig" - size = 0x20; - offset = 0x1300; - page_size = 0x20; - readsize = 0x100; - ; -; - -#------------------------------------------------------------ -# AVR8X mega family common values -#------------------------------------------------------------ - -part parent ".avr8x" - id = ".avr8x_mega"; - desc = "AVR8X mega family common values"; - family_id = "megaAVR"; - - memory "usersig" - size = 0x40; - offset = 0x1300; - page_size = 0x40; - readsize = 0x100; - ; -; - -#------------------------------------------------------------ -# ATtiny202 -#------------------------------------------------------------ - -part parent ".avr8x_tiny" - id = "t202"; - desc = "ATtiny202"; - signature = 0x1E 0x91 0x23; - - memory "flash" - size = 0x800; - offset = 0x8000; - page_size = 0x40; - readsize = 0x100; - ; - - memory "eeprom" - size = 0x40; - offset = 0x1400; - page_size = 0x20; - readsize = 0x100; - ; -; - -#------------------------------------------------------------ -# ATtiny204 -#------------------------------------------------------------ - -part parent ".avr8x_tiny" - id = "t204"; - desc = "ATtiny204"; - signature = 0x1E 0x91 0x22; - - memory "flash" - size = 0x800; - offset = 0x8000; - page_size = 0x40; - readsize = 0x100; - ; - - memory "eeprom" - size = 0x40; - offset = 0x1400; - page_size = 0x20; - readsize = 0x100; - ; -; - -#------------------------------------------------------------ -# ATtiny402 -#------------------------------------------------------------ - -part parent ".avr8x_tiny" - id = "t402"; - desc = "ATtiny402"; - signature = 0x1E 0x92 0x23; - - memory "flash" - size = 0x1000; - offset = 0x8000; - page_size = 0x40; - readsize = 0x100; - ; - - memory "eeprom" - size = 0x80; - offset = 0x1400; - page_size = 0x20; - readsize = 0x100; - ; -; - -#------------------------------------------------------------ -# ATtiny404 -#------------------------------------------------------------ - -part parent ".avr8x_tiny" - id = "t404"; - desc = "ATtiny404"; - signature = 0x1E 0x92 0x26; - - memory "flash" - size = 0x1000; - offset = 0x8000; - page_size = 0x40; - readsize = 0x100; - ; - - memory "eeprom" - size = 0x80; - offset = 0x1400; - page_size = 0x20; - readsize = 0x100; - ; -; - -#------------------------------------------------------------ -# ATtiny406 -#------------------------------------------------------------ - -part parent ".avr8x_tiny" - id = "t406"; - desc = "ATtiny406"; - signature = 0x1E 0x92 0x25; - - memory "flash" - size = 0x1000; - offset = 0x8000; - page_size = 0x40; - readsize = 0x100; - ; - - memory "eeprom" - size = 0x80; - offset = 0x1400; - page_size = 0x20; - readsize = 0x100; - ; -; - -#------------------------------------------------------------ -# ATtiny804 -#------------------------------------------------------------ - -part parent ".avr8x_tiny" - id = "t804"; - desc = "ATtiny804"; - signature = 0x1E 0x93 0x25; - - memory "flash" - size = 0x2000; - offset = 0x8000; - page_size = 0x40; - readsize = 0x100; - ; - - memory "eeprom" - size = 0x80; - offset = 0x1400; - page_size = 0x20; - readsize = 0x100; - ; -; - -#------------------------------------------------------------ -# ATtiny806 -#------------------------------------------------------------ - -part parent ".avr8x_tiny" - id = "t806"; - desc = "ATtiny806"; - signature = 0x1E 0x93 0x24; - - memory "flash" - size = 0x2000; - offset = 0x8000; - page_size = 0x40; - readsize = 0x100; - ; - - memory "eeprom" - size = 0x80; - offset = 0x1400; - page_size = 0x20; - readsize = 0x100; - ; -; - -#------------------------------------------------------------ -# ATtiny807 -#------------------------------------------------------------ - -part parent ".avr8x_tiny" - id = "t807"; - desc = "ATtiny807"; - signature = 0x1E 0x93 0x23; - - memory "flash" - size = 0x2000; - offset = 0x8000; - page_size = 0x40; - readsize = 0x100; - ; - - memory "eeprom" - size = 0x80; - offset = 0x1400; - page_size = 0x20; - readsize = 0x100; - ; -; - -#------------------------------------------------------------ -# ATtiny1604 -#------------------------------------------------------------ - -part parent ".avr8x_tiny" - id = "t1604"; - desc = "ATtiny1604"; - signature = 0x1E 0x94 0x25; - - memory "flash" - size = 0x4000; - offset = 0x8000; - page_size = 0x40; - readsize = 0x100; - ; - - memory "eeprom" - size = 0x100; - offset = 0x1400; - page_size = 0x20; - readsize = 0x100; - ; -; - -#------------------------------------------------------------ -# ATtiny1606 -#------------------------------------------------------------ - -part parent ".avr8x_tiny" - id = "t1606"; - desc = "ATtiny1606"; - signature = 0x1E 0x94 0x24; - - memory "flash" - size = 0x4000; - offset = 0x8000; - page_size = 0x40; - readsize = 0x100; - ; - - memory "eeprom" - size = 0x100; - offset = 0x1400; - page_size = 0x20; - readsize = 0x100; - ; -; - -#------------------------------------------------------------ -# ATtiny1607 -#------------------------------------------------------------ - -part parent ".avr8x_tiny" - id = "t1607"; - desc = "ATtiny1607"; - signature = 0x1E 0x94 0x23; - - memory "flash" - size = 0x4000; - offset = 0x8000; - page_size = 0x40; - readsize = 0x100; - ; - - memory "eeprom" - size = 0x100; - offset = 0x1400; - page_size = 0x20; - readsize = 0x100; - ; -; - -#------------------------------------------------------------ -# ATtiny212 -#------------------------------------------------------------ - -part parent ".avr8x_tiny" - id = "t212"; - desc = "ATtiny212"; - signature = 0x1E 0x91 0x21; - - memory "flash" - size = 0x800; - offset = 0x8000; - page_size = 0x40; - readsize = 0x100; - ; - - memory "eeprom" - size = 0x40; - offset = 0x1400; - page_size = 0x20; - readsize = 0x100; - ; -; - -#------------------------------------------------------------ -# ATtiny214 -#------------------------------------------------------------ - -part parent ".avr8x_tiny" - id = "t214"; - desc = "ATtiny214"; - signature = 0x1E 0x91 0x20; - - memory "flash" - size = 0x800; - offset = 0x8000; - page_size = 0x40; - readsize = 0x100; - ; - - memory "eeprom" - size = 0x40; - offset = 0x1400; - page_size = 0x20; - readsize = 0x100; - ; -; - -#------------------------------------------------------------ -# ATtiny412 -#------------------------------------------------------------ - -part parent ".avr8x_tiny" - id = "t412"; - desc = "ATtiny412"; - signature = 0x1E 0x92 0x23; - - memory "flash" - size = 0x1000; - offset = 0x8000; - page_size = 0x40; - readsize = 0x100; - ; - - memory "eeprom" - size = 0x80; - offset = 0x1400; - page_size = 0x20; - readsize = 0x100; - ; -; - - -#------------------------------------------------------------ -# ATtiny414 -#------------------------------------------------------------ - -part parent ".avr8x_tiny" - id = "t414"; - desc = "ATtiny414"; - signature = 0x1E 0x92 0x22; - - memory "flash" - size = 0x1000; - offset = 0x8000; - page_size = 0x40; - readsize = 0x100; - ; - - memory "eeprom" - size = 0x80; - offset = 0x1400; - page_size = 0x20; - readsize = 0x100; - ; -; - -#------------------------------------------------------------ -# ATtiny416 -#------------------------------------------------------------ - -part parent ".avr8x_tiny" - id = "t416"; - desc = "ATtiny416"; - signature = 0x1E 0x92 0x21; - - memory "flash" - size = 0x1000; - offset = 0x8000; - page_size = 0x40; - readsize = 0x100; - ; - - memory "eeprom" - size = 0x80; - offset = 0x1400; - page_size = 0x20; - readsize = 0x100; - ; -; - - -#------------------------------------------------------------ -# ATtiny417 -#------------------------------------------------------------ - -part parent ".avr8x_tiny" - id = "t417"; - desc = "ATtiny417"; - signature = 0x1E 0x92 0x20; - - memory "flash" - size = 0x1000; - offset = 0x8000; - page_size = 0x40; - readsize = 0x100; - ; - - memory "eeprom" - size = 0x80; - offset = 0x1400; - page_size = 0x20; - readsize = 0x100; - ; -; - - -#------------------------------------------------------------ -# ATtiny814 -#------------------------------------------------------------ - -part parent ".avr8x_tiny" - id = "t814"; - desc = "ATtiny814"; - signature = 0x1E 0x93 0x22; - - memory "flash" - size = 0x2000; - offset = 0x8000; - page_size = 0x40; - readsize = 0x100; - ; - - memory "eeprom" - size = 0x80; - offset = 0x1400; - page_size = 0x20; - readsize = 0x100; - ; -; - - -#------------------------------------------------------------ -# ATtiny816 -#------------------------------------------------------------ - -part parent ".avr8x_tiny" - id = "t816"; - desc = "ATtiny816"; - signature = 0x1E 0x93 0x21; - - memory "flash" - size = 0x2000; - offset = 0x8000; - page_size = 0x40; - readsize = 0x100; - ; - - memory "eeprom" - size = 0x80; - offset = 0x1400; - page_size = 0x20; - readsize = 0x100; - ; -; - -#------------------------------------------------------------ -# ATtiny817 -#------------------------------------------------------------ - -part parent ".avr8x_tiny" - id = "t817"; - desc = "ATtiny817"; - signature = 0x1E 0x93 0x20; - - memory "flash" - size = 0x2000; - offset = 0x8000; - page_size = 0x40; - readsize = 0x100; - ; - - memory "eeprom" - size = 0x80; - offset = 0x1400; - page_size = 0x20; - readsize = 0x100; - ; -; - -#------------------------------------------------------------ -# ATtiny1614 -#------------------------------------------------------------ - -part parent ".avr8x_tiny" - id = "t1614"; - desc = "ATtiny1614"; - signature = 0x1E 0x94 0x22; - - memory "flash" - size = 0x4000; - offset = 0x8000; - page_size = 0x40; - readsize = 0x100; - ; - - memory "eeprom" - size = 0x100; - offset = 0x1400; - page_size = 0x20; - readsize = 0x100; - ; -; - -#------------------------------------------------------------ -# ATtiny1616 -#------------------------------------------------------------ - -part parent ".avr8x_tiny" - id = "t1616"; - desc = "ATtiny1616"; - signature = 0x1E 0x94 0x21; - - memory "flash" - size = 0x4000; - offset = 0x8000; - page_size = 0x40; - readsize = 0x100; - ; - - memory "eeprom" - size = 0x100; - offset = 0x1400; - page_size = 0x20; - readsize = 0x100; - ; -; - -#------------------------------------------------------------ -# ATtiny1617 -#------------------------------------------------------------ - -part parent ".avr8x_tiny" - id = "t1617"; - desc = "ATtiny1617"; - signature = 0x1E 0x94 0x20; - - memory "flash" - size = 0x4000; - offset = 0x8000; - page_size = 0x40; - readsize = 0x100; - ; - - memory "eeprom" - size = 0x100; - offset = 0x1400; - page_size = 0x20; - readsize = 0x100; - ; -; - -#------------------------------------------------------------ -# ATtiny3214 -#------------------------------------------------------------ - -part parent ".avr8x_tiny" - id = "t3214"; - desc = "ATtiny3214"; - signature = 0x1E 0x95 0x20; - - memory "flash" - size = 0x8000; - offset = 0x8000; - page_size = 0x80; - readsize = 0x100; - ; - - memory "eeprom" - size = 0x100; - offset = 0x1400; - page_size = 0x40; - readsize = 0x100; - ; -; - -#------------------------------------------------------------ -# ATtiny3216 -#------------------------------------------------------------ - -part parent ".avr8x_tiny" - id = "t3216"; - desc = "ATtiny3216"; - signature = 0x1E 0x95 0x21; - - memory "flash" - size = 0x8000; - offset = 0x8000; - page_size = 0x80; - readsize = 0x100; - ; - - memory "eeprom" - size = 0x100; - offset = 0x1400; - page_size = 0x40; - readsize = 0x100; - ; -; - -#------------------------------------------------------------ -# ATtiny3217 -#------------------------------------------------------------ - -part parent ".avr8x_tiny" - id = "t3217"; - desc = "ATtiny3217"; - signature = 0x1E 0x95 0x22; - - memory "flash" - size = 0x8000; - offset = 0x8000; - page_size = 0x80; - readsize = 0x100; - ; - - memory "eeprom" - size = 0x100; - offset = 0x1400; - page_size = 0x40; - readsize = 0x100; - ; -; - -#------------------------------------------------------------ -# ATmega3208 -#------------------------------------------------------------ - -part parent ".avr8x_mega" - id = "m3208"; - desc = "ATmega3208"; - signature = 0x1E 0x95 0x52; - - memory "flash" - size = 0x8000; - offset = 0x4000; - page_size = 0x80; - readsize = 0x100; - ; - - memory "eeprom" - size = 0x100; - offset = 0x1400; - page_size = 0x40; - readsize = 0x100; - ; -; - -#------------------------------------------------------------ -# ATmega3209 -#------------------------------------------------------------ - -part parent ".avr8x_mega" - id = "m3209"; - desc = "ATmega3209"; - signature = 0x1E 0x95 0x53; - - memory "flash" - size = 0x8000; - offset = 0x4000; - page_size = 0x80; - readsize = 0x100; - ; - - memory "eeprom" - size = 0x100; - offset = 0x1400; - page_size = 0x40; - readsize = 0x100; - ; -; - -#------------------------------------------------------------ -# ATmega4808 -#------------------------------------------------------------ - -part parent ".avr8x_mega" - id = "m4808"; - desc = "ATmega4808"; - signature = 0x1E 0x96 0x50; - - memory "flash" - size = 0xC000; - offset = 0x4000; - page_size = 0x80; - readsize = 0x100; - ; - - memory "eeprom" - size = 0x100; - offset = 0x1400; - page_size = 0x40; - readsize = 0x100; - ; -; - -#------------------------------------------------------------ -# ATmega4809 -#------------------------------------------------------------ - -part parent ".avr8x_mega" - id = "m4809"; - desc = "ATmega4809"; - signature = 0x1E 0x96 0x51; - - memory "flash" - size = 0xC000; - offset = 0x4000; - page_size = 0x80; - readsize = 0x100; - ; - - memory "eeprom" - size = 0x100; - offset = 0x1400; - page_size = 0x40; - readsize = 0x100; - ; -; diff --git a/arduino/hardware/tools/avr/include/gdb/jit-reader.h b/arduino/hardware/tools/avr/include/gdb/jit-reader.h deleted file mode 100644 index e9599a2..0000000 --- a/arduino/hardware/tools/avr/include/gdb/jit-reader.h +++ /dev/null @@ -1,346 +0,0 @@ -/* JIT declarations for GDB, the GNU Debugger. - - Copyright (C) 2011-2014 Free Software Foundation, Inc. - - This file is part of GDB. - - This program is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - This program is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . */ - -#ifndef GDB_JIT_READER_H -#define GDB_JIT_READER_H - -#ifdef __cplusplus -extern "C" { -#endif - -/* Versioning information. See gdb_reader_funcs. */ - -#define GDB_READER_INTERFACE_VERSION 1 - -/* Readers must be released under a GPL compatible license. To - declare that the reader is indeed released under a GPL compatible - license, invoke the macro GDB_DECLARE_GPL_COMPATIBLE in a source - file. */ - -#ifdef __cplusplus -#define GDB_DECLARE_GPL_COMPATIBLE_READER \ - extern "C" { \ - extern int plugin_is_GPL_compatible (void); \ - extern int plugin_is_GPL_compatible (void) \ - { \ - return 0; \ - } \ - } - -#else - -#define GDB_DECLARE_GPL_COMPATIBLE_READER \ - extern int plugin_is_GPL_compatible (void); \ - extern int plugin_is_GPL_compatible (void) \ - { \ - return 0; \ - } - -#endif - -/* Represents an address on the target system. */ - -typedef unsigned long GDB_CORE_ADDR; - -/* Return status codes. */ - -enum gdb_status { - GDB_FAIL = 0, - GDB_SUCCESS = 1 -}; - -struct gdb_object; -struct gdb_symtab; -struct gdb_block; -struct gdb_symbol_callbacks; - -/* An array of these are used to represent a map from code addresses to line - numbers in the source file. */ - -struct gdb_line_mapping -{ - int line; - GDB_CORE_ADDR pc; -}; - -/* Create a new GDB code object. Each code object can have one or - more symbol tables, each representing a compiled source file. */ - -typedef struct gdb_object *(gdb_object_open) (struct gdb_symbol_callbacks *cb); - -/* The callback used to create new symbol table. CB is the - gdb_symbol_callbacks which the structure is part of. FILE_NAME is - an (optionally NULL) file name to associate with this new symbol - table. - - Returns a new instance to gdb_symtab that can later be passed to - gdb_block_new, gdb_symtab_add_line_mapping and gdb_symtab_close. */ - -typedef struct gdb_symtab *(gdb_symtab_open) (struct gdb_symbol_callbacks *cb, - struct gdb_object *obj, - const char *file_name); - -/* Creates a new block in a given symbol table. A symbol table is a - forest of blocks, each block representing an code address range and - a corresponding (optionally NULL) NAME. In case the block - corresponds to a function, the NAME passed should be the name of - the function. - - If the new block to be created is a child of (i.e. is nested in) - another block, the parent block can be passed in PARENT. SYMTAB is - the symbol table the new block is to belong in. BEGIN, END is the - code address range the block corresponds to. - - Returns a new instance of gdb_block, which, as of now, has no use. - Note that the gdb_block returned must not be freed by the - caller. */ - -typedef struct gdb_block *(gdb_block_open) (struct gdb_symbol_callbacks *cb, - struct gdb_symtab *symtab, - struct gdb_block *parent, - GDB_CORE_ADDR begin, - GDB_CORE_ADDR end, - const char *name); - -/* Adds a PC to line number mapping for the symbol table SYMTAB. - NLINES is the number of elements in LINES, each element - corresponding to one (PC, line) pair. */ - -typedef void (gdb_symtab_add_line_mapping) (struct gdb_symbol_callbacks *cb, - struct gdb_symtab *symtab, - int nlines, - struct gdb_line_mapping *lines); - -/* Close the symtab SYMTAB. This signals to GDB that no more blocks - will be opened on this symtab. */ - -typedef void (gdb_symtab_close) (struct gdb_symbol_callbacks *cb, - struct gdb_symtab *symtab); - - -/* Closes the gdb_object OBJ and adds the emitted information into - GDB's internal structures. Once this is done, the debug - information will be picked up and used; this will usually be the - last operation in gdb_read_debug_info. */ - -typedef void (gdb_object_close) (struct gdb_symbol_callbacks *cb, - struct gdb_object *obj); - -/* Reads LEN bytes from TARGET_MEM in the target's virtual address - space into GDB_BUF. - - Returns GDB_FAIL on failure, and GDB_SUCCESS on success. */ - -typedef enum gdb_status (gdb_target_read) (GDB_CORE_ADDR target_mem, - void *gdb_buf, int len); - -/* The list of callbacks that are passed to read. These callbacks are - to be used to construct the symbol table. The functions have been - described above. */ - -struct gdb_symbol_callbacks -{ - gdb_object_open *object_open; - gdb_symtab_open *symtab_open; - gdb_block_open *block_open; - gdb_symtab_close *symtab_close; - gdb_object_close *object_close; - - gdb_symtab_add_line_mapping *line_mapping_add; - gdb_target_read *target_read; - - /* For internal use by GDB. */ - void *priv_data; -}; - -/* Forward declaration. */ - -struct gdb_reg_value; - -/* A function of this type is used to free a gdb_reg_value. See the - comment on `free' in struct gdb_reg_value. */ - -typedef void (gdb_reg_value_free) (struct gdb_reg_value *); - -/* Denotes the value of a register. */ - -struct gdb_reg_value -{ - /* The size of the register in bytes. The reader need not set this - field. This will be set for (defined) register values being read - from GDB using reg_get. */ - int size; - - /* Set to non-zero if the value for the register is known. The - registers for which the reader does not call reg_set are also - assumed to be undefined */ - int defined; - - /* Since gdb_reg_value is a variable sized structure, it will - usually be allocated on the heap. This function is expected to - contain the corresponding "free" function. - - When a pointer to gdb_reg_value is being sent from GDB to the - reader (via gdb_unwind_reg_get), the reader is expected to call - this function (with the same gdb_reg_value as argument) once it - is done with the value. - - When the function sends the a gdb_reg_value to GDB (via - gdb_unwind_reg_set), it is expected to set this field to point to - an appropriate cleanup routine (or to NULL if no cleanup is - required). */ - gdb_reg_value_free *free; - - /* The value of the register. */ - unsigned char value[1]; -}; - -/* get_frame_id in gdb_reader_funcs is to return a gdb_frame_id - corresponding to the current frame. The registers corresponding to - the current frame can be read using reg_get. Calling get_frame_id - on a particular frame should return the same gdb_frame_id - throughout its lifetime (i.e. till before it gets unwound). One - way to do this is by having the CODE_ADDRESS point to the - function's first instruction and STACK_ADDRESS point to the value - of the stack pointer when entering the function. */ - -struct gdb_frame_id -{ - GDB_CORE_ADDR code_address; - GDB_CORE_ADDR stack_address; -}; - -/* Forward declaration. */ - -struct gdb_unwind_callbacks; - -/* Returns the value of a particular register in the current frame. - The current frame is the frame that needs to be unwound into the - outer (earlier) frame. - - CB is the struct gdb_unwind_callbacks * the callback belongs to. - REGNUM is the DWARF register number of the register that needs to - be unwound. - - Returns the gdb_reg_value corresponding to the register requested. - In case the value of the register has been optimized away or - otherwise unavailable, the defined flag in the returned - gdb_reg_value will be zero. */ - -typedef struct gdb_reg_value *(gdb_unwind_reg_get) - (struct gdb_unwind_callbacks *cb, int regnum); - -/* Sets the previous value of a particular register. REGNUM is the - (DWARF) register number whose value is to be set. VAL is the value - the register is to be set to. - - VAL is *not* copied, so the memory allocated to it cannot be - reused. Once GDB no longer needs the value, it is deallocated - using the FREE function (see gdb_reg_value). - - A register can also be "set" to an undefined value by setting the - defined in VAL to zero. */ - -typedef void (gdb_unwind_reg_set) (struct gdb_unwind_callbacks *cb, int regnum, - struct gdb_reg_value *val); - -/* This struct is passed to unwind in gdb_reader_funcs, and is to be - used to unwind the current frame (current being the frame whose - registers can be read using reg_get) into the earlier frame. The - functions have been described above. */ - -struct gdb_unwind_callbacks -{ - gdb_unwind_reg_get *reg_get; - gdb_unwind_reg_set *reg_set; - gdb_target_read *target_read; - - /* For internal use by GDB. */ - void *priv_data; -}; - -/* Forward declaration. */ - -struct gdb_reader_funcs; - -/* Parse the debug info off a block of memory, pointed to by MEMORY - (already copied to GDB's address space) and MEMORY_SZ bytes long. - The implementation has to use the functions in CB to actually emit - the parsed data into GDB. SELF is the same structure returned by - gdb_init_reader. - - Return GDB_FAIL on failure and GDB_SUCCESS on success. */ - -typedef enum gdb_status (gdb_read_debug_info) (struct gdb_reader_funcs *self, - struct gdb_symbol_callbacks *cb, - void *memory, long memory_sz); - -/* Unwind the current frame, CB is the set of unwind callbacks that - are to be used to do this. - - Return GDB_FAIL on failure and GDB_SUCCESS on success. */ - -typedef enum gdb_status (gdb_unwind_frame) (struct gdb_reader_funcs *self, - struct gdb_unwind_callbacks *cb); - -/* Return the frame ID corresponding to the current frame, using C to - read the current register values. See the comment on struct - gdb_frame_id. */ - -typedef struct gdb_frame_id (gdb_get_frame_id) (struct gdb_reader_funcs *self, - struct gdb_unwind_callbacks *c); - -/* Called when a reader is being unloaded. This function should also - free SELF, if required. */ - -typedef void (gdb_destroy_reader) (struct gdb_reader_funcs *self); - -/* Called when the reader is loaded. Must either return a properly - populated gdb_reader_funcs or NULL. The memory allocated for the - gdb_reader_funcs is to be managed by the reader itself (i.e. if it - is allocated from the heap, it must also be freed in - gdb_destroy_reader). */ - -extern struct gdb_reader_funcs *gdb_init_reader (void); - -/* Pointer to the functions which implement the reader's - functionality. The individual functions have been documented - above. - - None of the fields are optional. */ - -struct gdb_reader_funcs -{ - /* Must be set to GDB_READER_INTERFACE_VERSION. */ - int reader_version; - - /* For use by the reader. */ - void *priv_data; - - gdb_read_debug_info *read; - gdb_unwind_frame *unwind; - gdb_get_frame_id *get_frame_id; - gdb_destroy_reader *destroy; -}; - -#ifdef __cplusplus -} /* extern "C" */ -#endif - -#endif diff --git a/arduino/hardware/tools/avr/include/libiberty/ansidecl.h b/arduino/hardware/tools/avr/include/libiberty/ansidecl.h deleted file mode 100644 index 6e4bfc2..0000000 --- a/arduino/hardware/tools/avr/include/libiberty/ansidecl.h +++ /dev/null @@ -1,329 +0,0 @@ -/* ANSI and traditional C compatability macros - Copyright (C) 1991-2015 Free Software Foundation, Inc. - This file is part of the GNU C Library. - -This program is free software; you can redistribute it and/or modify -it under the terms of the GNU General Public License as published by -the Free Software Foundation; either version 2 of the License, or -(at your option) any later version. - -This program is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU General Public License for more details. - -You should have received a copy of the GNU General Public License -along with this program; if not, write to the Free Software -Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ - -/* ANSI and traditional C compatibility macros - - ANSI C is assumed if __STDC__ is #defined. - - Macro ANSI C definition Traditional C definition - ----- ---- - ---------- ----------- - ---------- - PTR `void *' `char *' - const not defined `' - volatile not defined `' - signed not defined `' - - For ease of writing code which uses GCC extensions but needs to be - portable to other compilers, we provide the GCC_VERSION macro that - simplifies testing __GNUC__ and __GNUC_MINOR__ together, and various - wrappers around __attribute__. Also, __extension__ will be #defined - to nothing if it doesn't work. See below. */ - -#ifndef _ANSIDECL_H -#define _ANSIDECL_H 1 - -#ifdef __cplusplus -extern "C" { -#endif - -/* Every source file includes this file, - so they will all get the switch for lint. */ -/* LINTLIBRARY */ - -/* Using MACRO(x,y) in cpp #if conditionals does not work with some - older preprocessors. Thus we can't define something like this: - -#define HAVE_GCC_VERSION(MAJOR, MINOR) \ - (__GNUC__ > (MAJOR) || (__GNUC__ == (MAJOR) && __GNUC_MINOR__ >= (MINOR))) - -and then test "#if HAVE_GCC_VERSION(2,7)". - -So instead we use the macro below and test it against specific values. */ - -/* This macro simplifies testing whether we are using gcc, and if it - is of a particular minimum version. (Both major & minor numbers are - significant.) This macro will evaluate to 0 if we are not using - gcc at all. */ -#ifndef GCC_VERSION -#define GCC_VERSION (__GNUC__ * 1000 + __GNUC_MINOR__) -#endif /* GCC_VERSION */ - -#if defined (__STDC__) || defined(__cplusplus) || defined (_AIX) || (defined (__mips) && defined (_SYSTYPE_SVR4)) || defined(_WIN32) -/* All known AIX compilers implement these things (but don't always - define __STDC__). The RISC/OS MIPS compiler defines these things - in SVR4 mode, but does not define __STDC__. */ -/* eraxxon@alumni.rice.edu: The Compaq C++ compiler, unlike many other - C++ compilers, does not define __STDC__, though it acts as if this - was so. (Verified versions: 5.7, 6.2, 6.3, 6.5) */ - -#define PTR void * - -#undef const -#undef volatile -#undef signed - -/* inline requires special treatment; it's in C99, and GCC >=2.7 supports - it too, but it's not in C89. */ -#undef inline -#if __STDC_VERSION__ >= 199901L || defined(__cplusplus) || (defined(__SUNPRO_C) && defined(__C99FEATURES__)) -/* it's a keyword */ -#else -# if GCC_VERSION >= 2007 -# define inline __inline__ /* __inline__ prevents -pedantic warnings */ -# else -# define inline /* nothing */ -# endif -#endif - -#else /* Not ANSI C. */ - -#define PTR char * - -/* some systems define these in header files for non-ansi mode */ -#undef const -#undef volatile -#undef signed -#undef inline -#define const -#define volatile -#define signed -#define inline - -#endif /* ANSI C. */ - -/* Define macros for some gcc attributes. This permits us to use the - macros freely, and know that they will come into play for the - version of gcc in which they are supported. */ - -#if (GCC_VERSION < 2007) -# define __attribute__(x) -#endif - -/* Attribute __malloc__ on functions was valid as of gcc 2.96. */ -#ifndef ATTRIBUTE_MALLOC -# if (GCC_VERSION >= 2096) -# define ATTRIBUTE_MALLOC __attribute__ ((__malloc__)) -# else -# define ATTRIBUTE_MALLOC -# endif /* GNUC >= 2.96 */ -#endif /* ATTRIBUTE_MALLOC */ - -/* Attributes on labels were valid as of gcc 2.93 and g++ 4.5. For - g++ an attribute on a label must be followed by a semicolon. */ -#ifndef ATTRIBUTE_UNUSED_LABEL -# ifndef __cplusplus -# if GCC_VERSION >= 2093 -# define ATTRIBUTE_UNUSED_LABEL ATTRIBUTE_UNUSED -# else -# define ATTRIBUTE_UNUSED_LABEL -# endif -# else -# if GCC_VERSION >= 4005 -# define ATTRIBUTE_UNUSED_LABEL ATTRIBUTE_UNUSED ; -# else -# define ATTRIBUTE_UNUSED_LABEL -# endif -# endif -#endif - -/* Similarly to ARG_UNUSED below. Prior to GCC 3.4, the C++ frontend - couldn't parse attributes placed after the identifier name, and now - the entire compiler is built with C++. */ -#ifndef ATTRIBUTE_UNUSED -#if GCC_VERSION >= 3004 -# define ATTRIBUTE_UNUSED __attribute__ ((__unused__)) -#else -#define ATTRIBUTE_UNUSED -#endif -#endif /* ATTRIBUTE_UNUSED */ - -/* Before GCC 3.4, the C++ frontend couldn't parse attributes placed after the - identifier name. */ -#if ! defined(__cplusplus) || (GCC_VERSION >= 3004) -# define ARG_UNUSED(NAME) NAME ATTRIBUTE_UNUSED -#else /* !__cplusplus || GNUC >= 3.4 */ -# define ARG_UNUSED(NAME) NAME -#endif /* !__cplusplus || GNUC >= 3.4 */ - -#ifndef ATTRIBUTE_NORETURN -#define ATTRIBUTE_NORETURN __attribute__ ((__noreturn__)) -#endif /* ATTRIBUTE_NORETURN */ - -/* Attribute `nonnull' was valid as of gcc 3.3. */ -#ifndef ATTRIBUTE_NONNULL -# if (GCC_VERSION >= 3003) -# define ATTRIBUTE_NONNULL(m) __attribute__ ((__nonnull__ (m))) -# else -# define ATTRIBUTE_NONNULL(m) -# endif /* GNUC >= 3.3 */ -#endif /* ATTRIBUTE_NONNULL */ - -/* Attribute `returns_nonnull' was valid as of gcc 4.9. */ -#ifndef ATTRIBUTE_RETURNS_NONNULL -# if (GCC_VERSION >= 4009) -# define ATTRIBUTE_RETURNS_NONNULL __attribute__ ((__returns_nonnull__)) -# else -# define ATTRIBUTE_RETURNS_NONNULL -# endif /* GNUC >= 4.9 */ -#endif /* ATTRIBUTE_RETURNS_NONNULL */ - -/* Attribute `pure' was valid as of gcc 3.0. */ -#ifndef ATTRIBUTE_PURE -# if (GCC_VERSION >= 3000) -# define ATTRIBUTE_PURE __attribute__ ((__pure__)) -# else -# define ATTRIBUTE_PURE -# endif /* GNUC >= 3.0 */ -#endif /* ATTRIBUTE_PURE */ - -/* Use ATTRIBUTE_PRINTF when the format specifier must not be NULL. - This was the case for the `printf' format attribute by itself - before GCC 3.3, but as of 3.3 we need to add the `nonnull' - attribute to retain this behavior. */ -#ifndef ATTRIBUTE_PRINTF -#define ATTRIBUTE_PRINTF(m, n) __attribute__ ((__format__ (__printf__, m, n))) ATTRIBUTE_NONNULL(m) -#define ATTRIBUTE_PRINTF_1 ATTRIBUTE_PRINTF(1, 2) -#define ATTRIBUTE_PRINTF_2 ATTRIBUTE_PRINTF(2, 3) -#define ATTRIBUTE_PRINTF_3 ATTRIBUTE_PRINTF(3, 4) -#define ATTRIBUTE_PRINTF_4 ATTRIBUTE_PRINTF(4, 5) -#define ATTRIBUTE_PRINTF_5 ATTRIBUTE_PRINTF(5, 6) -#endif /* ATTRIBUTE_PRINTF */ - -/* Use ATTRIBUTE_FPTR_PRINTF when the format attribute is to be set on - a function pointer. Format attributes were allowed on function - pointers as of gcc 3.1. */ -#ifndef ATTRIBUTE_FPTR_PRINTF -# if (GCC_VERSION >= 3001) -# define ATTRIBUTE_FPTR_PRINTF(m, n) ATTRIBUTE_PRINTF(m, n) -# else -# define ATTRIBUTE_FPTR_PRINTF(m, n) -# endif /* GNUC >= 3.1 */ -# define ATTRIBUTE_FPTR_PRINTF_1 ATTRIBUTE_FPTR_PRINTF(1, 2) -# define ATTRIBUTE_FPTR_PRINTF_2 ATTRIBUTE_FPTR_PRINTF(2, 3) -# define ATTRIBUTE_FPTR_PRINTF_3 ATTRIBUTE_FPTR_PRINTF(3, 4) -# define ATTRIBUTE_FPTR_PRINTF_4 ATTRIBUTE_FPTR_PRINTF(4, 5) -# define ATTRIBUTE_FPTR_PRINTF_5 ATTRIBUTE_FPTR_PRINTF(5, 6) -#endif /* ATTRIBUTE_FPTR_PRINTF */ - -/* Use ATTRIBUTE_NULL_PRINTF when the format specifier may be NULL. A - NULL format specifier was allowed as of gcc 3.3. */ -#ifndef ATTRIBUTE_NULL_PRINTF -# if (GCC_VERSION >= 3003) -# define ATTRIBUTE_NULL_PRINTF(m, n) __attribute__ ((__format__ (__printf__, m, n))) -# else -# define ATTRIBUTE_NULL_PRINTF(m, n) -# endif /* GNUC >= 3.3 */ -# define ATTRIBUTE_NULL_PRINTF_1 ATTRIBUTE_NULL_PRINTF(1, 2) -# define ATTRIBUTE_NULL_PRINTF_2 ATTRIBUTE_NULL_PRINTF(2, 3) -# define ATTRIBUTE_NULL_PRINTF_3 ATTRIBUTE_NULL_PRINTF(3, 4) -# define ATTRIBUTE_NULL_PRINTF_4 ATTRIBUTE_NULL_PRINTF(4, 5) -# define ATTRIBUTE_NULL_PRINTF_5 ATTRIBUTE_NULL_PRINTF(5, 6) -#endif /* ATTRIBUTE_NULL_PRINTF */ - -/* Attribute `sentinel' was valid as of gcc 3.5. */ -#ifndef ATTRIBUTE_SENTINEL -# if (GCC_VERSION >= 3005) -# define ATTRIBUTE_SENTINEL __attribute__ ((__sentinel__)) -# else -# define ATTRIBUTE_SENTINEL -# endif /* GNUC >= 3.5 */ -#endif /* ATTRIBUTE_SENTINEL */ - - -#ifndef ATTRIBUTE_ALIGNED_ALIGNOF -# if (GCC_VERSION >= 3000) -# define ATTRIBUTE_ALIGNED_ALIGNOF(m) __attribute__ ((__aligned__ (__alignof__ (m)))) -# else -# define ATTRIBUTE_ALIGNED_ALIGNOF(m) -# endif /* GNUC >= 3.0 */ -#endif /* ATTRIBUTE_ALIGNED_ALIGNOF */ - -/* Useful for structures whose layout must much some binary specification - regardless of the alignment and padding qualities of the compiler. */ -#ifndef ATTRIBUTE_PACKED -# define ATTRIBUTE_PACKED __attribute__ ((packed)) -#endif - -/* Attribute `hot' and `cold' was valid as of gcc 4.3. */ -#ifndef ATTRIBUTE_COLD -# if (GCC_VERSION >= 4003) -# define ATTRIBUTE_COLD __attribute__ ((__cold__)) -# else -# define ATTRIBUTE_COLD -# endif /* GNUC >= 4.3 */ -#endif /* ATTRIBUTE_COLD */ -#ifndef ATTRIBUTE_HOT -# if (GCC_VERSION >= 4003) -# define ATTRIBUTE_HOT __attribute__ ((__hot__)) -# else -# define ATTRIBUTE_HOT -# endif /* GNUC >= 4.3 */ -#endif /* ATTRIBUTE_HOT */ - -/* Attribute 'no_sanitize_undefined' was valid as of gcc 4.9. */ -#ifndef ATTRIBUTE_NO_SANITIZE_UNDEFINED -# if (GCC_VERSION >= 4009) -# define ATTRIBUTE_NO_SANITIZE_UNDEFINED __attribute__ ((no_sanitize_undefined)) -# else -# define ATTRIBUTE_NO_SANITIZE_UNDEFINED -# endif /* GNUC >= 4.9 */ -#endif /* ATTRIBUTE_NO_SANITIZE_UNDEFINED */ - -/* We use __extension__ in some places to suppress -pedantic warnings - about GCC extensions. This feature didn't work properly before - gcc 2.8. */ -#if GCC_VERSION < 2008 -#define __extension__ -#endif - -/* This is used to declare a const variable which should be visible - outside of the current compilation unit. Use it as - EXPORTED_CONST int i = 1; - This is because the semantics of const are different in C and C++. - "extern const" is permitted in C but it looks strange, and gcc - warns about it when -Wc++-compat is not used. */ -#ifdef __cplusplus -#define EXPORTED_CONST extern const -#else -#define EXPORTED_CONST const -#endif - -/* Be conservative and only use enum bitfields with C++ or GCC. - FIXME: provide a complete autoconf test for buggy enum bitfields. */ - -#ifdef __cplusplus -#define ENUM_BITFIELD(TYPE) enum TYPE -#elif (GCC_VERSION > 2000) -#define ENUM_BITFIELD(TYPE) __extension__ enum TYPE -#else -#define ENUM_BITFIELD(TYPE) unsigned int -#endif - - /* This is used to mark a class or virtual function as final. */ -#if __cplusplus >= 201103L -#define GCC_FINAL final -#elif GCC_VERSION >= 4007 -#define GCC_FINAL __final -#else -#define GCC_FINAL -#endif - -#ifdef __cplusplus -} -#endif - -#endif /* ansidecl.h */ diff --git a/arduino/hardware/tools/avr/include/libiberty/demangle.h b/arduino/hardware/tools/avr/include/libiberty/demangle.h deleted file mode 100644 index e415de0..0000000 --- a/arduino/hardware/tools/avr/include/libiberty/demangle.h +++ /dev/null @@ -1,685 +0,0 @@ -/* Defs for interface to demanglers. - Copyright (C) 1992-2015 Free Software Foundation, Inc. - - This program is free software; you can redistribute it and/or - modify it under the terms of the GNU Library General Public License - as published by the Free Software Foundation; either version 2, or - (at your option) any later version. - - In addition to the permissions in the GNU Library General Public - License, the Free Software Foundation gives you unlimited - permission to link the compiled version of this file into - combinations with other programs, and to distribute those - combinations without any restriction coming from the use of this - file. (The Library Public License restrictions do apply in other - respects; for example, they cover modification of the file, and - distribution when not linked into a combined executable.) - - This program is distributed in the hope that it will be useful, but - WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - Library General Public License for more details. - - You should have received a copy of the GNU Library General Public - License along with this program; if not, write to the Free Software - Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA - 02110-1301, USA. */ - - -#if !defined (DEMANGLE_H) -#define DEMANGLE_H - -#include "libiberty.h" - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -/* Options passed to cplus_demangle (in 2nd parameter). */ - -#define DMGL_NO_OPTS 0 /* For readability... */ -#define DMGL_PARAMS (1 << 0) /* Include function args */ -#define DMGL_ANSI (1 << 1) /* Include const, volatile, etc */ -#define DMGL_JAVA (1 << 2) /* Demangle as Java rather than C++. */ -#define DMGL_VERBOSE (1 << 3) /* Include implementation details. */ -#define DMGL_TYPES (1 << 4) /* Also try to demangle type encodings. */ -#define DMGL_RET_POSTFIX (1 << 5) /* Print function return types (when - present) after function signature. - It applies only to the toplevel - function type. */ -#define DMGL_RET_DROP (1 << 6) /* Suppress printing function return - types, even if present. It applies - only to the toplevel function type. - */ - -#define DMGL_AUTO (1 << 8) -#define DMGL_GNU (1 << 9) -#define DMGL_LUCID (1 << 10) -#define DMGL_ARM (1 << 11) -#define DMGL_HP (1 << 12) /* For the HP aCC compiler; - same as ARM except for - template arguments, etc. */ -#define DMGL_EDG (1 << 13) -#define DMGL_GNU_V3 (1 << 14) -#define DMGL_GNAT (1 << 15) -#define DMGL_DLANG (1 << 16) - -/* If none of these are set, use 'current_demangling_style' as the default. */ -#define DMGL_STYLE_MASK (DMGL_AUTO|DMGL_GNU|DMGL_LUCID|DMGL_ARM|DMGL_HP|DMGL_EDG|DMGL_GNU_V3|DMGL_JAVA|DMGL_GNAT|DMGL_DLANG) - -/* Enumeration of possible demangling styles. - - Lucid and ARM styles are still kept logically distinct, even though - they now both behave identically. The resulting style is actual the - union of both. I.E. either style recognizes both "__pt__" and "__rf__" - for operator "->", even though the first is lucid style and the second - is ARM style. (FIXME?) */ - -extern enum demangling_styles -{ - no_demangling = -1, - unknown_demangling = 0, - auto_demangling = DMGL_AUTO, - gnu_demangling = DMGL_GNU, - lucid_demangling = DMGL_LUCID, - arm_demangling = DMGL_ARM, - hp_demangling = DMGL_HP, - edg_demangling = DMGL_EDG, - gnu_v3_demangling = DMGL_GNU_V3, - java_demangling = DMGL_JAVA, - gnat_demangling = DMGL_GNAT, - dlang_demangling = DMGL_DLANG -} current_demangling_style; - -/* Define string names for the various demangling styles. */ - -#define NO_DEMANGLING_STYLE_STRING "none" -#define AUTO_DEMANGLING_STYLE_STRING "auto" -#define GNU_DEMANGLING_STYLE_STRING "gnu" -#define LUCID_DEMANGLING_STYLE_STRING "lucid" -#define ARM_DEMANGLING_STYLE_STRING "arm" -#define HP_DEMANGLING_STYLE_STRING "hp" -#define EDG_DEMANGLING_STYLE_STRING "edg" -#define GNU_V3_DEMANGLING_STYLE_STRING "gnu-v3" -#define JAVA_DEMANGLING_STYLE_STRING "java" -#define GNAT_DEMANGLING_STYLE_STRING "gnat" -#define DLANG_DEMANGLING_STYLE_STRING "dlang" - -/* Some macros to test what demangling style is active. */ - -#define CURRENT_DEMANGLING_STYLE current_demangling_style -#define AUTO_DEMANGLING (((int) CURRENT_DEMANGLING_STYLE) & DMGL_AUTO) -#define GNU_DEMANGLING (((int) CURRENT_DEMANGLING_STYLE) & DMGL_GNU) -#define LUCID_DEMANGLING (((int) CURRENT_DEMANGLING_STYLE) & DMGL_LUCID) -#define ARM_DEMANGLING (((int) CURRENT_DEMANGLING_STYLE) & DMGL_ARM) -#define HP_DEMANGLING (((int) CURRENT_DEMANGLING_STYLE) & DMGL_HP) -#define EDG_DEMANGLING (((int) CURRENT_DEMANGLING_STYLE) & DMGL_EDG) -#define GNU_V3_DEMANGLING (((int) CURRENT_DEMANGLING_STYLE) & DMGL_GNU_V3) -#define JAVA_DEMANGLING (((int) CURRENT_DEMANGLING_STYLE) & DMGL_JAVA) -#define GNAT_DEMANGLING (((int) CURRENT_DEMANGLING_STYLE) & DMGL_GNAT) -#define DLANG_DEMANGLING (((int) CURRENT_DEMANGLING_STYLE) & DMGL_DLANG) - -/* Provide information about the available demangle styles. This code is - pulled from gdb into libiberty because it is useful to binutils also. */ - -extern const struct demangler_engine -{ - const char *const demangling_style_name; - const enum demangling_styles demangling_style; - const char *const demangling_style_doc; -} libiberty_demanglers[]; - -extern char * -cplus_demangle (const char *mangled, int options); - -extern int -cplus_demangle_opname (const char *opname, char *result, int options); - -extern const char * -cplus_mangle_opname (const char *opname, int options); - -/* Note: This sets global state. FIXME if you care about multi-threading. */ - -extern void -set_cplus_marker_for_demangling (int ch); - -extern enum demangling_styles -cplus_demangle_set_style (enum demangling_styles style); - -extern enum demangling_styles -cplus_demangle_name_to_style (const char *name); - -/* Callback typedef for allocation-less demangler interfaces. */ -typedef void (*demangle_callbackref) (const char *, size_t, void *); - -/* V3 ABI demangling entry points, defined in cp-demangle.c. Callback - variants return non-zero on success, zero on error. char* variants - return a string allocated by malloc on success, NULL on error. */ -extern int -cplus_demangle_v3_callback (const char *mangled, int options, - demangle_callbackref callback, void *opaque); - -extern char* -cplus_demangle_v3 (const char *mangled, int options); - -extern int -java_demangle_v3_callback (const char *mangled, - demangle_callbackref callback, void *opaque); - -extern char* -java_demangle_v3 (const char *mangled); - -char * -ada_demangle (const char *mangled, int options); - -extern char * -dlang_demangle (const char *mangled, int options); - -enum gnu_v3_ctor_kinds { - gnu_v3_complete_object_ctor = 1, - gnu_v3_base_object_ctor, - gnu_v3_complete_object_allocating_ctor, - /* These are not part of the V3 ABI. Unified constructors are generated - as a speed-for-space optimization when the -fdeclone-ctor-dtor option - is used, and are always internal symbols. */ - gnu_v3_unified_ctor, - gnu_v3_object_ctor_group -}; - -/* Return non-zero iff NAME is the mangled form of a constructor name - in the G++ V3 ABI demangling style. Specifically, return an `enum - gnu_v3_ctor_kinds' value indicating what kind of constructor - it is. */ -extern enum gnu_v3_ctor_kinds - is_gnu_v3_mangled_ctor (const char *name); - - -enum gnu_v3_dtor_kinds { - gnu_v3_deleting_dtor = 1, - gnu_v3_complete_object_dtor, - gnu_v3_base_object_dtor, - /* These are not part of the V3 ABI. Unified destructors are generated - as a speed-for-space optimization when the -fdeclone-ctor-dtor option - is used, and are always internal symbols. */ - gnu_v3_unified_dtor, - gnu_v3_object_dtor_group -}; - -/* Return non-zero iff NAME is the mangled form of a destructor name - in the G++ V3 ABI demangling style. Specifically, return an `enum - gnu_v3_dtor_kinds' value, indicating what kind of destructor - it is. */ -extern enum gnu_v3_dtor_kinds - is_gnu_v3_mangled_dtor (const char *name); - -/* The V3 demangler works in two passes. The first pass builds a tree - representation of the mangled name, and the second pass turns the - tree representation into a demangled string. Here we define an - interface to permit a caller to build their own tree - representation, which they can pass to the demangler to get a - demangled string. This can be used to canonicalize user input into - something which the demangler might output. It could also be used - by other demanglers in the future. */ - -/* These are the component types which may be found in the tree. Many - component types have one or two subtrees, referred to as left and - right (a component type with only one subtree puts it in the left - subtree). */ - -enum demangle_component_type -{ - /* A name, with a length and a pointer to a string. */ - DEMANGLE_COMPONENT_NAME, - /* A qualified name. The left subtree is a class or namespace or - some such thing, and the right subtree is a name qualified by - that class. */ - DEMANGLE_COMPONENT_QUAL_NAME, - /* A local name. The left subtree describes a function, and the - right subtree is a name which is local to that function. */ - DEMANGLE_COMPONENT_LOCAL_NAME, - /* A typed name. The left subtree is a name, and the right subtree - describes that name as a function. */ - DEMANGLE_COMPONENT_TYPED_NAME, - /* A template. The left subtree is a template name, and the right - subtree is a template argument list. */ - DEMANGLE_COMPONENT_TEMPLATE, - /* A template parameter. This holds a number, which is the template - parameter index. */ - DEMANGLE_COMPONENT_TEMPLATE_PARAM, - /* A function parameter. This holds a number, which is the index. */ - DEMANGLE_COMPONENT_FUNCTION_PARAM, - /* A constructor. This holds a name and the kind of - constructor. */ - DEMANGLE_COMPONENT_CTOR, - /* A destructor. This holds a name and the kind of destructor. */ - DEMANGLE_COMPONENT_DTOR, - /* A vtable. This has one subtree, the type for which this is a - vtable. */ - DEMANGLE_COMPONENT_VTABLE, - /* A VTT structure. This has one subtree, the type for which this - is a VTT. */ - DEMANGLE_COMPONENT_VTT, - /* A construction vtable. The left subtree is the type for which - this is a vtable, and the right subtree is the derived type for - which this vtable is built. */ - DEMANGLE_COMPONENT_CONSTRUCTION_VTABLE, - /* A typeinfo structure. This has one subtree, the type for which - this is the tpeinfo structure. */ - DEMANGLE_COMPONENT_TYPEINFO, - /* A typeinfo name. This has one subtree, the type for which this - is the typeinfo name. */ - DEMANGLE_COMPONENT_TYPEINFO_NAME, - /* A typeinfo function. This has one subtree, the type for which - this is the tpyeinfo function. */ - DEMANGLE_COMPONENT_TYPEINFO_FN, - /* A thunk. This has one subtree, the name for which this is a - thunk. */ - DEMANGLE_COMPONENT_THUNK, - /* A virtual thunk. This has one subtree, the name for which this - is a virtual thunk. */ - DEMANGLE_COMPONENT_VIRTUAL_THUNK, - /* A covariant thunk. This has one subtree, the name for which this - is a covariant thunk. */ - DEMANGLE_COMPONENT_COVARIANT_THUNK, - /* A Java class. This has one subtree, the type. */ - DEMANGLE_COMPONENT_JAVA_CLASS, - /* A guard variable. This has one subtree, the name for which this - is a guard variable. */ - DEMANGLE_COMPONENT_GUARD, - /* The init and wrapper functions for C++11 thread_local variables. */ - DEMANGLE_COMPONENT_TLS_INIT, - DEMANGLE_COMPONENT_TLS_WRAPPER, - /* A reference temporary. This has one subtree, the name for which - this is a temporary. */ - DEMANGLE_COMPONENT_REFTEMP, - /* A hidden alias. This has one subtree, the encoding for which it - is providing alternative linkage. */ - DEMANGLE_COMPONENT_HIDDEN_ALIAS, - /* A standard substitution. This holds the name of the - substitution. */ - DEMANGLE_COMPONENT_SUB_STD, - /* The restrict qualifier. The one subtree is the type which is - being qualified. */ - DEMANGLE_COMPONENT_RESTRICT, - /* The volatile qualifier. The one subtree is the type which is - being qualified. */ - DEMANGLE_COMPONENT_VOLATILE, - /* The const qualifier. The one subtree is the type which is being - qualified. */ - DEMANGLE_COMPONENT_CONST, - /* The restrict qualifier modifying a member function. The one - subtree is the type which is being qualified. */ - DEMANGLE_COMPONENT_RESTRICT_THIS, - /* The volatile qualifier modifying a member function. The one - subtree is the type which is being qualified. */ - DEMANGLE_COMPONENT_VOLATILE_THIS, - /* The const qualifier modifying a member function. The one subtree - is the type which is being qualified. */ - DEMANGLE_COMPONENT_CONST_THIS, - /* C++11 A reference modifying a member function. The one subtree is the - type which is being referenced. */ - DEMANGLE_COMPONENT_REFERENCE_THIS, - /* C++11: An rvalue reference modifying a member function. The one - subtree is the type which is being referenced. */ - DEMANGLE_COMPONENT_RVALUE_REFERENCE_THIS, - /* A vendor qualifier. The left subtree is the type which is being - qualified, and the right subtree is the name of the - qualifier. */ - DEMANGLE_COMPONENT_VENDOR_TYPE_QUAL, - /* A pointer. The one subtree is the type which is being pointed - to. */ - DEMANGLE_COMPONENT_POINTER, - /* A reference. The one subtree is the type which is being - referenced. */ - DEMANGLE_COMPONENT_REFERENCE, - /* C++0x: An rvalue reference. The one subtree is the type which is - being referenced. */ - DEMANGLE_COMPONENT_RVALUE_REFERENCE, - /* A complex type. The one subtree is the base type. */ - DEMANGLE_COMPONENT_COMPLEX, - /* An imaginary type. The one subtree is the base type. */ - DEMANGLE_COMPONENT_IMAGINARY, - /* A builtin type. This holds the builtin type information. */ - DEMANGLE_COMPONENT_BUILTIN_TYPE, - /* A vendor's builtin type. This holds the name of the type. */ - DEMANGLE_COMPONENT_VENDOR_TYPE, - /* A function type. The left subtree is the return type. The right - subtree is a list of ARGLIST nodes. Either or both may be - NULL. */ - DEMANGLE_COMPONENT_FUNCTION_TYPE, - /* An array type. The left subtree is the dimension, which may be - NULL, or a string (represented as DEMANGLE_COMPONENT_NAME), or an - expression. The right subtree is the element type. */ - DEMANGLE_COMPONENT_ARRAY_TYPE, - /* A pointer to member type. The left subtree is the class type, - and the right subtree is the member type. CV-qualifiers appear - on the latter. */ - DEMANGLE_COMPONENT_PTRMEM_TYPE, - /* A fixed-point type. */ - DEMANGLE_COMPONENT_FIXED_TYPE, - /* A vector type. The left subtree is the number of elements, - the right subtree is the element type. */ - DEMANGLE_COMPONENT_VECTOR_TYPE, - /* An argument list. The left subtree is the current argument, and - the right subtree is either NULL or another ARGLIST node. */ - DEMANGLE_COMPONENT_ARGLIST, - /* A template argument list. The left subtree is the current - template argument, and the right subtree is either NULL or - another TEMPLATE_ARGLIST node. */ - DEMANGLE_COMPONENT_TEMPLATE_ARGLIST, - /* An initializer list. The left subtree is either an explicit type or - NULL, and the right subtree is a DEMANGLE_COMPONENT_ARGLIST. */ - DEMANGLE_COMPONENT_INITIALIZER_LIST, - /* An operator. This holds information about a standard - operator. */ - DEMANGLE_COMPONENT_OPERATOR, - /* An extended operator. This holds the number of arguments, and - the name of the extended operator. */ - DEMANGLE_COMPONENT_EXTENDED_OPERATOR, - /* A typecast, represented as a unary operator. The one subtree is - the type to which the argument should be cast. */ - DEMANGLE_COMPONENT_CAST, - /* A nullary expression. The left subtree is the operator. */ - DEMANGLE_COMPONENT_NULLARY, - /* A unary expression. The left subtree is the operator, and the - right subtree is the single argument. */ - DEMANGLE_COMPONENT_UNARY, - /* A binary expression. The left subtree is the operator, and the - right subtree is a BINARY_ARGS. */ - DEMANGLE_COMPONENT_BINARY, - /* Arguments to a binary expression. The left subtree is the first - argument, and the right subtree is the second argument. */ - DEMANGLE_COMPONENT_BINARY_ARGS, - /* A trinary expression. The left subtree is the operator, and the - right subtree is a TRINARY_ARG1. */ - DEMANGLE_COMPONENT_TRINARY, - /* Arguments to a trinary expression. The left subtree is the first - argument, and the right subtree is a TRINARY_ARG2. */ - DEMANGLE_COMPONENT_TRINARY_ARG1, - /* More arguments to a trinary expression. The left subtree is the - second argument, and the right subtree is the third argument. */ - DEMANGLE_COMPONENT_TRINARY_ARG2, - /* A literal. The left subtree is the type, and the right subtree - is the value, represented as a DEMANGLE_COMPONENT_NAME. */ - DEMANGLE_COMPONENT_LITERAL, - /* A negative literal. Like LITERAL, but the value is negated. - This is a minor hack: the NAME used for LITERAL points directly - to the mangled string, but since negative numbers are mangled - using 'n' instead of '-', we want a way to indicate a negative - number which involves neither modifying the mangled string nor - allocating a new copy of the literal in memory. */ - DEMANGLE_COMPONENT_LITERAL_NEG, - /* A libgcj compiled resource. The left subtree is the name of the - resource. */ - DEMANGLE_COMPONENT_JAVA_RESOURCE, - /* A name formed by the concatenation of two parts. The left - subtree is the first part and the right subtree the second. */ - DEMANGLE_COMPONENT_COMPOUND_NAME, - /* A name formed by a single character. */ - DEMANGLE_COMPONENT_CHARACTER, - /* A number. */ - DEMANGLE_COMPONENT_NUMBER, - /* A decltype type. */ - DEMANGLE_COMPONENT_DECLTYPE, - /* Global constructors keyed to name. */ - DEMANGLE_COMPONENT_GLOBAL_CONSTRUCTORS, - /* Global destructors keyed to name. */ - DEMANGLE_COMPONENT_GLOBAL_DESTRUCTORS, - /* A lambda closure type. */ - DEMANGLE_COMPONENT_LAMBDA, - /* A default argument scope. */ - DEMANGLE_COMPONENT_DEFAULT_ARG, - /* An unnamed type. */ - DEMANGLE_COMPONENT_UNNAMED_TYPE, - /* A transactional clone. This has one subtree, the encoding for - which it is providing alternative linkage. */ - DEMANGLE_COMPONENT_TRANSACTION_CLONE, - /* A non-transactional clone entry point. In the i386/x86_64 abi, - the unmangled symbol of a tm_callable becomes a thunk and the - non-transactional function version is mangled thus. */ - DEMANGLE_COMPONENT_NONTRANSACTION_CLONE, - /* A pack expansion. */ - DEMANGLE_COMPONENT_PACK_EXPANSION, - /* A name with an ABI tag. */ - DEMANGLE_COMPONENT_TAGGED_NAME, - /* A cloned function. */ - DEMANGLE_COMPONENT_CLONE -}; - -/* Types which are only used internally. */ - -struct demangle_operator_info; -struct demangle_builtin_type_info; - -/* A node in the tree representation is an instance of a struct - demangle_component. Note that the field names of the struct are - not well protected against macros defined by the file including - this one. We can fix this if it ever becomes a problem. */ - -struct demangle_component -{ - /* The type of this component. */ - enum demangle_component_type type; - - union - { - /* For DEMANGLE_COMPONENT_NAME. */ - struct - { - /* A pointer to the name (which need not NULL terminated) and - its length. */ - const char *s; - int len; - } s_name; - - /* For DEMANGLE_COMPONENT_OPERATOR. */ - struct - { - /* Operator. */ - const struct demangle_operator_info *op; - } s_operator; - - /* For DEMANGLE_COMPONENT_EXTENDED_OPERATOR. */ - struct - { - /* Number of arguments. */ - int args; - /* Name. */ - struct demangle_component *name; - } s_extended_operator; - - /* For DEMANGLE_COMPONENT_FIXED_TYPE. */ - struct - { - /* The length, indicated by a C integer type name. */ - struct demangle_component *length; - /* _Accum or _Fract? */ - short accum; - /* Saturating or not? */ - short sat; - } s_fixed; - - /* For DEMANGLE_COMPONENT_CTOR. */ - struct - { - /* Kind of constructor. */ - enum gnu_v3_ctor_kinds kind; - /* Name. */ - struct demangle_component *name; - } s_ctor; - - /* For DEMANGLE_COMPONENT_DTOR. */ - struct - { - /* Kind of destructor. */ - enum gnu_v3_dtor_kinds kind; - /* Name. */ - struct demangle_component *name; - } s_dtor; - - /* For DEMANGLE_COMPONENT_BUILTIN_TYPE. */ - struct - { - /* Builtin type. */ - const struct demangle_builtin_type_info *type; - } s_builtin; - - /* For DEMANGLE_COMPONENT_SUB_STD. */ - struct - { - /* Standard substitution string. */ - const char* string; - /* Length of string. */ - int len; - } s_string; - - /* For DEMANGLE_COMPONENT_*_PARAM. */ - struct - { - /* Parameter index. */ - long number; - } s_number; - - /* For DEMANGLE_COMPONENT_CHARACTER. */ - struct - { - int character; - } s_character; - - /* For other types. */ - struct - { - /* Left (or only) subtree. */ - struct demangle_component *left; - /* Right subtree. */ - struct demangle_component *right; - } s_binary; - - struct - { - /* subtree, same place as d_left. */ - struct demangle_component *sub; - /* integer. */ - int num; - } s_unary_num; - - } u; -}; - -/* People building mangled trees are expected to allocate instances of - struct demangle_component themselves. They can then call one of - the following functions to fill them in. */ - -/* Fill in most component types with a left subtree and a right - subtree. Returns non-zero on success, zero on failure, such as an - unrecognized or inappropriate component type. */ - -extern int -cplus_demangle_fill_component (struct demangle_component *fill, - enum demangle_component_type, - struct demangle_component *left, - struct demangle_component *right); - -/* Fill in a DEMANGLE_COMPONENT_NAME. Returns non-zero on success, - zero for bad arguments. */ - -extern int -cplus_demangle_fill_name (struct demangle_component *fill, - const char *, int); - -/* Fill in a DEMANGLE_COMPONENT_BUILTIN_TYPE, using the name of the - builtin type (e.g., "int", etc.). Returns non-zero on success, - zero if the type is not recognized. */ - -extern int -cplus_demangle_fill_builtin_type (struct demangle_component *fill, - const char *type_name); - -/* Fill in a DEMANGLE_COMPONENT_OPERATOR, using the name of the - operator and the number of arguments which it takes (the latter is - used to disambiguate operators which can be both binary and unary, - such as '-'). Returns non-zero on success, zero if the operator is - not recognized. */ - -extern int -cplus_demangle_fill_operator (struct demangle_component *fill, - const char *opname, int args); - -/* Fill in a DEMANGLE_COMPONENT_EXTENDED_OPERATOR, providing the - number of arguments and the name. Returns non-zero on success, - zero for bad arguments. */ - -extern int -cplus_demangle_fill_extended_operator (struct demangle_component *fill, - int numargs, - struct demangle_component *nm); - -/* Fill in a DEMANGLE_COMPONENT_CTOR. Returns non-zero on success, - zero for bad arguments. */ - -extern int -cplus_demangle_fill_ctor (struct demangle_component *fill, - enum gnu_v3_ctor_kinds kind, - struct demangle_component *name); - -/* Fill in a DEMANGLE_COMPONENT_DTOR. Returns non-zero on success, - zero for bad arguments. */ - -extern int -cplus_demangle_fill_dtor (struct demangle_component *fill, - enum gnu_v3_dtor_kinds kind, - struct demangle_component *name); - -/* This function translates a mangled name into a struct - demangle_component tree. The first argument is the mangled name. - The second argument is DMGL_* options. This returns a pointer to a - tree on success, or NULL on failure. On success, the third - argument is set to a block of memory allocated by malloc. This - block should be passed to free when the tree is no longer - needed. */ - -extern struct demangle_component * -cplus_demangle_v3_components (const char *mangled, int options, void **mem); - -/* This function takes a struct demangle_component tree and returns - the corresponding demangled string. The first argument is DMGL_* - options. The second is the tree to demangle. The third is a guess - at the length of the demangled string, used to initially allocate - the return buffer. The fourth is a pointer to a size_t. On - success, this function returns a buffer allocated by malloc(), and - sets the size_t pointed to by the fourth argument to the size of - the allocated buffer (not the length of the returned string). On - failure, this function returns NULL, and sets the size_t pointed to - by the fourth argument to 0 for an invalid tree, or to 1 for a - memory allocation error. */ - -extern char * -cplus_demangle_print (int options, - const struct demangle_component *tree, - int estimated_length, - size_t *p_allocated_size); - -/* This function takes a struct demangle_component tree and passes back - a demangled string in one or more calls to a callback function. - The first argument is DMGL_* options. The second is the tree to - demangle. The third is a pointer to a callback function; on each call - this receives an element of the demangled string, its length, and an - opaque value. The fourth is the opaque value passed to the callback. - The callback is called once or more to return the full demangled - string. The demangled element string is always nul-terminated, though - its length is also provided for convenience. In contrast to - cplus_demangle_print(), this function does not allocate heap memory - to grow output strings (except perhaps where alloca() is implemented - by malloc()), and so is normally safe for use where the heap has been - corrupted. On success, this function returns 1; on failure, 0. */ - -extern int -cplus_demangle_print_callback (int options, - const struct demangle_component *tree, - demangle_callbackref callback, void *opaque); - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - -#endif /* DEMANGLE_H */ diff --git a/arduino/hardware/tools/avr/include/libiberty/dyn-string.h b/arduino/hardware/tools/avr/include/libiberty/dyn-string.h deleted file mode 100644 index 7c3684b..0000000 --- a/arduino/hardware/tools/avr/include/libiberty/dyn-string.h +++ /dev/null @@ -1,72 +0,0 @@ -/* An abstract string datatype. - Copyright (C) 1998-2015 Free Software Foundation, Inc. - Contributed by Mark Mitchell (mark@markmitchell.com). - -This file is part of GCC. - -GCC is free software; you can redistribute it and/or modify -it under the terms of the GNU General Public License as published by -the Free Software Foundation; either version 2, or (at your option) -any later version. - -GCC is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU General Public License for more details. - -You should have received a copy of the GNU General Public License -along with GCC; see the file COPYING. If not, write to -the Free Software Foundation, 51 Franklin Street - Fifth Floor, -Boston, MA 02110-1301, USA. */ - -#ifndef DYN_STRING_H -#define DYN_STRING_H - -#ifdef __cplusplus -extern "C" { -#endif - -typedef struct dyn_string -{ - int allocated; /* The amount of space allocated for the string. */ - int length; /* The actual length of the string. */ - char *s; /* The string itself, NUL-terminated. */ -}* dyn_string_t; - -/* The length STR, in bytes, not including the terminating NUL. */ -#define dyn_string_length(STR) \ - ((STR)->length) - -/* The NTBS in which the contents of STR are stored. */ -#define dyn_string_buf(STR) \ - ((STR)->s) - -/* Compare DS1 to DS2 with strcmp. */ -#define dyn_string_compare(DS1, DS2) \ - (strcmp ((DS1)->s, (DS2)->s)) - - -extern int dyn_string_init (struct dyn_string *, int); -extern dyn_string_t dyn_string_new (int); -extern void dyn_string_delete (dyn_string_t); -extern char *dyn_string_release (dyn_string_t); -extern dyn_string_t dyn_string_resize (dyn_string_t, int); -extern void dyn_string_clear (dyn_string_t); -extern int dyn_string_copy (dyn_string_t, dyn_string_t); -extern int dyn_string_copy_cstr (dyn_string_t, const char *); -extern int dyn_string_prepend (dyn_string_t, dyn_string_t); -extern int dyn_string_prepend_cstr (dyn_string_t, const char *); -extern int dyn_string_insert (dyn_string_t, int, dyn_string_t); -extern int dyn_string_insert_cstr (dyn_string_t, int, const char *); -extern int dyn_string_insert_char (dyn_string_t, int, int); -extern int dyn_string_append (dyn_string_t, dyn_string_t); -extern int dyn_string_append_cstr (dyn_string_t, const char *); -extern int dyn_string_append_char (dyn_string_t, int); -extern int dyn_string_substring (dyn_string_t, dyn_string_t, int, int); -extern int dyn_string_eq (dyn_string_t, dyn_string_t); - -#ifdef __cplusplus -} -#endif - -#endif /* !defined (DYN_STRING_H) */ diff --git a/arduino/hardware/tools/avr/include/libiberty/fibheap.h b/arduino/hardware/tools/avr/include/libiberty/fibheap.h deleted file mode 100644 index 85b10c5..0000000 --- a/arduino/hardware/tools/avr/include/libiberty/fibheap.h +++ /dev/null @@ -1,94 +0,0 @@ -/* A Fibonacci heap datatype. - Copyright (C) 1998-2015 Free Software Foundation, Inc. - Contributed by Daniel Berlin (dan@cgsoftware.com). - -This file is part of GCC. - -GCC is free software; you can redistribute it and/or modify it -under the terms of the GNU General Public License as published by -the Free Software Foundation; either version 2, or (at your option) -any later version. - -GCC is distributed in the hope that it will be useful, but -WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -General Public License for more details. - -You should have received a copy of the GNU General Public License -along with GCC; see the file COPYING. If not, write to -the Free Software Foundation, 51 Franklin Street - Fifth Floor, -Boston, MA 02110-1301, USA. */ - -/* Fibonacci heaps are somewhat complex, but, there's an article in - DDJ that explains them pretty well: - - http://www.ddj.com/articles/1997/9701/9701o/9701o.htm?topic=algoritms - - Introduction to algorithms by Corman and Rivest also goes over them. - - The original paper that introduced them is "Fibonacci heaps and their - uses in improved network optimization algorithms" by Tarjan and - Fredman (JACM 34(3), July 1987). - - Amortized and real worst case time for operations: - - ExtractMin: O(lg n) amortized. O(n) worst case. - DecreaseKey: O(1) amortized. O(lg n) worst case. - Insert: O(2) amortized. O(1) actual. - Union: O(1) amortized. O(1) actual. */ - -#ifndef _FIBHEAP_H_ -#define _FIBHEAP_H_ - -#include "ansidecl.h" - -#ifdef __cplusplus -extern "C" { -#endif - -typedef long fibheapkey_t; - -typedef struct fibheap -{ - size_t nodes; - struct fibnode *min; - struct fibnode *root; -} *fibheap_t; - -typedef struct fibnode -{ - struct fibnode *parent; - struct fibnode *child; - struct fibnode *left; - struct fibnode *right; - fibheapkey_t key; - void *data; -#if defined (__GNUC__) && (!defined (SIZEOF_INT) || SIZEOF_INT < 4) - __extension__ unsigned long int degree : 31; - __extension__ unsigned long int mark : 1; -#else - unsigned int degree : 31; - unsigned int mark : 1; -#endif -} *fibnode_t; - -extern fibheap_t fibheap_new (void); -extern fibnode_t fibheap_insert (fibheap_t, fibheapkey_t, void *); -extern int fibheap_empty (fibheap_t); -extern fibheapkey_t fibheap_min_key (fibheap_t); -extern fibheapkey_t fibheap_replace_key (fibheap_t, fibnode_t, - fibheapkey_t); -extern void *fibheap_replace_key_data (fibheap_t, fibnode_t, - fibheapkey_t, void *); -extern void *fibheap_extract_min (fibheap_t); -extern void *fibheap_min (fibheap_t); -extern void *fibheap_replace_data (fibheap_t, fibnode_t, void *); -extern void *fibheap_delete_node (fibheap_t, fibnode_t); -extern void fibheap_delete (fibheap_t); -extern fibheap_t fibheap_union (fibheap_t, fibheap_t); - -#ifdef __cplusplus -} -#endif - -#endif /* _FIBHEAP_H_ */ diff --git a/arduino/hardware/tools/avr/include/libiberty/floatformat.h b/arduino/hardware/tools/avr/include/libiberty/floatformat.h deleted file mode 100644 index af4d09c..0000000 --- a/arduino/hardware/tools/avr/include/libiberty/floatformat.h +++ /dev/null @@ -1,159 +0,0 @@ -/* IEEE floating point support declarations, for GDB, the GNU Debugger. - Copyright (C) 1991-2015 Free Software Foundation, Inc. - -This file is part of GDB. - -This program is free software; you can redistribute it and/or modify -it under the terms of the GNU General Public License as published by -the Free Software Foundation; either version 2 of the License, or -(at your option) any later version. - -This program is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU General Public License for more details. - -You should have received a copy of the GNU General Public License -along with this program; if not, write to the Free Software -Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ - -#if !defined (FLOATFORMAT_H) -#define FLOATFORMAT_H 1 - -#include "ansidecl.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/* A floatformat consists of a sign bit, an exponent and a mantissa. Once the - bytes are concatenated according to the byteorder flag, then each of those - fields is contiguous. We number the bits with 0 being the most significant - (i.e. BITS_BIG_ENDIAN type numbering), and specify which bits each field - contains with the *_start and *_len fields. */ - -/* What is the order of the bytes? */ - -enum floatformat_byteorders { - /* Standard little endian byte order. - EX: 1.2345678e10 => 00 00 80 c5 e0 fe 06 42 */ - floatformat_little, - - /* Standard big endian byte order. - EX: 1.2345678e10 => 42 06 fe e0 c5 80 00 00 */ - floatformat_big, - - /* Little endian byte order but big endian word order. - EX: 1.2345678e10 => e0 fe 06 42 00 00 80 c5 */ - floatformat_littlebyte_bigword, - - /* VAX byte order. Little endian byte order with 16-bit words. The - following example is an illustration of the byte order only; VAX - doesn't have a fully IEEE compliant floating-point format. - EX: 1.2345678e10 => 80 c5 00 00 06 42 e0 fe */ - floatformat_vax -}; - -enum floatformat_intbit { floatformat_intbit_yes, floatformat_intbit_no }; - -struct floatformat -{ - enum floatformat_byteorders byteorder; - unsigned int totalsize; /* Total size of number in bits */ - - /* Sign bit is always one bit long. 1 means negative, 0 means positive. */ - unsigned int sign_start; - - unsigned int exp_start; - unsigned int exp_len; - /* Bias added to a "true" exponent to form the biased exponent. It - is intentionally signed as, otherwize, -exp_bias can turn into a - very large number (e.g., given the exp_bias of 0x3fff and a 64 - bit long, the equation (long)(1 - exp_bias) evaluates to - 4294950914) instead of -16382). */ - int exp_bias; - /* Exponent value which indicates NaN. This is the actual value stored in - the float, not adjusted by the exp_bias. This usually consists of all - one bits. */ - unsigned int exp_nan; - - unsigned int man_start; - unsigned int man_len; - - /* Is the integer bit explicit or implicit? */ - enum floatformat_intbit intbit; - - /* Internal name for debugging. */ - const char *name; - - /* Validator method. */ - int (*is_valid) (const struct floatformat *fmt, const void *from); - - /* Is the format actually the sum of two smaller floating point - formats (IBM long double, as described in - gcc/config/rs6000/darwin-ldouble-format)? If so, this is the - smaller format in question, and the fields sign_start through - intbit describe the first half. If not, this is NULL. */ - const struct floatformat *split_half; -}; - -/* floatformats for IEEE single and double, big and little endian. */ - -extern const struct floatformat floatformat_ieee_half_big; -extern const struct floatformat floatformat_ieee_half_little; -extern const struct floatformat floatformat_ieee_single_big; -extern const struct floatformat floatformat_ieee_single_little; -extern const struct floatformat floatformat_ieee_double_big; -extern const struct floatformat floatformat_ieee_double_little; - -/* floatformat for ARM IEEE double, little endian bytes and big endian words */ - -extern const struct floatformat floatformat_ieee_double_littlebyte_bigword; - -/* floatformats for VAX. */ - -extern const struct floatformat floatformat_vax_f; -extern const struct floatformat floatformat_vax_d; -extern const struct floatformat floatformat_vax_g; - -/* floatformats for various extendeds. */ - -extern const struct floatformat floatformat_i387_ext; -extern const struct floatformat floatformat_m68881_ext; -extern const struct floatformat floatformat_i960_ext; -extern const struct floatformat floatformat_m88110_ext; -extern const struct floatformat floatformat_m88110_harris_ext; -extern const struct floatformat floatformat_arm_ext_big; -extern const struct floatformat floatformat_arm_ext_littlebyte_bigword; -/* IA-64 Floating Point register spilt into memory. */ -extern const struct floatformat floatformat_ia64_spill_big; -extern const struct floatformat floatformat_ia64_spill_little; -extern const struct floatformat floatformat_ia64_quad_big; -extern const struct floatformat floatformat_ia64_quad_little; -/* IBM long double (double+double). */ -extern const struct floatformat floatformat_ibm_long_double_big; -extern const struct floatformat floatformat_ibm_long_double_little; - -/* Convert from FMT to a double. - FROM is the address of the extended float. - Store the double in *TO. */ - -extern void -floatformat_to_double (const struct floatformat *, const void *, double *); - -/* The converse: convert the double *FROM to FMT - and store where TO points. */ - -extern void -floatformat_from_double (const struct floatformat *, const double *, void *); - -/* Return non-zero iff the data at FROM is a valid number in format FMT. */ - -extern int -floatformat_is_valid (const struct floatformat *fmt, const void *from); - -#ifdef __cplusplus -} -#endif - -#endif /* defined (FLOATFORMAT_H) */ diff --git a/arduino/hardware/tools/avr/include/libiberty/hashtab.h b/arduino/hardware/tools/avr/include/libiberty/hashtab.h deleted file mode 100644 index b1b5877..0000000 --- a/arduino/hardware/tools/avr/include/libiberty/hashtab.h +++ /dev/null @@ -1,204 +0,0 @@ -/* An expandable hash tables datatype. - Copyright (C) 1999-2015 Free Software Foundation, Inc. - Contributed by Vladimir Makarov (vmakarov@cygnus.com). - -This program is free software; you can redistribute it and/or modify -it under the terms of the GNU General Public License as published by -the Free Software Foundation; either version 2 of the License, or -(at your option) any later version. - -This program is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU General Public License for more details. - -You should have received a copy of the GNU General Public License -along with this program; if not, write to the Free Software -Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ - -/* This package implements basic hash table functionality. It is possible - to search for an entry, create an entry and destroy an entry. - - Elements in the table are generic pointers. - - The size of the table is not fixed; if the occupancy of the table - grows too high the hash table will be expanded. - - The abstract data implementation is based on generalized Algorithm D - from Knuth's book "The art of computer programming". Hash table is - expanded by creation of new hash table and transferring elements from - the old table to the new table. */ - -#ifndef __HASHTAB_H__ -#define __HASHTAB_H__ - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -#include "ansidecl.h" - -/* The type for a hash code. */ -typedef unsigned int hashval_t; - -/* Callback function pointer types. */ - -/* Calculate hash of a table entry. */ -typedef hashval_t (*htab_hash) (const void *); - -/* Compare a table entry with a possible entry. The entry already in - the table always comes first, so the second element can be of a - different type (but in this case htab_find and htab_find_slot - cannot be used; instead the variants that accept a hash value - must be used). */ -typedef int (*htab_eq) (const void *, const void *); - -/* Cleanup function called whenever a live element is removed from - the hash table. */ -typedef void (*htab_del) (void *); - -/* Function called by htab_traverse for each live element. The first - arg is the slot of the element (which can be passed to htab_clear_slot - if desired), the second arg is the auxiliary pointer handed to - htab_traverse. Return 1 to continue scan, 0 to stop. */ -typedef int (*htab_trav) (void **, void *); - -/* Memory-allocation function, with the same functionality as calloc(). - Iff it returns NULL, the hash table implementation will pass an error - code back to the user, so if your code doesn't handle errors, - best if you use xcalloc instead. */ -typedef void *(*htab_alloc) (size_t, size_t); - -/* We also need a free() routine. */ -typedef void (*htab_free) (void *); - -/* Memory allocation and deallocation; variants which take an extra - argument. */ -typedef void *(*htab_alloc_with_arg) (void *, size_t, size_t); -typedef void (*htab_free_with_arg) (void *, void *); - -/* This macro defines reserved value for empty table entry. */ - -#define HTAB_EMPTY_ENTRY ((PTR) 0) - -/* This macro defines reserved value for table entry which contained - a deleted element. */ - -#define HTAB_DELETED_ENTRY ((PTR) 1) - -/* Hash tables are of the following type. The structure - (implementation) of this type is not needed for using the hash - tables. All work with hash table should be executed only through - functions mentioned below. The size of this structure is subject to - change. */ - -struct htab { - /* Pointer to hash function. */ - htab_hash hash_f; - - /* Pointer to comparison function. */ - htab_eq eq_f; - - /* Pointer to cleanup function. */ - htab_del del_f; - - /* Table itself. */ - void **entries; - - /* Current size (in entries) of the hash table. */ - size_t size; - - /* Current number of elements including also deleted elements. */ - size_t n_elements; - - /* Current number of deleted elements in the table. */ - size_t n_deleted; - - /* The following member is used for debugging. Its value is number - of all calls of `htab_find_slot' for the hash table. */ - unsigned int searches; - - /* The following member is used for debugging. Its value is number - of collisions fixed for time of work with the hash table. */ - unsigned int collisions; - - /* Pointers to allocate/free functions. */ - htab_alloc alloc_f; - htab_free free_f; - - /* Alternate allocate/free functions, which take an extra argument. */ - void *alloc_arg; - htab_alloc_with_arg alloc_with_arg_f; - htab_free_with_arg free_with_arg_f; - - /* Current size (in entries) of the hash table, as an index into the - table of primes. */ - unsigned int size_prime_index; -}; - -typedef struct htab *htab_t; - -/* An enum saying whether we insert into the hash table or not. */ -enum insert_option {NO_INSERT, INSERT}; - -/* The prototypes of the package functions. */ - -extern htab_t htab_create_alloc (size_t, htab_hash, - htab_eq, htab_del, - htab_alloc, htab_free); - -extern htab_t htab_create_alloc_ex (size_t, htab_hash, - htab_eq, htab_del, - void *, htab_alloc_with_arg, - htab_free_with_arg); - -extern htab_t htab_create_typed_alloc (size_t, htab_hash, htab_eq, htab_del, - htab_alloc, htab_alloc, htab_free); - -/* Backward-compatibility functions. */ -extern htab_t htab_create (size_t, htab_hash, htab_eq, htab_del); -extern htab_t htab_try_create (size_t, htab_hash, htab_eq, htab_del); - -extern void htab_set_functions_ex (htab_t, htab_hash, - htab_eq, htab_del, - void *, htab_alloc_with_arg, - htab_free_with_arg); - -extern void htab_delete (htab_t); -extern void htab_empty (htab_t); - -extern void * htab_find (htab_t, const void *); -extern void ** htab_find_slot (htab_t, const void *, enum insert_option); -extern void * htab_find_with_hash (htab_t, const void *, hashval_t); -extern void ** htab_find_slot_with_hash (htab_t, const void *, - hashval_t, enum insert_option); -extern void htab_clear_slot (htab_t, void **); -extern void htab_remove_elt (htab_t, void *); -extern void htab_remove_elt_with_hash (htab_t, void *, hashval_t); - -extern void htab_traverse (htab_t, htab_trav, void *); -extern void htab_traverse_noresize (htab_t, htab_trav, void *); - -extern size_t htab_size (htab_t); -extern size_t htab_elements (htab_t); -extern double htab_collisions (htab_t); - -/* A hash function for pointers. */ -extern htab_hash htab_hash_pointer; - -/* An equality function for pointers. */ -extern htab_eq htab_eq_pointer; - -/* A hash function for null-terminated strings. */ -extern hashval_t htab_hash_string (const void *); - -/* An iterative hash function for arbitrary data. */ -extern hashval_t iterative_hash (const void *, size_t, hashval_t); -/* Shorthand for hashing something with an intrinsic size. */ -#define iterative_hash_object(OB,INIT) iterative_hash (&OB, sizeof (OB), INIT) - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - -#endif /* __HASHTAB_H */ diff --git a/arduino/hardware/tools/avr/include/libiberty/libiberty.h b/arduino/hardware/tools/avr/include/libiberty/libiberty.h deleted file mode 100644 index 8e096a0..0000000 --- a/arduino/hardware/tools/avr/include/libiberty/libiberty.h +++ /dev/null @@ -1,739 +0,0 @@ -/* Function declarations for libiberty. - - Copyright (C) 1997-2015 Free Software Foundation, Inc. - - Note - certain prototypes declared in this header file are for - functions whoes implementation copyright does not belong to the - FSF. Those prototypes are present in this file for reference - purposes only and their presence in this file should not construed - as an indication of ownership by the FSF of the implementation of - those functions in any way or form whatsoever. - - This program is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2, or (at your option) - any later version. - - This program is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program; if not, write to the Free Software - Foundation, Inc., 51 Franklin Street - Fifth Floor, - Boston, MA 02110-1301, USA. - - Written by Cygnus Support, 1994. - - The libiberty library provides a number of functions which are - missing on some operating systems. We do not declare those here, - to avoid conflicts with the system header files on operating - systems that do support those functions. In this file we only - declare those functions which are specific to libiberty. */ - -#ifndef LIBIBERTY_H -#define LIBIBERTY_H - -#ifdef __cplusplus -extern "C" { -#endif - -#include "ansidecl.h" - -/* Get a definition for size_t. */ -#include -/* Get a definition for va_list. */ -#include - -#include - -/* If the OS supports it, ensure that the supplied stream is setup to - avoid any multi-threaded locking. Otherwise leave the FILE pointer - unchanged. If the stream is NULL do nothing. */ - -extern void unlock_stream (FILE *); - -/* If the OS supports it, ensure that the standard I/O streams, stdin, - stdout and stderr are setup to avoid any multi-threaded locking. - Otherwise do nothing. */ - -extern void unlock_std_streams (void); - -/* Open and return a FILE pointer. If the OS supports it, ensure that - the stream is setup to avoid any multi-threaded locking. Otherwise - return the FILE pointer unchanged. */ - -extern FILE *fopen_unlocked (const char *, const char *); -extern FILE *fdopen_unlocked (int, const char *); -extern FILE *freopen_unlocked (const char *, const char *, FILE *); - -/* Build an argument vector from a string. Allocates memory using - malloc. Use freeargv to free the vector. */ - -extern char **buildargv (const char *) ATTRIBUTE_MALLOC; - -/* Free a vector returned by buildargv. */ - -extern void freeargv (char **); - -/* Duplicate an argument vector. Allocates memory using malloc. Use - freeargv to free the vector. */ - -extern char **dupargv (char **) ATTRIBUTE_MALLOC; - -/* Expand "@file" arguments in argv. */ - -extern void expandargv (int *, char ***); - -/* Write argv to an @-file, inserting necessary quoting. */ - -extern int writeargv (char **, FILE *); - -/* Return the number of elements in argv. */ - -extern int countargv (char**); - -/* Return the last component of a path name. Note that we can't use a - prototype here because the parameter is declared inconsistently - across different systems, sometimes as "char *" and sometimes as - "const char *" */ - -/* HAVE_DECL_* is a three-state macro: undefined, 0 or 1. If it is - undefined, we haven't run the autoconf check so provide the - declaration without arguments. If it is 0, we checked and failed - to find the declaration so provide a fully prototyped one. If it - is 1, we found it so don't provide any declaration at all. */ -#if !HAVE_DECL_BASENAME -#if defined (__GNU_LIBRARY__ ) || defined (__linux__) \ - || defined (__FreeBSD__) || defined (__OpenBSD__) || defined (__NetBSD__) \ - || defined (__CYGWIN__) || defined (__CYGWIN32__) || defined (__MINGW32__) \ - || defined (__DragonFly__) || defined (HAVE_DECL_BASENAME) -extern char *basename (const char *) ATTRIBUTE_RETURNS_NONNULL ATTRIBUTE_NONNULL(1); -#else -/* Do not allow basename to be used if there is no prototype seen. We - either need to use the above prototype or have one from - autoconf which would result in HAVE_DECL_BASENAME being set. */ -#define basename basename_cannot_be_used_without_a_prototype -#endif -#endif - -/* A well-defined basename () that is always compiled in. */ - -extern const char *lbasename (const char *) ATTRIBUTE_RETURNS_NONNULL ATTRIBUTE_NONNULL(1); - -/* Same, but assumes DOS semantics (drive name, backslash is also a - dir separator) regardless of host. */ - -extern const char *dos_lbasename (const char *) ATTRIBUTE_RETURNS_NONNULL ATTRIBUTE_NONNULL(1); - -/* Same, but assumes Unix semantics (absolute paths always start with - a slash, only forward slash is accepted as dir separator) - regardless of host. */ - -extern const char *unix_lbasename (const char *) ATTRIBUTE_RETURNS_NONNULL ATTRIBUTE_NONNULL(1); - -/* A well-defined realpath () that is always compiled in. */ - -extern char *lrealpath (const char *); - -/* Concatenate an arbitrary number of strings. You must pass NULL as - the last argument of this function, to terminate the list of - strings. Allocates memory using xmalloc. */ - -extern char *concat (const char *, ...) ATTRIBUTE_MALLOC ATTRIBUTE_RETURNS_NONNULL ATTRIBUTE_SENTINEL; - -/* Concatenate an arbitrary number of strings. You must pass NULL as - the last argument of this function, to terminate the list of - strings. Allocates memory using xmalloc. The first argument is - not one of the strings to be concatenated, but if not NULL is a - pointer to be freed after the new string is created, similar to the - way xrealloc works. */ - -extern char *reconcat (char *, const char *, ...) ATTRIBUTE_MALLOC ATTRIBUTE_RETURNS_NONNULL ATTRIBUTE_SENTINEL; - -/* Determine the length of concatenating an arbitrary number of - strings. You must pass NULL as the last argument of this function, - to terminate the list of strings. */ - -extern unsigned long concat_length (const char *, ...) ATTRIBUTE_SENTINEL; - -/* Concatenate an arbitrary number of strings into a SUPPLIED area of - memory. You must pass NULL as the last argument of this function, - to terminate the list of strings. The supplied memory is assumed - to be large enough. */ - -extern char *concat_copy (char *, const char *, ...) ATTRIBUTE_RETURNS_NONNULL ATTRIBUTE_NONNULL(1) ATTRIBUTE_SENTINEL; - -/* Concatenate an arbitrary number of strings into a GLOBAL area of - memory. You must pass NULL as the last argument of this function, - to terminate the list of strings. The supplied memory is assumed - to be large enough. */ - -extern char *concat_copy2 (const char *, ...) ATTRIBUTE_RETURNS_NONNULL ATTRIBUTE_SENTINEL; - -/* This is the global area used by concat_copy2. */ - -extern char *libiberty_concat_ptr; - -/* Concatenate an arbitrary number of strings. You must pass NULL as - the last argument of this function, to terminate the list of - strings. Allocates memory using alloca. The arguments are - evaluated twice! */ -#define ACONCAT(ACONCAT_PARAMS) \ - (libiberty_concat_ptr = (char *) alloca (concat_length ACONCAT_PARAMS + 1), \ - concat_copy2 ACONCAT_PARAMS) - -/* Check whether two file descriptors refer to the same file. */ - -extern int fdmatch (int fd1, int fd2); - -/* Return the position of the first bit set in the argument. */ -/* Prototypes vary from system to system, so we only provide a - prototype on systems where we know that we need it. */ -#if defined (HAVE_DECL_FFS) && !HAVE_DECL_FFS -extern int ffs(int); -#endif - -/* Get the working directory. The result is cached, so don't call - chdir() between calls to getpwd(). */ - -extern char * getpwd (void); - -/* Get the current time. */ -/* Prototypes vary from system to system, so we only provide a - prototype on systems where we know that we need it. */ -#ifdef __MINGW32__ -/* Forward declaration to avoid #include . */ -struct timeval; -extern int gettimeofday (struct timeval *, void *); -#endif - -/* Get the amount of time the process has run, in microseconds. */ - -extern long get_run_time (void); - -/* Generate a relocated path to some installation directory. Allocates - return value using malloc. */ - -extern char *make_relative_prefix (const char *, const char *, - const char *) ATTRIBUTE_MALLOC; - -/* Generate a relocated path to some installation directory without - attempting to follow any soft links. Allocates - return value using malloc. */ - -extern char *make_relative_prefix_ignore_links (const char *, const char *, - const char *) ATTRIBUTE_MALLOC; - -/* Returns a pointer to a directory path suitable for creating temporary - files in. */ - -extern const char *choose_tmpdir (void) ATTRIBUTE_RETURNS_NONNULL; - -/* Choose a temporary directory to use for scratch files. */ - -extern char *choose_temp_base (void) ATTRIBUTE_MALLOC ATTRIBUTE_RETURNS_NONNULL; - -/* Return a temporary file name or NULL if unable to create one. */ - -extern char *make_temp_file (const char *) ATTRIBUTE_MALLOC; - -/* Remove a link to a file unless it is special. */ - -extern int unlink_if_ordinary (const char *); - -/* Allocate memory filled with spaces. Allocates using malloc. */ - -extern const char *spaces (int count); - -/* Return the maximum error number for which strerror will return a - string. */ - -extern int errno_max (void); - -/* Return the name of an errno value (e.g., strerrno (EINVAL) returns - "EINVAL"). */ - -extern const char *strerrno (int); - -/* Given the name of an errno value, return the value. */ - -extern int strtoerrno (const char *); - -/* ANSI's strerror(), but more robust. */ - -extern char *xstrerror (int) ATTRIBUTE_RETURNS_NONNULL; - -/* Return the maximum signal number for which strsignal will return a - string. */ - -extern int signo_max (void); - -/* Return a signal message string for a signal number - (e.g., strsignal (SIGHUP) returns something like "Hangup"). */ -/* This is commented out as it can conflict with one in system headers. - We still document its existence though. */ - -/*extern const char *strsignal (int);*/ - -/* Return the name of a signal number (e.g., strsigno (SIGHUP) returns - "SIGHUP"). */ - -extern const char *strsigno (int); - -/* Given the name of a signal, return its number. */ - -extern int strtosigno (const char *); - -/* Register a function to be run by xexit. Returns 0 on success. */ - -extern int xatexit (void (*fn) (void)); - -/* Exit, calling all the functions registered with xatexit. */ - -extern void xexit (int status) ATTRIBUTE_NORETURN; - -/* Set the program name used by xmalloc. */ - -extern void xmalloc_set_program_name (const char *); - -/* Report an allocation failure. */ -extern void xmalloc_failed (size_t) ATTRIBUTE_NORETURN; - -/* Allocate memory without fail. If malloc fails, this will print a - message to stderr (using the name set by xmalloc_set_program_name, - if any) and then call xexit. */ - -extern void *xmalloc (size_t) ATTRIBUTE_MALLOC ATTRIBUTE_RETURNS_NONNULL; - -/* Reallocate memory without fail. This works like xmalloc. Note, - realloc type functions are not suitable for attribute malloc since - they may return the same address across multiple calls. */ - -extern void *xrealloc (void *, size_t) ATTRIBUTE_RETURNS_NONNULL; - -/* Allocate memory without fail and set it to zero. This works like - xmalloc. */ - -extern void *xcalloc (size_t, size_t) ATTRIBUTE_MALLOC ATTRIBUTE_RETURNS_NONNULL; - -/* Copy a string into a memory buffer without fail. */ - -extern char *xstrdup (const char *) ATTRIBUTE_MALLOC ATTRIBUTE_RETURNS_NONNULL; - -/* Copy at most N characters from string into a buffer without fail. */ - -extern char *xstrndup (const char *, size_t) ATTRIBUTE_MALLOC ATTRIBUTE_RETURNS_NONNULL; - -/* Copy an existing memory buffer to a new memory buffer without fail. */ - -extern void *xmemdup (const void *, size_t, size_t) ATTRIBUTE_MALLOC ATTRIBUTE_RETURNS_NONNULL; - -/* Physical memory routines. Return values are in BYTES. */ -extern double physmem_total (void); -extern double physmem_available (void); - -/* Compute the 32-bit CRC of a block of memory. */ -extern unsigned int xcrc32 (const unsigned char *, int, unsigned int); - -/* These macros provide a K&R/C89/C++-friendly way of allocating structures - with nice encapsulation. The XDELETE*() macros are technically - superfluous, but provided here for symmetry. Using them consistently - makes it easier to update client code to use different allocators such - as new/delete and new[]/delete[]. */ - -/* Scalar allocators. */ - -#define XALLOCA(T) ((T *) alloca (sizeof (T))) -#define XNEW(T) ((T *) xmalloc (sizeof (T))) -#define XCNEW(T) ((T *) xcalloc (1, sizeof (T))) -#define XDUP(T, P) ((T *) xmemdup ((P), sizeof (T), sizeof (T))) -#define XDELETE(P) free ((void*) (P)) - -/* Array allocators. */ - -#define XALLOCAVEC(T, N) ((T *) alloca (sizeof (T) * (N))) -#define XNEWVEC(T, N) ((T *) xmalloc (sizeof (T) * (N))) -#define XCNEWVEC(T, N) ((T *) xcalloc ((N), sizeof (T))) -#define XDUPVEC(T, P, N) ((T *) xmemdup ((P), sizeof (T) * (N), sizeof (T) * (N))) -#define XRESIZEVEC(T, P, N) ((T *) xrealloc ((void *) (P), sizeof (T) * (N))) -#define XDELETEVEC(P) free ((void*) (P)) - -/* Allocators for variable-sized structures and raw buffers. */ - -#define XALLOCAVAR(T, S) ((T *) alloca ((S))) -#define XNEWVAR(T, S) ((T *) xmalloc ((S))) -#define XCNEWVAR(T, S) ((T *) xcalloc (1, (S))) -#define XDUPVAR(T, P, S1, S2) ((T *) xmemdup ((P), (S1), (S2))) -#define XRESIZEVAR(T, P, S) ((T *) xrealloc ((P), (S))) - -/* Type-safe obstack allocator. */ - -#define XOBNEW(O, T) ((T *) obstack_alloc ((O), sizeof (T))) -#define XOBNEWVEC(O, T, N) ((T *) obstack_alloc ((O), sizeof (T) * (N))) -#define XOBNEWVAR(O, T, S) ((T *) obstack_alloc ((O), (S))) -#define XOBFINISH(O, T) ((T) obstack_finish ((O))) - -/* hex character manipulation routines */ - -#define _hex_array_size 256 -#define _hex_bad 99 -extern const unsigned char _hex_value[_hex_array_size]; -extern void hex_init (void); -#define hex_p(c) (hex_value (c) != _hex_bad) -/* If you change this, note well: Some code relies on side effects in - the argument being performed exactly once. */ -#define hex_value(c) ((unsigned int) _hex_value[(unsigned char) (c)]) - -/* Flags for pex_init. These are bits to be or'ed together. */ - -/* Record subprocess times, if possible. */ -#define PEX_RECORD_TIMES 0x1 - -/* Use pipes for communication between processes, if possible. */ -#define PEX_USE_PIPES 0x2 - -/* Save files used for communication between processes. */ -#define PEX_SAVE_TEMPS 0x4 - -/* Prepare to execute one or more programs, with standard output of - each program fed to standard input of the next. - FLAGS As above. - PNAME The name of the program to report in error messages. - TEMPBASE A base name to use for temporary files; may be NULL to - use a random name. - Returns NULL on error. */ - -extern struct pex_obj *pex_init (int flags, const char *pname, - const char *tempbase) ATTRIBUTE_RETURNS_NONNULL; - -/* Flags for pex_run. These are bits to be or'ed together. */ - -/* Last program in pipeline. Standard output of program goes to - OUTNAME, or, if OUTNAME is NULL, to standard output of caller. Do - not set this if you want to call pex_read_output. After this is - set, pex_run may no longer be called with the same struct - pex_obj. */ -#define PEX_LAST 0x1 - -/* Search for program in executable search path. */ -#define PEX_SEARCH 0x2 - -/* OUTNAME is a suffix. */ -#define PEX_SUFFIX 0x4 - -/* Send program's standard error to standard output. */ -#define PEX_STDERR_TO_STDOUT 0x8 - -/* Input file should be opened in binary mode. This flag is ignored - on Unix. */ -#define PEX_BINARY_INPUT 0x10 - -/* Output file should be opened in binary mode. This flag is ignored - on Unix. For proper behaviour PEX_BINARY_INPUT and - PEX_BINARY_OUTPUT have to match appropriately--i.e., a call using - PEX_BINARY_OUTPUT should be followed by a call using - PEX_BINARY_INPUT. */ -#define PEX_BINARY_OUTPUT 0x20 - -/* Capture stderr to a pipe. The output can be read by - calling pex_read_err and reading from the returned - FILE object. This flag may be specified only for - the last program in a pipeline. - - This flag is supported only on Unix and Windows. */ -#define PEX_STDERR_TO_PIPE 0x40 - -/* Capture stderr in binary mode. This flag is ignored - on Unix. */ -#define PEX_BINARY_ERROR 0x80 - -/* Append stdout to existing file instead of truncating it. */ -#define PEX_STDOUT_APPEND 0x100 - -/* Thes same as PEX_STDOUT_APPEND, but for STDERR. */ -#define PEX_STDERR_APPEND 0x200 - -/* Execute one program. Returns NULL on success. On error returns an - error string (typically just the name of a system call); the error - string is statically allocated. - - OBJ Returned by pex_init. - - FLAGS As above. - - EXECUTABLE The program to execute. - - ARGV NULL terminated array of arguments to pass to the program. - - OUTNAME Sets the output file name as follows: - - PEX_SUFFIX set (OUTNAME may not be NULL): - TEMPBASE parameter to pex_init not NULL: - Output file name is the concatenation of TEMPBASE - and OUTNAME. - TEMPBASE is NULL: - Output file name is a random file name ending in - OUTNAME. - PEX_SUFFIX not set: - OUTNAME not NULL: - Output file name is OUTNAME. - OUTNAME NULL, TEMPBASE not NULL: - Output file name is randomly chosen using - TEMPBASE. - OUTNAME NULL, TEMPBASE NULL: - Output file name is randomly chosen. - - If PEX_LAST is not set, the output file name is the - name to use for a temporary file holding stdout, if - any (there will not be a file if PEX_USE_PIPES is set - and the system supports pipes). If a file is used, it - will be removed when no longer needed unless - PEX_SAVE_TEMPS is set. - - If PEX_LAST is set, and OUTNAME is not NULL, standard - output is written to the output file name. The file - will not be removed. If PEX_LAST and PEX_SUFFIX are - both set, TEMPBASE may not be NULL. - - ERRNAME If not NULL, this is the name of a file to which - standard error is written. If NULL, standard error of - the program is standard error of the caller. - - ERR On an error return, *ERR is set to an errno value, or - to 0 if there is no relevant errno. -*/ - -extern const char *pex_run (struct pex_obj *obj, int flags, - const char *executable, char * const *argv, - const char *outname, const char *errname, - int *err); - -/* As for pex_run (), but takes an extra parameter to enable the - environment for the child process to be specified. - - ENV The environment for the child process, specified as - an array of character pointers. Each element of the - array should point to a string of the form VAR=VALUE, - with the exception of the last element which must be - a null pointer. -*/ - -extern const char *pex_run_in_environment (struct pex_obj *obj, int flags, - const char *executable, - char * const *argv, - char * const *env, - const char *outname, - const char *errname, int *err); - -/* Return a stream for a temporary file to pass to the first program - in the pipeline as input. The file name is chosen as for pex_run. - pex_run closes the file automatically; don't close it yourself. */ - -extern FILE *pex_input_file (struct pex_obj *obj, int flags, - const char *in_name); - -/* Return a stream for a pipe connected to the standard input of the - first program in the pipeline. You must have passed - `PEX_USE_PIPES' to `pex_init'. Close the returned stream - yourself. */ - -extern FILE *pex_input_pipe (struct pex_obj *obj, int binary); - -/* Read the standard output of the last program to be executed. - pex_run can not be called after this. BINARY should be non-zero if - the file should be opened in binary mode; this is ignored on Unix. - Returns NULL on error. Don't call fclose on the returned FILE; it - will be closed by pex_free. */ - -extern FILE *pex_read_output (struct pex_obj *, int binary); - -/* Read the standard error of the last program to be executed. - pex_run can not be called after this. BINARY should be non-zero if - the file should be opened in binary mode; this is ignored on Unix. - Returns NULL on error. Don't call fclose on the returned FILE; it - will be closed by pex_free. */ - -extern FILE *pex_read_err (struct pex_obj *, int binary); - -/* Return exit status of all programs in VECTOR. COUNT indicates the - size of VECTOR. The status codes in the vector are in the order of - the calls to pex_run. Returns 0 on error, 1 on success. */ - -extern int pex_get_status (struct pex_obj *, int count, int *vector); - -/* Return times of all programs in VECTOR. COUNT indicates the size - of VECTOR. struct pex_time is really just struct timeval, but that - is not portable to all systems. Returns 0 on error, 1 on - success. */ - -struct pex_time -{ - unsigned long user_seconds; - unsigned long user_microseconds; - unsigned long system_seconds; - unsigned long system_microseconds; -}; - -extern int pex_get_times (struct pex_obj *, int count, - struct pex_time *vector); - -/* Clean up a pex_obj. If you have not called pex_get_times or - pex_get_status, this will try to kill the subprocesses. */ - -extern void pex_free (struct pex_obj *); - -/* Just execute one program. Return value is as for pex_run. - FLAGS Combination of PEX_SEARCH and PEX_STDERR_TO_STDOUT. - EXECUTABLE As for pex_run. - ARGV As for pex_run. - PNAME As for pex_init. - OUTNAME As for pex_run when PEX_LAST is set. - ERRNAME As for pex_run. - STATUS Set to exit status on success. - ERR As for pex_run. -*/ - -extern const char *pex_one (int flags, const char *executable, - char * const *argv, const char *pname, - const char *outname, const char *errname, - int *status, int *err); - -/* pexecute and pwait are the old pexecute interface, still here for - backward compatibility. Don't use these for new code. Instead, - use pex_init/pex_run/pex_get_status/pex_free, or pex_one. */ - -/* Definitions used by the pexecute routine. */ - -#define PEXECUTE_FIRST 1 -#define PEXECUTE_LAST 2 -#define PEXECUTE_ONE (PEXECUTE_FIRST + PEXECUTE_LAST) -#define PEXECUTE_SEARCH 4 -#define PEXECUTE_VERBOSE 8 - -/* Execute a program. */ - -extern int pexecute (const char *, char * const *, const char *, - const char *, char **, char **, int); - -/* Wait for pexecute to finish. */ - -extern int pwait (int, int *, int); - -#if defined(HAVE_DECL_ASPRINTF) && !HAVE_DECL_ASPRINTF -/* Like sprintf but provides a pointer to malloc'd storage, which must - be freed by the caller. */ - -extern int asprintf (char **, const char *, ...) ATTRIBUTE_PRINTF_2; -#endif - -/* Like asprintf but allocates memory without fail. This works like - xmalloc. */ - -extern char *xasprintf (const char *, ...) ATTRIBUTE_MALLOC ATTRIBUTE_PRINTF_1; - -#if !HAVE_DECL_VASPRINTF -/* Like vsprintf but provides a pointer to malloc'd storage, which - must be freed by the caller. */ - -extern int vasprintf (char **, const char *, va_list) ATTRIBUTE_PRINTF(2,0); -#endif - -/* Like vasprintf but allocates memory without fail. This works like - xmalloc. */ - -extern char *xvasprintf (const char *, va_list) ATTRIBUTE_MALLOC ATTRIBUTE_PRINTF(1,0); - -#if defined(HAVE_DECL_SNPRINTF) && !HAVE_DECL_SNPRINTF -/* Like sprintf but prints at most N characters. */ -extern int snprintf (char *, size_t, const char *, ...) ATTRIBUTE_PRINTF_3; -#endif - -#if defined(HAVE_DECL_VSNPRINTF) && !HAVE_DECL_VSNPRINTF -/* Like vsprintf but prints at most N characters. */ -extern int vsnprintf (char *, size_t, const char *, va_list) ATTRIBUTE_PRINTF(3,0); -#endif - -#if defined (HAVE_DECL_STRNLEN) && !HAVE_DECL_STRNLEN -extern size_t strnlen (const char *, size_t); -#endif - -#if defined(HAVE_DECL_STRVERSCMP) && !HAVE_DECL_STRVERSCMP -/* Compare version strings. */ -extern int strverscmp (const char *, const char *); -#endif - -#if defined(HAVE_DECL_STRTOL) && !HAVE_DECL_STRTOL -extern long int strtol (const char *nptr, - char **endptr, int base); -#endif - -#if defined(HAVE_DECL_STRTOUL) && !HAVE_DECL_STRTOUL -extern unsigned long int strtoul (const char *nptr, - char **endptr, int base); -#endif - -#if defined(HAVE_LONG_LONG) && defined(HAVE_DECL_STRTOLL) && !HAVE_DECL_STRTOLL -__extension__ -extern long long int strtoll (const char *nptr, - char **endptr, int base); -#endif - -#if defined(HAVE_LONG_LONG) && defined(HAVE_DECL_STRTOULL) && !HAVE_DECL_STRTOULL -__extension__ -extern unsigned long long int strtoull (const char *nptr, - char **endptr, int base); -#endif - -#if defined(HAVE_DECL_STRVERSCMP) && !HAVE_DECL_STRVERSCMP -/* Compare version strings. */ -extern int strverscmp (const char *, const char *); -#endif - -/* Set the title of a process */ -extern void setproctitle (const char *name, ...); - -/* Increase stack limit if possible. */ -extern void stack_limit_increase (unsigned long); - -#define ARRAY_SIZE(a) (sizeof (a) / sizeof ((a)[0])) - -/* Drastically simplified alloca configurator. If we're using GCC, - we use __builtin_alloca; otherwise we use the C alloca. The C - alloca is always available. You can override GCC by defining - USE_C_ALLOCA yourself. The canonical autoconf macro C_ALLOCA is - also set/unset as it is often used to indicate whether code needs - to call alloca(0). */ -extern void *C_alloca (size_t) ATTRIBUTE_MALLOC; -#undef alloca -#if GCC_VERSION >= 2000 && !defined USE_C_ALLOCA -# define alloca(x) __builtin_alloca(x) -# undef C_ALLOCA -# define ASTRDUP(X) \ - (__extension__ ({ const char *const libiberty_optr = (X); \ - const unsigned long libiberty_len = strlen (libiberty_optr) + 1; \ - char *const libiberty_nptr = (char *const) alloca (libiberty_len); \ - (char *) memcpy (libiberty_nptr, libiberty_optr, libiberty_len); })) -#else -# define alloca(x) C_alloca(x) -# undef USE_C_ALLOCA -# define USE_C_ALLOCA 1 -# undef C_ALLOCA -# define C_ALLOCA 1 -extern const char *libiberty_optr; -extern char *libiberty_nptr; -extern unsigned long libiberty_len; -# define ASTRDUP(X) \ - (libiberty_optr = (X), \ - libiberty_len = strlen (libiberty_optr) + 1, \ - libiberty_nptr = (char *) alloca (libiberty_len), \ - (char *) memcpy (libiberty_nptr, libiberty_optr, libiberty_len)) -#endif - -#ifdef __cplusplus -} -#endif - - -#endif /* ! defined (LIBIBERTY_H) */ diff --git a/arduino/hardware/tools/avr/include/libiberty/objalloc.h b/arduino/hardware/tools/avr/include/libiberty/objalloc.h deleted file mode 100644 index 2c06350..0000000 --- a/arduino/hardware/tools/avr/include/libiberty/objalloc.h +++ /dev/null @@ -1,115 +0,0 @@ -/* objalloc.h -- routines to allocate memory for objects - Copyright (C) 1997-2015 Free Software Foundation, Inc. - Written by Ian Lance Taylor, Cygnus Solutions. - -This program is free software; you can redistribute it and/or modify it -under the terms of the GNU General Public License as published by the -Free Software Foundation; either version 2, or (at your option) any -later version. - -This program is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU General Public License for more details. - -You should have received a copy of the GNU General Public License -along with this program; if not, write to the Free Software -Foundation, 51 Franklin Street - Fifth Floor, -Boston, MA 02110-1301, USA. */ - -#ifndef OBJALLOC_H -#define OBJALLOC_H - -#include "ansidecl.h" - -/* These routines allocate space for an object. The assumption is - that the object will want to allocate space as it goes along, but - will never want to free any particular block. There is a function - to free a block, which also frees all more recently allocated - blocks. There is also a function to free all the allocated space. - - This is essentially a specialization of obstacks. The main - difference is that a block may not be allocated a bit at a time. - Another difference is that these routines are always built on top - of malloc, and always pass an malloc failure back to the caller, - unlike more recent versions of obstacks. */ - -/* This is what an objalloc structure looks like. Callers should not - refer to these fields, nor should they allocate these structure - themselves. Instead, they should only create them via - objalloc_init, and only access them via the functions and macros - listed below. The structure is only defined here so that we can - access it via macros. */ - -struct objalloc -{ - char *current_ptr; - unsigned int current_space; - void *chunks; -}; - -/* Work out the required alignment. */ - -struct objalloc_align { char x; double d; }; - -#if defined (__STDC__) && __STDC__ -#ifndef offsetof -#include -#endif -#endif -#ifndef offsetof -#define offsetof(TYPE, MEMBER) ((unsigned long) &((TYPE *)0)->MEMBER) -#endif -#define OBJALLOC_ALIGN offsetof (struct objalloc_align, d) - -/* Create an objalloc structure. Returns NULL if malloc fails. */ - -extern struct objalloc *objalloc_create (void); - -/* Allocate space from an objalloc structure. Returns NULL if malloc - fails. */ - -extern void *_objalloc_alloc (struct objalloc *, unsigned long); - -/* The macro version of objalloc_alloc. We only define this if using - gcc, because otherwise we would have to evaluate the arguments - multiple times, or use a temporary field as obstack.h does. */ - -#if defined (__GNUC__) && defined (__STDC__) && __STDC__ - -/* NextStep 2.0 cc is really gcc 1.93 but it defines __GNUC__ = 2 and - does not implement __extension__. But that compiler doesn't define - __GNUC_MINOR__. */ -#if __GNUC__ < 2 || (__NeXT__ && !__GNUC_MINOR__) -#define __extension__ -#endif - -#define objalloc_alloc(o, l) \ - __extension__ \ - ({ struct objalloc *__o = (o); \ - unsigned long __len = (l); \ - if (__len == 0) \ - __len = 1; \ - __len = (__len + OBJALLOC_ALIGN - 1) &~ (OBJALLOC_ALIGN - 1); \ - (__len != 0 && __len <= __o->current_space \ - ? (__o->current_ptr += __len, \ - __o->current_space -= __len, \ - (void *) (__o->current_ptr - __len)) \ - : _objalloc_alloc (__o, __len)); }) - -#else /* ! __GNUC__ */ - -#define objalloc_alloc(o, l) _objalloc_alloc ((o), (l)) - -#endif /* ! __GNUC__ */ - -/* Free an entire objalloc structure. */ - -extern void objalloc_free (struct objalloc *); - -/* Free a block allocated by objalloc_alloc. This also frees all more - recently allocated blocks. */ - -extern void objalloc_free_block (struct objalloc *, void *); - -#endif /* OBJALLOC_H */ diff --git a/arduino/hardware/tools/avr/include/libiberty/partition.h b/arduino/hardware/tools/avr/include/libiberty/partition.h deleted file mode 100644 index c39873b..0000000 --- a/arduino/hardware/tools/avr/include/libiberty/partition.h +++ /dev/null @@ -1,82 +0,0 @@ -/* List implementation of a partition of consecutive integers. - Copyright (C) 2000, 2001, 2002 Free Software Foundation, Inc. - Contributed by CodeSourcery, LLC. - - This file is part of GCC. - - GCC is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2, or (at your option) - any later version. - - GCC is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with GCC; see the file COPYING. If not, write to - the Free Software Foundation, 51 Franklin Street - Fifth Floor, - Boston, MA 02110-1301, USA. */ - -/* This package implements a partition of consecutive integers. The - elements are partitioned into classes. Each class is represented - by one of its elements, the canonical element, which is chosen - arbitrarily from elements in the class. The principal operations - on a partition are FIND, which takes an element, determines its - class, and returns the canonical element for that class, and UNION, - which unites the two classes that contain two given elements into a - single class. - - The list implementation used here provides constant-time finds. By - storing the size of each class with the class's canonical element, - it is able to perform unions over all the classes in the partition - in O (N log N) time. */ - -#ifndef _PARTITION_H -#define _PARTITION_H - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -#include "ansidecl.h" -#include - -struct partition_elem -{ - /* The next element in this class. Elements in each class form a - circular list. */ - struct partition_elem* next; - /* The canonical element that represents the class containing this - element. */ - int class_element; - /* The number of elements in this class. Valid only if this is the - canonical element for its class. */ - unsigned class_count; -}; - -typedef struct partition_def -{ - /* The number of elements in this partition. */ - int num_elements; - /* The elements in the partition. */ - struct partition_elem elements[1]; -} *partition; - -extern partition partition_new (int); -extern void partition_delete (partition); -extern int partition_union (partition, int, int); -extern void partition_print (partition, FILE*); - -/* Returns the canonical element corresponding to the class containing - ELEMENT__ in PARTITION__. */ - -#define partition_find(partition__, element__) \ - ((partition__)->elements[(element__)].class_element) - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - -#endif /* _PARTITION_H */ diff --git a/arduino/hardware/tools/avr/include/libiberty/safe-ctype.h b/arduino/hardware/tools/avr/include/libiberty/safe-ctype.h deleted file mode 100644 index a6d163e..0000000 --- a/arduino/hardware/tools/avr/include/libiberty/safe-ctype.h +++ /dev/null @@ -1,150 +0,0 @@ -/* replacement macros. - - Copyright (C) 2000-2015 Free Software Foundation, Inc. - Contributed by Zack Weinberg . - -This file is part of the libiberty library. -Libiberty is free software; you can redistribute it and/or -modify it under the terms of the GNU Library General Public -License as published by the Free Software Foundation; either -version 2 of the License, or (at your option) any later version. - -Libiberty is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -Library General Public License for more details. - -You should have received a copy of the GNU Library General Public -License along with libiberty; see the file COPYING.LIB. If -not, write to the Free Software Foundation, Inc., 51 Franklin Street - Fifth Floor, -Boston, MA 02110-1301, USA. */ - -/* This is a compatible replacement of the standard C library's - with the following properties: - - - Implements all isxxx() macros required by C99. - - Also implements some character classes useful when - parsing C-like languages. - - Does not change behavior depending on the current locale. - - Behaves properly for all values in the range of a signed or - unsigned char. - - To avoid conflicts, this header defines the isxxx functions in upper - case, e.g. ISALPHA not isalpha. */ - -#ifndef SAFE_CTYPE_H -#define SAFE_CTYPE_H - -/* Determine host character set. */ -#define HOST_CHARSET_UNKNOWN 0 -#define HOST_CHARSET_ASCII 1 -#define HOST_CHARSET_EBCDIC 2 - -#if '\n' == 0x0A && ' ' == 0x20 && '0' == 0x30 \ - && 'A' == 0x41 && 'a' == 0x61 && '!' == 0x21 -# define HOST_CHARSET HOST_CHARSET_ASCII -#else -# if '\n' == 0x15 && ' ' == 0x40 && '0' == 0xF0 \ - && 'A' == 0xC1 && 'a' == 0x81 && '!' == 0x5A -# define HOST_CHARSET HOST_CHARSET_EBCDIC -# else -# define HOST_CHARSET HOST_CHARSET_UNKNOWN -# endif -#endif - -/* Categories. */ - -enum { - /* In C99 */ - _sch_isblank = 0x0001, /* space \t */ - _sch_iscntrl = 0x0002, /* nonprinting characters */ - _sch_isdigit = 0x0004, /* 0-9 */ - _sch_islower = 0x0008, /* a-z */ - _sch_isprint = 0x0010, /* any printing character including ' ' */ - _sch_ispunct = 0x0020, /* all punctuation */ - _sch_isspace = 0x0040, /* space \t \n \r \f \v */ - _sch_isupper = 0x0080, /* A-Z */ - _sch_isxdigit = 0x0100, /* 0-9A-Fa-f */ - - /* Extra categories useful to cpplib. */ - _sch_isidst = 0x0200, /* A-Za-z_ */ - _sch_isvsp = 0x0400, /* \n \r */ - _sch_isnvsp = 0x0800, /* space \t \f \v \0 */ - - /* Combinations of the above. */ - _sch_isalpha = _sch_isupper|_sch_islower, /* A-Za-z */ - _sch_isalnum = _sch_isalpha|_sch_isdigit, /* A-Za-z0-9 */ - _sch_isidnum = _sch_isidst|_sch_isdigit, /* A-Za-z0-9_ */ - _sch_isgraph = _sch_isalnum|_sch_ispunct, /* isprint and not space */ - _sch_iscppsp = _sch_isvsp|_sch_isnvsp, /* isspace + \0 */ - _sch_isbasic = _sch_isprint|_sch_iscppsp /* basic charset of ISO C - (plus ` and @) */ -}; - -/* Character classification. */ -extern const unsigned short _sch_istable[256]; - -#define _sch_test(c, bit) (_sch_istable[(c) & 0xff] & (unsigned short)(bit)) - -#define ISALPHA(c) _sch_test(c, _sch_isalpha) -#define ISALNUM(c) _sch_test(c, _sch_isalnum) -#define ISBLANK(c) _sch_test(c, _sch_isblank) -#define ISCNTRL(c) _sch_test(c, _sch_iscntrl) -#define ISDIGIT(c) _sch_test(c, _sch_isdigit) -#define ISGRAPH(c) _sch_test(c, _sch_isgraph) -#define ISLOWER(c) _sch_test(c, _sch_islower) -#define ISPRINT(c) _sch_test(c, _sch_isprint) -#define ISPUNCT(c) _sch_test(c, _sch_ispunct) -#define ISSPACE(c) _sch_test(c, _sch_isspace) -#define ISUPPER(c) _sch_test(c, _sch_isupper) -#define ISXDIGIT(c) _sch_test(c, _sch_isxdigit) - -#define ISIDNUM(c) _sch_test(c, _sch_isidnum) -#define ISIDST(c) _sch_test(c, _sch_isidst) -#define IS_ISOBASIC(c) _sch_test(c, _sch_isbasic) -#define IS_VSPACE(c) _sch_test(c, _sch_isvsp) -#define IS_NVSPACE(c) _sch_test(c, _sch_isnvsp) -#define IS_SPACE_OR_NUL(c) _sch_test(c, _sch_iscppsp) - -/* Character transformation. */ -extern const unsigned char _sch_toupper[256]; -extern const unsigned char _sch_tolower[256]; -#define TOUPPER(c) _sch_toupper[(c) & 0xff] -#define TOLOWER(c) _sch_tolower[(c) & 0xff] - -/* Prevent the users of safe-ctype.h from accidently using the routines - from ctype.h. Initially, the approach was to produce an error when - detecting that ctype.h has been included. But this was causing - trouble as ctype.h might get indirectly included as a result of - including another system header (for instance gnulib's stdint.h). - So we include ctype.h here and then immediately redefine its macros. */ - -#include -#undef isalpha -#define isalpha(c) do_not_use_isalpha_with_safe_ctype -#undef isalnum -#define isalnum(c) do_not_use_isalnum_with_safe_ctype -#undef iscntrl -#define iscntrl(c) do_not_use_iscntrl_with_safe_ctype -#undef isdigit -#define isdigit(c) do_not_use_isdigit_with_safe_ctype -#undef isgraph -#define isgraph(c) do_not_use_isgraph_with_safe_ctype -#undef islower -#define islower(c) do_not_use_islower_with_safe_ctype -#undef isprint -#define isprint(c) do_not_use_isprint_with_safe_ctype -#undef ispunct -#define ispunct(c) do_not_use_ispunct_with_safe_ctype -#undef isspace -#define isspace(c) do_not_use_isspace_with_safe_ctype -#undef isupper -#define isupper(c) do_not_use_isupper_with_safe_ctype -#undef isxdigit -#define isxdigit(c) do_not_use_isxdigit_with_safe_ctype -#undef toupper -#define toupper(c) do_not_use_toupper_with_safe_ctype -#undef tolower -#define tolower(c) do_not_use_tolower_with_safe_ctype - -#endif /* SAFE_CTYPE_H */ diff --git a/arduino/hardware/tools/avr/include/libiberty/sort.h b/arduino/hardware/tools/avr/include/libiberty/sort.h deleted file mode 100644 index 23025d4..0000000 --- a/arduino/hardware/tools/avr/include/libiberty/sort.h +++ /dev/null @@ -1,48 +0,0 @@ -/* Sorting algorithms. - Copyright (C) 2000-2015 Free Software Foundation, Inc. - Contributed by Mark Mitchell . - -This file is part of GCC. - -GCC is free software; you can redistribute it and/or modify it -under the terms of the GNU General Public License as published by -the Free Software Foundation; either version 2, or (at your option) -any later version. - -GCC is distributed in the hope that it will be useful, but -WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -General Public License for more details. - -You should have received a copy of the GNU General Public License -along with GCC; see the file COPYING. If not, write to -the Free Software Foundation, 51 Franklin Street - Fifth Floor, -Boston, MA 02110-1301, USA. */ - -#ifndef SORT_H -#define SORT_H - -#include /* For size_t */ -#ifdef __STDC__ -#include -#endif /* __STDC__ */ - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -#include "ansidecl.h" - -/* Sort an array of pointers. */ - -extern void sort_pointers (size_t, void **, void **); - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - -#endif /* SORT_H */ - - - - diff --git a/arduino/hardware/tools/avr/include/libiberty/splay-tree.h b/arduino/hardware/tools/avr/include/libiberty/splay-tree.h deleted file mode 100644 index f71d7d7..0000000 --- a/arduino/hardware/tools/avr/include/libiberty/splay-tree.h +++ /dev/null @@ -1,156 +0,0 @@ -/* A splay-tree datatype. - Copyright (C) 1998-2015 Free Software Foundation, Inc. - Contributed by Mark Mitchell (mark@markmitchell.com). - - This file is part of GCC. - - GCC is free software; you can redistribute it and/or modify it - under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2, or (at your option) - any later version. - - GCC is distributed in the hope that it will be useful, but - WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - General Public License for more details. - - You should have received a copy of the GNU General Public License - along with GCC; see the file COPYING. If not, write to - the Free Software Foundation, 51 Franklin Street - Fifth Floor, - Boston, MA 02110-1301, USA. */ - -/* For an easily readable description of splay-trees, see: - - Lewis, Harry R. and Denenberg, Larry. Data Structures and Their - Algorithms. Harper-Collins, Inc. 1991. - - The major feature of splay trees is that all basic tree operations - are amortized O(log n) time for a tree with n nodes. */ - -#ifndef _SPLAY_TREE_H -#define _SPLAY_TREE_H - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -#include "ansidecl.h" - -#ifdef HAVE_STDINT_H -#include -#endif -#ifdef HAVE_INTTYPES_H -#include -#endif - -/* Use typedefs for the key and data types to facilitate changing - these types, if necessary. These types should be sufficiently wide - that any pointer or scalar can be cast to these types, and then - cast back, without loss of precision. */ -typedef uintptr_t splay_tree_key; -typedef uintptr_t splay_tree_value; - -/* Forward declaration for a node in the tree. */ -typedef struct splay_tree_node_s *splay_tree_node; - -/* The type of a function which compares two splay-tree keys. The - function should return values as for qsort. */ -typedef int (*splay_tree_compare_fn) (splay_tree_key, splay_tree_key); - -/* The type of a function used to deallocate any resources associated - with the key. */ -typedef void (*splay_tree_delete_key_fn) (splay_tree_key); - -/* The type of a function used to deallocate any resources associated - with the value. */ -typedef void (*splay_tree_delete_value_fn) (splay_tree_value); - -/* The type of a function used to iterate over the tree. */ -typedef int (*splay_tree_foreach_fn) (splay_tree_node, void*); - -/* The type of a function used to allocate memory for tree root and - node structures. The first argument is the number of bytes needed; - the second is a data pointer the splay tree functions pass through - to the allocator. This function must never return zero. */ -typedef void *(*splay_tree_allocate_fn) (int, void *); - -/* The type of a function used to free memory allocated using the - corresponding splay_tree_allocate_fn. The first argument is the - memory to be freed; the latter is a data pointer the splay tree - functions pass through to the freer. */ -typedef void (*splay_tree_deallocate_fn) (void *, void *); - -/* The nodes in the splay tree. */ -struct splay_tree_node_s { - /* The key. */ - splay_tree_key key; - - /* The value. */ - splay_tree_value value; - - /* The left and right children, respectively. */ - splay_tree_node left; - splay_tree_node right; -}; - -/* The splay tree itself. */ -struct splay_tree_s { - /* The root of the tree. */ - splay_tree_node root; - - /* The comparision function. */ - splay_tree_compare_fn comp; - - /* The deallocate-key function. NULL if no cleanup is necessary. */ - splay_tree_delete_key_fn delete_key; - - /* The deallocate-value function. NULL if no cleanup is necessary. */ - splay_tree_delete_value_fn delete_value; - - /* Node allocate function. Takes allocate_data as a parameter. */ - splay_tree_allocate_fn allocate; - - /* Free function for nodes and trees. Takes allocate_data as a parameter. */ - splay_tree_deallocate_fn deallocate; - - /* Parameter for allocate/free functions. */ - void *allocate_data; -}; - -typedef struct splay_tree_s *splay_tree; - -extern splay_tree splay_tree_new (splay_tree_compare_fn, - splay_tree_delete_key_fn, - splay_tree_delete_value_fn); -extern splay_tree splay_tree_new_with_allocator (splay_tree_compare_fn, - splay_tree_delete_key_fn, - splay_tree_delete_value_fn, - splay_tree_allocate_fn, - splay_tree_deallocate_fn, - void *); -extern splay_tree splay_tree_new_typed_alloc (splay_tree_compare_fn, - splay_tree_delete_key_fn, - splay_tree_delete_value_fn, - splay_tree_allocate_fn, - splay_tree_allocate_fn, - splay_tree_deallocate_fn, - void *); -extern void splay_tree_delete (splay_tree); -extern splay_tree_node splay_tree_insert (splay_tree, - splay_tree_key, - splay_tree_value); -extern void splay_tree_remove (splay_tree, splay_tree_key); -extern splay_tree_node splay_tree_lookup (splay_tree, splay_tree_key); -extern splay_tree_node splay_tree_predecessor (splay_tree, splay_tree_key); -extern splay_tree_node splay_tree_successor (splay_tree, splay_tree_key); -extern splay_tree_node splay_tree_max (splay_tree); -extern splay_tree_node splay_tree_min (splay_tree); -extern int splay_tree_foreach (splay_tree, splay_tree_foreach_fn, void*); -extern int splay_tree_compare_ints (splay_tree_key, splay_tree_key); -extern int splay_tree_compare_pointers (splay_tree_key, splay_tree_key); - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - -#endif /* _SPLAY_TREE_H */ diff --git a/arduino/hardware/tools/avr/include/libiberty/timeval-utils.h b/arduino/hardware/tools/avr/include/libiberty/timeval-utils.h deleted file mode 100644 index adbe818..0000000 --- a/arduino/hardware/tools/avr/include/libiberty/timeval-utils.h +++ /dev/null @@ -1,40 +0,0 @@ -/* Basic struct timeval utilities. - Copyright (C) 2011-2015 Free Software Foundation, Inc. - -This file is part of the libiberty library. -Libiberty is free software; you can redistribute it and/or -modify it under the terms of the GNU Library General Public -License as published by the Free Software Foundation; either -version 2 of the License, or (at your option) any later version. - -Libiberty is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -Library General Public License for more details. - -You should have received a copy of the GNU Library General Public -License along with libiberty; see the file COPYING.LIB. If not, -write to the Free Software Foundation, Inc., 51 Franklin Street - Fifth Floor, -Boston, MA 02110-1301, USA. */ - -#ifndef TIMEVAL_UTILS_H -#define TIMEVAL_UTILS_H - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -/* forward decl */ -struct timeval; - -extern void timeval_add (struct timeval *result, - const struct timeval *a, const struct timeval *b); - -extern void timeval_sub (struct timeval *result, - const struct timeval *a, const struct timeval *b); - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - -#endif /* TIMEVAL_UTILS_H */ diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/avr25/libgcc.a b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/avr25/libgcc.a deleted file mode 100644 index 3e3698a..0000000 Binary files a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/avr25/libgcc.a and /dev/null differ diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/avr25/libgcov.a b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/avr25/libgcov.a deleted file mode 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--git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/avrxmega7/libgcc.a b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/avrxmega7/libgcc.a deleted file mode 100644 index 9613efb..0000000 Binary files a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/avrxmega7/libgcc.a and /dev/null differ diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/avrxmega7/libgcov.a b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/avrxmega7/libgcov.a deleted file mode 100644 index 876847c..0000000 Binary files a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/avrxmega7/libgcov.a and /dev/null differ diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-at43usb320 b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-at43usb320 deleted file mode 100644 index 491255e..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-at43usb320 +++ /dev/null @@ -1,99 +0,0 @@ -# -# Auto-generated specs for AVR device at43usb320 (core avr31, 16-bit SP) -# -# Generated by : ./gcc/config/avr/gen-avr-mmcu-specs.c -# Generated from : ./gcc/config/gcc.c -# ./gcc/config/avr/specs.h -# ./gcc/config/avr/avrlibc.h -# Used by : avr-gcc compiler driver -# Used for : building command options for sub-processes -# -# See -# for a documentation of spec files. - - -# If you intend to use an existing device specs file as a starting point -# for a new device spec file, make sure you are copying from a specs -# file for a device from the same core architecture and SP width. -# See for a description -# of how to use such own spec files. - -*avrlibc_startfile: - crtat43usb320.o%s - -*avrlibc_devicelib: - %{!nodevicelib:-lat43usb320} - -*cc1_n_flash: - %{!mn-flash=*:-mn-flash=1} - -*cc1_rmw: - %{mrmw} - -*cc1_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*cc1_absdata: - %{mabsdata} - -*asm_arch: - -mmcu=avr31 - -*asm_relax: - %{mrelax:--mlink-relax} - -*asm_rmw: - %{mrmw} - -*asm_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*link_pmem_wrap: - %{mpmem-wrap-around: --pmem-wrap-around=64k} - -*link_relax: - %{mrelax:--relax} - -*link_arch: - %{mmcu=*:-m%*} - -*link_data_start: - - -*link_text_start: - - -*self_spec: - %{!mmcu=avr*: % -# #elif ... -# -# If no device macro is defined, AVR-LibC uses __AVR_DEV_LIB_NAME__ -# as fallback to determine the name of the device header as -# -# "avr/io" + __AVR_DEV_LIB_NAME__ + ".h" -# -# If you provide your own specs file for a device not yet known to -# AVR-LibC, you can now define the hook macro __AVR_DEV_LIB_NAME__ -# as needed so that -# -# #include -# -# will include the desired device header. For ATmega8A the supplement -# to *cpp would read -# -# -D__AVR_DEV_LIB_NAME__=m8a - - -*cpp: - -D__AVR_AT43USB320__ -D__AVR_DEVICE_NAME__=at43usb320 - -# End of file diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-at43usb355 b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-at43usb355 deleted file mode 100644 index e0dc63f..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-at43usb355 +++ /dev/null @@ -1,99 +0,0 @@ -# -# Auto-generated specs for AVR device at43usb355 (core avr3, 16-bit SP) -# -# Generated by : ./gcc/config/avr/gen-avr-mmcu-specs.c -# Generated from : ./gcc/config/gcc.c -# ./gcc/config/avr/specs.h -# ./gcc/config/avr/avrlibc.h -# Used by : avr-gcc compiler driver -# Used for : building command options for sub-processes -# -# See -# for a documentation of spec files. - - -# If you intend to use an existing device specs file as a starting point -# for a new device spec file, make sure you are copying from a specs -# file for a device from the same core architecture and SP width. -# See for a description -# of how to use such own spec files. - -*avrlibc_startfile: - crtat43usb355.o%s - -*avrlibc_devicelib: - %{!nodevicelib:-lat43usb355} - -*cc1_n_flash: - %{!mn-flash=*:-mn-flash=1} - -*cc1_rmw: - %{mrmw} - -*cc1_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*cc1_absdata: - %{mabsdata} - -*asm_arch: - -mmcu=avr3 - -*asm_relax: - %{mrelax:--mlink-relax} - -*asm_rmw: - %{mrmw} - -*asm_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*link_pmem_wrap: - - -*link_relax: - %{mrelax:--relax} - -*link_arch: - %{mmcu=*:-m%*} - -*link_data_start: - - -*link_text_start: - - -*self_spec: - %{!mmcu=avr*: % -# #elif ... -# -# If no device macro is defined, AVR-LibC uses __AVR_DEV_LIB_NAME__ -# as fallback to determine the name of the device header as -# -# "avr/io" + __AVR_DEV_LIB_NAME__ + ".h" -# -# If you provide your own specs file for a device not yet known to -# AVR-LibC, you can now define the hook macro __AVR_DEV_LIB_NAME__ -# as needed so that -# -# #include -# -# will include the desired device header. For ATmega8A the supplement -# to *cpp would read -# -# -D__AVR_DEV_LIB_NAME__=m8a - - -*cpp: - -D__AVR_AT43USB355__ -D__AVR_DEVICE_NAME__=at43usb355 - -# End of file diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-at76c711 b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-at76c711 deleted file mode 100644 index f40e16d..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-at76c711 +++ /dev/null @@ -1,99 +0,0 @@ -# -# Auto-generated specs for AVR device at76c711 (core avr3, 16-bit SP) -# -# Generated by : ./gcc/config/avr/gen-avr-mmcu-specs.c -# Generated from : ./gcc/config/gcc.c -# ./gcc/config/avr/specs.h -# ./gcc/config/avr/avrlibc.h -# Used by : avr-gcc compiler driver -# Used for : building command options for sub-processes -# -# See -# for a documentation of spec files. - - -# If you intend to use an existing device specs file as a starting point -# for a new device spec file, make sure you are copying from a specs -# file for a device from the same core architecture and SP width. -# See for a description -# of how to use such own spec files. - -*avrlibc_startfile: - crtat76c711.o%s - -*avrlibc_devicelib: - %{!nodevicelib:-lat76c711} - -*cc1_n_flash: - %{!mn-flash=*:-mn-flash=1} - -*cc1_rmw: - %{mrmw} - -*cc1_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*cc1_absdata: - %{mabsdata} - -*asm_arch: - -mmcu=avr3 - -*asm_relax: - %{mrelax:--mlink-relax} - -*asm_rmw: - %{mrmw} - -*asm_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*link_pmem_wrap: - %{mpmem-wrap-around: --pmem-wrap-around=16k} - -*link_relax: - %{mrelax:--relax} - -*link_arch: - %{mmcu=*:-m%*} - -*link_data_start: - - -*link_text_start: - - -*self_spec: - %{!mmcu=avr*: % -# #elif ... -# -# If no device macro is defined, AVR-LibC uses __AVR_DEV_LIB_NAME__ -# as fallback to determine the name of the device header as -# -# "avr/io" + __AVR_DEV_LIB_NAME__ + ".h" -# -# If you provide your own specs file for a device not yet known to -# AVR-LibC, you can now define the hook macro __AVR_DEV_LIB_NAME__ -# as needed so that -# -# #include -# -# will include the desired device header. For ATmega8A the supplement -# to *cpp would read -# -# -D__AVR_DEV_LIB_NAME__=m8a - - -*cpp: - -D__AVR_AT76C711__ -D__AVR_DEVICE_NAME__=at76c711 - -# End of file diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-at86rf401 b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-at86rf401 deleted file mode 100644 index f9ae70e..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-at86rf401 +++ /dev/null @@ -1,99 +0,0 @@ -# -# Auto-generated specs for AVR device at86rf401 (core avr25, 16-bit SP) -# -# Generated by : ./gcc/config/avr/gen-avr-mmcu-specs.c -# Generated from : ./gcc/config/gcc.c -# ./gcc/config/avr/specs.h -# ./gcc/config/avr/avrlibc.h -# Used by : avr-gcc compiler driver -# Used for : building command options for sub-processes -# -# See -# for a documentation of spec files. - - -# If you intend to use an existing device specs file as a starting point -# for a new device spec file, make sure you are copying from a specs -# file for a device from the same core architecture and SP width. -# See for a description -# of how to use such own spec files. - -*avrlibc_startfile: - crtat86rf401.o%s - -*avrlibc_devicelib: - %{!nodevicelib:-lat86rf401} - -*cc1_n_flash: - %{!mn-flash=*:-mn-flash=1} - -*cc1_rmw: - %{mrmw} - -*cc1_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*cc1_absdata: - %{mabsdata} - -*asm_arch: - -mmcu=avr25 - -*asm_relax: - %{mrelax:--mlink-relax} - -*asm_rmw: - %{mrmw} - -*asm_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*link_pmem_wrap: - - -*link_relax: - %{mrelax:--relax} - -*link_arch: - %{mmcu=*:-m%*} - -*link_data_start: - - -*link_text_start: - - -*self_spec: - %{!mmcu=avr*: % -# #elif ... -# -# If no device macro is defined, AVR-LibC uses __AVR_DEV_LIB_NAME__ -# as fallback to determine the name of the device header as -# -# "avr/io" + __AVR_DEV_LIB_NAME__ + ".h" -# -# If you provide your own specs file for a device not yet known to -# AVR-LibC, you can now define the hook macro __AVR_DEV_LIB_NAME__ -# as needed so that -# -# #include -# -# will include the desired device header. For ATmega8A the supplement -# to *cpp would read -# -# -D__AVR_DEV_LIB_NAME__=m8a - - -*cpp: - -D__AVR_AT86RF401__ -D__AVR_DEVICE_NAME__=at86rf401 - -# End of file diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-at90c8534 b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-at90c8534 deleted file mode 100644 index eb209fc..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-at90c8534 +++ /dev/null @@ -1,99 +0,0 @@ -# -# Auto-generated specs for AVR device at90c8534 (core avr2, 16-bit SP) -# -# Generated by : ./gcc/config/avr/gen-avr-mmcu-specs.c -# Generated from : ./gcc/config/gcc.c -# ./gcc/config/avr/specs.h -# ./gcc/config/avr/avrlibc.h -# Used by : avr-gcc compiler driver -# Used for : building command options for sub-processes -# -# See -# for a documentation of spec files. - - -# If you intend to use an existing device specs file as a starting point -# for a new device spec file, make sure you are copying from a specs -# file for a device from the same core architecture and SP width. -# See for a description -# of how to use such own spec files. - -*avrlibc_startfile: - crtat90c8534.o%s - -*avrlibc_devicelib: - %{!nodevicelib:-lat90c8534} - -*cc1_n_flash: - %{!mn-flash=*:-mn-flash=1} - -*cc1_rmw: - %{mrmw} - -*cc1_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*cc1_absdata: - %{mabsdata} - -*asm_arch: - -mmcu=avr2 - -*asm_relax: - %{mrelax:--mlink-relax} - -*asm_rmw: - %{mrmw} - -*asm_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*link_pmem_wrap: - %{!mno-pmem-wrap-around: --pmem-wrap-around=8k} - -*link_relax: - %{mrelax:--relax} - -*link_arch: - %{mmcu=*:-m%*} - -*link_data_start: - - -*link_text_start: - - -*self_spec: - %{!mmcu=avr*: % -# #elif ... -# -# If no device macro is defined, AVR-LibC uses __AVR_DEV_LIB_NAME__ -# as fallback to determine the name of the device header as -# -# "avr/io" + __AVR_DEV_LIB_NAME__ + ".h" -# -# If you provide your own specs file for a device not yet known to -# AVR-LibC, you can now define the hook macro __AVR_DEV_LIB_NAME__ -# as needed so that -# -# #include -# -# will include the desired device header. For ATmega8A the supplement -# to *cpp would read -# -# -D__AVR_DEV_LIB_NAME__=m8a - - -*cpp: - -D__AVR_AT90C8534__ -D__AVR_DEVICE_NAME__=at90c8534 - -# End of file diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-at90can128 b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-at90can128 deleted file mode 100644 index 9062a34..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-at90can128 +++ /dev/null @@ -1,99 +0,0 @@ -# -# Auto-generated specs for AVR device at90can128 (core avr51, 16-bit SP) -# -# Generated by : ./gcc/config/avr/gen-avr-mmcu-specs.c -# Generated from : ./gcc/config/gcc.c -# ./gcc/config/avr/specs.h -# ./gcc/config/avr/avrlibc.h -# Used by : avr-gcc compiler driver -# Used for : building command options for sub-processes -# -# See -# for a documentation of spec files. - - -# If you intend to use an existing device specs file as a starting point -# for a new device spec file, make sure you are copying from a specs -# file for a device from the same core architecture and SP width. -# See for a description -# of how to use such own spec files. - -*avrlibc_startfile: - crtat90can128.o%s - -*avrlibc_devicelib: - %{!nodevicelib:-lat90can128} - -*cc1_n_flash: - %{!mn-flash=*:-mn-flash=2} - -*cc1_rmw: - %{mrmw} - -*cc1_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*cc1_absdata: - %{mabsdata} - -*asm_arch: - -mmcu=avr51 - -*asm_relax: - %{mrelax:--mlink-relax} - -*asm_rmw: - %{mrmw} - -*asm_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*link_pmem_wrap: - - -*link_relax: - %{mrelax:--relax} - -*link_arch: - %{mmcu=*:-m%*} - -*link_data_start: - -Tdata 0x800100 - -*link_text_start: - - -*self_spec: - %{!mmcu=avr*: % -# #elif ... -# -# If no device macro is defined, AVR-LibC uses __AVR_DEV_LIB_NAME__ -# as fallback to determine the name of the device header as -# -# "avr/io" + __AVR_DEV_LIB_NAME__ + ".h" -# -# If you provide your own specs file for a device not yet known to -# AVR-LibC, you can now define the hook macro __AVR_DEV_LIB_NAME__ -# as needed so that -# -# #include -# -# will include the desired device header. For ATmega8A the supplement -# to *cpp would read -# -# -D__AVR_DEV_LIB_NAME__=m8a - - -*cpp: - -D__AVR_AT90CAN128__ -D__AVR_DEVICE_NAME__=at90can128 - -# End of file diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-at90can32 b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-at90can32 deleted file mode 100644 index 2d296fe..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-at90can32 +++ /dev/null @@ -1,99 +0,0 @@ -# -# Auto-generated specs for AVR device at90can32 (core avr5, 16-bit SP) -# -# Generated by : ./gcc/config/avr/gen-avr-mmcu-specs.c -# Generated from : ./gcc/config/gcc.c -# ./gcc/config/avr/specs.h -# ./gcc/config/avr/avrlibc.h -# Used by : avr-gcc compiler driver -# Used for : building command options for sub-processes -# -# See -# for a documentation of spec files. - - -# If you intend to use an existing device specs file as a starting point -# for a new device spec file, make sure you are copying from a specs -# file for a device from the same core architecture and SP width. -# See for a description -# of how to use such own spec files. - -*avrlibc_startfile: - crtat90can32.o%s - -*avrlibc_devicelib: - %{!nodevicelib:-lat90can32} - -*cc1_n_flash: - %{!mn-flash=*:-mn-flash=1} - -*cc1_rmw: - %{mrmw} - -*cc1_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*cc1_absdata: - %{mabsdata} - -*asm_arch: - -mmcu=avr5 - -*asm_relax: - %{mrelax:--mlink-relax} - -*asm_rmw: - %{mrmw} - -*asm_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*link_pmem_wrap: - %{mpmem-wrap-around: --pmem-wrap-around=32k} - -*link_relax: - %{mrelax:--relax} - -*link_arch: - %{mmcu=*:-m%*} - -*link_data_start: - -Tdata 0x800100 - -*link_text_start: - - -*self_spec: - %{!mmcu=avr*: % -# #elif ... -# -# If no device macro is defined, AVR-LibC uses __AVR_DEV_LIB_NAME__ -# as fallback to determine the name of the device header as -# -# "avr/io" + __AVR_DEV_LIB_NAME__ + ".h" -# -# If you provide your own specs file for a device not yet known to -# AVR-LibC, you can now define the hook macro __AVR_DEV_LIB_NAME__ -# as needed so that -# -# #include -# -# will include the desired device header. For ATmega8A the supplement -# to *cpp would read -# -# -D__AVR_DEV_LIB_NAME__=m8a - - -*cpp: - -D__AVR_AT90CAN32__ -D__AVR_DEVICE_NAME__=at90can32 - -# End of file diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-at90can64 b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-at90can64 deleted file mode 100644 index 2d86f22..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-at90can64 +++ /dev/null @@ -1,99 +0,0 @@ -# -# Auto-generated specs for AVR device at90can64 (core avr5, 16-bit SP) -# -# Generated by : ./gcc/config/avr/gen-avr-mmcu-specs.c -# Generated from : ./gcc/config/gcc.c -# ./gcc/config/avr/specs.h -# ./gcc/config/avr/avrlibc.h -# Used by : avr-gcc compiler driver -# Used for : building command options for sub-processes -# -# See -# for a documentation of spec files. - - -# If you intend to use an existing device specs file as a starting point -# for a new device spec file, make sure you are copying from a specs -# file for a device from the same core architecture and SP width. -# See for a description -# of how to use such own spec files. - -*avrlibc_startfile: - crtat90can64.o%s - -*avrlibc_devicelib: - %{!nodevicelib:-lat90can64} - -*cc1_n_flash: - %{!mn-flash=*:-mn-flash=1} - -*cc1_rmw: - %{mrmw} - -*cc1_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*cc1_absdata: - %{mabsdata} - -*asm_arch: - -mmcu=avr5 - -*asm_relax: - %{mrelax:--mlink-relax} - -*asm_rmw: - %{mrmw} - -*asm_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*link_pmem_wrap: - %{mpmem-wrap-around: --pmem-wrap-around=64k} - -*link_relax: - %{mrelax:--relax} - -*link_arch: - %{mmcu=*:-m%*} - -*link_data_start: - -Tdata 0x800100 - -*link_text_start: - - -*self_spec: - %{!mmcu=avr*: % -# #elif ... -# -# If no device macro is defined, AVR-LibC uses __AVR_DEV_LIB_NAME__ -# as fallback to determine the name of the device header as -# -# "avr/io" + __AVR_DEV_LIB_NAME__ + ".h" -# -# If you provide your own specs file for a device not yet known to -# AVR-LibC, you can now define the hook macro __AVR_DEV_LIB_NAME__ -# as needed so that -# -# #include -# -# will include the desired device header. For ATmega8A the supplement -# to *cpp would read -# -# -D__AVR_DEV_LIB_NAME__=m8a - - -*cpp: - -D__AVR_AT90CAN64__ -D__AVR_DEVICE_NAME__=at90can64 - -# End of file diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-at90pwm1 b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-at90pwm1 deleted file mode 100644 index f77e20f..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-at90pwm1 +++ /dev/null @@ -1,99 +0,0 @@ -# -# Auto-generated specs for AVR device at90pwm1 (core avr4, 16-bit SP) -# -# Generated by : ./gcc/config/avr/gen-avr-mmcu-specs.c -# Generated from : ./gcc/config/gcc.c -# ./gcc/config/avr/specs.h -# ./gcc/config/avr/avrlibc.h -# Used by : avr-gcc compiler driver -# Used for : building command options for sub-processes -# -# See -# for a documentation of spec files. - - -# If you intend to use an existing device specs file as a starting point -# for a new device spec file, make sure you are copying from a specs -# file for a device from the same core architecture and SP width. -# See for a description -# of how to use such own spec files. - -*avrlibc_startfile: - crtat90pwm1.o%s - -*avrlibc_devicelib: - %{!nodevicelib:-lat90pwm1} - -*cc1_n_flash: - %{!mn-flash=*:-mn-flash=1} - -*cc1_rmw: - %{mrmw} - -*cc1_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*cc1_absdata: - %{mabsdata} - -*asm_arch: - -mmcu=avr4 - -*asm_relax: - %{mrelax:--mlink-relax} - -*asm_rmw: - %{mrmw} - -*asm_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*link_pmem_wrap: - %{!mno-pmem-wrap-around: --pmem-wrap-around=8k} - -*link_relax: - %{mrelax:--relax} - -*link_arch: - %{mmcu=*:-m%*} - -*link_data_start: - -Tdata 0x800100 - -*link_text_start: - - -*self_spec: - %{!mmcu=avr*: % -# #elif ... -# -# If no device macro is defined, AVR-LibC uses __AVR_DEV_LIB_NAME__ -# as fallback to determine the name of the device header as -# -# "avr/io" + __AVR_DEV_LIB_NAME__ + ".h" -# -# If you provide your own specs file for a device not yet known to -# AVR-LibC, you can now define the hook macro __AVR_DEV_LIB_NAME__ -# as needed so that -# -# #include -# -# will include the desired device header. For ATmega8A the supplement -# to *cpp would read -# -# -D__AVR_DEV_LIB_NAME__=m8a - - -*cpp: - -D__AVR_AT90PWM1__ -D__AVR_DEVICE_NAME__=at90pwm1 - -# End of file diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-at90pwm161 b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-at90pwm161 deleted file mode 100644 index cdc0af3..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-at90pwm161 +++ /dev/null @@ -1,99 +0,0 @@ -# -# Auto-generated specs for AVR device at90pwm161 (core avr5, 16-bit SP) -# -# Generated by : ./gcc/config/avr/gen-avr-mmcu-specs.c -# Generated from : ./gcc/config/gcc.c -# ./gcc/config/avr/specs.h -# ./gcc/config/avr/avrlibc.h -# Used by : avr-gcc compiler driver -# Used for : building command options for sub-processes -# -# See -# for a documentation of spec files. - - -# If you intend to use an existing device specs file as a starting point -# for a new device spec file, make sure you are copying from a specs -# file for a device from the same core architecture and SP width. -# See for a description -# of how to use such own spec files. - -*avrlibc_startfile: - crtat90pwm161.o%s - -*avrlibc_devicelib: - %{!nodevicelib:-lat90pwm161} - -*cc1_n_flash: - %{!mn-flash=*:-mn-flash=1} - -*cc1_rmw: - %{mrmw} - -*cc1_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*cc1_absdata: - %{mabsdata} - -*asm_arch: - -mmcu=avr5 - -*asm_relax: - %{mrelax:--mlink-relax} - -*asm_rmw: - %{mrmw} - -*asm_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*link_pmem_wrap: - %{mpmem-wrap-around: --pmem-wrap-around=16k} - -*link_relax: - %{mrelax:--relax} - -*link_arch: - %{mmcu=*:-m%*} - -*link_data_start: - -Tdata 0x800100 - -*link_text_start: - - -*self_spec: - %{!mmcu=avr*: % -# #elif ... -# -# If no device macro is defined, AVR-LibC uses __AVR_DEV_LIB_NAME__ -# as fallback to determine the name of the device header as -# -# "avr/io" + __AVR_DEV_LIB_NAME__ + ".h" -# -# If you provide your own specs file for a device not yet known to -# AVR-LibC, you can now define the hook macro __AVR_DEV_LIB_NAME__ -# as needed so that -# -# #include -# -# will include the desired device header. For ATmega8A the supplement -# to *cpp would read -# -# -D__AVR_DEV_LIB_NAME__=m8a - - -*cpp: - -D__AVR_AT90PWM161__ -D__AVR_DEVICE_NAME__=at90pwm161 - -# End of file diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-at90pwm2 b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-at90pwm2 deleted file mode 100644 index e862590..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-at90pwm2 +++ /dev/null @@ -1,99 +0,0 @@ -# -# Auto-generated specs for AVR device at90pwm2 (core avr4, 16-bit SP) -# -# Generated by : ./gcc/config/avr/gen-avr-mmcu-specs.c -# Generated from : ./gcc/config/gcc.c -# ./gcc/config/avr/specs.h -# ./gcc/config/avr/avrlibc.h -# Used by : avr-gcc compiler driver -# Used for : building command options for sub-processes -# -# See -# for a documentation of spec files. - - -# If you intend to use an existing device specs file as a starting point -# for a new device spec file, make sure you are copying from a specs -# file for a device from the same core architecture and SP width. -# See for a description -# of how to use such own spec files. - -*avrlibc_startfile: - crtat90pwm2.o%s - -*avrlibc_devicelib: - %{!nodevicelib:-lat90pwm2} - -*cc1_n_flash: - %{!mn-flash=*:-mn-flash=1} - -*cc1_rmw: - %{mrmw} - -*cc1_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*cc1_absdata: - %{mabsdata} - -*asm_arch: - -mmcu=avr4 - -*asm_relax: - %{mrelax:--mlink-relax} - -*asm_rmw: - %{mrmw} - -*asm_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*link_pmem_wrap: - %{!mno-pmem-wrap-around: --pmem-wrap-around=8k} - -*link_relax: - %{mrelax:--relax} - -*link_arch: - %{mmcu=*:-m%*} - -*link_data_start: - -Tdata 0x800100 - -*link_text_start: - - -*self_spec: - %{!mmcu=avr*: % -# #elif ... -# -# If no device macro is defined, AVR-LibC uses __AVR_DEV_LIB_NAME__ -# as fallback to determine the name of the device header as -# -# "avr/io" + __AVR_DEV_LIB_NAME__ + ".h" -# -# If you provide your own specs file for a device not yet known to -# AVR-LibC, you can now define the hook macro __AVR_DEV_LIB_NAME__ -# as needed so that -# -# #include -# -# will include the desired device header. For ATmega8A the supplement -# to *cpp would read -# -# -D__AVR_DEV_LIB_NAME__=m8a - - -*cpp: - -D__AVR_AT90PWM2__ -D__AVR_DEVICE_NAME__=at90pwm2 - -# End of file diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-at90pwm216 b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-at90pwm216 deleted file mode 100644 index b505616..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-at90pwm216 +++ /dev/null @@ -1,99 +0,0 @@ -# -# Auto-generated specs for AVR device at90pwm216 (core avr5, 16-bit SP) -# -# Generated by : ./gcc/config/avr/gen-avr-mmcu-specs.c -# Generated from : ./gcc/config/gcc.c -# ./gcc/config/avr/specs.h -# ./gcc/config/avr/avrlibc.h -# Used by : avr-gcc compiler driver -# Used for : building command options for sub-processes -# -# See -# for a documentation of spec files. - - -# If you intend to use an existing device specs file as a starting point -# for a new device spec file, make sure you are copying from a specs -# file for a device from the same core architecture and SP width. -# See for a description -# of how to use such own spec files. - -*avrlibc_startfile: - crtat90pwm216.o%s - -*avrlibc_devicelib: - %{!nodevicelib:-lat90pwm216} - -*cc1_n_flash: - %{!mn-flash=*:-mn-flash=1} - -*cc1_rmw: - %{mrmw} - -*cc1_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*cc1_absdata: - %{mabsdata} - -*asm_arch: - -mmcu=avr5 - -*asm_relax: - %{mrelax:--mlink-relax} - -*asm_rmw: - %{mrmw} - -*asm_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*link_pmem_wrap: - %{mpmem-wrap-around: --pmem-wrap-around=16k} - -*link_relax: - %{mrelax:--relax} - -*link_arch: - %{mmcu=*:-m%*} - -*link_data_start: - -Tdata 0x800100 - -*link_text_start: - - -*self_spec: - %{!mmcu=avr*: % -# #elif ... -# -# If no device macro is defined, AVR-LibC uses __AVR_DEV_LIB_NAME__ -# as fallback to determine the name of the device header as -# -# "avr/io" + __AVR_DEV_LIB_NAME__ + ".h" -# -# If you provide your own specs file for a device not yet known to -# AVR-LibC, you can now define the hook macro __AVR_DEV_LIB_NAME__ -# as needed so that -# -# #include -# -# will include the desired device header. For ATmega8A the supplement -# to *cpp would read -# -# -D__AVR_DEV_LIB_NAME__=m8a - - -*cpp: - -D__AVR_AT90PWM216__ -D__AVR_DEVICE_NAME__=at90pwm216 - -# End of file diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-at90pwm2b b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-at90pwm2b deleted file mode 100644 index eee6947..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-at90pwm2b +++ /dev/null @@ -1,99 +0,0 @@ -# -# Auto-generated specs for AVR device at90pwm2b (core avr4, 16-bit SP) -# -# Generated by : ./gcc/config/avr/gen-avr-mmcu-specs.c -# Generated from : ./gcc/config/gcc.c -# ./gcc/config/avr/specs.h -# ./gcc/config/avr/avrlibc.h -# Used by : avr-gcc compiler driver -# Used for : building command options for sub-processes -# -# See -# for a documentation of spec files. - - -# If you intend to use an existing device specs file as a starting point -# for a new device spec file, make sure you are copying from a specs -# file for a device from the same core architecture and SP width. -# See for a description -# of how to use such own spec files. - -*avrlibc_startfile: - crtat90pwm2b.o%s - -*avrlibc_devicelib: - %{!nodevicelib:-lat90pwm2b} - -*cc1_n_flash: - %{!mn-flash=*:-mn-flash=1} - -*cc1_rmw: - %{mrmw} - -*cc1_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*cc1_absdata: - %{mabsdata} - -*asm_arch: - -mmcu=avr4 - -*asm_relax: - %{mrelax:--mlink-relax} - -*asm_rmw: - %{mrmw} - -*asm_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*link_pmem_wrap: - %{!mno-pmem-wrap-around: --pmem-wrap-around=8k} - -*link_relax: - %{mrelax:--relax} - -*link_arch: - %{mmcu=*:-m%*} - -*link_data_start: - -Tdata 0x800100 - -*link_text_start: - - -*self_spec: - %{!mmcu=avr*: % -# #elif ... -# -# If no device macro is defined, AVR-LibC uses __AVR_DEV_LIB_NAME__ -# as fallback to determine the name of the device header as -# -# "avr/io" + __AVR_DEV_LIB_NAME__ + ".h" -# -# If you provide your own specs file for a device not yet known to -# AVR-LibC, you can now define the hook macro __AVR_DEV_LIB_NAME__ -# as needed so that -# -# #include -# -# will include the desired device header. For ATmega8A the supplement -# to *cpp would read -# -# -D__AVR_DEV_LIB_NAME__=m8a - - -*cpp: - -D__AVR_AT90PWM2B__ -D__AVR_DEVICE_NAME__=at90pwm2b - -# End of file diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-at90pwm3 b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-at90pwm3 deleted file mode 100644 index 33b3476..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-at90pwm3 +++ /dev/null @@ -1,99 +0,0 @@ -# -# Auto-generated specs for AVR device at90pwm3 (core avr4, 16-bit SP) -# -# Generated by : ./gcc/config/avr/gen-avr-mmcu-specs.c -# Generated from : ./gcc/config/gcc.c -# ./gcc/config/avr/specs.h -# ./gcc/config/avr/avrlibc.h -# Used by : avr-gcc compiler driver -# Used for : building command options for sub-processes -# -# See -# for a documentation of spec files. - - -# If you intend to use an existing device specs file as a starting point -# for a new device spec file, make sure you are copying from a specs -# file for a device from the same core architecture and SP width. -# See for a description -# of how to use such own spec files. - -*avrlibc_startfile: - crtat90pwm3.o%s - -*avrlibc_devicelib: - %{!nodevicelib:-lat90pwm3} - -*cc1_n_flash: - %{!mn-flash=*:-mn-flash=1} - -*cc1_rmw: - %{mrmw} - -*cc1_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*cc1_absdata: - %{mabsdata} - -*asm_arch: - -mmcu=avr4 - -*asm_relax: - %{mrelax:--mlink-relax} - -*asm_rmw: - %{mrmw} - -*asm_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*link_pmem_wrap: - %{!mno-pmem-wrap-around: --pmem-wrap-around=8k} - -*link_relax: - %{mrelax:--relax} - -*link_arch: - %{mmcu=*:-m%*} - -*link_data_start: - -Tdata 0x800100 - -*link_text_start: - - -*self_spec: - %{!mmcu=avr*: % -# #elif ... -# -# If no device macro is defined, AVR-LibC uses __AVR_DEV_LIB_NAME__ -# as fallback to determine the name of the device header as -# -# "avr/io" + __AVR_DEV_LIB_NAME__ + ".h" -# -# If you provide your own specs file for a device not yet known to -# AVR-LibC, you can now define the hook macro __AVR_DEV_LIB_NAME__ -# as needed so that -# -# #include -# -# will include the desired device header. For ATmega8A the supplement -# to *cpp would read -# -# -D__AVR_DEV_LIB_NAME__=m8a - - -*cpp: - -D__AVR_AT90PWM3__ -D__AVR_DEVICE_NAME__=at90pwm3 - -# End of file diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-at90pwm316 b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-at90pwm316 deleted file mode 100644 index 358d78b..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-at90pwm316 +++ /dev/null @@ -1,99 +0,0 @@ -# -# Auto-generated specs for AVR device at90pwm316 (core avr5, 16-bit SP) -# -# Generated by : ./gcc/config/avr/gen-avr-mmcu-specs.c -# Generated from : ./gcc/config/gcc.c -# ./gcc/config/avr/specs.h -# ./gcc/config/avr/avrlibc.h -# Used by : avr-gcc compiler driver -# Used for : building command options for sub-processes -# -# See -# for a documentation of spec files. - - -# If you intend to use an existing device specs file as a starting point -# for a new device spec file, make sure you are copying from a specs -# file for a device from the same core architecture and SP width. -# See for a description -# of how to use such own spec files. - -*avrlibc_startfile: - crtat90pwm316.o%s - -*avrlibc_devicelib: - %{!nodevicelib:-lat90pwm316} - -*cc1_n_flash: - %{!mn-flash=*:-mn-flash=1} - -*cc1_rmw: - %{mrmw} - -*cc1_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*cc1_absdata: - %{mabsdata} - -*asm_arch: - -mmcu=avr5 - -*asm_relax: - %{mrelax:--mlink-relax} - -*asm_rmw: - %{mrmw} - -*asm_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*link_pmem_wrap: - %{mpmem-wrap-around: --pmem-wrap-around=16k} - -*link_relax: - %{mrelax:--relax} - -*link_arch: - %{mmcu=*:-m%*} - -*link_data_start: - -Tdata 0x800100 - -*link_text_start: - - -*self_spec: - %{!mmcu=avr*: % -# #elif ... -# -# If no device macro is defined, AVR-LibC uses __AVR_DEV_LIB_NAME__ -# as fallback to determine the name of the device header as -# -# "avr/io" + __AVR_DEV_LIB_NAME__ + ".h" -# -# If you provide your own specs file for a device not yet known to -# AVR-LibC, you can now define the hook macro __AVR_DEV_LIB_NAME__ -# as needed so that -# -# #include -# -# will include the desired device header. For ATmega8A the supplement -# to *cpp would read -# -# -D__AVR_DEV_LIB_NAME__=m8a - - -*cpp: - -D__AVR_AT90PWM316__ -D__AVR_DEVICE_NAME__=at90pwm316 - -# End of file diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-at90pwm3b b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-at90pwm3b deleted file mode 100644 index d1335cc..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-at90pwm3b +++ /dev/null @@ -1,99 +0,0 @@ -# -# Auto-generated specs for AVR device at90pwm3b (core avr4, 16-bit SP) -# -# Generated by : ./gcc/config/avr/gen-avr-mmcu-specs.c -# Generated from : ./gcc/config/gcc.c -# ./gcc/config/avr/specs.h -# ./gcc/config/avr/avrlibc.h -# Used by : avr-gcc compiler driver -# Used for : building command options for sub-processes -# -# See -# for a documentation of spec files. - - -# If you intend to use an existing device specs file as a starting point -# for a new device spec file, make sure you are copying from a specs -# file for a device from the same core architecture and SP width. -# See for a description -# of how to use such own spec files. - -*avrlibc_startfile: - crtat90pwm3b.o%s - -*avrlibc_devicelib: - %{!nodevicelib:-lat90pwm3b} - -*cc1_n_flash: - %{!mn-flash=*:-mn-flash=1} - -*cc1_rmw: - %{mrmw} - -*cc1_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*cc1_absdata: - %{mabsdata} - -*asm_arch: - -mmcu=avr4 - -*asm_relax: - %{mrelax:--mlink-relax} - -*asm_rmw: - %{mrmw} - -*asm_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*link_pmem_wrap: - %{!mno-pmem-wrap-around: --pmem-wrap-around=8k} - -*link_relax: - %{mrelax:--relax} - -*link_arch: - %{mmcu=*:-m%*} - -*link_data_start: - -Tdata 0x800100 - -*link_text_start: - - -*self_spec: - %{!mmcu=avr*: % -# #elif ... -# -# If no device macro is defined, AVR-LibC uses __AVR_DEV_LIB_NAME__ -# as fallback to determine the name of the device header as -# -# "avr/io" + __AVR_DEV_LIB_NAME__ + ".h" -# -# If you provide your own specs file for a device not yet known to -# AVR-LibC, you can now define the hook macro __AVR_DEV_LIB_NAME__ -# as needed so that -# -# #include -# -# will include the desired device header. For ATmega8A the supplement -# to *cpp would read -# -# -D__AVR_DEV_LIB_NAME__=m8a - - -*cpp: - -D__AVR_AT90PWM3B__ -D__AVR_DEVICE_NAME__=at90pwm3b - -# End of file diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-at90pwm81 b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-at90pwm81 deleted file mode 100644 index 64e77b0..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-at90pwm81 +++ /dev/null @@ -1,99 +0,0 @@ -# -# Auto-generated specs for AVR device at90pwm81 (core avr4, 16-bit SP) -# -# Generated by : ./gcc/config/avr/gen-avr-mmcu-specs.c -# Generated from : ./gcc/config/gcc.c -# ./gcc/config/avr/specs.h -# ./gcc/config/avr/avrlibc.h -# Used by : avr-gcc compiler driver -# Used for : building command options for sub-processes -# -# See -# for a documentation of spec files. - - -# If you intend to use an existing device specs file as a starting point -# for a new device spec file, make sure you are copying from a specs -# file for a device from the same core architecture and SP width. -# See for a description -# of how to use such own spec files. - -*avrlibc_startfile: - crtat90pwm81.o%s - -*avrlibc_devicelib: - %{!nodevicelib:-lat90pwm81} - -*cc1_n_flash: - %{!mn-flash=*:-mn-flash=1} - -*cc1_rmw: - %{mrmw} - -*cc1_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*cc1_absdata: - %{mabsdata} - -*asm_arch: - -mmcu=avr4 - -*asm_relax: - %{mrelax:--mlink-relax} - -*asm_rmw: - %{mrmw} - -*asm_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*link_pmem_wrap: - %{!mno-pmem-wrap-around: --pmem-wrap-around=8k} - -*link_relax: - %{mrelax:--relax} - -*link_arch: - %{mmcu=*:-m%*} - -*link_data_start: - -Tdata 0x800100 - -*link_text_start: - - -*self_spec: - %{!mmcu=avr*: % -# #elif ... -# -# If no device macro is defined, AVR-LibC uses __AVR_DEV_LIB_NAME__ -# as fallback to determine the name of the device header as -# -# "avr/io" + __AVR_DEV_LIB_NAME__ + ".h" -# -# If you provide your own specs file for a device not yet known to -# AVR-LibC, you can now define the hook macro __AVR_DEV_LIB_NAME__ -# as needed so that -# -# #include -# -# will include the desired device header. For ATmega8A the supplement -# to *cpp would read -# -# -D__AVR_DEV_LIB_NAME__=m8a - - -*cpp: - -D__AVR_AT90PWM81__ -D__AVR_DEVICE_NAME__=at90pwm81 - -# End of file diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-at90s1200 b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-at90s1200 deleted file mode 100644 index cdd04ff..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-at90s1200 +++ /dev/null @@ -1,99 +0,0 @@ -# -# Auto-generated specs for AVR device at90s1200 (core avr1, 16-bit SP) -# -# Generated by : ./gcc/config/avr/gen-avr-mmcu-specs.c -# Generated from : ./gcc/config/gcc.c -# ./gcc/config/avr/specs.h -# ./gcc/config/avr/avrlibc.h -# Used by : avr-gcc compiler driver -# Used for : building command options for sub-processes -# -# See -# for a documentation of spec files. - - -# If you intend to use an existing device specs file as a starting point -# for a new device spec file, make sure you are copying from a specs -# file for a device from the same core architecture and SP width. -# See for a description -# of how to use such own spec files. - -*avrlibc_startfile: - crtat90s1200.o%s - -*avrlibc_devicelib: - %{!nodevicelib:-lat90s1200} - -*cc1_n_flash: - %{!mn-flash=*:-mn-flash=1} - -*cc1_rmw: - %{mrmw} - -*cc1_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*cc1_absdata: - %{mabsdata} - -*asm_arch: - -mmcu=avr1 - -*asm_relax: - %{mrelax:--mlink-relax} - -*asm_rmw: - %{mrmw} - -*asm_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*link_pmem_wrap: - - -*link_relax: - %{mrelax:--relax} - -*link_arch: - %{mmcu=*:-m%*} - -*link_data_start: - - -*link_text_start: - - -*self_spec: - %{!mmcu=avr*: % -# #elif ... -# -# If no device macro is defined, AVR-LibC uses __AVR_DEV_LIB_NAME__ -# as fallback to determine the name of the device header as -# -# "avr/io" + __AVR_DEV_LIB_NAME__ + ".h" -# -# If you provide your own specs file for a device not yet known to -# AVR-LibC, you can now define the hook macro __AVR_DEV_LIB_NAME__ -# as needed so that -# -# #include -# -# will include the desired device header. For ATmega8A the supplement -# to *cpp would read -# -# -D__AVR_DEV_LIB_NAME__=m8a - - -*cpp: - -D__AVR_AT90S1200__ -D__AVR_DEVICE_NAME__=at90s1200 - -# End of file diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-at90s2313 b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-at90s2313 deleted file mode 100644 index f70d6c8..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-at90s2313 +++ /dev/null @@ -1,99 +0,0 @@ -# -# Auto-generated specs for AVR device at90s2313 (core avr2, 8-bit SP) -# -# Generated by : ./gcc/config/avr/gen-avr-mmcu-specs.c -# Generated from : ./gcc/config/gcc.c -# ./gcc/config/avr/specs.h -# ./gcc/config/avr/avrlibc.h -# Used by : avr-gcc compiler driver -# Used for : building command options for sub-processes -# -# See -# for a documentation of spec files. - - -# If you intend to use an existing device specs file as a starting point -# for a new device spec file, make sure you are copying from a specs -# file for a device from the same core architecture and SP width. -# See for a description -# of how to use such own spec files. - -*avrlibc_startfile: - crtat90s2313.o%s - -*avrlibc_devicelib: - %{!nodevicelib:-lat90s2313} - -*cc1_n_flash: - %{!mn-flash=*:-mn-flash=1} - -*cc1_rmw: - %{mrmw} - -*cc1_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*cc1_absdata: - %{mabsdata} - -*asm_arch: - -mmcu=avr2 - -*asm_relax: - %{mrelax:--mlink-relax} - -*asm_rmw: - %{mrmw} - -*asm_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*link_pmem_wrap: - - -*link_relax: - %{mrelax:--relax} - -*link_arch: - %{mmcu=*:-m%*} - -*link_data_start: - - -*link_text_start: - - -*self_spec: - %{!mmcu=avr*: % -# #elif ... -# -# If no device macro is defined, AVR-LibC uses __AVR_DEV_LIB_NAME__ -# as fallback to determine the name of the device header as -# -# "avr/io" + __AVR_DEV_LIB_NAME__ + ".h" -# -# If you provide your own specs file for a device not yet known to -# AVR-LibC, you can now define the hook macro __AVR_DEV_LIB_NAME__ -# as needed so that -# -# #include -# -# will include the desired device header. For ATmega8A the supplement -# to *cpp would read -# -# -D__AVR_DEV_LIB_NAME__=m8a - - -*cpp: - -D__AVR_AT90S2313__ -D__AVR_DEVICE_NAME__=at90s2313 - -# End of file diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-at90s2323 b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-at90s2323 deleted file mode 100644 index f28dc7a..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-at90s2323 +++ /dev/null @@ -1,99 +0,0 @@ -# -# Auto-generated specs for AVR device at90s2323 (core avr2, 8-bit SP) -# -# Generated by : ./gcc/config/avr/gen-avr-mmcu-specs.c -# Generated from : ./gcc/config/gcc.c -# ./gcc/config/avr/specs.h -# ./gcc/config/avr/avrlibc.h -# Used by : avr-gcc compiler driver -# Used for : building command options for sub-processes -# -# See -# for a documentation of spec files. - - -# If you intend to use an existing device specs file as a starting point -# for a new device spec file, make sure you are copying from a specs -# file for a device from the same core architecture and SP width. -# See for a description -# of how to use such own spec files. - -*avrlibc_startfile: - crtat90s2323.o%s - -*avrlibc_devicelib: - %{!nodevicelib:-lat90s2323} - -*cc1_n_flash: - %{!mn-flash=*:-mn-flash=1} - -*cc1_rmw: - %{mrmw} - -*cc1_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*cc1_absdata: - %{mabsdata} - -*asm_arch: - -mmcu=avr2 - -*asm_relax: - %{mrelax:--mlink-relax} - -*asm_rmw: - %{mrmw} - -*asm_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*link_pmem_wrap: - - -*link_relax: - %{mrelax:--relax} - -*link_arch: - %{mmcu=*:-m%*} - -*link_data_start: - - -*link_text_start: - - -*self_spec: - %{!mmcu=avr*: % -# #elif ... -# -# If no device macro is defined, AVR-LibC uses __AVR_DEV_LIB_NAME__ -# as fallback to determine the name of the device header as -# -# "avr/io" + __AVR_DEV_LIB_NAME__ + ".h" -# -# If you provide your own specs file for a device not yet known to -# AVR-LibC, you can now define the hook macro __AVR_DEV_LIB_NAME__ -# as needed so that -# -# #include -# -# will include the desired device header. For ATmega8A the supplement -# to *cpp would read -# -# -D__AVR_DEV_LIB_NAME__=m8a - - -*cpp: - -D__AVR_AT90S2323__ -D__AVR_DEVICE_NAME__=at90s2323 - -# End of file diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-at90s2333 b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-at90s2333 deleted file mode 100644 index f9cfa71..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-at90s2333 +++ /dev/null @@ -1,99 +0,0 @@ -# -# Auto-generated specs for AVR device at90s2333 (core avr2, 8-bit SP) -# -# Generated by : ./gcc/config/avr/gen-avr-mmcu-specs.c -# Generated from : ./gcc/config/gcc.c -# ./gcc/config/avr/specs.h -# ./gcc/config/avr/avrlibc.h -# Used by : avr-gcc compiler driver -# Used for : building command options for sub-processes -# -# See -# for a documentation of spec files. - - -# If you intend to use an existing device specs file as a starting point -# for a new device spec file, make sure you are copying from a specs -# file for a device from the same core architecture and SP width. -# See for a description -# of how to use such own spec files. - -*avrlibc_startfile: - crtat90s2333.o%s - -*avrlibc_devicelib: - %{!nodevicelib:-lat90s2333} - -*cc1_n_flash: - %{!mn-flash=*:-mn-flash=1} - -*cc1_rmw: - %{mrmw} - -*cc1_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*cc1_absdata: - %{mabsdata} - -*asm_arch: - -mmcu=avr2 - -*asm_relax: - %{mrelax:--mlink-relax} - -*asm_rmw: - %{mrmw} - -*asm_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*link_pmem_wrap: - - -*link_relax: - %{mrelax:--relax} - -*link_arch: - %{mmcu=*:-m%*} - -*link_data_start: - - -*link_text_start: - - -*self_spec: - %{!mmcu=avr*: % -# #elif ... -# -# If no device macro is defined, AVR-LibC uses __AVR_DEV_LIB_NAME__ -# as fallback to determine the name of the device header as -# -# "avr/io" + __AVR_DEV_LIB_NAME__ + ".h" -# -# If you provide your own specs file for a device not yet known to -# AVR-LibC, you can now define the hook macro __AVR_DEV_LIB_NAME__ -# as needed so that -# -# #include -# -# will include the desired device header. For ATmega8A the supplement -# to *cpp would read -# -# -D__AVR_DEV_LIB_NAME__=m8a - - -*cpp: - -D__AVR_AT90S2333__ -D__AVR_DEVICE_NAME__=at90s2333 - -# End of file diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-at90s2343 b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-at90s2343 deleted file mode 100644 index 1f32878..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-at90s2343 +++ /dev/null @@ -1,99 +0,0 @@ -# -# Auto-generated specs for AVR device at90s2343 (core avr2, 8-bit SP) -# -# Generated by : ./gcc/config/avr/gen-avr-mmcu-specs.c -# Generated from : ./gcc/config/gcc.c -# ./gcc/config/avr/specs.h -# ./gcc/config/avr/avrlibc.h -# Used by : avr-gcc compiler driver -# Used for : building command options for sub-processes -# -# See -# for a documentation of spec files. - - -# If you intend to use an existing device specs file as a starting point -# for a new device spec file, make sure you are copying from a specs -# file for a device from the same core architecture and SP width. -# See for a description -# of how to use such own spec files. - -*avrlibc_startfile: - crtat90s2343.o%s - -*avrlibc_devicelib: - %{!nodevicelib:-lat90s2343} - -*cc1_n_flash: - %{!mn-flash=*:-mn-flash=1} - -*cc1_rmw: - %{mrmw} - -*cc1_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*cc1_absdata: - %{mabsdata} - -*asm_arch: - -mmcu=avr2 - -*asm_relax: - %{mrelax:--mlink-relax} - -*asm_rmw: - %{mrmw} - -*asm_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*link_pmem_wrap: - - -*link_relax: - %{mrelax:--relax} - -*link_arch: - %{mmcu=*:-m%*} - -*link_data_start: - - -*link_text_start: - - -*self_spec: - %{!mmcu=avr*: % -# #elif ... -# -# If no device macro is defined, AVR-LibC uses __AVR_DEV_LIB_NAME__ -# as fallback to determine the name of the device header as -# -# "avr/io" + __AVR_DEV_LIB_NAME__ + ".h" -# -# If you provide your own specs file for a device not yet known to -# AVR-LibC, you can now define the hook macro __AVR_DEV_LIB_NAME__ -# as needed so that -# -# #include -# -# will include the desired device header. For ATmega8A the supplement -# to *cpp would read -# -# -D__AVR_DEV_LIB_NAME__=m8a - - -*cpp: - -D__AVR_AT90S2343__ -D__AVR_DEVICE_NAME__=at90s2343 - -# End of file diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-at90s4414 b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-at90s4414 deleted file mode 100644 index 8f506e9..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-at90s4414 +++ /dev/null @@ -1,99 +0,0 @@ -# -# Auto-generated specs for AVR device at90s4414 (core avr2, 16-bit SP) -# -# Generated by : ./gcc/config/avr/gen-avr-mmcu-specs.c -# Generated from : ./gcc/config/gcc.c -# ./gcc/config/avr/specs.h -# ./gcc/config/avr/avrlibc.h -# Used by : avr-gcc compiler driver -# Used for : building command options for sub-processes -# -# See -# for a documentation of spec files. - - -# If you intend to use an existing device specs file as a starting point -# for a new device spec file, make sure you are copying from a specs -# file for a device from the same core architecture and SP width. -# See for a description -# of how to use such own spec files. - -*avrlibc_startfile: - crtat90s4414.o%s - -*avrlibc_devicelib: - %{!nodevicelib:-lat90s4414} - -*cc1_n_flash: - %{!mn-flash=*:-mn-flash=1} - -*cc1_rmw: - %{mrmw} - -*cc1_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*cc1_absdata: - %{mabsdata} - -*asm_arch: - -mmcu=avr2 - -*asm_relax: - %{mrelax:--mlink-relax} - -*asm_rmw: - %{mrmw} - -*asm_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*link_pmem_wrap: - - -*link_relax: - %{mrelax:--relax} - -*link_arch: - %{mmcu=*:-m%*} - -*link_data_start: - - -*link_text_start: - - -*self_spec: - %{!mmcu=avr*: % -# #elif ... -# -# If no device macro is defined, AVR-LibC uses __AVR_DEV_LIB_NAME__ -# as fallback to determine the name of the device header as -# -# "avr/io" + __AVR_DEV_LIB_NAME__ + ".h" -# -# If you provide your own specs file for a device not yet known to -# AVR-LibC, you can now define the hook macro __AVR_DEV_LIB_NAME__ -# as needed so that -# -# #include -# -# will include the desired device header. For ATmega8A the supplement -# to *cpp would read -# -# -D__AVR_DEV_LIB_NAME__=m8a - - -*cpp: - -D__AVR_AT90S4414__ -D__AVR_DEVICE_NAME__=at90s4414 - -# End of file diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-at90s4433 b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-at90s4433 deleted file mode 100644 index 577780a..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-at90s4433 +++ /dev/null @@ -1,99 +0,0 @@ -# -# Auto-generated specs for AVR device at90s4433 (core avr2, 8-bit SP) -# -# Generated by : ./gcc/config/avr/gen-avr-mmcu-specs.c -# Generated from : ./gcc/config/gcc.c -# ./gcc/config/avr/specs.h -# ./gcc/config/avr/avrlibc.h -# Used by : avr-gcc compiler driver -# Used for : building command options for sub-processes -# -# See -# for a documentation of spec files. - - -# If you intend to use an existing device specs file as a starting point -# for a new device spec file, make sure you are copying from a specs -# file for a device from the same core architecture and SP width. -# See for a description -# of how to use such own spec files. - -*avrlibc_startfile: - crtat90s4433.o%s - -*avrlibc_devicelib: - %{!nodevicelib:-lat90s4433} - -*cc1_n_flash: - %{!mn-flash=*:-mn-flash=1} - -*cc1_rmw: - %{mrmw} - -*cc1_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*cc1_absdata: - %{mabsdata} - -*asm_arch: - -mmcu=avr2 - -*asm_relax: - %{mrelax:--mlink-relax} - -*asm_rmw: - %{mrmw} - -*asm_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*link_pmem_wrap: - - -*link_relax: - %{mrelax:--relax} - -*link_arch: - %{mmcu=*:-m%*} - -*link_data_start: - - -*link_text_start: - - -*self_spec: - %{!mmcu=avr*: % -# #elif ... -# -# If no device macro is defined, AVR-LibC uses __AVR_DEV_LIB_NAME__ -# as fallback to determine the name of the device header as -# -# "avr/io" + __AVR_DEV_LIB_NAME__ + ".h" -# -# If you provide your own specs file for a device not yet known to -# AVR-LibC, you can now define the hook macro __AVR_DEV_LIB_NAME__ -# as needed so that -# -# #include -# -# will include the desired device header. For ATmega8A the supplement -# to *cpp would read -# -# -D__AVR_DEV_LIB_NAME__=m8a - - -*cpp: - -D__AVR_AT90S4433__ -D__AVR_DEVICE_NAME__=at90s4433 - -# End of file diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-at90s4434 b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-at90s4434 deleted file mode 100644 index 5094670..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-at90s4434 +++ /dev/null @@ -1,99 +0,0 @@ -# -# Auto-generated specs for AVR device at90s4434 (core avr2, 16-bit SP) -# -# Generated by : ./gcc/config/avr/gen-avr-mmcu-specs.c -# Generated from : ./gcc/config/gcc.c -# ./gcc/config/avr/specs.h -# ./gcc/config/avr/avrlibc.h -# Used by : avr-gcc compiler driver -# Used for : building command options for sub-processes -# -# See -# for a documentation of spec files. - - -# If you intend to use an existing device specs file as a starting point -# for a new device spec file, make sure you are copying from a specs -# file for a device from the same core architecture and SP width. -# See for a description -# of how to use such own spec files. - -*avrlibc_startfile: - crtat90s4434.o%s - -*avrlibc_devicelib: - %{!nodevicelib:-lat90s4434} - -*cc1_n_flash: - %{!mn-flash=*:-mn-flash=1} - -*cc1_rmw: - %{mrmw} - -*cc1_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*cc1_absdata: - %{mabsdata} - -*asm_arch: - -mmcu=avr2 - -*asm_relax: - %{mrelax:--mlink-relax} - -*asm_rmw: - %{mrmw} - -*asm_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*link_pmem_wrap: - - -*link_relax: - %{mrelax:--relax} - -*link_arch: - %{mmcu=*:-m%*} - -*link_data_start: - - -*link_text_start: - - -*self_spec: - %{!mmcu=avr*: % -# #elif ... -# -# If no device macro is defined, AVR-LibC uses __AVR_DEV_LIB_NAME__ -# as fallback to determine the name of the device header as -# -# "avr/io" + __AVR_DEV_LIB_NAME__ + ".h" -# -# If you provide your own specs file for a device not yet known to -# AVR-LibC, you can now define the hook macro __AVR_DEV_LIB_NAME__ -# as needed so that -# -# #include -# -# will include the desired device header. For ATmega8A the supplement -# to *cpp would read -# -# -D__AVR_DEV_LIB_NAME__=m8a - - -*cpp: - -D__AVR_AT90S4434__ -D__AVR_DEVICE_NAME__=at90s4434 - -# End of file diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-at90s8515 b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-at90s8515 deleted file mode 100644 index fca7b5f..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-at90s8515 +++ /dev/null @@ -1,99 +0,0 @@ -# -# Auto-generated specs for AVR device at90s8515 (core avr2, 16-bit SP) -# -# Generated by : ./gcc/config/avr/gen-avr-mmcu-specs.c -# Generated from : ./gcc/config/gcc.c -# ./gcc/config/avr/specs.h -# ./gcc/config/avr/avrlibc.h -# Used by : avr-gcc compiler driver -# Used for : building command options for sub-processes -# -# See -# for a documentation of spec files. - - -# If you intend to use an existing device specs file as a starting point -# for a new device spec file, make sure you are copying from a specs -# file for a device from the same core architecture and SP width. -# See for a description -# of how to use such own spec files. - -*avrlibc_startfile: - crtat90s8515.o%s - -*avrlibc_devicelib: - %{!nodevicelib:-lat90s8515} - -*cc1_n_flash: - %{!mn-flash=*:-mn-flash=1} - -*cc1_rmw: - %{mrmw} - -*cc1_errata_skip: - %{!mno-skip-bug: -mskip-bug} - -*cc1_absdata: - %{mabsdata} - -*asm_arch: - -mmcu=avr2 - -*asm_relax: - %{mrelax:--mlink-relax} - -*asm_rmw: - %{mrmw} - -*asm_errata_skip: - %{mno-skip-bug} - -*link_pmem_wrap: - %{!mno-pmem-wrap-around: --pmem-wrap-around=8k} - -*link_relax: - %{mrelax:--relax} - -*link_arch: - %{mmcu=*:-m%*} - -*link_data_start: - - -*link_text_start: - - -*self_spec: - %{!mmcu=avr*: % -# #elif ... -# -# If no device macro is defined, AVR-LibC uses __AVR_DEV_LIB_NAME__ -# as fallback to determine the name of the device header as -# -# "avr/io" + __AVR_DEV_LIB_NAME__ + ".h" -# -# If you provide your own specs file for a device not yet known to -# AVR-LibC, you can now define the hook macro __AVR_DEV_LIB_NAME__ -# as needed so that -# -# #include -# -# will include the desired device header. For ATmega8A the supplement -# to *cpp would read -# -# -D__AVR_DEV_LIB_NAME__=m8a - - -*cpp: - -D__AVR_AT90S8515__ -D__AVR_DEVICE_NAME__=at90s8515 - -# End of file diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-at90s8535 b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-at90s8535 deleted file mode 100644 index 20ba733..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-at90s8535 +++ /dev/null @@ -1,99 +0,0 @@ -# -# Auto-generated specs for AVR device at90s8535 (core avr2, 16-bit SP) -# -# Generated by : ./gcc/config/avr/gen-avr-mmcu-specs.c -# Generated from : ./gcc/config/gcc.c -# ./gcc/config/avr/specs.h -# ./gcc/config/avr/avrlibc.h -# Used by : avr-gcc compiler driver -# Used for : building command options for sub-processes -# -# See -# for a documentation of spec files. - - -# If you intend to use an existing device specs file as a starting point -# for a new device spec file, make sure you are copying from a specs -# file for a device from the same core architecture and SP width. -# See for a description -# of how to use such own spec files. - -*avrlibc_startfile: - crtat90s8535.o%s - -*avrlibc_devicelib: - %{!nodevicelib:-lat90s8535} - -*cc1_n_flash: - %{!mn-flash=*:-mn-flash=1} - -*cc1_rmw: - %{mrmw} - -*cc1_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*cc1_absdata: - %{mabsdata} - -*asm_arch: - -mmcu=avr2 - -*asm_relax: - %{mrelax:--mlink-relax} - -*asm_rmw: - %{mrmw} - -*asm_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*link_pmem_wrap: - %{!mno-pmem-wrap-around: --pmem-wrap-around=8k} - -*link_relax: - %{mrelax:--relax} - -*link_arch: - %{mmcu=*:-m%*} - -*link_data_start: - - -*link_text_start: - - -*self_spec: - %{!mmcu=avr*: % -# #elif ... -# -# If no device macro is defined, AVR-LibC uses __AVR_DEV_LIB_NAME__ -# as fallback to determine the name of the device header as -# -# "avr/io" + __AVR_DEV_LIB_NAME__ + ".h" -# -# If you provide your own specs file for a device not yet known to -# AVR-LibC, you can now define the hook macro __AVR_DEV_LIB_NAME__ -# as needed so that -# -# #include -# -# will include the desired device header. For ATmega8A the supplement -# to *cpp would read -# -# -D__AVR_DEV_LIB_NAME__=m8a - - -*cpp: - -D__AVR_AT90S8535__ -D__AVR_DEVICE_NAME__=at90s8535 - -# End of file diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-at90scr100 b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-at90scr100 deleted file mode 100644 index 3664861..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-at90scr100 +++ /dev/null @@ -1,99 +0,0 @@ -# -# Auto-generated specs for AVR device at90scr100 (core avr5, 16-bit SP) -# -# Generated by : ./gcc/config/avr/gen-avr-mmcu-specs.c -# Generated from : ./gcc/config/gcc.c -# ./gcc/config/avr/specs.h -# ./gcc/config/avr/avrlibc.h -# Used by : avr-gcc compiler driver -# Used for : building command options for sub-processes -# -# See -# for a documentation of spec files. - - -# If you intend to use an existing device specs file as a starting point -# for a new device spec file, make sure you are copying from a specs -# file for a device from the same core architecture and SP width. -# See for a description -# of how to use such own spec files. - -*avrlibc_startfile: - crtat90scr100.o%s - -*avrlibc_devicelib: - %{!nodevicelib:-lat90scr100} - -*cc1_n_flash: - %{!mn-flash=*:-mn-flash=1} - -*cc1_rmw: - %{mrmw} - -*cc1_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*cc1_absdata: - %{mabsdata} - -*asm_arch: - -mmcu=avr5 - -*asm_relax: - %{mrelax:--mlink-relax} - -*asm_rmw: - %{mrmw} - -*asm_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*link_pmem_wrap: - %{mpmem-wrap-around: --pmem-wrap-around=64k} - -*link_relax: - %{mrelax:--relax} - -*link_arch: - %{mmcu=*:-m%*} - -*link_data_start: - -Tdata 0x800100 - -*link_text_start: - - -*self_spec: - %{!mmcu=avr*: % -# #elif ... -# -# If no device macro is defined, AVR-LibC uses __AVR_DEV_LIB_NAME__ -# as fallback to determine the name of the device header as -# -# "avr/io" + __AVR_DEV_LIB_NAME__ + ".h" -# -# If you provide your own specs file for a device not yet known to -# AVR-LibC, you can now define the hook macro __AVR_DEV_LIB_NAME__ -# as needed so that -# -# #include -# -# will include the desired device header. For ATmega8A the supplement -# to *cpp would read -# -# -D__AVR_DEV_LIB_NAME__=m8a - - -*cpp: - -D__AVR_AT90SCR100__ -D__AVR_DEVICE_NAME__=at90scr100 - -# End of file diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-at90usb1286 b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-at90usb1286 deleted file mode 100644 index faecbe2..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-at90usb1286 +++ /dev/null @@ -1,99 +0,0 @@ -# -# Auto-generated specs for AVR device at90usb1286 (core avr51, 16-bit SP) -# -# Generated by : ./gcc/config/avr/gen-avr-mmcu-specs.c -# Generated from : ./gcc/config/gcc.c -# ./gcc/config/avr/specs.h -# ./gcc/config/avr/avrlibc.h -# Used by : avr-gcc compiler driver -# Used for : building command options for sub-processes -# -# See -# for a documentation of spec files. - - -# If you intend to use an existing device specs file as a starting point -# for a new device spec file, make sure you are copying from a specs -# file for a device from the same core architecture and SP width. -# See for a description -# of how to use such own spec files. - -*avrlibc_startfile: - crtat90usb1286.o%s - -*avrlibc_devicelib: - %{!nodevicelib:-lat90usb1286} - -*cc1_n_flash: - %{!mn-flash=*:-mn-flash=2} - -*cc1_rmw: - %{mrmw} - -*cc1_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*cc1_absdata: - %{mabsdata} - -*asm_arch: - -mmcu=avr51 - -*asm_relax: - %{mrelax:--mlink-relax} - -*asm_rmw: - %{mrmw} - -*asm_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*link_pmem_wrap: - - -*link_relax: - %{mrelax:--relax} - -*link_arch: - %{mmcu=*:-m%*} - -*link_data_start: - -Tdata 0x800100 - -*link_text_start: - - -*self_spec: - %{!mmcu=avr*: % -# #elif ... -# -# If no device macro is defined, AVR-LibC uses __AVR_DEV_LIB_NAME__ -# as fallback to determine the name of the device header as -# -# "avr/io" + __AVR_DEV_LIB_NAME__ + ".h" -# -# If you provide your own specs file for a device not yet known to -# AVR-LibC, you can now define the hook macro __AVR_DEV_LIB_NAME__ -# as needed so that -# -# #include -# -# will include the desired device header. For ATmega8A the supplement -# to *cpp would read -# -# -D__AVR_DEV_LIB_NAME__=m8a - - -*cpp: - -D__AVR_AT90USB1286__ -D__AVR_DEVICE_NAME__=at90usb1286 - -# End of file diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-at90usb1287 b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-at90usb1287 deleted file mode 100644 index 7874ebb..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-at90usb1287 +++ /dev/null @@ -1,99 +0,0 @@ -# -# Auto-generated specs for AVR device at90usb1287 (core avr51, 16-bit SP) -# -# Generated by : ./gcc/config/avr/gen-avr-mmcu-specs.c -# Generated from : ./gcc/config/gcc.c -# ./gcc/config/avr/specs.h -# ./gcc/config/avr/avrlibc.h -# Used by : avr-gcc compiler driver -# Used for : building command options for sub-processes -# -# See -# for a documentation of spec files. - - -# If you intend to use an existing device specs file as a starting point -# for a new device spec file, make sure you are copying from a specs -# file for a device from the same core architecture and SP width. -# See for a description -# of how to use such own spec files. - -*avrlibc_startfile: - crtat90usb1287.o%s - -*avrlibc_devicelib: - %{!nodevicelib:-lat90usb1287} - -*cc1_n_flash: - %{!mn-flash=*:-mn-flash=2} - -*cc1_rmw: - %{mrmw} - -*cc1_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*cc1_absdata: - %{mabsdata} - -*asm_arch: - -mmcu=avr51 - -*asm_relax: - %{mrelax:--mlink-relax} - -*asm_rmw: - %{mrmw} - -*asm_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*link_pmem_wrap: - - -*link_relax: - %{mrelax:--relax} - -*link_arch: - %{mmcu=*:-m%*} - -*link_data_start: - -Tdata 0x800100 - -*link_text_start: - - -*self_spec: - %{!mmcu=avr*: % -# #elif ... -# -# If no device macro is defined, AVR-LibC uses __AVR_DEV_LIB_NAME__ -# as fallback to determine the name of the device header as -# -# "avr/io" + __AVR_DEV_LIB_NAME__ + ".h" -# -# If you provide your own specs file for a device not yet known to -# AVR-LibC, you can now define the hook macro __AVR_DEV_LIB_NAME__ -# as needed so that -# -# #include -# -# will include the desired device header. For ATmega8A the supplement -# to *cpp would read -# -# -D__AVR_DEV_LIB_NAME__=m8a - - -*cpp: - -D__AVR_AT90USB1287__ -D__AVR_DEVICE_NAME__=at90usb1287 - -# End of file diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-at90usb162 b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-at90usb162 deleted file mode 100644 index f972ce6..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-at90usb162 +++ /dev/null @@ -1,99 +0,0 @@ -# -# Auto-generated specs for AVR device at90usb162 (core avr35, 16-bit SP) -# -# Generated by : ./gcc/config/avr/gen-avr-mmcu-specs.c -# Generated from : ./gcc/config/gcc.c -# ./gcc/config/avr/specs.h -# ./gcc/config/avr/avrlibc.h -# Used by : avr-gcc compiler driver -# Used for : building command options for sub-processes -# -# See -# for a documentation of spec files. - - -# If you intend to use an existing device specs file as a starting point -# for a new device spec file, make sure you are copying from a specs -# file for a device from the same core architecture and SP width. -# See for a description -# of how to use such own spec files. - -*avrlibc_startfile: - crtat90usb162.o%s - -*avrlibc_devicelib: - %{!nodevicelib:-lat90usb162} - -*cc1_n_flash: - %{!mn-flash=*:-mn-flash=1} - -*cc1_rmw: - %{mrmw} - -*cc1_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*cc1_absdata: - %{mabsdata} - -*asm_arch: - -mmcu=avr35 - -*asm_relax: - %{mrelax:--mlink-relax} - -*asm_rmw: - %{mrmw} - -*asm_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*link_pmem_wrap: - %{mpmem-wrap-around: --pmem-wrap-around=16k} - -*link_relax: - %{mrelax:--relax} - -*link_arch: - %{mmcu=*:-m%*} - -*link_data_start: - -Tdata 0x800100 - -*link_text_start: - - -*self_spec: - %{!mmcu=avr*: % -# #elif ... -# -# If no device macro is defined, AVR-LibC uses __AVR_DEV_LIB_NAME__ -# as fallback to determine the name of the device header as -# -# "avr/io" + __AVR_DEV_LIB_NAME__ + ".h" -# -# If you provide your own specs file for a device not yet known to -# AVR-LibC, you can now define the hook macro __AVR_DEV_LIB_NAME__ -# as needed so that -# -# #include -# -# will include the desired device header. For ATmega8A the supplement -# to *cpp would read -# -# -D__AVR_DEV_LIB_NAME__=m8a - - -*cpp: - -D__AVR_AT90USB162__ -D__AVR_DEVICE_NAME__=at90usb162 - -# End of file diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-at90usb646 b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-at90usb646 deleted file mode 100644 index c50e3ea..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-at90usb646 +++ /dev/null @@ -1,99 +0,0 @@ -# -# Auto-generated specs for AVR device at90usb646 (core avr5, 16-bit SP) -# -# Generated by : ./gcc/config/avr/gen-avr-mmcu-specs.c -# Generated from : ./gcc/config/gcc.c -# ./gcc/config/avr/specs.h -# ./gcc/config/avr/avrlibc.h -# Used by : avr-gcc compiler driver -# Used for : building command options for sub-processes -# -# See -# for a documentation of spec files. - - -# If you intend to use an existing device specs file as a starting point -# for a new device spec file, make sure you are copying from a specs -# file for a device from the same core architecture and SP width. -# See for a description -# of how to use such own spec files. - -*avrlibc_startfile: - crtat90usb646.o%s - -*avrlibc_devicelib: - %{!nodevicelib:-lat90usb646} - -*cc1_n_flash: - %{!mn-flash=*:-mn-flash=1} - -*cc1_rmw: - %{mrmw} - -*cc1_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*cc1_absdata: - %{mabsdata} - -*asm_arch: - -mmcu=avr5 - -*asm_relax: - %{mrelax:--mlink-relax} - -*asm_rmw: - %{mrmw} - -*asm_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*link_pmem_wrap: - %{mpmem-wrap-around: --pmem-wrap-around=64k} - -*link_relax: - %{mrelax:--relax} - -*link_arch: - %{mmcu=*:-m%*} - -*link_data_start: - -Tdata 0x800100 - -*link_text_start: - - -*self_spec: - %{!mmcu=avr*: % -# #elif ... -# -# If no device macro is defined, AVR-LibC uses __AVR_DEV_LIB_NAME__ -# as fallback to determine the name of the device header as -# -# "avr/io" + __AVR_DEV_LIB_NAME__ + ".h" -# -# If you provide your own specs file for a device not yet known to -# AVR-LibC, you can now define the hook macro __AVR_DEV_LIB_NAME__ -# as needed so that -# -# #include -# -# will include the desired device header. For ATmega8A the supplement -# to *cpp would read -# -# -D__AVR_DEV_LIB_NAME__=m8a - - -*cpp: - -D__AVR_AT90USB646__ -D__AVR_DEVICE_NAME__=at90usb646 - -# End of file diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-at90usb647 b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-at90usb647 deleted file mode 100644 index 0a5bf39..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-at90usb647 +++ /dev/null @@ -1,99 +0,0 @@ -# -# Auto-generated specs for AVR device at90usb647 (core avr5, 16-bit SP) -# -# Generated by : ./gcc/config/avr/gen-avr-mmcu-specs.c -# Generated from : ./gcc/config/gcc.c -# ./gcc/config/avr/specs.h -# ./gcc/config/avr/avrlibc.h -# Used by : avr-gcc compiler driver -# Used for : building command options for sub-processes -# -# See -# for a documentation of spec files. - - -# If you intend to use an existing device specs file as a starting point -# for a new device spec file, make sure you are copying from a specs -# file for a device from the same core architecture and SP width. -# See for a description -# of how to use such own spec files. - -*avrlibc_startfile: - crtat90usb647.o%s - -*avrlibc_devicelib: - %{!nodevicelib:-lat90usb647} - -*cc1_n_flash: - %{!mn-flash=*:-mn-flash=1} - -*cc1_rmw: - %{mrmw} - -*cc1_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*cc1_absdata: - %{mabsdata} - -*asm_arch: - -mmcu=avr5 - -*asm_relax: - %{mrelax:--mlink-relax} - -*asm_rmw: - %{mrmw} - -*asm_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*link_pmem_wrap: - %{mpmem-wrap-around: --pmem-wrap-around=64k} - -*link_relax: - %{mrelax:--relax} - -*link_arch: - %{mmcu=*:-m%*} - -*link_data_start: - -Tdata 0x800100 - -*link_text_start: - - -*self_spec: - %{!mmcu=avr*: % -# #elif ... -# -# If no device macro is defined, AVR-LibC uses __AVR_DEV_LIB_NAME__ -# as fallback to determine the name of the device header as -# -# "avr/io" + __AVR_DEV_LIB_NAME__ + ".h" -# -# If you provide your own specs file for a device not yet known to -# AVR-LibC, you can now define the hook macro __AVR_DEV_LIB_NAME__ -# as needed so that -# -# #include -# -# will include the desired device header. For ATmega8A the supplement -# to *cpp would read -# -# -D__AVR_DEV_LIB_NAME__=m8a - - -*cpp: - -D__AVR_AT90USB647__ -D__AVR_DEVICE_NAME__=at90usb647 - -# End of file diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-at90usb82 b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-at90usb82 deleted file mode 100644 index d0dd470..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-at90usb82 +++ /dev/null @@ -1,99 +0,0 @@ -# -# Auto-generated specs for AVR device at90usb82 (core avr35, 16-bit SP) -# -# Generated by : ./gcc/config/avr/gen-avr-mmcu-specs.c -# Generated from : ./gcc/config/gcc.c -# ./gcc/config/avr/specs.h -# ./gcc/config/avr/avrlibc.h -# Used by : avr-gcc compiler driver -# Used for : building command options for sub-processes -# -# See -# for a documentation of spec files. - - -# If you intend to use an existing device specs file as a starting point -# for a new device spec file, make sure you are copying from a specs -# file for a device from the same core architecture and SP width. -# See for a description -# of how to use such own spec files. - -*avrlibc_startfile: - crtat90usb82.o%s - -*avrlibc_devicelib: - %{!nodevicelib:-lat90usb82} - -*cc1_n_flash: - %{!mn-flash=*:-mn-flash=1} - -*cc1_rmw: - %{mrmw} - -*cc1_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*cc1_absdata: - %{mabsdata} - -*asm_arch: - -mmcu=avr35 - -*asm_relax: - %{mrelax:--mlink-relax} - -*asm_rmw: - %{mrmw} - -*asm_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*link_pmem_wrap: - %{!mno-pmem-wrap-around: --pmem-wrap-around=8k} - -*link_relax: - %{mrelax:--relax} - -*link_arch: - %{mmcu=*:-m%*} - -*link_data_start: - -Tdata 0x800100 - -*link_text_start: - - -*self_spec: - %{!mmcu=avr*: % -# #elif ... -# -# If no device macro is defined, AVR-LibC uses __AVR_DEV_LIB_NAME__ -# as fallback to determine the name of the device header as -# -# "avr/io" + __AVR_DEV_LIB_NAME__ + ".h" -# -# If you provide your own specs file for a device not yet known to -# AVR-LibC, you can now define the hook macro __AVR_DEV_LIB_NAME__ -# as needed so that -# -# #include -# -# will include the desired device header. For ATmega8A the supplement -# to *cpp would read -# -# -D__AVR_DEV_LIB_NAME__=m8a - - -*cpp: - -D__AVR_AT90USB82__ -D__AVR_DEVICE_NAME__=at90usb82 - -# End of file diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-at94k b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-at94k deleted file mode 100644 index 1d8fb69..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-at94k +++ /dev/null @@ -1,99 +0,0 @@ -# -# Auto-generated specs for AVR device at94k (core avr5, 16-bit SP) -# -# Generated by : ./gcc/config/avr/gen-avr-mmcu-specs.c -# Generated from : ./gcc/config/gcc.c -# ./gcc/config/avr/specs.h -# ./gcc/config/avr/avrlibc.h -# Used by : avr-gcc compiler driver -# Used for : building command options for sub-processes -# -# See -# for a documentation of spec files. - - -# If you intend to use an existing device specs file as a starting point -# for a new device spec file, make sure you are copying from a specs -# file for a device from the same core architecture and SP width. -# See for a description -# of how to use such own spec files. - -*avrlibc_startfile: - crtat94k.o%s - -*avrlibc_devicelib: - %{!nodevicelib:-lat94k} - -*cc1_n_flash: - %{!mn-flash=*:-mn-flash=1} - -*cc1_rmw: - %{mrmw} - -*cc1_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*cc1_absdata: - %{mabsdata} - -*asm_arch: - -mmcu=avr5 - -*asm_relax: - %{mrelax:--mlink-relax} - -*asm_rmw: - %{mrmw} - -*asm_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*link_pmem_wrap: - %{mpmem-wrap-around: --pmem-wrap-around=32k} - -*link_relax: - %{mrelax:--relax} - -*link_arch: - %{mmcu=*:-m%*} - -*link_data_start: - - -*link_text_start: - - -*self_spec: - %{!mmcu=avr*: % -# #elif ... -# -# If no device macro is defined, AVR-LibC uses __AVR_DEV_LIB_NAME__ -# as fallback to determine the name of the device header as -# -# "avr/io" + __AVR_DEV_LIB_NAME__ + ".h" -# -# If you provide your own specs file for a device not yet known to -# AVR-LibC, you can now define the hook macro __AVR_DEV_LIB_NAME__ -# as needed so that -# -# #include -# -# will include the desired device header. For ATmega8A the supplement -# to *cpp would read -# -# -D__AVR_DEV_LIB_NAME__=m8a - - -*cpp: - -D__AVR_AT94K__ -D__AVR_DEVICE_NAME__=at94k - -# End of file diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-ata5272 b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-ata5272 deleted file mode 100644 index 65b7821..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-ata5272 +++ /dev/null @@ -1,99 +0,0 @@ -# -# Auto-generated specs for AVR device ata5272 (core avr25, 16-bit SP) -# -# Generated by : ./gcc/config/avr/gen-avr-mmcu-specs.c -# Generated from : ./gcc/config/gcc.c -# ./gcc/config/avr/specs.h -# ./gcc/config/avr/avrlibc.h -# Used by : avr-gcc compiler driver -# Used for : building command options for sub-processes -# -# See -# for a documentation of spec files. - - -# If you intend to use an existing device specs file as a starting point -# for a new device spec file, make sure you are copying from a specs -# file for a device from the same core architecture and SP width. -# See for a description -# of how to use such own spec files. - -*avrlibc_startfile: - crtata5272.o%s - -*avrlibc_devicelib: - %{!nodevicelib:-lata5272} - -*cc1_n_flash: - %{!mn-flash=*:-mn-flash=1} - -*cc1_rmw: - %{mrmw} - -*cc1_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*cc1_absdata: - %{mabsdata} - -*asm_arch: - -mmcu=avr25 - -*asm_relax: - %{mrelax:--mlink-relax} - -*asm_rmw: - %{mrmw} - -*asm_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*link_pmem_wrap: - %{!mno-pmem-wrap-around: --pmem-wrap-around=8k} - -*link_relax: - %{mrelax:--relax} - -*link_arch: - %{mmcu=*:-m%*} - -*link_data_start: - -Tdata 0x800100 - -*link_text_start: - - -*self_spec: - %{!mmcu=avr*: % -# #elif ... -# -# If no device macro is defined, AVR-LibC uses __AVR_DEV_LIB_NAME__ -# as fallback to determine the name of the device header as -# -# "avr/io" + __AVR_DEV_LIB_NAME__ + ".h" -# -# If you provide your own specs file for a device not yet known to -# AVR-LibC, you can now define the hook macro __AVR_DEV_LIB_NAME__ -# as needed so that -# -# #include -# -# will include the desired device header. For ATmega8A the supplement -# to *cpp would read -# -# -D__AVR_DEV_LIB_NAME__=m8a - - -*cpp: - -D__AVR_ATA5272__ -D__AVR_DEVICE_NAME__=ata5272 - -# End of file diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-ata5505 b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-ata5505 deleted file mode 100644 index 0c97db3..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-ata5505 +++ /dev/null @@ -1,99 +0,0 @@ -# -# Auto-generated specs for AVR device ata5505 (core avr35, 16-bit SP) -# -# Generated by : ./gcc/config/avr/gen-avr-mmcu-specs.c -# Generated from : ./gcc/config/gcc.c -# ./gcc/config/avr/specs.h -# ./gcc/config/avr/avrlibc.h -# Used by : avr-gcc compiler driver -# Used for : building command options for sub-processes -# -# See -# for a documentation of spec files. - - -# If you intend to use an existing device specs file as a starting point -# for a new device spec file, make sure you are copying from a specs -# file for a device from the same core architecture and SP width. -# See for a description -# of how to use such own spec files. - -*avrlibc_startfile: - crtata5505.o%s - -*avrlibc_devicelib: - %{!nodevicelib:-lata5505} - -*cc1_n_flash: - %{!mn-flash=*:-mn-flash=1} - -*cc1_rmw: - %{mrmw} - -*cc1_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*cc1_absdata: - %{mabsdata} - -*asm_arch: - -mmcu=avr35 - -*asm_relax: - %{mrelax:--mlink-relax} - -*asm_rmw: - %{mrmw} - -*asm_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*link_pmem_wrap: - %{mpmem-wrap-around: --pmem-wrap-around=16k} - -*link_relax: - %{mrelax:--relax} - -*link_arch: - %{mmcu=*:-m%*} - -*link_data_start: - -Tdata 0x800100 - -*link_text_start: - - -*self_spec: - %{!mmcu=avr*: % -# #elif ... -# -# If no device macro is defined, AVR-LibC uses __AVR_DEV_LIB_NAME__ -# as fallback to determine the name of the device header as -# -# "avr/io" + __AVR_DEV_LIB_NAME__ + ".h" -# -# If you provide your own specs file for a device not yet known to -# AVR-LibC, you can now define the hook macro __AVR_DEV_LIB_NAME__ -# as needed so that -# -# #include -# -# will include the desired device header. For ATmega8A the supplement -# to *cpp would read -# -# -D__AVR_DEV_LIB_NAME__=m8a - - -*cpp: - -D__AVR_ATA5505__ -D__AVR_DEVICE_NAME__=ata5505 - -# End of file diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-ata5702m322 b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-ata5702m322 deleted file mode 100644 index f232a70..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-ata5702m322 +++ /dev/null @@ -1,99 +0,0 @@ -# -# Auto-generated specs for AVR device ata5702m322 (core avr5, 16-bit SP) -# -# Generated by : ./gcc/config/avr/gen-avr-mmcu-specs.c -# Generated from : ./gcc/config/gcc.c -# ./gcc/config/avr/specs.h -# ./gcc/config/avr/avrlibc.h -# Used by : avr-gcc compiler driver -# Used for : building command options for sub-processes -# -# See -# for a documentation of spec files. - - -# If you intend to use an existing device specs file as a starting point -# for a new device spec file, make sure you are copying from a specs -# file for a device from the same core architecture and SP width. -# See for a description -# of how to use such own spec files. - -*avrlibc_startfile: - crtata5702m322.o%s - -*avrlibc_devicelib: - %{!nodevicelib:-lata5702m322} - -*cc1_n_flash: - %{!mn-flash=*:-mn-flash=1} - -*cc1_rmw: - %{mrmw} - -*cc1_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*cc1_absdata: - %{mabsdata} - -*asm_arch: - -mmcu=avr5 - -*asm_relax: - %{mrelax:--mlink-relax} - -*asm_rmw: - %{mrmw} - -*asm_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*link_pmem_wrap: - %{mpmem-wrap-around: --pmem-wrap-around=64k} - -*link_relax: - %{mrelax:--relax} - -*link_arch: - %{mmcu=*:-m%*} - -*link_data_start: - -Tdata 0x800200 - -*link_text_start: - - -*self_spec: - %{!mmcu=avr*: % -# #elif ... -# -# If no device macro is defined, AVR-LibC uses __AVR_DEV_LIB_NAME__ -# as fallback to determine the name of the device header as -# -# "avr/io" + __AVR_DEV_LIB_NAME__ + ".h" -# -# If you provide your own specs file for a device not yet known to -# AVR-LibC, you can now define the hook macro __AVR_DEV_LIB_NAME__ -# as needed so that -# -# #include -# -# will include the desired device header. For ATmega8A the supplement -# to *cpp would read -# -# -D__AVR_DEV_LIB_NAME__=m8a - - -*cpp: - -D__AVR_ATA5702M322__ -D__AVR_DEVICE_NAME__=ata5702m322 - -# End of file diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-ata5782 b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-ata5782 deleted file mode 100644 index c0df087..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-ata5782 +++ /dev/null @@ -1,99 +0,0 @@ -# -# Auto-generated specs for AVR device ata5782 (core avr5, 16-bit SP) -# -# Generated by : ./gcc/config/avr/gen-avr-mmcu-specs.c -# Generated from : ./gcc/config/gcc.c -# ./gcc/config/avr/specs.h -# ./gcc/config/avr/avrlibc.h -# Used by : avr-gcc compiler driver -# Used for : building command options for sub-processes -# -# See -# for a documentation of spec files. - - -# If you intend to use an existing device specs file as a starting point -# for a new device spec file, make sure you are copying from a specs -# file for a device from the same core architecture and SP width. -# See for a description -# of how to use such own spec files. - -*avrlibc_startfile: - crtata5782.o%s - -*avrlibc_devicelib: - %{!nodevicelib:-lata5782} - -*cc1_n_flash: - %{!mn-flash=*:-mn-flash=1} - -*cc1_rmw: - %{mrmw} - -*cc1_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*cc1_absdata: - %{mabsdata} - -*asm_arch: - -mmcu=avr5 - -*asm_relax: - %{mrelax:--mlink-relax} - -*asm_rmw: - %{mrmw} - -*asm_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*link_pmem_wrap: - - -*link_relax: - %{mrelax:--relax} - -*link_arch: - %{mmcu=*:-m%*} - -*link_data_start: - -Tdata 0x800200 - -*link_text_start: - -Ttext 0x8000 - -*self_spec: - %{!mmcu=avr*: % -# #elif ... -# -# If no device macro is defined, AVR-LibC uses __AVR_DEV_LIB_NAME__ -# as fallback to determine the name of the device header as -# -# "avr/io" + __AVR_DEV_LIB_NAME__ + ".h" -# -# If you provide your own specs file for a device not yet known to -# AVR-LibC, you can now define the hook macro __AVR_DEV_LIB_NAME__ -# as needed so that -# -# #include -# -# will include the desired device header. For ATmega8A the supplement -# to *cpp would read -# -# -D__AVR_DEV_LIB_NAME__=m8a - - -*cpp: - -D__AVR_ATA5782__ -D__AVR_DEVICE_NAME__=ata5782 - -# End of file diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-ata5790 b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-ata5790 deleted file mode 100644 index ff3e9da..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-ata5790 +++ /dev/null @@ -1,99 +0,0 @@ -# -# Auto-generated specs for AVR device ata5790 (core avr5, 16-bit SP) -# -# Generated by : ./gcc/config/avr/gen-avr-mmcu-specs.c -# Generated from : ./gcc/config/gcc.c -# ./gcc/config/avr/specs.h -# ./gcc/config/avr/avrlibc.h -# Used by : avr-gcc compiler driver -# Used for : building command options for sub-processes -# -# See -# for a documentation of spec files. - - -# If you intend to use an existing device specs file as a starting point -# for a new device spec file, make sure you are copying from a specs -# file for a device from the same core architecture and SP width. -# See for a description -# of how to use such own spec files. - -*avrlibc_startfile: - crtata5790.o%s - -*avrlibc_devicelib: - %{!nodevicelib:-lata5790} - -*cc1_n_flash: - %{!mn-flash=*:-mn-flash=1} - -*cc1_rmw: - %{mrmw} - -*cc1_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*cc1_absdata: - %{mabsdata} - -*asm_arch: - -mmcu=avr5 - -*asm_relax: - %{mrelax:--mlink-relax} - -*asm_rmw: - %{mrmw} - -*asm_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*link_pmem_wrap: - %{mpmem-wrap-around: --pmem-wrap-around=16k} - -*link_relax: - %{mrelax:--relax} - -*link_arch: - %{mmcu=*:-m%*} - -*link_data_start: - -Tdata 0x800100 - -*link_text_start: - - -*self_spec: - %{!mmcu=avr*: % -# #elif ... -# -# If no device macro is defined, AVR-LibC uses __AVR_DEV_LIB_NAME__ -# as fallback to determine the name of the device header as -# -# "avr/io" + __AVR_DEV_LIB_NAME__ + ".h" -# -# If you provide your own specs file for a device not yet known to -# AVR-LibC, you can now define the hook macro __AVR_DEV_LIB_NAME__ -# as needed so that -# -# #include -# -# will include the desired device header. For ATmega8A the supplement -# to *cpp would read -# -# -D__AVR_DEV_LIB_NAME__=m8a - - -*cpp: - -D__AVR_ATA5790__ -D__AVR_DEVICE_NAME__=ata5790 - -# End of file diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-ata5790n b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-ata5790n deleted file mode 100644 index 6953194..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-ata5790n +++ /dev/null @@ -1,99 +0,0 @@ -# -# Auto-generated specs for AVR device ata5790n (core avr5, 16-bit SP) -# -# Generated by : ./gcc/config/avr/gen-avr-mmcu-specs.c -# Generated from : ./gcc/config/gcc.c -# ./gcc/config/avr/specs.h -# ./gcc/config/avr/avrlibc.h -# Used by : avr-gcc compiler driver -# Used for : building command options for sub-processes -# -# See -# for a documentation of spec files. - - -# If you intend to use an existing device specs file as a starting point -# for a new device spec file, make sure you are copying from a specs -# file for a device from the same core architecture and SP width. -# See for a description -# of how to use such own spec files. - -*avrlibc_startfile: - crtata5790n.o%s - -*avrlibc_devicelib: - %{!nodevicelib:-lata5790n} - -*cc1_n_flash: - %{!mn-flash=*:-mn-flash=1} - -*cc1_rmw: - %{mrmw} - -*cc1_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*cc1_absdata: - %{mabsdata} - -*asm_arch: - -mmcu=avr5 - -*asm_relax: - %{mrelax:--mlink-relax} - -*asm_rmw: - %{mrmw} - -*asm_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*link_pmem_wrap: - %{mpmem-wrap-around: --pmem-wrap-around=16k} - -*link_relax: - %{mrelax:--relax} - -*link_arch: - %{mmcu=*:-m%*} - -*link_data_start: - -Tdata 0x800100 - -*link_text_start: - - -*self_spec: - %{!mmcu=avr*: % -# #elif ... -# -# If no device macro is defined, AVR-LibC uses __AVR_DEV_LIB_NAME__ -# as fallback to determine the name of the device header as -# -# "avr/io" + __AVR_DEV_LIB_NAME__ + ".h" -# -# If you provide your own specs file for a device not yet known to -# AVR-LibC, you can now define the hook macro __AVR_DEV_LIB_NAME__ -# as needed so that -# -# #include -# -# will include the desired device header. For ATmega8A the supplement -# to *cpp would read -# -# -D__AVR_DEV_LIB_NAME__=m8a - - -*cpp: - -D__AVR_ATA5790N__ -D__AVR_DEVICE_NAME__=ata5790n - -# End of file diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-ata5791 b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-ata5791 deleted file mode 100644 index 52090c0..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-ata5791 +++ /dev/null @@ -1,99 +0,0 @@ -# -# Auto-generated specs for AVR device ata5791 (core avr5, 16-bit SP) -# -# Generated by : ./gcc/config/avr/gen-avr-mmcu-specs.c -# Generated from : ./gcc/config/gcc.c -# ./gcc/config/avr/specs.h -# ./gcc/config/avr/avrlibc.h -# Used by : avr-gcc compiler driver -# Used for : building command options for sub-processes -# -# See -# for a documentation of spec files. - - -# If you intend to use an existing device specs file as a starting point -# for a new device spec file, make sure you are copying from a specs -# file for a device from the same core architecture and SP width. -# See for a description -# of how to use such own spec files. - -*avrlibc_startfile: - crtata5791.o%s - -*avrlibc_devicelib: - %{!nodevicelib:-lata5791} - -*cc1_n_flash: - %{!mn-flash=*:-mn-flash=1} - -*cc1_rmw: - %{mrmw} - -*cc1_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*cc1_absdata: - %{mabsdata} - -*asm_arch: - -mmcu=avr5 - -*asm_relax: - %{mrelax:--mlink-relax} - -*asm_rmw: - %{mrmw} - -*asm_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*link_pmem_wrap: - %{mpmem-wrap-around: --pmem-wrap-around=16k} - -*link_relax: - %{mrelax:--relax} - -*link_arch: - %{mmcu=*:-m%*} - -*link_data_start: - -Tdata 0x800100 - -*link_text_start: - - -*self_spec: - %{!mmcu=avr*: % -# #elif ... -# -# If no device macro is defined, AVR-LibC uses __AVR_DEV_LIB_NAME__ -# as fallback to determine the name of the device header as -# -# "avr/io" + __AVR_DEV_LIB_NAME__ + ".h" -# -# If you provide your own specs file for a device not yet known to -# AVR-LibC, you can now define the hook macro __AVR_DEV_LIB_NAME__ -# as needed so that -# -# #include -# -# will include the desired device header. For ATmega8A the supplement -# to *cpp would read -# -# -D__AVR_DEV_LIB_NAME__=m8a - - -*cpp: - -D__AVR_ATA5791__ -D__AVR_DEVICE_NAME__=ata5791 - -# End of file diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-ata5795 b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-ata5795 deleted file mode 100644 index ec1548e..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-ata5795 +++ /dev/null @@ -1,99 +0,0 @@ -# -# Auto-generated specs for AVR device ata5795 (core avr5, 16-bit SP) -# -# Generated by : ./gcc/config/avr/gen-avr-mmcu-specs.c -# Generated from : ./gcc/config/gcc.c -# ./gcc/config/avr/specs.h -# ./gcc/config/avr/avrlibc.h -# Used by : avr-gcc compiler driver -# Used for : building command options for sub-processes -# -# See -# for a documentation of spec files. - - -# If you intend to use an existing device specs file as a starting point -# for a new device spec file, make sure you are copying from a specs -# file for a device from the same core architecture and SP width. -# See for a description -# of how to use such own spec files. - -*avrlibc_startfile: - crtata5795.o%s - -*avrlibc_devicelib: - %{!nodevicelib:-lata5795} - -*cc1_n_flash: - %{!mn-flash=*:-mn-flash=1} - -*cc1_rmw: - %{mrmw} - -*cc1_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*cc1_absdata: - %{mabsdata} - -*asm_arch: - -mmcu=avr5 - -*asm_relax: - %{mrelax:--mlink-relax} - -*asm_rmw: - %{mrmw} - -*asm_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*link_pmem_wrap: - %{!mno-pmem-wrap-around: --pmem-wrap-around=8k} - -*link_relax: - %{mrelax:--relax} - -*link_arch: - %{mmcu=*:-m%*} - -*link_data_start: - -Tdata 0x800100 - -*link_text_start: - - -*self_spec: - %{!mmcu=avr*: % -# #elif ... -# -# If no device macro is defined, AVR-LibC uses __AVR_DEV_LIB_NAME__ -# as fallback to determine the name of the device header as -# -# "avr/io" + __AVR_DEV_LIB_NAME__ + ".h" -# -# If you provide your own specs file for a device not yet known to -# AVR-LibC, you can now define the hook macro __AVR_DEV_LIB_NAME__ -# as needed so that -# -# #include -# -# will include the desired device header. For ATmega8A the supplement -# to *cpp would read -# -# -D__AVR_DEV_LIB_NAME__=m8a - - -*cpp: - -D__AVR_ATA5795__ -D__AVR_DEVICE_NAME__=ata5795 - -# End of file diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-ata5831 b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-ata5831 deleted file mode 100644 index 2c35770..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-ata5831 +++ /dev/null @@ -1,99 +0,0 @@ -# -# Auto-generated specs for AVR device ata5831 (core avr5, 16-bit SP) -# -# Generated by : ./gcc/config/avr/gen-avr-mmcu-specs.c -# Generated from : ./gcc/config/gcc.c -# ./gcc/config/avr/specs.h -# ./gcc/config/avr/avrlibc.h -# Used by : avr-gcc compiler driver -# Used for : building command options for sub-processes -# -# See -# for a documentation of spec files. - - -# If you intend to use an existing device specs file as a starting point -# for a new device spec file, make sure you are copying from a specs -# file for a device from the same core architecture and SP width. -# See for a description -# of how to use such own spec files. - -*avrlibc_startfile: - crtata5831.o%s - -*avrlibc_devicelib: - %{!nodevicelib:-lata5831} - -*cc1_n_flash: - %{!mn-flash=*:-mn-flash=1} - -*cc1_rmw: - %{mrmw} - -*cc1_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*cc1_absdata: - %{mabsdata} - -*asm_arch: - -mmcu=avr5 - -*asm_relax: - %{mrelax:--mlink-relax} - -*asm_rmw: - %{mrmw} - -*asm_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*link_pmem_wrap: - - -*link_relax: - %{mrelax:--relax} - -*link_arch: - %{mmcu=*:-m%*} - -*link_data_start: - -Tdata 0x800200 - -*link_text_start: - -Ttext 0x8000 - -*self_spec: - %{!mmcu=avr*: % -# #elif ... -# -# If no device macro is defined, AVR-LibC uses __AVR_DEV_LIB_NAME__ -# as fallback to determine the name of the device header as -# -# "avr/io" + __AVR_DEV_LIB_NAME__ + ".h" -# -# If you provide your own specs file for a device not yet known to -# AVR-LibC, you can now define the hook macro __AVR_DEV_LIB_NAME__ -# as needed so that -# -# #include -# -# will include the desired device header. For ATmega8A the supplement -# to *cpp would read -# -# -D__AVR_DEV_LIB_NAME__=m8a - - -*cpp: - -D__AVR_ATA5831__ -D__AVR_DEVICE_NAME__=ata5831 - -# End of file diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-ata6285 b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-ata6285 deleted file mode 100644 index ed43181..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-ata6285 +++ /dev/null @@ -1,99 +0,0 @@ -# -# Auto-generated specs for AVR device ata6285 (core avr4, 16-bit SP) -# -# Generated by : ./gcc/config/avr/gen-avr-mmcu-specs.c -# Generated from : ./gcc/config/gcc.c -# ./gcc/config/avr/specs.h -# ./gcc/config/avr/avrlibc.h -# Used by : avr-gcc compiler driver -# Used for : building command options for sub-processes -# -# See -# for a documentation of spec files. - - -# If you intend to use an existing device specs file as a starting point -# for a new device spec file, make sure you are copying from a specs -# file for a device from the same core architecture and SP width. -# See for a description -# of how to use such own spec files. - -*avrlibc_startfile: - crtata6285.o%s - -*avrlibc_devicelib: - %{!nodevicelib:-lata6285} - -*cc1_n_flash: - %{!mn-flash=*:-mn-flash=1} - -*cc1_rmw: - %{mrmw} - -*cc1_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*cc1_absdata: - %{mabsdata} - -*asm_arch: - -mmcu=avr4 - -*asm_relax: - %{mrelax:--mlink-relax} - -*asm_rmw: - %{mrmw} - -*asm_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*link_pmem_wrap: - %{!mno-pmem-wrap-around: --pmem-wrap-around=8k} - -*link_relax: - %{mrelax:--relax} - -*link_arch: - %{mmcu=*:-m%*} - -*link_data_start: - -Tdata 0x800100 - -*link_text_start: - - -*self_spec: - %{!mmcu=avr*: % -# #elif ... -# -# If no device macro is defined, AVR-LibC uses __AVR_DEV_LIB_NAME__ -# as fallback to determine the name of the device header as -# -# "avr/io" + __AVR_DEV_LIB_NAME__ + ".h" -# -# If you provide your own specs file for a device not yet known to -# AVR-LibC, you can now define the hook macro __AVR_DEV_LIB_NAME__ -# as needed so that -# -# #include -# -# will include the desired device header. For ATmega8A the supplement -# to *cpp would read -# -# -D__AVR_DEV_LIB_NAME__=m8a - - -*cpp: - -D__AVR_ATA6285__ -D__AVR_DEVICE_NAME__=ata6285 - -# End of file diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-ata6286 b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-ata6286 deleted file mode 100644 index bd42ed9..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-ata6286 +++ /dev/null @@ -1,99 +0,0 @@ -# -# Auto-generated specs for AVR device ata6286 (core avr4, 16-bit SP) -# -# Generated by : ./gcc/config/avr/gen-avr-mmcu-specs.c -# Generated from : ./gcc/config/gcc.c -# ./gcc/config/avr/specs.h -# ./gcc/config/avr/avrlibc.h -# Used by : avr-gcc compiler driver -# Used for : building command options for sub-processes -# -# See -# for a documentation of spec files. - - -# If you intend to use an existing device specs file as a starting point -# for a new device spec file, make sure you are copying from a specs -# file for a device from the same core architecture and SP width. -# See for a description -# of how to use such own spec files. - -*avrlibc_startfile: - crtata6286.o%s - -*avrlibc_devicelib: - %{!nodevicelib:-lata6286} - -*cc1_n_flash: - %{!mn-flash=*:-mn-flash=1} - -*cc1_rmw: - %{mrmw} - -*cc1_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*cc1_absdata: - %{mabsdata} - -*asm_arch: - -mmcu=avr4 - -*asm_relax: - %{mrelax:--mlink-relax} - -*asm_rmw: - %{mrmw} - -*asm_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*link_pmem_wrap: - %{!mno-pmem-wrap-around: --pmem-wrap-around=8k} - -*link_relax: - %{mrelax:--relax} - -*link_arch: - %{mmcu=*:-m%*} - -*link_data_start: - -Tdata 0x800100 - -*link_text_start: - - -*self_spec: - %{!mmcu=avr*: % -# #elif ... -# -# If no device macro is defined, AVR-LibC uses __AVR_DEV_LIB_NAME__ -# as fallback to determine the name of the device header as -# -# "avr/io" + __AVR_DEV_LIB_NAME__ + ".h" -# -# If you provide your own specs file for a device not yet known to -# AVR-LibC, you can now define the hook macro __AVR_DEV_LIB_NAME__ -# as needed so that -# -# #include -# -# will include the desired device header. For ATmega8A the supplement -# to *cpp would read -# -# -D__AVR_DEV_LIB_NAME__=m8a - - -*cpp: - -D__AVR_ATA6286__ -D__AVR_DEVICE_NAME__=ata6286 - -# End of file diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-ata6289 b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-ata6289 deleted file mode 100644 index 27707d9..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-ata6289 +++ /dev/null @@ -1,99 +0,0 @@ -# -# Auto-generated specs for AVR device ata6289 (core avr4, 16-bit SP) -# -# Generated by : ./gcc/config/avr/gen-avr-mmcu-specs.c -# Generated from : ./gcc/config/gcc.c -# ./gcc/config/avr/specs.h -# ./gcc/config/avr/avrlibc.h -# Used by : avr-gcc compiler driver -# Used for : building command options for sub-processes -# -# See -# for a documentation of spec files. - - -# If you intend to use an existing device specs file as a starting point -# for a new device spec file, make sure you are copying from a specs -# file for a device from the same core architecture and SP width. -# See for a description -# of how to use such own spec files. - -*avrlibc_startfile: - crtata6289.o%s - -*avrlibc_devicelib: - %{!nodevicelib:-lata6289} - -*cc1_n_flash: - %{!mn-flash=*:-mn-flash=1} - -*cc1_rmw: - %{mrmw} - -*cc1_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*cc1_absdata: - %{mabsdata} - -*asm_arch: - -mmcu=avr4 - -*asm_relax: - %{mrelax:--mlink-relax} - -*asm_rmw: - %{mrmw} - -*asm_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*link_pmem_wrap: - %{!mno-pmem-wrap-around: --pmem-wrap-around=8k} - -*link_relax: - %{mrelax:--relax} - -*link_arch: - %{mmcu=*:-m%*} - -*link_data_start: - -Tdata 0x800100 - -*link_text_start: - - -*self_spec: - %{!mmcu=avr*: % -# #elif ... -# -# If no device macro is defined, AVR-LibC uses __AVR_DEV_LIB_NAME__ -# as fallback to determine the name of the device header as -# -# "avr/io" + __AVR_DEV_LIB_NAME__ + ".h" -# -# If you provide your own specs file for a device not yet known to -# AVR-LibC, you can now define the hook macro __AVR_DEV_LIB_NAME__ -# as needed so that -# -# #include -# -# will include the desired device header. For ATmega8A the supplement -# to *cpp would read -# -# -D__AVR_DEV_LIB_NAME__=m8a - - -*cpp: - -D__AVR_ATA6289__ -D__AVR_DEVICE_NAME__=ata6289 - -# End of file diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-ata6612c b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-ata6612c deleted file mode 100644 index 73e0418..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-ata6612c +++ /dev/null @@ -1,99 +0,0 @@ -# -# Auto-generated specs for AVR device ata6612c (core avr4, 16-bit SP) -# -# Generated by : ./gcc/config/avr/gen-avr-mmcu-specs.c -# Generated from : ./gcc/config/gcc.c -# ./gcc/config/avr/specs.h -# ./gcc/config/avr/avrlibc.h -# Used by : avr-gcc compiler driver -# Used for : building command options for sub-processes -# -# See -# for a documentation of spec files. - - -# If you intend to use an existing device specs file as a starting point -# for a new device spec file, make sure you are copying from a specs -# file for a device from the same core architecture and SP width. -# See for a description -# of how to use such own spec files. - -*avrlibc_startfile: - crtata6612c.o%s - -*avrlibc_devicelib: - %{!nodevicelib:-lata6612c} - -*cc1_n_flash: - %{!mn-flash=*:-mn-flash=1} - -*cc1_rmw: - %{mrmw} - -*cc1_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*cc1_absdata: - %{mabsdata} - -*asm_arch: - -mmcu=avr4 - -*asm_relax: - %{mrelax:--mlink-relax} - -*asm_rmw: - %{mrmw} - -*asm_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*link_pmem_wrap: - %{!mno-pmem-wrap-around: --pmem-wrap-around=8k} - -*link_relax: - %{mrelax:--relax} - -*link_arch: - %{mmcu=*:-m%*} - -*link_data_start: - -Tdata 0x800100 - -*link_text_start: - - -*self_spec: - %{!mmcu=avr*: % -# #elif ... -# -# If no device macro is defined, AVR-LibC uses __AVR_DEV_LIB_NAME__ -# as fallback to determine the name of the device header as -# -# "avr/io" + __AVR_DEV_LIB_NAME__ + ".h" -# -# If you provide your own specs file for a device not yet known to -# AVR-LibC, you can now define the hook macro __AVR_DEV_LIB_NAME__ -# as needed so that -# -# #include -# -# will include the desired device header. For ATmega8A the supplement -# to *cpp would read -# -# -D__AVR_DEV_LIB_NAME__=m8a - - -*cpp: - -D__AVR_ATA6612C__ -D__AVR_DEVICE_NAME__=ata6612c - -# End of file diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-ata6613c b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-ata6613c deleted file mode 100644 index da06746..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-ata6613c +++ /dev/null @@ -1,99 +0,0 @@ -# -# Auto-generated specs for AVR device ata6613c (core avr5, 16-bit SP) -# -# Generated by : ./gcc/config/avr/gen-avr-mmcu-specs.c -# Generated from : ./gcc/config/gcc.c -# ./gcc/config/avr/specs.h -# ./gcc/config/avr/avrlibc.h -# Used by : avr-gcc compiler driver -# Used for : building command options for sub-processes -# -# See -# for a documentation of spec files. - - -# If you intend to use an existing device specs file as a starting point -# for a new device spec file, make sure you are copying from a specs -# file for a device from the same core architecture and SP width. -# See for a description -# of how to use such own spec files. - -*avrlibc_startfile: - crtata6613c.o%s - -*avrlibc_devicelib: - %{!nodevicelib:-lata6613c} - -*cc1_n_flash: - %{!mn-flash=*:-mn-flash=1} - -*cc1_rmw: - %{mrmw} - -*cc1_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*cc1_absdata: - %{mabsdata} - -*asm_arch: - -mmcu=avr5 - -*asm_relax: - %{mrelax:--mlink-relax} - -*asm_rmw: - %{mrmw} - -*asm_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*link_pmem_wrap: - %{mpmem-wrap-around: --pmem-wrap-around=16k} - -*link_relax: - %{mrelax:--relax} - -*link_arch: - %{mmcu=*:-m%*} - -*link_data_start: - -Tdata 0x800100 - -*link_text_start: - - -*self_spec: - %{!mmcu=avr*: % -# #elif ... -# -# If no device macro is defined, AVR-LibC uses __AVR_DEV_LIB_NAME__ -# as fallback to determine the name of the device header as -# -# "avr/io" + __AVR_DEV_LIB_NAME__ + ".h" -# -# If you provide your own specs file for a device not yet known to -# AVR-LibC, you can now define the hook macro __AVR_DEV_LIB_NAME__ -# as needed so that -# -# #include -# -# will include the desired device header. For ATmega8A the supplement -# to *cpp would read -# -# -D__AVR_DEV_LIB_NAME__=m8a - - -*cpp: - -D__AVR_ATA6613C__ -D__AVR_DEVICE_NAME__=ata6613c - -# End of file diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-ata6614q b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-ata6614q deleted file mode 100644 index a7e0a03..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-ata6614q +++ /dev/null @@ -1,99 +0,0 @@ -# -# Auto-generated specs for AVR device ata6614q (core avr5, 16-bit SP) -# -# Generated by : ./gcc/config/avr/gen-avr-mmcu-specs.c -# Generated from : ./gcc/config/gcc.c -# ./gcc/config/avr/specs.h -# ./gcc/config/avr/avrlibc.h -# Used by : avr-gcc compiler driver -# Used for : building command options for sub-processes -# -# See -# for a documentation of spec files. - - -# If you intend to use an existing device specs file as a starting point -# for a new device spec file, make sure you are copying from a specs -# file for a device from the same core architecture and SP width. -# See for a description -# of how to use such own spec files. - -*avrlibc_startfile: - crtata6614q.o%s - -*avrlibc_devicelib: - %{!nodevicelib:-lata6614q} - -*cc1_n_flash: - %{!mn-flash=*:-mn-flash=1} - -*cc1_rmw: - %{mrmw} - -*cc1_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*cc1_absdata: - %{mabsdata} - -*asm_arch: - -mmcu=avr5 - -*asm_relax: - %{mrelax:--mlink-relax} - -*asm_rmw: - %{mrmw} - -*asm_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*link_pmem_wrap: - %{mpmem-wrap-around: --pmem-wrap-around=32k} - -*link_relax: - %{mrelax:--relax} - -*link_arch: - %{mmcu=*:-m%*} - -*link_data_start: - -Tdata 0x800100 - -*link_text_start: - - -*self_spec: - %{!mmcu=avr*: % -# #elif ... -# -# If no device macro is defined, AVR-LibC uses __AVR_DEV_LIB_NAME__ -# as fallback to determine the name of the device header as -# -# "avr/io" + __AVR_DEV_LIB_NAME__ + ".h" -# -# If you provide your own specs file for a device not yet known to -# AVR-LibC, you can now define the hook macro __AVR_DEV_LIB_NAME__ -# as needed so that -# -# #include -# -# will include the desired device header. For ATmega8A the supplement -# to *cpp would read -# -# -D__AVR_DEV_LIB_NAME__=m8a - - -*cpp: - -D__AVR_ATA6614Q__ -D__AVR_DEVICE_NAME__=ata6614q - -# End of file diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-ata6616c b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-ata6616c deleted file mode 100644 index 7da868e..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-ata6616c +++ /dev/null @@ -1,99 +0,0 @@ -# -# Auto-generated specs for AVR device ata6616c (core avr25, 16-bit SP) -# -# Generated by : ./gcc/config/avr/gen-avr-mmcu-specs.c -# Generated from : ./gcc/config/gcc.c -# ./gcc/config/avr/specs.h -# ./gcc/config/avr/avrlibc.h -# Used by : avr-gcc compiler driver -# Used for : building command options for sub-processes -# -# See -# for a documentation of spec files. - - -# If you intend to use an existing device specs file as a starting point -# for a new device spec file, make sure you are copying from a specs -# file for a device from the same core architecture and SP width. -# See for a description -# of how to use such own spec files. - -*avrlibc_startfile: - crtata6616c.o%s - -*avrlibc_devicelib: - %{!nodevicelib:-lata6616c} - -*cc1_n_flash: - %{!mn-flash=*:-mn-flash=1} - -*cc1_rmw: - %{mrmw} - -*cc1_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*cc1_absdata: - %{mabsdata} - -*asm_arch: - -mmcu=avr25 - -*asm_relax: - %{mrelax:--mlink-relax} - -*asm_rmw: - %{mrmw} - -*asm_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*link_pmem_wrap: - %{!mno-pmem-wrap-around: --pmem-wrap-around=8k} - -*link_relax: - %{mrelax:--relax} - -*link_arch: - %{mmcu=*:-m%*} - -*link_data_start: - -Tdata 0x800100 - -*link_text_start: - - -*self_spec: - %{!mmcu=avr*: % -# #elif ... -# -# If no device macro is defined, AVR-LibC uses __AVR_DEV_LIB_NAME__ -# as fallback to determine the name of the device header as -# -# "avr/io" + __AVR_DEV_LIB_NAME__ + ".h" -# -# If you provide your own specs file for a device not yet known to -# AVR-LibC, you can now define the hook macro __AVR_DEV_LIB_NAME__ -# as needed so that -# -# #include -# -# will include the desired device header. For ATmega8A the supplement -# to *cpp would read -# -# -D__AVR_DEV_LIB_NAME__=m8a - - -*cpp: - -D__AVR_ATA6616C__ -D__AVR_DEVICE_NAME__=ata6616c - -# End of file diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-ata6617c b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-ata6617c deleted file mode 100644 index c37daae..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-ata6617c +++ /dev/null @@ -1,99 +0,0 @@ -# -# Auto-generated specs for AVR device ata6617c (core avr35, 16-bit SP) -# -# Generated by : ./gcc/config/avr/gen-avr-mmcu-specs.c -# Generated from : ./gcc/config/gcc.c -# ./gcc/config/avr/specs.h -# ./gcc/config/avr/avrlibc.h -# Used by : avr-gcc compiler driver -# Used for : building command options for sub-processes -# -# See -# for a documentation of spec files. - - -# If you intend to use an existing device specs file as a starting point -# for a new device spec file, make sure you are copying from a specs -# file for a device from the same core architecture and SP width. -# See for a description -# of how to use such own spec files. - -*avrlibc_startfile: - crtata6617c.o%s - -*avrlibc_devicelib: - %{!nodevicelib:-lata6617c} - -*cc1_n_flash: - %{!mn-flash=*:-mn-flash=1} - -*cc1_rmw: - %{mrmw} - -*cc1_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*cc1_absdata: - %{mabsdata} - -*asm_arch: - -mmcu=avr35 - -*asm_relax: - %{mrelax:--mlink-relax} - -*asm_rmw: - %{mrmw} - -*asm_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*link_pmem_wrap: - %{mpmem-wrap-around: --pmem-wrap-around=16k} - -*link_relax: - %{mrelax:--relax} - -*link_arch: - %{mmcu=*:-m%*} - -*link_data_start: - -Tdata 0x800100 - -*link_text_start: - - -*self_spec: - %{!mmcu=avr*: % -# #elif ... -# -# If no device macro is defined, AVR-LibC uses __AVR_DEV_LIB_NAME__ -# as fallback to determine the name of the device header as -# -# "avr/io" + __AVR_DEV_LIB_NAME__ + ".h" -# -# If you provide your own specs file for a device not yet known to -# AVR-LibC, you can now define the hook macro __AVR_DEV_LIB_NAME__ -# as needed so that -# -# #include -# -# will include the desired device header. For ATmega8A the supplement -# to *cpp would read -# -# -D__AVR_DEV_LIB_NAME__=m8a - - -*cpp: - -D__AVR_ATA6617C__ -D__AVR_DEVICE_NAME__=ata6617c - -# End of file diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-ata664251 b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-ata664251 deleted file mode 100644 index 2cbfc47..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-ata664251 +++ /dev/null @@ -1,99 +0,0 @@ -# -# Auto-generated specs for AVR device ata664251 (core avr35, 16-bit SP) -# -# Generated by : ./gcc/config/avr/gen-avr-mmcu-specs.c -# Generated from : ./gcc/config/gcc.c -# ./gcc/config/avr/specs.h -# ./gcc/config/avr/avrlibc.h -# Used by : avr-gcc compiler driver -# Used for : building command options for sub-processes -# -# See -# for a documentation of spec files. - - -# If you intend to use an existing device specs file as a starting point -# for a new device spec file, make sure you are copying from a specs -# file for a device from the same core architecture and SP width. -# See for a description -# of how to use such own spec files. - -*avrlibc_startfile: - crtata664251.o%s - -*avrlibc_devicelib: - %{!nodevicelib:-lata664251} - -*cc1_n_flash: - %{!mn-flash=*:-mn-flash=1} - -*cc1_rmw: - %{mrmw} - -*cc1_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*cc1_absdata: - %{mabsdata} - -*asm_arch: - -mmcu=avr35 - -*asm_relax: - %{mrelax:--mlink-relax} - -*asm_rmw: - %{mrmw} - -*asm_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*link_pmem_wrap: - %{mpmem-wrap-around: --pmem-wrap-around=16k} - -*link_relax: - %{mrelax:--relax} - -*link_arch: - %{mmcu=*:-m%*} - -*link_data_start: - -Tdata 0x800100 - -*link_text_start: - - -*self_spec: - %{!mmcu=avr*: % -# #elif ... -# -# If no device macro is defined, AVR-LibC uses __AVR_DEV_LIB_NAME__ -# as fallback to determine the name of the device header as -# -# "avr/io" + __AVR_DEV_LIB_NAME__ + ".h" -# -# If you provide your own specs file for a device not yet known to -# AVR-LibC, you can now define the hook macro __AVR_DEV_LIB_NAME__ -# as needed so that -# -# #include -# -# will include the desired device header. For ATmega8A the supplement -# to *cpp would read -# -# -D__AVR_DEV_LIB_NAME__=m8a - - -*cpp: - -D__AVR_ATA664251__ -D__AVR_DEVICE_NAME__=ata664251 - -# End of file diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-ata8210 b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-ata8210 deleted file mode 100644 index d783a79..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-ata8210 +++ /dev/null @@ -1,99 +0,0 @@ -# -# Auto-generated specs for AVR device ata8210 (core avr5, 16-bit SP) -# -# Generated by : ./gcc/config/avr/gen-avr-mmcu-specs.c -# Generated from : ./gcc/config/gcc.c -# ./gcc/config/avr/specs.h -# ./gcc/config/avr/avrlibc.h -# Used by : avr-gcc compiler driver -# Used for : building command options for sub-processes -# -# See -# for a documentation of spec files. - - -# If you intend to use an existing device specs file as a starting point -# for a new device spec file, make sure you are copying from a specs -# file for a device from the same core architecture and SP width. -# See for a description -# of how to use such own spec files. - -*avrlibc_startfile: - crtata8210.o%s - -*avrlibc_devicelib: - %{!nodevicelib:-lata8210} - -*cc1_n_flash: - %{!mn-flash=*:-mn-flash=1} - -*cc1_rmw: - %{mrmw} - -*cc1_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*cc1_absdata: - %{mabsdata} - -*asm_arch: - -mmcu=avr5 - -*asm_relax: - %{mrelax:--mlink-relax} - -*asm_rmw: - %{mrmw} - -*asm_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*link_pmem_wrap: - - -*link_relax: - %{mrelax:--relax} - -*link_arch: - %{mmcu=*:-m%*} - -*link_data_start: - -Tdata 0x800200 - -*link_text_start: - -Ttext 0x8000 - -*self_spec: - %{!mmcu=avr*: % -# #elif ... -# -# If no device macro is defined, AVR-LibC uses __AVR_DEV_LIB_NAME__ -# as fallback to determine the name of the device header as -# -# "avr/io" + __AVR_DEV_LIB_NAME__ + ".h" -# -# If you provide your own specs file for a device not yet known to -# AVR-LibC, you can now define the hook macro __AVR_DEV_LIB_NAME__ -# as needed so that -# -# #include -# -# will include the desired device header. For ATmega8A the supplement -# to *cpp would read -# -# -D__AVR_DEV_LIB_NAME__=m8a - - -*cpp: - -D__AVR_ATA8210__ -D__AVR_DEVICE_NAME__=ata8210 - -# End of file diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-ata8510 b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-ata8510 deleted file mode 100644 index 7446d42..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-ata8510 +++ /dev/null @@ -1,99 +0,0 @@ -# -# Auto-generated specs for AVR device ata8510 (core avr5, 16-bit SP) -# -# Generated by : ./gcc/config/avr/gen-avr-mmcu-specs.c -# Generated from : ./gcc/config/gcc.c -# ./gcc/config/avr/specs.h -# ./gcc/config/avr/avrlibc.h -# Used by : avr-gcc compiler driver -# Used for : building command options for sub-processes -# -# See -# for a documentation of spec files. - - -# If you intend to use an existing device specs file as a starting point -# for a new device spec file, make sure you are copying from a specs -# file for a device from the same core architecture and SP width. -# See for a description -# of how to use such own spec files. - -*avrlibc_startfile: - crtata8510.o%s - -*avrlibc_devicelib: - %{!nodevicelib:-lata8510} - -*cc1_n_flash: - %{!mn-flash=*:-mn-flash=1} - -*cc1_rmw: - %{mrmw} - -*cc1_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*cc1_absdata: - %{mabsdata} - -*asm_arch: - -mmcu=avr5 - -*asm_relax: - %{mrelax:--mlink-relax} - -*asm_rmw: - %{mrmw} - -*asm_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*link_pmem_wrap: - - -*link_relax: - %{mrelax:--relax} - -*link_arch: - %{mmcu=*:-m%*} - -*link_data_start: - -Tdata 0x800200 - -*link_text_start: - -Ttext 0x8000 - -*self_spec: - %{!mmcu=avr*: % -# #elif ... -# -# If no device macro is defined, AVR-LibC uses __AVR_DEV_LIB_NAME__ -# as fallback to determine the name of the device header as -# -# "avr/io" + __AVR_DEV_LIB_NAME__ + ".h" -# -# If you provide your own specs file for a device not yet known to -# AVR-LibC, you can now define the hook macro __AVR_DEV_LIB_NAME__ -# as needed so that -# -# #include -# -# will include the desired device header. For ATmega8A the supplement -# to *cpp would read -# -# -D__AVR_DEV_LIB_NAME__=m8a - - -*cpp: - -D__AVR_ATA8510__ -D__AVR_DEVICE_NAME__=ata8510 - -# End of file diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega103 b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega103 deleted file mode 100644 index 31002cc..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega103 +++ /dev/null @@ -1,99 +0,0 @@ -# -# Auto-generated specs for AVR device atmega103 (core avr31, 16-bit SP) -# -# Generated by : ./gcc/config/avr/gen-avr-mmcu-specs.c -# Generated from : ./gcc/config/gcc.c -# ./gcc/config/avr/specs.h -# ./gcc/config/avr/avrlibc.h -# Used by : avr-gcc compiler driver -# Used for : building command options for sub-processes -# -# See -# for a documentation of spec files. - - -# If you intend to use an existing device specs file as a starting point -# for a new device spec file, make sure you are copying from a specs -# file for a device from the same core architecture and SP width. -# See for a description -# of how to use such own spec files. - -*avrlibc_startfile: - crtatmega103.o%s - -*avrlibc_devicelib: - %{!nodevicelib:-latmega103} - -*cc1_n_flash: - %{!mn-flash=*:-mn-flash=2} - -*cc1_rmw: - %{mrmw} - -*cc1_errata_skip: - %{!mno-skip-bug: -mskip-bug} - -*cc1_absdata: - %{mabsdata} - -*asm_arch: - -mmcu=avr31 - -*asm_relax: - %{mrelax:--mlink-relax} - -*asm_rmw: - %{mrmw} - -*asm_errata_skip: - %{mno-skip-bug} - -*link_pmem_wrap: - - -*link_relax: - %{mrelax:--relax} - -*link_arch: - %{mmcu=*:-m%*} - -*link_data_start: - - -*link_text_start: - - -*self_spec: - %{!mmcu=avr*: % -# #elif ... -# -# If no device macro is defined, AVR-LibC uses __AVR_DEV_LIB_NAME__ -# as fallback to determine the name of the device header as -# -# "avr/io" + __AVR_DEV_LIB_NAME__ + ".h" -# -# If you provide your own specs file for a device not yet known to -# AVR-LibC, you can now define the hook macro __AVR_DEV_LIB_NAME__ -# as needed so that -# -# #include -# -# will include the desired device header. For ATmega8A the supplement -# to *cpp would read -# -# -D__AVR_DEV_LIB_NAME__=m8a - - -*cpp: - -D__AVR_ATmega103__ -D__AVR_DEVICE_NAME__=atmega103 - -# End of file diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega128 b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega128 deleted file mode 100644 index b0fcc67..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega128 +++ /dev/null @@ -1,99 +0,0 @@ -# -# Auto-generated specs for AVR device atmega128 (core avr51, 16-bit SP) -# -# Generated by : ./gcc/config/avr/gen-avr-mmcu-specs.c -# Generated from : ./gcc/config/gcc.c -# ./gcc/config/avr/specs.h -# ./gcc/config/avr/avrlibc.h -# Used by : avr-gcc compiler driver -# Used for : building command options for sub-processes -# -# See -# for a documentation of spec files. - - -# If you intend to use an existing device specs file as a starting point -# for a new device spec file, make sure you are copying from a specs -# file for a device from the same core architecture and SP width. -# See for a description -# of how to use such own spec files. - -*avrlibc_startfile: - crtatmega128.o%s - -*avrlibc_devicelib: - %{!nodevicelib:-latmega128} - -*cc1_n_flash: - %{!mn-flash=*:-mn-flash=2} - -*cc1_rmw: - %{mrmw} - -*cc1_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*cc1_absdata: - %{mabsdata} - -*asm_arch: - -mmcu=avr51 - -*asm_relax: - %{mrelax:--mlink-relax} - -*asm_rmw: - %{mrmw} - -*asm_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*link_pmem_wrap: - - -*link_relax: - %{mrelax:--relax} - -*link_arch: - %{mmcu=*:-m%*} - -*link_data_start: - -Tdata 0x800100 - -*link_text_start: - - -*self_spec: - %{!mmcu=avr*: % -# #elif ... -# -# If no device macro is defined, AVR-LibC uses __AVR_DEV_LIB_NAME__ -# as fallback to determine the name of the device header as -# -# "avr/io" + __AVR_DEV_LIB_NAME__ + ".h" -# -# If you provide your own specs file for a device not yet known to -# AVR-LibC, you can now define the hook macro __AVR_DEV_LIB_NAME__ -# as needed so that -# -# #include -# -# will include the desired device header. For ATmega8A the supplement -# to *cpp would read -# -# -D__AVR_DEV_LIB_NAME__=m8a - - -*cpp: - -D__AVR_ATmega128__ -D__AVR_DEVICE_NAME__=atmega128 - -# End of file diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega1280 b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega1280 deleted file mode 100644 index 7b1253b..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega1280 +++ /dev/null @@ -1,99 +0,0 @@ -# -# Auto-generated specs for AVR device atmega1280 (core avr51, 16-bit SP) -# -# Generated by : ./gcc/config/avr/gen-avr-mmcu-specs.c -# Generated from : ./gcc/config/gcc.c -# ./gcc/config/avr/specs.h -# ./gcc/config/avr/avrlibc.h -# Used by : avr-gcc compiler driver -# Used for : building command options for sub-processes -# -# See -# for a documentation of spec files. - - -# If you intend to use an existing device specs file as a starting point -# for a new device spec file, make sure you are copying from a specs -# file for a device from the same core architecture and SP width. -# See for a description -# of how to use such own spec files. - -*avrlibc_startfile: - crtatmega1280.o%s - -*avrlibc_devicelib: - %{!nodevicelib:-latmega1280} - -*cc1_n_flash: - %{!mn-flash=*:-mn-flash=2} - -*cc1_rmw: - %{mrmw} - -*cc1_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*cc1_absdata: - %{mabsdata} - -*asm_arch: - -mmcu=avr51 - -*asm_relax: - %{mrelax:--mlink-relax} - -*asm_rmw: - %{mrmw} - -*asm_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*link_pmem_wrap: - - -*link_relax: - %{mrelax:--relax} - -*link_arch: - %{mmcu=*:-m%*} - -*link_data_start: - -Tdata 0x800200 - -*link_text_start: - - -*self_spec: - %{!mmcu=avr*: % -# #elif ... -# -# If no device macro is defined, AVR-LibC uses __AVR_DEV_LIB_NAME__ -# as fallback to determine the name of the device header as -# -# "avr/io" + __AVR_DEV_LIB_NAME__ + ".h" -# -# If you provide your own specs file for a device not yet known to -# AVR-LibC, you can now define the hook macro __AVR_DEV_LIB_NAME__ -# as needed so that -# -# #include -# -# will include the desired device header. For ATmega8A the supplement -# to *cpp would read -# -# -D__AVR_DEV_LIB_NAME__=m8a - - -*cpp: - -D__AVR_ATmega1280__ -D__AVR_DEVICE_NAME__=atmega1280 - -# End of file diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega1281 b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega1281 deleted file mode 100644 index 650a67c..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega1281 +++ /dev/null @@ -1,99 +0,0 @@ -# -# Auto-generated specs for AVR device atmega1281 (core avr51, 16-bit SP) -# -# Generated by : ./gcc/config/avr/gen-avr-mmcu-specs.c -# Generated from : ./gcc/config/gcc.c -# ./gcc/config/avr/specs.h -# ./gcc/config/avr/avrlibc.h -# Used by : avr-gcc compiler driver -# Used for : building command options for sub-processes -# -# See -# for a documentation of spec files. - - -# If you intend to use an existing device specs file as a starting point -# for a new device spec file, make sure you are copying from a specs -# file for a device from the same core architecture and SP width. -# See for a description -# of how to use such own spec files. - -*avrlibc_startfile: - crtatmega1281.o%s - -*avrlibc_devicelib: - %{!nodevicelib:-latmega1281} - -*cc1_n_flash: - %{!mn-flash=*:-mn-flash=2} - -*cc1_rmw: - %{mrmw} - -*cc1_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*cc1_absdata: - %{mabsdata} - -*asm_arch: - -mmcu=avr51 - -*asm_relax: - %{mrelax:--mlink-relax} - -*asm_rmw: - %{mrmw} - -*asm_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*link_pmem_wrap: - - -*link_relax: - %{mrelax:--relax} - -*link_arch: - %{mmcu=*:-m%*} - -*link_data_start: - -Tdata 0x800200 - -*link_text_start: - - -*self_spec: - %{!mmcu=avr*: % -# #elif ... -# -# If no device macro is defined, AVR-LibC uses __AVR_DEV_LIB_NAME__ -# as fallback to determine the name of the device header as -# -# "avr/io" + __AVR_DEV_LIB_NAME__ + ".h" -# -# If you provide your own specs file for a device not yet known to -# AVR-LibC, you can now define the hook macro __AVR_DEV_LIB_NAME__ -# as needed so that -# -# #include -# -# will include the desired device header. For ATmega8A the supplement -# to *cpp would read -# -# -D__AVR_DEV_LIB_NAME__=m8a - - -*cpp: - -D__AVR_ATmega1281__ -D__AVR_DEVICE_NAME__=atmega1281 - -# End of file diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega1284 b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega1284 deleted file mode 100644 index 22c94fe..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega1284 +++ /dev/null @@ -1,99 +0,0 @@ -# -# Auto-generated specs for AVR device atmega1284 (core avr51, 16-bit SP) -# -# Generated by : ./gcc/config/avr/gen-avr-mmcu-specs.c -# Generated from : ./gcc/config/gcc.c -# ./gcc/config/avr/specs.h -# ./gcc/config/avr/avrlibc.h -# Used by : avr-gcc compiler driver -# Used for : building command options for sub-processes -# -# See -# for a documentation of spec files. - - -# If you intend to use an existing device specs file as a starting point -# for a new device spec file, make sure you are copying from a specs -# file for a device from the same core architecture and SP width. -# See for a description -# of how to use such own spec files. - -*avrlibc_startfile: - crtatmega1284.o%s - -*avrlibc_devicelib: - %{!nodevicelib:-latmega1284} - -*cc1_n_flash: - %{!mn-flash=*:-mn-flash=2} - -*cc1_rmw: - %{mrmw} - -*cc1_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*cc1_absdata: - %{mabsdata} - -*asm_arch: - -mmcu=avr51 - -*asm_relax: - %{mrelax:--mlink-relax} - -*asm_rmw: - %{mrmw} - -*asm_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*link_pmem_wrap: - - -*link_relax: - %{mrelax:--relax} - -*link_arch: - %{mmcu=*:-m%*} - -*link_data_start: - -Tdata 0x800100 - -*link_text_start: - - -*self_spec: - %{!mmcu=avr*: % -# #elif ... -# -# If no device macro is defined, AVR-LibC uses __AVR_DEV_LIB_NAME__ -# as fallback to determine the name of the device header as -# -# "avr/io" + __AVR_DEV_LIB_NAME__ + ".h" -# -# If you provide your own specs file for a device not yet known to -# AVR-LibC, you can now define the hook macro __AVR_DEV_LIB_NAME__ -# as needed so that -# -# #include -# -# will include the desired device header. For ATmega8A the supplement -# to *cpp would read -# -# -D__AVR_DEV_LIB_NAME__=m8a - - -*cpp: - -D__AVR_ATmega1284__ -D__AVR_DEVICE_NAME__=atmega1284 - -# End of file diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega1284p b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega1284p deleted file mode 100644 index 8260fa7..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega1284p +++ /dev/null @@ -1,99 +0,0 @@ -# -# Auto-generated specs for AVR device atmega1284p (core avr51, 16-bit SP) -# -# Generated by : ./gcc/config/avr/gen-avr-mmcu-specs.c -# Generated from : ./gcc/config/gcc.c -# ./gcc/config/avr/specs.h -# ./gcc/config/avr/avrlibc.h -# Used by : avr-gcc compiler driver -# Used for : building command options for sub-processes -# -# See -# for a documentation of spec files. - - -# If you intend to use an existing device specs file as a starting point -# for a new device spec file, make sure you are copying from a specs -# file for a device from the same core architecture and SP width. -# See for a description -# of how to use such own spec files. - -*avrlibc_startfile: - crtatmega1284p.o%s - -*avrlibc_devicelib: - %{!nodevicelib:-latmega1284p} - -*cc1_n_flash: - %{!mn-flash=*:-mn-flash=2} - -*cc1_rmw: - %{mrmw} - -*cc1_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*cc1_absdata: - %{mabsdata} - -*asm_arch: - -mmcu=avr51 - -*asm_relax: - %{mrelax:--mlink-relax} - -*asm_rmw: - %{mrmw} - -*asm_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*link_pmem_wrap: - - -*link_relax: - %{mrelax:--relax} - -*link_arch: - %{mmcu=*:-m%*} - -*link_data_start: - -Tdata 0x800100 - -*link_text_start: - - -*self_spec: - %{!mmcu=avr*: % -# #elif ... -# -# If no device macro is defined, AVR-LibC uses __AVR_DEV_LIB_NAME__ -# as fallback to determine the name of the device header as -# -# "avr/io" + __AVR_DEV_LIB_NAME__ + ".h" -# -# If you provide your own specs file for a device not yet known to -# AVR-LibC, you can now define the hook macro __AVR_DEV_LIB_NAME__ -# as needed so that -# -# #include -# -# will include the desired device header. For ATmega8A the supplement -# to *cpp would read -# -# -D__AVR_DEV_LIB_NAME__=m8a - - -*cpp: - -D__AVR_ATmega1284P__ -D__AVR_DEVICE_NAME__=atmega1284p - -# End of file diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega1284rfr2 b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega1284rfr2 deleted file mode 100644 index 4719996..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega1284rfr2 +++ /dev/null @@ -1,99 +0,0 @@ -# -# Auto-generated specs for AVR device atmega1284rfr2 (core avr51, 16-bit SP) -# -# Generated by : ./gcc/config/avr/gen-avr-mmcu-specs.c -# Generated from : ./gcc/config/gcc.c -# ./gcc/config/avr/specs.h -# ./gcc/config/avr/avrlibc.h -# Used by : avr-gcc compiler driver -# Used for : building command options for sub-processes -# -# See -# for a documentation of spec files. - - -# If you intend to use an existing device specs file as a starting point -# for a new device spec file, make sure you are copying from a specs -# file for a device from the same core architecture and SP width. -# See for a description -# of how to use such own spec files. - -*avrlibc_startfile: - crtatmega1284rfr2.o%s - -*avrlibc_devicelib: - %{!nodevicelib:-latmega1284rfr2} - -*cc1_n_flash: - %{!mn-flash=*:-mn-flash=2} - -*cc1_rmw: - %{mrmw} - -*cc1_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*cc1_absdata: - %{mabsdata} - -*asm_arch: - -mmcu=avr51 - -*asm_relax: - %{mrelax:--mlink-relax} - -*asm_rmw: - %{mrmw} - -*asm_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*link_pmem_wrap: - - -*link_relax: - %{mrelax:--relax} - -*link_arch: - %{mmcu=*:-m%*} - -*link_data_start: - -Tdata 0x800200 - -*link_text_start: - - -*self_spec: - %{!mmcu=avr*: % -# #elif ... -# -# If no device macro is defined, AVR-LibC uses __AVR_DEV_LIB_NAME__ -# as fallback to determine the name of the device header as -# -# "avr/io" + __AVR_DEV_LIB_NAME__ + ".h" -# -# If you provide your own specs file for a device not yet known to -# AVR-LibC, you can now define the hook macro __AVR_DEV_LIB_NAME__ -# as needed so that -# -# #include -# -# will include the desired device header. For ATmega8A the supplement -# to *cpp would read -# -# -D__AVR_DEV_LIB_NAME__=m8a - - -*cpp: - -D__AVR_ATmega1284RFR2__ -D__AVR_DEVICE_NAME__=atmega1284rfr2 - -# End of file diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega128a b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega128a deleted file mode 100644 index 567152f..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega128a +++ /dev/null @@ -1,99 +0,0 @@ -# -# Auto-generated specs for AVR device atmega128a (core avr51, 16-bit SP) -# -# Generated by : ./gcc/config/avr/gen-avr-mmcu-specs.c -# Generated from : ./gcc/config/gcc.c -# ./gcc/config/avr/specs.h -# ./gcc/config/avr/avrlibc.h -# Used by : avr-gcc compiler driver -# Used for : building command options for sub-processes -# -# See -# for a documentation of spec files. - - -# If you intend to use an existing device specs file as a starting point -# for a new device spec file, make sure you are copying from a specs -# file for a device from the same core architecture and SP width. -# See for a description -# of how to use such own spec files. - -*avrlibc_startfile: - crtatmega128a.o%s - -*avrlibc_devicelib: - %{!nodevicelib:-latmega128a} - -*cc1_n_flash: - %{!mn-flash=*:-mn-flash=2} - -*cc1_rmw: - %{mrmw} - -*cc1_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*cc1_absdata: - %{mabsdata} - -*asm_arch: - -mmcu=avr51 - -*asm_relax: - %{mrelax:--mlink-relax} - -*asm_rmw: - %{mrmw} - -*asm_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*link_pmem_wrap: - - -*link_relax: - %{mrelax:--relax} - -*link_arch: - %{mmcu=*:-m%*} - -*link_data_start: - -Tdata 0x800100 - -*link_text_start: - - -*self_spec: - %{!mmcu=avr*: % -# #elif ... -# -# If no device macro is defined, AVR-LibC uses __AVR_DEV_LIB_NAME__ -# as fallback to determine the name of the device header as -# -# "avr/io" + __AVR_DEV_LIB_NAME__ + ".h" -# -# If you provide your own specs file for a device not yet known to -# AVR-LibC, you can now define the hook macro __AVR_DEV_LIB_NAME__ -# as needed so that -# -# #include -# -# will include the desired device header. For ATmega8A the supplement -# to *cpp would read -# -# -D__AVR_DEV_LIB_NAME__=m8a - - -*cpp: - -D__AVR_ATmega128A__ -D__AVR_DEVICE_NAME__=atmega128a - -# End of file diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega128rfa1 b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega128rfa1 deleted file mode 100644 index 5eee734..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega128rfa1 +++ /dev/null @@ -1,99 +0,0 @@ -# -# Auto-generated specs for AVR device atmega128rfa1 (core avr51, 16-bit SP) -# -# Generated by : ./gcc/config/avr/gen-avr-mmcu-specs.c -# Generated from : ./gcc/config/gcc.c -# ./gcc/config/avr/specs.h -# ./gcc/config/avr/avrlibc.h -# Used by : avr-gcc compiler driver -# Used for : building command options for sub-processes -# -# See -# for a documentation of spec files. - - -# If you intend to use an existing device specs file as a starting point -# for a new device spec file, make sure you are copying from a specs -# file for a device from the same core architecture and SP width. -# See for a description -# of how to use such own spec files. - -*avrlibc_startfile: - crtatmega128rfa1.o%s - -*avrlibc_devicelib: - %{!nodevicelib:-latmega128rfa1} - -*cc1_n_flash: - %{!mn-flash=*:-mn-flash=2} - -*cc1_rmw: - %{mrmw} - -*cc1_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*cc1_absdata: - %{mabsdata} - -*asm_arch: - -mmcu=avr51 - -*asm_relax: - %{mrelax:--mlink-relax} - -*asm_rmw: - %{mrmw} - -*asm_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*link_pmem_wrap: - - -*link_relax: - %{mrelax:--relax} - -*link_arch: - %{mmcu=*:-m%*} - -*link_data_start: - -Tdata 0x800200 - -*link_text_start: - - -*self_spec: - %{!mmcu=avr*: % -# #elif ... -# -# If no device macro is defined, AVR-LibC uses __AVR_DEV_LIB_NAME__ -# as fallback to determine the name of the device header as -# -# "avr/io" + __AVR_DEV_LIB_NAME__ + ".h" -# -# If you provide your own specs file for a device not yet known to -# AVR-LibC, you can now define the hook macro __AVR_DEV_LIB_NAME__ -# as needed so that -# -# #include -# -# will include the desired device header. For ATmega8A the supplement -# to *cpp would read -# -# -D__AVR_DEV_LIB_NAME__=m8a - - -*cpp: - -D__AVR_ATmega128RFA1__ -D__AVR_DEVICE_NAME__=atmega128rfa1 - -# End of file diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega128rfr2 b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega128rfr2 deleted file mode 100644 index aa66832..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega128rfr2 +++ /dev/null @@ -1,99 +0,0 @@ -# -# Auto-generated specs for AVR device atmega128rfr2 (core avr51, 16-bit SP) -# -# Generated by : ./gcc/config/avr/gen-avr-mmcu-specs.c -# Generated from : ./gcc/config/gcc.c -# ./gcc/config/avr/specs.h -# ./gcc/config/avr/avrlibc.h -# Used by : avr-gcc compiler driver -# Used for : building command options for sub-processes -# -# See -# for a documentation of spec files. - - -# If you intend to use an existing device specs file as a starting point -# for a new device spec file, make sure you are copying from a specs -# file for a device from the same core architecture and SP width. -# See for a description -# of how to use such own spec files. - -*avrlibc_startfile: - crtatmega128rfr2.o%s - -*avrlibc_devicelib: - %{!nodevicelib:-latmega128rfr2} - -*cc1_n_flash: - %{!mn-flash=*:-mn-flash=2} - -*cc1_rmw: - %{mrmw} - -*cc1_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*cc1_absdata: - %{mabsdata} - -*asm_arch: - -mmcu=avr51 - -*asm_relax: - %{mrelax:--mlink-relax} - -*asm_rmw: - %{mrmw} - -*asm_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*link_pmem_wrap: - - -*link_relax: - %{mrelax:--relax} - -*link_arch: - %{mmcu=*:-m%*} - -*link_data_start: - -Tdata 0x800200 - -*link_text_start: - - -*self_spec: - %{!mmcu=avr*: % -# #elif ... -# -# If no device macro is defined, AVR-LibC uses __AVR_DEV_LIB_NAME__ -# as fallback to determine the name of the device header as -# -# "avr/io" + __AVR_DEV_LIB_NAME__ + ".h" -# -# If you provide your own specs file for a device not yet known to -# AVR-LibC, you can now define the hook macro __AVR_DEV_LIB_NAME__ -# as needed so that -# -# #include -# -# will include the desired device header. For ATmega8A the supplement -# to *cpp would read -# -# -D__AVR_DEV_LIB_NAME__=m8a - - -*cpp: - -D__AVR_ATmega128RFR2__ -D__AVR_DEVICE_NAME__=atmega128rfr2 - -# End of file diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega16 b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega16 deleted file mode 100644 index 0fe17da..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega16 +++ /dev/null @@ -1,99 +0,0 @@ -# -# Auto-generated specs for AVR device atmega16 (core avr5, 16-bit SP) -# -# Generated by : ./gcc/config/avr/gen-avr-mmcu-specs.c -# Generated from : ./gcc/config/gcc.c -# ./gcc/config/avr/specs.h -# ./gcc/config/avr/avrlibc.h -# Used by : avr-gcc compiler driver -# Used for : building command options for sub-processes -# -# See -# for a documentation of spec files. - - -# If you intend to use an existing device specs file as a starting point -# for a new device spec file, make sure you are copying from a specs -# file for a device from the same core architecture and SP width. -# See for a description -# of how to use such own spec files. - -*avrlibc_startfile: - crtatmega16.o%s - -*avrlibc_devicelib: - %{!nodevicelib:-latmega16} - -*cc1_n_flash: - %{!mn-flash=*:-mn-flash=1} - -*cc1_rmw: - %{mrmw} - -*cc1_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*cc1_absdata: - %{mabsdata} - -*asm_arch: - -mmcu=avr5 - -*asm_relax: - %{mrelax:--mlink-relax} - -*asm_rmw: - %{mrmw} - -*asm_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*link_pmem_wrap: - %{mpmem-wrap-around: --pmem-wrap-around=16k} - -*link_relax: - %{mrelax:--relax} - -*link_arch: - %{mmcu=*:-m%*} - -*link_data_start: - - -*link_text_start: - - -*self_spec: - %{!mmcu=avr*: % -# #elif ... -# -# If no device macro is defined, AVR-LibC uses __AVR_DEV_LIB_NAME__ -# as fallback to determine the name of the device header as -# -# "avr/io" + __AVR_DEV_LIB_NAME__ + ".h" -# -# If you provide your own specs file for a device not yet known to -# AVR-LibC, you can now define the hook macro __AVR_DEV_LIB_NAME__ -# as needed so that -# -# #include -# -# will include the desired device header. For ATmega8A the supplement -# to *cpp would read -# -# -D__AVR_DEV_LIB_NAME__=m8a - - -*cpp: - -D__AVR_ATmega16__ -D__AVR_DEVICE_NAME__=atmega16 - -# End of file diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega161 b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega161 deleted file mode 100644 index 5a641e8..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega161 +++ /dev/null @@ -1,99 +0,0 @@ -# -# Auto-generated specs for AVR device atmega161 (core avr5, 16-bit SP) -# -# Generated by : ./gcc/config/avr/gen-avr-mmcu-specs.c -# Generated from : ./gcc/config/gcc.c -# ./gcc/config/avr/specs.h -# ./gcc/config/avr/avrlibc.h -# Used by : avr-gcc compiler driver -# Used for : building command options for sub-processes -# -# See -# for a documentation of spec files. - - -# If you intend to use an existing device specs file as a starting point -# for a new device spec file, make sure you are copying from a specs -# file for a device from the same core architecture and SP width. -# See for a description -# of how to use such own spec files. - -*avrlibc_startfile: - crtatmega161.o%s - -*avrlibc_devicelib: - %{!nodevicelib:-latmega161} - -*cc1_n_flash: - %{!mn-flash=*:-mn-flash=1} - -*cc1_rmw: - %{mrmw} - -*cc1_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*cc1_absdata: - %{mabsdata} - -*asm_arch: - -mmcu=avr5 - -*asm_relax: - %{mrelax:--mlink-relax} - -*asm_rmw: - %{mrmw} - -*asm_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*link_pmem_wrap: - %{mpmem-wrap-around: --pmem-wrap-around=16k} - -*link_relax: - %{mrelax:--relax} - -*link_arch: - %{mmcu=*:-m%*} - -*link_data_start: - - -*link_text_start: - - -*self_spec: - %{!mmcu=avr*: % -# #elif ... -# -# If no device macro is defined, AVR-LibC uses __AVR_DEV_LIB_NAME__ -# as fallback to determine the name of the device header as -# -# "avr/io" + __AVR_DEV_LIB_NAME__ + ".h" -# -# If you provide your own specs file for a device not yet known to -# AVR-LibC, you can now define the hook macro __AVR_DEV_LIB_NAME__ -# as needed so that -# -# #include -# -# will include the desired device header. For ATmega8A the supplement -# to *cpp would read -# -# -D__AVR_DEV_LIB_NAME__=m8a - - -*cpp: - -D__AVR_ATmega161__ -D__AVR_DEVICE_NAME__=atmega161 - -# End of file diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega162 b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega162 deleted file mode 100644 index 1be62b5..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega162 +++ /dev/null @@ -1,99 +0,0 @@ -# -# Auto-generated specs for AVR device atmega162 (core avr5, 16-bit SP) -# -# Generated by : ./gcc/config/avr/gen-avr-mmcu-specs.c -# Generated from : ./gcc/config/gcc.c -# ./gcc/config/avr/specs.h -# ./gcc/config/avr/avrlibc.h -# Used by : avr-gcc compiler driver -# Used for : building command options for sub-processes -# -# See -# for a documentation of spec files. - - -# If you intend to use an existing device specs file as a starting point -# for a new device spec file, make sure you are copying from a specs -# file for a device from the same core architecture and SP width. -# See for a description -# of how to use such own spec files. - -*avrlibc_startfile: - crtatmega162.o%s - -*avrlibc_devicelib: - %{!nodevicelib:-latmega162} - -*cc1_n_flash: - %{!mn-flash=*:-mn-flash=1} - -*cc1_rmw: - %{mrmw} - -*cc1_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*cc1_absdata: - %{mabsdata} - -*asm_arch: - -mmcu=avr5 - -*asm_relax: - %{mrelax:--mlink-relax} - -*asm_rmw: - %{mrmw} - -*asm_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*link_pmem_wrap: - %{mpmem-wrap-around: --pmem-wrap-around=16k} - -*link_relax: - %{mrelax:--relax} - -*link_arch: - %{mmcu=*:-m%*} - -*link_data_start: - -Tdata 0x800100 - -*link_text_start: - - -*self_spec: - %{!mmcu=avr*: % -# #elif ... -# -# If no device macro is defined, AVR-LibC uses __AVR_DEV_LIB_NAME__ -# as fallback to determine the name of the device header as -# -# "avr/io" + __AVR_DEV_LIB_NAME__ + ".h" -# -# If you provide your own specs file for a device not yet known to -# AVR-LibC, you can now define the hook macro __AVR_DEV_LIB_NAME__ -# as needed so that -# -# #include -# -# will include the desired device header. For ATmega8A the supplement -# to *cpp would read -# -# -D__AVR_DEV_LIB_NAME__=m8a - - -*cpp: - -D__AVR_ATmega162__ -D__AVR_DEVICE_NAME__=atmega162 - -# End of file diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega163 b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega163 deleted file mode 100644 index 503ab26..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega163 +++ /dev/null @@ -1,99 +0,0 @@ -# -# Auto-generated specs for AVR device atmega163 (core avr5, 16-bit SP) -# -# Generated by : ./gcc/config/avr/gen-avr-mmcu-specs.c -# Generated from : ./gcc/config/gcc.c -# ./gcc/config/avr/specs.h -# ./gcc/config/avr/avrlibc.h -# Used by : avr-gcc compiler driver -# Used for : building command options for sub-processes -# -# See -# for a documentation of spec files. - - -# If you intend to use an existing device specs file as a starting point -# for a new device spec file, make sure you are copying from a specs -# file for a device from the same core architecture and SP width. -# See for a description -# of how to use such own spec files. - -*avrlibc_startfile: - crtatmega163.o%s - -*avrlibc_devicelib: - %{!nodevicelib:-latmega163} - -*cc1_n_flash: - %{!mn-flash=*:-mn-flash=1} - -*cc1_rmw: - %{mrmw} - -*cc1_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*cc1_absdata: - %{mabsdata} - -*asm_arch: - -mmcu=avr5 - -*asm_relax: - %{mrelax:--mlink-relax} - -*asm_rmw: - %{mrmw} - -*asm_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*link_pmem_wrap: - %{mpmem-wrap-around: --pmem-wrap-around=16k} - -*link_relax: - %{mrelax:--relax} - -*link_arch: - %{mmcu=*:-m%*} - -*link_data_start: - - -*link_text_start: - - -*self_spec: - %{!mmcu=avr*: % -# #elif ... -# -# If no device macro is defined, AVR-LibC uses __AVR_DEV_LIB_NAME__ -# as fallback to determine the name of the device header as -# -# "avr/io" + __AVR_DEV_LIB_NAME__ + ".h" -# -# If you provide your own specs file for a device not yet known to -# AVR-LibC, you can now define the hook macro __AVR_DEV_LIB_NAME__ -# as needed so that -# -# #include -# -# will include the desired device header. For ATmega8A the supplement -# to *cpp would read -# -# -D__AVR_DEV_LIB_NAME__=m8a - - -*cpp: - -D__AVR_ATmega163__ -D__AVR_DEVICE_NAME__=atmega163 - -# End of file diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega164a b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega164a deleted file mode 100644 index 47268b4..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega164a +++ /dev/null @@ -1,99 +0,0 @@ -# -# Auto-generated specs for AVR device atmega164a (core avr5, 16-bit SP) -# -# Generated by : ./gcc/config/avr/gen-avr-mmcu-specs.c -# Generated from : ./gcc/config/gcc.c -# ./gcc/config/avr/specs.h -# ./gcc/config/avr/avrlibc.h -# Used by : avr-gcc compiler driver -# Used for : building command options for sub-processes -# -# See -# for a documentation of spec files. - - -# If you intend to use an existing device specs file as a starting point -# for a new device spec file, make sure you are copying from a specs -# file for a device from the same core architecture and SP width. -# See for a description -# of how to use such own spec files. - -*avrlibc_startfile: - crtatmega164a.o%s - -*avrlibc_devicelib: - %{!nodevicelib:-latmega164a} - -*cc1_n_flash: - %{!mn-flash=*:-mn-flash=1} - -*cc1_rmw: - %{mrmw} - -*cc1_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*cc1_absdata: - %{mabsdata} - -*asm_arch: - -mmcu=avr5 - -*asm_relax: - %{mrelax:--mlink-relax} - -*asm_rmw: - %{mrmw} - -*asm_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*link_pmem_wrap: - %{mpmem-wrap-around: --pmem-wrap-around=16k} - -*link_relax: - %{mrelax:--relax} - -*link_arch: - %{mmcu=*:-m%*} - -*link_data_start: - -Tdata 0x800100 - -*link_text_start: - - -*self_spec: - %{!mmcu=avr*: % -# #elif ... -# -# If no device macro is defined, AVR-LibC uses __AVR_DEV_LIB_NAME__ -# as fallback to determine the name of the device header as -# -# "avr/io" + __AVR_DEV_LIB_NAME__ + ".h" -# -# If you provide your own specs file for a device not yet known to -# AVR-LibC, you can now define the hook macro __AVR_DEV_LIB_NAME__ -# as needed so that -# -# #include -# -# will include the desired device header. For ATmega8A the supplement -# to *cpp would read -# -# -D__AVR_DEV_LIB_NAME__=m8a - - -*cpp: - -D__AVR_ATmega164A__ -D__AVR_DEVICE_NAME__=atmega164a - -# End of file diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega164p b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega164p deleted file mode 100644 index d16491b..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega164p +++ /dev/null @@ -1,99 +0,0 @@ -# -# Auto-generated specs for AVR device atmega164p (core avr5, 16-bit SP) -# -# Generated by : ./gcc/config/avr/gen-avr-mmcu-specs.c -# Generated from : ./gcc/config/gcc.c -# ./gcc/config/avr/specs.h -# ./gcc/config/avr/avrlibc.h -# Used by : avr-gcc compiler driver -# Used for : building command options for sub-processes -# -# See -# for a documentation of spec files. - - -# If you intend to use an existing device specs file as a starting point -# for a new device spec file, make sure you are copying from a specs -# file for a device from the same core architecture and SP width. -# See for a description -# of how to use such own spec files. - -*avrlibc_startfile: - crtatmega164p.o%s - -*avrlibc_devicelib: - %{!nodevicelib:-latmega164p} - -*cc1_n_flash: - %{!mn-flash=*:-mn-flash=1} - -*cc1_rmw: - %{mrmw} - -*cc1_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*cc1_absdata: - %{mabsdata} - -*asm_arch: - -mmcu=avr5 - -*asm_relax: - %{mrelax:--mlink-relax} - -*asm_rmw: - %{mrmw} - -*asm_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*link_pmem_wrap: - %{mpmem-wrap-around: --pmem-wrap-around=16k} - -*link_relax: - %{mrelax:--relax} - -*link_arch: - %{mmcu=*:-m%*} - -*link_data_start: - -Tdata 0x800100 - -*link_text_start: - - -*self_spec: - %{!mmcu=avr*: % -# #elif ... -# -# If no device macro is defined, AVR-LibC uses __AVR_DEV_LIB_NAME__ -# as fallback to determine the name of the device header as -# -# "avr/io" + __AVR_DEV_LIB_NAME__ + ".h" -# -# If you provide your own specs file for a device not yet known to -# AVR-LibC, you can now define the hook macro __AVR_DEV_LIB_NAME__ -# as needed so that -# -# #include -# -# will include the desired device header. For ATmega8A the supplement -# to *cpp would read -# -# -D__AVR_DEV_LIB_NAME__=m8a - - -*cpp: - -D__AVR_ATmega164P__ -D__AVR_DEVICE_NAME__=atmega164p - -# End of file diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega164pa b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega164pa deleted file mode 100644 index bb734f2..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega164pa +++ /dev/null @@ -1,99 +0,0 @@ -# -# Auto-generated specs for AVR device atmega164pa (core avr5, 16-bit SP) -# -# Generated by : ./gcc/config/avr/gen-avr-mmcu-specs.c -# Generated from : ./gcc/config/gcc.c -# ./gcc/config/avr/specs.h -# ./gcc/config/avr/avrlibc.h -# Used by : avr-gcc compiler driver -# Used for : building command options for sub-processes -# -# See -# for a documentation of spec files. - - -# If you intend to use an existing device specs file as a starting point -# for a new device spec file, make sure you are copying from a specs -# file for a device from the same core architecture and SP width. -# See for a description -# of how to use such own spec files. - -*avrlibc_startfile: - crtatmega164pa.o%s - -*avrlibc_devicelib: - %{!nodevicelib:-latmega164pa} - -*cc1_n_flash: - %{!mn-flash=*:-mn-flash=1} - -*cc1_rmw: - %{mrmw} - -*cc1_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*cc1_absdata: - %{mabsdata} - -*asm_arch: - -mmcu=avr5 - -*asm_relax: - %{mrelax:--mlink-relax} - -*asm_rmw: - %{mrmw} - -*asm_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*link_pmem_wrap: - %{mpmem-wrap-around: --pmem-wrap-around=16k} - -*link_relax: - %{mrelax:--relax} - -*link_arch: - %{mmcu=*:-m%*} - -*link_data_start: - -Tdata 0x800100 - -*link_text_start: - - -*self_spec: - %{!mmcu=avr*: % -# #elif ... -# -# If no device macro is defined, AVR-LibC uses __AVR_DEV_LIB_NAME__ -# as fallback to determine the name of the device header as -# -# "avr/io" + __AVR_DEV_LIB_NAME__ + ".h" -# -# If you provide your own specs file for a device not yet known to -# AVR-LibC, you can now define the hook macro __AVR_DEV_LIB_NAME__ -# as needed so that -# -# #include -# -# will include the desired device header. For ATmega8A the supplement -# to *cpp would read -# -# -D__AVR_DEV_LIB_NAME__=m8a - - -*cpp: - -D__AVR_ATmega164PA__ -D__AVR_DEVICE_NAME__=atmega164pa - -# End of file diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega165 b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega165 deleted file mode 100644 index 2cb8ce3..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega165 +++ /dev/null @@ -1,99 +0,0 @@ -# -# Auto-generated specs for AVR device atmega165 (core avr5, 16-bit SP) -# -# Generated by : ./gcc/config/avr/gen-avr-mmcu-specs.c -# Generated from : ./gcc/config/gcc.c -# ./gcc/config/avr/specs.h -# ./gcc/config/avr/avrlibc.h -# Used by : avr-gcc compiler driver -# Used for : building command options for sub-processes -# -# See -# for a documentation of spec files. - - -# If you intend to use an existing device specs file as a starting point -# for a new device spec file, make sure you are copying from a specs -# file for a device from the same core architecture and SP width. -# See for a description -# of how to use such own spec files. - -*avrlibc_startfile: - crtatmega165.o%s - -*avrlibc_devicelib: - %{!nodevicelib:-latmega165} - -*cc1_n_flash: - %{!mn-flash=*:-mn-flash=1} - -*cc1_rmw: - %{mrmw} - -*cc1_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*cc1_absdata: - %{mabsdata} - -*asm_arch: - -mmcu=avr5 - -*asm_relax: - %{mrelax:--mlink-relax} - -*asm_rmw: - %{mrmw} - -*asm_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*link_pmem_wrap: - %{mpmem-wrap-around: --pmem-wrap-around=16k} - -*link_relax: - %{mrelax:--relax} - -*link_arch: - %{mmcu=*:-m%*} - -*link_data_start: - -Tdata 0x800100 - -*link_text_start: - - -*self_spec: - %{!mmcu=avr*: % -# #elif ... -# -# If no device macro is defined, AVR-LibC uses __AVR_DEV_LIB_NAME__ -# as fallback to determine the name of the device header as -# -# "avr/io" + __AVR_DEV_LIB_NAME__ + ".h" -# -# If you provide your own specs file for a device not yet known to -# AVR-LibC, you can now define the hook macro __AVR_DEV_LIB_NAME__ -# as needed so that -# -# #include -# -# will include the desired device header. For ATmega8A the supplement -# to *cpp would read -# -# -D__AVR_DEV_LIB_NAME__=m8a - - -*cpp: - -D__AVR_ATmega165__ -D__AVR_DEVICE_NAME__=atmega165 - -# End of file diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega165a b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega165a deleted file mode 100644 index 822cf08..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega165a +++ /dev/null @@ -1,99 +0,0 @@ -# -# Auto-generated specs for AVR device atmega165a (core avr5, 16-bit SP) -# -# Generated by : ./gcc/config/avr/gen-avr-mmcu-specs.c -# Generated from : ./gcc/config/gcc.c -# ./gcc/config/avr/specs.h -# ./gcc/config/avr/avrlibc.h -# Used by : avr-gcc compiler driver -# Used for : building command options for sub-processes -# -# See -# for a documentation of spec files. - - -# If you intend to use an existing device specs file as a starting point -# for a new device spec file, make sure you are copying from a specs -# file for a device from the same core architecture and SP width. -# See for a description -# of how to use such own spec files. - -*avrlibc_startfile: - crtatmega165a.o%s - -*avrlibc_devicelib: - %{!nodevicelib:-latmega165a} - -*cc1_n_flash: - %{!mn-flash=*:-mn-flash=1} - -*cc1_rmw: - %{mrmw} - -*cc1_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*cc1_absdata: - %{mabsdata} - -*asm_arch: - -mmcu=avr5 - -*asm_relax: - %{mrelax:--mlink-relax} - -*asm_rmw: - %{mrmw} - -*asm_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*link_pmem_wrap: - %{mpmem-wrap-around: --pmem-wrap-around=16k} - -*link_relax: - %{mrelax:--relax} - -*link_arch: - %{mmcu=*:-m%*} - -*link_data_start: - -Tdata 0x800100 - -*link_text_start: - - -*self_spec: - %{!mmcu=avr*: % -# #elif ... -# -# If no device macro is defined, AVR-LibC uses __AVR_DEV_LIB_NAME__ -# as fallback to determine the name of the device header as -# -# "avr/io" + __AVR_DEV_LIB_NAME__ + ".h" -# -# If you provide your own specs file for a device not yet known to -# AVR-LibC, you can now define the hook macro __AVR_DEV_LIB_NAME__ -# as needed so that -# -# #include -# -# will include the desired device header. For ATmega8A the supplement -# to *cpp would read -# -# -D__AVR_DEV_LIB_NAME__=m8a - - -*cpp: - -D__AVR_ATmega165A__ -D__AVR_DEVICE_NAME__=atmega165a - -# End of file diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega165p b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega165p deleted file mode 100644 index 8d7d831..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega165p +++ /dev/null @@ -1,99 +0,0 @@ -# -# Auto-generated specs for AVR device atmega165p (core avr5, 16-bit SP) -# -# Generated by : ./gcc/config/avr/gen-avr-mmcu-specs.c -# Generated from : ./gcc/config/gcc.c -# ./gcc/config/avr/specs.h -# ./gcc/config/avr/avrlibc.h -# Used by : avr-gcc compiler driver -# Used for : building command options for sub-processes -# -# See -# for a documentation of spec files. - - -# If you intend to use an existing device specs file as a starting point -# for a new device spec file, make sure you are copying from a specs -# file for a device from the same core architecture and SP width. -# See for a description -# of how to use such own spec files. - -*avrlibc_startfile: - crtatmega165p.o%s - -*avrlibc_devicelib: - %{!nodevicelib:-latmega165p} - -*cc1_n_flash: - %{!mn-flash=*:-mn-flash=1} - -*cc1_rmw: - %{mrmw} - -*cc1_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*cc1_absdata: - %{mabsdata} - -*asm_arch: - -mmcu=avr5 - -*asm_relax: - %{mrelax:--mlink-relax} - -*asm_rmw: - %{mrmw} - -*asm_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*link_pmem_wrap: - %{mpmem-wrap-around: --pmem-wrap-around=16k} - -*link_relax: - %{mrelax:--relax} - -*link_arch: - %{mmcu=*:-m%*} - -*link_data_start: - -Tdata 0x800100 - -*link_text_start: - - -*self_spec: - %{!mmcu=avr*: % -# #elif ... -# -# If no device macro is defined, AVR-LibC uses __AVR_DEV_LIB_NAME__ -# as fallback to determine the name of the device header as -# -# "avr/io" + __AVR_DEV_LIB_NAME__ + ".h" -# -# If you provide your own specs file for a device not yet known to -# AVR-LibC, you can now define the hook macro __AVR_DEV_LIB_NAME__ -# as needed so that -# -# #include -# -# will include the desired device header. For ATmega8A the supplement -# to *cpp would read -# -# -D__AVR_DEV_LIB_NAME__=m8a - - -*cpp: - -D__AVR_ATmega165P__ -D__AVR_DEVICE_NAME__=atmega165p - -# End of file diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega165pa b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega165pa deleted file mode 100644 index c895a01..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega165pa +++ /dev/null @@ -1,99 +0,0 @@ -# -# Auto-generated specs for AVR device atmega165pa (core avr5, 16-bit SP) -# -# Generated by : ./gcc/config/avr/gen-avr-mmcu-specs.c -# Generated from : ./gcc/config/gcc.c -# ./gcc/config/avr/specs.h -# ./gcc/config/avr/avrlibc.h -# Used by : avr-gcc compiler driver -# Used for : building command options for sub-processes -# -# See -# for a documentation of spec files. - - -# If you intend to use an existing device specs file as a starting point -# for a new device spec file, make sure you are copying from a specs -# file for a device from the same core architecture and SP width. -# See for a description -# of how to use such own spec files. - -*avrlibc_startfile: - crtatmega165pa.o%s - -*avrlibc_devicelib: - %{!nodevicelib:-latmega165pa} - -*cc1_n_flash: - %{!mn-flash=*:-mn-flash=1} - -*cc1_rmw: - %{mrmw} - -*cc1_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*cc1_absdata: - %{mabsdata} - -*asm_arch: - -mmcu=avr5 - -*asm_relax: - %{mrelax:--mlink-relax} - -*asm_rmw: - %{mrmw} - -*asm_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*link_pmem_wrap: - %{mpmem-wrap-around: --pmem-wrap-around=16k} - -*link_relax: - %{mrelax:--relax} - -*link_arch: - %{mmcu=*:-m%*} - -*link_data_start: - -Tdata 0x800100 - -*link_text_start: - - -*self_spec: - %{!mmcu=avr*: % -# #elif ... -# -# If no device macro is defined, AVR-LibC uses __AVR_DEV_LIB_NAME__ -# as fallback to determine the name of the device header as -# -# "avr/io" + __AVR_DEV_LIB_NAME__ + ".h" -# -# If you provide your own specs file for a device not yet known to -# AVR-LibC, you can now define the hook macro __AVR_DEV_LIB_NAME__ -# as needed so that -# -# #include -# -# will include the desired device header. For ATmega8A the supplement -# to *cpp would read -# -# -D__AVR_DEV_LIB_NAME__=m8a - - -*cpp: - -D__AVR_ATmega165PA__ -D__AVR_DEVICE_NAME__=atmega165pa - -# End of file diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega168 b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega168 deleted file mode 100644 index 7540ff9..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega168 +++ /dev/null @@ -1,99 +0,0 @@ -# -# Auto-generated specs for AVR device atmega168 (core avr5, 16-bit SP) -# -# Generated by : ./gcc/config/avr/gen-avr-mmcu-specs.c -# Generated from : ./gcc/config/gcc.c -# ./gcc/config/avr/specs.h -# ./gcc/config/avr/avrlibc.h -# Used by : avr-gcc compiler driver -# Used for : building command options for sub-processes -# -# See -# for a documentation of spec files. - - -# If you intend to use an existing device specs file as a starting point -# for a new device spec file, make sure you are copying from a specs -# file for a device from the same core architecture and SP width. -# See for a description -# of how to use such own spec files. - -*avrlibc_startfile: - crtatmega168.o%s - -*avrlibc_devicelib: - %{!nodevicelib:-latmega168} - -*cc1_n_flash: - %{!mn-flash=*:-mn-flash=1} - -*cc1_rmw: - %{mrmw} - -*cc1_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*cc1_absdata: - %{mabsdata} - -*asm_arch: - -mmcu=avr5 - -*asm_relax: - %{mrelax:--mlink-relax} - -*asm_rmw: - %{mrmw} - -*asm_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*link_pmem_wrap: - %{mpmem-wrap-around: --pmem-wrap-around=16k} - -*link_relax: - %{mrelax:--relax} - -*link_arch: - %{mmcu=*:-m%*} - -*link_data_start: - -Tdata 0x800100 - -*link_text_start: - - -*self_spec: - %{!mmcu=avr*: % -# #elif ... -# -# If no device macro is defined, AVR-LibC uses __AVR_DEV_LIB_NAME__ -# as fallback to determine the name of the device header as -# -# "avr/io" + __AVR_DEV_LIB_NAME__ + ".h" -# -# If you provide your own specs file for a device not yet known to -# AVR-LibC, you can now define the hook macro __AVR_DEV_LIB_NAME__ -# as needed so that -# -# #include -# -# will include the desired device header. For ATmega8A the supplement -# to *cpp would read -# -# -D__AVR_DEV_LIB_NAME__=m8a - - -*cpp: - -D__AVR_ATmega168__ -D__AVR_DEVICE_NAME__=atmega168 - -# End of file diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega168a b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega168a deleted file mode 100644 index ea92cbe..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega168a +++ /dev/null @@ -1,99 +0,0 @@ -# -# Auto-generated specs for AVR device atmega168a (core avr5, 16-bit SP) -# -# Generated by : ./gcc/config/avr/gen-avr-mmcu-specs.c -# Generated from : ./gcc/config/gcc.c -# ./gcc/config/avr/specs.h -# ./gcc/config/avr/avrlibc.h -# Used by : avr-gcc compiler driver -# Used for : building command options for sub-processes -# -# See -# for a documentation of spec files. - - -# If you intend to use an existing device specs file as a starting point -# for a new device spec file, make sure you are copying from a specs -# file for a device from the same core architecture and SP width. -# See for a description -# of how to use such own spec files. - -*avrlibc_startfile: - crtatmega168a.o%s - -*avrlibc_devicelib: - %{!nodevicelib:-latmega168a} - -*cc1_n_flash: - %{!mn-flash=*:-mn-flash=1} - -*cc1_rmw: - %{mrmw} - -*cc1_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*cc1_absdata: - %{mabsdata} - -*asm_arch: - -mmcu=avr5 - -*asm_relax: - %{mrelax:--mlink-relax} - -*asm_rmw: - %{mrmw} - -*asm_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*link_pmem_wrap: - %{mpmem-wrap-around: --pmem-wrap-around=16k} - -*link_relax: - %{mrelax:--relax} - -*link_arch: - %{mmcu=*:-m%*} - -*link_data_start: - -Tdata 0x800100 - -*link_text_start: - - -*self_spec: - %{!mmcu=avr*: % -# #elif ... -# -# If no device macro is defined, AVR-LibC uses __AVR_DEV_LIB_NAME__ -# as fallback to determine the name of the device header as -# -# "avr/io" + __AVR_DEV_LIB_NAME__ + ".h" -# -# If you provide your own specs file for a device not yet known to -# AVR-LibC, you can now define the hook macro __AVR_DEV_LIB_NAME__ -# as needed so that -# -# #include -# -# will include the desired device header. For ATmega8A the supplement -# to *cpp would read -# -# -D__AVR_DEV_LIB_NAME__=m8a - - -*cpp: - -D__AVR_ATmega168A__ -D__AVR_DEVICE_NAME__=atmega168a - -# End of file diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega168p b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega168p deleted file mode 100644 index 6a4cf80..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega168p +++ /dev/null @@ -1,99 +0,0 @@ -# -# Auto-generated specs for AVR device atmega168p (core avr5, 16-bit SP) -# -# Generated by : ./gcc/config/avr/gen-avr-mmcu-specs.c -# Generated from : ./gcc/config/gcc.c -# ./gcc/config/avr/specs.h -# ./gcc/config/avr/avrlibc.h -# Used by : avr-gcc compiler driver -# Used for : building command options for sub-processes -# -# See -# for a documentation of spec files. - - -# If you intend to use an existing device specs file as a starting point -# for a new device spec file, make sure you are copying from a specs -# file for a device from the same core architecture and SP width. -# See for a description -# of how to use such own spec files. - -*avrlibc_startfile: - crtatmega168p.o%s - -*avrlibc_devicelib: - %{!nodevicelib:-latmega168p} - -*cc1_n_flash: - %{!mn-flash=*:-mn-flash=1} - -*cc1_rmw: - %{mrmw} - -*cc1_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*cc1_absdata: - %{mabsdata} - -*asm_arch: - -mmcu=avr5 - -*asm_relax: - %{mrelax:--mlink-relax} - -*asm_rmw: - %{mrmw} - -*asm_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*link_pmem_wrap: - %{mpmem-wrap-around: --pmem-wrap-around=16k} - -*link_relax: - %{mrelax:--relax} - -*link_arch: - %{mmcu=*:-m%*} - -*link_data_start: - -Tdata 0x800100 - -*link_text_start: - - -*self_spec: - %{!mmcu=avr*: % -# #elif ... -# -# If no device macro is defined, AVR-LibC uses __AVR_DEV_LIB_NAME__ -# as fallback to determine the name of the device header as -# -# "avr/io" + __AVR_DEV_LIB_NAME__ + ".h" -# -# If you provide your own specs file for a device not yet known to -# AVR-LibC, you can now define the hook macro __AVR_DEV_LIB_NAME__ -# as needed so that -# -# #include -# -# will include the desired device header. For ATmega8A the supplement -# to *cpp would read -# -# -D__AVR_DEV_LIB_NAME__=m8a - - -*cpp: - -D__AVR_ATmega168P__ -D__AVR_DEVICE_NAME__=atmega168p - -# End of file diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega168pa b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega168pa deleted file mode 100644 index 07501c2..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega168pa +++ /dev/null @@ -1,99 +0,0 @@ -# -# Auto-generated specs for AVR device atmega168pa (core avr5, 16-bit SP) -# -# Generated by : ./gcc/config/avr/gen-avr-mmcu-specs.c -# Generated from : ./gcc/config/gcc.c -# ./gcc/config/avr/specs.h -# ./gcc/config/avr/avrlibc.h -# Used by : avr-gcc compiler driver -# Used for : building command options for sub-processes -# -# See -# for a documentation of spec files. - - -# If you intend to use an existing device specs file as a starting point -# for a new device spec file, make sure you are copying from a specs -# file for a device from the same core architecture and SP width. -# See for a description -# of how to use such own spec files. - -*avrlibc_startfile: - crtatmega168pa.o%s - -*avrlibc_devicelib: - %{!nodevicelib:-latmega168pa} - -*cc1_n_flash: - %{!mn-flash=*:-mn-flash=1} - -*cc1_rmw: - %{mrmw} - -*cc1_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*cc1_absdata: - %{mabsdata} - -*asm_arch: - -mmcu=avr5 - -*asm_relax: - %{mrelax:--mlink-relax} - -*asm_rmw: - %{mrmw} - -*asm_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*link_pmem_wrap: - %{mpmem-wrap-around: --pmem-wrap-around=16k} - -*link_relax: - %{mrelax:--relax} - -*link_arch: - %{mmcu=*:-m%*} - -*link_data_start: - -Tdata 0x800100 - -*link_text_start: - - -*self_spec: - %{!mmcu=avr*: % -# #elif ... -# -# If no device macro is defined, AVR-LibC uses __AVR_DEV_LIB_NAME__ -# as fallback to determine the name of the device header as -# -# "avr/io" + __AVR_DEV_LIB_NAME__ + ".h" -# -# If you provide your own specs file for a device not yet known to -# AVR-LibC, you can now define the hook macro __AVR_DEV_LIB_NAME__ -# as needed so that -# -# #include -# -# will include the desired device header. For ATmega8A the supplement -# to *cpp would read -# -# -D__AVR_DEV_LIB_NAME__=m8a - - -*cpp: - -D__AVR_ATmega168PA__ -D__AVR_DEVICE_NAME__=atmega168pa - -# End of file diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega168pb b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega168pb deleted file mode 100644 index f747b7a..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega168pb +++ /dev/null @@ -1,99 +0,0 @@ -# -# Auto-generated specs for AVR device atmega168pb (core avr5, 16-bit SP) -# -# Generated by : ./gcc/config/avr/gen-avr-mmcu-specs.c -# Generated from : ./gcc/config/gcc.c -# ./gcc/config/avr/specs.h -# ./gcc/config/avr/avrlibc.h -# Used by : avr-gcc compiler driver -# Used for : building command options for sub-processes -# -# See -# for a documentation of spec files. - - -# If you intend to use an existing device specs file as a starting point -# for a new device spec file, make sure you are copying from a specs -# file for a device from the same core architecture and SP width. -# See for a description -# of how to use such own spec files. - -*avrlibc_startfile: - crtatmega168pb.o%s - -*avrlibc_devicelib: - %{!nodevicelib:-latmega168pb} - -*cc1_n_flash: - %{!mn-flash=*:-mn-flash=1} - -*cc1_rmw: - %{mrmw} - -*cc1_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*cc1_absdata: - %{mabsdata} - -*asm_arch: - -mmcu=avr5 - -*asm_relax: - %{mrelax:--mlink-relax} - -*asm_rmw: - %{mrmw} - -*asm_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*link_pmem_wrap: - %{mpmem-wrap-around: --pmem-wrap-around=16k} - -*link_relax: - %{mrelax:--relax} - -*link_arch: - %{mmcu=*:-m%*} - -*link_data_start: - -Tdata 0x800100 - -*link_text_start: - - -*self_spec: - %{!mmcu=avr*: % -# #elif ... -# -# If no device macro is defined, AVR-LibC uses __AVR_DEV_LIB_NAME__ -# as fallback to determine the name of the device header as -# -# "avr/io" + __AVR_DEV_LIB_NAME__ + ".h" -# -# If you provide your own specs file for a device not yet known to -# AVR-LibC, you can now define the hook macro __AVR_DEV_LIB_NAME__ -# as needed so that -# -# #include -# -# will include the desired device header. For ATmega8A the supplement -# to *cpp would read -# -# -D__AVR_DEV_LIB_NAME__=m8a - - -*cpp: - -D__AVR_ATmega168PB__ -D__AVR_DEVICE_NAME__=atmega168pb - -# End of file diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega169 b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega169 deleted file mode 100644 index 601faa9..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega169 +++ /dev/null @@ -1,99 +0,0 @@ -# -# Auto-generated specs for AVR device atmega169 (core avr5, 16-bit SP) -# -# Generated by : ./gcc/config/avr/gen-avr-mmcu-specs.c -# Generated from : ./gcc/config/gcc.c -# ./gcc/config/avr/specs.h -# ./gcc/config/avr/avrlibc.h -# Used by : avr-gcc compiler driver -# Used for : building command options for sub-processes -# -# See -# for a documentation of spec files. - - -# If you intend to use an existing device specs file as a starting point -# for a new device spec file, make sure you are copying from a specs -# file for a device from the same core architecture and SP width. -# See for a description -# of how to use such own spec files. - -*avrlibc_startfile: - crtatmega169.o%s - -*avrlibc_devicelib: - %{!nodevicelib:-latmega169} - -*cc1_n_flash: - %{!mn-flash=*:-mn-flash=1} - -*cc1_rmw: - %{mrmw} - -*cc1_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*cc1_absdata: - %{mabsdata} - -*asm_arch: - -mmcu=avr5 - -*asm_relax: - %{mrelax:--mlink-relax} - -*asm_rmw: - %{mrmw} - -*asm_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*link_pmem_wrap: - %{mpmem-wrap-around: --pmem-wrap-around=16k} - -*link_relax: - %{mrelax:--relax} - -*link_arch: - %{mmcu=*:-m%*} - -*link_data_start: - -Tdata 0x800100 - -*link_text_start: - - -*self_spec: - %{!mmcu=avr*: % -# #elif ... -# -# If no device macro is defined, AVR-LibC uses __AVR_DEV_LIB_NAME__ -# as fallback to determine the name of the device header as -# -# "avr/io" + __AVR_DEV_LIB_NAME__ + ".h" -# -# If you provide your own specs file for a device not yet known to -# AVR-LibC, you can now define the hook macro __AVR_DEV_LIB_NAME__ -# as needed so that -# -# #include -# -# will include the desired device header. For ATmega8A the supplement -# to *cpp would read -# -# -D__AVR_DEV_LIB_NAME__=m8a - - -*cpp: - -D__AVR_ATmega169__ -D__AVR_DEVICE_NAME__=atmega169 - -# End of file diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega169a b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega169a deleted file mode 100644 index 074aa43..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega169a +++ /dev/null @@ -1,99 +0,0 @@ -# -# Auto-generated specs for AVR device atmega169a (core avr5, 16-bit SP) -# -# Generated by : ./gcc/config/avr/gen-avr-mmcu-specs.c -# Generated from : ./gcc/config/gcc.c -# ./gcc/config/avr/specs.h -# ./gcc/config/avr/avrlibc.h -# Used by : avr-gcc compiler driver -# Used for : building command options for sub-processes -# -# See -# for a documentation of spec files. - - -# If you intend to use an existing device specs file as a starting point -# for a new device spec file, make sure you are copying from a specs -# file for a device from the same core architecture and SP width. -# See for a description -# of how to use such own spec files. - -*avrlibc_startfile: - crtatmega169a.o%s - -*avrlibc_devicelib: - %{!nodevicelib:-latmega169a} - -*cc1_n_flash: - %{!mn-flash=*:-mn-flash=1} - -*cc1_rmw: - %{mrmw} - -*cc1_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*cc1_absdata: - %{mabsdata} - -*asm_arch: - -mmcu=avr5 - -*asm_relax: - %{mrelax:--mlink-relax} - -*asm_rmw: - %{mrmw} - -*asm_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*link_pmem_wrap: - %{mpmem-wrap-around: --pmem-wrap-around=16k} - -*link_relax: - %{mrelax:--relax} - -*link_arch: - %{mmcu=*:-m%*} - -*link_data_start: - -Tdata 0x800100 - -*link_text_start: - - -*self_spec: - %{!mmcu=avr*: % -# #elif ... -# -# If no device macro is defined, AVR-LibC uses __AVR_DEV_LIB_NAME__ -# as fallback to determine the name of the device header as -# -# "avr/io" + __AVR_DEV_LIB_NAME__ + ".h" -# -# If you provide your own specs file for a device not yet known to -# AVR-LibC, you can now define the hook macro __AVR_DEV_LIB_NAME__ -# as needed so that -# -# #include -# -# will include the desired device header. For ATmega8A the supplement -# to *cpp would read -# -# -D__AVR_DEV_LIB_NAME__=m8a - - -*cpp: - -D__AVR_ATmega169A__ -D__AVR_DEVICE_NAME__=atmega169a - -# End of file diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega169p b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega169p deleted file mode 100644 index 004c6e8..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega169p +++ /dev/null @@ -1,99 +0,0 @@ -# -# Auto-generated specs for AVR device atmega169p (core avr5, 16-bit SP) -# -# Generated by : ./gcc/config/avr/gen-avr-mmcu-specs.c -# Generated from : ./gcc/config/gcc.c -# ./gcc/config/avr/specs.h -# ./gcc/config/avr/avrlibc.h -# Used by : avr-gcc compiler driver -# Used for : building command options for sub-processes -# -# See -# for a documentation of spec files. - - -# If you intend to use an existing device specs file as a starting point -# for a new device spec file, make sure you are copying from a specs -# file for a device from the same core architecture and SP width. -# See for a description -# of how to use such own spec files. - -*avrlibc_startfile: - crtatmega169p.o%s - -*avrlibc_devicelib: - %{!nodevicelib:-latmega169p} - -*cc1_n_flash: - %{!mn-flash=*:-mn-flash=1} - -*cc1_rmw: - %{mrmw} - -*cc1_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*cc1_absdata: - %{mabsdata} - -*asm_arch: - -mmcu=avr5 - -*asm_relax: - %{mrelax:--mlink-relax} - -*asm_rmw: - %{mrmw} - -*asm_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*link_pmem_wrap: - %{mpmem-wrap-around: --pmem-wrap-around=16k} - -*link_relax: - %{mrelax:--relax} - -*link_arch: - %{mmcu=*:-m%*} - -*link_data_start: - -Tdata 0x800100 - -*link_text_start: - - -*self_spec: - %{!mmcu=avr*: % -# #elif ... -# -# If no device macro is defined, AVR-LibC uses __AVR_DEV_LIB_NAME__ -# as fallback to determine the name of the device header as -# -# "avr/io" + __AVR_DEV_LIB_NAME__ + ".h" -# -# If you provide your own specs file for a device not yet known to -# AVR-LibC, you can now define the hook macro __AVR_DEV_LIB_NAME__ -# as needed so that -# -# #include -# -# will include the desired device header. For ATmega8A the supplement -# to *cpp would read -# -# -D__AVR_DEV_LIB_NAME__=m8a - - -*cpp: - -D__AVR_ATmega169P__ -D__AVR_DEVICE_NAME__=atmega169p - -# End of file diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega169pa b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega169pa deleted file mode 100644 index 86a04fd..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega169pa +++ /dev/null @@ -1,99 +0,0 @@ -# -# Auto-generated specs for AVR device atmega169pa (core avr5, 16-bit SP) -# -# Generated by : ./gcc/config/avr/gen-avr-mmcu-specs.c -# Generated from : ./gcc/config/gcc.c -# ./gcc/config/avr/specs.h -# ./gcc/config/avr/avrlibc.h -# Used by : avr-gcc compiler driver -# Used for : building command options for sub-processes -# -# See -# for a documentation of spec files. - - -# If you intend to use an existing device specs file as a starting point -# for a new device spec file, make sure you are copying from a specs -# file for a device from the same core architecture and SP width. -# See for a description -# of how to use such own spec files. - -*avrlibc_startfile: - crtatmega169pa.o%s - -*avrlibc_devicelib: - %{!nodevicelib:-latmega169pa} - -*cc1_n_flash: - %{!mn-flash=*:-mn-flash=1} - -*cc1_rmw: - %{mrmw} - -*cc1_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*cc1_absdata: - %{mabsdata} - -*asm_arch: - -mmcu=avr5 - -*asm_relax: - %{mrelax:--mlink-relax} - -*asm_rmw: - %{mrmw} - -*asm_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*link_pmem_wrap: - %{mpmem-wrap-around: --pmem-wrap-around=16k} - -*link_relax: - %{mrelax:--relax} - -*link_arch: - %{mmcu=*:-m%*} - -*link_data_start: - -Tdata 0x800100 - -*link_text_start: - - -*self_spec: - %{!mmcu=avr*: % -# #elif ... -# -# If no device macro is defined, AVR-LibC uses __AVR_DEV_LIB_NAME__ -# as fallback to determine the name of the device header as -# -# "avr/io" + __AVR_DEV_LIB_NAME__ + ".h" -# -# If you provide your own specs file for a device not yet known to -# AVR-LibC, you can now define the hook macro __AVR_DEV_LIB_NAME__ -# as needed so that -# -# #include -# -# will include the desired device header. For ATmega8A the supplement -# to *cpp would read -# -# -D__AVR_DEV_LIB_NAME__=m8a - - -*cpp: - -D__AVR_ATmega169PA__ -D__AVR_DEVICE_NAME__=atmega169pa - -# End of file diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega16a b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega16a deleted file mode 100644 index cb4e5b0..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega16a +++ /dev/null @@ -1,99 +0,0 @@ -# -# Auto-generated specs for AVR device atmega16a (core avr5, 16-bit SP) -# -# Generated by : ./gcc/config/avr/gen-avr-mmcu-specs.c -# Generated from : ./gcc/config/gcc.c -# ./gcc/config/avr/specs.h -# ./gcc/config/avr/avrlibc.h -# Used by : avr-gcc compiler driver -# Used for : building command options for sub-processes -# -# See -# for a documentation of spec files. - - -# If you intend to use an existing device specs file as a starting point -# for a new device spec file, make sure you are copying from a specs -# file for a device from the same core architecture and SP width. -# See for a description -# of how to use such own spec files. - -*avrlibc_startfile: - crtatmega16a.o%s - -*avrlibc_devicelib: - %{!nodevicelib:-latmega16a} - -*cc1_n_flash: - %{!mn-flash=*:-mn-flash=1} - -*cc1_rmw: - %{mrmw} - -*cc1_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*cc1_absdata: - %{mabsdata} - -*asm_arch: - -mmcu=avr5 - -*asm_relax: - %{mrelax:--mlink-relax} - -*asm_rmw: - %{mrmw} - -*asm_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*link_pmem_wrap: - %{mpmem-wrap-around: --pmem-wrap-around=16k} - -*link_relax: - %{mrelax:--relax} - -*link_arch: - %{mmcu=*:-m%*} - -*link_data_start: - - -*link_text_start: - - -*self_spec: - %{!mmcu=avr*: % -# #elif ... -# -# If no device macro is defined, AVR-LibC uses __AVR_DEV_LIB_NAME__ -# as fallback to determine the name of the device header as -# -# "avr/io" + __AVR_DEV_LIB_NAME__ + ".h" -# -# If you provide your own specs file for a device not yet known to -# AVR-LibC, you can now define the hook macro __AVR_DEV_LIB_NAME__ -# as needed so that -# -# #include -# -# will include the desired device header. For ATmega8A the supplement -# to *cpp would read -# -# -D__AVR_DEV_LIB_NAME__=m8a - - -*cpp: - -D__AVR_ATmega16A__ -D__AVR_DEVICE_NAME__=atmega16a - -# End of file diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega16hva b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega16hva deleted file mode 100644 index 8acc805..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega16hva +++ /dev/null @@ -1,99 +0,0 @@ -# -# Auto-generated specs for AVR device atmega16hva (core avr5, 16-bit SP) -# -# Generated by : ./gcc/config/avr/gen-avr-mmcu-specs.c -# Generated from : ./gcc/config/gcc.c -# ./gcc/config/avr/specs.h -# ./gcc/config/avr/avrlibc.h -# Used by : avr-gcc compiler driver -# Used for : building command options for sub-processes -# -# See -# for a documentation of spec files. - - -# If you intend to use an existing device specs file as a starting point -# for a new device spec file, make sure you are copying from a specs -# file for a device from the same core architecture and SP width. -# See for a description -# of how to use such own spec files. - -*avrlibc_startfile: - crtatmega16hva.o%s - -*avrlibc_devicelib: - %{!nodevicelib:-latmega16hva} - -*cc1_n_flash: - %{!mn-flash=*:-mn-flash=1} - -*cc1_rmw: - %{mrmw} - -*cc1_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*cc1_absdata: - %{mabsdata} - -*asm_arch: - -mmcu=avr5 - -*asm_relax: - %{mrelax:--mlink-relax} - -*asm_rmw: - %{mrmw} - -*asm_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*link_pmem_wrap: - %{mpmem-wrap-around: --pmem-wrap-around=16k} - -*link_relax: - %{mrelax:--relax} - -*link_arch: - %{mmcu=*:-m%*} - -*link_data_start: - -Tdata 0x800100 - -*link_text_start: - - -*self_spec: - %{!mmcu=avr*: % -# #elif ... -# -# If no device macro is defined, AVR-LibC uses __AVR_DEV_LIB_NAME__ -# as fallback to determine the name of the device header as -# -# "avr/io" + __AVR_DEV_LIB_NAME__ + ".h" -# -# If you provide your own specs file for a device not yet known to -# AVR-LibC, you can now define the hook macro __AVR_DEV_LIB_NAME__ -# as needed so that -# -# #include -# -# will include the desired device header. For ATmega8A the supplement -# to *cpp would read -# -# -D__AVR_DEV_LIB_NAME__=m8a - - -*cpp: - -D__AVR_ATmega16HVA__ -D__AVR_DEVICE_NAME__=atmega16hva - -# End of file diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega16hva2 b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega16hva2 deleted file mode 100644 index 543f924..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega16hva2 +++ /dev/null @@ -1,99 +0,0 @@ -# -# Auto-generated specs for AVR device atmega16hva2 (core avr5, 16-bit SP) -# -# Generated by : ./gcc/config/avr/gen-avr-mmcu-specs.c -# Generated from : ./gcc/config/gcc.c -# ./gcc/config/avr/specs.h -# ./gcc/config/avr/avrlibc.h -# Used by : avr-gcc compiler driver -# Used for : building command options for sub-processes -# -# See -# for a documentation of spec files. - - -# If you intend to use an existing device specs file as a starting point -# for a new device spec file, make sure you are copying from a specs -# file for a device from the same core architecture and SP width. -# See for a description -# of how to use such own spec files. - -*avrlibc_startfile: - crtatmega16hva2.o%s - -*avrlibc_devicelib: - %{!nodevicelib:-latmega16hva2} - -*cc1_n_flash: - %{!mn-flash=*:-mn-flash=1} - -*cc1_rmw: - %{mrmw} - -*cc1_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*cc1_absdata: - %{mabsdata} - -*asm_arch: - -mmcu=avr5 - -*asm_relax: - %{mrelax:--mlink-relax} - -*asm_rmw: - %{mrmw} - -*asm_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*link_pmem_wrap: - %{mpmem-wrap-around: --pmem-wrap-around=16k} - -*link_relax: - %{mrelax:--relax} - -*link_arch: - %{mmcu=*:-m%*} - -*link_data_start: - -Tdata 0x800100 - -*link_text_start: - - -*self_spec: - %{!mmcu=avr*: % -# #elif ... -# -# If no device macro is defined, AVR-LibC uses __AVR_DEV_LIB_NAME__ -# as fallback to determine the name of the device header as -# -# "avr/io" + __AVR_DEV_LIB_NAME__ + ".h" -# -# If you provide your own specs file for a device not yet known to -# AVR-LibC, you can now define the hook macro __AVR_DEV_LIB_NAME__ -# as needed so that -# -# #include -# -# will include the desired device header. For ATmega8A the supplement -# to *cpp would read -# -# -D__AVR_DEV_LIB_NAME__=m8a - - -*cpp: - -D__AVR_ATmega16HVA2__ -D__AVR_DEVICE_NAME__=atmega16hva2 - -# End of file diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega16hvb b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega16hvb deleted file mode 100644 index 68d59a9..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega16hvb +++ /dev/null @@ -1,99 +0,0 @@ -# -# Auto-generated specs for AVR device atmega16hvb (core avr5, 16-bit SP) -# -# Generated by : ./gcc/config/avr/gen-avr-mmcu-specs.c -# Generated from : ./gcc/config/gcc.c -# ./gcc/config/avr/specs.h -# ./gcc/config/avr/avrlibc.h -# Used by : avr-gcc compiler driver -# Used for : building command options for sub-processes -# -# See -# for a documentation of spec files. - - -# If you intend to use an existing device specs file as a starting point -# for a new device spec file, make sure you are copying from a specs -# file for a device from the same core architecture and SP width. -# See for a description -# of how to use such own spec files. - -*avrlibc_startfile: - crtatmega16hvb.o%s - -*avrlibc_devicelib: - %{!nodevicelib:-latmega16hvb} - -*cc1_n_flash: - %{!mn-flash=*:-mn-flash=1} - -*cc1_rmw: - %{mrmw} - -*cc1_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*cc1_absdata: - %{mabsdata} - -*asm_arch: - -mmcu=avr5 - -*asm_relax: - %{mrelax:--mlink-relax} - -*asm_rmw: - %{mrmw} - -*asm_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*link_pmem_wrap: - %{mpmem-wrap-around: --pmem-wrap-around=16k} - -*link_relax: - %{mrelax:--relax} - -*link_arch: - %{mmcu=*:-m%*} - -*link_data_start: - -Tdata 0x800100 - -*link_text_start: - - -*self_spec: - %{!mmcu=avr*: % -# #elif ... -# -# If no device macro is defined, AVR-LibC uses __AVR_DEV_LIB_NAME__ -# as fallback to determine the name of the device header as -# -# "avr/io" + __AVR_DEV_LIB_NAME__ + ".h" -# -# If you provide your own specs file for a device not yet known to -# AVR-LibC, you can now define the hook macro __AVR_DEV_LIB_NAME__ -# as needed so that -# -# #include -# -# will include the desired device header. For ATmega8A the supplement -# to *cpp would read -# -# -D__AVR_DEV_LIB_NAME__=m8a - - -*cpp: - -D__AVR_ATmega16HVB__ -D__AVR_DEVICE_NAME__=atmega16hvb - -# End of file diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega16hvbrevb b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega16hvbrevb deleted file mode 100644 index 6c5012a..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega16hvbrevb +++ /dev/null @@ -1,99 +0,0 @@ -# -# Auto-generated specs for AVR device atmega16hvbrevb (core avr5, 16-bit SP) -# -# Generated by : ./gcc/config/avr/gen-avr-mmcu-specs.c -# Generated from : ./gcc/config/gcc.c -# ./gcc/config/avr/specs.h -# ./gcc/config/avr/avrlibc.h -# Used by : avr-gcc compiler driver -# Used for : building command options for sub-processes -# -# See -# for a documentation of spec files. - - -# If you intend to use an existing device specs file as a starting point -# for a new device spec file, make sure you are copying from a specs -# file for a device from the same core architecture and SP width. -# See for a description -# of how to use such own spec files. - -*avrlibc_startfile: - crtatmega16hvbrevb.o%s - -*avrlibc_devicelib: - %{!nodevicelib:-latmega16hvbrevb} - -*cc1_n_flash: - %{!mn-flash=*:-mn-flash=1} - -*cc1_rmw: - %{mrmw} - -*cc1_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*cc1_absdata: - %{mabsdata} - -*asm_arch: - -mmcu=avr5 - -*asm_relax: - %{mrelax:--mlink-relax} - -*asm_rmw: - %{mrmw} - -*asm_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*link_pmem_wrap: - %{mpmem-wrap-around: --pmem-wrap-around=16k} - -*link_relax: - %{mrelax:--relax} - -*link_arch: - %{mmcu=*:-m%*} - -*link_data_start: - -Tdata 0x800100 - -*link_text_start: - - -*self_spec: - %{!mmcu=avr*: % -# #elif ... -# -# If no device macro is defined, AVR-LibC uses __AVR_DEV_LIB_NAME__ -# as fallback to determine the name of the device header as -# -# "avr/io" + __AVR_DEV_LIB_NAME__ + ".h" -# -# If you provide your own specs file for a device not yet known to -# AVR-LibC, you can now define the hook macro __AVR_DEV_LIB_NAME__ -# as needed so that -# -# #include -# -# will include the desired device header. For ATmega8A the supplement -# to *cpp would read -# -# -D__AVR_DEV_LIB_NAME__=m8a - - -*cpp: - -D__AVR_ATmega16HVBREVB__ -D__AVR_DEVICE_NAME__=atmega16hvbrevb - -# End of file diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega16m1 b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega16m1 deleted file mode 100644 index 61dd215..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega16m1 +++ /dev/null @@ -1,99 +0,0 @@ -# -# Auto-generated specs for AVR device atmega16m1 (core avr5, 16-bit SP) -# -# Generated by : ./gcc/config/avr/gen-avr-mmcu-specs.c -# Generated from : ./gcc/config/gcc.c -# ./gcc/config/avr/specs.h -# ./gcc/config/avr/avrlibc.h -# Used by : avr-gcc compiler driver -# Used for : building command options for sub-processes -# -# See -# for a documentation of spec files. - - -# If you intend to use an existing device specs file as a starting point -# for a new device spec file, make sure you are copying from a specs -# file for a device from the same core architecture and SP width. -# See for a description -# of how to use such own spec files. - -*avrlibc_startfile: - crtatmega16m1.o%s - -*avrlibc_devicelib: - %{!nodevicelib:-latmega16m1} - -*cc1_n_flash: - %{!mn-flash=*:-mn-flash=1} - -*cc1_rmw: - %{mrmw} - -*cc1_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*cc1_absdata: - %{mabsdata} - -*asm_arch: - -mmcu=avr5 - -*asm_relax: - %{mrelax:--mlink-relax} - -*asm_rmw: - %{mrmw} - -*asm_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*link_pmem_wrap: - %{mpmem-wrap-around: --pmem-wrap-around=16k} - -*link_relax: - %{mrelax:--relax} - -*link_arch: - %{mmcu=*:-m%*} - -*link_data_start: - -Tdata 0x800100 - -*link_text_start: - - -*self_spec: - %{!mmcu=avr*: % -# #elif ... -# -# If no device macro is defined, AVR-LibC uses __AVR_DEV_LIB_NAME__ -# as fallback to determine the name of the device header as -# -# "avr/io" + __AVR_DEV_LIB_NAME__ + ".h" -# -# If you provide your own specs file for a device not yet known to -# AVR-LibC, you can now define the hook macro __AVR_DEV_LIB_NAME__ -# as needed so that -# -# #include -# -# will include the desired device header. For ATmega8A the supplement -# to *cpp would read -# -# -D__AVR_DEV_LIB_NAME__=m8a - - -*cpp: - -D__AVR_ATmega16M1__ -D__AVR_DEVICE_NAME__=atmega16m1 - -# End of file diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega16u2 b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega16u2 deleted file mode 100644 index c0e957a..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega16u2 +++ /dev/null @@ -1,99 +0,0 @@ -# -# Auto-generated specs for AVR device atmega16u2 (core avr35, 16-bit SP) -# -# Generated by : ./gcc/config/avr/gen-avr-mmcu-specs.c -# Generated from : ./gcc/config/gcc.c -# ./gcc/config/avr/specs.h -# ./gcc/config/avr/avrlibc.h -# Used by : avr-gcc compiler driver -# Used for : building command options for sub-processes -# -# See -# for a documentation of spec files. - - -# If you intend to use an existing device specs file as a starting point -# for a new device spec file, make sure you are copying from a specs -# file for a device from the same core architecture and SP width. -# See for a description -# of how to use such own spec files. - -*avrlibc_startfile: - crtatmega16u2.o%s - -*avrlibc_devicelib: - %{!nodevicelib:-latmega16u2} - -*cc1_n_flash: - %{!mn-flash=*:-mn-flash=1} - -*cc1_rmw: - %{mrmw} - -*cc1_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*cc1_absdata: - %{mabsdata} - -*asm_arch: - -mmcu=avr35 - -*asm_relax: - %{mrelax:--mlink-relax} - -*asm_rmw: - %{mrmw} - -*asm_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*link_pmem_wrap: - %{mpmem-wrap-around: --pmem-wrap-around=16k} - -*link_relax: - %{mrelax:--relax} - -*link_arch: - %{mmcu=*:-m%*} - -*link_data_start: - -Tdata 0x800100 - -*link_text_start: - - -*self_spec: - %{!mmcu=avr*: % -# #elif ... -# -# If no device macro is defined, AVR-LibC uses __AVR_DEV_LIB_NAME__ -# as fallback to determine the name of the device header as -# -# "avr/io" + __AVR_DEV_LIB_NAME__ + ".h" -# -# If you provide your own specs file for a device not yet known to -# AVR-LibC, you can now define the hook macro __AVR_DEV_LIB_NAME__ -# as needed so that -# -# #include -# -# will include the desired device header. For ATmega8A the supplement -# to *cpp would read -# -# -D__AVR_DEV_LIB_NAME__=m8a - - -*cpp: - -D__AVR_ATmega16U2__ -D__AVR_DEVICE_NAME__=atmega16u2 - -# End of file diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega16u4 b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega16u4 deleted file mode 100644 index f602bbf..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega16u4 +++ /dev/null @@ -1,99 +0,0 @@ -# -# Auto-generated specs for AVR device atmega16u4 (core avr5, 16-bit SP) -# -# Generated by : ./gcc/config/avr/gen-avr-mmcu-specs.c -# Generated from : ./gcc/config/gcc.c -# ./gcc/config/avr/specs.h -# ./gcc/config/avr/avrlibc.h -# Used by : avr-gcc compiler driver -# Used for : building command options for sub-processes -# -# See -# for a documentation of spec files. - - -# If you intend to use an existing device specs file as a starting point -# for a new device spec file, make sure you are copying from a specs -# file for a device from the same core architecture and SP width. -# See for a description -# of how to use such own spec files. - -*avrlibc_startfile: - crtatmega16u4.o%s - -*avrlibc_devicelib: - %{!nodevicelib:-latmega16u4} - -*cc1_n_flash: - %{!mn-flash=*:-mn-flash=1} - -*cc1_rmw: - %{mrmw} - -*cc1_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*cc1_absdata: - %{mabsdata} - -*asm_arch: - -mmcu=avr5 - -*asm_relax: - %{mrelax:--mlink-relax} - -*asm_rmw: - %{mrmw} - -*asm_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*link_pmem_wrap: - %{mpmem-wrap-around: --pmem-wrap-around=16k} - -*link_relax: - %{mrelax:--relax} - -*link_arch: - %{mmcu=*:-m%*} - -*link_data_start: - -Tdata 0x800100 - -*link_text_start: - - -*self_spec: - %{!mmcu=avr*: % -# #elif ... -# -# If no device macro is defined, AVR-LibC uses __AVR_DEV_LIB_NAME__ -# as fallback to determine the name of the device header as -# -# "avr/io" + __AVR_DEV_LIB_NAME__ + ".h" -# -# If you provide your own specs file for a device not yet known to -# AVR-LibC, you can now define the hook macro __AVR_DEV_LIB_NAME__ -# as needed so that -# -# #include -# -# will include the desired device header. For ATmega8A the supplement -# to *cpp would read -# -# -D__AVR_DEV_LIB_NAME__=m8a - - -*cpp: - -D__AVR_ATmega16U4__ -D__AVR_DEVICE_NAME__=atmega16u4 - -# End of file diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega2560 b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega2560 deleted file mode 100644 index 5f235df..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega2560 +++ /dev/null @@ -1,99 +0,0 @@ -# -# Auto-generated specs for AVR device atmega2560 (core avr6, 16-bit SP) -# -# Generated by : ./gcc/config/avr/gen-avr-mmcu-specs.c -# Generated from : ./gcc/config/gcc.c -# ./gcc/config/avr/specs.h -# ./gcc/config/avr/avrlibc.h -# Used by : avr-gcc compiler driver -# Used for : building command options for sub-processes -# -# See -# for a documentation of spec files. - - -# If you intend to use an existing device specs file as a starting point -# for a new device spec file, make sure you are copying from a specs -# file for a device from the same core architecture and SP width. -# See for a description -# of how to use such own spec files. - -*avrlibc_startfile: - crtatmega2560.o%s - -*avrlibc_devicelib: - %{!nodevicelib:-latmega2560} - -*cc1_n_flash: - %{!mn-flash=*:-mn-flash=4} - -*cc1_rmw: - %{mrmw} - -*cc1_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*cc1_absdata: - %{mabsdata} - -*asm_arch: - -mmcu=avr6 - -*asm_relax: - %{mrelax:--mlink-relax} - -*asm_rmw: - %{mrmw} - -*asm_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*link_pmem_wrap: - - -*link_relax: - %{mrelax:--relax} - -*link_arch: - %{mmcu=*:-m%*} - -*link_data_start: - -Tdata 0x800200 - -*link_text_start: - - -*self_spec: - %{!mmcu=avr*: % -# #elif ... -# -# If no device macro is defined, AVR-LibC uses __AVR_DEV_LIB_NAME__ -# as fallback to determine the name of the device header as -# -# "avr/io" + __AVR_DEV_LIB_NAME__ + ".h" -# -# If you provide your own specs file for a device not yet known to -# AVR-LibC, you can now define the hook macro __AVR_DEV_LIB_NAME__ -# as needed so that -# -# #include -# -# will include the desired device header. For ATmega8A the supplement -# to *cpp would read -# -# -D__AVR_DEV_LIB_NAME__=m8a - - -*cpp: - -D__AVR_ATmega2560__ -D__AVR_DEVICE_NAME__=atmega2560 - -# End of file diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega2561 b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega2561 deleted file mode 100644 index 2a2fdbc..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega2561 +++ /dev/null @@ -1,99 +0,0 @@ -# -# Auto-generated specs for AVR device atmega2561 (core avr6, 16-bit SP) -# -# Generated by : ./gcc/config/avr/gen-avr-mmcu-specs.c -# Generated from : ./gcc/config/gcc.c -# ./gcc/config/avr/specs.h -# ./gcc/config/avr/avrlibc.h -# Used by : avr-gcc compiler driver -# Used for : building command options for sub-processes -# -# See -# for a documentation of spec files. - - -# If you intend to use an existing device specs file as a starting point -# for a new device spec file, make sure you are copying from a specs -# file for a device from the same core architecture and SP width. -# See for a description -# of how to use such own spec files. - -*avrlibc_startfile: - crtatmega2561.o%s - -*avrlibc_devicelib: - %{!nodevicelib:-latmega2561} - -*cc1_n_flash: - %{!mn-flash=*:-mn-flash=4} - -*cc1_rmw: - %{mrmw} - -*cc1_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*cc1_absdata: - %{mabsdata} - -*asm_arch: - -mmcu=avr6 - -*asm_relax: - %{mrelax:--mlink-relax} - -*asm_rmw: - %{mrmw} - -*asm_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*link_pmem_wrap: - - -*link_relax: - %{mrelax:--relax} - -*link_arch: - %{mmcu=*:-m%*} - -*link_data_start: - -Tdata 0x800200 - -*link_text_start: - - -*self_spec: - %{!mmcu=avr*: % -# #elif ... -# -# If no device macro is defined, AVR-LibC uses __AVR_DEV_LIB_NAME__ -# as fallback to determine the name of the device header as -# -# "avr/io" + __AVR_DEV_LIB_NAME__ + ".h" -# -# If you provide your own specs file for a device not yet known to -# AVR-LibC, you can now define the hook macro __AVR_DEV_LIB_NAME__ -# as needed so that -# -# #include -# -# will include the desired device header. For ATmega8A the supplement -# to *cpp would read -# -# -D__AVR_DEV_LIB_NAME__=m8a - - -*cpp: - -D__AVR_ATmega2561__ -D__AVR_DEVICE_NAME__=atmega2561 - -# End of file diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega2564rfr2 b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega2564rfr2 deleted file mode 100644 index 7c3fff7..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega2564rfr2 +++ /dev/null @@ -1,99 +0,0 @@ -# -# Auto-generated specs for AVR device atmega2564rfr2 (core avr6, 16-bit SP) -# -# Generated by : ./gcc/config/avr/gen-avr-mmcu-specs.c -# Generated from : ./gcc/config/gcc.c -# ./gcc/config/avr/specs.h -# ./gcc/config/avr/avrlibc.h -# Used by : avr-gcc compiler driver -# Used for : building command options for sub-processes -# -# See -# for a documentation of spec files. - - -# If you intend to use an existing device specs file as a starting point -# for a new device spec file, make sure you are copying from a specs -# file for a device from the same core architecture and SP width. -# See for a description -# of how to use such own spec files. - -*avrlibc_startfile: - crtatmega2564rfr2.o%s - -*avrlibc_devicelib: - %{!nodevicelib:-latmega2564rfr2} - -*cc1_n_flash: - %{!mn-flash=*:-mn-flash=4} - -*cc1_rmw: - %{mrmw} - -*cc1_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*cc1_absdata: - %{mabsdata} - -*asm_arch: - -mmcu=avr6 - -*asm_relax: - %{mrelax:--mlink-relax} - -*asm_rmw: - %{mrmw} - -*asm_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*link_pmem_wrap: - - -*link_relax: - %{mrelax:--relax} - -*link_arch: - %{mmcu=*:-m%*} - -*link_data_start: - -Tdata 0x800200 - -*link_text_start: - - -*self_spec: - %{!mmcu=avr*: % -# #elif ... -# -# If no device macro is defined, AVR-LibC uses __AVR_DEV_LIB_NAME__ -# as fallback to determine the name of the device header as -# -# "avr/io" + __AVR_DEV_LIB_NAME__ + ".h" -# -# If you provide your own specs file for a device not yet known to -# AVR-LibC, you can now define the hook macro __AVR_DEV_LIB_NAME__ -# as needed so that -# -# #include -# -# will include the desired device header. For ATmega8A the supplement -# to *cpp would read -# -# -D__AVR_DEV_LIB_NAME__=m8a - - -*cpp: - -D__AVR_ATmega2564RFR2__ -D__AVR_DEVICE_NAME__=atmega2564rfr2 - -# End of file diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega256rfr2 b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega256rfr2 deleted file mode 100644 index b93ac1b..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega256rfr2 +++ /dev/null @@ -1,99 +0,0 @@ -# -# Auto-generated specs for AVR device atmega256rfr2 (core avr6, 16-bit SP) -# -# Generated by : ./gcc/config/avr/gen-avr-mmcu-specs.c -# Generated from : ./gcc/config/gcc.c -# ./gcc/config/avr/specs.h -# ./gcc/config/avr/avrlibc.h -# Used by : avr-gcc compiler driver -# Used for : building command options for sub-processes -# -# See -# for a documentation of spec files. - - -# If you intend to use an existing device specs file as a starting point -# for a new device spec file, make sure you are copying from a specs -# file for a device from the same core architecture and SP width. -# See for a description -# of how to use such own spec files. - -*avrlibc_startfile: - crtatmega256rfr2.o%s - -*avrlibc_devicelib: - %{!nodevicelib:-latmega256rfr2} - -*cc1_n_flash: - %{!mn-flash=*:-mn-flash=4} - -*cc1_rmw: - %{mrmw} - -*cc1_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*cc1_absdata: - %{mabsdata} - -*asm_arch: - -mmcu=avr6 - -*asm_relax: - %{mrelax:--mlink-relax} - -*asm_rmw: - %{mrmw} - -*asm_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*link_pmem_wrap: - - -*link_relax: - %{mrelax:--relax} - -*link_arch: - %{mmcu=*:-m%*} - -*link_data_start: - -Tdata 0x800200 - -*link_text_start: - - -*self_spec: - %{!mmcu=avr*: % -# #elif ... -# -# If no device macro is defined, AVR-LibC uses __AVR_DEV_LIB_NAME__ -# as fallback to determine the name of the device header as -# -# "avr/io" + __AVR_DEV_LIB_NAME__ + ".h" -# -# If you provide your own specs file for a device not yet known to -# AVR-LibC, you can now define the hook macro __AVR_DEV_LIB_NAME__ -# as needed so that -# -# #include -# -# will include the desired device header. For ATmega8A the supplement -# to *cpp would read -# -# -D__AVR_DEV_LIB_NAME__=m8a - - -*cpp: - -D__AVR_ATmega256RFR2__ -D__AVR_DEVICE_NAME__=atmega256rfr2 - -# End of file diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega32 b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega32 deleted file mode 100644 index f23e815..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega32 +++ /dev/null @@ -1,99 +0,0 @@ -# -# Auto-generated specs for AVR device atmega32 (core avr5, 16-bit SP) -# -# Generated by : ./gcc/config/avr/gen-avr-mmcu-specs.c -# Generated from : ./gcc/config/gcc.c -# ./gcc/config/avr/specs.h -# ./gcc/config/avr/avrlibc.h -# Used by : avr-gcc compiler driver -# Used for : building command options for sub-processes -# -# See -# for a documentation of spec files. - - -# If you intend to use an existing device specs file as a starting point -# for a new device spec file, make sure you are copying from a specs -# file for a device from the same core architecture and SP width. -# See for a description -# of how to use such own spec files. - -*avrlibc_startfile: - crtatmega32.o%s - -*avrlibc_devicelib: - %{!nodevicelib:-latmega32} - -*cc1_n_flash: - %{!mn-flash=*:-mn-flash=1} - -*cc1_rmw: - %{mrmw} - -*cc1_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*cc1_absdata: - %{mabsdata} - -*asm_arch: - -mmcu=avr5 - -*asm_relax: - %{mrelax:--mlink-relax} - -*asm_rmw: - %{mrmw} - -*asm_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*link_pmem_wrap: - %{mpmem-wrap-around: --pmem-wrap-around=32k} - -*link_relax: - %{mrelax:--relax} - -*link_arch: - %{mmcu=*:-m%*} - -*link_data_start: - - -*link_text_start: - - -*self_spec: - %{!mmcu=avr*: % -# #elif ... -# -# If no device macro is defined, AVR-LibC uses __AVR_DEV_LIB_NAME__ -# as fallback to determine the name of the device header as -# -# "avr/io" + __AVR_DEV_LIB_NAME__ + ".h" -# -# If you provide your own specs file for a device not yet known to -# AVR-LibC, you can now define the hook macro __AVR_DEV_LIB_NAME__ -# as needed so that -# -# #include -# -# will include the desired device header. For ATmega8A the supplement -# to *cpp would read -# -# -D__AVR_DEV_LIB_NAME__=m8a - - -*cpp: - -D__AVR_ATmega32__ -D__AVR_DEVICE_NAME__=atmega32 - -# End of file diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega3208 b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega3208 deleted file mode 100644 index cc49dae..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega3208 +++ /dev/null @@ -1,104 +0,0 @@ -# -# Auto-generated specs for AVR device atmega3208 (core avrxmega3, 16-bit SP) -# -# Generated by : ./gcc/config/avr/gen-avr-mmcu-specs.c -# Generated from : ./gcc/config/gcc.c -# ./gcc/config/avr/specs.h -# ./gcc/config/avr/avrlibc.h -# Used by : avr-gcc compiler driver -# Used for : building command options for sub-processes -# -# See -# for a documentation of spec files. - - -# If you intend to use an existing device specs file as a starting point -# for a new device spec file, make sure you are copying from a specs -# file for a device from the same core architecture and SP width. -# See for a description -# of how to use such own spec files. - -*avrlibc_startfile: - crtatmega3208.o%s - -*avrlibc_devicelib: - %{!nodevicelib:-latmega3208} - -*cc1_n_flash: - %{!mn-flash=*:-mn-flash=1} - -*cc1_rmw: - %{mrmw} - -*cc1_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*cc1_absdata: - %{mabsdata} - -*asm_arch: - -mmcu=avrxmega3 - -*asm_relax: - %{mrelax:--mlink-relax} - -*asm_rmw: - %{mrmw} - -*asm_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*link_pmem_wrap: - %{mpmem-wrap-around: --pmem-wrap-around=32k} - -*link_relax: - %{mrelax:--relax} - -*link_arch: - %{mmcu=*:-m%*} - -*link_data_start: - -Tdata 0x803000 - -*link_text_start: - - -*self_spec: - %{!mmcu=avr*: % -# #elif ... -# -# If no device macro is defined, AVR-LibC uses __AVR_DEV_LIB_NAME__ -# as fallback to determine the name of the device header as -# -# "avr/io" + __AVR_DEV_LIB_NAME__ + ".h" -# -# If you provide your own specs file for a device not yet known to -# AVR-LibC, you can now define the hook macro __AVR_DEV_LIB_NAME__ -# as needed so that -# -# #include -# -# will include the desired device header. For ATmega8A the supplement -# to *cpp would read -# -# -D__AVR_DEV_LIB_NAME__=m8a - - -*cpp: - -D__AVR_ATmega3208__ -D__AVR_DEVICE_NAME__=atmega3208 -D__AVR_DEV_LIB_NAME__=m3208 - -%rename link old_link - -*link: - %(old_link)--defsym=__RODATA_PM_OFFSET__=0x4000 - -# End of file diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega3209 b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega3209 deleted file mode 100644 index 87e09b2..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega3209 +++ /dev/null @@ -1,104 +0,0 @@ -# -# Auto-generated specs for AVR device atmega3209 (core avrxmega3, 16-bit SP) -# -# Generated by : ./gcc/config/avr/gen-avr-mmcu-specs.c -# Generated from : ./gcc/config/gcc.c -# ./gcc/config/avr/specs.h -# ./gcc/config/avr/avrlibc.h -# Used by : avr-gcc compiler driver -# Used for : building command options for sub-processes -# -# See -# for a documentation of spec files. - - -# If you intend to use an existing device specs file as a starting point -# for a new device spec file, make sure you are copying from a specs -# file for a device from the same core architecture and SP width. -# See for a description -# of how to use such own spec files. - -*avrlibc_startfile: - crtatmega3209.o%s - -*avrlibc_devicelib: - %{!nodevicelib:-latmega3209} - -*cc1_n_flash: - %{!mn-flash=*:-mn-flash=1} - -*cc1_rmw: - %{mrmw} - -*cc1_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*cc1_absdata: - %{mabsdata} - -*asm_arch: - -mmcu=avrxmega3 - -*asm_relax: - %{mrelax:--mlink-relax} - -*asm_rmw: - %{mrmw} - -*asm_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*link_pmem_wrap: - %{mpmem-wrap-around: --pmem-wrap-around=32k} - -*link_relax: - %{mrelax:--relax} - -*link_arch: - %{mmcu=*:-m%*} - -*link_data_start: - -Tdata 0x803000 - -*link_text_start: - - -*self_spec: - %{!mmcu=avr*: % -# #elif ... -# -# If no device macro is defined, AVR-LibC uses __AVR_DEV_LIB_NAME__ -# as fallback to determine the name of the device header as -# -# "avr/io" + __AVR_DEV_LIB_NAME__ + ".h" -# -# If you provide your own specs file for a device not yet known to -# AVR-LibC, you can now define the hook macro __AVR_DEV_LIB_NAME__ -# as needed so that -# -# #include -# -# will include the desired device header. For ATmega8A the supplement -# to *cpp would read -# -# -D__AVR_DEV_LIB_NAME__=m8a - - -*cpp: - -D__AVR_ATmega3209__ -D__AVR_DEVICE_NAME__=atmega3209 -D__AVR_DEV_LIB_NAME__=m3209 - -%rename link old_link - -*link: - %(old_link)--defsym=__RODATA_PM_OFFSET__=0x4000 - -# End of file diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega323 b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega323 deleted file mode 100644 index 61f9398..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega323 +++ /dev/null @@ -1,99 +0,0 @@ -# -# Auto-generated specs for AVR device atmega323 (core avr5, 16-bit SP) -# -# Generated by : ./gcc/config/avr/gen-avr-mmcu-specs.c -# Generated from : ./gcc/config/gcc.c -# ./gcc/config/avr/specs.h -# ./gcc/config/avr/avrlibc.h -# Used by : avr-gcc compiler driver -# Used for : building command options for sub-processes -# -# See -# for a documentation of spec files. - - -# If you intend to use an existing device specs file as a starting point -# for a new device spec file, make sure you are copying from a specs -# file for a device from the same core architecture and SP width. -# See for a description -# of how to use such own spec files. - -*avrlibc_startfile: - crtatmega323.o%s - -*avrlibc_devicelib: - %{!nodevicelib:-latmega323} - -*cc1_n_flash: - %{!mn-flash=*:-mn-flash=1} - -*cc1_rmw: - %{mrmw} - -*cc1_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*cc1_absdata: - %{mabsdata} - -*asm_arch: - -mmcu=avr5 - -*asm_relax: - %{mrelax:--mlink-relax} - -*asm_rmw: - %{mrmw} - -*asm_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*link_pmem_wrap: - %{mpmem-wrap-around: --pmem-wrap-around=32k} - -*link_relax: - %{mrelax:--relax} - -*link_arch: - %{mmcu=*:-m%*} - -*link_data_start: - - -*link_text_start: - - -*self_spec: - %{!mmcu=avr*: % -# #elif ... -# -# If no device macro is defined, AVR-LibC uses __AVR_DEV_LIB_NAME__ -# as fallback to determine the name of the device header as -# -# "avr/io" + __AVR_DEV_LIB_NAME__ + ".h" -# -# If you provide your own specs file for a device not yet known to -# AVR-LibC, you can now define the hook macro __AVR_DEV_LIB_NAME__ -# as needed so that -# -# #include -# -# will include the desired device header. For ATmega8A the supplement -# to *cpp would read -# -# -D__AVR_DEV_LIB_NAME__=m8a - - -*cpp: - -D__AVR_ATmega323__ -D__AVR_DEVICE_NAME__=atmega323 - -# End of file diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega324a b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega324a deleted file mode 100644 index 12d2fbb..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega324a +++ /dev/null @@ -1,99 +0,0 @@ -# -# Auto-generated specs for AVR device atmega324a (core avr5, 16-bit SP) -# -# Generated by : ./gcc/config/avr/gen-avr-mmcu-specs.c -# Generated from : ./gcc/config/gcc.c -# ./gcc/config/avr/specs.h -# ./gcc/config/avr/avrlibc.h -# Used by : avr-gcc compiler driver -# Used for : building command options for sub-processes -# -# See -# for a documentation of spec files. - - -# If you intend to use an existing device specs file as a starting point -# for a new device spec file, make sure you are copying from a specs -# file for a device from the same core architecture and SP width. -# See for a description -# of how to use such own spec files. - -*avrlibc_startfile: - crtatmega324a.o%s - -*avrlibc_devicelib: - %{!nodevicelib:-latmega324a} - -*cc1_n_flash: - %{!mn-flash=*:-mn-flash=1} - -*cc1_rmw: - %{mrmw} - -*cc1_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*cc1_absdata: - %{mabsdata} - -*asm_arch: - -mmcu=avr5 - -*asm_relax: - %{mrelax:--mlink-relax} - -*asm_rmw: - %{mrmw} - -*asm_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*link_pmem_wrap: - %{mpmem-wrap-around: --pmem-wrap-around=32k} - -*link_relax: - %{mrelax:--relax} - -*link_arch: - %{mmcu=*:-m%*} - -*link_data_start: - -Tdata 0x800100 - -*link_text_start: - - -*self_spec: - %{!mmcu=avr*: % -# #elif ... -# -# If no device macro is defined, AVR-LibC uses __AVR_DEV_LIB_NAME__ -# as fallback to determine the name of the device header as -# -# "avr/io" + __AVR_DEV_LIB_NAME__ + ".h" -# -# If you provide your own specs file for a device not yet known to -# AVR-LibC, you can now define the hook macro __AVR_DEV_LIB_NAME__ -# as needed so that -# -# #include -# -# will include the desired device header. For ATmega8A the supplement -# to *cpp would read -# -# -D__AVR_DEV_LIB_NAME__=m8a - - -*cpp: - -D__AVR_ATmega324A__ -D__AVR_DEVICE_NAME__=atmega324a - -# End of file diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega324p b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega324p deleted file mode 100644 index 1f79cd7..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega324p +++ /dev/null @@ -1,99 +0,0 @@ -# -# Auto-generated specs for AVR device atmega324p (core avr5, 16-bit SP) -# -# Generated by : ./gcc/config/avr/gen-avr-mmcu-specs.c -# Generated from : ./gcc/config/gcc.c -# ./gcc/config/avr/specs.h -# ./gcc/config/avr/avrlibc.h -# Used by : avr-gcc compiler driver -# Used for : building command options for sub-processes -# -# See -# for a documentation of spec files. - - -# If you intend to use an existing device specs file as a starting point -# for a new device spec file, make sure you are copying from a specs -# file for a device from the same core architecture and SP width. -# See for a description -# of how to use such own spec files. - -*avrlibc_startfile: - crtatmega324p.o%s - -*avrlibc_devicelib: - %{!nodevicelib:-latmega324p} - -*cc1_n_flash: - %{!mn-flash=*:-mn-flash=1} - -*cc1_rmw: - %{mrmw} - -*cc1_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*cc1_absdata: - %{mabsdata} - -*asm_arch: - -mmcu=avr5 - -*asm_relax: - %{mrelax:--mlink-relax} - -*asm_rmw: - %{mrmw} - -*asm_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*link_pmem_wrap: - %{mpmem-wrap-around: --pmem-wrap-around=32k} - -*link_relax: - %{mrelax:--relax} - -*link_arch: - %{mmcu=*:-m%*} - -*link_data_start: - -Tdata 0x800100 - -*link_text_start: - - -*self_spec: - %{!mmcu=avr*: % -# #elif ... -# -# If no device macro is defined, AVR-LibC uses __AVR_DEV_LIB_NAME__ -# as fallback to determine the name of the device header as -# -# "avr/io" + __AVR_DEV_LIB_NAME__ + ".h" -# -# If you provide your own specs file for a device not yet known to -# AVR-LibC, you can now define the hook macro __AVR_DEV_LIB_NAME__ -# as needed so that -# -# #include -# -# will include the desired device header. For ATmega8A the supplement -# to *cpp would read -# -# -D__AVR_DEV_LIB_NAME__=m8a - - -*cpp: - -D__AVR_ATmega324P__ -D__AVR_DEVICE_NAME__=atmega324p - -# End of file diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega324pa b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega324pa deleted file mode 100644 index 1e650fc..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega324pa +++ /dev/null @@ -1,99 +0,0 @@ -# -# Auto-generated specs for AVR device atmega324pa (core avr5, 16-bit SP) -# -# Generated by : ./gcc/config/avr/gen-avr-mmcu-specs.c -# Generated from : ./gcc/config/gcc.c -# ./gcc/config/avr/specs.h -# ./gcc/config/avr/avrlibc.h -# Used by : avr-gcc compiler driver -# Used for : building command options for sub-processes -# -# See -# for a documentation of spec files. - - -# If you intend to use an existing device specs file as a starting point -# for a new device spec file, make sure you are copying from a specs -# file for a device from the same core architecture and SP width. -# See for a description -# of how to use such own spec files. - -*avrlibc_startfile: - crtatmega324pa.o%s - -*avrlibc_devicelib: - %{!nodevicelib:-latmega324pa} - -*cc1_n_flash: - %{!mn-flash=*:-mn-flash=1} - -*cc1_rmw: - %{mrmw} - -*cc1_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*cc1_absdata: - %{mabsdata} - -*asm_arch: - -mmcu=avr5 - -*asm_relax: - %{mrelax:--mlink-relax} - -*asm_rmw: - %{mrmw} - -*asm_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*link_pmem_wrap: - %{mpmem-wrap-around: --pmem-wrap-around=32k} - -*link_relax: - %{mrelax:--relax} - -*link_arch: - %{mmcu=*:-m%*} - -*link_data_start: - -Tdata 0x800100 - -*link_text_start: - - -*self_spec: - %{!mmcu=avr*: % -# #elif ... -# -# If no device macro is defined, AVR-LibC uses __AVR_DEV_LIB_NAME__ -# as fallback to determine the name of the device header as -# -# "avr/io" + __AVR_DEV_LIB_NAME__ + ".h" -# -# If you provide your own specs file for a device not yet known to -# AVR-LibC, you can now define the hook macro __AVR_DEV_LIB_NAME__ -# as needed so that -# -# #include -# -# will include the desired device header. For ATmega8A the supplement -# to *cpp would read -# -# -D__AVR_DEV_LIB_NAME__=m8a - - -*cpp: - -D__AVR_ATmega324PA__ -D__AVR_DEVICE_NAME__=atmega324pa - -# End of file diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega324pb b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega324pb deleted file mode 100644 index 6c0df76..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega324pb +++ /dev/null @@ -1,99 +0,0 @@ -# -# Auto-generated specs for AVR device atmega324pb (core avr5, 16-bit SP) -# -# Generated by : ./gcc/config/avr/gen-avr-mmcu-specs.c -# Generated from : ./gcc/config/gcc.c -# ./gcc/config/avr/specs.h -# ./gcc/config/avr/avrlibc.h -# Used by : avr-gcc compiler driver -# Used for : building command options for sub-processes -# -# See -# for a documentation of spec files. - - -# If you intend to use an existing device specs file as a starting point -# for a new device spec file, make sure you are copying from a specs -# file for a device from the same core architecture and SP width. -# See for a description -# of how to use such own spec files. - -*avrlibc_startfile: - crtatmega324pb.o%s - -*avrlibc_devicelib: - %{!nodevicelib:-latmega324pb} - -*cc1_n_flash: - %{!mn-flash=*:-mn-flash=1} - -*cc1_rmw: - %{mrmw} - -*cc1_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*cc1_absdata: - %{mabsdata} - -*asm_arch: - -mmcu=avr5 - -*asm_relax: - %{mrelax:--mlink-relax} - -*asm_rmw: - %{mrmw} - -*asm_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*link_pmem_wrap: - %{mpmem-wrap-around: --pmem-wrap-around=32k} - -*link_relax: - %{mrelax:--relax} - -*link_arch: - %{mmcu=*:-m%*} - -*link_data_start: - -Tdata 0x800100 - -*link_text_start: - - -*self_spec: - %{!mmcu=avr*: % -# #elif ... -# -# If no device macro is defined, AVR-LibC uses __AVR_DEV_LIB_NAME__ -# as fallback to determine the name of the device header as -# -# "avr/io" + __AVR_DEV_LIB_NAME__ + ".h" -# -# If you provide your own specs file for a device not yet known to -# AVR-LibC, you can now define the hook macro __AVR_DEV_LIB_NAME__ -# as needed so that -# -# #include -# -# will include the desired device header. For ATmega8A the supplement -# to *cpp would read -# -# -D__AVR_DEV_LIB_NAME__=m8a - - -*cpp: - -D__AVR_ATmega324PB__ -D__AVR_DEVICE_NAME__=atmega324pb -D__AVR_DEV_LIB_NAME__=m324pb - -# End of file diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega325 b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega325 deleted file mode 100644 index dfb3702..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega325 +++ /dev/null @@ -1,99 +0,0 @@ -# -# Auto-generated specs for AVR device atmega325 (core avr5, 16-bit SP) -# -# Generated by : ./gcc/config/avr/gen-avr-mmcu-specs.c -# Generated from : ./gcc/config/gcc.c -# ./gcc/config/avr/specs.h -# ./gcc/config/avr/avrlibc.h -# Used by : avr-gcc compiler driver -# Used for : building command options for sub-processes -# -# See -# for a documentation of spec files. - - -# If you intend to use an existing device specs file as a starting point -# for a new device spec file, make sure you are copying from a specs -# file for a device from the same core architecture and SP width. -# See for a description -# of how to use such own spec files. - -*avrlibc_startfile: - crtatmega325.o%s - -*avrlibc_devicelib: - %{!nodevicelib:-latmega325} - -*cc1_n_flash: - %{!mn-flash=*:-mn-flash=1} - -*cc1_rmw: - %{mrmw} - -*cc1_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*cc1_absdata: - %{mabsdata} - -*asm_arch: - -mmcu=avr5 - -*asm_relax: - %{mrelax:--mlink-relax} - -*asm_rmw: - %{mrmw} - -*asm_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*link_pmem_wrap: - %{mpmem-wrap-around: --pmem-wrap-around=32k} - -*link_relax: - %{mrelax:--relax} - -*link_arch: - %{mmcu=*:-m%*} - -*link_data_start: - -Tdata 0x800100 - -*link_text_start: - - -*self_spec: - %{!mmcu=avr*: % -# #elif ... -# -# If no device macro is defined, AVR-LibC uses __AVR_DEV_LIB_NAME__ -# as fallback to determine the name of the device header as -# -# "avr/io" + __AVR_DEV_LIB_NAME__ + ".h" -# -# If you provide your own specs file for a device not yet known to -# AVR-LibC, you can now define the hook macro __AVR_DEV_LIB_NAME__ -# as needed so that -# -# #include -# -# will include the desired device header. For ATmega8A the supplement -# to *cpp would read -# -# -D__AVR_DEV_LIB_NAME__=m8a - - -*cpp: - -D__AVR_ATmega325__ -D__AVR_DEVICE_NAME__=atmega325 - -# End of file diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega3250 b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega3250 deleted file mode 100644 index ec1f8c4..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega3250 +++ /dev/null @@ -1,99 +0,0 @@ -# -# Auto-generated specs for AVR device atmega3250 (core avr5, 16-bit SP) -# -# Generated by : ./gcc/config/avr/gen-avr-mmcu-specs.c -# Generated from : ./gcc/config/gcc.c -# ./gcc/config/avr/specs.h -# ./gcc/config/avr/avrlibc.h -# Used by : avr-gcc compiler driver -# Used for : building command options for sub-processes -# -# See -# for a documentation of spec files. - - -# If you intend to use an existing device specs file as a starting point -# for a new device spec file, make sure you are copying from a specs -# file for a device from the same core architecture and SP width. -# See for a description -# of how to use such own spec files. - -*avrlibc_startfile: - crtatmega3250.o%s - -*avrlibc_devicelib: - %{!nodevicelib:-latmega3250} - -*cc1_n_flash: - %{!mn-flash=*:-mn-flash=1} - -*cc1_rmw: - %{mrmw} - -*cc1_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*cc1_absdata: - %{mabsdata} - -*asm_arch: - -mmcu=avr5 - -*asm_relax: - %{mrelax:--mlink-relax} - -*asm_rmw: - %{mrmw} - -*asm_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*link_pmem_wrap: - %{mpmem-wrap-around: --pmem-wrap-around=32k} - -*link_relax: - %{mrelax:--relax} - -*link_arch: - %{mmcu=*:-m%*} - -*link_data_start: - -Tdata 0x800100 - -*link_text_start: - - -*self_spec: - %{!mmcu=avr*: % -# #elif ... -# -# If no device macro is defined, AVR-LibC uses __AVR_DEV_LIB_NAME__ -# as fallback to determine the name of the device header as -# -# "avr/io" + __AVR_DEV_LIB_NAME__ + ".h" -# -# If you provide your own specs file for a device not yet known to -# AVR-LibC, you can now define the hook macro __AVR_DEV_LIB_NAME__ -# as needed so that -# -# #include -# -# will include the desired device header. For ATmega8A the supplement -# to *cpp would read -# -# -D__AVR_DEV_LIB_NAME__=m8a - - -*cpp: - -D__AVR_ATmega3250__ -D__AVR_DEVICE_NAME__=atmega3250 - -# End of file diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega3250a b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega3250a deleted file mode 100644 index f9f2d96..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega3250a +++ /dev/null @@ -1,99 +0,0 @@ -# -# Auto-generated specs for AVR device atmega3250a (core avr5, 16-bit SP) -# -# Generated by : ./gcc/config/avr/gen-avr-mmcu-specs.c -# Generated from : ./gcc/config/gcc.c -# ./gcc/config/avr/specs.h -# ./gcc/config/avr/avrlibc.h -# Used by : avr-gcc compiler driver -# Used for : building command options for sub-processes -# -# See -# for a documentation of spec files. - - -# If you intend to use an existing device specs file as a starting point -# for a new device spec file, make sure you are copying from a specs -# file for a device from the same core architecture and SP width. -# See for a description -# of how to use such own spec files. - -*avrlibc_startfile: - crtatmega3250a.o%s - -*avrlibc_devicelib: - %{!nodevicelib:-latmega3250a} - -*cc1_n_flash: - %{!mn-flash=*:-mn-flash=1} - -*cc1_rmw: - %{mrmw} - -*cc1_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*cc1_absdata: - %{mabsdata} - -*asm_arch: - -mmcu=avr5 - -*asm_relax: - %{mrelax:--mlink-relax} - -*asm_rmw: - %{mrmw} - -*asm_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*link_pmem_wrap: - %{mpmem-wrap-around: --pmem-wrap-around=32k} - -*link_relax: - %{mrelax:--relax} - -*link_arch: - %{mmcu=*:-m%*} - -*link_data_start: - -Tdata 0x800100 - -*link_text_start: - - -*self_spec: - %{!mmcu=avr*: % -# #elif ... -# -# If no device macro is defined, AVR-LibC uses __AVR_DEV_LIB_NAME__ -# as fallback to determine the name of the device header as -# -# "avr/io" + __AVR_DEV_LIB_NAME__ + ".h" -# -# If you provide your own specs file for a device not yet known to -# AVR-LibC, you can now define the hook macro __AVR_DEV_LIB_NAME__ -# as needed so that -# -# #include -# -# will include the desired device header. For ATmega8A the supplement -# to *cpp would read -# -# -D__AVR_DEV_LIB_NAME__=m8a - - -*cpp: - -D__AVR_ATmega3250A__ -D__AVR_DEVICE_NAME__=atmega3250a - -# End of file diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega3250p b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega3250p deleted file mode 100644 index 48775f0..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega3250p +++ /dev/null @@ -1,99 +0,0 @@ -# -# Auto-generated specs for AVR device atmega3250p (core avr5, 16-bit SP) -# -# Generated by : ./gcc/config/avr/gen-avr-mmcu-specs.c -# Generated from : ./gcc/config/gcc.c -# ./gcc/config/avr/specs.h -# ./gcc/config/avr/avrlibc.h -# Used by : avr-gcc compiler driver -# Used for : building command options for sub-processes -# -# See -# for a documentation of spec files. - - -# If you intend to use an existing device specs file as a starting point -# for a new device spec file, make sure you are copying from a specs -# file for a device from the same core architecture and SP width. -# See for a description -# of how to use such own spec files. - -*avrlibc_startfile: - crtatmega3250p.o%s - -*avrlibc_devicelib: - %{!nodevicelib:-latmega3250p} - -*cc1_n_flash: - %{!mn-flash=*:-mn-flash=1} - -*cc1_rmw: - %{mrmw} - -*cc1_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*cc1_absdata: - %{mabsdata} - -*asm_arch: - -mmcu=avr5 - -*asm_relax: - %{mrelax:--mlink-relax} - -*asm_rmw: - %{mrmw} - -*asm_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*link_pmem_wrap: - %{mpmem-wrap-around: --pmem-wrap-around=32k} - -*link_relax: - %{mrelax:--relax} - -*link_arch: - %{mmcu=*:-m%*} - -*link_data_start: - -Tdata 0x800100 - -*link_text_start: - - -*self_spec: - %{!mmcu=avr*: % -# #elif ... -# -# If no device macro is defined, AVR-LibC uses __AVR_DEV_LIB_NAME__ -# as fallback to determine the name of the device header as -# -# "avr/io" + __AVR_DEV_LIB_NAME__ + ".h" -# -# If you provide your own specs file for a device not yet known to -# AVR-LibC, you can now define the hook macro __AVR_DEV_LIB_NAME__ -# as needed so that -# -# #include -# -# will include the desired device header. For ATmega8A the supplement -# to *cpp would read -# -# -D__AVR_DEV_LIB_NAME__=m8a - - -*cpp: - -D__AVR_ATmega3250P__ -D__AVR_DEVICE_NAME__=atmega3250p - -# End of file diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega3250pa b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega3250pa deleted file mode 100644 index 4de9b7d..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega3250pa +++ /dev/null @@ -1,99 +0,0 @@ -# -# Auto-generated specs for AVR device atmega3250pa (core avr5, 16-bit SP) -# -# Generated by : ./gcc/config/avr/gen-avr-mmcu-specs.c -# Generated from : ./gcc/config/gcc.c -# ./gcc/config/avr/specs.h -# ./gcc/config/avr/avrlibc.h -# Used by : avr-gcc compiler driver -# Used for : building command options for sub-processes -# -# See -# for a documentation of spec files. - - -# If you intend to use an existing device specs file as a starting point -# for a new device spec file, make sure you are copying from a specs -# file for a device from the same core architecture and SP width. -# See for a description -# of how to use such own spec files. - -*avrlibc_startfile: - crtatmega3250pa.o%s - -*avrlibc_devicelib: - %{!nodevicelib:-latmega3250pa} - -*cc1_n_flash: - %{!mn-flash=*:-mn-flash=1} - -*cc1_rmw: - %{mrmw} - -*cc1_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*cc1_absdata: - %{mabsdata} - -*asm_arch: - -mmcu=avr5 - -*asm_relax: - %{mrelax:--mlink-relax} - -*asm_rmw: - %{mrmw} - -*asm_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*link_pmem_wrap: - %{mpmem-wrap-around: --pmem-wrap-around=32k} - -*link_relax: - %{mrelax:--relax} - -*link_arch: - %{mmcu=*:-m%*} - -*link_data_start: - -Tdata 0x800100 - -*link_text_start: - - -*self_spec: - %{!mmcu=avr*: % -# #elif ... -# -# If no device macro is defined, AVR-LibC uses __AVR_DEV_LIB_NAME__ -# as fallback to determine the name of the device header as -# -# "avr/io" + __AVR_DEV_LIB_NAME__ + ".h" -# -# If you provide your own specs file for a device not yet known to -# AVR-LibC, you can now define the hook macro __AVR_DEV_LIB_NAME__ -# as needed so that -# -# #include -# -# will include the desired device header. For ATmega8A the supplement -# to *cpp would read -# -# -D__AVR_DEV_LIB_NAME__=m8a - - -*cpp: - -D__AVR_ATmega3250PA__ -D__AVR_DEVICE_NAME__=atmega3250pa - -# End of file diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega325a b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega325a deleted file mode 100644 index 315b1c8..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega325a +++ /dev/null @@ -1,99 +0,0 @@ -# -# Auto-generated specs for AVR device atmega325a (core avr5, 16-bit SP) -# -# Generated by : ./gcc/config/avr/gen-avr-mmcu-specs.c -# Generated from : ./gcc/config/gcc.c -# ./gcc/config/avr/specs.h -# ./gcc/config/avr/avrlibc.h -# Used by : avr-gcc compiler driver -# Used for : building command options for sub-processes -# -# See -# for a documentation of spec files. - - -# If you intend to use an existing device specs file as a starting point -# for a new device spec file, make sure you are copying from a specs -# file for a device from the same core architecture and SP width. -# See for a description -# of how to use such own spec files. - -*avrlibc_startfile: - crtatmega325a.o%s - -*avrlibc_devicelib: - %{!nodevicelib:-latmega325a} - -*cc1_n_flash: - %{!mn-flash=*:-mn-flash=1} - -*cc1_rmw: - %{mrmw} - -*cc1_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*cc1_absdata: - %{mabsdata} - -*asm_arch: - -mmcu=avr5 - -*asm_relax: - %{mrelax:--mlink-relax} - -*asm_rmw: - %{mrmw} - -*asm_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*link_pmem_wrap: - %{mpmem-wrap-around: --pmem-wrap-around=32k} - -*link_relax: - %{mrelax:--relax} - -*link_arch: - %{mmcu=*:-m%*} - -*link_data_start: - -Tdata 0x800100 - -*link_text_start: - - -*self_spec: - %{!mmcu=avr*: % -# #elif ... -# -# If no device macro is defined, AVR-LibC uses __AVR_DEV_LIB_NAME__ -# as fallback to determine the name of the device header as -# -# "avr/io" + __AVR_DEV_LIB_NAME__ + ".h" -# -# If you provide your own specs file for a device not yet known to -# AVR-LibC, you can now define the hook macro __AVR_DEV_LIB_NAME__ -# as needed so that -# -# #include -# -# will include the desired device header. For ATmega8A the supplement -# to *cpp would read -# -# -D__AVR_DEV_LIB_NAME__=m8a - - -*cpp: - -D__AVR_ATmega325A__ -D__AVR_DEVICE_NAME__=atmega325a - -# End of file diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega325p b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega325p deleted file mode 100644 index 2a10ec4..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega325p +++ /dev/null @@ -1,99 +0,0 @@ -# -# Auto-generated specs for AVR device atmega325p (core avr5, 16-bit SP) -# -# Generated by : ./gcc/config/avr/gen-avr-mmcu-specs.c -# Generated from : ./gcc/config/gcc.c -# ./gcc/config/avr/specs.h -# ./gcc/config/avr/avrlibc.h -# Used by : avr-gcc compiler driver -# Used for : building command options for sub-processes -# -# See -# for a documentation of spec files. - - -# If you intend to use an existing device specs file as a starting point -# for a new device spec file, make sure you are copying from a specs -# file for a device from the same core architecture and SP width. -# See for a description -# of how to use such own spec files. - -*avrlibc_startfile: - crtatmega325p.o%s - -*avrlibc_devicelib: - %{!nodevicelib:-latmega325p} - -*cc1_n_flash: - %{!mn-flash=*:-mn-flash=1} - -*cc1_rmw: - %{mrmw} - -*cc1_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*cc1_absdata: - %{mabsdata} - -*asm_arch: - -mmcu=avr5 - -*asm_relax: - %{mrelax:--mlink-relax} - -*asm_rmw: - %{mrmw} - -*asm_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*link_pmem_wrap: - %{mpmem-wrap-around: --pmem-wrap-around=32k} - -*link_relax: - %{mrelax:--relax} - -*link_arch: - %{mmcu=*:-m%*} - -*link_data_start: - -Tdata 0x800100 - -*link_text_start: - - -*self_spec: - %{!mmcu=avr*: % -# #elif ... -# -# If no device macro is defined, AVR-LibC uses __AVR_DEV_LIB_NAME__ -# as fallback to determine the name of the device header as -# -# "avr/io" + __AVR_DEV_LIB_NAME__ + ".h" -# -# If you provide your own specs file for a device not yet known to -# AVR-LibC, you can now define the hook macro __AVR_DEV_LIB_NAME__ -# as needed so that -# -# #include -# -# will include the desired device header. For ATmega8A the supplement -# to *cpp would read -# -# -D__AVR_DEV_LIB_NAME__=m8a - - -*cpp: - -D__AVR_ATmega325P__ -D__AVR_DEVICE_NAME__=atmega325p - -# End of file diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega325pa b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega325pa deleted file mode 100644 index 6194154..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega325pa +++ /dev/null @@ -1,99 +0,0 @@ -# -# Auto-generated specs for AVR device atmega325pa (core avr5, 16-bit SP) -# -# Generated by : ./gcc/config/avr/gen-avr-mmcu-specs.c -# Generated from : ./gcc/config/gcc.c -# ./gcc/config/avr/specs.h -# ./gcc/config/avr/avrlibc.h -# Used by : avr-gcc compiler driver -# Used for : building command options for sub-processes -# -# See -# for a documentation of spec files. - - -# If you intend to use an existing device specs file as a starting point -# for a new device spec file, make sure you are copying from a specs -# file for a device from the same core architecture and SP width. -# See for a description -# of how to use such own spec files. - -*avrlibc_startfile: - crtatmega325pa.o%s - -*avrlibc_devicelib: - %{!nodevicelib:-latmega325pa} - -*cc1_n_flash: - %{!mn-flash=*:-mn-flash=1} - -*cc1_rmw: - %{mrmw} - -*cc1_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*cc1_absdata: - %{mabsdata} - -*asm_arch: - -mmcu=avr5 - -*asm_relax: - %{mrelax:--mlink-relax} - -*asm_rmw: - %{mrmw} - -*asm_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*link_pmem_wrap: - %{mpmem-wrap-around: --pmem-wrap-around=32k} - -*link_relax: - %{mrelax:--relax} - -*link_arch: - %{mmcu=*:-m%*} - -*link_data_start: - -Tdata 0x800100 - -*link_text_start: - - -*self_spec: - %{!mmcu=avr*: % -# #elif ... -# -# If no device macro is defined, AVR-LibC uses __AVR_DEV_LIB_NAME__ -# as fallback to determine the name of the device header as -# -# "avr/io" + __AVR_DEV_LIB_NAME__ + ".h" -# -# If you provide your own specs file for a device not yet known to -# AVR-LibC, you can now define the hook macro __AVR_DEV_LIB_NAME__ -# as needed so that -# -# #include -# -# will include the desired device header. For ATmega8A the supplement -# to *cpp would read -# -# -D__AVR_DEV_LIB_NAME__=m8a - - -*cpp: - -D__AVR_ATmega325PA__ -D__AVR_DEVICE_NAME__=atmega325pa - -# End of file diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega328 b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega328 deleted file mode 100644 index e899d66..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega328 +++ /dev/null @@ -1,99 +0,0 @@ -# -# Auto-generated specs for AVR device atmega328 (core avr5, 16-bit SP) -# -# Generated by : ./gcc/config/avr/gen-avr-mmcu-specs.c -# Generated from : ./gcc/config/gcc.c -# ./gcc/config/avr/specs.h -# ./gcc/config/avr/avrlibc.h -# Used by : avr-gcc compiler driver -# Used for : building command options for sub-processes -# -# See -# for a documentation of spec files. - - -# If you intend to use an existing device specs file as a starting point -# for a new device spec file, make sure you are copying from a specs -# file for a device from the same core architecture and SP width. -# See for a description -# of how to use such own spec files. - -*avrlibc_startfile: - crtatmega328.o%s - -*avrlibc_devicelib: - %{!nodevicelib:-latmega328} - -*cc1_n_flash: - %{!mn-flash=*:-mn-flash=1} - -*cc1_rmw: - %{mrmw} - -*cc1_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*cc1_absdata: - %{mabsdata} - -*asm_arch: - -mmcu=avr5 - -*asm_relax: - %{mrelax:--mlink-relax} - -*asm_rmw: - %{mrmw} - -*asm_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*link_pmem_wrap: - %{mpmem-wrap-around: --pmem-wrap-around=32k} - -*link_relax: - %{mrelax:--relax} - -*link_arch: - %{mmcu=*:-m%*} - -*link_data_start: - -Tdata 0x800100 - -*link_text_start: - - -*self_spec: - %{!mmcu=avr*: % -# #elif ... -# -# If no device macro is defined, AVR-LibC uses __AVR_DEV_LIB_NAME__ -# as fallback to determine the name of the device header as -# -# "avr/io" + __AVR_DEV_LIB_NAME__ + ".h" -# -# If you provide your own specs file for a device not yet known to -# AVR-LibC, you can now define the hook macro __AVR_DEV_LIB_NAME__ -# as needed so that -# -# #include -# -# will include the desired device header. For ATmega8A the supplement -# to *cpp would read -# -# -D__AVR_DEV_LIB_NAME__=m8a - - -*cpp: - -D__AVR_ATmega328__ -D__AVR_DEVICE_NAME__=atmega328 - -# End of file diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega328p b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega328p deleted file mode 100644 index dc07fbb..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega328p +++ /dev/null @@ -1,99 +0,0 @@ -# -# Auto-generated specs for AVR device atmega328p (core avr5, 16-bit SP) -# -# Generated by : ./gcc/config/avr/gen-avr-mmcu-specs.c -# Generated from : ./gcc/config/gcc.c -# ./gcc/config/avr/specs.h -# ./gcc/config/avr/avrlibc.h -# Used by : avr-gcc compiler driver -# Used for : building command options for sub-processes -# -# See -# for a documentation of spec files. - - -# If you intend to use an existing device specs file as a starting point -# for a new device spec file, make sure you are copying from a specs -# file for a device from the same core architecture and SP width. -# See for a description -# of how to use such own spec files. - -*avrlibc_startfile: - crtatmega328p.o%s - -*avrlibc_devicelib: - %{!nodevicelib:-latmega328p} - -*cc1_n_flash: - %{!mn-flash=*:-mn-flash=1} - -*cc1_rmw: - %{mrmw} - -*cc1_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*cc1_absdata: - %{mabsdata} - -*asm_arch: - -mmcu=avr5 - -*asm_relax: - %{mrelax:--mlink-relax} - -*asm_rmw: - %{mrmw} - -*asm_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*link_pmem_wrap: - %{mpmem-wrap-around: --pmem-wrap-around=32k} - -*link_relax: - %{mrelax:--relax} - -*link_arch: - %{mmcu=*:-m%*} - -*link_data_start: - -Tdata 0x800100 - -*link_text_start: - - -*self_spec: - %{!mmcu=avr*: % -# #elif ... -# -# If no device macro is defined, AVR-LibC uses __AVR_DEV_LIB_NAME__ -# as fallback to determine the name of the device header as -# -# "avr/io" + __AVR_DEV_LIB_NAME__ + ".h" -# -# If you provide your own specs file for a device not yet known to -# AVR-LibC, you can now define the hook macro __AVR_DEV_LIB_NAME__ -# as needed so that -# -# #include -# -# will include the desired device header. For ATmega8A the supplement -# to *cpp would read -# -# -D__AVR_DEV_LIB_NAME__=m8a - - -*cpp: - -D__AVR_ATmega328P__ -D__AVR_DEVICE_NAME__=atmega328p - -# End of file diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega328pb b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega328pb deleted file mode 100644 index 226bfae..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega328pb +++ /dev/null @@ -1,99 +0,0 @@ -# -# Auto-generated specs for AVR device atmega328pb (core avr5, 16-bit SP) -# -# Generated by : ./gcc/config/avr/gen-avr-mmcu-specs.c -# Generated from : ./gcc/config/gcc.c -# ./gcc/config/avr/specs.h -# ./gcc/config/avr/avrlibc.h -# Used by : avr-gcc compiler driver -# Used for : building command options for sub-processes -# -# See -# for a documentation of spec files. - - -# If you intend to use an existing device specs file as a starting point -# for a new device spec file, make sure you are copying from a specs -# file for a device from the same core architecture and SP width. -# See for a description -# of how to use such own spec files. - -*avrlibc_startfile: - crtatmega328pb.o%s - -*avrlibc_devicelib: - %{!nodevicelib:-latmega328pb} - -*cc1_n_flash: - %{!mn-flash=*:-mn-flash=1} - -*cc1_rmw: - %{mrmw} - -*cc1_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*cc1_absdata: - %{mabsdata} - -*asm_arch: - -mmcu=avr5 - -*asm_relax: - %{mrelax:--mlink-relax} - -*asm_rmw: - %{mrmw} - -*asm_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*link_pmem_wrap: - %{mpmem-wrap-around: --pmem-wrap-around=32k} - -*link_relax: - %{mrelax:--relax} - -*link_arch: - %{mmcu=*:-m%*} - -*link_data_start: - -Tdata 0x800100 - -*link_text_start: - - -*self_spec: - %{!mmcu=avr*: % -# #elif ... -# -# If no device macro is defined, AVR-LibC uses __AVR_DEV_LIB_NAME__ -# as fallback to determine the name of the device header as -# -# "avr/io" + __AVR_DEV_LIB_NAME__ + ".h" -# -# If you provide your own specs file for a device not yet known to -# AVR-LibC, you can now define the hook macro __AVR_DEV_LIB_NAME__ -# as needed so that -# -# #include -# -# will include the desired device header. For ATmega8A the supplement -# to *cpp would read -# -# -D__AVR_DEV_LIB_NAME__=m8a - - -*cpp: - -D__AVR_ATmega328PB__ -D__AVR_DEVICE_NAME__=atmega328pb - -# End of file diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega329 b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega329 deleted file mode 100644 index b0f7dd0..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega329 +++ /dev/null @@ -1,99 +0,0 @@ -# -# Auto-generated specs for AVR device atmega329 (core avr5, 16-bit SP) -# -# Generated by : ./gcc/config/avr/gen-avr-mmcu-specs.c -# Generated from : ./gcc/config/gcc.c -# ./gcc/config/avr/specs.h -# ./gcc/config/avr/avrlibc.h -# Used by : avr-gcc compiler driver -# Used for : building command options for sub-processes -# -# See -# for a documentation of spec files. - - -# If you intend to use an existing device specs file as a starting point -# for a new device spec file, make sure you are copying from a specs -# file for a device from the same core architecture and SP width. -# See for a description -# of how to use such own spec files. - -*avrlibc_startfile: - crtatmega329.o%s - -*avrlibc_devicelib: - %{!nodevicelib:-latmega329} - -*cc1_n_flash: - %{!mn-flash=*:-mn-flash=1} - -*cc1_rmw: - %{mrmw} - -*cc1_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*cc1_absdata: - %{mabsdata} - -*asm_arch: - -mmcu=avr5 - -*asm_relax: - %{mrelax:--mlink-relax} - -*asm_rmw: - %{mrmw} - -*asm_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*link_pmem_wrap: - %{mpmem-wrap-around: --pmem-wrap-around=32k} - -*link_relax: - %{mrelax:--relax} - -*link_arch: - %{mmcu=*:-m%*} - -*link_data_start: - -Tdata 0x800100 - -*link_text_start: - - -*self_spec: - %{!mmcu=avr*: % -# #elif ... -# -# If no device macro is defined, AVR-LibC uses __AVR_DEV_LIB_NAME__ -# as fallback to determine the name of the device header as -# -# "avr/io" + __AVR_DEV_LIB_NAME__ + ".h" -# -# If you provide your own specs file for a device not yet known to -# AVR-LibC, you can now define the hook macro __AVR_DEV_LIB_NAME__ -# as needed so that -# -# #include -# -# will include the desired device header. For ATmega8A the supplement -# to *cpp would read -# -# -D__AVR_DEV_LIB_NAME__=m8a - - -*cpp: - -D__AVR_ATmega329__ -D__AVR_DEVICE_NAME__=atmega329 - -# End of file diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega3290 b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega3290 deleted file mode 100644 index db41cd5..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega3290 +++ /dev/null @@ -1,99 +0,0 @@ -# -# Auto-generated specs for AVR device atmega3290 (core avr5, 16-bit SP) -# -# Generated by : ./gcc/config/avr/gen-avr-mmcu-specs.c -# Generated from : ./gcc/config/gcc.c -# ./gcc/config/avr/specs.h -# ./gcc/config/avr/avrlibc.h -# Used by : avr-gcc compiler driver -# Used for : building command options for sub-processes -# -# See -# for a documentation of spec files. - - -# If you intend to use an existing device specs file as a starting point -# for a new device spec file, make sure you are copying from a specs -# file for a device from the same core architecture and SP width. -# See for a description -# of how to use such own spec files. - -*avrlibc_startfile: - crtatmega3290.o%s - -*avrlibc_devicelib: - %{!nodevicelib:-latmega3290} - -*cc1_n_flash: - %{!mn-flash=*:-mn-flash=1} - -*cc1_rmw: - %{mrmw} - -*cc1_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*cc1_absdata: - %{mabsdata} - -*asm_arch: - -mmcu=avr5 - -*asm_relax: - %{mrelax:--mlink-relax} - -*asm_rmw: - %{mrmw} - -*asm_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*link_pmem_wrap: - %{mpmem-wrap-around: --pmem-wrap-around=32k} - -*link_relax: - %{mrelax:--relax} - -*link_arch: - %{mmcu=*:-m%*} - -*link_data_start: - -Tdata 0x800100 - -*link_text_start: - - -*self_spec: - %{!mmcu=avr*: % -# #elif ... -# -# If no device macro is defined, AVR-LibC uses __AVR_DEV_LIB_NAME__ -# as fallback to determine the name of the device header as -# -# "avr/io" + __AVR_DEV_LIB_NAME__ + ".h" -# -# If you provide your own specs file for a device not yet known to -# AVR-LibC, you can now define the hook macro __AVR_DEV_LIB_NAME__ -# as needed so that -# -# #include -# -# will include the desired device header. For ATmega8A the supplement -# to *cpp would read -# -# -D__AVR_DEV_LIB_NAME__=m8a - - -*cpp: - -D__AVR_ATmega3290__ -D__AVR_DEVICE_NAME__=atmega3290 - -# End of file diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega3290a b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega3290a deleted file mode 100644 index 740d7ee..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega3290a +++ /dev/null @@ -1,99 +0,0 @@ -# -# Auto-generated specs for AVR device atmega3290a (core avr5, 16-bit SP) -# -# Generated by : ./gcc/config/avr/gen-avr-mmcu-specs.c -# Generated from : ./gcc/config/gcc.c -# ./gcc/config/avr/specs.h -# ./gcc/config/avr/avrlibc.h -# Used by : avr-gcc compiler driver -# Used for : building command options for sub-processes -# -# See -# for a documentation of spec files. - - -# If you intend to use an existing device specs file as a starting point -# for a new device spec file, make sure you are copying from a specs -# file for a device from the same core architecture and SP width. -# See for a description -# of how to use such own spec files. - -*avrlibc_startfile: - crtatmega3290a.o%s - -*avrlibc_devicelib: - %{!nodevicelib:-latmega3290a} - -*cc1_n_flash: - %{!mn-flash=*:-mn-flash=1} - -*cc1_rmw: - %{mrmw} - -*cc1_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*cc1_absdata: - %{mabsdata} - -*asm_arch: - -mmcu=avr5 - -*asm_relax: - %{mrelax:--mlink-relax} - -*asm_rmw: - %{mrmw} - -*asm_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*link_pmem_wrap: - %{mpmem-wrap-around: --pmem-wrap-around=32k} - -*link_relax: - %{mrelax:--relax} - -*link_arch: - %{mmcu=*:-m%*} - -*link_data_start: - -Tdata 0x800100 - -*link_text_start: - - -*self_spec: - %{!mmcu=avr*: % -# #elif ... -# -# If no device macro is defined, AVR-LibC uses __AVR_DEV_LIB_NAME__ -# as fallback to determine the name of the device header as -# -# "avr/io" + __AVR_DEV_LIB_NAME__ + ".h" -# -# If you provide your own specs file for a device not yet known to -# AVR-LibC, you can now define the hook macro __AVR_DEV_LIB_NAME__ -# as needed so that -# -# #include -# -# will include the desired device header. For ATmega8A the supplement -# to *cpp would read -# -# -D__AVR_DEV_LIB_NAME__=m8a - - -*cpp: - -D__AVR_ATmega3290A__ -D__AVR_DEVICE_NAME__=atmega3290a - -# End of file diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega3290p b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega3290p deleted file mode 100644 index 60fbc43..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega3290p +++ /dev/null @@ -1,99 +0,0 @@ -# -# Auto-generated specs for AVR device atmega3290p (core avr5, 16-bit SP) -# -# Generated by : ./gcc/config/avr/gen-avr-mmcu-specs.c -# Generated from : ./gcc/config/gcc.c -# ./gcc/config/avr/specs.h -# ./gcc/config/avr/avrlibc.h -# Used by : avr-gcc compiler driver -# Used for : building command options for sub-processes -# -# See -# for a documentation of spec files. - - -# If you intend to use an existing device specs file as a starting point -# for a new device spec file, make sure you are copying from a specs -# file for a device from the same core architecture and SP width. -# See for a description -# of how to use such own spec files. - -*avrlibc_startfile: - crtatmega3290p.o%s - -*avrlibc_devicelib: - %{!nodevicelib:-latmega3290p} - -*cc1_n_flash: - %{!mn-flash=*:-mn-flash=1} - -*cc1_rmw: - %{mrmw} - -*cc1_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*cc1_absdata: - %{mabsdata} - -*asm_arch: - -mmcu=avr5 - -*asm_relax: - %{mrelax:--mlink-relax} - -*asm_rmw: - %{mrmw} - -*asm_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*link_pmem_wrap: - %{mpmem-wrap-around: --pmem-wrap-around=32k} - -*link_relax: - %{mrelax:--relax} - -*link_arch: - %{mmcu=*:-m%*} - -*link_data_start: - -Tdata 0x800100 - -*link_text_start: - - -*self_spec: - %{!mmcu=avr*: % -# #elif ... -# -# If no device macro is defined, AVR-LibC uses __AVR_DEV_LIB_NAME__ -# as fallback to determine the name of the device header as -# -# "avr/io" + __AVR_DEV_LIB_NAME__ + ".h" -# -# If you provide your own specs file for a device not yet known to -# AVR-LibC, you can now define the hook macro __AVR_DEV_LIB_NAME__ -# as needed so that -# -# #include -# -# will include the desired device header. For ATmega8A the supplement -# to *cpp would read -# -# -D__AVR_DEV_LIB_NAME__=m8a - - -*cpp: - -D__AVR_ATmega3290P__ -D__AVR_DEVICE_NAME__=atmega3290p - -# End of file diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega3290pa b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega3290pa deleted file mode 100644 index ae09ed0..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega3290pa +++ /dev/null @@ -1,99 +0,0 @@ -# -# Auto-generated specs for AVR device atmega3290pa (core avr5, 16-bit SP) -# -# Generated by : ./gcc/config/avr/gen-avr-mmcu-specs.c -# Generated from : ./gcc/config/gcc.c -# ./gcc/config/avr/specs.h -# ./gcc/config/avr/avrlibc.h -# Used by : avr-gcc compiler driver -# Used for : building command options for sub-processes -# -# See -# for a documentation of spec files. - - -# If you intend to use an existing device specs file as a starting point -# for a new device spec file, make sure you are copying from a specs -# file for a device from the same core architecture and SP width. -# See for a description -# of how to use such own spec files. - -*avrlibc_startfile: - crtatmega3290pa.o%s - -*avrlibc_devicelib: - %{!nodevicelib:-latmega3290pa} - -*cc1_n_flash: - %{!mn-flash=*:-mn-flash=1} - -*cc1_rmw: - %{mrmw} - -*cc1_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*cc1_absdata: - %{mabsdata} - -*asm_arch: - -mmcu=avr5 - -*asm_relax: - %{mrelax:--mlink-relax} - -*asm_rmw: - %{mrmw} - -*asm_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*link_pmem_wrap: - %{mpmem-wrap-around: --pmem-wrap-around=32k} - -*link_relax: - %{mrelax:--relax} - -*link_arch: - %{mmcu=*:-m%*} - -*link_data_start: - -Tdata 0x800100 - -*link_text_start: - - -*self_spec: - %{!mmcu=avr*: % -# #elif ... -# -# If no device macro is defined, AVR-LibC uses __AVR_DEV_LIB_NAME__ -# as fallback to determine the name of the device header as -# -# "avr/io" + __AVR_DEV_LIB_NAME__ + ".h" -# -# If you provide your own specs file for a device not yet known to -# AVR-LibC, you can now define the hook macro __AVR_DEV_LIB_NAME__ -# as needed so that -# -# #include -# -# will include the desired device header. For ATmega8A the supplement -# to *cpp would read -# -# -D__AVR_DEV_LIB_NAME__=m8a - - -*cpp: - -D__AVR_ATmega3290PA__ -D__AVR_DEVICE_NAME__=atmega3290pa - -# End of file diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega329a b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega329a deleted file mode 100644 index 18db55e..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega329a +++ /dev/null @@ -1,99 +0,0 @@ -# -# Auto-generated specs for AVR device atmega329a (core avr5, 16-bit SP) -# -# Generated by : ./gcc/config/avr/gen-avr-mmcu-specs.c -# Generated from : ./gcc/config/gcc.c -# ./gcc/config/avr/specs.h -# ./gcc/config/avr/avrlibc.h -# Used by : avr-gcc compiler driver -# Used for : building command options for sub-processes -# -# See -# for a documentation of spec files. - - -# If you intend to use an existing device specs file as a starting point -# for a new device spec file, make sure you are copying from a specs -# file for a device from the same core architecture and SP width. -# See for a description -# of how to use such own spec files. - -*avrlibc_startfile: - crtatmega329a.o%s - -*avrlibc_devicelib: - %{!nodevicelib:-latmega329a} - -*cc1_n_flash: - %{!mn-flash=*:-mn-flash=1} - -*cc1_rmw: - %{mrmw} - -*cc1_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*cc1_absdata: - %{mabsdata} - -*asm_arch: - -mmcu=avr5 - -*asm_relax: - %{mrelax:--mlink-relax} - -*asm_rmw: - %{mrmw} - -*asm_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*link_pmem_wrap: - %{mpmem-wrap-around: --pmem-wrap-around=32k} - -*link_relax: - %{mrelax:--relax} - -*link_arch: - %{mmcu=*:-m%*} - -*link_data_start: - -Tdata 0x800100 - -*link_text_start: - - -*self_spec: - %{!mmcu=avr*: % -# #elif ... -# -# If no device macro is defined, AVR-LibC uses __AVR_DEV_LIB_NAME__ -# as fallback to determine the name of the device header as -# -# "avr/io" + __AVR_DEV_LIB_NAME__ + ".h" -# -# If you provide your own specs file for a device not yet known to -# AVR-LibC, you can now define the hook macro __AVR_DEV_LIB_NAME__ -# as needed so that -# -# #include -# -# will include the desired device header. For ATmega8A the supplement -# to *cpp would read -# -# -D__AVR_DEV_LIB_NAME__=m8a - - -*cpp: - -D__AVR_ATmega329A__ -D__AVR_DEVICE_NAME__=atmega329a - -# End of file diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega329p b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega329p deleted file mode 100644 index c6dfc17..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega329p +++ /dev/null @@ -1,99 +0,0 @@ -# -# Auto-generated specs for AVR device atmega329p (core avr5, 16-bit SP) -# -# Generated by : ./gcc/config/avr/gen-avr-mmcu-specs.c -# Generated from : ./gcc/config/gcc.c -# ./gcc/config/avr/specs.h -# ./gcc/config/avr/avrlibc.h -# Used by : avr-gcc compiler driver -# Used for : building command options for sub-processes -# -# See -# for a documentation of spec files. - - -# If you intend to use an existing device specs file as a starting point -# for a new device spec file, make sure you are copying from a specs -# file for a device from the same core architecture and SP width. -# See for a description -# of how to use such own spec files. - -*avrlibc_startfile: - crtatmega329p.o%s - -*avrlibc_devicelib: - %{!nodevicelib:-latmega329p} - -*cc1_n_flash: - %{!mn-flash=*:-mn-flash=1} - -*cc1_rmw: - %{mrmw} - -*cc1_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*cc1_absdata: - %{mabsdata} - -*asm_arch: - -mmcu=avr5 - -*asm_relax: - %{mrelax:--mlink-relax} - -*asm_rmw: - %{mrmw} - -*asm_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*link_pmem_wrap: - %{mpmem-wrap-around: --pmem-wrap-around=32k} - -*link_relax: - %{mrelax:--relax} - -*link_arch: - %{mmcu=*:-m%*} - -*link_data_start: - -Tdata 0x800100 - -*link_text_start: - - -*self_spec: - %{!mmcu=avr*: % -# #elif ... -# -# If no device macro is defined, AVR-LibC uses __AVR_DEV_LIB_NAME__ -# as fallback to determine the name of the device header as -# -# "avr/io" + __AVR_DEV_LIB_NAME__ + ".h" -# -# If you provide your own specs file for a device not yet known to -# AVR-LibC, you can now define the hook macro __AVR_DEV_LIB_NAME__ -# as needed so that -# -# #include -# -# will include the desired device header. For ATmega8A the supplement -# to *cpp would read -# -# -D__AVR_DEV_LIB_NAME__=m8a - - -*cpp: - -D__AVR_ATmega329P__ -D__AVR_DEVICE_NAME__=atmega329p - -# End of file diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega329pa b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega329pa deleted file mode 100644 index 1497faf..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega329pa +++ /dev/null @@ -1,99 +0,0 @@ -# -# Auto-generated specs for AVR device atmega329pa (core avr5, 16-bit SP) -# -# Generated by : ./gcc/config/avr/gen-avr-mmcu-specs.c -# Generated from : ./gcc/config/gcc.c -# ./gcc/config/avr/specs.h -# ./gcc/config/avr/avrlibc.h -# Used by : avr-gcc compiler driver -# Used for : building command options for sub-processes -# -# See -# for a documentation of spec files. - - -# If you intend to use an existing device specs file as a starting point -# for a new device spec file, make sure you are copying from a specs -# file for a device from the same core architecture and SP width. -# See for a description -# of how to use such own spec files. - -*avrlibc_startfile: - crtatmega329pa.o%s - -*avrlibc_devicelib: - %{!nodevicelib:-latmega329pa} - -*cc1_n_flash: - %{!mn-flash=*:-mn-flash=1} - -*cc1_rmw: - %{mrmw} - -*cc1_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*cc1_absdata: - %{mabsdata} - -*asm_arch: - -mmcu=avr5 - -*asm_relax: - %{mrelax:--mlink-relax} - -*asm_rmw: - %{mrmw} - -*asm_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*link_pmem_wrap: - %{mpmem-wrap-around: --pmem-wrap-around=32k} - -*link_relax: - %{mrelax:--relax} - -*link_arch: - %{mmcu=*:-m%*} - -*link_data_start: - -Tdata 0x800100 - -*link_text_start: - - -*self_spec: - %{!mmcu=avr*: % -# #elif ... -# -# If no device macro is defined, AVR-LibC uses __AVR_DEV_LIB_NAME__ -# as fallback to determine the name of the device header as -# -# "avr/io" + __AVR_DEV_LIB_NAME__ + ".h" -# -# If you provide your own specs file for a device not yet known to -# AVR-LibC, you can now define the hook macro __AVR_DEV_LIB_NAME__ -# as needed so that -# -# #include -# -# will include the desired device header. For ATmega8A the supplement -# to *cpp would read -# -# -D__AVR_DEV_LIB_NAME__=m8a - - -*cpp: - -D__AVR_ATmega329PA__ -D__AVR_DEVICE_NAME__=atmega329pa - -# End of file diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega32a b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega32a deleted file mode 100644 index 7d31f07..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega32a +++ /dev/null @@ -1,99 +0,0 @@ -# -# Auto-generated specs for AVR device atmega32a (core avr5, 16-bit SP) -# -# Generated by : ./gcc/config/avr/gen-avr-mmcu-specs.c -# Generated from : ./gcc/config/gcc.c -# ./gcc/config/avr/specs.h -# ./gcc/config/avr/avrlibc.h -# Used by : avr-gcc compiler driver -# Used for : building command options for sub-processes -# -# See -# for a documentation of spec files. - - -# If you intend to use an existing device specs file as a starting point -# for a new device spec file, make sure you are copying from a specs -# file for a device from the same core architecture and SP width. -# See for a description -# of how to use such own spec files. - -*avrlibc_startfile: - crtatmega32a.o%s - -*avrlibc_devicelib: - %{!nodevicelib:-latmega32a} - -*cc1_n_flash: - %{!mn-flash=*:-mn-flash=1} - -*cc1_rmw: - %{mrmw} - -*cc1_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*cc1_absdata: - %{mabsdata} - -*asm_arch: - -mmcu=avr5 - -*asm_relax: - %{mrelax:--mlink-relax} - -*asm_rmw: - %{mrmw} - -*asm_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*link_pmem_wrap: - %{mpmem-wrap-around: --pmem-wrap-around=32k} - -*link_relax: - %{mrelax:--relax} - -*link_arch: - %{mmcu=*:-m%*} - -*link_data_start: - - -*link_text_start: - - -*self_spec: - %{!mmcu=avr*: % -# #elif ... -# -# If no device macro is defined, AVR-LibC uses __AVR_DEV_LIB_NAME__ -# as fallback to determine the name of the device header as -# -# "avr/io" + __AVR_DEV_LIB_NAME__ + ".h" -# -# If you provide your own specs file for a device not yet known to -# AVR-LibC, you can now define the hook macro __AVR_DEV_LIB_NAME__ -# as needed so that -# -# #include -# -# will include the desired device header. For ATmega8A the supplement -# to *cpp would read -# -# -D__AVR_DEV_LIB_NAME__=m8a - - -*cpp: - -D__AVR_ATmega32A__ -D__AVR_DEVICE_NAME__=atmega32a - -# End of file diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega32c1 b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega32c1 deleted file mode 100644 index f3b9d18..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega32c1 +++ /dev/null @@ -1,99 +0,0 @@ -# -# Auto-generated specs for AVR device atmega32c1 (core avr5, 16-bit SP) -# -# Generated by : ./gcc/config/avr/gen-avr-mmcu-specs.c -# Generated from : ./gcc/config/gcc.c -# ./gcc/config/avr/specs.h -# ./gcc/config/avr/avrlibc.h -# Used by : avr-gcc compiler driver -# Used for : building command options for sub-processes -# -# See -# for a documentation of spec files. - - -# If you intend to use an existing device specs file as a starting point -# for a new device spec file, make sure you are copying from a specs -# file for a device from the same core architecture and SP width. -# See for a description -# of how to use such own spec files. - -*avrlibc_startfile: - crtatmega32c1.o%s - -*avrlibc_devicelib: - %{!nodevicelib:-latmega32c1} - -*cc1_n_flash: - %{!mn-flash=*:-mn-flash=1} - -*cc1_rmw: - %{mrmw} - -*cc1_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*cc1_absdata: - %{mabsdata} - -*asm_arch: - -mmcu=avr5 - -*asm_relax: - %{mrelax:--mlink-relax} - -*asm_rmw: - %{mrmw} - -*asm_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*link_pmem_wrap: - %{mpmem-wrap-around: --pmem-wrap-around=32k} - -*link_relax: - %{mrelax:--relax} - -*link_arch: - %{mmcu=*:-m%*} - -*link_data_start: - -Tdata 0x800100 - -*link_text_start: - - -*self_spec: - %{!mmcu=avr*: % -# #elif ... -# -# If no device macro is defined, AVR-LibC uses __AVR_DEV_LIB_NAME__ -# as fallback to determine the name of the device header as -# -# "avr/io" + __AVR_DEV_LIB_NAME__ + ".h" -# -# If you provide your own specs file for a device not yet known to -# AVR-LibC, you can now define the hook macro __AVR_DEV_LIB_NAME__ -# as needed so that -# -# #include -# -# will include the desired device header. For ATmega8A the supplement -# to *cpp would read -# -# -D__AVR_DEV_LIB_NAME__=m8a - - -*cpp: - -D__AVR_ATmega32C1__ -D__AVR_DEVICE_NAME__=atmega32c1 - -# End of file diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega32hvb b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega32hvb deleted file mode 100644 index c5e875b..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega32hvb +++ /dev/null @@ -1,99 +0,0 @@ -# -# Auto-generated specs for AVR device atmega32hvb (core avr5, 16-bit SP) -# -# Generated by : ./gcc/config/avr/gen-avr-mmcu-specs.c -# Generated from : ./gcc/config/gcc.c -# ./gcc/config/avr/specs.h -# ./gcc/config/avr/avrlibc.h -# Used by : avr-gcc compiler driver -# Used for : building command options for sub-processes -# -# See -# for a documentation of spec files. - - -# If you intend to use an existing device specs file as a starting point -# for a new device spec file, make sure you are copying from a specs -# file for a device from the same core architecture and SP width. -# See for a description -# of how to use such own spec files. - -*avrlibc_startfile: - crtatmega32hvb.o%s - -*avrlibc_devicelib: - %{!nodevicelib:-latmega32hvb} - -*cc1_n_flash: - %{!mn-flash=*:-mn-flash=1} - -*cc1_rmw: - %{mrmw} - -*cc1_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*cc1_absdata: - %{mabsdata} - -*asm_arch: - -mmcu=avr5 - -*asm_relax: - %{mrelax:--mlink-relax} - -*asm_rmw: - %{mrmw} - -*asm_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*link_pmem_wrap: - %{mpmem-wrap-around: --pmem-wrap-around=32k} - -*link_relax: - %{mrelax:--relax} - -*link_arch: - %{mmcu=*:-m%*} - -*link_data_start: - -Tdata 0x800100 - -*link_text_start: - - -*self_spec: - %{!mmcu=avr*: % -# #elif ... -# -# If no device macro is defined, AVR-LibC uses __AVR_DEV_LIB_NAME__ -# as fallback to determine the name of the device header as -# -# "avr/io" + __AVR_DEV_LIB_NAME__ + ".h" -# -# If you provide your own specs file for a device not yet known to -# AVR-LibC, you can now define the hook macro __AVR_DEV_LIB_NAME__ -# as needed so that -# -# #include -# -# will include the desired device header. For ATmega8A the supplement -# to *cpp would read -# -# -D__AVR_DEV_LIB_NAME__=m8a - - -*cpp: - -D__AVR_ATmega32HVB__ -D__AVR_DEVICE_NAME__=atmega32hvb - -# End of file diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega32hvbrevb b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega32hvbrevb deleted file mode 100644 index 5d64581..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega32hvbrevb +++ /dev/null @@ -1,99 +0,0 @@ -# -# Auto-generated specs for AVR device atmega32hvbrevb (core avr5, 16-bit SP) -# -# Generated by : ./gcc/config/avr/gen-avr-mmcu-specs.c -# Generated from : ./gcc/config/gcc.c -# ./gcc/config/avr/specs.h -# ./gcc/config/avr/avrlibc.h -# Used by : avr-gcc compiler driver -# Used for : building command options for sub-processes -# -# See -# for a documentation of spec files. - - -# If you intend to use an existing device specs file as a starting point -# for a new device spec file, make sure you are copying from a specs -# file for a device from the same core architecture and SP width. -# See for a description -# of how to use such own spec files. - -*avrlibc_startfile: - crtatmega32hvbrevb.o%s - -*avrlibc_devicelib: - %{!nodevicelib:-latmega32hvbrevb} - -*cc1_n_flash: - %{!mn-flash=*:-mn-flash=1} - -*cc1_rmw: - %{mrmw} - -*cc1_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*cc1_absdata: - %{mabsdata} - -*asm_arch: - -mmcu=avr5 - -*asm_relax: - %{mrelax:--mlink-relax} - -*asm_rmw: - %{mrmw} - -*asm_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*link_pmem_wrap: - %{mpmem-wrap-around: --pmem-wrap-around=32k} - -*link_relax: - %{mrelax:--relax} - -*link_arch: - %{mmcu=*:-m%*} - -*link_data_start: - -Tdata 0x800100 - -*link_text_start: - - -*self_spec: - %{!mmcu=avr*: % -# #elif ... -# -# If no device macro is defined, AVR-LibC uses __AVR_DEV_LIB_NAME__ -# as fallback to determine the name of the device header as -# -# "avr/io" + __AVR_DEV_LIB_NAME__ + ".h" -# -# If you provide your own specs file for a device not yet known to -# AVR-LibC, you can now define the hook macro __AVR_DEV_LIB_NAME__ -# as needed so that -# -# #include -# -# will include the desired device header. For ATmega8A the supplement -# to *cpp would read -# -# -D__AVR_DEV_LIB_NAME__=m8a - - -*cpp: - -D__AVR_ATmega32HVBREVB__ -D__AVR_DEVICE_NAME__=atmega32hvbrevb - -# End of file diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega32m1 b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega32m1 deleted file mode 100644 index e637058..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega32m1 +++ /dev/null @@ -1,99 +0,0 @@ -# -# Auto-generated specs for AVR device atmega32m1 (core avr5, 16-bit SP) -# -# Generated by : ./gcc/config/avr/gen-avr-mmcu-specs.c -# Generated from : ./gcc/config/gcc.c -# ./gcc/config/avr/specs.h -# ./gcc/config/avr/avrlibc.h -# Used by : avr-gcc compiler driver -# Used for : building command options for sub-processes -# -# See -# for a documentation of spec files. - - -# If you intend to use an existing device specs file as a starting point -# for a new device spec file, make sure you are copying from a specs -# file for a device from the same core architecture and SP width. -# See for a description -# of how to use such own spec files. - -*avrlibc_startfile: - crtatmega32m1.o%s - -*avrlibc_devicelib: - %{!nodevicelib:-latmega32m1} - -*cc1_n_flash: - %{!mn-flash=*:-mn-flash=1} - -*cc1_rmw: - %{mrmw} - -*cc1_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*cc1_absdata: - %{mabsdata} - -*asm_arch: - -mmcu=avr5 - -*asm_relax: - %{mrelax:--mlink-relax} - -*asm_rmw: - %{mrmw} - -*asm_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*link_pmem_wrap: - %{mpmem-wrap-around: --pmem-wrap-around=32k} - -*link_relax: - %{mrelax:--relax} - -*link_arch: - %{mmcu=*:-m%*} - -*link_data_start: - -Tdata 0x800100 - -*link_text_start: - - -*self_spec: - %{!mmcu=avr*: % -# #elif ... -# -# If no device macro is defined, AVR-LibC uses __AVR_DEV_LIB_NAME__ -# as fallback to determine the name of the device header as -# -# "avr/io" + __AVR_DEV_LIB_NAME__ + ".h" -# -# If you provide your own specs file for a device not yet known to -# AVR-LibC, you can now define the hook macro __AVR_DEV_LIB_NAME__ -# as needed so that -# -# #include -# -# will include the desired device header. For ATmega8A the supplement -# to *cpp would read -# -# -D__AVR_DEV_LIB_NAME__=m8a - - -*cpp: - -D__AVR_ATmega32M1__ -D__AVR_DEVICE_NAME__=atmega32m1 - -# End of file diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega32u2 b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega32u2 deleted file mode 100644 index 93b768a..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega32u2 +++ /dev/null @@ -1,99 +0,0 @@ -# -# Auto-generated specs for AVR device atmega32u2 (core avr35, 16-bit SP) -# -# Generated by : ./gcc/config/avr/gen-avr-mmcu-specs.c -# Generated from : ./gcc/config/gcc.c -# ./gcc/config/avr/specs.h -# ./gcc/config/avr/avrlibc.h -# Used by : avr-gcc compiler driver -# Used for : building command options for sub-processes -# -# See -# for a documentation of spec files. - - -# If you intend to use an existing device specs file as a starting point -# for a new device spec file, make sure you are copying from a specs -# file for a device from the same core architecture and SP width. -# See for a description -# of how to use such own spec files. - -*avrlibc_startfile: - crtatmega32u2.o%s - -*avrlibc_devicelib: - %{!nodevicelib:-latmega32u2} - -*cc1_n_flash: - %{!mn-flash=*:-mn-flash=1} - -*cc1_rmw: - %{mrmw} - -*cc1_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*cc1_absdata: - %{mabsdata} - -*asm_arch: - -mmcu=avr35 - -*asm_relax: - %{mrelax:--mlink-relax} - -*asm_rmw: - %{mrmw} - -*asm_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*link_pmem_wrap: - %{mpmem-wrap-around: --pmem-wrap-around=32k} - -*link_relax: - %{mrelax:--relax} - -*link_arch: - %{mmcu=*:-m%*} - -*link_data_start: - -Tdata 0x800100 - -*link_text_start: - - -*self_spec: - %{!mmcu=avr*: % -# #elif ... -# -# If no device macro is defined, AVR-LibC uses __AVR_DEV_LIB_NAME__ -# as fallback to determine the name of the device header as -# -# "avr/io" + __AVR_DEV_LIB_NAME__ + ".h" -# -# If you provide your own specs file for a device not yet known to -# AVR-LibC, you can now define the hook macro __AVR_DEV_LIB_NAME__ -# as needed so that -# -# #include -# -# will include the desired device header. For ATmega8A the supplement -# to *cpp would read -# -# -D__AVR_DEV_LIB_NAME__=m8a - - -*cpp: - -D__AVR_ATmega32U2__ -D__AVR_DEVICE_NAME__=atmega32u2 - -# End of file diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega32u4 b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega32u4 deleted file mode 100644 index b0d2046..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega32u4 +++ /dev/null @@ -1,99 +0,0 @@ -# -# Auto-generated specs for AVR device atmega32u4 (core avr5, 16-bit SP) -# -# Generated by : ./gcc/config/avr/gen-avr-mmcu-specs.c -# Generated from : ./gcc/config/gcc.c -# ./gcc/config/avr/specs.h -# ./gcc/config/avr/avrlibc.h -# Used by : avr-gcc compiler driver -# Used for : building command options for sub-processes -# -# See -# for a documentation of spec files. - - -# If you intend to use an existing device specs file as a starting point -# for a new device spec file, make sure you are copying from a specs -# file for a device from the same core architecture and SP width. -# See for a description -# of how to use such own spec files. - -*avrlibc_startfile: - crtatmega32u4.o%s - -*avrlibc_devicelib: - %{!nodevicelib:-latmega32u4} - -*cc1_n_flash: - %{!mn-flash=*:-mn-flash=1} - -*cc1_rmw: - %{mrmw} - -*cc1_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*cc1_absdata: - %{mabsdata} - -*asm_arch: - -mmcu=avr5 - -*asm_relax: - %{mrelax:--mlink-relax} - -*asm_rmw: - %{mrmw} - -*asm_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*link_pmem_wrap: - %{mpmem-wrap-around: --pmem-wrap-around=32k} - -*link_relax: - %{mrelax:--relax} - -*link_arch: - %{mmcu=*:-m%*} - -*link_data_start: - -Tdata 0x800100 - -*link_text_start: - - -*self_spec: - %{!mmcu=avr*: % -# #elif ... -# -# If no device macro is defined, AVR-LibC uses __AVR_DEV_LIB_NAME__ -# as fallback to determine the name of the device header as -# -# "avr/io" + __AVR_DEV_LIB_NAME__ + ".h" -# -# If you provide your own specs file for a device not yet known to -# AVR-LibC, you can now define the hook macro __AVR_DEV_LIB_NAME__ -# as needed so that -# -# #include -# -# will include the desired device header. For ATmega8A the supplement -# to *cpp would read -# -# -D__AVR_DEV_LIB_NAME__=m8a - - -*cpp: - -D__AVR_ATmega32U4__ -D__AVR_DEVICE_NAME__=atmega32u4 - -# End of file diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega32u6 b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega32u6 deleted file mode 100644 index 033e344..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega32u6 +++ /dev/null @@ -1,99 +0,0 @@ -# -# Auto-generated specs for AVR device atmega32u6 (core avr5, 16-bit SP) -# -# Generated by : ./gcc/config/avr/gen-avr-mmcu-specs.c -# Generated from : ./gcc/config/gcc.c -# ./gcc/config/avr/specs.h -# ./gcc/config/avr/avrlibc.h -# Used by : avr-gcc compiler driver -# Used for : building command options for sub-processes -# -# See -# for a documentation of spec files. - - -# If you intend to use an existing device specs file as a starting point -# for a new device spec file, make sure you are copying from a specs -# file for a device from the same core architecture and SP width. -# See for a description -# of how to use such own spec files. - -*avrlibc_startfile: - crtatmega32u6.o%s - -*avrlibc_devicelib: - %{!nodevicelib:-latmega32u6} - -*cc1_n_flash: - %{!mn-flash=*:-mn-flash=1} - -*cc1_rmw: - %{mrmw} - -*cc1_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*cc1_absdata: - %{mabsdata} - -*asm_arch: - -mmcu=avr5 - -*asm_relax: - %{mrelax:--mlink-relax} - -*asm_rmw: - %{mrmw} - -*asm_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*link_pmem_wrap: - %{mpmem-wrap-around: --pmem-wrap-around=32k} - -*link_relax: - %{mrelax:--relax} - -*link_arch: - %{mmcu=*:-m%*} - -*link_data_start: - -Tdata 0x800100 - -*link_text_start: - - -*self_spec: - %{!mmcu=avr*: % -# #elif ... -# -# If no device macro is defined, AVR-LibC uses __AVR_DEV_LIB_NAME__ -# as fallback to determine the name of the device header as -# -# "avr/io" + __AVR_DEV_LIB_NAME__ + ".h" -# -# If you provide your own specs file for a device not yet known to -# AVR-LibC, you can now define the hook macro __AVR_DEV_LIB_NAME__ -# as needed so that -# -# #include -# -# will include the desired device header. For ATmega8A the supplement -# to *cpp would read -# -# -D__AVR_DEV_LIB_NAME__=m8a - - -*cpp: - -D__AVR_ATmega32U6__ -D__AVR_DEVICE_NAME__=atmega32u6 - -# End of file diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega406 b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega406 deleted file mode 100644 index 5946d8a..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega406 +++ /dev/null @@ -1,99 +0,0 @@ -# -# Auto-generated specs for AVR device atmega406 (core avr5, 16-bit SP) -# -# Generated by : ./gcc/config/avr/gen-avr-mmcu-specs.c -# Generated from : ./gcc/config/gcc.c -# ./gcc/config/avr/specs.h -# ./gcc/config/avr/avrlibc.h -# Used by : avr-gcc compiler driver -# Used for : building command options for sub-processes -# -# See -# for a documentation of spec files. - - -# If you intend to use an existing device specs file as a starting point -# for a new device spec file, make sure you are copying from a specs -# file for a device from the same core architecture and SP width. -# See for a description -# of how to use such own spec files. - -*avrlibc_startfile: - crtatmega406.o%s - -*avrlibc_devicelib: - %{!nodevicelib:-latmega406} - -*cc1_n_flash: - %{!mn-flash=*:-mn-flash=1} - -*cc1_rmw: - %{mrmw} - -*cc1_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*cc1_absdata: - %{mabsdata} - -*asm_arch: - -mmcu=avr5 - -*asm_relax: - %{mrelax:--mlink-relax} - -*asm_rmw: - %{mrmw} - -*asm_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*link_pmem_wrap: - - -*link_relax: - %{mrelax:--relax} - -*link_arch: - %{mmcu=*:-m%*} - -*link_data_start: - -Tdata 0x800100 - -*link_text_start: - - -*self_spec: - %{!mmcu=avr*: % -# #elif ... -# -# If no device macro is defined, AVR-LibC uses __AVR_DEV_LIB_NAME__ -# as fallback to determine the name of the device header as -# -# "avr/io" + __AVR_DEV_LIB_NAME__ + ".h" -# -# If you provide your own specs file for a device not yet known to -# AVR-LibC, you can now define the hook macro __AVR_DEV_LIB_NAME__ -# as needed so that -# -# #include -# -# will include the desired device header. For ATmega8A the supplement -# to *cpp would read -# -# -D__AVR_DEV_LIB_NAME__=m8a - - -*cpp: - -D__AVR_ATmega406__ -D__AVR_DEVICE_NAME__=atmega406 - -# End of file diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega48 b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega48 deleted file mode 100644 index 632395f..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega48 +++ /dev/null @@ -1,99 +0,0 @@ -# -# Auto-generated specs for AVR device atmega48 (core avr4, 16-bit SP) -# -# Generated by : ./gcc/config/avr/gen-avr-mmcu-specs.c -# Generated from : ./gcc/config/gcc.c -# ./gcc/config/avr/specs.h -# ./gcc/config/avr/avrlibc.h -# Used by : avr-gcc compiler driver -# Used for : building command options for sub-processes -# -# See -# for a documentation of spec files. - - -# If you intend to use an existing device specs file as a starting point -# for a new device spec file, make sure you are copying from a specs -# file for a device from the same core architecture and SP width. -# See for a description -# of how to use such own spec files. - -*avrlibc_startfile: - crtatmega48.o%s - -*avrlibc_devicelib: - %{!nodevicelib:-latmega48} - -*cc1_n_flash: - %{!mn-flash=*:-mn-flash=1} - -*cc1_rmw: - %{mrmw} - -*cc1_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*cc1_absdata: - %{mabsdata} - -*asm_arch: - -mmcu=avr4 - -*asm_relax: - %{mrelax:--mlink-relax} - -*asm_rmw: - %{mrmw} - -*asm_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*link_pmem_wrap: - - -*link_relax: - %{mrelax:--relax} - -*link_arch: - %{mmcu=*:-m%*} - -*link_data_start: - -Tdata 0x800100 - -*link_text_start: - - -*self_spec: - %{!mmcu=avr*: % -# #elif ... -# -# If no device macro is defined, AVR-LibC uses __AVR_DEV_LIB_NAME__ -# as fallback to determine the name of the device header as -# -# "avr/io" + __AVR_DEV_LIB_NAME__ + ".h" -# -# If you provide your own specs file for a device not yet known to -# AVR-LibC, you can now define the hook macro __AVR_DEV_LIB_NAME__ -# as needed so that -# -# #include -# -# will include the desired device header. For ATmega8A the supplement -# to *cpp would read -# -# -D__AVR_DEV_LIB_NAME__=m8a - - -*cpp: - -D__AVR_ATmega48__ -D__AVR_DEVICE_NAME__=atmega48 - -# End of file diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega4808 b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega4808 deleted file mode 100644 index 33d5836..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega4808 +++ /dev/null @@ -1,104 +0,0 @@ -# -# Auto-generated specs for AVR device atmega4808 (core avrxmega3, 16-bit SP) -# -# Generated by : ./gcc/config/avr/gen-avr-mmcu-specs.c -# Generated from : ./gcc/config/gcc.c -# ./gcc/config/avr/specs.h -# ./gcc/config/avr/avrlibc.h -# Used by : avr-gcc compiler driver -# Used for : building command options for sub-processes -# -# See -# for a documentation of spec files. - - -# If you intend to use an existing device specs file as a starting point -# for a new device spec file, make sure you are copying from a specs -# file for a device from the same core architecture and SP width. -# See for a description -# of how to use such own spec files. - -*avrlibc_startfile: - crtatmega4808.o%s - -*avrlibc_devicelib: - %{!nodevicelib:-latmega4808} - -*cc1_n_flash: - %{!mn-flash=*:-mn-flash=1} - -*cc1_rmw: - %{mrmw} - -*cc1_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*cc1_absdata: - %{mabsdata} - -*asm_arch: - -mmcu=avrxmega3 - -*asm_relax: - %{mrelax:--mlink-relax} - -*asm_rmw: - %{mrmw} - -*asm_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*link_pmem_wrap: - - -*link_relax: - %{mrelax:--relax} - -*link_arch: - %{mmcu=*:-m%*} - -*link_data_start: - -Tdata 0x802800 - -*link_text_start: - - -*self_spec: - %{!mmcu=avr*: % -# #elif ... -# -# If no device macro is defined, AVR-LibC uses __AVR_DEV_LIB_NAME__ -# as fallback to determine the name of the device header as -# -# "avr/io" + __AVR_DEV_LIB_NAME__ + ".h" -# -# If you provide your own specs file for a device not yet known to -# AVR-LibC, you can now define the hook macro __AVR_DEV_LIB_NAME__ -# as needed so that -# -# #include -# -# will include the desired device header. For ATmega8A the supplement -# to *cpp would read -# -# -D__AVR_DEV_LIB_NAME__=m8a - - -*cpp: - -D__AVR_ATmega4808__ -D__AVR_DEVICE_NAME__=atmega4808 -D__AVR_DEV_LIB_NAME__=m4808 - -%rename link old_link - -*link: - %(old_link)--defsym=__RODATA_PM_OFFSET__=0x4000 - -# End of file diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega4809 b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega4809 deleted file mode 100644 index b63a419..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega4809 +++ /dev/null @@ -1,104 +0,0 @@ -# -# Auto-generated specs for AVR device atmega4809 (core avrxmega3, 16-bit SP) -# -# Generated by : ./gcc/config/avr/gen-avr-mmcu-specs.c -# Generated from : ./gcc/config/gcc.c -# ./gcc/config/avr/specs.h -# ./gcc/config/avr/avrlibc.h -# Used by : avr-gcc compiler driver -# Used for : building command options for sub-processes -# -# See -# for a documentation of spec files. - - -# If you intend to use an existing device specs file as a starting point -# for a new device spec file, make sure you are copying from a specs -# file for a device from the same core architecture and SP width. -# See for a description -# of how to use such own spec files. - -*avrlibc_startfile: - crtatmega4809.o%s - -*avrlibc_devicelib: - %{!nodevicelib:-latmega4809} - -*cc1_n_flash: - %{!mn-flash=*:-mn-flash=1} - -*cc1_rmw: - %{mrmw} - -*cc1_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*cc1_absdata: - %{mabsdata} - -*asm_arch: - -mmcu=avrxmega3 - -*asm_relax: - %{mrelax:--mlink-relax} - -*asm_rmw: - %{mrmw} - -*asm_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*link_pmem_wrap: - - -*link_relax: - %{mrelax:--relax} - -*link_arch: - %{mmcu=*:-m%*} - -*link_data_start: - -Tdata 0x802800 - -*link_text_start: - - -*self_spec: - %{!mmcu=avr*: % -# #elif ... -# -# If no device macro is defined, AVR-LibC uses __AVR_DEV_LIB_NAME__ -# as fallback to determine the name of the device header as -# -# "avr/io" + __AVR_DEV_LIB_NAME__ + ".h" -# -# If you provide your own specs file for a device not yet known to -# AVR-LibC, you can now define the hook macro __AVR_DEV_LIB_NAME__ -# as needed so that -# -# #include -# -# will include the desired device header. For ATmega8A the supplement -# to *cpp would read -# -# -D__AVR_DEV_LIB_NAME__=m8a - - -*cpp: - -D__AVR_ATmega4809__ -D__AVR_DEVICE_NAME__=atmega4809 -D__AVR_DEV_LIB_NAME__=m4809 - -%rename link old_link - -*link: - %(old_link)--defsym=__RODATA_PM_OFFSET__=0x4000 - -# End of file diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega48a b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega48a deleted file mode 100644 index 052b169..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega48a +++ /dev/null @@ -1,99 +0,0 @@ -# -# Auto-generated specs for AVR device atmega48a (core avr4, 16-bit SP) -# -# Generated by : ./gcc/config/avr/gen-avr-mmcu-specs.c -# Generated from : ./gcc/config/gcc.c -# ./gcc/config/avr/specs.h -# ./gcc/config/avr/avrlibc.h -# Used by : avr-gcc compiler driver -# Used for : building command options for sub-processes -# -# See -# for a documentation of spec files. - - -# If you intend to use an existing device specs file as a starting point -# for a new device spec file, make sure you are copying from a specs -# file for a device from the same core architecture and SP width. -# See for a description -# of how to use such own spec files. - -*avrlibc_startfile: - crtatmega48a.o%s - -*avrlibc_devicelib: - %{!nodevicelib:-latmega48a} - -*cc1_n_flash: - %{!mn-flash=*:-mn-flash=1} - -*cc1_rmw: - %{mrmw} - -*cc1_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*cc1_absdata: - %{mabsdata} - -*asm_arch: - -mmcu=avr4 - -*asm_relax: - %{mrelax:--mlink-relax} - -*asm_rmw: - %{mrmw} - -*asm_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*link_pmem_wrap: - - -*link_relax: - %{mrelax:--relax} - -*link_arch: - %{mmcu=*:-m%*} - -*link_data_start: - -Tdata 0x800100 - -*link_text_start: - - -*self_spec: - %{!mmcu=avr*: % -# #elif ... -# -# If no device macro is defined, AVR-LibC uses __AVR_DEV_LIB_NAME__ -# as fallback to determine the name of the device header as -# -# "avr/io" + __AVR_DEV_LIB_NAME__ + ".h" -# -# If you provide your own specs file for a device not yet known to -# AVR-LibC, you can now define the hook macro __AVR_DEV_LIB_NAME__ -# as needed so that -# -# #include -# -# will include the desired device header. For ATmega8A the supplement -# to *cpp would read -# -# -D__AVR_DEV_LIB_NAME__=m8a - - -*cpp: - -D__AVR_ATmega48A__ -D__AVR_DEVICE_NAME__=atmega48a - -# End of file diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega48p b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega48p deleted file mode 100644 index f2f74ea..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega48p +++ /dev/null @@ -1,99 +0,0 @@ -# -# Auto-generated specs for AVR device atmega48p (core avr4, 16-bit SP) -# -# Generated by : ./gcc/config/avr/gen-avr-mmcu-specs.c -# Generated from : ./gcc/config/gcc.c -# ./gcc/config/avr/specs.h -# ./gcc/config/avr/avrlibc.h -# Used by : avr-gcc compiler driver -# Used for : building command options for sub-processes -# -# See -# for a documentation of spec files. - - -# If you intend to use an existing device specs file as a starting point -# for a new device spec file, make sure you are copying from a specs -# file for a device from the same core architecture and SP width. -# See for a description -# of how to use such own spec files. - -*avrlibc_startfile: - crtatmega48p.o%s - -*avrlibc_devicelib: - %{!nodevicelib:-latmega48p} - -*cc1_n_flash: - %{!mn-flash=*:-mn-flash=1} - -*cc1_rmw: - %{mrmw} - -*cc1_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*cc1_absdata: - %{mabsdata} - -*asm_arch: - -mmcu=avr4 - -*asm_relax: - %{mrelax:--mlink-relax} - -*asm_rmw: - %{mrmw} - -*asm_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*link_pmem_wrap: - - -*link_relax: - %{mrelax:--relax} - -*link_arch: - %{mmcu=*:-m%*} - -*link_data_start: - -Tdata 0x800100 - -*link_text_start: - - -*self_spec: - %{!mmcu=avr*: % -# #elif ... -# -# If no device macro is defined, AVR-LibC uses __AVR_DEV_LIB_NAME__ -# as fallback to determine the name of the device header as -# -# "avr/io" + __AVR_DEV_LIB_NAME__ + ".h" -# -# If you provide your own specs file for a device not yet known to -# AVR-LibC, you can now define the hook macro __AVR_DEV_LIB_NAME__ -# as needed so that -# -# #include -# -# will include the desired device header. For ATmega8A the supplement -# to *cpp would read -# -# -D__AVR_DEV_LIB_NAME__=m8a - - -*cpp: - -D__AVR_ATmega48P__ -D__AVR_DEVICE_NAME__=atmega48p - -# End of file diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega48pa b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega48pa deleted file mode 100644 index 30c8089..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega48pa +++ /dev/null @@ -1,99 +0,0 @@ -# -# Auto-generated specs for AVR device atmega48pa (core avr4, 16-bit SP) -# -# Generated by : ./gcc/config/avr/gen-avr-mmcu-specs.c -# Generated from : ./gcc/config/gcc.c -# ./gcc/config/avr/specs.h -# ./gcc/config/avr/avrlibc.h -# Used by : avr-gcc compiler driver -# Used for : building command options for sub-processes -# -# See -# for a documentation of spec files. - - -# If you intend to use an existing device specs file as a starting point -# for a new device spec file, make sure you are copying from a specs -# file for a device from the same core architecture and SP width. -# See for a description -# of how to use such own spec files. - -*avrlibc_startfile: - crtatmega48pa.o%s - -*avrlibc_devicelib: - %{!nodevicelib:-latmega48pa} - -*cc1_n_flash: - %{!mn-flash=*:-mn-flash=1} - -*cc1_rmw: - %{mrmw} - -*cc1_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*cc1_absdata: - %{mabsdata} - -*asm_arch: - -mmcu=avr4 - -*asm_relax: - %{mrelax:--mlink-relax} - -*asm_rmw: - %{mrmw} - -*asm_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*link_pmem_wrap: - - -*link_relax: - %{mrelax:--relax} - -*link_arch: - %{mmcu=*:-m%*} - -*link_data_start: - -Tdata 0x800100 - -*link_text_start: - - -*self_spec: - %{!mmcu=avr*: % -# #elif ... -# -# If no device macro is defined, AVR-LibC uses __AVR_DEV_LIB_NAME__ -# as fallback to determine the name of the device header as -# -# "avr/io" + __AVR_DEV_LIB_NAME__ + ".h" -# -# If you provide your own specs file for a device not yet known to -# AVR-LibC, you can now define the hook macro __AVR_DEV_LIB_NAME__ -# as needed so that -# -# #include -# -# will include the desired device header. For ATmega8A the supplement -# to *cpp would read -# -# -D__AVR_DEV_LIB_NAME__=m8a - - -*cpp: - -D__AVR_ATmega48PA__ -D__AVR_DEVICE_NAME__=atmega48pa - -# End of file diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega48pb b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega48pb deleted file mode 100644 index 0f16362..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega48pb +++ /dev/null @@ -1,99 +0,0 @@ -# -# Auto-generated specs for AVR device atmega48pb (core avr4, 16-bit SP) -# -# Generated by : ./gcc/config/avr/gen-avr-mmcu-specs.c -# Generated from : ./gcc/config/gcc.c -# ./gcc/config/avr/specs.h -# ./gcc/config/avr/avrlibc.h -# Used by : avr-gcc compiler driver -# Used for : building command options for sub-processes -# -# See -# for a documentation of spec files. - - -# If you intend to use an existing device specs file as a starting point -# for a new device spec file, make sure you are copying from a specs -# file for a device from the same core architecture and SP width. -# See for a description -# of how to use such own spec files. - -*avrlibc_startfile: - crtatmega48pb.o%s - -*avrlibc_devicelib: - %{!nodevicelib:-latmega48pb} - -*cc1_n_flash: - %{!mn-flash=*:-mn-flash=1} - -*cc1_rmw: - %{mrmw} - -*cc1_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*cc1_absdata: - %{mabsdata} - -*asm_arch: - -mmcu=avr4 - -*asm_relax: - %{mrelax:--mlink-relax} - -*asm_rmw: - %{mrmw} - -*asm_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*link_pmem_wrap: - - -*link_relax: - %{mrelax:--relax} - -*link_arch: - %{mmcu=*:-m%*} - -*link_data_start: - -Tdata 0x800100 - -*link_text_start: - - -*self_spec: - %{!mmcu=avr*: % -# #elif ... -# -# If no device macro is defined, AVR-LibC uses __AVR_DEV_LIB_NAME__ -# as fallback to determine the name of the device header as -# -# "avr/io" + __AVR_DEV_LIB_NAME__ + ".h" -# -# If you provide your own specs file for a device not yet known to -# AVR-LibC, you can now define the hook macro __AVR_DEV_LIB_NAME__ -# as needed so that -# -# #include -# -# will include the desired device header. For ATmega8A the supplement -# to *cpp would read -# -# -D__AVR_DEV_LIB_NAME__=m8a - - -*cpp: - -D__AVR_ATmega48PB__ -D__AVR_DEVICE_NAME__=atmega48pb - -# End of file diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega64 b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega64 deleted file mode 100644 index 6d8e69f..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega64 +++ /dev/null @@ -1,99 +0,0 @@ -# -# Auto-generated specs for AVR device atmega64 (core avr5, 16-bit SP) -# -# Generated by : ./gcc/config/avr/gen-avr-mmcu-specs.c -# Generated from : ./gcc/config/gcc.c -# ./gcc/config/avr/specs.h -# ./gcc/config/avr/avrlibc.h -# Used by : avr-gcc compiler driver -# Used for : building command options for sub-processes -# -# See -# for a documentation of spec files. - - -# If you intend to use an existing device specs file as a starting point -# for a new device spec file, make sure you are copying from a specs -# file for a device from the same core architecture and SP width. -# See for a description -# of how to use such own spec files. - -*avrlibc_startfile: - crtatmega64.o%s - -*avrlibc_devicelib: - %{!nodevicelib:-latmega64} - -*cc1_n_flash: - %{!mn-flash=*:-mn-flash=1} - -*cc1_rmw: - %{mrmw} - -*cc1_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*cc1_absdata: - %{mabsdata} - -*asm_arch: - -mmcu=avr5 - -*asm_relax: - %{mrelax:--mlink-relax} - -*asm_rmw: - %{mrmw} - -*asm_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*link_pmem_wrap: - %{mpmem-wrap-around: --pmem-wrap-around=64k} - -*link_relax: - %{mrelax:--relax} - -*link_arch: - %{mmcu=*:-m%*} - -*link_data_start: - -Tdata 0x800100 - -*link_text_start: - - -*self_spec: - %{!mmcu=avr*: % -# #elif ... -# -# If no device macro is defined, AVR-LibC uses __AVR_DEV_LIB_NAME__ -# as fallback to determine the name of the device header as -# -# "avr/io" + __AVR_DEV_LIB_NAME__ + ".h" -# -# If you provide your own specs file for a device not yet known to -# AVR-LibC, you can now define the hook macro __AVR_DEV_LIB_NAME__ -# as needed so that -# -# #include -# -# will include the desired device header. For ATmega8A the supplement -# to *cpp would read -# -# -D__AVR_DEV_LIB_NAME__=m8a - - -*cpp: - -D__AVR_ATmega64__ -D__AVR_DEVICE_NAME__=atmega64 - -# End of file diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega640 b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega640 deleted file mode 100644 index dc1587b..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega640 +++ /dev/null @@ -1,99 +0,0 @@ -# -# Auto-generated specs for AVR device atmega640 (core avr5, 16-bit SP) -# -# Generated by : ./gcc/config/avr/gen-avr-mmcu-specs.c -# Generated from : ./gcc/config/gcc.c -# ./gcc/config/avr/specs.h -# ./gcc/config/avr/avrlibc.h -# Used by : avr-gcc compiler driver -# Used for : building command options for sub-processes -# -# See -# for a documentation of spec files. - - -# If you intend to use an existing device specs file as a starting point -# for a new device spec file, make sure you are copying from a specs -# file for a device from the same core architecture and SP width. -# See for a description -# of how to use such own spec files. - -*avrlibc_startfile: - crtatmega640.o%s - -*avrlibc_devicelib: - %{!nodevicelib:-latmega640} - -*cc1_n_flash: - %{!mn-flash=*:-mn-flash=1} - -*cc1_rmw: - %{mrmw} - -*cc1_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*cc1_absdata: - %{mabsdata} - -*asm_arch: - -mmcu=avr5 - -*asm_relax: - %{mrelax:--mlink-relax} - -*asm_rmw: - %{mrmw} - -*asm_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*link_pmem_wrap: - %{mpmem-wrap-around: --pmem-wrap-around=64k} - -*link_relax: - %{mrelax:--relax} - -*link_arch: - %{mmcu=*:-m%*} - -*link_data_start: - -Tdata 0x800200 - -*link_text_start: - - -*self_spec: - %{!mmcu=avr*: % -# #elif ... -# -# If no device macro is defined, AVR-LibC uses __AVR_DEV_LIB_NAME__ -# as fallback to determine the name of the device header as -# -# "avr/io" + __AVR_DEV_LIB_NAME__ + ".h" -# -# If you provide your own specs file for a device not yet known to -# AVR-LibC, you can now define the hook macro __AVR_DEV_LIB_NAME__ -# as needed so that -# -# #include -# -# will include the desired device header. For ATmega8A the supplement -# to *cpp would read -# -# -D__AVR_DEV_LIB_NAME__=m8a - - -*cpp: - -D__AVR_ATmega640__ -D__AVR_DEVICE_NAME__=atmega640 - -# End of file diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega644 b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega644 deleted file mode 100644 index 2342085..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega644 +++ /dev/null @@ -1,99 +0,0 @@ -# -# Auto-generated specs for AVR device atmega644 (core avr5, 16-bit SP) -# -# Generated by : ./gcc/config/avr/gen-avr-mmcu-specs.c -# Generated from : ./gcc/config/gcc.c -# ./gcc/config/avr/specs.h -# ./gcc/config/avr/avrlibc.h -# Used by : avr-gcc compiler driver -# Used for : building command options for sub-processes -# -# See -# for a documentation of spec files. - - -# If you intend to use an existing device specs file as a starting point -# for a new device spec file, make sure you are copying from a specs -# file for a device from the same core architecture and SP width. -# See for a description -# of how to use such own spec files. - -*avrlibc_startfile: - crtatmega644.o%s - -*avrlibc_devicelib: - %{!nodevicelib:-latmega644} - -*cc1_n_flash: - %{!mn-flash=*:-mn-flash=1} - -*cc1_rmw: - %{mrmw} - -*cc1_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*cc1_absdata: - %{mabsdata} - -*asm_arch: - -mmcu=avr5 - -*asm_relax: - %{mrelax:--mlink-relax} - -*asm_rmw: - %{mrmw} - -*asm_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*link_pmem_wrap: - %{mpmem-wrap-around: --pmem-wrap-around=64k} - -*link_relax: - %{mrelax:--relax} - -*link_arch: - %{mmcu=*:-m%*} - -*link_data_start: - -Tdata 0x800100 - -*link_text_start: - - -*self_spec: - %{!mmcu=avr*: % -# #elif ... -# -# If no device macro is defined, AVR-LibC uses __AVR_DEV_LIB_NAME__ -# as fallback to determine the name of the device header as -# -# "avr/io" + __AVR_DEV_LIB_NAME__ + ".h" -# -# If you provide your own specs file for a device not yet known to -# AVR-LibC, you can now define the hook macro __AVR_DEV_LIB_NAME__ -# as needed so that -# -# #include -# -# will include the desired device header. For ATmega8A the supplement -# to *cpp would read -# -# -D__AVR_DEV_LIB_NAME__=m8a - - -*cpp: - -D__AVR_ATmega644__ -D__AVR_DEVICE_NAME__=atmega644 - -# End of file diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega644a b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega644a deleted file mode 100644 index 07ca7d3..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega644a +++ /dev/null @@ -1,99 +0,0 @@ -# -# Auto-generated specs for AVR device atmega644a (core avr5, 16-bit SP) -# -# Generated by : ./gcc/config/avr/gen-avr-mmcu-specs.c -# Generated from : ./gcc/config/gcc.c -# ./gcc/config/avr/specs.h -# ./gcc/config/avr/avrlibc.h -# Used by : avr-gcc compiler driver -# Used for : building command options for sub-processes -# -# See -# for a documentation of spec files. - - -# If you intend to use an existing device specs file as a starting point -# for a new device spec file, make sure you are copying from a specs -# file for a device from the same core architecture and SP width. -# See for a description -# of how to use such own spec files. - -*avrlibc_startfile: - crtatmega644a.o%s - -*avrlibc_devicelib: - %{!nodevicelib:-latmega644a} - -*cc1_n_flash: - %{!mn-flash=*:-mn-flash=1} - -*cc1_rmw: - %{mrmw} - -*cc1_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*cc1_absdata: - %{mabsdata} - -*asm_arch: - -mmcu=avr5 - -*asm_relax: - %{mrelax:--mlink-relax} - -*asm_rmw: - %{mrmw} - -*asm_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*link_pmem_wrap: - %{mpmem-wrap-around: --pmem-wrap-around=64k} - -*link_relax: - %{mrelax:--relax} - -*link_arch: - %{mmcu=*:-m%*} - -*link_data_start: - -Tdata 0x800100 - -*link_text_start: - - -*self_spec: - %{!mmcu=avr*: % -# #elif ... -# -# If no device macro is defined, AVR-LibC uses __AVR_DEV_LIB_NAME__ -# as fallback to determine the name of the device header as -# -# "avr/io" + __AVR_DEV_LIB_NAME__ + ".h" -# -# If you provide your own specs file for a device not yet known to -# AVR-LibC, you can now define the hook macro __AVR_DEV_LIB_NAME__ -# as needed so that -# -# #include -# -# will include the desired device header. For ATmega8A the supplement -# to *cpp would read -# -# -D__AVR_DEV_LIB_NAME__=m8a - - -*cpp: - -D__AVR_ATmega644A__ -D__AVR_DEVICE_NAME__=atmega644a - -# End of file diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega644p b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega644p deleted file mode 100644 index a2dc2f0..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega644p +++ /dev/null @@ -1,99 +0,0 @@ -# -# Auto-generated specs for AVR device atmega644p (core avr5, 16-bit SP) -# -# Generated by : ./gcc/config/avr/gen-avr-mmcu-specs.c -# Generated from : ./gcc/config/gcc.c -# ./gcc/config/avr/specs.h -# ./gcc/config/avr/avrlibc.h -# Used by : avr-gcc compiler driver -# Used for : building command options for sub-processes -# -# See -# for a documentation of spec files. - - -# If you intend to use an existing device specs file as a starting point -# for a new device spec file, make sure you are copying from a specs -# file for a device from the same core architecture and SP width. -# See for a description -# of how to use such own spec files. - -*avrlibc_startfile: - crtatmega644p.o%s - -*avrlibc_devicelib: - %{!nodevicelib:-latmega644p} - -*cc1_n_flash: - %{!mn-flash=*:-mn-flash=1} - -*cc1_rmw: - %{mrmw} - -*cc1_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*cc1_absdata: - %{mabsdata} - -*asm_arch: - -mmcu=avr5 - -*asm_relax: - %{mrelax:--mlink-relax} - -*asm_rmw: - %{mrmw} - -*asm_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*link_pmem_wrap: - %{mpmem-wrap-around: --pmem-wrap-around=64k} - -*link_relax: - %{mrelax:--relax} - -*link_arch: - %{mmcu=*:-m%*} - -*link_data_start: - -Tdata 0x800100 - -*link_text_start: - - -*self_spec: - %{!mmcu=avr*: % -# #elif ... -# -# If no device macro is defined, AVR-LibC uses __AVR_DEV_LIB_NAME__ -# as fallback to determine the name of the device header as -# -# "avr/io" + __AVR_DEV_LIB_NAME__ + ".h" -# -# If you provide your own specs file for a device not yet known to -# AVR-LibC, you can now define the hook macro __AVR_DEV_LIB_NAME__ -# as needed so that -# -# #include -# -# will include the desired device header. For ATmega8A the supplement -# to *cpp would read -# -# -D__AVR_DEV_LIB_NAME__=m8a - - -*cpp: - -D__AVR_ATmega644P__ -D__AVR_DEVICE_NAME__=atmega644p - -# End of file diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega644pa b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega644pa deleted file mode 100644 index 7fa55bd..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega644pa +++ /dev/null @@ -1,99 +0,0 @@ -# -# Auto-generated specs for AVR device atmega644pa (core avr5, 16-bit SP) -# -# Generated by : ./gcc/config/avr/gen-avr-mmcu-specs.c -# Generated from : ./gcc/config/gcc.c -# ./gcc/config/avr/specs.h -# ./gcc/config/avr/avrlibc.h -# Used by : avr-gcc compiler driver -# Used for : building command options for sub-processes -# -# See -# for a documentation of spec files. - - -# If you intend to use an existing device specs file as a starting point -# for a new device spec file, make sure you are copying from a specs -# file for a device from the same core architecture and SP width. -# See for a description -# of how to use such own spec files. - -*avrlibc_startfile: - crtatmega644pa.o%s - -*avrlibc_devicelib: - %{!nodevicelib:-latmega644pa} - -*cc1_n_flash: - %{!mn-flash=*:-mn-flash=1} - -*cc1_rmw: - %{mrmw} - -*cc1_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*cc1_absdata: - %{mabsdata} - -*asm_arch: - -mmcu=avr5 - -*asm_relax: - %{mrelax:--mlink-relax} - -*asm_rmw: - %{mrmw} - -*asm_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*link_pmem_wrap: - %{mpmem-wrap-around: --pmem-wrap-around=64k} - -*link_relax: - %{mrelax:--relax} - -*link_arch: - %{mmcu=*:-m%*} - -*link_data_start: - -Tdata 0x800100 - -*link_text_start: - - -*self_spec: - %{!mmcu=avr*: % -# #elif ... -# -# If no device macro is defined, AVR-LibC uses __AVR_DEV_LIB_NAME__ -# as fallback to determine the name of the device header as -# -# "avr/io" + __AVR_DEV_LIB_NAME__ + ".h" -# -# If you provide your own specs file for a device not yet known to -# AVR-LibC, you can now define the hook macro __AVR_DEV_LIB_NAME__ -# as needed so that -# -# #include -# -# will include the desired device header. For ATmega8A the supplement -# to *cpp would read -# -# -D__AVR_DEV_LIB_NAME__=m8a - - -*cpp: - -D__AVR_ATmega644PA__ -D__AVR_DEVICE_NAME__=atmega644pa - -# End of file diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega644rfr2 b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega644rfr2 deleted file mode 100644 index f516502..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega644rfr2 +++ /dev/null @@ -1,99 +0,0 @@ -# -# Auto-generated specs for AVR device atmega644rfr2 (core avr5, 16-bit SP) -# -# Generated by : ./gcc/config/avr/gen-avr-mmcu-specs.c -# Generated from : ./gcc/config/gcc.c -# ./gcc/config/avr/specs.h -# ./gcc/config/avr/avrlibc.h -# Used by : avr-gcc compiler driver -# Used for : building command options for sub-processes -# -# See -# for a documentation of spec files. - - -# If you intend to use an existing device specs file as a starting point -# for a new device spec file, make sure you are copying from a specs -# file for a device from the same core architecture and SP width. -# See for a description -# of how to use such own spec files. - -*avrlibc_startfile: - crtatmega644rfr2.o%s - -*avrlibc_devicelib: - %{!nodevicelib:-latmega644rfr2} - -*cc1_n_flash: - %{!mn-flash=*:-mn-flash=1} - -*cc1_rmw: - %{mrmw} - -*cc1_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*cc1_absdata: - %{mabsdata} - -*asm_arch: - -mmcu=avr5 - -*asm_relax: - %{mrelax:--mlink-relax} - -*asm_rmw: - %{mrmw} - -*asm_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*link_pmem_wrap: - %{mpmem-wrap-around: --pmem-wrap-around=64k} - -*link_relax: - %{mrelax:--relax} - -*link_arch: - %{mmcu=*:-m%*} - -*link_data_start: - -Tdata 0x800200 - -*link_text_start: - - -*self_spec: - %{!mmcu=avr*: % -# #elif ... -# -# If no device macro is defined, AVR-LibC uses __AVR_DEV_LIB_NAME__ -# as fallback to determine the name of the device header as -# -# "avr/io" + __AVR_DEV_LIB_NAME__ + ".h" -# -# If you provide your own specs file for a device not yet known to -# AVR-LibC, you can now define the hook macro __AVR_DEV_LIB_NAME__ -# as needed so that -# -# #include -# -# will include the desired device header. For ATmega8A the supplement -# to *cpp would read -# -# -D__AVR_DEV_LIB_NAME__=m8a - - -*cpp: - -D__AVR_ATmega644RFR2__ -D__AVR_DEVICE_NAME__=atmega644rfr2 - -# End of file diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega645 b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega645 deleted file mode 100644 index 5139641..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega645 +++ /dev/null @@ -1,99 +0,0 @@ -# -# Auto-generated specs for AVR device atmega645 (core avr5, 16-bit SP) -# -# Generated by : ./gcc/config/avr/gen-avr-mmcu-specs.c -# Generated from : ./gcc/config/gcc.c -# ./gcc/config/avr/specs.h -# ./gcc/config/avr/avrlibc.h -# Used by : avr-gcc compiler driver -# Used for : building command options for sub-processes -# -# See -# for a documentation of spec files. - - -# If you intend to use an existing device specs file as a starting point -# for a new device spec file, make sure you are copying from a specs -# file for a device from the same core architecture and SP width. -# See for a description -# of how to use such own spec files. - -*avrlibc_startfile: - crtatmega645.o%s - -*avrlibc_devicelib: - %{!nodevicelib:-latmega645} - -*cc1_n_flash: - %{!mn-flash=*:-mn-flash=1} - -*cc1_rmw: - %{mrmw} - -*cc1_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*cc1_absdata: - %{mabsdata} - -*asm_arch: - -mmcu=avr5 - -*asm_relax: - %{mrelax:--mlink-relax} - -*asm_rmw: - %{mrmw} - -*asm_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*link_pmem_wrap: - %{mpmem-wrap-around: --pmem-wrap-around=64k} - -*link_relax: - %{mrelax:--relax} - -*link_arch: - %{mmcu=*:-m%*} - -*link_data_start: - -Tdata 0x800100 - -*link_text_start: - - -*self_spec: - %{!mmcu=avr*: % -# #elif ... -# -# If no device macro is defined, AVR-LibC uses __AVR_DEV_LIB_NAME__ -# as fallback to determine the name of the device header as -# -# "avr/io" + __AVR_DEV_LIB_NAME__ + ".h" -# -# If you provide your own specs file for a device not yet known to -# AVR-LibC, you can now define the hook macro __AVR_DEV_LIB_NAME__ -# as needed so that -# -# #include -# -# will include the desired device header. For ATmega8A the supplement -# to *cpp would read -# -# -D__AVR_DEV_LIB_NAME__=m8a - - -*cpp: - -D__AVR_ATmega645__ -D__AVR_DEVICE_NAME__=atmega645 - -# End of file diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega6450 b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega6450 deleted file mode 100644 index 9792588..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega6450 +++ /dev/null @@ -1,99 +0,0 @@ -# -# Auto-generated specs for AVR device atmega6450 (core avr5, 16-bit SP) -# -# Generated by : ./gcc/config/avr/gen-avr-mmcu-specs.c -# Generated from : ./gcc/config/gcc.c -# ./gcc/config/avr/specs.h -# ./gcc/config/avr/avrlibc.h -# Used by : avr-gcc compiler driver -# Used for : building command options for sub-processes -# -# See -# for a documentation of spec files. - - -# If you intend to use an existing device specs file as a starting point -# for a new device spec file, make sure you are copying from a specs -# file for a device from the same core architecture and SP width. -# See for a description -# of how to use such own spec files. - -*avrlibc_startfile: - crtatmega6450.o%s - -*avrlibc_devicelib: - %{!nodevicelib:-latmega6450} - -*cc1_n_flash: - %{!mn-flash=*:-mn-flash=1} - -*cc1_rmw: - %{mrmw} - -*cc1_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*cc1_absdata: - %{mabsdata} - -*asm_arch: - -mmcu=avr5 - -*asm_relax: - %{mrelax:--mlink-relax} - -*asm_rmw: - %{mrmw} - -*asm_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*link_pmem_wrap: - %{mpmem-wrap-around: --pmem-wrap-around=64k} - -*link_relax: - %{mrelax:--relax} - -*link_arch: - %{mmcu=*:-m%*} - -*link_data_start: - -Tdata 0x800100 - -*link_text_start: - - -*self_spec: - %{!mmcu=avr*: % -# #elif ... -# -# If no device macro is defined, AVR-LibC uses __AVR_DEV_LIB_NAME__ -# as fallback to determine the name of the device header as -# -# "avr/io" + __AVR_DEV_LIB_NAME__ + ".h" -# -# If you provide your own specs file for a device not yet known to -# AVR-LibC, you can now define the hook macro __AVR_DEV_LIB_NAME__ -# as needed so that -# -# #include -# -# will include the desired device header. For ATmega8A the supplement -# to *cpp would read -# -# -D__AVR_DEV_LIB_NAME__=m8a - - -*cpp: - -D__AVR_ATmega6450__ -D__AVR_DEVICE_NAME__=atmega6450 - -# End of file diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega6450a b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega6450a deleted file mode 100644 index 3bcfced..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega6450a +++ /dev/null @@ -1,99 +0,0 @@ -# -# Auto-generated specs for AVR device atmega6450a (core avr5, 16-bit SP) -# -# Generated by : ./gcc/config/avr/gen-avr-mmcu-specs.c -# Generated from : ./gcc/config/gcc.c -# ./gcc/config/avr/specs.h -# ./gcc/config/avr/avrlibc.h -# Used by : avr-gcc compiler driver -# Used for : building command options for sub-processes -# -# See -# for a documentation of spec files. - - -# If you intend to use an existing device specs file as a starting point -# for a new device spec file, make sure you are copying from a specs -# file for a device from the same core architecture and SP width. -# See for a description -# of how to use such own spec files. - -*avrlibc_startfile: - crtatmega6450a.o%s - -*avrlibc_devicelib: - %{!nodevicelib:-latmega6450a} - -*cc1_n_flash: - %{!mn-flash=*:-mn-flash=1} - -*cc1_rmw: - %{mrmw} - -*cc1_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*cc1_absdata: - %{mabsdata} - -*asm_arch: - -mmcu=avr5 - -*asm_relax: - %{mrelax:--mlink-relax} - -*asm_rmw: - %{mrmw} - -*asm_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*link_pmem_wrap: - %{mpmem-wrap-around: --pmem-wrap-around=64k} - -*link_relax: - %{mrelax:--relax} - -*link_arch: - %{mmcu=*:-m%*} - -*link_data_start: - -Tdata 0x800100 - -*link_text_start: - - -*self_spec: - %{!mmcu=avr*: % -# #elif ... -# -# If no device macro is defined, AVR-LibC uses __AVR_DEV_LIB_NAME__ -# as fallback to determine the name of the device header as -# -# "avr/io" + __AVR_DEV_LIB_NAME__ + ".h" -# -# If you provide your own specs file for a device not yet known to -# AVR-LibC, you can now define the hook macro __AVR_DEV_LIB_NAME__ -# as needed so that -# -# #include -# -# will include the desired device header. For ATmega8A the supplement -# to *cpp would read -# -# -D__AVR_DEV_LIB_NAME__=m8a - - -*cpp: - -D__AVR_ATmega6450A__ -D__AVR_DEVICE_NAME__=atmega6450a - -# End of file diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega6450p b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega6450p deleted file mode 100644 index a8984ea..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega6450p +++ /dev/null @@ -1,99 +0,0 @@ -# -# Auto-generated specs for AVR device atmega6450p (core avr5, 16-bit SP) -# -# Generated by : ./gcc/config/avr/gen-avr-mmcu-specs.c -# Generated from : ./gcc/config/gcc.c -# ./gcc/config/avr/specs.h -# ./gcc/config/avr/avrlibc.h -# Used by : avr-gcc compiler driver -# Used for : building command options for sub-processes -# -# See -# for a documentation of spec files. - - -# If you intend to use an existing device specs file as a starting point -# for a new device spec file, make sure you are copying from a specs -# file for a device from the same core architecture and SP width. -# See for a description -# of how to use such own spec files. - -*avrlibc_startfile: - crtatmega6450p.o%s - -*avrlibc_devicelib: - %{!nodevicelib:-latmega6450p} - -*cc1_n_flash: - %{!mn-flash=*:-mn-flash=1} - -*cc1_rmw: - %{mrmw} - -*cc1_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*cc1_absdata: - %{mabsdata} - -*asm_arch: - -mmcu=avr5 - -*asm_relax: - %{mrelax:--mlink-relax} - -*asm_rmw: - %{mrmw} - -*asm_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*link_pmem_wrap: - %{mpmem-wrap-around: --pmem-wrap-around=64k} - -*link_relax: - %{mrelax:--relax} - -*link_arch: - %{mmcu=*:-m%*} - -*link_data_start: - -Tdata 0x800100 - -*link_text_start: - - -*self_spec: - %{!mmcu=avr*: % -# #elif ... -# -# If no device macro is defined, AVR-LibC uses __AVR_DEV_LIB_NAME__ -# as fallback to determine the name of the device header as -# -# "avr/io" + __AVR_DEV_LIB_NAME__ + ".h" -# -# If you provide your own specs file for a device not yet known to -# AVR-LibC, you can now define the hook macro __AVR_DEV_LIB_NAME__ -# as needed so that -# -# #include -# -# will include the desired device header. For ATmega8A the supplement -# to *cpp would read -# -# -D__AVR_DEV_LIB_NAME__=m8a - - -*cpp: - -D__AVR_ATmega6450P__ -D__AVR_DEVICE_NAME__=atmega6450p - -# End of file diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega645a b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega645a deleted file mode 100644 index 31ae612..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega645a +++ /dev/null @@ -1,99 +0,0 @@ -# -# Auto-generated specs for AVR device atmega645a (core avr5, 16-bit SP) -# -# Generated by : ./gcc/config/avr/gen-avr-mmcu-specs.c -# Generated from : ./gcc/config/gcc.c -# ./gcc/config/avr/specs.h -# ./gcc/config/avr/avrlibc.h -# Used by : avr-gcc compiler driver -# Used for : building command options for sub-processes -# -# See -# for a documentation of spec files. - - -# If you intend to use an existing device specs file as a starting point -# for a new device spec file, make sure you are copying from a specs -# file for a device from the same core architecture and SP width. -# See for a description -# of how to use such own spec files. - -*avrlibc_startfile: - crtatmega645a.o%s - -*avrlibc_devicelib: - %{!nodevicelib:-latmega645a} - -*cc1_n_flash: - %{!mn-flash=*:-mn-flash=1} - -*cc1_rmw: - %{mrmw} - -*cc1_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*cc1_absdata: - %{mabsdata} - -*asm_arch: - -mmcu=avr5 - -*asm_relax: - %{mrelax:--mlink-relax} - -*asm_rmw: - %{mrmw} - -*asm_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*link_pmem_wrap: - %{mpmem-wrap-around: --pmem-wrap-around=64k} - -*link_relax: - %{mrelax:--relax} - -*link_arch: - %{mmcu=*:-m%*} - -*link_data_start: - -Tdata 0x800100 - -*link_text_start: - - -*self_spec: - %{!mmcu=avr*: % -# #elif ... -# -# If no device macro is defined, AVR-LibC uses __AVR_DEV_LIB_NAME__ -# as fallback to determine the name of the device header as -# -# "avr/io" + __AVR_DEV_LIB_NAME__ + ".h" -# -# If you provide your own specs file for a device not yet known to -# AVR-LibC, you can now define the hook macro __AVR_DEV_LIB_NAME__ -# as needed so that -# -# #include -# -# will include the desired device header. For ATmega8A the supplement -# to *cpp would read -# -# -D__AVR_DEV_LIB_NAME__=m8a - - -*cpp: - -D__AVR_ATmega645A__ -D__AVR_DEVICE_NAME__=atmega645a - -# End of file diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega645p b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega645p deleted file mode 100644 index fb72607..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega645p +++ /dev/null @@ -1,99 +0,0 @@ -# -# Auto-generated specs for AVR device atmega645p (core avr5, 16-bit SP) -# -# Generated by : ./gcc/config/avr/gen-avr-mmcu-specs.c -# Generated from : ./gcc/config/gcc.c -# ./gcc/config/avr/specs.h -# ./gcc/config/avr/avrlibc.h -# Used by : avr-gcc compiler driver -# Used for : building command options for sub-processes -# -# See -# for a documentation of spec files. - - -# If you intend to use an existing device specs file as a starting point -# for a new device spec file, make sure you are copying from a specs -# file for a device from the same core architecture and SP width. -# See for a description -# of how to use such own spec files. - -*avrlibc_startfile: - crtatmega645p.o%s - -*avrlibc_devicelib: - %{!nodevicelib:-latmega645p} - -*cc1_n_flash: - %{!mn-flash=*:-mn-flash=1} - -*cc1_rmw: - %{mrmw} - -*cc1_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*cc1_absdata: - %{mabsdata} - -*asm_arch: - -mmcu=avr5 - -*asm_relax: - %{mrelax:--mlink-relax} - -*asm_rmw: - %{mrmw} - -*asm_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*link_pmem_wrap: - %{mpmem-wrap-around: --pmem-wrap-around=64k} - -*link_relax: - %{mrelax:--relax} - -*link_arch: - %{mmcu=*:-m%*} - -*link_data_start: - -Tdata 0x800100 - -*link_text_start: - - -*self_spec: - %{!mmcu=avr*: % -# #elif ... -# -# If no device macro is defined, AVR-LibC uses __AVR_DEV_LIB_NAME__ -# as fallback to determine the name of the device header as -# -# "avr/io" + __AVR_DEV_LIB_NAME__ + ".h" -# -# If you provide your own specs file for a device not yet known to -# AVR-LibC, you can now define the hook macro __AVR_DEV_LIB_NAME__ -# as needed so that -# -# #include -# -# will include the desired device header. For ATmega8A the supplement -# to *cpp would read -# -# -D__AVR_DEV_LIB_NAME__=m8a - - -*cpp: - -D__AVR_ATmega645P__ -D__AVR_DEVICE_NAME__=atmega645p - -# End of file diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega649 b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega649 deleted file mode 100644 index 63c8ec4..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega649 +++ /dev/null @@ -1,99 +0,0 @@ -# -# Auto-generated specs for AVR device atmega649 (core avr5, 16-bit SP) -# -# Generated by : ./gcc/config/avr/gen-avr-mmcu-specs.c -# Generated from : ./gcc/config/gcc.c -# ./gcc/config/avr/specs.h -# ./gcc/config/avr/avrlibc.h -# Used by : avr-gcc compiler driver -# Used for : building command options for sub-processes -# -# See -# for a documentation of spec files. - - -# If you intend to use an existing device specs file as a starting point -# for a new device spec file, make sure you are copying from a specs -# file for a device from the same core architecture and SP width. -# See for a description -# of how to use such own spec files. - -*avrlibc_startfile: - crtatmega649.o%s - -*avrlibc_devicelib: - %{!nodevicelib:-latmega649} - -*cc1_n_flash: - %{!mn-flash=*:-mn-flash=1} - -*cc1_rmw: - %{mrmw} - -*cc1_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*cc1_absdata: - %{mabsdata} - -*asm_arch: - -mmcu=avr5 - -*asm_relax: - %{mrelax:--mlink-relax} - -*asm_rmw: - %{mrmw} - -*asm_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*link_pmem_wrap: - %{mpmem-wrap-around: --pmem-wrap-around=64k} - -*link_relax: - %{mrelax:--relax} - -*link_arch: - %{mmcu=*:-m%*} - -*link_data_start: - -Tdata 0x800100 - -*link_text_start: - - -*self_spec: - %{!mmcu=avr*: % -# #elif ... -# -# If no device macro is defined, AVR-LibC uses __AVR_DEV_LIB_NAME__ -# as fallback to determine the name of the device header as -# -# "avr/io" + __AVR_DEV_LIB_NAME__ + ".h" -# -# If you provide your own specs file for a device not yet known to -# AVR-LibC, you can now define the hook macro __AVR_DEV_LIB_NAME__ -# as needed so that -# -# #include -# -# will include the desired device header. For ATmega8A the supplement -# to *cpp would read -# -# -D__AVR_DEV_LIB_NAME__=m8a - - -*cpp: - -D__AVR_ATmega649__ -D__AVR_DEVICE_NAME__=atmega649 - -# End of file diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega6490 b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega6490 deleted file mode 100644 index bce1c76..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega6490 +++ /dev/null @@ -1,99 +0,0 @@ -# -# Auto-generated specs for AVR device atmega6490 (core avr5, 16-bit SP) -# -# Generated by : ./gcc/config/avr/gen-avr-mmcu-specs.c -# Generated from : ./gcc/config/gcc.c -# ./gcc/config/avr/specs.h -# ./gcc/config/avr/avrlibc.h -# Used by : avr-gcc compiler driver -# Used for : building command options for sub-processes -# -# See -# for a documentation of spec files. - - -# If you intend to use an existing device specs file as a starting point -# for a new device spec file, make sure you are copying from a specs -# file for a device from the same core architecture and SP width. -# See for a description -# of how to use such own spec files. - -*avrlibc_startfile: - crtatmega6490.o%s - -*avrlibc_devicelib: - %{!nodevicelib:-latmega6490} - -*cc1_n_flash: - %{!mn-flash=*:-mn-flash=1} - -*cc1_rmw: - %{mrmw} - -*cc1_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*cc1_absdata: - %{mabsdata} - -*asm_arch: - -mmcu=avr5 - -*asm_relax: - %{mrelax:--mlink-relax} - -*asm_rmw: - %{mrmw} - -*asm_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*link_pmem_wrap: - %{mpmem-wrap-around: --pmem-wrap-around=64k} - -*link_relax: - %{mrelax:--relax} - -*link_arch: - %{mmcu=*:-m%*} - -*link_data_start: - -Tdata 0x800100 - -*link_text_start: - - -*self_spec: - %{!mmcu=avr*: % -# #elif ... -# -# If no device macro is defined, AVR-LibC uses __AVR_DEV_LIB_NAME__ -# as fallback to determine the name of the device header as -# -# "avr/io" + __AVR_DEV_LIB_NAME__ + ".h" -# -# If you provide your own specs file for a device not yet known to -# AVR-LibC, you can now define the hook macro __AVR_DEV_LIB_NAME__ -# as needed so that -# -# #include -# -# will include the desired device header. For ATmega8A the supplement -# to *cpp would read -# -# -D__AVR_DEV_LIB_NAME__=m8a - - -*cpp: - -D__AVR_ATmega6490__ -D__AVR_DEVICE_NAME__=atmega6490 - -# End of file diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega6490a b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega6490a deleted file mode 100644 index 5dd060e..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega6490a +++ /dev/null @@ -1,99 +0,0 @@ -# -# Auto-generated specs for AVR device atmega6490a (core avr5, 16-bit SP) -# -# Generated by : ./gcc/config/avr/gen-avr-mmcu-specs.c -# Generated from : ./gcc/config/gcc.c -# ./gcc/config/avr/specs.h -# ./gcc/config/avr/avrlibc.h -# Used by : avr-gcc compiler driver -# Used for : building command options for sub-processes -# -# See -# for a documentation of spec files. - - -# If you intend to use an existing device specs file as a starting point -# for a new device spec file, make sure you are copying from a specs -# file for a device from the same core architecture and SP width. -# See for a description -# of how to use such own spec files. - -*avrlibc_startfile: - crtatmega6490a.o%s - -*avrlibc_devicelib: - %{!nodevicelib:-latmega6490a} - -*cc1_n_flash: - %{!mn-flash=*:-mn-flash=1} - -*cc1_rmw: - %{mrmw} - -*cc1_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*cc1_absdata: - %{mabsdata} - -*asm_arch: - -mmcu=avr5 - -*asm_relax: - %{mrelax:--mlink-relax} - -*asm_rmw: - %{mrmw} - -*asm_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*link_pmem_wrap: - %{mpmem-wrap-around: --pmem-wrap-around=64k} - -*link_relax: - %{mrelax:--relax} - -*link_arch: - %{mmcu=*:-m%*} - -*link_data_start: - -Tdata 0x800100 - -*link_text_start: - - -*self_spec: - %{!mmcu=avr*: % -# #elif ... -# -# If no device macro is defined, AVR-LibC uses __AVR_DEV_LIB_NAME__ -# as fallback to determine the name of the device header as -# -# "avr/io" + __AVR_DEV_LIB_NAME__ + ".h" -# -# If you provide your own specs file for a device not yet known to -# AVR-LibC, you can now define the hook macro __AVR_DEV_LIB_NAME__ -# as needed so that -# -# #include -# -# will include the desired device header. For ATmega8A the supplement -# to *cpp would read -# -# -D__AVR_DEV_LIB_NAME__=m8a - - -*cpp: - -D__AVR_ATmega6490A__ -D__AVR_DEVICE_NAME__=atmega6490a - -# End of file diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega6490p b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega6490p deleted file mode 100644 index 8f61cb6..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega6490p +++ /dev/null @@ -1,99 +0,0 @@ -# -# Auto-generated specs for AVR device atmega6490p (core avr5, 16-bit SP) -# -# Generated by : ./gcc/config/avr/gen-avr-mmcu-specs.c -# Generated from : ./gcc/config/gcc.c -# ./gcc/config/avr/specs.h -# ./gcc/config/avr/avrlibc.h -# Used by : avr-gcc compiler driver -# Used for : building command options for sub-processes -# -# See -# for a documentation of spec files. - - -# If you intend to use an existing device specs file as a starting point -# for a new device spec file, make sure you are copying from a specs -# file for a device from the same core architecture and SP width. -# See for a description -# of how to use such own spec files. - -*avrlibc_startfile: - crtatmega6490p.o%s - -*avrlibc_devicelib: - %{!nodevicelib:-latmega6490p} - -*cc1_n_flash: - %{!mn-flash=*:-mn-flash=1} - -*cc1_rmw: - %{mrmw} - -*cc1_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*cc1_absdata: - %{mabsdata} - -*asm_arch: - -mmcu=avr5 - -*asm_relax: - %{mrelax:--mlink-relax} - -*asm_rmw: - %{mrmw} - -*asm_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*link_pmem_wrap: - %{mpmem-wrap-around: --pmem-wrap-around=64k} - -*link_relax: - %{mrelax:--relax} - -*link_arch: - %{mmcu=*:-m%*} - -*link_data_start: - -Tdata 0x800100 - -*link_text_start: - - -*self_spec: - %{!mmcu=avr*: % -# #elif ... -# -# If no device macro is defined, AVR-LibC uses __AVR_DEV_LIB_NAME__ -# as fallback to determine the name of the device header as -# -# "avr/io" + __AVR_DEV_LIB_NAME__ + ".h" -# -# If you provide your own specs file for a device not yet known to -# AVR-LibC, you can now define the hook macro __AVR_DEV_LIB_NAME__ -# as needed so that -# -# #include -# -# will include the desired device header. For ATmega8A the supplement -# to *cpp would read -# -# -D__AVR_DEV_LIB_NAME__=m8a - - -*cpp: - -D__AVR_ATmega6490P__ -D__AVR_DEVICE_NAME__=atmega6490p - -# End of file diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega649a b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega649a deleted file mode 100644 index f094d4b..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega649a +++ /dev/null @@ -1,99 +0,0 @@ -# -# Auto-generated specs for AVR device atmega649a (core avr5, 16-bit SP) -# -# Generated by : ./gcc/config/avr/gen-avr-mmcu-specs.c -# Generated from : ./gcc/config/gcc.c -# ./gcc/config/avr/specs.h -# ./gcc/config/avr/avrlibc.h -# Used by : avr-gcc compiler driver -# Used for : building command options for sub-processes -# -# See -# for a documentation of spec files. - - -# If you intend to use an existing device specs file as a starting point -# for a new device spec file, make sure you are copying from a specs -# file for a device from the same core architecture and SP width. -# See for a description -# of how to use such own spec files. - -*avrlibc_startfile: - crtatmega649a.o%s - -*avrlibc_devicelib: - %{!nodevicelib:-latmega649a} - -*cc1_n_flash: - %{!mn-flash=*:-mn-flash=1} - -*cc1_rmw: - %{mrmw} - -*cc1_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*cc1_absdata: - %{mabsdata} - -*asm_arch: - -mmcu=avr5 - -*asm_relax: - %{mrelax:--mlink-relax} - -*asm_rmw: - %{mrmw} - -*asm_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*link_pmem_wrap: - %{mpmem-wrap-around: --pmem-wrap-around=64k} - -*link_relax: - %{mrelax:--relax} - -*link_arch: - %{mmcu=*:-m%*} - -*link_data_start: - -Tdata 0x800100 - -*link_text_start: - - -*self_spec: - %{!mmcu=avr*: % -# #elif ... -# -# If no device macro is defined, AVR-LibC uses __AVR_DEV_LIB_NAME__ -# as fallback to determine the name of the device header as -# -# "avr/io" + __AVR_DEV_LIB_NAME__ + ".h" -# -# If you provide your own specs file for a device not yet known to -# AVR-LibC, you can now define the hook macro __AVR_DEV_LIB_NAME__ -# as needed so that -# -# #include -# -# will include the desired device header. For ATmega8A the supplement -# to *cpp would read -# -# -D__AVR_DEV_LIB_NAME__=m8a - - -*cpp: - -D__AVR_ATmega649A__ -D__AVR_DEVICE_NAME__=atmega649a - -# End of file diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega649p b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega649p deleted file mode 100644 index 05038f6..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega649p +++ /dev/null @@ -1,99 +0,0 @@ -# -# Auto-generated specs for AVR device atmega649p (core avr5, 16-bit SP) -# -# Generated by : ./gcc/config/avr/gen-avr-mmcu-specs.c -# Generated from : ./gcc/config/gcc.c -# ./gcc/config/avr/specs.h -# ./gcc/config/avr/avrlibc.h -# Used by : avr-gcc compiler driver -# Used for : building command options for sub-processes -# -# See -# for a documentation of spec files. - - -# If you intend to use an existing device specs file as a starting point -# for a new device spec file, make sure you are copying from a specs -# file for a device from the same core architecture and SP width. -# See for a description -# of how to use such own spec files. - -*avrlibc_startfile: - crtatmega649p.o%s - -*avrlibc_devicelib: - %{!nodevicelib:-latmega649p} - -*cc1_n_flash: - %{!mn-flash=*:-mn-flash=1} - -*cc1_rmw: - %{mrmw} - -*cc1_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*cc1_absdata: - %{mabsdata} - -*asm_arch: - -mmcu=avr5 - -*asm_relax: - %{mrelax:--mlink-relax} - -*asm_rmw: - %{mrmw} - -*asm_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*link_pmem_wrap: - %{mpmem-wrap-around: --pmem-wrap-around=64k} - -*link_relax: - %{mrelax:--relax} - -*link_arch: - %{mmcu=*:-m%*} - -*link_data_start: - -Tdata 0x800100 - -*link_text_start: - - -*self_spec: - %{!mmcu=avr*: % -# #elif ... -# -# If no device macro is defined, AVR-LibC uses __AVR_DEV_LIB_NAME__ -# as fallback to determine the name of the device header as -# -# "avr/io" + __AVR_DEV_LIB_NAME__ + ".h" -# -# If you provide your own specs file for a device not yet known to -# AVR-LibC, you can now define the hook macro __AVR_DEV_LIB_NAME__ -# as needed so that -# -# #include -# -# will include the desired device header. For ATmega8A the supplement -# to *cpp would read -# -# -D__AVR_DEV_LIB_NAME__=m8a - - -*cpp: - -D__AVR_ATmega649P__ -D__AVR_DEVICE_NAME__=atmega649p - -# End of file diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega64a b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega64a deleted file mode 100644 index ffd3b88..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega64a +++ /dev/null @@ -1,99 +0,0 @@ -# -# Auto-generated specs for AVR device atmega64a (core avr5, 16-bit SP) -# -# Generated by : ./gcc/config/avr/gen-avr-mmcu-specs.c -# Generated from : ./gcc/config/gcc.c -# ./gcc/config/avr/specs.h -# ./gcc/config/avr/avrlibc.h -# Used by : avr-gcc compiler driver -# Used for : building command options for sub-processes -# -# See -# for a documentation of spec files. - - -# If you intend to use an existing device specs file as a starting point -# for a new device spec file, make sure you are copying from a specs -# file for a device from the same core architecture and SP width. -# See for a description -# of how to use such own spec files. - -*avrlibc_startfile: - crtatmega64a.o%s - -*avrlibc_devicelib: - %{!nodevicelib:-latmega64a} - -*cc1_n_flash: - %{!mn-flash=*:-mn-flash=1} - -*cc1_rmw: - %{mrmw} - -*cc1_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*cc1_absdata: - %{mabsdata} - -*asm_arch: - -mmcu=avr5 - -*asm_relax: - %{mrelax:--mlink-relax} - -*asm_rmw: - %{mrmw} - -*asm_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*link_pmem_wrap: - %{mpmem-wrap-around: --pmem-wrap-around=64k} - -*link_relax: - %{mrelax:--relax} - -*link_arch: - %{mmcu=*:-m%*} - -*link_data_start: - -Tdata 0x800100 - -*link_text_start: - - -*self_spec: - %{!mmcu=avr*: % -# #elif ... -# -# If no device macro is defined, AVR-LibC uses __AVR_DEV_LIB_NAME__ -# as fallback to determine the name of the device header as -# -# "avr/io" + __AVR_DEV_LIB_NAME__ + ".h" -# -# If you provide your own specs file for a device not yet known to -# AVR-LibC, you can now define the hook macro __AVR_DEV_LIB_NAME__ -# as needed so that -# -# #include -# -# will include the desired device header. For ATmega8A the supplement -# to *cpp would read -# -# -D__AVR_DEV_LIB_NAME__=m8a - - -*cpp: - -D__AVR_ATmega64A__ -D__AVR_DEVICE_NAME__=atmega64a - -# End of file diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega64c1 b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega64c1 deleted file mode 100644 index 57e92fc..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega64c1 +++ /dev/null @@ -1,99 +0,0 @@ -# -# Auto-generated specs for AVR device atmega64c1 (core avr5, 16-bit SP) -# -# Generated by : ./gcc/config/avr/gen-avr-mmcu-specs.c -# Generated from : ./gcc/config/gcc.c -# ./gcc/config/avr/specs.h -# ./gcc/config/avr/avrlibc.h -# Used by : avr-gcc compiler driver -# Used for : building command options for sub-processes -# -# See -# for a documentation of spec files. - - -# If you intend to use an existing device specs file as a starting point -# for a new device spec file, make sure you are copying from a specs -# file for a device from the same core architecture and SP width. -# See for a description -# of how to use such own spec files. - -*avrlibc_startfile: - crtatmega64c1.o%s - -*avrlibc_devicelib: - %{!nodevicelib:-latmega64c1} - -*cc1_n_flash: - %{!mn-flash=*:-mn-flash=1} - -*cc1_rmw: - %{mrmw} - -*cc1_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*cc1_absdata: - %{mabsdata} - -*asm_arch: - -mmcu=avr5 - -*asm_relax: - %{mrelax:--mlink-relax} - -*asm_rmw: - %{mrmw} - -*asm_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*link_pmem_wrap: - %{mpmem-wrap-around: --pmem-wrap-around=64k} - -*link_relax: - %{mrelax:--relax} - -*link_arch: - %{mmcu=*:-m%*} - -*link_data_start: - -Tdata 0x800100 - -*link_text_start: - - -*self_spec: - %{!mmcu=avr*: % -# #elif ... -# -# If no device macro is defined, AVR-LibC uses __AVR_DEV_LIB_NAME__ -# as fallback to determine the name of the device header as -# -# "avr/io" + __AVR_DEV_LIB_NAME__ + ".h" -# -# If you provide your own specs file for a device not yet known to -# AVR-LibC, you can now define the hook macro __AVR_DEV_LIB_NAME__ -# as needed so that -# -# #include -# -# will include the desired device header. For ATmega8A the supplement -# to *cpp would read -# -# -D__AVR_DEV_LIB_NAME__=m8a - - -*cpp: - -D__AVR_ATmega64C1__ -D__AVR_DEVICE_NAME__=atmega64c1 - -# End of file diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega64hve b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega64hve deleted file mode 100644 index 2c4216b..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega64hve +++ /dev/null @@ -1,99 +0,0 @@ -# -# Auto-generated specs for AVR device atmega64hve (core avr5, 16-bit SP) -# -# Generated by : ./gcc/config/avr/gen-avr-mmcu-specs.c -# Generated from : ./gcc/config/gcc.c -# ./gcc/config/avr/specs.h -# ./gcc/config/avr/avrlibc.h -# Used by : avr-gcc compiler driver -# Used for : building command options for sub-processes -# -# See -# for a documentation of spec files. - - -# If you intend to use an existing device specs file as a starting point -# for a new device spec file, make sure you are copying from a specs -# file for a device from the same core architecture and SP width. -# See for a description -# of how to use such own spec files. - -*avrlibc_startfile: - crtatmega64hve.o%s - -*avrlibc_devicelib: - %{!nodevicelib:-latmega64hve} - -*cc1_n_flash: - %{!mn-flash=*:-mn-flash=1} - -*cc1_rmw: - %{mrmw} - -*cc1_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*cc1_absdata: - %{mabsdata} - -*asm_arch: - -mmcu=avr5 - -*asm_relax: - %{mrelax:--mlink-relax} - -*asm_rmw: - %{mrmw} - -*asm_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*link_pmem_wrap: - %{mpmem-wrap-around: --pmem-wrap-around=64k} - -*link_relax: - %{mrelax:--relax} - -*link_arch: - %{mmcu=*:-m%*} - -*link_data_start: - -Tdata 0x800100 - -*link_text_start: - - -*self_spec: - %{!mmcu=avr*: % -# #elif ... -# -# If no device macro is defined, AVR-LibC uses __AVR_DEV_LIB_NAME__ -# as fallback to determine the name of the device header as -# -# "avr/io" + __AVR_DEV_LIB_NAME__ + ".h" -# -# If you provide your own specs file for a device not yet known to -# AVR-LibC, you can now define the hook macro __AVR_DEV_LIB_NAME__ -# as needed so that -# -# #include -# -# will include the desired device header. For ATmega8A the supplement -# to *cpp would read -# -# -D__AVR_DEV_LIB_NAME__=m8a - - -*cpp: - -D__AVR_ATmega64HVE__ -D__AVR_DEVICE_NAME__=atmega64hve - -# End of file diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega64hve2 b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega64hve2 deleted file mode 100644 index 58d8646..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega64hve2 +++ /dev/null @@ -1,99 +0,0 @@ -# -# Auto-generated specs for AVR device atmega64hve2 (core avr5, 16-bit SP) -# -# Generated by : ./gcc/config/avr/gen-avr-mmcu-specs.c -# Generated from : ./gcc/config/gcc.c -# ./gcc/config/avr/specs.h -# ./gcc/config/avr/avrlibc.h -# Used by : avr-gcc compiler driver -# Used for : building command options for sub-processes -# -# See -# for a documentation of spec files. - - -# If you intend to use an existing device specs file as a starting point -# for a new device spec file, make sure you are copying from a specs -# file for a device from the same core architecture and SP width. -# See for a description -# of how to use such own spec files. - -*avrlibc_startfile: - crtatmega64hve2.o%s - -*avrlibc_devicelib: - %{!nodevicelib:-latmega64hve2} - -*cc1_n_flash: - %{!mn-flash=*:-mn-flash=1} - -*cc1_rmw: - %{mrmw} - -*cc1_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*cc1_absdata: - %{mabsdata} - -*asm_arch: - -mmcu=avr5 - -*asm_relax: - %{mrelax:--mlink-relax} - -*asm_rmw: - %{mrmw} - -*asm_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*link_pmem_wrap: - %{mpmem-wrap-around: --pmem-wrap-around=64k} - -*link_relax: - %{mrelax:--relax} - -*link_arch: - %{mmcu=*:-m%*} - -*link_data_start: - -Tdata 0x800100 - -*link_text_start: - - -*self_spec: - %{!mmcu=avr*: % -# #elif ... -# -# If no device macro is defined, AVR-LibC uses __AVR_DEV_LIB_NAME__ -# as fallback to determine the name of the device header as -# -# "avr/io" + __AVR_DEV_LIB_NAME__ + ".h" -# -# If you provide your own specs file for a device not yet known to -# AVR-LibC, you can now define the hook macro __AVR_DEV_LIB_NAME__ -# as needed so that -# -# #include -# -# will include the desired device header. For ATmega8A the supplement -# to *cpp would read -# -# -D__AVR_DEV_LIB_NAME__=m8a - - -*cpp: - -D__AVR_ATmega64HVE2__ -D__AVR_DEVICE_NAME__=atmega64hve2 - -# End of file diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega64m1 b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega64m1 deleted file mode 100644 index 2eb6681..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega64m1 +++ /dev/null @@ -1,99 +0,0 @@ -# -# Auto-generated specs for AVR device atmega64m1 (core avr5, 16-bit SP) -# -# Generated by : ./gcc/config/avr/gen-avr-mmcu-specs.c -# Generated from : ./gcc/config/gcc.c -# ./gcc/config/avr/specs.h -# ./gcc/config/avr/avrlibc.h -# Used by : avr-gcc compiler driver -# Used for : building command options for sub-processes -# -# See -# for a documentation of spec files. - - -# If you intend to use an existing device specs file as a starting point -# for a new device spec file, make sure you are copying from a specs -# file for a device from the same core architecture and SP width. -# See for a description -# of how to use such own spec files. - -*avrlibc_startfile: - crtatmega64m1.o%s - -*avrlibc_devicelib: - %{!nodevicelib:-latmega64m1} - -*cc1_n_flash: - %{!mn-flash=*:-mn-flash=1} - -*cc1_rmw: - %{mrmw} - -*cc1_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*cc1_absdata: - %{mabsdata} - -*asm_arch: - -mmcu=avr5 - -*asm_relax: - %{mrelax:--mlink-relax} - -*asm_rmw: - %{mrmw} - -*asm_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*link_pmem_wrap: - %{mpmem-wrap-around: --pmem-wrap-around=64k} - -*link_relax: - %{mrelax:--relax} - -*link_arch: - %{mmcu=*:-m%*} - -*link_data_start: - -Tdata 0x800100 - -*link_text_start: - - -*self_spec: - %{!mmcu=avr*: % -# #elif ... -# -# If no device macro is defined, AVR-LibC uses __AVR_DEV_LIB_NAME__ -# as fallback to determine the name of the device header as -# -# "avr/io" + __AVR_DEV_LIB_NAME__ + ".h" -# -# If you provide your own specs file for a device not yet known to -# AVR-LibC, you can now define the hook macro __AVR_DEV_LIB_NAME__ -# as needed so that -# -# #include -# -# will include the desired device header. For ATmega8A the supplement -# to *cpp would read -# -# -D__AVR_DEV_LIB_NAME__=m8a - - -*cpp: - -D__AVR_ATmega64M1__ -D__AVR_DEVICE_NAME__=atmega64m1 - -# End of file diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega64rfr2 b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega64rfr2 deleted file mode 100644 index d9fe73b..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega64rfr2 +++ /dev/null @@ -1,99 +0,0 @@ -# -# Auto-generated specs for AVR device atmega64rfr2 (core avr5, 16-bit SP) -# -# Generated by : ./gcc/config/avr/gen-avr-mmcu-specs.c -# Generated from : ./gcc/config/gcc.c -# ./gcc/config/avr/specs.h -# ./gcc/config/avr/avrlibc.h -# Used by : avr-gcc compiler driver -# Used for : building command options for sub-processes -# -# See -# for a documentation of spec files. - - -# If you intend to use an existing device specs file as a starting point -# for a new device spec file, make sure you are copying from a specs -# file for a device from the same core architecture and SP width. -# See for a description -# of how to use such own spec files. - -*avrlibc_startfile: - crtatmega64rfr2.o%s - -*avrlibc_devicelib: - %{!nodevicelib:-latmega64rfr2} - -*cc1_n_flash: - %{!mn-flash=*:-mn-flash=1} - -*cc1_rmw: - %{mrmw} - -*cc1_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*cc1_absdata: - %{mabsdata} - -*asm_arch: - -mmcu=avr5 - -*asm_relax: - %{mrelax:--mlink-relax} - -*asm_rmw: - %{mrmw} - -*asm_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*link_pmem_wrap: - %{mpmem-wrap-around: --pmem-wrap-around=64k} - -*link_relax: - %{mrelax:--relax} - -*link_arch: - %{mmcu=*:-m%*} - -*link_data_start: - -Tdata 0x800200 - -*link_text_start: - - -*self_spec: - %{!mmcu=avr*: % -# #elif ... -# -# If no device macro is defined, AVR-LibC uses __AVR_DEV_LIB_NAME__ -# as fallback to determine the name of the device header as -# -# "avr/io" + __AVR_DEV_LIB_NAME__ + ".h" -# -# If you provide your own specs file for a device not yet known to -# AVR-LibC, you can now define the hook macro __AVR_DEV_LIB_NAME__ -# as needed so that -# -# #include -# -# will include the desired device header. For ATmega8A the supplement -# to *cpp would read -# -# -D__AVR_DEV_LIB_NAME__=m8a - - -*cpp: - -D__AVR_ATmega64RFR2__ -D__AVR_DEVICE_NAME__=atmega64rfr2 - -# End of file diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega8 b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega8 deleted file mode 100644 index 351032f..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega8 +++ /dev/null @@ -1,99 +0,0 @@ -# -# Auto-generated specs for AVR device atmega8 (core avr4, 16-bit SP) -# -# Generated by : ./gcc/config/avr/gen-avr-mmcu-specs.c -# Generated from : ./gcc/config/gcc.c -# ./gcc/config/avr/specs.h -# ./gcc/config/avr/avrlibc.h -# Used by : avr-gcc compiler driver -# Used for : building command options for sub-processes -# -# See -# for a documentation of spec files. - - -# If you intend to use an existing device specs file as a starting point -# for a new device spec file, make sure you are copying from a specs -# file for a device from the same core architecture and SP width. -# See for a description -# of how to use such own spec files. - -*avrlibc_startfile: - crtatmega8.o%s - -*avrlibc_devicelib: - %{!nodevicelib:-latmega8} - -*cc1_n_flash: - %{!mn-flash=*:-mn-flash=1} - -*cc1_rmw: - %{mrmw} - -*cc1_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*cc1_absdata: - %{mabsdata} - -*asm_arch: - -mmcu=avr4 - -*asm_relax: - %{mrelax:--mlink-relax} - -*asm_rmw: - %{mrmw} - -*asm_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*link_pmem_wrap: - %{!mno-pmem-wrap-around: --pmem-wrap-around=8k} - -*link_relax: - %{mrelax:--relax} - -*link_arch: - %{mmcu=*:-m%*} - -*link_data_start: - - -*link_text_start: - - -*self_spec: - %{!mmcu=avr*: % -# #elif ... -# -# If no device macro is defined, AVR-LibC uses __AVR_DEV_LIB_NAME__ -# as fallback to determine the name of the device header as -# -# "avr/io" + __AVR_DEV_LIB_NAME__ + ".h" -# -# If you provide your own specs file for a device not yet known to -# AVR-LibC, you can now define the hook macro __AVR_DEV_LIB_NAME__ -# as needed so that -# -# #include -# -# will include the desired device header. For ATmega8A the supplement -# to *cpp would read -# -# -D__AVR_DEV_LIB_NAME__=m8a - - -*cpp: - -D__AVR_ATmega8__ -D__AVR_DEVICE_NAME__=atmega8 - -# End of file diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega8515 b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega8515 deleted file mode 100644 index 3e9d1b1..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega8515 +++ /dev/null @@ -1,99 +0,0 @@ -# -# Auto-generated specs for AVR device atmega8515 (core avr4, 16-bit SP) -# -# Generated by : ./gcc/config/avr/gen-avr-mmcu-specs.c -# Generated from : ./gcc/config/gcc.c -# ./gcc/config/avr/specs.h -# ./gcc/config/avr/avrlibc.h -# Used by : avr-gcc compiler driver -# Used for : building command options for sub-processes -# -# See -# for a documentation of spec files. - - -# If you intend to use an existing device specs file as a starting point -# for a new device spec file, make sure you are copying from a specs -# file for a device from the same core architecture and SP width. -# See for a description -# of how to use such own spec files. - -*avrlibc_startfile: - crtatmega8515.o%s - -*avrlibc_devicelib: - %{!nodevicelib:-latmega8515} - -*cc1_n_flash: - %{!mn-flash=*:-mn-flash=1} - -*cc1_rmw: - %{mrmw} - -*cc1_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*cc1_absdata: - %{mabsdata} - -*asm_arch: - -mmcu=avr4 - -*asm_relax: - %{mrelax:--mlink-relax} - -*asm_rmw: - %{mrmw} - -*asm_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*link_pmem_wrap: - %{!mno-pmem-wrap-around: --pmem-wrap-around=8k} - -*link_relax: - %{mrelax:--relax} - -*link_arch: - %{mmcu=*:-m%*} - -*link_data_start: - - -*link_text_start: - - -*self_spec: - %{!mmcu=avr*: % -# #elif ... -# -# If no device macro is defined, AVR-LibC uses __AVR_DEV_LIB_NAME__ -# as fallback to determine the name of the device header as -# -# "avr/io" + __AVR_DEV_LIB_NAME__ + ".h" -# -# If you provide your own specs file for a device not yet known to -# AVR-LibC, you can now define the hook macro __AVR_DEV_LIB_NAME__ -# as needed so that -# -# #include -# -# will include the desired device header. For ATmega8A the supplement -# to *cpp would read -# -# -D__AVR_DEV_LIB_NAME__=m8a - - -*cpp: - -D__AVR_ATmega8515__ -D__AVR_DEVICE_NAME__=atmega8515 - -# End of file diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega8535 b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega8535 deleted file mode 100644 index 3e0af86..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega8535 +++ /dev/null @@ -1,99 +0,0 @@ -# -# Auto-generated specs for AVR device atmega8535 (core avr4, 16-bit SP) -# -# Generated by : ./gcc/config/avr/gen-avr-mmcu-specs.c -# Generated from : ./gcc/config/gcc.c -# ./gcc/config/avr/specs.h -# ./gcc/config/avr/avrlibc.h -# Used by : avr-gcc compiler driver -# Used for : building command options for sub-processes -# -# See -# for a documentation of spec files. - - -# If you intend to use an existing device specs file as a starting point -# for a new device spec file, make sure you are copying from a specs -# file for a device from the same core architecture and SP width. -# See for a description -# of how to use such own spec files. - -*avrlibc_startfile: - crtatmega8535.o%s - -*avrlibc_devicelib: - %{!nodevicelib:-latmega8535} - -*cc1_n_flash: - %{!mn-flash=*:-mn-flash=1} - -*cc1_rmw: - %{mrmw} - -*cc1_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*cc1_absdata: - %{mabsdata} - -*asm_arch: - -mmcu=avr4 - -*asm_relax: - %{mrelax:--mlink-relax} - -*asm_rmw: - %{mrmw} - -*asm_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*link_pmem_wrap: - %{!mno-pmem-wrap-around: --pmem-wrap-around=8k} - -*link_relax: - %{mrelax:--relax} - -*link_arch: - %{mmcu=*:-m%*} - -*link_data_start: - - -*link_text_start: - - -*self_spec: - %{!mmcu=avr*: % -# #elif ... -# -# If no device macro is defined, AVR-LibC uses __AVR_DEV_LIB_NAME__ -# as fallback to determine the name of the device header as -# -# "avr/io" + __AVR_DEV_LIB_NAME__ + ".h" -# -# If you provide your own specs file for a device not yet known to -# AVR-LibC, you can now define the hook macro __AVR_DEV_LIB_NAME__ -# as needed so that -# -# #include -# -# will include the desired device header. For ATmega8A the supplement -# to *cpp would read -# -# -D__AVR_DEV_LIB_NAME__=m8a - - -*cpp: - -D__AVR_ATmega8535__ -D__AVR_DEVICE_NAME__=atmega8535 - -# End of file diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega88 b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega88 deleted file mode 100644 index fde5094..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega88 +++ /dev/null @@ -1,99 +0,0 @@ -# -# Auto-generated specs for AVR device atmega88 (core avr4, 16-bit SP) -# -# Generated by : ./gcc/config/avr/gen-avr-mmcu-specs.c -# Generated from : ./gcc/config/gcc.c -# ./gcc/config/avr/specs.h -# ./gcc/config/avr/avrlibc.h -# Used by : avr-gcc compiler driver -# Used for : building command options for sub-processes -# -# See -# for a documentation of spec files. - - -# If you intend to use an existing device specs file as a starting point -# for a new device spec file, make sure you are copying from a specs -# file for a device from the same core architecture and SP width. -# See for a description -# of how to use such own spec files. - -*avrlibc_startfile: - crtatmega88.o%s - -*avrlibc_devicelib: - %{!nodevicelib:-latmega88} - -*cc1_n_flash: - %{!mn-flash=*:-mn-flash=1} - -*cc1_rmw: - %{mrmw} - -*cc1_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*cc1_absdata: - %{mabsdata} - -*asm_arch: - -mmcu=avr4 - -*asm_relax: - %{mrelax:--mlink-relax} - -*asm_rmw: - %{mrmw} - -*asm_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*link_pmem_wrap: - %{!mno-pmem-wrap-around: --pmem-wrap-around=8k} - -*link_relax: - %{mrelax:--relax} - -*link_arch: - %{mmcu=*:-m%*} - -*link_data_start: - -Tdata 0x800100 - -*link_text_start: - - -*self_spec: - %{!mmcu=avr*: % -# #elif ... -# -# If no device macro is defined, AVR-LibC uses __AVR_DEV_LIB_NAME__ -# as fallback to determine the name of the device header as -# -# "avr/io" + __AVR_DEV_LIB_NAME__ + ".h" -# -# If you provide your own specs file for a device not yet known to -# AVR-LibC, you can now define the hook macro __AVR_DEV_LIB_NAME__ -# as needed so that -# -# #include -# -# will include the desired device header. For ATmega8A the supplement -# to *cpp would read -# -# -D__AVR_DEV_LIB_NAME__=m8a - - -*cpp: - -D__AVR_ATmega88__ -D__AVR_DEVICE_NAME__=atmega88 - -# End of file diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega88a b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega88a deleted file mode 100644 index 0fadcb0..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega88a +++ /dev/null @@ -1,99 +0,0 @@ -# -# Auto-generated specs for AVR device atmega88a (core avr4, 16-bit SP) -# -# Generated by : ./gcc/config/avr/gen-avr-mmcu-specs.c -# Generated from : ./gcc/config/gcc.c -# ./gcc/config/avr/specs.h -# ./gcc/config/avr/avrlibc.h -# Used by : avr-gcc compiler driver -# Used for : building command options for sub-processes -# -# See -# for a documentation of spec files. - - -# If you intend to use an existing device specs file as a starting point -# for a new device spec file, make sure you are copying from a specs -# file for a device from the same core architecture and SP width. -# See for a description -# of how to use such own spec files. - -*avrlibc_startfile: - crtatmega88a.o%s - -*avrlibc_devicelib: - %{!nodevicelib:-latmega88a} - -*cc1_n_flash: - %{!mn-flash=*:-mn-flash=1} - -*cc1_rmw: - %{mrmw} - -*cc1_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*cc1_absdata: - %{mabsdata} - -*asm_arch: - -mmcu=avr4 - -*asm_relax: - %{mrelax:--mlink-relax} - -*asm_rmw: - %{mrmw} - -*asm_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*link_pmem_wrap: - %{!mno-pmem-wrap-around: --pmem-wrap-around=8k} - -*link_relax: - %{mrelax:--relax} - -*link_arch: - %{mmcu=*:-m%*} - -*link_data_start: - -Tdata 0x800100 - -*link_text_start: - - -*self_spec: - %{!mmcu=avr*: % -# #elif ... -# -# If no device macro is defined, AVR-LibC uses __AVR_DEV_LIB_NAME__ -# as fallback to determine the name of the device header as -# -# "avr/io" + __AVR_DEV_LIB_NAME__ + ".h" -# -# If you provide your own specs file for a device not yet known to -# AVR-LibC, you can now define the hook macro __AVR_DEV_LIB_NAME__ -# as needed so that -# -# #include -# -# will include the desired device header. For ATmega8A the supplement -# to *cpp would read -# -# -D__AVR_DEV_LIB_NAME__=m8a - - -*cpp: - -D__AVR_ATmega88A__ -D__AVR_DEVICE_NAME__=atmega88a - -# End of file diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega88p b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega88p deleted file mode 100644 index 435b8b9..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega88p +++ /dev/null @@ -1,99 +0,0 @@ -# -# Auto-generated specs for AVR device atmega88p (core avr4, 16-bit SP) -# -# Generated by : ./gcc/config/avr/gen-avr-mmcu-specs.c -# Generated from : ./gcc/config/gcc.c -# ./gcc/config/avr/specs.h -# ./gcc/config/avr/avrlibc.h -# Used by : avr-gcc compiler driver -# Used for : building command options for sub-processes -# -# See -# for a documentation of spec files. - - -# If you intend to use an existing device specs file as a starting point -# for a new device spec file, make sure you are copying from a specs -# file for a device from the same core architecture and SP width. -# See for a description -# of how to use such own spec files. - -*avrlibc_startfile: - crtatmega88p.o%s - -*avrlibc_devicelib: - %{!nodevicelib:-latmega88p} - -*cc1_n_flash: - %{!mn-flash=*:-mn-flash=1} - -*cc1_rmw: - %{mrmw} - -*cc1_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*cc1_absdata: - %{mabsdata} - -*asm_arch: - -mmcu=avr4 - -*asm_relax: - %{mrelax:--mlink-relax} - -*asm_rmw: - %{mrmw} - -*asm_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*link_pmem_wrap: - %{!mno-pmem-wrap-around: --pmem-wrap-around=8k} - -*link_relax: - %{mrelax:--relax} - -*link_arch: - %{mmcu=*:-m%*} - -*link_data_start: - -Tdata 0x800100 - -*link_text_start: - - -*self_spec: - %{!mmcu=avr*: % -# #elif ... -# -# If no device macro is defined, AVR-LibC uses __AVR_DEV_LIB_NAME__ -# as fallback to determine the name of the device header as -# -# "avr/io" + __AVR_DEV_LIB_NAME__ + ".h" -# -# If you provide your own specs file for a device not yet known to -# AVR-LibC, you can now define the hook macro __AVR_DEV_LIB_NAME__ -# as needed so that -# -# #include -# -# will include the desired device header. For ATmega8A the supplement -# to *cpp would read -# -# -D__AVR_DEV_LIB_NAME__=m8a - - -*cpp: - -D__AVR_ATmega88P__ -D__AVR_DEVICE_NAME__=atmega88p - -# End of file diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega88pa b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega88pa deleted file mode 100644 index 189b0cd..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega88pa +++ /dev/null @@ -1,99 +0,0 @@ -# -# Auto-generated specs for AVR device atmega88pa (core avr4, 16-bit SP) -# -# Generated by : ./gcc/config/avr/gen-avr-mmcu-specs.c -# Generated from : ./gcc/config/gcc.c -# ./gcc/config/avr/specs.h -# ./gcc/config/avr/avrlibc.h -# Used by : avr-gcc compiler driver -# Used for : building command options for sub-processes -# -# See -# for a documentation of spec files. - - -# If you intend to use an existing device specs file as a starting point -# for a new device spec file, make sure you are copying from a specs -# file for a device from the same core architecture and SP width. -# See for a description -# of how to use such own spec files. - -*avrlibc_startfile: - crtatmega88pa.o%s - -*avrlibc_devicelib: - %{!nodevicelib:-latmega88pa} - -*cc1_n_flash: - %{!mn-flash=*:-mn-flash=1} - -*cc1_rmw: - %{mrmw} - -*cc1_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*cc1_absdata: - %{mabsdata} - -*asm_arch: - -mmcu=avr4 - -*asm_relax: - %{mrelax:--mlink-relax} - -*asm_rmw: - %{mrmw} - -*asm_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*link_pmem_wrap: - %{!mno-pmem-wrap-around: --pmem-wrap-around=8k} - -*link_relax: - %{mrelax:--relax} - -*link_arch: - %{mmcu=*:-m%*} - -*link_data_start: - -Tdata 0x800100 - -*link_text_start: - - -*self_spec: - %{!mmcu=avr*: % -# #elif ... -# -# If no device macro is defined, AVR-LibC uses __AVR_DEV_LIB_NAME__ -# as fallback to determine the name of the device header as -# -# "avr/io" + __AVR_DEV_LIB_NAME__ + ".h" -# -# If you provide your own specs file for a device not yet known to -# AVR-LibC, you can now define the hook macro __AVR_DEV_LIB_NAME__ -# as needed so that -# -# #include -# -# will include the desired device header. For ATmega8A the supplement -# to *cpp would read -# -# -D__AVR_DEV_LIB_NAME__=m8a - - -*cpp: - -D__AVR_ATmega88PA__ -D__AVR_DEVICE_NAME__=atmega88pa - -# End of file diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega88pb b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega88pb deleted file mode 100644 index 82ec173..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega88pb +++ /dev/null @@ -1,99 +0,0 @@ -# -# Auto-generated specs for AVR device atmega88pb (core avr4, 16-bit SP) -# -# Generated by : ./gcc/config/avr/gen-avr-mmcu-specs.c -# Generated from : ./gcc/config/gcc.c -# ./gcc/config/avr/specs.h -# ./gcc/config/avr/avrlibc.h -# Used by : avr-gcc compiler driver -# Used for : building command options for sub-processes -# -# See -# for a documentation of spec files. - - -# If you intend to use an existing device specs file as a starting point -# for a new device spec file, make sure you are copying from a specs -# file for a device from the same core architecture and SP width. -# See for a description -# of how to use such own spec files. - -*avrlibc_startfile: - crtatmega88pb.o%s - -*avrlibc_devicelib: - %{!nodevicelib:-latmega88pb} - -*cc1_n_flash: - %{!mn-flash=*:-mn-flash=1} - -*cc1_rmw: - %{mrmw} - -*cc1_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*cc1_absdata: - %{mabsdata} - -*asm_arch: - -mmcu=avr4 - -*asm_relax: - %{mrelax:--mlink-relax} - -*asm_rmw: - %{mrmw} - -*asm_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*link_pmem_wrap: - %{!mno-pmem-wrap-around: --pmem-wrap-around=8k} - -*link_relax: - %{mrelax:--relax} - -*link_arch: - %{mmcu=*:-m%*} - -*link_data_start: - -Tdata 0x800100 - -*link_text_start: - - -*self_spec: - %{!mmcu=avr*: % -# #elif ... -# -# If no device macro is defined, AVR-LibC uses __AVR_DEV_LIB_NAME__ -# as fallback to determine the name of the device header as -# -# "avr/io" + __AVR_DEV_LIB_NAME__ + ".h" -# -# If you provide your own specs file for a device not yet known to -# AVR-LibC, you can now define the hook macro __AVR_DEV_LIB_NAME__ -# as needed so that -# -# #include -# -# will include the desired device header. For ATmega8A the supplement -# to *cpp would read -# -# -D__AVR_DEV_LIB_NAME__=m8a - - -*cpp: - -D__AVR_ATmega88PB__ -D__AVR_DEVICE_NAME__=atmega88pb - -# End of file diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega8a b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega8a deleted file mode 100644 index e5d1af1..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega8a +++ /dev/null @@ -1,99 +0,0 @@ -# -# Auto-generated specs for AVR device atmega8a (core avr4, 16-bit SP) -# -# Generated by : ./gcc/config/avr/gen-avr-mmcu-specs.c -# Generated from : ./gcc/config/gcc.c -# ./gcc/config/avr/specs.h -# ./gcc/config/avr/avrlibc.h -# Used by : avr-gcc compiler driver -# Used for : building command options for sub-processes -# -# See -# for a documentation of spec files. - - -# If you intend to use an existing device specs file as a starting point -# for a new device spec file, make sure you are copying from a specs -# file for a device from the same core architecture and SP width. -# See for a description -# of how to use such own spec files. - -*avrlibc_startfile: - crtatmega8a.o%s - -*avrlibc_devicelib: - %{!nodevicelib:-latmega8a} - -*cc1_n_flash: - %{!mn-flash=*:-mn-flash=1} - -*cc1_rmw: - %{mrmw} - -*cc1_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*cc1_absdata: - %{mabsdata} - -*asm_arch: - -mmcu=avr4 - -*asm_relax: - %{mrelax:--mlink-relax} - -*asm_rmw: - %{mrmw} - -*asm_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*link_pmem_wrap: - %{!mno-pmem-wrap-around: --pmem-wrap-around=8k} - -*link_relax: - %{mrelax:--relax} - -*link_arch: - %{mmcu=*:-m%*} - -*link_data_start: - - -*link_text_start: - - -*self_spec: - %{!mmcu=avr*: % -# #elif ... -# -# If no device macro is defined, AVR-LibC uses __AVR_DEV_LIB_NAME__ -# as fallback to determine the name of the device header as -# -# "avr/io" + __AVR_DEV_LIB_NAME__ + ".h" -# -# If you provide your own specs file for a device not yet known to -# AVR-LibC, you can now define the hook macro __AVR_DEV_LIB_NAME__ -# as needed so that -# -# #include -# -# will include the desired device header. For ATmega8A the supplement -# to *cpp would read -# -# -D__AVR_DEV_LIB_NAME__=m8a - - -*cpp: - -D__AVR_ATmega8A__ -D__AVR_DEVICE_NAME__=atmega8a - -# End of file diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega8hva b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega8hva deleted file mode 100644 index 4f9c3aa..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega8hva +++ /dev/null @@ -1,99 +0,0 @@ -# -# Auto-generated specs for AVR device atmega8hva (core avr4, 16-bit SP) -# -# Generated by : ./gcc/config/avr/gen-avr-mmcu-specs.c -# Generated from : ./gcc/config/gcc.c -# ./gcc/config/avr/specs.h -# ./gcc/config/avr/avrlibc.h -# Used by : avr-gcc compiler driver -# Used for : building command options for sub-processes -# -# See -# for a documentation of spec files. - - -# If you intend to use an existing device specs file as a starting point -# for a new device spec file, make sure you are copying from a specs -# file for a device from the same core architecture and SP width. -# See for a description -# of how to use such own spec files. - -*avrlibc_startfile: - crtatmega8hva.o%s - -*avrlibc_devicelib: - %{!nodevicelib:-latmega8hva} - -*cc1_n_flash: - %{!mn-flash=*:-mn-flash=1} - -*cc1_rmw: - %{mrmw} - -*cc1_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*cc1_absdata: - %{mabsdata} - -*asm_arch: - -mmcu=avr4 - -*asm_relax: - %{mrelax:--mlink-relax} - -*asm_rmw: - %{mrmw} - -*asm_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*link_pmem_wrap: - %{!mno-pmem-wrap-around: --pmem-wrap-around=8k} - -*link_relax: - %{mrelax:--relax} - -*link_arch: - %{mmcu=*:-m%*} - -*link_data_start: - -Tdata 0x800100 - -*link_text_start: - - -*self_spec: - %{!mmcu=avr*: % -# #elif ... -# -# If no device macro is defined, AVR-LibC uses __AVR_DEV_LIB_NAME__ -# as fallback to determine the name of the device header as -# -# "avr/io" + __AVR_DEV_LIB_NAME__ + ".h" -# -# If you provide your own specs file for a device not yet known to -# AVR-LibC, you can now define the hook macro __AVR_DEV_LIB_NAME__ -# as needed so that -# -# #include -# -# will include the desired device header. For ATmega8A the supplement -# to *cpp would read -# -# -D__AVR_DEV_LIB_NAME__=m8a - - -*cpp: - -D__AVR_ATmega8HVA__ -D__AVR_DEVICE_NAME__=atmega8hva - -# End of file diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega8u2 b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega8u2 deleted file mode 100644 index 4deb873..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atmega8u2 +++ /dev/null @@ -1,99 +0,0 @@ -# -# Auto-generated specs for AVR device atmega8u2 (core avr35, 16-bit SP) -# -# Generated by : ./gcc/config/avr/gen-avr-mmcu-specs.c -# Generated from : ./gcc/config/gcc.c -# ./gcc/config/avr/specs.h -# ./gcc/config/avr/avrlibc.h -# Used by : avr-gcc compiler driver -# Used for : building command options for sub-processes -# -# See -# for a documentation of spec files. - - -# If you intend to use an existing device specs file as a starting point -# for a new device spec file, make sure you are copying from a specs -# file for a device from the same core architecture and SP width. -# See for a description -# of how to use such own spec files. - -*avrlibc_startfile: - crtatmega8u2.o%s - -*avrlibc_devicelib: - %{!nodevicelib:-latmega8u2} - -*cc1_n_flash: - %{!mn-flash=*:-mn-flash=1} - -*cc1_rmw: - %{mrmw} - -*cc1_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*cc1_absdata: - %{mabsdata} - -*asm_arch: - -mmcu=avr35 - -*asm_relax: - %{mrelax:--mlink-relax} - -*asm_rmw: - %{mrmw} - -*asm_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*link_pmem_wrap: - %{!mno-pmem-wrap-around: --pmem-wrap-around=8k} - -*link_relax: - %{mrelax:--relax} - -*link_arch: - %{mmcu=*:-m%*} - -*link_data_start: - -Tdata 0x800100 - -*link_text_start: - - -*self_spec: - %{!mmcu=avr*: % -# #elif ... -# -# If no device macro is defined, AVR-LibC uses __AVR_DEV_LIB_NAME__ -# as fallback to determine the name of the device header as -# -# "avr/io" + __AVR_DEV_LIB_NAME__ + ".h" -# -# If you provide your own specs file for a device not yet known to -# AVR-LibC, you can now define the hook macro __AVR_DEV_LIB_NAME__ -# as needed so that -# -# #include -# -# will include the desired device header. For ATmega8A the supplement -# to *cpp would read -# -# -D__AVR_DEV_LIB_NAME__=m8a - - -*cpp: - -D__AVR_ATmega8U2__ -D__AVR_DEVICE_NAME__=atmega8u2 - -# End of file diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-attiny10 b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-attiny10 deleted file mode 100644 index 2eb34f5..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-attiny10 +++ /dev/null @@ -1,99 +0,0 @@ -# -# Auto-generated specs for AVR device attiny10 (core avrtiny, 16-bit SP) -# -# Generated by : ./gcc/config/avr/gen-avr-mmcu-specs.c -# Generated from : ./gcc/config/gcc.c -# ./gcc/config/avr/specs.h -# ./gcc/config/avr/avrlibc.h -# Used by : avr-gcc compiler driver -# Used for : building command options for sub-processes -# -# See -# for a documentation of spec files. - - -# If you intend to use an existing device specs file as a starting point -# for a new device spec file, make sure you are copying from a specs -# file for a device from the same core architecture and SP width. -# See for a description -# of how to use such own spec files. - -*avrlibc_startfile: - crtattiny10.o%s - -*avrlibc_devicelib: - %{!nodevicelib:-lattiny10} - -*cc1_n_flash: - %{!mn-flash=*:-mn-flash=1} - -*cc1_rmw: - %{mrmw} - -*cc1_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*cc1_absdata: - %{!mno-absdata: -mabsdata} - -*asm_arch: - -mmcu=avrtiny - -*asm_relax: - %{mrelax:--mlink-relax} - -*asm_rmw: - %{mrmw} - -*asm_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*link_pmem_wrap: - - -*link_relax: - %{mrelax:--relax} - -*link_arch: - %{mmcu=*:-m%*} - -*link_data_start: - - -*link_text_start: - - -*self_spec: - %{!mmcu=avr*: % -# #elif ... -# -# If no device macro is defined, AVR-LibC uses __AVR_DEV_LIB_NAME__ -# as fallback to determine the name of the device header as -# -# "avr/io" + __AVR_DEV_LIB_NAME__ + ".h" -# -# If you provide your own specs file for a device not yet known to -# AVR-LibC, you can now define the hook macro __AVR_DEV_LIB_NAME__ -# as needed so that -# -# #include -# -# will include the desired device header. For ATmega8A the supplement -# to *cpp would read -# -# -D__AVR_DEV_LIB_NAME__=m8a - - -*cpp: - -D__AVR_ATtiny10__ -D__AVR_DEVICE_NAME__=attiny10 - -# End of file diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-attiny11 b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-attiny11 deleted file mode 100644 index e83e5cf..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-attiny11 +++ /dev/null @@ -1,99 +0,0 @@ -# -# Auto-generated specs for AVR device attiny11 (core avr1, 16-bit SP) -# -# Generated by : ./gcc/config/avr/gen-avr-mmcu-specs.c -# Generated from : ./gcc/config/gcc.c -# ./gcc/config/avr/specs.h -# ./gcc/config/avr/avrlibc.h -# Used by : avr-gcc compiler driver -# Used for : building command options for sub-processes -# -# See -# for a documentation of spec files. - - -# If you intend to use an existing device specs file as a starting point -# for a new device spec file, make sure you are copying from a specs -# file for a device from the same core architecture and SP width. -# See for a description -# of how to use such own spec files. - -*avrlibc_startfile: - crtattiny11.o%s - -*avrlibc_devicelib: - %{!nodevicelib:-lattiny11} - -*cc1_n_flash: - %{!mn-flash=*:-mn-flash=1} - -*cc1_rmw: - %{mrmw} - -*cc1_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*cc1_absdata: - %{mabsdata} - -*asm_arch: - -mmcu=avr1 - -*asm_relax: - %{mrelax:--mlink-relax} - -*asm_rmw: - %{mrmw} - -*asm_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*link_pmem_wrap: - - -*link_relax: - %{mrelax:--relax} - -*link_arch: - %{mmcu=*:-m%*} - -*link_data_start: - - -*link_text_start: - - -*self_spec: - %{!mmcu=avr*: % -# #elif ... -# -# If no device macro is defined, AVR-LibC uses __AVR_DEV_LIB_NAME__ -# as fallback to determine the name of the device header as -# -# "avr/io" + __AVR_DEV_LIB_NAME__ + ".h" -# -# If you provide your own specs file for a device not yet known to -# AVR-LibC, you can now define the hook macro __AVR_DEV_LIB_NAME__ -# as needed so that -# -# #include -# -# will include the desired device header. For ATmega8A the supplement -# to *cpp would read -# -# -D__AVR_DEV_LIB_NAME__=m8a - - -*cpp: - -D__AVR_ATtiny11__ -D__AVR_DEVICE_NAME__=attiny11 - -# End of file diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-attiny12 b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-attiny12 deleted file mode 100644 index 0e7266b..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-attiny12 +++ /dev/null @@ -1,99 +0,0 @@ -# -# Auto-generated specs for AVR device attiny12 (core avr1, 16-bit SP) -# -# Generated by : ./gcc/config/avr/gen-avr-mmcu-specs.c -# Generated from : ./gcc/config/gcc.c -# ./gcc/config/avr/specs.h -# ./gcc/config/avr/avrlibc.h -# Used by : avr-gcc compiler driver -# Used for : building command options for sub-processes -# -# See -# for a documentation of spec files. - - -# If you intend to use an existing device specs file as a starting point -# for a new device spec file, make sure you are copying from a specs -# file for a device from the same core architecture and SP width. -# See for a description -# of how to use such own spec files. - -*avrlibc_startfile: - crtattiny12.o%s - -*avrlibc_devicelib: - %{!nodevicelib:-lattiny12} - -*cc1_n_flash: - %{!mn-flash=*:-mn-flash=1} - -*cc1_rmw: - %{mrmw} - -*cc1_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*cc1_absdata: - %{mabsdata} - -*asm_arch: - -mmcu=avr1 - -*asm_relax: - %{mrelax:--mlink-relax} - -*asm_rmw: - %{mrmw} - -*asm_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*link_pmem_wrap: - - -*link_relax: - %{mrelax:--relax} - -*link_arch: - %{mmcu=*:-m%*} - -*link_data_start: - - -*link_text_start: - - -*self_spec: - %{!mmcu=avr*: % -# #elif ... -# -# If no device macro is defined, AVR-LibC uses __AVR_DEV_LIB_NAME__ -# as fallback to determine the name of the device header as -# -# "avr/io" + __AVR_DEV_LIB_NAME__ + ".h" -# -# If you provide your own specs file for a device not yet known to -# AVR-LibC, you can now define the hook macro __AVR_DEV_LIB_NAME__ -# as needed so that -# -# #include -# -# will include the desired device header. For ATmega8A the supplement -# to *cpp would read -# -# -D__AVR_DEV_LIB_NAME__=m8a - - -*cpp: - -D__AVR_ATtiny12__ -D__AVR_DEVICE_NAME__=attiny12 - -# End of file diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-attiny13 b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-attiny13 deleted file mode 100644 index 9092867..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-attiny13 +++ /dev/null @@ -1,99 +0,0 @@ -# -# Auto-generated specs for AVR device attiny13 (core avr25, 8-bit SP) -# -# Generated by : ./gcc/config/avr/gen-avr-mmcu-specs.c -# Generated from : ./gcc/config/gcc.c -# ./gcc/config/avr/specs.h -# ./gcc/config/avr/avrlibc.h -# Used by : avr-gcc compiler driver -# Used for : building command options for sub-processes -# -# See -# for a documentation of spec files. - - -# If you intend to use an existing device specs file as a starting point -# for a new device spec file, make sure you are copying from a specs -# file for a device from the same core architecture and SP width. -# See for a description -# of how to use such own spec files. - -*avrlibc_startfile: - crtattiny13.o%s - -*avrlibc_devicelib: - %{!nodevicelib:-lattiny13} - -*cc1_n_flash: - %{!mn-flash=*:-mn-flash=1} - -*cc1_rmw: - %{mrmw} - -*cc1_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*cc1_absdata: - %{mabsdata} - -*asm_arch: - -mmcu=avr25 - -*asm_relax: - %{mrelax:--mlink-relax} - -*asm_rmw: - %{mrmw} - -*asm_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*link_pmem_wrap: - - -*link_relax: - %{mrelax:--relax} - -*link_arch: - %{mmcu=*:-m%*} - -*link_data_start: - - -*link_text_start: - - -*self_spec: - %{!mmcu=avr*: % -# #elif ... -# -# If no device macro is defined, AVR-LibC uses __AVR_DEV_LIB_NAME__ -# as fallback to determine the name of the device header as -# -# "avr/io" + __AVR_DEV_LIB_NAME__ + ".h" -# -# If you provide your own specs file for a device not yet known to -# AVR-LibC, you can now define the hook macro __AVR_DEV_LIB_NAME__ -# as needed so that -# -# #include -# -# will include the desired device header. For ATmega8A the supplement -# to *cpp would read -# -# -D__AVR_DEV_LIB_NAME__=m8a - - -*cpp: - -D__AVR_ATtiny13__ -D__AVR_DEVICE_NAME__=attiny13 - -# End of file diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-attiny13a b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-attiny13a deleted file mode 100644 index e775fb9..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-attiny13a +++ /dev/null @@ -1,99 +0,0 @@ -# -# Auto-generated specs for AVR device attiny13a (core avr25, 8-bit SP) -# -# Generated by : ./gcc/config/avr/gen-avr-mmcu-specs.c -# Generated from : ./gcc/config/gcc.c -# ./gcc/config/avr/specs.h -# ./gcc/config/avr/avrlibc.h -# Used by : avr-gcc compiler driver -# Used for : building command options for sub-processes -# -# See -# for a documentation of spec files. - - -# If you intend to use an existing device specs file as a starting point -# for a new device spec file, make sure you are copying from a specs -# file for a device from the same core architecture and SP width. -# See for a description -# of how to use such own spec files. - -*avrlibc_startfile: - crtattiny13a.o%s - -*avrlibc_devicelib: - %{!nodevicelib:-lattiny13a} - -*cc1_n_flash: - %{!mn-flash=*:-mn-flash=1} - -*cc1_rmw: - %{mrmw} - -*cc1_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*cc1_absdata: - %{mabsdata} - -*asm_arch: - -mmcu=avr25 - -*asm_relax: - %{mrelax:--mlink-relax} - -*asm_rmw: - %{mrmw} - -*asm_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*link_pmem_wrap: - - -*link_relax: - %{mrelax:--relax} - -*link_arch: - %{mmcu=*:-m%*} - -*link_data_start: - - -*link_text_start: - - -*self_spec: - %{!mmcu=avr*: % -# #elif ... -# -# If no device macro is defined, AVR-LibC uses __AVR_DEV_LIB_NAME__ -# as fallback to determine the name of the device header as -# -# "avr/io" + __AVR_DEV_LIB_NAME__ + ".h" -# -# If you provide your own specs file for a device not yet known to -# AVR-LibC, you can now define the hook macro __AVR_DEV_LIB_NAME__ -# as needed so that -# -# #include -# -# will include the desired device header. For ATmega8A the supplement -# to *cpp would read -# -# -D__AVR_DEV_LIB_NAME__=m8a - - -*cpp: - -D__AVR_ATtiny13A__ -D__AVR_DEVICE_NAME__=attiny13a - -# End of file diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-attiny15 b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-attiny15 deleted file mode 100644 index 661fbcd..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-attiny15 +++ /dev/null @@ -1,99 +0,0 @@ -# -# Auto-generated specs for AVR device attiny15 (core avr1, 16-bit SP) -# -# Generated by : ./gcc/config/avr/gen-avr-mmcu-specs.c -# Generated from : ./gcc/config/gcc.c -# ./gcc/config/avr/specs.h -# ./gcc/config/avr/avrlibc.h -# Used by : avr-gcc compiler driver -# Used for : building command options for sub-processes -# -# See -# for a documentation of spec files. - - -# If you intend to use an existing device specs file as a starting point -# for a new device spec file, make sure you are copying from a specs -# file for a device from the same core architecture and SP width. -# See for a description -# of how to use such own spec files. - -*avrlibc_startfile: - crtattiny15.o%s - -*avrlibc_devicelib: - %{!nodevicelib:-lattiny15} - -*cc1_n_flash: - %{!mn-flash=*:-mn-flash=1} - -*cc1_rmw: - %{mrmw} - -*cc1_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*cc1_absdata: - %{mabsdata} - -*asm_arch: - -mmcu=avr1 - -*asm_relax: - %{mrelax:--mlink-relax} - -*asm_rmw: - %{mrmw} - -*asm_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*link_pmem_wrap: - - -*link_relax: - %{mrelax:--relax} - -*link_arch: - %{mmcu=*:-m%*} - -*link_data_start: - - -*link_text_start: - - -*self_spec: - %{!mmcu=avr*: % -# #elif ... -# -# If no device macro is defined, AVR-LibC uses __AVR_DEV_LIB_NAME__ -# as fallback to determine the name of the device header as -# -# "avr/io" + __AVR_DEV_LIB_NAME__ + ".h" -# -# If you provide your own specs file for a device not yet known to -# AVR-LibC, you can now define the hook macro __AVR_DEV_LIB_NAME__ -# as needed so that -# -# #include -# -# will include the desired device header. For ATmega8A the supplement -# to *cpp would read -# -# -D__AVR_DEV_LIB_NAME__=m8a - - -*cpp: - -D__AVR_ATtiny15__ -D__AVR_DEVICE_NAME__=attiny15 - -# End of file diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-attiny1614 b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-attiny1614 deleted file mode 100644 index b30a3d0..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-attiny1614 +++ /dev/null @@ -1,99 +0,0 @@ -# -# Auto-generated specs for AVR device attiny1614 (core avrxmega3, 16-bit SP) -# -# Generated by : ./gcc/config/avr/gen-avr-mmcu-specs.c -# Generated from : ./gcc/config/gcc.c -# ./gcc/config/avr/specs.h -# ./gcc/config/avr/avrlibc.h -# Used by : avr-gcc compiler driver -# Used for : building command options for sub-processes -# -# See -# for a documentation of spec files. - - -# If you intend to use an existing device specs file as a starting point -# for a new device spec file, make sure you are copying from a specs -# file for a device from the same core architecture and SP width. -# See for a description -# of how to use such own spec files. - -*avrlibc_startfile: - crtattiny1614.o%s - -*avrlibc_devicelib: - %{!nodevicelib:-lattiny1614} - -*cc1_n_flash: - %{!mn-flash=*:-mn-flash=1} - -*cc1_rmw: - %{mrmw} - -*cc1_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*cc1_absdata: - %{mabsdata} - -*asm_arch: - -mmcu=avrxmega3 - -*asm_relax: - %{mrelax:--mlink-relax} - -*asm_rmw: - %{mrmw} - -*asm_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*link_pmem_wrap: - %{mpmem-wrap-around: --pmem-wrap-around=16k} - -*link_relax: - %{mrelax:--relax} - -*link_arch: - %{mmcu=*:-m%*} - -*link_data_start: - -Tdata 0x803800 - -*link_text_start: - - -*self_spec: - %{!mmcu=avr*: % -# #elif ... -# -# If no device macro is defined, AVR-LibC uses __AVR_DEV_LIB_NAME__ -# as fallback to determine the name of the device header as -# -# "avr/io" + __AVR_DEV_LIB_NAME__ + ".h" -# -# If you provide your own specs file for a device not yet known to -# AVR-LibC, you can now define the hook macro __AVR_DEV_LIB_NAME__ -# as needed so that -# -# #include -# -# will include the desired device header. For ATmega8A the supplement -# to *cpp would read -# -# -D__AVR_DEV_LIB_NAME__=m8a - - -*cpp: - -D__AVR_ATtiny1614__ -D__AVR_DEVICE_NAME__=attiny1614 - -# End of file diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-attiny1616 b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-attiny1616 deleted file mode 100644 index 0f54541..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-attiny1616 +++ /dev/null @@ -1,99 +0,0 @@ -# -# Auto-generated specs for AVR device attiny1616 (core avrxmega3, 16-bit SP) -# -# Generated by : ./gcc/config/avr/gen-avr-mmcu-specs.c -# Generated from : ./gcc/config/gcc.c -# ./gcc/config/avr/specs.h -# ./gcc/config/avr/avrlibc.h -# Used by : avr-gcc compiler driver -# Used for : building command options for sub-processes -# -# See -# for a documentation of spec files. - - -# If you intend to use an existing device specs file as a starting point -# for a new device spec file, make sure you are copying from a specs -# file for a device from the same core architecture and SP width. -# See for a description -# of how to use such own spec files. - -*avrlibc_startfile: - crtattiny1616.o%s - -*avrlibc_devicelib: - %{!nodevicelib:-lattiny1616} - -*cc1_n_flash: - %{!mn-flash=*:-mn-flash=1} - -*cc1_rmw: - %{mrmw} - -*cc1_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*cc1_absdata: - %{mabsdata} - -*asm_arch: - -mmcu=avrxmega3 - -*asm_relax: - %{mrelax:--mlink-relax} - -*asm_rmw: - %{mrmw} - -*asm_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*link_pmem_wrap: - %{mpmem-wrap-around: --pmem-wrap-around=16k} - -*link_relax: - %{mrelax:--relax} - -*link_arch: - %{mmcu=*:-m%*} - -*link_data_start: - -Tdata 0x803800 - -*link_text_start: - - -*self_spec: - %{!mmcu=avr*: % -# #elif ... -# -# If no device macro is defined, AVR-LibC uses __AVR_DEV_LIB_NAME__ -# as fallback to determine the name of the device header as -# -# "avr/io" + __AVR_DEV_LIB_NAME__ + ".h" -# -# If you provide your own specs file for a device not yet known to -# AVR-LibC, you can now define the hook macro __AVR_DEV_LIB_NAME__ -# as needed so that -# -# #include -# -# will include the desired device header. For ATmega8A the supplement -# to *cpp would read -# -# -D__AVR_DEV_LIB_NAME__=m8a - - -*cpp: - -D__AVR_ATtiny1616__ -D__AVR_DEVICE_NAME__=attiny1616 - -# End of file diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-attiny1617 b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-attiny1617 deleted file mode 100644 index 6328239..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-attiny1617 +++ /dev/null @@ -1,99 +0,0 @@ -# -# Auto-generated specs for AVR device attiny1617 (core avrxmega3, 16-bit SP) -# -# Generated by : ./gcc/config/avr/gen-avr-mmcu-specs.c -# Generated from : ./gcc/config/gcc.c -# ./gcc/config/avr/specs.h -# ./gcc/config/avr/avrlibc.h -# Used by : avr-gcc compiler driver -# Used for : building command options for sub-processes -# -# See -# for a documentation of spec files. - - -# If you intend to use an existing device specs file as a starting point -# for a new device spec file, make sure you are copying from a specs -# file for a device from the same core architecture and SP width. -# See for a description -# of how to use such own spec files. - -*avrlibc_startfile: - crtattiny1617.o%s - -*avrlibc_devicelib: - %{!nodevicelib:-lattiny1617} - -*cc1_n_flash: - %{!mn-flash=*:-mn-flash=1} - -*cc1_rmw: - %{mrmw} - -*cc1_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*cc1_absdata: - %{mabsdata} - -*asm_arch: - -mmcu=avrxmega3 - -*asm_relax: - %{mrelax:--mlink-relax} - -*asm_rmw: - %{mrmw} - -*asm_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*link_pmem_wrap: - %{mpmem-wrap-around: --pmem-wrap-around=16k} - -*link_relax: - %{mrelax:--relax} - -*link_arch: - %{mmcu=*:-m%*} - -*link_data_start: - -Tdata 0x803800 - -*link_text_start: - - -*self_spec: - %{!mmcu=avr*: % -# #elif ... -# -# If no device macro is defined, AVR-LibC uses __AVR_DEV_LIB_NAME__ -# as fallback to determine the name of the device header as -# -# "avr/io" + __AVR_DEV_LIB_NAME__ + ".h" -# -# If you provide your own specs file for a device not yet known to -# AVR-LibC, you can now define the hook macro __AVR_DEV_LIB_NAME__ -# as needed so that -# -# #include -# -# will include the desired device header. For ATmega8A the supplement -# to *cpp would read -# -# -D__AVR_DEV_LIB_NAME__=m8a - - -*cpp: - -D__AVR_ATtiny1617__ -D__AVR_DEVICE_NAME__=attiny1617 - -# End of file diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-attiny1634 b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-attiny1634 deleted file mode 100644 index f71d30c..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-attiny1634 +++ /dev/null @@ -1,99 +0,0 @@ -# -# Auto-generated specs for AVR device attiny1634 (core avr35, 16-bit SP) -# -# Generated by : ./gcc/config/avr/gen-avr-mmcu-specs.c -# Generated from : ./gcc/config/gcc.c -# ./gcc/config/avr/specs.h -# ./gcc/config/avr/avrlibc.h -# Used by : avr-gcc compiler driver -# Used for : building command options for sub-processes -# -# See -# for a documentation of spec files. - - -# If you intend to use an existing device specs file as a starting point -# for a new device spec file, make sure you are copying from a specs -# file for a device from the same core architecture and SP width. -# See for a description -# of how to use such own spec files. - -*avrlibc_startfile: - crtattiny1634.o%s - -*avrlibc_devicelib: - %{!nodevicelib:-lattiny1634} - -*cc1_n_flash: - %{!mn-flash=*:-mn-flash=1} - -*cc1_rmw: - %{mrmw} - -*cc1_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*cc1_absdata: - %{mabsdata} - -*asm_arch: - -mmcu=avr35 - -*asm_relax: - %{mrelax:--mlink-relax} - -*asm_rmw: - %{mrmw} - -*asm_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*link_pmem_wrap: - %{mpmem-wrap-around: --pmem-wrap-around=16k} - -*link_relax: - %{mrelax:--relax} - -*link_arch: - %{mmcu=*:-m%*} - -*link_data_start: - -Tdata 0x800100 - -*link_text_start: - - -*self_spec: - %{!mmcu=avr*: % -# #elif ... -# -# If no device macro is defined, AVR-LibC uses __AVR_DEV_LIB_NAME__ -# as fallback to determine the name of the device header as -# -# "avr/io" + __AVR_DEV_LIB_NAME__ + ".h" -# -# If you provide your own specs file for a device not yet known to -# AVR-LibC, you can now define the hook macro __AVR_DEV_LIB_NAME__ -# as needed so that -# -# #include -# -# will include the desired device header. For ATmega8A the supplement -# to *cpp would read -# -# -D__AVR_DEV_LIB_NAME__=m8a - - -*cpp: - -D__AVR_ATtiny1634__ -D__AVR_DEVICE_NAME__=attiny1634 - -# End of file diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-attiny167 b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-attiny167 deleted file mode 100644 index b497f77..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-attiny167 +++ /dev/null @@ -1,99 +0,0 @@ -# -# Auto-generated specs for AVR device attiny167 (core avr35, 16-bit SP) -# -# Generated by : ./gcc/config/avr/gen-avr-mmcu-specs.c -# Generated from : ./gcc/config/gcc.c -# ./gcc/config/avr/specs.h -# ./gcc/config/avr/avrlibc.h -# Used by : avr-gcc compiler driver -# Used for : building command options for sub-processes -# -# See -# for a documentation of spec files. - - -# If you intend to use an existing device specs file as a starting point -# for a new device spec file, make sure you are copying from a specs -# file for a device from the same core architecture and SP width. -# See for a description -# of how to use such own spec files. - -*avrlibc_startfile: - crtattiny167.o%s - -*avrlibc_devicelib: - %{!nodevicelib:-lattiny167} - -*cc1_n_flash: - %{!mn-flash=*:-mn-flash=1} - -*cc1_rmw: - %{mrmw} - -*cc1_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*cc1_absdata: - %{mabsdata} - -*asm_arch: - -mmcu=avr35 - -*asm_relax: - %{mrelax:--mlink-relax} - -*asm_rmw: - %{mrmw} - -*asm_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*link_pmem_wrap: - %{mpmem-wrap-around: --pmem-wrap-around=16k} - -*link_relax: - %{mrelax:--relax} - -*link_arch: - %{mmcu=*:-m%*} - -*link_data_start: - -Tdata 0x800100 - -*link_text_start: - - -*self_spec: - %{!mmcu=avr*: % -# #elif ... -# -# If no device macro is defined, AVR-LibC uses __AVR_DEV_LIB_NAME__ -# as fallback to determine the name of the device header as -# -# "avr/io" + __AVR_DEV_LIB_NAME__ + ".h" -# -# If you provide your own specs file for a device not yet known to -# AVR-LibC, you can now define the hook macro __AVR_DEV_LIB_NAME__ -# as needed so that -# -# #include -# -# will include the desired device header. For ATmega8A the supplement -# to *cpp would read -# -# -D__AVR_DEV_LIB_NAME__=m8a - - -*cpp: - -D__AVR_ATtiny167__ -D__AVR_DEVICE_NAME__=attiny167 - -# End of file diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-attiny20 b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-attiny20 deleted file mode 100644 index 0f8b556..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-attiny20 +++ /dev/null @@ -1,99 +0,0 @@ -# -# Auto-generated specs for AVR device attiny20 (core avrtiny, 16-bit SP) -# -# Generated by : ./gcc/config/avr/gen-avr-mmcu-specs.c -# Generated from : ./gcc/config/gcc.c -# ./gcc/config/avr/specs.h -# ./gcc/config/avr/avrlibc.h -# Used by : avr-gcc compiler driver -# Used for : building command options for sub-processes -# -# See -# for a documentation of spec files. - - -# If you intend to use an existing device specs file as a starting point -# for a new device spec file, make sure you are copying from a specs -# file for a device from the same core architecture and SP width. -# See for a description -# of how to use such own spec files. - -*avrlibc_startfile: - crtattiny20.o%s - -*avrlibc_devicelib: - %{!nodevicelib:-lattiny20} - -*cc1_n_flash: - %{!mn-flash=*:-mn-flash=1} - -*cc1_rmw: - %{mrmw} - -*cc1_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*cc1_absdata: - %{!mno-absdata: -mabsdata} - -*asm_arch: - -mmcu=avrtiny - -*asm_relax: - %{mrelax:--mlink-relax} - -*asm_rmw: - %{mrmw} - -*asm_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*link_pmem_wrap: - - -*link_relax: - %{mrelax:--relax} - -*link_arch: - %{mmcu=*:-m%*} - -*link_data_start: - - -*link_text_start: - - -*self_spec: - %{!mmcu=avr*: % -# #elif ... -# -# If no device macro is defined, AVR-LibC uses __AVR_DEV_LIB_NAME__ -# as fallback to determine the name of the device header as -# -# "avr/io" + __AVR_DEV_LIB_NAME__ + ".h" -# -# If you provide your own specs file for a device not yet known to -# AVR-LibC, you can now define the hook macro __AVR_DEV_LIB_NAME__ -# as needed so that -# -# #include -# -# will include the desired device header. For ATmega8A the supplement -# to *cpp would read -# -# -D__AVR_DEV_LIB_NAME__=m8a - - -*cpp: - -D__AVR_ATtiny20__ -D__AVR_DEVICE_NAME__=attiny20 - -# End of file diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-attiny212 b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-attiny212 deleted file mode 100644 index 765d954..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-attiny212 +++ /dev/null @@ -1,99 +0,0 @@ -# -# Auto-generated specs for AVR device attiny212 (core avrxmega3, 16-bit SP, short-calls) -# -# Generated by : ./gcc/config/avr/gen-avr-mmcu-specs.c -# Generated from : ./gcc/config/gcc.c -# ./gcc/config/avr/specs.h -# ./gcc/config/avr/avrlibc.h -# Used by : avr-gcc compiler driver -# Used for : building command options for sub-processes -# -# See -# for a documentation of spec files. - - -# If you intend to use an existing device specs file as a starting point -# for a new device spec file, make sure you are copying from a specs -# file for a device from the same core architecture and SP width. -# See for a description -# of how to use such own spec files. - -*avrlibc_startfile: - crtattiny212.o%s - -*avrlibc_devicelib: - %{!nodevicelib:-lattiny212} - -*cc1_n_flash: - %{!mn-flash=*:-mn-flash=1} - -*cc1_rmw: - %{mrmw} - -*cc1_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*cc1_absdata: - %{mabsdata} - -*asm_arch: - -mmcu=avrxmega3 - -*asm_relax: - %{mrelax:--mlink-relax} - -*asm_rmw: - %{mrmw} - -*asm_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*link_pmem_wrap: - - -*link_relax: - %{mrelax:--relax} - -*link_arch: - %{mmcu=*:-m%*} - -*link_data_start: - -Tdata 0x803F80 - -*link_text_start: - - -*self_spec: - %{!mmcu=avr*: % -# #elif ... -# -# If no device macro is defined, AVR-LibC uses __AVR_DEV_LIB_NAME__ -# as fallback to determine the name of the device header as -# -# "avr/io" + __AVR_DEV_LIB_NAME__ + ".h" -# -# If you provide your own specs file for a device not yet known to -# AVR-LibC, you can now define the hook macro __AVR_DEV_LIB_NAME__ -# as needed so that -# -# #include -# -# will include the desired device header. For ATmega8A the supplement -# to *cpp would read -# -# -D__AVR_DEV_LIB_NAME__=m8a - - -*cpp: - -D__AVR_ATtiny212__ -D__AVR_DEVICE_NAME__=attiny212 - -# End of file diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-attiny214 b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-attiny214 deleted file mode 100644 index ab851ca..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-attiny214 +++ /dev/null @@ -1,99 +0,0 @@ -# -# Auto-generated specs for AVR device attiny214 (core avrxmega3, 16-bit SP, short-calls) -# -# Generated by : ./gcc/config/avr/gen-avr-mmcu-specs.c -# Generated from : ./gcc/config/gcc.c -# ./gcc/config/avr/specs.h -# ./gcc/config/avr/avrlibc.h -# Used by : avr-gcc compiler driver -# Used for : building command options for sub-processes -# -# See -# for a documentation of spec files. - - -# If you intend to use an existing device specs file as a starting point -# for a new device spec file, make sure you are copying from a specs -# file for a device from the same core architecture and SP width. -# See for a description -# of how to use such own spec files. - -*avrlibc_startfile: - crtattiny214.o%s - -*avrlibc_devicelib: - %{!nodevicelib:-lattiny214} - -*cc1_n_flash: - %{!mn-flash=*:-mn-flash=1} - -*cc1_rmw: - %{mrmw} - -*cc1_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*cc1_absdata: - %{mabsdata} - -*asm_arch: - -mmcu=avrxmega3 - -*asm_relax: - %{mrelax:--mlink-relax} - -*asm_rmw: - %{mrmw} - -*asm_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*link_pmem_wrap: - - -*link_relax: - %{mrelax:--relax} - -*link_arch: - %{mmcu=*:-m%*} - -*link_data_start: - -Tdata 0x803F80 - -*link_text_start: - - -*self_spec: - %{!mmcu=avr*: % -# #elif ... -# -# If no device macro is defined, AVR-LibC uses __AVR_DEV_LIB_NAME__ -# as fallback to determine the name of the device header as -# -# "avr/io" + __AVR_DEV_LIB_NAME__ + ".h" -# -# If you provide your own specs file for a device not yet known to -# AVR-LibC, you can now define the hook macro __AVR_DEV_LIB_NAME__ -# as needed so that -# -# #include -# -# will include the desired device header. For ATmega8A the supplement -# to *cpp would read -# -# -D__AVR_DEV_LIB_NAME__=m8a - - -*cpp: - -D__AVR_ATtiny214__ -D__AVR_DEVICE_NAME__=attiny214 - -# End of file diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-attiny22 b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-attiny22 deleted file mode 100644 index f5d8bc3..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-attiny22 +++ /dev/null @@ -1,99 +0,0 @@ -# -# Auto-generated specs for AVR device attiny22 (core avr2, 8-bit SP) -# -# Generated by : ./gcc/config/avr/gen-avr-mmcu-specs.c -# Generated from : ./gcc/config/gcc.c -# ./gcc/config/avr/specs.h -# ./gcc/config/avr/avrlibc.h -# Used by : avr-gcc compiler driver -# Used for : building command options for sub-processes -# -# See -# for a documentation of spec files. - - -# If you intend to use an existing device specs file as a starting point -# for a new device spec file, make sure you are copying from a specs -# file for a device from the same core architecture and SP width. -# See for a description -# of how to use such own spec files. - -*avrlibc_startfile: - crtattiny22.o%s - -*avrlibc_devicelib: - %{!nodevicelib:-lattiny22} - -*cc1_n_flash: - %{!mn-flash=*:-mn-flash=1} - -*cc1_rmw: - %{mrmw} - -*cc1_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*cc1_absdata: - %{mabsdata} - -*asm_arch: - -mmcu=avr2 - -*asm_relax: - %{mrelax:--mlink-relax} - -*asm_rmw: - %{mrmw} - -*asm_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*link_pmem_wrap: - - -*link_relax: - %{mrelax:--relax} - -*link_arch: - %{mmcu=*:-m%*} - -*link_data_start: - - -*link_text_start: - - -*self_spec: - %{!mmcu=avr*: % -# #elif ... -# -# If no device macro is defined, AVR-LibC uses __AVR_DEV_LIB_NAME__ -# as fallback to determine the name of the device header as -# -# "avr/io" + __AVR_DEV_LIB_NAME__ + ".h" -# -# If you provide your own specs file for a device not yet known to -# AVR-LibC, you can now define the hook macro __AVR_DEV_LIB_NAME__ -# as needed so that -# -# #include -# -# will include the desired device header. For ATmega8A the supplement -# to *cpp would read -# -# -D__AVR_DEV_LIB_NAME__=m8a - - -*cpp: - -D__AVR_ATtiny22__ -D__AVR_DEVICE_NAME__=attiny22 - -# End of file diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-attiny2313 b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-attiny2313 deleted file mode 100644 index d4c2421..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-attiny2313 +++ /dev/null @@ -1,99 +0,0 @@ -# -# Auto-generated specs for AVR device attiny2313 (core avr25, 8-bit SP) -# -# Generated by : ./gcc/config/avr/gen-avr-mmcu-specs.c -# Generated from : ./gcc/config/gcc.c -# ./gcc/config/avr/specs.h -# ./gcc/config/avr/avrlibc.h -# Used by : avr-gcc compiler driver -# Used for : building command options for sub-processes -# -# See -# for a documentation of spec files. - - -# If you intend to use an existing device specs file as a starting point -# for a new device spec file, make sure you are copying from a specs -# file for a device from the same core architecture and SP width. -# See for a description -# of how to use such own spec files. - -*avrlibc_startfile: - crtattiny2313.o%s - -*avrlibc_devicelib: - %{!nodevicelib:-lattiny2313} - -*cc1_n_flash: - %{!mn-flash=*:-mn-flash=1} - -*cc1_rmw: - %{mrmw} - -*cc1_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*cc1_absdata: - %{mabsdata} - -*asm_arch: - -mmcu=avr25 - -*asm_relax: - %{mrelax:--mlink-relax} - -*asm_rmw: - %{mrmw} - -*asm_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*link_pmem_wrap: - - -*link_relax: - %{mrelax:--relax} - -*link_arch: - %{mmcu=*:-m%*} - -*link_data_start: - - -*link_text_start: - - -*self_spec: - %{!mmcu=avr*: % -# #elif ... -# -# If no device macro is defined, AVR-LibC uses __AVR_DEV_LIB_NAME__ -# as fallback to determine the name of the device header as -# -# "avr/io" + __AVR_DEV_LIB_NAME__ + ".h" -# -# If you provide your own specs file for a device not yet known to -# AVR-LibC, you can now define the hook macro __AVR_DEV_LIB_NAME__ -# as needed so that -# -# #include -# -# will include the desired device header. For ATmega8A the supplement -# to *cpp would read -# -# -D__AVR_DEV_LIB_NAME__=m8a - - -*cpp: - -D__AVR_ATtiny2313__ -D__AVR_DEVICE_NAME__=attiny2313 - -# End of file diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-attiny2313a b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-attiny2313a deleted file mode 100644 index c09cb27..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-attiny2313a +++ /dev/null @@ -1,99 +0,0 @@ -# -# Auto-generated specs for AVR device attiny2313a (core avr25, 8-bit SP) -# -# Generated by : ./gcc/config/avr/gen-avr-mmcu-specs.c -# Generated from : ./gcc/config/gcc.c -# ./gcc/config/avr/specs.h -# ./gcc/config/avr/avrlibc.h -# Used by : avr-gcc compiler driver -# Used for : building command options for sub-processes -# -# See -# for a documentation of spec files. - - -# If you intend to use an existing device specs file as a starting point -# for a new device spec file, make sure you are copying from a specs -# file for a device from the same core architecture and SP width. -# See for a description -# of how to use such own spec files. - -*avrlibc_startfile: - crtattiny2313a.o%s - -*avrlibc_devicelib: - %{!nodevicelib:-lattiny2313a} - -*cc1_n_flash: - %{!mn-flash=*:-mn-flash=1} - -*cc1_rmw: - %{mrmw} - -*cc1_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*cc1_absdata: - %{mabsdata} - -*asm_arch: - -mmcu=avr25 - -*asm_relax: - %{mrelax:--mlink-relax} - -*asm_rmw: - %{mrmw} - -*asm_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*link_pmem_wrap: - - -*link_relax: - %{mrelax:--relax} - -*link_arch: - %{mmcu=*:-m%*} - -*link_data_start: - - -*link_text_start: - - -*self_spec: - %{!mmcu=avr*: % -# #elif ... -# -# If no device macro is defined, AVR-LibC uses __AVR_DEV_LIB_NAME__ -# as fallback to determine the name of the device header as -# -# "avr/io" + __AVR_DEV_LIB_NAME__ + ".h" -# -# If you provide your own specs file for a device not yet known to -# AVR-LibC, you can now define the hook macro __AVR_DEV_LIB_NAME__ -# as needed so that -# -# #include -# -# will include the desired device header. For ATmega8A the supplement -# to *cpp would read -# -# -D__AVR_DEV_LIB_NAME__=m8a - - -*cpp: - -D__AVR_ATtiny2313A__ -D__AVR_DEVICE_NAME__=attiny2313a - -# End of file diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-attiny24 b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-attiny24 deleted file mode 100644 index cdf07c7..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-attiny24 +++ /dev/null @@ -1,99 +0,0 @@ -# -# Auto-generated specs for AVR device attiny24 (core avr25, 8-bit SP) -# -# Generated by : ./gcc/config/avr/gen-avr-mmcu-specs.c -# Generated from : ./gcc/config/gcc.c -# ./gcc/config/avr/specs.h -# ./gcc/config/avr/avrlibc.h -# Used by : avr-gcc compiler driver -# Used for : building command options for sub-processes -# -# See -# for a documentation of spec files. - - -# If you intend to use an existing device specs file as a starting point -# for a new device spec file, make sure you are copying from a specs -# file for a device from the same core architecture and SP width. -# See for a description -# of how to use such own spec files. - -*avrlibc_startfile: - crtattiny24.o%s - -*avrlibc_devicelib: - %{!nodevicelib:-lattiny24} - -*cc1_n_flash: - %{!mn-flash=*:-mn-flash=1} - -*cc1_rmw: - %{mrmw} - -*cc1_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*cc1_absdata: - %{mabsdata} - -*asm_arch: - -mmcu=avr25 - -*asm_relax: - %{mrelax:--mlink-relax} - -*asm_rmw: - %{mrmw} - -*asm_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*link_pmem_wrap: - - -*link_relax: - %{mrelax:--relax} - -*link_arch: - %{mmcu=*:-m%*} - -*link_data_start: - - -*link_text_start: - - -*self_spec: - %{!mmcu=avr*: % -# #elif ... -# -# If no device macro is defined, AVR-LibC uses __AVR_DEV_LIB_NAME__ -# as fallback to determine the name of the device header as -# -# "avr/io" + __AVR_DEV_LIB_NAME__ + ".h" -# -# If you provide your own specs file for a device not yet known to -# AVR-LibC, you can now define the hook macro __AVR_DEV_LIB_NAME__ -# as needed so that -# -# #include -# -# will include the desired device header. For ATmega8A the supplement -# to *cpp would read -# -# -D__AVR_DEV_LIB_NAME__=m8a - - -*cpp: - -D__AVR_ATtiny24__ -D__AVR_DEVICE_NAME__=attiny24 - -# End of file diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-attiny24a b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-attiny24a deleted file mode 100644 index a1646c5..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-attiny24a +++ /dev/null @@ -1,99 +0,0 @@ -# -# Auto-generated specs for AVR device attiny24a (core avr25, 8-bit SP) -# -# Generated by : ./gcc/config/avr/gen-avr-mmcu-specs.c -# Generated from : ./gcc/config/gcc.c -# ./gcc/config/avr/specs.h -# ./gcc/config/avr/avrlibc.h -# Used by : avr-gcc compiler driver -# Used for : building command options for sub-processes -# -# See -# for a documentation of spec files. - - -# If you intend to use an existing device specs file as a starting point -# for a new device spec file, make sure you are copying from a specs -# file for a device from the same core architecture and SP width. -# See for a description -# of how to use such own spec files. - -*avrlibc_startfile: - crtattiny24a.o%s - -*avrlibc_devicelib: - %{!nodevicelib:-lattiny24a} - -*cc1_n_flash: - %{!mn-flash=*:-mn-flash=1} - -*cc1_rmw: - %{mrmw} - -*cc1_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*cc1_absdata: - %{mabsdata} - -*asm_arch: - -mmcu=avr25 - -*asm_relax: - %{mrelax:--mlink-relax} - -*asm_rmw: - %{mrmw} - -*asm_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*link_pmem_wrap: - - -*link_relax: - %{mrelax:--relax} - -*link_arch: - %{mmcu=*:-m%*} - -*link_data_start: - - -*link_text_start: - - -*self_spec: - %{!mmcu=avr*: % -# #elif ... -# -# If no device macro is defined, AVR-LibC uses __AVR_DEV_LIB_NAME__ -# as fallback to determine the name of the device header as -# -# "avr/io" + __AVR_DEV_LIB_NAME__ + ".h" -# -# If you provide your own specs file for a device not yet known to -# AVR-LibC, you can now define the hook macro __AVR_DEV_LIB_NAME__ -# as needed so that -# -# #include -# -# will include the desired device header. For ATmega8A the supplement -# to *cpp would read -# -# -D__AVR_DEV_LIB_NAME__=m8a - - -*cpp: - -D__AVR_ATtiny24A__ -D__AVR_DEVICE_NAME__=attiny24a - -# End of file diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-attiny25 b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-attiny25 deleted file mode 100644 index 8214a84..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-attiny25 +++ /dev/null @@ -1,99 +0,0 @@ -# -# Auto-generated specs for AVR device attiny25 (core avr25, 8-bit SP) -# -# Generated by : ./gcc/config/avr/gen-avr-mmcu-specs.c -# Generated from : ./gcc/config/gcc.c -# ./gcc/config/avr/specs.h -# ./gcc/config/avr/avrlibc.h -# Used by : avr-gcc compiler driver -# Used for : building command options for sub-processes -# -# See -# for a documentation of spec files. - - -# If you intend to use an existing device specs file as a starting point -# for a new device spec file, make sure you are copying from a specs -# file for a device from the same core architecture and SP width. -# See for a description -# of how to use such own spec files. - -*avrlibc_startfile: - crtattiny25.o%s - -*avrlibc_devicelib: - %{!nodevicelib:-lattiny25} - -*cc1_n_flash: - %{!mn-flash=*:-mn-flash=1} - -*cc1_rmw: - %{mrmw} - -*cc1_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*cc1_absdata: - %{mabsdata} - -*asm_arch: - -mmcu=avr25 - -*asm_relax: - %{mrelax:--mlink-relax} - -*asm_rmw: - %{mrmw} - -*asm_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*link_pmem_wrap: - - -*link_relax: - %{mrelax:--relax} - -*link_arch: - %{mmcu=*:-m%*} - -*link_data_start: - - -*link_text_start: - - -*self_spec: - %{!mmcu=avr*: % -# #elif ... -# -# If no device macro is defined, AVR-LibC uses __AVR_DEV_LIB_NAME__ -# as fallback to determine the name of the device header as -# -# "avr/io" + __AVR_DEV_LIB_NAME__ + ".h" -# -# If you provide your own specs file for a device not yet known to -# AVR-LibC, you can now define the hook macro __AVR_DEV_LIB_NAME__ -# as needed so that -# -# #include -# -# will include the desired device header. For ATmega8A the supplement -# to *cpp would read -# -# -D__AVR_DEV_LIB_NAME__=m8a - - -*cpp: - -D__AVR_ATtiny25__ -D__AVR_DEVICE_NAME__=attiny25 - -# End of file diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-attiny26 b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-attiny26 deleted file mode 100644 index ae2dd9f..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-attiny26 +++ /dev/null @@ -1,99 +0,0 @@ -# -# Auto-generated specs for AVR device attiny26 (core avr2, 8-bit SP) -# -# Generated by : ./gcc/config/avr/gen-avr-mmcu-specs.c -# Generated from : ./gcc/config/gcc.c -# ./gcc/config/avr/specs.h -# ./gcc/config/avr/avrlibc.h -# Used by : avr-gcc compiler driver -# Used for : building command options for sub-processes -# -# See -# for a documentation of spec files. - - -# If you intend to use an existing device specs file as a starting point -# for a new device spec file, make sure you are copying from a specs -# file for a device from the same core architecture and SP width. -# See for a description -# of how to use such own spec files. - -*avrlibc_startfile: - crtattiny26.o%s - -*avrlibc_devicelib: - %{!nodevicelib:-lattiny26} - -*cc1_n_flash: - %{!mn-flash=*:-mn-flash=1} - -*cc1_rmw: - %{mrmw} - -*cc1_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*cc1_absdata: - %{mabsdata} - -*asm_arch: - -mmcu=avr2 - -*asm_relax: - %{mrelax:--mlink-relax} - -*asm_rmw: - %{mrmw} - -*asm_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*link_pmem_wrap: - - -*link_relax: - %{mrelax:--relax} - -*link_arch: - %{mmcu=*:-m%*} - -*link_data_start: - - -*link_text_start: - - -*self_spec: - %{!mmcu=avr*: % -# #elif ... -# -# If no device macro is defined, AVR-LibC uses __AVR_DEV_LIB_NAME__ -# as fallback to determine the name of the device header as -# -# "avr/io" + __AVR_DEV_LIB_NAME__ + ".h" -# -# If you provide your own specs file for a device not yet known to -# AVR-LibC, you can now define the hook macro __AVR_DEV_LIB_NAME__ -# as needed so that -# -# #include -# -# will include the desired device header. For ATmega8A the supplement -# to *cpp would read -# -# -D__AVR_DEV_LIB_NAME__=m8a - - -*cpp: - -D__AVR_ATtiny26__ -D__AVR_DEVICE_NAME__=attiny26 - -# End of file diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-attiny261 b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-attiny261 deleted file mode 100644 index 7979d94..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-attiny261 +++ /dev/null @@ -1,99 +0,0 @@ -# -# Auto-generated specs for AVR device attiny261 (core avr25, 8-bit SP) -# -# Generated by : ./gcc/config/avr/gen-avr-mmcu-specs.c -# Generated from : ./gcc/config/gcc.c -# ./gcc/config/avr/specs.h -# ./gcc/config/avr/avrlibc.h -# Used by : avr-gcc compiler driver -# Used for : building command options for sub-processes -# -# See -# for a documentation of spec files. - - -# If you intend to use an existing device specs file as a starting point -# for a new device spec file, make sure you are copying from a specs -# file for a device from the same core architecture and SP width. -# See for a description -# of how to use such own spec files. - -*avrlibc_startfile: - crtattiny261.o%s - -*avrlibc_devicelib: - %{!nodevicelib:-lattiny261} - -*cc1_n_flash: - %{!mn-flash=*:-mn-flash=1} - -*cc1_rmw: - %{mrmw} - -*cc1_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*cc1_absdata: - %{mabsdata} - -*asm_arch: - -mmcu=avr25 - -*asm_relax: - %{mrelax:--mlink-relax} - -*asm_rmw: - %{mrmw} - -*asm_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*link_pmem_wrap: - - -*link_relax: - %{mrelax:--relax} - -*link_arch: - %{mmcu=*:-m%*} - -*link_data_start: - - -*link_text_start: - - -*self_spec: - %{!mmcu=avr*: % -# #elif ... -# -# If no device macro is defined, AVR-LibC uses __AVR_DEV_LIB_NAME__ -# as fallback to determine the name of the device header as -# -# "avr/io" + __AVR_DEV_LIB_NAME__ + ".h" -# -# If you provide your own specs file for a device not yet known to -# AVR-LibC, you can now define the hook macro __AVR_DEV_LIB_NAME__ -# as needed so that -# -# #include -# -# will include the desired device header. For ATmega8A the supplement -# to *cpp would read -# -# -D__AVR_DEV_LIB_NAME__=m8a - - -*cpp: - -D__AVR_ATtiny261__ -D__AVR_DEVICE_NAME__=attiny261 - -# End of file diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-attiny261a b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-attiny261a deleted file mode 100644 index f0c9d09..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-attiny261a +++ /dev/null @@ -1,99 +0,0 @@ -# -# Auto-generated specs for AVR device attiny261a (core avr25, 8-bit SP) -# -# Generated by : ./gcc/config/avr/gen-avr-mmcu-specs.c -# Generated from : ./gcc/config/gcc.c -# ./gcc/config/avr/specs.h -# ./gcc/config/avr/avrlibc.h -# Used by : avr-gcc compiler driver -# Used for : building command options for sub-processes -# -# See -# for a documentation of spec files. - - -# If you intend to use an existing device specs file as a starting point -# for a new device spec file, make sure you are copying from a specs -# file for a device from the same core architecture and SP width. -# See for a description -# of how to use such own spec files. - -*avrlibc_startfile: - crtattiny261a.o%s - -*avrlibc_devicelib: - %{!nodevicelib:-lattiny261a} - -*cc1_n_flash: - %{!mn-flash=*:-mn-flash=1} - -*cc1_rmw: - %{mrmw} - -*cc1_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*cc1_absdata: - %{mabsdata} - -*asm_arch: - -mmcu=avr25 - -*asm_relax: - %{mrelax:--mlink-relax} - -*asm_rmw: - %{mrmw} - -*asm_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*link_pmem_wrap: - - -*link_relax: - %{mrelax:--relax} - -*link_arch: - %{mmcu=*:-m%*} - -*link_data_start: - - -*link_text_start: - - -*self_spec: - %{!mmcu=avr*: % -# #elif ... -# -# If no device macro is defined, AVR-LibC uses __AVR_DEV_LIB_NAME__ -# as fallback to determine the name of the device header as -# -# "avr/io" + __AVR_DEV_LIB_NAME__ + ".h" -# -# If you provide your own specs file for a device not yet known to -# AVR-LibC, you can now define the hook macro __AVR_DEV_LIB_NAME__ -# as needed so that -# -# #include -# -# will include the desired device header. For ATmega8A the supplement -# to *cpp would read -# -# -D__AVR_DEV_LIB_NAME__=m8a - - -*cpp: - -D__AVR_ATtiny261A__ -D__AVR_DEVICE_NAME__=attiny261a - -# End of file diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-attiny28 b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-attiny28 deleted file mode 100644 index 2be3969..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-attiny28 +++ /dev/null @@ -1,99 +0,0 @@ -# -# Auto-generated specs for AVR device attiny28 (core avr1, 16-bit SP) -# -# Generated by : ./gcc/config/avr/gen-avr-mmcu-specs.c -# Generated from : ./gcc/config/gcc.c -# ./gcc/config/avr/specs.h -# ./gcc/config/avr/avrlibc.h -# Used by : avr-gcc compiler driver -# Used for : building command options for sub-processes -# -# See -# for a documentation of spec files. - - -# If you intend to use an existing device specs file as a starting point -# for a new device spec file, make sure you are copying from a specs -# file for a device from the same core architecture and SP width. -# See for a description -# of how to use such own spec files. - -*avrlibc_startfile: - crtattiny28.o%s - -*avrlibc_devicelib: - %{!nodevicelib:-lattiny28} - -*cc1_n_flash: - %{!mn-flash=*:-mn-flash=1} - -*cc1_rmw: - %{mrmw} - -*cc1_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*cc1_absdata: - %{mabsdata} - -*asm_arch: - -mmcu=avr1 - -*asm_relax: - %{mrelax:--mlink-relax} - -*asm_rmw: - %{mrmw} - -*asm_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*link_pmem_wrap: - - -*link_relax: - %{mrelax:--relax} - -*link_arch: - %{mmcu=*:-m%*} - -*link_data_start: - - -*link_text_start: - - -*self_spec: - %{!mmcu=avr*: % -# #elif ... -# -# If no device macro is defined, AVR-LibC uses __AVR_DEV_LIB_NAME__ -# as fallback to determine the name of the device header as -# -# "avr/io" + __AVR_DEV_LIB_NAME__ + ".h" -# -# If you provide your own specs file for a device not yet known to -# AVR-LibC, you can now define the hook macro __AVR_DEV_LIB_NAME__ -# as needed so that -# -# #include -# -# will include the desired device header. For ATmega8A the supplement -# to *cpp would read -# -# -D__AVR_DEV_LIB_NAME__=m8a - - -*cpp: - -D__AVR_ATtiny28__ -D__AVR_DEVICE_NAME__=attiny28 - -# End of file diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-attiny3214 b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-attiny3214 deleted file mode 100644 index 47669ca..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-attiny3214 +++ /dev/null @@ -1,99 +0,0 @@ -# -# Auto-generated specs for AVR device attiny3214 (core avrxmega3, 16-bit SP) -# -# Generated by : ./gcc/config/avr/gen-avr-mmcu-specs.c -# Generated from : ./gcc/config/gcc.c -# ./gcc/config/avr/specs.h -# ./gcc/config/avr/avrlibc.h -# Used by : avr-gcc compiler driver -# Used for : building command options for sub-processes -# -# See -# for a documentation of spec files. - - -# If you intend to use an existing device specs file as a starting point -# for a new device spec file, make sure you are copying from a specs -# file for a device from the same core architecture and SP width. -# See for a description -# of how to use such own spec files. - -*avrlibc_startfile: - crtattiny3214.o%s - -*avrlibc_devicelib: - %{!nodevicelib:-lattiny3214} - -*cc1_n_flash: - %{!mn-flash=*:-mn-flash=1} - -*cc1_rmw: - %{mrmw} - -*cc1_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*cc1_absdata: - %{mabsdata} - -*asm_arch: - -mmcu=avrxmega3 - -*asm_relax: - %{mrelax:--mlink-relax} - -*asm_rmw: - %{mrmw} - -*asm_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*link_pmem_wrap: - %{mpmem-wrap-around: --pmem-wrap-around=32k} - -*link_relax: - %{mrelax:--relax} - -*link_arch: - %{mmcu=*:-m%*} - -*link_data_start: - -Tdata 0x803800 - -*link_text_start: - - -*self_spec: - %{!mmcu=avr*: % -# #elif ... -# -# If no device macro is defined, AVR-LibC uses __AVR_DEV_LIB_NAME__ -# as fallback to determine the name of the device header as -# -# "avr/io" + __AVR_DEV_LIB_NAME__ + ".h" -# -# If you provide your own specs file for a device not yet known to -# AVR-LibC, you can now define the hook macro __AVR_DEV_LIB_NAME__ -# as needed so that -# -# #include -# -# will include the desired device header. For ATmega8A the supplement -# to *cpp would read -# -# -D__AVR_DEV_LIB_NAME__=m8a - - -*cpp: - -D__AVR_ATtiny3214__ -D__AVR_DEVICE_NAME__=attiny3214 - -# End of file diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-attiny3216 b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-attiny3216 deleted file mode 100644 index 1c77fdf..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-attiny3216 +++ /dev/null @@ -1,99 +0,0 @@ -# -# Auto-generated specs for AVR device attiny3216 (core avrxmega3, 16-bit SP) -# -# Generated by : ./gcc/config/avr/gen-avr-mmcu-specs.c -# Generated from : ./gcc/config/gcc.c -# ./gcc/config/avr/specs.h -# ./gcc/config/avr/avrlibc.h -# Used by : avr-gcc compiler driver -# Used for : building command options for sub-processes -# -# See -# for a documentation of spec files. - - -# If you intend to use an existing device specs file as a starting point -# for a new device spec file, make sure you are copying from a specs -# file for a device from the same core architecture and SP width. -# See for a description -# of how to use such own spec files. - -*avrlibc_startfile: - crtattiny3216.o%s - -*avrlibc_devicelib: - %{!nodevicelib:-lattiny3216} - -*cc1_n_flash: - %{!mn-flash=*:-mn-flash=1} - -*cc1_rmw: - %{mrmw} - -*cc1_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*cc1_absdata: - %{mabsdata} - -*asm_arch: - -mmcu=avrxmega3 - -*asm_relax: - %{mrelax:--mlink-relax} - -*asm_rmw: - %{mrmw} - -*asm_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*link_pmem_wrap: - %{mpmem-wrap-around: --pmem-wrap-around=32k} - -*link_relax: - %{mrelax:--relax} - -*link_arch: - %{mmcu=*:-m%*} - -*link_data_start: - -Tdata 0x803800 - -*link_text_start: - - -*self_spec: - %{!mmcu=avr*: % -# #elif ... -# -# If no device macro is defined, AVR-LibC uses __AVR_DEV_LIB_NAME__ -# as fallback to determine the name of the device header as -# -# "avr/io" + __AVR_DEV_LIB_NAME__ + ".h" -# -# If you provide your own specs file for a device not yet known to -# AVR-LibC, you can now define the hook macro __AVR_DEV_LIB_NAME__ -# as needed so that -# -# #include -# -# will include the desired device header. For ATmega8A the supplement -# to *cpp would read -# -# -D__AVR_DEV_LIB_NAME__=m8a - - -*cpp: - -D__AVR_ATtiny3216__ -D__AVR_DEVICE_NAME__=attiny3216 - -# End of file diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-attiny3217 b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-attiny3217 deleted file mode 100644 index 1722636..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-attiny3217 +++ /dev/null @@ -1,99 +0,0 @@ -# -# Auto-generated specs for AVR device attiny3217 (core avrxmega3, 16-bit SP) -# -# Generated by : ./gcc/config/avr/gen-avr-mmcu-specs.c -# Generated from : ./gcc/config/gcc.c -# ./gcc/config/avr/specs.h -# ./gcc/config/avr/avrlibc.h -# Used by : avr-gcc compiler driver -# Used for : building command options for sub-processes -# -# See -# for a documentation of spec files. - - -# If you intend to use an existing device specs file as a starting point -# for a new device spec file, make sure you are copying from a specs -# file for a device from the same core architecture and SP width. -# See for a description -# of how to use such own spec files. - -*avrlibc_startfile: - crtattiny3217.o%s - -*avrlibc_devicelib: - %{!nodevicelib:-lattiny3217} - -*cc1_n_flash: - %{!mn-flash=*:-mn-flash=1} - -*cc1_rmw: - %{mrmw} - -*cc1_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*cc1_absdata: - %{mabsdata} - -*asm_arch: - -mmcu=avrxmega3 - -*asm_relax: - %{mrelax:--mlink-relax} - -*asm_rmw: - %{mrmw} - -*asm_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*link_pmem_wrap: - %{mpmem-wrap-around: --pmem-wrap-around=32k} - -*link_relax: - %{mrelax:--relax} - -*link_arch: - %{mmcu=*:-m%*} - -*link_data_start: - -Tdata 0x803800 - -*link_text_start: - - -*self_spec: - %{!mmcu=avr*: % -# #elif ... -# -# If no device macro is defined, AVR-LibC uses __AVR_DEV_LIB_NAME__ -# as fallback to determine the name of the device header as -# -# "avr/io" + __AVR_DEV_LIB_NAME__ + ".h" -# -# If you provide your own specs file for a device not yet known to -# AVR-LibC, you can now define the hook macro __AVR_DEV_LIB_NAME__ -# as needed so that -# -# #include -# -# will include the desired device header. For ATmega8A the supplement -# to *cpp would read -# -# -D__AVR_DEV_LIB_NAME__=m8a - - -*cpp: - -D__AVR_ATtiny3217__ -D__AVR_DEVICE_NAME__=attiny3217 - -# End of file diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-attiny4 b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-attiny4 deleted file mode 100644 index 9d61d3a..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-attiny4 +++ /dev/null @@ -1,99 +0,0 @@ -# -# Auto-generated specs for AVR device attiny4 (core avrtiny, 16-bit SP) -# -# Generated by : ./gcc/config/avr/gen-avr-mmcu-specs.c -# Generated from : ./gcc/config/gcc.c -# ./gcc/config/avr/specs.h -# ./gcc/config/avr/avrlibc.h -# Used by : avr-gcc compiler driver -# Used for : building command options for sub-processes -# -# See -# for a documentation of spec files. - - -# If you intend to use an existing device specs file as a starting point -# for a new device spec file, make sure you are copying from a specs -# file for a device from the same core architecture and SP width. -# See for a description -# of how to use such own spec files. - -*avrlibc_startfile: - crtattiny4.o%s - -*avrlibc_devicelib: - %{!nodevicelib:-lattiny4} - -*cc1_n_flash: - %{!mn-flash=*:-mn-flash=1} - -*cc1_rmw: - %{mrmw} - -*cc1_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*cc1_absdata: - %{!mno-absdata: -mabsdata} - -*asm_arch: - -mmcu=avrtiny - -*asm_relax: - %{mrelax:--mlink-relax} - -*asm_rmw: - %{mrmw} - -*asm_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*link_pmem_wrap: - - -*link_relax: - %{mrelax:--relax} - -*link_arch: - %{mmcu=*:-m%*} - -*link_data_start: - - -*link_text_start: - - -*self_spec: - %{!mmcu=avr*: % -# #elif ... -# -# If no device macro is defined, AVR-LibC uses __AVR_DEV_LIB_NAME__ -# as fallback to determine the name of the device header as -# -# "avr/io" + __AVR_DEV_LIB_NAME__ + ".h" -# -# If you provide your own specs file for a device not yet known to -# AVR-LibC, you can now define the hook macro __AVR_DEV_LIB_NAME__ -# as needed so that -# -# #include -# -# will include the desired device header. For ATmega8A the supplement -# to *cpp would read -# -# -D__AVR_DEV_LIB_NAME__=m8a - - -*cpp: - -D__AVR_ATtiny4__ -D__AVR_DEVICE_NAME__=attiny4 - -# End of file diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-attiny40 b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-attiny40 deleted file mode 100644 index c5e929a..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-attiny40 +++ /dev/null @@ -1,99 +0,0 @@ -# -# Auto-generated specs for AVR device attiny40 (core avrtiny, 16-bit SP) -# -# Generated by : ./gcc/config/avr/gen-avr-mmcu-specs.c -# Generated from : ./gcc/config/gcc.c -# ./gcc/config/avr/specs.h -# ./gcc/config/avr/avrlibc.h -# Used by : avr-gcc compiler driver -# Used for : building command options for sub-processes -# -# See -# for a documentation of spec files. - - -# If you intend to use an existing device specs file as a starting point -# for a new device spec file, make sure you are copying from a specs -# file for a device from the same core architecture and SP width. -# See for a description -# of how to use such own spec files. - -*avrlibc_startfile: - crtattiny40.o%s - -*avrlibc_devicelib: - %{!nodevicelib:-lattiny40} - -*cc1_n_flash: - %{!mn-flash=*:-mn-flash=1} - -*cc1_rmw: - %{mrmw} - -*cc1_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*cc1_absdata: - %{mabsdata} - -*asm_arch: - -mmcu=avrtiny - -*asm_relax: - %{mrelax:--mlink-relax} - -*asm_rmw: - %{mrmw} - -*asm_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*link_pmem_wrap: - - -*link_relax: - %{mrelax:--relax} - -*link_arch: - %{mmcu=*:-m%*} - -*link_data_start: - - -*link_text_start: - - -*self_spec: - %{!mmcu=avr*: % -# #elif ... -# -# If no device macro is defined, AVR-LibC uses __AVR_DEV_LIB_NAME__ -# as fallback to determine the name of the device header as -# -# "avr/io" + __AVR_DEV_LIB_NAME__ + ".h" -# -# If you provide your own specs file for a device not yet known to -# AVR-LibC, you can now define the hook macro __AVR_DEV_LIB_NAME__ -# as needed so that -# -# #include -# -# will include the desired device header. For ATmega8A the supplement -# to *cpp would read -# -# -D__AVR_DEV_LIB_NAME__=m8a - - -*cpp: - -D__AVR_ATtiny40__ -D__AVR_DEVICE_NAME__=attiny40 - -# End of file diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-attiny412 b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-attiny412 deleted file mode 100644 index e8bb263..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-attiny412 +++ /dev/null @@ -1,99 +0,0 @@ -# -# Auto-generated specs for AVR device attiny412 (core avrxmega3, 16-bit SP, short-calls) -# -# Generated by : ./gcc/config/avr/gen-avr-mmcu-specs.c -# Generated from : ./gcc/config/gcc.c -# ./gcc/config/avr/specs.h -# ./gcc/config/avr/avrlibc.h -# Used by : avr-gcc compiler driver -# Used for : building command options for sub-processes -# -# See -# for a documentation of spec files. - - -# If you intend to use an existing device specs file as a starting point -# for a new device spec file, make sure you are copying from a specs -# file for a device from the same core architecture and SP width. -# See for a description -# of how to use such own spec files. - -*avrlibc_startfile: - crtattiny412.o%s - -*avrlibc_devicelib: - %{!nodevicelib:-lattiny412} - -*cc1_n_flash: - %{!mn-flash=*:-mn-flash=1} - -*cc1_rmw: - %{mrmw} - -*cc1_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*cc1_absdata: - %{mabsdata} - -*asm_arch: - -mmcu=avrxmega3 - -*asm_relax: - %{mrelax:--mlink-relax} - -*asm_rmw: - %{mrmw} - -*asm_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*link_pmem_wrap: - - -*link_relax: - %{mrelax:--relax} - -*link_arch: - %{mmcu=*:-m%*} - -*link_data_start: - -Tdata 0x803F00 - -*link_text_start: - - -*self_spec: - %{!mmcu=avr*: % -# #elif ... -# -# If no device macro is defined, AVR-LibC uses __AVR_DEV_LIB_NAME__ -# as fallback to determine the name of the device header as -# -# "avr/io" + __AVR_DEV_LIB_NAME__ + ".h" -# -# If you provide your own specs file for a device not yet known to -# AVR-LibC, you can now define the hook macro __AVR_DEV_LIB_NAME__ -# as needed so that -# -# #include -# -# will include the desired device header. For ATmega8A the supplement -# to *cpp would read -# -# -D__AVR_DEV_LIB_NAME__=m8a - - -*cpp: - -D__AVR_ATtiny412__ -D__AVR_DEVICE_NAME__=attiny412 - -# End of file diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-attiny414 b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-attiny414 deleted file mode 100644 index 753e195..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-attiny414 +++ /dev/null @@ -1,99 +0,0 @@ -# -# Auto-generated specs for AVR device attiny414 (core avrxmega3, 16-bit SP, short-calls) -# -# Generated by : ./gcc/config/avr/gen-avr-mmcu-specs.c -# Generated from : ./gcc/config/gcc.c -# ./gcc/config/avr/specs.h -# ./gcc/config/avr/avrlibc.h -# Used by : avr-gcc compiler driver -# Used for : building command options for sub-processes -# -# See -# for a documentation of spec files. - - -# If you intend to use an existing device specs file as a starting point -# for a new device spec file, make sure you are copying from a specs -# file for a device from the same core architecture and SP width. -# See for a description -# of how to use such own spec files. - -*avrlibc_startfile: - crtattiny414.o%s - -*avrlibc_devicelib: - %{!nodevicelib:-lattiny414} - -*cc1_n_flash: - %{!mn-flash=*:-mn-flash=1} - -*cc1_rmw: - %{mrmw} - -*cc1_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*cc1_absdata: - %{mabsdata} - -*asm_arch: - -mmcu=avrxmega3 - -*asm_relax: - %{mrelax:--mlink-relax} - -*asm_rmw: - %{mrmw} - -*asm_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*link_pmem_wrap: - - -*link_relax: - %{mrelax:--relax} - -*link_arch: - %{mmcu=*:-m%*} - -*link_data_start: - -Tdata 0x803F00 - -*link_text_start: - - -*self_spec: - %{!mmcu=avr*: % -# #elif ... -# -# If no device macro is defined, AVR-LibC uses __AVR_DEV_LIB_NAME__ -# as fallback to determine the name of the device header as -# -# "avr/io" + __AVR_DEV_LIB_NAME__ + ".h" -# -# If you provide your own specs file for a device not yet known to -# AVR-LibC, you can now define the hook macro __AVR_DEV_LIB_NAME__ -# as needed so that -# -# #include -# -# will include the desired device header. For ATmega8A the supplement -# to *cpp would read -# -# -D__AVR_DEV_LIB_NAME__=m8a - - -*cpp: - -D__AVR_ATtiny414__ -D__AVR_DEVICE_NAME__=attiny414 - -# End of file diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-attiny416 b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-attiny416 deleted file mode 100644 index 34bf7fa..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-attiny416 +++ /dev/null @@ -1,99 +0,0 @@ -# -# Auto-generated specs for AVR device attiny416 (core avrxmega3, 16-bit SP, short-calls) -# -# Generated by : ./gcc/config/avr/gen-avr-mmcu-specs.c -# Generated from : ./gcc/config/gcc.c -# ./gcc/config/avr/specs.h -# ./gcc/config/avr/avrlibc.h -# Used by : avr-gcc compiler driver -# Used for : building command options for sub-processes -# -# See -# for a documentation of spec files. - - -# If you intend to use an existing device specs file as a starting point -# for a new device spec file, make sure you are copying from a specs -# file for a device from the same core architecture and SP width. -# See for a description -# of how to use such own spec files. - -*avrlibc_startfile: - crtattiny416.o%s - -*avrlibc_devicelib: - %{!nodevicelib:-lattiny416} - -*cc1_n_flash: - %{!mn-flash=*:-mn-flash=1} - -*cc1_rmw: - %{mrmw} - -*cc1_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*cc1_absdata: - %{mabsdata} - -*asm_arch: - -mmcu=avrxmega3 - -*asm_relax: - %{mrelax:--mlink-relax} - -*asm_rmw: - %{mrmw} - -*asm_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*link_pmem_wrap: - - -*link_relax: - %{mrelax:--relax} - -*link_arch: - %{mmcu=*:-m%*} - -*link_data_start: - -Tdata 0x803F00 - -*link_text_start: - - -*self_spec: - %{!mmcu=avr*: % -# #elif ... -# -# If no device macro is defined, AVR-LibC uses __AVR_DEV_LIB_NAME__ -# as fallback to determine the name of the device header as -# -# "avr/io" + __AVR_DEV_LIB_NAME__ + ".h" -# -# If you provide your own specs file for a device not yet known to -# AVR-LibC, you can now define the hook macro __AVR_DEV_LIB_NAME__ -# as needed so that -# -# #include -# -# will include the desired device header. For ATmega8A the supplement -# to *cpp would read -# -# -D__AVR_DEV_LIB_NAME__=m8a - - -*cpp: - -D__AVR_ATtiny416__ -D__AVR_DEVICE_NAME__=attiny416 - -# End of file diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-attiny417 b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-attiny417 deleted file mode 100644 index 05fcf8b..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-attiny417 +++ /dev/null @@ -1,99 +0,0 @@ -# -# Auto-generated specs for AVR device attiny417 (core avrxmega3, 16-bit SP, short-calls) -# -# Generated by : ./gcc/config/avr/gen-avr-mmcu-specs.c -# Generated from : ./gcc/config/gcc.c -# ./gcc/config/avr/specs.h -# ./gcc/config/avr/avrlibc.h -# Used by : avr-gcc compiler driver -# Used for : building command options for sub-processes -# -# See -# for a documentation of spec files. - - -# If you intend to use an existing device specs file as a starting point -# for a new device spec file, make sure you are copying from a specs -# file for a device from the same core architecture and SP width. -# See for a description -# of how to use such own spec files. - -*avrlibc_startfile: - crtattiny417.o%s - -*avrlibc_devicelib: - %{!nodevicelib:-lattiny417} - -*cc1_n_flash: - %{!mn-flash=*:-mn-flash=1} - -*cc1_rmw: - %{mrmw} - -*cc1_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*cc1_absdata: - %{mabsdata} - -*asm_arch: - -mmcu=avrxmega3 - -*asm_relax: - %{mrelax:--mlink-relax} - -*asm_rmw: - %{mrmw} - -*asm_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*link_pmem_wrap: - - -*link_relax: - %{mrelax:--relax} - -*link_arch: - %{mmcu=*:-m%*} - -*link_data_start: - -Tdata 0x803F00 - -*link_text_start: - - -*self_spec: - %{!mmcu=avr*: % -# #elif ... -# -# If no device macro is defined, AVR-LibC uses __AVR_DEV_LIB_NAME__ -# as fallback to determine the name of the device header as -# -# "avr/io" + __AVR_DEV_LIB_NAME__ + ".h" -# -# If you provide your own specs file for a device not yet known to -# AVR-LibC, you can now define the hook macro __AVR_DEV_LIB_NAME__ -# as needed so that -# -# #include -# -# will include the desired device header. For ATmega8A the supplement -# to *cpp would read -# -# -D__AVR_DEV_LIB_NAME__=m8a - - -*cpp: - -D__AVR_ATtiny417__ -D__AVR_DEVICE_NAME__=attiny417 - -# End of file diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-attiny4313 b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-attiny4313 deleted file mode 100644 index e4b8eb9..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-attiny4313 +++ /dev/null @@ -1,99 +0,0 @@ -# -# Auto-generated specs for AVR device attiny4313 (core avr25, 16-bit SP) -# -# Generated by : ./gcc/config/avr/gen-avr-mmcu-specs.c -# Generated from : ./gcc/config/gcc.c -# ./gcc/config/avr/specs.h -# ./gcc/config/avr/avrlibc.h -# Used by : avr-gcc compiler driver -# Used for : building command options for sub-processes -# -# See -# for a documentation of spec files. - - -# If you intend to use an existing device specs file as a starting point -# for a new device spec file, make sure you are copying from a specs -# file for a device from the same core architecture and SP width. -# See for a description -# of how to use such own spec files. - -*avrlibc_startfile: - crtattiny4313.o%s - -*avrlibc_devicelib: - %{!nodevicelib:-lattiny4313} - -*cc1_n_flash: - %{!mn-flash=*:-mn-flash=1} - -*cc1_rmw: - %{mrmw} - -*cc1_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*cc1_absdata: - %{mabsdata} - -*asm_arch: - -mmcu=avr25 - -*asm_relax: - %{mrelax:--mlink-relax} - -*asm_rmw: - %{mrmw} - -*asm_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*link_pmem_wrap: - - -*link_relax: - %{mrelax:--relax} - -*link_arch: - %{mmcu=*:-m%*} - -*link_data_start: - - -*link_text_start: - - -*self_spec: - %{!mmcu=avr*: % -# #elif ... -# -# If no device macro is defined, AVR-LibC uses __AVR_DEV_LIB_NAME__ -# as fallback to determine the name of the device header as -# -# "avr/io" + __AVR_DEV_LIB_NAME__ + ".h" -# -# If you provide your own specs file for a device not yet known to -# AVR-LibC, you can now define the hook macro __AVR_DEV_LIB_NAME__ -# as needed so that -# -# #include -# -# will include the desired device header. For ATmega8A the supplement -# to *cpp would read -# -# -D__AVR_DEV_LIB_NAME__=m8a - - -*cpp: - -D__AVR_ATtiny4313__ -D__AVR_DEVICE_NAME__=attiny4313 - -# End of file diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-attiny43u b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-attiny43u deleted file mode 100644 index 230f582..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-attiny43u +++ /dev/null @@ -1,99 +0,0 @@ -# -# Auto-generated specs for AVR device attiny43u (core avr25, 16-bit SP) -# -# Generated by : ./gcc/config/avr/gen-avr-mmcu-specs.c -# Generated from : ./gcc/config/gcc.c -# ./gcc/config/avr/specs.h -# ./gcc/config/avr/avrlibc.h -# Used by : avr-gcc compiler driver -# Used for : building command options for sub-processes -# -# See -# for a documentation of spec files. - - -# If you intend to use an existing device specs file as a starting point -# for a new device spec file, make sure you are copying from a specs -# file for a device from the same core architecture and SP width. -# See for a description -# of how to use such own spec files. - -*avrlibc_startfile: - crtattiny43u.o%s - -*avrlibc_devicelib: - %{!nodevicelib:-lattiny43u} - -*cc1_n_flash: - %{!mn-flash=*:-mn-flash=1} - -*cc1_rmw: - %{mrmw} - -*cc1_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*cc1_absdata: - %{mabsdata} - -*asm_arch: - -mmcu=avr25 - -*asm_relax: - %{mrelax:--mlink-relax} - -*asm_rmw: - %{mrmw} - -*asm_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*link_pmem_wrap: - - -*link_relax: - %{mrelax:--relax} - -*link_arch: - %{mmcu=*:-m%*} - -*link_data_start: - - -*link_text_start: - - -*self_spec: - %{!mmcu=avr*: % -# #elif ... -# -# If no device macro is defined, AVR-LibC uses __AVR_DEV_LIB_NAME__ -# as fallback to determine the name of the device header as -# -# "avr/io" + __AVR_DEV_LIB_NAME__ + ".h" -# -# If you provide your own specs file for a device not yet known to -# AVR-LibC, you can now define the hook macro __AVR_DEV_LIB_NAME__ -# as needed so that -# -# #include -# -# will include the desired device header. For ATmega8A the supplement -# to *cpp would read -# -# -D__AVR_DEV_LIB_NAME__=m8a - - -*cpp: - -D__AVR_ATtiny43U__ -D__AVR_DEVICE_NAME__=attiny43u - -# End of file diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-attiny44 b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-attiny44 deleted file mode 100644 index db653ac..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-attiny44 +++ /dev/null @@ -1,99 +0,0 @@ -# -# Auto-generated specs for AVR device attiny44 (core avr25, 16-bit SP) -# -# Generated by : ./gcc/config/avr/gen-avr-mmcu-specs.c -# Generated from : ./gcc/config/gcc.c -# ./gcc/config/avr/specs.h -# ./gcc/config/avr/avrlibc.h -# Used by : avr-gcc compiler driver -# Used for : building command options for sub-processes -# -# See -# for a documentation of spec files. - - -# If you intend to use an existing device specs file as a starting point -# for a new device spec file, make sure you are copying from a specs -# file for a device from the same core architecture and SP width. -# See for a description -# of how to use such own spec files. - -*avrlibc_startfile: - crtattiny44.o%s - -*avrlibc_devicelib: - %{!nodevicelib:-lattiny44} - -*cc1_n_flash: - %{!mn-flash=*:-mn-flash=1} - -*cc1_rmw: - %{mrmw} - -*cc1_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*cc1_absdata: - %{mabsdata} - -*asm_arch: - -mmcu=avr25 - -*asm_relax: - %{mrelax:--mlink-relax} - -*asm_rmw: - %{mrmw} - -*asm_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*link_pmem_wrap: - - -*link_relax: - %{mrelax:--relax} - -*link_arch: - %{mmcu=*:-m%*} - -*link_data_start: - - -*link_text_start: - - -*self_spec: - %{!mmcu=avr*: % -# #elif ... -# -# If no device macro is defined, AVR-LibC uses __AVR_DEV_LIB_NAME__ -# as fallback to determine the name of the device header as -# -# "avr/io" + __AVR_DEV_LIB_NAME__ + ".h" -# -# If you provide your own specs file for a device not yet known to -# AVR-LibC, you can now define the hook macro __AVR_DEV_LIB_NAME__ -# as needed so that -# -# #include -# -# will include the desired device header. For ATmega8A the supplement -# to *cpp would read -# -# -D__AVR_DEV_LIB_NAME__=m8a - - -*cpp: - -D__AVR_ATtiny44__ -D__AVR_DEVICE_NAME__=attiny44 - -# End of file diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-attiny441 b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-attiny441 deleted file mode 100644 index 2409d04..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-attiny441 +++ /dev/null @@ -1,99 +0,0 @@ -# -# Auto-generated specs for AVR device attiny441 (core avr25, 16-bit SP) -# -# Generated by : ./gcc/config/avr/gen-avr-mmcu-specs.c -# Generated from : ./gcc/config/gcc.c -# ./gcc/config/avr/specs.h -# ./gcc/config/avr/avrlibc.h -# Used by : avr-gcc compiler driver -# Used for : building command options for sub-processes -# -# See -# for a documentation of spec files. - - -# If you intend to use an existing device specs file as a starting point -# for a new device spec file, make sure you are copying from a specs -# file for a device from the same core architecture and SP width. -# See for a description -# of how to use such own spec files. - -*avrlibc_startfile: - crtattiny441.o%s - -*avrlibc_devicelib: - %{!nodevicelib:-lattiny441} - -*cc1_n_flash: - %{!mn-flash=*:-mn-flash=1} - -*cc1_rmw: - %{mrmw} - -*cc1_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*cc1_absdata: - %{mabsdata} - -*asm_arch: - -mmcu=avr25 - -*asm_relax: - %{mrelax:--mlink-relax} - -*asm_rmw: - %{mrmw} - -*asm_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*link_pmem_wrap: - - -*link_relax: - %{mrelax:--relax} - -*link_arch: - %{mmcu=*:-m%*} - -*link_data_start: - -Tdata 0x800100 - -*link_text_start: - - -*self_spec: - %{!mmcu=avr*: % -# #elif ... -# -# If no device macro is defined, AVR-LibC uses __AVR_DEV_LIB_NAME__ -# as fallback to determine the name of the device header as -# -# "avr/io" + __AVR_DEV_LIB_NAME__ + ".h" -# -# If you provide your own specs file for a device not yet known to -# AVR-LibC, you can now define the hook macro __AVR_DEV_LIB_NAME__ -# as needed so that -# -# #include -# -# will include the desired device header. For ATmega8A the supplement -# to *cpp would read -# -# -D__AVR_DEV_LIB_NAME__=m8a - - -*cpp: - -D__AVR_ATtiny441__ -D__AVR_DEVICE_NAME__=attiny441 - -# End of file diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-attiny44a b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-attiny44a deleted file mode 100644 index bfd935d..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-attiny44a +++ /dev/null @@ -1,99 +0,0 @@ -# -# Auto-generated specs for AVR device attiny44a (core avr25, 16-bit SP) -# -# Generated by : ./gcc/config/avr/gen-avr-mmcu-specs.c -# Generated from : ./gcc/config/gcc.c -# ./gcc/config/avr/specs.h -# ./gcc/config/avr/avrlibc.h -# Used by : avr-gcc compiler driver -# Used for : building command options for sub-processes -# -# See -# for a documentation of spec files. - - -# If you intend to use an existing device specs file as a starting point -# for a new device spec file, make sure you are copying from a specs -# file for a device from the same core architecture and SP width. -# See for a description -# of how to use such own spec files. - -*avrlibc_startfile: - crtattiny44a.o%s - -*avrlibc_devicelib: - %{!nodevicelib:-lattiny44a} - -*cc1_n_flash: - %{!mn-flash=*:-mn-flash=1} - -*cc1_rmw: - %{mrmw} - -*cc1_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*cc1_absdata: - %{mabsdata} - -*asm_arch: - -mmcu=avr25 - -*asm_relax: - %{mrelax:--mlink-relax} - -*asm_rmw: - %{mrmw} - -*asm_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*link_pmem_wrap: - - -*link_relax: - %{mrelax:--relax} - -*link_arch: - %{mmcu=*:-m%*} - -*link_data_start: - - -*link_text_start: - - -*self_spec: - %{!mmcu=avr*: % -# #elif ... -# -# If no device macro is defined, AVR-LibC uses __AVR_DEV_LIB_NAME__ -# as fallback to determine the name of the device header as -# -# "avr/io" + __AVR_DEV_LIB_NAME__ + ".h" -# -# If you provide your own specs file for a device not yet known to -# AVR-LibC, you can now define the hook macro __AVR_DEV_LIB_NAME__ -# as needed so that -# -# #include -# -# will include the desired device header. For ATmega8A the supplement -# to *cpp would read -# -# -D__AVR_DEV_LIB_NAME__=m8a - - -*cpp: - -D__AVR_ATtiny44A__ -D__AVR_DEVICE_NAME__=attiny44a - -# End of file diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-attiny45 b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-attiny45 deleted file mode 100644 index dc329db..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-attiny45 +++ /dev/null @@ -1,99 +0,0 @@ -# -# Auto-generated specs for AVR device attiny45 (core avr25, 16-bit SP) -# -# Generated by : ./gcc/config/avr/gen-avr-mmcu-specs.c -# Generated from : ./gcc/config/gcc.c -# ./gcc/config/avr/specs.h -# ./gcc/config/avr/avrlibc.h -# Used by : avr-gcc compiler driver -# Used for : building command options for sub-processes -# -# See -# for a documentation of spec files. - - -# If you intend to use an existing device specs file as a starting point -# for a new device spec file, make sure you are copying from a specs -# file for a device from the same core architecture and SP width. -# See for a description -# of how to use such own spec files. - -*avrlibc_startfile: - crtattiny45.o%s - -*avrlibc_devicelib: - %{!nodevicelib:-lattiny45} - -*cc1_n_flash: - %{!mn-flash=*:-mn-flash=1} - -*cc1_rmw: - %{mrmw} - -*cc1_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*cc1_absdata: - %{mabsdata} - -*asm_arch: - -mmcu=avr25 - -*asm_relax: - %{mrelax:--mlink-relax} - -*asm_rmw: - %{mrmw} - -*asm_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*link_pmem_wrap: - - -*link_relax: - %{mrelax:--relax} - -*link_arch: - %{mmcu=*:-m%*} - -*link_data_start: - - -*link_text_start: - - -*self_spec: - %{!mmcu=avr*: % -# #elif ... -# -# If no device macro is defined, AVR-LibC uses __AVR_DEV_LIB_NAME__ -# as fallback to determine the name of the device header as -# -# "avr/io" + __AVR_DEV_LIB_NAME__ + ".h" -# -# If you provide your own specs file for a device not yet known to -# AVR-LibC, you can now define the hook macro __AVR_DEV_LIB_NAME__ -# as needed so that -# -# #include -# -# will include the desired device header. For ATmega8A the supplement -# to *cpp would read -# -# -D__AVR_DEV_LIB_NAME__=m8a - - -*cpp: - -D__AVR_ATtiny45__ -D__AVR_DEVICE_NAME__=attiny45 - -# End of file diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-attiny461 b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-attiny461 deleted file mode 100644 index 152d2a4..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-attiny461 +++ /dev/null @@ -1,99 +0,0 @@ -# -# Auto-generated specs for AVR device attiny461 (core avr25, 16-bit SP) -# -# Generated by : ./gcc/config/avr/gen-avr-mmcu-specs.c -# Generated from : ./gcc/config/gcc.c -# ./gcc/config/avr/specs.h -# ./gcc/config/avr/avrlibc.h -# Used by : avr-gcc compiler driver -# Used for : building command options for sub-processes -# -# See -# for a documentation of spec files. - - -# If you intend to use an existing device specs file as a starting point -# for a new device spec file, make sure you are copying from a specs -# file for a device from the same core architecture and SP width. -# See for a description -# of how to use such own spec files. - -*avrlibc_startfile: - crtattiny461.o%s - -*avrlibc_devicelib: - %{!nodevicelib:-lattiny461} - -*cc1_n_flash: - %{!mn-flash=*:-mn-flash=1} - -*cc1_rmw: - %{mrmw} - -*cc1_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*cc1_absdata: - %{mabsdata} - -*asm_arch: - -mmcu=avr25 - -*asm_relax: - %{mrelax:--mlink-relax} - -*asm_rmw: - %{mrmw} - -*asm_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*link_pmem_wrap: - - -*link_relax: - %{mrelax:--relax} - -*link_arch: - %{mmcu=*:-m%*} - -*link_data_start: - - -*link_text_start: - - -*self_spec: - %{!mmcu=avr*: % -# #elif ... -# -# If no device macro is defined, AVR-LibC uses __AVR_DEV_LIB_NAME__ -# as fallback to determine the name of the device header as -# -# "avr/io" + __AVR_DEV_LIB_NAME__ + ".h" -# -# If you provide your own specs file for a device not yet known to -# AVR-LibC, you can now define the hook macro __AVR_DEV_LIB_NAME__ -# as needed so that -# -# #include -# -# will include the desired device header. For ATmega8A the supplement -# to *cpp would read -# -# -D__AVR_DEV_LIB_NAME__=m8a - - -*cpp: - -D__AVR_ATtiny461__ -D__AVR_DEVICE_NAME__=attiny461 - -# End of file diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-attiny461a b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-attiny461a deleted file mode 100644 index 1d2b970..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-attiny461a +++ /dev/null @@ -1,99 +0,0 @@ -# -# Auto-generated specs for AVR device attiny461a (core avr25, 16-bit SP) -# -# Generated by : ./gcc/config/avr/gen-avr-mmcu-specs.c -# Generated from : ./gcc/config/gcc.c -# ./gcc/config/avr/specs.h -# ./gcc/config/avr/avrlibc.h -# Used by : avr-gcc compiler driver -# Used for : building command options for sub-processes -# -# See -# for a documentation of spec files. - - -# If you intend to use an existing device specs file as a starting point -# for a new device spec file, make sure you are copying from a specs -# file for a device from the same core architecture and SP width. -# See for a description -# of how to use such own spec files. - -*avrlibc_startfile: - crtattiny461a.o%s - -*avrlibc_devicelib: - %{!nodevicelib:-lattiny461a} - -*cc1_n_flash: - %{!mn-flash=*:-mn-flash=1} - -*cc1_rmw: - %{mrmw} - -*cc1_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*cc1_absdata: - %{mabsdata} - -*asm_arch: - -mmcu=avr25 - -*asm_relax: - %{mrelax:--mlink-relax} - -*asm_rmw: - %{mrmw} - -*asm_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*link_pmem_wrap: - - -*link_relax: - %{mrelax:--relax} - -*link_arch: - %{mmcu=*:-m%*} - -*link_data_start: - - -*link_text_start: - - -*self_spec: - %{!mmcu=avr*: % -# #elif ... -# -# If no device macro is defined, AVR-LibC uses __AVR_DEV_LIB_NAME__ -# as fallback to determine the name of the device header as -# -# "avr/io" + __AVR_DEV_LIB_NAME__ + ".h" -# -# If you provide your own specs file for a device not yet known to -# AVR-LibC, you can now define the hook macro __AVR_DEV_LIB_NAME__ -# as needed so that -# -# #include -# -# will include the desired device header. For ATmega8A the supplement -# to *cpp would read -# -# -D__AVR_DEV_LIB_NAME__=m8a - - -*cpp: - -D__AVR_ATtiny461A__ -D__AVR_DEVICE_NAME__=attiny461a - -# End of file diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-attiny48 b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-attiny48 deleted file mode 100644 index 886ba69..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-attiny48 +++ /dev/null @@ -1,99 +0,0 @@ -# -# Auto-generated specs for AVR device attiny48 (core avr25, 16-bit SP) -# -# Generated by : ./gcc/config/avr/gen-avr-mmcu-specs.c -# Generated from : ./gcc/config/gcc.c -# ./gcc/config/avr/specs.h -# ./gcc/config/avr/avrlibc.h -# Used by : avr-gcc compiler driver -# Used for : building command options for sub-processes -# -# See -# for a documentation of spec files. - - -# If you intend to use an existing device specs file as a starting point -# for a new device spec file, make sure you are copying from a specs -# file for a device from the same core architecture and SP width. -# See for a description -# of how to use such own spec files. - -*avrlibc_startfile: - crtattiny48.o%s - -*avrlibc_devicelib: - %{!nodevicelib:-lattiny48} - -*cc1_n_flash: - %{!mn-flash=*:-mn-flash=1} - -*cc1_rmw: - %{mrmw} - -*cc1_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*cc1_absdata: - %{mabsdata} - -*asm_arch: - -mmcu=avr25 - -*asm_relax: - %{mrelax:--mlink-relax} - -*asm_rmw: - %{mrmw} - -*asm_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*link_pmem_wrap: - - -*link_relax: - %{mrelax:--relax} - -*link_arch: - %{mmcu=*:-m%*} - -*link_data_start: - -Tdata 0x800100 - -*link_text_start: - - -*self_spec: - %{!mmcu=avr*: % -# #elif ... -# -# If no device macro is defined, AVR-LibC uses __AVR_DEV_LIB_NAME__ -# as fallback to determine the name of the device header as -# -# "avr/io" + __AVR_DEV_LIB_NAME__ + ".h" -# -# If you provide your own specs file for a device not yet known to -# AVR-LibC, you can now define the hook macro __AVR_DEV_LIB_NAME__ -# as needed so that -# -# #include -# -# will include the desired device header. For ATmega8A the supplement -# to *cpp would read -# -# -D__AVR_DEV_LIB_NAME__=m8a - - -*cpp: - -D__AVR_ATtiny48__ -D__AVR_DEVICE_NAME__=attiny48 - -# End of file diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-attiny5 b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-attiny5 deleted file mode 100644 index 1cb76ba..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-attiny5 +++ /dev/null @@ -1,99 +0,0 @@ -# -# Auto-generated specs for AVR device attiny5 (core avrtiny, 16-bit SP) -# -# Generated by : ./gcc/config/avr/gen-avr-mmcu-specs.c -# Generated from : ./gcc/config/gcc.c -# ./gcc/config/avr/specs.h -# ./gcc/config/avr/avrlibc.h -# Used by : avr-gcc compiler driver -# Used for : building command options for sub-processes -# -# See -# for a documentation of spec files. - - -# If you intend to use an existing device specs file as a starting point -# for a new device spec file, make sure you are copying from a specs -# file for a device from the same core architecture and SP width. -# See for a description -# of how to use such own spec files. - -*avrlibc_startfile: - crtattiny5.o%s - -*avrlibc_devicelib: - %{!nodevicelib:-lattiny5} - -*cc1_n_flash: - %{!mn-flash=*:-mn-flash=1} - -*cc1_rmw: - %{mrmw} - -*cc1_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*cc1_absdata: - %{!mno-absdata: -mabsdata} - -*asm_arch: - -mmcu=avrtiny - -*asm_relax: - %{mrelax:--mlink-relax} - -*asm_rmw: - %{mrmw} - -*asm_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*link_pmem_wrap: - - -*link_relax: - %{mrelax:--relax} - -*link_arch: - %{mmcu=*:-m%*} - -*link_data_start: - - -*link_text_start: - - -*self_spec: - %{!mmcu=avr*: % -# #elif ... -# -# If no device macro is defined, AVR-LibC uses __AVR_DEV_LIB_NAME__ -# as fallback to determine the name of the device header as -# -# "avr/io" + __AVR_DEV_LIB_NAME__ + ".h" -# -# If you provide your own specs file for a device not yet known to -# AVR-LibC, you can now define the hook macro __AVR_DEV_LIB_NAME__ -# as needed so that -# -# #include -# -# will include the desired device header. For ATmega8A the supplement -# to *cpp would read -# -# -D__AVR_DEV_LIB_NAME__=m8a - - -*cpp: - -D__AVR_ATtiny5__ -D__AVR_DEVICE_NAME__=attiny5 - -# End of file diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-attiny814 b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-attiny814 deleted file mode 100644 index 82994a6..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-attiny814 +++ /dev/null @@ -1,99 +0,0 @@ -# -# Auto-generated specs for AVR device attiny814 (core avrxmega3, 16-bit SP, short-calls) -# -# Generated by : ./gcc/config/avr/gen-avr-mmcu-specs.c -# Generated from : ./gcc/config/gcc.c -# ./gcc/config/avr/specs.h -# ./gcc/config/avr/avrlibc.h -# Used by : avr-gcc compiler driver -# Used for : building command options for sub-processes -# -# See -# for a documentation of spec files. - - -# If you intend to use an existing device specs file as a starting point -# for a new device spec file, make sure you are copying from a specs -# file for a device from the same core architecture and SP width. -# See for a description -# of how to use such own spec files. - -*avrlibc_startfile: - crtattiny814.o%s - -*avrlibc_devicelib: - %{!nodevicelib:-lattiny814} - -*cc1_n_flash: - %{!mn-flash=*:-mn-flash=1} - -*cc1_rmw: - %{mrmw} - -*cc1_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*cc1_absdata: - %{mabsdata} - -*asm_arch: - -mmcu=avrxmega3 - -*asm_relax: - %{mrelax:--mlink-relax} - -*asm_rmw: - %{mrmw} - -*asm_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*link_pmem_wrap: - %{!mno-pmem-wrap-around: --pmem-wrap-around=8k} - -*link_relax: - %{mrelax:--relax} - -*link_arch: - %{mmcu=*:-m%*} - -*link_data_start: - -Tdata 0x803E00 - -*link_text_start: - - -*self_spec: - %{!mmcu=avr*: % -# #elif ... -# -# If no device macro is defined, AVR-LibC uses __AVR_DEV_LIB_NAME__ -# as fallback to determine the name of the device header as -# -# "avr/io" + __AVR_DEV_LIB_NAME__ + ".h" -# -# If you provide your own specs file for a device not yet known to -# AVR-LibC, you can now define the hook macro __AVR_DEV_LIB_NAME__ -# as needed so that -# -# #include -# -# will include the desired device header. For ATmega8A the supplement -# to *cpp would read -# -# -D__AVR_DEV_LIB_NAME__=m8a - - -*cpp: - -D__AVR_ATtiny814__ -D__AVR_DEVICE_NAME__=attiny814 - -# End of file diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-attiny816 b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-attiny816 deleted file mode 100644 index e56596a..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-attiny816 +++ /dev/null @@ -1,99 +0,0 @@ -# -# Auto-generated specs for AVR device attiny816 (core avrxmega3, 16-bit SP, short-calls) -# -# Generated by : ./gcc/config/avr/gen-avr-mmcu-specs.c -# Generated from : ./gcc/config/gcc.c -# ./gcc/config/avr/specs.h -# ./gcc/config/avr/avrlibc.h -# Used by : avr-gcc compiler driver -# Used for : building command options for sub-processes -# -# See -# for a documentation of spec files. - - -# If you intend to use an existing device specs file as a starting point -# for a new device spec file, make sure you are copying from a specs -# file for a device from the same core architecture and SP width. -# See for a description -# of how to use such own spec files. - -*avrlibc_startfile: - crtattiny816.o%s - -*avrlibc_devicelib: - %{!nodevicelib:-lattiny816} - -*cc1_n_flash: - %{!mn-flash=*:-mn-flash=1} - -*cc1_rmw: - %{mrmw} - -*cc1_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*cc1_absdata: - %{mabsdata} - -*asm_arch: - -mmcu=avrxmega3 - -*asm_relax: - %{mrelax:--mlink-relax} - -*asm_rmw: - %{mrmw} - -*asm_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*link_pmem_wrap: - %{!mno-pmem-wrap-around: --pmem-wrap-around=8k} - -*link_relax: - %{mrelax:--relax} - -*link_arch: - %{mmcu=*:-m%*} - -*link_data_start: - -Tdata 0x803E00 - -*link_text_start: - - -*self_spec: - %{!mmcu=avr*: % -# #elif ... -# -# If no device macro is defined, AVR-LibC uses __AVR_DEV_LIB_NAME__ -# as fallback to determine the name of the device header as -# -# "avr/io" + __AVR_DEV_LIB_NAME__ + ".h" -# -# If you provide your own specs file for a device not yet known to -# AVR-LibC, you can now define the hook macro __AVR_DEV_LIB_NAME__ -# as needed so that -# -# #include -# -# will include the desired device header. For ATmega8A the supplement -# to *cpp would read -# -# -D__AVR_DEV_LIB_NAME__=m8a - - -*cpp: - -D__AVR_ATtiny816__ -D__AVR_DEVICE_NAME__=attiny816 - -# End of file diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-attiny817 b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-attiny817 deleted file mode 100644 index d4dd86f..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-attiny817 +++ /dev/null @@ -1,99 +0,0 @@ -# -# Auto-generated specs for AVR device attiny817 (core avrxmega3, 16-bit SP, short-calls) -# -# Generated by : ./gcc/config/avr/gen-avr-mmcu-specs.c -# Generated from : ./gcc/config/gcc.c -# ./gcc/config/avr/specs.h -# ./gcc/config/avr/avrlibc.h -# Used by : avr-gcc compiler driver -# Used for : building command options for sub-processes -# -# See -# for a documentation of spec files. - - -# If you intend to use an existing device specs file as a starting point -# for a new device spec file, make sure you are copying from a specs -# file for a device from the same core architecture and SP width. -# See for a description -# of how to use such own spec files. - -*avrlibc_startfile: - crtattiny817.o%s - -*avrlibc_devicelib: - %{!nodevicelib:-lattiny817} - -*cc1_n_flash: - %{!mn-flash=*:-mn-flash=1} - -*cc1_rmw: - %{mrmw} - -*cc1_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*cc1_absdata: - %{mabsdata} - -*asm_arch: - -mmcu=avrxmega3 - -*asm_relax: - %{mrelax:--mlink-relax} - -*asm_rmw: - %{mrmw} - -*asm_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*link_pmem_wrap: - %{!mno-pmem-wrap-around: --pmem-wrap-around=8k} - -*link_relax: - %{mrelax:--relax} - -*link_arch: - %{mmcu=*:-m%*} - -*link_data_start: - -Tdata 0x803E00 - -*link_text_start: - - -*self_spec: - %{!mmcu=avr*: % -# #elif ... -# -# If no device macro is defined, AVR-LibC uses __AVR_DEV_LIB_NAME__ -# as fallback to determine the name of the device header as -# -# "avr/io" + __AVR_DEV_LIB_NAME__ + ".h" -# -# If you provide your own specs file for a device not yet known to -# AVR-LibC, you can now define the hook macro __AVR_DEV_LIB_NAME__ -# as needed so that -# -# #include -# -# will include the desired device header. For ATmega8A the supplement -# to *cpp would read -# -# -D__AVR_DEV_LIB_NAME__=m8a - - -*cpp: - -D__AVR_ATtiny817__ -D__AVR_DEVICE_NAME__=attiny817 - -# End of file diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-attiny828 b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-attiny828 deleted file mode 100644 index 91fd503..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-attiny828 +++ /dev/null @@ -1,99 +0,0 @@ -# -# Auto-generated specs for AVR device attiny828 (core avr25, 16-bit SP) -# -# Generated by : ./gcc/config/avr/gen-avr-mmcu-specs.c -# Generated from : ./gcc/config/gcc.c -# ./gcc/config/avr/specs.h -# ./gcc/config/avr/avrlibc.h -# Used by : avr-gcc compiler driver -# Used for : building command options for sub-processes -# -# See -# for a documentation of spec files. - - -# If you intend to use an existing device specs file as a starting point -# for a new device spec file, make sure you are copying from a specs -# file for a device from the same core architecture and SP width. -# See for a description -# of how to use such own spec files. - -*avrlibc_startfile: - crtattiny828.o%s - -*avrlibc_devicelib: - %{!nodevicelib:-lattiny828} - -*cc1_n_flash: - %{!mn-flash=*:-mn-flash=1} - -*cc1_rmw: - %{mrmw} - -*cc1_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*cc1_absdata: - %{mabsdata} - -*asm_arch: - -mmcu=avr25 - -*asm_relax: - %{mrelax:--mlink-relax} - -*asm_rmw: - %{mrmw} - -*asm_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*link_pmem_wrap: - %{!mno-pmem-wrap-around: --pmem-wrap-around=8k} - -*link_relax: - %{mrelax:--relax} - -*link_arch: - %{mmcu=*:-m%*} - -*link_data_start: - -Tdata 0x800100 - -*link_text_start: - - -*self_spec: - %{!mmcu=avr*: % -# #elif ... -# -# If no device macro is defined, AVR-LibC uses __AVR_DEV_LIB_NAME__ -# as fallback to determine the name of the device header as -# -# "avr/io" + __AVR_DEV_LIB_NAME__ + ".h" -# -# If you provide your own specs file for a device not yet known to -# AVR-LibC, you can now define the hook macro __AVR_DEV_LIB_NAME__ -# as needed so that -# -# #include -# -# will include the desired device header. For ATmega8A the supplement -# to *cpp would read -# -# -D__AVR_DEV_LIB_NAME__=m8a - - -*cpp: - -D__AVR_ATtiny828__ -D__AVR_DEVICE_NAME__=attiny828 - -# End of file diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-attiny84 b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-attiny84 deleted file mode 100644 index 572ef71..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-attiny84 +++ /dev/null @@ -1,99 +0,0 @@ -# -# Auto-generated specs for AVR device attiny84 (core avr25, 16-bit SP) -# -# Generated by : ./gcc/config/avr/gen-avr-mmcu-specs.c -# Generated from : ./gcc/config/gcc.c -# ./gcc/config/avr/specs.h -# ./gcc/config/avr/avrlibc.h -# Used by : avr-gcc compiler driver -# Used for : building command options for sub-processes -# -# See -# for a documentation of spec files. - - -# If you intend to use an existing device specs file as a starting point -# for a new device spec file, make sure you are copying from a specs -# file for a device from the same core architecture and SP width. -# See for a description -# of how to use such own spec files. - -*avrlibc_startfile: - crtattiny84.o%s - -*avrlibc_devicelib: - %{!nodevicelib:-lattiny84} - -*cc1_n_flash: - %{!mn-flash=*:-mn-flash=1} - -*cc1_rmw: - %{mrmw} - -*cc1_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*cc1_absdata: - %{mabsdata} - -*asm_arch: - -mmcu=avr25 - -*asm_relax: - %{mrelax:--mlink-relax} - -*asm_rmw: - %{mrmw} - -*asm_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*link_pmem_wrap: - %{!mno-pmem-wrap-around: --pmem-wrap-around=8k} - -*link_relax: - %{mrelax:--relax} - -*link_arch: - %{mmcu=*:-m%*} - -*link_data_start: - - -*link_text_start: - - -*self_spec: - %{!mmcu=avr*: % -# #elif ... -# -# If no device macro is defined, AVR-LibC uses __AVR_DEV_LIB_NAME__ -# as fallback to determine the name of the device header as -# -# "avr/io" + __AVR_DEV_LIB_NAME__ + ".h" -# -# If you provide your own specs file for a device not yet known to -# AVR-LibC, you can now define the hook macro __AVR_DEV_LIB_NAME__ -# as needed so that -# -# #include -# -# will include the desired device header. For ATmega8A the supplement -# to *cpp would read -# -# -D__AVR_DEV_LIB_NAME__=m8a - - -*cpp: - -D__AVR_ATtiny84__ -D__AVR_DEVICE_NAME__=attiny84 - -# End of file diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-attiny841 b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-attiny841 deleted file mode 100644 index 900c3f3..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-attiny841 +++ /dev/null @@ -1,99 +0,0 @@ -# -# Auto-generated specs for AVR device attiny841 (core avr25, 16-bit SP) -# -# Generated by : ./gcc/config/avr/gen-avr-mmcu-specs.c -# Generated from : ./gcc/config/gcc.c -# ./gcc/config/avr/specs.h -# ./gcc/config/avr/avrlibc.h -# Used by : avr-gcc compiler driver -# Used for : building command options for sub-processes -# -# See -# for a documentation of spec files. - - -# If you intend to use an existing device specs file as a starting point -# for a new device spec file, make sure you are copying from a specs -# file for a device from the same core architecture and SP width. -# See for a description -# of how to use such own spec files. - -*avrlibc_startfile: - crtattiny841.o%s - -*avrlibc_devicelib: - %{!nodevicelib:-lattiny841} - -*cc1_n_flash: - %{!mn-flash=*:-mn-flash=1} - -*cc1_rmw: - %{mrmw} - -*cc1_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*cc1_absdata: - %{mabsdata} - -*asm_arch: - -mmcu=avr25 - -*asm_relax: - %{mrelax:--mlink-relax} - -*asm_rmw: - %{mrmw} - -*asm_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*link_pmem_wrap: - %{!mno-pmem-wrap-around: --pmem-wrap-around=8k} - -*link_relax: - %{mrelax:--relax} - -*link_arch: - %{mmcu=*:-m%*} - -*link_data_start: - -Tdata 0x800100 - -*link_text_start: - - -*self_spec: - %{!mmcu=avr*: % -# #elif ... -# -# If no device macro is defined, AVR-LibC uses __AVR_DEV_LIB_NAME__ -# as fallback to determine the name of the device header as -# -# "avr/io" + __AVR_DEV_LIB_NAME__ + ".h" -# -# If you provide your own specs file for a device not yet known to -# AVR-LibC, you can now define the hook macro __AVR_DEV_LIB_NAME__ -# as needed so that -# -# #include -# -# will include the desired device header. For ATmega8A the supplement -# to *cpp would read -# -# -D__AVR_DEV_LIB_NAME__=m8a - - -*cpp: - -D__AVR_ATtiny841__ -D__AVR_DEVICE_NAME__=attiny841 - -# End of file diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-attiny84a b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-attiny84a deleted file mode 100644 index a72c59f..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-attiny84a +++ /dev/null @@ -1,99 +0,0 @@ -# -# Auto-generated specs for AVR device attiny84a (core avr25, 16-bit SP) -# -# Generated by : ./gcc/config/avr/gen-avr-mmcu-specs.c -# Generated from : ./gcc/config/gcc.c -# ./gcc/config/avr/specs.h -# ./gcc/config/avr/avrlibc.h -# Used by : avr-gcc compiler driver -# Used for : building command options for sub-processes -# -# See -# for a documentation of spec files. - - -# If you intend to use an existing device specs file as a starting point -# for a new device spec file, make sure you are copying from a specs -# file for a device from the same core architecture and SP width. -# See for a description -# of how to use such own spec files. - -*avrlibc_startfile: - crtattiny84a.o%s - -*avrlibc_devicelib: - %{!nodevicelib:-lattiny84a} - -*cc1_n_flash: - %{!mn-flash=*:-mn-flash=1} - -*cc1_rmw: - %{mrmw} - -*cc1_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*cc1_absdata: - %{mabsdata} - -*asm_arch: - -mmcu=avr25 - -*asm_relax: - %{mrelax:--mlink-relax} - -*asm_rmw: - %{mrmw} - -*asm_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*link_pmem_wrap: - %{!mno-pmem-wrap-around: --pmem-wrap-around=8k} - -*link_relax: - %{mrelax:--relax} - -*link_arch: - %{mmcu=*:-m%*} - -*link_data_start: - - -*link_text_start: - - -*self_spec: - %{!mmcu=avr*: % -# #elif ... -# -# If no device macro is defined, AVR-LibC uses __AVR_DEV_LIB_NAME__ -# as fallback to determine the name of the device header as -# -# "avr/io" + __AVR_DEV_LIB_NAME__ + ".h" -# -# If you provide your own specs file for a device not yet known to -# AVR-LibC, you can now define the hook macro __AVR_DEV_LIB_NAME__ -# as needed so that -# -# #include -# -# will include the desired device header. For ATmega8A the supplement -# to *cpp would read -# -# -D__AVR_DEV_LIB_NAME__=m8a - - -*cpp: - -D__AVR_ATtiny84A__ -D__AVR_DEVICE_NAME__=attiny84a - -# End of file diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-attiny85 b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-attiny85 deleted file mode 100644 index 3a1d2c9..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-attiny85 +++ /dev/null @@ -1,99 +0,0 @@ -# -# Auto-generated specs for AVR device attiny85 (core avr25, 16-bit SP) -# -# Generated by : ./gcc/config/avr/gen-avr-mmcu-specs.c -# Generated from : ./gcc/config/gcc.c -# ./gcc/config/avr/specs.h -# ./gcc/config/avr/avrlibc.h -# Used by : avr-gcc compiler driver -# Used for : building command options for sub-processes -# -# See -# for a documentation of spec files. - - -# If you intend to use an existing device specs file as a starting point -# for a new device spec file, make sure you are copying from a specs -# file for a device from the same core architecture and SP width. -# See for a description -# of how to use such own spec files. - -*avrlibc_startfile: - crtattiny85.o%s - -*avrlibc_devicelib: - %{!nodevicelib:-lattiny85} - -*cc1_n_flash: - %{!mn-flash=*:-mn-flash=1} - -*cc1_rmw: - %{mrmw} - -*cc1_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*cc1_absdata: - %{mabsdata} - -*asm_arch: - -mmcu=avr25 - -*asm_relax: - %{mrelax:--mlink-relax} - -*asm_rmw: - %{mrmw} - -*asm_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*link_pmem_wrap: - %{!mno-pmem-wrap-around: --pmem-wrap-around=8k} - -*link_relax: - %{mrelax:--relax} - -*link_arch: - %{mmcu=*:-m%*} - -*link_data_start: - - -*link_text_start: - - -*self_spec: - %{!mmcu=avr*: % -# #elif ... -# -# If no device macro is defined, AVR-LibC uses __AVR_DEV_LIB_NAME__ -# as fallback to determine the name of the device header as -# -# "avr/io" + __AVR_DEV_LIB_NAME__ + ".h" -# -# If you provide your own specs file for a device not yet known to -# AVR-LibC, you can now define the hook macro __AVR_DEV_LIB_NAME__ -# as needed so that -# -# #include -# -# will include the desired device header. For ATmega8A the supplement -# to *cpp would read -# -# -D__AVR_DEV_LIB_NAME__=m8a - - -*cpp: - -D__AVR_ATtiny85__ -D__AVR_DEVICE_NAME__=attiny85 - -# End of file diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-attiny861 b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-attiny861 deleted file mode 100644 index 29b0a3c..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-attiny861 +++ /dev/null @@ -1,99 +0,0 @@ -# -# Auto-generated specs for AVR device attiny861 (core avr25, 16-bit SP) -# -# Generated by : ./gcc/config/avr/gen-avr-mmcu-specs.c -# Generated from : ./gcc/config/gcc.c -# ./gcc/config/avr/specs.h -# ./gcc/config/avr/avrlibc.h -# Used by : avr-gcc compiler driver -# Used for : building command options for sub-processes -# -# See -# for a documentation of spec files. - - -# If you intend to use an existing device specs file as a starting point -# for a new device spec file, make sure you are copying from a specs -# file for a device from the same core architecture and SP width. -# See for a description -# of how to use such own spec files. - -*avrlibc_startfile: - crtattiny861.o%s - -*avrlibc_devicelib: - %{!nodevicelib:-lattiny861} - -*cc1_n_flash: - %{!mn-flash=*:-mn-flash=1} - -*cc1_rmw: - %{mrmw} - -*cc1_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*cc1_absdata: - %{mabsdata} - -*asm_arch: - -mmcu=avr25 - -*asm_relax: - %{mrelax:--mlink-relax} - -*asm_rmw: - %{mrmw} - -*asm_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*link_pmem_wrap: - %{!mno-pmem-wrap-around: --pmem-wrap-around=8k} - -*link_relax: - %{mrelax:--relax} - -*link_arch: - %{mmcu=*:-m%*} - -*link_data_start: - - -*link_text_start: - - -*self_spec: - %{!mmcu=avr*: % -# #elif ... -# -# If no device macro is defined, AVR-LibC uses __AVR_DEV_LIB_NAME__ -# as fallback to determine the name of the device header as -# -# "avr/io" + __AVR_DEV_LIB_NAME__ + ".h" -# -# If you provide your own specs file for a device not yet known to -# AVR-LibC, you can now define the hook macro __AVR_DEV_LIB_NAME__ -# as needed so that -# -# #include -# -# will include the desired device header. For ATmega8A the supplement -# to *cpp would read -# -# -D__AVR_DEV_LIB_NAME__=m8a - - -*cpp: - -D__AVR_ATtiny861__ -D__AVR_DEVICE_NAME__=attiny861 - -# End of file diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-attiny861a b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-attiny861a deleted file mode 100644 index 7f91e35..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-attiny861a +++ /dev/null @@ -1,99 +0,0 @@ -# -# Auto-generated specs for AVR device attiny861a (core avr25, 16-bit SP) -# -# Generated by : ./gcc/config/avr/gen-avr-mmcu-specs.c -# Generated from : ./gcc/config/gcc.c -# ./gcc/config/avr/specs.h -# ./gcc/config/avr/avrlibc.h -# Used by : avr-gcc compiler driver -# Used for : building command options for sub-processes -# -# See -# for a documentation of spec files. - - -# If you intend to use an existing device specs file as a starting point -# for a new device spec file, make sure you are copying from a specs -# file for a device from the same core architecture and SP width. -# See for a description -# of how to use such own spec files. - -*avrlibc_startfile: - crtattiny861a.o%s - -*avrlibc_devicelib: - %{!nodevicelib:-lattiny861a} - -*cc1_n_flash: - %{!mn-flash=*:-mn-flash=1} - -*cc1_rmw: - %{mrmw} - -*cc1_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*cc1_absdata: - %{mabsdata} - -*asm_arch: - -mmcu=avr25 - -*asm_relax: - %{mrelax:--mlink-relax} - -*asm_rmw: - %{mrmw} - -*asm_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*link_pmem_wrap: - %{!mno-pmem-wrap-around: --pmem-wrap-around=8k} - -*link_relax: - %{mrelax:--relax} - -*link_arch: - %{mmcu=*:-m%*} - -*link_data_start: - - -*link_text_start: - - -*self_spec: - %{!mmcu=avr*: % -# #elif ... -# -# If no device macro is defined, AVR-LibC uses __AVR_DEV_LIB_NAME__ -# as fallback to determine the name of the device header as -# -# "avr/io" + __AVR_DEV_LIB_NAME__ + ".h" -# -# If you provide your own specs file for a device not yet known to -# AVR-LibC, you can now define the hook macro __AVR_DEV_LIB_NAME__ -# as needed so that -# -# #include -# -# will include the desired device header. For ATmega8A the supplement -# to *cpp would read -# -# -D__AVR_DEV_LIB_NAME__=m8a - - -*cpp: - -D__AVR_ATtiny861A__ -D__AVR_DEVICE_NAME__=attiny861a - -# End of file diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-attiny87 b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-attiny87 deleted file mode 100644 index da73ba6..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-attiny87 +++ /dev/null @@ -1,99 +0,0 @@ -# -# Auto-generated specs for AVR device attiny87 (core avr25, 16-bit SP) -# -# Generated by : ./gcc/config/avr/gen-avr-mmcu-specs.c -# Generated from : ./gcc/config/gcc.c -# ./gcc/config/avr/specs.h -# ./gcc/config/avr/avrlibc.h -# Used by : avr-gcc compiler driver -# Used for : building command options for sub-processes -# -# See -# for a documentation of spec files. - - -# If you intend to use an existing device specs file as a starting point -# for a new device spec file, make sure you are copying from a specs -# file for a device from the same core architecture and SP width. -# See for a description -# of how to use such own spec files. - -*avrlibc_startfile: - crtattiny87.o%s - -*avrlibc_devicelib: - %{!nodevicelib:-lattiny87} - -*cc1_n_flash: - %{!mn-flash=*:-mn-flash=1} - -*cc1_rmw: - %{mrmw} - -*cc1_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*cc1_absdata: - %{mabsdata} - -*asm_arch: - -mmcu=avr25 - -*asm_relax: - %{mrelax:--mlink-relax} - -*asm_rmw: - %{mrmw} - -*asm_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*link_pmem_wrap: - %{!mno-pmem-wrap-around: --pmem-wrap-around=8k} - -*link_relax: - %{mrelax:--relax} - -*link_arch: - %{mmcu=*:-m%*} - -*link_data_start: - -Tdata 0x800100 - -*link_text_start: - - -*self_spec: - %{!mmcu=avr*: % -# #elif ... -# -# If no device macro is defined, AVR-LibC uses __AVR_DEV_LIB_NAME__ -# as fallback to determine the name of the device header as -# -# "avr/io" + __AVR_DEV_LIB_NAME__ + ".h" -# -# If you provide your own specs file for a device not yet known to -# AVR-LibC, you can now define the hook macro __AVR_DEV_LIB_NAME__ -# as needed so that -# -# #include -# -# will include the desired device header. For ATmega8A the supplement -# to *cpp would read -# -# -D__AVR_DEV_LIB_NAME__=m8a - - -*cpp: - -D__AVR_ATtiny87__ -D__AVR_DEVICE_NAME__=attiny87 - -# End of file diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-attiny88 b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-attiny88 deleted file mode 100644 index 47343ac..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-attiny88 +++ /dev/null @@ -1,99 +0,0 @@ -# -# Auto-generated specs for AVR device attiny88 (core avr25, 16-bit SP) -# -# Generated by : ./gcc/config/avr/gen-avr-mmcu-specs.c -# Generated from : ./gcc/config/gcc.c -# ./gcc/config/avr/specs.h -# ./gcc/config/avr/avrlibc.h -# Used by : avr-gcc compiler driver -# Used for : building command options for sub-processes -# -# See -# for a documentation of spec files. - - -# If you intend to use an existing device specs file as a starting point -# for a new device spec file, make sure you are copying from a specs -# file for a device from the same core architecture and SP width. -# See for a description -# of how to use such own spec files. - -*avrlibc_startfile: - crtattiny88.o%s - -*avrlibc_devicelib: - %{!nodevicelib:-lattiny88} - -*cc1_n_flash: - %{!mn-flash=*:-mn-flash=1} - -*cc1_rmw: - %{mrmw} - -*cc1_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*cc1_absdata: - %{mabsdata} - -*asm_arch: - -mmcu=avr25 - -*asm_relax: - %{mrelax:--mlink-relax} - -*asm_rmw: - %{mrmw} - -*asm_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*link_pmem_wrap: - %{!mno-pmem-wrap-around: --pmem-wrap-around=8k} - -*link_relax: - %{mrelax:--relax} - -*link_arch: - %{mmcu=*:-m%*} - -*link_data_start: - -Tdata 0x800100 - -*link_text_start: - - -*self_spec: - %{!mmcu=avr*: % -# #elif ... -# -# If no device macro is defined, AVR-LibC uses __AVR_DEV_LIB_NAME__ -# as fallback to determine the name of the device header as -# -# "avr/io" + __AVR_DEV_LIB_NAME__ + ".h" -# -# If you provide your own specs file for a device not yet known to -# AVR-LibC, you can now define the hook macro __AVR_DEV_LIB_NAME__ -# as needed so that -# -# #include -# -# will include the desired device header. For ATmega8A the supplement -# to *cpp would read -# -# -D__AVR_DEV_LIB_NAME__=m8a - - -*cpp: - -D__AVR_ATtiny88__ -D__AVR_DEVICE_NAME__=attiny88 - -# End of file diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-attiny9 b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-attiny9 deleted file mode 100644 index 41f1bdb..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-attiny9 +++ /dev/null @@ -1,99 +0,0 @@ -# -# Auto-generated specs for AVR device attiny9 (core avrtiny, 16-bit SP) -# -# Generated by : ./gcc/config/avr/gen-avr-mmcu-specs.c -# Generated from : ./gcc/config/gcc.c -# ./gcc/config/avr/specs.h -# ./gcc/config/avr/avrlibc.h -# Used by : avr-gcc compiler driver -# Used for : building command options for sub-processes -# -# See -# for a documentation of spec files. - - -# If you intend to use an existing device specs file as a starting point -# for a new device spec file, make sure you are copying from a specs -# file for a device from the same core architecture and SP width. -# See for a description -# of how to use such own spec files. - -*avrlibc_startfile: - crtattiny9.o%s - -*avrlibc_devicelib: - %{!nodevicelib:-lattiny9} - -*cc1_n_flash: - %{!mn-flash=*:-mn-flash=1} - -*cc1_rmw: - %{mrmw} - -*cc1_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*cc1_absdata: - %{!mno-absdata: -mabsdata} - -*asm_arch: - -mmcu=avrtiny - -*asm_relax: - %{mrelax:--mlink-relax} - -*asm_rmw: - %{mrmw} - -*asm_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*link_pmem_wrap: - - -*link_relax: - %{mrelax:--relax} - -*link_arch: - %{mmcu=*:-m%*} - -*link_data_start: - - -*link_text_start: - - -*self_spec: - %{!mmcu=avr*: % -# #elif ... -# -# If no device macro is defined, AVR-LibC uses __AVR_DEV_LIB_NAME__ -# as fallback to determine the name of the device header as -# -# "avr/io" + __AVR_DEV_LIB_NAME__ + ".h" -# -# If you provide your own specs file for a device not yet known to -# AVR-LibC, you can now define the hook macro __AVR_DEV_LIB_NAME__ -# as needed so that -# -# #include -# -# will include the desired device header. For ATmega8A the supplement -# to *cpp would read -# -# -D__AVR_DEV_LIB_NAME__=m8a - - -*cpp: - -D__AVR_ATtiny9__ -D__AVR_DEVICE_NAME__=attiny9 - -# End of file diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atxmega128a1 b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atxmega128a1 deleted file mode 100644 index d378dd9..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atxmega128a1 +++ /dev/null @@ -1,99 +0,0 @@ -# -# Auto-generated specs for AVR device atxmega128a1 (core avrxmega7, 16-bit SP) -# -# Generated by : ./gcc/config/avr/gen-avr-mmcu-specs.c -# Generated from : ./gcc/config/gcc.c -# ./gcc/config/avr/specs.h -# ./gcc/config/avr/avrlibc.h -# Used by : avr-gcc compiler driver -# Used for : building command options for sub-processes -# -# See -# for a documentation of spec files. - - -# If you intend to use an existing device specs file as a starting point -# for a new device spec file, make sure you are copying from a specs -# file for a device from the same core architecture and SP width. -# See for a description -# of how to use such own spec files. - -*avrlibc_startfile: - crtatxmega128a1.o%s - -*avrlibc_devicelib: - %{!nodevicelib:-latxmega128a1} - -*cc1_n_flash: - %{!mn-flash=*:-mn-flash=3} - -*cc1_rmw: - %{mrmw} - -*cc1_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*cc1_absdata: - %{mabsdata} - -*asm_arch: - -mmcu=avrxmega7 - -*asm_relax: - %{mrelax:--mlink-relax} - -*asm_rmw: - %{mrmw} - -*asm_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*link_pmem_wrap: - - -*link_relax: - %{mrelax:--relax} - -*link_arch: - %{mmcu=*:-m%*} - -*link_data_start: - - -*link_text_start: - - -*self_spec: - %{!mmcu=avr*: % -# #elif ... -# -# If no device macro is defined, AVR-LibC uses __AVR_DEV_LIB_NAME__ -# as fallback to determine the name of the device header as -# -# "avr/io" + __AVR_DEV_LIB_NAME__ + ".h" -# -# If you provide your own specs file for a device not yet known to -# AVR-LibC, you can now define the hook macro __AVR_DEV_LIB_NAME__ -# as needed so that -# -# #include -# -# will include the desired device header. For ATmega8A the supplement -# to *cpp would read -# -# -D__AVR_DEV_LIB_NAME__=m8a - - -*cpp: - -D__AVR_ATxmega128A1__ -D__AVR_DEVICE_NAME__=atxmega128a1 - -# End of file diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atxmega128a1u b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atxmega128a1u deleted file mode 100644 index 05764e6..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atxmega128a1u +++ /dev/null @@ -1,99 +0,0 @@ -# -# Auto-generated specs for AVR device atxmega128a1u (core avrxmega7, 16-bit SP) -# -# Generated by : ./gcc/config/avr/gen-avr-mmcu-specs.c -# Generated from : ./gcc/config/gcc.c -# ./gcc/config/avr/specs.h -# ./gcc/config/avr/avrlibc.h -# Used by : avr-gcc compiler driver -# Used for : building command options for sub-processes -# -# See -# for a documentation of spec files. - - -# If you intend to use an existing device specs file as a starting point -# for a new device spec file, make sure you are copying from a specs -# file for a device from the same core architecture and SP width. -# See for a description -# of how to use such own spec files. - -*avrlibc_startfile: - crtatxmega128a1u.o%s - -*avrlibc_devicelib: - %{!nodevicelib:-latxmega128a1u} - -*cc1_n_flash: - %{!mn-flash=*:-mn-flash=3} - -*cc1_rmw: - %{!mno-rmw: -mrmw} - -*cc1_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*cc1_absdata: - %{mabsdata} - -*asm_arch: - -mmcu=avrxmega7 - -*asm_relax: - %{mrelax:--mlink-relax} - -*asm_rmw: - %{!mno-rmw: -mrmw} - -*asm_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*link_pmem_wrap: - - -*link_relax: - %{mrelax:--relax} - -*link_arch: - %{mmcu=*:-m%*} - -*link_data_start: - - -*link_text_start: - - -*self_spec: - %{!mmcu=avr*: % -# #elif ... -# -# If no device macro is defined, AVR-LibC uses __AVR_DEV_LIB_NAME__ -# as fallback to determine the name of the device header as -# -# "avr/io" + __AVR_DEV_LIB_NAME__ + ".h" -# -# If you provide your own specs file for a device not yet known to -# AVR-LibC, you can now define the hook macro __AVR_DEV_LIB_NAME__ -# as needed so that -# -# #include -# -# will include the desired device header. For ATmega8A the supplement -# to *cpp would read -# -# -D__AVR_DEV_LIB_NAME__=m8a - - -*cpp: - -D__AVR_ATxmega128A1U__ -D__AVR_DEVICE_NAME__=atxmega128a1u - -# End of file diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atxmega128a3 b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atxmega128a3 deleted file mode 100644 index 11ced85..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atxmega128a3 +++ /dev/null @@ -1,99 +0,0 @@ -# -# Auto-generated specs for AVR device atxmega128a3 (core avrxmega6, 16-bit SP) -# -# Generated by : ./gcc/config/avr/gen-avr-mmcu-specs.c -# Generated from : ./gcc/config/gcc.c -# ./gcc/config/avr/specs.h -# ./gcc/config/avr/avrlibc.h -# Used by : avr-gcc compiler driver -# Used for : building command options for sub-processes -# -# See -# for a documentation of spec files. - - -# If you intend to use an existing device specs file as a starting point -# for a new device spec file, make sure you are copying from a specs -# file for a device from the same core architecture and SP width. -# See for a description -# of how to use such own spec files. - -*avrlibc_startfile: - crtatxmega128a3.o%s - -*avrlibc_devicelib: - %{!nodevicelib:-latxmega128a3} - -*cc1_n_flash: - %{!mn-flash=*:-mn-flash=3} - -*cc1_rmw: - %{mrmw} - -*cc1_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*cc1_absdata: - %{mabsdata} - -*asm_arch: - -mmcu=avrxmega6 - -*asm_relax: - %{mrelax:--mlink-relax} - -*asm_rmw: - %{mrmw} - -*asm_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*link_pmem_wrap: - - -*link_relax: - %{mrelax:--relax} - -*link_arch: - %{mmcu=*:-m%*} - -*link_data_start: - - -*link_text_start: - - -*self_spec: - %{!mmcu=avr*: % -# #elif ... -# -# If no device macro is defined, AVR-LibC uses __AVR_DEV_LIB_NAME__ -# as fallback to determine the name of the device header as -# -# "avr/io" + __AVR_DEV_LIB_NAME__ + ".h" -# -# If you provide your own specs file for a device not yet known to -# AVR-LibC, you can now define the hook macro __AVR_DEV_LIB_NAME__ -# as needed so that -# -# #include -# -# will include the desired device header. For ATmega8A the supplement -# to *cpp would read -# -# -D__AVR_DEV_LIB_NAME__=m8a - - -*cpp: - -D__AVR_ATxmega128A3__ -D__AVR_DEVICE_NAME__=atxmega128a3 - -# End of file diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atxmega128a3u b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atxmega128a3u deleted file mode 100644 index 9b4911f..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atxmega128a3u +++ /dev/null @@ -1,99 +0,0 @@ -# -# Auto-generated specs for AVR device atxmega128a3u (core avrxmega6, 16-bit SP) -# -# Generated by : ./gcc/config/avr/gen-avr-mmcu-specs.c -# Generated from : ./gcc/config/gcc.c -# ./gcc/config/avr/specs.h -# ./gcc/config/avr/avrlibc.h -# Used by : avr-gcc compiler driver -# Used for : building command options for sub-processes -# -# See -# for a documentation of spec files. - - -# If you intend to use an existing device specs file as a starting point -# for a new device spec file, make sure you are copying from a specs -# file for a device from the same core architecture and SP width. -# See for a description -# of how to use such own spec files. - -*avrlibc_startfile: - crtatxmega128a3u.o%s - -*avrlibc_devicelib: - %{!nodevicelib:-latxmega128a3u} - -*cc1_n_flash: - %{!mn-flash=*:-mn-flash=3} - -*cc1_rmw: - %{!mno-rmw: -mrmw} - -*cc1_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*cc1_absdata: - %{mabsdata} - -*asm_arch: - -mmcu=avrxmega6 - -*asm_relax: - %{mrelax:--mlink-relax} - -*asm_rmw: - %{!mno-rmw: -mrmw} - -*asm_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*link_pmem_wrap: - - -*link_relax: - %{mrelax:--relax} - -*link_arch: - %{mmcu=*:-m%*} - -*link_data_start: - - -*link_text_start: - - -*self_spec: - %{!mmcu=avr*: % -# #elif ... -# -# If no device macro is defined, AVR-LibC uses __AVR_DEV_LIB_NAME__ -# as fallback to determine the name of the device header as -# -# "avr/io" + __AVR_DEV_LIB_NAME__ + ".h" -# -# If you provide your own specs file for a device not yet known to -# AVR-LibC, you can now define the hook macro __AVR_DEV_LIB_NAME__ -# as needed so that -# -# #include -# -# will include the desired device header. For ATmega8A the supplement -# to *cpp would read -# -# -D__AVR_DEV_LIB_NAME__=m8a - - -*cpp: - -D__AVR_ATxmega128A3U__ -D__AVR_DEVICE_NAME__=atxmega128a3u - -# End of file diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atxmega128a4u b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atxmega128a4u deleted file mode 100644 index 3608d16..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atxmega128a4u +++ /dev/null @@ -1,99 +0,0 @@ -# -# Auto-generated specs for AVR device atxmega128a4u (core avrxmega7, 16-bit SP) -# -# Generated by : ./gcc/config/avr/gen-avr-mmcu-specs.c -# Generated from : ./gcc/config/gcc.c -# ./gcc/config/avr/specs.h -# ./gcc/config/avr/avrlibc.h -# Used by : avr-gcc compiler driver -# Used for : building command options for sub-processes -# -# See -# for a documentation of spec files. - - -# If you intend to use an existing device specs file as a starting point -# for a new device spec file, make sure you are copying from a specs -# file for a device from the same core architecture and SP width. -# See for a description -# of how to use such own spec files. - -*avrlibc_startfile: - crtatxmega128a4u.o%s - -*avrlibc_devicelib: - %{!nodevicelib:-latxmega128a4u} - -*cc1_n_flash: - %{!mn-flash=*:-mn-flash=3} - -*cc1_rmw: - %{!mno-rmw: -mrmw} - -*cc1_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*cc1_absdata: - %{mabsdata} - -*asm_arch: - -mmcu=avrxmega7 - -*asm_relax: - %{mrelax:--mlink-relax} - -*asm_rmw: - %{!mno-rmw: -mrmw} - -*asm_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*link_pmem_wrap: - - -*link_relax: - %{mrelax:--relax} - -*link_arch: - %{mmcu=*:-m%*} - -*link_data_start: - - -*link_text_start: - - -*self_spec: - %{!mmcu=avr*: % -# #elif ... -# -# If no device macro is defined, AVR-LibC uses __AVR_DEV_LIB_NAME__ -# as fallback to determine the name of the device header as -# -# "avr/io" + __AVR_DEV_LIB_NAME__ + ".h" -# -# If you provide your own specs file for a device not yet known to -# AVR-LibC, you can now define the hook macro __AVR_DEV_LIB_NAME__ -# as needed so that -# -# #include -# -# will include the desired device header. For ATmega8A the supplement -# to *cpp would read -# -# -D__AVR_DEV_LIB_NAME__=m8a - - -*cpp: - -D__AVR_ATxmega128A4U__ -D__AVR_DEVICE_NAME__=atxmega128a4u - -# End of file diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atxmega128b1 b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atxmega128b1 deleted file mode 100644 index 4302024..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atxmega128b1 +++ /dev/null @@ -1,99 +0,0 @@ -# -# Auto-generated specs for AVR device atxmega128b1 (core avrxmega6, 16-bit SP) -# -# Generated by : ./gcc/config/avr/gen-avr-mmcu-specs.c -# Generated from : ./gcc/config/gcc.c -# ./gcc/config/avr/specs.h -# ./gcc/config/avr/avrlibc.h -# Used by : avr-gcc compiler driver -# Used for : building command options for sub-processes -# -# See -# for a documentation of spec files. - - -# If you intend to use an existing device specs file as a starting point -# for a new device spec file, make sure you are copying from a specs -# file for a device from the same core architecture and SP width. -# See for a description -# of how to use such own spec files. - -*avrlibc_startfile: - crtatxmega128b1.o%s - -*avrlibc_devicelib: - %{!nodevicelib:-latxmega128b1} - -*cc1_n_flash: - %{!mn-flash=*:-mn-flash=3} - -*cc1_rmw: - %{!mno-rmw: -mrmw} - -*cc1_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*cc1_absdata: - %{mabsdata} - -*asm_arch: - -mmcu=avrxmega6 - -*asm_relax: - %{mrelax:--mlink-relax} - -*asm_rmw: - %{!mno-rmw: -mrmw} - -*asm_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*link_pmem_wrap: - - -*link_relax: - %{mrelax:--relax} - -*link_arch: - %{mmcu=*:-m%*} - -*link_data_start: - - -*link_text_start: - - -*self_spec: - %{!mmcu=avr*: % -# #elif ... -# -# If no device macro is defined, AVR-LibC uses __AVR_DEV_LIB_NAME__ -# as fallback to determine the name of the device header as -# -# "avr/io" + __AVR_DEV_LIB_NAME__ + ".h" -# -# If you provide your own specs file for a device not yet known to -# AVR-LibC, you can now define the hook macro __AVR_DEV_LIB_NAME__ -# as needed so that -# -# #include -# -# will include the desired device header. For ATmega8A the supplement -# to *cpp would read -# -# -D__AVR_DEV_LIB_NAME__=m8a - - -*cpp: - -D__AVR_ATxmega128B1__ -D__AVR_DEVICE_NAME__=atxmega128b1 - -# End of file diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atxmega128b3 b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atxmega128b3 deleted file mode 100644 index ac97488..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atxmega128b3 +++ /dev/null @@ -1,99 +0,0 @@ -# -# Auto-generated specs for AVR device atxmega128b3 (core avrxmega6, 16-bit SP) -# -# Generated by : ./gcc/config/avr/gen-avr-mmcu-specs.c -# Generated from : ./gcc/config/gcc.c -# ./gcc/config/avr/specs.h -# ./gcc/config/avr/avrlibc.h -# Used by : avr-gcc compiler driver -# Used for : building command options for sub-processes -# -# See -# for a documentation of spec files. - - -# If you intend to use an existing device specs file as a starting point -# for a new device spec file, make sure you are copying from a specs -# file for a device from the same core architecture and SP width. -# See for a description -# of how to use such own spec files. - -*avrlibc_startfile: - crtatxmega128b3.o%s - -*avrlibc_devicelib: - %{!nodevicelib:-latxmega128b3} - -*cc1_n_flash: - %{!mn-flash=*:-mn-flash=3} - -*cc1_rmw: - %{!mno-rmw: -mrmw} - -*cc1_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*cc1_absdata: - %{mabsdata} - -*asm_arch: - -mmcu=avrxmega6 - -*asm_relax: - %{mrelax:--mlink-relax} - -*asm_rmw: - %{!mno-rmw: -mrmw} - -*asm_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*link_pmem_wrap: - - -*link_relax: - %{mrelax:--relax} - -*link_arch: - %{mmcu=*:-m%*} - -*link_data_start: - - -*link_text_start: - - -*self_spec: - %{!mmcu=avr*: % -# #elif ... -# -# If no device macro is defined, AVR-LibC uses __AVR_DEV_LIB_NAME__ -# as fallback to determine the name of the device header as -# -# "avr/io" + __AVR_DEV_LIB_NAME__ + ".h" -# -# If you provide your own specs file for a device not yet known to -# AVR-LibC, you can now define the hook macro __AVR_DEV_LIB_NAME__ -# as needed so that -# -# #include -# -# will include the desired device header. For ATmega8A the supplement -# to *cpp would read -# -# -D__AVR_DEV_LIB_NAME__=m8a - - -*cpp: - -D__AVR_ATxmega128B3__ -D__AVR_DEVICE_NAME__=atxmega128b3 - -# End of file diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atxmega128c3 b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atxmega128c3 deleted file mode 100644 index 1b6a5db..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atxmega128c3 +++ /dev/null @@ -1,99 +0,0 @@ -# -# Auto-generated specs for AVR device atxmega128c3 (core avrxmega6, 16-bit SP) -# -# Generated by : ./gcc/config/avr/gen-avr-mmcu-specs.c -# Generated from : ./gcc/config/gcc.c -# ./gcc/config/avr/specs.h -# ./gcc/config/avr/avrlibc.h -# Used by : avr-gcc compiler driver -# Used for : building command options for sub-processes -# -# See -# for a documentation of spec files. - - -# If you intend to use an existing device specs file as a starting point -# for a new device spec file, make sure you are copying from a specs -# file for a device from the same core architecture and SP width. -# See for a description -# of how to use such own spec files. - -*avrlibc_startfile: - crtatxmega128c3.o%s - -*avrlibc_devicelib: - %{!nodevicelib:-latxmega128c3} - -*cc1_n_flash: - %{!mn-flash=*:-mn-flash=3} - -*cc1_rmw: - %{!mno-rmw: -mrmw} - -*cc1_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*cc1_absdata: - %{mabsdata} - -*asm_arch: - -mmcu=avrxmega6 - -*asm_relax: - %{mrelax:--mlink-relax} - -*asm_rmw: - %{!mno-rmw: -mrmw} - -*asm_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*link_pmem_wrap: - - -*link_relax: - %{mrelax:--relax} - -*link_arch: - %{mmcu=*:-m%*} - -*link_data_start: - - -*link_text_start: - - -*self_spec: - %{!mmcu=avr*: % -# #elif ... -# -# If no device macro is defined, AVR-LibC uses __AVR_DEV_LIB_NAME__ -# as fallback to determine the name of the device header as -# -# "avr/io" + __AVR_DEV_LIB_NAME__ + ".h" -# -# If you provide your own specs file for a device not yet known to -# AVR-LibC, you can now define the hook macro __AVR_DEV_LIB_NAME__ -# as needed so that -# -# #include -# -# will include the desired device header. For ATmega8A the supplement -# to *cpp would read -# -# -D__AVR_DEV_LIB_NAME__=m8a - - -*cpp: - -D__AVR_ATxmega128C3__ -D__AVR_DEVICE_NAME__=atxmega128c3 - -# End of file diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atxmega128d3 b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atxmega128d3 deleted file mode 100644 index 45ae3bb..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atxmega128d3 +++ /dev/null @@ -1,99 +0,0 @@ -# -# Auto-generated specs for AVR device atxmega128d3 (core avrxmega6, 16-bit SP) -# -# Generated by : ./gcc/config/avr/gen-avr-mmcu-specs.c -# Generated from : ./gcc/config/gcc.c -# ./gcc/config/avr/specs.h -# ./gcc/config/avr/avrlibc.h -# Used by : avr-gcc compiler driver -# Used for : building command options for sub-processes -# -# See -# for a documentation of spec files. - - -# If you intend to use an existing device specs file as a starting point -# for a new device spec file, make sure you are copying from a specs -# file for a device from the same core architecture and SP width. -# See for a description -# of how to use such own spec files. - -*avrlibc_startfile: - crtatxmega128d3.o%s - -*avrlibc_devicelib: - %{!nodevicelib:-latxmega128d3} - -*cc1_n_flash: - %{!mn-flash=*:-mn-flash=3} - -*cc1_rmw: - %{mrmw} - -*cc1_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*cc1_absdata: - %{mabsdata} - -*asm_arch: - -mmcu=avrxmega6 - -*asm_relax: - %{mrelax:--mlink-relax} - -*asm_rmw: - %{mrmw} - -*asm_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*link_pmem_wrap: - - -*link_relax: - %{mrelax:--relax} - -*link_arch: - %{mmcu=*:-m%*} - -*link_data_start: - - -*link_text_start: - - -*self_spec: - %{!mmcu=avr*: % -# #elif ... -# -# If no device macro is defined, AVR-LibC uses __AVR_DEV_LIB_NAME__ -# as fallback to determine the name of the device header as -# -# "avr/io" + __AVR_DEV_LIB_NAME__ + ".h" -# -# If you provide your own specs file for a device not yet known to -# AVR-LibC, you can now define the hook macro __AVR_DEV_LIB_NAME__ -# as needed so that -# -# #include -# -# will include the desired device header. For ATmega8A the supplement -# to *cpp would read -# -# -D__AVR_DEV_LIB_NAME__=m8a - - -*cpp: - -D__AVR_ATxmega128D3__ -D__AVR_DEVICE_NAME__=atxmega128d3 - -# End of file diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atxmega128d4 b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atxmega128d4 deleted file mode 100644 index df0e0f9..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atxmega128d4 +++ /dev/null @@ -1,99 +0,0 @@ -# -# Auto-generated specs for AVR device atxmega128d4 (core avrxmega6, 16-bit SP) -# -# Generated by : ./gcc/config/avr/gen-avr-mmcu-specs.c -# Generated from : ./gcc/config/gcc.c -# ./gcc/config/avr/specs.h -# ./gcc/config/avr/avrlibc.h -# Used by : avr-gcc compiler driver -# Used for : building command options for sub-processes -# -# See -# for a documentation of spec files. - - -# If you intend to use an existing device specs file as a starting point -# for a new device spec file, make sure you are copying from a specs -# file for a device from the same core architecture and SP width. -# See for a description -# of how to use such own spec files. - -*avrlibc_startfile: - crtatxmega128d4.o%s - -*avrlibc_devicelib: - %{!nodevicelib:-latxmega128d4} - -*cc1_n_flash: - %{!mn-flash=*:-mn-flash=3} - -*cc1_rmw: - %{mrmw} - -*cc1_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*cc1_absdata: - %{mabsdata} - -*asm_arch: - -mmcu=avrxmega6 - -*asm_relax: - %{mrelax:--mlink-relax} - -*asm_rmw: - %{mrmw} - -*asm_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*link_pmem_wrap: - - -*link_relax: - %{mrelax:--relax} - -*link_arch: - %{mmcu=*:-m%*} - -*link_data_start: - - -*link_text_start: - - -*self_spec: - %{!mmcu=avr*: % -# #elif ... -# -# If no device macro is defined, AVR-LibC uses __AVR_DEV_LIB_NAME__ -# as fallback to determine the name of the device header as -# -# "avr/io" + __AVR_DEV_LIB_NAME__ + ".h" -# -# If you provide your own specs file for a device not yet known to -# AVR-LibC, you can now define the hook macro __AVR_DEV_LIB_NAME__ -# as needed so that -# -# #include -# -# will include the desired device header. For ATmega8A the supplement -# to *cpp would read -# -# -D__AVR_DEV_LIB_NAME__=m8a - - -*cpp: - -D__AVR_ATxmega128D4__ -D__AVR_DEVICE_NAME__=atxmega128d4 - -# End of file diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atxmega16a4 b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atxmega16a4 deleted file mode 100644 index 472791b..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atxmega16a4 +++ /dev/null @@ -1,99 +0,0 @@ -# -# Auto-generated specs for AVR device atxmega16a4 (core avrxmega2, 16-bit SP) -# -# Generated by : ./gcc/config/avr/gen-avr-mmcu-specs.c -# Generated from : ./gcc/config/gcc.c -# ./gcc/config/avr/specs.h -# ./gcc/config/avr/avrlibc.h -# Used by : avr-gcc compiler driver -# Used for : building command options for sub-processes -# -# See -# for a documentation of spec files. - - -# If you intend to use an existing device specs file as a starting point -# for a new device spec file, make sure you are copying from a specs -# file for a device from the same core architecture and SP width. -# See for a description -# of how to use such own spec files. - -*avrlibc_startfile: - crtatxmega16a4.o%s - -*avrlibc_devicelib: - %{!nodevicelib:-latxmega16a4} - -*cc1_n_flash: - %{!mn-flash=*:-mn-flash=1} - -*cc1_rmw: - %{mrmw} - -*cc1_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*cc1_absdata: - %{mabsdata} - -*asm_arch: - -mmcu=avrxmega2 - -*asm_relax: - %{mrelax:--mlink-relax} - -*asm_rmw: - %{mrmw} - -*asm_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*link_pmem_wrap: - - -*link_relax: - %{mrelax:--relax} - -*link_arch: - %{mmcu=*:-m%*} - -*link_data_start: - - -*link_text_start: - - -*self_spec: - %{!mmcu=avr*: % -# #elif ... -# -# If no device macro is defined, AVR-LibC uses __AVR_DEV_LIB_NAME__ -# as fallback to determine the name of the device header as -# -# "avr/io" + __AVR_DEV_LIB_NAME__ + ".h" -# -# If you provide your own specs file for a device not yet known to -# AVR-LibC, you can now define the hook macro __AVR_DEV_LIB_NAME__ -# as needed so that -# -# #include -# -# will include the desired device header. For ATmega8A the supplement -# to *cpp would read -# -# -D__AVR_DEV_LIB_NAME__=m8a - - -*cpp: - -D__AVR_ATxmega16A4__ -D__AVR_DEVICE_NAME__=atxmega16a4 - -# End of file diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atxmega16a4u b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atxmega16a4u deleted file mode 100644 index 5321f5f..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atxmega16a4u +++ /dev/null @@ -1,99 +0,0 @@ -# -# Auto-generated specs for AVR device atxmega16a4u (core avrxmega2, 16-bit SP) -# -# Generated by : ./gcc/config/avr/gen-avr-mmcu-specs.c -# Generated from : ./gcc/config/gcc.c -# ./gcc/config/avr/specs.h -# ./gcc/config/avr/avrlibc.h -# Used by : avr-gcc compiler driver -# Used for : building command options for sub-processes -# -# See -# for a documentation of spec files. - - -# If you intend to use an existing device specs file as a starting point -# for a new device spec file, make sure you are copying from a specs -# file for a device from the same core architecture and SP width. -# See for a description -# of how to use such own spec files. - -*avrlibc_startfile: - crtatxmega16a4u.o%s - -*avrlibc_devicelib: - %{!nodevicelib:-latxmega16a4u} - -*cc1_n_flash: - %{!mn-flash=*:-mn-flash=1} - -*cc1_rmw: - %{!mno-rmw: -mrmw} - -*cc1_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*cc1_absdata: - %{mabsdata} - -*asm_arch: - -mmcu=avrxmega2 - -*asm_relax: - %{mrelax:--mlink-relax} - -*asm_rmw: - %{!mno-rmw: -mrmw} - -*asm_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*link_pmem_wrap: - - -*link_relax: - %{mrelax:--relax} - -*link_arch: - %{mmcu=*:-m%*} - -*link_data_start: - - -*link_text_start: - - -*self_spec: - %{!mmcu=avr*: % -# #elif ... -# -# If no device macro is defined, AVR-LibC uses __AVR_DEV_LIB_NAME__ -# as fallback to determine the name of the device header as -# -# "avr/io" + __AVR_DEV_LIB_NAME__ + ".h" -# -# If you provide your own specs file for a device not yet known to -# AVR-LibC, you can now define the hook macro __AVR_DEV_LIB_NAME__ -# as needed so that -# -# #include -# -# will include the desired device header. For ATmega8A the supplement -# to *cpp would read -# -# -D__AVR_DEV_LIB_NAME__=m8a - - -*cpp: - -D__AVR_ATxmega16A4U__ -D__AVR_DEVICE_NAME__=atxmega16a4u - -# End of file diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atxmega16c4 b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atxmega16c4 deleted file mode 100644 index 69ce950..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atxmega16c4 +++ /dev/null @@ -1,99 +0,0 @@ -# -# Auto-generated specs for AVR device atxmega16c4 (core avrxmega2, 16-bit SP) -# -# Generated by : ./gcc/config/avr/gen-avr-mmcu-specs.c -# Generated from : ./gcc/config/gcc.c -# ./gcc/config/avr/specs.h -# ./gcc/config/avr/avrlibc.h -# Used by : avr-gcc compiler driver -# Used for : building command options for sub-processes -# -# See -# for a documentation of spec files. - - -# If you intend to use an existing device specs file as a starting point -# for a new device spec file, make sure you are copying from a specs -# file for a device from the same core architecture and SP width. -# See for a description -# of how to use such own spec files. - -*avrlibc_startfile: - crtatxmega16c4.o%s - -*avrlibc_devicelib: - %{!nodevicelib:-latxmega16c4} - -*cc1_n_flash: - %{!mn-flash=*:-mn-flash=1} - -*cc1_rmw: - %{!mno-rmw: -mrmw} - -*cc1_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*cc1_absdata: - %{mabsdata} - -*asm_arch: - -mmcu=avrxmega2 - -*asm_relax: - %{mrelax:--mlink-relax} - -*asm_rmw: - %{!mno-rmw: -mrmw} - -*asm_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*link_pmem_wrap: - - -*link_relax: - %{mrelax:--relax} - -*link_arch: - %{mmcu=*:-m%*} - -*link_data_start: - - -*link_text_start: - - -*self_spec: - %{!mmcu=avr*: % -# #elif ... -# -# If no device macro is defined, AVR-LibC uses __AVR_DEV_LIB_NAME__ -# as fallback to determine the name of the device header as -# -# "avr/io" + __AVR_DEV_LIB_NAME__ + ".h" -# -# If you provide your own specs file for a device not yet known to -# AVR-LibC, you can now define the hook macro __AVR_DEV_LIB_NAME__ -# as needed so that -# -# #include -# -# will include the desired device header. For ATmega8A the supplement -# to *cpp would read -# -# -D__AVR_DEV_LIB_NAME__=m8a - - -*cpp: - -D__AVR_ATxmega16C4__ -D__AVR_DEVICE_NAME__=atxmega16c4 - -# End of file diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atxmega16d4 b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atxmega16d4 deleted file mode 100644 index fcfaebc..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atxmega16d4 +++ /dev/null @@ -1,99 +0,0 @@ -# -# Auto-generated specs for AVR device atxmega16d4 (core avrxmega2, 16-bit SP) -# -# Generated by : ./gcc/config/avr/gen-avr-mmcu-specs.c -# Generated from : ./gcc/config/gcc.c -# ./gcc/config/avr/specs.h -# ./gcc/config/avr/avrlibc.h -# Used by : avr-gcc compiler driver -# Used for : building command options for sub-processes -# -# See -# for a documentation of spec files. - - -# If you intend to use an existing device specs file as a starting point -# for a new device spec file, make sure you are copying from a specs -# file for a device from the same core architecture and SP width. -# See for a description -# of how to use such own spec files. - -*avrlibc_startfile: - crtatxmega16d4.o%s - -*avrlibc_devicelib: - %{!nodevicelib:-latxmega16d4} - -*cc1_n_flash: - %{!mn-flash=*:-mn-flash=1} - -*cc1_rmw: - %{mrmw} - -*cc1_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*cc1_absdata: - %{mabsdata} - -*asm_arch: - -mmcu=avrxmega2 - -*asm_relax: - %{mrelax:--mlink-relax} - -*asm_rmw: - %{mrmw} - -*asm_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*link_pmem_wrap: - - -*link_relax: - %{mrelax:--relax} - -*link_arch: - %{mmcu=*:-m%*} - -*link_data_start: - - -*link_text_start: - - -*self_spec: - %{!mmcu=avr*: % -# #elif ... -# -# If no device macro is defined, AVR-LibC uses __AVR_DEV_LIB_NAME__ -# as fallback to determine the name of the device header as -# -# "avr/io" + __AVR_DEV_LIB_NAME__ + ".h" -# -# If you provide your own specs file for a device not yet known to -# AVR-LibC, you can now define the hook macro __AVR_DEV_LIB_NAME__ -# as needed so that -# -# #include -# -# will include the desired device header. For ATmega8A the supplement -# to *cpp would read -# -# -D__AVR_DEV_LIB_NAME__=m8a - - -*cpp: - -D__AVR_ATxmega16D4__ -D__AVR_DEVICE_NAME__=atxmega16d4 - -# End of file diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atxmega16e5 b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atxmega16e5 deleted file mode 100644 index 1985804..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atxmega16e5 +++ /dev/null @@ -1,99 +0,0 @@ -# -# Auto-generated specs for AVR device atxmega16e5 (core avrxmega2, 16-bit SP) -# -# Generated by : ./gcc/config/avr/gen-avr-mmcu-specs.c -# Generated from : ./gcc/config/gcc.c -# ./gcc/config/avr/specs.h -# ./gcc/config/avr/avrlibc.h -# Used by : avr-gcc compiler driver -# Used for : building command options for sub-processes -# -# See -# for a documentation of spec files. - - -# If you intend to use an existing device specs file as a starting point -# for a new device spec file, make sure you are copying from a specs -# file for a device from the same core architecture and SP width. -# See for a description -# of how to use such own spec files. - -*avrlibc_startfile: - crtatxmega16e5.o%s - -*avrlibc_devicelib: - %{!nodevicelib:-latxmega16e5} - -*cc1_n_flash: - %{!mn-flash=*:-mn-flash=1} - -*cc1_rmw: - %{mrmw} - -*cc1_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*cc1_absdata: - %{mabsdata} - -*asm_arch: - -mmcu=avrxmega2 - -*asm_relax: - %{mrelax:--mlink-relax} - -*asm_rmw: - %{mrmw} - -*asm_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*link_pmem_wrap: - - -*link_relax: - %{mrelax:--relax} - -*link_arch: - %{mmcu=*:-m%*} - -*link_data_start: - - -*link_text_start: - - -*self_spec: - %{!mmcu=avr*: % -# #elif ... -# -# If no device macro is defined, AVR-LibC uses __AVR_DEV_LIB_NAME__ -# as fallback to determine the name of the device header as -# -# "avr/io" + __AVR_DEV_LIB_NAME__ + ".h" -# -# If you provide your own specs file for a device not yet known to -# AVR-LibC, you can now define the hook macro __AVR_DEV_LIB_NAME__ -# as needed so that -# -# #include -# -# will include the desired device header. For ATmega8A the supplement -# to *cpp would read -# -# -D__AVR_DEV_LIB_NAME__=m8a - - -*cpp: - -D__AVR_ATxmega16E5__ -D__AVR_DEVICE_NAME__=atxmega16e5 - -# End of file diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atxmega192a3 b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atxmega192a3 deleted file mode 100644 index d55277a..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atxmega192a3 +++ /dev/null @@ -1,99 +0,0 @@ -# -# Auto-generated specs for AVR device atxmega192a3 (core avrxmega6, 16-bit SP) -# -# Generated by : ./gcc/config/avr/gen-avr-mmcu-specs.c -# Generated from : ./gcc/config/gcc.c -# ./gcc/config/avr/specs.h -# ./gcc/config/avr/avrlibc.h -# Used by : avr-gcc compiler driver -# Used for : building command options for sub-processes -# -# See -# for a documentation of spec files. - - -# If you intend to use an existing device specs file as a starting point -# for a new device spec file, make sure you are copying from a specs -# file for a device from the same core architecture and SP width. -# See for a description -# of how to use such own spec files. - -*avrlibc_startfile: - crtatxmega192a3.o%s - -*avrlibc_devicelib: - %{!nodevicelib:-latxmega192a3} - -*cc1_n_flash: - %{!mn-flash=*:-mn-flash=4} - -*cc1_rmw: - %{mrmw} - -*cc1_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*cc1_absdata: - %{mabsdata} - -*asm_arch: - -mmcu=avrxmega6 - -*asm_relax: - %{mrelax:--mlink-relax} - -*asm_rmw: - %{mrmw} - -*asm_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*link_pmem_wrap: - - -*link_relax: - %{mrelax:--relax} - -*link_arch: - %{mmcu=*:-m%*} - -*link_data_start: - - -*link_text_start: - - -*self_spec: - %{!mmcu=avr*: % -# #elif ... -# -# If no device macro is defined, AVR-LibC uses __AVR_DEV_LIB_NAME__ -# as fallback to determine the name of the device header as -# -# "avr/io" + __AVR_DEV_LIB_NAME__ + ".h" -# -# If you provide your own specs file for a device not yet known to -# AVR-LibC, you can now define the hook macro __AVR_DEV_LIB_NAME__ -# as needed so that -# -# #include -# -# will include the desired device header. For ATmega8A the supplement -# to *cpp would read -# -# -D__AVR_DEV_LIB_NAME__=m8a - - -*cpp: - -D__AVR_ATxmega192A3__ -D__AVR_DEVICE_NAME__=atxmega192a3 - -# End of file diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atxmega192a3u b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atxmega192a3u deleted file mode 100644 index 9c758f4..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atxmega192a3u +++ /dev/null @@ -1,99 +0,0 @@ -# -# Auto-generated specs for AVR device atxmega192a3u (core avrxmega6, 16-bit SP) -# -# Generated by : ./gcc/config/avr/gen-avr-mmcu-specs.c -# Generated from : ./gcc/config/gcc.c -# ./gcc/config/avr/specs.h -# ./gcc/config/avr/avrlibc.h -# Used by : avr-gcc compiler driver -# Used for : building command options for sub-processes -# -# See -# for a documentation of spec files. - - -# If you intend to use an existing device specs file as a starting point -# for a new device spec file, make sure you are copying from a specs -# file for a device from the same core architecture and SP width. -# See for a description -# of how to use such own spec files. - -*avrlibc_startfile: - crtatxmega192a3u.o%s - -*avrlibc_devicelib: - %{!nodevicelib:-latxmega192a3u} - -*cc1_n_flash: - %{!mn-flash=*:-mn-flash=4} - -*cc1_rmw: - %{!mno-rmw: -mrmw} - -*cc1_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*cc1_absdata: - %{mabsdata} - -*asm_arch: - -mmcu=avrxmega6 - -*asm_relax: - %{mrelax:--mlink-relax} - -*asm_rmw: - %{!mno-rmw: -mrmw} - -*asm_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*link_pmem_wrap: - - -*link_relax: - %{mrelax:--relax} - -*link_arch: - %{mmcu=*:-m%*} - -*link_data_start: - - -*link_text_start: - - -*self_spec: - %{!mmcu=avr*: % -# #elif ... -# -# If no device macro is defined, AVR-LibC uses __AVR_DEV_LIB_NAME__ -# as fallback to determine the name of the device header as -# -# "avr/io" + __AVR_DEV_LIB_NAME__ + ".h" -# -# If you provide your own specs file for a device not yet known to -# AVR-LibC, you can now define the hook macro __AVR_DEV_LIB_NAME__ -# as needed so that -# -# #include -# -# will include the desired device header. For ATmega8A the supplement -# to *cpp would read -# -# -D__AVR_DEV_LIB_NAME__=m8a - - -*cpp: - -D__AVR_ATxmega192A3U__ -D__AVR_DEVICE_NAME__=atxmega192a3u - -# End of file diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atxmega192c3 b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atxmega192c3 deleted file mode 100644 index aa2df99..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atxmega192c3 +++ /dev/null @@ -1,99 +0,0 @@ -# -# Auto-generated specs for AVR device atxmega192c3 (core avrxmega6, 16-bit SP) -# -# Generated by : ./gcc/config/avr/gen-avr-mmcu-specs.c -# Generated from : ./gcc/config/gcc.c -# ./gcc/config/avr/specs.h -# ./gcc/config/avr/avrlibc.h -# Used by : avr-gcc compiler driver -# Used for : building command options for sub-processes -# -# See -# for a documentation of spec files. - - -# If you intend to use an existing device specs file as a starting point -# for a new device spec file, make sure you are copying from a specs -# file for a device from the same core architecture and SP width. -# See for a description -# of how to use such own spec files. - -*avrlibc_startfile: - crtatxmega192c3.o%s - -*avrlibc_devicelib: - %{!nodevicelib:-latxmega192c3} - -*cc1_n_flash: - %{!mn-flash=*:-mn-flash=4} - -*cc1_rmw: - %{!mno-rmw: -mrmw} - -*cc1_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*cc1_absdata: - %{mabsdata} - -*asm_arch: - -mmcu=avrxmega6 - -*asm_relax: - %{mrelax:--mlink-relax} - -*asm_rmw: - %{!mno-rmw: -mrmw} - -*asm_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*link_pmem_wrap: - - -*link_relax: - %{mrelax:--relax} - -*link_arch: - %{mmcu=*:-m%*} - -*link_data_start: - - -*link_text_start: - - -*self_spec: - %{!mmcu=avr*: % -# #elif ... -# -# If no device macro is defined, AVR-LibC uses __AVR_DEV_LIB_NAME__ -# as fallback to determine the name of the device header as -# -# "avr/io" + __AVR_DEV_LIB_NAME__ + ".h" -# -# If you provide your own specs file for a device not yet known to -# AVR-LibC, you can now define the hook macro __AVR_DEV_LIB_NAME__ -# as needed so that -# -# #include -# -# will include the desired device header. For ATmega8A the supplement -# to *cpp would read -# -# -D__AVR_DEV_LIB_NAME__=m8a - - -*cpp: - -D__AVR_ATxmega192C3__ -D__AVR_DEVICE_NAME__=atxmega192c3 - -# End of file diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atxmega192d3 b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atxmega192d3 deleted file mode 100644 index 92bb515..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atxmega192d3 +++ /dev/null @@ -1,99 +0,0 @@ -# -# Auto-generated specs for AVR device atxmega192d3 (core avrxmega6, 16-bit SP) -# -# Generated by : ./gcc/config/avr/gen-avr-mmcu-specs.c -# Generated from : ./gcc/config/gcc.c -# ./gcc/config/avr/specs.h -# ./gcc/config/avr/avrlibc.h -# Used by : avr-gcc compiler driver -# Used for : building command options for sub-processes -# -# See -# for a documentation of spec files. - - -# If you intend to use an existing device specs file as a starting point -# for a new device spec file, make sure you are copying from a specs -# file for a device from the same core architecture and SP width. -# See for a description -# of how to use such own spec files. - -*avrlibc_startfile: - crtatxmega192d3.o%s - -*avrlibc_devicelib: - %{!nodevicelib:-latxmega192d3} - -*cc1_n_flash: - %{!mn-flash=*:-mn-flash=4} - -*cc1_rmw: - %{mrmw} - -*cc1_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*cc1_absdata: - %{mabsdata} - -*asm_arch: - -mmcu=avrxmega6 - -*asm_relax: - %{mrelax:--mlink-relax} - -*asm_rmw: - %{mrmw} - -*asm_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*link_pmem_wrap: - - -*link_relax: - %{mrelax:--relax} - -*link_arch: - %{mmcu=*:-m%*} - -*link_data_start: - - -*link_text_start: - - -*self_spec: - %{!mmcu=avr*: % -# #elif ... -# -# If no device macro is defined, AVR-LibC uses __AVR_DEV_LIB_NAME__ -# as fallback to determine the name of the device header as -# -# "avr/io" + __AVR_DEV_LIB_NAME__ + ".h" -# -# If you provide your own specs file for a device not yet known to -# AVR-LibC, you can now define the hook macro __AVR_DEV_LIB_NAME__ -# as needed so that -# -# #include -# -# will include the desired device header. For ATmega8A the supplement -# to *cpp would read -# -# -D__AVR_DEV_LIB_NAME__=m8a - - -*cpp: - -D__AVR_ATxmega192D3__ -D__AVR_DEVICE_NAME__=atxmega192d3 - -# End of file diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atxmega256a3 b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atxmega256a3 deleted file mode 100644 index 683bf53..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atxmega256a3 +++ /dev/null @@ -1,99 +0,0 @@ -# -# Auto-generated specs for AVR device atxmega256a3 (core avrxmega6, 16-bit SP) -# -# Generated by : ./gcc/config/avr/gen-avr-mmcu-specs.c -# Generated from : ./gcc/config/gcc.c -# ./gcc/config/avr/specs.h -# ./gcc/config/avr/avrlibc.h -# Used by : avr-gcc compiler driver -# Used for : building command options for sub-processes -# -# See -# for a documentation of spec files. - - -# If you intend to use an existing device specs file as a starting point -# for a new device spec file, make sure you are copying from a specs -# file for a device from the same core architecture and SP width. -# See for a description -# of how to use such own spec files. - -*avrlibc_startfile: - crtatxmega256a3.o%s - -*avrlibc_devicelib: - %{!nodevicelib:-latxmega256a3} - -*cc1_n_flash: - %{!mn-flash=*:-mn-flash=5} - -*cc1_rmw: - %{mrmw} - -*cc1_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*cc1_absdata: - %{mabsdata} - -*asm_arch: - -mmcu=avrxmega6 - -*asm_relax: - %{mrelax:--mlink-relax} - -*asm_rmw: - %{mrmw} - -*asm_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*link_pmem_wrap: - - -*link_relax: - %{mrelax:--relax} - -*link_arch: - %{mmcu=*:-m%*} - -*link_data_start: - - -*link_text_start: - - -*self_spec: - %{!mmcu=avr*: % -# #elif ... -# -# If no device macro is defined, AVR-LibC uses __AVR_DEV_LIB_NAME__ -# as fallback to determine the name of the device header as -# -# "avr/io" + __AVR_DEV_LIB_NAME__ + ".h" -# -# If you provide your own specs file for a device not yet known to -# AVR-LibC, you can now define the hook macro __AVR_DEV_LIB_NAME__ -# as needed so that -# -# #include -# -# will include the desired device header. For ATmega8A the supplement -# to *cpp would read -# -# -D__AVR_DEV_LIB_NAME__=m8a - - -*cpp: - -D__AVR_ATxmega256A3__ -D__AVR_DEVICE_NAME__=atxmega256a3 - -# End of file diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atxmega256a3b b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atxmega256a3b deleted file mode 100644 index 12d76df..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atxmega256a3b +++ /dev/null @@ -1,99 +0,0 @@ -# -# Auto-generated specs for AVR device atxmega256a3b (core avrxmega6, 16-bit SP) -# -# Generated by : ./gcc/config/avr/gen-avr-mmcu-specs.c -# Generated from : ./gcc/config/gcc.c -# ./gcc/config/avr/specs.h -# ./gcc/config/avr/avrlibc.h -# Used by : avr-gcc compiler driver -# Used for : building command options for sub-processes -# -# See -# for a documentation of spec files. - - -# If you intend to use an existing device specs file as a starting point -# for a new device spec file, make sure you are copying from a specs -# file for a device from the same core architecture and SP width. -# See for a description -# of how to use such own spec files. - -*avrlibc_startfile: - crtatxmega256a3b.o%s - -*avrlibc_devicelib: - %{!nodevicelib:-latxmega256a3b} - -*cc1_n_flash: - %{!mn-flash=*:-mn-flash=5} - -*cc1_rmw: - %{mrmw} - -*cc1_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*cc1_absdata: - %{mabsdata} - -*asm_arch: - -mmcu=avrxmega6 - -*asm_relax: - %{mrelax:--mlink-relax} - -*asm_rmw: - %{mrmw} - -*asm_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*link_pmem_wrap: - - -*link_relax: - %{mrelax:--relax} - -*link_arch: - %{mmcu=*:-m%*} - -*link_data_start: - - -*link_text_start: - - -*self_spec: - %{!mmcu=avr*: % -# #elif ... -# -# If no device macro is defined, AVR-LibC uses __AVR_DEV_LIB_NAME__ -# as fallback to determine the name of the device header as -# -# "avr/io" + __AVR_DEV_LIB_NAME__ + ".h" -# -# If you provide your own specs file for a device not yet known to -# AVR-LibC, you can now define the hook macro __AVR_DEV_LIB_NAME__ -# as needed so that -# -# #include -# -# will include the desired device header. For ATmega8A the supplement -# to *cpp would read -# -# -D__AVR_DEV_LIB_NAME__=m8a - - -*cpp: - -D__AVR_ATxmega256A3B__ -D__AVR_DEVICE_NAME__=atxmega256a3b - -# End of file diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atxmega256a3bu b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atxmega256a3bu deleted file mode 100644 index 51a3679..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atxmega256a3bu +++ /dev/null @@ -1,99 +0,0 @@ -# -# Auto-generated specs for AVR device atxmega256a3bu (core avrxmega6, 16-bit SP) -# -# Generated by : ./gcc/config/avr/gen-avr-mmcu-specs.c -# Generated from : ./gcc/config/gcc.c -# ./gcc/config/avr/specs.h -# ./gcc/config/avr/avrlibc.h -# Used by : avr-gcc compiler driver -# Used for : building command options for sub-processes -# -# See -# for a documentation of spec files. - - -# If you intend to use an existing device specs file as a starting point -# for a new device spec file, make sure you are copying from a specs -# file for a device from the same core architecture and SP width. -# See for a description -# of how to use such own spec files. - -*avrlibc_startfile: - crtatxmega256a3bu.o%s - -*avrlibc_devicelib: - %{!nodevicelib:-latxmega256a3bu} - -*cc1_n_flash: - %{!mn-flash=*:-mn-flash=5} - -*cc1_rmw: - %{mrmw} - -*cc1_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*cc1_absdata: - %{mabsdata} - -*asm_arch: - -mmcu=avrxmega6 - -*asm_relax: - %{mrelax:--mlink-relax} - -*asm_rmw: - %{mrmw} - -*asm_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*link_pmem_wrap: - - -*link_relax: - %{mrelax:--relax} - -*link_arch: - %{mmcu=*:-m%*} - -*link_data_start: - - -*link_text_start: - - -*self_spec: - %{!mmcu=avr*: % -# #elif ... -# -# If no device macro is defined, AVR-LibC uses __AVR_DEV_LIB_NAME__ -# as fallback to determine the name of the device header as -# -# "avr/io" + __AVR_DEV_LIB_NAME__ + ".h" -# -# If you provide your own specs file for a device not yet known to -# AVR-LibC, you can now define the hook macro __AVR_DEV_LIB_NAME__ -# as needed so that -# -# #include -# -# will include the desired device header. For ATmega8A the supplement -# to *cpp would read -# -# -D__AVR_DEV_LIB_NAME__=m8a - - -*cpp: - -D__AVR_ATxmega256A3BU__ -D__AVR_DEVICE_NAME__=atxmega256a3bu - -# End of file diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atxmega256a3u b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atxmega256a3u deleted file mode 100644 index 9a66ec0..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atxmega256a3u +++ /dev/null @@ -1,99 +0,0 @@ -# -# Auto-generated specs for AVR device atxmega256a3u (core avrxmega6, 16-bit SP) -# -# Generated by : ./gcc/config/avr/gen-avr-mmcu-specs.c -# Generated from : ./gcc/config/gcc.c -# ./gcc/config/avr/specs.h -# ./gcc/config/avr/avrlibc.h -# Used by : avr-gcc compiler driver -# Used for : building command options for sub-processes -# -# See -# for a documentation of spec files. - - -# If you intend to use an existing device specs file as a starting point -# for a new device spec file, make sure you are copying from a specs -# file for a device from the same core architecture and SP width. -# See for a description -# of how to use such own spec files. - -*avrlibc_startfile: - crtatxmega256a3u.o%s - -*avrlibc_devicelib: - %{!nodevicelib:-latxmega256a3u} - -*cc1_n_flash: - %{!mn-flash=*:-mn-flash=5} - -*cc1_rmw: - %{!mno-rmw: -mrmw} - -*cc1_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*cc1_absdata: - %{mabsdata} - -*asm_arch: - -mmcu=avrxmega6 - -*asm_relax: - %{mrelax:--mlink-relax} - -*asm_rmw: - %{!mno-rmw: -mrmw} - -*asm_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*link_pmem_wrap: - - -*link_relax: - %{mrelax:--relax} - -*link_arch: - %{mmcu=*:-m%*} - -*link_data_start: - - -*link_text_start: - - -*self_spec: - %{!mmcu=avr*: % -# #elif ... -# -# If no device macro is defined, AVR-LibC uses __AVR_DEV_LIB_NAME__ -# as fallback to determine the name of the device header as -# -# "avr/io" + __AVR_DEV_LIB_NAME__ + ".h" -# -# If you provide your own specs file for a device not yet known to -# AVR-LibC, you can now define the hook macro __AVR_DEV_LIB_NAME__ -# as needed so that -# -# #include -# -# will include the desired device header. For ATmega8A the supplement -# to *cpp would read -# -# -D__AVR_DEV_LIB_NAME__=m8a - - -*cpp: - -D__AVR_ATxmega256A3U__ -D__AVR_DEVICE_NAME__=atxmega256a3u - -# End of file diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atxmega256c3 b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atxmega256c3 deleted file mode 100644 index ea400f8..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atxmega256c3 +++ /dev/null @@ -1,99 +0,0 @@ -# -# Auto-generated specs for AVR device atxmega256c3 (core avrxmega6, 16-bit SP) -# -# Generated by : ./gcc/config/avr/gen-avr-mmcu-specs.c -# Generated from : ./gcc/config/gcc.c -# ./gcc/config/avr/specs.h -# ./gcc/config/avr/avrlibc.h -# Used by : avr-gcc compiler driver -# Used for : building command options for sub-processes -# -# See -# for a documentation of spec files. - - -# If you intend to use an existing device specs file as a starting point -# for a new device spec file, make sure you are copying from a specs -# file for a device from the same core architecture and SP width. -# See for a description -# of how to use such own spec files. - -*avrlibc_startfile: - crtatxmega256c3.o%s - -*avrlibc_devicelib: - %{!nodevicelib:-latxmega256c3} - -*cc1_n_flash: - %{!mn-flash=*:-mn-flash=5} - -*cc1_rmw: - %{!mno-rmw: -mrmw} - -*cc1_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*cc1_absdata: - %{mabsdata} - -*asm_arch: - -mmcu=avrxmega6 - -*asm_relax: - %{mrelax:--mlink-relax} - -*asm_rmw: - %{!mno-rmw: -mrmw} - -*asm_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*link_pmem_wrap: - - -*link_relax: - %{mrelax:--relax} - -*link_arch: - %{mmcu=*:-m%*} - -*link_data_start: - - -*link_text_start: - - -*self_spec: - %{!mmcu=avr*: % -# #elif ... -# -# If no device macro is defined, AVR-LibC uses __AVR_DEV_LIB_NAME__ -# as fallback to determine the name of the device header as -# -# "avr/io" + __AVR_DEV_LIB_NAME__ + ".h" -# -# If you provide your own specs file for a device not yet known to -# AVR-LibC, you can now define the hook macro __AVR_DEV_LIB_NAME__ -# as needed so that -# -# #include -# -# will include the desired device header. For ATmega8A the supplement -# to *cpp would read -# -# -D__AVR_DEV_LIB_NAME__=m8a - - -*cpp: - -D__AVR_ATxmega256C3__ -D__AVR_DEVICE_NAME__=atxmega256c3 - -# End of file diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atxmega256d3 b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atxmega256d3 deleted file mode 100644 index 1424fba..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atxmega256d3 +++ /dev/null @@ -1,99 +0,0 @@ -# -# Auto-generated specs for AVR device atxmega256d3 (core avrxmega6, 16-bit SP) -# -# Generated by : ./gcc/config/avr/gen-avr-mmcu-specs.c -# Generated from : ./gcc/config/gcc.c -# ./gcc/config/avr/specs.h -# ./gcc/config/avr/avrlibc.h -# Used by : avr-gcc compiler driver -# Used for : building command options for sub-processes -# -# See -# for a documentation of spec files. - - -# If you intend to use an existing device specs file as a starting point -# for a new device spec file, make sure you are copying from a specs -# file for a device from the same core architecture and SP width. -# See for a description -# of how to use such own spec files. - -*avrlibc_startfile: - crtatxmega256d3.o%s - -*avrlibc_devicelib: - %{!nodevicelib:-latxmega256d3} - -*cc1_n_flash: - %{!mn-flash=*:-mn-flash=5} - -*cc1_rmw: - %{mrmw} - -*cc1_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*cc1_absdata: - %{mabsdata} - -*asm_arch: - -mmcu=avrxmega6 - -*asm_relax: - %{mrelax:--mlink-relax} - -*asm_rmw: - %{mrmw} - -*asm_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*link_pmem_wrap: - - -*link_relax: - %{mrelax:--relax} - -*link_arch: - %{mmcu=*:-m%*} - -*link_data_start: - - -*link_text_start: - - -*self_spec: - %{!mmcu=avr*: % -# #elif ... -# -# If no device macro is defined, AVR-LibC uses __AVR_DEV_LIB_NAME__ -# as fallback to determine the name of the device header as -# -# "avr/io" + __AVR_DEV_LIB_NAME__ + ".h" -# -# If you provide your own specs file for a device not yet known to -# AVR-LibC, you can now define the hook macro __AVR_DEV_LIB_NAME__ -# as needed so that -# -# #include -# -# will include the desired device header. For ATmega8A the supplement -# to *cpp would read -# -# -D__AVR_DEV_LIB_NAME__=m8a - - -*cpp: - -D__AVR_ATxmega256D3__ -D__AVR_DEVICE_NAME__=atxmega256d3 - -# End of file diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atxmega32a4 b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atxmega32a4 deleted file mode 100644 index 3cae11a..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atxmega32a4 +++ /dev/null @@ -1,99 +0,0 @@ -# -# Auto-generated specs for AVR device atxmega32a4 (core avrxmega2, 16-bit SP) -# -# Generated by : ./gcc/config/avr/gen-avr-mmcu-specs.c -# Generated from : ./gcc/config/gcc.c -# ./gcc/config/avr/specs.h -# ./gcc/config/avr/avrlibc.h -# Used by : avr-gcc compiler driver -# Used for : building command options for sub-processes -# -# See -# for a documentation of spec files. - - -# If you intend to use an existing device specs file as a starting point -# for a new device spec file, make sure you are copying from a specs -# file for a device from the same core architecture and SP width. -# See for a description -# of how to use such own spec files. - -*avrlibc_startfile: - crtatxmega32a4.o%s - -*avrlibc_devicelib: - %{!nodevicelib:-latxmega32a4} - -*cc1_n_flash: - %{!mn-flash=*:-mn-flash=1} - -*cc1_rmw: - %{mrmw} - -*cc1_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*cc1_absdata: - %{mabsdata} - -*asm_arch: - -mmcu=avrxmega2 - -*asm_relax: - %{mrelax:--mlink-relax} - -*asm_rmw: - %{mrmw} - -*asm_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*link_pmem_wrap: - - -*link_relax: - %{mrelax:--relax} - -*link_arch: - %{mmcu=*:-m%*} - -*link_data_start: - - -*link_text_start: - - -*self_spec: - %{!mmcu=avr*: % -# #elif ... -# -# If no device macro is defined, AVR-LibC uses __AVR_DEV_LIB_NAME__ -# as fallback to determine the name of the device header as -# -# "avr/io" + __AVR_DEV_LIB_NAME__ + ".h" -# -# If you provide your own specs file for a device not yet known to -# AVR-LibC, you can now define the hook macro __AVR_DEV_LIB_NAME__ -# as needed so that -# -# #include -# -# will include the desired device header. For ATmega8A the supplement -# to *cpp would read -# -# -D__AVR_DEV_LIB_NAME__=m8a - - -*cpp: - -D__AVR_ATxmega32A4__ -D__AVR_DEVICE_NAME__=atxmega32a4 - -# End of file diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atxmega32a4u b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atxmega32a4u deleted file mode 100644 index 935aaf0..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atxmega32a4u +++ /dev/null @@ -1,99 +0,0 @@ -# -# Auto-generated specs for AVR device atxmega32a4u (core avrxmega2, 16-bit SP) -# -# Generated by : ./gcc/config/avr/gen-avr-mmcu-specs.c -# Generated from : ./gcc/config/gcc.c -# ./gcc/config/avr/specs.h -# ./gcc/config/avr/avrlibc.h -# Used by : avr-gcc compiler driver -# Used for : building command options for sub-processes -# -# See -# for a documentation of spec files. - - -# If you intend to use an existing device specs file as a starting point -# for a new device spec file, make sure you are copying from a specs -# file for a device from the same core architecture and SP width. -# See for a description -# of how to use such own spec files. - -*avrlibc_startfile: - crtatxmega32a4u.o%s - -*avrlibc_devicelib: - %{!nodevicelib:-latxmega32a4u} - -*cc1_n_flash: - %{!mn-flash=*:-mn-flash=1} - -*cc1_rmw: - %{!mno-rmw: -mrmw} - -*cc1_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*cc1_absdata: - %{mabsdata} - -*asm_arch: - -mmcu=avrxmega2 - -*asm_relax: - %{mrelax:--mlink-relax} - -*asm_rmw: - %{!mno-rmw: -mrmw} - -*asm_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*link_pmem_wrap: - - -*link_relax: - %{mrelax:--relax} - -*link_arch: - %{mmcu=*:-m%*} - -*link_data_start: - - -*link_text_start: - - -*self_spec: - %{!mmcu=avr*: % -# #elif ... -# -# If no device macro is defined, AVR-LibC uses __AVR_DEV_LIB_NAME__ -# as fallback to determine the name of the device header as -# -# "avr/io" + __AVR_DEV_LIB_NAME__ + ".h" -# -# If you provide your own specs file for a device not yet known to -# AVR-LibC, you can now define the hook macro __AVR_DEV_LIB_NAME__ -# as needed so that -# -# #include -# -# will include the desired device header. For ATmega8A the supplement -# to *cpp would read -# -# -D__AVR_DEV_LIB_NAME__=m8a - - -*cpp: - -D__AVR_ATxmega32A4U__ -D__AVR_DEVICE_NAME__=atxmega32a4u - -# End of file diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atxmega32c3 b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atxmega32c3 deleted file mode 100644 index 688cae3..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atxmega32c3 +++ /dev/null @@ -1,99 +0,0 @@ -# -# Auto-generated specs for AVR device atxmega32c3 (core avrxmega2, 16-bit SP) -# -# Generated by : ./gcc/config/avr/gen-avr-mmcu-specs.c -# Generated from : ./gcc/config/gcc.c -# ./gcc/config/avr/specs.h -# ./gcc/config/avr/avrlibc.h -# Used by : avr-gcc compiler driver -# Used for : building command options for sub-processes -# -# See -# for a documentation of spec files. - - -# If you intend to use an existing device specs file as a starting point -# for a new device spec file, make sure you are copying from a specs -# file for a device from the same core architecture and SP width. -# See for a description -# of how to use such own spec files. - -*avrlibc_startfile: - crtatxmega32c3.o%s - -*avrlibc_devicelib: - %{!nodevicelib:-latxmega32c3} - -*cc1_n_flash: - %{!mn-flash=*:-mn-flash=1} - -*cc1_rmw: - %{!mno-rmw: -mrmw} - -*cc1_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*cc1_absdata: - %{mabsdata} - -*asm_arch: - -mmcu=avrxmega2 - -*asm_relax: - %{mrelax:--mlink-relax} - -*asm_rmw: - %{!mno-rmw: -mrmw} - -*asm_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*link_pmem_wrap: - - -*link_relax: - %{mrelax:--relax} - -*link_arch: - %{mmcu=*:-m%*} - -*link_data_start: - - -*link_text_start: - - -*self_spec: - %{!mmcu=avr*: % -# #elif ... -# -# If no device macro is defined, AVR-LibC uses __AVR_DEV_LIB_NAME__ -# as fallback to determine the name of the device header as -# -# "avr/io" + __AVR_DEV_LIB_NAME__ + ".h" -# -# If you provide your own specs file for a device not yet known to -# AVR-LibC, you can now define the hook macro __AVR_DEV_LIB_NAME__ -# as needed so that -# -# #include -# -# will include the desired device header. For ATmega8A the supplement -# to *cpp would read -# -# -D__AVR_DEV_LIB_NAME__=m8a - - -*cpp: - -D__AVR_ATxmega32C3__ -D__AVR_DEVICE_NAME__=atxmega32c3 - -# End of file diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atxmega32c4 b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atxmega32c4 deleted file mode 100644 index 486b9f7..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atxmega32c4 +++ /dev/null @@ -1,99 +0,0 @@ -# -# Auto-generated specs for AVR device atxmega32c4 (core avrxmega2, 16-bit SP) -# -# Generated by : ./gcc/config/avr/gen-avr-mmcu-specs.c -# Generated from : ./gcc/config/gcc.c -# ./gcc/config/avr/specs.h -# ./gcc/config/avr/avrlibc.h -# Used by : avr-gcc compiler driver -# Used for : building command options for sub-processes -# -# See -# for a documentation of spec files. - - -# If you intend to use an existing device specs file as a starting point -# for a new device spec file, make sure you are copying from a specs -# file for a device from the same core architecture and SP width. -# See for a description -# of how to use such own spec files. - -*avrlibc_startfile: - crtatxmega32c4.o%s - -*avrlibc_devicelib: - %{!nodevicelib:-latxmega32c4} - -*cc1_n_flash: - %{!mn-flash=*:-mn-flash=1} - -*cc1_rmw: - %{!mno-rmw: -mrmw} - -*cc1_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*cc1_absdata: - %{mabsdata} - -*asm_arch: - -mmcu=avrxmega2 - -*asm_relax: - %{mrelax:--mlink-relax} - -*asm_rmw: - %{!mno-rmw: -mrmw} - -*asm_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*link_pmem_wrap: - - -*link_relax: - %{mrelax:--relax} - -*link_arch: - %{mmcu=*:-m%*} - -*link_data_start: - - -*link_text_start: - - -*self_spec: - %{!mmcu=avr*: % -# #elif ... -# -# If no device macro is defined, AVR-LibC uses __AVR_DEV_LIB_NAME__ -# as fallback to determine the name of the device header as -# -# "avr/io" + __AVR_DEV_LIB_NAME__ + ".h" -# -# If you provide your own specs file for a device not yet known to -# AVR-LibC, you can now define the hook macro __AVR_DEV_LIB_NAME__ -# as needed so that -# -# #include -# -# will include the desired device header. For ATmega8A the supplement -# to *cpp would read -# -# -D__AVR_DEV_LIB_NAME__=m8a - - -*cpp: - -D__AVR_ATxmega32C4__ -D__AVR_DEVICE_NAME__=atxmega32c4 - -# End of file diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atxmega32d3 b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atxmega32d3 deleted file mode 100644 index e2a4ddb..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atxmega32d3 +++ /dev/null @@ -1,99 +0,0 @@ -# -# Auto-generated specs for AVR device atxmega32d3 (core avrxmega2, 16-bit SP) -# -# Generated by : ./gcc/config/avr/gen-avr-mmcu-specs.c -# Generated from : ./gcc/config/gcc.c -# ./gcc/config/avr/specs.h -# ./gcc/config/avr/avrlibc.h -# Used by : avr-gcc compiler driver -# Used for : building command options for sub-processes -# -# See -# for a documentation of spec files. - - -# If you intend to use an existing device specs file as a starting point -# for a new device spec file, make sure you are copying from a specs -# file for a device from the same core architecture and SP width. -# See for a description -# of how to use such own spec files. - -*avrlibc_startfile: - crtatxmega32d3.o%s - -*avrlibc_devicelib: - %{!nodevicelib:-latxmega32d3} - -*cc1_n_flash: - %{!mn-flash=*:-mn-flash=1} - -*cc1_rmw: - %{mrmw} - -*cc1_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*cc1_absdata: - %{mabsdata} - -*asm_arch: - -mmcu=avrxmega2 - -*asm_relax: - %{mrelax:--mlink-relax} - -*asm_rmw: - %{mrmw} - -*asm_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*link_pmem_wrap: - - -*link_relax: - %{mrelax:--relax} - -*link_arch: - %{mmcu=*:-m%*} - -*link_data_start: - - -*link_text_start: - - -*self_spec: - %{!mmcu=avr*: % -# #elif ... -# -# If no device macro is defined, AVR-LibC uses __AVR_DEV_LIB_NAME__ -# as fallback to determine the name of the device header as -# -# "avr/io" + __AVR_DEV_LIB_NAME__ + ".h" -# -# If you provide your own specs file for a device not yet known to -# AVR-LibC, you can now define the hook macro __AVR_DEV_LIB_NAME__ -# as needed so that -# -# #include -# -# will include the desired device header. For ATmega8A the supplement -# to *cpp would read -# -# -D__AVR_DEV_LIB_NAME__=m8a - - -*cpp: - -D__AVR_ATxmega32D3__ -D__AVR_DEVICE_NAME__=atxmega32d3 - -# End of file diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atxmega32d4 b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atxmega32d4 deleted file mode 100644 index ae836b2..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atxmega32d4 +++ /dev/null @@ -1,99 +0,0 @@ -# -# Auto-generated specs for AVR device atxmega32d4 (core avrxmega2, 16-bit SP) -# -# Generated by : ./gcc/config/avr/gen-avr-mmcu-specs.c -# Generated from : ./gcc/config/gcc.c -# ./gcc/config/avr/specs.h -# ./gcc/config/avr/avrlibc.h -# Used by : avr-gcc compiler driver -# Used for : building command options for sub-processes -# -# See -# for a documentation of spec files. - - -# If you intend to use an existing device specs file as a starting point -# for a new device spec file, make sure you are copying from a specs -# file for a device from the same core architecture and SP width. -# See for a description -# of how to use such own spec files. - -*avrlibc_startfile: - crtatxmega32d4.o%s - -*avrlibc_devicelib: - %{!nodevicelib:-latxmega32d4} - -*cc1_n_flash: - %{!mn-flash=*:-mn-flash=1} - -*cc1_rmw: - %{mrmw} - -*cc1_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*cc1_absdata: - %{mabsdata} - -*asm_arch: - -mmcu=avrxmega2 - -*asm_relax: - %{mrelax:--mlink-relax} - -*asm_rmw: - %{mrmw} - -*asm_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*link_pmem_wrap: - - -*link_relax: - %{mrelax:--relax} - -*link_arch: - %{mmcu=*:-m%*} - -*link_data_start: - - -*link_text_start: - - -*self_spec: - %{!mmcu=avr*: % -# #elif ... -# -# If no device macro is defined, AVR-LibC uses __AVR_DEV_LIB_NAME__ -# as fallback to determine the name of the device header as -# -# "avr/io" + __AVR_DEV_LIB_NAME__ + ".h" -# -# If you provide your own specs file for a device not yet known to -# AVR-LibC, you can now define the hook macro __AVR_DEV_LIB_NAME__ -# as needed so that -# -# #include -# -# will include the desired device header. For ATmega8A the supplement -# to *cpp would read -# -# -D__AVR_DEV_LIB_NAME__=m8a - - -*cpp: - -D__AVR_ATxmega32D4__ -D__AVR_DEVICE_NAME__=atxmega32d4 - -# End of file diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atxmega32e5 b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atxmega32e5 deleted file mode 100644 index 42c9d07..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atxmega32e5 +++ /dev/null @@ -1,99 +0,0 @@ -# -# Auto-generated specs for AVR device atxmega32e5 (core avrxmega2, 16-bit SP) -# -# Generated by : ./gcc/config/avr/gen-avr-mmcu-specs.c -# Generated from : ./gcc/config/gcc.c -# ./gcc/config/avr/specs.h -# ./gcc/config/avr/avrlibc.h -# Used by : avr-gcc compiler driver -# Used for : building command options for sub-processes -# -# See -# for a documentation of spec files. - - -# If you intend to use an existing device specs file as a starting point -# for a new device spec file, make sure you are copying from a specs -# file for a device from the same core architecture and SP width. -# See for a description -# of how to use such own spec files. - -*avrlibc_startfile: - crtatxmega32e5.o%s - -*avrlibc_devicelib: - %{!nodevicelib:-latxmega32e5} - -*cc1_n_flash: - %{!mn-flash=*:-mn-flash=1} - -*cc1_rmw: - %{mrmw} - -*cc1_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*cc1_absdata: - %{mabsdata} - -*asm_arch: - -mmcu=avrxmega2 - -*asm_relax: - %{mrelax:--mlink-relax} - -*asm_rmw: - %{mrmw} - -*asm_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*link_pmem_wrap: - - -*link_relax: - %{mrelax:--relax} - -*link_arch: - %{mmcu=*:-m%*} - -*link_data_start: - - -*link_text_start: - - -*self_spec: - %{!mmcu=avr*: % -# #elif ... -# -# If no device macro is defined, AVR-LibC uses __AVR_DEV_LIB_NAME__ -# as fallback to determine the name of the device header as -# -# "avr/io" + __AVR_DEV_LIB_NAME__ + ".h" -# -# If you provide your own specs file for a device not yet known to -# AVR-LibC, you can now define the hook macro __AVR_DEV_LIB_NAME__ -# as needed so that -# -# #include -# -# will include the desired device header. For ATmega8A the supplement -# to *cpp would read -# -# -D__AVR_DEV_LIB_NAME__=m8a - - -*cpp: - -D__AVR_ATxmega32E5__ -D__AVR_DEVICE_NAME__=atxmega32e5 - -# End of file diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atxmega384c3 b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atxmega384c3 deleted file mode 100644 index 48cc8ab..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atxmega384c3 +++ /dev/null @@ -1,99 +0,0 @@ -# -# Auto-generated specs for AVR device atxmega384c3 (core avrxmega6, 16-bit SP) -# -# Generated by : ./gcc/config/avr/gen-avr-mmcu-specs.c -# Generated from : ./gcc/config/gcc.c -# ./gcc/config/avr/specs.h -# ./gcc/config/avr/avrlibc.h -# Used by : avr-gcc compiler driver -# Used for : building command options for sub-processes -# -# See -# for a documentation of spec files. - - -# If you intend to use an existing device specs file as a starting point -# for a new device spec file, make sure you are copying from a specs -# file for a device from the same core architecture and SP width. -# See for a description -# of how to use such own spec files. - -*avrlibc_startfile: - crtatxmega384c3.o%s - -*avrlibc_devicelib: - %{!nodevicelib:-latxmega384c3} - -*cc1_n_flash: - %{!mn-flash=*:-mn-flash=7} - -*cc1_rmw: - %{!mno-rmw: -mrmw} - -*cc1_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*cc1_absdata: - %{mabsdata} - -*asm_arch: - -mmcu=avrxmega6 - -*asm_relax: - %{mrelax:--mlink-relax} - -*asm_rmw: - %{!mno-rmw: -mrmw} - -*asm_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*link_pmem_wrap: - - -*link_relax: - %{mrelax:--relax} - -*link_arch: - %{mmcu=*:-m%*} - -*link_data_start: - - -*link_text_start: - - -*self_spec: - %{!mmcu=avr*: % -# #elif ... -# -# If no device macro is defined, AVR-LibC uses __AVR_DEV_LIB_NAME__ -# as fallback to determine the name of the device header as -# -# "avr/io" + __AVR_DEV_LIB_NAME__ + ".h" -# -# If you provide your own specs file for a device not yet known to -# AVR-LibC, you can now define the hook macro __AVR_DEV_LIB_NAME__ -# as needed so that -# -# #include -# -# will include the desired device header. For ATmega8A the supplement -# to *cpp would read -# -# -D__AVR_DEV_LIB_NAME__=m8a - - -*cpp: - -D__AVR_ATxmega384C3__ -D__AVR_DEVICE_NAME__=atxmega384c3 - -# End of file diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atxmega384d3 b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atxmega384d3 deleted file mode 100644 index 889e768..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atxmega384d3 +++ /dev/null @@ -1,99 +0,0 @@ -# -# Auto-generated specs for AVR device atxmega384d3 (core avrxmega6, 16-bit SP) -# -# Generated by : ./gcc/config/avr/gen-avr-mmcu-specs.c -# Generated from : ./gcc/config/gcc.c -# ./gcc/config/avr/specs.h -# ./gcc/config/avr/avrlibc.h -# Used by : avr-gcc compiler driver -# Used for : building command options for sub-processes -# -# See -# for a documentation of spec files. - - -# If you intend to use an existing device specs file as a starting point -# for a new device spec file, make sure you are copying from a specs -# file for a device from the same core architecture and SP width. -# See for a description -# of how to use such own spec files. - -*avrlibc_startfile: - crtatxmega384d3.o%s - -*avrlibc_devicelib: - %{!nodevicelib:-latxmega384d3} - -*cc1_n_flash: - %{!mn-flash=*:-mn-flash=7} - -*cc1_rmw: - %{mrmw} - -*cc1_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*cc1_absdata: - %{mabsdata} - -*asm_arch: - -mmcu=avrxmega6 - -*asm_relax: - %{mrelax:--mlink-relax} - -*asm_rmw: - %{mrmw} - -*asm_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*link_pmem_wrap: - - -*link_relax: - %{mrelax:--relax} - -*link_arch: - %{mmcu=*:-m%*} - -*link_data_start: - - -*link_text_start: - - -*self_spec: - %{!mmcu=avr*: % -# #elif ... -# -# If no device macro is defined, AVR-LibC uses __AVR_DEV_LIB_NAME__ -# as fallback to determine the name of the device header as -# -# "avr/io" + __AVR_DEV_LIB_NAME__ + ".h" -# -# If you provide your own specs file for a device not yet known to -# AVR-LibC, you can now define the hook macro __AVR_DEV_LIB_NAME__ -# as needed so that -# -# #include -# -# will include the desired device header. For ATmega8A the supplement -# to *cpp would read -# -# -D__AVR_DEV_LIB_NAME__=m8a - - -*cpp: - -D__AVR_ATxmega384D3__ -D__AVR_DEVICE_NAME__=atxmega384d3 - -# End of file diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atxmega64a1 b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atxmega64a1 deleted file mode 100644 index 5baa992..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atxmega64a1 +++ /dev/null @@ -1,99 +0,0 @@ -# -# Auto-generated specs for AVR device atxmega64a1 (core avrxmega5, 16-bit SP) -# -# Generated by : ./gcc/config/avr/gen-avr-mmcu-specs.c -# Generated from : ./gcc/config/gcc.c -# ./gcc/config/avr/specs.h -# ./gcc/config/avr/avrlibc.h -# Used by : avr-gcc compiler driver -# Used for : building command options for sub-processes -# -# See -# for a documentation of spec files. - - -# If you intend to use an existing device specs file as a starting point -# for a new device spec file, make sure you are copying from a specs -# file for a device from the same core architecture and SP width. -# See for a description -# of how to use such own spec files. - -*avrlibc_startfile: - crtatxmega64a1.o%s - -*avrlibc_devicelib: - %{!nodevicelib:-latxmega64a1} - -*cc1_n_flash: - %{!mn-flash=*:-mn-flash=2} - -*cc1_rmw: - %{mrmw} - -*cc1_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*cc1_absdata: - %{mabsdata} - -*asm_arch: - -mmcu=avrxmega5 - -*asm_relax: - %{mrelax:--mlink-relax} - -*asm_rmw: - %{mrmw} - -*asm_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*link_pmem_wrap: - - -*link_relax: - %{mrelax:--relax} - -*link_arch: - %{mmcu=*:-m%*} - -*link_data_start: - - -*link_text_start: - - -*self_spec: - %{!mmcu=avr*: % -# #elif ... -# -# If no device macro is defined, AVR-LibC uses __AVR_DEV_LIB_NAME__ -# as fallback to determine the name of the device header as -# -# "avr/io" + __AVR_DEV_LIB_NAME__ + ".h" -# -# If you provide your own specs file for a device not yet known to -# AVR-LibC, you can now define the hook macro __AVR_DEV_LIB_NAME__ -# as needed so that -# -# #include -# -# will include the desired device header. For ATmega8A the supplement -# to *cpp would read -# -# -D__AVR_DEV_LIB_NAME__=m8a - - -*cpp: - -D__AVR_ATxmega64A1__ -D__AVR_DEVICE_NAME__=atxmega64a1 - -# End of file diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atxmega64a1u b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atxmega64a1u deleted file mode 100644 index 8c79841..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atxmega64a1u +++ /dev/null @@ -1,99 +0,0 @@ -# -# Auto-generated specs for AVR device atxmega64a1u (core avrxmega5, 16-bit SP) -# -# Generated by : ./gcc/config/avr/gen-avr-mmcu-specs.c -# Generated from : ./gcc/config/gcc.c -# ./gcc/config/avr/specs.h -# ./gcc/config/avr/avrlibc.h -# Used by : avr-gcc compiler driver -# Used for : building command options for sub-processes -# -# See -# for a documentation of spec files. - - -# If you intend to use an existing device specs file as a starting point -# for a new device spec file, make sure you are copying from a specs -# file for a device from the same core architecture and SP width. -# See for a description -# of how to use such own spec files. - -*avrlibc_startfile: - crtatxmega64a1u.o%s - -*avrlibc_devicelib: - %{!nodevicelib:-latxmega64a1u} - -*cc1_n_flash: - %{!mn-flash=*:-mn-flash=2} - -*cc1_rmw: - %{!mno-rmw: -mrmw} - -*cc1_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*cc1_absdata: - %{mabsdata} - -*asm_arch: - -mmcu=avrxmega5 - -*asm_relax: - %{mrelax:--mlink-relax} - -*asm_rmw: - %{!mno-rmw: -mrmw} - -*asm_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*link_pmem_wrap: - - -*link_relax: - %{mrelax:--relax} - -*link_arch: - %{mmcu=*:-m%*} - -*link_data_start: - - -*link_text_start: - - -*self_spec: - %{!mmcu=avr*: % -# #elif ... -# -# If no device macro is defined, AVR-LibC uses __AVR_DEV_LIB_NAME__ -# as fallback to determine the name of the device header as -# -# "avr/io" + __AVR_DEV_LIB_NAME__ + ".h" -# -# If you provide your own specs file for a device not yet known to -# AVR-LibC, you can now define the hook macro __AVR_DEV_LIB_NAME__ -# as needed so that -# -# #include -# -# will include the desired device header. For ATmega8A the supplement -# to *cpp would read -# -# -D__AVR_DEV_LIB_NAME__=m8a - - -*cpp: - -D__AVR_ATxmega64A1U__ -D__AVR_DEVICE_NAME__=atxmega64a1u - -# End of file diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atxmega64a3 b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atxmega64a3 deleted file mode 100644 index 6833e8b..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atxmega64a3 +++ /dev/null @@ -1,99 +0,0 @@ -# -# Auto-generated specs for AVR device atxmega64a3 (core avrxmega4, 16-bit SP) -# -# Generated by : ./gcc/config/avr/gen-avr-mmcu-specs.c -# Generated from : ./gcc/config/gcc.c -# ./gcc/config/avr/specs.h -# ./gcc/config/avr/avrlibc.h -# Used by : avr-gcc compiler driver -# Used for : building command options for sub-processes -# -# See -# for a documentation of spec files. - - -# If you intend to use an existing device specs file as a starting point -# for a new device spec file, make sure you are copying from a specs -# file for a device from the same core architecture and SP width. -# See for a description -# of how to use such own spec files. - -*avrlibc_startfile: - crtatxmega64a3.o%s - -*avrlibc_devicelib: - %{!nodevicelib:-latxmega64a3} - -*cc1_n_flash: - %{!mn-flash=*:-mn-flash=2} - -*cc1_rmw: - %{mrmw} - -*cc1_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*cc1_absdata: - %{mabsdata} - -*asm_arch: - -mmcu=avrxmega4 - -*asm_relax: - %{mrelax:--mlink-relax} - -*asm_rmw: - %{mrmw} - -*asm_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*link_pmem_wrap: - - -*link_relax: - %{mrelax:--relax} - -*link_arch: - %{mmcu=*:-m%*} - -*link_data_start: - - -*link_text_start: - - -*self_spec: - %{!mmcu=avr*: % -# #elif ... -# -# If no device macro is defined, AVR-LibC uses __AVR_DEV_LIB_NAME__ -# as fallback to determine the name of the device header as -# -# "avr/io" + __AVR_DEV_LIB_NAME__ + ".h" -# -# If you provide your own specs file for a device not yet known to -# AVR-LibC, you can now define the hook macro __AVR_DEV_LIB_NAME__ -# as needed so that -# -# #include -# -# will include the desired device header. For ATmega8A the supplement -# to *cpp would read -# -# -D__AVR_DEV_LIB_NAME__=m8a - - -*cpp: - -D__AVR_ATxmega64A3__ -D__AVR_DEVICE_NAME__=atxmega64a3 - -# End of file diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atxmega64a3u b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atxmega64a3u deleted file mode 100644 index 8b4149f..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atxmega64a3u +++ /dev/null @@ -1,99 +0,0 @@ -# -# Auto-generated specs for AVR device atxmega64a3u (core avrxmega4, 16-bit SP) -# -# Generated by : ./gcc/config/avr/gen-avr-mmcu-specs.c -# Generated from : ./gcc/config/gcc.c -# ./gcc/config/avr/specs.h -# ./gcc/config/avr/avrlibc.h -# Used by : avr-gcc compiler driver -# Used for : building command options for sub-processes -# -# See -# for a documentation of spec files. - - -# If you intend to use an existing device specs file as a starting point -# for a new device spec file, make sure you are copying from a specs -# file for a device from the same core architecture and SP width. -# See for a description -# of how to use such own spec files. - -*avrlibc_startfile: - crtatxmega64a3u.o%s - -*avrlibc_devicelib: - %{!nodevicelib:-latxmega64a3u} - -*cc1_n_flash: - %{!mn-flash=*:-mn-flash=2} - -*cc1_rmw: - %{!mno-rmw: -mrmw} - -*cc1_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*cc1_absdata: - %{mabsdata} - -*asm_arch: - -mmcu=avrxmega4 - -*asm_relax: - %{mrelax:--mlink-relax} - -*asm_rmw: - %{!mno-rmw: -mrmw} - -*asm_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*link_pmem_wrap: - - -*link_relax: - %{mrelax:--relax} - -*link_arch: - %{mmcu=*:-m%*} - -*link_data_start: - - -*link_text_start: - - -*self_spec: - %{!mmcu=avr*: % -# #elif ... -# -# If no device macro is defined, AVR-LibC uses __AVR_DEV_LIB_NAME__ -# as fallback to determine the name of the device header as -# -# "avr/io" + __AVR_DEV_LIB_NAME__ + ".h" -# -# If you provide your own specs file for a device not yet known to -# AVR-LibC, you can now define the hook macro __AVR_DEV_LIB_NAME__ -# as needed so that -# -# #include -# -# will include the desired device header. For ATmega8A the supplement -# to *cpp would read -# -# -D__AVR_DEV_LIB_NAME__=m8a - - -*cpp: - -D__AVR_ATxmega64A3U__ -D__AVR_DEVICE_NAME__=atxmega64a3u - -# End of file diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atxmega64a4u b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atxmega64a4u deleted file mode 100644 index 91d1984..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atxmega64a4u +++ /dev/null @@ -1,99 +0,0 @@ -# -# Auto-generated specs for AVR device atxmega64a4u (core avrxmega4, 16-bit SP) -# -# Generated by : ./gcc/config/avr/gen-avr-mmcu-specs.c -# Generated from : ./gcc/config/gcc.c -# ./gcc/config/avr/specs.h -# ./gcc/config/avr/avrlibc.h -# Used by : avr-gcc compiler driver -# Used for : building command options for sub-processes -# -# See -# for a documentation of spec files. - - -# If you intend to use an existing device specs file as a starting point -# for a new device spec file, make sure you are copying from a specs -# file for a device from the same core architecture and SP width. -# See for a description -# of how to use such own spec files. - -*avrlibc_startfile: - crtatxmega64a4u.o%s - -*avrlibc_devicelib: - %{!nodevicelib:-latxmega64a4u} - -*cc1_n_flash: - %{!mn-flash=*:-mn-flash=2} - -*cc1_rmw: - %{!mno-rmw: -mrmw} - -*cc1_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*cc1_absdata: - %{mabsdata} - -*asm_arch: - -mmcu=avrxmega4 - -*asm_relax: - %{mrelax:--mlink-relax} - -*asm_rmw: - %{!mno-rmw: -mrmw} - -*asm_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*link_pmem_wrap: - - -*link_relax: - %{mrelax:--relax} - -*link_arch: - %{mmcu=*:-m%*} - -*link_data_start: - - -*link_text_start: - - -*self_spec: - %{!mmcu=avr*: % -# #elif ... -# -# If no device macro is defined, AVR-LibC uses __AVR_DEV_LIB_NAME__ -# as fallback to determine the name of the device header as -# -# "avr/io" + __AVR_DEV_LIB_NAME__ + ".h" -# -# If you provide your own specs file for a device not yet known to -# AVR-LibC, you can now define the hook macro __AVR_DEV_LIB_NAME__ -# as needed so that -# -# #include -# -# will include the desired device header. For ATmega8A the supplement -# to *cpp would read -# -# -D__AVR_DEV_LIB_NAME__=m8a - - -*cpp: - -D__AVR_ATxmega64A4U__ -D__AVR_DEVICE_NAME__=atxmega64a4u - -# End of file diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atxmega64b1 b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atxmega64b1 deleted file mode 100644 index 1c66b99..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atxmega64b1 +++ /dev/null @@ -1,99 +0,0 @@ -# -# Auto-generated specs for AVR device atxmega64b1 (core avrxmega4, 16-bit SP) -# -# Generated by : ./gcc/config/avr/gen-avr-mmcu-specs.c -# Generated from : ./gcc/config/gcc.c -# ./gcc/config/avr/specs.h -# ./gcc/config/avr/avrlibc.h -# Used by : avr-gcc compiler driver -# Used for : building command options for sub-processes -# -# See -# for a documentation of spec files. - - -# If you intend to use an existing device specs file as a starting point -# for a new device spec file, make sure you are copying from a specs -# file for a device from the same core architecture and SP width. -# See for a description -# of how to use such own spec files. - -*avrlibc_startfile: - crtatxmega64b1.o%s - -*avrlibc_devicelib: - %{!nodevicelib:-latxmega64b1} - -*cc1_n_flash: - %{!mn-flash=*:-mn-flash=2} - -*cc1_rmw: - %{!mno-rmw: -mrmw} - -*cc1_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*cc1_absdata: - %{mabsdata} - -*asm_arch: - -mmcu=avrxmega4 - -*asm_relax: - %{mrelax:--mlink-relax} - -*asm_rmw: - %{!mno-rmw: -mrmw} - -*asm_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*link_pmem_wrap: - - -*link_relax: - %{mrelax:--relax} - -*link_arch: - %{mmcu=*:-m%*} - -*link_data_start: - - -*link_text_start: - - -*self_spec: - %{!mmcu=avr*: % -# #elif ... -# -# If no device macro is defined, AVR-LibC uses __AVR_DEV_LIB_NAME__ -# as fallback to determine the name of the device header as -# -# "avr/io" + __AVR_DEV_LIB_NAME__ + ".h" -# -# If you provide your own specs file for a device not yet known to -# AVR-LibC, you can now define the hook macro __AVR_DEV_LIB_NAME__ -# as needed so that -# -# #include -# -# will include the desired device header. For ATmega8A the supplement -# to *cpp would read -# -# -D__AVR_DEV_LIB_NAME__=m8a - - -*cpp: - -D__AVR_ATxmega64B1__ -D__AVR_DEVICE_NAME__=atxmega64b1 - -# End of file diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atxmega64b3 b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atxmega64b3 deleted file mode 100644 index d916e0a..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atxmega64b3 +++ /dev/null @@ -1,99 +0,0 @@ -# -# Auto-generated specs for AVR device atxmega64b3 (core avrxmega4, 16-bit SP) -# -# Generated by : ./gcc/config/avr/gen-avr-mmcu-specs.c -# Generated from : ./gcc/config/gcc.c -# ./gcc/config/avr/specs.h -# ./gcc/config/avr/avrlibc.h -# Used by : avr-gcc compiler driver -# Used for : building command options for sub-processes -# -# See -# for a documentation of spec files. - - -# If you intend to use an existing device specs file as a starting point -# for a new device spec file, make sure you are copying from a specs -# file for a device from the same core architecture and SP width. -# See for a description -# of how to use such own spec files. - -*avrlibc_startfile: - crtatxmega64b3.o%s - -*avrlibc_devicelib: - %{!nodevicelib:-latxmega64b3} - -*cc1_n_flash: - %{!mn-flash=*:-mn-flash=2} - -*cc1_rmw: - %{!mno-rmw: -mrmw} - -*cc1_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*cc1_absdata: - %{mabsdata} - -*asm_arch: - -mmcu=avrxmega4 - -*asm_relax: - %{mrelax:--mlink-relax} - -*asm_rmw: - %{!mno-rmw: -mrmw} - -*asm_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*link_pmem_wrap: - - -*link_relax: - %{mrelax:--relax} - -*link_arch: - %{mmcu=*:-m%*} - -*link_data_start: - - -*link_text_start: - - -*self_spec: - %{!mmcu=avr*: % -# #elif ... -# -# If no device macro is defined, AVR-LibC uses __AVR_DEV_LIB_NAME__ -# as fallback to determine the name of the device header as -# -# "avr/io" + __AVR_DEV_LIB_NAME__ + ".h" -# -# If you provide your own specs file for a device not yet known to -# AVR-LibC, you can now define the hook macro __AVR_DEV_LIB_NAME__ -# as needed so that -# -# #include -# -# will include the desired device header. For ATmega8A the supplement -# to *cpp would read -# -# -D__AVR_DEV_LIB_NAME__=m8a - - -*cpp: - -D__AVR_ATxmega64B3__ -D__AVR_DEVICE_NAME__=atxmega64b3 - -# End of file diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atxmega64c3 b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atxmega64c3 deleted file mode 100644 index a09c83d..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atxmega64c3 +++ /dev/null @@ -1,99 +0,0 @@ -# -# Auto-generated specs for AVR device atxmega64c3 (core avrxmega4, 16-bit SP) -# -# Generated by : ./gcc/config/avr/gen-avr-mmcu-specs.c -# Generated from : ./gcc/config/gcc.c -# ./gcc/config/avr/specs.h -# ./gcc/config/avr/avrlibc.h -# Used by : avr-gcc compiler driver -# Used for : building command options for sub-processes -# -# See -# for a documentation of spec files. - - -# If you intend to use an existing device specs file as a starting point -# for a new device spec file, make sure you are copying from a specs -# file for a device from the same core architecture and SP width. -# See for a description -# of how to use such own spec files. - -*avrlibc_startfile: - crtatxmega64c3.o%s - -*avrlibc_devicelib: - %{!nodevicelib:-latxmega64c3} - -*cc1_n_flash: - %{!mn-flash=*:-mn-flash=2} - -*cc1_rmw: - %{!mno-rmw: -mrmw} - -*cc1_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*cc1_absdata: - %{mabsdata} - -*asm_arch: - -mmcu=avrxmega4 - -*asm_relax: - %{mrelax:--mlink-relax} - -*asm_rmw: - %{!mno-rmw: -mrmw} - -*asm_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*link_pmem_wrap: - - -*link_relax: - %{mrelax:--relax} - -*link_arch: - %{mmcu=*:-m%*} - -*link_data_start: - - -*link_text_start: - - -*self_spec: - %{!mmcu=avr*: % -# #elif ... -# -# If no device macro is defined, AVR-LibC uses __AVR_DEV_LIB_NAME__ -# as fallback to determine the name of the device header as -# -# "avr/io" + __AVR_DEV_LIB_NAME__ + ".h" -# -# If you provide your own specs file for a device not yet known to -# AVR-LibC, you can now define the hook macro __AVR_DEV_LIB_NAME__ -# as needed so that -# -# #include -# -# will include the desired device header. For ATmega8A the supplement -# to *cpp would read -# -# -D__AVR_DEV_LIB_NAME__=m8a - - -*cpp: - -D__AVR_ATxmega64C3__ -D__AVR_DEVICE_NAME__=atxmega64c3 - -# End of file diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atxmega64d3 b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atxmega64d3 deleted file mode 100644 index e95bf8f..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atxmega64d3 +++ /dev/null @@ -1,99 +0,0 @@ -# -# Auto-generated specs for AVR device atxmega64d3 (core avrxmega4, 16-bit SP) -# -# Generated by : ./gcc/config/avr/gen-avr-mmcu-specs.c -# Generated from : ./gcc/config/gcc.c -# ./gcc/config/avr/specs.h -# ./gcc/config/avr/avrlibc.h -# Used by : avr-gcc compiler driver -# Used for : building command options for sub-processes -# -# See -# for a documentation of spec files. - - -# If you intend to use an existing device specs file as a starting point -# for a new device spec file, make sure you are copying from a specs -# file for a device from the same core architecture and SP width. -# See for a description -# of how to use such own spec files. - -*avrlibc_startfile: - crtatxmega64d3.o%s - -*avrlibc_devicelib: - %{!nodevicelib:-latxmega64d3} - -*cc1_n_flash: - %{!mn-flash=*:-mn-flash=2} - -*cc1_rmw: - %{mrmw} - -*cc1_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*cc1_absdata: - %{mabsdata} - -*asm_arch: - -mmcu=avrxmega4 - -*asm_relax: - %{mrelax:--mlink-relax} - -*asm_rmw: - %{mrmw} - -*asm_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*link_pmem_wrap: - - -*link_relax: - %{mrelax:--relax} - -*link_arch: - %{mmcu=*:-m%*} - -*link_data_start: - - -*link_text_start: - - -*self_spec: - %{!mmcu=avr*: % -# #elif ... -# -# If no device macro is defined, AVR-LibC uses __AVR_DEV_LIB_NAME__ -# as fallback to determine the name of the device header as -# -# "avr/io" + __AVR_DEV_LIB_NAME__ + ".h" -# -# If you provide your own specs file for a device not yet known to -# AVR-LibC, you can now define the hook macro __AVR_DEV_LIB_NAME__ -# as needed so that -# -# #include -# -# will include the desired device header. For ATmega8A the supplement -# to *cpp would read -# -# -D__AVR_DEV_LIB_NAME__=m8a - - -*cpp: - -D__AVR_ATxmega64D3__ -D__AVR_DEVICE_NAME__=atxmega64d3 - -# End of file diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atxmega64d4 b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atxmega64d4 deleted file mode 100644 index 9809925..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atxmega64d4 +++ /dev/null @@ -1,99 +0,0 @@ -# -# Auto-generated specs for AVR device atxmega64d4 (core avrxmega4, 16-bit SP) -# -# Generated by : ./gcc/config/avr/gen-avr-mmcu-specs.c -# Generated from : ./gcc/config/gcc.c -# ./gcc/config/avr/specs.h -# ./gcc/config/avr/avrlibc.h -# Used by : avr-gcc compiler driver -# Used for : building command options for sub-processes -# -# See -# for a documentation of spec files. - - -# If you intend to use an existing device specs file as a starting point -# for a new device spec file, make sure you are copying from a specs -# file for a device from the same core architecture and SP width. -# See for a description -# of how to use such own spec files. - -*avrlibc_startfile: - crtatxmega64d4.o%s - -*avrlibc_devicelib: - %{!nodevicelib:-latxmega64d4} - -*cc1_n_flash: - %{!mn-flash=*:-mn-flash=2} - -*cc1_rmw: - %{mrmw} - -*cc1_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*cc1_absdata: - %{mabsdata} - -*asm_arch: - -mmcu=avrxmega4 - -*asm_relax: - %{mrelax:--mlink-relax} - -*asm_rmw: - %{mrmw} - -*asm_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*link_pmem_wrap: - - -*link_relax: - %{mrelax:--relax} - -*link_arch: - %{mmcu=*:-m%*} - -*link_data_start: - - -*link_text_start: - - -*self_spec: - %{!mmcu=avr*: % -# #elif ... -# -# If no device macro is defined, AVR-LibC uses __AVR_DEV_LIB_NAME__ -# as fallback to determine the name of the device header as -# -# "avr/io" + __AVR_DEV_LIB_NAME__ + ".h" -# -# If you provide your own specs file for a device not yet known to -# AVR-LibC, you can now define the hook macro __AVR_DEV_LIB_NAME__ -# as needed so that -# -# #include -# -# will include the desired device header. For ATmega8A the supplement -# to *cpp would read -# -# -D__AVR_DEV_LIB_NAME__=m8a - - -*cpp: - -D__AVR_ATxmega64D4__ -D__AVR_DEVICE_NAME__=atxmega64d4 - -# End of file diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atxmega8e5 b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atxmega8e5 deleted file mode 100644 index 522bc44..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-atxmega8e5 +++ /dev/null @@ -1,99 +0,0 @@ -# -# Auto-generated specs for AVR device atxmega8e5 (core avrxmega2, 16-bit SP) -# -# Generated by : ./gcc/config/avr/gen-avr-mmcu-specs.c -# Generated from : ./gcc/config/gcc.c -# ./gcc/config/avr/specs.h -# ./gcc/config/avr/avrlibc.h -# Used by : avr-gcc compiler driver -# Used for : building command options for sub-processes -# -# See -# for a documentation of spec files. - - -# If you intend to use an existing device specs file as a starting point -# for a new device spec file, make sure you are copying from a specs -# file for a device from the same core architecture and SP width. -# See for a description -# of how to use such own spec files. - -*avrlibc_startfile: - crtatxmega8e5.o%s - -*avrlibc_devicelib: - %{!nodevicelib:-latxmega8e5} - -*cc1_n_flash: - %{!mn-flash=*:-mn-flash=1} - -*cc1_rmw: - %{mrmw} - -*cc1_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*cc1_absdata: - %{mabsdata} - -*asm_arch: - -mmcu=avrxmega2 - -*asm_relax: - %{mrelax:--mlink-relax} - -*asm_rmw: - %{mrmw} - -*asm_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*link_pmem_wrap: - - -*link_relax: - %{mrelax:--relax} - -*link_arch: - %{mmcu=*:-m%*} - -*link_data_start: - - -*link_text_start: - - -*self_spec: - %{!mmcu=avr*: % -# #elif ... -# -# If no device macro is defined, AVR-LibC uses __AVR_DEV_LIB_NAME__ -# as fallback to determine the name of the device header as -# -# "avr/io" + __AVR_DEV_LIB_NAME__ + ".h" -# -# If you provide your own specs file for a device not yet known to -# AVR-LibC, you can now define the hook macro __AVR_DEV_LIB_NAME__ -# as needed so that -# -# #include -# -# will include the desired device header. For ATmega8A the supplement -# to *cpp would read -# -# -D__AVR_DEV_LIB_NAME__=m8a - - -*cpp: - -D__AVR_ATxmega8E5__ -D__AVR_DEVICE_NAME__=atxmega8e5 - -# End of file diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-avr1 b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-avr1 deleted file mode 100644 index 4b2444c..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-avr1 +++ /dev/null @@ -1,48 +0,0 @@ -# -# Auto-generated specs for AVR core architecture avr1 -# -# Generated by : ./gcc/config/avr/gen-avr-mmcu-specs.c -# Generated from : ./gcc/config/gcc.c -# ./gcc/config/avr/specs.h -# ./gcc/config/avr/avrlibc.h -# Used by : avr-gcc compiler driver -# Used for : building command options for sub-processes -# -# See -# for a documentation of spec files. - - -*cc1_n_flash: - %{!mn-flash=*:-mn-flash=1} - -*cc1_rmw: - %{mrmw} - -*cc1_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*cc1_absdata: - %{mabsdata} - -*asm_arch: - -mmcu=avr1 - -*asm_relax: - %{mrelax:--mlink-relax} - -*asm_rmw: - %{mrmw} - -*asm_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*link_pmem_wrap: - - -*link_relax: - %{mrelax:--relax} - -*link_arch: - %{mmcu=*:-m%*} - -# End of file diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-avr2 b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-avr2 deleted file mode 100644 index 1a35671..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-avr2 +++ /dev/null @@ -1,48 +0,0 @@ -# -# Auto-generated specs for AVR core architecture avr2 -# -# Generated by : ./gcc/config/avr/gen-avr-mmcu-specs.c -# Generated from : ./gcc/config/gcc.c -# ./gcc/config/avr/specs.h -# ./gcc/config/avr/avrlibc.h -# Used by : avr-gcc compiler driver -# Used for : building command options for sub-processes -# -# See -# for a documentation of spec files. - - -*cc1_n_flash: - %{!mn-flash=*:-mn-flash=1} - -*cc1_rmw: - %{mrmw} - -*cc1_errata_skip: - %{!mno-skip-bug: -mskip-bug} - -*cc1_absdata: - %{mabsdata} - -*asm_arch: - -mmcu=avr2 - -*asm_relax: - %{mrelax:--mlink-relax} - -*asm_rmw: - %{mrmw} - -*asm_errata_skip: - %{mno-skip-bug} - -*link_pmem_wrap: - %{!mno-pmem-wrap-around: --pmem-wrap-around=8k} - -*link_relax: - %{mrelax:--relax} - -*link_arch: - %{mmcu=*:-m%*} - -# End of file diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-avr25 b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-avr25 deleted file mode 100644 index df1f349..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-avr25 +++ /dev/null @@ -1,48 +0,0 @@ -# -# Auto-generated specs for AVR core architecture avr25 -# -# Generated by : ./gcc/config/avr/gen-avr-mmcu-specs.c -# Generated from : ./gcc/config/gcc.c -# ./gcc/config/avr/specs.h -# ./gcc/config/avr/avrlibc.h -# Used by : avr-gcc compiler driver -# Used for : building command options for sub-processes -# -# See -# for a documentation of spec files. - - -*cc1_n_flash: - %{!mn-flash=*:-mn-flash=1} - -*cc1_rmw: - %{mrmw} - -*cc1_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*cc1_absdata: - %{mabsdata} - -*asm_arch: - -mmcu=avr25 - -*asm_relax: - %{mrelax:--mlink-relax} - -*asm_rmw: - %{mrmw} - -*asm_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*link_pmem_wrap: - %{!mno-pmem-wrap-around: --pmem-wrap-around=8k} - -*link_relax: - %{mrelax:--relax} - -*link_arch: - %{mmcu=*:-m%*} - -# End of file diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-avr3 b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-avr3 deleted file mode 100644 index 8d7ce3c..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-avr3 +++ /dev/null @@ -1,48 +0,0 @@ -# -# Auto-generated specs for AVR core architecture avr3 -# -# Generated by : ./gcc/config/avr/gen-avr-mmcu-specs.c -# Generated from : ./gcc/config/gcc.c -# ./gcc/config/avr/specs.h -# ./gcc/config/avr/avrlibc.h -# Used by : avr-gcc compiler driver -# Used for : building command options for sub-processes -# -# See -# for a documentation of spec files. - - -*cc1_n_flash: - %{!mn-flash=*:-mn-flash=1} - -*cc1_rmw: - %{mrmw} - -*cc1_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*cc1_absdata: - %{mabsdata} - -*asm_arch: - -mmcu=avr3 - -*asm_relax: - %{mrelax:--mlink-relax} - -*asm_rmw: - %{mrmw} - -*asm_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*link_pmem_wrap: - - -*link_relax: - %{mrelax:--relax} - -*link_arch: - %{mmcu=*:-m%*} - -# End of file diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-avr31 b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-avr31 deleted file mode 100644 index 727300a..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-avr31 +++ /dev/null @@ -1,48 +0,0 @@ -# -# Auto-generated specs for AVR core architecture avr31 -# -# Generated by : ./gcc/config/avr/gen-avr-mmcu-specs.c -# Generated from : ./gcc/config/gcc.c -# ./gcc/config/avr/specs.h -# ./gcc/config/avr/avrlibc.h -# Used by : avr-gcc compiler driver -# Used for : building command options for sub-processes -# -# See -# for a documentation of spec files. - - -*cc1_n_flash: - %{!mn-flash=*:-mn-flash=2} - -*cc1_rmw: - %{mrmw} - -*cc1_errata_skip: - %{!mno-skip-bug: -mskip-bug} - -*cc1_absdata: - %{mabsdata} - -*asm_arch: - -mmcu=avr31 - -*asm_relax: - %{mrelax:--mlink-relax} - -*asm_rmw: - %{mrmw} - -*asm_errata_skip: - %{mno-skip-bug} - -*link_pmem_wrap: - - -*link_relax: - %{mrelax:--relax} - -*link_arch: - %{mmcu=*:-m%*} - -# End of file diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-avr35 b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-avr35 deleted file mode 100644 index e455827..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-avr35 +++ /dev/null @@ -1,48 +0,0 @@ -# -# Auto-generated specs for AVR core architecture avr35 -# -# Generated by : ./gcc/config/avr/gen-avr-mmcu-specs.c -# Generated from : ./gcc/config/gcc.c -# ./gcc/config/avr/specs.h -# ./gcc/config/avr/avrlibc.h -# Used by : avr-gcc compiler driver -# Used for : building command options for sub-processes -# -# See -# for a documentation of spec files. - - -*cc1_n_flash: - %{!mn-flash=*:-mn-flash=1} - -*cc1_rmw: - %{mrmw} - -*cc1_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*cc1_absdata: - %{mabsdata} - -*asm_arch: - -mmcu=avr35 - -*asm_relax: - %{mrelax:--mlink-relax} - -*asm_rmw: - %{mrmw} - -*asm_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*link_pmem_wrap: - %{mpmem-wrap-around: --pmem-wrap-around=16k} - -*link_relax: - %{mrelax:--relax} - -*link_arch: - %{mmcu=*:-m%*} - -# End of file diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-avr4 b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-avr4 deleted file mode 100644 index a4745e1..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-avr4 +++ /dev/null @@ -1,48 +0,0 @@ -# -# Auto-generated specs for AVR core architecture avr4 -# -# Generated by : ./gcc/config/avr/gen-avr-mmcu-specs.c -# Generated from : ./gcc/config/gcc.c -# ./gcc/config/avr/specs.h -# ./gcc/config/avr/avrlibc.h -# Used by : avr-gcc compiler driver -# Used for : building command options for sub-processes -# -# See -# for a documentation of spec files. - - -*cc1_n_flash: - %{!mn-flash=*:-mn-flash=1} - -*cc1_rmw: - %{mrmw} - -*cc1_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*cc1_absdata: - %{mabsdata} - -*asm_arch: - -mmcu=avr4 - -*asm_relax: - %{mrelax:--mlink-relax} - -*asm_rmw: - %{mrmw} - -*asm_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*link_pmem_wrap: - %{!mno-pmem-wrap-around: --pmem-wrap-around=8k} - -*link_relax: - %{mrelax:--relax} - -*link_arch: - %{mmcu=*:-m%*} - -# End of file diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-avr5 b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-avr5 deleted file mode 100644 index c1bc6a6..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-avr5 +++ /dev/null @@ -1,48 +0,0 @@ -# -# Auto-generated specs for AVR core architecture avr5 -# -# Generated by : ./gcc/config/avr/gen-avr-mmcu-specs.c -# Generated from : ./gcc/config/gcc.c -# ./gcc/config/avr/specs.h -# ./gcc/config/avr/avrlibc.h -# Used by : avr-gcc compiler driver -# Used for : building command options for sub-processes -# -# See -# for a documentation of spec files. - - -*cc1_n_flash: - %{!mn-flash=*:-mn-flash=1} - -*cc1_rmw: - %{mrmw} - -*cc1_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*cc1_absdata: - %{mabsdata} - -*asm_arch: - -mmcu=avr5 - -*asm_relax: - %{mrelax:--mlink-relax} - -*asm_rmw: - %{mrmw} - -*asm_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*link_pmem_wrap: - %{mpmem-wrap-around: --pmem-wrap-around=16k} - -*link_relax: - %{mrelax:--relax} - -*link_arch: - %{mmcu=*:-m%*} - -# End of file diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-avr51 b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-avr51 deleted file mode 100644 index 08db2d6..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-avr51 +++ /dev/null @@ -1,48 +0,0 @@ -# -# Auto-generated specs for AVR core architecture avr51 -# -# Generated by : ./gcc/config/avr/gen-avr-mmcu-specs.c -# Generated from : ./gcc/config/gcc.c -# ./gcc/config/avr/specs.h -# ./gcc/config/avr/avrlibc.h -# Used by : avr-gcc compiler driver -# Used for : building command options for sub-processes -# -# See -# for a documentation of spec files. - - -*cc1_n_flash: - %{!mn-flash=*:-mn-flash=2} - -*cc1_rmw: - %{mrmw} - -*cc1_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*cc1_absdata: - %{mabsdata} - -*asm_arch: - -mmcu=avr51 - -*asm_relax: - %{mrelax:--mlink-relax} - -*asm_rmw: - %{mrmw} - -*asm_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*link_pmem_wrap: - - -*link_relax: - %{mrelax:--relax} - -*link_arch: - %{mmcu=*:-m%*} - -# End of file diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-avr6 b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-avr6 deleted file mode 100644 index 8a7afb1..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-avr6 +++ /dev/null @@ -1,48 +0,0 @@ -# -# Auto-generated specs for AVR core architecture avr6 -# -# Generated by : ./gcc/config/avr/gen-avr-mmcu-specs.c -# Generated from : ./gcc/config/gcc.c -# ./gcc/config/avr/specs.h -# ./gcc/config/avr/avrlibc.h -# Used by : avr-gcc compiler driver -# Used for : building command options for sub-processes -# -# See -# for a documentation of spec files. - - -*cc1_n_flash: - %{!mn-flash=*:-mn-flash=4} - -*cc1_rmw: - %{mrmw} - -*cc1_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*cc1_absdata: - %{mabsdata} - -*asm_arch: - -mmcu=avr6 - -*asm_relax: - %{mrelax:--mlink-relax} - -*asm_rmw: - %{mrmw} - -*asm_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*link_pmem_wrap: - - -*link_relax: - %{mrelax:--relax} - -*link_arch: - %{mmcu=*:-m%*} - -# End of file diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-avrtiny b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-avrtiny deleted file mode 100644 index 35b387d..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-avrtiny +++ /dev/null @@ -1,48 +0,0 @@ -# -# Auto-generated specs for AVR core architecture avrtiny -# -# Generated by : ./gcc/config/avr/gen-avr-mmcu-specs.c -# Generated from : ./gcc/config/gcc.c -# ./gcc/config/avr/specs.h -# ./gcc/config/avr/avrlibc.h -# Used by : avr-gcc compiler driver -# Used for : building command options for sub-processes -# -# See -# for a documentation of spec files. - - -*cc1_n_flash: - %{!mn-flash=*:-mn-flash=1} - -*cc1_rmw: - %{mrmw} - -*cc1_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*cc1_absdata: - %{mabsdata} - -*asm_arch: - -mmcu=avrtiny - -*asm_relax: - %{mrelax:--mlink-relax} - -*asm_rmw: - %{mrmw} - -*asm_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*link_pmem_wrap: - - -*link_relax: - %{mrelax:--relax} - -*link_arch: - %{mmcu=*:-m%*} - -# End of file diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-avrxmega2 b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-avrxmega2 deleted file mode 100644 index a478e50..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-avrxmega2 +++ /dev/null @@ -1,48 +0,0 @@ -# -# Auto-generated specs for AVR core architecture avrxmega2 -# -# Generated by : ./gcc/config/avr/gen-avr-mmcu-specs.c -# Generated from : ./gcc/config/gcc.c -# ./gcc/config/avr/specs.h -# ./gcc/config/avr/avrlibc.h -# Used by : avr-gcc compiler driver -# Used for : building command options for sub-processes -# -# See -# for a documentation of spec files. - - -*cc1_n_flash: - %{!mn-flash=*:-mn-flash=1} - -*cc1_rmw: - %{mrmw} - -*cc1_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*cc1_absdata: - %{mabsdata} - -*asm_arch: - -mmcu=avrxmega2 - -*asm_relax: - %{mrelax:--mlink-relax} - -*asm_rmw: - %{mrmw} - -*asm_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*link_pmem_wrap: - - -*link_relax: - %{mrelax:--relax} - -*link_arch: - %{mmcu=*:-m%*} - -# End of file diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-avrxmega3 b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-avrxmega3 deleted file mode 100644 index 31a3a1e..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-avrxmega3 +++ /dev/null @@ -1,48 +0,0 @@ -# -# Auto-generated specs for AVR core architecture avrxmega3 -# -# Generated by : ./gcc/config/avr/gen-avr-mmcu-specs.c -# Generated from : ./gcc/config/gcc.c -# ./gcc/config/avr/specs.h -# ./gcc/config/avr/avrlibc.h -# Used by : avr-gcc compiler driver -# Used for : building command options for sub-processes -# -# See -# for a documentation of spec files. - - -*cc1_n_flash: - %{!mn-flash=*:-mn-flash=1} - -*cc1_rmw: - %{mrmw} - -*cc1_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*cc1_absdata: - %{mabsdata} - -*asm_arch: - -mmcu=avrxmega3 - -*asm_relax: - %{mrelax:--mlink-relax} - -*asm_rmw: - %{mrmw} - -*asm_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*link_pmem_wrap: - %{mpmem-wrap-around: --pmem-wrap-around=32k} - -*link_relax: - %{mrelax:--relax} - -*link_arch: - %{mmcu=*:-m%*} - -# End of file diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-avrxmega4 b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-avrxmega4 deleted file mode 100644 index 8415391..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-avrxmega4 +++ /dev/null @@ -1,48 +0,0 @@ -# -# Auto-generated specs for AVR core architecture avrxmega4 -# -# Generated by : ./gcc/config/avr/gen-avr-mmcu-specs.c -# Generated from : ./gcc/config/gcc.c -# ./gcc/config/avr/specs.h -# ./gcc/config/avr/avrlibc.h -# Used by : avr-gcc compiler driver -# Used for : building command options for sub-processes -# -# See -# for a documentation of spec files. - - -*cc1_n_flash: - %{!mn-flash=*:-mn-flash=2} - -*cc1_rmw: - %{mrmw} - -*cc1_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*cc1_absdata: - %{mabsdata} - -*asm_arch: - -mmcu=avrxmega4 - -*asm_relax: - %{mrelax:--mlink-relax} - -*asm_rmw: - %{mrmw} - -*asm_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*link_pmem_wrap: - - -*link_relax: - %{mrelax:--relax} - -*link_arch: - %{mmcu=*:-m%*} - -# End of file diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-avrxmega5 b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-avrxmega5 deleted file mode 100644 index 14c3cd6..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-avrxmega5 +++ /dev/null @@ -1,48 +0,0 @@ -# -# Auto-generated specs for AVR core architecture avrxmega5 -# -# Generated by : ./gcc/config/avr/gen-avr-mmcu-specs.c -# Generated from : ./gcc/config/gcc.c -# ./gcc/config/avr/specs.h -# ./gcc/config/avr/avrlibc.h -# Used by : avr-gcc compiler driver -# Used for : building command options for sub-processes -# -# See -# for a documentation of spec files. - - -*cc1_n_flash: - %{!mn-flash=*:-mn-flash=2} - -*cc1_rmw: - %{mrmw} - -*cc1_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*cc1_absdata: - %{mabsdata} - -*asm_arch: - -mmcu=avrxmega5 - -*asm_relax: - %{mrelax:--mlink-relax} - -*asm_rmw: - %{mrmw} - -*asm_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*link_pmem_wrap: - - -*link_relax: - %{mrelax:--relax} - -*link_arch: - %{mmcu=*:-m%*} - -# End of file diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-avrxmega6 b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-avrxmega6 deleted file mode 100644 index d869d44..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-avrxmega6 +++ /dev/null @@ -1,48 +0,0 @@ -# -# Auto-generated specs for AVR core architecture avrxmega6 -# -# Generated by : ./gcc/config/avr/gen-avr-mmcu-specs.c -# Generated from : ./gcc/config/gcc.c -# ./gcc/config/avr/specs.h -# ./gcc/config/avr/avrlibc.h -# Used by : avr-gcc compiler driver -# Used for : building command options for sub-processes -# -# See -# for a documentation of spec files. - - -*cc1_n_flash: - %{!mn-flash=*:-mn-flash=6} - -*cc1_rmw: - %{mrmw} - -*cc1_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*cc1_absdata: - %{mabsdata} - -*asm_arch: - -mmcu=avrxmega6 - -*asm_relax: - %{mrelax:--mlink-relax} - -*asm_rmw: - %{mrmw} - -*asm_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*link_pmem_wrap: - - -*link_relax: - %{mrelax:--relax} - -*link_arch: - %{mmcu=*:-m%*} - -# End of file diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-avrxmega7 b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-avrxmega7 deleted file mode 100644 index 8a08321..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-avrxmega7 +++ /dev/null @@ -1,48 +0,0 @@ -# -# Auto-generated specs for AVR core architecture avrxmega7 -# -# Generated by : ./gcc/config/avr/gen-avr-mmcu-specs.c -# Generated from : ./gcc/config/gcc.c -# ./gcc/config/avr/specs.h -# ./gcc/config/avr/avrlibc.h -# Used by : avr-gcc compiler driver -# Used for : building command options for sub-processes -# -# See -# for a documentation of spec files. - - -*cc1_n_flash: - %{!mn-flash=*:-mn-flash=3} - -*cc1_rmw: - %{mrmw} - -*cc1_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*cc1_absdata: - %{mabsdata} - -*asm_arch: - -mmcu=avrxmega7 - -*asm_relax: - %{mrelax:--mlink-relax} - -*asm_rmw: - %{mrmw} - -*asm_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*link_pmem_wrap: - - -*link_relax: - %{mrelax:--relax} - -*link_arch: - %{mmcu=*:-m%*} - -# End of file diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-m3000 b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-m3000 deleted file mode 100644 index b82c1a3..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/device-specs/specs-m3000 +++ /dev/null @@ -1,99 +0,0 @@ -# -# Auto-generated specs for AVR device m3000 (core avr5, 16-bit SP) -# -# Generated by : ./gcc/config/avr/gen-avr-mmcu-specs.c -# Generated from : ./gcc/config/gcc.c -# ./gcc/config/avr/specs.h -# ./gcc/config/avr/avrlibc.h -# Used by : avr-gcc compiler driver -# Used for : building command options for sub-processes -# -# See -# for a documentation of spec files. - - -# If you intend to use an existing device specs file as a starting point -# for a new device spec file, make sure you are copying from a specs -# file for a device from the same core architecture and SP width. -# See for a description -# of how to use such own spec files. - -*avrlibc_startfile: - crtm3000.o%s - -*avrlibc_devicelib: - %{!nodevicelib:-lm3000} - -*cc1_n_flash: - %{!mn-flash=*:-mn-flash=1} - -*cc1_rmw: - %{mrmw} - -*cc1_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*cc1_absdata: - %{mabsdata} - -*asm_arch: - -mmcu=avr5 - -*asm_relax: - %{mrelax:--mlink-relax} - -*asm_rmw: - %{mrmw} - -*asm_errata_skip: - %{!mskip-bug: -mno-skip-bug} - -*link_pmem_wrap: - %{mpmem-wrap-around: --pmem-wrap-around=64k} - -*link_relax: - %{mrelax:--relax} - -*link_arch: - %{mmcu=*:-m%*} - -*link_data_start: - -Tdata 0x801000 - -*link_text_start: - - -*self_spec: - %{!mmcu=avr*: % -# #elif ... -# -# If no device macro is defined, AVR-LibC uses __AVR_DEV_LIB_NAME__ -# as fallback to determine the name of the device header as -# -# "avr/io" + __AVR_DEV_LIB_NAME__ + ".h" -# -# If you provide your own specs file for a device not yet known to -# AVR-LibC, you can now define the hook macro __AVR_DEV_LIB_NAME__ -# as needed so that -# -# #include -# -# will include the desired device header. For ATmega8A the supplement -# to *cpp would read -# -# -D__AVR_DEV_LIB_NAME__=m8a - - -*cpp: - -D__AVR_M3000__ -D__AVR_DEVICE_NAME__=m3000 - -# End of file diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/include-fixed/README b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/include-fixed/README deleted file mode 100644 index 7086a77..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/include-fixed/README +++ /dev/null @@ -1,14 +0,0 @@ -This README file is copied into the directory for GCC-only header files -when fixincludes is run by the makefile for GCC. - -Many of the files in this directory were automatically edited from the -standard system header files by the fixincludes process. They are -system-specific, and will not work on any other kind of system. They -are also not part of GCC. The reason we have to do this is because -GCC requires ANSI C headers and many vendors supply ANSI-incompatible -headers. - -Because this is an automated process, sometimes headers get "fixed" -that do not, strictly speaking, need a fix. As long as nothing is broken -by the process, it is just an unfortunate collateral inconvenience. -We would like to rectify it, if it is not "too inconvenient". diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/include-fixed/limits.h b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/include-fixed/limits.h deleted file mode 100644 index 984302e..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/include-fixed/limits.h +++ /dev/null @@ -1,126 +0,0 @@ -/* Copyright (C) 1991-2015 Free Software Foundation, Inc. - -This file is part of GCC. - -GCC is free software; you can redistribute it and/or modify it under -the terms of the GNU General Public License as published by the Free -Software Foundation; either version 3, or (at your option) any later -version. - -GCC is distributed in the hope that it will be useful, but WITHOUT ANY -WARRANTY; without even the implied warranty of MERCHANTABILITY or -FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -for more details. - -Under Section 7 of GPL version 3, you are granted additional -permissions described in the GCC Runtime Library Exception, version -3.1, as published by the Free Software Foundation. - -You should have received a copy of the GNU General Public License and -a copy of the GCC Runtime Library Exception along with this program; -see the files COPYING3 and COPYING.RUNTIME respectively. If not, see -. */ - -#ifndef _LIMITS_H___ -#define _LIMITS_H___ - -/* Number of bits in a `char'. */ -#undef CHAR_BIT -#define CHAR_BIT __CHAR_BIT__ - -/* Maximum length of a multibyte character. */ -#ifndef MB_LEN_MAX -#define MB_LEN_MAX 1 -#endif - -/* Minimum and maximum values a `signed char' can hold. */ -#undef SCHAR_MIN -#define SCHAR_MIN (-SCHAR_MAX - 1) -#undef SCHAR_MAX -#define SCHAR_MAX __SCHAR_MAX__ - -/* Maximum value an `unsigned char' can hold. (Minimum is 0). */ -#undef UCHAR_MAX -#if __SCHAR_MAX__ == __INT_MAX__ -# define UCHAR_MAX (SCHAR_MAX * 2U + 1U) -#else -# define UCHAR_MAX (SCHAR_MAX * 2 + 1) -#endif - -/* Minimum and maximum values a `char' can hold. */ -#ifdef __CHAR_UNSIGNED__ -# undef CHAR_MIN -# if __SCHAR_MAX__ == __INT_MAX__ -# define CHAR_MIN 0U -# else -# define CHAR_MIN 0 -# endif -# undef CHAR_MAX -# define CHAR_MAX UCHAR_MAX -#else -# undef CHAR_MIN -# define CHAR_MIN SCHAR_MIN -# undef CHAR_MAX -# define CHAR_MAX SCHAR_MAX -#endif - -/* Minimum and maximum values a `signed short int' can hold. */ -#undef SHRT_MIN -#define SHRT_MIN (-SHRT_MAX - 1) -#undef SHRT_MAX -#define SHRT_MAX __SHRT_MAX__ - -/* Maximum value an `unsigned short int' can hold. (Minimum is 0). */ -#undef USHRT_MAX -#if __SHRT_MAX__ == __INT_MAX__ -# define USHRT_MAX (SHRT_MAX * 2U + 1U) -#else -# define USHRT_MAX (SHRT_MAX * 2 + 1) -#endif - -/* Minimum and maximum values a `signed int' can hold. */ -#undef INT_MIN -#define INT_MIN (-INT_MAX - 1) -#undef INT_MAX -#define INT_MAX __INT_MAX__ - -/* Maximum value an `unsigned int' can hold. (Minimum is 0). */ -#undef UINT_MAX -#define UINT_MAX (INT_MAX * 2U + 1U) - -/* Minimum and maximum values a `signed long int' can hold. - (Same as `int'). */ -#undef LONG_MIN -#define LONG_MIN (-LONG_MAX - 1L) -#undef LONG_MAX -#define LONG_MAX __LONG_MAX__ - -/* Maximum value an `unsigned long int' can hold. (Minimum is 0). */ -#undef ULONG_MAX -#define ULONG_MAX (LONG_MAX * 2UL + 1UL) - -#if defined (__STDC_VERSION__) && __STDC_VERSION__ >= 199901L -/* Minimum and maximum values a `signed long long int' can hold. */ -# undef LLONG_MIN -# define LLONG_MIN (-LLONG_MAX - 1LL) -# undef LLONG_MAX -# define LLONG_MAX __LONG_LONG_MAX__ - -/* Maximum value an `unsigned long long int' can hold. (Minimum is 0). */ -# undef ULLONG_MAX -# define ULLONG_MAX (LLONG_MAX * 2ULL + 1ULL) -#endif - -#if defined (__GNU_LIBRARY__) ? defined (__USE_GNU) : !defined (__STRICT_ANSI__) -/* Minimum and maximum values a `signed long long int' can hold. */ -# undef LONG_LONG_MIN -# define LONG_LONG_MIN (-LONG_LONG_MAX - 1LL) -# undef LONG_LONG_MAX -# define LONG_LONG_MAX __LONG_LONG_MAX__ - -/* Maximum value an `unsigned long long int' can hold. (Minimum is 0). */ -# undef ULONG_LONG_MAX -# define ULONG_LONG_MAX (LONG_LONG_MAX * 2ULL + 1ULL) -#endif - -#endif /* _LIMITS_H___ */ diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/include-fixed/syslimits.h b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/include-fixed/syslimits.h deleted file mode 100644 index a362802..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/include-fixed/syslimits.h +++ /dev/null @@ -1,8 +0,0 @@ -/* syslimits.h stands for the system's own limits.h file. - If we can use it ok unmodified, then we install this text. - If fixincludes fixes it, then the fixed version is installed - instead of this text. */ - -#define _GCC_NEXT_LIMITS_H /* tell gcc's limits.h to recurse */ -#include_next -#undef _GCC_NEXT_LIMITS_H diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/include/float.h b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/include/float.h deleted file mode 100644 index 805b84d..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/include/float.h +++ /dev/null @@ -1,265 +0,0 @@ -/* Copyright (C) 2002-2015 Free Software Foundation, Inc. - -This file is part of GCC. - -GCC is free software; you can redistribute it and/or modify -it under the terms of the GNU General Public License as published by -the Free Software Foundation; either version 3, or (at your option) -any later version. - -GCC is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU General Public License for more details. - -Under Section 7 of GPL version 3, you are granted additional -permissions described in the GCC Runtime Library Exception, version -3.1, as published by the Free Software Foundation. - -You should have received a copy of the GNU General Public License and -a copy of the GCC Runtime Library Exception along with this program; -see the files COPYING3 and COPYING.RUNTIME respectively. If not, see -. */ - -/* - * ISO C Standard: 5.2.4.2.2 Characteristics of floating types - */ - -#ifndef _FLOAT_H___ -#define _FLOAT_H___ - -/* Radix of exponent representation, b. */ -#undef FLT_RADIX -#define FLT_RADIX __FLT_RADIX__ - -/* Number of base-FLT_RADIX digits in the significand, p. */ -#undef FLT_MANT_DIG -#undef DBL_MANT_DIG -#undef LDBL_MANT_DIG -#define FLT_MANT_DIG __FLT_MANT_DIG__ -#define DBL_MANT_DIG __DBL_MANT_DIG__ -#define LDBL_MANT_DIG __LDBL_MANT_DIG__ - -/* Number of decimal digits, q, such that any floating-point number with q - decimal digits can be rounded into a floating-point number with p radix b - digits and back again without change to the q decimal digits, - - p * log10(b) if b is a power of 10 - floor((p - 1) * log10(b)) otherwise -*/ -#undef FLT_DIG -#undef DBL_DIG -#undef LDBL_DIG -#define FLT_DIG __FLT_DIG__ -#define DBL_DIG __DBL_DIG__ -#define LDBL_DIG __LDBL_DIG__ - -/* Minimum int x such that FLT_RADIX**(x-1) is a normalized float, emin */ -#undef FLT_MIN_EXP -#undef DBL_MIN_EXP -#undef LDBL_MIN_EXP -#define FLT_MIN_EXP __FLT_MIN_EXP__ -#define DBL_MIN_EXP __DBL_MIN_EXP__ -#define LDBL_MIN_EXP __LDBL_MIN_EXP__ - -/* Minimum negative integer such that 10 raised to that power is in the - range of normalized floating-point numbers, - - ceil(log10(b) * (emin - 1)) -*/ -#undef FLT_MIN_10_EXP -#undef DBL_MIN_10_EXP -#undef LDBL_MIN_10_EXP -#define FLT_MIN_10_EXP __FLT_MIN_10_EXP__ -#define DBL_MIN_10_EXP __DBL_MIN_10_EXP__ -#define LDBL_MIN_10_EXP __LDBL_MIN_10_EXP__ - -/* Maximum int x such that FLT_RADIX**(x-1) is a representable float, emax. */ -#undef FLT_MAX_EXP -#undef DBL_MAX_EXP -#undef LDBL_MAX_EXP -#define FLT_MAX_EXP __FLT_MAX_EXP__ -#define DBL_MAX_EXP __DBL_MAX_EXP__ -#define LDBL_MAX_EXP __LDBL_MAX_EXP__ - -/* Maximum integer such that 10 raised to that power is in the range of - representable finite floating-point numbers, - - floor(log10((1 - b**-p) * b**emax)) -*/ -#undef FLT_MAX_10_EXP -#undef DBL_MAX_10_EXP -#undef LDBL_MAX_10_EXP -#define FLT_MAX_10_EXP __FLT_MAX_10_EXP__ -#define DBL_MAX_10_EXP __DBL_MAX_10_EXP__ -#define LDBL_MAX_10_EXP __LDBL_MAX_10_EXP__ - -/* Maximum representable finite floating-point number, - - (1 - b**-p) * b**emax -*/ -#undef FLT_MAX -#undef DBL_MAX -#undef LDBL_MAX -#define FLT_MAX __FLT_MAX__ -#define DBL_MAX __DBL_MAX__ -#define LDBL_MAX __LDBL_MAX__ - -/* The difference between 1 and the least value greater than 1 that is - representable in the given floating point type, b**1-p. */ -#undef FLT_EPSILON -#undef DBL_EPSILON -#undef LDBL_EPSILON -#define FLT_EPSILON __FLT_EPSILON__ -#define DBL_EPSILON __DBL_EPSILON__ -#define LDBL_EPSILON __LDBL_EPSILON__ - -/* Minimum normalized positive floating-point number, b**(emin - 1). */ -#undef FLT_MIN -#undef DBL_MIN -#undef LDBL_MIN -#define FLT_MIN __FLT_MIN__ -#define DBL_MIN __DBL_MIN__ -#define LDBL_MIN __LDBL_MIN__ - -/* Addition rounds to 0: zero, 1: nearest, 2: +inf, 3: -inf, -1: unknown. */ -/* ??? This is supposed to change with calls to fesetround in . */ -#undef FLT_ROUNDS -#define FLT_ROUNDS 1 - -#if defined (__STDC_VERSION__) && __STDC_VERSION__ >= 199901L -/* The floating-point expression evaluation method. - -1 indeterminate - 0 evaluate all operations and constants just to the range and - precision of the type - 1 evaluate operations and constants of type float and double - to the range and precision of the double type, evaluate - long double operations and constants to the range and - precision of the long double type - 2 evaluate all operations and constants to the range and - precision of the long double type - - ??? This ought to change with the setting of the fp control word; - the value provided by the compiler assumes the widest setting. */ -#undef FLT_EVAL_METHOD -#define FLT_EVAL_METHOD __FLT_EVAL_METHOD__ - -/* Number of decimal digits, n, such that any floating-point number in the - widest supported floating type with pmax radix b digits can be rounded - to a floating-point number with n decimal digits and back again without - change to the value, - - pmax * log10(b) if b is a power of 10 - ceil(1 + pmax * log10(b)) otherwise -*/ -#undef DECIMAL_DIG -#define DECIMAL_DIG __DECIMAL_DIG__ - -#endif /* C99 */ - -#if defined (__STDC_VERSION__) && __STDC_VERSION__ >= 201112L -/* Versions of DECIMAL_DIG for each floating-point type. */ -#undef FLT_DECIMAL_DIG -#undef DBL_DECIMAL_DIG -#undef LDBL_DECIMAL_DIG -#define FLT_DECIMAL_DIG __FLT_DECIMAL_DIG__ -#define DBL_DECIMAL_DIG __DBL_DECIMAL_DIG__ -#define LDBL_DECIMAL_DIG __DECIMAL_DIG__ - -/* Whether types support subnormal numbers. */ -#undef FLT_HAS_SUBNORM -#undef DBL_HAS_SUBNORM -#undef LDBL_HAS_SUBNORM -#define FLT_HAS_SUBNORM __FLT_HAS_DENORM__ -#define DBL_HAS_SUBNORM __DBL_HAS_DENORM__ -#define LDBL_HAS_SUBNORM __LDBL_HAS_DENORM__ - -/* Minimum positive values, including subnormals. */ -#undef FLT_TRUE_MIN -#undef DBL_TRUE_MIN -#undef LDBL_TRUE_MIN -#define FLT_TRUE_MIN __FLT_DENORM_MIN__ -#define DBL_TRUE_MIN __DBL_DENORM_MIN__ -#define LDBL_TRUE_MIN __LDBL_DENORM_MIN__ - -#endif /* C11 */ - -#ifdef __STDC_WANT_DEC_FP__ -/* Draft Technical Report 24732, extension for decimal floating-point - arithmetic: Characteristic of decimal floating types . */ - -/* Number of base-FLT_RADIX digits in the significand, p. */ -#undef DEC32_MANT_DIG -#undef DEC64_MANT_DIG -#undef DEC128_MANT_DIG -#define DEC32_MANT_DIG __DEC32_MANT_DIG__ -#define DEC64_MANT_DIG __DEC64_MANT_DIG__ -#define DEC128_MANT_DIG __DEC128_MANT_DIG__ - -/* Minimum exponent. */ -#undef DEC32_MIN_EXP -#undef DEC64_MIN_EXP -#undef DEC128_MIN_EXP -#define DEC32_MIN_EXP __DEC32_MIN_EXP__ -#define DEC64_MIN_EXP __DEC64_MIN_EXP__ -#define DEC128_MIN_EXP __DEC128_MIN_EXP__ - -/* Maximum exponent. */ -#undef DEC32_MAX_EXP -#undef DEC64_MAX_EXP -#undef DEC128_MAX_EXP -#define DEC32_MAX_EXP __DEC32_MAX_EXP__ -#define DEC64_MAX_EXP __DEC64_MAX_EXP__ -#define DEC128_MAX_EXP __DEC128_MAX_EXP__ - -/* Maximum representable finite decimal floating-point number - (there are 6, 15, and 33 9s after the decimal points respectively). */ -#undef DEC32_MAX -#undef DEC64_MAX -#undef DEC128_MAX -#define DEC32_MAX __DEC32_MAX__ -#define DEC64_MAX __DEC64_MAX__ -#define DEC128_MAX __DEC128_MAX__ - -/* The difference between 1 and the least value greater than 1 that is - representable in the given floating point type. */ -#undef DEC32_EPSILON -#undef DEC64_EPSILON -#undef DEC128_EPSILON -#define DEC32_EPSILON __DEC32_EPSILON__ -#define DEC64_EPSILON __DEC64_EPSILON__ -#define DEC128_EPSILON __DEC128_EPSILON__ - -/* Minimum normalized positive floating-point number. */ -#undef DEC32_MIN -#undef DEC64_MIN -#undef DEC128_MIN -#define DEC32_MIN __DEC32_MIN__ -#define DEC64_MIN __DEC64_MIN__ -#define DEC128_MIN __DEC128_MIN__ - -/* Minimum subnormal positive floating-point number. */ -#undef DEC32_SUBNORMAL_MIN -#undef DEC64_SUBNORMAL_MIN -#undef DEC128_SUBNORMAL_MIN -#define DEC32_SUBNORMAL_MIN __DEC32_SUBNORMAL_MIN__ -#define DEC64_SUBNORMAL_MIN __DEC64_SUBNORMAL_MIN__ -#define DEC128_SUBNORMAL_MIN __DEC128_SUBNORMAL_MIN__ - -/* The floating-point expression evaluation method. - -1 indeterminate - 0 evaluate all operations and constants just to the range and - precision of the type - 1 evaluate operations and constants of type _Decimal32 - and _Decimal64 to the range and precision of the _Decimal64 - type, evaluate _Decimal128 operations and constants to the - range and precision of the _Decimal128 type; - 2 evaluate all operations and constants to the range and - precision of the _Decimal128 type. */ - -#undef DEC_EVAL_METHOD -#define DEC_EVAL_METHOD __DEC_EVAL_METHOD__ - -#endif /* __STDC_WANT_DEC_FP__ */ - -#endif /* _FLOAT_H___ */ diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/include/iso646.h b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/include/iso646.h deleted file mode 100644 index 73c677f..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/include/iso646.h +++ /dev/null @@ -1,45 +0,0 @@ -/* Copyright (C) 1997-2015 Free Software Foundation, Inc. - -This file is part of GCC. - -GCC is free software; you can redistribute it and/or modify -it under the terms of the GNU General Public License as published by -the Free Software Foundation; either version 3, or (at your option) -any later version. - -GCC is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU General Public License for more details. - -Under Section 7 of GPL version 3, you are granted additional -permissions described in the GCC Runtime Library Exception, version -3.1, as published by the Free Software Foundation. - -You should have received a copy of the GNU General Public License and -a copy of the GCC Runtime Library Exception along with this program; -see the files COPYING3 and COPYING.RUNTIME respectively. If not, see -. */ - -/* - * ISO C Standard: 7.9 Alternative spellings - */ - -#ifndef _ISO646_H -#define _ISO646_H - -#ifndef __cplusplus -#define and && -#define and_eq &= -#define bitand & -#define bitor | -#define compl ~ -#define not ! -#define not_eq != -#define or || -#define or_eq |= -#define xor ^ -#define xor_eq ^= -#endif - -#endif diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/include/stdalign.h b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/include/stdalign.h deleted file mode 100644 index 1615657..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/include/stdalign.h +++ /dev/null @@ -1,39 +0,0 @@ -/* Copyright (C) 2011-2015 Free Software Foundation, Inc. - -This file is part of GCC. - -GCC is free software; you can redistribute it and/or modify -it under the terms of the GNU General Public License as published by -the Free Software Foundation; either version 3, or (at your option) -any later version. - -GCC is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU General Public License for more details. - -Under Section 7 of GPL version 3, you are granted additional -permissions described in the GCC Runtime Library Exception, version -3.1, as published by the Free Software Foundation. - -You should have received a copy of the GNU General Public License and -a copy of the GCC Runtime Library Exception along with this program; -see the files COPYING3 and COPYING.RUNTIME respectively. If not, see -. */ - -/* ISO C1X: 7.15 Alignment . */ - -#ifndef _STDALIGN_H -#define _STDALIGN_H - -#ifndef __cplusplus - -#define alignas _Alignas -#define alignof _Alignof - -#define __alignas_is_defined 1 -#define __alignof_is_defined 1 - -#endif - -#endif /* stdalign.h */ diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/include/stdarg.h b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/include/stdarg.h deleted file mode 100644 index afc1cc5..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/include/stdarg.h +++ /dev/null @@ -1,126 +0,0 @@ -/* Copyright (C) 1989-2015 Free Software Foundation, Inc. - -This file is part of GCC. - -GCC is free software; you can redistribute it and/or modify -it under the terms of the GNU General Public License as published by -the Free Software Foundation; either version 3, or (at your option) -any later version. - -GCC is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU General Public License for more details. - -Under Section 7 of GPL version 3, you are granted additional -permissions described in the GCC Runtime Library Exception, version -3.1, as published by the Free Software Foundation. - -You should have received a copy of the GNU General Public License and -a copy of the GCC Runtime Library Exception along with this program; -see the files COPYING3 and COPYING.RUNTIME respectively. If not, see -. */ - -/* - * ISO C Standard: 7.15 Variable arguments - */ - -#ifndef _STDARG_H -#ifndef _ANSI_STDARG_H_ -#ifndef __need___va_list -#define _STDARG_H -#define _ANSI_STDARG_H_ -#endif /* not __need___va_list */ -#undef __need___va_list - -/* Define __gnuc_va_list. */ - -#ifndef __GNUC_VA_LIST -#define __GNUC_VA_LIST -typedef __builtin_va_list __gnuc_va_list; -#endif - -/* Define the standard macros for the user, - if this invocation was from the user program. */ -#ifdef _STDARG_H - -#define va_start(v,l) __builtin_va_start(v,l) -#define va_end(v) __builtin_va_end(v) -#define va_arg(v,l) __builtin_va_arg(v,l) -#if !defined(__STRICT_ANSI__) || __STDC_VERSION__ + 0 >= 199900L || defined(__GXX_EXPERIMENTAL_CXX0X__) -#define va_copy(d,s) __builtin_va_copy(d,s) -#endif -#define __va_copy(d,s) __builtin_va_copy(d,s) - -/* Define va_list, if desired, from __gnuc_va_list. */ -/* We deliberately do not define va_list when called from - stdio.h, because ANSI C says that stdio.h is not supposed to define - va_list. stdio.h needs to have access to that data type, - but must not use that name. It should use the name __gnuc_va_list, - which is safe because it is reserved for the implementation. */ - -#ifdef _BSD_VA_LIST -#undef _BSD_VA_LIST -#endif - -#if defined(__svr4__) || (defined(_SCO_DS) && !defined(__VA_LIST)) -/* SVR4.2 uses _VA_LIST for an internal alias for va_list, - so we must avoid testing it and setting it here. - SVR4 uses _VA_LIST as a flag in stdarg.h, but we should - have no conflict with that. */ -#ifndef _VA_LIST_ -#define _VA_LIST_ -#ifdef __i860__ -#ifndef _VA_LIST -#define _VA_LIST va_list -#endif -#endif /* __i860__ */ -typedef __gnuc_va_list va_list; -#ifdef _SCO_DS -#define __VA_LIST -#endif -#endif /* _VA_LIST_ */ -#else /* not __svr4__ || _SCO_DS */ - -/* The macro _VA_LIST_ is the same thing used by this file in Ultrix. - But on BSD NET2 we must not test or define or undef it. - (Note that the comments in NET 2's ansi.h - are incorrect for _VA_LIST_--see stdio.h!) */ -#if !defined (_VA_LIST_) || defined (__BSD_NET2__) || defined (____386BSD____) || defined (__bsdi__) || defined (__sequent__) || defined (__FreeBSD__) || defined(WINNT) -/* The macro _VA_LIST_DEFINED is used in Windows NT 3.5 */ -#ifndef _VA_LIST_DEFINED -/* The macro _VA_LIST is used in SCO Unix 3.2. */ -#ifndef _VA_LIST -/* The macro _VA_LIST_T_H is used in the Bull dpx2 */ -#ifndef _VA_LIST_T_H -/* The macro __va_list__ is used by BeOS. */ -#ifndef __va_list__ -typedef __gnuc_va_list va_list; -#endif /* not __va_list__ */ -#endif /* not _VA_LIST_T_H */ -#endif /* not _VA_LIST */ -#endif /* not _VA_LIST_DEFINED */ -#if !(defined (__BSD_NET2__) || defined (____386BSD____) || defined (__bsdi__) || defined (__sequent__) || defined (__FreeBSD__)) -#define _VA_LIST_ -#endif -#ifndef _VA_LIST -#define _VA_LIST -#endif -#ifndef _VA_LIST_DEFINED -#define _VA_LIST_DEFINED -#endif -#ifndef _VA_LIST_T_H -#define _VA_LIST_T_H -#endif -#ifndef __va_list__ -#define __va_list__ -#endif - -#endif /* not _VA_LIST_, except on certain systems */ - -#endif /* not __svr4__ */ - -#endif /* _STDARG_H */ - -#endif /* not _ANSI_STDARG_H_ */ -#endif /* not _STDARG_H */ diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/include/stdatomic.h b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/include/stdatomic.h deleted file mode 100644 index b961da2..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/include/stdatomic.h +++ /dev/null @@ -1,238 +0,0 @@ -/* Copyright (C) 2013-2015 Free Software Foundation, Inc. - -This file is part of GCC. - -GCC is free software; you can redistribute it and/or modify -it under the terms of the GNU General Public License as published by -the Free Software Foundation; either version 3, or (at your option) -any later version. - -GCC is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU General Public License for more details. - -Under Section 7 of GPL version 3, you are granted additional -permissions described in the GCC Runtime Library Exception, version -3.1, as published by the Free Software Foundation. - -You should have received a copy of the GNU General Public License and -a copy of the GCC Runtime Library Exception along with this program; -see the files COPYING3 and COPYING.RUNTIME respectively. If not, see -. */ - -/* ISO C11 Standard: 7.17 Atomics . */ - -#ifndef _STDATOMIC_H -#define _STDATOMIC_H - -typedef enum - { - memory_order_relaxed = __ATOMIC_RELAXED, - memory_order_consume = __ATOMIC_CONSUME, - memory_order_acquire = __ATOMIC_ACQUIRE, - memory_order_release = __ATOMIC_RELEASE, - memory_order_acq_rel = __ATOMIC_ACQ_REL, - memory_order_seq_cst = __ATOMIC_SEQ_CST - } memory_order; - - -typedef _Atomic _Bool atomic_bool; -typedef _Atomic char atomic_char; -typedef _Atomic signed char atomic_schar; -typedef _Atomic unsigned char atomic_uchar; -typedef _Atomic short atomic_short; -typedef _Atomic unsigned short atomic_ushort; -typedef _Atomic int atomic_int; -typedef _Atomic unsigned int atomic_uint; -typedef _Atomic long atomic_long; -typedef _Atomic unsigned long atomic_ulong; -typedef _Atomic long long atomic_llong; -typedef _Atomic unsigned long long atomic_ullong; -typedef _Atomic __CHAR16_TYPE__ atomic_char16_t; -typedef _Atomic __CHAR32_TYPE__ atomic_char32_t; -typedef _Atomic __WCHAR_TYPE__ atomic_wchar_t; -typedef _Atomic __INT_LEAST8_TYPE__ atomic_int_least8_t; -typedef _Atomic __UINT_LEAST8_TYPE__ atomic_uint_least8_t; -typedef _Atomic __INT_LEAST16_TYPE__ atomic_int_least16_t; -typedef _Atomic __UINT_LEAST16_TYPE__ atomic_uint_least16_t; -typedef _Atomic __INT_LEAST32_TYPE__ atomic_int_least32_t; -typedef _Atomic __UINT_LEAST32_TYPE__ atomic_uint_least32_t; -typedef _Atomic __INT_LEAST64_TYPE__ atomic_int_least64_t; -typedef _Atomic __UINT_LEAST64_TYPE__ atomic_uint_least64_t; -typedef _Atomic __INT_FAST8_TYPE__ atomic_int_fast8_t; -typedef _Atomic __UINT_FAST8_TYPE__ atomic_uint_fast8_t; -typedef _Atomic __INT_FAST16_TYPE__ atomic_int_fast16_t; -typedef _Atomic __UINT_FAST16_TYPE__ atomic_uint_fast16_t; -typedef _Atomic __INT_FAST32_TYPE__ atomic_int_fast32_t; -typedef _Atomic __UINT_FAST32_TYPE__ atomic_uint_fast32_t; -typedef _Atomic __INT_FAST64_TYPE__ atomic_int_fast64_t; -typedef _Atomic __UINT_FAST64_TYPE__ atomic_uint_fast64_t; -typedef _Atomic __INTPTR_TYPE__ atomic_intptr_t; -typedef _Atomic __UINTPTR_TYPE__ atomic_uintptr_t; -typedef _Atomic __SIZE_TYPE__ atomic_size_t; -typedef _Atomic __PTRDIFF_TYPE__ atomic_ptrdiff_t; -typedef _Atomic __INTMAX_TYPE__ atomic_intmax_t; -typedef _Atomic __UINTMAX_TYPE__ atomic_uintmax_t; - - -#define ATOMIC_VAR_INIT(VALUE) (VALUE) -#define atomic_init(PTR, VAL) \ - do \ - { \ - *(PTR) = (VAL); \ - } \ - while (0) - -#define kill_dependency(Y) \ - __extension__ \ - ({ \ - __auto_type __kill_dependency_tmp = (Y); \ - __kill_dependency_tmp; \ - }) - -#define atomic_thread_fence(MO) __atomic_thread_fence (MO) -#define atomic_signal_fence(MO) __atomic_signal_fence (MO) -#define atomic_is_lock_free(OBJ) __atomic_is_lock_free (sizeof (*(OBJ)), (OBJ)) - -#define ATOMIC_BOOL_LOCK_FREE __GCC_ATOMIC_BOOL_LOCK_FREE -#define ATOMIC_CHAR_LOCK_FREE __GCC_ATOMIC_CHAR_LOCK_FREE -#define ATOMIC_CHAR16_T_LOCK_FREE __GCC_ATOMIC_CHAR16_T_LOCK_FREE -#define ATOMIC_CHAR32_T_LOCK_FREE __GCC_ATOMIC_CHAR32_T_LOCK_FREE -#define ATOMIC_WCHAR_T_LOCK_FREE __GCC_ATOMIC_WCHAR_T_LOCK_FREE -#define ATOMIC_SHORT_LOCK_FREE __GCC_ATOMIC_SHORT_LOCK_FREE -#define ATOMIC_INT_LOCK_FREE __GCC_ATOMIC_INT_LOCK_FREE -#define ATOMIC_LONG_LOCK_FREE __GCC_ATOMIC_LONG_LOCK_FREE -#define ATOMIC_LLONG_LOCK_FREE __GCC_ATOMIC_LLONG_LOCK_FREE -#define ATOMIC_POINTER_LOCK_FREE __GCC_ATOMIC_POINTER_LOCK_FREE - - -/* Note that these macros require __typeof__ and __auto_type to remove - _Atomic qualifiers (and const qualifiers, if those are valid on - macro operands). - - Also note that the header file uses the generic form of __atomic - builtins, which requires the address to be taken of the value - parameter, and then we pass that value on. This allows the macros - to work for any type, and the compiler is smart enough to convert - these to lock-free _N variants if possible, and throw away the - temps. */ - -#define atomic_store_explicit(PTR, VAL, MO) \ - __extension__ \ - ({ \ - __auto_type __atomic_store_ptr = (PTR); \ - __typeof__ (*__atomic_store_ptr) __atomic_store_tmp = (VAL); \ - __atomic_store (__atomic_store_ptr, &__atomic_store_tmp, (MO)); \ - }) - -#define atomic_store(PTR, VAL) \ - atomic_store_explicit (PTR, VAL, __ATOMIC_SEQ_CST) - - -#define atomic_load_explicit(PTR, MO) \ - __extension__ \ - ({ \ - __auto_type __atomic_load_ptr = (PTR); \ - __typeof__ (*__atomic_load_ptr) __atomic_load_tmp; \ - __atomic_load (__atomic_load_ptr, &__atomic_load_tmp, (MO)); \ - __atomic_load_tmp; \ - }) - -#define atomic_load(PTR) atomic_load_explicit (PTR, __ATOMIC_SEQ_CST) - - -#define atomic_exchange_explicit(PTR, VAL, MO) \ - __extension__ \ - ({ \ - __auto_type __atomic_exchange_ptr = (PTR); \ - __typeof__ (*__atomic_exchange_ptr) __atomic_exchange_val = (VAL); \ - __typeof__ (*__atomic_exchange_ptr) __atomic_exchange_tmp; \ - __atomic_exchange (__atomic_exchange_ptr, &__atomic_exchange_val, \ - &__atomic_exchange_tmp, (MO)); \ - __atomic_exchange_tmp; \ - }) - -#define atomic_exchange(PTR, VAL) \ - atomic_exchange_explicit (PTR, VAL, __ATOMIC_SEQ_CST) - - -#define atomic_compare_exchange_strong_explicit(PTR, VAL, DES, SUC, FAIL) \ - __extension__ \ - ({ \ - __auto_type __atomic_compare_exchange_ptr = (PTR); \ - __typeof__ (*__atomic_compare_exchange_ptr) __atomic_compare_exchange_tmp \ - = (DES); \ - __atomic_compare_exchange (__atomic_compare_exchange_ptr, (VAL), \ - &__atomic_compare_exchange_tmp, 0, \ - (SUC), (FAIL)); \ - }) - -#define atomic_compare_exchange_strong(PTR, VAL, DES) \ - atomic_compare_exchange_strong_explicit (PTR, VAL, DES, __ATOMIC_SEQ_CST, \ - __ATOMIC_SEQ_CST) - -#define atomic_compare_exchange_weak_explicit(PTR, VAL, DES, SUC, FAIL) \ - __extension__ \ - ({ \ - __auto_type __atomic_compare_exchange_ptr = (PTR); \ - __typeof__ (*__atomic_compare_exchange_ptr) __atomic_compare_exchange_tmp \ - = (DES); \ - __atomic_compare_exchange (__atomic_compare_exchange_ptr, (VAL), \ - &__atomic_compare_exchange_tmp, 1, \ - (SUC), (FAIL)); \ - }) - -#define atomic_compare_exchange_weak(PTR, VAL, DES) \ - atomic_compare_exchange_weak_explicit (PTR, VAL, DES, __ATOMIC_SEQ_CST, \ - __ATOMIC_SEQ_CST) - - - -#define atomic_fetch_add(PTR, VAL) __atomic_fetch_add ((PTR), (VAL), \ - __ATOMIC_SEQ_CST) -#define atomic_fetch_add_explicit(PTR, VAL, MO) \ - __atomic_fetch_add ((PTR), (VAL), (MO)) - -#define atomic_fetch_sub(PTR, VAL) __atomic_fetch_sub ((PTR), (VAL), \ - __ATOMIC_SEQ_CST) -#define atomic_fetch_sub_explicit(PTR, VAL, MO) \ - __atomic_fetch_sub ((PTR), (VAL), (MO)) - -#define atomic_fetch_or(PTR, VAL) __atomic_fetch_or ((PTR), (VAL), \ - __ATOMIC_SEQ_CST) -#define atomic_fetch_or_explicit(PTR, VAL, MO) \ - __atomic_fetch_or ((PTR), (VAL), (MO)) - -#define atomic_fetch_xor(PTR, VAL) __atomic_fetch_xor ((PTR), (VAL), \ - __ATOMIC_SEQ_CST) -#define atomic_fetch_xor_explicit(PTR, VAL, MO) \ - __atomic_fetch_xor ((PTR), (VAL), (MO)) - -#define atomic_fetch_and(PTR, VAL) __atomic_fetch_and ((PTR), (VAL), \ - __ATOMIC_SEQ_CST) -#define atomic_fetch_and_explicit(PTR, VAL, MO) \ - __atomic_fetch_and ((PTR), (VAL), (MO)) - - -typedef _Atomic struct -{ -#if __GCC_ATOMIC_TEST_AND_SET_TRUEVAL == 1 - _Bool __val; -#else - unsigned char __val; -#endif -} atomic_flag; - -#define ATOMIC_FLAG_INIT { 0 } - - -#define atomic_flag_test_and_set(PTR) \ - __atomic_test_and_set ((PTR), __ATOMIC_SEQ_CST) -#define atomic_flag_test_and_set_explicit(PTR, MO) \ - __atomic_test_and_set ((PTR), (MO)) - -#define atomic_flag_clear(PTR) __atomic_clear ((PTR), __ATOMIC_SEQ_CST) -#define atomic_flag_clear_explicit(PTR, MO) __atomic_clear ((PTR), (MO)) - -#endif /* _STDATOMIC_H */ diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/include/stdbool.h b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/include/stdbool.h deleted file mode 100644 index a951510..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/include/stdbool.h +++ /dev/null @@ -1,54 +0,0 @@ -/* Copyright (C) 1998-2015 Free Software Foundation, Inc. - -This file is part of GCC. - -GCC is free software; you can redistribute it and/or modify -it under the terms of the GNU General Public License as published by -the Free Software Foundation; either version 3, or (at your option) -any later version. - -GCC is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU General Public License for more details. - -Under Section 7 of GPL version 3, you are granted additional -permissions described in the GCC Runtime Library Exception, version -3.1, as published by the Free Software Foundation. - -You should have received a copy of the GNU General Public License and -a copy of the GCC Runtime Library Exception along with this program; -see the files COPYING3 and COPYING.RUNTIME respectively. If not, see -. */ - -/* - * ISO C Standard: 7.16 Boolean type and values - */ - -#ifndef _STDBOOL_H -#define _STDBOOL_H - -#ifndef __cplusplus - -#define bool _Bool -#define true 1 -#define false 0 - -#else /* __cplusplus */ - -/* Supporting _Bool in C++ is a GCC extension. */ -#define _Bool bool - -#if __cplusplus < 201103L -/* Defining these macros in C++98 is a GCC extension. */ -#define bool bool -#define false false -#define true true -#endif - -#endif /* __cplusplus */ - -/* Signal that all the definitions are present. */ -#define __bool_true_false_are_defined 1 - -#endif /* stdbool.h */ diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/include/stddef.h b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/include/stddef.h deleted file mode 100644 index f20a41b..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/include/stddef.h +++ /dev/null @@ -1,443 +0,0 @@ -/* Copyright (C) 1989-2015 Free Software Foundation, Inc. - -This file is part of GCC. - -GCC is free software; you can redistribute it and/or modify -it under the terms of the GNU General Public License as published by -the Free Software Foundation; either version 3, or (at your option) -any later version. - -GCC is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU General Public License for more details. - -Under Section 7 of GPL version 3, you are granted additional -permissions described in the GCC Runtime Library Exception, version -3.1, as published by the Free Software Foundation. - -You should have received a copy of the GNU General Public License and -a copy of the GCC Runtime Library Exception along with this program; -see the files COPYING3 and COPYING.RUNTIME respectively. If not, see -. */ - -/* - * ISO C Standard: 7.17 Common definitions - */ -#if (!defined(_STDDEF_H) && !defined(_STDDEF_H_) && !defined(_ANSI_STDDEF_H) \ - && !defined(__STDDEF_H__)) \ - || defined(__need_wchar_t) || defined(__need_size_t) \ - || defined(__need_ptrdiff_t) || defined(__need_NULL) \ - || defined(__need_wint_t) - -/* Any one of these symbols __need_* means that GNU libc - wants us just to define one data type. So don't define - the symbols that indicate this file's entire job has been done. */ -#if (!defined(__need_wchar_t) && !defined(__need_size_t) \ - && !defined(__need_ptrdiff_t) && !defined(__need_NULL) \ - && !defined(__need_wint_t)) -#define _STDDEF_H -#define _STDDEF_H_ -/* snaroff@next.com says the NeXT needs this. */ -#define _ANSI_STDDEF_H -#endif - -#ifndef __sys_stdtypes_h -/* This avoids lossage on SunOS but only if stdtypes.h comes first. - There's no way to win with the other order! Sun lossage. */ - -/* On 4.3bsd-net2, make sure ansi.h is included, so we have - one less case to deal with in the following. */ -#if defined (__BSD_NET2__) || defined (____386BSD____) || (defined (__FreeBSD__) && (__FreeBSD__ < 5)) || defined(__NetBSD__) -#include -#endif -/* On FreeBSD 5, machine/ansi.h does not exist anymore... */ -#if defined (__FreeBSD__) && (__FreeBSD__ >= 5) -#include -#endif - -/* In 4.3bsd-net2, machine/ansi.h defines these symbols, which are - defined if the corresponding type is *not* defined. - FreeBSD-2.1 defines _MACHINE_ANSI_H_ instead of _ANSI_H_. - NetBSD defines _I386_ANSI_H_ and _X86_64_ANSI_H_ instead of _ANSI_H_ */ -#if defined(_ANSI_H_) || defined(_MACHINE_ANSI_H_) || defined(_X86_64_ANSI_H_) || defined(_I386_ANSI_H_) -#if !defined(_SIZE_T_) && !defined(_BSD_SIZE_T_) -#define _SIZE_T -#endif -#if !defined(_PTRDIFF_T_) && !defined(_BSD_PTRDIFF_T_) -#define _PTRDIFF_T -#endif -/* On BSD/386 1.1, at least, machine/ansi.h defines _BSD_WCHAR_T_ - instead of _WCHAR_T_. */ -#if !defined(_WCHAR_T_) && !defined(_BSD_WCHAR_T_) -#ifndef _BSD_WCHAR_T_ -#define _WCHAR_T -#endif -#endif -/* Undef _FOO_T_ if we are supposed to define foo_t. */ -#if defined (__need_ptrdiff_t) || defined (_STDDEF_H_) -#undef _PTRDIFF_T_ -#undef _BSD_PTRDIFF_T_ -#endif -#if defined (__need_size_t) || defined (_STDDEF_H_) -#undef _SIZE_T_ -#undef _BSD_SIZE_T_ -#endif -#if defined (__need_wchar_t) || defined (_STDDEF_H_) -#undef _WCHAR_T_ -#undef _BSD_WCHAR_T_ -#endif -#endif /* defined(_ANSI_H_) || defined(_MACHINE_ANSI_H_) || defined(_X86_64_ANSI_H_) || defined(_I386_ANSI_H_) */ - -/* Sequent's header files use _PTRDIFF_T_ in some conflicting way. - Just ignore it. */ -#if defined (__sequent__) && defined (_PTRDIFF_T_) -#undef _PTRDIFF_T_ -#endif - -/* On VxWorks, may have defined macros like - _TYPE_size_t which will typedef size_t. fixincludes patched the - vxTypesBase.h so that this macro is only defined if _GCC_SIZE_T is - not defined, and so that defining this macro defines _GCC_SIZE_T. - If we find that the macros are still defined at this point, we must - invoke them so that the type is defined as expected. */ -#if defined (_TYPE_ptrdiff_t) && (defined (__need_ptrdiff_t) || defined (_STDDEF_H_)) -_TYPE_ptrdiff_t; -#undef _TYPE_ptrdiff_t -#endif -#if defined (_TYPE_size_t) && (defined (__need_size_t) || defined (_STDDEF_H_)) -_TYPE_size_t; -#undef _TYPE_size_t -#endif -#if defined (_TYPE_wchar_t) && (defined (__need_wchar_t) || defined (_STDDEF_H_)) -_TYPE_wchar_t; -#undef _TYPE_wchar_t -#endif - -/* In case nobody has defined these types, but we aren't running under - GCC 2.00, make sure that __PTRDIFF_TYPE__, __SIZE_TYPE__, and - __WCHAR_TYPE__ have reasonable values. This can happen if the - parts of GCC is compiled by an older compiler, that actually - include gstddef.h, such as collect2. */ - -/* Signed type of difference of two pointers. */ - -/* Define this type if we are doing the whole job, - or if we want this type in particular. */ -#if defined (_STDDEF_H) || defined (__need_ptrdiff_t) -#ifndef _PTRDIFF_T /* in case has defined it. */ -#ifndef _T_PTRDIFF_ -#ifndef _T_PTRDIFF -#ifndef __PTRDIFF_T -#ifndef _PTRDIFF_T_ -#ifndef _BSD_PTRDIFF_T_ -#ifndef ___int_ptrdiff_t_h -#ifndef _GCC_PTRDIFF_T -#ifndef _PTRDIFF_T_DECLARED /* DragonFly */ -#define _PTRDIFF_T -#define _T_PTRDIFF_ -#define _T_PTRDIFF -#define __PTRDIFF_T -#define _PTRDIFF_T_ -#define _BSD_PTRDIFF_T_ -#define ___int_ptrdiff_t_h -#define _GCC_PTRDIFF_T -#define _PTRDIFF_T_DECLARED -#ifndef __PTRDIFF_TYPE__ -#define __PTRDIFF_TYPE__ long int -#endif -typedef __PTRDIFF_TYPE__ ptrdiff_t; -#endif /* _PTRDIFF_T_DECLARED */ -#endif /* _GCC_PTRDIFF_T */ -#endif /* ___int_ptrdiff_t_h */ -#endif /* _BSD_PTRDIFF_T_ */ -#endif /* _PTRDIFF_T_ */ -#endif /* __PTRDIFF_T */ -#endif /* _T_PTRDIFF */ -#endif /* _T_PTRDIFF_ */ -#endif /* _PTRDIFF_T */ - -/* If this symbol has done its job, get rid of it. */ -#undef __need_ptrdiff_t - -#endif /* _STDDEF_H or __need_ptrdiff_t. */ - -/* Unsigned type of `sizeof' something. */ - -/* Define this type if we are doing the whole job, - or if we want this type in particular. */ -#if defined (_STDDEF_H) || defined (__need_size_t) -#ifndef __size_t__ /* BeOS */ -#ifndef __SIZE_T__ /* Cray Unicos/Mk */ -#ifndef _SIZE_T /* in case has defined it. */ -#ifndef _SYS_SIZE_T_H -#ifndef _T_SIZE_ -#ifndef _T_SIZE -#ifndef __SIZE_T -#ifndef _SIZE_T_ -#ifndef _BSD_SIZE_T_ -#ifndef _SIZE_T_DEFINED_ -#ifndef _SIZE_T_DEFINED -#ifndef _BSD_SIZE_T_DEFINED_ /* Darwin */ -#ifndef _SIZE_T_DECLARED /* FreeBSD 5 */ -#ifndef ___int_size_t_h -#ifndef _GCC_SIZE_T -#ifndef _SIZET_ -#ifndef __size_t -#define __size_t__ /* BeOS */ -#define __SIZE_T__ /* Cray Unicos/Mk */ -#define _SIZE_T -#define _SYS_SIZE_T_H -#define _T_SIZE_ -#define _T_SIZE -#define __SIZE_T -#define _SIZE_T_ -#define _BSD_SIZE_T_ -#define _SIZE_T_DEFINED_ -#define _SIZE_T_DEFINED -#define _BSD_SIZE_T_DEFINED_ /* Darwin */ -#define _SIZE_T_DECLARED /* FreeBSD 5 */ -#define ___int_size_t_h -#define _GCC_SIZE_T -#define _SIZET_ -#if (defined (__FreeBSD__) && (__FreeBSD__ >= 5)) \ - || defined(__DragonFly__) \ - || defined(__FreeBSD_kernel__) -/* __size_t is a typedef on FreeBSD 5, must not trash it. */ -#elif defined (__VMS__) -/* __size_t is also a typedef on VMS. */ -#else -#define __size_t -#endif -#ifndef __SIZE_TYPE__ -#define __SIZE_TYPE__ long unsigned int -#endif -#if !(defined (__GNUG__) && defined (size_t)) -typedef __SIZE_TYPE__ size_t; -#ifdef __BEOS__ -typedef long ssize_t; -#endif /* __BEOS__ */ -#endif /* !(defined (__GNUG__) && defined (size_t)) */ -#endif /* __size_t */ -#endif /* _SIZET_ */ -#endif /* _GCC_SIZE_T */ -#endif /* ___int_size_t_h */ -#endif /* _SIZE_T_DECLARED */ -#endif /* _BSD_SIZE_T_DEFINED_ */ -#endif /* _SIZE_T_DEFINED */ -#endif /* _SIZE_T_DEFINED_ */ -#endif /* _BSD_SIZE_T_ */ -#endif /* _SIZE_T_ */ -#endif /* __SIZE_T */ -#endif /* _T_SIZE */ -#endif /* _T_SIZE_ */ -#endif /* _SYS_SIZE_T_H */ -#endif /* _SIZE_T */ -#endif /* __SIZE_T__ */ -#endif /* __size_t__ */ -#undef __need_size_t -#endif /* _STDDEF_H or __need_size_t. */ - - -/* Wide character type. - Locale-writers should change this as necessary to - be big enough to hold unique values not between 0 and 127, - and not (wchar_t) -1, for each defined multibyte character. */ - -/* Define this type if we are doing the whole job, - or if we want this type in particular. */ -#if defined (_STDDEF_H) || defined (__need_wchar_t) -#ifndef __wchar_t__ /* BeOS */ -#ifndef __WCHAR_T__ /* Cray Unicos/Mk */ -#ifndef _WCHAR_T -#ifndef _T_WCHAR_ -#ifndef _T_WCHAR -#ifndef __WCHAR_T -#ifndef _WCHAR_T_ -#ifndef _BSD_WCHAR_T_ -#ifndef _BSD_WCHAR_T_DEFINED_ /* Darwin */ -#ifndef _BSD_RUNE_T_DEFINED_ /* Darwin */ -#ifndef _WCHAR_T_DECLARED /* FreeBSD 5 */ -#ifndef _WCHAR_T_DEFINED_ -#ifndef _WCHAR_T_DEFINED -#ifndef _WCHAR_T_H -#ifndef ___int_wchar_t_h -#ifndef __INT_WCHAR_T_H -#ifndef _GCC_WCHAR_T -#define __wchar_t__ /* BeOS */ -#define __WCHAR_T__ /* Cray Unicos/Mk */ -#define _WCHAR_T -#define _T_WCHAR_ -#define _T_WCHAR -#define __WCHAR_T -#define _WCHAR_T_ -#define _BSD_WCHAR_T_ -#define _WCHAR_T_DEFINED_ -#define _WCHAR_T_DEFINED -#define _WCHAR_T_H -#define ___int_wchar_t_h -#define __INT_WCHAR_T_H -#define _GCC_WCHAR_T -#define _WCHAR_T_DECLARED - -/* On BSD/386 1.1, at least, machine/ansi.h defines _BSD_WCHAR_T_ - instead of _WCHAR_T_, and _BSD_RUNE_T_ (which, unlike the other - symbols in the _FOO_T_ family, stays defined even after its - corresponding type is defined). If we define wchar_t, then we - must undef _WCHAR_T_; for BSD/386 1.1 (and perhaps others), if - we undef _WCHAR_T_, then we must also define rune_t, since - headers like runetype.h assume that if machine/ansi.h is included, - and _BSD_WCHAR_T_ is not defined, then rune_t is available. - machine/ansi.h says, "Note that _WCHAR_T_ and _RUNE_T_ must be of - the same type." */ -#ifdef _BSD_WCHAR_T_ -#undef _BSD_WCHAR_T_ -#ifdef _BSD_RUNE_T_ -#if !defined (_ANSI_SOURCE) && !defined (_POSIX_SOURCE) -typedef _BSD_RUNE_T_ rune_t; -#define _BSD_WCHAR_T_DEFINED_ -#define _BSD_RUNE_T_DEFINED_ /* Darwin */ -#if defined (__FreeBSD__) && (__FreeBSD__ < 5) -/* Why is this file so hard to maintain properly? In contrast to - the comment above regarding BSD/386 1.1, on FreeBSD for as long - as the symbol has existed, _BSD_RUNE_T_ must not stay defined or - redundant typedefs will occur when stdlib.h is included after this file. */ -#undef _BSD_RUNE_T_ -#endif -#endif -#endif -#endif -/* FreeBSD 5 can't be handled well using "traditional" logic above - since it no longer defines _BSD_RUNE_T_ yet still desires to export - rune_t in some cases... */ -#if defined (__FreeBSD__) && (__FreeBSD__ >= 5) -#if !defined (_ANSI_SOURCE) && !defined (_POSIX_SOURCE) -#if __BSD_VISIBLE -#ifndef _RUNE_T_DECLARED -typedef __rune_t rune_t; -#define _RUNE_T_DECLARED -#endif -#endif -#endif -#endif - -#ifndef __WCHAR_TYPE__ -#define __WCHAR_TYPE__ int -#endif -#ifndef __cplusplus -typedef __WCHAR_TYPE__ wchar_t; -#endif -#endif -#endif -#endif -#endif -#endif -#endif -#endif /* _WCHAR_T_DECLARED */ -#endif /* _BSD_RUNE_T_DEFINED_ */ -#endif -#endif -#endif -#endif -#endif -#endif -#endif -#endif /* __WCHAR_T__ */ -#endif /* __wchar_t__ */ -#undef __need_wchar_t -#endif /* _STDDEF_H or __need_wchar_t. */ - -#if defined (__need_wint_t) -#ifndef _WINT_T -#define _WINT_T - -#ifndef __WINT_TYPE__ -#define __WINT_TYPE__ unsigned int -#endif -typedef __WINT_TYPE__ wint_t; -#endif -#undef __need_wint_t -#endif - -/* In 4.3bsd-net2, leave these undefined to indicate that size_t, etc. - are already defined. */ -/* BSD/OS 3.1 and FreeBSD [23].x require the MACHINE_ANSI_H check here. */ -/* NetBSD 5 requires the I386_ANSI_H and X86_64_ANSI_H checks here. */ -#if defined(_ANSI_H_) || defined(_MACHINE_ANSI_H_) || defined(_X86_64_ANSI_H_) || defined(_I386_ANSI_H_) -/* The references to _GCC_PTRDIFF_T_, _GCC_SIZE_T_, and _GCC_WCHAR_T_ - are probably typos and should be removed before 2.8 is released. */ -#ifdef _GCC_PTRDIFF_T_ -#undef _PTRDIFF_T_ -#undef _BSD_PTRDIFF_T_ -#endif -#ifdef _GCC_SIZE_T_ -#undef _SIZE_T_ -#undef _BSD_SIZE_T_ -#endif -#ifdef _GCC_WCHAR_T_ -#undef _WCHAR_T_ -#undef _BSD_WCHAR_T_ -#endif -/* The following ones are the real ones. */ -#ifdef _GCC_PTRDIFF_T -#undef _PTRDIFF_T_ -#undef _BSD_PTRDIFF_T_ -#endif -#ifdef _GCC_SIZE_T -#undef _SIZE_T_ -#undef _BSD_SIZE_T_ -#endif -#ifdef _GCC_WCHAR_T -#undef _WCHAR_T_ -#undef _BSD_WCHAR_T_ -#endif -#endif /* _ANSI_H_ || _MACHINE_ANSI_H_ || _X86_64_ANSI_H_ || _I386_ANSI_H_ */ - -#endif /* __sys_stdtypes_h */ - -/* A null pointer constant. */ - -#if defined (_STDDEF_H) || defined (__need_NULL) -#undef NULL /* in case has defined it. */ -#ifdef __GNUG__ -#define NULL __null -#else /* G++ */ -#ifndef __cplusplus -#define NULL ((void *)0) -#else /* C++ */ -#define NULL 0 -#endif /* C++ */ -#endif /* G++ */ -#endif /* NULL not defined and or need NULL. */ -#undef __need_NULL - -#ifdef _STDDEF_H - -/* Offset of member MEMBER in a struct of type TYPE. */ -#define offsetof(TYPE, MEMBER) __builtin_offsetof (TYPE, MEMBER) - -#if (defined (__STDC_VERSION__) && __STDC_VERSION__ >= 201112L) \ - || (defined(__cplusplus) && __cplusplus >= 201103L) -#ifndef _GCC_MAX_ALIGN_T -#define _GCC_MAX_ALIGN_T -/* Type whose alignment is supported in every context and is at least - as great as that of any standard type not using alignment - specifiers. */ -typedef struct { - long long __max_align_ll __attribute__((__aligned__(__alignof__(long long)))); - long double __max_align_ld __attribute__((__aligned__(__alignof__(long double)))); -} max_align_t; -#endif -#endif /* C11 or C++11. */ - -#if defined(__cplusplus) && __cplusplus >= 201103L -#ifndef _GXX_NULLPTR_T -#define _GXX_NULLPTR_T - typedef decltype(nullptr) nullptr_t; -#endif -#endif /* C++11. */ - -#endif /* _STDDEF_H was defined this time */ - -#endif /* !_STDDEF_H && !_STDDEF_H_ && !_ANSI_STDDEF_H && !__STDDEF_H__ - || __need_XXX was not defined before */ diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/include/stdfix-gcc.h b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/include/stdfix-gcc.h deleted file mode 100644 index 5429fb8..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/include/stdfix-gcc.h +++ /dev/null @@ -1,204 +0,0 @@ -/* Copyright (C) 2007-2015 Free Software Foundation, Inc. - -This file is part of GCC. - -GCC is free software; you can redistribute it and/or modify -it under the terms of the GNU General Public License as published by -the Free Software Foundation; either version 3, or (at your option) -any later version. - -GCC is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU General Public License for more details. - -Under Section 7 of GPL version 3, you are granted additional -permissions described in the GCC Runtime Library Exception, version -3.1, as published by the Free Software Foundation. - -You should have received a copy of the GNU General Public License and -a copy of the GCC Runtime Library Exception along with this program; -see the files COPYING3 and COPYING.RUNTIME respectively. If not, see -. */ - -/* ISO/IEC JTC1 SC22 WG14 N1169 - * Date: 2006-04-04 - * ISO/IEC TR 18037 - * Programming languages - C - Extensions to support embedded processors - */ - -#ifndef _STDFIX_H -#define _STDFIX_H - -/* 7.18a.1 Introduction. */ - -#undef fract -#undef accum -#undef sat -#define fract _Fract -#define accum _Accum -#define sat _Sat - -/* 7.18a.3 Precision macros. */ - -#undef SFRACT_FBIT -#undef SFRACT_MIN -#undef SFRACT_MAX -#undef SFRACT_EPSILON -#define SFRACT_FBIT __SFRACT_FBIT__ -#define SFRACT_MIN __SFRACT_MIN__ -#define SFRACT_MAX __SFRACT_MAX__ -#define SFRACT_EPSILON __SFRACT_EPSILON__ - -#undef USFRACT_FBIT -#undef USFRACT_MIN -#undef USFRACT_MAX -#undef USFRACT_EPSILON -#define USFRACT_FBIT __USFRACT_FBIT__ -#define USFRACT_MIN __USFRACT_MIN__ /* GCC extension. */ -#define USFRACT_MAX __USFRACT_MAX__ -#define USFRACT_EPSILON __USFRACT_EPSILON__ - -#undef FRACT_FBIT -#undef FRACT_MIN -#undef FRACT_MAX -#undef FRACT_EPSILON -#define FRACT_FBIT __FRACT_FBIT__ -#define FRACT_MIN __FRACT_MIN__ -#define FRACT_MAX __FRACT_MAX__ -#define FRACT_EPSILON __FRACT_EPSILON__ - -#undef UFRACT_FBIT -#undef UFRACT_MIN -#undef UFRACT_MAX -#undef UFRACT_EPSILON -#define UFRACT_FBIT __UFRACT_FBIT__ -#define UFRACT_MIN __UFRACT_MIN__ /* GCC extension. */ -#define UFRACT_MAX __UFRACT_MAX__ -#define UFRACT_EPSILON __UFRACT_EPSILON__ - -#undef LFRACT_FBIT -#undef LFRACT_MIN -#undef LFRACT_MAX -#undef LFRACT_EPSILON -#define LFRACT_FBIT __LFRACT_FBIT__ -#define LFRACT_MIN __LFRACT_MIN__ -#define LFRACT_MAX __LFRACT_MAX__ -#define LFRACT_EPSILON __LFRACT_EPSILON__ - -#undef ULFRACT_FBIT -#undef ULFRACT_MIN -#undef ULFRACT_MAX -#undef ULFRACT_EPSILON -#define ULFRACT_FBIT __ULFRACT_FBIT__ -#define ULFRACT_MIN __ULFRACT_MIN__ /* GCC extension. */ -#define ULFRACT_MAX __ULFRACT_MAX__ -#define ULFRACT_EPSILON __ULFRACT_EPSILON__ - -#undef LLFRACT_FBIT -#undef LLFRACT_MIN -#undef LLFRACT_MAX -#undef LLFRACT_EPSILON -#define LLFRACT_FBIT __LLFRACT_FBIT__ /* GCC extension. */ -#define LLFRACT_MIN __LLFRACT_MIN__ /* GCC extension. */ -#define LLFRACT_MAX __LLFRACT_MAX__ /* GCC extension. */ -#define LLFRACT_EPSILON __LLFRACT_EPSILON__ /* GCC extension. */ - -#undef ULLFRACT_FBIT -#undef ULLFRACT_MIN -#undef ULLFRACT_MAX -#undef ULLFRACT_EPSILON -#define ULLFRACT_FBIT __ULLFRACT_FBIT__ /* GCC extension. */ -#define ULLFRACT_MIN __ULLFRACT_MIN__ /* GCC extension. */ -#define ULLFRACT_MAX __ULLFRACT_MAX__ /* GCC extension. */ -#define ULLFRACT_EPSILON __ULLFRACT_EPSILON__ /* GCC extension. */ - -#undef SACCUM_FBIT -#undef SACCUM_IBIT -#undef SACCUM_MIN -#undef SACCUM_MAX -#undef SACCUM_EPSILON -#define SACCUM_FBIT __SACCUM_FBIT__ -#define SACCUM_IBIT __SACCUM_IBIT__ -#define SACCUM_MIN __SACCUM_MIN__ -#define SACCUM_MAX __SACCUM_MAX__ -#define SACCUM_EPSILON __SACCUM_EPSILON__ - -#undef USACCUM_FBIT -#undef USACCUM_IBIT -#undef USACCUM_MIN -#undef USACCUM_MAX -#undef USACCUM_EPSILON -#define USACCUM_FBIT __USACCUM_FBIT__ -#define USACCUM_IBIT __USACCUM_IBIT__ -#define USACCUM_MIN __USACCUM_MIN__ /* GCC extension. */ -#define USACCUM_MAX __USACCUM_MAX__ -#define USACCUM_EPSILON __USACCUM_EPSILON__ - -#undef ACCUM_FBIT -#undef ACCUM_IBIT -#undef ACCUM_MIN -#undef ACCUM_MAX -#undef ACCUM_EPSILON -#define ACCUM_FBIT __ACCUM_FBIT__ -#define ACCUM_IBIT __ACCUM_IBIT__ -#define ACCUM_MIN __ACCUM_MIN__ -#define ACCUM_MAX __ACCUM_MAX__ -#define ACCUM_EPSILON __ACCUM_EPSILON__ - -#undef UACCUM_FBIT -#undef UACCUM_IBIT -#undef UACCUM_MIN -#undef UACCUM_MAX -#undef UACCUM_EPSILON -#define UACCUM_FBIT __UACCUM_FBIT__ -#define UACCUM_IBIT __UACCUM_IBIT__ -#define UACCUM_MIN __UACCUM_MIN__ /* GCC extension. */ -#define UACCUM_MAX __UACCUM_MAX__ -#define UACCUM_EPSILON __UACCUM_EPSILON__ - -#undef LACCUM_FBIT -#undef LACCUM_IBIT -#undef LACCUM_MIN -#undef LACCUM_MAX -#undef LACCUM_EPSILON -#define LACCUM_FBIT __LACCUM_FBIT__ -#define LACCUM_IBIT __LACCUM_IBIT__ -#define LACCUM_MIN __LACCUM_MIN__ -#define LACCUM_MAX __LACCUM_MAX__ -#define LACCUM_EPSILON __LACCUM_EPSILON__ - -#undef ULACCUM_FBIT -#undef ULACCUM_IBIT -#undef ULACCUM_MIN -#undef ULACCUM_MAX -#undef ULACCUM_EPSILON -#define ULACCUM_FBIT __ULACCUM_FBIT__ -#define ULACCUM_IBIT __ULACCUM_IBIT__ -#define ULACCUM_MIN __ULACCUM_MIN__ /* GCC extension. */ -#define ULACCUM_MAX __ULACCUM_MAX__ -#define ULACCUM_EPSILON __ULACCUM_EPSILON__ - -#undef LLACCUM_FBIT -#undef LLACCUM_IBIT -#undef LLACCUM_MIN -#undef LLACCUM_MAX -#undef LLACCUM_EPSILON -#define LLACCUM_FBIT __LLACCUM_FBIT__ /* GCC extension. */ -#define LLACCUM_IBIT __LLACCUM_IBIT__ /* GCC extension. */ -#define LLACCUM_MIN __LLACCUM_MIN__ /* GCC extension. */ -#define LLACCUM_MAX __LLACCUM_MAX__ /* GCC extension. */ -#define LLACCUM_EPSILON __LLACCUM_EPSILON__ /* GCC extension. */ - -#undef ULLACCUM_FBIT -#undef ULLACCUM_IBIT -#undef ULLACCUM_MIN -#undef ULLACCUM_MAX -#undef ULLACCUM_EPSILON -#define ULLACCUM_FBIT __ULLACCUM_FBIT__ /* GCC extension. */ -#define ULLACCUM_IBIT __ULLACCUM_IBIT__ /* GCC extension. */ -#define ULLACCUM_MIN __ULLACCUM_MIN__ /* GCC extension. */ -#define ULLACCUM_MAX __ULLACCUM_MAX__ /* GCC extension. */ -#define ULLACCUM_EPSILON __ULLACCUM_EPSILON__ /* GCC extension. */ - -#endif /* _STDFIX_H */ diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/include/stdfix.h b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/include/stdfix.h deleted file mode 100644 index 51f848b..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/include/stdfix.h +++ /dev/null @@ -1,245 +0,0 @@ -/* Copyright (C) 2007-2015 Free Software Foundation, Inc. - - This file is part of GCC. - - GCC is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3, or (at your option) - any later version. - - GCC is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - Under Section 7 of GPL version 3, you are granted additional - permissions described in the GCC Runtime Library Exception, version - 3.1, as published by the Free Software Foundation. - - You should have received a copy of the GNU General Public License and - a copy of the GCC Runtime Library Exception along with this program; - see the files COPYING3 and COPYING.RUNTIME respectively. If not, see - . */ - -/* ISO/IEC JTC1 SC22 WG14 N1169 - * Date: 2006-04-04 - * ISO/IEC TR 18037 - * Programming languages - C - Extensions to support embedded processors - */ - -#ifndef _AVRGCC_STDFIX_H -#define _AVRGCC_STDFIX_H - -/* 7.18a.1 Introduction. */ -/* 7.18a.3 Precision macros. */ - -#include - - -#if __SIZEOF_INT__ == 2 - -typedef signed char int_hr_t; -typedef unsigned char uint_uhr_t; - -typedef short int int_r_t; -typedef short unsigned int uint_ur_t; - -typedef short int int_hk_t; -typedef short unsigned int uint_uhk_t; - -typedef long int int_lr_t; -typedef long unsigned int uint_ulr_t; - -typedef long int int_k_t; -typedef long unsigned int uint_uk_t; - -typedef long long int int_llr_t; -typedef long long unsigned int uint_ullr_t; - -typedef long long int int_lk_t; -typedef long long unsigned int uint_ulk_t; - -typedef long long int int_llk_t; -typedef long long unsigned int uint_ullk_t; - -#elif __SIZEOF_INT__ == 1 /* -mint8 */ - -typedef signed char int_hr_t; -typedef unsigned char uint_uhr_t; - -typedef long int int_r_t; -typedef long unsigned int uint_ur_t; - -typedef long int int_hk_t; -typedef long unsigned int uint_uhk_t; - -typedef long long int int_lr_t; -typedef long long unsigned int uint_ulr_t; - -typedef long long int int_k_t; -typedef long long unsigned int uint_uk_t; - -#endif /* __SIZEOF_INT__ == 1, 2 */ - - -/* 7.18a.6 The fixed-point intrinsic functions. */ - - -/* 7.18a.6.2 The fixed-point absolute value functions. */ - -#define abshr __builtin_avr_abshr -#define absr __builtin_avr_absr -#define abslr __builtin_avr_abslr - -#define abshk __builtin_avr_abshk -#define absk __builtin_avr_absk - -#if __SIZEOF_INT__ == 2 - -#define abslk __builtin_avr_abslk -#define absllr __builtin_avr_absllr /* GCC Extension */ -#define absllk __builtin_avr_absllk /* GCC Extension */ - -#endif /* sizeof (int) == 2 */ - - -/* 7.18a.6.3 The fixed-point round functions. */ - -/* The Embedded-C paper specifies results only for rounding points - - 0 < RP < FBIT - - As an extension, the following functions work as expected - with rounding points - - -IBIT < RP < FBIT - - For example, rounding an accum with a rounding point of -1 will - result in an even integer value. */ - -#define roundhr __builtin_avr_roundhr -#define roundr __builtin_avr_roundr -#define roundlr __builtin_avr_roundlr - -#define rounduhr __builtin_avr_rounduhr -#define roundur __builtin_avr_roundur -#define roundulr __builtin_avr_roundulr - -#define roundhk __builtin_avr_roundhk -#define roundk __builtin_avr_roundk - -#define rounduhk __builtin_avr_rounduhk -#define rounduk __builtin_avr_rounduk - -#if __SIZEOF_INT__ == 2 - -#define roundlk __builtin_avr_roundlk -#define roundulk __builtin_avr_roundulk -#define roundllr __builtin_avr_roundllr /* GCC Extension */ -#define roundullr __builtin_avr_roundullr /* GCC Extension */ -#define roundllk __builtin_avr_roundllk /* GCC Extension */ -#define roundullk __builtin_avr_roundullk /* GCC Extension */ - -#endif /* sizeof (int) == 2 */ - - -/* 7.18a.6.4 The fixed-point bit countls functions. */ - -#define countlshr __builtin_avr_countlshr -#define countlsr __builtin_avr_countlsr -#define countlslr __builtin_avr_countlslr - -#define countlsuhr __builtin_avr_countlsuhr -#define countlsur __builtin_avr_countlsur -#define countlsulr __builtin_avr_countlsulr - -#define countlshk __builtin_avr_countlshk -#define countlsk __builtin_avr_countlsk - -#define countlsuhk __builtin_avr_countlsuhk -#define countlsuk __builtin_avr_countlsuk - -#if __SIZEOF_INT__ == 2 - -#define countlslk __builtin_avr_countlslk -#define countlsulk __builtin_avr_countlsulk -#define countlsllr __builtin_avr_countlsllr /* GCC Extension */ -#define countlsullr __builtin_avr_countlsullr /* GCC Extension */ -#define countlsllk __builtin_avr_countlsllk /* GCC Extension */ -#define countlsullk __builtin_avr_countlsullk /* GCC Extension */ - -#endif /* sizeof (int) == 2 */ - - -/* 7.18a.6.5 The bitwise fixed-point to integer conversion functions. */ - -#define bitshr __builtin_avr_bitshr -#define bitsr __builtin_avr_bitsr -#define bitslr __builtin_avr_bitslr - -#define bitsuhr __builtin_avr_bitsuhr -#define bitsur __builtin_avr_bitsur -#define bitsulr __builtin_avr_bitsulr - -#define bitshk __builtin_avr_bitshk -#define bitsk __builtin_avr_bitsk - -#define bitsuhk __builtin_avr_bitsuhk -#define bitsuk __builtin_avr_bitsuk - -#if __SIZEOF_INT__ == 2 - -#define bitslk __builtin_avr_bitslk -#define bitsulk __builtin_avr_bitsulk -#define bitsllr __builtin_avr_bitsllr /* GCC Extension */ -#define bitsullr __builtin_avr_bitsullr /* GCC Extension */ -#define bitsllk __builtin_avr_bitsllk /* GCC Extension */ -#define bitsullk __builtin_avr_bitsullk /* GCC Extension */ - -#endif /* sizeof (int) == 2 */ - - -/* 7.18a.6.6 The bitwise integer to fixed-point conversion functions. */ - -#define hrbits __builtin_avr_hrbits -#define rbits __builtin_avr_rbits -#define lrbits __builtin_avr_lrbits - -#define uhrbits __builtin_avr_uhrbits -#define urbits __builtin_avr_urbits -#define ulrbits __builtin_avr_ulrbits - -#define hkbits __builtin_avr_hkbits -#define kbits __builtin_avr_kbits - -#define uhkbits __builtin_avr_uhkbits -#define ukbits __builtin_avr_ukbits - -#if __SIZEOF_INT__ == 2 - -#define lkbits __builtin_avr_lkbits -#define ulkbits __builtin_avr_ulkbits -#define llrbits __builtin_avr_llrbits /* GCC Extension */ -#define ullrbits __builtin_avr_ullrbits /* GCC Extension */ -#define llkbits __builtin_avr_llkbits /* GCC Extension */ -#define ullkbits __builtin_avr_ullkbits /* GCC Extension */ - -#endif /* sizeof (int) == 2 */ - - -/* 7.18a.6.7 Type-generic fixed-point functions. */ - -#define absfx __builtin_avr_absfx -#define roundfx __builtin_avr_roundfx -#define countlsfx __builtin_avr_countlsfx - - -/* Hook in stuff from AVR-Libc. */ - -#if (defined (__WITH_AVRLIBC__) \ - && defined (__has_include) \ - && __has_include ()) -#include -#endif - -#endif /* _AVRGCC_STDFIX_H */ diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/include/stdint-gcc.h b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/include/stdint-gcc.h deleted file mode 100644 index 9129427..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/include/stdint-gcc.h +++ /dev/null @@ -1,263 +0,0 @@ -/* Copyright (C) 2008-2015 Free Software Foundation, Inc. - -This file is part of GCC. - -GCC is free software; you can redistribute it and/or modify -it under the terms of the GNU General Public License as published by -the Free Software Foundation; either version 3, or (at your option) -any later version. - -GCC is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU General Public License for more details. - -Under Section 7 of GPL version 3, you are granted additional -permissions described in the GCC Runtime Library Exception, version -3.1, as published by the Free Software Foundation. - -You should have received a copy of the GNU General Public License and -a copy of the GCC Runtime Library Exception along with this program; -see the files COPYING3 and COPYING.RUNTIME respectively. If not, see -. */ - -/* - * ISO C Standard: 7.18 Integer types - */ - -#ifndef _GCC_STDINT_H -#define _GCC_STDINT_H - -/* 7.8.1.1 Exact-width integer types */ - -#ifdef __INT8_TYPE__ -typedef __INT8_TYPE__ int8_t; -#endif -#ifdef __INT16_TYPE__ -typedef __INT16_TYPE__ int16_t; -#endif -#ifdef __INT32_TYPE__ -typedef __INT32_TYPE__ int32_t; -#endif -#ifdef __INT64_TYPE__ -typedef __INT64_TYPE__ int64_t; -#endif -#ifdef __UINT8_TYPE__ -typedef __UINT8_TYPE__ uint8_t; -#endif -#ifdef __UINT16_TYPE__ -typedef __UINT16_TYPE__ uint16_t; -#endif -#ifdef __UINT32_TYPE__ -typedef __UINT32_TYPE__ uint32_t; -#endif -#ifdef __UINT64_TYPE__ -typedef __UINT64_TYPE__ uint64_t; -#endif - -/* 7.8.1.2 Minimum-width integer types */ - -typedef __INT_LEAST8_TYPE__ int_least8_t; -typedef __INT_LEAST16_TYPE__ int_least16_t; -typedef __INT_LEAST32_TYPE__ int_least32_t; -typedef __INT_LEAST64_TYPE__ int_least64_t; -typedef __UINT_LEAST8_TYPE__ uint_least8_t; -typedef __UINT_LEAST16_TYPE__ uint_least16_t; -typedef __UINT_LEAST32_TYPE__ uint_least32_t; -typedef __UINT_LEAST64_TYPE__ uint_least64_t; - -/* 7.8.1.3 Fastest minimum-width integer types */ - -typedef __INT_FAST8_TYPE__ int_fast8_t; -typedef __INT_FAST16_TYPE__ int_fast16_t; -typedef __INT_FAST32_TYPE__ int_fast32_t; -typedef __INT_FAST64_TYPE__ int_fast64_t; -typedef __UINT_FAST8_TYPE__ uint_fast8_t; -typedef __UINT_FAST16_TYPE__ uint_fast16_t; -typedef __UINT_FAST32_TYPE__ uint_fast32_t; -typedef __UINT_FAST64_TYPE__ uint_fast64_t; - -/* 7.8.1.4 Integer types capable of holding object pointers */ - -#ifdef __INTPTR_TYPE__ -typedef __INTPTR_TYPE__ intptr_t; -#endif -#ifdef __UINTPTR_TYPE__ -typedef __UINTPTR_TYPE__ uintptr_t; -#endif - -/* 7.8.1.5 Greatest-width integer types */ - -typedef __INTMAX_TYPE__ intmax_t; -typedef __UINTMAX_TYPE__ uintmax_t; - -#if (!defined __cplusplus || __cplusplus >= 201103L \ - || defined __STDC_LIMIT_MACROS) - -/* 7.18.2 Limits of specified-width integer types */ - -#ifdef __INT8_MAX__ -# undef INT8_MAX -# define INT8_MAX __INT8_MAX__ -# undef INT8_MIN -# define INT8_MIN (-INT8_MAX - 1) -#endif -#ifdef __UINT8_MAX__ -# undef UINT8_MAX -# define UINT8_MAX __UINT8_MAX__ -#endif -#ifdef __INT16_MAX__ -# undef INT16_MAX -# define INT16_MAX __INT16_MAX__ -# undef INT16_MIN -# define INT16_MIN (-INT16_MAX - 1) -#endif -#ifdef __UINT16_MAX__ -# undef UINT16_MAX -# define UINT16_MAX __UINT16_MAX__ -#endif -#ifdef __INT32_MAX__ -# undef INT32_MAX -# define INT32_MAX __INT32_MAX__ -# undef INT32_MIN -# define INT32_MIN (-INT32_MAX - 1) -#endif -#ifdef __UINT32_MAX__ -# undef UINT32_MAX -# define UINT32_MAX __UINT32_MAX__ -#endif -#ifdef __INT64_MAX__ -# undef INT64_MAX -# define INT64_MAX __INT64_MAX__ -# undef INT64_MIN -# define INT64_MIN (-INT64_MAX - 1) -#endif -#ifdef __UINT64_MAX__ -# undef UINT64_MAX -# define UINT64_MAX __UINT64_MAX__ -#endif - -#undef INT_LEAST8_MAX -#define INT_LEAST8_MAX __INT_LEAST8_MAX__ -#undef INT_LEAST8_MIN -#define INT_LEAST8_MIN (-INT_LEAST8_MAX - 1) -#undef UINT_LEAST8_MAX -#define UINT_LEAST8_MAX __UINT_LEAST8_MAX__ -#undef INT_LEAST16_MAX -#define INT_LEAST16_MAX __INT_LEAST16_MAX__ -#undef INT_LEAST16_MIN -#define INT_LEAST16_MIN (-INT_LEAST16_MAX - 1) -#undef UINT_LEAST16_MAX -#define UINT_LEAST16_MAX __UINT_LEAST16_MAX__ -#undef INT_LEAST32_MAX -#define INT_LEAST32_MAX __INT_LEAST32_MAX__ -#undef INT_LEAST32_MIN -#define INT_LEAST32_MIN (-INT_LEAST32_MAX - 1) -#undef UINT_LEAST32_MAX -#define UINT_LEAST32_MAX __UINT_LEAST32_MAX__ -#undef INT_LEAST64_MAX -#define INT_LEAST64_MAX __INT_LEAST64_MAX__ -#undef INT_LEAST64_MIN -#define INT_LEAST64_MIN (-INT_LEAST64_MAX - 1) -#undef UINT_LEAST64_MAX -#define UINT_LEAST64_MAX __UINT_LEAST64_MAX__ - -#undef INT_FAST8_MAX -#define INT_FAST8_MAX __INT_FAST8_MAX__ -#undef INT_FAST8_MIN -#define INT_FAST8_MIN (-INT_FAST8_MAX - 1) -#undef UINT_FAST8_MAX -#define UINT_FAST8_MAX __UINT_FAST8_MAX__ -#undef INT_FAST16_MAX -#define INT_FAST16_MAX __INT_FAST16_MAX__ -#undef INT_FAST16_MIN -#define INT_FAST16_MIN (-INT_FAST16_MAX - 1) -#undef UINT_FAST16_MAX -#define UINT_FAST16_MAX __UINT_FAST16_MAX__ -#undef INT_FAST32_MAX -#define INT_FAST32_MAX __INT_FAST32_MAX__ -#undef INT_FAST32_MIN -#define INT_FAST32_MIN (-INT_FAST32_MAX - 1) -#undef UINT_FAST32_MAX -#define UINT_FAST32_MAX __UINT_FAST32_MAX__ -#undef INT_FAST64_MAX -#define INT_FAST64_MAX __INT_FAST64_MAX__ -#undef INT_FAST64_MIN -#define INT_FAST64_MIN (-INT_FAST64_MAX - 1) -#undef UINT_FAST64_MAX -#define UINT_FAST64_MAX __UINT_FAST64_MAX__ - -#ifdef __INTPTR_MAX__ -# undef INTPTR_MAX -# define INTPTR_MAX __INTPTR_MAX__ -# undef INTPTR_MIN -# define INTPTR_MIN (-INTPTR_MAX - 1) -#endif -#ifdef __UINTPTR_MAX__ -# undef UINTPTR_MAX -# define UINTPTR_MAX __UINTPTR_MAX__ -#endif - -#undef INTMAX_MAX -#define INTMAX_MAX __INTMAX_MAX__ -#undef INTMAX_MIN -#define INTMAX_MIN (-INTMAX_MAX - 1) -#undef UINTMAX_MAX -#define UINTMAX_MAX __UINTMAX_MAX__ - -/* 7.18.3 Limits of other integer types */ - -#undef PTRDIFF_MAX -#define PTRDIFF_MAX __PTRDIFF_MAX__ -#undef PTRDIFF_MIN -#define PTRDIFF_MIN (-PTRDIFF_MAX - 1) - -#undef SIG_ATOMIC_MAX -#define SIG_ATOMIC_MAX __SIG_ATOMIC_MAX__ -#undef SIG_ATOMIC_MIN -#define SIG_ATOMIC_MIN __SIG_ATOMIC_MIN__ - -#undef SIZE_MAX -#define SIZE_MAX __SIZE_MAX__ - -#undef WCHAR_MAX -#define WCHAR_MAX __WCHAR_MAX__ -#undef WCHAR_MIN -#define WCHAR_MIN __WCHAR_MIN__ - -#undef WINT_MAX -#define WINT_MAX __WINT_MAX__ -#undef WINT_MIN -#define WINT_MIN __WINT_MIN__ - -#endif /* (!defined __cplusplus || __cplusplus >= 201103L - || defined __STDC_LIMIT_MACROS) */ - -#if (!defined __cplusplus || __cplusplus >= 201103L \ - || defined __STDC_CONSTANT_MACROS) - -#undef INT8_C -#define INT8_C(c) __INT8_C(c) -#undef INT16_C -#define INT16_C(c) __INT16_C(c) -#undef INT32_C -#define INT32_C(c) __INT32_C(c) -#undef INT64_C -#define INT64_C(c) __INT64_C(c) -#undef UINT8_C -#define UINT8_C(c) __UINT8_C(c) -#undef UINT16_C -#define UINT16_C(c) __UINT16_C(c) -#undef UINT32_C -#define UINT32_C(c) __UINT32_C(c) -#undef UINT64_C -#define UINT64_C(c) __UINT64_C(c) -#undef INTMAX_C -#define INTMAX_C(c) __INTMAX_C(c) -#undef UINTMAX_C -#define UINTMAX_C(c) __UINTMAX_C(c) - -#endif /* (!defined __cplusplus || __cplusplus >= 201103L - || defined __STDC_CONSTANT_MACROS) */ - -#endif /* _GCC_STDINT_H */ diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/include/stdint.h b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/include/stdint.h deleted file mode 100644 index 83b6f70..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/include/stdint.h +++ /dev/null @@ -1,14 +0,0 @@ -#ifndef _GCC_WRAP_STDINT_H -#if __STDC_HOSTED__ -# if defined __cplusplus && __cplusplus >= 201103L -# undef __STDC_LIMIT_MACROS -# define __STDC_LIMIT_MACROS -# undef __STDC_CONSTANT_MACROS -# define __STDC_CONSTANT_MACROS -# endif -# include_next -#else -# include "stdint-gcc.h" -#endif -#define _GCC_WRAP_STDINT_H -#endif diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/include/stdnoreturn.h b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/include/stdnoreturn.h deleted file mode 100644 index 8137eee..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/include/stdnoreturn.h +++ /dev/null @@ -1,35 +0,0 @@ -/* Copyright (C) 2011-2015 Free Software Foundation, Inc. - -This file is part of GCC. - -GCC is free software; you can redistribute it and/or modify -it under the terms of the GNU General Public License as published by -the Free Software Foundation; either version 3, or (at your option) -any later version. - -GCC is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU General Public License for more details. - -Under Section 7 of GPL version 3, you are granted additional -permissions described in the GCC Runtime Library Exception, version -3.1, as published by the Free Software Foundation. - -You should have received a copy of the GNU General Public License and -a copy of the GCC Runtime Library Exception along with this program; -see the files COPYING3 and COPYING.RUNTIME respectively. If not, see -. */ - -/* ISO C1X: 7.23 _Noreturn . */ - -#ifndef _STDNORETURN_H -#define _STDNORETURN_H - -#ifndef __cplusplus - -#define noreturn _Noreturn - -#endif - -#endif /* stdnoreturn.h */ diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/include/unwind.h b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/include/unwind.h deleted file mode 100644 index a51ffd6..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/include/unwind.h +++ /dev/null @@ -1,293 +0,0 @@ -/* Exception handling and frame unwind runtime interface routines. - Copyright (C) 2001-2015 Free Software Foundation, Inc. - - This file is part of GCC. - - GCC is free software; you can redistribute it and/or modify it - under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3, or (at your option) - any later version. - - GCC is distributed in the hope that it will be useful, but WITHOUT - ANY WARRANTY; without even the implied warranty of MERCHANTABILITY - or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public - License for more details. - - Under Section 7 of GPL version 3, you are granted additional - permissions described in the GCC Runtime Library Exception, version - 3.1, as published by the Free Software Foundation. - - You should have received a copy of the GNU General Public License and - a copy of the GCC Runtime Library Exception along with this program; - see the files COPYING3 and COPYING.RUNTIME respectively. If not, see - . */ - -/* This is derived from the C++ ABI for IA-64. Where we diverge - for cross-architecture compatibility are noted with "@@@". */ - -#ifndef _UNWIND_H -#define _UNWIND_H - -#if defined (__SEH__) && !defined (__USING_SJLJ_EXCEPTIONS__) -/* Only for _GCC_specific_handler. */ -#include -#endif - -#ifndef HIDE_EXPORTS -#pragma GCC visibility push(default) -#endif - -#ifdef __cplusplus -extern "C" { -#endif - -/* Level 1: Base ABI */ - -/* @@@ The IA-64 ABI uses uint64 throughout. Most places this is - inefficient for 32-bit and smaller machines. */ -typedef unsigned _Unwind_Word __attribute__((__mode__(__unwind_word__))); -typedef signed _Unwind_Sword __attribute__((__mode__(__unwind_word__))); -#if defined(__ia64__) && defined(__hpux__) -typedef unsigned _Unwind_Ptr __attribute__((__mode__(__word__))); -#else -typedef unsigned _Unwind_Ptr __attribute__((__mode__(__pointer__))); -#endif -typedef unsigned _Unwind_Internal_Ptr __attribute__((__mode__(__pointer__))); - -/* @@@ The IA-64 ABI uses a 64-bit word to identify the producer and - consumer of an exception. We'll go along with this for now even on - 32-bit machines. We'll need to provide some other option for - 16-bit machines and for machines with > 8 bits per byte. */ -typedef unsigned _Unwind_Exception_Class __attribute__((__mode__(__DI__))); - -/* The unwind interface uses reason codes in several contexts to - identify the reasons for failures or other actions. */ -typedef enum -{ - _URC_NO_REASON = 0, - _URC_FOREIGN_EXCEPTION_CAUGHT = 1, - _URC_FATAL_PHASE2_ERROR = 2, - _URC_FATAL_PHASE1_ERROR = 3, - _URC_NORMAL_STOP = 4, - _URC_END_OF_STACK = 5, - _URC_HANDLER_FOUND = 6, - _URC_INSTALL_CONTEXT = 7, - _URC_CONTINUE_UNWIND = 8 -} _Unwind_Reason_Code; - - -/* The unwind interface uses a pointer to an exception header object - as its representation of an exception being thrown. In general, the - full representation of an exception object is language- and - implementation-specific, but it will be prefixed by a header - understood by the unwind interface. */ - -struct _Unwind_Exception; - -typedef void (*_Unwind_Exception_Cleanup_Fn) (_Unwind_Reason_Code, - struct _Unwind_Exception *); - -struct _Unwind_Exception -{ - _Unwind_Exception_Class exception_class; - _Unwind_Exception_Cleanup_Fn exception_cleanup; - -#if !defined (__USING_SJLJ_EXCEPTIONS__) && defined (__SEH__) - _Unwind_Word private_[6]; -#else - _Unwind_Word private_1; - _Unwind_Word private_2; -#endif - - /* @@@ The IA-64 ABI says that this structure must be double-word aligned. - Taking that literally does not make much sense generically. Instead we - provide the maximum alignment required by any type for the machine. */ -} __attribute__((__aligned__)); - - -/* The ACTIONS argument to the personality routine is a bitwise OR of one - or more of the following constants. */ -typedef int _Unwind_Action; - -#define _UA_SEARCH_PHASE 1 -#define _UA_CLEANUP_PHASE 2 -#define _UA_HANDLER_FRAME 4 -#define _UA_FORCE_UNWIND 8 -#define _UA_END_OF_STACK 16 - -/* The target can override this macro to define any back-end-specific - attributes required for the lowest-level stack frame. */ -#ifndef LIBGCC2_UNWIND_ATTRIBUTE -#define LIBGCC2_UNWIND_ATTRIBUTE -#endif - -/* This is an opaque type used to refer to a system-specific data - structure used by the system unwinder. This context is created and - destroyed by the system, and passed to the personality routine - during unwinding. */ -struct _Unwind_Context; - -/* Raise an exception, passing along the given exception object. */ -extern _Unwind_Reason_Code LIBGCC2_UNWIND_ATTRIBUTE -_Unwind_RaiseException (struct _Unwind_Exception *); - -/* Raise an exception for forced unwinding. */ - -typedef _Unwind_Reason_Code (*_Unwind_Stop_Fn) - (int, _Unwind_Action, _Unwind_Exception_Class, - struct _Unwind_Exception *, struct _Unwind_Context *, void *); - -extern _Unwind_Reason_Code LIBGCC2_UNWIND_ATTRIBUTE -_Unwind_ForcedUnwind (struct _Unwind_Exception *, _Unwind_Stop_Fn, void *); - -/* Helper to invoke the exception_cleanup routine. */ -extern void _Unwind_DeleteException (struct _Unwind_Exception *); - -/* Resume propagation of an existing exception. This is used after - e.g. executing cleanup code, and not to implement rethrowing. */ -extern void LIBGCC2_UNWIND_ATTRIBUTE -_Unwind_Resume (struct _Unwind_Exception *); - -/* @@@ Resume propagation of a FORCE_UNWIND exception, or to rethrow - a normal exception that was handled. */ -extern _Unwind_Reason_Code LIBGCC2_UNWIND_ATTRIBUTE -_Unwind_Resume_or_Rethrow (struct _Unwind_Exception *); - -/* @@@ Use unwind data to perform a stack backtrace. The trace callback - is called for every stack frame in the call chain, but no cleanup - actions are performed. */ -typedef _Unwind_Reason_Code (*_Unwind_Trace_Fn) - (struct _Unwind_Context *, void *); - -extern _Unwind_Reason_Code LIBGCC2_UNWIND_ATTRIBUTE -_Unwind_Backtrace (_Unwind_Trace_Fn, void *); - -/* These functions are used for communicating information about the unwind - context (i.e. the unwind descriptors and the user register state) between - the unwind library and the personality routine and landing pad. Only - selected registers may be manipulated. */ - -extern _Unwind_Word _Unwind_GetGR (struct _Unwind_Context *, int); -extern void _Unwind_SetGR (struct _Unwind_Context *, int, _Unwind_Word); - -extern _Unwind_Ptr _Unwind_GetIP (struct _Unwind_Context *); -extern _Unwind_Ptr _Unwind_GetIPInfo (struct _Unwind_Context *, int *); -extern void _Unwind_SetIP (struct _Unwind_Context *, _Unwind_Ptr); - -/* @@@ Retrieve the CFA of the given context. */ -extern _Unwind_Word _Unwind_GetCFA (struct _Unwind_Context *); - -extern void *_Unwind_GetLanguageSpecificData (struct _Unwind_Context *); - -extern _Unwind_Ptr _Unwind_GetRegionStart (struct _Unwind_Context *); - - -/* The personality routine is the function in the C++ (or other language) - runtime library which serves as an interface between the system unwind - library and language-specific exception handling semantics. It is - specific to the code fragment described by an unwind info block, and - it is always referenced via the pointer in the unwind info block, and - hence it has no ABI-specified name. - - Note that this implies that two different C++ implementations can - use different names, and have different contents in the language - specific data area. Moreover, that the language specific data - area contains no version info because name of the function invoked - provides more effective versioning by detecting at link time the - lack of code to handle the different data format. */ - -typedef _Unwind_Reason_Code (*_Unwind_Personality_Fn) - (int, _Unwind_Action, _Unwind_Exception_Class, - struct _Unwind_Exception *, struct _Unwind_Context *); - -/* @@@ The following alternate entry points are for setjmp/longjmp - based unwinding. */ - -struct SjLj_Function_Context; -extern void _Unwind_SjLj_Register (struct SjLj_Function_Context *); -extern void _Unwind_SjLj_Unregister (struct SjLj_Function_Context *); - -extern _Unwind_Reason_Code LIBGCC2_UNWIND_ATTRIBUTE -_Unwind_SjLj_RaiseException (struct _Unwind_Exception *); -extern _Unwind_Reason_Code LIBGCC2_UNWIND_ATTRIBUTE -_Unwind_SjLj_ForcedUnwind (struct _Unwind_Exception *, _Unwind_Stop_Fn, void *); -extern void LIBGCC2_UNWIND_ATTRIBUTE -_Unwind_SjLj_Resume (struct _Unwind_Exception *); -extern _Unwind_Reason_Code LIBGCC2_UNWIND_ATTRIBUTE -_Unwind_SjLj_Resume_or_Rethrow (struct _Unwind_Exception *); - -/* @@@ The following provide access to the base addresses for text - and data-relative addressing in the LDSA. In order to stay link - compatible with the standard ABI for IA-64, we inline these. */ - -#ifdef __ia64__ -#include - -static inline _Unwind_Ptr -_Unwind_GetDataRelBase (struct _Unwind_Context *_C) -{ - /* The GP is stored in R1. */ - return _Unwind_GetGR (_C, 1); -} - -static inline _Unwind_Ptr -_Unwind_GetTextRelBase (struct _Unwind_Context *_C __attribute__ ((__unused__))) -{ - abort (); - return 0; -} - -/* @@@ Retrieve the Backing Store Pointer of the given context. */ -extern _Unwind_Word _Unwind_GetBSP (struct _Unwind_Context *); -#else -extern _Unwind_Ptr _Unwind_GetDataRelBase (struct _Unwind_Context *); -extern _Unwind_Ptr _Unwind_GetTextRelBase (struct _Unwind_Context *); -#endif - -/* @@@ Given an address, return the entry point of the function that - contains it. */ -extern void * _Unwind_FindEnclosingFunction (void *pc); - -#ifndef __SIZEOF_LONG__ - #error "__SIZEOF_LONG__ macro not defined" -#endif - -#ifndef __SIZEOF_POINTER__ - #error "__SIZEOF_POINTER__ macro not defined" -#endif - - -/* leb128 type numbers have a potentially unlimited size. - The target of the following definitions of _sleb128_t and _uleb128_t - is to have efficient data types large enough to hold the leb128 type - numbers used in the unwind code. - Mostly these types will simply be defined to long and unsigned long - except when a unsigned long data type on the target machine is not - capable of storing a pointer. */ - -#if __SIZEOF_LONG__ >= __SIZEOF_POINTER__ - typedef long _sleb128_t; - typedef unsigned long _uleb128_t; -#elif __SIZEOF_LONG_LONG__ >= __SIZEOF_POINTER__ - typedef long long _sleb128_t; - typedef unsigned long long _uleb128_t; -#else -# error "What type shall we use for _sleb128_t?" -#endif - -#if defined (__SEH__) && !defined (__USING_SJLJ_EXCEPTIONS__) -/* Handles the mapping from SEH to GCC interfaces. */ -EXCEPTION_DISPOSITION _GCC_specific_handler (PEXCEPTION_RECORD, void *, - PCONTEXT, PDISPATCHER_CONTEXT, - _Unwind_Personality_Fn); -#endif - -#ifdef __cplusplus -} -#endif - -#ifndef HIDE_EXPORTS -#pragma GCC visibility pop -#endif - -#endif /* unwind.h */ diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/include/varargs.h b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/include/varargs.h deleted file mode 100644 index 4b9803e..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/include/varargs.h +++ /dev/null @@ -1,7 +0,0 @@ -#ifndef _VARARGS_H -#define _VARARGS_H - -#error "GCC no longer implements ." -#error "Revise your code to use ." - -#endif diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/install-tools/fixinc_list b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/install-tools/fixinc_list deleted file mode 100644 index 092bc2b..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/install-tools/fixinc_list +++ /dev/null @@ -1 +0,0 @@ -; diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/install-tools/gsyslimits.h b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/install-tools/gsyslimits.h deleted file mode 100644 index a362802..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/install-tools/gsyslimits.h +++ /dev/null @@ -1,8 +0,0 @@ -/* syslimits.h stands for the system's own limits.h file. - If we can use it ok unmodified, then we install this text. - If fixincludes fixes it, then the fixed version is installed - instead of this text. */ - -#define _GCC_NEXT_LIMITS_H /* tell gcc's limits.h to recurse */ -#include_next -#undef _GCC_NEXT_LIMITS_H diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/install-tools/include/README b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/install-tools/include/README deleted file mode 100644 index 7086a77..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/install-tools/include/README +++ /dev/null @@ -1,14 +0,0 @@ -This README file is copied into the directory for GCC-only header files -when fixincludes is run by the makefile for GCC. - -Many of the files in this directory were automatically edited from the -standard system header files by the fixincludes process. They are -system-specific, and will not work on any other kind of system. They -are also not part of GCC. The reason we have to do this is because -GCC requires ANSI C headers and many vendors supply ANSI-incompatible -headers. - -Because this is an automated process, sometimes headers get "fixed" -that do not, strictly speaking, need a fix. As long as nothing is broken -by the process, it is just an unfortunate collateral inconvenience. -We would like to rectify it, if it is not "too inconvenient". diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/install-tools/include/limits.h b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/install-tools/include/limits.h deleted file mode 100644 index 984302e..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/install-tools/include/limits.h +++ /dev/null @@ -1,126 +0,0 @@ -/* Copyright (C) 1991-2015 Free Software Foundation, Inc. - -This file is part of GCC. - -GCC is free software; you can redistribute it and/or modify it under -the terms of the GNU General Public License as published by the Free -Software Foundation; either version 3, or (at your option) any later -version. - -GCC is distributed in the hope that it will be useful, but WITHOUT ANY -WARRANTY; without even the implied warranty of MERCHANTABILITY or -FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -for more details. - -Under Section 7 of GPL version 3, you are granted additional -permissions described in the GCC Runtime Library Exception, version -3.1, as published by the Free Software Foundation. - -You should have received a copy of the GNU General Public License and -a copy of the GCC Runtime Library Exception along with this program; -see the files COPYING3 and COPYING.RUNTIME respectively. If not, see -. */ - -#ifndef _LIMITS_H___ -#define _LIMITS_H___ - -/* Number of bits in a `char'. */ -#undef CHAR_BIT -#define CHAR_BIT __CHAR_BIT__ - -/* Maximum length of a multibyte character. */ -#ifndef MB_LEN_MAX -#define MB_LEN_MAX 1 -#endif - -/* Minimum and maximum values a `signed char' can hold. */ -#undef SCHAR_MIN -#define SCHAR_MIN (-SCHAR_MAX - 1) -#undef SCHAR_MAX -#define SCHAR_MAX __SCHAR_MAX__ - -/* Maximum value an `unsigned char' can hold. (Minimum is 0). */ -#undef UCHAR_MAX -#if __SCHAR_MAX__ == __INT_MAX__ -# define UCHAR_MAX (SCHAR_MAX * 2U + 1U) -#else -# define UCHAR_MAX (SCHAR_MAX * 2 + 1) -#endif - -/* Minimum and maximum values a `char' can hold. */ -#ifdef __CHAR_UNSIGNED__ -# undef CHAR_MIN -# if __SCHAR_MAX__ == __INT_MAX__ -# define CHAR_MIN 0U -# else -# define CHAR_MIN 0 -# endif -# undef CHAR_MAX -# define CHAR_MAX UCHAR_MAX -#else -# undef CHAR_MIN -# define CHAR_MIN SCHAR_MIN -# undef CHAR_MAX -# define CHAR_MAX SCHAR_MAX -#endif - -/* Minimum and maximum values a `signed short int' can hold. */ -#undef SHRT_MIN -#define SHRT_MIN (-SHRT_MAX - 1) -#undef SHRT_MAX -#define SHRT_MAX __SHRT_MAX__ - -/* Maximum value an `unsigned short int' can hold. (Minimum is 0). */ -#undef USHRT_MAX -#if __SHRT_MAX__ == __INT_MAX__ -# define USHRT_MAX (SHRT_MAX * 2U + 1U) -#else -# define USHRT_MAX (SHRT_MAX * 2 + 1) -#endif - -/* Minimum and maximum values a `signed int' can hold. */ -#undef INT_MIN -#define INT_MIN (-INT_MAX - 1) -#undef INT_MAX -#define INT_MAX __INT_MAX__ - -/* Maximum value an `unsigned int' can hold. (Minimum is 0). */ -#undef UINT_MAX -#define UINT_MAX (INT_MAX * 2U + 1U) - -/* Minimum and maximum values a `signed long int' can hold. - (Same as `int'). */ -#undef LONG_MIN -#define LONG_MIN (-LONG_MAX - 1L) -#undef LONG_MAX -#define LONG_MAX __LONG_MAX__ - -/* Maximum value an `unsigned long int' can hold. (Minimum is 0). */ -#undef ULONG_MAX -#define ULONG_MAX (LONG_MAX * 2UL + 1UL) - -#if defined (__STDC_VERSION__) && __STDC_VERSION__ >= 199901L -/* Minimum and maximum values a `signed long long int' can hold. */ -# undef LLONG_MIN -# define LLONG_MIN (-LLONG_MAX - 1LL) -# undef LLONG_MAX -# define LLONG_MAX __LONG_LONG_MAX__ - -/* Maximum value an `unsigned long long int' can hold. (Minimum is 0). */ -# undef ULLONG_MAX -# define ULLONG_MAX (LLONG_MAX * 2ULL + 1ULL) -#endif - -#if defined (__GNU_LIBRARY__) ? defined (__USE_GNU) : !defined (__STRICT_ANSI__) -/* Minimum and maximum values a `signed long long int' can hold. */ -# undef LONG_LONG_MIN -# define LONG_LONG_MIN (-LONG_LONG_MAX - 1LL) -# undef LONG_LONG_MAX -# define LONG_LONG_MAX __LONG_LONG_MAX__ - -/* Maximum value an `unsigned long long int' can hold. (Minimum is 0). */ -# undef ULONG_LONG_MAX -# define ULONG_LONG_MAX (LONG_LONG_MAX * 2ULL + 1ULL) -#endif - -#endif /* _LIMITS_H___ */ diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/install-tools/macro_list b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/install-tools/macro_list deleted file mode 100644 index c3e2b66..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/install-tools/macro_list +++ /dev/null @@ -1 +0,0 @@ -AVR diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/install-tools/mkheaders.conf b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/install-tools/mkheaders.conf deleted file mode 100644 index 26e5dce..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/install-tools/mkheaders.conf +++ /dev/null @@ -1,3 +0,0 @@ -SYSTEM_HEADER_DIR="/home/jenkins/workspace/avr-gcc-staging/label/debian7-x86_64/objdir/avr/sys-include" -OTHER_FIXINCLUDES_DIRS="" -STMP_FIXINC="stmp-fixinc" diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/libgcc.a b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/libgcc.a deleted file mode 100644 index 19ac279..0000000 Binary files a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/libgcc.a and /dev/null differ diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/libgcov.a b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/libgcov.a deleted file mode 100644 index b9cd137..0000000 Binary files a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/libgcov.a and /dev/null differ diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/gtype.state b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/gtype.state deleted file mode 100644 index 9f22890..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/gtype.state +++ /dev/null @@ -1,30136 +0,0 @@ -;;;;@@@@ GCC gengtype state -;;; DON'T EDIT THIS FILE, since generated by GCC's gengtype -;;; The format of this file is tied to a particular version of GCC. -;;; Don't parse this file wihout knowing GCC gengtype internals. -;;; This file should be parsed by the same gengtype which wrote it. - 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(!type already_seen 135) - ) - (!srcfileloc "rtl.h" 2997) - nil ) - (!pair "gcov_fn_info_ptr_type" - (!type already_seen 5) - (!srcfileloc "coverage.c" 140) - nil ) - (!pair "gcov_fn_info_type" - (!type already_seen 5) - (!srcfileloc "coverage.c" 139) - nil ) - (!pair "gcov_info_var" - (!type already_seen 5) - (!srcfileloc "coverage.c" 138) - nil ) - (!pair "fn_v_ctrs" - (!type array 1795 nil gc_used "GCOV_COUNTERS" - (!type already_seen 5) - ) - (!srcfileloc "coverage.c" 133) - nil ) - (!pair "functions_head" - (!type already_seen 1609) - (!srcfileloc "coverage.c" 124) - nil ) - (!pair "line_table" - (!type already_seen 1721) - (!srcfileloc "input.h" 26) - nil ) -) - -(!endfile) diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/ada/gcc-interface/ada-tree.def b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/ada/gcc-interface/ada-tree.def deleted file mode 100644 index 93967b5..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/ada/gcc-interface/ada-tree.def +++ /dev/null @@ -1,74 +0,0 @@ -/**************************************************************************** - * * - * GNAT COMPILER COMPONENTS * - * * - * GNAT-SPECIFIC GCC TREE CODES * - * * - * Specification * - * * - * Copyright (C) 1992-2009, Free Software Foundation, Inc. * - * * - * GNAT is free software; you can redistribute it and/or modify it under * - * terms of the GNU General Public License as published by the Free Soft- * - * ware Foundation; either version 3, or (at your option) any later ver- * - * sion. GNAT is distributed in the hope that it will be useful, but WITH- * - * OUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY * - * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License * - * for more details. You should have received a copy of the GNU General * - * Public License along with GCC; see the file COPYING3. If not see * - * . * - * * - * GNAT was originally developed by the GNAT team at New York University. * - * Extensive contributions were provided by Ada Core Technologies Inc. * - * * - ****************************************************************************/ - -/* A type that is an unconstrained array. This node is never passed to GCC. - TREE_TYPE is the type of the fat pointer and TYPE_OBJECT_RECORD_TYPE is - the type of a record containing the template and data. */ -DEFTREECODE (UNCONSTRAINED_ARRAY_TYPE, "unconstrained_array_type", tcc_type, 0) - -/* A reference to an unconstrained array. This node only exists as an - intermediate node during the translation of a GNAT tree to a GCC tree; - it is never passed to GCC. The only field used is operand 0, which - is the fat pointer object. */ -DEFTREECODE (UNCONSTRAINED_ARRAY_REF, "unconstrained_array_ref", - tcc_reference, 1) - -/* An expression that returns an RTL suitable for its type. Operand 0 - is an expression to be evaluated for side effects only. */ -DEFTREECODE (NULL_EXPR, "null_expr", tcc_expression, 1) - -/* Same as PLUS_EXPR, except that no modulo reduction is applied. - This is used for loops and never shows up in the tree. */ -DEFTREECODE (PLUS_NOMOD_EXPR, "plus_nomod_expr", tcc_binary, 2) - -/* Same as MINUS_EXPR, except that no modulo reduction is applied. - This is used for loops and never shows up in the tree. */ -DEFTREECODE (MINUS_NOMOD_EXPR, "minus_nomod_expr", tcc_binary, 2) - -/* Same as ADDR_EXPR, except that if the operand represents a bit field, - return the address of the byte containing the bit. This is used - for the Address attribute and never shows up in the tree. */ -DEFTREECODE (ATTR_ADDR_EXPR, "attr_addr_expr", tcc_reference, 1) - -/* Here are the tree codes for the statement types known to Ada. These - must be at the end of this file to allow IS_ADA_STMT to work. */ - -/* This is how record_code_position and insert_code_for work. The former - makes this tree node, whose operand is a statement. The latter inserts - the actual statements into this node. Gimplification consists of - just returning the inner statement. */ -DEFTREECODE (STMT_STMT, "stmt_stmt", tcc_statement, 1) - -/* A loop. LOOP_STMT_COND is the test to exit the loop. LOOP_STMT_UPDATE - is the statement to update the loop iteration variable at the continue - point. LOOP_STMT_BODY are the statements in the body of the loop. And - LOOP_STMT_LABEL points to the LABEL_DECL of the end label of the loop. */ -DEFTREECODE (LOOP_STMT, "loop_stmt", tcc_statement, 4) - -/* Conditionally exit a loop. EXIT_STMT_COND is the condition, which, if - true, will cause the loop to be exited. If no condition is specified, - the loop is unconditionally exited. EXIT_STMT_LABEL is the end label - corresponding to the loop to exit. */ -DEFTREECODE (EXIT_STMT, "exit_stmt", tcc_statement, 2) diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/addresses.h b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/addresses.h deleted file mode 100644 index 3e348e2..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/addresses.h +++ /dev/null @@ -1,89 +0,0 @@ -/* Inline functions to test validity of reg classes for addressing modes. - Copyright (C) 2006-2015 Free Software Foundation, Inc. - -This file is part of GCC. - -GCC is free software; you can redistribute it and/or modify it under -the terms of the GNU General Public License as published by the Free -Software Foundation; either version 3, or (at your option) any later -version. - -GCC is distributed in the hope that it will be useful, but WITHOUT ANY -WARRANTY; without even the implied warranty of MERCHANTABILITY or -FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -for more details. - -You should have received a copy of the GNU General Public License -along with GCC; see the file COPYING3. If not see -. */ - -/* Wrapper function to unify target macros MODE_CODE_BASE_REG_CLASS, - MODE_BASE_REG_REG_CLASS, MODE_BASE_REG_CLASS and BASE_REG_CLASS. - Arguments as for the MODE_CODE_BASE_REG_CLASS macro. */ - -#ifndef GCC_ADDRESSES_H -#define GCC_ADDRESSES_H - -static inline enum reg_class -base_reg_class (machine_mode mode ATTRIBUTE_UNUSED, - addr_space_t as ATTRIBUTE_UNUSED, - enum rtx_code outer_code ATTRIBUTE_UNUSED, - enum rtx_code index_code ATTRIBUTE_UNUSED) -{ -#ifdef MODE_CODE_BASE_REG_CLASS - return MODE_CODE_BASE_REG_CLASS (mode, as, outer_code, index_code); -#else -#ifdef MODE_BASE_REG_REG_CLASS - if (index_code == REG) - return MODE_BASE_REG_REG_CLASS (mode); -#endif -#ifdef MODE_BASE_REG_CLASS - return MODE_BASE_REG_CLASS (mode); -#else - return BASE_REG_CLASS; -#endif -#endif -} - -/* Wrapper function to unify target macros REGNO_MODE_CODE_OK_FOR_BASE_P, - REGNO_MODE_OK_FOR_REG_BASE_P, REGNO_MODE_OK_FOR_BASE_P and - REGNO_OK_FOR_BASE_P. - Arguments as for the REGNO_MODE_CODE_OK_FOR_BASE_P macro. */ - -static inline bool -ok_for_base_p_1 (unsigned regno ATTRIBUTE_UNUSED, - machine_mode mode ATTRIBUTE_UNUSED, - addr_space_t as ATTRIBUTE_UNUSED, - enum rtx_code outer_code ATTRIBUTE_UNUSED, - enum rtx_code index_code ATTRIBUTE_UNUSED) -{ -#ifdef REGNO_MODE_CODE_OK_FOR_BASE_P - return REGNO_MODE_CODE_OK_FOR_BASE_P (regno, mode, as, - outer_code, index_code); -#else -#ifdef REGNO_MODE_OK_FOR_REG_BASE_P - if (index_code == REG) - return REGNO_MODE_OK_FOR_REG_BASE_P (regno, mode); -#endif -#ifdef REGNO_MODE_OK_FOR_BASE_P - return REGNO_MODE_OK_FOR_BASE_P (regno, mode); -#else - return REGNO_OK_FOR_BASE_P (regno); -#endif -#endif -} - -/* Wrapper around ok_for_base_p_1, for use after register allocation is - complete. Arguments as for the called function. */ - -static inline bool -regno_ok_for_base_p (unsigned regno, machine_mode mode, addr_space_t as, - enum rtx_code outer_code, enum rtx_code index_code) -{ - if (regno >= FIRST_PSEUDO_REGISTER && reg_renumber[regno] >= 0) - regno = reg_renumber[regno]; - - return ok_for_base_p_1 (regno, mode, as, outer_code, index_code); -} - -#endif /* GCC_ADDRESSES_H */ diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/alias.h b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/alias.h deleted file mode 100644 index 58fbcc5..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/alias.h +++ /dev/null @@ -1,53 +0,0 @@ -/* Exported functions from alias.c - Copyright (C) 2004-2015 Free Software Foundation, Inc. - -This file is part of GCC. - -GCC is free software; you can redistribute it and/or modify it under -the terms of the GNU General Public License as published by the Free -Software Foundation; either version 3, or (at your option) any later -version. - -GCC is distributed in the hope that it will be useful, but WITHOUT ANY -WARRANTY; without even the implied warranty of MERCHANTABILITY or -FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -for more details. - -You should have received a copy of the GNU General Public License -along with GCC; see the file COPYING3. If not see -. */ - -#ifndef GCC_ALIAS_H -#define GCC_ALIAS_H - -/* The type of an alias set. Code currently assumes that variables of - this type can take the values 0 (the alias set which aliases - everything) and -1 (sometimes indicating that the alias set is - unknown, sometimes indicating a memory barrier) and -2 (indicating - that the alias set should be set to a unique value but has not been - set yet). */ -typedef int alias_set_type; - -extern alias_set_type new_alias_set (void); -extern alias_set_type get_alias_set (tree); -extern alias_set_type get_deref_alias_set (tree); -extern alias_set_type get_varargs_alias_set (void); -extern alias_set_type get_frame_alias_set (void); -extern tree component_uses_parent_alias_set_from (const_tree); -extern bool alias_set_subset_of (alias_set_type, alias_set_type); -extern void record_alias_subset (alias_set_type, alias_set_type); -extern void record_component_aliases (tree); -extern int alias_sets_conflict_p (alias_set_type, alias_set_type); -extern int alias_sets_must_conflict_p (alias_set_type, alias_set_type); -extern int objects_must_conflict_p (tree, tree); -extern int nonoverlapping_memrefs_p (const_rtx, const_rtx, bool); -tree reference_alias_ptr_type (tree); -bool alias_ptr_types_compatible_p (tree, tree); - -/* This alias set can be used to force a memory to conflict with all - other memories, creating a barrier across which no memory reference - can move. Note that there are other legacy ways to create such - memory barriers, including an address of SCRATCH. */ -#define ALIAS_SET_MEMORY_BARRIER ((alias_set_type) -1) - -#endif /* GCC_ALIAS_H */ diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/all-tree.def b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/all-tree.def deleted file mode 100644 index 8a2da69..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/all-tree.def +++ /dev/null @@ -1,7 +0,0 @@ -#include "tree.def" -END_OF_BASE_TREE_CODES -#include "c-family/c-common.def" -#include "ada/gcc-interface/ada-tree.def" -#include "cp/cp-tree.def" -#include "java/java-tree.def" -#include "objc/objc-tree.def" diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/alloc-pool.h b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/alloc-pool.h deleted file mode 100644 index 0c30711..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/alloc-pool.h +++ /dev/null @@ -1,66 +0,0 @@ -/* Functions to support a pool of allocatable objects - Copyright (C) 1997-2015 Free Software Foundation, Inc. - Contributed by Daniel Berlin - -This file is part of GCC. - -GCC is free software; you can redistribute it and/or modify -it under the terms of the GNU General Public License as published by -the Free Software Foundation; either version 3, or (at your option) -any later version. - -GCC is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU General Public License for more details. - -You should have received a copy of the GNU General Public License -along with GCC; see the file COPYING3. If not see -. */ -#ifndef ALLOC_POOL_H -#define ALLOC_POOL_H - -typedef unsigned long ALLOC_POOL_ID_TYPE; - -typedef struct alloc_pool_list_def -{ - struct alloc_pool_list_def *next; -} - *alloc_pool_list; - -typedef struct alloc_pool_def -{ - const char *name; -#ifdef ENABLE_CHECKING - ALLOC_POOL_ID_TYPE id; -#endif - size_t elts_per_block; - - /* These are the elements that have been allocated at least once and freed. */ - alloc_pool_list returned_free_list; - - /* These are the elements that have not yet been allocated out of - the last block obtained from XNEWVEC. */ - char* virgin_free_list; - - /* The number of elements in the virgin_free_list that can be - allocated before needing another block. */ - size_t virgin_elts_remaining; - - size_t elts_allocated; - size_t elts_free; - size_t blocks_allocated; - alloc_pool_list block_list; - size_t block_size; - size_t elt_size; -} - *alloc_pool; - -extern alloc_pool create_alloc_pool (const char *, size_t, size_t); -extern void free_alloc_pool (alloc_pool); -extern void empty_alloc_pool (alloc_pool); -extern void free_alloc_pool_if_empty (alloc_pool *); -extern void *pool_alloc (alloc_pool) ATTRIBUTE_MALLOC; -extern void pool_free (alloc_pool, void *); -extern void dump_alloc_pool_statistics (void); -#endif diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/ansidecl.h b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/ansidecl.h deleted file mode 100644 index 04d75c3..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/ansidecl.h +++ /dev/null @@ -1,322 +0,0 @@ -/* ANSI and traditional C compatability macros - Copyright 1991, 1992, 1993, 1994, 1995, 1996, 1998, 1999, 2000, 2001, - 2002, 2003, 2004, 2005, 2006, 2007, 2009, 2010, 2013 - Free Software Foundation, Inc. - This file is part of the GNU C Library. - -This program is free software; you can redistribute it and/or modify -it under the terms of the GNU General Public License as published by -the Free Software Foundation; either version 2 of the License, or -(at your option) any later version. - -This program is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU General Public License for more details. - -You should have received a copy of the GNU General Public License -along with this program; if not, write to the Free Software -Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ - -/* ANSI and traditional C compatibility macros - - ANSI C is assumed if __STDC__ is #defined. - - Macro ANSI C definition Traditional C definition - ----- ---- - ---------- ----------- - ---------- - PTR `void *' `char *' - const not defined `' - volatile not defined `' - signed not defined `' - - For ease of writing code which uses GCC extensions but needs to be - portable to other compilers, we provide the GCC_VERSION macro that - simplifies testing __GNUC__ and __GNUC_MINOR__ together, and various - wrappers around __attribute__. Also, __extension__ will be #defined - to nothing if it doesn't work. See below. */ - -#ifndef _ANSIDECL_H -#define _ANSIDECL_H 1 - -#ifdef __cplusplus -extern "C" { -#endif - -/* Every source file includes this file, - so they will all get the switch for lint. */ -/* LINTLIBRARY */ - -/* Using MACRO(x,y) in cpp #if conditionals does not work with some - older preprocessors. Thus we can't define something like this: - -#define HAVE_GCC_VERSION(MAJOR, MINOR) \ - (__GNUC__ > (MAJOR) || (__GNUC__ == (MAJOR) && __GNUC_MINOR__ >= (MINOR))) - -and then test "#if HAVE_GCC_VERSION(2,7)". - -So instead we use the macro below and test it against specific values. */ - -/* This macro simplifies testing whether we are using gcc, and if it - is of a particular minimum version. (Both major & minor numbers are - significant.) This macro will evaluate to 0 if we are not using - gcc at all. */ -#ifndef GCC_VERSION -#define GCC_VERSION (__GNUC__ * 1000 + __GNUC_MINOR__) -#endif /* GCC_VERSION */ - -#if defined (__STDC__) || defined(__cplusplus) || defined (_AIX) || (defined (__mips) && defined (_SYSTYPE_SVR4)) || defined(_WIN32) -/* All known AIX compilers implement these things (but don't always - define __STDC__). The RISC/OS MIPS compiler defines these things - in SVR4 mode, but does not define __STDC__. */ -/* eraxxon@alumni.rice.edu: The Compaq C++ compiler, unlike many other - C++ compilers, does not define __STDC__, though it acts as if this - was so. (Verified versions: 5.7, 6.2, 6.3, 6.5) */ - -#define PTR void * - -#undef const -#undef volatile -#undef signed - -/* inline requires special treatment; it's in C99, and GCC >=2.7 supports - it too, but it's not in C89. */ -#undef inline -#if __STDC_VERSION__ >= 199901L || defined(__cplusplus) || (defined(__SUNPRO_C) && defined(__C99FEATURES__)) -/* it's a keyword */ -#else -# if GCC_VERSION >= 2007 -# define inline __inline__ /* __inline__ prevents -pedantic warnings */ -# else -# define inline /* nothing */ -# endif -#endif - -#else /* Not ANSI C. */ - -#define PTR char * - -/* some systems define these in header files for non-ansi mode */ -#undef const -#undef volatile -#undef signed -#undef inline -#define const -#define volatile -#define signed -#define inline - -#endif /* ANSI C. */ - -/* Define macros for some gcc attributes. This permits us to use the - macros freely, and know that they will come into play for the - version of gcc in which they are supported. */ - -#if (GCC_VERSION < 2007) -# define __attribute__(x) -#endif - -/* Attribute __malloc__ on functions was valid as of gcc 2.96. */ -#ifndef ATTRIBUTE_MALLOC -# if (GCC_VERSION >= 2096) -# define ATTRIBUTE_MALLOC __attribute__ ((__malloc__)) -# else -# define ATTRIBUTE_MALLOC -# endif /* GNUC >= 2.96 */ -#endif /* ATTRIBUTE_MALLOC */ - -/* Attributes on labels were valid as of gcc 2.93 and g++ 4.5. For - g++ an attribute on a label must be followed by a semicolon. */ -#ifndef ATTRIBUTE_UNUSED_LABEL -# ifndef __cplusplus -# if GCC_VERSION >= 2093 -# define ATTRIBUTE_UNUSED_LABEL ATTRIBUTE_UNUSED -# else -# define ATTRIBUTE_UNUSED_LABEL -# endif -# else -# if GCC_VERSION >= 4005 -# define ATTRIBUTE_UNUSED_LABEL ATTRIBUTE_UNUSED ; -# else -# define ATTRIBUTE_UNUSED_LABEL -# endif -# endif -#endif - -/* Similarly to ARG_UNUSED below. Prior to GCC 3.4, the C++ frontend - couldn't parse attributes placed after the identifier name, and now - the entire compiler is built with C++. */ -#ifndef ATTRIBUTE_UNUSED -#if GCC_VERSION >= 3004 -# define ATTRIBUTE_UNUSED __attribute__ ((__unused__)) -#else -#define ATTRIBUTE_UNUSED -#endif -#endif /* ATTRIBUTE_UNUSED */ - -/* Before GCC 3.4, the C++ frontend couldn't parse attributes placed after the - identifier name. */ -#if ! defined(__cplusplus) || (GCC_VERSION >= 3004) -# define ARG_UNUSED(NAME) NAME ATTRIBUTE_UNUSED -#else /* !__cplusplus || GNUC >= 3.4 */ -# define ARG_UNUSED(NAME) NAME -#endif /* !__cplusplus || GNUC >= 3.4 */ - -#ifndef ATTRIBUTE_NORETURN -#define ATTRIBUTE_NORETURN __attribute__ ((__noreturn__)) -#endif /* ATTRIBUTE_NORETURN */ - -/* Attribute `nonnull' was valid as of gcc 3.3. */ -#ifndef ATTRIBUTE_NONNULL -# if (GCC_VERSION >= 3003) -# define ATTRIBUTE_NONNULL(m) __attribute__ ((__nonnull__ (m))) -# else -# define ATTRIBUTE_NONNULL(m) -# endif /* GNUC >= 3.3 */ -#endif /* ATTRIBUTE_NONNULL */ - -/* Attribute `returns_nonnull' was valid as of gcc 4.9. */ -#ifndef ATTRIBUTE_RETURNS_NONNULL -# if (GCC_VERSION >= 4009) -# define ATTRIBUTE_RETURNS_NONNULL __attribute__ ((__returns_nonnull__)) -# else -# define ATTRIBUTE_RETURNS_NONNULL -# endif /* GNUC >= 4.9 */ -#endif /* ATTRIBUTE_RETURNS_NONNULL */ - -/* Attribute `pure' was valid as of gcc 3.0. */ -#ifndef ATTRIBUTE_PURE -# if (GCC_VERSION >= 3000) -# define ATTRIBUTE_PURE __attribute__ ((__pure__)) -# else -# define ATTRIBUTE_PURE -# endif /* GNUC >= 3.0 */ -#endif /* ATTRIBUTE_PURE */ - -/* Use ATTRIBUTE_PRINTF when the format specifier must not be NULL. - This was the case for the `printf' format attribute by itself - before GCC 3.3, but as of 3.3 we need to add the `nonnull' - attribute to retain this behavior. */ -#ifndef ATTRIBUTE_PRINTF -#define ATTRIBUTE_PRINTF(m, n) __attribute__ ((__format__ (__printf__, m, n))) ATTRIBUTE_NONNULL(m) -#define ATTRIBUTE_PRINTF_1 ATTRIBUTE_PRINTF(1, 2) -#define ATTRIBUTE_PRINTF_2 ATTRIBUTE_PRINTF(2, 3) -#define ATTRIBUTE_PRINTF_3 ATTRIBUTE_PRINTF(3, 4) -#define ATTRIBUTE_PRINTF_4 ATTRIBUTE_PRINTF(4, 5) -#define ATTRIBUTE_PRINTF_5 ATTRIBUTE_PRINTF(5, 6) -#endif /* ATTRIBUTE_PRINTF */ - -/* Use ATTRIBUTE_FPTR_PRINTF when the format attribute is to be set on - a function pointer. Format attributes were allowed on function - pointers as of gcc 3.1. */ -#ifndef ATTRIBUTE_FPTR_PRINTF -# if (GCC_VERSION >= 3001) -# define ATTRIBUTE_FPTR_PRINTF(m, n) ATTRIBUTE_PRINTF(m, n) -# else -# define ATTRIBUTE_FPTR_PRINTF(m, n) -# endif /* GNUC >= 3.1 */ -# define ATTRIBUTE_FPTR_PRINTF_1 ATTRIBUTE_FPTR_PRINTF(1, 2) -# define ATTRIBUTE_FPTR_PRINTF_2 ATTRIBUTE_FPTR_PRINTF(2, 3) -# define ATTRIBUTE_FPTR_PRINTF_3 ATTRIBUTE_FPTR_PRINTF(3, 4) -# define ATTRIBUTE_FPTR_PRINTF_4 ATTRIBUTE_FPTR_PRINTF(4, 5) -# define ATTRIBUTE_FPTR_PRINTF_5 ATTRIBUTE_FPTR_PRINTF(5, 6) -#endif /* ATTRIBUTE_FPTR_PRINTF */ - -/* Use ATTRIBUTE_NULL_PRINTF when the format specifier may be NULL. A - NULL format specifier was allowed as of gcc 3.3. */ -#ifndef ATTRIBUTE_NULL_PRINTF -# if (GCC_VERSION >= 3003) -# define ATTRIBUTE_NULL_PRINTF(m, n) __attribute__ ((__format__ (__printf__, m, n))) -# else -# define ATTRIBUTE_NULL_PRINTF(m, n) -# endif /* GNUC >= 3.3 */ -# define ATTRIBUTE_NULL_PRINTF_1 ATTRIBUTE_NULL_PRINTF(1, 2) -# define ATTRIBUTE_NULL_PRINTF_2 ATTRIBUTE_NULL_PRINTF(2, 3) -# define ATTRIBUTE_NULL_PRINTF_3 ATTRIBUTE_NULL_PRINTF(3, 4) -# define ATTRIBUTE_NULL_PRINTF_4 ATTRIBUTE_NULL_PRINTF(4, 5) -# define ATTRIBUTE_NULL_PRINTF_5 ATTRIBUTE_NULL_PRINTF(5, 6) -#endif /* ATTRIBUTE_NULL_PRINTF */ - -/* Attribute `sentinel' was valid as of gcc 3.5. */ -#ifndef ATTRIBUTE_SENTINEL -# if (GCC_VERSION >= 3005) -# define ATTRIBUTE_SENTINEL __attribute__ ((__sentinel__)) -# else -# define ATTRIBUTE_SENTINEL -# endif /* GNUC >= 3.5 */ -#endif /* ATTRIBUTE_SENTINEL */ - - -#ifndef ATTRIBUTE_ALIGNED_ALIGNOF -# if (GCC_VERSION >= 3000) -# define ATTRIBUTE_ALIGNED_ALIGNOF(m) __attribute__ ((__aligned__ (__alignof__ (m)))) -# else -# define ATTRIBUTE_ALIGNED_ALIGNOF(m) -# endif /* GNUC >= 3.0 */ -#endif /* ATTRIBUTE_ALIGNED_ALIGNOF */ - -/* Useful for structures whose layout must much some binary specification - regardless of the alignment and padding qualities of the compiler. */ -#ifndef ATTRIBUTE_PACKED -# define ATTRIBUTE_PACKED __attribute__ ((packed)) -#endif - -/* Attribute `hot' and `cold' was valid as of gcc 4.3. */ -#ifndef ATTRIBUTE_COLD -# if (GCC_VERSION >= 4003) -# define ATTRIBUTE_COLD __attribute__ ((__cold__)) -# else -# define ATTRIBUTE_COLD -# endif /* GNUC >= 4.3 */ -#endif /* ATTRIBUTE_COLD */ -#ifndef ATTRIBUTE_HOT -# if (GCC_VERSION >= 4003) -# define ATTRIBUTE_HOT __attribute__ ((__hot__)) -# else -# define ATTRIBUTE_HOT -# endif /* GNUC >= 4.3 */ -#endif /* ATTRIBUTE_HOT */ - -/* Attribute 'no_sanitize_undefined' was valid as of gcc 4.9. */ -#ifndef ATTRIBUTE_NO_SANITIZE_UNDEFINED -# if (GCC_VERSION >= 4009) -# define ATTRIBUTE_NO_SANITIZE_UNDEFINED __attribute__ ((no_sanitize_undefined)) -# else -# define ATTRIBUTE_NO_SANITIZE_UNDEFINED -# endif /* GNUC >= 4.9 */ -#endif /* ATTRIBUTE_NO_SANITIZE_UNDEFINED */ - -/* We use __extension__ in some places to suppress -pedantic warnings - about GCC extensions. This feature didn't work properly before - gcc 2.8. */ -#if GCC_VERSION < 2008 -#define __extension__ -#endif - -/* This is used to declare a const variable which should be visible - outside of the current compilation unit. Use it as - EXPORTED_CONST int i = 1; - This is because the semantics of const are different in C and C++. - "extern const" is permitted in C but it looks strange, and gcc - warns about it when -Wc++-compat is not used. */ -#ifdef __cplusplus -#define EXPORTED_CONST extern const -#else -#define EXPORTED_CONST const -#endif - -/* Be conservative and only use enum bitfields with C++ or GCC. - FIXME: provide a complete autoconf test for buggy enum bitfields. */ - -#ifdef __cplusplus -#define ENUM_BITFIELD(TYPE) enum TYPE -#elif (GCC_VERSION > 2000) -#define ENUM_BITFIELD(TYPE) __extension__ enum TYPE -#else -#define ENUM_BITFIELD(TYPE) unsigned int -#endif - -#ifdef __cplusplus -} -#endif - -#endif /* ansidecl.h */ diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/asan.h b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/asan.h deleted file mode 100644 index 51fd9cc..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/asan.h +++ /dev/null @@ -1,106 +0,0 @@ -/* AddressSanitizer, a fast memory error detector. - Copyright (C) 2011-2015 Free Software Foundation, Inc. - Contributed by Kostya Serebryany - -This file is part of GCC. - -GCC is free software; you can redistribute it and/or modify it under -the terms of the GNU General Public License as published by the Free -Software Foundation; either version 3, or (at your option) any later -version. - -GCC is distributed in the hope that it will be useful, but WITHOUT ANY -WARRANTY; without even the implied warranty of MERCHANTABILITY or -FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -for more details. - -You should have received a copy of the GNU General Public License -along with GCC; see the file COPYING3. If not see -. */ - -#ifndef TREE_ASAN -#define TREE_ASAN - -extern void asan_function_start (void); -extern void asan_finish_file (void); -extern rtx_insn *asan_emit_stack_protection (rtx, rtx, unsigned int, - HOST_WIDE_INT *, tree *, int); -extern bool asan_protect_global (tree); -extern void initialize_sanitizer_builtins (void); -extern tree asan_dynamic_init_call (bool); -extern bool asan_expand_check_ifn (gimple_stmt_iterator *, bool); - -extern gimple_stmt_iterator create_cond_insert_point - (gimple_stmt_iterator *, bool, bool, bool, basic_block *, basic_block *); - -/* Alias set for accessing the shadow memory. */ -extern alias_set_type asan_shadow_set; - -/* Shadow memory is found at - (address >> ASAN_SHADOW_SHIFT) + asan_shadow_offset (). */ -#define ASAN_SHADOW_SHIFT 3 - -/* Red zone size, stack and global variables are padded by ASAN_RED_ZONE_SIZE - up to 2 * ASAN_RED_ZONE_SIZE - 1 bytes. */ -#define ASAN_RED_ZONE_SIZE 32 - -/* Shadow memory values for stack protection. Left is below protected vars, - the first pointer in stack corresponding to that offset contains - ASAN_STACK_FRAME_MAGIC word, the second pointer to a string describing - the frame. Middle is for padding in between variables, right is - above the last protected variable and partial immediately after variables - up to ASAN_RED_ZONE_SIZE alignment. */ -#define ASAN_STACK_MAGIC_LEFT 0xf1 -#define ASAN_STACK_MAGIC_MIDDLE 0xf2 -#define ASAN_STACK_MAGIC_RIGHT 0xf3 -#define ASAN_STACK_MAGIC_PARTIAL 0xf4 -#define ASAN_STACK_MAGIC_USE_AFTER_RET 0xf5 - -#define ASAN_STACK_FRAME_MAGIC 0x41b58ab3 -#define ASAN_STACK_RETIRED_MAGIC 0x45e0360e - -/* Return true if DECL should be guarded on the stack. */ - -static inline bool -asan_protect_stack_decl (tree decl) -{ - return DECL_P (decl) && !DECL_ARTIFICIAL (decl); -} - -/* Return the size of padding needed to insert after a protected - decl of SIZE. */ - -static inline unsigned int -asan_red_zone_size (unsigned int size) -{ - unsigned int c = size & (ASAN_RED_ZONE_SIZE - 1); - return c ? 2 * ASAN_RED_ZONE_SIZE - c : ASAN_RED_ZONE_SIZE; -} - -extern bool set_asan_shadow_offset (const char *); - -/* Return TRUE if builtin with given FCODE will be intercepted by - libasan. */ - -static inline bool -asan_intercepted_p (enum built_in_function fcode) -{ - return fcode == BUILT_IN_INDEX - || fcode == BUILT_IN_MEMCHR - || fcode == BUILT_IN_MEMCMP - || fcode == BUILT_IN_MEMCPY - || fcode == BUILT_IN_MEMMOVE - || fcode == BUILT_IN_MEMSET - || fcode == BUILT_IN_STRCASECMP - || fcode == BUILT_IN_STRCAT - || fcode == BUILT_IN_STRCHR - || fcode == BUILT_IN_STRCMP - || fcode == BUILT_IN_STRCPY - || fcode == BUILT_IN_STRDUP - || fcode == BUILT_IN_STRLEN - || fcode == BUILT_IN_STRNCASECMP - || fcode == BUILT_IN_STRNCAT - || fcode == BUILT_IN_STRNCMP - || fcode == BUILT_IN_STRNCPY; -} -#endif /* TREE_ASAN */ diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/attribs.h b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/attribs.h deleted file mode 100644 index ac855d5..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/attribs.h +++ /dev/null @@ -1,40 +0,0 @@ -/* Declarations and definitions dealing with attribute handling. - Copyright (C) 2013-2015 Free Software Foundation, Inc. - -This file is part of GCC. - -GCC is free software; you can redistribute it and/or modify it under -the terms of the GNU General Public License as published by the Free -Software Foundation; either version 3, or (at your option) any later -version. - -GCC is distributed in the hope that it will be useful, but WITHOUT ANY -WARRANTY; without even the implied warranty of MERCHANTABILITY or -FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -for more details. - -You should have received a copy of the GNU General Public License -along with GCC; see the file COPYING3. If not see -. */ - -#ifndef GCC_ATTRIBS_H -#define GCC_ATTRIBS_H - -extern const struct attribute_spec *lookup_attribute_spec (const_tree); -extern void init_attributes (void); - -/* Process the attributes listed in ATTRIBUTES and install them in *NODE, - which is either a DECL (including a TYPE_DECL) or a TYPE. If a DECL, - it should be modified in place; if a TYPE, a copy should be created - unless ATTR_FLAG_TYPE_IN_PLACE is set in FLAGS. FLAGS gives further - information, in the form of a bitwise OR of flags in enum attribute_flags - from tree.h. Depending on these flags, some attributes may be - returned to be applied at a later stage (for example, to apply - a decl attribute to the declaration rather than to its type). */ -extern tree decl_attributes (tree *, tree, int); - -extern bool cxx11_attribute_p (const_tree); -extern tree get_attribute_name (const_tree); -extern void apply_tm_attr (tree, tree); - -#endif // GCC_ATTRIBS_H diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/auto-host.h b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/auto-host.h deleted file mode 100644 index 2a7fdef..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/auto-host.h +++ /dev/null @@ -1,2262 +0,0 @@ -/* auto-host.h. Generated from config.in by configure. */ -/* config.in. Generated from configure.ac by autoheader. */ - -/* Define if this compiler should be built as the offload target compiler. */ -#ifndef USED_FOR_TARGET -/* #undef ACCEL_COMPILER */ -#endif - - -/* Define if building universal (internal helper macro) */ -#ifndef USED_FOR_TARGET -/* #undef AC_APPLE_UNIVERSAL_BUILD */ -#endif - - -/* Define to the assembler option to enable compressed debug sections. */ -#ifndef USED_FOR_TARGET -#define AS_COMPRESS_DEBUG_OPTION "--compress-debug-sections" -#endif - - -/* Define to the assembler option to disable compressed debug sections. */ -#ifndef USED_FOR_TARGET -#define AS_NO_COMPRESS_DEBUG_OPTION "--nocompress-debug-sections" -#endif - - -/* Define as the number of bits in a byte, if `limits.h' doesn't. */ -#ifndef USED_FOR_TARGET -/* #undef CHAR_BIT */ -#endif - - -/* Define 0/1 to force the choice for exception handling model. */ -#ifndef USED_FOR_TARGET -/* #undef CONFIG_SJLJ_EXCEPTIONS */ -#endif - - -/* Define to enable the use of a default assembler. */ -#ifndef USED_FOR_TARGET -/* #undef DEFAULT_ASSEMBLER */ -#endif - - -/* Define to enable the use of a default linker. */ -#ifndef USED_FOR_TARGET -/* #undef DEFAULT_LINKER */ -#endif - - -/* Define if you want to use __cxa_atexit, rather than atexit, to register C++ - destructors for local statics and global objects. This is essential for - fully standards-compliant handling of destructors, but requires - __cxa_atexit in libc. */ -#ifndef USED_FOR_TARGET -/* #undef DEFAULT_USE_CXA_ATEXIT */ -#endif - - -/* The default for -fdiagnostics-color option */ -#ifndef USED_FOR_TARGET -#define DIAGNOSTICS_COLOR_DEFAULT DIAGNOSTICS_COLOR_AUTO -#endif - - -/* Define if you want assertions enabled. This is a cheap check. */ -#ifndef USED_FOR_TARGET -#define ENABLE_ASSERT_CHECKING 1 -#endif - - -/* Define if you want more run-time sanity checks. This one gets a grab bag of - miscellaneous but relatively cheap checks. */ -#ifndef USED_FOR_TARGET -/* #undef ENABLE_CHECKING */ -#endif - - -/* Define to 1 to specify that we are using the BID decimal floating point - format instead of DPD */ -#ifndef USED_FOR_TARGET -#define ENABLE_DECIMAL_BID_FORMAT 0 -#endif - - -/* Define to 1 to enable decimal float extension to C. */ -#ifndef USED_FOR_TARGET -#define ENABLE_DECIMAL_FLOAT 0 -#endif - - -/* Define if you want more run-time sanity checks for dataflow. */ -#ifndef USED_FOR_TARGET -/* #undef ENABLE_DF_CHECKING */ -#endif - - -/* Define to 1 to enable fixed-point arithmetic extension to C. */ -#ifndef USED_FOR_TARGET -#define ENABLE_FIXED_POINT 1 -#endif - - -/* Define if you want fold checked that it never destructs its argument. This - is quite expensive. */ -#ifndef USED_FOR_TARGET -/* #undef ENABLE_FOLD_CHECKING */ -#endif - - -/* Define if you want the garbage collector to operate in maximally paranoid - mode, validating the entire heap and collecting garbage at every - opportunity. This is extremely expensive. */ -#ifndef USED_FOR_TARGET -/* #undef ENABLE_GC_ALWAYS_COLLECT */ -#endif - - -/* Define if you want the garbage collector to do object poisoning and other - memory allocation checks. This is quite expensive. */ -#ifndef USED_FOR_TARGET -/* #undef ENABLE_GC_CHECKING */ -#endif - - -/* Define if you want operations on GIMPLE (the basic data structure of the - high-level optimizers) to be checked for dynamic type safety at runtime. - This is moderately expensive. */ -#ifndef USED_FOR_TARGET -/* #undef ENABLE_GIMPLE_CHECKING */ -#endif - - -/* Define if gcc should always pass --build-id to linker. */ -#ifndef USED_FOR_TARGET -/* #undef ENABLE_LD_BUILDID */ -#endif - - -/* Define to 1 to enable libquadmath support */ -#ifndef USED_FOR_TARGET -#define ENABLE_LIBQUADMATH_SUPPORT 1 -#endif - - -/* Define to enable LTO support. */ -#ifndef USED_FOR_TARGET -#define ENABLE_LTO 1 -#endif - - -/* Define to 1 if translation of program messages to the user's native - language is requested. */ -#ifndef USED_FOR_TARGET -/* #undef ENABLE_NLS */ -#endif - - -/* Define this to enable support for offloading. */ -#ifndef USED_FOR_TARGET -/* #undef ENABLE_OFFLOADING */ -#endif - - -/* Define to enable plugin support. */ -#ifndef USED_FOR_TARGET -#define ENABLE_PLUGIN 1 -#endif - - -/* Define if you want all operations on RTL (the basic data structure of the - optimizer and back end) to be checked for dynamic type safety at runtime. - This is quite expensive. */ -#ifndef USED_FOR_TARGET -/* #undef ENABLE_RTL_CHECKING */ -#endif - - -/* Define if you want RTL flag accesses to be checked against the RTL codes - that are supported for each access macro. This is relatively cheap. */ -#ifndef USED_FOR_TARGET -/* #undef ENABLE_RTL_FLAG_CHECKING */ -#endif - - -/* Define if you want runtime assertions enabled. This is a cheap check. */ -#define ENABLE_RUNTIME_CHECKING 1 - -/* Define if you want all operations on trees (the basic data structure of the - front ends) to be checked for dynamic type safety at runtime. This is - moderately expensive. The tree browser debugging routines will also be - enabled by this option. */ -#ifndef USED_FOR_TARGET -/* #undef ENABLE_TREE_CHECKING */ -#endif - - -/* Define if you want all gimple types to be verified after gimplifiation. - This is cheap. */ -#ifndef USED_FOR_TARGET -/* #undef ENABLE_TYPES_CHECKING */ -#endif - - -/* Define to get calls to the valgrind runtime enabled. */ -#ifndef USED_FOR_TARGET -/* #undef ENABLE_VALGRIND_ANNOTATIONS */ -#endif - - -/* Define if you want to run subprograms and generated programs through - valgrind (a memory checker). This is extremely expensive. */ -#ifndef USED_FOR_TARGET -/* #undef ENABLE_VALGRIND_CHECKING */ -#endif - - -/* Define to 1 if installation paths should be looked up in the Windows - Registry. Ignored on non-Windows hosts. */ -#ifndef USED_FOR_TARGET -/* #undef ENABLE_WIN32_REGISTRY */ -#endif - - -/* Define to the name of a file containing a list of extra machine modes for - this architecture. */ -#ifndef USED_FOR_TARGET -#define EXTRA_MODES_FILE "config/avr/avr-modes.def" -#endif - - -/* Define to enable detailed memory allocation stats gathering. */ -#ifndef USED_FOR_TARGET -#define GATHER_STATISTICS 0 -#endif - - -/* Define to 1 if `TIOCGWINSZ' requires . */ -#ifndef USED_FOR_TARGET -#define GWINSZ_IN_SYS_IOCTL 1 -#endif - - -/* mcontext_t fields start with __ */ -#ifndef USED_FOR_TARGET -/* #undef HAS_MCONTEXT_T_UNDERSCORES */ -#endif - - -/* Define if your avr assembler supports --mlink-relax option. */ -#ifndef USED_FOR_TARGET -#define HAVE_AS_AVR_MLINK_RELAX_OPTION 1 -#endif - - -/* Define if your avr assembler supports -mrmw option. */ -#ifndef USED_FOR_TARGET -#define HAVE_AS_AVR_MRMW_OPTION 1 -#endif - - -/* Define if your assembler supports cmpb. */ -#ifndef USED_FOR_TARGET -/* #undef HAVE_AS_CMPB */ -#endif - - -/* Define to the level of your assembler's compressed debug section support. - */ -#ifndef USED_FOR_TARGET -#define HAVE_AS_COMPRESS_DEBUG 1 -#endif - - -/* Define if your assembler supports the DCI/ICI instructions. */ -#ifndef USED_FOR_TARGET -/* #undef HAVE_AS_DCI */ -#endif - - -/* Define if your assembler supports the --debug-prefix-map option. */ -#ifndef USED_FOR_TARGET -#define HAVE_AS_DEBUG_PREFIX_MAP 1 -#endif - - -/* Define if your assembler supports DFP instructions. */ -#ifndef USED_FOR_TARGET -/* #undef HAVE_AS_DFP */ -#endif - - -/* Define if your assembler supports .module. */ -#ifndef USED_FOR_TARGET -/* #undef HAVE_AS_DOT_MODULE */ -#endif - - -/* Define if your assembler supports DSPR1 mult. */ -#ifndef USED_FOR_TARGET -/* #undef HAVE_AS_DSPR1_MULT */ -#endif - - -/* Define if your assembler supports .dtprelword. */ -#ifndef USED_FOR_TARGET -/* #undef HAVE_AS_DTPRELWORD */ -#endif - - -/* Define if your assembler supports dwarf2 .file/.loc directives, and - preserves file table indices exactly as given. */ -#ifndef USED_FOR_TARGET -#define HAVE_AS_DWARF2_DEBUG_LINE 1 -#endif - - -/* Define if your assembler supports explicit relocations. */ -#ifndef USED_FOR_TARGET -/* #undef HAVE_AS_EXPLICIT_RELOCS */ -#endif - - -/* Define if your assembler supports FMAF, HPC, and VIS 3.0 instructions. */ -#ifndef USED_FOR_TARGET -/* #undef HAVE_AS_FMAF_HPC_VIS3 */ -#endif - - -/* Define if your assembler supports fprnd. */ -#ifndef USED_FOR_TARGET -/* #undef HAVE_AS_FPRND */ -#endif - - -/* Define if your assembler supports the --gdwarf2 option. */ -#ifndef USED_FOR_TARGET -#define HAVE_AS_GDWARF2_DEBUG_FLAG 1 -#endif - - -/* Define if your assembler supports .gnu_attribute. */ -#ifndef USED_FOR_TARGET -/* #undef HAVE_AS_GNU_ATTRIBUTE */ -#endif - - -/* Define true if the assembler supports '.long foo@GOTOFF'. */ -#ifndef USED_FOR_TARGET -/* #undef HAVE_AS_GOTOFF_IN_DATA */ -#endif - - -/* Define if your assembler supports the --gstabs option. */ -#ifndef USED_FOR_TARGET -#define HAVE_AS_GSTABS_DEBUG_FLAG 1 -#endif - - -/* Define if your assembler supports the Sun syntax for cmov. */ -#ifndef USED_FOR_TARGET -/* #undef HAVE_AS_IX86_CMOV_SUN_SYNTAX */ -#endif - - -/* Define if your assembler supports the subtraction of symbols in different - sections. */ -#ifndef USED_FOR_TARGET -/* #undef HAVE_AS_IX86_DIFF_SECT_DELTA */ -#endif - - -/* Define if your assembler supports the ffreep mnemonic. */ -#ifndef USED_FOR_TARGET -/* #undef HAVE_AS_IX86_FFREEP */ -#endif - - -/* Define if your assembler uses fildq and fistq mnemonics. */ -#ifndef USED_FOR_TARGET -/* #undef HAVE_AS_IX86_FILDQ */ -#endif - - -/* Define if your assembler uses filds and fists mnemonics. */ -#ifndef USED_FOR_TARGET -/* #undef HAVE_AS_IX86_FILDS */ -#endif - - -/* Define if your assembler supports HLE prefixes. */ -#ifndef USED_FOR_TARGET -/* #undef HAVE_AS_IX86_HLE */ -#endif - - -/* Define if your assembler supports interunit movq mnemonic. */ -#ifndef USED_FOR_TARGET -/* #undef HAVE_AS_IX86_INTERUNIT_MOVQ */ -#endif - - -/* Define if your assembler supports the .quad directive. */ -#ifndef USED_FOR_TARGET -/* #undef HAVE_AS_IX86_QUAD */ -#endif - - -/* Define if the assembler supports 'rep , lock '. */ -#ifndef USED_FOR_TARGET -/* #undef HAVE_AS_IX86_REP_LOCK_PREFIX */ -#endif - - -/* Define if your assembler supports the sahf mnemonic in 64bit mode. */ -#ifndef USED_FOR_TARGET -/* #undef HAVE_AS_IX86_SAHF */ -#endif - - -/* Define if your assembler supports the swap suffix. */ -#ifndef USED_FOR_TARGET -/* #undef HAVE_AS_IX86_SWAP */ -#endif - - -/* Define if your assembler and linker support @tlsgdplt. */ -#ifndef USED_FOR_TARGET -/* #undef HAVE_AS_IX86_TLSGDPLT */ -#endif - - -/* Define to 1 if your assembler and linker support @tlsldm. */ -#ifndef USED_FOR_TARGET -/* #undef HAVE_AS_IX86_TLSLDM */ -#endif - - -/* Define to 1 if your assembler and linker support @tlsldmplt. */ -#ifndef USED_FOR_TARGET -/* #undef HAVE_AS_IX86_TLSLDMPLT */ -#endif - - -/* Define if your assembler supports the 'ud2' mnemonic. */ -#ifndef USED_FOR_TARGET -/* #undef HAVE_AS_IX86_UD2 */ -#endif - - -/* Define if your assembler supports the lituse_jsrdirect relocation. */ -#ifndef USED_FOR_TARGET -/* #undef HAVE_AS_JSRDIRECT_RELOCS */ -#endif - - -/* Define if your assembler supports .sleb128 and .uleb128. */ -#ifndef USED_FOR_TARGET -#define HAVE_AS_LEB128 1 -#endif - - -/* Define if your assembler supports LEON instructions. */ -#ifndef USED_FOR_TARGET -/* #undef HAVE_AS_LEON */ -#endif - - -/* Define if the assembler won't complain about a line such as # 0 "" 2. */ -#ifndef USED_FOR_TARGET -#define HAVE_AS_LINE_ZERO 1 -#endif - - -/* Define if your assembler supports ltoffx and ldxmov relocations. */ -#ifndef USED_FOR_TARGET -/* #undef HAVE_AS_LTOFFX_LDXMOV_RELOCS */ -#endif - - -/* Define if your assembler supports LWSYNC instructions. */ -#ifndef USED_FOR_TARGET -/* #undef HAVE_AS_LWSYNC */ -#endif - - -/* Define if your assembler supports the -mabi option. */ -#ifndef USED_FOR_TARGET -/* #undef HAVE_AS_MABI_OPTION */ -#endif - - -/* Define if your assembler supports mfcr field. */ -#ifndef USED_FOR_TARGET -/* #undef HAVE_AS_MFCRF */ -#endif - - -/* Define if your assembler supports mffgpr and mftgpr. */ -#ifndef USED_FOR_TARGET -/* #undef HAVE_AS_MFPGPR */ -#endif - - -/* Define if the assembler understands -mnan=. */ -#ifndef USED_FOR_TARGET -/* #undef HAVE_AS_NAN */ -#endif - - -/* Define if your assembler supports the -no-mul-bug-abort option. */ -#ifndef USED_FOR_TARGET -/* #undef HAVE_AS_NO_MUL_BUG_ABORT_OPTION */ -#endif - - -/* Define if the assembler understands -mno-shared. */ -#ifndef USED_FOR_TARGET -/* #undef HAVE_AS_NO_SHARED */ -#endif - - -/* Define if your assembler supports offsetable %lo(). */ -#ifndef USED_FOR_TARGET -/* #undef HAVE_AS_OFFSETABLE_LO10 */ -#endif - - -/* Define if your assembler supports popcntb field. */ -#ifndef USED_FOR_TARGET -/* #undef HAVE_AS_POPCNTB */ -#endif - - -/* Define if your assembler supports POPCNTD instructions. */ -#ifndef USED_FOR_TARGET -/* #undef HAVE_AS_POPCNTD */ -#endif - - -/* Define if your assembler supports POWER8 instructions. */ -#ifndef USED_FOR_TARGET -/* #undef HAVE_AS_POWER8 */ -#endif - - -/* Define if your assembler supports .ref */ -#ifndef USED_FOR_TARGET -/* #undef HAVE_AS_REF */ -#endif - - -/* Define if your assembler supports .register. */ -#ifndef USED_FOR_TARGET -/* #undef HAVE_AS_REGISTER_PSEUDO_OP */ -#endif - - -/* Define if your assembler supports R_PPC_REL16 relocs. */ -#ifndef USED_FOR_TARGET -/* #undef HAVE_AS_REL16 */ -#endif - - -/* Define if your assembler supports -relax option. */ -#ifndef USED_FOR_TARGET -/* #undef HAVE_AS_RELAX_OPTION */ -#endif - - -/* Define if your assembler supports SPARC4 instructions. */ -#ifndef USED_FOR_TARGET -/* #undef HAVE_AS_SPARC4 */ -#endif - - -/* Define if your assembler and linker support GOTDATA_OP relocs. */ -#ifndef USED_FOR_TARGET -/* #undef HAVE_AS_SPARC_GOTDATA_OP */ -#endif - - -/* Define to 1 if your assembler supports #nobits, 0 otherwise. */ -#ifndef USED_FOR_TARGET -/* #undef HAVE_AS_SPARC_NOBITS */ -#endif - - -/* Define if your assembler and linker support unaligned PC relative relocs. - */ -#ifndef USED_FOR_TARGET -/* #undef HAVE_AS_SPARC_UA_PCREL */ -#endif - - -/* Define if your assembler and linker support unaligned PC relative relocs - against hidden symbols. */ -#ifndef USED_FOR_TARGET -/* #undef HAVE_AS_SPARC_UA_PCREL_HIDDEN */ -#endif - - -/* Define if your assembler supports .stabs. */ -#ifndef USED_FOR_TARGET -#define HAVE_AS_STABS_DIRECTIVE 1 -#endif - - -/* Define if your assembler and linker support thread-local storage. */ -#ifndef USED_FOR_TARGET -/* #undef HAVE_AS_TLS */ -#endif - - -/* Define if your assembler supports arg info for __tls_get_addr. */ -#ifndef USED_FOR_TARGET -/* #undef HAVE_AS_TLS_MARKERS */ -#endif - - -/* Define if your assembler supports VSX instructions. */ -#ifndef USED_FOR_TARGET -/* #undef HAVE_AS_VSX */ -#endif - - -/* Define to 1 if you have the `atoll' function. */ -#ifndef USED_FOR_TARGET -#define HAVE_ATOLL 1 -#endif - - -/* Define to 1 if you have the `atoq' function. */ -#ifndef USED_FOR_TARGET -/* #undef HAVE_ATOQ */ -#endif - - -/* Define to 1 if you have the `clearerr_unlocked' function. */ -#ifndef USED_FOR_TARGET -#define HAVE_CLEARERR_UNLOCKED 1 -#endif - - -/* Define to 1 if you have the `clock' function. */ -#ifndef USED_FOR_TARGET -#define HAVE_CLOCK 1 -#endif - - -/* Define if defines clock_t. */ -#ifndef USED_FOR_TARGET -#define HAVE_CLOCK_T 1 -#endif - - -/* Define 0/1 if your assembler and linker support COMDAT groups. */ -#ifndef USED_FOR_TARGET -#define HAVE_COMDAT_GROUP 1 -#endif - - -/* Define to 1 if we found a declaration for 'abort', otherwise define to 0. - */ -#ifndef USED_FOR_TARGET -#define HAVE_DECL_ABORT 1 -#endif - - -/* Define to 1 if we found a declaration for 'asprintf', otherwise define to - 0. */ -#ifndef USED_FOR_TARGET -#define HAVE_DECL_ASPRINTF 1 -#endif - - -/* Define to 1 if we found a declaration for 'atof', otherwise define to 0. */ -#ifndef USED_FOR_TARGET -#define HAVE_DECL_ATOF 1 -#endif - - -/* Define to 1 if we found a declaration for 'atol', otherwise define to 0. */ -#ifndef USED_FOR_TARGET -#define HAVE_DECL_ATOL 1 -#endif - - -/* Define to 1 if we found a declaration for 'basename', otherwise define to - 0. */ -#ifndef USED_FOR_TARGET -#define HAVE_DECL_BASENAME 1 -#endif - - -/* Define to 1 if we found a declaration for 'calloc', otherwise define to 0. - */ -#ifndef USED_FOR_TARGET -#define HAVE_DECL_CALLOC 1 -#endif - - -/* Define to 1 if we found a declaration for 'clearerr_unlocked', otherwise - define to 0. */ -#ifndef USED_FOR_TARGET -#define HAVE_DECL_CLEARERR_UNLOCKED 1 -#endif - - -/* Define to 1 if we found a declaration for 'clock', otherwise define to 0. - */ -#ifndef USED_FOR_TARGET -#define HAVE_DECL_CLOCK 1 -#endif - - -/* Define to 1 if we found a declaration for 'errno', otherwise define to 0. - */ -#ifndef USED_FOR_TARGET -#define HAVE_DECL_ERRNO 1 -#endif - - -/* Define to 1 if we found a declaration for 'feof_unlocked', otherwise define - to 0. */ -#ifndef USED_FOR_TARGET -#define HAVE_DECL_FEOF_UNLOCKED 1 -#endif - - -/* Define to 1 if we found a declaration for 'ferror_unlocked', otherwise - define to 0. */ -#ifndef USED_FOR_TARGET -#define HAVE_DECL_FERROR_UNLOCKED 1 -#endif - - -/* Define to 1 if we found a declaration for 'fflush_unlocked', otherwise - define to 0. */ -#ifndef USED_FOR_TARGET -#define HAVE_DECL_FFLUSH_UNLOCKED 1 -#endif - - -/* Define to 1 if we found a declaration for 'ffs', otherwise define to 0. */ -#ifndef USED_FOR_TARGET -#define HAVE_DECL_FFS 1 -#endif - - -/* Define to 1 if we found a declaration for 'fgetc_unlocked', otherwise - define to 0. */ -#ifndef USED_FOR_TARGET -#define HAVE_DECL_FGETC_UNLOCKED 1 -#endif - - -/* Define to 1 if we found a declaration for 'fgets_unlocked', otherwise - define to 0. */ -#ifndef USED_FOR_TARGET -#define HAVE_DECL_FGETS_UNLOCKED 1 -#endif - - -/* Define to 1 if we found a declaration for 'fileno_unlocked', otherwise - define to 0. */ -#ifndef USED_FOR_TARGET -#define HAVE_DECL_FILENO_UNLOCKED 1 -#endif - - -/* Define to 1 if we found a declaration for 'fprintf_unlocked', otherwise - define to 0. */ -#ifndef USED_FOR_TARGET -#define HAVE_DECL_FPRINTF_UNLOCKED 0 -#endif - - -/* Define to 1 if we found a declaration for 'fputc_unlocked', otherwise - define to 0. */ -#ifndef USED_FOR_TARGET -#define HAVE_DECL_FPUTC_UNLOCKED 1 -#endif - - -/* Define to 1 if we found a declaration for 'fputs_unlocked', otherwise - define to 0. */ -#ifndef USED_FOR_TARGET -#define HAVE_DECL_FPUTS_UNLOCKED 1 -#endif - - -/* Define to 1 if we found a declaration for 'fread_unlocked', otherwise - define to 0. */ -#ifndef USED_FOR_TARGET -#define HAVE_DECL_FREAD_UNLOCKED 1 -#endif - - -/* Define to 1 if we found a declaration for 'free', otherwise define to 0. */ -#ifndef USED_FOR_TARGET -#define HAVE_DECL_FREE 1 -#endif - - -/* Define to 1 if we found a declaration for 'fwrite_unlocked', otherwise - define to 0. */ -#ifndef USED_FOR_TARGET -#define HAVE_DECL_FWRITE_UNLOCKED 1 -#endif - - -/* Define to 1 if we found a declaration for 'getchar_unlocked', otherwise - define to 0. */ -#ifndef USED_FOR_TARGET -#define HAVE_DECL_GETCHAR_UNLOCKED 1 -#endif - - -/* Define to 1 if we found a declaration for 'getcwd', otherwise define to 0. - */ -#ifndef USED_FOR_TARGET -#define HAVE_DECL_GETCWD 1 -#endif - - -/* Define to 1 if we found a declaration for 'getc_unlocked', otherwise define - to 0. */ -#ifndef USED_FOR_TARGET -#define HAVE_DECL_GETC_UNLOCKED 1 -#endif - - -/* Define to 1 if we found a declaration for 'getenv', otherwise define to 0. - */ -#ifndef USED_FOR_TARGET -#define HAVE_DECL_GETENV 1 -#endif - - -/* Define to 1 if we found a declaration for 'getopt', otherwise define to 0. - */ -#ifndef USED_FOR_TARGET -#define HAVE_DECL_GETOPT 0 -#endif - - -/* Define to 1 if we found a declaration for 'getpagesize', otherwise define - to 0. */ -#ifndef USED_FOR_TARGET -#define HAVE_DECL_GETPAGESIZE 1 -#endif - - -/* Define to 1 if we found a declaration for 'getrlimit', otherwise define to - 0. */ -#ifndef USED_FOR_TARGET -#define HAVE_DECL_GETRLIMIT 1 -#endif - - -/* Define to 1 if we found a declaration for 'getrusage', otherwise define to - 0. */ -#ifndef USED_FOR_TARGET -#define HAVE_DECL_GETRUSAGE 1 -#endif - - -/* Define to 1 if we found a declaration for 'getwd', otherwise define to 0. - */ -#ifndef USED_FOR_TARGET -#define HAVE_DECL_GETWD 1 -#endif - - -/* Define to 1 if we found a declaration for 'ldgetname', otherwise define to - 0. */ -#ifndef USED_FOR_TARGET -#define HAVE_DECL_LDGETNAME 0 -#endif - - -/* Define to 1 if we found a declaration for 'madvise', otherwise define to 0. - */ -#ifndef USED_FOR_TARGET -#define HAVE_DECL_MADVISE 1 -#endif - - -/* Define to 1 if we found a declaration for 'malloc', otherwise define to 0. - */ -#ifndef USED_FOR_TARGET -#define HAVE_DECL_MALLOC 1 -#endif - - -/* Define to 1 if we found a declaration for 'putchar_unlocked', otherwise - define to 0. */ -#ifndef USED_FOR_TARGET -#define HAVE_DECL_PUTCHAR_UNLOCKED 1 -#endif - - -/* Define to 1 if we found a declaration for 'putc_unlocked', otherwise define - to 0. */ -#ifndef USED_FOR_TARGET -#define HAVE_DECL_PUTC_UNLOCKED 1 -#endif - - -/* Define to 1 if we found a declaration for 'realloc', otherwise define to 0. - */ -#ifndef USED_FOR_TARGET -#define HAVE_DECL_REALLOC 1 -#endif - - -/* Define to 1 if we found a declaration for 'sbrk', otherwise define to 0. */ -#ifndef USED_FOR_TARGET -#define HAVE_DECL_SBRK 1 -#endif - - -/* Define to 1 if we found a declaration for 'setrlimit', otherwise define to - 0. */ -#ifndef USED_FOR_TARGET -#define HAVE_DECL_SETRLIMIT 1 -#endif - - -/* Define to 1 if we found a declaration for 'sigaltstack', otherwise define - to 0. */ -#ifndef USED_FOR_TARGET -#define HAVE_DECL_SIGALTSTACK 1 -#endif - - -/* Define to 1 if we found a declaration for 'snprintf', otherwise define to - 0. */ -#ifndef USED_FOR_TARGET -#define HAVE_DECL_SNPRINTF 1 -#endif - - -/* Define to 1 if we found a declaration for 'stpcpy', otherwise define to 0. - */ -#ifndef USED_FOR_TARGET -#define HAVE_DECL_STPCPY 1 -#endif - - -/* Define to 1 if we found a declaration for 'strnlen', otherwise define to 0. - */ -#ifndef USED_FOR_TARGET -#define HAVE_DECL_STRNLEN 1 -#endif - - -/* Define to 1 if we found a declaration for 'strsignal', otherwise define to - 0. */ -#ifndef USED_FOR_TARGET -#define HAVE_DECL_STRSIGNAL 1 -#endif - - -/* Define to 1 if we found a declaration for 'strstr', otherwise define to 0. - */ -#ifndef USED_FOR_TARGET -#define HAVE_DECL_STRSTR 1 -#endif - - -/* Define to 1 if we found a declaration for 'strtol', otherwise define to 0. - */ -#ifndef USED_FOR_TARGET -#define HAVE_DECL_STRTOL 1 -#endif - - -/* Define to 1 if we found a declaration for 'strtoll', otherwise define to 0. - */ -#ifndef USED_FOR_TARGET -#define HAVE_DECL_STRTOLL 1 -#endif - - -/* Define to 1 if we found a declaration for 'strtoul', otherwise define to 0. - */ -#ifndef USED_FOR_TARGET -#define HAVE_DECL_STRTOUL 1 -#endif - - -/* Define to 1 if we found a declaration for 'strtoull', otherwise define to - 0. */ -#ifndef USED_FOR_TARGET -#define HAVE_DECL_STRTOULL 1 -#endif - - -/* Define to 1 if we found a declaration for 'strverscmp', otherwise define to - 0. */ -#ifndef USED_FOR_TARGET -#define HAVE_DECL_STRVERSCMP 1 -#endif - - -/* Define to 1 if we found a declaration for 'times', otherwise define to 0. - */ -#ifndef USED_FOR_TARGET -#define HAVE_DECL_TIMES 1 -#endif - - -/* Define to 1 if we found a declaration for 'vasprintf', otherwise define to - 0. */ -#ifndef USED_FOR_TARGET -#define HAVE_DECL_VASPRINTF 1 -#endif - - -/* Define to 1 if we found a declaration for 'vsnprintf', otherwise define to - 0. */ -#ifndef USED_FOR_TARGET -#define HAVE_DECL_VSNPRINTF 1 -#endif - - -/* Define to 1 if you have the header file. */ -#ifndef USED_FOR_TARGET -/* #undef HAVE_DIRECT_H */ -#endif - - -/* Define to 1 if you have the header file. */ -#ifndef USED_FOR_TARGET -#define HAVE_DLFCN_H 1 -#endif - - -/* Define to 1 if you have the header file. */ -#ifndef USED_FOR_TARGET -#define HAVE_EXT_HASH_MAP 1 -#endif - - -/* Define to 1 if you have the header file. */ -#ifndef USED_FOR_TARGET -#define HAVE_FCNTL_H 1 -#endif - - -/* Define to 1 if you have the `feof_unlocked' function. */ -#ifndef USED_FOR_TARGET -#define HAVE_FEOF_UNLOCKED 1 -#endif - - -/* Define to 1 if you have the `ferror_unlocked' function. */ -#ifndef USED_FOR_TARGET -#define HAVE_FERROR_UNLOCKED 1 -#endif - - -/* Define to 1 if you have the `fflush_unlocked' function. */ -#ifndef USED_FOR_TARGET -#define HAVE_FFLUSH_UNLOCKED 1 -#endif - - -/* Define to 1 if you have the `fgetc_unlocked' function. */ -#ifndef USED_FOR_TARGET -#define HAVE_FGETC_UNLOCKED 1 -#endif - - -/* Define to 1 if you have the `fgets_unlocked' function. */ -#ifndef USED_FOR_TARGET -#define HAVE_FGETS_UNLOCKED 1 -#endif - - -/* Define to 1 if you have the `fileno_unlocked' function. */ -#ifndef USED_FOR_TARGET -#define HAVE_FILENO_UNLOCKED 1 -#endif - - -/* Define to 1 if you have the `fork' function. */ -#ifndef USED_FOR_TARGET -#define HAVE_FORK 1 -#endif - - -/* Define to 1 if you have the `fprintf_unlocked' function. */ -#ifndef USED_FOR_TARGET -/* #undef HAVE_FPRINTF_UNLOCKED */ -#endif - - -/* Define to 1 if you have the `fputc_unlocked' function. */ -#ifndef USED_FOR_TARGET -#define HAVE_FPUTC_UNLOCKED 1 -#endif - - -/* Define to 1 if you have the `fputs_unlocked' function. */ -#ifndef USED_FOR_TARGET -#define HAVE_FPUTS_UNLOCKED 1 -#endif - - -/* Define to 1 if you have the `fread_unlocked' function. */ -#ifndef USED_FOR_TARGET -#define HAVE_FREAD_UNLOCKED 1 -#endif - - -/* Define to 1 if you have the header file. */ -#ifndef USED_FOR_TARGET -#define HAVE_FTW_H 1 -#endif - - -/* Define to 1 if you have the `fwrite_unlocked' function. */ -#ifndef USED_FOR_TARGET -#define HAVE_FWRITE_UNLOCKED 1 -#endif - - -/* Define if your assembler supports specifying the alignment of objects - allocated using the GAS .comm command. */ -#ifndef USED_FOR_TARGET -/* #undef HAVE_GAS_ALIGNED_COMM */ -#endif - - -/* Define if your assembler supports .balign and .p2align. */ -#ifndef USED_FOR_TARGET -#define HAVE_GAS_BALIGN_AND_P2ALIGN 1 -#endif - - -/* Define 0/1 if your assembler supports CFI directives. */ -#define HAVE_GAS_CFI_DIRECTIVE 1 - -/* Define 0/1 if your assembler supports .cfi_personality. */ -#define HAVE_GAS_CFI_PERSONALITY_DIRECTIVE 1 - -/* Define 0/1 if your assembler supports .cfi_sections. */ -#define HAVE_GAS_CFI_SECTIONS_DIRECTIVE 1 - -/* Define if your assembler supports the .loc discriminator sub-directive. */ -#ifndef USED_FOR_TARGET -#define HAVE_GAS_DISCRIMINATOR 1 -#endif - - -/* Define if your assembler supports @gnu_unique_object. */ -#ifndef USED_FOR_TARGET -/* #undef HAVE_GAS_GNU_UNIQUE_OBJECT */ -#endif - - -/* Define if your assembler and linker support .hidden. */ -#define HAVE_GAS_HIDDEN 1 - -/* Define if your assembler supports .lcomm with an alignment field. */ -#ifndef USED_FOR_TARGET -/* #undef HAVE_GAS_LCOMM_WITH_ALIGNMENT */ -#endif - - -/* Define if your assembler supports .literal16. */ -#ifndef USED_FOR_TARGET -/* #undef HAVE_GAS_LITERAL16 */ -#endif - - -/* Define if your assembler supports specifying the maximum number of bytes to - skip when using the GAS .p2align command. */ -#ifndef USED_FOR_TARGET -#define HAVE_GAS_MAX_SKIP_P2ALIGN 1 -#endif - - -/* Define if your assembler supports the .set micromips directive */ -#ifndef USED_FOR_TARGET -/* #undef HAVE_GAS_MICROMIPS */ -#endif - - -/* Define if your assembler supports .nsubspa comdat option. */ -#ifndef USED_FOR_TARGET -/* #undef HAVE_GAS_NSUBSPA_COMDAT */ -#endif - - -/* Define if your assembler and linker support 32-bit section relative relocs - via '.secrel32 label'. */ -#ifndef USED_FOR_TARGET -/* #undef HAVE_GAS_PE_SECREL32_RELOC */ -#endif - - -/* Define if your assembler supports specifying the section flag e. */ -#ifndef USED_FOR_TARGET -/* #undef HAVE_GAS_SECTION_EXCLUDE */ -#endif - - -/* Define 0/1 if your assembler supports marking sections with SHF_MERGE flag. - */ -#ifndef USED_FOR_TARGET -#define HAVE_GAS_SHF_MERGE 1 -#endif - - -/* Define if your assembler supports .subsection and .subsection -1 starts - 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- -/* Define if your system supports gnu indirect functions. */ -#ifndef USED_FOR_TARGET -#define HAVE_GNU_INDIRECT_FUNCTION 0 -#endif - - -/* Define to 1 if using GNU ld. */ -#ifndef USED_FOR_TARGET -#define HAVE_GNU_LD 0 -#endif - - -/* Define if you have the iconv() function. */ -#ifndef USED_FOR_TARGET -#define HAVE_ICONV 1 -#endif - - -/* Define to 1 if you have the header file. */ -#ifndef USED_FOR_TARGET -#define HAVE_ICONV_H 1 -#endif - - -/* Define .init_array/.fini_array sections are available and working. */ -#ifndef USED_FOR_TARGET -/* #undef HAVE_INITFINI_ARRAY_SUPPORT */ -#endif - - -/* Define to 1 if the system has the type `intmax_t'. */ -#ifndef USED_FOR_TARGET -#define HAVE_INTMAX_T 1 -#endif - - -/* Define to 1 if the system has the type `intptr_t'. */ -#ifndef USED_FOR_TARGET -#define HAVE_INTPTR_T 1 -#endif - - -/* Define if you have a working header file. */ -#ifndef USED_FOR_TARGET -#define HAVE_INTTYPES_H 1 -#endif - - -/* Define if isl_options_set_schedule_serialize_sccs exists. */ -#ifndef USED_FOR_TARGET -/* #undef HAVE_ISL_OPTIONS_SET_SCHEDULE_SERIALIZE_SCCS */ -#endif - - -/* Define if isl_schedule_constraints_compute_schedule exists. */ -#ifndef USED_FOR_TARGET -/* #undef HAVE_ISL_SCHED_CONSTRAINTS_COMPUTE_SCHEDULE */ -#endif - - -/* Define to 1 if you have the `kill' function. */ -#ifndef USED_FOR_TARGET -#define HAVE_KILL 1 -#endif - - -/* Define if you have and nl_langinfo(CODESET). */ -#ifndef USED_FOR_TARGET -#define HAVE_LANGINFO_CODESET 1 -#endif - - -/* Define to 1 if you have the header file. */ -#ifndef USED_FOR_TARGET -#define HAVE_LANGINFO_H 1 -#endif - - -/* Define if your file defines LC_MESSAGES. */ -#ifndef USED_FOR_TARGET -#define HAVE_LC_MESSAGES 1 -#endif - - -/* Define to 1 if you have the header file. */ -#ifndef USED_FOR_TARGET -/* #undef HAVE_LDFCN_H */ -#endif - - -/* Define if your linker supports --as-needed/--no-as-needed or equivalent - options. */ -#ifndef USED_FOR_TARGET -#define HAVE_LD_AS_NEEDED 1 -#endif - - -/* Define if your linker supports --build-id. */ -#ifndef USED_FOR_TARGET -#define HAVE_LD_BUILDID 1 -#endif - - -/* Define if the linker supports clearing hardware capabilities via mapfile. - */ -#ifndef USED_FOR_TARGET -/* #undef HAVE_LD_CLEARCAP */ -#endif - - -/* Define to the level of your linker's compressed debug section support. */ -#ifndef USED_FOR_TARGET -#define HAVE_LD_COMPRESS_DEBUG 1 -#endif - - -/* Define if your linker supports --demangle option. */ -#ifndef USED_FOR_TARGET -/* #undef HAVE_LD_DEMANGLE */ -#endif - - -/* Define 0/1 if your linker supports CIE v3 in .eh_frame. */ -#ifndef USED_FOR_TARGET -#define HAVE_LD_EH_FRAME_CIEV3 1 -#endif - - -/* Define if your linker supports .eh_frame_hdr. */ -/* #undef HAVE_LD_EH_FRAME_HDR */ - -/* Define if your linker supports garbage collection of sections in presence - of EH frames. */ -#ifndef USED_FOR_TARGET -/* #undef HAVE_LD_EH_GC_SECTIONS */ -#endif - - -/* Define if your linker has buggy garbage collection of sections support when - .text.startup.foo like sections are used. */ -#ifndef USED_FOR_TARGET -#define HAVE_LD_EH_GC_SECTIONS_BUG 1 -#endif - - -/* Define if your PowerPC64 linker supports a large TOC. */ -#ifndef USED_FOR_TARGET -/* #undef HAVE_LD_LARGE_TOC */ -#endif - - -/* Define if your PowerPC64 linker only needs function descriptor syms. */ -#ifndef USED_FOR_TARGET -/* #undef HAVE_LD_NO_DOT_SYMS */ -#endif - - -/* Define if your linker can relax absolute .eh_frame personality pointers - into PC-relative form. */ -#ifndef USED_FOR_TARGET -/* #undef HAVE_LD_PERSONALITY_RELAXATION */ -#endif - - -/* Define if your linker supports PIE option. */ -#ifndef USED_FOR_TARGET -#define HAVE_LD_PIE 1 -#endif - - -/* Define 0/1 if your linker supports -pie option with copy reloc. */ -#ifndef USED_FOR_TARGET -#define HAVE_LD_PIE_COPYRELOC 0 -#endif - - -/* Define if your linker links a mix of read-only and read-write sections into - a read-write section. */ -#ifndef USED_FOR_TARGET -/* #undef HAVE_LD_RO_RW_SECTION_MIXING */ -#endif - - -/* Define if your linker supports the *_sol2 emulations. */ -#ifndef USED_FOR_TARGET -/* #undef HAVE_LD_SOL2_EMULATION */ -#endif - - -/* Define if your linker supports -Bstatic/-Bdynamic or equivalent options. */ -#ifndef USED_FOR_TARGET -#define HAVE_LD_STATIC_DYNAMIC 1 -#endif - - -/* Define if your linker supports --sysroot. */ -#ifndef USED_FOR_TARGET -#define HAVE_LD_SYSROOT 1 -#endif - - -/* Define to 1 if you have the header file. */ -#ifndef USED_FOR_TARGET -#define HAVE_LIMITS_H 1 -#endif - - -/* Define to 1 if you have the header file. */ -#ifndef USED_FOR_TARGET -#define HAVE_LOCALE_H 1 -#endif - - -/* Define to 1 if the system has the type `long long'. */ -#ifndef USED_FOR_TARGET -#define HAVE_LONG_LONG 1 -#endif - - -/* Define to 1 if the system has the type `long long int'. */ -#ifndef USED_FOR_TARGET -#define HAVE_LONG_LONG_INT 1 -#endif - - -/* Define to the level of your linker's plugin support. */ -#ifndef USED_FOR_TARGET -#define HAVE_LTO_PLUGIN 2 -#endif - - -/* Define to 1 if you have the `madvise' function. */ -#ifndef USED_FOR_TARGET -#define HAVE_MADVISE 1 -#endif - - -/* Define to 1 if you have the header file. */ -#ifndef USED_FOR_TARGET -#define HAVE_MALLOC_H 1 -#endif - - -/* Define to 1 if you have the `mbstowcs' function. */ -#ifndef USED_FOR_TARGET -#define HAVE_MBSTOWCS 1 -#endif - - -/* Define if valgrind's memcheck.h header is installed. */ -#ifndef USED_FOR_TARGET -/* #undef HAVE_MEMCHECK_H */ -#endif - - -/* Define to 1 if you have the header file. */ -#ifndef USED_FOR_TARGET -#define HAVE_MEMORY_H 1 -#endif - - -/* Define to 1 if you have the `mmap' function. */ -#ifndef USED_FOR_TARGET -#define HAVE_MMAP 1 -#endif - - -/* Define if mmap with MAP_ANON(YMOUS) works. */ -#ifndef USED_FOR_TARGET -#define HAVE_MMAP_ANON 1 -#endif - - -/* Define if mmap of /dev/zero works. */ -#ifndef USED_FOR_TARGET -#define HAVE_MMAP_DEV_ZERO 1 -#endif - - -/* Define if read-only mmap of a plain file works. */ -#ifndef USED_FOR_TARGET -#define HAVE_MMAP_FILE 1 -#endif - - -/* Define to 1 if you have the `nl_langinfo' function. */ -#ifndef USED_FOR_TARGET -#define HAVE_NL_LANGINFO 1 -#endif - - -/* Define to 1 if you have the `popen' function. */ -#ifndef USED_FOR_TARGET -#define HAVE_POPEN 1 -#endif - - -/* Define to 1 if you have the `putchar_unlocked' function. */ -#ifndef USED_FOR_TARGET -#define HAVE_PUTCHAR_UNLOCKED 1 -#endif - - -/* Define to 1 if you have the `putc_unlocked' function. */ -#ifndef USED_FOR_TARGET -#define HAVE_PUTC_UNLOCKED 1 -#endif - - -/* Define to 1 if you have the `setlocale' function. */ -#ifndef USED_FOR_TARGET -#define HAVE_SETLOCALE 1 -#endif - - -/* Define to 1 if you have the `setrlimit' function. */ -#ifndef USED_FOR_TARGET -#define HAVE_SETRLIMIT 1 -#endif - - -/* Define if the system-provided CRTs are present on Solaris. */ -#ifndef USED_FOR_TARGET -/* #undef HAVE_SOLARIS_CRTS */ -#endif - - -/* Define to 1 if you have the header file. */ -#ifndef USED_FOR_TARGET -#define HAVE_STDDEF_H 1 -#endif - - -/* Define to 1 if you have the header file. */ -#ifndef USED_FOR_TARGET -#define HAVE_STDINT_H 1 -#endif - - -/* Define to 1 if you have the header file. */ -#ifndef USED_FOR_TARGET -#define HAVE_STDLIB_H 1 -#endif - - -/* Define to 1 if you have the header file. */ -#ifndef USED_FOR_TARGET -#define HAVE_STRINGS_H 1 -#endif - - -/* Define to 1 if you have the header file. */ -#ifndef USED_FOR_TARGET -#define HAVE_STRING_H 1 -#endif - - -/* Define to 1 if you have the `strsignal' function. */ -#ifndef USED_FOR_TARGET -#define HAVE_STRSIGNAL 1 -#endif - - -/* Define if defines struct tms. */ -#ifndef USED_FOR_TARGET -#define HAVE_STRUCT_TMS 1 -#endif - - -/* Define to 1 if you have the `sysconf' function. */ -#ifndef USED_FOR_TARGET -#define HAVE_SYSCONF 1 -#endif - - -/* Define to 1 if you have the header file. */ -#ifndef USED_FOR_TARGET -#define HAVE_SYS_FILE_H 1 -#endif - - -/* Define to 1 if you have the header file. */ -#ifndef USED_FOR_TARGET -#define HAVE_SYS_MMAN_H 1 -#endif - - -/* Define to 1 if you have the header file. */ -#ifndef USED_FOR_TARGET -#define HAVE_SYS_PARAM_H 1 -#endif - - -/* Define to 1 if you have the header file. */ -#ifndef USED_FOR_TARGET -#define HAVE_SYS_RESOURCE_H 1 -#endif - - -/* Define if your target C library provides sys/sdt.h */ -/* #undef HAVE_SYS_SDT_H */ - -/* Define to 1 if you have the header file. */ -#ifndef USED_FOR_TARGET -#define HAVE_SYS_STAT_H 1 -#endif - - -/* Define to 1 if you have the header file. */ -#ifndef USED_FOR_TARGET -#define HAVE_SYS_TIMES_H 1 -#endif - - -/* Define to 1 if you have the header file. */ -#ifndef USED_FOR_TARGET -#define HAVE_SYS_TIME_H 1 -#endif - - -/* Define to 1 if you have the header file. */ -#ifndef USED_FOR_TARGET -#define HAVE_SYS_TYPES_H 1 -#endif - - -/* Define to 1 if you have that is POSIX.1 compatible. */ -#ifndef USED_FOR_TARGET -#define HAVE_SYS_WAIT_H 1 -#endif - - -/* Define to 1 if you have the `times' function. */ -#ifndef USED_FOR_TARGET -#define HAVE_TIMES 1 -#endif - - -/* Define to 1 if you have the header file. */ -#ifndef USED_FOR_TARGET -#define HAVE_TIME_H 1 -#endif - - -/* Define to 1 if you have the header file. */ -#ifndef USED_FOR_TARGET -#define HAVE_TR1_UNORDERED_MAP 1 -#endif - - -/* Define to 1 if the system has the type `uintmax_t'. */ -#ifndef USED_FOR_TARGET -#define HAVE_UINTMAX_T 1 -#endif - - -/* Define to 1 if the system has the type `uintptr_t'. */ -#ifndef USED_FOR_TARGET -#define HAVE_UINTPTR_T 1 -#endif - - -/* Define to 1 if you have the header file. */ -#ifndef USED_FOR_TARGET -#define HAVE_UNISTD_H 1 -#endif - - -/* Define to 1 if you have the header file. */ -#ifndef USED_FOR_TARGET -/* #undef HAVE_UNORDERED_MAP */ -#endif - - -/* Define to 1 if the system has the type `unsigned long long int'. */ -#ifndef USED_FOR_TARGET -#define HAVE_UNSIGNED_LONG_LONG_INT 1 -#endif - - -/* Define if valgrind's valgrind/memcheck.h header is installed. */ -#ifndef USED_FOR_TARGET -/* #undef HAVE_VALGRIND_MEMCHECK_H */ -#endif - - -/* Define to 1 if you have the `vfork' function. */ -#ifndef USED_FOR_TARGET -#define HAVE_VFORK 1 -#endif - - -/* Define to 1 if you have the header file. */ -#ifndef USED_FOR_TARGET -/* #undef HAVE_VFORK_H */ -#endif - - -/* Define to 1 if you have the header file. */ -#ifndef USED_FOR_TARGET -#define HAVE_WCHAR_H 1 -#endif - - -/* Define to 1 if you have the `wcswidth' function. */ -#ifndef USED_FOR_TARGET -#define HAVE_WCSWIDTH 1 -#endif - - -/* Define to 1 if `fork' works. */ -#ifndef USED_FOR_TARGET -#define HAVE_WORKING_FORK 1 -#endif - - -/* Define this macro if mbstowcs does not crash when its first argument is - NULL. */ -#ifndef USED_FOR_TARGET -#define HAVE_WORKING_MBSTOWCS 1 -#endif - - -/* Define to 1 if `vfork' works. */ -#ifndef USED_FOR_TARGET -#define HAVE_WORKING_VFORK 1 -#endif - - -/* Define if isl is in use. */ -#ifndef USED_FOR_TARGET -/* #undef HAVE_isl */ -#endif - - -/* Define if F_SETLKW supported by fcntl. */ -#ifndef USED_FOR_TARGET -#define HOST_HAS_F_SETLKW 1 -#endif - - -/* Define as const if the declaration of iconv() needs const. */ -#ifndef USED_FOR_TARGET -#define ICONV_CONST -#endif - - -/* Define if int64_t uses long as underlying type. */ -#ifndef USED_FOR_TARGET -#define INT64_T_IS_LONG 1 -#endif - - -/* Define to the linker option to ignore unused dependencies. */ -#ifndef USED_FOR_TARGET -#define LD_AS_NEEDED_OPTION "--as-needed" -#endif - - -/* Define to the linker option to enable compressed debug sections. */ -#ifndef USED_FOR_TARGET -#define LD_COMPRESS_DEBUG_OPTION "" -#endif - - -/* Define to the linker option to enable use of shared objects. */ -#ifndef USED_FOR_TARGET -#define LD_DYNAMIC_OPTION "-Bdynamic" -#endif - - -/* Define to the linker option to keep unused dependencies. */ -#ifndef USED_FOR_TARGET -#define LD_NO_AS_NEEDED_OPTION "--no-as-needed" -#endif - - -/* Define to the linker option to disable use of shared objects. */ -#ifndef USED_FOR_TARGET -#define LD_STATIC_OPTION "-Bstatic" -#endif - - -/* The linker hash style */ -#ifndef USED_FOR_TARGET -/* #undef LINKER_HASH_STYLE */ -#endif - - -/* Define to the name of the LTO plugin DSO that must be passed to the - linker's -plugin=LIB option. */ -#ifndef USED_FOR_TARGET -#define LTOPLUGINSONAME "liblto_plugin.so" -#endif - - -/* Define to the sub-directory in which libtool stores uninstalled libraries. - */ -#ifndef USED_FOR_TARGET -#define LT_OBJDIR ".libs/" -#endif - - -/* Define if host mkdir takes a single argument. */ -#ifndef USED_FOR_TARGET -/* #undef MKDIR_TAKES_ONE_ARG */ -#endif - - -/* Define to hold the list of target names suitable for offloading. */ -#ifndef USED_FOR_TARGET -#define OFFLOAD_TARGETS "" -#endif - - -/* Define to the address where bug reports for this package should be sent. */ -#ifndef USED_FOR_TARGET -#define PACKAGE_BUGREPORT "" -#endif - - -/* Define to the full name of this package. */ -#ifndef USED_FOR_TARGET -#define PACKAGE_NAME "" -#endif - - -/* Define to the full name and version of this package. */ -#ifndef USED_FOR_TARGET -#define PACKAGE_STRING "" -#endif - - -/* Define to the one symbol short name of this package. */ -#ifndef USED_FOR_TARGET -#define PACKAGE_TARNAME "" -#endif - - -/* Define to the home page for this package. */ -#ifndef USED_FOR_TARGET -#define PACKAGE_URL "" -#endif - - -/* Define to the version of this package. */ -#ifndef USED_FOR_TARGET -#define PACKAGE_VERSION "" -#endif - - -/* Specify plugin linker */ -#ifndef USED_FOR_TARGET -#define PLUGIN_LD_SUFFIX "ld" -#endif - - -/* Define to PREFIX/include if cpp should also search that directory. */ -#ifndef USED_FOR_TARGET -/* #undef PREFIX_INCLUDE_DIR */ -#endif - - -/* The size of `int', as computed by sizeof. */ -#ifndef USED_FOR_TARGET -#define SIZEOF_INT 4 -#endif - - -/* The size of `long', as computed by sizeof. */ -#ifndef USED_FOR_TARGET -#define SIZEOF_LONG 8 -#endif - - -/* The size of `long long', as computed by sizeof. */ -#ifndef USED_FOR_TARGET -#define SIZEOF_LONG_LONG 8 -#endif - - -/* The size of `short', as computed by sizeof. */ -#ifndef USED_FOR_TARGET -#define SIZEOF_SHORT 2 -#endif - - -/* The size of `void *', as computed by sizeof. */ -#ifndef USED_FOR_TARGET -#define SIZEOF_VOID_P 8 -#endif - - -/* Define to 1 if you have the ANSI C header files. */ -#ifndef USED_FOR_TARGET -#define STDC_HEADERS 1 -#endif - - -/* Define if you can safely include both and . */ -#ifndef USED_FOR_TARGET -#define STRING_WITH_STRINGS 1 -#endif - - -/* Define if TFmode long double should be the default */ -#ifndef USED_FOR_TARGET -/* #undef TARGET_DEFAULT_LONG_DOUBLE_128 */ -#endif - - -/* Define if your target C library provides the `dl_iterate_phdr' function. */ -/* #undef TARGET_DL_ITERATE_PHDR */ - -/* GNU C Library major version number used on the target, or 0. */ -#ifndef USED_FOR_TARGET -#define TARGET_GLIBC_MAJOR 0 -#endif - - -/* GNU C Library minor version number used on the target, or 0. */ -#ifndef USED_FOR_TARGET -#define TARGET_GLIBC_MINOR 0 -#endif - - -/* Define if your target C library provides stack protector support */ -#ifndef USED_FOR_TARGET -/* #undef TARGET_LIBC_PROVIDES_SSP */ -#endif - - -/* Define to 1 if you can safely include both and . */ -#ifndef USED_FOR_TARGET -#define TIME_WITH_SYS_TIME 1 -#endif - - -/* Define to the flag used to mark TLS sections if the default (`T') doesn't - work. */ -#ifndef USED_FOR_TARGET -/* #undef TLS_SECTION_ASM_FLAG */ -#endif - - -/* Define if your assembler mis-optimizes .eh_frame data. */ -#ifndef USED_FOR_TARGET -/* #undef USE_AS_TRADITIONAL_FORMAT */ -#endif - - -/* Define if you want to generate code by default that assumes that the Cygwin - DLL exports wrappers to support libstdc++ function replacement. */ -#ifndef USED_FOR_TARGET -/* #undef USE_CYGWIN_LIBSTDCXX_WRAPPERS */ -#endif - - -/* Define to 1 if the 'long long' type is wider than 'long' but still - efficiently supported by the host hardware. */ -#ifndef USED_FOR_TARGET -/* #undef USE_LONG_LONG_FOR_WIDEST_FAST_INT */ -#endif - - -/* Define if we should use leading underscore on 64 bit mingw targets */ -#ifndef USED_FOR_TARGET -/* #undef USE_MINGW64_LEADING_UNDERSCORES */ -#endif - - -/* Enable extensions on AIX 3, Interix. */ -#ifndef _ALL_SOURCE -# define _ALL_SOURCE 1 -#endif -/* Enable GNU extensions on systems that have them. */ -#ifndef _GNU_SOURCE -# define _GNU_SOURCE 1 -#endif -/* Enable threading extensions on Solaris. */ -#ifndef _POSIX_PTHREAD_SEMANTICS -# define _POSIX_PTHREAD_SEMANTICS 1 -#endif -/* Enable extensions on HP NonStop. */ -#ifndef _TANDEM_SOURCE -# define _TANDEM_SOURCE 1 -#endif -/* Enable general extensions on Solaris. */ -#ifndef __EXTENSIONS__ -# define __EXTENSIONS__ 1 -#endif - - -/* Define to be the last component of the Windows registry key under which to - look for installation paths. The full key used will be - HKEY_LOCAL_MACHINE/SOFTWARE/Free Software Foundation/{WIN32_REGISTRY_KEY}. - The default is the GCC version number. */ -#ifndef USED_FOR_TARGET -/* #undef WIN32_REGISTRY_KEY */ -#endif - - -/* Define WORDS_BIGENDIAN to 1 if your processor stores words with the most - significant byte first (like Motorola and SPARC, unlike Intel). */ -#if defined AC_APPLE_UNIVERSAL_BUILD -# if defined __BIG_ENDIAN__ -# define WORDS_BIGENDIAN 1 -# endif -#else -# ifndef WORDS_BIGENDIAN -/* # undef WORDS_BIGENDIAN */ -# endif -#endif - -/* Number of bits in a file offset, on hosts where this is settable. */ -#ifndef USED_FOR_TARGET -/* #undef _FILE_OFFSET_BITS */ -#endif - - -/* Define for large files, on AIX-style hosts. */ -#ifndef USED_FOR_TARGET -/* #undef _LARGE_FILES */ -#endif - - -/* Define to 1 if on MINIX. */ -#ifndef USED_FOR_TARGET -/* #undef _MINIX */ -#endif - - -/* Define to 2 if the system does not provide POSIX.1 features except with - this defined. */ -#ifndef USED_FOR_TARGET -/* #undef _POSIX_1_SOURCE */ -#endif - - -/* Define to 1 if you need to in order for `stat' and other things to work. */ -#ifndef USED_FOR_TARGET -/* #undef _POSIX_SOURCE */ -#endif - - -/* Define for Solaris 2.5.1 so the uint32_t typedef from , - , or is not used. If the typedef were allowed, the - #define below would cause a syntax error. */ -#ifndef USED_FOR_TARGET -/* #undef _UINT32_T */ -#endif - - -/* Define for Solaris 2.5.1 so the uint64_t typedef from , - , or is not used. If the typedef were allowed, the - #define below would cause a syntax error. */ -#ifndef USED_FOR_TARGET -/* #undef _UINT64_T */ -#endif - - -/* Define for Solaris 2.5.1 so the uint8_t typedef from , - , or is not used. If the typedef were allowed, the - #define below would cause a syntax error. */ -#ifndef USED_FOR_TARGET -/* #undef _UINT8_T */ -#endif - - -/* Define to `char *' if does not define. */ -#ifndef USED_FOR_TARGET -/* #undef caddr_t */ -#endif - - -/* Define to `__inline__' or `__inline' if that's what the C compiler - calls it, or to nothing if 'inline' is not supported under any name. */ -#ifndef __cplusplus -/* #undef inline */ -#endif - -/* Define to the type of a signed integer type of width exactly 16 bits if - such a type exists and the standard includes do not define it. */ -#ifndef USED_FOR_TARGET -/* #undef int16_t */ -#endif - - -/* Define to the type of a signed integer type of width exactly 32 bits if - such a type exists and the standard includes do not define it. */ -#ifndef USED_FOR_TARGET -/* #undef int32_t */ -#endif - - -/* Define to the type of a signed integer type of width exactly 64 bits if - such a type exists and the standard includes do not define it. */ -#ifndef USED_FOR_TARGET -/* #undef int64_t */ -#endif - - -/* Define to the type of a signed integer type of width exactly 8 bits if such - a type exists and the standard includes do not define it. */ -#ifndef USED_FOR_TARGET -/* #undef int8_t */ -#endif - - -/* Define to the widest signed integer type if and do - not define. */ -#ifndef USED_FOR_TARGET -/* #undef intmax_t */ -#endif - - -/* Define to the type of a signed integer type wide enough to hold a pointer, - if such a type exists, and if the system does not define it. */ -#ifndef USED_FOR_TARGET -/* #undef intptr_t */ -#endif - - -/* Define to `int' if does not define. */ -#ifndef USED_FOR_TARGET -/* #undef pid_t */ -#endif - - -/* Define to `long' if doesn't define. */ -#ifndef USED_FOR_TARGET -/* #undef rlim_t */ -#endif - - -/* Define to `int' if does not define. */ -#ifndef USED_FOR_TARGET -/* #undef ssize_t */ -#endif - - -/* Define to the type of an unsigned integer type of width exactly 16 bits if - such a type exists and the standard includes do not define it. */ -#ifndef USED_FOR_TARGET -/* #undef uint16_t */ -#endif - - -/* Define to the type of an unsigned integer type of width exactly 32 bits if - such a type exists and the standard includes do not define it. */ -#ifndef USED_FOR_TARGET -/* #undef uint32_t */ -#endif - - -/* Define to the type of an unsigned integer type of width exactly 64 bits if - such a type exists and the standard includes do not define it. */ -#ifndef USED_FOR_TARGET -/* #undef uint64_t */ -#endif - - -/* Define to the type of an unsigned integer type of width exactly 8 bits if - such a type exists and the standard includes do not define it. */ -#ifndef USED_FOR_TARGET -/* #undef uint8_t */ -#endif - - -/* Define to the widest unsigned integer type if and - do not define. */ -#ifndef USED_FOR_TARGET -/* #undef uintmax_t */ -#endif - - -/* Define to the type of an unsigned integer type wide enough to hold a - pointer, if such a type exists, and if the system does not define it. */ -#ifndef USED_FOR_TARGET -/* #undef uintptr_t */ -#endif - - -/* Define as `fork' if `vfork' does not work. */ -#ifndef USED_FOR_TARGET -/* #undef vfork */ -#endif - diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/auto-profile.h b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/auto-profile.h deleted file mode 100644 index 6ef34b0..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/auto-profile.h +++ /dev/null @@ -1,31 +0,0 @@ -/* auto-profile.h - Defines data exported from auto-profile.c - Copyright (C) 2014-2015 Free Software Foundation, Inc. - Contributed by Dehao Chen (dehao@google.com) - -This file is part of GCC. - -GCC is free software; you can redistribute it and/or modify it under -the terms of the GNU General Public License as published by the Free -Software Foundation; either version 3, or (at your option) any later -version. - -GCC is distributed in the hope that it will be useful, but WITHOUT ANY -WARRANTY; without even the implied warranty of MERCHANTABILITY or -FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -for more details. - -You should have received a copy of the GNU General Public License -along with GCC; see the file COPYING3. If not see -. */ - -#ifndef AUTO_PROFILE_H -#define AUTO_PROFILE_H - -/* Read, process, finalize AutoFDO data structures. */ -extern void read_autofdo_file (void); -extern void end_auto_profile (void); - -/* Returns TRUE if EDGE is hot enough to be inlined early. */ -extern bool afdo_callsite_hot_enough_for_early_inline (struct cgraph_edge *); - -#endif /* AUTO_PROFILE_H */ diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/b-header-vars b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/b-header-vars deleted file mode 100644 index 44fd5c0..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/b-header-vars +++ /dev/null @@ -1,88 +0,0 @@ -USER_H=stdfix.h stdfix-gcc.h -HASHTAB_H=hashtab.h -OBSTACK_H=obstack.h -SPLAY_TREE_H=splay-tree.h -XREGEX_H=xregex.h -FNMATCH_H=fnmatch.h -LINKER_PLUGIN_API_H=plugin-api.h -BCONFIG_H=bconfig.h auto-host.h ansidecl.h -CONFIG_H=config.h auto-host.h ansidecl.h -TCONFIG_H=tconfig.h auto-host.h ansidecl.h -TM_P_H=tm_p.h config/avr/avr-protos.h tm-preds.h -GTM_H=tm.h options.h config/elfos.h defaults.h insn-constants.h -TM_H=tm.h options.h config/elfos.h defaults.h insn-constants.h insn-flags.h options.h flag-types.h -DUMPFILE_H=line-map.h dumpfile.h -VEC_H=vec.h statistics.h ggc.h gtype-desc.h statistics.h -HASH_TABLE_H=hashtab.h hash-table.h -EXCEPT_H=except.h hashtab.h -TARGET_H=tm.h options.h config/elfos.h defaults.h insn-constants.h insn-flags.h options.h flag-types.h target.h target.def target-hooks-macros.h insn-modes.h insn-codes.h -C_TARGET_H=c-family/c-target.h c-family/c-target.def target-hooks-macros.h -COMMON_TARGET_H=common/common-target.h common-target.def target-hooks-macros.h -MACHMODE_H=machmode.h mode-classes.def insn-modes.h -HOOKS_H=hooks.h machmode.h mode-classes.def insn-modes.h -HOSTHOOKS_DEF_H=hosthooks-def.h hooks.h machmode.h mode-classes.def insn-modes.h -LANGHOOKS_DEF_H=langhooks-def.h hooks.h machmode.h mode-classes.def insn-modes.h -TARGET_DEF_H=target-def.h target-hooks-def.h hooks.h machmode.h mode-classes.def insn-modes.h targhooks.h -C_TARGET_DEF_H=c-family/c-target-def.h c-family/c-target-hooks-def.h tree.h tree-core.h coretypes.h all-tree.def tree.def c-family/c-common.def common-targhooks.h -RTL_BASE_H=coretypes.h rtl.h rtl.def machmode.h mode-classes.def insn-modes.h reg-notes.def insn-notes.def hashtab.h -FIXED_VALUE_H=fixed-value.h machmode.h mode-classes.def insn-modes.h double-int.h -RTL_H=coretypes.h rtl.h rtl.def machmode.h mode-classes.def insn-modes.h reg-notes.def insn-notes.def hashtab.h flags.h flag-types.h options.h flag-types.h genrtl.h -READ_MD_H=hashtab.h read-md.h -PARAMS_H=params.h params.def -INTERNAL_FN_H=internal-fn.h internal-fn.def -TREE_CORE_H=tree-core.h coretypes.h all-tree.def tree.def c-family/c-common.def obstack.h flags.h flag-types.h options.h flag-types.h real.h machmode.h mode-classes.def insn-modes.h fixed-value.h machmode.h mode-classes.def insn-modes.h double-int.h -TREE_H=tree.h tree-core.h coretypes.h all-tree.def tree.def c-family/c-common.def obstack.h flags.h flag-types.h options.h flag-types.h real.h machmode.h mode-classes.def insn-modes.h fixed-value.h machmode.h mode-classes.def insn-modes.h double-int.h tree-check.h -REGSET_H=regset.h bitmap.h hashtab.h statistics.h hard-reg-set.h -BASIC_BLOCK_H=basic-block.h predict.h predict.def vec.h statistics.h ggc.h gtype-desc.h statistics.h function.h line-map.h input.h machmode.h mode-classes.def insn-modes.h cfg-flags.def cfghooks.h -GIMPLE_H=gimple.h gimple.def gsstruct.def vec.h statistics.h ggc.h gtype-desc.h statistics.h ggc.h gtype-desc.h statistics.h basic-block.h predict.h predict.def vec.h statistics.h ggc.h gtype-desc.h statistics.h function.h hashtab.h hash-table.h is-a.h -GCOV_IO_H=gcov-io.h gcov-iov.h auto-host.h gcov-counter.def -RECOG_H=recog.h -EMIT_RTL_H=emit-rtl.h -FLAGS_H=flags.h flag-types.h options.h flag-types.h -OPTIONS_H=options.h flag-types.h -FUNCTION_H=function.h line-map.h input.h machmode.h mode-classes.def insn-modes.h -EXPR_H=expr.h insn-config.h function.h obstack.h flags.h flag-types.h options.h flag-types.h real.h machmode.h mode-classes.def insn-modes.h fixed-value.h machmode.h mode-classes.def insn-modes.h double-int.h tree-check.h machmode.h mode-classes.def insn-modes.h emit-rtl.h -OPTABS_H=optabs.h insn-codes.h insn-opinit.h -REGS_H=regs.h machmode.h mode-classes.def insn-modes.h hard-reg-set.h -CFGLOOP_H=cfgloop.h basic-block.h predict.h predict.def vec.h statistics.h ggc.h gtype-desc.h statistics.h function.h hashtab.h statistics.h sbitmap.h -IPA_UTILS_H=ipa-utils.h tree.h tree-core.h coretypes.h all-tree.def tree.def c-family/c-common.def plugin-api.h is-a.h -IPA_REFERENCE_H=ipa-reference.h bitmap.h obstack.h flags.h flag-types.h options.h flag-types.h real.h machmode.h mode-classes.def insn-modes.h fixed-value.h machmode.h mode-classes.def insn-modes.h double-int.h tree-check.h -CGRAPH_H=cgraph.h vec.h statistics.h ggc.h gtype-desc.h statistics.h tree.h tree-core.h coretypes.h all-tree.def tree.def c-family/c-common.def plugin-api.h is-a.h -DF_H=df.h bitmap.h line-map.h input.h machmode.h mode-classes.def insn-modes.h cfg-flags.def cfghooks.h alloc-pool.h timevar.h timevar.def -RESOURCE_H=resource.h hard-reg-set.h df.h bitmap.h line-map.h input.h machmode.h mode-classes.def insn-modes.h cfg-flags.def cfghooks.h alloc-pool.h timevar.h timevar.def -GCC_H=gcc.h version.h diagnostic-core.h line-map.h input.h bversion.h diagnostic.def -GGC_H=ggc.h gtype-desc.h statistics.h -TIMEVAR_H=timevar.h timevar.def -INSN_ATTR_H=insn-attr.h insn-attr-common.h insn-addr.h -INSN_ADDR_H=insn-addr.h -C_COMMON_H=c-family/c-common.h c-family/c-common.def tree.h tree-core.h coretypes.h all-tree.def tree.def c-family/c-common.def line-map.h input.h bversion.h diagnostic.def -C_PRAGMA_H=c-family/c-pragma.h cpplib.h -C_TREE_H=c/c-tree.h c-family/c-common.h c-family/c-common.def tree.h tree-core.h coretypes.h all-tree.def tree.def c-family/c-common.def obstack.h wide-int-print.h -SYSTEM_H=system.h hwint.h filenames.h -PREDICT_H=predict.h predict.def -CPPLIB_H=cpplib.h -INPUT_H=line-map.h input.h -OPTS_H=obstack.h -SYMTAB_H=obstack.h -CPP_ID_DATA_H=cpp-id-data.h -CPP_INTERNAL_H=cpp-id-data.h -TREE_DUMP_H=tree-dump.h line-map.h dumpfile.h -TREE_PASS_H=tree-pass.h timevar.h timevar.def line-map.h dumpfile.h -TREE_SSA_H=tree-ssa.h tree-ssa-operands.h bitmap.h obstack.h flags.h flag-types.h options.h flag-types.h real.h machmode.h mode-classes.def insn-modes.h fixed-value.h machmode.h mode-classes.def insn-modes.h double-int.h tree-check.h tree-ssa-alias.h -PRETTY_PRINT_H=pretty-print.h obstack.h wide-int-print.h -TREE_PRETTY_PRINT_H=tree-pretty-print.h pretty-print.h obstack.h wide-int-print.h -GIMPLE_PRETTY_PRINT_H=gimple-pretty-print.h tree-pretty-print.h pretty-print.h obstack.h wide-int-print.h -DIAGNOSTIC_CORE_H=diagnostic-core.h line-map.h input.h bversion.h diagnostic.def -DIAGNOSTIC_H=diagnostic.h diagnostic-core.h obstack.h wide-int-print.h -C_PRETTY_PRINT_H=c-family/c-pretty-print.h pretty-print.h obstack.h flags.h flag-types.h options.h flag-types.h real.h machmode.h mode-classes.def insn-modes.h fixed-value.h machmode.h mode-classes.def insn-modes.h double-int.h tree-check.h -TREE_INLINE_H=tree-inline.h -REAL_H=real.h machmode.h mode-classes.def insn-modes.h -LTO_STREAMER_H=lto-streamer.h obstack.h wide-int-print.h alloc-pool.h -IPA_PROP_H=ipa-prop.h tree.h tree-core.h coretypes.h all-tree.def tree.def c-family/c-common.def hashtab.h hash-table.h is-a.h alloc-pool.h -BITMAP_H=bitmap.h hashtab.h statistics.h -GCC_PLUGIN_H=gcc-plugin.h highlev-plugin-common.h plugin.def config.h auto-host.h hashtab.h -PLUGIN_H=plugin.h gcc-plugin.h highlev-plugin-common.h plugin.def config.h auto-host.h hashtab.h -PLUGIN_VERSION_H=plugin-version.h configargs.h -CONTEXT_H=context.h -GTFILES_H=gt-coverage.h gt-caller-save.h gt-symtab.h gt-alias.h gt-bitmap.h gt-cselib.h gt-cgraph.h gt-ipa-prop.h gt-ipa-cp.h gt-dbxout.h gt-dwarf2asm.h gt-dwarf2cfi.h gt-dwarf2out.h gt-tree-vect-generic.h gt-dojump.h gt-emit-rtl.h gt-explow.h gt-expr.h gt-function.h gt-except.h gt-gcse.h gt-godump.h gt-lists.h gt-optabs.h gt-profile.h gt-mcf.h gt-reg-stack.h gt-cfgrtl.h gt-sdbout.h gt-stor-layout.h gt-stringpool.h gt-tree.h gt-varasm.h gt-tree-chkp.h gt-tree-ssanames.h gt-tree-eh.h gt-tree-ssa-address.h gt-tree-cfg.h gt-tree-dfa.h gt-tree-iterator.h gt-gimple-expr.h gt-tree-scalar-evolution.h gt-tree-profile.h gt-tree-nested.h gt-omp-low.h gt-targhooks.h gt-avr.h gt-passes.h gt-cgraphunit.h gt-cgraphclones.h gt-tree-phinodes.h gt-trans-mem.h gt-vtable-verify.h gt-asan.h gt-ubsan.h gt-tsan.h gt-sanopt.h gt-ipa-devirt.h gt-ada-decl.h gt-ada-trans.h gt-ada-utils.h gt-ada-misc.h gt-c-c-lang.h gt-c-c-decl.h gt-c-family-c-common.h gt-c-family-c-cppbuiltin.h gt-c-family-c-pragma.h gt-c-c-objc-common.h gt-c-c-parser.h gt-cp-rtti.h gt-cp-mangle.h gt-cp-name-lookup.h gt-cp-call.h gt-cp-decl.h gt-cp-decl2.h gt-cp-pt.h gt-cp-repo.h gt-cp-semantics.h gt-cp-tree.h gt-cp-parser.h gt-cp-method.h gt-cp-typeck2.h gt-c-family-c-common.h gt-c-family-c-lex.h gt-c-family-c-pragma.h gt-cp-class.h gt-cp-cp-objcp-common.h gt-cp-cp-lang.h gt-cp-except.h gt-cp-vtable-class-hierarchy.h gt-cp-constexpr.h gt-fortran-f95-lang.h gt-fortran-trans-decl.h gt-fortran-trans-intrinsic.h gt-fortran-trans-io.h gt-fortran-trans-stmt.h gt-fortran-trans-types.h gt-go-go-lang.h gt-java-builtins.h gt-java-class.h gt-java-constants.h gt-java-decl.h gt-java-expr.h gt-java-jcf-parse.h gt-java-lang.h gt-java-mangle.h gt-java-resource.h gt-jit-dummy-frontend.h gt-lto-lto-lang.h gt-lto-lto.h gt-objc-objc-act.h gt-objc-objc-runtime-shared-support.h gt-objc-objc-gnu-runtime-abi-01.h gt-objc-objc-next-runtime-abi-01.h gt-objc-objc-next-runtime-abi-02.h gt-c-c-parser.h gt-c-c-decl.h gt-c-c-objc-common.h gt-c-family-c-common.h gt-c-family-c-cppbuiltin.h gt-c-family-c-pragma.h gt-cp-rtti.h gt-cp-mangle.h gt-cp-name-lookup.h gt-cp-call.h gt-cp-decl.h gt-cp-decl2.h gt-cp-pt.h gt-cp-repo.h gt-cp-semantics.h gt-cp-tree.h gt-cp-parser.h gt-cp-method.h gt-cp-typeck2.h gt-c-family-c-common.h gt-c-family-c-lex.h gt-c-family-c-pragma.h gt-cp-class.h gt-cp-cp-objcp-common.h gt-cp-except.h gt-cp-vtable-class-hierarchy.h gt-cp-constexpr.h gt-objc-objc-act.h gt-objc-objc-runtime-shared-support.h gt-objc-objc-gnu-runtime-abi-01.h gt-objc-objc-next-runtime-abi-01.h gt-objc-objc-next-runtime-abi-02.h gt-c-family-c-cppbuiltin.h -GTFILES_LANG_H=gtype-ada.h gtype-c.h gtype-cp.h gtype-fortran.h gtype-go.h gtype-java.h gtype-jit.h gtype-lto.h gtype-objc.h gtype-objcp.h diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/basic-block.h b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/basic-block.h deleted file mode 100644 index f28fa57..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/basic-block.h +++ /dev/null @@ -1,637 +0,0 @@ -/* Define control flow data structures for the CFG. - Copyright (C) 1987-2015 Free Software Foundation, Inc. - -This file is part of GCC. - -GCC is free software; you can redistribute it and/or modify it under -the terms of the GNU General Public License as published by the Free -Software Foundation; either version 3, or (at your option) any later -version. - -GCC is distributed in the hope that it will be useful, but WITHOUT ANY -WARRANTY; without even the implied warranty of MERCHANTABILITY or -FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -for more details. - -You should have received a copy of the GNU General Public License -along with GCC; see the file COPYING3. If not see -. */ - -#ifndef GCC_BASIC_BLOCK_H -#define GCC_BASIC_BLOCK_H - - -/* Use gcov_type to hold basic block counters. Should be at least - 64bit. Although a counter cannot be negative, we use a signed - type, because erroneous negative counts can be generated when the - flow graph is manipulated by various optimizations. A signed type - makes those easy to detect. */ - -/* Control flow edge information. */ -struct GTY((user)) edge_def { - /* The two blocks at the ends of the edge. */ - basic_block src; - basic_block dest; - - /* Instructions queued on the edge. */ - union edge_def_insns { - gimple_seq g; - rtx_insn *r; - } insns; - - /* Auxiliary info specific to a pass. */ - PTR aux; - - /* Location of any goto implicit in the edge. */ - location_t goto_locus; - - /* The index number corresponding to this edge in the edge vector - dest->preds. */ - unsigned int dest_idx; - - int flags; /* see cfg-flags.def */ - int probability; /* biased by REG_BR_PROB_BASE */ - gcov_type count; /* Expected number of executions calculated - in profile.c */ -}; - -/* Masks for edge.flags. */ -#define DEF_EDGE_FLAG(NAME,IDX) EDGE_##NAME = 1 << IDX , -enum cfg_edge_flags { -#include "cfg-flags.def" - LAST_CFG_EDGE_FLAG /* this is only used for EDGE_ALL_FLAGS */ -}; -#undef DEF_EDGE_FLAG - -/* Bit mask for all edge flags. */ -#define EDGE_ALL_FLAGS ((LAST_CFG_EDGE_FLAG - 1) * 2 - 1) - -/* The following four flags all indicate something special about an edge. - Test the edge flags on EDGE_COMPLEX to detect all forms of "strange" - control flow transfers. */ -#define EDGE_COMPLEX \ - (EDGE_ABNORMAL | EDGE_ABNORMAL_CALL | EDGE_EH | EDGE_PRESERVE) - -struct GTY(()) rtl_bb_info { - /* The first insn of the block is embedded into bb->il.x. */ - /* The last insn of the block. */ - rtx_insn *end_; - - /* In CFGlayout mode points to insn notes/jumptables to be placed just before - and after the block. */ - rtx_insn *header_; - rtx_insn *footer_; -}; - -struct GTY(()) gimple_bb_info { - /* Sequence of statements in this block. */ - gimple_seq seq; - - /* PHI nodes for this block. */ - gimple_seq phi_nodes; -}; - -/* A basic block is a sequence of instructions with only one entry and - only one exit. If any one of the instructions are executed, they - will all be executed, and in sequence from first to last. - - There may be COND_EXEC instructions in the basic block. The - COND_EXEC *instructions* will be executed -- but if the condition - is false the conditionally executed *expressions* will of course - not be executed. We don't consider the conditionally executed - expression (which might have side-effects) to be in a separate - basic block because the program counter will always be at the same - location after the COND_EXEC instruction, regardless of whether the - condition is true or not. - - Basic blocks need not start with a label nor end with a jump insn. - For example, a previous basic block may just "conditionally fall" - into the succeeding basic block, and the last basic block need not - end with a jump insn. Block 0 is a descendant of the entry block. - - A basic block beginning with two labels cannot have notes between - the labels. - - Data for jump tables are stored in jump_insns that occur in no - basic block even though these insns can follow or precede insns in - basic blocks. */ - -/* Basic block information indexed by block number. */ -struct GTY((chain_next ("%h.next_bb"), chain_prev ("%h.prev_bb"))) basic_block_def { - /* The edges into and out of the block. */ - vec *preds; - vec *succs; - - /* Auxiliary info specific to a pass. */ - PTR GTY ((skip (""))) aux; - - /* Innermost loop containing the block. */ - struct loop *loop_father; - - /* The dominance and postdominance information node. */ - struct et_node * GTY ((skip (""))) dom[2]; - - /* Previous and next blocks in the chain. */ - basic_block prev_bb; - basic_block next_bb; - - union basic_block_il_dependent { - struct gimple_bb_info GTY ((tag ("0"))) gimple; - struct { - rtx_insn *head_; - struct rtl_bb_info * rtl; - } GTY ((tag ("1"))) x; - } GTY ((desc ("((%1.flags & BB_RTL) != 0)"))) il; - - /* Various flags. See cfg-flags.def. */ - int flags; - - /* The index of this block. */ - int index; - - /* Expected number of executions: calculated in profile.c. */ - gcov_type count; - - /* Expected frequency. Normalized to be in range 0 to BB_FREQ_MAX. */ - int frequency; - - /* The discriminator for this block. The discriminator distinguishes - among several basic blocks that share a common locus, allowing for - more accurate sample-based profiling. */ - int discriminator; -}; - -/* This ensures that struct gimple_bb_info is smaller than - struct rtl_bb_info, so that inlining the former into basic_block_def - is the better choice. */ -typedef int __assert_gimple_bb_smaller_rtl_bb - [(int) sizeof (struct rtl_bb_info) - - (int) sizeof (struct gimple_bb_info)]; - - -#define BB_FREQ_MAX 10000 - -/* Masks for basic_block.flags. */ -#define DEF_BASIC_BLOCK_FLAG(NAME,IDX) BB_##NAME = 1 << IDX , -enum cfg_bb_flags -{ -#include "cfg-flags.def" - LAST_CFG_BB_FLAG /* this is only used for BB_ALL_FLAGS */ -}; -#undef DEF_BASIC_BLOCK_FLAG - -/* Bit mask for all basic block flags. */ -#define BB_ALL_FLAGS ((LAST_CFG_BB_FLAG - 1) * 2 - 1) - -/* Bit mask for all basic block flags that must be preserved. These are - the bit masks that are *not* cleared by clear_bb_flags. */ -#define BB_FLAGS_TO_PRESERVE \ - (BB_DISABLE_SCHEDULE | BB_RTL | BB_NON_LOCAL_GOTO_TARGET \ - | BB_HOT_PARTITION | BB_COLD_PARTITION) - -/* Dummy bitmask for convenience in the hot/cold partitioning code. */ -#define BB_UNPARTITIONED 0 - -/* Partitions, to be used when partitioning hot and cold basic blocks into - separate sections. */ -#define BB_PARTITION(bb) ((bb)->flags & (BB_HOT_PARTITION|BB_COLD_PARTITION)) -#define BB_SET_PARTITION(bb, part) do { \ - basic_block bb_ = (bb); \ - bb_->flags = ((bb_->flags & ~(BB_HOT_PARTITION|BB_COLD_PARTITION)) \ - | (part)); \ -} while (0) - -#define BB_COPY_PARTITION(dstbb, srcbb) \ - BB_SET_PARTITION (dstbb, BB_PARTITION (srcbb)) - -/* Defines for accessing the fields of the CFG structure for function FN. */ -#define ENTRY_BLOCK_PTR_FOR_FN(FN) ((FN)->cfg->x_entry_block_ptr) -#define EXIT_BLOCK_PTR_FOR_FN(FN) ((FN)->cfg->x_exit_block_ptr) -#define basic_block_info_for_fn(FN) ((FN)->cfg->x_basic_block_info) -#define n_basic_blocks_for_fn(FN) ((FN)->cfg->x_n_basic_blocks) -#define n_edges_for_fn(FN) ((FN)->cfg->x_n_edges) -#define last_basic_block_for_fn(FN) ((FN)->cfg->x_last_basic_block) -#define label_to_block_map_for_fn(FN) ((FN)->cfg->x_label_to_block_map) -#define profile_status_for_fn(FN) ((FN)->cfg->x_profile_status) - -#define BASIC_BLOCK_FOR_FN(FN,N) \ - ((*basic_block_info_for_fn (FN))[(N)]) -#define SET_BASIC_BLOCK_FOR_FN(FN,N,BB) \ - ((*basic_block_info_for_fn (FN))[(N)] = (BB)) - -/* For iterating over basic blocks. */ -#define FOR_BB_BETWEEN(BB, FROM, TO, DIR) \ - for (BB = FROM; BB != TO; BB = BB->DIR) - -#define FOR_EACH_BB_FN(BB, FN) \ - FOR_BB_BETWEEN (BB, (FN)->cfg->x_entry_block_ptr->next_bb, (FN)->cfg->x_exit_block_ptr, next_bb) - -#define FOR_EACH_BB_REVERSE_FN(BB, FN) \ - FOR_BB_BETWEEN (BB, (FN)->cfg->x_exit_block_ptr->prev_bb, (FN)->cfg->x_entry_block_ptr, prev_bb) - -/* For iterating over insns in basic block. */ -#define FOR_BB_INSNS(BB, INSN) \ - for ((INSN) = BB_HEAD (BB); \ - (INSN) && (INSN) != NEXT_INSN (BB_END (BB)); \ - (INSN) = NEXT_INSN (INSN)) - -/* For iterating over insns in basic block when we might remove the - current insn. */ -#define FOR_BB_INSNS_SAFE(BB, INSN, CURR) \ - for ((INSN) = BB_HEAD (BB), (CURR) = (INSN) ? NEXT_INSN ((INSN)): NULL; \ - (INSN) && (INSN) != NEXT_INSN (BB_END (BB)); \ - (INSN) = (CURR), (CURR) = (INSN) ? NEXT_INSN ((INSN)) : NULL) - -#define FOR_BB_INSNS_REVERSE(BB, INSN) \ - for ((INSN) = BB_END (BB); \ - (INSN) && (INSN) != PREV_INSN (BB_HEAD (BB)); \ - (INSN) = PREV_INSN (INSN)) - -#define FOR_BB_INSNS_REVERSE_SAFE(BB, INSN, CURR) \ - for ((INSN) = BB_END (BB),(CURR) = (INSN) ? PREV_INSN ((INSN)) : NULL; \ - (INSN) && (INSN) != PREV_INSN (BB_HEAD (BB)); \ - (INSN) = (CURR), (CURR) = (INSN) ? PREV_INSN ((INSN)) : NULL) - -/* Cycles through _all_ basic blocks, even the fake ones (entry and - exit block). */ - -#define FOR_ALL_BB_FN(BB, FN) \ - for (BB = ENTRY_BLOCK_PTR_FOR_FN (FN); BB; BB = BB->next_bb) - - -/* Stuff for recording basic block info. */ - -/* For now, these will be functions (so that they can include checked casts - to rtx_insn. Once the underlying fields are converted from rtx - to rtx_insn, these can be converted back to macros. */ - -#define BB_HEAD(B) (B)->il.x.head_ -#define BB_END(B) (B)->il.x.rtl->end_ -#define BB_HEADER(B) (B)->il.x.rtl->header_ -#define BB_FOOTER(B) (B)->il.x.rtl->footer_ - -/* Special block numbers [markers] for entry and exit. - Neither of them is supposed to hold actual statements. */ -#define ENTRY_BLOCK (0) -#define EXIT_BLOCK (1) - -/* The two blocks that are always in the cfg. */ -#define NUM_FIXED_BLOCKS (2) - -/* The base value for branch probability notes and edge probabilities. */ -#define REG_BR_PROB_BASE 10000 - -/* This is the value which indicates no edge is present. */ -#define EDGE_INDEX_NO_EDGE -1 - -/* EDGE_INDEX returns an integer index for an edge, or EDGE_INDEX_NO_EDGE - if there is no edge between the 2 basic blocks. */ -#define EDGE_INDEX(el, pred, succ) (find_edge_index ((el), (pred), (succ))) - -/* INDEX_EDGE_PRED_BB and INDEX_EDGE_SUCC_BB return a pointer to the basic - block which is either the pred or succ end of the indexed edge. */ -#define INDEX_EDGE_PRED_BB(el, index) ((el)->index_to_edge[(index)]->src) -#define INDEX_EDGE_SUCC_BB(el, index) ((el)->index_to_edge[(index)]->dest) - -/* INDEX_EDGE returns a pointer to the edge. */ -#define INDEX_EDGE(el, index) ((el)->index_to_edge[(index)]) - -/* Number of edges in the compressed edge list. */ -#define NUM_EDGES(el) ((el)->num_edges) - -/* BB is assumed to contain conditional jump. Return the fallthru edge. */ -#define FALLTHRU_EDGE(bb) (EDGE_SUCC ((bb), 0)->flags & EDGE_FALLTHRU \ - ? EDGE_SUCC ((bb), 0) : EDGE_SUCC ((bb), 1)) - -/* BB is assumed to contain conditional jump. Return the branch edge. */ -#define BRANCH_EDGE(bb) (EDGE_SUCC ((bb), 0)->flags & EDGE_FALLTHRU \ - ? EDGE_SUCC ((bb), 1) : EDGE_SUCC ((bb), 0)) - -#define RDIV(X,Y) (((X) + (Y) / 2) / (Y)) -/* Return expected execution frequency of the edge E. */ -#define EDGE_FREQUENCY(e) RDIV ((e)->src->frequency * (e)->probability, \ - REG_BR_PROB_BASE) - -/* Compute a scale factor (or probability) suitable for scaling of - gcov_type values via apply_probability() and apply_scale(). */ -#define GCOV_COMPUTE_SCALE(num,den) \ - ((den) ? RDIV ((num) * REG_BR_PROB_BASE, (den)) : REG_BR_PROB_BASE) - -/* Return nonzero if edge is critical. */ -#define EDGE_CRITICAL_P(e) (EDGE_COUNT ((e)->src->succs) >= 2 \ - && EDGE_COUNT ((e)->dest->preds) >= 2) - -#define EDGE_COUNT(ev) vec_safe_length (ev) -#define EDGE_I(ev,i) (*ev)[(i)] -#define EDGE_PRED(bb,i) (*(bb)->preds)[(i)] -#define EDGE_SUCC(bb,i) (*(bb)->succs)[(i)] - -/* Returns true if BB has precisely one successor. */ - -static inline bool -single_succ_p (const_basic_block bb) -{ - return EDGE_COUNT (bb->succs) == 1; -} - -/* Returns true if BB has precisely one predecessor. */ - -static inline bool -single_pred_p (const_basic_block bb) -{ - return EDGE_COUNT (bb->preds) == 1; -} - -/* Returns the single successor edge of basic block BB. Aborts if - BB does not have exactly one successor. */ - -static inline edge -single_succ_edge (const_basic_block bb) -{ - gcc_checking_assert (single_succ_p (bb)); - return EDGE_SUCC (bb, 0); -} - -/* Returns the single predecessor edge of basic block BB. Aborts - if BB does not have exactly one predecessor. */ - -static inline edge -single_pred_edge (const_basic_block bb) -{ - gcc_checking_assert (single_pred_p (bb)); - return EDGE_PRED (bb, 0); -} - -/* Returns the single successor block of basic block BB. Aborts - if BB does not have exactly one successor. */ - -static inline basic_block -single_succ (const_basic_block bb) -{ - return single_succ_edge (bb)->dest; -} - -/* Returns the single predecessor block of basic block BB. Aborts - if BB does not have exactly one predecessor.*/ - -static inline basic_block -single_pred (const_basic_block bb) -{ - return single_pred_edge (bb)->src; -} - -/* Iterator object for edges. */ - -struct edge_iterator { - unsigned index; - vec **container; -}; - -static inline vec * -ei_container (edge_iterator i) -{ - gcc_checking_assert (i.container); - return *i.container; -} - -#define ei_start(iter) ei_start_1 (&(iter)) -#define ei_last(iter) ei_last_1 (&(iter)) - -/* Return an iterator pointing to the start of an edge vector. */ -static inline edge_iterator -ei_start_1 (vec **ev) -{ - edge_iterator i; - - i.index = 0; - i.container = ev; - - return i; -} - -/* Return an iterator pointing to the last element of an edge - vector. */ -static inline edge_iterator -ei_last_1 (vec **ev) -{ - edge_iterator i; - - i.index = EDGE_COUNT (*ev) - 1; - i.container = ev; - - return i; -} - -/* Is the iterator `i' at the end of the sequence? */ -static inline bool -ei_end_p (edge_iterator i) -{ - return (i.index == EDGE_COUNT (ei_container (i))); -} - -/* Is the iterator `i' at one position before the end of the - sequence? */ -static inline bool -ei_one_before_end_p (edge_iterator i) -{ - return (i.index + 1 == EDGE_COUNT (ei_container (i))); -} - -/* Advance the iterator to the next element. */ -static inline void -ei_next (edge_iterator *i) -{ - gcc_checking_assert (i->index < EDGE_COUNT (ei_container (*i))); - i->index++; -} - -/* Move the iterator to the previous element. */ -static inline void -ei_prev (edge_iterator *i) -{ - gcc_checking_assert (i->index > 0); - i->index--; -} - -/* Return the edge pointed to by the iterator `i'. */ -static inline edge -ei_edge (edge_iterator i) -{ - return EDGE_I (ei_container (i), i.index); -} - -/* Return an edge pointed to by the iterator. Do it safely so that - NULL is returned when the iterator is pointing at the end of the - sequence. */ -static inline edge -ei_safe_edge (edge_iterator i) -{ - return !ei_end_p (i) ? ei_edge (i) : NULL; -} - -/* Return 1 if we should continue to iterate. Return 0 otherwise. - *Edge P is set to the next edge if we are to continue to iterate - and NULL otherwise. */ - -static inline bool -ei_cond (edge_iterator ei, edge *p) -{ - if (!ei_end_p (ei)) - { - *p = ei_edge (ei); - return 1; - } - else - { - *p = NULL; - return 0; - } -} - -/* This macro serves as a convenient way to iterate each edge in a - vector of predecessor or successor edges. It must not be used when - an element might be removed during the traversal, otherwise - elements will be missed. Instead, use a for-loop like that shown - in the following pseudo-code: - - FOR (ei = ei_start (bb->succs); (e = ei_safe_edge (ei)); ) - { - IF (e != taken_edge) - remove_edge (e); - ELSE - ei_next (&ei); - } -*/ - -#define FOR_EACH_EDGE(EDGE,ITER,EDGE_VEC) \ - for ((ITER) = ei_start ((EDGE_VEC)); \ - ei_cond ((ITER), &(EDGE)); \ - ei_next (&(ITER))) - -#define CLEANUP_EXPENSIVE 1 /* Do relatively expensive optimizations - except for edge forwarding */ -#define CLEANUP_CROSSJUMP 2 /* Do crossjumping. */ -#define CLEANUP_POST_REGSTACK 4 /* We run after reg-stack and need - to care REG_DEAD notes. */ -#define CLEANUP_THREADING 8 /* Do jump threading. */ -#define CLEANUP_NO_INSN_DEL 16 /* Do not try to delete trivially dead - insns. */ -#define CLEANUP_CFGLAYOUT 32 /* Do cleanup in cfglayout mode. */ -#define CLEANUP_CFG_CHANGED 64 /* The caller changed the CFG. */ - -#include "cfghooks.h" - -/* Return true if BB is in a transaction. */ - -static inline bool -bb_in_transaction (basic_block bb) -{ - return bb->flags & BB_IN_TRANSACTION; -} - -/* Return true when one of the predecessor edges of BB is marked with EDGE_EH. */ -static inline bool -bb_has_eh_pred (basic_block bb) -{ - edge e; - edge_iterator ei; - - FOR_EACH_EDGE (e, ei, bb->preds) - { - if (e->flags & EDGE_EH) - return true; - } - return false; -} - -/* Return true when one of the predecessor edges of BB is marked with EDGE_ABNORMAL. */ -static inline bool -bb_has_abnormal_pred (basic_block bb) -{ - edge e; - edge_iterator ei; - - FOR_EACH_EDGE (e, ei, bb->preds) - { - if (e->flags & EDGE_ABNORMAL) - return true; - } - return false; -} - -/* Return the fallthru edge in EDGES if it exists, NULL otherwise. */ -static inline edge -find_fallthru_edge (vec *edges) -{ - edge e; - edge_iterator ei; - - FOR_EACH_EDGE (e, ei, edges) - if (e->flags & EDGE_FALLTHRU) - break; - - return e; -} - -/* Check tha probability is sane. */ - -static inline void -check_probability (int prob) -{ - gcc_checking_assert (prob >= 0 && prob <= REG_BR_PROB_BASE); -} - -/* Given PROB1 and PROB2, return PROB1*PROB2/REG_BR_PROB_BASE. - Used to combine BB probabilities. */ - -static inline int -combine_probabilities (int prob1, int prob2) -{ - check_probability (prob1); - check_probability (prob2); - return RDIV (prob1 * prob2, REG_BR_PROB_BASE); -} - -/* Apply scale factor SCALE on frequency or count FREQ. Use this - interface when potentially scaling up, so that SCALE is not - constrained to be < REG_BR_PROB_BASE. */ - -static inline gcov_type -apply_scale (gcov_type freq, gcov_type scale) -{ - return RDIV (freq * scale, REG_BR_PROB_BASE); -} - -/* Apply probability PROB on frequency or count FREQ. */ - -static inline gcov_type -apply_probability (gcov_type freq, int prob) -{ - check_probability (prob); - return apply_scale (freq, prob); -} - -/* Return inverse probability for PROB. */ - -static inline int -inverse_probability (int prob1) -{ - check_probability (prob1); - return REG_BR_PROB_BASE - prob1; -} - -/* Return true if BB has at least one abnormal outgoing edge. */ - -static inline bool -has_abnormal_or_eh_outgoing_edge_p (basic_block bb) -{ - edge e; - edge_iterator ei; - - FOR_EACH_EDGE (e, ei, bb->succs) - if (e->flags & (EDGE_ABNORMAL | EDGE_EH)) - return true; - - return false; -} -#endif /* GCC_BASIC_BLOCK_H */ diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/bb-reorder.h b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/bb-reorder.h deleted file mode 100644 index 9bc326c..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/bb-reorder.h +++ /dev/null @@ -1,40 +0,0 @@ -/* Basic block reordering routines for the GNU compiler. - Copyright (C) 2000-2015 Free Software Foundation, Inc. - - This file is part of GCC. - - GCC is free software; you can redistribute it and/or modify it - under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3, or (at your option) - any later version. - - GCC is distributed in the hope that it will be useful, but WITHOUT - ANY WARRANTY; without even the implied warranty of MERCHANTABILITY - or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public - License for more details. - - You should have received a copy of the GNU General Public License - along with GCC; see the file COPYING3. If not see - . */ - -#ifndef GCC_BB_REORDER -#define GCC_BB_REORDER - -/* Target-specific globals. */ -struct target_bb_reorder { - /* Length of unconditional jump instruction. */ - int x_uncond_jump_length; -}; - -extern struct target_bb_reorder default_target_bb_reorder; -#if SWITCHABLE_TARGET -extern struct target_bb_reorder *this_target_bb_reorder; -#else -#define this_target_bb_reorder (&default_target_bb_reorder) -#endif - -extern int get_uncond_jump_length (void); - -extern void insert_section_boundary_note (void); - -#endif diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/bitmap.h b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/bitmap.h deleted file mode 100644 index 3f9bbf3..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/bitmap.h +++ /dev/null @@ -1,715 +0,0 @@ -/* Functions to support general ended bitmaps. - Copyright (C) 1997-2015 Free Software Foundation, Inc. - -This file is part of GCC. - -GCC is free software; you can redistribute it and/or modify it under -the terms of the GNU General Public License as published by the Free -Software Foundation; either version 3, or (at your option) any later -version. - -GCC is distributed in the hope that it will be useful, but WITHOUT ANY -WARRANTY; without even the implied warranty of MERCHANTABILITY or -FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -for more details. - -You should have received a copy of the GNU General Public License -along with GCC; see the file COPYING3. If not see -. */ - -#ifndef GCC_BITMAP_H -#define GCC_BITMAP_H - -/* Implementation of sparse integer sets as a linked list. - - This sparse set representation is suitable for sparse sets with an - unknown (a priori) universe. The set is represented as a double-linked - list of container nodes (struct bitmap_element). Each node consists - of an index for the first member that could be held in the container, - a small array of integers that represent the members in the container, - and pointers to the next and previous element in the linked list. The - elements in the list are sorted in ascending order, i.e. the head of - the list holds the element with the smallest member of the set. - - For a given member I in the set: - - the element for I will have index is I / (bits per element) - - the position for I within element is I % (bits per element) - - This representation is very space-efficient for large sparse sets, and - the size of the set can be changed dynamically without much overhead. - An important parameter is the number of bits per element. In this - implementation, there are 128 bits per element. This results in a - high storage overhead *per element*, but a small overall overhead if - the set is very sparse. - - The downside is that many operations are relatively slow because the - linked list has to be traversed to test membership (i.e. member_p/ - add_member/remove_member). To improve the performance of this set - representation, the last accessed element and its index are cached. - For membership tests on members close to recently accessed members, - the cached last element improves membership test to a constant-time - operation. - - The following operations can always be performed in O(1) time: - - * clear : bitmap_clear - * choose_one : (not implemented, but could be - implemented in constant time) - - The following operations can be performed in O(E) time worst-case (with - E the number of elements in the linked list), but in O(1) time with a - suitable access patterns: - - * member_p : bitmap_bit_p - * add_member : bitmap_set_bit - * remove_member : bitmap_clear_bit - - The following operations can be performed in O(E) time: - - * cardinality : bitmap_count_bits - * set_size : bitmap_last_set_bit (but this could - in constant time with a pointer to - the last element in the chain) - - Additionally, the linked-list sparse set representation supports - enumeration of the members in O(E) time: - - * forall : EXECUTE_IF_SET_IN_BITMAP - * set_copy : bitmap_copy - * set_intersection : bitmap_intersect_p / - bitmap_and / bitmap_and_into / - EXECUTE_IF_AND_IN_BITMAP - * set_union : bitmap_ior / bitmap_ior_into - * set_difference : bitmap_intersect_compl_p / - bitmap_and_comp / bitmap_and_comp_into / - EXECUTE_IF_AND_COMPL_IN_BITMAP - * set_disjuction : bitmap_xor_comp / bitmap_xor_comp_into - * set_compare : bitmap_equal_p - - Some operations on 3 sets that occur frequently in in data flow problems - are also implemented: - - * A | (B & C) : bitmap_ior_and_into - * A | (B & ~C) : bitmap_ior_and_compl / - bitmap_ior_and_compl_into - - The storage requirements for linked-list sparse sets are O(E), with E->N - in the worst case (a sparse set with large distances between the values - of the set members). - - The linked-list set representation works well for problems involving very - sparse sets. The canonical example in GCC is, of course, the "set of - sets" for some CFG-based data flow problems (liveness analysis, dominance - frontiers, etc.). - - This representation also works well for data flow problems where the size - of the set may grow dynamically, but care must be taken that the member_p, - add_member, and remove_member operations occur with a suitable access - pattern. - - For random-access sets with a known, relatively small universe size, the - SparseSet or simple bitmap representations may be more efficient than a - linked-list set. For random-access sets of unknown universe, a hash table - or a balanced binary tree representation is likely to be a more suitable - choice. - - Traversing linked lists is usually cache-unfriendly, even with the last - accessed element cached. - - Cache performance can be improved by keeping the elements in the set - grouped together in memory, using a dedicated obstack for a set (or group - of related sets). Elements allocated on obstacks are released to a - free-list and taken off the free list. If multiple sets are allocated on - the same obstack, elements freed from one set may be re-used for one of - the other sets. This usually helps avoid cache misses. - - A single free-list is used for all sets allocated in GGC space. This is - bad for persistent sets, so persistent sets should be allocated on an - obstack whenever possible. */ - -#include "hashtab.h" -#include "statistics.h" -#include "obstack.h" - -/* Fundamental storage type for bitmap. */ - -typedef unsigned long BITMAP_WORD; -/* BITMAP_WORD_BITS needs to be unsigned, but cannot contain casts as - it is used in preprocessor directives -- hence the 1u. */ -#define BITMAP_WORD_BITS (CHAR_BIT * SIZEOF_LONG * 1u) - -/* Number of words to use for each element in the linked list. */ - -#ifndef BITMAP_ELEMENT_WORDS -#define BITMAP_ELEMENT_WORDS ((128 + BITMAP_WORD_BITS - 1) / BITMAP_WORD_BITS) -#endif - -/* Number of bits in each actual element of a bitmap. */ - -#define BITMAP_ELEMENT_ALL_BITS (BITMAP_ELEMENT_WORDS * BITMAP_WORD_BITS) - -/* Obstack for allocating bitmaps and elements from. */ -struct GTY (()) bitmap_obstack { - struct bitmap_element *elements; - struct bitmap_head *heads; - struct obstack GTY ((skip)) obstack; -}; - -/* Bitmap set element. We use a linked list to hold only the bits that - are set. This allows for use to grow the bitset dynamically without - having to realloc and copy a giant bit array. - - The free list is implemented as a list of lists. There is one - outer list connected together by prev fields. Each element of that - outer is an inner list (that may consist only of the outer list - element) that are connected by the next fields. The prev pointer - is undefined for interior elements. This allows - bitmap_elt_clear_from to be implemented in unit time rather than - linear in the number of elements to be freed. */ - -struct GTY((chain_next ("%h.next"), chain_prev ("%h.prev"))) bitmap_element { - struct bitmap_element *next; /* Next element. */ - struct bitmap_element *prev; /* Previous element. */ - unsigned int indx; /* regno/BITMAP_ELEMENT_ALL_BITS. */ - BITMAP_WORD bits[BITMAP_ELEMENT_WORDS]; /* Bits that are set. */ -}; - -/* Head of bitmap linked list. The 'current' member points to something - already pointed to by the chain started by first, so GTY((skip)) it. */ - -struct GTY(()) bitmap_head { - unsigned int indx; /* Index of last element looked at. */ - unsigned int descriptor_id; /* Unique identifier for the allocation - site of this bitmap, for detailed - statistics gathering. */ - bitmap_element *first; /* First element in linked list. */ - bitmap_element * GTY((skip(""))) current; /* Last element looked at. */ - bitmap_obstack *obstack; /* Obstack to allocate elements from. - If NULL, then use GGC allocation. */ -}; - -/* Global data */ -extern bitmap_element bitmap_zero_bits; /* Zero bitmap element */ -extern bitmap_obstack bitmap_default_obstack; /* Default bitmap obstack */ - -/* Clear a bitmap by freeing up the linked list. */ -extern void bitmap_clear (bitmap); - -/* Copy a bitmap to another bitmap. */ -extern void bitmap_copy (bitmap, const_bitmap); - -/* True if two bitmaps are identical. */ -extern bool bitmap_equal_p (const_bitmap, const_bitmap); - -/* True if the bitmaps intersect (their AND is non-empty). */ -extern bool bitmap_intersect_p (const_bitmap, const_bitmap); - -/* True if the complement of the second intersects the first (their - AND_COMPL is non-empty). */ -extern bool bitmap_intersect_compl_p (const_bitmap, const_bitmap); - -/* True if MAP is an empty bitmap. */ -inline bool bitmap_empty_p (const_bitmap map) -{ - return !map->first; -} - -/* True if the bitmap has only a single bit set. */ -extern bool bitmap_single_bit_set_p (const_bitmap); - -/* Count the number of bits set in the bitmap. */ -extern unsigned long bitmap_count_bits (const_bitmap); - -/* Boolean operations on bitmaps. The _into variants are two operand - versions that modify the first source operand. The other variants - are three operand versions that to not destroy the source bitmaps. - The operations supported are &, & ~, |, ^. */ -extern void bitmap_and (bitmap, const_bitmap, const_bitmap); -extern bool bitmap_and_into (bitmap, const_bitmap); -extern bool bitmap_and_compl (bitmap, const_bitmap, const_bitmap); -extern bool bitmap_and_compl_into (bitmap, const_bitmap); -#define bitmap_compl_and(DST, A, B) bitmap_and_compl (DST, B, A) -extern void bitmap_compl_and_into (bitmap, const_bitmap); -extern void bitmap_clear_range (bitmap, unsigned int, unsigned int); -extern void bitmap_set_range (bitmap, unsigned int, unsigned int); -extern bool bitmap_ior (bitmap, const_bitmap, const_bitmap); -extern bool bitmap_ior_into (bitmap, const_bitmap); -extern void bitmap_xor (bitmap, const_bitmap, const_bitmap); -extern void bitmap_xor_into (bitmap, const_bitmap); - -/* DST = A | (B & C). Return true if DST changes. */ -extern bool bitmap_ior_and_into (bitmap DST, const_bitmap B, const_bitmap C); -/* DST = A | (B & ~C). Return true if DST changes. */ -extern bool bitmap_ior_and_compl (bitmap DST, const_bitmap A, - const_bitmap B, const_bitmap C); -/* A |= (B & ~C). Return true if A changes. */ -extern bool bitmap_ior_and_compl_into (bitmap A, - const_bitmap B, const_bitmap C); - -/* Clear a single bit in a bitmap. Return true if the bit changed. */ -extern bool bitmap_clear_bit (bitmap, int); - -/* Set a single bit in a bitmap. Return true if the bit changed. */ -extern bool bitmap_set_bit (bitmap, int); - -/* Return true if a register is set in a register set. */ -extern int bitmap_bit_p (bitmap, int); - -/* Debug functions to print a bitmap linked list. */ -extern void debug_bitmap (const_bitmap); -extern void debug_bitmap_file (FILE *, const_bitmap); - -/* Print a bitmap. */ -extern void bitmap_print (FILE *, const_bitmap, const char *, const char *); - -/* Initialize and release a bitmap obstack. */ -extern void bitmap_obstack_initialize (bitmap_obstack *); -extern void bitmap_obstack_release (bitmap_obstack *); -extern void bitmap_register (bitmap MEM_STAT_DECL); -extern void dump_bitmap_statistics (void); - -/* Initialize a bitmap header. OBSTACK indicates the bitmap obstack - to allocate from, NULL for GC'd bitmap. */ - -static inline void -bitmap_initialize_stat (bitmap head, bitmap_obstack *obstack MEM_STAT_DECL) -{ - head->first = head->current = NULL; - head->obstack = obstack; - if (GATHER_STATISTICS) - bitmap_register (head PASS_MEM_STAT); -} -#define bitmap_initialize(h,o) bitmap_initialize_stat (h,o MEM_STAT_INFO) - -/* Allocate and free bitmaps from obstack, malloc and gc'd memory. */ -extern bitmap bitmap_obstack_alloc_stat (bitmap_obstack *obstack MEM_STAT_DECL); -#define bitmap_obstack_alloc(t) bitmap_obstack_alloc_stat (t MEM_STAT_INFO) -extern bitmap bitmap_gc_alloc_stat (ALONE_MEM_STAT_DECL); -#define bitmap_gc_alloc() bitmap_gc_alloc_stat (ALONE_MEM_STAT_INFO) -extern void bitmap_obstack_free (bitmap); - -/* A few compatibility/functions macros for compatibility with sbitmaps */ -inline void dump_bitmap (FILE *file, const_bitmap map) -{ - bitmap_print (file, map, "", "\n"); -} -extern void debug (const bitmap_head &ref); -extern void debug (const bitmap_head *ptr); - -extern unsigned bitmap_first_set_bit (const_bitmap); -extern unsigned bitmap_last_set_bit (const_bitmap); - -/* Compute bitmap hash (for purposes of hashing etc.) */ -extern hashval_t bitmap_hash (const_bitmap); - -/* Allocate a bitmap from a bit obstack. */ -#define BITMAP_ALLOC(OBSTACK) bitmap_obstack_alloc (OBSTACK) - -/* Allocate a gc'd bitmap. */ -#define BITMAP_GGC_ALLOC() bitmap_gc_alloc () - -/* Do any cleanup needed on a bitmap when it is no longer used. */ -#define BITMAP_FREE(BITMAP) \ - ((void) (bitmap_obstack_free ((bitmap) BITMAP), (BITMAP) = (bitmap) NULL)) - -/* Iterator for bitmaps. */ - -struct bitmap_iterator -{ - /* Pointer to the current bitmap element. */ - bitmap_element *elt1; - - /* Pointer to 2nd bitmap element when two are involved. */ - bitmap_element *elt2; - - /* Word within the current element. */ - unsigned word_no; - - /* Contents of the actually processed word. When finding next bit - it is shifted right, so that the actual bit is always the least - significant bit of ACTUAL. */ - BITMAP_WORD bits; -}; - -/* Initialize a single bitmap iterator. START_BIT is the first bit to - iterate from. */ - -static inline void -bmp_iter_set_init (bitmap_iterator *bi, const_bitmap map, - unsigned start_bit, unsigned *bit_no) -{ - bi->elt1 = map->first; - bi->elt2 = NULL; - - /* Advance elt1 until it is not before the block containing start_bit. */ - while (1) - { - if (!bi->elt1) - { - bi->elt1 = &bitmap_zero_bits; - break; - } - - if (bi->elt1->indx >= start_bit / BITMAP_ELEMENT_ALL_BITS) - break; - bi->elt1 = bi->elt1->next; - } - - /* We might have gone past the start bit, so reinitialize it. */ - if (bi->elt1->indx != start_bit / BITMAP_ELEMENT_ALL_BITS) - start_bit = bi->elt1->indx * BITMAP_ELEMENT_ALL_BITS; - - /* Initialize for what is now start_bit. */ - bi->word_no = start_bit / BITMAP_WORD_BITS % BITMAP_ELEMENT_WORDS; - bi->bits = bi->elt1->bits[bi->word_no]; - bi->bits >>= start_bit % BITMAP_WORD_BITS; - - /* If this word is zero, we must make sure we're not pointing at the - first bit, otherwise our incrementing to the next word boundary - will fail. It won't matter if this increment moves us into the - next word. */ - start_bit += !bi->bits; - - *bit_no = start_bit; -} - -/* Initialize an iterator to iterate over the intersection of two - bitmaps. START_BIT is the bit to commence from. */ - -static inline void -bmp_iter_and_init (bitmap_iterator *bi, const_bitmap map1, const_bitmap map2, - unsigned start_bit, unsigned *bit_no) -{ - bi->elt1 = map1->first; - bi->elt2 = map2->first; - - /* Advance elt1 until it is not before the block containing - start_bit. */ - while (1) - { - if (!bi->elt1) - { - bi->elt2 = NULL; - break; - } - - if (bi->elt1->indx >= start_bit / BITMAP_ELEMENT_ALL_BITS) - break; - bi->elt1 = bi->elt1->next; - } - - /* Advance elt2 until it is not before elt1. */ - while (1) - { - if (!bi->elt2) - { - bi->elt1 = bi->elt2 = &bitmap_zero_bits; - break; - } - - if (bi->elt2->indx >= bi->elt1->indx) - break; - bi->elt2 = bi->elt2->next; - } - - /* If we're at the same index, then we have some intersecting bits. */ - if (bi->elt1->indx == bi->elt2->indx) - { - /* We might have advanced beyond the start_bit, so reinitialize - for that. */ - if (bi->elt1->indx != start_bit / BITMAP_ELEMENT_ALL_BITS) - start_bit = bi->elt1->indx * BITMAP_ELEMENT_ALL_BITS; - - bi->word_no = start_bit / BITMAP_WORD_BITS % BITMAP_ELEMENT_WORDS; - bi->bits = bi->elt1->bits[bi->word_no] & bi->elt2->bits[bi->word_no]; - bi->bits >>= start_bit % BITMAP_WORD_BITS; - } - else - { - /* Otherwise we must immediately advance elt1, so initialize for - that. */ - bi->word_no = BITMAP_ELEMENT_WORDS - 1; - bi->bits = 0; - } - - /* If this word is zero, we must make sure we're not pointing at the - first bit, otherwise our incrementing to the next word boundary - will fail. It won't matter if this increment moves us into the - next word. */ - start_bit += !bi->bits; - - *bit_no = start_bit; -} - -/* Initialize an iterator to iterate over the bits in MAP1 & ~MAP2. - */ - -static inline void -bmp_iter_and_compl_init (bitmap_iterator *bi, - const_bitmap map1, const_bitmap map2, - unsigned start_bit, unsigned *bit_no) -{ - bi->elt1 = map1->first; - bi->elt2 = map2->first; - - /* Advance elt1 until it is not before the block containing start_bit. */ - while (1) - { - if (!bi->elt1) - { - bi->elt1 = &bitmap_zero_bits; - break; - } - - if (bi->elt1->indx >= start_bit / BITMAP_ELEMENT_ALL_BITS) - break; - bi->elt1 = bi->elt1->next; - } - - /* Advance elt2 until it is not before elt1. */ - while (bi->elt2 && bi->elt2->indx < bi->elt1->indx) - bi->elt2 = bi->elt2->next; - - /* We might have advanced beyond the start_bit, so reinitialize for - that. */ - if (bi->elt1->indx != start_bit / BITMAP_ELEMENT_ALL_BITS) - start_bit = bi->elt1->indx * BITMAP_ELEMENT_ALL_BITS; - - bi->word_no = start_bit / BITMAP_WORD_BITS % BITMAP_ELEMENT_WORDS; - bi->bits = bi->elt1->bits[bi->word_no]; - if (bi->elt2 && bi->elt1->indx == bi->elt2->indx) - bi->bits &= ~bi->elt2->bits[bi->word_no]; - bi->bits >>= start_bit % BITMAP_WORD_BITS; - - /* If this word is zero, we must make sure we're not pointing at the - first bit, otherwise our incrementing to the next word boundary - will fail. It won't matter if this increment moves us into the - next word. */ - start_bit += !bi->bits; - - *bit_no = start_bit; -} - -/* Advance to the next bit in BI. We don't advance to the next - nonzero bit yet. */ - -static inline void -bmp_iter_next (bitmap_iterator *bi, unsigned *bit_no) -{ - bi->bits >>= 1; - *bit_no += 1; -} - -/* Advance to first set bit in BI. */ - -static inline void -bmp_iter_next_bit (bitmap_iterator * bi, unsigned *bit_no) -{ -#if (GCC_VERSION >= 3004) - { - unsigned int n = __builtin_ctzl (bi->bits); - gcc_assert (sizeof (unsigned long) == sizeof (BITMAP_WORD)); - bi->bits >>= n; - *bit_no += n; - } -#else - while (!(bi->bits & 1)) - { - bi->bits >>= 1; - *bit_no += 1; - } -#endif -} - -/* Advance to the next nonzero bit of a single bitmap, we will have - already advanced past the just iterated bit. Return true if there - is a bit to iterate. */ - -static inline bool -bmp_iter_set (bitmap_iterator *bi, unsigned *bit_no) -{ - /* If our current word is nonzero, it contains the bit we want. */ - if (bi->bits) - { - next_bit: - bmp_iter_next_bit (bi, bit_no); - return true; - } - - /* Round up to the word boundary. We might have just iterated past - the end of the last word, hence the -1. It is not possible for - bit_no to point at the beginning of the now last word. */ - *bit_no = ((*bit_no + BITMAP_WORD_BITS - 1) - / BITMAP_WORD_BITS * BITMAP_WORD_BITS); - bi->word_no++; - - while (1) - { - /* Find the next nonzero word in this elt. */ - while (bi->word_no != BITMAP_ELEMENT_WORDS) - { - bi->bits = bi->elt1->bits[bi->word_no]; - if (bi->bits) - goto next_bit; - *bit_no += BITMAP_WORD_BITS; - bi->word_no++; - } - - /* Advance to the next element. */ - bi->elt1 = bi->elt1->next; - if (!bi->elt1) - return false; - *bit_no = bi->elt1->indx * BITMAP_ELEMENT_ALL_BITS; - bi->word_no = 0; - } -} - -/* Advance to the next nonzero bit of an intersecting pair of - bitmaps. We will have already advanced past the just iterated bit. - Return true if there is a bit to iterate. */ - -static inline bool -bmp_iter_and (bitmap_iterator *bi, unsigned *bit_no) -{ - /* If our current word is nonzero, it contains the bit we want. */ - if (bi->bits) - { - next_bit: - bmp_iter_next_bit (bi, bit_no); - return true; - } - - /* Round up to the word boundary. We might have just iterated past - the end of the last word, hence the -1. It is not possible for - bit_no to point at the beginning of the now last word. */ - *bit_no = ((*bit_no + BITMAP_WORD_BITS - 1) - / BITMAP_WORD_BITS * BITMAP_WORD_BITS); - bi->word_no++; - - while (1) - { - /* Find the next nonzero word in this elt. */ - while (bi->word_no != BITMAP_ELEMENT_WORDS) - { - bi->bits = bi->elt1->bits[bi->word_no] & bi->elt2->bits[bi->word_no]; - if (bi->bits) - goto next_bit; - *bit_no += BITMAP_WORD_BITS; - bi->word_no++; - } - - /* Advance to the next identical element. */ - do - { - /* Advance elt1 while it is less than elt2. We always want - to advance one elt. */ - do - { - bi->elt1 = bi->elt1->next; - if (!bi->elt1) - return false; - } - while (bi->elt1->indx < bi->elt2->indx); - - /* Advance elt2 to be no less than elt1. This might not - advance. */ - while (bi->elt2->indx < bi->elt1->indx) - { - bi->elt2 = bi->elt2->next; - if (!bi->elt2) - return false; - } - } - while (bi->elt1->indx != bi->elt2->indx); - - *bit_no = bi->elt1->indx * BITMAP_ELEMENT_ALL_BITS; - bi->word_no = 0; - } -} - -/* Advance to the next nonzero bit in the intersection of - complemented bitmaps. We will have already advanced past the just - iterated bit. */ - -static inline bool -bmp_iter_and_compl (bitmap_iterator *bi, unsigned *bit_no) -{ - /* If our current word is nonzero, it contains the bit we want. */ - if (bi->bits) - { - next_bit: - bmp_iter_next_bit (bi, bit_no); - return true; - } - - /* Round up to the word boundary. We might have just iterated past - the end of the last word, hence the -1. It is not possible for - bit_no to point at the beginning of the now last word. */ - *bit_no = ((*bit_no + BITMAP_WORD_BITS - 1) - / BITMAP_WORD_BITS * BITMAP_WORD_BITS); - bi->word_no++; - - while (1) - { - /* Find the next nonzero word in this elt. */ - while (bi->word_no != BITMAP_ELEMENT_WORDS) - { - bi->bits = bi->elt1->bits[bi->word_no]; - if (bi->elt2 && bi->elt2->indx == bi->elt1->indx) - bi->bits &= ~bi->elt2->bits[bi->word_no]; - if (bi->bits) - goto next_bit; - *bit_no += BITMAP_WORD_BITS; - bi->word_no++; - } - - /* Advance to the next element of elt1. */ - bi->elt1 = bi->elt1->next; - if (!bi->elt1) - return false; - - /* Advance elt2 until it is no less than elt1. */ - while (bi->elt2 && bi->elt2->indx < bi->elt1->indx) - bi->elt2 = bi->elt2->next; - - *bit_no = bi->elt1->indx * BITMAP_ELEMENT_ALL_BITS; - bi->word_no = 0; - } -} - -/* Loop over all bits set in BITMAP, starting with MIN and setting - BITNUM to the bit number. ITER is a bitmap iterator. BITNUM - should be treated as a read-only variable as it contains loop - state. */ - -#ifndef EXECUTE_IF_SET_IN_BITMAP -/* See sbitmap.h for the other definition of EXECUTE_IF_SET_IN_BITMAP. */ -#define EXECUTE_IF_SET_IN_BITMAP(BITMAP, MIN, BITNUM, ITER) \ - for (bmp_iter_set_init (&(ITER), (BITMAP), (MIN), &(BITNUM)); \ - bmp_iter_set (&(ITER), &(BITNUM)); \ - bmp_iter_next (&(ITER), &(BITNUM))) -#endif - -/* Loop over all the bits set in BITMAP1 & BITMAP2, starting with MIN - and setting BITNUM to the bit number. ITER is a bitmap iterator. - BITNUM should be treated as a read-only variable as it contains - loop state. */ - -#define EXECUTE_IF_AND_IN_BITMAP(BITMAP1, BITMAP2, MIN, BITNUM, ITER) \ - for (bmp_iter_and_init (&(ITER), (BITMAP1), (BITMAP2), (MIN), \ - &(BITNUM)); \ - bmp_iter_and (&(ITER), &(BITNUM)); \ - bmp_iter_next (&(ITER), &(BITNUM))) - -/* Loop over all the bits set in BITMAP1 & ~BITMAP2, starting with MIN - and setting BITNUM to the bit number. ITER is a bitmap iterator. - BITNUM should be treated as a read-only variable as it contains - loop state. */ - -#define EXECUTE_IF_AND_COMPL_IN_BITMAP(BITMAP1, BITMAP2, MIN, BITNUM, ITER) \ - for (bmp_iter_and_compl_init (&(ITER), (BITMAP1), (BITMAP2), (MIN), \ - &(BITNUM)); \ - bmp_iter_and_compl (&(ITER), &(BITNUM)); \ - bmp_iter_next (&(ITER), &(BITNUM))) - -#endif /* GCC_BITMAP_H */ diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/builtin-attrs.def b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/builtin-attrs.def deleted file mode 100644 index 1338644..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/builtin-attrs.def +++ /dev/null @@ -1,287 +0,0 @@ -/* Copyright (C) 2001-2015 Free Software Foundation, Inc. - Contributed by Joseph Myers . - -This file is part of GCC. - -GCC is free software; you can redistribute it and/or modify it under -the terms of the GNU General Public License as published by the Free -Software Foundation; either version 3, or (at your option) any later -version. - -GCC is distributed in the hope that it will be useful, but WITHOUT ANY -WARRANTY; without even the implied warranty of MERCHANTABILITY or -FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -for more details. - -You should have received a copy of the GNU General Public License -along with GCC; see the file COPYING3. If not see -. */ - -/* This header provides a declarative way of describing the attributes - that are applied to some functions by default. - - Before including this header, you must define the following macros. - In each case where there is an ENUM, it is an identifier used to - reference the tree in subsequent definitions. - - DEF_ATTR_NULL_TREE (ENUM) - - Constructs a NULL_TREE. - - DEF_ATTR_INT (ENUM, VALUE) - - Constructs an INTEGER_CST with value VALUE (an integer representable - in HOST_WIDE_INT). - - DEF_ATTR_IDENT (ENUM, STRING) - - Constructs an IDENTIFIER_NODE for STRING. - - DEF_ATTR_TREE_LIST (ENUM, PURPOSE, VALUE, CHAIN) - - Constructs a TREE_LIST with given PURPOSE, VALUE and CHAIN (given - as previous ENUM names). */ - -DEF_ATTR_NULL_TREE (ATTR_NULL) - -/* Construct a tree for a given integer and a list containing it. */ -#define DEF_ATTR_FOR_INT(VALUE) \ - DEF_ATTR_INT (ATTR_##VALUE, VALUE) \ - DEF_ATTR_TREE_LIST (ATTR_LIST_##VALUE, ATTR_NULL, \ - ATTR_##VALUE, ATTR_NULL) -DEF_ATTR_FOR_INT (0) -DEF_ATTR_FOR_INT (1) -DEF_ATTR_FOR_INT (2) -DEF_ATTR_FOR_INT (3) -DEF_ATTR_FOR_INT (4) -DEF_ATTR_FOR_INT (5) -DEF_ATTR_FOR_INT (6) -#undef DEF_ATTR_FOR_INT - -/* Construct a tree for a given string and a list containing it. */ -#define DEF_ATTR_FOR_STRING(ENUM, VALUE) \ - DEF_ATTR_STRING (ATTR_##ENUM, VALUE) \ - DEF_ATTR_TREE_LIST (ATTR_LIST_##ENUM, ATTR_NULL, \ - ATTR_##ENUM, ATTR_NULL) -DEF_ATTR_FOR_STRING (STR1, "1") -#undef DEF_ATTR_FOR_STRING - -/* Construct a tree for a list of two integers. */ -#define DEF_LIST_INT_INT(VALUE1, VALUE2) \ - DEF_ATTR_TREE_LIST (ATTR_LIST_##VALUE1##_##VALUE2, ATTR_NULL, \ - ATTR_##VALUE1, ATTR_LIST_##VALUE2) -DEF_LIST_INT_INT (1,0) -DEF_LIST_INT_INT (1,2) -DEF_LIST_INT_INT (2,0) -DEF_LIST_INT_INT (2,3) -DEF_LIST_INT_INT (3,0) -DEF_LIST_INT_INT (3,4) -DEF_LIST_INT_INT (4,0) -DEF_LIST_INT_INT (4,5) -DEF_LIST_INT_INT (5,0) -DEF_LIST_INT_INT (5,6) -#undef DEF_LIST_INT_INT - -/* Construct trees for identifiers. */ -DEF_ATTR_IDENT (ATTR_COLD, "cold") -DEF_ATTR_IDENT (ATTR_CONST, "const") -DEF_ATTR_IDENT (ATTR_FORMAT, "format") -DEF_ATTR_IDENT (ATTR_FORMAT_ARG, "format_arg") -DEF_ATTR_IDENT (ATTR_MALLOC, "malloc") -DEF_ATTR_IDENT (ATTR_NONNULL, "nonnull") -DEF_ATTR_IDENT (ATTR_NORETURN, "noreturn") -DEF_ATTR_IDENT (ATTR_NOTHROW, "nothrow") -DEF_ATTR_IDENT (ATTR_LEAF, "leaf") -DEF_ATTR_IDENT (ATTR_FNSPEC, "fn spec") -DEF_ATTR_IDENT (ATTR_PRINTF, "printf") -DEF_ATTR_IDENT (ATTR_ASM_FPRINTF, "asm_fprintf") -DEF_ATTR_IDENT (ATTR_GCC_DIAG, "gcc_diag") -DEF_ATTR_IDENT (ATTR_GCC_CDIAG, "gcc_cdiag") -DEF_ATTR_IDENT (ATTR_GCC_CXXDIAG, "gcc_cxxdiag") -DEF_ATTR_IDENT (ATTR_PURE, "pure") -DEF_ATTR_IDENT (ATTR_NOVOPS, "no vops") -DEF_ATTR_IDENT (ATTR_SCANF, "scanf") -DEF_ATTR_IDENT (ATTR_SENTINEL, "sentinel") -DEF_ATTR_IDENT (ATTR_STRFMON, "strfmon") -DEF_ATTR_IDENT (ATTR_STRFTIME, "strftime") -DEF_ATTR_IDENT (ATTR_TYPEGENERIC, "type generic") -DEF_ATTR_IDENT (ATTR_TM_REGPARM, "*tm regparm") -DEF_ATTR_IDENT (ATTR_TM_TMPURE, "transaction_pure") -DEF_ATTR_IDENT (ATTR_RETURNS_TWICE, "returns_twice") - -DEF_ATTR_TREE_LIST (ATTR_NOVOPS_LIST, ATTR_NOVOPS, ATTR_NULL, ATTR_NULL) - -DEF_ATTR_TREE_LIST (ATTR_NOVOPS_LEAF_LIST, ATTR_LEAF, ATTR_NULL, ATTR_NOVOPS_LIST) - -DEF_ATTR_TREE_LIST (ATTR_LEAF_LIST, ATTR_LEAF, ATTR_NULL, ATTR_NULL) - -DEF_ATTR_TREE_LIST (ATTR_NOTHROW_LIST, ATTR_NOTHROW, ATTR_NULL, ATTR_NULL) - -DEF_ATTR_TREE_LIST (ATTR_NOTHROW_LEAF_LIST, ATTR_LEAF, ATTR_NULL, ATTR_NOTHROW_LIST) - -DEF_ATTR_TREE_LIST (ATTR_CONST_NOTHROW_LIST, ATTR_CONST, \ - ATTR_NULL, ATTR_NOTHROW_LIST) -DEF_ATTR_TREE_LIST (ATTR_CONST_NOTHROW_LEAF_LIST, ATTR_CONST, \ - ATTR_NULL, ATTR_NOTHROW_LEAF_LIST) -DEF_ATTR_TREE_LIST (ATTR_PURE_NOTHROW_LIST, ATTR_PURE, \ - ATTR_NULL, ATTR_NOTHROW_LIST) -DEF_ATTR_TREE_LIST (ATTR_PURE_NOTHROW_LEAF_LIST, ATTR_PURE, \ - ATTR_NULL, ATTR_NOTHROW_LEAF_LIST) -DEF_ATTR_TREE_LIST (ATTR_NORETURN_NOTHROW_LIST, ATTR_NORETURN, \ - ATTR_NULL, ATTR_NOTHROW_LIST) -DEF_ATTR_TREE_LIST (ATTR_NORETURN_NOTHROW_LEAF_LIST, ATTR_NORETURN,\ - ATTR_NULL, ATTR_NOTHROW_LEAF_LIST) -DEF_ATTR_TREE_LIST (ATTR_COLD_NOTHROW_LEAF_LIST, ATTR_COLD,\ - ATTR_NULL, ATTR_NOTHROW_LEAF_LIST) -DEF_ATTR_TREE_LIST (ATTR_COLD_NORETURN_NOTHROW_LEAF_LIST, ATTR_COLD,\ - ATTR_NULL, ATTR_NORETURN_NOTHROW_LEAF_LIST) -DEF_ATTR_TREE_LIST (ATTR_CONST_NORETURN_NOTHROW_LEAF_LIST, ATTR_CONST,\ - ATTR_NULL, ATTR_NORETURN_NOTHROW_LEAF_LIST) -DEF_ATTR_TREE_LIST (ATTR_MALLOC_NOTHROW_LIST, ATTR_MALLOC, \ - ATTR_NULL, ATTR_NOTHROW_LIST) -DEF_ATTR_TREE_LIST (ATTR_MALLOC_NOTHROW_LEAF_LIST, ATTR_MALLOC, \ - ATTR_NULL, ATTR_NOTHROW_LEAF_LIST) -DEF_ATTR_TREE_LIST (ATTR_SENTINEL_NOTHROW_LIST, ATTR_SENTINEL, \ - ATTR_NULL, ATTR_NOTHROW_LIST) -DEF_ATTR_TREE_LIST (ATTR_SENTINEL_NOTHROW_LEAF_LIST, ATTR_SENTINEL, \ - ATTR_NULL, ATTR_NOTHROW_LEAF_LIST) -DEF_ATTR_TREE_LIST (ATTR_COLD_CONST_NORETURN_NOTHROW_LEAF_LIST, ATTR_CONST,\ - ATTR_NULL, ATTR_COLD_NORETURN_NOTHROW_LEAF_LIST) - -/* Functions whose pointer parameter(s) are all nonnull. */ -DEF_ATTR_TREE_LIST (ATTR_NONNULL_LIST, ATTR_NONNULL, ATTR_NULL, ATTR_NULL) -/* Functions whose first parameter is a nonnull pointer. */ -DEF_ATTR_TREE_LIST (ATTR_NONNULL_1, ATTR_NONNULL, ATTR_LIST_1, ATTR_NULL) -/* Functions whose second parameter is a nonnull pointer. */ -DEF_ATTR_TREE_LIST (ATTR_NONNULL_2, ATTR_NONNULL, ATTR_LIST_2, ATTR_NULL) -/* Functions whose third parameter is a nonnull pointer. */ -DEF_ATTR_TREE_LIST (ATTR_NONNULL_3, ATTR_NONNULL, ATTR_LIST_3, ATTR_NULL) -/* Nothrow functions with the sentinel(1) attribute. */ -DEF_ATTR_TREE_LIST (ATTR_NOTHROW_SENTINEL_1, ATTR_SENTINEL, ATTR_LIST_1, \ - ATTR_NOTHROW_LIST) -/* Nothrow functions whose pointer parameter(s) are all nonnull. */ -DEF_ATTR_TREE_LIST (ATTR_NOTHROW_NONNULL, ATTR_NONNULL, ATTR_NULL, \ - ATTR_NOTHROW_LIST) -/* Nothrow leaf functions whose pointer parameter(s) are all nonnull. */ -DEF_ATTR_TREE_LIST (ATTR_NOTHROW_NONNULL_LEAF, ATTR_NONNULL, ATTR_NULL, \ - ATTR_NOTHROW_LEAF_LIST) -/* Nothrow functions whose first parameter is a nonnull pointer. */ -DEF_ATTR_TREE_LIST (ATTR_NOTHROW_NONNULL_1, ATTR_NONNULL, ATTR_LIST_1, \ - ATTR_NOTHROW_LIST) -/* Nothrow functions whose second parameter is a nonnull pointer. */ -DEF_ATTR_TREE_LIST (ATTR_NOTHROW_NONNULL_2, ATTR_NONNULL, ATTR_LIST_2, \ - ATTR_NOTHROW_LIST) -/* Nothrow functions whose third parameter is a nonnull pointer. */ -DEF_ATTR_TREE_LIST (ATTR_NOTHROW_NONNULL_3, ATTR_NONNULL, ATTR_LIST_3, \ - ATTR_NOTHROW_LIST) -/* Nothrow functions whose fourth parameter is a nonnull pointer. */ -DEF_ATTR_TREE_LIST (ATTR_NOTHROW_NONNULL_4, ATTR_NONNULL, ATTR_LIST_4, \ - ATTR_NOTHROW_LIST) -/* Nothrow functions whose fifth parameter is a nonnull pointer. */ -DEF_ATTR_TREE_LIST (ATTR_NOTHROW_NONNULL_5, ATTR_NONNULL, ATTR_LIST_5, \ - ATTR_NOTHROW_LIST) -/* Nothrow leaf functions which are type-generic. */ -DEF_ATTR_TREE_LIST (ATTR_NOTHROW_TYPEGENERIC_LEAF, ATTR_TYPEGENERIC, ATTR_NULL, \ - ATTR_NOTHROW_LEAF_LIST) -/* Nothrow const functions whose pointer parameter(s) are all nonnull. */ -DEF_ATTR_TREE_LIST (ATTR_CONST_NOTHROW_NONNULL, ATTR_CONST, ATTR_NULL, \ - ATTR_NOTHROW_NONNULL) -/* Nothrow leaf functions whose pointer parameter(s) are all nonnull, - and which return their first argument. */ -DEF_ATTR_TREE_LIST (ATTR_RET1_NOTHROW_NONNULL_LEAF, ATTR_FNSPEC, ATTR_LIST_STR1, \ - ATTR_NOTHROW_NONNULL_LEAF) -/* Nothrow const leaf functions whose pointer parameter(s) are all nonnull. */ -DEF_ATTR_TREE_LIST (ATTR_CONST_NOTHROW_NONNULL_LEAF, ATTR_CONST, ATTR_NULL, \ - ATTR_NOTHROW_NONNULL_LEAF) -/* Nothrow const functions which are type-generic. */ -DEF_ATTR_TREE_LIST (ATTR_CONST_NOTHROW_TYPEGENERIC, ATTR_TYPEGENERIC, ATTR_NULL, \ - ATTR_CONST_NOTHROW_LIST) -/* Nothrow const leaf functions which are type-generic. */ -DEF_ATTR_TREE_LIST (ATTR_CONST_NOTHROW_TYPEGENERIC_LEAF, ATTR_TYPEGENERIC, ATTR_NULL, \ - ATTR_CONST_NOTHROW_LEAF_LIST) -/* Nothrow pure functions whose pointer parameter(s) are all nonnull. */ -DEF_ATTR_TREE_LIST (ATTR_PURE_NOTHROW_NONNULL, ATTR_PURE, ATTR_NULL, \ - ATTR_NOTHROW_NONNULL) -/* Nothrow pure leaf functions whose pointer parameter(s) are all nonnull. */ -DEF_ATTR_TREE_LIST (ATTR_PURE_NOTHROW_NONNULL_LEAF, ATTR_PURE, ATTR_NULL, \ - ATTR_NOTHROW_NONNULL_LEAF) -/* Nothrow malloc functions whose pointer parameter(s) are all nonnull. */ -DEF_ATTR_TREE_LIST (ATTR_MALLOC_NOTHROW_NONNULL, ATTR_MALLOC, ATTR_NULL, \ - ATTR_NOTHROW_NONNULL) -/* Nothrow malloc leaf functions whose pointer parameter(s) are all nonnull. */ -DEF_ATTR_TREE_LIST (ATTR_MALLOC_NOTHROW_NONNULL_LEAF, ATTR_MALLOC, ATTR_NULL, \ - ATTR_NOTHROW_NONNULL_LEAF) - -/* Construct a tree for a format attribute. */ -#define DEF_FORMAT_ATTRIBUTE(TYPE, FA, VALUES) \ - DEF_ATTR_TREE_LIST (ATTR_##TYPE##_##VALUES, ATTR_NULL, \ - ATTR_##TYPE, ATTR_LIST_##VALUES) \ - DEF_ATTR_TREE_LIST (ATTR_FORMAT_##TYPE##_##VALUES, ATTR_FORMAT, \ - ATTR_##TYPE##_##VALUES, ATTR_NONNULL_##FA) -#define DEF_FORMAT_ATTRIBUTE_NOTHROW(TYPE, FA, VALUES) \ - DEF_ATTR_TREE_LIST (ATTR_##TYPE##_##VALUES, ATTR_NULL, \ - ATTR_##TYPE, ATTR_LIST_##VALUES) \ - DEF_ATTR_TREE_LIST (ATTR_FORMAT_##TYPE##_NOTHROW_##VALUES, ATTR_FORMAT,\ - ATTR_##TYPE##_##VALUES, ATTR_NOTHROW_NONNULL_##FA) -#define DEF_FORMAT_ATTRIBUTE_BOTH(TYPE, FA, VALUES) \ - DEF_ATTR_TREE_LIST (ATTR_##TYPE##_##VALUES, ATTR_NULL, \ - ATTR_##TYPE, ATTR_LIST_##VALUES) \ - DEF_ATTR_TREE_LIST (ATTR_FORMAT_##TYPE##_##VALUES, ATTR_FORMAT, \ - ATTR_##TYPE##_##VALUES, ATTR_NONNULL_##FA) \ - DEF_ATTR_TREE_LIST (ATTR_FORMAT_##TYPE##_NOTHROW_##VALUES, ATTR_FORMAT,\ - ATTR_##TYPE##_##VALUES, ATTR_NOTHROW_NONNULL_##FA) -DEF_FORMAT_ATTRIBUTE(PRINTF,1,1_0) -DEF_FORMAT_ATTRIBUTE(PRINTF,1,1_2) -DEF_FORMAT_ATTRIBUTE_BOTH(PRINTF,2,2_0) -DEF_FORMAT_ATTRIBUTE_BOTH(PRINTF,2,2_3) -DEF_FORMAT_ATTRIBUTE_BOTH(PRINTF,3,3_0) -DEF_FORMAT_ATTRIBUTE_BOTH(PRINTF,3,3_4) -DEF_FORMAT_ATTRIBUTE_NOTHROW(PRINTF,4,4_0) -DEF_FORMAT_ATTRIBUTE_NOTHROW(PRINTF,4,4_5) -DEF_FORMAT_ATTRIBUTE_NOTHROW(PRINTF,5,5_0) -DEF_FORMAT_ATTRIBUTE_NOTHROW(PRINTF,5,5_6) -DEF_FORMAT_ATTRIBUTE(SCANF,1,1_0) -DEF_FORMAT_ATTRIBUTE(SCANF,1,1_2) -DEF_FORMAT_ATTRIBUTE_BOTH(SCANF,2,2_0) -DEF_FORMAT_ATTRIBUTE_BOTH(SCANF,2,2_3) -DEF_FORMAT_ATTRIBUTE_NOTHROW(STRFTIME,3,3_0) -DEF_FORMAT_ATTRIBUTE_NOTHROW(STRFMON,3,3_4) -#undef DEF_FORMAT_ATTRIBUTE -#undef DEF_FORMAT_ATTRIBUTE_NOTHROW -#undef DEF_FORMAT_ATTRIBUTE_BOTH - -/* Transactional memory variants of the above. */ - -DEF_ATTR_TREE_LIST (ATTR_TM_NOTHROW_LIST, - ATTR_TM_REGPARM, ATTR_NULL, ATTR_NOTHROW_LIST) -DEF_ATTR_TREE_LIST (ATTR_TM_TMPURE_NOTHROW_LIST, - ATTR_TM_TMPURE, ATTR_NULL, ATTR_TM_NOTHROW_LIST) -DEF_ATTR_TREE_LIST (ATTR_TM_PURE_TMPURE_NOTHROW_LIST, - ATTR_PURE, ATTR_NULL, ATTR_TM_TMPURE_NOTHROW_LIST) -DEF_ATTR_TREE_LIST (ATTR_TM_NORETURN_NOTHROW_LIST, - ATTR_TM_REGPARM, ATTR_NULL, ATTR_NORETURN_NOTHROW_LIST) -DEF_ATTR_TREE_LIST (ATTR_TM_CONST_NOTHROW_LIST, - ATTR_TM_REGPARM, ATTR_NULL, ATTR_CONST_NOTHROW_LIST) -DEF_ATTR_TREE_LIST (ATTR_TM_NOTHROW_RT_LIST, - ATTR_RETURNS_TWICE, ATTR_NULL, ATTR_TM_NOTHROW_LIST) - -/* Same attributes used for BUILT_IN_MALLOC except with TM_PURE thrown in. */ -DEF_ATTR_TREE_LIST (ATTR_TMPURE_MALLOC_NOTHROW_LIST, - ATTR_TM_TMPURE, ATTR_NULL, ATTR_MALLOC_NOTHROW_LIST) -/* Same attributes used for BUILT_IN_FREE except with TM_PURE thrown in. */ -DEF_ATTR_TREE_LIST (ATTR_TMPURE_NOTHROW_LIST, - ATTR_TM_TMPURE, ATTR_NULL, ATTR_NOTHROW_LIST) - -DEF_ATTR_TREE_LIST (ATTR_TMPURE_NOTHROW_LEAF_LIST, - ATTR_TM_TMPURE, ATTR_NULL, ATTR_NOTHROW_LEAF_LIST) -DEF_ATTR_TREE_LIST (ATTR_TMPURE_NORETURN_NOTHROW_LEAF_LIST, - ATTR_TM_TMPURE, ATTR_NULL, ATTR_NORETURN_NOTHROW_LEAF_LIST) - -/* Construct a tree for a format_arg attribute. */ -#define DEF_FORMAT_ARG_ATTRIBUTE(FA) \ - DEF_ATTR_TREE_LIST (ATTR_FORMAT_ARG_##FA, ATTR_FORMAT_ARG, \ - ATTR_LIST_##FA, ATTR_NOTHROW_NONNULL_##FA) -DEF_FORMAT_ARG_ATTRIBUTE(1) -DEF_FORMAT_ARG_ATTRIBUTE(2) -#undef DEF_FORMAT_ARG_ATTRIBUTE - diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/builtin-types.def b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/builtin-types.def deleted file mode 100644 index 0e34531..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/builtin-types.def +++ /dev/null @@ -1,625 +0,0 @@ -/* Copyright (C) 2001-2015 Free Software Foundation, Inc. - -This file is part of GCC. - -GCC is free software; you can redistribute it and/or modify it under -the terms of the GNU General Public License as published by the Free -Software Foundation; either version 3, or (at your option) any later -version. - -GCC is distributed in the hope that it will be useful, but WITHOUT ANY -WARRANTY; without even the implied warranty of MERCHANTABILITY or -FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -for more details. - -You should have received a copy of the GNU General Public License -along with GCC; see the file COPYING3. If not see -. */ - -/* This header provides a declarative way of describing the types that - are used when declaring builtin functions. - - Before including this header, you must define the following macros: - - DEF_PRIMITIVE_TYPE (ENUM, TYPE) - - The ENUM is an identifier indicating which type is being defined. - TYPE is an expression for a `tree' that represents the type. - - DEF_FUNCTION_TYPE_0 (ENUM, RETURN) - DEF_FUNCTION_TYPE_1 (ENUM, RETURN, ARG1) - DEF_FUNCTION_TYPE_2 (ENUM, RETURN, ARG1, ARG2) - [...] - - These macros describe function types. ENUM is as above. The - RETURN type is one of the enumerals already defined. ARG1, ARG2, - etc, give the types of the arguments, similarly. - - DEF_FUNCTION_TYPE_VAR_0 (ENUM, RETURN) - DEF_FUNCTION_TYPE_VAR_1 (ENUM, RETURN, ARG1) - DEF_FUNCTION_TYPE_VAR_2 (ENUM, RETURN, ARG1, ARG2) - [...] - - Similar, but for function types that take variable arguments. - For example: - - DEF_FUNCTION_TYPE_1 (BT_INT_DOUBLE, BT_INT, BT_DOUBLE) - - describes the type `int ()(double)', using the enumeral - BT_INT_DOUBLE, whereas: - - DEF_FUNCTION_TYPE_VAR_1 (BT_INT_DOUBLE_VAR, BT_INT, BT_DOUBLE) - - describes the type `int ()(double, ...)'. - - DEF_POINTER_TYPE (ENUM, TYPE) - - This macro describes a pointer type. ENUM is as above; TYPE is - the type pointed to. */ - -DEF_PRIMITIVE_TYPE (BT_VOID, void_type_node) -DEF_PRIMITIVE_TYPE (BT_BOOL, boolean_type_node) -DEF_PRIMITIVE_TYPE (BT_INT, integer_type_node) -DEF_PRIMITIVE_TYPE (BT_UINT, unsigned_type_node) -DEF_PRIMITIVE_TYPE (BT_LONG, long_integer_type_node) -DEF_PRIMITIVE_TYPE (BT_ULONG, long_unsigned_type_node) -DEF_PRIMITIVE_TYPE (BT_LONGLONG, long_long_integer_type_node) -DEF_PRIMITIVE_TYPE (BT_ULONGLONG, long_long_unsigned_type_node) -DEF_PRIMITIVE_TYPE (BT_INTMAX, intmax_type_node) -DEF_PRIMITIVE_TYPE (BT_UINTMAX, uintmax_type_node) -DEF_PRIMITIVE_TYPE (BT_UINT16, uint16_type_node) -DEF_PRIMITIVE_TYPE (BT_UINT32, uint32_type_node) -DEF_PRIMITIVE_TYPE (BT_UINT64, uint64_type_node) -DEF_PRIMITIVE_TYPE (BT_WORD, (*lang_hooks.types.type_for_mode) (word_mode, 1)) -DEF_PRIMITIVE_TYPE (BT_UNWINDWORD, (*lang_hooks.types.type_for_mode) - (targetm.unwind_word_mode (), 1)) -DEF_PRIMITIVE_TYPE (BT_FLOAT, float_type_node) -DEF_PRIMITIVE_TYPE (BT_DOUBLE, double_type_node) -DEF_PRIMITIVE_TYPE (BT_LONGDOUBLE, long_double_type_node) -DEF_PRIMITIVE_TYPE (BT_COMPLEX_FLOAT, complex_float_type_node) -DEF_PRIMITIVE_TYPE (BT_COMPLEX_DOUBLE, complex_double_type_node) -DEF_PRIMITIVE_TYPE (BT_COMPLEX_LONGDOUBLE, complex_long_double_type_node) - -DEF_PRIMITIVE_TYPE (BT_PTR, ptr_type_node) -DEF_PRIMITIVE_TYPE (BT_FILEPTR, fileptr_type_node) -DEF_PRIMITIVE_TYPE (BT_CONST_PTR, const_ptr_type_node) -DEF_PRIMITIVE_TYPE (BT_VOLATILE_PTR, - build_pointer_type - (build_qualified_type (void_type_node, - TYPE_QUAL_VOLATILE))) -DEF_PRIMITIVE_TYPE (BT_CONST_VOLATILE_PTR, - build_pointer_type - (build_qualified_type (void_type_node, - TYPE_QUAL_VOLATILE|TYPE_QUAL_CONST))) -DEF_PRIMITIVE_TYPE (BT_PTRMODE, (*lang_hooks.types.type_for_mode)(ptr_mode, 0)) -DEF_PRIMITIVE_TYPE (BT_INT_PTR, integer_ptr_type_node) -DEF_PRIMITIVE_TYPE (BT_FLOAT_PTR, float_ptr_type_node) -DEF_PRIMITIVE_TYPE (BT_DOUBLE_PTR, double_ptr_type_node) -DEF_PRIMITIVE_TYPE (BT_CONST_DOUBLE_PTR, - build_pointer_type - (build_qualified_type (double_type_node, - TYPE_QUAL_CONST))) -DEF_PRIMITIVE_TYPE (BT_LONGDOUBLE_PTR, long_double_ptr_type_node) -DEF_PRIMITIVE_TYPE (BT_PID, pid_type_node) -DEF_PRIMITIVE_TYPE (BT_SIZE, size_type_node) -DEF_PRIMITIVE_TYPE (BT_SSIZE, signed_size_type_node) -DEF_PRIMITIVE_TYPE (BT_WINT, wint_type_node) -DEF_PRIMITIVE_TYPE (BT_STRING, string_type_node) -DEF_PRIMITIVE_TYPE (BT_CONST_STRING, const_string_type_node) - -DEF_PRIMITIVE_TYPE (BT_DFLOAT32, dfloat32_type_node) -DEF_PRIMITIVE_TYPE (BT_DFLOAT64, dfloat64_type_node) -DEF_PRIMITIVE_TYPE (BT_DFLOAT128, dfloat128_type_node) -DEF_PRIMITIVE_TYPE (BT_DFLOAT32_PTR, dfloat32_ptr_type_node) -DEF_PRIMITIVE_TYPE (BT_DFLOAT64_PTR, dfloat64_ptr_type_node) -DEF_PRIMITIVE_TYPE (BT_DFLOAT128_PTR, dfloat128_ptr_type_node) - -DEF_PRIMITIVE_TYPE (BT_VALIST_REF, va_list_ref_type_node) -DEF_PRIMITIVE_TYPE (BT_VALIST_ARG, va_list_arg_type_node) - -DEF_PRIMITIVE_TYPE (BT_I1, builtin_type_for_size (BITS_PER_UNIT*1, 1)) -DEF_PRIMITIVE_TYPE (BT_I2, builtin_type_for_size (BITS_PER_UNIT*2, 1)) -DEF_PRIMITIVE_TYPE (BT_I4, builtin_type_for_size (BITS_PER_UNIT*4, 1)) -DEF_PRIMITIVE_TYPE (BT_I8, builtin_type_for_size (BITS_PER_UNIT*8, 1)) -DEF_PRIMITIVE_TYPE (BT_I16, builtin_type_for_size (BITS_PER_UNIT*16, 1)) - -DEF_PRIMITIVE_TYPE (BT_BND, pointer_bounds_type_node) - -DEF_POINTER_TYPE (BT_PTR_CONST_STRING, BT_CONST_STRING) -DEF_POINTER_TYPE (BT_PTR_UINT, BT_UINT) -DEF_POINTER_TYPE (BT_PTR_LONG, BT_LONG) -DEF_POINTER_TYPE (BT_PTR_ULONG, BT_ULONG) -DEF_POINTER_TYPE (BT_PTR_LONGLONG, BT_LONGLONG) -DEF_POINTER_TYPE (BT_PTR_ULONGLONG, BT_ULONGLONG) -DEF_POINTER_TYPE (BT_PTR_PTR, BT_PTR) - -DEF_FUNCTION_TYPE_0 (BT_FN_VOID, BT_VOID) -DEF_FUNCTION_TYPE_0 (BT_FN_BOOL, BT_BOOL) -DEF_FUNCTION_TYPE_0 (BT_FN_PTR, BT_PTR) -DEF_FUNCTION_TYPE_0 (BT_FN_CONST_STRING, BT_CONST_STRING) -DEF_FUNCTION_TYPE_0 (BT_FN_PID, BT_PID) -DEF_FUNCTION_TYPE_0 (BT_FN_INT, BT_INT) -DEF_FUNCTION_TYPE_0 (BT_FN_UINT, BT_UINT) -DEF_FUNCTION_TYPE_0 (BT_FN_FLOAT, BT_FLOAT) -DEF_FUNCTION_TYPE_0 (BT_FN_DOUBLE, BT_DOUBLE) -/* For "long double" we use LONGDOUBLE (not LONG_DOUBLE) to - distinguish it from two types in sequence, "long" followed by - "double". */ -DEF_FUNCTION_TYPE_0 (BT_FN_LONGDOUBLE, BT_LONGDOUBLE) -DEF_FUNCTION_TYPE_0 (BT_FN_DFLOAT32, BT_DFLOAT32) -DEF_FUNCTION_TYPE_0 (BT_FN_DFLOAT64, BT_DFLOAT64) -DEF_FUNCTION_TYPE_0 (BT_FN_DFLOAT128, BT_DFLOAT128) - -DEF_FUNCTION_TYPE_1 (BT_FN_LONG_LONG, BT_LONG, BT_LONG) -DEF_FUNCTION_TYPE_1 (BT_FN_LONGLONG_LONGLONG, BT_LONGLONG, BT_LONGLONG) -DEF_FUNCTION_TYPE_1 (BT_FN_INTMAX_INTMAX, BT_INTMAX, BT_INTMAX) -DEF_FUNCTION_TYPE_1 (BT_FN_FLOAT_FLOAT, BT_FLOAT, BT_FLOAT) -DEF_FUNCTION_TYPE_1 (BT_FN_DOUBLE_DOUBLE, BT_DOUBLE, BT_DOUBLE) -DEF_FUNCTION_TYPE_1 (BT_FN_LONGDOUBLE_LONGDOUBLE, - BT_LONGDOUBLE, BT_LONGDOUBLE) -DEF_FUNCTION_TYPE_1 (BT_FN_COMPLEX_FLOAT_COMPLEX_FLOAT, - BT_COMPLEX_FLOAT, BT_COMPLEX_FLOAT) -DEF_FUNCTION_TYPE_1 (BT_FN_COMPLEX_DOUBLE_COMPLEX_DOUBLE, - BT_COMPLEX_DOUBLE, BT_COMPLEX_DOUBLE) -DEF_FUNCTION_TYPE_1 (BT_FN_COMPLEX_LONGDOUBLE_COMPLEX_LONGDOUBLE, - BT_COMPLEX_LONGDOUBLE, BT_COMPLEX_LONGDOUBLE) -DEF_FUNCTION_TYPE_1 (BT_FN_FLOAT_COMPLEX_FLOAT, - BT_FLOAT, BT_COMPLEX_FLOAT) -DEF_FUNCTION_TYPE_1 (BT_FN_DOUBLE_COMPLEX_DOUBLE, - BT_DOUBLE, BT_COMPLEX_DOUBLE) -DEF_FUNCTION_TYPE_1 (BT_FN_LONGDOUBLE_COMPLEX_LONGDOUBLE, - BT_LONGDOUBLE, BT_COMPLEX_LONGDOUBLE) -DEF_FUNCTION_TYPE_1 (BT_FN_COMPLEX_FLOAT_FLOAT, - BT_COMPLEX_FLOAT, BT_FLOAT) -DEF_FUNCTION_TYPE_1 (BT_FN_COMPLEX_DOUBLE_DOUBLE, - BT_COMPLEX_DOUBLE, BT_DOUBLE) -DEF_FUNCTION_TYPE_1 (BT_FN_COMPLEX_LONGDOUBLE_LONGDOUBLE, - BT_COMPLEX_LONGDOUBLE, BT_LONGDOUBLE) -DEF_FUNCTION_TYPE_1 (BT_FN_PTR_UINT, BT_PTR, BT_UINT) -DEF_FUNCTION_TYPE_1 (BT_FN_PTR_SIZE, BT_PTR, BT_SIZE) -DEF_FUNCTION_TYPE_1 (BT_FN_INT_INT, BT_INT, BT_INT) -DEF_FUNCTION_TYPE_1 (BT_FN_INT_UINT, BT_INT, BT_UINT) -DEF_FUNCTION_TYPE_1 (BT_FN_INT_LONG, BT_INT, BT_LONG) -DEF_FUNCTION_TYPE_1 (BT_FN_INT_ULONG, BT_INT, BT_ULONG) -DEF_FUNCTION_TYPE_1 (BT_FN_INT_LONGLONG, BT_INT, BT_LONGLONG) -DEF_FUNCTION_TYPE_1 (BT_FN_INT_ULONGLONG, BT_INT, BT_ULONGLONG) -DEF_FUNCTION_TYPE_1 (BT_FN_INT_INTMAX, BT_INT, BT_INTMAX) -DEF_FUNCTION_TYPE_1 (BT_FN_INT_UINTMAX, BT_INT, BT_UINTMAX) -DEF_FUNCTION_TYPE_1 (BT_FN_INT_PTR, BT_INT, BT_PTR) -DEF_FUNCTION_TYPE_1 (BT_FN_INT_FLOAT, BT_INT, BT_FLOAT) -DEF_FUNCTION_TYPE_1 (BT_FN_INT_DOUBLE, BT_INT, BT_DOUBLE) -DEF_FUNCTION_TYPE_1 (BT_FN_INT_LONGDOUBLE, BT_INT, BT_LONGDOUBLE) -DEF_FUNCTION_TYPE_1 (BT_FN_INT_DFLOAT32, BT_INT, BT_DFLOAT32) -DEF_FUNCTION_TYPE_1 (BT_FN_INT_DFLOAT64, BT_INT, BT_DFLOAT64) -DEF_FUNCTION_TYPE_1 (BT_FN_INT_DFLOAT128, BT_INT, BT_DFLOAT128) -DEF_FUNCTION_TYPE_1 (BT_FN_LONG_FLOAT, BT_LONG, BT_FLOAT) -DEF_FUNCTION_TYPE_1 (BT_FN_LONG_DOUBLE, BT_LONG, BT_DOUBLE) -DEF_FUNCTION_TYPE_1 (BT_FN_LONG_LONGDOUBLE, BT_LONG, BT_LONGDOUBLE) -DEF_FUNCTION_TYPE_1 (BT_FN_LONGLONG_FLOAT, BT_LONGLONG, BT_FLOAT) -DEF_FUNCTION_TYPE_1 (BT_FN_LONGLONG_DOUBLE, BT_LONGLONG, BT_DOUBLE) -DEF_FUNCTION_TYPE_1 (BT_FN_LONGLONG_LONGDOUBLE, BT_LONGLONG, BT_LONGDOUBLE) -DEF_FUNCTION_TYPE_1 (BT_FN_VOID_PTR, BT_VOID, BT_PTR) -DEF_FUNCTION_TYPE_1 (BT_FN_SIZE_CONST_STRING, BT_SIZE, BT_CONST_STRING) -DEF_FUNCTION_TYPE_1 (BT_FN_INT_CONST_STRING, BT_INT, BT_CONST_STRING) -DEF_FUNCTION_TYPE_1 (BT_FN_PTR_PTR, BT_PTR, BT_PTR) -DEF_FUNCTION_TYPE_1 (BT_FN_VOID_VALIST_REF, BT_VOID, BT_VALIST_REF) -DEF_FUNCTION_TYPE_1 (BT_FN_VOID_INT, BT_VOID, BT_INT) -DEF_FUNCTION_TYPE_1 (BT_FN_FLOAT_CONST_STRING, BT_FLOAT, BT_CONST_STRING) -DEF_FUNCTION_TYPE_1 (BT_FN_DOUBLE_CONST_STRING, BT_DOUBLE, BT_CONST_STRING) -DEF_FUNCTION_TYPE_1 (BT_FN_LONGDOUBLE_CONST_STRING, - BT_LONGDOUBLE, BT_CONST_STRING) -DEF_FUNCTION_TYPE_1 (BT_FN_DFLOAT32_CONST_STRING, BT_DFLOAT32, BT_CONST_STRING) -DEF_FUNCTION_TYPE_1 (BT_FN_DFLOAT64_CONST_STRING, BT_DFLOAT64, BT_CONST_STRING) -DEF_FUNCTION_TYPE_1 (BT_FN_DFLOAT128_CONST_STRING, - BT_DFLOAT128, BT_CONST_STRING) -DEF_FUNCTION_TYPE_1 (BT_FN_STRING_CONST_STRING, BT_STRING, BT_CONST_STRING) -DEF_FUNCTION_TYPE_1 (BT_FN_UNWINDWORD_PTR, BT_UNWINDWORD, BT_PTR) -DEF_FUNCTION_TYPE_1 (BT_FN_INT_WINT, BT_INT, BT_WINT) -DEF_FUNCTION_TYPE_1 (BT_FN_WINT_WINT, BT_WINT, BT_WINT) -DEF_FUNCTION_TYPE_1 (BT_FN_DFLOAT32_DFLOAT32, BT_DFLOAT32, BT_DFLOAT32) -DEF_FUNCTION_TYPE_1 (BT_FN_DFLOAT64_DFLOAT64, BT_DFLOAT64, BT_DFLOAT64) -DEF_FUNCTION_TYPE_1 (BT_FN_DFLOAT128_DFLOAT128, BT_DFLOAT128, BT_DFLOAT128) -DEF_FUNCTION_TYPE_1 (BT_FN_VOID_VPTR, BT_VOID, BT_VOLATILE_PTR) -DEF_FUNCTION_TYPE_1 (BT_FN_VOID_PTRPTR, BT_VOID, BT_PTR_PTR) -DEF_FUNCTION_TYPE_1 (BT_FN_VOID_CONST_PTR, BT_VOID, BT_CONST_PTR) -DEF_FUNCTION_TYPE_1 (BT_FN_UINT_UINT, BT_UINT, BT_UINT) -DEF_FUNCTION_TYPE_1 (BT_FN_ULONG_ULONG, BT_ULONG, BT_ULONG) -DEF_FUNCTION_TYPE_1 (BT_FN_ULONGLONG_ULONGLONG, BT_ULONGLONG, BT_ULONGLONG) -DEF_FUNCTION_TYPE_1 (BT_FN_UINT16_UINT16, BT_UINT16, BT_UINT16) -DEF_FUNCTION_TYPE_1 (BT_FN_UINT32_UINT32, BT_UINT32, BT_UINT32) -DEF_FUNCTION_TYPE_1 (BT_FN_UINT64_UINT64, BT_UINT64, BT_UINT64) -DEF_FUNCTION_TYPE_1 (BT_FN_BOOL_INT, BT_BOOL, BT_INT) -DEF_FUNCTION_TYPE_1 (BT_FN_PTR_CONST_PTR, BT_PTR, BT_CONST_PTR) -DEF_FUNCTION_TYPE_1 (BT_FN_CONST_PTR_CONST_PTR, BT_CONST_PTR, BT_CONST_PTR) -DEF_FUNCTION_TYPE_1 (BT_FN_BND_CONST_PTR, BT_BND, BT_CONST_PTR) -DEF_FUNCTION_TYPE_1 (BT_FN_CONST_PTR_BND, BT_CONST_PTR, BT_BND) - -DEF_POINTER_TYPE (BT_PTR_FN_VOID_PTR, BT_FN_VOID_PTR) - -DEF_FUNCTION_TYPE_2 (BT_FN_VOID_PTR_INT, BT_VOID, BT_PTR, BT_INT) -DEF_FUNCTION_TYPE_2 (BT_FN_STRING_STRING_CONST_STRING, - BT_STRING, BT_STRING, BT_CONST_STRING) -DEF_FUNCTION_TYPE_2 (BT_FN_INT_CONST_STRING_CONST_STRING, - BT_INT, BT_CONST_STRING, BT_CONST_STRING) -DEF_FUNCTION_TYPE_2 (BT_FN_STRING_CONST_STRING_CONST_STRING, - BT_STRING, BT_CONST_STRING, BT_CONST_STRING) -DEF_FUNCTION_TYPE_2 (BT_FN_SIZE_CONST_STRING_CONST_STRING, - BT_SIZE, BT_CONST_STRING, BT_CONST_STRING) -DEF_FUNCTION_TYPE_2 (BT_FN_STRING_CONST_STRING_INT, - BT_STRING, BT_CONST_STRING, BT_INT) -DEF_FUNCTION_TYPE_2 (BT_FN_STRING_CONST_STRING_SIZE, - BT_STRING, BT_CONST_STRING, BT_SIZE) -DEF_FUNCTION_TYPE_2 (BT_FN_INT_CONST_STRING_FILEPTR, - BT_INT, BT_CONST_STRING, BT_FILEPTR) -DEF_FUNCTION_TYPE_2 (BT_FN_INT_INT_FILEPTR, - BT_INT, BT_INT, BT_FILEPTR) -DEF_FUNCTION_TYPE_2 (BT_FN_VOID_PTRMODE_PTR, - BT_VOID, BT_PTRMODE, BT_PTR) -DEF_FUNCTION_TYPE_2 (BT_FN_VOID_PTR_PTRMODE, - BT_VOID, BT_PTR, BT_PTRMODE) -DEF_FUNCTION_TYPE_2 (BT_FN_VOID_VALIST_REF_VALIST_ARG, - BT_VOID, BT_VALIST_REF, BT_VALIST_ARG) -DEF_FUNCTION_TYPE_2 (BT_FN_LONG_LONG_LONG, - BT_LONG, BT_LONG, BT_LONG) -DEF_FUNCTION_TYPE_2 (BT_FN_INT_PTR_CONST_STRING, - BT_INT, BT_PTR, BT_CONST_STRING) -DEF_FUNCTION_TYPE_2 (BT_FN_VOID_PTR_SIZE, - BT_VOID, BT_PTR, BT_SIZE) -DEF_FUNCTION_TYPE_2 (BT_FN_FLOAT_FLOAT_FLOAT, - BT_FLOAT, BT_FLOAT, BT_FLOAT) -DEF_FUNCTION_TYPE_2 (BT_FN_DOUBLE_DOUBLE_DOUBLE, - BT_DOUBLE, BT_DOUBLE, BT_DOUBLE) -DEF_FUNCTION_TYPE_2 (BT_FN_LONGDOUBLE_LONGDOUBLE_LONGDOUBLE, - BT_LONGDOUBLE, BT_LONGDOUBLE, BT_LONGDOUBLE) -DEF_FUNCTION_TYPE_2 (BT_FN_FLOAT_FLOAT_FLOATPTR, - BT_FLOAT, BT_FLOAT, BT_FLOAT_PTR) -DEF_FUNCTION_TYPE_2 (BT_FN_DOUBLE_DOUBLE_DOUBLEPTR, - BT_DOUBLE, BT_DOUBLE, BT_DOUBLE_PTR) -DEF_FUNCTION_TYPE_2 (BT_FN_LONGDOUBLE_LONGDOUBLE_LONGDOUBLEPTR, - BT_LONGDOUBLE, BT_LONGDOUBLE, BT_LONGDOUBLE_PTR) -DEF_FUNCTION_TYPE_2 (BT_FN_FLOAT_FLOAT_LONGDOUBLE, - BT_FLOAT, BT_FLOAT, BT_LONGDOUBLE) -DEF_FUNCTION_TYPE_2 (BT_FN_DOUBLE_DOUBLE_LONGDOUBLE, - BT_DOUBLE, BT_DOUBLE, BT_LONGDOUBLE) -DEF_FUNCTION_TYPE_2 (BT_FN_FLOAT_FLOAT_INT, - BT_FLOAT, BT_FLOAT, BT_INT) -DEF_FUNCTION_TYPE_2 (BT_FN_DOUBLE_DOUBLE_INT, - BT_DOUBLE, BT_DOUBLE, BT_INT) -DEF_FUNCTION_TYPE_2 (BT_FN_LONGDOUBLE_LONGDOUBLE_INT, - BT_LONGDOUBLE, BT_LONGDOUBLE, BT_INT) -DEF_FUNCTION_TYPE_2 (BT_FN_FLOAT_FLOAT_INTPTR, - BT_FLOAT, BT_FLOAT, BT_INT_PTR) -DEF_FUNCTION_TYPE_2 (BT_FN_DOUBLE_DOUBLE_INTPTR, - BT_DOUBLE, BT_DOUBLE, BT_INT_PTR) -DEF_FUNCTION_TYPE_2 (BT_FN_LONGDOUBLE_LONGDOUBLE_INTPTR, - BT_LONGDOUBLE, BT_LONGDOUBLE, BT_INT_PTR) -DEF_FUNCTION_TYPE_2 (BT_FN_FLOAT_INT_FLOAT, - BT_FLOAT, BT_INT, BT_FLOAT) -DEF_FUNCTION_TYPE_2 (BT_FN_DOUBLE_INT_DOUBLE, - BT_DOUBLE, BT_INT, BT_DOUBLE) -DEF_FUNCTION_TYPE_2 (BT_FN_LONGDOUBLE_INT_LONGDOUBLE, - BT_LONGDOUBLE, BT_INT, BT_LONGDOUBLE) -DEF_FUNCTION_TYPE_2 (BT_FN_FLOAT_FLOAT_LONG, - BT_FLOAT, BT_FLOAT, BT_LONG) -DEF_FUNCTION_TYPE_2 (BT_FN_DOUBLE_DOUBLE_LONG, - BT_DOUBLE, BT_DOUBLE, BT_LONG) -DEF_FUNCTION_TYPE_2 (BT_FN_LONGDOUBLE_LONGDOUBLE_LONG, - BT_LONGDOUBLE, BT_LONGDOUBLE, BT_LONG) -DEF_FUNCTION_TYPE_2 (BT_FN_INT_CONST_STRING_VALIST_ARG, - BT_INT, BT_CONST_STRING, BT_VALIST_ARG) -DEF_FUNCTION_TYPE_2 (BT_FN_PTR_SIZE_SIZE, - BT_PTR, BT_SIZE, BT_SIZE) -DEF_FUNCTION_TYPE_2 (BT_FN_PTR_PTR_SIZE, - BT_PTR, BT_PTR, BT_SIZE) -DEF_FUNCTION_TYPE_2 (BT_FN_COMPLEX_FLOAT_COMPLEX_FLOAT_COMPLEX_FLOAT, - BT_COMPLEX_FLOAT, BT_COMPLEX_FLOAT, BT_COMPLEX_FLOAT) -DEF_FUNCTION_TYPE_2 (BT_FN_COMPLEX_DOUBLE_COMPLEX_DOUBLE_COMPLEX_DOUBLE, - BT_COMPLEX_DOUBLE, BT_COMPLEX_DOUBLE, BT_COMPLEX_DOUBLE) -DEF_FUNCTION_TYPE_2 (BT_FN_COMPLEX_LONGDOUBLE_COMPLEX_LONGDOUBLE_COMPLEX_LONGDOUBLE, - BT_COMPLEX_LONGDOUBLE, BT_COMPLEX_LONGDOUBLE, BT_COMPLEX_LONGDOUBLE) -DEF_FUNCTION_TYPE_2 (BT_FN_VOID_PTR_PTR, BT_VOID, BT_PTR, BT_PTR) -DEF_FUNCTION_TYPE_2 (BT_FN_INT_CONST_STRING_PTR_CONST_STRING, - BT_INT, BT_CONST_STRING, BT_PTR_CONST_STRING) -DEF_FUNCTION_TYPE_2 (BT_FN_SIZE_CONST_PTR_INT, BT_SIZE, BT_CONST_PTR, BT_INT) -DEF_FUNCTION_TYPE_2 (BT_FN_I1_VPTR_I1, BT_I1, BT_VOLATILE_PTR, BT_I1) -DEF_FUNCTION_TYPE_2 (BT_FN_I2_VPTR_I2, BT_I2, BT_VOLATILE_PTR, BT_I2) -DEF_FUNCTION_TYPE_2 (BT_FN_I4_VPTR_I4, BT_I4, BT_VOLATILE_PTR, BT_I4) -DEF_FUNCTION_TYPE_2 (BT_FN_I8_VPTR_I8, BT_I8, BT_VOLATILE_PTR, BT_I8) -DEF_FUNCTION_TYPE_2 (BT_FN_I16_VPTR_I16, BT_I16, BT_VOLATILE_PTR, BT_I16) -DEF_FUNCTION_TYPE_2 (BT_FN_BOOL_LONGPTR_LONGPTR, - BT_BOOL, BT_PTR_LONG, BT_PTR_LONG) -DEF_FUNCTION_TYPE_2 (BT_FN_BOOL_ULONGLONGPTR_ULONGLONGPTR, - BT_BOOL, BT_PTR_ULONGLONG, BT_PTR_ULONGLONG) -DEF_FUNCTION_TYPE_2 (BT_FN_I1_CONST_VPTR_INT, BT_I1, BT_CONST_VOLATILE_PTR, - BT_INT) -DEF_FUNCTION_TYPE_2 (BT_FN_I2_CONST_VPTR_INT, BT_I2, BT_CONST_VOLATILE_PTR, - BT_INT) -DEF_FUNCTION_TYPE_2 (BT_FN_I4_CONST_VPTR_INT, BT_I4, BT_CONST_VOLATILE_PTR, - BT_INT) -DEF_FUNCTION_TYPE_2 (BT_FN_I8_CONST_VPTR_INT, BT_I8, BT_CONST_VOLATILE_PTR, - BT_INT) -DEF_FUNCTION_TYPE_2 (BT_FN_I16_CONST_VPTR_INT, BT_I16, BT_CONST_VOLATILE_PTR, - BT_INT) -DEF_FUNCTION_TYPE_2 (BT_FN_VOID_VPTR_INT, BT_VOID, BT_VOLATILE_PTR, BT_INT) -DEF_FUNCTION_TYPE_2 (BT_FN_BOOL_VPTR_INT, BT_BOOL, BT_VOLATILE_PTR, BT_INT) -DEF_FUNCTION_TYPE_2 (BT_FN_BOOL_SIZE_CONST_VPTR, BT_BOOL, BT_SIZE, - BT_CONST_VOLATILE_PTR) -DEF_FUNCTION_TYPE_2 (BT_FN_BOOL_INT_BOOL, BT_BOOL, BT_INT, BT_BOOL) -DEF_FUNCTION_TYPE_2 (BT_FN_VOID_UINT_UINT, BT_VOID, BT_UINT, BT_UINT) -DEF_FUNCTION_TYPE_2 (BT_FN_PTR_CONST_PTR_SIZE, BT_PTR, BT_CONST_PTR, BT_SIZE) -DEF_FUNCTION_TYPE_2 (BT_FN_PTR_CONST_PTR_CONST_PTR, BT_PTR, BT_CONST_PTR, BT_CONST_PTR) -DEF_FUNCTION_TYPE_2 (BT_FN_VOID_PTRPTR_CONST_PTR, BT_VOID, BT_PTR_PTR, BT_CONST_PTR) -DEF_FUNCTION_TYPE_2 (BT_FN_VOID_CONST_PTR_SIZE, BT_VOID, BT_CONST_PTR, BT_SIZE) -DEF_FUNCTION_TYPE_2 (BT_FN_VOID_PTR_BND, BT_VOID, BT_PTR, BT_BND) -DEF_FUNCTION_TYPE_2 (BT_FN_CONST_PTR_CONST_PTR_CONST_PTR, BT_CONST_PTR, BT_CONST_PTR, BT_CONST_PTR) -DEF_FUNCTION_TYPE_2 (BT_FN_BND_CONST_PTR_SIZE, BT_BND, BT_CONST_PTR, BT_SIZE) - -DEF_POINTER_TYPE (BT_PTR_FN_VOID_PTR_PTR, BT_FN_VOID_PTR_PTR) - -DEF_FUNCTION_TYPE_3 (BT_FN_STRING_STRING_CONST_STRING_SIZE, - BT_STRING, BT_STRING, BT_CONST_STRING, BT_SIZE) -DEF_FUNCTION_TYPE_3 (BT_FN_INT_CONST_STRING_CONST_STRING_SIZE, - BT_INT, BT_CONST_STRING, BT_CONST_STRING, BT_SIZE) -DEF_FUNCTION_TYPE_3 (BT_FN_PTR_PTR_CONST_PTR_SIZE, - BT_PTR, BT_PTR, BT_CONST_PTR, BT_SIZE) -DEF_FUNCTION_TYPE_3 (BT_FN_VOID_PTR_CONST_PTR_SIZE, - BT_VOID, BT_PTR, BT_CONST_PTR, BT_SIZE) -DEF_FUNCTION_TYPE_3 (BT_FN_INT_CONST_PTR_CONST_PTR_SIZE, - BT_INT, BT_CONST_PTR, BT_CONST_PTR, BT_SIZE) -DEF_FUNCTION_TYPE_3 (BT_FN_PTR_PTR_INT_SIZE, - BT_PTR, BT_PTR, BT_INT, BT_SIZE) -DEF_FUNCTION_TYPE_3 (BT_FN_VOID_PTR_INT_SIZE, - BT_VOID, BT_PTR, BT_INT, BT_SIZE) -DEF_FUNCTION_TYPE_3 (BT_FN_VOID_PTR_INT_INT, - BT_VOID, BT_PTR, BT_INT, BT_INT) -DEF_FUNCTION_TYPE_3 (BT_FN_VOID_CONST_PTR_PTR_SIZE, - BT_VOID, BT_CONST_PTR, BT_PTR, BT_SIZE) -DEF_FUNCTION_TYPE_3 (BT_FN_INT_STRING_CONST_STRING_VALIST_ARG, - BT_INT, BT_STRING, BT_CONST_STRING, BT_VALIST_ARG) -DEF_FUNCTION_TYPE_3 (BT_FN_INT_CONST_STRING_CONST_STRING_VALIST_ARG, - BT_INT, BT_CONST_STRING, BT_CONST_STRING, BT_VALIST_ARG) -DEF_FUNCTION_TYPE_3 (BT_FN_INT_FILEPTR_CONST_STRING_VALIST_ARG, - BT_INT, BT_FILEPTR, BT_CONST_STRING, BT_VALIST_ARG) -DEF_FUNCTION_TYPE_3 (BT_FN_INT_PTR_PTR_PTR, - BT_INT, BT_PTR, BT_PTR, BT_PTR) -DEF_FUNCTION_TYPE_3 (BT_FN_STRING_CONST_STRING_CONST_STRING_INT, - BT_STRING, BT_CONST_STRING, BT_CONST_STRING, BT_INT) -DEF_FUNCTION_TYPE_3 (BT_FN_FLOAT_FLOAT_FLOAT_FLOAT, - BT_FLOAT, BT_FLOAT, BT_FLOAT, BT_FLOAT) -DEF_FUNCTION_TYPE_3 (BT_FN_DOUBLE_DOUBLE_DOUBLE_DOUBLE, - BT_DOUBLE, BT_DOUBLE, BT_DOUBLE, BT_DOUBLE) -DEF_FUNCTION_TYPE_3 (BT_FN_LONGDOUBLE_LONGDOUBLE_LONGDOUBLE_LONGDOUBLE, - BT_LONGDOUBLE, BT_LONGDOUBLE, BT_LONGDOUBLE, BT_LONGDOUBLE) -DEF_FUNCTION_TYPE_3 (BT_FN_FLOAT_FLOAT_FLOAT_INTPTR, - BT_FLOAT, BT_FLOAT, BT_FLOAT, BT_INT_PTR) -DEF_FUNCTION_TYPE_3 (BT_FN_DOUBLE_DOUBLE_DOUBLE_INTPTR, - BT_DOUBLE, BT_DOUBLE, BT_DOUBLE, BT_INT_PTR) -DEF_FUNCTION_TYPE_3 (BT_FN_LONGDOUBLE_LONGDOUBLE_LONGDOUBLE_INTPTR, - BT_LONGDOUBLE, BT_LONGDOUBLE, BT_LONGDOUBLE, BT_INT_PTR) -DEF_FUNCTION_TYPE_3 (BT_FN_VOID_FLOAT_FLOATPTR_FLOATPTR, - BT_VOID, BT_FLOAT, BT_FLOAT_PTR, BT_FLOAT_PTR) -DEF_FUNCTION_TYPE_3 (BT_FN_VOID_DOUBLE_DOUBLEPTR_DOUBLEPTR, - BT_VOID, BT_DOUBLE, BT_DOUBLE_PTR, BT_DOUBLE_PTR) -DEF_FUNCTION_TYPE_3 (BT_FN_VOID_LONGDOUBLE_LONGDOUBLEPTR_LONGDOUBLEPTR, - BT_VOID, BT_LONGDOUBLE, BT_LONGDOUBLE_PTR, BT_LONGDOUBLE_PTR) -DEF_FUNCTION_TYPE_3 (BT_FN_VOID_PTR_PTR_PTR, BT_VOID, BT_PTR, BT_PTR, BT_PTR) -DEF_FUNCTION_TYPE_3 (BT_FN_INT_CONST_STRING_PTR_CONST_STRING_PTR_CONST_STRING, - BT_INT, BT_CONST_STRING, BT_PTR_CONST_STRING, BT_PTR_CONST_STRING) -DEF_FUNCTION_TYPE_3 (BT_FN_INT_INT_CONST_STRING_VALIST_ARG, - BT_INT, BT_INT, BT_CONST_STRING, BT_VALIST_ARG) -DEF_FUNCTION_TYPE_3 (BT_FN_BOOL_VPTR_I1_I1, BT_BOOL, BT_VOLATILE_PTR, - BT_I1, BT_I1) -DEF_FUNCTION_TYPE_3 (BT_FN_BOOL_VPTR_I2_I2, BT_BOOL, BT_VOLATILE_PTR, - BT_I2, BT_I2) -DEF_FUNCTION_TYPE_3 (BT_FN_BOOL_VPTR_I4_I4, BT_BOOL, BT_VOLATILE_PTR, - BT_I4, BT_I4) -DEF_FUNCTION_TYPE_3 (BT_FN_BOOL_VPTR_I8_I8, BT_BOOL, BT_VOLATILE_PTR, - BT_I8, BT_I8) -DEF_FUNCTION_TYPE_3 (BT_FN_BOOL_VPTR_I16_I16, BT_BOOL, BT_VOLATILE_PTR, - BT_I16, BT_I16) -DEF_FUNCTION_TYPE_3 (BT_FN_I1_VPTR_I1_I1, BT_I1, BT_VOLATILE_PTR, BT_I1, BT_I1) -DEF_FUNCTION_TYPE_3 (BT_FN_I2_VPTR_I2_I2, BT_I2, BT_VOLATILE_PTR, BT_I2, BT_I2) -DEF_FUNCTION_TYPE_3 (BT_FN_I4_VPTR_I4_I4, BT_I4, BT_VOLATILE_PTR, BT_I4, BT_I4) -DEF_FUNCTION_TYPE_3 (BT_FN_I8_VPTR_I8_I8, BT_I8, BT_VOLATILE_PTR, BT_I8, BT_I8) -DEF_FUNCTION_TYPE_3 (BT_FN_I16_VPTR_I16_I16, BT_I16, BT_VOLATILE_PTR, - BT_I16, BT_I16) -DEF_FUNCTION_TYPE_3 (BT_FN_PTR_CONST_PTR_INT_SIZE, BT_PTR, - BT_CONST_PTR, BT_INT, BT_SIZE) -DEF_FUNCTION_TYPE_3 (BT_FN_I1_VPTR_I1_INT, BT_I1, BT_VOLATILE_PTR, BT_I1, BT_INT) -DEF_FUNCTION_TYPE_3 (BT_FN_I2_VPTR_I2_INT, BT_I2, BT_VOLATILE_PTR, BT_I2, BT_INT) -DEF_FUNCTION_TYPE_3 (BT_FN_I4_VPTR_I4_INT, BT_I4, BT_VOLATILE_PTR, BT_I4, BT_INT) -DEF_FUNCTION_TYPE_3 (BT_FN_I8_VPTR_I8_INT, BT_I8, BT_VOLATILE_PTR, BT_I8, BT_INT) -DEF_FUNCTION_TYPE_3 (BT_FN_I16_VPTR_I16_INT, BT_I16, BT_VOLATILE_PTR, BT_I16, BT_INT) -DEF_FUNCTION_TYPE_3 (BT_FN_VOID_VPTR_I1_INT, BT_VOID, BT_VOLATILE_PTR, BT_I1, BT_INT) -DEF_FUNCTION_TYPE_3 (BT_FN_VOID_VPTR_I2_INT, BT_VOID, BT_VOLATILE_PTR, BT_I2, BT_INT) -DEF_FUNCTION_TYPE_3 (BT_FN_VOID_VPTR_I4_INT, BT_VOID, BT_VOLATILE_PTR, BT_I4, BT_INT) -DEF_FUNCTION_TYPE_3 (BT_FN_VOID_VPTR_I8_INT, BT_VOID, BT_VOLATILE_PTR, BT_I8, BT_INT) -DEF_FUNCTION_TYPE_3 (BT_FN_VOID_VPTR_I16_INT, BT_VOID, BT_VOLATILE_PTR, BT_I16, BT_INT) -DEF_FUNCTION_TYPE_3 (BT_FN_INT_PTRPTR_SIZE_SIZE, BT_INT, BT_PTR_PTR, BT_SIZE, BT_SIZE) -DEF_FUNCTION_TYPE_3 (BT_FN_PTR_CONST_PTR_CONST_PTR_SIZE, BT_PTR, BT_CONST_PTR, BT_CONST_PTR, BT_SIZE) -DEF_FUNCTION_TYPE_3 (BT_FN_VOID_CONST_PTR_BND_CONST_PTR, BT_VOID, BT_CONST_PTR, BT_BND, BT_CONST_PTR) -DEF_FUNCTION_TYPE_3 (BT_FN_BOOL_INT_INT_INTPTR, BT_BOOL, BT_INT, BT_INT, - BT_INT_PTR) -DEF_FUNCTION_TYPE_3 (BT_FN_BOOL_LONG_LONG_LONGPTR, BT_BOOL, BT_LONG, BT_LONG, - BT_PTR_LONG) -DEF_FUNCTION_TYPE_3 (BT_FN_BOOL_LONGLONG_LONGLONG_LONGLONGPTR, BT_BOOL, - BT_LONGLONG, BT_LONGLONG, BT_PTR_LONGLONG) -DEF_FUNCTION_TYPE_3 (BT_FN_BOOL_UINT_UINT_UINTPTR, BT_BOOL, BT_UINT, BT_UINT, - BT_PTR_UINT) -DEF_FUNCTION_TYPE_3 (BT_FN_BOOL_ULONG_ULONG_ULONGPTR, BT_BOOL, BT_ULONG, - BT_ULONG, BT_PTR_ULONG) -DEF_FUNCTION_TYPE_3 (BT_FN_BOOL_ULONGLONG_ULONGLONG_ULONGLONGPTR, BT_BOOL, - BT_ULONGLONG, BT_ULONGLONG, BT_PTR_ULONGLONG) - -DEF_FUNCTION_TYPE_4 (BT_FN_SIZE_CONST_PTR_SIZE_SIZE_FILEPTR, - BT_SIZE, BT_CONST_PTR, BT_SIZE, BT_SIZE, BT_FILEPTR) -DEF_FUNCTION_TYPE_4 (BT_FN_INT_STRING_SIZE_CONST_STRING_VALIST_ARG, - BT_INT, BT_STRING, BT_SIZE, BT_CONST_STRING, BT_VALIST_ARG) -DEF_FUNCTION_TYPE_4 (BT_FN_SIZE_STRING_SIZE_CONST_STRING_CONST_PTR, - BT_SIZE, BT_STRING, BT_SIZE, BT_CONST_STRING, BT_CONST_PTR) -DEF_FUNCTION_TYPE_4 (BT_FN_PTR_PTR_CONST_PTR_SIZE_SIZE, - BT_PTR, BT_PTR, BT_CONST_PTR, BT_SIZE, BT_SIZE) -DEF_FUNCTION_TYPE_4 (BT_FN_PTR_PTR_INT_SIZE_SIZE, - BT_PTR, BT_PTR, BT_INT, BT_SIZE, BT_SIZE) -DEF_FUNCTION_TYPE_4 (BT_FN_STRING_STRING_CONST_STRING_SIZE_SIZE, - BT_STRING, BT_STRING, BT_CONST_STRING, BT_SIZE, BT_SIZE) -DEF_FUNCTION_TYPE_4 (BT_FN_INT_FILEPTR_INT_CONST_STRING_VALIST_ARG, - BT_INT, BT_FILEPTR, BT_INT, BT_CONST_STRING, BT_VALIST_ARG) -DEF_FUNCTION_TYPE_4 (BT_FN_VOID_OMPFN_PTR_UINT_UINT, - BT_VOID, BT_PTR_FN_VOID_PTR, BT_PTR, BT_UINT, BT_UINT) -DEF_FUNCTION_TYPE_4 (BT_FN_VOID_PTR_WORD_WORD_PTR, - BT_VOID, BT_PTR, BT_WORD, BT_WORD, BT_PTR) -DEF_FUNCTION_TYPE_4 (BT_FN_VOID_SIZE_VPTR_PTR_INT, BT_VOID, BT_SIZE, - BT_VOLATILE_PTR, BT_PTR, BT_INT) -DEF_FUNCTION_TYPE_4 (BT_FN_VOID_SIZE_CONST_VPTR_PTR_INT, BT_VOID, BT_SIZE, - BT_CONST_VOLATILE_PTR, BT_PTR, BT_INT) - -DEF_FUNCTION_TYPE_5 (BT_FN_INT_STRING_INT_SIZE_CONST_STRING_VALIST_ARG, - BT_INT, BT_STRING, BT_INT, BT_SIZE, BT_CONST_STRING, - BT_VALIST_ARG) -DEF_FUNCTION_TYPE_5 (BT_FN_BOOL_LONG_LONG_LONG_LONGPTR_LONGPTR, - BT_BOOL, BT_LONG, BT_LONG, BT_LONG, - BT_PTR_LONG, BT_PTR_LONG) -DEF_FUNCTION_TYPE_5 (BT_FN_VOID_SIZE_VPTR_PTR_PTR_INT, BT_VOID, BT_SIZE, - BT_VOLATILE_PTR, BT_PTR, BT_PTR, BT_INT) -DEF_FUNCTION_TYPE_5 (BT_FN_BOOL_VPTR_PTR_I1_INT_INT, - BT_BOOL, BT_VOLATILE_PTR, BT_PTR, BT_I1, BT_INT, BT_INT) -DEF_FUNCTION_TYPE_5 (BT_FN_BOOL_VPTR_PTR_I2_INT_INT, - BT_BOOL, BT_VOLATILE_PTR, BT_PTR, BT_I2, BT_INT, BT_INT) -DEF_FUNCTION_TYPE_5 (BT_FN_BOOL_VPTR_PTR_I4_INT_INT, - BT_BOOL, BT_VOLATILE_PTR, BT_PTR, BT_I4, BT_INT, BT_INT) -DEF_FUNCTION_TYPE_5 (BT_FN_BOOL_VPTR_PTR_I8_INT_INT, - BT_BOOL, BT_VOLATILE_PTR, BT_PTR, BT_I8, BT_INT, BT_INT) -DEF_FUNCTION_TYPE_5 (BT_FN_BOOL_VPTR_PTR_I16_INT_INT, - BT_BOOL, BT_VOLATILE_PTR, BT_PTR, BT_I16, BT_INT, BT_INT) -DEF_FUNCTION_TYPE_5 (BT_FN_VOID_INT_SIZE_PTR_PTR_PTR, - BT_VOID, BT_INT, BT_SIZE, BT_PTR, BT_PTR, BT_PTR) -DEF_FUNCTION_TYPE_5 (BT_FN_VOID_OMPFN_PTR_UINT_UINT_UINT, - BT_VOID, BT_PTR_FN_VOID_PTR, BT_PTR, BT_UINT, BT_UINT, - BT_UINT) - -DEF_FUNCTION_TYPE_6 (BT_FN_INT_STRING_SIZE_INT_SIZE_CONST_STRING_VALIST_ARG, - BT_INT, BT_STRING, BT_SIZE, BT_INT, BT_SIZE, - BT_CONST_STRING, BT_VALIST_ARG) -DEF_FUNCTION_TYPE_6 (BT_FN_BOOL_LONG_LONG_LONG_LONG_LONGPTR_LONGPTR, - BT_BOOL, BT_LONG, BT_LONG, BT_LONG, BT_LONG, - BT_PTR_LONG, BT_PTR_LONG) -DEF_FUNCTION_TYPE_6 (BT_FN_BOOL_BOOL_ULL_ULL_ULL_ULLPTR_ULLPTR, - BT_BOOL, BT_BOOL, BT_ULONGLONG, BT_ULONGLONG, - BT_ULONGLONG, BT_PTR_ULONGLONG, BT_PTR_ULONGLONG) -DEF_FUNCTION_TYPE_6 (BT_FN_BOOL_VPTR_PTR_I1_BOOL_INT_INT, - BT_BOOL, BT_VOLATILE_PTR, BT_PTR, BT_I1, BT_BOOL, BT_INT, - BT_INT) -DEF_FUNCTION_TYPE_6 (BT_FN_BOOL_VPTR_PTR_I2_BOOL_INT_INT, - BT_BOOL, BT_VOLATILE_PTR, BT_PTR, BT_I2, BT_BOOL, BT_INT, - BT_INT) -DEF_FUNCTION_TYPE_6 (BT_FN_BOOL_VPTR_PTR_I4_BOOL_INT_INT, - BT_BOOL, BT_VOLATILE_PTR, BT_PTR, BT_I4, BT_BOOL, BT_INT, - BT_INT) -DEF_FUNCTION_TYPE_6 (BT_FN_BOOL_VPTR_PTR_I8_BOOL_INT_INT, - BT_BOOL, BT_VOLATILE_PTR, BT_PTR, BT_I8, BT_BOOL, BT_INT, - BT_INT) -DEF_FUNCTION_TYPE_6 (BT_FN_BOOL_VPTR_PTR_I16_BOOL_INT_INT, - BT_BOOL, BT_VOLATILE_PTR, BT_PTR, BT_I16, BT_BOOL, BT_INT, - BT_INT) -DEF_FUNCTION_TYPE_6 (BT_FN_BOOL_SIZE_VPTR_PTR_PTR_INT_INT, BT_BOOL, BT_SIZE, - BT_VOLATILE_PTR, BT_PTR, BT_PTR, BT_INT, BT_INT) -DEF_FUNCTION_TYPE_6 (BT_FN_VOID_INT_PTR_SIZE_PTR_PTR_PTR, - BT_VOID, BT_INT, BT_PTR, BT_SIZE, BT_PTR, BT_PTR, BT_PTR) - -DEF_FUNCTION_TYPE_7 (BT_FN_VOID_OMPFN_PTR_UINT_LONG_LONG_LONG_UINT, - BT_VOID, BT_PTR_FN_VOID_PTR, BT_PTR, BT_UINT, - BT_LONG, BT_LONG, BT_LONG, BT_UINT) -DEF_FUNCTION_TYPE_7 (BT_FN_BOOL_BOOL_ULL_ULL_ULL_ULL_ULLPTR_ULLPTR, - BT_BOOL, BT_BOOL, BT_ULONGLONG, BT_ULONGLONG, - BT_ULONGLONG, BT_ULONGLONG, - BT_PTR_ULONGLONG, BT_PTR_ULONGLONG) -DEF_FUNCTION_TYPE_7 (BT_FN_VOID_INT_OMPFN_PTR_SIZE_PTR_PTR_PTR, - BT_VOID, BT_INT, BT_PTR_FN_VOID_PTR, BT_PTR, BT_SIZE, - BT_PTR, BT_PTR, BT_PTR) - -DEF_FUNCTION_TYPE_8 (BT_FN_VOID_OMPFN_PTR_UINT_LONG_LONG_LONG_LONG_UINT, - BT_VOID, BT_PTR_FN_VOID_PTR, BT_PTR, BT_UINT, - BT_LONG, BT_LONG, BT_LONG, BT_LONG, BT_UINT) -DEF_FUNCTION_TYPE_8 (BT_FN_VOID_OMPFN_PTR_OMPCPYFN_LONG_LONG_BOOL_UINT_PTR, - BT_VOID, BT_PTR_FN_VOID_PTR, BT_PTR, - BT_PTR_FN_VOID_PTR_PTR, BT_LONG, BT_LONG, - BT_BOOL, BT_UINT, BT_PTR) - -DEF_FUNCTION_TYPE_VAR_0 (BT_FN_VOID_VAR, BT_VOID) -DEF_FUNCTION_TYPE_VAR_0 (BT_FN_INT_VAR, BT_INT) -DEF_FUNCTION_TYPE_VAR_0 (BT_FN_PTR_VAR, BT_PTR) -DEF_FUNCTION_TYPE_VAR_0 (BT_FN_BOOL_VAR, BT_BOOL) - -DEF_FUNCTION_TYPE_VAR_1 (BT_FN_VOID_VALIST_REF_VAR, - BT_VOID, BT_VALIST_REF) -DEF_FUNCTION_TYPE_VAR_1 (BT_FN_VOID_CONST_PTR_VAR, - BT_VOID, BT_CONST_PTR) -DEF_FUNCTION_TYPE_VAR_1 (BT_FN_INT_CONST_STRING_VAR, - BT_INT, BT_CONST_STRING) -DEF_FUNCTION_TYPE_VAR_1 (BT_FN_UINT32_UINT32_VAR, - BT_UINT32, BT_UINT32) - -DEF_FUNCTION_TYPE_VAR_2 (BT_FN_INT_FILEPTR_CONST_STRING_VAR, - BT_INT, BT_FILEPTR, BT_CONST_STRING) -DEF_FUNCTION_TYPE_VAR_2 (BT_FN_INT_STRING_CONST_STRING_VAR, - BT_INT, BT_STRING, BT_CONST_STRING) -DEF_FUNCTION_TYPE_VAR_2 (BT_FN_INT_CONST_STRING_CONST_STRING_VAR, - BT_INT, BT_CONST_STRING, BT_CONST_STRING) -DEF_FUNCTION_TYPE_VAR_2 (BT_FN_INT_INT_CONST_STRING_VAR, - BT_INT, BT_INT, BT_CONST_STRING) -DEF_FUNCTION_TYPE_VAR_2 (BT_FN_PTR_CONST_PTR_SIZE_VAR, BT_PTR, - BT_CONST_PTR, BT_SIZE) -DEF_FUNCTION_TYPE_VAR_2 (BT_FN_VOID_INT_INT_VAR, BT_VOID, - BT_INT, BT_INT) - -DEF_FUNCTION_TYPE_VAR_3 (BT_FN_INT_STRING_SIZE_CONST_STRING_VAR, - BT_INT, BT_STRING, BT_SIZE, BT_CONST_STRING) -DEF_FUNCTION_TYPE_VAR_3 (BT_FN_SSIZE_STRING_SIZE_CONST_STRING_VAR, - BT_SSIZE, BT_STRING, BT_SIZE, BT_CONST_STRING) -DEF_FUNCTION_TYPE_VAR_3 (BT_FN_INT_FILEPTR_INT_CONST_STRING_VAR, - BT_INT, BT_FILEPTR, BT_INT, BT_CONST_STRING) - -DEF_FUNCTION_TYPE_VAR_4 (BT_FN_INT_STRING_INT_SIZE_CONST_STRING_VAR, - BT_INT, BT_STRING, BT_INT, BT_SIZE, BT_CONST_STRING) - -DEF_FUNCTION_TYPE_VAR_5 (BT_FN_INT_STRING_SIZE_INT_SIZE_CONST_STRING_VAR, - BT_INT, BT_STRING, BT_SIZE, BT_INT, BT_SIZE, - BT_CONST_STRING) - -DEF_FUNCTION_TYPE_VAR_5 (BT_FN_INT_INT_INT_INT_INT_INT_VAR, - BT_INT, BT_INT, BT_INT, BT_INT, BT_INT, BT_INT) - -DEF_FUNCTION_TYPE_VAR_7 (BT_FN_VOID_INT_SIZE_PTR_PTR_PTR_INT_INT_VAR, - BT_VOID, BT_INT, BT_SIZE, BT_PTR, BT_PTR, - BT_PTR, BT_INT, BT_INT) - -DEF_FUNCTION_TYPE_VAR_11 (BT_FN_VOID_INT_OMPFN_SIZE_PTR_PTR_PTR_INT_INT_INT_INT_INT_VAR, - BT_VOID, BT_INT, BT_PTR_FN_VOID_PTR, BT_SIZE, - BT_PTR, BT_PTR, BT_PTR, BT_INT, BT_INT, BT_INT, - BT_INT, BT_INT) - -DEF_POINTER_TYPE (BT_PTR_FN_VOID_VAR, BT_FN_VOID_VAR) -DEF_FUNCTION_TYPE_3 (BT_FN_PTR_PTR_FN_VOID_VAR_PTR_SIZE, - BT_PTR, BT_PTR_FN_VOID_VAR, BT_PTR, BT_SIZE) - - -DEF_FUNCTION_TYPE_1 (BT_FN_I1_VPTR, BT_I1, BT_VOLATILE_PTR) -DEF_FUNCTION_TYPE_1 (BT_FN_I2_VPTR, BT_I2, BT_VOLATILE_PTR) -DEF_FUNCTION_TYPE_1 (BT_FN_I4_VPTR, BT_I4, BT_VOLATILE_PTR) -DEF_FUNCTION_TYPE_1 (BT_FN_I8_VPTR, BT_I8, BT_VOLATILE_PTR) -DEF_FUNCTION_TYPE_1 (BT_FN_FLOAT_VPTR, BT_FLOAT, BT_VOLATILE_PTR) -DEF_FUNCTION_TYPE_1 (BT_FN_DOUBLE_CONST_DOUBLE_PTR, BT_DOUBLE, BT_DOUBLE_PTR) -DEF_FUNCTION_TYPE_1 (BT_FN_LDOUBLE_VPTR, BT_LONGDOUBLE, BT_VOLATILE_PTR) - -DEF_FUNCTION_TYPE_2 (BT_FN_VOID_VPTR_I1, BT_VOID, BT_VOLATILE_PTR, BT_I1) -DEF_FUNCTION_TYPE_2 (BT_FN_VOID_VPTR_I2, BT_VOID, BT_VOLATILE_PTR, BT_I2) -DEF_FUNCTION_TYPE_2 (BT_FN_VOID_VPTR_I4, BT_VOID, BT_VOLATILE_PTR, BT_I4) -DEF_FUNCTION_TYPE_2 (BT_FN_VOID_VPTR_I8, BT_VOID, BT_VOLATILE_PTR, BT_I8) -DEF_FUNCTION_TYPE_2 (BT_FN_VOID_VPTR_FLOAT, BT_VOID, BT_VOLATILE_PTR, BT_FLOAT) -DEF_FUNCTION_TYPE_2 (BT_FN_VOID_VPTR_DOUBLE, BT_VOID, - BT_VOLATILE_PTR, BT_DOUBLE) -DEF_FUNCTION_TYPE_2 (BT_FN_VOID_VPTR_LDOUBLE, BT_VOID, - BT_VOLATILE_PTR, BT_LONGDOUBLE) -DEF_FUNCTION_TYPE_2 (BT_FN_VOID_VPTR_SIZE, BT_VOID, - BT_VOLATILE_PTR, BT_SIZE) diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/builtins.def b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/builtins.def deleted file mode 100644 index 55ce9f6..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/builtins.def +++ /dev/null @@ -1,944 +0,0 @@ -/* This file contains the definitions and documentation for the - builtins used in the GNU compiler. - Copyright (C) 2000-2015 Free Software Foundation, Inc. - -This file is part of GCC. - -GCC is free software; you can redistribute it and/or modify it under -the terms of the GNU General Public License as published by the Free -Software Foundation; either version 3, or (at your option) any later -version. - -GCC is distributed in the hope that it will be useful, but WITHOUT ANY -WARRANTY; without even the implied warranty of MERCHANTABILITY or -FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -for more details. - -You should have received a copy of the GNU General Public License -along with GCC; see the file COPYING3. If not see -. */ - -/* Before including this file, you should define a macro: - - DEF_BUILTIN (ENUM, NAME, CLASS, TYPE, LIBTYPE, BOTH_P, - FALLBACK_P, NONANSI_P, ATTRS, IMPLICIT, COND) - - This macro will be called once for each builtin function. The - ENUM will be of type `enum built_in_function', and will indicate - which builtin function is being processed. The NAME of the builtin - function (which will always start with `__builtin_') is a string - literal. The CLASS is of type `enum built_in_class' and indicates - what kind of builtin is being processed. - - Some builtins are actually two separate functions. For example, - for `strcmp' there are two builtin functions; `__builtin_strcmp' - and `strcmp' itself. Both behave identically. Other builtins - define only the `__builtin' variant. If BOTH_P is TRUE, then this - builtin has both variants; otherwise, it is has only the first - variant. - - TYPE indicates the type of the function. The symbols correspond to - enumerals from builtin-types.def. If BOTH_P is true, then LIBTYPE - is the type of the non-`__builtin_' variant. Otherwise, LIBTYPE - should be ignored. - - If FALLBACK_P is true then, if for some reason, the compiler cannot - expand the builtin function directly, it will call the - corresponding library function (which does not have the - `__builtin_' prefix. - - If NONANSI_P is true, then the non-`__builtin_' variant is not an - ANSI/ISO library function, and so we should pretend it does not - exist when compiling in ANSI conformant mode. - - ATTRs is an attribute list as defined in builtin-attrs.def that - describes the attributes of this builtin function. - - IMPLICIT specifies condition when the builtin can be produced by - compiler. For instance C90 reserves floorf function, but does not - define it's meaning. When user uses floorf we may assume that the - floorf has the meaning we expect, but we can't produce floorf by - simplifying floor((double)float) since the runtime need not implement - it. - - The builtins is registered only if COND is true. */ - -/* A macro for builtins where the - BUILT_IN_*_CHKP = BUILT_IN_* + BEGIN_CHKP_BUILTINS + 1 - enums should be defined too. */ -#ifndef DEF_BUILTIN_CHKP -#define DEF_BUILTIN_CHKP(ENUM, NAME, CLASS, TYPE, LIBTYPE, BOTH_P, \ - FALLBACK_P, NONANSI_P, ATTRS, IMPLICIT, COND) \ - DEF_BUILTIN(ENUM, NAME, CLASS, TYPE, LIBTYPE, BOTH_P, FALLBACK_P, \ - NONANSI_P, ATTRS, IMPLICIT, COND) -#endif - -/* A GCC builtin (like __builtin_saveregs) is provided by the - compiler, but does not correspond to a function in the standard - library. */ -#undef DEF_GCC_BUILTIN -#define DEF_GCC_BUILTIN(ENUM, NAME, TYPE, ATTRS) \ - DEF_BUILTIN (ENUM, "__builtin_" NAME, BUILT_IN_NORMAL, TYPE, BT_LAST, \ - false, false, false, ATTRS, true, true) - -/* Like DEF_GCC_BUILTIN, except we don't prepend "__builtin_". */ -#undef DEF_SYNC_BUILTIN -#define DEF_SYNC_BUILTIN(ENUM, NAME, TYPE, ATTRS) \ - DEF_BUILTIN (ENUM, NAME, BUILT_IN_NORMAL, TYPE, BT_LAST, \ - false, false, false, ATTRS, true, true) - -/* A library builtin (like __builtin_strchr) is a builtin equivalent - of an ANSI/ISO standard library function. In addition to the - `__builtin' version, we will create an ordinary version (e.g, - `strchr') as well. If we cannot compute the answer using the - builtin function, we will fall back to the standard library - version. */ -#undef DEF_LIB_BUILTIN -#define DEF_LIB_BUILTIN(ENUM, NAME, TYPE, ATTRS) \ - DEF_BUILTIN (ENUM, "__builtin_" NAME, BUILT_IN_NORMAL, TYPE, TYPE, \ - true, true, false, ATTRS, true, true) -#undef DEF_LIB_BUILTIN_CHKP -#define DEF_LIB_BUILTIN_CHKP(ENUM, NAME, TYPE, ATTRS) \ - DEF_BUILTIN_CHKP (ENUM, "__builtin_" NAME, BUILT_IN_NORMAL, TYPE, \ - TYPE, true, true, false, ATTRS, true, true) - -/* Like DEF_LIB_BUILTIN, except that the function is not one that is - specified by ANSI/ISO C. So, when we're being fully conformant we - ignore the version of these builtins that does not begin with - __builtin. */ -#undef DEF_EXT_LIB_BUILTIN -#define DEF_EXT_LIB_BUILTIN(ENUM, NAME, TYPE, ATTRS) \ - DEF_BUILTIN (ENUM, "__builtin_" NAME, BUILT_IN_NORMAL, TYPE, TYPE, \ - true, true, true, ATTRS, false, true) -#undef DEF_EXT_LIB_BUILTIN_CHKP -#define DEF_EXT_LIB_BUILTIN_CHKP(ENUM, NAME, TYPE, ATTRS) \ - DEF_BUILTIN_CHKP (ENUM, "__builtin_" NAME, BUILT_IN_NORMAL, TYPE, \ - TYPE, true, true, true, ATTRS, false, true) - -/* Like DEF_LIB_BUILTIN, except that the function is only a part of - the standard in C94 or above. */ -#undef DEF_C94_BUILTIN -#define DEF_C94_BUILTIN(ENUM, NAME, TYPE, ATTRS) \ - DEF_BUILTIN (ENUM, "__builtin_" NAME, BUILT_IN_NORMAL, TYPE, TYPE, \ - true, true, !flag_isoc94, ATTRS, targetm.libc_has_function (function_c94), true) - -/* Like DEF_LIB_BUILTIN, except that the function is only a part of - the standard in C99 or above. */ -#undef DEF_C99_BUILTIN -#define DEF_C99_BUILTIN(ENUM, NAME, TYPE, ATTRS) \ - DEF_BUILTIN (ENUM, "__builtin_" NAME, BUILT_IN_NORMAL, TYPE, TYPE, \ - true, true, !flag_isoc99, ATTRS, targetm.libc_has_function (function_c99_misc), true) - -/* Like DEF_LIB_BUILTIN, except that the function is only a part of - the standard in C11 or above. */ -#undef DEF_C11_BUILTIN -#define DEF_C11_BUILTIN(ENUM, NAME, TYPE, ATTRS) \ - DEF_BUILTIN (ENUM, "__builtin_" NAME, BUILT_IN_NORMAL, TYPE, TYPE, \ - true, true, !flag_isoc11, ATTRS, targetm.libc_has_function (function_c11_misc), true) - -/* Like DEF_C99_BUILTIN, but for complex math functions. */ -#undef DEF_C99_COMPL_BUILTIN -#define DEF_C99_COMPL_BUILTIN(ENUM, NAME, TYPE, ATTRS) \ - DEF_BUILTIN (ENUM, "__builtin_" NAME, BUILT_IN_NORMAL, TYPE, TYPE, \ - true, true, !flag_isoc99, ATTRS, targetm.libc_has_function (function_c99_math_complex), true) - -/* Builtin that is specified by C99 and C90 reserve the name for future use. - We can still recognize the builtin in C90 mode but we can't produce it - implicitly. */ -#undef DEF_C99_C90RES_BUILTIN -#define DEF_C99_C90RES_BUILTIN(ENUM, NAME, TYPE, ATTRS) \ - DEF_BUILTIN (ENUM, "__builtin_" NAME, BUILT_IN_NORMAL, TYPE, TYPE, \ - true, true, !flag_isoc99, ATTRS, targetm.libc_has_function (function_c99_misc), true) - -/* Builtin that C99 reserve the name for future use. We can still recognize - the builtin in C99 mode but we can't produce it implicitly. */ -#undef DEF_EXT_C99RES_BUILTIN -#define DEF_EXT_C99RES_BUILTIN(ENUM, NAME, TYPE, ATTRS) \ - DEF_BUILTIN (ENUM, "__builtin_" NAME, BUILT_IN_NORMAL, TYPE, TYPE, \ - true, true, true, ATTRS, false, true) - -/* Allocate the enum and the name for a builtin, but do not actually - define it here at all. */ -#undef DEF_BUILTIN_STUB -#define DEF_BUILTIN_STUB(ENUM, NAME) \ - DEF_BUILTIN (ENUM, NAME, BUILT_IN_NORMAL, BT_LAST, BT_LAST, false, false, \ - false, ATTR_LAST, false, false) - -/* Builtin used by the implementation of OpenACC and OpenMP. Few of these are - actually implemented in the compiler; most are in libgomp. */ -/* These builtins also need to be enabled in offloading compilers invoked from - mkoffload; for that purpose, we're checking the -foffload-abi flag here. */ -#undef DEF_GOACC_BUILTIN -#define DEF_GOACC_BUILTIN(ENUM, NAME, TYPE, ATTRS) \ - DEF_BUILTIN (ENUM, "__builtin_" NAME, BUILT_IN_NORMAL, TYPE, TYPE, \ - false, true, true, ATTRS, false, \ - (flag_openacc \ - || flag_offload_abi != OFFLOAD_ABI_UNSET)) -#undef DEF_GOACC_BUILTIN_COMPILER -#define DEF_GOACC_BUILTIN_COMPILER(ENUM, NAME, TYPE, ATTRS) \ - DEF_BUILTIN (ENUM, "__builtin_" NAME, BUILT_IN_NORMAL, TYPE, TYPE, \ - flag_openacc, true, true, ATTRS, false, true) -#undef DEF_GOMP_BUILTIN -#define DEF_GOMP_BUILTIN(ENUM, NAME, TYPE, ATTRS) \ - DEF_BUILTIN (ENUM, "__builtin_" NAME, BUILT_IN_NORMAL, TYPE, TYPE, \ - false, true, true, ATTRS, false, \ - (flag_openmp || flag_tree_parallelize_loops \ - || flag_offload_abi != OFFLOAD_ABI_UNSET)) - -/* Builtin used by implementation of Cilk Plus. Most of these are decomposed - by the compiler but a few are implemented in libcilkrts. */ -#undef DEF_CILK_BUILTIN_STUB -#define DEF_CILK_BUILTIN_STUB(ENUM, NAME) \ - DEF_BUILTIN (ENUM, NAME, BUILT_IN_NORMAL, BT_LAST, BT_LAST, false, false, \ - false, ATTR_LAST, false, false) - -/* Builtin used by the implementation of GNU TM. These - functions are mapped to the actual implementation of the STM library. */ -#undef DEF_TM_BUILTIN -#define DEF_TM_BUILTIN(ENUM, NAME, TYPE, ATTRS) \ - DEF_BUILTIN (ENUM, "__builtin_" NAME, BUILT_IN_NORMAL, TYPE, TYPE, \ - true, true, true, ATTRS, false, flag_tm) - -/* Builtin used by the implementation of libsanitizer. These - functions are mapped to the actual implementation of the - libtsan library. */ -#undef DEF_SANITIZER_BUILTIN -#define DEF_SANITIZER_BUILTIN(ENUM, NAME, TYPE, ATTRS) \ - DEF_BUILTIN (ENUM, "__builtin_" NAME, BUILT_IN_NORMAL, TYPE, TYPE, \ - true, true, true, ATTRS, true, \ - (flag_sanitize & (SANITIZE_ADDRESS | SANITIZE_THREAD \ - | SANITIZE_UNDEFINED | SANITIZE_NONDEFAULT))) - -#undef DEF_CILKPLUS_BUILTIN -#define DEF_CILKPLUS_BUILTIN(ENUM, NAME, TYPE, ATTRS) \ - DEF_BUILTIN (ENUM, NAME, BUILT_IN_NORMAL, BT_FN_INT_VAR, BT_LAST, \ - false, false, false, ATTRS, false, flag_cilkplus) - -/* Builtin used by the implementation of Pointer Bounds Checker. */ -#undef DEF_CHKP_BUILTIN -#define DEF_CHKP_BUILTIN(ENUM, NAME, TYPE, ATTRS) \ - DEF_BUILTIN_CHKP (ENUM, "__builtin_" NAME, BUILT_IN_NORMAL, TYPE, \ - TYPE, true, true, false, ATTRS, true, true) - -/* Define an attribute list for math functions that are normally - "impure" because some of them may write into global memory for - `errno'. If !flag_errno_math they are instead "const". */ -#undef ATTR_MATHFN_ERRNO -#define ATTR_MATHFN_ERRNO (flag_errno_math ? \ - ATTR_NOTHROW_LEAF_LIST : ATTR_CONST_NOTHROW_LEAF_LIST) - -/* Define an attribute list for math functions that are normally - "const" but if flag_rounding_math is set they are instead "pure". - This distinction accounts for the fact that some math functions - check the rounding mode which is akin to examining global - memory. */ -#undef ATTR_MATHFN_FPROUNDING -#define ATTR_MATHFN_FPROUNDING (flag_rounding_math ? \ - ATTR_PURE_NOTHROW_LEAF_LIST : ATTR_CONST_NOTHROW_LEAF_LIST) - -/* Define an attribute list for math functions that are normally - "impure" because some of them may write into global memory for - `errno'. If !flag_errno_math, we can possibly use "pure" or - "const" depending on whether we care about FP rounding. */ -#undef ATTR_MATHFN_FPROUNDING_ERRNO -#define ATTR_MATHFN_FPROUNDING_ERRNO (flag_errno_math ? \ - ATTR_NOTHROW_LEAF_LIST : ATTR_MATHFN_FPROUNDING) - -/* Define an attribute list for math functions that need to mind FP - rounding, but because they store into memory they are never "const" - or "pure". Use of this macro is mainly for documentation and - maintenance purposes. */ -#undef ATTR_MATHFN_FPROUNDING_STORE -#define ATTR_MATHFN_FPROUNDING_STORE ATTR_NOTHROW_LEAF_LIST - -/* Define an attribute list for leaf functions that do not throw - exceptions normally, but may throw exceptions when using - -fnon-call-exceptions. */ -#define ATTR_NOTHROWCALL_LEAF_LIST (flag_non_call_exceptions ? \ - ATTR_LEAF_LIST : ATTR_NOTHROW_LEAF_LIST) - -/* Make sure 0 is not a legitimate builtin. */ -DEF_BUILTIN_STUB(BUILT_IN_NONE, (const char *)0) - -/* Category: math builtins. */ -DEF_LIB_BUILTIN (BUILT_IN_ACOS, "acos", BT_FN_DOUBLE_DOUBLE, ATTR_MATHFN_FPROUNDING_ERRNO) -DEF_C99_C90RES_BUILTIN (BUILT_IN_ACOSF, "acosf", BT_FN_FLOAT_FLOAT, ATTR_MATHFN_FPROUNDING_ERRNO) -DEF_C99_BUILTIN (BUILT_IN_ACOSH, "acosh", BT_FN_DOUBLE_DOUBLE, ATTR_MATHFN_FPROUNDING_ERRNO) -DEF_C99_BUILTIN (BUILT_IN_ACOSHF, "acoshf", BT_FN_FLOAT_FLOAT, ATTR_MATHFN_FPROUNDING_ERRNO) -DEF_C99_BUILTIN (BUILT_IN_ACOSHL, "acoshl", BT_FN_LONGDOUBLE_LONGDOUBLE, ATTR_MATHFN_FPROUNDING_ERRNO) -DEF_C99_C90RES_BUILTIN (BUILT_IN_ACOSL, "acosl", BT_FN_LONGDOUBLE_LONGDOUBLE, ATTR_MATHFN_FPROUNDING_ERRNO) -DEF_C11_BUILTIN (BUILT_IN_ALIGNED_ALLOC, "aligned_alloc", BT_FN_PTR_SIZE_SIZE, ATTR_MALLOC_NOTHROW_LIST) -DEF_LIB_BUILTIN (BUILT_IN_ASIN, "asin", BT_FN_DOUBLE_DOUBLE, ATTR_MATHFN_FPROUNDING_ERRNO) -DEF_C99_C90RES_BUILTIN (BUILT_IN_ASINF, "asinf", BT_FN_FLOAT_FLOAT, ATTR_MATHFN_FPROUNDING_ERRNO) -DEF_C99_BUILTIN (BUILT_IN_ASINH, "asinh", BT_FN_DOUBLE_DOUBLE, ATTR_MATHFN_FPROUNDING) -DEF_C99_BUILTIN (BUILT_IN_ASINHF, "asinhf", BT_FN_FLOAT_FLOAT, ATTR_MATHFN_FPROUNDING) -DEF_C99_BUILTIN (BUILT_IN_ASINHL, "asinhl", BT_FN_LONGDOUBLE_LONGDOUBLE, ATTR_MATHFN_FPROUNDING) -DEF_C99_C90RES_BUILTIN (BUILT_IN_ASINL, "asinl", BT_FN_LONGDOUBLE_LONGDOUBLE, ATTR_MATHFN_FPROUNDING_ERRNO) -DEF_LIB_BUILTIN (BUILT_IN_ATAN, "atan", BT_FN_DOUBLE_DOUBLE, ATTR_MATHFN_FPROUNDING) -DEF_LIB_BUILTIN (BUILT_IN_ATAN2, "atan2", BT_FN_DOUBLE_DOUBLE_DOUBLE, ATTR_MATHFN_FPROUNDING_ERRNO) -DEF_C99_C90RES_BUILTIN (BUILT_IN_ATAN2F, "atan2f", BT_FN_FLOAT_FLOAT_FLOAT, ATTR_MATHFN_FPROUNDING_ERRNO) -DEF_C99_C90RES_BUILTIN (BUILT_IN_ATAN2L, "atan2l", BT_FN_LONGDOUBLE_LONGDOUBLE_LONGDOUBLE, ATTR_MATHFN_FPROUNDING_ERRNO) -DEF_C99_C90RES_BUILTIN (BUILT_IN_ATANF, "atanf", BT_FN_FLOAT_FLOAT, ATTR_MATHFN_FPROUNDING) -DEF_C99_BUILTIN (BUILT_IN_ATANH, "atanh", BT_FN_DOUBLE_DOUBLE, ATTR_MATHFN_FPROUNDING_ERRNO) -DEF_C99_BUILTIN (BUILT_IN_ATANHF, "atanhf", BT_FN_FLOAT_FLOAT, ATTR_MATHFN_FPROUNDING_ERRNO) -DEF_C99_BUILTIN (BUILT_IN_ATANHL, "atanhl", BT_FN_LONGDOUBLE_LONGDOUBLE, ATTR_MATHFN_FPROUNDING_ERRNO) -DEF_C99_C90RES_BUILTIN (BUILT_IN_ATANL, "atanl", BT_FN_LONGDOUBLE_LONGDOUBLE, ATTR_MATHFN_FPROUNDING) -DEF_C99_BUILTIN (BUILT_IN_CBRT, "cbrt", BT_FN_DOUBLE_DOUBLE, ATTR_MATHFN_FPROUNDING) -DEF_C99_BUILTIN (BUILT_IN_CBRTF, "cbrtf", BT_FN_FLOAT_FLOAT, ATTR_MATHFN_FPROUNDING) -DEF_C99_BUILTIN (BUILT_IN_CBRTL, "cbrtl", BT_FN_LONGDOUBLE_LONGDOUBLE, ATTR_MATHFN_FPROUNDING) -DEF_LIB_BUILTIN (BUILT_IN_CEIL, "ceil", BT_FN_DOUBLE_DOUBLE, ATTR_CONST_NOTHROW_LEAF_LIST) -DEF_C99_C90RES_BUILTIN (BUILT_IN_CEILF, "ceilf", BT_FN_FLOAT_FLOAT, ATTR_CONST_NOTHROW_LEAF_LIST) -DEF_C99_C90RES_BUILTIN (BUILT_IN_CEILL, "ceill", BT_FN_LONGDOUBLE_LONGDOUBLE, ATTR_CONST_NOTHROW_LEAF_LIST) -DEF_C99_BUILTIN (BUILT_IN_COPYSIGN, "copysign", BT_FN_DOUBLE_DOUBLE_DOUBLE, ATTR_CONST_NOTHROW_LEAF_LIST) -DEF_C99_BUILTIN (BUILT_IN_COPYSIGNF, "copysignf", BT_FN_FLOAT_FLOAT_FLOAT, ATTR_CONST_NOTHROW_LEAF_LIST) -DEF_C99_BUILTIN (BUILT_IN_COPYSIGNL, "copysignl", BT_FN_LONGDOUBLE_LONGDOUBLE_LONGDOUBLE, ATTR_CONST_NOTHROW_LEAF_LIST) -DEF_LIB_BUILTIN (BUILT_IN_COS, "cos", BT_FN_DOUBLE_DOUBLE, ATTR_MATHFN_FPROUNDING) -DEF_C99_C90RES_BUILTIN (BUILT_IN_COSF, "cosf", BT_FN_FLOAT_FLOAT, ATTR_MATHFN_FPROUNDING) -DEF_LIB_BUILTIN (BUILT_IN_COSH, "cosh", BT_FN_DOUBLE_DOUBLE, ATTR_MATHFN_FPROUNDING_ERRNO) -DEF_C99_C90RES_BUILTIN (BUILT_IN_COSHF, "coshf", BT_FN_FLOAT_FLOAT, ATTR_MATHFN_FPROUNDING_ERRNO) -DEF_C99_C90RES_BUILTIN (BUILT_IN_COSHL, "coshl", BT_FN_LONGDOUBLE_LONGDOUBLE, ATTR_MATHFN_FPROUNDING_ERRNO) -DEF_C99_C90RES_BUILTIN (BUILT_IN_COSL, "cosl", BT_FN_LONGDOUBLE_LONGDOUBLE, ATTR_MATHFN_FPROUNDING) -DEF_EXT_LIB_BUILTIN (BUILT_IN_DREM, "drem", BT_FN_DOUBLE_DOUBLE_DOUBLE, ATTR_MATHFN_FPROUNDING_ERRNO) -DEF_EXT_LIB_BUILTIN (BUILT_IN_DREMF, "dremf", BT_FN_FLOAT_FLOAT_FLOAT, ATTR_MATHFN_FPROUNDING_ERRNO) -DEF_EXT_LIB_BUILTIN (BUILT_IN_DREML, "dreml", BT_FN_LONGDOUBLE_LONGDOUBLE_LONGDOUBLE, ATTR_MATHFN_FPROUNDING_ERRNO) -DEF_C99_BUILTIN (BUILT_IN_ERF, "erf", BT_FN_DOUBLE_DOUBLE, ATTR_MATHFN_FPROUNDING) -DEF_C99_BUILTIN (BUILT_IN_ERFC, "erfc", BT_FN_DOUBLE_DOUBLE, ATTR_MATHFN_FPROUNDING_ERRNO) -DEF_C99_BUILTIN (BUILT_IN_ERFCF, "erfcf", BT_FN_FLOAT_FLOAT, ATTR_MATHFN_FPROUNDING_ERRNO) -DEF_C99_BUILTIN (BUILT_IN_ERFCL, "erfcl", BT_FN_LONGDOUBLE_LONGDOUBLE, ATTR_MATHFN_FPROUNDING_ERRNO) -DEF_C99_BUILTIN (BUILT_IN_ERFF, "erff", BT_FN_FLOAT_FLOAT, ATTR_MATHFN_FPROUNDING) -DEF_C99_BUILTIN (BUILT_IN_ERFL, "erfl", BT_FN_LONGDOUBLE_LONGDOUBLE, ATTR_MATHFN_FPROUNDING) -DEF_LIB_BUILTIN (BUILT_IN_EXP, "exp", BT_FN_DOUBLE_DOUBLE, ATTR_MATHFN_FPROUNDING_ERRNO) -DEF_EXT_LIB_BUILTIN (BUILT_IN_EXP10, "exp10", BT_FN_DOUBLE_DOUBLE, ATTR_MATHFN_FPROUNDING_ERRNO) -DEF_EXT_LIB_BUILTIN (BUILT_IN_EXP10F, "exp10f", BT_FN_FLOAT_FLOAT, ATTR_MATHFN_FPROUNDING_ERRNO) -DEF_EXT_LIB_BUILTIN (BUILT_IN_EXP10L, "exp10l", BT_FN_LONGDOUBLE_LONGDOUBLE, ATTR_MATHFN_FPROUNDING_ERRNO) -DEF_C99_BUILTIN (BUILT_IN_EXP2, "exp2", BT_FN_DOUBLE_DOUBLE, ATTR_MATHFN_FPROUNDING_ERRNO) -DEF_C99_BUILTIN (BUILT_IN_EXP2F, "exp2f", BT_FN_FLOAT_FLOAT, ATTR_MATHFN_FPROUNDING_ERRNO) -DEF_C99_BUILTIN (BUILT_IN_EXP2L, "exp2l", BT_FN_LONGDOUBLE_LONGDOUBLE, ATTR_MATHFN_FPROUNDING_ERRNO) -DEF_C99_C90RES_BUILTIN (BUILT_IN_EXPF, "expf", BT_FN_FLOAT_FLOAT, ATTR_MATHFN_FPROUNDING_ERRNO) -DEF_C99_C90RES_BUILTIN (BUILT_IN_EXPL, "expl", BT_FN_LONGDOUBLE_LONGDOUBLE, ATTR_MATHFN_FPROUNDING_ERRNO) -DEF_C99_BUILTIN (BUILT_IN_EXPM1, "expm1", BT_FN_DOUBLE_DOUBLE, ATTR_MATHFN_FPROUNDING_ERRNO) -DEF_C99_BUILTIN (BUILT_IN_EXPM1F, "expm1f", BT_FN_FLOAT_FLOAT, ATTR_MATHFN_FPROUNDING_ERRNO) -DEF_C99_BUILTIN (BUILT_IN_EXPM1L, "expm1l", BT_FN_LONGDOUBLE_LONGDOUBLE, ATTR_MATHFN_FPROUNDING_ERRNO) -DEF_LIB_BUILTIN (BUILT_IN_FABS, "fabs", BT_FN_DOUBLE_DOUBLE, ATTR_CONST_NOTHROW_LEAF_LIST) -DEF_C99_C90RES_BUILTIN (BUILT_IN_FABSF, "fabsf", BT_FN_FLOAT_FLOAT, ATTR_CONST_NOTHROW_LEAF_LIST) -DEF_C99_C90RES_BUILTIN (BUILT_IN_FABSL, "fabsl", BT_FN_LONGDOUBLE_LONGDOUBLE, ATTR_CONST_NOTHROW_LEAF_LIST) -DEF_GCC_BUILTIN (BUILT_IN_FABSD32, "fabsd32", BT_FN_DFLOAT32_DFLOAT32, ATTR_CONST_NOTHROW_LEAF_LIST) -DEF_GCC_BUILTIN (BUILT_IN_FABSD64, "fabsd64", BT_FN_DFLOAT64_DFLOAT64, ATTR_CONST_NOTHROW_LEAF_LIST) -DEF_GCC_BUILTIN (BUILT_IN_FABSD128, "fabsd128", BT_FN_DFLOAT128_DFLOAT128, ATTR_CONST_NOTHROW_LEAF_LIST) -DEF_C99_BUILTIN (BUILT_IN_FDIM, "fdim", BT_FN_DOUBLE_DOUBLE_DOUBLE, ATTR_MATHFN_FPROUNDING_ERRNO) -DEF_C99_BUILTIN (BUILT_IN_FDIMF, "fdimf", BT_FN_FLOAT_FLOAT_FLOAT, ATTR_MATHFN_FPROUNDING_ERRNO) -DEF_C99_BUILTIN (BUILT_IN_FDIML, "fdiml", BT_FN_LONGDOUBLE_LONGDOUBLE_LONGDOUBLE, ATTR_MATHFN_FPROUNDING_ERRNO) -DEF_LIB_BUILTIN (BUILT_IN_FLOOR, "floor", BT_FN_DOUBLE_DOUBLE, ATTR_CONST_NOTHROW_LEAF_LIST) -DEF_C99_C90RES_BUILTIN (BUILT_IN_FLOORF, "floorf", BT_FN_FLOAT_FLOAT, ATTR_CONST_NOTHROW_LEAF_LIST) -DEF_C99_C90RES_BUILTIN (BUILT_IN_FLOORL, "floorl", BT_FN_LONGDOUBLE_LONGDOUBLE, ATTR_CONST_NOTHROW_LEAF_LIST) -DEF_C99_BUILTIN (BUILT_IN_FMA, "fma", BT_FN_DOUBLE_DOUBLE_DOUBLE_DOUBLE, ATTR_MATHFN_FPROUNDING) -DEF_C99_BUILTIN (BUILT_IN_FMAF, "fmaf", BT_FN_FLOAT_FLOAT_FLOAT_FLOAT, ATTR_MATHFN_FPROUNDING) -DEF_C99_BUILTIN (BUILT_IN_FMAL, "fmal", BT_FN_LONGDOUBLE_LONGDOUBLE_LONGDOUBLE_LONGDOUBLE, ATTR_MATHFN_FPROUNDING) -DEF_C99_BUILTIN (BUILT_IN_FMAX, "fmax", BT_FN_DOUBLE_DOUBLE_DOUBLE, ATTR_CONST_NOTHROW_LEAF_LIST) -DEF_C99_BUILTIN (BUILT_IN_FMAXF, "fmaxf", BT_FN_FLOAT_FLOAT_FLOAT, ATTR_CONST_NOTHROW_LEAF_LIST) -DEF_C99_BUILTIN (BUILT_IN_FMAXL, "fmaxl", BT_FN_LONGDOUBLE_LONGDOUBLE_LONGDOUBLE, ATTR_CONST_NOTHROW_LEAF_LIST) -DEF_C99_BUILTIN (BUILT_IN_FMIN, "fmin", BT_FN_DOUBLE_DOUBLE_DOUBLE, ATTR_CONST_NOTHROW_LEAF_LIST) -DEF_C99_BUILTIN (BUILT_IN_FMINF, "fminf", BT_FN_FLOAT_FLOAT_FLOAT, ATTR_CONST_NOTHROW_LEAF_LIST) -DEF_C99_BUILTIN (BUILT_IN_FMINL, "fminl", BT_FN_LONGDOUBLE_LONGDOUBLE_LONGDOUBLE, ATTR_CONST_NOTHROW_LEAF_LIST) -DEF_LIB_BUILTIN (BUILT_IN_FMOD, "fmod", BT_FN_DOUBLE_DOUBLE_DOUBLE, ATTR_MATHFN_FPROUNDING_ERRNO) -DEF_C99_C90RES_BUILTIN (BUILT_IN_FMODF, "fmodf", BT_FN_FLOAT_FLOAT_FLOAT, ATTR_MATHFN_FPROUNDING_ERRNO) -DEF_C99_C90RES_BUILTIN (BUILT_IN_FMODL, "fmodl", BT_FN_LONGDOUBLE_LONGDOUBLE_LONGDOUBLE, ATTR_MATHFN_FPROUNDING_ERRNO) -DEF_LIB_BUILTIN (BUILT_IN_FREXP, "frexp", BT_FN_DOUBLE_DOUBLE_INTPTR, ATTR_MATHFN_FPROUNDING_STORE) -DEF_C99_C90RES_BUILTIN (BUILT_IN_FREXPF, "frexpf", BT_FN_FLOAT_FLOAT_INTPTR, ATTR_MATHFN_FPROUNDING_STORE) -DEF_C99_C90RES_BUILTIN (BUILT_IN_FREXPL, "frexpl", BT_FN_LONGDOUBLE_LONGDOUBLE_INTPTR, ATTR_MATHFN_FPROUNDING_STORE) -DEF_EXT_LIB_BUILTIN (BUILT_IN_GAMMA, "gamma", BT_FN_DOUBLE_DOUBLE, ATTR_MATHFN_FPROUNDING_STORE) -DEF_EXT_LIB_BUILTIN (BUILT_IN_GAMMAF, "gammaf", BT_FN_FLOAT_FLOAT, ATTR_MATHFN_FPROUNDING_STORE) -DEF_EXT_LIB_BUILTIN (BUILT_IN_GAMMAL, "gammal", BT_FN_LONGDOUBLE_LONGDOUBLE, ATTR_MATHFN_FPROUNDING_STORE) -DEF_EXT_LIB_BUILTIN (BUILT_IN_GAMMA_R, "gamma_r", BT_FN_DOUBLE_DOUBLE_INTPTR, ATTR_MATHFN_FPROUNDING_STORE) -DEF_EXT_LIB_BUILTIN (BUILT_IN_GAMMAF_R, "gammaf_r", BT_FN_FLOAT_FLOAT_INTPTR, ATTR_MATHFN_FPROUNDING_STORE) -DEF_EXT_LIB_BUILTIN (BUILT_IN_GAMMAL_R, "gammal_r", BT_FN_LONGDOUBLE_LONGDOUBLE_INTPTR, ATTR_MATHFN_FPROUNDING_STORE) -DEF_GCC_BUILTIN (BUILT_IN_HUGE_VAL, "huge_val", BT_FN_DOUBLE, ATTR_CONST_NOTHROW_LEAF_LIST) -DEF_GCC_BUILTIN (BUILT_IN_HUGE_VALF, "huge_valf", BT_FN_FLOAT, ATTR_CONST_NOTHROW_LEAF_LIST) -DEF_GCC_BUILTIN (BUILT_IN_HUGE_VALL, "huge_vall", BT_FN_LONGDOUBLE, ATTR_CONST_NOTHROW_LEAF_LIST) -DEF_C99_BUILTIN (BUILT_IN_HYPOT, "hypot", BT_FN_DOUBLE_DOUBLE_DOUBLE, ATTR_MATHFN_FPROUNDING_ERRNO) -DEF_C99_BUILTIN (BUILT_IN_HYPOTF, "hypotf", BT_FN_FLOAT_FLOAT_FLOAT, ATTR_MATHFN_FPROUNDING_ERRNO) -DEF_C99_BUILTIN (BUILT_IN_HYPOTL, "hypotl", BT_FN_LONGDOUBLE_LONGDOUBLE_LONGDOUBLE, ATTR_MATHFN_FPROUNDING_ERRNO) -DEF_GCC_BUILTIN (BUILT_IN_ICEIL, "iceil", BT_FN_INT_DOUBLE, ATTR_CONST_NOTHROW_LEAF_LIST) -DEF_GCC_BUILTIN (BUILT_IN_ICEILF, "iceilf", BT_FN_INT_FLOAT, ATTR_CONST_NOTHROW_LEAF_LIST) -DEF_GCC_BUILTIN (BUILT_IN_ICEILL, "iceill", BT_FN_INT_LONGDOUBLE, ATTR_CONST_NOTHROW_LEAF_LIST) -DEF_GCC_BUILTIN (BUILT_IN_IFLOOR, "ifloor", BT_FN_INT_DOUBLE, ATTR_CONST_NOTHROW_LEAF_LIST) -DEF_GCC_BUILTIN (BUILT_IN_IFLOORF, "ifloorf", BT_FN_INT_FLOAT, ATTR_CONST_NOTHROW_LEAF_LIST) -DEF_GCC_BUILTIN (BUILT_IN_IFLOORL, "ifloorl", BT_FN_INT_LONGDOUBLE, ATTR_CONST_NOTHROW_LEAF_LIST) -DEF_C99_BUILTIN (BUILT_IN_ILOGB, "ilogb", BT_FN_INT_DOUBLE, ATTR_MATHFN_FPROUNDING_ERRNO) -DEF_C99_BUILTIN (BUILT_IN_ILOGBF, "ilogbf", BT_FN_INT_FLOAT, ATTR_MATHFN_FPROUNDING_ERRNO) -DEF_C99_BUILTIN (BUILT_IN_ILOGBL, "ilogbl", BT_FN_INT_LONGDOUBLE, ATTR_MATHFN_FPROUNDING_ERRNO) -DEF_GCC_BUILTIN (BUILT_IN_INF, "inf", BT_FN_DOUBLE, ATTR_CONST_NOTHROW_LEAF_LIST) -DEF_GCC_BUILTIN (BUILT_IN_INFF, "inff", BT_FN_FLOAT, ATTR_CONST_NOTHROW_LEAF_LIST) -DEF_GCC_BUILTIN (BUILT_IN_INFL, "infl", BT_FN_LONGDOUBLE, ATTR_CONST_NOTHROW_LEAF_LIST) -DEF_GCC_BUILTIN (BUILT_IN_INFD32, "infd32", BT_FN_DFLOAT32, ATTR_CONST_NOTHROW_LEAF_LIST) -DEF_GCC_BUILTIN (BUILT_IN_INFD64, "infd64", BT_FN_DFLOAT64, ATTR_CONST_NOTHROW_LEAF_LIST) -DEF_GCC_BUILTIN (BUILT_IN_INFD128, "infd128", BT_FN_DFLOAT128, ATTR_CONST_NOTHROW_LEAF_LIST) -DEF_GCC_BUILTIN (BUILT_IN_IRINT, "irint", BT_FN_INT_DOUBLE, ATTR_MATHFN_FPROUNDING_ERRNO) -DEF_GCC_BUILTIN (BUILT_IN_IRINTF, "irintf", BT_FN_INT_FLOAT, ATTR_MATHFN_FPROUNDING_ERRNO) -DEF_GCC_BUILTIN (BUILT_IN_IRINTL, "irintl", BT_FN_INT_LONGDOUBLE, ATTR_MATHFN_FPROUNDING_ERRNO) -DEF_GCC_BUILTIN (BUILT_IN_IROUND, "iround", BT_FN_INT_DOUBLE, ATTR_MATHFN_ERRNO) -DEF_GCC_BUILTIN (BUILT_IN_IROUNDF, "iroundf", BT_FN_INT_FLOAT, ATTR_MATHFN_ERRNO) -DEF_GCC_BUILTIN (BUILT_IN_IROUNDL, "iroundl", BT_FN_INT_LONGDOUBLE, ATTR_MATHFN_ERRNO) -DEF_EXT_LIB_BUILTIN (BUILT_IN_J0, "j0", BT_FN_DOUBLE_DOUBLE, ATTR_MATHFN_FPROUNDING_ERRNO) -DEF_EXT_LIB_BUILTIN (BUILT_IN_J0F, "j0f", BT_FN_FLOAT_FLOAT, ATTR_MATHFN_FPROUNDING_ERRNO) -DEF_EXT_LIB_BUILTIN (BUILT_IN_J0L, "j0l", BT_FN_LONGDOUBLE_LONGDOUBLE, ATTR_MATHFN_FPROUNDING_ERRNO) -DEF_EXT_LIB_BUILTIN (BUILT_IN_J1, "j1", BT_FN_DOUBLE_DOUBLE, ATTR_MATHFN_FPROUNDING_ERRNO) -DEF_EXT_LIB_BUILTIN (BUILT_IN_J1F, "j1f", BT_FN_FLOAT_FLOAT, ATTR_MATHFN_FPROUNDING_ERRNO) -DEF_EXT_LIB_BUILTIN (BUILT_IN_J1L, "j1l", BT_FN_LONGDOUBLE_LONGDOUBLE, ATTR_MATHFN_FPROUNDING_ERRNO) -DEF_EXT_LIB_BUILTIN (BUILT_IN_JN, "jn", BT_FN_DOUBLE_INT_DOUBLE, ATTR_MATHFN_FPROUNDING_ERRNO) -DEF_EXT_LIB_BUILTIN (BUILT_IN_JNF, "jnf", BT_FN_FLOAT_INT_FLOAT, ATTR_MATHFN_FPROUNDING_ERRNO) -DEF_EXT_LIB_BUILTIN (BUILT_IN_JNL, "jnl", BT_FN_LONGDOUBLE_INT_LONGDOUBLE, ATTR_MATHFN_FPROUNDING_ERRNO) -DEF_GCC_BUILTIN (BUILT_IN_LCEIL, "lceil", BT_FN_LONG_DOUBLE, ATTR_CONST_NOTHROW_LEAF_LIST) -DEF_GCC_BUILTIN (BUILT_IN_LCEILF, "lceilf", BT_FN_LONG_FLOAT, ATTR_CONST_NOTHROW_LEAF_LIST) -DEF_GCC_BUILTIN (BUILT_IN_LCEILL, "lceill", BT_FN_LONG_LONGDOUBLE, ATTR_CONST_NOTHROW_LEAF_LIST) -DEF_LIB_BUILTIN (BUILT_IN_LDEXP, "ldexp", BT_FN_DOUBLE_DOUBLE_INT, ATTR_MATHFN_FPROUNDING_ERRNO) -DEF_C99_C90RES_BUILTIN (BUILT_IN_LDEXPF, "ldexpf", BT_FN_FLOAT_FLOAT_INT, ATTR_MATHFN_FPROUNDING_ERRNO) -DEF_C99_C90RES_BUILTIN (BUILT_IN_LDEXPL, "ldexpl", BT_FN_LONGDOUBLE_LONGDOUBLE_INT, ATTR_MATHFN_FPROUNDING_ERRNO) -DEF_GCC_BUILTIN (BUILT_IN_LFLOOR, "lfloor", BT_FN_LONG_DOUBLE, ATTR_CONST_NOTHROW_LEAF_LIST) -DEF_GCC_BUILTIN (BUILT_IN_LFLOORF, "lfloorf", BT_FN_LONG_FLOAT, ATTR_CONST_NOTHROW_LEAF_LIST) -DEF_GCC_BUILTIN (BUILT_IN_LFLOORL, "lfloorl", BT_FN_LONG_LONGDOUBLE, ATTR_CONST_NOTHROW_LEAF_LIST) -DEF_C99_BUILTIN (BUILT_IN_LGAMMA, "lgamma", BT_FN_DOUBLE_DOUBLE, ATTR_MATHFN_FPROUNDING_STORE) -DEF_C99_BUILTIN (BUILT_IN_LGAMMAF, "lgammaf", BT_FN_FLOAT_FLOAT, ATTR_MATHFN_FPROUNDING_STORE) -DEF_C99_BUILTIN (BUILT_IN_LGAMMAL, "lgammal", BT_FN_LONGDOUBLE_LONGDOUBLE, ATTR_MATHFN_FPROUNDING_STORE) -DEF_EXT_LIB_BUILTIN (BUILT_IN_LGAMMA_R, "lgamma_r", BT_FN_DOUBLE_DOUBLE_INTPTR, ATTR_MATHFN_FPROUNDING_STORE) -DEF_EXT_LIB_BUILTIN (BUILT_IN_LGAMMAF_R, "lgammaf_r", BT_FN_FLOAT_FLOAT_INTPTR, ATTR_MATHFN_FPROUNDING_STORE) -DEF_EXT_LIB_BUILTIN (BUILT_IN_LGAMMAL_R, "lgammal_r", BT_FN_LONGDOUBLE_LONGDOUBLE_INTPTR, ATTR_MATHFN_FPROUNDING_STORE) -DEF_GCC_BUILTIN (BUILT_IN_LLCEIL, "llceil", BT_FN_LONGLONG_DOUBLE, ATTR_CONST_NOTHROW_LEAF_LIST) -DEF_GCC_BUILTIN (BUILT_IN_LLCEILF, "llceilf", BT_FN_LONGLONG_FLOAT, ATTR_CONST_NOTHROW_LEAF_LIST) -DEF_GCC_BUILTIN (BUILT_IN_LLCEILL, "llceill", BT_FN_LONGLONG_LONGDOUBLE, ATTR_CONST_NOTHROW_LEAF_LIST) -DEF_GCC_BUILTIN (BUILT_IN_LLFLOOR, "llfloor", BT_FN_LONGLONG_DOUBLE, ATTR_CONST_NOTHROW_LEAF_LIST) -DEF_GCC_BUILTIN (BUILT_IN_LLFLOORF, "llfloorf", BT_FN_LONGLONG_FLOAT, ATTR_CONST_NOTHROW_LEAF_LIST) -DEF_GCC_BUILTIN (BUILT_IN_LLFLOORL, "llfloorl", BT_FN_LONGLONG_LONGDOUBLE, ATTR_CONST_NOTHROW_LEAF_LIST) -DEF_C99_BUILTIN (BUILT_IN_LLRINT, "llrint", BT_FN_LONGLONG_DOUBLE, ATTR_MATHFN_FPROUNDING_ERRNO) -DEF_C99_BUILTIN (BUILT_IN_LLRINTF, "llrintf", BT_FN_LONGLONG_FLOAT, ATTR_MATHFN_FPROUNDING_ERRNO) -DEF_C99_BUILTIN (BUILT_IN_LLRINTL, "llrintl", BT_FN_LONGLONG_LONGDOUBLE, ATTR_MATHFN_FPROUNDING_ERRNO) -DEF_C99_BUILTIN (BUILT_IN_LLROUND, "llround", BT_FN_LONGLONG_DOUBLE, ATTR_MATHFN_ERRNO) -DEF_C99_BUILTIN (BUILT_IN_LLROUNDF, "llroundf", BT_FN_LONGLONG_FLOAT, ATTR_MATHFN_ERRNO) -DEF_C99_BUILTIN (BUILT_IN_LLROUNDL, "llroundl", BT_FN_LONGLONG_LONGDOUBLE, ATTR_MATHFN_ERRNO) -DEF_LIB_BUILTIN (BUILT_IN_LOG, "log", BT_FN_DOUBLE_DOUBLE, ATTR_MATHFN_FPROUNDING_ERRNO) -DEF_LIB_BUILTIN (BUILT_IN_LOG10, "log10", BT_FN_DOUBLE_DOUBLE, ATTR_MATHFN_FPROUNDING_ERRNO) -DEF_C99_C90RES_BUILTIN (BUILT_IN_LOG10F, "log10f", BT_FN_FLOAT_FLOAT, ATTR_MATHFN_FPROUNDING_ERRNO) -DEF_C99_C90RES_BUILTIN (BUILT_IN_LOG10L, "log10l", BT_FN_LONGDOUBLE_LONGDOUBLE, ATTR_MATHFN_FPROUNDING_ERRNO) -DEF_C99_BUILTIN (BUILT_IN_LOG1P, "log1p", BT_FN_DOUBLE_DOUBLE, ATTR_MATHFN_FPROUNDING_ERRNO) -DEF_C99_BUILTIN (BUILT_IN_LOG1PF, "log1pf", BT_FN_FLOAT_FLOAT, ATTR_MATHFN_FPROUNDING_ERRNO) -DEF_C99_BUILTIN (BUILT_IN_LOG1PL, "log1pl", BT_FN_LONGDOUBLE_LONGDOUBLE, ATTR_MATHFN_FPROUNDING_ERRNO) -DEF_C99_BUILTIN (BUILT_IN_LOG2, "log2", BT_FN_DOUBLE_DOUBLE, ATTR_MATHFN_FPROUNDING_ERRNO) -DEF_C99_BUILTIN (BUILT_IN_LOG2F, "log2f", BT_FN_FLOAT_FLOAT, ATTR_MATHFN_FPROUNDING_ERRNO) -DEF_C99_BUILTIN (BUILT_IN_LOG2L, "log2l", BT_FN_LONGDOUBLE_LONGDOUBLE, ATTR_MATHFN_FPROUNDING_ERRNO) -DEF_C99_BUILTIN (BUILT_IN_LOGB, "logb", BT_FN_DOUBLE_DOUBLE, ATTR_MATHFN_FPROUNDING_ERRNO) -DEF_C99_BUILTIN (BUILT_IN_LOGBF, "logbf", BT_FN_FLOAT_FLOAT, ATTR_MATHFN_FPROUNDING_ERRNO) -DEF_C99_BUILTIN (BUILT_IN_LOGBL, "logbl", BT_FN_LONGDOUBLE_LONGDOUBLE, ATTR_MATHFN_FPROUNDING_ERRNO) -DEF_C99_C90RES_BUILTIN (BUILT_IN_LOGF, "logf", BT_FN_FLOAT_FLOAT, ATTR_MATHFN_FPROUNDING_ERRNO) -DEF_C99_C90RES_BUILTIN (BUILT_IN_LOGL, "logl", BT_FN_LONGDOUBLE_LONGDOUBLE, ATTR_MATHFN_FPROUNDING_ERRNO) -DEF_C99_BUILTIN (BUILT_IN_LRINT, "lrint", BT_FN_LONG_DOUBLE, ATTR_MATHFN_FPROUNDING_ERRNO) -DEF_C99_BUILTIN (BUILT_IN_LRINTF, "lrintf", BT_FN_LONG_FLOAT, ATTR_MATHFN_FPROUNDING_ERRNO) -DEF_C99_BUILTIN (BUILT_IN_LRINTL, "lrintl", BT_FN_LONG_LONGDOUBLE, ATTR_MATHFN_FPROUNDING_ERRNO) -DEF_C99_BUILTIN (BUILT_IN_LROUND, "lround", BT_FN_LONG_DOUBLE, ATTR_MATHFN_ERRNO) -DEF_C99_BUILTIN (BUILT_IN_LROUNDF, "lroundf", BT_FN_LONG_FLOAT, ATTR_MATHFN_ERRNO) -DEF_C99_BUILTIN (BUILT_IN_LROUNDL, "lroundl", BT_FN_LONG_LONGDOUBLE, ATTR_MATHFN_ERRNO) -DEF_LIB_BUILTIN (BUILT_IN_MODF, "modf", BT_FN_DOUBLE_DOUBLE_DOUBLEPTR, ATTR_MATHFN_FPROUNDING_STORE) -DEF_C99_C90RES_BUILTIN (BUILT_IN_MODFF, "modff", BT_FN_FLOAT_FLOAT_FLOATPTR, ATTR_MATHFN_FPROUNDING_STORE) -DEF_C99_C90RES_BUILTIN (BUILT_IN_MODFL, "modfl", BT_FN_LONGDOUBLE_LONGDOUBLE_LONGDOUBLEPTR, ATTR_MATHFN_FPROUNDING_STORE) -DEF_C99_BUILTIN (BUILT_IN_NAN, "nan", BT_FN_DOUBLE_CONST_STRING, ATTR_CONST_NOTHROW_NONNULL) -DEF_C99_BUILTIN (BUILT_IN_NANF, "nanf", BT_FN_FLOAT_CONST_STRING, ATTR_CONST_NOTHROW_NONNULL) -DEF_C99_BUILTIN (BUILT_IN_NANL, "nanl", BT_FN_LONGDOUBLE_CONST_STRING, ATTR_CONST_NOTHROW_NONNULL) -DEF_GCC_BUILTIN (BUILT_IN_NAND32, "nand32", BT_FN_DFLOAT32_CONST_STRING, ATTR_CONST_NOTHROW_NONNULL) -DEF_GCC_BUILTIN (BUILT_IN_NAND64, "nand64", BT_FN_DFLOAT64_CONST_STRING, ATTR_CONST_NOTHROW_NONNULL) -DEF_GCC_BUILTIN (BUILT_IN_NAND128, "nand128", BT_FN_DFLOAT128_CONST_STRING, ATTR_CONST_NOTHROW_NONNULL) -DEF_GCC_BUILTIN (BUILT_IN_NANS, "nans", BT_FN_DOUBLE_CONST_STRING, ATTR_CONST_NOTHROW_NONNULL) -DEF_GCC_BUILTIN (BUILT_IN_NANSF, "nansf", BT_FN_FLOAT_CONST_STRING, ATTR_CONST_NOTHROW_NONNULL) -DEF_GCC_BUILTIN (BUILT_IN_NANSL, "nansl", BT_FN_LONGDOUBLE_CONST_STRING, ATTR_CONST_NOTHROW_NONNULL) -DEF_C99_BUILTIN (BUILT_IN_NEARBYINT, "nearbyint", BT_FN_DOUBLE_DOUBLE, ATTR_CONST_NOTHROW_LEAF_LIST) -DEF_C99_BUILTIN (BUILT_IN_NEARBYINTF, "nearbyintf", BT_FN_FLOAT_FLOAT, ATTR_CONST_NOTHROW_LEAF_LIST) -DEF_C99_BUILTIN (BUILT_IN_NEARBYINTL, "nearbyintl", BT_FN_LONGDOUBLE_LONGDOUBLE, ATTR_CONST_NOTHROW_LEAF_LIST) -DEF_C99_BUILTIN (BUILT_IN_NEXTAFTER, "nextafter", BT_FN_DOUBLE_DOUBLE_DOUBLE, ATTR_MATHFN_FPROUNDING_ERRNO) -DEF_C99_BUILTIN (BUILT_IN_NEXTAFTERF, "nextafterf", BT_FN_FLOAT_FLOAT_FLOAT, ATTR_MATHFN_FPROUNDING_ERRNO) -DEF_C99_BUILTIN (BUILT_IN_NEXTAFTERL, "nextafterl", BT_FN_LONGDOUBLE_LONGDOUBLE_LONGDOUBLE, ATTR_MATHFN_FPROUNDING_ERRNO) -DEF_C99_BUILTIN (BUILT_IN_NEXTTOWARD, "nexttoward", BT_FN_DOUBLE_DOUBLE_LONGDOUBLE, ATTR_MATHFN_FPROUNDING_ERRNO) -DEF_C99_BUILTIN (BUILT_IN_NEXTTOWARDF, "nexttowardf", BT_FN_FLOAT_FLOAT_LONGDOUBLE, ATTR_MATHFN_FPROUNDING_ERRNO) -DEF_C99_BUILTIN (BUILT_IN_NEXTTOWARDL, "nexttowardl", BT_FN_LONGDOUBLE_LONGDOUBLE_LONGDOUBLE, ATTR_MATHFN_FPROUNDING_ERRNO) -DEF_LIB_BUILTIN (BUILT_IN_POW, "pow", BT_FN_DOUBLE_DOUBLE_DOUBLE, ATTR_MATHFN_FPROUNDING_ERRNO) -DEF_EXT_LIB_BUILTIN (BUILT_IN_POW10, "pow10", BT_FN_DOUBLE_DOUBLE, ATTR_MATHFN_FPROUNDING_ERRNO) -DEF_EXT_LIB_BUILTIN (BUILT_IN_POW10F, "pow10f", BT_FN_FLOAT_FLOAT, ATTR_MATHFN_FPROUNDING_ERRNO) -DEF_EXT_LIB_BUILTIN (BUILT_IN_POW10L, "pow10l", BT_FN_LONGDOUBLE_LONGDOUBLE, ATTR_MATHFN_FPROUNDING_ERRNO) -DEF_C99_C90RES_BUILTIN (BUILT_IN_POWF, "powf", BT_FN_FLOAT_FLOAT_FLOAT, ATTR_MATHFN_FPROUNDING_ERRNO) -DEF_GCC_BUILTIN (BUILT_IN_POWI, "powi", BT_FN_DOUBLE_DOUBLE_INT, ATTR_MATHFN_FPROUNDING) -DEF_GCC_BUILTIN (BUILT_IN_POWIF, "powif", BT_FN_FLOAT_FLOAT_INT, ATTR_MATHFN_FPROUNDING) -DEF_GCC_BUILTIN (BUILT_IN_POWIL, "powil", BT_FN_LONGDOUBLE_LONGDOUBLE_INT, ATTR_MATHFN_FPROUNDING) -DEF_C99_C90RES_BUILTIN (BUILT_IN_POWL, "powl", BT_FN_LONGDOUBLE_LONGDOUBLE_LONGDOUBLE, ATTR_MATHFN_FPROUNDING_ERRNO) -DEF_C99_BUILTIN (BUILT_IN_REMAINDER, "remainder", BT_FN_DOUBLE_DOUBLE_DOUBLE, ATTR_MATHFN_FPROUNDING_ERRNO) -DEF_C99_BUILTIN (BUILT_IN_REMAINDERF, "remainderf", BT_FN_FLOAT_FLOAT_FLOAT, ATTR_MATHFN_FPROUNDING_ERRNO) -DEF_C99_BUILTIN (BUILT_IN_REMAINDERL, "remainderl", BT_FN_LONGDOUBLE_LONGDOUBLE_LONGDOUBLE, ATTR_MATHFN_FPROUNDING_ERRNO) -DEF_C99_BUILTIN (BUILT_IN_REMQUO, "remquo", BT_FN_DOUBLE_DOUBLE_DOUBLE_INTPTR, ATTR_MATHFN_FPROUNDING_STORE) -DEF_C99_BUILTIN (BUILT_IN_REMQUOF, "remquof", BT_FN_FLOAT_FLOAT_FLOAT_INTPTR, ATTR_MATHFN_FPROUNDING_STORE) -DEF_C99_BUILTIN (BUILT_IN_REMQUOL, "remquol", BT_FN_LONGDOUBLE_LONGDOUBLE_LONGDOUBLE_INTPTR, ATTR_MATHFN_FPROUNDING_STORE) -DEF_C99_BUILTIN (BUILT_IN_RINT, "rint", BT_FN_DOUBLE_DOUBLE, ATTR_MATHFN_FPROUNDING_ERRNO) -DEF_C99_BUILTIN (BUILT_IN_RINTF, "rintf", BT_FN_FLOAT_FLOAT, ATTR_MATHFN_FPROUNDING_ERRNO) -DEF_C99_BUILTIN (BUILT_IN_RINTL, "rintl", BT_FN_LONGDOUBLE_LONGDOUBLE, ATTR_MATHFN_FPROUNDING_ERRNO) -DEF_C99_BUILTIN (BUILT_IN_ROUND, "round", BT_FN_DOUBLE_DOUBLE, ATTR_CONST_NOTHROW_LEAF_LIST) -DEF_C99_BUILTIN (BUILT_IN_ROUNDF, "roundf", BT_FN_FLOAT_FLOAT, ATTR_CONST_NOTHROW_LEAF_LIST) -DEF_C99_BUILTIN (BUILT_IN_ROUNDL, "roundl", BT_FN_LONGDOUBLE_LONGDOUBLE, ATTR_CONST_NOTHROW_LEAF_LIST) -DEF_EXT_LIB_BUILTIN (BUILT_IN_SCALB, "scalb", BT_FN_DOUBLE_DOUBLE_DOUBLE, ATTR_MATHFN_FPROUNDING_ERRNO) -DEF_EXT_LIB_BUILTIN (BUILT_IN_SCALBF, "scalbf", BT_FN_FLOAT_FLOAT_FLOAT, ATTR_MATHFN_FPROUNDING_ERRNO) -DEF_EXT_LIB_BUILTIN (BUILT_IN_SCALBL, "scalbl", BT_FN_LONGDOUBLE_LONGDOUBLE_LONGDOUBLE, ATTR_MATHFN_FPROUNDING_ERRNO) -DEF_C99_BUILTIN (BUILT_IN_SCALBLN, "scalbln", BT_FN_DOUBLE_DOUBLE_LONG, ATTR_MATHFN_FPROUNDING_ERRNO) -DEF_C99_BUILTIN (BUILT_IN_SCALBLNF, "scalblnf", BT_FN_FLOAT_FLOAT_LONG, ATTR_MATHFN_FPROUNDING_ERRNO) -DEF_C99_BUILTIN (BUILT_IN_SCALBLNL, "scalblnl", BT_FN_LONGDOUBLE_LONGDOUBLE_LONG, ATTR_MATHFN_FPROUNDING_ERRNO) -DEF_C99_BUILTIN (BUILT_IN_SCALBN, "scalbn", BT_FN_DOUBLE_DOUBLE_INT, ATTR_MATHFN_FPROUNDING_ERRNO) -DEF_C99_BUILTIN (BUILT_IN_SCALBNF, "scalbnf", BT_FN_FLOAT_FLOAT_INT, ATTR_MATHFN_FPROUNDING_ERRNO) -DEF_C99_BUILTIN (BUILT_IN_SCALBNL, "scalbnl", BT_FN_LONGDOUBLE_LONGDOUBLE_INT, ATTR_MATHFN_FPROUNDING_ERRNO) -DEF_EXT_LIB_BUILTIN (BUILT_IN_SIGNBIT, "signbit", BT_FN_INT_DOUBLE, ATTR_CONST_NOTHROW_LEAF_LIST) -DEF_EXT_LIB_BUILTIN (BUILT_IN_SIGNBITF, "signbitf", BT_FN_INT_FLOAT, ATTR_CONST_NOTHROW_LEAF_LIST) -DEF_EXT_LIB_BUILTIN (BUILT_IN_SIGNBITL, "signbitl", BT_FN_INT_LONGDOUBLE, ATTR_CONST_NOTHROW_LEAF_LIST) -DEF_EXT_LIB_BUILTIN (BUILT_IN_SIGNBITD32, "signbitd32", BT_FN_INT_DFLOAT32, ATTR_CONST_NOTHROW_LEAF_LIST) -DEF_EXT_LIB_BUILTIN (BUILT_IN_SIGNBITD64, "signbitd64", BT_FN_INT_DFLOAT64, ATTR_CONST_NOTHROW_LEAF_LIST) -DEF_EXT_LIB_BUILTIN (BUILT_IN_SIGNBITD128, "signbitd128", BT_FN_INT_DFLOAT128, ATTR_CONST_NOTHROW_LEAF_LIST) -DEF_EXT_LIB_BUILTIN (BUILT_IN_SIGNIFICAND, "significand", BT_FN_DOUBLE_DOUBLE, ATTR_MATHFN_FPROUNDING_ERRNO) -DEF_EXT_LIB_BUILTIN (BUILT_IN_SIGNIFICANDF, "significandf", BT_FN_FLOAT_FLOAT, ATTR_MATHFN_FPROUNDING_ERRNO) -DEF_EXT_LIB_BUILTIN (BUILT_IN_SIGNIFICANDL, "significandl", BT_FN_LONGDOUBLE_LONGDOUBLE, ATTR_MATHFN_FPROUNDING_ERRNO) -DEF_LIB_BUILTIN (BUILT_IN_SIN, "sin", BT_FN_DOUBLE_DOUBLE, ATTR_MATHFN_FPROUNDING) -DEF_EXT_LIB_BUILTIN (BUILT_IN_SINCOS, "sincos", BT_FN_VOID_DOUBLE_DOUBLEPTR_DOUBLEPTR, ATTR_MATHFN_FPROUNDING_STORE) -DEF_EXT_LIB_BUILTIN (BUILT_IN_SINCOSF, "sincosf", BT_FN_VOID_FLOAT_FLOATPTR_FLOATPTR, ATTR_MATHFN_FPROUNDING_STORE) -DEF_EXT_LIB_BUILTIN (BUILT_IN_SINCOSL, "sincosl", BT_FN_VOID_LONGDOUBLE_LONGDOUBLEPTR_LONGDOUBLEPTR, ATTR_MATHFN_FPROUNDING_STORE) -DEF_C99_C90RES_BUILTIN (BUILT_IN_SINF, "sinf", BT_FN_FLOAT_FLOAT, ATTR_MATHFN_FPROUNDING) -DEF_LIB_BUILTIN (BUILT_IN_SINH, "sinh", BT_FN_DOUBLE_DOUBLE, ATTR_MATHFN_FPROUNDING_ERRNO) -DEF_C99_C90RES_BUILTIN (BUILT_IN_SINHF, "sinhf", BT_FN_FLOAT_FLOAT, ATTR_MATHFN_FPROUNDING_ERRNO) -DEF_C99_C90RES_BUILTIN (BUILT_IN_SINHL, "sinhl", BT_FN_LONGDOUBLE_LONGDOUBLE, ATTR_MATHFN_FPROUNDING_ERRNO) -DEF_C99_C90RES_BUILTIN (BUILT_IN_SINL, "sinl", BT_FN_LONGDOUBLE_LONGDOUBLE, ATTR_MATHFN_FPROUNDING) -DEF_LIB_BUILTIN (BUILT_IN_SQRT, "sqrt", BT_FN_DOUBLE_DOUBLE, ATTR_MATHFN_FPROUNDING_ERRNO) -DEF_C99_C90RES_BUILTIN (BUILT_IN_SQRTF, "sqrtf", BT_FN_FLOAT_FLOAT, ATTR_MATHFN_FPROUNDING_ERRNO) -DEF_C99_C90RES_BUILTIN (BUILT_IN_SQRTL, "sqrtl", BT_FN_LONGDOUBLE_LONGDOUBLE, ATTR_MATHFN_FPROUNDING_ERRNO) -DEF_LIB_BUILTIN (BUILT_IN_TAN, "tan", BT_FN_DOUBLE_DOUBLE, ATTR_MATHFN_FPROUNDING) -DEF_C99_C90RES_BUILTIN (BUILT_IN_TANF, "tanf", BT_FN_FLOAT_FLOAT, ATTR_MATHFN_FPROUNDING) -DEF_LIB_BUILTIN (BUILT_IN_TANH, "tanh", BT_FN_DOUBLE_DOUBLE, ATTR_MATHFN_FPROUNDING) -DEF_C99_C90RES_BUILTIN (BUILT_IN_TANHF, "tanhf", BT_FN_FLOAT_FLOAT, ATTR_MATHFN_FPROUNDING) -DEF_C99_C90RES_BUILTIN (BUILT_IN_TANHL, "tanhl", BT_FN_LONGDOUBLE_LONGDOUBLE, ATTR_MATHFN_FPROUNDING) -DEF_C99_C90RES_BUILTIN (BUILT_IN_TANL, "tanl", BT_FN_LONGDOUBLE_LONGDOUBLE, ATTR_MATHFN_FPROUNDING) -DEF_C99_BUILTIN (BUILT_IN_TGAMMA, "tgamma", BT_FN_DOUBLE_DOUBLE, ATTR_MATHFN_FPROUNDING_ERRNO) -DEF_C99_BUILTIN (BUILT_IN_TGAMMAF, "tgammaf", BT_FN_FLOAT_FLOAT, ATTR_MATHFN_FPROUNDING_ERRNO) -DEF_C99_BUILTIN (BUILT_IN_TGAMMAL, "tgammal", BT_FN_LONGDOUBLE_LONGDOUBLE, ATTR_MATHFN_FPROUNDING_ERRNO) -DEF_C99_BUILTIN (BUILT_IN_TRUNC, "trunc", BT_FN_DOUBLE_DOUBLE, ATTR_CONST_NOTHROW_LEAF_LIST) -DEF_C99_BUILTIN (BUILT_IN_TRUNCF, "truncf", BT_FN_FLOAT_FLOAT, ATTR_CONST_NOTHROW_LEAF_LIST) -DEF_C99_BUILTIN (BUILT_IN_TRUNCL, "truncl", BT_FN_LONGDOUBLE_LONGDOUBLE, ATTR_CONST_NOTHROW_LEAF_LIST) -DEF_EXT_LIB_BUILTIN (BUILT_IN_Y0, "y0", BT_FN_DOUBLE_DOUBLE, ATTR_MATHFN_FPROUNDING_ERRNO) -DEF_EXT_LIB_BUILTIN (BUILT_IN_Y0F, "y0f", BT_FN_FLOAT_FLOAT, ATTR_MATHFN_FPROUNDING_ERRNO) -DEF_EXT_LIB_BUILTIN (BUILT_IN_Y0L, "y0l", BT_FN_LONGDOUBLE_LONGDOUBLE, ATTR_MATHFN_FPROUNDING_ERRNO) -DEF_EXT_LIB_BUILTIN (BUILT_IN_Y1, "y1", BT_FN_DOUBLE_DOUBLE, ATTR_MATHFN_FPROUNDING_ERRNO) -DEF_EXT_LIB_BUILTIN (BUILT_IN_Y1F, "y1f", BT_FN_FLOAT_FLOAT, ATTR_MATHFN_FPROUNDING_ERRNO) -DEF_EXT_LIB_BUILTIN (BUILT_IN_Y1L, "y1l", BT_FN_LONGDOUBLE_LONGDOUBLE, ATTR_MATHFN_FPROUNDING_ERRNO) -DEF_EXT_LIB_BUILTIN (BUILT_IN_YN, "yn", BT_FN_DOUBLE_INT_DOUBLE, ATTR_MATHFN_FPROUNDING_ERRNO) -DEF_EXT_LIB_BUILTIN (BUILT_IN_YNF, "ynf", BT_FN_FLOAT_INT_FLOAT, ATTR_MATHFN_FPROUNDING_ERRNO) -DEF_EXT_LIB_BUILTIN (BUILT_IN_YNL, "ynl", BT_FN_LONGDOUBLE_INT_LONGDOUBLE, ATTR_MATHFN_FPROUNDING_ERRNO) - -/* Category: _Complex math builtins. */ -DEF_C99_COMPL_BUILTIN (BUILT_IN_CABS, "cabs", BT_FN_DOUBLE_COMPLEX_DOUBLE, ATTR_MATHFN_FPROUNDING) -DEF_C99_COMPL_BUILTIN (BUILT_IN_CABSF, "cabsf", BT_FN_FLOAT_COMPLEX_FLOAT, ATTR_MATHFN_FPROUNDING) -DEF_C99_COMPL_BUILTIN (BUILT_IN_CABSL, "cabsl", BT_FN_LONGDOUBLE_COMPLEX_LONGDOUBLE, ATTR_MATHFN_FPROUNDING) -DEF_C99_COMPL_BUILTIN (BUILT_IN_CACOS, "cacos", BT_FN_COMPLEX_DOUBLE_COMPLEX_DOUBLE, ATTR_MATHFN_FPROUNDING) -DEF_C99_COMPL_BUILTIN (BUILT_IN_CACOSF, "cacosf", BT_FN_COMPLEX_FLOAT_COMPLEX_FLOAT, ATTR_MATHFN_FPROUNDING) -DEF_C99_COMPL_BUILTIN (BUILT_IN_CACOSH, "cacosh", BT_FN_COMPLEX_DOUBLE_COMPLEX_DOUBLE, ATTR_MATHFN_FPROUNDING) -DEF_C99_COMPL_BUILTIN (BUILT_IN_CACOSHF, "cacoshf", BT_FN_COMPLEX_FLOAT_COMPLEX_FLOAT, ATTR_MATHFN_FPROUNDING) -DEF_C99_COMPL_BUILTIN (BUILT_IN_CACOSHL, "cacoshl", BT_FN_COMPLEX_LONGDOUBLE_COMPLEX_LONGDOUBLE, ATTR_MATHFN_FPROUNDING) -DEF_C99_COMPL_BUILTIN (BUILT_IN_CACOSL, "cacosl", BT_FN_COMPLEX_LONGDOUBLE_COMPLEX_LONGDOUBLE, ATTR_MATHFN_FPROUNDING) -DEF_C99_COMPL_BUILTIN (BUILT_IN_CARG, "carg", BT_FN_DOUBLE_COMPLEX_DOUBLE, ATTR_MATHFN_FPROUNDING) -DEF_C99_COMPL_BUILTIN (BUILT_IN_CARGF, "cargf", BT_FN_FLOAT_COMPLEX_FLOAT, ATTR_MATHFN_FPROUNDING) -DEF_C99_COMPL_BUILTIN (BUILT_IN_CARGL, "cargl", BT_FN_LONGDOUBLE_COMPLEX_LONGDOUBLE, ATTR_MATHFN_FPROUNDING) -DEF_C99_COMPL_BUILTIN (BUILT_IN_CASIN, "casin", BT_FN_COMPLEX_DOUBLE_COMPLEX_DOUBLE, ATTR_MATHFN_FPROUNDING) -DEF_C99_COMPL_BUILTIN (BUILT_IN_CASINF, "casinf", BT_FN_COMPLEX_FLOAT_COMPLEX_FLOAT, ATTR_MATHFN_FPROUNDING) -DEF_C99_COMPL_BUILTIN (BUILT_IN_CASINH, "casinh", BT_FN_COMPLEX_DOUBLE_COMPLEX_DOUBLE, ATTR_MATHFN_FPROUNDING) -DEF_C99_COMPL_BUILTIN (BUILT_IN_CASINHF, "casinhf", BT_FN_COMPLEX_FLOAT_COMPLEX_FLOAT, ATTR_MATHFN_FPROUNDING) -DEF_C99_COMPL_BUILTIN (BUILT_IN_CASINHL, "casinhl", BT_FN_COMPLEX_LONGDOUBLE_COMPLEX_LONGDOUBLE, ATTR_MATHFN_FPROUNDING) -DEF_C99_COMPL_BUILTIN (BUILT_IN_CASINL, "casinl", BT_FN_COMPLEX_LONGDOUBLE_COMPLEX_LONGDOUBLE, ATTR_MATHFN_FPROUNDING) -DEF_C99_COMPL_BUILTIN (BUILT_IN_CATAN, "catan", BT_FN_COMPLEX_DOUBLE_COMPLEX_DOUBLE, ATTR_MATHFN_FPROUNDING) -DEF_C99_COMPL_BUILTIN (BUILT_IN_CATANF, "catanf", BT_FN_COMPLEX_FLOAT_COMPLEX_FLOAT, ATTR_MATHFN_FPROUNDING) -DEF_C99_COMPL_BUILTIN (BUILT_IN_CATANH, "catanh", BT_FN_COMPLEX_DOUBLE_COMPLEX_DOUBLE, ATTR_MATHFN_FPROUNDING) -DEF_C99_COMPL_BUILTIN (BUILT_IN_CATANHF, "catanhf", BT_FN_COMPLEX_FLOAT_COMPLEX_FLOAT, ATTR_MATHFN_FPROUNDING) -DEF_C99_COMPL_BUILTIN (BUILT_IN_CATANHL, "catanhl", BT_FN_COMPLEX_LONGDOUBLE_COMPLEX_LONGDOUBLE, ATTR_MATHFN_FPROUNDING) -DEF_C99_COMPL_BUILTIN (BUILT_IN_CATANL, "catanl", BT_FN_COMPLEX_LONGDOUBLE_COMPLEX_LONGDOUBLE, ATTR_MATHFN_FPROUNDING) -DEF_C99_COMPL_BUILTIN (BUILT_IN_CCOS, "ccos", BT_FN_COMPLEX_DOUBLE_COMPLEX_DOUBLE, ATTR_MATHFN_FPROUNDING) -DEF_C99_COMPL_BUILTIN (BUILT_IN_CCOSF, "ccosf", BT_FN_COMPLEX_FLOAT_COMPLEX_FLOAT, ATTR_MATHFN_FPROUNDING) -DEF_C99_COMPL_BUILTIN (BUILT_IN_CCOSH, "ccosh", BT_FN_COMPLEX_DOUBLE_COMPLEX_DOUBLE, ATTR_MATHFN_FPROUNDING) -DEF_C99_COMPL_BUILTIN (BUILT_IN_CCOSHF, "ccoshf", BT_FN_COMPLEX_FLOAT_COMPLEX_FLOAT, ATTR_MATHFN_FPROUNDING) -DEF_C99_COMPL_BUILTIN (BUILT_IN_CCOSHL, "ccoshl", BT_FN_COMPLEX_LONGDOUBLE_COMPLEX_LONGDOUBLE, ATTR_MATHFN_FPROUNDING) -DEF_C99_COMPL_BUILTIN (BUILT_IN_CCOSL, "ccosl", BT_FN_COMPLEX_LONGDOUBLE_COMPLEX_LONGDOUBLE, ATTR_MATHFN_FPROUNDING) -DEF_C99_COMPL_BUILTIN (BUILT_IN_CEXP, "cexp", BT_FN_COMPLEX_DOUBLE_COMPLEX_DOUBLE, ATTR_MATHFN_FPROUNDING) -DEF_C99_COMPL_BUILTIN (BUILT_IN_CEXPF, "cexpf", BT_FN_COMPLEX_FLOAT_COMPLEX_FLOAT, ATTR_MATHFN_FPROUNDING) -DEF_C99_COMPL_BUILTIN (BUILT_IN_CEXPL, "cexpl", BT_FN_COMPLEX_LONGDOUBLE_COMPLEX_LONGDOUBLE, ATTR_MATHFN_FPROUNDING) -DEF_GCC_BUILTIN (BUILT_IN_CEXPI, "cexpi", BT_FN_COMPLEX_DOUBLE_DOUBLE, ATTR_MATHFN_FPROUNDING) -DEF_GCC_BUILTIN (BUILT_IN_CEXPIF, "cexpif", BT_FN_COMPLEX_FLOAT_FLOAT, ATTR_MATHFN_FPROUNDING) -DEF_GCC_BUILTIN (BUILT_IN_CEXPIL, "cexpil", BT_FN_COMPLEX_LONGDOUBLE_LONGDOUBLE, ATTR_MATHFN_FPROUNDING) -DEF_C99_COMPL_BUILTIN (BUILT_IN_CIMAG, "cimag", BT_FN_DOUBLE_COMPLEX_DOUBLE, ATTR_CONST_NOTHROW_LEAF_LIST) -DEF_C99_COMPL_BUILTIN (BUILT_IN_CIMAGF, "cimagf", BT_FN_FLOAT_COMPLEX_FLOAT, ATTR_CONST_NOTHROW_LEAF_LIST) -DEF_C99_COMPL_BUILTIN (BUILT_IN_CIMAGL, "cimagl", BT_FN_LONGDOUBLE_COMPLEX_LONGDOUBLE, ATTR_CONST_NOTHROW_LEAF_LIST) -DEF_C99_COMPL_BUILTIN (BUILT_IN_CLOG, "clog", BT_FN_COMPLEX_DOUBLE_COMPLEX_DOUBLE, ATTR_MATHFN_FPROUNDING) -DEF_C99_COMPL_BUILTIN (BUILT_IN_CLOGF, "clogf", BT_FN_COMPLEX_FLOAT_COMPLEX_FLOAT, ATTR_MATHFN_FPROUNDING) -DEF_C99_COMPL_BUILTIN (BUILT_IN_CLOGL, "clogl", BT_FN_COMPLEX_LONGDOUBLE_COMPLEX_LONGDOUBLE, ATTR_MATHFN_FPROUNDING) -DEF_EXT_C99RES_BUILTIN (BUILT_IN_CLOG10, "clog10", BT_FN_COMPLEX_DOUBLE_COMPLEX_DOUBLE, ATTR_MATHFN_FPROUNDING) -DEF_EXT_C99RES_BUILTIN (BUILT_IN_CLOG10F, "clog10f", BT_FN_COMPLEX_FLOAT_COMPLEX_FLOAT, ATTR_MATHFN_FPROUNDING) -DEF_EXT_C99RES_BUILTIN (BUILT_IN_CLOG10L, "clog10l", BT_FN_COMPLEX_LONGDOUBLE_COMPLEX_LONGDOUBLE, ATTR_MATHFN_FPROUNDING) -DEF_C99_COMPL_BUILTIN (BUILT_IN_CONJ, "conj", BT_FN_COMPLEX_DOUBLE_COMPLEX_DOUBLE, ATTR_CONST_NOTHROW_LEAF_LIST) -DEF_C99_COMPL_BUILTIN (BUILT_IN_CONJF, "conjf", BT_FN_COMPLEX_FLOAT_COMPLEX_FLOAT, ATTR_CONST_NOTHROW_LEAF_LIST) -DEF_C99_COMPL_BUILTIN (BUILT_IN_CONJL, "conjl", BT_FN_COMPLEX_LONGDOUBLE_COMPLEX_LONGDOUBLE, ATTR_CONST_NOTHROW_LEAF_LIST) -DEF_C99_COMPL_BUILTIN (BUILT_IN_CPOW, "cpow", BT_FN_COMPLEX_DOUBLE_COMPLEX_DOUBLE_COMPLEX_DOUBLE, ATTR_MATHFN_FPROUNDING) -DEF_C99_COMPL_BUILTIN (BUILT_IN_CPOWF, "cpowf", BT_FN_COMPLEX_FLOAT_COMPLEX_FLOAT_COMPLEX_FLOAT, ATTR_MATHFN_FPROUNDING) -DEF_C99_COMPL_BUILTIN (BUILT_IN_CPOWL, "cpowl", BT_FN_COMPLEX_LONGDOUBLE_COMPLEX_LONGDOUBLE_COMPLEX_LONGDOUBLE, ATTR_MATHFN_FPROUNDING) -DEF_C99_COMPL_BUILTIN (BUILT_IN_CPROJ, "cproj", BT_FN_COMPLEX_DOUBLE_COMPLEX_DOUBLE, ATTR_CONST_NOTHROW_LEAF_LIST) -DEF_C99_COMPL_BUILTIN (BUILT_IN_CPROJF, "cprojf", BT_FN_COMPLEX_FLOAT_COMPLEX_FLOAT, ATTR_CONST_NOTHROW_LEAF_LIST) -DEF_C99_COMPL_BUILTIN (BUILT_IN_CPROJL, "cprojl", BT_FN_COMPLEX_LONGDOUBLE_COMPLEX_LONGDOUBLE, ATTR_CONST_NOTHROW_LEAF_LIST) -DEF_C99_COMPL_BUILTIN (BUILT_IN_CREAL, "creal", BT_FN_DOUBLE_COMPLEX_DOUBLE, ATTR_CONST_NOTHROW_LEAF_LIST) -DEF_C99_COMPL_BUILTIN (BUILT_IN_CREALF, "crealf", BT_FN_FLOAT_COMPLEX_FLOAT, ATTR_CONST_NOTHROW_LEAF_LIST) -DEF_C99_COMPL_BUILTIN (BUILT_IN_CREALL, "creall", BT_FN_LONGDOUBLE_COMPLEX_LONGDOUBLE, ATTR_CONST_NOTHROW_LEAF_LIST) -DEF_C99_COMPL_BUILTIN (BUILT_IN_CSIN, "csin", BT_FN_COMPLEX_DOUBLE_COMPLEX_DOUBLE, ATTR_MATHFN_FPROUNDING) -DEF_C99_COMPL_BUILTIN (BUILT_IN_CSINF, "csinf", BT_FN_COMPLEX_FLOAT_COMPLEX_FLOAT, ATTR_MATHFN_FPROUNDING) -DEF_C99_COMPL_BUILTIN (BUILT_IN_CSINH, "csinh", BT_FN_COMPLEX_DOUBLE_COMPLEX_DOUBLE, ATTR_MATHFN_FPROUNDING) -DEF_C99_COMPL_BUILTIN (BUILT_IN_CSINHF, "csinhf", BT_FN_COMPLEX_FLOAT_COMPLEX_FLOAT, ATTR_MATHFN_FPROUNDING) -DEF_C99_COMPL_BUILTIN (BUILT_IN_CSINHL, "csinhl", BT_FN_COMPLEX_LONGDOUBLE_COMPLEX_LONGDOUBLE, ATTR_MATHFN_FPROUNDING) -DEF_C99_COMPL_BUILTIN (BUILT_IN_CSINL, "csinl", BT_FN_COMPLEX_LONGDOUBLE_COMPLEX_LONGDOUBLE, ATTR_MATHFN_FPROUNDING) -DEF_C99_COMPL_BUILTIN (BUILT_IN_CSQRT, "csqrt", BT_FN_COMPLEX_DOUBLE_COMPLEX_DOUBLE, ATTR_MATHFN_FPROUNDING) -DEF_C99_COMPL_BUILTIN (BUILT_IN_CSQRTF, "csqrtf", BT_FN_COMPLEX_FLOAT_COMPLEX_FLOAT, ATTR_MATHFN_FPROUNDING) -DEF_C99_COMPL_BUILTIN (BUILT_IN_CSQRTL, "csqrtl", BT_FN_COMPLEX_LONGDOUBLE_COMPLEX_LONGDOUBLE, ATTR_MATHFN_FPROUNDING) -DEF_C99_COMPL_BUILTIN (BUILT_IN_CTAN, "ctan", BT_FN_COMPLEX_DOUBLE_COMPLEX_DOUBLE, ATTR_MATHFN_FPROUNDING) -DEF_C99_COMPL_BUILTIN (BUILT_IN_CTANF, "ctanf", BT_FN_COMPLEX_FLOAT_COMPLEX_FLOAT, ATTR_MATHFN_FPROUNDING) -DEF_C99_COMPL_BUILTIN (BUILT_IN_CTANH, "ctanh", BT_FN_COMPLEX_DOUBLE_COMPLEX_DOUBLE, ATTR_MATHFN_FPROUNDING) -DEF_C99_COMPL_BUILTIN (BUILT_IN_CTANHF, "ctanhf", BT_FN_COMPLEX_FLOAT_COMPLEX_FLOAT, ATTR_MATHFN_FPROUNDING) -DEF_C99_COMPL_BUILTIN (BUILT_IN_CTANHL, "ctanhl", BT_FN_COMPLEX_LONGDOUBLE_COMPLEX_LONGDOUBLE, ATTR_MATHFN_FPROUNDING) -DEF_C99_COMPL_BUILTIN (BUILT_IN_CTANL, "ctanl", BT_FN_COMPLEX_LONGDOUBLE_COMPLEX_LONGDOUBLE, ATTR_MATHFN_FPROUNDING) - -/* Category: string/memory builtins. */ -/* bcmp, bcopy and bzero have traditionally accepted NULL pointers - when the length parameter is zero, so don't apply attribute "nonnull". */ -DEF_EXT_LIB_BUILTIN (BUILT_IN_BCMP, "bcmp", BT_FN_INT_CONST_PTR_CONST_PTR_SIZE, ATTR_PURE_NOTHROW_LEAF_LIST) -DEF_EXT_LIB_BUILTIN (BUILT_IN_BCOPY, "bcopy", BT_FN_VOID_CONST_PTR_PTR_SIZE, ATTR_NOTHROW_LEAF_LIST) -DEF_EXT_LIB_BUILTIN (BUILT_IN_BZERO, "bzero", BT_FN_VOID_PTR_SIZE, ATTR_NOTHROW_LEAF_LIST) -DEF_EXT_LIB_BUILTIN (BUILT_IN_INDEX, "index", BT_FN_STRING_CONST_STRING_INT, ATTR_PURE_NOTHROW_NONNULL_LEAF) -DEF_LIB_BUILTIN (BUILT_IN_MEMCHR, "memchr", BT_FN_PTR_CONST_PTR_INT_SIZE, ATTR_PURE_NOTHROW_NONNULL_LEAF) -DEF_LIB_BUILTIN (BUILT_IN_MEMCMP, "memcmp", BT_FN_INT_CONST_PTR_CONST_PTR_SIZE, ATTR_PURE_NOTHROW_NONNULL_LEAF) -DEF_LIB_BUILTIN_CHKP (BUILT_IN_MEMCPY, "memcpy", BT_FN_PTR_PTR_CONST_PTR_SIZE, ATTR_RET1_NOTHROW_NONNULL_LEAF) -DEF_LIB_BUILTIN_CHKP (BUILT_IN_MEMMOVE, "memmove", BT_FN_PTR_PTR_CONST_PTR_SIZE, ATTR_RET1_NOTHROW_NONNULL_LEAF) -DEF_EXT_LIB_BUILTIN_CHKP (BUILT_IN_MEMPCPY, "mempcpy", BT_FN_PTR_PTR_CONST_PTR_SIZE, ATTR_NOTHROW_NONNULL_LEAF) -DEF_LIB_BUILTIN_CHKP (BUILT_IN_MEMSET, "memset", BT_FN_PTR_PTR_INT_SIZE, ATTR_RET1_NOTHROW_NONNULL_LEAF) -DEF_EXT_LIB_BUILTIN (BUILT_IN_RINDEX, "rindex", BT_FN_STRING_CONST_STRING_INT, ATTR_PURE_NOTHROW_NONNULL_LEAF) -DEF_EXT_LIB_BUILTIN_CHKP (BUILT_IN_STPCPY, "stpcpy", BT_FN_STRING_STRING_CONST_STRING, ATTR_NOTHROW_NONNULL_LEAF) -DEF_EXT_LIB_BUILTIN (BUILT_IN_STPNCPY, "stpncpy", BT_FN_STRING_STRING_CONST_STRING_SIZE, ATTR_NOTHROW_NONNULL_LEAF) -DEF_EXT_LIB_BUILTIN (BUILT_IN_STRCASECMP, "strcasecmp", BT_FN_INT_CONST_STRING_CONST_STRING, ATTR_PURE_NOTHROW_NONNULL_LEAF) -DEF_LIB_BUILTIN_CHKP (BUILT_IN_STRCAT, "strcat", BT_FN_STRING_STRING_CONST_STRING, ATTR_NOTHROW_NONNULL_LEAF) -DEF_LIB_BUILTIN_CHKP (BUILT_IN_STRCHR, "strchr", BT_FN_STRING_CONST_STRING_INT, ATTR_PURE_NOTHROW_NONNULL_LEAF) -DEF_LIB_BUILTIN (BUILT_IN_STRCMP, "strcmp", BT_FN_INT_CONST_STRING_CONST_STRING, ATTR_PURE_NOTHROW_NONNULL_LEAF) -DEF_LIB_BUILTIN_CHKP (BUILT_IN_STRCPY, "strcpy", BT_FN_STRING_STRING_CONST_STRING, ATTR_RET1_NOTHROW_NONNULL_LEAF) -DEF_LIB_BUILTIN (BUILT_IN_STRCSPN, "strcspn", BT_FN_SIZE_CONST_STRING_CONST_STRING, ATTR_PURE_NOTHROW_NONNULL_LEAF) -DEF_EXT_LIB_BUILTIN (BUILT_IN_STRDUP, "strdup", BT_FN_STRING_CONST_STRING, ATTR_MALLOC_NOTHROW_NONNULL_LEAF) -DEF_EXT_LIB_BUILTIN (BUILT_IN_STRNDUP, "strndup", BT_FN_STRING_CONST_STRING_SIZE, ATTR_MALLOC_NOTHROW_NONNULL_LEAF) -DEF_LIB_BUILTIN_CHKP (BUILT_IN_STRLEN, "strlen", BT_FN_SIZE_CONST_STRING, ATTR_PURE_NOTHROW_NONNULL_LEAF) -DEF_EXT_LIB_BUILTIN (BUILT_IN_STRNCASECMP, "strncasecmp", BT_FN_INT_CONST_STRING_CONST_STRING_SIZE, ATTR_PURE_NOTHROW_NONNULL_LEAF) -DEF_LIB_BUILTIN (BUILT_IN_STRNCAT, "strncat", BT_FN_STRING_STRING_CONST_STRING_SIZE, ATTR_NOTHROW_NONNULL_LEAF) -DEF_LIB_BUILTIN (BUILT_IN_STRNCMP, "strncmp", BT_FN_INT_CONST_STRING_CONST_STRING_SIZE, ATTR_PURE_NOTHROW_NONNULL_LEAF) -DEF_LIB_BUILTIN (BUILT_IN_STRNCPY, "strncpy", BT_FN_STRING_STRING_CONST_STRING_SIZE, ATTR_NOTHROW_NONNULL_LEAF) -DEF_LIB_BUILTIN (BUILT_IN_STRPBRK, "strpbrk", BT_FN_STRING_CONST_STRING_CONST_STRING, ATTR_PURE_NOTHROW_NONNULL_LEAF) -DEF_LIB_BUILTIN (BUILT_IN_STRRCHR, "strrchr", BT_FN_STRING_CONST_STRING_INT, ATTR_PURE_NOTHROW_NONNULL_LEAF) -DEF_LIB_BUILTIN (BUILT_IN_STRSPN, "strspn", BT_FN_SIZE_CONST_STRING_CONST_STRING, ATTR_PURE_NOTHROW_NONNULL_LEAF) -DEF_LIB_BUILTIN (BUILT_IN_STRSTR, "strstr", BT_FN_STRING_CONST_STRING_CONST_STRING, ATTR_PURE_NOTHROW_NONNULL_LEAF) - -/* Category: stdio builtins. */ -DEF_LIB_BUILTIN (BUILT_IN_FPRINTF, "fprintf", BT_FN_INT_FILEPTR_CONST_STRING_VAR, ATTR_FORMAT_PRINTF_2_3) -DEF_EXT_LIB_BUILTIN (BUILT_IN_FPRINTF_UNLOCKED, "fprintf_unlocked", BT_FN_INT_FILEPTR_CONST_STRING_VAR, ATTR_FORMAT_PRINTF_2_3) -DEF_LIB_BUILTIN (BUILT_IN_PUTC, "putc", BT_FN_INT_INT_FILEPTR, ATTR_NONNULL_LIST) -DEF_EXT_LIB_BUILTIN (BUILT_IN_PUTC_UNLOCKED, "putc_unlocked", BT_FN_INT_INT_FILEPTR, ATTR_NONNULL_LIST) -DEF_LIB_BUILTIN (BUILT_IN_FPUTC, "fputc", BT_FN_INT_INT_FILEPTR, ATTR_NONNULL_LIST) -DEF_EXT_LIB_BUILTIN (BUILT_IN_FPUTC_UNLOCKED, "fputc_unlocked", BT_FN_INT_INT_FILEPTR, ATTR_NONNULL_LIST) -DEF_LIB_BUILTIN (BUILT_IN_FPUTS, "fputs", BT_FN_INT_CONST_STRING_FILEPTR, ATTR_NONNULL_LIST) -DEF_EXT_LIB_BUILTIN (BUILT_IN_FPUTS_UNLOCKED, "fputs_unlocked", BT_FN_INT_CONST_STRING_FILEPTR, ATTR_NONNULL_LIST) -DEF_LIB_BUILTIN (BUILT_IN_FSCANF, "fscanf", BT_FN_INT_FILEPTR_CONST_STRING_VAR, ATTR_FORMAT_SCANF_2_3) -DEF_LIB_BUILTIN (BUILT_IN_FWRITE, "fwrite", BT_FN_SIZE_CONST_PTR_SIZE_SIZE_FILEPTR, ATTR_NONNULL_LIST) -DEF_EXT_LIB_BUILTIN (BUILT_IN_FWRITE_UNLOCKED, "fwrite_unlocked", BT_FN_SIZE_CONST_PTR_SIZE_SIZE_FILEPTR, ATTR_NONNULL_LIST) -DEF_LIB_BUILTIN (BUILT_IN_PRINTF, "printf", BT_FN_INT_CONST_STRING_VAR, ATTR_FORMAT_PRINTF_1_2) -DEF_EXT_LIB_BUILTIN (BUILT_IN_PRINTF_UNLOCKED, "printf_unlocked", BT_FN_INT_CONST_STRING_VAR, ATTR_FORMAT_PRINTF_1_2) -DEF_LIB_BUILTIN (BUILT_IN_PUTCHAR, "putchar", BT_FN_INT_INT, ATTR_NULL) -DEF_EXT_LIB_BUILTIN (BUILT_IN_PUTCHAR_UNLOCKED, "putchar_unlocked", BT_FN_INT_INT, ATTR_NULL) -DEF_LIB_BUILTIN (BUILT_IN_PUTS, "puts", BT_FN_INT_CONST_STRING, ATTR_NONNULL_LIST) -DEF_EXT_LIB_BUILTIN (BUILT_IN_PUTS_UNLOCKED, "puts_unlocked", BT_FN_INT_CONST_STRING, ATTR_NONNULL_LIST) -DEF_LIB_BUILTIN (BUILT_IN_SCANF, "scanf", BT_FN_INT_CONST_STRING_VAR, ATTR_FORMAT_SCANF_1_2) -DEF_C99_BUILTIN (BUILT_IN_SNPRINTF, "snprintf", BT_FN_INT_STRING_SIZE_CONST_STRING_VAR, ATTR_FORMAT_PRINTF_NOTHROW_3_4) -DEF_LIB_BUILTIN (BUILT_IN_SPRINTF, "sprintf", BT_FN_INT_STRING_CONST_STRING_VAR, ATTR_FORMAT_PRINTF_NOTHROW_2_3) -DEF_LIB_BUILTIN (BUILT_IN_SSCANF, "sscanf", BT_FN_INT_CONST_STRING_CONST_STRING_VAR, ATTR_FORMAT_SCANF_NOTHROW_2_3) -DEF_LIB_BUILTIN (BUILT_IN_VFPRINTF, "vfprintf", BT_FN_INT_FILEPTR_CONST_STRING_VALIST_ARG, ATTR_FORMAT_PRINTF_2_0) -DEF_C99_BUILTIN (BUILT_IN_VFSCANF, "vfscanf", BT_FN_INT_FILEPTR_CONST_STRING_VALIST_ARG, ATTR_FORMAT_SCANF_2_0) -DEF_LIB_BUILTIN (BUILT_IN_VPRINTF, "vprintf", BT_FN_INT_CONST_STRING_VALIST_ARG, ATTR_FORMAT_PRINTF_1_0) -DEF_C99_BUILTIN (BUILT_IN_VSCANF, "vscanf", BT_FN_INT_CONST_STRING_VALIST_ARG, ATTR_FORMAT_SCANF_1_0) -DEF_C99_BUILTIN (BUILT_IN_VSNPRINTF, "vsnprintf", BT_FN_INT_STRING_SIZE_CONST_STRING_VALIST_ARG, ATTR_FORMAT_PRINTF_NOTHROW_3_0) -DEF_LIB_BUILTIN (BUILT_IN_VSPRINTF, "vsprintf", BT_FN_INT_STRING_CONST_STRING_VALIST_ARG, ATTR_FORMAT_PRINTF_NOTHROW_2_0) -DEF_C99_BUILTIN (BUILT_IN_VSSCANF, "vsscanf", BT_FN_INT_CONST_STRING_CONST_STRING_VALIST_ARG, ATTR_FORMAT_SCANF_NOTHROW_2_0) - -/* Category: ctype builtins. */ -DEF_LIB_BUILTIN (BUILT_IN_ISALNUM, "isalnum", BT_FN_INT_INT, ATTR_PURE_NOTHROW_LEAF_LIST) -DEF_LIB_BUILTIN (BUILT_IN_ISALPHA, "isalpha", BT_FN_INT_INT, ATTR_PURE_NOTHROW_LEAF_LIST) -DEF_EXT_LIB_BUILTIN (BUILT_IN_ISASCII, "isascii", BT_FN_INT_INT, ATTR_CONST_NOTHROW_LEAF_LIST) -DEF_C99_BUILTIN (BUILT_IN_ISBLANK, "isblank", BT_FN_INT_INT, ATTR_PURE_NOTHROW_LEAF_LIST) -DEF_LIB_BUILTIN (BUILT_IN_ISCNTRL, "iscntrl", BT_FN_INT_INT, ATTR_PURE_NOTHROW_LEAF_LIST) -DEF_LIB_BUILTIN (BUILT_IN_ISDIGIT, "isdigit", BT_FN_INT_INT, ATTR_CONST_NOTHROW_LEAF_LIST) -DEF_LIB_BUILTIN (BUILT_IN_ISGRAPH, "isgraph", BT_FN_INT_INT, ATTR_PURE_NOTHROW_LEAF_LIST) -DEF_LIB_BUILTIN (BUILT_IN_ISLOWER, "islower", BT_FN_INT_INT, ATTR_PURE_NOTHROW_LEAF_LIST) -DEF_LIB_BUILTIN (BUILT_IN_ISPRINT, "isprint", BT_FN_INT_INT, ATTR_PURE_NOTHROW_LEAF_LIST) -DEF_LIB_BUILTIN (BUILT_IN_ISPUNCT, "ispunct", BT_FN_INT_INT, ATTR_PURE_NOTHROW_LEAF_LIST) -DEF_LIB_BUILTIN (BUILT_IN_ISSPACE, "isspace", BT_FN_INT_INT, ATTR_PURE_NOTHROW_LEAF_LIST) -DEF_LIB_BUILTIN (BUILT_IN_ISUPPER, "isupper", BT_FN_INT_INT, ATTR_PURE_NOTHROW_LEAF_LIST) -DEF_LIB_BUILTIN (BUILT_IN_ISXDIGIT, "isxdigit", BT_FN_INT_INT, ATTR_CONST_NOTHROW_LEAF_LIST) -DEF_EXT_LIB_BUILTIN (BUILT_IN_TOASCII, "toascii", BT_FN_INT_INT, ATTR_CONST_NOTHROW_LEAF_LIST) -DEF_LIB_BUILTIN (BUILT_IN_TOLOWER, "tolower", BT_FN_INT_INT, ATTR_PURE_NOTHROW_LEAF_LIST) -DEF_LIB_BUILTIN (BUILT_IN_TOUPPER, "toupper", BT_FN_INT_INT, ATTR_PURE_NOTHROW_LEAF_LIST) - -/* Category: wctype builtins. */ -DEF_C94_BUILTIN (BUILT_IN_ISWALNUM, "iswalnum", BT_FN_INT_WINT, ATTR_PURE_NOTHROW_LEAF_LIST) -DEF_C94_BUILTIN (BUILT_IN_ISWALPHA, "iswalpha", BT_FN_INT_WINT, ATTR_PURE_NOTHROW_LEAF_LIST) -DEF_C99_BUILTIN (BUILT_IN_ISWBLANK, "iswblank", BT_FN_INT_WINT, ATTR_PURE_NOTHROW_LEAF_LIST) -DEF_C94_BUILTIN (BUILT_IN_ISWCNTRL, "iswcntrl", BT_FN_INT_WINT, ATTR_PURE_NOTHROW_LEAF_LIST) -DEF_C94_BUILTIN (BUILT_IN_ISWDIGIT, "iswdigit", BT_FN_INT_WINT, ATTR_PURE_NOTHROW_LEAF_LIST) -DEF_C94_BUILTIN (BUILT_IN_ISWGRAPH, "iswgraph", BT_FN_INT_WINT, ATTR_PURE_NOTHROW_LEAF_LIST) -DEF_C94_BUILTIN (BUILT_IN_ISWLOWER, "iswlower", BT_FN_INT_WINT, ATTR_PURE_NOTHROW_LEAF_LIST) -DEF_C94_BUILTIN (BUILT_IN_ISWPRINT, "iswprint", BT_FN_INT_WINT, ATTR_PURE_NOTHROW_LEAF_LIST) -DEF_C94_BUILTIN (BUILT_IN_ISWPUNCT, "iswpunct", BT_FN_INT_WINT, ATTR_PURE_NOTHROW_LEAF_LIST) -DEF_C94_BUILTIN (BUILT_IN_ISWSPACE, "iswspace", BT_FN_INT_WINT, ATTR_PURE_NOTHROW_LEAF_LIST) -DEF_C94_BUILTIN (BUILT_IN_ISWUPPER, "iswupper", BT_FN_INT_WINT, ATTR_PURE_NOTHROW_LEAF_LIST) -DEF_C94_BUILTIN (BUILT_IN_ISWXDIGIT, "iswxdigit", BT_FN_INT_WINT, ATTR_PURE_NOTHROW_LEAF_LIST) -DEF_C94_BUILTIN (BUILT_IN_TOWLOWER, "towlower", BT_FN_WINT_WINT, ATTR_PURE_NOTHROW_LEAF_LIST) -DEF_C94_BUILTIN (BUILT_IN_TOWUPPER, "towupper", BT_FN_WINT_WINT, ATTR_PURE_NOTHROW_LEAF_LIST) - -/* Category: integer overflow checking builtins. */ -DEF_GCC_BUILTIN (BUILT_IN_ADD_OVERFLOW, "add_overflow", BT_FN_BOOL_VAR, ATTR_NOTHROW_TYPEGENERIC_LEAF) -DEF_GCC_BUILTIN (BUILT_IN_SUB_OVERFLOW, "sub_overflow", BT_FN_BOOL_VAR, ATTR_NOTHROW_TYPEGENERIC_LEAF) -DEF_GCC_BUILTIN (BUILT_IN_MUL_OVERFLOW, "mul_overflow", BT_FN_BOOL_VAR, ATTR_NOTHROW_TYPEGENERIC_LEAF) -/* Clang compatibility. */ -DEF_GCC_BUILTIN (BUILT_IN_SADD_OVERFLOW, "sadd_overflow", BT_FN_BOOL_INT_INT_INTPTR, ATTR_NOTHROW_LEAF_LIST) -DEF_GCC_BUILTIN (BUILT_IN_SADDL_OVERFLOW, "saddl_overflow", BT_FN_BOOL_LONG_LONG_LONGPTR, ATTR_NOTHROW_LEAF_LIST) -DEF_GCC_BUILTIN (BUILT_IN_SADDLL_OVERFLOW, "saddll_overflow", BT_FN_BOOL_LONGLONG_LONGLONG_LONGLONGPTR, ATTR_NOTHROW_LEAF_LIST) -DEF_GCC_BUILTIN (BUILT_IN_SSUB_OVERFLOW, "ssub_overflow", BT_FN_BOOL_INT_INT_INTPTR, ATTR_NOTHROW_LEAF_LIST) -DEF_GCC_BUILTIN (BUILT_IN_SSUBL_OVERFLOW, "ssubl_overflow", BT_FN_BOOL_LONG_LONG_LONGPTR, ATTR_NOTHROW_LEAF_LIST) -DEF_GCC_BUILTIN (BUILT_IN_SSUBLL_OVERFLOW, "ssubll_overflow", BT_FN_BOOL_LONGLONG_LONGLONG_LONGLONGPTR, ATTR_NOTHROW_LEAF_LIST) -DEF_GCC_BUILTIN (BUILT_IN_SMUL_OVERFLOW, "smul_overflow", BT_FN_BOOL_INT_INT_INTPTR, ATTR_NOTHROW_LEAF_LIST) -DEF_GCC_BUILTIN (BUILT_IN_SMULL_OVERFLOW, "smull_overflow", BT_FN_BOOL_LONG_LONG_LONGPTR, ATTR_NOTHROW_LEAF_LIST) -DEF_GCC_BUILTIN (BUILT_IN_SMULLL_OVERFLOW, "smulll_overflow", BT_FN_BOOL_LONGLONG_LONGLONG_LONGLONGPTR, ATTR_NOTHROW_LEAF_LIST) -DEF_GCC_BUILTIN (BUILT_IN_UADD_OVERFLOW, "uadd_overflow", BT_FN_BOOL_UINT_UINT_UINTPTR, ATTR_NOTHROW_LEAF_LIST) -DEF_GCC_BUILTIN (BUILT_IN_UADDL_OVERFLOW, "uaddl_overflow", BT_FN_BOOL_ULONG_ULONG_ULONGPTR, ATTR_NOTHROW_LEAF_LIST) -DEF_GCC_BUILTIN (BUILT_IN_UADDLL_OVERFLOW, "uaddll_overflow", BT_FN_BOOL_ULONGLONG_ULONGLONG_ULONGLONGPTR, ATTR_NOTHROW_LEAF_LIST) -DEF_GCC_BUILTIN (BUILT_IN_USUB_OVERFLOW, "usub_overflow", BT_FN_BOOL_UINT_UINT_UINTPTR, ATTR_NOTHROW_LEAF_LIST) -DEF_GCC_BUILTIN (BUILT_IN_USUBL_OVERFLOW, "usubl_overflow", BT_FN_BOOL_ULONG_ULONG_ULONGPTR, ATTR_NOTHROW_LEAF_LIST) -DEF_GCC_BUILTIN (BUILT_IN_USUBLL_OVERFLOW, "usubll_overflow", BT_FN_BOOL_ULONGLONG_ULONGLONG_ULONGLONGPTR, ATTR_NOTHROW_LEAF_LIST) -DEF_GCC_BUILTIN (BUILT_IN_UMUL_OVERFLOW, "umul_overflow", BT_FN_BOOL_UINT_UINT_UINTPTR, ATTR_NOTHROW_LEAF_LIST) -DEF_GCC_BUILTIN (BUILT_IN_UMULL_OVERFLOW, "umull_overflow", BT_FN_BOOL_ULONG_ULONG_ULONGPTR, ATTR_NOTHROW_LEAF_LIST) -DEF_GCC_BUILTIN (BUILT_IN_UMULLL_OVERFLOW, "umulll_overflow", BT_FN_BOOL_ULONGLONG_ULONGLONG_ULONGLONGPTR, ATTR_NOTHROW_LEAF_LIST) - -/* Category: miscellaneous builtins. */ -DEF_LIB_BUILTIN (BUILT_IN_ABORT, "abort", BT_FN_VOID, ATTR_NORETURN_NOTHROW_LEAF_LIST) -DEF_LIB_BUILTIN (BUILT_IN_ABS, "abs", BT_FN_INT_INT, ATTR_CONST_NOTHROW_LEAF_LIST) -DEF_GCC_BUILTIN (BUILT_IN_AGGREGATE_INCOMING_ADDRESS, "aggregate_incoming_address", BT_FN_PTR_VAR, ATTR_LEAF_LIST) -DEF_EXT_LIB_BUILTIN (BUILT_IN_ALLOCA, "alloca", BT_FN_PTR_SIZE, ATTR_MALLOC_NOTHROW_LEAF_LIST) -DEF_GCC_BUILTIN (BUILT_IN_APPLY, "apply", BT_FN_PTR_PTR_FN_VOID_VAR_PTR_SIZE, ATTR_NULL) -DEF_GCC_BUILTIN (BUILT_IN_APPLY_ARGS, "apply_args", BT_FN_PTR_VAR, ATTR_LEAF_LIST) -DEF_GCC_BUILTIN (BUILT_IN_BSWAP16, "bswap16", BT_FN_UINT16_UINT16, ATTR_CONST_NOTHROW_LEAF_LIST) -DEF_GCC_BUILTIN (BUILT_IN_BSWAP32, "bswap32", BT_FN_UINT32_UINT32, ATTR_CONST_NOTHROW_LEAF_LIST) -DEF_GCC_BUILTIN (BUILT_IN_BSWAP64, "bswap64", BT_FN_UINT64_UINT64, ATTR_CONST_NOTHROW_LEAF_LIST) -DEF_EXT_LIB_BUILTIN (BUILT_IN_CLEAR_CACHE, "__clear_cache", BT_FN_VOID_PTR_PTR, ATTR_NOTHROW_LEAF_LIST) -/* [trans-mem]: Adjust BUILT_IN_TM_CALLOC if BUILT_IN_CALLOC is changed. */ -DEF_LIB_BUILTIN (BUILT_IN_CALLOC, "calloc", BT_FN_PTR_SIZE_SIZE, ATTR_MALLOC_NOTHROW_LEAF_LIST) -DEF_GCC_BUILTIN (BUILT_IN_CLASSIFY_TYPE, "classify_type", BT_FN_INT_VAR, ATTR_LEAF_LIST) -DEF_GCC_BUILTIN (BUILT_IN_CLZ, "clz", BT_FN_INT_UINT, ATTR_CONST_NOTHROW_LEAF_LIST) -DEF_GCC_BUILTIN (BUILT_IN_CLZIMAX, "clzimax", BT_FN_INT_UINTMAX, ATTR_CONST_NOTHROW_LEAF_LIST) -DEF_GCC_BUILTIN (BUILT_IN_CLZL, "clzl", BT_FN_INT_ULONG, ATTR_CONST_NOTHROW_LEAF_LIST) -DEF_GCC_BUILTIN (BUILT_IN_CLZLL, "clzll", BT_FN_INT_ULONGLONG, ATTR_CONST_NOTHROW_LEAF_LIST) -DEF_GCC_BUILTIN (BUILT_IN_CONSTANT_P, "constant_p", BT_FN_INT_VAR, ATTR_CONST_NOTHROW_LEAF_LIST) -DEF_GCC_BUILTIN (BUILT_IN_CTZ, "ctz", BT_FN_INT_UINT, ATTR_CONST_NOTHROW_LEAF_LIST) -DEF_GCC_BUILTIN (BUILT_IN_CTZIMAX, "ctzimax", BT_FN_INT_UINTMAX, ATTR_CONST_NOTHROW_LEAF_LIST) -DEF_GCC_BUILTIN (BUILT_IN_CTZL, "ctzl", BT_FN_INT_ULONG, ATTR_CONST_NOTHROW_LEAF_LIST) -DEF_GCC_BUILTIN (BUILT_IN_CTZLL, "ctzll", BT_FN_INT_ULONGLONG, ATTR_CONST_NOTHROW_LEAF_LIST) -DEF_GCC_BUILTIN (BUILT_IN_CLRSB, "clrsb", BT_FN_INT_INT, ATTR_CONST_NOTHROW_LEAF_LIST) -DEF_GCC_BUILTIN (BUILT_IN_CLRSBIMAX, "clrsbimax", BT_FN_INT_INTMAX, ATTR_CONST_NOTHROW_LEAF_LIST) -DEF_GCC_BUILTIN (BUILT_IN_CLRSBL, "clrsbl", BT_FN_INT_LONG, ATTR_CONST_NOTHROW_LEAF_LIST) -DEF_GCC_BUILTIN (BUILT_IN_CLRSBLL, "clrsbll", BT_FN_INT_LONGLONG, ATTR_CONST_NOTHROW_LEAF_LIST) -DEF_EXT_LIB_BUILTIN (BUILT_IN_DCGETTEXT, "dcgettext", BT_FN_STRING_CONST_STRING_CONST_STRING_INT, ATTR_FORMAT_ARG_2) -DEF_EXT_LIB_BUILTIN (BUILT_IN_DGETTEXT, "dgettext", BT_FN_STRING_CONST_STRING_CONST_STRING, ATTR_FORMAT_ARG_2) -DEF_GCC_BUILTIN (BUILT_IN_DWARF_CFA, "dwarf_cfa", BT_FN_PTR, ATTR_NULL) -DEF_GCC_BUILTIN (BUILT_IN_DWARF_SP_COLUMN, "dwarf_sp_column", BT_FN_UINT, ATTR_NULL) -DEF_GCC_BUILTIN (BUILT_IN_EH_RETURN, "eh_return", BT_FN_VOID_PTRMODE_PTR, ATTR_NORETURN_NOTHROW_LEAF_LIST) -DEF_GCC_BUILTIN (BUILT_IN_EH_RETURN_DATA_REGNO, "eh_return_data_regno", BT_FN_INT_INT, ATTR_LEAF_LIST) -DEF_EXT_LIB_BUILTIN (BUILT_IN_EXECL, "execl", BT_FN_INT_CONST_STRING_CONST_STRING_VAR, ATTR_SENTINEL_NOTHROW_LIST) -DEF_EXT_LIB_BUILTIN (BUILT_IN_EXECLP, "execlp", BT_FN_INT_CONST_STRING_CONST_STRING_VAR, ATTR_SENTINEL_NOTHROW_LIST) -DEF_EXT_LIB_BUILTIN (BUILT_IN_EXECLE, "execle", BT_FN_INT_CONST_STRING_CONST_STRING_VAR, ATTR_NOTHROW_SENTINEL_1) -DEF_EXT_LIB_BUILTIN (BUILT_IN_EXECV, "execv", BT_FN_INT_CONST_STRING_PTR_CONST_STRING, ATTR_NOTHROW_LIST) -DEF_EXT_LIB_BUILTIN (BUILT_IN_EXECVP, "execvp", BT_FN_INT_CONST_STRING_PTR_CONST_STRING, ATTR_NOTHROW_LIST) -DEF_EXT_LIB_BUILTIN (BUILT_IN_EXECVE, "execve", BT_FN_INT_CONST_STRING_PTR_CONST_STRING_PTR_CONST_STRING, ATTR_NOTHROW_LIST) -DEF_LIB_BUILTIN (BUILT_IN_EXIT, "exit", BT_FN_VOID_INT, ATTR_NORETURN_NOTHROW_LIST) -DEF_GCC_BUILTIN (BUILT_IN_EXPECT, "expect", BT_FN_LONG_LONG_LONG, ATTR_CONST_NOTHROW_LEAF_LIST) -DEF_GCC_BUILTIN (BUILT_IN_ASSUME_ALIGNED, "assume_aligned", BT_FN_PTR_CONST_PTR_SIZE_VAR, ATTR_CONST_NOTHROW_LEAF_LIST) -DEF_GCC_BUILTIN (BUILT_IN_EXTEND_POINTER, "extend_pointer", BT_FN_UNWINDWORD_PTR, ATTR_CONST_NOTHROW_LEAF_LIST) -DEF_GCC_BUILTIN (BUILT_IN_EXTRACT_RETURN_ADDR, "extract_return_addr", BT_FN_PTR_PTR, ATTR_LEAF_LIST) -DEF_EXT_LIB_BUILTIN (BUILT_IN_FFS, "ffs", BT_FN_INT_INT, ATTR_CONST_NOTHROW_LEAF_LIST) -DEF_EXT_LIB_BUILTIN (BUILT_IN_FFSIMAX, "ffsimax", BT_FN_INT_INTMAX, ATTR_CONST_NOTHROW_LEAF_LIST) -DEF_EXT_LIB_BUILTIN (BUILT_IN_FFSL, "ffsl", BT_FN_INT_LONG, ATTR_CONST_NOTHROW_LEAF_LIST) -DEF_EXT_LIB_BUILTIN (BUILT_IN_FFSLL, "ffsll", BT_FN_INT_LONGLONG, ATTR_CONST_NOTHROW_LEAF_LIST) -DEF_EXT_LIB_BUILTIN (BUILT_IN_FORK, "fork", BT_FN_PID, ATTR_NOTHROW_LIST) -DEF_GCC_BUILTIN (BUILT_IN_FRAME_ADDRESS, "frame_address", BT_FN_PTR_UINT, ATTR_NULL) -/* [trans-mem]: Adjust BUILT_IN_TM_FREE if BUILT_IN_FREE is changed. */ -DEF_LIB_BUILTIN (BUILT_IN_FREE, "free", BT_FN_VOID_PTR, ATTR_NOTHROW_LEAF_LIST) -DEF_GCC_BUILTIN (BUILT_IN_FROB_RETURN_ADDR, "frob_return_addr", BT_FN_PTR_PTR, ATTR_NULL) -DEF_EXT_LIB_BUILTIN (BUILT_IN_GETTEXT, "gettext", BT_FN_STRING_CONST_STRING, ATTR_FORMAT_ARG_1) -DEF_C99_BUILTIN (BUILT_IN_IMAXABS, "imaxabs", BT_FN_INTMAX_INTMAX, ATTR_CONST_NOTHROW_LEAF_LIST) -DEF_GCC_BUILTIN (BUILT_IN_INIT_DWARF_REG_SIZES, "init_dwarf_reg_size_table", BT_FN_VOID_PTR, ATTR_NULL) -DEF_EXT_LIB_BUILTIN (BUILT_IN_FINITE, "finite", BT_FN_INT_DOUBLE, ATTR_CONST_NOTHROW_LEAF_LIST) -DEF_EXT_LIB_BUILTIN (BUILT_IN_FINITEF, "finitef", BT_FN_INT_FLOAT, ATTR_CONST_NOTHROW_LEAF_LIST) -DEF_EXT_LIB_BUILTIN (BUILT_IN_FINITEL, "finitel", BT_FN_INT_LONGDOUBLE, ATTR_CONST_NOTHROW_LEAF_LIST) -DEF_EXT_LIB_BUILTIN (BUILT_IN_FINITED32, "finited32", BT_FN_INT_DFLOAT32, ATTR_CONST_NOTHROW_LEAF_LIST) -DEF_EXT_LIB_BUILTIN (BUILT_IN_FINITED64, "finited64", BT_FN_INT_DFLOAT64, ATTR_CONST_NOTHROW_LEAF_LIST) -DEF_EXT_LIB_BUILTIN (BUILT_IN_FINITED128, "finited128", BT_FN_INT_DFLOAT128, ATTR_CONST_NOTHROW_LEAF_LIST) -DEF_GCC_BUILTIN (BUILT_IN_FPCLASSIFY, "fpclassify", BT_FN_INT_INT_INT_INT_INT_INT_VAR, ATTR_CONST_NOTHROW_TYPEGENERIC_LEAF) -DEF_GCC_BUILTIN (BUILT_IN_ISFINITE, "isfinite", BT_FN_INT_VAR, ATTR_CONST_NOTHROW_TYPEGENERIC_LEAF) -DEF_GCC_BUILTIN (BUILT_IN_ISINF_SIGN, "isinf_sign", BT_FN_INT_VAR, ATTR_CONST_NOTHROW_TYPEGENERIC_LEAF) -DEF_C99_C90RES_BUILTIN (BUILT_IN_ISINF, "isinf", BT_FN_INT_VAR, ATTR_CONST_NOTHROW_TYPEGENERIC) -DEF_EXT_LIB_BUILTIN (BUILT_IN_ISINFF, "isinff", BT_FN_INT_FLOAT, ATTR_CONST_NOTHROW_LEAF_LIST) -DEF_EXT_LIB_BUILTIN (BUILT_IN_ISINFL, "isinfl", BT_FN_INT_LONGDOUBLE, ATTR_CONST_NOTHROW_LEAF_LIST) -DEF_EXT_LIB_BUILTIN (BUILT_IN_ISINFD32, "isinfd32", BT_FN_INT_DFLOAT32, ATTR_CONST_NOTHROW_LEAF_LIST) -DEF_EXT_LIB_BUILTIN (BUILT_IN_ISINFD64, "isinfd64", BT_FN_INT_DFLOAT64, ATTR_CONST_NOTHROW_LEAF_LIST) -DEF_EXT_LIB_BUILTIN (BUILT_IN_ISINFD128, "isinfd128", BT_FN_INT_DFLOAT128, ATTR_CONST_NOTHROW_LEAF_LIST) -DEF_C99_C90RES_BUILTIN (BUILT_IN_ISNAN, "isnan", BT_FN_INT_VAR, ATTR_CONST_NOTHROW_TYPEGENERIC_LEAF) -DEF_EXT_LIB_BUILTIN (BUILT_IN_ISNANF, "isnanf", BT_FN_INT_FLOAT, ATTR_CONST_NOTHROW_LEAF_LIST) -DEF_EXT_LIB_BUILTIN (BUILT_IN_ISNANL, "isnanl", BT_FN_INT_LONGDOUBLE, ATTR_CONST_NOTHROW_LEAF_LIST) -DEF_EXT_LIB_BUILTIN (BUILT_IN_ISNAND32, "isnand32", BT_FN_INT_DFLOAT32, ATTR_CONST_NOTHROW_LEAF_LIST) -DEF_EXT_LIB_BUILTIN (BUILT_IN_ISNAND64, "isnand64", BT_FN_INT_DFLOAT64, ATTR_CONST_NOTHROW_LEAF_LIST) -DEF_EXT_LIB_BUILTIN (BUILT_IN_ISNAND128, "isnand128", BT_FN_INT_DFLOAT128, ATTR_CONST_NOTHROW_LEAF_LIST) -DEF_GCC_BUILTIN (BUILT_IN_ISNORMAL, "isnormal", BT_FN_INT_VAR, ATTR_CONST_NOTHROW_TYPEGENERIC_LEAF) -DEF_GCC_BUILTIN (BUILT_IN_ISGREATER, "isgreater", BT_FN_INT_VAR, ATTR_CONST_NOTHROW_TYPEGENERIC_LEAF) -DEF_GCC_BUILTIN (BUILT_IN_ISGREATEREQUAL, "isgreaterequal", BT_FN_INT_VAR, ATTR_CONST_NOTHROW_TYPEGENERIC_LEAF) -DEF_GCC_BUILTIN (BUILT_IN_ISLESS, "isless", BT_FN_INT_VAR, ATTR_CONST_NOTHROW_TYPEGENERIC_LEAF) -DEF_GCC_BUILTIN (BUILT_IN_ISLESSEQUAL, "islessequal", BT_FN_INT_VAR, ATTR_CONST_NOTHROW_TYPEGENERIC_LEAF) -DEF_GCC_BUILTIN (BUILT_IN_ISLESSGREATER, "islessgreater", BT_FN_INT_VAR, ATTR_CONST_NOTHROW_TYPEGENERIC_LEAF) -DEF_GCC_BUILTIN (BUILT_IN_ISUNORDERED, "isunordered", BT_FN_INT_VAR, ATTR_CONST_NOTHROW_TYPEGENERIC_LEAF) -DEF_LIB_BUILTIN (BUILT_IN_LABS, "labs", BT_FN_LONG_LONG, ATTR_CONST_NOTHROW_LEAF_LIST) -DEF_C99_BUILTIN (BUILT_IN_LLABS, "llabs", BT_FN_LONGLONG_LONGLONG, ATTR_CONST_NOTHROW_LEAF_LIST) -DEF_GCC_BUILTIN (BUILT_IN_LONGJMP, "longjmp", BT_FN_VOID_PTR_INT, ATTR_NORETURN_NOTHROW_LIST) -/* [trans-mem]: Adjust BUILT_IN_TM_MALLOC if BUILT_IN_MALLOC is changed. */ -DEF_LIB_BUILTIN (BUILT_IN_MALLOC, "malloc", BT_FN_PTR_SIZE, ATTR_MALLOC_NOTHROW_LEAF_LIST) -DEF_GCC_BUILTIN (BUILT_IN_NEXT_ARG, "next_arg", BT_FN_PTR_VAR, ATTR_LEAF_LIST) -DEF_GCC_BUILTIN (BUILT_IN_PARITY, "parity", BT_FN_INT_UINT, ATTR_CONST_NOTHROW_LEAF_LIST) -DEF_GCC_BUILTIN (BUILT_IN_PARITYIMAX, "parityimax", BT_FN_INT_UINTMAX, ATTR_CONST_NOTHROW_LEAF_LIST) -DEF_GCC_BUILTIN (BUILT_IN_PARITYL, "parityl", BT_FN_INT_ULONG, ATTR_CONST_NOTHROW_LEAF_LIST) -DEF_GCC_BUILTIN (BUILT_IN_PARITYLL, "parityll", BT_FN_INT_ULONGLONG, ATTR_CONST_NOTHROW_LEAF_LIST) -DEF_GCC_BUILTIN (BUILT_IN_POPCOUNT, "popcount", BT_FN_INT_UINT, ATTR_CONST_NOTHROW_LEAF_LIST) -DEF_GCC_BUILTIN (BUILT_IN_POPCOUNTIMAX, "popcountimax", BT_FN_INT_UINTMAX, ATTR_CONST_NOTHROW_LEAF_LIST) -DEF_GCC_BUILTIN (BUILT_IN_POPCOUNTL, "popcountl", BT_FN_INT_ULONG, ATTR_CONST_NOTHROW_LEAF_LIST) -DEF_GCC_BUILTIN (BUILT_IN_POPCOUNTLL, "popcountll", BT_FN_INT_ULONGLONG, ATTR_CONST_NOTHROW_LEAF_LIST) -DEF_EXT_LIB_BUILTIN (BUILT_IN_POSIX_MEMALIGN, "posix_memalign", BT_FN_INT_PTRPTR_SIZE_SIZE, ATTR_NOTHROW_NONNULL_LEAF) -DEF_GCC_BUILTIN (BUILT_IN_PREFETCH, "prefetch", BT_FN_VOID_CONST_PTR_VAR, ATTR_NOVOPS_LEAF_LIST) -DEF_LIB_BUILTIN (BUILT_IN_REALLOC, "realloc", BT_FN_PTR_PTR_SIZE, ATTR_NOTHROW_LEAF_LIST) -DEF_GCC_BUILTIN (BUILT_IN_RETURN, "return", BT_FN_VOID_PTR, ATTR_NORETURN_NOTHROW_LEAF_LIST) -DEF_GCC_BUILTIN (BUILT_IN_RETURN_ADDRESS, "return_address", BT_FN_PTR_UINT, ATTR_LEAF_LIST) -DEF_GCC_BUILTIN (BUILT_IN_SAVEREGS, "saveregs", BT_FN_PTR_VAR, ATTR_NULL) -DEF_GCC_BUILTIN (BUILT_IN_SETJMP, "setjmp", BT_FN_INT_PTR, ATTR_NOTHROW_LEAF_LIST) -DEF_EXT_LIB_BUILTIN (BUILT_IN_STRFMON, "strfmon", BT_FN_SSIZE_STRING_SIZE_CONST_STRING_VAR, ATTR_FORMAT_STRFMON_NOTHROW_3_4) -DEF_LIB_BUILTIN (BUILT_IN_STRFTIME, "strftime", BT_FN_SIZE_STRING_SIZE_CONST_STRING_CONST_PTR, ATTR_FORMAT_STRFTIME_NOTHROW_3_0) -DEF_GCC_BUILTIN (BUILT_IN_TRAP, "trap", BT_FN_VOID, ATTR_NORETURN_NOTHROW_LEAF_LIST) -DEF_GCC_BUILTIN (BUILT_IN_UNREACHABLE, "unreachable", BT_FN_VOID, ATTR_CONST_NORETURN_NOTHROW_LEAF_LIST) -DEF_GCC_BUILTIN (BUILT_IN_UNWIND_INIT, "unwind_init", BT_FN_VOID, ATTR_NULL) -DEF_GCC_BUILTIN (BUILT_IN_UPDATE_SETJMP_BUF, "update_setjmp_buf", BT_FN_VOID_PTR_INT, ATTR_NULL) -DEF_GCC_BUILTIN (BUILT_IN_VA_COPY, "va_copy", BT_FN_VOID_VALIST_REF_VALIST_ARG, ATTR_NOTHROW_LEAF_LIST) -DEF_GCC_BUILTIN (BUILT_IN_VA_END, "va_end", BT_FN_VOID_VALIST_REF, ATTR_NOTHROW_LEAF_LIST) -DEF_GCC_BUILTIN (BUILT_IN_VA_START, "va_start", BT_FN_VOID_VALIST_REF_VAR, ATTR_NOTHROW_LEAF_LIST) -DEF_GCC_BUILTIN (BUILT_IN_VA_ARG_PACK, "va_arg_pack", BT_FN_INT, ATTR_PURE_NOTHROW_LEAF_LIST) -DEF_GCC_BUILTIN (BUILT_IN_VA_ARG_PACK_LEN, "va_arg_pack_len", BT_FN_INT, ATTR_PURE_NOTHROW_LEAF_LIST) -DEF_EXT_LIB_BUILTIN (BUILT_IN__EXIT, "_exit", BT_FN_VOID_INT, ATTR_NORETURN_NOTHROW_LEAF_LIST) -DEF_C99_BUILTIN (BUILT_IN__EXIT2, "_Exit", BT_FN_VOID_INT, ATTR_NORETURN_NOTHROW_LEAF_LIST) - -/* Implementing nested functions. */ -DEF_BUILTIN_STUB (BUILT_IN_INIT_TRAMPOLINE, "__builtin_init_trampoline") -DEF_BUILTIN_STUB (BUILT_IN_INIT_HEAP_TRAMPOLINE, "__builtin_init_heap_trampoline") -DEF_BUILTIN_STUB (BUILT_IN_ADJUST_TRAMPOLINE, "__builtin_adjust_trampoline") -DEF_BUILTIN_STUB (BUILT_IN_NONLOCAL_GOTO, "__builtin_nonlocal_goto") - -/* Implementing __builtin_setjmp. */ -DEF_BUILTIN_STUB (BUILT_IN_SETJMP_SETUP, "__builtin_setjmp_setup") -DEF_BUILTIN_STUB (BUILT_IN_SETJMP_RECEIVER, "__builtin_setjmp_receiver") - -/* Implementing variable sized local variables. */ -DEF_BUILTIN_STUB (BUILT_IN_STACK_SAVE, "__builtin_stack_save") -DEF_BUILTIN_STUB (BUILT_IN_STACK_RESTORE, "__builtin_stack_restore") -DEF_BUILTIN_STUB (BUILT_IN_ALLOCA_WITH_ALIGN, "__builtin_alloca_with_align") - -/* Object size checking builtins. */ -DEF_GCC_BUILTIN (BUILT_IN_OBJECT_SIZE, "object_size", BT_FN_SIZE_CONST_PTR_INT, ATTR_PURE_NOTHROW_LEAF_LIST) -DEF_EXT_LIB_BUILTIN_CHKP (BUILT_IN_MEMCPY_CHK, "__memcpy_chk", BT_FN_PTR_PTR_CONST_PTR_SIZE_SIZE, ATTR_RET1_NOTHROW_NONNULL_LEAF) -DEF_EXT_LIB_BUILTIN_CHKP (BUILT_IN_MEMMOVE_CHK, "__memmove_chk", BT_FN_PTR_PTR_CONST_PTR_SIZE_SIZE, ATTR_RET1_NOTHROW_NONNULL_LEAF) -DEF_EXT_LIB_BUILTIN_CHKP (BUILT_IN_MEMPCPY_CHK, "__mempcpy_chk", BT_FN_PTR_PTR_CONST_PTR_SIZE_SIZE, ATTR_NOTHROW_NONNULL_LEAF) -DEF_EXT_LIB_BUILTIN_CHKP (BUILT_IN_MEMSET_CHK, "__memset_chk", BT_FN_PTR_PTR_INT_SIZE_SIZE, ATTR_NOTHROW_NONNULL_LEAF) -DEF_EXT_LIB_BUILTIN_CHKP (BUILT_IN_STPCPY_CHK, "__stpcpy_chk", BT_FN_STRING_STRING_CONST_STRING_SIZE, ATTR_NOTHROW_NONNULL_LEAF) -DEF_EXT_LIB_BUILTIN (BUILT_IN_STPNCPY_CHK, "__stpncpy_chk", BT_FN_STRING_STRING_CONST_STRING_SIZE_SIZE, ATTR_NOTHROW_NONNULL_LEAF) -DEF_EXT_LIB_BUILTIN_CHKP (BUILT_IN_STRCAT_CHK, "__strcat_chk", BT_FN_STRING_STRING_CONST_STRING_SIZE, ATTR_NOTHROW_NONNULL_LEAF) -DEF_EXT_LIB_BUILTIN_CHKP (BUILT_IN_STRCPY_CHK, "__strcpy_chk", BT_FN_STRING_STRING_CONST_STRING_SIZE, ATTR_NOTHROW_NONNULL_LEAF) -DEF_EXT_LIB_BUILTIN (BUILT_IN_STRNCAT_CHK, "__strncat_chk", BT_FN_STRING_STRING_CONST_STRING_SIZE_SIZE, ATTR_NOTHROW_NONNULL_LEAF) -DEF_EXT_LIB_BUILTIN (BUILT_IN_STRNCPY_CHK, "__strncpy_chk", BT_FN_STRING_STRING_CONST_STRING_SIZE_SIZE, ATTR_NOTHROW_NONNULL_LEAF) -DEF_EXT_LIB_BUILTIN (BUILT_IN_SNPRINTF_CHK, "__snprintf_chk", BT_FN_INT_STRING_SIZE_INT_SIZE_CONST_STRING_VAR, ATTR_FORMAT_PRINTF_NOTHROW_5_6) -DEF_EXT_LIB_BUILTIN (BUILT_IN_SPRINTF_CHK, "__sprintf_chk", BT_FN_INT_STRING_INT_SIZE_CONST_STRING_VAR, ATTR_FORMAT_PRINTF_NOTHROW_4_5) -DEF_EXT_LIB_BUILTIN (BUILT_IN_VSNPRINTF_CHK, "__vsnprintf_chk", BT_FN_INT_STRING_SIZE_INT_SIZE_CONST_STRING_VALIST_ARG, ATTR_FORMAT_PRINTF_NOTHROW_5_0) -DEF_EXT_LIB_BUILTIN (BUILT_IN_VSPRINTF_CHK, "__vsprintf_chk", BT_FN_INT_STRING_INT_SIZE_CONST_STRING_VALIST_ARG, ATTR_FORMAT_PRINTF_NOTHROW_4_0) -DEF_EXT_LIB_BUILTIN (BUILT_IN_FPRINTF_CHK, "__fprintf_chk", BT_FN_INT_FILEPTR_INT_CONST_STRING_VAR, ATTR_FORMAT_PRINTF_3_4) -DEF_EXT_LIB_BUILTIN (BUILT_IN_PRINTF_CHK, "__printf_chk", BT_FN_INT_INT_CONST_STRING_VAR, ATTR_FORMAT_PRINTF_2_3) -DEF_EXT_LIB_BUILTIN (BUILT_IN_VFPRINTF_CHK, "__vfprintf_chk", BT_FN_INT_FILEPTR_INT_CONST_STRING_VALIST_ARG, ATTR_FORMAT_PRINTF_3_0) -DEF_EXT_LIB_BUILTIN (BUILT_IN_VPRINTF_CHK, "__vprintf_chk", BT_FN_INT_INT_CONST_STRING_VALIST_ARG, ATTR_FORMAT_PRINTF_2_0) - -/* Profiling hooks. */ -DEF_BUILTIN (BUILT_IN_PROFILE_FUNC_ENTER, "__cyg_profile_func_enter", BUILT_IN_NORMAL, BT_FN_VOID_PTR_PTR, BT_LAST, - false, false, false, ATTR_NULL, true, true) -DEF_BUILTIN (BUILT_IN_PROFILE_FUNC_EXIT, "__cyg_profile_func_exit", BUILT_IN_NORMAL, BT_FN_VOID_PTR_PTR, BT_LAST, - false, false, false, ATTR_NULL, true, true) - -/* TLS thread pointer related builtins. */ -DEF_BUILTIN (BUILT_IN_THREAD_POINTER, "__builtin_thread_pointer", - BUILT_IN_NORMAL, BT_FN_PTR, BT_LAST, - false, false, true, ATTR_CONST_NOTHROW_LIST, true, - targetm.have_tls) - -DEF_BUILTIN (BUILT_IN_SET_THREAD_POINTER, "__builtin_set_thread_pointer", - BUILT_IN_NORMAL, BT_FN_VOID_PTR, BT_LAST, - false, false, true, ATTR_NOTHROW_LIST, true, - targetm.have_tls) - -/* TLS emulation. */ -DEF_BUILTIN (BUILT_IN_EMUTLS_GET_ADDRESS, targetm.emutls.get_address, - BUILT_IN_NORMAL, - BT_FN_PTR_PTR, BT_FN_PTR_PTR, - true, true, true, ATTR_CONST_NOTHROW_NONNULL_LEAF, false, - !targetm.have_tls) -DEF_BUILTIN (BUILT_IN_EMUTLS_REGISTER_COMMON, - targetm.emutls.register_common, BUILT_IN_NORMAL, - BT_FN_VOID_PTR_WORD_WORD_PTR, BT_FN_VOID_PTR_WORD_WORD_PTR, - true, true, true, ATTR_NOTHROW_LEAF_LIST, false, - !targetm.have_tls) - -/* Exception support. */ -DEF_BUILTIN_STUB (BUILT_IN_UNWIND_RESUME, "__builtin_unwind_resume") -DEF_BUILTIN_STUB (BUILT_IN_CXA_END_CLEANUP, "__builtin_cxa_end_cleanup") -DEF_BUILTIN_STUB (BUILT_IN_EH_POINTER, "__builtin_eh_pointer") -DEF_BUILTIN_STUB (BUILT_IN_EH_FILTER, "__builtin_eh_filter") -DEF_BUILTIN_STUB (BUILT_IN_EH_COPY_VALUES, "__builtin_eh_copy_values") - -/* __FILE__, __LINE__, __FUNCTION__ as builtins. */ -DEF_GCC_BUILTIN (BUILT_IN_FILE, "FILE", BT_FN_CONST_STRING, ATTR_NOTHROW_LEAF_LIST) -DEF_GCC_BUILTIN (BUILT_IN_FUNCTION, "FUNCTION", BT_FN_CONST_STRING, ATTR_NOTHROW_LEAF_LIST) -DEF_GCC_BUILTIN (BUILT_IN_LINE, "LINE", BT_FN_INT, ATTR_NOTHROW_LEAF_LIST) - -/* Synchronization Primitives. */ -#include "sync-builtins.def" - -/* Offloading and Multi Processing builtins. */ -#include "omp-builtins.def" - -/* Cilk keywords builtins. */ -#include "cilk-builtins.def" - -/* GTM builtins. */ -#include "gtm-builtins.def" - -/* Sanitizer builtins. */ -#include "sanitizer.def" - -/* Cilk Plus builtins. */ -#include "cilkplus.def" - -/* Pointer Bounds Checker builtins. */ -#include "chkp-builtins.def" diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/builtins.h b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/builtins.h deleted file mode 100644 index cf2ddb4..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/builtins.h +++ /dev/null @@ -1,98 +0,0 @@ -/* Expand builtin functions. - Copyright (C) 1988-2015 Free Software Foundation, Inc. - -This file is part of GCC. - -GCC is free software; you can redistribute it and/or modify it under -the terms of the GNU General Public License as published by the Free -Software Foundation; either version 3, or (at your option) any later -version. - -GCC is distributed in the hope that it will be useful, but WITHOUT ANY -WARRANTY; without even the implied warranty of MERCHANTABILITY or -FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -for more details. - -You should have received a copy of the GNU General Public License -along with GCC; see the file COPYING3. If not see -. */ - -#ifndef GCC_BUILTINS_H -#define GCC_BUILTINS_H - -#include - -/* Target-dependent globals. */ -struct target_builtins { - /* For each register that may be used for calling a function, this - gives a mode used to copy the register's value. VOIDmode indicates - the register is not used for calling a function. If the machine - has register windows, this gives only the outbound registers. - INCOMING_REGNO gives the corresponding inbound register. */ - machine_mode x_apply_args_mode[FIRST_PSEUDO_REGISTER]; - - /* For each register that may be used for returning values, this gives - a mode used to copy the register's value. VOIDmode indicates the - register is not used for returning values. If the machine has - register windows, this gives only the outbound registers. - INCOMING_REGNO gives the corresponding inbound register. */ - machine_mode x_apply_result_mode[FIRST_PSEUDO_REGISTER]; -}; - -extern struct target_builtins default_target_builtins; -#if SWITCHABLE_TARGET -extern struct target_builtins *this_target_builtins; -#else -#define this_target_builtins (&default_target_builtins) -#endif - -/* Non-zero if __builtin_constant_p should be folded right away. */ -extern bool force_folding_builtin_constant_p; - -extern bool is_builtin_fn (tree); -extern bool get_object_alignment_1 (tree, unsigned int *, - unsigned HOST_WIDE_INT *); -extern unsigned int get_object_alignment (tree); -extern bool get_pointer_alignment_1 (tree, unsigned int *, - unsigned HOST_WIDE_INT *); -extern unsigned int get_pointer_alignment (tree); -extern tree c_strlen (tree, int); -extern void expand_builtin_setjmp_setup (rtx, rtx); -extern void expand_builtin_setjmp_receiver (rtx); -extern tree mathfn_built_in (tree, enum built_in_function fn); -extern rtx builtin_strncpy_read_str (void *, HOST_WIDE_INT, machine_mode); -extern rtx builtin_memset_read_str (void *, HOST_WIDE_INT, machine_mode); -extern rtx expand_builtin_saveregs (void); -extern tree std_build_builtin_va_list (void); -extern tree std_fn_abi_va_list (tree); -extern tree std_canonical_va_list_type (tree); -extern void std_expand_builtin_va_start (tree, rtx); -extern void expand_builtin_trap (void); -extern rtx expand_builtin (tree, rtx, rtx, machine_mode, int); -extern rtx expand_builtin_with_bounds (tree, rtx, rtx, machine_mode, int); -extern enum built_in_function builtin_mathfn_code (const_tree); -extern tree fold_builtin_expect (location_t, tree, tree, tree); -extern tree fold_fma (location_t, tree, tree, tree, tree); -extern bool avoid_folding_inline_builtin (tree); -extern tree fold_call_expr (location_t, tree, bool); -extern tree fold_builtin_call_array (location_t, tree, tree, int, tree *); -extern tree fold_builtin_n (location_t, tree, tree *, int, bool); -extern bool validate_gimple_arglist (const gcall *, ...); -extern rtx default_expand_builtin (tree, rtx, rtx, machine_mode, int); -extern bool fold_builtin_next_arg (tree, bool); -extern tree do_mpc_arg2 (tree, tree, tree, int, int (*)(mpc_ptr, mpc_srcptr, mpc_srcptr, mpc_rnd_t)); -extern tree fold_call_stmt (gcall *, bool); -extern void set_builtin_user_assembler_name (tree decl, const char *asmspec); -extern bool is_simple_builtin (tree); -extern bool is_inexpensive_builtin (tree); - -extern bool readonly_data_expr (tree exp); -extern const char *c_getstr (tree); -extern bool init_target_chars (void); -extern unsigned HOST_WIDE_INT target_newline; -extern unsigned HOST_WIDE_INT target_percent; -extern char target_percent_s[3]; -extern char target_percent_c[3]; -extern char target_percent_s_newline[4]; - -#endif diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/bversion.h b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/bversion.h deleted file mode 100644 index d1f4aaa..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/bversion.h +++ /dev/null @@ -1,4 +0,0 @@ -#define BUILDING_GCC_MAJOR 5 -#define BUILDING_GCC_MINOR 4 -#define BUILDING_GCC_PATCHLEVEL 0 -#define BUILDING_GCC_VERSION (BUILDING_GCC_MAJOR * 1000 + BUILDING_GCC_MINOR) diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/c-family/c-common.def b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/c-family/c-common.def deleted file mode 100644 index cd2c6b1..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/c-family/c-common.def +++ /dev/null @@ -1,69 +0,0 @@ -/* This file contains the definitions and documentation for the - additional tree codes used in the GNU C compiler (see tree.def - for the standard codes). - Copyright (C) 1987-2015 Free Software Foundation, Inc. - Written by Benjamin Chelf - -This file is part of GCC. - -GCC is free software; you can redistribute it and/or modify it under -the terms of the GNU General Public License as published by the Free -Software Foundation; either version 3, or (at your option) any later -version. - -GCC is distributed in the hope that it will be useful, but WITHOUT ANY -WARRANTY; without even the implied warranty of MERCHANTABILITY or -FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -for more details. - -You should have received a copy of the GNU General Public License -along with GCC; see the file COPYING3. If not see -. */ - -/* Tree nodes used in the C frontend. These are also shared with the - C++ and Objective C frontends. */ - -/* A C_MAYBE_CONST_EXPR, currently only used for C and Objective C, - tracks information about constancy of an expression and VLA type - sizes or VM expressions from typeof that need to be evaluated - before the main expression. It is used during parsing and removed - in c_fully_fold. C_MAYBE_CONST_EXPR_PRE is the expression to - evaluate first, if not NULL; C_MAYBE_CONST_EXPR_EXPR is the main - expression. If C_MAYBE_CONST_EXPR_INT_OPERANDS is set then the - expression may be used in an unevaluated part of an integer - constant expression, but not in an evaluated part. If - C_MAYBE_CONST_EXPR_NON_CONST is set then the expression contains - something that cannot occur in an evaluated part of a constant - expression (or outside of sizeof in C90 mode); otherwise it does - not. */ -DEFTREECODE (C_MAYBE_CONST_EXPR, "c_maybe_const_expr", tcc_expression, 2) - -/* An EXCESS_PRECISION_EXPR, currently only used for C and Objective - C, represents an expression evaluated in greater range or precision - than its type. The type of the EXCESS_PRECISION_EXPR is the - semantic type while the operand represents what is actually being - evaluated. */ -DEFTREECODE (EXCESS_PRECISION_EXPR, "excess_precision_expr", tcc_expression, 1) - -/* Used to represent a user-defined literal. - The operands are an IDENTIFIER for the suffix, the VALUE of the literal, - and for numeric literals the original string representation of the - number. */ -DEFTREECODE (USERDEF_LITERAL, "userdef_literal", tcc_exceptional, 3) - -/* Represents a 'sizeof' expression during C++ template expansion, - or for the purpose of -Wsizeof-pointer-memaccess warning. */ -DEFTREECODE (SIZEOF_EXPR, "sizeof_expr", tcc_expression, 1) - -/* Array Notation expression. - Operand 0 is the array. - Operand 1 is the starting array index. - Operand 2 contains the number of elements you need to access. - Operand 3 is the stride. */ -DEFTREECODE (ARRAY_NOTATION_REF, "array_notation_ref", tcc_reference, 4) - -/* -Local variables: -mode:c -End: -*/ diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/c-family/c-common.h b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/c-family/c-common.h deleted file mode 100644 index fdb227f..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/c-family/c-common.h +++ /dev/null @@ -1,1440 +0,0 @@ -/* Definitions for c-common.c. - Copyright (C) 1987-2015 Free Software Foundation, Inc. - -This file is part of GCC. - -GCC is free software; you can redistribute it and/or modify it under -the terms of the GNU General Public License as published by the Free -Software Foundation; either version 3, or (at your option) any later -version. - -GCC is distributed in the hope that it will be useful, but WITHOUT ANY -WARRANTY; without even the implied warranty of MERCHANTABILITY or -FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -for more details. - -You should have received a copy of the GNU General Public License -along with GCC; see the file COPYING3. If not see -. */ - -#ifndef GCC_C_COMMON_H -#define GCC_C_COMMON_H - -#include "splay-tree.h" -#include "cpplib.h" -#include "ggc.h" -#include "hashtab.h" -#include "hash-set.h" -#include "machmode.h" -#include "input.h" -#include "statistics.h" -#include "vec.h" -#include "double-int.h" -#include "real.h" -#include "fixed-value.h" -#include "alias.h" -#include "flags.h" -#include "symtab.h" -#include "wide-int.h" -#include "inchash.h" -#include "tree.h" -#include "fold-const.h" - -/* In order for the format checking to accept the C frontend - diagnostic framework extensions, you must include this file before - diagnostic-core.h, not after. The C front end formats are a subset of those - for C++, so they are the appropriate set to use in common code; - cp-tree.h overrides this for C++. */ -#if defined(GCC_DIAGNOSTIC_CORE_H) -#error \ -In order for the format checking to accept the C front end diagnostic \ -framework extensions, you must include this file before diagnostic-core.h \ -never after. -#endif -#ifndef GCC_DIAG_STYLE -#define GCC_DIAG_STYLE __gcc_cdiag__ -#endif -#include "diagnostic-core.h" - -/* Usage of TREE_LANG_FLAG_?: - 0: IDENTIFIER_MARKED (used by search routines). - C_MAYBE_CONST_EXPR_INT_OPERANDS (in C_MAYBE_CONST_EXPR, for C) - 1: C_DECLARED_LABEL_FLAG (in LABEL_DECL) - STATEMENT_LIST_STMT_EXPR (in STATEMENT_LIST) - C_MAYBE_CONST_EXPR_NON_CONST (in C_MAYBE_CONST_EXPR, for C) - 2: unused - 3: STATEMENT_LIST_HAS_LABEL (in STATEMENT_LIST) - 4: unused -*/ - -/* Reserved identifiers. This is the union of all the keywords for C, - C++, and Objective-C. All the type modifiers have to be in one - block at the beginning, because they are used as mask bits. There - are 28 type modifiers; if we add many more we will have to redesign - the mask mechanism. */ - -enum rid -{ - /* Modifiers: */ - /* C, in empirical order of frequency. */ - RID_STATIC = 0, - RID_UNSIGNED, RID_LONG, RID_CONST, RID_EXTERN, - RID_REGISTER, RID_TYPEDEF, RID_SHORT, RID_INLINE, - RID_VOLATILE, RID_SIGNED, RID_AUTO, RID_RESTRICT, - RID_NORETURN, RID_ATOMIC, - - /* C extensions */ - RID_COMPLEX, RID_THREAD, RID_SAT, - - /* C++ */ - RID_FRIEND, RID_VIRTUAL, RID_EXPLICIT, RID_EXPORT, RID_MUTABLE, - - /* ObjC ("PQ" reserved words - they do not appear after a '@' and - are keywords only in specific contexts) */ - RID_IN, RID_OUT, RID_INOUT, RID_BYCOPY, RID_BYREF, RID_ONEWAY, - - /* ObjC ("PATTR" reserved words - they do not appear after a '@' - and are keywords only as property attributes) */ - RID_GETTER, RID_SETTER, - RID_READONLY, RID_READWRITE, - RID_ASSIGN, RID_RETAIN, RID_COPY, - RID_NONATOMIC, - - /* C (reserved and imaginary types not implemented, so any use is a - syntax error) */ - RID_IMAGINARY, - - /* C */ - RID_INT, RID_CHAR, RID_FLOAT, RID_DOUBLE, RID_VOID, - RID_ENUM, RID_STRUCT, RID_UNION, RID_IF, RID_ELSE, - RID_WHILE, RID_DO, RID_FOR, RID_SWITCH, RID_CASE, - RID_DEFAULT, RID_BREAK, RID_CONTINUE, RID_RETURN, RID_GOTO, - RID_SIZEOF, - - /* C extensions */ - RID_ASM, RID_TYPEOF, RID_ALIGNOF, RID_ATTRIBUTE, RID_VA_ARG, - RID_EXTENSION, RID_IMAGPART, RID_REALPART, RID_LABEL, RID_CHOOSE_EXPR, - RID_TYPES_COMPATIBLE_P, RID_BUILTIN_COMPLEX, RID_BUILTIN_SHUFFLE, - RID_DFLOAT32, RID_DFLOAT64, RID_DFLOAT128, - RID_FRACT, RID_ACCUM, RID_AUTO_TYPE, RID_BUILTIN_CALL_WITH_STATIC_CHAIN, - - /* C11 */ - RID_ALIGNAS, RID_GENERIC, - - /* This means to warn that this is a C++ keyword, and then treat it - as a normal identifier. */ - RID_CXX_COMPAT_WARN, - - /* GNU transactional memory extension */ - RID_TRANSACTION_ATOMIC, RID_TRANSACTION_RELAXED, RID_TRANSACTION_CANCEL, - - /* Too many ways of getting the name of a function as a string */ - RID_FUNCTION_NAME, RID_PRETTY_FUNCTION_NAME, RID_C99_FUNCTION_NAME, - - /* C++ (some of these are keywords in Objective-C as well, but only - if they appear after a '@') */ - RID_BOOL, RID_WCHAR, RID_CLASS, - RID_PUBLIC, RID_PRIVATE, RID_PROTECTED, - RID_TEMPLATE, RID_NULL, RID_CATCH, - RID_DELETE, RID_FALSE, RID_NAMESPACE, - RID_NEW, RID_OFFSETOF, RID_OPERATOR, - RID_THIS, RID_THROW, RID_TRUE, - RID_TRY, RID_TYPENAME, RID_TYPEID, - RID_USING, RID_CHAR16, RID_CHAR32, - - /* casts */ - RID_CONSTCAST, RID_DYNCAST, RID_REINTCAST, RID_STATCAST, - - /* C++ extensions */ - RID_BASES, RID_DIRECT_BASES, - RID_HAS_NOTHROW_ASSIGN, RID_HAS_NOTHROW_CONSTRUCTOR, - RID_HAS_NOTHROW_COPY, RID_HAS_TRIVIAL_ASSIGN, - RID_HAS_TRIVIAL_CONSTRUCTOR, RID_HAS_TRIVIAL_COPY, - RID_HAS_TRIVIAL_DESTRUCTOR, RID_HAS_VIRTUAL_DESTRUCTOR, - RID_IS_ABSTRACT, RID_IS_BASE_OF, - RID_IS_CLASS, - RID_IS_EMPTY, RID_IS_ENUM, - RID_IS_FINAL, RID_IS_LITERAL_TYPE, - RID_IS_POD, RID_IS_POLYMORPHIC, - RID_IS_STD_LAYOUT, RID_IS_TRIVIAL, - RID_IS_TRIVIALLY_ASSIGNABLE, RID_IS_TRIVIALLY_CONSTRUCTIBLE, - RID_IS_TRIVIALLY_COPYABLE, - RID_IS_UNION, RID_UNDERLYING_TYPE, - - /* C++11 */ - RID_CONSTEXPR, RID_DECLTYPE, RID_NOEXCEPT, RID_NULLPTR, RID_STATIC_ASSERT, - - /* Cilk Plus keywords. */ - RID_CILK_SPAWN, RID_CILK_SYNC, RID_CILK_FOR, - - /* Objective-C ("AT" reserved words - they are only keywords when - they follow '@') */ - RID_AT_ENCODE, RID_AT_END, - RID_AT_CLASS, RID_AT_ALIAS, RID_AT_DEFS, - RID_AT_PRIVATE, RID_AT_PROTECTED, RID_AT_PUBLIC, RID_AT_PACKAGE, - RID_AT_PROTOCOL, RID_AT_SELECTOR, - RID_AT_THROW, RID_AT_TRY, RID_AT_CATCH, - RID_AT_FINALLY, RID_AT_SYNCHRONIZED, - RID_AT_OPTIONAL, RID_AT_REQUIRED, RID_AT_PROPERTY, - RID_AT_SYNTHESIZE, RID_AT_DYNAMIC, - RID_AT_INTERFACE, - RID_AT_IMPLEMENTATION, - - /* Named address support, mapping the keyword to a particular named address - number. Named address space 0 is reserved for the generic address. If - there are more than 254 named addresses, the addr_space_t type will need - to be grown from an unsigned char to unsigned short. */ - RID_ADDR_SPACE_0, /* generic address */ - RID_ADDR_SPACE_1, - RID_ADDR_SPACE_2, - RID_ADDR_SPACE_3, - RID_ADDR_SPACE_4, - RID_ADDR_SPACE_5, - RID_ADDR_SPACE_6, - RID_ADDR_SPACE_7, - RID_ADDR_SPACE_8, - RID_ADDR_SPACE_9, - RID_ADDR_SPACE_10, - RID_ADDR_SPACE_11, - RID_ADDR_SPACE_12, - RID_ADDR_SPACE_13, - RID_ADDR_SPACE_14, - RID_ADDR_SPACE_15, - - RID_FIRST_ADDR_SPACE = RID_ADDR_SPACE_0, - RID_LAST_ADDR_SPACE = RID_ADDR_SPACE_15, - - /* __intN keywords. The _N_M here doesn't correspond to the intN - in the keyword; use the bitsize in int_n_t_data_t[M] for that. - For example, if int_n_t_data_t[0].bitsize is 13, then RID_INT_N_0 - is for __int13. */ - - /* Note that the range to use is RID_FIRST_INT_N through - RID_FIRST_INT_N + NUM_INT_N_ENTS - 1 and c-parser.c has a list of - all RID_INT_N_* in a case statement. */ - - RID_INT_N_0, - RID_INT_N_1, - RID_INT_N_2, - RID_INT_N_3, - - RID_FIRST_INT_N = RID_INT_N_0, - RID_LAST_INT_N = RID_INT_N_3, - - RID_MAX, - - RID_FIRST_MODIFIER = RID_STATIC, - RID_LAST_MODIFIER = RID_ONEWAY, - - RID_FIRST_CXX0X = RID_CONSTEXPR, - RID_LAST_CXX0X = RID_STATIC_ASSERT, - RID_FIRST_AT = RID_AT_ENCODE, - RID_LAST_AT = RID_AT_IMPLEMENTATION, - RID_FIRST_PQ = RID_IN, - RID_LAST_PQ = RID_ONEWAY, - RID_FIRST_PATTR = RID_GETTER, - RID_LAST_PATTR = RID_NONATOMIC -}; - -#define OBJC_IS_AT_KEYWORD(rid) \ - ((unsigned int) (rid) >= (unsigned int) RID_FIRST_AT && \ - (unsigned int) (rid) <= (unsigned int) RID_LAST_AT) - -#define OBJC_IS_PQ_KEYWORD(rid) \ - ((unsigned int) (rid) >= (unsigned int) RID_FIRST_PQ && \ - (unsigned int) (rid) <= (unsigned int) RID_LAST_PQ) - -#define OBJC_IS_PATTR_KEYWORD(rid) \ - ((unsigned int) (rid) >= (unsigned int) RID_FIRST_PATTR && \ - (unsigned int) (rid) <= (unsigned int) RID_LAST_PATTR) - -/* OBJC_IS_CXX_KEYWORD recognizes the 'CXX_OBJC' keywords (such as - 'class') which are shared in a subtle way between Objective-C and - C++. When the lexer is lexing in Objective-C/Objective-C++, if it - finds '@' followed by one of these identifiers (eg, '@class'), it - recognizes the whole as an Objective-C keyword. If the identifier - is found elsewhere, it follows the rules of the C/C++ language. - */ -#define OBJC_IS_CXX_KEYWORD(rid) \ - (rid == RID_CLASS \ - || rid == RID_PUBLIC || rid == RID_PROTECTED || rid == RID_PRIVATE \ - || rid == RID_TRY || rid == RID_THROW || rid == RID_CATCH) - -/* The elements of `ridpointers' are identifier nodes for the reserved - type names and storage classes. It is indexed by a RID_... value. */ -extern GTY ((length ("(int) RID_MAX"))) tree *ridpointers; - -/* Standard named or nameless data types of the C compiler. */ - -enum c_tree_index -{ - CTI_CHAR16_TYPE, - CTI_CHAR32_TYPE, - CTI_WCHAR_TYPE, - CTI_UNDERLYING_WCHAR_TYPE, - CTI_WINT_TYPE, - CTI_SIGNED_SIZE_TYPE, /* For format checking only. */ - CTI_UNSIGNED_PTRDIFF_TYPE, /* For format checking only. */ - CTI_INTMAX_TYPE, - CTI_UINTMAX_TYPE, - CTI_WIDEST_INT_LIT_TYPE, - CTI_WIDEST_UINT_LIT_TYPE, - - /* Types for , that may not be defined on all - targets. */ - CTI_SIG_ATOMIC_TYPE, - CTI_INT8_TYPE, - CTI_INT16_TYPE, - CTI_INT32_TYPE, - CTI_INT64_TYPE, - CTI_UINT8_TYPE, - CTI_UINT16_TYPE, - CTI_UINT32_TYPE, - CTI_UINT64_TYPE, - CTI_INT_LEAST8_TYPE, - CTI_INT_LEAST16_TYPE, - CTI_INT_LEAST32_TYPE, - CTI_INT_LEAST64_TYPE, - CTI_UINT_LEAST8_TYPE, - CTI_UINT_LEAST16_TYPE, - CTI_UINT_LEAST32_TYPE, - CTI_UINT_LEAST64_TYPE, - CTI_INT_FAST8_TYPE, - CTI_INT_FAST16_TYPE, - CTI_INT_FAST32_TYPE, - CTI_INT_FAST64_TYPE, - CTI_UINT_FAST8_TYPE, - CTI_UINT_FAST16_TYPE, - CTI_UINT_FAST32_TYPE, - CTI_UINT_FAST64_TYPE, - CTI_INTPTR_TYPE, - CTI_UINTPTR_TYPE, - - CTI_CHAR_ARRAY_TYPE, - CTI_CHAR16_ARRAY_TYPE, - CTI_CHAR32_ARRAY_TYPE, - CTI_WCHAR_ARRAY_TYPE, - CTI_STRING_TYPE, - CTI_CONST_STRING_TYPE, - - /* Type for boolean expressions (bool in C++, int in C). */ - CTI_TRUTHVALUE_TYPE, - CTI_TRUTHVALUE_TRUE, - CTI_TRUTHVALUE_FALSE, - - CTI_DEFAULT_FUNCTION_TYPE, - - /* These are not types, but we have to look them up all the time. */ - CTI_FUNCTION_NAME_DECL, - CTI_PRETTY_FUNCTION_NAME_DECL, - CTI_C99_FUNCTION_NAME_DECL, - CTI_SAVED_FUNCTION_NAME_DECLS, - - CTI_NULL, - - CTI_MAX -}; - -#define C_CPP_HASHNODE(id) \ - (&(((struct c_common_identifier *) (id))->node)) -#define C_RID_CODE(id) \ - ((enum rid) (((struct c_common_identifier *) (id))->node.rid_code)) -#define C_SET_RID_CODE(id, code) \ - (((struct c_common_identifier *) (id))->node.rid_code = (unsigned char) code) - -/* Identifier part common to the C front ends. Inherits from - tree_identifier, despite appearances. */ -struct GTY(()) c_common_identifier { - struct tree_common common; - struct cpp_hashnode node; -}; - -/* An entry in the reserved keyword table. */ - -struct c_common_resword -{ - const char *const word; - ENUM_BITFIELD(rid) const rid : 16; - const unsigned int disable : 16; -}; - -/* Mode used to build pointers (VOIDmode means ptr_mode). */ - -extern machine_mode c_default_pointer_mode; - -/* Extra cpp_ttype values for C++. */ - -/* A token type for template-ids. If a template-id is processed while - parsing tentatively, it is replaced with a CPP_TEMPLATE_ID token; - the value of the CPP_TEMPLATE_ID is whatever was returned by - cp_parser_template_id. */ -#define CPP_TEMPLATE_ID ((enum cpp_ttype) (CPP_KEYWORD + 1)) - -/* A token type for nested-name-specifiers. If a - nested-name-specifier is processed while parsing tentatively, it is - replaced with a CPP_NESTED_NAME_SPECIFIER token; the value of the - CPP_NESTED_NAME_SPECIFIER is whatever was returned by - cp_parser_nested_name_specifier_opt. */ -#define CPP_NESTED_NAME_SPECIFIER ((enum cpp_ttype) (CPP_TEMPLATE_ID + 1)) - -/* A token type for pre-parsed C++0x decltype. */ -#define CPP_DECLTYPE ((enum cpp_ttype) (CPP_NESTED_NAME_SPECIFIER + 1)) - -/* A token type for pre-parsed primary-expression (lambda- or statement-). */ -#define CPP_PREPARSED_EXPR ((enum cpp_ttype) (CPP_DECLTYPE + 1)) - -/* The number of token types, including C++-specific ones. */ -#define N_CP_TTYPES ((int) (CPP_PREPARSED_EXPR + 1)) - -/* Disable mask. Keywords are disabled if (reswords[i].disable & - mask) is _true_. Thus for keywords which are present in all - languages the disable field is zero. */ - -#define D_CONLY 0x001 /* C only (not in C++). */ -#define D_CXXONLY 0x002 /* C++ only (not in C). */ -#define D_C99 0x004 /* In C, C99 only. */ -#define D_CXX0X 0x008 /* In C++, C++0X only. */ -#define D_EXT 0x010 /* GCC extension. */ -#define D_EXT89 0x020 /* GCC extension incorporated in C99. */ -#define D_ASM 0x040 /* Disabled by -fno-asm. */ -#define D_OBJC 0x080 /* In Objective C and neither C nor C++. */ -#define D_CXX_OBJC 0x100 /* In Objective C, and C++, but not C. */ -#define D_CXXWARN 0x200 /* In C warn with -Wcxx-compat. */ - -/* The reserved keyword table. */ -extern const struct c_common_resword c_common_reswords[]; - -/* The number of items in the reserved keyword table. */ -extern const unsigned int num_c_common_reswords; - -#define char16_type_node c_global_trees[CTI_CHAR16_TYPE] -#define char32_type_node c_global_trees[CTI_CHAR32_TYPE] -#define wchar_type_node c_global_trees[CTI_WCHAR_TYPE] -#define underlying_wchar_type_node c_global_trees[CTI_UNDERLYING_WCHAR_TYPE] -#define wint_type_node c_global_trees[CTI_WINT_TYPE] -#define signed_size_type_node c_global_trees[CTI_SIGNED_SIZE_TYPE] -#define unsigned_ptrdiff_type_node c_global_trees[CTI_UNSIGNED_PTRDIFF_TYPE] -#define intmax_type_node c_global_trees[CTI_INTMAX_TYPE] -#define uintmax_type_node c_global_trees[CTI_UINTMAX_TYPE] -#define widest_integer_literal_type_node c_global_trees[CTI_WIDEST_INT_LIT_TYPE] -#define widest_unsigned_literal_type_node c_global_trees[CTI_WIDEST_UINT_LIT_TYPE] - -#define sig_atomic_type_node c_global_trees[CTI_SIG_ATOMIC_TYPE] -#define int8_type_node c_global_trees[CTI_INT8_TYPE] -#define int16_type_node c_global_trees[CTI_INT16_TYPE] -#define int32_type_node c_global_trees[CTI_INT32_TYPE] -#define int64_type_node c_global_trees[CTI_INT64_TYPE] -#define uint8_type_node c_global_trees[CTI_UINT8_TYPE] -#define c_uint16_type_node c_global_trees[CTI_UINT16_TYPE] -#define c_uint32_type_node c_global_trees[CTI_UINT32_TYPE] -#define c_uint64_type_node c_global_trees[CTI_UINT64_TYPE] -#define int_least8_type_node c_global_trees[CTI_INT_LEAST8_TYPE] -#define int_least16_type_node c_global_trees[CTI_INT_LEAST16_TYPE] -#define int_least32_type_node c_global_trees[CTI_INT_LEAST32_TYPE] -#define int_least64_type_node c_global_trees[CTI_INT_LEAST64_TYPE] -#define uint_least8_type_node c_global_trees[CTI_UINT_LEAST8_TYPE] -#define uint_least16_type_node c_global_trees[CTI_UINT_LEAST16_TYPE] -#define uint_least32_type_node c_global_trees[CTI_UINT_LEAST32_TYPE] -#define uint_least64_type_node c_global_trees[CTI_UINT_LEAST64_TYPE] -#define int_fast8_type_node c_global_trees[CTI_INT_FAST8_TYPE] -#define int_fast16_type_node c_global_trees[CTI_INT_FAST16_TYPE] -#define int_fast32_type_node c_global_trees[CTI_INT_FAST32_TYPE] -#define int_fast64_type_node c_global_trees[CTI_INT_FAST64_TYPE] -#define uint_fast8_type_node c_global_trees[CTI_UINT_FAST8_TYPE] -#define uint_fast16_type_node c_global_trees[CTI_UINT_FAST16_TYPE] -#define uint_fast32_type_node c_global_trees[CTI_UINT_FAST32_TYPE] -#define uint_fast64_type_node c_global_trees[CTI_UINT_FAST64_TYPE] -#define intptr_type_node c_global_trees[CTI_INTPTR_TYPE] -#define uintptr_type_node c_global_trees[CTI_UINTPTR_TYPE] - -#define truthvalue_type_node c_global_trees[CTI_TRUTHVALUE_TYPE] -#define truthvalue_true_node c_global_trees[CTI_TRUTHVALUE_TRUE] -#define truthvalue_false_node c_global_trees[CTI_TRUTHVALUE_FALSE] - -#define char_array_type_node c_global_trees[CTI_CHAR_ARRAY_TYPE] -#define char16_array_type_node c_global_trees[CTI_CHAR16_ARRAY_TYPE] -#define char32_array_type_node c_global_trees[CTI_CHAR32_ARRAY_TYPE] -#define wchar_array_type_node c_global_trees[CTI_WCHAR_ARRAY_TYPE] -#define string_type_node c_global_trees[CTI_STRING_TYPE] -#define const_string_type_node c_global_trees[CTI_CONST_STRING_TYPE] - -#define default_function_type c_global_trees[CTI_DEFAULT_FUNCTION_TYPE] - -#define function_name_decl_node c_global_trees[CTI_FUNCTION_NAME_DECL] -#define pretty_function_name_decl_node c_global_trees[CTI_PRETTY_FUNCTION_NAME_DECL] -#define c99_function_name_decl_node c_global_trees[CTI_C99_FUNCTION_NAME_DECL] -#define saved_function_name_decls c_global_trees[CTI_SAVED_FUNCTION_NAME_DECLS] - -/* The node for C++ `__null'. */ -#define null_node c_global_trees[CTI_NULL] - -extern GTY(()) tree c_global_trees[CTI_MAX]; - -/* In a RECORD_TYPE, a sorted array of the fields of the type, not a - tree for size reasons. */ -struct GTY(()) sorted_fields_type { - int len; - tree GTY((length ("%h.len"))) elts[1]; -}; - -/* Mark which labels are explicitly declared. - These may be shadowed, and may be referenced from nested functions. */ -#define C_DECLARED_LABEL_FLAG(label) TREE_LANG_FLAG_1 (label) - -typedef enum c_language_kind -{ - clk_c = 0, /* C90, C94, C99 or C11 */ - clk_objc = 1, /* clk_c with ObjC features. */ - clk_cxx = 2, /* ANSI/ISO C++ */ - clk_objcxx = 3 /* clk_cxx with ObjC features. */ -} -c_language_kind; - -/* To test for a specific language use c_language, defined by each - front end. For "ObjC features" or "not C++" use the macros. */ -extern c_language_kind c_language; - -#define c_dialect_cxx() ((c_language & clk_cxx) != 0) -#define c_dialect_objc() ((c_language & clk_objc) != 0) - -/* The various name of operator that appears in error messages. */ -typedef enum ref_operator { - /* NULL */ - RO_NULL, - /* array indexing */ - RO_ARRAY_INDEXING, - /* unary * */ - RO_UNARY_STAR, - /* -> */ - RO_ARROW, - /* implicit conversion */ - RO_IMPLICIT_CONVERSION, - /* ->* */ - RO_ARROW_STAR -} ref_operator; - -/* Information about a statement tree. */ - -struct GTY(()) stmt_tree_s { - /* A stack of statement lists being collected. */ - vec *x_cur_stmt_list; - - /* In C++, Nonzero if we should treat statements as full - expressions. In particular, this variable is non-zero if at the - end of a statement we should destroy any temporaries created - during that statement. Similarly, if, at the end of a block, we - should destroy any local variables in this block. Normally, this - variable is nonzero, since those are the normal semantics of - C++. - - This flag has no effect in C. */ - int stmts_are_full_exprs_p; -}; - -typedef struct stmt_tree_s *stmt_tree; - -/* Global state pertinent to the current function. Some C dialects - extend this structure with additional fields. */ - -struct GTY(()) c_language_function { - /* While we are parsing the function, this contains information - about the statement-tree that we are building. */ - struct stmt_tree_s x_stmt_tree; - - /* Vector of locally defined typedefs, for - -Wunused-local-typedefs. */ - vec *local_typedefs; -}; - -#define stmt_list_stack (current_stmt_tree ()->x_cur_stmt_list) - -/* When building a statement-tree, this is the current statement list - being collected. */ -#define cur_stmt_list (stmt_list_stack->last ()) - -#define building_stmt_list_p() (stmt_list_stack && !stmt_list_stack->is_empty()) - -/* Language-specific hooks. */ - -/* If non-NULL, this function is called after a precompile header file - is loaded. */ -extern void (*lang_post_pch_load) (void); - -extern void push_file_scope (void); -extern void pop_file_scope (void); -extern stmt_tree current_stmt_tree (void); -extern tree push_stmt_list (void); -extern tree pop_stmt_list (tree); -extern tree add_stmt (tree); -extern void push_cleanup (tree, tree, bool); -extern tree pushdecl_top_level (tree); -extern tree pushdecl (tree); -extern tree build_modify_expr (location_t, tree, tree, enum tree_code, - location_t, tree, tree); -extern tree build_array_notation_expr (location_t, tree, tree, enum tree_code, - location_t, tree, tree); -extern tree build_array_notation_ref (location_t, tree, tree, tree, tree, tree); -extern tree build_indirect_ref (location_t, tree, ref_operator); - -extern int field_decl_cmp (const void *, const void *); -extern void resort_sorted_fields (void *, void *, gt_pointer_operator, - void *); -extern bool has_c_linkage (const_tree decl); - -/* Switches common to the C front ends. */ - -/* Nonzero means don't output line number information. */ - -extern char flag_no_line_commands; - -/* Nonzero causes -E output not to be done, but directives such as - #define that have side effects are still obeyed. */ - -extern char flag_no_output; - -/* Nonzero means dump macros in some fashion; contains the 'D', 'M', - 'N' or 'U' of the command line switch. */ - -extern char flag_dump_macros; - -/* Nonzero means pass #include lines through to the output. */ - -extern char flag_dump_includes; - -/* Nonzero means process PCH files while preprocessing. */ - -extern bool flag_pch_preprocess; - -/* The file name to which we should write a precompiled header, or - NULL if no header will be written in this compile. */ - -extern const char *pch_file; - -/* Nonzero if an ISO standard was selected. It rejects macros in the - user's namespace. */ - -extern int flag_iso; - -/* C/ObjC language option variables. */ - - -/* Nonzero means allow type mismatches in conditional expressions; - just make their values `void'. */ - -extern int flag_cond_mismatch; - -/* Nonzero means enable C89 Amendment 1 features. */ - -extern int flag_isoc94; - -/* Nonzero means use the ISO C99 (or C11) dialect of C. */ - -extern int flag_isoc99; - -/* Nonzero means use the ISO C11 dialect of C. */ - -extern int flag_isoc11; - -/* Nonzero means that we have builtin functions, and main is an int. */ - -extern int flag_hosted; - -/* ObjC language option variables. */ - - -/* Tells the compiler that this is a special run. Do not perform any - compiling, instead we are to test some platform dependent features - and output a C header file with appropriate definitions. */ - -extern int print_struct_values; - -/* Tells the compiler what is the constant string class for ObjC. */ - -extern const char *constant_string_class_name; - - -/* C++ language option variables. */ - - -/* Return TRUE if one of {flag_abi_version,flag_abi_compat_version} is - less than N and the other is at least N, for use by -Wabi. */ -#define abi_version_crosses(N) \ - (abi_version_at_least(N) \ - != (flag_abi_compat_version == 0 \ - || flag_abi_compat_version >= (N))) - -/* Nonzero means generate separate instantiation control files and - juggle them at link time. */ - -extern int flag_use_repository; - -/* The supported C++ dialects. */ - -enum cxx_dialect { - /* C++98 with TC1 */ - cxx98, - cxx03 = cxx98, - /* C++11 */ - cxx0x, - cxx11 = cxx0x, - /* C++14 */ - cxx14, - /* C++1z (C++17?) */ - cxx1z -}; - -/* The C++ dialect being used. C++98 is the default. */ -extern enum cxx_dialect cxx_dialect; - -/* Maximum template instantiation depth. This limit is rather - arbitrary, but it exists to limit the time it takes to notice - excessively recursive template instantiations. */ - -extern int max_tinst_depth; - -/* Nonzero means that we should not issue warnings about problems that - occur when the code is executed, because the code being processed - is not expected to be executed. This is set during parsing. This - is used for cases like sizeof() and "0 ? a : b". This is a count, - not a bool, because unexecuted expressions can nest. */ - -extern int c_inhibit_evaluation_warnings; - -/* Whether lexing has been completed, so subsequent preprocessor - errors should use the compiler's input_location. */ - -extern bool done_lexing; - -/* C types are partitioned into three subsets: object, function, and - incomplete types. */ -#define C_TYPE_OBJECT_P(type) \ - (TREE_CODE (type) != FUNCTION_TYPE && TYPE_SIZE (type)) - -#define C_TYPE_INCOMPLETE_P(type) \ - (TREE_CODE (type) != FUNCTION_TYPE && TYPE_SIZE (type) == 0) - -#define C_TYPE_FUNCTION_P(type) \ - (TREE_CODE (type) == FUNCTION_TYPE) - -/* For convenience we define a single macro to identify the class of - object or incomplete types. */ -#define C_TYPE_OBJECT_OR_INCOMPLETE_P(type) \ - (!C_TYPE_FUNCTION_P (type)) - -struct visibility_flags -{ - unsigned inpragma : 1; /* True when in #pragma GCC visibility. */ - unsigned inlines_hidden : 1; /* True when -finlineshidden in effect. */ -}; - -/* These enumerators are possible types of unsafe conversions. - SAFE_CONVERSION The conversion is safe - UNSAFE_OTHER Another type of conversion with problems - UNSAFE_SIGN Conversion between signed and unsigned integers - which are all warned about immediately, so this is unused - UNSAFE_REAL Conversions that reduce the precision of reals - including conversions from reals to integers - */ -enum conversion_safety { SAFE_CONVERSION = 0, UNSAFE_OTHER, UNSAFE_SIGN, UNSAFE_REAL }; - -/* Global visibility options. */ -extern struct visibility_flags visibility_options; - -/* Attribute table common to the C front ends. */ -extern const struct attribute_spec c_common_attribute_table[]; -extern const struct attribute_spec c_common_format_attribute_table[]; - -/* Pointer to function to lazily generate the VAR_DECL for __FUNCTION__ etc. - ID is the identifier to use, NAME is the string. - TYPE_DEP indicates whether it depends on type of the function or not - (i.e. __PRETTY_FUNCTION__). */ - -extern tree (*make_fname_decl) (location_t, tree, int); - -/* In c-decl.c and cp/tree.c. FIXME. */ -extern void c_register_addr_space (const char *str, addr_space_t as); - -/* In c-common.c. */ -extern bool in_late_binary_op; -extern const char *c_addr_space_name (addr_space_t as); -extern tree identifier_global_value (tree); -extern tree c_linkage_bindings (tree); -extern void record_builtin_type (enum rid, const char *, tree); -extern tree build_void_list_node (void); -extern void start_fname_decls (void); -extern void finish_fname_decls (void); -extern const char *fname_as_string (int); -extern tree fname_decl (location_t, unsigned, tree); - -extern int check_user_alignment (const_tree, bool); -extern void check_function_arguments (const_tree, int, tree *); -extern void check_function_arguments_recurse (void (*) - (void *, tree, - unsigned HOST_WIDE_INT), - void *, tree, - unsigned HOST_WIDE_INT); -extern bool check_builtin_function_arguments (tree, int, tree *); -extern void check_function_format (tree, int, tree *); -extern tree handle_format_attribute (tree *, tree, tree, int, bool *); -extern tree handle_format_arg_attribute (tree *, tree, tree, int, bool *); -extern bool attribute_takes_identifier_p (const_tree); -extern bool c_common_handle_option (size_t, const char *, int, int, location_t, - const struct cl_option_handlers *); -extern bool default_handle_c_option (size_t, const char *, int); -extern tree c_common_type_for_mode (machine_mode, int); -extern tree c_common_type_for_size (unsigned int, int); -extern tree c_common_fixed_point_type_for_size (unsigned int, unsigned int, - int, int); -extern tree c_common_unsigned_type (tree); -extern tree c_common_signed_type (tree); -extern tree c_common_signed_or_unsigned_type (int, tree); -extern void c_common_init_ts (void); -extern tree c_build_bitfield_integer_type (unsigned HOST_WIDE_INT, int); -extern enum conversion_safety unsafe_conversion_p (location_t, tree, tree, - bool); -extern bool decl_with_nonnull_addr_p (const_tree); -extern tree c_fully_fold (tree, bool, bool *); -extern tree decl_constant_value_for_optimization (tree); -extern tree c_wrap_maybe_const (tree, bool); -extern tree c_save_expr (tree); -extern tree c_common_truthvalue_conversion (location_t, tree); -extern void c_apply_type_quals_to_decl (int, tree); -extern tree c_sizeof_or_alignof_type (location_t, tree, bool, bool, int); -extern tree c_alignof_expr (location_t, tree); -/* Print an error message for invalid operands to arith operation CODE. - NOP_EXPR is used as a special case (see truthvalue_conversion). */ -extern void binary_op_error (location_t, enum tree_code, tree, tree); -extern tree fix_string_type (tree); -extern void constant_expression_warning (tree); -extern void constant_expression_error (tree); -extern bool strict_aliasing_warning (tree, tree, tree); -extern void sizeof_pointer_memaccess_warning (location_t *, tree, - vec *, tree *, - bool (*) (tree, tree)); -extern void warnings_for_convert_and_check (location_t, tree, tree, tree); -extern tree convert_and_check (location_t, tree, tree); -extern void overflow_warning (location_t, tree); -extern bool warn_if_unused_value (const_tree, location_t); -extern void warn_logical_operator (location_t, enum tree_code, tree, - enum tree_code, tree, enum tree_code, tree); -extern void warn_logical_not_parentheses (location_t, enum tree_code, tree); -extern void check_main_parameter_types (tree decl); -extern bool c_determine_visibility (tree); -extern bool vector_types_compatible_elements_p (tree, tree); -extern void mark_valid_location_for_stdc_pragma (bool); -extern bool valid_location_for_stdc_pragma_p (void); -extern void set_float_const_decimal64 (void); -extern void clear_float_const_decimal64 (void); -extern bool float_const_decimal64_p (void); - -extern bool keyword_begins_type_specifier (enum rid); -extern bool keyword_is_storage_class_specifier (enum rid); -extern bool keyword_is_type_qualifier (enum rid); -extern bool keyword_is_decl_specifier (enum rid); -extern bool cxx_fundamental_alignment_p (unsigned); -extern bool pointer_to_zero_sized_aggr_p (tree); - -#define c_sizeof(LOC, T) c_sizeof_or_alignof_type (LOC, T, true, false, 1) -#define c_alignof(LOC, T) c_sizeof_or_alignof_type (LOC, T, false, false, 1) - -/* Subroutine of build_binary_op, used for certain operations. */ -extern tree shorten_binary_op (tree result_type, tree op0, tree op1, bool bitwise); - -/* Subroutine of build_binary_op, used for comparison operations. - See if the operands have both been converted from subword integer types - and, if so, perhaps change them both back to their original type. */ -extern tree shorten_compare (location_t, tree *, tree *, tree *, - enum tree_code *); - -extern tree pointer_int_sum (location_t, enum tree_code, tree, tree, - bool = true); - -/* Add qualifiers to a type, in the fashion for C. */ -extern tree c_build_qualified_type (tree, int, tree = NULL_TREE, size_t = 0); - -/* Build tree nodes and builtin functions common to both C and C++ language - frontends. */ -extern void c_common_nodes_and_builtins (void); - -extern void disable_builtin_function (const char *); - -extern void set_compound_literal_name (tree decl); - -extern tree build_va_arg (location_t, tree, tree); - -extern const unsigned int c_family_lang_mask; -extern unsigned int c_common_option_lang_mask (void); -extern void c_common_diagnostics_set_defaults (diagnostic_context *); -extern bool c_common_complain_wrong_lang_p (const struct cl_option *); -extern void c_common_init_options_struct (struct gcc_options *); -extern void c_common_init_options (unsigned int, struct cl_decoded_option *); -extern bool c_common_post_options (const char **); -extern bool c_common_init (void); -extern void c_common_finish (void); -extern void c_common_parse_file (void); -extern FILE *get_dump_info (int, int *); -extern alias_set_type c_common_get_alias_set (tree); -extern void c_register_builtin_type (tree, const char*); -extern bool c_promoting_integer_type_p (const_tree); -extern int self_promoting_args_p (const_tree); -extern tree strip_pointer_operator (tree); -extern tree strip_pointer_or_array_types (tree); -extern HOST_WIDE_INT c_common_to_target_charset (HOST_WIDE_INT); - -/* This is the basic parsing function. */ -extern void c_parse_file (void); - -extern void warn_for_omitted_condop (location_t, tree); - -/* These macros provide convenient access to the various _STMT nodes. */ - -/* Nonzero if a given STATEMENT_LIST represents the outermost binding - if a statement expression. */ -#define STATEMENT_LIST_STMT_EXPR(NODE) \ - TREE_LANG_FLAG_1 (STATEMENT_LIST_CHECK (NODE)) - -/* Nonzero if a label has been added to the statement list. */ -#define STATEMENT_LIST_HAS_LABEL(NODE) \ - TREE_LANG_FLAG_3 (STATEMENT_LIST_CHECK (NODE)) - -/* C_MAYBE_CONST_EXPR accessors. */ -#define C_MAYBE_CONST_EXPR_PRE(NODE) \ - TREE_OPERAND (C_MAYBE_CONST_EXPR_CHECK (NODE), 0) -#define C_MAYBE_CONST_EXPR_EXPR(NODE) \ - TREE_OPERAND (C_MAYBE_CONST_EXPR_CHECK (NODE), 1) -#define C_MAYBE_CONST_EXPR_INT_OPERANDS(NODE) \ - TREE_LANG_FLAG_0 (C_MAYBE_CONST_EXPR_CHECK (NODE)) -#define C_MAYBE_CONST_EXPR_NON_CONST(NODE) \ - TREE_LANG_FLAG_1 (C_MAYBE_CONST_EXPR_CHECK (NODE)) -#define EXPR_INT_CONST_OPERANDS(EXPR) \ - (INTEGRAL_TYPE_P (TREE_TYPE (EXPR)) \ - && (TREE_CODE (EXPR) == INTEGER_CST \ - || (TREE_CODE (EXPR) == C_MAYBE_CONST_EXPR \ - && C_MAYBE_CONST_EXPR_INT_OPERANDS (EXPR)))) - -/* In a FIELD_DECL, nonzero if the decl was originally a bitfield. */ -#define DECL_C_BIT_FIELD(NODE) \ - (DECL_LANG_FLAG_4 (FIELD_DECL_CHECK (NODE)) == 1) -#define SET_DECL_C_BIT_FIELD(NODE) \ - (DECL_LANG_FLAG_4 (FIELD_DECL_CHECK (NODE)) = 1) -#define CLEAR_DECL_C_BIT_FIELD(NODE) \ - (DECL_LANG_FLAG_4 (FIELD_DECL_CHECK (NODE)) = 0) - -extern tree do_case (location_t, tree, tree); -extern tree build_stmt (location_t, enum tree_code, ...); -extern tree build_real_imag_expr (location_t, enum tree_code, tree); - -/* These functions must be defined by each front-end which implements - a variant of the C language. They are used in c-common.c. */ - -extern tree build_unary_op (location_t, enum tree_code, tree, int); -extern tree build_binary_op (location_t, enum tree_code, tree, tree, int); -extern tree perform_integral_promotions (tree); - -/* These functions must be defined by each front-end which implements - a variant of the C language. They are used by port files. */ - -extern tree default_conversion (tree); - -/* Given two integer or real types, return the type for their sum. - Given two compatible ANSI C types, returns the merged type. */ - -extern tree common_type (tree, tree); - -extern tree decl_constant_value (tree); - -/* Handle increment and decrement of boolean types. */ -extern tree boolean_increment (enum tree_code, tree); - -extern int case_compare (splay_tree_key, splay_tree_key); - -extern tree c_add_case_label (location_t, splay_tree, tree, tree, tree, tree); - -extern void c_do_switch_warnings (splay_tree, location_t, tree, tree); - -extern tree build_function_call (location_t, tree, tree); - -extern tree build_function_call_vec (location_t, vec, tree, - vec *, vec *); - -extern tree resolve_overloaded_builtin (location_t, tree, vec *); - -extern tree finish_label_address_expr (tree, location_t); - -/* Same function prototype, but the C and C++ front ends have - different implementations. Used in c-common.c. */ -extern tree lookup_label (tree); -extern tree lookup_name (tree); -extern bool lvalue_p (const_tree); - -extern bool vector_targets_convertible_p (const_tree t1, const_tree t2); -extern bool vector_types_convertible_p (const_tree t1, const_tree t2, bool emit_lax_note); -extern tree c_build_vec_perm_expr (location_t, tree, tree, tree, bool = true); - -extern void init_c_lex (void); - -extern void c_cpp_builtins (cpp_reader *); -extern void c_cpp_builtins_optimize_pragma (cpp_reader *, tree, tree); -extern bool c_cpp_error (cpp_reader *, int, int, location_t, unsigned int, - const char *, va_list *) - ATTRIBUTE_GCC_DIAG(6,0); -extern int c_common_has_attribute (cpp_reader *); - -extern bool parse_optimize_options (tree, bool); - -/* Positive if an implicit `extern "C"' scope has just been entered; - negative if such a scope has just been exited. */ -extern GTY(()) int pending_lang_change; - -/* Information recorded about each file examined during compilation. */ - -struct c_fileinfo -{ - int time; /* Time spent in the file. */ - - /* Flags used only by C++. - INTERFACE_ONLY nonzero means that we are in an "interface" section - of the compiler. INTERFACE_UNKNOWN nonzero means we cannot trust - the value of INTERFACE_ONLY. If INTERFACE_UNKNOWN is zero and - INTERFACE_ONLY is zero, it means that we are responsible for - exporting definitions that others might need. */ - short interface_only; - short interface_unknown; -}; - -struct c_fileinfo *get_fileinfo (const char *); -extern void dump_time_statistics (void); - -extern bool c_dump_tree (void *, tree); - -extern void verify_sequence_points (tree); - -extern tree fold_offsetof_1 (tree); -extern tree fold_offsetof (tree); - -/* Places where an lvalue, or modifiable lvalue, may be required. - Used to select diagnostic messages in lvalue_error and - readonly_error. */ -enum lvalue_use { - lv_assign, - lv_increment, - lv_decrement, - lv_addressof, - lv_asm -}; - -extern void readonly_error (location_t, tree, enum lvalue_use); -extern void lvalue_error (location_t, enum lvalue_use); -extern void invalid_indirection_error (location_t, tree, ref_operator); - -extern int complete_array_type (tree *, tree, bool); - -extern tree builtin_type_for_size (int, bool); - -extern void c_common_mark_addressable_vec (tree); - -extern void warn_array_subscript_with_type_char (location_t, tree); -extern void warn_about_parentheses (location_t, - enum tree_code, - enum tree_code, tree, - enum tree_code, tree); -extern void warn_for_unused_label (tree label); -extern void warn_for_div_by_zero (location_t, tree divisor); -extern void warn_for_sign_compare (location_t, - tree orig_op0, tree orig_op1, - tree op0, tree op1, - tree result_type, - enum tree_code resultcode); -extern void do_warn_double_promotion (tree, tree, tree, const char *, - location_t); -extern void set_underlying_type (tree); -extern void record_types_used_by_current_var_decl (tree); -extern void record_locally_defined_typedef (tree); -extern void maybe_record_typedef_use (tree); -extern void maybe_warn_unused_local_typedefs (void); -extern void maybe_warn_bool_compare (location_t, enum tree_code, tree, tree); -extern vec *make_tree_vector (void); -extern void release_tree_vector (vec *); -extern vec *make_tree_vector_single (tree); -extern vec *make_tree_vector_from_list (tree); -extern vec *make_tree_vector_copy (const vec *); - -/* Used for communication between c_common_type_for_mode and - c_register_builtin_type. */ -extern GTY(()) tree registered_builtin_types; - -/* In c-gimplify.c */ -extern void c_genericize (tree); -extern int c_gimplify_expr (tree *, gimple_seq *, gimple_seq *); -extern tree c_build_bind_expr (location_t, tree, tree); - -/* In c-pch.c */ -extern void pch_init (void); -extern void pch_cpp_save_state (void); -extern int c_common_valid_pch (cpp_reader *pfile, const char *name, int fd); -extern void c_common_read_pch (cpp_reader *pfile, const char *name, int fd, - const char *orig); -extern void c_common_write_pch (void); -extern void c_common_no_more_pch (void); -extern void c_common_pch_pragma (cpp_reader *pfile, const char *); - -/* In *-checksum.c */ -extern const unsigned char executable_checksum[16]; - -/* In c-cppbuiltin.c */ -extern void builtin_define_std (const char *macro); -extern void builtin_define_with_value (const char *, const char *, int); -extern void c_stddef_cpp_builtins (void); -extern void fe_file_change (const struct line_map *); -extern void c_parse_error (const char *, enum cpp_ttype, tree, unsigned char); - -/* In c-ppoutput.c */ -extern void init_pp_output (FILE *); -extern void preprocess_file (cpp_reader *); -extern void pp_file_change (const struct line_map *); -extern void pp_dir_change (cpp_reader *, const char *); -extern bool check_missing_format_attribute (tree, tree); - -/* In c-omp.c */ -#if HOST_BITS_PER_WIDE_INT >= 64 -typedef unsigned HOST_WIDE_INT omp_clause_mask; -# define OMP_CLAUSE_MASK_1 ((omp_clause_mask) 1) -#else -struct omp_clause_mask -{ - inline omp_clause_mask (); - inline omp_clause_mask (unsigned HOST_WIDE_INT l); - inline omp_clause_mask (unsigned HOST_WIDE_INT l, - unsigned HOST_WIDE_INT h); - inline omp_clause_mask &operator &= (omp_clause_mask); - inline omp_clause_mask &operator |= (omp_clause_mask); - inline omp_clause_mask operator ~ () const; - inline omp_clause_mask operator & (omp_clause_mask) const; - inline omp_clause_mask operator | (omp_clause_mask) const; - inline omp_clause_mask operator >> (int); - inline omp_clause_mask operator << (int); - inline bool operator == (omp_clause_mask) const; - inline bool operator != (omp_clause_mask) const; - unsigned HOST_WIDE_INT low, high; -}; - -inline -omp_clause_mask::omp_clause_mask () -{ -} - -inline -omp_clause_mask::omp_clause_mask (unsigned HOST_WIDE_INT l) -: low (l), high (0) -{ -} - -inline -omp_clause_mask::omp_clause_mask (unsigned HOST_WIDE_INT l, - unsigned HOST_WIDE_INT h) -: low (l), high (h) -{ -} - -inline omp_clause_mask & -omp_clause_mask::operator &= (omp_clause_mask b) -{ - low &= b.low; - high &= b.high; - return *this; -} - -inline omp_clause_mask & -omp_clause_mask::operator |= (omp_clause_mask b) -{ - low |= b.low; - high |= b.high; - return *this; -} - -inline omp_clause_mask -omp_clause_mask::operator ~ () const -{ - omp_clause_mask ret (~low, ~high); - return ret; -} - -inline omp_clause_mask -omp_clause_mask::operator | (omp_clause_mask b) const -{ - omp_clause_mask ret (low | b.low, high | b.high); - return ret; -} - -inline omp_clause_mask -omp_clause_mask::operator & (omp_clause_mask b) const -{ - omp_clause_mask ret (low & b.low, high & b.high); - return ret; -} - -inline omp_clause_mask -omp_clause_mask::operator << (int amount) -{ - omp_clause_mask ret; - if (amount >= HOST_BITS_PER_WIDE_INT) - { - ret.low = 0; - ret.high = low << (amount - HOST_BITS_PER_WIDE_INT); - } - else if (amount == 0) - ret = *this; - else - { - ret.low = low << amount; - ret.high = (low >> (HOST_BITS_PER_WIDE_INT - amount)) - | (high << amount); - } - return ret; -} - -inline omp_clause_mask -omp_clause_mask::operator >> (int amount) -{ - omp_clause_mask ret; - if (amount >= HOST_BITS_PER_WIDE_INT) - { - ret.low = high >> (amount - HOST_BITS_PER_WIDE_INT); - ret.high = 0; - } - else if (amount == 0) - ret = *this; - else - { - ret.low = (high << (HOST_BITS_PER_WIDE_INT - amount)) - | (low >> amount); - ret.high = high >> amount; - } - return ret; -} - -inline bool -omp_clause_mask::operator == (omp_clause_mask b) const -{ - return low == b.low && high == b.high; -} - -inline bool -omp_clause_mask::operator != (omp_clause_mask b) const -{ - return low != b.low || high != b.high; -} - -# define OMP_CLAUSE_MASK_1 omp_clause_mask (1) -#endif - -enum c_omp_clause_split -{ - C_OMP_CLAUSE_SPLIT_TARGET = 0, - C_OMP_CLAUSE_SPLIT_TEAMS, - C_OMP_CLAUSE_SPLIT_DISTRIBUTE, - C_OMP_CLAUSE_SPLIT_PARALLEL, - C_OMP_CLAUSE_SPLIT_FOR, - C_OMP_CLAUSE_SPLIT_SIMD, - C_OMP_CLAUSE_SPLIT_COUNT, - C_OMP_CLAUSE_SPLIT_SECTIONS = C_OMP_CLAUSE_SPLIT_FOR -}; - -extern tree c_finish_omp_master (location_t, tree); -extern tree c_finish_omp_taskgroup (location_t, tree); -extern tree c_finish_omp_critical (location_t, tree, tree); -extern tree c_finish_omp_ordered (location_t, tree); -extern void c_finish_omp_barrier (location_t); -extern tree c_finish_omp_atomic (location_t, enum tree_code, enum tree_code, - tree, tree, tree, tree, tree, bool, bool); -extern void c_finish_omp_flush (location_t); -extern void c_finish_omp_taskwait (location_t); -extern void c_finish_omp_taskyield (location_t); -extern tree c_finish_omp_for (location_t, enum tree_code, tree, tree, tree, - tree, tree, tree); -extern tree c_finish_oacc_wait (location_t, tree, tree); -extern void c_omp_split_clauses (location_t, enum tree_code, omp_clause_mask, - tree, tree *); -extern tree c_omp_declare_simd_clauses_to_numbers (tree, tree); -extern void c_omp_declare_simd_clauses_to_decls (tree, tree); -extern enum omp_clause_default_kind c_omp_predetermined_sharing (tree); - -/* Return next tree in the chain for chain_next walking of tree nodes. */ -static inline tree -c_tree_chain_next (tree t) -{ - /* TREE_CHAIN of a type is TYPE_STUB_DECL, which is different - kind of object, never a long chain of nodes. Prefer - TYPE_NEXT_VARIANT for types. */ - if (CODE_CONTAINS_STRUCT (TREE_CODE (t), TS_TYPE_COMMON)) - return TYPE_NEXT_VARIANT (t); - /* Otherwise, if there is TREE_CHAIN, return it. */ - if (CODE_CONTAINS_STRUCT (TREE_CODE (t), TS_COMMON)) - return TREE_CHAIN (t); - return NULL; -} - -/* Mask used by tm_stmt_attr. */ -#define TM_STMT_ATTR_OUTER 2 -#define TM_STMT_ATTR_ATOMIC 4 -#define TM_STMT_ATTR_RELAXED 8 - -extern int parse_tm_stmt_attr (tree, int); - -/* Mask used by tm_attr_to_mask and tm_mask_to_attr. Note that these - are ordered specifically such that more restrictive attributes are - at lower bit positions. This fact is known by the C++ tm attribute - inheritance code such that least bit extraction (mask & -mask) results - in the most restrictive attribute. */ -#define TM_ATTR_SAFE 1 -#define TM_ATTR_CALLABLE 2 -#define TM_ATTR_PURE 4 -#define TM_ATTR_IRREVOCABLE 8 -#define TM_ATTR_MAY_CANCEL_OUTER 16 - -extern int tm_attr_to_mask (tree); -extern tree tm_mask_to_attr (int); -extern tree find_tm_attribute (tree); - -/* A suffix-identifier value doublet that represents user-defined literals - for C++-0x. */ -enum overflow_type { - OT_UNDERFLOW = -1, - OT_NONE, - OT_OVERFLOW -}; - -struct GTY(()) tree_userdef_literal { - struct tree_base base; - tree suffix_id; - tree value; - tree num_string; - enum overflow_type overflow; -}; - -#define USERDEF_LITERAL_SUFFIX_ID(NODE) \ - (((struct tree_userdef_literal *)USERDEF_LITERAL_CHECK (NODE))->suffix_id) - -#define USERDEF_LITERAL_VALUE(NODE) \ - (((struct tree_userdef_literal *)USERDEF_LITERAL_CHECK (NODE))->value) - -#define USERDEF_LITERAL_OVERFLOW(NODE) \ - (((struct tree_userdef_literal *)USERDEF_LITERAL_CHECK (NODE))->overflow) - -#define USERDEF_LITERAL_NUM_STRING(NODE) \ - (((struct tree_userdef_literal *)USERDEF_LITERAL_CHECK (NODE))->num_string) - -#define USERDEF_LITERAL_TYPE(NODE) \ - (TREE_TYPE (USERDEF_LITERAL_VALUE (NODE))) - -extern tree build_userdef_literal (tree suffix_id, tree value, - enum overflow_type overflow, - tree num_string); - -extern bool convert_vector_to_pointer_for_subscript (location_t, tree *, tree); - -/* Possibe cases of scalar_to_vector conversion. */ -enum stv_conv { - stv_error, /* Error occurred. */ - stv_nothing, /* Nothing happened. */ - stv_firstarg, /* First argument must be expanded. */ - stv_secondarg /* Second argument must be expanded. */ -}; - -extern enum stv_conv scalar_to_vector (location_t loc, enum tree_code code, - tree op0, tree op1, bool); - -/* In c-cilkplus.c */ -extern tree c_finish_cilk_clauses (tree); -extern tree c_validate_cilk_plus_loop (tree *, int *, void *); -extern bool c_check_cilk_loop (location_t, tree); - -/* These #defines allow users to access different operands of the - array notation tree. */ - -#define ARRAY_NOTATION_CHECK(NODE) TREE_CHECK (NODE, ARRAY_NOTATION_REF) -#define ARRAY_NOTATION_ARRAY(NODE) \ - TREE_OPERAND (ARRAY_NOTATION_CHECK (NODE), 0) -#define ARRAY_NOTATION_START(NODE) \ - TREE_OPERAND (ARRAY_NOTATION_CHECK (NODE), 1) -#define ARRAY_NOTATION_LENGTH(NODE) \ - TREE_OPERAND (ARRAY_NOTATION_CHECK (NODE), 2) -#define ARRAY_NOTATION_STRIDE(NODE) \ - TREE_OPERAND (ARRAY_NOTATION_CHECK (NODE), 3) - -/* This structure holds all the scalar values and its appropriate variable - replacment. It is mainly used by the function that pulls all the invariant - parts that should be executed only once, which comes with array notation - expressions. */ -struct inv_list -{ - vec *list_values; - vec *replacement; - vec *additional_tcodes; -}; - -/* This structure holds all the important components that can be extracted - from an ARRAY_NOTATION_REF expression. It is used to pass array notation - information between the functions that are responsible for expansion. */ -typedef struct cilkplus_an_parts -{ - tree value; - tree start; - tree length; - tree stride; - bool is_vector; -} an_parts; - -/* This structure holds the components necessary to create the loop around - the ARRAY_REF that is created using the ARRAY_NOTATION information. */ - -typedef struct cilkplus_an_loop_parts -{ - tree var; /* Loop induction variable. */ - tree incr; /* Loop increment/decrement expression. */ - tree cmp; /* Loop condition. */ - tree ind_init; /* Initialization of the loop induction variable. */ -} an_loop_parts; - -/* In array-notation-common.c. */ -extern HOST_WIDE_INT extract_sec_implicit_index_arg (location_t, tree); -extern bool is_sec_implicit_index_fn (tree); -extern void array_notation_init_builtins (void); -extern struct c_expr fix_array_notation_expr (location_t, enum tree_code, - struct c_expr); -extern bool contains_array_notation_expr (tree); -extern tree expand_array_notation_exprs (tree); -extern tree fix_conditional_array_notations (tree); -extern tree find_correct_array_notation_type (tree); -extern bool length_mismatch_in_expr_p (location_t, vec >); -extern enum built_in_function is_cilkplus_reduce_builtin (tree); -extern bool find_rank (location_t, tree, tree, bool, size_t *); -extern void extract_array_notation_exprs (tree, bool, vec **); -extern void replace_array_notations (tree *, bool, vec *, - vec *); -extern tree find_inv_trees (tree *, int *, void *); -extern tree replace_inv_trees (tree *, int *, void *); -extern tree find_correct_array_notation_type (tree op); -extern void cilkplus_extract_an_triplets (vec *, size_t, size_t, - vec > *); -extern vec *fix_sec_implicit_args - (location_t, vec *, vec, size_t, tree); - -/* In cilk.c. */ -extern tree insert_cilk_frame (tree); -extern void cilk_init_builtins (void); -extern int gimplify_cilk_spawn (tree *); -extern void cilk_install_body_with_frame_cleanup (tree, tree, void *); -extern bool cilk_detect_spawn_and_unwrap (tree *); -extern bool cilk_set_spawn_marker (location_t, tree); -extern tree build_cilk_sync (void); -extern tree build_cilk_spawn (location_t, tree); -extern tree make_cilk_frame (tree); -extern tree create_cilk_function_exit (tree, bool, bool); -extern tree cilk_install_body_pedigree_operations (tree); -extern void cilk_outline (tree, tree *, void *); -extern bool contains_cilk_spawn_stmt (tree); -extern tree cilk_for_number_of_iterations (tree); -extern bool check_no_cilk (tree, const char *, const char *, - location_t loc = UNKNOWN_LOCATION); -#endif /* ! GCC_C_COMMON_H */ diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/c-family/c-objc.h b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/c-family/c-objc.h deleted file mode 100644 index 656b6de..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/c-family/c-objc.h +++ /dev/null @@ -1,114 +0,0 @@ -/* Definitions of Objective-C front-end entry points used for C and C++. - Copyright (C) 1987-2015 Free Software Foundation, Inc. - -This file is part of GCC. - -GCC is free software; you can redistribute it and/or modify it under -the terms of the GNU General Public License as published by the Free -Software Foundation; either version 3, or (at your option) any later -version. - -GCC is distributed in the hope that it will be useful, but WITHOUT ANY -WARRANTY; without even the implied warranty of MERCHANTABILITY or -FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -for more details. - -You should have received a copy of the GNU General Public License -along with GCC; see the file COPYING3. If not see -. */ - -#ifndef GCC_C_COMMON_OBJC_H -#define GCC_C_COMMON_OBJC_H - -/* ObjC ivar visibility types. */ -typedef enum objc_ivar_visibility_kind { - OBJC_IVAR_VIS_PROTECTED = 0, - OBJC_IVAR_VIS_PUBLIC = 1, - OBJC_IVAR_VIS_PRIVATE = 2, - OBJC_IVAR_VIS_PACKAGE = 3 -} objc_ivar_visibility_kind; - -/* Objective-C / Objective-C++ entry points. */ - -/* The following ObjC/ObjC++ functions are called by the C and/or C++ - front-ends; they all must have corresponding stubs in stub-objc.c. */ -extern void objc_write_global_declarations (void); -extern tree objc_is_class_name (tree); -extern tree objc_is_object_ptr (tree); -extern void objc_check_decl (tree); -extern void objc_check_global_decl (tree); -extern tree objc_common_type (tree, tree); -extern bool objc_compare_types (tree, tree, int, tree); -extern bool objc_have_common_type (tree, tree, int, tree); -extern bool objc_diagnose_private_ivar (tree); -extern void objc_volatilize_decl (tree); -extern tree objc_rewrite_function_call (tree, tree); -extern tree objc_message_selector (void); -extern tree objc_lookup_ivar (tree, tree); -extern void objc_clear_super_receiver (void); -extern int objc_is_public (tree, tree); -extern tree objc_is_id (tree); -extern void objc_declare_alias (tree, tree); -extern void objc_declare_class (tree); -extern void objc_declare_protocol (tree, tree); -extern tree objc_build_message_expr (tree, tree); -extern tree objc_finish_message_expr (tree, tree, tree, tree*); -extern tree objc_build_selector_expr (location_t, tree); -extern tree objc_build_protocol_expr (tree); -extern tree objc_build_encode_expr (tree); -extern tree objc_build_string_object (tree); -extern tree objc_get_protocol_qualified_type (tree, tree); -extern tree objc_get_class_reference (tree); -extern tree objc_get_class_ivars (tree); -extern bool objc_detect_field_duplicates (bool); -extern void objc_start_class_interface (tree, tree, tree, tree); -extern void objc_start_category_interface (tree, tree, tree, tree); -extern void objc_start_protocol (tree, tree, tree); -extern void objc_continue_interface (void); -extern void objc_finish_interface (void); -extern void objc_start_class_implementation (tree, tree); -extern void objc_start_category_implementation (tree, tree); -extern void objc_continue_implementation (void); -extern void objc_finish_implementation (void); -extern void objc_set_visibility (objc_ivar_visibility_kind); -extern tree objc_build_method_signature (bool, tree, tree, tree, bool); -extern void objc_add_method_declaration (bool, tree, tree); -extern bool objc_start_method_definition (bool, tree, tree, tree); -extern void objc_finish_method_definition (tree); -extern void objc_add_instance_variable (tree); -extern tree objc_build_keyword_decl (tree, tree, tree, tree); -extern tree objc_build_throw_stmt (location_t, tree); -extern void objc_begin_try_stmt (location_t, tree); -extern tree objc_finish_try_stmt (void); -extern void objc_begin_catch_clause (tree); -extern void objc_finish_catch_clause (void); -extern void objc_build_finally_clause (location_t, tree); -extern tree objc_build_synchronized (location_t, tree, tree); -extern int objc_static_init_needed_p (void); -extern tree objc_generate_static_init_call (tree); -extern tree objc_generate_write_barrier (tree, enum tree_code, tree); -extern void objc_set_method_opt (bool); -extern void objc_finish_foreach_loop (location_t, tree, tree, tree, tree, tree); -extern bool objc_method_decl (enum tree_code); -extern void objc_add_property_declaration (location_t, tree, bool, bool, bool, - bool, bool, bool, tree, tree); -extern tree objc_maybe_build_component_ref (tree, tree); -extern tree objc_build_class_component_ref (tree, tree); -extern tree objc_maybe_build_modify_expr (tree, tree); -extern tree objc_build_incr_expr_for_property_ref (location_t, enum tree_code, - tree, tree); -extern void objc_add_synthesize_declaration (location_t, tree); -extern void objc_add_dynamic_declaration (location_t, tree); -extern const char * objc_maybe_printable_name (tree, int); -extern bool objc_is_property_ref (tree); -extern bool objc_string_ref_type_p (tree); -extern void objc_check_format_arg (tree, tree); -extern void objc_finish_function (void); -extern void objc_maybe_warn_exceptions (location_t); - -/* The following are provided by the C and C++ front-ends, and called by - ObjC/ObjC++. */ -extern void *objc_get_current_scope (void); -extern void objc_mark_locals_volatile (void *); - -#endif /* ! GCC_C_COMMON_OBJC_H */ diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/c-family/c-pragma.h b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/c-family/c-pragma.h deleted file mode 100644 index eff94c1..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/c-family/c-pragma.h +++ /dev/null @@ -1,236 +0,0 @@ -/* Pragma related interfaces. - Copyright (C) 1995-2015 Free Software Foundation, Inc. - -This file is part of GCC. - -GCC is free software; you can redistribute it and/or modify it under -the terms of the GNU General Public License as published by the Free -Software Foundation; either version 3, or (at your option) any later -version. - -GCC is distributed in the hope that it will be useful, but WITHOUT ANY -WARRANTY; without even the implied warranty of MERCHANTABILITY or -FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -for more details. - -You should have received a copy of the GNU General Public License -along with GCC; see the file COPYING3. If not see -. */ - -#ifndef GCC_C_PRAGMA_H -#define GCC_C_PRAGMA_H - -#include "cpplib.h" /* For enum cpp_ttype. */ - -/* Pragma identifiers built in to the front end parsers. Identifiers - for ancillary handlers will follow these. */ -typedef enum pragma_kind { - PRAGMA_NONE = 0, - - PRAGMA_OACC_CACHE, - PRAGMA_OACC_DATA, - PRAGMA_OACC_ENTER_DATA, - PRAGMA_OACC_EXIT_DATA, - PRAGMA_OACC_KERNELS, - PRAGMA_OACC_LOOP, - PRAGMA_OACC_PARALLEL, - PRAGMA_OACC_UPDATE, - PRAGMA_OACC_WAIT, - PRAGMA_OMP_ATOMIC, - PRAGMA_OMP_BARRIER, - PRAGMA_OMP_CANCEL, - PRAGMA_OMP_CANCELLATION_POINT, - PRAGMA_OMP_CRITICAL, - PRAGMA_OMP_DECLARE_REDUCTION, - PRAGMA_OMP_DISTRIBUTE, - PRAGMA_OMP_END_DECLARE_TARGET, - PRAGMA_OMP_FLUSH, - PRAGMA_OMP_FOR, - PRAGMA_OMP_MASTER, - PRAGMA_OMP_ORDERED, - PRAGMA_OMP_PARALLEL, - PRAGMA_OMP_SECTION, - PRAGMA_OMP_SECTIONS, - PRAGMA_OMP_SIMD, - PRAGMA_OMP_SINGLE, - PRAGMA_OMP_TARGET, - PRAGMA_OMP_TASK, - PRAGMA_OMP_TASKGROUP, - PRAGMA_OMP_TASKWAIT, - PRAGMA_OMP_TASKYIELD, - PRAGMA_OMP_THREADPRIVATE, - PRAGMA_OMP_TEAMS, - - /* Top level clause to handle all Cilk Plus pragma simd clauses. */ - PRAGMA_CILK_SIMD, - - /* This pragma handles setting of grainsize for a _Cilk_for. */ - PRAGMA_CILK_GRAINSIZE, - - PRAGMA_GCC_PCH_PREPROCESS, - PRAGMA_IVDEP, - - PRAGMA_FIRST_EXTERNAL -} pragma_kind; - - -/* All clauses defined by OpenACC 2.0, and OpenMP 2.5, 3.0, 3.1, and 4.0. - Used internally by both C and C++ parsers. */ -typedef enum pragma_omp_clause { - PRAGMA_OMP_CLAUSE_NONE = 0, - - PRAGMA_OMP_CLAUSE_ALIGNED, - PRAGMA_OMP_CLAUSE_COLLAPSE, - PRAGMA_OMP_CLAUSE_COPYIN, - PRAGMA_OMP_CLAUSE_COPYPRIVATE, - PRAGMA_OMP_CLAUSE_DEFAULT, - PRAGMA_OMP_CLAUSE_DEPEND, - PRAGMA_OMP_CLAUSE_DEVICE, - PRAGMA_OMP_CLAUSE_DIST_SCHEDULE, - PRAGMA_OMP_CLAUSE_FINAL, - PRAGMA_OMP_CLAUSE_FIRSTPRIVATE, - PRAGMA_OMP_CLAUSE_FOR, - PRAGMA_OMP_CLAUSE_FROM, - PRAGMA_OMP_CLAUSE_IF, - PRAGMA_OMP_CLAUSE_INBRANCH, - PRAGMA_OMP_CLAUSE_LASTPRIVATE, - PRAGMA_OMP_CLAUSE_LINEAR, - PRAGMA_OMP_CLAUSE_MAP, - PRAGMA_OMP_CLAUSE_MERGEABLE, - PRAGMA_OMP_CLAUSE_NOTINBRANCH, - PRAGMA_OMP_CLAUSE_NOWAIT, - PRAGMA_OMP_CLAUSE_NUM_TEAMS, - PRAGMA_OMP_CLAUSE_NUM_THREADS, - PRAGMA_OMP_CLAUSE_ORDERED, - PRAGMA_OMP_CLAUSE_PARALLEL, - PRAGMA_OMP_CLAUSE_PRIVATE, - PRAGMA_OMP_CLAUSE_PROC_BIND, - PRAGMA_OMP_CLAUSE_REDUCTION, - PRAGMA_OMP_CLAUSE_SAFELEN, - PRAGMA_OMP_CLAUSE_SCHEDULE, - PRAGMA_OMP_CLAUSE_SECTIONS, - PRAGMA_OMP_CLAUSE_SHARED, - PRAGMA_OMP_CLAUSE_SIMDLEN, - PRAGMA_OMP_CLAUSE_TASKGROUP, - PRAGMA_OMP_CLAUSE_THREAD_LIMIT, - PRAGMA_OMP_CLAUSE_TO, - PRAGMA_OMP_CLAUSE_UNIFORM, - PRAGMA_OMP_CLAUSE_UNTIED, - - /* Clauses for Cilk Plus SIMD-enabled function. */ - PRAGMA_CILK_CLAUSE_NOMASK, - PRAGMA_CILK_CLAUSE_MASK, - PRAGMA_CILK_CLAUSE_VECTORLENGTH, - PRAGMA_CILK_CLAUSE_NONE = PRAGMA_OMP_CLAUSE_NONE, - PRAGMA_CILK_CLAUSE_LINEAR = PRAGMA_OMP_CLAUSE_LINEAR, - PRAGMA_CILK_CLAUSE_PRIVATE = PRAGMA_OMP_CLAUSE_PRIVATE, - PRAGMA_CILK_CLAUSE_FIRSTPRIVATE = PRAGMA_OMP_CLAUSE_FIRSTPRIVATE, - PRAGMA_CILK_CLAUSE_LASTPRIVATE = PRAGMA_OMP_CLAUSE_LASTPRIVATE, - PRAGMA_CILK_CLAUSE_REDUCTION = PRAGMA_OMP_CLAUSE_REDUCTION, - PRAGMA_CILK_CLAUSE_UNIFORM = PRAGMA_OMP_CLAUSE_UNIFORM, - - /* Clauses for OpenACC. */ - PRAGMA_OACC_CLAUSE_ASYNC = PRAGMA_CILK_CLAUSE_VECTORLENGTH + 1, - PRAGMA_OACC_CLAUSE_AUTO, - PRAGMA_OACC_CLAUSE_COPY, - PRAGMA_OACC_CLAUSE_COPYOUT, - PRAGMA_OACC_CLAUSE_CREATE, - PRAGMA_OACC_CLAUSE_DELETE, - PRAGMA_OACC_CLAUSE_DEVICEPTR, - PRAGMA_OACC_CLAUSE_GANG, - PRAGMA_OACC_CLAUSE_HOST, - PRAGMA_OACC_CLAUSE_NUM_GANGS, - PRAGMA_OACC_CLAUSE_NUM_WORKERS, - PRAGMA_OACC_CLAUSE_PRESENT, - PRAGMA_OACC_CLAUSE_PRESENT_OR_COPY, - PRAGMA_OACC_CLAUSE_PRESENT_OR_COPYIN, - PRAGMA_OACC_CLAUSE_PRESENT_OR_COPYOUT, - PRAGMA_OACC_CLAUSE_PRESENT_OR_CREATE, - PRAGMA_OACC_CLAUSE_SELF, - PRAGMA_OACC_CLAUSE_SEQ, - PRAGMA_OACC_CLAUSE_VECTOR, - PRAGMA_OACC_CLAUSE_VECTOR_LENGTH, - PRAGMA_OACC_CLAUSE_WAIT, - PRAGMA_OACC_CLAUSE_WORKER, - PRAGMA_OACC_CLAUSE_COLLAPSE = PRAGMA_OMP_CLAUSE_COLLAPSE, - PRAGMA_OACC_CLAUSE_COPYIN = PRAGMA_OMP_CLAUSE_COPYIN, - PRAGMA_OACC_CLAUSE_DEVICE = PRAGMA_OMP_CLAUSE_DEVICE, - PRAGMA_OACC_CLAUSE_FIRSTPRIVATE = PRAGMA_OMP_CLAUSE_FIRSTPRIVATE, - PRAGMA_OACC_CLAUSE_IF = PRAGMA_OMP_CLAUSE_IF, - PRAGMA_OACC_CLAUSE_PRIVATE = PRAGMA_OMP_CLAUSE_PRIVATE, - PRAGMA_OACC_CLAUSE_REDUCTION = PRAGMA_OMP_CLAUSE_REDUCTION -} pragma_omp_clause; - -extern struct cpp_reader* parse_in; - -/* It's safe to always leave visibility pragma enabled as if - visibility is not supported on the host OS platform the - statements are ignored. */ -extern void push_visibility (const char *, int); -extern bool pop_visibility (int); - -extern void init_pragma (void); - -/* Front-end wrappers for pragma registration. */ -typedef void (*pragma_handler_1arg)(struct cpp_reader *); -/* A second pragma handler, which adds a void * argument allowing to pass extra - data to the handler. */ -typedef void (*pragma_handler_2arg)(struct cpp_reader *, void *); - -/* This union allows to abstract the different handlers. */ -union gen_pragma_handler { - pragma_handler_1arg handler_1arg; - pragma_handler_2arg handler_2arg; -}; -/* Internally used to keep the data of the handler. */ -struct internal_pragma_handler_d { - union gen_pragma_handler handler; - /* Permits to know if handler is a pragma_handler_1arg (extra_data is false) - or a pragma_handler_2arg (extra_data is true). */ - bool extra_data; - /* A data field which can be used when extra_data is true. */ - void * data; -}; -typedef struct internal_pragma_handler_d internal_pragma_handler; - -extern void c_register_pragma (const char *space, const char *name, - pragma_handler_1arg handler); -extern void c_register_pragma_with_data (const char *space, const char *name, - pragma_handler_2arg handler, - void *data); - -extern void c_register_pragma_with_expansion (const char *space, - const char *name, - pragma_handler_1arg handler); -extern void c_register_pragma_with_expansion_and_data (const char *space, - const char *name, - pragma_handler_2arg handler, - void *data); -extern void c_invoke_pragma_handler (unsigned int); - -extern void maybe_apply_pragma_weak (tree); -extern void maybe_apply_pending_pragma_weaks (void); -extern tree maybe_apply_renaming_pragma (tree, tree); -extern void add_to_renaming_pragma_list (tree, tree); - -extern enum cpp_ttype pragma_lex (tree *); - -/* Flags for use with c_lex_with_flags. The values here were picked - so that 0 means to translate and join strings. */ -#define C_LEX_STRING_NO_TRANSLATE 1 /* Do not lex strings into - execution character set. */ -#define C_LEX_STRING_NO_JOIN 2 /* Do not concatenate strings - nor translate them into execution - character set. */ - -/* This is not actually available to pragma parsers. It's merely a - convenient location to declare this function for c-lex, after - having enum cpp_ttype declared. */ -extern enum cpp_ttype c_lex_with_flags (tree *, location_t *, unsigned char *, - int); - -extern void c_pp_lookup_pragma (unsigned int, const char **, const char **); - -extern GTY(()) tree pragma_extern_prefix; - -#endif /* GCC_C_PRAGMA_H */ diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/c-family/c-pretty-print.h b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/c-family/c-pretty-print.h deleted file mode 100644 index c78f799..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/c-family/c-pretty-print.h +++ /dev/null @@ -1,139 +0,0 @@ -/* Various declarations for the C and C++ pretty-printers. - Copyright (C) 2002-2015 Free Software Foundation, Inc. - Contributed by Gabriel Dos Reis - -This file is part of GCC. - -GCC is free software; you can redistribute it and/or modify it under -the terms of the GNU General Public License as published by the Free -Software Foundation; either version 3, or (at your option) any later -version. - -GCC is distributed in the hope that it will be useful, but WITHOUT ANY -WARRANTY; without even the implied warranty of MERCHANTABILITY or -FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -for more details. - -You should have received a copy of the GNU General Public License -along with GCC; see the file COPYING3. If not see -. */ - -#ifndef GCC_C_PRETTY_PRINTER -#define GCC_C_PRETTY_PRINTER - -#include "tree.h" -#include "c-family/c-common.h" -#include "pretty-print.h" - - -enum pp_c_pretty_print_flags - { - pp_c_flag_abstract = 1 << 1, - pp_c_flag_gnu_v3 = 1 << 2, - pp_c_flag_last_bit = 3 - }; - - -/* The data type used to bundle information necessary for pretty-printing - a C or C++ entity. */ -struct c_pretty_printer; - -/* The type of a C pretty-printer 'member' function. */ -typedef void (*c_pretty_print_fn) (c_pretty_printer *, tree); - -/* The datatype that contains information necessary for pretty-printing - a tree that represents a C construct. Any pretty-printer for a - language using C syntax can derive from this datatype and reuse - facilities provided here. A derived pretty-printer can override - any function listed in the vtable below. See cp/cxx-pretty-print.h - and cp/cxx-pretty-print.c for an example of derivation. */ -struct c_pretty_printer : pretty_printer -{ - c_pretty_printer (); - - // Format string, possibly translated. - void translate_string (const char *); - - virtual void constant (tree); - virtual void id_expression (tree); - virtual void primary_expression (tree); - virtual void postfix_expression (tree); - virtual void unary_expression (tree); - virtual void multiplicative_expression (tree); - virtual void conditional_expression (tree); - virtual void assignment_expression (tree); - virtual void expression (tree); - - virtual void type_id (tree); - virtual void statement (tree); - - virtual void declaration (tree); - virtual void declaration_specifiers (tree); - virtual void simple_type_specifier (tree); - virtual void function_specifier (tree); - virtual void storage_class_specifier (tree); - virtual void declarator (tree); - virtual void direct_declarator (tree); - virtual void abstract_declarator (tree); - virtual void direct_abstract_declarator (tree); - - virtual void initializer (tree); - /* Points to the first element of an array of offset-list. - Not used yet. */ - int *offset_list; - - pp_flags flags; - - /* These must be overridden by each of the C and C++ front-end to - reflect their understanding of syntactic productions when they differ. */ - c_pretty_print_fn type_specifier_seq; - c_pretty_print_fn ptr_operator; - c_pretty_print_fn parameter_list; -}; - -#define pp_c_tree_identifier(PPI, ID) \ - pp_c_identifier (PPI, IDENTIFIER_POINTER (ID)) - -#define pp_type_specifier_seq(PP, D) (PP)->type_specifier_seq (PP, D) -#define pp_ptr_operator(PP, D) (PP)->ptr_operator (PP, D) -#define pp_parameter_list(PP, T) (PP)->parameter_list (PP, T) - -void pp_c_whitespace (c_pretty_printer *); -void pp_c_left_paren (c_pretty_printer *); -void pp_c_right_paren (c_pretty_printer *); -void pp_c_left_brace (c_pretty_printer *); -void pp_c_right_brace (c_pretty_printer *); -void pp_c_left_bracket (c_pretty_printer *); -void pp_c_right_bracket (c_pretty_printer *); -void pp_c_dot (c_pretty_printer *); -void pp_c_ampersand (c_pretty_printer *); -void pp_c_star (c_pretty_printer *); -void pp_c_arrow (c_pretty_printer *); -void pp_c_semicolon (c_pretty_printer *); -void pp_c_complement (c_pretty_printer *); -void pp_c_exclamation (c_pretty_printer *); -void pp_c_space_for_pointer_operator (c_pretty_printer *, tree); - -/* Declarations. */ -void pp_c_tree_decl_identifier (c_pretty_printer *, tree); -void pp_c_function_definition (c_pretty_printer *, tree); -void pp_c_attributes (c_pretty_printer *, tree); -void pp_c_attributes_display (c_pretty_printer *, tree); -void pp_c_cv_qualifiers (c_pretty_printer *pp, int qualifiers, bool func_type); -void pp_c_type_qualifier_list (c_pretty_printer *, tree); -void pp_c_parameter_type_list (c_pretty_printer *, tree); -void pp_c_specifier_qualifier_list (c_pretty_printer *, tree); -/* Expressions. */ -void pp_c_logical_or_expression (c_pretty_printer *, tree); -void pp_c_expression_list (c_pretty_printer *, tree); -void pp_c_constructor_elts (c_pretty_printer *, vec *); -void pp_c_call_argument_list (c_pretty_printer *, tree); -void pp_c_cast_expression (c_pretty_printer *, tree); -void pp_c_init_declarator (c_pretty_printer *, tree); -void pp_c_ws_string (c_pretty_printer *, const char *); -void pp_c_identifier (c_pretty_printer *, const char *); -void pp_c_string_literal (c_pretty_printer *, tree); - -void print_c_tree (FILE *file, tree t); - -#endif /* GCC_C_PRETTY_PRINTER */ diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/c-tree.h b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/c-tree.h deleted file mode 100644 index 885bfd6..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/c-tree.h +++ /dev/null @@ -1,713 +0,0 @@ -/* Definitions for C parsing and type checking. - Copyright (C) 1987-2015 Free Software Foundation, Inc. - -This file is part of GCC. - -GCC is free software; you can redistribute it and/or modify it under -the terms of the GNU General Public License as published by the Free -Software Foundation; either version 3, or (at your option) any later -version. - -GCC is distributed in the hope that it will be useful, but WITHOUT ANY -WARRANTY; without even the implied warranty of MERCHANTABILITY or -FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -for more details. - -You should have received a copy of the GNU General Public License -along with GCC; see the file COPYING3. If not see -. */ - -#ifndef GCC_C_TREE_H -#define GCC_C_TREE_H - -#include "c-family/c-common.h" -#include "diagnostic.h" - -/* struct lang_identifier is private to c-decl.c, but langhooks.c needs to - know how big it is. This is sanity-checked in c-decl.c. */ -#define C_SIZEOF_STRUCT_LANG_IDENTIFIER \ - (sizeof (struct c_common_identifier) + 3 * sizeof (void *)) - -/* In a RECORD_TYPE or UNION_TYPE, nonzero if any component is read-only. */ -#define C_TYPE_FIELDS_READONLY(TYPE) TREE_LANG_FLAG_1 (TYPE) - -/* In a RECORD_TYPE or UNION_TYPE, nonzero if any component is volatile. */ -#define C_TYPE_FIELDS_VOLATILE(TYPE) TREE_LANG_FLAG_2 (TYPE) - -/* In a RECORD_TYPE or UNION_TYPE or ENUMERAL_TYPE - nonzero if the definition of the type has already started. */ -#define C_TYPE_BEING_DEFINED(TYPE) TYPE_LANG_FLAG_0 (TYPE) - -/* In an incomplete RECORD_TYPE or UNION_TYPE, a list of variable - declarations whose type would be completed by completing that type. */ -#define C_TYPE_INCOMPLETE_VARS(TYPE) TYPE_VFIELD (TYPE) - -/* In an IDENTIFIER_NODE, nonzero if this identifier is actually a - keyword. C_RID_CODE (node) is then the RID_* value of the keyword, - and C_RID_YYCODE is the token number wanted by Yacc. */ -#define C_IS_RESERVED_WORD(ID) TREE_LANG_FLAG_0 (ID) - -/* Record whether a type or decl was written with nonconstant size. - Note that TYPE_SIZE may have simplified to a constant. */ -#define C_TYPE_VARIABLE_SIZE(TYPE) TYPE_LANG_FLAG_1 (TYPE) -#define C_DECL_VARIABLE_SIZE(TYPE) DECL_LANG_FLAG_0 (TYPE) - -/* Record whether a type is defined inside a struct or union type. - This is used for -Wc++-compat. */ -#define C_TYPE_DEFINED_IN_STRUCT(TYPE) TYPE_LANG_FLAG_2 (TYPE) - -/* Record whether an "incomplete type" error was given for the type. */ -#define C_TYPE_ERROR_REPORTED(TYPE) TYPE_LANG_FLAG_3 (TYPE) - -/* Record whether a typedef for type `int' was actually `signed int'. */ -#define C_TYPEDEF_EXPLICITLY_SIGNED(EXP) DECL_LANG_FLAG_1 (EXP) - -/* For a FUNCTION_DECL, nonzero if it was defined without an explicit - return type. */ -#define C_FUNCTION_IMPLICIT_INT(EXP) DECL_LANG_FLAG_1 (EXP) - -/* For a FUNCTION_DECL, nonzero if it was an implicit declaration. */ -#define C_DECL_IMPLICIT(EXP) DECL_LANG_FLAG_2 (EXP) - -/* For a PARM_DECL, nonzero if it was declared as an array. */ -#define C_ARRAY_PARAMETER(NODE) DECL_LANG_FLAG_0 (NODE) - -/* For FUNCTION_DECLs, evaluates true if the decl is built-in but has - been declared. */ -#define C_DECL_DECLARED_BUILTIN(EXP) \ - DECL_LANG_FLAG_3 (FUNCTION_DECL_CHECK (EXP)) - -/* For FUNCTION_DECLs, evaluates true if the decl is built-in, has a - built-in prototype and does not have a non-built-in prototype. */ -#define C_DECL_BUILTIN_PROTOTYPE(EXP) \ - DECL_LANG_FLAG_6 (FUNCTION_DECL_CHECK (EXP)) - -/* Record whether a decl was declared register. This is strictly a - front-end flag, whereas DECL_REGISTER is used for code generation; - they may differ for structures with volatile fields. */ -#define C_DECL_REGISTER(EXP) DECL_LANG_FLAG_4 (EXP) - -/* Record whether a decl was used in an expression anywhere except an - unevaluated operand of sizeof / typeof / alignof. This is only - used for functions declared static but not defined, though outside - sizeof and typeof it is set for other function decls as well. */ -#define C_DECL_USED(EXP) DECL_LANG_FLAG_5 (FUNCTION_DECL_CHECK (EXP)) - -/* Record whether a variable has been declared threadprivate by - #pragma omp threadprivate. */ -#define C_DECL_THREADPRIVATE_P(DECL) DECL_LANG_FLAG_3 (VAR_DECL_CHECK (DECL)) - -/* Nonzero for a decl which either doesn't exist or isn't a prototype. - N.B. Could be simplified if all built-in decls had complete prototypes - (but this is presently difficult because some of them need FILE*). */ -#define C_DECL_ISNT_PROTOTYPE(EXP) \ - (EXP == 0 \ - || (!prototype_p (TREE_TYPE (EXP)) \ - && !DECL_BUILT_IN (EXP))) - -/* For FUNCTION_TYPE, a hidden list of types of arguments. The same as - TYPE_ARG_TYPES for functions with prototypes, but created for functions - without prototypes. */ -#define TYPE_ACTUAL_ARG_TYPES(NODE) TYPE_LANG_SLOT_1 (NODE) - -/* For a CONSTRUCTOR, whether some initializer contains a - subexpression meaning it is not a constant expression. */ -#define CONSTRUCTOR_NON_CONST(EXPR) TREE_LANG_FLAG_1 (CONSTRUCTOR_CHECK (EXPR)) - -/* Record parser information about an expression that is irrelevant - for code generation alongside a tree representing its value. */ -struct c_expr -{ - /* The value of the expression. */ - tree value; - /* Record the original unary/binary operator of an expression, which may - have been changed by fold, STRING_CST for unparenthesized string - constants, C_MAYBE_CONST_EXPR for __builtin_constant_p calls - (even if parenthesized), for subexpressions, and for non-constant - initializers, or ERROR_MARK for other expressions (including - parenthesized expressions). */ - enum tree_code original_code; - /* If not NULL, the original type of an expression. This will - differ from the type of the value field for an enum constant. - The type of an enum constant is a plain integer type, but this - field will be the enum type. */ - tree original_type; -}; - -/* Type alias for struct c_expr. This allows to use the structure - inside the VEC types. */ -typedef struct c_expr c_expr_t; - -/* A kind of type specifier. Note that this information is currently - only used to distinguish tag definitions, tag references and typeof - uses. */ -enum c_typespec_kind { - /* No typespec. This appears only in struct c_declspec. */ - ctsk_none, - /* A reserved keyword type specifier. */ - ctsk_resword, - /* A reference to a tag, previously declared, such as "struct foo". - This includes where the previous declaration was as a different - kind of tag, in which case this is only valid if shadowing that - tag in an inner scope. */ - ctsk_tagref, - /* A reference to a tag, not previously declared in a visible - scope. */ - ctsk_tagfirstref, - /* A definition of a tag such as "struct foo { int a; }". */ - ctsk_tagdef, - /* A typedef name. */ - ctsk_typedef, - /* An ObjC-specific kind of type specifier. */ - ctsk_objc, - /* A typeof specifier, or _Atomic ( type-name ). */ - ctsk_typeof -}; - -/* A type specifier: this structure is created in the parser and - passed to declspecs_add_type only. */ -struct c_typespec { - /* What kind of type specifier this is. */ - enum c_typespec_kind kind; - /* Whether the expression has operands suitable for use in constant - expressions. */ - bool expr_const_operands; - /* The specifier itself. */ - tree spec; - /* An expression to be evaluated before the type specifier, in the - case of typeof specifiers, or NULL otherwise or if no such - expression is required for a particular typeof specifier. In - particular, when typeof is applied to an expression of variably - modified type, that expression must be evaluated in order to - determine array sizes that form part of the type, but the - expression itself (as opposed to the array sizes) forms no part - of the type and so needs to be recorded separately. */ - tree expr; -}; - -/* A storage class specifier. */ -enum c_storage_class { - csc_none, - csc_auto, - csc_extern, - csc_register, - csc_static, - csc_typedef -}; - -/* A type specifier keyword "void", "_Bool", "char", "int", "float", - "double", "_Decimal32", "_Decimal64", "_Decimal128", "_Fract", "_Accum", - or none of these. */ -enum c_typespec_keyword { - cts_none, - cts_void, - cts_bool, - cts_char, - cts_int, - cts_float, - cts_int_n, - cts_double, - cts_dfloat32, - cts_dfloat64, - cts_dfloat128, - cts_fract, - cts_accum, - cts_auto_type -}; - -/* This enum lists all the possible declarator specifiers, storage - class or attribute that a user can write. There is at least one - enumerator per possible declarator specifier in the struct - c_declspecs below. - - It is used to index the array of declspec locations in struct - c_declspecs. */ -enum c_declspec_word { - cdw_typespec /* A catch-all for a typespec. */, - cdw_storage_class /* A catch-all for a storage class */, - cdw_attributes, - cdw_typedef, - cdw_explicit_signed, - cdw_deprecated, - cdw_default_int, - cdw_long, - cdw_long_long, - cdw_short, - cdw_signed, - cdw_unsigned, - cdw_complex, - cdw_inline, - cdw_noreturn, - cdw_thread, - cdw_const, - cdw_volatile, - cdw_restrict, - cdw_saturating, - cdw_alignas, - cdw_address_space, - cdw_number_of_elements /* This one must always be the last - enumerator. */ -}; - -/* A sequence of declaration specifiers in C. When a new declaration - specifier is added, please update the enum c_declspec_word above - accordingly. */ -struct c_declspecs { - source_location locations[cdw_number_of_elements]; - /* The type specified, if a single type specifier such as a struct, - union or enum specifier, typedef name or typeof specifies the - whole type, or NULL_TREE if none or a keyword such as "void" or - "char" is used. Does not include qualifiers. */ - tree type; - /* Any expression to be evaluated before the type, from a typeof - specifier. */ - tree expr; - /* The attributes from a typedef decl. */ - tree decl_attr; - /* When parsing, the attributes. Outside the parser, this will be - NULL; attributes (possibly from multiple lists) will be passed - separately. */ - tree attrs; - /* The base-2 log of the greatest alignment required by an _Alignas - specifier, in bytes, or -1 if no such specifiers with nonzero - alignment. */ - int align_log; - /* For the __intN declspec, this stores the index into the int_n_* arrays. */ - int int_n_idx; - /* The storage class specifier, or csc_none if none. */ - enum c_storage_class storage_class; - /* Any type specifier keyword used such as "int", not reflecting - modifiers such as "short", or cts_none if none. */ - ENUM_BITFIELD (c_typespec_keyword) typespec_word : 8; - /* The kind of type specifier if one has been seen, ctsk_none - otherwise. */ - ENUM_BITFIELD (c_typespec_kind) typespec_kind : 3; - /* Whether any expressions in typeof specifiers may appear in - constant expressions. */ - BOOL_BITFIELD expr_const_operands : 1; - /* Whether any declaration specifiers have been seen at all. */ - BOOL_BITFIELD declspecs_seen_p : 1; - /* Whether something other than a storage class specifier or - attribute has been seen. This is used to warn for the - obsolescent usage of storage class specifiers other than at the - start of the list. (Doing this properly would require function - specifiers to be handled separately from storage class - specifiers.) */ - BOOL_BITFIELD non_sc_seen_p : 1; - /* Whether the type is specified by a typedef or typeof name. */ - BOOL_BITFIELD typedef_p : 1; - /* Whether the type is explicitly "signed" or specified by a typedef - whose type is explicitly "signed". */ - BOOL_BITFIELD explicit_signed_p : 1; - /* Whether the specifiers include a deprecated typedef. */ - BOOL_BITFIELD deprecated_p : 1; - /* Whether the type defaulted to "int" because there were no type - specifiers. */ - BOOL_BITFIELD default_int_p : 1; - /* Whether "long" was specified. */ - BOOL_BITFIELD long_p : 1; - /* Whether "long" was specified more than once. */ - BOOL_BITFIELD long_long_p : 1; - /* Whether "short" was specified. */ - BOOL_BITFIELD short_p : 1; - /* Whether "signed" was specified. */ - BOOL_BITFIELD signed_p : 1; - /* Whether "unsigned" was specified. */ - BOOL_BITFIELD unsigned_p : 1; - /* Whether "complex" was specified. */ - BOOL_BITFIELD complex_p : 1; - /* Whether "inline" was specified. */ - BOOL_BITFIELD inline_p : 1; - /* Whether "_Noreturn" was speciied. */ - BOOL_BITFIELD noreturn_p : 1; - /* Whether "__thread" or "_Thread_local" was specified. */ - BOOL_BITFIELD thread_p : 1; - /* Whether "__thread" rather than "_Thread_local" was specified. */ - BOOL_BITFIELD thread_gnu_p : 1; - /* Whether "const" was specified. */ - BOOL_BITFIELD const_p : 1; - /* Whether "volatile" was specified. */ - BOOL_BITFIELD volatile_p : 1; - /* Whether "restrict" was specified. */ - BOOL_BITFIELD restrict_p : 1; - /* Whether "_Atomic" was specified. */ - BOOL_BITFIELD atomic_p : 1; - /* Whether "_Sat" was specified. */ - BOOL_BITFIELD saturating_p : 1; - /* Whether any alignment specifier (even with zero alignment) was - specified. */ - BOOL_BITFIELD alignas_p : 1; - /* The address space that the declaration belongs to. */ - addr_space_t address_space; -}; - -/* The various kinds of declarators in C. */ -enum c_declarator_kind { - /* An identifier. */ - cdk_id, - /* A function. */ - cdk_function, - /* An array. */ - cdk_array, - /* A pointer. */ - cdk_pointer, - /* Parenthesized declarator with nested attributes. */ - cdk_attrs -}; - -typedef struct c_arg_tag_d { - /* The argument name. */ - tree id; - /* The type of the argument. */ - tree type; -} c_arg_tag; - - -/* Information about the parameters in a function declarator. */ -struct c_arg_info { - /* A list of parameter decls. */ - tree parms; - /* A list of structure, union and enum tags defined. */ - vec *tags; - /* A list of argument types to go in the FUNCTION_TYPE. */ - tree types; - /* A list of non-parameter decls (notably enumeration constants) - defined with the parameters. */ - tree others; - /* A compound expression of VLA sizes from the parameters, or NULL. - In a function definition, these are used to ensure that - side-effects in sizes of arrays converted to pointers (such as a - parameter int i[n++]) take place; otherwise, they are - ignored. */ - tree pending_sizes; - /* True when these arguments had [*]. */ - BOOL_BITFIELD had_vla_unspec : 1; -}; - -/* A declarator. */ -struct c_declarator { - /* The kind of declarator. */ - enum c_declarator_kind kind; - location_t id_loc; /* Currently only set for cdk_id, cdk_array. */ - /* Except for cdk_id, the contained declarator. For cdk_id, NULL. */ - struct c_declarator *declarator; - union { - /* For identifiers, an IDENTIFIER_NODE or NULL_TREE if an abstract - declarator. */ - tree id; - /* For functions. */ - struct c_arg_info *arg_info; - /* For arrays. */ - struct { - /* The array dimension, or NULL for [] and [*]. */ - tree dimen; - /* The qualifiers inside []. */ - int quals; - /* The attributes (currently ignored) inside []. */ - tree attrs; - /* Whether [static] was used. */ - BOOL_BITFIELD static_p : 1; - /* Whether [*] was used. */ - BOOL_BITFIELD vla_unspec_p : 1; - } array; - /* For pointers, the qualifiers on the pointer type. */ - int pointer_quals; - /* For attributes. */ - tree attrs; - } u; -}; - -/* A type name. */ -struct c_type_name { - /* The declaration specifiers. */ - struct c_declspecs *specs; - /* The declarator. */ - struct c_declarator *declarator; -}; - -/* A parameter. */ -struct c_parm { - /* The declaration specifiers, minus any prefix attributes. */ - struct c_declspecs *specs; - /* The attributes. */ - tree attrs; - /* The declarator. */ - struct c_declarator *declarator; -}; - -/* Used when parsing an enum. Initialized by start_enum. */ -struct c_enum_contents -{ - /* While defining an enum type, this is 1 plus the last enumerator - constant value. */ - tree enum_next_value; - - /* Nonzero means that there was overflow computing enum_next_value. */ - int enum_overflow; -}; - -/* A type of reference to a static identifier in an inline - function. */ -enum c_inline_static_type { - /* Identifier with internal linkage used in function that may be an - inline definition (i.e., file-scope static). */ - csi_internal, - /* Modifiable object with static storage duration defined in - function that may be an inline definition (i.e., local - static). */ - csi_modifiable -}; - - -/* in c-parser.c */ -extern void c_parse_init (void); - -/* in c-aux-info.c */ -extern void gen_aux_info_record (tree, int, int, int); - -/* in c-decl.c */ -struct c_spot_bindings; -struct c_struct_parse_info; -extern struct obstack parser_obstack; -extern tree c_break_label; -extern tree c_cont_label; - -extern bool global_bindings_p (void); -extern void push_scope (void); -extern tree pop_scope (void); -extern void c_bindings_start_stmt_expr (struct c_spot_bindings *); -extern void c_bindings_end_stmt_expr (struct c_spot_bindings *); - -extern void record_inline_static (location_t, tree, tree, - enum c_inline_static_type); -extern void c_init_decl_processing (void); -extern void c_print_identifier (FILE *, tree, int); -extern int quals_from_declspecs (const struct c_declspecs *); -extern struct c_declarator *build_array_declarator (location_t, tree, - struct c_declspecs *, - bool, bool); -extern tree build_enumerator (location_t, location_t, struct c_enum_contents *, - tree, tree); -extern tree check_for_loop_decls (location_t, bool); -extern void mark_forward_parm_decls (void); -extern void declare_parm_level (void); -extern void undeclared_variable (location_t, tree); -extern tree lookup_label_for_goto (location_t, tree); -extern tree declare_label (tree); -extern tree define_label (location_t, tree); -extern struct c_spot_bindings *c_get_switch_bindings (void); -extern void c_release_switch_bindings (struct c_spot_bindings *); -extern bool c_check_switch_jump_warnings (struct c_spot_bindings *, - location_t, location_t); -extern void finish_decl (tree, location_t, tree, tree, tree); -extern tree finish_enum (tree, tree, tree); -extern void finish_function (void); -extern tree finish_struct (location_t, tree, tree, tree, - struct c_struct_parse_info *); -extern struct c_arg_info *build_arg_info (void); -extern struct c_arg_info *get_parm_info (bool, tree); -extern tree grokfield (location_t, struct c_declarator *, - struct c_declspecs *, tree, tree *); -extern tree groktypename (struct c_type_name *, tree *, bool *); -extern tree grokparm (const struct c_parm *, tree *); -extern tree implicitly_declare (location_t, tree); -extern void keep_next_level (void); -extern void pending_xref_error (void); -extern void c_push_function_context (void); -extern void c_pop_function_context (void); -extern void push_parm_decl (const struct c_parm *, tree *); -extern struct c_declarator *set_array_declarator_inner (struct c_declarator *, - struct c_declarator *); -extern tree c_builtin_function (tree); -extern tree c_builtin_function_ext_scope (tree); -extern void shadow_tag (const struct c_declspecs *); -extern void shadow_tag_warned (const struct c_declspecs *, int); -extern tree start_enum (location_t, struct c_enum_contents *, tree); -extern int start_function (struct c_declspecs *, struct c_declarator *, tree); -extern tree start_decl (struct c_declarator *, struct c_declspecs *, bool, - tree); -extern tree start_struct (location_t, enum tree_code, tree, - struct c_struct_parse_info **); -extern void store_parm_decls (void); -extern void store_parm_decls_from (struct c_arg_info *); -extern void temp_store_parm_decls (tree, tree); -extern void temp_pop_parm_decls (void); -extern tree xref_tag (enum tree_code, tree); -extern struct c_typespec parser_xref_tag (location_t, enum tree_code, tree); -extern struct c_parm *build_c_parm (struct c_declspecs *, tree, - struct c_declarator *); -extern struct c_declarator *build_attrs_declarator (tree, - struct c_declarator *); -extern struct c_declarator *build_function_declarator (struct c_arg_info *, - struct c_declarator *); -extern struct c_declarator *build_id_declarator (tree); -extern struct c_declarator *make_pointer_declarator (struct c_declspecs *, - struct c_declarator *); -extern struct c_declspecs *build_null_declspecs (void); -extern struct c_declspecs *declspecs_add_qual (source_location, - struct c_declspecs *, tree); -extern struct c_declspecs *declspecs_add_type (location_t, - struct c_declspecs *, - struct c_typespec); -extern struct c_declspecs *declspecs_add_scspec (source_location, - struct c_declspecs *, tree); -extern struct c_declspecs *declspecs_add_attrs (source_location, - struct c_declspecs *, tree); -extern struct c_declspecs *declspecs_add_addrspace (source_location, - struct c_declspecs *, - addr_space_t); -extern struct c_declspecs *declspecs_add_alignas (source_location, - struct c_declspecs *, tree); -extern struct c_declspecs *finish_declspecs (struct c_declspecs *); - -/* in c-objc-common.c */ -extern bool c_objc_common_init (void); -extern bool c_missing_noreturn_ok_p (tree); -extern bool c_warn_unused_global_decl (const_tree); -extern void c_initialize_diagnostics (diagnostic_context *); -extern bool c_vla_unspec_p (tree x, tree fn); - -/* in c-typeck.c */ -extern int in_alignof; -extern int in_sizeof; -extern int in_typeof; - -extern tree c_last_sizeof_arg; - -extern struct c_switch *c_switch_stack; - -extern tree c_objc_common_truthvalue_conversion (location_t, tree); -extern tree require_complete_type (tree); -extern int same_translation_unit_p (const_tree, const_tree); -extern int comptypes (tree, tree); -extern int comptypes_check_different_types (tree, tree, bool *); -extern bool c_vla_type_p (const_tree); -extern bool c_mark_addressable (tree); -extern void c_incomplete_type_error (const_tree, const_tree); -extern tree c_type_promotes_to (tree); -extern struct c_expr default_function_array_conversion (location_t, - struct c_expr); -extern struct c_expr default_function_array_read_conversion (location_t, - struct c_expr); -extern struct c_expr convert_lvalue_to_rvalue (location_t, struct c_expr, - bool, bool); -extern void mark_exp_read (tree); -extern tree composite_type (tree, tree); -extern tree build_component_ref (location_t, tree, tree); -extern tree build_array_ref (location_t, tree, tree); -extern tree build_external_ref (location_t, tree, int, tree *); -extern void pop_maybe_used (bool); -extern struct c_expr c_expr_sizeof_expr (location_t, struct c_expr); -extern struct c_expr c_expr_sizeof_type (location_t, struct c_type_name *); -extern struct c_expr parser_build_unary_op (location_t, enum tree_code, - struct c_expr); -extern struct c_expr parser_build_binary_op (location_t, - enum tree_code, struct c_expr, - struct c_expr); -extern tree build_conditional_expr (location_t, tree, bool, tree, tree, - tree, tree); -extern tree build_compound_expr (location_t, tree, tree); -extern tree c_cast_expr (location_t, struct c_type_name *, tree); -extern tree build_c_cast (location_t, tree, tree); -extern void store_init_value (location_t, tree, tree, tree); -extern void maybe_warn_string_init (location_t, tree, struct c_expr); -extern void start_init (tree, tree, int); -extern void finish_init (void); -extern void really_start_incremental_init (tree); -extern void finish_implicit_inits (location_t, struct obstack *); -extern void push_init_level (location_t, int, struct obstack *); -extern struct c_expr pop_init_level (location_t, int, struct obstack *); -extern void set_init_index (location_t, tree, tree, struct obstack *); -extern void set_init_label (location_t, tree, struct obstack *); -extern void process_init_element (location_t, struct c_expr, bool, - struct obstack *); -extern tree build_compound_literal (location_t, tree, tree, bool); -extern void check_compound_literal_type (location_t, struct c_type_name *); -extern tree c_start_case (location_t, location_t, tree, bool); -extern void c_finish_case (tree, tree); -extern tree build_asm_expr (location_t, tree, tree, tree, tree, tree, bool); -extern tree build_asm_stmt (tree, tree); -extern int c_types_compatible_p (tree, tree); -extern tree c_begin_compound_stmt (bool); -extern tree c_end_compound_stmt (location_t, tree, bool); -extern void c_finish_if_stmt (location_t, tree, tree, tree, bool); -extern void c_finish_loop (location_t, tree, tree, tree, tree, tree, bool); -extern tree c_begin_stmt_expr (void); -extern tree c_finish_stmt_expr (location_t, tree); -extern tree c_process_expr_stmt (location_t, tree); -extern tree c_finish_expr_stmt (location_t, tree); -extern tree c_finish_return (location_t, tree, tree); -extern tree c_finish_bc_stmt (location_t, tree *, bool); -extern tree c_finish_goto_label (location_t, tree); -extern tree c_finish_goto_ptr (location_t, tree); -extern tree c_expr_to_decl (tree, bool *, bool *); -extern tree c_finish_oacc_parallel (location_t, tree, tree); -extern tree c_finish_oacc_kernels (location_t, tree, tree); -extern tree c_finish_oacc_data (location_t, tree, tree); -extern tree c_begin_omp_parallel (void); -extern tree c_finish_omp_parallel (location_t, tree, tree); -extern tree c_begin_omp_task (void); -extern tree c_finish_omp_task (location_t, tree, tree); -extern void c_finish_omp_cancel (location_t, tree); -extern void c_finish_omp_cancellation_point (location_t, tree); -extern tree c_finish_omp_clauses (tree); -extern tree c_build_va_arg (location_t, tree, tree); -extern tree c_finish_transaction (location_t, tree, int); -extern bool c_tree_equal (tree, tree); -extern tree c_build_function_call_vec (location_t, vec, tree, - vec *, vec *); - -/* Set to 0 at beginning of a function definition, set to 1 if - a return statement that specifies a return value is seen. */ - -extern int current_function_returns_value; - -/* Set to 0 at beginning of a function definition, set to 1 if - a return statement with no argument is seen. */ - -extern int current_function_returns_null; - -/* Set to 0 at beginning of a function definition, set to 1 if - a call to a noreturn function is seen. */ - -extern int current_function_returns_abnormally; - -/* In c-decl.c */ - -/* Tell the binding oracle what kind of binding we are looking for. */ - -enum c_oracle_request -{ - C_ORACLE_SYMBOL, - C_ORACLE_TAG, - C_ORACLE_LABEL -}; - -/* If this is non-NULL, then it is a "binding oracle" which can lazily - create bindings when needed by the C compiler. The oracle is told - the name and type of the binding to create. It can call pushdecl - or the like to ensure the binding is visible; or do nothing, - leaving the binding untouched. c-decl.c takes note of when the - oracle has been called and will not call it again if it fails to - create a given binding. */ - -typedef void c_binding_oracle_function (enum c_oracle_request, tree identifier); - -extern c_binding_oracle_function *c_binding_oracle; - -extern void c_finish_incomplete_decl (tree); -extern void c_write_global_declarations (void); -extern tree c_omp_reduction_id (enum tree_code, tree); -extern tree c_omp_reduction_decl (tree); -extern tree c_omp_reduction_lookup (tree, tree); -extern tree c_check_omp_declare_reduction_r (tree *, int *, void *); -extern void c_pushtag (location_t, tree, tree); -extern void c_bind (location_t, tree, bool); - -/* In c-errors.c */ -extern void pedwarn_c90 (location_t, int opt, const char *, ...) - ATTRIBUTE_GCC_DIAG(3,4); -extern bool pedwarn_c99 (location_t, int opt, const char *, ...) - ATTRIBUTE_GCC_DIAG(3,4); - -#endif /* ! GCC_C_TREE_H */ diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/calls.h b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/calls.h deleted file mode 100644 index fc8458c..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/calls.h +++ /dev/null @@ -1,37 +0,0 @@ -/* Declarations and data types for RTL call insn generation. - Copyright (C) 2013-2015 Free Software Foundation, Inc. - -This file is part of GCC. - -GCC is free software; you can redistribute it and/or modify it under -the terms of the GNU General Public License as published by the Free -Software Foundation; either version 3, or (at your option) any later -version. - -GCC is distributed in the hope that it will be useful, but WITHOUT ANY -WARRANTY; without even the implied warranty of MERCHANTABILITY or -FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -for more details. - -You should have received a copy of the GNU General Public License -along with GCC; see the file COPYING3. If not see -. */ - -#ifndef GCC_CALLS_H -#define GCC_CALLS_H - -extern int flags_from_decl_or_type (const_tree); -extern int call_expr_flags (const_tree); -extern int setjmp_call_p (const_tree); -extern bool gimple_alloca_call_p (const_gimple); -extern bool alloca_call_p (const_tree); -extern bool must_pass_in_stack_var_size (machine_mode, const_tree); -extern bool must_pass_in_stack_var_size_or_pad (machine_mode, const_tree); -extern rtx prepare_call_address (tree, rtx, rtx, rtx *, int, int); -extern bool shift_return_value (machine_mode, bool, rtx); -extern rtx expand_call (tree, rtx, int); -extern void fixup_tail_calls (void); - - - -#endif // GCC_CALLS_H diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/ccmp.h b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/ccmp.h deleted file mode 100644 index 7c138d0..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/ccmp.h +++ /dev/null @@ -1,25 +0,0 @@ -/* Conditional comapre related functions. - Copyright (C) 2014-2015 Free Software Foundation, Inc. - -This file is part of GCC. - -GCC is free software; you can redistribute it and/or modify it under -the terms of the GNU General Public License as published by the Free -Software Foundation; either version 3, or (at your option) any later -version. - -GCC is distributed in the hope that it will be useful, but WITHOUT ANY -WARRANTY; without even the implied warranty of MERCHANTABILITY or -FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -for more details. - -You should have received a copy of the GNU General Public License -along with GCC; see the file COPYING3. If not see -. */ - -#ifndef GCC_CCMP_H -#define GCC_CCMP_H - -extern rtx expand_ccmp_expr (gimple); - -#endif /* GCC_CCMP_H */ diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/cfg-flags.def b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/cfg-flags.def deleted file mode 100644 index eedcd69..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/cfg-flags.def +++ /dev/null @@ -1,186 +0,0 @@ -/* Flags on basic blocks and edges. - Copyright (C) 2012-2015 Free Software Foundation, Inc. - -This file is part of GCC. - -GCC is free software; you can redistribute it and/or modify it under -the terms of the GNU General Public License as published by the Free -Software Foundation; either version 3, or (at your option) any later -version. - -GCC is distributed in the hope that it will be useful, but WITHOUT ANY -WARRANTY; without even the implied warranty of MERCHANTABILITY or -FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -for more details. - -You should have received a copy of the GNU General Public License -along with GCC; see the file COPYING3. If not see -. */ - -/* This file defines flags that may appear on basic blocks or on - edges. Source files define DEF_BASIC_BLOCK_FLAG or DEF_EDGE_FLAG - appropriately before including this file. */ - -#if !defined(DEF_BASIC_BLOCK_FLAG) && !defined(DEF_EDGE_FLAG) -#error "You must define DEF_BASIC_BLOCK_FLAG or DEF_EDGE_FLAG" -#endif - -#ifdef DEF_BASIC_BLOCK_FLAG - -/* Masks for basic_block.flags. - - The format of this file is: DEF_BASIC_BLOCK_FLAG(NAME, IDX). - NAME is the name of the basic block flag. A flag BB_#NAME will be - created and the name is used in dump_edge_info. - IDX is a sequence number that is used to determine the value - of the flag, which is 1 << IDX). - - BB_HOT_PARTITION and BB_COLD_PARTITION should be preserved throughout - the compilation, so they are never cleared. - - All other flags may be cleared by clear_bb_flags(). It is generally - a bad idea to rely on any flags being up-to-date. */ - -/* Only set on blocks that have just been created by create_bb. */ -DEF_BASIC_BLOCK_FLAG(NEW, 0) - -/* Set by find_unreachable_blocks. Do not rely on this being set in any - pass. */ -DEF_BASIC_BLOCK_FLAG(REACHABLE, 1) - -/* Set for blocks in an irreducible loop by loop analysis. */ -DEF_BASIC_BLOCK_FLAG(IRREDUCIBLE_LOOP, 2) - -/* Set on blocks that may actually not be single-entry single-exit block. */ -DEF_BASIC_BLOCK_FLAG(SUPERBLOCK, 3) - -/* Set on basic blocks that the scheduler should not touch. This is used - by SMS to prevent other schedulers from messing with the loop schedule. */ -DEF_BASIC_BLOCK_FLAG(DISABLE_SCHEDULE, 4) - -/* Set on blocks that should be put in a hot section. */ -DEF_BASIC_BLOCK_FLAG(HOT_PARTITION, 5) - -/* Set on blocks that should be put in a cold section. */ -DEF_BASIC_BLOCK_FLAG(COLD_PARTITION, 6) - -/* Set on block that was duplicated. */ -DEF_BASIC_BLOCK_FLAG(DUPLICATED, 7) - -/* Set if the label at the top of this block is the target of a non-local goto. */ -DEF_BASIC_BLOCK_FLAG(NON_LOCAL_GOTO_TARGET, 8) - -/* Set on blocks that are in RTL format. */ -DEF_BASIC_BLOCK_FLAG(RTL, 9) - -/* Set on blocks that are forwarder blocks. - Only used in cfgcleanup.c. */ -DEF_BASIC_BLOCK_FLAG(FORWARDER_BLOCK, 10) - -/* Set on blocks that cannot be threaded through. - Only used in cfgcleanup.c. */ -DEF_BASIC_BLOCK_FLAG(NONTHREADABLE_BLOCK, 11) - -/* Set on blocks that were modified in some way. This bit is set in - df_set_bb_dirty, but not cleared by df_analyze, so it can be used - to test whether a block has been modified prior to a df_analyze call. */ -DEF_BASIC_BLOCK_FLAG(MODIFIED, 12) - -/* A general visited flag for passes to use. */ -DEF_BASIC_BLOCK_FLAG(VISITED, 13) - -/* Set on blocks that are in a transaction. This is calculated on - demand, and is available after calling compute_transaction_bits(). */ -DEF_BASIC_BLOCK_FLAG(IN_TRANSACTION, 14) - -#endif - -#ifdef DEF_EDGE_FLAG - -/* Masks for edge.flags. - - The format of this file is: DEF_EDGE_FLAG(NAME, IDX, STRING). - NAME is the name of the edge flag. A flag EDGE_#NAME will be - created and the name is used in dump_edge_info. - IDX is a sequence number that is used to determine the value - of the flag, which is 1 << IDX). */ - -/* 'Straight line' flow. In GIMPLE and in cfglayout mode, all normal - edges are fallthru edges. In cfgrtl mode, this flag really means - that control flow falls through to the next basic block in the line. */ -DEF_EDGE_FLAG(FALLTHRU, 0) - -/* Strange flow, like a computed jump or exception handling. Usually - this means that the edge cannot be split. */ -DEF_EDGE_FLAG(ABNORMAL, 1) - -/* Edge out of a basic block that ends with a CALL_INSN with abnormal - exit, like an exception or a non-local goto. - ABNORMAL_CALL edges also have ABNORMAL set. - This flag is only used for the RTL CFG. */ -DEF_EDGE_FLAG(ABNORMAL_CALL, 2) - -/* Exception edge. Exception handling edges represent possible control - transfers from a trapping instruction to an exception handler. - EH edges also have ABNORMAL set for the RTL CFG. */ -DEF_EDGE_FLAG(EH, 3) - -/* Never merge blocks via this edge. This is used for exception handling, - to prevent merging away edges to the post-landing-pad basic block. - This flag is only used for the RTL CFG. */ -DEF_EDGE_FLAG(PRESERVE, 4) - -/* Not a real edge. This is used to connect parts of the CFG that do - not halt, such as infinite loops and noreturn functions, to the - EXIT_BLOCK, so that traversing of the reverse CFG is possible. */ -DEF_EDGE_FLAG(FAKE, 5) - -/* A back edge, marked in a depth-first search of the CFG. Back edges - are hints that this edge may be part of a loop in the CFG. */ -DEF_EDGE_FLAG(DFS_BACK, 6) - -/* Edge in a part of the CFG that is an irreducible loop. */ -DEF_EDGE_FLAG(IRREDUCIBLE_LOOP, 7) - -/* Edge taken when controlling predicate is nonzero. - This is only used for the GIMPLE CFG. */ -DEF_EDGE_FLAG(TRUE_VALUE, 8) - -/* Edge taken when controlling predicate is zero. - This is only used for the GIMPLE CFG. */ -DEF_EDGE_FLAG(FALSE_VALUE, 9) - -/* Edge is executable. This is only used in GIMPLE SSA-CCP and VRP. - This is only used for the GIMPLE CFG. */ -DEF_EDGE_FLAG(EXECUTABLE, 10) - -/* Edge crosses between hot and cold sections, when we do partitioning. - This flag is only used for the RTL CFG. */ -DEF_EDGE_FLAG(CROSSING, 11) - -/* Edge from a sibcall CALL_INSN to exit. - SIBCALL edges also have ABNORMAL set. - This flag is only used for the RTL CFG. */ -DEF_EDGE_FLAG(SIBCALL, 12) - -/* Candidate for straight line flow. Only used in bb-reorder.c. - This flag is only used for the RTL CFG. */ -DEF_EDGE_FLAG(CAN_FALLTHRU, 13) - -/* Exit of a loop. This is only used in ifcvt.c. - This flag is only used for the RTL CFG. */ -DEF_EDGE_FLAG(LOOP_EXIT, 14) - -/* Uninstrumented edge out of a GIMPLE_TRANSACTION statement. */ -DEF_EDGE_FLAG(TM_UNINSTRUMENTED, 15) - -/* Abort (over) edge out of a GIMPLE_TRANSACTION statement. */ -DEF_EDGE_FLAG(TM_ABORT, 16) - -#endif - -/* -Local variables: -mode:c -End: -*/ diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/cfg.h b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/cfg.h deleted file mode 100644 index f5ea2ce..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/cfg.h +++ /dev/null @@ -1,117 +0,0 @@ -/* Control flow graph manipulation code header file. - Copyright (C) 2014-2015 Free Software Foundation, Inc. - -This file is part of GCC. - -GCC is free software; you can redistribute it and/or modify it under -the terms of the GNU General Public License as published by the Free -Software Foundation; either version 3, or (at your option) any later -version. - -GCC is distributed in the hope that it will be useful, but WITHOUT ANY -WARRANTY; without even the implied warranty of MERCHANTABILITY or -FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -for more details. - -You should have received a copy of the GNU General Public License -along with GCC; see the file COPYING3. If not see -. */ - -#ifndef GCC_CFG_H -#define GCC_CFG_H - -/* What sort of profiling information we have. */ -enum profile_status_d -{ - PROFILE_ABSENT, - PROFILE_GUESSED, - PROFILE_READ, - PROFILE_LAST /* Last value, used by profile streaming. */ -}; - -/* A structure to group all the per-function control flow graph data. - The x_* prefixing is necessary because otherwise references to the - fields of this struct are interpreted as the defines for backward - source compatibility following the definition of this struct. */ -struct GTY(()) control_flow_graph { - /* Block pointers for the exit and entry of a function. - These are always the head and tail of the basic block list. */ - basic_block x_entry_block_ptr; - basic_block x_exit_block_ptr; - - /* Index by basic block number, get basic block struct info. */ - vec *x_basic_block_info; - - /* Number of basic blocks in this flow graph. */ - int x_n_basic_blocks; - - /* Number of edges in this flow graph. */ - int x_n_edges; - - /* The first free basic block number. */ - int x_last_basic_block; - - /* UIDs for LABEL_DECLs. */ - int last_label_uid; - - /* Mapping of labels to their associated blocks. At present - only used for the gimple CFG. */ - vec *x_label_to_block_map; - - enum profile_status_d x_profile_status; - - /* Whether the dominators and the postdominators are available. */ - enum dom_state x_dom_computed[2]; - - /* Number of basic blocks in the dominance tree. */ - unsigned x_n_bbs_in_dom_tree[2]; - - /* Maximal number of entities in the single jumptable. Used to estimate - final flowgraph size. */ - int max_jumptable_ents; -}; - - -extern void init_flow (struct function *); -extern void clear_edges (void); -extern basic_block alloc_block (void); -extern void link_block (basic_block, basic_block); -extern void unlink_block (basic_block); -extern void compact_blocks (void); -extern void expunge_block (basic_block); -extern edge unchecked_make_edge (basic_block, basic_block, int); -extern edge cached_make_edge (sbitmap, basic_block, basic_block, int); -extern edge make_edge (basic_block, basic_block, int); -extern edge make_single_succ_edge (basic_block, basic_block, int); -extern void remove_edge_raw (edge); -extern void redirect_edge_succ (edge, basic_block); -extern void redirect_edge_pred (edge, basic_block); -extern void clear_bb_flags (void); -extern void dump_edge_info (FILE *, edge, int, int); -extern void debug (edge_def &ref); -extern void debug (edge_def *ptr); -extern void alloc_aux_for_blocks (int); -extern void clear_aux_for_blocks (void); -extern void free_aux_for_blocks (void); -extern void alloc_aux_for_edge (edge, int); -extern void alloc_aux_for_edges (int); -extern void clear_aux_for_edges (void); -extern void free_aux_for_edges (void); -extern void debug_bb (basic_block); -extern basic_block debug_bb_n (int); -extern void dump_bb_info (FILE *, basic_block, int, int, bool, bool); -extern void brief_dump_cfg (FILE *, int); -extern void update_bb_profile_for_threading (basic_block, int, gcov_type, edge); -extern void scale_bbs_frequencies_int (basic_block *, int, int, int); -extern void scale_bbs_frequencies_gcov_type (basic_block *, int, gcov_type, - gcov_type); -extern void initialize_original_copy_tables (void); -extern void free_original_copy_tables (void); -extern void set_bb_original (basic_block, basic_block); -extern basic_block get_bb_original (basic_block); -extern void set_bb_copy (basic_block, basic_block); -extern basic_block get_bb_copy (basic_block); -void set_loop_copy (struct loop *, struct loop *); -struct loop *get_loop_copy (struct loop *); - -#endif /* GCC_CFG_H */ diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/cfganal.h b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/cfganal.h deleted file mode 100644 index 3eb4764..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/cfganal.h +++ /dev/null @@ -1,79 +0,0 @@ -/* Control flow graph analysis header file. - Copyright (C) 2014-2015 Free Software Foundation, Inc. - -This file is part of GCC. - -GCC is free software; you can redistribute it and/or modify it under -the terms of the GNU General Public License as published by the Free -Software Foundation; either version 3, or (at your option) any later -version. - -GCC is distributed in the hope that it will be useful, but WITHOUT ANY -WARRANTY; without even the implied warranty of MERCHANTABILITY or -FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -for more details. - -You should have received a copy of the GNU General Public License -along with GCC; see the file COPYING3. If not see -. */ - - -#ifndef GCC_CFGANAL_H -#define GCC_CFGANAL_H - -/* This structure maintains an edge list vector. */ -/* FIXME: Make this a vec. */ -struct edge_list -{ - int num_edges; - edge *index_to_edge; -}; - - -/* Class to compute and manage control dependences on an edge-list. */ -class control_dependences -{ -public: - control_dependences (edge_list *); - ~control_dependences (); - bitmap get_edges_dependent_on (int); - edge get_edge (int); - -private: - void set_control_dependence_map_bit (basic_block, int); - void clear_control_dependence_bitmap (basic_block); - void find_control_dependence (int); - vec control_dependence_map; - edge_list *m_el; -}; - -extern bool mark_dfs_back_edges (void); -extern void find_unreachable_blocks (void); -struct edge_list * create_edge_list (void); -void free_edge_list (struct edge_list *); -void print_edge_list (FILE *, struct edge_list *); -void verify_edge_list (FILE *, struct edge_list *); -edge find_edge (basic_block, basic_block); -int find_edge_index (struct edge_list *, basic_block, basic_block); -extern void remove_fake_edges (void); -extern void remove_fake_exit_edges (void); -extern void add_noreturn_fake_exit_edges (void); -extern void connect_infinite_loops_to_exit (void); -extern int post_order_compute (int *, bool, bool); -extern basic_block dfs_find_deadend (basic_block); -extern int inverted_post_order_compute (int *); -extern int pre_and_rev_post_order_compute_fn (struct function *, - int *, int *, bool); -extern int pre_and_rev_post_order_compute (int *, int *, bool); -extern int dfs_enumerate_from (basic_block, int, - bool (*)(const_basic_block, const void *), - basic_block *, int, const void *); -extern void compute_dominance_frontiers (struct bitmap_head *); -extern bitmap compute_idf (bitmap, struct bitmap_head *); -extern void bitmap_intersection_of_succs (sbitmap, sbitmap *, basic_block); -extern void bitmap_intersection_of_preds (sbitmap, sbitmap *, basic_block); -extern void bitmap_union_of_succs (sbitmap, sbitmap *, basic_block); -extern void bitmap_union_of_preds (sbitmap, sbitmap *, basic_block); -extern basic_block * single_pred_before_succ_order (void); - -#endif /* GCC_CFGANAL_H */ diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/cfgbuild.h b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/cfgbuild.h deleted file mode 100644 index a2816db..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/cfgbuild.h +++ /dev/null @@ -1,28 +0,0 @@ -/* Control flow graph building header file. - Copyright (C) 2014-2015 Free Software Foundation, Inc. - -This file is part of GCC. - -GCC is free software; you can redistribute it and/or modify it under -the terms of the GNU General Public License as published by the Free -Software Foundation; either version 3, or (at your option) any later -version. - -GCC is distributed in the hope that it will be useful, but WITHOUT ANY -WARRANTY; without even the implied warranty of MERCHANTABILITY or -FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -for more details. - -You should have received a copy of the GNU General Public License -along with GCC; see the file COPYING3. If not see -. */ - -#ifndef GCC_CFGBUILD_H -#define GCC_CFGBUILD_H - -extern bool inside_basic_block_p (const rtx_insn *); -extern bool control_flow_insn_p (const rtx_insn *); -extern void rtl_make_eh_edge (sbitmap, basic_block, rtx); -extern void find_many_sub_basic_blocks (sbitmap); - -#endif /* GCC_CFGBUILD_H */ diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/cfgcleanup.h b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/cfgcleanup.h deleted file mode 100644 index b77bb2f..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/cfgcleanup.h +++ /dev/null @@ -1,34 +0,0 @@ -/* Control flow optimization header file. - Copyright (C) 2014-2015 Free Software Foundation, Inc. - -This file is part of GCC. - -GCC is free software; you can redistribute it and/or modify it under -the terms of the GNU General Public License as published by the Free -Software Foundation; either version 3, or (at your option) any later -version. - -GCC is distributed in the hope that it will be useful, but WITHOUT ANY -WARRANTY; without even the implied warranty of MERCHANTABILITY or -FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -for more details. - -You should have received a copy of the GNU General Public License -along with GCC; see the file COPYING3. If not see -. */ - - -#ifndef GCC_CFGCLEANUP_H -#define GCC_CFGCLEANUP_H - -enum replace_direction { dir_none, dir_forward, dir_backward, dir_both }; - -extern int flow_find_cross_jump (basic_block, basic_block, rtx_insn **, - rtx_insn **, enum replace_direction*); -extern int flow_find_head_matching_sequence (basic_block, basic_block, - rtx_insn **, rtx_insn **, int); -extern bool delete_unreachable_blocks (void); -extern void delete_dead_jumptables (void); -extern bool cleanup_cfg (int); - -#endif /* GCC_CFGCLEANUP_H */ diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/cfgexpand.h b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/cfgexpand.h deleted file mode 100644 index a0b6e3e..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/cfgexpand.h +++ /dev/null @@ -1,26 +0,0 @@ -/* Header file for lowering trees to RTL. - Copyright (C) 2013-2015 Free Software Foundation, Inc. - -This file is part of GCC. - -GCC is free software; you can redistribute it and/or modify it under -the terms of the GNU General Public License as published by the Free -Software Foundation; either version 3, or (at your option) any later -version. - -GCC is distributed in the hope that it will be useful, but WITHOUT ANY -WARRANTY; without even the implied warranty of MERCHANTABILITY or -FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License - for more details. - -You should have received a copy of the GNU General Public License -along with GCC; see the file COPYING3. If not see -. */ - -#ifndef GCC_CFGEXPAND_H -#define GCC_CFGEXPAND_H - -extern tree gimple_assign_rhs_to_tree (gimple); -extern HOST_WIDE_INT estimated_stack_frame_size (struct cgraph_node *); - -#endif /* GCC_CFGEXPAND_H */ diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/cfghooks.h b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/cfghooks.h deleted file mode 100644 index 4a1340e..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/cfghooks.h +++ /dev/null @@ -1,258 +0,0 @@ -/* Hooks for cfg representation specific functions. - Copyright (C) 2003-2015 Free Software Foundation, Inc. - Contributed by Sebastian Pop - -This file is part of GCC. - -GCC is free software; you can redistribute it and/or modify -it under the terms of the GNU General Public License as published by -the Free Software Foundation; either version 3, or (at your option) -any later version. - -GCC is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU General Public License for more details. - -You should have received a copy of the GNU General Public License -along with GCC; see the file COPYING3. If not see -. */ - -#ifndef GCC_CFGHOOKS_H -#define GCC_CFGHOOKS_H - -/* Only basic-block.h includes this. */ - -/* Structure to gather statistic about profile consistency, per pass. - An array of this structure, indexed by pass static number, is allocated - in passes.c. The structure is defined here so that different CFG modes - can do their book-keeping via CFG hooks. - - For every field[2], field[0] is the count before the pass runs, and - field[1] is the post-pass count. This allows us to monitor the effect - of each individual pass on the profile consistency. - - This structure is not supposed to be used by anything other than passes.c - and one CFG hook per CFG mode. */ -struct profile_record -{ - /* The number of basic blocks where sum(freq) of the block's predecessors - doesn't match reasonably well with the incoming frequency. */ - int num_mismatched_freq_in[2]; - /* Likewise for a basic block's successors. */ - int num_mismatched_freq_out[2]; - /* The number of basic blocks where sum(count) of the block's predecessors - doesn't match reasonably well with the incoming frequency. */ - int num_mismatched_count_in[2]; - /* Likewise for a basic block's successors. */ - int num_mismatched_count_out[2]; - /* A weighted cost of the run-time of the function body. */ - gcov_type time[2]; - /* A weighted cost of the size of the function body. */ - int size[2]; - /* True iff this pass actually was run. */ - bool run; -}; - - -struct cfg_hooks -{ - /* Name of the corresponding ir. */ - const char *name; - - /* Debugging. */ - int (*verify_flow_info) (void); - void (*dump_bb) (FILE *, basic_block, int, int); - void (*dump_bb_for_graph) (pretty_printer *, basic_block); - - /* Basic CFG manipulation. */ - - /* Return new basic block. */ - basic_block (*create_basic_block) (void *head, void *end, basic_block after); - - /* Redirect edge E to the given basic block B and update underlying program - representation. Returns edge representing redirected branch (that may not - be equivalent to E in the case of duplicate edges being removed) or NULL - if edge is not easily redirectable for whatever reason. */ - edge (*redirect_edge_and_branch) (edge e, basic_block b); - - /* Same as the above but allows redirecting of fallthru edges. In that case - newly created forwarder basic block is returned. The edge must - not be abnormal. */ - basic_block (*redirect_edge_and_branch_force) (edge, basic_block); - - /* Returns true if it is possible to remove the edge by redirecting it - to the destination of the other edge going from its source. */ - bool (*can_remove_branch_p) (const_edge); - - /* Remove statements corresponding to a given basic block. */ - void (*delete_basic_block) (basic_block); - - /* Creates a new basic block just after basic block B by splitting - everything after specified instruction I. */ - basic_block (*split_block) (basic_block b, void * i); - - /* Move block B immediately after block A. */ - bool (*move_block_after) (basic_block b, basic_block a); - - /* Return true when blocks A and B can be merged into single basic block. */ - bool (*can_merge_blocks_p) (basic_block a, basic_block b); - - /* Merge blocks A and B. */ - void (*merge_blocks) (basic_block a, basic_block b); - - /* Predict edge E using PREDICTOR to given PROBABILITY. */ - void (*predict_edge) (edge e, enum br_predictor predictor, int probability); - - /* Return true if the one of outgoing edges is already predicted by - PREDICTOR. */ - bool (*predicted_by_p) (const_basic_block bb, enum br_predictor predictor); - - /* Return true when block A can be duplicated. */ - bool (*can_duplicate_block_p) (const_basic_block a); - - /* Duplicate block A. */ - basic_block (*duplicate_block) (basic_block a); - - /* Higher level functions representable by primitive operations above if - we didn't have some oddities in RTL and Tree representations. */ - basic_block (*split_edge) (edge); - void (*make_forwarder_block) (edge); - - /* Try to make the edge fallthru. */ - void (*tidy_fallthru_edge) (edge); - - /* Make the edge non-fallthru. */ - basic_block (*force_nonfallthru) (edge); - - /* Say whether a block ends with a call, possibly followed by some - other code that must stay with the call. */ - bool (*block_ends_with_call_p) (basic_block); - - /* Say whether a block ends with a conditional branch. Switches - and unconditional branches do not qualify. */ - bool (*block_ends_with_condjump_p) (const_basic_block); - - /* Add fake edges to the function exit for any non constant and non noreturn - calls, volatile inline assembly in the bitmap of blocks specified by - BLOCKS or to the whole CFG if BLOCKS is zero. Return the number of blocks - that were split. - - The goal is to expose cases in which entering a basic block does not imply - that all subsequent instructions must be executed. */ - int (*flow_call_edges_add) (sbitmap); - - /* This function is called immediately after edge E is added to the - edge vector E->dest->preds. */ - void (*execute_on_growing_pred) (edge); - - /* This function is called immediately before edge E is removed from - the edge vector E->dest->preds. */ - void (*execute_on_shrinking_pred) (edge); - - /* A hook for duplicating loop in CFG, currently this is used - in loop versioning. */ - bool (*cfg_hook_duplicate_loop_to_header_edge) (struct loop *, edge, - unsigned, sbitmap, - edge, vec *, - int); - - /* Add condition to new basic block and update CFG used in loop - versioning. */ - void (*lv_add_condition_to_bb) (basic_block, basic_block, basic_block, - void *); - /* Update the PHI nodes in case of loop versioning. */ - void (*lv_adjust_loop_header_phi) (basic_block, basic_block, - basic_block, edge); - - /* Given a condition BB extract the true/false taken/not taken edges - (depending if we are on tree's or RTL). */ - void (*extract_cond_bb_edges) (basic_block, edge *, edge *); - - - /* Add PHI arguments queued in PENDINT_STMT list on edge E to edge - E->dest (only in tree-ssa loop versioning. */ - void (*flush_pending_stmts) (edge); - - /* True if a block contains no executable instructions. */ - bool (*empty_block_p) (basic_block); - - /* Split a basic block if it ends with a conditional branch and if - the other part of the block is not empty. */ - basic_block (*split_block_before_cond_jump) (basic_block); - - /* Do book-keeping of a basic block for the profile consistency checker. */ - void (*account_profile_record) (basic_block, int, struct profile_record *); -}; - -extern void verify_flow_info (void); -extern void dump_bb (FILE *, basic_block, int, int); -extern void dump_bb_for_graph (pretty_printer *, basic_block); -extern void dump_flow_info (FILE *, int); - -extern edge redirect_edge_and_branch (edge, basic_block); -extern basic_block redirect_edge_and_branch_force (edge, basic_block); -extern edge redirect_edge_succ_nodup (edge, basic_block); -extern bool can_remove_branch_p (const_edge); -extern void remove_branch (edge); -extern void remove_edge (edge); -extern edge split_block (basic_block, void *); -extern edge split_block_after_labels (basic_block); -extern bool move_block_after (basic_block, basic_block); -extern void delete_basic_block (basic_block); -extern basic_block split_edge (edge); -extern basic_block create_basic_block (void *, void *, basic_block); -extern basic_block create_empty_bb (basic_block); -extern bool can_merge_blocks_p (basic_block, basic_block); -extern void merge_blocks (basic_block, basic_block); -extern edge make_forwarder_block (basic_block, bool (*)(edge), - void (*) (basic_block)); -extern basic_block force_nonfallthru (edge); -extern void tidy_fallthru_edge (edge); -extern void tidy_fallthru_edges (void); -extern void predict_edge (edge e, enum br_predictor predictor, int probability); -extern bool predicted_by_p (const_basic_block bb, enum br_predictor predictor); -extern bool can_duplicate_block_p (const_basic_block); -extern basic_block duplicate_block (basic_block, edge, basic_block); -extern bool block_ends_with_call_p (basic_block bb); -extern bool empty_block_p (basic_block); -extern basic_block split_block_before_cond_jump (basic_block); -extern bool block_ends_with_condjump_p (const_basic_block bb); -extern int flow_call_edges_add (sbitmap); -extern void execute_on_growing_pred (edge); -extern void execute_on_shrinking_pred (edge); -extern bool cfg_hook_duplicate_loop_to_header_edge (struct loop *loop, edge, - unsigned int ndupl, - sbitmap wont_exit, - edge orig, - vec *to_remove, - int flags); - -extern void lv_flush_pending_stmts (edge); -extern void extract_cond_bb_edges (basic_block, edge *, edge*); -extern void lv_adjust_loop_header_phi (basic_block, basic_block, basic_block, - edge); -extern void lv_add_condition_to_bb (basic_block, basic_block, basic_block, - void *); - -extern bool can_copy_bbs_p (basic_block *, unsigned); -extern void copy_bbs (basic_block *, unsigned, basic_block *, - edge *, unsigned, edge *, struct loop *, - basic_block, bool); - -void account_profile_record (struct profile_record *, int); - -/* Hooks containers. */ -extern struct cfg_hooks gimple_cfg_hooks; -extern struct cfg_hooks rtl_cfg_hooks; -extern struct cfg_hooks cfg_layout_rtl_cfg_hooks; - -/* Declarations. */ -extern enum ir_type current_ir_type (void); -extern void rtl_register_cfg_hooks (void); -extern void cfg_layout_rtl_register_cfg_hooks (void); -extern void gimple_register_cfg_hooks (void); -extern struct cfg_hooks get_cfg_hooks (void); -extern void set_cfg_hooks (struct cfg_hooks); - -#endif /* GCC_CFGHOOKS_H */ diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/cfgloop.h b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/cfgloop.h deleted file mode 100644 index 1d84572..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/cfgloop.h +++ /dev/null @@ -1,743 +0,0 @@ -/* Natural loop functions - Copyright (C) 1987-2015 Free Software Foundation, Inc. - -This file is part of GCC. - -GCC is free software; you can redistribute it and/or modify it under -the terms of the GNU General Public License as published by the Free -Software Foundation; either version 3, or (at your option) any later -version. - -GCC is distributed in the hope that it will be useful, but WITHOUT ANY -WARRANTY; without even the implied warranty of MERCHANTABILITY or -FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -for more details. - -You should have received a copy of the GNU General Public License -along with GCC; see the file COPYING3. If not see -. */ - -#ifndef GCC_CFGLOOP_H -#define GCC_CFGLOOP_H - -#include "double-int.h" -#include "wide-int.h" -#include "bitmap.h" -#include "sbitmap.h" -#include "hashtab.h" -#include "hash-set.h" -#include "vec.h" -#include "machmode.h" -#include "tm.h" -#include "hard-reg-set.h" -#include "input.h" -#include "function.h" -#include "cfgloopmanip.h" - -/* Structure to hold decision about unrolling/peeling. */ -enum lpt_dec -{ - LPT_NONE, - LPT_UNROLL_CONSTANT, - LPT_UNROLL_RUNTIME, - LPT_UNROLL_STUPID -}; - -struct GTY (()) lpt_decision { - enum lpt_dec decision; - unsigned times; -}; - -/* The type of extend applied to an IV. */ -enum iv_extend_code -{ - IV_SIGN_EXTEND, - IV_ZERO_EXTEND, - IV_UNKNOWN_EXTEND -}; - -/* The structure describing a bound on number of iterations of a loop. */ - -struct GTY ((chain_next ("%h.next"))) nb_iter_bound { - /* The statement STMT is executed at most ... */ - gimple stmt; - - /* ... BOUND + 1 times (BOUND must be an unsigned constant). - The + 1 is added for the following reasons: - - a) 0 would otherwise be unused, while we would need to care more about - overflows (as MAX + 1 is sometimes produced as the estimate on number - of executions of STMT). - b) it is consistent with the result of number_of_iterations_exit. */ - widest_int bound; - - /* True if the statement will cause the loop to be leaved the (at most) - BOUND + 1-st time it is executed, that is, all the statements after it - are executed at most BOUND times. */ - bool is_exit; - - /* The next bound in the list. */ - struct nb_iter_bound *next; -}; - -/* Description of the loop exit. */ - -struct GTY ((for_user)) loop_exit { - /* The exit edge. */ - edge e; - - /* Previous and next exit in the list of the exits of the loop. */ - struct loop_exit *prev; - struct loop_exit *next; - - /* Next element in the list of loops from that E exits. */ - struct loop_exit *next_e; -}; - -struct loop_exit_hasher : ggc_hasher -{ - typedef edge compare_type; - - static hashval_t hash (loop_exit *); - static bool equal (loop_exit *, edge); - static void remove (loop_exit *); -}; - -typedef struct loop *loop_p; - -/* An integer estimation of the number of iterations. Estimate_state - describes what is the state of the estimation. */ -enum loop_estimation -{ - /* Estimate was not computed yet. */ - EST_NOT_COMPUTED, - /* Estimate is ready. */ - EST_AVAILABLE, - EST_LAST -}; - -/* Structure to hold information for each natural loop. */ -struct GTY ((chain_next ("%h.next"))) loop { - /* Index into loops array. */ - int num; - - /* Number of loop insns. */ - unsigned ninsns; - - /* Basic block of loop header. */ - basic_block header; - - /* Basic block of loop latch. */ - basic_block latch; - - /* For loop unrolling/peeling decision. */ - struct lpt_decision lpt_decision; - - /* Average number of executed insns per iteration. */ - unsigned av_ninsns; - - /* Number of blocks contained within the loop. */ - unsigned num_nodes; - - /* Superloops of the loop, starting with the outermost loop. */ - vec *superloops; - - /* The first inner (child) loop or NULL if innermost loop. */ - struct loop *inner; - - /* Link to the next (sibling) loop. */ - struct loop *next; - - /* Auxiliary info specific to a pass. */ - PTR GTY ((skip (""))) aux; - - /* The number of times the latch of the loop is executed. This can be an - INTEGER_CST, or a symbolic expression representing the number of - iterations like "N - 1", or a COND_EXPR containing the runtime - conditions under which the number of iterations is non zero. - - Don't access this field directly: number_of_latch_executions - computes and caches the computed information in this field. */ - tree nb_iterations; - - /* An integer guaranteed to be greater or equal to nb_iterations. Only - valid if any_upper_bound is true. */ - widest_int nb_iterations_upper_bound; - - /* An integer giving an estimate on nb_iterations. Unlike - nb_iterations_upper_bound, there is no guarantee that it is at least - nb_iterations. */ - widest_int nb_iterations_estimate; - - bool any_upper_bound; - bool any_estimate; - - /* True if the loop can be parallel. */ - bool can_be_parallel; - - /* True if -Waggressive-loop-optimizations warned about this loop - already. */ - bool warned_aggressive_loop_optimizations; - - /* An integer estimation of the number of iterations. Estimate_state - describes what is the state of the estimation. */ - enum loop_estimation estimate_state; - - /* If > 0, an integer, where the user asserted that for any - I in [ 0, nb_iterations ) and for any J in - [ I, min ( I + safelen, nb_iterations ) ), the Ith and Jth iterations - of the loop can be safely evaluated concurrently. */ - int safelen; - - /* True if this loop should never be vectorized. */ - bool dont_vectorize; - - /* True if we should try harder to vectorize this loop. */ - bool force_vectorize; - - /* For SIMD loops, this is a unique identifier of the loop, referenced - by IFN_GOMP_SIMD_VF, IFN_GOMP_SIMD_LANE and IFN_GOMP_SIMD_LAST_LANE - builtins. */ - tree simduid; - - /* Upper bound on number of iterations of a loop. */ - struct nb_iter_bound *bounds; - - /* Head of the cyclic list of the exits of the loop. */ - struct loop_exit *exits; - - /* Number of iteration analysis data for RTL. */ - struct niter_desc *simple_loop_desc; - - /* For sanity checking during loop fixup we record here the former - loop header for loops marked for removal. Note that this prevents - the basic-block from being collected but its index can still be - reused. */ - basic_block former_header; -}; - -/* Flags for state of loop structure. */ -enum -{ - LOOPS_HAVE_PREHEADERS = 1, - LOOPS_HAVE_SIMPLE_LATCHES = 2, - LOOPS_HAVE_MARKED_IRREDUCIBLE_REGIONS = 4, - LOOPS_HAVE_RECORDED_EXITS = 8, - LOOPS_MAY_HAVE_MULTIPLE_LATCHES = 16, - LOOP_CLOSED_SSA = 32, - LOOPS_NEED_FIXUP = 64, - LOOPS_HAVE_FALLTHRU_PREHEADERS = 128 -}; - -#define LOOPS_NORMAL (LOOPS_HAVE_PREHEADERS | LOOPS_HAVE_SIMPLE_LATCHES \ - | LOOPS_HAVE_MARKED_IRREDUCIBLE_REGIONS) -#define AVOID_CFG_MODIFICATIONS (LOOPS_MAY_HAVE_MULTIPLE_LATCHES) - -/* Structure to hold CFG information about natural loops within a function. */ -struct GTY (()) loops { - /* State of loops. */ - int state; - - /* Array of the loops. */ - vec *larray; - - /* Maps edges to the list of their descriptions as loop exits. Edges - whose sources or destinations have loop_father == NULL (which may - happen during the cfg manipulations) should not appear in EXITS. */ - hash_table *GTY(()) exits; - - /* Pointer to root of loop hierarchy tree. */ - struct loop *tree_root; -}; - -/* Loop recognition. */ -bool bb_loop_header_p (basic_block); -void init_loops_structure (struct function *, struct loops *, unsigned); -extern struct loops *flow_loops_find (struct loops *); -extern void disambiguate_loops_with_multiple_latches (void); -extern void flow_loops_free (struct loops *); -extern void flow_loops_dump (FILE *, - void (*)(const struct loop *, FILE *, int), int); -extern void flow_loop_dump (const struct loop *, FILE *, - void (*)(const struct loop *, FILE *, int), int); -struct loop *alloc_loop (void); -extern void flow_loop_free (struct loop *); -int flow_loop_nodes_find (basic_block, struct loop *); -unsigned fix_loop_structure (bitmap changed_bbs); -bool mark_irreducible_loops (void); -void release_recorded_exits (void); -void record_loop_exits (void); -void rescan_loop_exit (edge, bool, bool); - -/* Loop data structure manipulation/querying. */ -extern void flow_loop_tree_node_add (struct loop *, struct loop *); -extern void flow_loop_tree_node_remove (struct loop *); -extern bool flow_loop_nested_p (const struct loop *, const struct loop *); -extern bool flow_bb_inside_loop_p (const struct loop *, const_basic_block); -extern struct loop * find_common_loop (struct loop *, struct loop *); -struct loop *superloop_at_depth (struct loop *, unsigned); -struct eni_weights_d; -extern int num_loop_insns (const struct loop *); -extern int average_num_loop_insns (const struct loop *); -extern unsigned get_loop_level (const struct loop *); -extern bool loop_exit_edge_p (const struct loop *, const_edge); -extern bool loop_exits_to_bb_p (struct loop *, basic_block); -extern bool loop_exits_from_bb_p (struct loop *, basic_block); -extern void mark_loop_exit_edges (void); -extern location_t get_loop_location (struct loop *loop); - -/* Loops & cfg manipulation. */ -extern basic_block *get_loop_body (const struct loop *); -extern unsigned get_loop_body_with_size (const struct loop *, basic_block *, - unsigned); -extern basic_block *get_loop_body_in_dom_order (const struct loop *); -extern basic_block *get_loop_body_in_bfs_order (const struct loop *); -extern basic_block *get_loop_body_in_custom_order (const struct loop *, - int (*) (const void *, const void *)); - -extern vec get_loop_exit_edges (const struct loop *); -extern edge single_exit (const struct loop *); -extern edge single_likely_exit (struct loop *loop); -extern unsigned num_loop_branches (const struct loop *); - -extern edge loop_preheader_edge (const struct loop *); -extern edge loop_latch_edge (const struct loop *); - -extern void add_bb_to_loop (basic_block, struct loop *); -extern void remove_bb_from_loops (basic_block); - -extern void cancel_loop_tree (struct loop *); -extern void delete_loop (struct loop *); - - -extern void verify_loop_structure (void); - -/* Loop analysis. */ -extern bool just_once_each_iteration_p (const struct loop *, const_basic_block); -gcov_type expected_loop_iterations_unbounded (const struct loop *); -extern unsigned expected_loop_iterations (const struct loop *); -extern rtx doloop_condition_get (rtx); - -void mark_loop_for_removal (loop_p); - -/* Induction variable analysis. */ - -/* The description of induction variable. The things are a bit complicated - due to need to handle subregs and extends. The value of the object described - by it can be obtained as follows (all computations are done in extend_mode): - - Value in i-th iteration is - delta + mult * extend_{extend_mode} (subreg_{mode} (base + i * step)). - - If first_special is true, the value in the first iteration is - delta + mult * base - - If extend = UNKNOWN, first_special must be false, delta 0, mult 1 and value is - subreg_{mode} (base + i * step) - - The get_iv_value function can be used to obtain these expressions. - - ??? Add a third mode field that would specify the mode in that inner - computation is done, which would enable it to be different from the - outer one? */ - -struct rtx_iv -{ - /* Its base and step (mode of base and step is supposed to be extend_mode, - see the description above). */ - rtx base, step; - - /* The type of extend applied to it (IV_SIGN_EXTEND, IV_ZERO_EXTEND, - or IV_UNKNOWN_EXTEND). */ - enum iv_extend_code extend; - - /* Operations applied in the extended mode. */ - rtx delta, mult; - - /* The mode it is extended to. */ - machine_mode extend_mode; - - /* The mode the variable iterates in. */ - machine_mode mode; - - /* Whether the first iteration needs to be handled specially. */ - unsigned first_special : 1; -}; - -/* The description of an exit from the loop and of the number of iterations - till we take the exit. */ - -struct GTY(()) niter_desc -{ - /* The edge out of the loop. */ - edge out_edge; - - /* The other edge leading from the condition. */ - edge in_edge; - - /* True if we are able to say anything about number of iterations of the - loop. */ - bool simple_p; - - /* True if the loop iterates the constant number of times. */ - bool const_iter; - - /* Number of iterations if constant. */ - uint64_t niter; - - /* Assumptions under that the rest of the information is valid. */ - rtx assumptions; - - /* Assumptions under that the loop ends before reaching the latch, - even if value of niter_expr says otherwise. */ - rtx noloop_assumptions; - - /* Condition under that the loop is infinite. */ - rtx infinite; - - /* Whether the comparison is signed. */ - bool signed_p; - - /* The mode in that niter_expr should be computed. */ - machine_mode mode; - - /* The number of iterations of the loop. */ - rtx niter_expr; -}; - -extern void iv_analysis_loop_init (struct loop *); -extern bool iv_analyze (rtx_insn *, rtx, struct rtx_iv *); -extern bool iv_analyze_result (rtx_insn *, rtx, struct rtx_iv *); -extern bool iv_analyze_expr (rtx_insn *, rtx, machine_mode, - struct rtx_iv *); -extern rtx get_iv_value (struct rtx_iv *, rtx); -extern bool biv_p (rtx_insn *, rtx); -extern void find_simple_exit (struct loop *, struct niter_desc *); -extern void iv_analysis_done (void); - -extern struct niter_desc *get_simple_loop_desc (struct loop *loop); -extern void free_simple_loop_desc (struct loop *loop); - -static inline struct niter_desc * -simple_loop_desc (struct loop *loop) -{ - return loop->simple_loop_desc; -} - -/* Accessors for the loop structures. */ - -/* Returns the loop with index NUM from FNs loop tree. */ - -static inline struct loop * -get_loop (struct function *fn, unsigned num) -{ - return (*loops_for_fn (fn)->larray)[num]; -} - -/* Returns the number of superloops of LOOP. */ - -static inline unsigned -loop_depth (const struct loop *loop) -{ - return vec_safe_length (loop->superloops); -} - -/* Returns the immediate superloop of LOOP, or NULL if LOOP is the outermost - loop. */ - -static inline struct loop * -loop_outer (const struct loop *loop) -{ - unsigned n = vec_safe_length (loop->superloops); - - if (n == 0) - return NULL; - - return (*loop->superloops)[n - 1]; -} - -/* Returns true if LOOP has at least one exit edge. */ - -static inline bool -loop_has_exit_edges (const struct loop *loop) -{ - return loop->exits->next->e != NULL; -} - -/* Returns the list of loops in FN. */ - -inline vec * -get_loops (struct function *fn) -{ - struct loops *loops = loops_for_fn (fn); - if (!loops) - return NULL; - - return loops->larray; -} - -/* Returns the number of loops in FN (including the removed - ones and the fake loop that forms the root of the loop tree). */ - -static inline unsigned -number_of_loops (struct function *fn) -{ - struct loops *loops = loops_for_fn (fn); - if (!loops) - return 0; - - return vec_safe_length (loops->larray); -} - -/* Returns true if state of the loops satisfies all properties - described by FLAGS. */ - -static inline bool -loops_state_satisfies_p (unsigned flags) -{ - return (current_loops->state & flags) == flags; -} - -/* Sets FLAGS to the loops state. */ - -static inline void -loops_state_set (unsigned flags) -{ - current_loops->state |= flags; -} - -/* Clears FLAGS from the loops state. */ - -static inline void -loops_state_clear (unsigned flags) -{ - if (!current_loops) - return; - current_loops->state &= ~flags; -} - -/* Loop iterators. */ - -/* Flags for loop iteration. */ - -enum li_flags -{ - LI_INCLUDE_ROOT = 1, /* Include the fake root of the loop tree. */ - LI_FROM_INNERMOST = 2, /* Iterate over the loops in the reverse order, - starting from innermost ones. */ - LI_ONLY_INNERMOST = 4 /* Iterate only over innermost loops. */ -}; - -/* The iterator for loops. */ - -struct loop_iterator -{ - loop_iterator (loop_p *loop, unsigned flags); - ~loop_iterator (); - - inline loop_p next (); - - /* The list of loops to visit. */ - vec to_visit; - - /* The index of the actual loop. */ - unsigned idx; -}; - -inline loop_p -loop_iterator::next () -{ - int anum; - - while (this->to_visit.iterate (this->idx, &anum)) - { - this->idx++; - loop_p loop = get_loop (cfun, anum); - if (loop) - return loop; - } - - return NULL; -} - -inline -loop_iterator::loop_iterator (loop_p *loop, unsigned flags) -{ - struct loop *aloop; - unsigned i; - int mn; - - this->idx = 0; - if (!current_loops) - { - this->to_visit.create (0); - *loop = NULL; - return; - } - - this->to_visit.create (number_of_loops (cfun)); - mn = (flags & LI_INCLUDE_ROOT) ? 0 : 1; - - if (flags & LI_ONLY_INNERMOST) - { - for (i = 0; vec_safe_iterate (current_loops->larray, i, &aloop); i++) - if (aloop != NULL - && aloop->inner == NULL - && aloop->num >= mn) - this->to_visit.quick_push (aloop->num); - } - else if (flags & LI_FROM_INNERMOST) - { - /* Push the loops to LI->TO_VISIT in postorder. */ - for (aloop = current_loops->tree_root; - aloop->inner != NULL; - aloop = aloop->inner) - continue; - - while (1) - { - if (aloop->num >= mn) - this->to_visit.quick_push (aloop->num); - - if (aloop->next) - { - for (aloop = aloop->next; - aloop->inner != NULL; - aloop = aloop->inner) - continue; - } - else if (!loop_outer (aloop)) - break; - else - aloop = loop_outer (aloop); - } - } - else - { - /* Push the loops to LI->TO_VISIT in preorder. */ - aloop = current_loops->tree_root; - while (1) - { - if (aloop->num >= mn) - this->to_visit.quick_push (aloop->num); - - if (aloop->inner != NULL) - aloop = aloop->inner; - else - { - while (aloop != NULL && aloop->next == NULL) - aloop = loop_outer (aloop); - if (aloop == NULL) - break; - aloop = aloop->next; - } - } - } - - *loop = this->next (); -} - -inline -loop_iterator::~loop_iterator () -{ - this->to_visit.release (); -} - -#define FOR_EACH_LOOP(LOOP, FLAGS) \ - for (loop_iterator li(&(LOOP), FLAGS); \ - (LOOP); \ - (LOOP) = li.next ()) - -/* The properties of the target. */ -struct target_cfgloop { - /* Number of available registers. */ - unsigned x_target_avail_regs; - - /* Number of available registers that are call-clobbered. */ - unsigned x_target_clobbered_regs; - - /* Number of registers reserved for temporary expressions. */ - unsigned x_target_res_regs; - - /* The cost for register when there still is some reserve, but we are - approaching the number of available registers. */ - unsigned x_target_reg_cost[2]; - - /* The cost for register when we need to spill. */ - unsigned x_target_spill_cost[2]; -}; - -extern struct target_cfgloop default_target_cfgloop; -#if SWITCHABLE_TARGET -extern struct target_cfgloop *this_target_cfgloop; -#else -#define this_target_cfgloop (&default_target_cfgloop) -#endif - -#define target_avail_regs \ - (this_target_cfgloop->x_target_avail_regs) -#define target_clobbered_regs \ - (this_target_cfgloop->x_target_clobbered_regs) -#define target_res_regs \ - (this_target_cfgloop->x_target_res_regs) -#define target_reg_cost \ - (this_target_cfgloop->x_target_reg_cost) -#define target_spill_cost \ - (this_target_cfgloop->x_target_spill_cost) - -/* Register pressure estimation for induction variable optimizations & loop - invariant motion. */ -extern unsigned estimate_reg_pressure_cost (unsigned, unsigned, bool, bool); -extern void init_set_costs (void); - -/* Loop optimizer initialization. */ -extern void loop_optimizer_init (unsigned); -extern void loop_optimizer_finalize (void); - -/* Optimization passes. */ -enum -{ - UAP_UNROLL = 1, /* Enables unrolling of loops if it seems profitable. */ - UAP_UNROLL_ALL = 2 /* Enables unrolling of all loops. */ -}; - -extern void doloop_optimize_loops (void); -extern void move_loop_invariants (void); -extern vec get_loop_hot_path (const struct loop *loop); - -/* Returns the outermost loop of the loop nest that contains LOOP.*/ -static inline struct loop * -loop_outermost (struct loop *loop) -{ - unsigned n = vec_safe_length (loop->superloops); - - if (n <= 1) - return loop; - - return (*loop->superloops)[1]; -} - -extern void record_niter_bound (struct loop *, const widest_int &, bool, bool); -extern HOST_WIDE_INT get_estimated_loop_iterations_int (struct loop *); -extern HOST_WIDE_INT get_max_loop_iterations_int (struct loop *); -extern bool get_estimated_loop_iterations (struct loop *loop, widest_int *nit); -extern bool get_max_loop_iterations (struct loop *loop, widest_int *nit); -extern int bb_loop_depth (const_basic_block); - -/* Converts VAL to widest_int. */ - -static inline widest_int -gcov_type_to_wide_int (gcov_type val) -{ - HOST_WIDE_INT a[2]; - - a[0] = (unsigned HOST_WIDE_INT) val; - /* If HOST_BITS_PER_WIDE_INT == HOST_BITS_PER_WIDEST_INT, avoid shifting by - the size of type. */ - val >>= HOST_BITS_PER_WIDE_INT - 1; - val >>= 1; - a[1] = (unsigned HOST_WIDE_INT) val; - - return widest_int::from_array (a, 2); -} -#endif /* GCC_CFGLOOP_H */ diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/cfgloopmanip.h b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/cfgloopmanip.h deleted file mode 100644 index 56a0266..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/cfgloopmanip.h +++ /dev/null @@ -1,63 +0,0 @@ -/* Loop manipulation header. - Copyright (C) 2014-2015 Free Software Foundation, Inc. - -This file is part of GCC. - -GCC is free software; you can redistribute it and/or modify it under -the terms of the GNU General Public License as published by the Free -Software Foundation; either version 3, or (at your option) any later -version. - -GCC is distributed in the hope that it will be useful, but WITHOUT ANY -WARRANTY; without even the implied warranty of MERCHANTABILITY or -FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -for more details. - -You should have received a copy of the GNU General Public License -along with GCC; see the file COPYING3. If not see -. */ - -#ifndef GCC_CFGLOOPMANIP_H -#define GCC_CFGLOOPMANIP_H - -enum -{ - CP_SIMPLE_PREHEADERS = 1, - CP_FALLTHRU_PREHEADERS = 2 -}; - -#define DLTHE_FLAG_UPDATE_FREQ 1 /* Update frequencies in - duplicate_loop_to_header_edge. */ -#define DLTHE_RECORD_COPY_NUMBER 2 /* Record copy number in the aux - field of newly create BB. */ -#define DLTHE_FLAG_COMPLETTE_PEEL 4 /* Update frequencies expecting - a complete peeling. */ -extern edge mfb_kj_edge; - -extern bool remove_path (edge); -extern void place_new_loop (struct function *, struct loop *); -extern void add_loop (struct loop *, struct loop *); -extern void scale_loop_frequencies (struct loop *, int, int); -extern void scale_loop_profile (struct loop *, int, gcov_type); -extern edge create_empty_if_region_on_edge (edge, tree); -extern struct loop *create_empty_loop_on_edge (edge, tree, tree, tree, tree, - tree *, tree *, struct loop *); -extern struct loop *loopify (edge, edge, - basic_block, edge, edge, bool, - unsigned, unsigned); -extern void unloop (struct loop *, bool *, bitmap); -extern void copy_loop_info (struct loop *loop, struct loop *target); -extern struct loop * duplicate_loop (struct loop *, struct loop *); -extern void duplicate_subloops (struct loop *, struct loop *); -extern bool can_duplicate_loop_p (const struct loop *loop); -extern bool duplicate_loop_to_header_edge (struct loop *, edge, - unsigned, sbitmap, edge, - vec *, int); -extern bool mfb_keep_just (edge); -basic_block create_preheader (struct loop *, int); -extern void create_preheaders (int); -extern void force_single_succ_latches (void); -struct loop * loop_version (struct loop *, void *, - basic_block *, unsigned, unsigned, unsigned, bool); - -#endif /* GCC_CFGLOOPMANIP_H */ diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/cfgrtl.h b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/cfgrtl.h deleted file mode 100644 index 32c8ff6..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/cfgrtl.h +++ /dev/null @@ -1,58 +0,0 @@ -/* Define control flow data structures for the CFG. - Copyright (C) 2014-2015 Free Software Foundation, Inc. - -This file is part of GCC. - -GCC is free software; you can redistribute it and/or modify it under -the terms of the GNU General Public License as published by the Free -Software Foundation; either version 3, or (at your option) any later -version. - -GCC is distributed in the hope that it will be useful, but WITHOUT ANY -WARRANTY; without even the implied warranty of MERCHANTABILITY or -FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -for more details. - -You should have received a copy of the GNU General Public License -along with GCC; see the file COPYING3. If not see -. */ - -#ifndef GCC_CFGRTL_H -#define GCC_CFGRTL_H - -extern void delete_insn (rtx); -extern void delete_insn_and_edges (rtx_insn *); -extern void delete_insn_chain (rtx, rtx, bool); -extern basic_block create_basic_block_structure (rtx_insn *, rtx_insn *, - rtx_note *, basic_block); -extern void compute_bb_for_insn (void); -extern unsigned int free_bb_for_insn (void); -extern rtx_insn *entry_of_function (void); -extern void update_bb_for_insn (basic_block); -extern bool contains_no_active_insn_p (const_basic_block); -extern bool forwarder_block_p (const_basic_block); -extern bool can_fallthru (basic_block, basic_block); -extern rtx_note *bb_note (basic_block); -extern rtx block_label (basic_block); -extern edge try_redirect_by_replacing_jump (edge, basic_block, bool); -extern void emit_barrier_after_bb (basic_block bb); -extern basic_block force_nonfallthru_and_redirect (edge, basic_block, rtx); -extern void insert_insn_on_edge (rtx, edge); -extern void commit_one_edge_insertion (edge e); -extern void commit_edge_insertions (void); -extern void print_rtl_with_bb (FILE *, const rtx_insn *, int); -extern void update_br_prob_note (basic_block); -extern rtx_insn *get_last_bb_insn (basic_block); -extern void fixup_partitions (void); -extern bool purge_dead_edges (basic_block); -extern bool purge_all_dead_edges (void); -extern bool fixup_abnormal_edges (void); -extern rtx_insn *unlink_insn_chain (rtx_insn *, rtx_insn *); -extern void relink_block_chain (bool); -extern rtx_insn *duplicate_insn_chain (rtx_insn *, rtx_insn *); -extern void cfg_layout_initialize (unsigned int); -extern void cfg_layout_finalize (void); -extern void break_superblocks (void); -extern void init_rtl_bb_info (basic_block); - -#endif /* GCC_CFGRTL_H */ diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/cgraph.h b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/cgraph.h deleted file mode 100644 index e368996..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/cgraph.h +++ /dev/null @@ -1,3188 +0,0 @@ -/* Callgraph handling code. - Copyright (C) 2003-2015 Free Software Foundation, Inc. - Contributed by Jan Hubicka - -This file is part of GCC. - -GCC is free software; you can redistribute it and/or modify it under -the terms of the GNU General Public License as published by the Free -Software Foundation; either version 3, or (at your option) any later -version. - -GCC is distributed in the hope that it will be useful, but WITHOUT ANY -WARRANTY; without even the implied warranty of MERCHANTABILITY or -FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -for more details. - -You should have received a copy of the GNU General Public License -along with GCC; see the file COPYING3. If not see -. */ - -#ifndef GCC_CGRAPH_H -#define GCC_CGRAPH_H - - -/* Symbol table consists of functions and variables. - TODO: add labels and CONST_DECLs. */ -enum symtab_type -{ - SYMTAB_SYMBOL, - SYMTAB_FUNCTION, - SYMTAB_VARIABLE -}; - -/* Section names are stored as reference counted strings in GGC safe hashtable - (to make them survive through PCH). */ - -struct GTY((for_user)) section_hash_entry_d -{ - int ref_count; - char *name; /* As long as this datastructure stays in GGC, we can not put - string at the tail of structure of GGC dies in horrible - way */ -}; - -typedef struct section_hash_entry_d section_hash_entry; - -struct section_name_hasher : ggc_hasher -{ - typedef const char *compare_type; - - static hashval_t hash (section_hash_entry *); - static bool equal (section_hash_entry *, const char *); -}; - -enum availability -{ - /* Not yet set by cgraph_function_body_availability. */ - AVAIL_UNSET, - /* Function body/variable initializer is unknown. */ - AVAIL_NOT_AVAILABLE, - /* Function body/variable initializer is known but might be replaced - by a different one from other compilation unit and thus needs to - be dealt with a care. Like AVAIL_NOT_AVAILABLE it can have - arbitrary side effects on escaping variables and functions, while - like AVAILABLE it might access static variables. */ - AVAIL_INTERPOSABLE, - /* Function body/variable initializer is known and will be used in final - program. */ - AVAIL_AVAILABLE, - /* Function body/variable initializer is known and all it's uses are - explicitly visible within current unit (ie it's address is never taken and - it is not exported to other units). Currently used only for functions. */ - AVAIL_LOCAL -}; - -/* Classification of symbols WRT partitioning. */ -enum symbol_partitioning_class -{ - /* External declarations are ignored by partitioning algorithms and they are - added into the boundary later via compute_ltrans_boundary. */ - SYMBOL_EXTERNAL, - /* Partitioned symbols are pur into one of partitions. */ - SYMBOL_PARTITION, - /* Duplicated symbols (such as comdat or constant pool references) are - copied into every node needing them via add_symbol_to_partition. */ - SYMBOL_DUPLICATE -}; - -/* Base of all entries in the symbol table. - The symtab_node is inherited by cgraph and varpol nodes. */ -class GTY((desc ("%h.type"), tag ("SYMTAB_SYMBOL"), - chain_next ("%h.next"), chain_prev ("%h.previous"))) - symtab_node -{ -public: - /* Return name. */ - const char *name () const; - - /* Return asm name. */ - const char * asm_name () const; - - /* Add node into symbol table. This function is not used directly, but via - cgraph/varpool node creation routines. */ - void register_symbol (void); - - /* Remove symbol from symbol table. */ - void remove (void); - - /* Dump symtab node to F. */ - void dump (FILE *f); - - /* Dump symtab node to stderr. */ - void DEBUG_FUNCTION debug (void); - - /* Verify consistency of node. */ - void DEBUG_FUNCTION verify (void); - - /* Return ipa reference from this symtab_node to - REFERED_NODE or REFERED_VARPOOL_NODE. USE_TYPE specify type - of the use and STMT the statement (if it exists). */ - ipa_ref *create_reference (symtab_node *referred_node, - enum ipa_ref_use use_type); - - /* Return ipa reference from this symtab_node to - REFERED_NODE or REFERED_VARPOOL_NODE. USE_TYPE specify type - of the use and STMT the statement (if it exists). */ - ipa_ref *create_reference (symtab_node *referred_node, - enum ipa_ref_use use_type, gimple stmt); - - /* If VAL is a reference to a function or a variable, add a reference from - this symtab_node to the corresponding symbol table node. USE_TYPE specify - type of the use and STMT the statement (if it exists). Return the new - reference or NULL if none was created. */ - ipa_ref *maybe_create_reference (tree val, enum ipa_ref_use use_type, - gimple stmt); - - /* Clone all references from symtab NODE to this symtab_node. */ - void clone_references (symtab_node *node); - - /* Remove all stmt references in non-speculative references. - Those are not maintained during inlining & clonning. - The exception are speculative references that are updated along - with callgraph edges associated with them. */ - void clone_referring (symtab_node *node); - - /* Clone reference REF to this symtab_node and set its stmt to STMT. */ - ipa_ref *clone_reference (ipa_ref *ref, gimple stmt); - - /* Find the structure describing a reference to REFERRED_NODE - and associated with statement STMT. */ - ipa_ref *find_reference (symtab_node *referred_node, gimple stmt, - unsigned int lto_stmt_uid); - - /* Remove all references that are associated with statement STMT. */ - void remove_stmt_references (gimple stmt); - - /* Remove all stmt references in non-speculative references. - Those are not maintained during inlining & clonning. - The exception are speculative references that are updated along - with callgraph edges associated with them. */ - void clear_stmts_in_references (void); - - /* Remove all references in ref list. */ - void remove_all_references (void); - - /* Remove all referring items in ref list. */ - void remove_all_referring (void); - - /* Dump references in ref list to FILE. */ - void dump_references (FILE *file); - - /* Dump referring in list to FILE. */ - void dump_referring (FILE *); - - /* Get number of references for this node. */ - inline unsigned num_references (void) - { - return ref_list.references ? ref_list.references->length () : 0; - } - - /* Iterates I-th reference in the list, REF is also set. */ - ipa_ref *iterate_reference (unsigned i, ipa_ref *&ref); - - /* Iterates I-th referring item in the list, REF is also set. */ - ipa_ref *iterate_referring (unsigned i, ipa_ref *&ref); - - /* Iterates I-th referring alias item in the list, REF is also set. */ - ipa_ref *iterate_direct_aliases (unsigned i, ipa_ref *&ref); - - /* Return true if symtab node and TARGET represents - semantically equivalent symbols. */ - bool semantically_equivalent_p (symtab_node *target); - - /* Classify symbol symtab node for partitioning. */ - enum symbol_partitioning_class get_partitioning_class (void); - - /* Return comdat group. */ - tree get_comdat_group () - { - return x_comdat_group; - } - - /* Return comdat group as identifier_node. */ - tree get_comdat_group_id () - { - if (x_comdat_group && TREE_CODE (x_comdat_group) != IDENTIFIER_NODE) - x_comdat_group = DECL_ASSEMBLER_NAME (x_comdat_group); - return x_comdat_group; - } - - /* Set comdat group. */ - void set_comdat_group (tree group) - { - gcc_checking_assert (!group || TREE_CODE (group) == IDENTIFIER_NODE - || DECL_P (group)); - x_comdat_group = group; - } - - /* Return section as string. */ - const char * get_section () - { - if (!x_section) - return NULL; - return x_section->name; - } - - /* Remove node from same comdat group. */ - void remove_from_same_comdat_group (void); - - /* Add this symtab_node to the same comdat group that OLD is in. */ - void add_to_same_comdat_group (symtab_node *old_node); - - /* Dissolve the same_comdat_group list in which NODE resides. */ - void dissolve_same_comdat_group_list (void); - - /* Return true when symtab_node is known to be used from other (non-LTO) - object file. Known only when doing LTO via linker plugin. */ - bool used_from_object_file_p (void); - - /* Walk the alias chain to return the symbol NODE is alias of. - If NODE is not an alias, return NODE. - When AVAILABILITY is non-NULL, get minimal availability in the chain. */ - symtab_node *ultimate_alias_target (enum availability *avail = NULL); - - /* Return next reachable static symbol with initializer after NODE. */ - inline symtab_node *next_defined_symbol (void); - - /* Add reference recording that symtab node is alias of TARGET. - The function can fail in the case of aliasing cycles; in this case - it returns false. */ - bool resolve_alias (symtab_node *target); - - /* C++ FE sometimes change linkage flags after producing same - body aliases. */ - void fixup_same_cpp_alias_visibility (symtab_node *target); - - /* Call callback on symtab node and aliases associated to this node. - When INCLUDE_OVERWRITABLE is false, overwritable aliases and thunks are - skipped. */ - bool call_for_symbol_and_aliases (bool (*callback) (symtab_node *, void *), - void *data, - bool include_overwrite); - - /* If node can not be interposable by static or dynamic linker to point to - different definition, return this symbol. Otherwise look for alias with - such property and if none exists, introduce new one. */ - symtab_node *noninterposable_alias (void); - - /* Return node that alias is aliasing. */ - inline symtab_node *get_alias_target (void); - - /* Set section for symbol and its aliases. */ - void set_section (const char *section); - - /* Set section, do not recurse into aliases. - When one wants to change section of symbol and its aliases, - use set_section. */ - void set_section_for_node (const char *section); - - /* Set initialization priority to PRIORITY. */ - void set_init_priority (priority_type priority); - - /* Return the initialization priority. */ - priority_type get_init_priority (); - - /* Return availability of NODE. */ - enum availability get_availability (void); - - /* Make DECL local. */ - void make_decl_local (void); - - /* Return desired alignment of the definition. This is NOT alignment useful - to access THIS, because THIS may be interposable and DECL_ALIGN should - be used instead. It however must be guaranteed when output definition - of THIS. */ - unsigned int definition_alignment (); - - /* Return true if alignment can be increased. */ - bool can_increase_alignment_p (); - - /* Increase alignment of symbol to ALIGN. */ - void increase_alignment (unsigned int align); - - /* Return true if list contains an alias. */ - bool has_aliases_p (void); - - /* Return true when the symbol is real symbol, i.e. it is not inline clone - or abstract function kept for debug info purposes only. */ - bool real_symbol_p (void); - - /* Determine if symbol declaration is needed. That is, visible to something - either outside this translation unit, something magic in the system - configury. This function is used just during symbol creation. */ - bool needed_p (void); - - /* Return true when there are references to the node. */ - bool referred_to_p (void); - - /* Return true if NODE can be discarded by linker from the binary. */ - inline bool - can_be_discarded_p (void) - { - return (DECL_EXTERNAL (decl) - || (get_comdat_group () - && resolution != LDPR_PREVAILING_DEF - && resolution != LDPR_PREVAILING_DEF_IRONLY - && resolution != LDPR_PREVAILING_DEF_IRONLY_EXP)); - } - - /* Return true if NODE is local to a particular COMDAT group, and must not - be named from outside the COMDAT. This is used for C++ decloned - constructors. */ - inline bool comdat_local_p (void) - { - return (same_comdat_group && !TREE_PUBLIC (decl)); - } - - /* Return true if ONE and TWO are part of the same COMDAT group. */ - inline bool in_same_comdat_group_p (symtab_node *target); - - /* Return true if symbol is known to be nonzero. */ - bool nonzero_address (); - - /* Return 0 if symbol is known to have different address than S2, - Return 1 if symbol is known to have same address as S2, - return 2 otherwise. */ - int equal_address_to (symtab_node *s2); - - /* Return true if symbol's address may possibly be compared to other - symbol's address. */ - bool address_matters_p (); - - /* Return true if NODE's address can be compared. This use properties - of NODE only and does not look if the address is actually taken in - interesting way. For that use ADDRESS_MATTERS_P instead. */ - bool address_can_be_compared_p (void); - - /* Return symbol table node associated with DECL, if any, - and NULL otherwise. */ - static inline symtab_node *get (const_tree decl) - { -#ifdef ENABLE_CHECKING - /* Check that we are called for sane type of object - functions - and static or external variables. */ - gcc_checking_assert (TREE_CODE (decl) == FUNCTION_DECL - || (TREE_CODE (decl) == VAR_DECL - && (TREE_STATIC (decl) || DECL_EXTERNAL (decl) - || in_lto_p))); - /* Check that the mapping is sane - perhaps this check can go away, - but at the moment frontends tends to corrupt the mapping by calling - memcpy/memset on the tree nodes. */ - gcc_checking_assert (!decl->decl_with_vis.symtab_node - || decl->decl_with_vis.symtab_node->decl == decl); -#endif - return decl->decl_with_vis.symtab_node; - } - - /* Try to find a symtab node for declaration DECL and if it does not - exist or if it corresponds to an inline clone, create a new one. */ - static inline symtab_node * get_create (tree node); - - /* Return the cgraph node that has ASMNAME for its DECL_ASSEMBLER_NAME. - Return NULL if there's no such node. */ - static symtab_node *get_for_asmname (const_tree asmname); - - /* Dump symbol table to F. */ - static void dump_table (FILE *); - - /* Dump symbol table to stderr. */ - static inline DEBUG_FUNCTION void debug_symtab (void) - { - dump_table (stderr); - } - - /* Verify symbol table for internal consistency. */ - static DEBUG_FUNCTION void verify_symtab_nodes (void); - - /* Type of the symbol. */ - ENUM_BITFIELD (symtab_type) type : 8; - - /* The symbols resolution. */ - ENUM_BITFIELD (ld_plugin_symbol_resolution) resolution : 8; - - /*** Flags representing the symbol type. ***/ - - /* True when symbol corresponds to a definition in current unit. - set via finalize_function or finalize_decl */ - unsigned definition : 1; - /* True when symbol is an alias. - Set by ssemble_alias. */ - unsigned alias : 1; - /* True when alias is a weakref. */ - unsigned weakref : 1; - /* C++ frontend produce same body aliases and extra name aliases for - virtual functions and vtables that are obviously equivalent. - Those aliases are bit special, especially because C++ frontend - visibility code is so ugly it can not get them right at first time - and their visibility needs to be copied from their "masters" at - the end of parsing. */ - unsigned cpp_implicit_alias : 1; - /* Set once the definition was analyzed. The list of references and - other properties are built during analysis. */ - unsigned analyzed : 1; - /* Set for write-only variables. */ - unsigned writeonly : 1; - /* Visibility of symbol was used for further optimization; do not - permit further changes. */ - unsigned refuse_visibility_changes : 1; - - /*** Visibility and linkage flags. ***/ - - /* Set when function is visible by other units. */ - unsigned externally_visible : 1; - /* Don't reorder to other symbols having this set. */ - unsigned no_reorder : 1; - /* The symbol will be assumed to be used in an invisible way (like - by an toplevel asm statement). */ - unsigned force_output : 1; - /* Like FORCE_OUTPUT, but in the case it is ABI requiring the symbol to be - exported. Unlike FORCE_OUTPUT this flag gets cleared to symbols promoted - to static and it does not inhibit optimization. */ - unsigned forced_by_abi : 1; - /* True when the name is known to be unique and thus it does not need mangling. */ - unsigned unique_name : 1; - /* Specify whether the section was set by user or by - compiler via -ffunction-sections. */ - unsigned implicit_section : 1; - /* True when body and other characteristics have been removed by - symtab_remove_unreachable_nodes. */ - unsigned body_removed : 1; - - /*** WHOPR Partitioning flags. - These flags are used at ltrans stage when only part of the callgraph is - available. ***/ - - /* Set when variable is used from other LTRANS partition. */ - unsigned used_from_other_partition : 1; - /* Set when function is available in the other LTRANS partition. - During WPA output it is used to mark nodes that are present in - multiple partitions. */ - unsigned in_other_partition : 1; - - - - /*** other flags. ***/ - - /* Set when symbol has address taken. */ - unsigned address_taken : 1; - /* Set when init priority is set. */ - unsigned in_init_priority_hash : 1; - - /* Set when symbol needs to be streamed into LTO bytecode for LTO, or in case - of offloading, for separate compilation for a different target. */ - unsigned need_lto_streaming : 1; - - /* Set when symbol can be streamed into bytecode for offloading. */ - unsigned offloadable : 1; - - - /* Ordering of all symtab entries. */ - int order; - - /* Declaration representing the symbol. */ - tree decl; - - /* Linked list of symbol table entries starting with symtab_nodes. */ - symtab_node *next; - symtab_node *previous; - - /* Linked list of symbols with the same asm name. There may be multiple - entries for single symbol name during LTO, because symbols are renamed - only after partitioning. - - Because inline clones are kept in the assembler name has, they also produce - duplicate entries. - - There are also several long standing bugs where frontends and builtin - code produce duplicated decls. */ - symtab_node *next_sharing_asm_name; - symtab_node *previous_sharing_asm_name; - - /* Circular list of nodes in the same comdat group if non-NULL. */ - symtab_node *same_comdat_group; - - /* Vectors of referring and referenced entities. */ - ipa_ref_list ref_list; - - /* Alias target. May be either DECL pointer or ASSEMBLER_NAME pointer - depending to what was known to frontend on the creation time. - Once alias is resolved, this pointer become NULL. */ - tree alias_target; - - /* File stream where this node is being written to. */ - struct lto_file_decl_data * lto_file_data; - - PTR GTY ((skip)) aux; - - /* Comdat group the symbol is in. Can be private if GGC allowed that. */ - tree x_comdat_group; - - /* Section name. Again can be private, if allowed. */ - section_hash_entry *x_section; - -protected: - /* Dump base fields of symtab nodes to F. Not to be used directly. */ - void dump_base (FILE *); - - /* Verify common part of symtab node. */ - bool DEBUG_FUNCTION verify_base (void); - - /* Remove node from symbol table. This function is not used directly, but via - cgraph/varpool node removal routines. */ - void unregister (void); - - /* Return the initialization and finalization priority information for - DECL. If there is no previous priority information, a freshly - allocated structure is returned. */ - struct symbol_priority_map *priority_info (void); - - /* Worker for call_for_symbol_and_aliases_1. */ - bool call_for_symbol_and_aliases_1 (bool (*callback) (symtab_node *, void *), - void *data, - bool include_overwrite); -private: - /* Worker for set_section. */ - static bool set_section (symtab_node *n, void *s); - - /* Worker for symtab_resolve_alias. */ - static bool set_implicit_section (symtab_node *n, void *); - - /* Worker searching noninterposable alias. */ - static bool noninterposable_alias (symtab_node *node, void *data); - - /* Worker for ultimate_alias_target. */ - symtab_node *ultimate_alias_target_1 (enum availability *avail = NULL); -}; - -/* Walk all aliases for NODE. */ -#define FOR_EACH_ALIAS(node, alias) \ - for (unsigned x_i = 0; node->iterate_direct_aliases (x_i, alias); x_i++) - -/* This is the information that is put into the cgraph local structure - to recover a function. */ -struct lto_file_decl_data; - -extern const char * const cgraph_availability_names[]; -extern const char * const ld_plugin_symbol_resolution_names[]; -extern const char * const tls_model_names[]; - -/* Information about thunk, used only for same body aliases. */ - -struct GTY(()) cgraph_thunk_info { - /* Information about the thunk. */ - HOST_WIDE_INT fixed_offset; - HOST_WIDE_INT virtual_value; - tree alias; - bool this_adjusting; - bool virtual_offset_p; - bool add_pointer_bounds_args; - /* Set to true when alias node is thunk. */ - bool thunk_p; -}; - -/* Information about the function collected locally. - Available after function is analyzed. */ - -struct GTY(()) cgraph_local_info { - /* Set when function function is visible in current compilation unit only - and its address is never taken. */ - unsigned local : 1; - - /* False when there is something makes versioning impossible. */ - unsigned versionable : 1; - - /* False when function calling convention and signature can not be changed. - This is the case when __builtin_apply_args is used. */ - unsigned can_change_signature : 1; - - /* True when the function has been originally extern inline, but it is - redefined now. */ - unsigned redefined_extern_inline : 1; - - /* True if the function may enter serial irrevocable mode. */ - unsigned tm_may_enter_irr : 1; -}; - -/* Information about the function that needs to be computed globally - once compilation is finished. Available only with -funit-at-a-time. */ - -struct GTY(()) cgraph_global_info { - /* For inline clones this points to the function they will be - inlined into. */ - cgraph_node *inlined_to; -}; - -/* Information about the function that is propagated by the RTL backend. - Available only for functions that has been already assembled. */ - -struct GTY(()) cgraph_rtl_info { - unsigned int preferred_incoming_stack_boundary; - - /* Call unsaved hard registers really used by the corresponding - function (including ones used by functions called by the - function). */ - HARD_REG_SET function_used_regs; - /* Set if function_used_regs is valid. */ - unsigned function_used_regs_valid: 1; -}; - -/* Represent which DECL tree (or reference to such tree) - will be replaced by another tree while versioning. */ -struct GTY(()) ipa_replace_map -{ - /* The tree that will be replaced. */ - tree old_tree; - /* The new (replacing) tree. */ - tree new_tree; - /* Parameter number to replace, when old_tree is NULL. */ - int parm_num; - /* True when a substitution should be done, false otherwise. */ - bool replace_p; - /* True when we replace a reference to old_tree. */ - bool ref_p; -}; - -struct GTY(()) cgraph_clone_info -{ - vec *tree_map; - bitmap args_to_skip; - bitmap combined_args_to_skip; -}; - -enum cgraph_simd_clone_arg_type -{ - SIMD_CLONE_ARG_TYPE_VECTOR, - SIMD_CLONE_ARG_TYPE_UNIFORM, - SIMD_CLONE_ARG_TYPE_LINEAR_CONSTANT_STEP, - SIMD_CLONE_ARG_TYPE_LINEAR_VARIABLE_STEP, - SIMD_CLONE_ARG_TYPE_MASK -}; - -/* Function arguments in the original function of a SIMD clone. - Supplementary data for `struct simd_clone'. */ - -struct GTY(()) cgraph_simd_clone_arg { - /* Original function argument as it originally existed in - DECL_ARGUMENTS. */ - tree orig_arg; - - /* orig_arg's function (or for extern functions type from - TYPE_ARG_TYPES). */ - tree orig_type; - - /* If argument is a vector, this holds the vector version of - orig_arg that after adjusting the argument types will live in - DECL_ARGUMENTS. Otherwise, this is NULL. - - This basically holds: - vector(simdlen) __typeof__(orig_arg) new_arg. */ - tree vector_arg; - - /* vector_arg's type (or for extern functions new vector type. */ - tree vector_type; - - /* If argument is a vector, this holds the array where the simd - argument is held while executing the simd clone function. This - is a local variable in the cloned function. Its content is - copied from vector_arg upon entry to the clone. - - This basically holds: - __typeof__(orig_arg) simd_array[simdlen]. */ - tree simd_array; - - /* A SIMD clone's argument can be either linear (constant or - variable), uniform, or vector. */ - enum cgraph_simd_clone_arg_type arg_type; - - /* For arg_type SIMD_CLONE_ARG_TYPE_LINEAR_CONSTANT_STEP this is - the constant linear step, if arg_type is - SIMD_CLONE_ARG_TYPE_LINEAR_VARIABLE_STEP, this is index of - the uniform argument holding the step, otherwise 0. */ - HOST_WIDE_INT linear_step; - - /* Variable alignment if available, otherwise 0. */ - unsigned int alignment; -}; - -/* Specific data for a SIMD function clone. */ - -struct GTY(()) cgraph_simd_clone { - /* Number of words in the SIMD lane associated with this clone. */ - unsigned int simdlen; - - /* Number of annotated function arguments in `args'. This is - usually the number of named arguments in FNDECL. */ - unsigned int nargs; - - /* Max hardware vector size in bits for integral vectors. */ - unsigned int vecsize_int; - - /* Max hardware vector size in bits for floating point vectors. */ - unsigned int vecsize_float; - - /* The mangling character for a given vector size. This is is used - to determine the ISA mangling bit as specified in the Intel - Vector ABI. */ - unsigned char vecsize_mangle; - - /* True if this is the masked, in-branch version of the clone, - otherwise false. */ - unsigned int inbranch : 1; - - /* True if this is a Cilk Plus variant. */ - unsigned int cilk_elemental : 1; - - /* Doubly linked list of SIMD clones. */ - cgraph_node *prev_clone, *next_clone; - - /* Original cgraph node the SIMD clones were created for. */ - cgraph_node *origin; - - /* Annotated function arguments for the original function. */ - cgraph_simd_clone_arg GTY((length ("%h.nargs"))) args[1]; -}; - -/* Function Multiversioning info. */ -struct GTY((for_user)) cgraph_function_version_info { - /* The cgraph_node for which the function version info is stored. */ - cgraph_node *this_node; - /* Chains all the semantically identical function versions. The - first function in this chain is the version_info node of the - default function. */ - cgraph_function_version_info *prev; - /* If this version node corresponds to a dispatcher for function - versions, this points to the version info node of the default - function, the first node in the chain. */ - cgraph_function_version_info *next; - /* If this node corresponds to a function version, this points - to the dispatcher function decl, which is the function that must - be called to execute the right function version at run-time. - - If this cgraph node is a dispatcher (if dispatcher_function is - true, in the cgraph_node struct) for function versions, this - points to resolver function, which holds the function body of the - dispatcher. The dispatcher decl is an alias to the resolver - function decl. */ - tree dispatcher_resolver; -}; - -#define DEFCIFCODE(code, type, string) CIF_ ## code, -/* Reasons for inlining failures. */ - -enum cgraph_inline_failed_t { -#include "cif-code.def" - CIF_N_REASONS -}; - -enum cgraph_inline_failed_type_t -{ - CIF_FINAL_NORMAL = 0, - CIF_FINAL_ERROR -}; - -struct cgraph_edge; - -struct cgraph_edge_hasher : ggc_hasher -{ - typedef gimple compare_type; - - static hashval_t hash (cgraph_edge *); - static hashval_t hash (gimple); - static bool equal (cgraph_edge *, gimple); -}; - -/* The cgraph data structure. - Each function decl has assigned cgraph_node listing callees and callers. */ - -struct GTY((tag ("SYMTAB_FUNCTION"))) cgraph_node : public symtab_node { -public: - /* Remove the node from cgraph and all inline clones inlined into it. - Skip however removal of FORBIDDEN_NODE and return true if it needs to be - removed. This allows to call the function from outer loop walking clone - tree. */ - bool remove_symbol_and_inline_clones (cgraph_node *forbidden_node = NULL); - - /* Record all references from cgraph_node that are taken - in statement STMT. */ - void record_stmt_references (gimple stmt); - - /* Like cgraph_set_call_stmt but walk the clone tree and update all - clones sharing the same function body. - When WHOLE_SPECULATIVE_EDGES is true, all three components of - speculative edge gets updated. Otherwise we update only direct - call. */ - void set_call_stmt_including_clones (gimple old_stmt, gcall *new_stmt, - bool update_speculative = true); - - /* Walk the alias chain to return the function cgraph_node is alias of. - Walk through thunk, too. - When AVAILABILITY is non-NULL, get minimal availability in the chain. */ - cgraph_node *function_symbol (enum availability *avail = NULL); - - /* Walk the alias chain to return the function cgraph_node is alias of. - Walk through non virtual thunks, too. Thus we return either a function - or a virtual thunk node. - When AVAILABILITY is non-NULL, get minimal availability in the chain. */ - cgraph_node *function_or_virtual_thunk_symbol - (enum availability *avail = NULL); - - /* Create node representing clone of N executed COUNT times. Decrease - the execution counts from original node too. - The new clone will have decl set to DECL that may or may not be the same - as decl of N. - - When UPDATE_ORIGINAL is true, the counts are subtracted from the original - function's profile to reflect the fact that part of execution is handled - by node. - When CALL_DUPLICATOIN_HOOK is true, the ipa passes are acknowledged about - the new clone. Otherwise the caller is responsible for doing so later. - - If the new node is being inlined into another one, NEW_INLINED_TO should be - the outline function the new one is (even indirectly) inlined to. - All hooks will see this in node's global.inlined_to, when invoked. - Can be NULL if the node is not inlined. */ - cgraph_node *create_clone (tree decl, gcov_type count, int freq, - bool update_original, - vec redirect_callers, - bool call_duplication_hook, - cgraph_node *new_inlined_to, - bitmap args_to_skip); - - /* Create callgraph node clone with new declaration. The actual body will - be copied later at compilation stage. */ - cgraph_node *create_virtual_clone (vec redirect_callers, - vec *tree_map, - bitmap args_to_skip, const char * suffix); - - /* cgraph node being removed from symbol table; see if its entry can be - replaced by other inline clone. */ - cgraph_node *find_replacement (void); - - /* Create a new cgraph node which is the new version of - callgraph node. REDIRECT_CALLERS holds the callers - edges which should be redirected to point to - NEW_VERSION. ALL the callees edges of the node - are cloned to the new version node. Return the new - version node. - - If non-NULL BLOCK_TO_COPY determine what basic blocks - was copied to prevent duplications of calls that are dead - in the clone. */ - - cgraph_node *create_version_clone (tree new_decl, - vec redirect_callers, - bitmap bbs_to_copy); - - /* Perform function versioning. - Function versioning includes copying of the tree and - a callgraph update (creating a new cgraph node and updating - its callees and callers). - - REDIRECT_CALLERS varray includes the edges to be redirected - to the new version. - - TREE_MAP is a mapping of tree nodes we want to replace with - new ones (according to results of prior analysis). - - If non-NULL ARGS_TO_SKIP determine function parameters to remove - from new version. - If SKIP_RETURN is true, the new version will return void. - If non-NULL BLOCK_TO_COPY determine what basic blocks to copy. - If non_NULL NEW_ENTRY determine new entry BB of the clone. - - Return the new version's cgraph node. */ - cgraph_node *create_version_clone_with_body - (vec redirect_callers, - vec *tree_map, bitmap args_to_skip, - bool skip_return, bitmap bbs_to_copy, basic_block new_entry_block, - const char *clone_name); - - /* Insert a new cgraph_function_version_info node into cgraph_fnver_htab - corresponding to cgraph_node. */ - cgraph_function_version_info *insert_new_function_version (void); - - /* Get the cgraph_function_version_info node corresponding to node. */ - cgraph_function_version_info *function_version (void); - - /* Discover all functions and variables that are trivially needed, analyze - them as well as all functions and variables referred by them */ - void analyze (void); - - /* Add thunk alias into callgraph. The alias declaration is ALIAS and it - aliases DECL with an adjustments made into the first parameter. - See comments in thunk_adjust for detail on the parameters. */ - cgraph_node * create_thunk (tree alias, tree, bool this_adjusting, - HOST_WIDE_INT fixed_offset, - HOST_WIDE_INT virtual_value, - tree virtual_offset, - tree real_alias); - - - /* Return node that alias is aliasing. */ - inline cgraph_node *get_alias_target (void); - - /* Given function symbol, walk the alias chain to return the function node - is alias of. Do not walk through thunks. - When AVAILABILITY is non-NULL, get minimal availability in the chain. */ - - cgraph_node *ultimate_alias_target (availability *availability = NULL); - - /* Expand thunk NODE to gimple if possible. - When FORCE_GIMPLE_THUNK is true, gimple thunk is created and - no assembler is produced. - When OUTPUT_ASM_THUNK is true, also produce assembler for - thunks that are not lowered. */ - bool expand_thunk (bool output_asm_thunks, bool force_gimple_thunk); - - /* Call expand_thunk on all callers that are thunks and analyze those - nodes that were expanded. */ - void expand_all_artificial_thunks (); - - /* Assemble thunks and aliases associated to node. */ - void assemble_thunks_and_aliases (void); - - /* Expand function specified by node. */ - void expand (void); - - /* As an GCC extension we allow redefinition of the function. The - semantics when both copies of bodies differ is not well defined. - We replace the old body with new body so in unit at a time mode - we always use new body, while in normal mode we may end up with - old body inlined into some functions and new body expanded and - inlined in others. */ - void reset (void); - - /* Creates a wrapper from cgraph_node to TARGET node. Thunk is used for this - kind of wrapper method. */ - void create_wrapper (cgraph_node *target); - - /* Verify cgraph nodes of the cgraph node. */ - void DEBUG_FUNCTION verify_node (void); - - /* Remove function from symbol table. */ - void remove (void); - - /* Dump call graph node to file F. */ - void dump (FILE *f); - - /* Dump call graph node to stderr. */ - void DEBUG_FUNCTION debug (void); - - /* When doing LTO, read cgraph_node's body from disk if it is not already - present. */ - bool get_untransformed_body (void); - - /* Prepare function body. When doing LTO, read cgraph_node's body from disk - if it is not already present. When some IPA transformations are scheduled, - apply them. */ - bool get_body (void); - - /* Release memory used to represent body of function. - Use this only for functions that are released before being translated to - target code (i.e. RTL). Functions that are compiled to RTL and beyond - are free'd in final.c via free_after_compilation(). */ - void release_body (bool keep_arguments = false); - - /* Return the DECL_STRUCT_FUNCTION of the function. */ - struct function *get_fun (void); - - /* cgraph_node is no longer nested function; update cgraph accordingly. */ - void unnest (void); - - /* Bring cgraph node local. */ - void make_local (void); - - /* Likewise indicate that a node is having address taken. */ - void mark_address_taken (void); - - /* Set fialization priority to PRIORITY. */ - void set_fini_priority (priority_type priority); - - /* Return the finalization priority. */ - priority_type get_fini_priority (void); - - /* Create edge from a given function to CALLEE in the cgraph. */ - cgraph_edge *create_edge (cgraph_node *callee, - gcall *call_stmt, gcov_type count, - int freq); - - /* Create an indirect edge with a yet-undetermined callee where the call - statement destination is a formal parameter of the caller with index - PARAM_INDEX. */ - cgraph_edge *create_indirect_edge (gcall *call_stmt, int ecf_flags, - gcov_type count, int freq, - bool compute_indirect_info = true); - - /* Like cgraph_create_edge walk the clone tree and update all clones sharing - same function body. If clones already have edge for OLD_STMT; only - update the edge same way as cgraph_set_call_stmt_including_clones does. */ - void create_edge_including_clones (cgraph_node *callee, - gimple old_stmt, gcall *stmt, - gcov_type count, - int freq, - cgraph_inline_failed_t reason); - - /* Return the callgraph edge representing the GIMPLE_CALL statement - CALL_STMT. */ - cgraph_edge *get_edge (gimple call_stmt); - - /* Collect all callers of cgraph_node and its aliases that are known to lead - to NODE (i.e. are not overwritable) and that are not thunks. */ - vec collect_callers (void); - - /* Remove all callers from the node. */ - void remove_callers (void); - - /* Remove all callees from the node. */ - void remove_callees (void); - - /* Return function availability. See cgraph.h for description of individual - return values. */ - enum availability get_availability (void); - - /* Set TREE_NOTHROW on cgraph_node's decl and on aliases of the node - if any to NOTHROW. */ - void set_nothrow_flag (bool nothrow); - - /* Set TREE_READONLY on cgraph_node's decl and on aliases of the node - if any to READONLY. */ - void set_const_flag (bool readonly, bool looping); - - /* Set DECL_PURE_P on cgraph_node's decl and on aliases of the node - if any to PURE. */ - void set_pure_flag (bool pure, bool looping); - - /* Call callback on function and aliases associated to the function. - When INCLUDE_OVERWRITABLE is false, overwritable aliases and thunks are - skipped. */ - - bool call_for_symbol_and_aliases (bool (*callback) (cgraph_node *, - void *), - void *data, bool include_overwritable); - - /* Call callback on cgraph_node, thunks and aliases associated to NODE. - When INCLUDE_OVERWRITABLE is false, overwritable aliases and thunks are - skipped. When EXCLUDE_VIRTUAL_THUNKS is true, virtual thunks are - skipped. */ - bool call_for_symbol_thunks_and_aliases (bool (*callback) (cgraph_node *node, - void *data), - void *data, - bool include_overwritable, - bool exclude_virtual_thunks = false); - - /* Likewise indicate that a node is needed, i.e. reachable via some - external means. */ - inline void mark_force_output (void); - - /* Return true when function can be marked local. */ - bool local_p (void); - - /* Return true if cgraph_node can be made local for API change. - Extern inline functions and C++ COMDAT functions can be made local - at the expense of possible code size growth if function is used in multiple - compilation units. */ - bool can_be_local_p (void); - - /* Return true when cgraph_node can not return or throw and thus - it is safe to ignore its side effects for IPA analysis. */ - bool cannot_return_p (void); - - /* Return true when function cgraph_node and all its aliases are only called - directly. - i.e. it is not externally visible, address was not taken and - it is not used in any other non-standard way. */ - bool only_called_directly_p (void); - - /* Return true when function is only called directly or it has alias. - i.e. it is not externally visible, address was not taken and - it is not used in any other non-standard way. */ - inline bool only_called_directly_or_aliased_p (void); - - /* Return true when function cgraph_node can be expected to be removed - from program when direct calls in this compilation unit are removed. - - As a special case COMDAT functions are - cgraph_can_remove_if_no_direct_calls_p while the are not - cgraph_only_called_directly_p (it is possible they are called from other - unit) - - This function behaves as cgraph_only_called_directly_p because eliminating - all uses of COMDAT function does not make it necessarily disappear from - the program unless we are compiling whole program or we do LTO. In this - case we know we win since dynamic linking will not really discard the - linkonce section. - - If WILL_INLINE is true, assume that function will be inlined into all the - direct calls. */ - bool will_be_removed_from_program_if_no_direct_calls_p - (bool will_inline = false); - - /* Return true when function can be removed from callgraph - if all direct calls and references are eliminated. The function does - not take into account comdat groups. */ - bool can_remove_if_no_direct_calls_and_refs_p (void); - - /* Return true when function cgraph_node and its aliases can be removed from - callgraph if all direct calls are eliminated. - If WILL_INLINE is true, assume that function will be inlined into all the - direct calls. */ - bool can_remove_if_no_direct_calls_p (bool will_inline = false); - - /* Return true when callgraph node is a function with Gimple body defined - in current unit. Functions can also be define externally or they - can be thunks with no Gimple representation. - - Note that at WPA stage, the function body may not be present in memory. */ - inline bool has_gimple_body_p (void); - - /* Return true if function should be optimized for size. */ - bool optimize_for_size_p (void); - - /* Dump the callgraph to file F. */ - static void dump_cgraph (FILE *f); - - /* Dump the call graph to stderr. */ - static inline - void debug_cgraph (void) - { - dump_cgraph (stderr); - } - - /* Record that DECL1 and DECL2 are semantically identical function - versions. */ - static void record_function_versions (tree decl1, tree decl2); - - /* Remove the cgraph_function_version_info and cgraph_node for DECL. This - DECL is a duplicate declaration. */ - static void delete_function_version (tree decl); - - /* Add the function FNDECL to the call graph. - Unlike finalize_function, this function is intended to be used - by middle end and allows insertion of new function at arbitrary point - of compilation. The function can be either in high, low or SSA form - GIMPLE. - - The function is assumed to be reachable and have address taken (so no - API breaking optimizations are performed on it). - - Main work done by this function is to enqueue the function for later - processing to avoid need the passes to be re-entrant. */ - static void add_new_function (tree fndecl, bool lowered); - - /* Return callgraph node for given symbol and check it is a function. */ - static inline cgraph_node *get (const_tree decl) - { - gcc_checking_assert (TREE_CODE (decl) == FUNCTION_DECL); - return dyn_cast (symtab_node::get (decl)); - } - - /* DECL has been parsed. Take it, queue it, compile it at the whim of the - logic in effect. If NO_COLLECT is true, then our caller cannot stand to - have the garbage collector run at the moment. We would need to either - create a new GC context, or just not compile right now. */ - static void finalize_function (tree, bool); - - /* Return cgraph node assigned to DECL. Create new one when needed. */ - static cgraph_node * create (tree decl); - - /* Try to find a call graph node for declaration DECL and if it does not - exist or if it corresponds to an inline clone, create a new one. */ - static cgraph_node * get_create (tree); - - /* Return local info for the compiled function. */ - static cgraph_local_info *local_info (tree decl); - - /* Return local info for the compiled function. */ - static cgraph_rtl_info *rtl_info (tree); - - /* Return the cgraph node that has ASMNAME for its DECL_ASSEMBLER_NAME. - Return NULL if there's no such node. */ - static cgraph_node *get_for_asmname (tree asmname); - - /* Attempt to mark ALIAS as an alias to DECL. Return alias node if - successful and NULL otherwise. - Same body aliases are output whenever the body of DECL is output, - and cgraph_node::get (ALIAS) transparently - returns cgraph_node::get (DECL). */ - static cgraph_node * create_same_body_alias (tree alias, tree decl); - - /* Verify whole cgraph structure. */ - static void DEBUG_FUNCTION verify_cgraph_nodes (void); - - /* Worker to bring NODE local. */ - static bool make_local (cgraph_node *node, void *); - - /* Mark ALIAS as an alias to DECL. DECL_NODE is cgraph node representing - the function body is associated - with (not necessarily cgraph_node (DECL). */ - static cgraph_node *create_alias (tree alias, tree target); - - /* Return true if NODE has thunk. */ - static bool has_thunk_p (cgraph_node *node, void *); - - cgraph_edge *callees; - cgraph_edge *callers; - /* List of edges representing indirect calls with a yet undetermined - callee. */ - cgraph_edge *indirect_calls; - /* For nested functions points to function the node is nested in. */ - cgraph_node *origin; - /* Points to first nested function, if any. */ - cgraph_node *nested; - /* Pointer to the next function with same origin, if any. */ - cgraph_node *next_nested; - /* Pointer to the next clone. */ - cgraph_node *next_sibling_clone; - cgraph_node *prev_sibling_clone; - cgraph_node *clones; - cgraph_node *clone_of; - /* If instrumentation_clone is 1 then instrumented_version points - to the original function used to make instrumented version. - Otherwise points to instrumented version of the function. */ - cgraph_node *instrumented_version; - /* If instrumentation_clone is 1 then orig_decl is the original - function declaration. */ - tree orig_decl; - /* For functions with many calls sites it holds map from call expression - to the edge to speed up cgraph_edge function. */ - hash_table *GTY(()) call_site_hash; - /* Declaration node used to be clone of. */ - tree former_clone_of; - - /* If this is a SIMD clone, this points to the SIMD specific - information for it. */ - cgraph_simd_clone *simdclone; - /* If this function has SIMD clones, this points to the first clone. */ - cgraph_node *simd_clones; - - /* Interprocedural passes scheduled to have their transform functions - applied next time we execute local pass on them. We maintain it - per-function in order to allow IPA passes to introduce new functions. */ - vec GTY((skip)) ipa_transforms_to_apply; - - cgraph_local_info local; - cgraph_global_info global; - cgraph_rtl_info rtl; - cgraph_clone_info clone; - cgraph_thunk_info thunk; - - /* Expected number of executions: calculated in profile.c. */ - gcov_type count; - /* How to scale counts at materialization time; used to merge - LTO units with different number of profile runs. */ - int count_materialization_scale; - /* Unique id of the node. */ - int uid; - /* Summary unique id of the node. */ - int summary_uid; - /* ID assigned by the profiling. */ - unsigned int profile_id; - /* Time profiler: first run of function. */ - int tp_first_run; - - /* Set when decl is an abstract function pointed to by the - ABSTRACT_DECL_ORIGIN of a reachable function. */ - unsigned used_as_abstract_origin : 1; - /* Set once the function is lowered (i.e. its CFG is built). */ - unsigned lowered : 1; - /* Set once the function has been instantiated and its callee - lists created. */ - unsigned process : 1; - /* How commonly executed the node is. Initialized during branch - probabilities pass. */ - ENUM_BITFIELD (node_frequency) frequency : 2; - /* True when function can only be called at startup (from static ctor). */ - unsigned only_called_at_startup : 1; - /* True when function can only be called at startup (from static dtor). */ - unsigned only_called_at_exit : 1; - /* True when function is the transactional clone of a function which - is called only from inside transactions. */ - /* ?? We should be able to remove this. We have enough bits in - cgraph to calculate it. */ - unsigned tm_clone : 1; - /* True if this decl is a dispatcher for function versions. */ - unsigned dispatcher_function : 1; - /* True if this decl calls a COMDAT-local function. This is set up in - compute_inline_parameters and inline_call. */ - unsigned calls_comdat_local : 1; - /* True if node has been created by merge operation in IPA-ICF. */ - unsigned icf_merged: 1; - /* True when function is clone created for Pointer Bounds Checker - instrumentation. */ - unsigned instrumentation_clone : 1; - /* True if call to node can't result in a call to free, munmap or - other operation that could make previously non-trapping memory - accesses trapping. */ - unsigned nonfreeing_fn : 1; - /* True if there was multiple COMDAT bodies merged by lto-symtab. */ - unsigned merged : 1; - /* True if function was created to be executed in parallel. */ - unsigned parallelized_function : 1; - /* True if function is part split out by ipa-split. */ - unsigned split_part : 1; - -private: - /* Worker for call_for_symbol_and_aliases. */ - bool call_for_symbol_and_aliases_1 (bool (*callback) (cgraph_node *, - void *), - void *data, bool include_overwritable); -}; - -/* A cgraph node set is a collection of cgraph nodes. A cgraph node - can appear in multiple sets. */ -struct cgraph_node_set_def -{ - hash_map *map; - vec nodes; -}; - -typedef cgraph_node_set_def *cgraph_node_set; -typedef struct varpool_node_set_def *varpool_node_set; - -class varpool_node; - -/* A varpool node set is a collection of varpool nodes. A varpool node - can appear in multiple sets. */ -struct varpool_node_set_def -{ - hash_map * map; - vec nodes; -}; - -/* Iterator structure for cgraph node sets. */ -struct cgraph_node_set_iterator -{ - cgraph_node_set set; - unsigned index; -}; - -/* Iterator structure for varpool node sets. */ -struct varpool_node_set_iterator -{ - varpool_node_set set; - unsigned index; -}; - -/* Context of polymorphic call. It represent information about the type of - instance that may reach the call. This is used by ipa-devirt walkers of the - type inheritance graph. */ - -class GTY(()) ipa_polymorphic_call_context { -public: - /* The called object appears in an object of type OUTER_TYPE - at offset OFFSET. When information is not 100% reliable, we - use SPECULATIVE_OUTER_TYPE and SPECULATIVE_OFFSET. */ - HOST_WIDE_INT offset; - HOST_WIDE_INT speculative_offset; - tree outer_type; - tree speculative_outer_type; - /* True if outer object may be in construction or destruction. */ - unsigned maybe_in_construction : 1; - /* True if outer object may be of derived type. */ - unsigned maybe_derived_type : 1; - /* True if speculative outer object may be of derived type. We always - speculate that construction does not happen. */ - unsigned speculative_maybe_derived_type : 1; - /* True if the context is invalid and all calls should be redirected - to BUILTIN_UNREACHABLE. */ - unsigned invalid : 1; - /* True if the outer type is dynamic. */ - unsigned dynamic : 1; - - /* Build empty "I know nothing" context. */ - ipa_polymorphic_call_context (); - /* Build polymorphic call context for indirect call E. */ - ipa_polymorphic_call_context (cgraph_edge *e); - /* Build polymorphic call context for IP invariant CST. - If specified, OTR_TYPE specify the type of polymorphic call - that takes CST+OFFSET as a prameter. */ - ipa_polymorphic_call_context (tree cst, tree otr_type = NULL, - HOST_WIDE_INT offset = 0); - /* Build context for pointer REF contained in FNDECL at statement STMT. - if INSTANCE is non-NULL, return pointer to the object described by - the context. */ - ipa_polymorphic_call_context (tree fndecl, tree ref, gimple stmt, - tree *instance = NULL); - - /* Look for vtable stores or constructor calls to work out dynamic type - of memory location. */ - bool get_dynamic_type (tree, tree, tree, gimple); - - /* Make context non-speculative. */ - void clear_speculation (); - - /* Produce context specifying all derrived types of OTR_TYPE. If OTR_TYPE is - NULL, the context is set to dummy "I know nothing" setting. */ - void clear_outer_type (tree otr_type = NULL); - - /* Walk container types and modify context to point to actual class - containing OTR_TYPE (if non-NULL) as base class. - Return true if resulting context is valid. - - When CONSIDER_PLACEMENT_NEW is false, reject contexts that may be made - valid only via alocation of new polymorphic type inside by means - of placement new. - - When CONSIDER_BASES is false, only look for actual fields, not base types - of TYPE. */ - bool restrict_to_inner_class (tree otr_type, - bool consider_placement_new = true, - bool consider_bases = true); - - /* Adjust all offsets in contexts by given number of bits. */ - void offset_by (HOST_WIDE_INT); - /* Use when we can not track dynamic type change. This speculatively assume - type change is not happening. */ - void possible_dynamic_type_change (bool, tree otr_type = NULL); - /* Assume that both THIS and a given context is valid and strenghten THIS - if possible. Return true if any strenghtening was made. - If actual type the context is being used in is known, OTR_TYPE should be - set accordingly. This improves quality of combined result. */ - bool combine_with (ipa_polymorphic_call_context, tree otr_type = NULL); - bool meet_with (ipa_polymorphic_call_context, tree otr_type = NULL); - - /* Return TRUE if context is fully useless. */ - bool useless_p () const; - /* Return TRUE if this context conveys the same information as X. */ - bool equal_to (const ipa_polymorphic_call_context &x) const; - - /* Dump human readable context to F. If NEWLINE is true, it will be - terminated by a newline. */ - void dump (FILE *f, bool newline = true) const; - void DEBUG_FUNCTION debug () const; - - /* LTO streaming. */ - void stream_out (struct output_block *) const; - void stream_in (struct lto_input_block *, struct data_in *data_in); - -private: - bool combine_speculation_with (tree, HOST_WIDE_INT, bool, tree); - bool meet_speculation_with (tree, HOST_WIDE_INT, bool, tree); - void set_by_decl (tree, HOST_WIDE_INT); - bool set_by_invariant (tree, tree, HOST_WIDE_INT); - bool speculation_consistent_p (tree, HOST_WIDE_INT, bool, tree) const; - void make_speculative (tree otr_type = NULL); -}; - -/* Structure containing additional information about an indirect call. */ - -struct GTY(()) cgraph_indirect_call_info -{ - /* When agg_content is set, an offset where the call pointer is located - within the aggregate. */ - HOST_WIDE_INT offset; - /* Context of the polymorphic call; use only when POLYMORPHIC flag is set. */ - ipa_polymorphic_call_context context; - /* OBJ_TYPE_REF_TOKEN of a polymorphic call (if polymorphic is set). */ - HOST_WIDE_INT otr_token; - /* Type of the object from OBJ_TYPE_REF_OBJECT. */ - tree otr_type; - /* Index of the parameter that is called. */ - int param_index; - /* ECF flags determined from the caller. */ - int ecf_flags; - /* Profile_id of common target obtrained from profile. */ - int common_target_id; - /* Probability that call will land in function with COMMON_TARGET_ID. */ - int common_target_probability; - - /* Set when the call is a virtual call with the parameter being the - associated object pointer rather than a simple direct call. */ - unsigned polymorphic : 1; - /* Set when the call is a call of a pointer loaded from contents of an - aggregate at offset. */ - unsigned agg_contents : 1; - /* Set when this is a call through a member pointer. */ - unsigned member_ptr : 1; - /* When the previous bit is set, this one determines whether the destination - is loaded from a parameter passed by reference. */ - unsigned by_ref : 1; - /* For polymorphic calls this specify whether the virtual table pointer - may have changed in between function entry and the call. */ - unsigned vptr_changed : 1; -}; - -struct GTY((chain_next ("%h.next_caller"), chain_prev ("%h.prev_caller"), - for_user)) cgraph_edge { - friend class cgraph_node; - - /* Remove the edge in the cgraph. */ - void remove (void); - - /* Change field call_stmt of edge to NEW_STMT. - If UPDATE_SPECULATIVE and E is any component of speculative - edge, then update all components. */ - void set_call_stmt (gcall *new_stmt, bool update_speculative = true); - - /* Redirect callee of the edge to N. The function does not update underlying - call expression. */ - void redirect_callee (cgraph_node *n); - - /* If the edge does not lead to a thunk, simply redirect it to N. Otherwise - create one or more equivalent thunks for N and redirect E to the first in - the chain. Note that it is then necessary to call - n->expand_all_artificial_thunks once all callers are redirected. */ - void redirect_callee_duplicating_thunks (cgraph_node *n); - - /* Make an indirect edge with an unknown callee an ordinary edge leading to - CALLEE. DELTA is an integer constant that is to be added to the this - pointer (first parameter) to compensate for skipping - a thunk adjustment. */ - cgraph_edge *make_direct (cgraph_node *callee); - - /* Turn edge into speculative call calling N2. Update - the profile so the direct call is taken COUNT times - with FREQUENCY. */ - cgraph_edge *make_speculative (cgraph_node *n2, gcov_type direct_count, - int direct_frequency); - - /* Given speculative call edge, return all three components. */ - void speculative_call_info (cgraph_edge *&direct, cgraph_edge *&indirect, - ipa_ref *&reference); - - /* Speculative call edge turned out to be direct call to CALLE_DECL. - Remove the speculative call sequence and return edge representing the call. - It is up to caller to redirect the call as appropriate. */ - cgraph_edge *resolve_speculation (tree callee_decl = NULL); - - /* If necessary, change the function declaration in the call statement - associated with the edge so that it corresponds to the edge callee. */ - gimple redirect_call_stmt_to_callee (void); - - /* Create clone of edge in the node N represented - by CALL_EXPR the callgraph. */ - cgraph_edge * clone (cgraph_node *n, gcall *call_stmt, unsigned stmt_uid, - gcov_type count_scale, int freq_scale, bool update_original); - - /* Verify edge count and frequency. */ - bool verify_count_and_frequency (); - - /* Return true when call of edge can not lead to return from caller - and thus it is safe to ignore its side effects for IPA analysis - when computing side effects of the caller. */ - bool cannot_lead_to_return_p (void); - - /* Return true when the edge represents a direct recursion. */ - bool recursive_p (void); - - /* Return true if the call can be hot. */ - bool maybe_hot_p (void); - - /* Rebuild cgraph edges for current function node. This needs to be run after - passes that don't update the cgraph. */ - static unsigned int rebuild_edges (void); - - /* Rebuild cgraph references for current function node. This needs to be run - after passes that don't update the cgraph. */ - static void rebuild_references (void); - - /* Expected number of executions: calculated in profile.c. */ - gcov_type count; - cgraph_node *caller; - cgraph_node *callee; - cgraph_edge *prev_caller; - cgraph_edge *next_caller; - cgraph_edge *prev_callee; - cgraph_edge *next_callee; - gcall *call_stmt; - /* Additional information about an indirect call. Not cleared when an edge - becomes direct. */ - cgraph_indirect_call_info *indirect_info; - PTR GTY ((skip (""))) aux; - /* When equal to CIF_OK, inline this call. Otherwise, points to the - explanation why function was not inlined. */ - enum cgraph_inline_failed_t inline_failed; - /* The stmt_uid of call_stmt. This is used by LTO to recover the call_stmt - when the function is serialized in. */ - unsigned int lto_stmt_uid; - /* Expected frequency of executions within the function. - When set to CGRAPH_FREQ_BASE, the edge is expected to be called once - per function call. The range is 0 to CGRAPH_FREQ_MAX. */ - int frequency; - /* Unique id of the edge. */ - int uid; - /* Whether this edge was made direct by indirect inlining. */ - unsigned int indirect_inlining_edge : 1; - /* Whether this edge describes an indirect call with an undetermined - callee. */ - unsigned int indirect_unknown_callee : 1; - /* Whether this edge is still a dangling */ - /* True if the corresponding CALL stmt cannot be inlined. */ - unsigned int call_stmt_cannot_inline_p : 1; - /* Can this call throw externally? */ - unsigned int can_throw_external : 1; - /* Edges with SPECULATIVE flag represents indirect calls that was - speculatively turned into direct (i.e. by profile feedback). - The final code sequence will have form: - - if (call_target == expected_fn) - expected_fn (); - else - call_target (); - - Every speculative call is represented by three components attached - to a same call statement: - 1) a direct call (to expected_fn) - 2) an indirect call (to call_target) - 3) a IPA_REF_ADDR refrence to expected_fn. - - Optimizers may later redirect direct call to clone, so 1) and 3) - do not need to necesarily agree with destination. */ - unsigned int speculative : 1; - /* Set to true when caller is a constructor or destructor of polymorphic - type. */ - unsigned in_polymorphic_cdtor : 1; - -private: - /* Remove the edge from the list of the callers of the callee. */ - void remove_caller (void); - - /* Remove the edge from the list of the callees of the caller. */ - void remove_callee (void); - - /* Set callee N of call graph edge and add it to the corresponding set of - callers. */ - void set_callee (cgraph_node *n); - - /* Output flags of edge to a file F. */ - void dump_edge_flags (FILE *f); - - /* Verify that call graph edge corresponds to DECL from the associated - statement. Return true if the verification should fail. */ - bool verify_corresponds_to_fndecl (tree decl); -}; - -#define CGRAPH_FREQ_BASE 1000 -#define CGRAPH_FREQ_MAX 100000 - -/* The varpool data structure. - Each static variable decl has assigned varpool_node. */ - -class GTY((tag ("SYMTAB_VARIABLE"))) varpool_node : public symtab_node { -public: - /* Dump given varpool node to F. */ - void dump (FILE *f); - - /* Dump given varpool node to stderr. */ - void DEBUG_FUNCTION debug (void); - - /* Remove variable from symbol table. */ - void remove (void); - - /* Remove node initializer when it is no longer needed. */ - void remove_initializer (void); - - void analyze (void); - - /* Return variable availability. */ - availability get_availability (void); - - /* When doing LTO, read variable's constructor from disk if - it is not already present. */ - tree get_constructor (void); - - /* Return true if variable has constructor that can be used for folding. */ - bool ctor_useable_for_folding_p (void); - - /* For given variable pool node, walk the alias chain to return the function - the variable is alias of. Do not walk through thunks. - When AVAILABILITY is non-NULL, get minimal availability in the chain. */ - inline varpool_node *ultimate_alias_target - (availability *availability = NULL); - - /* Return node that alias is aliasing. */ - inline varpool_node *get_alias_target (void); - - /* Output one variable, if necessary. Return whether we output it. */ - bool assemble_decl (void); - - /* For variables in named sections make sure get_variable_section - is called before we switch to those sections. Then section - conflicts between read-only and read-only requiring relocations - sections can be resolved. */ - void finalize_named_section_flags (void); - - /* Call calback on varpool symbol and aliases associated to varpool symbol. - When INCLUDE_OVERWRITABLE is false, overwritable aliases and thunks are - skipped. */ - bool call_for_symbol_and_aliases (bool (*callback) (varpool_node *, void *), - void *data, - bool include_overwritable); - - /* Return true when variable should be considered externally visible. */ - bool externally_visible_p (void); - - /* Return true when all references to variable must be visible - in ipa_ref_list. - i.e. if the variable is not externally visible or not used in some magic - way (asm statement or such). - The magic uses are all summarized in force_output flag. */ - inline bool all_refs_explicit_p (); - - /* Return true when variable can be removed from variable pool - if all direct calls are eliminated. */ - inline bool can_remove_if_no_refs_p (void); - - /* Add the variable DECL to the varpool. - Unlike finalize_decl function is intended to be used - by middle end and allows insertion of new variable at arbitrary point - of compilation. */ - static void add (tree decl); - - /* Return varpool node for given symbol and check it is a function. */ - static inline varpool_node *get (const_tree decl); - - /* Mark DECL as finalized. By finalizing the declaration, frontend instruct - the middle end to output the variable to asm file, if needed or externally - visible. */ - static void finalize_decl (tree decl); - - /* Attempt to mark ALIAS as an alias to DECL. Return TRUE if successful. - Extra name aliases are output whenever DECL is output. */ - static varpool_node * create_extra_name_alias (tree alias, tree decl); - - /* Attempt to mark ALIAS as an alias to DECL. Return TRUE if successful. - Extra name aliases are output whenever DECL is output. */ - static varpool_node * create_alias (tree, tree); - - /* Dump the variable pool to F. */ - static void dump_varpool (FILE *f); - - /* Dump the variable pool to stderr. */ - static void DEBUG_FUNCTION debug_varpool (void); - - /* Allocate new callgraph node and insert it into basic data structures. */ - static varpool_node *create_empty (void); - - /* Return varpool node assigned to DECL. Create new one when needed. */ - static varpool_node *get_create (tree decl); - - /* Given an assembler name, lookup node. */ - static varpool_node *get_for_asmname (tree asmname); - - /* Set when variable is scheduled to be assembled. */ - unsigned output : 1; - - /* Set when variable has statically initialized pointer - or is a static bounds variable and needs initalization. */ - unsigned need_bounds_init : 1; - - /* Set if the variable is dynamically initialized, except for - function local statics. */ - unsigned dynamically_initialized : 1; - - ENUM_BITFIELD(tls_model) tls_model : 3; - - /* Set if the variable is known to be used by single function only. - This is computed by ipa_signle_use pass and used by late optimizations - in places where optimization would be valid for local static variable - if we did not do any inter-procedural code movement. */ - unsigned used_by_single_function : 1; - -private: - /* Assemble thunks and aliases associated to varpool node. */ - void assemble_aliases (void); - - /* Worker for call_for_node_and_aliases. */ - bool call_for_symbol_and_aliases_1 (bool (*callback) (varpool_node *, void *), - void *data, - bool include_overwritable); -}; - -/* Every top level asm statement is put into a asm_node. */ - -struct GTY(()) asm_node { - - - /* Next asm node. */ - asm_node *next; - /* String for this asm node. */ - tree asm_str; - /* Ordering of all cgraph nodes. */ - int order; -}; - -/* Report whether or not THIS symtab node is a function, aka cgraph_node. */ - -template <> -template <> -inline bool -is_a_helper ::test (symtab_node *p) -{ - return p && p->type == SYMTAB_FUNCTION; -} - -/* Report whether or not THIS symtab node is a vriable, aka varpool_node. */ - -template <> -template <> -inline bool -is_a_helper ::test (symtab_node *p) -{ - return p && p->type == SYMTAB_VARIABLE; -} - -/* Macros to access the next item in the list of free cgraph nodes and - edges. */ -#define NEXT_FREE_NODE(NODE) dyn_cast ((NODE)->next) -#define SET_NEXT_FREE_NODE(NODE,NODE2) ((NODE))->next = NODE2 -#define NEXT_FREE_EDGE(EDGE) (EDGE)->prev_caller - -typedef void (*cgraph_edge_hook)(cgraph_edge *, void *); -typedef void (*cgraph_node_hook)(cgraph_node *, void *); -typedef void (*varpool_node_hook)(varpool_node *, void *); -typedef void (*cgraph_2edge_hook)(cgraph_edge *, cgraph_edge *, void *); -typedef void (*cgraph_2node_hook)(cgraph_node *, cgraph_node *, void *); - -struct cgraph_edge_hook_list; -struct cgraph_node_hook_list; -struct varpool_node_hook_list; -struct cgraph_2edge_hook_list; -struct cgraph_2node_hook_list; - -/* Map from a symbol to initialization/finalization priorities. */ -struct GTY(()) symbol_priority_map { - priority_type init; - priority_type fini; -}; - -enum symtab_state -{ - /* Frontend is parsing and finalizing functions. */ - PARSING, - /* Callgraph is being constructed. It is safe to add new functions. */ - CONSTRUCTION, - /* Callgraph is being streamed-in at LTO time. */ - LTO_STREAMING, - /* Callgraph is built and early IPA passes are being run. */ - IPA, - /* Callgraph is built and all functions are transformed to SSA form. */ - IPA_SSA, - /* All inline decisions are done; it is now possible to remove extern inline - functions and virtual call targets. */ - IPA_SSA_AFTER_INLINING, - /* Functions are now ordered and being passed to RTL expanders. */ - EXPANSION, - /* All cgraph expansion is done. */ - FINISHED -}; - -struct asmname_hasher -{ - typedef symtab_node *value_type; - typedef const_tree compare_type; - typedef int store_values_directly; - - static hashval_t hash (symtab_node *n); - static bool equal (symtab_node *n, const_tree t); - static void ggc_mx (symtab_node *n); - static void pch_nx (symtab_node *&); - static void pch_nx (symtab_node *&, gt_pointer_operator, void *); - static void remove (symtab_node *) {} -}; - -class GTY((tag ("SYMTAB"))) symbol_table -{ -public: - friend class symtab_node; - friend class cgraph_node; - friend class cgraph_edge; - - symbol_table (): cgraph_max_summary_uid (1) - { - } - - /* Initialize callgraph dump file. */ - void initialize (void); - - /* Register a top-level asm statement ASM_STR. */ - inline asm_node *finalize_toplevel_asm (tree asm_str); - - /* Analyze the whole compilation unit once it is parsed completely. */ - void finalize_compilation_unit (void); - - /* C++ frontend produce same body aliases all over the place, even before PCH - gets streamed out. It relies on us linking the aliases with their function - in order to do the fixups, but ipa-ref is not PCH safe. Consequentely we - first produce aliases without links, but once C++ FE is sure he won't sream - PCH we build the links via this function. */ - void process_same_body_aliases (void); - - /* Perform simple optimizations based on callgraph. */ - void compile (void); - - /* Process CGRAPH_NEW_FUNCTIONS and perform actions necessary to add these - functions into callgraph in a way so they look like ordinary reachable - functions inserted into callgraph already at construction time. */ - void process_new_functions (void); - - /* Once all functions from compilation unit are in memory, produce all clones - and update all calls. We might also do this on demand if we don't want to - bring all functions to memory prior compilation, but current WHOPR - implementation does that and it is is bit easier to keep everything right - in this order. */ - void materialize_all_clones (void); - - /* Register a symbol NODE. */ - inline void register_symbol (symtab_node *node); - - inline void - clear_asm_symbols (void) - { - asmnodes = NULL; - asm_last_node = NULL; - } - - /* Perform reachability analysis and reclaim all unreachable nodes. */ - bool remove_unreachable_nodes (FILE *file); - - /* Optimization of function bodies might've rendered some variables as - unnecessary so we want to avoid these from being compiled. Re-do - reachability starting from variables that are either externally visible - or was referred from the asm output routines. */ - void remove_unreferenced_decls (void); - - /* Unregister a symbol NODE. */ - inline void unregister (symtab_node *node); - - /* Allocate new callgraph node and insert it into basic data structures. */ - cgraph_node *create_empty (void); - - /* Release a callgraph NODE with UID and put in to the list - of free nodes. */ - void release_symbol (cgraph_node *node, int uid); - - /* Output all variables enqueued to be assembled. */ - bool output_variables (void); - - /* Weakrefs may be associated to external decls and thus not output - at expansion time. Emit all necessary aliases. */ - void output_weakrefs (void); - - /* Return first static symbol with definition. */ - inline symtab_node *first_symbol (void); - - /* Return first assembler symbol. */ - inline asm_node * - first_asm_symbol (void) - { - return asmnodes; - } - - /* Return first static symbol with definition. */ - inline symtab_node *first_defined_symbol (void); - - /* Return first variable. */ - inline varpool_node *first_variable (void); - - /* Return next variable after NODE. */ - inline varpool_node *next_variable (varpool_node *node); - - /* Return first static variable with initializer. */ - inline varpool_node *first_static_initializer (void); - - /* Return next static variable with initializer after NODE. */ - inline varpool_node *next_static_initializer (varpool_node *node); - - /* Return first static variable with definition. */ - inline varpool_node *first_defined_variable (void); - - /* Return next static variable with definition after NODE. */ - inline varpool_node *next_defined_variable (varpool_node *node); - - /* Return first function with body defined. */ - inline cgraph_node *first_defined_function (void); - - /* Return next function with body defined after NODE. */ - inline cgraph_node *next_defined_function (cgraph_node *node); - - /* Return first function. */ - inline cgraph_node *first_function (void); - - /* Return next function. */ - inline cgraph_node *next_function (cgraph_node *node); - - /* Return first function with body defined. */ - cgraph_node *first_function_with_gimple_body (void); - - /* Return next reachable static variable with initializer after NODE. */ - inline cgraph_node *next_function_with_gimple_body (cgraph_node *node); - - /* Register HOOK to be called with DATA on each removed edge. */ - cgraph_edge_hook_list *add_edge_removal_hook (cgraph_edge_hook hook, - void *data); - - /* Remove ENTRY from the list of hooks called on removing edges. */ - void remove_edge_removal_hook (cgraph_edge_hook_list *entry); - - /* Register HOOK to be called with DATA on each removed node. */ - cgraph_node_hook_list *add_cgraph_removal_hook (cgraph_node_hook hook, - void *data); - - /* Remove ENTRY from the list of hooks called on removing nodes. */ - void remove_cgraph_removal_hook (cgraph_node_hook_list *entry); - - /* Register HOOK to be called with DATA on each removed node. */ - varpool_node_hook_list *add_varpool_removal_hook (varpool_node_hook hook, - void *data); - - /* Remove ENTRY from the list of hooks called on removing nodes. */ - void remove_varpool_removal_hook (varpool_node_hook_list *entry); - - /* Register HOOK to be called with DATA on each inserted node. */ - cgraph_node_hook_list *add_cgraph_insertion_hook (cgraph_node_hook hook, - void *data); - - /* Remove ENTRY from the list of hooks called on inserted nodes. */ - void remove_cgraph_insertion_hook (cgraph_node_hook_list *entry); - - /* Register HOOK to be called with DATA on each inserted node. */ - varpool_node_hook_list *add_varpool_insertion_hook (varpool_node_hook hook, - void *data); - - /* Remove ENTRY from the list of hooks called on inserted nodes. */ - void remove_varpool_insertion_hook (varpool_node_hook_list *entry); - - /* Register HOOK to be called with DATA on each duplicated edge. */ - cgraph_2edge_hook_list *add_edge_duplication_hook (cgraph_2edge_hook hook, - void *data); - /* Remove ENTRY from the list of hooks called on duplicating edges. */ - void remove_edge_duplication_hook (cgraph_2edge_hook_list *entry); - - /* Register HOOK to be called with DATA on each duplicated node. */ - cgraph_2node_hook_list *add_cgraph_duplication_hook (cgraph_2node_hook hook, - void *data); - - /* Remove ENTRY from the list of hooks called on duplicating nodes. */ - void remove_cgraph_duplication_hook (cgraph_2node_hook_list *entry); - - /* Call all edge removal hooks. */ - void call_edge_removal_hooks (cgraph_edge *e); - - /* Call all node insertion hooks. */ - void call_cgraph_insertion_hooks (cgraph_node *node); - - /* Call all node removal hooks. */ - void call_cgraph_removal_hooks (cgraph_node *node); - - /* Call all node duplication hooks. */ - void call_cgraph_duplication_hooks (cgraph_node *node, cgraph_node *node2); - - /* Call all edge duplication hooks. */ - void call_edge_duplication_hooks (cgraph_edge *cs1, cgraph_edge *cs2); - - /* Call all node removal hooks. */ - void call_varpool_removal_hooks (varpool_node *node); - - /* Call all node insertion hooks. */ - void call_varpool_insertion_hooks (varpool_node *node); - - /* Arrange node to be first in its entry of assembler_name_hash. */ - void symtab_prevail_in_asm_name_hash (symtab_node *node); - - /* Initalize asm name hash unless. */ - void symtab_initialize_asm_name_hash (void); - - /* Set the DECL_ASSEMBLER_NAME and update symtab hashtables. */ - void change_decl_assembler_name (tree decl, tree name); - - int cgraph_count; - int cgraph_max_uid; - int cgraph_max_summary_uid; - - int edges_count; - int edges_max_uid; - - symtab_node* GTY(()) nodes; - asm_node* GTY(()) asmnodes; - asm_node* GTY(()) asm_last_node; - cgraph_node* GTY(()) free_nodes; - - /* Head of a linked list of unused (freed) call graph edges. - Do not GTY((delete)) this list so UIDs gets reliably recycled. */ - cgraph_edge * GTY(()) free_edges; - - /* The order index of the next symtab node to be created. This is - used so that we can sort the cgraph nodes in order by when we saw - them, to support -fno-toplevel-reorder. */ - int order; - - /* Set when whole unit has been analyzed so we can access global info. */ - bool global_info_ready; - /* What state callgraph is in right now. */ - enum symtab_state state; - /* Set when the cgraph is fully build and the basic flags are computed. */ - bool function_flags_ready; - - bool cpp_implicit_aliases_done; - - /* Hash table used to hold sectoons. */ - hash_table *GTY(()) section_hash; - - /* Hash table used to convert assembler names into nodes. */ - hash_table *assembler_name_hash; - - /* Hash table used to hold init priorities. */ - hash_map *init_priority_hash; - - FILE* GTY ((skip)) dump_file; - -private: - /* Allocate new callgraph node. */ - inline cgraph_node * allocate_cgraph_symbol (void); - - /* Allocate a cgraph_edge structure and fill it with data according to the - parameters of which only CALLEE can be NULL (when creating an indirect call - edge). */ - cgraph_edge *create_edge (cgraph_node *caller, cgraph_node *callee, - gcall *call_stmt, gcov_type count, int freq, - bool indir_unknown_callee); - - /* Put the edge onto the free list. */ - void free_edge (cgraph_edge *e); - - /* Insert NODE to assembler name hash. */ - void insert_to_assembler_name_hash (symtab_node *node, bool with_clones); - - /* Remove NODE from assembler name hash. */ - void unlink_from_assembler_name_hash (symtab_node *node, bool with_clones); - - /* Hash asmnames ignoring the user specified marks. */ - static hashval_t decl_assembler_name_hash (const_tree asmname); - - /* Compare ASMNAME with the DECL_ASSEMBLER_NAME of DECL. */ - static bool decl_assembler_name_equal (tree decl, const_tree asmname); - - friend struct asmname_hasher; - - /* List of hooks triggered when an edge is removed. */ - cgraph_edge_hook_list * GTY((skip)) m_first_edge_removal_hook; - /* List of hooks triggem_red when a cgraph node is removed. */ - cgraph_node_hook_list * GTY((skip)) m_first_cgraph_removal_hook; - /* List of hooks triggered when an edge is duplicated. */ - cgraph_2edge_hook_list * GTY((skip)) m_first_edge_duplicated_hook; - /* List of hooks triggered when a node is duplicated. */ - cgraph_2node_hook_list * GTY((skip)) m_first_cgraph_duplicated_hook; - /* List of hooks triggered when an function is inserted. */ - cgraph_node_hook_list * GTY((skip)) m_first_cgraph_insertion_hook; - /* List of hooks triggered when an variable is inserted. */ - varpool_node_hook_list * GTY((skip)) m_first_varpool_insertion_hook; - /* List of hooks triggered when a node is removed. */ - varpool_node_hook_list * GTY((skip)) m_first_varpool_removal_hook; -}; - -extern GTY(()) symbol_table *symtab; - -extern vec cgraph_new_nodes; - -inline hashval_t -asmname_hasher::hash (symtab_node *n) -{ - return symbol_table::decl_assembler_name_hash - (DECL_ASSEMBLER_NAME (n->decl)); -} - -inline bool -asmname_hasher::equal (symtab_node *n, const_tree t) -{ - return symbol_table::decl_assembler_name_equal (n->decl, t); -} - -extern void gt_ggc_mx (symtab_node *&); - -inline void -asmname_hasher::ggc_mx (symtab_node *n) -{ - gt_ggc_mx (n); -} - -extern void gt_pch_nx (symtab_node *&); - -inline void -asmname_hasher::pch_nx (symtab_node *&n) -{ - gt_pch_nx (n); -} - -inline void -asmname_hasher::pch_nx (symtab_node *&n, gt_pointer_operator op, void *cookie) -{ - op (&n, cookie); -} - -/* In cgraph.c */ -void cgraph_c_finalize (void); -void release_function_body (tree); -cgraph_indirect_call_info *cgraph_allocate_init_indirect_info (void); - -void cgraph_update_edges_for_call_stmt (gimple, tree, gimple); -bool cgraph_function_possibly_inlined_p (tree); - -const char* cgraph_inline_failed_string (cgraph_inline_failed_t); -cgraph_inline_failed_type_t cgraph_inline_failed_type (cgraph_inline_failed_t); - -extern bool gimple_check_call_matching_types (gimple, tree, bool); - -/* In cgraphunit.c */ -void cgraphunit_c_finalize (void); - -/* Initialize datastructures so DECL is a function in lowered gimple form. - IN_SSA is true if the gimple is in SSA. */ -basic_block init_lowered_empty_function (tree, bool, gcov_type); - -/* In cgraphclones.c */ - -tree clone_function_name_1 (const char *, const char *); -tree clone_function_name (tree decl, const char *); - -void tree_function_versioning (tree, tree, vec *, - bool, bitmap, bool, bitmap, basic_block); - -/* In cgraphbuild.c */ -int compute_call_stmt_bb_frequency (tree, basic_block bb); -void record_references_in_initializer (tree, bool); - -/* In ipa.c */ -void cgraph_build_static_cdtor (char which, tree body, int priority); -bool ipa_discover_readonly_nonaddressable_vars (void); - -/* In varpool.c */ -tree ctor_for_folding (tree); - -/* In tree-chkp.c */ -extern bool chkp_function_instrumented_p (tree fndecl); - -/* Return true when the symbol is real symbol, i.e. it is not inline clone - or abstract function kept for debug info purposes only. */ -inline bool -symtab_node::real_symbol_p (void) -{ - cgraph_node *cnode; - - if (DECL_ABSTRACT_P (decl)) - return false; - if (!is_a (this)) - return true; - cnode = dyn_cast (this); - if (cnode->global.inlined_to) - return false; - return true; -} - -/* Return true if DECL should have entry in symbol table if used. - Those are functions and static & external veriables*/ - -static inline bool -decl_in_symtab_p (const_tree decl) -{ - return (TREE_CODE (decl) == FUNCTION_DECL - || (TREE_CODE (decl) == VAR_DECL - && (TREE_STATIC (decl) || DECL_EXTERNAL (decl)))); -} - -inline bool -symtab_node::in_same_comdat_group_p (symtab_node *target) -{ - symtab_node *source = this; - - if (cgraph_node *cn = dyn_cast (target)) - { - if (cn->global.inlined_to) - source = cn->global.inlined_to; - } - if (cgraph_node *cn = dyn_cast (target)) - { - if (cn->global.inlined_to) - target = cn->global.inlined_to; - } - - return source->get_comdat_group () == target->get_comdat_group (); -} - -/* Return node that alias is aliasing. */ - -inline symtab_node * -symtab_node::get_alias_target (void) -{ - ipa_ref *ref = NULL; - iterate_reference (0, ref); - if (ref->use == IPA_REF_CHKP) - iterate_reference (1, ref); - gcc_checking_assert (ref->use == IPA_REF_ALIAS); - return ref->referred; -} - -/* Return next reachable static symbol with initializer after the node. */ - -inline symtab_node * -symtab_node::next_defined_symbol (void) -{ - symtab_node *node1 = next; - - for (; node1; node1 = node1->next) - if (node1->definition) - return node1; - - return NULL; -} - -/* Iterates I-th reference in the list, REF is also set. */ - -inline ipa_ref * -symtab_node::iterate_reference (unsigned i, ipa_ref *&ref) -{ - vec_safe_iterate (ref_list.references, i, &ref); - - return ref; -} - -/* Iterates I-th referring item in the list, REF is also set. */ - -inline ipa_ref * -symtab_node::iterate_referring (unsigned i, ipa_ref *&ref) -{ - ref_list.referring.iterate (i, &ref); - - return ref; -} - -/* Iterates I-th referring alias item in the list, REF is also set. */ - -inline ipa_ref * -symtab_node::iterate_direct_aliases (unsigned i, ipa_ref *&ref) -{ - ref_list.referring.iterate (i, &ref); - - if (ref && ref->use != IPA_REF_ALIAS) - return NULL; - - return ref; -} - -/* Return true if list contains an alias. */ - -inline bool -symtab_node::has_aliases_p (void) -{ - ipa_ref *ref = NULL; - - return (iterate_direct_aliases (0, ref) != NULL); -} - -/* Return true when RESOLUTION indicate that linker will use - the symbol from non-LTO object files. */ - -inline bool -resolution_used_from_other_file_p (enum ld_plugin_symbol_resolution resolution) -{ - return (resolution == LDPR_PREVAILING_DEF - || resolution == LDPR_PREEMPTED_REG - || resolution == LDPR_RESOLVED_EXEC - || resolution == LDPR_RESOLVED_DYN); -} - -/* Return true when symtab_node is known to be used from other (non-LTO) - object file. Known only when doing LTO via linker plugin. */ - -inline bool -symtab_node::used_from_object_file_p (void) -{ - if (!TREE_PUBLIC (decl) || DECL_EXTERNAL (decl)) - return false; - if (resolution_used_from_other_file_p (resolution)) - return true; - return false; -} - -/* Return varpool node for given symbol and check it is a function. */ - -inline varpool_node * -varpool_node::get (const_tree decl) -{ - gcc_checking_assert (TREE_CODE (decl) == VAR_DECL); - return dyn_cast (symtab_node::get (decl)); -} - -/* Register a symbol NODE. */ - -inline void -symbol_table::register_symbol (symtab_node *node) -{ - node->next = nodes; - node->previous = NULL; - - if (nodes) - nodes->previous = node; - nodes = node; - - node->order = order++; -} - -/* Register a top-level asm statement ASM_STR. */ - -asm_node * -symbol_table::finalize_toplevel_asm (tree asm_str) -{ - asm_node *node; - - node = ggc_cleared_alloc (); - node->asm_str = asm_str; - node->order = order++; - node->next = NULL; - - if (asmnodes == NULL) - asmnodes = node; - else - asm_last_node->next = node; - - asm_last_node = node; - return node; -} - -/* Unregister a symbol NODE. */ -inline void -symbol_table::unregister (symtab_node *node) -{ - if (node->previous) - node->previous->next = node->next; - else - nodes = node->next; - - if (node->next) - node->next->previous = node->previous; - - node->next = NULL; - node->previous = NULL; -} - -/* Release a callgraph NODE with UID and put in to the list of free nodes. */ - -inline void -symbol_table::release_symbol (cgraph_node *node, int uid) -{ - cgraph_count--; - - /* Clear out the node to NULL all pointers and add the node to the free - list. */ - memset (node, 0, sizeof (*node)); - node->type = SYMTAB_FUNCTION; - node->uid = uid; - SET_NEXT_FREE_NODE (node, free_nodes); - free_nodes = node; -} - -/* Allocate new callgraph node. */ - -inline cgraph_node * -symbol_table::allocate_cgraph_symbol (void) -{ - cgraph_node *node; - - if (free_nodes) - { - node = free_nodes; - free_nodes = NEXT_FREE_NODE (node); - } - else - { - node = ggc_cleared_alloc (); - node->uid = cgraph_max_uid++; - } - - node->summary_uid = cgraph_max_summary_uid++; - return node; -} - - -/* Return first static symbol with definition. */ -inline symtab_node * -symbol_table::first_symbol (void) -{ - return nodes; -} - -/* Walk all symbols. */ -#define FOR_EACH_SYMBOL(node) \ - for ((node) = symtab->first_symbol (); (node); (node) = (node)->next) - -/* Return first static symbol with definition. */ -inline symtab_node * -symbol_table::first_defined_symbol (void) -{ - symtab_node *node; - - for (node = nodes; node; node = node->next) - if (node->definition) - return node; - - return NULL; -} - -/* Walk all symbols with definitions in current unit. */ -#define FOR_EACH_DEFINED_SYMBOL(node) \ - for ((node) = symtab->first_defined_symbol (); (node); \ - (node) = node->next_defined_symbol ()) - -/* Return first variable. */ -inline varpool_node * -symbol_table::first_variable (void) -{ - symtab_node *node; - for (node = nodes; node; node = node->next) - if (varpool_node *vnode = dyn_cast (node)) - return vnode; - return NULL; -} - -/* Return next variable after NODE. */ -inline varpool_node * -symbol_table::next_variable (varpool_node *node) -{ - symtab_node *node1 = node->next; - for (; node1; node1 = node1->next) - if (varpool_node *vnode1 = dyn_cast (node1)) - return vnode1; - return NULL; -} -/* Walk all variables. */ -#define FOR_EACH_VARIABLE(node) \ - for ((node) = symtab->first_variable (); \ - (node); \ - (node) = symtab->next_variable ((node))) - -/* Return first static variable with initializer. */ -inline varpool_node * -symbol_table::first_static_initializer (void) -{ - symtab_node *node; - for (node = nodes; node; node = node->next) - { - varpool_node *vnode = dyn_cast (node); - if (vnode && DECL_INITIAL (node->decl)) - return vnode; - } - return NULL; -} - -/* Return next static variable with initializer after NODE. */ -inline varpool_node * -symbol_table::next_static_initializer (varpool_node *node) -{ - symtab_node *node1 = node->next; - for (; node1; node1 = node1->next) - { - varpool_node *vnode1 = dyn_cast (node1); - if (vnode1 && DECL_INITIAL (node1->decl)) - return vnode1; - } - return NULL; -} - -/* Walk all static variables with initializer set. */ -#define FOR_EACH_STATIC_INITIALIZER(node) \ - for ((node) = symtab->first_static_initializer (); (node); \ - (node) = symtab->next_static_initializer (node)) - -/* Return first static variable with definition. */ -inline varpool_node * -symbol_table::first_defined_variable (void) -{ - symtab_node *node; - for (node = nodes; node; node = node->next) - { - varpool_node *vnode = dyn_cast (node); - if (vnode && vnode->definition) - return vnode; - } - return NULL; -} - -/* Return next static variable with definition after NODE. */ -inline varpool_node * -symbol_table::next_defined_variable (varpool_node *node) -{ - symtab_node *node1 = node->next; - for (; node1; node1 = node1->next) - { - varpool_node *vnode1 = dyn_cast (node1); - if (vnode1 && vnode1->definition) - return vnode1; - } - return NULL; -} -/* Walk all variables with definitions in current unit. */ -#define FOR_EACH_DEFINED_VARIABLE(node) \ - for ((node) = symtab->first_defined_variable (); (node); \ - (node) = symtab->next_defined_variable (node)) - -/* Return first function with body defined. */ -inline cgraph_node * -symbol_table::first_defined_function (void) -{ - symtab_node *node; - for (node = nodes; node; node = node->next) - { - cgraph_node *cn = dyn_cast (node); - if (cn && cn->definition) - return cn; - } - return NULL; -} - -/* Return next function with body defined after NODE. */ -inline cgraph_node * -symbol_table::next_defined_function (cgraph_node *node) -{ - symtab_node *node1 = node->next; - for (; node1; node1 = node1->next) - { - cgraph_node *cn1 = dyn_cast (node1); - if (cn1 && cn1->definition) - return cn1; - } - return NULL; -} - -/* Walk all functions with body defined. */ -#define FOR_EACH_DEFINED_FUNCTION(node) \ - for ((node) = symtab->first_defined_function (); (node); \ - (node) = symtab->next_defined_function ((node))) - -/* Return first function. */ -inline cgraph_node * -symbol_table::first_function (void) -{ - symtab_node *node; - for (node = nodes; node; node = node->next) - if (cgraph_node *cn = dyn_cast (node)) - return cn; - return NULL; -} - -/* Return next function. */ -inline cgraph_node * -symbol_table::next_function (cgraph_node *node) -{ - symtab_node *node1 = node->next; - for (; node1; node1 = node1->next) - if (cgraph_node *cn1 = dyn_cast (node1)) - return cn1; - return NULL; -} - -/* Return first function with body defined. */ -inline cgraph_node * -symbol_table::first_function_with_gimple_body (void) -{ - symtab_node *node; - for (node = nodes; node; node = node->next) - { - cgraph_node *cn = dyn_cast (node); - if (cn && cn->has_gimple_body_p ()) - return cn; - } - return NULL; -} - -/* Return next reachable static variable with initializer after NODE. */ -inline cgraph_node * -symbol_table::next_function_with_gimple_body (cgraph_node *node) -{ - symtab_node *node1 = node->next; - for (; node1; node1 = node1->next) - { - cgraph_node *cn1 = dyn_cast (node1); - if (cn1 && cn1->has_gimple_body_p ()) - return cn1; - } - return NULL; -} - -/* Walk all functions. */ -#define FOR_EACH_FUNCTION(node) \ - for ((node) = symtab->first_function (); (node); \ - (node) = symtab->next_function ((node))) - -/* Return true when callgraph node is a function with Gimple body defined - in current unit. Functions can also be define externally or they - can be thunks with no Gimple representation. - - Note that at WPA stage, the function body may not be present in memory. */ - -inline bool -cgraph_node::has_gimple_body_p (void) -{ - return definition && !thunk.thunk_p && !alias; -} - -/* Walk all functions with body defined. */ -#define FOR_EACH_FUNCTION_WITH_GIMPLE_BODY(node) \ - for ((node) = symtab->first_function_with_gimple_body (); (node); \ - (node) = symtab->next_function_with_gimple_body (node)) - -/* Uniquize all constants that appear in memory. - Each constant in memory thus far output is recorded - in `const_desc_table'. */ - -struct GTY((for_user)) constant_descriptor_tree { - /* A MEM for the constant. */ - rtx rtl; - - /* The value of the constant. */ - tree value; - - /* Hash of value. Computing the hash from value each time - hashfn is called can't work properly, as that means recursive - use of the hash table during hash table expansion. */ - hashval_t hash; -}; - -/* Return true when function is only called directly or it has alias. - i.e. it is not externally visible, address was not taken and - it is not used in any other non-standard way. */ - -inline bool -cgraph_node::only_called_directly_or_aliased_p (void) -{ - gcc_assert (!global.inlined_to); - return (!force_output && !address_taken - && !used_from_other_partition - && !DECL_VIRTUAL_P (decl) - && !DECL_STATIC_CONSTRUCTOR (decl) - && !DECL_STATIC_DESTRUCTOR (decl) - && !used_from_object_file_p () - && !externally_visible); -} - -/* Return true when function can be removed from callgraph - if all direct calls are eliminated. */ - -inline bool -cgraph_node::can_remove_if_no_direct_calls_and_refs_p (void) -{ - gcc_checking_assert (!global.inlined_to); - /* Instrumentation clones should not be removed before - instrumentation happens. New callers may appear after - instrumentation. */ - if (instrumentation_clone - && !chkp_function_instrumented_p (decl)) - return false; - /* Extern inlines can always go, we will use the external definition. */ - if (DECL_EXTERNAL (decl)) - return true; - /* When function is needed, we can not remove it. */ - if (force_output || used_from_other_partition) - return false; - if (DECL_STATIC_CONSTRUCTOR (decl) - || DECL_STATIC_DESTRUCTOR (decl)) - return false; - /* Only COMDAT functions can be removed if externally visible. */ - if (externally_visible - && (!DECL_COMDAT (decl) - || forced_by_abi - || used_from_object_file_p ())) - return false; - return true; -} - -/* Return true when variable can be removed from variable pool - if all direct calls are eliminated. */ - -inline bool -varpool_node::can_remove_if_no_refs_p (void) -{ - if (DECL_EXTERNAL (decl)) - return true; - return (!force_output && !used_from_other_partition - && ((DECL_COMDAT (decl) - && !forced_by_abi - && !used_from_object_file_p ()) - || !externally_visible - || DECL_HAS_VALUE_EXPR_P (decl))); -} - -/* Return true when all references to variable must be visible in ipa_ref_list. - i.e. if the variable is not externally visible or not used in some magic - way (asm statement or such). - The magic uses are all summarized in force_output flag. */ - -inline bool -varpool_node::all_refs_explicit_p () -{ - return (definition - && !externally_visible - && !used_from_other_partition - && !force_output); -} - -struct tree_descriptor_hasher : ggc_hasher -{ - static hashval_t hash (constant_descriptor_tree *); - static bool equal (constant_descriptor_tree *, constant_descriptor_tree *); -}; - -/* Constant pool accessor function. */ -hash_table *constant_pool_htab (void); - -/* Return node that alias is aliasing. */ - -inline cgraph_node * -cgraph_node::get_alias_target (void) -{ - return dyn_cast (symtab_node::get_alias_target ()); -} - -/* Return node that alias is aliasing. */ - -inline varpool_node * -varpool_node::get_alias_target (void) -{ - return dyn_cast (symtab_node::get_alias_target ()); -} - -/* Walk the alias chain to return the symbol NODE is alias of. - If NODE is not an alias, return NODE. - When AVAILABILITY is non-NULL, get minimal availability in the chain. */ - -inline symtab_node * -symtab_node::ultimate_alias_target (enum availability *availability) -{ - if (!alias) - { - if (availability) - *availability = get_availability (); - return this; - } - - return ultimate_alias_target_1 (availability); -} - -/* Given function symbol, walk the alias chain to return the function node - is alias of. Do not walk through thunks. - When AVAILABILITY is non-NULL, get minimal availability in the chain. */ - -inline cgraph_node * -cgraph_node::ultimate_alias_target (enum availability *availability) -{ - cgraph_node *n = dyn_cast - (symtab_node::ultimate_alias_target (availability)); - if (!n && availability) - *availability = AVAIL_NOT_AVAILABLE; - return n; -} - -/* For given variable pool node, walk the alias chain to return the function - the variable is alias of. Do not walk through thunks. - When AVAILABILITY is non-NULL, get minimal availability in the chain. */ - -inline varpool_node * -varpool_node::ultimate_alias_target (availability *availability) -{ - varpool_node *n = dyn_cast - (symtab_node::ultimate_alias_target (availability)); - - if (!n && availability) - *availability = AVAIL_NOT_AVAILABLE; - return n; -} - -/* Set callee N of call graph edge and add it to the corresponding set of - callers. */ - -inline void -cgraph_edge::set_callee (cgraph_node *n) -{ - prev_caller = NULL; - if (n->callers) - n->callers->prev_caller = this; - next_caller = n->callers; - n->callers = this; - callee = n; -} - -/* Redirect callee of the edge to N. The function does not update underlying - call expression. */ - -inline void -cgraph_edge::redirect_callee (cgraph_node *n) -{ - /* Remove from callers list of the current callee. */ - remove_callee (); - - /* Insert to callers list of the new callee. */ - set_callee (n); -} - -/* Return true when the edge represents a direct recursion. */ - -inline bool -cgraph_edge::recursive_p (void) -{ - cgraph_node *c = callee->ultimate_alias_target (); - if (caller->global.inlined_to) - return caller->global.inlined_to->decl == c->decl; - else - return caller->decl == c->decl; -} - -/* Remove the edge from the list of the callers of the callee. */ - -inline void -cgraph_edge::remove_callee (void) -{ - gcc_assert (!indirect_unknown_callee); - if (prev_caller) - prev_caller->next_caller = next_caller; - if (next_caller) - next_caller->prev_caller = prev_caller; - if (!prev_caller) - callee->callers = next_caller; -} - -/* Return true if the TM_CLONE bit is set for a given FNDECL. */ -static inline bool -decl_is_tm_clone (const_tree fndecl) -{ - cgraph_node *n = cgraph_node::get (fndecl); - if (n) - return n->tm_clone; - return false; -} - -/* Likewise indicate that a node is needed, i.e. reachable via some - external means. */ - -inline void -cgraph_node::mark_force_output (void) -{ - force_output = 1; - gcc_checking_assert (!global.inlined_to); -} - -/* Return true if function should be optimized for size. */ - -inline bool -cgraph_node::optimize_for_size_p (void) -{ - if (opt_for_fn (decl, optimize_size)) - return true; - if (frequency == NODE_FREQUENCY_UNLIKELY_EXECUTED) - return true; - else - return false; -} - -/* Return symtab_node for NODE or create one if it is not present - in symtab. */ - -inline symtab_node * -symtab_node::get_create (tree node) -{ - if (TREE_CODE (node) == VAR_DECL) - return varpool_node::get_create (node); - else - return cgraph_node::get_create (node); -} - -/* Return availability of NODE. */ - -inline enum availability -symtab_node::get_availability (void) -{ - if (is_a (this)) - return dyn_cast (this)->get_availability (); - else - return dyn_cast (this)->get_availability ();; -} - -/* Call calback on symtab node and aliases associated to this node. - When INCLUDE_OVERWRITABLE is false, overwritable aliases and thunks are - skipped. */ - -inline bool -symtab_node::call_for_symbol_and_aliases (bool (*callback) (symtab_node *, - void *), - void *data, - bool include_overwritable) -{ - if (callback (this, data)) - return true; - if (has_aliases_p ()) - return call_for_symbol_and_aliases_1 (callback, data, include_overwritable); - return false; -} - -/* Call callback on function and aliases associated to the function. - When INCLUDE_OVERWRITABLE is false, overwritable aliases and thunks are - skipped. */ - -inline bool -cgraph_node::call_for_symbol_and_aliases (bool (*callback) (cgraph_node *, - void *), - void *data, - bool include_overwritable) -{ - if (callback (this, data)) - return true; - if (has_aliases_p ()) - return call_for_symbol_and_aliases_1 (callback, data, include_overwritable); - return false; -} - -/* Call calback on varpool symbol and aliases associated to varpool symbol. - When INCLUDE_OVERWRITABLE is false, overwritable aliases and thunks are - skipped. */ - -inline bool -varpool_node::call_for_symbol_and_aliases (bool (*callback) (varpool_node *, - void *), - void *data, - bool include_overwritable) -{ - if (callback (this, data)) - return true; - if (has_aliases_p ()) - return call_for_symbol_and_aliases_1 (callback, data, include_overwritable); - return false; -} - -/* Return true if NODE's address can be compared. */ - -inline bool -symtab_node::address_can_be_compared_p () -{ - /* Address of virtual tables and functions is never compared. */ - if (DECL_VIRTUAL_P (decl)) - return false; - /* Address of C++ cdtors is never compared. */ - if (is_a (this) - && (DECL_CXX_CONSTRUCTOR_P (decl) - || DECL_CXX_DESTRUCTOR_P (decl))) - return false; - /* Constant pool symbols addresses are never compared. - flag_merge_constants permits us to assume the same on readonly vars. */ - if (is_a (this) - && (DECL_IN_CONSTANT_POOL (decl) - || (flag_merge_constants >= 2 - && TREE_READONLY (decl) && !TREE_THIS_VOLATILE (decl)))) - return false; - return true; -} - -/* Return true if refernece may be used in address compare. */ - -inline bool -ipa_ref::address_matters_p () -{ - if (use != IPA_REF_ADDR) - return false; - /* Addresses taken from virtual tables are never compared. */ - if (is_a (referring) - && DECL_VIRTUAL_P (referring->decl)) - return false; - return referred->address_can_be_compared_p (); -} - -/* Build polymorphic call context for indirect call E. */ - -inline -ipa_polymorphic_call_context::ipa_polymorphic_call_context (cgraph_edge *e) -{ - gcc_checking_assert (e->indirect_info->polymorphic); - *this = e->indirect_info->context; -} - -/* Build empty "I know nothing" context. */ - -inline -ipa_polymorphic_call_context::ipa_polymorphic_call_context () -{ - clear_speculation (); - clear_outer_type (); - invalid = false; -} - -/* Make context non-speculative. */ - -inline void -ipa_polymorphic_call_context::clear_speculation () -{ - speculative_outer_type = NULL; - speculative_offset = 0; - speculative_maybe_derived_type = false; -} - -/* Produce context specifying all derrived types of OTR_TYPE. If OTR_TYPE is - NULL, the context is set to dummy "I know nothing" setting. */ - -inline void -ipa_polymorphic_call_context::clear_outer_type (tree otr_type) -{ - outer_type = otr_type ? TYPE_MAIN_VARIANT (otr_type) : NULL; - offset = 0; - maybe_derived_type = true; - maybe_in_construction = true; - dynamic = true; -} - -/* Adjust all offsets in contexts by OFF bits. */ - -inline void -ipa_polymorphic_call_context::offset_by (HOST_WIDE_INT off) -{ - if (outer_type) - offset += off; - if (speculative_outer_type) - speculative_offset += off; -} - -/* Return TRUE if context is fully useless. */ - -inline bool -ipa_polymorphic_call_context::useless_p () const -{ - return (!outer_type && !speculative_outer_type); -} - -/* Return true if NODE is local. Instrumentation clones are counted as local - only when original function is local. */ - -static inline bool -cgraph_local_p (cgraph_node *node) -{ - if (!node->instrumentation_clone || !node->instrumented_version) - return node->local.local; - - return node->local.local && node->instrumented_version->local.local; -} - -/* When using fprintf (or similar), problems can arise with - transient generated strings. Many string-generation APIs - only support one result being alive at once (e.g. by - returning a pointer to a statically-allocated buffer). - - If there is more than one generated string within one - fprintf call: the first string gets evicted or overwritten - by the second, before fprintf is fully evaluated. - See e.g. PR/53136. - - This function provides a workaround for this, by providing - a simple way to create copies of these transient strings, - without the need to have explicit cleanup: - - fprintf (dumpfile, "string 1: %s string 2:%s\n", - xstrdup_for_dump (EXPR_1), - xstrdup_for_dump (EXPR_2)); - - This is actually a simple wrapper around ggc_strdup, but - the name documents the intent. We require that no GC can occur - within the fprintf call. */ - -static inline const char * -xstrdup_for_dump (const char *transient_str) -{ - return ggc_strdup (transient_str); -} - -#endif /* GCC_CGRAPH_H */ diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/chkp-builtins.def b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/chkp-builtins.def deleted file mode 100644 index 97c1898..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/chkp-builtins.def +++ /dev/null @@ -1,71 +0,0 @@ -/* This file contains the definitions and documentation for the - builtins used in the GNU compiler. - Copyright (C) 2013-2015 Free Software Foundation, Inc. - -This file is part of GCC. - -GCC is free software; you can redistribute it and/or modify it under -the terms of the GNU General Public License as published by the Free -Software Foundation; either version 3, or (at your option) any later -version. - -GCC is distributed in the hope that it will be useful, but WITHOUT ANY -WARRANTY; without even the implied warranty of MERCHANTABILITY or -FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -for more details. - -You should have received a copy of the GNU General Public License -along with GCC; see the file COPYING3. If not see -. */ - -/* Before including this file, you should define macros: - - DEF_BUILTIN_STUB(ENUM, NAME) - DEF_CHKP_BUILTIN(ENUM, NAME, TYPE, ATTRS) - - See builtins.def for details. */ - -/* Following builtins are used by compiler for Pointer Bounds Checker - instrumentation. Currently these generic builtins are not - implemented and target has to provide his own version. See - builtin_chkp_function target hook documentation for more details. */ -DEF_BUILTIN_STUB (BUILT_IN_CHKP_INTERSECT, "__chkp_intersect") -DEF_BUILTIN_STUB (BUILT_IN_CHKP_SIZEOF, "__chkp_sizeof") -DEF_BUILTIN_STUB (BUILT_IN_CHKP_NARROW, "__chkp_narrow") -DEF_CHKP_BUILTIN (BUILT_IN_CHKP_BNDCL, "__chkp_bndcl", BT_FN_VOID_PTR_BND, ATTR_NOTHROW_LEAF_LIST) -DEF_CHKP_BUILTIN (BUILT_IN_CHKP_BNDCU, "__chkp_bndcu", BT_FN_VOID_PTR_BND, ATTR_NOTHROW_LEAF_LIST) -DEF_CHKP_BUILTIN (BUILT_IN_CHKP_BNDSTX, "__chkp_bndstx", BT_FN_VOID_CONST_PTR_BND_CONST_PTR, ATTR_NOTHROW_LEAF_LIST) -DEF_CHKP_BUILTIN (BUILT_IN_CHKP_BNDLDX, "__chkp_bndldx", BT_FN_CONST_PTR_CONST_PTR_CONST_PTR, ATTR_NOTHROW_LEAF_LIST) -DEF_CHKP_BUILTIN (BUILT_IN_CHKP_BNDRET, "__chkp_bndret", BT_FN_BND_CONST_PTR, ATTR_CONST_NOTHROW_LEAF_LIST) -DEF_CHKP_BUILTIN (BUILT_IN_CHKP_BNDMK, "__chkp_bndmk", BT_FN_BND_CONST_PTR_SIZE, ATTR_CONST_NOTHROW_LEAF_LIST) -DEF_CHKP_BUILTIN (BUILT_IN_CHKP_EXTRACT_LOWER, "__chkp_extract_lower", BT_FN_CONST_PTR_BND, ATTR_CONST_NOTHROW_LEAF_LIST) -DEF_CHKP_BUILTIN (BUILT_IN_CHKP_EXTRACT_UPPER, "__chkp_extract_upper", BT_FN_CONST_PTR_BND, ATTR_CONST_NOTHROW_LEAF_LIST) - -/* Pointer Bounds Checker builtins for users. - All builtins calls are expanded in the - Pointer Bounds Checker pass. */ -DEF_CHKP_BUILTIN (BUILT_IN_CHKP_SET_PTR_BOUNDS, "__bnd_set_ptr_bounds", BT_FN_PTR_CONST_PTR_SIZE, ATTR_CONST_NOTHROW_LEAF_LIST) -DEF_CHKP_BUILTIN (BUILT_IN_CHKP_INIT_PTR_BOUNDS, "__bnd_init_ptr_bounds", BT_FN_PTR_CONST_PTR, ATTR_CONST_NOTHROW_LEAF_LIST) -DEF_CHKP_BUILTIN (BUILT_IN_CHKP_NULL_PTR_BOUNDS, "__bnd_null_ptr_bounds", BT_FN_PTR_CONST_PTR, ATTR_CONST_NOTHROW_LEAF_LIST) -DEF_CHKP_BUILTIN (BUILT_IN_CHKP_COPY_PTR_BOUNDS, "__bnd_copy_ptr_bounds", BT_FN_PTR_CONST_PTR_CONST_PTR, ATTR_CONST_NOTHROW_LEAF_LIST) -DEF_CHKP_BUILTIN (BUILT_IN_CHKP_NARROW_PTR_BOUNDS, "__bnd_narrow_ptr_bounds", BT_FN_PTR_CONST_PTR_CONST_PTR_SIZE, ATTR_CONST_NOTHROW_LEAF_LIST) -DEF_CHKP_BUILTIN (BUILT_IN_CHKP_STORE_PTR_BOUNDS, "__bnd_store_ptr_bounds", BT_FN_VOID_PTRPTR_CONST_PTR, ATTR_NOTHROW_LEAF_LIST) -DEF_CHKP_BUILTIN (BUILT_IN_CHKP_CHECK_PTR_LBOUNDS, "__bnd_chk_ptr_lbounds", BT_FN_VOID_CONST_PTR, ATTR_NOTHROW_LEAF_LIST) -DEF_CHKP_BUILTIN (BUILT_IN_CHKP_CHECK_PTR_UBOUNDS, "__bnd_chk_ptr_ubounds", BT_FN_VOID_CONST_PTR, ATTR_NOTHROW_LEAF_LIST) -DEF_CHKP_BUILTIN (BUILT_IN_CHKP_CHECK_PTR_BOUNDS, "__bnd_chk_ptr_bounds", BT_FN_VOID_CONST_PTR_SIZE, ATTR_NOTHROW_LEAF_LIST) -DEF_CHKP_BUILTIN (BUILT_IN_CHKP_GET_PTR_LBOUND, "__bnd_get_ptr_lbound", BT_FN_CONST_PTR_CONST_PTR, ATTR_CONST_NOTHROW_LEAF_LIST) -DEF_CHKP_BUILTIN (BUILT_IN_CHKP_GET_PTR_UBOUND, "__bnd_get_ptr_ubound", BT_FN_CONST_PTR_CONST_PTR, ATTR_CONST_NOTHROW_LEAF_LIST) - -/* Pointer Bounds Checker specific versions of string functions. */ -DEF_CHKP_BUILTIN (BUILT_IN_CHKP_MEMCPY_NOBND, "chkp_memcpy_nobnd", BT_FN_PTR_PTR_CONST_PTR_SIZE, ATTR_RET1_NOTHROW_NONNULL_LEAF) -DEF_CHKP_BUILTIN (BUILT_IN_CHKP_MEMCPY_NOCHK, "chkp_memcpy_nochk", BT_FN_PTR_PTR_CONST_PTR_SIZE, ATTR_RET1_NOTHROW_NONNULL_LEAF) -DEF_CHKP_BUILTIN (BUILT_IN_CHKP_MEMCPY_NOBND_NOCHK, "chkp_memcpy_nobnd_nochk", BT_FN_PTR_PTR_CONST_PTR_SIZE, ATTR_RET1_NOTHROW_NONNULL_LEAF) -DEF_CHKP_BUILTIN (BUILT_IN_CHKP_MEMMOVE_NOBND, "chkp_memmove_nobnd", BT_FN_PTR_PTR_CONST_PTR_SIZE, ATTR_RET1_NOTHROW_NONNULL_LEAF) -DEF_CHKP_BUILTIN (BUILT_IN_CHKP_MEMMOVE_NOCHK, "chkp_memmove_nochk", BT_FN_PTR_PTR_CONST_PTR_SIZE, ATTR_RET1_NOTHROW_NONNULL_LEAF) -DEF_CHKP_BUILTIN (BUILT_IN_CHKP_MEMMOVE_NOBND_NOCHK, "chkp_memmove_nobnd_nochk", BT_FN_PTR_PTR_CONST_PTR_SIZE, ATTR_RET1_NOTHROW_NONNULL_LEAF) -DEF_CHKP_BUILTIN (BUILT_IN_CHKP_MEMPCPY_NOBND, "chkp_mempcpy_nobnd", BT_FN_PTR_PTR_CONST_PTR_SIZE, ATTR_NOTHROW_NONNULL_LEAF) -DEF_CHKP_BUILTIN (BUILT_IN_CHKP_MEMPCPY_NOCHK, "chkp_mempcpy_nochk", BT_FN_PTR_PTR_CONST_PTR_SIZE, ATTR_NOTHROW_NONNULL_LEAF) -DEF_CHKP_BUILTIN (BUILT_IN_CHKP_MEMPCPY_NOBND_NOCHK, "chkp_mempcpy_nobnd_nochk", BT_FN_PTR_PTR_CONST_PTR_SIZE, ATTR_NOTHROW_NONNULL_LEAF) -DEF_CHKP_BUILTIN (BUILT_IN_CHKP_MEMSET_NOBND, "chkp_memset_nobnd", BT_FN_PTR_PTR_INT_SIZE, ATTR_RET1_NOTHROW_NONNULL_LEAF) -DEF_CHKP_BUILTIN (BUILT_IN_CHKP_MEMSET_NOCHK, "chkp_memset_nochk", BT_FN_PTR_PTR_INT_SIZE, ATTR_RET1_NOTHROW_NONNULL_LEAF) -DEF_CHKP_BUILTIN (BUILT_IN_CHKP_MEMSET_NOBND_NOCHK, "chkp_memset_nobnd_nochk", BT_FN_PTR_PTR_INT_SIZE, ATTR_RET1_NOTHROW_NONNULL_LEAF) diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/cif-code.def b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/cif-code.def deleted file mode 100644 index c70888d..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/cif-code.def +++ /dev/null @@ -1,133 +0,0 @@ -/* This file contains the definitions of the cgraph_inline_failed_t - enums used in GCC. - - Copyright (C) 2008-2015 Free Software Foundation, Inc. - Contributed by Doug Kwan - -This file is part of GCC. - -GCC is free software you can redistribute it and/or modify it under -the terms of the GNU General Public License as published by the Free -Software Foundation either version 3, or (at your option) any later -version. - -GCC is distributed in the hope that it will be useful, but WITHOUT ANY -WARRANTY without even the implied warranty of MERCHANTABILITY or -FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -for more details. - -You should have received a copy of the GNU General Public License -along with GCC see the file COPYING3. If not see -. */ - -/* The format of this file is - DEFCIFCODE(code, string). - - Where symbol is the enumeration name without the ``''. - The argument STRING is a explain the failure. Except for OK, - which is a NULL pointer. */ - -/* Inlining successful. This must be the first code. */ -DEFCIFCODE(OK, CIF_FINAL_NORMAL, NULL) - -/* Inlining failed for an unspecified reason. */ -DEFCIFCODE(UNSPECIFIED, CIF_FINAL_ERROR, "") - -/* Function has not be considered for inlining. This is the code for - functions that have not been rejected for inlining yet. */ -DEFCIFCODE(FUNCTION_NOT_CONSIDERED, CIF_FINAL_NORMAL, - N_("function not considered for inlining")) - -/* Caller is compiled with optimizations disabled. */ -DEFCIFCODE(FUNCTION_NOT_OPTIMIZED, CIF_FINAL_ERROR, - N_("caller is not optimized")) - -/* Inlining failed owing to unavailable function body. */ -DEFCIFCODE(BODY_NOT_AVAILABLE, CIF_FINAL_ERROR, - N_("function body not available")) - -/* Extern inline function that has been redefined. */ -DEFCIFCODE(REDEFINED_EXTERN_INLINE, CIF_FINAL_ERROR, - N_("redefined extern inline functions are not considered for " - "inlining")) - -/* Function is not inlinable. */ -DEFCIFCODE(FUNCTION_NOT_INLINABLE, CIF_FINAL_ERROR, - N_("function not inlinable")) - -/* Function is overwritable. */ -DEFCIFCODE(OVERWRITABLE, CIF_FINAL_ERROR, - N_("function body can be overwritten at link time")) - -/* Function is not an inlining candidate. */ -DEFCIFCODE(FUNCTION_NOT_INLINE_CANDIDATE, CIF_FINAL_NORMAL, - N_("function not inline candidate")) - -/* Inlining failed because of various limit parameters. */ -DEFCIFCODE(LARGE_FUNCTION_GROWTH_LIMIT, CIF_FINAL_NORMAL, - N_("--param large-function-growth limit reached")) -DEFCIFCODE(LARGE_STACK_FRAME_GROWTH_LIMIT, CIF_FINAL_NORMAL, - N_("--param large-stack-frame-growth limit reached")) -DEFCIFCODE(MAX_INLINE_INSNS_SINGLE_LIMIT, CIF_FINAL_NORMAL, - N_("--param max-inline-insns-single limit reached")) -DEFCIFCODE(MAX_INLINE_INSNS_AUTO_LIMIT, CIF_FINAL_NORMAL, - N_("--param max-inline-insns-auto limit reached")) -DEFCIFCODE(INLINE_UNIT_GROWTH_LIMIT, CIF_FINAL_NORMAL, - N_("--param inline-unit-growth limit reached")) - -/* Recursive inlining. */ -DEFCIFCODE(RECURSIVE_INLINING, CIF_FINAL_NORMAL, - N_("recursive inlining")) - -/* Call is unlikely. */ -DEFCIFCODE(UNLIKELY_CALL, CIF_FINAL_NORMAL, - N_("call is unlikely and code size would grow")) - -/* Function is not declared as inline. */ -DEFCIFCODE(NOT_DECLARED_INLINED, CIF_FINAL_NORMAL, - N_("function not declared inline and code size would grow")) - -/* Caller and callee disagree on the arguments. */ -DEFCIFCODE(MISMATCHED_ARGUMENTS, CIF_FINAL_ERROR, - N_("mismatched arguments")) - -/* Call was originally indirect. */ -DEFCIFCODE(ORIGINALLY_INDIRECT_CALL, CIF_FINAL_NORMAL, - N_("originally indirect function call not considered for inlining")) - -/* Ths edge represents an indirect edge with a yet-undetermined callee . */ -DEFCIFCODE(INDIRECT_UNKNOWN_CALL, CIF_FINAL_NORMAL, - N_("indirect function call with a yet undetermined callee")) - -/* We can't inline different EH personalities together. */ -DEFCIFCODE(EH_PERSONALITY, CIF_FINAL_ERROR, - N_("exception handling personality mismatch")) - -/* We can't inline if the callee can throw non-call exceptions but the - caller cannot. */ -DEFCIFCODE(NON_CALL_EXCEPTIONS, CIF_FINAL_ERROR, - N_("non-call exception handling mismatch")) - -/* We can't inline because of mismatched target specific options. */ -DEFCIFCODE(TARGET_OPTION_MISMATCH, CIF_FINAL_ERROR, - N_("target specific option mismatch")) - -/* We can't inline because of mismatched optimization levels. */ -DEFCIFCODE(OPTIMIZATION_MISMATCH, CIF_FINAL_ERROR, - N_("optimization level attribute mismatch")) - -/* We can't inline because the callee refers to comdat-local symbols. */ -DEFCIFCODE(USES_COMDAT_LOCAL, CIF_FINAL_ERROR, - N_("callee refers to comdat-local symbols")) - -/* We can't inline because of mismatched caller/callee attributes. */ -DEFCIFCODE(ATTRIBUTE_MISMATCH, CIF_FINAL_ERROR, - N_("function attribute mismatch")) - -/* We can't inline because of mismatched caller/callee attributes. */ -DEFCIFCODE(CILK_SPAWN, CIF_FINAL_ERROR, - N_("caller function contains cilk spawn")) - -/* We proved that the call is unreachable. */ -DEFCIFCODE(UNREACHABLE, CIF_FINAL_ERROR, - N_("unreachable")) diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/cilk-builtins.def b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/cilk-builtins.def deleted file mode 100644 index 6dd24e8..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/cilk-builtins.def +++ /dev/null @@ -1,35 +0,0 @@ -/* This file contains the definitions and documentation for the - Cilk Plus builtins used in the GNU compiler. - Copyright (C) 2013-2015 Free Software Foundation, Inc. - - Contributed by Balaji V. Iyer - Intel Corporation. - -This file is part of GCC. - -GCC is free software; you can redistribute it and/or modify it under -the terms of the GNU General Public License as published by the Free -Software Foundation; either version 3, or (at your option) any later -version. - -GCC is distributed in the hope that it will be useful, but WITHOUT ANY -WARRANTY; without even the implied warranty of MERCHANTABILITY or -FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -for more details. - -You should have received a copy of the GNU General Public License -along with GCC; see the file COPYING3. If not see -. */ - -DEF_CILK_BUILTIN_STUB (BUILT_IN_CILK_ENTER_FRAME, "__cilkrts_enter_frame_1") -DEF_CILK_BUILTIN_STUB (BUILT_IN_CILK_ENTER_FRAME_FAST, - "__cilkrts_enter_frame_fast_1") -DEF_CILK_BUILTIN_STUB (BUILT_IN_CILK_DETACH, "__cilkrts_detach") -DEF_CILK_BUILTIN_STUB (BUILT_IN_CILK_RETHROW, "__cilkrts_rethrow") -DEF_CILK_BUILTIN_STUB (BUILT_IN_CILK_SYNCHED, "__cilkrts_synched") -DEF_CILK_BUILTIN_STUB (BUILT_IN_CILK_SYNC, "__cilkrts_sync") -DEF_CILK_BUILTIN_STUB (BUILT_IN_CILK_LEAVE_FRAME, "__cilkrts_leave_frame") -DEF_CILK_BUILTIN_STUB (BUILT_IN_CILK_POP_FRAME, "__cilkrts_pop_frame") -DEF_CILK_BUILTIN_STUB (BUILT_IN_CILK_SAVE_FP, "__cilkrts_save_fp_ctrl_state") -DEF_CILK_BUILTIN_STUB (BUILT_IN_CILK_FOR_32, "__cilkrts_cilk_for_32") -DEF_CILK_BUILTIN_STUB (BUILT_IN_CILK_FOR_64, "__cilkrts_cilk_for_64") diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/cilk.h b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/cilk.h deleted file mode 100644 index 5c0db55..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/cilk.h +++ /dev/null @@ -1,109 +0,0 @@ -/* This file is part of the Intel(R) Cilk(TM) Plus support - This file contains Cilk Support files. - Copyright (C) 2013-2015 Free Software Foundation, Inc. - Contributed by Balaji V. Iyer , - Intel Corporation - - This file is part of GCC. - - GCC is free software; you can redistribute it and/or modify it - under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3, or (at your option) - any later version. - - GCC is distributed in the hope that it will be useful, but - WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - General Public License for more details. - - You should have received a copy of the GNU General Public License - along with GCC; see the file COPYING3. If not see - . */ - -#ifndef GCC_CILK_H -#define GCC_CILK_H - -/* Frame status bits known to compiler. */ -#define CILK_FRAME_UNSYNCHED 0x02 -#define CILK_FRAME_DETACHED 0x04 -#define CILK_FRAME_EXCEPTING 0x10 -#define CILK_FRAME_VERSION (1 << 24) - -enum cilk_tree_index { -/* All the built-in functions for Cilk keywords. */ - CILK_TI_F_WORKER = 0, /* __cilkrts_get_worker (). */ - CILK_TI_F_SYNC, /* __cilkrts_sync (). */ - CILK_TI_F_DETACH, /* __cilkrts_detach (...). */ - CILK_TI_F_ENTER, /* __cilkrts_enter_frame (...). */ - CILK_TI_F_ENTER_FAST, /* __cilkrts_enter_frame_fast (.). */ - CILK_TI_F_LEAVE, /* __cilkrts_leave_frame (...). */ - CILK_TI_F_POP, /* __cilkrts_pop_frame (...). */ - CILK_TI_F_RETHROW, /* __cilkrts_rethrow (...). */ - CILK_TI_F_SAVE_FP, /* __cilkrts_save_fp_ctrl_state (...). */ - CILK_TI_F_LOOP_32, /* __cilkrts_cilk_for_32 (...). */ - CILK_TI_F_LOOP_64, /* __cilkrts_cilk_for_64 (...). */ - - /* __cilkrts_stack_frame struct fields. */ - CILK_TI_FRAME_FLAGS, /* stack_frame->flags. */ - CILK_TI_FRAME_PARENT, /* stack_frame->parent. */ - CILK_TI_FRAME_WORKER, /* stack_frame->worker. */ - CILK_TI_FRAME_EXCEPTION, /* stack_frame->except_data. */ - CILK_TI_FRAME_CONTEXT, /* stack_frame->context[4]. */ - CILK_TI_FRAME_PEDIGREE, /* stack_frame->pedigree. */ - - /* __cilkrts_worker struct fields. */ - CILK_TI_WORKER_CUR, /* worker->current_stack_frame. */ - CILK_TI_WORKER_TAIL, /* worker->tail. */ - CILK_TI_WORKER_PEDIGREE, /* worker->pedigree. */ - - /* __cilkrts_pedigree struct fields. */ - CILK_TI_PEDIGREE_RANK, /* pedigree->rank. */ - CILK_TI_PEDIGREE_PARENT, /* pedigree->parent. */ - - /* Types. */ - CILK_TI_FRAME_TYPE, /* struct __cilkrts_stack_frame. */ - CILK_TI_FRAME_PTR, /* __cilkrts_stack_frame *. */ - CILK_TI_WORKER_TYPE, /* struct __cilkrts_worker. */ - CILK_TI_PEDIGREE_TYPE, /* struct __cilkrts_pedigree. */ - CILK_TI_MAX -}; - -extern GTY (()) tree cilk_trees[CILK_TI_MAX]; - -#define cilk_worker_fndecl cilk_trees[CILK_TI_F_WORKER] -#define cilk_sync_fndecl cilk_trees[CILK_TI_F_SYNC] -#define cilk_synched_fndecl cilk_trees[CILK_TI_F_SYNCED] -#define cilk_detach_fndecl cilk_trees[CILK_TI_F_DETACH] -#define cilk_enter_fndecl cilk_trees[CILK_TI_F_ENTER] -#define cilk_enter_fast_fndecl cilk_trees[CILK_TI_F_ENTER_FAST] -#define cilk_leave_fndecl cilk_trees[CILK_TI_F_LEAVE] -#define cilk_rethrow_fndecl cilk_trees[CILK_TI_F_RETHROW] -#define cilk_pop_fndecl cilk_trees[CILK_TI_F_POP] -#define cilk_save_fp_fndecl cilk_trees[CILK_TI_F_SAVE_FP] -#define cilk_for_32_fndecl cilk_trees[CILK_TI_F_LOOP_32] -#define cilk_for_64_fndecl cilk_trees[CILK_TI_F_LOOP_64] - -#define cilk_worker_type_fndecl cilk_trees[CILK_TI_WORKER_TYPE] -#define cilk_frame_type_decl cilk_trees[CILK_TI_FRAME_TYPE] -#define cilk_frame_ptr_type_decl cilk_trees[CILK_TI_FRAME_PTR] -#define cilk_pedigree_type_decl cilk_trees[CILK_TI_PEDIGREE_TYPE] - -extern void expand_builtin_cilk_detach (tree); -extern void expand_builtin_cilk_pop_frame (tree); -extern tree cilk_arrow (tree, int, bool); -extern tree cilk_dot (tree, int, bool); -extern void cilk_init_builtins (void); -extern void gimplify_cilk_sync (tree *, gimple_seq *); -extern tree cilk_call_setjmp (tree); - -/* Returns true if Cilk Plus is enabled and if F->cilk_frame_decl is not - NULL_TREE. */ - -inline bool -fn_contains_cilk_spawn_p (function *f) -{ - return (flag_cilkplus - && (f->calls_cilk_spawn || f->cilk_frame_decl != NULL_TREE)); -} - -#endif diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/cilkplus.def b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/cilkplus.def deleted file mode 100644 index 0f65e65..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/cilkplus.def +++ /dev/null @@ -1,59 +0,0 @@ -/* This file contains the definitions and documentation for the - CilkPlus builtins used in the GNU compiler. - Copyright (C) 2013-2015 Free Software Foundation, Inc. - -This file is part of GCC. - -GCC is free software; you can redistribute it and/or modify it under -the terms of the GNU General Public License as published by the Free -Software Foundation; either version 3, or (at your option) any later -version. - -GCC is distributed in the hope that it will be useful, but WITHOUT ANY -WARRANTY; without even the implied warranty of MERCHANTABILITY or -FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -for more details. - -You should have received a copy of the GNU General Public License -along with GCC; see the file COPYING3. If not see -. */ - -/* Before including this file, you should define a macro: - - DEF_CILKPLUS_BUILTIN (ENUM, NAME, TYPE, ATTRS) - - See builtins.def for details. */ - -DEF_CILKPLUS_BUILTIN (BUILT_IN_CILKPLUS_SEC_REDUCE_ADD, - "__sec_reduce_add", BT_FN_INT_PTR, ATTR_NULL) -DEF_CILKPLUS_BUILTIN (BUILT_IN_CILKPLUS_SEC_REDUCE_MUL, - "__sec_reduce_mul", BT_FN_INT_PTR, ATTR_NULL) -DEF_CILKPLUS_BUILTIN (BUILT_IN_CILKPLUS_SEC_REDUCE_ALL_ZERO, - "__sec_reduce_all_zero", BT_FN_INT_PTR, ATTR_NULL) -DEF_CILKPLUS_BUILTIN (BUILT_IN_CILKPLUS_SEC_REDUCE_ANY_ZERO, - "__sec_reduce_any_zero", BT_FN_INT_PTR, ATTR_NULL) -DEF_CILKPLUS_BUILTIN (BUILT_IN_CILKPLUS_SEC_REDUCE_MAX, - "__sec_reduce_max", BT_FN_INT_PTR, ATTR_NULL) -DEF_CILKPLUS_BUILTIN (BUILT_IN_CILKPLUS_SEC_REDUCE_MIN, - "__sec_reduce_min", BT_FN_INT_PTR, ATTR_NULL) -DEF_CILKPLUS_BUILTIN (BUILT_IN_CILKPLUS_SEC_REDUCE_MIN_IND, - "__sec_reduce_min_ind", BT_FN_INT_PTR, ATTR_NULL) -DEF_CILKPLUS_BUILTIN (BUILT_IN_CILKPLUS_SEC_REDUCE_MAX_IND, - "__sec_reduce_max_ind", BT_FN_INT_PTR, ATTR_NULL) -DEF_CILKPLUS_BUILTIN (BUILT_IN_CILKPLUS_SEC_REDUCE_ANY_NONZERO, - "__sec_reduce_any_nonzero", BT_FN_INT_PTR, ATTR_NULL) -DEF_CILKPLUS_BUILTIN (BUILT_IN_CILKPLUS_SEC_REDUCE_ALL_NONZERO, - "__sec_reduce_all_nonzero", BT_FN_INT_PTR, ATTR_NULL) -DEF_CILKPLUS_BUILTIN (BUILT_IN_CILKPLUS_SEC_REDUCE, - "__sec_reduce", BT_FN_INT_PTR_PTR_PTR, ATTR_NULL) -DEF_CILKPLUS_BUILTIN (BUILT_IN_CILKPLUS_SEC_REDUCE_MUTATING, - "__sec_reduce_mutating", BT_FN_INT_PTR_PTR_PTR, ATTR_NULL) -// FIXME: This probably needs to be rewritten as a keyword. -DEF_CILKPLUS_BUILTIN (BUILT_IN_CILKPLUS_SEC_IMPLICIT_INDEX, - "__sec_implicit_index", BT_FN_INT_INT, ATTR_NULL) - -/* -Local variables: -mode:c -End: -*/ diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/collect-utils.h b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/collect-utils.h deleted file mode 100644 index 2b3ed44..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/collect-utils.h +++ /dev/null @@ -1,49 +0,0 @@ -/* Utility functions used by tools like collect2 and lto-wrapper. - Copyright (C) 2009-2015 Free Software Foundation, Inc. - -This file is part of GCC. - -GCC is free software; you can redistribute it and/or modify it under -the terms of the GNU General Public License as published by the Free -Software Foundation; either version 3, or (at your option) any later -version. - -GCC is distributed in the hope that it will be useful, but WITHOUT ANY -WARRANTY; without even the implied warranty of MERCHANTABILITY or -FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -for more details. - -You should have received a copy of the GNU General Public License -along with GCC; see the file COPYING3. If not see -. */ - -#ifndef GCC_COLLECT_UTILS_H -#define GCC_COLLECT_UTILS_H - -/* Provided in collect-utils.c. */ -extern void notice (const char *, ...) - __attribute__ ((format (printf, 1, 2))); -extern void fatal_signal (int); - -extern struct pex_obj *collect_execute (const char *, char **, - const char *, const char *, - int, bool); -extern int collect_wait (const char *, struct pex_obj *); -extern void do_wait (const char *, struct pex_obj *); -extern void fork_execute (const char *, char **, bool); -extern void utils_cleanup (bool); - - -extern bool debug; -extern bool verbose; -extern bool save_temps; - -/* Provided by the tool itself. */ - -/* The name of the tool, printed in error messages. */ -extern const char tool_name[]; -/* Called by utils_cleanup. */ -extern void tool_cleanup (bool); -extern void maybe_unlink (const char *); - -#endif /* GCC_COLLECT_UTILS_H */ diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/collect2-aix.h b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/collect2-aix.h deleted file mode 100644 index a6abec9..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/collect2-aix.h +++ /dev/null @@ -1,306 +0,0 @@ -/* AIX cross support for collect2. - Copyright (C) 2009-2015 Free Software Foundation, Inc. - -This file is part of GCC. - -GCC is free software; you can redistribute it and/or modify it under -the terms of the GNU General Public License as published by the Free -Software Foundation; either version 3, or (at your option) any later -version. - -GCC is distributed in the hope that it will be useful, but WITHOUT ANY -WARRANTY; without even the implied warranty of MERCHANTABILITY or -FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -for more details. - -You should have received a copy of the GNU General Public License -along with GCC; see the file COPYING3. If not see -. */ - -#ifndef GCC_COLLECT2_AIX_H -#define GCC_COLLECT2_AIX_H -/* collect2-aix.c requires mmap support. It should otherwise be - fairly portable. */ -#if defined(CROSS_DIRECTORY_STRUCTURE) \ - && defined(TARGET_AIX_VERSION) \ - && HAVE_MMAP - -#define CROSS_AIX_SUPPORT 1 - -/* ------------------------------------------------------------------------- - Definitions adapted from bfd. (Fairly heavily adapted in some cases.) - ------------------------------------------------------------------------- */ - -/* Compatibility types for bfd. */ -typedef unsigned HOST_WIDE_INT bfd_vma; - -/* The size of an archive's fl_magic field. */ -#define FL_MAGIC_SIZE 8 - -/* The expected contents of fl_magic for big archives. */ -#define FL_MAGIC_BIG_AR "\012" - -/* The size of each offset string in the header of a big archive. */ -#define AR_BIG_OFFSET_SIZE 20 - -/* The format of the file header in a "big" XCOFF archive. */ -struct external_big_ar_filehdr -{ - /* Magic string. */ - char fl_magic[FL_MAGIC_SIZE]; - - /* Offset of the member table (decimal ASCII string). */ - char fl_memoff[AR_BIG_OFFSET_SIZE]; - - /* Offset of the global symbol table for 32-bit objects (decimal ASCII - string). */ - char fl_symoff[AR_BIG_OFFSET_SIZE]; - - /* Offset of the global symbol table for 64-bit objects (decimal ASCII - string). */ - char fl_symoff64[AR_BIG_OFFSET_SIZE]; - - /* Offset of the first member in the archive (decimal ASCII string). */ - char fl_firstmemoff[AR_BIG_OFFSET_SIZE]; - - /* Offset of the last member in the archive (decimal ASCII string). */ - char fl_lastmemoff[AR_BIG_OFFSET_SIZE]; - - /* Offset of the first member on the free list (decimal ASCII - string). */ - char fl_freeoff[AR_BIG_OFFSET_SIZE]; -}; - -/* Each archive name is followed by this many bytes of magic string. */ -#define SXCOFFARFMAG 2 - -/* The format of a member header in a "big" XCOFF archive. */ -struct external_big_ar_member -{ - /* File size not including the header (decimal ASCII string). */ - char ar_size[AR_BIG_OFFSET_SIZE]; - - /* File offset of next archive member (decimal ASCII string). */ - char ar_nextoff[AR_BIG_OFFSET_SIZE]; - - /* File offset of previous archive member (decimal ASCII string). */ - char ar_prevoff[AR_BIG_OFFSET_SIZE]; - - /* File mtime (decimal ASCII string). */ - char ar_date[12]; - - /* File UID (decimal ASCII string). */ - char ar_uid[12]; - - /* File GID (decimal ASCII string). */ - char ar_gid[12]; - - /* File mode (octal ASCII string). */ - char ar_mode[12]; - - /* Length of file name (decimal ASCII string). */ - char ar_namlen[4]; - - /* This structure is followed by the file name. The length of the - name is given in the namlen field. If the length of the name is - odd, the name is followed by a null byte. The name and optional - null byte are followed by XCOFFARFMAG, which is not included in - namlen. The contents of the archive member follow; the number of - bytes is given in the size field. */ -}; - -/* The known values of f_magic in an XCOFF file header. */ -#define U802WRMAGIC 0730 /* Writeable text segments. */ -#define U802ROMAGIC 0735 /* Readonly sharable text segments. */ -#define U802TOCMAGIC 0737 /* Readonly text segments and TOC. */ -#define U803XTOCMAGIC 0757 /* Aix 4.3 64-bit XCOFF. */ -#define U64_TOCMAGIC 0767 /* AIX 5+ 64-bit XCOFF. */ - -/* The number of bytes in an XCOFF file's f_magic field. */ -#define F_MAGIC_SIZE 2 - -/* The format of a 32-bit XCOFF file header. */ -struct external_filehdr_32 -{ - /* The magic number. */ - char f_magic[F_MAGIC_SIZE]; - - /* The number of sections. */ - char f_nscns[2]; - - /* Time & date stamp. */ - char f_timdat[4]; - - /* The offset of the symbol table from the start of the file. */ - char f_symptr[4]; - - /* The number of entries in the symbol table. */ - char f_nsyms[4]; - - /* The size of the auxiliary header. */ - char f_opthdr[2]; - - /* Flags. */ - char f_flags[2]; -}; - -/* The format of a 64-bit XCOFF file header. */ -struct external_filehdr_64 -{ - /* The magic number. */ - char f_magic[F_MAGIC_SIZE]; - - /* The number of sections. */ - char f_nscns[2]; - - /* Time & date stamp. */ - char f_timdat[4]; - - /* The offset of the symbol table from the start of the file. */ - char f_symptr[8]; - - /* The size of the auxiliary header. */ - char f_opthdr[2]; - - /* Flags. */ - char f_flags[2]; - - /* The number of entries in the symbol table. */ - char f_nsyms[4]; -}; - -/* An internal representation of the XCOFF file header. */ -struct internal_filehdr -{ - unsigned short f_magic; - unsigned short f_nscns; - long f_timdat; - bfd_vma f_symptr; - long f_nsyms; - unsigned short f_opthdr; - unsigned short f_flags; -}; - -/* Symbol classes have their names in the debug section if this flag - is set. */ -#define DBXMASK 0x80 - -/* The format of an XCOFF symbol-table entry. */ -struct external_syment -{ - union { - struct { - union { - /* The name of the symbol. There is an implicit null character - after the end of the array. */ - char n_name[8]; - struct { - /* If n_zeroes is zero, n_offset is the offset the name from - the start of the string table. */ - char n_zeroes[4]; - char n_offset[4]; - } u; - } u; - - /* The symbol's value. */ - char n_value[4]; - } xcoff32; - struct { - /* The symbol's value. */ - char n_value[8]; - - /* The offset of the symbol from the start of the string table. */ - char n_offset[4]; - } xcoff64; - } u; - - /* The number of the section to which this symbol belongs. */ - char n_scnum[2]; - - /* The type of symbol. (It can be interpreted as an n_lang - and an n_cpu byte, but we don't care about that here.) */ - char n_type[2]; - - /* The class of symbol (a C_* value). */ - char n_sclass[1]; - - /* The number of auxiliary symbols attached to this entry. */ - char n_numaux[1]; -}; - -/* Definitions required by collect2. */ -#define C_EXT 2 - -#define F_SHROBJ 0x2000 -#define F_LOADONLY 0x4000 - -#define N_UNDEF ((short) 0) -#define N_TMASK 060 -#define N_BTSHFT 4 - -#define DT_NON 0 -#define DT_FCN 2 - -/* ------------------------------------------------------------------------- - Local code. - ------------------------------------------------------------------------- */ - -/* An internal representation of an XCOFF symbol-table entry, - which is associated with the API-defined SYMENT type. */ -struct internal_syment -{ - char n_name[9]; - unsigned int n_zeroes; - bfd_vma n_offset; - bfd_vma n_value; - short n_scnum; - unsigned short n_flags; - unsigned short n_type; - unsigned char n_sclass; - unsigned char n_numaux; -}; -typedef struct internal_syment SYMENT; - -/* The internal representation of the API-defined LDFILE type. */ -struct internal_ldfile -{ - /* The file handle for the associated file, or -1 if it hasn't been - opened yet. */ - int fd; - - /* The start of the current XCOFF object, if one has been mapped - into memory. Null otherwise. */ - char *object; - - /* The offset of OBJECT from the start of the containing page. */ - size_t page_offset; - - /* The size of the file pointed to by OBJECT. Valid iff OFFSET - is nonnull. */ - size_t object_size; - - /* The offset of the next member in an archive after OBJECT, - or -1 if this isn't an archive. Valid iff OFFSET is nonnull. */ - off_t next_member; - - /* The parsed version of the XCOFF file header. */ - struct internal_filehdr filehdr; -}; -typedef struct internal_ldfile LDFILE; - -/* The API allows the file header to be directly accessed via this macro. */ -#define HEADER(FILE) ((FILE)->filehdr) - -/* API-defined return codes. SUCCESS must be > 0 and FAILURE must be <= 0. */ -#define SUCCESS 1 -#define FAILURE 0 - -/* API-defined functions. */ -extern LDFILE *ldopen (char *, LDFILE *); -extern char *ldgetname (LDFILE *, SYMENT *); -extern int ldtbread (LDFILE *, long, SYMENT *); -extern int ldclose (LDFILE *); - -#endif - -#endif /* GCC_COLLECT2_AIX_H */ diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/collect2.h b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/collect2.h deleted file mode 100644 index c30c9ef..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/collect2.h +++ /dev/null @@ -1,45 +0,0 @@ -/* Header file for collect/tlink routines. - Copyright (C) 1998-2015 Free Software Foundation, Inc. - -This file is part of GCC. - -GCC is free software; you can redistribute it and/or modify it under -the terms of the GNU General Public License as published by the Free -Software Foundation; either version 3, or (at your option) any later -version. - -GCC is distributed in the hope that it will be useful, but WITHOUT ANY -WARRANTY; without even the implied warranty of MERCHANTABILITY or -FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -for more details. - -You should have received a copy of the GNU General Public License -along with GCC; see the file COPYING3. If not see -. */ - -#ifndef GCC_COLLECT2_H -#define GCC_COLLECT2_H - -extern void do_tlink (char **, char **); - -extern struct pex_obj *collect_execute (const char *, char **, const char *, - const char *, int flags); - -extern int collect_wait (const char *, struct pex_obj *); - -extern void dump_ld_file (const char *, FILE *); - -extern int file_exists (const char *); - -extern const char *ldout; -extern const char *lderrout; -extern const char *c_file_name; -extern struct obstack temporary_obstack; -extern char *temporary_firstobj; -extern bool may_unlink_output_file; - -extern void notice_translated (const char *, ...) ATTRIBUTE_PRINTF_1; -extern void notice (const char *, ...) ATTRIBUTE_PRINTF_1; - -extern bool at_file_supplied; -#endif /* ! GCC_COLLECT2_H */ diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/conditions.h b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/conditions.h deleted file mode 100644 index 2308bfc..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/conditions.h +++ /dev/null @@ -1,122 +0,0 @@ -/* Definitions for condition code handling in final.c and output routines. - Copyright (C) 1987-2015 Free Software Foundation, Inc. - -This file is part of GCC. - -GCC is free software; you can redistribute it and/or modify it under -the terms of the GNU General Public License as published by the Free -Software Foundation; either version 3, or (at your option) any later -version. - -GCC is distributed in the hope that it will be useful, but WITHOUT ANY -WARRANTY; without even the implied warranty of MERCHANTABILITY or -FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -for more details. - -You should have received a copy of the GNU General Public License -along with GCC; see the file COPYING3. If not see -. */ - -#ifndef GCC_CONDITIONS_H -#define GCC_CONDITIONS_H - -/* None of the things in the files exist if we don't use CC0. */ - -#ifdef HAVE_cc0 - -/* The variable cc_status says how to interpret the condition code. - It is set by output routines for an instruction that sets the cc's - and examined by output routines for jump instructions. - - cc_status contains two components named `value1' and `value2' - that record two equivalent expressions for the values that the - condition codes were set from. (Either or both may be null if - there is no useful expression to record.) These fields are - used for eliminating redundant test and compare instructions - in the cases where the condition codes were already set by the - previous instruction. - - cc_status.flags contains flags which say that the condition codes - were set in a nonstandard manner. The output of jump instructions - uses these flags to compensate and produce the standard result - with the nonstandard condition codes. Standard flags are defined here. - The tm.h file can also define other machine-dependent flags. - - cc_status also contains a machine-dependent component `mdep' - whose type, `CC_STATUS_MDEP', may be defined as a macro in the - tm.h file. */ - -#ifndef CC_STATUS_MDEP -#define CC_STATUS_MDEP int -#endif - -#ifndef CC_STATUS_MDEP_INIT -#define CC_STATUS_MDEP_INIT 0 -#endif - -struct CC_STATUS {int flags; rtx value1, value2; CC_STATUS_MDEP mdep;}; - -/* While outputting an insn as assembler code, - this is the status BEFORE that insn. */ -extern CC_STATUS cc_prev_status; - -/* While outputting an insn as assembler code, - this is being altered to the status AFTER that insn. */ -extern CC_STATUS cc_status; - -/* These are the machine-independent flags: */ - -/* Set if the sign of the cc value is inverted: - output a following jump-if-less as a jump-if-greater, etc. */ -#define CC_REVERSED 1 - -/* This bit means that the current setting of the N bit is bogus - and conditional jumps should use the Z bit in its place. - This state obtains when an extraction of a signed single-bit field - or an arithmetic shift right of a byte by 7 bits - is turned into a btst, because btst does not set the N bit. */ -#define CC_NOT_POSITIVE 2 - -/* This bit means that the current setting of the N bit is bogus - and conditional jumps should pretend that the N bit is clear. - Used after extraction of an unsigned bit - or logical shift right of a byte by 7 bits is turned into a btst. - The btst does not alter the N bit, but the result of that shift - or extract is never negative. */ -#define CC_NOT_NEGATIVE 4 - -/* This bit means that the current setting of the overflow flag - is bogus and conditional jumps should pretend there is no overflow. */ -/* ??? Note that for most targets this macro is misnamed as it applies - to the carry flag, not the overflow flag. */ -#define CC_NO_OVERFLOW 010 - -/* This bit means that what ought to be in the Z bit - should be tested as the complement of the N bit. */ -#define CC_Z_IN_NOT_N 020 - -/* This bit means that what ought to be in the Z bit - should be tested as the N bit. */ -#define CC_Z_IN_N 040 - -/* Nonzero if we must invert the sense of the following branch, i.e. - change EQ to NE. This is not safe for IEEE floating point operations! - It is intended for use only when a combination of arithmetic - or logical insns can leave the condition codes set in a fortuitous - (though inverted) state. */ -#define CC_INVERTED 0100 - -/* Nonzero if we must convert signed condition operators to unsigned. - This is only used by machine description files. */ -#define CC_NOT_SIGNED 0200 - -/* This is how to initialize the variable cc_status. - final does this at appropriate moments. */ - -#define CC_STATUS_INIT \ - (cc_status.flags = 0, cc_status.value1 = 0, cc_status.value2 = 0, \ - CC_STATUS_MDEP_INIT) - -#endif - -#endif /* GCC_CONDITIONS_H */ diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/config.h b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/config.h deleted file mode 100644 index aa6dd6b..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/config.h +++ /dev/null @@ -1,10 +0,0 @@ -#ifndef GCC_CONFIG_H -#define GCC_CONFIG_H -#ifdef GENERATOR_FILE -#error config.h is for the host, not build, machine. -#endif -#include "auto-host.h" -#ifdef IN_GCC -# include "ansidecl.h" -#endif -#endif /* GCC_CONFIG_H */ diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/config/avr/avr-arch.h b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/config/avr/avr-arch.h deleted file mode 100644 index dbe9543..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/config/avr/avr-arch.h +++ /dev/null @@ -1,204 +0,0 @@ -/* Definitions of types that are used to store AVR architecture and - device information. - Copyright (C) 2012-2015 Free Software Foundation, Inc. - Contributed by Georg-Johann Lay (avr@gjlay.de) - -This file is part of GCC. - -GCC is free software; you can redistribute it and/or modify -it under the terms of the GNU General Public License as published by -the Free Software Foundation; either version 3, or (at your option) -any later version. - -GCC is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU General Public License for more details. - -You should have received a copy of the GNU General Public License -along with GCC; see the file COPYING3. If not see -. */ - -#ifndef AVR_ARCH_H -#define AVR_ARCH_H - -#define AVR_MMCU_DEFAULT "avr2" - -/* This enum supplies indices into the avr_arch_types[] table below. */ - -enum avr_arch_id -{ - ARCH_UNKNOWN, - ARCH_AVR1, - ARCH_AVR2, - ARCH_AVR25, - ARCH_AVR3, - ARCH_AVR31, - ARCH_AVR35, - ARCH_AVR4, - ARCH_AVR5, - ARCH_AVR51, - ARCH_AVR6, - ARCH_AVRTINY, - ARCH_AVRXMEGA2, - ARCH_AVRXMEGA3, - ARCH_AVRXMEGA4, - ARCH_AVRXMEGA5, - ARCH_AVRXMEGA6, - ARCH_AVRXMEGA7 -}; - - -/* Architecture-specific properties. */ - -typedef struct -{ - /* Assembler only. */ - int asm_only; - - /* Core have 'MUL*' instructions. */ - int have_mul; - - /* Core have 'CALL' and 'JMP' instructions. */ - int have_jmp_call; - - /* Core have 'MOVW' and 'LPM Rx,Z' instructions. */ - int have_movw_lpmx; - - /* Core have 'ELPM' instructions. */ - int have_elpm; - - /* Core have 'ELPM Rx,Z' instructions. */ - int have_elpmx; - - /* Core have 'EICALL' and 'EIJMP' instructions. */ - int have_eijmp_eicall; - - /* This is an XMEGA core. */ - int xmega_p; - - /* This core has the RAMPD special function register - and thus also the RAMPX, RAMPY and RAMPZ registers. */ - int have_rampd; - - /* This is a TINY core. */ - int tiny_p; - - /* Default start of data section address for architecture. */ - int default_data_section_start; - - /* Offset where flash memory is seen in RAM address range or 0. */ - int flash_pm_offset; - - /* Offset between SFR address and RAM address: - SFR-address = RAM-address - sfr_offset */ - int sfr_offset; - - /* Architecture id to built-in define __AVR_ARCH__ (NULL -> no macro) */ - const char *const macro; - - /* Architecture name. */ - const char *const name; -} avr_arch_t; - - -/* Device-specific properties. */ - -typedef struct -{ - /* Device name. */ - const char *const name; - - /* Index in avr_arch_types[]. */ - enum avr_arch_id arch_id; - - /* device specific feature */ - int dev_attribute; - - /* Must lie outside user's namespace. NULL == no macro. */ - const char *const macro; - - /* Start of data section. */ - int data_section_start; - - /* Start of text section. */ - int text_section_start; - - /* Non bit addressable registers mask. */ - unsigned int non_bit_addressable_registers_mask; - - /* Flash size in bytes. */ - int flash_size; -} avr_mcu_t; - -/* AVR device specific features. - -AVR_ISA_RMW - Only few avr devices have Read-Modify-Write (RMW) instructions - (XCH, LAC, LAS and LAT) - -AVR_SHORT_SP - Stack Pointer has only 8 bit width. - The device / multilib has an 8-bit stack pointer (no SPH). - -AVR_ERRATA_SKIP - Some AVR devices have a core erratum when skipping a 2-word instruction. - Skip instructions are: SBRC, SBRS, SBIC, SBIS, CPSE. - Problems will occur with return address is IRQ executes during the - skip sequence. - - A support ticket from Atmel returned the following information: - - Subject: (ATTicket:644469) On AVR skip-bug core Erratum - From: avr@atmel.com Date: 2011-07-27 - (Please keep the subject when replying to this mail) - - This errata exists only in AT90S8515 and ATmega103 devices. - - For information please refer the following respective errata links - http://www.atmel.com/dyn/resources/prod_documents/doc2494.pdf - http://www.atmel.com/dyn/resources/prod_documents/doc1436.pdf - -AVR_ISA_RCALL - Always use RJMP / RCALL and assume JMP / CALL are not available. - This affects multilib selection via specs generation and -mshort-calls. - Even if a device like ATtiny417 from avrxmega3 supports JMP / CALL, we - assume these instructions are not available and we set the built-in - macro __AVR_HAVE_JMP_CALL__ accordingly. This macro is used to - determine a rough estimate of flash size in libgcc, and AVR-LibC uses - this macro to determine vector sizes. */ - -enum avr_device_specific_features -{ - AVR_ISA_NONE, - AVR_ISA_RMW = 0x1, /* device has RMW instructions. */ - AVR_SHORT_SP = 0x2, /* Stack Pointer has 8 bits width. */ - AVR_ERRATA_SKIP = 0x4, /* device has a core erratum. */ - AVR_ISA_LDS = 0x8, /* whether LDS / STS is valid for all data in static - storage. Only useful for reduced Tiny. */ - AVR_ISA_RCALL = 0x10 /* Use RJMP / RCALL even though JMP / CALL - are available (-mshort-calls). */ -}; - -/* Map architecture to its texinfo string. */ - -typedef struct -{ - /* Architecture ID. */ - enum avr_arch_id arch_id; - - /* textinfo source to describe the archtiecture. */ - const char *texinfo; -} avr_arch_info_t; - -/* Preprocessor macros to define depending on MCU type. */ - -extern const avr_arch_t avr_arch_types[]; -extern const avr_arch_t *avr_arch; - -extern const avr_mcu_t avr_mcu_types[]; - -extern void avr_inform_devices (void); -extern void avr_inform_core_architectures (void); - -#endif /* AVR_ARCH_H */ diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/config/avr/avr-protos.h b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/config/avr/avr-protos.h deleted file mode 100644 index aeb2859..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/config/avr/avr-protos.h +++ /dev/null @@ -1,177 +0,0 @@ -/* Prototypes for exported functions defined in avr.c - - Copyright (C) 2000-2015 Free Software Foundation, Inc. - Contributed by Denis Chertykov (chertykov@gmail.com) - - This file is part of GCC. - - GCC is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3, or (at your option) - any later version. - - GCC is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with GCC; see the file COPYING3. If not see - . */ - - -extern int avr_function_arg_regno_p (int r); -extern void avr_cpu_cpp_builtins (struct cpp_reader * pfile); -extern enum reg_class avr_regno_reg_class (int r); -extern void asm_globalize_label (FILE *file, const char *name); -extern void avr_adjust_reg_alloc_order (void); -extern int avr_initial_elimination_offset (int from, int to); -extern int avr_simple_epilogue (void); -extern int avr_hard_regno_rename_ok (unsigned int, unsigned int); -extern rtx avr_return_addr_rtx (int count, rtx tem); -extern void avr_register_target_pragmas (void); -extern void avr_init_expanders (void); - -#ifdef TREE_CODE -extern void avr_asm_output_aligned_decl_common (FILE*, tree, const char*, unsigned HOST_WIDE_INT, unsigned int, bool); -extern void avr_asm_asm_output_aligned_bss (FILE *, tree, const char *, unsigned HOST_WIDE_INT, int, void (*) (FILE *, tree, const char *, unsigned HOST_WIDE_INT, int)); -extern void asm_output_external (FILE *file, tree decl, char *name); -extern int avr_progmem_p (tree decl, tree attributes); - -#ifdef RTX_CODE /* inside TREE_CODE */ -extern void avr_init_cumulative_args (CUMULATIVE_ARGS*, tree, rtx, tree); -#endif /* RTX_CODE inside TREE_CODE */ - -#endif /* TREE_CODE */ - -#ifdef RTX_CODE -extern int avr_hard_regno_call_part_clobbered (unsigned, machine_mode); -extern const char *output_movqi (rtx_insn *insn, rtx operands[], int *l); -extern const char *output_movhi (rtx_insn *insn, rtx operands[], int *l); -extern const char *output_movsisf (rtx_insn *insn, rtx operands[], int *l); -extern const char *avr_out_tstsi (rtx_insn *, rtx*, int*); -extern const char *avr_out_tsthi (rtx_insn *, rtx*, int*); -extern const char *avr_out_tstpsi (rtx_insn *, rtx*, int*); -extern const char *avr_out_compare (rtx_insn *, rtx*, int*); -extern const char *avr_out_compare64 (rtx_insn *, rtx*, int*); -extern const char *ret_cond_branch (rtx x, int len, int reverse); -extern const char *avr_out_movpsi (rtx_insn *, rtx*, int*); -extern const char *avr_out_sign_extend (rtx_insn *, rtx*, int*); - -extern const char *ashlqi3_out (rtx_insn *insn, rtx operands[], int *len); -extern const char *ashlhi3_out (rtx_insn *insn, rtx operands[], int *len); -extern const char *ashlsi3_out (rtx_insn *insn, rtx operands[], int *len); - -extern const char *ashrqi3_out (rtx_insn *insn, rtx operands[], int *len); -extern const char *ashrhi3_out (rtx_insn *insn, rtx operands[], int *len); -extern const char *ashrsi3_out (rtx_insn *insn, rtx operands[], int *len); - -extern const char *lshrqi3_out (rtx_insn *insn, rtx operands[], int *len); -extern const char *lshrhi3_out (rtx_insn *insn, rtx operands[], int *len); -extern const char *lshrsi3_out (rtx_insn *insn, rtx operands[], int *len); - -extern const char *avr_out_ashlpsi3 (rtx_insn *, rtx*, int*); -extern const char *avr_out_ashrpsi3 (rtx_insn *, rtx*, int*); -extern const char *avr_out_lshrpsi3 (rtx_insn *, rtx*, int*); - -extern bool avr_rotate_bytes (rtx operands[]); - -extern const char* avr_out_fract (rtx_insn *, rtx[], bool, int*); -extern rtx avr_to_int_mode (rtx); - -extern void avr_expand_prologue (void); -extern void avr_expand_epilogue (bool); -extern bool avr_emit_movmemhi (rtx*); -extern int avr_epilogue_uses (int regno); -extern int avr_starting_frame_offset (void); - -extern void avr_output_addr_vec_elt (FILE *stream, int value); -extern const char *avr_out_sbxx_branch (rtx_insn *insn, rtx operands[]); -extern const char* avr_out_bitop (rtx, rtx*, int*); -extern const char* avr_out_plus (rtx, rtx*, int* =NULL, int* =NULL, bool =true); -extern const char* avr_out_round (rtx_insn *, rtx*, int* =NULL); -extern const char* avr_out_addto_sp (rtx*, int*); -extern const char* avr_out_xload (rtx_insn *, rtx*, int*); -extern const char* avr_out_movmem (rtx_insn *, rtx*, int*); -extern const char* avr_out_insert_bits (rtx*, int*); -extern bool avr_popcount_each_byte (rtx, int, int); -extern bool avr_has_nibble_0xf (rtx); - -extern int extra_constraint_Q (rtx x); -extern int avr_adjust_insn_length (rtx_insn *insn, int len); -extern const char* output_reload_inhi (rtx*, rtx, int*); -extern const char* output_reload_insisf (rtx*, rtx, int*); -extern const char* avr_out_reload_inpsi (rtx*, rtx, int*); -extern const char* avr_out_lpm (rtx_insn *, rtx*, int*); -extern void avr_notice_update_cc (rtx body, rtx_insn *insn); -extern int reg_unused_after (rtx_insn *insn, rtx reg); -extern int _reg_unused_after (rtx_insn *insn, rtx reg); -extern int avr_jump_mode (rtx x, rtx_insn *insn); -extern int test_hard_reg_class (enum reg_class rclass, rtx x); -extern int jump_over_one_insn_p (rtx_insn *insn, rtx dest); - -extern int avr_hard_regno_mode_ok (int regno, machine_mode mode); -extern void avr_final_prescan_insn (rtx_insn *insn, rtx *operand, - int num_operands); -extern int avr_simplify_comparison_p (machine_mode mode, - RTX_CODE op, rtx x); -extern RTX_CODE avr_normalize_condition (RTX_CODE condition); -extern void out_shift_with_cnt (const char *templ, rtx_insn *insn, - rtx operands[], int *len, int t_len); -extern enum reg_class avr_mode_code_base_reg_class (machine_mode, addr_space_t, RTX_CODE, RTX_CODE); -extern bool avr_regno_mode_code_ok_for_base_p (int, machine_mode, addr_space_t, RTX_CODE, RTX_CODE); -extern rtx avr_incoming_return_addr_rtx (void); -extern rtx avr_legitimize_reload_address (rtx*, machine_mode, int, int, int, int, rtx (*)(rtx,int)); -extern bool avr_mem_flash_p (rtx); -extern bool avr_mem_memx_p (rtx); -extern bool avr_load_libgcc_p (rtx); -extern bool avr_xload_libgcc_p (machine_mode); -extern rtx avr_eval_addr_attrib (rtx x); - -static inline unsigned -regmask (machine_mode mode, unsigned regno) -{ - return ((1u << GET_MODE_SIZE (mode)) - 1) << regno; -} - -extern void avr_fix_inputs (rtx*, unsigned, unsigned); -extern bool avr_emit3_fix_outputs (rtx (*)(rtx,rtx,rtx), rtx*, unsigned, unsigned); - -extern rtx lpm_reg_rtx; -extern rtx lpm_addr_reg_rtx; -extern rtx tmp_reg_rtx; -extern rtx zero_reg_rtx; -extern rtx all_regs_rtx[32]; -extern rtx rampz_rtx; - -#endif /* RTX_CODE */ - -#ifdef REAL_VALUE_TYPE -extern void asm_output_float (FILE *file, REAL_VALUE_TYPE n); -#endif - -extern bool avr_have_dimode; - -/* From avr-log.c */ - -#define avr_dump(...) avr_vdump (NULL, __FUNCTION__, __VA_ARGS__) -#define avr_edump(...) avr_vdump (stderr, __FUNCTION__, __VA_ARGS__) -#define avr_fdump(FIL, ...) avr_vdump (FIL, __FUNCTION__, __VA_ARGS__) - -extern int avr_vdump (FILE*, const char*, ...); -extern void avr_log_set_avr_log (void); - -typedef struct -{ - unsigned address_cost :1; - unsigned builtin :1; - unsigned constraints :1; - unsigned legitimate_address_p :1; - unsigned legitimize_address :1; - unsigned legitimize_reload_address :1; - unsigned progmem :1; - unsigned rtx_costs :1; -} avr_log_t; - -extern avr_log_t avr_log; -extern unsigned long avr_non_bit_addressable_registers_mask; diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/config/avr/avr-stdint.h b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/config/avr/avr-stdint.h deleted file mode 100644 index 910ee9e..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/config/avr/avr-stdint.h +++ /dev/null @@ -1,66 +0,0 @@ -/* Definitions for types on systems using newlib. - Copyright (C) 2012-2015 Free Software Foundation, Inc. - -This file is part of GCC. - -GCC is free software; you can redistribute it and/or modify -it under the terms of the GNU General Public License as published by -the Free Software Foundation; either version 3, or (at your option) -any later version. - -GCC is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU General Public License for more details. - -You should have received a copy of the GNU General Public License -along with GCC; see the file COPYING3. If not see -. */ - -/* - The intention of this file is to supply definitions that work with - avr-gcc's -mint8 that sets int to an 8-bit type. - - This file is intended to yield the same results as newlib-stdint.h, - but there are some differences to newlib-stdint.h: - - - AVR is an 8-bit architecture that cannot access 16-bit values - atomically, this SIG_ATOMIC_TYPE is "char". - - - For the same reason, [u]int_fast8_t is defined as 8-bit type. - -*/ - -#define SIG_ATOMIC_TYPE "char" - -#define INT8_TYPE "signed char" -#define INT16_TYPE (INT_TYPE_SIZE == 16 ? "int" : "long int") -#define INT32_TYPE (INT_TYPE_SIZE == 16 ? "long int" : "long long int") -#define INT64_TYPE (INT_TYPE_SIZE == 16 ? "long long int" : 0) -#define UINT8_TYPE "unsigned char" -#define UINT16_TYPE (INT_TYPE_SIZE == 16 ? "unsigned int" : "long unsigned int") -#define UINT32_TYPE (INT_TYPE_SIZE == 16 ? "long unsigned int" : "long long unsigned int") -#define UINT64_TYPE (INT_TYPE_SIZE == 16 ? "long long unsigned int" : 0) - -#define INT_LEAST8_TYPE INT8_TYPE -#define INT_LEAST16_TYPE INT16_TYPE -#define INT_LEAST32_TYPE INT32_TYPE -#define INT_LEAST64_TYPE INT64_TYPE -#define UINT_LEAST8_TYPE UINT8_TYPE -#define UINT_LEAST16_TYPE UINT16_TYPE -#define UINT_LEAST32_TYPE UINT32_TYPE -#define UINT_LEAST64_TYPE UINT64_TYPE - -#define INT_FAST8_TYPE INT8_TYPE -#define INT_FAST16_TYPE (INT_TYPE_SIZE == 16 ? "int" : INT16_TYPE) -#define INT_FAST32_TYPE INT32_TYPE -#define INT_FAST64_TYPE INT64_TYPE -#define UINT_FAST8_TYPE UINT8_TYPE -#define UINT_FAST16_TYPE (INT_TYPE_SIZE == 16 ? "unsigned int" : UINT16_TYPE) -#define UINT_FAST32_TYPE UINT32_TYPE -#define UINT_FAST64_TYPE UINT64_TYPE - -#define INTPTR_TYPE PTRDIFF_TYPE -#ifndef UINTPTR_TYPE -#define UINTPTR_TYPE SIZE_TYPE -#endif diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/config/avr/avr.h b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/config/avr/avr.h deleted file mode 100644 index 6d48a6d..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/config/avr/avr.h +++ /dev/null @@ -1,602 +0,0 @@ -/* Definitions of target machine for GNU compiler, - for ATMEL AVR at90s8515, ATmega103/103L, ATmega603/603L microcontrollers. - Copyright (C) 1998-2015 Free Software Foundation, Inc. - Contributed by Denis Chertykov (chertykov@gmail.com) - -This file is part of GCC. - -GCC is free software; you can redistribute it and/or modify -it under the terms of the GNU General Public License as published by -the Free Software Foundation; either version 3, or (at your option) -any later version. - -GCC is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU General Public License for more details. - -You should have received a copy of the GNU General Public License -along with GCC; see the file COPYING3. If not see -. */ - -typedef struct -{ - /* Id of the address space as used in c_register_addr_space */ - unsigned char id; - - /* Flavour of memory: 0 = RAM, 1 = Flash */ - int memory_class; - - /* Width of pointer (in bytes) */ - int pointer_size; - - /* Name of the address space as visible to the user */ - const char *name; - - /* Segment (i.e. 64k memory chunk) number. */ - int segment; - - /* Section prefix, e.g. ".progmem1.data" */ - const char *section_name; -} avr_addrspace_t; - -extern const avr_addrspace_t avr_addrspace[]; - -/* Known address spaces */ - -enum - { - ADDR_SPACE_RAM, /* ADDR_SPACE_GENERIC */ - ADDR_SPACE_FLASH, - ADDR_SPACE_FLASH1, - ADDR_SPACE_FLASH2, - ADDR_SPACE_FLASH3, - ADDR_SPACE_FLASH4, - ADDR_SPACE_FLASH5, - ADDR_SPACE_MEMX, - /* Sentinel */ - ADDR_SPACE_COUNT - }; - -#define TARGET_CPU_CPP_BUILTINS() avr_cpu_cpp_builtins (pfile) - -#define AVR_SHORT_CALLS (TARGET_SHORT_CALLS \ - && avr_arch == &avr_arch_types[ARCH_AVRXMEGA3]) -#define AVR_HAVE_JMP_CALL (avr_arch->have_jmp_call && ! AVR_SHORT_CALLS) -#define AVR_HAVE_MUL (avr_arch->have_mul) -#define AVR_HAVE_MOVW (avr_arch->have_movw_lpmx) -#define AVR_HAVE_LPM (!AVR_TINY) -#define AVR_HAVE_LPMX (avr_arch->have_movw_lpmx) -#define AVR_HAVE_ELPM (avr_arch->have_elpm) -#define AVR_HAVE_ELPMX (avr_arch->have_elpmx) -#define AVR_HAVE_RAMPD (avr_arch->have_rampd) -#define AVR_HAVE_RAMPX (avr_arch->have_rampd) -#define AVR_HAVE_RAMPY (avr_arch->have_rampd) -#define AVR_HAVE_RAMPZ (avr_arch->have_elpm \ - || avr_arch->have_rampd) -#define AVR_HAVE_EIJMP_EICALL (avr_arch->have_eijmp_eicall) - -/* Handling of 8-bit SP versus 16-bit SP is as follows: - -FIXME: DRIVER_SELF_SPECS has changed. - -msp8 is used internally to select the right multilib for targets with - 8-bit SP. -msp8 is set automatically by DRIVER_SELF_SPECS for devices - with 8-bit SP or by multilib generation machinery. If a frame pointer is - needed and SP is only 8 bits wide, SP is zero-extended to get FP. - - TARGET_TINY_STACK is triggered by -mtiny-stack which is a user option. - This option has no effect on multilib selection. It serves to save some - bytes on 16-bit SP devices by only changing SP_L and leaving SP_H alone. - - These two properties are reflected by built-in macros __AVR_SP8__ resp. - __AVR_HAVE_8BIT_SP__ and __AVR_HAVE_16BIT_SP__. During multilib generation - there is always __AVR_SP8__ == __AVR_HAVE_8BIT_SP__. */ - -#define AVR_HAVE_8BIT_SP \ - (TARGET_TINY_STACK || avr_sp8) - -#define AVR_HAVE_SPH (!avr_sp8) - -#define AVR_2_BYTE_PC (!AVR_HAVE_EIJMP_EICALL) -#define AVR_3_BYTE_PC (AVR_HAVE_EIJMP_EICALL) - -#define AVR_XMEGA (avr_arch->xmega_p) -#define AVR_TINY (avr_arch->tiny_p) - -#define BITS_BIG_ENDIAN 0 -#define BYTES_BIG_ENDIAN 0 -#define WORDS_BIG_ENDIAN 0 - -#ifdef IN_LIBGCC2 -/* This is to get correct SI and DI modes in libgcc2.c (32 and 64 bits). */ -#define UNITS_PER_WORD 4 -#else -/* Width of a word, in units (bytes). */ -#define UNITS_PER_WORD 1 -#endif - -#define POINTER_SIZE 16 - - -/* Maximum sized of reasonable data type - DImode or Dfmode ... */ -#define MAX_FIXED_MODE_SIZE 32 - -#define PARM_BOUNDARY 8 - -#define FUNCTION_BOUNDARY 8 - -#define EMPTY_FIELD_BOUNDARY 8 - -/* No data type wants to be aligned rounder than this. */ -#define BIGGEST_ALIGNMENT 8 - -#define TARGET_VTABLE_ENTRY_ALIGN 8 - -#define STRICT_ALIGNMENT 0 - -#define INT_TYPE_SIZE (TARGET_INT8 ? 8 : 16) -#define SHORT_TYPE_SIZE (INT_TYPE_SIZE == 8 ? INT_TYPE_SIZE : 16) -#define LONG_TYPE_SIZE (INT_TYPE_SIZE == 8 ? 16 : 32) -#define LONG_LONG_TYPE_SIZE (INT_TYPE_SIZE == 8 ? 32 : 64) -#define FLOAT_TYPE_SIZE 32 -#define DOUBLE_TYPE_SIZE 32 -#define LONG_DOUBLE_TYPE_SIZE 32 -#define LONG_LONG_ACCUM_TYPE_SIZE 64 - -#define DEFAULT_SIGNED_CHAR 1 - -#define SIZE_TYPE (INT_TYPE_SIZE == 8 ? "long unsigned int" : "unsigned int") -#define PTRDIFF_TYPE (INT_TYPE_SIZE == 8 ? "long int" :"int") - -#define WCHAR_TYPE "int" -#define WINT_TYPE "int" -#define WCHAR_TYPE_SIZE 16 - -#define FIRST_PSEUDO_REGISTER 36 - -#define FIXED_REGISTERS {\ - 1,1,/* r0 r1 */\ - 0,0,/* r2 r3 */\ - 0,0,/* r4 r5 */\ - 0,0,/* r6 r7 */\ - 0,0,/* r8 r9 */\ - 0,0,/* r10 r11 */\ - 0,0,/* r12 r13 */\ - 0,0,/* r14 r15 */\ - 0,0,/* r16 r17 */\ - 0,0,/* r18 r19 */\ - 0,0,/* r20 r21 */\ - 0,0,/* r22 r23 */\ - 0,0,/* r24 r25 */\ - 0,0,/* r26 r27 */\ - 0,0,/* r28 r29 */\ - 0,0,/* r30 r31 */\ - 1,1,/* STACK */\ - 1,1 /* arg pointer */ } - -#define CALL_USED_REGISTERS { \ - 1,1,/* r0 r1 */ \ - 0,0,/* r2 r3 */ \ - 0,0,/* r4 r5 */ \ - 0,0,/* r6 r7 */ \ - 0,0,/* r8 r9 */ \ - 0,0,/* r10 r11 */ \ - 0,0,/* r12 r13 */ \ - 0,0,/* r14 r15 */ \ - 0,0,/* r16 r17 */ \ - 1,1,/* r18 r19 */ \ - 1,1,/* r20 r21 */ \ - 1,1,/* r22 r23 */ \ - 1,1,/* r24 r25 */ \ - 1,1,/* r26 r27 */ \ - 0,0,/* r28 r29 */ \ - 1,1,/* r30 r31 */ \ - 1,1,/* STACK */ \ - 1,1 /* arg pointer */ } - -#define REG_ALLOC_ORDER { \ - 24,25, \ - 18,19, \ - 20,21, \ - 22,23, \ - 30,31, \ - 26,27, \ - 28,29, \ - 17,16,15,14,13,12,11,10,9,8,7,6,5,4,3,2, \ - 0,1, \ - 32,33,34,35 \ - } - -#define ADJUST_REG_ALLOC_ORDER avr_adjust_reg_alloc_order() - - -#define HARD_REGNO_NREGS(REGNO, MODE) \ - ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD) - -#define HARD_REGNO_MODE_OK(REGNO, MODE) avr_hard_regno_mode_ok(REGNO, MODE) - -#define MODES_TIEABLE_P(MODE1, MODE2) 1 - -enum reg_class { - NO_REGS, - R0_REG, /* r0 */ - POINTER_X_REGS, /* r26 - r27 */ - POINTER_Y_REGS, /* r28 - r29 */ - POINTER_Z_REGS, /* r30 - r31 */ - STACK_REG, /* STACK */ - BASE_POINTER_REGS, /* r28 - r31 */ - POINTER_REGS, /* r26 - r31 */ - ADDW_REGS, /* r24 - r31 */ - SIMPLE_LD_REGS, /* r16 - r23 */ - LD_REGS, /* r16 - r31 */ - NO_LD_REGS, /* r0 - r15 */ - GENERAL_REGS, /* r0 - r31 */ - ALL_REGS, LIM_REG_CLASSES -}; - - -#define N_REG_CLASSES (int)LIM_REG_CLASSES - -#define REG_CLASS_NAMES { \ - "NO_REGS", \ - "R0_REG", /* r0 */ \ - "POINTER_X_REGS", /* r26 - r27 */ \ - "POINTER_Y_REGS", /* r28 - r29 */ \ - "POINTER_Z_REGS", /* r30 - r31 */ \ - "STACK_REG", /* STACK */ \ - "BASE_POINTER_REGS", /* r28 - r31 */ \ - "POINTER_REGS", /* r26 - r31 */ \ - "ADDW_REGS", /* r24 - r31 */ \ - "SIMPLE_LD_REGS", /* r16 - r23 */ \ - "LD_REGS", /* r16 - r31 */ \ - "NO_LD_REGS", /* r0 - r15 */ \ - "GENERAL_REGS", /* r0 - r31 */ \ - "ALL_REGS" } - -#define REG_CLASS_CONTENTS { \ - {0x00000000,0x00000000}, /* NO_REGS */ \ - {0x00000001,0x00000000}, /* R0_REG */ \ - {3u << REG_X,0x00000000}, /* POINTER_X_REGS, r26 - r27 */ \ - {3u << REG_Y,0x00000000}, /* POINTER_Y_REGS, r28 - r29 */ \ - {3u << REG_Z,0x00000000}, /* POINTER_Z_REGS, r30 - r31 */ \ - {0x00000000,0x00000003}, /* STACK_REG, STACK */ \ - {(3u << REG_Y) | (3u << REG_Z), \ - 0x00000000}, /* BASE_POINTER_REGS, r28 - r31 */ \ - {(3u << REG_X) | (3u << REG_Y) | (3u << REG_Z), \ - 0x00000000}, /* POINTER_REGS, r26 - r31 */ \ - {(3u << REG_X) | (3u << REG_Y) | (3u << REG_Z) | (3u << REG_W), \ - 0x00000000}, /* ADDW_REGS, r24 - r31 */ \ - {0x00ff0000,0x00000000}, /* SIMPLE_LD_REGS r16 - r23 */ \ - {(3u << REG_X)|(3u << REG_Y)|(3u << REG_Z)|(3u << REG_W)|(0xffu << 16),\ - 0x00000000}, /* LD_REGS, r16 - r31 */ \ - {0x0000ffff,0x00000000}, /* NO_LD_REGS r0 - r15 */ \ - {0xffffffff,0x00000000}, /* GENERAL_REGS, r0 - r31 */ \ - {0xffffffff,0x00000003} /* ALL_REGS */ \ -} - -#define REGNO_REG_CLASS(R) avr_regno_reg_class(R) - -#define MODE_CODE_BASE_REG_CLASS(mode, as, outer_code, index_code) \ - avr_mode_code_base_reg_class (mode, as, outer_code, index_code) - -#define INDEX_REG_CLASS NO_REGS - -#define REGNO_MODE_CODE_OK_FOR_BASE_P(num, mode, as, outer_code, index_code) \ - avr_regno_mode_code_ok_for_base_p (num, mode, as, outer_code, index_code) - -#define REGNO_OK_FOR_INDEX_P(NUM) 0 - -#define HARD_REGNO_CALL_PART_CLOBBERED(REGNO, MODE) \ - avr_hard_regno_call_part_clobbered (REGNO, MODE) - -#define TARGET_SMALL_REGISTER_CLASSES_FOR_MODE_P hook_bool_mode_true - -#define STACK_PUSH_CODE POST_DEC - -#define STACK_GROWS_DOWNWARD - -#define STARTING_FRAME_OFFSET avr_starting_frame_offset() - -#define STACK_POINTER_OFFSET 1 - -#define FIRST_PARM_OFFSET(FUNDECL) 0 - -#define STACK_BOUNDARY 8 - -#define STACK_POINTER_REGNUM 32 - -#define FRAME_POINTER_REGNUM REG_Y - -#define ARG_POINTER_REGNUM 34 - -#define STATIC_CHAIN_REGNUM ((AVR_TINY) ? 18 :2) - -#define ELIMINABLE_REGS { \ - { ARG_POINTER_REGNUM, STACK_POINTER_REGNUM }, \ - { ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM }, \ - { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM }, \ - { FRAME_POINTER_REGNUM + 1, STACK_POINTER_REGNUM + 1 } } - -#define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \ - OFFSET = avr_initial_elimination_offset (FROM, TO) - -#define RETURN_ADDR_RTX(count, tem) avr_return_addr_rtx (count, tem) - -/* Don't use Push rounding. expr.c: emit_single_push_insn is broken - for POST_DEC targets (PR27386). */ -/*#define PUSH_ROUNDING(NPUSHED) (NPUSHED)*/ - -typedef struct avr_args -{ - /* # Registers available for passing */ - int nregs; - - /* Next available register number */ - int regno; -} CUMULATIVE_ARGS; - -#define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) \ - avr_init_cumulative_args (&(CUM), FNTYPE, LIBNAME, FNDECL) - -#define FUNCTION_ARG_REGNO_P(r) avr_function_arg_regno_p(r) - -#define DEFAULT_PCC_STRUCT_RETURN 0 - -#define EPILOGUE_USES(REGNO) avr_epilogue_uses(REGNO) - -#define HAVE_POST_INCREMENT 1 -#define HAVE_PRE_DECREMENT 1 - -#define MAX_REGS_PER_ADDRESS 1 - -#define LEGITIMIZE_RELOAD_ADDRESS(X,MODE,OPNUM,TYPE,IND_L,WIN) \ - do { \ - rtx new_x = avr_legitimize_reload_address (&(X), MODE, OPNUM, TYPE, \ - ADDR_TYPE (TYPE), \ - IND_L, make_memloc); \ - if (new_x) \ - { \ - X = new_x; \ - goto WIN; \ - } \ - } while (0) - -#define BRANCH_COST(speed_p, predictable_p) avr_branch_cost - -#define SLOW_BYTE_ACCESS 0 - -#define NO_FUNCTION_CSE - -#define REGISTER_TARGET_PRAGMAS() \ - do { \ - avr_register_target_pragmas(); \ - } while (0) - -#define TEXT_SECTION_ASM_OP "\t.text" - -#define DATA_SECTION_ASM_OP "\t.data" - -#define BSS_SECTION_ASM_OP "\t.section .bss" - -/* Define the pseudo-ops used to switch to the .ctors and .dtors sections. - There are no shared libraries on this target, and these sections are - placed in the read-only program memory, so they are not writable. */ - -#undef CTORS_SECTION_ASM_OP -#define CTORS_SECTION_ASM_OP "\t.section .ctors,\"a\",@progbits" - -#undef DTORS_SECTION_ASM_OP -#define DTORS_SECTION_ASM_OP "\t.section .dtors,\"a\",@progbits" - -#define TARGET_ASM_CONSTRUCTOR avr_asm_out_ctor - -#define TARGET_ASM_DESTRUCTOR avr_asm_out_dtor - -#define SUPPORTS_INIT_PRIORITY 0 - -#define JUMP_TABLES_IN_TEXT_SECTION 0 - -#define ASM_COMMENT_START " ; " - -#define ASM_APP_ON "/* #APP */\n" - -#define ASM_APP_OFF "/* #NOAPP */\n" - -#define IS_ASM_LOGICAL_LINE_SEPARATOR(C, STR) ((C) == '\n' || ((C) == '$')) - -#define ASM_OUTPUT_ALIGNED_DECL_COMMON(STREAM, DECL, NAME, SIZE, ALIGN) \ - avr_asm_output_aligned_decl_common (STREAM, DECL, NAME, SIZE, ALIGN, false) - -#define ASM_OUTPUT_ALIGNED_BSS(FILE, DECL, NAME, SIZE, ALIGN) \ - avr_asm_asm_output_aligned_bss (FILE, DECL, NAME, SIZE, ALIGN, \ - asm_output_aligned_bss) - -#define ASM_OUTPUT_ALIGNED_DECL_LOCAL(STREAM, DECL, NAME, SIZE, ALIGN) \ - avr_asm_output_aligned_decl_common (STREAM, DECL, NAME, SIZE, ALIGN, true) - -/* Globalizing directive for a label. */ -#define GLOBAL_ASM_OP ".global\t" - -#define SUPPORTS_WEAK 1 - -#define HAS_INIT_SECTION 1 - -#define REGISTER_NAMES { \ - "r0","r1","r2","r3","r4","r5","r6","r7", \ - "r8","r9","r10","r11","r12","r13","r14","r15", \ - "r16","r17","r18","r19","r20","r21","r22","r23", \ - "r24","r25","r26","r27","r28","r29","r30","r31", \ - "__SP_L__","__SP_H__","argL","argH"} - -#define FINAL_PRESCAN_INSN(insn, operand, nop) \ - avr_final_prescan_insn (insn, operand,nop) - -#define ASM_OUTPUT_REG_PUSH(STREAM, REGNO) \ -{ \ - gcc_assert (REGNO < 32); \ - fprintf (STREAM, "\tpush\tr%d", REGNO); \ -} - -#define ASM_OUTPUT_REG_POP(STREAM, REGNO) \ -{ \ - gcc_assert (REGNO < 32); \ - fprintf (STREAM, "\tpop\tr%d", REGNO); \ -} - -#define ASM_OUTPUT_ADDR_VEC_ELT(STREAM, VALUE) \ - avr_output_addr_vec_elt (STREAM, VALUE) - -#define ASM_OUTPUT_ALIGN(STREAM, POWER) \ - do { \ - if ((POWER) > 0) \ - fprintf (STREAM, "\t.p2align\t%d\n", POWER); \ - } while (0) - -#define CASE_VECTOR_MODE HImode - -#undef WORD_REGISTER_OPERATIONS - -/* Can move only a single byte from memory to reg in a - single instruction. */ - -#define MOVE_MAX 1 - -/* Allow upto two bytes moves to occur using by_pieces - infrastructure */ - -#define MOVE_MAX_PIECES 2 - -/* Set MOVE_RATIO to 3 to allow memory moves upto 4 bytes to happen - by pieces when optimizing for speed, like it did when MOVE_MAX_PIECES - was 4. When optimizing for size, allow memory moves upto 2 bytes. - Also see avr_use_by_pieces_infrastructure_p. */ - -#define MOVE_RATIO(speed) ((speed) ? 3 : 2) - -#define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1 - -#define Pmode HImode - -#define FUNCTION_MODE HImode - -#define DOLLARS_IN_IDENTIFIERS 0 - -#define TRAMPOLINE_SIZE 4 - -/* Store in cc_status the expressions - that the condition codes will describe - after execution of an instruction whose pattern is EXP. - Do not alter them if the instruction would not alter the cc's. */ - -#define NOTICE_UPDATE_CC(EXP, INSN) avr_notice_update_cc (EXP, INSN) - -/* The add insns don't set overflow in a usable way. */ -#define CC_OVERFLOW_UNUSABLE 01000 -/* The mov,and,or,xor insns don't set carry. That's ok though as the - Z bit is all we need when doing unsigned comparisons on the result of - these insns (since they're always with 0). However, conditions.h has - CC_NO_OVERFLOW defined for this purpose. Rename it to something more - understandable. */ -#define CC_NO_CARRY CC_NO_OVERFLOW - - -/* Output assembler code to FILE to increment profiler label # LABELNO - for profiling a function entry. */ - -#define FUNCTION_PROFILER(FILE, LABELNO) \ - fprintf (FILE, "/* profiler %d */", (LABELNO)) - -#define ADJUST_INSN_LENGTH(INSN, LENGTH) \ - (LENGTH = avr_adjust_insn_length (INSN, LENGTH)) - -extern const char *avr_devicespecs_file (int, const char**); - -#define EXTRA_SPEC_FUNCTIONS \ - { "device-specs-file", avr_devicespecs_file }, - -/* Driver self specs has lmited functionality w.r.t. '%s' for dynamic specs. - Apply '%s' to a static string to inflate the file (directory) name which - is used to diagnose problems with reading the specs file. */ - -#undef DRIVER_SELF_SPECS -#define DRIVER_SELF_SPECS \ - " %:device-specs-file(device-specs%s %{mmcu=*:%*})" - -/* No libstdc++ for now. Empty string doesn't work. */ -#define LIBSTDCXX "gcc" - -/* This is the default without any -mmcu=* option. */ -#define MULTILIB_DEFAULTS { "mmcu=" AVR_MMCU_DEFAULT } - -#define TEST_HARD_REG_CLASS(CLASS, REGNO) \ - TEST_HARD_REG_BIT (reg_class_contents[ (int) (CLASS)], REGNO) - -#define CR_TAB "\n\t" - -#define DWARF2_ADDR_SIZE 4 - -#define INCOMING_RETURN_ADDR_RTX avr_incoming_return_addr_rtx () -#define INCOMING_FRAME_SP_OFFSET (AVR_3_BYTE_PC ? 3 : 2) - -/* The caller's stack pointer value immediately before the call - is one byte below the first argument. */ -#define ARG_POINTER_CFA_OFFSET(FNDECL) -1 - -#define HARD_REGNO_RENAME_OK(OLD_REG, NEW_REG) \ - avr_hard_regno_rename_ok (OLD_REG, NEW_REG) - -/* A C structure for machine-specific, per-function data. - This is added to the cfun structure. */ -struct GTY(()) machine_function -{ - /* 'true' - if current function is a naked function. */ - int is_naked; - - /* 'true' - if current function is an interrupt function - as specified by the "interrupt" attribute. */ - int is_interrupt; - - /* 'true' - if current function is a signal function - as specified by the "signal" attribute. */ - int is_signal; - - /* 'true' - if current function is an nmi function - as specified by the "nmi" attribute. */ - int is_nmi; - - /* 'true' - if current function is a 'task' function - as specified by the "OS_task" attribute. */ - int is_OS_task; - - /* 'true' - if current function is a 'main' function - as specified by the "OS_main" attribute. */ - int is_OS_main; - - /* Current function stack size. */ - int stack_usage; - - /* 'true' if a callee might be tail called */ - int sibcall_fails; - - /* 'true' if the above is_foo predicates are sanity-checked to avoid - multiple diagnose for the same function. */ - int attributes_checked_p; -}; - -/* AVR does not round pushes, but the existence of this macro is - required in order for pushes to be generated. */ -#define PUSH_ROUNDING(X) (X) - -/* Define prototype here to avoid build warning. Some files using - ACCUMULATE_OUTGOING_ARGS (directly or indirectly) include - tm.h but not tm_p.h. */ -extern int avr_accumulate_outgoing_args (void); -#define ACCUMULATE_OUTGOING_ARGS avr_accumulate_outgoing_args() - -#define INIT_EXPANDERS avr_init_expanders() - -/* Flags used for io and address attributes. */ -#define SYMBOL_FLAG_IO_LOW (SYMBOL_FLAG_MACH_DEP << 4) -#define SYMBOL_FLAG_IO (SYMBOL_FLAG_MACH_DEP << 5) -#define SYMBOL_FLAG_ADDRESS (SYMBOL_FLAG_MACH_DEP << 6) diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/config/avr/avrlibc.h b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/config/avr/avrlibc.h deleted file mode 100644 index 59e6485..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/config/avr/avrlibc.h +++ /dev/null @@ -1,40 +0,0 @@ -/* Definitions of target machine for the GNU compiler collection - for Atmel AVR micro controller if configured for AVR-Libc. - Copyright (C) 2012-2015 Free Software Foundation, Inc. - Contributed by Georg-Johann Lay (avr@gjlay.de) - -This file is part of GCC. - -GCC is free software; you can redistribute it and/or modify -it under the terms of the GNU General Public License as published by -the Free Software Foundation; either version 3, or (at your option) -any later version. - -GCC is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU General Public License for more details. - -You should have received a copy of the GNU General Public License -along with GCC; see the file COPYING3. If not see -. */ - -#undef LIB_SPEC -#define LIB_SPEC \ - "%{!mmcu=avr1:-lc} %(avrlibc_devicelib)" - -// AVR-Libc implements functions from libgcc.a in libm.a, see PR54461. -// For a list of functions which are provided by libm.a and are -// omitted from libgcc.a see libgcc's t-avrlibc. - -#undef LIBGCC_SPEC -#define LIBGCC_SPEC \ - "%{!mmcu=avr1:-lgcc -lm}" - -#undef STARTFILE_SPEC -#define STARTFILE_SPEC \ - " %(avrlibc_startfile) " - -#undef LINK_GCC_C_SEQUENCE_SPEC -#define LINK_GCC_C_SEQUENCE_SPEC \ - "--start-group %G %L --end-group" diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/config/avr/elf.h b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/config/avr/elf.h deleted file mode 100644 index 56fa0b2..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/config/avr/elf.h +++ /dev/null @@ -1,41 +0,0 @@ -/* Copyright (C) 2011-2015 Free Software Foundation, Inc. - Contributed by Georg-Johann Lay (avr@gjlay.de) - - This file is part of GCC. - - GCC is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3, or (at your option) - any later version. - - GCC is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with GCC; see the file COPYING3. If not see - . */ - - -/* Overriding some definitions from elfos.h for AVR. */ - -#undef PCC_BITFIELD_TYPE_MATTERS - -#undef PREFERRED_DEBUGGING_TYPE -#define PREFERRED_DEBUGGING_TYPE DBX_DEBUG - -#undef MAX_OFILE_ALIGNMENT -#define MAX_OFILE_ALIGNMENT (32768 * 8) - -#undef STRING_LIMIT -#define STRING_LIMIT ((unsigned) 64) - -/* Output alignment 2**1 for jump tables. */ -#undef ASM_OUTPUT_BEFORE_CASE_LABEL -#define ASM_OUTPUT_BEFORE_CASE_LABEL(FILE, PREFIX, NUM, TABLE) \ - ASM_OUTPUT_ALIGN (FILE, 1); - -/* Be conservative in crtstuff.c. */ -#undef INIT_SECTION_ASM_OP -#undef FINI_SECTION_ASM_OP diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/config/avr/specs.h b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/config/avr/specs.h deleted file mode 100644 index c93f84e..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/config/avr/specs.h +++ /dev/null @@ -1,80 +0,0 @@ -/* Specs definitions for Atmel AVR back end. - - Copyright (C) 2012-2015 Free Software Foundation, Inc. - Contributed by Georg-Johann Lay (avr@gjlay.de) - -This file is part of GCC. - -GCC is free software; you can redistribute it and/or modify -it under the terms of the GNU General Public License as published by -the Free Software Foundation; either version 3, or (at your option) -any later version. - -GCC is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU General Public License for more details. - -You should have received a copy of the GNU General Public License -along with GCC; see the file COPYING3. If not see -. */ - - -/* Default specs layout. The actual definitions might be superseeded - by device- or OS- specific files, like avrlibc.h, ../rtems.h, etc. - The specs are repeated in the device specs files. Subspecs are - specs known to GCC or specs defined in the device specs files. */ - - -#undef CPLUSPLUS_CPP_SPEC -#define CPLUSPLUS_CPP_SPEC \ - "%(cpp)" - -#undef CC1_SPEC -#define CC1_SPEC \ - "%(cc1_n_flash) " \ - "%(cc1_errata_skip) " \ - "%(cc1_rmw) " \ - "%(cc1_non_bit_addressable_registers_mask) " \ - "%(cc1_absdata) " - -#undef CC1PLUS_SPEC -#define CC1PLUS_SPEC \ - "%(cc1) " \ - "%{!frtti:-fno-rtti} " \ - "%{!fenforce-eh-specs:-fno-enforce-eh-specs} " \ - "%{!fexceptions:-fno-exceptions} " - -#define ASM_RELAX_SPEC \ - "%{mrelax:--mlink-relax} " - -#undef ASM_SPEC -#define ASM_SPEC \ - "%(asm_arch) " \ - "%(asm_relax) " \ - "%(asm_rmw) " \ - "%(asm_errata_skip) " - -#define LINK_ARCH_SPEC \ - "%{mmcu=*:-m%*} " - -#define LINK_RELAX_SPEC \ - "%{mrelax:--relax} " - -#undef LINK_SPEC -#define LINK_SPEC \ - "%(link_arch) " \ - "%(link_data_start) " \ - "%(link_text_start) " \ - "%(link_relax) " \ - "%(link_pmem_wrap) " \ - "%{shared:%eshared is not supported} " - -#undef LIB_SPEC -#define LIB_SPEC " %{!mmcu=avr1:-lc} " - -#undef LIBGCC_SPEC -#define LIBGCC_SPEC " %{!mmcu=avr1:-lgcc} " - -#define STARTFILE_SPEC "" -#define ENDFILE_SPEC "" diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/config/dbxelf.h b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/config/dbxelf.h deleted file mode 100644 index b4b4a24..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/config/dbxelf.h +++ /dev/null @@ -1,68 +0,0 @@ -/* Definitions needed when using stabs embedded in ELF sections. - Copyright (C) 1999-2015 Free Software Foundation, Inc. - -This file is part of GCC. - -GCC is free software; you can redistribute it and/or modify -it under the terms of the GNU General Public License as published by -the Free Software Foundation; either version 3, or (at your option) -any later version. - -GCC is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU General Public License for more details. - -Under Section 7 of GPL version 3, you are granted additional -permissions described in the GCC Runtime Library Exception, version -3.1, as published by the Free Software Foundation. - -You should have received a copy of the GNU General Public License and -a copy of the GCC Runtime Library Exception along with this program; -see the files COPYING3 and COPYING.RUNTIME respectively. If not, see -. */ - -/* This file may be included by any ELF target which wishes to - support -gstabs generating stabs in sections, as produced by gas - and understood by gdb. */ - -#ifndef GCC_DBX_ELF_H -#define GCC_DBX_ELF_H - -/* Output DBX (stabs) debugging information if doing -gstabs. */ - -#define DBX_DEBUGGING_INFO 1 - -/* Make LBRAC and RBRAC addresses relative to the start of the - function. The native Solaris stabs debugging format works this - way, gdb expects it, and it reduces the number of relocation - entries... */ - -#define DBX_BLOCKS_FUNCTION_RELATIVE 1 - -/* ... but, to make this work, functions must appear prior to line info. */ - -#define DBX_FUNCTION_FIRST - -/* When generating stabs debugging, use N_BINCL entries. */ - -#define DBX_USE_BINCL - -/* There is no limit to the length of stabs strings. */ - -#ifndef DBX_CONTIN_LENGTH -#define DBX_CONTIN_LENGTH 0 -#endif - -/* Like block addresses, stabs line numbers are relative to the - current function. */ - -#define DBX_LINES_FUNCTION_RELATIVE 1 - -/* Generate a blank trailing N_SO to mark the end of the .o file, since - we can't depend upon the linker to mark .o file boundaries with - embedded stabs. */ - -#define DBX_OUTPUT_NULL_N_SO_AT_MAIN_SOURCE_FILE_END - -#endif /* ! GCC_DBX_ELF_H */ diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/config/elfos.h b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/config/elfos.h deleted file mode 100644 index c3b9487..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/config/elfos.h +++ /dev/null @@ -1,438 +0,0 @@ -/* elfos.h -- operating system specific defines to be used when - targeting GCC for some generic ELF system - Copyright (C) 1991-2015 Free Software Foundation, Inc. - Based on svr4.h contributed by Ron Guilmette (rfg@netcom.com). - -This file is part of GCC. - -GCC is free software; you can redistribute it and/or modify -it under the terms of the GNU General Public License as published by -the Free Software Foundation; either version 3, or (at your option) -any later version. - -GCC is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU General Public License for more details. - -Under Section 7 of GPL version 3, you are granted additional -permissions described in the GCC Runtime Library Exception, version -3.1, as published by the Free Software Foundation. - -You should have received a copy of the GNU General Public License and -a copy of the GCC Runtime Library Exception along with this program; -see the files COPYING3 and COPYING.RUNTIME respectively. If not, see -. */ - -#define TARGET_OBJFMT_CPP_BUILTINS() \ - do \ - { \ - builtin_define ("__ELF__"); \ - } \ - while (0) - -/* Define a symbol indicating that we are using elfos.h. - Some CPU specific configuration files use this. */ -#define USING_ELFOS_H - -/* The prefix to add to user-visible assembler symbols. - - For ELF systems the convention is *not* to prepend a leading - underscore onto user-level symbol names. */ - -#undef USER_LABEL_PREFIX -#define USER_LABEL_PREFIX "" - -/* The biggest alignment supported by ELF in bits. 32-bit ELF - supports section alignment up to (0x80000000 * 8), while - 64-bit ELF supports (0x8000000000000000 * 8). If this macro - is not defined, the default is the largest alignment supported - by 32-bit ELF and representable on a 32-bit host. Use this - macro to limit the alignment which can be specified using - the `__attribute__ ((aligned (N)))' construct. */ -#ifndef MAX_OFILE_ALIGNMENT -#define MAX_OFILE_ALIGNMENT (((unsigned int) 1 << 28) * 8) -#endif - -/* Use periods rather than dollar signs in special g++ assembler names. */ - -#define NO_DOLLAR_IN_LABEL - -/* Writing `int' for a bit-field forces int alignment for the structure. */ - -#ifndef PCC_BITFIELD_TYPE_MATTERS -#define PCC_BITFIELD_TYPE_MATTERS 1 -#endif - -/* All ELF targets can support DWARF-2. */ - -#define DWARF2_DEBUGGING_INFO 1 - -/* The GNU tools operate better with dwarf2, and it is required by some - psABI's. Since we don't have any native tools to be compatible with, - default to dwarf2. */ - -#ifndef PREFERRED_DEBUGGING_TYPE -#define PREFERRED_DEBUGGING_TYPE DWARF2_DEBUG -#endif - -/* All SVR4 targets use the ELF object file format. */ -#define OBJECT_FORMAT_ELF - - -/* Output #ident as a .ident. */ - -#undef TARGET_ASM_OUTPUT_IDENT -#define TARGET_ASM_OUTPUT_IDENT default_asm_output_ident_directive - -#undef SET_ASM_OP -#define SET_ASM_OP "\t.set\t" - -/* Most svr4 assemblers want a .file directive at the beginning of - their input file. */ -#define TARGET_ASM_FILE_START_FILE_DIRECTIVE true - -/* This is how to allocate empty space in some section. The .zero - pseudo-op is used for this on most svr4 assemblers. */ - -#define SKIP_ASM_OP "\t.zero\t" - -#undef ASM_OUTPUT_SKIP -#define ASM_OUTPUT_SKIP(FILE, SIZE) \ - fprintf ((FILE), "%s"HOST_WIDE_INT_PRINT_UNSIGNED"\n",\ - SKIP_ASM_OP, (SIZE)) - -/* This is how to store into the string LABEL - the symbol_ref name of an internal numbered label where - PREFIX is the class of label and NUM is the number within the class. - This is suitable for output with `assemble_name'. - - For most svr4 systems, the convention is that any symbol which begins - with a period is not put into the linker symbol table by the assembler. */ - -#undef ASM_GENERATE_INTERNAL_LABEL -#define ASM_GENERATE_INTERNAL_LABEL(LABEL, PREFIX, NUM) \ - do \ - { \ - char *__p; \ - (LABEL)[0] = '*'; \ - (LABEL)[1] = '.'; \ - __p = stpcpy (&(LABEL)[2], PREFIX); \ - sprint_ul (__p, (unsigned long) (NUM)); \ - } \ - while (0) - -/* Output the label which precedes a jumptable. Note that for all svr4 - systems where we actually generate jumptables (which is to say every - svr4 target except i386, where we use casesi instead) we put the jump- - tables into the .rodata section and since other stuff could have been - put into the .rodata section prior to any given jumptable, we have to - make sure that the location counter for the .rodata section gets pro- - perly re-aligned prior to the actual beginning of the jump table. */ - -#undef ALIGN_ASM_OP -#define ALIGN_ASM_OP "\t.align\t" - -#ifndef ASM_OUTPUT_BEFORE_CASE_LABEL -#define ASM_OUTPUT_BEFORE_CASE_LABEL(FILE, PREFIX, NUM, TABLE) \ - ASM_OUTPUT_ALIGN ((FILE), 2); -#endif - -#undef ASM_OUTPUT_CASE_LABEL -#define ASM_OUTPUT_CASE_LABEL(FILE, PREFIX, NUM, JUMPTABLE) \ - do \ - { \ - ASM_OUTPUT_BEFORE_CASE_LABEL (FILE, PREFIX, NUM, JUMPTABLE) \ - (*targetm.asm_out.internal_label) (FILE, PREFIX, NUM); \ - } \ - while (0) - -/* The standard SVR4 assembler seems to require that certain builtin - library routines (e.g. .udiv) be explicitly declared as .globl - in each assembly file where they are referenced. */ - -#define ASM_OUTPUT_EXTERNAL_LIBCALL(FILE, FUN) \ - (*targetm.asm_out.globalize_label) (FILE, XSTR (FUN, 0)) - -/* This says how to output assembler code to declare an - uninitialized external linkage data object. Under SVR4, - the linker seems to want the alignment of data objects - to depend on their types. We do exactly that here. */ - -#define COMMON_ASM_OP "\t.comm\t" - -#undef ASM_OUTPUT_ALIGNED_COMMON -#define ASM_OUTPUT_ALIGNED_COMMON(FILE, NAME, SIZE, ALIGN) \ - do \ - { \ - fprintf ((FILE), "%s", COMMON_ASM_OP); \ - assemble_name ((FILE), (NAME)); \ - fprintf ((FILE), ","HOST_WIDE_INT_PRINT_UNSIGNED",%u\n", \ - (SIZE), (ALIGN) / BITS_PER_UNIT); \ - } \ - while (0) - -/* This says how to output assembler code to declare an - uninitialized internal linkage data object. Under SVR4, - the linker seems to want the alignment of data objects - to depend on their types. We do exactly that here. */ - -#define LOCAL_ASM_OP "\t.local\t" - -#undef ASM_OUTPUT_ALIGNED_LOCAL -#define ASM_OUTPUT_ALIGNED_LOCAL(FILE, NAME, SIZE, ALIGN) \ - do \ - { \ - fprintf ((FILE), "%s", LOCAL_ASM_OP); \ - assemble_name ((FILE), (NAME)); \ - fprintf ((FILE), "\n"); \ - ASM_OUTPUT_ALIGNED_COMMON (FILE, NAME, SIZE, ALIGN); \ - } \ - while (0) - -/* This is the pseudo-op used to generate a contiguous sequence of byte - values from a double-quoted string WITHOUT HAVING A TERMINATING NUL - AUTOMATICALLY APPENDED. This is the same for most svr4 assemblers. */ - -#undef ASCII_DATA_ASM_OP -#define ASCII_DATA_ASM_OP "\t.ascii\t" - -/* Support a read-only data section. */ -#define READONLY_DATA_SECTION_ASM_OP "\t.section\t.rodata" - -/* On svr4, we *do* have support for the .init and .fini sections, and we - can put stuff in there to be executed before and after `main'. We let - crtstuff.c and other files know this by defining the following symbols. - The definitions say how to change sections to the .init and .fini - sections. This is the same for all known svr4 assemblers. */ - -#define INIT_SECTION_ASM_OP "\t.section\t.init" -#define FINI_SECTION_ASM_OP "\t.section\t.fini" - -/* Output assembly directive to move to the beginning of current section. */ -#ifdef HAVE_GAS_SUBSECTION_ORDERING -# define ASM_SECTION_START_OP "\t.subsection\t-1" -# define ASM_OUTPUT_SECTION_START(FILE) \ - fprintf ((FILE), "%s\n", ASM_SECTION_START_OP) -#endif - -#define MAKE_DECL_ONE_ONLY(DECL) (DECL_WEAK (DECL) = 1) - -/* Switch into a generic section. */ -#define TARGET_ASM_NAMED_SECTION default_elf_asm_named_section - -#undef TARGET_ASM_SELECT_RTX_SECTION -#define TARGET_ASM_SELECT_RTX_SECTION default_elf_select_rtx_section -#undef TARGET_ASM_SELECT_SECTION -#define TARGET_ASM_SELECT_SECTION default_elf_select_section -#undef TARGET_HAVE_SWITCHABLE_BSS_SECTIONS -#define TARGET_HAVE_SWITCHABLE_BSS_SECTIONS true - -/* Define the strings used for the special svr4 .type and .size directives. - These strings generally do not vary from one system running svr4 to - another, but if a given system (e.g. m88k running svr) needs to use - different pseudo-op names for these, they may be overridden in the - file which includes this one. */ - -#define TYPE_ASM_OP "\t.type\t" -#define SIZE_ASM_OP "\t.size\t" - -/* This is how we tell the assembler that a symbol is weak. */ - -#define ASM_WEAKEN_LABEL(FILE, NAME) \ - do \ - { \ - fputs ("\t.weak\t", (FILE)); \ - assemble_name ((FILE), (NAME)); \ - fputc ('\n', (FILE)); \ - } \ - while (0) - -/* The following macro defines the format used to output the second - operand of the .type assembler directive. Different svr4 assemblers - expect various different forms for this operand. The one given here - is just a default. You may need to override it in your machine- - specific tm.h file (depending upon the particulars of your assembler). */ - -#define TYPE_OPERAND_FMT "@%s" - -/* Write the extra assembler code needed to declare a function's result. - Most svr4 assemblers don't require any special declaration of the - result value, but there are exceptions. */ - -#ifndef ASM_DECLARE_RESULT -#define ASM_DECLARE_RESULT(FILE, RESULT) -#endif - -/* These macros generate the special .type and .size directives which - are used to set the corresponding fields of the linker symbol table - entries in an ELF object file under SVR4. These macros also output - the starting labels for the relevant functions/objects. */ - -/* Write the extra assembler code needed to declare a function properly. - Some svr4 assemblers need to also have something extra said about the - function's return value. We allow for that here. */ - -#ifndef ASM_DECLARE_FUNCTION_NAME -#define ASM_DECLARE_FUNCTION_NAME(FILE, NAME, DECL) \ - do \ - { \ - ASM_OUTPUT_TYPE_DIRECTIVE (FILE, NAME, "function"); \ - ASM_DECLARE_RESULT (FILE, DECL_RESULT (DECL)); \ - ASM_OUTPUT_FUNCTION_LABEL (FILE, NAME, DECL); \ - } \ - while (0) -#endif - -/* Write the extra assembler code needed to declare an object properly. */ - -#ifdef HAVE_GAS_GNU_UNIQUE_OBJECT -#define USE_GNU_UNIQUE_OBJECT flag_gnu_unique -#else -#define USE_GNU_UNIQUE_OBJECT 0 -#endif - -#define ASM_DECLARE_OBJECT_NAME(FILE, NAME, DECL) \ - do \ - { \ - HOST_WIDE_INT size; \ - \ - /* For template static data member instantiations or \ - inline fn local statics and their guard variables, use \ - gnu_unique_object so that they will be combined even under \ - RTLD_LOCAL. Don't use gnu_unique_object for typeinfo, \ - vtables and other read-only artificial decls. */ \ - if (USE_GNU_UNIQUE_OBJECT && DECL_ONE_ONLY (DECL) \ - && (!DECL_ARTIFICIAL (DECL) || !TREE_READONLY (DECL))) \ - ASM_OUTPUT_TYPE_DIRECTIVE (FILE, NAME, "gnu_unique_object"); \ - else \ - ASM_OUTPUT_TYPE_DIRECTIVE (FILE, NAME, "object"); \ - \ - size_directive_output = 0; \ - if (!flag_inhibit_size_directive \ - && (DECL) && DECL_SIZE (DECL)) \ - { \ - size_directive_output = 1; \ - size = tree_to_uhwi (DECL_SIZE_UNIT (DECL)); \ - ASM_OUTPUT_SIZE_DIRECTIVE (FILE, NAME, size); \ - } \ - \ - ASM_OUTPUT_LABEL (FILE, NAME); \ - } \ - while (0) - -/* Output the size directive for a decl in rest_of_decl_compilation - in the case where we did not do so before the initializer. - Once we find the error_mark_node, we know that the value of - size_directive_output was set - by ASM_DECLARE_OBJECT_NAME when it was run for the same decl. */ - -#undef ASM_FINISH_DECLARE_OBJECT -#define ASM_FINISH_DECLARE_OBJECT(FILE, DECL, TOP_LEVEL, AT_END)\ - do \ - { \ - const char *name = XSTR (XEXP (DECL_RTL (DECL), 0), 0); \ - HOST_WIDE_INT size; \ - \ - if (!flag_inhibit_size_directive \ - && DECL_SIZE (DECL) \ - && ! AT_END && TOP_LEVEL \ - && DECL_INITIAL (DECL) == error_mark_node \ - && !size_directive_output) \ - { \ - size_directive_output = 1; \ - size = tree_to_uhwi (DECL_SIZE_UNIT (DECL)); \ - ASM_OUTPUT_SIZE_DIRECTIVE (FILE, name, size); \ - } \ - } \ - while (0) - -/* This is how to declare the size of a function. */ -#ifndef ASM_DECLARE_FUNCTION_SIZE -#define ASM_DECLARE_FUNCTION_SIZE(FILE, FNAME, DECL) \ - do \ - { \ - if (!flag_inhibit_size_directive) \ - ASM_OUTPUT_MEASURED_SIZE (FILE, FNAME); \ - } \ - while (0) -#endif - -/* A table of bytes codes used by the ASM_OUTPUT_ASCII and - ASM_OUTPUT_LIMITED_STRING macros. Each byte in the table - corresponds to a particular byte value [0..255]. For any - given byte value, if the value in the corresponding table - position is zero, the given character can be output directly. - If the table value is 1, the byte must be output as a \ooo - octal escape. If the tables value is anything else, then the - byte value should be output as a \ followed by the value - in the table. Note that we can use standard UN*X escape - sequences for many control characters, but we don't use - \a to represent BEL because some svr4 assemblers (e.g. on - the i386) don't know about that. Also, we don't use \v - since some versions of gas, such as 2.2 did not accept it. */ - -#define ELF_ASCII_ESCAPES \ -"\1\1\1\1\1\1\1\1btn\1fr\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\ -\0\0\"\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\ -\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\\\0\0\0\ -\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\1\ -\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\ -\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\ -\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\ -\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1" - -/* Some svr4 assemblers have a limit on the number of characters which - can appear in the operand of a .string directive. If your assembler - has such a limitation, you should define STRING_LIMIT to reflect that - limit. Note that at least some svr4 assemblers have a limit on the - actual number of bytes in the double-quoted string, and that they - count each character in an escape sequence as one byte. Thus, an - escape sequence like \377 would count as four bytes. - - If your target assembler doesn't support the .string directive, you - should define this to zero. -*/ - -#define ELF_STRING_LIMIT ((unsigned) 256) - -#define STRING_ASM_OP "\t.string\t" - -/* The routine used to output NUL terminated strings. We use a special - version of this for most svr4 targets because doing so makes the - generated assembly code more compact (and thus faster to assemble) - as well as more readable, especially for targets like the i386 - (where the only alternative is to output character sequences as - comma separated lists of numbers). */ - -#define ASM_OUTPUT_LIMITED_STRING(FILE, STR) \ - default_elf_asm_output_limited_string ((FILE), (STR)) - -/* The routine used to output sequences of byte values. We use a special - version of this for most svr4 targets because doing so makes the - generated assembly code more compact (and thus faster to assemble) - as well as more readable. Note that if we find subparts of the - character sequence which end with NUL (and which are shorter than - STRING_LIMIT) we output those using ASM_OUTPUT_LIMITED_STRING. */ - -#undef ASM_OUTPUT_ASCII -#define ASM_OUTPUT_ASCII(FILE, STR, LENGTH) \ - default_elf_asm_output_ascii ((FILE), (STR), (LENGTH)); - -/* Allow the use of the -frecord-gcc-switches switch via the - elf_record_gcc_switches function defined in varasm.c. */ -#undef TARGET_ASM_RECORD_GCC_SWITCHES -#define TARGET_ASM_RECORD_GCC_SWITCHES elf_record_gcc_switches - -/* A C statement (sans semicolon) to output to the stdio stream STREAM - any text necessary for declaring the name of an external symbol - named NAME which is referenced in this compilation but not defined. - It is needed to properly support non-default visibility. */ - -#ifndef ASM_OUTPUT_EXTERNAL -#define ASM_OUTPUT_EXTERNAL(FILE, DECL, NAME) \ - default_elf_asm_output_external (FILE, DECL, NAME) -#endif - -#undef TARGET_LIBC_HAS_FUNCTION -#define TARGET_LIBC_HAS_FUNCTION no_c99_libc_has_function diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/config/initfini-array.h b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/config/initfini-array.h deleted file mode 100644 index 06da397..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/config/initfini-array.h +++ /dev/null @@ -1,45 +0,0 @@ -/* Definitions for ELF systems with .init_array/.fini_array section - support. - Copyright (C) 2011-2015 Free Software Foundation, Inc. - - This file is part of GCC. - - GCC is free software; you can redistribute it and/or modify it - under the terms of the GNU General Public License as published - by the Free Software Foundation; either version 3, or (at your - option) any later version. - - GCC is distributed in the hope that it will be useful, but WITHOUT - ANY WARRANTY; without even the implied warranty of MERCHANTABILITY - or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public - License for more details. - - Under Section 7 of GPL version 3, you are granted additional - permissions described in the GCC Runtime Library Exception, version - 3.1, as published by the Free Software Foundation. - - You should have received a copy of the GNU General Public License and - a copy of the GCC Runtime Library Exception along with this program; - see the files COPYING3 and COPYING.RUNTIME respectively. If not, see - . */ - -#ifdef HAVE_INITFINI_ARRAY_SUPPORT - -#define USE_INITFINI_ARRAY - -#undef INIT_SECTION_ASM_OP -#undef FINI_SECTION_ASM_OP - -#undef INIT_ARRAY_SECTION_ASM_OP -#define INIT_ARRAY_SECTION_ASM_OP - -#undef FINI_ARRAY_SECTION_ASM_OP -#define FINI_ARRAY_SECTION_ASM_OP - -/* Use .init_array/.fini_array section for constructors and destructors. */ -#undef TARGET_ASM_CONSTRUCTOR -#define TARGET_ASM_CONSTRUCTOR default_elf_init_array_asm_out_constructor -#undef TARGET_ASM_DESTRUCTOR -#define TARGET_ASM_DESTRUCTOR default_elf_fini_array_asm_out_destructor - -#endif diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/config/tm-dwarf2.h b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/config/tm-dwarf2.h deleted file mode 100644 index d08646e..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/config/tm-dwarf2.h +++ /dev/null @@ -1,4 +0,0 @@ -/* Enable Dwarf2 debugging and make it the default */ -#define DWARF2_DEBUGGING_INFO 1 -#undef PREFERRED_DEBUGGING_TYPE -#define PREFERRED_DEBUGGING_TYPE DWARF2_DEBUG diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/configargs.h b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/configargs.h deleted file mode 100644 index aa0135a..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/configargs.h +++ /dev/null @@ -1,7 +0,0 @@ -/* Generated automatically. */ -static const char configuration_arguments[] = "../gcc/configure --enable-fixed-point --enable-languages=c,c++ --prefix=/home/jenkins/workspace/avr-gcc-staging/label/debian7-x86_64/objdir --disable-nls --disable-libssp --disable-libada --disable-shared --with-avrlibc=yes --with-dwarf2 --disable-doc --target=avr"; -static const char thread_model[] = "single"; - -static const struct { - const char *name, *value; -} configure_default_options[] = { { NULL, NULL} }; diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/context.h b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/context.h deleted file mode 100644 index 21013a0..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/context.h +++ /dev/null @@ -1,63 +0,0 @@ -/* context.h - Holder for global state - Copyright (C) 2013-2015 Free Software Foundation, Inc. - -This file is part of GCC. - -GCC is free software; you can redistribute it and/or modify it under -the terms of the GNU General Public License as published by the Free -Software Foundation; either version 3, or (at your option) any later -version. - -GCC is distributed in the hope that it will be useful, but WITHOUT ANY -WARRANTY; without even the implied warranty of MERCHANTABILITY or -FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -for more details. - -You should have received a copy of the GNU General Public License -along with GCC; see the file COPYING3. If not see -. */ - -#ifndef GCC_CONTEXT_H -#define GCC_CONTEXT_H - -namespace gcc { - -class pass_manager; -class dump_manager; - -/* GCC's internal state can be divided into zero or more - "parallel universe" of state; an instance of this class is one such - context of state. */ -class context -{ -public: - context (); - ~context (); - - /* The flag shows if there are symbols to be streamed for offloading. */ - bool have_offload; - - /* Pass-management. */ - - pass_manager *get_passes () { gcc_assert (m_passes); return m_passes; } - - /* Handling dump files. */ - - dump_manager *get_dumps () {gcc_assert (m_dumps); return m_dumps; } - -private: - /* Pass-management. */ - pass_manager *m_passes; - - /* Dump files. */ - dump_manager *m_dumps; - -}; // class context - -} // namespace gcc - -/* The global singleton context aka "g". - (the name is chosen to be easy to type in a debugger). */ -extern gcc::context *g; - -#endif /* ! GCC_CONTEXT_H */ diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/convert.h b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/convert.h deleted file mode 100644 index f2e4a65..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/convert.h +++ /dev/null @@ -1,30 +0,0 @@ -/* Definition of functions in convert.c. - Copyright (C) 1993-2015 Free Software Foundation, Inc. - -This file is part of GCC. - -GCC is free software; you can redistribute it and/or modify it under -the terms of the GNU General Public License as published by the Free -Software Foundation; either version 3, or (at your option) any later -version. - -GCC is distributed in the hope that it will be useful, but WITHOUT ANY -WARRANTY; without even the implied warranty of MERCHANTABILITY or -FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -for more details. - -You should have received a copy of the GNU General Public License -along with GCC; see the file COPYING3. If not see -. */ - -#ifndef GCC_CONVERT_H -#define GCC_CONVERT_H - -extern tree convert_to_integer (tree, tree); -extern tree convert_to_pointer (tree, tree); -extern tree convert_to_real (tree, tree); -extern tree convert_to_fixed (tree, tree); -extern tree convert_to_complex (tree, tree); -extern tree convert_to_vector (tree, tree); - -#endif /* GCC_CONVERT_H */ diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/coretypes.h b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/coretypes.h deleted file mode 100644 index 0ee8633..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/coretypes.h +++ /dev/null @@ -1,302 +0,0 @@ -/* GCC core type declarations. - Copyright (C) 2002-2015 Free Software Foundation, Inc. - -This file is part of GCC. - -GCC is free software; you can redistribute it and/or modify it under -the terms of the GNU General Public License as published by the Free -Software Foundation; either version 3, or (at your option) any later -version. - -GCC is distributed in the hope that it will be useful, but WITHOUT ANY -WARRANTY; without even the implied warranty of MERCHANTABILITY or -FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -for more details. - -Under Section 7 of GPL version 3, you are granted additional -permissions described in the GCC Runtime Library Exception, version -3.1, as published by the Free Software Foundation. - -You should have received a copy of the GNU General Public License and -a copy of the GCC Runtime Library Exception along with this program; -see the files COPYING3 and COPYING.RUNTIME respectively. If not, see -. */ - -/* Provide forward declarations of core types which are referred to by - most of the compiler. This allows header files to use these types - (e.g. in function prototypes) without concern for whether the full - definitions are visible. Some other declarations that need to be - universally visible are here, too. - - In the context of tconfig.h, most of these have special definitions - which prevent them from being used except in further type - declarations. This is a kludge; the right thing is to avoid - including the "tm.h" header set in the context of tconfig.h, but - we're not there yet. */ - -#ifndef GCC_CORETYPES_H -#define GCC_CORETYPES_H - -#ifndef GTY -#define GTY(x) /* nothing - marker for gengtype */ -#endif - -#ifndef USED_FOR_TARGET - -typedef int64_t gcov_type; -typedef uint64_t gcov_type_unsigned; - -struct bitmap_head; -typedef struct bitmap_head *bitmap; -typedef const struct bitmap_head *const_bitmap; -struct simple_bitmap_def; -typedef struct simple_bitmap_def *sbitmap; -typedef const struct simple_bitmap_def *const_sbitmap; -struct rtx_def; -typedef struct rtx_def *rtx; -typedef const struct rtx_def *const_rtx; - -/* Subclasses of rtx_def, using indentation to show the class - hierarchy, along with the relevant invariant. - Where possible, keep this list in the same order as in rtl.def. */ -class rtx_def; - class rtx_expr_list; /* GET_CODE (X) == EXPR_LIST */ - class rtx_insn_list; /* GET_CODE (X) == INSN_LIST */ - class rtx_sequence; /* GET_CODE (X) == SEQUENCE */ - class rtx_insn; - class rtx_debug_insn; /* DEBUG_INSN_P (X) */ - class rtx_nonjump_insn; /* NONJUMP_INSN_P (X) */ - class rtx_jump_insn; /* JUMP_P (X) */ - class rtx_call_insn; /* CALL_P (X) */ - class rtx_jump_table_data; /* JUMP_TABLE_DATA_P (X) */ - class rtx_barrier; /* BARRIER_P (X) */ - class rtx_code_label; /* LABEL_P (X) */ - class rtx_note; /* NOTE_P (X) */ - -struct rtvec_def; -typedef struct rtvec_def *rtvec; -typedef const struct rtvec_def *const_rtvec; -struct hwivec_def; -typedef struct hwivec_def *hwivec; -typedef const struct hwivec_def *const_hwivec; -union tree_node; -typedef union tree_node *tree; -typedef const union tree_node *const_tree; -typedef struct gimple_statement_base *gimple; -typedef const struct gimple_statement_base *const_gimple; -typedef gimple gimple_seq; -struct gimple_stmt_iterator; - -/* Forward decls for leaf gimple subclasses (for individual gimple codes). - Keep this in the same order as the corresponding codes in gimple.def. */ - -struct gcond; -struct gdebug; -struct ggoto; -struct glabel; -struct gswitch; -struct gassign; -struct gasm; -struct gcall; -struct gtransaction; -struct greturn; -struct gbind; -struct gcatch; -struct geh_filter; -struct geh_mnt; -struct geh_else; -struct gresx; -struct geh_dispatch; -struct gphi; -struct gtry; -struct gomp_atomic_load; -struct gomp_atomic_store; -struct gomp_continue; -struct gomp_critical; -struct gomp_for; -struct gomp_parallel; -struct gomp_task; -struct gomp_sections; -struct gomp_single; -struct gomp_target; -struct gomp_teams; - -union section; -typedef union section section; -struct gcc_options; -struct cl_target_option; -struct cl_optimization; -struct cl_option; -struct cl_decoded_option; -struct cl_option_handlers; -struct diagnostic_context; -struct pretty_printer; - -/* Address space number for named address space support. */ -typedef unsigned char addr_space_t; - -/* The value of addr_space_t that represents the generic address space. */ -#define ADDR_SPACE_GENERIC 0 -#define ADDR_SPACE_GENERIC_P(AS) ((AS) == ADDR_SPACE_GENERIC) - -/* The major intermediate representations of GCC. */ -enum ir_type { - IR_GIMPLE, - IR_RTL_CFGRTL, - IR_RTL_CFGLAYOUT -}; - -/* Provide forward struct declaration so that we don't have to include - all of cpplib.h whenever a random prototype includes a pointer. - Note that the cpp_reader and cpp_token typedefs remain part of - cpplib.h. */ - -struct cpp_reader; -struct cpp_token; - -/* The thread-local storage model associated with a given VAR_DECL - or SYMBOL_REF. This isn't used much, but both trees and RTL refer - to it, so it's here. */ -enum tls_model { - TLS_MODEL_NONE, - TLS_MODEL_EMULATED, - TLS_MODEL_REAL, - TLS_MODEL_GLOBAL_DYNAMIC = TLS_MODEL_REAL, - TLS_MODEL_LOCAL_DYNAMIC, - TLS_MODEL_INITIAL_EXEC, - TLS_MODEL_LOCAL_EXEC -}; - -/* Types of ABI for an offload compiler. */ -enum offload_abi { - OFFLOAD_ABI_UNSET, - OFFLOAD_ABI_LP64, - OFFLOAD_ABI_ILP32 -}; - -/* Types of unwind/exception handling info that can be generated. */ - -enum unwind_info_type -{ - UI_NONE, - UI_SJLJ, - UI_DWARF2, - UI_TARGET, - UI_SEH -}; - -/* Callgraph node profile representation. */ -enum node_frequency { - /* This function most likely won't be executed at all. - (set only when profile feedback is available or via function attribute). */ - NODE_FREQUENCY_UNLIKELY_EXECUTED, - /* For functions that are known to be executed once (i.e. constructors, destructors - and main function. */ - NODE_FREQUENCY_EXECUTED_ONCE, - /* The default value. */ - NODE_FREQUENCY_NORMAL, - /* Optimize this function hard - (set only when profile feedback is available or via function attribute). */ - NODE_FREQUENCY_HOT -}; - -/* Possible initialization status of a variable. When requested - by the user, this information is tracked and recorded in the DWARF - debug information, along with the variable's location. */ -enum var_init_status -{ - VAR_INIT_STATUS_UNKNOWN, - VAR_INIT_STATUS_UNINITIALIZED, - VAR_INIT_STATUS_INITIALIZED -}; - - -struct edge_def; -typedef struct edge_def *edge; -typedef const struct edge_def *const_edge; -struct basic_block_def; -typedef struct basic_block_def *basic_block; -typedef const struct basic_block_def *const_basic_block; - -#define obstack_chunk_alloc xmalloc -#define obstack_chunk_free free -#define OBSTACK_CHUNK_SIZE 0 -#define gcc_obstack_init(OBSTACK) \ - obstack_specify_allocation ((OBSTACK), OBSTACK_CHUNK_SIZE, 0, \ - obstack_chunk_alloc, \ - obstack_chunk_free) - -/* enum reg_class is target specific, so it should not appear in - target-independent code or interfaces, like the target hook declarations - in target.h. */ -typedef int reg_class_t; - -class rtl_opt_pass; - -namespace gcc { - class context; -} - -#else - -struct _dont_use_rtx_here_; -struct _dont_use_rtvec_here_; -struct _dont_use_rtx_insn_here_; -union _dont_use_tree_here_; -#define rtx struct _dont_use_rtx_here_ * -#define const_rtx struct _dont_use_rtx_here_ * -#define rtvec struct _dont_use_rtvec_here * -#define const_rtvec struct _dont_use_rtvec_here * -#define rtx_insn struct _dont_use_rtx_insn_here_ -#define tree union _dont_use_tree_here_ * -#define const_tree union _dont_use_tree_here_ * - -#endif - -/* Classes of functions that compiler needs to check - whether they are present at the runtime or not. */ -enum function_class { - function_c94, - function_c99_misc, - function_c99_math_complex, - function_sincos, - function_c11_misc -}; - -/* Suppose that higher bits are target dependent. */ -#define MEMMODEL_MASK ((1<<16)-1) - -/* Legacy sync operations set this upper flag in the memory model. This allows - targets that need to do something stronger for sync operations to - differentiate with their target patterns and issue a more appropriate insn - sequence. See bugzilla 65697 for background. */ -#define MEMMODEL_SYNC (1<<15) - -/* Memory model without SYNC bit for targets/operations that do not care. */ -#define MEMMODEL_BASE_MASK (MEMMODEL_SYNC-1) - -/* Memory model types for the __atomic* builtins. - This must match the order in libstdc++-v3/include/bits/atomic_base.h. */ -enum memmodel -{ - MEMMODEL_RELAXED = 0, - MEMMODEL_CONSUME = 1, - MEMMODEL_ACQUIRE = 2, - MEMMODEL_RELEASE = 3, - MEMMODEL_ACQ_REL = 4, - MEMMODEL_SEQ_CST = 5, - MEMMODEL_LAST = 6, - MEMMODEL_SYNC_ACQUIRE = MEMMODEL_ACQUIRE | MEMMODEL_SYNC, - MEMMODEL_SYNC_RELEASE = MEMMODEL_RELEASE | MEMMODEL_SYNC, - MEMMODEL_SYNC_SEQ_CST = MEMMODEL_SEQ_CST | MEMMODEL_SYNC -}; - -/* Support for user-provided GGC and PCH markers. The first parameter - is a pointer to a pointer, the second a cookie. */ -typedef void (*gt_pointer_operator) (void *, void *); - -#if !defined (HAVE_UCHAR) -typedef unsigned char uchar; -#endif - -#endif /* coretypes.h */ diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/coverage.h b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/coverage.h deleted file mode 100644 index bac242f..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/coverage.h +++ /dev/null @@ -1,61 +0,0 @@ -/* coverage.h - Defines data exported from coverage.c - Copyright (C) 1998-2015 Free Software Foundation, Inc. - -This file is part of GCC. - -GCC is free software; you can redistribute it and/or modify it under -the terms of the GNU General Public License as published by the Free -Software Foundation; either version 3, or (at your option) any later -version. - -GCC is distributed in the hope that it will be useful, but WITHOUT ANY -WARRANTY; without even the implied warranty of MERCHANTABILITY or -FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -for more details. - -You should have received a copy of the GNU General Public License -along with GCC; see the file COPYING3. If not see -. */ - -#ifndef GCC_COVERAGE_H -#define GCC_COVERAGE_H - -#include "gcov-io.h" - -extern void coverage_init (const char *); -extern void coverage_finish (void); - -/* Start outputting coverage information for the current - function. */ -extern int coverage_begin_function (unsigned, unsigned); - -/* Complete the coverage information for the current function. */ -extern void coverage_end_function (unsigned, unsigned); - -/* Compute the control flow checksum for the function FN given as argument. */ -extern unsigned coverage_compute_cfg_checksum (struct function *fn); - -/* Compute the profile id of function N. */ -extern unsigned coverage_compute_profile_id (struct cgraph_node *n); - -/* Compute the line number checksum for the current function. */ -extern unsigned coverage_compute_lineno_checksum (void); - -/* Allocate some counters. Repeatable per function. */ -extern int coverage_counter_alloc (unsigned /*counter*/, unsigned/*num*/); -/* Use a counter from the most recent allocation. */ -extern tree tree_coverage_counter_ref (unsigned /*counter*/, unsigned/*num*/); -/* Use a counter address from the most recent allocation. */ -extern tree tree_coverage_counter_addr (unsigned /*counter*/, unsigned/*num*/); - -/* Get all the counters for the current function. */ -extern gcov_type *get_coverage_counts (unsigned /*counter*/, - unsigned /*expected*/, - unsigned /*cfg_checksum*/, - unsigned /*lineno_checksum*/, - const struct gcov_ctr_summary **); - -extern tree get_gcov_type (void); -extern bool coverage_node_map_initialized_p (void); - -#endif diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/cp/cp-tree.def b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/cp/cp-tree.def deleted file mode 100644 index 6117771..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/cp/cp-tree.def +++ /dev/null @@ -1,482 +0,0 @@ -/* This file contains the definitions and documentation for the - additional tree codes used in the GNU C++ compiler (see tree.def - for the standard codes). - Copyright (C) 1987-2015 Free Software Foundation, Inc. - Hacked by Michael Tiemann (tiemann@cygnus.com) - -This file is part of GCC. - -GCC is free software; you can redistribute it and/or modify -it under the terms of the GNU General Public License as published by -the Free Software Foundation; either version 3, or (at your option) -any later version. - -GCC is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU General Public License for more details. - -You should have received a copy of the GNU General Public License -along with GCC; see the file COPYING3. If not see -. */ - - -/* An OFFSET_REF is used in two situations: - - 1. An expression of the form `A::m' where `A' is a class and `m' is - a non-static member. In this case, operand 0 will be a TYPE - (corresponding to `A') and operand 1 will be a FIELD_DECL, - BASELINK, or TEMPLATE_ID_EXPR (corresponding to `m'). - - The expression is a pointer-to-member if its address is taken, - but simply denotes a member of the object if its address is not - taken. - - This form is only used during the parsing phase; once semantic - analysis has taken place they are eliminated. - - 2. An expression of the form `x.*p'. In this case, operand 0 will - be an expression corresponding to `x' and operand 1 will be an - expression with pointer-to-member type. */ -DEFTREECODE (OFFSET_REF, "offset_ref", tcc_reference, 2) - -/* A pointer-to-member constant. For a pointer-to-member constant - `X::Y' The PTRMEM_CST_CLASS is the RECORD_TYPE for `X' and the - PTRMEM_CST_MEMBER is the _DECL for `Y'. */ -DEFTREECODE (PTRMEM_CST, "ptrmem_cst", tcc_constant, 0) - -/* For NEW_EXPR, operand 0 is the placement list. - Operand 1 is the new-declarator. - Operand 2 is the number of elements in the array. - Operand 3 is the initializer. */ -DEFTREECODE (NEW_EXPR, "nw_expr", tcc_expression, 4) -DEFTREECODE (VEC_NEW_EXPR, "vec_nw_expr", tcc_expression, 3) - -/* For DELETE_EXPR, operand 0 is the store to be destroyed. - Operand 1 is the value to pass to the destroying function - saying whether the store should be deallocated as well. */ -DEFTREECODE (DELETE_EXPR, "dl_expr", tcc_expression, 2) -DEFTREECODE (VEC_DELETE_EXPR, "vec_dl_expr", tcc_expression, 2) - -/* Value is reference to particular overloaded class method. - Operand 0 is the class, operand 1 is the field - The COMPLEXITY field holds the class level (usually 0). */ -DEFTREECODE (SCOPE_REF, "scope_ref", tcc_reference, 2) - -/* When composing an object with a member, this is the result. - Operand 0 is the object. Operand 1 is the member (usually - a dereferenced pointer to member). */ -DEFTREECODE (MEMBER_REF, "member_ref", tcc_reference, 2) - -/* Type conversion operator in C++. TREE_TYPE is type that this - operator converts to. Operand is expression to be converted. */ -DEFTREECODE (TYPE_EXPR, "type_expr", tcc_expression, 1) - -/* AGGR_INIT_EXPRs have a variably-sized representation similar to - that of CALL_EXPRs. Operand 0 is an INTEGER_CST node containing the - operand count, operand 1 is the function which performs initialization, - operand 2 is the slot which was allocated for this expression, and - the remaining operands are the arguments to the initialization function. */ -DEFTREECODE (AGGR_INIT_EXPR, "aggr_init_expr", tcc_vl_exp, 3) - -/* Initialization of an array from another array, expressed at a high level - so that it works with TARGET_EXPR. Operand 0 is the target, operand 1 - is the initializer. */ -DEFTREECODE (VEC_INIT_EXPR, "vec_init_expr", tcc_expression, 2) - -/* A throw expression. operand 0 is the expression, if there was one, - else it is NULL_TREE. */ -DEFTREECODE (THROW_EXPR, "throw_expr", tcc_expression, 1) - -/* An empty class object. The TREE_TYPE gives the class type. We use - these to avoid actually creating instances of the empty classes. */ -DEFTREECODE (EMPTY_CLASS_EXPR, "empty_class_expr", tcc_expression, 0) - -/* A reference to a member function or member functions from a base - class. BASELINK_FUNCTIONS gives the FUNCTION_DECL, - TEMPLATE_DECL, OVERLOAD, or TEMPLATE_ID_EXPR corresponding to the - functions. BASELINK_BINFO gives the base from which the functions - come, i.e., the base to which the `this' pointer must be converted - before the functions are called. BASELINK_ACCESS_BINFO gives the - base used to name the functions. - - A BASELINK is an expression; the TREE_TYPE of the BASELINK gives - the type of the expression. This type is either a FUNCTION_TYPE, - METHOD_TYPE, or `unknown_type_node' indicating that the function is - overloaded. */ -DEFTREECODE (BASELINK, "baselink", tcc_exceptional, 0) - -/* Template definition. The following fields have the specified uses, - although there are other macros in cp-tree.h that should be used for - accessing this data. - DECL_ARGUMENTS template parm vector - DECL_TEMPLATE_INFO template text &c - DECL_VINDEX list of instantiations already produced; - only done for functions so far - For class template: - DECL_INITIAL associated templates (methods &c) - DECL_TEMPLATE_RESULT null - For non-class templates: - TREE_TYPE type of object to be constructed - DECL_TEMPLATE_RESULT decl for object to be created - (e.g., FUNCTION_DECL with tmpl parms used) - */ -DEFTREECODE (TEMPLATE_DECL, "template_decl", tcc_declaration, 0) - -/* Index into a template parameter list. The TEMPLATE_PARM_IDX gives - the index (from 0) of the parameter, while the TEMPLATE_PARM_LEVEL - gives the level (from 1) of the parameter. - - Here's an example: - - template // Index 0, Level 1. - struct S - { - template // Index 1, Level 2. - void f(); - }; - - The DESCENDANTS will be a chain of TEMPLATE_PARM_INDEXs descended - from this one. The first descendant will have the same IDX, but - its LEVEL will be one less. The TREE_CHAIN field is used to chain - together the descendants. The TEMPLATE_PARM_DECL is the - declaration of this parameter, either a TYPE_DECL or CONST_DECL. - The TEMPLATE_PARM_ORIG_LEVEL is the LEVEL of the most distant - parent, i.e., the LEVEL that the parameter originally had when it - was declared. For example, if we instantiate S, we will have: - - struct S - { - template // Index 1, Level 1, Orig Level 2 - void f(); - }; - - The LEVEL is the level of the parameter when we are worrying about - the types of things; the ORIG_LEVEL is the level when we are - worrying about instantiating things. */ -DEFTREECODE (TEMPLATE_PARM_INDEX, "template_parm_index", tcc_exceptional, 0) - -/* Index into a template parameter list for template template parameters. - This parameter must be a type. The TYPE_FIELDS value will be a - TEMPLATE_PARM_INDEX. - - It is used without template arguments like TT in C, - TEMPLATE_TEMPLATE_PARM_TEMPLATE_INFO is NULL_TREE - and TYPE_NAME is a TEMPLATE_DECL. */ -DEFTREECODE (TEMPLATE_TEMPLATE_PARM, "template_template_parm", tcc_type, 0) - -/* The ordering of the following codes is optimized for the checking - macros in tree.h. Changing the order will degrade the speed of the - compiler. TEMPLATE_TYPE_PARM, TYPENAME_TYPE, TYPEOF_TYPE, - BOUND_TEMPLATE_TEMPLATE_PARM. */ - -/* Index into a template parameter list. This parameter must be a type. - The type.values field will be a TEMPLATE_PARM_INDEX. */ -DEFTREECODE (TEMPLATE_TYPE_PARM, "template_type_parm", tcc_type, 0) - -/* A type designated by `typename T::t'. TYPE_CONTEXT is `T', - TYPE_NAME is an IDENTIFIER_NODE for `t'. If the type was named via - template-id, TYPENAME_TYPE_FULLNAME will hold the TEMPLATE_ID_EXPR. - TREE_TYPE is always NULL. */ -DEFTREECODE (TYPENAME_TYPE, "typename_type", tcc_type, 0) - -/* A type designated by `__typeof (expr)'. TYPEOF_TYPE_EXPR is the - expression in question. */ -DEFTREECODE (TYPEOF_TYPE, "typeof_type", tcc_type, 0) - -/* Like TEMPLATE_TEMPLATE_PARM it is used with bound template arguments - like TT. - In this case, TEMPLATE_TEMPLATE_PARM_TEMPLATE_INFO contains the - template name and its bound arguments. TYPE_NAME is a TYPE_DECL. */ -DEFTREECODE (BOUND_TEMPLATE_TEMPLATE_PARM, "bound_template_template_parm", - tcc_type, 0) - -/* For template template argument of the form `T::template C'. - TYPE_CONTEXT is `T', the template parameter dependent object. - TYPE_NAME is an IDENTIFIER_NODE for `C', the member class template. */ -DEFTREECODE (UNBOUND_CLASS_TEMPLATE, "unbound_class_template", tcc_type, 0) - -/* A using declaration. USING_DECL_SCOPE contains the specified - scope. In a member using decl, unless DECL_DEPENDENT_P is true, - USING_DECL_DECLS contains the _DECL or OVERLOAD so named. This is - not an alias, but is later expanded into multiple aliases. */ -DEFTREECODE (USING_DECL, "using_decl", tcc_declaration, 0) - -/* A using directive. The operand is USING_STMT_NAMESPACE. */ -DEFTREECODE (USING_STMT, "using_stmt", tcc_statement, 1) - -/* An un-parsed default argument. Holds a vector of input tokens and - a vector of places where the argument was instantiated before - parsing had occurred. */ -DEFTREECODE (DEFAULT_ARG, "default_arg", tcc_exceptional, 0) - -/* An uninstantiated/unevaluated noexcept-specification. For the - uninstantiated case, DEFERRED_NOEXCEPT_PATTERN is the pattern from the - template, and DEFERRED_NOEXCEPT_ARGS are the template arguments to - substitute into the pattern when needed. For the unevaluated case, - those slots are NULL_TREE and we use get_defaulted_eh_spec to find - the exception-specification. */ -DEFTREECODE (DEFERRED_NOEXCEPT, "deferred_noexcept", tcc_exceptional, 0) - -/* A template-id, like foo. The first operand is the template. - The second is NULL if there are no explicit arguments, or a - TREE_VEC of arguments. The template will be a FUNCTION_DECL, - TEMPLATE_DECL, or an OVERLOAD. If the template-id refers to a - member template, the template may be an IDENTIFIER_NODE. */ -DEFTREECODE (TEMPLATE_ID_EXPR, "template_id_expr", tcc_expression, 2) - -/* A list-like node for chaining overloading candidates. TREE_TYPE is - the original name, and the parameter is the FUNCTION_DECL. */ -DEFTREECODE (OVERLOAD, "overload", tcc_exceptional, 0) - -/* A pseudo-destructor, of the form "OBJECT.~DESTRUCTOR" or - "OBJECT.SCOPE::~DESTRUCTOR. The first operand is the OBJECT. The - second operand (if non-NULL) is the SCOPE. The third operand is - the TYPE node corresponding to the DESTRUCTOR. The type of the - first operand will always be a scalar type. - - The type of a PSEUDO_DTOR_EXPR is always "void", even though it can - be used as if it were a zero-argument function. We handle the - function-call case specially, and giving it "void" type prevents it - being used in expressions in ways that are not permitted. */ -DEFTREECODE (PSEUDO_DTOR_EXPR, "pseudo_dtor_expr", tcc_expression, 3) - -/* A whole bunch of tree codes for the initial, superficial parsing of - templates. */ -DEFTREECODE (MODOP_EXPR, "modop_expr", tcc_expression, 3) -DEFTREECODE (CAST_EXPR, "cast_expr", tcc_unary, 1) -DEFTREECODE (REINTERPRET_CAST_EXPR, "reinterpret_cast_expr", tcc_unary, 1) -DEFTREECODE (CONST_CAST_EXPR, "const_cast_expr", tcc_unary, 1) -DEFTREECODE (STATIC_CAST_EXPR, "static_cast_expr", tcc_unary, 1) -DEFTREECODE (DYNAMIC_CAST_EXPR, "dynamic_cast_expr", tcc_unary, 1) -DEFTREECODE (IMPLICIT_CONV_EXPR, "implicit_conv_expr", tcc_unary, 1) -DEFTREECODE (DOTSTAR_EXPR, "dotstar_expr", tcc_expression, 2) -DEFTREECODE (TYPEID_EXPR, "typeid_expr", tcc_expression, 1) -DEFTREECODE (NOEXCEPT_EXPR, "noexcept_expr", tcc_unary, 1) - -/* A placeholder for an expression that is not type-dependent, but - does occur in a template. When an expression that is not - type-dependent appears in a larger expression, we must compute the - type of that larger expression. That computation would normally - modify the original expression, which would change the mangling of - that expression if it appeared in a template argument list. In - that situation, we create a NON_DEPENDENT_EXPR to take the place of - the original expression. The expression is the only operand -- it - is only needed for diagnostics. */ -DEFTREECODE (NON_DEPENDENT_EXPR, "non_dependent_expr", tcc_expression, 1) - -/* CTOR_INITIALIZER is a placeholder in template code for a call to - setup_vtbl_pointer (and appears in all functions, not just ctors). */ -DEFTREECODE (CTOR_INITIALIZER, "ctor_initializer", tcc_expression, 1) - -DEFTREECODE (TRY_BLOCK, "try_block", tcc_statement, 2) - -DEFTREECODE (EH_SPEC_BLOCK, "eh_spec_block", tcc_statement, 2) - -/* A HANDLER wraps a catch handler for the HANDLER_TYPE. If this is - CATCH_ALL_TYPE, then the handler catches all types. The declaration of - the catch variable is in HANDLER_PARMS, and the body block in - HANDLER_BODY. */ -DEFTREECODE (HANDLER, "handler", tcc_statement, 2) - -/* A MUST_NOT_THROW_EXPR wraps an expression that may not - throw, and must call terminate if it does. The second argument - is a condition, used in templates to express noexcept (condition). */ -DEFTREECODE (MUST_NOT_THROW_EXPR, "must_not_throw_expr", tcc_expression, 2) - -/* A CLEANUP_STMT marks the point at which a declaration is fully - constructed. The CLEANUP_EXPR is run on behalf of CLEANUP_DECL - when CLEANUP_BODY completes. */ -DEFTREECODE (CLEANUP_STMT, "cleanup_stmt", tcc_statement, 3) - -/* Represents an 'if' statement. The operands are IF_COND, - THEN_CLAUSE, and ELSE_CLAUSE, and the current scope, respectively. */ -/* ??? It is currently still necessary to distinguish between IF_STMT - and COND_EXPR for the benefit of templates. */ -DEFTREECODE (IF_STMT, "if_stmt", tcc_statement, 4) - -/* Used to represent a `for' statement. The operands are - FOR_INIT_STMT, FOR_COND, FOR_EXPR, and FOR_BODY, respectively. */ -DEFTREECODE (FOR_STMT, "for_stmt", tcc_statement, 5) - -/* Used to represent a range-based `for' statement. The operands are - RANGE_FOR_DECL, RANGE_FOR_EXPR, RANGE_FOR_BODY, and RANGE_FOR_SCOPE, - respectively. Only used in templates. */ -DEFTREECODE (RANGE_FOR_STMT, "range_for_stmt", tcc_statement, 4) - -/* Used to represent a 'while' statement. The operands are WHILE_COND - and WHILE_BODY, respectively. */ -DEFTREECODE (WHILE_STMT, "while_stmt", tcc_statement, 2) - -/* Used to represent a 'do' statement. The operands are DO_BODY and - DO_COND, respectively. */ -DEFTREECODE (DO_STMT, "do_stmt", tcc_statement, 2) - -/* Used to represent a 'break' statement. */ -DEFTREECODE (BREAK_STMT, "break_stmt", tcc_statement, 0) - -/* Used to represent a 'continue' statement. */ -DEFTREECODE (CONTINUE_STMT, "continue_stmt", tcc_statement, 0) - -/* Used to represent a 'switch' statement. The operands are - SWITCH_STMT_COND, SWITCH_STMT_BODY, SWITCH_STMT_TYPE, and - SWITCH_STMT_SCOPE, respectively. */ -DEFTREECODE (SWITCH_STMT, "switch_stmt", tcc_statement, 4) - -/* Used to represent an expression statement. Use `EXPR_STMT_EXPR' to - obtain the expression. */ -DEFTREECODE (EXPR_STMT, "expr_stmt", tcc_expression, 1) - -DEFTREECODE (TAG_DEFN, "tag_defn", tcc_expression, 0) - -/* Represents an 'offsetof' expression during template expansion. */ -DEFTREECODE (OFFSETOF_EXPR, "offsetof_expr", tcc_expression, 1) - -/* Represents the -> operator during template expansion. */ -DEFTREECODE (ARROW_EXPR, "arrow_expr", tcc_expression, 1) - -/* Represents an '__alignof__' expression during template - expansion. */ -DEFTREECODE (ALIGNOF_EXPR, "alignof_expr", tcc_expression, 1) - -/* Represents an Objective-C++ '@encode' expression during template - expansion. */ -DEFTREECODE (AT_ENCODE_EXPR, "at_encode_expr", tcc_expression, 1) - -/* A STMT_EXPR represents a statement-expression during template - expansion. This is the GCC extension { ( ... ) }. The - STMT_EXPR_STMT is the statement given by the expression. */ -DEFTREECODE (STMT_EXPR, "stmt_expr", tcc_expression, 1) - -/* Unary plus. Operand 0 is the expression to which the unary plus - is applied. */ -DEFTREECODE (UNARY_PLUS_EXPR, "unary_plus_expr", tcc_unary, 1) - -/** C++11 extensions. */ - -/* A static assertion. This is a C++11 extension. - STATIC_ASSERT_CONDITION contains the condition that is being - checked. STATIC_ASSERT_MESSAGE contains the message (a string - literal) to be displayed if the condition fails to hold. */ -DEFTREECODE (STATIC_ASSERT, "static_assert", tcc_exceptional, 0) - -/* Represents an argument pack of types (or templates). An argument - pack stores zero or more arguments that will be used to instantiate - a parameter pack. - - ARGUMENT_PACK_ARGS retrieves the arguments stored in the argument - pack. - - Example: - template - class tuple { ... }; - - tuple t; - - Values is a (template) parameter pack. When tuple is instantiated, the Values parameter pack is instantiated - with the argument pack . ARGUMENT_PACK_ARGS will - be a TREE_VEC containing int, float, and double. */ -DEFTREECODE (TYPE_ARGUMENT_PACK, "type_argument_pack", tcc_type, 0) - -/* Represents an argument pack of values, which can be used either for - non-type template arguments or function call arguments. - - NONTYPE_ARGUMENT_PACK plays precisely the same role as - TYPE_ARGUMENT_PACK, but will be used for packing non-type template - arguments (e.g., "int... Dimensions") or function arguments ("const - Args&... args"). */ -DEFTREECODE (NONTYPE_ARGUMENT_PACK, "nontype_argument_pack", tcc_expression, 1) - -/* Represents a type expression that will be expanded into a list of - types when instantiated with one or more argument packs. - - PACK_EXPANSION_PATTERN retrieves the expansion pattern. This is - the type or expression that we will substitute into with each - argument in an argument pack. - - SET_PACK_EXPANSION_PATTERN sets the expansion pattern. - - PACK_EXPANSION_PARAMETER_PACKS contains a TREE_LIST of the parameter - packs that are used in this pack expansion. - - Example: - template - struct tied : tuple { - // ... - }; - - The derivation from tuple contains a TYPE_PACK_EXPANSION for the - template arguments. Its PACK_EXPANSION_PATTERN is "Values&" and its - PACK_EXPANSION_PARAMETER_PACKS will contain "Values". */ -DEFTREECODE (TYPE_PACK_EXPANSION, "type_pack_expansion", tcc_type, 0) - -/* Represents an expression that will be expanded into a list of - expressions when instantiated with one or more argument packs. - - EXPR_PACK_EXPANSION plays precisely the same role as TYPE_PACK_EXPANSION, - but will be used for expressions. */ -DEFTREECODE (EXPR_PACK_EXPANSION, "expr_pack_expansion", tcc_expression, 3) - -/* Selects the Ith parameter out of an argument pack. This node will - be used when instantiating pack expansions; see - tsubst_pack_expansion. - - ARGUMENT_PACK_SELECT_FROM_PACK contains the *_ARGUMENT_PACK node - from which the argument will be selected. - - ARGUMENT_PACK_SELECT_INDEX contains the index into the argument - pack that will be returned by this ARGUMENT_PACK_SELECT node. The - index is a machine integer. */ -DEFTREECODE (ARGUMENT_PACK_SELECT, "argument_pack_select", tcc_exceptional, 0) - -/** C++ extensions. */ - -/* Represents a trait expression during template expansion. */ -DEFTREECODE (TRAIT_EXPR, "trait_expr", tcc_exceptional, 0) - -/* A lambda expression. This is a C++0x extension. - LAMBDA_EXPR_DEFAULT_CAPTURE_MODE is an enum for the default, which may be - none. - LAMBDA_EXPR_CAPTURE_LIST holds the capture-list, including `this'. - LAMBDA_EXPR_THIS_CAPTURE goes straight to the capture of `this', if it exists. - LAMBDA_EXPR_PENDING_PROXIES is a vector of capture proxies which need to - be pushed once scope returns to the lambda. - LAMBDA_EXPR_MUTABLE_P signals whether this lambda was declared mutable. - LAMBDA_EXPR_RETURN_TYPE holds the return type, if it was specified. */ -DEFTREECODE (LAMBDA_EXPR, "lambda_expr", tcc_exceptional, 0) - -/* The declared type of an expression. This is a C++0x extension. - DECLTYPE_TYPE_EXPR is the expression whose type we are computing. - DECLTYPE_TYPE_ID_EXPR_OR_MEMBER_ACCESS_P states whether the - expression was parsed as an id-expression or a member access - expression. When false, it was parsed as a full expression. - DECLTYPE_FOR_LAMBDA_CAPTURE is set if we want lambda capture semantics. - DECLTYPE_FOR_LAMBDA_RETURN is set if we want lambda return deduction. */ -DEFTREECODE (DECLTYPE_TYPE, "decltype_type", tcc_type, 0) - -/* A type designated by `__underlying_type (type)'. - UNDERLYING_TYPE_TYPE is the type in question. */ -DEFTREECODE (UNDERLYING_TYPE, "underlying_type", tcc_type, 0) - -/* A type designated by one of the bases type traits. - BASES_TYPE is the type in question. */ -DEFTREECODE (BASES, "bases", tcc_type, 0) - -/* Used to represent the template information stored by template - specializations. - The accessors are: - TI_TEMPLATE the template declaration associated to the specialization - TI_ARGS the arguments of the template specialization - TI_TYPEDEFS_NEEDING_ACCESS_CHECKING the vector of typedefs used in - the pattern of the template for which access check is needed at template - instantiation time. */ -DEFTREECODE (TEMPLATE_INFO, "template_info", tcc_exceptional, 0) - -/* -Local variables: -mode:c -End: -*/ diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/cp/cp-tree.h b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/cp/cp-tree.h deleted file mode 100644 index cb92704..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/cp/cp-tree.h +++ /dev/null @@ -1,6444 +0,0 @@ -/* Definitions for C++ parsing and type checking. - Copyright (C) 1987-2015 Free Software Foundation, Inc. - Contributed by Michael Tiemann (tiemann@cygnus.com) - -This file is part of GCC. - -GCC is free software; you can redistribute it and/or modify -it under the terms of the GNU General Public License as published by -the Free Software Foundation; either version 3, or (at your option) -any later version. - -GCC is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU General Public License for more details. - -You should have received a copy of the GNU General Public License -along with GCC; see the file COPYING3. If not see -. */ - -#ifndef GCC_CP_TREE_H -#define GCC_CP_TREE_H - -#include "ggc.h" -#include "hashtab.h" -#include "hash-set.h" -#include "vec.h" -#include "machmode.h" -#include "tm.h" -#include "hard-reg-set.h" -#include "input.h" -#include "function.h" -#include "hash-map.h" - -/* In order for the format checking to accept the C++ front end - diagnostic framework extensions, you must include this file before - diagnostic-core.h, not after. We override the definition of GCC_DIAG_STYLE - in c-common.h. */ -#undef GCC_DIAG_STYLE -#define GCC_DIAG_STYLE __gcc_cxxdiag__ -#if defined(GCC_DIAGNOSTIC_CORE_H) || defined (GCC_C_COMMON_H) -#error \ -In order for the format checking to accept the C++ front end diagnostic \ -framework extensions, you must include this file before diagnostic-core.h and \ -c-common.h, not after. -#endif -#include "c-family/c-common.h" -#include "diagnostic.h" - -#include "name-lookup.h" - -/* Usage of TREE_LANG_FLAG_?: - 0: IDENTIFIER_MARKED (IDENTIFIER_NODEs) - NEW_EXPR_USE_GLOBAL (in NEW_EXPR). - DELETE_EXPR_USE_GLOBAL (in DELETE_EXPR). - COMPOUND_EXPR_OVERLOADED (in COMPOUND_EXPR). - CLEANUP_P (in TRY_BLOCK) - AGGR_INIT_VIA_CTOR_P (in AGGR_INIT_EXPR) - PTRMEM_OK_P (in ADDR_EXPR, OFFSET_REF, SCOPE_REF) - PAREN_STRING_LITERAL (in STRING_CST) - DECL_GNU_TLS_P (in VAR_DECL) - KOENIG_LOOKUP_P (in CALL_EXPR) - STATEMENT_LIST_NO_SCOPE (in STATEMENT_LIST). - EXPR_STMT_STMT_EXPR_RESULT (in EXPR_STMT) - STMT_EXPR_NO_SCOPE (in STMT_EXPR) - BIND_EXPR_TRY_BLOCK (in BIND_EXPR) - TYPENAME_IS_ENUM_P (in TYPENAME_TYPE) - OMP_FOR_GIMPLIFYING_P (in OMP_FOR, OMP_SIMD and OMP_DISTRIBUTE) - BASELINK_QUALIFIED_P (in BASELINK) - TARGET_EXPR_IMPLICIT_P (in TARGET_EXPR) - TEMPLATE_PARM_PARAMETER_PACK (in TEMPLATE_PARM_INDEX) - TREE_INDIRECT_USING (in a TREE_LIST of using-directives) - ATTR_IS_DEPENDENT (in the TREE_LIST for an attribute) - ABI_TAG_IMPLICIT (in the TREE_LIST for the argument of abi_tag) - CONSTRUCTOR_IS_DIRECT_INIT (in CONSTRUCTOR) - LAMBDA_EXPR_CAPTURES_THIS_P (in LAMBDA_EXPR) - DECLTYPE_FOR_LAMBDA_CAPTURE (in DECLTYPE_TYPE) - VEC_INIT_EXPR_IS_CONSTEXPR (in VEC_INIT_EXPR) - DECL_OVERRIDE_P (in FUNCTION_DECL) - IMPLICIT_CONV_EXPR_DIRECT_INIT (in IMPLICIT_CONV_EXPR) - TRANSACTION_EXPR_IS_STMT (in TRANSACTION_EXPR) - CONVERT_EXPR_VBASE_PATH (in CONVERT_EXPR) - OVL_ARG_DEPENDENT (in OVERLOAD) - PACK_EXPANSION_LOCAL_P (in *_PACK_EXPANSION) - TINFO_HAS_ACCESS_ERRORS (in TEMPLATE_INFO) - SIZEOF_EXPR_TYPE_P (in SIZEOF_EXPR) - BLOCK_OUTER_CURLY_BRACE_P (in BLOCK) - 1: IDENTIFIER_VIRTUAL_P (in IDENTIFIER_NODE) - TI_PENDING_TEMPLATE_FLAG. - TEMPLATE_PARMS_FOR_INLINE. - DELETE_EXPR_USE_VEC (in DELETE_EXPR). - (TREE_CALLS_NEW) (in _EXPR or _REF) (commented-out). - ICS_ELLIPSIS_FLAG (in _CONV) - DECL_INITIALIZED_P (in VAR_DECL) - TYPENAME_IS_CLASS_P (in TYPENAME_TYPE) - STMT_IS_FULL_EXPR_P (in _STMT) - TARGET_EXPR_LIST_INIT_P (in TARGET_EXPR) - LAMBDA_EXPR_MUTABLE_P (in LAMBDA_EXPR) - DECL_FINAL_P (in FUNCTION_DECL) - QUALIFIED_NAME_IS_TEMPLATE (in SCOPE_REF) - DECLTYPE_FOR_INIT_CAPTURE (in DECLTYPE_TYPE) - CONSTRUCTOR_NO_IMPLICIT_ZERO (in CONSTRUCTOR) - TINFO_USED_TEMPLATE_ID (in TEMPLATE_INFO) - PACK_EXPANSION_SIZEOF_P (in *_PACK_EXPANSION) - 2: IDENTIFIER_OPNAME_P (in IDENTIFIER_NODE) - ICS_THIS_FLAG (in _CONV) - DECL_INITIALIZED_BY_CONSTANT_EXPRESSION_P (in VAR_DECL) - STATEMENT_LIST_TRY_BLOCK (in STATEMENT_LIST) - TYPENAME_IS_RESOLVING_P (in TYPE_NAME_TYPE) - TARGET_EXPR_DIRECT_INIT_P (in TARGET_EXPR) - FNDECL_USED_AUTO (in FUNCTION_DECL) - DECLTYPE_FOR_LAMBDA_PROXY (in DECLTYPE_TYPE) - REF_PARENTHESIZED_P (in COMPONENT_REF, INDIRECT_REF) - AGGR_INIT_ZERO_FIRST (in AGGR_INIT_EXPR) - CONSTRUCTOR_MUTABLE_POISON (in CONSTRUCTOR) - 3: (TREE_REFERENCE_EXPR) (in NON_LVALUE_EXPR) (commented-out). - ICS_BAD_FLAG (in _CONV) - FN_TRY_BLOCK_P (in TRY_BLOCK) - IDENTIFIER_CTOR_OR_DTOR_P (in IDENTIFIER_NODE) - BIND_EXPR_BODY_BLOCK (in BIND_EXPR) - DECL_NON_TRIVIALLY_INITIALIZED_P (in VAR_DECL) - CALL_EXPR_LIST_INIT_P (in CALL_EXPR, AGGR_INIT_EXPR) - 4: TREE_HAS_CONSTRUCTOR (in INDIRECT_REF, SAVE_EXPR, CONSTRUCTOR, - or FIELD_DECL). - IDENTIFIER_TYPENAME_P (in IDENTIFIER_NODE) - DECL_TINFO_P (in VAR_DECL) - FUNCTION_REF_QUALIFIED (in FUNCTION_TYPE, METHOD_TYPE) - 5: C_IS_RESERVED_WORD (in IDENTIFIER_NODE) - DECL_VTABLE_OR_VTT_P (in VAR_DECL) - FUNCTION_RVALUE_QUALIFIED (in FUNCTION_TYPE, METHOD_TYPE) - 6: IDENTIFIER_REPO_CHOSEN (in IDENTIFIER_NODE) - DECL_CONSTRUCTION_VTABLE_P (in VAR_DECL) - TYPE_MARKED_P (in _TYPE) - RANGE_FOR_IVDEP (in RANGE_FOR_STMT) - - Usage of TYPE_LANG_FLAG_?: - 0: TYPE_DEPENDENT_P - 1: TYPE_HAS_USER_CONSTRUCTOR. - 2: TYPE_HAS_LATE_RETURN_TYPE (in FUNCTION_TYPE, METHOD_TYPE) - TYPE_PTRMEMFUNC_FLAG (in RECORD_TYPE) - 3: TYPE_FOR_JAVA. - 4: TYPE_HAS_NONTRIVIAL_DESTRUCTOR - 5: CLASS_TYPE_P (in RECORD_TYPE and UNION_TYPE) - ENUM_FIXED_UNDERLYING_TYPE_P (in ENUMERAL_TYPE) - AUTO_IS_DECLTYPE (in TEMPLATE_TYPE_PARM) - REFERENCE_VLA_OK (in REFERENCE_TYPE) - 6: TYPE_DEPENDENT_P_VALID - - Usage of DECL_LANG_FLAG_?: - 0: DECL_ERROR_REPORTED (in VAR_DECL). - DECL_TEMPLATE_PARM_P (in PARM_DECL, CONST_DECL, TYPE_DECL, or TEMPLATE_DECL) - DECL_LOCAL_FUNCTION_P (in FUNCTION_DECL) - DECL_MUTABLE_P (in FIELD_DECL) - DECL_DEPENDENT_P (in USING_DECL) - LABEL_DECL_BREAK (in LABEL_DECL) - 1: C_TYPEDEF_EXPLICITLY_SIGNED (in TYPE_DECL). - DECL_TEMPLATE_INSTANTIATED (in a VAR_DECL or a FUNCTION_DECL) - DECL_MEMBER_TEMPLATE_P (in TEMPLATE_DECL) - USING_DECL_TYPENAME_P (in USING_DECL) - DECL_VLA_CAPTURE_P (in FIELD_DECL) - DECL_ARRAY_PARAMETER_P (in PARM_DECL) - LABEL_DECL_CONTINUE (in LABEL_DECL) - 2: DECL_THIS_EXTERN (in VAR_DECL or FUNCTION_DECL). - DECL_IMPLICIT_TYPEDEF_P (in a TYPE_DECL) - TEMPLATE_DECL_COMPLEX_ALIAS_P (in TEMPLATE_DECL) - 3: DECL_IN_AGGR_P. - 4: DECL_C_BIT_FIELD (in a FIELD_DECL) - DECL_ANON_UNION_VAR_P (in a VAR_DECL) - DECL_SELF_REFERENCE_P (in a TYPE_DECL) - DECL_INVALID_OVERRIDER_P (in a FUNCTION_DECL) - 5: DECL_INTERFACE_KNOWN. - 6: DECL_THIS_STATIC (in VAR_DECL or FUNCTION_DECL). - DECL_FIELD_IS_BASE (in FIELD_DECL) - TYPE_DECL_ALIAS_P (in TYPE_DECL) - 7: DECL_DEAD_FOR_LOCAL (in VAR_DECL). - DECL_THUNK_P (in a member FUNCTION_DECL) - DECL_NORMAL_CAPTURE_P (in FIELD_DECL) - 8: DECL_DECLARED_CONSTEXPR_P (in VAR_DECL, FUNCTION_DECL) - - Usage of language-independent fields in a language-dependent manner: - - TYPE_ALIAS_SET - This field is used by TYPENAME_TYPEs, TEMPLATE_TYPE_PARMs, and so - forth as a substitute for the mark bits provided in `lang_type'. - At present, only the six low-order bits are used. - - TYPE_LANG_SLOT_1 - For an ENUMERAL_TYPE, this is ENUM_TEMPLATE_INFO. - For a FUNCTION_TYPE or METHOD_TYPE, this is TYPE_RAISES_EXCEPTIONS - - BINFO_VIRTUALS - For a binfo, this is a TREE_LIST. There is an entry for each - virtual function declared either in BINFO or its direct and - indirect primary bases. - - The BV_DELTA of each node gives the amount by which to adjust the - `this' pointer when calling the function. If the method is an - overridden version of a base class method, then it is assumed - that, prior to adjustment, the this pointer points to an object - of the base class. - - The BV_VCALL_INDEX of each node, if non-NULL, gives the vtable - index of the vcall offset for this entry. - - The BV_FN is the declaration for the virtual function itself. - - If BV_LOST_PRIMARY is set, it means that this entry is for a lost - primary virtual base and can be left null in the vtable. - - BINFO_VTABLE - This is an expression with POINTER_TYPE that gives the value - to which the vptr should be initialized. Use get_vtbl_decl_for_binfo - to extract the VAR_DECL for the complete vtable. - - DECL_VINDEX - This field is NULL for a non-virtual function. For a virtual - function, it is eventually set to an INTEGER_CST indicating the - index in the vtable at which this function can be found. When - a virtual function is declared, but before it is known what - function is overridden, this field is the error_mark_node. - - Temporarily, it may be set to a TREE_LIST whose TREE_VALUE is - the virtual function this one overrides, and whose TREE_CHAIN is - the old DECL_VINDEX. */ - -/* Language-specific tree checkers. */ - -#define VAR_OR_FUNCTION_DECL_CHECK(NODE) \ - TREE_CHECK2(NODE,VAR_DECL,FUNCTION_DECL) - -#define TYPE_FUNCTION_OR_TEMPLATE_DECL_CHECK(NODE) \ - TREE_CHECK3(NODE,TYPE_DECL,TEMPLATE_DECL,FUNCTION_DECL) - -#define TYPE_FUNCTION_OR_TEMPLATE_DECL_P(NODE) \ - (TREE_CODE (NODE) == TYPE_DECL || TREE_CODE (NODE) == TEMPLATE_DECL \ - || TREE_CODE (NODE) == FUNCTION_DECL) - -#define VAR_FUNCTION_OR_PARM_DECL_CHECK(NODE) \ - TREE_CHECK3(NODE,VAR_DECL,FUNCTION_DECL,PARM_DECL) - -#define VAR_TEMPL_TYPE_OR_FUNCTION_DECL_CHECK(NODE) \ - TREE_CHECK4(NODE,VAR_DECL,FUNCTION_DECL,TYPE_DECL,TEMPLATE_DECL) - -#define VAR_TEMPL_TYPE_FIELD_OR_FUNCTION_DECL_CHECK(NODE) \ - TREE_CHECK5(NODE,VAR_DECL,FIELD_DECL,FUNCTION_DECL,TYPE_DECL,TEMPLATE_DECL) - -#define BOUND_TEMPLATE_TEMPLATE_PARM_TYPE_CHECK(NODE) \ - TREE_CHECK(NODE,BOUND_TEMPLATE_TEMPLATE_PARM) - -#if defined ENABLE_TREE_CHECKING && (GCC_VERSION >= 2007) -#define THUNK_FUNCTION_CHECK(NODE) __extension__ \ -({ __typeof (NODE) const __t = (NODE); \ - if (TREE_CODE (__t) != FUNCTION_DECL || !__t->decl_common.lang_specific \ - || !__t->decl_common.lang_specific->u.fn.thunk_p) \ - tree_check_failed (__t, __FILE__, __LINE__, __FUNCTION__, 0); \ - __t; }) -#else -#define THUNK_FUNCTION_CHECK(NODE) (NODE) -#endif - -/* Language-dependent contents of an identifier. */ - -struct GTY(()) lang_identifier { - struct c_common_identifier c_common; - cxx_binding *namespace_bindings; - cxx_binding *bindings; - tree class_template_info; - tree label_value; -}; - -/* Return a typed pointer version of T if it designates a - C++ front-end identifier. */ -inline lang_identifier* -identifier_p (tree t) -{ - if (TREE_CODE (t) == IDENTIFIER_NODE) - return (lang_identifier*) t; - return NULL; -} - -/* In an IDENTIFIER_NODE, nonzero if this identifier is actually a - keyword. C_RID_CODE (node) is then the RID_* value of the keyword, - and C_RID_YYCODE is the token number wanted by Yacc. */ - -#define C_IS_RESERVED_WORD(ID) TREE_LANG_FLAG_5 (ID) - -#define LANG_IDENTIFIER_CAST(NODE) \ - ((struct lang_identifier*)IDENTIFIER_NODE_CHECK (NODE)) - -struct GTY(()) template_parm_index_s { - struct tree_common common; - int index; - int level; - int orig_level; - tree decl; -}; -typedef struct template_parm_index_s template_parm_index; - -struct GTY(()) ptrmem_cst { - struct tree_common common; - tree member; -}; -typedef struct ptrmem_cst * ptrmem_cst_t; - -#define IDENTIFIER_GLOBAL_VALUE(NODE) \ - namespace_binding ((NODE), global_namespace) -#define SET_IDENTIFIER_GLOBAL_VALUE(NODE, VAL) \ - set_namespace_binding ((NODE), global_namespace, (VAL)) -#define IDENTIFIER_NAMESPACE_VALUE(NODE) \ - namespace_binding ((NODE), current_namespace) -#define SET_IDENTIFIER_NAMESPACE_VALUE(NODE, VAL) \ - set_namespace_binding ((NODE), current_namespace, (VAL)) - -#define CLEANUP_P(NODE) TREE_LANG_FLAG_0 (TRY_BLOCK_CHECK (NODE)) - -#define BIND_EXPR_TRY_BLOCK(NODE) \ - TREE_LANG_FLAG_0 (BIND_EXPR_CHECK (NODE)) - -/* Used to mark the block around the member initializers and cleanups. */ -#define BIND_EXPR_BODY_BLOCK(NODE) \ - TREE_LANG_FLAG_3 (BIND_EXPR_CHECK (NODE)) -#define FUNCTION_NEEDS_BODY_BLOCK(NODE) \ - (DECL_CONSTRUCTOR_P (NODE) || DECL_DESTRUCTOR_P (NODE) \ - || LAMBDA_FUNCTION_P (NODE)) - -#define STATEMENT_LIST_NO_SCOPE(NODE) \ - TREE_LANG_FLAG_0 (STATEMENT_LIST_CHECK (NODE)) -#define STATEMENT_LIST_TRY_BLOCK(NODE) \ - TREE_LANG_FLAG_2 (STATEMENT_LIST_CHECK (NODE)) - -/* Mark the outer curly brace BLOCK. */ -#define BLOCK_OUTER_CURLY_BRACE_P(NODE) TREE_LANG_FLAG_0 (BLOCK_CHECK (NODE)) - -/* Nonzero if this statement should be considered a full-expression, - i.e., if temporaries created during this statement should have - their destructors run at the end of this statement. */ -#define STMT_IS_FULL_EXPR_P(NODE) TREE_LANG_FLAG_1 ((NODE)) - -/* Marks the result of a statement expression. */ -#define EXPR_STMT_STMT_EXPR_RESULT(NODE) \ - TREE_LANG_FLAG_0 (EXPR_STMT_CHECK (NODE)) - -/* Nonzero if this statement-expression does not have an associated scope. */ -#define STMT_EXPR_NO_SCOPE(NODE) \ - TREE_LANG_FLAG_0 (STMT_EXPR_CHECK (NODE)) - -/* Returns nonzero iff TYPE1 and TYPE2 are the same type, in the usual - sense of `same'. */ -#define same_type_p(TYPE1, TYPE2) \ - comptypes ((TYPE1), (TYPE2), COMPARE_STRICT) - -/* Returns nonzero iff NODE is a declaration for the global function - `main'. */ -#define DECL_MAIN_P(NODE) \ - (DECL_EXTERN_C_FUNCTION_P (NODE) \ - && DECL_NAME (NODE) != NULL_TREE \ - && MAIN_NAME_P (DECL_NAME (NODE)) \ - && flag_hosted) - -/* The overloaded FUNCTION_DECL. */ -#define OVL_FUNCTION(NODE) \ - (((struct tree_overload*)OVERLOAD_CHECK (NODE))->function) -#define OVL_CHAIN(NODE) TREE_CHAIN (NODE) -/* Polymorphic access to FUNCTION and CHAIN. */ -#define OVL_CURRENT(NODE) \ - ((TREE_CODE (NODE) == OVERLOAD) ? OVL_FUNCTION (NODE) : (NODE)) -#define OVL_NEXT(NODE) \ - ((TREE_CODE (NODE) == OVERLOAD) ? TREE_CHAIN (NODE) : NULL_TREE) -/* If set, this was imported in a using declaration. - This is not to confuse with being used somewhere, which - is not important for this node. */ -#define OVL_USED(NODE) TREE_USED (OVERLOAD_CHECK (NODE)) -/* If set, this OVERLOAD was created for argument-dependent lookup - and can be freed afterward. */ -#define OVL_ARG_DEPENDENT(NODE) TREE_LANG_FLAG_0 (OVERLOAD_CHECK (NODE)) - -struct GTY(()) tree_overload { - struct tree_common common; - tree function; -}; - -struct GTY(()) tree_template_decl { - struct tree_decl_common common; - tree arguments; - tree result; -}; - -/* Returns true iff NODE is a BASELINK. */ -#define BASELINK_P(NODE) \ - (TREE_CODE (NODE) == BASELINK) -/* The BINFO indicating the base in which lookup found the - BASELINK_FUNCTIONS. */ -#define BASELINK_BINFO(NODE) \ - (((struct tree_baselink*) BASELINK_CHECK (NODE))->binfo) -/* The functions referred to by the BASELINK; either a FUNCTION_DECL, - a TEMPLATE_DECL, an OVERLOAD, or a TEMPLATE_ID_EXPR. */ -#define BASELINK_FUNCTIONS(NODE) \ - (((struct tree_baselink*) BASELINK_CHECK (NODE))->functions) -/* The BINFO in which the search for the functions indicated by this baselink - began. This base is used to determine the accessibility of functions - selected by overload resolution. */ -#define BASELINK_ACCESS_BINFO(NODE) \ - (((struct tree_baselink*) BASELINK_CHECK (NODE))->access_binfo) -/* For a type-conversion operator, the BASELINK_OPTYPE indicates the type - to which the conversion should occur. This value is important if - the BASELINK_FUNCTIONS include a template conversion operator -- - the BASELINK_OPTYPE can be used to determine what type the user - requested. */ -#define BASELINK_OPTYPE(NODE) \ - (TREE_CHAIN (BASELINK_CHECK (NODE))) -/* Nonzero if this baselink was from a qualified lookup. */ -#define BASELINK_QUALIFIED_P(NODE) \ - TREE_LANG_FLAG_0 (BASELINK_CHECK (NODE)) - -struct GTY(()) tree_baselink { - struct tree_common common; - tree binfo; - tree functions; - tree access_binfo; -}; - -/* The different kinds of ids that we encounter. */ - -typedef enum cp_id_kind -{ - /* Not an id at all. */ - CP_ID_KIND_NONE, - /* An unqualified-id that is not a template-id. */ - CP_ID_KIND_UNQUALIFIED, - /* An unqualified-id that is a dependent name. */ - CP_ID_KIND_UNQUALIFIED_DEPENDENT, - /* An unqualified template-id. */ - CP_ID_KIND_TEMPLATE_ID, - /* A qualified-id. */ - CP_ID_KIND_QUALIFIED -} cp_id_kind; - - -/* The various kinds of C++0x warnings we encounter. */ - -typedef enum cpp0x_warn_str -{ - /* extended initializer lists */ - CPP0X_INITIALIZER_LISTS, - /* explicit conversion operators */ - CPP0X_EXPLICIT_CONVERSION, - /* variadic templates */ - CPP0X_VARIADIC_TEMPLATES, - /* lambda expressions */ - CPP0X_LAMBDA_EXPR, - /* C++0x auto */ - CPP0X_AUTO, - /* scoped enums */ - CPP0X_SCOPED_ENUMS, - /* defaulted and deleted functions */ - CPP0X_DEFAULTED_DELETED, - /* inline namespaces */ - CPP0X_INLINE_NAMESPACES, - /* override controls, override/final */ - CPP0X_OVERRIDE_CONTROLS, - /* non-static data member initializers */ - CPP0X_NSDMI, - /* user defined literals */ - CPP0X_USER_DEFINED_LITERALS, - /* delegating constructors */ - CPP0X_DELEGATING_CTORS, - /* inheriting constructors */ - CPP0X_INHERITING_CTORS, - /* C++11 attributes */ - CPP0X_ATTRIBUTES, - /* ref-qualified member functions */ - CPP0X_REF_QUALIFIER -} cpp0x_warn_str; - -/* The various kinds of operation used by composite_pointer_type. */ - -typedef enum composite_pointer_operation -{ - /* comparison */ - CPO_COMPARISON, - /* conversion */ - CPO_CONVERSION, - /* conditional expression */ - CPO_CONDITIONAL_EXPR -} composite_pointer_operation; - -/* Possible cases of expression list used by build_x_compound_expr_from_list. */ -typedef enum expr_list_kind { - ELK_INIT, /* initializer */ - ELK_MEM_INIT, /* member initializer */ - ELK_FUNC_CAST /* functional cast */ -} expr_list_kind; - -/* Possible cases of implicit bad rhs conversions. */ -typedef enum impl_conv_rhs { - ICR_DEFAULT_ARGUMENT, /* default argument */ - ICR_CONVERTING, /* converting */ - ICR_INIT, /* initialization */ - ICR_ARGPASS, /* argument passing */ - ICR_RETURN, /* return */ - ICR_ASSIGN /* assignment */ -} impl_conv_rhs; - -/* Possible cases of implicit or explicit bad conversions to void. */ -typedef enum impl_conv_void { - ICV_CAST, /* (explicit) conversion to void */ - ICV_SECOND_OF_COND, /* second operand of conditional expression */ - ICV_THIRD_OF_COND, /* third operand of conditional expression */ - ICV_RIGHT_OF_COMMA, /* right operand of comma operator */ - ICV_LEFT_OF_COMMA, /* left operand of comma operator */ - ICV_STATEMENT, /* statement */ - ICV_THIRD_IN_FOR /* for increment expression */ -} impl_conv_void; - -/* Possible invalid uses of an abstract class that might not have a - specific associated declaration. */ -typedef enum abstract_class_use { - ACU_UNKNOWN, /* unknown or decl provided */ - ACU_CAST, /* cast to abstract class */ - ACU_NEW, /* new-expression of abstract class */ - ACU_THROW, /* throw-expression of abstract class */ - ACU_CATCH, /* catch-parameter of abstract class */ - ACU_ARRAY, /* array of abstract class */ - ACU_RETURN, /* return type of abstract class */ - ACU_PARM /* parameter type of abstract class */ -} abstract_class_use; - -/* Macros for access to language-specific slots in an identifier. */ - -#define IDENTIFIER_NAMESPACE_BINDINGS(NODE) \ - (LANG_IDENTIFIER_CAST (NODE)->namespace_bindings) -#define IDENTIFIER_TEMPLATE(NODE) \ - (LANG_IDENTIFIER_CAST (NODE)->class_template_info) - -/* The IDENTIFIER_BINDING is the innermost cxx_binding for the - identifier. It's PREVIOUS is the next outermost binding. Each - VALUE field is a DECL for the associated declaration. Thus, - name lookup consists simply of pulling off the node at the front - of the list (modulo oddities for looking up the names of types, - and such.) You can use SCOPE field to determine the scope - that bound the name. */ -#define IDENTIFIER_BINDING(NODE) \ - (LANG_IDENTIFIER_CAST (NODE)->bindings) - -/* TREE_TYPE only indicates on local and class scope the current - type. For namespace scope, the presence of a type in any namespace - is indicated with global_type_node, and the real type behind must - be found through lookup. */ -#define IDENTIFIER_TYPE_VALUE(NODE) identifier_type_value (NODE) -#define REAL_IDENTIFIER_TYPE_VALUE(NODE) TREE_TYPE (NODE) -#define SET_IDENTIFIER_TYPE_VALUE(NODE,TYPE) (TREE_TYPE (NODE) = (TYPE)) -#define IDENTIFIER_HAS_TYPE_VALUE(NODE) (IDENTIFIER_TYPE_VALUE (NODE) ? 1 : 0) - -#define IDENTIFIER_LABEL_VALUE(NODE) \ - (LANG_IDENTIFIER_CAST (NODE)->label_value) -#define SET_IDENTIFIER_LABEL_VALUE(NODE, VALUE) \ - IDENTIFIER_LABEL_VALUE (NODE) = (VALUE) - -/* Nonzero if this identifier is used as a virtual function name somewhere - (optimizes searches). */ -#define IDENTIFIER_VIRTUAL_P(NODE) TREE_LANG_FLAG_1 (NODE) - -/* Nonzero if this identifier is the prefix for a mangled C++ operator - name. */ -#define IDENTIFIER_OPNAME_P(NODE) TREE_LANG_FLAG_2 (NODE) - -/* Nonzero if this identifier is the name of a type-conversion - operator. */ -#define IDENTIFIER_TYPENAME_P(NODE) \ - TREE_LANG_FLAG_4 (NODE) - -/* Nonzero if this identifier is the name of a constructor or - destructor. */ -#define IDENTIFIER_CTOR_OR_DTOR_P(NODE) \ - TREE_LANG_FLAG_3 (NODE) - -/* True iff NAME is the DECL_ASSEMBLER_NAME for an entity with vague - linkage which the prelinker has assigned to this translation - unit. */ -#define IDENTIFIER_REPO_CHOSEN(NAME) \ - (TREE_LANG_FLAG_6 (NAME)) - -/* In a RECORD_TYPE or UNION_TYPE, nonzero if any component is read-only. */ -#define C_TYPE_FIELDS_READONLY(TYPE) \ - (LANG_TYPE_CLASS_CHECK (TYPE)->fields_readonly) - -/* The tokens stored in the default argument. */ - -#define DEFARG_TOKENS(NODE) \ - (((struct tree_default_arg *)DEFAULT_ARG_CHECK (NODE))->tokens) -#define DEFARG_INSTANTIATIONS(NODE) \ - (((struct tree_default_arg *)DEFAULT_ARG_CHECK (NODE))->instantiations) - -struct GTY (()) tree_default_arg { - struct tree_common common; - struct cp_token_cache *tokens; - vec *instantiations; -}; - - -#define DEFERRED_NOEXCEPT_PATTERN(NODE) \ - (((struct tree_deferred_noexcept *)DEFERRED_NOEXCEPT_CHECK (NODE))->pattern) -#define DEFERRED_NOEXCEPT_ARGS(NODE) \ - (((struct tree_deferred_noexcept *)DEFERRED_NOEXCEPT_CHECK (NODE))->args) -#define DEFERRED_NOEXCEPT_SPEC_P(NODE) \ - ((NODE) && (TREE_PURPOSE (NODE)) \ - && (TREE_CODE (TREE_PURPOSE (NODE)) == DEFERRED_NOEXCEPT)) -#define UNEVALUATED_NOEXCEPT_SPEC_P(NODE) \ - (DEFERRED_NOEXCEPT_SPEC_P (NODE) \ - && DEFERRED_NOEXCEPT_PATTERN (TREE_PURPOSE (NODE)) == NULL_TREE) - -struct GTY (()) tree_deferred_noexcept { - struct tree_base base; - tree pattern; - tree args; -}; - - -/* The condition associated with the static assertion. This must be - an integral constant expression. */ -#define STATIC_ASSERT_CONDITION(NODE) \ - (((struct tree_static_assert *)STATIC_ASSERT_CHECK (NODE))->condition) - -/* The message associated with the static assertion. This must be a - string constant, which will be emitted as an error message when the - static assert condition is false. */ -#define STATIC_ASSERT_MESSAGE(NODE) \ - (((struct tree_static_assert *)STATIC_ASSERT_CHECK (NODE))->message) - -/* Source location information for a static assertion. */ -#define STATIC_ASSERT_SOURCE_LOCATION(NODE) \ - (((struct tree_static_assert *)STATIC_ASSERT_CHECK (NODE))->location) - -struct GTY (()) tree_static_assert { - struct tree_common common; - tree condition; - tree message; - location_t location; -}; - -struct GTY (()) tree_argument_pack_select { - struct tree_common common; - tree argument_pack; - int index; -}; - -/* The different kinds of traits that we encounter. */ - -typedef enum cp_trait_kind -{ - CPTK_BASES, - CPTK_DIRECT_BASES, - CPTK_HAS_NOTHROW_ASSIGN, - CPTK_HAS_NOTHROW_CONSTRUCTOR, - CPTK_HAS_NOTHROW_COPY, - CPTK_HAS_TRIVIAL_ASSIGN, - CPTK_HAS_TRIVIAL_CONSTRUCTOR, - CPTK_HAS_TRIVIAL_COPY, - CPTK_HAS_TRIVIAL_DESTRUCTOR, - CPTK_HAS_VIRTUAL_DESTRUCTOR, - CPTK_IS_ABSTRACT, - CPTK_IS_BASE_OF, - CPTK_IS_CLASS, - CPTK_IS_EMPTY, - CPTK_IS_ENUM, - CPTK_IS_FINAL, - CPTK_IS_LITERAL_TYPE, - CPTK_IS_POD, - CPTK_IS_POLYMORPHIC, - CPTK_IS_STD_LAYOUT, - CPTK_IS_TRIVIAL, - CPTK_IS_TRIVIALLY_ASSIGNABLE, - CPTK_IS_TRIVIALLY_CONSTRUCTIBLE, - CPTK_IS_TRIVIALLY_COPYABLE, - CPTK_IS_UNION, - CPTK_UNDERLYING_TYPE -} cp_trait_kind; - -/* The types that we are processing. */ -#define TRAIT_EXPR_TYPE1(NODE) \ - (((struct tree_trait_expr *)TRAIT_EXPR_CHECK (NODE))->type1) - -#define TRAIT_EXPR_TYPE2(NODE) \ - (((struct tree_trait_expr *)TRAIT_EXPR_CHECK (NODE))->type2) - -/* The specific trait that we are processing. */ -#define TRAIT_EXPR_KIND(NODE) \ - (((struct tree_trait_expr *)TRAIT_EXPR_CHECK (NODE))->kind) - -struct GTY (()) tree_trait_expr { - struct tree_common common; - tree type1; - tree type2; - enum cp_trait_kind kind; -}; - -/* Based off of TYPE_ANONYMOUS_P. */ -#define LAMBDA_TYPE_P(NODE) \ - (CLASS_TYPE_P (NODE) && CLASSTYPE_LAMBDA_EXPR (NODE)) - -/* Test if FUNCTION_DECL is a lambda function. */ -#define LAMBDA_FUNCTION_P(FNDECL) \ - (DECL_OVERLOADED_OPERATOR_P (FNDECL) == CALL_EXPR \ - && LAMBDA_TYPE_P (CP_DECL_CONTEXT (FNDECL))) - -enum cp_lambda_default_capture_mode_type { - CPLD_NONE, - CPLD_COPY, - CPLD_REFERENCE -}; - -/* The method of default capture, if any. */ -#define LAMBDA_EXPR_DEFAULT_CAPTURE_MODE(NODE) \ - (((struct tree_lambda_expr *)LAMBDA_EXPR_CHECK (NODE))->default_capture_mode) - -/* The capture-list, including `this'. Each capture is stored as a FIELD_DECL - * so that the name, type, and field are all together, whether or not it has - * been added to the lambda's class type. - TREE_LIST: - TREE_PURPOSE: The FIELD_DECL for this capture. - TREE_VALUE: The initializer. This is part of a GNU extension. */ -#define LAMBDA_EXPR_CAPTURE_LIST(NODE) \ - (((struct tree_lambda_expr *)LAMBDA_EXPR_CHECK (NODE))->capture_list) - -/* During parsing of the lambda-introducer, the node in the capture-list - that holds the 'this' capture. During parsing of the body, the - capture proxy for that node. */ -#define LAMBDA_EXPR_THIS_CAPTURE(NODE) \ - (((struct tree_lambda_expr *)LAMBDA_EXPR_CHECK (NODE))->this_capture) - -/* Predicate tracking whether `this' is in the effective capture set. */ -#define LAMBDA_EXPR_CAPTURES_THIS_P(NODE) \ - LAMBDA_EXPR_THIS_CAPTURE(NODE) - -/* Predicate tracking whether the lambda was declared 'mutable'. */ -#define LAMBDA_EXPR_MUTABLE_P(NODE) \ - TREE_LANG_FLAG_1 (LAMBDA_EXPR_CHECK (NODE)) - -/* The return type in the expression. - * NULL_TREE indicates that none was specified. */ -#define LAMBDA_EXPR_RETURN_TYPE(NODE) \ - (((struct tree_lambda_expr *)LAMBDA_EXPR_CHECK (NODE))->return_type) - -/* The source location of the lambda. */ -#define LAMBDA_EXPR_LOCATION(NODE) \ - (((struct tree_lambda_expr *)LAMBDA_EXPR_CHECK (NODE))->locus) - -/* The mangling scope for the lambda: FUNCTION_DECL, PARM_DECL, VAR_DECL, - FIELD_DECL or NULL_TREE. If this is NULL_TREE, we have no linkage. */ -#define LAMBDA_EXPR_EXTRA_SCOPE(NODE) \ - (((struct tree_lambda_expr *)LAMBDA_EXPR_CHECK (NODE))->extra_scope) - -/* If EXTRA_SCOPE, this is the number of the lambda within that scope. */ -#define LAMBDA_EXPR_DISCRIMINATOR(NODE) \ - (((struct tree_lambda_expr *)LAMBDA_EXPR_CHECK (NODE))->discriminator) - -/* During parsing of the lambda, a vector of capture proxies which need - to be pushed once we're done processing a nested lambda. */ -#define LAMBDA_EXPR_PENDING_PROXIES(NODE) \ - (((struct tree_lambda_expr *)LAMBDA_EXPR_CHECK (NODE))->pending_proxies) - -/* The closure type of the lambda. Note that the TREE_TYPE of a - LAMBDA_EXPR is always NULL_TREE, because we need to instantiate the - LAMBDA_EXPR in order to instantiate the type. */ -#define LAMBDA_EXPR_CLOSURE(NODE) \ - (((struct tree_lambda_expr *)LAMBDA_EXPR_CHECK (NODE))->closure) - -struct GTY (()) tree_lambda_expr -{ - struct tree_typed typed; - tree capture_list; - tree this_capture; - tree return_type; - tree extra_scope; - tree closure; - vec *pending_proxies; - location_t locus; - enum cp_lambda_default_capture_mode_type default_capture_mode; - int discriminator; -}; - -/* A (typedef,context,usage location) triplet. - It represents a typedef used through a - context at a given source location. - e.g. - struct foo { - typedef int myint; - }; - - struct bar { - foo::myint v; // #1<-- this location. - }; - - In bar, the triplet will be (myint, foo, #1). - */ -struct GTY(()) qualified_typedef_usage_s { - tree typedef_decl; - tree context; - location_t locus; -}; -typedef struct qualified_typedef_usage_s qualified_typedef_usage_t; - -/* Non-zero if this template specialization has access violations that - should be rechecked when the function is instantiated outside argument - deduction. */ -#define TINFO_HAS_ACCESS_ERRORS(NODE) \ - (TREE_LANG_FLAG_0 (TEMPLATE_INFO_CHECK (NODE))) -#define FNDECL_HAS_ACCESS_ERRORS(NODE) \ - (TINFO_HAS_ACCESS_ERRORS (DECL_TEMPLATE_INFO (NODE))) - -/* Non-zero if this variable template specialization was specified using a - template-id, so it's a partial or full specialization and not a definition - of the member template of a particular class specialization. */ -#define TINFO_USED_TEMPLATE_ID(NODE) \ - (TREE_LANG_FLAG_1 (TEMPLATE_INFO_CHECK (NODE))) - -struct GTY(()) tree_template_info { - struct tree_common common; - vec *typedefs_needing_access_checking; -}; - -enum cp_tree_node_structure_enum { - TS_CP_GENERIC, - TS_CP_IDENTIFIER, - TS_CP_TPI, - TS_CP_PTRMEM, - TS_CP_BINDING, - TS_CP_OVERLOAD, - TS_CP_BASELINK, - TS_CP_TEMPLATE_DECL, - TS_CP_WRAPPER, - TS_CP_DEFAULT_ARG, - TS_CP_DEFERRED_NOEXCEPT, - TS_CP_STATIC_ASSERT, - TS_CP_ARGUMENT_PACK_SELECT, - TS_CP_TRAIT_EXPR, - TS_CP_LAMBDA_EXPR, - TS_CP_TEMPLATE_INFO, - TS_CP_USERDEF_LITERAL, - LAST_TS_CP_ENUM -}; - -/* The resulting tree type. */ -union GTY((desc ("cp_tree_node_structure (&%h)"), - chain_next ("(union lang_tree_node *) c_tree_chain_next (&%h.generic)"))) lang_tree_node { - union tree_node GTY ((tag ("TS_CP_GENERIC"), - desc ("tree_node_structure (&%h)"))) generic; - struct template_parm_index_s GTY ((tag ("TS_CP_TPI"))) tpi; - struct ptrmem_cst GTY ((tag ("TS_CP_PTRMEM"))) ptrmem; - struct tree_overload GTY ((tag ("TS_CP_OVERLOAD"))) overload; - struct tree_baselink GTY ((tag ("TS_CP_BASELINK"))) baselink; - struct tree_template_decl GTY ((tag ("TS_CP_TEMPLATE_DECL"))) template_decl; - struct tree_default_arg GTY ((tag ("TS_CP_DEFAULT_ARG"))) default_arg; - struct tree_deferred_noexcept GTY ((tag ("TS_CP_DEFERRED_NOEXCEPT"))) deferred_noexcept; - struct lang_identifier GTY ((tag ("TS_CP_IDENTIFIER"))) identifier; - struct tree_static_assert GTY ((tag ("TS_CP_STATIC_ASSERT"))) - static_assertion; - struct tree_argument_pack_select GTY ((tag ("TS_CP_ARGUMENT_PACK_SELECT"))) - argument_pack_select; - struct tree_trait_expr GTY ((tag ("TS_CP_TRAIT_EXPR"))) - trait_expression; - struct tree_lambda_expr GTY ((tag ("TS_CP_LAMBDA_EXPR"))) - lambda_expression; - struct tree_template_info GTY ((tag ("TS_CP_TEMPLATE_INFO"))) - template_info; - struct tree_userdef_literal GTY ((tag ("TS_CP_USERDEF_LITERAL"))) - userdef_literal; -}; - - -enum cp_tree_index -{ - CPTI_JAVA_BYTE_TYPE, - CPTI_JAVA_SHORT_TYPE, - CPTI_JAVA_INT_TYPE, - CPTI_JAVA_LONG_TYPE, - CPTI_JAVA_FLOAT_TYPE, - CPTI_JAVA_DOUBLE_TYPE, - CPTI_JAVA_CHAR_TYPE, - CPTI_JAVA_BOOLEAN_TYPE, - - CPTI_WCHAR_DECL, - CPTI_VTABLE_ENTRY_TYPE, - CPTI_DELTA_TYPE, - CPTI_VTABLE_INDEX_TYPE, - CPTI_CLEANUP_TYPE, - CPTI_VTT_PARM_TYPE, - - CPTI_CLASS_TYPE, - CPTI_UNKNOWN_TYPE, - CPTI_INIT_LIST_TYPE, - CPTI_VTBL_TYPE, - CPTI_VTBL_PTR_TYPE, - CPTI_STD, - CPTI_ABI, - CPTI_CONST_TYPE_INFO_TYPE, - CPTI_TYPE_INFO_PTR_TYPE, - CPTI_ABORT_FNDECL, - CPTI_AGGR_TAG, - - CPTI_CTOR_IDENTIFIER, - CPTI_COMPLETE_CTOR_IDENTIFIER, - CPTI_BASE_CTOR_IDENTIFIER, - CPTI_DTOR_IDENTIFIER, - CPTI_COMPLETE_DTOR_IDENTIFIER, - CPTI_BASE_DTOR_IDENTIFIER, - CPTI_DELETING_DTOR_IDENTIFIER, - CPTI_DELTA_IDENTIFIER, - CPTI_IN_CHARGE_IDENTIFIER, - CPTI_VTT_PARM_IDENTIFIER, - CPTI_NELTS_IDENTIFIER, - CPTI_THIS_IDENTIFIER, - CPTI_PFN_IDENTIFIER, - CPTI_VPTR_IDENTIFIER, - CPTI_STD_IDENTIFIER, - - CPTI_LANG_NAME_C, - CPTI_LANG_NAME_CPLUSPLUS, - CPTI_LANG_NAME_JAVA, - - CPTI_EMPTY_EXCEPT_SPEC, - CPTI_NOEXCEPT_TRUE_SPEC, - CPTI_NOEXCEPT_FALSE_SPEC, - CPTI_JCLASS, - CPTI_TERMINATE, - CPTI_CALL_UNEXPECTED, - CPTI_ATEXIT_FN_PTR_TYPE, - CPTI_ATEXIT, - CPTI_DSO_HANDLE, - CPTI_DCAST, - - CPTI_KEYED_CLASSES, - - CPTI_NULLPTR, - CPTI_NULLPTR_TYPE, - - CPTI_MAX -}; - -extern GTY(()) tree cp_global_trees[CPTI_MAX]; - -#define java_byte_type_node cp_global_trees[CPTI_JAVA_BYTE_TYPE] -#define java_short_type_node cp_global_trees[CPTI_JAVA_SHORT_TYPE] -#define java_int_type_node cp_global_trees[CPTI_JAVA_INT_TYPE] -#define java_long_type_node cp_global_trees[CPTI_JAVA_LONG_TYPE] -#define java_float_type_node cp_global_trees[CPTI_JAVA_FLOAT_TYPE] -#define java_double_type_node cp_global_trees[CPTI_JAVA_DOUBLE_TYPE] -#define java_char_type_node cp_global_trees[CPTI_JAVA_CHAR_TYPE] -#define java_boolean_type_node cp_global_trees[CPTI_JAVA_BOOLEAN_TYPE] - -#define wchar_decl_node cp_global_trees[CPTI_WCHAR_DECL] -#define vtable_entry_type cp_global_trees[CPTI_VTABLE_ENTRY_TYPE] -/* The type used to represent an offset by which to adjust the `this' - pointer in pointer-to-member types. */ -#define delta_type_node cp_global_trees[CPTI_DELTA_TYPE] -/* The type used to represent an index into the vtable. */ -#define vtable_index_type cp_global_trees[CPTI_VTABLE_INDEX_TYPE] - -#define class_type_node cp_global_trees[CPTI_CLASS_TYPE] -#define unknown_type_node cp_global_trees[CPTI_UNKNOWN_TYPE] -#define init_list_type_node cp_global_trees[CPTI_INIT_LIST_TYPE] -#define vtbl_type_node cp_global_trees[CPTI_VTBL_TYPE] -#define vtbl_ptr_type_node cp_global_trees[CPTI_VTBL_PTR_TYPE] -#define std_node cp_global_trees[CPTI_STD] -#define abi_node cp_global_trees[CPTI_ABI] -#define const_type_info_type_node cp_global_trees[CPTI_CONST_TYPE_INFO_TYPE] -#define type_info_ptr_type cp_global_trees[CPTI_TYPE_INFO_PTR_TYPE] -#define abort_fndecl cp_global_trees[CPTI_ABORT_FNDECL] -#define current_aggr cp_global_trees[CPTI_AGGR_TAG] -#define nullptr_node cp_global_trees[CPTI_NULLPTR] -#define nullptr_type_node cp_global_trees[CPTI_NULLPTR_TYPE] - -/* We cache these tree nodes so as to call get_identifier less - frequently. */ - -/* The name of a constructor that takes an in-charge parameter to - decide whether or not to construct virtual base classes. */ -#define ctor_identifier cp_global_trees[CPTI_CTOR_IDENTIFIER] -/* The name of a constructor that constructs virtual base classes. */ -#define complete_ctor_identifier cp_global_trees[CPTI_COMPLETE_CTOR_IDENTIFIER] -/* The name of a constructor that does not construct virtual base classes. */ -#define base_ctor_identifier cp_global_trees[CPTI_BASE_CTOR_IDENTIFIER] -/* The name of a destructor that takes an in-charge parameter to - decide whether or not to destroy virtual base classes and whether - or not to delete the object. */ -#define dtor_identifier cp_global_trees[CPTI_DTOR_IDENTIFIER] -/* The name of a destructor that destroys virtual base classes. */ -#define complete_dtor_identifier cp_global_trees[CPTI_COMPLETE_DTOR_IDENTIFIER] -/* The name of a destructor that does not destroy virtual base - classes. */ -#define base_dtor_identifier cp_global_trees[CPTI_BASE_DTOR_IDENTIFIER] -/* The name of a destructor that destroys virtual base classes, and - then deletes the entire object. */ -#define deleting_dtor_identifier cp_global_trees[CPTI_DELETING_DTOR_IDENTIFIER] -#define delta_identifier cp_global_trees[CPTI_DELTA_IDENTIFIER] -#define in_charge_identifier cp_global_trees[CPTI_IN_CHARGE_IDENTIFIER] -/* The name of the parameter that contains a pointer to the VTT to use - for this subobject constructor or destructor. */ -#define vtt_parm_identifier cp_global_trees[CPTI_VTT_PARM_IDENTIFIER] -#define nelts_identifier cp_global_trees[CPTI_NELTS_IDENTIFIER] -#define this_identifier cp_global_trees[CPTI_THIS_IDENTIFIER] -#define pfn_identifier cp_global_trees[CPTI_PFN_IDENTIFIER] -#define vptr_identifier cp_global_trees[CPTI_VPTR_IDENTIFIER] -/* The name of the std namespace. */ -#define std_identifier cp_global_trees[CPTI_STD_IDENTIFIER] -#define lang_name_c cp_global_trees[CPTI_LANG_NAME_C] -#define lang_name_cplusplus cp_global_trees[CPTI_LANG_NAME_CPLUSPLUS] -#define lang_name_java cp_global_trees[CPTI_LANG_NAME_JAVA] - -/* Exception specifier used for throw(). */ -#define empty_except_spec cp_global_trees[CPTI_EMPTY_EXCEPT_SPEC] -#define noexcept_true_spec cp_global_trees[CPTI_NOEXCEPT_TRUE_SPEC] -#define noexcept_false_spec cp_global_trees[CPTI_NOEXCEPT_FALSE_SPEC] - -/* If non-NULL, a POINTER_TYPE equivalent to (java::lang::Class*). */ -#define jclass_node cp_global_trees[CPTI_JCLASS] - -/* The declaration for `std::terminate'. */ -#define terminate_node cp_global_trees[CPTI_TERMINATE] - -/* The declaration for "__cxa_call_unexpected". */ -#define call_unexpected_node cp_global_trees[CPTI_CALL_UNEXPECTED] - -/* The type of the function-pointer argument to "__cxa_atexit" (or - "std::atexit", if "__cxa_atexit" is not being used). */ -#define atexit_fn_ptr_type_node cp_global_trees[CPTI_ATEXIT_FN_PTR_TYPE] - -/* A pointer to `std::atexit'. */ -#define atexit_node cp_global_trees[CPTI_ATEXIT] - -/* A pointer to `__dso_handle'. */ -#define dso_handle_node cp_global_trees[CPTI_DSO_HANDLE] - -/* The declaration of the dynamic_cast runtime. */ -#define dynamic_cast_node cp_global_trees[CPTI_DCAST] - -/* The type of a destructor. */ -#define cleanup_type cp_global_trees[CPTI_CLEANUP_TYPE] - -/* The type of the vtt parameter passed to subobject constructors and - destructors. */ -#define vtt_parm_type cp_global_trees[CPTI_VTT_PARM_TYPE] - -/* A TREE_LIST of the dynamic classes whose vtables may have to be - emitted in this translation unit. */ - -#define keyed_classes cp_global_trees[CPTI_KEYED_CLASSES] - -/* Node to indicate default access. This must be distinct from the - access nodes in tree.h. */ - -#define access_default_node null_node - -/* Global state. */ - -struct GTY(()) saved_scope { - vec *old_bindings; - tree old_namespace; - vec *decl_ns_list; - tree class_name; - tree class_type; - tree access_specifier; - tree function_decl; - vec *lang_base; - tree lang_name; - tree template_parms; - cp_binding_level *x_previous_class_level; - tree x_saved_tree; - - /* Only used for uses of this in trailing return type. */ - tree x_current_class_ptr; - tree x_current_class_ref; - - int x_processing_template_decl; - int x_processing_specialization; - BOOL_BITFIELD x_processing_explicit_instantiation : 1; - BOOL_BITFIELD need_pop_function_context : 1; - - int unevaluated_operand; - int inhibit_evaluation_warnings; - int noexcept_operand; - /* If non-zero, implicit "omp declare target" attribute is added into the - attribute lists. */ - int omp_declare_target_attribute; - - struct stmt_tree_s x_stmt_tree; - - cp_binding_level *class_bindings; - cp_binding_level *bindings; - - hash_map *GTY((skip)) x_local_specializations; - - struct saved_scope *prev; -}; - -extern GTY(()) struct saved_scope *scope_chain; - -/* The current open namespace. */ - -#define current_namespace scope_chain->old_namespace - -/* The stack for namespaces of current declarations. */ - -#define decl_namespace_list scope_chain->decl_ns_list - -/* IDENTIFIER_NODE: name of current class */ - -#define current_class_name scope_chain->class_name - -/* _TYPE: the type of the current class */ - -#define current_class_type scope_chain->class_type - -/* When parsing a class definition, the access specifier most recently - given by the user, or, if no access specifier was given, the - default value appropriate for the kind of class (i.e., struct, - class, or union). */ - -#define current_access_specifier scope_chain->access_specifier - -/* Pointer to the top of the language name stack. */ - -#define current_lang_base scope_chain->lang_base -#define current_lang_name scope_chain->lang_name - -/* When parsing a template declaration, a TREE_LIST represents the - active template parameters. Each node in the list represents one - level of template parameters. The innermost level is first in the - list. The depth of each level is stored as an INTEGER_CST in the - TREE_PURPOSE of each node. The parameters for that level are - stored in the TREE_VALUE. */ - -#define current_template_parms scope_chain->template_parms - -#define processing_template_decl scope_chain->x_processing_template_decl -#define processing_specialization scope_chain->x_processing_specialization -#define processing_explicit_instantiation scope_chain->x_processing_explicit_instantiation - -/* RAII sentinel to handle clearing processing_template_decl and restoring - it when done. */ - -struct processing_template_decl_sentinel -{ - int saved; - processing_template_decl_sentinel (bool reset = true) - : saved (processing_template_decl) - { - if (reset) - processing_template_decl = 0; - } - ~processing_template_decl_sentinel() - { - processing_template_decl = saved; - } -}; - -/* RAII sentinel to disable certain warnings during template substitution - and elsewhere. */ - -struct warning_sentinel -{ - int &flag; - int val; - warning_sentinel(int& flag, bool suppress=true) - : flag(flag), val(flag) { if (suppress) flag = 0; } - ~warning_sentinel() { flag = val; } -}; - -/* The cached class binding level, from the most recently exited - class, or NULL if none. */ - -#define previous_class_level scope_chain->x_previous_class_level - -/* A map from local variable declarations in the body of the template - presently being instantiated to the corresponding instantiated - local variables. */ - -#define local_specializations scope_chain->x_local_specializations - -/* Nonzero if we are parsing the operand of a noexcept operator. */ - -#define cp_noexcept_operand scope_chain->noexcept_operand - -/* A list of private types mentioned, for deferred access checking. */ - -struct GTY((for_user)) cxx_int_tree_map { - unsigned int uid; - tree to; -}; - -struct cxx_int_tree_map_hasher : ggc_hasher -{ - static hashval_t hash (cxx_int_tree_map *); - static bool equal (cxx_int_tree_map *, cxx_int_tree_map *); -}; - -struct named_label_entry; - -struct named_label_hasher : ggc_hasher -{ - static hashval_t hash (named_label_entry *); - static bool equal (named_label_entry *, named_label_entry *); -}; - -/* Global state pertinent to the current function. */ - -struct GTY(()) language_function { - struct c_language_function base; - - tree x_cdtor_label; - tree x_current_class_ptr; - tree x_current_class_ref; - tree x_eh_spec_block; - tree x_in_charge_parm; - tree x_vtt_parm; - tree x_return_value; - tree x_auto_return_pattern; - - BOOL_BITFIELD returns_value : 1; - BOOL_BITFIELD returns_null : 1; - BOOL_BITFIELD returns_abnormally : 1; - BOOL_BITFIELD infinite_loop: 1; - BOOL_BITFIELD x_in_function_try_handler : 1; - BOOL_BITFIELD x_in_base_initializer : 1; - - /* True if this function can throw an exception. */ - BOOL_BITFIELD can_throw : 1; - - BOOL_BITFIELD invalid_constexpr : 1; - - hash_table *x_named_labels; - cp_binding_level *bindings; - vec *x_local_names; - /* Tracking possibly infinite loops. This is a vec only because - vec doesn't work with gtype. */ - vec *infinite_loops; - hash_table *extern_decl_map; -}; - -/* The current C++-specific per-function global variables. */ - -#define cp_function_chain (cfun->language) - -/* In a constructor destructor, the point at which all derived class - destroying/construction has been done. I.e., just before a - constructor returns, or before any base class destroying will be done - in a destructor. */ - -#define cdtor_label cp_function_chain->x_cdtor_label - -/* When we're processing a member function, current_class_ptr is the - PARM_DECL for the `this' pointer. The current_class_ref is an - expression for `*this'. */ - -#define current_class_ptr \ - (*(cfun && cp_function_chain \ - ? &cp_function_chain->x_current_class_ptr \ - : &scope_chain->x_current_class_ptr)) -#define current_class_ref \ - (*(cfun && cp_function_chain \ - ? &cp_function_chain->x_current_class_ref \ - : &scope_chain->x_current_class_ref)) - -/* The EH_SPEC_BLOCK for the exception-specifiers for the current - function, if any. */ - -#define current_eh_spec_block cp_function_chain->x_eh_spec_block - -/* The `__in_chrg' parameter for the current function. Only used for - constructors and destructors. */ - -#define current_in_charge_parm cp_function_chain->x_in_charge_parm - -/* The `__vtt_parm' parameter for the current function. Only used for - constructors and destructors. */ - -#define current_vtt_parm cp_function_chain->x_vtt_parm - -/* Set to 0 at beginning of a function definition, set to 1 if - a return statement that specifies a return value is seen. */ - -#define current_function_returns_value cp_function_chain->returns_value - -/* Set to 0 at beginning of a function definition, set to 1 if - a return statement with no argument is seen. */ - -#define current_function_returns_null cp_function_chain->returns_null - -/* Set to 0 at beginning of a function definition, set to 1 if - a call to a noreturn function is seen. */ - -#define current_function_returns_abnormally \ - cp_function_chain->returns_abnormally - -/* Set to 0 at beginning of a function definition, set to 1 if we see an - obvious infinite loop. This can have false positives and false - negatives, so it should only be used as a heuristic. */ - -#define current_function_infinite_loop cp_function_chain->infinite_loop - -/* Nonzero if we are processing a base initializer. Zero elsewhere. */ -#define in_base_initializer cp_function_chain->x_in_base_initializer - -#define in_function_try_handler cp_function_chain->x_in_function_try_handler - -/* Expression always returned from function, or error_mark_node - otherwise, for use by the automatic named return value optimization. */ - -#define current_function_return_value \ - (cp_function_chain->x_return_value) - -/* A type involving 'auto' to be used for return type deduction. */ - -#define current_function_auto_return_pattern \ - (cp_function_chain->x_auto_return_pattern) - -/* True if NAME is the IDENTIFIER_NODE for an overloaded "operator - new" or "operator delete". */ -#define NEW_DELETE_OPNAME_P(NAME) \ - ((NAME) == ansi_opname (NEW_EXPR) \ - || (NAME) == ansi_opname (VEC_NEW_EXPR) \ - || (NAME) == ansi_opname (DELETE_EXPR) \ - || (NAME) == ansi_opname (VEC_DELETE_EXPR)) - -#define ansi_opname(CODE) \ - (operator_name_info[(int) (CODE)].identifier) -#define ansi_assopname(CODE) \ - (assignment_operator_name_info[(int) (CODE)].identifier) - -/* TRUE if a tree code represents a statement. */ -extern bool statement_code_p[MAX_TREE_CODES]; - -#define STATEMENT_CODE_P(CODE) statement_code_p[(int) (CODE)] - -enum languages { lang_c, lang_cplusplus, lang_java }; - -/* Macros to make error reporting functions' lives easier. */ -#define TYPE_LINKAGE_IDENTIFIER(NODE) \ - (TYPE_IDENTIFIER (TYPE_MAIN_VARIANT (NODE))) -#define TYPE_NAME_STRING(NODE) (IDENTIFIER_POINTER (TYPE_IDENTIFIER (NODE))) -#define TYPE_NAME_LENGTH(NODE) (IDENTIFIER_LENGTH (TYPE_IDENTIFIER (NODE))) - -/* Nonzero if NODE has no name for linkage purposes. */ -#define TYPE_ANONYMOUS_P(NODE) \ - (OVERLOAD_TYPE_P (NODE) && ANON_AGGRNAME_P (TYPE_LINKAGE_IDENTIFIER (NODE))) - -/* The _DECL for this _TYPE. */ -#define TYPE_MAIN_DECL(NODE) (TYPE_STUB_DECL (TYPE_MAIN_VARIANT (NODE))) - -/* Nonzero if T is a type that could resolve to any kind of concrete type - at instantiation time. */ -#define WILDCARD_TYPE_P(T) \ - (TREE_CODE (T) == TEMPLATE_TYPE_PARM \ - || TREE_CODE (T) == TYPENAME_TYPE \ - || TREE_CODE (T) == TYPEOF_TYPE \ - || TREE_CODE (T) == BOUND_TEMPLATE_TEMPLATE_PARM \ - || TREE_CODE (T) == DECLTYPE_TYPE) - -/* Nonzero if T is a class (or struct or union) type. Also nonzero - for template type parameters, typename types, and instantiated - template template parameters. Keep these checks in ascending code - order. */ -#define MAYBE_CLASS_TYPE_P(T) (WILDCARD_TYPE_P (T) || CLASS_TYPE_P (T)) - -/* Set CLASS_TYPE_P for T to VAL. T must be a class, struct, or - union type. */ -#define SET_CLASS_TYPE_P(T, VAL) \ - (TYPE_LANG_FLAG_5 (T) = (VAL)) - -/* Nonzero if T is a class type. Zero for template type parameters, - typename types, and so forth. */ -#define CLASS_TYPE_P(T) \ - (RECORD_OR_UNION_CODE_P (TREE_CODE (T)) && TYPE_LANG_FLAG_5 (T)) - -/* Nonzero if T is a class type but not an union. */ -#define NON_UNION_CLASS_TYPE_P(T) \ - (CLASS_TYPE_P (T) && TREE_CODE (T) != UNION_TYPE) - -/* Keep these checks in ascending code order. */ -#define RECORD_OR_UNION_CODE_P(T) \ - ((T) == RECORD_TYPE || (T) == UNION_TYPE) -#define OVERLOAD_TYPE_P(T) \ - (CLASS_TYPE_P (T) || TREE_CODE (T) == ENUMERAL_TYPE) - -/* True if this a "Java" type, defined in 'extern "Java"'. */ -#define TYPE_FOR_JAVA(NODE) TYPE_LANG_FLAG_3 (NODE) - -/* True if this type is dependent. This predicate is only valid if - TYPE_DEPENDENT_P_VALID is true. */ -#define TYPE_DEPENDENT_P(NODE) TYPE_LANG_FLAG_0 (NODE) - -/* True if dependent_type_p has been called for this type, with the - result that TYPE_DEPENDENT_P is valid. */ -#define TYPE_DEPENDENT_P_VALID(NODE) TYPE_LANG_FLAG_6(NODE) - -/* Nonzero if this type is const-qualified. */ -#define CP_TYPE_CONST_P(NODE) \ - ((cp_type_quals (NODE) & TYPE_QUAL_CONST) != 0) - -/* Nonzero if this type is volatile-qualified. */ -#define CP_TYPE_VOLATILE_P(NODE) \ - ((cp_type_quals (NODE) & TYPE_QUAL_VOLATILE) != 0) - -/* Nonzero if this type is restrict-qualified. */ -#define CP_TYPE_RESTRICT_P(NODE) \ - ((cp_type_quals (NODE) & TYPE_QUAL_RESTRICT) != 0) - -/* Nonzero if this type is const-qualified, but not - volatile-qualified. Other qualifiers are ignored. This macro is - used to test whether or not it is OK to bind an rvalue to a - reference. */ -#define CP_TYPE_CONST_NON_VOLATILE_P(NODE) \ - ((cp_type_quals (NODE) & (TYPE_QUAL_CONST | TYPE_QUAL_VOLATILE)) \ - == TYPE_QUAL_CONST) - -#define FUNCTION_ARG_CHAIN(NODE) \ - TREE_CHAIN (TYPE_ARG_TYPES (TREE_TYPE (NODE))) - -/* Given a FUNCTION_DECL, returns the first TREE_LIST out of TYPE_ARG_TYPES - which refers to a user-written parameter. */ -#define FUNCTION_FIRST_USER_PARMTYPE(NODE) \ - skip_artificial_parms_for ((NODE), TYPE_ARG_TYPES (TREE_TYPE (NODE))) - -/* Similarly, but for DECL_ARGUMENTS. */ -#define FUNCTION_FIRST_USER_PARM(NODE) \ - skip_artificial_parms_for ((NODE), DECL_ARGUMENTS (NODE)) - -/* Nonzero iff TYPE is derived from PARENT. Ignores accessibility and - ambiguity issues. */ -#define DERIVED_FROM_P(PARENT, TYPE) \ - (lookup_base ((TYPE), (PARENT), ba_any, NULL, tf_none) != NULL_TREE) - -/* Gives the visibility specification for a class type. */ -#define CLASSTYPE_VISIBILITY(TYPE) \ - DECL_VISIBILITY (TYPE_MAIN_DECL (TYPE)) -#define CLASSTYPE_VISIBILITY_SPECIFIED(TYPE) \ - DECL_VISIBILITY_SPECIFIED (TYPE_MAIN_DECL (TYPE)) - -typedef struct GTY (()) tree_pair_s { - tree purpose; - tree value; -} tree_pair_s; -typedef tree_pair_s *tree_pair_p; - -/* This is a few header flags for 'struct lang_type'. Actually, - all but the first are used only for lang_type_class; they - are put in this structure to save space. */ -struct GTY(()) lang_type_header { - BOOL_BITFIELD is_lang_type_class : 1; - - BOOL_BITFIELD has_type_conversion : 1; - BOOL_BITFIELD has_copy_ctor : 1; - BOOL_BITFIELD has_default_ctor : 1; - BOOL_BITFIELD const_needs_init : 1; - BOOL_BITFIELD ref_needs_init : 1; - BOOL_BITFIELD has_const_copy_assign : 1; - - BOOL_BITFIELD spare : 1; -}; - -/* This structure provides additional information above and beyond - what is provide in the ordinary tree_type. In the past, we used it - for the types of class types, template parameters types, typename - types, and so forth. However, there can be many (tens to hundreds - of thousands) of template parameter types in a compilation, and - there's no need for this additional information in that case. - Therefore, we now use this data structure only for class types. - - In the past, it was thought that there would be relatively few - class types. However, in the presence of heavy use of templates, - many (i.e., thousands) of classes can easily be generated. - Therefore, we should endeavor to keep the size of this structure to - a minimum. */ -struct GTY(()) lang_type_class { - struct lang_type_header h; - - unsigned char align; - - unsigned has_mutable : 1; - unsigned com_interface : 1; - unsigned non_pod_class : 1; - unsigned nearly_empty_p : 1; - unsigned user_align : 1; - unsigned has_copy_assign : 1; - unsigned has_new : 1; - unsigned has_array_new : 1; - - unsigned gets_delete : 2; - unsigned interface_only : 1; - unsigned interface_unknown : 1; - unsigned contains_empty_class_p : 1; - unsigned anon_aggr : 1; - unsigned non_zero_init : 1; - unsigned empty_p : 1; - - unsigned vec_new_uses_cookie : 1; - unsigned declared_class : 1; - unsigned diamond_shaped : 1; - unsigned repeated_base : 1; - unsigned being_defined : 1; - unsigned java_interface : 1; - unsigned debug_requested : 1; - unsigned fields_readonly : 1; - - unsigned use_template : 2; - unsigned ptrmemfunc_flag : 1; - unsigned was_anonymous : 1; - unsigned lazy_default_ctor : 1; - unsigned lazy_copy_ctor : 1; - unsigned lazy_copy_assign : 1; - unsigned lazy_destructor : 1; - - unsigned has_const_copy_ctor : 1; - unsigned has_complex_copy_ctor : 1; - unsigned has_complex_copy_assign : 1; - unsigned non_aggregate : 1; - unsigned has_complex_dflt : 1; - unsigned has_list_ctor : 1; - unsigned non_std_layout : 1; - unsigned is_literal : 1; - - unsigned lazy_move_ctor : 1; - unsigned lazy_move_assign : 1; - unsigned has_complex_move_ctor : 1; - unsigned has_complex_move_assign : 1; - unsigned has_constexpr_ctor : 1; - - /* When adding a flag here, consider whether or not it ought to - apply to a template instance if it applies to the template. If - so, make sure to copy it in instantiate_class_template! */ - - /* There are some bits left to fill out a 32-bit word. Keep track - of this by updating the size of this bitfield whenever you add or - remove a flag. */ - unsigned dummy : 3; - - tree primary_base; - vec *vcall_indices; - tree vtables; - tree typeinfo_var; - vec *vbases; - binding_table nested_udts; - tree as_base; - vec *pure_virtuals; - tree friend_classes; - vec * GTY((reorder ("resort_type_method_vec"))) methods; - tree key_method; - tree decl_list; - tree template_info; - tree befriending_classes; - /* In a RECORD_TYPE, information specific to Objective-C++, such - as a list of adopted protocols or a pointer to a corresponding - @interface. See objc/objc-act.h for details. */ - tree objc_info; - /* sorted_fields is sorted based on a pointer, so we need to be able - to resort it if pointers get rearranged. */ - struct sorted_fields_type * GTY ((reorder ("resort_sorted_fields"))) - sorted_fields; - /* FIXME reuse another field? */ - tree lambda_expr; -}; - -struct GTY(()) lang_type_ptrmem { - struct lang_type_header h; - tree record; -}; - -struct GTY(()) lang_type { - union lang_type_u - { - struct lang_type_header GTY((skip (""))) h; - struct lang_type_class GTY((tag ("1"))) c; - struct lang_type_ptrmem GTY((tag ("0"))) ptrmem; - } GTY((desc ("%h.h.is_lang_type_class"))) u; -}; - -#if defined ENABLE_TREE_CHECKING && (GCC_VERSION >= 2007) - -#define LANG_TYPE_CLASS_CHECK(NODE) __extension__ \ -({ struct lang_type *lt = TYPE_LANG_SPECIFIC (NODE); \ - if (! lt->u.h.is_lang_type_class) \ - lang_check_failed (__FILE__, __LINE__, __FUNCTION__); \ - <->u.c; }) - -#define LANG_TYPE_PTRMEM_CHECK(NODE) __extension__ \ -({ struct lang_type *lt = TYPE_LANG_SPECIFIC (NODE); \ - if (lt->u.h.is_lang_type_class) \ - lang_check_failed (__FILE__, __LINE__, __FUNCTION__); \ - <->u.ptrmem; }) - -#else - -#define LANG_TYPE_CLASS_CHECK(NODE) (&TYPE_LANG_SPECIFIC (NODE)->u.c) -#define LANG_TYPE_PTRMEM_CHECK(NODE) (&TYPE_LANG_SPECIFIC (NODE)->u.ptrmem) - -#endif /* ENABLE_TREE_CHECKING */ - -/* Nonzero for _CLASSTYPE means that operator delete is defined. */ -#define TYPE_GETS_DELETE(NODE) (LANG_TYPE_CLASS_CHECK (NODE)->gets_delete) -#define TYPE_GETS_REG_DELETE(NODE) (TYPE_GETS_DELETE (NODE) & 1) - -/* Nonzero if `new NODE[x]' should cause the allocation of extra - storage to indicate how many array elements are in use. */ -#define TYPE_VEC_NEW_USES_COOKIE(NODE) \ - (CLASS_TYPE_P (NODE) \ - && LANG_TYPE_CLASS_CHECK (NODE)->vec_new_uses_cookie) - -/* Nonzero means that this _CLASSTYPE node defines ways of converting - itself to other types. */ -#define TYPE_HAS_CONVERSION(NODE) \ - (LANG_TYPE_CLASS_CHECK (NODE)->h.has_type_conversion) - -/* Nonzero means that NODE (a class type) has a default constructor -- - but that it has not yet been declared. */ -#define CLASSTYPE_LAZY_DEFAULT_CTOR(NODE) \ - (LANG_TYPE_CLASS_CHECK (NODE)->lazy_default_ctor) - -/* Nonzero means that NODE (a class type) has a copy constructor -- - but that it has not yet been declared. */ -#define CLASSTYPE_LAZY_COPY_CTOR(NODE) \ - (LANG_TYPE_CLASS_CHECK (NODE)->lazy_copy_ctor) - -/* Nonzero means that NODE (a class type) has a move constructor -- - but that it has not yet been declared. */ -#define CLASSTYPE_LAZY_MOVE_CTOR(NODE) \ - (LANG_TYPE_CLASS_CHECK (NODE)->lazy_move_ctor) - -/* Nonzero means that NODE (a class type) has an assignment operator - -- but that it has not yet been declared. */ -#define CLASSTYPE_LAZY_COPY_ASSIGN(NODE) \ - (LANG_TYPE_CLASS_CHECK (NODE)->lazy_copy_assign) - -/* Nonzero means that NODE (a class type) has an assignment operator - -- but that it has not yet been declared. */ -#define CLASSTYPE_LAZY_MOVE_ASSIGN(NODE) \ - (LANG_TYPE_CLASS_CHECK (NODE)->lazy_move_assign) - -/* Nonzero means that NODE (a class type) has a destructor -- but that - it has not yet been declared. */ -#define CLASSTYPE_LAZY_DESTRUCTOR(NODE) \ - (LANG_TYPE_CLASS_CHECK (NODE)->lazy_destructor) - -/* Nonzero means that NODE (a class type) is final */ -#define CLASSTYPE_FINAL(NODE) \ - TYPE_FINAL_P (NODE) - - -/* Nonzero means that this _CLASSTYPE node overloads operator=(X&). */ -#define TYPE_HAS_COPY_ASSIGN(NODE) (LANG_TYPE_CLASS_CHECK (NODE)->has_copy_assign) - -/* True iff the class type NODE has an "operator =" whose parameter - has a parameter of type "const X&". */ -#define TYPE_HAS_CONST_COPY_ASSIGN(NODE) \ - (LANG_TYPE_CLASS_CHECK (NODE)->h.has_const_copy_assign) - -/* Nonzero means that this _CLASSTYPE node has an X(X&) constructor. */ -#define TYPE_HAS_COPY_CTOR(NODE) (LANG_TYPE_CLASS_CHECK (NODE)->h.has_copy_ctor) -#define TYPE_HAS_CONST_COPY_CTOR(NODE) \ - (LANG_TYPE_CLASS_CHECK (NODE)->has_const_copy_ctor) - -/* Nonzero if this class has an X(initializer_list) constructor. */ -#define TYPE_HAS_LIST_CTOR(NODE) \ - (LANG_TYPE_CLASS_CHECK (NODE)->has_list_ctor) - -/* Nonzero if this class has a constexpr constructor other than a copy/move - constructor. Note that a class can have constexpr constructors for - static initialization even if it isn't a literal class. */ -#define TYPE_HAS_CONSTEXPR_CTOR(NODE) \ - (LANG_TYPE_CLASS_CHECK (NODE)->has_constexpr_ctor) - -/* Nonzero if this class defines an overloaded operator new. (An - operator new [] doesn't count.) */ -#define TYPE_HAS_NEW_OPERATOR(NODE) \ - (LANG_TYPE_CLASS_CHECK (NODE)->has_new) - -/* Nonzero if this class defines an overloaded operator new[]. */ -#define TYPE_HAS_ARRAY_NEW_OPERATOR(NODE) \ - (LANG_TYPE_CLASS_CHECK (NODE)->has_array_new) - -/* Nonzero means that this type is being defined. I.e., the left brace - starting the definition of this type has been seen. */ -#define TYPE_BEING_DEFINED(NODE) (LANG_TYPE_CLASS_CHECK (NODE)->being_defined) - -/* Nonzero means that this type is either complete or being defined, so we - can do lookup in it. */ -#define COMPLETE_OR_OPEN_TYPE_P(NODE) \ - (COMPLETE_TYPE_P (NODE) || (CLASS_TYPE_P (NODE) && TYPE_BEING_DEFINED (NODE))) - -/* Mark bits for repeated base checks. */ -#define TYPE_MARKED_P(NODE) TREE_LANG_FLAG_6 (TYPE_CHECK (NODE)) - -/* Nonzero if the class NODE has multiple paths to the same (virtual) - base object. */ -#define CLASSTYPE_DIAMOND_SHAPED_P(NODE) \ - (LANG_TYPE_CLASS_CHECK(NODE)->diamond_shaped) - -/* Nonzero if the class NODE has multiple instances of the same base - type. */ -#define CLASSTYPE_REPEATED_BASE_P(NODE) \ - (LANG_TYPE_CLASS_CHECK(NODE)->repeated_base) - -/* The member function with which the vtable will be emitted: - the first noninline non-pure-virtual member function. NULL_TREE - if there is no key function or if this is a class template */ -#define CLASSTYPE_KEY_METHOD(NODE) (LANG_TYPE_CLASS_CHECK (NODE)->key_method) - -/* Vector member functions defined in this class. Each element is - either a FUNCTION_DECL, a TEMPLATE_DECL, or an OVERLOAD. All - functions with the same name end up in the same slot. The first - two elements are for constructors, and destructors, respectively. - All template conversion operators to innermost template dependent - types are overloaded on the next slot, if they exist. Note, the - names for these functions will not all be the same. The - non-template conversion operators & templated conversions to - non-innermost template types are next, followed by ordinary member - functions. There may be empty entries at the end of the vector. - The conversion operators are unsorted. The ordinary member - functions are sorted, once the class is complete. */ -#define CLASSTYPE_METHOD_VEC(NODE) (LANG_TYPE_CLASS_CHECK (NODE)->methods) - -/* For class templates, this is a TREE_LIST of all member data, - functions, types, and friends in the order of declaration. - The TREE_PURPOSE of each TREE_LIST is NULL_TREE for a friend, - and the RECORD_TYPE for the class template otherwise. */ -#define CLASSTYPE_DECL_LIST(NODE) (LANG_TYPE_CLASS_CHECK (NODE)->decl_list) - -/* The slot in the CLASSTYPE_METHOD_VEC where constructors go. */ -#define CLASSTYPE_CONSTRUCTOR_SLOT 0 - -/* The slot in the CLASSTYPE_METHOD_VEC where destructors go. */ -#define CLASSTYPE_DESTRUCTOR_SLOT 1 - -/* The first slot in the CLASSTYPE_METHOD_VEC where conversion - operators can appear. */ -#define CLASSTYPE_FIRST_CONVERSION_SLOT 2 - -/* A FUNCTION_DECL or OVERLOAD for the constructors for NODE. These - are the constructors that take an in-charge parameter. */ -#define CLASSTYPE_CONSTRUCTORS(NODE) \ - ((*CLASSTYPE_METHOD_VEC (NODE))[CLASSTYPE_CONSTRUCTOR_SLOT]) - -/* A FUNCTION_DECL for the destructor for NODE. These are the - destructors that take an in-charge parameter. If - CLASSTYPE_LAZY_DESTRUCTOR is true, then this entry will be NULL - until the destructor is created with lazily_declare_fn. */ -#define CLASSTYPE_DESTRUCTORS(NODE) \ - (CLASSTYPE_METHOD_VEC (NODE) \ - ? (*CLASSTYPE_METHOD_VEC (NODE))[CLASSTYPE_DESTRUCTOR_SLOT] \ - : NULL_TREE) - -/* A dictionary of the nested user-defined-types (class-types, or enums) - found within this class. This table includes nested member class - templates. */ -#define CLASSTYPE_NESTED_UTDS(NODE) \ - (LANG_TYPE_CLASS_CHECK (NODE)->nested_udts) - -/* Nonzero if NODE has a primary base class, i.e., a base class with - which it shares the virtual function table pointer. */ -#define CLASSTYPE_HAS_PRIMARY_BASE_P(NODE) \ - (CLASSTYPE_PRIMARY_BINFO (NODE) != NULL_TREE) - -/* If non-NULL, this is the binfo for the primary base class, i.e., - the base class which contains the virtual function table pointer - for this class. */ -#define CLASSTYPE_PRIMARY_BINFO(NODE) \ - (LANG_TYPE_CLASS_CHECK (NODE)->primary_base) - -/* A vector of BINFOs for the direct and indirect virtual base classes - that this type uses in a post-order depth-first left-to-right - order. (In other words, these bases appear in the order that they - should be initialized.) */ -#define CLASSTYPE_VBASECLASSES(NODE) (LANG_TYPE_CLASS_CHECK (NODE)->vbases) - -/* The type corresponding to NODE when NODE is used as a base class, - i.e., NODE without virtual base classes. */ - -#define CLASSTYPE_AS_BASE(NODE) (LANG_TYPE_CLASS_CHECK (NODE)->as_base) - -/* True iff NODE is the CLASSTYPE_AS_BASE version of some type. */ - -#define IS_FAKE_BASE_TYPE(NODE) \ - (TREE_CODE (NODE) == RECORD_TYPE \ - && TYPE_CONTEXT (NODE) && CLASS_TYPE_P (TYPE_CONTEXT (NODE)) \ - && CLASSTYPE_AS_BASE (TYPE_CONTEXT (NODE)) == (NODE)) - -/* These are the size and alignment of the type without its virtual - base classes, for when we use this type as a base itself. */ -#define CLASSTYPE_SIZE(NODE) TYPE_SIZE (CLASSTYPE_AS_BASE (NODE)) -#define CLASSTYPE_SIZE_UNIT(NODE) TYPE_SIZE_UNIT (CLASSTYPE_AS_BASE (NODE)) -#define CLASSTYPE_ALIGN(NODE) TYPE_ALIGN (CLASSTYPE_AS_BASE (NODE)) -#define CLASSTYPE_USER_ALIGN(NODE) TYPE_USER_ALIGN (CLASSTYPE_AS_BASE (NODE)) - -/* The alignment of NODE, without its virtual bases, in bytes. */ -#define CLASSTYPE_ALIGN_UNIT(NODE) \ - (CLASSTYPE_ALIGN (NODE) / BITS_PER_UNIT) - -/* True if this a Java interface type, declared with - '__attribute__ ((java_interface))'. */ -#define TYPE_JAVA_INTERFACE(NODE) \ - (LANG_TYPE_CLASS_CHECK (NODE)->java_interface) - -/* A vec of virtual functions which cannot be inherited by - derived classes. When deriving from this type, the derived - class must provide its own definition for each of these functions. */ -#define CLASSTYPE_PURE_VIRTUALS(NODE) \ - (LANG_TYPE_CLASS_CHECK (NODE)->pure_virtuals) - -/* Nonzero means that this type is an abstract class type. */ -#define ABSTRACT_CLASS_TYPE_P(NODE) \ - (CLASS_TYPE_P (NODE) && CLASSTYPE_PURE_VIRTUALS(NODE)) - -/* Nonzero means that this type has an X() constructor. */ -#define TYPE_HAS_DEFAULT_CONSTRUCTOR(NODE) \ - (LANG_TYPE_CLASS_CHECK (NODE)->h.has_default_ctor) - -/* Nonzero means that this type contains a mutable member. */ -#define CLASSTYPE_HAS_MUTABLE(NODE) (LANG_TYPE_CLASS_CHECK (NODE)->has_mutable) -#define TYPE_HAS_MUTABLE_P(NODE) (cp_has_mutable_p (NODE)) - -/* Nonzero means that this class type is not POD for the purpose of layout - (as defined in the ABI). This is different from the language's POD. */ -#define CLASSTYPE_NON_LAYOUT_POD_P(NODE) \ - (LANG_TYPE_CLASS_CHECK (NODE)->non_pod_class) - -/* Nonzero means that this class type is a non-standard-layout class. */ -#define CLASSTYPE_NON_STD_LAYOUT(NODE) \ - (LANG_TYPE_CLASS_CHECK (NODE)->non_std_layout) - -/* Nonzero means that this class contains pod types whose default - initialization is not a zero initialization (namely, pointers to - data members). */ -#define CLASSTYPE_NON_ZERO_INIT_P(NODE) \ - (LANG_TYPE_CLASS_CHECK (NODE)->non_zero_init) - -/* Nonzero if this class is "empty" in the sense of the C++ ABI. */ -#define CLASSTYPE_EMPTY_P(NODE) \ - (LANG_TYPE_CLASS_CHECK (NODE)->empty_p) - -/* Nonzero if this class is "nearly empty", i.e., contains only a - virtual function table pointer. */ -#define CLASSTYPE_NEARLY_EMPTY_P(NODE) \ - (LANG_TYPE_CLASS_CHECK (NODE)->nearly_empty_p) - -/* Nonzero if this class contains an empty subobject. */ -#define CLASSTYPE_CONTAINS_EMPTY_CLASS_P(NODE) \ - (LANG_TYPE_CLASS_CHECK (NODE)->contains_empty_class_p) - -/* A list of class types of which this type is a friend. The - TREE_VALUE is normally a TYPE, but will be a TEMPLATE_DECL in the - case of a template friend. */ -#define CLASSTYPE_FRIEND_CLASSES(NODE) \ - (LANG_TYPE_CLASS_CHECK (NODE)->friend_classes) - -/* A list of the classes which grant friendship to this class. */ -#define CLASSTYPE_BEFRIENDING_CLASSES(NODE) \ - (LANG_TYPE_CLASS_CHECK (NODE)->befriending_classes) - -/* The associated LAMBDA_EXPR that made this class. */ -#define CLASSTYPE_LAMBDA_EXPR(NODE) \ - (LANG_TYPE_CLASS_CHECK (NODE)->lambda_expr) -/* The extra mangling scope for this closure type. */ -#define LAMBDA_TYPE_EXTRA_SCOPE(NODE) \ - (LAMBDA_EXPR_EXTRA_SCOPE (CLASSTYPE_LAMBDA_EXPR (NODE))) - -/* Say whether this node was declared as a "class" or a "struct". */ -#define CLASSTYPE_DECLARED_CLASS(NODE) \ - (LANG_TYPE_CLASS_CHECK (NODE)->declared_class) - -/* Nonzero if this class has const members - which have no specified initialization. */ -#define CLASSTYPE_READONLY_FIELDS_NEED_INIT(NODE) \ - (TYPE_LANG_SPECIFIC (NODE) \ - ? LANG_TYPE_CLASS_CHECK (NODE)->h.const_needs_init : 0) -#define SET_CLASSTYPE_READONLY_FIELDS_NEED_INIT(NODE, VALUE) \ - (LANG_TYPE_CLASS_CHECK (NODE)->h.const_needs_init = (VALUE)) - -/* Nonzero if this class has ref members - which have no specified initialization. */ -#define CLASSTYPE_REF_FIELDS_NEED_INIT(NODE) \ - (TYPE_LANG_SPECIFIC (NODE) \ - ? LANG_TYPE_CLASS_CHECK (NODE)->h.ref_needs_init : 0) -#define SET_CLASSTYPE_REF_FIELDS_NEED_INIT(NODE, VALUE) \ - (LANG_TYPE_CLASS_CHECK (NODE)->h.ref_needs_init = (VALUE)) - -/* Nonzero if this class is included from a header file which employs - `#pragma interface', and it is not included in its implementation file. */ -#define CLASSTYPE_INTERFACE_ONLY(NODE) \ - (LANG_TYPE_CLASS_CHECK (NODE)->interface_only) - -/* True if we have already determined whether or not vtables, VTTs, - typeinfo, and other similar per-class data should be emitted in - this translation unit. This flag does not indicate whether or not - these items should be emitted; it only indicates that we know one - way or the other. */ -#define CLASSTYPE_INTERFACE_KNOWN(NODE) \ - (LANG_TYPE_CLASS_CHECK (NODE)->interface_unknown == 0) -/* The opposite of CLASSTYPE_INTERFACE_KNOWN. */ -#define CLASSTYPE_INTERFACE_UNKNOWN(NODE) \ - (LANG_TYPE_CLASS_CHECK (NODE)->interface_unknown) - -#define SET_CLASSTYPE_INTERFACE_UNKNOWN_X(NODE,X) \ - (LANG_TYPE_CLASS_CHECK (NODE)->interface_unknown = !!(X)) -#define SET_CLASSTYPE_INTERFACE_UNKNOWN(NODE) \ - (LANG_TYPE_CLASS_CHECK (NODE)->interface_unknown = 1) -#define SET_CLASSTYPE_INTERFACE_KNOWN(NODE) \ - (LANG_TYPE_CLASS_CHECK (NODE)->interface_unknown = 0) - -/* Nonzero if a _DECL node requires us to output debug info for this class. */ -#define CLASSTYPE_DEBUG_REQUESTED(NODE) \ - (LANG_TYPE_CLASS_CHECK (NODE)->debug_requested) - -/* Additional macros for inheritance information. */ - -/* Nonzero means that this class is on a path leading to a new vtable. */ -#define BINFO_VTABLE_PATH_MARKED(NODE) BINFO_FLAG_1 (NODE) - -/* Nonzero means B (a BINFO) has its own vtable. Any copies will not - have this flag set. */ -#define BINFO_NEW_VTABLE_MARKED(B) (BINFO_FLAG_2 (B)) - -/* Compare a BINFO_TYPE with another type for equality. For a binfo, - this is functionally equivalent to using same_type_p, but - measurably faster. At least one of the arguments must be a - BINFO_TYPE. The other can be a BINFO_TYPE or a regular type. If - BINFO_TYPE(T) ever stops being the main variant of the class the - binfo is for, this macro must change. */ -#define SAME_BINFO_TYPE_P(A, B) ((A) == (B)) - -/* Any subobject that needs a new vtable must have a vptr and must not - be a non-virtual primary base (since it would then use the vtable from a - derived class and never become non-primary.) */ -#define SET_BINFO_NEW_VTABLE_MARKED(B) \ - (BINFO_NEW_VTABLE_MARKED (B) = 1, \ - gcc_assert (!BINFO_PRIMARY_P (B) || BINFO_VIRTUAL_P (B)), \ - gcc_assert (TYPE_VFIELD (BINFO_TYPE (B)))) - -/* Nonzero if this binfo is for a dependent base - one that should not - be searched. */ -#define BINFO_DEPENDENT_BASE_P(NODE) BINFO_FLAG_3 (NODE) - -/* Nonzero if this binfo has lost its primary base binfo (because that - is a nearly-empty virtual base that has been taken by some other - base in the complete hierarchy. */ -#define BINFO_LOST_PRIMARY_P(NODE) BINFO_FLAG_4 (NODE) - -/* Nonzero if this BINFO is a primary base class. */ -#define BINFO_PRIMARY_P(NODE) BINFO_FLAG_5(NODE) - -/* Used by various search routines. */ -#define IDENTIFIER_MARKED(NODE) TREE_LANG_FLAG_0 (NODE) - -/* A vec of the vcall indices associated with the class - NODE. The PURPOSE of each element is a FUNCTION_DECL for a virtual - function. The VALUE is the index into the virtual table where the - vcall offset for that function is stored, when NODE is a virtual - base. */ -#define CLASSTYPE_VCALL_INDICES(NODE) \ - (LANG_TYPE_CLASS_CHECK (NODE)->vcall_indices) - -/* The various vtables for the class NODE. The primary vtable will be - first, followed by the construction vtables and VTT, if any. */ -#define CLASSTYPE_VTABLES(NODE) \ - (LANG_TYPE_CLASS_CHECK (NODE)->vtables) - -/* The std::type_info variable representing this class, or NULL if no - such variable has been created. This field is only set for the - TYPE_MAIN_VARIANT of the class. */ -#define CLASSTYPE_TYPEINFO_VAR(NODE) \ - (LANG_TYPE_CLASS_CHECK (NODE)->typeinfo_var) - -/* Accessor macros for the BINFO_VIRTUALS list. */ - -/* The number of bytes by which to adjust the `this' pointer when - calling this virtual function. Subtract this value from the this - pointer. Always non-NULL, might be constant zero though. */ -#define BV_DELTA(NODE) (TREE_PURPOSE (NODE)) - -/* If non-NULL, the vtable index at which to find the vcall offset - when calling this virtual function. Add the value at that vtable - index to the this pointer. */ -#define BV_VCALL_INDEX(NODE) (TREE_TYPE (NODE)) - -/* The function to call. */ -#define BV_FN(NODE) (TREE_VALUE (NODE)) - -/* Whether or not this entry is for a lost primary virtual base. */ -#define BV_LOST_PRIMARY(NODE) (TREE_LANG_FLAG_0 (NODE)) - -/* For FUNCTION_TYPE or METHOD_TYPE, a list of the exceptions that - this type can raise. Each TREE_VALUE is a _TYPE. The TREE_VALUE - will be NULL_TREE to indicate a throw specification of `()', or - no exceptions allowed. For a noexcept specification, TREE_VALUE - is NULL_TREE and TREE_PURPOSE is the constant-expression. For - a deferred noexcept-specification, TREE_PURPOSE is a DEFERRED_NOEXCEPT - (for templates) or an OVERLOAD list of functions (for implicitly - declared functions). */ -#define TYPE_RAISES_EXCEPTIONS(NODE) \ - TYPE_LANG_SLOT_1 (FUNC_OR_METHOD_CHECK (NODE)) - -/* For FUNCTION_TYPE or METHOD_TYPE, return 1 iff it is declared `throw()' - or noexcept(true). */ -#define TYPE_NOTHROW_P(NODE) nothrow_spec_p (TYPE_RAISES_EXCEPTIONS (NODE)) - -/* For FUNCTION_TYPE or METHOD_TYPE, true if NODE is noexcept. This is the - case for things declared noexcept(true) and, with -fnothrow-opt, for - throw() functions. */ -#define TYPE_NOEXCEPT_P(NODE) type_noexcept_p (NODE) - -/* The binding level associated with the namespace. */ -#define NAMESPACE_LEVEL(NODE) \ - (LANG_DECL_NS_CHECK (NODE)->level) - -/* Flags shared by all forms of DECL_LANG_SPECIFIC. - - Some of the flags live here only to make lang_decl_min/fn smaller. Do - not make this struct larger than 32 bits; instead, make sel smaller. */ - -struct GTY(()) lang_decl_base { - unsigned selector : 16; /* Larger than necessary for faster access. */ - ENUM_BITFIELD(languages) language : 4; - unsigned use_template : 2; - unsigned not_really_extern : 1; /* var or fn */ - unsigned initialized_in_class : 1; /* var or fn */ - unsigned repo_available_p : 1; /* var or fn */ - unsigned threadprivate_or_deleted_p : 1; /* var or fn */ - unsigned anticipated_p : 1; /* fn, type or template */ - unsigned friend_attr : 1; /* fn, type or template */ - unsigned template_conv_p : 1; /* var or template */ - unsigned odr_used : 1; /* var or fn */ - unsigned u2sel : 1; - /* 1 spare bit */ -}; - -/* True for DECL codes which have template info and access. */ -#define LANG_DECL_HAS_MIN(NODE) \ - (VAR_OR_FUNCTION_DECL_P (NODE) \ - || TREE_CODE (NODE) == FIELD_DECL \ - || TREE_CODE (NODE) == CONST_DECL \ - || TREE_CODE (NODE) == TYPE_DECL \ - || TREE_CODE (NODE) == TEMPLATE_DECL \ - || TREE_CODE (NODE) == USING_DECL) - -/* DECL_LANG_SPECIFIC for the above codes. */ - -struct GTY(()) lang_decl_min { - struct lang_decl_base base; - - /* In a FUNCTION_DECL for which DECL_THUNK_P holds, this is - THUNK_ALIAS. - In a FUNCTION_DECL for which DECL_THUNK_P does not hold, - VAR_DECL, TYPE_DECL, or TEMPLATE_DECL, this is - DECL_TEMPLATE_INFO. */ - tree template_info; - - union lang_decl_u2 { - /* In a FUNCTION_DECL for which DECL_THUNK_P holds, this is - THUNK_VIRTUAL_OFFSET. - Otherwise this is DECL_ACCESS. */ - tree GTY ((tag ("0"))) access; - - /* For VAR_DECL in function, this is DECL_DISCRIMINATOR. */ - int GTY ((tag ("1"))) discriminator; - } GTY ((desc ("%0.u.base.u2sel"))) u2; -}; - -/* Additional DECL_LANG_SPECIFIC information for functions. */ - -struct GTY(()) lang_decl_fn { - struct lang_decl_min min; - - /* In an overloaded operator, this is the value of - DECL_OVERLOADED_OPERATOR_P. */ - ENUM_BITFIELD (tree_code) operator_code : 16; - - unsigned global_ctor_p : 1; - unsigned global_dtor_p : 1; - unsigned assignment_operator_p : 1; - unsigned static_function : 1; - unsigned pure_virtual : 1; - unsigned defaulted_p : 1; - - unsigned has_in_charge_parm_p : 1; - unsigned has_vtt_parm_p : 1; - unsigned pending_inline_p : 1; - unsigned nonconverting : 1; - unsigned thunk_p : 1; - unsigned this_thunk_p : 1; - unsigned hidden_friend_p : 1; - unsigned omp_declare_reduction_p : 1; - /* 2 spare bits on 32-bit hosts, 34 on 64-bit hosts. */ - - /* For a non-thunk function decl, this is a tree list of - friendly classes. For a thunk function decl, it is the - thunked to function decl. */ - tree befriending_classes; - - /* For a non-virtual FUNCTION_DECL, this is - DECL_FRIEND_CONTEXT. For a virtual FUNCTION_DECL for which - DECL_THIS_THUNK_P does not hold, this is DECL_THUNKS. Both - this pointer and result pointer adjusting thunks are - chained here. This pointer thunks to return pointer thunks - will be chained on the return pointer thunk. */ - tree context; - - union lang_decl_u5 - { - /* In a non-thunk FUNCTION_DECL or TEMPLATE_DECL, this is - DECL_CLONED_FUNCTION. */ - tree GTY ((tag ("0"))) cloned_function; - - /* In a FUNCTION_DECL for which THUNK_P holds this is the - THUNK_FIXED_OFFSET. */ - HOST_WIDE_INT GTY ((tag ("1"))) fixed_offset; - } GTY ((desc ("%1.thunk_p"))) u5; - - union lang_decl_u3 - { - struct cp_token_cache * GTY ((tag ("1"))) pending_inline_info; - struct language_function * GTY ((tag ("0"))) - saved_language_function; - } GTY ((desc ("%1.pending_inline_p"))) u; - -}; - -/* DECL_LANG_SPECIFIC for namespaces. */ - -struct GTY(()) lang_decl_ns { - struct lang_decl_base base; - cp_binding_level *level; - tree ns_using; - tree ns_users; -}; - -/* DECL_LANG_SPECIFIC for parameters. */ - -struct GTY(()) lang_decl_parm { - struct lang_decl_base base; - int level; - int index; -}; - -/* DECL_LANG_SPECIFIC for all types. It would be nice to just make this a - union rather than a struct containing a union as its only field, but - tree.h declares it as a struct. */ - -struct GTY(()) lang_decl { - union GTY((desc ("%h.base.selector"))) lang_decl_u { - struct lang_decl_base GTY ((default)) base; - struct lang_decl_min GTY((tag ("0"))) min; - struct lang_decl_fn GTY ((tag ("1"))) fn; - struct lang_decl_ns GTY((tag ("2"))) ns; - struct lang_decl_parm GTY((tag ("3"))) parm; - } u; -}; - -/* Looks through a template (if present) to find what it declares. */ -#define STRIP_TEMPLATE(NODE) \ - (TREE_CODE (NODE) == TEMPLATE_DECL ? DECL_TEMPLATE_RESULT (NODE) : NODE) - -#if defined ENABLE_TREE_CHECKING && (GCC_VERSION >= 2007) - -#define LANG_DECL_MIN_CHECK(NODE) __extension__ \ -({ struct lang_decl *lt = DECL_LANG_SPECIFIC (NODE); \ - if (!LANG_DECL_HAS_MIN (NODE)) \ - lang_check_failed (__FILE__, __LINE__, __FUNCTION__); \ - <->u.min; }) - -/* We want to be able to check DECL_CONSTRUCTOR_P and such on a function - template, not just on a FUNCTION_DECL. So when looking for things in - lang_decl_fn, look down through a TEMPLATE_DECL into its result. */ -#define LANG_DECL_FN_CHECK(NODE) __extension__ \ -({ struct lang_decl *lt = DECL_LANG_SPECIFIC (STRIP_TEMPLATE (NODE)); \ - if (!DECL_DECLARES_FUNCTION_P (NODE) || lt->u.base.selector != 1) \ - lang_check_failed (__FILE__, __LINE__, __FUNCTION__); \ - <->u.fn; }) - -#define LANG_DECL_NS_CHECK(NODE) __extension__ \ -({ struct lang_decl *lt = DECL_LANG_SPECIFIC (NODE); \ - if (TREE_CODE (NODE) != NAMESPACE_DECL || lt->u.base.selector != 2) \ - lang_check_failed (__FILE__, __LINE__, __FUNCTION__); \ - <->u.ns; }) - -#define LANG_DECL_PARM_CHECK(NODE) __extension__ \ -({ struct lang_decl *lt = DECL_LANG_SPECIFIC (NODE); \ - if (TREE_CODE (NODE) != PARM_DECL) \ - lang_check_failed (__FILE__, __LINE__, __FUNCTION__); \ - <->u.parm; }) - -#define LANG_DECL_U2_CHECK(NODE, TF) __extension__ \ -({ struct lang_decl *lt = DECL_LANG_SPECIFIC (NODE); \ - if (!LANG_DECL_HAS_MIN (NODE) || lt->u.base.u2sel != TF) \ - lang_check_failed (__FILE__, __LINE__, __FUNCTION__); \ - <->u.min.u2; }) - -#else - -#define LANG_DECL_MIN_CHECK(NODE) \ - (&DECL_LANG_SPECIFIC (NODE)->u.min) - -#define LANG_DECL_FN_CHECK(NODE) \ - (&DECL_LANG_SPECIFIC (STRIP_TEMPLATE (NODE))->u.fn) - -#define LANG_DECL_NS_CHECK(NODE) \ - (&DECL_LANG_SPECIFIC (NODE)->u.ns) - -#define LANG_DECL_PARM_CHECK(NODE) \ - (&DECL_LANG_SPECIFIC (NODE)->u.parm) - -#define LANG_DECL_U2_CHECK(NODE, TF) \ - (&DECL_LANG_SPECIFIC (NODE)->u.min.u2) - -#endif /* ENABLE_TREE_CHECKING */ - -/* For a FUNCTION_DECL or a VAR_DECL, the language linkage for the - declaration. Some entities (like a member function in a local - class, or a local variable) do not have linkage at all, and this - macro should not be used in those cases. - - Implementation note: A FUNCTION_DECL without DECL_LANG_SPECIFIC was - created by language-independent code, and has C linkage. Most - VAR_DECLs have C++ linkage, and do not have DECL_LANG_SPECIFIC, but - we do create DECL_LANG_SPECIFIC for variables with non-C++ linkage. */ -#define DECL_LANGUAGE(NODE) \ - (DECL_LANG_SPECIFIC (NODE) \ - ? DECL_LANG_SPECIFIC (NODE)->u.base.language \ - : (TREE_CODE (NODE) == FUNCTION_DECL \ - ? lang_c : lang_cplusplus)) - -/* Set the language linkage for NODE to LANGUAGE. */ -#define SET_DECL_LANGUAGE(NODE, LANGUAGE) \ - (DECL_LANG_SPECIFIC (NODE)->u.base.language = (LANGUAGE)) - -/* For FUNCTION_DECLs and TEMPLATE_DECLs: nonzero means that this function - is a constructor. */ -#define DECL_CONSTRUCTOR_P(NODE) \ - DECL_CXX_CONSTRUCTOR_P (STRIP_TEMPLATE (NODE)) - -/* Nonzero if NODE (a FUNCTION_DECL) is a constructor for a complete - object. */ -#define DECL_COMPLETE_CONSTRUCTOR_P(NODE) \ - (DECL_CONSTRUCTOR_P (NODE) \ - && DECL_NAME (NODE) == complete_ctor_identifier) - -/* Nonzero if NODE (a FUNCTION_DECL) is a constructor for a base - object. */ -#define DECL_BASE_CONSTRUCTOR_P(NODE) \ - (DECL_CONSTRUCTOR_P (NODE) \ - && DECL_NAME (NODE) == base_ctor_identifier) - -/* Nonzero if NODE (a FUNCTION_DECL) is a constructor, but not either the - specialized in-charge constructor or the specialized not-in-charge - constructor. */ -#define DECL_MAYBE_IN_CHARGE_CONSTRUCTOR_P(NODE) \ - (DECL_DECLARES_FUNCTION_P (NODE) && DECL_CONSTRUCTOR_P (NODE) \ - && !DECL_CLONED_FUNCTION_P (NODE)) - -/* Nonzero if NODE (a FUNCTION_DECL) is a copy constructor. */ -#define DECL_COPY_CONSTRUCTOR_P(NODE) \ - (DECL_CONSTRUCTOR_P (NODE) && copy_fn_p (NODE) > 0) - -/* Nonzero if NODE (a FUNCTION_DECL) is a move constructor. */ -#define DECL_MOVE_CONSTRUCTOR_P(NODE) \ - (DECL_CONSTRUCTOR_P (NODE) && move_fn_p (NODE)) - -/* Nonzero if NODE (a FUNCTION_DECL or TEMPLATE_DECL) - is a destructor. */ -#define DECL_DESTRUCTOR_P(NODE) \ - DECL_CXX_DESTRUCTOR_P (STRIP_TEMPLATE (NODE)) - -/* Nonzero if NODE (a FUNCTION_DECL) is a destructor, but not the - specialized in-charge constructor, in-charge deleting constructor, - or the base destructor. */ -#define DECL_MAYBE_IN_CHARGE_DESTRUCTOR_P(NODE) \ - (DECL_DECLARES_FUNCTION_P (NODE) && DECL_DESTRUCTOR_P (NODE) \ - && !DECL_CLONED_FUNCTION_P (NODE)) - -/* Nonzero if NODE (a FUNCTION_DECL) is a destructor for a complete - object. */ -#define DECL_COMPLETE_DESTRUCTOR_P(NODE) \ - (DECL_DESTRUCTOR_P (NODE) \ - && DECL_NAME (NODE) == complete_dtor_identifier) - -/* Nonzero if NODE (a FUNCTION_DECL) is a destructor for a base - object. */ -#define DECL_BASE_DESTRUCTOR_P(NODE) \ - (DECL_DESTRUCTOR_P (NODE) \ - && DECL_NAME (NODE) == base_dtor_identifier) - -/* Nonzero if NODE (a FUNCTION_DECL) is a destructor for a complete - object that deletes the object after it has been destroyed. */ -#define DECL_DELETING_DESTRUCTOR_P(NODE) \ - (DECL_DESTRUCTOR_P (NODE) \ - && DECL_NAME (NODE) == deleting_dtor_identifier) - -/* Nonzero if NODE (a FUNCTION_DECL) is a cloned constructor or - destructor. */ -#define DECL_CLONED_FUNCTION_P(NODE) (!!decl_cloned_function_p (NODE, true)) - -/* If DECL_CLONED_FUNCTION_P holds, this is the function that was - cloned. */ -#define DECL_CLONED_FUNCTION(NODE) (*decl_cloned_function_p (NODE, false)) - -/* Perform an action for each clone of FN, if FN is a function with - clones. This macro should be used like: - - FOR_EACH_CLONE (clone, fn) - { ... } - - */ -#define FOR_EACH_CLONE(CLONE, FN) \ - if (TREE_CODE (FN) == FUNCTION_DECL \ - && (DECL_MAYBE_IN_CHARGE_CONSTRUCTOR_P (FN) \ - || DECL_MAYBE_IN_CHARGE_DESTRUCTOR_P (FN))) \ - for (CLONE = DECL_CHAIN (FN); \ - CLONE && DECL_CLONED_FUNCTION_P (CLONE); \ - CLONE = DECL_CHAIN (CLONE)) - -/* Nonzero if NODE has DECL_DISCRIMINATOR and not DECL_ACCESS. */ -#define DECL_DISCRIMINATOR_P(NODE) \ - (VAR_P (NODE) && DECL_FUNCTION_SCOPE_P (NODE)) - -/* Discriminator for name mangling. */ -#define DECL_DISCRIMINATOR(NODE) (LANG_DECL_U2_CHECK (NODE, 1)->discriminator) - -/* True iff DECL_DISCRIMINATOR is set for a DECL_DISCRIMINATOR_P decl. */ -#define DECL_DISCRIMINATOR_SET_P(NODE) \ - (DECL_LANG_SPECIFIC (NODE) && DECL_LANG_SPECIFIC (NODE)->u.base.u2sel == 1) - -/* The index of a user-declared parameter in its function, starting at 1. - All artificial parameters will have index 0. */ -#define DECL_PARM_INDEX(NODE) \ - (LANG_DECL_PARM_CHECK (NODE)->index) - -/* The level of a user-declared parameter in its function, starting at 1. - A parameter of the function will have level 1; a parameter of the first - nested function declarator (i.e. t in void f (void (*p)(T t))) will have - level 2. */ -#define DECL_PARM_LEVEL(NODE) \ - (LANG_DECL_PARM_CHECK (NODE)->level) - -/* Nonzero if the VTT parm has been added to NODE. */ -#define DECL_HAS_VTT_PARM_P(NODE) \ - (LANG_DECL_FN_CHECK (NODE)->has_vtt_parm_p) - -/* Nonzero if NODE is a FUNCTION_DECL for which a VTT parameter is - required. */ -#define DECL_NEEDS_VTT_PARM_P(NODE) \ - (CLASSTYPE_VBASECLASSES (DECL_CONTEXT (NODE)) \ - && (DECL_BASE_CONSTRUCTOR_P (NODE) \ - || DECL_BASE_DESTRUCTOR_P (NODE))) - -/* Nonzero if NODE is a user-defined conversion operator. */ -#define DECL_CONV_FN_P(NODE) \ - (DECL_NAME (NODE) && IDENTIFIER_TYPENAME_P (DECL_NAME (NODE))) - -/* If FN is a conversion operator, the type to which it converts. - Otherwise, NULL_TREE. */ -#define DECL_CONV_FN_TYPE(FN) \ - (DECL_CONV_FN_P (FN) ? TREE_TYPE (DECL_NAME (FN)) : NULL_TREE) - -/* Nonzero if NODE, which is a TEMPLATE_DECL, is a template - conversion operator to a type dependent on the innermost template - args. */ -#define DECL_TEMPLATE_CONV_FN_P(NODE) \ - (DECL_LANG_SPECIFIC (TEMPLATE_DECL_CHECK (NODE))->u.base.template_conv_p) - -/* Nonzero if NODE, a static data member, was declared in its class as an - array of unknown bound. */ -#define VAR_HAD_UNKNOWN_BOUND(NODE) \ - (DECL_LANG_SPECIFIC (VAR_DECL_CHECK (NODE)) \ - ? DECL_LANG_SPECIFIC (NODE)->u.base.template_conv_p \ - : false) -#define SET_VAR_HAD_UNKNOWN_BOUND(NODE) \ - (DECL_LANG_SPECIFIC (VAR_DECL_CHECK (NODE))->u.base.template_conv_p = true) - -/* Set the overloaded operator code for NODE to CODE. */ -#define SET_OVERLOADED_OPERATOR_CODE(NODE, CODE) \ - (LANG_DECL_FN_CHECK (NODE)->operator_code = (CODE)) - -/* If NODE is an overloaded operator, then this returns the TREE_CODE - associated with the overloaded operator. - DECL_ASSIGNMENT_OPERATOR_P must also be checked to determine - whether or not NODE is an assignment operator. If NODE is not an - overloaded operator, ERROR_MARK is returned. Since the numerical - value of ERROR_MARK is zero, this macro can be used as a predicate - to test whether or not NODE is an overloaded operator. */ -#define DECL_OVERLOADED_OPERATOR_P(NODE) \ - (IDENTIFIER_OPNAME_P (DECL_NAME (NODE)) \ - ? LANG_DECL_FN_CHECK (NODE)->operator_code : ERROR_MARK) - -/* Nonzero if NODE is an assignment operator (including += and such). */ -#define DECL_ASSIGNMENT_OPERATOR_P(NODE) \ - (LANG_DECL_FN_CHECK (NODE)->assignment_operator_p) - -/* For FUNCTION_DECLs: nonzero means that this function is a - constructor or a destructor with an extra in-charge parameter to - control whether or not virtual bases are constructed. */ -#define DECL_HAS_IN_CHARGE_PARM_P(NODE) \ - (LANG_DECL_FN_CHECK (NODE)->has_in_charge_parm_p) - -/* Nonzero if DECL is a declaration of __builtin_constant_p. */ -#define DECL_IS_BUILTIN_CONSTANT_P(NODE) \ - (TREE_CODE (NODE) == FUNCTION_DECL \ - && DECL_BUILT_IN_CLASS (NODE) == BUILT_IN_NORMAL \ - && DECL_FUNCTION_CODE (NODE) == BUILT_IN_CONSTANT_P) - -/* Nonzero for _DECL means that this decl appears in (or will appear - in) as a member in a RECORD_TYPE or UNION_TYPE node. It is also for - detecting circularity in case members are multiply defined. In the - case of a VAR_DECL, it is also used to determine how program storage - should be allocated. */ -#define DECL_IN_AGGR_P(NODE) (DECL_LANG_FLAG_3 (NODE)) - -/* Nonzero for a VAR_DECL means that the variable's initialization (if - any) has been processed. (In general, DECL_INITIALIZED_P is - !DECL_EXTERNAL, but static data members may be initialized even if - not defined.) */ -#define DECL_INITIALIZED_P(NODE) \ - (TREE_LANG_FLAG_1 (VAR_DECL_CHECK (NODE))) - -/* Nonzero for a VAR_DECL iff an explicit initializer was provided - or a non-trivial constructor is called. */ -#define DECL_NONTRIVIALLY_INITIALIZED_P(NODE) \ - (TREE_LANG_FLAG_3 (VAR_DECL_CHECK (NODE))) - -/* Nonzero for a VAR_DECL that was initialized with a - constant-expression. */ -#define DECL_INITIALIZED_BY_CONSTANT_EXPRESSION_P(NODE) \ - (TREE_LANG_FLAG_2 (VAR_DECL_CHECK (NODE))) - -/* Nonzero if the DECL was initialized in the class definition itself, - rather than outside the class. This is used for both static member - VAR_DECLS, and FUNCTION_DECLS that are defined in the class. */ -#define DECL_INITIALIZED_IN_CLASS_P(DECL) \ - (DECL_LANG_SPECIFIC (VAR_OR_FUNCTION_DECL_CHECK (DECL)) \ - ->u.base.initialized_in_class) - -/* Nonzero if the DECL is used in the sense of 3.2 [basic.def.odr]. - Only available for decls with DECL_LANG_SPECIFIC. */ -#define DECL_ODR_USED(DECL) \ - (DECL_LANG_SPECIFIC (VAR_OR_FUNCTION_DECL_CHECK (DECL)) \ - ->u.base.odr_used) - -/* Nonzero for DECL means that this decl is just a friend declaration, - and should not be added to the list of members for this class. */ -#define DECL_FRIEND_P(NODE) \ - (DECL_LANG_SPECIFIC (TYPE_FUNCTION_OR_TEMPLATE_DECL_CHECK (NODE)) \ - ->u.base.friend_attr) - -/* A TREE_LIST of the types which have befriended this FUNCTION_DECL. */ -#define DECL_BEFRIENDING_CLASSES(NODE) \ - (LANG_DECL_FN_CHECK (NODE)->befriending_classes) - -/* Nonzero for FUNCTION_DECL means that this decl is a static - member function. */ -#define DECL_STATIC_FUNCTION_P(NODE) \ - (LANG_DECL_FN_CHECK (NODE)->static_function) - -/* Nonzero for FUNCTION_DECL means that this decl is a non-static - member function. */ -#define DECL_NONSTATIC_MEMBER_FUNCTION_P(NODE) \ - (TREE_CODE (TREE_TYPE (NODE)) == METHOD_TYPE) - -/* Nonzero for FUNCTION_DECL means that this decl is a member function - (static or non-static). */ -#define DECL_FUNCTION_MEMBER_P(NODE) \ - (DECL_NONSTATIC_MEMBER_FUNCTION_P (NODE) || DECL_STATIC_FUNCTION_P (NODE)) - -/* Nonzero for FUNCTION_DECL means that this member function - has `this' as const X *const. */ -#define DECL_CONST_MEMFUNC_P(NODE) \ - (DECL_NONSTATIC_MEMBER_FUNCTION_P (NODE) \ - && CP_TYPE_CONST_P (TREE_TYPE (TREE_VALUE \ - (TYPE_ARG_TYPES (TREE_TYPE (NODE)))))) - -/* Nonzero for FUNCTION_DECL means that this member function - has `this' as volatile X *const. */ -#define DECL_VOLATILE_MEMFUNC_P(NODE) \ - (DECL_NONSTATIC_MEMBER_FUNCTION_P (NODE) \ - && CP_TYPE_VOLATILE_P (TREE_TYPE (TREE_VALUE \ - (TYPE_ARG_TYPES (TREE_TYPE (NODE)))))) - -/* Nonzero for a DECL means that this member is a non-static member. */ -#define DECL_NONSTATIC_MEMBER_P(NODE) \ - (DECL_NONSTATIC_MEMBER_FUNCTION_P (NODE) \ - || TREE_CODE (NODE) == FIELD_DECL) - -/* Nonzero for _DECL means that this member object type - is mutable. */ -#define DECL_MUTABLE_P(NODE) (DECL_LANG_FLAG_0 (NODE)) - -/* Nonzero for _DECL means that this constructor or conversion function is - non-converting. */ -#define DECL_NONCONVERTING_P(NODE) \ - (LANG_DECL_FN_CHECK (NODE)->nonconverting) - -/* Nonzero for FUNCTION_DECL means that this member function is a pure - virtual function. */ -#define DECL_PURE_VIRTUAL_P(NODE) \ - (LANG_DECL_FN_CHECK (NODE)->pure_virtual) - -/* True (in a FUNCTION_DECL) if NODE is a virtual function that is an - invalid overrider for a function from a base class. Once we have - complained about an invalid overrider we avoid complaining about it - again. */ -#define DECL_INVALID_OVERRIDER_P(NODE) \ - (DECL_LANG_FLAG_4 (NODE)) - -/* True (in a FUNCTION_DECL) if NODE is a function declared with - an override virt-specifier */ -#define DECL_OVERRIDE_P(NODE) (TREE_LANG_FLAG_0 (NODE)) - -/* The thunks associated with NODE, a FUNCTION_DECL. */ -#define DECL_THUNKS(NODE) \ - (DECL_VIRTUAL_P (NODE) ? LANG_DECL_FN_CHECK (NODE)->context : NULL_TREE) - -/* Set DECL_THUNKS. */ -#define SET_DECL_THUNKS(NODE,THUNKS) \ - (LANG_DECL_FN_CHECK (NODE)->context = (THUNKS)) - -/* If NODE, a FUNCTION_DECL, is a C++11 inheriting constructor, then this - is the base it inherits from. */ -#define DECL_INHERITED_CTOR_BASE(NODE) \ - (DECL_CONSTRUCTOR_P (NODE) ? LANG_DECL_FN_CHECK (NODE)->context : NULL_TREE) - -/* Set the inherited base. */ -#define SET_DECL_INHERITED_CTOR_BASE(NODE,INH) \ - (LANG_DECL_FN_CHECK (NODE)->context = (INH)) - -/* Nonzero if NODE is a thunk, rather than an ordinary function. */ -#define DECL_THUNK_P(NODE) \ - (TREE_CODE (NODE) == FUNCTION_DECL \ - && DECL_LANG_SPECIFIC (NODE) \ - && LANG_DECL_FN_CHECK (NODE)->thunk_p) - -/* Set DECL_THUNK_P for node. */ -#define SET_DECL_THUNK_P(NODE, THIS_ADJUSTING) \ - (LANG_DECL_FN_CHECK (NODE)->thunk_p = 1, \ - LANG_DECL_FN_CHECK (NODE)->this_thunk_p = (THIS_ADJUSTING)) - -/* Nonzero if NODE is a this pointer adjusting thunk. */ -#define DECL_THIS_THUNK_P(NODE) \ - (DECL_THUNK_P (NODE) && LANG_DECL_FN_CHECK (NODE)->this_thunk_p) - -/* Nonzero if NODE is a result pointer adjusting thunk. */ -#define DECL_RESULT_THUNK_P(NODE) \ - (DECL_THUNK_P (NODE) && !LANG_DECL_FN_CHECK (NODE)->this_thunk_p) - -/* Nonzero if NODE is a FUNCTION_DECL, but not a thunk. */ -#define DECL_NON_THUNK_FUNCTION_P(NODE) \ - (TREE_CODE (NODE) == FUNCTION_DECL && !DECL_THUNK_P (NODE)) - -/* Nonzero if NODE is `extern "C"'. */ -#define DECL_EXTERN_C_P(NODE) \ - (DECL_LANGUAGE (NODE) == lang_c) - -/* Nonzero if NODE is an `extern "C"' function. */ -#define DECL_EXTERN_C_FUNCTION_P(NODE) \ - (DECL_NON_THUNK_FUNCTION_P (NODE) && DECL_EXTERN_C_P (NODE)) - -/* True iff DECL is an entity with vague linkage whose definition is - available in this translation unit. */ -#define DECL_REPO_AVAILABLE_P(NODE) \ - (DECL_LANG_SPECIFIC (NODE)->u.base.repo_available_p) - -/* True if DECL is declared 'constexpr'. */ -#define DECL_DECLARED_CONSTEXPR_P(DECL) \ - DECL_LANG_FLAG_8 (VAR_OR_FUNCTION_DECL_CHECK (STRIP_TEMPLATE (DECL))) - -/* Nonzero if this DECL is the __PRETTY_FUNCTION__ variable in a - template function. */ -#define DECL_PRETTY_FUNCTION_P(NODE) \ - (DECL_NAME (NODE) \ - && !strcmp (IDENTIFIER_POINTER (DECL_NAME (NODE)), "__PRETTY_FUNCTION__")) - -/* Nonzero if the thread-local variable was declared with __thread - as opposed to thread_local. */ -#define DECL_GNU_TLS_P(NODE) \ - (TREE_LANG_FLAG_0 (VAR_DECL_CHECK (NODE))) - -/* The _TYPE context in which this _DECL appears. This field holds the - class where a virtual function instance is actually defined. */ -#define DECL_CLASS_CONTEXT(NODE) \ - (DECL_CLASS_SCOPE_P (NODE) ? DECL_CONTEXT (NODE) : NULL_TREE) - -/* For a non-member friend function, the class (if any) in which this - friend was defined. For example, given: - - struct S { friend void f (); }; - - the DECL_FRIEND_CONTEXT for `f' will be `S'. */ -#define DECL_FRIEND_CONTEXT(NODE) \ - ((DECL_DECLARES_FUNCTION_P (NODE) \ - && DECL_FRIEND_P (NODE) && !DECL_FUNCTION_MEMBER_P (NODE)) \ - ? LANG_DECL_FN_CHECK (NODE)->context \ - : NULL_TREE) - -/* Set the DECL_FRIEND_CONTEXT for NODE to CONTEXT. */ -#define SET_DECL_FRIEND_CONTEXT(NODE, CONTEXT) \ - (LANG_DECL_FN_CHECK (NODE)->context = (CONTEXT)) - -#define CP_DECL_CONTEXT(NODE) \ - (!DECL_FILE_SCOPE_P (NODE) ? DECL_CONTEXT (NODE) : global_namespace) -#define CP_TYPE_CONTEXT(NODE) \ - (!TYPE_FILE_SCOPE_P (NODE) ? TYPE_CONTEXT (NODE) : global_namespace) -#define FROB_CONTEXT(NODE) \ - ((NODE) == global_namespace ? DECL_CONTEXT (NODE) : (NODE)) - -/* 1 iff NODE has namespace scope, including the global namespace. */ -#define DECL_NAMESPACE_SCOPE_P(NODE) \ - (!DECL_TEMPLATE_PARM_P (NODE) \ - && TREE_CODE (CP_DECL_CONTEXT (NODE)) == NAMESPACE_DECL) - -#define TYPE_NAMESPACE_SCOPE_P(NODE) \ - (TREE_CODE (CP_TYPE_CONTEXT (NODE)) == NAMESPACE_DECL) - -#define NAMESPACE_SCOPE_P(NODE) \ - ((DECL_P (NODE) && DECL_NAMESPACE_SCOPE_P (NODE)) \ - || (TYPE_P (NODE) && TYPE_NAMESPACE_SCOPE_P (NODE))) - -/* 1 iff NODE is a class member. */ -#define DECL_CLASS_SCOPE_P(NODE) \ - (DECL_CONTEXT (NODE) && TYPE_P (DECL_CONTEXT (NODE))) - -#define TYPE_CLASS_SCOPE_P(NODE) \ - (TYPE_CONTEXT (NODE) && TYPE_P (TYPE_CONTEXT (NODE))) - -/* 1 iff NODE is function-local. */ -#define DECL_FUNCTION_SCOPE_P(NODE) \ - (DECL_CONTEXT (NODE) \ - && TREE_CODE (DECL_CONTEXT (NODE)) == FUNCTION_DECL) - -#define TYPE_FUNCTION_SCOPE_P(NODE) \ - (TYPE_CONTEXT (NODE) && TREE_CODE (TYPE_CONTEXT (NODE)) == FUNCTION_DECL) - -/* 1 iff VAR_DECL node NODE is a type-info decl. This flag is set for - both the primary typeinfo object and the associated NTBS name. */ -#define DECL_TINFO_P(NODE) TREE_LANG_FLAG_4 (VAR_DECL_CHECK (NODE)) - -/* 1 iff VAR_DECL node NODE is virtual table or VTT. */ -#define DECL_VTABLE_OR_VTT_P(NODE) TREE_LANG_FLAG_5 (VAR_DECL_CHECK (NODE)) - -/* 1 iff FUNCTION_TYPE or METHOD_TYPE has a ref-qualifier (either & or &&). */ -#define FUNCTION_REF_QUALIFIED(NODE) \ - TREE_LANG_FLAG_4 (FUNC_OR_METHOD_CHECK (NODE)) - -/* 1 iff FUNCTION_TYPE or METHOD_TYPE has &&-ref-qualifier. */ -#define FUNCTION_RVALUE_QUALIFIED(NODE) \ - TREE_LANG_FLAG_5 (FUNC_OR_METHOD_CHECK (NODE)) - -/* Returns 1 iff VAR_DECL is a construction virtual table. - DECL_VTABLE_OR_VTT_P will be true in this case and must be checked - before using this macro. */ -#define DECL_CONSTRUCTION_VTABLE_P(NODE) \ - TREE_LANG_FLAG_6 (VAR_DECL_CHECK (NODE)) - -/* 1 iff NODE is function-local, but for types. */ -#define LOCAL_CLASS_P(NODE) \ - (decl_function_context (TYPE_MAIN_DECL (NODE)) != NULL_TREE) - -/* For a NAMESPACE_DECL: the list of using namespace directives - The PURPOSE is the used namespace, the value is the namespace - that is the common ancestor. */ -#define DECL_NAMESPACE_USING(NODE) (LANG_DECL_NS_CHECK (NODE)->ns_using) - -/* In a NAMESPACE_DECL, the DECL_INITIAL is used to record all users - of a namespace, to record the transitive closure of using namespace. */ -#define DECL_NAMESPACE_USERS(NODE) (LANG_DECL_NS_CHECK (NODE)->ns_users) - -/* In a NAMESPACE_DECL, the list of namespaces which have associated - themselves with this one. */ -#define DECL_NAMESPACE_ASSOCIATIONS(NODE) \ - DECL_INITIAL (NAMESPACE_DECL_CHECK (NODE)) - -/* In a NAMESPACE_DECL, points to the original namespace if this is - a namespace alias. */ -#define DECL_NAMESPACE_ALIAS(NODE) \ - DECL_ABSTRACT_ORIGIN (NAMESPACE_DECL_CHECK (NODE)) -#define ORIGINAL_NAMESPACE(NODE) \ - (DECL_NAMESPACE_ALIAS (NODE) ? DECL_NAMESPACE_ALIAS (NODE) : (NODE)) - -/* Nonzero if NODE is the std namespace. */ -#define DECL_NAMESPACE_STD_P(NODE) \ - (TREE_CODE (NODE) == NAMESPACE_DECL \ - && CP_DECL_CONTEXT (NODE) == global_namespace \ - && DECL_NAME (NODE) == std_identifier) - -/* In a TREE_LIST concatenating using directives, indicate indirect - directives */ -#define TREE_INDIRECT_USING(NODE) TREE_LANG_FLAG_0 (TREE_LIST_CHECK (NODE)) - -/* In a TREE_LIST in an attribute list, indicates that the attribute - must be applied at instantiation time. */ -#define ATTR_IS_DEPENDENT(NODE) TREE_LANG_FLAG_0 (TREE_LIST_CHECK (NODE)) - -/* In a TREE_LIST in the argument of attribute abi_tag, indicates that the tag - was inherited from a template parameter, not explicitly indicated. */ -#define ABI_TAG_IMPLICIT(NODE) TREE_LANG_FLAG_0 (TREE_LIST_CHECK (NODE)) - -extern tree decl_shadowed_for_var_lookup (tree); -extern void decl_shadowed_for_var_insert (tree, tree); - -/* Non zero if this is a using decl for a dependent scope. */ -#define DECL_DEPENDENT_P(NODE) DECL_LANG_FLAG_0 (USING_DECL_CHECK (NODE)) - -/* The scope named in a using decl. */ -#define USING_DECL_SCOPE(NODE) TREE_TYPE (USING_DECL_CHECK (NODE)) - -/* The decls named by a using decl. */ -#define USING_DECL_DECLS(NODE) DECL_INITIAL (USING_DECL_CHECK (NODE)) - -/* Non zero if the using decl refers to a dependent type. */ -#define USING_DECL_TYPENAME_P(NODE) DECL_LANG_FLAG_1 (USING_DECL_CHECK (NODE)) - -/* In a VAR_DECL, true if we have a shadowed local variable - in the shadowed var table for this VAR_DECL. */ -#define DECL_HAS_SHADOWED_FOR_VAR_P(NODE) \ - (VAR_DECL_CHECK (NODE)->decl_with_vis.shadowed_for_var_p) - -/* In a VAR_DECL for a variable declared in a for statement, - this is the shadowed (local) variable. */ -#define DECL_SHADOWED_FOR_VAR(NODE) \ - (DECL_HAS_SHADOWED_FOR_VAR_P(NODE) ? decl_shadowed_for_var_lookup (NODE) : NULL) - -#define SET_DECL_SHADOWED_FOR_VAR(NODE, VAL) \ - (decl_shadowed_for_var_insert (NODE, VAL)) - -/* In a FUNCTION_DECL, this is nonzero if this function was defined in - the class definition. We have saved away the text of the function, - but have not yet processed it. */ -#define DECL_PENDING_INLINE_P(NODE) \ - (LANG_DECL_FN_CHECK (NODE)->pending_inline_p) - -/* If DECL_PENDING_INLINE_P holds, this is the saved text of the - function. */ -#define DECL_PENDING_INLINE_INFO(NODE) \ - (LANG_DECL_FN_CHECK (NODE)->u.pending_inline_info) - -/* Nonzero for TYPE_DECL means that it was written 'using name = type'. */ -#define TYPE_DECL_ALIAS_P(NODE) \ - DECL_LANG_FLAG_6 (TYPE_DECL_CHECK (NODE)) - -/* Nonzero for TEMPLATE_DECL means that it is a 'complex' alias template. */ -#define TEMPLATE_DECL_COMPLEX_ALIAS_P(NODE) \ - DECL_LANG_FLAG_2 (TEMPLATE_DECL_CHECK (NODE)) - -/* Nonzero for a type which is an alias for another type; i.e, a type - which declaration was written 'using name-of-type = - another-type'. */ -#define TYPE_ALIAS_P(NODE) \ - (TYPE_P (NODE) \ - && TYPE_NAME (NODE) \ - && TREE_CODE (TYPE_NAME (NODE)) == TYPE_DECL \ - && TYPE_DECL_ALIAS_P (TYPE_NAME (NODE))) - -/* For a class type: if this structure has many fields, we'll sort them - and put them into a TREE_VEC. */ -#define CLASSTYPE_SORTED_FIELDS(NODE) \ - (LANG_TYPE_CLASS_CHECK (NODE)->sorted_fields) - -/* If non-NULL for a VAR_DECL, FUNCTION_DECL, TYPE_DECL or - TEMPLATE_DECL, the entity is either a template specialization (if - DECL_USE_TEMPLATE is nonzero) or the abstract instance of the - template itself. - - In either case, DECL_TEMPLATE_INFO is a TREE_LIST, whose - TREE_PURPOSE is the TEMPLATE_DECL of which this entity is a - specialization or abstract instance. The TREE_VALUE is the - template arguments used to specialize the template. - - Consider: - - template struct S { friend void f(T) {} }; - - In this case, S::f is, from the point of view of the compiler, - an instantiation of a template -- but, from the point of view of - the language, each instantiation of S results in a wholly unrelated - global function f. In this case, DECL_TEMPLATE_INFO for S::f - will be non-NULL, but DECL_USE_TEMPLATE will be zero. */ -#define DECL_TEMPLATE_INFO(NODE) \ - (DECL_LANG_SPECIFIC (VAR_TEMPL_TYPE_FIELD_OR_FUNCTION_DECL_CHECK (NODE)) \ - ->u.min.template_info) - -/* For a VAR_DECL, indicates that the variable is actually a - non-static data member of anonymous union that has been promoted to - variable status. */ -#define DECL_ANON_UNION_VAR_P(NODE) \ - (DECL_LANG_FLAG_4 (VAR_DECL_CHECK (NODE))) - -/* Template information for a RECORD_TYPE or UNION_TYPE. */ -#define CLASSTYPE_TEMPLATE_INFO(NODE) \ - (LANG_TYPE_CLASS_CHECK (RECORD_OR_UNION_CHECK (NODE))->template_info) - -/* Template information for an ENUMERAL_TYPE. Although an enumeration may - not be a primary template, it may be declared within the scope of a - primary template and the enumeration constants may depend on - non-type template parameters. */ -#define ENUM_TEMPLATE_INFO(NODE) \ - (TYPE_LANG_SLOT_1 (ENUMERAL_TYPE_CHECK (NODE))) - -/* Template information for a template template parameter. */ -#define TEMPLATE_TEMPLATE_PARM_TEMPLATE_INFO(NODE) \ - (LANG_TYPE_CLASS_CHECK (BOUND_TEMPLATE_TEMPLATE_PARM_TYPE_CHECK (NODE)) \ - ->template_info) - -/* Template information for an ENUMERAL_, RECORD_, UNION_TYPE, or - BOUND_TEMPLATE_TEMPLATE_PARM type. Note that if NODE is a - specialization of an alias template, this accessor returns the - template info for the alias template, not the one (if any) for the - template of the underlying type. */ -#define TYPE_TEMPLATE_INFO(NODE) \ - ((TYPE_ALIAS_P (NODE) && DECL_LANG_SPECIFIC (TYPE_NAME (NODE))) \ - ? (DECL_LANG_SPECIFIC (TYPE_NAME (NODE)) \ - ? DECL_TEMPLATE_INFO (TYPE_NAME (NODE)) \ - : NULL_TREE) \ - : ((TREE_CODE (NODE) == ENUMERAL_TYPE) \ - ? ENUM_TEMPLATE_INFO (NODE) \ - : ((TREE_CODE (NODE) == BOUND_TEMPLATE_TEMPLATE_PARM) \ - ? TEMPLATE_TEMPLATE_PARM_TEMPLATE_INFO (NODE) \ - : (CLASS_TYPE_P (NODE) \ - ? CLASSTYPE_TEMPLATE_INFO (NODE) \ - : NULL_TREE)))) - - -/* Set the template information for an ENUMERAL_, RECORD_, or - UNION_TYPE to VAL. */ -#define SET_TYPE_TEMPLATE_INFO(NODE, VAL) \ - (TREE_CODE (NODE) == ENUMERAL_TYPE \ - ? (ENUM_TEMPLATE_INFO (NODE) = (VAL)) \ - : ((CLASS_TYPE_P (NODE) && !TYPE_ALIAS_P (NODE)) \ - ? (CLASSTYPE_TEMPLATE_INFO (NODE) = (VAL)) \ - : (DECL_TEMPLATE_INFO (TYPE_NAME (NODE)) = (VAL)))) - -#define TI_TEMPLATE(NODE) TREE_TYPE (TEMPLATE_INFO_CHECK (NODE)) -#define TI_ARGS(NODE) TREE_CHAIN (TEMPLATE_INFO_CHECK (NODE)) -#define TI_PENDING_TEMPLATE_FLAG(NODE) TREE_LANG_FLAG_1 (NODE) -/* For a given TREE_VEC containing a template argument list, - this property contains the number of arguments that are not - defaulted. */ -#define NON_DEFAULT_TEMPLATE_ARGS_COUNT(NODE) TREE_CHAIN (TREE_VEC_CHECK (NODE)) -/* Below are the setter and getter of the NON_DEFAULT_TEMPLATE_ARGS_COUNT - property. */ -#define SET_NON_DEFAULT_TEMPLATE_ARGS_COUNT(NODE, INT_VALUE) \ - NON_DEFAULT_TEMPLATE_ARGS_COUNT(NODE) = build_int_cst (NULL_TREE, INT_VALUE) -#ifdef ENABLE_CHECKING -#define GET_NON_DEFAULT_TEMPLATE_ARGS_COUNT(NODE) \ - int_cst_value (NON_DEFAULT_TEMPLATE_ARGS_COUNT (NODE)) -#else -#define GET_NON_DEFAULT_TEMPLATE_ARGS_COUNT(NODE) \ - NON_DEFAULT_TEMPLATE_ARGS_COUNT (NODE) \ - ? int_cst_value (NON_DEFAULT_TEMPLATE_ARGS_COUNT (NODE)) \ - : TREE_VEC_LENGTH (INNERMOST_TEMPLATE_ARGS (NODE)) -#endif -/* The list of typedefs - used in the template - that need - access checking at template instantiation time. - - FIXME this should be associated with the TEMPLATE_DECL, not the - TEMPLATE_INFO. */ -#define TI_TYPEDEFS_NEEDING_ACCESS_CHECKING(NODE) \ - ((struct tree_template_info*)TEMPLATE_INFO_CHECK \ - (NODE))->typedefs_needing_access_checking - -/* We use TREE_VECs to hold template arguments. If there is only one - level of template arguments, then the TREE_VEC contains the - arguments directly. If there is more than one level of template - arguments, then each entry in the TREE_VEC is itself a TREE_VEC, - containing the template arguments for a single level. The first - entry in the outer TREE_VEC is the outermost level of template - parameters; the last is the innermost. - - It is incorrect to ever form a template argument vector containing - only one level of arguments, but which is a TREE_VEC containing as - its only entry the TREE_VEC for that level. - - For each TREE_VEC containing the template arguments for a single - level, it's possible to get or set the number of non defaulted - template arguments by using the accessor macros - GET_NON_DEFAULT_TEMPLATE_ARGS_COUNT or - SET_NON_DEFAULT_TEMPLATE_ARGS_COUNT. */ - -/* Nonzero if the template arguments is actually a vector of vectors, - rather than just a vector. */ -#define TMPL_ARGS_HAVE_MULTIPLE_LEVELS(NODE) \ - (NODE && TREE_VEC_LENGTH (NODE) && TREE_VEC_ELT (NODE, 0) \ - && TREE_CODE (TREE_VEC_ELT (NODE, 0)) == TREE_VEC) - -/* The depth of a template argument vector. When called directly by - the parser, we use a TREE_LIST rather than a TREE_VEC to represent - template arguments. In fact, we may even see NULL_TREE if there - are no template arguments. In both of those cases, there is only - one level of template arguments. */ -#define TMPL_ARGS_DEPTH(NODE) \ - (TMPL_ARGS_HAVE_MULTIPLE_LEVELS (NODE) ? TREE_VEC_LENGTH (NODE) : 1) - -/* The LEVELth level of the template ARGS. The outermost level of - args is level 1, not level 0. */ -#define TMPL_ARGS_LEVEL(ARGS, LEVEL) \ - (TMPL_ARGS_HAVE_MULTIPLE_LEVELS (ARGS) \ - ? TREE_VEC_ELT (ARGS, (LEVEL) - 1) : (ARGS)) - -/* Set the LEVELth level of the template ARGS to VAL. This macro does - not work with single-level argument vectors. */ -#define SET_TMPL_ARGS_LEVEL(ARGS, LEVEL, VAL) \ - (TREE_VEC_ELT (ARGS, (LEVEL) - 1) = (VAL)) - -/* Accesses the IDXth parameter in the LEVELth level of the ARGS. */ -#define TMPL_ARG(ARGS, LEVEL, IDX) \ - (TREE_VEC_ELT (TMPL_ARGS_LEVEL (ARGS, LEVEL), IDX)) - -/* Given a single level of template arguments in NODE, return the - number of arguments. */ -#define NUM_TMPL_ARGS(NODE) \ - (TREE_VEC_LENGTH (NODE)) - -/* Returns the innermost level of template arguments in ARGS. */ -#define INNERMOST_TEMPLATE_ARGS(NODE) \ - (get_innermost_template_args ((NODE), 1)) - -/* The number of levels of template parameters given by NODE. */ -#define TMPL_PARMS_DEPTH(NODE) \ - ((HOST_WIDE_INT) TREE_INT_CST_LOW (TREE_PURPOSE (NODE))) - -/* The TEMPLATE_DECL instantiated or specialized by NODE. This - TEMPLATE_DECL will be the immediate parent, not the most general - template. For example, in: - - template struct S { template void f(U); } - - the FUNCTION_DECL for S::f will have, as its - DECL_TI_TEMPLATE, `template S::f'. - - As a special case, for a member friend template of a template - class, this value will not be a TEMPLATE_DECL, but rather an - IDENTIFIER_NODE or OVERLOAD indicating the name of the template and - any explicit template arguments provided. For example, in: - - template struct S { friend void f(int, double); } - - the DECL_TI_TEMPLATE will be an IDENTIFIER_NODE for `f' and the - DECL_TI_ARGS will be {int}. - - For a FIELD_DECL with a non-static data member initializer, this value - is the FIELD_DECL it was instantiated from. */ -#define DECL_TI_TEMPLATE(NODE) TI_TEMPLATE (DECL_TEMPLATE_INFO (NODE)) - -/* The template arguments used to obtain this decl from the most - general form of DECL_TI_TEMPLATE. For the example given for - DECL_TI_TEMPLATE, the DECL_TI_ARGS will be {int, double}. These - are always the full set of arguments required to instantiate this - declaration from the most general template specialized here. */ -#define DECL_TI_ARGS(NODE) TI_ARGS (DECL_TEMPLATE_INFO (NODE)) - -/* The TEMPLATE_DECL associated with NODE, a class type. Even if NODE - will be generated from a partial specialization, the TEMPLATE_DECL - referred to here will be the original template. For example, - given: - - template struct S {}; - template struct S {}; - - the CLASSTPYE_TI_TEMPLATE for S will be S, not the S. */ -#define CLASSTYPE_TI_TEMPLATE(NODE) TI_TEMPLATE (CLASSTYPE_TEMPLATE_INFO (NODE)) -#define CLASSTYPE_TI_ARGS(NODE) TI_ARGS (CLASSTYPE_TEMPLATE_INFO (NODE)) - -/* For a template instantiation TYPE, returns the TYPE corresponding - to the primary template. Otherwise returns TYPE itself. */ -#define CLASSTYPE_PRIMARY_TEMPLATE_TYPE(TYPE) \ - ((CLASSTYPE_USE_TEMPLATE ((TYPE)) \ - && !CLASSTYPE_TEMPLATE_SPECIALIZATION ((TYPE))) \ - ? TREE_TYPE (DECL_TEMPLATE_RESULT (DECL_PRIMARY_TEMPLATE \ - (CLASSTYPE_TI_TEMPLATE ((TYPE))))) \ - : (TYPE)) - -/* Like CLASS_TI_TEMPLATE, but also works for ENUMERAL_TYPEs. */ -#define TYPE_TI_TEMPLATE(NODE) \ - (TI_TEMPLATE (TYPE_TEMPLATE_INFO (NODE))) - -/* Like DECL_TI_ARGS, but for an ENUMERAL_, RECORD_, or UNION_TYPE. */ -#define TYPE_TI_ARGS(NODE) \ - (TI_ARGS (TYPE_TEMPLATE_INFO (NODE))) - -#define INNERMOST_TEMPLATE_PARMS(NODE) TREE_VALUE (NODE) - -/* Nonzero if NODE (a TEMPLATE_DECL) is a member template, in the - sense of [temp.mem]. */ -#define DECL_MEMBER_TEMPLATE_P(NODE) \ - (DECL_LANG_FLAG_1 (TEMPLATE_DECL_CHECK (NODE))) - -/* Nonzero if the NODE corresponds to the template parameters for a - member template, whose inline definition is being processed after - the class definition is complete. */ -#define TEMPLATE_PARMS_FOR_INLINE(NODE) TREE_LANG_FLAG_1 (NODE) - -/* Determine if a declaration (PARM_DECL or FIELD_DECL) is a pack. */ -#define DECL_PACK_P(NODE) \ - (DECL_P (NODE) && PACK_EXPANSION_P (TREE_TYPE (NODE))) - -/* Determines if NODE is an expansion of one or more parameter packs, - e.g., a TYPE_PACK_EXPANSION or EXPR_PACK_EXPANSION. */ -#define PACK_EXPANSION_P(NODE) \ - (TREE_CODE (NODE) == TYPE_PACK_EXPANSION \ - || TREE_CODE (NODE) == EXPR_PACK_EXPANSION) - -/* Extracts the type or expression pattern from a TYPE_PACK_EXPANSION or - EXPR_PACK_EXPANSION. */ -#define PACK_EXPANSION_PATTERN(NODE) \ - (TREE_CODE (NODE) == TYPE_PACK_EXPANSION? TREE_TYPE (NODE) \ - : TREE_OPERAND (NODE, 0)) - -/* Sets the type or expression pattern for a TYPE_PACK_EXPANSION or - EXPR_PACK_EXPANSION. */ -#define SET_PACK_EXPANSION_PATTERN(NODE,VALUE) \ - if (TREE_CODE (NODE) == TYPE_PACK_EXPANSION) \ - TREE_TYPE (NODE) = VALUE; \ - else \ - TREE_OPERAND (NODE, 0) = VALUE - -/* The list of parameter packs used in the PACK_EXPANSION_* node. The - TREE_VALUE of each TREE_LIST contains the parameter packs. */ -#define PACK_EXPANSION_PARAMETER_PACKS(NODE) \ - *(TREE_CODE (NODE) == EXPR_PACK_EXPANSION \ - ? &TREE_OPERAND (NODE, 1) \ - : &TYPE_MINVAL (TYPE_PACK_EXPANSION_CHECK (NODE))) - -/* Any additional template args to be applied when substituting into - the pattern, set by tsubst_pack_expansion for partial instantiations. */ -#define PACK_EXPANSION_EXTRA_ARGS(NODE) \ - *(TREE_CODE (NODE) == TYPE_PACK_EXPANSION \ - ? &TYPE_MAXVAL (NODE) \ - : &TREE_OPERAND ((NODE), 2)) - -/* True iff this pack expansion is within a function context. */ -#define PACK_EXPANSION_LOCAL_P(NODE) TREE_LANG_FLAG_0 (NODE) - -/* True iff this pack expansion is for sizeof.... */ -#define PACK_EXPANSION_SIZEOF_P(NODE) TREE_LANG_FLAG_1 (NODE) - -/* Determine if this is an argument pack. */ -#define ARGUMENT_PACK_P(NODE) \ - (TREE_CODE (NODE) == TYPE_ARGUMENT_PACK \ - || TREE_CODE (NODE) == NONTYPE_ARGUMENT_PACK) - -/* The arguments stored in an argument pack. Arguments are stored in a - TREE_VEC, which may have length zero. */ -#define ARGUMENT_PACK_ARGS(NODE) \ - (TREE_CODE (NODE) == TYPE_ARGUMENT_PACK? TREE_TYPE (NODE) \ - : TREE_OPERAND (NODE, 0)) - -/* Set the arguments stored in an argument pack. VALUE must be a - TREE_VEC. */ -#define SET_ARGUMENT_PACK_ARGS(NODE,VALUE) \ - if (TREE_CODE (NODE) == TYPE_ARGUMENT_PACK) \ - TREE_TYPE (NODE) = VALUE; \ - else \ - TREE_OPERAND (NODE, 0) = VALUE - -/* Whether the argument pack is "incomplete", meaning that more - arguments can still be deduced. Incomplete argument packs are only - used when the user has provided an explicit template argument list - for a variadic function template. Some of the explicit template - arguments will be placed into the beginning of the argument pack, - but additional arguments might still be deduced. */ -#define ARGUMENT_PACK_INCOMPLETE_P(NODE) \ - TREE_ADDRESSABLE (ARGUMENT_PACK_ARGS (NODE)) - -/* When ARGUMENT_PACK_INCOMPLETE_P, stores the explicit template - arguments used to fill this pack. */ -#define ARGUMENT_PACK_EXPLICIT_ARGS(NODE) \ - TREE_TYPE (ARGUMENT_PACK_ARGS (NODE)) - -/* In an ARGUMENT_PACK_SELECT, the argument pack from which an - argument will be selected. */ -#define ARGUMENT_PACK_SELECT_FROM_PACK(NODE) \ - (((struct tree_argument_pack_select *)ARGUMENT_PACK_SELECT_CHECK (NODE))->argument_pack) - -/* In an ARGUMENT_PACK_SELECT, the index of the argument we want to - select. */ -#define ARGUMENT_PACK_SELECT_INDEX(NODE) \ - (((struct tree_argument_pack_select *)ARGUMENT_PACK_SELECT_CHECK (NODE))->index) - -/* In an ARGUMENT_PACK_SELECT, the actual underlying argument that the - ARGUMENT_PACK_SELECT represents. */ -#define ARGUMENT_PACK_SELECT_ARG(NODE) \ - TREE_VEC_ELT (ARGUMENT_PACK_ARGS (ARGUMENT_PACK_SELECT_FROM_PACK (NODE)), \ - ARGUMENT_PACK_SELECT_INDEX (NODE)); - -/* In a FUNCTION_DECL, the saved language-specific per-function data. */ -#define DECL_SAVED_FUNCTION_DATA(NODE) \ - (LANG_DECL_FN_CHECK (FUNCTION_DECL_CHECK (NODE)) \ - ->u.saved_language_function) - -/* True if NODE is an implicit INDIRECT_EXPR from convert_from_reference. */ -#define REFERENCE_REF_P(NODE) \ - (INDIRECT_REF_P (NODE) \ - && TREE_TYPE (TREE_OPERAND (NODE, 0)) \ - && (TREE_CODE (TREE_TYPE (TREE_OPERAND ((NODE), 0))) \ - == REFERENCE_TYPE)) - -/* True if NODE is a REFERENCE_TYPE which is OK to instantiate to be a - reference to VLA type, because it's used for VLA capture. */ -#define REFERENCE_VLA_OK(NODE) \ - (TYPE_LANG_FLAG_5 (REFERENCE_TYPE_CHECK (NODE))) - -#define NEW_EXPR_USE_GLOBAL(NODE) \ - TREE_LANG_FLAG_0 (NEW_EXPR_CHECK (NODE)) -#define DELETE_EXPR_USE_GLOBAL(NODE) \ - TREE_LANG_FLAG_0 (DELETE_EXPR_CHECK (NODE)) -#define DELETE_EXPR_USE_VEC(NODE) \ - TREE_LANG_FLAG_1 (DELETE_EXPR_CHECK (NODE)) - -/* Indicates that this is a non-dependent COMPOUND_EXPR which will - resolve to a function call. */ -#define COMPOUND_EXPR_OVERLOADED(NODE) \ - TREE_LANG_FLAG_0 (COMPOUND_EXPR_CHECK (NODE)) - -/* In a CALL_EXPR appearing in a template, true if Koenig lookup - should be performed at instantiation time. */ -#define KOENIG_LOOKUP_P(NODE) TREE_LANG_FLAG_0 (CALL_EXPR_CHECK (NODE)) - -/* True if CALL_EXPR expresses list-initialization of an object. */ -#define CALL_EXPR_LIST_INIT_P(NODE) \ - TREE_LANG_FLAG_3 (TREE_CHECK2 ((NODE),CALL_EXPR,AGGR_INIT_EXPR)) - -/* Indicates whether a string literal has been parenthesized. Such - usages are disallowed in certain circumstances. */ - -#define PAREN_STRING_LITERAL_P(NODE) \ - TREE_LANG_FLAG_0 (STRING_CST_CHECK (NODE)) - -/* Indicates whether a COMPONENT_REF has been parenthesized, or an - INDIRECT_REF comes from parenthesizing a VAR_DECL. Currently only set - some of the time in C++14 mode. */ - -#define REF_PARENTHESIZED_P(NODE) \ - TREE_LANG_FLAG_2 (TREE_CHECK2 ((NODE), COMPONENT_REF, INDIRECT_REF)) - -/* Nonzero if this AGGR_INIT_EXPR provides for initialization via a - constructor call, rather than an ordinary function call. */ -#define AGGR_INIT_VIA_CTOR_P(NODE) \ - TREE_LANG_FLAG_0 (AGGR_INIT_EXPR_CHECK (NODE)) - -/* Nonzero if expanding this AGGR_INIT_EXPR should first zero-initialize - the object. */ -#define AGGR_INIT_ZERO_FIRST(NODE) \ - TREE_LANG_FLAG_2 (AGGR_INIT_EXPR_CHECK (NODE)) - -/* AGGR_INIT_EXPR accessors. These are equivalent to the CALL_EXPR - accessors, except for AGGR_INIT_EXPR_SLOT (which takes the place of - CALL_EXPR_STATIC_CHAIN). */ - -#define AGGR_INIT_EXPR_FN(NODE) TREE_OPERAND (AGGR_INIT_EXPR_CHECK (NODE), 1) -#define AGGR_INIT_EXPR_SLOT(NODE) \ - TREE_OPERAND (AGGR_INIT_EXPR_CHECK (NODE), 2) -#define AGGR_INIT_EXPR_ARG(NODE, I) \ - TREE_OPERAND (AGGR_INIT_EXPR_CHECK (NODE), (I) + 3) -#define aggr_init_expr_nargs(NODE) (VL_EXP_OPERAND_LENGTH(NODE) - 3) - -/* AGGR_INIT_EXPR_ARGP returns a pointer to the argument vector for NODE. - We can't use &AGGR_INIT_EXPR_ARG (NODE, 0) because that will complain if - the argument count is zero when checking is enabled. Instead, do - the pointer arithmetic to advance past the 3 fixed operands in a - AGGR_INIT_EXPR. That produces a valid pointer to just past the end of - the operand array, even if it's not valid to dereference it. */ -#define AGGR_INIT_EXPR_ARGP(NODE) \ - (&(TREE_OPERAND (AGGR_INIT_EXPR_CHECK (NODE), 0)) + 3) - -/* Abstract iterators for AGGR_INIT_EXPRs. */ - -/* Structure containing iterator state. */ -typedef struct aggr_init_expr_arg_iterator_d { - tree t; /* the aggr_init_expr */ - int n; /* argument count */ - int i; /* next argument index */ -} aggr_init_expr_arg_iterator; - -/* Initialize the abstract argument list iterator object ITER with the - arguments from AGGR_INIT_EXPR node EXP. */ -inline void -init_aggr_init_expr_arg_iterator (tree exp, - aggr_init_expr_arg_iterator *iter) -{ - iter->t = exp; - iter->n = aggr_init_expr_nargs (exp); - iter->i = 0; -} - -/* Return the next argument from abstract argument list iterator object ITER, - and advance its state. Return NULL_TREE if there are no more arguments. */ -inline tree -next_aggr_init_expr_arg (aggr_init_expr_arg_iterator *iter) -{ - tree result; - if (iter->i >= iter->n) - return NULL_TREE; - result = AGGR_INIT_EXPR_ARG (iter->t, iter->i); - iter->i++; - return result; -} - -/* Initialize the abstract argument list iterator object ITER, then advance - past and return the first argument. Useful in for expressions, e.g. - for (arg = first_aggr_init_expr_arg (exp, &iter); arg; - arg = next_aggr_init_expr_arg (&iter)) */ -inline tree -first_aggr_init_expr_arg (tree exp, aggr_init_expr_arg_iterator *iter) -{ - init_aggr_init_expr_arg_iterator (exp, iter); - return next_aggr_init_expr_arg (iter); -} - -/* Test whether there are more arguments in abstract argument list iterator - ITER, without changing its state. */ -inline bool -more_aggr_init_expr_args_p (const aggr_init_expr_arg_iterator *iter) -{ - return (iter->i < iter->n); -} - -/* Iterate through each argument ARG of AGGR_INIT_EXPR CALL, using variable - ITER (of type aggr_init_expr_arg_iterator) to hold the iteration state. */ -#define FOR_EACH_AGGR_INIT_EXPR_ARG(arg, iter, call) \ - for ((arg) = first_aggr_init_expr_arg ((call), &(iter)); (arg); \ - (arg) = next_aggr_init_expr_arg (&(iter))) - -/* VEC_INIT_EXPR accessors. */ -#define VEC_INIT_EXPR_SLOT(NODE) TREE_OPERAND (VEC_INIT_EXPR_CHECK (NODE), 0) -#define VEC_INIT_EXPR_INIT(NODE) TREE_OPERAND (VEC_INIT_EXPR_CHECK (NODE), 1) - -/* Indicates that a VEC_INIT_EXPR is a potential constant expression. - Only set when the current function is constexpr. */ -#define VEC_INIT_EXPR_IS_CONSTEXPR(NODE) \ - TREE_LANG_FLAG_0 (VEC_INIT_EXPR_CHECK (NODE)) - -/* Indicates that a VEC_INIT_EXPR is expressing value-initialization. */ -#define VEC_INIT_EXPR_VALUE_INIT(NODE) \ - TREE_LANG_FLAG_1 (VEC_INIT_EXPR_CHECK (NODE)) - -/* The condition under which this MUST_NOT_THROW_EXPR actually blocks - exceptions. NULL_TREE means 'true'. */ -#define MUST_NOT_THROW_COND(NODE) \ - TREE_OPERAND (MUST_NOT_THROW_EXPR_CHECK (NODE), 1) - -/* The TYPE_MAIN_DECL for a class template type is a TYPE_DECL, not a - TEMPLATE_DECL. This macro determines whether or not a given class - type is really a template type, as opposed to an instantiation or - specialization of one. */ -#define CLASSTYPE_IS_TEMPLATE(NODE) \ - (CLASSTYPE_TEMPLATE_INFO (NODE) \ - && !CLASSTYPE_USE_TEMPLATE (NODE) \ - && PRIMARY_TEMPLATE_P (CLASSTYPE_TI_TEMPLATE (NODE))) - -/* The name used by the user to name the typename type. Typically, - this is an IDENTIFIER_NODE, and the same as the DECL_NAME on the - corresponding TYPE_DECL. However, this may also be a - TEMPLATE_ID_EXPR if we had something like `typename X::Y'. */ -#define TYPENAME_TYPE_FULLNAME(NODE) \ - (TYPE_VALUES_RAW (TYPENAME_TYPE_CHECK (NODE))) - -/* True if a TYPENAME_TYPE was declared as an "enum". */ -#define TYPENAME_IS_ENUM_P(NODE) \ - (TREE_LANG_FLAG_0 (TYPENAME_TYPE_CHECK (NODE))) - -/* True if a TYPENAME_TYPE was declared as a "class", "struct", or - "union". */ -#define TYPENAME_IS_CLASS_P(NODE) \ - (TREE_LANG_FLAG_1 (TYPENAME_TYPE_CHECK (NODE))) - -/* True if a TYPENAME_TYPE is in the process of being resolved. */ -#define TYPENAME_IS_RESOLVING_P(NODE) \ - (TREE_LANG_FLAG_2 (TYPENAME_TYPE_CHECK (NODE))) - -/* [class.virtual] - - A class that declares or inherits a virtual function is called a - polymorphic class. */ -#define TYPE_POLYMORPHIC_P(NODE) (TREE_LANG_FLAG_2 (NODE)) - -/* Nonzero if this class has a virtual function table pointer. */ -#define TYPE_CONTAINS_VPTR_P(NODE) \ - (TYPE_POLYMORPHIC_P (NODE) || CLASSTYPE_VBASECLASSES (NODE)) - -/* This flag is true of a local VAR_DECL if it was declared in a for - statement, but we are no longer in the scope of the for. */ -#define DECL_DEAD_FOR_LOCAL(NODE) DECL_LANG_FLAG_7 (VAR_DECL_CHECK (NODE)) - -/* This flag is set on a VAR_DECL that is a DECL_DEAD_FOR_LOCAL - if we already emitted a warning about using it. */ -#define DECL_ERROR_REPORTED(NODE) DECL_LANG_FLAG_0 (VAR_DECL_CHECK (NODE)) - -/* Nonzero if NODE is a FUNCTION_DECL (for a function with global - scope) declared in a local scope. */ -#define DECL_LOCAL_FUNCTION_P(NODE) \ - DECL_LANG_FLAG_0 (FUNCTION_DECL_CHECK (NODE)) - -/* Nonzero if NODE is the target for genericization of 'break' stmts. */ -#define LABEL_DECL_BREAK(NODE) \ - DECL_LANG_FLAG_0 (LABEL_DECL_CHECK (NODE)) - -/* Nonzero if NODE is the target for genericization of 'continue' stmts. */ -#define LABEL_DECL_CONTINUE(NODE) \ - DECL_LANG_FLAG_1 (LABEL_DECL_CHECK (NODE)) - -/* True if NODE was declared with auto in its return type, but it has - started compilation and so the return type might have been changed by - return type deduction; its declared return type should be found in - DECL_STRUCT_FUNCTION(NODE)->language->x_auto_return_pattern. */ -#define FNDECL_USED_AUTO(NODE) \ - TREE_LANG_FLAG_2 (FUNCTION_DECL_CHECK (NODE)) - -/* Nonzero if NODE is a DECL which we know about but which has not - been explicitly declared, such as a built-in function or a friend - declared inside a class. In the latter case DECL_HIDDEN_FRIEND_P - will be set. */ -#define DECL_ANTICIPATED(NODE) \ - (DECL_LANG_SPECIFIC (TYPE_FUNCTION_OR_TEMPLATE_DECL_CHECK (NODE)) \ - ->u.base.anticipated_p) - -/* Nonzero if NODE is a FUNCTION_DECL which was declared as a friend - within a class but has not been declared in the surrounding scope. - The function is invisible except via argument dependent lookup. */ -#define DECL_HIDDEN_FRIEND_P(NODE) \ - (LANG_DECL_FN_CHECK (DECL_COMMON_CHECK (NODE))->hidden_friend_p) - -/* Nonzero if NODE is an artificial FUNCTION_DECL for - #pragma omp declare reduction. */ -#define DECL_OMP_DECLARE_REDUCTION_P(NODE) \ - (LANG_DECL_FN_CHECK (DECL_COMMON_CHECK (NODE))->omp_declare_reduction_p) - -/* Nonzero if DECL has been declared threadprivate by - #pragma omp threadprivate. */ -#define CP_DECL_THREADPRIVATE_P(DECL) \ - (DECL_LANG_SPECIFIC (VAR_DECL_CHECK (DECL))->u.base.threadprivate_or_deleted_p) - -/* Nonzero if DECL was declared with '= delete'. */ -#define DECL_DELETED_FN(DECL) \ - (LANG_DECL_FN_CHECK (DECL)->min.base.threadprivate_or_deleted_p) - -/* Nonzero if DECL was declared with '= default' (maybe implicitly). */ -#define DECL_DEFAULTED_FN(DECL) \ - (LANG_DECL_FN_CHECK (DECL)->defaulted_p) - -/* Nonzero if DECL is explicitly defaulted in the class body. */ -#define DECL_DEFAULTED_IN_CLASS_P(DECL) \ - (DECL_DEFAULTED_FN (DECL) && DECL_INITIALIZED_IN_CLASS_P (DECL)) -/* Nonzero if DECL was defaulted outside the class body. */ -#define DECL_DEFAULTED_OUTSIDE_CLASS_P(DECL) \ - (DECL_DEFAULTED_FN (DECL) \ - && !(DECL_ARTIFICIAL (DECL) || DECL_INITIALIZED_IN_CLASS_P (DECL))) - -/* Record whether a typedef for type `int' was actually `signed int'. */ -#define C_TYPEDEF_EXPLICITLY_SIGNED(EXP) DECL_LANG_FLAG_1 (EXP) - -/* Returns nonzero if DECL has external linkage, as specified by the - language standard. (This predicate may hold even when the - corresponding entity is not actually given external linkage in the - object file; see decl_linkage for details.) */ -#define DECL_EXTERNAL_LINKAGE_P(DECL) \ - (decl_linkage (DECL) == lk_external) - -/* Keep these codes in ascending code order. */ - -#define INTEGRAL_CODE_P(CODE) \ - ((CODE) == ENUMERAL_TYPE \ - || (CODE) == BOOLEAN_TYPE \ - || (CODE) == INTEGER_TYPE) - -/* [basic.fundamental] - - Types bool, char, wchar_t, and the signed and unsigned integer types - are collectively called integral types. - - Note that INTEGRAL_TYPE_P, as defined in tree.h, allows enumeration - types as well, which is incorrect in C++. Keep these checks in - ascending code order. */ -#define CP_INTEGRAL_TYPE_P(TYPE) \ - (TREE_CODE (TYPE) == BOOLEAN_TYPE \ - || TREE_CODE (TYPE) == INTEGER_TYPE) - -/* Returns true if TYPE is an integral or enumeration name. Keep - these checks in ascending code order. */ -#define INTEGRAL_OR_ENUMERATION_TYPE_P(TYPE) \ - (TREE_CODE (TYPE) == ENUMERAL_TYPE || CP_INTEGRAL_TYPE_P (TYPE)) - -/* Returns true if TYPE is an integral or unscoped enumeration type. */ -#define INTEGRAL_OR_UNSCOPED_ENUMERATION_TYPE_P(TYPE) \ - (UNSCOPED_ENUM_P (TYPE) || CP_INTEGRAL_TYPE_P (TYPE)) - -/* True if the class type TYPE is a literal type. */ -#define CLASSTYPE_LITERAL_P(TYPE) \ - (LANG_TYPE_CLASS_CHECK (TYPE)->is_literal) - -/* [basic.fundamental] - - Integral and floating types are collectively called arithmetic - types. - - As a GNU extension, we also accept complex types. - - Keep these checks in ascending code order. */ -#define ARITHMETIC_TYPE_P(TYPE) \ - (CP_INTEGRAL_TYPE_P (TYPE) \ - || TREE_CODE (TYPE) == REAL_TYPE \ - || TREE_CODE (TYPE) == COMPLEX_TYPE) - -/* True iff TYPE is cv decltype(nullptr). */ -#define NULLPTR_TYPE_P(TYPE) (TREE_CODE (TYPE) == NULLPTR_TYPE) - -/* [basic.types] - - Arithmetic types, enumeration types, pointer types, - pointer-to-member types, and std::nullptr_t are collectively called - scalar types. - - Keep these checks in ascending code order. */ -#define SCALAR_TYPE_P(TYPE) \ - (TYPE_PTRDATAMEM_P (TYPE) \ - || TREE_CODE (TYPE) == ENUMERAL_TYPE \ - || ARITHMETIC_TYPE_P (TYPE) \ - || TYPE_PTR_P (TYPE) \ - || TYPE_PTRMEMFUNC_P (TYPE) \ - || NULLPTR_TYPE_P (TYPE)) - -/* Determines whether this type is a C++0x scoped enumeration - type. Scoped enumerations types are introduced via "enum class" or - "enum struct", e.g., - - enum class Color { - Red, Green, Blue - }; - - Scoped enumeration types are different from normal (unscoped) - enumeration types in several ways: - - - The enumerators of a scoped enumeration type are only available - within the scope of the enumeration type and not in the - enclosing scope. For example, the Red color can be referred to - with "Color::Red" but not "Red". - - - Scoped enumerators and enumerations do not implicitly convert - to integers or 'bool'. - - - The underlying type of the enum is well-defined. */ -#define SCOPED_ENUM_P(TYPE) \ - (TREE_CODE (TYPE) == ENUMERAL_TYPE && ENUM_IS_SCOPED (TYPE)) - -/* Determine whether this is an unscoped enumeration type. */ -#define UNSCOPED_ENUM_P(TYPE) \ - (TREE_CODE (TYPE) == ENUMERAL_TYPE && !ENUM_IS_SCOPED (TYPE)) - -/* Set the flag indicating whether an ENUMERAL_TYPE is a C++0x scoped - enumeration type (1) or a normal (unscoped) enumeration type - (0). */ -#define SET_SCOPED_ENUM_P(TYPE, VAL) \ - (ENUM_IS_SCOPED (TYPE) = (VAL)) - -#define SET_OPAQUE_ENUM_P(TYPE, VAL) \ - (ENUM_IS_OPAQUE (TYPE) = (VAL)) - -#define OPAQUE_ENUM_P(TYPE) \ - (TREE_CODE (TYPE) == ENUMERAL_TYPE && ENUM_IS_OPAQUE (TYPE)) - -/* Determines whether an ENUMERAL_TYPE has an explicit - underlying type. */ -#define ENUM_FIXED_UNDERLYING_TYPE_P(NODE) (TYPE_LANG_FLAG_5 (NODE)) - -/* Returns the underlying type of the given enumeration type. The - underlying type is determined in different ways, depending on the - properties of the enum: - - - In C++0x, the underlying type can be explicitly specified, e.g., - - enum E1 : char { ... } // underlying type is char - - - In a C++0x scoped enumeration, the underlying type is int - unless otherwises specified: - - enum class E2 { ... } // underlying type is int - - - Otherwise, the underlying type is determined based on the - values of the enumerators. In this case, the - ENUM_UNDERLYING_TYPE will not be set until after the definition - of the enumeration is completed by finish_enum. */ -#define ENUM_UNDERLYING_TYPE(TYPE) \ - TREE_TYPE (ENUMERAL_TYPE_CHECK (TYPE)) - -/* [dcl.init.aggr] - - An aggregate is an array or a class with no user-provided - constructors, no brace-or-equal-initializers for non-static data - members, no private or protected non-static data members, no - base classes, and no virtual functions. - - As an extension, we also treat vectors as aggregates. Keep these - checks in ascending code order. */ -#define CP_AGGREGATE_TYPE_P(TYPE) \ - (TREE_CODE (TYPE) == VECTOR_TYPE \ - ||TREE_CODE (TYPE) == ARRAY_TYPE \ - || (CLASS_TYPE_P (TYPE) && !CLASSTYPE_NON_AGGREGATE (TYPE))) - -/* Nonzero for a class type means that the class type has a - user-declared constructor. */ -#define TYPE_HAS_USER_CONSTRUCTOR(NODE) (TYPE_LANG_FLAG_1 (NODE)) - -/* Nonzero means that the FUNCTION_TYPE or METHOD_TYPE has a - late-specified return type. */ -#define TYPE_HAS_LATE_RETURN_TYPE(NODE) \ - (TYPE_LANG_FLAG_2 (FUNC_OR_METHOD_CHECK (NODE))) - -/* When appearing in an INDIRECT_REF, it means that the tree structure - underneath is actually a call to a constructor. This is needed - when the constructor must initialize local storage (which can - be automatically destroyed), rather than allowing it to allocate - space from the heap. - - When appearing in a SAVE_EXPR, it means that underneath - is a call to a constructor. - - When appearing in a CONSTRUCTOR, the expression is a - compound literal. - - When appearing in a FIELD_DECL, it means that this field - has been duly initialized in its constructor. */ -#define TREE_HAS_CONSTRUCTOR(NODE) (TREE_LANG_FLAG_4 (NODE)) - -/* True if NODE is a brace-enclosed initializer. */ -#define BRACE_ENCLOSED_INITIALIZER_P(NODE) \ - (TREE_CODE (NODE) == CONSTRUCTOR && TREE_TYPE (NODE) == init_list_type_node) - -/* True if NODE is a compound-literal, i.e., a brace-enclosed - initializer cast to a particular type. */ -#define COMPOUND_LITERAL_P(NODE) \ - (TREE_CODE (NODE) == CONSTRUCTOR && TREE_HAS_CONSTRUCTOR (NODE)) - -#define EMPTY_CONSTRUCTOR_P(NODE) (TREE_CODE (NODE) == CONSTRUCTOR \ - && vec_safe_is_empty(CONSTRUCTOR_ELTS(NODE))\ - && !TREE_HAS_CONSTRUCTOR (NODE)) - -/* True if NODE is a init-list used as a direct-initializer, i.e. - B b{1,2}, not B b({1,2}) or B b = {1,2}. */ -#define CONSTRUCTOR_IS_DIRECT_INIT(NODE) (TREE_LANG_FLAG_0 (CONSTRUCTOR_CHECK (NODE))) - -/* True if an uninitialized element in NODE should not be treated as - implicitly value-initialized. Only used in constexpr evaluation. */ -#define CONSTRUCTOR_NO_IMPLICIT_ZERO(NODE) \ - (TREE_LANG_FLAG_1 (CONSTRUCTOR_CHECK (NODE))) - -/* True if this CONSTRUCTOR should not be used as a variable initializer - because it was loaded from a constexpr variable with mutable fields. */ -#define CONSTRUCTOR_MUTABLE_POISON(NODE) \ - (TREE_LANG_FLAG_2 (CONSTRUCTOR_CHECK (NODE))) - -#define DIRECT_LIST_INIT_P(NODE) \ - (BRACE_ENCLOSED_INITIALIZER_P (NODE) && CONSTRUCTOR_IS_DIRECT_INIT (NODE)) - -/* True if NODE represents a conversion for direct-initialization in a - template. Set by perform_implicit_conversion_flags. */ -#define IMPLICIT_CONV_EXPR_DIRECT_INIT(NODE) \ - (TREE_LANG_FLAG_0 (IMPLICIT_CONV_EXPR_CHECK (NODE))) - -/* Nonzero means that an object of this type can not be initialized using - an initializer list. */ -#define CLASSTYPE_NON_AGGREGATE(NODE) \ - (LANG_TYPE_CLASS_CHECK (NODE)->non_aggregate) -#define TYPE_NON_AGGREGATE_CLASS(NODE) \ - (CLASS_TYPE_P (NODE) && CLASSTYPE_NON_AGGREGATE (NODE)) - -/* Nonzero if there is a non-trivial X::op=(cv X&) for this class. */ -#define TYPE_HAS_COMPLEX_COPY_ASSIGN(NODE) (LANG_TYPE_CLASS_CHECK (NODE)->has_complex_copy_assign) - -/* Nonzero if there is a non-trivial X::X(cv X&) for this class. */ -#define TYPE_HAS_COMPLEX_COPY_CTOR(NODE) (LANG_TYPE_CLASS_CHECK (NODE)->has_complex_copy_ctor) - -/* Nonzero if there is a non-trivial X::op=(X&&) for this class. */ -#define TYPE_HAS_COMPLEX_MOVE_ASSIGN(NODE) (LANG_TYPE_CLASS_CHECK (NODE)->has_complex_move_assign) - -/* Nonzero if there is a non-trivial X::X(X&&) for this class. */ -#define TYPE_HAS_COMPLEX_MOVE_CTOR(NODE) (LANG_TYPE_CLASS_CHECK (NODE)->has_complex_move_ctor) - -/* Nonzero if there is no trivial default constructor for this class. */ -#define TYPE_HAS_COMPLEX_DFLT(NODE) (LANG_TYPE_CLASS_CHECK (NODE)->has_complex_dflt) - -/* Nonzero if TYPE has a trivial destructor. From [class.dtor]: - - A destructor is trivial if it is an implicitly declared - destructor and if: - - - all of the direct base classes of its class have trivial - destructors, - - - for all of the non-static data members of its class that are - of class type (or array thereof), each such class has a - trivial destructor. */ -#define TYPE_HAS_TRIVIAL_DESTRUCTOR(NODE) \ - (!TYPE_HAS_NONTRIVIAL_DESTRUCTOR (NODE)) - -/* Nonzero for _TYPE node means that this type does not have a trivial - destructor. Therefore, destroying an object of this type will - involve a call to a destructor. This can apply to objects of - ARRAY_TYPE is the type of the elements needs a destructor. */ -#define TYPE_HAS_NONTRIVIAL_DESTRUCTOR(NODE) \ - (TYPE_LANG_FLAG_4 (NODE)) - -/* Nonzero for class type means that the default constructor is trivial. */ -#define TYPE_HAS_TRIVIAL_DFLT(NODE) \ - (TYPE_HAS_DEFAULT_CONSTRUCTOR (NODE) && ! TYPE_HAS_COMPLEX_DFLT (NODE)) - -/* Nonzero for class type means that copy initialization of this type can use - a bitwise copy. */ -#define TYPE_HAS_TRIVIAL_COPY_CTOR(NODE) \ - (TYPE_HAS_COPY_CTOR (NODE) && ! TYPE_HAS_COMPLEX_COPY_CTOR (NODE)) - -/* Nonzero for class type means that assignment of this type can use - a bitwise copy. */ -#define TYPE_HAS_TRIVIAL_COPY_ASSIGN(NODE) \ - (TYPE_HAS_COPY_ASSIGN (NODE) && ! TYPE_HAS_COMPLEX_COPY_ASSIGN (NODE)) - -/* Returns true if NODE is a pointer-to-data-member. */ -#define TYPE_PTRDATAMEM_P(NODE) \ - (TREE_CODE (NODE) == OFFSET_TYPE) -/* Returns true if NODE is a pointer. */ -#define TYPE_PTR_P(NODE) \ - (TREE_CODE (NODE) == POINTER_TYPE) - -/* Returns true if NODE is an object type: - - [basic.types] - - An object type is a (possibly cv-qualified) type that is not a - function type, not a reference type, and not a void type. - - Keep these checks in ascending order, for speed. */ -#define TYPE_OBJ_P(NODE) \ - (TREE_CODE (NODE) != REFERENCE_TYPE \ - && !VOID_TYPE_P (NODE) \ - && TREE_CODE (NODE) != FUNCTION_TYPE \ - && TREE_CODE (NODE) != METHOD_TYPE) - -/* Returns true if NODE is a pointer to an object. Keep these checks - in ascending tree code order. */ -#define TYPE_PTROB_P(NODE) \ - (TYPE_PTR_P (NODE) && TYPE_OBJ_P (TREE_TYPE (NODE))) - -/* Returns true if NODE is a reference to an object. Keep these checks - in ascending tree code order. */ -#define TYPE_REF_OBJ_P(NODE) \ - (TREE_CODE (NODE) == REFERENCE_TYPE && TYPE_OBJ_P (TREE_TYPE (NODE))) - -/* Returns true if NODE is a pointer to an object, or a pointer to - void. Keep these checks in ascending tree code order. */ -#define TYPE_PTROBV_P(NODE) \ - (TYPE_PTR_P (NODE) \ - && !(TREE_CODE (TREE_TYPE (NODE)) == FUNCTION_TYPE \ - || TREE_CODE (TREE_TYPE (NODE)) == METHOD_TYPE)) - -/* Returns true if NODE is a pointer to function type. */ -#define TYPE_PTRFN_P(NODE) \ - (TYPE_PTR_P (NODE) \ - && TREE_CODE (TREE_TYPE (NODE)) == FUNCTION_TYPE) - -/* Returns true if NODE is a reference to function type. */ -#define TYPE_REFFN_P(NODE) \ - (TREE_CODE (NODE) == REFERENCE_TYPE \ - && TREE_CODE (TREE_TYPE (NODE)) == FUNCTION_TYPE) - -/* Returns true if NODE is a pointer to member function type. */ -#define TYPE_PTRMEMFUNC_P(NODE) \ - (TREE_CODE (NODE) == RECORD_TYPE \ - && TYPE_PTRMEMFUNC_FLAG (NODE)) - -#define TYPE_PTRMEMFUNC_FLAG(NODE) \ - (TYPE_LANG_FLAG_2 (RECORD_TYPE_CHECK (NODE))) - -/* Returns true if NODE is a pointer-to-member. */ -#define TYPE_PTRMEM_P(NODE) \ - (TYPE_PTRDATAMEM_P (NODE) || TYPE_PTRMEMFUNC_P (NODE)) - -/* Returns true if NODE is a pointer or a pointer-to-member. */ -#define TYPE_PTR_OR_PTRMEM_P(NODE) \ - (TYPE_PTR_P (NODE) || TYPE_PTRMEM_P (NODE)) - -/* Indicates when overload resolution may resolve to a pointer to - member function. [expr.unary.op]/3 */ -#define PTRMEM_OK_P(NODE) \ - TREE_LANG_FLAG_0 (TREE_CHECK3 ((NODE), ADDR_EXPR, OFFSET_REF, SCOPE_REF)) - -/* Get the POINTER_TYPE to the METHOD_TYPE associated with this - pointer to member function. TYPE_PTRMEMFUNC_P _must_ be true, - before using this macro. */ -#define TYPE_PTRMEMFUNC_FN_TYPE(NODE) \ - (cp_build_qualified_type (TREE_TYPE (TYPE_FIELDS (NODE)),\ - cp_type_quals (NODE))) - -/* As above, but can be used in places that want an lvalue at the expense - of not necessarily having the correct cv-qualifiers. */ -#define TYPE_PTRMEMFUNC_FN_TYPE_RAW(NODE) \ - (TREE_TYPE (TYPE_FIELDS (NODE))) - -/* Returns `A' for a type like `int (A::*)(double)' */ -#define TYPE_PTRMEMFUNC_OBJECT_TYPE(NODE) \ - TYPE_METHOD_BASETYPE (TREE_TYPE (TYPE_PTRMEMFUNC_FN_TYPE (NODE))) - -/* These are use to manipulate the canonical RECORD_TYPE from the - hashed POINTER_TYPE, and can only be used on the POINTER_TYPE. */ -#define TYPE_GET_PTRMEMFUNC_TYPE(NODE) \ - (TYPE_LANG_SPECIFIC (NODE) ? LANG_TYPE_PTRMEM_CHECK (NODE)->record : NULL) -#define TYPE_SET_PTRMEMFUNC_TYPE(NODE, VALUE) \ - do { \ - if (TYPE_LANG_SPECIFIC (NODE) == NULL) \ - { \ - TYPE_LANG_SPECIFIC (NODE) \ - = (struct lang_type *) ggc_internal_cleared_alloc \ - (sizeof (struct lang_type_ptrmem)); \ - TYPE_LANG_SPECIFIC (NODE)->u.ptrmem.h.is_lang_type_class = 0; \ - } \ - TYPE_LANG_SPECIFIC (NODE)->u.ptrmem.record = (VALUE); \ - } while (0) - -/* For a pointer-to-member type of the form `T X::*', this is `X'. - For a type like `void (X::*)() const', this type is `X', not `const - X'. To get at the `const X' you have to look at the - TYPE_PTRMEM_POINTED_TO_TYPE; there, the first parameter will have - type `const X*'. */ -#define TYPE_PTRMEM_CLASS_TYPE(NODE) \ - (TYPE_PTRDATAMEM_P (NODE) \ - ? TYPE_OFFSET_BASETYPE (NODE) \ - : TYPE_PTRMEMFUNC_OBJECT_TYPE (NODE)) - -/* For a pointer-to-member type of the form `T X::*', this is `T'. */ -#define TYPE_PTRMEM_POINTED_TO_TYPE(NODE) \ - (TYPE_PTRDATAMEM_P (NODE) \ - ? TREE_TYPE (NODE) \ - : TREE_TYPE (TYPE_PTRMEMFUNC_FN_TYPE (NODE))) - -/* For a pointer-to-member constant `X::Y' this is the RECORD_TYPE for - `X'. */ -#define PTRMEM_CST_CLASS(NODE) \ - TYPE_PTRMEM_CLASS_TYPE (TREE_TYPE (PTRMEM_CST_CHECK (NODE))) - -/* For a pointer-to-member constant `X::Y' this is the _DECL for - `Y'. */ -#define PTRMEM_CST_MEMBER(NODE) (((ptrmem_cst_t)PTRMEM_CST_CHECK (NODE))->member) - -/* The expression in question for a TYPEOF_TYPE. */ -#define TYPEOF_TYPE_EXPR(NODE) (TYPE_VALUES_RAW (TYPEOF_TYPE_CHECK (NODE))) - -/* The type in question for an UNDERLYING_TYPE. */ -#define UNDERLYING_TYPE_TYPE(NODE) \ - (TYPE_VALUES_RAW (UNDERLYING_TYPE_CHECK (NODE))) - -/* The type in question for BASES. */ -#define BASES_TYPE(NODE) \ - (TYPE_VALUES_RAW (BASES_CHECK (NODE))) - -#define BASES_DIRECT(NODE) \ - TREE_LANG_FLAG_0 (BASES_CHECK (NODE)) - -/* The expression in question for a DECLTYPE_TYPE. */ -#define DECLTYPE_TYPE_EXPR(NODE) (TYPE_VALUES_RAW (DECLTYPE_TYPE_CHECK (NODE))) - -/* Whether the DECLTYPE_TYPE_EXPR of NODE was originally parsed as an - id-expression or a member-access expression. When false, it was - parsed as a full expression. */ -#define DECLTYPE_TYPE_ID_EXPR_OR_MEMBER_ACCESS_P(NODE) \ - (DECLTYPE_TYPE_CHECK (NODE))->type_common.string_flag - -/* These flags indicate that we want different semantics from normal - decltype: lambda capture just drops references, init capture - uses auto semantics, lambda proxies look through implicit dereference. */ -#define DECLTYPE_FOR_LAMBDA_CAPTURE(NODE) \ - TREE_LANG_FLAG_0 (DECLTYPE_TYPE_CHECK (NODE)) -#define DECLTYPE_FOR_INIT_CAPTURE(NODE) \ - TREE_LANG_FLAG_1 (DECLTYPE_TYPE_CHECK (NODE)) -#define DECLTYPE_FOR_LAMBDA_PROXY(NODE) \ - TREE_LANG_FLAG_2 (DECLTYPE_TYPE_CHECK (NODE)) - -/* Nonzero for VAR_DECL and FUNCTION_DECL node means that `extern' was - specified in its declaration. This can also be set for an - erroneously declared PARM_DECL. */ -#define DECL_THIS_EXTERN(NODE) \ - DECL_LANG_FLAG_2 (VAR_FUNCTION_OR_PARM_DECL_CHECK (NODE)) - -/* Nonzero for VAR_DECL and FUNCTION_DECL node means that `static' was - specified in its declaration. This can also be set for an - erroneously declared PARM_DECL. */ -#define DECL_THIS_STATIC(NODE) \ - DECL_LANG_FLAG_6 (VAR_FUNCTION_OR_PARM_DECL_CHECK (NODE)) - -/* Nonzero for FIELD_DECL node means that this field is a lambda capture - field for an array of runtime bound. */ -#define DECL_VLA_CAPTURE_P(NODE) \ - DECL_LANG_FLAG_1 (FIELD_DECL_CHECK (NODE)) - -/* Nonzero for PARM_DECL node means that this is an array function - parameter, i.e, a[] rather than *a. */ -#define DECL_ARRAY_PARAMETER_P(NODE) \ - DECL_LANG_FLAG_1 (PARM_DECL_CHECK (NODE)) - -/* Nonzero for FIELD_DECL node means that this field is a base class - of the parent object, as opposed to a member field. */ -#define DECL_FIELD_IS_BASE(NODE) \ - DECL_LANG_FLAG_6 (FIELD_DECL_CHECK (NODE)) - -/* Nonzero for FIELD_DECL node means that this field is a simple (no - explicit initializer) lambda capture field, making it invisible to - name lookup in unevaluated contexts. */ -#define DECL_NORMAL_CAPTURE_P(NODE) \ - DECL_LANG_FLAG_7 (FIELD_DECL_CHECK (NODE)) - -/* Nonzero if TYPE is an anonymous union or struct type. We have to use a - flag for this because "A union for which objects or pointers are - declared is not an anonymous union" [class.union]. */ -#define ANON_AGGR_TYPE_P(NODE) \ - (CLASS_TYPE_P (NODE) && LANG_TYPE_CLASS_CHECK (NODE)->anon_aggr) -#define SET_ANON_AGGR_TYPE_P(NODE) \ - (LANG_TYPE_CLASS_CHECK (NODE)->anon_aggr = 1) - -/* Nonzero if TYPE is an anonymous union type. */ -#define ANON_UNION_TYPE_P(NODE) \ - (TREE_CODE (NODE) == UNION_TYPE && ANON_AGGR_TYPE_P (NODE)) - -/* Define fields and accessors for nodes representing declared names. */ - -#define TYPE_WAS_ANONYMOUS(NODE) (LANG_TYPE_CLASS_CHECK (NODE)->was_anonymous) - -/* C++: all of these are overloaded! These apply only to TYPE_DECLs. */ - -/* The format of each node in the DECL_FRIENDLIST is as follows: - - The TREE_PURPOSE will be the name of a function, i.e., an - IDENTIFIER_NODE. The TREE_VALUE will be itself a TREE_LIST, whose - TREE_VALUEs are friends with the given name. */ -#define DECL_FRIENDLIST(NODE) (DECL_INITIAL (NODE)) -#define FRIEND_NAME(LIST) (TREE_PURPOSE (LIST)) -#define FRIEND_DECLS(LIST) (TREE_VALUE (LIST)) - -/* The DECL_ACCESS, if non-NULL, is a TREE_LIST. The TREE_PURPOSE of - each node is a type; the TREE_VALUE is the access granted for this - DECL in that type. The DECL_ACCESS is set by access declarations. - For example, if a member that would normally be public in a - derived class is made protected, then the derived class and the - protected_access_node will appear in the DECL_ACCESS for the node. */ -#define DECL_ACCESS(NODE) (LANG_DECL_U2_CHECK (NODE, 0)->access) - -/* Nonzero if the FUNCTION_DECL is a global constructor. */ -#define DECL_GLOBAL_CTOR_P(NODE) \ - (LANG_DECL_FN_CHECK (NODE)->global_ctor_p) - -/* Nonzero if the FUNCTION_DECL is a global destructor. */ -#define DECL_GLOBAL_DTOR_P(NODE) \ - (LANG_DECL_FN_CHECK (NODE)->global_dtor_p) - -/* Accessor macros for C++ template decl nodes. */ - -/* The DECL_TEMPLATE_PARMS are a list. The TREE_PURPOSE of each node - is a INT_CST whose TREE_INT_CST_LOW indicates the level of the - template parameters, with 1 being the outermost set of template - parameters. The TREE_VALUE is a vector, whose elements are the - template parameters at each level. Each element in the vector is a - TREE_LIST, whose TREE_VALUE is a PARM_DECL (if the parameter is a - non-type parameter), or a TYPE_DECL (if the parameter is a type - parameter). The TREE_PURPOSE is the default value, if any. The - TEMPLATE_PARM_INDEX for the parameter is available as the - DECL_INITIAL (for a PARM_DECL) or as the TREE_TYPE (for a - TYPE_DECL). - - FIXME: CONST_CAST_TREE is a hack that hopefully will go away after - tree is converted to C++ class hiearchy. */ -#define DECL_TEMPLATE_PARMS(NODE) \ - ((struct tree_template_decl *)CONST_CAST_TREE (TEMPLATE_DECL_CHECK (NODE)))->arguments -#define DECL_INNERMOST_TEMPLATE_PARMS(NODE) \ - INNERMOST_TEMPLATE_PARMS (DECL_TEMPLATE_PARMS (NODE)) -#define DECL_NTPARMS(NODE) \ - TREE_VEC_LENGTH (DECL_INNERMOST_TEMPLATE_PARMS (NODE)) -/* For function, method, class-data templates. - - FIXME: CONST_CAST_TREE is a hack that hopefully will go away after - tree is converted to C++ class hiearchy. */ -#define DECL_TEMPLATE_RESULT(NODE) \ - ((struct tree_template_decl *)CONST_CAST_TREE(TEMPLATE_DECL_CHECK (NODE)))->result -/* For a function template at namespace scope, DECL_TEMPLATE_INSTANTIATIONS - lists all instantiations and specializations of the function so that - tsubst_friend_function can reassign them to another template if we find - that the namespace-scope template is really a partial instantiation of a - friend template. - - For a class template the DECL_TEMPLATE_INSTANTIATIONS lists holds - all instantiations and specializations of the class type, including - partial instantiations and partial specializations, so that if we - explicitly specialize a partial instantiation we can walk the list - in maybe_process_partial_specialization and reassign them or complain - as appropriate. - - In both cases, the TREE_PURPOSE of each node contains the arguments - used; the TREE_VALUE contains the generated variable. The template - arguments are always complete. For example, given: - - template struct S1 { - template struct S2 {}; - template struct S2 {}; - }; - - the record for the partial specialization will contain, as its - argument list, { {T}, {U*} }, and will be on the - DECL_TEMPLATE_INSTANTIATIONS list for `template template - struct S1::S2'. - - This list is not used for other templates. */ -#define DECL_TEMPLATE_INSTANTIATIONS(NODE) \ - DECL_SIZE_UNIT (TEMPLATE_DECL_CHECK (NODE)) - -/* For a class template, this list contains the partial - specializations of this template. (Full specializations are not - recorded on this list.) The TREE_PURPOSE holds the arguments used - in the partial specialization (e.g., for `template struct - S' this will be `T*, int'.) The arguments will also include - any outer template arguments. The TREE_VALUE holds the TEMPLATE_DECL - for the partial specialization. The TREE_TYPE is the _TYPE node for - the partial specialization. - - This list is not used for other templates. */ -#define DECL_TEMPLATE_SPECIALIZATIONS(NODE) \ - DECL_SIZE (TEMPLATE_DECL_CHECK (NODE)) - -/* Nonzero for a DECL which is actually a template parameter. Keep - these checks in ascending tree code order. */ -#define DECL_TEMPLATE_PARM_P(NODE) \ - (DECL_LANG_FLAG_0 (NODE) \ - && (TREE_CODE (NODE) == CONST_DECL \ - || TREE_CODE (NODE) == PARM_DECL \ - || TREE_CODE (NODE) == TYPE_DECL \ - || TREE_CODE (NODE) == TEMPLATE_DECL)) - -/* Mark NODE as a template parameter. */ -#define SET_DECL_TEMPLATE_PARM_P(NODE) \ - (DECL_LANG_FLAG_0 (NODE) = 1) - -/* Nonzero if NODE is a template template parameter. */ -#define DECL_TEMPLATE_TEMPLATE_PARM_P(NODE) \ - (TREE_CODE (NODE) == TEMPLATE_DECL && DECL_TEMPLATE_PARM_P (NODE)) - -/* Nonzero for a DECL that represents a function template. */ -#define DECL_FUNCTION_TEMPLATE_P(NODE) \ - (TREE_CODE (NODE) == TEMPLATE_DECL \ - && DECL_TEMPLATE_RESULT (NODE) != NULL_TREE \ - && TREE_CODE (DECL_TEMPLATE_RESULT (NODE)) == FUNCTION_DECL) - -/* Nonzero for a DECL that represents a class template or alias - template. */ -#define DECL_TYPE_TEMPLATE_P(NODE) \ - (TREE_CODE (NODE) == TEMPLATE_DECL \ - && DECL_TEMPLATE_RESULT (NODE) != NULL_TREE \ - && TREE_CODE (DECL_TEMPLATE_RESULT (NODE)) == TYPE_DECL) - -/* Nonzero for a DECL that represents a class template. */ -#define DECL_CLASS_TEMPLATE_P(NODE) \ - (DECL_TYPE_TEMPLATE_P (NODE) \ - && DECL_IMPLICIT_TYPEDEF_P (DECL_TEMPLATE_RESULT (NODE))) - -/* Nonzero for a TEMPLATE_DECL that represents an alias template. */ -#define DECL_ALIAS_TEMPLATE_P(NODE) \ - (DECL_TYPE_TEMPLATE_P (NODE) \ - && !DECL_ARTIFICIAL (DECL_TEMPLATE_RESULT (NODE))) - -/* Nonzero for a NODE which declares a type. */ -#define DECL_DECLARES_TYPE_P(NODE) \ - (TREE_CODE (NODE) == TYPE_DECL || DECL_TYPE_TEMPLATE_P (NODE)) - -/* Nonzero if NODE declares a function. */ -#define DECL_DECLARES_FUNCTION_P(NODE) \ - (TREE_CODE (NODE) == FUNCTION_DECL || DECL_FUNCTION_TEMPLATE_P (NODE)) - -/* Nonzero if NODE is the typedef implicitly generated for a type when - the type is declared. In C++, `struct S {};' is roughly - equivalent to `struct S {}; typedef struct S S;' in C. - DECL_IMPLICIT_TYPEDEF_P will hold for the typedef indicated in this - example. In C++, there is a second implicit typedef for each - class, in the scope of `S' itself, so that you can say `S::S'. - DECL_SELF_REFERENCE_P will hold for that second typedef. */ -#define DECL_IMPLICIT_TYPEDEF_P(NODE) \ - (TREE_CODE (NODE) == TYPE_DECL && DECL_LANG_FLAG_2 (NODE)) -#define SET_DECL_IMPLICIT_TYPEDEF_P(NODE) \ - (DECL_LANG_FLAG_2 (NODE) = 1) -#define DECL_SELF_REFERENCE_P(NODE) \ - (TREE_CODE (NODE) == TYPE_DECL && DECL_LANG_FLAG_4 (NODE)) -#define SET_DECL_SELF_REFERENCE_P(NODE) \ - (DECL_LANG_FLAG_4 (NODE) = 1) - -/* A `primary' template is one that has its own template header and is not - a partial specialization. A member function of a class template is a - template, but not primary. A member template is primary. Friend - templates are primary, too. */ - -/* Returns the primary template corresponding to these parameters. */ -#define DECL_PRIMARY_TEMPLATE(NODE) \ - (TREE_TYPE (DECL_INNERMOST_TEMPLATE_PARMS (NODE))) - -/* Returns nonzero if NODE is a primary template. */ -#define PRIMARY_TEMPLATE_P(NODE) (DECL_PRIMARY_TEMPLATE (NODE) == (NODE)) - -/* Nonzero iff NODE is a specialization of a template. The value - indicates the type of specializations: - - 1=implicit instantiation - - 2=partial or explicit specialization, e.g.: - - template <> int min (int, int), - - 3=explicit instantiation, e.g.: - - template int min (int, int); - - Note that NODE will be marked as a specialization even if the - template it is instantiating is not a primary template. For - example, given: - - template struct O { - void f(); - struct I {}; - }; - - both O::f and O::I will be marked as instantiations. - - If DECL_USE_TEMPLATE is nonzero, then DECL_TEMPLATE_INFO will also - be non-NULL. */ -#define DECL_USE_TEMPLATE(NODE) (DECL_LANG_SPECIFIC (NODE)->u.base.use_template) - -/* Like DECL_USE_TEMPLATE, but for class types. */ -#define CLASSTYPE_USE_TEMPLATE(NODE) \ - (LANG_TYPE_CLASS_CHECK (NODE)->use_template) - -/* True if NODE is a specialization of a primary template. */ -#define CLASSTYPE_SPECIALIZATION_OF_PRIMARY_TEMPLATE_P(NODE) \ - (CLASS_TYPE_P (NODE) \ - && CLASSTYPE_USE_TEMPLATE (NODE) \ - && PRIMARY_TEMPLATE_P (CLASSTYPE_TI_TEMPLATE (NODE))) - -#define DECL_TEMPLATE_INSTANTIATION(NODE) (DECL_USE_TEMPLATE (NODE) & 1) -#define CLASSTYPE_TEMPLATE_INSTANTIATION(NODE) \ - (CLASSTYPE_USE_TEMPLATE (NODE) & 1) - -#define DECL_TEMPLATE_SPECIALIZATION(NODE) (DECL_USE_TEMPLATE (NODE) == 2) -#define SET_DECL_TEMPLATE_SPECIALIZATION(NODE) (DECL_USE_TEMPLATE (NODE) = 2) - -/* Returns true for an explicit or partial specialization of a class - template. */ -#define CLASSTYPE_TEMPLATE_SPECIALIZATION(NODE) \ - (CLASSTYPE_USE_TEMPLATE (NODE) == 2) -#define SET_CLASSTYPE_TEMPLATE_SPECIALIZATION(NODE) \ - (CLASSTYPE_USE_TEMPLATE (NODE) = 2) - -#define DECL_IMPLICIT_INSTANTIATION(NODE) (DECL_USE_TEMPLATE (NODE) == 1) -#define SET_DECL_IMPLICIT_INSTANTIATION(NODE) (DECL_USE_TEMPLATE (NODE) = 1) -#define CLASSTYPE_IMPLICIT_INSTANTIATION(NODE) \ - (CLASSTYPE_USE_TEMPLATE (NODE) == 1) -#define SET_CLASSTYPE_IMPLICIT_INSTANTIATION(NODE) \ - (CLASSTYPE_USE_TEMPLATE (NODE) = 1) - -#define DECL_EXPLICIT_INSTANTIATION(NODE) (DECL_USE_TEMPLATE (NODE) == 3) -#define SET_DECL_EXPLICIT_INSTANTIATION(NODE) (DECL_USE_TEMPLATE (NODE) = 3) -#define CLASSTYPE_EXPLICIT_INSTANTIATION(NODE) \ - (CLASSTYPE_USE_TEMPLATE (NODE) == 3) -#define SET_CLASSTYPE_EXPLICIT_INSTANTIATION(NODE) \ - (CLASSTYPE_USE_TEMPLATE (NODE) = 3) - -/* Nonzero if DECL is a friend function which is an instantiation - from the point of view of the compiler, but not from the point of - view of the language. For example given: - template struct S { friend void f(T) {}; }; - the declaration of `void f(int)' generated when S is - instantiated will not be a DECL_TEMPLATE_INSTANTIATION, but will be - a DECL_FRIEND_PSEUDO_TEMPLATE_INSTANTIATION. */ -#define DECL_FRIEND_PSEUDO_TEMPLATE_INSTANTIATION(DECL) \ - (DECL_TEMPLATE_INFO (DECL) && !DECL_USE_TEMPLATE (DECL)) - -/* Nonzero if DECL is a function generated from a function 'temploid', - i.e. template, member of class template, or dependent friend. */ -#define DECL_TEMPLOID_INSTANTIATION(DECL) \ - (DECL_TEMPLATE_INSTANTIATION (DECL) \ - || DECL_FRIEND_PSEUDO_TEMPLATE_INSTANTIATION (DECL)) - -/* Nonzero if DECL is either defined implicitly by the compiler or - generated from a temploid. */ -#define DECL_GENERATED_P(DECL) \ - (DECL_TEMPLOID_INSTANTIATION (DECL) || DECL_DEFAULTED_FN (DECL)) - -/* Nonzero iff we are currently processing a declaration for an - entity with its own template parameter list, and which is not a - full specialization. */ -#define PROCESSING_REAL_TEMPLATE_DECL_P() \ - (processing_template_decl > template_class_depth (current_scope ())) - -/* Nonzero if this VAR_DECL or FUNCTION_DECL has already been - instantiated, i.e. its definition has been generated from the - pattern given in the template. */ -#define DECL_TEMPLATE_INSTANTIATED(NODE) \ - DECL_LANG_FLAG_1 (VAR_OR_FUNCTION_DECL_CHECK (NODE)) - -/* We know what we're doing with this decl now. */ -#define DECL_INTERFACE_KNOWN(NODE) DECL_LANG_FLAG_5 (NODE) - -/* DECL_EXTERNAL must be set on a decl until the decl is actually emitted, - so that assemble_external will work properly. So we have this flag to - tell us whether the decl is really not external. - - This flag does not indicate whether or not the decl is defined in the - current translation unit; it indicates whether or not we should emit the - decl at the end of compilation if it is defined and needed. */ -#define DECL_NOT_REALLY_EXTERN(NODE) \ - (DECL_LANG_SPECIFIC (NODE)->u.base.not_really_extern) - -#define DECL_REALLY_EXTERN(NODE) \ - (DECL_EXTERNAL (NODE) \ - && (!DECL_LANG_SPECIFIC (NODE) || !DECL_NOT_REALLY_EXTERN (NODE))) - -/* A thunk is a stub function. - - A thunk is an alternate entry point for an ordinary FUNCTION_DECL. - The address of the ordinary FUNCTION_DECL is given by the - DECL_INITIAL, which is always an ADDR_EXPR whose operand is a - FUNCTION_DECL. The job of the thunk is to either adjust the this - pointer before transferring control to the FUNCTION_DECL, or call - FUNCTION_DECL and then adjust the result value. Note, the result - pointer adjusting thunk must perform a call to the thunked - function, (or be implemented via passing some invisible parameter - to the thunked function, which is modified to perform the - adjustment just before returning). - - A thunk may perform either, or both, of the following operations: - - o Adjust the this or result pointer by a constant offset. - o Adjust the this or result pointer by looking up a vcall or vbase offset - in the vtable. - - A this pointer adjusting thunk converts from a base to a derived - class, and hence adds the offsets. A result pointer adjusting thunk - converts from a derived class to a base, and hence subtracts the - offsets. If both operations are performed, then the constant - adjustment is performed first for this pointer adjustment and last - for the result pointer adjustment. - - The constant adjustment is given by THUNK_FIXED_OFFSET. If the - vcall or vbase offset is required, THUNK_VIRTUAL_OFFSET is - used. For this pointer adjusting thunks, it is the vcall offset - into the vtable. For result pointer adjusting thunks it is the - binfo of the virtual base to convert to. Use that binfo's vbase - offset. - - It is possible to have equivalent covariant thunks. These are - distinct virtual covariant thunks whose vbase offsets happen to - have the same value. THUNK_ALIAS is used to pick one as the - canonical thunk, which will get all the this pointer adjusting - thunks attached to it. */ - -/* An integer indicating how many bytes should be subtracted from the - this or result pointer when this function is called. */ -#define THUNK_FIXED_OFFSET(DECL) \ - (DECL_LANG_SPECIFIC (THUNK_FUNCTION_CHECK (DECL))->u.fn.u5.fixed_offset) - -/* A tree indicating how to perform the virtual adjustment. For a this - adjusting thunk it is the number of bytes to be added to the vtable - to find the vcall offset. For a result adjusting thunk, it is the - binfo of the relevant virtual base. If NULL, then there is no - virtual adjust. (The vptr is always located at offset zero from - the this or result pointer.) (If the covariant type is within the - class hierarchy being laid out, the vbase index is not yet known - at the point we need to create the thunks, hence the need to use - binfos.) */ - -#define THUNK_VIRTUAL_OFFSET(DECL) \ - (LANG_DECL_U2_CHECK (FUNCTION_DECL_CHECK (DECL), 0)->access) - -/* A thunk which is equivalent to another thunk. */ -#define THUNK_ALIAS(DECL) \ - (DECL_LANG_SPECIFIC (FUNCTION_DECL_CHECK (DECL))->u.min.template_info) - -/* For thunk NODE, this is the FUNCTION_DECL thunked to. It is - possible for the target to be a thunk too. */ -#define THUNK_TARGET(NODE) \ - (LANG_DECL_FN_CHECK (NODE)->befriending_classes) - -/* True for a SCOPE_REF iff the "template" keyword was used to - indicate that the qualified name denotes a template. */ -#define QUALIFIED_NAME_IS_TEMPLATE(NODE) \ - (TREE_LANG_FLAG_1 (SCOPE_REF_CHECK (NODE))) - -/* True for an OMP_ATOMIC that has dependent parameters. These are stored - as an expr in operand 1, and integer_zero_node in operand 0. */ -#define OMP_ATOMIC_DEPENDENT_P(NODE) \ - (TREE_CODE (TREE_OPERAND (OMP_ATOMIC_CHECK (NODE), 0)) == INTEGER_CST) - -/* Used while gimplifying continue statements bound to OMP_FOR nodes. */ -#define OMP_FOR_GIMPLIFYING_P(NODE) \ - (TREE_LANG_FLAG_0 (OMP_LOOP_CHECK (NODE))) - -/* A language-specific token attached to the OpenMP data clauses to - hold code (or code fragments) related to ctors, dtors, and op=. - See semantics.c for details. */ -#define CP_OMP_CLAUSE_INFO(NODE) \ - TREE_TYPE (OMP_CLAUSE_RANGE_CHECK (NODE, OMP_CLAUSE_PRIVATE, \ - OMP_CLAUSE_LINEAR)) - -/* Nonzero if this transaction expression's body contains statements. */ -#define TRANSACTION_EXPR_IS_STMT(NODE) \ - TREE_LANG_FLAG_0 (TRANSACTION_EXPR_CHECK (NODE)) - -/* These macros provide convenient access to the various _STMT nodes - created when parsing template declarations. */ -#define TRY_STMTS(NODE) TREE_OPERAND (TRY_BLOCK_CHECK (NODE), 0) -#define TRY_HANDLERS(NODE) TREE_OPERAND (TRY_BLOCK_CHECK (NODE), 1) - -#define EH_SPEC_STMTS(NODE) TREE_OPERAND (EH_SPEC_BLOCK_CHECK (NODE), 0) -#define EH_SPEC_RAISES(NODE) TREE_OPERAND (EH_SPEC_BLOCK_CHECK (NODE), 1) - -#define USING_STMT_NAMESPACE(NODE) TREE_OPERAND (USING_STMT_CHECK (NODE), 0) - -/* Nonzero if this try block is a function try block. */ -#define FN_TRY_BLOCK_P(NODE) TREE_LANG_FLAG_3 (TRY_BLOCK_CHECK (NODE)) -#define HANDLER_PARMS(NODE) TREE_OPERAND (HANDLER_CHECK (NODE), 0) -#define HANDLER_BODY(NODE) TREE_OPERAND (HANDLER_CHECK (NODE), 1) -#define HANDLER_TYPE(NODE) TREE_TYPE (HANDLER_CHECK (NODE)) - -/* CLEANUP_STMT accessors. The statement(s) covered, the cleanup to run - and the VAR_DECL for which this cleanup exists. */ -#define CLEANUP_BODY(NODE) TREE_OPERAND (CLEANUP_STMT_CHECK (NODE), 0) -#define CLEANUP_EXPR(NODE) TREE_OPERAND (CLEANUP_STMT_CHECK (NODE), 1) -#define CLEANUP_DECL(NODE) TREE_OPERAND (CLEANUP_STMT_CHECK (NODE), 2) - -/* IF_STMT accessors. These give access to the condition of the if - statement, the then block of the if statement, and the else block - of the if statement if it exists. */ -#define IF_COND(NODE) TREE_OPERAND (IF_STMT_CHECK (NODE), 0) -#define THEN_CLAUSE(NODE) TREE_OPERAND (IF_STMT_CHECK (NODE), 1) -#define ELSE_CLAUSE(NODE) TREE_OPERAND (IF_STMT_CHECK (NODE), 2) -#define IF_SCOPE(NODE) TREE_OPERAND (IF_STMT_CHECK (NODE), 3) - -/* WHILE_STMT accessors. These give access to the condition of the - while statement and the body of the while statement, respectively. */ -#define WHILE_COND(NODE) TREE_OPERAND (WHILE_STMT_CHECK (NODE), 0) -#define WHILE_BODY(NODE) TREE_OPERAND (WHILE_STMT_CHECK (NODE), 1) - -/* DO_STMT accessors. These give access to the condition of the do - statement and the body of the do statement, respectively. */ -#define DO_COND(NODE) TREE_OPERAND (DO_STMT_CHECK (NODE), 0) -#define DO_BODY(NODE) TREE_OPERAND (DO_STMT_CHECK (NODE), 1) - -/* FOR_STMT accessors. These give access to the init statement, - condition, update expression, and body of the for statement, - respectively. */ -#define FOR_INIT_STMT(NODE) TREE_OPERAND (FOR_STMT_CHECK (NODE), 0) -#define FOR_COND(NODE) TREE_OPERAND (FOR_STMT_CHECK (NODE), 1) -#define FOR_EXPR(NODE) TREE_OPERAND (FOR_STMT_CHECK (NODE), 2) -#define FOR_BODY(NODE) TREE_OPERAND (FOR_STMT_CHECK (NODE), 3) -#define FOR_SCOPE(NODE) TREE_OPERAND (FOR_STMT_CHECK (NODE), 4) - -/* RANGE_FOR_STMT accessors. These give access to the declarator, - expression, body, and scope of the statement, respectively. */ -#define RANGE_FOR_DECL(NODE) TREE_OPERAND (RANGE_FOR_STMT_CHECK (NODE), 0) -#define RANGE_FOR_EXPR(NODE) TREE_OPERAND (RANGE_FOR_STMT_CHECK (NODE), 1) -#define RANGE_FOR_BODY(NODE) TREE_OPERAND (RANGE_FOR_STMT_CHECK (NODE), 2) -#define RANGE_FOR_SCOPE(NODE) TREE_OPERAND (RANGE_FOR_STMT_CHECK (NODE), 3) -#define RANGE_FOR_IVDEP(NODE) TREE_LANG_FLAG_6 (RANGE_FOR_STMT_CHECK (NODE)) - -#define SWITCH_STMT_COND(NODE) TREE_OPERAND (SWITCH_STMT_CHECK (NODE), 0) -#define SWITCH_STMT_BODY(NODE) TREE_OPERAND (SWITCH_STMT_CHECK (NODE), 1) -#define SWITCH_STMT_TYPE(NODE) TREE_OPERAND (SWITCH_STMT_CHECK (NODE), 2) -#define SWITCH_STMT_SCOPE(NODE) TREE_OPERAND (SWITCH_STMT_CHECK (NODE), 3) - -/* STMT_EXPR accessor. */ -#define STMT_EXPR_STMT(NODE) TREE_OPERAND (STMT_EXPR_CHECK (NODE), 0) - -/* EXPR_STMT accessor. This gives the expression associated with an - expression statement. */ -#define EXPR_STMT_EXPR(NODE) TREE_OPERAND (EXPR_STMT_CHECK (NODE), 0) - -/* True if this TARGET_EXPR was created by build_cplus_new, and so we can - discard it if it isn't useful. */ -#define TARGET_EXPR_IMPLICIT_P(NODE) \ - TREE_LANG_FLAG_0 (TARGET_EXPR_CHECK (NODE)) - -/* True if this TARGET_EXPR is the result of list-initialization of a - temporary. */ -#define TARGET_EXPR_LIST_INIT_P(NODE) \ - TREE_LANG_FLAG_1 (TARGET_EXPR_CHECK (NODE)) - -/* True if this TARGET_EXPR expresses direct-initialization of an object - to be named later. */ -#define TARGET_EXPR_DIRECT_INIT_P(NODE) \ - TREE_LANG_FLAG_2 (TARGET_EXPR_CHECK (NODE)) - -/* True if EXPR expresses direct-initialization of a TYPE. */ -#define DIRECT_INIT_EXPR_P(TYPE,EXPR) \ - (TREE_CODE (EXPR) == TARGET_EXPR && TREE_LANG_FLAG_2 (EXPR) \ - && same_type_ignoring_top_level_qualifiers_p (TYPE, TREE_TYPE (EXPR))) - -/* True if this CONVERT_EXPR is for a conversion to virtual base in - an NSDMI, and should be re-evaluated when used in a constructor. */ -#define CONVERT_EXPR_VBASE_PATH(NODE) \ - TREE_LANG_FLAG_0 (CONVERT_EXPR_CHECK (NODE)) - -/* True if SIZEOF_EXPR argument is type. */ -#define SIZEOF_EXPR_TYPE_P(NODE) \ - TREE_LANG_FLAG_0 (SIZEOF_EXPR_CHECK (NODE)) - -/* True if INTEGER_CST is a zero literal seen in function argument list. */ -#define LITERAL_ZERO_P(NODE) \ - (INTEGER_CST_CHECK (NODE)->base.nothrow_flag) - -/* An enumeration of the kind of tags that C++ accepts. */ -enum tag_types { - none_type = 0, /* Not a tag type. */ - record_type, /* "struct" types. */ - class_type, /* "class" types. */ - union_type, /* "union" types. */ - enum_type, /* "enum" types. */ - typename_type /* "typename" types. */ -}; - -/* The various kinds of lvalues we distinguish. */ -enum cp_lvalue_kind_flags { - clk_none = 0, /* Things that are not an lvalue. */ - clk_ordinary = 1, /* An ordinary lvalue. */ - clk_rvalueref = 2,/* An xvalue (rvalue formed using an rvalue reference) */ - clk_class = 4, /* A prvalue of class-type. */ - clk_bitfield = 8, /* An lvalue for a bit-field. */ - clk_packed = 16 /* An lvalue for a packed field. */ -}; - -/* This type is used for parameters and variables which hold - combinations of the flags in enum cp_lvalue_kind_flags. */ -typedef int cp_lvalue_kind; - -/* Various kinds of template specialization, instantiation, etc. */ -typedef enum tmpl_spec_kind { - tsk_none, /* Not a template at all. */ - tsk_invalid_member_spec, /* An explicit member template - specialization, but the enclosing - classes have not all been explicitly - specialized. */ - tsk_invalid_expl_inst, /* An explicit instantiation containing - template parameter lists. */ - tsk_excessive_parms, /* A template declaration with too many - template parameter lists. */ - tsk_insufficient_parms, /* A template declaration with too few - parameter lists. */ - tsk_template, /* A template declaration. */ - tsk_expl_spec, /* An explicit specialization. */ - tsk_expl_inst /* An explicit instantiation. */ -} tmpl_spec_kind; - -/* The various kinds of access. BINFO_ACCESS depends on these being - two bit quantities. The numerical values are important; they are - used to initialize RTTI data structures, so changing them changes - the ABI. */ -typedef enum access_kind { - ak_none = 0, /* Inaccessible. */ - ak_public = 1, /* Accessible, as a `public' thing. */ - ak_protected = 2, /* Accessible, as a `protected' thing. */ - ak_private = 3 /* Accessible, as a `private' thing. */ -} access_kind; - -/* The various kinds of special functions. If you add to this list, - you should update special_function_p as well. */ -typedef enum special_function_kind { - sfk_none = 0, /* Not a special function. This enumeral - must have value zero; see - special_function_p. */ - sfk_constructor, /* A constructor. */ - sfk_copy_constructor, /* A copy constructor. */ - sfk_move_constructor, /* A move constructor. */ - sfk_copy_assignment, /* A copy assignment operator. */ - sfk_move_assignment, /* A move assignment operator. */ - sfk_destructor, /* A destructor. */ - sfk_complete_destructor, /* A destructor for complete objects. */ - sfk_base_destructor, /* A destructor for base subobjects. */ - sfk_deleting_destructor, /* A destructor for complete objects that - deletes the object after it has been - destroyed. */ - sfk_conversion, /* A conversion operator. */ - sfk_inheriting_constructor /* An inheriting constructor */ -} special_function_kind; - -/* The various kinds of linkage. From [basic.link], - - A name is said to have linkage when it might denote the same - object, reference, function, type, template, namespace or value - as a name introduced in another scope: - - -- When a name has external linkage, the entity it denotes can - be referred to from scopes of other translation units or from - other scopes of the same translation unit. - - -- When a name has internal linkage, the entity it denotes can - be referred to by names from other scopes in the same - translation unit. - - -- When a name has no linkage, the entity it denotes cannot be - referred to by names from other scopes. */ - -typedef enum linkage_kind { - lk_none, /* No linkage. */ - lk_internal, /* Internal linkage. */ - lk_external /* External linkage. */ -} linkage_kind; - -typedef enum duration_kind { - dk_static, - dk_thread, - dk_auto, - dk_dynamic -} duration_kind; - -/* Bitmask flags to control type substitution. */ -enum tsubst_flags { - tf_none = 0, /* nothing special */ - tf_error = 1 << 0, /* give error messages */ - tf_warning = 1 << 1, /* give warnings too */ - tf_ignore_bad_quals = 1 << 2, /* ignore bad cvr qualifiers */ - tf_keep_type_decl = 1 << 3, /* retain typedef type decls - (make_typename_type use) */ - tf_ptrmem_ok = 1 << 4, /* pointers to member ok (internal - instantiate_type use) */ - tf_user = 1 << 5, /* found template must be a user template - (lookup_template_class use) */ - tf_conv = 1 << 6, /* We are determining what kind of - conversion might be permissible, - not actually performing the - conversion. */ - tf_decltype = 1 << 7, /* We are the operand of decltype. - Used to implement the special rules - for calls in decltype (5.2.2/11). */ - tf_partial = 1 << 8, /* Doing initial explicit argument - substitution in fn_type_unification. */ - /* Convenient substitution flags combinations. */ - tf_warning_or_error = tf_warning | tf_error -}; - -/* This type is used for parameters and variables which hold - combinations of the flags in enum tsubst_flags. */ -typedef int tsubst_flags_t; - -/* The kind of checking we can do looking in a class hierarchy. */ -enum base_access_flags { - ba_any = 0, /* Do not check access, allow an ambiguous base, - prefer a non-virtual base */ - ba_unique = 1 << 0, /* Must be a unique base. */ - ba_check_bit = 1 << 1, /* Check access. */ - ba_check = ba_unique | ba_check_bit, - ba_ignore_scope = 1 << 2 /* Ignore access allowed by local scope. */ -}; - -/* This type is used for parameters and variables which hold - combinations of the flags in enum base_access_flags. */ -typedef int base_access; - -/* The various kinds of access check during parsing. */ -typedef enum deferring_kind { - dk_no_deferred = 0, /* Check access immediately */ - dk_deferred = 1, /* Deferred check */ - dk_no_check = 2 /* No access check */ -} deferring_kind; - -/* The kind of base we can find, looking in a class hierarchy. - Values <0 indicate we failed. */ -typedef enum base_kind { - bk_inaccessible = -3, /* The base is inaccessible */ - bk_ambig = -2, /* The base is ambiguous */ - bk_not_base = -1, /* It is not a base */ - bk_same_type = 0, /* It is the same type */ - bk_proper_base = 1, /* It is a proper base */ - bk_via_virtual = 2 /* It is a proper base, but via a virtual - path. This might not be the canonical - binfo. */ -} base_kind; - -/* Node for "pointer to (virtual) function". - This may be distinct from ptr_type_node so gdb can distinguish them. */ -#define vfunc_ptr_type_node vtable_entry_type - - -/* For building calls to `delete'. */ -extern GTY(()) tree integer_two_node; - -/* The number of function bodies which we are currently processing. - (Zero if we are at namespace scope, one inside the body of a - function, two inside the body of a function in a local class, etc.) */ -extern int function_depth; - -/* Nonzero if we are inside eq_specializations, which affects comparison of - PARM_DECLs in cp_tree_equal. */ -extern int comparing_specializations; - -/* In parser.c. */ - -/* Nonzero if we are parsing an unevaluated operand: an operand to - sizeof, typeof, or alignof. This is a count since operands to - sizeof can be nested. */ - -extern int cp_unevaluated_operand; - -/* in pt.c */ - -/* These values are used for the `STRICT' parameter to type_unification and - fn_type_unification. Their meanings are described with the - documentation for fn_type_unification. */ - -typedef enum unification_kind_t { - DEDUCE_CALL, - DEDUCE_CONV, - DEDUCE_EXACT -} unification_kind_t; - -/* in class.c */ - -extern int current_class_depth; - -/* An array of all local classes present in this translation unit, in - declaration order. */ -extern GTY(()) vec *local_classes; - -/* Here's where we control how name mangling takes place. */ - -/* Cannot use '$' up front, because this confuses gdb - (names beginning with '$' are gdb-local identifiers). - - Note that all forms in which the '$' is significant are long enough - for direct indexing (meaning that if we know there is a '$' - at a particular location, we can index into the string at - any other location that provides distinguishing characters). */ - -/* Define NO_DOT_IN_LABEL in your favorite tm file if your assembler - doesn't allow '.' in symbol names. */ -#ifndef NO_DOT_IN_LABEL - -#define JOINER '.' - -#define AUTO_TEMP_NAME "_.tmp_" -#define VFIELD_BASE ".vf" -#define VFIELD_NAME "_vptr." -#define VFIELD_NAME_FORMAT "_vptr.%s" - -#else /* NO_DOT_IN_LABEL */ - -#ifndef NO_DOLLAR_IN_LABEL - -#define JOINER '$' - -#define AUTO_TEMP_NAME "_$tmp_" -#define VFIELD_BASE "$vf" -#define VFIELD_NAME "_vptr$" -#define VFIELD_NAME_FORMAT "_vptr$%s" - -#else /* NO_DOLLAR_IN_LABEL */ - -#define AUTO_TEMP_NAME "__tmp_" -#define TEMP_NAME_P(ID_NODE) \ - (!strncmp (IDENTIFIER_POINTER (ID_NODE), AUTO_TEMP_NAME, \ - sizeof (AUTO_TEMP_NAME) - 1)) -#define VTABLE_NAME "__vt_" -#define VTABLE_NAME_P(ID_NODE) \ - (!strncmp (IDENTIFIER_POINTER (ID_NODE), VTABLE_NAME, \ - sizeof (VTABLE_NAME) - 1)) -#define VFIELD_BASE "__vfb" -#define VFIELD_NAME "__vptr_" -#define VFIELD_NAME_P(ID_NODE) \ - (!strncmp (IDENTIFIER_POINTER (ID_NODE), VFIELD_NAME, \ - sizeof (VFIELD_NAME) - 1)) -#define VFIELD_NAME_FORMAT "__vptr_%s" - -#endif /* NO_DOLLAR_IN_LABEL */ -#endif /* NO_DOT_IN_LABEL */ - -#define THIS_NAME "this" - -#define IN_CHARGE_NAME "__in_chrg" - -#define VTBL_PTR_TYPE "__vtbl_ptr_type" -#define VTABLE_DELTA_NAME "__delta" -#define VTABLE_PFN_NAME "__pfn" - -#define LAMBDANAME_PREFIX "__lambda" -#define LAMBDANAME_FORMAT LAMBDANAME_PREFIX "%d" - -#define UDLIT_OP_ANSI_PREFIX "operator\"\"" -#define UDLIT_OP_ANSI_FORMAT UDLIT_OP_ANSI_PREFIX "%s" -#define UDLIT_OP_MANGLED_PREFIX "li" -#define UDLIT_OP_MANGLED_FORMAT UDLIT_OP_MANGLED_PREFIX "%s" -#define UDLIT_OPER_P(ID_NODE) \ - (!strncmp (IDENTIFIER_POINTER (ID_NODE), \ - UDLIT_OP_ANSI_PREFIX, \ - sizeof (UDLIT_OP_ANSI_PREFIX) - 1)) -#define UDLIT_OP_SUFFIX(ID_NODE) \ - (IDENTIFIER_POINTER (ID_NODE) + sizeof (UDLIT_OP_ANSI_PREFIX) - 1) - -#if !defined(NO_DOLLAR_IN_LABEL) || !defined(NO_DOT_IN_LABEL) - -#define VTABLE_NAME_P(ID_NODE) (IDENTIFIER_POINTER (ID_NODE)[1] == 'v' \ - && IDENTIFIER_POINTER (ID_NODE)[2] == 't' \ - && IDENTIFIER_POINTER (ID_NODE)[3] == JOINER) - -#define TEMP_NAME_P(ID_NODE) \ - (!strncmp (IDENTIFIER_POINTER (ID_NODE), AUTO_TEMP_NAME, sizeof (AUTO_TEMP_NAME)-1)) -#define VFIELD_NAME_P(ID_NODE) \ - (!strncmp (IDENTIFIER_POINTER (ID_NODE), VFIELD_NAME, sizeof(VFIELD_NAME)-1)) - -#endif /* !defined(NO_DOLLAR_IN_LABEL) || !defined(NO_DOT_IN_LABEL) */ - - -/* Nonzero if we're done parsing and into end-of-file activities. */ - -extern int at_eof; - -/* True if note_mangling_alias should enqueue mangling aliases for - later generation, rather than emitting them right away. */ - -extern bool defer_mangling_aliases; - -/* A list of namespace-scope objects which have constructors or - destructors which reside in the global scope. The decl is stored - in the TREE_VALUE slot and the initializer is stored in the - TREE_PURPOSE slot. */ -extern GTY(()) tree static_aggregates; -/* Likewise, for thread local storage. */ -extern GTY(()) tree tls_aggregates; - -enum overload_flags { NO_SPECIAL = 0, DTOR_FLAG, TYPENAME_FLAG }; - -/* These are uses as bits in flags passed to various functions to - control their behavior. Despite the LOOKUP_ prefix, many of these - do not control name lookup. ??? Functions using these flags should - probably be modified to accept explicit boolean flags for the - behaviors relevant to them. */ -/* Check for access violations. */ -#define LOOKUP_PROTECT (1 << 0) -#define LOOKUP_NORMAL (LOOKUP_PROTECT) -/* Even if the function found by lookup is a virtual function, it - should be called directly. */ -#define LOOKUP_NONVIRTUAL (1 << 1) -/* Non-converting (i.e., "explicit") constructors are not tried. This flag - indicates that we are not performing direct-initialization. */ -#define LOOKUP_ONLYCONVERTING (1 << 2) -#define LOOKUP_IMPLICIT (LOOKUP_NORMAL | LOOKUP_ONLYCONVERTING) -/* If a temporary is created, it should be created so that it lives - as long as the current variable bindings; otherwise it only lives - until the end of the complete-expression. It also forces - direct-initialization in cases where other parts of the compiler - have already generated a temporary, such as reference - initialization and the catch parameter. */ -#define DIRECT_BIND (1 << 3) -/* We're performing a user-defined conversion, so more user-defined - conversions are not permitted (only built-in conversions). */ -#define LOOKUP_NO_CONVERSION (1 << 4) -/* The user has explicitly called a destructor. (Therefore, we do - not need to check that the object is non-NULL before calling the - destructor.) */ -#define LOOKUP_DESTRUCTOR (1 << 5) -/* Do not permit references to bind to temporaries. */ -#define LOOKUP_NO_TEMP_BIND (1 << 6) -/* Do not accept objects, and possibly namespaces. */ -#define LOOKUP_PREFER_TYPES (1 << 7) -/* Do not accept objects, and possibly types. */ -#define LOOKUP_PREFER_NAMESPACES (1 << 8) -/* Accept types or namespaces. */ -#define LOOKUP_PREFER_BOTH (LOOKUP_PREFER_TYPES | LOOKUP_PREFER_NAMESPACES) -/* Return friend declarations and un-declared builtin functions. - (Normally, these entities are registered in the symbol table, but - not found by lookup.) */ -#define LOOKUP_HIDDEN (LOOKUP_PREFER_NAMESPACES << 1) -/* Prefer that the lvalue be treated as an rvalue. */ -#define LOOKUP_PREFER_RVALUE (LOOKUP_HIDDEN << 1) -/* We're inside an init-list, so narrowing conversions are ill-formed. */ -#define LOOKUP_NO_NARROWING (LOOKUP_PREFER_RVALUE << 1) -/* We're looking up a constructor for list-initialization. */ -#define LOOKUP_LIST_INIT_CTOR (LOOKUP_NO_NARROWING << 1) -/* This is the first parameter of a copy constructor. */ -#define LOOKUP_COPY_PARM (LOOKUP_LIST_INIT_CTOR << 1) -/* We only want to consider list constructors. */ -#define LOOKUP_LIST_ONLY (LOOKUP_COPY_PARM << 1) -/* Return after determining which function to call and checking access. - Used by sythesized_method_walk to determine which functions will - be called to initialize subobjects, in order to determine exception - specification and possible implicit delete. - This is kind of a hack, but exiting early avoids problems with trying - to perform argument conversions when the class isn't complete yet. */ -#define LOOKUP_SPECULATIVE (LOOKUP_LIST_ONLY << 1) -/* Used by calls from defaulted functions to limit the overload set to avoid - cycles trying to declare them (core issue 1092). */ -#define LOOKUP_DEFAULTED (LOOKUP_SPECULATIVE << 1) -/* Used in calls to store_init_value to suppress its usual call to - digest_init. */ -#define LOOKUP_ALREADY_DIGESTED (LOOKUP_DEFAULTED << 1) -/* An instantiation with explicit template arguments. */ -#define LOOKUP_EXPLICIT_TMPL_ARGS (LOOKUP_ALREADY_DIGESTED << 1) -/* Like LOOKUP_NO_TEMP_BIND, but also prevent binding to xvalues. */ -#define LOOKUP_NO_RVAL_BIND (LOOKUP_EXPLICIT_TMPL_ARGS << 1) -/* Used by case_conversion to disregard non-integral conversions. */ -#define LOOKUP_NO_NON_INTEGRAL (LOOKUP_NO_RVAL_BIND << 1) -/* Used for delegating constructors in order to diagnose self-delegation. */ -#define LOOKUP_DELEGATING_CONS (LOOKUP_NO_NON_INTEGRAL << 1) - -#define LOOKUP_NAMESPACES_ONLY(F) \ - (((F) & LOOKUP_PREFER_NAMESPACES) && !((F) & LOOKUP_PREFER_TYPES)) -#define LOOKUP_TYPES_ONLY(F) \ - (!((F) & LOOKUP_PREFER_NAMESPACES) && ((F) & LOOKUP_PREFER_TYPES)) -#define LOOKUP_QUALIFIERS_ONLY(F) ((F) & LOOKUP_PREFER_BOTH) - - -/* These flags are used by the conversion code. - CONV_IMPLICIT : Perform implicit conversions (standard and user-defined). - CONV_STATIC : Perform the explicit conversions for static_cast. - CONV_CONST : Perform the explicit conversions for const_cast. - CONV_REINTERPRET: Perform the explicit conversions for reinterpret_cast. - CONV_PRIVATE : Perform upcasts to private bases. - CONV_FORCE_TEMP : Require a new temporary when converting to the same - aggregate type. */ - -#define CONV_IMPLICIT 1 -#define CONV_STATIC 2 -#define CONV_CONST 4 -#define CONV_REINTERPRET 8 -#define CONV_PRIVATE 16 -/* #define CONV_NONCONVERTING 32 */ -#define CONV_FORCE_TEMP 64 -#define CONV_OLD_CONVERT (CONV_IMPLICIT | CONV_STATIC | CONV_CONST \ - | CONV_REINTERPRET) -#define CONV_C_CAST (CONV_IMPLICIT | CONV_STATIC | CONV_CONST \ - | CONV_REINTERPRET | CONV_PRIVATE | CONV_FORCE_TEMP) - -/* Used by build_expr_type_conversion to indicate which types are - acceptable as arguments to the expression under consideration. */ - -#define WANT_INT 1 /* integer types, including bool */ -#define WANT_FLOAT 2 /* floating point types */ -#define WANT_ENUM 4 /* enumerated types */ -#define WANT_POINTER 8 /* pointer types */ -#define WANT_NULL 16 /* null pointer constant */ -#define WANT_VECTOR_OR_COMPLEX 32 /* vector or complex types */ -#define WANT_ARITH (WANT_INT | WANT_FLOAT | WANT_VECTOR_OR_COMPLEX) - -/* Used with comptypes, and related functions, to guide type - comparison. */ - -#define COMPARE_STRICT 0 /* Just check if the types are the - same. */ -#define COMPARE_BASE 1 /* Check to see if the second type is - derived from the first. */ -#define COMPARE_DERIVED 2 /* Like COMPARE_BASE, but in - reverse. */ -#define COMPARE_REDECLARATION 4 /* The comparison is being done when - another declaration of an existing - entity is seen. */ -#define COMPARE_STRUCTURAL 8 /* The comparison is intended to be - structural. The actual comparison - will be identical to - COMPARE_STRICT. */ - -/* Used with push_overloaded_decl. */ -#define PUSH_GLOBAL 0 /* Push the DECL into namespace scope, - regardless of the current scope. */ -#define PUSH_LOCAL 1 /* Push the DECL into the current - scope. */ -#define PUSH_USING 2 /* We are pushing this DECL as the - result of a using declaration. */ - -/* Used with start function. */ -#define SF_DEFAULT 0 /* No flags. */ -#define SF_PRE_PARSED 1 /* The function declaration has - already been parsed. */ -#define SF_INCLASS_INLINE 2 /* The function is an inline, defined - in the class body. */ - -/* Used with start_decl's initialized parameter. */ -#define SD_UNINITIALIZED 0 -#define SD_INITIALIZED 1 -#define SD_DEFAULTED 2 -#define SD_DELETED 3 - -/* Returns nonzero iff TYPE1 and TYPE2 are the same type, or if TYPE2 - is derived from TYPE1, or if TYPE2 is a pointer (reference) to a - class derived from the type pointed to (referred to) by TYPE1. */ -#define same_or_base_type_p(TYPE1, TYPE2) \ - comptypes ((TYPE1), (TYPE2), COMPARE_BASE) - -/* These macros are used to access a TEMPLATE_PARM_INDEX. */ -#define TEMPLATE_PARM_INDEX_CAST(NODE) \ - ((template_parm_index*)TEMPLATE_PARM_INDEX_CHECK (NODE)) -#define TEMPLATE_PARM_IDX(NODE) (TEMPLATE_PARM_INDEX_CAST (NODE)->index) -#define TEMPLATE_PARM_LEVEL(NODE) (TEMPLATE_PARM_INDEX_CAST (NODE)->level) -#define TEMPLATE_PARM_DESCENDANTS(NODE) (TREE_CHAIN (NODE)) -#define TEMPLATE_PARM_ORIG_LEVEL(NODE) (TEMPLATE_PARM_INDEX_CAST (NODE)->orig_level) -#define TEMPLATE_PARM_DECL(NODE) (TEMPLATE_PARM_INDEX_CAST (NODE)->decl) -#define TEMPLATE_PARM_PARAMETER_PACK(NODE) \ - (TREE_LANG_FLAG_0 (TEMPLATE_PARM_INDEX_CHECK (NODE))) - -/* These macros are for accessing the fields of TEMPLATE_TYPE_PARM, - TEMPLATE_TEMPLATE_PARM and BOUND_TEMPLATE_TEMPLATE_PARM nodes. */ -#define TEMPLATE_TYPE_PARM_INDEX(NODE) \ - (TYPE_VALUES_RAW (TREE_CHECK3 ((NODE), TEMPLATE_TYPE_PARM, \ - TEMPLATE_TEMPLATE_PARM, \ - BOUND_TEMPLATE_TEMPLATE_PARM))) -#define TEMPLATE_TYPE_IDX(NODE) \ - (TEMPLATE_PARM_IDX (TEMPLATE_TYPE_PARM_INDEX (NODE))) -#define TEMPLATE_TYPE_LEVEL(NODE) \ - (TEMPLATE_PARM_LEVEL (TEMPLATE_TYPE_PARM_INDEX (NODE))) -#define TEMPLATE_TYPE_ORIG_LEVEL(NODE) \ - (TEMPLATE_PARM_ORIG_LEVEL (TEMPLATE_TYPE_PARM_INDEX (NODE))) -#define TEMPLATE_TYPE_DECL(NODE) \ - (TEMPLATE_PARM_DECL (TEMPLATE_TYPE_PARM_INDEX (NODE))) -#define TEMPLATE_TYPE_PARAMETER_PACK(NODE) \ - (TEMPLATE_PARM_PARAMETER_PACK (TEMPLATE_TYPE_PARM_INDEX (NODE))) - -/* True iff this TEMPLATE_TYPE_PARM represents decltype(auto). */ -#define AUTO_IS_DECLTYPE(NODE) \ - (TYPE_LANG_FLAG_5 (TEMPLATE_TYPE_PARM_CHECK (NODE))) - -/* These constants can used as bit flags in the process of tree formatting. - - TFF_PLAIN_IDENTIFIER: unqualified part of a name. - TFF_SCOPE: include the class and namespace scope of the name. - TFF_CHASE_TYPEDEF: print the original type-id instead of the typedef-name. - TFF_DECL_SPECIFIERS: print decl-specifiers. - TFF_CLASS_KEY_OR_ENUM: precede a class-type name (resp. enum name) with - a class-key (resp. `enum'). - TFF_RETURN_TYPE: include function return type. - TFF_FUNCTION_DEFAULT_ARGUMENTS: include function default parameter values. - TFF_EXCEPTION_SPECIFICATION: show function exception specification. - TFF_TEMPLATE_HEADER: show the template<...> header in a - template-declaration. - TFF_TEMPLATE_NAME: show only template-name. - TFF_EXPR_IN_PARENS: parenthesize expressions. - TFF_NO_FUNCTION_ARGUMENTS: don't show function arguments. - TFF_UNQUALIFIED_NAME: do not print the qualifying scope of the - top-level entity. - TFF_NO_OMIT_DEFAULT_TEMPLATE_ARGUMENTS: do not omit template arguments - identical to their defaults. - TFF_NO_TEMPLATE_BINDINGS: do not print information about the template - arguments for a function template specialization. - TFF_POINTER: we are printing a pointer type. */ - -#define TFF_PLAIN_IDENTIFIER (0) -#define TFF_SCOPE (1) -#define TFF_CHASE_TYPEDEF (1 << 1) -#define TFF_DECL_SPECIFIERS (1 << 2) -#define TFF_CLASS_KEY_OR_ENUM (1 << 3) -#define TFF_RETURN_TYPE (1 << 4) -#define TFF_FUNCTION_DEFAULT_ARGUMENTS (1 << 5) -#define TFF_EXCEPTION_SPECIFICATION (1 << 6) -#define TFF_TEMPLATE_HEADER (1 << 7) -#define TFF_TEMPLATE_NAME (1 << 8) -#define TFF_EXPR_IN_PARENS (1 << 9) -#define TFF_NO_FUNCTION_ARGUMENTS (1 << 10) -#define TFF_UNQUALIFIED_NAME (1 << 11) -#define TFF_NO_OMIT_DEFAULT_TEMPLATE_ARGUMENTS (1 << 12) -#define TFF_NO_TEMPLATE_BINDINGS (1 << 13) -#define TFF_POINTER (1 << 14) - -/* Returns the TEMPLATE_DECL associated to a TEMPLATE_TEMPLATE_PARM - node. */ -#define TEMPLATE_TEMPLATE_PARM_TEMPLATE_DECL(NODE) \ - ((TREE_CODE (NODE) == BOUND_TEMPLATE_TEMPLATE_PARM) \ - ? TYPE_TI_TEMPLATE (NODE) \ - : TYPE_NAME (NODE)) - -/* in lex.c */ - -extern void init_reswords (void); - -typedef struct GTY(()) operator_name_info_t { - /* The IDENTIFIER_NODE for the operator. */ - tree identifier; - /* The name of the operator. */ - const char *name; - /* The mangled name of the operator. */ - const char *mangled_name; - /* The arity of the operator. */ - int arity; -} operator_name_info_t; - -/* A mapping from tree codes to operator name information. */ -extern GTY(()) operator_name_info_t operator_name_info - [(int) MAX_TREE_CODES]; -/* Similar, but for assignment operators. */ -extern GTY(()) operator_name_info_t assignment_operator_name_info - [(int) MAX_TREE_CODES]; - -/* A type-qualifier, or bitmask therefore, using the TYPE_QUAL - constants. */ - -typedef int cp_cv_quals; - -/* Non-static member functions have an optional virt-specifier-seq. - There is a VIRT_SPEC value for each virt-specifier. - They can be combined by bitwise-or to form the complete set of - virt-specifiers for a member function. */ -enum virt_specifier - { - VIRT_SPEC_UNSPECIFIED = 0x0, - VIRT_SPEC_FINAL = 0x1, - VIRT_SPEC_OVERRIDE = 0x2 - }; - -/* A type-qualifier, or bitmask therefore, using the VIRT_SPEC - constants. */ - -typedef int cp_virt_specifiers; - -/* Wherever there is a function-cv-qual, there could also be a ref-qualifier: - - [dcl.fct] - The return type, the parameter-type-list, the ref-qualifier, and - the cv-qualifier-seq, but not the default arguments or the exception - specification, are part of the function type. - - REF_QUAL_NONE Ordinary member function with no ref-qualifier - REF_QUAL_LVALUE Member function with the &-ref-qualifier - REF_QUAL_RVALUE Member function with the &&-ref-qualifier */ - -enum cp_ref_qualifier { - REF_QUAL_NONE = 0, - REF_QUAL_LVALUE = 1, - REF_QUAL_RVALUE = 2 -}; - -/* A storage class. */ - -typedef enum cp_storage_class { - /* sc_none must be zero so that zeroing a cp_decl_specifier_seq - sets the storage_class field to sc_none. */ - sc_none = 0, - sc_auto, - sc_register, - sc_static, - sc_extern, - sc_mutable -} cp_storage_class; - -/* An individual decl-specifier. This is used to index the array of - locations for the declspecs in struct cp_decl_specifier_seq - below. */ - -typedef enum cp_decl_spec { - ds_first, - ds_signed = ds_first, - ds_unsigned, - ds_short, - ds_long, - ds_const, - ds_volatile, - ds_restrict, - ds_inline, - ds_virtual, - ds_explicit, - ds_friend, - ds_typedef, - ds_alias, - ds_constexpr, - ds_complex, - ds_thread, - ds_type_spec, - ds_redefined_builtin_type_spec, - ds_attribute, - ds_std_attribute, - ds_storage_class, - ds_long_long, - ds_last /* This enumerator must always be the last one. */ -} cp_decl_spec; - -/* A decl-specifier-seq. */ - -typedef struct cp_decl_specifier_seq { - /* An array of locations for the declaration sepecifiers, indexed by - enum cp_decl_spec_word. */ - source_location locations[ds_last]; - /* The primary type, if any, given by the decl-specifier-seq. - Modifiers, like "short", "const", and "unsigned" are not - reflected here. This field will be a TYPE, unless a typedef-name - was used, in which case it will be a TYPE_DECL. */ - tree type; - /* The attributes, if any, provided with the specifier sequence. */ - tree attributes; - /* The c++11 attributes that follows the type specifier. */ - tree std_attributes; - /* If non-NULL, a built-in type that the user attempted to redefine - to some other type. */ - tree redefined_builtin_type; - /* The storage class specified -- or sc_none if no storage class was - explicitly specified. */ - cp_storage_class storage_class; - /* For the __intN declspec, this stores the index into the int_n_* arrays. */ - int int_n_idx; - /* True iff TYPE_SPEC defines a class or enum. */ - BOOL_BITFIELD type_definition_p : 1; - /* True iff multiple types were (erroneously) specified for this - decl-specifier-seq. */ - BOOL_BITFIELD multiple_types_p : 1; - /* True iff multiple storage classes were (erroneously) specified - for this decl-specifier-seq or a combination of a storage class - with a typedef specifier. */ - BOOL_BITFIELD conflicting_specifiers_p : 1; - /* True iff at least one decl-specifier was found. */ - BOOL_BITFIELD any_specifiers_p : 1; - /* True iff at least one type-specifier was found. */ - BOOL_BITFIELD any_type_specifiers_p : 1; - /* True iff "int" was explicitly provided. */ - BOOL_BITFIELD explicit_int_p : 1; - /* True iff "__intN" was explicitly provided. */ - BOOL_BITFIELD explicit_intN_p : 1; - /* True iff "char" was explicitly provided. */ - BOOL_BITFIELD explicit_char_p : 1; - /* True iff ds_thread is set for __thread, not thread_local. */ - BOOL_BITFIELD gnu_thread_keyword_p : 1; - /* True iff the type is a decltype. */ - BOOL_BITFIELD decltype_p : 1; -} cp_decl_specifier_seq; - -/* The various kinds of declarators. */ - -typedef enum cp_declarator_kind { - cdk_id, - cdk_function, - cdk_array, - cdk_pointer, - cdk_reference, - cdk_ptrmem, - cdk_error -} cp_declarator_kind; - -/* A declarator. */ - -typedef struct cp_declarator cp_declarator; - -typedef struct cp_parameter_declarator cp_parameter_declarator; - -/* A parameter, before it has been semantically analyzed. */ -struct cp_parameter_declarator { - /* The next parameter, or NULL_TREE if none. */ - cp_parameter_declarator *next; - /* The decl-specifiers-seq for the parameter. */ - cp_decl_specifier_seq decl_specifiers; - /* The declarator for the parameter. */ - cp_declarator *declarator; - /* The default-argument expression, or NULL_TREE, if none. */ - tree default_argument; - /* True iff this is the first parameter in the list and the - parameter sequence ends with an ellipsis. */ - bool ellipsis_p; -}; - -/* A declarator. */ -struct cp_declarator { - /* The kind of declarator. */ - ENUM_BITFIELD (cp_declarator_kind) kind : 4; - /* Whether we parsed an ellipsis (`...') just before the declarator, - to indicate this is a parameter pack. */ - BOOL_BITFIELD parameter_pack_p : 1; - location_t id_loc; /* Currently only set for cdk_id and cdk_function. */ - /* GNU Attributes that apply to this declarator. If the declarator - is a pointer or a reference, these attribute apply to the type - pointed to. */ - tree attributes; - /* Standard C++11 attributes that apply to this declarator. If the - declarator is a pointer or a reference, these attributes apply - to the pointer, rather than to the type pointed to. */ - tree std_attributes; - /* For all but cdk_id and cdk_error, the contained declarator. For - cdk_id and cdk_error, guaranteed to be NULL. */ - cp_declarator *declarator; - union { - /* For identifiers. */ - struct { - /* If non-NULL, the qualifying scope (a NAMESPACE_DECL or - *_TYPE) for this identifier. */ - tree qualifying_scope; - /* The unqualified name of the entity -- an IDENTIFIER_NODE, - BIT_NOT_EXPR, or TEMPLATE_ID_EXPR. */ - tree unqualified_name; - /* If this is the name of a function, what kind of special - function (if any). */ - special_function_kind sfk; - } id; - /* For functions. */ - struct { - /* The parameters to the function as a TREE_LIST of decl/default. */ - tree parameters; - /* The cv-qualifiers for the function. */ - cp_cv_quals qualifiers; - /* The virt-specifiers for the function. */ - cp_virt_specifiers virt_specifiers; - /* The ref-qualifier for the function. */ - cp_ref_qualifier ref_qualifier; - /* The exception-specification for the function. */ - tree exception_specification; - /* The late-specified return type, if any. */ - tree late_return_type; - } function; - /* For arrays. */ - struct { - /* The bounds to the array. */ - tree bounds; - } array; - /* For cdk_pointer and cdk_ptrmem. */ - struct { - /* The cv-qualifiers for the pointer. */ - cp_cv_quals qualifiers; - /* For cdk_ptrmem, the class type containing the member. */ - tree class_type; - } pointer; - /* For cdk_reference */ - struct { - /* The cv-qualifiers for the reference. These qualifiers are - only used to diagnose ill-formed code. */ - cp_cv_quals qualifiers; - /* Whether this is an rvalue reference */ - bool rvalue_ref; - } reference; - } u; -}; - -/* A level of template instantiation. */ -struct GTY((chain_next ("%h.next"))) tinst_level { - /* The immediately deeper level in the chain. */ - struct tinst_level *next; - - /* The original node. Can be either a DECL (for a function or static - data member) or a TYPE (for a class), depending on what we were - asked to instantiate. */ - tree decl; - - /* The location where the template is instantiated. */ - location_t locus; - - /* errorcount+sorrycount when we pushed this level. */ - int errors; - - /* True if the location is in a system header. */ - bool in_system_header_p; -}; - -bool decl_spec_seq_has_spec_p (const cp_decl_specifier_seq *, cp_decl_spec); - -/* Return the type of the `this' parameter of FNTYPE. */ - -inline tree -type_of_this_parm (const_tree fntype) -{ - function_args_iterator iter; - gcc_assert (TREE_CODE (fntype) == METHOD_TYPE); - function_args_iter_init (&iter, fntype); - return function_args_iter_cond (&iter); -} - -/* Return the class of the `this' parameter of FNTYPE. */ - -inline tree -class_of_this_parm (const_tree fntype) -{ - return TREE_TYPE (type_of_this_parm (fntype)); -} - -/* True if T designates a variable template declaration. */ -inline bool -variable_template_p (tree t) -{ - if (TREE_CODE (t) != TEMPLATE_DECL) - return false; - if (!PRIMARY_TEMPLATE_P (t)) - return false; - if (tree r = DECL_TEMPLATE_RESULT (t)) - return VAR_P (r); - return false; -} - -/* A parameter list indicating for a function with no parameters, - e.g "int f(void)". */ -extern cp_parameter_declarator *no_parameters; - -/* True if we saw "#pragma GCC java_exceptions". */ -extern bool pragma_java_exceptions; - -/* in call.c */ -extern bool check_dtor_name (tree, tree); -bool magic_varargs_p (tree); - -extern tree build_conditional_expr (location_t, tree, tree, tree, - tsubst_flags_t); -extern tree build_addr_func (tree, tsubst_flags_t); -extern void set_flags_from_callee (tree); -extern tree build_call_a (tree, int, tree*); -extern tree build_call_n (tree, int, ...); -extern bool null_ptr_cst_p (tree); -extern bool null_member_pointer_value_p (tree); -extern bool sufficient_parms_p (const_tree); -extern tree type_decays_to (tree); -extern tree build_user_type_conversion (tree, tree, int, - tsubst_flags_t); -extern tree build_new_function_call (tree, vec **, bool, - tsubst_flags_t); -extern tree build_operator_new_call (tree, vec **, tree *, - tree *, tree, tree *, - tsubst_flags_t); -extern tree build_new_method_call (tree, tree, vec **, - tree, int, tree *, - tsubst_flags_t); -extern tree build_special_member_call (tree, tree, vec **, - tree, int, tsubst_flags_t); -extern tree build_new_op (location_t, enum tree_code, - int, tree, tree, tree, tree *, - tsubst_flags_t); -extern tree build_op_call (tree, vec **, - tsubst_flags_t); -extern bool non_placement_deallocation_fn_p (tree); -extern tree build_op_delete_call (enum tree_code, tree, tree, - bool, tree, tree, - tsubst_flags_t); -extern bool can_convert (tree, tree, tsubst_flags_t); -extern bool can_convert_standard (tree, tree, tsubst_flags_t); -extern bool can_convert_arg (tree, tree, tree, int, - tsubst_flags_t); -extern bool can_convert_arg_bad (tree, tree, tree, int, - tsubst_flags_t); -extern bool enforce_access (tree, tree, tree, - tsubst_flags_t); -extern void push_defarg_context (tree); -extern void pop_defarg_context (void); -extern tree convert_default_arg (tree, tree, tree, int, - tsubst_flags_t); -extern tree convert_arg_to_ellipsis (tree, tsubst_flags_t); -extern tree build_x_va_arg (source_location, tree, tree); -extern tree cxx_type_promotes_to (tree); -extern tree type_passed_as (tree); -extern tree convert_for_arg_passing (tree, tree, tsubst_flags_t); -extern bool is_properly_derived_from (tree, tree); -extern tree initialize_reference (tree, tree, int, - tsubst_flags_t); -extern tree extend_ref_init_temps (tree, tree, vec**); -extern tree make_temporary_var_for_ref_to_temp (tree, tree); -extern bool type_has_extended_temps (tree); -extern tree strip_top_quals (tree); -extern bool reference_related_p (tree, tree); -extern int remaining_arguments (tree); -extern tree perform_implicit_conversion (tree, tree, tsubst_flags_t); -extern tree perform_implicit_conversion_flags (tree, tree, tsubst_flags_t, int); -extern tree build_integral_nontype_arg_conv (tree, tree, tsubst_flags_t); -extern tree perform_direct_initialization_if_possible (tree, tree, bool, - tsubst_flags_t); -extern tree in_charge_arg_for_name (tree); -extern tree build_cxx_call (tree, int, tree *, - tsubst_flags_t); -extern bool is_std_init_list (tree); -extern bool is_list_ctor (tree); -#ifdef ENABLE_CHECKING -extern void validate_conversion_obstack (void); -#endif /* ENABLE_CHECKING */ -extern void mark_versions_used (tree); -extern tree get_function_version_dispatcher (tree); - -/* in class.c */ -extern tree build_vfield_ref (tree, tree); -extern tree build_base_path (enum tree_code, tree, - tree, int, tsubst_flags_t); -extern tree convert_to_base (tree, tree, bool, bool, - tsubst_flags_t); -extern tree convert_to_base_statically (tree, tree); -extern tree build_vtbl_ref (tree, tree); -extern tree build_vfn_ref (tree, tree); -extern tree get_vtable_decl (tree, int); -extern void resort_type_method_vec (void *, void *, - gt_pointer_operator, void *); -extern bool add_method (tree, tree, tree); -extern bool currently_open_class (tree); -extern tree currently_open_derived_class (tree); -extern tree outermost_open_class (void); -extern tree current_nonlambda_class_type (void); -extern tree finish_struct (tree, tree); -extern void finish_struct_1 (tree); -extern int resolves_to_fixed_type_p (tree, int *); -extern void init_class_processing (void); -extern int is_empty_class (tree); -extern bool is_really_empty_class (tree); -extern void pushclass (tree); -extern void popclass (void); -extern void push_nested_class (tree); -extern void pop_nested_class (void); -extern int current_lang_depth (void); -extern void push_lang_context (tree); -extern void pop_lang_context (void); -extern tree instantiate_type (tree, tree, tsubst_flags_t); -extern void print_class_statistics (void); -extern void build_self_reference (void); -extern int same_signature_p (const_tree, const_tree); -extern void maybe_add_class_template_decl_list (tree, tree, int); -extern void unreverse_member_declarations (tree); -extern void invalidate_class_lookup_cache (void); -extern void maybe_note_name_used_in_class (tree, tree); -extern void note_name_declared_in_class (tree, tree); -extern tree get_vtbl_decl_for_binfo (tree); -extern void debug_class (tree); -extern void debug_thunks (tree); -extern void set_linkage_according_to_type (tree, tree); -extern void determine_key_method (tree); -extern void check_for_override (tree, tree); -extern void push_class_stack (void); -extern void pop_class_stack (void); -extern bool type_has_user_nondefault_constructor (tree); -extern tree in_class_defaulted_default_constructor (tree); -extern bool user_provided_p (tree); -extern bool type_has_user_provided_constructor (tree); -extern bool type_has_non_user_provided_default_constructor (tree); -extern bool vbase_has_user_provided_move_assign (tree); -extern tree default_init_uninitialized_part (tree); -extern bool trivial_default_constructor_is_constexpr (tree); -extern bool type_has_constexpr_default_constructor (tree); -extern bool type_has_virtual_destructor (tree); -extern bool type_has_move_constructor (tree); -extern bool type_has_move_assign (tree); -extern bool type_has_user_declared_move_constructor (tree); -extern bool type_has_user_declared_move_assign(tree); -extern bool type_build_ctor_call (tree); -extern bool type_build_dtor_call (tree); -extern void explain_non_literal_class (tree); -extern void inherit_targ_abi_tags (tree); -extern void defaulted_late_check (tree); -extern bool defaultable_fn_check (tree); -extern void check_abi_tags (tree); -extern void fixup_type_variants (tree); -extern void fixup_attribute_variants (tree); -extern tree* decl_cloned_function_p (const_tree, bool); -extern void clone_function_decl (tree, int); -extern void adjust_clone_args (tree); -extern void deduce_noexcept_on_destructor (tree); -extern void insert_late_enum_def_into_classtype_sorted_fields (tree, tree); -extern bool uniquely_derived_from_p (tree, tree); -extern bool publicly_uniquely_derived_p (tree, tree); -extern tree common_enclosing_class (tree, tree); - -/* in cvt.c */ -extern tree convert_to_reference (tree, tree, int, int, tree, - tsubst_flags_t); -extern tree convert_from_reference (tree); -extern tree force_rvalue (tree, tsubst_flags_t); -extern tree ocp_convert (tree, tree, int, int, - tsubst_flags_t); -extern tree cp_convert (tree, tree, tsubst_flags_t); -extern tree cp_convert_and_check (tree, tree, tsubst_flags_t); -extern tree cp_fold_convert (tree, tree); -extern tree convert_to_void (tree, impl_conv_void, - tsubst_flags_t); -extern tree convert_force (tree, tree, int, - tsubst_flags_t); -extern tree build_expr_type_conversion (int, tree, bool); -extern tree type_promotes_to (tree); -extern tree perform_qualification_conversions (tree, tree); - -/* in name-lookup.c */ -extern tree pushdecl (tree); -extern tree pushdecl_maybe_friend (tree, bool); -extern void maybe_push_cleanup_level (tree); -extern tree pushtag (tree, tree, tag_scope); -extern tree make_anon_name (void); -extern tree pushdecl_top_level_maybe_friend (tree, bool); -extern tree pushdecl_top_level_and_finish (tree, tree); -extern tree check_for_out_of_scope_variable (tree); -extern void dump (cp_binding_level &ref); -extern void dump (cp_binding_level *ptr); -extern void print_other_binding_stack (cp_binding_level *); -extern tree maybe_push_decl (tree); -extern tree current_decl_namespace (void); - -/* decl.c */ -extern tree poplevel (int, int, int); -extern void cxx_init_decl_processing (void); -enum cp_tree_node_structure_enum cp_tree_node_structure - (union lang_tree_node *); -extern void finish_scope (void); -extern void push_switch (tree); -extern void pop_switch (void); -extern tree make_lambda_name (void); -extern int decls_match (tree, tree); -extern tree duplicate_decls (tree, tree, bool); -extern tree declare_local_label (tree); -extern tree define_label (location_t, tree); -extern void check_goto (tree); -extern bool check_omp_return (void); -extern tree make_typename_type (tree, tree, enum tag_types, tsubst_flags_t); -extern tree make_unbound_class_template (tree, tree, tree, tsubst_flags_t); -extern tree build_library_fn_ptr (const char *, tree, int); -extern tree build_cp_library_fn_ptr (const char *, tree, int); -extern tree push_library_fn (tree, tree, tree, int); -extern tree push_void_library_fn (tree, tree, int); -extern tree push_throw_library_fn (tree, tree); -extern void warn_misplaced_attr_for_class_type (source_location location, - tree class_type); -extern tree check_tag_decl (cp_decl_specifier_seq *, bool); -extern tree shadow_tag (cp_decl_specifier_seq *); -extern tree groktypename (cp_decl_specifier_seq *, const cp_declarator *, bool); -extern tree start_decl (const cp_declarator *, cp_decl_specifier_seq *, int, tree, tree, tree *); -extern void start_decl_1 (tree, bool); -extern bool check_array_initializer (tree, tree, tree); -extern void cp_finish_decl (tree, tree, bool, tree, int); -extern int cp_complete_array_type (tree *, tree, bool); -extern int cp_complete_array_type_or_error (tree *, tree, bool, tsubst_flags_t); -extern tree build_ptrmemfunc_type (tree); -extern tree build_ptrmem_type (tree, tree); -/* the grokdeclarator prototype is in decl.h */ -extern tree build_this_parm (tree, cp_cv_quals); -extern int copy_fn_p (const_tree); -extern bool move_fn_p (const_tree); -extern bool move_signature_fn_p (const_tree); -extern tree get_scope_of_declarator (const cp_declarator *); -extern void grok_special_member_properties (tree); -extern int grok_ctor_properties (const_tree, const_tree); -extern bool grok_op_properties (tree, bool); -extern tree xref_tag (enum tag_types, tree, tag_scope, bool); -extern tree xref_tag_from_type (tree, tree, tag_scope); -extern bool xref_basetypes (tree, tree); -extern tree start_enum (tree, tree, tree, bool, bool *); -extern void finish_enum_value_list (tree); -extern void finish_enum (tree); -extern void build_enumerator (tree, tree, tree, location_t); -extern tree lookup_enumerator (tree, tree); -extern bool start_preparsed_function (tree, tree, int); -extern bool start_function (cp_decl_specifier_seq *, - const cp_declarator *, tree); -extern tree begin_function_body (void); -extern void finish_function_body (tree); -extern tree outer_curly_brace_block (tree); -extern tree finish_function (int); -extern tree grokmethod (cp_decl_specifier_seq *, const cp_declarator *, tree); -extern void maybe_register_incomplete_var (tree); -extern void maybe_commonize_var (tree); -extern void complete_vars (tree); -extern tree static_fn_type (tree); -extern void revert_static_member_fn (tree); -extern void fixup_anonymous_aggr (tree); -extern tree compute_array_index_type (tree, tree, tsubst_flags_t); -extern tree check_default_argument (tree, tree, tsubst_flags_t); -typedef int (*walk_namespaces_fn) (tree, void *); -extern int walk_namespaces (walk_namespaces_fn, - void *); -extern int wrapup_globals_for_namespace (tree, void *); -extern tree create_implicit_typedef (tree, tree); -extern int local_variable_p (const_tree); -extern tree register_dtor_fn (tree); -extern tmpl_spec_kind current_tmpl_spec_kind (int); -extern tree cp_fname_init (const char *, tree *); -extern tree cxx_builtin_function (tree decl); -extern tree cxx_builtin_function_ext_scope (tree decl); -extern tree check_elaborated_type_specifier (enum tag_types, tree, bool); -extern void warn_extern_redeclared_static (tree, tree); -extern tree cxx_comdat_group (tree); -extern bool cp_missing_noreturn_ok_p (tree); -extern void initialize_artificial_var (tree, vec *); -extern tree check_var_type (tree, tree); -extern tree reshape_init (tree, tree, tsubst_flags_t); -extern tree next_initializable_field (tree); -extern tree fndecl_declared_return_type (tree); -extern bool undeduced_auto_decl (tree); -extern void require_deduced_type (tree); - -extern bool defer_mark_used_calls; -extern GTY(()) vec *deferred_mark_used_calls; -extern tree finish_case_label (location_t, tree, tree); -extern tree cxx_maybe_build_cleanup (tree, tsubst_flags_t); - -/* in decl2.c */ -extern void note_mangling_alias (tree, tree); -extern void generate_mangling_aliases (void); -extern bool check_java_method (tree); -extern tree build_memfn_type (tree, tree, cp_cv_quals, cp_ref_qualifier); -extern tree build_pointer_ptrmemfn_type (tree); -extern tree change_return_type (tree, tree); -extern void maybe_retrofit_in_chrg (tree); -extern void maybe_make_one_only (tree); -extern bool vague_linkage_p (tree); -extern void grokclassfn (tree, tree, - enum overload_flags); -extern tree grok_array_decl (location_t, tree, tree, bool); -extern tree delete_sanity (tree, tree, bool, int, tsubst_flags_t); -extern tree check_classfn (tree, tree, tree); -extern void check_member_template (tree); -extern tree grokfield (const cp_declarator *, cp_decl_specifier_seq *, - tree, bool, tree, tree); -extern tree grokbitfield (const cp_declarator *, cp_decl_specifier_seq *, - tree, tree); -extern tree cp_reconstruct_complex_type (tree, tree); -extern bool attributes_naming_typedef_ok (tree); -extern void cplus_decl_attributes (tree *, tree, int); -extern void finish_anon_union (tree); -extern void cp_write_global_declarations (void); -extern tree coerce_new_type (tree); -extern tree coerce_delete_type (tree); -extern void comdat_linkage (tree); -extern void determine_visibility (tree); -extern void constrain_class_visibility (tree); -extern void reset_type_linkage (tree); -extern void tentative_decl_linkage (tree); -extern void import_export_decl (tree); -extern tree build_cleanup (tree); -extern tree build_offset_ref_call_from_tree (tree, vec **, - tsubst_flags_t); -extern bool decl_constant_var_p (tree); -extern bool decl_maybe_constant_var_p (tree); -extern void no_linkage_error (tree); -extern void check_default_args (tree); -extern bool mark_used (tree); -extern bool mark_used (tree, tsubst_flags_t); -extern void finish_static_data_member_decl (tree, tree, bool, tree, int); -extern tree cp_build_parm_decl (tree, tree); -extern tree get_guard (tree); -extern tree get_guard_cond (tree); -extern tree set_guard (tree); -extern tree get_tls_wrapper_fn (tree); -extern void mark_needed (tree); -extern bool decl_needed_p (tree); -extern void note_vague_linkage_fn (tree); -extern void note_variable_template_instantiation (tree); -extern tree build_artificial_parm (tree, tree); -extern bool possibly_inlined_p (tree); -extern int parm_index (tree); -extern tree vtv_start_verification_constructor_init_function (void); -extern tree vtv_finish_verification_constructor_init_function (tree); -extern bool cp_omp_mappable_type (tree); - -/* in error.c */ -extern void init_error (void); -extern const char *type_as_string (tree, int); -extern const char *type_as_string_translate (tree, int); -extern const char *decl_as_string (tree, int); -extern const char *decl_as_string_translate (tree, int); -extern const char *decl_as_dwarf_string (tree, int); -extern const char *expr_as_string (tree, int); -extern const char *lang_decl_name (tree, int, bool); -extern const char *lang_decl_dwarf_name (tree, int, bool); -extern const char *language_to_string (enum languages); -extern const char *class_key_or_enum_as_string (tree); -extern void maybe_warn_variadic_templates (void); -extern void maybe_warn_cpp0x (cpp0x_warn_str str); -extern bool pedwarn_cxx98 (location_t, int, const char *, ...) ATTRIBUTE_GCC_DIAG(3,4); -extern location_t location_of (tree); -extern void qualified_name_lookup_error (tree, tree, tree, - location_t); - -/* in except.c */ -extern void init_exception_processing (void); -extern tree expand_start_catch_block (tree); -extern void expand_end_catch_block (void); -extern tree build_exc_ptr (void); -extern tree build_throw (tree); -extern int nothrow_libfn_p (const_tree); -extern void check_handlers (tree); -extern tree finish_noexcept_expr (tree, tsubst_flags_t); -extern bool expr_noexcept_p (tree, tsubst_flags_t); -extern void perform_deferred_noexcept_checks (void); -extern bool nothrow_spec_p (const_tree); -extern bool type_noexcept_p (const_tree); -extern bool type_throw_all_p (const_tree); -extern tree build_noexcept_spec (tree, int); -extern void choose_personality_routine (enum languages); -extern tree build_must_not_throw_expr (tree,tree); -extern tree eh_type_info (tree); -extern tree begin_eh_spec_block (void); -extern void finish_eh_spec_block (tree, tree); -extern tree build_eh_type_type (tree); -extern tree cp_protect_cleanup_actions (void); -extern tree create_try_catch_expr (tree, tree); - -/* in expr.c */ -extern tree cplus_expand_constant (tree); -extern tree mark_rvalue_use (tree); -extern tree mark_lvalue_use (tree); -extern tree mark_type_use (tree); -extern void mark_exp_read (tree); - -/* friend.c */ -extern int is_friend (tree, tree); -extern void make_friend_class (tree, tree, bool); -extern void add_friend (tree, tree, bool); -extern tree do_friend (tree, tree, tree, tree, enum overload_flags, bool); - -/* in init.c */ -extern tree expand_member_init (tree); -extern void emit_mem_initializers (tree); -extern tree build_aggr_init (tree, tree, int, - tsubst_flags_t); -extern int is_class_type (tree, int); -extern tree get_type_value (tree); -extern tree build_zero_init (tree, tree, bool); -extern tree build_value_init (tree, tsubst_flags_t); -extern tree build_value_init_noctor (tree, tsubst_flags_t); -extern tree get_nsdmi (tree, bool); -extern tree build_offset_ref (tree, tree, bool, - tsubst_flags_t); -extern tree throw_bad_array_new_length (void); -extern tree build_new (vec **, tree, tree, - vec **, int, - tsubst_flags_t); -extern tree get_temp_regvar (tree, tree); -extern tree build_vec_init (tree, tree, tree, bool, int, - tsubst_flags_t); -extern tree build_delete (tree, tree, - special_function_kind, - int, int, tsubst_flags_t); -extern void push_base_cleanups (void); -extern tree build_vec_delete (tree, tree, - special_function_kind, int, - tsubst_flags_t); -extern tree create_temporary_var (tree); -extern void initialize_vtbl_ptrs (tree); -extern tree build_java_class_ref (tree); -extern tree scalar_constant_value (tree); -extern tree decl_really_constant_value (tree); -extern int diagnose_uninitialized_cst_or_ref_member (tree, bool, bool); -extern tree build_vtbl_address (tree); - -/* in lex.c */ -extern void cxx_dup_lang_specific_decl (tree); -extern void yyungetc (int, int); - -extern tree unqualified_name_lookup_error (tree); -extern tree unqualified_fn_lookup_error (tree); -extern tree build_lang_decl (enum tree_code, tree, tree); -extern tree build_lang_decl_loc (location_t, enum tree_code, tree, tree); -extern void retrofit_lang_decl (tree); -extern tree copy_decl (tree); -extern tree copy_type (tree); -extern tree cxx_make_type (enum tree_code); -extern tree make_class_type (enum tree_code); -extern bool cxx_init (void); -extern void cxx_finish (void); -extern bool in_main_input_context (void); - -/* in method.c */ -extern void init_method (void); -extern tree make_thunk (tree, bool, tree, tree); -extern void finish_thunk (tree); -extern void use_thunk (tree, bool); -extern bool trivial_fn_p (tree); -extern bool is_trivially_xible (enum tree_code, tree, tree); -extern tree get_defaulted_eh_spec (tree); -extern tree unevaluated_noexcept_spec (void); -extern void after_nsdmi_defaulted_late_checks (tree); -extern bool maybe_explain_implicit_delete (tree); -extern void explain_implicit_non_constexpr (tree); -extern void deduce_inheriting_ctor (tree); -extern void synthesize_method (tree); -extern tree lazily_declare_fn (special_function_kind, - tree); -extern tree skip_artificial_parms_for (const_tree, tree); -extern int num_artificial_parms_for (const_tree); -extern tree make_alias_for (tree, tree); -extern tree get_copy_ctor (tree, tsubst_flags_t); -extern tree get_copy_assign (tree); -extern tree get_default_ctor (tree); -extern tree get_dtor (tree, tsubst_flags_t); -extern tree get_inherited_ctor (tree); -extern tree locate_ctor (tree); -extern tree implicitly_declare_fn (special_function_kind, tree, - bool, tree, tree); - -/* In optimize.c */ -extern bool maybe_clone_body (tree); - -/* In parser.c */ -extern tree cp_convert_range_for (tree, tree, tree, bool); -extern bool parsing_nsdmi (void); -extern void inject_this_parameter (tree, cp_cv_quals); - -/* in pt.c */ -extern bool check_template_shadow (tree); -extern tree get_innermost_template_args (tree, int); -extern void maybe_begin_member_template_processing (tree); -extern void maybe_end_member_template_processing (void); -extern tree finish_member_template_decl (tree); -extern void begin_template_parm_list (void); -extern bool begin_specialization (void); -extern void reset_specialization (void); -extern void end_specialization (void); -extern void begin_explicit_instantiation (void); -extern void end_explicit_instantiation (void); -extern tree check_explicit_specialization (tree, tree, int, int); -extern int num_template_headers_for_class (tree); -extern void check_template_variable (tree); -extern tree make_auto (void); -extern tree make_decltype_auto (void); -extern tree do_auto_deduction (tree, tree, tree); -extern tree type_uses_auto (tree); -extern tree type_uses_auto_or_concept (tree); -extern void append_type_to_template_for_access_check (tree, tree, tree, - location_t); -extern tree convert_generic_types_to_packs (tree, int, int); -extern tree splice_late_return_type (tree, tree); -extern bool is_auto (const_tree); -extern bool is_auto_or_concept (const_tree); -extern tree process_template_parm (tree, location_t, tree, - bool, bool); -extern tree end_template_parm_list (tree); -extern void end_template_decl (void); -extern tree maybe_update_decl_type (tree, tree); -extern bool check_default_tmpl_args (tree, tree, bool, bool, int); -extern tree push_template_decl (tree); -extern tree push_template_decl_real (tree, bool); -extern tree add_inherited_template_parms (tree, tree); -extern bool redeclare_class_template (tree, tree); -extern tree lookup_template_class (tree, tree, tree, tree, - int, tsubst_flags_t); -extern tree lookup_template_function (tree, tree); -extern tree lookup_template_variable (tree, tree); -extern int uses_template_parms (tree); -extern int uses_template_parms_level (tree, int); -extern bool in_template_function (void); -extern tree instantiate_class_template (tree); -extern tree instantiate_template (tree, tree, tsubst_flags_t); -extern tree fn_type_unification (tree, tree, tree, - const tree *, unsigned int, - tree, unification_kind_t, int, - bool, bool); -extern void mark_decl_instantiated (tree, int); -extern int more_specialized_fn (tree, tree, int); -extern void do_decl_instantiation (tree, tree); -extern void do_type_instantiation (tree, tree, tsubst_flags_t); -extern bool always_instantiate_p (tree); -extern void maybe_instantiate_noexcept (tree); -extern tree instantiate_decl (tree, int, bool); -extern int comp_template_parms (const_tree, const_tree); -extern bool uses_parameter_packs (tree); -extern bool template_parameter_pack_p (const_tree); -extern bool function_parameter_pack_p (const_tree); -extern bool function_parameter_expanded_from_pack_p (tree, tree); -extern tree make_pack_expansion (tree); -extern bool check_for_bare_parameter_packs (tree); -extern tree build_template_info (tree, tree); -extern tree get_template_info (const_tree); -extern vec *get_types_needing_access_check (tree); -extern int template_class_depth (tree); -extern int is_specialization_of (tree, tree); -extern bool is_specialization_of_friend (tree, tree); -extern tree get_pattern_parm (tree, tree); -extern int comp_template_args (tree, tree); -extern tree maybe_process_partial_specialization (tree); -extern tree most_specialized_instantiation (tree); -extern void print_candidates (tree); -extern void instantiate_pending_templates (int); -extern tree tsubst_default_argument (tree, tree, tree, - tsubst_flags_t); -extern tree tsubst (tree, tree, tsubst_flags_t, tree); -extern tree tsubst_copy_and_build (tree, tree, tsubst_flags_t, - tree, bool, bool); -extern tree most_general_template (tree); -extern tree get_mostly_instantiated_function_type (tree); -extern bool problematic_instantiation_changed (void); -extern void record_last_problematic_instantiation (void); -extern struct tinst_level *current_instantiation(void); -extern bool instantiating_current_function_p (void); -extern tree maybe_get_template_decl_from_type_decl (tree); -extern int processing_template_parmlist; -extern bool dependent_type_p (tree); -extern bool dependent_scope_p (tree); -extern bool any_dependent_template_arguments_p (const_tree); -extern bool dependent_template_p (tree); -extern bool dependent_template_id_p (tree, tree); -extern bool type_dependent_expression_p (tree); -extern bool any_type_dependent_arguments_p (const vec *); -extern bool any_type_dependent_elements_p (const_tree); -extern bool type_dependent_expression_p_push (tree); -extern bool value_dependent_expression_p (tree); -extern bool instantiation_dependent_expression_p (tree); -extern bool any_value_dependent_elements_p (const_tree); -extern bool dependent_omp_for_p (tree, tree, tree, tree); -extern tree resolve_typename_type (tree, bool); -extern tree template_for_substitution (tree); -extern tree build_non_dependent_expr (tree); -extern void make_args_non_dependent (vec *); -extern bool reregister_specialization (tree, tree, tree); -extern tree instantiate_non_dependent_expr (tree); -extern tree instantiate_non_dependent_expr_sfinae (tree, tsubst_flags_t); -extern tree instantiate_non_dependent_expr_internal (tree, tsubst_flags_t); -extern bool variable_template_specialization_p (tree); -extern bool alias_type_or_template_p (tree); -extern bool alias_template_specialization_p (const_tree); -extern bool dependent_alias_template_spec_p (const_tree); -extern bool explicit_class_specialization_p (tree); -extern bool push_tinst_level (tree); -extern bool push_tinst_level_loc (tree, location_t); -extern void pop_tinst_level (void); -extern struct tinst_level *outermost_tinst_level(void); -extern void init_template_processing (void); -extern void print_template_statistics (void); -bool template_template_parameter_p (const_tree); -bool template_type_parameter_p (const_tree); -extern bool primary_template_instantiation_p (const_tree); -extern tree get_primary_template_innermost_parameters (const_tree); -extern tree get_template_parms_at_level (tree, int); -extern tree get_template_innermost_arguments (const_tree); -extern tree get_template_argument_pack_elems (const_tree); -extern tree get_function_template_decl (const_tree); -extern tree resolve_nondeduced_context (tree, tsubst_flags_t); -extern hashval_t iterative_hash_template_arg (tree arg, hashval_t val); - -/* in repo.c */ -extern void init_repo (void); -extern int repo_emit_p (tree); -extern bool repo_export_class_p (const_tree); -extern void finish_repo (void); - -/* in rtti.c */ -/* A vector of all tinfo decls that haven't been emitted yet. */ -extern GTY(()) vec *unemitted_tinfo_decls; - -extern void init_rtti_processing (void); -extern tree build_typeid (tree, tsubst_flags_t); -extern tree get_tinfo_decl (tree); -extern tree get_typeid (tree, tsubst_flags_t); -extern tree build_headof (tree); -extern tree build_dynamic_cast (tree, tree, tsubst_flags_t); -extern void emit_support_tinfos (void); -extern bool emit_tinfo_decl (tree); - -/* in search.c */ -extern bool accessible_base_p (tree, tree, bool); -extern tree lookup_base (tree, tree, base_access, - base_kind *, tsubst_flags_t); -extern tree dcast_base_hint (tree, tree); -extern int accessible_p (tree, tree, bool); -extern int accessible_in_template_p (tree, tree); -extern tree lookup_field_1 (tree, tree, bool); -extern tree lookup_field (tree, tree, int, bool); -extern int lookup_fnfields_1 (tree, tree); -extern tree lookup_fnfields_slot (tree, tree); -extern tree lookup_fnfields_slot_nolazy (tree, tree); -extern int class_method_index_for_fn (tree, tree); -extern tree lookup_fnfields (tree, tree, int); -extern tree lookup_member (tree, tree, int, bool, - tsubst_flags_t); -extern int look_for_overrides (tree, tree); -extern void get_pure_virtuals (tree); -extern void maybe_suppress_debug_info (tree); -extern void note_debug_info_needed (tree); -extern void print_search_statistics (void); -extern void reinit_search_statistics (void); -extern tree current_scope (void); -extern int at_function_scope_p (void); -extern bool at_class_scope_p (void); -extern bool at_namespace_scope_p (void); -extern tree context_for_name_lookup (tree); -extern tree lookup_conversions (tree); -extern tree binfo_from_vbase (tree); -extern tree binfo_for_vbase (tree, tree); -extern tree look_for_overrides_here (tree, tree); -#define dfs_skip_bases ((tree)1) -extern tree dfs_walk_all (tree, tree (*) (tree, void *), - tree (*) (tree, void *), void *); -extern tree dfs_walk_once (tree, tree (*) (tree, void *), - tree (*) (tree, void *), void *); -extern tree binfo_via_virtual (tree, tree); -extern tree build_baselink (tree, tree, tree, tree); -extern tree adjust_result_of_qualified_name_lookup - (tree, tree, tree); -extern tree copied_binfo (tree, tree); -extern tree original_binfo (tree, tree); -extern int shared_member_p (tree); - -/* The representation of a deferred access check. */ - -typedef struct GTY(()) deferred_access_check { - /* The base class in which the declaration is referenced. */ - tree binfo; - /* The declaration whose access must be checked. */ - tree decl; - /* The declaration that should be used in the error message. */ - tree diag_decl; - /* The location of this access. */ - location_t loc; -} deferred_access_check; - -/* in semantics.c */ -extern void push_deferring_access_checks (deferring_kind); -extern void resume_deferring_access_checks (void); -extern void stop_deferring_access_checks (void); -extern void pop_deferring_access_checks (void); -extern vec *get_deferred_access_checks (void); -extern void reopen_deferring_access_checks (vec *); -extern void pop_to_parent_deferring_access_checks (void); -extern bool perform_access_checks (vec *, - tsubst_flags_t); -extern bool perform_deferred_access_checks (tsubst_flags_t); -extern bool perform_or_defer_access_check (tree, tree, tree, - tsubst_flags_t); -extern int stmts_are_full_exprs_p (void); -extern void init_cp_semantics (void); -extern tree do_poplevel (tree); -extern void break_maybe_infinite_loop (void); -extern void add_decl_expr (tree); -extern tree maybe_cleanup_point_expr_void (tree); -extern tree finish_expr_stmt (tree); -extern tree begin_if_stmt (void); -extern void finish_if_stmt_cond (tree, tree); -extern tree finish_then_clause (tree); -extern void begin_else_clause (tree); -extern void finish_else_clause (tree); -extern void finish_if_stmt (tree); -extern tree begin_while_stmt (void); -extern void finish_while_stmt_cond (tree, tree, bool); -extern void finish_while_stmt (tree); -extern tree begin_do_stmt (void); -extern void finish_do_body (tree); -extern void finish_do_stmt (tree, tree, bool); -extern tree finish_return_stmt (tree); -extern tree begin_for_scope (tree *); -extern tree begin_for_stmt (tree, tree); -extern void finish_for_init_stmt (tree); -extern void finish_for_cond (tree, tree, bool); -extern void finish_for_expr (tree, tree); -extern void finish_for_stmt (tree); -extern tree begin_range_for_stmt (tree, tree); -extern void finish_range_for_decl (tree, tree, tree); -extern void finish_range_for_stmt (tree); -extern tree finish_break_stmt (void); -extern tree finish_continue_stmt (void); -extern tree begin_switch_stmt (void); -extern void finish_switch_cond (tree, tree); -extern void finish_switch_stmt (tree); -extern tree finish_goto_stmt (tree); -extern tree begin_try_block (void); -extern void finish_try_block (tree); -extern void finish_handler_sequence (tree); -extern tree begin_function_try_block (tree *); -extern void finish_function_try_block (tree); -extern void finish_function_handler_sequence (tree, tree); -extern void finish_cleanup_try_block (tree); -extern tree begin_handler (void); -extern void finish_handler_parms (tree, tree); -extern void finish_handler (tree); -extern void finish_cleanup (tree, tree); -extern bool is_this_parameter (tree); - -enum { - BCS_NO_SCOPE = 1, - BCS_TRY_BLOCK = 2, - BCS_FN_BODY = 4 -}; -extern tree begin_compound_stmt (unsigned int); - -extern void finish_compound_stmt (tree); -extern tree finish_asm_stmt (int, tree, tree, tree, tree, - tree); -extern tree finish_label_stmt (tree); -extern void finish_label_decl (tree); -extern tree finish_parenthesized_expr (tree); -extern tree force_paren_expr (tree); -extern tree finish_non_static_data_member (tree, tree, tree); -extern tree begin_stmt_expr (void); -extern tree finish_stmt_expr_expr (tree, tree); -extern tree finish_stmt_expr (tree, bool); -extern tree stmt_expr_value_expr (tree); -bool empty_expr_stmt_p (tree); -extern tree perform_koenig_lookup (tree, vec *, - tsubst_flags_t); -extern tree finish_call_expr (tree, vec **, bool, - bool, tsubst_flags_t); -extern tree finish_template_variable (tree, tsubst_flags_t = tf_warning_or_error); -extern tree finish_increment_expr (tree, enum tree_code); -extern tree finish_this_expr (void); -extern tree finish_pseudo_destructor_expr (tree, tree, tree, location_t); -extern tree finish_unary_op_expr (location_t, enum tree_code, tree, - tsubst_flags_t); -extern tree finish_compound_literal (tree, tree, tsubst_flags_t); -extern tree finish_fname (tree); -extern void finish_translation_unit (void); -extern tree finish_template_type_parm (tree, tree); -extern tree finish_template_template_parm (tree, tree); -extern tree begin_class_definition (tree); -extern void finish_template_decl (tree); -extern tree finish_template_type (tree, tree, int); -extern tree finish_base_specifier (tree, tree, bool); -extern void finish_member_declaration (tree); -extern bool outer_automatic_var_p (tree); -extern tree process_outer_var_ref (tree, tsubst_flags_t); -extern tree finish_id_expression (tree, tree, tree, - cp_id_kind *, - bool, bool, bool *, - bool, bool, bool, bool, - const char **, - location_t); -extern tree finish_typeof (tree); -extern tree finish_underlying_type (tree); -extern tree calculate_bases (tree); -extern tree finish_bases (tree, bool); -extern tree calculate_direct_bases (tree); -extern tree finish_offsetof (tree, location_t); -extern void finish_decl_cleanup (tree, tree); -extern void finish_eh_cleanup (tree); -extern void emit_associated_thunks (tree); -extern void finish_mem_initializers (tree); -extern tree check_template_template_default_arg (tree); -extern bool expand_or_defer_fn_1 (tree); -extern void expand_or_defer_fn (tree); -extern void add_typedef_to_current_template_for_access_check (tree, tree, - location_t); -extern void check_accessibility_of_qualified_id (tree, tree, tree); -extern tree finish_qualified_id_expr (tree, tree, bool, bool, - bool, bool, tsubst_flags_t); -extern void simplify_aggr_init_expr (tree *); -extern void finalize_nrv (tree *, tree, tree); -extern void note_decl_for_pch (tree); -extern tree omp_reduction_id (enum tree_code, tree, tree); -extern tree cp_remove_omp_priv_cleanup_stmt (tree *, int *, void *); -extern void cp_check_omp_declare_reduction (tree); -extern tree finish_omp_clauses (tree); -extern void finish_omp_threadprivate (tree); -extern tree begin_omp_structured_block (void); -extern tree finish_omp_structured_block (tree); -extern tree finish_oacc_data (tree, tree); -extern tree finish_oacc_kernels (tree, tree); -extern tree finish_oacc_parallel (tree, tree); -extern tree begin_omp_parallel (void); -extern tree finish_omp_parallel (tree, tree); -extern tree begin_omp_task (void); -extern tree finish_omp_task (tree, tree); -extern tree finish_omp_for (location_t, enum tree_code, - tree, tree, tree, tree, tree, - tree, tree); -extern void finish_omp_atomic (enum tree_code, enum tree_code, - tree, tree, tree, tree, tree, - bool); -extern void finish_omp_barrier (void); -extern void finish_omp_flush (void); -extern void finish_omp_taskwait (void); -extern void finish_omp_taskyield (void); -extern void finish_omp_cancel (tree); -extern void finish_omp_cancellation_point (tree); -extern tree begin_transaction_stmt (location_t, tree *, int); -extern void finish_transaction_stmt (tree, tree, int, tree); -extern tree build_transaction_expr (location_t, tree, int, tree); -extern bool cxx_omp_create_clause_info (tree, tree, bool, bool, - bool, bool); -extern tree baselink_for_fns (tree); -extern void finish_static_assert (tree, tree, location_t, - bool); -extern tree finish_decltype_type (tree, bool, tsubst_flags_t); -extern tree finish_trait_expr (enum cp_trait_kind, tree, tree); -extern tree build_lambda_expr (void); -extern tree build_lambda_object (tree); -extern tree begin_lambda_type (tree); -extern tree lambda_capture_field_type (tree, bool); -extern tree lambda_return_type (tree); -extern tree lambda_proxy_type (tree); -extern tree lambda_function (tree); -extern void apply_deduced_return_type (tree, tree); -extern tree add_capture (tree, tree, tree, bool, bool); -extern tree add_default_capture (tree, tree, tree); -extern tree build_capture_proxy (tree); -extern void insert_capture_proxy (tree); -extern void insert_pending_capture_proxies (void); -extern bool is_capture_proxy (tree); -extern bool is_normal_capture_proxy (tree); -extern void register_capture_members (tree); -extern tree lambda_expr_this_capture (tree, bool); -extern tree maybe_resolve_dummy (tree, bool); -extern tree current_nonlambda_function (void); -extern tree nonlambda_method_basetype (void); -extern void maybe_add_lambda_conv_op (tree); -extern bool is_lambda_ignored_entity (tree); - -/* in tree.c */ -extern int cp_tree_operand_length (const_tree); -void cp_free_lang_data (tree t); -extern tree force_target_expr (tree, tree, tsubst_flags_t); -extern tree build_target_expr_with_type (tree, tree, tsubst_flags_t); -extern void lang_check_failed (const char *, int, - const char *) ATTRIBUTE_NORETURN; -extern tree stabilize_expr (tree, tree *); -extern void stabilize_call (tree, tree *); -extern bool stabilize_init (tree, tree *); -extern tree add_stmt_to_compound (tree, tree); -extern void init_tree (void); -extern bool pod_type_p (const_tree); -extern bool layout_pod_type_p (const_tree); -extern bool std_layout_type_p (const_tree); -extern bool trivial_type_p (const_tree); -extern bool trivially_copyable_p (const_tree); -extern bool scalarish_type_p (const_tree); -extern bool type_has_nontrivial_default_init (const_tree); -extern bool type_has_nontrivial_copy_init (const_tree); -extern bool class_tmpl_impl_spec_p (const_tree); -extern int zero_init_p (const_tree); -extern bool check_abi_tag_redeclaration (const_tree, const_tree, const_tree); -extern bool check_abi_tag_args (tree, tree); -extern tree strip_typedefs (tree); -extern tree strip_typedefs_expr (tree); -extern tree copy_binfo (tree, tree, tree, - tree *, int); -extern int member_p (const_tree); -extern cp_lvalue_kind real_lvalue_p (const_tree); -extern cp_lvalue_kind lvalue_kind (const_tree); -extern bool lvalue_or_rvalue_with_address_p (const_tree); -extern bool xvalue_p (const_tree); -extern bool builtin_valid_in_constant_expr_p (const_tree); -extern tree build_min (enum tree_code, tree, ...); -extern tree build_min_nt_loc (location_t, enum tree_code, - ...); -extern tree build_min_non_dep (enum tree_code, tree, ...); -extern tree build_min_non_dep_call_vec (tree, tree, vec *); -extern tree build_cplus_new (tree, tree, tsubst_flags_t); -extern tree build_aggr_init_expr (tree, tree); -extern tree get_target_expr (tree); -extern tree get_target_expr_sfinae (tree, tsubst_flags_t); -extern tree build_cplus_array_type (tree, tree); -extern tree build_array_of_n_type (tree, int); -extern bool array_of_runtime_bound_p (tree); -extern tree build_array_copy (tree); -extern tree build_vec_init_expr (tree, tree, tsubst_flags_t); -extern void diagnose_non_constexpr_vec_init (tree); -extern tree hash_tree_cons (tree, tree, tree); -extern tree hash_tree_chain (tree, tree); -extern tree build_qualified_name (tree, tree, tree, bool); -extern tree build_ref_qualified_type (tree, cp_ref_qualifier); -extern int is_overloaded_fn (tree); -extern tree dependent_name (tree); -extern tree get_fns (tree); -extern tree get_first_fn (tree); -extern tree ovl_cons (tree, tree); -extern tree build_overload (tree, tree); -extern tree ovl_scope (tree); -extern bool non_static_member_function_p (tree); -extern const char *cxx_printable_name (tree, int); -extern const char *cxx_printable_name_translate (tree, int); -extern tree build_exception_variant (tree, tree); -extern tree bind_template_template_parm (tree, tree); -extern tree array_type_nelts_total (tree); -extern tree array_type_nelts_top (tree); -extern tree break_out_target_exprs (tree); -extern tree build_ctor_subob_ref (tree, tree, tree); -extern tree replace_placeholders (tree, tree); -extern tree get_type_decl (tree); -extern tree decl_namespace_context (tree); -extern bool decl_anon_ns_mem_p (const_tree); -extern tree lvalue_type (tree); -extern tree error_type (tree); -extern int varargs_function_p (const_tree); -extern bool really_overloaded_fn (tree); -extern bool cp_tree_equal (tree, tree); -extern tree no_linkage_check (tree, bool); -extern void debug_binfo (tree); -extern tree build_dummy_object (tree); -extern tree maybe_dummy_object (tree, tree *); -extern int is_dummy_object (const_tree); -extern const struct attribute_spec cxx_attribute_table[]; -extern tree make_ptrmem_cst (tree, tree); -extern tree cp_build_type_attribute_variant (tree, tree); -extern tree cp_build_reference_type (tree, bool); -extern tree move (tree); -extern tree cp_build_qualified_type_real (tree, int, tsubst_flags_t); -#define cp_build_qualified_type(TYPE, QUALS) \ - cp_build_qualified_type_real ((TYPE), (QUALS), tf_warning_or_error) -extern bool cv_qualified_p (const_tree); -extern tree cv_unqualified (tree); -extern special_function_kind special_function_p (const_tree); -extern int count_trees (tree); -extern int char_type_p (tree); -extern void verify_stmt_tree (tree); -extern linkage_kind decl_linkage (tree); -extern duration_kind decl_storage_duration (tree); -extern tree cp_walk_subtrees (tree*, int*, walk_tree_fn, - void*, hash_set *); -#define cp_walk_tree(tp,func,data,pset) \ - walk_tree_1 (tp, func, data, pset, cp_walk_subtrees) -#define cp_walk_tree_without_duplicates(tp,func,data) \ - walk_tree_without_duplicates_1 (tp, func, data, cp_walk_subtrees) -extern tree fold_if_not_in_template (tree); -extern tree rvalue (tree); -extern tree convert_bitfield_to_declared_type (tree); -extern tree cp_save_expr (tree); -extern bool cast_valid_in_integral_constant_expression_p (tree); -extern bool cxx_type_hash_eq (const_tree, const_tree); - -extern void cxx_print_statistics (void); -extern bool maybe_warn_zero_as_null_pointer_constant (tree, location_t); - -/* in ptree.c */ -extern void cxx_print_xnode (FILE *, tree, int); -extern void cxx_print_decl (FILE *, tree, int); -extern void cxx_print_type (FILE *, tree, int); -extern void cxx_print_identifier (FILE *, tree, int); -extern void cxx_print_error_function (diagnostic_context *, - const char *, - struct diagnostic_info *); - -/* in typeck.c */ -extern bool cxx_mark_addressable (tree); -extern int string_conv_p (const_tree, const_tree, int); -extern tree cp_truthvalue_conversion (tree); -extern tree condition_conversion (tree); -extern tree require_complete_type (tree); -extern tree require_complete_type_sfinae (tree, tsubst_flags_t); -extern tree complete_type (tree); -extern tree complete_type_or_else (tree, tree); -extern tree complete_type_or_maybe_complain (tree, tree, tsubst_flags_t); -extern int type_unknown_p (const_tree); -enum { ce_derived, ce_normal, ce_exact }; -extern bool comp_except_specs (const_tree, const_tree, int); -extern bool comptypes (tree, tree, int); -extern bool same_type_ignoring_top_level_qualifiers_p (tree, tree); -extern bool compparms (const_tree, const_tree); -extern int comp_cv_qualification (const_tree, const_tree); -extern int comp_cv_qualification (int, int); -extern int comp_cv_qual_signature (tree, tree); -extern tree cxx_sizeof_or_alignof_expr (tree, enum tree_code, bool); -extern tree cxx_sizeof_or_alignof_type (tree, enum tree_code, bool); -extern tree cxx_alignas_expr (tree); -extern tree cxx_sizeof_nowarn (tree); -extern tree is_bitfield_expr_with_lowered_type (const_tree); -extern tree unlowered_expr_type (const_tree); -extern tree decay_conversion (tree, tsubst_flags_t); -extern tree build_class_member_access_expr (tree, tree, tree, bool, - tsubst_flags_t); -extern tree finish_class_member_access_expr (tree, tree, bool, - tsubst_flags_t); -extern tree build_x_indirect_ref (location_t, tree, - ref_operator, tsubst_flags_t); -extern tree cp_build_indirect_ref (tree, ref_operator, - tsubst_flags_t); -extern tree build_array_ref (location_t, tree, tree); -extern tree cp_build_array_ref (location_t, tree, tree, - tsubst_flags_t); -extern tree get_member_function_from_ptrfunc (tree *, tree, tsubst_flags_t); -extern tree cp_build_function_call_nary (tree, tsubst_flags_t, ...) - ATTRIBUTE_SENTINEL; -extern tree cp_build_function_call_vec (tree, vec **, - tsubst_flags_t); -extern tree build_x_binary_op (location_t, - enum tree_code, tree, - enum tree_code, tree, - enum tree_code, tree *, - tsubst_flags_t); -extern tree build_x_array_ref (location_t, tree, tree, - tsubst_flags_t); -extern tree build_x_unary_op (location_t, - enum tree_code, tree, - tsubst_flags_t); -extern tree cp_build_addr_expr (tree, tsubst_flags_t); -extern tree cp_build_unary_op (enum tree_code, tree, int, - tsubst_flags_t); -extern tree unary_complex_lvalue (enum tree_code, tree); -extern tree build_x_conditional_expr (location_t, tree, tree, tree, - tsubst_flags_t); -extern tree build_x_compound_expr_from_list (tree, expr_list_kind, - tsubst_flags_t); -extern tree build_x_compound_expr_from_vec (vec *, - const char *, tsubst_flags_t); -extern tree build_x_compound_expr (location_t, tree, tree, - tsubst_flags_t); -extern tree build_compound_expr (location_t, tree, tree); -extern tree cp_build_compound_expr (tree, tree, tsubst_flags_t); -extern tree build_static_cast (tree, tree, tsubst_flags_t); -extern tree build_reinterpret_cast (tree, tree, tsubst_flags_t); -extern tree build_const_cast (tree, tree, tsubst_flags_t); -extern tree build_c_cast (location_t, tree, tree); -extern tree cp_build_c_cast (tree, tree, tsubst_flags_t); -extern tree build_x_modify_expr (location_t, tree, - enum tree_code, tree, - tsubst_flags_t); -extern tree cp_build_modify_expr (tree, enum tree_code, tree, - tsubst_flags_t); -extern tree convert_for_initialization (tree, tree, tree, int, - impl_conv_rhs, tree, int, - tsubst_flags_t); -extern int comp_ptr_ttypes (tree, tree); -extern bool comp_ptr_ttypes_const (tree, tree); -extern bool error_type_p (const_tree); -extern bool ptr_reasonably_similar (const_tree, const_tree); -extern tree build_ptrmemfunc (tree, tree, int, bool, - tsubst_flags_t); -extern int cp_type_quals (const_tree); -extern int type_memfn_quals (const_tree); -extern cp_ref_qualifier type_memfn_rqual (const_tree); -extern tree apply_memfn_quals (tree, cp_cv_quals, cp_ref_qualifier); -extern bool cp_has_mutable_p (const_tree); -extern bool at_least_as_qualified_p (const_tree, const_tree); -extern void cp_apply_type_quals_to_decl (int, tree); -extern tree build_ptrmemfunc1 (tree, tree, tree); -extern void expand_ptrmemfunc_cst (tree, tree *, tree *); -extern tree type_after_usual_arithmetic_conversions (tree, tree); -extern tree common_pointer_type (tree, tree); -extern tree composite_pointer_type (tree, tree, tree, tree, - composite_pointer_operation, - tsubst_flags_t); -extern tree merge_types (tree, tree); -extern tree strip_array_domain (tree); -extern tree check_return_expr (tree, bool *); -extern tree cp_build_binary_op (location_t, - enum tree_code, tree, tree, - tsubst_flags_t); -extern tree build_x_vec_perm_expr (location_t, - tree, tree, tree, - tsubst_flags_t); -#define cxx_sizeof(T) cxx_sizeof_or_alignof_type (T, SIZEOF_EXPR, true) -extern tree build_simple_component_ref (tree, tree); -extern tree build_ptrmemfunc_access_expr (tree, tree); -extern tree build_address (tree); -extern tree build_nop (tree, tree); -extern tree non_reference (tree); -extern tree lookup_anon_field (tree, tree); -extern bool invalid_nonstatic_memfn_p (tree, tsubst_flags_t); -extern tree convert_member_func_to_ptr (tree, tree, tsubst_flags_t); -extern tree convert_ptrmem (tree, tree, bool, bool, - tsubst_flags_t); -extern int lvalue_or_else (tree, enum lvalue_use, - tsubst_flags_t); -extern void check_template_keyword (tree); -extern bool check_raw_literal_operator (const_tree decl); -extern bool check_literal_operator_args (const_tree, bool *, bool *); -extern void maybe_warn_about_useless_cast (tree, tree, tsubst_flags_t); -extern tree cp_perform_integral_promotions (tree, tsubst_flags_t); - -/* in typeck2.c */ -extern void require_complete_eh_spec_types (tree, tree); -extern void cxx_incomplete_type_diagnostic (const_tree, const_tree, diagnostic_t); -#undef cxx_incomplete_type_error -extern void cxx_incomplete_type_error (const_tree, const_tree); -#define cxx_incomplete_type_error(V,T) \ - (cxx_incomplete_type_diagnostic ((V), (T), DK_ERROR)) -extern void cxx_incomplete_type_inform (const_tree); -extern tree error_not_base_type (tree, tree); -extern tree binfo_or_else (tree, tree); -extern void cxx_readonly_error (tree, enum lvalue_use); -extern void complete_type_check_abstract (tree); -extern int abstract_virtuals_error (tree, tree); -extern int abstract_virtuals_error (abstract_class_use, tree); -extern int abstract_virtuals_error_sfinae (tree, tree, tsubst_flags_t); -extern int abstract_virtuals_error_sfinae (abstract_class_use, tree, tsubst_flags_t); - -extern tree store_init_value (tree, tree, vec**, int); -extern tree split_nonconstant_init (tree, tree); -extern bool check_narrowing (tree, tree, tsubst_flags_t); -extern tree digest_init (tree, tree, tsubst_flags_t); -extern tree digest_init_flags (tree, tree, int); -extern tree digest_nsdmi_init (tree, tree); -extern tree build_scoped_ref (tree, tree, tree *); -extern tree build_x_arrow (location_t, tree, - tsubst_flags_t); -extern tree build_m_component_ref (tree, tree, tsubst_flags_t); -extern tree build_functional_cast (tree, tree, tsubst_flags_t); -extern tree add_exception_specifier (tree, tree, int); -extern tree merge_exception_specifiers (tree, tree); - -/* in mangle.c */ -extern bool maybe_remove_implicit_alias (tree); -extern void init_mangle (void); -extern void mangle_decl (tree); -extern const char *mangle_type_string (tree); -extern tree mangle_typeinfo_for_type (tree); -extern tree mangle_typeinfo_string_for_type (tree); -extern tree mangle_vtbl_for_type (tree); -extern tree mangle_vtt_for_type (tree); -extern tree mangle_ctor_vtbl_for_type (tree, tree); -extern tree mangle_thunk (tree, int, tree, tree); -extern tree mangle_conv_op_name_for_type (tree); -extern tree mangle_guard_variable (tree); -extern tree mangle_tls_init_fn (tree); -extern tree mangle_tls_wrapper_fn (tree); -extern bool decl_tls_wrapper_p (tree); -extern tree mangle_ref_init_variable (tree); -extern char * get_mangled_vtable_map_var_name (tree); -extern bool mangle_return_type_p (tree); - -/* in dump.c */ -extern bool cp_dump_tree (void *, tree); - -/* In cp/cp-objcp-common.c. */ - -extern alias_set_type cxx_get_alias_set (tree); -extern bool cxx_warn_unused_global_decl (const_tree); -extern size_t cp_tree_size (enum tree_code); -extern bool cp_var_mod_type_p (tree, tree); -extern void cxx_initialize_diagnostics (diagnostic_context *); -extern int cxx_types_compatible_p (tree, tree); -extern void init_shadowed_var_for_decl (void); -extern bool cxx_block_may_fallthru (const_tree); - -/* in cp-gimplify.c */ -extern int cp_gimplify_expr (tree *, gimple_seq *, - gimple_seq *); -extern void cp_genericize (tree); -extern bool cxx_omp_const_qual_no_mutable (tree); -extern enum omp_clause_default_kind cxx_omp_predetermined_sharing (tree); -extern tree cxx_omp_clause_default_ctor (tree, tree, tree); -extern tree cxx_omp_clause_copy_ctor (tree, tree, tree); -extern tree cxx_omp_clause_assign_op (tree, tree, tree); -extern tree cxx_omp_clause_dtor (tree, tree); -extern void cxx_omp_finish_clause (tree, gimple_seq *); -extern bool cxx_omp_privatize_by_reference (const_tree); - -/* in name-lookup.c */ -extern void suggest_alternatives_for (location_t, tree); -extern tree strip_using_decl (tree); - -/* in vtable-class-hierarchy.c */ -extern void vtv_compute_class_hierarchy_transitive_closure (void); -extern void vtv_generate_init_routine (void); -extern void vtv_save_class_info (tree); -extern void vtv_recover_class_info (void); -extern void vtv_build_vtable_verify_fndecl (void); - -/* In cp-cilkplus.c. */ -extern bool cpp_validate_cilk_plus_loop (tree); - -/* In cp/cp-array-notations.c */ -extern tree expand_array_notation_exprs (tree); -bool cilkplus_an_triplet_types_ok_p (location_t, tree, tree, tree, - tree); - -/* In constexpr.c */ -extern bool literal_type_p (tree); -extern tree register_constexpr_fundef (tree, tree); -extern bool check_constexpr_ctor_body (tree, tree, bool); -extern tree ensure_literal_type_for_constexpr_object (tree); -extern bool potential_constant_expression (tree); -extern bool potential_static_init_expression (tree); -extern bool potential_rvalue_constant_expression (tree); -extern bool require_potential_constant_expression (tree); -extern bool require_potential_rvalue_constant_expression (tree); -extern tree cxx_constant_value (tree, tree = NULL_TREE); -extern tree maybe_constant_value (tree, tree = NULL_TREE); -extern tree maybe_constant_init (tree, tree = NULL_TREE); -extern tree fold_non_dependent_expr (tree); -extern bool is_sub_constant_expr (tree); -extern bool reduced_constant_expression_p (tree); -extern bool is_instantiation_of_constexpr (tree); -extern bool var_in_constexpr_fn (tree); -extern void explain_invalid_constexpr_fn (tree); -extern vec cx_error_context (void); - -/* In c-family/cilk.c */ -extern bool cilk_valid_spawn (tree); - -/* In cp-ubsan.c */ -extern void cp_ubsan_maybe_instrument_member_call (tree); -extern void cp_ubsan_instrument_member_accesses (tree *); -extern tree cp_ubsan_maybe_instrument_downcast (location_t, tree, tree, tree); -extern tree cp_ubsan_maybe_instrument_cast_to_vbase (location_t, tree, tree); - -/* -- end of C++ */ - -#endif /* ! GCC_CP_TREE_H */ diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/cp/cxx-pretty-print.h b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/cp/cxx-pretty-print.h deleted file mode 100644 index 16f3238..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/cp/cxx-pretty-print.h +++ /dev/null @@ -1,96 +0,0 @@ -/* Interface for the GNU C++ pretty-printer. - Copyright (C) 2003-2015 Free Software Foundation, Inc. - Contributed by Gabriel Dos Reis - -This file is part of GCC. - -GCC is free software; you can redistribute it and/or modify it under -the terms of the GNU General Public License as published by the Free -Software Foundation; either version 3, or (at your option) any later -version. - -GCC is distributed in the hope that it will be useful, but WITHOUT ANY -WARRANTY; without even the implied warranty of MERCHANTABILITY or -FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -for more details. - -You should have received a copy of the GNU General Public License -along with GCC; see the file COPYING3. If not see -. */ - -#ifndef GCC_CXX_PRETTY_PRINT_H -#define GCC_CXX_PRETTY_PRINT_H - -#include "c-family/c-pretty-print.h" - -enum cxx_pretty_printer_flags -{ - /* Ask for a qualified-id. */ - pp_cxx_flag_default_argument = 1 << pp_c_flag_last_bit -}; - -struct cxx_pretty_printer : c_pretty_printer -{ - cxx_pretty_printer (); - - void constant (tree); - void id_expression (tree); - void primary_expression (tree); - void postfix_expression (tree); - void unary_expression (tree); - void multiplicative_expression (tree); - void conditional_expression (tree); - void assignment_expression (tree); - void expression (tree); - void type_id (tree); - void statement (tree); - void declaration (tree); - void declaration_specifiers (tree); - void simple_type_specifier (tree); - void function_specifier (tree); - void declarator (tree); - void direct_declarator (tree); - void abstract_declarator (tree); - void direct_abstract_declarator (tree); - - /* This is the enclosing scope of the entity being pretty-printed. */ - tree enclosing_scope; -}; - -#define pp_cxx_cv_qualifier_seq(PP, T) \ - pp_c_type_qualifier_list (PP, T) -#define pp_cxx_cv_qualifiers(PP, CV, FT) \ - pp_c_cv_qualifiers (PP, CV, FT) - -#define pp_cxx_whitespace(PP) pp_c_whitespace (PP) -#define pp_cxx_left_paren(PP) pp_c_left_paren (PP) -#define pp_cxx_right_paren(PP) pp_c_right_paren (PP) -#define pp_cxx_left_brace(PP) pp_c_left_brace (PP) -#define pp_cxx_right_brace(PP) pp_c_right_brace (PP) -#define pp_cxx_left_bracket(PP) pp_c_left_bracket (PP) -#define pp_cxx_right_bracket(PP) pp_c_right_bracket (PP) -#define pp_cxx_dot(PP) pp_c_dot (PP) -#define pp_cxx_ampersand(PP) pp_c_ampersand (PP) -#define pp_cxx_star(PP) pp_c_star (PP) -#define pp_cxx_arrow(PP) pp_c_arrow (PP) -#define pp_cxx_semicolon(PP) pp_c_semicolon (PP) -#define pp_cxx_complement(PP) pp_c_complement (PP) - -#define pp_cxx_ws_string(PP, I) pp_c_ws_string (PP, I) -#define pp_cxx_identifier(PP, I) pp_c_identifier (PP, I) -#define pp_cxx_tree_identifier(PP, T) \ - pp_c_tree_identifier (PP, T) - -void pp_cxx_begin_template_argument_list (cxx_pretty_printer *); -void pp_cxx_end_template_argument_list (cxx_pretty_printer *); -void pp_cxx_colon_colon (cxx_pretty_printer *); -void pp_cxx_separate_with (cxx_pretty_printer *, int); - -void pp_cxx_canonical_template_parameter (cxx_pretty_printer *, tree); -void pp_cxx_trait_expression (cxx_pretty_printer *, tree); -void pp_cxx_va_arg_expression (cxx_pretty_printer *, tree); -void pp_cxx_offsetof_expression (cxx_pretty_printer *, tree); -void pp_cxx_userdef_literal (cxx_pretty_printer *, tree); - - -#endif /* GCC_CXX_PRETTY_PRINT_H */ diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/cp/name-lookup.h b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/cp/name-lookup.h deleted file mode 100644 index 4d941fe..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/cp/name-lookup.h +++ /dev/null @@ -1,377 +0,0 @@ -/* Declarations for C++ name lookup routines. - Copyright (C) 2003-2015 Free Software Foundation, Inc. - Contributed by Gabriel Dos Reis - -This file is part of GCC. - -GCC is free software; you can redistribute it and/or modify -it under the terms of the GNU General Public License as published by -the Free Software Foundation; either version 3, or (at your option) -any later version. - -GCC is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU General Public License for more details. - -You should have received a copy of the GNU General Public License -along with GCC; see the file COPYING3. If not see -. */ - -#ifndef GCC_CP_NAME_LOOKUP_H -#define GCC_CP_NAME_LOOKUP_H - -#include "c-family/c-common.h" - -/* The type of dictionary used to map names to types declared at - a given scope. */ -typedef struct binding_table_s *binding_table; -typedef struct binding_entry_s *binding_entry; - -/* The type of a routine repeatedly called by binding_table_foreach. */ -typedef void (*bt_foreach_proc) (binding_entry, void *); - -struct GTY(()) binding_entry_s { - binding_entry chain; - tree name; - tree type; -}; - -/* These macros indicate the initial chains count for binding_table. */ -#define SCOPE_DEFAULT_HT_SIZE (1 << 3) -#define CLASS_SCOPE_HT_SIZE (1 << 3) -#define NAMESPACE_ORDINARY_HT_SIZE (1 << 5) -#define NAMESPACE_STD_HT_SIZE (1 << 8) -#define GLOBAL_SCOPE_HT_SIZE (1 << 8) - -extern void binding_table_foreach (binding_table, bt_foreach_proc, void *); -extern binding_entry binding_table_find (binding_table, tree); - -/* Datatype that represents binding established by a declaration between - a name and a C++ entity. */ -typedef struct cxx_binding cxx_binding; - -/* The datatype used to implement C++ scope. */ -typedef struct cp_binding_level cp_binding_level; - -/* Nonzero if this binding is for a local scope, as opposed to a class - or namespace scope. */ -#define LOCAL_BINDING_P(NODE) ((NODE)->is_local) - -/* True if NODE->value is from a base class of the class which is - currently being defined. */ -#define INHERITED_VALUE_BINDING_P(NODE) ((NODE)->value_is_inherited) - -struct GTY(()) cxx_binding { - /* Link to chain together various bindings for this name. */ - cxx_binding *previous; - /* The non-type entity this name is bound to. */ - tree value; - /* The type entity this name is bound to. */ - tree type; - /* The scope at which this binding was made. */ - cp_binding_level *scope; - unsigned value_is_inherited : 1; - unsigned is_local : 1; -}; - -/* Datatype used to temporarily save C++ bindings (for implicit - instantiations purposes and like). Implemented in decl.c. */ -typedef struct GTY(()) cxx_saved_binding { - /* The name of the current binding. */ - tree identifier; - /* The binding we're saving. */ - cxx_binding *binding; - tree real_type_value; -} cxx_saved_binding; - - -extern tree identifier_type_value (tree); -extern void set_identifier_type_value (tree, tree); -extern void pop_binding (tree, tree); -extern void pop_bindings_and_leave_scope (void); -extern tree constructor_name (tree); -extern bool constructor_name_p (tree, tree); - -/* The kinds of scopes we recognize. */ -typedef enum scope_kind { - sk_block = 0, /* An ordinary block scope. This enumerator must - have the value zero because "cp_binding_level" - is initialized by using "memset" to set the - contents to zero, and the default scope kind - is "sk_block". */ - sk_cleanup, /* A scope for (pseudo-)scope for cleanup. It is - pseudo in that it is transparent to name lookup - activities. */ - sk_try, /* A try-block. */ - sk_catch, /* A catch-block. */ - sk_for, /* The scope of the variable declared in a - for-init-statement. */ - sk_cond, /* The scope of the variable declared in the condition - of an if or switch statement. */ - sk_function_parms, /* The scope containing function parameters. */ - sk_class, /* The scope containing the members of a class. */ - sk_scoped_enum, /* The scope containing the enumertors of a C++0x - scoped enumeration. */ - sk_namespace, /* The scope containing the members of a - namespace, including the global scope. */ - sk_template_parms, /* A scope for template parameters. */ - sk_template_spec, /* Like sk_template_parms, but for an explicit - specialization. Since, by definition, an - explicit specialization is introduced by - "template <>", this scope is always empty. */ - sk_omp /* An OpenMP structured block. */ -} scope_kind; - -/* The scope where the class/struct/union/enum tag applies. */ -typedef enum tag_scope { - ts_current = 0, /* Current scope only. This is for the - class-key identifier; - case mentioned in [basic.lookup.elab]/2, - or the class/enum definition - class-key identifier { ... }; */ - ts_global = 1, /* All scopes. This is the 3.4.1 - [basic.lookup.unqual] lookup mentioned - in [basic.lookup.elab]/2. */ - ts_within_enclosing_non_class = 2, /* Search within enclosing non-class - only, for friend class lookup - according to [namespace.memdef]/3 - and [class.friend]/9. */ - ts_lambda = 3 /* Declaring a lambda closure. */ -} tag_scope; - -typedef struct GTY(()) cp_class_binding { - cxx_binding *base; - /* The bound name. */ - tree identifier; -} cp_class_binding; - - -typedef struct GTY(()) cp_label_binding { - /* The bound LABEL_DECL. */ - tree label; - /* The previous IDENTIFIER_LABEL_VALUE. */ - tree prev_value; -} cp_label_binding; - - -/* For each binding contour we allocate a binding_level structure - which records the names defined in that contour. - Contours include: - 0) the global one - 1) one for each function definition, - where internal declarations of the parameters appear. - 2) one for each compound statement, - to record its declarations. - - The current meaning of a name can be found by searching the levels - from the current one out to the global one. - - Off to the side, may be the class_binding_level. This exists only - to catch class-local declarations. It is otherwise nonexistent. - - Also there may be binding levels that catch cleanups that must be - run when exceptions occur. Thus, to see whether a name is bound in - the current scope, it is not enough to look in the - CURRENT_BINDING_LEVEL. You should use lookup_name_current_level - instead. */ - -/* Note that the information in the `names' component of the global contour - is duplicated in the IDENTIFIER_GLOBAL_VALUEs of all identifiers. */ - -struct GTY(()) cp_binding_level { - /* A chain of _DECL nodes for all variables, constants, functions, - and typedef types. These are in the reverse of the order - supplied. There may be OVERLOADs on this list, too, but they - are wrapped in TREE_LISTs; the TREE_VALUE is the OVERLOAD. */ - tree names; - - /* A chain of NAMESPACE_DECL nodes. */ - tree namespaces; - - /* An array of static functions and variables (for namespaces only) */ - vec *static_decls; - - /* A list of USING_DECL nodes. */ - tree usings; - - /* A list of used namespaces. PURPOSE is the namespace, - VALUE the common ancestor with this binding_level's namespace. */ - tree using_directives; - - /* For the binding level corresponding to a class, the entities - declared in the class or its base classes. */ - vec *class_shadowed; - - /* Similar to class_shadowed, but for IDENTIFIER_TYPE_VALUE, and - is used for all binding levels. The TREE_PURPOSE is the name of - the entity, the TREE_TYPE is the associated type. In addition - the TREE_VALUE is the IDENTIFIER_TYPE_VALUE before we entered - the class. */ - tree type_shadowed; - - /* Similar to class_shadowed, but for IDENTIFIER_LABEL_VALUE, and - used for all binding levels. */ - vec *shadowed_labels; - - /* For each level (except not the global one), - a chain of BLOCK nodes for all the levels - that were entered and exited one level down. */ - tree blocks; - - /* The entity (namespace, class, function) the scope of which this - binding contour corresponds to. Otherwise NULL. */ - tree this_entity; - - /* The binding level which this one is contained in (inherits from). */ - cp_binding_level *level_chain; - - /* List of VAR_DECLS saved from a previous for statement. - These would be dead in ISO-conforming code, but might - be referenced in ARM-era code. */ - vec *dead_vars_from_for; - - /* STATEMENT_LIST for statements in this binding contour. - Only used at present for SK_CLEANUP temporary bindings. */ - tree statement_list; - - /* Binding depth at which this level began. */ - int binding_depth; - - /* The kind of scope that this object represents. However, a - SK_TEMPLATE_SPEC scope is represented with KIND set to - SK_TEMPLATE_PARMS and EXPLICIT_SPEC_P set to true. */ - ENUM_BITFIELD (scope_kind) kind : 4; - - /* True if this scope is an SK_TEMPLATE_SPEC scope. This field is - only valid if KIND == SK_TEMPLATE_PARMS. */ - BOOL_BITFIELD explicit_spec_p : 1; - - /* true means make a BLOCK for this level regardless of all else. */ - unsigned keep : 1; - - /* Nonzero if this level can safely have additional - cleanup-needing variables added to it. */ - unsigned more_cleanups_ok : 1; - unsigned have_cleanups : 1; - - /* Transient state set if this scope is of sk_class kind - and is in the process of defining 'this_entity'. Reset - on leaving the class definition to allow for the scope - to be subsequently re-used as a non-defining scope for - 'this_entity'. */ - unsigned defining_class_p : 1; - - /* 23 bits left to fill a 32-bit word. */ -}; - -/* The binding level currently in effect. */ - -#define current_binding_level \ - (*(cfun && cp_function_chain && cp_function_chain->bindings \ - ? &cp_function_chain->bindings \ - : &scope_chain->bindings)) - -/* The binding level of the current class, if any. */ - -#define class_binding_level scope_chain->class_bindings - -/* The tree node representing the global scope. */ -extern GTY(()) tree global_namespace; -extern GTY(()) tree global_scope_name; - -/* Indicates that there is a type value in some namespace, although - that is not necessarily in scope at the moment. */ - -extern GTY(()) tree global_type_node; - -/* True if SCOPE designates the global scope binding contour. */ -#define global_scope_p(SCOPE) \ - ((SCOPE) == NAMESPACE_LEVEL (global_namespace)) - -extern cp_binding_level *leave_scope (void); -extern bool kept_level_p (void); -extern bool global_bindings_p (void); -extern bool toplevel_bindings_p (void); -extern bool namespace_bindings_p (void); -extern bool local_bindings_p (void); -extern bool template_parm_scope_p (void); -extern scope_kind innermost_scope_kind (void); -extern cp_binding_level *begin_scope (scope_kind, tree); -extern void print_binding_stack (void); -extern void push_to_top_level (void); -extern void pop_from_top_level (void); -extern void pop_everything (void); -extern void keep_next_level (bool); -extern bool is_ancestor (tree, tree); -extern tree push_scope (tree); -extern void pop_scope (tree); -extern tree push_inner_scope (tree); -extern void pop_inner_scope (tree, tree); -extern void push_binding_level (cp_binding_level *); - -extern void push_namespace (tree); -extern void pop_namespace (void); -extern void push_nested_namespace (tree); -extern void pop_nested_namespace (tree); -extern bool handle_namespace_attrs (tree, tree); -extern void pushlevel_class (void); -extern void poplevel_class (void); -extern tree pushdecl_with_scope (tree, cp_binding_level *, bool); -extern tree lookup_name_prefer_type (tree, int); -extern tree lookup_name_real (tree, int, int, bool, int, int); -extern tree lookup_type_scope (tree, tag_scope); -extern tree namespace_binding (tree, tree); -extern void set_namespace_binding (tree, tree, tree); -extern bool hidden_name_p (tree); -extern tree remove_hidden_names (tree); -extern tree lookup_qualified_name (tree, tree, bool, bool); -extern tree lookup_name_nonclass (tree); -extern tree lookup_name_innermost_nonclass_level (tree); -extern bool is_local_extern (tree); -extern tree lookup_function_nonclass (tree, vec *, bool); -extern void push_local_binding (tree, tree, int); -extern bool pushdecl_class_level (tree); -extern tree pushdecl_namespace_level (tree, bool); -extern bool push_class_level_binding (tree, tree); -extern tree getdecls (void); -extern int function_parm_depth (void); -extern tree cp_namespace_decls (tree); -extern void set_decl_namespace (tree, tree, bool); -extern void push_decl_namespace (tree); -extern void pop_decl_namespace (void); -extern void do_namespace_alias (tree, tree); -extern void do_toplevel_using_decl (tree, tree, tree); -extern void do_local_using_decl (tree, tree, tree); -extern tree do_class_using_decl (tree, tree); -extern void do_using_directive (tree); -extern tree lookup_arg_dependent (tree, tree, vec *); -extern bool is_associated_namespace (tree, tree); -extern void parse_using_directive (tree, tree); -extern tree innermost_non_namespace_value (tree); -extern cxx_binding *outer_binding (tree, cxx_binding *, bool); -extern void cp_emit_debug_info_for_using (tree, tree); - -/* Set *DECL to the (non-hidden) declaration for ID at global scope, - if present and return true; otherwise return false. */ - -inline bool -get_global_value_if_present (tree id, tree *decl) -{ - tree global_value = namespace_binding (id, global_namespace); - if (global_value) - *decl = global_value; - return global_value != NULL; -} - -/* True is the binding of IDENTIFIER at global scope names a type. */ - -inline bool -is_typename_at_global_scope (tree id) -{ - tree global_value = namespace_binding (id, global_namespace); - - return global_value && TREE_CODE (global_value) == TYPE_DECL; -} - -#endif /* GCC_CP_NAME_LOOKUP_H */ diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/cp/type-utils.h b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/cp/type-utils.h deleted file mode 100644 index 05f2785..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/cp/type-utils.h +++ /dev/null @@ -1,55 +0,0 @@ -/* Utilities for querying and manipulating type trees. - Copyright (C) 2013-2015 Free Software Foundation, Inc. - -This file is part of GCC. - -GCC is free software; you can redistribute it and/or modify -it under the terms of the GNU General Public License as published by -the Free Software Foundation; either version 3, or (at your option) -any later version. - -GCC is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU General Public License for more details. - -You should have received a copy of the GNU General Public License -along with GCC; see the file COPYING3. If not see -. */ - -#ifndef GCC_CP_TYPE_UTILS_H -#define GCC_CP_TYPE_UTILS_H - -/* Returns the first tree within T that is directly matched by PRED. T may be a - type or PARM_DECL and is incrementally decomposed toward its type-specifier - until a match is found. NULL_TREE is returned if PRED does not match any - part of T. - - This is primarily intended for detecting whether T uses `auto' or a concept - identifier. Since either of these can only appear as a type-specifier for - the declaration in question, only top-level qualifications are traversed; - find_type_usage does not look through the whole type. */ - -inline tree -find_type_usage (tree t, bool (*pred) (const_tree)) -{ - enum tree_code code; - if (pred (t)) - return t; - - code = TREE_CODE (t); - - if (code == POINTER_TYPE || code == REFERENCE_TYPE - || code == PARM_DECL || code == OFFSET_TYPE - || code == FUNCTION_TYPE || code == METHOD_TYPE - || code == ARRAY_TYPE) - return find_type_usage (TREE_TYPE (t), pred); - - if (TYPE_PTRMEMFUNC_P (t)) - return find_type_usage - (TREE_TYPE (TYPE_PTRMEMFUNC_FN_TYPE (t)), pred); - - return NULL_TREE; -} - -#endif // GCC_CP_TYPE_UTILS_H diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/cppbuiltin.h b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/cppbuiltin.h deleted file mode 100644 index 4f96197..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/cppbuiltin.h +++ /dev/null @@ -1,33 +0,0 @@ -/* Define builtin-in macros for all front ends that perform preprocessing - Copyright (C) 2010-2015 Free Software Foundation, Inc. - -This file is part of GCC. - -GCC is free software; you can redistribute it and/or modify it under -the terms of the GNU General Public License as published by the Free -Software Foundation; either version 3, or (at your option) any later -version. - -GCC is distributed in the hope that it will be useful, but WITHOUT ANY -WARRANTY; without even the implied warranty of MERCHANTABILITY or -FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -for more details. - -You should have received a copy of the GNU General Public License -along with GCC; see the file COPYING3. If not see -. */ - -#ifndef GCC_CPPBUILTIN_H -#define GCC_CPPBUILTIN_H - -/* Parse a BASEVER version string of the format "major.minor.patchlevel" - or "major.minor" to extract its components. */ -extern void parse_basever (int *, int *, int *); - -/* Define macros builtins common to all language performing CPP - preprocessing. */ -extern void define_language_independent_builtin_macros (cpp_reader *); - - -#endif /* ! GCC_CPPBUILTIN_H */ - diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/cppdefault.h b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/cppdefault.h deleted file mode 100644 index c98644f..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/cppdefault.h +++ /dev/null @@ -1,71 +0,0 @@ -/* CPP Library. - Copyright (C) 1986-2015 Free Software Foundation, Inc. - Contributed by Per Bothner, 1994-95. - Based on CCCP program by Paul Rubin, June 1986 - Adapted to ANSI C, Richard Stallman, Jan 1987 - - This program is free software; you can redistribute it and/or modify it - under the terms of the GNU General Public License as published by the - Free Software Foundation; either version 3, or (at your option) any - later version. - - This program is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program; see the file COPYING3. If not see - . */ - -#ifndef GCC_CPPDEFAULT_H -#define GCC_CPPDEFAULT_H - -/* This is the default list of directories to search for include files. - It may be overridden by the various -I and -ixxx options. - - #include "file" looks in the same directory as the current file, - then this list. - #include just looks in this list. - - All these directories are treated as `system' include directories - (they are not subject to pedantic warnings in some cases). */ - -struct default_include -{ - const char *const fname; /* The name of the directory. */ - const char *const component; /* The component containing the directory - (see update_path in prefix.c) */ - const char cplusplus; /* Only look here if we're compiling C++. */ - const char cxx_aware; /* Includes in this directory don't need to - be wrapped in extern "C" when compiling - C++. */ - const char add_sysroot; /* FNAME should be prefixed by - cpp_SYSROOT. */ - const char multilib; /* FNAME should have appended - - the multilib path specified with -imultilib - when set to 1, - - the multiarch path specified with - -imultiarch, when set to 2. */ -}; - -extern const struct default_include cpp_include_defaults[]; -extern const char cpp_GCC_INCLUDE_DIR[]; -extern const size_t cpp_GCC_INCLUDE_DIR_len; - -/* The configure-time prefix, i.e., the value supplied as the argument - to --prefix=. */ -extern const char cpp_PREFIX[]; -/* The length of the configure-time prefix. */ -extern const size_t cpp_PREFIX_len; -/* The configure-time execution prefix. This is typically the lib/gcc - subdirectory of cpp_PREFIX. */ -extern const char cpp_EXEC_PREFIX[]; -/* The run-time execution prefix. This is typically the lib/gcc - subdirectory of the actual installation. */ -extern const char *gcc_exec_prefix; - -/* Return true if the toolchain is relocated. */ -bool cpp_relocated (void); - -#endif /* ! GCC_CPPDEFAULT_H */ diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/cpplib.h b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/cpplib.h deleted file mode 100644 index 1b731d1..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/cpplib.h +++ /dev/null @@ -1,1105 +0,0 @@ -/* Definitions for CPP library. - Copyright (C) 1995-2015 Free Software Foundation, Inc. - Written by Per Bothner, 1994-95. - -This program is free software; you can redistribute it and/or modify it -under the terms of the GNU General Public License as published by the -Free Software Foundation; either version 3, or (at your option) any -later version. - -This program is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU General Public License for more details. - -You should have received a copy of the GNU General Public License -along with this program; see the file COPYING3. If not see -. - - In other words, you are welcome to use, share and improve this program. - You are forbidden to forbid anyone else to use, share and improve - what you give them. Help stamp out software-hoarding! */ -#ifndef LIBCPP_CPPLIB_H -#define LIBCPP_CPPLIB_H - -#include -#include "symtab.h" -#include "line-map.h" - -typedef struct cpp_reader cpp_reader; -typedef struct cpp_buffer cpp_buffer; -typedef struct cpp_options cpp_options; -typedef struct cpp_token cpp_token; -typedef struct cpp_string cpp_string; -typedef struct cpp_hashnode cpp_hashnode; -typedef struct cpp_macro cpp_macro; -typedef struct cpp_callbacks cpp_callbacks; -typedef struct cpp_dir cpp_dir; - -struct answer; -struct _cpp_file; - -/* The first three groups, apart from '=', can appear in preprocessor - expressions (+= and -= are used to indicate unary + and - resp.). - This allows a lookup table to be implemented in _cpp_parse_expr. - - The first group, to CPP_LAST_EQ, can be immediately followed by an - '='. The lexer needs operators ending in '=', like ">>=", to be in - the same order as their counterparts without the '=', like ">>". - - See the cpp_operator table optab in expr.c if you change the order or - add or remove anything in the first group. */ - -#define TTYPE_TABLE \ - OP(EQ, "=") \ - OP(NOT, "!") \ - OP(GREATER, ">") /* compare */ \ - OP(LESS, "<") \ - OP(PLUS, "+") /* math */ \ - OP(MINUS, "-") \ - OP(MULT, "*") \ - OP(DIV, "/") \ - OP(MOD, "%") \ - OP(AND, "&") /* bit ops */ \ - OP(OR, "|") \ - OP(XOR, "^") \ - OP(RSHIFT, ">>") \ - OP(LSHIFT, "<<") \ - \ - OP(COMPL, "~") \ - OP(AND_AND, "&&") /* logical */ \ - OP(OR_OR, "||") \ - OP(QUERY, "?") \ - OP(COLON, ":") \ - OP(COMMA, ",") /* grouping */ \ - OP(OPEN_PAREN, "(") \ - OP(CLOSE_PAREN, ")") \ - TK(EOF, NONE) \ - OP(EQ_EQ, "==") /* compare */ \ - OP(NOT_EQ, "!=") \ - OP(GREATER_EQ, ">=") \ - OP(LESS_EQ, "<=") \ - \ - /* These two are unary + / - in preprocessor expressions. */ \ - OP(PLUS_EQ, "+=") /* math */ \ - OP(MINUS_EQ, "-=") \ - \ - OP(MULT_EQ, "*=") \ - OP(DIV_EQ, "/=") \ - OP(MOD_EQ, "%=") \ - OP(AND_EQ, "&=") /* bit ops */ \ - OP(OR_EQ, "|=") \ - OP(XOR_EQ, "^=") \ - OP(RSHIFT_EQ, ">>=") \ - OP(LSHIFT_EQ, "<<=") \ - /* Digraphs together, beginning with CPP_FIRST_DIGRAPH. */ \ - OP(HASH, "#") /* digraphs */ \ - OP(PASTE, "##") \ - OP(OPEN_SQUARE, "[") \ - OP(CLOSE_SQUARE, "]") \ - OP(OPEN_BRACE, "{") \ - OP(CLOSE_BRACE, "}") \ - /* The remainder of the punctuation. Order is not significant. */ \ - OP(SEMICOLON, ";") /* structure */ \ - OP(ELLIPSIS, "...") \ - OP(PLUS_PLUS, "++") /* increment */ \ - OP(MINUS_MINUS, "--") \ - OP(DEREF, "->") /* accessors */ \ - OP(DOT, ".") \ - OP(SCOPE, "::") \ - OP(DEREF_STAR, "->*") \ - OP(DOT_STAR, ".*") \ - OP(ATSIGN, "@") /* used in Objective-C */ \ - \ - TK(NAME, IDENT) /* word */ \ - TK(AT_NAME, IDENT) /* @word - Objective-C */ \ - TK(NUMBER, LITERAL) /* 34_be+ta */ \ - \ - TK(CHAR, LITERAL) /* 'char' */ \ - TK(WCHAR, LITERAL) /* L'char' */ \ - TK(CHAR16, LITERAL) /* u'char' */ \ - TK(CHAR32, LITERAL) /* U'char' */ \ - TK(OTHER, LITERAL) /* stray punctuation */ \ - \ - TK(STRING, LITERAL) /* "string" */ \ - TK(WSTRING, LITERAL) /* L"string" */ \ - TK(STRING16, LITERAL) /* u"string" */ \ - TK(STRING32, LITERAL) /* U"string" */ \ - TK(UTF8STRING, LITERAL) /* u8"string" */ \ - TK(OBJC_STRING, LITERAL) /* @"string" - Objective-C */ \ - TK(HEADER_NAME, LITERAL) /* in #include */ \ - \ - TK(CHAR_USERDEF, LITERAL) /* 'char'_suffix - C++-0x */ \ - TK(WCHAR_USERDEF, LITERAL) /* L'char'_suffix - C++-0x */ \ - TK(CHAR16_USERDEF, LITERAL) /* u'char'_suffix - C++-0x */ \ - TK(CHAR32_USERDEF, LITERAL) /* U'char'_suffix - C++-0x */ \ - TK(STRING_USERDEF, LITERAL) /* "string"_suffix - C++-0x */ \ - TK(WSTRING_USERDEF, LITERAL) /* L"string"_suffix - C++-0x */ \ - TK(STRING16_USERDEF, LITERAL) /* u"string"_suffix - C++-0x */ \ - TK(STRING32_USERDEF, LITERAL) /* U"string"_suffix - C++-0x */ \ - TK(UTF8STRING_USERDEF,LITERAL) /* u8"string"_suffix - C++-0x */ \ - \ - TK(COMMENT, LITERAL) /* Only if output comments. */ \ - /* SPELL_LITERAL happens to DTRT. */ \ - TK(MACRO_ARG, NONE) /* Macro argument. */ \ - TK(PRAGMA, NONE) /* Only for deferred pragmas. */ \ - TK(PRAGMA_EOL, NONE) /* End-of-line for deferred pragmas. */ \ - TK(PADDING, NONE) /* Whitespace for -E. */ - -#define OP(e, s) CPP_ ## e, -#define TK(e, s) CPP_ ## e, -enum cpp_ttype -{ - TTYPE_TABLE - N_TTYPES, - - /* A token type for keywords, as opposed to ordinary identifiers. */ - CPP_KEYWORD, - - /* Positions in the table. */ - CPP_LAST_EQ = CPP_LSHIFT, - CPP_FIRST_DIGRAPH = CPP_HASH, - CPP_LAST_PUNCTUATOR= CPP_ATSIGN, - CPP_LAST_CPP_OP = CPP_LESS_EQ -}; -#undef OP -#undef TK - -/* C language kind, used when calling cpp_create_reader. */ -enum c_lang {CLK_GNUC89 = 0, CLK_GNUC99, CLK_GNUC11, - CLK_STDC89, CLK_STDC94, CLK_STDC99, CLK_STDC11, - CLK_GNUCXX, CLK_CXX98, CLK_GNUCXX11, CLK_CXX11, - CLK_GNUCXX14, CLK_CXX14, CLK_GNUCXX1Z, CLK_CXX1Z, CLK_ASM}; - -/* Payload of a NUMBER, STRING, CHAR or COMMENT token. */ -struct GTY(()) cpp_string { - unsigned int len; - const unsigned char *text; -}; - -/* Flags for the cpp_token structure. */ -#define PREV_WHITE (1 << 0) /* If whitespace before this token. */ -#define DIGRAPH (1 << 1) /* If it was a digraph. */ -#define STRINGIFY_ARG (1 << 2) /* If macro argument to be stringified. */ -#define PASTE_LEFT (1 << 3) /* If on LHS of a ## operator. */ -#define NAMED_OP (1 << 4) /* C++ named operators. */ -#define NO_EXPAND (1 << 5) /* Do not macro-expand this token. */ -#define BOL (1 << 6) /* Token at beginning of line. */ -#define PURE_ZERO (1 << 7) /* Single 0 digit, used by the C++ frontend, - set in c-lex.c. */ -#define SP_DIGRAPH (1 << 8) /* # or ## token was a digraph. */ -#define SP_PREV_WHITE (1 << 9) /* If whitespace before a ## - operator, or before this token - after a # operator. */ - -/* Specify which field, if any, of the cpp_token union is used. */ - -enum cpp_token_fld_kind { - CPP_TOKEN_FLD_NODE, - CPP_TOKEN_FLD_SOURCE, - CPP_TOKEN_FLD_STR, - CPP_TOKEN_FLD_ARG_NO, - CPP_TOKEN_FLD_TOKEN_NO, - CPP_TOKEN_FLD_PRAGMA, - CPP_TOKEN_FLD_NONE -}; - -/* A macro argument in the cpp_token union. */ -struct GTY(()) cpp_macro_arg { - /* Argument number. */ - unsigned int arg_no; - /* The original spelling of the macro argument token. */ - cpp_hashnode * - GTY ((nested_ptr (union tree_node, - "%h ? CPP_HASHNODE (GCC_IDENT_TO_HT_IDENT (%h)) : NULL", - "%h ? HT_IDENT_TO_GCC_IDENT (HT_NODE (%h)) : NULL"))) - spelling; -}; - -/* An identifier in the cpp_token union. */ -struct GTY(()) cpp_identifier { - /* The canonical (UTF-8) spelling of the identifier. */ - cpp_hashnode * - GTY ((nested_ptr (union tree_node, - "%h ? CPP_HASHNODE (GCC_IDENT_TO_HT_IDENT (%h)) : NULL", - "%h ? HT_IDENT_TO_GCC_IDENT (HT_NODE (%h)) : NULL"))) - node; - /* The original spelling of the identifier. */ - cpp_hashnode * - GTY ((nested_ptr (union tree_node, - "%h ? CPP_HASHNODE (GCC_IDENT_TO_HT_IDENT (%h)) : NULL", - "%h ? HT_IDENT_TO_GCC_IDENT (HT_NODE (%h)) : NULL"))) - spelling; -}; - -/* A preprocessing token. This has been carefully packed and should - occupy 16 bytes on 32-bit hosts and 24 bytes on 64-bit hosts. */ -struct GTY(()) cpp_token { - source_location src_loc; /* Location of first char of token. */ - ENUM_BITFIELD(cpp_ttype) type : CHAR_BIT; /* token type */ - unsigned short flags; /* flags - see above */ - - union cpp_token_u - { - /* An identifier. */ - struct cpp_identifier GTY ((tag ("CPP_TOKEN_FLD_NODE"))) node; - - /* Inherit padding from this token. */ - cpp_token * GTY ((tag ("CPP_TOKEN_FLD_SOURCE"))) source; - - /* A string, or number. */ - struct cpp_string GTY ((tag ("CPP_TOKEN_FLD_STR"))) str; - - /* Argument no. (and original spelling) for a CPP_MACRO_ARG. */ - struct cpp_macro_arg GTY ((tag ("CPP_TOKEN_FLD_ARG_NO"))) macro_arg; - - /* Original token no. for a CPP_PASTE (from a sequence of - consecutive paste tokens in a macro expansion). */ - unsigned int GTY ((tag ("CPP_TOKEN_FLD_TOKEN_NO"))) token_no; - - /* Caller-supplied identifier for a CPP_PRAGMA. */ - unsigned int GTY ((tag ("CPP_TOKEN_FLD_PRAGMA"))) pragma; - } GTY ((desc ("cpp_token_val_index (&%1)"))) val; -}; - -/* Say which field is in use. */ -extern enum cpp_token_fld_kind cpp_token_val_index (const cpp_token *tok); - -/* A type wide enough to hold any multibyte source character. - cpplib's character constant interpreter requires an unsigned type. - Also, a typedef for the signed equivalent. - The width of this type is capped at 32 bits; there do exist targets - where wchar_t is 64 bits, but only in a non-default mode, and there - would be no meaningful interpretation for a wchar_t value greater - than 2^32 anyway -- the widest wide-character encoding around is - ISO 10646, which stops at 2^31. */ -#if CHAR_BIT * SIZEOF_INT >= 32 -# define CPPCHAR_SIGNED_T int -#elif CHAR_BIT * SIZEOF_LONG >= 32 -# define CPPCHAR_SIGNED_T long -#else -# error "Cannot find a least-32-bit signed integer type" -#endif -typedef unsigned CPPCHAR_SIGNED_T cppchar_t; -typedef CPPCHAR_SIGNED_T cppchar_signed_t; - -/* Style of header dependencies to generate. */ -enum cpp_deps_style { DEPS_NONE = 0, DEPS_USER, DEPS_SYSTEM }; - -/* The possible normalization levels, from most restrictive to least. */ -enum cpp_normalize_level { - /* In NFKC. */ - normalized_KC = 0, - /* In NFC. */ - normalized_C, - /* In NFC, except for subsequences where being in NFC would make - the identifier invalid. */ - normalized_identifier_C, - /* Not normalized at all. */ - normalized_none -}; - -/* This structure is nested inside struct cpp_reader, and - carries all the options visible to the command line. */ -struct cpp_options -{ - /* Characters between tab stops. */ - unsigned int tabstop; - - /* The language we're preprocessing. */ - enum c_lang lang; - - /* Nonzero means use extra default include directories for C++. */ - unsigned char cplusplus; - - /* Nonzero means handle cplusplus style comments. */ - unsigned char cplusplus_comments; - - /* Nonzero means define __OBJC__, treat @ as a special token, use - the OBJC[PLUS]_INCLUDE_PATH environment variable, and allow - "#import". */ - unsigned char objc; - - /* Nonzero means don't copy comments into the output file. */ - unsigned char discard_comments; - - /* Nonzero means don't copy comments into the output file during - macro expansion. */ - unsigned char discard_comments_in_macro_exp; - - /* Nonzero means process the ISO trigraph sequences. */ - unsigned char trigraphs; - - /* Nonzero means process the ISO digraph sequences. */ - unsigned char digraphs; - - /* Nonzero means to allow hexadecimal floats and LL suffixes. */ - unsigned char extended_numbers; - - /* Nonzero means process u/U prefix literals (UTF-16/32). */ - unsigned char uliterals; - - /* Nonzero means process r/R raw strings. If this is set, uliterals - must be set as well. */ - unsigned char rliterals; - - /* Nonzero means print names of header files (-H). */ - unsigned char print_include_names; - - /* Nonzero means complain about deprecated features. */ - unsigned char cpp_warn_deprecated; - - /* Nonzero means warn if slash-star appears in a comment. */ - unsigned char warn_comments; - - /* Nonzero means to warn about __DATA__, __TIME__ and __TIMESTAMP__ usage. */ - unsigned char warn_date_time; - - /* Nonzero means warn if a user-supplied include directory does not - exist. */ - unsigned char warn_missing_include_dirs; - - /* Nonzero means warn if there are any trigraphs. */ - unsigned char warn_trigraphs; - - /* Nonzero means warn about multicharacter charconsts. */ - unsigned char warn_multichar; - - /* Nonzero means warn about various incompatibilities with - traditional C. */ - unsigned char cpp_warn_traditional; - - /* Nonzero means warn about long long numeric constants. */ - unsigned char cpp_warn_long_long; - - /* Nonzero means warn about text after an #endif (or #else). */ - unsigned char warn_endif_labels; - - /* Nonzero means warn about implicit sign changes owing to integer - promotions. */ - unsigned char warn_num_sign_change; - - /* Zero means don't warn about __VA_ARGS__ usage in c89 pedantic mode. - Presumably the usage is protected by the appropriate #ifdef. */ - unsigned char warn_variadic_macros; - - /* Nonzero means warn about builtin macros that are redefined or - explicitly undefined. */ - unsigned char warn_builtin_macro_redefined; - - /* Nonzero means we should look for header.gcc files that remap file - names. */ - unsigned char remap; - - /* Zero means dollar signs are punctuation. */ - unsigned char dollars_in_ident; - - /* Nonzero means UCNs are accepted in identifiers. */ - unsigned char extended_identifiers; - - /* True if we should warn about dollars in identifiers or numbers - for this translation unit. */ - unsigned char warn_dollars; - - /* Nonzero means warn if undefined identifiers are evaluated in an #if. */ - unsigned char warn_undef; - - /* Nonzero means warn of unused macros from the main file. */ - unsigned char warn_unused_macros; - - /* Nonzero for the 1999 C Standard, including corrigenda and amendments. */ - unsigned char c99; - - /* Nonzero if we are conforming to a specific C or C++ standard. */ - unsigned char std; - - /* Nonzero means give all the error messages the ANSI standard requires. */ - unsigned char cpp_pedantic; - - /* Nonzero means we're looking at already preprocessed code, so don't - bother trying to do macro expansion and whatnot. */ - unsigned char preprocessed; - - /* Nonzero means we are going to emit debugging logs during - preprocessing. */ - unsigned char debug; - - /* Nonzero means we are tracking locations of tokens involved in - macro expansion. 1 Means we track the location in degraded mode - where we do not track locations of tokens resulting from the - expansion of arguments of function-like macro. 2 Means we do - track all macro expansions. This last option is the one that - consumes the highest amount of memory. */ - unsigned char track_macro_expansion; - - /* Nonzero means handle C++ alternate operator names. */ - unsigned char operator_names; - - /* Nonzero means warn about use of C++ alternate operator names. */ - unsigned char warn_cxx_operator_names; - - /* True for traditional preprocessing. */ - unsigned char traditional; - - /* Nonzero for C++ 2011 Standard user-defined literals. */ - unsigned char user_literals; - - /* Nonzero means warn when a string or character literal is followed by a - ud-suffix which does not beging with an underscore. */ - unsigned char warn_literal_suffix; - - /* Nonzero means interpret imaginary, fixed-point, or other gnu extension - literal number suffixes as user-defined literal number suffixes. */ - unsigned char ext_numeric_literals; - - /* Nonzero means extended identifiers allow the characters specified - in C11 and C++11. */ - unsigned char c11_identifiers; - - /* Nonzero for C++ 2014 Standard binary constants. */ - unsigned char binary_constants; - - /* Nonzero for C++ 2014 Standard digit separators. */ - unsigned char digit_separators; - - /* Holds the name of the target (execution) character set. */ - const char *narrow_charset; - - /* Holds the name of the target wide character set. */ - const char *wide_charset; - - /* Holds the name of the input character set. */ - const char *input_charset; - - /* The minimum permitted level of normalization before a warning - is generated. See enum cpp_normalize_level. */ - int warn_normalize; - - /* True to warn about precompiled header files we couldn't use. */ - bool warn_invalid_pch; - - /* True if dependencies should be restored from a precompiled header. */ - bool restore_pch_deps; - - /* True if warn about differences between C90 and C99. */ - signed char cpp_warn_c90_c99_compat; - - /* Dependency generation. */ - struct - { - /* Style of header dependencies to generate. */ - enum cpp_deps_style style; - - /* Assume missing files are generated files. */ - bool missing_files; - - /* Generate phony targets for each dependency apart from the first - one. */ - bool phony_targets; - - /* If true, no dependency is generated on the main file. */ - bool ignore_main_file; - - /* If true, intend to use the preprocessor output (e.g., for compilation) - in addition to the dependency info. */ - bool need_preprocessor_output; - } deps; - - /* Target-specific features set by the front end or client. */ - - /* Precision for target CPP arithmetic, target characters, target - ints and target wide characters, respectively. */ - size_t precision, char_precision, int_precision, wchar_precision; - - /* True means chars (wide chars) are unsigned. */ - bool unsigned_char, unsigned_wchar; - - /* True if the most significant byte in a word has the lowest - address in memory. */ - bool bytes_big_endian; - - /* Nonzero means __STDC__ should have the value 0 in system headers. */ - unsigned char stdc_0_in_system_headers; - - /* True disables tokenization outside of preprocessing directives. */ - bool directives_only; - - /* True enables canonicalization of system header file paths. */ - bool canonical_system_headers; -}; - -/* Callback for header lookup for HEADER, which is the name of a - source file. It is used as a method of last resort to find headers - that are not otherwise found during the normal include processing. - The return value is the malloced name of a header to try and open, - if any, or NULL otherwise. This callback is called only if the - header is otherwise unfound. */ -typedef const char *(*missing_header_cb)(cpp_reader *, const char *header, cpp_dir **); - -/* Call backs to cpplib client. */ -struct cpp_callbacks -{ - /* Called when a new line of preprocessed output is started. */ - void (*line_change) (cpp_reader *, const cpp_token *, int); - - /* Called when switching to/from a new file. - The line_map is for the new file. It is NULL if there is no new file. - (In C this happens when done with + and also - when done with a main file.) This can be used for resource cleanup. */ - void (*file_change) (cpp_reader *, const struct line_map *); - - void (*dir_change) (cpp_reader *, const char *); - void (*include) (cpp_reader *, source_location, const unsigned char *, - const char *, int, const cpp_token **); - void (*define) (cpp_reader *, source_location, cpp_hashnode *); - void (*undef) (cpp_reader *, source_location, cpp_hashnode *); - void (*ident) (cpp_reader *, source_location, const cpp_string *); - void (*def_pragma) (cpp_reader *, source_location); - int (*valid_pch) (cpp_reader *, const char *, int); - void (*read_pch) (cpp_reader *, const char *, int, const char *); - missing_header_cb missing_header; - - /* Context-sensitive macro support. Returns macro (if any) that should - be expanded. */ - cpp_hashnode * (*macro_to_expand) (cpp_reader *, const cpp_token *); - - /* Called to emit a diagnostic. This callback receives the - translated message. */ - bool (*error) (cpp_reader *, int, int, source_location, unsigned int, - const char *, va_list *) - ATTRIBUTE_FPTR_PRINTF(6,0); - - /* Callbacks for when a macro is expanded, or tested (whether - defined or not at the time) in #ifdef, #ifndef or "defined". */ - void (*used_define) (cpp_reader *, source_location, cpp_hashnode *); - void (*used_undef) (cpp_reader *, source_location, cpp_hashnode *); - /* Called before #define and #undef or other macro definition - changes are processed. */ - void (*before_define) (cpp_reader *); - /* Called whenever a macro is expanded or tested. - Second argument is the location of the start of the current expansion. */ - void (*used) (cpp_reader *, source_location, cpp_hashnode *); - - /* Callback to identify whether an attribute exists. */ - int (*has_attribute) (cpp_reader *); - - /* Callback that can change a user builtin into normal macro. */ - bool (*user_builtin_macro) (cpp_reader *, cpp_hashnode *); -}; - -#ifdef VMS -#define INO_T_CPP ino_t ino[3] -#else -#define INO_T_CPP ino_t ino -#endif - -/* Chain of directories to look for include files in. */ -struct cpp_dir -{ - /* NULL-terminated singly-linked list. */ - struct cpp_dir *next; - - /* NAME of the directory, NUL-terminated. */ - char *name; - unsigned int len; - - /* One if a system header, two if a system header that has extern - "C" guards for C++. */ - unsigned char sysp; - - /* Is this a user-supplied directory? */ - bool user_supplied_p; - - /* The canonicalized NAME as determined by lrealpath. This field - is only used by hosts that lack reliable inode numbers. */ - char *canonical_name; - - /* Mapping of file names for this directory for MS-DOS and related - platforms. A NULL-terminated array of (from, to) pairs. */ - const char **name_map; - - /* Routine to construct pathname, given the search path name and the - HEADER we are trying to find, return a constructed pathname to - try and open. If this is NULL, the constructed pathname is as - constructed by append_file_to_dir. */ - char *(*construct) (const char *header, cpp_dir *dir); - - /* The C front end uses these to recognize duplicated - directories in the search path. */ - INO_T_CPP; - dev_t dev; -}; - -/* The structure of a node in the hash table. The hash table has - entries for all identifiers: either macros defined by #define - commands (type NT_MACRO), assertions created with #assert - (NT_ASSERTION), or neither of the above (NT_VOID). Builtin macros - like __LINE__ are flagged NODE_BUILTIN. Poisoned identifiers are - flagged NODE_POISONED. NODE_OPERATOR (C++ only) indicates an - identifier that behaves like an operator such as "xor". - NODE_DIAGNOSTIC is for speed in lex_token: it indicates a - diagnostic may be required for this node. Currently this only - applies to __VA_ARGS__, poisoned identifiers, and -Wc++-compat - warnings about NODE_OPERATOR. */ - -/* Hash node flags. */ -#define NODE_OPERATOR (1 << 0) /* C++ named operator. */ -#define NODE_POISONED (1 << 1) /* Poisoned identifier. */ -#define NODE_BUILTIN (1 << 2) /* Builtin macro. */ -#define NODE_DIAGNOSTIC (1 << 3) /* Possible diagnostic when lexed. */ -#define NODE_WARN (1 << 4) /* Warn if redefined or undefined. */ -#define NODE_DISABLED (1 << 5) /* A disabled macro. */ -#define NODE_MACRO_ARG (1 << 6) /* Used during #define processing. */ -#define NODE_USED (1 << 7) /* Dumped with -dU. */ -#define NODE_CONDITIONAL (1 << 8) /* Conditional macro */ -#define NODE_WARN_OPERATOR (1 << 9) /* Warn about C++ named operator. */ - -/* Different flavors of hash node. */ -enum node_type -{ - NT_VOID = 0, /* No definition yet. */ - NT_MACRO, /* A macro of some form. */ - NT_ASSERTION /* Predicate for #assert. */ -}; - -/* Different flavors of builtin macro. _Pragma is an operator, but we - handle it with the builtin code for efficiency reasons. */ -enum cpp_builtin_type -{ - BT_SPECLINE = 0, /* `__LINE__' */ - BT_DATE, /* `__DATE__' */ - BT_FILE, /* `__FILE__' */ - BT_BASE_FILE, /* `__BASE_FILE__' */ - BT_INCLUDE_LEVEL, /* `__INCLUDE_LEVEL__' */ - BT_TIME, /* `__TIME__' */ - BT_STDC, /* `__STDC__' */ - BT_PRAGMA, /* `_Pragma' operator */ - BT_TIMESTAMP, /* `__TIMESTAMP__' */ - BT_COUNTER, /* `__COUNTER__' */ - BT_HAS_ATTRIBUTE, /* `__has_attribute__(x)' */ - BT_FIRST_USER, /* User defined builtin macros. */ - BT_LAST_USER = BT_FIRST_USER + 31 -}; - -#define CPP_HASHNODE(HNODE) ((cpp_hashnode *) (HNODE)) -#define HT_NODE(NODE) ((ht_identifier *) (NODE)) -#define NODE_LEN(NODE) HT_LEN (&(NODE)->ident) -#define NODE_NAME(NODE) HT_STR (&(NODE)->ident) - -/* Specify which field, if any, of the union is used. */ - -enum { - NTV_MACRO, - NTV_ANSWER, - NTV_BUILTIN, - NTV_ARGUMENT, - NTV_NONE -}; - -#define CPP_HASHNODE_VALUE_IDX(HNODE) \ - ((HNODE.flags & NODE_MACRO_ARG) ? NTV_ARGUMENT \ - : HNODE.type == NT_MACRO ? ((HNODE.flags & NODE_BUILTIN) \ - ? NTV_BUILTIN : NTV_MACRO) \ - : HNODE.type == NT_ASSERTION ? NTV_ANSWER \ - : NTV_NONE) - -/* The common part of an identifier node shared amongst all 3 C front - ends. Also used to store CPP identifiers, which are a superset of - identifiers in the grammatical sense. */ - -union GTY(()) _cpp_hashnode_value { - /* If a macro. */ - cpp_macro * GTY((tag ("NTV_MACRO"))) macro; - /* Answers to an assertion. */ - struct answer * GTY ((tag ("NTV_ANSWER"))) answers; - /* Code for a builtin macro. */ - enum cpp_builtin_type GTY ((tag ("NTV_BUILTIN"))) builtin; - /* Macro argument index. */ - unsigned short GTY ((tag ("NTV_ARGUMENT"))) arg_index; -}; - -struct GTY(()) cpp_hashnode { - struct ht_identifier ident; - unsigned int is_directive : 1; - unsigned int directive_index : 7; /* If is_directive, - then index into directive table. - Otherwise, a NODE_OPERATOR. */ - unsigned char rid_code; /* Rid code - for front ends. */ - ENUM_BITFIELD(node_type) type : 6; /* CPP node type. */ - unsigned int flags : 10; /* CPP flags. */ - - union _cpp_hashnode_value GTY ((desc ("CPP_HASHNODE_VALUE_IDX (%1)"))) value; -}; - -/* Call this first to get a handle to pass to other functions. - - If you want cpplib to manage its own hashtable, pass in a NULL - pointer. Otherwise you should pass in an initialized hash table - that cpplib will share; this technique is used by the C front - ends. */ -extern cpp_reader *cpp_create_reader (enum c_lang, struct ht *, - struct line_maps *); - -/* Reset the cpp_reader's line_map. This is only used after reading a - PCH file. */ -extern void cpp_set_line_map (cpp_reader *, struct line_maps *); - -/* Call this to change the selected language standard (e.g. because of - command line options). */ -extern void cpp_set_lang (cpp_reader *, enum c_lang); - -/* Set the include paths. */ -extern void cpp_set_include_chains (cpp_reader *, cpp_dir *, cpp_dir *, int); - -/* Call these to get pointers to the options, callback, and deps - structures for a given reader. These pointers are good until you - call cpp_finish on that reader. You can either edit the callbacks - through the pointer returned from cpp_get_callbacks, or set them - with cpp_set_callbacks. */ -extern cpp_options *cpp_get_options (cpp_reader *); -extern cpp_callbacks *cpp_get_callbacks (cpp_reader *); -extern void cpp_set_callbacks (cpp_reader *, cpp_callbacks *); -extern struct deps *cpp_get_deps (cpp_reader *); - -/* This function reads the file, but does not start preprocessing. It - returns the name of the original file; this is the same as the - input file, except for preprocessed input. This will generate at - least one file change callback, and possibly a line change callback - too. If there was an error opening the file, it returns NULL. */ -extern const char *cpp_read_main_file (cpp_reader *, const char *); - -/* Set up built-ins with special behavior. Use cpp_init_builtins() - instead unless your know what you are doing. */ -extern void cpp_init_special_builtins (cpp_reader *); - -/* Set up built-ins like __FILE__. */ -extern void cpp_init_builtins (cpp_reader *, int); - -/* This is called after options have been parsed, and partially - processed. */ -extern void cpp_post_options (cpp_reader *); - -/* Set up translation to the target character set. */ -extern void cpp_init_iconv (cpp_reader *); - -/* Call this to finish preprocessing. If you requested dependency - generation, pass an open stream to write the information to, - otherwise NULL. It is your responsibility to close the stream. */ -extern void cpp_finish (cpp_reader *, FILE *deps_stream); - -/* Call this to release the handle at the end of preprocessing. Any - use of the handle after this function returns is invalid. */ -extern void cpp_destroy (cpp_reader *); - -extern unsigned int cpp_token_len (const cpp_token *); -extern unsigned char *cpp_token_as_text (cpp_reader *, const cpp_token *); -extern unsigned char *cpp_spell_token (cpp_reader *, const cpp_token *, - unsigned char *, bool); -extern void cpp_register_pragma (cpp_reader *, const char *, const char *, - void (*) (cpp_reader *), bool); -extern void cpp_register_deferred_pragma (cpp_reader *, const char *, - const char *, unsigned, bool, bool); -extern int cpp_avoid_paste (cpp_reader *, const cpp_token *, - const cpp_token *); -extern const cpp_token *cpp_get_token (cpp_reader *); -extern const cpp_token *cpp_get_token_with_location (cpp_reader *, - source_location *); -extern bool cpp_fun_like_macro_p (cpp_hashnode *); -extern const unsigned char *cpp_macro_definition (cpp_reader *, - cpp_hashnode *); -extern void _cpp_backup_tokens (cpp_reader *, unsigned int); -extern const cpp_token *cpp_peek_token (cpp_reader *, int); - -/* Evaluate a CPP_*CHAR* token. */ -extern cppchar_t cpp_interpret_charconst (cpp_reader *, const cpp_token *, - unsigned int *, int *); -/* Evaluate a vector of CPP_*STRING* tokens. */ -extern bool cpp_interpret_string (cpp_reader *, - const cpp_string *, size_t, - cpp_string *, enum cpp_ttype); -extern bool cpp_interpret_string_notranslate (cpp_reader *, - const cpp_string *, size_t, - cpp_string *, enum cpp_ttype); - -/* Convert a host character constant to the execution character set. */ -extern cppchar_t cpp_host_to_exec_charset (cpp_reader *, cppchar_t); - -/* Used to register macros and assertions, perhaps from the command line. - The text is the same as the command line argument. */ -extern void cpp_define (cpp_reader *, const char *); -extern void cpp_define_formatted (cpp_reader *pfile, - const char *fmt, ...) ATTRIBUTE_PRINTF_2; -extern void cpp_assert (cpp_reader *, const char *); -extern void cpp_undef (cpp_reader *, const char *); -extern void cpp_unassert (cpp_reader *, const char *); - -/* Undefine all macros and assertions. */ -extern void cpp_undef_all (cpp_reader *); - -extern cpp_buffer *cpp_push_buffer (cpp_reader *, const unsigned char *, - size_t, int); -extern int cpp_defined (cpp_reader *, const unsigned char *, int); - -/* A preprocessing number. Code assumes that any unused high bits of - the double integer are set to zero. */ - -/* This type has to be equal to unsigned HOST_WIDE_INT, see - gcc/c-family/c-lex.c. */ -typedef uint64_t cpp_num_part; -typedef struct cpp_num cpp_num; -struct cpp_num -{ - cpp_num_part high; - cpp_num_part low; - bool unsignedp; /* True if value should be treated as unsigned. */ - bool overflow; /* True if the most recent calculation overflowed. */ -}; - -/* cpplib provides two interfaces for interpretation of preprocessing - numbers. - - cpp_classify_number categorizes numeric constants according to - their field (integer, floating point, or invalid), radix (decimal, - octal, hexadecimal), and type suffixes. */ - -#define CPP_N_CATEGORY 0x000F -#define CPP_N_INVALID 0x0000 -#define CPP_N_INTEGER 0x0001 -#define CPP_N_FLOATING 0x0002 - -#define CPP_N_WIDTH 0x00F0 -#define CPP_N_SMALL 0x0010 /* int, float, shrot _Fract/Accum */ -#define CPP_N_MEDIUM 0x0020 /* long, double, long _Fract/_Accum. */ -#define CPP_N_LARGE 0x0040 /* long long, long double, - long long _Fract/Accum. */ - -#define CPP_N_WIDTH_MD 0xF0000 /* machine defined. */ -#define CPP_N_MD_W 0x10000 -#define CPP_N_MD_Q 0x20000 - -#define CPP_N_RADIX 0x0F00 -#define CPP_N_DECIMAL 0x0100 -#define CPP_N_HEX 0x0200 -#define CPP_N_OCTAL 0x0400 -#define CPP_N_BINARY 0x0800 - -#define CPP_N_UNSIGNED 0x1000 /* Properties. */ -#define CPP_N_IMAGINARY 0x2000 -#define CPP_N_DFLOAT 0x4000 -#define CPP_N_DEFAULT 0x8000 - -#define CPP_N_FRACT 0x100000 /* Fract types. */ -#define CPP_N_ACCUM 0x200000 /* Accum types. */ - -#define CPP_N_USERDEF 0x1000000 /* C++0x user-defined literal. */ - -/* Classify a CPP_NUMBER token. The return value is a combination of - the flags from the above sets. */ -extern unsigned cpp_classify_number (cpp_reader *, const cpp_token *, - const char **, source_location); - -/* Return the classification flags for a float suffix. */ -extern unsigned int cpp_interpret_float_suffix (cpp_reader *, const char *, - size_t); - -/* Return the classification flags for an int suffix. */ -extern unsigned int cpp_interpret_int_suffix (cpp_reader *, const char *, - size_t); - -/* Evaluate a token classified as category CPP_N_INTEGER. */ -extern cpp_num cpp_interpret_integer (cpp_reader *, const cpp_token *, - unsigned int); - -/* Sign extend a number, with PRECISION significant bits and all - others assumed clear, to fill out a cpp_num structure. */ -cpp_num cpp_num_sign_extend (cpp_num, size_t); - -/* Diagnostic levels. To get a diagnostic without associating a - position in the translation unit with it, use cpp_error_with_line - with a line number of zero. */ - -enum { - /* Warning, an error with -Werror. */ - CPP_DL_WARNING = 0, - /* Same as CPP_DL_WARNING, except it is not suppressed in system headers. */ - CPP_DL_WARNING_SYSHDR, - /* Warning, an error with -pedantic-errors or -Werror. */ - CPP_DL_PEDWARN, - /* An error. */ - CPP_DL_ERROR, - /* An internal consistency check failed. Prints "internal error: ", - otherwise the same as CPP_DL_ERROR. */ - CPP_DL_ICE, - /* An informative note following a warning. */ - CPP_DL_NOTE, - /* A fatal error. */ - CPP_DL_FATAL -}; - -/* Warning reason codes. Use a reason code of zero for unclassified warnings - and errors that are not warnings. */ -enum { - CPP_W_NONE = 0, - CPP_W_DEPRECATED, - CPP_W_COMMENTS, - CPP_W_MISSING_INCLUDE_DIRS, - CPP_W_TRIGRAPHS, - CPP_W_MULTICHAR, - CPP_W_TRADITIONAL, - CPP_W_LONG_LONG, - CPP_W_ENDIF_LABELS, - CPP_W_NUM_SIGN_CHANGE, - CPP_W_VARIADIC_MACROS, - CPP_W_BUILTIN_MACRO_REDEFINED, - CPP_W_DOLLARS, - CPP_W_UNDEF, - CPP_W_UNUSED_MACROS, - CPP_W_CXX_OPERATOR_NAMES, - CPP_W_NORMALIZE, - CPP_W_INVALID_PCH, - CPP_W_WARNING_DIRECTIVE, - CPP_W_LITERAL_SUFFIX, - CPP_W_DATE_TIME, - CPP_W_PEDANTIC, - CPP_W_C90_C99_COMPAT -}; - -/* Output a diagnostic of some kind. */ -extern bool cpp_error (cpp_reader *, int, const char *msgid, ...) - ATTRIBUTE_PRINTF_3; -extern bool cpp_warning (cpp_reader *, int, const char *msgid, ...) - ATTRIBUTE_PRINTF_3; -extern bool cpp_pedwarning (cpp_reader *, int, const char *msgid, ...) - ATTRIBUTE_PRINTF_3; -extern bool cpp_warning_syshdr (cpp_reader *, int, const char *msgid, ...) - ATTRIBUTE_PRINTF_3; - -/* Output a diagnostic with "MSGID: " preceding the - error string of errno. No location is printed. */ -extern bool cpp_errno (cpp_reader *, int, const char *msgid); -/* Similarly, but with "FILENAME: " instead of "MSGID: ", where - the filename is not localized. */ -extern bool cpp_errno_filename (cpp_reader *, int, const char *filename); - -/* Same as cpp_error, except additionally specifies a position as a - (translation unit) physical line and physical column. If the line is - zero, then no location is printed. */ -extern bool cpp_error_with_line (cpp_reader *, int, source_location, - unsigned, const char *msgid, ...) - ATTRIBUTE_PRINTF_5; -extern bool cpp_warning_with_line (cpp_reader *, int, source_location, - unsigned, const char *msgid, ...) - ATTRIBUTE_PRINTF_5; -extern bool cpp_pedwarning_with_line (cpp_reader *, int, source_location, - unsigned, const char *msgid, ...) - ATTRIBUTE_PRINTF_5; -extern bool cpp_warning_with_line_syshdr (cpp_reader *, int, source_location, - unsigned, const char *msgid, ...) - ATTRIBUTE_PRINTF_5; - -/* In lex.c */ -extern int cpp_ideq (const cpp_token *, const char *); -extern void cpp_output_line (cpp_reader *, FILE *); -extern unsigned char *cpp_output_line_to_string (cpp_reader *, - const unsigned char *); -extern void cpp_output_token (const cpp_token *, FILE *); -extern const char *cpp_type2name (enum cpp_ttype, unsigned char flags); -/* Returns the value of an escape sequence, truncated to the correct - target precision. PSTR points to the input pointer, which is just - after the backslash. LIMIT is how much text we have. WIDE is true - if the escape sequence is part of a wide character constant or - string literal. Handles all relevant diagnostics. */ -extern cppchar_t cpp_parse_escape (cpp_reader *, const unsigned char ** pstr, - const unsigned char *limit, int wide); - -/* Structure used to hold a comment block at a given location in the - source code. */ - -typedef struct -{ - /* Text of the comment including the terminators. */ - char *comment; - - /* source location for the given comment. */ - source_location sloc; -} cpp_comment; - -/* Structure holding all comments for a given cpp_reader. */ - -typedef struct -{ - /* table of comment entries. */ - cpp_comment *entries; - - /* number of actual entries entered in the table. */ - int count; - - /* number of entries allocated currently. */ - int allocated; -} cpp_comment_table; - -/* Returns the table of comments encountered by the preprocessor. This - table is only populated when pfile->state.save_comments is true. */ -extern cpp_comment_table *cpp_get_comments (cpp_reader *); - -/* In hash.c */ - -/* Lookup an identifier in the hashtable. Puts the identifier in the - table if it is not already there. */ -extern cpp_hashnode *cpp_lookup (cpp_reader *, const unsigned char *, - unsigned int); - -typedef int (*cpp_cb) (cpp_reader *, cpp_hashnode *, void *); -extern void cpp_forall_identifiers (cpp_reader *, cpp_cb, void *); - -/* In macro.c */ -extern void cpp_scan_nooutput (cpp_reader *); -extern int cpp_sys_macro_p (cpp_reader *); -extern unsigned char *cpp_quote_string (unsigned char *, const unsigned char *, - unsigned int); - -/* In files.c */ -extern bool cpp_included (cpp_reader *, const char *); -extern bool cpp_included_before (cpp_reader *, const char *, source_location); -extern void cpp_make_system_header (cpp_reader *, int, int); -extern bool cpp_push_include (cpp_reader *, const char *); -extern bool cpp_push_default_include (cpp_reader *, const char *); -extern void cpp_change_file (cpp_reader *, enum lc_reason, const char *); -extern const char *cpp_get_path (struct _cpp_file *); -extern cpp_dir *cpp_get_dir (struct _cpp_file *); -extern cpp_buffer *cpp_get_buffer (cpp_reader *); -extern struct _cpp_file *cpp_get_file (cpp_buffer *); -extern cpp_buffer *cpp_get_prev (cpp_buffer *); -extern void cpp_clear_file_cache (cpp_reader *); - -/* In pch.c */ -struct save_macro_data; -extern int cpp_save_state (cpp_reader *, FILE *); -extern int cpp_write_pch_deps (cpp_reader *, FILE *); -extern int cpp_write_pch_state (cpp_reader *, FILE *); -extern int cpp_valid_state (cpp_reader *, const char *, int); -extern void cpp_prepare_state (cpp_reader *, struct save_macro_data **); -extern int cpp_read_state (cpp_reader *, const char *, FILE *, - struct save_macro_data *); - -/* In lex.c */ -extern void cpp_force_token_locations (cpp_reader *, source_location *); -extern void cpp_stop_forcing_token_locations (cpp_reader *); - -/* In expr.c */ -extern enum cpp_ttype cpp_userdef_string_remove_type - (enum cpp_ttype type); -extern enum cpp_ttype cpp_userdef_string_add_type - (enum cpp_ttype type); -extern enum cpp_ttype cpp_userdef_char_remove_type - (enum cpp_ttype type); -extern enum cpp_ttype cpp_userdef_char_add_type - (enum cpp_ttype type); -extern bool cpp_userdef_string_p - (enum cpp_ttype type); -extern bool cpp_userdef_char_p - (enum cpp_ttype type); -extern const char * cpp_get_userdef_suffix - (const cpp_token *); - -#endif /* ! LIBCPP_CPPLIB_H */ diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/cselib.h b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/cselib.h deleted file mode 100644 index c20f85f..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/cselib.h +++ /dev/null @@ -1,127 +0,0 @@ -/* Common subexpression elimination for GNU compiler. - Copyright (C) 1987-2015 Free Software Foundation, Inc. - -This file is part of GCC. - -GCC is free software; you can redistribute it and/or modify it under -the terms of the GNU General Public License as published by the Free -Software Foundation; either version 3, or (at your option) any later -version. - -GCC is distributed in the hope that it will be useful, but WITHOUT ANY -WARRANTY; without even the implied warranty of MERCHANTABILITY or -FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -for more details. - -You should have received a copy of the GNU General Public License -along with GCC; see the file COPYING3. If not see -. */ - -#ifndef GCC_CSELIB_H -#define GCC_CSELIB_H - -/* Describe a value. */ -struct cselib_val { - /* The hash value. */ - unsigned int hash; - - /* A unique id assigned to values. */ - int uid; - - /* A VALUE rtx that points back to this structure. */ - rtx val_rtx; - - /* All rtl expressions that hold this value at the current time during a - scan. */ - struct elt_loc_list *locs; - - /* If this value is used as an address, points to a list of values that - use it as an address in a MEM. */ - struct elt_list *addr_list; - - struct cselib_val *next_containing_mem; -}; - -/* A list of rtl expressions that hold the same value. */ -struct elt_loc_list { - /* Next element in the list. */ - struct elt_loc_list *next; - /* An rtl expression that holds the value. */ - rtx loc; - /* The insn that made the equivalence. */ - rtx_insn *setting_insn; -}; - -/* Describe a single set that is part of an insn. */ -struct cselib_set -{ - rtx src; - rtx dest; - cselib_val *src_elt; - cselib_val *dest_addr_elt; -}; - -enum cselib_record_what -{ - CSELIB_RECORD_MEMORY = 1, - CSELIB_PRESERVE_CONSTANTS = 2 -}; - -extern void (*cselib_discard_hook) (cselib_val *); -extern void (*cselib_record_sets_hook) (rtx_insn *insn, struct cselib_set *sets, - int n_sets); - -extern cselib_val *cselib_lookup (rtx, machine_mode, - int, machine_mode); -extern cselib_val *cselib_lookup_from_insn (rtx, machine_mode, - int, machine_mode, rtx_insn *); -extern void cselib_init (int); -extern void cselib_clear_table (void); -extern void cselib_finish (void); -extern void cselib_process_insn (rtx_insn *); -extern bool fp_setter_insn (rtx); -extern machine_mode cselib_reg_set_mode (const_rtx); -extern int rtx_equal_for_cselib_p (rtx, rtx); -extern int references_value_p (const_rtx, int); -extern rtx cselib_expand_value_rtx (rtx, bitmap, int); -typedef rtx (*cselib_expand_callback)(rtx, bitmap, int, void *); -extern rtx cselib_expand_value_rtx_cb (rtx, bitmap, int, - cselib_expand_callback, void *); -extern bool cselib_dummy_expand_value_rtx_cb (rtx, bitmap, int, - cselib_expand_callback, void *); -extern rtx cselib_subst_to_values (rtx, machine_mode); -extern rtx cselib_subst_to_values_from_insn (rtx, machine_mode, rtx_insn *); -extern void cselib_invalidate_rtx (rtx); - -extern void cselib_reset_table (unsigned int); -extern unsigned int cselib_get_next_uid (void); -extern void cselib_preserve_value (cselib_val *); -extern bool cselib_preserved_value_p (cselib_val *); -extern void cselib_preserve_only_values (void); -extern void cselib_preserve_cfa_base_value (cselib_val *, unsigned int); -extern void cselib_add_permanent_equiv (cselib_val *, rtx, rtx_insn *); -extern bool cselib_have_permanent_equivalences (void); -extern void cselib_set_value_sp_based (cselib_val *); -extern bool cselib_sp_based_value_p (cselib_val *); - -extern void dump_cselib_table (FILE *); - -/* Return the canonical value for VAL, following the equivalence chain - towards the earliest (== lowest uid) equivalent value. */ - -static inline cselib_val * -canonical_cselib_val (cselib_val *val) -{ - cselib_val *canon; - - if (!val->locs || val->locs->next - || !val->locs->loc || GET_CODE (val->locs->loc) != VALUE - || val->uid < CSELIB_VAL_PTR (val->locs->loc)->uid) - return val; - - canon = CSELIB_VAL_PTR (val->locs->loc); - gcc_checking_assert (canonical_cselib_val (canon) == canon); - return canon; -} - -#endif /* GCC_CSELIB_H */ diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/data-streamer.h b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/data-streamer.h deleted file mode 100644 index c26dda0..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/data-streamer.h +++ /dev/null @@ -1,320 +0,0 @@ -/* Generic streaming support for various data types. - - Copyright (C) 2011-2015 Free Software Foundation, Inc. - Contributed by Diego Novillo - -This file is part of GCC. - -GCC is free software; you can redistribute it and/or modify it under -the terms of the GNU General Public License as published by the Free -Software Foundation; either version 3, or (at your option) any later -version. - -GCC is distributed in the hope that it will be useful, but WITHOUT ANY -WARRANTY; without even the implied warranty of MERCHANTABILITY or -FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -for more details. - -You should have received a copy of the GNU General Public License -along with GCC; see the file COPYING3. If not see -. */ - -#ifndef GCC_DATA_STREAMER_H -#define GCC_DATA_STREAMER_H - -#include "vec.h" -#include "lto-streamer.h" - -/* Data structures used to pack values and bitflags into a vector of - words. Used to stream values of a fixed number of bits in a space - efficient way. */ -static unsigned const BITS_PER_BITPACK_WORD = HOST_BITS_PER_WIDE_INT; - -typedef unsigned HOST_WIDE_INT bitpack_word_t; - -struct bitpack_d -{ - /* The position of the first unused or unconsumed bit in the word. */ - unsigned pos; - - /* The current word we are (un)packing. */ - bitpack_word_t word; - - /* The lto_output_stream or the lto_input_block we are streaming to/from. */ - void *stream; -}; - -/* In data-streamer.c */ -void bp_pack_var_len_unsigned (struct bitpack_d *, unsigned HOST_WIDE_INT); -void bp_pack_var_len_int (struct bitpack_d *, HOST_WIDE_INT); -unsigned HOST_WIDE_INT bp_unpack_var_len_unsigned (struct bitpack_d *); -HOST_WIDE_INT bp_unpack_var_len_int (struct bitpack_d *); - -/* In data-streamer-out.c */ -void streamer_write_zero (struct output_block *); -void streamer_write_uhwi (struct output_block *, unsigned HOST_WIDE_INT); -void streamer_write_hwi (struct output_block *, HOST_WIDE_INT); -void streamer_write_gcov_count (struct output_block *, gcov_type); -void streamer_write_string (struct output_block *, struct lto_output_stream *, - const char *, bool); -void streamer_write_string_with_length (struct output_block *, - struct lto_output_stream *, - const char *, unsigned int, bool); -void bp_pack_string_with_length (struct output_block *, struct bitpack_d *, - const char *, unsigned int, bool); -void bp_pack_string (struct output_block *, struct bitpack_d *, - const char *, bool); -void streamer_write_uhwi_stream (struct lto_output_stream *, - unsigned HOST_WIDE_INT); -void streamer_write_hwi_stream (struct lto_output_stream *, HOST_WIDE_INT); -void streamer_write_gcov_count_stream (struct lto_output_stream *, gcov_type); -void streamer_write_data_stream (struct lto_output_stream *, const void *, - size_t); - -/* In data-streamer-in.c */ -const char *streamer_read_string (struct data_in *, struct lto_input_block *); -const char *streamer_read_indexed_string (struct data_in *, - struct lto_input_block *, - unsigned int *); -const char *bp_unpack_indexed_string (struct data_in *, struct bitpack_d *, - unsigned int *); -const char *bp_unpack_string (struct data_in *, struct bitpack_d *); -unsigned HOST_WIDE_INT streamer_read_uhwi (struct lto_input_block *); -HOST_WIDE_INT streamer_read_hwi (struct lto_input_block *); -gcov_type streamer_read_gcov_count (struct lto_input_block *); - -/* Returns a new bit-packing context for bit-packing into S. */ -static inline struct bitpack_d -bitpack_create (struct lto_output_stream *s) -{ - struct bitpack_d bp; - bp.pos = 0; - bp.word = 0; - bp.stream = (void *)s; - return bp; -} - -/* Pack the NBITS bit sized value VAL into the bit-packing context BP. */ -static inline void -bp_pack_value (struct bitpack_d *bp, bitpack_word_t val, unsigned nbits) -{ - bitpack_word_t word = bp->word; - int pos = bp->pos; - - /* Verify that VAL fits in the NBITS. */ - gcc_checking_assert (nbits == BITS_PER_BITPACK_WORD - || !(val & ~(((bitpack_word_t)1< BITS_PER_BITPACK_WORD) - { - streamer_write_uhwi_stream ((struct lto_output_stream *) bp->stream, - word); - word = val; - pos = nbits; - } - else - { - word |= val << pos; - pos += nbits; - } - bp->word = word; - bp->pos = pos; -} - -/* Finishes bit-packing of BP. */ -static inline void -streamer_write_bitpack (struct bitpack_d *bp) -{ - streamer_write_uhwi_stream ((struct lto_output_stream *) bp->stream, - bp->word); - bp->word = 0; - bp->pos = 0; -} - -/* Returns a new bit-packing context for bit-unpacking from IB. */ -static inline struct bitpack_d -streamer_read_bitpack (struct lto_input_block *ib) -{ - struct bitpack_d bp; - bp.word = streamer_read_uhwi (ib); - bp.pos = 0; - bp.stream = (void *)ib; - return bp; -} - -/* Unpacks NBITS bits from the bit-packing context BP and returns them. */ -static inline bitpack_word_t -bp_unpack_value (struct bitpack_d *bp, unsigned nbits) -{ - bitpack_word_t mask, val; - int pos = bp->pos; - - mask = (nbits == BITS_PER_BITPACK_WORD - ? (bitpack_word_t) -1 - : ((bitpack_word_t) 1 << nbits) - 1); - - /* If there are not continuous nbits in the current bitpack word - switch to the next one. */ - if (pos + nbits > BITS_PER_BITPACK_WORD) - { - bp->word = val - = streamer_read_uhwi ((struct lto_input_block *)bp->stream); - bp->pos = nbits; - return val & mask; - } - val = bp->word; - val >>= pos; - bp->pos = pos + nbits; - - return val & mask; -} - - -/* Write a character to the output block. */ - -static inline void -streamer_write_char_stream (struct lto_output_stream *obs, char c) -{ - /* No space left. */ - if (obs->left_in_block == 0) - lto_append_block (obs); - - /* Write the actual character. */ - char *current_pointer = obs->current_pointer; - *(current_pointer++) = c; - obs->current_pointer = current_pointer; - obs->total_size++; - obs->left_in_block--; -} - - -/* Read byte from the input block. */ - -static inline unsigned char -streamer_read_uchar (struct lto_input_block *ib) -{ - if (ib->p >= ib->len) - lto_section_overrun (ib); - return (ib->data[ib->p++]); -} - -/* Output VAL into OBS and verify it is in range MIN...MAX that is supposed - to be compile time constant. - Be host independent, limit range to 31bits. */ - -static inline void -streamer_write_hwi_in_range (struct lto_output_stream *obs, - HOST_WIDE_INT min, - HOST_WIDE_INT max, - HOST_WIDE_INT val) -{ - HOST_WIDE_INT range = max - min; - - gcc_checking_assert (val >= min && val <= max && range > 0 - && range < 0x7fffffff); - - val -= min; - streamer_write_uhwi_stream (obs, (unsigned HOST_WIDE_INT) val); -} - -/* Input VAL into OBS and verify it is in range MIN...MAX that is supposed - to be compile time constant. PURPOSE is used for error reporting. */ - -static inline HOST_WIDE_INT -streamer_read_hwi_in_range (struct lto_input_block *ib, - const char *purpose, - HOST_WIDE_INT min, - HOST_WIDE_INT max) -{ - HOST_WIDE_INT range = max - min; - unsigned HOST_WIDE_INT uval = streamer_read_uhwi (ib); - - gcc_checking_assert (range > 0 && range < 0x7fffffff); - - HOST_WIDE_INT val = (HOST_WIDE_INT) (uval + (unsigned HOST_WIDE_INT) min); - if (val < min || val > max) - lto_value_range_error (purpose, val, min, max); - return val; -} - -/* Output VAL into BP and verify it is in range MIN...MAX that is supposed - to be compile time constant. - Be host independent, limit range to 31bits. */ - -static inline void -bp_pack_int_in_range (struct bitpack_d *bp, - HOST_WIDE_INT min, - HOST_WIDE_INT max, - HOST_WIDE_INT val) -{ - HOST_WIDE_INT range = max - min; - int nbits = floor_log2 (range) + 1; - - gcc_checking_assert (val >= min && val <= max && range > 0 - && range < 0x7fffffff); - - val -= min; - bp_pack_value (bp, val, nbits); -} - -/* Input VAL into BP and verify it is in range MIN...MAX that is supposed - to be compile time constant. PURPOSE is used for error reporting. */ - -static inline HOST_WIDE_INT -bp_unpack_int_in_range (struct bitpack_d *bp, - const char *purpose, - HOST_WIDE_INT min, - HOST_WIDE_INT max) -{ - HOST_WIDE_INT range = max - min; - int nbits = floor_log2 (range) + 1; - HOST_WIDE_INT val = bp_unpack_value (bp, nbits); - - gcc_checking_assert (range > 0 && range < 0x7fffffff); - - if (val < min || val > max) - lto_value_range_error (purpose, val, min, max); - return val; -} - -/* Output VAL of type "enum enum_name" into OBS. - Assume range 0...ENUM_LAST - 1. */ -#define streamer_write_enum(obs,enum_name,enum_last,val) \ - streamer_write_hwi_in_range ((obs), 0, (int)(enum_last) - 1, (int)(val)) - -/* Input enum of type "enum enum_name" from IB. - Assume range 0...ENUM_LAST - 1. */ -#define streamer_read_enum(ib,enum_name,enum_last) \ - (enum enum_name)streamer_read_hwi_in_range ((ib), #enum_name, 0, \ - (int)(enum_last) - 1) - -/* Output VAL of type "enum enum_name" into BP. - Assume range 0...ENUM_LAST - 1. */ -#define bp_pack_enum(bp,enum_name,enum_last,val) \ - bp_pack_int_in_range ((bp), 0, (int)(enum_last) - 1, (int)(val)) - -/* Input enum of type "enum enum_name" from BP. - Assume range 0...ENUM_LAST - 1. */ -#define bp_unpack_enum(bp,enum_name,enum_last) \ - (enum enum_name)bp_unpack_int_in_range ((bp), #enum_name, 0, \ - (int)(enum_last) - 1) - -/* Output the start of a record with TAG to output block OB. */ - -static inline void -streamer_write_record_start (struct output_block *ob, enum LTO_tags tag) -{ - streamer_write_enum (ob->main_stream, LTO_tags, LTO_NUM_TAGS, tag); -} - -/* Return the next tag in the input block IB. */ - -static inline enum LTO_tags -streamer_read_record_start (struct lto_input_block *ib) -{ - return streamer_read_enum (ib, LTO_tags, LTO_NUM_TAGS); -} - -#endif /* GCC_DATA_STREAMER_H */ diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/dbgcnt.def b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/dbgcnt.def deleted file mode 100644 index 4b26e77..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/dbgcnt.def +++ /dev/null @@ -1,192 +0,0 @@ -/* This file contains the list of the debug counter for GCC. - Copyright (C) 2006-2015 Free Software Foundation, Inc. - -This file is part of GCC. - -GCC is free software; you can redistribute it and/or modify it under -the terms of the GNU General Public License as published by the Free -Software Foundation; either version 3, or (at your option) any later -version. - -GCC is distributed in the hope that it will be useful, but WITHOUT ANY -WARRANTY; without even the implied warranty of MERCHANTABILITY or -FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -for more details. - -You should have received a copy of the GNU General Public License -along with GCC; see the file COPYING3. If not see -. */ - - -/* A debug counter provides you a way to count an event - and return false after the counter has exceeded the threshold - specified by the option. - - What is it used for ? - - This is primarily used to speed up the search for the bad transformation - an optimization pass does. By doing a binary search on N, - you can quickly narrow down to one transformation - which is bad, or which triggers the bad behavior downstream - (usually in the form of the badly generated code). - - How does it work ? - - Every time dbg_cnt(named-counter) is called, - the counter is incremented for the named-counter. - And the incremented value is compared against the threshold (limit) - specified by the option. - dbg_cnt () returns true if it is at or below threshold, and false if above. - - How to add a new one ? - - To add a new counter, simply add an entry below with some descriptive name, - and add call(s) to dbg_cnt(your-counter-name) in appropriate places. - Usually, you want to control at the finest granularity - any particular transformation can happen. - e.g. for each instruction in a dead code elimination, - or for each copy instruction in register coalescing, - or constant-propagation for each insn, - or a block straightening, etc. - See dce.c for an example. With the dbg_cnt () call in dce.c, - now a developer can use -fdbg-cnt=dce:N - to stop doing the dead code elimination after N times. - - How to use it ? - - By default, all limits are UINT_MAX. - Since debug count is unsigned int, <= UINT_MAX returns true always. - i.e. dbg_cnt() returns true always regardless of the counter value - (although it still counts the event). - Use -fdbg-cnt=counter1:N,counter2:M,... - which sets the limit for counter1 to N, and the limit for counter2 to M, etc. - e.g. setting a limit to zero will make dbg_cnt () return false *always*. - - The following shell file can then be used to binary search for - exact transformation that causes the bug. A second shell script - should be written, say "tryTest", which exits with 1 if the - compiled program fails and exits with 0 if the program succeeds. - This shell script should take 1 parameter, the value to be passed - to set the counter of the compilation command in tryTest. Then, - assuming that the following script is called binarySearch, - the command: - - binarySearch tryTest - - will automatically find the highest value of the counter for which - the program fails. If tryTest never fails, binarySearch will - produce unpredictable results as it will try to find an upper bound - that does not exist. - - When dbgcnt does hits the limit, it writes a comment in the current - dump_file of the form: - - ***dbgcnt: limit reached for %s.*** - - Assuming that the dump file is logging the analysis/transformations - it is making, this pinpoints the exact position in the log file - where the problem transformation is being logged. - -===================================== -#!/bin/bash - -while getopts "l:u:i:" opt -do - case $opt in - l) lb="$OPTARG";; - u) ub="$OPTARG";; - i) init="$OPTARG";; - ?) usage; exit 3;; - esac -done - -shift $(($OPTIND - 1)) -echo $@ -cmd=${1+"${@}"} - -lb=${lb:=0} -init=${init:=100} - -$cmd $lb -lb_val=$? -if [ -z "$ub" ]; then - # find the upper bound - ub=$(($init + $lb)) - true - while [ $? -eq $lb_val ]; do - ub=$(($ub * 10)) - #ub=`expr $ub \* 10` - $cmd $ub - done -fi - -echo command: $cmd - -true -while [ `expr $ub - $lb` -gt 1 ]; do - try=$(($lb + ( $ub - $lb ) / 2)) - $cmd $try - if [ $? -eq $lb_val ]; then - lb=$try - else - ub=$try - fi -done - -echo lbound: $lb -echo ubound: $ub - -===================================== - -*/ - -/* Debug counter definitions. */ -DEBUG_COUNTER (auto_inc_dec) -DEBUG_COUNTER (ccp) -DEBUG_COUNTER (cfg_cleanup) -DEBUG_COUNTER (cse2_move2add) -DEBUG_COUNTER (cprop) -DEBUG_COUNTER (dce) -DEBUG_COUNTER (dce_fast) -DEBUG_COUNTER (dce_ud) -DEBUG_COUNTER (delete_trivial_dead) -DEBUG_COUNTER (devirt) -DEBUG_COUNTER (df_byte_scan) -DEBUG_COUNTER (dse) -DEBUG_COUNTER (dse1) -DEBUG_COUNTER (dse2) -DEBUG_COUNTER (gcse2_delete) -DEBUG_COUNTER (global_alloc_at_func) -DEBUG_COUNTER (global_alloc_at_reg) -DEBUG_COUNTER (graphite_scop) -DEBUG_COUNTER (hoist) -DEBUG_COUNTER (hoist_insn) -DEBUG_COUNTER (ia64_sched2) -DEBUG_COUNTER (if_conversion) -DEBUG_COUNTER (if_conversion_tree) -DEBUG_COUNTER (if_after_combine) -DEBUG_COUNTER (if_after_reload) -DEBUG_COUNTER (local_alloc_for_sched) -DEBUG_COUNTER (postreload_cse) -DEBUG_COUNTER (pre) -DEBUG_COUNTER (pre_insn) -DEBUG_COUNTER (treepre_insert) -DEBUG_COUNTER (tree_sra) -DEBUG_COUNTER (eipa_sra) -DEBUG_COUNTER (vect_loop) -DEBUG_COUNTER (vect_slp) -DEBUG_COUNTER (sched2_func) -DEBUG_COUNTER (sched_block) -DEBUG_COUNTER (sched_func) -DEBUG_COUNTER (sched_insn) -DEBUG_COUNTER (sched_breakdep) -DEBUG_COUNTER (sched_region) -DEBUG_COUNTER (sel_sched_cnt) -DEBUG_COUNTER (sel_sched_region_cnt) -DEBUG_COUNTER (sel_sched_insn_cnt) -DEBUG_COUNTER (sms_sched_loop) -DEBUG_COUNTER (store_motion) -DEBUG_COUNTER (split_for_sched2) -DEBUG_COUNTER (tail_call) -DEBUG_COUNTER (ira_move) -DEBUG_COUNTER (registered_jump_thread) diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/dbgcnt.h b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/dbgcnt.h deleted file mode 100644 index e924bc7..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/dbgcnt.h +++ /dev/null @@ -1,39 +0,0 @@ -/* Debug counter for debugging support - Copyright (C) 2006-2015 Free Software Foundation, Inc. - -This file is part of GCC. - -GCC is free software; you can redistribute it and/or modify it under -the terms of the GNU General Public License as published by the Free -Software Foundation; either version 3, or (at your option) any later -version. - -GCC is distributed in the hope that it will be useful, but WITHOUT ANY -WARRANTY; without even the implied warranty of MERCHANTABILITY or -FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -for more details. - -You should have received a copy of the GNU General Public License -along with GCC; see the file COPYING3. If not see -. - -See dbgcnt.def for usage information. */ - -#ifndef GCC_DBGCNT_H -#define GCC_DBGCNT_H - -#define DEBUG_COUNTER(a) a, - -enum debug_counter { -#include "dbgcnt.def" - debug_counter_number_of_counters -}; - -#undef DEBUG_COUNTER - -extern bool dbg_cnt_is_enabled (enum debug_counter index); -extern bool dbg_cnt (enum debug_counter index); -extern void dbg_cnt_process_opt (const char *arg); -extern void dbg_cnt_list_all_counters (void); - -#endif /* GCC_DBGCNT_H */ diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/dbxout.h b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/dbxout.h deleted file mode 100644 index 098213f..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/dbxout.h +++ /dev/null @@ -1,61 +0,0 @@ -/* dbxout.h - Various declarations for functions found in dbxout.c - Copyright (C) 1998-2015 Free Software Foundation, Inc. - -This file is part of GCC. - -GCC is free software; you can redistribute it and/or modify it under -the terms of the GNU General Public License as published by the Free -Software Foundation; either version 3, or (at your option) any later -version. - -GCC is distributed in the hope that it will be useful, but WITHOUT ANY -WARRANTY; without even the implied warranty of MERCHANTABILITY or -FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -for more details. - -You should have received a copy of the GNU General Public License -along with GCC; see the file COPYING3. If not see -. */ - -#ifndef GCC_DBXOUT_H -#define GCC_DBXOUT_H - -extern int dbxout_symbol (tree, int); -extern void dbxout_parms (tree); -extern void dbxout_reg_parms (tree); -extern int dbxout_syms (tree); - -extern void default_stabs_asm_out_destructor (rtx, int); -extern void default_stabs_asm_out_constructor (rtx, int); - -/* dbxout helper functions */ -#if defined DBX_DEBUGGING_INFO || defined XCOFF_DEBUGGING_INFO - -extern void dbxout_int (int); -extern void dbxout_stabd (int, int); -extern void dbxout_begin_stabn (int); -extern void dbxout_begin_stabn_sline (int); -extern void dbxout_begin_empty_stabs (int); -extern void dbxout_begin_simple_stabs (const char *, int); -extern void dbxout_begin_simple_stabs_desc (const char *, int, int); - -extern void dbxout_stab_value_zero (void); -extern void dbxout_stab_value_label (const char *); -extern void dbxout_stab_value_label_diff (const char *, const char *); -extern void dbxout_stab_value_internal_label (const char *, int *); -extern void dbxout_stab_value_internal_label_diff (const char *, int *, - const char *); -#endif - -/* Language description for N_SO stabs. */ -#define N_SO_AS 1 -#define N_SO_C 2 -#define N_SO_ANSI_C 3 -#define N_SO_CC 4 /* c++*/ -#define N_SO_FORTRAN 5 -#define N_SO_PASCAL 6 -#define N_SO_FORTRAN90 7 -#define N_SO_OBJC 50 -#define N_SO_OBJCPLUS 51 - -#endif /* GCC_DBXOUT_H */ diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/dce.h b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/dce.h deleted file mode 100644 index 39abbb1..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/dce.h +++ /dev/null @@ -1,27 +0,0 @@ -/* RTL dead code elimination. - Copyright (C) 2005-2015 Free Software Foundation, Inc. - -This file is part of GCC. - -GCC is free software; you can redistribute it and/or modify it under -the terms of the GNU General Public License as published by the Free -Software Foundation; either version 3, or (at your option) any later -version. - -GCC is distributed in the hope that it will be useful, but WITHOUT ANY -WARRANTY; without even the implied warranty of MERCHANTABILITY or -FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License - for more details. - -You should have received a copy of the GNU General Public License -along with GCC; see the file COPYING3. If not see -. */ - -#ifndef GCC_DCE_H -#define GCC_DCE_H - -extern void run_word_dce (void); -extern void run_fast_dce (void); -extern void run_fast_df_dce (void); - -#endif /* GCC_DCE_H */ diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/ddg.h b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/ddg.h deleted file mode 100644 index 28413ce..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/ddg.h +++ /dev/null @@ -1,185 +0,0 @@ -/* DDG - Data Dependence Graph - interface. - Copyright (C) 2004-2015 Free Software Foundation, Inc. - Contributed by Ayal Zaks and Mustafa Hagog - -This file is part of GCC. - -GCC is free software; you can redistribute it and/or modify it under -the terms of the GNU General Public License as published by the Free -Software Foundation; either version 3, or (at your option) any later -version. - -GCC is distributed in the hope that it will be useful, but WITHOUT ANY -WARRANTY; without even the implied warranty of MERCHANTABILITY or -FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -for more details. - -You should have received a copy of the GNU General Public License -along with GCC; see the file COPYING3. If not see -. */ - -#ifndef GCC_DDG_H -#define GCC_DDG_H - -/* For sbitmap. */ - -typedef struct ddg_node *ddg_node_ptr; -typedef struct ddg_edge *ddg_edge_ptr; -typedef struct ddg *ddg_ptr; -typedef struct ddg_scc *ddg_scc_ptr; -typedef struct ddg_all_sccs *ddg_all_sccs_ptr; - -enum dep_type {TRUE_DEP, OUTPUT_DEP, ANTI_DEP}; -enum dep_data_type {REG_OR_MEM_DEP, REG_DEP, MEM_DEP, REG_AND_MEM_DEP}; - -/* The following two macros enables direct access to the successors and - predecessors bitmaps held in each ddg_node. Do not make changes to - these bitmaps, unless you want to change the DDG. */ -#define NODE_SUCCESSORS(x) ((x)->successors) -#define NODE_PREDECESSORS(x) ((x)->predecessors) - -/* A structure that represents a node in the DDG. */ -struct ddg_node -{ - /* Each node has a unique CUID index. These indices increase monotonically - (according to the order of the corresponding INSN in the BB), starting - from 0 with no gaps. */ - int cuid; - - /* The insn represented by the node. */ - rtx_insn *insn; - - /* A note preceding INSN (or INSN itself), such that all insns linked - from FIRST_NOTE until INSN (inclusive of both) are moved together - when reordering the insns. This takes care of notes that should - continue to precede INSN. */ - rtx_insn *first_note; - - /* Incoming and outgoing dependency edges. */ - ddg_edge_ptr in; - ddg_edge_ptr out; - - /* Each bit corresponds to a ddg_node according to its cuid, and is - set iff the node is a successor/predecessor of "this" node. */ - sbitmap successors; - sbitmap predecessors; - - /* For general use by algorithms manipulating the ddg. */ - union { - int count; - void *info; - } aux; -}; - -/* A structure that represents an edge in the DDG. */ -struct ddg_edge -{ - /* The source and destination nodes of the dependency edge. */ - ddg_node_ptr src; - ddg_node_ptr dest; - - /* TRUE, OUTPUT or ANTI dependency. */ - dep_type type; - - /* REG or MEM dependency. */ - dep_data_type data_type; - - /* Latency of the dependency. */ - int latency; - - /* The distance: number of loop iterations the dependency crosses. */ - int distance; - - /* The following two fields are used to form a linked list of the in/out - going edges to/from each node. */ - ddg_edge_ptr next_in; - ddg_edge_ptr next_out; - - /* For general use by algorithms manipulating the ddg. */ - union { - int count; - void *info; - } aux; -}; - -/* This structure holds the Data Dependence Graph for a basic block. */ -struct ddg -{ - /* The basic block for which this DDG is built. */ - basic_block bb; - - /* Number of instructions in the basic block. */ - int num_nodes; - - /* Number of load/store instructions in the BB - statistics. */ - int num_loads; - int num_stores; - - /* Number of debug instructions in the BB. */ - int num_debug; - - /* This array holds the nodes in the graph; it is indexed by the node - cuid, which follows the order of the instructions in the BB. */ - ddg_node_ptr nodes; - - /* The branch closing the loop. */ - ddg_node_ptr closing_branch; - - /* Build dependence edges for closing_branch, when set. In certain cases, - the closing branch can be dealt with separately from the insns of the - loop, and then no such deps are needed. */ - int closing_branch_deps; - - /* Array and number of backarcs (edges with distance > 0) in the DDG. */ - int num_backarcs; - ddg_edge_ptr *backarcs; -}; - - -/* Holds information on an SCC (Strongly Connected Component) of the DDG. */ -struct ddg_scc -{ - /* A bitmap that represents the nodes of the DDG that are in the SCC. */ - sbitmap nodes; - - /* Array and number of backarcs (edges with distance > 0) in the SCC. */ - ddg_edge_ptr *backarcs; - int num_backarcs; - - /* The maximum of (total_latency/total_distance) over all cycles in SCC. */ - int recurrence_length; -}; - -/* This structure holds the SCCs of the DDG. */ -struct ddg_all_sccs -{ - /* Array that holds the SCCs in the DDG, and their number. */ - ddg_scc_ptr *sccs; - int num_sccs; - - ddg_ptr ddg; -}; - - -ddg_ptr create_ddg (basic_block, int closing_branch_deps); -void free_ddg (ddg_ptr); - -void print_ddg (FILE *, ddg_ptr); -void vcg_print_ddg (FILE *, ddg_ptr); -void print_ddg_edge (FILE *, ddg_edge_ptr); -void print_sccs (FILE *, ddg_all_sccs_ptr, ddg_ptr); - -ddg_node_ptr get_node_of_insn (ddg_ptr, rtx_insn *); - -void find_successors (sbitmap result, ddg_ptr, sbitmap); -void find_predecessors (sbitmap result, ddg_ptr, sbitmap); - -ddg_all_sccs_ptr create_ddg_all_sccs (ddg_ptr); -void free_ddg_all_sccs (ddg_all_sccs_ptr); - -int find_nodes_on_paths (sbitmap result, ddg_ptr, sbitmap from, sbitmap to); -int longest_simple_path (ddg_ptr, int from, int to, sbitmap via); - -bool autoinc_var_is_used_p (rtx_insn *, rtx_insn *); - -#endif /* GCC_DDG_H */ diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/debug.h b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/debug.h deleted file mode 100644 index 82634c6..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/debug.h +++ /dev/null @@ -1,199 +0,0 @@ -/* Debug hooks for GCC. - Copyright (C) 2001-2015 Free Software Foundation, Inc. - - This program is free software; you can redistribute it and/or modify it - under the terms of the GNU General Public License as published by the - Free Software Foundation; either version 3, or (at your option) any - later version. - - This program is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program; see the file COPYING3. If not see - . */ - -#ifndef GCC_DEBUG_H -#define GCC_DEBUG_H - -/* This structure contains hooks for the debug information output - functions, accessed through the global instance debug_hooks set in - toplev.c according to command line options. */ -struct gcc_debug_hooks -{ - /* Initialize debug output. MAIN_FILENAME is the name of the main - input file. */ - void (* init) (const char *main_filename); - - /* Output debug symbols. */ - void (* finish) (const char *main_filename); - - /* Called from cgraph_optimize before starting to assemble - functions/variables/toplevel asms. */ - void (* assembly_start) (void); - - /* Macro defined on line LINE with name and expansion TEXT. */ - void (* define) (unsigned int line, const char *text); - - /* MACRO undefined on line LINE. */ - void (* undef) (unsigned int line, const char *macro); - - /* Record the beginning of a new source file FILE from LINE number - in the previous one. */ - void (* start_source_file) (unsigned int line, const char *file); - - /* Record the resumption of a source file. LINE is the line number - in the source file we are returning to. */ - void (* end_source_file) (unsigned int line); - - /* Record the beginning of block N, counting from 1 and not - including the function-scope block, at LINE. */ - void (* begin_block) (unsigned int line, unsigned int n); - - /* Record the end of a block. Arguments as for begin_block. */ - void (* end_block) (unsigned int line, unsigned int n); - - /* Returns nonzero if it is appropriate not to emit any debugging - information for BLOCK, because it doesn't contain any - instructions. This may not be the case for blocks containing - nested functions, since we may actually call such a function even - though the BLOCK information is messed up. Defaults to true. */ - bool (* ignore_block) (const_tree); - - /* Record a source file location at (FILE, LINE, DISCRIMINATOR). */ - void (* source_line) (unsigned int line, const char *file, - int discriminator, bool is_stmt); - - /* Called at start of prologue code. LINE is the first line in the - function. */ - void (* begin_prologue) (unsigned int line, const char *file); - - /* Called at end of prologue code. LINE is the first line in the - function. */ - void (* end_prologue) (unsigned int line, const char *file); - - /* Called at beginning of epilogue code. */ - void (* begin_epilogue) (unsigned int line, const char *file); - - /* Record end of epilogue code. */ - void (* end_epilogue) (unsigned int line, const char *file); - - /* Called at start of function DECL, before it is declared. */ - void (* begin_function) (tree decl); - - /* Record end of function. LINE is highest line number in function. */ - void (* end_function) (unsigned int line); - - /* Register UNIT as the main translation unit. Called from front-ends when - they create their main translation unit. */ - void (* register_main_translation_unit) (tree); - - /* Debug information for a function DECL. This might include the - function name (a symbol), its parameters, and the block that - makes up the function's body, and the local variables of the - function. */ - void (* function_decl) (tree decl); - - /* Debug information for a global DECL. Called from toplev.c after - compilation proper has finished. */ - void (* global_decl) (tree decl); - - /* Debug information for a type DECL. Called from toplev.c after - compilation proper, also from various language front ends to - record built-in types. The second argument is properly a - boolean, which indicates whether or not the type is a "local" - type as determined by the language. (It's not a boolean for - legacy reasons.) */ - void (* type_decl) (tree decl, int local); - - /* Debug information for imported modules and declarations. */ - void (* imported_module_or_decl) (tree decl, tree name, - tree context, bool child); - - /* DECL is an inline function, whose body is present, but which is - not being output at this point. */ - void (* deferred_inline_function) (tree decl); - - /* DECL is an inline function which is about to be emitted out of - line. The hook is useful to, e.g., emit abstract debug info for - the inline before it gets mangled by optimization. */ - void (* outlining_inline_function) (tree decl); - - /* Called from final_scan_insn for any CODE_LABEL insn whose - LABEL_NAME is non-null. */ - void (* label) (rtx_code_label *); - - /* Called after the start and before the end of writing a PCH file. - The parameter is 0 if after the start, 1 if before the end. */ - void (* handle_pch) (unsigned int); - - /* Called from final_scan_insn for any NOTE_INSN_VAR_LOCATION note. */ - void (* var_location) (rtx_insn *); - - /* Called from final_scan_insn if there is a switch between hot and cold - text sections. */ - void (* switch_text_section) (void); - - /* Called from grokdeclarator. Replaces the anonymous name with the - type name. */ - void (* set_name) (tree, tree); - - /* This is 1 if the debug writer wants to see start and end commands for the - main source files, and 0 otherwise. */ - int start_end_main_source_file; - - /* The type of symtab field used by these debug hooks. This is one - of the TYPE_SYMTAB_IS_xxx values defined in tree.h. */ - int tree_type_symtab_field; -}; - -extern const struct gcc_debug_hooks *debug_hooks; - -/* The do-nothing hooks. */ -extern void debug_nothing_void (void); -extern void debug_nothing_charstar (const char *); -extern void debug_nothing_int_charstar (unsigned int, const char *); -extern void debug_nothing_int_charstar_int_bool (unsigned int, const char *, - int, bool); -extern void debug_nothing_int (unsigned int); -extern void debug_nothing_int_int (unsigned int, unsigned int); -extern void debug_nothing_tree (tree); -extern void debug_nothing_tree_tree (tree, tree); -extern void debug_nothing_tree_int (tree, int); -extern void debug_nothing_tree_tree_tree_bool (tree, tree, tree, bool); -extern bool debug_true_const_tree (const_tree); -extern void debug_nothing_rtx_insn (rtx_insn *); -extern void debug_nothing_rtx_code_label (rtx_code_label *); - -/* Hooks for various debug formats. */ -extern const struct gcc_debug_hooks do_nothing_debug_hooks; -extern const struct gcc_debug_hooks dbx_debug_hooks; -extern const struct gcc_debug_hooks sdb_debug_hooks; -extern const struct gcc_debug_hooks xcoff_debug_hooks; -extern const struct gcc_debug_hooks dwarf2_debug_hooks; -extern const struct gcc_debug_hooks vmsdbg_debug_hooks; - -/* Dwarf2 frame information. */ - -extern void dwarf2out_begin_prologue (unsigned int, const char *); -extern void dwarf2out_vms_end_prologue (unsigned int, const char *); -extern void dwarf2out_vms_begin_epilogue (unsigned int, const char *); -extern void dwarf2out_end_epilogue (unsigned int, const char *); -extern void dwarf2out_frame_finish (void); -/* Decide whether we want to emit frame unwind information for the current - translation unit. */ -extern bool dwarf2out_do_frame (void); -extern bool dwarf2out_do_cfi_asm (void); -extern void dwarf2out_switch_text_section (void); - -const char *remap_debug_filename (const char *); -void add_debug_prefix_map (const char *); - -/* For -fdump-go-spec. */ - -extern const struct gcc_debug_hooks * -dump_go_spec_init (const char *, const struct gcc_debug_hooks *); - -#endif /* !GCC_DEBUG_H */ diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/defaults.h b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/defaults.h deleted file mode 100644 index 1d54798..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/defaults.h +++ /dev/null @@ -1,1364 +0,0 @@ -/* Definitions of various defaults for tm.h macros. - Copyright (C) 1992-2015 Free Software Foundation, Inc. - Contributed by Ron Guilmette (rfg@monkeys.com) - -This file is part of GCC. - -GCC is free software; you can redistribute it and/or modify it under -the terms of the GNU General Public License as published by the Free -Software Foundation; either version 3, or (at your option) any later -version. - -GCC is distributed in the hope that it will be useful, but WITHOUT ANY -WARRANTY; without even the implied warranty of MERCHANTABILITY or -FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -for more details. - -Under Section 7 of GPL version 3, you are granted additional -permissions described in the GCC Runtime Library Exception, version -3.1, as published by the Free Software Foundation. - -You should have received a copy of the GNU General Public License and -a copy of the GCC Runtime Library Exception along with this program; -see the files COPYING3 and COPYING.RUNTIME respectively. If not, see -. */ - -#ifndef GCC_DEFAULTS_H -#define GCC_DEFAULTS_H - -/* How to start an assembler comment. */ -#ifndef ASM_COMMENT_START -#define ASM_COMMENT_START ";#" -#endif - -/* Store in OUTPUT a string (made with alloca) containing an - assembler-name for a local static variable or function named NAME. - LABELNO is an integer which is different for each call. */ - -#ifndef ASM_PN_FORMAT -# ifndef NO_DOT_IN_LABEL -# define ASM_PN_FORMAT "%s.%lu" -# else -# ifndef NO_DOLLAR_IN_LABEL -# define ASM_PN_FORMAT "%s$%lu" -# else -# define ASM_PN_FORMAT "__%s_%lu" -# endif -# endif -#endif /* ! ASM_PN_FORMAT */ - -#ifndef ASM_FORMAT_PRIVATE_NAME -# define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO) \ - do { const char *const name_ = (NAME); \ - char *const output_ = (OUTPUT) = \ - (char *) alloca (strlen (name_) + 32); \ - sprintf (output_, ASM_PN_FORMAT, name_, (unsigned long)(LABELNO)); \ - } while (0) -#endif - -/* Choose a reasonable default for ASM_OUTPUT_ASCII. */ - -#ifndef ASM_OUTPUT_ASCII -#define ASM_OUTPUT_ASCII(MYFILE, MYSTRING, MYLENGTH) \ - do { \ - FILE *_hide_asm_out_file = (MYFILE); \ - const unsigned char *_hide_p = (const unsigned char *) (MYSTRING); \ - int _hide_thissize = (MYLENGTH); \ - { \ - FILE *asm_out_file = _hide_asm_out_file; \ - const unsigned char *p = _hide_p; \ - int thissize = _hide_thissize; \ - int i; \ - fprintf (asm_out_file, "\t.ascii \""); \ - \ - for (i = 0; i < thissize; i++) \ - { \ - int c = p[i]; \ - if (c == '\"' || c == '\\') \ - putc ('\\', asm_out_file); \ - if (ISPRINT (c)) \ - putc (c, asm_out_file); \ - else \ - { \ - fprintf (asm_out_file, "\\%o", c); \ - /* After an octal-escape, if a digit follows, \ - terminate one string constant and start another. \ - The VAX assembler fails to stop reading the escape \ - after three digits, so this is the only way we \ - can get it to parse the data properly. */ \ - if (i < thissize - 1 && ISDIGIT (p[i + 1])) \ - fprintf (asm_out_file, "\"\n\t.ascii \""); \ - } \ - } \ - fprintf (asm_out_file, "\"\n"); \ - } \ - } \ - while (0) -#endif - -/* This is how we tell the assembler to equate two values. */ -#ifdef SET_ASM_OP -#ifndef ASM_OUTPUT_DEF -#define ASM_OUTPUT_DEF(FILE,LABEL1,LABEL2) \ - do { fprintf ((FILE), "%s", SET_ASM_OP); \ - assemble_name (FILE, LABEL1); \ - fprintf (FILE, ","); \ - assemble_name (FILE, LABEL2); \ - fprintf (FILE, "\n"); \ - } while (0) -#endif -#endif - -#ifndef IFUNC_ASM_TYPE -#define IFUNC_ASM_TYPE "gnu_indirect_function" -#endif - -#ifndef TLS_COMMON_ASM_OP -#define TLS_COMMON_ASM_OP ".tls_common" -#endif - -#if defined (HAVE_AS_TLS) && !defined (ASM_OUTPUT_TLS_COMMON) -#define ASM_OUTPUT_TLS_COMMON(FILE, DECL, NAME, SIZE) \ - do \ - { \ - fprintf ((FILE), "\t%s\t", TLS_COMMON_ASM_OP); \ - assemble_name ((FILE), (NAME)); \ - fprintf ((FILE), ","HOST_WIDE_INT_PRINT_UNSIGNED",%u\n", \ - (SIZE), DECL_ALIGN (DECL) / BITS_PER_UNIT); \ - } \ - while (0) -#endif - -/* Decide whether to defer emitting the assembler output for an equate - of two values. The default is to not defer output. */ -#ifndef TARGET_DEFERRED_OUTPUT_DEFS -#define TARGET_DEFERRED_OUTPUT_DEFS(DECL,TARGET) false -#endif - -/* This is how to output the definition of a user-level label named - NAME, such as the label on variable NAME. */ - -#ifndef ASM_OUTPUT_LABEL -#define ASM_OUTPUT_LABEL(FILE,NAME) \ - do { \ - assemble_name ((FILE), (NAME)); \ - fputs (":\n", (FILE)); \ - } while (0) -#endif - -/* This is how to output the definition of a user-level label named - NAME, such as the label on a function. */ - -#ifndef ASM_OUTPUT_FUNCTION_LABEL -#define ASM_OUTPUT_FUNCTION_LABEL(FILE, NAME, DECL) \ - ASM_OUTPUT_LABEL ((FILE), (NAME)) -#endif - -/* Output the definition of a compiler-generated label named NAME. */ -#ifndef ASM_OUTPUT_INTERNAL_LABEL -#define ASM_OUTPUT_INTERNAL_LABEL(FILE,NAME) \ - do { \ - assemble_name_raw ((FILE), (NAME)); \ - fputs (":\n", (FILE)); \ - } while (0) -#endif - -/* This is how to output a reference to a user-level label named NAME. */ - -#ifndef ASM_OUTPUT_LABELREF -#define ASM_OUTPUT_LABELREF(FILE,NAME) \ - do { \ - fputs (user_label_prefix, (FILE)); \ - fputs ((NAME), (FILE)); \ - } while (0); -#endif - -/* Allow target to print debug info labels specially. This is useful for - VLIW targets, since debug info labels should go into the middle of - instruction bundles instead of breaking them. */ - -#ifndef ASM_OUTPUT_DEBUG_LABEL -#define ASM_OUTPUT_DEBUG_LABEL(FILE, PREFIX, NUM) \ - (*targetm.asm_out.internal_label) (FILE, PREFIX, NUM) -#endif - -/* This is how we tell the assembler that a symbol is weak. */ -#ifndef ASM_OUTPUT_WEAK_ALIAS -#if defined (ASM_WEAKEN_LABEL) && defined (ASM_OUTPUT_DEF) -#define ASM_OUTPUT_WEAK_ALIAS(STREAM, NAME, VALUE) \ - do \ - { \ - ASM_WEAKEN_LABEL (STREAM, NAME); \ - if (VALUE) \ - ASM_OUTPUT_DEF (STREAM, NAME, VALUE); \ - } \ - while (0) -#endif -#endif - -/* This is how we tell the assembler that a symbol is a weak alias to - another symbol that doesn't require the other symbol to be defined. - Uses of the former will turn into weak uses of the latter, i.e., - uses that, in case the latter is undefined, will not cause errors, - and will add it to the symbol table as weak undefined. However, if - the latter is referenced directly, a strong reference prevails. */ -#ifndef ASM_OUTPUT_WEAKREF -#if defined HAVE_GAS_WEAKREF -#define ASM_OUTPUT_WEAKREF(FILE, DECL, NAME, VALUE) \ - do \ - { \ - fprintf ((FILE), "\t.weakref\t"); \ - assemble_name ((FILE), (NAME)); \ - fprintf ((FILE), ","); \ - assemble_name ((FILE), (VALUE)); \ - fprintf ((FILE), "\n"); \ - } \ - while (0) -#endif -#endif - -/* How to emit a .type directive. */ -#ifndef ASM_OUTPUT_TYPE_DIRECTIVE -#if defined TYPE_ASM_OP && defined TYPE_OPERAND_FMT -#define ASM_OUTPUT_TYPE_DIRECTIVE(STREAM, NAME, TYPE) \ - do \ - { \ - fputs (TYPE_ASM_OP, STREAM); \ - assemble_name (STREAM, NAME); \ - fputs (", ", STREAM); \ - fprintf (STREAM, TYPE_OPERAND_FMT, TYPE); \ - putc ('\n', STREAM); \ - } \ - while (0) -#endif -#endif - -/* How to emit a .size directive. */ -#ifndef ASM_OUTPUT_SIZE_DIRECTIVE -#ifdef SIZE_ASM_OP -#define ASM_OUTPUT_SIZE_DIRECTIVE(STREAM, NAME, SIZE) \ - do \ - { \ - HOST_WIDE_INT size_ = (SIZE); \ - fputs (SIZE_ASM_OP, STREAM); \ - assemble_name (STREAM, NAME); \ - fprintf (STREAM, ", " HOST_WIDE_INT_PRINT_DEC "\n", size_); \ - } \ - while (0) - -#define ASM_OUTPUT_MEASURED_SIZE(STREAM, NAME) \ - do \ - { \ - fputs (SIZE_ASM_OP, STREAM); \ - assemble_name (STREAM, NAME); \ - fputs (", .-", STREAM); \ - assemble_name (STREAM, NAME); \ - putc ('\n', STREAM); \ - } \ - while (0) - -#endif -#endif - -/* This determines whether or not we support weak symbols. SUPPORTS_WEAK - must be a preprocessor constant. */ -#ifndef SUPPORTS_WEAK -#if defined (ASM_WEAKEN_LABEL) || defined (ASM_WEAKEN_DECL) -#define SUPPORTS_WEAK 1 -#else -#define SUPPORTS_WEAK 0 -#endif -#endif - -/* This determines whether or not we support weak symbols during target - code generation. TARGET_SUPPORTS_WEAK can be any valid C expression. */ -#ifndef TARGET_SUPPORTS_WEAK -#define TARGET_SUPPORTS_WEAK (SUPPORTS_WEAK) -#endif - -/* This determines whether or not we support the discriminator - attribute in the .loc directive. */ -#ifndef SUPPORTS_DISCRIMINATOR -#ifdef HAVE_GAS_DISCRIMINATOR -#define SUPPORTS_DISCRIMINATOR 1 -#else -#define SUPPORTS_DISCRIMINATOR 0 -#endif -#endif - -/* This determines whether or not we support link-once semantics. */ -#ifndef SUPPORTS_ONE_ONLY -#ifdef MAKE_DECL_ONE_ONLY -#define SUPPORTS_ONE_ONLY 1 -#else -#define SUPPORTS_ONE_ONLY 0 -#endif -#endif - -/* This determines whether weak symbols must be left out of a static - archive's table of contents. Defining this macro to be nonzero has - the consequence that certain symbols will not be made weak that - otherwise would be. The C++ ABI requires this macro to be zero; - see the documentation. */ -#ifndef TARGET_WEAK_NOT_IN_ARCHIVE_TOC -#define TARGET_WEAK_NOT_IN_ARCHIVE_TOC 0 -#endif - -/* This determines whether or not we need linkonce unwind information. */ -#ifndef TARGET_USES_WEAK_UNWIND_INFO -#define TARGET_USES_WEAK_UNWIND_INFO 0 -#endif - -/* By default, there is no prefix on user-defined symbols. */ -#ifndef USER_LABEL_PREFIX -#define USER_LABEL_PREFIX "" -#endif - -/* If the target supports weak symbols, define TARGET_ATTRIBUTE_WEAK to - provide a weak attribute. Else define it to nothing. - - This would normally belong in ansidecl.h, but SUPPORTS_WEAK is - not available at that time. - - Note, this is only for use by target files which we know are to be - compiled by GCC. */ -#ifndef TARGET_ATTRIBUTE_WEAK -# if SUPPORTS_WEAK -# define TARGET_ATTRIBUTE_WEAK __attribute__ ((weak)) -# else -# define TARGET_ATTRIBUTE_WEAK -# endif -#endif - -/* By default we can assume that all global symbols are in one namespace, - across all shared libraries. */ -#ifndef MULTIPLE_SYMBOL_SPACES -# define MULTIPLE_SYMBOL_SPACES 0 -#endif - -/* If the target supports init_priority C++ attribute, give - SUPPORTS_INIT_PRIORITY a nonzero value. */ -#ifndef SUPPORTS_INIT_PRIORITY -#define SUPPORTS_INIT_PRIORITY 1 -#endif /* SUPPORTS_INIT_PRIORITY */ - -/* If we have a definition of INCOMING_RETURN_ADDR_RTX, assume that - the rest of the DWARF 2 frame unwind support is also provided. */ -#if !defined (DWARF2_UNWIND_INFO) && defined (INCOMING_RETURN_ADDR_RTX) -#define DWARF2_UNWIND_INFO 1 -#endif - -/* If we have named sections, and we're using crtstuff to run ctors, - use them for registering eh frame information. */ -#if defined (TARGET_ASM_NAMED_SECTION) && DWARF2_UNWIND_INFO \ - && !defined (EH_FRAME_IN_DATA_SECTION) -#ifndef EH_FRAME_SECTION_NAME -#define EH_FRAME_SECTION_NAME ".eh_frame" -#endif -#endif - -/* On many systems, different EH table encodings are used under - difference circumstances. Some will require runtime relocations; - some will not. For those that do not require runtime relocations, - we would like to make the table read-only. However, since the - read-only tables may need to be combined with read-write tables - that do require runtime relocation, it is not safe to make the - tables read-only unless the linker will merge read-only and - read-write sections into a single read-write section. If your - linker does not have this ability, but your system is such that no - encoding used with non-PIC code will ever require a runtime - relocation, then you can define EH_TABLES_CAN_BE_READ_ONLY to 1 in - your target configuration file. */ -#ifndef EH_TABLES_CAN_BE_READ_ONLY -#ifdef HAVE_LD_RO_RW_SECTION_MIXING -#define EH_TABLES_CAN_BE_READ_ONLY 1 -#else -#define EH_TABLES_CAN_BE_READ_ONLY 0 -#endif -#endif - -/* If we have named section and we support weak symbols, then use the - .jcr section for recording java classes which need to be registered - at program start-up time. */ -#if defined (TARGET_ASM_NAMED_SECTION) && SUPPORTS_WEAK -#ifndef JCR_SECTION_NAME -#define JCR_SECTION_NAME ".jcr" -#endif -#endif - -/* This decision to use a .jcr section can be overridden by defining - USE_JCR_SECTION to 0 in target file. This is necessary if target - can define JCR_SECTION_NAME but does not have crtstuff or - linker support for .jcr section. */ -#ifndef TARGET_USE_JCR_SECTION -#ifdef JCR_SECTION_NAME -#define TARGET_USE_JCR_SECTION 1 -#else -#define TARGET_USE_JCR_SECTION 0 -#endif -#endif - -/* Number of hardware registers that go into the DWARF-2 unwind info. - If not defined, equals FIRST_PSEUDO_REGISTER */ - -#ifndef DWARF_FRAME_REGISTERS -#define DWARF_FRAME_REGISTERS FIRST_PSEUDO_REGISTER -#endif - -/* Offsets recorded in opcodes are a multiple of this alignment factor. */ -#ifndef DWARF_CIE_DATA_ALIGNMENT -#ifdef STACK_GROWS_DOWNWARD -#define DWARF_CIE_DATA_ALIGNMENT (-((int) UNITS_PER_WORD)) -#else -#define DWARF_CIE_DATA_ALIGNMENT ((int) UNITS_PER_WORD) -#endif -#endif - -/* The DWARF 2 CFA column which tracks the return address. Normally this - is the column for PC, or the first column after all of the hard - registers. */ -#ifndef DWARF_FRAME_RETURN_COLUMN -#ifdef PC_REGNUM -#define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (PC_REGNUM) -#else -#define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGISTERS -#endif -#endif - -/* How to renumber registers for dbx and gdb. If not defined, assume - no renumbering is necessary. */ - -#ifndef DBX_REGISTER_NUMBER -#define DBX_REGISTER_NUMBER(REGNO) (REGNO) -#endif - -/* The mapping from gcc register number to DWARF 2 CFA column number. - By default, we just provide columns for all registers. */ -#ifndef DWARF_FRAME_REGNUM -#define DWARF_FRAME_REGNUM(REG) DBX_REGISTER_NUMBER (REG) -#endif - -/* The mapping from dwarf CFA reg number to internal dwarf reg numbers. */ -#ifndef DWARF_REG_TO_UNWIND_COLUMN -#define DWARF_REG_TO_UNWIND_COLUMN(REGNO) (REGNO) -#endif - -/* Map register numbers held in the call frame info that gcc has - collected using DWARF_FRAME_REGNUM to those that should be output in - .debug_frame and .eh_frame. */ -#ifndef DWARF2_FRAME_REG_OUT -#define DWARF2_FRAME_REG_OUT(REGNO, FOR_EH) (REGNO) -#endif - -/* The size of addresses as they appear in the Dwarf 2 data. - Some architectures use word addresses to refer to code locations, - but Dwarf 2 info always uses byte addresses. On such machines, - Dwarf 2 addresses need to be larger than the architecture's - pointers. */ -#ifndef DWARF2_ADDR_SIZE -#define DWARF2_ADDR_SIZE ((POINTER_SIZE + BITS_PER_UNIT - 1) / BITS_PER_UNIT) -#endif - -/* The size in bytes of a DWARF field indicating an offset or length - relative to a debug info section, specified to be 4 bytes in the - DWARF-2 specification. The SGI/MIPS ABI defines it to be the same - as PTR_SIZE. */ -#ifndef DWARF_OFFSET_SIZE -#define DWARF_OFFSET_SIZE 4 -#endif - -/* The size in bytes of a DWARF 4 type signature. */ -#ifndef DWARF_TYPE_SIGNATURE_SIZE -#define DWARF_TYPE_SIGNATURE_SIZE 8 -#endif - -/* Default sizes for base C types. If the sizes are different for - your target, you should override these values by defining the - appropriate symbols in your tm.h file. */ - -#if BITS_PER_UNIT == 8 -#define LOG2_BITS_PER_UNIT 3 -#elif BITS_PER_UNIT == 16 -#define LOG2_BITS_PER_UNIT 4 -#else -#error Unknown BITS_PER_UNIT -#endif - -#ifndef BITS_PER_WORD -#define BITS_PER_WORD (BITS_PER_UNIT * UNITS_PER_WORD) -#endif - -#ifndef CHAR_TYPE_SIZE -#define CHAR_TYPE_SIZE BITS_PER_UNIT -#endif - -#ifndef BOOL_TYPE_SIZE -/* `bool' has size and alignment `1', on almost all platforms. */ -#define BOOL_TYPE_SIZE CHAR_TYPE_SIZE -#endif - -#ifndef SHORT_TYPE_SIZE -#define SHORT_TYPE_SIZE (BITS_PER_UNIT * MIN ((UNITS_PER_WORD + 1) / 2, 2)) -#endif - -#ifndef INT_TYPE_SIZE -#define INT_TYPE_SIZE BITS_PER_WORD -#endif - -#ifndef LONG_TYPE_SIZE -#define LONG_TYPE_SIZE BITS_PER_WORD -#endif - -#ifndef LONG_LONG_TYPE_SIZE -#define LONG_LONG_TYPE_SIZE (BITS_PER_WORD * 2) -#endif - -#ifndef WCHAR_TYPE_SIZE -#define WCHAR_TYPE_SIZE INT_TYPE_SIZE -#endif - -#ifndef FLOAT_TYPE_SIZE -#define FLOAT_TYPE_SIZE BITS_PER_WORD -#endif - -#ifndef DOUBLE_TYPE_SIZE -#define DOUBLE_TYPE_SIZE (BITS_PER_WORD * 2) -#endif - -#ifndef LONG_DOUBLE_TYPE_SIZE -#define LONG_DOUBLE_TYPE_SIZE (BITS_PER_WORD * 2) -#endif - -#ifndef DECIMAL32_TYPE_SIZE -#define DECIMAL32_TYPE_SIZE 32 -#endif - -#ifndef DECIMAL64_TYPE_SIZE -#define DECIMAL64_TYPE_SIZE 64 -#endif - -#ifndef DECIMAL128_TYPE_SIZE -#define DECIMAL128_TYPE_SIZE 128 -#endif - -#ifndef SHORT_FRACT_TYPE_SIZE -#define SHORT_FRACT_TYPE_SIZE BITS_PER_UNIT -#endif - -#ifndef FRACT_TYPE_SIZE -#define FRACT_TYPE_SIZE (BITS_PER_UNIT * 2) -#endif - -#ifndef LONG_FRACT_TYPE_SIZE -#define LONG_FRACT_TYPE_SIZE (BITS_PER_UNIT * 4) -#endif - -#ifndef LONG_LONG_FRACT_TYPE_SIZE -#define LONG_LONG_FRACT_TYPE_SIZE (BITS_PER_UNIT * 8) -#endif - -#ifndef SHORT_ACCUM_TYPE_SIZE -#define SHORT_ACCUM_TYPE_SIZE (SHORT_FRACT_TYPE_SIZE * 2) -#endif - -#ifndef ACCUM_TYPE_SIZE -#define ACCUM_TYPE_SIZE (FRACT_TYPE_SIZE * 2) -#endif - -#ifndef LONG_ACCUM_TYPE_SIZE -#define LONG_ACCUM_TYPE_SIZE (LONG_FRACT_TYPE_SIZE * 2) -#endif - -#ifndef LONG_LONG_ACCUM_TYPE_SIZE -#define LONG_LONG_ACCUM_TYPE_SIZE (LONG_LONG_FRACT_TYPE_SIZE * 2) -#endif - -/* We let tm.h override the types used here, to handle trivial differences - such as the choice of unsigned int or long unsigned int for size_t. - When machines start needing nontrivial differences in the size type, - it would be best to do something here to figure out automatically - from other information what type to use. */ - -#ifndef SIZE_TYPE -#define SIZE_TYPE "long unsigned int" -#endif - -#ifndef SIZETYPE -#define SIZETYPE SIZE_TYPE -#endif - -#ifndef PID_TYPE -#define PID_TYPE "int" -#endif - -/* If GCC knows the exact uint_least16_t and uint_least32_t types from - , use them for char16_t and char32_t. Otherwise, use - these guesses; getting the wrong type of a given width will not - affect C++ name mangling because in C++ these are distinct types - not typedefs. */ - -#ifdef UINT_LEAST16_TYPE -#define CHAR16_TYPE UINT_LEAST16_TYPE -#else -#define CHAR16_TYPE "short unsigned int" -#endif - -#ifdef UINT_LEAST32_TYPE -#define CHAR32_TYPE UINT_LEAST32_TYPE -#else -#define CHAR32_TYPE "unsigned int" -#endif - -#ifndef WCHAR_TYPE -#define WCHAR_TYPE "int" -#endif - -/* WCHAR_TYPE gets overridden by -fshort-wchar. */ -#define MODIFIED_WCHAR_TYPE \ - (flag_short_wchar ? "short unsigned int" : WCHAR_TYPE) - -#ifndef PTRDIFF_TYPE -#define PTRDIFF_TYPE "long int" -#endif - -#ifndef WINT_TYPE -#define WINT_TYPE "unsigned int" -#endif - -#ifndef INTMAX_TYPE -#define INTMAX_TYPE ((INT_TYPE_SIZE == LONG_LONG_TYPE_SIZE) \ - ? "int" \ - : ((LONG_TYPE_SIZE == LONG_LONG_TYPE_SIZE) \ - ? "long int" \ - : "long long int")) -#endif - -#ifndef UINTMAX_TYPE -#define UINTMAX_TYPE ((INT_TYPE_SIZE == LONG_LONG_TYPE_SIZE) \ - ? "unsigned int" \ - : ((LONG_TYPE_SIZE == LONG_LONG_TYPE_SIZE) \ - ? "long unsigned int" \ - : "long long unsigned int")) -#endif - - -/* There are no default definitions of these types. */ - -#ifndef SIG_ATOMIC_TYPE -#define SIG_ATOMIC_TYPE ((const char *) NULL) -#endif - -#ifndef INT8_TYPE -#define INT8_TYPE ((const char *) NULL) -#endif - -#ifndef INT16_TYPE -#define INT16_TYPE ((const char *) NULL) -#endif - -#ifndef INT32_TYPE -#define INT32_TYPE ((const char *) NULL) -#endif - -#ifndef INT64_TYPE -#define INT64_TYPE ((const char *) NULL) -#endif - -#ifndef UINT8_TYPE -#define UINT8_TYPE ((const char *) NULL) -#endif - -#ifndef UINT16_TYPE -#define UINT16_TYPE ((const char *) NULL) -#endif - -#ifndef UINT32_TYPE -#define UINT32_TYPE ((const char *) NULL) -#endif - -#ifndef UINT64_TYPE -#define UINT64_TYPE ((const char *) NULL) -#endif - -#ifndef INT_LEAST8_TYPE -#define INT_LEAST8_TYPE ((const char *) NULL) -#endif - -#ifndef INT_LEAST16_TYPE -#define INT_LEAST16_TYPE ((const char *) NULL) -#endif - -#ifndef INT_LEAST32_TYPE -#define INT_LEAST32_TYPE ((const char *) NULL) -#endif - -#ifndef INT_LEAST64_TYPE -#define INT_LEAST64_TYPE ((const char *) NULL) -#endif - -#ifndef UINT_LEAST8_TYPE -#define UINT_LEAST8_TYPE ((const char *) NULL) -#endif - -#ifndef UINT_LEAST16_TYPE -#define UINT_LEAST16_TYPE ((const char *) NULL) -#endif - -#ifndef UINT_LEAST32_TYPE -#define UINT_LEAST32_TYPE ((const char *) NULL) -#endif - -#ifndef UINT_LEAST64_TYPE -#define UINT_LEAST64_TYPE ((const char *) NULL) -#endif - -#ifndef INT_FAST8_TYPE -#define INT_FAST8_TYPE ((const char *) NULL) -#endif - -#ifndef INT_FAST16_TYPE -#define INT_FAST16_TYPE ((const char *) NULL) -#endif - -#ifndef INT_FAST32_TYPE -#define INT_FAST32_TYPE ((const char *) NULL) -#endif - -#ifndef INT_FAST64_TYPE -#define INT_FAST64_TYPE ((const char *) NULL) -#endif - -#ifndef UINT_FAST8_TYPE -#define UINT_FAST8_TYPE ((const char *) NULL) -#endif - -#ifndef UINT_FAST16_TYPE -#define UINT_FAST16_TYPE ((const char *) NULL) -#endif - -#ifndef UINT_FAST32_TYPE -#define UINT_FAST32_TYPE ((const char *) NULL) -#endif - -#ifndef UINT_FAST64_TYPE -#define UINT_FAST64_TYPE ((const char *) NULL) -#endif - -#ifndef INTPTR_TYPE -#define INTPTR_TYPE ((const char *) NULL) -#endif - -#ifndef UINTPTR_TYPE -#define UINTPTR_TYPE ((const char *) NULL) -#endif - -/* Width in bits of a pointer. Mind the value of the macro `Pmode'. */ -#ifndef POINTER_SIZE -#define POINTER_SIZE BITS_PER_WORD -#endif -#ifndef POINTER_SIZE_UNITS -#define POINTER_SIZE_UNITS ((POINTER_SIZE + BITS_PER_UNIT - 1) / BITS_PER_UNIT) -#endif - - -#ifndef PIC_OFFSET_TABLE_REGNUM -#define PIC_OFFSET_TABLE_REGNUM INVALID_REGNUM -#endif - -#ifndef PIC_OFFSET_TABLE_REG_CALL_CLOBBERED -#define PIC_OFFSET_TABLE_REG_CALL_CLOBBERED 0 -#endif - -#ifndef TARGET_DLLIMPORT_DECL_ATTRIBUTES -#define TARGET_DLLIMPORT_DECL_ATTRIBUTES 0 -#endif - -#ifndef TARGET_DECLSPEC -#if TARGET_DLLIMPORT_DECL_ATTRIBUTES -/* If the target supports the "dllimport" attribute, users are - probably used to the "__declspec" syntax. */ -#define TARGET_DECLSPEC 1 -#else -#define TARGET_DECLSPEC 0 -#endif -#endif - -/* By default, the preprocessor should be invoked the same way in C++ - as in C. */ -#ifndef CPLUSPLUS_CPP_SPEC -#ifdef CPP_SPEC -#define CPLUSPLUS_CPP_SPEC CPP_SPEC -#endif -#endif - -#ifndef ACCUMULATE_OUTGOING_ARGS -#define ACCUMULATE_OUTGOING_ARGS 0 -#endif - -/* By default, use the GNU runtime for Objective C. */ -#ifndef NEXT_OBJC_RUNTIME -#define NEXT_OBJC_RUNTIME 0 -#endif - -/* Supply a default definition for PUSH_ARGS. */ -#ifndef PUSH_ARGS -#ifdef PUSH_ROUNDING -#define PUSH_ARGS !ACCUMULATE_OUTGOING_ARGS -#else -#define PUSH_ARGS 0 -#endif -#endif - -/* Decide whether a function's arguments should be processed - from first to last or from last to first. - - They should if the stack and args grow in opposite directions, but - only if we have push insns. */ - -#ifdef PUSH_ROUNDING - -#ifndef PUSH_ARGS_REVERSED -#if defined (STACK_GROWS_DOWNWARD) != defined (ARGS_GROW_DOWNWARD) -#define PUSH_ARGS_REVERSED PUSH_ARGS -#endif -#endif - -#endif - -#ifndef PUSH_ARGS_REVERSED -#define PUSH_ARGS_REVERSED 0 -#endif - -/* Default value for the alignment (in bits) a C conformant malloc has to - provide. This default is intended to be safe and always correct. */ -#ifndef MALLOC_ABI_ALIGNMENT -#define MALLOC_ABI_ALIGNMENT BITS_PER_WORD -#endif - -/* If PREFERRED_STACK_BOUNDARY is not defined, set it to STACK_BOUNDARY. - STACK_BOUNDARY is required. */ -#ifndef PREFERRED_STACK_BOUNDARY -#define PREFERRED_STACK_BOUNDARY STACK_BOUNDARY -#endif - -/* Set INCOMING_STACK_BOUNDARY to PREFERRED_STACK_BOUNDARY if it is not - defined. */ -#ifndef INCOMING_STACK_BOUNDARY -#define INCOMING_STACK_BOUNDARY PREFERRED_STACK_BOUNDARY -#endif - -#ifndef TARGET_DEFAULT_PACK_STRUCT -#define TARGET_DEFAULT_PACK_STRUCT 0 -#endif - -/* By default, the vtable entries are void pointers, the so the alignment - is the same as pointer alignment. The value of this macro specifies - the alignment of the vtable entry in bits. It should be defined only - when special alignment is necessary. */ -#ifndef TARGET_VTABLE_ENTRY_ALIGN -#define TARGET_VTABLE_ENTRY_ALIGN POINTER_SIZE -#endif - -/* There are a few non-descriptor entries in the vtable at offsets below - zero. If these entries must be padded (say, to preserve the alignment - specified by TARGET_VTABLE_ENTRY_ALIGN), set this to the number of - words in each data entry. */ -#ifndef TARGET_VTABLE_DATA_ENTRY_DISTANCE -#define TARGET_VTABLE_DATA_ENTRY_DISTANCE 1 -#endif - -/* Decide whether it is safe to use a local alias for a virtual function - when constructing thunks. */ -#ifndef TARGET_USE_LOCAL_THUNK_ALIAS_P -#ifdef ASM_OUTPUT_DEF -#define TARGET_USE_LOCAL_THUNK_ALIAS_P(DECL) 1 -#else -#define TARGET_USE_LOCAL_THUNK_ALIAS_P(DECL) 0 -#endif -#endif - -/* Select a format to encode pointers in exception handling data. We - prefer those that result in fewer dynamic relocations. Assume no - special support here and encode direct references. */ -#ifndef ASM_PREFERRED_EH_DATA_FORMAT -#define ASM_PREFERRED_EH_DATA_FORMAT(CODE,GLOBAL) DW_EH_PE_absptr -#endif - -/* By default, the C++ compiler will use the lowest bit of the pointer - to function to indicate a pointer-to-member-function points to a - virtual member function. However, if FUNCTION_BOUNDARY indicates - function addresses aren't always even, the lowest bit of the delta - field will be used. */ -#ifndef TARGET_PTRMEMFUNC_VBIT_LOCATION -#define TARGET_PTRMEMFUNC_VBIT_LOCATION \ - (FUNCTION_BOUNDARY >= 2 * BITS_PER_UNIT \ - ? ptrmemfunc_vbit_in_pfn : ptrmemfunc_vbit_in_delta) -#endif - -#ifndef DEFAULT_GDB_EXTENSIONS -#define DEFAULT_GDB_EXTENSIONS 1 -#endif - -/* If more than one debugging type is supported, you must define - PREFERRED_DEBUGGING_TYPE to choose the default. */ - -#if 1 < (defined (DBX_DEBUGGING_INFO) + defined (SDB_DEBUGGING_INFO) \ - + defined (DWARF2_DEBUGGING_INFO) + defined (XCOFF_DEBUGGING_INFO) \ - + defined (VMS_DEBUGGING_INFO)) -#ifndef PREFERRED_DEBUGGING_TYPE -#error You must define PREFERRED_DEBUGGING_TYPE -#endif /* no PREFERRED_DEBUGGING_TYPE */ - -/* If only one debugging format is supported, define PREFERRED_DEBUGGING_TYPE - here so other code needn't care. */ -#elif defined DBX_DEBUGGING_INFO -#define PREFERRED_DEBUGGING_TYPE DBX_DEBUG - -#elif defined SDB_DEBUGGING_INFO -#define PREFERRED_DEBUGGING_TYPE SDB_DEBUG - -#elif defined DWARF2_DEBUGGING_INFO -#define PREFERRED_DEBUGGING_TYPE DWARF2_DEBUG - -#elif defined VMS_DEBUGGING_INFO -#define PREFERRED_DEBUGGING_TYPE VMS_AND_DWARF2_DEBUG - -#elif defined XCOFF_DEBUGGING_INFO -#define PREFERRED_DEBUGGING_TYPE XCOFF_DEBUG - -#else -/* No debugging format is supported by this target. */ -#define PREFERRED_DEBUGGING_TYPE NO_DEBUG -#endif - -#ifndef FLOAT_LIB_COMPARE_RETURNS_BOOL -#define FLOAT_LIB_COMPARE_RETURNS_BOOL(MODE, COMPARISON) false -#endif - -/* True if the targets integer-comparison functions return { 0, 1, 2 - } to indicate { <, ==, > }. False if { -1, 0, 1 } is used - instead. The libgcc routines are biased. */ -#ifndef TARGET_LIB_INT_CMP_BIASED -#define TARGET_LIB_INT_CMP_BIASED (true) -#endif - -/* If FLOAT_WORDS_BIG_ENDIAN is not defined in the header files, - then the word-endianness is the same as for integers. */ -#ifndef FLOAT_WORDS_BIG_ENDIAN -#define FLOAT_WORDS_BIG_ENDIAN WORDS_BIG_ENDIAN -#endif - -#ifndef REG_WORDS_BIG_ENDIAN -#define REG_WORDS_BIG_ENDIAN WORDS_BIG_ENDIAN -#endif - -#ifdef TARGET_FLT_EVAL_METHOD -#define TARGET_FLT_EVAL_METHOD_NON_DEFAULT 1 -#else -#define TARGET_FLT_EVAL_METHOD 0 -#define TARGET_FLT_EVAL_METHOD_NON_DEFAULT 0 -#endif - -#ifndef TARGET_DEC_EVAL_METHOD -#define TARGET_DEC_EVAL_METHOD 2 -#endif - -#ifndef HAS_LONG_COND_BRANCH -#define HAS_LONG_COND_BRANCH 0 -#endif - -#ifndef HAS_LONG_UNCOND_BRANCH -#define HAS_LONG_UNCOND_BRANCH 0 -#endif - -/* Determine whether __cxa_atexit, rather than atexit, is used to - register C++ destructors for local statics and global objects. */ -#ifndef DEFAULT_USE_CXA_ATEXIT -#define DEFAULT_USE_CXA_ATEXIT 0 -#endif - -#if GCC_VERSION >= 3000 && defined IN_GCC -/* These old constraint macros shouldn't appear anywhere in a - configuration using MD constraint definitions. */ -#endif - -/* Determin whether the target runtime library is Bionic */ -#ifndef TARGET_HAS_BIONIC -#define TARGET_HAS_BIONIC 0 -#endif - -/* Indicate that CLZ and CTZ are undefined at zero. */ -#ifndef CLZ_DEFINED_VALUE_AT_ZERO -#define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) 0 -#endif -#ifndef CTZ_DEFINED_VALUE_AT_ZERO -#define CTZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) 0 -#endif - -/* Provide a default value for STORE_FLAG_VALUE. */ -#ifndef STORE_FLAG_VALUE -#define STORE_FLAG_VALUE 1 -#endif - -/* This macro is used to determine what the largest unit size that - move_by_pieces can use is. */ - -/* MOVE_MAX_PIECES is the number of bytes at a time which we can - move efficiently, as opposed to MOVE_MAX which is the maximum - number of bytes we can move with a single instruction. */ - -#ifndef MOVE_MAX_PIECES -#define MOVE_MAX_PIECES MOVE_MAX -#endif - -/* STORE_MAX_PIECES is the number of bytes at a time that we can - store efficiently. Due to internal GCC limitations, this is - MOVE_MAX_PIECES limited by the number of bytes GCC can represent - for an immediate constant. */ - -#ifndef STORE_MAX_PIECES -#define STORE_MAX_PIECES MIN (MOVE_MAX_PIECES, 2 * sizeof (HOST_WIDE_INT)) -#endif - -#ifndef MAX_MOVE_MAX -#define MAX_MOVE_MAX MOVE_MAX -#endif - -#ifndef MIN_UNITS_PER_WORD -#define MIN_UNITS_PER_WORD UNITS_PER_WORD -#endif - -#ifndef MAX_BITS_PER_WORD -#define MAX_BITS_PER_WORD BITS_PER_WORD -#endif - -#ifndef STACK_POINTER_OFFSET -#define STACK_POINTER_OFFSET 0 -#endif - -#ifndef LOCAL_REGNO -#define LOCAL_REGNO(REGNO) 0 -#endif - -#ifndef HONOR_REG_ALLOC_ORDER -#define HONOR_REG_ALLOC_ORDER 0 -#endif - -/* EXIT_IGNORE_STACK should be nonzero if, when returning from a function, - the stack pointer does not matter. The value is tested only in - functions that have frame pointers. */ -#ifndef EXIT_IGNORE_STACK -#define EXIT_IGNORE_STACK 0 -#endif - -/* Assume that case vectors are not pc-relative. */ -#ifndef CASE_VECTOR_PC_RELATIVE -#define CASE_VECTOR_PC_RELATIVE 0 -#endif - -/* Assume that trampolines need function alignment. */ -#ifndef TRAMPOLINE_ALIGNMENT -#define TRAMPOLINE_ALIGNMENT FUNCTION_BOUNDARY -#endif - -/* Register mappings for target machines without register windows. */ -#ifndef INCOMING_REGNO -#define INCOMING_REGNO(N) (N) -#endif - -#ifndef OUTGOING_REGNO -#define OUTGOING_REGNO(N) (N) -#endif - -#ifndef SHIFT_COUNT_TRUNCATED -#define SHIFT_COUNT_TRUNCATED 0 -#endif - -#ifndef LEGITIMATE_PIC_OPERAND_P -#define LEGITIMATE_PIC_OPERAND_P(X) 1 -#endif - -#ifndef TARGET_MEM_CONSTRAINT -#define TARGET_MEM_CONSTRAINT 'm' -#endif - -#ifndef REVERSIBLE_CC_MODE -#define REVERSIBLE_CC_MODE(MODE) 0 -#endif - -/* Biggest alignment supported by the object file format of this machine. */ -#ifndef MAX_OFILE_ALIGNMENT -#define MAX_OFILE_ALIGNMENT BIGGEST_ALIGNMENT -#endif - -#ifndef FRAME_GROWS_DOWNWARD -#define FRAME_GROWS_DOWNWARD 0 -#endif - -#ifndef RETURN_ADDR_IN_PREVIOUS_FRAME -#define RETURN_ADDR_IN_PREVIOUS_FRAME 0 -#endif - -/* On most machines, the CFA coincides with the first incoming parm. */ -#ifndef ARG_POINTER_CFA_OFFSET -#define ARG_POINTER_CFA_OFFSET(FNDECL) \ - (FIRST_PARM_OFFSET (FNDECL) + crtl->args.pretend_args_size) -#endif - -/* On most machines, we use the CFA as DW_AT_frame_base. */ -#ifndef CFA_FRAME_BASE_OFFSET -#define CFA_FRAME_BASE_OFFSET(FNDECL) 0 -#endif - -/* The offset from the incoming value of %sp to the top of the stack frame - for the current function. */ -#ifndef INCOMING_FRAME_SP_OFFSET -#define INCOMING_FRAME_SP_OFFSET 0 -#endif - -#ifndef HARD_REGNO_NREGS_HAS_PADDING -#define HARD_REGNO_NREGS_HAS_PADDING(REGNO, MODE) 0 -#define HARD_REGNO_NREGS_WITH_PADDING(REGNO, MODE) -1 -#endif - -#ifndef OUTGOING_REG_PARM_STACK_SPACE -#define OUTGOING_REG_PARM_STACK_SPACE(FNTYPE) 0 -#endif - -/* MAX_STACK_ALIGNMENT is the maximum stack alignment guaranteed by - the backend. MAX_SUPPORTED_STACK_ALIGNMENT is the maximum best - effort stack alignment supported by the backend. If the backend - supports stack alignment, MAX_SUPPORTED_STACK_ALIGNMENT and - MAX_STACK_ALIGNMENT are the same. Otherwise, the incoming stack - boundary will limit the maximum guaranteed stack alignment. */ -#ifdef MAX_STACK_ALIGNMENT -#define MAX_SUPPORTED_STACK_ALIGNMENT MAX_STACK_ALIGNMENT -#else -#define MAX_STACK_ALIGNMENT STACK_BOUNDARY -#define MAX_SUPPORTED_STACK_ALIGNMENT PREFERRED_STACK_BOUNDARY -#endif - -#define SUPPORTS_STACK_ALIGNMENT (MAX_STACK_ALIGNMENT > STACK_BOUNDARY) - -#ifndef LOCAL_ALIGNMENT -#define LOCAL_ALIGNMENT(TYPE, ALIGNMENT) ALIGNMENT -#endif - -#ifndef STACK_SLOT_ALIGNMENT -#define STACK_SLOT_ALIGNMENT(TYPE,MODE,ALIGN) \ - ((TYPE) ? LOCAL_ALIGNMENT ((TYPE), (ALIGN)) : (ALIGN)) -#endif - -#ifndef LOCAL_DECL_ALIGNMENT -#define LOCAL_DECL_ALIGNMENT(DECL) \ - LOCAL_ALIGNMENT (TREE_TYPE (DECL), DECL_ALIGN (DECL)) -#endif - -#ifndef MINIMUM_ALIGNMENT -#define MINIMUM_ALIGNMENT(EXP,MODE,ALIGN) (ALIGN) -#endif - -/* Alignment value for attribute ((aligned)). */ -#ifndef ATTRIBUTE_ALIGNED_VALUE -#define ATTRIBUTE_ALIGNED_VALUE BIGGEST_ALIGNMENT -#endif - -#ifndef SLOW_UNALIGNED_ACCESS -#define SLOW_UNALIGNED_ACCESS(MODE, ALIGN) STRICT_ALIGNMENT -#endif - -/* For most ports anything that evaluates to a constant symbolic - or integer value is acceptable as a constant address. */ -#ifndef CONSTANT_ADDRESS_P -#define CONSTANT_ADDRESS_P(X) (CONSTANT_P (X) && GET_CODE (X) != CONST_DOUBLE) -#endif - -#ifndef MAX_FIXED_MODE_SIZE -#define MAX_FIXED_MODE_SIZE GET_MODE_BITSIZE (DImode) -#endif - -/* Nonzero if structures and unions should be returned in memory. - - This should only be defined if compatibility with another compiler or - with an ABI is needed, because it results in slower code. */ - -#ifndef DEFAULT_PCC_STRUCT_RETURN -#define DEFAULT_PCC_STRUCT_RETURN 1 -#endif - -#ifdef GCC_INSN_FLAGS_H -/* Dependent default target macro definitions - - This section of defaults.h defines target macros that depend on generated - headers. This is a bit awkward: We want to put all default definitions - for target macros in defaults.h, but some of the defaults depend on the - HAVE_* flags defines of insn-flags.h. But insn-flags.h is not always - included by files that do include defaults.h. - - Fortunately, the default macro definitions that depend on the HAVE_* - macros are also the ones that will only be used inside GCC itself, i.e. - not in the gen* programs or in target objects like libgcc. - - Obviously, it would be best to keep this section of defaults.h as small - as possible, by converting the macros defined below to target hooks or - functions. -*/ - -/* The default branch cost is 1. */ -#ifndef BRANCH_COST -#define BRANCH_COST(speed_p, predictable_p) 1 -#endif - -/* If a memory-to-memory move would take MOVE_RATIO or more simple - move-instruction sequences, we will do a movmem or libcall instead. */ - -#ifndef MOVE_RATIO -#if defined (HAVE_movmemqi) || defined (HAVE_movmemhi) || defined (HAVE_movmemsi) || defined (HAVE_movmemdi) || defined (HAVE_movmemti) -#define MOVE_RATIO(speed) 2 -#else -/* If we are optimizing for space (-Os), cut down the default move ratio. */ -#define MOVE_RATIO(speed) ((speed) ? 15 : 3) -#endif -#endif - -/* If a clear memory operation would take CLEAR_RATIO or more simple - move-instruction sequences, we will do a setmem or libcall instead. */ - -#ifndef CLEAR_RATIO -#if defined (HAVE_setmemqi) || defined (HAVE_setmemhi) || defined (HAVE_setmemsi) || defined (HAVE_setmemdi) || defined (HAVE_setmemti) -#define CLEAR_RATIO(speed) 2 -#else -/* If we are optimizing for space, cut down the default clear ratio. */ -#define CLEAR_RATIO(speed) ((speed) ? 15 :3) -#endif -#endif - -/* If a memory set (to value other than zero) operation would take - SET_RATIO or more simple move-instruction sequences, we will do a movmem - or libcall instead. */ -#ifndef SET_RATIO -#define SET_RATIO(speed) MOVE_RATIO (speed) -#endif - -/* Supply a default definition for FUNCTION_ARG_PADDING: - usually pad upward, but pad short args downward on - big-endian machines. */ - -#define DEFAULT_FUNCTION_ARG_PADDING(MODE, TYPE) \ - (! BYTES_BIG_ENDIAN \ - ? upward \ - : (((MODE) == BLKmode \ - ? ((TYPE) && TREE_CODE (TYPE_SIZE (TYPE)) == INTEGER_CST \ - && int_size_in_bytes (TYPE) < (PARM_BOUNDARY / BITS_PER_UNIT)) \ - : GET_MODE_BITSIZE (MODE) < PARM_BOUNDARY) \ - ? downward : upward)) - -#ifndef FUNCTION_ARG_PADDING -#define FUNCTION_ARG_PADDING(MODE, TYPE) \ - DEFAULT_FUNCTION_ARG_PADDING ((MODE), (TYPE)) -#endif - -/* Supply a default definition of STACK_SAVEAREA_MODE for emit_stack_save. - Normally move_insn, so Pmode stack pointer. */ - -#ifndef STACK_SAVEAREA_MODE -#define STACK_SAVEAREA_MODE(LEVEL) Pmode -#endif - -/* Supply a default definition of STACK_SIZE_MODE for - allocate_dynamic_stack_space. Normally PLUS/MINUS, so word_mode. */ - -#ifndef STACK_SIZE_MODE -#define STACK_SIZE_MODE word_mode -#endif - -/* Provide default values for the macros controlling stack checking. */ - -/* The default is neither full builtin stack checking... */ -#ifndef STACK_CHECK_BUILTIN -#define STACK_CHECK_BUILTIN 0 -#endif - -/* ...nor static builtin stack checking. */ -#ifndef STACK_CHECK_STATIC_BUILTIN -#define STACK_CHECK_STATIC_BUILTIN 0 -#endif - -/* The default interval is one page (4096 bytes). */ -#ifndef STACK_CHECK_PROBE_INTERVAL_EXP -#define STACK_CHECK_PROBE_INTERVAL_EXP 12 -#endif - -/* The default is not to move the stack pointer. */ -#ifndef STACK_CHECK_MOVING_SP -#define STACK_CHECK_MOVING_SP 0 -#endif - -/* This is a kludge to try to capture the discrepancy between the old - mechanism (generic stack checking) and the new mechanism (static - builtin stack checking). STACK_CHECK_PROTECT needs to be bumped - for the latter because part of the protection area is effectively - included in STACK_CHECK_MAX_FRAME_SIZE for the former. */ -#ifdef STACK_CHECK_PROTECT -#define STACK_OLD_CHECK_PROTECT STACK_CHECK_PROTECT -#else -#define STACK_OLD_CHECK_PROTECT \ - (targetm_common.except_unwind_info (&global_options) == UI_SJLJ \ - ? 75 * UNITS_PER_WORD \ - : 8 * 1024) -#endif - -/* Minimum amount of stack required to recover from an anticipated stack - overflow detection. The default value conveys an estimate of the amount - of stack required to propagate an exception. */ -#ifndef STACK_CHECK_PROTECT -#define STACK_CHECK_PROTECT \ - (targetm_common.except_unwind_info (&global_options) == UI_SJLJ \ - ? 75 * UNITS_PER_WORD \ - : 12 * 1024) -#endif - -/* Make the maximum frame size be the largest we can and still only need - one probe per function. */ -#ifndef STACK_CHECK_MAX_FRAME_SIZE -#define STACK_CHECK_MAX_FRAME_SIZE \ - ((1 << STACK_CHECK_PROBE_INTERVAL_EXP) - UNITS_PER_WORD) -#endif - -/* This is arbitrary, but should be large enough everywhere. */ -#ifndef STACK_CHECK_FIXED_FRAME_SIZE -#define STACK_CHECK_FIXED_FRAME_SIZE (4 * UNITS_PER_WORD) -#endif - -/* Provide a reasonable default for the maximum size of an object to - allocate in the fixed frame. We may need to be able to make this - controllable by the user at some point. */ -#ifndef STACK_CHECK_MAX_VAR_SIZE -#define STACK_CHECK_MAX_VAR_SIZE (STACK_CHECK_MAX_FRAME_SIZE / 100) -#endif - -/* By default, the C++ compiler will use function addresses in the - vtable entries. Setting this nonzero tells the compiler to use - function descriptors instead. The value of this macro says how - many words wide the descriptor is (normally 2). It is assumed - that the address of a function descriptor may be treated as a - pointer to a function. */ -#ifndef TARGET_VTABLE_USES_DESCRIPTORS -#define TARGET_VTABLE_USES_DESCRIPTORS 0 -#endif - -#ifndef SWITCHABLE_TARGET -#define SWITCHABLE_TARGET 0 -#endif - -/* If the target supports integers that are wider than two - HOST_WIDE_INTs on the host compiler, then the target should define - TARGET_SUPPORTS_WIDE_INT and make the appropriate fixups. - Otherwise the compiler really is not robust. */ -#ifndef TARGET_SUPPORTS_WIDE_INT -#define TARGET_SUPPORTS_WIDE_INT 0 -#endif - -#endif /* GCC_INSN_FLAGS_H */ - -#endif /* ! GCC_DEFAULTS_H */ diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/df.h b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/df.h deleted file mode 100644 index 532a2fd..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/df.h +++ /dev/null @@ -1,1215 +0,0 @@ -/* Form lists of pseudo register references for autoinc optimization - for GNU compiler. This is part of flow optimization. - Copyright (C) 1999-2015 Free Software Foundation, Inc. - Originally contributed by Michael P. Hayes - (m.hayes@elec.canterbury.ac.nz, mhayes@redhat.com) - Major rewrite contributed by Danny Berlin (dberlin@dberlin.org) - and Kenneth Zadeck (zadeck@naturalbridge.com). - -This file is part of GCC. - -GCC is free software; you can redistribute it and/or modify it under -the terms of the GNU General Public License as published by the Free -Software Foundation; either version 3, or (at your option) any later -version. - -GCC is distributed in the hope that it will be useful, but WITHOUT ANY -WARRANTY; without even the implied warranty of MERCHANTABILITY or -FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -for more details. - -You should have received a copy of the GNU General Public License -along with GCC; see the file COPYING3. If not see -. */ - -#ifndef GCC_DF_H -#define GCC_DF_H - -#include "bitmap.h" -#include "regset.h" -#include "sbitmap.h" -#include "predict.h" -#include "vec.h" -#include "hashtab.h" -#include "hash-set.h" -#include "machmode.h" -#include "tm.h" -#include "hard-reg-set.h" -#include "input.h" -#include "function.h" -#include "alloc-pool.h" -#include "timevar.h" - -struct dataflow; -struct df_d; -struct df_problem; -struct df_link; -struct df_insn_info; -union df_ref_d; - -/* Data flow problems. All problems must have a unique id here. */ - -/* Scanning is not really a dataflow problem, but it is useful to have - the basic block functions in the vector so that things get done in - a uniform manner. The last four problems can be added or deleted - at any time are always defined (though LIVE is always there at -O2 - or higher); the others are always there. */ -#define DF_SCAN 0 -#define DF_LR 1 /* Live Registers backward. */ -#define DF_LIVE 2 /* Live Registers & Uninitialized Registers */ -#define DF_RD 3 /* Reaching Defs. */ -#define DF_CHAIN 4 /* Def-Use and/or Use-Def Chains. */ -#define DF_WORD_LR 5 /* Subreg tracking lr. */ -#define DF_NOTE 6 /* REG_DEAD and REG_UNUSED notes. */ -#define DF_MD 7 /* Multiple Definitions. */ - -#define DF_LAST_PROBLEM_PLUS1 (DF_MD + 1) - -/* Dataflow direction. */ -enum df_flow_dir - { - DF_NONE, - DF_FORWARD, - DF_BACKWARD - }; - -/* Descriminator for the various df_ref types. */ -enum df_ref_class {DF_REF_BASE, DF_REF_ARTIFICIAL, DF_REF_REGULAR}; - -/* The first of these us a set of a registers. The remaining three - are all uses of a register (the mem_load and mem_store relate to - how the register as an addressing operand). */ -enum df_ref_type {DF_REF_REG_DEF, DF_REF_REG_USE, - DF_REF_REG_MEM_LOAD, DF_REF_REG_MEM_STORE}; - -enum df_ref_flags - { - /* This flag is set if this ref occurs inside of a conditional - execution instruction. */ - DF_REF_CONDITIONAL = 1 << 0, - - /* If this flag is set for an artificial use or def, that ref - logically happens at the top of the block. If it is not set - for an artificial use or def, that ref logically happens at the - bottom of the block. This is never set for regular refs. */ - DF_REF_AT_TOP = 1 << 1, - - /* This flag is set if the use is inside a REG_EQUAL or REG_EQUIV - note. */ - DF_REF_IN_NOTE = 1 << 2, - - /* This bit is true if this ref can make regs_ever_live true for - this regno. */ - DF_HARD_REG_LIVE = 1 << 3, - - - /* This flag is set if this ref is a partial use or def of the - associated register. */ - DF_REF_PARTIAL = 1 << 4, - - /* Read-modify-write refs generate both a use and a def and - these are marked with this flag to show that they are not - independent. */ - DF_REF_READ_WRITE = 1 << 5, - - /* This flag is set if this ref, generally a def, may clobber the - referenced register. This is generally only set for hard - registers that cross a call site. With better information - about calls, some of these could be changed in the future to - DF_REF_MUST_CLOBBER. */ - DF_REF_MAY_CLOBBER = 1 << 6, - - /* This flag is set if this ref, generally a def, is a real - clobber. This is not currently set for registers live across a - call because that clobbering may or may not happen. - - Most of the uses of this are with sets that have a - GET_CODE(..)==CLOBBER. Note that this is set even if the - clobber is to a subreg. So in order to tell if the clobber - wipes out the entire register, it is necessary to also check - the DF_REF_PARTIAL flag. */ - DF_REF_MUST_CLOBBER = 1 << 7, - - - /* If the ref has one of the following two flags set, then the - struct df_ref can be cast to struct df_ref_extract to access - the width and offset fields. */ - - /* This flag is set if the ref contains a SIGN_EXTRACT. */ - DF_REF_SIGN_EXTRACT = 1 << 8, - - /* This flag is set if the ref contains a ZERO_EXTRACT. */ - DF_REF_ZERO_EXTRACT = 1 << 9, - - /* This flag is set if the ref contains a STRICT_LOW_PART. */ - DF_REF_STRICT_LOW_PART = 1 << 10, - - /* This flag is set if the ref contains a SUBREG. */ - DF_REF_SUBREG = 1 << 11, - - - /* This bit is true if this ref is part of a multiword hardreg. */ - DF_REF_MW_HARDREG = 1 << 12, - - /* This flag is set if this ref is a usage of the stack pointer by - a function call. */ - DF_REF_CALL_STACK_USAGE = 1 << 13, - - /* This flag is used for verification of existing refs. */ - DF_REF_REG_MARKER = 1 << 14, - - /* This flag is set if this ref is inside a pre/post modify. */ - DF_REF_PRE_POST_MODIFY = 1 << 15 - - }; - -/* The possible ordering of refs within the df_ref_info. */ -enum df_ref_order - { - /* There is not table. */ - DF_REF_ORDER_NO_TABLE, - - /* There is a table of refs but it is not (or no longer) organized - by one of the following methods. */ - DF_REF_ORDER_UNORDERED, - DF_REF_ORDER_UNORDERED_WITH_NOTES, - - /* Organize the table by reg order, all of the refs with regno 0 - followed by all of the refs with regno 1 ... . Within all of - the regs for a particular regno, the refs are unordered. */ - DF_REF_ORDER_BY_REG, - - /* For uses, the refs within eq notes may be added for - DF_REF_ORDER_BY_REG. */ - DF_REF_ORDER_BY_REG_WITH_NOTES, - - /* Organize the refs in insn order. The insns are ordered within a - block, and the blocks are ordered by FOR_ALL_BB_FN. */ - DF_REF_ORDER_BY_INSN, - - /* For uses, the refs within eq notes may be added for - DF_REF_ORDER_BY_INSN. */ - DF_REF_ORDER_BY_INSN_WITH_NOTES - }; - -/* Function prototypes added to df_problem instance. */ - -/* Allocate the problem specific data. */ -typedef void (*df_alloc_function) (bitmap); - -/* This function is called if the problem has global data that needs - to be cleared when ever the set of blocks changes. The bitmap - contains the set of blocks that may require special attention. - This call is only made if some of the blocks are going to change. - If everything is to be deleted, the wholesale deletion mechanisms - apply. */ -typedef void (*df_reset_function) (bitmap); - -/* Free the basic block info. Called from the block reordering code - to get rid of the blocks that have been squished down. */ -typedef void (*df_free_bb_function) (basic_block, void *); - -/* Local compute function. */ -typedef void (*df_local_compute_function) (bitmap); - -/* Init the solution specific data. */ -typedef void (*df_init_function) (bitmap); - -/* Iterative dataflow function. */ -typedef void (*df_dataflow_function) (struct dataflow *, bitmap, int *, int); - -/* Confluence operator for blocks with 0 out (or in) edges. */ -typedef void (*df_confluence_function_0) (basic_block); - -/* Confluence operator for blocks with 1 or more out (or in) edges. - Return true if BB input data has changed. */ -typedef bool (*df_confluence_function_n) (edge); - -/* Transfer function for blocks. - Return true if BB output data has changed. */ -typedef bool (*df_transfer_function) (int); - -/* Function to massage the information after the problem solving. */ -typedef void (*df_finalizer_function) (bitmap); - -/* Function to free all of the problem specific datastructures. */ -typedef void (*df_free_function) (void); - -/* Function to remove this problem from the stack of dataflow problems - without effecting the other problems in the stack except for those - that depend on this problem. */ -typedef void (*df_remove_problem_function) (void); - -/* Function to dump basic block independent results to FILE. */ -typedef void (*df_dump_problem_function) (FILE *); - -/* Function to dump top or bottom of basic block results to FILE. */ -typedef void (*df_dump_bb_problem_function) (basic_block, FILE *); - -/* Function to dump before or after an insn to FILE. */ -typedef void (*df_dump_insn_problem_function) (const rtx_insn *, FILE *); - -/* Function to dump top or bottom of basic block results to FILE. */ -typedef void (*df_verify_solution_start) (void); - -/* Function to dump top or bottom of basic block results to FILE. */ -typedef void (*df_verify_solution_end) (void); - -/* The static description of a dataflow problem to solve. See above - typedefs for doc for the function fields. */ - -struct df_problem { - /* The unique id of the problem. This is used it index into - df->defined_problems to make accessing the problem data easy. */ - unsigned int id; - enum df_flow_dir dir; /* Dataflow direction. */ - df_alloc_function alloc_fun; - df_reset_function reset_fun; - df_free_bb_function free_bb_fun; - df_local_compute_function local_compute_fun; - df_init_function init_fun; - df_dataflow_function dataflow_fun; - df_confluence_function_0 con_fun_0; - df_confluence_function_n con_fun_n; - df_transfer_function trans_fun; - df_finalizer_function finalize_fun; - df_free_function free_fun; - df_remove_problem_function remove_problem_fun; - df_dump_problem_function dump_start_fun; - df_dump_bb_problem_function dump_top_fun; - df_dump_bb_problem_function dump_bottom_fun; - df_dump_insn_problem_function dump_insn_top_fun; - df_dump_insn_problem_function dump_insn_bottom_fun; - df_verify_solution_start verify_start_fun; - df_verify_solution_end verify_end_fun; - struct df_problem *dependent_problem; - unsigned int block_info_elt_size; - - /* The timevar id associated with this pass. */ - timevar_id_t tv_id; - - /* True if the df_set_blocks should null out the basic block info if - this block drops out of df->blocks_to_analyze. */ - bool free_blocks_on_set_blocks; -}; - - -/* The specific instance of the problem to solve. */ -struct dataflow -{ - struct df_problem *problem; /* The problem to be solved. */ - - /* Array indexed by bb->index, that contains basic block problem and - solution specific information. */ - void *block_info; - unsigned int block_info_size; - - /* The pool to allocate the block_info from. */ - alloc_pool block_pool; - - /* The lr and live problems have their transfer functions recomputed - only if necessary. This is possible for them because, the - problems are kept active for the entire backend and their - transfer functions are indexed by the REGNO. These are not - defined for any other problem. */ - bitmap out_of_date_transfer_functions; - - /* Other problem specific data that is not on a per basic block - basis. The structure is generally defined privately for the - problem. The exception being the scanning problem where it is - fully public. */ - void *problem_data; - - /* Local flags for some of the problems. */ - unsigned int local_flags; - - /* True if this problem of this instance has been initialized. This - is used by the dumpers to keep garbage out of the dumps if, for - debugging a dump is produced before the first call to - df_analyze after a new problem is added. */ - bool computed; - - /* True if the something has changed which invalidates the dataflow - solutions. Note that this bit is always true for all problems except - lr and live. */ - bool solutions_dirty; - - /* If true, this pass is deleted by df_finish_pass. This is never - true for DF_SCAN and DF_LR. It is true for DF_LIVE if optimize > - 1. It is always true for the other problems. */ - bool optional_p; -}; - - -/* The set of multiword hardregs used as operands to this - instruction. These are factored into individual uses and defs but - the aggregate is still needed to service the REG_DEAD and - REG_UNUSED notes. */ -struct df_mw_hardreg -{ - df_mw_hardreg *next; /* Next entry for this instruction. */ - rtx mw_reg; /* The multiword hardreg. */ - /* These two bitfields are intentionally oversized, in the hope that - accesses to 16-bit fields will usually be quicker. */ - ENUM_BITFIELD(df_ref_type) type : 16; - /* Used to see if the ref is read or write. */ - int flags : 16; /* Various df_ref_flags. */ - unsigned int start_regno; /* First word of the multi word subreg. */ - unsigned int end_regno; /* Last word of the multi word subreg. */ - unsigned int mw_order; /* Same as df_ref.ref_order. */ -}; - - -/* Define a register reference structure. One of these is allocated - for every register reference (use or def). Note some register - references (e.g., post_inc, subreg) generate both a def and a use. */ -struct df_base_ref -{ - /* These three bitfields are intentionally oversized, in the hope that - accesses to 8 and 16-bit fields will usually be quicker. */ - ENUM_BITFIELD(df_ref_class) cl : 8; - - ENUM_BITFIELD(df_ref_type) type : 8; - /* Type of ref. */ - int flags : 16; /* Various df_ref_flags. */ - unsigned int regno; /* The register number referenced. */ - rtx reg; /* The register referenced. */ - union df_ref_d *next_loc; /* Next ref for same insn or bb. */ - struct df_link *chain; /* Head of def-use, use-def. */ - /* Pointer to the insn info of the containing instruction. FIXME! - Currently this is NULL for artificial refs but this will be used - when FUDs are added. */ - struct df_insn_info *insn_info; - /* For each regno, there are three chains of refs, one for the uses, - the eq_uses and the defs. These chains go through the refs - themselves rather than using an external structure. */ - union df_ref_d *next_reg; /* Next ref with same regno and type. */ - union df_ref_d *prev_reg; /* Prev ref with same regno and type. */ - /* Location in the ref table. This is only valid after a call to - df_maybe_reorganize_[use,def]_refs which is an expensive operation. */ - int id; - /* The index at which the operand was scanned in the insn. This is - used to totally order the refs in an insn. */ - unsigned int ref_order; -}; - - -/* The three types of df_refs. Note that the df_ref_extract is an - extension of the df_regular_ref, not the df_base_ref. */ -struct df_artificial_ref -{ - struct df_base_ref base; - - /* Artificial refs do not have an insn, so to get the basic block, - it must be explicitly here. */ - basic_block bb; -}; - - -struct df_regular_ref -{ - struct df_base_ref base; - /* The loc is the address in the insn of the reg. This is not - defined for special registers, such as clobbers and stack - pointers that are also associated with call insns and so those - just use the base. */ - rtx *loc; -}; - -/* Union of the different kinds of defs/uses placeholders. */ -union df_ref_d -{ - struct df_base_ref base; - struct df_regular_ref regular_ref; - struct df_artificial_ref artificial_ref; -}; -typedef union df_ref_d *df_ref; - - -/* One of these structures is allocated for every insn. */ -struct df_insn_info -{ - rtx_insn *insn; /* The insn this info comes from. */ - df_ref defs; /* Head of insn-def chain. */ - df_ref uses; /* Head of insn-use chain. */ - /* Head of insn-use chain for uses in REG_EQUAL/EQUIV notes. */ - df_ref eq_uses; - struct df_mw_hardreg *mw_hardregs; - /* The logical uid of the insn in the basic block. This is valid - after any call to df_analyze but may rot after insns are added, - deleted or moved. */ - int luid; -}; - -/* These links are used for ref-ref chains. Currently only DEF-USE and - USE-DEF chains can be built by DF. */ -struct df_link -{ - df_ref ref; - struct df_link *next; -}; - - -enum df_chain_flags -{ - /* Flags that control the building of chains. */ - DF_DU_CHAIN = 1, /* Build DU chains. */ - DF_UD_CHAIN = 2 /* Build UD chains. */ -}; - -enum df_changeable_flags -{ - /* Scanning flags. */ - /* Flag to control the running of dce as a side effect of building LR. */ - DF_LR_RUN_DCE = 1 << 0, /* Run DCE. */ - DF_NO_HARD_REGS = 1 << 1, /* Skip hard registers in RD and CHAIN Building. */ - - DF_EQ_NOTES = 1 << 2, /* Build chains with uses present in EQUIV/EQUAL notes. */ - DF_NO_REGS_EVER_LIVE = 1 << 3, /* Do not compute the regs_ever_live. */ - - /* Cause df_insn_rescan df_notes_rescan and df_insn_delete, to - return immediately. This is used by passes that know how to update - the scanning them selves. */ - DF_NO_INSN_RESCAN = 1 << 4, - - /* Cause df_insn_rescan df_notes_rescan and df_insn_delete, to - return after marking the insn for later processing. This allows all - rescans to be batched. */ - DF_DEFER_INSN_RESCAN = 1 << 5, - - /* Compute the reaching defs problem as "live and reaching defs" (LR&RD). - A DEF is reaching and live at insn I if DEF reaches I and REGNO(DEF) - is in LR_IN of the basic block containing I. */ - DF_RD_PRUNE_DEAD_DEFS = 1 << 6, - - DF_VERIFY_SCHEDULED = 1 << 7 -}; - -/* Two of these structures are inline in df, one for the uses and one - for the defs. This structure is only contains the refs within the - boundary of the df_set_blocks if that has been defined. */ -struct df_ref_info -{ - df_ref *refs; /* Ref table, indexed by id. */ - unsigned int *begin; /* First ref_index for this pseudo. */ - unsigned int *count; /* Count of refs for this pseudo. */ - unsigned int refs_size; /* Size of currently allocated refs table. */ - - /* Table_size is the number of elements in the refs table. This - will also be the width of the bitvectors in the rd and ru - problems. Total_size is the number of refs. These will be the - same if the focus has not been reduced by df_set_blocks. If the - focus has been reduced, table_size will be smaller since it only - contains the refs in the set blocks. */ - unsigned int table_size; - unsigned int total_size; - - enum df_ref_order ref_order; -}; - -/* Three of these structures are allocated for every pseudo reg. One - for the uses, one for the eq_uses and one for the defs. */ -struct df_reg_info -{ - /* Head of chain for refs of that type and regno. */ - df_ref reg_chain; - /* Number of refs in the chain. */ - unsigned int n_refs; -}; - - -/*---------------------------------------------------------------------------- - Problem data for the scanning dataflow problem. Unlike the other - dataflow problems, the problem data for scanning is fully exposed and - used by owners of the problem. -----------------------------------------------------------------------------*/ - -struct df_d -{ - - /* The set of problems to be solved is stored in two arrays. In - PROBLEMS_IN_ORDER, the problems are stored in the order that they - are solved. This is an internally dense array that may have - nulls at the end of it. In PROBLEMS_BY_INDEX, the problem is - stored by the value in df_problem.id. These are used to access - the problem local data without having to search the first - array. */ - - struct dataflow *problems_in_order[DF_LAST_PROBLEM_PLUS1]; - struct dataflow *problems_by_index[DF_LAST_PROBLEM_PLUS1]; - - /* If not NULL, this subset of blocks of the program to be - considered for analysis. At certain times, this will contain all - the blocks in the function so it cannot be used as an indicator - of if we are analyzing a subset. See analyze_subset. */ - bitmap blocks_to_analyze; - - /* The following information is really the problem data for the - scanning instance but it is used too often by the other problems - to keep getting it from there. */ - struct df_ref_info def_info; /* Def info. */ - struct df_ref_info use_info; /* Use info. */ - - /* The following three arrays are allocated in parallel. They contain - the sets of refs of each type for each reg. */ - struct df_reg_info **def_regs; /* Def reg info. */ - struct df_reg_info **use_regs; /* Eq_use reg info. */ - struct df_reg_info **eq_use_regs; /* Eq_use info. */ - unsigned int regs_size; /* Size of currently allocated regs table. */ - unsigned int regs_inited; /* Number of regs with reg_infos allocated. */ - - - struct df_insn_info **insns; /* Insn table, indexed by insn UID. */ - unsigned int insns_size; /* Size of insn table. */ - - int num_problems_defined; - - bitmap_head hardware_regs_used; /* The set of hardware registers used. */ - /* The set of hard regs that are in the artificial uses at the end - of a regular basic block. */ - bitmap_head regular_block_artificial_uses; - /* The set of hard regs that are in the artificial uses at the end - of a basic block that has an EH pred. */ - bitmap_head eh_block_artificial_uses; - /* The set of hardware registers live on entry to the function. */ - bitmap entry_block_defs; - bitmap exit_block_uses; /* The set of hardware registers used in exit block. */ - - /* Insns to delete, rescan or reprocess the notes at next - df_rescan_all or df_process_deferred_rescans. */ - bitmap_head insns_to_delete; - bitmap_head insns_to_rescan; - bitmap_head insns_to_notes_rescan; - int *postorder; /* The current set of basic blocks - in reverse postorder. */ - int *postorder_inverted; /* The current set of basic blocks - in reverse postorder of inverted CFG. */ - int n_blocks; /* The number of blocks in reverse postorder. */ - int n_blocks_inverted; /* The number of blocks - in reverse postorder of inverted CFG. */ - - /* An array [FIRST_PSEUDO_REGISTER], indexed by regno, of the number - of refs that qualify as being real hard regs uses. Artificial - uses and defs as well as refs in eq notes are ignored. If the - ref is a def, it cannot be a MAY_CLOBBER def. If the ref is a - use, it cannot be the emim_reg_set or be the frame or arg pointer - register. Uses in debug insns are ignored. - - IT IS NOT ACCEPTABLE TO MANUALLY CHANGE THIS ARRAY. This array - always reflects the actual number of refs in the insn stream that - satisfy the above criteria. */ - unsigned int *hard_regs_live_count; - - /* This counter provides a way to totally order refs without using - addresses. It is incremented whenever a ref is created. */ - unsigned int ref_order; - - /* Problem specific control information. This is a combination of - enum df_changeable_flags values. */ - int changeable_flags : 8; - - /* If this is true, then only a subset of the blocks of the program - is considered to compute the solutions of dataflow problems. */ - bool analyze_subset; - - /* True if someone added or deleted something from regs_ever_live so - that the entry and exit blocks need be reprocessed. */ - bool redo_entry_and_exit; -}; - -#define DF_SCAN_BB_INFO(BB) (df_scan_get_bb_info ((BB)->index)) -#define DF_RD_BB_INFO(BB) (df_rd_get_bb_info ((BB)->index)) -#define DF_LR_BB_INFO(BB) (df_lr_get_bb_info ((BB)->index)) -#define DF_LIVE_BB_INFO(BB) (df_live_get_bb_info ((BB)->index)) -#define DF_WORD_LR_BB_INFO(BB) (df_word_lr_get_bb_info ((BB)->index)) -#define DF_MD_BB_INFO(BB) (df_md_get_bb_info ((BB)->index)) - -/* Most transformations that wish to use live register analysis will - use these macros. This info is the and of the lr and live sets. */ -#define DF_LIVE_IN(BB) (&DF_LIVE_BB_INFO (BB)->in) -#define DF_LIVE_OUT(BB) (&DF_LIVE_BB_INFO (BB)->out) - -/* These macros are used by passes that are not tolerant of - uninitialized variables. This intolerance should eventually - be fixed. */ -#define DF_LR_IN(BB) (&DF_LR_BB_INFO (BB)->in) -#define DF_LR_OUT(BB) (&DF_LR_BB_INFO (BB)->out) - -/* These macros are used by passes that are not tolerant of - uninitialized variables. This intolerance should eventually - be fixed. */ -#define DF_WORD_LR_IN(BB) (&DF_WORD_LR_BB_INFO (BB)->in) -#define DF_WORD_LR_OUT(BB) (&DF_WORD_LR_BB_INFO (BB)->out) - -/* Macros to access the elements within the ref structure. */ - - -#define DF_REF_REAL_REG(REF) (GET_CODE ((REF)->base.reg) == SUBREG \ - ? SUBREG_REG ((REF)->base.reg) : ((REF)->base.reg)) -#define DF_REF_REGNO(REF) ((REF)->base.regno) -#define DF_REF_REAL_LOC(REF) (GET_CODE (*((REF)->regular_ref.loc)) == SUBREG \ - ? &SUBREG_REG (*((REF)->regular_ref.loc)) : ((REF)->regular_ref.loc)) -#define DF_REF_REG(REF) ((REF)->base.reg) -#define DF_REF_LOC(REF) (DF_REF_CLASS (REF) == DF_REF_REGULAR ? \ - (REF)->regular_ref.loc : NULL) -#define DF_REF_BB(REF) (DF_REF_IS_ARTIFICIAL (REF) \ - ? (REF)->artificial_ref.bb \ - : BLOCK_FOR_INSN (DF_REF_INSN (REF))) -#define DF_REF_BBNO(REF) (DF_REF_BB (REF)->index) -#define DF_REF_INSN_INFO(REF) ((REF)->base.insn_info) -#define DF_REF_INSN(REF) ((REF)->base.insn_info->insn) -#define DF_REF_INSN_UID(REF) (INSN_UID (DF_REF_INSN(REF))) -#define DF_REF_CLASS(REF) ((REF)->base.cl) -#define DF_REF_TYPE(REF) ((REF)->base.type) -#define DF_REF_CHAIN(REF) ((REF)->base.chain) -#define DF_REF_ID(REF) ((REF)->base.id) -#define DF_REF_FLAGS(REF) ((REF)->base.flags) -#define DF_REF_FLAGS_IS_SET(REF, v) ((DF_REF_FLAGS (REF) & (v)) != 0) -#define DF_REF_FLAGS_SET(REF, v) (DF_REF_FLAGS (REF) |= (v)) -#define DF_REF_FLAGS_CLEAR(REF, v) (DF_REF_FLAGS (REF) &= ~(v)) -#define DF_REF_ORDER(REF) ((REF)->base.ref_order) -/* If DF_REF_IS_ARTIFICIAL () is true, this is not a real - definition/use, but an artificial one created to model always live - registers, eh uses, etc. */ -#define DF_REF_IS_ARTIFICIAL(REF) (DF_REF_CLASS (REF) == DF_REF_ARTIFICIAL) -#define DF_REF_REG_MARK(REF) (DF_REF_FLAGS_SET ((REF),DF_REF_REG_MARKER)) -#define DF_REF_REG_UNMARK(REF) (DF_REF_FLAGS_CLEAR ((REF),DF_REF_REG_MARKER)) -#define DF_REF_IS_REG_MARKED(REF) (DF_REF_FLAGS_IS_SET ((REF),DF_REF_REG_MARKER)) -#define DF_REF_NEXT_LOC(REF) ((REF)->base.next_loc) -#define DF_REF_NEXT_REG(REF) ((REF)->base.next_reg) -#define DF_REF_PREV_REG(REF) ((REF)->base.prev_reg) -/* The following two macros may only be applied if one of - DF_REF_SIGN_EXTRACT | DF_REF_ZERO_EXTRACT is true. */ -#define DF_REF_EXTRACT_WIDTH(REF) ((REF)->extract_ref.width) -#define DF_REF_EXTRACT_OFFSET(REF) ((REF)->extract_ref.offset) -#define DF_REF_EXTRACT_MODE(REF) ((REF)->extract_ref.mode) - -/* Macros to determine the reference type. */ -#define DF_REF_REG_DEF_P(REF) (DF_REF_TYPE (REF) == DF_REF_REG_DEF) -#define DF_REF_REG_USE_P(REF) (!DF_REF_REG_DEF_P (REF)) -#define DF_REF_REG_MEM_STORE_P(REF) (DF_REF_TYPE (REF) == DF_REF_REG_MEM_STORE) -#define DF_REF_REG_MEM_LOAD_P(REF) (DF_REF_TYPE (REF) == DF_REF_REG_MEM_LOAD) -#define DF_REF_REG_MEM_P(REF) (DF_REF_REG_MEM_STORE_P (REF) \ - || DF_REF_REG_MEM_LOAD_P (REF)) - -#define DF_MWS_REG_DEF_P(MREF) (DF_MWS_TYPE (MREF) == DF_REF_REG_DEF) -#define DF_MWS_REG_USE_P(MREF) (!DF_MWS_REG_DEF_P (MREF)) -#define DF_MWS_NEXT(MREF) ((MREF)->next) -#define DF_MWS_TYPE(MREF) ((MREF)->type) - -/* Macros to get the refs out of def_info or use_info refs table. If - the focus of the dataflow has been set to some subset of blocks - with df_set_blocks, these macros will only find the uses and defs - in that subset of blocks. - - These macros should be used with care. The def macros are only - usable after a call to df_maybe_reorganize_def_refs and the use - macros are only usable after a call to - df_maybe_reorganize_use_refs. HOWEVER, BUILDING AND USING THESE - ARRAYS ARE A CACHE LOCALITY KILLER. */ - -#define DF_DEFS_TABLE_SIZE() (df->def_info.table_size) -#define DF_DEFS_GET(ID) (df->def_info.refs[(ID)]) -#define DF_DEFS_SET(ID,VAL) (df->def_info.refs[(ID)]=(VAL)) -#define DF_DEFS_COUNT(ID) (df->def_info.count[(ID)]) -#define DF_DEFS_BEGIN(ID) (df->def_info.begin[(ID)]) -#define DF_USES_TABLE_SIZE() (df->use_info.table_size) -#define DF_USES_GET(ID) (df->use_info.refs[(ID)]) -#define DF_USES_SET(ID,VAL) (df->use_info.refs[(ID)]=(VAL)) -#define DF_USES_COUNT(ID) (df->use_info.count[(ID)]) -#define DF_USES_BEGIN(ID) (df->use_info.begin[(ID)]) - -/* Macros to access the register information from scan dataflow record. */ - -#define DF_REG_SIZE(DF) (df->regs_inited) -#define DF_REG_DEF_GET(REG) (df->def_regs[(REG)]) -#define DF_REG_DEF_CHAIN(REG) (df->def_regs[(REG)]->reg_chain) -#define DF_REG_DEF_COUNT(REG) (df->def_regs[(REG)]->n_refs) -#define DF_REG_USE_GET(REG) (df->use_regs[(REG)]) -#define DF_REG_USE_CHAIN(REG) (df->use_regs[(REG)]->reg_chain) -#define DF_REG_USE_COUNT(REG) (df->use_regs[(REG)]->n_refs) -#define DF_REG_EQ_USE_GET(REG) (df->eq_use_regs[(REG)]) -#define DF_REG_EQ_USE_CHAIN(REG) (df->eq_use_regs[(REG)]->reg_chain) -#define DF_REG_EQ_USE_COUNT(REG) (df->eq_use_regs[(REG)]->n_refs) - -/* Macros to access the elements within the reg_info structure table. */ - -#define DF_REGNO_FIRST_DEF(REGNUM) \ -(DF_REG_DEF_GET(REGNUM) ? DF_REG_DEF_GET (REGNUM) : 0) -#define DF_REGNO_LAST_USE(REGNUM) \ -(DF_REG_USE_GET(REGNUM) ? DF_REG_USE_GET (REGNUM) : 0) - -/* Macros to access the elements within the insn_info structure table. */ - -#define DF_INSN_SIZE() ((df)->insns_size) -#define DF_INSN_INFO_GET(INSN) (df->insns[(INSN_UID (INSN))]) -#define DF_INSN_INFO_SET(INSN,VAL) (df->insns[(INSN_UID (INSN))]=(VAL)) -#define DF_INSN_INFO_LUID(II) ((II)->luid) -#define DF_INSN_INFO_DEFS(II) ((II)->defs) -#define DF_INSN_INFO_USES(II) ((II)->uses) -#define DF_INSN_INFO_EQ_USES(II) ((II)->eq_uses) -#define DF_INSN_INFO_MWS(II) ((II)->mw_hardregs) - -#define DF_INSN_LUID(INSN) (DF_INSN_INFO_LUID (DF_INSN_INFO_GET (INSN))) -#define DF_INSN_DEFS(INSN) (DF_INSN_INFO_DEFS (DF_INSN_INFO_GET (INSN))) -#define DF_INSN_USES(INSN) (DF_INSN_INFO_USES (DF_INSN_INFO_GET (INSN))) -#define DF_INSN_EQ_USES(INSN) (DF_INSN_INFO_EQ_USES (DF_INSN_INFO_GET (INSN))) - -#define DF_INSN_UID_GET(UID) (df->insns[(UID)]) -#define DF_INSN_UID_SET(UID,VAL) (df->insns[(UID)]=(VAL)) -#define DF_INSN_UID_SAFE_GET(UID) (((unsigned)(UID) < DF_INSN_SIZE ()) \ - ? DF_INSN_UID_GET (UID) \ - : NULL) -#define DF_INSN_UID_LUID(INSN) (DF_INSN_UID_GET (INSN)->luid) -#define DF_INSN_UID_DEFS(INSN) (DF_INSN_UID_GET (INSN)->defs) -#define DF_INSN_UID_USES(INSN) (DF_INSN_UID_GET (INSN)->uses) -#define DF_INSN_UID_EQ_USES(INSN) (DF_INSN_UID_GET (INSN)->eq_uses) -#define DF_INSN_UID_MWS(INSN) (DF_INSN_UID_GET (INSN)->mw_hardregs) - -#define FOR_EACH_INSN_INFO_DEF(ITER, INSN) \ - for (ITER = DF_INSN_INFO_DEFS (INSN); ITER; ITER = DF_REF_NEXT_LOC (ITER)) - -#define FOR_EACH_INSN_INFO_USE(ITER, INSN) \ - for (ITER = DF_INSN_INFO_USES (INSN); ITER; ITER = DF_REF_NEXT_LOC (ITER)) - -#define FOR_EACH_INSN_INFO_EQ_USE(ITER, INSN) \ - for (ITER = DF_INSN_INFO_EQ_USES (INSN); ITER; ITER = DF_REF_NEXT_LOC (ITER)) - -#define FOR_EACH_INSN_INFO_MW(ITER, INSN) \ - for (ITER = DF_INSN_INFO_MWS (INSN); ITER; ITER = DF_MWS_NEXT (ITER)) - -#define FOR_EACH_INSN_DEF(ITER, INSN) \ - FOR_EACH_INSN_INFO_DEF(ITER, DF_INSN_INFO_GET (INSN)) - -#define FOR_EACH_INSN_USE(ITER, INSN) \ - FOR_EACH_INSN_INFO_USE(ITER, DF_INSN_INFO_GET (INSN)) - -#define FOR_EACH_INSN_EQ_USE(ITER, INSN) \ - FOR_EACH_INSN_INFO_EQ_USE(ITER, DF_INSN_INFO_GET (INSN)) - -#define FOR_EACH_ARTIFICIAL_USE(ITER, BB_INDEX) \ - for (ITER = df_get_artificial_uses (BB_INDEX); ITER; \ - ITER = DF_REF_NEXT_LOC (ITER)) - -#define FOR_EACH_ARTIFICIAL_DEF(ITER, BB_INDEX) \ - for (ITER = df_get_artificial_defs (BB_INDEX); ITER; \ - ITER = DF_REF_NEXT_LOC (ITER)) - -/* An obstack for bitmap not related to specific dataflow problems. - This obstack should e.g. be used for bitmaps with a short life time - such as temporary bitmaps. This obstack is declared in df-core.c. */ - -extern bitmap_obstack df_bitmap_obstack; - - -/* One of these structures is allocated for every basic block. */ -struct df_scan_bb_info -{ - /* The entry block has many artificial defs and these are at the - bottom of the block. - - Blocks that are targets of exception edges may have some - artificial defs. These are logically located at the top of the - block. - - Blocks that are the targets of non-local goto's have the hard - frame pointer defined at the top of the block. */ - df_ref artificial_defs; - - /* Blocks that are targets of exception edges may have some - artificial uses. These are logically at the top of the block. - - Most blocks have artificial uses at the bottom of the block. */ - df_ref artificial_uses; -}; - - -/* Reaching definitions. All bitmaps are indexed by the id field of - the ref except sparse_kill which is indexed by regno. For the - LR&RD problem, the kill set is not complete: It does not contain - DEFs killed because the set register has died in the LR set. */ -struct df_rd_bb_info -{ - /* Local sets to describe the basic blocks. */ - bitmap_head kill; - bitmap_head sparse_kill; - bitmap_head gen; /* The set of defs generated in this block. */ - - /* The results of the dataflow problem. */ - bitmap_head in; /* At the top of the block. */ - bitmap_head out; /* At the bottom of the block. */ -}; - - -/* Multiple reaching definitions. All bitmaps are referenced by the - register number. */ - -struct df_md_bb_info -{ - /* Local sets to describe the basic blocks. */ - bitmap_head gen; /* Partial/conditional definitions live at BB out. */ - bitmap_head kill; /* Other definitions that are live at BB out. */ - bitmap_head init; /* Definitions coming from dominance frontier edges. */ - - /* The results of the dataflow problem. */ - bitmap_head in; /* Just before the block itself. */ - bitmap_head out; /* At the bottom of the block. */ -}; - - -/* Live registers, a backwards dataflow problem. All bitmaps are - referenced by the register number. */ - -struct df_lr_bb_info -{ - /* Local sets to describe the basic blocks. */ - bitmap_head def; /* The set of registers set in this block - - except artificial defs at the top. */ - bitmap_head use; /* The set of registers used in this block. */ - - /* The results of the dataflow problem. */ - bitmap_head in; /* Just before the block itself. */ - bitmap_head out; /* At the bottom of the block. */ -}; - - -/* Uninitialized registers. All bitmaps are referenced by the - register number. Anded results of the forwards and backward live - info. Note that the forwards live information is not available - separately. */ -struct df_live_bb_info -{ - /* Local sets to describe the basic blocks. */ - bitmap_head kill; /* The set of registers unset in this block. Calls, - for instance, unset registers. */ - bitmap_head gen; /* The set of registers set in this block. */ - - /* The results of the dataflow problem. */ - bitmap_head in; /* At the top of the block. */ - bitmap_head out; /* At the bottom of the block. */ -}; - - -/* Live registers, a backwards dataflow problem. These bitmaps are - indexed by 2 * regno for each pseudo and have two entries for each - pseudo. Only pseudos that have a size of 2 * UNITS_PER_WORD are - meaningfully tracked. */ - -struct df_word_lr_bb_info -{ - /* Local sets to describe the basic blocks. */ - bitmap_head def; /* The set of registers set in this block - - except artificial defs at the top. */ - bitmap_head use; /* The set of registers used in this block. */ - - /* The results of the dataflow problem. */ - bitmap_head in; /* Just before the block itself. */ - bitmap_head out; /* At the bottom of the block. */ -}; - - -/* This is used for debugging and for the dumpers to find the latest - instance so that the df info can be added to the dumps. This - should not be used by regular code. */ -extern struct df_d *df; -#define df_scan (df->problems_by_index[DF_SCAN]) -#define df_rd (df->problems_by_index[DF_RD]) -#define df_lr (df->problems_by_index[DF_LR]) -#define df_live (df->problems_by_index[DF_LIVE]) -#define df_chain (df->problems_by_index[DF_CHAIN]) -#define df_word_lr (df->problems_by_index[DF_WORD_LR]) -#define df_note (df->problems_by_index[DF_NOTE]) -#define df_md (df->problems_by_index[DF_MD]) - -/* This symbol turns on checking that each modification of the cfg has - been identified to the appropriate df routines. It is not part of - verification per se because the check that the final solution has - not changed covers this. However, if the solution is not being - properly recomputed because the cfg is being modified, adding in - calls to df_check_cfg_clean can be used to find the source of that - kind of problem. */ -#if 0 -#define DF_DEBUG_CFG -#endif - - -/* Functions defined in df-core.c. */ - -extern void df_add_problem (struct df_problem *); -extern int df_set_flags (int); -extern int df_clear_flags (int); -extern void df_set_blocks (bitmap); -extern void df_remove_problem (struct dataflow *); -extern void df_finish_pass (bool); -extern void df_analyze_problem (struct dataflow *, bitmap, int *, int); -extern void df_analyze (); -extern void df_analyze_loop (struct loop *); -extern int df_get_n_blocks (enum df_flow_dir); -extern int *df_get_postorder (enum df_flow_dir); -extern void df_simple_dataflow (enum df_flow_dir, df_init_function, - df_confluence_function_0, df_confluence_function_n, - df_transfer_function, bitmap, int *, int); -extern void df_mark_solutions_dirty (void); -extern bool df_get_bb_dirty (basic_block); -extern void df_set_bb_dirty (basic_block); -extern void df_compact_blocks (void); -extern void df_bb_replace (int, basic_block); -extern void df_bb_delete (int); -extern void df_verify (void); -#ifdef DF_DEBUG_CFG -extern void df_check_cfg_clean (void); -#endif -extern df_ref df_bb_regno_first_def_find (basic_block, unsigned int); -extern df_ref df_bb_regno_last_def_find (basic_block, unsigned int); -extern df_ref df_find_def (rtx_insn *, rtx); -extern bool df_reg_defined (rtx_insn *, rtx); -extern df_ref df_find_use (rtx_insn *, rtx); -extern bool df_reg_used (rtx_insn *, rtx); -extern void df_worklist_dataflow (struct dataflow *,bitmap, int *, int); -extern void df_print_regset (FILE *file, bitmap r); -extern void df_print_word_regset (FILE *file, bitmap r); -extern void df_dump (FILE *); -extern void df_dump_region (FILE *); -extern void df_dump_start (FILE *); -extern void df_dump_top (basic_block, FILE *); -extern void df_dump_bottom (basic_block, FILE *); -extern void df_dump_insn_top (const rtx_insn *, FILE *); -extern void df_dump_insn_bottom (const rtx_insn *, FILE *); -extern void df_refs_chain_dump (df_ref, bool, FILE *); -extern void df_regs_chain_dump (df_ref, FILE *); -extern void df_insn_debug (rtx_insn *, bool, FILE *); -extern void df_insn_debug_regno (rtx_insn *, FILE *); -extern void df_regno_debug (unsigned int, FILE *); -extern void df_ref_debug (df_ref, FILE *); -extern void debug_df_insn (rtx_insn *); -extern void debug_df_regno (unsigned int); -extern void debug_df_reg (rtx); -extern void debug_df_defno (unsigned int); -extern void debug_df_useno (unsigned int); -extern void debug_df_ref (df_ref); -extern void debug_df_chain (struct df_link *); - -/* Functions defined in df-problems.c. */ - -extern struct df_link *df_chain_create (df_ref, df_ref); -extern void df_chain_unlink (df_ref); -extern void df_chain_copy (df_ref, struct df_link *); -extern void df_grow_bb_info (struct dataflow *); -extern void df_chain_dump (struct df_link *, FILE *); -extern void df_print_bb_index (basic_block bb, FILE *file); -extern void df_rd_add_problem (void); -extern void df_rd_simulate_artificial_defs_at_top (basic_block, bitmap); -extern void df_rd_simulate_one_insn (basic_block, rtx_insn *, bitmap); -extern void df_lr_add_problem (void); -extern void df_lr_verify_transfer_functions (void); -extern void df_live_verify_transfer_functions (void); -extern void df_live_add_problem (void); -extern void df_live_set_all_dirty (void); -extern void df_chain_add_problem (unsigned int); -extern void df_word_lr_add_problem (void); -extern bool df_word_lr_mark_ref (df_ref, bool, bitmap); -extern bool df_word_lr_simulate_defs (rtx_insn *, bitmap); -extern void df_word_lr_simulate_uses (rtx_insn *, bitmap); -extern void df_word_lr_simulate_artificial_refs_at_top (basic_block, bitmap); -extern void df_word_lr_simulate_artificial_refs_at_end (basic_block, bitmap); -extern void df_note_add_problem (void); -extern void df_md_add_problem (void); -extern void df_md_simulate_artificial_defs_at_top (basic_block, bitmap); -extern void df_md_simulate_one_insn (basic_block, rtx_insn *, bitmap); -extern void df_simulate_find_noclobber_defs (rtx_insn *, bitmap); -extern void df_simulate_find_defs (rtx_insn *, bitmap); -extern void df_simulate_defs (rtx_insn *, bitmap); -extern void df_simulate_uses (rtx_insn *, bitmap); -extern void df_simulate_initialize_backwards (basic_block, bitmap); -extern void df_simulate_one_insn_backwards (basic_block, rtx_insn *, bitmap); -extern void df_simulate_finalize_backwards (basic_block, bitmap); -extern void df_simulate_initialize_forwards (basic_block, bitmap); -extern void df_simulate_one_insn_forwards (basic_block, rtx_insn *, bitmap); -extern void simulate_backwards_to_point (basic_block, regset, rtx); -extern bool can_move_insns_across (rtx_insn *, rtx_insn *, - rtx_insn *, rtx_insn *, - basic_block, regset, - regset, rtx_insn **); -/* Functions defined in df-scan.c. */ - -extern void df_scan_alloc (bitmap); -extern void df_scan_add_problem (void); -extern void df_grow_reg_info (void); -extern void df_grow_insn_info (void); -extern void df_scan_blocks (void); -extern void df_uses_create (rtx *, rtx_insn *, int); -extern struct df_insn_info * df_insn_create_insn_record (rtx_insn *); -extern void df_insn_delete (rtx_insn *); -extern void df_bb_refs_record (int, bool); -extern bool df_insn_rescan (rtx_insn *); -extern bool df_insn_rescan_debug_internal (rtx_insn *); -extern void df_insn_rescan_all (void); -extern void df_process_deferred_rescans (void); -extern void df_recompute_luids (basic_block); -extern void df_insn_change_bb (rtx_insn *, basic_block); -extern void df_maybe_reorganize_use_refs (enum df_ref_order); -extern void df_maybe_reorganize_def_refs (enum df_ref_order); -extern void df_ref_change_reg_with_loc (int, int, rtx); -extern void df_notes_rescan (rtx_insn *); -extern void df_hard_reg_init (void); -extern void df_update_entry_block_defs (void); -extern void df_update_exit_block_uses (void); -extern void df_update_entry_exit_and_calls (void); -extern bool df_hard_reg_used_p (unsigned int); -extern unsigned int df_hard_reg_used_count (unsigned int); -extern bool df_regs_ever_live_p (unsigned int); -extern void df_set_regs_ever_live (unsigned int, bool); -extern void df_compute_regs_ever_live (bool); -extern bool df_read_modify_subreg_p (rtx); -extern void df_scan_verify (void); - - -/*---------------------------------------------------------------------------- - Public functions access functions for the dataflow problems. -----------------------------------------------------------------------------*/ - -static inline struct df_scan_bb_info * -df_scan_get_bb_info (unsigned int index) -{ - if (index < df_scan->block_info_size) - return &((struct df_scan_bb_info *) df_scan->block_info)[index]; - else - return NULL; -} - -static inline struct df_rd_bb_info * -df_rd_get_bb_info (unsigned int index) -{ - if (index < df_rd->block_info_size) - return &((struct df_rd_bb_info *) df_rd->block_info)[index]; - else - return NULL; -} - -static inline struct df_lr_bb_info * -df_lr_get_bb_info (unsigned int index) -{ - if (index < df_lr->block_info_size) - return &((struct df_lr_bb_info *) df_lr->block_info)[index]; - else - return NULL; -} - -static inline struct df_md_bb_info * -df_md_get_bb_info (unsigned int index) -{ - if (index < df_md->block_info_size) - return &((struct df_md_bb_info *) df_md->block_info)[index]; - else - return NULL; -} - -static inline struct df_live_bb_info * -df_live_get_bb_info (unsigned int index) -{ - if (index < df_live->block_info_size) - return &((struct df_live_bb_info *) df_live->block_info)[index]; - else - return NULL; -} - -static inline struct df_word_lr_bb_info * -df_word_lr_get_bb_info (unsigned int index) -{ - if (index < df_word_lr->block_info_size) - return &((struct df_word_lr_bb_info *) df_word_lr->block_info)[index]; - else - return NULL; -} - -/* Get the live at out set for BB no matter what problem happens to be - defined. This function is used by the register allocators who - choose different dataflow problems depending on the optimization - level. */ - -static inline bitmap -df_get_live_out (basic_block bb) -{ - gcc_checking_assert (df_lr); - - if (df_live) - return DF_LIVE_OUT (bb); - else - return DF_LR_OUT (bb); -} - -/* Get the live at in set for BB no matter what problem happens to be - defined. This function is used by the register allocators who - choose different dataflow problems depending on the optimization - level. */ - -static inline bitmap -df_get_live_in (basic_block bb) -{ - gcc_checking_assert (df_lr); - - if (df_live) - return DF_LIVE_IN (bb); - else - return DF_LR_IN (bb); -} - -/* Get basic block info. */ -/* Get the artificial defs for a basic block. */ - -static inline df_ref -df_get_artificial_defs (unsigned int bb_index) -{ - return df_scan_get_bb_info (bb_index)->artificial_defs; -} - - -/* Get the artificial uses for a basic block. */ - -static inline df_ref -df_get_artificial_uses (unsigned int bb_index) -{ - return df_scan_get_bb_info (bb_index)->artificial_uses; -} - -/* If INSN defines exactly one register, return the associated reference, - otherwise return null. */ - -static inline df_ref -df_single_def (const df_insn_info *info) -{ - df_ref defs = DF_INSN_INFO_DEFS (info); - return defs && !DF_REF_NEXT_LOC (defs) ? defs : NULL; -} - -/* If INSN uses exactly one register, return the associated reference, - otherwise return null. */ - -static inline df_ref -df_single_use (const df_insn_info *info) -{ - df_ref uses = DF_INSN_INFO_USES (info); - return uses && !DF_REF_NEXT_LOC (uses) ? uses : NULL; -} - -/* web */ - -class web_entry_base -{ - private: - /* Reference to the parent in the union/find tree. */ - web_entry_base *pred_pvt; - - public: - /* Accessors. */ - web_entry_base *pred () { return pred_pvt; } - void set_pred (web_entry_base *p) { pred_pvt = p; } - - /* Find representative in union-find tree. */ - web_entry_base *unionfind_root (); - - /* Union with another set, returning TRUE if they are already unioned. */ - friend bool unionfind_union (web_entry_base *first, web_entry_base *second); -}; - -#endif /* GCC_DF_H */ diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/dfp.h b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/dfp.h deleted file mode 100644 index 013de8b..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/dfp.h +++ /dev/null @@ -1,49 +0,0 @@ -/* Decimal floating point support functions for GNU compiler. - Copyright (C) 2005-2015 Free Software Foundation, Inc. - -This file is part of GCC. - -GCC is free software; you can redistribute it and/or modify it under -the terms of the GNU General Public License as published by the Free -Software Foundation; either version 3, or (at your option) any later -version. - -GCC is distributed in the hope that it will be useful, but WITHOUT ANY -WARRANTY; without even the implied warranty of MERCHANTABILITY or -FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -for more details. - -You should have received a copy of the GNU General Public License -along with GCC; see the file COPYING3. If not see -. */ - -#ifndef GCC_DFP_H -#define GCC_DFP_H - -/* Encode REAL_VALUE_TYPEs into 32/64/128-bit IEEE 754 encoded values. */ -void encode_decimal32 (const struct real_format *fmt, long *, const REAL_VALUE_TYPE *); -void encode_decimal64 (const struct real_format *fmt, long *, const REAL_VALUE_TYPE *); -void decode_decimal128 (const struct real_format *, REAL_VALUE_TYPE *, const long *); - -/* Decode 32/64/128-bit IEEE 754 encoded values into REAL_VALUE_TYPEs. */ -void decode_decimal32 (const struct real_format *, REAL_VALUE_TYPE *, const long *); -void decode_decimal64 (const struct real_format *, REAL_VALUE_TYPE *, const long *); -void encode_decimal128 (const struct real_format *fmt, long *, const REAL_VALUE_TYPE *); - -/* Arithmetic and conversion functions. */ -int decimal_do_compare (const REAL_VALUE_TYPE *, const REAL_VALUE_TYPE *, int); -void decimal_real_from_string (REAL_VALUE_TYPE *, const char *); -void decimal_round_for_format (const struct real_format *, REAL_VALUE_TYPE *); -void decimal_real_convert (REAL_VALUE_TYPE *, machine_mode, const REAL_VALUE_TYPE *); -void decimal_real_to_decimal (char *, const REAL_VALUE_TYPE *, size_t, size_t, int); -void decimal_do_fix_trunc (REAL_VALUE_TYPE *, const REAL_VALUE_TYPE *); -void decimal_real_maxval (REAL_VALUE_TYPE *, int, machine_mode); -wide_int decimal_real_to_integer (const REAL_VALUE_TYPE *, bool *, int); -HOST_WIDE_INT decimal_real_to_integer (const REAL_VALUE_TYPE *); - -#ifdef TREE_CODE -bool decimal_real_arithmetic (REAL_VALUE_TYPE *, enum tree_code, const REAL_VALUE_TYPE *, - const REAL_VALUE_TYPE *); -#endif - -#endif /* GCC_DFP_H */ diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/diagnostic-color.h b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/diagnostic-color.h deleted file mode 100644 index de7f8b9..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/diagnostic-color.h +++ /dev/null @@ -1,65 +0,0 @@ -/* Copyright (C) 2013-2015 Free Software Foundation, Inc. - Contributed by Manuel Lopez-Ibanez - -This file is part of GCC. - -GCC is free software; you can redistribute it and/or modify it under -the terms of the GNU General Public License as published by the Free -Software Foundation; either version 3, or (at your option) any later -version. - -GCC is distributed in the hope that it will be useful, but WITHOUT ANY -WARRANTY; without even the implied warranty of MERCHANTABILITY or -FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -for more details. - -You should have received a copy of the GNU General Public License -along with GCC; see the file COPYING3. If not see -. */ - -/* Based on code from: */ -/* grep.c - main driver file for grep. - Copyright (C) 1992-2015 Free Software Foundation, Inc. - - This program is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3, or (at your option) - any later version. - - This program is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program; if not, write to the Free Software - Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA - 02110-1301, USA. - - Written July 1992 by Mike Haertel. */ - -#ifndef GCC_DIAGNOSTIC_COLOR_H -#define GCC_DIAGNOSTIC_COLOR_H - -/* Whether to add color to diagnostics: - o DIAGNOSTICS_COLOR_NO: never - o DIAGNOSTICS_COLOR_YES: always - o DIAGNOSTICS_COLOR_AUTO: depending on the output stream. */ -typedef enum -{ - DIAGNOSTICS_COLOR_NO = 0, - DIAGNOSTICS_COLOR_YES = 1, - DIAGNOSTICS_COLOR_AUTO = 2 -} diagnostic_color_rule_t; - -const char *colorize_start (bool, const char *, size_t); -const char *colorize_stop (bool); -bool colorize_init (diagnostic_color_rule_t); - -inline const char * -colorize_start (bool show_color, const char *name) -{ - return colorize_start (show_color, name, strlen (name)); -} - -#endif /* ! GCC_DIAGNOSTIC_COLOR_H */ diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/diagnostic-core.h b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/diagnostic-core.h deleted file mode 100644 index 09a6867..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/diagnostic-core.h +++ /dev/null @@ -1,93 +0,0 @@ -/* Declarations of core diagnostic functionality for code that does - not need to deal with diagnostic contexts or diagnostic info - structures. - Copyright (C) 1998-2015 Free Software Foundation, Inc. - -This file is part of GCC. - -GCC is free software; you can redistribute it and/or modify it under -the terms of the GNU General Public License as published by the Free -Software Foundation; either version 3, or (at your option) any later -version. - -GCC is distributed in the hope that it will be useful, but WITHOUT ANY -WARRANTY; without even the implied warranty of MERCHANTABILITY or -FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -for more details. - -You should have received a copy of the GNU General Public License -along with GCC; see the file COPYING3. If not see -. */ - -#ifndef GCC_DIAGNOSTIC_CORE_H -#define GCC_DIAGNOSTIC_CORE_H - -#include "input.h" -#include "bversion.h" - -/* Constants used to discriminate diagnostics. */ -typedef enum -{ -#define DEFINE_DIAGNOSTIC_KIND(K, msgid, C) K, -#include "diagnostic.def" -#undef DEFINE_DIAGNOSTIC_KIND - DK_LAST_DIAGNOSTIC_KIND, - /* This is used for tagging pragma pops in the diagnostic - classification history chain. */ - DK_POP -} diagnostic_t; - -extern const char *progname; - -extern const char *trim_filename (const char *); - -/* If we haven't already defined a front-end-specific diagnostics - style, use the generic one. */ -#ifndef GCC_DIAG_STYLE -#define GCC_DIAG_STYLE __gcc_tdiag__ -#endif -/* None of these functions are suitable for ATTRIBUTE_PRINTF, because - each language front end can extend them with its own set of format - specifiers. We must use custom format checks. */ -#if (ENABLE_CHECKING && GCC_VERSION >= 4001) || GCC_VERSION == BUILDING_GCC_VERSION -#define ATTRIBUTE_GCC_DIAG(m, n) __attribute__ ((__format__ (GCC_DIAG_STYLE, m, n))) ATTRIBUTE_NONNULL(m) -#else -#define ATTRIBUTE_GCC_DIAG(m, n) ATTRIBUTE_NONNULL(m) -#endif -extern void internal_error (const char *, ...) ATTRIBUTE_GCC_DIAG(1,2) - ATTRIBUTE_NORETURN; -extern void internal_error_no_backtrace (const char *, ...) - ATTRIBUTE_GCC_DIAG(1,2) ATTRIBUTE_NORETURN; -/* Pass one of the OPT_W* from options.h as the first parameter. */ -extern bool warning (int, const char *, ...) ATTRIBUTE_GCC_DIAG(2,3); -extern bool warning_n (location_t, int, int, const char *, const char *, ...) - ATTRIBUTE_GCC_DIAG(4,6) ATTRIBUTE_GCC_DIAG(5,6); -extern bool warning_at (location_t, int, const char *, ...) - ATTRIBUTE_GCC_DIAG(3,4); -extern void error (const char *, ...) ATTRIBUTE_GCC_DIAG(1,2); -extern void error_n (location_t, int, const char *, const char *, ...) - ATTRIBUTE_GCC_DIAG(3,5) ATTRIBUTE_GCC_DIAG(4,5); -extern void error_at (location_t, const char *, ...) ATTRIBUTE_GCC_DIAG(2,3); -extern void fatal_error (location_t, const char *, ...) ATTRIBUTE_GCC_DIAG(2,3) - ATTRIBUTE_NORETURN; -/* Pass one of the OPT_W* from options.h as the second parameter. */ -extern bool pedwarn (location_t, int, const char *, ...) - ATTRIBUTE_GCC_DIAG(3,4); -extern bool permerror (location_t, const char *, ...) ATTRIBUTE_GCC_DIAG(2,3); -extern void sorry (const char *, ...) ATTRIBUTE_GCC_DIAG(1,2); -extern void inform (location_t, const char *, ...) ATTRIBUTE_GCC_DIAG(2,3); -extern void inform_n (location_t, int, const char *, const char *, ...) - ATTRIBUTE_GCC_DIAG(3,5) ATTRIBUTE_GCC_DIAG(4,5); -extern void verbatim (const char *, ...) ATTRIBUTE_GCC_DIAG(1,2); -extern bool emit_diagnostic (diagnostic_t, location_t, int, - const char *, ...) ATTRIBUTE_GCC_DIAG(4,5); -extern bool seen_error (void); - -#ifdef BUFSIZ - /* N.B. Unlike all the others, fnotice is just gettext+fprintf, and - therefore it can have ATTRIBUTE_PRINTF. */ -extern void fnotice (FILE *, const char *, ...) - ATTRIBUTE_PRINTF_2; -#endif - -#endif /* ! GCC_DIAGNOSTIC_CORE_H */ diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/diagnostic.def b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/diagnostic.def deleted file mode 100644 index b90ca69..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/diagnostic.def +++ /dev/null @@ -1,50 +0,0 @@ -/* Copyright (C) 2001-2015 Free Software Foundation, Inc. - -This file is part of GCC. - -GCC is free software; you can redistribute it and/or modify it under -the terms of the GNU General Public License as published by the Free -Software Foundation; either version 3, or (at your option) any later -version. - -GCC is distributed in the hope that it will be useful, but WITHOUT ANY -WARRANTY; without even the implied warranty of MERCHANTABILITY or -FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -for more details. - -You should have received a copy of the GNU General Public License -along with GCC; see the file COPYING3. If not see -. */ - -/* DK_UNSPECIFIED must be first so it has a value of zero. We never - assign this kind to an actual diagnostic, we only use this in - variables that can hold a kind, to mean they have yet to have a - kind specified. I.e. they're uninitialized. Within the diagnostic - machinery, this kind also means "don't change the existing kind", - meaning "no change is specified". */ -DEFINE_DIAGNOSTIC_KIND (DK_UNSPECIFIED, "", NULL) - -/* If a diagnostic is set to DK_IGNORED, it won't get reported at all. - This is used by the diagnostic machinery when it wants to disable a - diagnostic without disabling the option which causes it. */ -DEFINE_DIAGNOSTIC_KIND (DK_IGNORED, "", NULL) - -/* The remainder are real diagnostic types. */ -DEFINE_DIAGNOSTIC_KIND (DK_FATAL, "fatal error: ", "error") -DEFINE_DIAGNOSTIC_KIND (DK_ICE, "internal compiler error: ", "error") -DEFINE_DIAGNOSTIC_KIND (DK_ERROR, "error: ", "error") -DEFINE_DIAGNOSTIC_KIND (DK_SORRY, "sorry, unimplemented: ", "error") -DEFINE_DIAGNOSTIC_KIND (DK_WARNING, "warning: ", "warning") -DEFINE_DIAGNOSTIC_KIND (DK_ANACHRONISM, "anachronism: ", "warning") -DEFINE_DIAGNOSTIC_KIND (DK_NOTE, "note: ", "note") -DEFINE_DIAGNOSTIC_KIND (DK_DEBUG, "debug: ", "note") -/* These two would be re-classified as DK_WARNING or DK_ERROR, so the -prefix does not matter. */ -DEFINE_DIAGNOSTIC_KIND (DK_PEDWARN, "pedwarn: ", NULL) -DEFINE_DIAGNOSTIC_KIND (DK_PERMERROR, "permerror: ", NULL) -/* This one is just for counting DK_WARNING promoted to DK_ERROR - due to -Werror and -Werror=warning. */ -DEFINE_DIAGNOSTIC_KIND (DK_WERROR, "error: ", NULL) -/* This is like DK_ICE, but backtrace is not printed. Used in the driver - when reporting fatal signal in the compiler. */ -DEFINE_DIAGNOSTIC_KIND (DK_ICE_NOBT, "internal compiler error: ", "error") diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/diagnostic.h b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/diagnostic.h deleted file mode 100644 index 0ace012..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/diagnostic.h +++ /dev/null @@ -1,317 +0,0 @@ -/* Various declarations for language-independent diagnostics subroutines. - Copyright (C) 2000-2015 Free Software Foundation, Inc. - Contributed by Gabriel Dos Reis - -This file is part of GCC. - -GCC is free software; you can redistribute it and/or modify it under -the terms of the GNU General Public License as published by the Free -Software Foundation; either version 3, or (at your option) any later -version. - -GCC is distributed in the hope that it will be useful, but WITHOUT ANY -WARRANTY; without even the implied warranty of MERCHANTABILITY or -FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -for more details. - -You should have received a copy of the GNU General Public License -along with GCC; see the file COPYING3. If not see -. */ - -#ifndef GCC_DIAGNOSTIC_H -#define GCC_DIAGNOSTIC_H - -#include "pretty-print.h" -#include "diagnostic-core.h" - -/* A diagnostic is described by the MESSAGE to send, the FILE and LINE of - its context and its KIND (ice, error, warning, note, ...) See complete - list in diagnostic.def. */ -struct diagnostic_info -{ - text_info message; - location_t location; - unsigned int override_column; - /* Auxiliary data for client. */ - void *x_data; - /* The kind of diagnostic it is about. */ - diagnostic_t kind; - /* Which OPT_* directly controls this diagnostic. */ - int option_index; -}; - -/* Each time a diagnostic's classification is changed with a pragma, - we record the change and the location of the change in an array of - these structs. */ -struct diagnostic_classification_change_t -{ - location_t location; - int option; - diagnostic_t kind; -}; - -/* Forward declarations. */ -typedef void (*diagnostic_starter_fn) (diagnostic_context *, - diagnostic_info *); -typedef diagnostic_starter_fn diagnostic_finalizer_fn; - -/* This data structure bundles altogether any information relevant to - the context of a diagnostic message. */ -struct diagnostic_context -{ - /* Where most of the diagnostic formatting work is done. */ - pretty_printer *printer; - - /* The number of times we have issued diagnostics. */ - int diagnostic_count[DK_LAST_DIAGNOSTIC_KIND]; - - /* True if it has been requested that warnings be treated as errors. */ - bool warning_as_error_requested; - - /* The number of option indexes that can be passed to warning() et - al. */ - int n_opts; - - /* For each option index that can be passed to warning() et al - (OPT_* from options.h when using this code with the core GCC - options), this array may contain a new kind that the diagnostic - should be changed to before reporting, or DK_UNSPECIFIED to leave - it as the reported kind, or DK_IGNORED to not report it at - all. */ - diagnostic_t *classify_diagnostic; - - /* History of all changes to the classifications above. This list - is stored in location-order, so we can search it, either - binary-wise or end-to-front, to find the most recent - classification for a given diagnostic, given the location of the - diagnostic. */ - diagnostic_classification_change_t *classification_history; - - /* The size of the above array. */ - int n_classification_history; - - /* For pragma push/pop. */ - int *push_list; - int n_push; - - /* True if we should print the source line with a caret indicating - the location. */ - bool show_caret; - - /* Maximum width of the source line printed. */ - int caret_max_width; - - /* Character used for caret diagnostics. */ - char caret_char; - - /* True if we should print the command line option which controls - each diagnostic, if known. */ - bool show_option_requested; - - /* True if we should raise a SIGABRT on errors. */ - bool abort_on_error; - - /* True if we should show the column number on diagnostics. */ - bool show_column; - - /* True if pedwarns are errors. */ - bool pedantic_errors; - - /* True if permerrors are warnings. */ - bool permissive; - - /* The index of the option to associate with turning permerrors into - warnings. */ - int opt_permissive; - - /* True if errors are fatal. */ - bool fatal_errors; - - /* True if all warnings should be disabled. */ - bool dc_inhibit_warnings; - - /* True if warnings should be given in system headers. */ - bool dc_warn_system_headers; - - /* Maximum number of errors to report. */ - unsigned int max_errors; - - /* This function is called before any message is printed out. It is - responsible for preparing message prefix and such. For example, it - might say: - In file included from "/usr/local/include/curses.h:5: - from "/home/gdr/src/nifty_printer.h:56: - ... - */ - diagnostic_starter_fn begin_diagnostic; - - /* This function is called after the diagnostic message is printed. */ - diagnostic_finalizer_fn end_diagnostic; - - /* Client hook to report an internal error. */ - void (*internal_error) (diagnostic_context *, const char *, va_list *); - - /* Client hook to say whether the option controlling a diagnostic is - enabled. Returns nonzero if enabled, zero if disabled. */ - int (*option_enabled) (int, void *); - - /* Client information to pass as second argument to - option_enabled. */ - void *option_state; - - /* Client hook to return the name of an option that controls a - diagnostic. Returns malloced memory. The first diagnostic_t - argument is the kind of diagnostic before any reclassification - (of warnings as errors, etc.); the second is the kind after any - reclassification. May return NULL if no name is to be printed. - May be passed 0 as well as the index of a particular option. */ - char *(*option_name) (diagnostic_context *, int, diagnostic_t, diagnostic_t); - - /* Auxiliary data for client. */ - void *x_data; - - /* Used to detect that the last caret was printed at the same location. */ - location_t last_location; - - /* Used to detect when the input file stack has changed since last - described. */ - const struct line_map *last_module; - - int lock; - - bool inhibit_notes_p; -}; - -static inline void -diagnostic_inhibit_notes (diagnostic_context * context) -{ - context->inhibit_notes_p = true; -} - - -/* Client supplied function to announce a diagnostic. */ -#define diagnostic_starter(DC) (DC)->begin_diagnostic - -/* Client supplied function called after a diagnostic message is - displayed. */ -#define diagnostic_finalizer(DC) (DC)->end_diagnostic - -/* Extension hooks for client. */ -#define diagnostic_context_auxiliary_data(DC) (DC)->x_data -#define diagnostic_info_auxiliary_data(DI) (DI)->x_data - -/* Same as pp_format_decoder. Works on 'diagnostic_context *'. */ -#define diagnostic_format_decoder(DC) ((DC)->printer->format_decoder) - -/* Same as output_prefixing_rule. Works on 'diagnostic_context *'. */ -#define diagnostic_prefixing_rule(DC) ((DC)->printer->wrapping.rule) - -/* Maximum characters per line in automatic line wrapping mode. - Zero means don't wrap lines. */ -#define diagnostic_line_cutoff(DC) ((DC)->printer->wrapping.line_cutoff) - -#define diagnostic_flush_buffer(DC) pp_flush ((DC)->printer) - -/* True if the last module or file in which a diagnostic was reported is - different from the current one. */ -#define diagnostic_last_module_changed(DC, MAP) \ - ((DC)->last_module != MAP) - -/* Remember the current module or file as being the last one in which we - report a diagnostic. */ -#define diagnostic_set_last_module(DC, MAP) \ - (DC)->last_module = MAP - -/* Raise SIGABRT on any diagnostic of severity DK_ERROR or higher. */ -#define diagnostic_abort_on_error(DC) \ - (DC)->abort_on_error = true - -/* This diagnostic_context is used by front-ends that directly output - diagnostic messages without going through `error', `warning', - and similar functions. */ -extern diagnostic_context *global_dc; - -/* The total count of a KIND of diagnostics emitted so far. */ -#define diagnostic_kind_count(DC, DK) (DC)->diagnostic_count[(int) (DK)] - -/* The number of errors that have been issued so far. Ideally, these - would take a diagnostic_context as an argument. */ -#define errorcount diagnostic_kind_count (global_dc, DK_ERROR) -/* Similarly, but for warnings. */ -#define warningcount diagnostic_kind_count (global_dc, DK_WARNING) -/* Similarly, but for warnings promoted to errors. */ -#define werrorcount diagnostic_kind_count (global_dc, DK_WERROR) -/* Similarly, but for sorrys. */ -#define sorrycount diagnostic_kind_count (global_dc, DK_SORRY) - -/* Returns nonzero if warnings should be emitted. */ -#define diagnostic_report_warnings_p(DC, LOC) \ - (!(DC)->dc_inhibit_warnings \ - && !(in_system_header_at (LOC) && !(DC)->dc_warn_system_headers)) - -#define report_diagnostic(D) diagnostic_report_diagnostic (global_dc, D) - -/* Override the column number to be used for reporting a - diagnostic. */ -#define diagnostic_override_column(DI, COL) (DI)->override_column = (COL) - -/* Override the option index to be used for reporting a - diagnostic. */ -#define diagnostic_override_option_index(DI, OPTIDX) \ - ((DI)->option_index = (OPTIDX)) - -/* Diagnostic related functions. */ -extern void diagnostic_initialize (diagnostic_context *, int); -extern void diagnostic_color_init (diagnostic_context *, int value = -1); -extern void diagnostic_finish (diagnostic_context *); -extern void diagnostic_report_current_module (diagnostic_context *, location_t); -extern void diagnostic_show_locus (diagnostic_context *, const diagnostic_info *); - -/* Force diagnostics controlled by OPTIDX to be kind KIND. */ -extern diagnostic_t diagnostic_classify_diagnostic (diagnostic_context *, - int /* optidx */, - diagnostic_t /* kind */, - location_t); -extern void diagnostic_push_diagnostics (diagnostic_context *, location_t); -extern void diagnostic_pop_diagnostics (diagnostic_context *, location_t); -extern bool diagnostic_report_diagnostic (diagnostic_context *, - diagnostic_info *); -#ifdef ATTRIBUTE_GCC_DIAG -extern void diagnostic_set_info (diagnostic_info *, const char *, va_list *, - location_t, diagnostic_t) ATTRIBUTE_GCC_DIAG(2,0); -extern void diagnostic_set_info_translated (diagnostic_info *, const char *, - va_list *, location_t, - diagnostic_t) - ATTRIBUTE_GCC_DIAG(2,0); -extern void diagnostic_append_note (diagnostic_context *, location_t, - const char *, ...) ATTRIBUTE_GCC_DIAG(3,4); -#endif -extern char *diagnostic_build_prefix (diagnostic_context *, const diagnostic_info *); -void default_diagnostic_starter (diagnostic_context *, diagnostic_info *); -void default_diagnostic_finalizer (diagnostic_context *, diagnostic_info *); -void diagnostic_set_caret_max_width (diagnostic_context *context, int value); -void diagnostic_action_after_output (diagnostic_context *, diagnostic_t); - -void diagnostic_file_cache_fini (void); - -int get_terminal_width (void); - -/* Expand the location of this diagnostic. Use this function for consistency. */ - -static inline expanded_location -diagnostic_expand_location (const diagnostic_info * diagnostic) -{ - expanded_location s - = expand_location_to_spelling_point (diagnostic->location); - if (diagnostic->override_column) - s.column = diagnostic->override_column; - return s; -} - -/* Pure text formatting support functions. */ -extern char *file_name_as_prefix (diagnostic_context *, const char *); - -extern char *build_message_string (const char *, ...) ATTRIBUTE_PRINTF_1; - - -#endif /* ! GCC_DIAGNOSTIC_H */ diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/dojump.h b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/dojump.h deleted file mode 100644 index 74d3f37..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/dojump.h +++ /dev/null @@ -1,78 +0,0 @@ -/* Export function prototypes from dojump.c. - Copyright (C) 2015-2016 Free Software Foundation, Inc. - -This file is part of GCC. - -GCC is free software; you can redistribute it and/or modify it under -the terms of the GNU General Public License as published by the Free -Software Foundation; either version 3, or (at your option) any later -version. - -GCC is distributed in the hope that it will be useful, but WITHOUT ANY -WARRANTY; without even the implied warranty of MERCHANTABILITY or -FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -for more details. - -You should have received a copy of the GNU General Public License -along with GCC; see the file COPYING3. If not see -. */ - -#ifndef GCC_DOJUMP_H -#define GCC_DOJUMP_H - -/* At the start of a function, record that we have no previously-pushed - arguments waiting to be popped. */ -extern void init_pending_stack_adjust (void); - -/* Discard any pending stack adjustment. */ -extern void discard_pending_stack_adjust (void); - -/* When exiting from function, if safe, clear out any pending stack adjust - so the adjustment won't get done. */ -extern void clear_pending_stack_adjust (void); - -/* Pop any previously-pushed arguments that have not been popped yet. */ -extern void do_pending_stack_adjust (void); - -/* Struct for saving/restoring of pending_stack_adjust/stack_pointer_delta - values. */ - -struct saved_pending_stack_adjust -{ - /* Saved value of pending_stack_adjust. */ - int x_pending_stack_adjust; - - /* Saved value of stack_pointer_delta. */ - int x_stack_pointer_delta; -}; - -/* Remember pending_stack_adjust/stack_pointer_delta. - To be used around code that may call do_pending_stack_adjust (), - but the generated code could be discarded e.g. using delete_insns_since. */ - -extern void save_pending_stack_adjust (saved_pending_stack_adjust *); - -/* Restore the saved pending_stack_adjust/stack_pointer_delta. */ - -extern void restore_pending_stack_adjust (saved_pending_stack_adjust *); - -/* Generate code to evaluate EXP and jump to LABEL if the value is zero. */ -extern void jumpifnot (tree, rtx, int); -extern void jumpifnot_1 (enum tree_code, tree, tree, rtx, int); - -/* Generate code to evaluate EXP and jump to LABEL if the value is nonzero. */ -extern void jumpif (tree, rtx, int); -extern void jumpif_1 (enum tree_code, tree, tree, rtx, int); - -/* Generate code to evaluate EXP and jump to IF_FALSE_LABEL if - the result is zero, or IF_TRUE_LABEL if the result is one. */ -extern void do_jump (tree, rtx, rtx, int); -extern void do_jump_1 (enum tree_code, tree, tree, rtx, rtx, int); - -extern void do_compare_rtx_and_jump (rtx, rtx, enum rtx_code, int, - machine_mode, rtx, rtx, rtx, int); - -extern bool split_comparison (enum rtx_code, machine_mode, - enum rtx_code *, enum rtx_code *); - -#endif /* GCC_DOJUMP_H */ diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/dominance.h b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/dominance.h deleted file mode 100644 index 37e138b..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/dominance.h +++ /dev/null @@ -1,78 +0,0 @@ -/* Calculate (post)dominators header file. - Copyright (C) 2014-2015 Free Software Foundation, Inc. - - This file is part of GCC. - - GCC is free software; you can redistribute it and/or modify it - under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3, or (at your option) - any later version. - - GCC is distributed in the hope that it will be useful, but WITHOUT - ANY WARRANTY; without even the implied warranty of MERCHANTABILITY - or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public - License for more details. - - You should have received a copy of the GNU General Public License - along with GCC; see the file COPYING3. If not see - . */ - -#ifndef GCC_DOMINANCE_H -#define GCC_DOMINANCE_H - -enum cdi_direction -{ - CDI_DOMINATORS = 1, - CDI_POST_DOMINATORS = 2 -}; - -/* State of dominance information. */ - -enum dom_state -{ - DOM_NONE, /* Not computed at all. */ - DOM_NO_FAST_QUERY, /* The data is OK, but the fast query data are not usable. */ - DOM_OK /* Everything is ok. */ -}; - -extern void calculate_dominance_info (enum cdi_direction); -extern void free_dominance_info (function *, enum cdi_direction); -extern void free_dominance_info (enum cdi_direction); -extern basic_block get_immediate_dominator (enum cdi_direction, basic_block); -extern void set_immediate_dominator (enum cdi_direction, basic_block, - basic_block); -extern vec get_dominated_by (enum cdi_direction, basic_block); -extern vec get_dominated_by_region (enum cdi_direction, - basic_block *, - unsigned); -extern vec get_dominated_to_depth (enum cdi_direction, - basic_block, int); -extern vec get_all_dominated_blocks (enum cdi_direction, - basic_block); -extern void redirect_immediate_dominators (enum cdi_direction, basic_block, - basic_block); -extern basic_block nearest_common_dominator (enum cdi_direction, - basic_block, basic_block); -extern basic_block nearest_common_dominator_for_set (enum cdi_direction, - bitmap); -extern bool dominated_by_p (enum cdi_direction, const_basic_block, - const_basic_block); -unsigned bb_dom_dfs_in (enum cdi_direction, basic_block); -unsigned bb_dom_dfs_out (enum cdi_direction, basic_block); -extern void verify_dominators (enum cdi_direction); -basic_block recompute_dominator (enum cdi_direction, basic_block); -extern void iterate_fix_dominators (enum cdi_direction, - vec , bool); -extern void add_to_dominance_info (enum cdi_direction, basic_block); -extern void delete_from_dominance_info (enum cdi_direction, basic_block); -extern basic_block first_dom_son (enum cdi_direction, basic_block); -extern basic_block next_dom_son (enum cdi_direction, basic_block); -extern enum dom_state dom_info_state (function *, enum cdi_direction); -extern enum dom_state dom_info_state (enum cdi_direction); -extern void set_dom_info_availability (enum cdi_direction, enum dom_state); -extern bool dom_info_available_p (function *, enum cdi_direction); -extern bool dom_info_available_p (enum cdi_direction); - - - -#endif /* GCC_DOMINANCE_H */ diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/domwalk.h b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/domwalk.h deleted file mode 100644 index 71a7c47..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/domwalk.h +++ /dev/null @@ -1,52 +0,0 @@ -/* Generic dominator tree walker - Copyright (C) 2003-2015 Free Software Foundation, Inc. - Contributed by Diego Novillo - -This file is part of GCC. - -GCC is free software; you can redistribute it and/or modify -it under the terms of the GNU General Public License as published by -the Free Software Foundation; either version 3, or (at your option) -any later version. - -GCC is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU General Public License for more details. - -You should have received a copy of the GNU General Public License -along with GCC; see the file COPYING3. If not see -. */ - -#ifndef GCC_DOM_WALK_H -#define GCC_DOM_WALK_H - -/** - * This is the main class for the dominator walker. It is expected that - * consumers will have a custom class inheriting from it, which will over ride - * at least one of before_dom_children and after_dom_children to implement the - * custom behavior. - */ -class dom_walker -{ -public: - dom_walker (cdi_direction direction) : m_dom_direction (direction) {} - - /* Walk the dominator tree. */ - void walk (basic_block); - - /* Function to call before the recursive walk of the dominator children. */ - virtual void before_dom_children (basic_block) {} - - /* Function to call after the recursive walk of the dominator children. */ - virtual void after_dom_children (basic_block) {} - -private: - /* This is the direction of the dominator tree we want to walk. i.e., - if it is set to CDI_DOMINATORS, then we walk the dominator tree, - if it is set to CDI_POST_DOMINATORS, then we walk the post - dominator tree. */ - const ENUM_BITFIELD (cdi_direction) m_dom_direction : 2; -}; - -#endif diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/double-int.h b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/double-int.h deleted file mode 100644 index 6db4b9e..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/double-int.h +++ /dev/null @@ -1,472 +0,0 @@ -/* Operations with long integers. - Copyright (C) 2006-2015 Free Software Foundation, Inc. - -This file is part of GCC. - -GCC is free software; you can redistribute it and/or modify it -under the terms of the GNU General Public License as published by the -Free Software Foundation; either version 3, or (at your option) any -later version. - -GCC is distributed in the hope that it will be useful, but WITHOUT -ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -for more details. - -You should have received a copy of the GNU General Public License -along with GCC; see the file COPYING3. If not see -. */ - -#ifndef DOUBLE_INT_H -#define DOUBLE_INT_H - -#include "wide-int.h" - -/* A large integer is currently represented as a pair of HOST_WIDE_INTs. - It therefore represents a number with precision of - 2 * HOST_BITS_PER_WIDE_INT bits (it is however possible that the - internal representation will change, if numbers with greater precision - are needed, so the users should not rely on it). The representation does - not contain any information about signedness of the represented value, so - it can be used to represent both signed and unsigned numbers. For - operations where the results depend on signedness (division, comparisons), - it must be specified separately. For each such operation, there are three - versions of the function -- double_int_op, that takes an extra UNS argument - giving the signedness of the values, and double_int_sop and double_int_uop - that stand for its specializations for signed and unsigned values. - - You may also represent with numbers in smaller precision using double_int. - You however need to use double_int_ext (that fills in the bits of the - number over the prescribed precision with zeros or with the sign bit) before - operations that do not perform arithmetics modulo 2^precision (comparisons, - division), and possibly before storing the results, if you want to keep - them in some canonical form). In general, the signedness of double_int_ext - should match the signedness of the operation. - - ??? The components of double_int differ in signedness mostly for - historical reasons (they replace an older structure used to represent - numbers with precision higher than HOST_WIDE_INT). It might be less - confusing to have them both signed or both unsigned. */ - -struct double_int -{ - /* Normally, we would define constructors to create instances. - Two things prevent us from doing so. - First, defining a constructor makes the class non-POD in C++03, - and we certainly want double_int to be a POD. - Second, the GCC conding conventions prefer explicit conversion, - and explicit conversion operators are not available until C++11. */ - - static double_int from_uhwi (unsigned HOST_WIDE_INT cst); - static double_int from_shwi (HOST_WIDE_INT cst); - static double_int from_pair (HOST_WIDE_INT high, unsigned HOST_WIDE_INT low); - - /* Construct from a fuffer of length LEN. BUFFER will be read according - to byte endianess and word endianess. */ - static double_int from_buffer (const unsigned char *buffer, int len); - - /* No copy assignment operator or destructor to keep the type a POD. */ - - /* There are some special value-creation static member functions. */ - - static double_int mask (unsigned prec); - static double_int max_value (unsigned int prec, bool uns); - static double_int min_value (unsigned int prec, bool uns); - - /* The following functions are mutating operations. */ - - double_int &operator ++ (); // prefix - double_int &operator -- (); // prefix - double_int &operator *= (double_int); - double_int &operator += (double_int); - double_int &operator -= (double_int); - double_int &operator &= (double_int); - double_int &operator ^= (double_int); - double_int &operator |= (double_int); - - /* The following functions are non-mutating operations. */ - - /* Conversion functions. */ - - HOST_WIDE_INT to_shwi () const; - unsigned HOST_WIDE_INT to_uhwi () const; - - /* Conversion query functions. */ - - bool fits_uhwi () const; - bool fits_shwi () const; - bool fits_hwi (bool uns) const; - - /* Attribute query functions. */ - - int trailing_zeros () const; - int popcount () const; - - /* Arithmetic query operations. */ - - bool multiple_of (double_int, bool, double_int *) const; - - /* Arithmetic operation functions. */ - - /* The following operations perform arithmetics modulo 2^precision, so you - do not need to call .ext between them, even if you are representing - numbers with precision less than HOST_BITS_PER_DOUBLE_INT bits. */ - - double_int set_bit (unsigned) const; - double_int mul_with_sign (double_int, bool unsigned_p, bool *overflow) const; - double_int wide_mul_with_sign (double_int, bool unsigned_p, - double_int *higher, bool *overflow) const; - double_int add_with_sign (double_int, bool unsigned_p, bool *overflow) const; - double_int sub_with_overflow (double_int, bool *overflow) const; - double_int neg_with_overflow (bool *overflow) const; - - double_int operator * (double_int) const; - double_int operator + (double_int) const; - double_int operator - (double_int) const; - double_int operator - () const; - double_int operator ~ () const; - double_int operator & (double_int) const; - double_int operator | (double_int) const; - double_int operator ^ (double_int) const; - double_int and_not (double_int) const; - - double_int lshift (HOST_WIDE_INT count) const; - double_int lshift (HOST_WIDE_INT count, unsigned int prec, bool arith) const; - double_int rshift (HOST_WIDE_INT count) const; - double_int rshift (HOST_WIDE_INT count, unsigned int prec, bool arith) const; - double_int alshift (HOST_WIDE_INT count, unsigned int prec) const; - double_int arshift (HOST_WIDE_INT count, unsigned int prec) const; - double_int llshift (HOST_WIDE_INT count, unsigned int prec) const; - double_int lrshift (HOST_WIDE_INT count, unsigned int prec) const; - double_int lrotate (HOST_WIDE_INT count, unsigned int prec) const; - double_int rrotate (HOST_WIDE_INT count, unsigned int prec) const; - - /* You must ensure that double_int::ext is called on the operands - of the following operations, if the precision of the numbers - is less than HOST_BITS_PER_DOUBLE_INT bits. */ - - double_int div (double_int, bool, unsigned) const; - double_int sdiv (double_int, unsigned) const; - double_int udiv (double_int, unsigned) const; - double_int mod (double_int, bool, unsigned) const; - double_int smod (double_int, unsigned) const; - double_int umod (double_int, unsigned) const; - double_int divmod_with_overflow (double_int, bool, unsigned, - double_int *, bool *) const; - double_int divmod (double_int, bool, unsigned, double_int *) const; - double_int sdivmod (double_int, unsigned, double_int *) const; - double_int udivmod (double_int, unsigned, double_int *) const; - - /* Precision control functions. */ - - double_int ext (unsigned prec, bool uns) const; - double_int zext (unsigned prec) const; - double_int sext (unsigned prec) const; - - /* Comparative functions. */ - - bool is_zero () const; - bool is_one () const; - bool is_minus_one () const; - bool is_negative () const; - - int cmp (double_int b, bool uns) const; - int ucmp (double_int b) const; - int scmp (double_int b) const; - - bool ult (double_int b) const; - bool ule (double_int b) const; - bool ugt (double_int b) const; - bool slt (double_int b) const; - bool sle (double_int b) const; - bool sgt (double_int b) const; - - double_int max (double_int b, bool uns); - double_int smax (double_int b); - double_int umax (double_int b); - - double_int min (double_int b, bool uns); - double_int smin (double_int b); - double_int umin (double_int b); - - bool operator == (double_int cst2) const; - bool operator != (double_int cst2) const; - - /* Please migrate away from using these member variables publicly. */ - - unsigned HOST_WIDE_INT low; - HOST_WIDE_INT high; - -}; - -#define HOST_BITS_PER_DOUBLE_INT (2 * HOST_BITS_PER_WIDE_INT) - -/* Constructors and conversions. */ - -/* Constructs double_int from integer CST. The bits over the precision of - HOST_WIDE_INT are filled with the sign bit. */ - -inline double_int -double_int::from_shwi (HOST_WIDE_INT cst) -{ - double_int r; - r.low = (unsigned HOST_WIDE_INT) cst; - r.high = cst < 0 ? -1 : 0; - return r; -} - -/* Some useful constants. */ -/* FIXME(crowl): Maybe remove after converting callers? - The problem is that a named constant would not be as optimizable, - while the functional syntax is more verbose. */ - -#define double_int_minus_one (double_int::from_shwi (-1)) -#define double_int_zero (double_int::from_shwi (0)) -#define double_int_one (double_int::from_shwi (1)) -#define double_int_two (double_int::from_shwi (2)) -#define double_int_ten (double_int::from_shwi (10)) - -/* Constructs double_int from unsigned integer CST. The bits over the - precision of HOST_WIDE_INT are filled with zeros. */ - -inline double_int -double_int::from_uhwi (unsigned HOST_WIDE_INT cst) -{ - double_int r; - r.low = cst; - r.high = 0; - return r; -} - -inline double_int -double_int::from_pair (HOST_WIDE_INT high, unsigned HOST_WIDE_INT low) -{ - double_int r; - r.low = low; - r.high = high; - return r; -} - -inline double_int & -double_int::operator ++ () -{ - *this += double_int_one; - return *this; -} - -inline double_int & -double_int::operator -- () -{ - *this -= double_int_one; - return *this; -} - -inline double_int & -double_int::operator &= (double_int b) -{ - *this = *this & b; - return *this; -} - -inline double_int & -double_int::operator ^= (double_int b) -{ - *this = *this ^ b; - return *this; -} - -inline double_int & -double_int::operator |= (double_int b) -{ - *this = *this | b; - return *this; -} - -/* Returns value of CST as a signed number. CST must satisfy - double_int::fits_signed. */ - -inline HOST_WIDE_INT -double_int::to_shwi () const -{ - return (HOST_WIDE_INT) low; -} - -/* Returns value of CST as an unsigned number. CST must satisfy - double_int::fits_unsigned. */ - -inline unsigned HOST_WIDE_INT -double_int::to_uhwi () const -{ - return low; -} - -/* Returns true if CST fits in unsigned HOST_WIDE_INT. */ - -inline bool -double_int::fits_uhwi () const -{ - return high == 0; -} - -/* Logical operations. */ - -/* Returns ~A. */ - -inline double_int -double_int::operator ~ () const -{ - double_int result; - result.low = ~low; - result.high = ~high; - return result; -} - -/* Returns A | B. */ - -inline double_int -double_int::operator | (double_int b) const -{ - double_int result; - result.low = low | b.low; - result.high = high | b.high; - return result; -} - -/* Returns A & B. */ - -inline double_int -double_int::operator & (double_int b) const -{ - double_int result; - result.low = low & b.low; - result.high = high & b.high; - return result; -} - -/* Returns A & ~B. */ - -inline double_int -double_int::and_not (double_int b) const -{ - double_int result; - result.low = low & ~b.low; - result.high = high & ~b.high; - return result; -} - -/* Returns A ^ B. */ - -inline double_int -double_int::operator ^ (double_int b) const -{ - double_int result; - result.low = low ^ b.low; - result.high = high ^ b.high; - return result; -} - -void dump_double_int (FILE *, double_int, bool); - -#define ALL_ONES (~((unsigned HOST_WIDE_INT) 0)) - -/* The operands of the following comparison functions must be processed - with double_int_ext, if their precision is less than - HOST_BITS_PER_DOUBLE_INT bits. */ - -/* Returns true if CST is zero. */ - -inline bool -double_int::is_zero () const -{ - return low == 0 && high == 0; -} - -/* Returns true if CST is one. */ - -inline bool -double_int::is_one () const -{ - return low == 1 && high == 0; -} - -/* Returns true if CST is minus one. */ - -inline bool -double_int::is_minus_one () const -{ - return low == ALL_ONES && high == -1; -} - -/* Returns true if CST is negative. */ - -inline bool -double_int::is_negative () const -{ - return high < 0; -} - -/* Returns true if CST1 == CST2. */ - -inline bool -double_int::operator == (double_int cst2) const -{ - return low == cst2.low && high == cst2.high; -} - -/* Returns true if CST1 != CST2. */ - -inline bool -double_int::operator != (double_int cst2) const -{ - return low != cst2.low || high != cst2.high; -} - -/* Return number of set bits of CST. */ - -inline int -double_int::popcount () const -{ - return popcount_hwi (high) + popcount_hwi (low); -} - - -#ifndef GENERATOR_FILE -/* Conversion to and from GMP integer representations. */ - -void mpz_set_double_int (mpz_t, double_int, bool); -double_int mpz_get_double_int (const_tree, mpz_t, bool); -#endif - -namespace wi -{ - template <> - struct int_traits - { - static const enum precision_type precision_type = CONST_PRECISION; - static const bool host_dependent_precision = true; - static const unsigned int precision = HOST_BITS_PER_DOUBLE_INT; - static unsigned int get_precision (const double_int &); - static wi::storage_ref decompose (HOST_WIDE_INT *, unsigned int, - const double_int &); - }; -} - -inline unsigned int -wi::int_traits ::get_precision (const double_int &) -{ - return precision; -} - -inline wi::storage_ref -wi::int_traits ::decompose (HOST_WIDE_INT *scratch, unsigned int p, - const double_int &x) -{ - gcc_checking_assert (precision == p); - scratch[0] = x.low; - if ((x.high == 0 && scratch[0] >= 0) || (x.high == -1 && scratch[0] < 0)) - return wi::storage_ref (scratch, 1, precision); - scratch[1] = x.high; - return wi::storage_ref (scratch, 2, precision); -} - -#endif /* DOUBLE_INT_H */ diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/dumpfile.h b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/dumpfile.h deleted file mode 100644 index 40b6473..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/dumpfile.h +++ /dev/null @@ -1,255 +0,0 @@ -/* Definitions for the shared dumpfile. - Copyright (C) 2004-2015 Free Software Foundation, Inc. - -This file is part of GCC. - -GCC is free software; you can redistribute it and/or modify -it under the terms of the GNU General Public License as published by -the Free Software Foundation; either version 3, or (at your option) -any later version. - -GCC is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU General Public License for more details. - -You should have received a copy of the GNU General Public License -along with GCC; see the file COPYING3. If not see -. */ - - -#ifndef GCC_DUMPFILE_H -#define GCC_DUMPFILE_H 1 - -#include "line-map.h" - -/* Different tree dump places. When you add new tree dump places, - extend the DUMP_FILES array in dumpfile.c. */ -enum tree_dump_index -{ - TDI_none, /* No dump */ - TDI_cgraph, /* dump function call graph. */ - TDI_inheritance, /* dump type inheritance graph. */ - TDI_tu, /* dump the whole translation unit. */ - TDI_class, /* dump class hierarchy. */ - TDI_original, /* dump each function before optimizing it */ - TDI_generic, /* dump each function after genericizing it */ - TDI_nested, /* dump each function after unnesting it */ - TDI_tree_all, /* enable all the GENERIC/GIMPLE dumps. */ - TDI_rtl_all, /* enable all the RTL dumps. */ - TDI_ipa_all, /* enable all the IPA dumps. */ - - TDI_end -}; - -/* Bit masks to control dumping. Not all values are applicable to all - dumps. Add new ones at the end. When you define new values, extend - the DUMP_OPTIONS array in dumpfile.c. The TDF_* flags coexist with - MSG_* flags (for -fopt-info) and the bit values must be chosen to - allow that. */ -#define TDF_ADDRESS (1 << 0) /* dump node addresses */ -#define TDF_SLIM (1 << 1) /* don't go wild following links */ -#define TDF_RAW (1 << 2) /* don't unparse the function */ -#define TDF_DETAILS (1 << 3) /* show more detailed info about - each pass */ -#define TDF_STATS (1 << 4) /* dump various statistics about - each pass */ -#define TDF_BLOCKS (1 << 5) /* display basic block boundaries */ -#define TDF_VOPS (1 << 6) /* display virtual operands */ -#define TDF_LINENO (1 << 7) /* display statement line numbers */ -#define TDF_UID (1 << 8) /* display decl UIDs */ - -#define TDF_TREE (1 << 9) /* is a tree dump */ -#define TDF_RTL (1 << 10) /* is a RTL dump */ -#define TDF_IPA (1 << 11) /* is an IPA dump */ -#define TDF_STMTADDR (1 << 12) /* Address of stmt. */ - -#define TDF_GRAPH (1 << 13) /* a graph dump is being emitted */ -#define TDF_MEMSYMS (1 << 14) /* display memory symbols in expr. - Implies TDF_VOPS. */ - -#define TDF_DIAGNOSTIC (1 << 15) /* A dump to be put in a diagnostic - message. */ -#define TDF_VERBOSE (1 << 16) /* A dump that uses the full tree - dumper to print stmts. */ -#define TDF_RHS_ONLY (1 << 17) /* a flag to only print the RHS of - a gimple stmt. */ -#define TDF_ASMNAME (1 << 18) /* display asm names of decls */ -#define TDF_EH (1 << 19) /* display EH region number - holding this gimple statement. */ -#define TDF_NOUID (1 << 20) /* omit UIDs from dumps. */ -#define TDF_ALIAS (1 << 21) /* display alias information */ -#define TDF_ENUMERATE_LOCALS (1 << 22) /* Enumerate locals by uid. */ -#define TDF_CSELIB (1 << 23) /* Dump cselib details. */ -#define TDF_SCEV (1 << 24) /* Dump SCEV details. */ -#define TDF_COMMENT (1 << 25) /* Dump lines with prefix ";;" */ -#define MSG_OPTIMIZED_LOCATIONS (1 << 26) /* -fopt-info optimized sources */ -#define MSG_MISSED_OPTIMIZATION (1 << 27) /* missed opportunities */ -#define MSG_NOTE (1 << 28) /* general optimization info */ -#define MSG_ALL (MSG_OPTIMIZED_LOCATIONS | MSG_MISSED_OPTIMIZATION \ - | MSG_NOTE) - - -/* Flags to control high-level -fopt-info dumps. Usually these flags - define a group of passes. An optimization pass can be part of - multiple groups. */ -#define OPTGROUP_NONE (0) -#define OPTGROUP_IPA (1 << 1) /* IPA optimization passes */ -#define OPTGROUP_LOOP (1 << 2) /* Loop optimization passes */ -#define OPTGROUP_INLINE (1 << 3) /* Inlining passes */ -#define OPTGROUP_VEC (1 << 4) /* Vectorization passes */ -#define OPTGROUP_OTHER (1 << 5) /* All other passes */ -#define OPTGROUP_ALL (OPTGROUP_IPA | OPTGROUP_LOOP | OPTGROUP_INLINE \ - | OPTGROUP_VEC | OPTGROUP_OTHER) - -/* Define a tree dump switch. */ -struct dump_file_info -{ - const char *suffix; /* suffix to give output file. */ - const char *swtch; /* command line dump switch */ - const char *glob; /* command line glob */ - const char *pfilename; /* filename for the pass-specific stream */ - const char *alt_filename; /* filename for the -fopt-info stream */ - FILE *pstream; /* pass-specific dump stream */ - FILE *alt_stream; /* -fopt-info stream */ - int pflags; /* dump flags */ - int optgroup_flags; /* optgroup flags for -fopt-info */ - int alt_flags; /* flags for opt-info */ - int pstate; /* state of pass-specific stream */ - int alt_state; /* state of the -fopt-info stream */ - int num; /* dump file number */ - bool owns_strings; /* fields "suffix", "swtch", "glob" can be - const strings, or can be dynamically - allocated, needing free. */ -}; - -/* In dumpfile.c */ -extern FILE *dump_begin (int, int *); -extern void dump_end (int, FILE *); -extern int opt_info_switch_p (const char *); -extern const char *dump_flag_name (int); -extern void dump_printf (int, const char *, ...) ATTRIBUTE_PRINTF_2; -extern void dump_printf_loc (int, source_location, - const char *, ...) ATTRIBUTE_PRINTF_3; -extern void dump_basic_block (int, basic_block, int); -extern void dump_generic_expr_loc (int, source_location, int, tree); -extern void dump_generic_expr (int, int, tree); -extern void dump_gimple_stmt_loc (int, source_location, int, gimple, int); -extern void dump_gimple_stmt (int, int, gimple, int); -extern void print_combine_total_stats (void); -extern bool enable_rtl_dump_file (void); - -/* In tree-dump.c */ -extern void dump_node (const_tree, int, FILE *); - -/* In combine.c */ -extern void dump_combine_total_stats (FILE *); -/* In cfghooks.c */ -extern void dump_bb (FILE *, basic_block, int, int); - -/* Global variables used to communicate with passes. */ -extern FILE *dump_file; -extern FILE *alt_dump_file; -extern int dump_flags; -extern const char *dump_file_name; - -/* Return true if any of the dumps is enabled, false otherwise. */ -static inline bool -dump_enabled_p (void) -{ - return (dump_file || alt_dump_file); -} - -namespace gcc { - -class dump_manager -{ -public: - - dump_manager (); - ~dump_manager (); - - /* Register a dumpfile. - - TAKE_OWNERSHIP determines whether callee takes ownership of strings - SUFFIX, SWTCH, and GLOB. */ - unsigned int - dump_register (const char *suffix, const char *swtch, const char *glob, - int flags, int optgroup_flags, - bool take_ownership); - - /* Return the dump_file_info for the given phase. */ - struct dump_file_info * - get_dump_file_info (int phase) const; - - struct dump_file_info * - get_dump_file_info_by_switch (const char *swtch) const; - - /* Return the name of the dump file for the given phase. - If the dump is not enabled, returns NULL. */ - char * - get_dump_file_name (int phase) const; - - char * - get_dump_file_name (struct dump_file_info *dfi) const; - - int - dump_switch_p (const char *arg); - - /* Start a dump for PHASE. Store user-supplied dump flags in - *FLAG_PTR. Return the number of streams opened. Set globals - DUMP_FILE, and ALT_DUMP_FILE to point to the opened streams, and - set dump_flags appropriately for both pass dump stream and - -fopt-info stream. */ - int - dump_start (int phase, int *flag_ptr); - - /* Finish a tree dump for PHASE and close associated dump streams. Also - reset the globals DUMP_FILE, ALT_DUMP_FILE, and DUMP_FLAGS. */ - void - dump_finish (int phase); - - FILE * - dump_begin (int phase, int *flag_ptr); - - /* Returns nonzero if tree dump PHASE has been initialized. */ - int - dump_initialized_p (int phase) const; - - /* Returns the switch name of PHASE. */ - const char * - dump_flag_name (int phase) const; - -private: - - int - dump_phase_enabled_p (int phase) const; - - int - dump_switch_p_1 (const char *arg, struct dump_file_info *dfi, bool doglob); - - int - dump_enable_all (int flags, const char *filename); - - int - opt_info_enable_passes (int optgroup_flags, int flags, const char *filename); - -private: - - /* Dynamically registered dump files and switches. */ - int m_next_dump; - struct dump_file_info *m_extra_dump_files; - size_t m_extra_dump_files_in_use; - size_t m_extra_dump_files_alloced; - - /* Grant access to dump_enable_all. */ - friend bool ::enable_rtl_dump_file (void); - - /* Grant access to opt_info_enable_passes. */ - friend int ::opt_info_switch_p (const char *arg); - -}; // class dump_manager - -} // namespace gcc - -#endif /* GCC_DUMPFILE_H */ diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/dwarf2asm.h b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/dwarf2asm.h deleted file mode 100644 index d4a5706..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/dwarf2asm.h +++ /dev/null @@ -1,92 +0,0 @@ -/* Dwarf2 assembler output helper routines. - Copyright (C) 2001-2015 Free Software Foundation, Inc. - -This file is part of GCC. - -GCC is free software; you can redistribute it and/or modify it under -the terms of the GNU General Public License as published by the Free -Software Foundation; either version 3, or (at your option) any later -version. - -GCC is distributed in the hope that it will be useful, but WITHOUT ANY -WARRANTY; without even the implied warranty of MERCHANTABILITY or -FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -for more details. - -You should have received a copy of the GNU General Public License -along with GCC; see the file COPYING3. If not see -. */ - -#ifndef GCC_DWARF2ASM_H -#define GCC_DWARF2ASM_H - -extern void dw2_assemble_integer (int, rtx); - -extern void dw2_asm_output_data_raw (int, unsigned HOST_WIDE_INT); - -extern void dw2_asm_output_data (int, unsigned HOST_WIDE_INT, - const char *, ...) - ATTRIBUTE_NULL_PRINTF_3; - -extern void dw2_asm_output_delta (int, const char *, const char *, - const char *, ...) - ATTRIBUTE_NULL_PRINTF_4; - -extern void dw2_asm_output_vms_delta (int, const char *, const char *, - const char *, ...) - ATTRIBUTE_NULL_PRINTF_4; - -extern void dw2_asm_output_offset (int, const char *, section *, - const char *, ...) - ATTRIBUTE_NULL_PRINTF_4; - -extern void dw2_asm_output_addr (int, const char *, const char *, ...) - ATTRIBUTE_NULL_PRINTF_3; - -extern void dw2_asm_output_addr_rtx (int, rtx, const char *, ...) - ATTRIBUTE_NULL_PRINTF_3; - -extern void dw2_asm_output_encoded_addr_rtx (int, rtx, bool, - const char *, ...) - ATTRIBUTE_NULL_PRINTF_4; - -extern void dw2_asm_output_nstring (const char *, size_t, - const char *, ...) - ATTRIBUTE_NULL_PRINTF_3; - -extern void dw2_asm_output_data_uleb128_raw (unsigned HOST_WIDE_INT); - -extern void dw2_asm_output_data_uleb128 (unsigned HOST_WIDE_INT, - const char *, ...) - ATTRIBUTE_NULL_PRINTF_2; - -extern void dw2_asm_output_data_sleb128_raw (HOST_WIDE_INT); - -extern void dw2_asm_output_data_sleb128 (HOST_WIDE_INT, - const char *, ...) - ATTRIBUTE_NULL_PRINTF_2; - -extern void dw2_asm_output_delta_uleb128 (const char *, const char *, - const char *, ...) - ATTRIBUTE_NULL_PRINTF_3; - -extern int size_of_uleb128 (unsigned HOST_WIDE_INT); -extern int size_of_sleb128 (HOST_WIDE_INT); -extern int size_of_encoded_value (int); -extern const char *eh_data_format_name (int); - -extern rtx dw2_force_const_mem (rtx, bool); -extern void dw2_output_indirect_constants (void); - -/* These are currently unused. */ - -#if 0 -extern void dw2_asm_output_pcrel (int, const char *, const char *, ...) - ATTRIBUTE_NULL_PRINTF_3; - -extern void dw2_asm_output_delta_sleb128 (const char *, const char *, - const char *, ...) - ATTRIBUTE_NULL_PRINTF_3; -#endif - -#endif /* GCC_DWARF2ASM_H */ diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/dwarf2out.h b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/dwarf2out.h deleted file mode 100644 index a4d7df8..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/dwarf2out.h +++ /dev/null @@ -1,295 +0,0 @@ -/* dwarf2out.h - Various declarations for functions found in dwarf2out.c - Copyright (C) 1998-2015 Free Software Foundation, Inc. - -This file is part of GCC. - -GCC is free software; you can redistribute it and/or modify it under -the terms of the GNU General Public License as published by the Free -Software Foundation; either version 3, or (at your option) any later -version. - -GCC is distributed in the hope that it will be useful, but WITHOUT ANY -WARRANTY; without even the implied warranty of MERCHANTABILITY or -FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -for more details. - -You should have received a copy of the GNU General Public License -along with GCC; see the file COPYING3. If not see -. */ - -#ifndef GCC_DWARF2OUT_H -#define GCC_DWARF2OUT_H 1 - -#include "dwarf2.h" /* ??? Remove this once only used by dwarf2foo.c. */ -#include "wide-int.h" - -typedef struct die_struct *dw_die_ref; -typedef const struct die_struct *const_dw_die_ref; - -typedef struct dw_val_node *dw_val_ref; -typedef struct dw_cfi_node *dw_cfi_ref; -typedef struct dw_loc_descr_node *dw_loc_descr_ref; -typedef struct dw_loc_list_struct *dw_loc_list_ref; -typedef wide_int *wide_int_ptr; - - -/* Call frames are described using a sequence of Call Frame - Information instructions. The register number, offset - and address fields are provided as possible operands; - their use is selected by the opcode field. */ - -enum dw_cfi_oprnd_type { - dw_cfi_oprnd_unused, - dw_cfi_oprnd_reg_num, - dw_cfi_oprnd_offset, - dw_cfi_oprnd_addr, - dw_cfi_oprnd_loc -}; - -typedef union GTY(()) { - unsigned int GTY ((tag ("dw_cfi_oprnd_reg_num"))) dw_cfi_reg_num; - HOST_WIDE_INT GTY ((tag ("dw_cfi_oprnd_offset"))) dw_cfi_offset; - const char * GTY ((tag ("dw_cfi_oprnd_addr"))) dw_cfi_addr; - struct dw_loc_descr_node * GTY ((tag ("dw_cfi_oprnd_loc"))) dw_cfi_loc; -} dw_cfi_oprnd; - -struct GTY(()) dw_cfi_node { - enum dwarf_call_frame_info dw_cfi_opc; - dw_cfi_oprnd GTY ((desc ("dw_cfi_oprnd1_desc (%1.dw_cfi_opc)"))) - dw_cfi_oprnd1; - dw_cfi_oprnd GTY ((desc ("dw_cfi_oprnd2_desc (%1.dw_cfi_opc)"))) - dw_cfi_oprnd2; -}; - - -typedef vec *cfi_vec; - -typedef struct dw_fde_node *dw_fde_ref; - -/* All call frame descriptions (FDE's) in the GCC generated DWARF - refer to a single Common Information Entry (CIE), defined at - the beginning of the .debug_frame section. This use of a single - CIE obviates the need to keep track of multiple CIE's - in the DWARF generation routines below. */ - -struct GTY(()) dw_fde_node { - tree decl; - const char *dw_fde_begin; - const char *dw_fde_current_label; - const char *dw_fde_end; - const char *dw_fde_vms_end_prologue; - const char *dw_fde_vms_begin_epilogue; - const char *dw_fde_second_begin; - const char *dw_fde_second_end; - cfi_vec dw_fde_cfi; - int dw_fde_switch_cfi_index; /* Last CFI before switching sections. */ - HOST_WIDE_INT stack_realignment; - - unsigned funcdef_number; - unsigned fde_index; - - /* Dynamic realign argument pointer register. */ - unsigned int drap_reg; - /* Virtual dynamic realign argument pointer register. */ - unsigned int vdrap_reg; - /* These 3 flags are copied from rtl_data in function.h. */ - unsigned all_throwers_are_sibcalls : 1; - unsigned uses_eh_lsda : 1; - unsigned nothrow : 1; - /* Whether we did stack realign in this call frame. */ - unsigned stack_realign : 1; - /* Whether dynamic realign argument pointer register has been saved. */ - unsigned drap_reg_saved: 1; - /* True iff dw_fde_begin label is in text_section or cold_text_section. */ - unsigned in_std_section : 1; - /* True iff dw_fde_second_begin label is in text_section or - cold_text_section. */ - unsigned second_in_std_section : 1; -}; - - -/* This is how we define the location of the CFA. We use to handle it - as REG + OFFSET all the time, but now it can be more complex. - It can now be either REG + CFA_OFFSET or *(REG + BASE_OFFSET) + CFA_OFFSET. - Instead of passing around REG and OFFSET, we pass a copy - of this structure. */ -struct GTY(()) dw_cfa_location { - HOST_WIDE_INT offset; - HOST_WIDE_INT base_offset; - /* REG is in DWARF_FRAME_REGNUM space, *not* normal REGNO space. */ - unsigned int reg; - BOOL_BITFIELD indirect : 1; /* 1 if CFA is accessed via a dereference. */ - BOOL_BITFIELD in_use : 1; /* 1 if a saved cfa is stored here. */ -}; - - -/* Each DIE may have a series of attribute/value pairs. Values - can take on several forms. The forms that are used in this - implementation are listed below. */ - -enum dw_val_class -{ - dw_val_class_none, - dw_val_class_addr, - dw_val_class_offset, - dw_val_class_loc, - dw_val_class_loc_list, - dw_val_class_range_list, - dw_val_class_const, - dw_val_class_unsigned_const, - dw_val_class_const_double, - dw_val_class_wide_int, - dw_val_class_vec, - dw_val_class_flag, - dw_val_class_die_ref, - dw_val_class_fde_ref, - dw_val_class_lbl_id, - dw_val_class_lineptr, - dw_val_class_str, - dw_val_class_macptr, - dw_val_class_file, - dw_val_class_data8, - dw_val_class_decl_ref, - dw_val_class_vms_delta, - dw_val_class_high_pc -}; - -/* Describe a floating point constant value, or a vector constant value. */ - -struct GTY(()) dw_vec_const { - unsigned char * GTY((atomic)) array; - unsigned length; - unsigned elt_size; -}; - -struct addr_table_entry_struct; - -/* The dw_val_node describes an attribute's value, as it is - represented internally. */ - -struct GTY(()) dw_val_node { - enum dw_val_class val_class; - struct addr_table_entry_struct * GTY(()) val_entry; - union dw_val_struct_union - { - rtx GTY ((tag ("dw_val_class_addr"))) val_addr; - unsigned HOST_WIDE_INT GTY ((tag ("dw_val_class_offset"))) val_offset; - dw_loc_list_ref GTY ((tag ("dw_val_class_loc_list"))) val_loc_list; - dw_loc_descr_ref GTY ((tag ("dw_val_class_loc"))) val_loc; - HOST_WIDE_INT GTY ((default)) val_int; - unsigned HOST_WIDE_INT GTY ((tag ("dw_val_class_unsigned_const"))) val_unsigned; - double_int GTY ((tag ("dw_val_class_const_double"))) val_double; - wide_int_ptr GTY ((tag ("dw_val_class_wide_int"))) val_wide; - dw_vec_const GTY ((tag ("dw_val_class_vec"))) val_vec; - struct dw_val_die_union - { - dw_die_ref die; - int external; - } GTY ((tag ("dw_val_class_die_ref"))) val_die_ref; - unsigned GTY ((tag ("dw_val_class_fde_ref"))) val_fde_index; - struct indirect_string_node * GTY ((tag ("dw_val_class_str"))) val_str; - char * GTY ((tag ("dw_val_class_lbl_id"))) val_lbl_id; - unsigned char GTY ((tag ("dw_val_class_flag"))) val_flag; - struct dwarf_file_data * GTY ((tag ("dw_val_class_file"))) val_file; - unsigned char GTY ((tag ("dw_val_class_data8"))) val_data8[8]; - tree GTY ((tag ("dw_val_class_decl_ref"))) val_decl_ref; - struct dw_val_vms_delta_union - { - char * lbl1; - char * lbl2; - } GTY ((tag ("dw_val_class_vms_delta"))) val_vms_delta; - } - GTY ((desc ("%1.val_class"))) v; -}; - -/* Locations in memory are described using a sequence of stack machine - operations. */ - -struct GTY((chain_next ("%h.dw_loc_next"))) dw_loc_descr_node { - dw_loc_descr_ref dw_loc_next; - ENUM_BITFIELD (dwarf_location_atom) dw_loc_opc : 8; - /* Used to distinguish DW_OP_addr with a direct symbol relocation - from DW_OP_addr with a dtp-relative symbol relocation. */ - unsigned int dtprel : 1; - int dw_loc_addr; - dw_val_node dw_loc_oprnd1; - dw_val_node dw_loc_oprnd2; -}; - - -/* Interface from dwarf2out.c to dwarf2cfi.c. */ -extern struct dw_loc_descr_node *build_cfa_loc - (dw_cfa_location *, HOST_WIDE_INT); -extern struct dw_loc_descr_node *build_cfa_aligned_loc - (dw_cfa_location *, HOST_WIDE_INT offset, HOST_WIDE_INT alignment); -extern struct dw_loc_descr_node *mem_loc_descriptor - (rtx, machine_mode mode, machine_mode mem_mode, - enum var_init_status); -extern bool loc_descr_equal_p (dw_loc_descr_ref, dw_loc_descr_ref); -extern dw_fde_ref dwarf2out_alloc_current_fde (void); - -extern unsigned long size_of_locs (dw_loc_descr_ref); -extern void output_loc_sequence (dw_loc_descr_ref, int); -extern void output_loc_sequence_raw (dw_loc_descr_ref); - -/* Interface from dwarf2cfi.c to dwarf2out.c. */ -extern void lookup_cfa_1 (dw_cfi_ref cfi, dw_cfa_location *loc, - dw_cfa_location *remember); -extern bool cfa_equal_p (const dw_cfa_location *, const dw_cfa_location *); - -extern void output_cfi (dw_cfi_ref, dw_fde_ref, int); - -extern GTY(()) cfi_vec cie_cfi_vec; - -/* Interface from dwarf2*.c to the rest of the compiler. */ -extern enum dw_cfi_oprnd_type dw_cfi_oprnd1_desc - (enum dwarf_call_frame_info cfi); -extern enum dw_cfi_oprnd_type dw_cfi_oprnd2_desc - (enum dwarf_call_frame_info cfi); - -extern void output_cfi_directive (FILE *f, struct dw_cfi_node *cfi); - -extern void dwarf2out_emit_cfi (dw_cfi_ref cfi); - -extern void debug_dwarf (void); -struct die_struct; -extern void debug_dwarf_die (struct die_struct *); -extern void debug_dwarf_loc_descr (dw_loc_descr_ref); -extern void debug (die_struct &ref); -extern void debug (die_struct *ptr); -extern void dwarf2out_set_demangle_name_func (const char *(*) (const char *)); -#ifdef VMS_DEBUGGING_INFO -extern void dwarf2out_vms_debug_main_pointer (void); -#endif - -enum array_descr_ordering -{ - array_descr_ordering_default, - array_descr_ordering_row_major, - array_descr_ordering_column_major -}; - -struct array_descr_info -{ - int ndimensions; - enum array_descr_ordering ordering; - tree element_type; - tree base_decl; - tree data_location; - tree allocated; - tree associated; - struct array_descr_dimen - { - /* GCC uses sizetype for array indices, so lower_bound and upper_bound - will likely be "sizetype" values. However, bounds may have another - type in the original source code. */ - tree bounds_type; - tree lower_bound; - tree upper_bound; - tree stride; - } dimen[10]; -}; - -void dwarf2out_c_finalize (void); - -#endif /* GCC_DWARF2OUT_H */ diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/emit-rtl.h b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/emit-rtl.h deleted file mode 100644 index 3abe58e..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/emit-rtl.h +++ /dev/null @@ -1,192 +0,0 @@ -/* Exported functions from emit-rtl.c - Copyright (C) 2004-2015 Free Software Foundation, Inc. - -This file is part of GCC. - -GCC is free software; you can redistribute it and/or modify it under -the terms of the GNU General Public License as published by the Free -Software Foundation; either version 3, or (at your option) any later -version. - -GCC is distributed in the hope that it will be useful, but WITHOUT ANY -WARRANTY; without even the implied warranty of MERCHANTABILITY or -FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -for more details. - -You should have received a copy of the GNU General Public License -along with GCC; see the file COPYING3. If not see -. */ - -#ifndef GCC_EMIT_RTL_H -#define GCC_EMIT_RTL_H - -/* Return whether two MEM_ATTRs are equal. */ -bool mem_attrs_eq_p (const struct mem_attrs *, const struct mem_attrs *); - -/* Set the alias set of MEM to SET. */ -extern void set_mem_alias_set (rtx, alias_set_type); - -/* Set the alignment of MEM to ALIGN bits. */ -extern void set_mem_align (rtx, unsigned int); - -/* Set the address space of MEM to ADDRSPACE. */ -extern void set_mem_addr_space (rtx, addr_space_t); - -/* Set the expr for MEM to EXPR. */ -extern void set_mem_expr (rtx, tree); - -/* Set the offset for MEM to OFFSET. */ -extern void set_mem_offset (rtx, HOST_WIDE_INT); - -/* Clear the offset recorded for MEM. */ -extern void clear_mem_offset (rtx); - -/* Set the size for MEM to SIZE. */ -extern void set_mem_size (rtx, HOST_WIDE_INT); - -/* Clear the size recorded for MEM. */ -extern void clear_mem_size (rtx); - -/* Set the attributes for MEM appropriate for a spill slot. */ -extern void set_mem_attrs_for_spill (rtx); -extern tree get_spill_slot_decl (bool); - -/* Return a memory reference like MEMREF, but with its address changed to - ADDR. The caller is asserting that the actual piece of memory pointed - to is the same, just the form of the address is being changed, such as - by putting something into a register. */ -extern rtx replace_equiv_address (rtx, rtx, bool = false); - -/* Likewise, but the reference is not required to be valid. */ -extern rtx replace_equiv_address_nv (rtx, rtx, bool = false); - -extern rtx gen_blockage (void); -extern rtvec gen_rtvec (int, ...); -extern rtx copy_insn_1 (rtx); -extern rtx copy_insn (rtx); -extern rtx_insn *copy_delay_slot_insn (rtx_insn *); -extern rtx gen_int_mode (HOST_WIDE_INT, machine_mode); -extern rtx_insn *emit_copy_of_insn_after (rtx_insn *, rtx_insn *); -extern void set_reg_attrs_from_value (rtx, rtx); -extern void set_reg_attrs_for_parm (rtx, rtx); -extern void set_reg_attrs_for_decl_rtl (tree t, rtx x); -extern void adjust_reg_mode (rtx, machine_mode); -extern int mem_expr_equal_p (const_tree, const_tree); - -extern bool need_atomic_barrier_p (enum memmodel, bool); - -/* Return the first insn of the current sequence or current function. */ - -static inline rtx_insn * -get_insns (void) -{ - return crtl->emit.x_first_insn; -} - -/* Specify a new insn as the first in the chain. */ - -static inline void -set_first_insn (rtx_insn *insn) -{ - gcc_checking_assert (!insn || !PREV_INSN (insn)); - crtl->emit.x_first_insn = insn; -} - -/* Return the last insn emitted in current sequence or current function. */ - -static inline rtx_insn * -get_last_insn (void) -{ - return crtl->emit.x_last_insn; -} - -/* Specify a new insn as the last in the chain. */ - -static inline void -set_last_insn (rtx_insn *insn) -{ - gcc_checking_assert (!insn || !NEXT_INSN (insn)); - crtl->emit.x_last_insn = insn; -} - -/* Return a number larger than any instruction's uid in this function. */ - -static inline int -get_max_uid (void) -{ - return crtl->emit.x_cur_insn_uid; -} - -extern void set_decl_incoming_rtl (tree, rtx, bool); - -/* Return a memory reference like MEMREF, but with its mode changed - to MODE and its address changed to ADDR. - (VOIDmode means don't change the mode. - NULL for ADDR means don't change the address.) */ -extern rtx change_address (rtx, machine_mode, rtx); - -/* Return a memory reference like MEMREF, but with its mode changed - to MODE and its address offset by OFFSET bytes. */ -#define adjust_address(MEMREF, MODE, OFFSET) \ - adjust_address_1 (MEMREF, MODE, OFFSET, 1, 1, 0, 0) - -/* Likewise, but the reference is not required to be valid. */ -#define adjust_address_nv(MEMREF, MODE, OFFSET) \ - adjust_address_1 (MEMREF, MODE, OFFSET, 0, 1, 0, 0) - -/* Return a memory reference like MEMREF, but with its mode changed - to MODE and its address offset by OFFSET bytes. Assume that it's - for a bitfield and conservatively drop the underlying object if we - cannot be sure to stay within its bounds. */ -#define adjust_bitfield_address(MEMREF, MODE, OFFSET) \ - adjust_address_1 (MEMREF, MODE, OFFSET, 1, 1, 1, 0) - -/* As for adjust_bitfield_address, but specify that the width of - BLKmode accesses is SIZE bytes. */ -#define adjust_bitfield_address_size(MEMREF, MODE, OFFSET, SIZE) \ - adjust_address_1 (MEMREF, MODE, OFFSET, 1, 1, 1, SIZE) - -/* Likewise, but the reference is not required to be valid. */ -#define adjust_bitfield_address_nv(MEMREF, MODE, OFFSET) \ - adjust_address_1 (MEMREF, MODE, OFFSET, 0, 1, 1, 0) - -/* Return a memory reference like MEMREF, but with its mode changed - to MODE and its address changed to ADDR, which is assumed to be - increased by OFFSET bytes from MEMREF. */ -#define adjust_automodify_address(MEMREF, MODE, ADDR, OFFSET) \ - adjust_automodify_address_1 (MEMREF, MODE, ADDR, OFFSET, 1) - -/* Likewise, but the reference is not required to be valid. */ -#define adjust_automodify_address_nv(MEMREF, MODE, ADDR, OFFSET) \ - adjust_automodify_address_1 (MEMREF, MODE, ADDR, OFFSET, 0) - -extern rtx adjust_address_1 (rtx, machine_mode, HOST_WIDE_INT, int, int, - int, HOST_WIDE_INT); -extern rtx adjust_automodify_address_1 (rtx, machine_mode, rtx, - HOST_WIDE_INT, int); - -/* Return a memory reference like MEMREF, but whose address is changed by - adding OFFSET, an RTX, to it. POW2 is the highest power of two factor - known to be in OFFSET (possibly 1). */ -extern rtx offset_address (rtx, rtx, unsigned HOST_WIDE_INT); - -/* Given REF, a MEM, and T, either the type of X or the expression - corresponding to REF, set the memory attributes. OBJECTP is nonzero - if we are making a new object of this type. */ -extern void set_mem_attributes (rtx, tree, int); - -/* Similar, except that BITPOS has not yet been applied to REF, so if - we alter MEM_OFFSET according to T then we should subtract BITPOS - expecting that it'll be added back in later. */ -extern void set_mem_attributes_minus_bitpos (rtx, tree, int, HOST_WIDE_INT); - -/* Return OFFSET if XEXP (MEM, 0) - OFFSET is known to be ALIGN - bits aligned for 0 <= OFFSET < ALIGN / BITS_PER_UNIT, or - -1 if not known. */ -extern int get_mem_align_offset (rtx, unsigned int); - -/* Return a memory reference like MEMREF, but with its mode widened to - MODE and adjusted by OFFSET. */ -extern rtx widen_memory_access (rtx, machine_mode, HOST_WIDE_INT); - -#endif /* GCC_EMIT_RTL_H */ diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/errors.h b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/errors.h deleted file mode 100644 index edff6a9..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/errors.h +++ /dev/null @@ -1,40 +0,0 @@ -/* Basic error reporting routines. - Copyright (C) 1999-2015 Free Software Foundation, Inc. - -This file is part of GCC. - -GCC is free software; you can redistribute it and/or modify it under -the terms of the GNU General Public License as published by the Free -Software Foundation; either version 3, or (at your option) any later -version. - -GCC is distributed in the hope that it will be useful, but WITHOUT ANY -WARRANTY; without even the implied warranty of MERCHANTABILITY or -FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -for more details. - -You should have received a copy of the GNU General Public License -along with GCC; see the file COPYING3. If not see -. */ - -/* warning, error, and fatal. These definitions are suitable for use - in the generator programs; eventually we would like to use them in - cc1 too, but that's a longer term project. - - N.B. We cannot presently use ATTRIBUTE_PRINTF with these functions, - because they can be extended with additional format specifiers which - GCC does not know about. */ - -#ifndef GCC_ERRORS_H -#define GCC_ERRORS_H - -extern void warning (const char *, ...) ATTRIBUTE_PRINTF_1 ATTRIBUTE_COLD; -extern void error (const char *, ...) ATTRIBUTE_PRINTF_1 ATTRIBUTE_COLD; -extern void fatal (const char *, ...) ATTRIBUTE_NORETURN ATTRIBUTE_PRINTF_1 ATTRIBUTE_COLD; -extern void internal_error (const char *, ...) ATTRIBUTE_NORETURN ATTRIBUTE_PRINTF_1 ATTRIBUTE_COLD; -extern const char *trim_filename (const char *); - -extern int have_error; -extern const char *progname; - -#endif /* ! GCC_ERRORS_H */ diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/et-forest.h b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/et-forest.h deleted file mode 100644 index b507c64..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/et-forest.h +++ /dev/null @@ -1,85 +0,0 @@ -/* Et-forest data structure implementation. - Copyright (C) 2002-2015 Free Software Foundation, Inc. - - This program is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - This program is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program; see the file COPYING3. If not see - . */ - -/* This package implements ET forest data structure. Each tree in - the structure maintains a tree structure and offers logarithmic time - for tree operations (insertion and removal of nodes and edges) and - poly-logarithmic time for nearest common ancestor. - - ET tree stores its structure as a sequence of symbols obtained - by dfs(root) - - dfs (node) - { - s = node; - for each child c of node do - s = concat (s, c, node); - return s; - } - - For example for tree - - 1 - / | \ - 2 3 4 - / | - 4 5 - - the sequence is 1 2 4 2 5 3 1 3 1 4 1. - - The sequence is stored in a slightly modified splay tree. - In order to support various types of node values, a hashtable - is used to convert node values to the internal representation. */ - -#ifndef _ET_TREE_H -#define _ET_TREE_H - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -/* The node representing the node in an et tree. */ -struct et_node -{ - void *data; /* The data represented by the node. */ - - int dfs_num_in, dfs_num_out; /* Number of the node in the dfs ordering. */ - - struct et_node *father; /* Father of the node. */ - struct et_node *son; /* The first of the sons of the node. */ - struct et_node *left; - struct et_node *right; /* The brothers of the node. */ - - struct et_occ *rightmost_occ; /* The rightmost occurrence. */ - struct et_occ *parent_occ; /* The occurrence of the parent node. */ -}; - -struct et_node *et_new_tree (void *data); -void et_free_tree (struct et_node *); -void et_free_tree_force (struct et_node *); -void et_free_pools (void); -void et_set_father (struct et_node *, struct et_node *); -void et_split (struct et_node *); -struct et_node *et_nca (struct et_node *, struct et_node *); -bool et_below (struct et_node *, struct et_node *); -struct et_node *et_root (struct et_node *); - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - -#endif /* _ET_TREE_H */ diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/except.h b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/except.h deleted file mode 100644 index eb81203..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/except.h +++ /dev/null @@ -1,336 +0,0 @@ -/* Exception Handling interface routines. - Copyright (C) 1996-2015 Free Software Foundation, Inc. - Contributed by Mike Stump . - -This file is part of GCC. - -GCC is free software; you can redistribute it and/or modify it under -the terms of the GNU General Public License as published by the Free -Software Foundation; either version 3, or (at your option) any later -version. - -GCC is distributed in the hope that it will be useful, but WITHOUT ANY -WARRANTY; without even the implied warranty of MERCHANTABILITY or -FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -for more details. - -You should have received a copy of the GNU General Public License -along with GCC; see the file COPYING3. If not see -. */ - -/* No include guards here, but define an include file marker anyway, so - that the compiler can keep track of where this file is included. This - is e.g. used to avoid including this file in front-end specific files. */ -#ifndef GCC_EXCEPT_H -#define GCC_EXCEPT_H - -#include "hash-map.h" -#include "hashtab.h" - -struct function; -struct eh_region_d; - -/* The type of an exception region. */ -enum eh_region_type -{ - /* CLEANUP regions implement e.g. destructors run when exiting a block. - They can be generated from both GIMPLE_TRY_FINALLY and GIMPLE_TRY_CATCH - nodes. It is expected by the runtime that cleanup regions will *not* - resume normal program flow, but will continue propagation of the - exception. */ - ERT_CLEANUP, - - /* TRY regions implement catching an exception. The list of types associated - with the attached catch handlers is examined in order by the runtime and - control is transferred to the appropriate handler. Note that a NULL type - list is a catch-all handler, and that it will catch *all* exceptions - including those originating from a different language. */ - ERT_TRY, - - /* ALLOWED_EXCEPTIONS regions implement exception filtering, e.g. the - throw(type-list) specification that can be added to C++ functions. - The runtime examines the thrown exception vs the type list, and if - the exception does not match, transfers control to the handler. The - normal handler for C++ calls __cxa_call_unexpected. */ - ERT_ALLOWED_EXCEPTIONS, - - /* MUST_NOT_THROW regions prevent all exceptions from propagating. This - region type is used in C++ to surround destructors being run inside a - CLEANUP region. This differs from an ALLOWED_EXCEPTIONS region with - an empty type list in that the runtime is prepared to terminate the - program directly. We only generate code for MUST_NOT_THROW regions - along control paths that are already handling an exception within the - current function. */ - ERT_MUST_NOT_THROW -}; - - -/* A landing pad for a given exception region. Any transfer of control - from the EH runtime to the function happens at a landing pad. */ - -struct GTY(()) eh_landing_pad_d -{ - /* The linked list of all landing pads associated with the region. */ - struct eh_landing_pad_d *next_lp; - - /* The region with which this landing pad is associated. */ - struct eh_region_d *region; - - /* At the gimple level, the location to which control will be transferred - for this landing pad. There can be both EH and normal edges into the - block containing the post-landing-pad label. */ - tree post_landing_pad; - - /* At the rtl level, the location to which the runtime will transfer - control. This differs from the post-landing-pad in that the target's - EXCEPTION_RECEIVER pattern will be expanded here, as well as other - bookkeeping specific to exceptions. There must not be normal edges - into the block containing the landing-pad label. */ - rtx_code_label *landing_pad; - - /* The index of this landing pad within fun->eh->lp_array. */ - int index; -}; - -/* A catch handler associated with an ERT_TRY region. */ - -struct GTY(()) eh_catch_d -{ - /* The double-linked list of all catch handlers for the region. */ - struct eh_catch_d *next_catch; - struct eh_catch_d *prev_catch; - - /* A TREE_LIST of runtime type objects that this catch handler - will catch, or NULL if all exceptions are caught. */ - tree type_list; - - /* A TREE_LIST of INTEGER_CSTs that correspond to the type_list entries, - having been mapped by assign_filter_values. These integers are to be - compared against the __builtin_eh_filter value. */ - tree filter_list; - - /* The code that should be executed if this catch handler matches the - thrown exception. This label is only maintained until - pass_lower_eh_dispatch, at which point it is cleared. */ - tree label; -}; - -/* Describes one exception region. */ - -struct GTY(()) eh_region_d -{ - /* The immediately surrounding region. */ - struct eh_region_d *outer; - - /* The list of immediately contained regions. */ - struct eh_region_d *inner; - struct eh_region_d *next_peer; - - /* The index of this region within fun->eh->region_array. */ - int index; - - /* Each region does exactly one thing. */ - enum eh_region_type type; - - /* Holds the action to perform based on the preceding type. */ - union eh_region_u { - struct eh_region_u_try { - /* The double-linked list of all catch handlers for this region. */ - struct eh_catch_d *first_catch; - struct eh_catch_d *last_catch; - } GTY ((tag ("ERT_TRY"))) eh_try; - - struct eh_region_u_allowed { - /* A TREE_LIST of runtime type objects allowed to pass. */ - tree type_list; - /* The code that should be executed if the thrown exception does - not match the type list. This label is only maintained until - pass_lower_eh_dispatch, at which point it is cleared. */ - tree label; - /* The integer that will be passed by the runtime to signal that - we should execute the code at LABEL. This integer is assigned - by assign_filter_values and is to be compared against the - __builtin_eh_filter value. */ - int filter; - } GTY ((tag ("ERT_ALLOWED_EXCEPTIONS"))) allowed; - - struct eh_region_u_must_not_throw { - /* A function decl to be invoked if this region is actually reachable - from within the function, rather than implementable from the runtime. - The normal way for this to happen is for there to be a CLEANUP region - contained within this MUST_NOT_THROW region. Note that if the - runtime handles the MUST_NOT_THROW region, we have no control over - what termination function is called; it will be decided by the - personality function in effect for this CIE. */ - tree failure_decl; - /* The location assigned to the call of FAILURE_DECL, if expanded. */ - location_t failure_loc; - } GTY ((tag ("ERT_MUST_NOT_THROW"))) must_not_throw; - } GTY ((desc ("%0.type"))) u; - - /* The list of landing pads associated with this region. */ - struct eh_landing_pad_d *landing_pads; - - /* EXC_PTR and FILTER values copied from the runtime for this region. - Each region gets its own psuedos so that if there are nested exceptions - we do not overwrite the values of the first exception. */ - rtx exc_ptr_reg, filter_reg; - - /* True if this region should use __cxa_end_cleanup instead - of _Unwind_Resume. */ - bool use_cxa_end_cleanup; -}; - -typedef struct eh_landing_pad_d *eh_landing_pad; -typedef struct eh_catch_d *eh_catch; -typedef struct eh_region_d *eh_region; - - - - -/* The exception status for each function. */ - -struct GTY(()) eh_status -{ - /* The tree of all regions for this function. */ - eh_region region_tree; - - /* The same information as an indexable array. */ - vec *region_array; - - /* The landing pads as an indexable array. */ - vec *lp_array; - - /* At the gimple level, a mapping from gimple statement to landing pad - or must-not-throw region. See record_stmt_eh_region. */ - hash_map *GTY(()) throw_stmt_table; - - /* All of the runtime type data used by the function. These objects - are emitted to the lang-specific-data-area for the function. */ - vec *ttype_data; - - /* The table of all action chains. These encode the eh_region tree in - a compact form for use by the runtime, and is also emitted to the - lang-specific-data-area. Note that the ARM EABI uses a different - format for the encoding than all other ports. */ - union eh_status_u { - vec *GTY((tag ("1"))) arm_eabi; - vec *GTY((tag ("0"))) other; - } GTY ((desc ("targetm.arm_eabi_unwinder"))) ehspec_data; -}; - - -/* Invokes CALLBACK for every exception handler label. Only used by old - loop hackery; should not be used by new code. */ -extern void for_each_eh_label (void (*) (rtx)); - -extern void init_eh_for_function (void); - -extern void remove_eh_landing_pad (eh_landing_pad); -extern void remove_eh_handler (eh_region); -extern void remove_unreachable_eh_regions (sbitmap); - -extern bool current_function_has_exception_handlers (void); -extern void output_function_exception_table (const char *); - -extern rtx expand_builtin_eh_pointer (tree); -extern rtx expand_builtin_eh_filter (tree); -extern rtx expand_builtin_eh_copy_values (tree); -extern void expand_builtin_unwind_init (void); -extern rtx expand_builtin_eh_return_data_regno (tree); -extern rtx expand_builtin_extract_return_addr (tree); -extern void expand_builtin_init_dwarf_reg_sizes (tree); -extern rtx expand_builtin_frob_return_addr (tree); -extern rtx expand_builtin_dwarf_sp_column (void); -extern void expand_builtin_eh_return (tree, tree); -extern void expand_eh_return (void); -extern rtx expand_builtin_extend_pointer (tree); -extern void expand_dw2_landing_pad_for_region (eh_region); - -typedef tree (*duplicate_eh_regions_map) (tree, void *); -extern hash_map *duplicate_eh_regions - (struct function *, eh_region, int, duplicate_eh_regions_map, void *); - -extern void sjlj_emit_function_exit_after (rtx_insn *); - -extern eh_region gen_eh_region_cleanup (eh_region); -extern eh_region gen_eh_region_try (eh_region); -extern eh_region gen_eh_region_allowed (eh_region, tree); -extern eh_region gen_eh_region_must_not_throw (eh_region); - -extern eh_catch gen_eh_region_catch (eh_region, tree); -extern eh_landing_pad gen_eh_landing_pad (eh_region); - -extern eh_region get_eh_region_from_number_fn (struct function *, int); -extern eh_region get_eh_region_from_number (int); -extern eh_landing_pad get_eh_landing_pad_from_number_fn (struct function*,int); -extern eh_landing_pad get_eh_landing_pad_from_number (int); -extern eh_region get_eh_region_from_lp_number_fn (struct function *, int); -extern eh_region get_eh_region_from_lp_number (int); - -extern eh_region eh_region_outermost (struct function *, eh_region, eh_region); - -extern void make_reg_eh_region_note (rtx insn, int ecf_flags, int lp_nr); -extern void make_reg_eh_region_note_nothrow_nononlocal (rtx); - -extern void verify_eh_tree (struct function *); -extern void dump_eh_tree (FILE *, struct function *); -void debug_eh_tree (struct function *); -extern void add_type_for_runtime (tree); -extern tree lookup_type_for_runtime (tree); -extern void assign_filter_values (void); - -extern eh_region get_eh_region_from_rtx (const_rtx); -extern eh_landing_pad get_eh_landing_pad_from_rtx (const_rtx); - -extern void finish_eh_generation (void); - -struct GTY(()) throw_stmt_node { - gimple stmt; - int lp_nr; -}; - -extern hash_map *get_eh_throw_stmt_table (struct function *); -extern void set_eh_throw_stmt_table (function *, hash_map *); - -enum eh_personality_kind { - eh_personality_none, - eh_personality_any, - eh_personality_lang -}; - -extern enum eh_personality_kind -function_needs_eh_personality (struct function *); - -/* Pre-order iteration within the eh_region tree. */ - -static inline eh_region -ehr_next (eh_region r, eh_region start) -{ - if (r->inner) - r = r->inner; - else if (r->next_peer && r != start) - r = r->next_peer; - else - { - do - { - r = r->outer; - if (r == start) - return NULL; - } - while (r->next_peer == NULL); - r = r->next_peer; - } - return r; -} - -#define FOR_ALL_EH_REGION_AT(R, START) \ - for ((R) = (START); (R) != NULL; (R) = ehr_next (R, START)) - -#define FOR_ALL_EH_REGION_FN(R, FN) \ - for ((R) = (FN)->eh->region_tree; (R) != NULL; (R) = ehr_next (R, NULL)) - -#define FOR_ALL_EH_REGION(R) FOR_ALL_EH_REGION_FN (R, cfun) - -#endif diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/explow.h b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/explow.h deleted file mode 100644 index 48f1859..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/explow.h +++ /dev/null @@ -1,113 +0,0 @@ -/* Export function prototypes from explow.c. - Copyright (C) 2015-2016 Free Software Foundation, Inc. - -This file is part of GCC. - -GCC is free software; you can redistribute it and/or modify it under -the terms of the GNU General Public License as published by the Free -Software Foundation; either version 3, or (at your option) any later -version. - -GCC is distributed in the hope that it will be useful, but WITHOUT ANY -WARRANTY; without even the implied warranty of MERCHANTABILITY or -FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -for more details. - -You should have received a copy of the GNU General Public License -along with GCC; see the file COPYING3. If not see -. */ - -#ifndef GCC_EXPLOW_H -#define GCC_EXPLOW_H - -/* Return a memory reference like MEMREF, but which is known to have a - valid address. */ -extern rtx validize_mem (rtx); - -extern rtx use_anchored_address (rtx); - -/* Copy given rtx to a new temp reg and return that. */ -extern rtx copy_to_reg (rtx); - -/* Like copy_to_reg but always make the reg Pmode. */ -extern rtx copy_addr_to_reg (rtx); - -/* Like copy_to_reg but always make the reg the specified mode MODE. */ -extern rtx copy_to_mode_reg (machine_mode, rtx); - -/* Copy given rtx to given temp reg and return that. */ -extern rtx copy_to_suggested_reg (rtx, rtx, machine_mode); - -/* Copy a value to a register if it isn't already a register. - Args are mode (in case value is a constant) and the value. */ -extern rtx force_reg (machine_mode, rtx); - -/* Return given rtx, copied into a new temp reg if it was in memory. */ -extern rtx force_not_mem (rtx); - -/* Return mode and signedness to use when an argument or result in the - given mode is promoted. */ -extern machine_mode promote_function_mode (const_tree, machine_mode, int *, - const_tree, int); - -/* Return mode and signedness to use when an object in the given mode - is promoted. */ -extern machine_mode promote_mode (const_tree, machine_mode, int *); - -/* Return mode and signedness to use when object is promoted. */ -machine_mode promote_decl_mode (const_tree, int *); - -/* Remove some bytes from the stack. An rtx says how many. */ -extern void adjust_stack (rtx); - -/* Add some bytes to the stack. An rtx says how many. */ -extern void anti_adjust_stack (rtx); - -/* Add some bytes to the stack while probing it. An rtx says how many. */ -extern void anti_adjust_stack_and_probe (rtx, bool); - -/* This enum is used for the following two functions. */ -enum save_level {SAVE_BLOCK, SAVE_FUNCTION, SAVE_NONLOCAL}; - -/* Save the stack pointer at the specified level. */ -extern void emit_stack_save (enum save_level, rtx *); - -/* Restore the stack pointer from a save area of the specified level. */ -extern void emit_stack_restore (enum save_level, rtx); - -/* Invoke emit_stack_save for the nonlocal_goto_save_area. */ -extern void update_nonlocal_goto_save_area (void); - -/* Allocate some space on the stack dynamically and return its address. */ -extern rtx allocate_dynamic_stack_space (rtx, unsigned, unsigned, bool); - -/* Emit one stack probe at ADDRESS, an address within the stack. */ -extern void emit_stack_probe (rtx); - -/* Probe a range of stack addresses from FIRST to FIRST+SIZE, inclusive. - FIRST is a constant and size is a Pmode RTX. These are offsets from - the current stack pointer. STACK_GROWS_DOWNWARD says whether to add - or subtract them from the stack pointer. */ -extern void probe_stack_range (HOST_WIDE_INT, rtx); - -/* Return an rtx that refers to the value returned by a library call - in its original home. This becomes invalid if any more code is emitted. */ -extern rtx hard_libcall_value (machine_mode, rtx); - -/* Return an rtx that refers to the value returned by a function - in its original home. This becomes invalid if any more code is emitted. */ -extern rtx hard_function_value (const_tree, const_tree, const_tree, int); - -/* Convert arg to a valid memory address for specified machine mode that points - to a specific named address space, by emitting insns to perform arithmetic - if necessary. */ -extern rtx memory_address_addr_space (machine_mode, rtx, addr_space_t); - -extern rtx eliminate_constant_term (rtx, rtx *); - -/* Like memory_address_addr_space, except assume the memory address points to - the generic named address space. */ -#define memory_address(MODE,RTX) \ - memory_address_addr_space ((MODE), (RTX), ADDR_SPACE_GENERIC) - -#endif /* GCC_EXPLOW_H */ diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/expmed.h b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/expmed.h deleted file mode 100644 index 1378192..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/expmed.h +++ /dev/null @@ -1,718 +0,0 @@ -/* Target-dependent costs for expmed.c. - Copyright (C) 1987-2015 Free Software Foundation, Inc. - -This file is part of GCC. - -GCC is free software; you can redistribute it and/or modify it under -the terms of the GNU General Public License as published by the Free -Software Foundation; either version 3, or (at your option; any later -version. - -GCC is distributed in the hope that it will be useful, but WITHOUT ANY -WARRANTY; without even the implied warranty of MERCHANTABILITY or -FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -for more details. - -You should have received a copy of the GNU General Public License -along with GCC; see the file COPYING3. If not see -. */ - -#ifndef EXPMED_H -#define EXPMED_H 1 - -#include "insn-codes.h" - -enum alg_code { - alg_unknown, - alg_zero, - alg_m, alg_shift, - alg_add_t_m2, - alg_sub_t_m2, - alg_add_factor, - alg_sub_factor, - alg_add_t2_m, - alg_sub_t2_m, - alg_impossible -}; - -/* This structure holds the "cost" of a multiply sequence. The - "cost" field holds the total rtx_cost of every operator in the - synthetic multiplication sequence, hence cost(a op b) is defined - as rtx_cost(op) + cost(a) + cost(b), where cost(leaf) is zero. - The "latency" field holds the minimum possible latency of the - synthetic multiply, on a hypothetical infinitely parallel CPU. - This is the critical path, or the maximum height, of the expression - tree which is the sum of rtx_costs on the most expensive path from - any leaf to the root. Hence latency(a op b) is defined as zero for - leaves and rtx_cost(op) + max(latency(a), latency(b)) otherwise. */ - -struct mult_cost { - short cost; /* Total rtx_cost of the multiplication sequence. */ - short latency; /* The latency of the multiplication sequence. */ -}; - -/* This macro is used to compare a pointer to a mult_cost against an - single integer "rtx_cost" value. This is equivalent to the macro - CHEAPER_MULT_COST(X,Z) where Z = {Y,Y}. */ -#define MULT_COST_LESS(X,Y) ((X)->cost < (Y) \ - || ((X)->cost == (Y) && (X)->latency < (Y))) - -/* This macro is used to compare two pointers to mult_costs against - each other. The macro returns true if X is cheaper than Y. - Currently, the cheaper of two mult_costs is the one with the - lower "cost". If "cost"s are tied, the lower latency is cheaper. */ -#define CHEAPER_MULT_COST(X,Y) ((X)->cost < (Y)->cost \ - || ((X)->cost == (Y)->cost \ - && (X)->latency < (Y)->latency)) - -/* This structure records a sequence of operations. - `ops' is the number of operations recorded. - `cost' is their total cost. - The operations are stored in `op' and the corresponding - logarithms of the integer coefficients in `log'. - - These are the operations: - alg_zero total := 0; - alg_m total := multiplicand; - alg_shift total := total * coeff - alg_add_t_m2 total := total + multiplicand * coeff; - alg_sub_t_m2 total := total - multiplicand * coeff; - alg_add_factor total := total * coeff + total; - alg_sub_factor total := total * coeff - total; - alg_add_t2_m total := total * coeff + multiplicand; - alg_sub_t2_m total := total * coeff - multiplicand; - - The first operand must be either alg_zero or alg_m. */ - -struct algorithm -{ - struct mult_cost cost; - short ops; - /* The size of the OP and LOG fields are not directly related to the - word size, but the worst-case algorithms will be if we have few - consecutive ones or zeros, i.e., a multiplicand like 10101010101... - In that case we will generate shift-by-2, add, shift-by-2, add,..., - in total wordsize operations. */ - enum alg_code op[MAX_BITS_PER_WORD]; - char log[MAX_BITS_PER_WORD]; -}; - -/* The entry for our multiplication cache/hash table. */ -struct alg_hash_entry { - /* The number we are multiplying by. */ - unsigned HOST_WIDE_INT t; - - /* The mode in which we are multiplying something by T. */ - machine_mode mode; - - /* The best multiplication algorithm for t. */ - enum alg_code alg; - - /* The cost of multiplication if ALG_CODE is not alg_impossible. - Otherwise, the cost within which multiplication by T is - impossible. */ - struct mult_cost cost; - - /* Optimized for speed? */ - bool speed; -}; - -/* The number of cache/hash entries. */ -#if HOST_BITS_PER_WIDE_INT == 64 -#define NUM_ALG_HASH_ENTRIES 1031 -#else -#define NUM_ALG_HASH_ENTRIES 307 -#endif - -#define NUM_MODE_INT \ - (MAX_MODE_INT - MIN_MODE_INT + 1) -#define NUM_MODE_PARTIAL_INT \ - (MIN_MODE_PARTIAL_INT == VOIDmode ? 0 \ - : MAX_MODE_PARTIAL_INT - MIN_MODE_PARTIAL_INT + 1) -#define NUM_MODE_VECTOR_INT \ - (MIN_MODE_VECTOR_INT == VOIDmode ? 0 \ - : MAX_MODE_VECTOR_INT - MIN_MODE_VECTOR_INT + 1) - -#define NUM_MODE_IP_INT (NUM_MODE_INT + NUM_MODE_PARTIAL_INT) -#define NUM_MODE_IPV_INT (NUM_MODE_IP_INT + NUM_MODE_VECTOR_INT) - -struct expmed_op_cheap { - bool cheap[2][NUM_MODE_IPV_INT]; -}; - -struct expmed_op_costs { - int cost[2][NUM_MODE_IPV_INT]; -}; - -/* Target-dependent globals. */ -struct target_expmed { - /* Each entry of ALG_HASH caches alg_code for some integer. This is - actually a hash table. If we have a collision, that the older - entry is kicked out. */ - struct alg_hash_entry x_alg_hash[NUM_ALG_HASH_ENTRIES]; - - /* True if x_alg_hash might already have been used. */ - bool x_alg_hash_used_p; - - /* Nonzero means divides or modulus operations are relatively cheap for - powers of two, so don't use branches; emit the operation instead. - Usually, this will mean that the MD file will emit non-branch - sequences. */ - struct expmed_op_cheap x_sdiv_pow2_cheap; - struct expmed_op_cheap x_smod_pow2_cheap; - - /* Cost of various pieces of RTL. Note that some of these are indexed by - shift count and some by mode. */ - int x_zero_cost[2]; - struct expmed_op_costs x_add_cost; - struct expmed_op_costs x_neg_cost; - struct expmed_op_costs x_shift_cost[MAX_BITS_PER_WORD]; - struct expmed_op_costs x_shiftadd_cost[MAX_BITS_PER_WORD]; - struct expmed_op_costs x_shiftsub0_cost[MAX_BITS_PER_WORD]; - struct expmed_op_costs x_shiftsub1_cost[MAX_BITS_PER_WORD]; - struct expmed_op_costs x_mul_cost; - struct expmed_op_costs x_sdiv_cost; - struct expmed_op_costs x_udiv_cost; - int x_mul_widen_cost[2][NUM_MODE_INT]; - int x_mul_highpart_cost[2][NUM_MODE_INT]; - - /* Conversion costs are only defined between two scalar integer modes - of different sizes. The first machine mode is the destination mode, - and the second is the source mode. */ - int x_convert_cost[2][NUM_MODE_IP_INT][NUM_MODE_IP_INT]; -}; - -extern struct target_expmed default_target_expmed; -#if SWITCHABLE_TARGET -extern struct target_expmed *this_target_expmed; -#else -#define this_target_expmed (&default_target_expmed) -#endif - -/* Return a pointer to the alg_hash_entry at IDX. */ - -static inline struct alg_hash_entry * -alg_hash_entry_ptr (int idx) -{ - return &this_target_expmed->x_alg_hash[idx]; -} - -/* Return true if the x_alg_hash field might have been used. */ - -static inline bool -alg_hash_used_p (void) -{ - return this_target_expmed->x_alg_hash_used_p; -} - -/* Set whether the x_alg_hash field might have been used. */ - -static inline void -set_alg_hash_used_p (bool usedp) -{ - this_target_expmed->x_alg_hash_used_p = usedp; -} - -/* Compute an index into the cost arrays by mode class. */ - -static inline int -expmed_mode_index (machine_mode mode) -{ - switch (GET_MODE_CLASS (mode)) - { - case MODE_INT: - return mode - MIN_MODE_INT; - case MODE_PARTIAL_INT: - /* If there are no partial integer modes, help the compiler - to figure out this will never happen. See PR59934. */ - if (MIN_MODE_PARTIAL_INT != VOIDmode) - return mode - MIN_MODE_PARTIAL_INT + NUM_MODE_INT; - break; - case MODE_VECTOR_INT: - /* If there are no vector integer modes, help the compiler - to figure out this will never happen. See PR59934. */ - if (MIN_MODE_VECTOR_INT != VOIDmode) - return mode - MIN_MODE_VECTOR_INT + NUM_MODE_IP_INT; - break; - default: - break; - } - gcc_unreachable (); -} - -/* Return a pointer to a boolean contained in EOC indicating whether - a particular operation performed in MODE is cheap when optimizing - for SPEED. */ - -static inline bool * -expmed_op_cheap_ptr (struct expmed_op_cheap *eoc, bool speed, - machine_mode mode) -{ - int idx = expmed_mode_index (mode); - return &eoc->cheap[speed][idx]; -} - -/* Return a pointer to a cost contained in COSTS when a particular - operation is performed in MODE when optimizing for SPEED. */ - -static inline int * -expmed_op_cost_ptr (struct expmed_op_costs *costs, bool speed, - machine_mode mode) -{ - int idx = expmed_mode_index (mode); - return &costs->cost[speed][idx]; -} - -/* Subroutine of {set_,}sdiv_pow2_cheap. Not to be used otherwise. */ - -static inline bool * -sdiv_pow2_cheap_ptr (bool speed, machine_mode mode) -{ - return expmed_op_cheap_ptr (&this_target_expmed->x_sdiv_pow2_cheap, - speed, mode); -} - -/* Set whether a signed division by a power of 2 is cheap in MODE - when optimizing for SPEED. */ - -static inline void -set_sdiv_pow2_cheap (bool speed, machine_mode mode, bool cheap_p) -{ - *sdiv_pow2_cheap_ptr (speed, mode) = cheap_p; -} - -/* Return whether a signed division by a power of 2 is cheap in MODE - when optimizing for SPEED. */ - -static inline bool -sdiv_pow2_cheap (bool speed, machine_mode mode) -{ - return *sdiv_pow2_cheap_ptr (speed, mode); -} - -/* Subroutine of {set_,}smod_pow2_cheap. Not to be used otherwise. */ - -static inline bool * -smod_pow2_cheap_ptr (bool speed, machine_mode mode) -{ - return expmed_op_cheap_ptr (&this_target_expmed->x_smod_pow2_cheap, - speed, mode); -} - -/* Set whether a signed modulo by a power of 2 is CHEAP in MODE when - optimizing for SPEED. */ - -static inline void -set_smod_pow2_cheap (bool speed, machine_mode mode, bool cheap) -{ - *smod_pow2_cheap_ptr (speed, mode) = cheap; -} - -/* Return whether a signed modulo by a power of 2 is cheap in MODE - when optimizing for SPEED. */ - -static inline bool -smod_pow2_cheap (bool speed, machine_mode mode) -{ - return *smod_pow2_cheap_ptr (speed, mode); -} - -/* Subroutine of {set_,}zero_cost. Not to be used otherwise. */ - -static inline int * -zero_cost_ptr (bool speed) -{ - return &this_target_expmed->x_zero_cost[speed]; -} - -/* Set the COST of loading zero when optimizing for SPEED. */ - -static inline void -set_zero_cost (bool speed, int cost) -{ - *zero_cost_ptr (speed) = cost; -} - -/* Return the COST of loading zero when optimizing for SPEED. */ - -static inline int -zero_cost (bool speed) -{ - return *zero_cost_ptr (speed); -} - -/* Subroutine of {set_,}add_cost. Not to be used otherwise. */ - -static inline int * -add_cost_ptr (bool speed, machine_mode mode) -{ - return expmed_op_cost_ptr (&this_target_expmed->x_add_cost, speed, mode); -} - -/* Set the COST of computing an add in MODE when optimizing for SPEED. */ - -static inline void -set_add_cost (bool speed, machine_mode mode, int cost) -{ - *add_cost_ptr (speed, mode) = cost; -} - -/* Return the cost of computing an add in MODE when optimizing for SPEED. */ - -static inline int -add_cost (bool speed, machine_mode mode) -{ - return *add_cost_ptr (speed, mode); -} - -/* Subroutine of {set_,}neg_cost. Not to be used otherwise. */ - -static inline int * -neg_cost_ptr (bool speed, machine_mode mode) -{ - return expmed_op_cost_ptr (&this_target_expmed->x_neg_cost, speed, mode); -} - -/* Set the COST of computing a negation in MODE when optimizing for SPEED. */ - -static inline void -set_neg_cost (bool speed, machine_mode mode, int cost) -{ - *neg_cost_ptr (speed, mode) = cost; -} - -/* Return the cost of computing a negation in MODE when optimizing for - SPEED. */ - -static inline int -neg_cost (bool speed, machine_mode mode) -{ - return *neg_cost_ptr (speed, mode); -} - -/* Subroutine of {set_,}shift_cost. Not to be used otherwise. */ - -static inline int * -shift_cost_ptr (bool speed, machine_mode mode, int bits) -{ - return expmed_op_cost_ptr (&this_target_expmed->x_shift_cost[bits], - speed, mode); -} - -/* Set the COST of doing a shift in MODE by BITS when optimizing for SPEED. */ - -static inline void -set_shift_cost (bool speed, machine_mode mode, int bits, int cost) -{ - *shift_cost_ptr (speed, mode, bits) = cost; -} - -/* Return the cost of doing a shift in MODE by BITS when optimizing for - SPEED. */ - -static inline int -shift_cost (bool speed, machine_mode mode, int bits) -{ - return *shift_cost_ptr (speed, mode, bits); -} - -/* Subroutine of {set_,}shiftadd_cost. Not to be used otherwise. */ - -static inline int * -shiftadd_cost_ptr (bool speed, machine_mode mode, int bits) -{ - return expmed_op_cost_ptr (&this_target_expmed->x_shiftadd_cost[bits], - speed, mode); -} - -/* Set the COST of doing a shift in MODE by BITS followed by an add when - optimizing for SPEED. */ - -static inline void -set_shiftadd_cost (bool speed, machine_mode mode, int bits, int cost) -{ - *shiftadd_cost_ptr (speed, mode, bits) = cost; -} - -/* Return the cost of doing a shift in MODE by BITS followed by an add - when optimizing for SPEED. */ - -static inline int -shiftadd_cost (bool speed, machine_mode mode, int bits) -{ - return *shiftadd_cost_ptr (speed, mode, bits); -} - -/* Subroutine of {set_,}shiftsub0_cost. Not to be used otherwise. */ - -static inline int * -shiftsub0_cost_ptr (bool speed, machine_mode mode, int bits) -{ - return expmed_op_cost_ptr (&this_target_expmed->x_shiftsub0_cost[bits], - speed, mode); -} - -/* Set the COST of doing a shift in MODE by BITS and then subtracting a - value when optimizing for SPEED. */ - -static inline void -set_shiftsub0_cost (bool speed, machine_mode mode, int bits, int cost) -{ - *shiftsub0_cost_ptr (speed, mode, bits) = cost; -} - -/* Return the cost of doing a shift in MODE by BITS and then subtracting - a value when optimizing for SPEED. */ - -static inline int -shiftsub0_cost (bool speed, machine_mode mode, int bits) -{ - return *shiftsub0_cost_ptr (speed, mode, bits); -} - -/* Subroutine of {set_,}shiftsub1_cost. Not to be used otherwise. */ - -static inline int * -shiftsub1_cost_ptr (bool speed, machine_mode mode, int bits) -{ - return expmed_op_cost_ptr (&this_target_expmed->x_shiftsub1_cost[bits], - speed, mode); -} - -/* Set the COST of subtracting a shift in MODE by BITS from a value when - optimizing for SPEED. */ - -static inline void -set_shiftsub1_cost (bool speed, machine_mode mode, int bits, int cost) -{ - *shiftsub1_cost_ptr (speed, mode, bits) = cost; -} - -/* Return the cost of subtracting a shift in MODE by BITS from a value - when optimizing for SPEED. */ - -static inline int -shiftsub1_cost (bool speed, machine_mode mode, int bits) -{ - return *shiftsub1_cost_ptr (speed, mode, bits); -} - -/* Subroutine of {set_,}mul_cost. Not to be used otherwise. */ - -static inline int * -mul_cost_ptr (bool speed, machine_mode mode) -{ - return expmed_op_cost_ptr (&this_target_expmed->x_mul_cost, speed, mode); -} - -/* Set the COST of doing a multiplication in MODE when optimizing for - SPEED. */ - -static inline void -set_mul_cost (bool speed, machine_mode mode, int cost) -{ - *mul_cost_ptr (speed, mode) = cost; -} - -/* Return the cost of doing a multiplication in MODE when optimizing - for SPEED. */ - -static inline int -mul_cost (bool speed, machine_mode mode) -{ - return *mul_cost_ptr (speed, mode); -} - -/* Subroutine of {set_,}sdiv_cost. Not to be used otherwise. */ - -static inline int * -sdiv_cost_ptr (bool speed, machine_mode mode) -{ - return expmed_op_cost_ptr (&this_target_expmed->x_sdiv_cost, speed, mode); -} - -/* Set the COST of doing a signed division in MODE when optimizing - for SPEED. */ - -static inline void -set_sdiv_cost (bool speed, machine_mode mode, int cost) -{ - *sdiv_cost_ptr (speed, mode) = cost; -} - -/* Return the cost of doing a signed division in MODE when optimizing - for SPEED. */ - -static inline int -sdiv_cost (bool speed, machine_mode mode) -{ - return *sdiv_cost_ptr (speed, mode); -} - -/* Subroutine of {set_,}udiv_cost. Not to be used otherwise. */ - -static inline int * -udiv_cost_ptr (bool speed, machine_mode mode) -{ - return expmed_op_cost_ptr (&this_target_expmed->x_udiv_cost, speed, mode); -} - -/* Set the COST of doing an unsigned division in MODE when optimizing - for SPEED. */ - -static inline void -set_udiv_cost (bool speed, machine_mode mode, int cost) -{ - *udiv_cost_ptr (speed, mode) = cost; -} - -/* Return the cost of doing an unsigned division in MODE when - optimizing for SPEED. */ - -static inline int -udiv_cost (bool speed, machine_mode mode) -{ - return *udiv_cost_ptr (speed, mode); -} - -/* Subroutine of {set_,}mul_widen_cost. Not to be used otherwise. */ - -static inline int * -mul_widen_cost_ptr (bool speed, machine_mode mode) -{ - gcc_assert (GET_MODE_CLASS (mode) == MODE_INT); - - return &this_target_expmed->x_mul_widen_cost[speed][mode - MIN_MODE_INT]; -} - -/* Set the COST for computing a widening multiplication in MODE when - optimizing for SPEED. */ - -static inline void -set_mul_widen_cost (bool speed, machine_mode mode, int cost) -{ - *mul_widen_cost_ptr (speed, mode) = cost; -} - -/* Return the cost for computing a widening multiplication in MODE when - optimizing for SPEED. */ - -static inline int -mul_widen_cost (bool speed, machine_mode mode) -{ - return *mul_widen_cost_ptr (speed, mode); -} - -/* Subroutine of {set_,}mul_highpart_cost. Not to be used otherwise. */ - -static inline int * -mul_highpart_cost_ptr (bool speed, machine_mode mode) -{ - gcc_assert (GET_MODE_CLASS (mode) == MODE_INT); - - return &this_target_expmed->x_mul_highpart_cost[speed][mode - MIN_MODE_INT]; -} - -/* Set the COST for computing the high part of a multiplication in MODE - when optimizing for SPEED. */ - -static inline void -set_mul_highpart_cost (bool speed, machine_mode mode, int cost) -{ - *mul_highpart_cost_ptr (speed, mode) = cost; -} - -/* Return the cost for computing the high part of a multiplication in MODE - when optimizing for SPEED. */ - -static inline int -mul_highpart_cost (bool speed, machine_mode mode) -{ - return *mul_highpart_cost_ptr (speed, mode); -} - -/* Subroutine of {set_,}convert_cost. Not to be used otherwise. */ - -static inline int * -convert_cost_ptr (machine_mode to_mode, machine_mode from_mode, - bool speed) -{ - int to_idx = expmed_mode_index (to_mode); - int from_idx = expmed_mode_index (from_mode); - - gcc_assert (IN_RANGE (to_idx, 0, NUM_MODE_IP_INT - 1)); - gcc_assert (IN_RANGE (from_idx, 0, NUM_MODE_IP_INT - 1)); - - return &this_target_expmed->x_convert_cost[speed][to_idx][from_idx]; -} - -/* Set the COST for converting from FROM_MODE to TO_MODE when optimizing - for SPEED. */ - -static inline void -set_convert_cost (machine_mode to_mode, machine_mode from_mode, - bool speed, int cost) -{ - *convert_cost_ptr (to_mode, from_mode, speed) = cost; -} - -/* Return the cost for converting from FROM_MODE to TO_MODE when optimizing - for SPEED. */ - -static inline int -convert_cost (machine_mode to_mode, machine_mode from_mode, - bool speed) -{ - return *convert_cost_ptr (to_mode, from_mode, speed); -} - -extern int mult_by_coeff_cost (HOST_WIDE_INT, machine_mode, bool); -extern rtx emit_cstore (rtx target, enum insn_code icode, enum rtx_code code, - enum machine_mode mode, enum machine_mode compare_mode, - int unsignedp, rtx x, rtx y, int normalizep, - enum machine_mode target_mode); - -/* Arguments MODE, RTX: return an rtx for the negation of that value. - May emit insns. */ -extern rtx negate_rtx (machine_mode, rtx); - -/* Expand a logical AND operation. */ -extern rtx expand_and (machine_mode, rtx, rtx, rtx); - -/* Emit a store-flag operation. */ -extern rtx emit_store_flag (rtx, enum rtx_code, rtx, rtx, machine_mode, - int, int); - -/* Like emit_store_flag, but always succeeds. */ -extern rtx emit_store_flag_force (rtx, enum rtx_code, rtx, rtx, - machine_mode, int, int); - -/* Choose a minimal N + 1 bit approximation to 1/D that can be used to - replace division by D, and put the least significant N bits of the result - in *MULTIPLIER_PTR and return the most significant bit. */ -extern unsigned HOST_WIDE_INT choose_multiplier (unsigned HOST_WIDE_INT, int, - int, unsigned HOST_WIDE_INT *, - int *, int *); - -#ifdef TREE_CODE -extern rtx expand_variable_shift (enum tree_code, machine_mode, - rtx, tree, rtx, int); -extern rtx expand_shift (enum tree_code, machine_mode, rtx, int, rtx, - int); -extern rtx expand_divmod (int, enum tree_code, machine_mode, rtx, rtx, - rtx, int); -#endif - -extern void store_bit_field (rtx, unsigned HOST_WIDE_INT, - unsigned HOST_WIDE_INT, - unsigned HOST_WIDE_INT, - unsigned HOST_WIDE_INT, - machine_mode, rtx); -extern rtx extract_bit_field (rtx, unsigned HOST_WIDE_INT, - unsigned HOST_WIDE_INT, int, rtx, - machine_mode, machine_mode); -extern rtx extract_low_bits (machine_mode, machine_mode, rtx); -extern rtx expand_mult (machine_mode, rtx, rtx, rtx, int); -extern rtx expand_mult_highpart_adjust (machine_mode, rtx, rtx, rtx, rtx, int); - -#endif // EXPMED_H diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/expr.h b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/expr.h deleted file mode 100644 index 867852e..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/expr.h +++ /dev/null @@ -1,303 +0,0 @@ -/* Definitions for code generation pass of GNU compiler. - Copyright (C) 1987-2015 Free Software Foundation, Inc. - -This file is part of GCC. - -GCC is free software; you can redistribute it and/or modify it under -the terms of the GNU General Public License as published by the Free -Software Foundation; either version 3, or (at your option) any later -version. - -GCC is distributed in the hope that it will be useful, but WITHOUT ANY -WARRANTY; without even the implied warranty of MERCHANTABILITY or -FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -for more details. - -You should have received a copy of the GNU General Public License -along with GCC; see the file COPYING3. If not see -. */ - -#ifndef GCC_EXPR_H -#define GCC_EXPR_H - -/* This is the 4th arg to `expand_expr'. - EXPAND_STACK_PARM means we are possibly expanding a call param onto - the stack. - EXPAND_SUM means it is ok to return a PLUS rtx or MULT rtx. - EXPAND_INITIALIZER is similar but also record any labels on forced_labels. - EXPAND_CONST_ADDRESS means it is ok to return a MEM whose address - is a constant that is not a legitimate address. - EXPAND_WRITE means we are only going to write to the resulting rtx. - EXPAND_MEMORY means we are interested in a memory result, even if - the memory is constant and we could have propagated a constant value, - or the memory is unaligned on a STRICT_ALIGNMENT target. */ -enum expand_modifier {EXPAND_NORMAL = 0, EXPAND_STACK_PARM, EXPAND_SUM, - EXPAND_CONST_ADDRESS, EXPAND_INITIALIZER, EXPAND_WRITE, - EXPAND_MEMORY}; - -/* Prevent the compiler from deferring stack pops. See - inhibit_defer_pop for more information. */ -#define NO_DEFER_POP (inhibit_defer_pop += 1) - -/* Allow the compiler to defer stack pops. See inhibit_defer_pop for - more information. */ -#define OK_DEFER_POP (inhibit_defer_pop -= 1) - -/* This structure is used to pass around information about exploded - unary, binary and trinary expressions between expand_expr_real_1 and - friends. */ -typedef struct separate_ops -{ - enum tree_code code; - location_t location; - tree type; - tree op0, op1, op2; -} *sepops; - -/* This is run during target initialization to set up which modes can be - used directly in memory and to initialize the block move optab. */ -extern void init_expr_target (void); - -/* This is run at the start of compiling a function. */ -extern void init_expr (void); - -/* Emit some rtl insns to move data between rtx's, converting machine modes. - Both modes must be floating or both fixed. */ -extern void convert_move (rtx, rtx, int); - -/* Convert an rtx to specified machine mode and return the result. */ -extern rtx convert_to_mode (machine_mode, rtx, int); - -/* Convert an rtx to MODE from OLDMODE and return the result. */ -extern rtx convert_modes (machine_mode, machine_mode, rtx, int); - -/* Emit code to move a block Y to a block X. */ - -enum block_op_methods -{ - BLOCK_OP_NORMAL, - BLOCK_OP_NO_LIBCALL, - BLOCK_OP_CALL_PARM, - /* Like BLOCK_OP_NORMAL, but the libcall can be tail call optimized. */ - BLOCK_OP_TAILCALL -}; - -extern GTY(()) tree block_clear_fn; -extern void init_block_move_fn (const char *); -extern void init_block_clear_fn (const char *); - -extern rtx emit_block_move (rtx, rtx, rtx, enum block_op_methods); -extern rtx emit_block_move_via_libcall (rtx, rtx, rtx, bool); -extern rtx emit_block_move_hints (rtx, rtx, rtx, enum block_op_methods, - unsigned int, HOST_WIDE_INT, - unsigned HOST_WIDE_INT, - unsigned HOST_WIDE_INT, - unsigned HOST_WIDE_INT); -extern bool emit_storent_insn (rtx to, rtx from); - -/* Copy all or part of a value X into registers starting at REGNO. - The number of registers to be filled is NREGS. */ -extern void move_block_to_reg (int, rtx, int, machine_mode); - -/* Copy all or part of a BLKmode value X out of registers starting at REGNO. - The number of registers to be filled is NREGS. */ -extern void move_block_from_reg (int, rtx, int); - -/* Generate a non-consecutive group of registers represented by a PARALLEL. */ -extern rtx gen_group_rtx (rtx); - -/* Load a BLKmode value into non-consecutive registers represented by a - PARALLEL. */ -extern void emit_group_load (rtx, rtx, tree, int); - -/* Similarly, but load into new temporaries. */ -extern rtx emit_group_load_into_temps (rtx, rtx, tree, int); - -/* Move a non-consecutive group of registers represented by a PARALLEL into - a non-consecutive group of registers represented by a PARALLEL. */ -extern void emit_group_move (rtx, rtx); - -/* Move a group of registers represented by a PARALLEL into pseudos. */ -extern rtx emit_group_move_into_temps (rtx); - -/* Store a BLKmode value from non-consecutive registers represented by a - PARALLEL. */ -extern void emit_group_store (rtx, rtx, tree, int); - -extern rtx maybe_emit_group_store (rtx, tree); - -/* Copy BLKmode object from a set of registers. */ -extern void copy_blkmode_from_reg (rtx, rtx, tree); - -/* Mark REG as holding a parameter for the next CALL_INSN. - Mode is TYPE_MODE of the non-promoted parameter, or VOIDmode. */ -extern void use_reg_mode (rtx *, rtx, machine_mode); -extern void clobber_reg_mode (rtx *, rtx, machine_mode); - -extern rtx copy_blkmode_to_reg (machine_mode, tree); - -/* Mark REG as holding a parameter for the next CALL_INSN. */ -static inline void -use_reg (rtx *fusage, rtx reg) -{ - use_reg_mode (fusage, reg, VOIDmode); -} - -/* Mark REG as clobbered by the call with FUSAGE as CALL_INSN_FUNCTION_USAGE. */ -static inline void -clobber_reg (rtx *fusage, rtx reg) -{ - clobber_reg_mode (fusage, reg, VOIDmode); -} - -/* Mark NREGS consecutive regs, starting at REGNO, as holding parameters - for the next CALL_INSN. */ -extern void use_regs (rtx *, int, int); - -/* Mark a PARALLEL as holding a parameter for the next CALL_INSN. */ -extern void use_group_regs (rtx *, rtx); - -/* Write zeros through the storage of OBJECT. - If OBJECT has BLKmode, SIZE is its length in bytes. */ -extern rtx clear_storage (rtx, rtx, enum block_op_methods); -extern rtx clear_storage_hints (rtx, rtx, enum block_op_methods, - unsigned int, HOST_WIDE_INT, - unsigned HOST_WIDE_INT, - unsigned HOST_WIDE_INT, - unsigned HOST_WIDE_INT); -/* The same, but always output an library call. */ -rtx set_storage_via_libcall (rtx, rtx, rtx, bool); - -/* Expand a setmem pattern; return true if successful. */ -extern bool set_storage_via_setmem (rtx, rtx, rtx, unsigned int, - unsigned int, HOST_WIDE_INT, - unsigned HOST_WIDE_INT, - unsigned HOST_WIDE_INT, - unsigned HOST_WIDE_INT); - -extern unsigned HOST_WIDE_INT move_by_pieces_ninsns (unsigned HOST_WIDE_INT, - unsigned int, - unsigned int); - -/* Return nonzero if it is desirable to store LEN bytes generated by - CONSTFUN with several move instructions by store_by_pieces - function. CONSTFUNDATA is a pointer which will be passed as argument - in every CONSTFUN call. - ALIGN is maximum alignment we can assume. - MEMSETP is true if this is a real memset/bzero, not a copy - of a const string. */ -extern int can_store_by_pieces (unsigned HOST_WIDE_INT, - rtx (*) (void *, HOST_WIDE_INT, - machine_mode), - void *, unsigned int, bool); - -/* Generate several move instructions to store LEN bytes generated by - CONSTFUN to block TO. (A MEM rtx with BLKmode). CONSTFUNDATA is a - pointer which will be passed as argument in every CONSTFUN call. - ALIGN is maximum alignment we can assume. - MEMSETP is true if this is a real memset/bzero, not a copy. - Returns TO + LEN. */ -extern rtx store_by_pieces (rtx, unsigned HOST_WIDE_INT, - rtx (*) (void *, HOST_WIDE_INT, machine_mode), - void *, unsigned int, bool, int); - -/* Emit insns to set X from Y. */ -extern rtx_insn *emit_move_insn (rtx, rtx); -extern rtx gen_move_insn (rtx, rtx); - -/* Emit insns to set X from Y, with no frills. */ -extern rtx_insn *emit_move_insn_1 (rtx, rtx); - -extern rtx_insn *emit_move_complex_push (machine_mode, rtx, rtx); -extern rtx_insn *emit_move_complex_parts (rtx, rtx); -extern void write_complex_part (rtx, rtx, bool); -extern rtx emit_move_resolve_push (machine_mode, rtx); - -/* Push a block of length SIZE (perhaps variable) - and return an rtx to address the beginning of the block. */ -extern rtx push_block (rtx, int, int); - -/* Generate code to push something onto the stack, given its mode and type. */ -extern void emit_push_insn (rtx, machine_mode, tree, rtx, unsigned int, - int, rtx, int, rtx, rtx, int, rtx); - -/* Expand an assignment that stores the value of FROM into TO. */ -extern void expand_assignment (tree, tree, bool); - -/* Generate code for computing expression EXP, - and storing the value into TARGET. - If SUGGEST_REG is nonzero, copy the value through a register - and return that register, if that is possible. */ -extern rtx store_expr_with_bounds (tree, rtx, int, bool, tree); -extern rtx store_expr (tree, rtx, int, bool); - -/* Given an rtx that may include add and multiply operations, - generate them as insns and return a pseudo-reg containing the value. - Useful after calling expand_expr with 1 as sum_ok. */ -extern rtx force_operand (rtx, rtx); - -/* Work horses for expand_expr. */ -extern rtx expand_expr_real (tree, rtx, machine_mode, - enum expand_modifier, rtx *, bool); -extern rtx expand_expr_real_1 (tree, rtx, machine_mode, - enum expand_modifier, rtx *, bool); -extern rtx expand_expr_real_2 (sepops, rtx, machine_mode, - enum expand_modifier); - -/* Generate code for computing expression EXP. - An rtx for the computed value is returned. The value is never null. - In the case of a void EXP, const0_rtx is returned. */ -static inline rtx -expand_expr (tree exp, rtx target, machine_mode mode, - enum expand_modifier modifier) -{ - return expand_expr_real (exp, target, mode, modifier, NULL, false); -} - -static inline rtx -expand_normal (tree exp) -{ - return expand_expr_real (exp, NULL_RTX, VOIDmode, EXPAND_NORMAL, NULL, false); -} - - -/* Return the tree node and offset if a given argument corresponds to - a string constant. */ -extern tree string_constant (tree, tree *); - -/* Two different ways of generating switch statements. */ -extern int try_casesi (tree, tree, tree, tree, rtx, rtx, rtx, int); -extern int try_tablejump (tree, tree, tree, tree, rtx, rtx, int); - -extern int safe_from_p (const_rtx, tree, int); - -/* Get the personality libfunc for a function decl. */ -rtx get_personality_function (tree); - -/* Determine whether the LEN bytes can be moved by using several move - instructions. Return nonzero if a call to move_by_pieces should - succeed. */ -extern int can_move_by_pieces (unsigned HOST_WIDE_INT, unsigned int); - -extern unsigned HOST_WIDE_INT highest_pow2_factor (const_tree); -bool array_at_struct_end_p (tree); - -/* Return a tree of sizetype representing the size, in bytes, of the element - of EXP, an ARRAY_REF or an ARRAY_RANGE_REF. */ -extern tree array_ref_element_size (tree); - -extern bool categorize_ctor_elements (const_tree, HOST_WIDE_INT *, - HOST_WIDE_INT *, bool *); - -/* Return a tree representing the offset, in bytes, of the field referenced - by EXP. This does not include any offset in DECL_FIELD_BIT_OFFSET. */ -extern tree component_ref_field_offset (tree); - -extern void expand_operands (tree, tree, rtx, rtx*, rtx*, - enum expand_modifier); - -/* rtl.h and tree.h were included. */ -/* Return an rtx for the size in bytes of the value of an expr. */ -extern rtx expr_size (tree); - -#endif /* GCC_EXPR_H */ diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/fibonacci_heap.h b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/fibonacci_heap.h deleted file mode 100644 index 0d9226b..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/fibonacci_heap.h +++ /dev/null @@ -1,634 +0,0 @@ -/* Vector API for GNU compiler. - Copyright (C) 1998-2015 Free Software Foundation, Inc. - Contributed by Daniel Berlin (dan@cgsoftware.com). - Re-implemented in C++ by Martin Liska - -This file is part of GCC. - -GCC is free software; you can redistribute it and/or modify it under -the terms of the GNU General Public License as published by the Free -Software Foundation; either version 3, or (at your option) any later -version. - -GCC is distributed in the hope that it will be useful, but WITHOUT ANY -WARRANTY; without even the implied warranty of MERCHANTABILITY or -FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -for more details. - -You should have received a copy of the GNU General Public License -along with GCC; see the file COPYING3. If not see -. */ - -/* Fibonacci heaps are somewhat complex, but, there's an article in - DDJ that explains them pretty well: - - http://www.ddj.com/articles/1997/9701/9701o/9701o.htm?topic=algoritms - - Introduction to algorithms by Corman and Rivest also goes over them. - - The original paper that introduced them is "Fibonacci heaps and their - uses in improved network optimization algorithms" by Tarjan and - Fredman (JACM 34(3), July 1987). - - Amortized and real worst case time for operations: - - ExtractMin: O(lg n) amortized. O(n) worst case. - DecreaseKey: O(1) amortized. O(lg n) worst case. - Insert: O(1) amortized. - Union: O(1) amortized. */ - -#ifndef GCC_FIBONACCI_HEAP_H -#define GCC_FIBONACCI_HEAP_H - -/* Forward definition. */ - -template -class fibonacci_heap; - -/* Fibonacci heap node class. */ - -template -class fibonacci_node -{ - typedef fibonacci_node fibonacci_node_t; - friend class fibonacci_heap; - -public: - /* Default constructor. */ - fibonacci_node (): m_parent (NULL), m_child (NULL), m_left (this), - m_right (this), m_degree (0), m_mark (0) - { - } - - /* Constructor for a node with given KEY. */ - fibonacci_node (K key): m_parent (NULL), m_child (NULL), m_left (this), - m_right (this), m_key (key), - m_degree (0), m_mark (0) - { - } - - /* Compare fibonacci node with OTHER node. */ - int compare (fibonacci_node_t *other) - { - if (m_key < other->m_key) - return -1; - if (m_key > other->m_key) - return 1; - return 0; - } - - /* Compare the node with a given KEY. */ - int compare_data (K key) - { - return fibonacci_node_t (key).compare (this); - } - - /* Remove fibonacci heap node. */ - fibonacci_node_t *remove (); - - /* Link the node with PARENT. */ - void link (fibonacci_node_t *parent); - - /* Return key associated with the node. */ - K get_key () - { - return m_key; - } - - /* Return data associated with the node. */ - V *get_data () - { - return m_data; - } - -private: - /* Put node B after this node. */ - void insert_after (fibonacci_node_t *b); - - /* Insert fibonacci node B after this node. */ - void insert_before (fibonacci_node_t *b) - { - m_left->insert_after (b); - } - - /* Parent node. */ - fibonacci_node *m_parent; - /* Child node. */ - fibonacci_node *m_child; - /* Left sibling. */ - fibonacci_node *m_left; - /* Right node. */ - fibonacci_node *m_right; - /* Key associated with node. */ - K m_key; - /* Data associated with node. */ - V *m_data; - -#if defined (__GNUC__) && (!defined (SIZEOF_INT) || SIZEOF_INT < 4) - /* Degree of the node. */ - __extension__ unsigned long int m_degree : 31; - /* Mark of the node. */ - __extension__ unsigned long int m_mark : 1; -#else - /* Degree of the node. */ - unsigned int m_degree : 31; - /* Mark of the node. */ - unsigned int m_mark : 1; -#endif -}; - -/* Fibonacci heap class. */ -template -class fibonacci_heap -{ - typedef fibonacci_node fibonacci_node_t; - friend class fibonacci_node; - -public: - /* Default constructor. */ - fibonacci_heap (K global_min_key): m_nodes (0), m_min (NULL), m_root (NULL), - m_global_min_key (global_min_key) - { - } - - /* Destructor. */ - ~fibonacci_heap () - { - while (m_min != NULL) - delete (extract_minimum_node ()); - } - - /* Insert new node given by KEY and DATA associated with the key. */ - fibonacci_node_t *insert (K key, V *data); - - /* Return true if no entry is present. */ - bool empty () - { - return m_nodes == 0; - } - - /* Return the number of nodes. */ - size_t nodes () - { - return m_nodes; - } - - /* Return minimal key presented in the heap. */ - K min_key () - { - if (m_min == NULL) - gcc_unreachable (); - - return m_min->m_key; - } - - /* For given NODE, set new KEY value. */ - K replace_key (fibonacci_node_t *node, K key) - { - K okey = node->m_key; - - replace_key_data (node, key, node->m_data); - return okey; - } - - /* For given NODE, decrease value to new KEY. */ - K decrease_key (fibonacci_node_t *node, K key) - { - gcc_assert (key <= node->m_key); - return replace_key (node, key); - } - - /* For given NODE, set new KEY and DATA value. */ - V *replace_key_data (fibonacci_node_t *node, K key, V *data); - - /* Extract minimum node in the heap. If RELEASE is specified, - memory is released. */ - V *extract_min (bool release = true); - - /* Return value associated with minimum node in the heap. */ - V *min () - { - if (m_min == NULL) - return NULL; - - return m_min->m_data; - } - - /* Replace data associated with NODE and replace it with DATA. */ - V *replace_data (fibonacci_node_t *node, V *data) - { - return replace_key_data (node, node->m_key, data); - } - - /* Delete NODE in the heap. */ - V *delete_node (fibonacci_node_t *node, bool release = true); - - /* Union the heap with HEAPB. */ - fibonacci_heap *union_with (fibonacci_heap *heapb); - -private: - /* Insert new NODE given by KEY and DATA associated with the key. */ - fibonacci_node_t *insert (fibonacci_node_t *node, K key, V *data); - - /* Insert it into the root list. */ - void insert_root (fibonacci_node_t *node); - - /* Remove NODE from PARENT's child list. */ - void cut (fibonacci_node_t *node, fibonacci_node_t *parent); - - /* Process cut of node Y and do it recursivelly. */ - void cascading_cut (fibonacci_node_t *y); - - /* Extract minimum node from the heap. */ - fibonacci_node_t * extract_minimum_node (); - - /* Remove root NODE from the heap. */ - void remove_root (fibonacci_node_t *node); - - /* Consolidate heap. */ - void consolidate (); - - /* Number of nodes. */ - size_t m_nodes; - /* Minimum node of the heap. */ - fibonacci_node_t *m_min; - /* Root node of the heap. */ - fibonacci_node_t *m_root; - /* Global minimum given in the heap construction. */ - K m_global_min_key; -}; - -/* Remove fibonacci heap node. */ - -template -fibonacci_node * -fibonacci_node::remove () -{ - fibonacci_node *ret; - - if (this == m_left) - ret = NULL; - else - ret = m_left; - - if (m_parent != NULL && m_parent->m_child == this) - m_parent->m_child = ret; - - m_right->m_left = m_left; - m_left->m_right = m_right; - - m_parent = NULL; - m_left = this; - m_right = this; - - return ret; -} - -/* Link the node with PARENT. */ - -template -void -fibonacci_node::link (fibonacci_node *parent) -{ - if (parent->m_child == NULL) - parent->m_child = this; - else - parent->m_child->insert_before (this); - m_parent = parent; - parent->m_degree++; - m_mark = 0; -} - -/* Put node B after this node. */ - -template -void -fibonacci_node::insert_after (fibonacci_node *b) -{ - fibonacci_node *a = this; - - if (a == a->m_right) - { - a->m_right = b; - a->m_left = b; - b->m_right = a; - b->m_left = a; - } - else - { - b->m_right = a->m_right; - a->m_right->m_left = b; - a->m_right = b; - b->m_left = a; - } -} - -/* Insert new node given by KEY and DATA associated with the key. */ - -template -fibonacci_node* -fibonacci_heap::insert (K key, V *data) -{ - /* Create the new node. */ - fibonacci_node *node = new fibonacci_node_t (); - - return insert (node, key, data); -} - -/* Insert new NODE given by KEY and DATA associated with the key. */ - -template -fibonacci_node* -fibonacci_heap::insert (fibonacci_node_t *node, K key, V *data) -{ - /* Set the node's data. */ - node->m_data = data; - node->m_key = key; - - /* Insert it into the root list. */ - insert_root (node); - - /* If their was no minimum, or this key is less than the min, - it's the new min. */ - if (m_min == NULL || node->m_key < m_min->m_key) - m_min = node; - - m_nodes++; - - return node; -} - -/* For given NODE, set new KEY and DATA value. */ -template -V* -fibonacci_heap::replace_key_data (fibonacci_node *node, K key, - V *data) -{ - K okey; - fibonacci_node *y; - V *odata = node->m_data; - - /* If we wanted to, we do a real increase by redeleting and - inserting. */ - if (node->compare_data (key) > 0) - { - delete_node (node, false); - - node = new (node) fibonacci_node_t (); - insert (node, key, data); - - return odata; - } - - okey = node->m_key; - node->m_data = data; - node->m_key = key; - y = node->m_parent; - - /* Short-circuit if the key is the same, as we then don't have to - do anything. Except if we're trying to force the new node to - be the new minimum for delete. */ - if (okey == key && okey != m_global_min_key) - return odata; - - /* These two compares are specifically <= 0 to make sure that in the case - of equality, a node we replaced the data on, becomes the new min. This - is needed so that delete's call to extractmin gets the right node. */ - if (y != NULL && node->compare (y) <= 0) - { - cut (node, y); - cascading_cut (y); - } - - if (node->compare (m_min) <= 0) - m_min = node; - - return odata; -} - -/* Extract minimum node in the heap. */ -template -V* -fibonacci_heap::extract_min (bool release) -{ - fibonacci_node *z; - V *ret = NULL; - - /* If we don't have a min set, it means we have no nodes. */ - if (m_min != NULL) - { - /* Otherwise, extract the min node, free the node, and return the - node's data. */ - z = extract_minimum_node (); - ret = z->m_data; - - if (release) - delete (z); - } - - return ret; -} - -/* Delete NODE in the heap, if RELEASE is specified memory is released. */ - -template -V* -fibonacci_heap::delete_node (fibonacci_node *node, bool release) -{ - V *ret = node->m_data; - - /* To perform delete, we just make it the min key, and extract. */ - replace_key (node, m_global_min_key); - if (node != m_min) - { - fprintf (stderr, "Can't force minimum on fibheap.\n"); - abort (); - } - extract_min (release); - - return ret; -} - -/* Union the heap with HEAPB. */ - -template -fibonacci_heap* -fibonacci_heap::union_with (fibonacci_heap *heapb) -{ - fibonacci_heap *heapa = this; - - fibonacci_node *a_root, *b_root, *temp; - - /* If one of the heaps is empty, the union is just the other heap. */ - if ((a_root = heapa->m_root) == NULL) - { - delete (heapa); - return heapb; - } - if ((b_root = heapb->m_root) == NULL) - { - delete (heapb); - return heapa; - } - - /* Merge them to the next nodes on the opposite chain. */ - a_root->m_left->m_right = b_root; - b_root->m_left->m_right = a_root; - temp = a_root->m_left; - a_root->m_left = b_root->m_left; - b_root->m_left = temp; - heapa->m_nodes += heapb->m_nodes; - - /* And set the new minimum, if it's changed. */ - if (heapb->min->compare (heapa->min) < 0) - heapa->m_min = heapb->m_min; - - delete (heapb); - return heapa; -} - -/* Insert it into the root list. */ - -template -void -fibonacci_heap::insert_root (fibonacci_node_t *node) -{ - /* If the heap is currently empty, the new node becomes the singleton - circular root list. */ - if (m_root == NULL) - { - m_root = node; - node->m_left = node; - node->m_right = node; - return; - } - - /* Otherwise, insert it in the circular root list between the root - and it's right node. */ - m_root->insert_after (node); -} - -/* Remove NODE from PARENT's child list. */ - -template -void -fibonacci_heap::cut (fibonacci_node *node, - fibonacci_node *parent) -{ - node->remove (); - parent->m_degree--; - insert_root (node); - node->m_parent = NULL; - node->m_mark = 0; -} - -/* Process cut of node Y and do it recursivelly. */ - -template -void -fibonacci_heap::cascading_cut (fibonacci_node *y) -{ - fibonacci_node *z; - - while ((z = y->m_parent) != NULL) - { - if (y->m_mark == 0) - { - y->m_mark = 1; - return; - } - else - { - cut (y, z); - y = z; - } - } -} - -/* Extract minimum node from the heap. */ -template -fibonacci_node* -fibonacci_heap::extract_minimum_node () -{ - fibonacci_node *ret = m_min; - fibonacci_node *x, *y, *orig; - - /* Attach the child list of the minimum node to the root list of the heap. - If there is no child list, we don't do squat. */ - for (x = ret->m_child, orig = NULL; x != orig && x != NULL; x = y) - { - if (orig == NULL) - orig = x; - y = x->m_right; - x->m_parent = NULL; - insert_root (x); - } - - /* Remove the old root. */ - remove_root (ret); - m_nodes--; - - /* If we are left with no nodes, then the min is NULL. */ - if (m_nodes == 0) - m_min = NULL; - else - { - /* Otherwise, consolidate to find new minimum, as well as do the reorg - work that needs to be done. */ - m_min = ret->m_right; - consolidate (); - } - - return ret; -} - -/* Remove root NODE from the heap. */ - -template -void -fibonacci_heap::remove_root (fibonacci_node *node) -{ - if (node->m_left == node) - m_root = NULL; - else - m_root = node->remove (); -} - -/* Consolidate heap. */ - -template -void fibonacci_heap::consolidate () -{ - int D = 1 + 8 * sizeof (long); - auto_vec *> a (D); - a.safe_grow_cleared (D); - fibonacci_node *w, *x, *y; - int i, d; - - while ((w = m_root) != NULL) - { - x = w; - remove_root (w); - d = x->m_degree; - while (a[d] != NULL) - { - y = a[d]; - if (x->compare (y) > 0) - std::swap (x, y); - y->link (x); - a[d] = NULL; - d++; - } - a[d] = x; - } - m_min = NULL; - for (i = 0; i < D; i++) - if (a[i] != NULL) - { - insert_root (a[i]); - if (m_min == NULL || a[i]->compare (m_min) < 0) - m_min = a[i]; - } -} - -#endif // GCC_FIBONACCI_HEAP_H diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/file-find.h b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/file-find.h deleted file mode 100644 index ecf457f..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/file-find.h +++ /dev/null @@ -1,47 +0,0 @@ -/* Prototypes and data structures used for implementing functions for - finding files relative to GCC binaries. - Copyright (C) 1992-2015 Free Software Foundation, Inc. - -This file is part of GCC. - -GCC is free software; you can redistribute it and/or modify it under -the terms of the GNU General Public License as published by the Free -Software Foundation; either version 3, or (at your option) any later -version. - -GCC is distributed in the hope that it will be useful, but WITHOUT ANY -WARRANTY; without even the implied warranty of MERCHANTABILITY or -FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -for more details. - -You should have received a copy of the GNU General Public License -along with GCC; see the file COPYING3. If not see -. */ - -#ifndef GCC_FILE_FIND_H -#define GCC_FILE_FIND_H - -/* Structure to hold all the directories in which to search for files to - execute. */ - -struct prefix_list -{ - const char *prefix; /* String to prepend to the path. */ - struct prefix_list *next; /* Next in linked list. */ -}; - -struct path_prefix -{ - struct prefix_list *plist; /* List of prefixes to try */ - int max_len; /* Max length of a prefix in PLIST */ - const char *name; /* Name of this list (used in config stuff) */ -}; - -extern void find_file_set_debug (bool); -extern char *find_a_file (struct path_prefix *, const char *, int); -extern void add_prefix (struct path_prefix *, const char *); -extern void add_prefix_begin (struct path_prefix *, const char *); -extern void prefix_from_env (const char *, struct path_prefix *); -extern void prefix_from_string (const char *, struct path_prefix *); - -#endif /* GCC_FILE_FIND_H */ diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/filenames.h b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/filenames.h deleted file mode 100644 index 470c5e0..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/filenames.h +++ /dev/null @@ -1,99 +0,0 @@ -/* Macros for taking apart, interpreting and processing file names. - - These are here because some non-Posix (a.k.a. DOSish) systems have - drive letter brain-damage at the beginning of an absolute file name, - use forward- and back-slash in path names interchangeably, and - some of them have case-insensitive file names. - - Copyright 2000, 2001, 2007, 2010 Free Software Foundation, Inc. - -This file is part of BFD, the Binary File Descriptor library. - -This program is free software; you can redistribute it and/or modify -it under the terms of the GNU General Public License as published by -the Free Software Foundation; either version 2 of the License, or -(at your option) any later version. - -This program is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU General Public License for more details. - -You should have received a copy of the GNU General Public License -along with this program; if not, write to the Free Software -Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ - -#ifndef FILENAMES_H -#define FILENAMES_H - -#include "hashtab.h" /* for hashval_t */ - -#ifdef __cplusplus -extern "C" { -#endif - -#if defined(__MSDOS__) || defined(_WIN32) || defined(__OS2__) || defined (__CYGWIN__) -# ifndef HAVE_DOS_BASED_FILE_SYSTEM -# define HAVE_DOS_BASED_FILE_SYSTEM 1 -# endif -# ifndef HAVE_CASE_INSENSITIVE_FILE_SYSTEM -# define HAVE_CASE_INSENSITIVE_FILE_SYSTEM 1 -# endif -# define HAS_DRIVE_SPEC(f) HAS_DOS_DRIVE_SPEC (f) -# define IS_DIR_SEPARATOR(c) IS_DOS_DIR_SEPARATOR (c) -# define IS_ABSOLUTE_PATH(f) IS_DOS_ABSOLUTE_PATH (f) -#else /* not DOSish */ -# if defined(__APPLE__) -# ifndef HAVE_CASE_INSENSITIVE_FILE_SYSTEM -# define HAVE_CASE_INSENSITIVE_FILE_SYSTEM 1 -# endif -# endif /* __APPLE__ */ -# define HAS_DRIVE_SPEC(f) (0) -# define IS_DIR_SEPARATOR(c) IS_UNIX_DIR_SEPARATOR (c) -# define IS_ABSOLUTE_PATH(f) IS_UNIX_ABSOLUTE_PATH (f) -#endif - -#define IS_DIR_SEPARATOR_1(dos_based, c) \ - (((c) == '/') \ - || (((c) == '\\') && (dos_based))) - -#define HAS_DRIVE_SPEC_1(dos_based, f) \ - ((f)[0] && ((f)[1] == ':') && (dos_based)) - -/* Remove the drive spec from F, assuming HAS_DRIVE_SPEC (f). - The result is a pointer to the remainder of F. */ -#define STRIP_DRIVE_SPEC(f) ((f) + 2) - -#define IS_DOS_DIR_SEPARATOR(c) IS_DIR_SEPARATOR_1 (1, c) -#define IS_DOS_ABSOLUTE_PATH(f) IS_ABSOLUTE_PATH_1 (1, f) -#define HAS_DOS_DRIVE_SPEC(f) HAS_DRIVE_SPEC_1 (1, f) - -#define IS_UNIX_DIR_SEPARATOR(c) IS_DIR_SEPARATOR_1 (0, c) -#define IS_UNIX_ABSOLUTE_PATH(f) IS_ABSOLUTE_PATH_1 (0, f) - -/* Note that when DOS_BASED is true, IS_ABSOLUTE_PATH accepts d:foo as - well, although it is only semi-absolute. This is because the users - of IS_ABSOLUTE_PATH want to know whether to prepend the current - working directory to a file name, which should not be done with a - name like d:foo. */ -#define IS_ABSOLUTE_PATH_1(dos_based, f) \ - (IS_DIR_SEPARATOR_1 (dos_based, (f)[0]) \ - || HAS_DRIVE_SPEC_1 (dos_based, f)) - -extern int filename_cmp (const char *s1, const char *s2); -#define FILENAME_CMP(s1, s2) filename_cmp(s1, s2) - -extern int filename_ncmp (const char *s1, const char *s2, - size_t n); - -extern hashval_t filename_hash (const void *s); - -extern int filename_eq (const void *s1, const void *s2); - -extern int canonical_filename_eq (const char *a, const char *b); - -#ifdef __cplusplus -} -#endif - -#endif /* FILENAMES_H */ diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/fixed-value.h b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/fixed-value.h deleted file mode 100644 index bf30c1a..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/fixed-value.h +++ /dev/null @@ -1,116 +0,0 @@ -/* Fixed-point arithmetic support. - Copyright (C) 2006-2015 Free Software Foundation, Inc. - -This file is part of GCC. - -GCC is free software; you can redistribute it and/or modify it under -the terms of the GNU General Public License as published by the Free -Software Foundation; either version 3, or (at your option) any later -version. - -GCC is distributed in the hope that it will be useful, but WITHOUT ANY -WARRANTY; without even the implied warranty of MERCHANTABILITY or -FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -for more details. - -You should have received a copy of the GNU General Public License -along with GCC; see the file COPYING3. If not see -. */ - -#ifndef GCC_FIXED_VALUE_H -#define GCC_FIXED_VALUE_H - -#include "machmode.h" -#include "real.h" -#include "double-int.h" - -struct GTY(()) fixed_value -{ - double_int data; /* Store data up to 2 wide integers. */ - machine_mode mode; /* Use machine mode to know IBIT and FBIT. */ -}; - -#define FIXED_VALUE_TYPE struct fixed_value - -#define MAX_FCONST0 18 /* For storing 18 fixed-point zeros per - fract, ufract, accum, and uaccum modes . */ -#define MAX_FCONST1 8 /* For storing 8 fixed-point ones per accum - and uaccum modes. */ -/* Constant fixed-point values 0 and 1. */ -extern FIXED_VALUE_TYPE fconst0[MAX_FCONST0]; -extern FIXED_VALUE_TYPE fconst1[MAX_FCONST1]; - -/* Macros to access fconst0 and fconst1 via machine modes. */ -#define FCONST0(mode) fconst0[mode - QQmode] -#define FCONST1(mode) fconst1[mode - HAmode] - -/* Return a CONST_FIXED with value R and mode M. */ -#define CONST_FIXED_FROM_FIXED_VALUE(r, m) \ - const_fixed_from_fixed_value (r, m) -extern rtx const_fixed_from_fixed_value (FIXED_VALUE_TYPE, machine_mode); - -/* Construct a FIXED_VALUE from a bit payload and machine mode MODE. - The bits in PAYLOAD are sign-extended/zero-extended according to MODE. */ -extern FIXED_VALUE_TYPE fixed_from_double_int (double_int, - machine_mode); - -/* Return a CONST_FIXED from a bit payload and machine mode MODE. - The bits in PAYLOAD are sign-extended/zero-extended according to MODE. */ -static inline rtx -const_fixed_from_double_int (double_int payload, - machine_mode mode) -{ - return - const_fixed_from_fixed_value (fixed_from_double_int (payload, mode), - mode); -} - -/* Initialize from a decimal or hexadecimal string. */ -extern void fixed_from_string (FIXED_VALUE_TYPE *, const char *, - machine_mode); - -/* In tree.c: wrap up a FIXED_VALUE_TYPE in a tree node. */ -extern tree build_fixed (tree, FIXED_VALUE_TYPE); - -/* Extend or truncate to a new mode. */ -extern bool fixed_convert (FIXED_VALUE_TYPE *, machine_mode, - const FIXED_VALUE_TYPE *, bool); - -/* Convert to a fixed-point mode from an integer. */ -extern bool fixed_convert_from_int (FIXED_VALUE_TYPE *, machine_mode, - double_int, bool, bool); - -/* Convert to a fixed-point mode from a real. */ -extern bool fixed_convert_from_real (FIXED_VALUE_TYPE *, machine_mode, - const REAL_VALUE_TYPE *, bool); - -/* Convert to a real mode from a fixed-point. */ -extern void real_convert_from_fixed (REAL_VALUE_TYPE *, machine_mode, - const FIXED_VALUE_TYPE *); - -/* Compare two fixed-point objects for bitwise identity. */ -extern bool fixed_identical (const FIXED_VALUE_TYPE *, const FIXED_VALUE_TYPE *); - -/* Calculate a hash value. */ -extern unsigned int fixed_hash (const FIXED_VALUE_TYPE *); - -#define FIXED_VALUES_IDENTICAL(x, y) fixed_identical (&(x), &(y)) - -/* Determine whether a fixed-point value X is negative. */ -#define FIXED_VALUE_NEGATIVE(x) fixed_isneg (&(x)) - -/* Render F as a decimal floating point constant. */ -extern void fixed_to_decimal (char *str, const FIXED_VALUE_TYPE *, size_t); - -/* Binary or unary arithmetic on tree_code. */ -extern bool fixed_arithmetic (FIXED_VALUE_TYPE *, int, const FIXED_VALUE_TYPE *, - const FIXED_VALUE_TYPE *, bool); - -/* Compare fixed-point values by tree_code. */ -extern bool fixed_compare (int, const FIXED_VALUE_TYPE *, - const FIXED_VALUE_TYPE *); - -/* Determine whether a fixed-point value X is negative. */ -extern bool fixed_isneg (const FIXED_VALUE_TYPE *); - -#endif /* GCC_FIXED_VALUE_H */ diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/flag-types.h b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/flag-types.h deleted file mode 100644 index bfdce44..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/flag-types.h +++ /dev/null @@ -1,301 +0,0 @@ -/* Compilation switch flag type definitions for GCC. - Copyright (C) 1987-2015 Free Software Foundation, Inc. - -This file is part of GCC. - -GCC is free software; you can redistribute it and/or modify it under -the terms of the GNU General Public License as published by the Free -Software Foundation; either version 3, or (at your option) any later -version. - -GCC is distributed in the hope that it will be useful, but WITHOUT ANY -WARRANTY; without even the implied warranty of MERCHANTABILITY or -FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -for more details. - -You should have received a copy of the GNU General Public License -along with GCC; see the file COPYING3. If not see -. */ - -#ifndef GCC_FLAG_TYPES_H -#define GCC_FLAG_TYPES_H - -enum debug_info_type -{ - NO_DEBUG, /* Write no debug info. */ - DBX_DEBUG, /* Write BSD .stabs for DBX (using dbxout.c). */ - SDB_DEBUG, /* Write COFF for (old) SDB (using sdbout.c). */ - DWARF2_DEBUG, /* Write Dwarf v2 debug info (using dwarf2out.c). */ - XCOFF_DEBUG, /* Write IBM/Xcoff debug info (using dbxout.c). */ - VMS_DEBUG, /* Write VMS debug info (using vmsdbgout.c). */ - VMS_AND_DWARF2_DEBUG /* Write VMS debug info (using vmsdbgout.c). - and DWARF v2 debug info (using dwarf2out.c). */ -}; - -enum debug_info_levels -{ - DINFO_LEVEL_NONE, /* Write no debugging info. */ - DINFO_LEVEL_TERSE, /* Write minimal info to support tracebacks only. */ - DINFO_LEVEL_NORMAL, /* Write info for all declarations (and line table). */ - DINFO_LEVEL_VERBOSE /* Write normal info plus #define/#undef info. */ -}; - -/* A major contribution to object and executable size is debug - information size. A major contribution to debug information - size is struct descriptions replicated in several object files. - The following function determines whether or not debug information - should be generated for a given struct. The indirect parameter - indicates that the struct is being handled indirectly, via - a pointer. See opts.c for the implementation. */ - -enum debug_info_usage -{ - DINFO_USAGE_DFN, /* A struct definition. */ - DINFO_USAGE_DIR_USE, /* A direct use, such as the type of a variable. */ - DINFO_USAGE_IND_USE, /* An indirect use, such as through a pointer. */ - DINFO_USAGE_NUM_ENUMS /* The number of enumerators. */ -}; - -/* A major contribution to object and executable size is debug - information size. A major contribution to debug information size - is struct descriptions replicated in several object files. The - following flags attempt to reduce this information. The basic - idea is to not emit struct debugging information in the current - compilation unit when that information will be generated by - another compilation unit. - - Debug information for a struct defined in the current source - file should be generated in the object file. Likewise the - debug information for a struct defined in a header should be - generated in the object file of the corresponding source file. - Both of these case are handled when the base name of the file of - the struct definition matches the base name of the source file - of the current compilation unit. This matching emits minimal - struct debugging information. - - The base file name matching rule above will fail to emit debug - information for structs defined in system headers. So a second - category of files includes system headers in addition to files - with matching bases. - - The remaining types of files are library headers and application - headers. We cannot currently distinguish these two types. */ - -enum debug_struct_file -{ - DINFO_STRUCT_FILE_NONE, /* Debug no structs. */ - DINFO_STRUCT_FILE_BASE, /* Debug structs defined in files with the - same base name as the compilation unit. */ - DINFO_STRUCT_FILE_SYS, /* Also debug structs defined in system - header files. */ - DINFO_STRUCT_FILE_ANY /* Debug structs defined in all files. */ -}; - -/* Enumerate visibility settings. This is deliberately ordered from most - to least visibility. */ -#ifndef SYMBOL_VISIBILITY_DEFINED -#define SYMBOL_VISIBILITY_DEFINED -enum symbol_visibility -{ - VISIBILITY_DEFAULT, - VISIBILITY_PROTECTED, - VISIBILITY_HIDDEN, - VISIBILITY_INTERNAL -}; -#endif - -/* Enumerate Objective-c instance variable visibility settings. */ - -enum ivar_visibility -{ - IVAR_VISIBILITY_PRIVATE, - IVAR_VISIBILITY_PROTECTED, - IVAR_VISIBILITY_PUBLIC, - IVAR_VISIBILITY_PACKAGE -}; - -/* The stack reuse level. */ -enum stack_reuse_level -{ - SR_NONE, - SR_NAMED_VARS, - SR_ALL -}; - -/* The algorithm used for the integrated register allocator (IRA). */ -enum ira_algorithm -{ - IRA_ALGORITHM_CB, - IRA_ALGORITHM_PRIORITY -}; - -/* The regions used for the integrated register allocator (IRA). */ -enum ira_region -{ - IRA_REGION_ONE, - IRA_REGION_ALL, - IRA_REGION_MIXED, - /* This value means that there were no options -fira-region on the - command line and that we should choose a value depending on the - used -O option. */ - IRA_REGION_AUTODETECT -}; - -/* The options for excess precision. */ -enum excess_precision -{ - EXCESS_PRECISION_DEFAULT, - EXCESS_PRECISION_FAST, - EXCESS_PRECISION_STANDARD -}; - -/* Type of stack check. */ -enum stack_check_type -{ - /* Do not check the stack. */ - NO_STACK_CHECK = 0, - - /* Check the stack generically, i.e. assume no specific support - from the target configuration files. */ - GENERIC_STACK_CHECK, - - /* Check the stack and rely on the target configuration files to - check the static frame of functions, i.e. use the generic - mechanism only for dynamic stack allocations. */ - STATIC_BUILTIN_STACK_CHECK, - - /* Check the stack and entirely rely on the target configuration - files, i.e. do not use the generic mechanism at all. */ - FULL_BUILTIN_STACK_CHECK -}; - -/* Names for the different levels of -Wstrict-overflow=N. The numeric - values here correspond to N. */ - -enum warn_strict_overflow_code -{ - /* Overflow warning that should be issued with -Wall: a questionable - construct that is easy to avoid even when using macros. Example: - folding (x + CONSTANT > x) to 1. */ - WARN_STRICT_OVERFLOW_ALL = 1, - /* Overflow warning about folding a comparison to a constant because - of undefined signed overflow, other than cases covered by - WARN_STRICT_OVERFLOW_ALL. Example: folding (abs (x) >= 0) to 1 - (this is false when x == INT_MIN). */ - WARN_STRICT_OVERFLOW_CONDITIONAL = 2, - /* Overflow warning about changes to comparisons other than folding - them to a constant. Example: folding (x + 1 > 1) to (x > 0). */ - WARN_STRICT_OVERFLOW_COMPARISON = 3, - /* Overflow warnings not covered by the above cases. Example: - folding ((x * 10) / 5) to (x * 2). */ - WARN_STRICT_OVERFLOW_MISC = 4, - /* Overflow warnings about reducing magnitude of constants in - comparison. Example: folding (x + 2 > y) to (x + 1 >= y). */ - WARN_STRICT_OVERFLOW_MAGNITUDE = 5 -}; - -/* Floating-point contraction mode. */ -enum fp_contract_mode { - FP_CONTRACT_OFF = 0, - FP_CONTRACT_ON = 1, - FP_CONTRACT_FAST = 2 -}; - -/* Vectorizer cost-model. */ -enum vect_cost_model { - VECT_COST_MODEL_UNLIMITED = 0, - VECT_COST_MODEL_CHEAP = 1, - VECT_COST_MODEL_DYNAMIC = 2, - VECT_COST_MODEL_DEFAULT = 3 -}; - - -/* Different instrumentation modes. */ -enum sanitize_code { - /* AddressSanitizer. */ - SANITIZE_ADDRESS = 1 << 0, - SANITIZE_USER_ADDRESS = 1 << 1, - SANITIZE_KERNEL_ADDRESS = 1 << 2, - /* ThreadSanitizer. */ - SANITIZE_THREAD = 1 << 3, - /* LeakSanitizer. */ - SANITIZE_LEAK = 1 << 4, - /* UndefinedBehaviorSanitizer. */ - SANITIZE_SHIFT = 1 << 5, - SANITIZE_DIVIDE = 1 << 6, - SANITIZE_UNREACHABLE = 1 << 7, - SANITIZE_VLA = 1 << 8, - SANITIZE_NULL = 1 << 9, - SANITIZE_RETURN = 1 << 10, - SANITIZE_SI_OVERFLOW = 1 << 11, - SANITIZE_BOOL = 1 << 12, - SANITIZE_ENUM = 1 << 13, - SANITIZE_FLOAT_DIVIDE = 1 << 14, - SANITIZE_FLOAT_CAST = 1 << 15, - SANITIZE_BOUNDS = 1UL << 16, - SANITIZE_ALIGNMENT = 1UL << 17, - SANITIZE_NONNULL_ATTRIBUTE = 1UL << 18, - SANITIZE_RETURNS_NONNULL_ATTRIBUTE = 1UL << 19, - SANITIZE_OBJECT_SIZE = 1UL << 20, - SANITIZE_VPTR = 1UL << 21, - SANITIZE_UNDEFINED = SANITIZE_SHIFT | SANITIZE_DIVIDE | SANITIZE_UNREACHABLE - | SANITIZE_VLA | SANITIZE_NULL | SANITIZE_RETURN - | SANITIZE_SI_OVERFLOW | SANITIZE_BOOL | SANITIZE_ENUM - | SANITIZE_BOUNDS | SANITIZE_ALIGNMENT - | SANITIZE_NONNULL_ATTRIBUTE - | SANITIZE_RETURNS_NONNULL_ATTRIBUTE - | SANITIZE_OBJECT_SIZE | SANITIZE_VPTR, - SANITIZE_NONDEFAULT = SANITIZE_FLOAT_DIVIDE | SANITIZE_FLOAT_CAST -}; - -/* flag_vtable_verify initialization levels. */ -enum vtv_priority { - VTV_NO_PRIORITY = 0, /* i.E. Do NOT do vtable verification. */ - VTV_STANDARD_PRIORITY = 1, - VTV_PREINIT_PRIORITY = 2 -}; - -/* flag_lto_partition initialization values. */ -enum lto_partition_model { - LTO_PARTITION_NONE = 0, - LTO_PARTITION_ONE = 1, - LTO_PARTITION_BALANCED = 2, - LTO_PARTITION_1TO1 = 3, - LTO_PARTITION_MAX = 4 -}; - - -/* gfortran -finit-real= values. */ - -enum gfc_init_local_real -{ - GFC_INIT_REAL_OFF = 0, - GFC_INIT_REAL_ZERO, - GFC_INIT_REAL_NAN, - GFC_INIT_REAL_SNAN, - GFC_INIT_REAL_INF, - GFC_INIT_REAL_NEG_INF -}; - -/* gfortran -fcoarray= values. */ - -enum gfc_fcoarray -{ - GFC_FCOARRAY_NONE = 0, - GFC_FCOARRAY_SINGLE, - GFC_FCOARRAY_LIB -}; - - -/* gfortran -fconvert= values; used for unformatted I/O. - Keep in sync with GFC_CONVERT_* in gcc/fortran/libgfortran.h. */ -enum gfc_convert -{ - GFC_FLAG_CONVERT_NATIVE = 0, - GFC_FLAG_CONVERT_SWAP, - GFC_FLAG_CONVERT_BIG, - GFC_FLAG_CONVERT_LITTLE -}; - - -#endif /* ! GCC_FLAG_TYPES_H */ diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/flags.h b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/flags.h deleted file mode 100644 index 22abddc..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/flags.h +++ /dev/null @@ -1,101 +0,0 @@ -/* Compilation switch flag definitions for GCC. - Copyright (C) 1987-2015 Free Software Foundation, Inc. - -This file is part of GCC. - -GCC is free software; you can redistribute it and/or modify it under -the terms of the GNU General Public License as published by the Free -Software Foundation; either version 3, or (at your option) any later -version. - -GCC is distributed in the hope that it will be useful, but WITHOUT ANY -WARRANTY; without even the implied warranty of MERCHANTABILITY or -FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -for more details. - -You should have received a copy of the GNU General Public License -along with GCC; see the file COPYING3. If not see -. */ - -#ifndef GCC_FLAGS_H -#define GCC_FLAGS_H - -#include "flag-types.h" -#include "options.h" - -#if !defined(IN_LIBGCC2) && !defined(IN_TARGET_LIBS) && !defined(IN_RTS) - -/* Names of debug_info_type, for error messages. */ -extern const char *const debug_type_names[]; - -extern void strip_off_ending (char *, int); -extern int base_of_path (const char *path, const char **base_out); - -/* Return true iff flags are set as if -ffast-math. */ -extern bool fast_math_flags_set_p (const struct gcc_options *); -extern bool fast_math_flags_struct_set_p (struct cl_optimization *); - - -/* Now the symbols that are set with `-f' switches. */ - -/* True if printing into -fdump-final-insns= dump. */ - -extern bool final_insns_dump_p; - - -/* Other basic status info about current function. */ - -/* Target-dependent global state. */ -struct target_flag_state { - /* Values of the -falign-* flags: how much to align labels in code. - 0 means `use default', 1 means `don't align'. - For each variable, there is an _log variant which is the power - of two not less than the variable, for .align output. */ - int x_align_loops_log; - int x_align_loops_max_skip; - int x_align_jumps_log; - int x_align_jumps_max_skip; - int x_align_labels_log; - int x_align_labels_max_skip; - int x_align_functions_log; - - /* The excess precision currently in effect. */ - enum excess_precision x_flag_excess_precision; -}; - -extern struct target_flag_state default_target_flag_state; -#if SWITCHABLE_TARGET -extern struct target_flag_state *this_target_flag_state; -#else -#define this_target_flag_state (&default_target_flag_state) -#endif - -#define align_loops_log \ - (this_target_flag_state->x_align_loops_log) -#define align_loops_max_skip \ - (this_target_flag_state->x_align_loops_max_skip) -#define align_jumps_log \ - (this_target_flag_state->x_align_jumps_log) -#define align_jumps_max_skip \ - (this_target_flag_state->x_align_jumps_max_skip) -#define align_labels_log \ - (this_target_flag_state->x_align_labels_log) -#define align_labels_max_skip \ - (this_target_flag_state->x_align_labels_max_skip) -#define align_functions_log \ - (this_target_flag_state->x_align_functions_log) -#define flag_excess_precision \ - (this_target_flag_state->x_flag_excess_precision) - -/* Returns TRUE if generated code should match ABI version N or - greater is in use. */ - -#define abi_version_at_least(N) \ - (flag_abi_version == 0 || flag_abi_version >= (N)) - -/* Whether to emit an overflow warning whose code is C. */ -#define issue_strict_overflow_warning(c) (warn_strict_overflow >= (int) (c)) - -#endif - -#endif /* ! GCC_FLAGS_H */ diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/fold-const.h b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/fold-const.h deleted file mode 100644 index a6d0cea..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/fold-const.h +++ /dev/null @@ -1,192 +0,0 @@ -/* Fold a constant sub-tree into a single node for C-compiler - Copyright (C) 1987-2015 Free Software Foundation, Inc. - -This file is part of GCC. - -GCC is free software; you can redistribute it and/or modify it under -the terms of the GNU General Public License as published by the Free -Software Foundation; either version 3, or (at your option) any later -version. - -GCC is distributed in the hope that it will be useful, but WITHOUT ANY -WARRANTY; without even the implied warranty of MERCHANTABILITY or -FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -for more details. - -You should have received a copy of the GNU General Public License -along with GCC; see the file COPYING3. If not see -. */ - -#ifndef GCC_FOLD_CONST_H -#define GCC_FOLD_CONST_H - -/* Non-zero if we are folding constants inside an initializer; zero - otherwise. */ -extern int folding_initializer; - -/* Convert between trees and native memory representation. */ -extern int native_encode_expr (const_tree, unsigned char *, int, int off = -1); -extern tree native_interpret_expr (tree, const unsigned char *, int); - -/* Fold constants as much as possible in an expression. - Returns the simplified expression. - Acts only on the top level of the expression; - if the argument itself cannot be simplified, its - subexpressions are not changed. */ - -extern tree fold (tree); -#define fold_unary(CODE,T1,T2)\ - fold_unary_loc (UNKNOWN_LOCATION, CODE, T1, T2) -extern tree fold_unary_loc (location_t, enum tree_code, tree, tree); -#define fold_unary_ignore_overflow(CODE,T1,T2)\ - fold_unary_ignore_overflow_loc (UNKNOWN_LOCATION, CODE, T1, T2) -extern tree fold_unary_ignore_overflow_loc (location_t, enum tree_code, tree, tree); -#define fold_binary(CODE,T1,T2,T3)\ - fold_binary_loc (UNKNOWN_LOCATION, CODE, T1, T2, T3) -extern tree fold_binary_loc (location_t, enum tree_code, tree, tree, tree); -#define fold_ternary(CODE,T1,T2,T3,T4)\ - fold_ternary_loc (UNKNOWN_LOCATION, CODE, T1, T2, T3, T4) -extern tree fold_ternary_loc (location_t, enum tree_code, tree, tree, tree, tree); -#define fold_build1(c,t1,t2)\ - fold_build1_stat_loc (UNKNOWN_LOCATION, c, t1, t2 MEM_STAT_INFO) -#define fold_build1_loc(l,c,t1,t2)\ - fold_build1_stat_loc (l, c, t1, t2 MEM_STAT_INFO) -extern tree fold_build1_stat_loc (location_t, enum tree_code, tree, - tree MEM_STAT_DECL); -#define fold_build2(c,t1,t2,t3)\ - fold_build2_stat_loc (UNKNOWN_LOCATION, c, t1, t2, t3 MEM_STAT_INFO) -#define fold_build2_loc(l,c,t1,t2,t3)\ - fold_build2_stat_loc (l, c, t1, t2, t3 MEM_STAT_INFO) -extern tree fold_build2_stat_loc (location_t, enum tree_code, tree, tree, - tree MEM_STAT_DECL); -#define fold_build3(c,t1,t2,t3,t4)\ - fold_build3_stat_loc (UNKNOWN_LOCATION, c, t1, t2, t3, t4 MEM_STAT_INFO) -#define fold_build3_loc(l,c,t1,t2,t3,t4)\ - fold_build3_stat_loc (l, c, t1, t2, t3, t4 MEM_STAT_INFO) -extern tree fold_build3_stat_loc (location_t, enum tree_code, tree, tree, tree, - tree MEM_STAT_DECL); -extern tree fold_build1_initializer_loc (location_t, enum tree_code, tree, tree); -extern tree fold_build2_initializer_loc (location_t, enum tree_code, tree, tree, tree); -#define fold_build_call_array(T1,T2,N,T4)\ - fold_build_call_array_loc (UNKNOWN_LOCATION, T1, T2, N, T4) -extern tree fold_build_call_array_loc (location_t, tree, tree, int, tree *); -#define fold_build_call_array_initializer(T1,T2,N,T4)\ - fold_build_call_array_initializer_loc (UNKNOWN_LOCATION, T1, T2, N, T4) -extern tree fold_build_call_array_initializer_loc (location_t, tree, tree, int, tree *); -extern bool fold_convertible_p (const_tree, const_tree); -#define fold_convert(T1,T2)\ - fold_convert_loc (UNKNOWN_LOCATION, T1, T2) -extern tree fold_convert_loc (location_t, tree, tree); -extern tree fold_single_bit_test (location_t, enum tree_code, tree, tree, tree); -extern tree fold_ignored_result (tree); -extern tree fold_abs_const (tree, tree); -extern tree fold_indirect_ref_1 (location_t, tree, tree); -extern void fold_defer_overflow_warnings (void); -extern void fold_undefer_overflow_warnings (bool, const_gimple, int); -extern void fold_undefer_and_ignore_overflow_warnings (void); -extern bool fold_deferring_overflow_warnings_p (void); -extern int operand_equal_p (const_tree, const_tree, unsigned int); -extern int multiple_of_p (tree, const_tree, const_tree); -#define omit_one_operand(T1,T2,T3)\ - omit_one_operand_loc (UNKNOWN_LOCATION, T1, T2, T3) -extern tree omit_one_operand_loc (location_t, tree, tree, tree); -#define omit_two_operands(T1,T2,T3,T4)\ - omit_two_operands_loc (UNKNOWN_LOCATION, T1, T2, T3, T4) -extern tree omit_two_operands_loc (location_t, tree, tree, tree, tree); -#define invert_truthvalue(T)\ - invert_truthvalue_loc (UNKNOWN_LOCATION, T) -extern tree invert_truthvalue_loc (location_t, tree); -extern tree fold_unary_to_constant (enum tree_code, tree, tree); -extern tree fold_binary_to_constant (enum tree_code, tree, tree, tree); -extern tree fold_read_from_constant_string (tree); -extern tree int_const_binop (enum tree_code, const_tree, const_tree); -#define build_fold_addr_expr(T)\ - build_fold_addr_expr_loc (UNKNOWN_LOCATION, (T)) -extern tree build_fold_addr_expr_loc (location_t, tree); -#define build_fold_addr_expr_with_type(T,TYPE)\ - build_fold_addr_expr_with_type_loc (UNKNOWN_LOCATION, (T), TYPE) -extern tree build_fold_addr_expr_with_type_loc (location_t, tree, tree); -extern tree fold_build_cleanup_point_expr (tree type, tree expr); -extern tree fold_strip_sign_ops (tree); -#define build_fold_indirect_ref(T)\ - build_fold_indirect_ref_loc (UNKNOWN_LOCATION, T) -extern tree build_fold_indirect_ref_loc (location_t, tree); -#define fold_indirect_ref(T)\ - fold_indirect_ref_loc (UNKNOWN_LOCATION, T) -extern tree fold_indirect_ref_loc (location_t, tree); -extern tree build_simple_mem_ref_loc (location_t, tree); -#define build_simple_mem_ref(T)\ - build_simple_mem_ref_loc (UNKNOWN_LOCATION, T) -extern offset_int mem_ref_offset (const_tree); -extern tree build_invariant_address (tree, tree, HOST_WIDE_INT); -extern tree constant_boolean_node (bool, tree); -extern tree div_if_zero_remainder (const_tree, const_tree); - -extern bool tree_swap_operands_p (const_tree, const_tree, bool); -extern enum tree_code swap_tree_comparison (enum tree_code); - -extern bool ptr_difference_const (tree, tree, HOST_WIDE_INT *); -extern enum tree_code invert_tree_comparison (enum tree_code, bool); - -extern bool tree_unary_nonzero_warnv_p (enum tree_code, tree, tree, bool *); -extern bool tree_binary_nonzero_warnv_p (enum tree_code, tree, tree, tree op1, - bool *); -extern bool tree_single_nonzero_warnv_p (tree, bool *); -extern bool tree_unary_nonnegative_warnv_p (enum tree_code, tree, tree, bool *); -extern bool tree_binary_nonnegative_warnv_p (enum tree_code, tree, tree, tree, - bool *); -extern bool tree_single_nonnegative_warnv_p (tree t, bool *strict_overflow_p); -extern bool tree_call_nonnegative_warnv_p (tree, tree, tree, tree, bool *); - -extern bool fold_real_zero_addition_p (const_tree, const_tree, int); -extern tree combine_comparisons (location_t, enum tree_code, enum tree_code, - enum tree_code, tree, tree, tree); -extern void debug_fold_checksum (const_tree); -extern bool may_negate_without_overflow_p (const_tree); -#define round_up(T,N) round_up_loc (UNKNOWN_LOCATION, T, N) -extern tree round_up_loc (location_t, tree, unsigned int); -#define round_down(T,N) round_down_loc (UNKNOWN_LOCATION, T, N) -extern tree round_down_loc (location_t, tree, int); -extern tree size_int_kind (HOST_WIDE_INT, enum size_type_kind); -#define size_binop(CODE,T1,T2)\ - size_binop_loc (UNKNOWN_LOCATION, CODE, T1, T2) -extern tree size_binop_loc (location_t, enum tree_code, tree, tree); -#define size_diffop(T1,T2)\ - size_diffop_loc (UNKNOWN_LOCATION, T1, T2) -extern tree size_diffop_loc (location_t, tree, tree); - -/* Return an expr equal to X but certainly not valid as an lvalue. */ -#define non_lvalue(T) non_lvalue_loc (UNKNOWN_LOCATION, T) -extern tree non_lvalue_loc (location_t, tree); - -extern bool tree_expr_nonnegative_p (tree); -extern bool tree_expr_nonnegative_warnv_p (tree, bool *); -extern tree make_range (tree, int *, tree *, tree *, bool *); -extern tree make_range_step (location_t, enum tree_code, tree, tree, tree, - tree *, tree *, int *, bool *); -extern tree build_range_check (location_t, tree, tree, int, tree, tree); -extern bool merge_ranges (int *, tree *, tree *, int, tree, tree, int, - tree, tree); -extern tree sign_bit_p (tree, const_tree); -extern tree exact_inverse (tree, tree); -extern tree const_unop (enum tree_code, tree, tree); -extern tree const_binop (enum tree_code, tree, tree, tree); - -/* Return OFF converted to a pointer offset type suitable as offset for - POINTER_PLUS_EXPR. Use location LOC for this conversion. */ -extern tree convert_to_ptrofftype_loc (location_t loc, tree off); - -#define convert_to_ptrofftype(t) convert_to_ptrofftype_loc (UNKNOWN_LOCATION, t) - -/* Build and fold a POINTER_PLUS_EXPR at LOC offsetting PTR by OFF. */ -extern tree fold_build_pointer_plus_loc (location_t loc, tree ptr, tree off); - -#define fold_build_pointer_plus(p,o) \ - fold_build_pointer_plus_loc (UNKNOWN_LOCATION, p, o) - -/* Build and fold a POINTER_PLUS_EXPR at LOC offsetting PTR by OFF. */ -extern tree fold_build_pointer_plus_hwi_loc (location_t loc, tree ptr, HOST_WIDE_INT off); - -#define fold_build_pointer_plus_hwi(p,o) \ - fold_build_pointer_plus_hwi_loc (UNKNOWN_LOCATION, p, o) -#endif // GCC_FOLD_CONST_H diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/function.h b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/function.h deleted file mode 100644 index b89c5ae..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/function.h +++ /dev/null @@ -1,936 +0,0 @@ -/* Structure for saving state for a nested function. - Copyright (C) 1989-2015 Free Software Foundation, Inc. - -This file is part of GCC. - -GCC is free software; you can redistribute it and/or modify it under -the terms of the GNU General Public License as published by the Free -Software Foundation; either version 3, or (at your option) any later -version. - -GCC is distributed in the hope that it will be useful, but WITHOUT ANY -WARRANTY; without even the implied warranty of MERCHANTABILITY or -FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -for more details. - -You should have received a copy of the GNU General Public License -along with GCC; see the file COPYING3. If not see -. */ - -#ifndef GCC_FUNCTION_H -#define GCC_FUNCTION_H - - -/* Stack of pending (incomplete) sequences saved by `start_sequence'. - Each element describes one pending sequence. - The main insn-chain is saved in the last element of the chain, - unless the chain is empty. */ - -struct GTY(()) sequence_stack { - /* First and last insns in the chain of the saved sequence. */ - rtx_insn *first; - rtx_insn *last; - struct sequence_stack *next; -}; - -struct GTY(()) emit_status { - /* This is reset to LAST_VIRTUAL_REGISTER + 1 at the start of each function. - After rtl generation, it is 1 plus the largest register number used. */ - int x_reg_rtx_no; - - /* Lowest label number in current function. */ - int x_first_label_num; - - /* The ends of the doubly-linked chain of rtl for the current function. - Both are reset to null at the start of rtl generation for the function. - - start_sequence saves both of these on `sequence_stack' and then starts - a new, nested sequence of insns. */ - rtx_insn *x_first_insn; - rtx_insn *x_last_insn; - - /* Stack of pending (incomplete) sequences saved by `start_sequence'. - Each element describes one pending sequence. - The main insn-chain is saved in the last element of the chain, - unless the chain is empty. */ - struct sequence_stack *sequence_stack; - - /* INSN_UID for next insn emitted. - Reset to 1 for each function compiled. */ - int x_cur_insn_uid; - - /* INSN_UID for next debug insn emitted. Only used if - --param min-nondebug-insn-uid= is given with nonzero value. */ - int x_cur_debug_insn_uid; - - /* The length of the regno_pointer_align, regno_decl, and x_regno_reg_rtx - vectors. Since these vectors are needed during the expansion phase when - the total number of registers in the function is not yet known, the - vectors are copied and made bigger when necessary. */ - int regno_pointer_align_length; - - /* Indexed by pseudo register number, if nonzero gives the known alignment - for that pseudo (if REG_POINTER is set in x_regno_reg_rtx). - Allocated in parallel with x_regno_reg_rtx. */ - unsigned char * GTY((skip)) regno_pointer_align; -}; - - -/* Indexed by register number, gives an rtx for that register (and only - that register). For pseudo registers, it is the unique rtx for - that pseudo. For hard registers, it is an rtx of the mode specified - by reg_raw_mode. - - FIXME: We could put it into emit_status struct, but gengtype is not - able to deal with length attribute nested in top level structures. */ - -extern GTY ((length ("crtl->emit.x_reg_rtx_no"))) rtx * regno_reg_rtx; - -/* For backward compatibility... eventually these should all go away. */ -#define reg_rtx_no (crtl->emit.x_reg_rtx_no) -#define seq_stack (crtl->emit.sequence_stack) - -#define REGNO_POINTER_ALIGN(REGNO) (crtl->emit.regno_pointer_align[REGNO]) - -struct GTY(()) expr_status { - /* Number of units that we should eventually pop off the stack. - These are the arguments to function calls that have already returned. */ - int x_pending_stack_adjust; - - /* Under some ABIs, it is the caller's responsibility to pop arguments - pushed for function calls. A naive implementation would simply pop - the arguments immediately after each call. However, if several - function calls are made in a row, it is typically cheaper to pop - all the arguments after all of the calls are complete since a - single pop instruction can be used. Therefore, GCC attempts to - defer popping the arguments until absolutely necessary. (For - example, at the end of a conditional, the arguments must be popped, - since code outside the conditional won't know whether or not the - arguments need to be popped.) - - When INHIBIT_DEFER_POP is nonzero, however, the compiler does not - attempt to defer pops. Instead, the stack is popped immediately - after each call. Rather then setting this variable directly, use - NO_DEFER_POP and OK_DEFER_POP. */ - int x_inhibit_defer_pop; - - /* If PREFERRED_STACK_BOUNDARY and PUSH_ROUNDING are defined, the stack - boundary can be momentarily unaligned while pushing the arguments. - Record the delta since last aligned boundary here in order to get - stack alignment in the nested function calls working right. */ - int x_stack_pointer_delta; - - /* Nonzero means __builtin_saveregs has already been done in this function. - The value is the pseudoreg containing the value __builtin_saveregs - returned. */ - rtx x_saveregs_value; - - /* Similarly for __builtin_apply_args. */ - rtx x_apply_args_value; - - /* List of labels that must never be deleted. */ - rtx_insn_list *x_forced_labels; -}; - -typedef struct call_site_record_d *call_site_record; - -/* RTL representation of exception handling. */ -struct GTY(()) rtl_eh { - rtx ehr_stackadj; - rtx ehr_handler; - rtx_code_label *ehr_label; - - rtx sjlj_fc; - rtx_insn *sjlj_exit_after; - - vec *action_record_data; - - vec *call_site_record_v[2]; -}; - -#define pending_stack_adjust (crtl->expr.x_pending_stack_adjust) -#define inhibit_defer_pop (crtl->expr.x_inhibit_defer_pop) -#define saveregs_value (crtl->expr.x_saveregs_value) -#define apply_args_value (crtl->expr.x_apply_args_value) -#define forced_labels (crtl->expr.x_forced_labels) -#define stack_pointer_delta (crtl->expr.x_stack_pointer_delta) - -struct gimple_df; -struct temp_slot; -typedef struct temp_slot *temp_slot_p; -struct call_site_record_d; -struct dw_fde_node; - -class ipa_opt_pass_d; -typedef ipa_opt_pass_d *ipa_opt_pass; - - -struct GTY(()) varasm_status { - /* If we're using a per-function constant pool, this is it. */ - struct rtx_constant_pool *pool; - - /* Number of tree-constants deferred during the expansion of this - function. */ - unsigned int deferred_constants; -}; - -/* Information mainlined about RTL representation of incoming arguments. */ -struct GTY(()) incoming_args { - /* Number of bytes of args popped by function being compiled on its return. - Zero if no bytes are to be popped. - May affect compilation of return insn or of function epilogue. */ - int pops_args; - - /* If function's args have a fixed size, this is that size, in bytes. - Otherwise, it is -1. - May affect compilation of return insn or of function epilogue. */ - int size; - - /* # bytes the prologue should push and pretend that the caller pushed them. - The prologue must do this, but only if parms can be passed in - registers. */ - int pretend_args_size; - - /* This is the offset from the arg pointer to the place where the first - anonymous arg can be found, if there is one. */ - rtx arg_offset_rtx; - - /* Quantities of various kinds of registers - used for the current function's args. */ - CUMULATIVE_ARGS info; - - /* The arg pointer hard register, or the pseudo into which it was copied. */ - rtx internal_arg_pointer; -}; - -/* Data for function partitioning. */ -struct GTY(()) function_subsections { - /* Assembly labels for the hot and cold text sections, to - be used by debugger functions for determining the size of text - sections. */ - - const char *hot_section_label; - const char *cold_section_label; - const char *hot_section_end_label; - const char *cold_section_end_label; -}; - -/* Describe an empty area of space in the stack frame. These can be chained - into a list; this is used to keep track of space wasted for alignment - reasons. */ -struct GTY(()) frame_space -{ - struct frame_space *next; - - HOST_WIDE_INT start; - HOST_WIDE_INT length; -}; - -/* Datastructures maintained for currently processed function in RTL form. */ -struct GTY(()) rtl_data { - struct expr_status expr; - struct emit_status emit; - struct varasm_status varasm; - struct incoming_args args; - struct function_subsections subsections; - struct rtl_eh eh; - - /* For function.c */ - - /* # of bytes of outgoing arguments. If ACCUMULATE_OUTGOING_ARGS is - defined, the needed space is pushed by the prologue. */ - int outgoing_args_size; - - /* If nonzero, an RTL expression for the location at which the current - function returns its result. If the current function returns its - result in a register, current_function_return_rtx will always be - the hard register containing the result. */ - rtx return_rtx; - /* If nonxero, an RTL expression for the lcoation at which the current - function returns bounds for its result. */ - rtx return_bnd; - - /* Vector of initial-value pairs. Each pair consists of a pseudo - register of approprite mode that stores the initial value a hard - register REGNO, and that hard register itself. */ - /* ??? This could be a VEC but there is currently no way to define an - opaque VEC type. */ - struct initial_value_struct *hard_reg_initial_vals; - - /* A variable living at the top of the frame that holds a known value. - Used for detecting stack clobbers. */ - tree stack_protect_guard; - - /* List (chain of INSN_LIST) of labels heading the current handlers for - nonlocal gotos. */ - rtx_insn_list *x_nonlocal_goto_handler_labels; - - /* Label that will go on function epilogue. - Jumping to this label serves as a "return" instruction - on machines which require execution of the epilogue on all returns. */ - rtx_code_label *x_return_label; - - /* Label that will go on the end of function epilogue. - Jumping to this label serves as a "naked return" instruction - on machines which require execution of the epilogue on all returns. */ - rtx_code_label *x_naked_return_label; - - /* List (chain of EXPR_LISTs) of all stack slots in this function. - Made for the sake of unshare_all_rtl. */ - rtx_expr_list *x_stack_slot_list; - - /* List of empty areas in the stack frame. */ - struct frame_space *frame_space_list; - - /* Place after which to insert the tail_recursion_label if we need one. */ - rtx_note *x_stack_check_probe_note; - - /* Location at which to save the argument pointer if it will need to be - referenced. There are two cases where this is done: if nonlocal gotos - exist, or if vars stored at an offset from the argument pointer will be - needed by inner routines. */ - rtx x_arg_pointer_save_area; - - /* Dynamic Realign Argument Pointer used for realigning stack. */ - rtx drap_reg; - - /* Offset to end of allocated area of stack frame. - If stack grows down, this is the address of the last stack slot allocated. - If stack grows up, this is the address for the next slot. */ - HOST_WIDE_INT x_frame_offset; - - /* Insn after which register parms and SAVE_EXPRs are born, if nonopt. */ - rtx_insn *x_parm_birth_insn; - - /* List of all used temporaries allocated, by level. */ - vec *x_used_temp_slots; - - /* List of available temp slots. */ - struct temp_slot *x_avail_temp_slots; - - /* Current nesting level for temporaries. */ - int x_temp_slot_level; - - /* The largest alignment needed on the stack, including requirement - for outgoing stack alignment. */ - unsigned int stack_alignment_needed; - - /* Preferred alignment of the end of stack frame, which is preferred - to call other functions. */ - unsigned int preferred_stack_boundary; - - /* The minimum alignment of parameter stack. */ - unsigned int parm_stack_boundary; - - /* The largest alignment of slot allocated on the stack. */ - unsigned int max_used_stack_slot_alignment; - - /* The stack alignment estimated before reload, with consideration of - following factors: - 1. Alignment of local stack variables (max_used_stack_slot_alignment) - 2. Alignment requirement to call other functions - (preferred_stack_boundary) - 3. Alignment of non-local stack variables but might be spilled in - local stack. */ - unsigned int stack_alignment_estimated; - - /* For reorg. */ - - /* Nonzero if function being compiled called builtin_return_addr or - builtin_frame_address with nonzero count. */ - bool accesses_prior_frames; - - /* Nonzero if the function calls __builtin_eh_return. */ - bool calls_eh_return; - - /* Nonzero if function saves all registers, e.g. if it has a nonlocal - label that can reach the exit block via non-exceptional paths. */ - bool saves_all_registers; - - /* Nonzero if function being compiled has nonlocal gotos to parent - function. */ - bool has_nonlocal_goto; - - /* Nonzero if function being compiled has an asm statement. */ - bool has_asm_statement; - - /* This bit is used by the exception handling logic. It is set if all - calls (if any) are sibling calls. Such functions do not have to - have EH tables generated, as they cannot throw. A call to such a - function, however, should be treated as throwing if any of its callees - can throw. */ - bool all_throwers_are_sibcalls; - - /* Nonzero if stack limit checking should be enabled in the current - function. */ - bool limit_stack; - - /* Nonzero if profiling code should be generated. */ - bool profile; - - /* Nonzero if the current function uses the constant pool. */ - bool uses_const_pool; - - /* Nonzero if the current function uses pic_offset_table_rtx. */ - bool uses_pic_offset_table; - - /* Nonzero if the current function needs an lsda for exception handling. */ - bool uses_eh_lsda; - - /* Set when the tail call has been produced. */ - bool tail_call_emit; - - /* Nonzero if code to initialize arg_pointer_save_area has been emitted. */ - bool arg_pointer_save_area_init; - - /* Nonzero if current function must be given a frame pointer. - Set in reload1.c or lra-eliminations.c if anything is allocated - on the stack there. */ - bool frame_pointer_needed; - - /* When set, expand should optimize for speed. */ - bool maybe_hot_insn_p; - - /* Nonzero if function stack realignment is needed. This flag may be - set twice: before and after reload. It is set before reload wrt - stack alignment estimation before reload. It will be changed after - reload if by then criteria of stack realignment is different. - The value set after reload is the accurate one and is finalized. */ - bool stack_realign_needed; - - /* Nonzero if function stack realignment is tried. This flag is set - only once before reload. It affects register elimination. This - is used to generate DWARF debug info for stack variables. */ - bool stack_realign_tried; - - /* Nonzero if function being compiled needs dynamic realigned - argument pointer (drap) if stack needs realigning. */ - bool need_drap; - - /* Nonzero if function stack realignment estimation is done, namely - stack_realign_needed flag has been set before reload wrt estimated - stack alignment info. */ - bool stack_realign_processed; - - /* Nonzero if function stack realignment has been finalized, namely - stack_realign_needed flag has been set and finalized after reload. */ - bool stack_realign_finalized; - - /* True if dbr_schedule has already been called for this function. */ - bool dbr_scheduled_p; - - /* True if current function can not throw. Unlike - TREE_NOTHROW (current_function_decl) it is set even for overwritable - function where currently compiled version of it is nothrow. */ - bool nothrow; - - /* True if we performed shrink-wrapping for the current function. */ - bool shrink_wrapped; - - /* Nonzero if function being compiled doesn't modify the stack pointer - (ignoring the prologue and epilogue). This is only valid after - pass_stack_ptr_mod has run. */ - bool sp_is_unchanging; - - /* Nonzero if function being compiled doesn't contain any calls - (ignoring the prologue and epilogue). This is set prior to - local register allocation and is valid for the remaining - compiler passes. */ - bool is_leaf; - - /* Nonzero if the function being compiled is a leaf function which only - uses leaf registers. This is valid after reload (specifically after - sched2) and is useful only if the port defines LEAF_REGISTERS. */ - bool uses_only_leaf_regs; - - /* Nonzero if the function being compiled has undergone hot/cold partitioning - (under flag_reorder_blocks_and_partition) and has at least one cold - block. */ - bool has_bb_partition; - - /* Nonzero if the function being compiled has completed the bb reordering - pass. */ - bool bb_reorder_complete; - - /* Like regs_ever_live, but 1 if a reg is set or clobbered from an - asm. Unlike regs_ever_live, elements of this array corresponding - to eliminable regs (like the frame pointer) are set if an asm - sets them. */ - HARD_REG_SET asm_clobbers; -}; - -#define return_label (crtl->x_return_label) -#define naked_return_label (crtl->x_naked_return_label) -#define stack_slot_list (crtl->x_stack_slot_list) -#define parm_birth_insn (crtl->x_parm_birth_insn) -#define frame_offset (crtl->x_frame_offset) -#define stack_check_probe_note (crtl->x_stack_check_probe_note) -#define arg_pointer_save_area (crtl->x_arg_pointer_save_area) -#define used_temp_slots (crtl->x_used_temp_slots) -#define avail_temp_slots (crtl->x_avail_temp_slots) -#define temp_slot_level (crtl->x_temp_slot_level) -#define nonlocal_goto_handler_labels (crtl->x_nonlocal_goto_handler_labels) -#define frame_pointer_needed (crtl->frame_pointer_needed) -#define stack_realign_fp (crtl->stack_realign_needed && !crtl->need_drap) -#define stack_realign_drap (crtl->stack_realign_needed && crtl->need_drap) - -extern GTY(()) struct rtl_data x_rtl; - -/* Accessor to RTL datastructures. We keep them statically allocated now since - we never keep multiple functions. For threaded compiler we might however - want to do differently. */ -#define crtl (&x_rtl) - -struct GTY(()) stack_usage -{ - /* # of bytes of static stack space allocated by the function. */ - HOST_WIDE_INT static_stack_size; - - /* # of bytes of dynamic stack space allocated by the function. This is - meaningful only if has_unbounded_dynamic_stack_size is zero. */ - HOST_WIDE_INT dynamic_stack_size; - - /* # of bytes of space pushed onto the stack after the prologue. If - !ACCUMULATE_OUTGOING_ARGS, it contains the outgoing arguments. */ - int pushed_stack_size; - - /* Nonzero if the amount of stack space allocated dynamically cannot - be bounded at compile-time. */ - unsigned int has_unbounded_dynamic_stack_size : 1; -}; - -#define current_function_static_stack_size (cfun->su->static_stack_size) -#define current_function_dynamic_stack_size (cfun->su->dynamic_stack_size) -#define current_function_pushed_stack_size (cfun->su->pushed_stack_size) -#define current_function_has_unbounded_dynamic_stack_size \ - (cfun->su->has_unbounded_dynamic_stack_size) -#define current_function_allocates_dynamic_stack_space \ - (current_function_dynamic_stack_size != 0 \ - || current_function_has_unbounded_dynamic_stack_size) - -/* This structure can save all the important global and static variables - describing the status of the current function. */ - -struct GTY(()) function { - struct eh_status *eh; - - /* The control flow graph for this function. */ - struct control_flow_graph *cfg; - - /* GIMPLE body for this function. */ - gimple_seq gimple_body; - - /* SSA and dataflow information. */ - struct gimple_df *gimple_df; - - /* The loops in this function. */ - struct loops *x_current_loops; - - /* The stack usage of this function. */ - struct stack_usage *su; - - /* Value histograms attached to particular statements. */ - htab_t GTY((skip)) value_histograms; - - /* For function.c. */ - - /* Points to the FUNCTION_DECL of this function. */ - tree decl; - - /* A PARM_DECL that should contain the static chain for this function. - It will be initialized at the beginning of the function. */ - tree static_chain_decl; - - /* An expression that contains the non-local goto save area. The first - word is the saved frame pointer and the second is the saved stack - pointer. */ - tree nonlocal_goto_save_area; - - /* Vector of function local variables, functions, types and constants. */ - vec *local_decls; - - /* In a Cilk function, the VAR_DECL for the frame descriptor. */ - tree cilk_frame_decl; - - /* For md files. */ - - /* tm.h can use this to store whatever it likes. */ - struct machine_function * GTY ((maybe_undef)) machine; - - /* Language-specific code can use this to store whatever it likes. */ - struct language_function * language; - - /* Used types hash table. */ - hash_set *GTY (()) used_types_hash; - - /* Dwarf2 Frame Description Entry, containing the Call Frame Instructions - used for unwinding. Only set when either dwarf2 unwinding or dwarf2 - debugging is enabled. */ - struct dw_fde_node *fde; - - /* Last statement uid. */ - int last_stmt_uid; - - /* Function sequence number for profiling, debugging, etc. */ - int funcdef_no; - - /* Line number of the start of the function for debugging purposes. */ - location_t function_start_locus; - - /* Line number of the end of the function. */ - location_t function_end_locus; - - /* Properties used by the pass manager. */ - unsigned int curr_properties; - unsigned int last_verified; - - /* Non-null if the function does something that would prevent it from - being copied; this applies to both versioning and inlining. Set to - a string describing the reason for failure. */ - const char * GTY((skip)) cannot_be_copied_reason; - - /* Last assigned dependence info clique. */ - unsigned short last_clique; - - /* Collected bit flags. */ - - /* Number of units of general registers that need saving in stdarg - function. What unit is depends on the backend, either it is number - of bytes, or it can be number of registers. */ - unsigned int va_list_gpr_size : 8; - - /* Number of units of floating point registers that need saving in stdarg - function. */ - unsigned int va_list_fpr_size : 8; - - /* Nonzero if function being compiled can call setjmp. */ - unsigned int calls_setjmp : 1; - - /* Nonzero if function being compiled can call alloca, - either as a subroutine or builtin. */ - unsigned int calls_alloca : 1; - - /* This will indicate whether a function is a cilk function */ - unsigned int is_cilk_function : 1; - - /* Nonzero if this is a Cilk function that spawns. */ - unsigned int calls_cilk_spawn : 1; - - /* Nonzero if function being compiled receives nonlocal gotos - from nested functions. */ - unsigned int has_nonlocal_label : 1; - - /* Nonzero if we've set cannot_be_copied_reason. I.e. if - (cannot_be_copied_set && !cannot_be_copied_reason), the function - can in fact be copied. */ - unsigned int cannot_be_copied_set : 1; - - /* Nonzero if current function uses stdarg.h or equivalent. */ - unsigned int stdarg : 1; - - unsigned int after_inlining : 1; - unsigned int always_inline_functions_inlined : 1; - - /* Nonzero if function being compiled can throw synchronous non-call - exceptions. */ - unsigned int can_throw_non_call_exceptions : 1; - - /* Nonzero if instructions that may throw exceptions but don't otherwise - contribute to the execution of the program can be deleted. */ - unsigned int can_delete_dead_exceptions : 1; - - /* Fields below this point are not set for abstract functions; see - allocate_struct_function. */ - - /* Nonzero if function being compiled needs to be given an address - where the value should be stored. */ - unsigned int returns_struct : 1; - - /* Nonzero if function being compiled needs to - return the address of where it has put a structure value. */ - unsigned int returns_pcc_struct : 1; - - /* Nonzero if this function has local DECL_HARD_REGISTER variables. - In this case code motion has to be done more carefully. */ - unsigned int has_local_explicit_reg_vars : 1; - - /* Nonzero if the current function is a thunk, i.e., a lightweight - function implemented by the output_mi_thunk hook) that just - adjusts one of its arguments and forwards to another - function. */ - unsigned int is_thunk : 1; - - /* Nonzero if the current function contains any loops with - loop->force_vectorize set. */ - unsigned int has_force_vectorize_loops : 1; - - /* Nonzero if the current function contains any loops with - nonzero value in loop->simduid. */ - unsigned int has_simduid_loops : 1; - - /* Set when the tail call has been identified. */ - unsigned int tail_call_marked : 1; -}; - -/* Add the decl D to the local_decls list of FUN. */ - -void add_local_decl (struct function *fun, tree d); - -#define FOR_EACH_LOCAL_DECL(FUN, I, D) \ - FOR_EACH_VEC_SAFE_ELT_REVERSE ((FUN)->local_decls, I, D) - -/* If va_list_[gf]pr_size is set to this, it means we don't know how - many units need to be saved. */ -#define VA_LIST_MAX_GPR_SIZE 255 -#define VA_LIST_MAX_FPR_SIZE 255 - -/* The function currently being compiled. */ -extern GTY(()) struct function *cfun; - -/* In order to ensure that cfun is not set directly, we redefine it so - that it is not an lvalue. Rather than assign to cfun, use - push_cfun or set_cfun. */ -#define cfun (cfun + 0) - -/* Nonzero if we've already converted virtual regs to hard regs. */ -extern int virtuals_instantiated; - -/* Nonzero if at least one trampoline has been created. */ -extern int trampolines_created; - -struct GTY((for_user)) types_used_by_vars_entry { - tree type; - tree var_decl; -}; - -struct used_type_hasher : ggc_hasher -{ - static hashval_t hash (types_used_by_vars_entry *); - static bool equal (types_used_by_vars_entry *, types_used_by_vars_entry *); -}; - -/* Hash table making the relationship between a global variable - and the types it references in its initializer. The key of the - entry is a referenced type, and the value is the DECL of the global - variable. types_use_by_vars_do_hash and types_used_by_vars_eq below are - the hash and equality functions to use for this hash table. */ -extern GTY(()) hash_table *types_used_by_vars_hash; - -void types_used_by_var_decl_insert (tree type, tree var_decl); - -/* During parsing of a global variable, this vector contains the types - referenced by the global variable. */ -extern GTY(()) vec *types_used_by_cur_var_decl; - - -/* Return the loop tree of FN. */ - -inline struct loops * -loops_for_fn (struct function *fn) -{ - return fn->x_current_loops; -} - -/* Set the loop tree of FN to LOOPS. */ - -inline void -set_loops_for_fn (struct function *fn, struct loops *loops) -{ - gcc_checking_assert (fn->x_current_loops == NULL || loops == NULL); - fn->x_current_loops = loops; -} - -/* For backward compatibility... eventually these should all go away. */ -#define current_function_funcdef_no (cfun->funcdef_no) - -#define current_loops (cfun->x_current_loops) -#define dom_computed (cfun->cfg->x_dom_computed) -#define n_bbs_in_dom_tree (cfun->cfg->x_n_bbs_in_dom_tree) -#define VALUE_HISTOGRAMS(fun) (fun)->value_histograms - -/* A pointer to a function to create target specific, per-function - data structures. */ -extern struct machine_function * (*init_machine_status) (void); - -enum direction {none, upward, downward}; - -/* Structure to record the size of a sequence of arguments - as the sum of a tree-expression and a constant. This structure is - also used to store offsets from the stack, which might be negative, - so the variable part must be ssizetype, not sizetype. */ - -struct args_size -{ - HOST_WIDE_INT constant; - tree var; -}; - -/* Package up various arg related fields of struct args for - locate_and_pad_parm. */ -struct locate_and_pad_arg_data -{ - /* Size of this argument on the stack, rounded up for any padding it - gets. If REG_PARM_STACK_SPACE is defined, then register parms are - counted here, otherwise they aren't. */ - struct args_size size; - /* Offset of this argument from beginning of stack-args. */ - struct args_size offset; - /* Offset to the start of the stack slot. Different from OFFSET - if this arg pads downward. */ - struct args_size slot_offset; - /* The amount that the stack pointer needs to be adjusted to - force alignment for the next argument. */ - struct args_size alignment_pad; - /* Which way we should pad this arg. */ - enum direction where_pad; - /* slot_offset is at least this aligned. */ - unsigned int boundary; -}; - -/* Add the value of the tree INC to the `struct args_size' TO. */ - -#define ADD_PARM_SIZE(TO, INC) \ -do { \ - tree inc = (INC); \ - if (tree_fits_shwi_p (inc)) \ - (TO).constant += tree_to_shwi (inc); \ - else if ((TO).var == 0) \ - (TO).var = fold_convert (ssizetype, inc); \ - else \ - (TO).var = size_binop (PLUS_EXPR, (TO).var, \ - fold_convert (ssizetype, inc)); \ -} while (0) - -#define SUB_PARM_SIZE(TO, DEC) \ -do { \ - tree dec = (DEC); \ - if (tree_fits_shwi_p (dec)) \ - (TO).constant -= tree_to_shwi (dec); \ - else if ((TO).var == 0) \ - (TO).var = size_binop (MINUS_EXPR, ssize_int (0), \ - fold_convert (ssizetype, dec)); \ - else \ - (TO).var = size_binop (MINUS_EXPR, (TO).var, \ - fold_convert (ssizetype, dec)); \ -} while (0) - -/* Convert the implicit sum in a `struct args_size' into a tree - of type ssizetype. */ -#define ARGS_SIZE_TREE(SIZE) \ -((SIZE).var == 0 ? ssize_int ((SIZE).constant) \ - : size_binop (PLUS_EXPR, fold_convert (ssizetype, (SIZE).var), \ - ssize_int ((SIZE).constant))) - -/* Convert the implicit sum in a `struct args_size' into an rtx. */ -#define ARGS_SIZE_RTX(SIZE) \ -((SIZE).var == 0 ? GEN_INT ((SIZE).constant) \ - : expand_normal (ARGS_SIZE_TREE (SIZE))) - -#define ASLK_REDUCE_ALIGN 1 -#define ASLK_RECORD_PAD 2 - - - -extern void push_function_context (void); -extern void pop_function_context (void); - -/* Save and restore status information for a nested function. */ -extern void free_after_parsing (struct function *); -extern void free_after_compilation (struct function *); - -/* Return size needed for stack frame based on slots so far allocated. - This size counts from zero. It is not rounded to STACK_BOUNDARY; - the caller may have to do that. */ -extern HOST_WIDE_INT get_frame_size (void); - -/* Issue an error message and return TRUE if frame OFFSET overflows in - the signed target pointer arithmetics for function FUNC. Otherwise - return FALSE. */ -extern bool frame_offset_overflow (HOST_WIDE_INT, tree); - -extern rtx assign_stack_local_1 (machine_mode, HOST_WIDE_INT, int, int); -extern rtx assign_stack_local (machine_mode, HOST_WIDE_INT, int); -extern rtx assign_stack_temp_for_type (machine_mode, HOST_WIDE_INT, tree); -extern rtx assign_stack_temp (machine_mode, HOST_WIDE_INT); -extern rtx assign_temp (tree, int, int); -extern void update_temp_slot_address (rtx, rtx); -extern void preserve_temp_slots (rtx); -extern void free_temp_slots (void); -extern void push_temp_slots (void); -extern void pop_temp_slots (void); -extern void init_temp_slots (void); -extern rtx get_hard_reg_initial_reg (rtx); -extern rtx get_hard_reg_initial_val (machine_mode, unsigned int); -extern rtx has_hard_reg_initial_val (machine_mode, unsigned int); - -/* Called from gimple_expand_cfg. */ -extern unsigned int emit_initial_value_sets (void); - -extern bool initial_value_entry (int i, rtx *, rtx *); -extern void instantiate_decl_rtl (rtx x); -extern int aggregate_value_p (const_tree, const_tree); -extern bool use_register_for_decl (const_tree); -extern bool pass_by_reference (CUMULATIVE_ARGS *, machine_mode, - tree, bool); -extern bool reference_callee_copied (CUMULATIVE_ARGS *, machine_mode, - tree, bool); -extern gimple_seq gimplify_parameters (void); -extern void locate_and_pad_parm (machine_mode, tree, int, int, int, - tree, struct args_size *, - struct locate_and_pad_arg_data *); -extern void generate_setjmp_warnings (void); - -/* Identify BLOCKs referenced by more than one NOTE_INSN_BLOCK_{BEG,END}, - and create duplicate blocks. */ -extern void reorder_blocks (void); -extern void clear_block_marks (tree); -extern tree blocks_nreverse (tree); -extern tree block_chainon (tree, tree); - -/* Set BLOCK_NUMBER for all the blocks in FN. */ -extern void number_blocks (tree); - -/* cfun shouldn't be set directly; use one of these functions instead. */ -extern void set_cfun (struct function *new_cfun); -extern void push_cfun (struct function *new_cfun); -extern void pop_cfun (void); - -extern int get_next_funcdef_no (void); -extern int get_last_funcdef_no (void); -extern void allocate_struct_function (tree, bool); -extern void push_struct_function (tree fndecl); -extern void init_dummy_function_start (void); -extern void init_function_start (tree); -extern void stack_protect_epilogue (void); -extern void expand_function_start (tree); -extern void expand_dummy_function_end (void); - -extern void thread_prologue_and_epilogue_insns (void); - -#ifdef RTX_CODE -extern void diddle_return_value (void (*)(rtx, void*), void*); -extern void clobber_return_register (void); -#endif - -extern void do_warn_unused_parameter (tree); -extern void expand_function_end (void); -extern rtx get_arg_pointer_save_area (void); -extern void maybe_copy_prologue_epilogue_insn (rtx, rtx); -extern int prologue_epilogue_contains (const_rtx); -extern void emit_return_into_block (bool simple_p, basic_block bb); -extern void set_return_jump_label (rtx); -extern bool active_insn_between (rtx_insn *head, rtx_insn *tail); -extern vec convert_jumps_to_returns (basic_block last_bb, bool simple_p, - vec unconverted); -extern basic_block emit_return_for_exit (edge exit_fallthru_edge, - bool simple_p); -extern void reposition_prologue_and_epilogue_notes (void); - -/* Returns the name of the current function. */ -extern const char *fndecl_name (tree); -extern const char *function_name (struct function *); -extern const char *current_function_name (void); - -extern void used_types_insert (tree); - -#endif /* GCC_FUNCTION_H */ diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/gcc-plugin.h b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/gcc-plugin.h deleted file mode 100644 index 3dd52ee..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/gcc-plugin.h +++ /dev/null @@ -1,198 +0,0 @@ -/* Public header file for plugins to include. - Copyright (C) 2009-2015 Free Software Foundation, Inc. - -This file is part of GCC. - -GCC is free software; you can redistribute it and/or modify -it under the terms of the GNU General Public License as published by -the Free Software Foundation; either version 3, or (at your option) -any later version. - -GCC is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU General Public License for more details. - -You should have received a copy of the GNU General Public License -along with GCC; see the file COPYING3. If not see -. */ - -#ifndef GCC_PLUGIN_H -#define GCC_PLUGIN_H - -#ifndef IN_GCC -#define IN_GCC -#endif - -#include "config.h" -#include "system.h" -#include "coretypes.h" -#include "highlev-plugin-common.h" -#include "tm.h" -#include "hashtab.h" -#include "hash-set.h" -#include "vec.h" -#include "machmode.h" -#include "hard-reg-set.h" -#include "input.h" -#include "function.h" -#include "predict.h" -#include "dominance.h" -#include "cfg.h" -#include "cfgrtl.h" -#include "cfganal.h" -#include "lcm.h" -#include "cfgbuild.h" -#include "cfgcleanup.h" -#include "hash-map.h" -#include "is-a.h" -#include "plugin-api.h" -#include "ipa-ref.h" -#include "statistics.h" -#include "double-int.h" -#include "real.h" -#include "fixed-value.h" -#include "alias.h" -#include "flags.h" -#include "symtab.h" -#include "tree-core.h" -#include "hash-set.h" -#include "wide-int.h" -#include "inchash.h" -#include "fold-const.h" -#include "tree-check.h" - -/* Event names. */ -enum plugin_event -{ -# define DEFEVENT(NAME) NAME, -# include "plugin.def" -# undef DEFEVENT - PLUGIN_EVENT_FIRST_DYNAMIC -}; - -/* All globals declared here have C linkage to reduce link compatibility - issues with implementation language choice and mangling. */ -#ifdef __cplusplus -extern "C" { -#endif - -extern const char **plugin_event_name; - -struct plugin_argument -{ - char *key; /* key of the argument. */ - char *value; /* value is optional and can be NULL. */ -}; - -/* Additional information about the plugin. Used by --help and --version. */ - -struct plugin_info -{ - const char *version; - const char *help; -}; - -/* Represents the gcc version. Used to avoid using an incompatible plugin. */ - -struct plugin_gcc_version -{ - const char *basever; - const char *datestamp; - const char *devphase; - const char *revision; - const char *configuration_arguments; -}; - -/* Object that keeps track of the plugin name and its arguments. */ -struct plugin_name_args -{ - char *base_name; /* Short name of the plugin (filename without - .so suffix). */ - const char *full_name; /* Path to the plugin as specified with - -fplugin=. */ - int argc; /* Number of arguments specified with - -fplugin-arg-... */ - struct plugin_argument *argv; /* Array of ARGC key-value pairs. */ - const char *version; /* Version string provided by plugin. */ - const char *help; /* Help string provided by plugin. */ -}; - -/* The default version check. Compares every field in VERSION. */ - -extern bool plugin_default_version_check (struct plugin_gcc_version *, - struct plugin_gcc_version *); - -/* Function type for the plugin initialization routine. Each plugin module - should define this as an externally-visible function with name - "plugin_init." - - PLUGIN_INFO - plugin invocation information. - VERSION - the plugin_gcc_version symbol of GCC. - - Returns 0 if initialization finishes successfully. */ - -typedef int (*plugin_init_func) (struct plugin_name_args *plugin_info, - struct plugin_gcc_version *version); - -/* Declaration for "plugin_init" function so that it doesn't need to be - duplicated in every plugin. */ -extern int plugin_init (struct plugin_name_args *plugin_info, - struct plugin_gcc_version *version); - -/* Function type for a plugin callback routine. - - GCC_DATA - event-specific data provided by GCC - USER_DATA - plugin-specific data provided by the plugin */ - -typedef void (*plugin_callback_func) (void *gcc_data, void *user_data); - -/* Called from the plugin's initialization code. Register a single callback. - This function can be called multiple times. - - PLUGIN_NAME - display name for this plugin - EVENT - which event the callback is for - CALLBACK - the callback to be called at the event - USER_DATA - plugin-provided data. -*/ - -/* Number of event ids / names registered so far. */ - -extern int get_event_last (void); - -int get_named_event_id (const char *name, enum insert_option insert); - -/* This is also called without a callback routine for the - PLUGIN_PASS_MANAGER_SETUP, PLUGIN_INFO and PLUGIN_REGISTER_GGC_ROOTS - pseudo-events, with a specific user_data. - */ - -extern void register_callback (const char *plugin_name, - int event, - plugin_callback_func callback, - void *user_data); - -extern int unregister_callback (const char *plugin_name, int event); - - -/* Retrieve the plugin directory name, as returned by the - -fprint-file-name=plugin argument to the gcc program, which is the - -iplugindir program argument to cc1. */ -extern const char* default_plugin_dir_name (void); - -#ifdef __cplusplus -} -#endif - -/* In case the C++ compiler does name mangling for globals, declare - plugin_is_GPL_compatible extern "C" so that a later definition - in a plugin file will have this linkage. */ -#ifdef __cplusplus -extern "C" { -#endif -extern int plugin_is_GPL_compatible; -#ifdef __cplusplus -} -#endif - -#endif /* GCC_PLUGIN_H */ diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/gcc-symtab.h b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/gcc-symtab.h deleted file mode 100644 index 5e682ef..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/gcc-symtab.h +++ /dev/null @@ -1,28 +0,0 @@ -/* Declarations for symtab.c. - FIXME - This file should be named symtab.h, but that name conflicts - with libcpp's symtab.h. - - Copyright (C) 2013-2015 Free Software Foundation, Inc. - -This file is part of GCC. - -GCC is free software; you can redistribute it and/or modify it under -the terms of the GNU General Public License as published by the Free -Software Foundation; either version 3, or (at your option) any later -version. - -GCC is distributed in the hope that it will be useful, but WITHOUT ANY -WARRANTY; without even the implied warranty of MERCHANTABILITY or -FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -for more details. - -You should have received a copy of the GNU General Public License -along with GCC; see the file COPYING3. If not see -. */ - -#ifndef GCC_SYMTAB_H -#define GCC_SYMTAB_H - -extern void change_decl_assembler_name (tree, tree); - -#endif // GCC_SYMTAB_H diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/gcc.h b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/gcc.h deleted file mode 100644 index f10a103..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/gcc.h +++ /dev/null @@ -1,96 +0,0 @@ -/* Header file for modules that link with gcc.c - Copyright (C) 1999-2015 Free Software Foundation, Inc. - -This file is part of GCC. - -GCC is free software; you can redistribute it and/or modify it under -the terms of the GNU General Public License as published by the Free -Software Foundation; either version 3, or (at your option) any later -version. - -GCC is distributed in the hope that it will be useful, but WITHOUT ANY -WARRANTY; without even the implied warranty of MERCHANTABILITY or -FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -for more details. - -You should have received a copy of the GNU General Public License -along with GCC; see the file COPYING3. If not see -. */ - -#ifndef GCC_GCC_H -#define GCC_GCC_H - -#include "version.h" -#include "diagnostic-core.h" - -/* The top-level "main" within the driver would be ~1000 lines long. - This class breaks it up into smaller functions and contains some - state shared by them. */ - -class driver -{ - public: - int main (int argc, char **argv); - - private: - void set_progname (const char *argv0) const; - void expand_at_files (int *argc, char ***argv) const; - void decode_argv (int argc, const char **argv); - void global_initializations (); - void build_multilib_strings () const; - void set_up_specs () const; - void putenv_COLLECT_GCC (const char *argv0) const; - void maybe_putenv_COLLECT_LTO_WRAPPER () const; - void maybe_putenv_OFFLOAD_TARGETS () const; - void handle_unrecognized_options () const; - int maybe_print_and_exit () const; - bool prepare_infiles (); - void do_spec_on_infiles () const; - void maybe_run_linker (const char *argv0) const; - void final_actions () const; - int get_exit_code () const; - - private: - char *explicit_link_files; - struct cl_decoded_option *decoded_options; - unsigned int decoded_options_count; -}; - -/* The mapping of a spec function name to the C function that - implements it. */ -struct spec_function -{ - const char *name; - const char *(*func) (int, const char **); -}; - -/* These are exported by gcc.c. */ -extern int do_spec (const char *); -extern void record_temp_file (const char *, int, int); -extern void pfatal_with_name (const char *) ATTRIBUTE_NORETURN; -extern void set_input (const char *); - -/* Spec files linked with gcc.c must provide definitions for these. */ - -/* Called before processing to change/add/remove arguments. */ -extern void lang_specific_driver (struct cl_decoded_option **, - unsigned int *, int *); - -/* Called before linking. Returns 0 on success and -1 on failure. */ -extern int lang_specific_pre_link (void); - -extern int n_infiles; - -/* Number of extra output files that lang_specific_pre_link may generate. */ -extern int lang_specific_extra_outfiles; - -/* A vector of corresponding output files is made up later. */ - -extern const char **outfiles; - -extern void -driver_get_configure_time_options (void (*cb)(const char *option, - void *user_data), - void *user_data); - -#endif /* ! GCC_GCC_H */ diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/gcov-counter.def b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/gcov-counter.def deleted file mode 100644 index 4a38062..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/gcov-counter.def +++ /dev/null @@ -1,57 +0,0 @@ -/* Definitions for the gcov counters in the GNU compiler. - Copyright (C) 2001-2015 Free Software Foundation, Inc. - -This file is part of GCC. - -GCC is free software; you can redistribute it and/or modify it under -the terms of the GNU General Public License as published by the Free -Software Foundation; either version 3, or (at your option) any later -version. - -GCC is distributed in the hope that it will be useful, but WITHOUT ANY -WARRANTY; without even the implied warranty of MERCHANTABILITY or -FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -for more details. - -You should have received a copy of the GNU General Public License -along with GCC; see the file COPYING3. If not see -. */ - -/* Before including this file, define a macro: - - DEF_GCOV_COUNTER(COUNTER, NAME, FN_TYPE) - - This macro will be expanded to all supported gcov counters, their - names, or the type of handler functions. FN_TYPE will be - expanded to a handler function, like in gcov_merge, it is - expanded to __gcov_merge ## FN_TYPE. */ - -/* Arc transitions. */ -DEF_GCOV_COUNTER(GCOV_COUNTER_ARCS, "arcs", _add) - -/* Histogram of value inside an interval. */ -DEF_GCOV_COUNTER(GCOV_COUNTER_V_INTERVAL, "interval", _add) - -/* Histogram of exact power2 logarithm of a value. */ -DEF_GCOV_COUNTER(GCOV_COUNTER_V_POW2, "pow2", _add) - -/* The most common value of expression. */ -DEF_GCOV_COUNTER(GCOV_COUNTER_V_SINGLE, "single", _single) - -/* The most common difference between consecutive values of expression. */ -DEF_GCOV_COUNTER(GCOV_COUNTER_V_DELTA, "delta", _delta) - -/* The most common indirect address. */ -DEF_GCOV_COUNTER(GCOV_COUNTER_V_INDIR, "indirect_call", _single) - -/* Compute average value passed to the counter. */ -DEF_GCOV_COUNTER(GCOV_COUNTER_AVERAGE, "average", _add) - -/* IOR of the all values passed to counter. */ -DEF_GCOV_COUNTER(GCOV_COUNTER_IOR, "ior", _ior) - -/* Time profile collecting first run of a function */ -DEF_GCOV_COUNTER(GCOV_TIME_PROFILER, "time_profiler", _time_profile) - -/* Top N value tracking for indirect calls. */ -DEF_GCOV_COUNTER(GCOV_COUNTER_ICALL_TOPNV, "indirect_call_topn", _icall_topn) diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/gcov-io.h b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/gcov-io.h deleted file mode 100644 index dcb2944..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/gcov-io.h +++ /dev/null @@ -1,426 +0,0 @@ -/* File format for coverage information - Copyright (C) 1996-2015 Free Software Foundation, Inc. - Contributed by Bob Manson . - Completely remangled by Nathan Sidwell . - -This file is part of GCC. - -GCC is free software; you can redistribute it and/or modify it under -the terms of the GNU General Public License as published by the Free -Software Foundation; either version 3, or (at your option) any later -version. - -GCC is distributed in the hope that it will be useful, but WITHOUT ANY -WARRANTY; without even the implied warranty of MERCHANTABILITY or -FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -for more details. - -Under Section 7 of GPL version 3, you are granted additional -permissions described in the GCC Runtime Library Exception, version -3.1, as published by the Free Software Foundation. - -You should have received a copy of the GNU General Public License and -a copy of the GCC Runtime Library Exception along with this program; -see the files COPYING3 and COPYING.RUNTIME respectively. If not, see -. */ - - -/* Coverage information is held in two files. A notes file, which is - generated by the compiler, and a data file, which is generated by - the program under test. Both files use a similar structure. We do - not attempt to make these files backwards compatible with previous - versions, as you only need coverage information when developing a - program. We do hold version information, so that mismatches can be - detected, and we use a format that allows tools to skip information - they do not understand or are not interested in. - - Numbers are recorded in the 32 bit unsigned binary form of the - endianness of the machine generating the file. 64 bit numbers are - stored as two 32 bit numbers, the low part first. Strings are - padded with 1 to 4 NUL bytes, to bring the length up to a multiple - of 4. The number of 4 bytes is stored, followed by the padded - string. Zero length and NULL strings are simply stored as a length - of zero (they have no trailing NUL or padding). - - int32: byte3 byte2 byte1 byte0 | byte0 byte1 byte2 byte3 - int64: int32:low int32:high - string: int32:0 | int32:length char* char:0 padding - padding: | char:0 | char:0 char:0 | char:0 char:0 char:0 - item: int32 | int64 | string - - The basic format of the files is - - file : int32:magic int32:version int32:stamp record* - - The magic ident is different for the notes and the data files. The - magic ident is used to determine the endianness of the file, when - reading. The version is the same for both files and is derived - from gcc's version number. The stamp value is used to synchronize - note and data files and to synchronize merging within a data - file. It need not be an absolute time stamp, merely a ticker that - increments fast enough and cycles slow enough to distinguish - different compile/run/compile cycles. - - Although the ident and version are formally 32 bit numbers, they - are derived from 4 character ASCII strings. The version number - consists of the single character major version number, a two - character minor version number (leading zero for versions less than - 10), and a single character indicating the status of the release. - That will be 'e' experimental, 'p' prerelease and 'r' for release. - Because, by good fortune, these are in alphabetical order, string - collating can be used to compare version strings. Be aware that - the 'e' designation will (naturally) be unstable and might be - incompatible with itself. For gcc 3.4 experimental, it would be - '304e' (0x33303465). When the major version reaches 10, the - letters A-Z will be used. Assuming minor increments releases every - 6 months, we have to make a major increment every 50 years. - Assuming major increments releases every 5 years, we're ok for the - next 155 years -- good enough for me. - - A record has a tag, length and variable amount of data. - - record: header data - header: int32:tag int32:length - data: item* - - Records are not nested, but there is a record hierarchy. Tag - numbers reflect this hierarchy. Tags are unique across note and - data files. Some record types have a varying amount of data. The - LENGTH is the number of 4bytes that follow and is usually used to - determine how much data. The tag value is split into 4 8-bit - fields, one for each of four possible levels. The most significant - is allocated first. Unused levels are zero. Active levels are - odd-valued, so that the LSB of the level is one. A sub-level - incorporates the values of its superlevels. This formatting allows - you to determine the tag hierarchy, without understanding the tags - themselves, and is similar to the standard section numbering used - in technical documents. Level values [1..3f] are used for common - tags, values [41..9f] for the notes file and [a1..ff] for the data - file. - - The notes file contains the following records - note: unit function-graph* - unit: header int32:checksum string:source - function-graph: announce_function basic_blocks {arcs | lines}* - announce_function: header int32:ident - int32:lineno_checksum int32:cfg_checksum - string:name string:source int32:lineno - basic_block: header int32:flags* - arcs: header int32:block_no arc* - arc: int32:dest_block int32:flags - lines: header int32:block_no line* - int32:0 string:NULL - line: int32:line_no | int32:0 string:filename - - The BASIC_BLOCK record holds per-bb flags. The number of blocks - can be inferred from its data length. There is one ARCS record per - basic block. The number of arcs from a bb is implicit from the - data length. It enumerates the destination bb and per-arc flags. - There is one LINES record per basic block, it enumerates the source - lines which belong to that basic block. Source file names are - introduced by a line number of 0, following lines are from the new - source file. The initial source file for the function is NULL, but - the current source file should be remembered from one LINES record - to the next. The end of a block is indicated by an empty filename - - this does not reset the current source file. Note there is no - ordering of the ARCS and LINES records: they may be in any order, - interleaved in any manner. The current filename follows the order - the LINES records are stored in the file, *not* the ordering of the - blocks they are for. - - The data file contains the following records. - data: {unit summary:object summary:program* function-data*}* - unit: header int32:checksum - function-data: announce_function present counts - announce_function: header int32:ident - int32:lineno_checksum int32:cfg_checksum - present: header int32:present - counts: header int64:count* - summary: int32:checksum {count-summary}GCOV_COUNTERS_SUMMABLE - count-summary: int32:num int32:runs int64:sum - int64:max int64:sum_max histogram - histogram: {int32:bitvector}8 histogram-buckets* - histogram-buckets: int32:num int64:min int64:sum - - The ANNOUNCE_FUNCTION record is the same as that in the note file, - but without the source location. The COUNTS gives the - counter values for instrumented features. The about the whole - program. The checksum is used for whole program summaries, and - disambiguates different programs which include the same - instrumented object file. There may be several program summaries, - each with a unique checksum. The object summary's checksum is - zero. Note that the data file might contain information from - several runs concatenated, or the data might be merged. - - This file is included by both the compiler, gcov tools and the - runtime support library libgcov. IN_LIBGCOV and IN_GCOV are used to - distinguish which case is which. If IN_LIBGCOV is nonzero, - libgcov is being built. If IN_GCOV is nonzero, the gcov tools are - being built. Otherwise the compiler is being built. IN_GCOV may be - positive or negative. If positive, we are compiling a tool that - requires additional functions (see the code for knowledge of what - those functions are). */ - -#ifndef GCC_GCOV_IO_H -#define GCC_GCOV_IO_H - -#ifndef IN_LIBGCOV -/* About the host */ - -typedef unsigned gcov_unsigned_t; -typedef unsigned gcov_position_t; -/* gcov_type is typedef'd elsewhere for the compiler */ -#if IN_GCOV -#define GCOV_LINKAGE static -typedef int64_t gcov_type; -typedef uint64_t gcov_type_unsigned; -#if IN_GCOV > 0 -#include -#endif -#else /*!IN_GCOV */ -#define GCOV_TYPE_SIZE (LONG_LONG_TYPE_SIZE > 32 ? 64 : 32) -#endif - -#if defined (HOST_HAS_F_SETLKW) -#define GCOV_LOCKED 1 -#else -#define GCOV_LOCKED 0 -#endif - -#define ATTRIBUTE_HIDDEN - -#endif /* !IN_LIBGOCV */ - -#ifndef GCOV_LINKAGE -#define GCOV_LINKAGE extern -#endif - -#if IN_LIBGCOV -#define gcov_nonruntime_assert(EXPR) ((void)(0 && (EXPR))) -#else -#define gcov_nonruntime_assert(EXPR) gcc_assert (EXPR) -#define gcov_error(...) fatal_error (input_location, __VA_ARGS__) -#endif - -/* File suffixes. */ -#define GCOV_DATA_SUFFIX ".gcda" -#define GCOV_NOTE_SUFFIX ".gcno" - -/* File magic. Must not be palindromes. */ -#define GCOV_DATA_MAGIC ((gcov_unsigned_t)0x67636461) /* "gcda" */ -#define GCOV_NOTE_MAGIC ((gcov_unsigned_t)0x67636e6f) /* "gcno" */ - -/* gcov-iov.h is automatically generated by the makefile from - version.c, it looks like - #define GCOV_VERSION ((gcov_unsigned_t)0x89abcdef) -*/ -#include "gcov-iov.h" - -/* Convert a magic or version number to a 4 character string. */ -#define GCOV_UNSIGNED2STRING(ARRAY,VALUE) \ - ((ARRAY)[0] = (char)((VALUE) >> 24), \ - (ARRAY)[1] = (char)((VALUE) >> 16), \ - (ARRAY)[2] = (char)((VALUE) >> 8), \ - (ARRAY)[3] = (char)((VALUE) >> 0)) - -/* The record tags. Values [1..3f] are for tags which may be in either - file. Values [41..9f] for those in the note file and [a1..ff] for - the data file. The tag value zero is used as an explicit end of - file marker -- it is not required to be present. */ - -#define GCOV_TAG_FUNCTION ((gcov_unsigned_t)0x01000000) -#define GCOV_TAG_FUNCTION_LENGTH (3) -#define GCOV_TAG_BLOCKS ((gcov_unsigned_t)0x01410000) -#define GCOV_TAG_BLOCKS_LENGTH(NUM) (NUM) -#define GCOV_TAG_BLOCKS_NUM(LENGTH) (LENGTH) -#define GCOV_TAG_ARCS ((gcov_unsigned_t)0x01430000) -#define GCOV_TAG_ARCS_LENGTH(NUM) (1 + (NUM) * 2) -#define GCOV_TAG_ARCS_NUM(LENGTH) (((LENGTH) - 1) / 2) -#define GCOV_TAG_LINES ((gcov_unsigned_t)0x01450000) -#define GCOV_TAG_COUNTER_BASE ((gcov_unsigned_t)0x01a10000) -#define GCOV_TAG_COUNTER_LENGTH(NUM) ((NUM) * 2) -#define GCOV_TAG_COUNTER_NUM(LENGTH) ((LENGTH) / 2) -#define GCOV_TAG_OBJECT_SUMMARY ((gcov_unsigned_t)0xa1000000) /* Obsolete */ -#define GCOV_TAG_PROGRAM_SUMMARY ((gcov_unsigned_t)0xa3000000) -#define GCOV_TAG_SUMMARY_LENGTH(NUM) \ - (1 + GCOV_COUNTERS_SUMMABLE * (10 + 3 * 2) + (NUM) * 5) -#define GCOV_TAG_AFDO_FILE_NAMES ((gcov_unsigned_t)0xaa000000) -#define GCOV_TAG_AFDO_FUNCTION ((gcov_unsigned_t)0xac000000) -#define GCOV_TAG_AFDO_WORKING_SET ((gcov_unsigned_t)0xaf000000) - - -/* Counters that are collected. */ - -#define DEF_GCOV_COUNTER(COUNTER, NAME, MERGE_FN) COUNTER, -enum { -#include "gcov-counter.def" -GCOV_COUNTERS -}; -#undef DEF_GCOV_COUNTER - -/* Counters which can be summaried. */ -#define GCOV_COUNTERS_SUMMABLE (GCOV_COUNTER_ARCS + 1) - -/* The first of counters used for value profiling. They must form a - consecutive interval and their order must match the order of - HIST_TYPEs in value-prof.h. */ -#define GCOV_FIRST_VALUE_COUNTER GCOV_COUNTERS_SUMMABLE - -/* The last of counters used for value profiling. */ -#define GCOV_LAST_VALUE_COUNTER (GCOV_COUNTERS - 1) - -/* Number of counters used for value profiling. */ -#define GCOV_N_VALUE_COUNTERS \ - (GCOV_LAST_VALUE_COUNTER - GCOV_FIRST_VALUE_COUNTER + 1) - -/* The number of hottest callees to be tracked. */ -#define GCOV_ICALL_TOPN_VAL 2 - -/* The number of counter entries per icall callsite. */ -#define GCOV_ICALL_TOPN_NCOUNTS (1 + GCOV_ICALL_TOPN_VAL * 4) - -/* Convert a counter index to a tag. */ -#define GCOV_TAG_FOR_COUNTER(COUNT) \ - (GCOV_TAG_COUNTER_BASE + ((gcov_unsigned_t)(COUNT) << 17)) -/* Convert a tag to a counter. */ -#define GCOV_COUNTER_FOR_TAG(TAG) \ - ((unsigned)(((TAG) - GCOV_TAG_COUNTER_BASE) >> 17)) -/* Check whether a tag is a counter tag. */ -#define GCOV_TAG_IS_COUNTER(TAG) \ - (!((TAG) & 0xFFFF) && GCOV_COUNTER_FOR_TAG (TAG) < GCOV_COUNTERS) - -/* The tag level mask has 1's in the position of the inner levels, & - the lsb of the current level, and zero on the current and outer - levels. */ -#define GCOV_TAG_MASK(TAG) (((TAG) - 1) ^ (TAG)) - -/* Return nonzero if SUB is an immediate subtag of TAG. */ -#define GCOV_TAG_IS_SUBTAG(TAG,SUB) \ - (GCOV_TAG_MASK (TAG) >> 8 == GCOV_TAG_MASK (SUB) \ - && !(((SUB) ^ (TAG)) & ~GCOV_TAG_MASK (TAG))) - -/* Return nonzero if SUB is at a sublevel to TAG. */ -#define GCOV_TAG_IS_SUBLEVEL(TAG,SUB) \ - (GCOV_TAG_MASK (TAG) > GCOV_TAG_MASK (SUB)) - -/* Basic block flags. */ -#define GCOV_BLOCK_UNEXPECTED (1 << 1) - -/* Arc flags. */ -#define GCOV_ARC_ON_TREE (1 << 0) -#define GCOV_ARC_FAKE (1 << 1) -#define GCOV_ARC_FALLTHROUGH (1 << 2) - -/* Structured records. */ - -/* Structure used for each bucket of the log2 histogram of counter values. */ -typedef struct -{ - /* Number of counters whose profile count falls within the bucket. */ - gcov_unsigned_t num_counters; - /* Smallest profile count included in this bucket. */ - gcov_type min_value; - /* Cumulative value of the profile counts in this bucket. */ - gcov_type cum_value; -} gcov_bucket_type; - -/* For a log2 scale histogram with each range split into 4 - linear sub-ranges, there will be at most 64 (max gcov_type bit size) - 1 log2 - ranges since the lowest 2 log2 values share the lowest 4 linear - sub-range (values 0 - 3). This is 252 total entries (63*4). */ - -#define GCOV_HISTOGRAM_SIZE 252 - -/* How many unsigned ints are required to hold a bit vector of non-zero - histogram entries when the histogram is written to the gcov file. - This is essentially a ceiling divide by 32 bits. */ -#define GCOV_HISTOGRAM_BITVECTOR_SIZE (GCOV_HISTOGRAM_SIZE + 31) / 32 - -/* Cumulative counter data. */ -struct gcov_ctr_summary -{ - gcov_unsigned_t num; /* number of counters. */ - gcov_unsigned_t runs; /* number of program runs */ - gcov_type sum_all; /* sum of all counters accumulated. */ - gcov_type run_max; /* maximum value on a single run. */ - gcov_type sum_max; /* sum of individual run max values. */ - gcov_bucket_type histogram[GCOV_HISTOGRAM_SIZE]; /* histogram of - counter values. */ -}; - -/* Object & program summary record. */ -struct gcov_summary -{ - gcov_unsigned_t checksum; /* checksum of program */ - struct gcov_ctr_summary ctrs[GCOV_COUNTERS_SUMMABLE]; -}; - -#if !defined(inhibit_libc) - -/* Functions for reading and writing gcov files. In libgcov you can - open the file for reading then writing. Elsewhere you can open the - file either for reading or for writing. When reading a file you may - use the gcov_read_* functions, gcov_sync, gcov_position, & - gcov_error. When writing a file you may use the gcov_write - functions, gcov_seek & gcov_error. When a file is to be rewritten - you use the functions for reading, then gcov_rewrite then the - functions for writing. Your file may become corrupted if you break - these invariants. */ - -#if !IN_LIBGCOV -GCOV_LINKAGE int gcov_open (const char */*name*/, int /*direction*/); -GCOV_LINKAGE int gcov_magic (gcov_unsigned_t, gcov_unsigned_t); -#endif - -/* Available everywhere. */ -GCOV_LINKAGE int gcov_close (void) ATTRIBUTE_HIDDEN; -GCOV_LINKAGE gcov_unsigned_t gcov_read_unsigned (void) ATTRIBUTE_HIDDEN; -GCOV_LINKAGE gcov_type gcov_read_counter (void) ATTRIBUTE_HIDDEN; -GCOV_LINKAGE void gcov_read_summary (struct gcov_summary *) ATTRIBUTE_HIDDEN; -GCOV_LINKAGE const char *gcov_read_string (void); -GCOV_LINKAGE void gcov_sync (gcov_position_t /*base*/, - gcov_unsigned_t /*length */); - -#if !IN_GCOV -/* Available outside gcov */ -GCOV_LINKAGE void gcov_write_unsigned (gcov_unsigned_t) ATTRIBUTE_HIDDEN; -#endif - -#if !IN_GCOV && !IN_LIBGCOV -/* Available only in compiler */ -GCOV_LINKAGE unsigned gcov_histo_index (gcov_type value); -GCOV_LINKAGE void gcov_write_string (const char *); -GCOV_LINKAGE gcov_position_t gcov_write_tag (gcov_unsigned_t); -GCOV_LINKAGE void gcov_write_length (gcov_position_t /*position*/); -#endif - -#if IN_GCOV <= 0 && !IN_LIBGCOV -/* Available in gcov-dump and the compiler. */ - -/* Number of data points in the working set summary array. Using 128 - provides information for at least every 1% increment of the total - profile size. The last entry is hardwired to 99.9% of the total. */ -#define NUM_GCOV_WORKING_SETS 128 - -/* Working set size statistics for a given percentage of the entire - profile (sum_all from the counter summary). */ -typedef struct gcov_working_set_info -{ - /* Number of hot counters included in this working set. */ - unsigned num_counters; - /* Smallest counter included in this working set. */ - gcov_type min_counter; -} gcov_working_set_t; - -GCOV_LINKAGE void compute_working_sets (const struct gcov_ctr_summary *summary, - gcov_working_set_t *gcov_working_sets); -#endif - -#if IN_GCOV > 0 -/* Available in gcov */ -GCOV_LINKAGE time_t gcov_time (void); -#endif - -#endif /* !inhibit_libc */ - -#endif /* GCC_GCOV_IO_H */ diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/gcse-common.h b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/gcse-common.h deleted file mode 100644 index a6b1a0c..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/gcse-common.h +++ /dev/null @@ -1,47 +0,0 @@ -/* Structures and prototypes common across the normal GCSE - implementation and the post-reload implementation. - Copyright (C) 1997-2015 Free Software Foundation, Inc. - -This file is part of GCC. - -GCC is free software; you can redistribute it and/or modify it under -the terms of the GNU General Public License as published by the Free -Software Foundation; either version 3, or (at your option) any later -version. - -GCC is distributed in the hope that it will be useful, but WITHOUT ANY -WARRANTY; without even the implied warranty of MERCHANTABILITY or -FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -for more details. - -You should have received a copy of the GNU General Public License -along with GCC; see the file COPYING3. If not see -. */ - -#ifndef GCC_GCSE_COMMON_H -#define GCC_GCSE_COMMON_H - -typedef vec vec_rtx_heap; -typedef struct modify_pair_s -{ - rtx dest; /* A MEM. */ - rtx dest_addr; /* The canonical address of `dest'. */ -} modify_pair; - -typedef vec vec_modify_pair_heap; - -struct gcse_note_stores_info -{ - rtx_insn *insn; - vec *canon_mem_list; -}; - -extern void compute_transp (const_rtx, int, sbitmap *, bitmap, - bitmap, vec *); -extern void record_last_mem_set_info_common (rtx_insn *, - vec *, - vec *, - bitmap, bitmap); - - -#endif diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/gcse.h b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/gcse.h deleted file mode 100644 index e28a07d..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/gcse.h +++ /dev/null @@ -1,44 +0,0 @@ -/* Global common subexpression elimination/Partial redundancy elimination - and global constant/copy propagation for GNU compiler. - Copyright (C) 1997-2015 Free Software Foundation, Inc. - -This file is part of GCC. - -GCC is free software; you can redistribute it and/or modify it under -the terms of the GNU General Public License as published by the Free -Software Foundation; either version 3, or (at your option) any later -version. - -GCC is distributed in the hope that it will be useful, but WITHOUT ANY -WARRANTY; without even the implied warranty of MERCHANTABILITY or -FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -for more details. - -You should have received a copy of the GNU General Public License -along with GCC; see the file COPYING3. If not see -. */ - -#ifndef GCC_GCSE_H -#define GCC_GCSE_H - -/* Target-dependent globals. */ -struct target_gcse { - /* Nonzero for each mode that supports (set (reg) (reg)). - This is trivially true for integer and floating point values. - It may or may not be true for condition codes. */ - char x_can_copy[(int) NUM_MACHINE_MODES]; - - /* True if the previous field has been initialized. */ - bool x_can_copy_init_p; -}; - -extern struct target_gcse default_target_gcse; -#if SWITCHABLE_TARGET -extern struct target_gcse *this_target_gcse; -#else -#define this_target_gcse (&default_target_gcse) -#endif - -void gcse_c_finalize (void); - -#endif diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/generic-match.h b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/generic-match.h deleted file mode 100644 index 6e44684..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/generic-match.h +++ /dev/null @@ -1,33 +0,0 @@ -/* Generic simplify definitions. - - Copyright (C) 2011-2015 Free Software Foundation, Inc. - Contributed by Richard Guenther - -This file is part of GCC. - -GCC is free software; you can redistribute it and/or modify it under -the terms of the GNU General Public License as published by the Free -Software Foundation; either version 3, or (at your option) any later -version. - -GCC is distributed in the hope that it will be useful, but WITHOUT ANY -WARRANTY; without even the implied warranty of MERCHANTABILITY or -FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -for more details. - -You should have received a copy of the GNU General Public License -along with GCC; see the file COPYING3. If not see -. */ - -#ifndef GCC_GENERIC_MATCH_H -#define GCC_GENERIC_MATCH_H - -/* Note the following functions are supposed to be only used from - fold_unary_loc, fold_binary_loc and fold_ternary_loc respectively. - They are not considered a public API. */ - -tree generic_simplify (location_t, enum tree_code, tree, tree); -tree generic_simplify (location_t, enum tree_code, tree, tree, tree); -tree generic_simplify (location_t, enum tree_code, tree, tree, tree, tree); - -#endif /* GCC_GENERIC_MATCH_H */ diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/gengtype.h b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/gengtype.h deleted file mode 100644 index 83f3632..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/gengtype.h +++ /dev/null @@ -1,515 +0,0 @@ -/* Process source files and output type information. - Copyright (C) 2002-2015 Free Software Foundation, Inc. - - This file is part of GCC. - - GCC is free software; you can redistribute it and/or modify it under - the terms of the GNU General Public License as published by the Free - Software Foundation; either version 3, or (at your option) any later - version. - - GCC is distributed in the hope that it will be useful, but WITHOUT ANY - WARRANTY; without even the implied warranty of MERCHANTABILITY or - FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License - for more details. - - You should have received a copy of the GNU General Public License - along with GCC; see the file COPYING3. If not see - . */ - -#ifndef GCC_GENGTYPE_H -#define GCC_GENGTYPE_H - -#define obstack_chunk_alloc xmalloc -#define obstack_chunk_free free -#define OBSTACK_CHUNK_SIZE 0 - -/* Sets of accepted source languages like C, C++, Ada... are - represented by a bitmap. */ -typedef unsigned lang_bitmap; - -/* Variable length structure representing an input file. A hash table - ensure uniqueness for a given input file name. The only function - allocating input_file-s is input_file_by_name. */ -struct input_file_st -{ - struct outf* inpoutf; /* Cached corresponding output file, computed - in get_output_file_with_visibility. */ - lang_bitmap inpbitmap; /* The set of languages using this file. */ - bool inpisplugin; /* Flag set for plugin input files. */ - char inpname[1]; /* A variable-length array, ended by a null - char. */ -}; -typedef struct input_file_st input_file; - -/* A file position, mostly for error messages. - The FILE element may be compared using pointer equality. */ -struct fileloc -{ - const input_file *file; - int line; -}; - - -/* Table of all input files and its size. */ -extern const input_file** gt_files; -extern size_t num_gt_files; - -/* A number of places use the name of this "gengtype.c" file for a - location for things that we can't rely on the source to define. We - also need to refer to the "system.h" file specifically. These two - pointers are initialized early in main. */ -extern input_file* this_file; -extern input_file* system_h_file; - -/* Retrieve or create the input_file for a given name, which is a file - path. This is the only function allocating input_file-s and it is - hash-consing them. */ -input_file* input_file_by_name (const char* name); - -/* For F an input_file, return the relative path to F from $(srcdir) - if the latter is a prefix in F, NULL otherwise. */ -const char *get_file_srcdir_relative_path (const input_file *inpf); - -/* Get the name of an input file. */ -static inline const char* -get_input_file_name (const input_file *inpf) -{ - if (inpf) - return inpf->inpname; - return NULL; -} - -/* Return a bitmap which has bit `1 << BASE_FILE_' set iff - INPUT_FILE is used by . - - This function should be written to assume that a file _is_ used - if the situation is unclear. If it wrongly assumes a file _is_ used, - a linker error will result. If it wrongly assumes a file _is not_ used, - some GC roots may be missed, which is a much harder-to-debug problem. - */ - -static inline lang_bitmap -get_lang_bitmap (const input_file* inpf) -{ - if (inpf == NULL) - return 0; - return inpf->inpbitmap; -} - -/* Set the bitmap returned by get_lang_bitmap. The only legitimate - callers of this function are read_input_list & read_state_*. */ -static inline void -set_lang_bitmap (input_file* inpf, lang_bitmap n) -{ - gcc_assert (inpf); - inpf->inpbitmap = n; -} - -/* Vector of per-language directories. */ -extern const char **lang_dir_names; -extern size_t num_lang_dirs; - -/* Data types handed around within, but opaque to, the lexer and parser. */ -typedef struct pair *pair_p; -typedef struct type *type_p; -typedef const struct type *const_type_p; -typedef struct options *options_p; - -/* Variables used to communicate between the lexer and the parser. */ -extern int lexer_toplevel_done; -extern struct fileloc lexer_line; - -/* Various things, organized as linked lists, needed both in - gengtype.c & in gengtype-state.c files. */ -extern pair_p typedefs; -extern type_p structures; -extern pair_p variables; - -/* An enum for distinguishing GGC vs PCH. */ - -enum write_types_kinds -{ - WTK_GGC, - WTK_PCH, - - NUM_WTK -}; - -/* Discrimating kind of types we can understand. */ - -enum typekind { - TYPE_NONE=0, /* Never used, so zeroed memory is invalid. */ - TYPE_UNDEFINED, /* We have not yet seen a definition for this type. - If a type is still undefined when generating code, - an error will be generated. */ - TYPE_SCALAR, /* Scalar types like char. */ - TYPE_STRING, /* The string type. */ - TYPE_STRUCT, /* Type for GTY-ed structs. */ - TYPE_UNION, /* Type for GTY-ed discriminated unions. */ - TYPE_POINTER, /* Pointer type to GTY-ed type. */ - TYPE_ARRAY, /* Array of GTY-ed types. */ - TYPE_LANG_STRUCT, /* GCC front-end language specific structs. - Various languages may have homonymous but - different structs. */ - TYPE_USER_STRUCT /* User defined type. Walkers and markers for - this type are assumed to be provided by the - user. */ -}; - -/* Discriminating kind for options. */ -enum option_kind { - OPTION_NONE=0, /* Never used, so zeroed memory is invalid. */ - OPTION_STRING, /* A string-valued option. Most options are - strings. */ - OPTION_TYPE, /* A type-valued option. */ - OPTION_NESTED /* Option data for 'nested_ptr'. */ -}; - - -/* A way to pass data through to the output end. */ -struct options { - struct options *next; /* next option of the same pair. */ - const char *name; /* GTY option name. */ - enum option_kind kind; /* discriminating option kind. */ - union { - const char* string; /* When OPTION_STRING. */ - type_p type; /* When OPTION_TYPE. */ - struct nested_ptr_data* nested; /* when OPTION_NESTED. */ - } info; -}; - - -/* Option data for the 'nested_ptr' option. */ -struct nested_ptr_data { - type_p type; - const char *convert_to; - const char *convert_from; -}; - -/* Some functions to create various options structures with name NAME - and info INFO. NEXT is the next option in the chain. */ - -/* Create a string option. */ -options_p create_string_option (options_p next, const char* name, - const char* info); - -/* Create a type option. */ -options_p create_type_option (options_p next, const char* name, - type_p info); - -/* Create a nested option. */ -options_p create_nested_option (options_p next, const char* name, - struct nested_ptr_data* info); - -/* Create a nested pointer option. */ -options_p create_nested_ptr_option (options_p, type_p t, - const char *from, const char *to); - -/* A name and a type. */ -struct pair { - pair_p next; /* The next pair in the linked list. */ - const char *name; /* The defined name. */ - type_p type; /* Its GTY-ed type. */ - struct fileloc line; /* The file location. */ - options_p opt; /* GTY options, as a linked list. */ -}; - -/* Usage information for GTY-ed types. Gengtype has to care only of - used GTY-ed types. Types are initially unused, and their usage is - computed by set_gc_used_type and set_gc_used functions. */ - -enum gc_used_enum { - - /* We need that zeroed types are initially unused. */ - GC_UNUSED=0, - - /* The GTY-ed type is used, e.g by a GTY-ed variable or a field - inside a GTY-ed used type. */ - GC_USED, - - /* For GTY-ed structures whose definitions we haven't seen so far - when we encounter a pointer to it that is annotated with - ``maybe_undef''. If after reading in everything we don't have - source file information for it, we assume that it never has been - defined. */ - GC_MAYBE_POINTED_TO, - - /* For known GTY-ed structures which are pointed to by GTY-ed - variables or fields. */ - GC_POINTED_TO -}; - -/* Our type structure describes all types handled by gengtype. */ -struct type { - /* Discriminating kind, cannot be TYPE_NONE. */ - enum typekind kind; - - /* For top-level structs or unions, the 'next' field links the - global list 'structures'; for lang_structs, their homonymous structs are - linked using this 'next' field. The homonymous list starts at the - s.lang_struct field of the lang_struct. See the new_structure function - for details. This is tricky! */ - type_p next; - - /* State number used when writing & reading the persistent state. A - type with a positive number has already been written. For ease - of debugging, newly allocated types have a unique negative - number. */ - int state_number; - - /* Each GTY-ed type which is pointed to by some GTY-ed type knows - the GTY pointer type pointing to it. See create_pointer - function. */ - type_p pointer_to; - - /* Type usage information, computed by set_gc_used_type and - set_gc_used functions. */ - enum gc_used_enum gc_used; - - /* The following union is discriminated by the 'kind' field above. */ - union { - /* TYPE__NONE is impossible. */ - - /* when TYPE_POINTER: */ - type_p p; - - /* when TYPE_STRUCT or TYPE_UNION or TYPE_LANG_STRUCT, we have an - aggregate type containing fields: */ - struct { - const char *tag; /* the aggragate tag, if any. */ - struct fileloc line; /* the source location. */ - pair_p fields; /* the linked list of fields. */ - options_p opt; /* the GTY options if any. */ - lang_bitmap bitmap; /* the set of front-end languages - using that GTY-ed aggregate. */ - /* For TYPE_LANG_STRUCT, the lang_struct field gives the first - element of a linked list of homonymous struct or union types. - Within this list, each homonymous type has as its lang_struct - field the original TYPE_LANG_STRUCT type. This is a dirty - trick, see the new_structure function for details. */ - type_p lang_struct; - - type_p base_class; /* the parent class, if any. */ - - /* The following two fields are not serialized in state files, and - are instead reconstructed on load. */ - - /* The head of a singly-linked list of immediate descendents in - the inheritance hierarchy. */ - type_p first_subclass; - /* The next in that list. */ - type_p next_sibling_class; - - /* Have we already written ggc/pch user func for ptr to this? - (in write_user_func_for_structure_ptr). */ - bool wrote_user_func_for_ptr[NUM_WTK]; - } s; - - /* when TYPE_SCALAR: */ - bool scalar_is_char; - - /* when TYPE_ARRAY: */ - struct { - type_p p; /* The array component type. */ - const char *len; /* The string if any giving its length. */ - } a; - - } u; -}; - -/* The one and only TYPE_STRING. */ -extern struct type string_type; - -/* The two and only TYPE_SCALARs. Their u.scalar_is_char flags are - set early in main. */ -extern struct type scalar_nonchar; -extern struct type scalar_char; - -/* Test if a type is a union, either a plain one or a language - specific one. */ -#define UNION_P(x) \ - ((x)->kind == TYPE_UNION \ - || ((x)->kind == TYPE_LANG_STRUCT \ - && (x)->u.s.lang_struct->kind == TYPE_UNION)) - -/* Test if a type is a union or a structure, perhaps a language - specific one. */ -static inline bool -union_or_struct_p (enum typekind kind) -{ - return (kind == TYPE_UNION - || kind == TYPE_STRUCT - || kind == TYPE_LANG_STRUCT - || kind == TYPE_USER_STRUCT); -} - -static inline bool -union_or_struct_p (const_type_p x) -{ - return union_or_struct_p (x->kind); -} - -/* Give the file location of a type, if any. */ -static inline struct fileloc* -type_fileloc (type_p t) -{ - if (!t) - return NULL; - if (union_or_struct_p (t)) - return &t->u.s.line; - return NULL; -} - -/* Structure representing an output file. */ -struct outf -{ - struct outf *next; - const char *name; - size_t buflength; - size_t bufused; - char *buf; -}; -typedef struct outf *outf_p; - -/* The list of output files. */ -extern outf_p output_files; - -/* The output header file that is included into pretty much every - source file. */ -extern outf_p header_file; - -/* Print, like fprintf, to O. No-op if O is NULL. */ -void -oprintf (outf_p o, const char *S, ...) - ATTRIBUTE_PRINTF_2; - -/* An output file, suitable for definitions, that can see declarations - made in INPF and is linked into every language that uses INPF. May - return NULL in plugin mode. The INPF argument is almost const, but - since the result is cached in its inpoutf field it cannot be - declared const. */ -outf_p get_output_file_with_visibility (input_file* inpf); - -/* The name of an output file, suitable for definitions, that can see - declarations made in INPF and is linked into every language that - uses INPF. May return NULL. */ -const char *get_output_file_name (input_file *inpf); - - -/* Source directory. */ -extern const char *srcdir; /* (-S) program argument. */ - -/* Length of srcdir name. */ -extern size_t srcdir_len; - -/* Variable used for reading and writing the state. */ -extern const char *read_state_filename; /* (-r) program argument. */ -extern const char *write_state_filename; /* (-w) program argument. */ - -/* Functions reading and writing the entire gengtype state, called from - main, and implemented in file gengtype-state.c. */ -void read_state (const char* path); -/* Write the state, and update the state_number field in types. */ -void write_state (const char* path); - - -/* Print an error message. */ -extern void error_at_line -(const struct fileloc *pos, const char *msg, ...) ATTRIBUTE_PRINTF_2; - -/* Constructor routines for types. */ -extern void do_typedef (const char *s, type_p t, struct fileloc *pos); -extern void do_scalar_typedef (const char *s, struct fileloc *pos); -extern type_p resolve_typedef (const char *s, struct fileloc *pos); -extern void add_subclass (type_p base, type_p subclass); -extern type_p new_structure (const char *name, enum typekind kind, - struct fileloc *pos, pair_p fields, - options_p o, type_p base); -type_p create_user_defined_type (const char *, struct fileloc *); -extern type_p find_structure (const char *s, enum typekind kind); -extern type_p create_scalar_type (const char *name); -extern type_p create_pointer (type_p t); -extern type_p create_array (type_p t, const char *len); -extern pair_p create_field_at (pair_p next, type_p type, - const char *name, options_p opt, - struct fileloc *pos); -extern pair_p nreverse_pairs (pair_p list); -extern type_p adjust_field_type (type_p, options_p); -extern void note_variable (const char *s, type_p t, options_p o, - struct fileloc *pos); - -/* Lexer and parser routines. */ -extern int yylex (const char **yylval); -extern void yybegin (const char *fname); -extern void yyend (void); -extern void parse_file (const char *name); -extern bool hit_error; - -/* Token codes. */ -enum gty_token -{ - EOF_TOKEN = 0, - - /* Per standard convention, codes in the range (0, UCHAR_MAX] - represent single characters with those character codes. */ - CHAR_TOKEN_OFFSET = UCHAR_MAX + 1, - GTY_TOKEN = CHAR_TOKEN_OFFSET, - TYPEDEF, - EXTERN, - STATIC, - UNION, - STRUCT, - ENUM, - ELLIPSIS, - PTR_ALIAS, - NESTED_PTR, - USER_GTY, - NUM, - SCALAR, - ID, - STRING, - CHAR, - ARRAY, - IGNORABLE_CXX_KEYWORD, - - /* print_token assumes that any token >= FIRST_TOKEN_WITH_VALUE may have - a meaningful value to be printed. */ - FIRST_TOKEN_WITH_VALUE = USER_GTY -}; - - -/* Level for verbose messages, e.g. output file generation... */ -extern int verbosity_level; /* (-v) program argument. */ - -/* For debugging purposes we provide two flags. */ - -/* Dump everything to understand gengtype's state. Might be useful to - gengtype users. */ -extern int do_dump; /* (-d) program argument. */ - -/* Trace the execution by many DBGPRINTF (with the position inside - gengtype source code). Only useful to debug gengtype itself. */ -extern int do_debug; /* (-D) program argument. */ - -#if ENABLE_CHECKING -#define DBGPRINTF(Fmt,...) do {if (do_debug) \ - fprintf (stderr, "%s:%d: " Fmt "\n", \ - lbasename (__FILE__),__LINE__, ##__VA_ARGS__);} while (0) -void dbgprint_count_type_at (const char *, int, const char *, type_p); -#define DBGPRINT_COUNT_TYPE(Msg,Ty) do {if (do_debug) \ - dbgprint_count_type_at (__FILE__, __LINE__, Msg, Ty);}while (0) -#else -#define DBGPRINTF(Fmt,...) do {/*nodbgrintf*/} while (0) -#define DBGPRINT_COUNT_TYPE(Msg,Ty) do{/*nodbgprint_count_type*/}while (0) -#endif /*ENABLE_CHECKING */ - -#define FOR_ALL_INHERITED_FIELDS(TYPE, FIELD_VAR) \ - for (type_p sub = (TYPE); sub; sub = sub->u.s.base_class) \ - for (FIELD_VAR = sub->u.s.fields; FIELD_VAR; FIELD_VAR = FIELD_VAR->next) - -extern bool -opts_have (options_p opts, const char *str); - - -#endif diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/genrtl.h b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/genrtl.h deleted file mode 100644 index 30e36ec..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/genrtl.h +++ /dev/null @@ -1,1229 +0,0 @@ -/* Generated automatically by gengenrtl from rtl.def. */ - -#ifndef GCC_GENRTL_H -#define GCC_GENRTL_H - -#include "statistics.h" - -static inline rtx -gen_rtx_fmt_0_stat (RTX_CODE code, machine_mode mode MEM_STAT_DECL) -{ - rtx rt; - rt = rtx_alloc_stat (code PASS_MEM_STAT); - - PUT_MODE (rt, mode); - X0EXP (rt, 0) = NULL_RTX; - - return rt; -} - -#define gen_rtx_fmt_0(c, m)\ - gen_rtx_fmt_0_stat (c, m MEM_STAT_INFO) - -static inline rtx -gen_rtx_fmt_ee_stat (RTX_CODE code, machine_mode mode, - rtx arg0, - rtx arg1 MEM_STAT_DECL) -{ - rtx rt; - rt = rtx_alloc_stat (code PASS_MEM_STAT); - - PUT_MODE (rt, mode); - XEXP (rt, 0) = arg0; - XEXP (rt, 1) = arg1; - - return rt; -} - -#define gen_rtx_fmt_ee(c, m, p0, p1)\ - gen_rtx_fmt_ee_stat (c, m, p0, p1 MEM_STAT_INFO) - -static inline rtx -gen_rtx_fmt_ue_stat (RTX_CODE code, machine_mode mode, - rtx arg0, - rtx arg1 MEM_STAT_DECL) -{ - rtx rt; - rt = rtx_alloc_stat (code PASS_MEM_STAT); - - PUT_MODE (rt, mode); - XEXP (rt, 0) = arg0; - XEXP (rt, 1) = arg1; - - return rt; -} - -#define gen_rtx_fmt_ue(c, m, p0, p1)\ - gen_rtx_fmt_ue_stat (c, m, p0, p1 MEM_STAT_INFO) - -static inline rtx -gen_rtx_fmt_ie_stat (RTX_CODE code, machine_mode mode, - int arg0, - rtx arg1 MEM_STAT_DECL) -{ - rtx rt; - rt = rtx_alloc_stat (code PASS_MEM_STAT); - - PUT_MODE (rt, mode); - XINT (rt, 0) = arg0; - XEXP (rt, 1) = arg1; - - return rt; -} - -#define gen_rtx_fmt_ie(c, m, p0, p1)\ - gen_rtx_fmt_ie_stat (c, m, p0, p1 MEM_STAT_INFO) - -static inline rtx -gen_rtx_fmt_E_stat (RTX_CODE code, machine_mode mode, - rtvec arg0 MEM_STAT_DECL) -{ - rtx rt; - rt = rtx_alloc_stat (code PASS_MEM_STAT); - - PUT_MODE (rt, mode); - XVEC (rt, 0) = arg0; - - return rt; -} - -#define gen_rtx_fmt_E(c, m, p0)\ - gen_rtx_fmt_E_stat (c, m, p0 MEM_STAT_INFO) - -static inline rtx -gen_rtx_fmt_i_stat (RTX_CODE code, machine_mode mode, - int arg0 MEM_STAT_DECL) -{ - rtx rt; - rt = rtx_alloc_stat (code PASS_MEM_STAT); - - PUT_MODE (rt, mode); - XINT (rt, 0) = arg0; - - return rt; -} - -#define gen_rtx_fmt_i(c, m, p0)\ - gen_rtx_fmt_i_stat (c, m, p0 MEM_STAT_INFO) - -static inline rtx -gen_rtx_fmt_uuBeiie_stat (RTX_CODE code, machine_mode mode, - rtx arg0, - rtx arg1, - basic_block arg2, - rtx arg3, - int arg4, - int arg5, - rtx arg6 MEM_STAT_DECL) -{ - rtx rt; - rt = rtx_alloc_stat (code PASS_MEM_STAT); - - PUT_MODE (rt, mode); - XEXP (rt, 0) = arg0; - XEXP (rt, 1) = arg1; - XBBDEF (rt, 2) = arg2; - XEXP (rt, 3) = arg3; - XINT (rt, 4) = arg4; - XINT (rt, 5) = arg5; - XEXP (rt, 6) = arg6; - - return rt; -} - -#define gen_rtx_fmt_uuBeiie(c, m, p0, p1, p2, p3, p4, p5, p6)\ - gen_rtx_fmt_uuBeiie_stat (c, m, p0, p1, p2, p3, p4, p5, p6 MEM_STAT_INFO) - -static inline rtx -gen_rtx_fmt_uuBeiie0_stat (RTX_CODE code, machine_mode mode, - rtx arg0, - rtx arg1, - basic_block arg2, - rtx arg3, - int arg4, - int arg5, - rtx arg6 MEM_STAT_DECL) -{ - rtx rt; - rt = rtx_alloc_stat (code PASS_MEM_STAT); - - PUT_MODE (rt, mode); - XEXP (rt, 0) = arg0; - XEXP (rt, 1) = arg1; - XBBDEF (rt, 2) = arg2; - XEXP (rt, 3) = arg3; - XINT (rt, 4) = arg4; - XINT (rt, 5) = arg5; - XEXP (rt, 6) = arg6; - X0EXP (rt, 7) = NULL_RTX; - - return rt; -} - -#define gen_rtx_fmt_uuBeiie0(c, m, p0, p1, p2, p3, p4, p5, p6)\ - gen_rtx_fmt_uuBeiie0_stat (c, m, p0, p1, p2, p3, p4, p5, p6 MEM_STAT_INFO) - -static inline rtx -gen_rtx_fmt_uuBeiiee_stat (RTX_CODE code, machine_mode mode, - rtx arg0, - rtx arg1, - basic_block arg2, - rtx arg3, - int arg4, - int arg5, - rtx arg6, - rtx arg7 MEM_STAT_DECL) -{ - rtx rt; - rt = rtx_alloc_stat (code PASS_MEM_STAT); - - PUT_MODE (rt, mode); - XEXP (rt, 0) = arg0; - XEXP (rt, 1) = arg1; - XBBDEF (rt, 2) = arg2; - XEXP (rt, 3) = arg3; - XINT (rt, 4) = arg4; - XINT (rt, 5) = arg5; - XEXP (rt, 6) = arg6; - XEXP (rt, 7) = arg7; - - return rt; -} - -#define gen_rtx_fmt_uuBeiiee(c, m, p0, p1, p2, p3, p4, p5, p6, p7)\ - gen_rtx_fmt_uuBeiiee_stat (c, m, p0, p1, p2, p3, p4, p5, p6, p7 MEM_STAT_INFO) - -static inline rtx -gen_rtx_fmt_uuBe0000_stat (RTX_CODE code, machine_mode mode, - rtx arg0, - rtx arg1, - basic_block arg2, - rtx arg3 MEM_STAT_DECL) -{ - rtx rt; - rt = rtx_alloc_stat (code PASS_MEM_STAT); - - PUT_MODE (rt, mode); - XEXP (rt, 0) = arg0; - XEXP (rt, 1) = arg1; - XBBDEF (rt, 2) = arg2; - XEXP (rt, 3) = arg3; - X0EXP (rt, 4) = NULL_RTX; - X0EXP (rt, 5) = NULL_RTX; - X0EXP (rt, 6) = NULL_RTX; - X0EXP (rt, 7) = NULL_RTX; - - return rt; -} - -#define gen_rtx_fmt_uuBe0000(c, m, p0, p1, p2, p3)\ - gen_rtx_fmt_uuBe0000_stat (c, m, p0, p1, p2, p3 MEM_STAT_INFO) - -static inline rtx -gen_rtx_fmt_uu00000_stat (RTX_CODE code, machine_mode mode, - rtx arg0, - rtx arg1 MEM_STAT_DECL) -{ - rtx rt; - rt = rtx_alloc_stat (code PASS_MEM_STAT); - - PUT_MODE (rt, mode); - XEXP (rt, 0) = arg0; - XEXP (rt, 1) = arg1; - X0EXP (rt, 2) = NULL_RTX; - X0EXP (rt, 3) = NULL_RTX; - X0EXP (rt, 4) = NULL_RTX; - X0EXP (rt, 5) = NULL_RTX; - X0EXP (rt, 6) = NULL_RTX; - - return rt; -} - -#define gen_rtx_fmt_uu00000(c, m, p0, p1)\ - gen_rtx_fmt_uu00000_stat (c, m, p0, p1 MEM_STAT_INFO) - -static inline rtx -gen_rtx_fmt_uuB00is_stat (RTX_CODE code, machine_mode mode, - rtx arg0, - rtx arg1, - basic_block arg2, - int arg3, - const char *arg4 MEM_STAT_DECL) -{ - rtx rt; - rt = rtx_alloc_stat (code PASS_MEM_STAT); - - PUT_MODE (rt, mode); - XEXP (rt, 0) = arg0; - XEXP (rt, 1) = arg1; - XBBDEF (rt, 2) = arg2; - X0EXP (rt, 3) = NULL_RTX; - X0EXP (rt, 4) = NULL_RTX; - XINT (rt, 5) = arg3; - XSTR (rt, 6) = arg4; - - return rt; -} - -#define gen_rtx_fmt_uuB00is(c, m, p0, p1, p2, p3, p4)\ - gen_rtx_fmt_uuB00is_stat (c, m, p0, p1, p2, p3, p4 MEM_STAT_INFO) - -static inline rtx -gen_rtx_fmt_si_stat (RTX_CODE code, machine_mode mode, - const char *arg0, - int arg1 MEM_STAT_DECL) -{ - rtx rt; - rt = rtx_alloc_stat (code PASS_MEM_STAT); - - PUT_MODE (rt, mode); - XSTR (rt, 0) = arg0; - XINT (rt, 1) = arg1; - - return rt; -} - -#define gen_rtx_fmt_si(c, m, p0, p1)\ - gen_rtx_fmt_si_stat (c, m, p0, p1 MEM_STAT_INFO) - -static inline rtx -gen_rtx_fmt_ssiEEEi_stat (RTX_CODE code, machine_mode mode, - const char *arg0, - const char *arg1, - int arg2, - rtvec arg3, - rtvec arg4, - rtvec arg5, - int arg6 MEM_STAT_DECL) -{ - rtx rt; - rt = rtx_alloc_stat (code PASS_MEM_STAT); - - PUT_MODE (rt, mode); - XSTR (rt, 0) = arg0; - XSTR (rt, 1) = arg1; - XINT (rt, 2) = arg2; - XVEC (rt, 3) = arg3; - XVEC (rt, 4) = arg4; - XVEC (rt, 5) = arg5; - XINT (rt, 6) = arg6; - - return rt; -} - -#define gen_rtx_fmt_ssiEEEi(c, m, p0, p1, p2, p3, p4, p5, p6)\ - gen_rtx_fmt_ssiEEEi_stat (c, m, p0, p1, p2, p3, p4, p5, p6 MEM_STAT_INFO) - -static inline rtx -gen_rtx_fmt_Ei_stat (RTX_CODE code, machine_mode mode, - rtvec arg0, - int arg1 MEM_STAT_DECL) -{ - rtx rt; - rt = rtx_alloc_stat (code PASS_MEM_STAT); - - PUT_MODE (rt, mode); - XVEC (rt, 0) = arg0; - XINT (rt, 1) = arg1; - - return rt; -} - -#define gen_rtx_fmt_Ei(c, m, p0, p1)\ - gen_rtx_fmt_Ei_stat (c, m, p0, p1 MEM_STAT_INFO) - -static inline rtx -gen_rtx_fmt_eEee0_stat (RTX_CODE code, machine_mode mode, - rtx arg0, - rtvec arg1, - rtx arg2, - rtx arg3 MEM_STAT_DECL) -{ - rtx rt; - rt = rtx_alloc_stat (code PASS_MEM_STAT); - - PUT_MODE (rt, mode); - XEXP (rt, 0) = arg0; - XVEC (rt, 1) = arg1; - XEXP (rt, 2) = arg2; - XEXP (rt, 3) = arg3; - X0EXP (rt, 4) = NULL_RTX; - - return rt; -} - -#define gen_rtx_fmt_eEee0(c, m, p0, p1, p2, p3)\ - gen_rtx_fmt_eEee0_stat (c, m, p0, p1, p2, p3 MEM_STAT_INFO) - -static inline rtx -gen_rtx_fmt_eee_stat (RTX_CODE code, machine_mode mode, - rtx arg0, - rtx arg1, - rtx arg2 MEM_STAT_DECL) -{ - rtx rt; - rt = rtx_alloc_stat (code PASS_MEM_STAT); - - PUT_MODE (rt, mode); - XEXP (rt, 0) = arg0; - XEXP (rt, 1) = arg1; - XEXP (rt, 2) = arg2; - - return rt; -} - -#define gen_rtx_fmt_eee(c, m, p0, p1, p2)\ - gen_rtx_fmt_eee_stat (c, m, p0, p1, p2 MEM_STAT_INFO) - -static inline rtx -gen_rtx_fmt_e_stat (RTX_CODE code, machine_mode mode, - rtx arg0 MEM_STAT_DECL) -{ - rtx rt; - rt = rtx_alloc_stat (code PASS_MEM_STAT); - - PUT_MODE (rt, mode); - XEXP (rt, 0) = arg0; - - return rt; -} - -#define gen_rtx_fmt_e(c, m, p0)\ - gen_rtx_fmt_e_stat (c, m, p0 MEM_STAT_INFO) - -static inline rtx -gen_rtx_fmt__stat (RTX_CODE code, machine_mode mode MEM_STAT_DECL) -{ - rtx rt; - rt = rtx_alloc_stat (code PASS_MEM_STAT); - - PUT_MODE (rt, mode); - - return rt; -} - -#define gen_rtx_fmt_(c, m)\ - gen_rtx_fmt__stat (c, m MEM_STAT_INFO) - -static inline rtx -gen_rtx_fmt_w_stat (RTX_CODE code, machine_mode mode, - HOST_WIDE_INT arg0 MEM_STAT_DECL) -{ - rtx rt; - rt = rtx_alloc_stat (code PASS_MEM_STAT); - - PUT_MODE (rt, mode); - XWINT (rt, 0) = arg0; - - return rt; -} - -#define gen_rtx_fmt_w(c, m, p0)\ - gen_rtx_fmt_w_stat (c, m, p0 MEM_STAT_INFO) - -static inline rtx -gen_rtx_fmt_www_stat (RTX_CODE code, machine_mode mode, - HOST_WIDE_INT arg0, - HOST_WIDE_INT arg1, - HOST_WIDE_INT arg2 MEM_STAT_DECL) -{ - rtx rt; - rt = rtx_alloc_stat (code PASS_MEM_STAT); - - PUT_MODE (rt, mode); - XWINT (rt, 0) = arg0; - XWINT (rt, 1) = arg1; - XWINT (rt, 2) = arg2; - - return rt; -} - -#define gen_rtx_fmt_www(c, m, p0, p1, p2)\ - gen_rtx_fmt_www_stat (c, m, p0, p1, p2 MEM_STAT_INFO) - -static inline rtx -gen_rtx_fmt_s_stat (RTX_CODE code, machine_mode mode, - const char *arg0 MEM_STAT_DECL) -{ - rtx rt; - rt = rtx_alloc_stat (code PASS_MEM_STAT); - - PUT_MODE (rt, mode); - XSTR (rt, 0) = arg0; - - return rt; -} - -#define gen_rtx_fmt_s(c, m, p0)\ - gen_rtx_fmt_s_stat (c, m, p0 MEM_STAT_INFO) - -static inline rtx -gen_rtx_fmt_i0_stat (RTX_CODE code, machine_mode mode, - int arg0 MEM_STAT_DECL) -{ - rtx rt; - rt = rtx_alloc_stat (code PASS_MEM_STAT); - - PUT_MODE (rt, mode); - XINT (rt, 0) = arg0; - X0EXP (rt, 1) = NULL_RTX; - - return rt; -} - -#define gen_rtx_fmt_i0(c, m, p0)\ - gen_rtx_fmt_i0_stat (c, m, p0 MEM_STAT_INFO) - -static inline rtx -gen_rtx_fmt_ei_stat (RTX_CODE code, machine_mode mode, - rtx arg0, - int arg1 MEM_STAT_DECL) -{ - rtx rt; - rt = rtx_alloc_stat (code PASS_MEM_STAT); - - PUT_MODE (rt, mode); - XEXP (rt, 0) = arg0; - XINT (rt, 1) = arg1; - - return rt; -} - -#define gen_rtx_fmt_ei(c, m, p0, p1)\ - gen_rtx_fmt_ei_stat (c, m, p0, p1 MEM_STAT_INFO) - -static inline rtx -gen_rtx_fmt_e0_stat (RTX_CODE code, machine_mode mode, - rtx arg0 MEM_STAT_DECL) -{ - rtx rt; - rt = rtx_alloc_stat (code PASS_MEM_STAT); - - PUT_MODE (rt, mode); - XEXP (rt, 0) = arg0; - X0EXP (rt, 1) = NULL_RTX; - - return rt; -} - -#define gen_rtx_fmt_e0(c, m, p0)\ - gen_rtx_fmt_e0_stat (c, m, p0 MEM_STAT_INFO) - -static inline rtx -gen_rtx_fmt_u_stat (RTX_CODE code, machine_mode mode, - rtx arg0 MEM_STAT_DECL) -{ - rtx rt; - rt = rtx_alloc_stat (code PASS_MEM_STAT); - - PUT_MODE (rt, mode); - XEXP (rt, 0) = arg0; - - return rt; -} - -#define gen_rtx_fmt_u(c, m, p0)\ - gen_rtx_fmt_u_stat (c, m, p0 MEM_STAT_INFO) - -static inline rtx -gen_rtx_fmt_s0_stat (RTX_CODE code, machine_mode mode, - const char *arg0 MEM_STAT_DECL) -{ - rtx rt; - rt = rtx_alloc_stat (code PASS_MEM_STAT); - - PUT_MODE (rt, mode); - XSTR (rt, 0) = arg0; - X0EXP (rt, 1) = NULL_RTX; - - return rt; -} - -#define gen_rtx_fmt_s0(c, m, p0)\ - gen_rtx_fmt_s0_stat (c, m, p0 MEM_STAT_INFO) - -static inline rtx -gen_rtx_fmt_te_stat (RTX_CODE code, machine_mode mode, - tree arg0, - rtx arg1 MEM_STAT_DECL) -{ - rtx rt; - rt = rtx_alloc_stat (code PASS_MEM_STAT); - - PUT_MODE (rt, mode); - XTREE (rt, 0) = arg0; - XEXP (rt, 1) = arg1; - - return rt; -} - -#define gen_rtx_fmt_te(c, m, p0, p1)\ - gen_rtx_fmt_te_stat (c, m, p0, p1 MEM_STAT_INFO) - -static inline rtx -gen_rtx_fmt_t_stat (RTX_CODE code, machine_mode mode, - tree arg0 MEM_STAT_DECL) -{ - rtx rt; - rt = rtx_alloc_stat (code PASS_MEM_STAT); - - PUT_MODE (rt, mode); - XTREE (rt, 0) = arg0; - - return rt; -} - -#define gen_rtx_fmt_t(c, m, p0)\ - gen_rtx_fmt_t_stat (c, m, p0 MEM_STAT_INFO) - -static inline rtx -gen_rtx_fmt_iss_stat (RTX_CODE code, machine_mode mode, - int arg0, - const char *arg1, - const char *arg2 MEM_STAT_DECL) -{ - rtx rt; - rt = rtx_alloc_stat (code PASS_MEM_STAT); - - PUT_MODE (rt, mode); - XINT (rt, 0) = arg0; - XSTR (rt, 1) = arg1; - XSTR (rt, 2) = arg2; - - return rt; -} - -#define gen_rtx_fmt_iss(c, m, p0, p1, p2)\ - gen_rtx_fmt_iss_stat (c, m, p0, p1, p2 MEM_STAT_INFO) - -static inline rtx -gen_rtx_fmt_is_stat (RTX_CODE code, machine_mode mode, - int arg0, - const char *arg1 MEM_STAT_DECL) -{ - rtx rt; - rt = rtx_alloc_stat (code PASS_MEM_STAT); - - PUT_MODE (rt, mode); - XINT (rt, 0) = arg0; - XSTR (rt, 1) = arg1; - - return rt; -} - -#define gen_rtx_fmt_is(c, m, p0, p1)\ - gen_rtx_fmt_is_stat (c, m, p0, p1 MEM_STAT_INFO) - -static inline rtx -gen_rtx_fmt_isE_stat (RTX_CODE code, machine_mode mode, - int arg0, - const char *arg1, - rtvec arg2 MEM_STAT_DECL) -{ - rtx rt; - rt = rtx_alloc_stat (code PASS_MEM_STAT); - - PUT_MODE (rt, mode); - XINT (rt, 0) = arg0; - XSTR (rt, 1) = arg1; - XVEC (rt, 2) = arg2; - - return rt; -} - -#define gen_rtx_fmt_isE(c, m, p0, p1, p2)\ - gen_rtx_fmt_isE_stat (c, m, p0, p1, p2 MEM_STAT_INFO) - -static inline rtx -gen_rtx_fmt_iE_stat (RTX_CODE code, machine_mode mode, - int arg0, - rtvec arg1 MEM_STAT_DECL) -{ - rtx rt; - rt = rtx_alloc_stat (code PASS_MEM_STAT); - - PUT_MODE (rt, mode); - XINT (rt, 0) = arg0; - XVEC (rt, 1) = arg1; - - return rt; -} - -#define gen_rtx_fmt_iE(c, m, p0, p1)\ - gen_rtx_fmt_iE_stat (c, m, p0, p1 MEM_STAT_INFO) - -static inline rtx -gen_rtx_fmt_ss_stat (RTX_CODE code, machine_mode mode, - const char *arg0, - const char *arg1 MEM_STAT_DECL) -{ - rtx rt; - rt = rtx_alloc_stat (code PASS_MEM_STAT); - - PUT_MODE (rt, mode); - XSTR (rt, 0) = arg0; - XSTR (rt, 1) = arg1; - - return rt; -} - -#define gen_rtx_fmt_ss(c, m, p0, p1)\ - gen_rtx_fmt_ss_stat (c, m, p0, p1 MEM_STAT_INFO) - -static inline rtx -gen_rtx_fmt_eE_stat (RTX_CODE code, machine_mode mode, - rtx arg0, - rtvec arg1 MEM_STAT_DECL) -{ - rtx rt; - rt = rtx_alloc_stat (code PASS_MEM_STAT); - - PUT_MODE (rt, mode); - XEXP (rt, 0) = arg0; - XVEC (rt, 1) = arg1; - - return rt; -} - -#define gen_rtx_fmt_eE(c, m, p0, p1)\ - gen_rtx_fmt_eE_stat (c, m, p0, p1 MEM_STAT_INFO) - -static inline rtx -gen_rtx_fmt_ses_stat (RTX_CODE code, machine_mode mode, - const char *arg0, - rtx arg1, - const char *arg2 MEM_STAT_DECL) -{ - rtx rt; - rt = rtx_alloc_stat (code PASS_MEM_STAT); - - PUT_MODE (rt, mode); - XSTR (rt, 0) = arg0; - XEXP (rt, 1) = arg1; - XSTR (rt, 2) = arg2; - - return rt; -} - -#define gen_rtx_fmt_ses(c, m, p0, p1, p2)\ - gen_rtx_fmt_ses_stat (c, m, p0, p1, p2 MEM_STAT_INFO) - -static inline rtx -gen_rtx_fmt_sss_stat (RTX_CODE code, machine_mode mode, - const char *arg0, - const char *arg1, - const char *arg2 MEM_STAT_DECL) -{ - rtx rt; - rt = rtx_alloc_stat (code PASS_MEM_STAT); - - PUT_MODE (rt, mode); - XSTR (rt, 0) = arg0; - XSTR (rt, 1) = arg1; - XSTR (rt, 2) = arg2; - - return rt; -} - -#define gen_rtx_fmt_sss(c, m, p0, p1, p2)\ - gen_rtx_fmt_sss_stat (c, m, p0, p1, p2 MEM_STAT_INFO) - -static inline rtx -gen_rtx_fmt_sse_stat (RTX_CODE code, machine_mode mode, - const char *arg0, - const char *arg1, - rtx arg2 MEM_STAT_DECL) -{ - rtx rt; - rt = rtx_alloc_stat (code PASS_MEM_STAT); - - PUT_MODE (rt, mode); - XSTR (rt, 0) = arg0; - XSTR (rt, 1) = arg1; - XEXP (rt, 2) = arg2; - - return rt; -} - -#define gen_rtx_fmt_sse(c, m, p0, p1, p2)\ - gen_rtx_fmt_sse_stat (c, m, p0, p1, p2 MEM_STAT_INFO) - -static inline rtx -gen_rtx_fmt_sies_stat (RTX_CODE code, machine_mode mode, - const char *arg0, - int arg1, - rtx arg2, - const char *arg3 MEM_STAT_DECL) -{ - rtx rt; - rt = rtx_alloc_stat (code PASS_MEM_STAT); - - PUT_MODE (rt, mode); - XSTR (rt, 0) = arg0; - XINT (rt, 1) = arg1; - XEXP (rt, 2) = arg2; - XSTR (rt, 3) = arg3; - - return rt; -} - -#define gen_rtx_fmt_sies(c, m, p0, p1, p2, p3)\ - gen_rtx_fmt_sies_stat (c, m, p0, p1, p2, p3 MEM_STAT_INFO) - -static inline rtx -gen_rtx_fmt_sE_stat (RTX_CODE code, machine_mode mode, - const char *arg0, - rtvec arg1 MEM_STAT_DECL) -{ - rtx rt; - rt = rtx_alloc_stat (code PASS_MEM_STAT); - - PUT_MODE (rt, mode); - XSTR (rt, 0) = arg0; - XVEC (rt, 1) = arg1; - - return rt; -} - -#define gen_rtx_fmt_sE(c, m, p0, p1)\ - gen_rtx_fmt_sE_stat (c, m, p0, p1 MEM_STAT_INFO) - -static inline rtx -gen_rtx_fmt_ii_stat (RTX_CODE code, machine_mode mode, - int arg0, - int arg1 MEM_STAT_DECL) -{ - rtx rt; - rt = rtx_alloc_stat (code PASS_MEM_STAT); - - PUT_MODE (rt, mode); - XINT (rt, 0) = arg0; - XINT (rt, 1) = arg1; - - return rt; -} - -#define gen_rtx_fmt_ii(c, m, p0, p1)\ - gen_rtx_fmt_ii_stat (c, m, p0, p1 MEM_STAT_INFO) - -static inline rtx -gen_rtx_fmt_Ee_stat (RTX_CODE code, machine_mode mode, - rtvec arg0, - rtx arg1 MEM_STAT_DECL) -{ - rtx rt; - rt = rtx_alloc_stat (code PASS_MEM_STAT); - - PUT_MODE (rt, mode); - XVEC (rt, 0) = arg0; - XEXP (rt, 1) = arg1; - - return rt; -} - -#define gen_rtx_fmt_Ee(c, m, p0, p1)\ - gen_rtx_fmt_Ee_stat (c, m, p0, p1 MEM_STAT_INFO) - -static inline rtx -gen_rtx_fmt_sEsE_stat (RTX_CODE code, machine_mode mode, - const char *arg0, - rtvec arg1, - const char *arg2, - rtvec arg3 MEM_STAT_DECL) -{ - rtx rt; - rt = rtx_alloc_stat (code PASS_MEM_STAT); - - PUT_MODE (rt, mode); - XSTR (rt, 0) = arg0; - XVEC (rt, 1) = arg1; - XSTR (rt, 2) = arg2; - XVEC (rt, 3) = arg3; - - return rt; -} - -#define gen_rtx_fmt_sEsE(c, m, p0, p1, p2, p3)\ - gen_rtx_fmt_sEsE_stat (c, m, p0, p1, p2, p3 MEM_STAT_INFO) - -static inline rtx -gen_rtx_fmt_ssss_stat (RTX_CODE code, machine_mode mode, - const char *arg0, - const char *arg1, - const char *arg2, - const char *arg3 MEM_STAT_DECL) -{ - rtx rt; - rt = rtx_alloc_stat (code PASS_MEM_STAT); - - PUT_MODE (rt, mode); - XSTR (rt, 0) = arg0; - XSTR (rt, 1) = arg1; - XSTR (rt, 2) = arg2; - XSTR (rt, 3) = arg3; - - return rt; -} - -#define gen_rtx_fmt_ssss(c, m, p0, p1, p2, p3)\ - gen_rtx_fmt_ssss_stat (c, m, p0, p1, p2, p3 MEM_STAT_INFO) - - -#define gen_rtx_VALUE(MODE) \ - gen_rtx_fmt_0 (VALUE, (MODE)) -#define gen_rtx_DEBUG_EXPR(MODE) \ - gen_rtx_fmt_0 (DEBUG_EXPR, (MODE)) -#define gen_rtx_raw_EXPR_LIST(MODE, ARG0, ARG1) \ - gen_rtx_fmt_ee (EXPR_LIST, (MODE), (ARG0), (ARG1)) -#define gen_rtx_raw_INSN_LIST(MODE, ARG0, ARG1) \ - gen_rtx_fmt_ue (INSN_LIST, (MODE), (ARG0), (ARG1)) -#define gen_rtx_INT_LIST(MODE, ARG0, ARG1) \ - gen_rtx_fmt_ie (INT_LIST, (MODE), (ARG0), (ARG1)) -#define gen_rtx_SEQUENCE(MODE, ARG0) \ - gen_rtx_fmt_E (SEQUENCE, (MODE), (ARG0)) -#define gen_rtx_ADDRESS(MODE, ARG0) \ - gen_rtx_fmt_i (ADDRESS, (MODE), (ARG0)) -#define gen_rtx_DEBUG_INSN(MODE, ARG0, ARG1, ARG2, ARG3, ARG4, ARG5, ARG6) \ - gen_rtx_fmt_uuBeiie (DEBUG_INSN, (MODE), (ARG0), (ARG1), (ARG2), (ARG3), (ARG4), (ARG5), (ARG6)) -#define gen_rtx_raw_INSN(MODE, ARG0, ARG1, ARG2, ARG3, ARG4, ARG5, ARG6) \ - gen_rtx_fmt_uuBeiie (INSN, (MODE), (ARG0), (ARG1), (ARG2), (ARG3), (ARG4), (ARG5), (ARG6)) -#define gen_rtx_JUMP_INSN(MODE, ARG0, ARG1, ARG2, ARG3, ARG4, ARG5, ARG6) \ - gen_rtx_fmt_uuBeiie0 (JUMP_INSN, (MODE), (ARG0), (ARG1), (ARG2), (ARG3), (ARG4), (ARG5), (ARG6)) -#define gen_rtx_CALL_INSN(MODE, ARG0, ARG1, ARG2, ARG3, ARG4, ARG5, ARG6, ARG7) \ - gen_rtx_fmt_uuBeiiee (CALL_INSN, (MODE), (ARG0), (ARG1), (ARG2), (ARG3), (ARG4), (ARG5), (ARG6), (ARG7)) -#define gen_rtx_JUMP_TABLE_DATA(MODE, ARG0, ARG1, ARG2, ARG3) \ - gen_rtx_fmt_uuBe0000 (JUMP_TABLE_DATA, (MODE), (ARG0), (ARG1), (ARG2), (ARG3)) -#define gen_rtx_BARRIER(MODE, ARG0, ARG1) \ - gen_rtx_fmt_uu00000 (BARRIER, (MODE), (ARG0), (ARG1)) -#define gen_rtx_CODE_LABEL(MODE, ARG0, ARG1, ARG2, ARG3, ARG4) \ - gen_rtx_fmt_uuB00is (CODE_LABEL, (MODE), (ARG0), (ARG1), (ARG2), (ARG3), (ARG4)) -#define gen_rtx_COND_EXEC(MODE, ARG0, ARG1) \ - gen_rtx_fmt_ee (COND_EXEC, (MODE), (ARG0), (ARG1)) -#define gen_rtx_PARALLEL(MODE, ARG0) \ - gen_rtx_fmt_E (PARALLEL, (MODE), (ARG0)) -#define gen_rtx_ASM_INPUT(MODE, ARG0, ARG1) \ - gen_rtx_fmt_si (ASM_INPUT, (MODE), (ARG0), (ARG1)) -#define gen_rtx_ASM_OPERANDS(MODE, ARG0, ARG1, ARG2, ARG3, ARG4, ARG5, ARG6) \ - gen_rtx_fmt_ssiEEEi (ASM_OPERANDS, (MODE), (ARG0), (ARG1), (ARG2), (ARG3), (ARG4), (ARG5), (ARG6)) -#define gen_rtx_UNSPEC(MODE, ARG0, ARG1) \ - gen_rtx_fmt_Ei (UNSPEC, (MODE), (ARG0), (ARG1)) -#define gen_rtx_UNSPEC_VOLATILE(MODE, ARG0, ARG1) \ - gen_rtx_fmt_Ei (UNSPEC_VOLATILE, (MODE), (ARG0), (ARG1)) -#define gen_rtx_ADDR_VEC(MODE, ARG0) \ - gen_rtx_fmt_E (ADDR_VEC, (MODE), (ARG0)) -#define gen_rtx_ADDR_DIFF_VEC(MODE, ARG0, ARG1, ARG2, ARG3) \ - gen_rtx_fmt_eEee0 (ADDR_DIFF_VEC, (MODE), (ARG0), (ARG1), (ARG2), (ARG3)) -#define gen_rtx_PREFETCH(MODE, ARG0, ARG1, ARG2) \ - gen_rtx_fmt_eee (PREFETCH, (MODE), (ARG0), (ARG1), (ARG2)) -#define gen_rtx_SET(MODE, ARG0, ARG1) \ - gen_rtx_fmt_ee (SET, (MODE), (ARG0), (ARG1)) -#define gen_rtx_USE(MODE, ARG0) \ - gen_rtx_fmt_e (USE, (MODE), (ARG0)) -#define gen_rtx_CLOBBER(MODE, ARG0) \ - gen_rtx_fmt_e (CLOBBER, (MODE), (ARG0)) -#define gen_rtx_CALL(MODE, ARG0, ARG1) \ - gen_rtx_fmt_ee (CALL, (MODE), (ARG0), (ARG1)) -#define gen_rtx_raw_RETURN(MODE) \ - gen_rtx_fmt_ (RETURN, (MODE)) -#define gen_rtx_raw_SIMPLE_RETURN(MODE) \ - gen_rtx_fmt_ (SIMPLE_RETURN, (MODE)) -#define gen_rtx_EH_RETURN(MODE) \ - gen_rtx_fmt_ (EH_RETURN, (MODE)) -#define gen_rtx_TRAP_IF(MODE, ARG0, ARG1) \ - gen_rtx_fmt_ee (TRAP_IF, (MODE), (ARG0), (ARG1)) -#define gen_rtx_raw_CONST_INT(MODE, ARG0) \ - gen_rtx_fmt_w (CONST_INT, (MODE), (ARG0)) -#define gen_rtx_raw_CONST_VECTOR(MODE, ARG0) \ - gen_rtx_fmt_E (CONST_VECTOR, (MODE), (ARG0)) -#define gen_rtx_CONST_STRING(MODE, ARG0) \ - gen_rtx_fmt_s (CONST_STRING, (MODE), (ARG0)) -#define gen_rtx_CONST(MODE, ARG0) \ - gen_rtx_fmt_e (CONST, (MODE), (ARG0)) -#define gen_rtx_raw_PC(MODE) \ - gen_rtx_fmt_ (PC, (MODE)) -#define gen_rtx_raw_REG(MODE, ARG0) \ - gen_rtx_fmt_i0 (REG, (MODE), (ARG0)) -#define gen_rtx_SCRATCH(MODE) \ - gen_rtx_fmt_ (SCRATCH, (MODE)) -#define gen_rtx_raw_SUBREG(MODE, ARG0, ARG1) \ - gen_rtx_fmt_ei (SUBREG, (MODE), (ARG0), (ARG1)) -#define gen_rtx_STRICT_LOW_PART(MODE, ARG0) \ - gen_rtx_fmt_e (STRICT_LOW_PART, (MODE), (ARG0)) -#define gen_rtx_CONCAT(MODE, ARG0, ARG1) \ - gen_rtx_fmt_ee (CONCAT, (MODE), (ARG0), (ARG1)) -#define gen_rtx_CONCATN(MODE, ARG0) \ - gen_rtx_fmt_E (CONCATN, (MODE), (ARG0)) -#define gen_rtx_raw_MEM(MODE, ARG0) \ - gen_rtx_fmt_e0 (MEM, (MODE), (ARG0)) -#define gen_rtx_LABEL_REF(MODE, ARG0) \ - gen_rtx_fmt_u (LABEL_REF, (MODE), (ARG0)) -#define gen_rtx_SYMBOL_REF(MODE, ARG0) \ - gen_rtx_fmt_s0 (SYMBOL_REF, (MODE), (ARG0)) -#define gen_rtx_raw_CC0(MODE) \ - gen_rtx_fmt_ (CC0, (MODE)) -#define gen_rtx_IF_THEN_ELSE(MODE, ARG0, ARG1, ARG2) \ - gen_rtx_fmt_eee (IF_THEN_ELSE, (MODE), (ARG0), (ARG1), (ARG2)) -#define gen_rtx_COMPARE(MODE, ARG0, ARG1) \ - gen_rtx_fmt_ee (COMPARE, (MODE), (ARG0), (ARG1)) -#define gen_rtx_PLUS(MODE, ARG0, ARG1) \ - gen_rtx_fmt_ee (PLUS, (MODE), (ARG0), (ARG1)) -#define gen_rtx_MINUS(MODE, ARG0, ARG1) \ - gen_rtx_fmt_ee (MINUS, (MODE), (ARG0), (ARG1)) -#define gen_rtx_NEG(MODE, ARG0) \ - gen_rtx_fmt_e (NEG, (MODE), (ARG0)) -#define gen_rtx_MULT(MODE, ARG0, ARG1) \ - gen_rtx_fmt_ee (MULT, (MODE), (ARG0), (ARG1)) -#define gen_rtx_SS_MULT(MODE, ARG0, ARG1) \ - gen_rtx_fmt_ee (SS_MULT, (MODE), (ARG0), (ARG1)) -#define gen_rtx_US_MULT(MODE, ARG0, ARG1) \ - gen_rtx_fmt_ee (US_MULT, (MODE), (ARG0), (ARG1)) -#define gen_rtx_DIV(MODE, ARG0, ARG1) \ - gen_rtx_fmt_ee (DIV, (MODE), (ARG0), (ARG1)) -#define gen_rtx_SS_DIV(MODE, ARG0, ARG1) \ - gen_rtx_fmt_ee (SS_DIV, (MODE), (ARG0), (ARG1)) -#define gen_rtx_US_DIV(MODE, ARG0, ARG1) \ - gen_rtx_fmt_ee (US_DIV, (MODE), (ARG0), (ARG1)) -#define gen_rtx_MOD(MODE, ARG0, ARG1) \ - gen_rtx_fmt_ee (MOD, (MODE), (ARG0), (ARG1)) -#define gen_rtx_UDIV(MODE, ARG0, ARG1) \ - gen_rtx_fmt_ee (UDIV, (MODE), (ARG0), (ARG1)) -#define gen_rtx_UMOD(MODE, ARG0, ARG1) \ - gen_rtx_fmt_ee (UMOD, (MODE), (ARG0), (ARG1)) -#define gen_rtx_AND(MODE, ARG0, ARG1) \ - gen_rtx_fmt_ee (AND, (MODE), (ARG0), (ARG1)) -#define gen_rtx_IOR(MODE, ARG0, ARG1) \ - gen_rtx_fmt_ee (IOR, (MODE), (ARG0), (ARG1)) -#define gen_rtx_XOR(MODE, ARG0, ARG1) \ - gen_rtx_fmt_ee (XOR, (MODE), (ARG0), (ARG1)) -#define gen_rtx_NOT(MODE, ARG0) \ - gen_rtx_fmt_e (NOT, (MODE), (ARG0)) -#define gen_rtx_ASHIFT(MODE, ARG0, ARG1) \ - gen_rtx_fmt_ee (ASHIFT, (MODE), (ARG0), (ARG1)) -#define gen_rtx_ROTATE(MODE, ARG0, ARG1) \ - gen_rtx_fmt_ee (ROTATE, (MODE), (ARG0), (ARG1)) -#define gen_rtx_ASHIFTRT(MODE, ARG0, ARG1) \ - gen_rtx_fmt_ee (ASHIFTRT, (MODE), (ARG0), (ARG1)) -#define gen_rtx_LSHIFTRT(MODE, ARG0, ARG1) \ - gen_rtx_fmt_ee (LSHIFTRT, (MODE), (ARG0), (ARG1)) -#define gen_rtx_ROTATERT(MODE, ARG0, ARG1) \ - gen_rtx_fmt_ee (ROTATERT, (MODE), (ARG0), (ARG1)) -#define gen_rtx_SMIN(MODE, ARG0, ARG1) \ - gen_rtx_fmt_ee (SMIN, (MODE), (ARG0), (ARG1)) -#define gen_rtx_SMAX(MODE, ARG0, ARG1) \ - gen_rtx_fmt_ee (SMAX, (MODE), (ARG0), (ARG1)) -#define gen_rtx_UMIN(MODE, ARG0, ARG1) \ - gen_rtx_fmt_ee (UMIN, (MODE), (ARG0), (ARG1)) -#define gen_rtx_UMAX(MODE, ARG0, ARG1) \ - gen_rtx_fmt_ee (UMAX, (MODE), (ARG0), (ARG1)) -#define gen_rtx_PRE_DEC(MODE, ARG0) \ - gen_rtx_fmt_e (PRE_DEC, (MODE), (ARG0)) -#define gen_rtx_PRE_INC(MODE, ARG0) \ - gen_rtx_fmt_e (PRE_INC, (MODE), (ARG0)) -#define gen_rtx_POST_DEC(MODE, ARG0) \ - gen_rtx_fmt_e (POST_DEC, (MODE), (ARG0)) -#define gen_rtx_POST_INC(MODE, ARG0) \ - gen_rtx_fmt_e (POST_INC, (MODE), (ARG0)) -#define gen_rtx_PRE_MODIFY(MODE, ARG0, ARG1) \ - gen_rtx_fmt_ee (PRE_MODIFY, (MODE), (ARG0), (ARG1)) -#define gen_rtx_POST_MODIFY(MODE, ARG0, ARG1) \ - gen_rtx_fmt_ee (POST_MODIFY, (MODE), (ARG0), (ARG1)) -#define gen_rtx_NE(MODE, ARG0, ARG1) \ - gen_rtx_fmt_ee (NE, (MODE), (ARG0), (ARG1)) -#define gen_rtx_EQ(MODE, ARG0, ARG1) \ - gen_rtx_fmt_ee (EQ, (MODE), (ARG0), (ARG1)) -#define gen_rtx_GE(MODE, ARG0, ARG1) \ - gen_rtx_fmt_ee (GE, (MODE), (ARG0), (ARG1)) -#define gen_rtx_GT(MODE, ARG0, ARG1) \ - gen_rtx_fmt_ee (GT, (MODE), (ARG0), (ARG1)) -#define gen_rtx_LE(MODE, ARG0, ARG1) \ - gen_rtx_fmt_ee (LE, (MODE), (ARG0), (ARG1)) -#define gen_rtx_LT(MODE, ARG0, ARG1) \ - gen_rtx_fmt_ee (LT, (MODE), (ARG0), (ARG1)) -#define gen_rtx_GEU(MODE, ARG0, ARG1) \ - gen_rtx_fmt_ee (GEU, (MODE), (ARG0), (ARG1)) -#define gen_rtx_GTU(MODE, ARG0, ARG1) \ - gen_rtx_fmt_ee (GTU, (MODE), (ARG0), (ARG1)) -#define gen_rtx_LEU(MODE, ARG0, ARG1) \ - gen_rtx_fmt_ee (LEU, (MODE), (ARG0), (ARG1)) -#define gen_rtx_LTU(MODE, ARG0, ARG1) \ - gen_rtx_fmt_ee (LTU, (MODE), (ARG0), (ARG1)) -#define gen_rtx_UNORDERED(MODE, ARG0, ARG1) \ - gen_rtx_fmt_ee (UNORDERED, (MODE), (ARG0), (ARG1)) -#define gen_rtx_ORDERED(MODE, ARG0, ARG1) \ - gen_rtx_fmt_ee (ORDERED, (MODE), (ARG0), (ARG1)) -#define gen_rtx_UNEQ(MODE, ARG0, ARG1) \ - gen_rtx_fmt_ee (UNEQ, (MODE), (ARG0), (ARG1)) -#define gen_rtx_UNGE(MODE, ARG0, ARG1) \ - gen_rtx_fmt_ee (UNGE, (MODE), (ARG0), (ARG1)) -#define gen_rtx_UNGT(MODE, ARG0, ARG1) \ - gen_rtx_fmt_ee (UNGT, (MODE), (ARG0), (ARG1)) -#define gen_rtx_UNLE(MODE, ARG0, ARG1) \ - gen_rtx_fmt_ee (UNLE, (MODE), (ARG0), (ARG1)) -#define gen_rtx_UNLT(MODE, ARG0, ARG1) \ - gen_rtx_fmt_ee (UNLT, (MODE), (ARG0), (ARG1)) -#define gen_rtx_LTGT(MODE, ARG0, ARG1) \ - gen_rtx_fmt_ee (LTGT, (MODE), (ARG0), (ARG1)) -#define gen_rtx_SIGN_EXTEND(MODE, ARG0) \ - gen_rtx_fmt_e (SIGN_EXTEND, (MODE), (ARG0)) -#define gen_rtx_ZERO_EXTEND(MODE, ARG0) \ - gen_rtx_fmt_e (ZERO_EXTEND, (MODE), (ARG0)) -#define gen_rtx_TRUNCATE(MODE, ARG0) \ - gen_rtx_fmt_e (TRUNCATE, (MODE), (ARG0)) -#define gen_rtx_FLOAT_EXTEND(MODE, ARG0) \ - gen_rtx_fmt_e (FLOAT_EXTEND, (MODE), (ARG0)) -#define gen_rtx_FLOAT_TRUNCATE(MODE, ARG0) \ - gen_rtx_fmt_e (FLOAT_TRUNCATE, (MODE), (ARG0)) -#define gen_rtx_FLOAT(MODE, ARG0) \ - gen_rtx_fmt_e (FLOAT, (MODE), (ARG0)) -#define gen_rtx_FIX(MODE, ARG0) \ - gen_rtx_fmt_e (FIX, (MODE), (ARG0)) -#define gen_rtx_UNSIGNED_FLOAT(MODE, ARG0) \ - gen_rtx_fmt_e (UNSIGNED_FLOAT, (MODE), (ARG0)) -#define gen_rtx_UNSIGNED_FIX(MODE, ARG0) \ - gen_rtx_fmt_e (UNSIGNED_FIX, (MODE), (ARG0)) -#define gen_rtx_FRACT_CONVERT(MODE, ARG0) \ - gen_rtx_fmt_e (FRACT_CONVERT, (MODE), (ARG0)) -#define gen_rtx_UNSIGNED_FRACT_CONVERT(MODE, ARG0) \ - gen_rtx_fmt_e (UNSIGNED_FRACT_CONVERT, (MODE), (ARG0)) -#define gen_rtx_SAT_FRACT(MODE, ARG0) \ - gen_rtx_fmt_e (SAT_FRACT, (MODE), (ARG0)) -#define gen_rtx_UNSIGNED_SAT_FRACT(MODE, ARG0) \ - gen_rtx_fmt_e (UNSIGNED_SAT_FRACT, (MODE), (ARG0)) -#define gen_rtx_ABS(MODE, ARG0) \ - gen_rtx_fmt_e (ABS, (MODE), (ARG0)) -#define gen_rtx_SQRT(MODE, ARG0) \ - gen_rtx_fmt_e (SQRT, (MODE), (ARG0)) -#define gen_rtx_BSWAP(MODE, ARG0) \ - gen_rtx_fmt_e (BSWAP, (MODE), (ARG0)) -#define gen_rtx_FFS(MODE, ARG0) \ - gen_rtx_fmt_e (FFS, (MODE), (ARG0)) -#define gen_rtx_CLRSB(MODE, ARG0) \ - gen_rtx_fmt_e (CLRSB, (MODE), (ARG0)) -#define gen_rtx_CLZ(MODE, ARG0) \ - gen_rtx_fmt_e (CLZ, (MODE), (ARG0)) -#define gen_rtx_CTZ(MODE, ARG0) \ - gen_rtx_fmt_e (CTZ, (MODE), (ARG0)) -#define gen_rtx_POPCOUNT(MODE, ARG0) \ - gen_rtx_fmt_e (POPCOUNT, (MODE), (ARG0)) -#define gen_rtx_PARITY(MODE, ARG0) \ - gen_rtx_fmt_e (PARITY, (MODE), (ARG0)) -#define gen_rtx_SIGN_EXTRACT(MODE, ARG0, ARG1, ARG2) \ - gen_rtx_fmt_eee (SIGN_EXTRACT, (MODE), (ARG0), (ARG1), (ARG2)) -#define gen_rtx_ZERO_EXTRACT(MODE, ARG0, ARG1, ARG2) \ - gen_rtx_fmt_eee (ZERO_EXTRACT, (MODE), (ARG0), (ARG1), (ARG2)) -#define gen_rtx_HIGH(MODE, ARG0) \ - gen_rtx_fmt_e (HIGH, (MODE), (ARG0)) -#define gen_rtx_LO_SUM(MODE, ARG0, ARG1) \ - gen_rtx_fmt_ee (LO_SUM, (MODE), (ARG0), (ARG1)) -#define gen_rtx_VEC_MERGE(MODE, ARG0, ARG1, ARG2) \ - gen_rtx_fmt_eee (VEC_MERGE, (MODE), (ARG0), (ARG1), (ARG2)) -#define gen_rtx_VEC_SELECT(MODE, ARG0, ARG1) \ - gen_rtx_fmt_ee (VEC_SELECT, (MODE), (ARG0), (ARG1)) -#define gen_rtx_VEC_CONCAT(MODE, ARG0, ARG1) \ - gen_rtx_fmt_ee (VEC_CONCAT, (MODE), (ARG0), (ARG1)) -#define gen_rtx_VEC_DUPLICATE(MODE, ARG0) \ - gen_rtx_fmt_e (VEC_DUPLICATE, (MODE), (ARG0)) -#define gen_rtx_SS_PLUS(MODE, ARG0, ARG1) \ - gen_rtx_fmt_ee (SS_PLUS, (MODE), (ARG0), (ARG1)) -#define gen_rtx_US_PLUS(MODE, ARG0, ARG1) \ - gen_rtx_fmt_ee (US_PLUS, (MODE), (ARG0), (ARG1)) -#define gen_rtx_SS_MINUS(MODE, ARG0, ARG1) \ - gen_rtx_fmt_ee (SS_MINUS, (MODE), (ARG0), (ARG1)) -#define gen_rtx_SS_NEG(MODE, ARG0) \ - gen_rtx_fmt_e (SS_NEG, (MODE), (ARG0)) -#define gen_rtx_US_NEG(MODE, ARG0) \ - gen_rtx_fmt_e (US_NEG, (MODE), (ARG0)) -#define gen_rtx_SS_ABS(MODE, ARG0) \ - gen_rtx_fmt_e (SS_ABS, (MODE), (ARG0)) -#define gen_rtx_SS_ASHIFT(MODE, ARG0, ARG1) \ - gen_rtx_fmt_ee (SS_ASHIFT, (MODE), (ARG0), (ARG1)) -#define gen_rtx_US_ASHIFT(MODE, ARG0, ARG1) \ - gen_rtx_fmt_ee (US_ASHIFT, (MODE), (ARG0), (ARG1)) -#define gen_rtx_US_MINUS(MODE, ARG0, ARG1) \ - gen_rtx_fmt_ee (US_MINUS, (MODE), (ARG0), (ARG1)) -#define gen_rtx_SS_TRUNCATE(MODE, ARG0) \ - gen_rtx_fmt_e (SS_TRUNCATE, (MODE), (ARG0)) -#define gen_rtx_US_TRUNCATE(MODE, ARG0) \ - gen_rtx_fmt_e (US_TRUNCATE, (MODE), (ARG0)) -#define gen_rtx_FMA(MODE, ARG0, ARG1, ARG2) \ - gen_rtx_fmt_eee (FMA, (MODE), (ARG0), (ARG1), (ARG2)) -#define gen_rtx_DEBUG_IMPLICIT_PTR(MODE, ARG0) \ - gen_rtx_fmt_t (DEBUG_IMPLICIT_PTR, (MODE), (ARG0)) -#define gen_rtx_ENTRY_VALUE(MODE) \ - gen_rtx_fmt_0 (ENTRY_VALUE, (MODE)) -#define gen_rtx_DEBUG_PARAMETER_REF(MODE, ARG0) \ - gen_rtx_fmt_t (DEBUG_PARAMETER_REF, (MODE), (ARG0)) -#define gen_rtx_MATCH_OPERAND(MODE, ARG0, ARG1, ARG2) \ - gen_rtx_fmt_iss (MATCH_OPERAND, (MODE), (ARG0), (ARG1), (ARG2)) -#define gen_rtx_MATCH_SCRATCH(MODE, ARG0, ARG1) \ - gen_rtx_fmt_is (MATCH_SCRATCH, (MODE), (ARG0), (ARG1)) -#define gen_rtx_MATCH_OPERATOR(MODE, ARG0, ARG1, ARG2) \ - gen_rtx_fmt_isE (MATCH_OPERATOR, (MODE), (ARG0), (ARG1), (ARG2)) -#define gen_rtx_MATCH_PARALLEL(MODE, ARG0, ARG1, ARG2) \ - gen_rtx_fmt_isE (MATCH_PARALLEL, (MODE), (ARG0), (ARG1), (ARG2)) -#define gen_rtx_MATCH_DUP(MODE, ARG0) \ - gen_rtx_fmt_i (MATCH_DUP, (MODE), (ARG0)) -#define gen_rtx_MATCH_OP_DUP(MODE, ARG0, ARG1) \ - gen_rtx_fmt_iE (MATCH_OP_DUP, (MODE), (ARG0), (ARG1)) -#define gen_rtx_MATCH_PAR_DUP(MODE, ARG0, ARG1) \ - gen_rtx_fmt_iE (MATCH_PAR_DUP, (MODE), (ARG0), (ARG1)) -#define gen_rtx_MATCH_CODE(MODE, ARG0, ARG1) \ - gen_rtx_fmt_ss (MATCH_CODE, (MODE), (ARG0), (ARG1)) -#define gen_rtx_MATCH_TEST(MODE, ARG0) \ - gen_rtx_fmt_s (MATCH_TEST, (MODE), (ARG0)) -#define gen_rtx_DEFINE_DELAY(MODE, ARG0, ARG1) \ - gen_rtx_fmt_eE (DEFINE_DELAY, (MODE), (ARG0), (ARG1)) -#define gen_rtx_DEFINE_PREDICATE(MODE, ARG0, ARG1, ARG2) \ - gen_rtx_fmt_ses (DEFINE_PREDICATE, (MODE), (ARG0), (ARG1), (ARG2)) -#define gen_rtx_DEFINE_SPECIAL_PREDICATE(MODE, ARG0, ARG1, ARG2) \ - gen_rtx_fmt_ses (DEFINE_SPECIAL_PREDICATE, (MODE), (ARG0), (ARG1), (ARG2)) -#define gen_rtx_DEFINE_REGISTER_CONSTRAINT(MODE, ARG0, ARG1, ARG2) \ - gen_rtx_fmt_sss (DEFINE_REGISTER_CONSTRAINT, (MODE), (ARG0), (ARG1), (ARG2)) -#define gen_rtx_DEFINE_CONSTRAINT(MODE, ARG0, ARG1, ARG2) \ - gen_rtx_fmt_sse (DEFINE_CONSTRAINT, (MODE), (ARG0), (ARG1), (ARG2)) -#define gen_rtx_DEFINE_MEMORY_CONSTRAINT(MODE, ARG0, ARG1, ARG2) \ - gen_rtx_fmt_sse (DEFINE_MEMORY_CONSTRAINT, (MODE), (ARG0), (ARG1), (ARG2)) -#define gen_rtx_DEFINE_ADDRESS_CONSTRAINT(MODE, ARG0, ARG1, ARG2) \ - gen_rtx_fmt_sse (DEFINE_ADDRESS_CONSTRAINT, (MODE), (ARG0), (ARG1), (ARG2)) -#define gen_rtx_EXCLUSION_SET(MODE, ARG0, ARG1) \ - gen_rtx_fmt_ss (EXCLUSION_SET, (MODE), (ARG0), (ARG1)) -#define gen_rtx_PRESENCE_SET(MODE, ARG0, ARG1) \ - gen_rtx_fmt_ss (PRESENCE_SET, (MODE), (ARG0), (ARG1)) -#define gen_rtx_FINAL_PRESENCE_SET(MODE, ARG0, ARG1) \ - gen_rtx_fmt_ss (FINAL_PRESENCE_SET, (MODE), (ARG0), (ARG1)) -#define gen_rtx_ABSENCE_SET(MODE, ARG0, ARG1) \ - gen_rtx_fmt_ss (ABSENCE_SET, (MODE), (ARG0), (ARG1)) -#define gen_rtx_FINAL_ABSENCE_SET(MODE, ARG0, ARG1) \ - gen_rtx_fmt_ss (FINAL_ABSENCE_SET, (MODE), (ARG0), (ARG1)) -#define gen_rtx_DEFINE_AUTOMATON(MODE, ARG0) \ - gen_rtx_fmt_s (DEFINE_AUTOMATON, (MODE), (ARG0)) -#define gen_rtx_AUTOMATA_OPTION(MODE, ARG0) \ - gen_rtx_fmt_s (AUTOMATA_OPTION, (MODE), (ARG0)) -#define gen_rtx_DEFINE_RESERVATION(MODE, ARG0, ARG1) \ - gen_rtx_fmt_ss (DEFINE_RESERVATION, (MODE), (ARG0), (ARG1)) -#define gen_rtx_DEFINE_INSN_RESERVATION(MODE, ARG0, ARG1, ARG2, ARG3) \ - gen_rtx_fmt_sies (DEFINE_INSN_RESERVATION, (MODE), (ARG0), (ARG1), (ARG2), (ARG3)) -#define gen_rtx_DEFINE_ATTR(MODE, ARG0, ARG1, ARG2) \ - gen_rtx_fmt_sse (DEFINE_ATTR, (MODE), (ARG0), (ARG1), (ARG2)) -#define gen_rtx_DEFINE_ENUM_ATTR(MODE, ARG0, ARG1, ARG2) \ - gen_rtx_fmt_sse (DEFINE_ENUM_ATTR, (MODE), (ARG0), (ARG1), (ARG2)) -#define gen_rtx_ATTR(MODE, ARG0) \ - gen_rtx_fmt_s (ATTR, (MODE), (ARG0)) -#define gen_rtx_SET_ATTR(MODE, ARG0, ARG1) \ - gen_rtx_fmt_ss (SET_ATTR, (MODE), (ARG0), (ARG1)) -#define gen_rtx_SET_ATTR_ALTERNATIVE(MODE, ARG0, ARG1) \ - gen_rtx_fmt_sE (SET_ATTR_ALTERNATIVE, (MODE), (ARG0), (ARG1)) -#define gen_rtx_EQ_ATTR(MODE, ARG0, ARG1) \ - gen_rtx_fmt_ss (EQ_ATTR, (MODE), (ARG0), (ARG1)) -#define gen_rtx_EQ_ATTR_ALT(MODE, ARG0, ARG1) \ - gen_rtx_fmt_ii (EQ_ATTR_ALT, (MODE), (ARG0), (ARG1)) -#define gen_rtx_ATTR_FLAG(MODE, ARG0) \ - gen_rtx_fmt_s (ATTR_FLAG, (MODE), (ARG0)) -#define gen_rtx_COND(MODE, ARG0, ARG1) \ - gen_rtx_fmt_Ee (COND, (MODE), (ARG0), (ARG1)) -#define gen_rtx_DEFINE_SUBST(MODE, ARG0, ARG1, ARG2, ARG3) \ - gen_rtx_fmt_sEsE (DEFINE_SUBST, (MODE), (ARG0), (ARG1), (ARG2), (ARG3)) -#define gen_rtx_DEFINE_SUBST_ATTR(MODE, ARG0, ARG1, ARG2, ARG3) \ - gen_rtx_fmt_ssss (DEFINE_SUBST_ATTR, (MODE), (ARG0), (ARG1), (ARG2), (ARG3)) - -#endif /* GCC_GENRTL_H */ diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/gensupport.h b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/gensupport.h deleted file mode 100644 index bb36f21..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/gensupport.h +++ /dev/null @@ -1,113 +0,0 @@ -/* Declarations for rtx-reader support for gen* routines. - Copyright (C) 2000-2015 Free Software Foundation, Inc. - -This file is part of GCC. - -GCC is free software; you can redistribute it and/or modify it under -the terms of the GNU General Public License as published by the Free -Software Foundation; either version 3, or (at your option) any later -version. - -GCC is distributed in the hope that it will be useful, but WITHOUT ANY -WARRANTY; without even the implied warranty of MERCHANTABILITY or -FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -for more details. - -You should have received a copy of the GNU General Public License -along with GCC; see the file COPYING3. If not see -. */ - -#ifndef GCC_GENSUPPORT_H -#define GCC_GENSUPPORT_H - -struct obstack; -extern struct obstack *rtl_obstack; - -extern bool init_rtx_reader_args_cb (int, char **, bool (*)(const char *)); -extern bool init_rtx_reader_args (int, char **); -extern rtx read_md_rtx (int *, int *); - -/* Set this to 0 to disable automatic elision of insn patterns which - can never be used in this configuration. See genconditions.c. - Must be set before calling init_md_reader. */ -extern int insn_elision; - -/* If the C test passed as the argument can be evaluated at compile - time, return its truth value; else return -1. The test must have - appeared somewhere in the machine description when genconditions - was run. */ -extern int maybe_eval_c_test (const char *); - -/* Add an entry to the table of conditions. Used by genconditions and - by read-rtl.c. */ -extern void add_c_test (const char *, int); - -/* This structure is used internally by gensupport.c and genconditions.c. */ -struct c_test -{ - const char *expr; - int value; -}; - -#ifdef __HASHTAB_H__ -extern hashval_t hash_c_test (const void *); -extern int cmp_c_test (const void *, const void *); -extern void traverse_c_tests (htab_trav, void *); -#endif - -/* Predicate handling: helper functions and data structures. */ - -struct pred_data -{ - struct pred_data *next; /* for iterating over the set of all preds */ - const char *name; /* predicate name */ - bool special; /* special handling of modes? */ - - /* data used primarily by genpreds.c */ - const char *c_block; /* C test block */ - rtx exp; /* RTL test expression */ - - /* data used primarily by genrecog.c */ - enum rtx_code singleton; /* if pred takes only one code, that code */ - int num_codes; /* number of codes accepted */ - bool allows_non_lvalue; /* if pred allows non-lvalue expressions */ - bool allows_non_const; /* if pred allows non-const expressions */ - bool codes[NUM_RTX_CODE]; /* set of codes accepted */ -}; - -extern struct pred_data *first_predicate; -extern struct pred_data *lookup_predicate (const char *); -extern void add_predicate_code (struct pred_data *, enum rtx_code); -extern void add_predicate (struct pred_data *); - -#define FOR_ALL_PREDICATES(p) for (p = first_predicate; p; p = p->next) - -struct pattern_stats -{ - /* The largest match_operand, match_operator or match_parallel - number found. */ - int max_opno; - - /* The largest match_dup, match_op_dup or match_par_dup number found. */ - int max_dup_opno; - - /* The largest match_scratch number found. */ - int max_scratch_opno; - - /* The number of times match_dup, match_op_dup or match_par_dup appears - in the pattern. */ - int num_dups; - - /* The number of rtx arguments to the generator function. */ - int num_generator_args; - - /* The number of rtx operands in an insn. */ - int num_insn_operands; - - /* The number of operand variables that are needed. */ - int num_operand_vars; -}; - -extern void get_pattern_stats (struct pattern_stats *ranges, rtvec vec); - -#endif /* GCC_GENSUPPORT_H */ diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/ggc-internal.h b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/ggc-internal.h deleted file mode 100644 index 8781010..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/ggc-internal.h +++ /dev/null @@ -1,119 +0,0 @@ -/* Garbage collection for the GNU compiler. Internal definitions - for ggc-*.c and stringpool.c. - - Copyright (C) 2009-2015 Free Software Foundation, Inc. - -This file is part of GCC. - -GCC is free software; you can redistribute it and/or modify it under -the terms of the GNU General Public License as published by the Free -Software Foundation; either version 3, or (at your option) any later -version. - -GCC is distributed in the hope that it will be useful, but WITHOUT ANY -WARRANTY; without even the implied warranty of MERCHANTABILITY or -FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -for more details. - -You should have received a copy of the GNU General Public License -along with GCC; see the file COPYING3. If not see -. */ - -#ifndef GCC_GGC_INTERNAL_H -#define GCC_GGC_INTERNAL_H - -#include "ggc.h" - -/* Call ggc_set_mark on all the roots. */ -extern void ggc_mark_roots (void); - -/* Stringpool. */ - -/* Mark the entries in the string pool. */ -extern void ggc_mark_stringpool (void); - -/* Purge the entries in the string pool. */ -extern void ggc_purge_stringpool (void); - -/* Save and restore the string pool entries for PCH. */ - -extern void gt_pch_save_stringpool (void); -extern void gt_pch_fixup_stringpool (void); -extern void gt_pch_restore_stringpool (void); - -/* PCH and GGC handling for strings, mostly trivial. */ -extern void gt_pch_p_S (void *, void *, gt_pointer_operator, void *); - -/* PCH. */ - -struct ggc_pch_data; - -/* Return a new ggc_pch_data structure. */ -extern struct ggc_pch_data *init_ggc_pch (void); - -/* The second parameter and third parameters give the address and size - of an object. Update the ggc_pch_data structure with as much of - that information as is necessary. The bool argument should be true - if the object is a string. */ -extern void ggc_pch_count_object (struct ggc_pch_data *, void *, size_t, bool); - -/* Return the total size of the data to be written to hold all - the objects previously passed to ggc_pch_count_object. */ -extern size_t ggc_pch_total_size (struct ggc_pch_data *); - -/* The objects, when read, will most likely be at the address - in the second parameter. */ -extern void ggc_pch_this_base (struct ggc_pch_data *, void *); - -/* Assuming that the objects really do end up at the address - passed to ggc_pch_this_base, return the address of this object. - The bool argument should be true if the object is a string. */ -extern char *ggc_pch_alloc_object (struct ggc_pch_data *, void *, size_t, bool); - -/* Write out any initial information required. */ -extern void ggc_pch_prepare_write (struct ggc_pch_data *, FILE *); - -/* Write out this object, including any padding. The last argument should be - true if the object is a string. */ -extern void ggc_pch_write_object (struct ggc_pch_data *, FILE *, void *, - void *, size_t, bool); - -/* All objects have been written, write out any final information - required. */ -extern void ggc_pch_finish (struct ggc_pch_data *, FILE *); - -/* A PCH file has just been read in at the address specified second - parameter. Set up the GC implementation for the new objects. */ -extern void ggc_pch_read (FILE *, void *); - - -/* Allocation and collection. */ - -/* When set, ggc_collect will do collection. */ -extern bool ggc_force_collect; - -extern void ggc_record_overhead (size_t, size_t, void * FINAL_MEM_STAT_DECL); - -extern void ggc_free_overhead (void *); - -extern void ggc_prune_overhead_list (void); - -/* Return the number of bytes allocated at the indicated address. */ -extern size_t ggc_get_size (const void *); - - -/* Statistics. */ - -/* This structure contains the statistics common to all collectors. - Particular collectors can extend this structure. */ -struct ggc_statistics -{ - /* At present, we don't really gather any interesting statistics. */ - int unused; -}; - -/* Used by the various collectors to gather and print statistics that - do not depend on the collector in use. */ -extern void ggc_print_common_statistics (FILE *, ggc_statistics *); - -#endif diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/ggc.h b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/ggc.h deleted file mode 100644 index 2f73a9b..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/ggc.h +++ /dev/null @@ -1,329 +0,0 @@ -/* Garbage collection for the GNU compiler. - - Copyright (C) 1998-2015 Free Software Foundation, Inc. - -This file is part of GCC. - -GCC is free software; you can redistribute it and/or modify it under -the terms of the GNU General Public License as published by the Free -Software Foundation; either version 3, or (at your option) any later -version. - -GCC is distributed in the hope that it will be useful, but WITHOUT ANY -WARRANTY; without even the implied warranty of MERCHANTABILITY or -FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -for more details. - -You should have received a copy of the GNU General Public License -along with GCC; see the file COPYING3. If not see -. */ - -#ifndef GCC_GGC_H -#define GCC_GGC_H -#include "statistics.h" - -/* Symbols are marked with `ggc' for `gcc gc' so as not to interfere with - an external gc library that might be linked in. */ - -/* Constants for general use. */ -extern const char empty_string[]; /* empty string */ - -/* Internal functions and data structures used by the GTY - machinery, including the generated gt*.[hc] files. */ - -#include "gtype-desc.h" - -/* One of these applies its third parameter (with cookie in the fourth - parameter) to each pointer in the object pointed to by the first - parameter, using the second parameter. */ -typedef void (*gt_note_pointers) (void *, void *, gt_pointer_operator, - void *); - -/* One of these is called before objects are re-ordered in memory. - The first parameter is the original object, the second is the - subobject that has had its pointers reordered, the third parameter - can compute the new values of a pointer when given the cookie in - the fourth parameter. */ -typedef void (*gt_handle_reorder) (void *, void *, gt_pointer_operator, - void *); - -/* Used by the gt_pch_n_* routines. Register an object in the hash table. */ -extern int gt_pch_note_object (void *, void *, gt_note_pointers); - -/* Used by the gt_pch_n_* routines. Register that an object has a reorder - function. */ -extern void gt_pch_note_reorder (void *, void *, gt_handle_reorder); - -/* generated function to clear caches in gc memory. */ -extern void gt_clear_caches (); - -/* Mark the object in the first parameter and anything it points to. */ -typedef void (*gt_pointer_walker) (void *); - -/* Structures for the easy way to mark roots. - In an array, terminated by having base == NULL. */ -struct ggc_root_tab { - void *base; - size_t nelt; - size_t stride; - gt_pointer_walker cb; - gt_pointer_walker pchw; -}; -#define LAST_GGC_ROOT_TAB { NULL, 0, 0, NULL, NULL } -/* Pointers to arrays of ggc_root_tab, terminated by NULL. */ -extern const struct ggc_root_tab * const gt_ggc_rtab[]; -extern const struct ggc_root_tab * const gt_ggc_deletable_rtab[]; -extern const struct ggc_root_tab * const gt_pch_scalar_rtab[]; - -/* If EXPR is not NULL and previously unmarked, mark it and evaluate - to true. Otherwise evaluate to false. */ -#define ggc_test_and_set_mark(EXPR) \ - ((EXPR) != NULL && ((void *) (EXPR)) != (void *) 1 && ! ggc_set_mark (EXPR)) - -#define ggc_mark(EXPR) \ - do { \ - const void *const a__ = (EXPR); \ - if (a__ != NULL && a__ != (void *) 1) \ - ggc_set_mark (a__); \ - } while (0) - -/* Actually set the mark on a particular region of memory, but don't - follow pointers. This function is called by ggc_mark_*. It - returns zero if the object was not previously marked; nonzero if - the object was already marked, or if, for any other reason, - pointers in this data structure should not be traversed. */ -extern int ggc_set_mark (const void *); - -/* Return 1 if P has been marked, zero otherwise. - P must have been allocated by the GC allocator; it mustn't point to - static objects, stack variables, or memory allocated with malloc. */ -extern int ggc_marked_p (const void *); - -/* PCH and GGC handling for strings, mostly trivial. */ -extern void gt_pch_n_S (const void *); -extern void gt_ggc_m_S (const void *); - -/* End of GTY machinery API. */ - -/* Initialize the string pool. */ -extern void init_stringpool (void); - -/* Initialize the garbage collector. */ -extern void init_ggc (void); - -/* When true, identifier nodes are considered as GC roots. When - false, identifier nodes are treated like any other GC-allocated - object, and the identifier hash table is treated as a weak - hash. */ -extern bool ggc_protect_identifiers; - -/* Write out all GCed objects to F. */ -extern void gt_pch_save (FILE *f); - - -/* Allocation. */ - -/* The internal primitive. */ -extern void *ggc_internal_alloc (size_t, void (*)(void *), size_t, - size_t CXX_MEM_STAT_INFO) - ATTRIBUTE_MALLOC; - - static inline - void * - ggc_internal_alloc (size_t s CXX_MEM_STAT_INFO) -{ - return ggc_internal_alloc (s, NULL, 0, 1 PASS_MEM_STAT); -} - -extern size_t ggc_round_alloc_size (size_t requested_size); - -/* Allocates cleared memory. */ -extern void *ggc_internal_cleared_alloc (size_t, void (*)(void *), - size_t, size_t - CXX_MEM_STAT_INFO) ATTRIBUTE_MALLOC; - -static inline -void * -ggc_internal_cleared_alloc (size_t s CXX_MEM_STAT_INFO) -{ - return ggc_internal_cleared_alloc (s, NULL, 0, 1 PASS_MEM_STAT); -} - -/* Resize a block. */ -extern void *ggc_realloc (void *, size_t CXX_MEM_STAT_INFO); - -/* Free a block. To be used when known for certain it's not reachable. */ -extern void ggc_free (void *); - -extern void dump_ggc_loc_statistics (bool); - -/* Reallocator. */ -#define GGC_RESIZEVEC(T, P, N) \ - ((T *) ggc_realloc ((P), (N) * sizeof (T) MEM_STAT_INFO)) - -template -void -finalize (void *p) -{ - static_cast (p)->~T (); -} - -template -static inline bool -need_finalization_p () -{ -#if GCC_VERSION >= 4003 - return !__has_trivial_destructor (T); -#else - return true; -#endif -} - -template -static inline T * -ggc_alloc (ALONE_CXX_MEM_STAT_INFO) -{ - if (need_finalization_p ()) - return static_cast (ggc_internal_alloc (sizeof (T), finalize, 0, 1 - PASS_MEM_STAT)); - else - return static_cast (ggc_internal_alloc (sizeof (T), NULL, 0, 1 - PASS_MEM_STAT)); -} - -template -static inline T * -ggc_cleared_alloc (ALONE_CXX_MEM_STAT_INFO) -{ - if (need_finalization_p ()) - return static_cast (ggc_internal_cleared_alloc (sizeof (T), - finalize, 0, 1 - PASS_MEM_STAT)); - else - return static_cast (ggc_internal_cleared_alloc (sizeof (T), NULL, 0, 1 - PASS_MEM_STAT)); -} - -template -static inline T * -ggc_vec_alloc (size_t c CXX_MEM_STAT_INFO) -{ - if (need_finalization_p ()) - return static_cast (ggc_internal_alloc (c * sizeof (T), finalize, - sizeof (T), c PASS_MEM_STAT)); - else - return static_cast (ggc_internal_alloc (c * sizeof (T), NULL, 0, 0 - PASS_MEM_STAT)); -} - -template -static inline T * -ggc_cleared_vec_alloc (size_t c CXX_MEM_STAT_INFO) -{ - if (need_finalization_p ()) - return static_cast (ggc_internal_cleared_alloc (c * sizeof (T), - finalize, - sizeof (T), c - PASS_MEM_STAT)); - else - return static_cast (ggc_internal_cleared_alloc (c * sizeof (T), NULL, - 0, 0 PASS_MEM_STAT)); -} - -static inline void * -ggc_alloc_atomic (size_t s CXX_MEM_STAT_INFO) -{ - return ggc_internal_alloc (s PASS_MEM_STAT); -} - -/* Allocate a gc-able string, and fill it with LENGTH bytes from CONTENTS. - If LENGTH is -1, then CONTENTS is assumed to be a - null-terminated string and the memory sized accordingly. */ -extern const char *ggc_alloc_string (const char *contents, int length - CXX_MEM_STAT_INFO); - -/* Make a copy of S, in GC-able memory. */ -#define ggc_strdup(S) ggc_alloc_string ((S), -1 MEM_STAT_INFO) - -/* Invoke the collector. Garbage collection occurs only when this - function is called, not during allocations. */ -extern void ggc_collect (void); - -/* Assume that all GGC memory is reachable and grow the limits for next collection. */ -extern void ggc_grow (void); - -/* Register an additional root table. This can be useful for some - plugins. Does nothing if the passed pointer is NULL. */ -extern void ggc_register_root_tab (const struct ggc_root_tab *); - -/* Read objects previously saved with gt_pch_save from F. */ -extern void gt_pch_restore (FILE *f); - -/* Statistics. */ - -/* Print allocation statistics. */ -extern void ggc_print_statistics (void); - -extern void stringpool_statistics (void); - -/* Heuristics. */ -extern void init_ggc_heuristics (void); - -#define ggc_alloc_rtvec_sized(NELT) \ - (rtvec_def *) ggc_internal_alloc (sizeof (struct rtvec_def) \ - + ((NELT) - 1) * sizeof (rtx)) \ - -/* Memory statistics passing versions of some allocators. Too few of them to - make gengtype produce them, so just define the needed ones here. */ -static inline struct rtx_def * -ggc_alloc_rtx_def_stat (size_t s CXX_MEM_STAT_INFO) -{ - return (struct rtx_def *) ggc_internal_alloc (s PASS_MEM_STAT); -} - -static inline union tree_node * -ggc_alloc_tree_node_stat (size_t s CXX_MEM_STAT_INFO) -{ - return (union tree_node *) ggc_internal_alloc (s PASS_MEM_STAT); -} - -static inline union tree_node * -ggc_alloc_cleared_tree_node_stat (size_t s CXX_MEM_STAT_INFO) -{ - return (union tree_node *) ggc_internal_cleared_alloc (s PASS_MEM_STAT); -} - -static inline struct gimple_statement_base * -ggc_alloc_cleared_gimple_statement_stat (size_t s CXX_MEM_STAT_INFO) -{ - return (struct gimple_statement_base *) - ggc_internal_cleared_alloc (s PASS_MEM_STAT); -} - -static inline void -gt_ggc_mx (const char *s) -{ - ggc_test_and_set_mark (const_cast (s)); -} - -static inline void -gt_pch_nx (const char *) -{ -} - -static inline void -gt_ggc_mx (int) -{ -} - -static inline void -gt_pch_nx (int) -{ -} - -static inline void -gt_pch_nx (unsigned int) -{ -} - -#endif diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/gimple-builder.h b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/gimple-builder.h deleted file mode 100644 index b58fc3e..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/gimple-builder.h +++ /dev/null @@ -1,33 +0,0 @@ -/* Header file for high level statement building routines. - Copyright (C) 2013-2015 Free Software Foundation, Inc. - -This file is part of GCC. - -GCC is free software; you can redistribute it and/or modify it under -the terms of the GNU General Public License as published by the Free -Software Foundation; either version 3, or (at your option) any later -version. - -GCC is distributed in the hope that it will be useful, but WITHOUT ANY -WARRANTY; without even the implied warranty of MERCHANTABILITY or -FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License - for more details. - -You should have received a copy of the GNU General Public License -along with GCC; see the file COPYING3. If not see -. */ - - -#ifndef GCC_GIMPLE_BUILDER_H -#define GCC_GIMPLE_BUILDER_H - -gassign *build_assign (enum tree_code, tree, int, tree lhs = NULL_TREE); -gassign *build_assign (enum tree_code, gimple, int, tree lhs = NULL_TREE); -gassign *build_assign (enum tree_code, tree, tree, tree lhs = NULL_TREE); -gassign *build_assign (enum tree_code, gimple, tree, tree lhs = NULL_TREE); -gassign *build_assign (enum tree_code, tree, gimple, tree lhs = NULL_TREE); -gassign *build_assign (enum tree_code, gimple, gimple, tree lhs = NULL_TREE); -gassign *build_type_cast (tree, tree, tree lhs = NULL_TREE); -gassign *build_type_cast (tree, gimple, tree lhs = NULL_TREE); - -#endif /* GCC_GIMPLE_BUILDER_H */ diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/gimple-expr.h b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/gimple-expr.h deleted file mode 100644 index 20815b0..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/gimple-expr.h +++ /dev/null @@ -1,180 +0,0 @@ -/* Header file for gimple decl, type and expressions. - Copyright (C) 2013-2015 Free Software Foundation, Inc. - -This file is part of GCC. - -GCC is free software; you can redistribute it and/or modify it under -the terms of the GNU General Public License as published by the Free -Software Foundation; either version 3, or (at your option) any later -version. - -GCC is distributed in the hope that it will be useful, but WITHOUT ANY -WARRANTY; without even the implied warranty of MERCHANTABILITY or -FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License - for more details. - -You should have received a copy of the GNU General Public License -along with GCC; see the file COPYING3. If not see -. */ - -#ifndef GCC_GIMPLE_EXPR_H -#define GCC_GIMPLE_EXPR_H - -extern bool useless_type_conversion_p (tree, tree); - - -extern void gimple_set_body (tree, gimple_seq); -extern gimple_seq gimple_body (tree); -extern bool gimple_has_body_p (tree); -extern const char *gimple_decl_printable_name (tree, int); -extern tree copy_var_decl (tree, tree, tree); -extern bool gimple_can_coalesce_p (tree, tree); -extern tree create_tmp_var_name (const char *); -extern tree create_tmp_var_raw (tree, const char * = NULL); -extern tree create_tmp_var (tree, const char * = NULL); -extern tree create_tmp_reg (tree, const char * = NULL); -extern tree create_tmp_reg_fn (struct function *, tree, const char *); - - -extern void extract_ops_from_tree (tree, enum tree_code *, tree *, tree *, - tree *); -extern void gimple_cond_get_ops_from_tree (tree, enum tree_code *, tree *, - tree *); -extern bool is_gimple_lvalue (tree); -extern bool is_gimple_condexpr (tree); -extern bool is_gimple_address (const_tree); -extern bool is_gimple_invariant_address (const_tree); -extern bool is_gimple_ip_invariant_address (const_tree); -extern bool is_gimple_min_invariant (const_tree); -extern bool is_gimple_ip_invariant (const_tree); -extern bool is_gimple_reg (tree); -extern bool is_gimple_val (tree); -extern bool is_gimple_asm_val (tree); -extern bool is_gimple_min_lval (tree); -extern bool is_gimple_call_addr (tree); -extern bool is_gimple_mem_ref_addr (tree); -extern void mark_addressable (tree); -extern bool is_gimple_reg_rhs (tree); - -/* Return true if a conversion from either type of TYPE1 and TYPE2 - to the other is not required. Otherwise return false. */ - -static inline bool -types_compatible_p (tree type1, tree type2) -{ - return (type1 == type2 - || (useless_type_conversion_p (type1, type2) - && useless_type_conversion_p (type2, type1))); -} - -/* Return true if TYPE is a suitable type for a scalar register variable. */ - -static inline bool -is_gimple_reg_type (tree type) -{ - return !AGGREGATE_TYPE_P (type); -} - -/* Return true if T is a variable. */ - -static inline bool -is_gimple_variable (tree t) -{ - return (TREE_CODE (t) == VAR_DECL - || TREE_CODE (t) == PARM_DECL - || TREE_CODE (t) == RESULT_DECL - || TREE_CODE (t) == SSA_NAME); -} - -/* Return true if T is a GIMPLE identifier (something with an address). */ - -static inline bool -is_gimple_id (tree t) -{ - return (is_gimple_variable (t) - || TREE_CODE (t) == FUNCTION_DECL - || TREE_CODE (t) == LABEL_DECL - || TREE_CODE (t) == CONST_DECL - /* Allow string constants, since they are addressable. */ - || TREE_CODE (t) == STRING_CST); -} - -/* Return true if OP, an SSA name or a DECL is a virtual operand. */ - -static inline bool -virtual_operand_p (tree op) -{ - if (TREE_CODE (op) == SSA_NAME) - { - op = SSA_NAME_VAR (op); - if (!op) - return false; - } - - if (TREE_CODE (op) == VAR_DECL) - return VAR_DECL_IS_VIRTUAL_OPERAND (op); - - return false; -} - -/* Return true if T is something whose address can be taken. */ - -static inline bool -is_gimple_addressable (tree t) -{ - return (is_gimple_id (t) || handled_component_p (t) - || TREE_CODE (t) == MEM_REF); -} - -/* Return true if T is a valid gimple constant. */ - -static inline bool -is_gimple_constant (const_tree t) -{ - switch (TREE_CODE (t)) - { - case INTEGER_CST: - case REAL_CST: - case FIXED_CST: - case STRING_CST: - case COMPLEX_CST: - case VECTOR_CST: - return true; - - default: - return false; - } -} - -/* A wrapper around extract_ops_from_tree with 3 ops, for callers which - expect to see only a maximum of two operands. */ - -static inline void -extract_ops_from_tree (tree expr, enum tree_code *code, tree *op0, - tree *op1) -{ - tree op2; - extract_ops_from_tree (expr, code, op0, op1, &op2); - gcc_assert (op2 == NULL_TREE); -} - -/* Given a valid GIMPLE_CALL function address return the FUNCTION_DECL - associated with the callee if known. Otherwise return NULL_TREE. */ - -static inline tree -gimple_call_addr_fndecl (const_tree fn) -{ - if (fn && TREE_CODE (fn) == ADDR_EXPR) - { - tree fndecl = TREE_OPERAND (fn, 0); - if (TREE_CODE (fndecl) == MEM_REF - && TREE_CODE (TREE_OPERAND (fndecl, 0)) == ADDR_EXPR - && integer_zerop (TREE_OPERAND (fndecl, 1))) - fndecl = TREE_OPERAND (TREE_OPERAND (fndecl, 0), 0); - if (TREE_CODE (fndecl) == FUNCTION_DECL) - return fndecl; - } - return NULL_TREE; -} - -#endif /* GCC_GIMPLE_EXPR_H */ diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/gimple-fold.h b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/gimple-fold.h deleted file mode 100644 index 5eb5446..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/gimple-fold.h +++ /dev/null @@ -1,136 +0,0 @@ -/* Gimple folding definitions. - - Copyright (C) 2011-2015 Free Software Foundation, Inc. - Contributed by Richard Guenther - -This file is part of GCC. - -GCC is free software; you can redistribute it and/or modify it under -the terms of the GNU General Public License as published by the Free -Software Foundation; either version 3, or (at your option) any later -version. - -GCC is distributed in the hope that it will be useful, but WITHOUT ANY -WARRANTY; without even the implied warranty of MERCHANTABILITY or -FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -for more details. - -You should have received a copy of the GNU General Public License -along with GCC; see the file COPYING3. If not see -. */ - -#ifndef GCC_GIMPLE_FOLD_H -#define GCC_GIMPLE_FOLD_H - -extern tree canonicalize_constructor_val (tree, tree); -extern tree get_symbol_constant_value (tree); -extern void gimplify_and_update_call_from_tree (gimple_stmt_iterator *, tree); -extern bool fold_stmt (gimple_stmt_iterator *); -extern bool fold_stmt (gimple_stmt_iterator *, tree (*) (tree)); -extern bool fold_stmt_inplace (gimple_stmt_iterator *); -extern tree maybe_fold_and_comparisons (enum tree_code, tree, tree, - enum tree_code, tree, tree); -extern tree maybe_fold_or_comparisons (enum tree_code, tree, tree, - enum tree_code, tree, tree); -extern bool arith_overflowed_p (enum tree_code, const_tree, const_tree, - const_tree); -extern tree no_follow_ssa_edges (tree); -extern tree follow_single_use_edges (tree); -extern tree gimple_fold_stmt_to_constant_1 (gimple, tree (*) (tree), - tree (*) (tree) = no_follow_ssa_edges); -extern tree gimple_fold_stmt_to_constant (gimple, tree (*) (tree)); -extern tree fold_ctor_reference (tree, tree, unsigned HOST_WIDE_INT, - unsigned HOST_WIDE_INT, tree); -extern tree fold_const_aggregate_ref_1 (tree, tree (*) (tree)); -extern tree fold_const_aggregate_ref (tree); -extern tree gimple_get_virt_method_for_binfo (HOST_WIDE_INT, tree, - bool *can_refer = NULL); -extern tree gimple_get_virt_method_for_vtable (HOST_WIDE_INT, tree, - unsigned HOST_WIDE_INT, - bool *can_refer = NULL); -extern bool gimple_val_nonnegative_real_p (tree); -extern tree gimple_fold_indirect_ref (tree); -extern bool arith_code_with_undefined_signed_overflow (tree_code); -extern gimple_seq rewrite_to_defined_overflow (gimple); - -/* gimple_build, functionally matching fold_buildN, outputs stmts - int the provided sequence, matching and simplifying them on-the-fly. - Supposed to replace force_gimple_operand (fold_buildN (...), ...). */ -extern tree gimple_build (gimple_seq *, location_t, - enum tree_code, tree, tree, - tree (*valueize) (tree) = NULL); -inline tree -gimple_build (gimple_seq *seq, - enum tree_code code, tree type, tree op0) -{ - return gimple_build (seq, UNKNOWN_LOCATION, code, type, op0); -} -extern tree gimple_build (gimple_seq *, location_t, - enum tree_code, tree, tree, tree, - tree (*valueize) (tree) = NULL); -inline tree -gimple_build (gimple_seq *seq, - enum tree_code code, tree type, tree op0, tree op1) -{ - return gimple_build (seq, UNKNOWN_LOCATION, code, type, op0, op1); -} -extern tree gimple_build (gimple_seq *, location_t, - enum tree_code, tree, tree, tree, tree, - tree (*valueize) (tree) = NULL); -inline tree -gimple_build (gimple_seq *seq, - enum tree_code code, tree type, tree op0, tree op1, tree op2) -{ - return gimple_build (seq, UNKNOWN_LOCATION, code, type, op0, op1, op2); -} -extern tree gimple_build (gimple_seq *, location_t, - enum built_in_function, tree, tree, - tree (*valueize) (tree) = NULL); -inline tree -gimple_build (gimple_seq *seq, - enum built_in_function fn, tree type, tree arg0) -{ - return gimple_build (seq, UNKNOWN_LOCATION, fn, type, arg0); -} -extern tree gimple_build (gimple_seq *, location_t, - enum built_in_function, tree, tree, tree, - tree (*valueize) (tree) = NULL); -inline tree -gimple_build (gimple_seq *seq, - enum built_in_function fn, tree type, tree arg0, tree arg1) -{ - return gimple_build (seq, UNKNOWN_LOCATION, fn, type, arg0, arg1); -} -extern tree gimple_build (gimple_seq *, location_t, - enum built_in_function, tree, tree, tree, tree, - tree (*valueize) (tree) = NULL); -inline tree -gimple_build (gimple_seq *seq, - enum built_in_function fn, tree type, - tree arg0, tree arg1, tree arg2) -{ - return gimple_build (seq, UNKNOWN_LOCATION, fn, type, arg0, arg1, arg2); -} - -extern tree gimple_convert (gimple_seq *, location_t, tree, tree); -inline tree -gimple_convert (gimple_seq *seq, tree type, tree op) -{ - return gimple_convert (seq, UNKNOWN_LOCATION, type, op); -} - -/* In gimple-match.c. */ -extern tree gimple_simplify (enum tree_code, tree, tree, - gimple_seq *, tree (*)(tree)); -extern tree gimple_simplify (enum tree_code, tree, tree, tree, - gimple_seq *, tree (*)(tree)); -extern tree gimple_simplify (enum tree_code, tree, tree, tree, tree, - gimple_seq *, tree (*)(tree)); -extern tree gimple_simplify (enum built_in_function, tree, tree, - gimple_seq *, tree (*)(tree)); -extern tree gimple_simplify (enum built_in_function, tree, tree, tree, - gimple_seq *, tree (*)(tree)); -extern tree gimple_simplify (enum built_in_function, tree, tree, tree, tree, - gimple_seq *, tree (*)(tree)); - -#endif /* GCC_GIMPLE_FOLD_H */ diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/gimple-iterator.h b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/gimple-iterator.h deleted file mode 100644 index 9aa7508..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/gimple-iterator.h +++ /dev/null @@ -1,347 +0,0 @@ -/* Header file for gimple iterators. - Copyright (C) 2013-2015 Free Software Foundation, Inc. - -This file is part of GCC. - -GCC is free software; you can redistribute it and/or modify it under -the terms of the GNU General Public License as published by the Free -Software Foundation; either version 3, or (at your option) any later -version. - -GCC is distributed in the hope that it will be useful, but WITHOUT ANY -WARRANTY; without even the implied warranty of MERCHANTABILITY or -FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License - for more details. - -You should have received a copy of the GNU General Public License -along with GCC; see the file COPYING3. If not see -. */ - -#ifndef GCC_GIMPLE_ITERATOR_H -#define GCC_GIMPLE_ITERATOR_H - -/* Iterator object for GIMPLE statement sequences. */ - -struct gimple_stmt_iterator -{ - /* Sequence node holding the current statement. */ - gimple_seq_node ptr; - - /* Sequence and basic block holding the statement. These fields - are necessary to handle edge cases such as when statement is - added to an empty basic block or when the last statement of a - block/sequence is removed. */ - gimple_seq *seq; - basic_block bb; -}; - -/* Iterator over GIMPLE_PHI statements. */ -struct gphi_iterator : public gimple_stmt_iterator -{ - gphi *phi () const - { - return as_a (ptr); - } -}; - -enum gsi_iterator_update -{ - GSI_NEW_STMT, /* Only valid when single statement is added, move - iterator to it. */ - GSI_SAME_STMT, /* Leave the iterator at the same statement. */ - GSI_CONTINUE_LINKING /* Move iterator to whatever position is suitable - for linking other statements in the same - direction. */ -}; - -extern void gsi_insert_seq_before_without_update (gimple_stmt_iterator *, - gimple_seq, - enum gsi_iterator_update); -extern void gsi_insert_seq_before (gimple_stmt_iterator *, gimple_seq, - enum gsi_iterator_update); -extern void gsi_insert_seq_after_without_update (gimple_stmt_iterator *, - gimple_seq, - enum gsi_iterator_update); -extern void gsi_insert_seq_after (gimple_stmt_iterator *, gimple_seq, - enum gsi_iterator_update); -extern gimple_seq gsi_split_seq_after (gimple_stmt_iterator); -extern void gsi_set_stmt (gimple_stmt_iterator *, gimple); -extern void gsi_split_seq_before (gimple_stmt_iterator *, gimple_seq *); -extern bool gsi_replace (gimple_stmt_iterator *, gimple, bool); -extern void gsi_replace_with_seq (gimple_stmt_iterator *, gimple_seq, bool); -extern void gsi_insert_before_without_update (gimple_stmt_iterator *, gimple, - enum gsi_iterator_update); -extern void gsi_insert_before (gimple_stmt_iterator *, gimple, - enum gsi_iterator_update); -extern void gsi_insert_after_without_update (gimple_stmt_iterator *, gimple, - enum gsi_iterator_update); -extern void gsi_insert_after (gimple_stmt_iterator *, gimple, - enum gsi_iterator_update); -extern bool gsi_remove (gimple_stmt_iterator *, bool); -extern gimple_stmt_iterator gsi_for_stmt (gimple); -extern gphi_iterator gsi_for_phi (gphi *); -extern void gsi_move_after (gimple_stmt_iterator *, gimple_stmt_iterator *); -extern void gsi_move_before (gimple_stmt_iterator *, gimple_stmt_iterator *); -extern void gsi_move_to_bb_end (gimple_stmt_iterator *, basic_block); -extern void gsi_insert_on_edge (edge, gimple); -extern void gsi_insert_seq_on_edge (edge, gimple_seq); -extern basic_block gsi_insert_on_edge_immediate (edge, gimple); -extern basic_block gsi_insert_seq_on_edge_immediate (edge, gimple_seq); -extern void gsi_commit_edge_inserts (void); -extern void gsi_commit_one_edge_insert (edge, basic_block *); -extern gphi_iterator gsi_start_phis (basic_block); - -/* Return a new iterator pointing to GIMPLE_SEQ's first statement. */ - -static inline gimple_stmt_iterator -gsi_start_1 (gimple_seq *seq) -{ - gimple_stmt_iterator i; - - i.ptr = gimple_seq_first (*seq); - i.seq = seq; - i.bb = i.ptr ? gimple_bb (i.ptr) : NULL; - - return i; -} - -#define gsi_start(x) gsi_start_1 (&(x)) - -static inline gimple_stmt_iterator -gsi_none (void) -{ - gimple_stmt_iterator i; - i.ptr = NULL; - i.seq = NULL; - i.bb = NULL; - return i; -} - -/* Return a new iterator pointing to the first statement in basic block BB. */ - -static inline gimple_stmt_iterator -gsi_start_bb (basic_block bb) -{ - gimple_stmt_iterator i; - gimple_seq *seq; - - seq = bb_seq_addr (bb); - i.ptr = gimple_seq_first (*seq); - i.seq = seq; - i.bb = bb; - - return i; -} - -gimple_stmt_iterator gsi_start_edge (edge e); - -/* Return a new iterator initially pointing to GIMPLE_SEQ's last statement. */ - -static inline gimple_stmt_iterator -gsi_last_1 (gimple_seq *seq) -{ - gimple_stmt_iterator i; - - i.ptr = gimple_seq_last (*seq); - i.seq = seq; - i.bb = i.ptr ? gimple_bb (i.ptr) : NULL; - - return i; -} - -#define gsi_last(x) gsi_last_1 (&(x)) - -/* Return a new iterator pointing to the last statement in basic block BB. */ - -static inline gimple_stmt_iterator -gsi_last_bb (basic_block bb) -{ - gimple_stmt_iterator i; - gimple_seq *seq; - - seq = bb_seq_addr (bb); - i.ptr = gimple_seq_last (*seq); - i.seq = seq; - i.bb = bb; - - return i; -} - -/* Return true if I is at the end of its sequence. */ - -static inline bool -gsi_end_p (gimple_stmt_iterator i) -{ - return i.ptr == NULL; -} - -/* Return true if I is one statement before the end of its sequence. */ - -static inline bool -gsi_one_before_end_p (gimple_stmt_iterator i) -{ - return i.ptr != NULL && i.ptr->next == NULL; -} - -/* Advance the iterator to the next gimple statement. */ - -static inline void -gsi_next (gimple_stmt_iterator *i) -{ - i->ptr = i->ptr->next; -} - -/* Advance the iterator to the previous gimple statement. */ - -static inline void -gsi_prev (gimple_stmt_iterator *i) -{ - gimple prev = i->ptr->prev; - if (prev->next) - i->ptr = prev; - else - i->ptr = NULL; -} - -/* Return the current stmt. */ - -static inline gimple -gsi_stmt (gimple_stmt_iterator i) -{ - return i.ptr; -} - -/* Return a new iterator pointing to the first non-debug statement - in basic block BB. */ - -static inline gimple_stmt_iterator -gsi_start_bb_nondebug (basic_block bb) -{ - gimple_stmt_iterator gsi = gsi_start_bb (bb); - while (!gsi_end_p (gsi) && is_gimple_debug (gsi_stmt (gsi))) - gsi_next (&gsi); - - return gsi; -} - -/* Return a block statement iterator that points to the first non-label - statement in block BB. */ - -static inline gimple_stmt_iterator -gsi_after_labels (basic_block bb) -{ - gimple_stmt_iterator gsi = gsi_start_bb (bb); - - while (!gsi_end_p (gsi) && gimple_code (gsi_stmt (gsi)) == GIMPLE_LABEL) - gsi_next (&gsi); - - return gsi; -} - -/* Advance the iterator to the next non-debug gimple statement. */ - -static inline void -gsi_next_nondebug (gimple_stmt_iterator *i) -{ - do - { - gsi_next (i); - } - while (!gsi_end_p (*i) && is_gimple_debug (gsi_stmt (*i))); -} - -/* Advance the iterator to the previous non-debug gimple statement. */ - -static inline void -gsi_prev_nondebug (gimple_stmt_iterator *i) -{ - do - { - gsi_prev (i); - } - while (!gsi_end_p (*i) && is_gimple_debug (gsi_stmt (*i))); -} - -/* Return a new iterator pointing to the first non-debug statement in - basic block BB. */ - -static inline gimple_stmt_iterator -gsi_start_nondebug_bb (basic_block bb) -{ - gimple_stmt_iterator i = gsi_start_bb (bb); - - if (!gsi_end_p (i) && is_gimple_debug (gsi_stmt (i))) - gsi_next_nondebug (&i); - - return i; -} - -/* Return a new iterator pointing to the first non-debug non-label statement in - basic block BB. */ - -static inline gimple_stmt_iterator -gsi_start_nondebug_after_labels_bb (basic_block bb) -{ - gimple_stmt_iterator i = gsi_after_labels (bb); - - if (!gsi_end_p (i) && is_gimple_debug (gsi_stmt (i))) - gsi_next_nondebug (&i); - - return i; -} - -/* Return a new iterator pointing to the last non-debug statement in - basic block BB. */ - -static inline gimple_stmt_iterator -gsi_last_nondebug_bb (basic_block bb) -{ - gimple_stmt_iterator i = gsi_last_bb (bb); - - if (!gsi_end_p (i) && is_gimple_debug (gsi_stmt (i))) - gsi_prev_nondebug (&i); - - return i; -} - -/* Iterates I statement iterator to the next non-virtual statement. */ - -static inline void -gsi_next_nonvirtual_phi (gphi_iterator *i) -{ - gphi *phi; - - if (gsi_end_p (*i)) - return; - - phi = i->phi (); - gcc_assert (phi != NULL); - - while (virtual_operand_p (gimple_phi_result (phi))) - { - gsi_next (i); - - if (gsi_end_p (*i)) - return; - - phi = i->phi (); - } -} - -/* Return the basic block associated with this iterator. */ - -static inline basic_block -gsi_bb (gimple_stmt_iterator i) -{ - return i.bb; -} - -/* Return the sequence associated with this iterator. */ - -static inline gimple_seq -gsi_seq (gimple_stmt_iterator i) -{ - return *i.seq; -} - -#endif /* GCC_GIMPLE_ITERATOR_H */ diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/gimple-low.h b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/gimple-low.h deleted file mode 100644 index fb9d8fd..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/gimple-low.h +++ /dev/null @@ -1,28 +0,0 @@ -/* Header file for gimple lowering pass. - Copyright (C) 2013-2015 Free Software Foundation, Inc. - -This file is part of GCC. - -GCC is free software; you can redistribute it and/or modify it under -the terms of the GNU General Public License as published by the Free -Software Foundation; either version 3, or (at your option) any later -version. - -GCC is distributed in the hope that it will be useful, but WITHOUT ANY -WARRANTY; without even the implied warranty of MERCHANTABILITY or -FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License - for more details. - -You should have received a copy of the GNU General Public License -along with GCC; see the file COPYING3. If not see -. */ - -#ifndef GCC_GIMPLE_LOW_H -#define GCC_GIMPLE_LOW_H - -extern bool gimple_stmt_may_fallthru (gimple); -extern bool gimple_seq_may_fallthru (gimple_seq); -extern void record_vars_into (tree, tree); -extern void record_vars (tree); - -#endif /* GCC_GIMPLE_LOW_H */ diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/gimple-match.h b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/gimple-match.h deleted file mode 100644 index 47ee2cc..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/gimple-match.h +++ /dev/null @@ -1,50 +0,0 @@ -/* Gimple simplify definitions. - - Copyright (C) 2011-2015 Free Software Foundation, Inc. - Contributed by Richard Guenther - -This file is part of GCC. - -GCC is free software; you can redistribute it and/or modify it under -the terms of the GNU General Public License as published by the Free -Software Foundation; either version 3, or (at your option) any later -version. - -GCC is distributed in the hope that it will be useful, but WITHOUT ANY -WARRANTY; without even the implied warranty of MERCHANTABILITY or -FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -for more details. - -You should have received a copy of the GNU General Public License -along with GCC; see the file COPYING3. If not see -. */ - -#ifndef GCC_GIMPLE_MATCH_H -#define GCC_GIMPLE_MATCH_H - - -/* Helper to transparently allow tree codes and builtin function codes - exist in one storage entity. */ -class code_helper -{ -public: - code_helper () {} - code_helper (tree_code code) : rep ((int) code) {} - code_helper (built_in_function fn) : rep (-(int) fn) {} - operator tree_code () const { return (tree_code) rep; } - operator built_in_function () const { return (built_in_function) -rep; } - bool is_tree_code () const { return rep > 0; } - bool is_fn_code () const { return rep < 0; } - int get_rep () const { return rep; } -private: - int rep; -}; - -bool gimple_simplify (gimple, code_helper *, tree *, gimple_seq *, - tree (*)(tree)); -tree maybe_push_res_to_seq (code_helper, tree, tree *, - gimple_seq *, tree res = NULL_TREE); -void maybe_build_generic_op (enum tree_code, tree, tree *, tree, tree); - - -#endif /* GCC_GIMPLE_MATCH_H */ diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/gimple-pretty-print.h b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/gimple-pretty-print.h deleted file mode 100644 index 883a7a3..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/gimple-pretty-print.h +++ /dev/null @@ -1,39 +0,0 @@ -/* Various declarations for pretty formatting of GIMPLE statements and - expressions. - Copyright (C) 2000-2015 Free Software Foundation, Inc. - -This file is part of GCC. - -GCC is free software; you can redistribute it and/or modify it under -the terms of the GNU General Public License as published by the Free -Software Foundation; either version 3, or (at your option) any later -version. - -GCC is distributed in the hope that it will be useful, but WITHOUT ANY -WARRANTY; without even the implied warranty of MERCHANTABILITY or -FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -for more details. - -You should have received a copy of the GNU General Public License -along with GCC; see the file COPYING3. If not see -. */ - -#ifndef GCC_GIMPLE_PRETTY_PRINT_H -#define GCC_GIMPLE_PRETTY_PRINT_H - -#include "pretty-print.h" -#include "tree-pretty-print.h" - -/* In gimple-pretty-print.c */ -extern void debug_gimple_stmt (gimple); -extern void debug_gimple_seq (gimple_seq); -extern void print_gimple_seq (FILE *, gimple_seq, int, int); -extern void print_gimple_stmt (FILE *, gimple, int, int); -extern void debug (gimple_statement_base &ref); -extern void debug (gimple_statement_base *ptr); -extern void print_gimple_expr (FILE *, gimple, int, int); -extern void pp_gimple_stmt_1 (pretty_printer *, gimple, int, int); -extern void gimple_dump_bb (FILE *, basic_block, int, int); -extern void gimple_dump_bb_for_graph (pretty_printer *, basic_block); - -#endif /* ! GCC_GIMPLE_PRETTY_PRINT_H */ diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/gimple-ssa.h b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/gimple-ssa.h deleted file mode 100644 index 0b56a61..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/gimple-ssa.h +++ /dev/null @@ -1,204 +0,0 @@ -/* Header file for routines that straddle the border between GIMPLE and - SSA in gimple. - Copyright (C) 2009-2015 Free Software Foundation, Inc. - -This file is part of GCC. - -GCC is free software; you can redistribute it and/or modify -it under the terms of the GNU General Public License as published by -the Free Software Foundation; either version 3, or (at your option) -any later version. - -GCC is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU General Public License for more details. - -You should have received a copy of the GNU General Public License -along with GCC; see the file COPYING3. If not see -. */ - -#ifndef GCC_GIMPLE_SSA_H -#define GCC_GIMPLE_SSA_H - -#include "hash-map.h" -#include "tree-hasher.h" -#include "tree-ssa-operands.h" - -/* This structure is used to map a gimple statement to a label, - or list of labels to represent transaction restart. */ - -struct GTY((for_user)) tm_restart_node { - gimple stmt; - tree label_or_list; -}; - -/* Hasher for tm_restart_node. */ - -struct tm_restart_hasher : ggc_hasher -{ - static hashval_t hash (tm_restart_node *n) { return htab_hash_pointer (n); } - - static bool - equal (tm_restart_node *a, tm_restart_node *b) - { - return a == b; - } -}; - -struct ssa_name_hasher : ggc_hasher -{ - /* Hash a tree in a uid_decl_map. */ - - static hashval_t - hash (tree item) - { - return item->ssa_name.var->decl_minimal.uid; - } - - /* Return true if the DECL_UID in both trees are equal. */ - - static bool - equal (tree a, tree b) -{ - return (a->ssa_name.var->decl_minimal.uid == b->ssa_name.var->decl_minimal.uid); -} -}; - -/* Gimple dataflow datastructure. All publicly available fields shall have - gimple_ accessor defined, all publicly modifiable fields should have - gimple_set accessor. */ -struct GTY(()) gimple_df { - /* A vector of all the noreturn calls passed to modify_stmt. - cleanup_control_flow uses it to detect cases where a mid-block - indirect call has been turned into a noreturn call. When this - happens, all the instructions after the call are no longer - reachable and must be deleted as dead. */ - vec *modified_noreturn_calls; - - /* Array of all SSA_NAMEs used in the function. */ - vec *ssa_names; - - /* Artificial variable used for the virtual operand FUD chain. */ - tree vop; - - /* The PTA solution for the ESCAPED artificial variable. */ - struct pt_solution escaped; - - /* A map of decls to artificial ssa-names that point to the partition - of the decl. */ - hash_map * GTY((skip(""))) decls_to_pointers; - - /* Free list of SSA_NAMEs. */ - vec *free_ssanames; - - /* Hashtable holding definition for symbol. If this field is not NULL, it - means that the first reference to this variable in the function is a - USE or a VUSE. In those cases, the SSA renamer creates an SSA name - for this variable with an empty defining statement. */ - hash_table *default_defs; - - /* True if there are any symbols that need to be renamed. */ - unsigned int ssa_renaming_needed : 1; - - /* True if all virtual operands need to be renamed. */ - unsigned int rename_vops : 1; - - /* True if the code is in ssa form. */ - unsigned int in_ssa_p : 1; - - /* True if IPA points-to information was computed for this function. */ - unsigned int ipa_pta : 1; - - struct ssa_operands ssa_operands; - - /* Map gimple stmt to tree label (or list of labels) for transaction - restart and abort. */ - hash_table *tm_restart; -}; - - -/* Return true when gimple SSA form was built. - gimple_in_ssa_p is queried by gimplifier in various early stages before SSA - infrastructure is initialized. Check for presence of the datastructures - at first place. */ -static inline bool -gimple_in_ssa_p (const struct function *fun) -{ - return fun && fun->gimple_df && fun->gimple_df->in_ssa_p; -} - -/* Artificial variable used for the virtual operand FUD chain. */ -static inline tree -gimple_vop (const struct function *fun) -{ - gcc_checking_assert (fun && fun->gimple_df); - return fun->gimple_df->vop; -} - -/* Return the set of VUSE operand for statement G. */ - -static inline use_operand_p -gimple_vuse_op (const_gimple g) -{ - struct use_optype_d *ops; - const gimple_statement_with_memory_ops *mem_ops_stmt = - dyn_cast (g); - if (!mem_ops_stmt) - return NULL_USE_OPERAND_P; - ops = mem_ops_stmt->use_ops; - if (ops - && USE_OP_PTR (ops)->use == &mem_ops_stmt->vuse) - return USE_OP_PTR (ops); - return NULL_USE_OPERAND_P; -} - -/* Return the set of VDEF operand for statement G. */ - -static inline def_operand_p -gimple_vdef_op (gimple g) -{ - gimple_statement_with_memory_ops *mem_ops_stmt = - dyn_cast (g); - if (!mem_ops_stmt) - return NULL_DEF_OPERAND_P; - if (mem_ops_stmt->vdef) - return &mem_ops_stmt->vdef; - return NULL_DEF_OPERAND_P; -} - -/* Mark statement S as modified, and update it. */ - -static inline void -update_stmt (gimple s) -{ - if (gimple_has_ops (s)) - { - gimple_set_modified (s, true); - update_stmt_operands (cfun, s); - } -} - -/* Update statement S if it has been optimized. */ - -static inline void -update_stmt_if_modified (gimple s) -{ - if (gimple_modified_p (s)) - update_stmt_operands (cfun, s); -} - -/* Mark statement S as modified, and update it. */ - -static inline void -update_stmt_fn (struct function *fn, gimple s) -{ - if (gimple_has_ops (s)) - { - gimple_set_modified (s, true); - update_stmt_operands (fn, s); - } -} - - -#endif /* GCC_GIMPLE_SSA_H */ diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/gimple-streamer.h b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/gimple-streamer.h deleted file mode 100644 index 440bce7..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/gimple-streamer.h +++ /dev/null @@ -1,42 +0,0 @@ -/* Data structures and functions for streaming GIMPLE. - - Copyright (C) 2011-2015 Free Software Foundation, Inc. - Contributed by Diego Novillo - -This file is part of GCC. - -GCC is free software; you can redistribute it and/or modify it under -the terms of the GNU General Public License as published by the Free -Software Foundation; either version 3, or (at your option) any later -version. - -GCC is distributed in the hope that it will be useful, but WITHOUT ANY -WARRANTY; without even the implied warranty of MERCHANTABILITY or -FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -for more details. - -You should have received a copy of the GNU General Public License -along with GCC; see the file COPYING3. If not see -. */ - -#ifndef GCC_GIMPLE_STREAMER_H -#define GCC_GIMPLE_STREAMER_H - -#include "hashtab.h" -#include "hash-set.h" -#include "vec.h" -#include "machmode.h" -#include "tm.h" -#include "hard-reg-set.h" -#include "input.h" -#include "function.h" -#include "lto-streamer.h" - -/* In gimple-streamer-in.c */ -void input_bb (struct lto_input_block *, enum LTO_tags, struct data_in *, - struct function *, int); - -/* In gimple-streamer-out.c */ -void output_bb (struct output_block *, basic_block, struct function *); - -#endif /* GCC_GIMPLE_STREAMER_H */ diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/gimple-walk.h b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/gimple-walk.h deleted file mode 100644 index d6151aa..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/gimple-walk.h +++ /dev/null @@ -1,100 +0,0 @@ -/* Header file for gimple statement walk support. - Copyright (C) 2013-2015 Free Software Foundation, Inc. - -This file is part of GCC. - -GCC is free software; you can redistribute it and/or modify it under -the terms of the GNU General Public License as published by the Free -Software Foundation; either version 3, or (at your option) any later -version. - -GCC is distributed in the hope that it will be useful, but WITHOUT ANY -WARRANTY; without even the implied warranty of MERCHANTABILITY or -FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License - for more details. - -You should have received a copy of the GNU General Public License -along with GCC; see the file COPYING3. If not see -. */ - -#ifndef GCC_GIMPLE_WALK_H -#define GCC_GIMPLE_WALK_H - -/* Convenience routines to walk all statements of a gimple function. - Note that this is useful exclusively before the code is converted - into SSA form. Once the program is in SSA form, the standard - operand interface should be used to analyze/modify statements. */ -struct walk_stmt_info -{ - /* Points to the current statement being walked. */ - gimple_stmt_iterator gsi; - - /* Additional data that the callback functions may want to carry - through the recursion. */ - void *info; - - /* Pointer map used to mark visited tree nodes when calling - walk_tree on each operand. If set to NULL, duplicate tree nodes - will be visited more than once. */ - hash_set *pset; - - /* Operand returned by the callbacks. This is set when calling - walk_gimple_seq. If the walk_stmt_fn or walk_tree_fn callback - returns non-NULL, this field will contain the tree returned by - the last callback. */ - tree callback_result; - - /* Indicates whether the operand being examined may be replaced - with something that matches is_gimple_val (if true) or something - slightly more complicated (if false). "Something" technically - means the common subset of is_gimple_lvalue and is_gimple_rhs, - but we never try to form anything more complicated than that, so - we don't bother checking. - - Also note that CALLBACK should update this flag while walking the - sub-expressions of a statement. For instance, when walking the - statement 'foo (&var)', the flag VAL_ONLY will initially be set - to true, however, when walking &var, the operand of that - ADDR_EXPR does not need to be a GIMPLE value. */ - BOOL_BITFIELD val_only : 1; - - /* True if we are currently walking the LHS of an assignment. */ - BOOL_BITFIELD is_lhs : 1; - - /* Optional. Set to true by the callback functions if they made any - changes. */ - BOOL_BITFIELD changed : 1; - - /* True if we're interested in location information. */ - BOOL_BITFIELD want_locations : 1; - - /* True if we've removed the statement that was processed. */ - BOOL_BITFIELD removed_stmt : 1; -}; - -/* Callback for walk_gimple_stmt. Called for every statement found - during traversal. The first argument points to the statement to - walk. The second argument is a flag that the callback sets to - 'true' if it the callback handled all the operands and - sub-statements of the statement (the default value of this flag is - 'false'). The third argument is an anonymous pointer to data - to be used by the callback. */ -typedef tree (*walk_stmt_fn) (gimple_stmt_iterator *, bool *, - struct walk_stmt_info *); - -extern gimple walk_gimple_seq_mod (gimple_seq *, walk_stmt_fn, walk_tree_fn, - struct walk_stmt_info *); -extern gimple walk_gimple_seq (gimple_seq, walk_stmt_fn, walk_tree_fn, - struct walk_stmt_info *); -extern tree walk_gimple_op (gimple, walk_tree_fn, struct walk_stmt_info *); -extern tree walk_gimple_stmt (gimple_stmt_iterator *, walk_stmt_fn, - walk_tree_fn, struct walk_stmt_info *); -typedef bool (*walk_stmt_load_store_addr_fn) (gimple, tree, tree, void *); -extern bool walk_stmt_load_store_addr_ops (gimple, void *, - walk_stmt_load_store_addr_fn, - walk_stmt_load_store_addr_fn, - walk_stmt_load_store_addr_fn); -extern bool walk_stmt_load_store_ops (gimple, void *, - walk_stmt_load_store_addr_fn, - walk_stmt_load_store_addr_fn); -#endif /* GCC_GIMPLE_WALK_H */ diff --git a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/gimple.def b/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/gimple.def deleted file mode 100644 index 96602df..0000000 --- a/arduino/hardware/tools/avr/lib/gcc/avr/5.4.0/plugin/include/gimple.def +++ /dev/null @@ -1,390 +0,0 @@ -/* This file contains the definitions of the GIMPLE IR tuples used in GCC. - - Copyright (C) 2007-2015 Free Software Foundation, Inc. - Contributed by Aldy Hernandez - -This file is part of GCC. - -GCC is free software; you can redistribute it and/or modify it under -the terms of the GNU General Public License as published by the Free -Software Foundation; either version 3, or (at your option) any later -version. - -GCC is distributed in the hope that it will be useful, but WITHOUT ANY -WARRANTY; without even the implied warranty of MERCHANTABILITY or -FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -for more details. - -You should have received a copy of the GNU General Public License -along with GCC; see the file COPYING3. If not see -. */ - -/* The format of this file is - DEFGSCODE(GIMPLE_symbol, printable name, GSS_symbol). */ - - -/* Error marker. This is used in similar ways as ERROR_MARK in tree.def. */ -DEFGSCODE(GIMPLE_ERROR_MARK, "gimple_error_mark", GSS_BASE) - -/* IMPORTANT. Do not rearrange the codes between GIMPLE_COND and - GIMPLE_RETURN. The ordering is exposed by gimple_has_ops calls. - These are all the GIMPLE statements with register operands. */ - -/* GIMPLE_COND - represents the conditional jump: - - if (OP1 COND_CODE OP2) goto TRUE_LABEL else goto FALSE_LABEL - - COND_CODE is the tree code used as the comparison predicate. It - must be of class tcc_comparison. - - OP1 and OP2 are the operands used in the comparison. They must be - accepted by is_gimple_operand. - - TRUE_LABEL and FALSE_LABEL are the LABEL_DECL nodes used as the - jump target for the comparison. */ -DEFGSCODE(GIMPLE_COND, "gimple_cond", GSS_WITH_OPS) - -/* GIMPLE_DEBUG represents a debug statement. */ -DEFGSCODE(GIMPLE_DEBUG, "gimple_debug", GSS_WITH_OPS) - -/* GIMPLE_GOTO represents unconditional jumps. - TARGET is a LABEL_DECL or an expression node for computed GOTOs. */ -DEFGSCODE(GIMPLE_GOTO, "gimple_goto", GSS_WITH_OPS) - -/* GIMPLE_LABEL